From b85281b9fc822ea2428327d3bd1f6f00049ff491 Mon Sep 17 00:00:00 2001 From: Luke Kenneth Casson Leighton Date: Sat, 19 Sep 2020 13:23:34 +0000 Subject: [PATCH] first attempt putting in litex pins instead of bare core --- experiments9/Makefile | 18 +- experiments9/cells.lst | 1 + experiments9/doDesign.py | 2 +- experiments9/non_generated/ls180.il | 381473 +++++++++++++++++++ experiments9/non_generated/test_issuer.il | 278106 -------------- 5 files changed, 381484 insertions(+), 278116 deletions(-) create mode 100644 experiments9/non_generated/ls180.il delete mode 100644 experiments9/non_generated/test_issuer.il diff --git a/experiments9/Makefile b/experiments9/Makefile index 5429920..fb09980 100755 --- a/experiments9/Makefile +++ b/experiments9/Makefile @@ -10,20 +10,20 @@ VST_FLAGS = --vst-use-concat NETLISTS = $(shell cat cells.lst) - YOSYS_FLATTEN = $(shell cat flatten.lst) +# YOSYS_FLATTEN = $(shell cat flatten.lst) include ./mk/design-flow.mk -blif: test_issuer.blif -vst: test_issuer.vst +blif: ls180.blif +vst: ls180.vst -layout: test_issuer_r.ap -gds: test_issuer_r.gds +layout: ls180_r.ap +gds: ls180_r.gds -lvx: lvx-test_issuer_r -druc: druc-test_issuer_r -view: cgt-test_issuer_r -viewn: cgt-test_issuer +lvx: lvx-ls180_r +druc: druc-ls180_r +view: cgt-ls180_r +viewn: cgt-ls180 diff --git a/experiments9/cells.lst b/experiments9/cells.lst index f0f6b36..de39d12 100644 --- a/experiments9/cells.lst +++ b/experiments9/cells.lst @@ -1,3 +1,4 @@ +ls180 test_issuer adr_l adrok_l diff --git a/experiments9/doDesign.py b/experiments9/doDesign.py index 8a89103..cedcf3e 100644 --- a/experiments9/doDesign.py +++ b/experiments9/doDesign.py @@ -582,7 +582,7 @@ def scriptMain ( **kw ): blockInt.state.useSpares = False #rvalue = blockInt.build() - issuer = af.getCell( 'test_issuer' , CRL.Catalog.State.Logical ) + issuer = af.getCell( 'ls180' , CRL.Catalog.State.Logical ) blockIssuer = Block.create \ ( issuer , ioPins=[] diff --git a/experiments9/non_generated/ls180.il b/experiments9/non_generated/ls180.il new file mode 100644 index 0000000..d1229d1 --- /dev/null +++ b/experiments9/non_generated/ls180.il @@ -0,0 +1,381473 @@ +# Generated by Yosys 0.9+2406 (git sha1 f7fdd99e, clang 3.8.1-24 -fPIC -Os) +autoidx 13726 +attribute \src "issuer_ls180.v:5.1-330.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.dec_ALU.dec.ALU_dec19" +attribute \generator "nMigen" +module \ALU_dec19 + attribute \src "issuer_ls180.v:279.3-288.6" + wire width 3 $0\ALU_dec19_cr_in[2:0] + attribute \src "issuer_ls180.v:289.3-298.6" + wire width 3 $0\ALU_dec19_cr_out[2:0] + attribute \src "issuer_ls180.v:319.3-328.6" + wire width 2 $0\ALU_dec19_cry_in[1:0] + attribute \src "issuer_ls180.v:219.3-228.6" + wire $0\ALU_dec19_cry_out[0:0] + attribute \src "issuer_ls180.v:189.3-198.6" + wire width 12 $0\ALU_dec19_function_unit[11:0] + attribute \src "issuer_ls180.v:259.3-268.6" + wire width 3 $0\ALU_dec19_in1_sel[2:0] + attribute \src "issuer_ls180.v:269.3-278.6" + wire width 4 $0\ALU_dec19_in2_sel[3:0] + attribute \src "issuer_ls180.v:249.3-258.6" + wire width 7 $0\ALU_dec19_internal_op[6:0] + attribute \src "issuer_ls180.v:199.3-208.6" + wire $0\ALU_dec19_inv_a[0:0] + attribute \src "issuer_ls180.v:209.3-218.6" + wire $0\ALU_dec19_inv_out[0:0] + attribute \src "issuer_ls180.v:229.3-238.6" + wire $0\ALU_dec19_is_32b[0:0] + attribute \src "issuer_ls180.v:299.3-308.6" + wire width 4 $0\ALU_dec19_ldst_len[3:0] + attribute \src "issuer_ls180.v:309.3-318.6" + wire width 2 $0\ALU_dec19_rc_sel[1:0] + attribute \src "issuer_ls180.v:239.3-248.6" + wire $0\ALU_dec19_sgn[0:0] + attribute \src "issuer_ls180.v:6.7-6.20" + wire $0\initial[0:0] + attribute \src "issuer_ls180.v:279.3-288.6" + wire width 3 $1\ALU_dec19_cr_in[2:0] + attribute \src "issuer_ls180.v:289.3-298.6" + wire width 3 $1\ALU_dec19_cr_out[2:0] + attribute \src "issuer_ls180.v:319.3-328.6" + wire width 2 $1\ALU_dec19_cry_in[1:0] + attribute \src "issuer_ls180.v:219.3-228.6" + wire $1\ALU_dec19_cry_out[0:0] + attribute \src "issuer_ls180.v:189.3-198.6" + wire width 12 $1\ALU_dec19_function_unit[11:0] + attribute \src "issuer_ls180.v:259.3-268.6" + wire width 3 $1\ALU_dec19_in1_sel[2:0] + attribute \src "issuer_ls180.v:269.3-278.6" + wire width 4 $1\ALU_dec19_in2_sel[3:0] + attribute \src "issuer_ls180.v:249.3-258.6" + wire width 7 $1\ALU_dec19_internal_op[6:0] + attribute \src "issuer_ls180.v:199.3-208.6" + wire $1\ALU_dec19_inv_a[0:0] + attribute \src "issuer_ls180.v:209.3-218.6" + wire $1\ALU_dec19_inv_out[0:0] + attribute \src "issuer_ls180.v:229.3-238.6" + wire $1\ALU_dec19_is_32b[0:0] + attribute \src "issuer_ls180.v:299.3-308.6" + wire width 4 $1\ALU_dec19_ldst_len[3:0] + attribute \src "issuer_ls180.v:309.3-318.6" + wire width 2 $1\ALU_dec19_rc_sel[1:0] + attribute \src "issuer_ls180.v:239.3-248.6" + wire $1\ALU_dec19_sgn[0:0] + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 5 \ALU_dec19_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 6 \ALU_dec19_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 9 \ALU_dec19_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 12 \ALU_dec19_cry_out + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 12 output 1 \ALU_dec19_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 3 \ALU_dec19_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 output 4 \ALU_dec19_in2_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 7 output 2 \ALU_dec19_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 10 \ALU_dec19_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 11 \ALU_dec19_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 13 \ALU_dec19_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 output 7 \ALU_dec19_ldst_len + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 8 \ALU_dec19_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 14 \ALU_dec19_sgn + attribute \src "issuer_ls180.v:6.7-6.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + wire width 32 input 15 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:320" + wire width 10 \opcode_switch + attribute \src "issuer_ls180.v:189.3-198.6" + process $proc$issuer_ls180.v:189$1 + assign { } { } + assign { } { } + assign $0\ALU_dec19_function_unit[11:0] $1\ALU_dec19_function_unit[11:0] + attribute \src "issuer_ls180.v:190.5-190.29" + switch \initial + attribute \src "issuer_ls180.v:190.9-190.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0010010110 + assign { } { } + assign $1\ALU_dec19_function_unit[11:0] 12'000000000010 + case + assign $1\ALU_dec19_function_unit[11:0] 12'000000000000 + end + sync always + update \ALU_dec19_function_unit $0\ALU_dec19_function_unit[11:0] + end + attribute \src "issuer_ls180.v:199.3-208.6" + process $proc$issuer_ls180.v:199$2 + assign { } { } + assign { } { } + assign $0\ALU_dec19_inv_a[0:0] $1\ALU_dec19_inv_a[0:0] + attribute \src "issuer_ls180.v:200.5-200.29" + switch \initial + attribute \src "issuer_ls180.v:200.9-200.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0010010110 + assign { } { } + assign $1\ALU_dec19_inv_a[0:0] 1'0 + case + assign $1\ALU_dec19_inv_a[0:0] 1'0 + end + sync always + update \ALU_dec19_inv_a $0\ALU_dec19_inv_a[0:0] + end + attribute \src "issuer_ls180.v:209.3-218.6" + process $proc$issuer_ls180.v:209$3 + assign { } { } + assign { } { } + assign $0\ALU_dec19_inv_out[0:0] $1\ALU_dec19_inv_out[0:0] + attribute \src "issuer_ls180.v:210.5-210.29" + switch \initial + attribute \src "issuer_ls180.v:210.9-210.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0010010110 + assign { } { } + assign $1\ALU_dec19_inv_out[0:0] 1'0 + case + assign $1\ALU_dec19_inv_out[0:0] 1'0 + end + sync always + update \ALU_dec19_inv_out $0\ALU_dec19_inv_out[0:0] + end + attribute \src "issuer_ls180.v:219.3-228.6" + process $proc$issuer_ls180.v:219$4 + assign { } { } + assign { } { } + assign $0\ALU_dec19_cry_out[0:0] $1\ALU_dec19_cry_out[0:0] + attribute \src "issuer_ls180.v:220.5-220.29" + switch \initial + attribute \src "issuer_ls180.v:220.9-220.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0010010110 + assign { } { } + assign $1\ALU_dec19_cry_out[0:0] 1'0 + case + assign $1\ALU_dec19_cry_out[0:0] 1'0 + end + sync always + update \ALU_dec19_cry_out $0\ALU_dec19_cry_out[0:0] + end + attribute \src "issuer_ls180.v:229.3-238.6" + process $proc$issuer_ls180.v:229$5 + assign { } { } + assign { } { } + assign $0\ALU_dec19_is_32b[0:0] $1\ALU_dec19_is_32b[0:0] + attribute \src "issuer_ls180.v:230.5-230.29" + switch \initial + attribute \src "issuer_ls180.v:230.9-230.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0010010110 + assign { } { } + assign $1\ALU_dec19_is_32b[0:0] 1'0 + case + assign $1\ALU_dec19_is_32b[0:0] 1'0 + end + sync always + update \ALU_dec19_is_32b $0\ALU_dec19_is_32b[0:0] + end + attribute \src "issuer_ls180.v:239.3-248.6" + process $proc$issuer_ls180.v:239$6 + assign { } { } + assign { } { } + assign $0\ALU_dec19_sgn[0:0] $1\ALU_dec19_sgn[0:0] + attribute \src "issuer_ls180.v:240.5-240.29" + switch \initial + attribute \src "issuer_ls180.v:240.9-240.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0010010110 + assign { } { } + assign $1\ALU_dec19_sgn[0:0] 1'0 + case + assign $1\ALU_dec19_sgn[0:0] 1'0 + end + sync always + update \ALU_dec19_sgn $0\ALU_dec19_sgn[0:0] + end + attribute \src "issuer_ls180.v:249.3-258.6" + process $proc$issuer_ls180.v:249$7 + assign { } { } + assign { } { } + assign $0\ALU_dec19_internal_op[6:0] $1\ALU_dec19_internal_op[6:0] + attribute \src "issuer_ls180.v:250.5-250.29" + switch \initial + attribute \src "issuer_ls180.v:250.9-250.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0010010110 + assign { } { } + assign $1\ALU_dec19_internal_op[6:0] 7'0100100 + case + assign $1\ALU_dec19_internal_op[6:0] 7'0000000 + end + sync always + update \ALU_dec19_internal_op $0\ALU_dec19_internal_op[6:0] + end + attribute \src "issuer_ls180.v:259.3-268.6" + process $proc$issuer_ls180.v:259$8 + assign { } { } + assign { } { } + assign $0\ALU_dec19_in1_sel[2:0] $1\ALU_dec19_in1_sel[2:0] + attribute \src "issuer_ls180.v:260.5-260.29" + switch \initial + attribute \src "issuer_ls180.v:260.9-260.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0010010110 + assign { } { } + assign $1\ALU_dec19_in1_sel[2:0] 3'000 + case + assign $1\ALU_dec19_in1_sel[2:0] 3'000 + end + sync always + update \ALU_dec19_in1_sel $0\ALU_dec19_in1_sel[2:0] + end + attribute \src "issuer_ls180.v:269.3-278.6" + process $proc$issuer_ls180.v:269$9 + assign { } { } + assign { } { } + assign $0\ALU_dec19_in2_sel[3:0] $1\ALU_dec19_in2_sel[3:0] + attribute \src "issuer_ls180.v:270.5-270.29" + switch \initial + attribute \src "issuer_ls180.v:270.9-270.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0010010110 + assign { } { } + assign $1\ALU_dec19_in2_sel[3:0] 4'0000 + case + assign $1\ALU_dec19_in2_sel[3:0] 4'0000 + end + sync always + update \ALU_dec19_in2_sel $0\ALU_dec19_in2_sel[3:0] + end + attribute \src "issuer_ls180.v:279.3-288.6" + process $proc$issuer_ls180.v:279$10 + assign { } { } + assign { } { } + assign $0\ALU_dec19_cr_in[2:0] $1\ALU_dec19_cr_in[2:0] + attribute \src "issuer_ls180.v:280.5-280.29" + switch \initial + attribute \src "issuer_ls180.v:280.9-280.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0010010110 + assign { } { } + assign $1\ALU_dec19_cr_in[2:0] 3'000 + case + assign $1\ALU_dec19_cr_in[2:0] 3'000 + end + sync always + update \ALU_dec19_cr_in $0\ALU_dec19_cr_in[2:0] + end + attribute \src "issuer_ls180.v:289.3-298.6" + process $proc$issuer_ls180.v:289$11 + assign { } { } + assign { } { } + assign $0\ALU_dec19_cr_out[2:0] $1\ALU_dec19_cr_out[2:0] + attribute \src "issuer_ls180.v:290.5-290.29" + switch \initial + attribute \src "issuer_ls180.v:290.9-290.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0010010110 + assign { } { } + assign $1\ALU_dec19_cr_out[2:0] 3'000 + case + assign $1\ALU_dec19_cr_out[2:0] 3'000 + end + sync always + update \ALU_dec19_cr_out $0\ALU_dec19_cr_out[2:0] + end + attribute \src "issuer_ls180.v:299.3-308.6" + process $proc$issuer_ls180.v:299$12 + assign { } { } + assign { } { } + assign $0\ALU_dec19_ldst_len[3:0] $1\ALU_dec19_ldst_len[3:0] + attribute \src "issuer_ls180.v:300.5-300.29" + switch \initial + attribute \src "issuer_ls180.v:300.9-300.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0010010110 + assign { } { } + assign $1\ALU_dec19_ldst_len[3:0] 4'0000 + case + assign $1\ALU_dec19_ldst_len[3:0] 4'0000 + end + sync always + update \ALU_dec19_ldst_len $0\ALU_dec19_ldst_len[3:0] + end + attribute \src "issuer_ls180.v:309.3-318.6" + process $proc$issuer_ls180.v:309$13 + assign { } { } + assign { } { } + assign $0\ALU_dec19_rc_sel[1:0] $1\ALU_dec19_rc_sel[1:0] + attribute \src "issuer_ls180.v:310.5-310.29" + switch \initial + attribute \src "issuer_ls180.v:310.9-310.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0010010110 + assign { } { } + assign $1\ALU_dec19_rc_sel[1:0] 2'00 + case + assign $1\ALU_dec19_rc_sel[1:0] 2'00 + end + sync always + update \ALU_dec19_rc_sel $0\ALU_dec19_rc_sel[1:0] + end + attribute \src "issuer_ls180.v:319.3-328.6" + process $proc$issuer_ls180.v:319$14 + assign { } { } + assign { } { } + assign $0\ALU_dec19_cry_in[1:0] $1\ALU_dec19_cry_in[1:0] + attribute \src "issuer_ls180.v:320.5-320.29" + switch \initial + attribute \src "issuer_ls180.v:320.9-320.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0010010110 + assign { } { } + assign $1\ALU_dec19_cry_in[1:0] 2'00 + case + assign $1\ALU_dec19_cry_in[1:0] 2'00 + end + sync always + update \ALU_dec19_cry_in $0\ALU_dec19_cry_in[1:0] + end + attribute \src "issuer_ls180.v:6.7-6.20" + process $proc$issuer_ls180.v:6$15 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + connect \opcode_switch \opcode_in [10:1] +end +attribute \src "issuer_ls180.v:334.1-1750.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.dec_ALU.dec.ALU_dec31" +attribute \generator "nMigen" +module \ALU_dec31 + attribute \src "issuer_ls180.v:1457.3-1478.6" + wire width 3 $0\ALU_dec31_cr_in[2:0] + attribute \src "issuer_ls180.v:1479.3-1500.6" + wire width 3 $0\ALU_dec31_cr_out[2:0] + attribute \src "issuer_ls180.v:1545.3-1566.6" + wire width 2 $0\ALU_dec31_cry_in[1:0] + attribute \src "issuer_ls180.v:1611.3-1632.6" + wire $0\ALU_dec31_cry_out[0:0] + attribute \src "issuer_ls180.v:1677.3-1698.6" + wire width 12 $0\ALU_dec31_function_unit[11:0] + attribute \src "issuer_ls180.v:1721.3-1742.6" + wire width 3 $0\ALU_dec31_in1_sel[2:0] + attribute \src "issuer_ls180.v:1435.3-1456.6" + wire width 4 $0\ALU_dec31_in2_sel[3:0] + attribute \src "issuer_ls180.v:1699.3-1720.6" + wire width 7 $0\ALU_dec31_internal_op[6:0] + attribute \src "issuer_ls180.v:1567.3-1588.6" + wire $0\ALU_dec31_inv_a[0:0] + attribute \src "issuer_ls180.v:1589.3-1610.6" + wire $0\ALU_dec31_inv_out[0:0] + attribute \src "issuer_ls180.v:1633.3-1654.6" + wire $0\ALU_dec31_is_32b[0:0] + attribute \src "issuer_ls180.v:1501.3-1522.6" + wire width 4 $0\ALU_dec31_ldst_len[3:0] + attribute \src "issuer_ls180.v:1523.3-1544.6" + wire width 2 $0\ALU_dec31_rc_sel[1:0] + attribute \src "issuer_ls180.v:1655.3-1676.6" + wire $0\ALU_dec31_sgn[0:0] + attribute \src "issuer_ls180.v:335.7-335.20" + wire $0\initial[0:0] + attribute \src "issuer_ls180.v:1457.3-1478.6" + wire width 3 $1\ALU_dec31_cr_in[2:0] + attribute \src "issuer_ls180.v:1479.3-1500.6" + wire width 3 $1\ALU_dec31_cr_out[2:0] + attribute \src "issuer_ls180.v:1545.3-1566.6" + wire width 2 $1\ALU_dec31_cry_in[1:0] + attribute \src "issuer_ls180.v:1611.3-1632.6" + wire $1\ALU_dec31_cry_out[0:0] + attribute \src "issuer_ls180.v:1677.3-1698.6" + wire width 12 $1\ALU_dec31_function_unit[11:0] + attribute \src "issuer_ls180.v:1721.3-1742.6" + wire width 3 $1\ALU_dec31_in1_sel[2:0] + attribute \src "issuer_ls180.v:1435.3-1456.6" + wire width 4 $1\ALU_dec31_in2_sel[3:0] + attribute \src "issuer_ls180.v:1699.3-1720.6" + wire width 7 $1\ALU_dec31_internal_op[6:0] + attribute \src "issuer_ls180.v:1567.3-1588.6" + wire $1\ALU_dec31_inv_a[0:0] + attribute \src "issuer_ls180.v:1589.3-1610.6" + wire $1\ALU_dec31_inv_out[0:0] + attribute \src "issuer_ls180.v:1633.3-1654.6" + wire $1\ALU_dec31_is_32b[0:0] + attribute \src "issuer_ls180.v:1501.3-1522.6" + wire width 4 $1\ALU_dec31_ldst_len[3:0] + attribute \src "issuer_ls180.v:1523.3-1544.6" + wire width 2 $1\ALU_dec31_rc_sel[1:0] + attribute \src "issuer_ls180.v:1655.3-1676.6" + wire $1\ALU_dec31_sgn[0:0] + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 5 \ALU_dec31_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 6 \ALU_dec31_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 9 \ALU_dec31_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 12 \ALU_dec31_cry_out + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 \ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 \ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_cry_out + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 12 \ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 \ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 \ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_in2_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 7 \ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 \ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_ldst_len + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + wire width 32 \ALU_dec31_dec_sub0_opcode_in + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 \ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 \ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_cry_out + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 12 \ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 \ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 \ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_in2_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 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"/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 \ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_ldst_len + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + wire width 32 \ALU_dec31_dec_sub26_opcode_in + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 \ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 \ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_cry_out + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 12 \ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 \ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 \ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_in2_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 7 \ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 \ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_ldst_len + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + wire width 32 \ALU_dec31_dec_sub8_opcode_in + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 12 output 1 \ALU_dec31_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 3 \ALU_dec31_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 output 4 \ALU_dec31_in2_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 7 output 2 \ALU_dec31_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 10 \ALU_dec31_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 11 \ALU_dec31_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 13 \ALU_dec31_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 output 7 \ALU_dec31_ldst_len + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 8 \ALU_dec31_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 14 \ALU_dec31_sgn + attribute \src "issuer_ls180.v:335.7-335.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:326" + wire width 5 \opc_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + wire width 32 input 15 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:320" + wire width 10 \opcode_switch + attribute \module_not_derived 1 + attribute \src "issuer_ls180.v:1350.22-1366.4" + cell \ALU_dec31_dec_sub0 \ALU_dec31_dec_sub0 + connect \ALU_dec31_dec_sub0_cr_in \ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_cr_in + connect \ALU_dec31_dec_sub0_cr_out \ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_cr_out + connect \ALU_dec31_dec_sub0_cry_in \ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_cry_in + connect \ALU_dec31_dec_sub0_cry_out \ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_cry_out + connect \ALU_dec31_dec_sub0_function_unit \ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_function_unit + connect \ALU_dec31_dec_sub0_in1_sel \ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_in1_sel + connect \ALU_dec31_dec_sub0_in2_sel \ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_in2_sel + connect \ALU_dec31_dec_sub0_internal_op \ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_internal_op + connect \ALU_dec31_dec_sub0_inv_a \ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_inv_a + connect \ALU_dec31_dec_sub0_inv_out \ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_inv_out + connect \ALU_dec31_dec_sub0_is_32b \ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_is_32b + connect \ALU_dec31_dec_sub0_ldst_len \ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_ldst_len + connect \ALU_dec31_dec_sub0_rc_sel \ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_rc_sel + connect \ALU_dec31_dec_sub0_sgn \ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_sgn + connect \opcode_in \ALU_dec31_dec_sub0_opcode_in + end + attribute \module_not_derived 1 + attribute \src "issuer_ls180.v:1367.23-1383.4" + cell \ALU_dec31_dec_sub10 \ALU_dec31_dec_sub10 + connect \ALU_dec31_dec_sub10_cr_in \ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_cr_in + connect \ALU_dec31_dec_sub10_cr_out \ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_cr_out + connect \ALU_dec31_dec_sub10_cry_in \ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_cry_in + connect \ALU_dec31_dec_sub10_cry_out \ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_cry_out + connect \ALU_dec31_dec_sub10_function_unit \ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_function_unit + connect \ALU_dec31_dec_sub10_in1_sel \ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_in1_sel + connect \ALU_dec31_dec_sub10_in2_sel \ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_in2_sel + connect \ALU_dec31_dec_sub10_internal_op \ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_internal_op + connect \ALU_dec31_dec_sub10_inv_a \ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_inv_a + connect \ALU_dec31_dec_sub10_inv_out \ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_inv_out + connect \ALU_dec31_dec_sub10_is_32b \ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_is_32b + connect \ALU_dec31_dec_sub10_ldst_len \ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_ldst_len + connect \ALU_dec31_dec_sub10_rc_sel \ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_rc_sel + connect \ALU_dec31_dec_sub10_sgn \ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_sgn + connect \opcode_in \ALU_dec31_dec_sub10_opcode_in + end + attribute \module_not_derived 1 + attribute \src "issuer_ls180.v:1384.23-1400.4" + cell \ALU_dec31_dec_sub22 \ALU_dec31_dec_sub22 + connect \ALU_dec31_dec_sub22_cr_in \ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_cr_in + connect \ALU_dec31_dec_sub22_cr_out \ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_cr_out + connect \ALU_dec31_dec_sub22_cry_in \ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_cry_in + connect \ALU_dec31_dec_sub22_cry_out \ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_cry_out + connect \ALU_dec31_dec_sub22_function_unit \ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_function_unit + connect \ALU_dec31_dec_sub22_in1_sel \ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_in1_sel + connect \ALU_dec31_dec_sub22_in2_sel \ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_in2_sel + connect \ALU_dec31_dec_sub22_internal_op \ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_internal_op + connect \ALU_dec31_dec_sub22_inv_a \ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_inv_a + connect \ALU_dec31_dec_sub22_inv_out \ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_inv_out + connect \ALU_dec31_dec_sub22_is_32b \ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_is_32b + connect \ALU_dec31_dec_sub22_ldst_len \ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_ldst_len + connect \ALU_dec31_dec_sub22_rc_sel \ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_rc_sel + connect \ALU_dec31_dec_sub22_sgn \ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_sgn + connect \opcode_in \ALU_dec31_dec_sub22_opcode_in + end + attribute \module_not_derived 1 + attribute \src "issuer_ls180.v:1401.23-1417.4" + cell \ALU_dec31_dec_sub26 \ALU_dec31_dec_sub26 + connect \ALU_dec31_dec_sub26_cr_in \ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_cr_in + connect \ALU_dec31_dec_sub26_cr_out \ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_cr_out + connect \ALU_dec31_dec_sub26_cry_in \ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_cry_in + connect \ALU_dec31_dec_sub26_cry_out \ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_cry_out + connect \ALU_dec31_dec_sub26_function_unit \ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_function_unit + connect \ALU_dec31_dec_sub26_in1_sel \ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_in1_sel + connect \ALU_dec31_dec_sub26_in2_sel \ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_in2_sel + connect \ALU_dec31_dec_sub26_internal_op \ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_internal_op + connect \ALU_dec31_dec_sub26_inv_a \ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_inv_a + connect \ALU_dec31_dec_sub26_inv_out \ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_inv_out + connect \ALU_dec31_dec_sub26_is_32b \ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_is_32b + connect \ALU_dec31_dec_sub26_ldst_len \ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_ldst_len + connect \ALU_dec31_dec_sub26_rc_sel \ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_rc_sel + connect \ALU_dec31_dec_sub26_sgn \ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_sgn + connect \opcode_in \ALU_dec31_dec_sub26_opcode_in + end + attribute \module_not_derived 1 + attribute \src "issuer_ls180.v:1418.22-1434.4" + cell \ALU_dec31_dec_sub8 \ALU_dec31_dec_sub8 + connect \ALU_dec31_dec_sub8_cr_in \ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_cr_in + connect \ALU_dec31_dec_sub8_cr_out \ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_cr_out + connect \ALU_dec31_dec_sub8_cry_in \ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_cry_in + connect \ALU_dec31_dec_sub8_cry_out \ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_cry_out + connect \ALU_dec31_dec_sub8_function_unit \ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_function_unit + connect \ALU_dec31_dec_sub8_in1_sel \ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_in1_sel + connect \ALU_dec31_dec_sub8_in2_sel \ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_in2_sel + connect \ALU_dec31_dec_sub8_internal_op \ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_internal_op + connect \ALU_dec31_dec_sub8_inv_a \ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_inv_a + connect \ALU_dec31_dec_sub8_inv_out \ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_inv_out + connect \ALU_dec31_dec_sub8_is_32b \ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_is_32b + connect \ALU_dec31_dec_sub8_ldst_len \ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_ldst_len + connect \ALU_dec31_dec_sub8_rc_sel \ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_rc_sel + connect \ALU_dec31_dec_sub8_sgn \ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_sgn + connect \opcode_in \ALU_dec31_dec_sub8_opcode_in + end + attribute \src "issuer_ls180.v:1435.3-1456.6" + process $proc$issuer_ls180.v:1435$16 + assign { } { } + assign { } { } + assign $0\ALU_dec31_in2_sel[3:0] $1\ALU_dec31_in2_sel[3:0] + attribute \src "issuer_ls180.v:1436.5-1436.29" + switch \initial + attribute \src "issuer_ls180.v:1436.9-1436.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opc_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\ALU_dec31_in2_sel[3:0] \ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_in2_sel + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\ALU_dec31_in2_sel[3:0] \ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_in2_sel + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\ALU_dec31_in2_sel[3:0] \ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_in2_sel + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\ALU_dec31_in2_sel[3:0] \ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_in2_sel + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\ALU_dec31_in2_sel[3:0] \ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_in2_sel + case + assign $1\ALU_dec31_in2_sel[3:0] 4'0000 + end + sync always + update \ALU_dec31_in2_sel $0\ALU_dec31_in2_sel[3:0] + end + attribute \src "issuer_ls180.v:1457.3-1478.6" + process $proc$issuer_ls180.v:1457$17 + assign { } { } + assign { } { } + assign $0\ALU_dec31_cr_in[2:0] $1\ALU_dec31_cr_in[2:0] + attribute \src "issuer_ls180.v:1458.5-1458.29" + switch \initial + attribute \src "issuer_ls180.v:1458.9-1458.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opc_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\ALU_dec31_cr_in[2:0] \ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_cr_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\ALU_dec31_cr_in[2:0] \ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_cr_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\ALU_dec31_cr_in[2:0] \ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_cr_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\ALU_dec31_cr_in[2:0] \ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_cr_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\ALU_dec31_cr_in[2:0] \ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_cr_in + case + assign $1\ALU_dec31_cr_in[2:0] 3'000 + end + sync always + update \ALU_dec31_cr_in $0\ALU_dec31_cr_in[2:0] + end + attribute \src "issuer_ls180.v:1479.3-1500.6" + process $proc$issuer_ls180.v:1479$18 + assign { } { } + assign { } { } + assign $0\ALU_dec31_cr_out[2:0] $1\ALU_dec31_cr_out[2:0] + attribute \src "issuer_ls180.v:1480.5-1480.29" + switch \initial + attribute \src "issuer_ls180.v:1480.9-1480.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opc_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\ALU_dec31_cr_out[2:0] \ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_cr_out + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\ALU_dec31_cr_out[2:0] \ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_cr_out + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\ALU_dec31_cr_out[2:0] \ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_cr_out + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\ALU_dec31_cr_out[2:0] \ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_cr_out + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\ALU_dec31_cr_out[2:0] \ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_cr_out + case + assign $1\ALU_dec31_cr_out[2:0] 3'000 + end + sync always + update \ALU_dec31_cr_out $0\ALU_dec31_cr_out[2:0] + end + attribute \src "issuer_ls180.v:1501.3-1522.6" + process $proc$issuer_ls180.v:1501$19 + assign { } { } + assign { } { } + assign $0\ALU_dec31_ldst_len[3:0] $1\ALU_dec31_ldst_len[3:0] + attribute \src "issuer_ls180.v:1502.5-1502.29" + switch \initial + attribute \src "issuer_ls180.v:1502.9-1502.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opc_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\ALU_dec31_ldst_len[3:0] \ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_ldst_len + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\ALU_dec31_ldst_len[3:0] \ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_ldst_len + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\ALU_dec31_ldst_len[3:0] \ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_ldst_len + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\ALU_dec31_ldst_len[3:0] \ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_ldst_len + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\ALU_dec31_ldst_len[3:0] \ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_ldst_len + case + assign $1\ALU_dec31_ldst_len[3:0] 4'0000 + end + sync always + update \ALU_dec31_ldst_len $0\ALU_dec31_ldst_len[3:0] + end + attribute \src "issuer_ls180.v:1523.3-1544.6" + process $proc$issuer_ls180.v:1523$20 + assign { } { } + assign { } { } + assign $0\ALU_dec31_rc_sel[1:0] $1\ALU_dec31_rc_sel[1:0] + attribute \src "issuer_ls180.v:1524.5-1524.29" + switch \initial + attribute \src "issuer_ls180.v:1524.9-1524.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opc_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\ALU_dec31_rc_sel[1:0] \ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_rc_sel + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\ALU_dec31_rc_sel[1:0] \ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_rc_sel + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\ALU_dec31_rc_sel[1:0] \ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_rc_sel + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\ALU_dec31_rc_sel[1:0] \ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_rc_sel + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\ALU_dec31_rc_sel[1:0] \ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_rc_sel + case + assign $1\ALU_dec31_rc_sel[1:0] 2'00 + end + sync always + update \ALU_dec31_rc_sel $0\ALU_dec31_rc_sel[1:0] + end + attribute \src "issuer_ls180.v:1545.3-1566.6" + process $proc$issuer_ls180.v:1545$21 + assign { } { } + assign { } { } + assign $0\ALU_dec31_cry_in[1:0] $1\ALU_dec31_cry_in[1:0] + attribute \src "issuer_ls180.v:1546.5-1546.29" + switch \initial + attribute \src "issuer_ls180.v:1546.9-1546.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opc_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\ALU_dec31_cry_in[1:0] \ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_cry_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\ALU_dec31_cry_in[1:0] \ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_cry_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\ALU_dec31_cry_in[1:0] \ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_cry_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\ALU_dec31_cry_in[1:0] \ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_cry_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\ALU_dec31_cry_in[1:0] \ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_cry_in + case + assign $1\ALU_dec31_cry_in[1:0] 2'00 + end + sync always + update \ALU_dec31_cry_in $0\ALU_dec31_cry_in[1:0] + end + attribute \src "issuer_ls180.v:1567.3-1588.6" + process $proc$issuer_ls180.v:1567$22 + assign { } { } + assign { } { } + assign $0\ALU_dec31_inv_a[0:0] $1\ALU_dec31_inv_a[0:0] + attribute \src "issuer_ls180.v:1568.5-1568.29" + switch \initial + attribute \src "issuer_ls180.v:1568.9-1568.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opc_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\ALU_dec31_inv_a[0:0] \ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_inv_a + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\ALU_dec31_inv_a[0:0] \ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_inv_a + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\ALU_dec31_inv_a[0:0] \ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_inv_a + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\ALU_dec31_inv_a[0:0] \ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_inv_a + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\ALU_dec31_inv_a[0:0] \ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_inv_a + case + assign $1\ALU_dec31_inv_a[0:0] 1'0 + end + sync always + update \ALU_dec31_inv_a $0\ALU_dec31_inv_a[0:0] + end + attribute \src "issuer_ls180.v:1589.3-1610.6" + process $proc$issuer_ls180.v:1589$23 + assign { } { } + assign { } { } + assign $0\ALU_dec31_inv_out[0:0] $1\ALU_dec31_inv_out[0:0] + attribute \src "issuer_ls180.v:1590.5-1590.29" + switch \initial + attribute \src "issuer_ls180.v:1590.9-1590.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opc_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\ALU_dec31_inv_out[0:0] \ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_inv_out + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\ALU_dec31_inv_out[0:0] \ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_inv_out + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\ALU_dec31_inv_out[0:0] \ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_inv_out + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\ALU_dec31_inv_out[0:0] \ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_inv_out + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\ALU_dec31_inv_out[0:0] \ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_inv_out + case + assign $1\ALU_dec31_inv_out[0:0] 1'0 + end + sync always + update \ALU_dec31_inv_out $0\ALU_dec31_inv_out[0:0] + end + attribute \src "issuer_ls180.v:1611.3-1632.6" + process $proc$issuer_ls180.v:1611$24 + assign { } { } + assign { } { } + assign $0\ALU_dec31_cry_out[0:0] $1\ALU_dec31_cry_out[0:0] + attribute \src "issuer_ls180.v:1612.5-1612.29" + switch \initial + attribute \src "issuer_ls180.v:1612.9-1612.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opc_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\ALU_dec31_cry_out[0:0] \ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_cry_out + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\ALU_dec31_cry_out[0:0] \ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_cry_out + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\ALU_dec31_cry_out[0:0] \ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_cry_out + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\ALU_dec31_cry_out[0:0] \ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_cry_out + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\ALU_dec31_cry_out[0:0] \ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_cry_out + case + assign $1\ALU_dec31_cry_out[0:0] 1'0 + end + sync always + update \ALU_dec31_cry_out $0\ALU_dec31_cry_out[0:0] + end + attribute \src "issuer_ls180.v:1633.3-1654.6" + process $proc$issuer_ls180.v:1633$25 + assign { } { } + assign { } { } + assign $0\ALU_dec31_is_32b[0:0] $1\ALU_dec31_is_32b[0:0] + attribute \src "issuer_ls180.v:1634.5-1634.29" + switch \initial + attribute \src "issuer_ls180.v:1634.9-1634.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opc_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\ALU_dec31_is_32b[0:0] \ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_is_32b + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\ALU_dec31_is_32b[0:0] \ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_is_32b + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\ALU_dec31_is_32b[0:0] \ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_is_32b + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\ALU_dec31_is_32b[0:0] \ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_is_32b + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\ALU_dec31_is_32b[0:0] \ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_is_32b + case + assign $1\ALU_dec31_is_32b[0:0] 1'0 + end + sync always + update \ALU_dec31_is_32b $0\ALU_dec31_is_32b[0:0] + end + attribute \src "issuer_ls180.v:1655.3-1676.6" + process $proc$issuer_ls180.v:1655$26 + assign { } { } + assign { } { } + assign $0\ALU_dec31_sgn[0:0] $1\ALU_dec31_sgn[0:0] + attribute \src "issuer_ls180.v:1656.5-1656.29" + switch \initial + attribute \src "issuer_ls180.v:1656.9-1656.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opc_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\ALU_dec31_sgn[0:0] \ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_sgn + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\ALU_dec31_sgn[0:0] \ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_sgn + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\ALU_dec31_sgn[0:0] \ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_sgn + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\ALU_dec31_sgn[0:0] \ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_sgn + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\ALU_dec31_sgn[0:0] \ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_sgn + case + assign $1\ALU_dec31_sgn[0:0] 1'0 + end + sync always + update \ALU_dec31_sgn $0\ALU_dec31_sgn[0:0] + end + attribute \src "issuer_ls180.v:1677.3-1698.6" + process $proc$issuer_ls180.v:1677$27 + assign { } { } + assign { } { } + assign $0\ALU_dec31_function_unit[11:0] $1\ALU_dec31_function_unit[11:0] + attribute \src "issuer_ls180.v:1678.5-1678.29" + switch \initial + attribute \src "issuer_ls180.v:1678.9-1678.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opc_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\ALU_dec31_function_unit[11:0] \ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_function_unit + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\ALU_dec31_function_unit[11:0] \ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_function_unit + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\ALU_dec31_function_unit[11:0] \ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_function_unit + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\ALU_dec31_function_unit[11:0] \ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_function_unit + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\ALU_dec31_function_unit[11:0] \ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_function_unit + case + assign $1\ALU_dec31_function_unit[11:0] 12'000000000000 + end + sync always + update \ALU_dec31_function_unit $0\ALU_dec31_function_unit[11:0] + end + attribute \src "issuer_ls180.v:1699.3-1720.6" + process $proc$issuer_ls180.v:1699$28 + assign { } { } + assign { } { } + assign $0\ALU_dec31_internal_op[6:0] $1\ALU_dec31_internal_op[6:0] + attribute \src "issuer_ls180.v:1700.5-1700.29" + switch \initial + attribute \src "issuer_ls180.v:1700.9-1700.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opc_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\ALU_dec31_internal_op[6:0] \ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_internal_op + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\ALU_dec31_internal_op[6:0] \ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_internal_op + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\ALU_dec31_internal_op[6:0] \ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_internal_op + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\ALU_dec31_internal_op[6:0] \ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_internal_op + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\ALU_dec31_internal_op[6:0] \ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_internal_op + case + assign $1\ALU_dec31_internal_op[6:0] 7'0000000 + end + sync always + update \ALU_dec31_internal_op $0\ALU_dec31_internal_op[6:0] + end + attribute \src "issuer_ls180.v:1721.3-1742.6" + process $proc$issuer_ls180.v:1721$29 + assign { } { } + assign { } { } + assign $0\ALU_dec31_in1_sel[2:0] $1\ALU_dec31_in1_sel[2:0] + attribute \src "issuer_ls180.v:1722.5-1722.29" + switch \initial + attribute \src "issuer_ls180.v:1722.9-1722.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opc_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\ALU_dec31_in1_sel[2:0] \ALU_dec31_dec_sub10_ALU_dec31_dec_sub10_in1_sel + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\ALU_dec31_in1_sel[2:0] \ALU_dec31_dec_sub0_ALU_dec31_dec_sub0_in1_sel + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\ALU_dec31_in1_sel[2:0] \ALU_dec31_dec_sub26_ALU_dec31_dec_sub26_in1_sel + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\ALU_dec31_in1_sel[2:0] \ALU_dec31_dec_sub22_ALU_dec31_dec_sub22_in1_sel + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\ALU_dec31_in1_sel[2:0] \ALU_dec31_dec_sub8_ALU_dec31_dec_sub8_in1_sel + case + assign $1\ALU_dec31_in1_sel[2:0] 3'000 + end + sync always + update \ALU_dec31_in1_sel $0\ALU_dec31_in1_sel[2:0] + end + attribute \src "issuer_ls180.v:335.7-335.20" + process $proc$issuer_ls180.v:335$30 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + connect \ALU_dec31_dec_sub8_opcode_in \opcode_in + connect \ALU_dec31_dec_sub22_opcode_in \opcode_in + connect \ALU_dec31_dec_sub26_opcode_in \opcode_in + connect \ALU_dec31_dec_sub0_opcode_in \opcode_in + connect \ALU_dec31_dec_sub10_opcode_in \opcode_in + connect \opc_in \opcode_switch [4:0] + connect \opcode_switch \opcode_in [10:1] +end +attribute \src "issuer_ls180.v:1754.1-2163.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.dec_ALU.dec.ALU_dec31.ALU_dec31_dec_sub0" +attribute \generator "nMigen" +module \ALU_dec31_dec_sub0 + attribute \src "issuer_ls180.v:2082.3-2097.6" + wire width 3 $0\ALU_dec31_dec_sub0_cr_in[2:0] + attribute \src "issuer_ls180.v:2098.3-2113.6" + wire width 3 $0\ALU_dec31_dec_sub0_cr_out[2:0] + attribute \src "issuer_ls180.v:2146.3-2161.6" + wire width 2 $0\ALU_dec31_dec_sub0_cry_in[1:0] + attribute \src "issuer_ls180.v:1986.3-2001.6" + wire $0\ALU_dec31_dec_sub0_cry_out[0:0] + attribute \src "issuer_ls180.v:1938.3-1953.6" + wire width 12 $0\ALU_dec31_dec_sub0_function_unit[11:0] + attribute \src "issuer_ls180.v:2050.3-2065.6" + wire width 3 $0\ALU_dec31_dec_sub0_in1_sel[2:0] + attribute \src "issuer_ls180.v:2066.3-2081.6" + wire width 4 $0\ALU_dec31_dec_sub0_in2_sel[3:0] + attribute \src "issuer_ls180.v:2034.3-2049.6" + wire width 7 $0\ALU_dec31_dec_sub0_internal_op[6:0] + attribute \src "issuer_ls180.v:1954.3-1969.6" + wire $0\ALU_dec31_dec_sub0_inv_a[0:0] + attribute \src "issuer_ls180.v:1970.3-1985.6" + wire $0\ALU_dec31_dec_sub0_inv_out[0:0] + attribute \src "issuer_ls180.v:2002.3-2017.6" + wire $0\ALU_dec31_dec_sub0_is_32b[0:0] + attribute \src "issuer_ls180.v:2114.3-2129.6" + wire width 4 $0\ALU_dec31_dec_sub0_ldst_len[3:0] + attribute \src "issuer_ls180.v:2130.3-2145.6" + wire width 2 $0\ALU_dec31_dec_sub0_rc_sel[1:0] + attribute \src "issuer_ls180.v:2018.3-2033.6" + wire $0\ALU_dec31_dec_sub0_sgn[0:0] + attribute \src "issuer_ls180.v:1755.7-1755.20" + wire $0\initial[0:0] + attribute \src "issuer_ls180.v:2082.3-2097.6" + wire width 3 $1\ALU_dec31_dec_sub0_cr_in[2:0] + attribute \src "issuer_ls180.v:2098.3-2113.6" + wire width 3 $1\ALU_dec31_dec_sub0_cr_out[2:0] + attribute \src "issuer_ls180.v:2146.3-2161.6" + wire width 2 $1\ALU_dec31_dec_sub0_cry_in[1:0] + attribute \src "issuer_ls180.v:1986.3-2001.6" + wire $1\ALU_dec31_dec_sub0_cry_out[0:0] + attribute \src "issuer_ls180.v:1938.3-1953.6" + wire width 12 $1\ALU_dec31_dec_sub0_function_unit[11:0] + attribute \src "issuer_ls180.v:2050.3-2065.6" + wire width 3 $1\ALU_dec31_dec_sub0_in1_sel[2:0] + attribute \src "issuer_ls180.v:2066.3-2081.6" + wire width 4 $1\ALU_dec31_dec_sub0_in2_sel[3:0] + attribute \src "issuer_ls180.v:2034.3-2049.6" + wire width 7 $1\ALU_dec31_dec_sub0_internal_op[6:0] + attribute \src "issuer_ls180.v:1954.3-1969.6" + wire $1\ALU_dec31_dec_sub0_inv_a[0:0] + attribute \src "issuer_ls180.v:1970.3-1985.6" + wire $1\ALU_dec31_dec_sub0_inv_out[0:0] + attribute \src "issuer_ls180.v:2002.3-2017.6" + wire $1\ALU_dec31_dec_sub0_is_32b[0:0] + attribute \src "issuer_ls180.v:2114.3-2129.6" + wire width 4 $1\ALU_dec31_dec_sub0_ldst_len[3:0] + attribute \src "issuer_ls180.v:2130.3-2145.6" + wire width 2 $1\ALU_dec31_dec_sub0_rc_sel[1:0] + attribute \src "issuer_ls180.v:2018.3-2033.6" + wire $1\ALU_dec31_dec_sub0_sgn[0:0] + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 5 \ALU_dec31_dec_sub0_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 6 \ALU_dec31_dec_sub0_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 9 \ALU_dec31_dec_sub0_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 12 \ALU_dec31_dec_sub0_cry_out + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 12 output 1 \ALU_dec31_dec_sub0_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 3 \ALU_dec31_dec_sub0_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 output 4 \ALU_dec31_dec_sub0_in2_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 7 output 2 \ALU_dec31_dec_sub0_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 10 \ALU_dec31_dec_sub0_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 11 \ALU_dec31_dec_sub0_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 13 \ALU_dec31_dec_sub0_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 output 7 \ALU_dec31_dec_sub0_ldst_len + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 8 \ALU_dec31_dec_sub0_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 14 \ALU_dec31_dec_sub0_sgn + attribute \src "issuer_ls180.v:1755.7-1755.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + wire width 32 input 15 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:320" + wire width 5 \opcode_switch + attribute \src "issuer_ls180.v:1755.7-1755.20" + process $proc$issuer_ls180.v:1755$45 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "issuer_ls180.v:1938.3-1953.6" + process $proc$issuer_ls180.v:1938$31 + assign { } { } + assign { } { } + assign $0\ALU_dec31_dec_sub0_function_unit[11:0] $1\ALU_dec31_dec_sub0_function_unit[11:0] + attribute \src "issuer_ls180.v:1939.5-1939.29" + switch \initial + attribute \src "issuer_ls180.v:1939.9-1939.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\ALU_dec31_dec_sub0_function_unit[11:0] 12'000000000010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\ALU_dec31_dec_sub0_function_unit[11:0] 12'000000000010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\ALU_dec31_dec_sub0_function_unit[11:0] 12'000000000010 + case + assign $1\ALU_dec31_dec_sub0_function_unit[11:0] 12'000000000000 + end + sync always + update \ALU_dec31_dec_sub0_function_unit $0\ALU_dec31_dec_sub0_function_unit[11:0] + end + attribute \src "issuer_ls180.v:1954.3-1969.6" + process $proc$issuer_ls180.v:1954$32 + assign { } { } + assign { } { } + assign $0\ALU_dec31_dec_sub0_inv_a[0:0] $1\ALU_dec31_dec_sub0_inv_a[0:0] + attribute \src "issuer_ls180.v:1955.5-1955.29" + switch \initial + attribute \src "issuer_ls180.v:1955.9-1955.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\ALU_dec31_dec_sub0_inv_a[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\ALU_dec31_dec_sub0_inv_a[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\ALU_dec31_dec_sub0_inv_a[0:0] 1'1 + case + assign $1\ALU_dec31_dec_sub0_inv_a[0:0] 1'0 + end + sync always + update \ALU_dec31_dec_sub0_inv_a $0\ALU_dec31_dec_sub0_inv_a[0:0] + end + attribute \src "issuer_ls180.v:1970.3-1985.6" + process $proc$issuer_ls180.v:1970$33 + assign { } { } + assign { } { } + assign $0\ALU_dec31_dec_sub0_inv_out[0:0] $1\ALU_dec31_dec_sub0_inv_out[0:0] + attribute \src "issuer_ls180.v:1971.5-1971.29" + switch \initial + attribute \src "issuer_ls180.v:1971.9-1971.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\ALU_dec31_dec_sub0_inv_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\ALU_dec31_dec_sub0_inv_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\ALU_dec31_dec_sub0_inv_out[0:0] 1'0 + case + assign $1\ALU_dec31_dec_sub0_inv_out[0:0] 1'0 + end + sync always + update \ALU_dec31_dec_sub0_inv_out $0\ALU_dec31_dec_sub0_inv_out[0:0] + end + attribute \src "issuer_ls180.v:1986.3-2001.6" + process $proc$issuer_ls180.v:1986$34 + assign { } { } + assign { } { } + assign $0\ALU_dec31_dec_sub0_cry_out[0:0] $1\ALU_dec31_dec_sub0_cry_out[0:0] + attribute \src "issuer_ls180.v:1987.5-1987.29" + switch \initial + attribute \src "issuer_ls180.v:1987.9-1987.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\ALU_dec31_dec_sub0_cry_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\ALU_dec31_dec_sub0_cry_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\ALU_dec31_dec_sub0_cry_out[0:0] 1'0 + case + assign $1\ALU_dec31_dec_sub0_cry_out[0:0] 1'0 + end + sync always + update \ALU_dec31_dec_sub0_cry_out $0\ALU_dec31_dec_sub0_cry_out[0:0] + end + attribute \src "issuer_ls180.v:2002.3-2017.6" + process $proc$issuer_ls180.v:2002$35 + assign { } { } + assign { } { } + assign $0\ALU_dec31_dec_sub0_is_32b[0:0] $1\ALU_dec31_dec_sub0_is_32b[0:0] + attribute \src "issuer_ls180.v:2003.5-2003.29" + switch \initial + attribute \src "issuer_ls180.v:2003.9-2003.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\ALU_dec31_dec_sub0_is_32b[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\ALU_dec31_dec_sub0_is_32b[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\ALU_dec31_dec_sub0_is_32b[0:0] 1'0 + case + assign $1\ALU_dec31_dec_sub0_is_32b[0:0] 1'0 + end + sync always + update \ALU_dec31_dec_sub0_is_32b $0\ALU_dec31_dec_sub0_is_32b[0:0] + end + attribute \src "issuer_ls180.v:2018.3-2033.6" + process $proc$issuer_ls180.v:2018$36 + assign { } { } + assign { } { } + assign $0\ALU_dec31_dec_sub0_sgn[0:0] $1\ALU_dec31_dec_sub0_sgn[0:0] + attribute \src "issuer_ls180.v:2019.5-2019.29" + switch \initial + attribute \src "issuer_ls180.v:2019.9-2019.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\ALU_dec31_dec_sub0_sgn[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\ALU_dec31_dec_sub0_sgn[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\ALU_dec31_dec_sub0_sgn[0:0] 1'0 + case + assign $1\ALU_dec31_dec_sub0_sgn[0:0] 1'0 + end + sync always + update \ALU_dec31_dec_sub0_sgn $0\ALU_dec31_dec_sub0_sgn[0:0] + end + attribute \src "issuer_ls180.v:2034.3-2049.6" + process $proc$issuer_ls180.v:2034$37 + assign { } { } + assign { } { } + assign $0\ALU_dec31_dec_sub0_internal_op[6:0] $1\ALU_dec31_dec_sub0_internal_op[6:0] + attribute \src "issuer_ls180.v:2035.5-2035.29" + switch \initial + attribute \src "issuer_ls180.v:2035.9-2035.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\ALU_dec31_dec_sub0_internal_op[6:0] 7'0001010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\ALU_dec31_dec_sub0_internal_op[6:0] 7'0001100 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\ALU_dec31_dec_sub0_internal_op[6:0] 7'0001010 + case + assign $1\ALU_dec31_dec_sub0_internal_op[6:0] 7'0000000 + end + sync always + update \ALU_dec31_dec_sub0_internal_op $0\ALU_dec31_dec_sub0_internal_op[6:0] + end + attribute \src "issuer_ls180.v:2050.3-2065.6" + process $proc$issuer_ls180.v:2050$38 + assign { } { } + assign { } { } + assign $0\ALU_dec31_dec_sub0_in1_sel[2:0] $1\ALU_dec31_dec_sub0_in1_sel[2:0] + attribute \src "issuer_ls180.v:2051.5-2051.29" + switch \initial + attribute \src "issuer_ls180.v:2051.9-2051.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\ALU_dec31_dec_sub0_in1_sel[2:0] 3'001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\ALU_dec31_dec_sub0_in1_sel[2:0] 3'001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\ALU_dec31_dec_sub0_in1_sel[2:0] 3'001 + case + assign $1\ALU_dec31_dec_sub0_in1_sel[2:0] 3'000 + end + sync always + update \ALU_dec31_dec_sub0_in1_sel $0\ALU_dec31_dec_sub0_in1_sel[2:0] + end + attribute \src "issuer_ls180.v:2066.3-2081.6" + process $proc$issuer_ls180.v:2066$39 + assign { } { } + assign { } { } + assign $0\ALU_dec31_dec_sub0_in2_sel[3:0] $1\ALU_dec31_dec_sub0_in2_sel[3:0] + attribute \src "issuer_ls180.v:2067.5-2067.29" + switch \initial + attribute \src "issuer_ls180.v:2067.9-2067.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\ALU_dec31_dec_sub0_in2_sel[3:0] 4'0001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\ALU_dec31_dec_sub0_in2_sel[3:0] 4'0001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\ALU_dec31_dec_sub0_in2_sel[3:0] 4'0001 + case + assign $1\ALU_dec31_dec_sub0_in2_sel[3:0] 4'0000 + end + sync always + update \ALU_dec31_dec_sub0_in2_sel $0\ALU_dec31_dec_sub0_in2_sel[3:0] + end + attribute \src "issuer_ls180.v:2082.3-2097.6" + process $proc$issuer_ls180.v:2082$40 + assign { } { } + assign { } { } + assign $0\ALU_dec31_dec_sub0_cr_in[2:0] $1\ALU_dec31_dec_sub0_cr_in[2:0] + attribute \src "issuer_ls180.v:2083.5-2083.29" + switch \initial + attribute \src "issuer_ls180.v:2083.9-2083.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\ALU_dec31_dec_sub0_cr_in[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\ALU_dec31_dec_sub0_cr_in[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\ALU_dec31_dec_sub0_cr_in[2:0] 3'000 + case + assign $1\ALU_dec31_dec_sub0_cr_in[2:0] 3'000 + end + sync always + update \ALU_dec31_dec_sub0_cr_in $0\ALU_dec31_dec_sub0_cr_in[2:0] + end + attribute \src "issuer_ls180.v:2098.3-2113.6" + process $proc$issuer_ls180.v:2098$41 + assign { } { } + assign { } { } + assign $0\ALU_dec31_dec_sub0_cr_out[2:0] $1\ALU_dec31_dec_sub0_cr_out[2:0] + attribute \src "issuer_ls180.v:2099.5-2099.29" + switch \initial + attribute \src "issuer_ls180.v:2099.9-2099.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\ALU_dec31_dec_sub0_cr_out[2:0] 3'010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\ALU_dec31_dec_sub0_cr_out[2:0] 3'010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\ALU_dec31_dec_sub0_cr_out[2:0] 3'010 + case + assign $1\ALU_dec31_dec_sub0_cr_out[2:0] 3'000 + end + sync always + update \ALU_dec31_dec_sub0_cr_out $0\ALU_dec31_dec_sub0_cr_out[2:0] + end + attribute \src "issuer_ls180.v:2114.3-2129.6" + process $proc$issuer_ls180.v:2114$42 + assign { } { } + assign { } { } + assign $0\ALU_dec31_dec_sub0_ldst_len[3:0] $1\ALU_dec31_dec_sub0_ldst_len[3:0] + attribute \src "issuer_ls180.v:2115.5-2115.29" + switch \initial + attribute \src "issuer_ls180.v:2115.9-2115.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\ALU_dec31_dec_sub0_ldst_len[3:0] 4'0000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\ALU_dec31_dec_sub0_ldst_len[3:0] 4'0000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\ALU_dec31_dec_sub0_ldst_len[3:0] 4'0000 + case + assign $1\ALU_dec31_dec_sub0_ldst_len[3:0] 4'0000 + end + sync always + update \ALU_dec31_dec_sub0_ldst_len $0\ALU_dec31_dec_sub0_ldst_len[3:0] + end + attribute \src "issuer_ls180.v:2130.3-2145.6" + process $proc$issuer_ls180.v:2130$43 + assign { } { } + assign { } { } + assign $0\ALU_dec31_dec_sub0_rc_sel[1:0] $1\ALU_dec31_dec_sub0_rc_sel[1:0] + attribute \src "issuer_ls180.v:2131.5-2131.29" + switch \initial + attribute \src "issuer_ls180.v:2131.9-2131.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\ALU_dec31_dec_sub0_rc_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\ALU_dec31_dec_sub0_rc_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\ALU_dec31_dec_sub0_rc_sel[1:0] 2'00 + case + assign $1\ALU_dec31_dec_sub0_rc_sel[1:0] 2'00 + end + sync always + update \ALU_dec31_dec_sub0_rc_sel $0\ALU_dec31_dec_sub0_rc_sel[1:0] + end + attribute \src "issuer_ls180.v:2146.3-2161.6" + process $proc$issuer_ls180.v:2146$44 + assign { } { } + assign { } { } + assign $0\ALU_dec31_dec_sub0_cry_in[1:0] $1\ALU_dec31_dec_sub0_cry_in[1:0] + attribute \src "issuer_ls180.v:2147.5-2147.29" + switch \initial + attribute \src "issuer_ls180.v:2147.9-2147.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\ALU_dec31_dec_sub0_cry_in[1:0] 2'01 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\ALU_dec31_dec_sub0_cry_in[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\ALU_dec31_dec_sub0_cry_in[1:0] 2'01 + case + assign $1\ALU_dec31_dec_sub0_cry_in[1:0] 2'00 + end + sync always + update \ALU_dec31_dec_sub0_cry_in $0\ALU_dec31_dec_sub0_cry_in[1:0] + end + connect \opcode_switch \opcode_in [10:6] +end +attribute \src "issuer_ls180.v:2167.1-2870.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.dec_ALU.dec.ALU_dec31.ALU_dec31_dec_sub10" +attribute \generator "nMigen" +module \ALU_dec31_dec_sub10 + attribute \src "issuer_ls180.v:2684.3-2720.6" + wire width 3 $0\ALU_dec31_dec_sub10_cr_in[2:0] + attribute \src "issuer_ls180.v:2721.3-2757.6" + wire width 3 $0\ALU_dec31_dec_sub10_cr_out[2:0] + attribute \src "issuer_ls180.v:2832.3-2868.6" + wire width 2 $0\ALU_dec31_dec_sub10_cry_in[1:0] + attribute \src "issuer_ls180.v:2462.3-2498.6" + wire $0\ALU_dec31_dec_sub10_cry_out[0:0] + attribute \src "issuer_ls180.v:2351.3-2387.6" + wire width 12 $0\ALU_dec31_dec_sub10_function_unit[11:0] + attribute \src "issuer_ls180.v:2610.3-2646.6" + wire width 3 $0\ALU_dec31_dec_sub10_in1_sel[2:0] + attribute \src "issuer_ls180.v:2647.3-2683.6" + wire width 4 $0\ALU_dec31_dec_sub10_in2_sel[3:0] + attribute \src "issuer_ls180.v:2573.3-2609.6" + wire width 7 $0\ALU_dec31_dec_sub10_internal_op[6:0] + attribute \src "issuer_ls180.v:2388.3-2424.6" + wire $0\ALU_dec31_dec_sub10_inv_a[0:0] + attribute \src "issuer_ls180.v:2425.3-2461.6" + wire $0\ALU_dec31_dec_sub10_inv_out[0:0] + attribute \src "issuer_ls180.v:2499.3-2535.6" + wire $0\ALU_dec31_dec_sub10_is_32b[0:0] + attribute \src "issuer_ls180.v:2758.3-2794.6" + wire width 4 $0\ALU_dec31_dec_sub10_ldst_len[3:0] + attribute \src "issuer_ls180.v:2795.3-2831.6" + wire width 2 $0\ALU_dec31_dec_sub10_rc_sel[1:0] + attribute \src "issuer_ls180.v:2536.3-2572.6" + wire $0\ALU_dec31_dec_sub10_sgn[0:0] + attribute \src "issuer_ls180.v:2168.7-2168.20" + wire $0\initial[0:0] + attribute \src "issuer_ls180.v:2684.3-2720.6" + wire width 3 $1\ALU_dec31_dec_sub10_cr_in[2:0] + attribute \src "issuer_ls180.v:2721.3-2757.6" + wire width 3 $1\ALU_dec31_dec_sub10_cr_out[2:0] + attribute \src "issuer_ls180.v:2832.3-2868.6" + wire width 2 $1\ALU_dec31_dec_sub10_cry_in[1:0] + attribute \src "issuer_ls180.v:2462.3-2498.6" + wire $1\ALU_dec31_dec_sub10_cry_out[0:0] + attribute \src "issuer_ls180.v:2351.3-2387.6" + wire width 12 $1\ALU_dec31_dec_sub10_function_unit[11:0] + attribute \src "issuer_ls180.v:2610.3-2646.6" + wire width 3 $1\ALU_dec31_dec_sub10_in1_sel[2:0] + attribute \src "issuer_ls180.v:2647.3-2683.6" + wire width 4 $1\ALU_dec31_dec_sub10_in2_sel[3:0] + attribute \src "issuer_ls180.v:2573.3-2609.6" + wire width 7 $1\ALU_dec31_dec_sub10_internal_op[6:0] + attribute \src "issuer_ls180.v:2388.3-2424.6" + wire $1\ALU_dec31_dec_sub10_inv_a[0:0] + attribute \src "issuer_ls180.v:2425.3-2461.6" + wire $1\ALU_dec31_dec_sub10_inv_out[0:0] + attribute \src "issuer_ls180.v:2499.3-2535.6" + wire $1\ALU_dec31_dec_sub10_is_32b[0:0] + attribute \src "issuer_ls180.v:2758.3-2794.6" + wire width 4 $1\ALU_dec31_dec_sub10_ldst_len[3:0] + attribute \src "issuer_ls180.v:2795.3-2831.6" + wire width 2 $1\ALU_dec31_dec_sub10_rc_sel[1:0] + attribute \src "issuer_ls180.v:2536.3-2572.6" + wire $1\ALU_dec31_dec_sub10_sgn[0:0] + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 5 \ALU_dec31_dec_sub10_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 6 \ALU_dec31_dec_sub10_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 9 \ALU_dec31_dec_sub10_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 12 \ALU_dec31_dec_sub10_cry_out + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 12 output 1 \ALU_dec31_dec_sub10_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 3 \ALU_dec31_dec_sub10_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 output 4 \ALU_dec31_dec_sub10_in2_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 7 output 2 \ALU_dec31_dec_sub10_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 10 \ALU_dec31_dec_sub10_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 11 \ALU_dec31_dec_sub10_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 13 \ALU_dec31_dec_sub10_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 output 7 \ALU_dec31_dec_sub10_ldst_len + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 8 \ALU_dec31_dec_sub10_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 14 \ALU_dec31_dec_sub10_sgn + attribute \src "issuer_ls180.v:2168.7-2168.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + wire width 32 input 15 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:320" + wire width 5 \opcode_switch + attribute \src "issuer_ls180.v:2168.7-2168.20" + process $proc$issuer_ls180.v:2168$60 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "issuer_ls180.v:2351.3-2387.6" + process $proc$issuer_ls180.v:2351$46 + assign { } { } + assign { } { } + assign $0\ALU_dec31_dec_sub10_function_unit[11:0] $1\ALU_dec31_dec_sub10_function_unit[11:0] + attribute \src "issuer_ls180.v:2352.5-2352.29" + switch \initial + attribute \src "issuer_ls180.v:2352.9-2352.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\ALU_dec31_dec_sub10_function_unit[11:0] 12'000000000010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\ALU_dec31_dec_sub10_function_unit[11:0] 12'000000000010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\ALU_dec31_dec_sub10_function_unit[11:0] 12'000000000010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\ALU_dec31_dec_sub10_function_unit[11:0] 12'000000000010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\ALU_dec31_dec_sub10_function_unit[11:0] 12'000000000010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\ALU_dec31_dec_sub10_function_unit[11:0] 12'000000000010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\ALU_dec31_dec_sub10_function_unit[11:0] 12'000000000010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\ALU_dec31_dec_sub10_function_unit[11:0] 12'000000000010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\ALU_dec31_dec_sub10_function_unit[11:0] 12'000000000010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\ALU_dec31_dec_sub10_function_unit[11:0] 12'000000000010 + case + assign $1\ALU_dec31_dec_sub10_function_unit[11:0] 12'000000000000 + end + sync always + update \ALU_dec31_dec_sub10_function_unit $0\ALU_dec31_dec_sub10_function_unit[11:0] + end + attribute \src "issuer_ls180.v:2388.3-2424.6" + process $proc$issuer_ls180.v:2388$47 + assign { } { } + assign { } { } + assign $0\ALU_dec31_dec_sub10_inv_a[0:0] $1\ALU_dec31_dec_sub10_inv_a[0:0] + attribute \src "issuer_ls180.v:2389.5-2389.29" + switch \initial + attribute \src "issuer_ls180.v:2389.9-2389.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\ALU_dec31_dec_sub10_inv_a[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\ALU_dec31_dec_sub10_inv_a[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\ALU_dec31_dec_sub10_inv_a[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\ALU_dec31_dec_sub10_inv_a[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\ALU_dec31_dec_sub10_inv_a[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\ALU_dec31_dec_sub10_inv_a[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\ALU_dec31_dec_sub10_inv_a[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\ALU_dec31_dec_sub10_inv_a[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\ALU_dec31_dec_sub10_inv_a[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\ALU_dec31_dec_sub10_inv_a[0:0] 1'0 + case + assign $1\ALU_dec31_dec_sub10_inv_a[0:0] 1'0 + end + sync always + update \ALU_dec31_dec_sub10_inv_a $0\ALU_dec31_dec_sub10_inv_a[0:0] + end + attribute \src "issuer_ls180.v:2425.3-2461.6" + process $proc$issuer_ls180.v:2425$48 + assign { } { } + assign { } { } + assign $0\ALU_dec31_dec_sub10_inv_out[0:0] $1\ALU_dec31_dec_sub10_inv_out[0:0] + attribute \src "issuer_ls180.v:2426.5-2426.29" + switch \initial + attribute \src "issuer_ls180.v:2426.9-2426.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\ALU_dec31_dec_sub10_inv_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\ALU_dec31_dec_sub10_inv_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\ALU_dec31_dec_sub10_inv_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\ALU_dec31_dec_sub10_inv_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\ALU_dec31_dec_sub10_inv_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\ALU_dec31_dec_sub10_inv_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\ALU_dec31_dec_sub10_inv_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\ALU_dec31_dec_sub10_inv_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\ALU_dec31_dec_sub10_inv_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\ALU_dec31_dec_sub10_inv_out[0:0] 1'0 + case + assign $1\ALU_dec31_dec_sub10_inv_out[0:0] 1'0 + end + sync always + update \ALU_dec31_dec_sub10_inv_out $0\ALU_dec31_dec_sub10_inv_out[0:0] + end + attribute \src "issuer_ls180.v:2462.3-2498.6" + process $proc$issuer_ls180.v:2462$49 + assign { } { } + assign { } { } + assign $0\ALU_dec31_dec_sub10_cry_out[0:0] $1\ALU_dec31_dec_sub10_cry_out[0:0] + attribute \src "issuer_ls180.v:2463.5-2463.29" + switch \initial + attribute \src "issuer_ls180.v:2463.9-2463.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\ALU_dec31_dec_sub10_cry_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\ALU_dec31_dec_sub10_cry_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\ALU_dec31_dec_sub10_cry_out[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\ALU_dec31_dec_sub10_cry_out[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\ALU_dec31_dec_sub10_cry_out[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\ALU_dec31_dec_sub10_cry_out[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\ALU_dec31_dec_sub10_cry_out[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\ALU_dec31_dec_sub10_cry_out[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\ALU_dec31_dec_sub10_cry_out[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\ALU_dec31_dec_sub10_cry_out[0:0] 1'1 + case + assign $1\ALU_dec31_dec_sub10_cry_out[0:0] 1'0 + end + sync always + update \ALU_dec31_dec_sub10_cry_out $0\ALU_dec31_dec_sub10_cry_out[0:0] + end + attribute \src "issuer_ls180.v:2499.3-2535.6" + process $proc$issuer_ls180.v:2499$50 + assign { } { } + assign { } { } + assign $0\ALU_dec31_dec_sub10_is_32b[0:0] $1\ALU_dec31_dec_sub10_is_32b[0:0] + attribute \src "issuer_ls180.v:2500.5-2500.29" + switch \initial + attribute \src "issuer_ls180.v:2500.9-2500.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\ALU_dec31_dec_sub10_is_32b[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\ALU_dec31_dec_sub10_is_32b[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\ALU_dec31_dec_sub10_is_32b[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\ALU_dec31_dec_sub10_is_32b[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\ALU_dec31_dec_sub10_is_32b[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\ALU_dec31_dec_sub10_is_32b[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\ALU_dec31_dec_sub10_is_32b[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\ALU_dec31_dec_sub10_is_32b[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\ALU_dec31_dec_sub10_is_32b[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\ALU_dec31_dec_sub10_is_32b[0:0] 1'0 + case + assign $1\ALU_dec31_dec_sub10_is_32b[0:0] 1'0 + end + sync always + update \ALU_dec31_dec_sub10_is_32b $0\ALU_dec31_dec_sub10_is_32b[0:0] + end + attribute \src "issuer_ls180.v:2536.3-2572.6" + process $proc$issuer_ls180.v:2536$51 + assign { } { } + assign { } { } + assign $0\ALU_dec31_dec_sub10_sgn[0:0] $1\ALU_dec31_dec_sub10_sgn[0:0] + attribute \src "issuer_ls180.v:2537.5-2537.29" + switch \initial + attribute \src "issuer_ls180.v:2537.9-2537.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\ALU_dec31_dec_sub10_sgn[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\ALU_dec31_dec_sub10_sgn[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\ALU_dec31_dec_sub10_sgn[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\ALU_dec31_dec_sub10_sgn[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\ALU_dec31_dec_sub10_sgn[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\ALU_dec31_dec_sub10_sgn[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\ALU_dec31_dec_sub10_sgn[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\ALU_dec31_dec_sub10_sgn[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\ALU_dec31_dec_sub10_sgn[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\ALU_dec31_dec_sub10_sgn[0:0] 1'0 + case + assign $1\ALU_dec31_dec_sub10_sgn[0:0] 1'0 + end + sync always + update \ALU_dec31_dec_sub10_sgn $0\ALU_dec31_dec_sub10_sgn[0:0] + end + attribute \src "issuer_ls180.v:2573.3-2609.6" + process $proc$issuer_ls180.v:2573$52 + assign { } { } + assign { } { } + assign $0\ALU_dec31_dec_sub10_internal_op[6:0] $1\ALU_dec31_dec_sub10_internal_op[6:0] + attribute \src "issuer_ls180.v:2574.5-2574.29" + switch \initial + attribute \src "issuer_ls180.v:2574.9-2574.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\ALU_dec31_dec_sub10_internal_op[6:0] 7'0000010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\ALU_dec31_dec_sub10_internal_op[6:0] 7'0000010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\ALU_dec31_dec_sub10_internal_op[6:0] 7'0000010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\ALU_dec31_dec_sub10_internal_op[6:0] 7'0000010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\ALU_dec31_dec_sub10_internal_op[6:0] 7'0000010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\ALU_dec31_dec_sub10_internal_op[6:0] 7'0000010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\ALU_dec31_dec_sub10_internal_op[6:0] 7'0000010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\ALU_dec31_dec_sub10_internal_op[6:0] 7'0000010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\ALU_dec31_dec_sub10_internal_op[6:0] 7'0000010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\ALU_dec31_dec_sub10_internal_op[6:0] 7'0000010 + case + assign $1\ALU_dec31_dec_sub10_internal_op[6:0] 7'0000000 + end + sync always + update \ALU_dec31_dec_sub10_internal_op $0\ALU_dec31_dec_sub10_internal_op[6:0] + end + attribute \src "issuer_ls180.v:2610.3-2646.6" + process $proc$issuer_ls180.v:2610$53 + assign { } { } + assign { } { } + assign $0\ALU_dec31_dec_sub10_in1_sel[2:0] $1\ALU_dec31_dec_sub10_in1_sel[2:0] + attribute \src "issuer_ls180.v:2611.5-2611.29" + switch \initial + attribute \src "issuer_ls180.v:2611.9-2611.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\ALU_dec31_dec_sub10_in1_sel[2:0] 3'001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\ALU_dec31_dec_sub10_in1_sel[2:0] 3'001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\ALU_dec31_dec_sub10_in1_sel[2:0] 3'001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\ALU_dec31_dec_sub10_in1_sel[2:0] 3'001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\ALU_dec31_dec_sub10_in1_sel[2:0] 3'001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\ALU_dec31_dec_sub10_in1_sel[2:0] 3'001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\ALU_dec31_dec_sub10_in1_sel[2:0] 3'001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\ALU_dec31_dec_sub10_in1_sel[2:0] 3'001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\ALU_dec31_dec_sub10_in1_sel[2:0] 3'001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\ALU_dec31_dec_sub10_in1_sel[2:0] 3'001 + case + assign $1\ALU_dec31_dec_sub10_in1_sel[2:0] 3'000 + end + sync always + update \ALU_dec31_dec_sub10_in1_sel $0\ALU_dec31_dec_sub10_in1_sel[2:0] + end + attribute \src "issuer_ls180.v:2647.3-2683.6" + process $proc$issuer_ls180.v:2647$54 + assign { } { } + assign { } { } + assign $0\ALU_dec31_dec_sub10_in2_sel[3:0] $1\ALU_dec31_dec_sub10_in2_sel[3:0] + attribute \src "issuer_ls180.v:2648.5-2648.29" + switch \initial + attribute \src "issuer_ls180.v:2648.9-2648.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\ALU_dec31_dec_sub10_in2_sel[3:0] 4'0001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\ALU_dec31_dec_sub10_in2_sel[3:0] 4'0001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\ALU_dec31_dec_sub10_in2_sel[3:0] 4'0001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\ALU_dec31_dec_sub10_in2_sel[3:0] 4'0001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\ALU_dec31_dec_sub10_in2_sel[3:0] 4'0001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\ALU_dec31_dec_sub10_in2_sel[3:0] 4'0001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\ALU_dec31_dec_sub10_in2_sel[3:0] 4'1001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\ALU_dec31_dec_sub10_in2_sel[3:0] 4'1001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\ALU_dec31_dec_sub10_in2_sel[3:0] 4'0000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\ALU_dec31_dec_sub10_in2_sel[3:0] 4'0000 + case + assign $1\ALU_dec31_dec_sub10_in2_sel[3:0] 4'0000 + end + sync always + update \ALU_dec31_dec_sub10_in2_sel $0\ALU_dec31_dec_sub10_in2_sel[3:0] + end + attribute \src "issuer_ls180.v:2684.3-2720.6" + process $proc$issuer_ls180.v:2684$55 + assign { } { } + assign { } { } + assign $0\ALU_dec31_dec_sub10_cr_in[2:0] $1\ALU_dec31_dec_sub10_cr_in[2:0] + attribute \src "issuer_ls180.v:2685.5-2685.29" + switch \initial + attribute \src "issuer_ls180.v:2685.9-2685.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\ALU_dec31_dec_sub10_cr_in[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\ALU_dec31_dec_sub10_cr_in[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\ALU_dec31_dec_sub10_cr_in[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\ALU_dec31_dec_sub10_cr_in[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\ALU_dec31_dec_sub10_cr_in[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\ALU_dec31_dec_sub10_cr_in[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\ALU_dec31_dec_sub10_cr_in[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\ALU_dec31_dec_sub10_cr_in[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\ALU_dec31_dec_sub10_cr_in[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\ALU_dec31_dec_sub10_cr_in[2:0] 3'000 + case + assign $1\ALU_dec31_dec_sub10_cr_in[2:0] 3'000 + end + sync always + update \ALU_dec31_dec_sub10_cr_in $0\ALU_dec31_dec_sub10_cr_in[2:0] + end + attribute \src "issuer_ls180.v:2721.3-2757.6" + process $proc$issuer_ls180.v:2721$56 + assign { } { } + assign { } { } + assign $0\ALU_dec31_dec_sub10_cr_out[2:0] $1\ALU_dec31_dec_sub10_cr_out[2:0] + attribute \src "issuer_ls180.v:2722.5-2722.29" + switch \initial + attribute \src "issuer_ls180.v:2722.9-2722.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\ALU_dec31_dec_sub10_cr_out[2:0] 3'001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\ALU_dec31_dec_sub10_cr_out[2:0] 3'001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\ALU_dec31_dec_sub10_cr_out[2:0] 3'001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\ALU_dec31_dec_sub10_cr_out[2:0] 3'001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\ALU_dec31_dec_sub10_cr_out[2:0] 3'001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\ALU_dec31_dec_sub10_cr_out[2:0] 3'001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\ALU_dec31_dec_sub10_cr_out[2:0] 3'001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\ALU_dec31_dec_sub10_cr_out[2:0] 3'001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\ALU_dec31_dec_sub10_cr_out[2:0] 3'001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\ALU_dec31_dec_sub10_cr_out[2:0] 3'001 + case + assign $1\ALU_dec31_dec_sub10_cr_out[2:0] 3'000 + end + sync always + update \ALU_dec31_dec_sub10_cr_out $0\ALU_dec31_dec_sub10_cr_out[2:0] + end + attribute \src "issuer_ls180.v:2758.3-2794.6" + process $proc$issuer_ls180.v:2758$57 + assign { } { } + assign { } { } + assign $0\ALU_dec31_dec_sub10_ldst_len[3:0] $1\ALU_dec31_dec_sub10_ldst_len[3:0] + attribute \src "issuer_ls180.v:2759.5-2759.29" + switch \initial + attribute \src "issuer_ls180.v:2759.9-2759.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\ALU_dec31_dec_sub10_ldst_len[3:0] 4'0000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\ALU_dec31_dec_sub10_ldst_len[3:0] 4'0000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\ALU_dec31_dec_sub10_ldst_len[3:0] 4'0000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\ALU_dec31_dec_sub10_ldst_len[3:0] 4'0000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\ALU_dec31_dec_sub10_ldst_len[3:0] 4'0000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\ALU_dec31_dec_sub10_ldst_len[3:0] 4'0000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\ALU_dec31_dec_sub10_ldst_len[3:0] 4'0000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\ALU_dec31_dec_sub10_ldst_len[3:0] 4'0000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\ALU_dec31_dec_sub10_ldst_len[3:0] 4'0000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\ALU_dec31_dec_sub10_ldst_len[3:0] 4'0000 + case + assign $1\ALU_dec31_dec_sub10_ldst_len[3:0] 4'0000 + end + sync always + update \ALU_dec31_dec_sub10_ldst_len $0\ALU_dec31_dec_sub10_ldst_len[3:0] + end + attribute \src "issuer_ls180.v:2795.3-2831.6" + process $proc$issuer_ls180.v:2795$58 + assign { } { } + assign { } { } + assign $0\ALU_dec31_dec_sub10_rc_sel[1:0] $1\ALU_dec31_dec_sub10_rc_sel[1:0] + attribute \src "issuer_ls180.v:2796.5-2796.29" + switch \initial + attribute \src "issuer_ls180.v:2796.9-2796.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\ALU_dec31_dec_sub10_rc_sel[1:0] 2'10 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\ALU_dec31_dec_sub10_rc_sel[1:0] 2'10 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\ALU_dec31_dec_sub10_rc_sel[1:0] 2'10 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\ALU_dec31_dec_sub10_rc_sel[1:0] 2'10 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\ALU_dec31_dec_sub10_rc_sel[1:0] 2'10 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\ALU_dec31_dec_sub10_rc_sel[1:0] 2'10 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\ALU_dec31_dec_sub10_rc_sel[1:0] 2'10 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\ALU_dec31_dec_sub10_rc_sel[1:0] 2'10 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\ALU_dec31_dec_sub10_rc_sel[1:0] 2'10 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\ALU_dec31_dec_sub10_rc_sel[1:0] 2'10 + case + assign $1\ALU_dec31_dec_sub10_rc_sel[1:0] 2'00 + end + sync always + update \ALU_dec31_dec_sub10_rc_sel $0\ALU_dec31_dec_sub10_rc_sel[1:0] + end + attribute \src "issuer_ls180.v:2832.3-2868.6" + process $proc$issuer_ls180.v:2832$59 + assign { } { } + assign { } { } + assign $0\ALU_dec31_dec_sub10_cry_in[1:0] $1\ALU_dec31_dec_sub10_cry_in[1:0] + attribute \src "issuer_ls180.v:2833.5-2833.29" + switch \initial + attribute \src "issuer_ls180.v:2833.9-2833.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\ALU_dec31_dec_sub10_cry_in[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\ALU_dec31_dec_sub10_cry_in[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\ALU_dec31_dec_sub10_cry_in[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\ALU_dec31_dec_sub10_cry_in[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\ALU_dec31_dec_sub10_cry_in[1:0] 2'10 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\ALU_dec31_dec_sub10_cry_in[1:0] 2'10 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\ALU_dec31_dec_sub10_cry_in[1:0] 2'10 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\ALU_dec31_dec_sub10_cry_in[1:0] 2'10 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\ALU_dec31_dec_sub10_cry_in[1:0] 2'10 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\ALU_dec31_dec_sub10_cry_in[1:0] 2'10 + case + assign $1\ALU_dec31_dec_sub10_cry_in[1:0] 2'00 + end + sync always + update \ALU_dec31_dec_sub10_cry_in $0\ALU_dec31_dec_sub10_cry_in[1:0] + end + connect \opcode_switch \opcode_in [10:6] +end +attribute \src "issuer_ls180.v:2874.1-3451.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.dec_ALU.dec.ALU_dec31.ALU_dec31_dec_sub22" +attribute \generator "nMigen" +module \ALU_dec31_dec_sub22 + attribute \src "issuer_ls180.v:3310.3-3337.6" + wire width 3 $0\ALU_dec31_dec_sub22_cr_in[2:0] + attribute \src "issuer_ls180.v:3338.3-3365.6" + wire width 3 $0\ALU_dec31_dec_sub22_cr_out[2:0] + attribute \src "issuer_ls180.v:3422.3-3449.6" + wire width 2 $0\ALU_dec31_dec_sub22_cry_in[1:0] + attribute \src "issuer_ls180.v:3142.3-3169.6" + wire $0\ALU_dec31_dec_sub22_cry_out[0:0] + attribute \src "issuer_ls180.v:3058.3-3085.6" + wire width 12 $0\ALU_dec31_dec_sub22_function_unit[11:0] + attribute \src "issuer_ls180.v:3254.3-3281.6" + wire width 3 $0\ALU_dec31_dec_sub22_in1_sel[2:0] + attribute \src "issuer_ls180.v:3282.3-3309.6" + wire width 4 $0\ALU_dec31_dec_sub22_in2_sel[3:0] + attribute \src "issuer_ls180.v:3226.3-3253.6" + wire width 7 $0\ALU_dec31_dec_sub22_internal_op[6:0] + attribute \src "issuer_ls180.v:3086.3-3113.6" + wire $0\ALU_dec31_dec_sub22_inv_a[0:0] + attribute \src "issuer_ls180.v:3114.3-3141.6" + wire $0\ALU_dec31_dec_sub22_inv_out[0:0] + attribute \src "issuer_ls180.v:3170.3-3197.6" + wire $0\ALU_dec31_dec_sub22_is_32b[0:0] + attribute \src "issuer_ls180.v:3366.3-3393.6" + wire width 4 $0\ALU_dec31_dec_sub22_ldst_len[3:0] + attribute \src "issuer_ls180.v:3394.3-3421.6" + wire width 2 $0\ALU_dec31_dec_sub22_rc_sel[1:0] + attribute \src "issuer_ls180.v:3198.3-3225.6" + wire $0\ALU_dec31_dec_sub22_sgn[0:0] + attribute \src "issuer_ls180.v:2875.7-2875.20" + wire $0\initial[0:0] + attribute \src "issuer_ls180.v:3310.3-3337.6" + wire width 3 $1\ALU_dec31_dec_sub22_cr_in[2:0] + attribute \src "issuer_ls180.v:3338.3-3365.6" + wire width 3 $1\ALU_dec31_dec_sub22_cr_out[2:0] + attribute \src "issuer_ls180.v:3422.3-3449.6" + wire width 2 $1\ALU_dec31_dec_sub22_cry_in[1:0] + attribute \src "issuer_ls180.v:3142.3-3169.6" + wire $1\ALU_dec31_dec_sub22_cry_out[0:0] + attribute \src "issuer_ls180.v:3058.3-3085.6" + wire width 12 $1\ALU_dec31_dec_sub22_function_unit[11:0] + attribute \src "issuer_ls180.v:3254.3-3281.6" + wire width 3 $1\ALU_dec31_dec_sub22_in1_sel[2:0] + attribute \src "issuer_ls180.v:3282.3-3309.6" + wire width 4 $1\ALU_dec31_dec_sub22_in2_sel[3:0] + attribute \src "issuer_ls180.v:3226.3-3253.6" + wire width 7 $1\ALU_dec31_dec_sub22_internal_op[6:0] + attribute \src "issuer_ls180.v:3086.3-3113.6" + wire $1\ALU_dec31_dec_sub22_inv_a[0:0] + attribute \src "issuer_ls180.v:3114.3-3141.6" + wire $1\ALU_dec31_dec_sub22_inv_out[0:0] + attribute \src "issuer_ls180.v:3170.3-3197.6" + wire $1\ALU_dec31_dec_sub22_is_32b[0:0] + attribute \src "issuer_ls180.v:3366.3-3393.6" + wire width 4 $1\ALU_dec31_dec_sub22_ldst_len[3:0] + attribute \src "issuer_ls180.v:3394.3-3421.6" + wire width 2 $1\ALU_dec31_dec_sub22_rc_sel[1:0] + attribute \src "issuer_ls180.v:3198.3-3225.6" + wire $1\ALU_dec31_dec_sub22_sgn[0:0] + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 5 \ALU_dec31_dec_sub22_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 6 \ALU_dec31_dec_sub22_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 9 \ALU_dec31_dec_sub22_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 12 \ALU_dec31_dec_sub22_cry_out + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 12 output 1 \ALU_dec31_dec_sub22_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 3 \ALU_dec31_dec_sub22_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 output 4 \ALU_dec31_dec_sub22_in2_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 7 output 2 \ALU_dec31_dec_sub22_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 10 \ALU_dec31_dec_sub22_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 11 \ALU_dec31_dec_sub22_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 13 \ALU_dec31_dec_sub22_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 output 7 \ALU_dec31_dec_sub22_ldst_len + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 8 \ALU_dec31_dec_sub22_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 14 \ALU_dec31_dec_sub22_sgn + attribute \src "issuer_ls180.v:2875.7-2875.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + wire width 32 input 15 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:320" + wire width 5 \opcode_switch + attribute \src "issuer_ls180.v:2875.7-2875.20" + process $proc$issuer_ls180.v:2875$75 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "issuer_ls180.v:3058.3-3085.6" + process $proc$issuer_ls180.v:3058$61 + assign { } { } + assign { } { } + assign $0\ALU_dec31_dec_sub22_function_unit[11:0] $1\ALU_dec31_dec_sub22_function_unit[11:0] + attribute \src "issuer_ls180.v:3059.5-3059.29" + switch \initial + attribute \src "issuer_ls180.v:3059.9-3059.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\ALU_dec31_dec_sub22_function_unit[11:0] 12'000000000010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\ALU_dec31_dec_sub22_function_unit[11:0] 12'000000000010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\ALU_dec31_dec_sub22_function_unit[11:0] 12'000000000010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\ALU_dec31_dec_sub22_function_unit[11:0] 12'000000000010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\ALU_dec31_dec_sub22_function_unit[11:0] 12'000000000010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\ALU_dec31_dec_sub22_function_unit[11:0] 12'000000000010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\ALU_dec31_dec_sub22_function_unit[11:0] 12'000000000010 + case + assign $1\ALU_dec31_dec_sub22_function_unit[11:0] 12'000000000000 + end + sync always + update \ALU_dec31_dec_sub22_function_unit $0\ALU_dec31_dec_sub22_function_unit[11:0] + end + attribute \src "issuer_ls180.v:3086.3-3113.6" + process $proc$issuer_ls180.v:3086$62 + assign { } { } + assign { } { } + assign $0\ALU_dec31_dec_sub22_inv_a[0:0] $1\ALU_dec31_dec_sub22_inv_a[0:0] + attribute \src "issuer_ls180.v:3087.5-3087.29" + switch \initial + attribute \src "issuer_ls180.v:3087.9-3087.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\ALU_dec31_dec_sub22_inv_a[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\ALU_dec31_dec_sub22_inv_a[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\ALU_dec31_dec_sub22_inv_a[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\ALU_dec31_dec_sub22_inv_a[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\ALU_dec31_dec_sub22_inv_a[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\ALU_dec31_dec_sub22_inv_a[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\ALU_dec31_dec_sub22_inv_a[0:0] 1'0 + case + assign $1\ALU_dec31_dec_sub22_inv_a[0:0] 1'0 + end + sync always + update \ALU_dec31_dec_sub22_inv_a $0\ALU_dec31_dec_sub22_inv_a[0:0] + end + attribute \src "issuer_ls180.v:3114.3-3141.6" + process $proc$issuer_ls180.v:3114$63 + assign { } { } + assign { } { } + assign $0\ALU_dec31_dec_sub22_inv_out[0:0] $1\ALU_dec31_dec_sub22_inv_out[0:0] + attribute \src "issuer_ls180.v:3115.5-3115.29" + switch \initial + attribute \src "issuer_ls180.v:3115.9-3115.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\ALU_dec31_dec_sub22_inv_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\ALU_dec31_dec_sub22_inv_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\ALU_dec31_dec_sub22_inv_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\ALU_dec31_dec_sub22_inv_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\ALU_dec31_dec_sub22_inv_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\ALU_dec31_dec_sub22_inv_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\ALU_dec31_dec_sub22_inv_out[0:0] 1'0 + case + assign $1\ALU_dec31_dec_sub22_inv_out[0:0] 1'0 + end + sync always + update \ALU_dec31_dec_sub22_inv_out $0\ALU_dec31_dec_sub22_inv_out[0:0] + end + attribute \src "issuer_ls180.v:3142.3-3169.6" + process $proc$issuer_ls180.v:3142$64 + assign { } { } + assign { } { } + assign $0\ALU_dec31_dec_sub22_cry_out[0:0] $1\ALU_dec31_dec_sub22_cry_out[0:0] + attribute \src "issuer_ls180.v:3143.5-3143.29" + switch \initial + attribute \src "issuer_ls180.v:3143.9-3143.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\ALU_dec31_dec_sub22_cry_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\ALU_dec31_dec_sub22_cry_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\ALU_dec31_dec_sub22_cry_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\ALU_dec31_dec_sub22_cry_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\ALU_dec31_dec_sub22_cry_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\ALU_dec31_dec_sub22_cry_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\ALU_dec31_dec_sub22_cry_out[0:0] 1'0 + case + assign $1\ALU_dec31_dec_sub22_cry_out[0:0] 1'0 + end + sync always + update \ALU_dec31_dec_sub22_cry_out $0\ALU_dec31_dec_sub22_cry_out[0:0] + end + attribute \src "issuer_ls180.v:3170.3-3197.6" + process $proc$issuer_ls180.v:3170$65 + assign { } { } + assign { } { } + assign $0\ALU_dec31_dec_sub22_is_32b[0:0] $1\ALU_dec31_dec_sub22_is_32b[0:0] + attribute \src "issuer_ls180.v:3171.5-3171.29" + switch \initial + attribute \src "issuer_ls180.v:3171.9-3171.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\ALU_dec31_dec_sub22_is_32b[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\ALU_dec31_dec_sub22_is_32b[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\ALU_dec31_dec_sub22_is_32b[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\ALU_dec31_dec_sub22_is_32b[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\ALU_dec31_dec_sub22_is_32b[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\ALU_dec31_dec_sub22_is_32b[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\ALU_dec31_dec_sub22_is_32b[0:0] 1'0 + case + assign $1\ALU_dec31_dec_sub22_is_32b[0:0] 1'0 + end + sync always + update \ALU_dec31_dec_sub22_is_32b $0\ALU_dec31_dec_sub22_is_32b[0:0] + end + attribute \src "issuer_ls180.v:3198.3-3225.6" + process $proc$issuer_ls180.v:3198$66 + assign { } { } + assign { } { } + assign $0\ALU_dec31_dec_sub22_sgn[0:0] $1\ALU_dec31_dec_sub22_sgn[0:0] + attribute \src "issuer_ls180.v:3199.5-3199.29" + switch \initial + attribute \src "issuer_ls180.v:3199.9-3199.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\ALU_dec31_dec_sub22_sgn[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\ALU_dec31_dec_sub22_sgn[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\ALU_dec31_dec_sub22_sgn[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\ALU_dec31_dec_sub22_sgn[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\ALU_dec31_dec_sub22_sgn[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\ALU_dec31_dec_sub22_sgn[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\ALU_dec31_dec_sub22_sgn[0:0] 1'0 + case + assign $1\ALU_dec31_dec_sub22_sgn[0:0] 1'0 + end + sync always + update \ALU_dec31_dec_sub22_sgn $0\ALU_dec31_dec_sub22_sgn[0:0] + end + attribute \src "issuer_ls180.v:3226.3-3253.6" + process $proc$issuer_ls180.v:3226$67 + assign { } { } + assign { } { } + assign $0\ALU_dec31_dec_sub22_internal_op[6:0] $1\ALU_dec31_dec_sub22_internal_op[6:0] + attribute \src "issuer_ls180.v:3227.5-3227.29" + switch \initial + attribute \src "issuer_ls180.v:3227.9-3227.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\ALU_dec31_dec_sub22_internal_op[6:0] 7'0000001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\ALU_dec31_dec_sub22_internal_op[6:0] 7'0000001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\ALU_dec31_dec_sub22_internal_op[6:0] 7'0000001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\ALU_dec31_dec_sub22_internal_op[6:0] 7'0000001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\ALU_dec31_dec_sub22_internal_op[6:0] 7'0100001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\ALU_dec31_dec_sub22_internal_op[6:0] 7'0000001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\ALU_dec31_dec_sub22_internal_op[6:0] 7'0000001 + case + assign $1\ALU_dec31_dec_sub22_internal_op[6:0] 7'0000000 + end + sync always + update \ALU_dec31_dec_sub22_internal_op $0\ALU_dec31_dec_sub22_internal_op[6:0] + end + attribute \src "issuer_ls180.v:3254.3-3281.6" + process $proc$issuer_ls180.v:3254$68 + assign { } { } + assign { } { } + assign $0\ALU_dec31_dec_sub22_in1_sel[2:0] $1\ALU_dec31_dec_sub22_in1_sel[2:0] + attribute \src "issuer_ls180.v:3255.5-3255.29" + switch \initial + attribute \src "issuer_ls180.v:3255.9-3255.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\ALU_dec31_dec_sub22_in1_sel[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\ALU_dec31_dec_sub22_in1_sel[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\ALU_dec31_dec_sub22_in1_sel[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\ALU_dec31_dec_sub22_in1_sel[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\ALU_dec31_dec_sub22_in1_sel[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\ALU_dec31_dec_sub22_in1_sel[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\ALU_dec31_dec_sub22_in1_sel[2:0] 3'000 + case + assign $1\ALU_dec31_dec_sub22_in1_sel[2:0] 3'000 + end + sync always + update \ALU_dec31_dec_sub22_in1_sel $0\ALU_dec31_dec_sub22_in1_sel[2:0] + end + attribute \src "issuer_ls180.v:3282.3-3309.6" + process $proc$issuer_ls180.v:3282$69 + assign { } { } + assign { } { } + assign $0\ALU_dec31_dec_sub22_in2_sel[3:0] $1\ALU_dec31_dec_sub22_in2_sel[3:0] + attribute \src "issuer_ls180.v:3283.5-3283.29" + switch \initial + attribute \src "issuer_ls180.v:3283.9-3283.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\ALU_dec31_dec_sub22_in2_sel[3:0] 4'0000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\ALU_dec31_dec_sub22_in2_sel[3:0] 4'0000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\ALU_dec31_dec_sub22_in2_sel[3:0] 4'0000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\ALU_dec31_dec_sub22_in2_sel[3:0] 4'0000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\ALU_dec31_dec_sub22_in2_sel[3:0] 4'0000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\ALU_dec31_dec_sub22_in2_sel[3:0] 4'0000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\ALU_dec31_dec_sub22_in2_sel[3:0] 4'0000 + case + assign $1\ALU_dec31_dec_sub22_in2_sel[3:0] 4'0000 + end + sync always + update \ALU_dec31_dec_sub22_in2_sel $0\ALU_dec31_dec_sub22_in2_sel[3:0] + end + attribute \src "issuer_ls180.v:3310.3-3337.6" + process $proc$issuer_ls180.v:3310$70 + assign { } { } + assign { } { } + assign $0\ALU_dec31_dec_sub22_cr_in[2:0] $1\ALU_dec31_dec_sub22_cr_in[2:0] + attribute \src "issuer_ls180.v:3311.5-3311.29" + switch \initial + attribute \src "issuer_ls180.v:3311.9-3311.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\ALU_dec31_dec_sub22_cr_in[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\ALU_dec31_dec_sub22_cr_in[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\ALU_dec31_dec_sub22_cr_in[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\ALU_dec31_dec_sub22_cr_in[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\ALU_dec31_dec_sub22_cr_in[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\ALU_dec31_dec_sub22_cr_in[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\ALU_dec31_dec_sub22_cr_in[2:0] 3'000 + case + assign $1\ALU_dec31_dec_sub22_cr_in[2:0] 3'000 + end + sync always + update \ALU_dec31_dec_sub22_cr_in $0\ALU_dec31_dec_sub22_cr_in[2:0] + end + attribute \src "issuer_ls180.v:3338.3-3365.6" + process $proc$issuer_ls180.v:3338$71 + assign { } { } + assign { } { } + assign $0\ALU_dec31_dec_sub22_cr_out[2:0] $1\ALU_dec31_dec_sub22_cr_out[2:0] + attribute \src "issuer_ls180.v:3339.5-3339.29" + switch \initial + attribute \src "issuer_ls180.v:3339.9-3339.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\ALU_dec31_dec_sub22_cr_out[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\ALU_dec31_dec_sub22_cr_out[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\ALU_dec31_dec_sub22_cr_out[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\ALU_dec31_dec_sub22_cr_out[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\ALU_dec31_dec_sub22_cr_out[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\ALU_dec31_dec_sub22_cr_out[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\ALU_dec31_dec_sub22_cr_out[2:0] 3'000 + case + assign $1\ALU_dec31_dec_sub22_cr_out[2:0] 3'000 + end + sync always + update \ALU_dec31_dec_sub22_cr_out $0\ALU_dec31_dec_sub22_cr_out[2:0] + end + attribute \src "issuer_ls180.v:3366.3-3393.6" + process $proc$issuer_ls180.v:3366$72 + assign { } { } + assign { } { } + assign $0\ALU_dec31_dec_sub22_ldst_len[3:0] $1\ALU_dec31_dec_sub22_ldst_len[3:0] + attribute \src "issuer_ls180.v:3367.5-3367.29" + switch \initial + attribute \src "issuer_ls180.v:3367.9-3367.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\ALU_dec31_dec_sub22_ldst_len[3:0] 4'0000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\ALU_dec31_dec_sub22_ldst_len[3:0] 4'0000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\ALU_dec31_dec_sub22_ldst_len[3:0] 4'0000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\ALU_dec31_dec_sub22_ldst_len[3:0] 4'0000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\ALU_dec31_dec_sub22_ldst_len[3:0] 4'0000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\ALU_dec31_dec_sub22_ldst_len[3:0] 4'0000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\ALU_dec31_dec_sub22_ldst_len[3:0] 4'0000 + case + assign $1\ALU_dec31_dec_sub22_ldst_len[3:0] 4'0000 + end + sync always + update \ALU_dec31_dec_sub22_ldst_len $0\ALU_dec31_dec_sub22_ldst_len[3:0] + end + attribute \src "issuer_ls180.v:3394.3-3421.6" + process $proc$issuer_ls180.v:3394$73 + assign { } { } + assign { } { } + assign $0\ALU_dec31_dec_sub22_rc_sel[1:0] $1\ALU_dec31_dec_sub22_rc_sel[1:0] + attribute \src "issuer_ls180.v:3395.5-3395.29" + switch \initial + attribute \src "issuer_ls180.v:3395.9-3395.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\ALU_dec31_dec_sub22_rc_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\ALU_dec31_dec_sub22_rc_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\ALU_dec31_dec_sub22_rc_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\ALU_dec31_dec_sub22_rc_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\ALU_dec31_dec_sub22_rc_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\ALU_dec31_dec_sub22_rc_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\ALU_dec31_dec_sub22_rc_sel[1:0] 2'00 + case + assign $1\ALU_dec31_dec_sub22_rc_sel[1:0] 2'00 + end + sync always + update \ALU_dec31_dec_sub22_rc_sel $0\ALU_dec31_dec_sub22_rc_sel[1:0] + end + attribute \src "issuer_ls180.v:3422.3-3449.6" + process $proc$issuer_ls180.v:3422$74 + assign { } { } + assign { } { } + assign $0\ALU_dec31_dec_sub22_cry_in[1:0] $1\ALU_dec31_dec_sub22_cry_in[1:0] + attribute \src "issuer_ls180.v:3423.5-3423.29" + switch \initial + attribute \src "issuer_ls180.v:3423.9-3423.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\ALU_dec31_dec_sub22_cry_in[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\ALU_dec31_dec_sub22_cry_in[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\ALU_dec31_dec_sub22_cry_in[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\ALU_dec31_dec_sub22_cry_in[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\ALU_dec31_dec_sub22_cry_in[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\ALU_dec31_dec_sub22_cry_in[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\ALU_dec31_dec_sub22_cry_in[1:0] 2'00 + case + assign $1\ALU_dec31_dec_sub22_cry_in[1:0] 2'00 + end + sync always + update \ALU_dec31_dec_sub22_cry_in $0\ALU_dec31_dec_sub22_cry_in[1:0] + end + connect \opcode_switch \opcode_in [10:6] +end +attribute \src "issuer_ls180.v:3455.1-3864.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.dec_ALU.dec.ALU_dec31.ALU_dec31_dec_sub26" +attribute \generator "nMigen" +module \ALU_dec31_dec_sub26 + attribute \src "issuer_ls180.v:3783.3-3798.6" + wire width 3 $0\ALU_dec31_dec_sub26_cr_in[2:0] + attribute \src "issuer_ls180.v:3799.3-3814.6" + wire width 3 $0\ALU_dec31_dec_sub26_cr_out[2:0] + attribute \src "issuer_ls180.v:3847.3-3862.6" + wire width 2 $0\ALU_dec31_dec_sub26_cry_in[1:0] + attribute \src "issuer_ls180.v:3687.3-3702.6" + wire $0\ALU_dec31_dec_sub26_cry_out[0:0] + attribute \src "issuer_ls180.v:3639.3-3654.6" + wire width 12 $0\ALU_dec31_dec_sub26_function_unit[11:0] + attribute \src "issuer_ls180.v:3751.3-3766.6" + wire width 3 $0\ALU_dec31_dec_sub26_in1_sel[2:0] + attribute \src "issuer_ls180.v:3767.3-3782.6" + wire width 4 $0\ALU_dec31_dec_sub26_in2_sel[3:0] + attribute \src "issuer_ls180.v:3735.3-3750.6" + wire width 7 $0\ALU_dec31_dec_sub26_internal_op[6:0] + attribute \src "issuer_ls180.v:3655.3-3670.6" + wire $0\ALU_dec31_dec_sub26_inv_a[0:0] + attribute \src "issuer_ls180.v:3671.3-3686.6" + wire $0\ALU_dec31_dec_sub26_inv_out[0:0] + attribute \src "issuer_ls180.v:3703.3-3718.6" + wire $0\ALU_dec31_dec_sub26_is_32b[0:0] + attribute \src "issuer_ls180.v:3815.3-3830.6" + wire width 4 $0\ALU_dec31_dec_sub26_ldst_len[3:0] + attribute \src "issuer_ls180.v:3831.3-3846.6" + wire width 2 $0\ALU_dec31_dec_sub26_rc_sel[1:0] + attribute \src "issuer_ls180.v:3719.3-3734.6" + wire $0\ALU_dec31_dec_sub26_sgn[0:0] + attribute \src "issuer_ls180.v:3456.7-3456.20" + wire $0\initial[0:0] + attribute \src "issuer_ls180.v:3783.3-3798.6" + wire width 3 $1\ALU_dec31_dec_sub26_cr_in[2:0] + attribute \src "issuer_ls180.v:3799.3-3814.6" + wire width 3 $1\ALU_dec31_dec_sub26_cr_out[2:0] + attribute \src "issuer_ls180.v:3847.3-3862.6" + wire width 2 $1\ALU_dec31_dec_sub26_cry_in[1:0] + attribute \src "issuer_ls180.v:3687.3-3702.6" + wire $1\ALU_dec31_dec_sub26_cry_out[0:0] + attribute \src "issuer_ls180.v:3639.3-3654.6" + wire width 12 $1\ALU_dec31_dec_sub26_function_unit[11:0] + attribute \src "issuer_ls180.v:3751.3-3766.6" + wire width 3 $1\ALU_dec31_dec_sub26_in1_sel[2:0] + attribute \src "issuer_ls180.v:3767.3-3782.6" + wire width 4 $1\ALU_dec31_dec_sub26_in2_sel[3:0] + attribute \src "issuer_ls180.v:3735.3-3750.6" + wire width 7 $1\ALU_dec31_dec_sub26_internal_op[6:0] + attribute \src "issuer_ls180.v:3655.3-3670.6" + wire $1\ALU_dec31_dec_sub26_inv_a[0:0] + attribute \src "issuer_ls180.v:3671.3-3686.6" + wire $1\ALU_dec31_dec_sub26_inv_out[0:0] + attribute \src "issuer_ls180.v:3703.3-3718.6" + wire $1\ALU_dec31_dec_sub26_is_32b[0:0] + attribute \src "issuer_ls180.v:3815.3-3830.6" + wire width 4 $1\ALU_dec31_dec_sub26_ldst_len[3:0] + attribute \src "issuer_ls180.v:3831.3-3846.6" + wire width 2 $1\ALU_dec31_dec_sub26_rc_sel[1:0] + attribute \src "issuer_ls180.v:3719.3-3734.6" + wire $1\ALU_dec31_dec_sub26_sgn[0:0] + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 5 \ALU_dec31_dec_sub26_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 6 \ALU_dec31_dec_sub26_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 9 \ALU_dec31_dec_sub26_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 12 \ALU_dec31_dec_sub26_cry_out + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 12 output 1 \ALU_dec31_dec_sub26_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 3 \ALU_dec31_dec_sub26_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 output 4 \ALU_dec31_dec_sub26_in2_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 7 output 2 \ALU_dec31_dec_sub26_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 10 \ALU_dec31_dec_sub26_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 11 \ALU_dec31_dec_sub26_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 13 \ALU_dec31_dec_sub26_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 output 7 \ALU_dec31_dec_sub26_ldst_len + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 8 \ALU_dec31_dec_sub26_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 14 \ALU_dec31_dec_sub26_sgn + attribute \src "issuer_ls180.v:3456.7-3456.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + wire width 32 input 15 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:320" + wire width 5 \opcode_switch + attribute \src "issuer_ls180.v:3456.7-3456.20" + process $proc$issuer_ls180.v:3456$90 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "issuer_ls180.v:3639.3-3654.6" + process $proc$issuer_ls180.v:3639$76 + assign { } { } + assign { } { } + assign $0\ALU_dec31_dec_sub26_function_unit[11:0] $1\ALU_dec31_dec_sub26_function_unit[11:0] + attribute \src "issuer_ls180.v:3640.5-3640.29" + switch \initial + attribute \src "issuer_ls180.v:3640.9-3640.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\ALU_dec31_dec_sub26_function_unit[11:0] 12'000000000010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\ALU_dec31_dec_sub26_function_unit[11:0] 12'000000000010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\ALU_dec31_dec_sub26_function_unit[11:0] 12'000000000010 + case + assign $1\ALU_dec31_dec_sub26_function_unit[11:0] 12'000000000000 + end + sync always + update \ALU_dec31_dec_sub26_function_unit $0\ALU_dec31_dec_sub26_function_unit[11:0] + end + attribute \src "issuer_ls180.v:3655.3-3670.6" + process $proc$issuer_ls180.v:3655$77 + assign { } { } + assign { } { } + assign $0\ALU_dec31_dec_sub26_inv_a[0:0] $1\ALU_dec31_dec_sub26_inv_a[0:0] + attribute \src "issuer_ls180.v:3656.5-3656.29" + switch \initial + attribute \src "issuer_ls180.v:3656.9-3656.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\ALU_dec31_dec_sub26_inv_a[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\ALU_dec31_dec_sub26_inv_a[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\ALU_dec31_dec_sub26_inv_a[0:0] 1'0 + case + assign $1\ALU_dec31_dec_sub26_inv_a[0:0] 1'0 + end + sync always + update \ALU_dec31_dec_sub26_inv_a $0\ALU_dec31_dec_sub26_inv_a[0:0] + end + attribute \src "issuer_ls180.v:3671.3-3686.6" + process $proc$issuer_ls180.v:3671$78 + assign { } { } + assign { } { } + assign $0\ALU_dec31_dec_sub26_inv_out[0:0] $1\ALU_dec31_dec_sub26_inv_out[0:0] + attribute \src "issuer_ls180.v:3672.5-3672.29" + switch \initial + attribute \src "issuer_ls180.v:3672.9-3672.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\ALU_dec31_dec_sub26_inv_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\ALU_dec31_dec_sub26_inv_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\ALU_dec31_dec_sub26_inv_out[0:0] 1'0 + case + assign $1\ALU_dec31_dec_sub26_inv_out[0:0] 1'0 + end + sync always + update \ALU_dec31_dec_sub26_inv_out $0\ALU_dec31_dec_sub26_inv_out[0:0] + end + attribute \src "issuer_ls180.v:3687.3-3702.6" + process $proc$issuer_ls180.v:3687$79 + assign { } { } + assign { } { } + assign $0\ALU_dec31_dec_sub26_cry_out[0:0] $1\ALU_dec31_dec_sub26_cry_out[0:0] + attribute \src "issuer_ls180.v:3688.5-3688.29" + switch \initial + attribute \src "issuer_ls180.v:3688.9-3688.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\ALU_dec31_dec_sub26_cry_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\ALU_dec31_dec_sub26_cry_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\ALU_dec31_dec_sub26_cry_out[0:0] 1'0 + case + assign $1\ALU_dec31_dec_sub26_cry_out[0:0] 1'0 + end + sync always + update \ALU_dec31_dec_sub26_cry_out $0\ALU_dec31_dec_sub26_cry_out[0:0] + end + attribute \src "issuer_ls180.v:3703.3-3718.6" + process $proc$issuer_ls180.v:3703$80 + assign { } { } + assign { } { } + assign $0\ALU_dec31_dec_sub26_is_32b[0:0] $1\ALU_dec31_dec_sub26_is_32b[0:0] + attribute \src "issuer_ls180.v:3704.5-3704.29" + switch \initial + attribute \src "issuer_ls180.v:3704.9-3704.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\ALU_dec31_dec_sub26_is_32b[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\ALU_dec31_dec_sub26_is_32b[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\ALU_dec31_dec_sub26_is_32b[0:0] 1'0 + case + assign $1\ALU_dec31_dec_sub26_is_32b[0:0] 1'0 + end + sync always + update \ALU_dec31_dec_sub26_is_32b $0\ALU_dec31_dec_sub26_is_32b[0:0] + end + attribute \src "issuer_ls180.v:3719.3-3734.6" + process $proc$issuer_ls180.v:3719$81 + assign { } { } + assign { } { } + assign $0\ALU_dec31_dec_sub26_sgn[0:0] $1\ALU_dec31_dec_sub26_sgn[0:0] + attribute \src "issuer_ls180.v:3720.5-3720.29" + switch \initial + attribute \src "issuer_ls180.v:3720.9-3720.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\ALU_dec31_dec_sub26_sgn[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\ALU_dec31_dec_sub26_sgn[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\ALU_dec31_dec_sub26_sgn[0:0] 1'0 + case + assign $1\ALU_dec31_dec_sub26_sgn[0:0] 1'0 + end + sync always + update \ALU_dec31_dec_sub26_sgn $0\ALU_dec31_dec_sub26_sgn[0:0] + end + attribute \src "issuer_ls180.v:3735.3-3750.6" + process $proc$issuer_ls180.v:3735$82 + assign { } { } + assign { } { } + assign $0\ALU_dec31_dec_sub26_internal_op[6:0] $1\ALU_dec31_dec_sub26_internal_op[6:0] + attribute \src "issuer_ls180.v:3736.5-3736.29" + switch \initial + attribute \src "issuer_ls180.v:3736.9-3736.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\ALU_dec31_dec_sub26_internal_op[6:0] 7'0011111 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\ALU_dec31_dec_sub26_internal_op[6:0] 7'0011111 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\ALU_dec31_dec_sub26_internal_op[6:0] 7'0011111 + case + assign $1\ALU_dec31_dec_sub26_internal_op[6:0] 7'0000000 + end + sync always + update \ALU_dec31_dec_sub26_internal_op $0\ALU_dec31_dec_sub26_internal_op[6:0] + end + attribute \src "issuer_ls180.v:3751.3-3766.6" + process $proc$issuer_ls180.v:3751$83 + assign { } { } + assign { } { } + assign $0\ALU_dec31_dec_sub26_in1_sel[2:0] $1\ALU_dec31_dec_sub26_in1_sel[2:0] + attribute \src "issuer_ls180.v:3752.5-3752.29" + switch \initial + attribute \src "issuer_ls180.v:3752.9-3752.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\ALU_dec31_dec_sub26_in1_sel[2:0] 3'100 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\ALU_dec31_dec_sub26_in1_sel[2:0] 3'100 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\ALU_dec31_dec_sub26_in1_sel[2:0] 3'100 + case + assign $1\ALU_dec31_dec_sub26_in1_sel[2:0] 3'000 + end + sync always + update \ALU_dec31_dec_sub26_in1_sel $0\ALU_dec31_dec_sub26_in1_sel[2:0] + end + attribute \src "issuer_ls180.v:3767.3-3782.6" + process $proc$issuer_ls180.v:3767$84 + assign { } { } + assign { } { } + assign $0\ALU_dec31_dec_sub26_in2_sel[3:0] $1\ALU_dec31_dec_sub26_in2_sel[3:0] + attribute \src "issuer_ls180.v:3768.5-3768.29" + switch \initial + attribute \src "issuer_ls180.v:3768.9-3768.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\ALU_dec31_dec_sub26_in2_sel[3:0] 4'0000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\ALU_dec31_dec_sub26_in2_sel[3:0] 4'0000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\ALU_dec31_dec_sub26_in2_sel[3:0] 4'0000 + case + assign $1\ALU_dec31_dec_sub26_in2_sel[3:0] 4'0000 + end + sync always + update \ALU_dec31_dec_sub26_in2_sel $0\ALU_dec31_dec_sub26_in2_sel[3:0] + end + attribute \src "issuer_ls180.v:3783.3-3798.6" + process $proc$issuer_ls180.v:3783$85 + assign { } { } + assign { } { } + assign $0\ALU_dec31_dec_sub26_cr_in[2:0] $1\ALU_dec31_dec_sub26_cr_in[2:0] + attribute \src "issuer_ls180.v:3784.5-3784.29" + switch \initial + attribute \src "issuer_ls180.v:3784.9-3784.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\ALU_dec31_dec_sub26_cr_in[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\ALU_dec31_dec_sub26_cr_in[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\ALU_dec31_dec_sub26_cr_in[2:0] 3'000 + case + assign $1\ALU_dec31_dec_sub26_cr_in[2:0] 3'000 + end + sync always + update \ALU_dec31_dec_sub26_cr_in $0\ALU_dec31_dec_sub26_cr_in[2:0] + end + attribute \src "issuer_ls180.v:3799.3-3814.6" + process $proc$issuer_ls180.v:3799$86 + assign { } { } + assign { } { } + assign $0\ALU_dec31_dec_sub26_cr_out[2:0] $1\ALU_dec31_dec_sub26_cr_out[2:0] + attribute \src "issuer_ls180.v:3800.5-3800.29" + switch \initial + attribute \src "issuer_ls180.v:3800.9-3800.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\ALU_dec31_dec_sub26_cr_out[2:0] 3'001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\ALU_dec31_dec_sub26_cr_out[2:0] 3'001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\ALU_dec31_dec_sub26_cr_out[2:0] 3'001 + case + assign $1\ALU_dec31_dec_sub26_cr_out[2:0] 3'000 + end + sync always + update \ALU_dec31_dec_sub26_cr_out $0\ALU_dec31_dec_sub26_cr_out[2:0] + end + attribute \src "issuer_ls180.v:3815.3-3830.6" + process $proc$issuer_ls180.v:3815$87 + assign { } { } + assign { } { } + assign $0\ALU_dec31_dec_sub26_ldst_len[3:0] $1\ALU_dec31_dec_sub26_ldst_len[3:0] + attribute \src "issuer_ls180.v:3816.5-3816.29" + switch \initial + attribute \src "issuer_ls180.v:3816.9-3816.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\ALU_dec31_dec_sub26_ldst_len[3:0] 4'0001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\ALU_dec31_dec_sub26_ldst_len[3:0] 4'0010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\ALU_dec31_dec_sub26_ldst_len[3:0] 4'0100 + case + assign $1\ALU_dec31_dec_sub26_ldst_len[3:0] 4'0000 + end + sync always + update \ALU_dec31_dec_sub26_ldst_len $0\ALU_dec31_dec_sub26_ldst_len[3:0] + end + attribute \src "issuer_ls180.v:3831.3-3846.6" + process $proc$issuer_ls180.v:3831$88 + assign { } { } + assign { } { } + assign $0\ALU_dec31_dec_sub26_rc_sel[1:0] $1\ALU_dec31_dec_sub26_rc_sel[1:0] + attribute \src "issuer_ls180.v:3832.5-3832.29" + switch \initial + attribute \src "issuer_ls180.v:3832.9-3832.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\ALU_dec31_dec_sub26_rc_sel[1:0] 2'10 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\ALU_dec31_dec_sub26_rc_sel[1:0] 2'10 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\ALU_dec31_dec_sub26_rc_sel[1:0] 2'10 + case + assign $1\ALU_dec31_dec_sub26_rc_sel[1:0] 2'00 + end + sync always + update \ALU_dec31_dec_sub26_rc_sel $0\ALU_dec31_dec_sub26_rc_sel[1:0] + end + attribute \src "issuer_ls180.v:3847.3-3862.6" + process $proc$issuer_ls180.v:3847$89 + assign { } { } + assign { } { } + assign $0\ALU_dec31_dec_sub26_cry_in[1:0] $1\ALU_dec31_dec_sub26_cry_in[1:0] + attribute \src "issuer_ls180.v:3848.5-3848.29" + switch \initial + attribute \src "issuer_ls180.v:3848.9-3848.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\ALU_dec31_dec_sub26_cry_in[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\ALU_dec31_dec_sub26_cry_in[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\ALU_dec31_dec_sub26_cry_in[1:0] 2'00 + case + assign $1\ALU_dec31_dec_sub26_cry_in[1:0] 2'00 + end + sync always + update \ALU_dec31_dec_sub26_cry_in $0\ALU_dec31_dec_sub26_cry_in[1:0] + end + connect \opcode_switch \opcode_in [10:6] +end +attribute \src "issuer_ls180.v:3868.1-4655.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.dec_ALU.dec.ALU_dec31.ALU_dec31_dec_sub8" +attribute \generator "nMigen" +module \ALU_dec31_dec_sub8 + attribute \src "issuer_ls180.v:4439.3-4481.6" + wire width 3 $0\ALU_dec31_dec_sub8_cr_in[2:0] + attribute \src "issuer_ls180.v:4482.3-4524.6" + wire width 3 $0\ALU_dec31_dec_sub8_cr_out[2:0] + attribute \src "issuer_ls180.v:4611.3-4653.6" + wire width 2 $0\ALU_dec31_dec_sub8_cry_in[1:0] + attribute \src "issuer_ls180.v:4181.3-4223.6" + wire $0\ALU_dec31_dec_sub8_cry_out[0:0] + attribute \src "issuer_ls180.v:4052.3-4094.6" + wire width 12 $0\ALU_dec31_dec_sub8_function_unit[11:0] + attribute \src "issuer_ls180.v:4353.3-4395.6" + wire width 3 $0\ALU_dec31_dec_sub8_in1_sel[2:0] + attribute \src "issuer_ls180.v:4396.3-4438.6" + wire width 4 $0\ALU_dec31_dec_sub8_in2_sel[3:0] + attribute \src "issuer_ls180.v:4310.3-4352.6" + wire width 7 $0\ALU_dec31_dec_sub8_internal_op[6:0] + attribute \src "issuer_ls180.v:4095.3-4137.6" + wire $0\ALU_dec31_dec_sub8_inv_a[0:0] + attribute \src "issuer_ls180.v:4138.3-4180.6" + wire $0\ALU_dec31_dec_sub8_inv_out[0:0] + attribute \src "issuer_ls180.v:4224.3-4266.6" + wire $0\ALU_dec31_dec_sub8_is_32b[0:0] + attribute \src "issuer_ls180.v:4525.3-4567.6" + wire width 4 $0\ALU_dec31_dec_sub8_ldst_len[3:0] + attribute \src "issuer_ls180.v:4568.3-4610.6" + wire width 2 $0\ALU_dec31_dec_sub8_rc_sel[1:0] + attribute \src "issuer_ls180.v:4267.3-4309.6" + wire $0\ALU_dec31_dec_sub8_sgn[0:0] + attribute \src "issuer_ls180.v:3869.7-3869.20" + wire $0\initial[0:0] + attribute \src "issuer_ls180.v:4439.3-4481.6" + wire width 3 $1\ALU_dec31_dec_sub8_cr_in[2:0] + attribute \src "issuer_ls180.v:4482.3-4524.6" + wire width 3 $1\ALU_dec31_dec_sub8_cr_out[2:0] + attribute \src "issuer_ls180.v:4611.3-4653.6" + wire width 2 $1\ALU_dec31_dec_sub8_cry_in[1:0] + attribute \src "issuer_ls180.v:4181.3-4223.6" + wire $1\ALU_dec31_dec_sub8_cry_out[0:0] + attribute \src "issuer_ls180.v:4052.3-4094.6" + wire width 12 $1\ALU_dec31_dec_sub8_function_unit[11:0] + attribute \src "issuer_ls180.v:4353.3-4395.6" + wire width 3 $1\ALU_dec31_dec_sub8_in1_sel[2:0] + attribute \src "issuer_ls180.v:4396.3-4438.6" + wire width 4 $1\ALU_dec31_dec_sub8_in2_sel[3:0] + attribute \src "issuer_ls180.v:4310.3-4352.6" + wire width 7 $1\ALU_dec31_dec_sub8_internal_op[6:0] + attribute \src "issuer_ls180.v:4095.3-4137.6" + wire $1\ALU_dec31_dec_sub8_inv_a[0:0] + attribute \src "issuer_ls180.v:4138.3-4180.6" + wire $1\ALU_dec31_dec_sub8_inv_out[0:0] + attribute \src "issuer_ls180.v:4224.3-4266.6" + wire $1\ALU_dec31_dec_sub8_is_32b[0:0] + attribute \src "issuer_ls180.v:4525.3-4567.6" + wire width 4 $1\ALU_dec31_dec_sub8_ldst_len[3:0] + attribute \src "issuer_ls180.v:4568.3-4610.6" + wire width 2 $1\ALU_dec31_dec_sub8_rc_sel[1:0] + attribute \src "issuer_ls180.v:4267.3-4309.6" + wire $1\ALU_dec31_dec_sub8_sgn[0:0] + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 5 \ALU_dec31_dec_sub8_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 6 \ALU_dec31_dec_sub8_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 9 \ALU_dec31_dec_sub8_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 12 \ALU_dec31_dec_sub8_cry_out + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 12 output 1 \ALU_dec31_dec_sub8_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 3 \ALU_dec31_dec_sub8_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 output 4 \ALU_dec31_dec_sub8_in2_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 7 output 2 \ALU_dec31_dec_sub8_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 10 \ALU_dec31_dec_sub8_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 11 \ALU_dec31_dec_sub8_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 13 \ALU_dec31_dec_sub8_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 output 7 \ALU_dec31_dec_sub8_ldst_len + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 8 \ALU_dec31_dec_sub8_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 14 \ALU_dec31_dec_sub8_sgn + attribute \src "issuer_ls180.v:3869.7-3869.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + wire width 32 input 15 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:320" + wire width 5 \opcode_switch + attribute \src "issuer_ls180.v:3869.7-3869.20" + process $proc$issuer_ls180.v:3869$105 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "issuer_ls180.v:4052.3-4094.6" + process $proc$issuer_ls180.v:4052$91 + assign { } { } + assign { } { } + assign $0\ALU_dec31_dec_sub8_function_unit[11:0] $1\ALU_dec31_dec_sub8_function_unit[11:0] + attribute \src "issuer_ls180.v:4053.5-4053.29" + switch \initial + attribute \src "issuer_ls180.v:4053.9-4053.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\ALU_dec31_dec_sub8_function_unit[11:0] 12'000000000010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\ALU_dec31_dec_sub8_function_unit[11:0] 12'000000000010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\ALU_dec31_dec_sub8_function_unit[11:0] 12'000000000010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\ALU_dec31_dec_sub8_function_unit[11:0] 12'000000000010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\ALU_dec31_dec_sub8_function_unit[11:0] 12'000000000010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\ALU_dec31_dec_sub8_function_unit[11:0] 12'000000000010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\ALU_dec31_dec_sub8_function_unit[11:0] 12'000000000010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\ALU_dec31_dec_sub8_function_unit[11:0] 12'000000000010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\ALU_dec31_dec_sub8_function_unit[11:0] 12'000000000010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\ALU_dec31_dec_sub8_function_unit[11:0] 12'000000000010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\ALU_dec31_dec_sub8_function_unit[11:0] 12'000000000010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\ALU_dec31_dec_sub8_function_unit[11:0] 12'000000000010 + case + assign $1\ALU_dec31_dec_sub8_function_unit[11:0] 12'000000000000 + end + sync always + update \ALU_dec31_dec_sub8_function_unit $0\ALU_dec31_dec_sub8_function_unit[11:0] + end + attribute \src "issuer_ls180.v:4095.3-4137.6" + process $proc$issuer_ls180.v:4095$92 + assign { } { } + assign { } { } + assign $0\ALU_dec31_dec_sub8_inv_a[0:0] $1\ALU_dec31_dec_sub8_inv_a[0:0] + attribute \src "issuer_ls180.v:4096.5-4096.29" + switch \initial + attribute \src "issuer_ls180.v:4096.9-4096.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\ALU_dec31_dec_sub8_inv_a[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\ALU_dec31_dec_sub8_inv_a[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\ALU_dec31_dec_sub8_inv_a[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\ALU_dec31_dec_sub8_inv_a[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\ALU_dec31_dec_sub8_inv_a[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\ALU_dec31_dec_sub8_inv_a[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\ALU_dec31_dec_sub8_inv_a[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\ALU_dec31_dec_sub8_inv_a[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\ALU_dec31_dec_sub8_inv_a[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\ALU_dec31_dec_sub8_inv_a[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\ALU_dec31_dec_sub8_inv_a[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\ALU_dec31_dec_sub8_inv_a[0:0] 1'1 + case + assign $1\ALU_dec31_dec_sub8_inv_a[0:0] 1'0 + end + sync always + update \ALU_dec31_dec_sub8_inv_a $0\ALU_dec31_dec_sub8_inv_a[0:0] + end + attribute \src "issuer_ls180.v:4138.3-4180.6" + process $proc$issuer_ls180.v:4138$93 + assign { } { } + assign { } { } + assign $0\ALU_dec31_dec_sub8_inv_out[0:0] $1\ALU_dec31_dec_sub8_inv_out[0:0] + attribute \src "issuer_ls180.v:4139.5-4139.29" + switch \initial + attribute \src "issuer_ls180.v:4139.9-4139.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\ALU_dec31_dec_sub8_inv_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\ALU_dec31_dec_sub8_inv_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\ALU_dec31_dec_sub8_inv_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\ALU_dec31_dec_sub8_inv_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\ALU_dec31_dec_sub8_inv_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\ALU_dec31_dec_sub8_inv_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\ALU_dec31_dec_sub8_inv_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\ALU_dec31_dec_sub8_inv_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\ALU_dec31_dec_sub8_inv_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\ALU_dec31_dec_sub8_inv_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\ALU_dec31_dec_sub8_inv_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\ALU_dec31_dec_sub8_inv_out[0:0] 1'0 + case + assign $1\ALU_dec31_dec_sub8_inv_out[0:0] 1'0 + end + sync always + update \ALU_dec31_dec_sub8_inv_out $0\ALU_dec31_dec_sub8_inv_out[0:0] + end + attribute \src "issuer_ls180.v:4181.3-4223.6" + process $proc$issuer_ls180.v:4181$94 + assign { } { } + assign { } { } + assign $0\ALU_dec31_dec_sub8_cry_out[0:0] $1\ALU_dec31_dec_sub8_cry_out[0:0] + attribute \src "issuer_ls180.v:4182.5-4182.29" + switch \initial + attribute \src "issuer_ls180.v:4182.9-4182.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\ALU_dec31_dec_sub8_cry_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\ALU_dec31_dec_sub8_cry_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\ALU_dec31_dec_sub8_cry_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\ALU_dec31_dec_sub8_cry_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\ALU_dec31_dec_sub8_cry_out[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\ALU_dec31_dec_sub8_cry_out[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\ALU_dec31_dec_sub8_cry_out[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\ALU_dec31_dec_sub8_cry_out[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\ALU_dec31_dec_sub8_cry_out[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\ALU_dec31_dec_sub8_cry_out[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\ALU_dec31_dec_sub8_cry_out[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\ALU_dec31_dec_sub8_cry_out[0:0] 1'1 + case + assign $1\ALU_dec31_dec_sub8_cry_out[0:0] 1'0 + end + sync always + update \ALU_dec31_dec_sub8_cry_out $0\ALU_dec31_dec_sub8_cry_out[0:0] + end + attribute \src "issuer_ls180.v:4224.3-4266.6" + process $proc$issuer_ls180.v:4224$95 + assign { } { } + assign { } { } + assign $0\ALU_dec31_dec_sub8_is_32b[0:0] $1\ALU_dec31_dec_sub8_is_32b[0:0] + attribute \src "issuer_ls180.v:4225.5-4225.29" + switch \initial + attribute \src "issuer_ls180.v:4225.9-4225.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\ALU_dec31_dec_sub8_is_32b[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\ALU_dec31_dec_sub8_is_32b[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\ALU_dec31_dec_sub8_is_32b[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\ALU_dec31_dec_sub8_is_32b[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\ALU_dec31_dec_sub8_is_32b[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\ALU_dec31_dec_sub8_is_32b[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\ALU_dec31_dec_sub8_is_32b[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\ALU_dec31_dec_sub8_is_32b[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\ALU_dec31_dec_sub8_is_32b[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\ALU_dec31_dec_sub8_is_32b[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\ALU_dec31_dec_sub8_is_32b[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\ALU_dec31_dec_sub8_is_32b[0:0] 1'0 + case + assign $1\ALU_dec31_dec_sub8_is_32b[0:0] 1'0 + end + sync always + update \ALU_dec31_dec_sub8_is_32b $0\ALU_dec31_dec_sub8_is_32b[0:0] + end + attribute \src "issuer_ls180.v:4267.3-4309.6" + process $proc$issuer_ls180.v:4267$96 + assign { } { } + assign { } { } + assign $0\ALU_dec31_dec_sub8_sgn[0:0] $1\ALU_dec31_dec_sub8_sgn[0:0] + attribute \src "issuer_ls180.v:4268.5-4268.29" + switch \initial + attribute \src "issuer_ls180.v:4268.9-4268.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\ALU_dec31_dec_sub8_sgn[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\ALU_dec31_dec_sub8_sgn[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\ALU_dec31_dec_sub8_sgn[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\ALU_dec31_dec_sub8_sgn[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\ALU_dec31_dec_sub8_sgn[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\ALU_dec31_dec_sub8_sgn[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\ALU_dec31_dec_sub8_sgn[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\ALU_dec31_dec_sub8_sgn[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\ALU_dec31_dec_sub8_sgn[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\ALU_dec31_dec_sub8_sgn[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\ALU_dec31_dec_sub8_sgn[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\ALU_dec31_dec_sub8_sgn[0:0] 1'0 + case + assign $1\ALU_dec31_dec_sub8_sgn[0:0] 1'0 + end + sync always + update \ALU_dec31_dec_sub8_sgn $0\ALU_dec31_dec_sub8_sgn[0:0] + end + attribute \src "issuer_ls180.v:4310.3-4352.6" + process $proc$issuer_ls180.v:4310$97 + assign { } { } + assign { } { } + assign $0\ALU_dec31_dec_sub8_internal_op[6:0] $1\ALU_dec31_dec_sub8_internal_op[6:0] + attribute \src "issuer_ls180.v:4311.5-4311.29" + switch \initial + attribute \src "issuer_ls180.v:4311.9-4311.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\ALU_dec31_dec_sub8_internal_op[6:0] 7'0000010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\ALU_dec31_dec_sub8_internal_op[6:0] 7'0000010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\ALU_dec31_dec_sub8_internal_op[6:0] 7'0000010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\ALU_dec31_dec_sub8_internal_op[6:0] 7'0000010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\ALU_dec31_dec_sub8_internal_op[6:0] 7'0000010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\ALU_dec31_dec_sub8_internal_op[6:0] 7'0000010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\ALU_dec31_dec_sub8_internal_op[6:0] 7'0000010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\ALU_dec31_dec_sub8_internal_op[6:0] 7'0000010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\ALU_dec31_dec_sub8_internal_op[6:0] 7'0000010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\ALU_dec31_dec_sub8_internal_op[6:0] 7'0000010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\ALU_dec31_dec_sub8_internal_op[6:0] 7'0000010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\ALU_dec31_dec_sub8_internal_op[6:0] 7'0000010 + case + assign $1\ALU_dec31_dec_sub8_internal_op[6:0] 7'0000000 + end + sync always + update \ALU_dec31_dec_sub8_internal_op $0\ALU_dec31_dec_sub8_internal_op[6:0] + end + attribute \src "issuer_ls180.v:4353.3-4395.6" + process $proc$issuer_ls180.v:4353$98 + assign { } { } + assign { } { } + assign $0\ALU_dec31_dec_sub8_in1_sel[2:0] $1\ALU_dec31_dec_sub8_in1_sel[2:0] + attribute \src "issuer_ls180.v:4354.5-4354.29" + switch \initial + attribute \src "issuer_ls180.v:4354.9-4354.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\ALU_dec31_dec_sub8_in1_sel[2:0] 3'001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\ALU_dec31_dec_sub8_in1_sel[2:0] 3'001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\ALU_dec31_dec_sub8_in1_sel[2:0] 3'001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\ALU_dec31_dec_sub8_in1_sel[2:0] 3'001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\ALU_dec31_dec_sub8_in1_sel[2:0] 3'001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\ALU_dec31_dec_sub8_in1_sel[2:0] 3'001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\ALU_dec31_dec_sub8_in1_sel[2:0] 3'001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\ALU_dec31_dec_sub8_in1_sel[2:0] 3'001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\ALU_dec31_dec_sub8_in1_sel[2:0] 3'001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\ALU_dec31_dec_sub8_in1_sel[2:0] 3'001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\ALU_dec31_dec_sub8_in1_sel[2:0] 3'001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\ALU_dec31_dec_sub8_in1_sel[2:0] 3'001 + case + assign $1\ALU_dec31_dec_sub8_in1_sel[2:0] 3'000 + end + sync always + update \ALU_dec31_dec_sub8_in1_sel $0\ALU_dec31_dec_sub8_in1_sel[2:0] + end + attribute \src "issuer_ls180.v:4396.3-4438.6" + process $proc$issuer_ls180.v:4396$99 + assign { } { } + assign { } { } + assign $0\ALU_dec31_dec_sub8_in2_sel[3:0] $1\ALU_dec31_dec_sub8_in2_sel[3:0] + attribute \src "issuer_ls180.v:4397.5-4397.29" + switch \initial + attribute \src "issuer_ls180.v:4397.9-4397.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\ALU_dec31_dec_sub8_in2_sel[3:0] 4'0000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\ALU_dec31_dec_sub8_in2_sel[3:0] 4'0000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\ALU_dec31_dec_sub8_in2_sel[3:0] 4'0001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\ALU_dec31_dec_sub8_in2_sel[3:0] 4'0001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\ALU_dec31_dec_sub8_in2_sel[3:0] 4'0001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\ALU_dec31_dec_sub8_in2_sel[3:0] 4'0001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\ALU_dec31_dec_sub8_in2_sel[3:0] 4'0001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\ALU_dec31_dec_sub8_in2_sel[3:0] 4'0001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\ALU_dec31_dec_sub8_in2_sel[3:0] 4'1001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\ALU_dec31_dec_sub8_in2_sel[3:0] 4'1001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\ALU_dec31_dec_sub8_in2_sel[3:0] 4'0000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\ALU_dec31_dec_sub8_in2_sel[3:0] 4'0000 + case + assign $1\ALU_dec31_dec_sub8_in2_sel[3:0] 4'0000 + end + sync always + update \ALU_dec31_dec_sub8_in2_sel $0\ALU_dec31_dec_sub8_in2_sel[3:0] + end + attribute \src "issuer_ls180.v:4439.3-4481.6" + process $proc$issuer_ls180.v:4439$100 + assign { } { } + assign { } { } + assign $0\ALU_dec31_dec_sub8_cr_in[2:0] $1\ALU_dec31_dec_sub8_cr_in[2:0] + attribute \src "issuer_ls180.v:4440.5-4440.29" + switch \initial + attribute \src "issuer_ls180.v:4440.9-4440.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\ALU_dec31_dec_sub8_cr_in[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\ALU_dec31_dec_sub8_cr_in[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\ALU_dec31_dec_sub8_cr_in[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\ALU_dec31_dec_sub8_cr_in[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\ALU_dec31_dec_sub8_cr_in[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\ALU_dec31_dec_sub8_cr_in[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\ALU_dec31_dec_sub8_cr_in[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\ALU_dec31_dec_sub8_cr_in[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\ALU_dec31_dec_sub8_cr_in[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\ALU_dec31_dec_sub8_cr_in[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\ALU_dec31_dec_sub8_cr_in[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\ALU_dec31_dec_sub8_cr_in[2:0] 3'000 + case + assign $1\ALU_dec31_dec_sub8_cr_in[2:0] 3'000 + end + sync always + update \ALU_dec31_dec_sub8_cr_in $0\ALU_dec31_dec_sub8_cr_in[2:0] + end + attribute \src "issuer_ls180.v:4482.3-4524.6" + process $proc$issuer_ls180.v:4482$101 + assign { } { } + assign { } { } + assign $0\ALU_dec31_dec_sub8_cr_out[2:0] $1\ALU_dec31_dec_sub8_cr_out[2:0] + attribute \src "issuer_ls180.v:4483.5-4483.29" + switch \initial + attribute \src "issuer_ls180.v:4483.9-4483.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\ALU_dec31_dec_sub8_cr_out[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\ALU_dec31_dec_sub8_cr_out[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\ALU_dec31_dec_sub8_cr_out[2:0] 3'001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\ALU_dec31_dec_sub8_cr_out[2:0] 3'001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\ALU_dec31_dec_sub8_cr_out[2:0] 3'001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\ALU_dec31_dec_sub8_cr_out[2:0] 3'001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\ALU_dec31_dec_sub8_cr_out[2:0] 3'001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\ALU_dec31_dec_sub8_cr_out[2:0] 3'001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\ALU_dec31_dec_sub8_cr_out[2:0] 3'001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\ALU_dec31_dec_sub8_cr_out[2:0] 3'001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\ALU_dec31_dec_sub8_cr_out[2:0] 3'001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\ALU_dec31_dec_sub8_cr_out[2:0] 3'001 + case + assign $1\ALU_dec31_dec_sub8_cr_out[2:0] 3'000 + end + sync always + update \ALU_dec31_dec_sub8_cr_out $0\ALU_dec31_dec_sub8_cr_out[2:0] + end + attribute \src "issuer_ls180.v:4525.3-4567.6" + process $proc$issuer_ls180.v:4525$102 + assign { } { } + assign { } { } + assign $0\ALU_dec31_dec_sub8_ldst_len[3:0] $1\ALU_dec31_dec_sub8_ldst_len[3:0] + attribute \src "issuer_ls180.v:4526.5-4526.29" + switch \initial + attribute \src "issuer_ls180.v:4526.9-4526.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\ALU_dec31_dec_sub8_ldst_len[3:0] 4'0000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\ALU_dec31_dec_sub8_ldst_len[3:0] 4'0000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\ALU_dec31_dec_sub8_ldst_len[3:0] 4'0000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\ALU_dec31_dec_sub8_ldst_len[3:0] 4'0000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\ALU_dec31_dec_sub8_ldst_len[3:0] 4'0000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\ALU_dec31_dec_sub8_ldst_len[3:0] 4'0000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\ALU_dec31_dec_sub8_ldst_len[3:0] 4'0000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\ALU_dec31_dec_sub8_ldst_len[3:0] 4'0000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\ALU_dec31_dec_sub8_ldst_len[3:0] 4'0000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\ALU_dec31_dec_sub8_ldst_len[3:0] 4'0000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\ALU_dec31_dec_sub8_ldst_len[3:0] 4'0000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\ALU_dec31_dec_sub8_ldst_len[3:0] 4'0000 + case + assign $1\ALU_dec31_dec_sub8_ldst_len[3:0] 4'0000 + end + sync always + update \ALU_dec31_dec_sub8_ldst_len $0\ALU_dec31_dec_sub8_ldst_len[3:0] + end + attribute \src "issuer_ls180.v:4568.3-4610.6" + process $proc$issuer_ls180.v:4568$103 + assign { } { } + assign { } { } + assign $0\ALU_dec31_dec_sub8_rc_sel[1:0] $1\ALU_dec31_dec_sub8_rc_sel[1:0] + attribute \src "issuer_ls180.v:4569.5-4569.29" + switch \initial + attribute \src "issuer_ls180.v:4569.9-4569.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\ALU_dec31_dec_sub8_rc_sel[1:0] 2'10 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\ALU_dec31_dec_sub8_rc_sel[1:0] 2'10 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\ALU_dec31_dec_sub8_rc_sel[1:0] 2'10 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\ALU_dec31_dec_sub8_rc_sel[1:0] 2'10 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\ALU_dec31_dec_sub8_rc_sel[1:0] 2'10 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\ALU_dec31_dec_sub8_rc_sel[1:0] 2'10 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\ALU_dec31_dec_sub8_rc_sel[1:0] 2'10 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\ALU_dec31_dec_sub8_rc_sel[1:0] 2'10 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\ALU_dec31_dec_sub8_rc_sel[1:0] 2'10 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\ALU_dec31_dec_sub8_rc_sel[1:0] 2'10 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\ALU_dec31_dec_sub8_rc_sel[1:0] 2'10 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\ALU_dec31_dec_sub8_rc_sel[1:0] 2'10 + case + assign $1\ALU_dec31_dec_sub8_rc_sel[1:0] 2'00 + end + sync always + update \ALU_dec31_dec_sub8_rc_sel $0\ALU_dec31_dec_sub8_rc_sel[1:0] + end + attribute \src "issuer_ls180.v:4611.3-4653.6" + process $proc$issuer_ls180.v:4611$104 + assign { } { } + assign { } { } + assign $0\ALU_dec31_dec_sub8_cry_in[1:0] $1\ALU_dec31_dec_sub8_cry_in[1:0] + attribute \src "issuer_ls180.v:4612.5-4612.29" + switch \initial + attribute \src "issuer_ls180.v:4612.9-4612.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\ALU_dec31_dec_sub8_cry_in[1:0] 2'01 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\ALU_dec31_dec_sub8_cry_in[1:0] 2'01 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\ALU_dec31_dec_sub8_cry_in[1:0] 2'01 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\ALU_dec31_dec_sub8_cry_in[1:0] 2'01 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\ALU_dec31_dec_sub8_cry_in[1:0] 2'01 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\ALU_dec31_dec_sub8_cry_in[1:0] 2'01 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\ALU_dec31_dec_sub8_cry_in[1:0] 2'10 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\ALU_dec31_dec_sub8_cry_in[1:0] 2'10 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\ALU_dec31_dec_sub8_cry_in[1:0] 2'10 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\ALU_dec31_dec_sub8_cry_in[1:0] 2'10 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\ALU_dec31_dec_sub8_cry_in[1:0] 2'10 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\ALU_dec31_dec_sub8_cry_in[1:0] 2'10 + case + assign $1\ALU_dec31_dec_sub8_cry_in[1:0] 2'00 + end + sync always + update \ALU_dec31_dec_sub8_cry_in $0\ALU_dec31_dec_sub8_cry_in[1:0] + end + connect \opcode_switch \opcode_in [10:6] +end +attribute \src "issuer_ls180.v:4659.1-4938.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.dec_BRANCH.dec.BRANCH_dec19" +attribute \generator "nMigen" +module \BRANCH_dec19 + attribute \src "issuer_ls180.v:4857.3-4872.6" + wire width 3 $0\BRANCH_dec19_cr_in[2:0] + attribute \src "issuer_ls180.v:4873.3-4888.6" + wire width 3 $0\BRANCH_dec19_cr_out[2:0] + attribute \src "issuer_ls180.v:4809.3-4824.6" + wire width 12 $0\BRANCH_dec19_function_unit[11:0] + attribute \src "issuer_ls180.v:4841.3-4856.6" + wire width 4 $0\BRANCH_dec19_in2_sel[3:0] + attribute \src "issuer_ls180.v:4825.3-4840.6" + wire width 7 $0\BRANCH_dec19_internal_op[6:0] + attribute \src "issuer_ls180.v:4905.3-4920.6" + wire $0\BRANCH_dec19_is_32b[0:0] + attribute \src "issuer_ls180.v:4921.3-4936.6" + wire $0\BRANCH_dec19_lk[0:0] + attribute \src "issuer_ls180.v:4889.3-4904.6" + wire width 2 $0\BRANCH_dec19_rc_sel[1:0] + attribute \src "issuer_ls180.v:4660.7-4660.20" + wire $0\initial[0:0] + attribute \src "issuer_ls180.v:4857.3-4872.6" + wire width 3 $1\BRANCH_dec19_cr_in[2:0] + attribute \src "issuer_ls180.v:4873.3-4888.6" + wire width 3 $1\BRANCH_dec19_cr_out[2:0] + attribute \src "issuer_ls180.v:4809.3-4824.6" + wire width 12 $1\BRANCH_dec19_function_unit[11:0] + attribute \src "issuer_ls180.v:4841.3-4856.6" + wire width 4 $1\BRANCH_dec19_in2_sel[3:0] + attribute \src "issuer_ls180.v:4825.3-4840.6" + wire width 7 $1\BRANCH_dec19_internal_op[6:0] + attribute \src "issuer_ls180.v:4905.3-4920.6" + wire $1\BRANCH_dec19_is_32b[0:0] + attribute \src "issuer_ls180.v:4921.3-4936.6" + wire $1\BRANCH_dec19_lk[0:0] + attribute \src "issuer_ls180.v:4889.3-4904.6" + wire width 2 $1\BRANCH_dec19_rc_sel[1:0] + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 4 \BRANCH_dec19_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 5 \BRANCH_dec19_cr_out + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 12 output 1 \BRANCH_dec19_function_unit + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 output 3 \BRANCH_dec19_in2_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 7 output 2 \BRANCH_dec19_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 7 \BRANCH_dec19_is_32b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 8 \BRANCH_dec19_lk + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 6 \BRANCH_dec19_rc_sel + attribute \src "issuer_ls180.v:4660.7-4660.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + wire width 32 input 9 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:320" + wire width 10 \opcode_switch + attribute \src "issuer_ls180.v:4660.7-4660.20" + process $proc$issuer_ls180.v:4660$114 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "issuer_ls180.v:4809.3-4824.6" + process $proc$issuer_ls180.v:4809$106 + assign { } { } + assign { } { } + assign $0\BRANCH_dec19_function_unit[11:0] $1\BRANCH_dec19_function_unit[11:0] + attribute \src "issuer_ls180.v:4810.5-4810.29" + switch \initial + attribute \src "issuer_ls180.v:4810.9-4810.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'1000010000 + assign { } { } + assign $1\BRANCH_dec19_function_unit[11:0] 12'000000100000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0000010000 + assign { } { } + assign $1\BRANCH_dec19_function_unit[11:0] 12'000000100000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'1000110000 + assign { } { } + assign $1\BRANCH_dec19_function_unit[11:0] 12'000000100000 + case + assign $1\BRANCH_dec19_function_unit[11:0] 12'000000000000 + end + sync always + update \BRANCH_dec19_function_unit $0\BRANCH_dec19_function_unit[11:0] + end + attribute \src "issuer_ls180.v:4825.3-4840.6" + process $proc$issuer_ls180.v:4825$107 + assign { } { } + assign { } { } + assign $0\BRANCH_dec19_internal_op[6:0] $1\BRANCH_dec19_internal_op[6:0] + attribute \src "issuer_ls180.v:4826.5-4826.29" + switch \initial + attribute \src "issuer_ls180.v:4826.9-4826.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'1000010000 + assign { } { } + assign $1\BRANCH_dec19_internal_op[6:0] 7'0001000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0000010000 + assign { } { } + assign $1\BRANCH_dec19_internal_op[6:0] 7'0001000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'1000110000 + assign { } { } + assign $1\BRANCH_dec19_internal_op[6:0] 7'0001000 + case + assign $1\BRANCH_dec19_internal_op[6:0] 7'0000000 + end + sync always + update \BRANCH_dec19_internal_op $0\BRANCH_dec19_internal_op[6:0] + end + attribute \src "issuer_ls180.v:4841.3-4856.6" + process $proc$issuer_ls180.v:4841$108 + assign { } { } + assign { } { } + assign $0\BRANCH_dec19_in2_sel[3:0] $1\BRANCH_dec19_in2_sel[3:0] + attribute \src "issuer_ls180.v:4842.5-4842.29" + switch \initial + attribute \src "issuer_ls180.v:4842.9-4842.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'1000010000 + assign { } { } + assign $1\BRANCH_dec19_in2_sel[3:0] 4'1100 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0000010000 + assign { } { } + assign $1\BRANCH_dec19_in2_sel[3:0] 4'1100 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'1000110000 + assign { } { } + assign $1\BRANCH_dec19_in2_sel[3:0] 4'1100 + case + assign $1\BRANCH_dec19_in2_sel[3:0] 4'0000 + end + sync always + update \BRANCH_dec19_in2_sel $0\BRANCH_dec19_in2_sel[3:0] + end + attribute \src "issuer_ls180.v:4857.3-4872.6" + process $proc$issuer_ls180.v:4857$109 + assign { } { } + assign { } { } + assign $0\BRANCH_dec19_cr_in[2:0] $1\BRANCH_dec19_cr_in[2:0] + attribute \src "issuer_ls180.v:4858.5-4858.29" + switch \initial + attribute \src "issuer_ls180.v:4858.9-4858.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'1000010000 + assign { } { } + assign $1\BRANCH_dec19_cr_in[2:0] 3'010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0000010000 + assign { } { } + assign $1\BRANCH_dec19_cr_in[2:0] 3'010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'1000110000 + assign { } { } + assign $1\BRANCH_dec19_cr_in[2:0] 3'010 + case + assign $1\BRANCH_dec19_cr_in[2:0] 3'000 + end + sync always + update \BRANCH_dec19_cr_in $0\BRANCH_dec19_cr_in[2:0] + end + attribute \src "issuer_ls180.v:4873.3-4888.6" + process $proc$issuer_ls180.v:4873$110 + assign { } { } + assign { } { } + assign $0\BRANCH_dec19_cr_out[2:0] $1\BRANCH_dec19_cr_out[2:0] + attribute \src "issuer_ls180.v:4874.5-4874.29" + switch \initial + attribute \src "issuer_ls180.v:4874.9-4874.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'1000010000 + assign { } { } + assign $1\BRANCH_dec19_cr_out[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0000010000 + assign { } { } + assign $1\BRANCH_dec19_cr_out[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'1000110000 + assign { } { } + assign $1\BRANCH_dec19_cr_out[2:0] 3'000 + case + assign $1\BRANCH_dec19_cr_out[2:0] 3'000 + end + sync always + update \BRANCH_dec19_cr_out $0\BRANCH_dec19_cr_out[2:0] + end + attribute \src "issuer_ls180.v:4889.3-4904.6" + process $proc$issuer_ls180.v:4889$111 + assign { } { } + assign { } { } + assign $0\BRANCH_dec19_rc_sel[1:0] $1\BRANCH_dec19_rc_sel[1:0] + attribute \src "issuer_ls180.v:4890.5-4890.29" + switch \initial + attribute \src "issuer_ls180.v:4890.9-4890.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'1000010000 + assign { } { } + assign $1\BRANCH_dec19_rc_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0000010000 + assign { } { } + assign $1\BRANCH_dec19_rc_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'1000110000 + assign { } { } + assign $1\BRANCH_dec19_rc_sel[1:0] 2'00 + case + assign $1\BRANCH_dec19_rc_sel[1:0] 2'00 + end + sync always + update \BRANCH_dec19_rc_sel $0\BRANCH_dec19_rc_sel[1:0] + end + attribute \src "issuer_ls180.v:4905.3-4920.6" + process $proc$issuer_ls180.v:4905$112 + assign { } { } + assign { } { } + assign $0\BRANCH_dec19_is_32b[0:0] $1\BRANCH_dec19_is_32b[0:0] + attribute \src "issuer_ls180.v:4906.5-4906.29" + switch \initial + attribute \src "issuer_ls180.v:4906.9-4906.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'1000010000 + assign { } { } + assign $1\BRANCH_dec19_is_32b[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0000010000 + assign { } { } + assign $1\BRANCH_dec19_is_32b[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'1000110000 + assign { } { } + assign $1\BRANCH_dec19_is_32b[0:0] 1'0 + case + assign $1\BRANCH_dec19_is_32b[0:0] 1'0 + end + sync always + update \BRANCH_dec19_is_32b $0\BRANCH_dec19_is_32b[0:0] + end + attribute \src "issuer_ls180.v:4921.3-4936.6" + process $proc$issuer_ls180.v:4921$113 + assign { } { } + assign { } { } + assign $0\BRANCH_dec19_lk[0:0] $1\BRANCH_dec19_lk[0:0] + attribute \src "issuer_ls180.v:4922.5-4922.29" + switch \initial + attribute \src "issuer_ls180.v:4922.9-4922.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'1000010000 + assign { } { } + assign $1\BRANCH_dec19_lk[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0000010000 + assign { } { } + assign $1\BRANCH_dec19_lk[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'1000110000 + assign { } { } + assign $1\BRANCH_dec19_lk[0:0] 1'1 + case + assign $1\BRANCH_dec19_lk[0:0] 1'0 + end + sync always + update \BRANCH_dec19_lk $0\BRANCH_dec19_lk[0:0] + end + connect \opcode_switch \opcode_in [10:1] +end +attribute \src "issuer_ls180.v:4942.1-5239.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.dec_CR.dec.CR_dec19" +attribute \generator "nMigen" +module \CR_dec19 + attribute \src "issuer_ls180.v:5136.3-5169.6" + wire width 3 $0\CR_dec19_cr_in[2:0] + attribute \src "issuer_ls180.v:5170.3-5203.6" + wire width 3 $0\CR_dec19_cr_out[2:0] + attribute \src "issuer_ls180.v:5068.3-5101.6" + wire width 12 $0\CR_dec19_function_unit[11:0] + attribute \src "issuer_ls180.v:5102.3-5135.6" + wire width 7 $0\CR_dec19_internal_op[6:0] + attribute \src "issuer_ls180.v:5204.3-5237.6" + wire width 2 $0\CR_dec19_rc_sel[1:0] + attribute \src "issuer_ls180.v:4943.7-4943.20" + wire $0\initial[0:0] + attribute \src "issuer_ls180.v:5136.3-5169.6" + wire width 3 $1\CR_dec19_cr_in[2:0] + attribute \src "issuer_ls180.v:5170.3-5203.6" + wire width 3 $1\CR_dec19_cr_out[2:0] + attribute \src "issuer_ls180.v:5068.3-5101.6" + wire width 12 $1\CR_dec19_function_unit[11:0] + attribute \src "issuer_ls180.v:5102.3-5135.6" + wire width 7 $1\CR_dec19_internal_op[6:0] + attribute \src "issuer_ls180.v:5204.3-5237.6" + wire width 2 $1\CR_dec19_rc_sel[1:0] + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 3 \CR_dec19_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 4 \CR_dec19_cr_out + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 12 output 1 \CR_dec19_function_unit + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 7 output 2 \CR_dec19_internal_op + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 5 \CR_dec19_rc_sel + attribute \src "issuer_ls180.v:4943.7-4943.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + wire width 32 input 6 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:320" + wire width 10 \opcode_switch + attribute \src "issuer_ls180.v:4943.7-4943.20" + process $proc$issuer_ls180.v:4943$120 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "issuer_ls180.v:5068.3-5101.6" + process $proc$issuer_ls180.v:5068$115 + assign { } { } + assign { } { } + assign $0\CR_dec19_function_unit[11:0] $1\CR_dec19_function_unit[11:0] + attribute \src "issuer_ls180.v:5069.5-5069.29" + switch \initial + attribute \src "issuer_ls180.v:5069.9-5069.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0000000000 + assign { } { } + assign $1\CR_dec19_function_unit[11:0] 12'000001000000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0100000001 + assign { } { } + assign $1\CR_dec19_function_unit[11:0] 12'000001000000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0010000001 + assign { } { } + assign $1\CR_dec19_function_unit[11:0] 12'000001000000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0100100001 + assign { } { } + assign $1\CR_dec19_function_unit[11:0] 12'000001000000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0011100001 + assign { } { } + assign $1\CR_dec19_function_unit[11:0] 12'000001000000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0000100001 + assign { } { } + assign $1\CR_dec19_function_unit[11:0] 12'000001000000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0111000001 + assign { } { } + assign $1\CR_dec19_function_unit[11:0] 12'000001000000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0110100001 + assign { } { } + assign $1\CR_dec19_function_unit[11:0] 12'000001000000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0011000001 + assign { } { } + assign $1\CR_dec19_function_unit[11:0] 12'000001000000 + case + assign $1\CR_dec19_function_unit[11:0] 12'000000000000 + end + sync always + update \CR_dec19_function_unit $0\CR_dec19_function_unit[11:0] + end + attribute \src "issuer_ls180.v:5102.3-5135.6" + process $proc$issuer_ls180.v:5102$116 + assign { } { } + assign { } { } + assign $0\CR_dec19_internal_op[6:0] $1\CR_dec19_internal_op[6:0] + attribute \src "issuer_ls180.v:5103.5-5103.29" + switch \initial + attribute \src "issuer_ls180.v:5103.9-5103.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0000000000 + assign { } { } + assign $1\CR_dec19_internal_op[6:0] 7'0101010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0100000001 + assign { } { } + assign $1\CR_dec19_internal_op[6:0] 7'1000101 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0010000001 + assign { } { } + assign $1\CR_dec19_internal_op[6:0] 7'1000101 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0100100001 + assign { } { } + assign $1\CR_dec19_internal_op[6:0] 7'1000101 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0011100001 + assign { } { } + assign $1\CR_dec19_internal_op[6:0] 7'1000101 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0000100001 + assign { } { } + assign $1\CR_dec19_internal_op[6:0] 7'1000101 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0111000001 + assign { } { } + assign $1\CR_dec19_internal_op[6:0] 7'1000101 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0110100001 + assign { } { } + assign $1\CR_dec19_internal_op[6:0] 7'1000101 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0011000001 + assign { } { } + assign $1\CR_dec19_internal_op[6:0] 7'1000101 + case + assign $1\CR_dec19_internal_op[6:0] 7'0000000 + end + sync always + update \CR_dec19_internal_op $0\CR_dec19_internal_op[6:0] + end + attribute \src "issuer_ls180.v:5136.3-5169.6" + process $proc$issuer_ls180.v:5136$117 + assign { } { } + assign { } { } + assign $0\CR_dec19_cr_in[2:0] $1\CR_dec19_cr_in[2:0] + attribute \src "issuer_ls180.v:5137.5-5137.29" + switch \initial + attribute \src "issuer_ls180.v:5137.9-5137.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0000000000 + assign { } { } + assign $1\CR_dec19_cr_in[2:0] 3'011 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0100000001 + assign { } { } + assign $1\CR_dec19_cr_in[2:0] 3'100 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0010000001 + assign { } { } + assign $1\CR_dec19_cr_in[2:0] 3'100 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0100100001 + assign { } { } + assign $1\CR_dec19_cr_in[2:0] 3'100 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0011100001 + assign { } { } + assign $1\CR_dec19_cr_in[2:0] 3'100 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0000100001 + assign { } { } + assign $1\CR_dec19_cr_in[2:0] 3'100 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0111000001 + assign { } { } + assign $1\CR_dec19_cr_in[2:0] 3'100 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0110100001 + assign { } { } + assign $1\CR_dec19_cr_in[2:0] 3'100 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0011000001 + assign { } { } + assign $1\CR_dec19_cr_in[2:0] 3'100 + case + assign $1\CR_dec19_cr_in[2:0] 3'000 + end + sync always + update \CR_dec19_cr_in $0\CR_dec19_cr_in[2:0] + end + attribute \src "issuer_ls180.v:5170.3-5203.6" + process $proc$issuer_ls180.v:5170$118 + assign { } { } + assign { } { } + assign $0\CR_dec19_cr_out[2:0] $1\CR_dec19_cr_out[2:0] + attribute \src "issuer_ls180.v:5171.5-5171.29" + switch \initial + attribute \src "issuer_ls180.v:5171.9-5171.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0000000000 + assign { } { } + assign $1\CR_dec19_cr_out[2:0] 3'010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0100000001 + assign { } { } + assign $1\CR_dec19_cr_out[2:0] 3'011 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0010000001 + assign { } { } + assign $1\CR_dec19_cr_out[2:0] 3'011 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0100100001 + assign { } { } + assign $1\CR_dec19_cr_out[2:0] 3'011 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0011100001 + assign { } { } + assign $1\CR_dec19_cr_out[2:0] 3'011 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0000100001 + assign { } { } + assign $1\CR_dec19_cr_out[2:0] 3'011 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0111000001 + assign { } { } + assign $1\CR_dec19_cr_out[2:0] 3'011 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0110100001 + assign { } { } + assign $1\CR_dec19_cr_out[2:0] 3'011 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0011000001 + assign { } { } + assign $1\CR_dec19_cr_out[2:0] 3'011 + case + assign $1\CR_dec19_cr_out[2:0] 3'000 + end + sync always + update \CR_dec19_cr_out $0\CR_dec19_cr_out[2:0] + end + attribute \src "issuer_ls180.v:5204.3-5237.6" + process $proc$issuer_ls180.v:5204$119 + assign { } { } + assign { } { } + assign $0\CR_dec19_rc_sel[1:0] $1\CR_dec19_rc_sel[1:0] + attribute \src "issuer_ls180.v:5205.5-5205.29" + switch \initial + attribute \src "issuer_ls180.v:5205.9-5205.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0000000000 + assign { } { } + assign $1\CR_dec19_rc_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0100000001 + assign { } { } + assign $1\CR_dec19_rc_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0010000001 + assign { } { } + assign $1\CR_dec19_rc_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0100100001 + assign { } { } + assign $1\CR_dec19_rc_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0011100001 + assign { } { } + assign $1\CR_dec19_rc_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0000100001 + assign { } { } + assign $1\CR_dec19_rc_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0111000001 + assign { } { } + assign $1\CR_dec19_rc_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0110100001 + assign { } { } + assign $1\CR_dec19_rc_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0011000001 + assign { } { } + assign $1\CR_dec19_rc_sel[1:0] 2'00 + case + assign $1\CR_dec19_rc_sel[1:0] 2'00 + end + sync always + update \CR_dec19_rc_sel $0\CR_dec19_rc_sel[1:0] + end + connect \opcode_switch \opcode_in [10:1] +end +attribute \src "issuer_ls180.v:5243.1-5972.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.dec_CR.dec.CR_dec31" +attribute \generator "nMigen" +module \CR_dec31 + attribute \src "issuer_ls180.v:5928.3-5946.6" + wire width 3 $0\CR_dec31_cr_in[2:0] + attribute \src "issuer_ls180.v:5947.3-5965.6" + wire width 3 $0\CR_dec31_cr_out[2:0] + attribute \src "issuer_ls180.v:5890.3-5908.6" + wire width 12 $0\CR_dec31_function_unit[11:0] + attribute \src "issuer_ls180.v:5909.3-5927.6" + wire width 7 $0\CR_dec31_internal_op[6:0] + attribute \src "issuer_ls180.v:5871.3-5889.6" + wire width 2 $0\CR_dec31_rc_sel[1:0] + attribute \src "issuer_ls180.v:5244.7-5244.20" + wire $0\initial[0:0] + attribute \src "issuer_ls180.v:5928.3-5946.6" + wire width 3 $1\CR_dec31_cr_in[2:0] + attribute \src "issuer_ls180.v:5947.3-5965.6" + wire width 3 $1\CR_dec31_cr_out[2:0] + attribute \src "issuer_ls180.v:5890.3-5908.6" + wire width 12 $1\CR_dec31_function_unit[11:0] + attribute \src "issuer_ls180.v:5909.3-5927.6" + wire width 7 $1\CR_dec31_internal_op[6:0] + attribute \src "issuer_ls180.v:5871.3-5889.6" + wire width 2 $1\CR_dec31_rc_sel[1:0] + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 3 \CR_dec31_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 4 \CR_dec31_cr_out + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 \CR_dec31_dec_sub0_CR_dec31_dec_sub0_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 \CR_dec31_dec_sub0_CR_dec31_dec_sub0_cr_out + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 12 \CR_dec31_dec_sub0_CR_dec31_dec_sub0_function_unit + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 7 \CR_dec31_dec_sub0_CR_dec31_dec_sub0_internal_op + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \CR_dec31_dec_sub0_CR_dec31_dec_sub0_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + wire width 32 \CR_dec31_dec_sub0_opcode_in + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 \CR_dec31_dec_sub15_CR_dec31_dec_sub15_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 \CR_dec31_dec_sub15_CR_dec31_dec_sub15_cr_out + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 12 \CR_dec31_dec_sub15_CR_dec31_dec_sub15_function_unit + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 7 \CR_dec31_dec_sub15_CR_dec31_dec_sub15_internal_op + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \CR_dec31_dec_sub15_CR_dec31_dec_sub15_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + wire width 32 \CR_dec31_dec_sub15_opcode_in + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 \CR_dec31_dec_sub16_CR_dec31_dec_sub16_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 \CR_dec31_dec_sub16_CR_dec31_dec_sub16_cr_out + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 12 \CR_dec31_dec_sub16_CR_dec31_dec_sub16_function_unit + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 7 \CR_dec31_dec_sub16_CR_dec31_dec_sub16_internal_op + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \CR_dec31_dec_sub16_CR_dec31_dec_sub16_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + wire width 32 \CR_dec31_dec_sub16_opcode_in + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 \CR_dec31_dec_sub19_CR_dec31_dec_sub19_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 \CR_dec31_dec_sub19_CR_dec31_dec_sub19_cr_out + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 12 \CR_dec31_dec_sub19_CR_dec31_dec_sub19_function_unit + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 7 \CR_dec31_dec_sub19_CR_dec31_dec_sub19_internal_op + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \CR_dec31_dec_sub19_CR_dec31_dec_sub19_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + wire width 32 \CR_dec31_dec_sub19_opcode_in + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 12 output 1 \CR_dec31_function_unit + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 7 output 2 \CR_dec31_internal_op + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 5 \CR_dec31_rc_sel + attribute \src "issuer_ls180.v:5244.7-5244.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:326" + wire width 5 \opc_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + wire width 32 input 6 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:320" + wire width 10 \opcode_switch + attribute \module_not_derived 1 + attribute \src "issuer_ls180.v:5839.21-5846.4" + cell \CR_dec31_dec_sub0 \CR_dec31_dec_sub0 + connect \CR_dec31_dec_sub0_cr_in \CR_dec31_dec_sub0_CR_dec31_dec_sub0_cr_in + connect \CR_dec31_dec_sub0_cr_out \CR_dec31_dec_sub0_CR_dec31_dec_sub0_cr_out + connect \CR_dec31_dec_sub0_function_unit \CR_dec31_dec_sub0_CR_dec31_dec_sub0_function_unit + connect \CR_dec31_dec_sub0_internal_op \CR_dec31_dec_sub0_CR_dec31_dec_sub0_internal_op + connect \CR_dec31_dec_sub0_rc_sel \CR_dec31_dec_sub0_CR_dec31_dec_sub0_rc_sel + connect \opcode_in \CR_dec31_dec_sub0_opcode_in + end + attribute \module_not_derived 1 + attribute \src "issuer_ls180.v:5847.22-5854.4" + cell \CR_dec31_dec_sub15 \CR_dec31_dec_sub15 + connect \CR_dec31_dec_sub15_cr_in \CR_dec31_dec_sub15_CR_dec31_dec_sub15_cr_in + connect \CR_dec31_dec_sub15_cr_out \CR_dec31_dec_sub15_CR_dec31_dec_sub15_cr_out + connect \CR_dec31_dec_sub15_function_unit \CR_dec31_dec_sub15_CR_dec31_dec_sub15_function_unit + connect \CR_dec31_dec_sub15_internal_op \CR_dec31_dec_sub15_CR_dec31_dec_sub15_internal_op + connect \CR_dec31_dec_sub15_rc_sel \CR_dec31_dec_sub15_CR_dec31_dec_sub15_rc_sel + connect \opcode_in \CR_dec31_dec_sub15_opcode_in + end + attribute \module_not_derived 1 + attribute \src "issuer_ls180.v:5855.22-5862.4" + cell \CR_dec31_dec_sub16 \CR_dec31_dec_sub16 + connect \CR_dec31_dec_sub16_cr_in \CR_dec31_dec_sub16_CR_dec31_dec_sub16_cr_in + connect \CR_dec31_dec_sub16_cr_out \CR_dec31_dec_sub16_CR_dec31_dec_sub16_cr_out + connect \CR_dec31_dec_sub16_function_unit \CR_dec31_dec_sub16_CR_dec31_dec_sub16_function_unit + connect \CR_dec31_dec_sub16_internal_op \CR_dec31_dec_sub16_CR_dec31_dec_sub16_internal_op + connect \CR_dec31_dec_sub16_rc_sel \CR_dec31_dec_sub16_CR_dec31_dec_sub16_rc_sel + connect \opcode_in \CR_dec31_dec_sub16_opcode_in + end + attribute \module_not_derived 1 + attribute \src "issuer_ls180.v:5863.22-5870.4" + cell \CR_dec31_dec_sub19 \CR_dec31_dec_sub19 + connect \CR_dec31_dec_sub19_cr_in \CR_dec31_dec_sub19_CR_dec31_dec_sub19_cr_in + connect \CR_dec31_dec_sub19_cr_out \CR_dec31_dec_sub19_CR_dec31_dec_sub19_cr_out + connect \CR_dec31_dec_sub19_function_unit \CR_dec31_dec_sub19_CR_dec31_dec_sub19_function_unit + connect \CR_dec31_dec_sub19_internal_op \CR_dec31_dec_sub19_CR_dec31_dec_sub19_internal_op + connect \CR_dec31_dec_sub19_rc_sel \CR_dec31_dec_sub19_CR_dec31_dec_sub19_rc_sel + connect \opcode_in \CR_dec31_dec_sub19_opcode_in + end + attribute \src "issuer_ls180.v:5244.7-5244.20" + process $proc$issuer_ls180.v:5244$126 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "issuer_ls180.v:5871.3-5889.6" + process $proc$issuer_ls180.v:5871$121 + assign { } { } + assign { } { } + assign $0\CR_dec31_rc_sel[1:0] $1\CR_dec31_rc_sel[1:0] + attribute \src "issuer_ls180.v:5872.5-5872.29" + switch \initial + attribute \src "issuer_ls180.v:5872.9-5872.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opc_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\CR_dec31_rc_sel[1:0] \CR_dec31_dec_sub0_CR_dec31_dec_sub0_rc_sel + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\CR_dec31_rc_sel[1:0] \CR_dec31_dec_sub19_CR_dec31_dec_sub19_rc_sel + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\CR_dec31_rc_sel[1:0] \CR_dec31_dec_sub15_CR_dec31_dec_sub15_rc_sel + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\CR_dec31_rc_sel[1:0] \CR_dec31_dec_sub16_CR_dec31_dec_sub16_rc_sel + case + assign $1\CR_dec31_rc_sel[1:0] 2'00 + end + sync always + update \CR_dec31_rc_sel $0\CR_dec31_rc_sel[1:0] + end + attribute \src "issuer_ls180.v:5890.3-5908.6" + process $proc$issuer_ls180.v:5890$122 + assign { } { } + assign { } { } + assign $0\CR_dec31_function_unit[11:0] $1\CR_dec31_function_unit[11:0] + attribute \src "issuer_ls180.v:5891.5-5891.29" + switch \initial + attribute \src "issuer_ls180.v:5891.9-5891.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opc_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\CR_dec31_function_unit[11:0] \CR_dec31_dec_sub0_CR_dec31_dec_sub0_function_unit + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\CR_dec31_function_unit[11:0] \CR_dec31_dec_sub19_CR_dec31_dec_sub19_function_unit + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\CR_dec31_function_unit[11:0] \CR_dec31_dec_sub15_CR_dec31_dec_sub15_function_unit + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\CR_dec31_function_unit[11:0] \CR_dec31_dec_sub16_CR_dec31_dec_sub16_function_unit + case + assign $1\CR_dec31_function_unit[11:0] 12'000000000000 + end + sync always + update \CR_dec31_function_unit $0\CR_dec31_function_unit[11:0] + end + attribute \src "issuer_ls180.v:5909.3-5927.6" + process $proc$issuer_ls180.v:5909$123 + assign { } { } + assign { } { } + assign $0\CR_dec31_internal_op[6:0] $1\CR_dec31_internal_op[6:0] + attribute \src "issuer_ls180.v:5910.5-5910.29" + switch \initial + attribute \src "issuer_ls180.v:5910.9-5910.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opc_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\CR_dec31_internal_op[6:0] \CR_dec31_dec_sub0_CR_dec31_dec_sub0_internal_op + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\CR_dec31_internal_op[6:0] \CR_dec31_dec_sub19_CR_dec31_dec_sub19_internal_op + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\CR_dec31_internal_op[6:0] \CR_dec31_dec_sub15_CR_dec31_dec_sub15_internal_op + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\CR_dec31_internal_op[6:0] \CR_dec31_dec_sub16_CR_dec31_dec_sub16_internal_op + case + assign $1\CR_dec31_internal_op[6:0] 7'0000000 + end + sync always + update \CR_dec31_internal_op $0\CR_dec31_internal_op[6:0] + end + attribute \src "issuer_ls180.v:5928.3-5946.6" + process $proc$issuer_ls180.v:5928$124 + assign { } { } + assign { } { } + assign $0\CR_dec31_cr_in[2:0] $1\CR_dec31_cr_in[2:0] + attribute \src "issuer_ls180.v:5929.5-5929.29" + switch \initial + attribute \src "issuer_ls180.v:5929.9-5929.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opc_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\CR_dec31_cr_in[2:0] \CR_dec31_dec_sub0_CR_dec31_dec_sub0_cr_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\CR_dec31_cr_in[2:0] \CR_dec31_dec_sub19_CR_dec31_dec_sub19_cr_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\CR_dec31_cr_in[2:0] \CR_dec31_dec_sub15_CR_dec31_dec_sub15_cr_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\CR_dec31_cr_in[2:0] \CR_dec31_dec_sub16_CR_dec31_dec_sub16_cr_in + case + assign $1\CR_dec31_cr_in[2:0] 3'000 + end + sync always + update \CR_dec31_cr_in $0\CR_dec31_cr_in[2:0] + end + attribute \src "issuer_ls180.v:5947.3-5965.6" + process $proc$issuer_ls180.v:5947$125 + assign { } { } + assign { } { } + assign $0\CR_dec31_cr_out[2:0] $1\CR_dec31_cr_out[2:0] + attribute \src "issuer_ls180.v:5948.5-5948.29" + switch \initial + attribute \src "issuer_ls180.v:5948.9-5948.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opc_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\CR_dec31_cr_out[2:0] \CR_dec31_dec_sub0_CR_dec31_dec_sub0_cr_out + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\CR_dec31_cr_out[2:0] \CR_dec31_dec_sub19_CR_dec31_dec_sub19_cr_out + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\CR_dec31_cr_out[2:0] \CR_dec31_dec_sub15_CR_dec31_dec_sub15_cr_out + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\CR_dec31_cr_out[2:0] \CR_dec31_dec_sub16_CR_dec31_dec_sub16_cr_out + case + assign $1\CR_dec31_cr_out[2:0] 3'000 + end + sync always + update \CR_dec31_cr_out $0\CR_dec31_cr_out[2:0] + end + connect \CR_dec31_dec_sub16_opcode_in \opcode_in + connect \CR_dec31_dec_sub15_opcode_in \opcode_in + connect \CR_dec31_dec_sub19_opcode_in \opcode_in + connect \CR_dec31_dec_sub0_opcode_in \opcode_in + connect \opc_in \opcode_switch [4:0] + connect \opcode_switch \opcode_in [10:1] +end +attribute \src "issuer_ls180.v:5976.1-6153.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.dec_CR.dec.CR_dec31.CR_dec31_dec_sub0" +attribute \generator "nMigen" +module \CR_dec31_dec_sub0 + attribute \src "issuer_ls180.v:6122.3-6131.6" + wire width 3 $0\CR_dec31_dec_sub0_cr_in[2:0] + attribute \src "issuer_ls180.v:6132.3-6141.6" + wire width 3 $0\CR_dec31_dec_sub0_cr_out[2:0] + attribute \src "issuer_ls180.v:6102.3-6111.6" + wire width 12 $0\CR_dec31_dec_sub0_function_unit[11:0] + attribute \src "issuer_ls180.v:6112.3-6121.6" + wire width 7 $0\CR_dec31_dec_sub0_internal_op[6:0] + attribute \src "issuer_ls180.v:6142.3-6151.6" + wire width 2 $0\CR_dec31_dec_sub0_rc_sel[1:0] + attribute \src "issuer_ls180.v:5977.7-5977.20" + wire $0\initial[0:0] + attribute \src "issuer_ls180.v:6122.3-6131.6" + wire width 3 $1\CR_dec31_dec_sub0_cr_in[2:0] + attribute \src "issuer_ls180.v:6132.3-6141.6" + wire width 3 $1\CR_dec31_dec_sub0_cr_out[2:0] + attribute \src "issuer_ls180.v:6102.3-6111.6" + wire width 12 $1\CR_dec31_dec_sub0_function_unit[11:0] + attribute \src "issuer_ls180.v:6112.3-6121.6" + wire width 7 $1\CR_dec31_dec_sub0_internal_op[6:0] + attribute \src "issuer_ls180.v:6142.3-6151.6" + wire width 2 $1\CR_dec31_dec_sub0_rc_sel[1:0] + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 3 \CR_dec31_dec_sub0_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 4 \CR_dec31_dec_sub0_cr_out + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 12 output 1 \CR_dec31_dec_sub0_function_unit + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 7 output 2 \CR_dec31_dec_sub0_internal_op + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 5 \CR_dec31_dec_sub0_rc_sel + attribute \src "issuer_ls180.v:5977.7-5977.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + wire width 32 input 6 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:320" + wire width 5 \opcode_switch + attribute \src "issuer_ls180.v:5977.7-5977.20" + process $proc$issuer_ls180.v:5977$132 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "issuer_ls180.v:6102.3-6111.6" + process $proc$issuer_ls180.v:6102$127 + assign { } { } + assign { } { } + assign $0\CR_dec31_dec_sub0_function_unit[11:0] $1\CR_dec31_dec_sub0_function_unit[11:0] + attribute \src "issuer_ls180.v:6103.5-6103.29" + switch \initial + attribute \src "issuer_ls180.v:6103.9-6103.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\CR_dec31_dec_sub0_function_unit[11:0] 12'000001000000 + case + assign $1\CR_dec31_dec_sub0_function_unit[11:0] 12'000000000000 + end + sync always + update \CR_dec31_dec_sub0_function_unit $0\CR_dec31_dec_sub0_function_unit[11:0] + end + attribute \src "issuer_ls180.v:6112.3-6121.6" + process $proc$issuer_ls180.v:6112$128 + assign { } { } + assign { } { } + assign $0\CR_dec31_dec_sub0_internal_op[6:0] $1\CR_dec31_dec_sub0_internal_op[6:0] + attribute \src "issuer_ls180.v:6113.5-6113.29" + switch \initial + attribute \src "issuer_ls180.v:6113.9-6113.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\CR_dec31_dec_sub0_internal_op[6:0] 7'0111011 + case + assign $1\CR_dec31_dec_sub0_internal_op[6:0] 7'0000000 + end + sync always + update \CR_dec31_dec_sub0_internal_op $0\CR_dec31_dec_sub0_internal_op[6:0] + end + attribute \src "issuer_ls180.v:6122.3-6131.6" + process $proc$issuer_ls180.v:6122$129 + assign { } { } + assign { } { } + assign $0\CR_dec31_dec_sub0_cr_in[2:0] $1\CR_dec31_dec_sub0_cr_in[2:0] + attribute \src "issuer_ls180.v:6123.5-6123.29" + switch \initial + attribute \src "issuer_ls180.v:6123.9-6123.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\CR_dec31_dec_sub0_cr_in[2:0] 3'011 + case + assign $1\CR_dec31_dec_sub0_cr_in[2:0] 3'000 + end + sync always + update \CR_dec31_dec_sub0_cr_in $0\CR_dec31_dec_sub0_cr_in[2:0] + end + attribute \src "issuer_ls180.v:6132.3-6141.6" + process $proc$issuer_ls180.v:6132$130 + assign { } { } + assign { } { } + assign $0\CR_dec31_dec_sub0_cr_out[2:0] $1\CR_dec31_dec_sub0_cr_out[2:0] + attribute \src "issuer_ls180.v:6133.5-6133.29" + switch \initial + attribute \src "issuer_ls180.v:6133.9-6133.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\CR_dec31_dec_sub0_cr_out[2:0] 3'000 + case + assign $1\CR_dec31_dec_sub0_cr_out[2:0] 3'000 + end + sync always + update \CR_dec31_dec_sub0_cr_out $0\CR_dec31_dec_sub0_cr_out[2:0] + end + attribute \src "issuer_ls180.v:6142.3-6151.6" + process $proc$issuer_ls180.v:6142$131 + assign { } { } + assign { } { } + assign $0\CR_dec31_dec_sub0_rc_sel[1:0] $1\CR_dec31_dec_sub0_rc_sel[1:0] + attribute \src "issuer_ls180.v:6143.5-6143.29" + switch \initial + attribute \src "issuer_ls180.v:6143.9-6143.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\CR_dec31_dec_sub0_rc_sel[1:0] 2'00 + case + assign $1\CR_dec31_dec_sub0_rc_sel[1:0] 2'00 + end + sync always + update \CR_dec31_dec_sub0_rc_sel $0\CR_dec31_dec_sub0_rc_sel[1:0] + end + connect \opcode_switch \opcode_in [10:6] +end +attribute \src "issuer_ls180.v:6157.1-6799.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.dec_CR.dec.CR_dec31.CR_dec31_dec_sub15" +attribute \generator "nMigen" +module \CR_dec31_dec_sub15 + attribute \src "issuer_ls180.v:6489.3-6591.6" + wire width 3 $0\CR_dec31_dec_sub15_cr_in[2:0] + attribute \src "issuer_ls180.v:6592.3-6694.6" + wire width 3 $0\CR_dec31_dec_sub15_cr_out[2:0] + attribute \src "issuer_ls180.v:6283.3-6385.6" + wire width 12 $0\CR_dec31_dec_sub15_function_unit[11:0] + attribute \src "issuer_ls180.v:6386.3-6488.6" + wire width 7 $0\CR_dec31_dec_sub15_internal_op[6:0] + attribute \src "issuer_ls180.v:6695.3-6797.6" + wire width 2 $0\CR_dec31_dec_sub15_rc_sel[1:0] + attribute \src "issuer_ls180.v:6158.7-6158.20" + wire $0\initial[0:0] + attribute \src "issuer_ls180.v:6489.3-6591.6" + wire width 3 $1\CR_dec31_dec_sub15_cr_in[2:0] + attribute \src "issuer_ls180.v:6592.3-6694.6" + wire width 3 $1\CR_dec31_dec_sub15_cr_out[2:0] + attribute \src "issuer_ls180.v:6283.3-6385.6" + wire width 12 $1\CR_dec31_dec_sub15_function_unit[11:0] + attribute \src "issuer_ls180.v:6386.3-6488.6" + wire width 7 $1\CR_dec31_dec_sub15_internal_op[6:0] + attribute \src "issuer_ls180.v:6695.3-6797.6" + wire width 2 $1\CR_dec31_dec_sub15_rc_sel[1:0] + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 3 \CR_dec31_dec_sub15_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 4 \CR_dec31_dec_sub15_cr_out + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 12 output 1 \CR_dec31_dec_sub15_function_unit + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 7 output 2 \CR_dec31_dec_sub15_internal_op + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 5 \CR_dec31_dec_sub15_rc_sel + attribute \src "issuer_ls180.v:6158.7-6158.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + wire width 32 input 6 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:320" + wire width 5 \opcode_switch + attribute \src "issuer_ls180.v:6158.7-6158.20" + process $proc$issuer_ls180.v:6158$138 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "issuer_ls180.v:6283.3-6385.6" + process $proc$issuer_ls180.v:6283$133 + assign { } { } + assign { } { } + assign $0\CR_dec31_dec_sub15_function_unit[11:0] $1\CR_dec31_dec_sub15_function_unit[11:0] + attribute \src "issuer_ls180.v:6284.5-6284.29" + switch \initial + attribute \src "issuer_ls180.v:6284.9-6284.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\CR_dec31_dec_sub15_function_unit[11:0] 12'000001000000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\CR_dec31_dec_sub15_function_unit[11:0] 12'000001000000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\CR_dec31_dec_sub15_function_unit[11:0] 12'000001000000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\CR_dec31_dec_sub15_function_unit[11:0] 12'000001000000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\CR_dec31_dec_sub15_function_unit[11:0] 12'000001000000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\CR_dec31_dec_sub15_function_unit[11:0] 12'000001000000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\CR_dec31_dec_sub15_function_unit[11:0] 12'000001000000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\CR_dec31_dec_sub15_function_unit[11:0] 12'000001000000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\CR_dec31_dec_sub15_function_unit[11:0] 12'000001000000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\CR_dec31_dec_sub15_function_unit[11:0] 12'000001000000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\CR_dec31_dec_sub15_function_unit[11:0] 12'000001000000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\CR_dec31_dec_sub15_function_unit[11:0] 12'000001000000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\CR_dec31_dec_sub15_function_unit[11:0] 12'000001000000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\CR_dec31_dec_sub15_function_unit[11:0] 12'000001000000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\CR_dec31_dec_sub15_function_unit[11:0] 12'000001000000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\CR_dec31_dec_sub15_function_unit[11:0] 12'000001000000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\CR_dec31_dec_sub15_function_unit[11:0] 12'000001000000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\CR_dec31_dec_sub15_function_unit[11:0] 12'000001000000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\CR_dec31_dec_sub15_function_unit[11:0] 12'000001000000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\CR_dec31_dec_sub15_function_unit[11:0] 12'000001000000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\CR_dec31_dec_sub15_function_unit[11:0] 12'000001000000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\CR_dec31_dec_sub15_function_unit[11:0] 12'000001000000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\CR_dec31_dec_sub15_function_unit[11:0] 12'000001000000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\CR_dec31_dec_sub15_function_unit[11:0] 12'000001000000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\CR_dec31_dec_sub15_function_unit[11:0] 12'000001000000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\CR_dec31_dec_sub15_function_unit[11:0] 12'000001000000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\CR_dec31_dec_sub15_function_unit[11:0] 12'000001000000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\CR_dec31_dec_sub15_function_unit[11:0] 12'000001000000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\CR_dec31_dec_sub15_function_unit[11:0] 12'000001000000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\CR_dec31_dec_sub15_function_unit[11:0] 12'000001000000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\CR_dec31_dec_sub15_function_unit[11:0] 12'000001000000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\CR_dec31_dec_sub15_function_unit[11:0] 12'000001000000 + case + assign $1\CR_dec31_dec_sub15_function_unit[11:0] 12'000000000000 + end + sync always + update \CR_dec31_dec_sub15_function_unit $0\CR_dec31_dec_sub15_function_unit[11:0] + end + attribute \src "issuer_ls180.v:6386.3-6488.6" + process $proc$issuer_ls180.v:6386$134 + assign { } { } + assign { } { } + assign $0\CR_dec31_dec_sub15_internal_op[6:0] $1\CR_dec31_dec_sub15_internal_op[6:0] + attribute \src "issuer_ls180.v:6387.5-6387.29" + switch \initial + attribute \src "issuer_ls180.v:6387.9-6387.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\CR_dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\CR_dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\CR_dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\CR_dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\CR_dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\CR_dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\CR_dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\CR_dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\CR_dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\CR_dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\CR_dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\CR_dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\CR_dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\CR_dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\CR_dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\CR_dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\CR_dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\CR_dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\CR_dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\CR_dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\CR_dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\CR_dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\CR_dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\CR_dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\CR_dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\CR_dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\CR_dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\CR_dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\CR_dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\CR_dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\CR_dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\CR_dec31_dec_sub15_internal_op[6:0] 7'0100011 + case + assign $1\CR_dec31_dec_sub15_internal_op[6:0] 7'0000000 + end + sync always + update \CR_dec31_dec_sub15_internal_op $0\CR_dec31_dec_sub15_internal_op[6:0] + end + attribute \src "issuer_ls180.v:6489.3-6591.6" + process $proc$issuer_ls180.v:6489$135 + assign { } { } + assign { } { } + assign $0\CR_dec31_dec_sub15_cr_in[2:0] $1\CR_dec31_dec_sub15_cr_in[2:0] + attribute \src "issuer_ls180.v:6490.5-6490.29" + switch \initial + attribute \src "issuer_ls180.v:6490.9-6490.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\CR_dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\CR_dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\CR_dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\CR_dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\CR_dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\CR_dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\CR_dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\CR_dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\CR_dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\CR_dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\CR_dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\CR_dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\CR_dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\CR_dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\CR_dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\CR_dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\CR_dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\CR_dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\CR_dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\CR_dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\CR_dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\CR_dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\CR_dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\CR_dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\CR_dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\CR_dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\CR_dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\CR_dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\CR_dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\CR_dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\CR_dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\CR_dec31_dec_sub15_cr_in[2:0] 3'101 + case + assign $1\CR_dec31_dec_sub15_cr_in[2:0] 3'000 + end + sync always + update \CR_dec31_dec_sub15_cr_in $0\CR_dec31_dec_sub15_cr_in[2:0] + end + attribute \src "issuer_ls180.v:6592.3-6694.6" + process $proc$issuer_ls180.v:6592$136 + assign { } { } + assign { } { } + assign $0\CR_dec31_dec_sub15_cr_out[2:0] $1\CR_dec31_dec_sub15_cr_out[2:0] + attribute \src "issuer_ls180.v:6593.5-6593.29" + switch \initial + attribute \src "issuer_ls180.v:6593.9-6593.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\CR_dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\CR_dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\CR_dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\CR_dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\CR_dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\CR_dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\CR_dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\CR_dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\CR_dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\CR_dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\CR_dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\CR_dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\CR_dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\CR_dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\CR_dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\CR_dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\CR_dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\CR_dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\CR_dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\CR_dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\CR_dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\CR_dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\CR_dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\CR_dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\CR_dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\CR_dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\CR_dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\CR_dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\CR_dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\CR_dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\CR_dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\CR_dec31_dec_sub15_cr_out[2:0] 3'000 + case + assign $1\CR_dec31_dec_sub15_cr_out[2:0] 3'000 + end + sync always + update \CR_dec31_dec_sub15_cr_out $0\CR_dec31_dec_sub15_cr_out[2:0] + end + attribute \src "issuer_ls180.v:6695.3-6797.6" + process $proc$issuer_ls180.v:6695$137 + assign { } { } + assign { } { } + assign $0\CR_dec31_dec_sub15_rc_sel[1:0] $1\CR_dec31_dec_sub15_rc_sel[1:0] + attribute \src "issuer_ls180.v:6696.5-6696.29" + switch \initial + attribute \src "issuer_ls180.v:6696.9-6696.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\CR_dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\CR_dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\CR_dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\CR_dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\CR_dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\CR_dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\CR_dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\CR_dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\CR_dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\CR_dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\CR_dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\CR_dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\CR_dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\CR_dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\CR_dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\CR_dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\CR_dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\CR_dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\CR_dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\CR_dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\CR_dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\CR_dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\CR_dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\CR_dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\CR_dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\CR_dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\CR_dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\CR_dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\CR_dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\CR_dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\CR_dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\CR_dec31_dec_sub15_rc_sel[1:0] 2'00 + case + assign $1\CR_dec31_dec_sub15_rc_sel[1:0] 2'00 + end + sync always + update \CR_dec31_dec_sub15_rc_sel $0\CR_dec31_dec_sub15_rc_sel[1:0] + end + connect \opcode_switch \opcode_in [10:6] +end +attribute \src "issuer_ls180.v:6803.1-6980.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.dec_CR.dec.CR_dec31.CR_dec31_dec_sub16" +attribute \generator "nMigen" +module \CR_dec31_dec_sub16 + attribute \src "issuer_ls180.v:6949.3-6958.6" + wire width 3 $0\CR_dec31_dec_sub16_cr_in[2:0] + attribute \src "issuer_ls180.v:6959.3-6968.6" + wire width 3 $0\CR_dec31_dec_sub16_cr_out[2:0] + attribute \src "issuer_ls180.v:6929.3-6938.6" + wire width 12 $0\CR_dec31_dec_sub16_function_unit[11:0] + attribute \src "issuer_ls180.v:6939.3-6948.6" + wire width 7 $0\CR_dec31_dec_sub16_internal_op[6:0] + attribute \src "issuer_ls180.v:6969.3-6978.6" + wire width 2 $0\CR_dec31_dec_sub16_rc_sel[1:0] + attribute \src "issuer_ls180.v:6804.7-6804.20" + wire $0\initial[0:0] + attribute \src "issuer_ls180.v:6949.3-6958.6" + wire width 3 $1\CR_dec31_dec_sub16_cr_in[2:0] + attribute \src "issuer_ls180.v:6959.3-6968.6" + wire width 3 $1\CR_dec31_dec_sub16_cr_out[2:0] + attribute \src "issuer_ls180.v:6929.3-6938.6" + wire width 12 $1\CR_dec31_dec_sub16_function_unit[11:0] + attribute \src "issuer_ls180.v:6939.3-6948.6" + wire width 7 $1\CR_dec31_dec_sub16_internal_op[6:0] + attribute \src "issuer_ls180.v:6969.3-6978.6" + wire width 2 $1\CR_dec31_dec_sub16_rc_sel[1:0] + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 3 \CR_dec31_dec_sub16_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 4 \CR_dec31_dec_sub16_cr_out + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 12 output 1 \CR_dec31_dec_sub16_function_unit + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 7 output 2 \CR_dec31_dec_sub16_internal_op + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 5 \CR_dec31_dec_sub16_rc_sel + attribute \src "issuer_ls180.v:6804.7-6804.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + wire width 32 input 6 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:320" + wire width 5 \opcode_switch + attribute \src "issuer_ls180.v:6804.7-6804.20" + process $proc$issuer_ls180.v:6804$144 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "issuer_ls180.v:6929.3-6938.6" + process $proc$issuer_ls180.v:6929$139 + assign { } { } + assign { } { } + assign $0\CR_dec31_dec_sub16_function_unit[11:0] $1\CR_dec31_dec_sub16_function_unit[11:0] + attribute \src "issuer_ls180.v:6930.5-6930.29" + switch \initial + attribute \src "issuer_ls180.v:6930.9-6930.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\CR_dec31_dec_sub16_function_unit[11:0] 12'000001000000 + case + assign $1\CR_dec31_dec_sub16_function_unit[11:0] 12'000000000000 + end + sync always + update \CR_dec31_dec_sub16_function_unit $0\CR_dec31_dec_sub16_function_unit[11:0] + end + attribute \src "issuer_ls180.v:6939.3-6948.6" + process $proc$issuer_ls180.v:6939$140 + assign { } { } + assign { } { } + assign $0\CR_dec31_dec_sub16_internal_op[6:0] $1\CR_dec31_dec_sub16_internal_op[6:0] + attribute \src "issuer_ls180.v:6940.5-6940.29" + switch \initial + attribute \src "issuer_ls180.v:6940.9-6940.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\CR_dec31_dec_sub16_internal_op[6:0] 7'0110000 + case + assign $1\CR_dec31_dec_sub16_internal_op[6:0] 7'0000000 + end + sync always + update \CR_dec31_dec_sub16_internal_op $0\CR_dec31_dec_sub16_internal_op[6:0] + end + attribute \src "issuer_ls180.v:6949.3-6958.6" + process $proc$issuer_ls180.v:6949$141 + assign { } { } + assign { } { } + assign $0\CR_dec31_dec_sub16_cr_in[2:0] $1\CR_dec31_dec_sub16_cr_in[2:0] + attribute \src "issuer_ls180.v:6950.5-6950.29" + switch \initial + attribute \src "issuer_ls180.v:6950.9-6950.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\CR_dec31_dec_sub16_cr_in[2:0] 3'110 + case + assign $1\CR_dec31_dec_sub16_cr_in[2:0] 3'000 + end + sync always + update \CR_dec31_dec_sub16_cr_in $0\CR_dec31_dec_sub16_cr_in[2:0] + end + attribute \src "issuer_ls180.v:6959.3-6968.6" + process $proc$issuer_ls180.v:6959$142 + assign { } { } + assign { } { } + assign $0\CR_dec31_dec_sub16_cr_out[2:0] $1\CR_dec31_dec_sub16_cr_out[2:0] + attribute \src "issuer_ls180.v:6960.5-6960.29" + switch \initial + attribute \src "issuer_ls180.v:6960.9-6960.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\CR_dec31_dec_sub16_cr_out[2:0] 3'100 + case + assign $1\CR_dec31_dec_sub16_cr_out[2:0] 3'000 + end + sync always + update \CR_dec31_dec_sub16_cr_out $0\CR_dec31_dec_sub16_cr_out[2:0] + end + attribute \src "issuer_ls180.v:6969.3-6978.6" + process $proc$issuer_ls180.v:6969$143 + assign { } { } + assign { } { } + assign $0\CR_dec31_dec_sub16_rc_sel[1:0] $1\CR_dec31_dec_sub16_rc_sel[1:0] + attribute \src "issuer_ls180.v:6970.5-6970.29" + switch \initial + attribute \src "issuer_ls180.v:6970.9-6970.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\CR_dec31_dec_sub16_rc_sel[1:0] 2'00 + case + assign $1\CR_dec31_dec_sub16_rc_sel[1:0] 2'00 + end + sync always + update \CR_dec31_dec_sub16_rc_sel $0\CR_dec31_dec_sub16_rc_sel[1:0] + end + connect \opcode_switch \opcode_in [10:6] +end +attribute \src "issuer_ls180.v:6984.1-7161.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.dec_CR.dec.CR_dec31.CR_dec31_dec_sub19" +attribute \generator "nMigen" +module \CR_dec31_dec_sub19 + attribute \src "issuer_ls180.v:7130.3-7139.6" + wire width 3 $0\CR_dec31_dec_sub19_cr_in[2:0] + attribute \src "issuer_ls180.v:7140.3-7149.6" + wire width 3 $0\CR_dec31_dec_sub19_cr_out[2:0] + attribute \src "issuer_ls180.v:7110.3-7119.6" + wire width 12 $0\CR_dec31_dec_sub19_function_unit[11:0] + attribute \src "issuer_ls180.v:7120.3-7129.6" + wire width 7 $0\CR_dec31_dec_sub19_internal_op[6:0] + attribute \src "issuer_ls180.v:7150.3-7159.6" + wire width 2 $0\CR_dec31_dec_sub19_rc_sel[1:0] + attribute \src "issuer_ls180.v:6985.7-6985.20" + wire $0\initial[0:0] + attribute \src "issuer_ls180.v:7130.3-7139.6" + wire width 3 $1\CR_dec31_dec_sub19_cr_in[2:0] + attribute \src "issuer_ls180.v:7140.3-7149.6" + wire width 3 $1\CR_dec31_dec_sub19_cr_out[2:0] + attribute \src "issuer_ls180.v:7110.3-7119.6" + wire width 12 $1\CR_dec31_dec_sub19_function_unit[11:0] + attribute \src "issuer_ls180.v:7120.3-7129.6" + wire width 7 $1\CR_dec31_dec_sub19_internal_op[6:0] + attribute \src "issuer_ls180.v:7150.3-7159.6" + wire width 2 $1\CR_dec31_dec_sub19_rc_sel[1:0] + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 3 \CR_dec31_dec_sub19_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 4 \CR_dec31_dec_sub19_cr_out + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 12 output 1 \CR_dec31_dec_sub19_function_unit + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 7 output 2 \CR_dec31_dec_sub19_internal_op + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 5 \CR_dec31_dec_sub19_rc_sel + attribute \src "issuer_ls180.v:6985.7-6985.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + wire width 32 input 6 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:320" + wire width 5 \opcode_switch + attribute \src "issuer_ls180.v:6985.7-6985.20" + process $proc$issuer_ls180.v:6985$150 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "issuer_ls180.v:7110.3-7119.6" + process $proc$issuer_ls180.v:7110$145 + assign { } { } + assign { } { } + assign $0\CR_dec31_dec_sub19_function_unit[11:0] $1\CR_dec31_dec_sub19_function_unit[11:0] + attribute \src "issuer_ls180.v:7111.5-7111.29" + switch \initial + attribute \src "issuer_ls180.v:7111.9-7111.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\CR_dec31_dec_sub19_function_unit[11:0] 12'000001000000 + case + assign $1\CR_dec31_dec_sub19_function_unit[11:0] 12'000000000000 + end + sync always + update \CR_dec31_dec_sub19_function_unit $0\CR_dec31_dec_sub19_function_unit[11:0] + end + attribute \src "issuer_ls180.v:7120.3-7129.6" + process $proc$issuer_ls180.v:7120$146 + assign { } { } + assign { } { } + assign $0\CR_dec31_dec_sub19_internal_op[6:0] $1\CR_dec31_dec_sub19_internal_op[6:0] + attribute \src "issuer_ls180.v:7121.5-7121.29" + switch \initial + attribute \src "issuer_ls180.v:7121.9-7121.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\CR_dec31_dec_sub19_internal_op[6:0] 7'0101101 + case + assign $1\CR_dec31_dec_sub19_internal_op[6:0] 7'0000000 + end + sync always + update \CR_dec31_dec_sub19_internal_op $0\CR_dec31_dec_sub19_internal_op[6:0] + end + attribute \src "issuer_ls180.v:7130.3-7139.6" + process $proc$issuer_ls180.v:7130$147 + assign { } { } + assign { } { } + assign $0\CR_dec31_dec_sub19_cr_in[2:0] $1\CR_dec31_dec_sub19_cr_in[2:0] + attribute \src "issuer_ls180.v:7131.5-7131.29" + switch \initial + attribute \src "issuer_ls180.v:7131.9-7131.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\CR_dec31_dec_sub19_cr_in[2:0] 3'110 + case + assign $1\CR_dec31_dec_sub19_cr_in[2:0] 3'000 + end + sync always + update \CR_dec31_dec_sub19_cr_in $0\CR_dec31_dec_sub19_cr_in[2:0] + end + attribute \src "issuer_ls180.v:7140.3-7149.6" + process $proc$issuer_ls180.v:7140$148 + assign { } { } + assign { } { } + assign $0\CR_dec31_dec_sub19_cr_out[2:0] $1\CR_dec31_dec_sub19_cr_out[2:0] + attribute \src "issuer_ls180.v:7141.5-7141.29" + switch \initial + attribute \src "issuer_ls180.v:7141.9-7141.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\CR_dec31_dec_sub19_cr_out[2:0] 3'000 + case + assign $1\CR_dec31_dec_sub19_cr_out[2:0] 3'000 + end + sync always + update \CR_dec31_dec_sub19_cr_out $0\CR_dec31_dec_sub19_cr_out[2:0] + end + attribute \src "issuer_ls180.v:7150.3-7159.6" + process $proc$issuer_ls180.v:7150$149 + assign { } { } + assign { } { } + assign $0\CR_dec31_dec_sub19_rc_sel[1:0] $1\CR_dec31_dec_sub19_rc_sel[1:0] + attribute \src "issuer_ls180.v:7151.5-7151.29" + switch \initial + attribute \src "issuer_ls180.v:7151.9-7151.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\CR_dec31_dec_sub19_rc_sel[1:0] 2'00 + case + assign $1\CR_dec31_dec_sub19_rc_sel[1:0] 2'00 + end + sync always + update \CR_dec31_dec_sub19_rc_sel $0\CR_dec31_dec_sub19_rc_sel[1:0] + end + connect \opcode_switch \opcode_in [10:6] +end +attribute \src "issuer_ls180.v:7165.1-7903.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.dec_DIV.dec.DIV_dec31" +attribute \generator "nMigen" +module \DIV_dec31 + attribute \src "issuer_ls180.v:7873.3-7885.6" + wire width 3 $0\DIV_dec31_cr_in[2:0] + attribute \src "issuer_ls180.v:7886.3-7898.6" + wire width 3 $0\DIV_dec31_cr_out[2:0] + attribute \src "issuer_ls180.v:7743.3-7755.6" + wire width 2 $0\DIV_dec31_cry_in[1:0] + attribute \src "issuer_ls180.v:7782.3-7794.6" + wire $0\DIV_dec31_cry_out[0:0] + attribute \src "issuer_ls180.v:7821.3-7833.6" + wire width 12 $0\DIV_dec31_function_unit[11:0] + attribute \src "issuer_ls180.v:7847.3-7859.6" + wire width 3 $0\DIV_dec31_in1_sel[2:0] + attribute \src "issuer_ls180.v:7860.3-7872.6" + wire width 4 $0\DIV_dec31_in2_sel[3:0] + attribute \src "issuer_ls180.v:7834.3-7846.6" + wire width 7 $0\DIV_dec31_internal_op[6:0] + attribute \src "issuer_ls180.v:7756.3-7768.6" + wire $0\DIV_dec31_inv_a[0:0] + attribute \src "issuer_ls180.v:7769.3-7781.6" + wire $0\DIV_dec31_inv_out[0:0] + attribute \src "issuer_ls180.v:7795.3-7807.6" + wire $0\DIV_dec31_is_32b[0:0] + attribute \src "issuer_ls180.v:7717.3-7729.6" + wire width 4 $0\DIV_dec31_ldst_len[3:0] + attribute \src "issuer_ls180.v:7730.3-7742.6" + wire width 2 $0\DIV_dec31_rc_sel[1:0] + attribute \src "issuer_ls180.v:7808.3-7820.6" + wire $0\DIV_dec31_sgn[0:0] + attribute \src "issuer_ls180.v:7166.7-7166.20" + wire $0\initial[0:0] + attribute \src "issuer_ls180.v:7873.3-7885.6" + wire width 3 $1\DIV_dec31_cr_in[2:0] + attribute \src "issuer_ls180.v:7886.3-7898.6" + wire width 3 $1\DIV_dec31_cr_out[2:0] + attribute \src "issuer_ls180.v:7743.3-7755.6" + wire width 2 $1\DIV_dec31_cry_in[1:0] + attribute \src "issuer_ls180.v:7782.3-7794.6" + wire $1\DIV_dec31_cry_out[0:0] + attribute \src "issuer_ls180.v:7821.3-7833.6" + wire width 12 $1\DIV_dec31_function_unit[11:0] + attribute \src "issuer_ls180.v:7847.3-7859.6" + wire width 3 $1\DIV_dec31_in1_sel[2:0] + attribute \src "issuer_ls180.v:7860.3-7872.6" + wire width 4 $1\DIV_dec31_in2_sel[3:0] + attribute \src "issuer_ls180.v:7834.3-7846.6" + wire width 7 $1\DIV_dec31_internal_op[6:0] + attribute \src "issuer_ls180.v:7756.3-7768.6" + wire $1\DIV_dec31_inv_a[0:0] + attribute \src "issuer_ls180.v:7769.3-7781.6" + wire $1\DIV_dec31_inv_out[0:0] + attribute \src "issuer_ls180.v:7795.3-7807.6" + wire $1\DIV_dec31_is_32b[0:0] + attribute \src "issuer_ls180.v:7717.3-7729.6" + wire width 4 $1\DIV_dec31_ldst_len[3:0] + attribute \src "issuer_ls180.v:7730.3-7742.6" + wire width 2 $1\DIV_dec31_rc_sel[1:0] + attribute \src "issuer_ls180.v:7808.3-7820.6" + wire $1\DIV_dec31_sgn[0:0] + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 5 \DIV_dec31_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 6 \DIV_dec31_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 9 \DIV_dec31_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 12 \DIV_dec31_cry_out + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 \DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 \DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_cry_out + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 12 \DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 \DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 \DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_in2_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 7 \DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 \DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_ldst_len + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + wire width 32 \DIV_dec31_dec_sub11_opcode_in + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 \DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 \DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_cry_out + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 12 \DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 \DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 \DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_in2_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 7 \DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 \DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_ldst_len + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + wire width 32 \DIV_dec31_dec_sub9_opcode_in + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 12 output 1 \DIV_dec31_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 3 \DIV_dec31_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 output 4 \DIV_dec31_in2_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 7 output 2 \DIV_dec31_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 10 \DIV_dec31_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 11 \DIV_dec31_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 13 \DIV_dec31_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 output 7 \DIV_dec31_ldst_len + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 8 \DIV_dec31_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 14 \DIV_dec31_sgn + attribute \src "issuer_ls180.v:7166.7-7166.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:326" + wire width 5 \opc_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + wire width 32 input 15 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:320" + wire width 10 \opcode_switch + attribute \module_not_derived 1 + attribute \src "issuer_ls180.v:7683.23-7699.4" + cell \DIV_dec31_dec_sub11 \DIV_dec31_dec_sub11 + connect \DIV_dec31_dec_sub11_cr_in \DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_cr_in + connect \DIV_dec31_dec_sub11_cr_out \DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_cr_out + connect \DIV_dec31_dec_sub11_cry_in \DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_cry_in + connect \DIV_dec31_dec_sub11_cry_out \DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_cry_out + connect \DIV_dec31_dec_sub11_function_unit \DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_function_unit + connect \DIV_dec31_dec_sub11_in1_sel \DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_in1_sel + connect \DIV_dec31_dec_sub11_in2_sel \DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_in2_sel + connect \DIV_dec31_dec_sub11_internal_op \DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_internal_op + connect \DIV_dec31_dec_sub11_inv_a \DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_inv_a + connect \DIV_dec31_dec_sub11_inv_out \DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_inv_out + connect \DIV_dec31_dec_sub11_is_32b \DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_is_32b + connect \DIV_dec31_dec_sub11_ldst_len \DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_ldst_len + connect \DIV_dec31_dec_sub11_rc_sel \DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_rc_sel + connect \DIV_dec31_dec_sub11_sgn \DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_sgn + connect \opcode_in \DIV_dec31_dec_sub11_opcode_in + end + attribute \module_not_derived 1 + attribute \src "issuer_ls180.v:7700.22-7716.4" + cell \DIV_dec31_dec_sub9 \DIV_dec31_dec_sub9 + connect \DIV_dec31_dec_sub9_cr_in \DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_cr_in + connect \DIV_dec31_dec_sub9_cr_out \DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_cr_out + connect \DIV_dec31_dec_sub9_cry_in \DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_cry_in + connect \DIV_dec31_dec_sub9_cry_out \DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_cry_out + connect \DIV_dec31_dec_sub9_function_unit \DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_function_unit + connect \DIV_dec31_dec_sub9_in1_sel \DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_in1_sel + connect \DIV_dec31_dec_sub9_in2_sel \DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_in2_sel + connect \DIV_dec31_dec_sub9_internal_op \DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_internal_op + connect \DIV_dec31_dec_sub9_inv_a \DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_inv_a + connect \DIV_dec31_dec_sub9_inv_out \DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_inv_out + connect \DIV_dec31_dec_sub9_is_32b \DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_is_32b + connect \DIV_dec31_dec_sub9_ldst_len \DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_ldst_len + connect \DIV_dec31_dec_sub9_rc_sel \DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_rc_sel + connect \DIV_dec31_dec_sub9_sgn \DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_sgn + connect \opcode_in \DIV_dec31_dec_sub9_opcode_in + end + attribute \src "issuer_ls180.v:7166.7-7166.20" + process $proc$issuer_ls180.v:7166$165 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "issuer_ls180.v:7717.3-7729.6" + process $proc$issuer_ls180.v:7717$151 + assign { } { } + assign { } { } + assign $0\DIV_dec31_ldst_len[3:0] $1\DIV_dec31_ldst_len[3:0] + attribute \src "issuer_ls180.v:7718.5-7718.29" + switch \initial + attribute \src "issuer_ls180.v:7718.9-7718.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opc_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\DIV_dec31_ldst_len[3:0] \DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_ldst_len + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\DIV_dec31_ldst_len[3:0] \DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_ldst_len + case + assign $1\DIV_dec31_ldst_len[3:0] 4'0000 + end + sync always + update \DIV_dec31_ldst_len $0\DIV_dec31_ldst_len[3:0] + end + attribute \src "issuer_ls180.v:7730.3-7742.6" + process $proc$issuer_ls180.v:7730$152 + assign { } { } + assign { } { } + assign $0\DIV_dec31_rc_sel[1:0] $1\DIV_dec31_rc_sel[1:0] + attribute \src "issuer_ls180.v:7731.5-7731.29" + switch \initial + attribute \src "issuer_ls180.v:7731.9-7731.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opc_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\DIV_dec31_rc_sel[1:0] \DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_rc_sel + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\DIV_dec31_rc_sel[1:0] \DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_rc_sel + case + assign $1\DIV_dec31_rc_sel[1:0] 2'00 + end + sync always + update \DIV_dec31_rc_sel $0\DIV_dec31_rc_sel[1:0] + end + attribute \src "issuer_ls180.v:7743.3-7755.6" + process $proc$issuer_ls180.v:7743$153 + assign { } { } + assign { } { } + assign $0\DIV_dec31_cry_in[1:0] $1\DIV_dec31_cry_in[1:0] + attribute \src "issuer_ls180.v:7744.5-7744.29" + switch \initial + attribute \src "issuer_ls180.v:7744.9-7744.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opc_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\DIV_dec31_cry_in[1:0] \DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_cry_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\DIV_dec31_cry_in[1:0] \DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_cry_in + case + assign $1\DIV_dec31_cry_in[1:0] 2'00 + end + sync always + update \DIV_dec31_cry_in $0\DIV_dec31_cry_in[1:0] + end + attribute \src "issuer_ls180.v:7756.3-7768.6" + process $proc$issuer_ls180.v:7756$154 + assign { } { } + assign { } { } + assign $0\DIV_dec31_inv_a[0:0] $1\DIV_dec31_inv_a[0:0] + attribute \src "issuer_ls180.v:7757.5-7757.29" + switch \initial + attribute \src "issuer_ls180.v:7757.9-7757.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opc_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\DIV_dec31_inv_a[0:0] \DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_inv_a + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\DIV_dec31_inv_a[0:0] \DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_inv_a + case + assign $1\DIV_dec31_inv_a[0:0] 1'0 + end + sync always + update \DIV_dec31_inv_a $0\DIV_dec31_inv_a[0:0] + end + attribute \src "issuer_ls180.v:7769.3-7781.6" + process $proc$issuer_ls180.v:7769$155 + assign { } { } + assign { } { } + assign $0\DIV_dec31_inv_out[0:0] $1\DIV_dec31_inv_out[0:0] + attribute \src "issuer_ls180.v:7770.5-7770.29" + switch \initial + attribute \src "issuer_ls180.v:7770.9-7770.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opc_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\DIV_dec31_inv_out[0:0] \DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_inv_out + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\DIV_dec31_inv_out[0:0] \DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_inv_out + case + assign $1\DIV_dec31_inv_out[0:0] 1'0 + end + sync always + update \DIV_dec31_inv_out $0\DIV_dec31_inv_out[0:0] + end + attribute \src "issuer_ls180.v:7782.3-7794.6" + process $proc$issuer_ls180.v:7782$156 + assign { } { } + assign { } { } + assign $0\DIV_dec31_cry_out[0:0] $1\DIV_dec31_cry_out[0:0] + attribute \src "issuer_ls180.v:7783.5-7783.29" + switch \initial + attribute \src "issuer_ls180.v:7783.9-7783.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opc_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\DIV_dec31_cry_out[0:0] \DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_cry_out + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\DIV_dec31_cry_out[0:0] \DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_cry_out + case + assign $1\DIV_dec31_cry_out[0:0] 1'0 + end + sync always + update \DIV_dec31_cry_out $0\DIV_dec31_cry_out[0:0] + end + attribute \src "issuer_ls180.v:7795.3-7807.6" + process $proc$issuer_ls180.v:7795$157 + assign { } { } + assign { } { } + assign $0\DIV_dec31_is_32b[0:0] $1\DIV_dec31_is_32b[0:0] + attribute \src "issuer_ls180.v:7796.5-7796.29" + switch \initial + attribute \src "issuer_ls180.v:7796.9-7796.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opc_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\DIV_dec31_is_32b[0:0] \DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_is_32b + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\DIV_dec31_is_32b[0:0] \DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_is_32b + case + assign $1\DIV_dec31_is_32b[0:0] 1'0 + end + sync always + update \DIV_dec31_is_32b $0\DIV_dec31_is_32b[0:0] + end + attribute \src "issuer_ls180.v:7808.3-7820.6" + process $proc$issuer_ls180.v:7808$158 + assign { } { } + assign { } { } + assign $0\DIV_dec31_sgn[0:0] $1\DIV_dec31_sgn[0:0] + attribute \src "issuer_ls180.v:7809.5-7809.29" + switch \initial + attribute \src "issuer_ls180.v:7809.9-7809.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opc_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\DIV_dec31_sgn[0:0] \DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_sgn + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\DIV_dec31_sgn[0:0] \DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_sgn + case + assign $1\DIV_dec31_sgn[0:0] 1'0 + end + sync always + update \DIV_dec31_sgn $0\DIV_dec31_sgn[0:0] + end + attribute \src "issuer_ls180.v:7821.3-7833.6" + process $proc$issuer_ls180.v:7821$159 + assign { } { } + assign { } { } + assign $0\DIV_dec31_function_unit[11:0] $1\DIV_dec31_function_unit[11:0] + attribute \src "issuer_ls180.v:7822.5-7822.29" + switch \initial + attribute \src "issuer_ls180.v:7822.9-7822.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opc_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\DIV_dec31_function_unit[11:0] \DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_function_unit + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\DIV_dec31_function_unit[11:0] \DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_function_unit + case + assign $1\DIV_dec31_function_unit[11:0] 12'000000000000 + end + sync always + update \DIV_dec31_function_unit $0\DIV_dec31_function_unit[11:0] + end + attribute \src "issuer_ls180.v:7834.3-7846.6" + process $proc$issuer_ls180.v:7834$160 + assign { } { } + assign { } { } + assign $0\DIV_dec31_internal_op[6:0] $1\DIV_dec31_internal_op[6:0] + attribute \src "issuer_ls180.v:7835.5-7835.29" + switch \initial + attribute \src "issuer_ls180.v:7835.9-7835.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opc_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\DIV_dec31_internal_op[6:0] \DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_internal_op + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\DIV_dec31_internal_op[6:0] \DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_internal_op + case + assign $1\DIV_dec31_internal_op[6:0] 7'0000000 + end + sync always + update \DIV_dec31_internal_op $0\DIV_dec31_internal_op[6:0] + end + attribute \src "issuer_ls180.v:7847.3-7859.6" + process $proc$issuer_ls180.v:7847$161 + assign { } { } + assign { } { } + assign $0\DIV_dec31_in1_sel[2:0] $1\DIV_dec31_in1_sel[2:0] + attribute \src "issuer_ls180.v:7848.5-7848.29" + switch \initial + attribute \src "issuer_ls180.v:7848.9-7848.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opc_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\DIV_dec31_in1_sel[2:0] \DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_in1_sel + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\DIV_dec31_in1_sel[2:0] \DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_in1_sel + case + assign $1\DIV_dec31_in1_sel[2:0] 3'000 + end + sync always + update \DIV_dec31_in1_sel $0\DIV_dec31_in1_sel[2:0] + end + attribute \src "issuer_ls180.v:7860.3-7872.6" + process $proc$issuer_ls180.v:7860$162 + assign { } { } + assign { } { } + assign $0\DIV_dec31_in2_sel[3:0] $1\DIV_dec31_in2_sel[3:0] + attribute \src "issuer_ls180.v:7861.5-7861.29" + switch \initial + attribute \src "issuer_ls180.v:7861.9-7861.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opc_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\DIV_dec31_in2_sel[3:0] \DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_in2_sel + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\DIV_dec31_in2_sel[3:0] \DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_in2_sel + case + assign $1\DIV_dec31_in2_sel[3:0] 4'0000 + end + sync always + update \DIV_dec31_in2_sel $0\DIV_dec31_in2_sel[3:0] + end + attribute \src "issuer_ls180.v:7873.3-7885.6" + process $proc$issuer_ls180.v:7873$163 + assign { } { } + assign { } { } + assign $0\DIV_dec31_cr_in[2:0] $1\DIV_dec31_cr_in[2:0] + attribute \src "issuer_ls180.v:7874.5-7874.29" + switch \initial + attribute \src "issuer_ls180.v:7874.9-7874.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opc_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\DIV_dec31_cr_in[2:0] \DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_cr_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\DIV_dec31_cr_in[2:0] \DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_cr_in + case + assign $1\DIV_dec31_cr_in[2:0] 3'000 + end + sync always + update \DIV_dec31_cr_in $0\DIV_dec31_cr_in[2:0] + end + attribute \src "issuer_ls180.v:7886.3-7898.6" + process $proc$issuer_ls180.v:7886$164 + assign { } { } + assign { } { } + assign $0\DIV_dec31_cr_out[2:0] $1\DIV_dec31_cr_out[2:0] + attribute \src "issuer_ls180.v:7887.5-7887.29" + switch \initial + attribute \src "issuer_ls180.v:7887.9-7887.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opc_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\DIV_dec31_cr_out[2:0] \DIV_dec31_dec_sub9_DIV_dec31_dec_sub9_cr_out + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\DIV_dec31_cr_out[2:0] \DIV_dec31_dec_sub11_DIV_dec31_dec_sub11_cr_out + case + assign $1\DIV_dec31_cr_out[2:0] 3'000 + end + sync always + update \DIV_dec31_cr_out $0\DIV_dec31_cr_out[2:0] + end + connect \DIV_dec31_dec_sub11_opcode_in \opcode_in + connect \DIV_dec31_dec_sub9_opcode_in \opcode_in + connect \opc_in \opcode_switch [4:0] + connect \opcode_switch \opcode_in [10:1] +end +attribute \src "issuer_ls180.v:7907.1-8610.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.dec_DIV.dec.DIV_dec31.DIV_dec31_dec_sub11" +attribute \generator "nMigen" +module \DIV_dec31_dec_sub11 + attribute \src "issuer_ls180.v:8424.3-8460.6" + wire width 3 $0\DIV_dec31_dec_sub11_cr_in[2:0] + attribute \src "issuer_ls180.v:8461.3-8497.6" + wire width 3 $0\DIV_dec31_dec_sub11_cr_out[2:0] + attribute \src "issuer_ls180.v:8572.3-8608.6" + wire width 2 $0\DIV_dec31_dec_sub11_cry_in[1:0] + attribute \src "issuer_ls180.v:8202.3-8238.6" + wire $0\DIV_dec31_dec_sub11_cry_out[0:0] + attribute \src "issuer_ls180.v:8091.3-8127.6" + wire width 12 $0\DIV_dec31_dec_sub11_function_unit[11:0] + attribute \src "issuer_ls180.v:8350.3-8386.6" + wire width 3 $0\DIV_dec31_dec_sub11_in1_sel[2:0] + attribute \src "issuer_ls180.v:8387.3-8423.6" + wire width 4 $0\DIV_dec31_dec_sub11_in2_sel[3:0] + attribute \src "issuer_ls180.v:8313.3-8349.6" + wire width 7 $0\DIV_dec31_dec_sub11_internal_op[6:0] + attribute \src "issuer_ls180.v:8128.3-8164.6" + wire $0\DIV_dec31_dec_sub11_inv_a[0:0] + attribute \src "issuer_ls180.v:8165.3-8201.6" + wire $0\DIV_dec31_dec_sub11_inv_out[0:0] + attribute \src "issuer_ls180.v:8239.3-8275.6" + wire $0\DIV_dec31_dec_sub11_is_32b[0:0] + attribute \src "issuer_ls180.v:8498.3-8534.6" + wire width 4 $0\DIV_dec31_dec_sub11_ldst_len[3:0] + attribute \src "issuer_ls180.v:8535.3-8571.6" + wire width 2 $0\DIV_dec31_dec_sub11_rc_sel[1:0] + attribute \src "issuer_ls180.v:8276.3-8312.6" + wire $0\DIV_dec31_dec_sub11_sgn[0:0] + attribute \src "issuer_ls180.v:7908.7-7908.20" + wire $0\initial[0:0] + attribute \src "issuer_ls180.v:8424.3-8460.6" + wire width 3 $1\DIV_dec31_dec_sub11_cr_in[2:0] + attribute \src "issuer_ls180.v:8461.3-8497.6" + wire width 3 $1\DIV_dec31_dec_sub11_cr_out[2:0] + attribute \src "issuer_ls180.v:8572.3-8608.6" + wire width 2 $1\DIV_dec31_dec_sub11_cry_in[1:0] + attribute \src "issuer_ls180.v:8202.3-8238.6" + wire $1\DIV_dec31_dec_sub11_cry_out[0:0] + attribute \src "issuer_ls180.v:8091.3-8127.6" + wire width 12 $1\DIV_dec31_dec_sub11_function_unit[11:0] + attribute \src "issuer_ls180.v:8350.3-8386.6" + wire width 3 $1\DIV_dec31_dec_sub11_in1_sel[2:0] + attribute \src "issuer_ls180.v:8387.3-8423.6" + wire width 4 $1\DIV_dec31_dec_sub11_in2_sel[3:0] + attribute \src "issuer_ls180.v:8313.3-8349.6" + wire width 7 $1\DIV_dec31_dec_sub11_internal_op[6:0] + attribute \src "issuer_ls180.v:8128.3-8164.6" + wire $1\DIV_dec31_dec_sub11_inv_a[0:0] + attribute \src "issuer_ls180.v:8165.3-8201.6" + wire $1\DIV_dec31_dec_sub11_inv_out[0:0] + attribute \src "issuer_ls180.v:8239.3-8275.6" + wire $1\DIV_dec31_dec_sub11_is_32b[0:0] + attribute \src "issuer_ls180.v:8498.3-8534.6" + wire width 4 $1\DIV_dec31_dec_sub11_ldst_len[3:0] + attribute \src "issuer_ls180.v:8535.3-8571.6" + wire width 2 $1\DIV_dec31_dec_sub11_rc_sel[1:0] + attribute \src "issuer_ls180.v:8276.3-8312.6" + wire $1\DIV_dec31_dec_sub11_sgn[0:0] + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 5 \DIV_dec31_dec_sub11_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 6 \DIV_dec31_dec_sub11_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 9 \DIV_dec31_dec_sub11_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 12 \DIV_dec31_dec_sub11_cry_out + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 12 output 1 \DIV_dec31_dec_sub11_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 3 \DIV_dec31_dec_sub11_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 output 4 \DIV_dec31_dec_sub11_in2_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 7 output 2 \DIV_dec31_dec_sub11_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 10 \DIV_dec31_dec_sub11_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 11 \DIV_dec31_dec_sub11_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 13 \DIV_dec31_dec_sub11_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 output 7 \DIV_dec31_dec_sub11_ldst_len + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 8 \DIV_dec31_dec_sub11_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 14 \DIV_dec31_dec_sub11_sgn + attribute \src "issuer_ls180.v:7908.7-7908.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + wire width 32 input 15 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:320" + wire width 5 \opcode_switch + attribute \src "issuer_ls180.v:7908.7-7908.20" + process $proc$issuer_ls180.v:7908$180 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "issuer_ls180.v:8091.3-8127.6" + process $proc$issuer_ls180.v:8091$166 + assign { } { } + assign { } { } + assign $0\DIV_dec31_dec_sub11_function_unit[11:0] $1\DIV_dec31_dec_sub11_function_unit[11:0] + attribute \src "issuer_ls180.v:8092.5-8092.29" + switch \initial + attribute \src "issuer_ls180.v:8092.9-8092.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\DIV_dec31_dec_sub11_function_unit[11:0] 12'001000000000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\DIV_dec31_dec_sub11_function_unit[11:0] 12'001000000000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\DIV_dec31_dec_sub11_function_unit[11:0] 12'001000000000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\DIV_dec31_dec_sub11_function_unit[11:0] 12'001000000000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\DIV_dec31_dec_sub11_function_unit[11:0] 12'001000000000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\DIV_dec31_dec_sub11_function_unit[11:0] 12'001000000000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\DIV_dec31_dec_sub11_function_unit[11:0] 12'001000000000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\DIV_dec31_dec_sub11_function_unit[11:0] 12'001000000000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\DIV_dec31_dec_sub11_function_unit[11:0] 12'001000000000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\DIV_dec31_dec_sub11_function_unit[11:0] 12'001000000000 + case + assign $1\DIV_dec31_dec_sub11_function_unit[11:0] 12'000000000000 + end + sync always + update \DIV_dec31_dec_sub11_function_unit $0\DIV_dec31_dec_sub11_function_unit[11:0] + end + attribute \src "issuer_ls180.v:8128.3-8164.6" + process $proc$issuer_ls180.v:8128$167 + assign { } { } + assign { } { } + assign $0\DIV_dec31_dec_sub11_inv_a[0:0] $1\DIV_dec31_dec_sub11_inv_a[0:0] + attribute \src "issuer_ls180.v:8129.5-8129.29" + switch \initial + attribute \src "issuer_ls180.v:8129.9-8129.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\DIV_dec31_dec_sub11_inv_a[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\DIV_dec31_dec_sub11_inv_a[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\DIV_dec31_dec_sub11_inv_a[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\DIV_dec31_dec_sub11_inv_a[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\DIV_dec31_dec_sub11_inv_a[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\DIV_dec31_dec_sub11_inv_a[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\DIV_dec31_dec_sub11_inv_a[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\DIV_dec31_dec_sub11_inv_a[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\DIV_dec31_dec_sub11_inv_a[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\DIV_dec31_dec_sub11_inv_a[0:0] 1'0 + case + assign $1\DIV_dec31_dec_sub11_inv_a[0:0] 1'0 + end + sync always + update \DIV_dec31_dec_sub11_inv_a $0\DIV_dec31_dec_sub11_inv_a[0:0] + end + attribute \src "issuer_ls180.v:8165.3-8201.6" + process $proc$issuer_ls180.v:8165$168 + assign { } { } + assign { } { } + assign $0\DIV_dec31_dec_sub11_inv_out[0:0] $1\DIV_dec31_dec_sub11_inv_out[0:0] + attribute \src "issuer_ls180.v:8166.5-8166.29" + switch \initial + attribute \src "issuer_ls180.v:8166.9-8166.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\DIV_dec31_dec_sub11_inv_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\DIV_dec31_dec_sub11_inv_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\DIV_dec31_dec_sub11_inv_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\DIV_dec31_dec_sub11_inv_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\DIV_dec31_dec_sub11_inv_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\DIV_dec31_dec_sub11_inv_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\DIV_dec31_dec_sub11_inv_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\DIV_dec31_dec_sub11_inv_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\DIV_dec31_dec_sub11_inv_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\DIV_dec31_dec_sub11_inv_out[0:0] 1'0 + case + assign $1\DIV_dec31_dec_sub11_inv_out[0:0] 1'0 + end + sync always + update \DIV_dec31_dec_sub11_inv_out $0\DIV_dec31_dec_sub11_inv_out[0:0] + end + attribute \src "issuer_ls180.v:8202.3-8238.6" + process $proc$issuer_ls180.v:8202$169 + assign { } { } + assign { } { } + assign $0\DIV_dec31_dec_sub11_cry_out[0:0] $1\DIV_dec31_dec_sub11_cry_out[0:0] + attribute \src "issuer_ls180.v:8203.5-8203.29" + switch \initial + attribute \src "issuer_ls180.v:8203.9-8203.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\DIV_dec31_dec_sub11_cry_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\DIV_dec31_dec_sub11_cry_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\DIV_dec31_dec_sub11_cry_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\DIV_dec31_dec_sub11_cry_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\DIV_dec31_dec_sub11_cry_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\DIV_dec31_dec_sub11_cry_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\DIV_dec31_dec_sub11_cry_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\DIV_dec31_dec_sub11_cry_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\DIV_dec31_dec_sub11_cry_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\DIV_dec31_dec_sub11_cry_out[0:0] 1'0 + case + assign $1\DIV_dec31_dec_sub11_cry_out[0:0] 1'0 + end + sync always + update \DIV_dec31_dec_sub11_cry_out $0\DIV_dec31_dec_sub11_cry_out[0:0] + end + attribute \src "issuer_ls180.v:8239.3-8275.6" + process $proc$issuer_ls180.v:8239$170 + assign { } { } + assign { } { } + assign $0\DIV_dec31_dec_sub11_is_32b[0:0] $1\DIV_dec31_dec_sub11_is_32b[0:0] + attribute \src "issuer_ls180.v:8240.5-8240.29" + switch \initial + attribute \src "issuer_ls180.v:8240.9-8240.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\DIV_dec31_dec_sub11_is_32b[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\DIV_dec31_dec_sub11_is_32b[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\DIV_dec31_dec_sub11_is_32b[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\DIV_dec31_dec_sub11_is_32b[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\DIV_dec31_dec_sub11_is_32b[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\DIV_dec31_dec_sub11_is_32b[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\DIV_dec31_dec_sub11_is_32b[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\DIV_dec31_dec_sub11_is_32b[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\DIV_dec31_dec_sub11_is_32b[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\DIV_dec31_dec_sub11_is_32b[0:0] 1'1 + case + assign $1\DIV_dec31_dec_sub11_is_32b[0:0] 1'0 + end + sync always + update \DIV_dec31_dec_sub11_is_32b $0\DIV_dec31_dec_sub11_is_32b[0:0] + end + attribute \src "issuer_ls180.v:8276.3-8312.6" + process $proc$issuer_ls180.v:8276$171 + assign { } { } + assign { } { } + assign $0\DIV_dec31_dec_sub11_sgn[0:0] $1\DIV_dec31_dec_sub11_sgn[0:0] + attribute \src "issuer_ls180.v:8277.5-8277.29" + switch \initial + attribute \src "issuer_ls180.v:8277.9-8277.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\DIV_dec31_dec_sub11_sgn[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\DIV_dec31_dec_sub11_sgn[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\DIV_dec31_dec_sub11_sgn[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\DIV_dec31_dec_sub11_sgn[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\DIV_dec31_dec_sub11_sgn[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\DIV_dec31_dec_sub11_sgn[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\DIV_dec31_dec_sub11_sgn[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\DIV_dec31_dec_sub11_sgn[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\DIV_dec31_dec_sub11_sgn[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\DIV_dec31_dec_sub11_sgn[0:0] 1'1 + case + assign $1\DIV_dec31_dec_sub11_sgn[0:0] 1'0 + end + sync always + update \DIV_dec31_dec_sub11_sgn $0\DIV_dec31_dec_sub11_sgn[0:0] + end + attribute \src "issuer_ls180.v:8313.3-8349.6" + process $proc$issuer_ls180.v:8313$172 + assign { } { } + assign { } { } + assign $0\DIV_dec31_dec_sub11_internal_op[6:0] $1\DIV_dec31_dec_sub11_internal_op[6:0] + attribute \src "issuer_ls180.v:8314.5-8314.29" + switch \initial + attribute \src "issuer_ls180.v:8314.9-8314.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\DIV_dec31_dec_sub11_internal_op[6:0] 7'0011110 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\DIV_dec31_dec_sub11_internal_op[6:0] 7'0011110 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\DIV_dec31_dec_sub11_internal_op[6:0] 7'0011110 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\DIV_dec31_dec_sub11_internal_op[6:0] 7'0011110 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\DIV_dec31_dec_sub11_internal_op[6:0] 7'0011101 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\DIV_dec31_dec_sub11_internal_op[6:0] 7'0011101 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\DIV_dec31_dec_sub11_internal_op[6:0] 7'0011101 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\DIV_dec31_dec_sub11_internal_op[6:0] 7'0011101 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\DIV_dec31_dec_sub11_internal_op[6:0] 7'0101111 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\DIV_dec31_dec_sub11_internal_op[6:0] 7'0101111 + case + assign $1\DIV_dec31_dec_sub11_internal_op[6:0] 7'0000000 + end + sync always + update \DIV_dec31_dec_sub11_internal_op $0\DIV_dec31_dec_sub11_internal_op[6:0] + end + attribute \src "issuer_ls180.v:8350.3-8386.6" + process $proc$issuer_ls180.v:8350$173 + assign { } { } + assign { } { } + assign $0\DIV_dec31_dec_sub11_in1_sel[2:0] $1\DIV_dec31_dec_sub11_in1_sel[2:0] + attribute \src "issuer_ls180.v:8351.5-8351.29" + switch \initial + attribute \src "issuer_ls180.v:8351.9-8351.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\DIV_dec31_dec_sub11_in1_sel[2:0] 3'001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\DIV_dec31_dec_sub11_in1_sel[2:0] 3'001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\DIV_dec31_dec_sub11_in1_sel[2:0] 3'001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\DIV_dec31_dec_sub11_in1_sel[2:0] 3'001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\DIV_dec31_dec_sub11_in1_sel[2:0] 3'001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\DIV_dec31_dec_sub11_in1_sel[2:0] 3'001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\DIV_dec31_dec_sub11_in1_sel[2:0] 3'001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\DIV_dec31_dec_sub11_in1_sel[2:0] 3'001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\DIV_dec31_dec_sub11_in1_sel[2:0] 3'001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\DIV_dec31_dec_sub11_in1_sel[2:0] 3'001 + case + assign $1\DIV_dec31_dec_sub11_in1_sel[2:0] 3'000 + end + sync always + update \DIV_dec31_dec_sub11_in1_sel $0\DIV_dec31_dec_sub11_in1_sel[2:0] + end + attribute \src "issuer_ls180.v:8387.3-8423.6" + process $proc$issuer_ls180.v:8387$174 + assign { } { } + assign { } { } + assign $0\DIV_dec31_dec_sub11_in2_sel[3:0] $1\DIV_dec31_dec_sub11_in2_sel[3:0] + attribute \src "issuer_ls180.v:8388.5-8388.29" + switch \initial + attribute \src "issuer_ls180.v:8388.9-8388.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\DIV_dec31_dec_sub11_in2_sel[3:0] 4'0001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\DIV_dec31_dec_sub11_in2_sel[3:0] 4'0001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\DIV_dec31_dec_sub11_in2_sel[3:0] 4'0001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\DIV_dec31_dec_sub11_in2_sel[3:0] 4'0001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\DIV_dec31_dec_sub11_in2_sel[3:0] 4'0001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\DIV_dec31_dec_sub11_in2_sel[3:0] 4'0001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\DIV_dec31_dec_sub11_in2_sel[3:0] 4'0001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\DIV_dec31_dec_sub11_in2_sel[3:0] 4'0001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\DIV_dec31_dec_sub11_in2_sel[3:0] 4'0001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\DIV_dec31_dec_sub11_in2_sel[3:0] 4'0001 + case + assign $1\DIV_dec31_dec_sub11_in2_sel[3:0] 4'0000 + end + sync always + update \DIV_dec31_dec_sub11_in2_sel $0\DIV_dec31_dec_sub11_in2_sel[3:0] + end + attribute \src "issuer_ls180.v:8424.3-8460.6" + process $proc$issuer_ls180.v:8424$175 + assign { } { } + assign { } { } + assign $0\DIV_dec31_dec_sub11_cr_in[2:0] $1\DIV_dec31_dec_sub11_cr_in[2:0] + attribute \src "issuer_ls180.v:8425.5-8425.29" + switch \initial + attribute \src "issuer_ls180.v:8425.9-8425.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\DIV_dec31_dec_sub11_cr_in[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\DIV_dec31_dec_sub11_cr_in[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\DIV_dec31_dec_sub11_cr_in[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\DIV_dec31_dec_sub11_cr_in[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\DIV_dec31_dec_sub11_cr_in[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\DIV_dec31_dec_sub11_cr_in[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\DIV_dec31_dec_sub11_cr_in[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\DIV_dec31_dec_sub11_cr_in[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\DIV_dec31_dec_sub11_cr_in[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\DIV_dec31_dec_sub11_cr_in[2:0] 3'000 + case + assign $1\DIV_dec31_dec_sub11_cr_in[2:0] 3'000 + end + sync always + update \DIV_dec31_dec_sub11_cr_in $0\DIV_dec31_dec_sub11_cr_in[2:0] + end + attribute \src "issuer_ls180.v:8461.3-8497.6" + process $proc$issuer_ls180.v:8461$176 + assign { } { } + assign { } { } + assign $0\DIV_dec31_dec_sub11_cr_out[2:0] $1\DIV_dec31_dec_sub11_cr_out[2:0] + attribute \src "issuer_ls180.v:8462.5-8462.29" + switch \initial + attribute \src "issuer_ls180.v:8462.9-8462.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\DIV_dec31_dec_sub11_cr_out[2:0] 3'001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\DIV_dec31_dec_sub11_cr_out[2:0] 3'001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\DIV_dec31_dec_sub11_cr_out[2:0] 3'001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\DIV_dec31_dec_sub11_cr_out[2:0] 3'001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\DIV_dec31_dec_sub11_cr_out[2:0] 3'001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\DIV_dec31_dec_sub11_cr_out[2:0] 3'001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\DIV_dec31_dec_sub11_cr_out[2:0] 3'001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\DIV_dec31_dec_sub11_cr_out[2:0] 3'001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\DIV_dec31_dec_sub11_cr_out[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\DIV_dec31_dec_sub11_cr_out[2:0] 3'000 + case + assign $1\DIV_dec31_dec_sub11_cr_out[2:0] 3'000 + end + sync always + update \DIV_dec31_dec_sub11_cr_out $0\DIV_dec31_dec_sub11_cr_out[2:0] + end + attribute \src "issuer_ls180.v:8498.3-8534.6" + process $proc$issuer_ls180.v:8498$177 + assign { } { } + assign { } { } + assign $0\DIV_dec31_dec_sub11_ldst_len[3:0] $1\DIV_dec31_dec_sub11_ldst_len[3:0] + attribute \src "issuer_ls180.v:8499.5-8499.29" + switch \initial + attribute \src "issuer_ls180.v:8499.9-8499.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\DIV_dec31_dec_sub11_ldst_len[3:0] 4'0000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\DIV_dec31_dec_sub11_ldst_len[3:0] 4'0000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\DIV_dec31_dec_sub11_ldst_len[3:0] 4'0000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\DIV_dec31_dec_sub11_ldst_len[3:0] 4'0000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\DIV_dec31_dec_sub11_ldst_len[3:0] 4'0000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\DIV_dec31_dec_sub11_ldst_len[3:0] 4'0000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\DIV_dec31_dec_sub11_ldst_len[3:0] 4'0000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\DIV_dec31_dec_sub11_ldst_len[3:0] 4'0000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\DIV_dec31_dec_sub11_ldst_len[3:0] 4'0000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\DIV_dec31_dec_sub11_ldst_len[3:0] 4'0000 + case + assign $1\DIV_dec31_dec_sub11_ldst_len[3:0] 4'0000 + end + sync always + update \DIV_dec31_dec_sub11_ldst_len $0\DIV_dec31_dec_sub11_ldst_len[3:0] + end + attribute \src "issuer_ls180.v:8535.3-8571.6" + process $proc$issuer_ls180.v:8535$178 + assign { } { } + assign { } { } + assign $0\DIV_dec31_dec_sub11_rc_sel[1:0] $1\DIV_dec31_dec_sub11_rc_sel[1:0] + attribute \src "issuer_ls180.v:8536.5-8536.29" + switch \initial + attribute \src "issuer_ls180.v:8536.9-8536.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\DIV_dec31_dec_sub11_rc_sel[1:0] 2'10 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\DIV_dec31_dec_sub11_rc_sel[1:0] 2'10 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\DIV_dec31_dec_sub11_rc_sel[1:0] 2'10 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\DIV_dec31_dec_sub11_rc_sel[1:0] 2'10 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\DIV_dec31_dec_sub11_rc_sel[1:0] 2'10 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\DIV_dec31_dec_sub11_rc_sel[1:0] 2'10 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\DIV_dec31_dec_sub11_rc_sel[1:0] 2'10 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\DIV_dec31_dec_sub11_rc_sel[1:0] 2'10 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\DIV_dec31_dec_sub11_rc_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\DIV_dec31_dec_sub11_rc_sel[1:0] 2'00 + case + assign $1\DIV_dec31_dec_sub11_rc_sel[1:0] 2'00 + end + sync always + update \DIV_dec31_dec_sub11_rc_sel $0\DIV_dec31_dec_sub11_rc_sel[1:0] + end + attribute \src "issuer_ls180.v:8572.3-8608.6" + process $proc$issuer_ls180.v:8572$179 + assign { } { } + assign { } { } + assign $0\DIV_dec31_dec_sub11_cry_in[1:0] $1\DIV_dec31_dec_sub11_cry_in[1:0] + attribute \src "issuer_ls180.v:8573.5-8573.29" + switch \initial + attribute \src "issuer_ls180.v:8573.9-8573.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\DIV_dec31_dec_sub11_cry_in[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\DIV_dec31_dec_sub11_cry_in[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\DIV_dec31_dec_sub11_cry_in[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\DIV_dec31_dec_sub11_cry_in[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\DIV_dec31_dec_sub11_cry_in[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\DIV_dec31_dec_sub11_cry_in[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\DIV_dec31_dec_sub11_cry_in[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\DIV_dec31_dec_sub11_cry_in[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\DIV_dec31_dec_sub11_cry_in[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\DIV_dec31_dec_sub11_cry_in[1:0] 2'00 + case + assign $1\DIV_dec31_dec_sub11_cry_in[1:0] 2'00 + end + sync always + update \DIV_dec31_dec_sub11_cry_in $0\DIV_dec31_dec_sub11_cry_in[1:0] + end + connect \opcode_switch \opcode_in [10:6] +end +attribute \src "issuer_ls180.v:8614.1-9317.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.dec_DIV.dec.DIV_dec31.DIV_dec31_dec_sub9" +attribute \generator "nMigen" +module \DIV_dec31_dec_sub9 + attribute \src "issuer_ls180.v:9131.3-9167.6" + wire width 3 $0\DIV_dec31_dec_sub9_cr_in[2:0] + attribute \src "issuer_ls180.v:9168.3-9204.6" + wire width 3 $0\DIV_dec31_dec_sub9_cr_out[2:0] + attribute \src "issuer_ls180.v:9279.3-9315.6" + wire width 2 $0\DIV_dec31_dec_sub9_cry_in[1:0] + attribute \src "issuer_ls180.v:8909.3-8945.6" + wire $0\DIV_dec31_dec_sub9_cry_out[0:0] + attribute \src "issuer_ls180.v:8798.3-8834.6" + wire width 12 $0\DIV_dec31_dec_sub9_function_unit[11:0] + attribute \src "issuer_ls180.v:9057.3-9093.6" + wire width 3 $0\DIV_dec31_dec_sub9_in1_sel[2:0] + attribute \src "issuer_ls180.v:9094.3-9130.6" + wire width 4 $0\DIV_dec31_dec_sub9_in2_sel[3:0] + attribute \src "issuer_ls180.v:9020.3-9056.6" + wire width 7 $0\DIV_dec31_dec_sub9_internal_op[6:0] + attribute \src "issuer_ls180.v:8835.3-8871.6" + wire $0\DIV_dec31_dec_sub9_inv_a[0:0] + attribute \src "issuer_ls180.v:8872.3-8908.6" + wire $0\DIV_dec31_dec_sub9_inv_out[0:0] + attribute \src "issuer_ls180.v:8946.3-8982.6" + wire $0\DIV_dec31_dec_sub9_is_32b[0:0] + attribute \src "issuer_ls180.v:9205.3-9241.6" + wire width 4 $0\DIV_dec31_dec_sub9_ldst_len[3:0] + attribute \src "issuer_ls180.v:9242.3-9278.6" + wire width 2 $0\DIV_dec31_dec_sub9_rc_sel[1:0] + attribute \src "issuer_ls180.v:8983.3-9019.6" + wire $0\DIV_dec31_dec_sub9_sgn[0:0] + attribute \src "issuer_ls180.v:8615.7-8615.20" + wire $0\initial[0:0] + attribute \src "issuer_ls180.v:9131.3-9167.6" + wire width 3 $1\DIV_dec31_dec_sub9_cr_in[2:0] + attribute \src "issuer_ls180.v:9168.3-9204.6" + wire width 3 $1\DIV_dec31_dec_sub9_cr_out[2:0] + attribute \src "issuer_ls180.v:9279.3-9315.6" + wire width 2 $1\DIV_dec31_dec_sub9_cry_in[1:0] + attribute \src "issuer_ls180.v:8909.3-8945.6" + wire $1\DIV_dec31_dec_sub9_cry_out[0:0] + attribute \src "issuer_ls180.v:8798.3-8834.6" + wire width 12 $1\DIV_dec31_dec_sub9_function_unit[11:0] + attribute \src "issuer_ls180.v:9057.3-9093.6" + wire width 3 $1\DIV_dec31_dec_sub9_in1_sel[2:0] + attribute \src "issuer_ls180.v:9094.3-9130.6" + wire width 4 $1\DIV_dec31_dec_sub9_in2_sel[3:0] + attribute \src "issuer_ls180.v:9020.3-9056.6" + wire width 7 $1\DIV_dec31_dec_sub9_internal_op[6:0] + attribute \src "issuer_ls180.v:8835.3-8871.6" + wire $1\DIV_dec31_dec_sub9_inv_a[0:0] + attribute \src "issuer_ls180.v:8872.3-8908.6" + wire $1\DIV_dec31_dec_sub9_inv_out[0:0] + attribute \src "issuer_ls180.v:8946.3-8982.6" + wire $1\DIV_dec31_dec_sub9_is_32b[0:0] + attribute \src "issuer_ls180.v:9205.3-9241.6" + wire width 4 $1\DIV_dec31_dec_sub9_ldst_len[3:0] + attribute \src "issuer_ls180.v:9242.3-9278.6" + wire width 2 $1\DIV_dec31_dec_sub9_rc_sel[1:0] + attribute \src "issuer_ls180.v:8983.3-9019.6" + wire $1\DIV_dec31_dec_sub9_sgn[0:0] + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 5 \DIV_dec31_dec_sub9_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 6 \DIV_dec31_dec_sub9_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 9 \DIV_dec31_dec_sub9_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 12 \DIV_dec31_dec_sub9_cry_out + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 12 output 1 \DIV_dec31_dec_sub9_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 3 \DIV_dec31_dec_sub9_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 output 4 \DIV_dec31_dec_sub9_in2_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 7 output 2 \DIV_dec31_dec_sub9_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 10 \DIV_dec31_dec_sub9_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 11 \DIV_dec31_dec_sub9_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 13 \DIV_dec31_dec_sub9_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 output 7 \DIV_dec31_dec_sub9_ldst_len + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 8 \DIV_dec31_dec_sub9_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 14 \DIV_dec31_dec_sub9_sgn + attribute \src "issuer_ls180.v:8615.7-8615.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + wire width 32 input 15 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:320" + wire width 5 \opcode_switch + attribute \src "issuer_ls180.v:8615.7-8615.20" + process $proc$issuer_ls180.v:8615$195 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "issuer_ls180.v:8798.3-8834.6" + process $proc$issuer_ls180.v:8798$181 + assign { } { } + assign { } { } + assign $0\DIV_dec31_dec_sub9_function_unit[11:0] $1\DIV_dec31_dec_sub9_function_unit[11:0] + attribute \src "issuer_ls180.v:8799.5-8799.29" + switch \initial + attribute \src "issuer_ls180.v:8799.9-8799.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\DIV_dec31_dec_sub9_function_unit[11:0] 12'001000000000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\DIV_dec31_dec_sub9_function_unit[11:0] 12'001000000000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\DIV_dec31_dec_sub9_function_unit[11:0] 12'001000000000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\DIV_dec31_dec_sub9_function_unit[11:0] 12'001000000000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\DIV_dec31_dec_sub9_function_unit[11:0] 12'001000000000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\DIV_dec31_dec_sub9_function_unit[11:0] 12'001000000000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\DIV_dec31_dec_sub9_function_unit[11:0] 12'001000000000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\DIV_dec31_dec_sub9_function_unit[11:0] 12'001000000000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\DIV_dec31_dec_sub9_function_unit[11:0] 12'001000000000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\DIV_dec31_dec_sub9_function_unit[11:0] 12'001000000000 + case + assign $1\DIV_dec31_dec_sub9_function_unit[11:0] 12'000000000000 + end + sync always + update \DIV_dec31_dec_sub9_function_unit $0\DIV_dec31_dec_sub9_function_unit[11:0] + end + attribute \src "issuer_ls180.v:8835.3-8871.6" + process $proc$issuer_ls180.v:8835$182 + assign { } { } + assign { } { } + assign $0\DIV_dec31_dec_sub9_inv_a[0:0] $1\DIV_dec31_dec_sub9_inv_a[0:0] + attribute \src "issuer_ls180.v:8836.5-8836.29" + switch \initial + attribute \src "issuer_ls180.v:8836.9-8836.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\DIV_dec31_dec_sub9_inv_a[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\DIV_dec31_dec_sub9_inv_a[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\DIV_dec31_dec_sub9_inv_a[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\DIV_dec31_dec_sub9_inv_a[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\DIV_dec31_dec_sub9_inv_a[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\DIV_dec31_dec_sub9_inv_a[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\DIV_dec31_dec_sub9_inv_a[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\DIV_dec31_dec_sub9_inv_a[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\DIV_dec31_dec_sub9_inv_a[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\DIV_dec31_dec_sub9_inv_a[0:0] 1'0 + case + assign $1\DIV_dec31_dec_sub9_inv_a[0:0] 1'0 + end + sync always + update \DIV_dec31_dec_sub9_inv_a $0\DIV_dec31_dec_sub9_inv_a[0:0] + end + attribute \src "issuer_ls180.v:8872.3-8908.6" + process $proc$issuer_ls180.v:8872$183 + assign { } { } + assign { } { } + assign $0\DIV_dec31_dec_sub9_inv_out[0:0] $1\DIV_dec31_dec_sub9_inv_out[0:0] + attribute \src "issuer_ls180.v:8873.5-8873.29" + switch \initial + attribute \src "issuer_ls180.v:8873.9-8873.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\DIV_dec31_dec_sub9_inv_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\DIV_dec31_dec_sub9_inv_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\DIV_dec31_dec_sub9_inv_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\DIV_dec31_dec_sub9_inv_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\DIV_dec31_dec_sub9_inv_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\DIV_dec31_dec_sub9_inv_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\DIV_dec31_dec_sub9_inv_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\DIV_dec31_dec_sub9_inv_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\DIV_dec31_dec_sub9_inv_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\DIV_dec31_dec_sub9_inv_out[0:0] 1'0 + case + assign $1\DIV_dec31_dec_sub9_inv_out[0:0] 1'0 + end + sync always + update \DIV_dec31_dec_sub9_inv_out $0\DIV_dec31_dec_sub9_inv_out[0:0] + end + attribute \src "issuer_ls180.v:8909.3-8945.6" + process $proc$issuer_ls180.v:8909$184 + assign { } { } + assign { } { } + assign $0\DIV_dec31_dec_sub9_cry_out[0:0] $1\DIV_dec31_dec_sub9_cry_out[0:0] + attribute \src "issuer_ls180.v:8910.5-8910.29" + switch \initial + attribute \src "issuer_ls180.v:8910.9-8910.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\DIV_dec31_dec_sub9_cry_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\DIV_dec31_dec_sub9_cry_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\DIV_dec31_dec_sub9_cry_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\DIV_dec31_dec_sub9_cry_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\DIV_dec31_dec_sub9_cry_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\DIV_dec31_dec_sub9_cry_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\DIV_dec31_dec_sub9_cry_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\DIV_dec31_dec_sub9_cry_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\DIV_dec31_dec_sub9_cry_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\DIV_dec31_dec_sub9_cry_out[0:0] 1'0 + case + assign $1\DIV_dec31_dec_sub9_cry_out[0:0] 1'0 + end + sync always + update \DIV_dec31_dec_sub9_cry_out $0\DIV_dec31_dec_sub9_cry_out[0:0] + end + attribute \src "issuer_ls180.v:8946.3-8982.6" + process $proc$issuer_ls180.v:8946$185 + assign { } { } + assign { } { } + assign $0\DIV_dec31_dec_sub9_is_32b[0:0] $1\DIV_dec31_dec_sub9_is_32b[0:0] + attribute \src "issuer_ls180.v:8947.5-8947.29" + switch \initial + attribute \src "issuer_ls180.v:8947.9-8947.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\DIV_dec31_dec_sub9_is_32b[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\DIV_dec31_dec_sub9_is_32b[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\DIV_dec31_dec_sub9_is_32b[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\DIV_dec31_dec_sub9_is_32b[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\DIV_dec31_dec_sub9_is_32b[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\DIV_dec31_dec_sub9_is_32b[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\DIV_dec31_dec_sub9_is_32b[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\DIV_dec31_dec_sub9_is_32b[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\DIV_dec31_dec_sub9_is_32b[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\DIV_dec31_dec_sub9_is_32b[0:0] 1'0 + case + assign $1\DIV_dec31_dec_sub9_is_32b[0:0] 1'0 + end + sync always + update \DIV_dec31_dec_sub9_is_32b $0\DIV_dec31_dec_sub9_is_32b[0:0] + end + attribute \src "issuer_ls180.v:8983.3-9019.6" + process $proc$issuer_ls180.v:8983$186 + assign { } { } + assign { } { } + assign $0\DIV_dec31_dec_sub9_sgn[0:0] $1\DIV_dec31_dec_sub9_sgn[0:0] + attribute \src "issuer_ls180.v:8984.5-8984.29" + switch \initial + attribute \src "issuer_ls180.v:8984.9-8984.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\DIV_dec31_dec_sub9_sgn[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\DIV_dec31_dec_sub9_sgn[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\DIV_dec31_dec_sub9_sgn[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\DIV_dec31_dec_sub9_sgn[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\DIV_dec31_dec_sub9_sgn[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\DIV_dec31_dec_sub9_sgn[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\DIV_dec31_dec_sub9_sgn[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\DIV_dec31_dec_sub9_sgn[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\DIV_dec31_dec_sub9_sgn[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\DIV_dec31_dec_sub9_sgn[0:0] 1'1 + case + assign $1\DIV_dec31_dec_sub9_sgn[0:0] 1'0 + end + sync always + update \DIV_dec31_dec_sub9_sgn $0\DIV_dec31_dec_sub9_sgn[0:0] + end + attribute \src "issuer_ls180.v:9020.3-9056.6" + process $proc$issuer_ls180.v:9020$187 + assign { } { } + assign { } { } + assign $0\DIV_dec31_dec_sub9_internal_op[6:0] $1\DIV_dec31_dec_sub9_internal_op[6:0] + attribute \src "issuer_ls180.v:9021.5-9021.29" + switch \initial + attribute \src "issuer_ls180.v:9021.9-9021.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\DIV_dec31_dec_sub9_internal_op[6:0] 7'0011110 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\DIV_dec31_dec_sub9_internal_op[6:0] 7'0011110 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\DIV_dec31_dec_sub9_internal_op[6:0] 7'0011110 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\DIV_dec31_dec_sub9_internal_op[6:0] 7'0011110 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\DIV_dec31_dec_sub9_internal_op[6:0] 7'0011101 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\DIV_dec31_dec_sub9_internal_op[6:0] 7'0011101 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\DIV_dec31_dec_sub9_internal_op[6:0] 7'0011101 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\DIV_dec31_dec_sub9_internal_op[6:0] 7'0011101 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\DIV_dec31_dec_sub9_internal_op[6:0] 7'0101111 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\DIV_dec31_dec_sub9_internal_op[6:0] 7'0101111 + case + assign $1\DIV_dec31_dec_sub9_internal_op[6:0] 7'0000000 + end + sync always + update \DIV_dec31_dec_sub9_internal_op $0\DIV_dec31_dec_sub9_internal_op[6:0] + end + attribute \src "issuer_ls180.v:9057.3-9093.6" + process $proc$issuer_ls180.v:9057$188 + assign { } { } + assign { } { } + assign $0\DIV_dec31_dec_sub9_in1_sel[2:0] $1\DIV_dec31_dec_sub9_in1_sel[2:0] + attribute \src "issuer_ls180.v:9058.5-9058.29" + switch \initial + attribute \src "issuer_ls180.v:9058.9-9058.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\DIV_dec31_dec_sub9_in1_sel[2:0] 3'001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\DIV_dec31_dec_sub9_in1_sel[2:0] 3'001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\DIV_dec31_dec_sub9_in1_sel[2:0] 3'001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\DIV_dec31_dec_sub9_in1_sel[2:0] 3'001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\DIV_dec31_dec_sub9_in1_sel[2:0] 3'001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\DIV_dec31_dec_sub9_in1_sel[2:0] 3'001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\DIV_dec31_dec_sub9_in1_sel[2:0] 3'001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\DIV_dec31_dec_sub9_in1_sel[2:0] 3'001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\DIV_dec31_dec_sub9_in1_sel[2:0] 3'001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\DIV_dec31_dec_sub9_in1_sel[2:0] 3'001 + case + assign $1\DIV_dec31_dec_sub9_in1_sel[2:0] 3'000 + end + sync always + update \DIV_dec31_dec_sub9_in1_sel $0\DIV_dec31_dec_sub9_in1_sel[2:0] + end + attribute \src "issuer_ls180.v:9094.3-9130.6" + process $proc$issuer_ls180.v:9094$189 + assign { } { } + assign { } { } + assign $0\DIV_dec31_dec_sub9_in2_sel[3:0] $1\DIV_dec31_dec_sub9_in2_sel[3:0] + attribute \src "issuer_ls180.v:9095.5-9095.29" + switch \initial + attribute \src "issuer_ls180.v:9095.9-9095.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\DIV_dec31_dec_sub9_in2_sel[3:0] 4'0001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\DIV_dec31_dec_sub9_in2_sel[3:0] 4'0001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\DIV_dec31_dec_sub9_in2_sel[3:0] 4'0001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\DIV_dec31_dec_sub9_in2_sel[3:0] 4'0001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\DIV_dec31_dec_sub9_in2_sel[3:0] 4'0001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\DIV_dec31_dec_sub9_in2_sel[3:0] 4'0001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\DIV_dec31_dec_sub9_in2_sel[3:0] 4'0001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\DIV_dec31_dec_sub9_in2_sel[3:0] 4'0001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\DIV_dec31_dec_sub9_in2_sel[3:0] 4'0001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\DIV_dec31_dec_sub9_in2_sel[3:0] 4'0001 + case + assign $1\DIV_dec31_dec_sub9_in2_sel[3:0] 4'0000 + end + sync always + update \DIV_dec31_dec_sub9_in2_sel $0\DIV_dec31_dec_sub9_in2_sel[3:0] + end + attribute \src "issuer_ls180.v:9131.3-9167.6" + process $proc$issuer_ls180.v:9131$190 + assign { } { } + assign { } { } + assign $0\DIV_dec31_dec_sub9_cr_in[2:0] $1\DIV_dec31_dec_sub9_cr_in[2:0] + attribute \src "issuer_ls180.v:9132.5-9132.29" + switch \initial + attribute \src "issuer_ls180.v:9132.9-9132.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\DIV_dec31_dec_sub9_cr_in[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\DIV_dec31_dec_sub9_cr_in[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\DIV_dec31_dec_sub9_cr_in[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\DIV_dec31_dec_sub9_cr_in[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\DIV_dec31_dec_sub9_cr_in[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\DIV_dec31_dec_sub9_cr_in[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\DIV_dec31_dec_sub9_cr_in[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\DIV_dec31_dec_sub9_cr_in[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\DIV_dec31_dec_sub9_cr_in[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\DIV_dec31_dec_sub9_cr_in[2:0] 3'000 + case + assign $1\DIV_dec31_dec_sub9_cr_in[2:0] 3'000 + end + sync always + update \DIV_dec31_dec_sub9_cr_in $0\DIV_dec31_dec_sub9_cr_in[2:0] + end + attribute \src "issuer_ls180.v:9168.3-9204.6" + process $proc$issuer_ls180.v:9168$191 + assign { } { } + assign { } { } + assign $0\DIV_dec31_dec_sub9_cr_out[2:0] $1\DIV_dec31_dec_sub9_cr_out[2:0] + attribute \src "issuer_ls180.v:9169.5-9169.29" + switch \initial + attribute \src "issuer_ls180.v:9169.9-9169.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\DIV_dec31_dec_sub9_cr_out[2:0] 3'001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\DIV_dec31_dec_sub9_cr_out[2:0] 3'001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\DIV_dec31_dec_sub9_cr_out[2:0] 3'001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\DIV_dec31_dec_sub9_cr_out[2:0] 3'001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\DIV_dec31_dec_sub9_cr_out[2:0] 3'001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\DIV_dec31_dec_sub9_cr_out[2:0] 3'001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\DIV_dec31_dec_sub9_cr_out[2:0] 3'001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\DIV_dec31_dec_sub9_cr_out[2:0] 3'001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\DIV_dec31_dec_sub9_cr_out[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\DIV_dec31_dec_sub9_cr_out[2:0] 3'000 + case + assign $1\DIV_dec31_dec_sub9_cr_out[2:0] 3'000 + end + sync always + update \DIV_dec31_dec_sub9_cr_out $0\DIV_dec31_dec_sub9_cr_out[2:0] + end + attribute \src "issuer_ls180.v:9205.3-9241.6" + process $proc$issuer_ls180.v:9205$192 + assign { } { } + assign { } { } + assign $0\DIV_dec31_dec_sub9_ldst_len[3:0] $1\DIV_dec31_dec_sub9_ldst_len[3:0] + attribute \src "issuer_ls180.v:9206.5-9206.29" + switch \initial + attribute \src "issuer_ls180.v:9206.9-9206.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\DIV_dec31_dec_sub9_ldst_len[3:0] 4'0000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\DIV_dec31_dec_sub9_ldst_len[3:0] 4'0000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\DIV_dec31_dec_sub9_ldst_len[3:0] 4'0000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\DIV_dec31_dec_sub9_ldst_len[3:0] 4'0000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\DIV_dec31_dec_sub9_ldst_len[3:0] 4'0000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\DIV_dec31_dec_sub9_ldst_len[3:0] 4'0000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\DIV_dec31_dec_sub9_ldst_len[3:0] 4'0000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\DIV_dec31_dec_sub9_ldst_len[3:0] 4'0000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\DIV_dec31_dec_sub9_ldst_len[3:0] 4'0000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\DIV_dec31_dec_sub9_ldst_len[3:0] 4'0000 + case + assign $1\DIV_dec31_dec_sub9_ldst_len[3:0] 4'0000 + end + sync always + update \DIV_dec31_dec_sub9_ldst_len $0\DIV_dec31_dec_sub9_ldst_len[3:0] + end + attribute \src "issuer_ls180.v:9242.3-9278.6" + process $proc$issuer_ls180.v:9242$193 + assign { } { } + assign { } { } + assign $0\DIV_dec31_dec_sub9_rc_sel[1:0] $1\DIV_dec31_dec_sub9_rc_sel[1:0] + attribute \src "issuer_ls180.v:9243.5-9243.29" + switch \initial + attribute \src "issuer_ls180.v:9243.9-9243.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\DIV_dec31_dec_sub9_rc_sel[1:0] 2'10 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\DIV_dec31_dec_sub9_rc_sel[1:0] 2'10 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\DIV_dec31_dec_sub9_rc_sel[1:0] 2'10 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\DIV_dec31_dec_sub9_rc_sel[1:0] 2'10 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\DIV_dec31_dec_sub9_rc_sel[1:0] 2'10 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\DIV_dec31_dec_sub9_rc_sel[1:0] 2'10 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\DIV_dec31_dec_sub9_rc_sel[1:0] 2'10 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\DIV_dec31_dec_sub9_rc_sel[1:0] 2'10 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\DIV_dec31_dec_sub9_rc_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\DIV_dec31_dec_sub9_rc_sel[1:0] 2'00 + case + assign $1\DIV_dec31_dec_sub9_rc_sel[1:0] 2'00 + end + sync always + update \DIV_dec31_dec_sub9_rc_sel $0\DIV_dec31_dec_sub9_rc_sel[1:0] + end + attribute \src "issuer_ls180.v:9279.3-9315.6" + process $proc$issuer_ls180.v:9279$194 + assign { } { } + assign { } { } + assign $0\DIV_dec31_dec_sub9_cry_in[1:0] $1\DIV_dec31_dec_sub9_cry_in[1:0] + attribute \src "issuer_ls180.v:9280.5-9280.29" + switch \initial + attribute \src "issuer_ls180.v:9280.9-9280.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\DIV_dec31_dec_sub9_cry_in[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\DIV_dec31_dec_sub9_cry_in[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\DIV_dec31_dec_sub9_cry_in[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\DIV_dec31_dec_sub9_cry_in[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\DIV_dec31_dec_sub9_cry_in[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\DIV_dec31_dec_sub9_cry_in[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\DIV_dec31_dec_sub9_cry_in[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\DIV_dec31_dec_sub9_cry_in[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\DIV_dec31_dec_sub9_cry_in[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\DIV_dec31_dec_sub9_cry_in[1:0] 2'00 + case + assign $1\DIV_dec31_dec_sub9_cry_in[1:0] 2'00 + end + sync always + update \DIV_dec31_dec_sub9_cry_in $0\DIV_dec31_dec_sub9_cry_in[1:0] + end + connect \opcode_switch \opcode_in [10:6] +end +attribute \src "issuer_ls180.v:9321.1-10482.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.dec_LDST.dec.LDST_dec31" +attribute \generator "nMigen" +module \LDST_dec31 + attribute \src "issuer_ls180.v:10324.3-10342.6" + wire $0\LDST_dec31_br[0:0] + attribute \src "issuer_ls180.v:10229.3-10247.6" + wire width 3 $0\LDST_dec31_cr_in[2:0] + attribute \src "issuer_ls180.v:10248.3-10266.6" + wire width 3 $0\LDST_dec31_cr_out[2:0] + attribute \src "issuer_ls180.v:10400.3-10418.6" + wire width 12 $0\LDST_dec31_function_unit[11:0] + attribute \src "issuer_ls180.v:10438.3-10456.6" + wire width 3 $0\LDST_dec31_in1_sel[2:0] + attribute \src "issuer_ls180.v:10457.3-10475.6" + wire width 4 $0\LDST_dec31_in2_sel[3:0] + attribute \src "issuer_ls180.v:10419.3-10437.6" + wire width 7 $0\LDST_dec31_internal_op[6:0] + attribute \src "issuer_ls180.v:10362.3-10380.6" + wire $0\LDST_dec31_is_32b[0:0] + attribute \src "issuer_ls180.v:10267.3-10285.6" + wire width 4 $0\LDST_dec31_ldst_len[3:0] + attribute \src "issuer_ls180.v:10305.3-10323.6" + wire width 2 $0\LDST_dec31_rc_sel[1:0] + attribute \src "issuer_ls180.v:10381.3-10399.6" + wire $0\LDST_dec31_sgn[0:0] + attribute \src "issuer_ls180.v:10343.3-10361.6" + wire $0\LDST_dec31_sgn_ext[0:0] + attribute \src "issuer_ls180.v:10286.3-10304.6" + wire width 2 $0\LDST_dec31_upd[1:0] + attribute \src "issuer_ls180.v:9322.7-9322.20" + wire $0\initial[0:0] + attribute \src "issuer_ls180.v:10324.3-10342.6" + wire $1\LDST_dec31_br[0:0] + attribute \src "issuer_ls180.v:10229.3-10247.6" + wire width 3 $1\LDST_dec31_cr_in[2:0] + attribute \src "issuer_ls180.v:10248.3-10266.6" + wire width 3 $1\LDST_dec31_cr_out[2:0] + attribute \src "issuer_ls180.v:10400.3-10418.6" + wire width 12 $1\LDST_dec31_function_unit[11:0] + attribute \src "issuer_ls180.v:10438.3-10456.6" + wire width 3 $1\LDST_dec31_in1_sel[2:0] + attribute \src "issuer_ls180.v:10457.3-10475.6" + wire width 4 $1\LDST_dec31_in2_sel[3:0] + attribute \src "issuer_ls180.v:10419.3-10437.6" + wire width 7 $1\LDST_dec31_internal_op[6:0] + attribute \src "issuer_ls180.v:10362.3-10380.6" + wire $1\LDST_dec31_is_32b[0:0] + attribute \src "issuer_ls180.v:10267.3-10285.6" + wire width 4 $1\LDST_dec31_ldst_len[3:0] + attribute \src "issuer_ls180.v:10305.3-10323.6" + wire width 2 $1\LDST_dec31_rc_sel[1:0] + attribute \src "issuer_ls180.v:10381.3-10399.6" + wire $1\LDST_dec31_sgn[0:0] + attribute \src "issuer_ls180.v:10343.3-10361.6" + wire $1\LDST_dec31_sgn_ext[0:0] + attribute \src "issuer_ls180.v:10286.3-10304.6" + wire width 2 $1\LDST_dec31_upd[1:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 10 \LDST_dec31_br + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 5 \LDST_dec31_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 6 \LDST_dec31_cr_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_br + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 \LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 \LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_cr_out + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 12 \LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 \LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 \LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_in2_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 7 \LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 \LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_ldst_len + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_sgn_ext + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_upd + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + wire width 32 \LDST_dec31_dec_sub20_opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_br + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 \LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 \LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_cr_out + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 12 \LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 \LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 \LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_in2_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 7 \LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 \LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_ldst_len + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_sgn_ext + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_upd + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + wire width 32 \LDST_dec31_dec_sub21_opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_br + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 \LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 \LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_cr_out + attribute \enum_base_type "Function" + attribute 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\enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 7 output 2 \LDST_dec31_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 12 \LDST_dec31_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 output 7 \LDST_dec31_ldst_len + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 9 \LDST_dec31_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 13 \LDST_dec31_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 11 \LDST_dec31_sgn_ext + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 8 \LDST_dec31_upd + attribute \src "issuer_ls180.v:9322.7-9322.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:326" + wire width 5 \opc_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + wire width 32 input 14 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:320" + wire width 10 \opcode_switch + attribute \module_not_derived 1 + attribute \src "issuer_ls180.v:10165.24-10180.4" + cell \LDST_dec31_dec_sub20 \LDST_dec31_dec_sub20 + connect \LDST_dec31_dec_sub20_br \LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_br + connect \LDST_dec31_dec_sub20_cr_in \LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_cr_in + connect \LDST_dec31_dec_sub20_cr_out \LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_cr_out + connect \LDST_dec31_dec_sub20_function_unit \LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_function_unit + connect \LDST_dec31_dec_sub20_in1_sel \LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_in1_sel + connect \LDST_dec31_dec_sub20_in2_sel \LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_in2_sel + connect \LDST_dec31_dec_sub20_internal_op \LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_internal_op + connect \LDST_dec31_dec_sub20_is_32b \LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_is_32b + connect \LDST_dec31_dec_sub20_ldst_len \LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_ldst_len + connect \LDST_dec31_dec_sub20_rc_sel \LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_rc_sel + connect \LDST_dec31_dec_sub20_sgn \LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_sgn + connect \LDST_dec31_dec_sub20_sgn_ext \LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_sgn_ext + connect \LDST_dec31_dec_sub20_upd \LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_upd + connect \opcode_in \LDST_dec31_dec_sub20_opcode_in + end + attribute \module_not_derived 1 + attribute \src "issuer_ls180.v:10181.24-10196.4" + cell \LDST_dec31_dec_sub21 \LDST_dec31_dec_sub21 + connect \LDST_dec31_dec_sub21_br \LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_br + connect \LDST_dec31_dec_sub21_cr_in \LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_cr_in + connect \LDST_dec31_dec_sub21_cr_out \LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_cr_out + connect \LDST_dec31_dec_sub21_function_unit \LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_function_unit + connect \LDST_dec31_dec_sub21_in1_sel \LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_in1_sel + connect \LDST_dec31_dec_sub21_in2_sel \LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_in2_sel + connect \LDST_dec31_dec_sub21_internal_op \LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_internal_op + connect \LDST_dec31_dec_sub21_is_32b \LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_is_32b + connect \LDST_dec31_dec_sub21_ldst_len \LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_ldst_len + connect \LDST_dec31_dec_sub21_rc_sel \LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_rc_sel + connect \LDST_dec31_dec_sub21_sgn \LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_sgn + connect \LDST_dec31_dec_sub21_sgn_ext \LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_sgn_ext + connect \LDST_dec31_dec_sub21_upd \LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_upd + connect \opcode_in \LDST_dec31_dec_sub21_opcode_in + end + attribute \module_not_derived 1 + attribute \src "issuer_ls180.v:10197.24-10212.4" + cell \LDST_dec31_dec_sub22 \LDST_dec31_dec_sub22 + connect \LDST_dec31_dec_sub22_br \LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_br + connect \LDST_dec31_dec_sub22_cr_in \LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_cr_in + connect \LDST_dec31_dec_sub22_cr_out \LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_cr_out + connect \LDST_dec31_dec_sub22_function_unit \LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_function_unit + connect \LDST_dec31_dec_sub22_in1_sel \LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_in1_sel + connect \LDST_dec31_dec_sub22_in2_sel \LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_in2_sel + connect \LDST_dec31_dec_sub22_internal_op \LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_internal_op + connect \LDST_dec31_dec_sub22_is_32b \LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_is_32b + connect \LDST_dec31_dec_sub22_ldst_len \LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_ldst_len + connect \LDST_dec31_dec_sub22_rc_sel \LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_rc_sel + connect \LDST_dec31_dec_sub22_sgn \LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_sgn + connect \LDST_dec31_dec_sub22_sgn_ext \LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_sgn_ext + connect \LDST_dec31_dec_sub22_upd \LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_upd + connect \opcode_in \LDST_dec31_dec_sub22_opcode_in + end + attribute \module_not_derived 1 + attribute \src "issuer_ls180.v:10213.24-10228.4" + cell \LDST_dec31_dec_sub23 \LDST_dec31_dec_sub23 + connect \LDST_dec31_dec_sub23_br \LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_br + connect \LDST_dec31_dec_sub23_cr_in \LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_cr_in + connect \LDST_dec31_dec_sub23_cr_out \LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_cr_out + connect \LDST_dec31_dec_sub23_function_unit \LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_function_unit + connect \LDST_dec31_dec_sub23_in1_sel \LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_in1_sel + connect \LDST_dec31_dec_sub23_in2_sel \LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_in2_sel + connect \LDST_dec31_dec_sub23_internal_op \LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_internal_op + connect \LDST_dec31_dec_sub23_is_32b \LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_is_32b + connect \LDST_dec31_dec_sub23_ldst_len \LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_ldst_len + connect \LDST_dec31_dec_sub23_rc_sel \LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_rc_sel + connect \LDST_dec31_dec_sub23_sgn \LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_sgn + connect \LDST_dec31_dec_sub23_sgn_ext \LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_sgn_ext + connect \LDST_dec31_dec_sub23_upd \LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_upd + connect \opcode_in \LDST_dec31_dec_sub23_opcode_in + end + attribute \src "issuer_ls180.v:10229.3-10247.6" + process $proc$issuer_ls180.v:10229$196 + assign { } { } + assign { } { } + assign $0\LDST_dec31_cr_in[2:0] $1\LDST_dec31_cr_in[2:0] + attribute \src "issuer_ls180.v:10230.5-10230.29" + switch \initial + attribute \src "issuer_ls180.v:10230.9-10230.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opc_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\LDST_dec31_cr_in[2:0] \LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_cr_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\LDST_dec31_cr_in[2:0] \LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_cr_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\LDST_dec31_cr_in[2:0] \LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_cr_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\LDST_dec31_cr_in[2:0] \LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_cr_in + case + assign $1\LDST_dec31_cr_in[2:0] 3'000 + end + sync always + update \LDST_dec31_cr_in $0\LDST_dec31_cr_in[2:0] + end + attribute \src "issuer_ls180.v:10248.3-10266.6" + process $proc$issuer_ls180.v:10248$197 + assign { } { } + assign { } { } + assign $0\LDST_dec31_cr_out[2:0] $1\LDST_dec31_cr_out[2:0] + attribute \src "issuer_ls180.v:10249.5-10249.29" + switch \initial + attribute \src "issuer_ls180.v:10249.9-10249.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opc_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\LDST_dec31_cr_out[2:0] \LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_cr_out + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\LDST_dec31_cr_out[2:0] \LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_cr_out + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\LDST_dec31_cr_out[2:0] \LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_cr_out + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\LDST_dec31_cr_out[2:0] \LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_cr_out + case + assign $1\LDST_dec31_cr_out[2:0] 3'000 + end + sync always + update \LDST_dec31_cr_out $0\LDST_dec31_cr_out[2:0] + end + attribute \src "issuer_ls180.v:10267.3-10285.6" + process $proc$issuer_ls180.v:10267$198 + assign { } { } + assign { } { } + assign $0\LDST_dec31_ldst_len[3:0] $1\LDST_dec31_ldst_len[3:0] + attribute \src "issuer_ls180.v:10268.5-10268.29" + switch \initial + attribute \src "issuer_ls180.v:10268.9-10268.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opc_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\LDST_dec31_ldst_len[3:0] \LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_ldst_len + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\LDST_dec31_ldst_len[3:0] \LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_ldst_len + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\LDST_dec31_ldst_len[3:0] \LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_ldst_len + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\LDST_dec31_ldst_len[3:0] \LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_ldst_len + case + assign $1\LDST_dec31_ldst_len[3:0] 4'0000 + end + sync always + update \LDST_dec31_ldst_len $0\LDST_dec31_ldst_len[3:0] + end + attribute \src "issuer_ls180.v:10286.3-10304.6" + process $proc$issuer_ls180.v:10286$199 + assign { } { } + assign { } { } + assign $0\LDST_dec31_upd[1:0] $1\LDST_dec31_upd[1:0] + attribute \src "issuer_ls180.v:10287.5-10287.29" + switch \initial + attribute \src "issuer_ls180.v:10287.9-10287.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opc_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\LDST_dec31_upd[1:0] \LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_upd + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\LDST_dec31_upd[1:0] \LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_upd + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\LDST_dec31_upd[1:0] \LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_upd + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\LDST_dec31_upd[1:0] \LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_upd + case + assign $1\LDST_dec31_upd[1:0] 2'00 + end + sync always + update \LDST_dec31_upd $0\LDST_dec31_upd[1:0] + end + attribute \src "issuer_ls180.v:10305.3-10323.6" + process $proc$issuer_ls180.v:10305$200 + assign { } { } + assign { } { } + assign $0\LDST_dec31_rc_sel[1:0] $1\LDST_dec31_rc_sel[1:0] + attribute \src "issuer_ls180.v:10306.5-10306.29" + switch \initial + attribute \src "issuer_ls180.v:10306.9-10306.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opc_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\LDST_dec31_rc_sel[1:0] \LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_rc_sel + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\LDST_dec31_rc_sel[1:0] \LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_rc_sel + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\LDST_dec31_rc_sel[1:0] \LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_rc_sel + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\LDST_dec31_rc_sel[1:0] \LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_rc_sel + case + assign $1\LDST_dec31_rc_sel[1:0] 2'00 + end + sync always + update \LDST_dec31_rc_sel $0\LDST_dec31_rc_sel[1:0] + end + attribute \src "issuer_ls180.v:10324.3-10342.6" + process $proc$issuer_ls180.v:10324$201 + assign { } { } + assign { } { } + assign $0\LDST_dec31_br[0:0] $1\LDST_dec31_br[0:0] + attribute \src "issuer_ls180.v:10325.5-10325.29" + switch \initial + attribute \src "issuer_ls180.v:10325.9-10325.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opc_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\LDST_dec31_br[0:0] \LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_br + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\LDST_dec31_br[0:0] \LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_br + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\LDST_dec31_br[0:0] \LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_br + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\LDST_dec31_br[0:0] \LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_br + case + assign $1\LDST_dec31_br[0:0] 1'0 + end + sync always + update \LDST_dec31_br $0\LDST_dec31_br[0:0] + end + attribute \src "issuer_ls180.v:10343.3-10361.6" + process $proc$issuer_ls180.v:10343$202 + assign { } { } + assign { } { } + assign $0\LDST_dec31_sgn_ext[0:0] $1\LDST_dec31_sgn_ext[0:0] + attribute \src "issuer_ls180.v:10344.5-10344.29" + switch \initial + attribute \src "issuer_ls180.v:10344.9-10344.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opc_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\LDST_dec31_sgn_ext[0:0] \LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_sgn_ext + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\LDST_dec31_sgn_ext[0:0] \LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_sgn_ext + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\LDST_dec31_sgn_ext[0:0] \LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_sgn_ext + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\LDST_dec31_sgn_ext[0:0] \LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_sgn_ext + case + assign $1\LDST_dec31_sgn_ext[0:0] 1'0 + end + sync always + update \LDST_dec31_sgn_ext $0\LDST_dec31_sgn_ext[0:0] + end + attribute \src "issuer_ls180.v:10362.3-10380.6" + process $proc$issuer_ls180.v:10362$203 + assign { } { } + assign { } { } + assign $0\LDST_dec31_is_32b[0:0] $1\LDST_dec31_is_32b[0:0] + attribute \src "issuer_ls180.v:10363.5-10363.29" + switch \initial + attribute \src "issuer_ls180.v:10363.9-10363.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opc_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\LDST_dec31_is_32b[0:0] \LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_is_32b + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\LDST_dec31_is_32b[0:0] \LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_is_32b + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\LDST_dec31_is_32b[0:0] \LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_is_32b + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\LDST_dec31_is_32b[0:0] \LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_is_32b + case + assign $1\LDST_dec31_is_32b[0:0] 1'0 + end + sync always + update \LDST_dec31_is_32b $0\LDST_dec31_is_32b[0:0] + end + attribute \src "issuer_ls180.v:10381.3-10399.6" + process $proc$issuer_ls180.v:10381$204 + assign { } { } + assign { } { } + assign $0\LDST_dec31_sgn[0:0] $1\LDST_dec31_sgn[0:0] + attribute \src "issuer_ls180.v:10382.5-10382.29" + switch \initial + attribute \src "issuer_ls180.v:10382.9-10382.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opc_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\LDST_dec31_sgn[0:0] \LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_sgn + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\LDST_dec31_sgn[0:0] \LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_sgn + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\LDST_dec31_sgn[0:0] \LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_sgn + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\LDST_dec31_sgn[0:0] \LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_sgn + case + assign $1\LDST_dec31_sgn[0:0] 1'0 + end + sync always + update \LDST_dec31_sgn $0\LDST_dec31_sgn[0:0] + end + attribute \src "issuer_ls180.v:10400.3-10418.6" + process $proc$issuer_ls180.v:10400$205 + assign { } { } + assign { } { } + assign $0\LDST_dec31_function_unit[11:0] $1\LDST_dec31_function_unit[11:0] + attribute \src "issuer_ls180.v:10401.5-10401.29" + switch \initial + attribute \src "issuer_ls180.v:10401.9-10401.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opc_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\LDST_dec31_function_unit[11:0] \LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_function_unit + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\LDST_dec31_function_unit[11:0] \LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_function_unit + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\LDST_dec31_function_unit[11:0] \LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_function_unit + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\LDST_dec31_function_unit[11:0] \LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_function_unit + case + assign $1\LDST_dec31_function_unit[11:0] 12'000000000000 + end + sync always + update \LDST_dec31_function_unit $0\LDST_dec31_function_unit[11:0] + end + attribute \src "issuer_ls180.v:10419.3-10437.6" + process $proc$issuer_ls180.v:10419$206 + assign { } { } + assign { } { } + assign $0\LDST_dec31_internal_op[6:0] $1\LDST_dec31_internal_op[6:0] + attribute \src "issuer_ls180.v:10420.5-10420.29" + switch \initial + attribute \src "issuer_ls180.v:10420.9-10420.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opc_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\LDST_dec31_internal_op[6:0] \LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_internal_op + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\LDST_dec31_internal_op[6:0] \LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_internal_op + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\LDST_dec31_internal_op[6:0] \LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_internal_op + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\LDST_dec31_internal_op[6:0] \LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_internal_op + case + assign $1\LDST_dec31_internal_op[6:0] 7'0000000 + end + sync always + update \LDST_dec31_internal_op $0\LDST_dec31_internal_op[6:0] + end + attribute \src "issuer_ls180.v:10438.3-10456.6" + process $proc$issuer_ls180.v:10438$207 + assign { } { } + assign { } { } + assign $0\LDST_dec31_in1_sel[2:0] $1\LDST_dec31_in1_sel[2:0] + attribute \src "issuer_ls180.v:10439.5-10439.29" + switch \initial + attribute \src "issuer_ls180.v:10439.9-10439.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opc_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\LDST_dec31_in1_sel[2:0] \LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_in1_sel + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\LDST_dec31_in1_sel[2:0] \LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_in1_sel + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\LDST_dec31_in1_sel[2:0] \LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_in1_sel + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\LDST_dec31_in1_sel[2:0] \LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_in1_sel + case + assign $1\LDST_dec31_in1_sel[2:0] 3'000 + end + sync always + update \LDST_dec31_in1_sel $0\LDST_dec31_in1_sel[2:0] + end + attribute \src "issuer_ls180.v:10457.3-10475.6" + process $proc$issuer_ls180.v:10457$208 + assign { } { } + assign { } { } + assign $0\LDST_dec31_in2_sel[3:0] $1\LDST_dec31_in2_sel[3:0] + attribute \src "issuer_ls180.v:10458.5-10458.29" + switch \initial + attribute \src "issuer_ls180.v:10458.9-10458.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opc_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\LDST_dec31_in2_sel[3:0] \LDST_dec31_dec_sub22_LDST_dec31_dec_sub22_in2_sel + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\LDST_dec31_in2_sel[3:0] \LDST_dec31_dec_sub20_LDST_dec31_dec_sub20_in2_sel + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\LDST_dec31_in2_sel[3:0] \LDST_dec31_dec_sub21_LDST_dec31_dec_sub21_in2_sel + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\LDST_dec31_in2_sel[3:0] \LDST_dec31_dec_sub23_LDST_dec31_dec_sub23_in2_sel + case + assign $1\LDST_dec31_in2_sel[3:0] 4'0000 + end + sync always + update \LDST_dec31_in2_sel $0\LDST_dec31_in2_sel[3:0] + end + attribute \src "issuer_ls180.v:9322.7-9322.20" + process $proc$issuer_ls180.v:9322$209 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + connect \LDST_dec31_dec_sub23_opcode_in \opcode_in + connect \LDST_dec31_dec_sub21_opcode_in \opcode_in + connect \LDST_dec31_dec_sub20_opcode_in \opcode_in + connect \LDST_dec31_dec_sub22_opcode_in \opcode_in + connect \opc_in \opcode_switch [4:0] + connect \opcode_switch \opcode_in [10:1] +end +attribute \src "issuer_ls180.v:10486.1-10994.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.dec_LDST.dec.LDST_dec31.LDST_dec31_dec_sub20" +attribute \generator "nMigen" +module \LDST_dec31_dec_sub20 + attribute \src "issuer_ls180.v:10693.3-10717.6" + wire $0\LDST_dec31_dec_sub20_br[0:0] + attribute \src "issuer_ls180.v:10868.3-10892.6" + wire width 3 $0\LDST_dec31_dec_sub20_cr_in[2:0] + attribute \src "issuer_ls180.v:10893.3-10917.6" + wire width 3 $0\LDST_dec31_dec_sub20_cr_out[2:0] + attribute \src "issuer_ls180.v:10668.3-10692.6" + wire width 12 $0\LDST_dec31_dec_sub20_function_unit[11:0] + attribute \src "issuer_ls180.v:10818.3-10842.6" + wire width 3 $0\LDST_dec31_dec_sub20_in1_sel[2:0] + attribute \src "issuer_ls180.v:10843.3-10867.6" + wire width 4 $0\LDST_dec31_dec_sub20_in2_sel[3:0] + attribute \src "issuer_ls180.v:10793.3-10817.6" + wire width 7 $0\LDST_dec31_dec_sub20_internal_op[6:0] + attribute \src "issuer_ls180.v:10743.3-10767.6" + wire $0\LDST_dec31_dec_sub20_is_32b[0:0] + attribute \src "issuer_ls180.v:10918.3-10942.6" + wire width 4 $0\LDST_dec31_dec_sub20_ldst_len[3:0] + attribute \src "issuer_ls180.v:10968.3-10992.6" + wire width 2 $0\LDST_dec31_dec_sub20_rc_sel[1:0] + attribute \src "issuer_ls180.v:10768.3-10792.6" + wire $0\LDST_dec31_dec_sub20_sgn[0:0] + attribute \src "issuer_ls180.v:10718.3-10742.6" + wire $0\LDST_dec31_dec_sub20_sgn_ext[0:0] + attribute \src "issuer_ls180.v:10943.3-10967.6" + wire width 2 $0\LDST_dec31_dec_sub20_upd[1:0] + attribute \src "issuer_ls180.v:10487.7-10487.20" + wire $0\initial[0:0] + attribute \src "issuer_ls180.v:10693.3-10717.6" + wire $1\LDST_dec31_dec_sub20_br[0:0] + attribute \src "issuer_ls180.v:10868.3-10892.6" + wire width 3 $1\LDST_dec31_dec_sub20_cr_in[2:0] + attribute \src "issuer_ls180.v:10893.3-10917.6" + wire width 3 $1\LDST_dec31_dec_sub20_cr_out[2:0] + attribute \src "issuer_ls180.v:10668.3-10692.6" + wire width 12 $1\LDST_dec31_dec_sub20_function_unit[11:0] + attribute \src "issuer_ls180.v:10818.3-10842.6" + wire width 3 $1\LDST_dec31_dec_sub20_in1_sel[2:0] + attribute \src "issuer_ls180.v:10843.3-10867.6" + wire width 4 $1\LDST_dec31_dec_sub20_in2_sel[3:0] + attribute \src "issuer_ls180.v:10793.3-10817.6" + wire width 7 $1\LDST_dec31_dec_sub20_internal_op[6:0] + attribute \src "issuer_ls180.v:10743.3-10767.6" + wire $1\LDST_dec31_dec_sub20_is_32b[0:0] + attribute \src "issuer_ls180.v:10918.3-10942.6" + wire width 4 $1\LDST_dec31_dec_sub20_ldst_len[3:0] + attribute \src "issuer_ls180.v:10968.3-10992.6" + wire width 2 $1\LDST_dec31_dec_sub20_rc_sel[1:0] + attribute \src "issuer_ls180.v:10768.3-10792.6" + wire $1\LDST_dec31_dec_sub20_sgn[0:0] + attribute \src "issuer_ls180.v:10718.3-10742.6" + wire $1\LDST_dec31_dec_sub20_sgn_ext[0:0] + attribute \src "issuer_ls180.v:10943.3-10967.6" + wire width 2 $1\LDST_dec31_dec_sub20_upd[1:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 10 \LDST_dec31_dec_sub20_br + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 5 \LDST_dec31_dec_sub20_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 6 \LDST_dec31_dec_sub20_cr_out + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 12 output 1 \LDST_dec31_dec_sub20_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 3 \LDST_dec31_dec_sub20_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 output 4 \LDST_dec31_dec_sub20_in2_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 7 output 2 \LDST_dec31_dec_sub20_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 12 \LDST_dec31_dec_sub20_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 output 7 \LDST_dec31_dec_sub20_ldst_len + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 9 \LDST_dec31_dec_sub20_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 13 \LDST_dec31_dec_sub20_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 11 \LDST_dec31_dec_sub20_sgn_ext + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 8 \LDST_dec31_dec_sub20_upd + attribute \src "issuer_ls180.v:10487.7-10487.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + wire width 32 input 14 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:320" + wire width 5 \opcode_switch + attribute \src "issuer_ls180.v:10487.7-10487.20" + process $proc$issuer_ls180.v:10487$223 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "issuer_ls180.v:10668.3-10692.6" + process $proc$issuer_ls180.v:10668$210 + assign { } { } + assign { } { } + assign $0\LDST_dec31_dec_sub20_function_unit[11:0] $1\LDST_dec31_dec_sub20_function_unit[11:0] + attribute \src "issuer_ls180.v:10669.5-10669.29" + switch \initial + attribute \src "issuer_ls180.v:10669.9-10669.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\LDST_dec31_dec_sub20_function_unit[11:0] 12'000000000100 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\LDST_dec31_dec_sub20_function_unit[11:0] 12'000000000100 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\LDST_dec31_dec_sub20_function_unit[11:0] 12'000000000100 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\LDST_dec31_dec_sub20_function_unit[11:0] 12'000000000100 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\LDST_dec31_dec_sub20_function_unit[11:0] 12'000000000100 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\LDST_dec31_dec_sub20_function_unit[11:0] 12'000000000100 + case + assign $1\LDST_dec31_dec_sub20_function_unit[11:0] 12'000000000000 + end + sync always + update \LDST_dec31_dec_sub20_function_unit $0\LDST_dec31_dec_sub20_function_unit[11:0] + end + attribute \src "issuer_ls180.v:10693.3-10717.6" + process $proc$issuer_ls180.v:10693$211 + assign { } { } + assign { } { } + assign $0\LDST_dec31_dec_sub20_br[0:0] $1\LDST_dec31_dec_sub20_br[0:0] + attribute \src "issuer_ls180.v:10694.5-10694.29" + switch \initial + attribute \src "issuer_ls180.v:10694.9-10694.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\LDST_dec31_dec_sub20_br[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\LDST_dec31_dec_sub20_br[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\LDST_dec31_dec_sub20_br[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\LDST_dec31_dec_sub20_br[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\LDST_dec31_dec_sub20_br[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\LDST_dec31_dec_sub20_br[0:0] 1'1 + case + assign $1\LDST_dec31_dec_sub20_br[0:0] 1'0 + end + sync always + update \LDST_dec31_dec_sub20_br $0\LDST_dec31_dec_sub20_br[0:0] + end + attribute \src "issuer_ls180.v:10718.3-10742.6" + process $proc$issuer_ls180.v:10718$212 + assign { } { } + assign { } { } + assign $0\LDST_dec31_dec_sub20_sgn_ext[0:0] $1\LDST_dec31_dec_sub20_sgn_ext[0:0] + attribute \src "issuer_ls180.v:10719.5-10719.29" + switch \initial + attribute \src "issuer_ls180.v:10719.9-10719.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\LDST_dec31_dec_sub20_sgn_ext[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\LDST_dec31_dec_sub20_sgn_ext[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\LDST_dec31_dec_sub20_sgn_ext[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\LDST_dec31_dec_sub20_sgn_ext[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\LDST_dec31_dec_sub20_sgn_ext[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\LDST_dec31_dec_sub20_sgn_ext[0:0] 1'0 + case + assign $1\LDST_dec31_dec_sub20_sgn_ext[0:0] 1'0 + end + sync always + update \LDST_dec31_dec_sub20_sgn_ext $0\LDST_dec31_dec_sub20_sgn_ext[0:0] + end + attribute \src "issuer_ls180.v:10743.3-10767.6" + process $proc$issuer_ls180.v:10743$213 + assign { } { } + assign { } { } + assign $0\LDST_dec31_dec_sub20_is_32b[0:0] $1\LDST_dec31_dec_sub20_is_32b[0:0] + attribute \src "issuer_ls180.v:10744.5-10744.29" + switch \initial + attribute \src "issuer_ls180.v:10744.9-10744.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\LDST_dec31_dec_sub20_is_32b[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\LDST_dec31_dec_sub20_is_32b[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\LDST_dec31_dec_sub20_is_32b[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\LDST_dec31_dec_sub20_is_32b[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\LDST_dec31_dec_sub20_is_32b[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\LDST_dec31_dec_sub20_is_32b[0:0] 1'0 + case + assign $1\LDST_dec31_dec_sub20_is_32b[0:0] 1'0 + end + sync always + update \LDST_dec31_dec_sub20_is_32b $0\LDST_dec31_dec_sub20_is_32b[0:0] + end + attribute \src "issuer_ls180.v:10768.3-10792.6" + process $proc$issuer_ls180.v:10768$214 + assign { } { } + assign { } { } + assign $0\LDST_dec31_dec_sub20_sgn[0:0] $1\LDST_dec31_dec_sub20_sgn[0:0] + attribute \src "issuer_ls180.v:10769.5-10769.29" + switch \initial + attribute \src "issuer_ls180.v:10769.9-10769.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\LDST_dec31_dec_sub20_sgn[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\LDST_dec31_dec_sub20_sgn[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\LDST_dec31_dec_sub20_sgn[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\LDST_dec31_dec_sub20_sgn[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\LDST_dec31_dec_sub20_sgn[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\LDST_dec31_dec_sub20_sgn[0:0] 1'0 + case + assign $1\LDST_dec31_dec_sub20_sgn[0:0] 1'0 + end + sync always + update \LDST_dec31_dec_sub20_sgn $0\LDST_dec31_dec_sub20_sgn[0:0] + end + attribute \src "issuer_ls180.v:10793.3-10817.6" + process $proc$issuer_ls180.v:10793$215 + assign { } { } + assign { } { } + assign $0\LDST_dec31_dec_sub20_internal_op[6:0] $1\LDST_dec31_dec_sub20_internal_op[6:0] + attribute \src "issuer_ls180.v:10794.5-10794.29" + switch \initial + attribute \src "issuer_ls180.v:10794.9-10794.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\LDST_dec31_dec_sub20_internal_op[6:0] 7'0100101 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\LDST_dec31_dec_sub20_internal_op[6:0] 7'0100101 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\LDST_dec31_dec_sub20_internal_op[6:0] 7'0100101 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\LDST_dec31_dec_sub20_internal_op[6:0] 7'0100101 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\LDST_dec31_dec_sub20_internal_op[6:0] 7'0100101 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\LDST_dec31_dec_sub20_internal_op[6:0] 7'0100110 + case + assign $1\LDST_dec31_dec_sub20_internal_op[6:0] 7'0000000 + end + sync always + update \LDST_dec31_dec_sub20_internal_op $0\LDST_dec31_dec_sub20_internal_op[6:0] + end + attribute \src "issuer_ls180.v:10818.3-10842.6" + process $proc$issuer_ls180.v:10818$216 + assign { } { } + assign { } { } + assign $0\LDST_dec31_dec_sub20_in1_sel[2:0] $1\LDST_dec31_dec_sub20_in1_sel[2:0] + attribute \src "issuer_ls180.v:10819.5-10819.29" + switch \initial + attribute \src "issuer_ls180.v:10819.9-10819.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\LDST_dec31_dec_sub20_in1_sel[2:0] 3'010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\LDST_dec31_dec_sub20_in1_sel[2:0] 3'010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\LDST_dec31_dec_sub20_in1_sel[2:0] 3'010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\LDST_dec31_dec_sub20_in1_sel[2:0] 3'010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\LDST_dec31_dec_sub20_in1_sel[2:0] 3'010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\LDST_dec31_dec_sub20_in1_sel[2:0] 3'010 + case + assign $1\LDST_dec31_dec_sub20_in1_sel[2:0] 3'000 + end + sync always + update \LDST_dec31_dec_sub20_in1_sel $0\LDST_dec31_dec_sub20_in1_sel[2:0] + end + attribute \src "issuer_ls180.v:10843.3-10867.6" + process $proc$issuer_ls180.v:10843$217 + assign { } { } + assign { } { } + assign $0\LDST_dec31_dec_sub20_in2_sel[3:0] $1\LDST_dec31_dec_sub20_in2_sel[3:0] + attribute \src "issuer_ls180.v:10844.5-10844.29" + switch \initial + attribute \src "issuer_ls180.v:10844.9-10844.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\LDST_dec31_dec_sub20_in2_sel[3:0] 4'0001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\LDST_dec31_dec_sub20_in2_sel[3:0] 4'0001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\LDST_dec31_dec_sub20_in2_sel[3:0] 4'0001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\LDST_dec31_dec_sub20_in2_sel[3:0] 4'0001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\LDST_dec31_dec_sub20_in2_sel[3:0] 4'0001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\LDST_dec31_dec_sub20_in2_sel[3:0] 4'0001 + case + assign $1\LDST_dec31_dec_sub20_in2_sel[3:0] 4'0000 + end + sync always + update \LDST_dec31_dec_sub20_in2_sel $0\LDST_dec31_dec_sub20_in2_sel[3:0] + end + attribute \src "issuer_ls180.v:10868.3-10892.6" + process $proc$issuer_ls180.v:10868$218 + assign { } { } + assign { } { } + assign $0\LDST_dec31_dec_sub20_cr_in[2:0] $1\LDST_dec31_dec_sub20_cr_in[2:0] + attribute \src "issuer_ls180.v:10869.5-10869.29" + switch \initial + attribute \src "issuer_ls180.v:10869.9-10869.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\LDST_dec31_dec_sub20_cr_in[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\LDST_dec31_dec_sub20_cr_in[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\LDST_dec31_dec_sub20_cr_in[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\LDST_dec31_dec_sub20_cr_in[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\LDST_dec31_dec_sub20_cr_in[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\LDST_dec31_dec_sub20_cr_in[2:0] 3'000 + case + assign $1\LDST_dec31_dec_sub20_cr_in[2:0] 3'000 + end + sync always + update \LDST_dec31_dec_sub20_cr_in $0\LDST_dec31_dec_sub20_cr_in[2:0] + end + attribute \src "issuer_ls180.v:10893.3-10917.6" + process $proc$issuer_ls180.v:10893$219 + assign { } { } + assign { } { } + assign $0\LDST_dec31_dec_sub20_cr_out[2:0] $1\LDST_dec31_dec_sub20_cr_out[2:0] + attribute \src "issuer_ls180.v:10894.5-10894.29" + switch \initial + attribute \src "issuer_ls180.v:10894.9-10894.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\LDST_dec31_dec_sub20_cr_out[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\LDST_dec31_dec_sub20_cr_out[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\LDST_dec31_dec_sub20_cr_out[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\LDST_dec31_dec_sub20_cr_out[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\LDST_dec31_dec_sub20_cr_out[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\LDST_dec31_dec_sub20_cr_out[2:0] 3'000 + case + assign $1\LDST_dec31_dec_sub20_cr_out[2:0] 3'000 + end + sync always + update \LDST_dec31_dec_sub20_cr_out $0\LDST_dec31_dec_sub20_cr_out[2:0] + end + attribute \src "issuer_ls180.v:10918.3-10942.6" + process $proc$issuer_ls180.v:10918$220 + assign { } { } + assign { } { } + assign $0\LDST_dec31_dec_sub20_ldst_len[3:0] $1\LDST_dec31_dec_sub20_ldst_len[3:0] + attribute \src "issuer_ls180.v:10919.5-10919.29" + switch \initial + attribute \src "issuer_ls180.v:10919.9-10919.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\LDST_dec31_dec_sub20_ldst_len[3:0] 4'0001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\LDST_dec31_dec_sub20_ldst_len[3:0] 4'1000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\LDST_dec31_dec_sub20_ldst_len[3:0] 4'1000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\LDST_dec31_dec_sub20_ldst_len[3:0] 4'0010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\LDST_dec31_dec_sub20_ldst_len[3:0] 4'0100 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\LDST_dec31_dec_sub20_ldst_len[3:0] 4'1000 + case + assign $1\LDST_dec31_dec_sub20_ldst_len[3:0] 4'0000 + end + sync always + update \LDST_dec31_dec_sub20_ldst_len $0\LDST_dec31_dec_sub20_ldst_len[3:0] + end + attribute \src "issuer_ls180.v:10943.3-10967.6" + process $proc$issuer_ls180.v:10943$221 + assign { } { } + assign { } { } + assign $0\LDST_dec31_dec_sub20_upd[1:0] $1\LDST_dec31_dec_sub20_upd[1:0] + attribute \src "issuer_ls180.v:10944.5-10944.29" + switch \initial + attribute \src "issuer_ls180.v:10944.9-10944.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\LDST_dec31_dec_sub20_upd[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\LDST_dec31_dec_sub20_upd[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\LDST_dec31_dec_sub20_upd[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\LDST_dec31_dec_sub20_upd[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\LDST_dec31_dec_sub20_upd[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\LDST_dec31_dec_sub20_upd[1:0] 2'00 + case + assign $1\LDST_dec31_dec_sub20_upd[1:0] 2'00 + end + sync always + update \LDST_dec31_dec_sub20_upd $0\LDST_dec31_dec_sub20_upd[1:0] + end + attribute \src "issuer_ls180.v:10968.3-10992.6" + process $proc$issuer_ls180.v:10968$222 + assign { } { } + assign { } { } + assign $0\LDST_dec31_dec_sub20_rc_sel[1:0] $1\LDST_dec31_dec_sub20_rc_sel[1:0] + attribute \src "issuer_ls180.v:10969.5-10969.29" + switch \initial + attribute \src "issuer_ls180.v:10969.9-10969.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\LDST_dec31_dec_sub20_rc_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\LDST_dec31_dec_sub20_rc_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\LDST_dec31_dec_sub20_rc_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\LDST_dec31_dec_sub20_rc_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\LDST_dec31_dec_sub20_rc_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\LDST_dec31_dec_sub20_rc_sel[1:0] 2'00 + case + assign $1\LDST_dec31_dec_sub20_rc_sel[1:0] 2'00 + end + sync always + update \LDST_dec31_dec_sub20_rc_sel $0\LDST_dec31_dec_sub20_rc_sel[1:0] + end + connect \opcode_switch \opcode_in [10:6] +end +attribute \src "issuer_ls180.v:10998.1-11818.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.dec_LDST.dec.LDST_dec31.LDST_dec31_dec_sub21" +attribute \generator "nMigen" +module \LDST_dec31_dec_sub21 + attribute \src "issuer_ls180.v:11229.3-11277.6" + wire $0\LDST_dec31_dec_sub21_br[0:0] + attribute \src "issuer_ls180.v:11572.3-11620.6" + wire width 3 $0\LDST_dec31_dec_sub21_cr_in[2:0] + attribute \src "issuer_ls180.v:11621.3-11669.6" + wire width 3 $0\LDST_dec31_dec_sub21_cr_out[2:0] + attribute \src "issuer_ls180.v:11180.3-11228.6" + wire width 12 $0\LDST_dec31_dec_sub21_function_unit[11:0] + attribute \src "issuer_ls180.v:11474.3-11522.6" + wire width 3 $0\LDST_dec31_dec_sub21_in1_sel[2:0] + attribute \src "issuer_ls180.v:11523.3-11571.6" + wire width 4 $0\LDST_dec31_dec_sub21_in2_sel[3:0] + attribute \src "issuer_ls180.v:11425.3-11473.6" + wire width 7 $0\LDST_dec31_dec_sub21_internal_op[6:0] + attribute \src "issuer_ls180.v:11327.3-11375.6" + wire $0\LDST_dec31_dec_sub21_is_32b[0:0] + attribute \src "issuer_ls180.v:11670.3-11718.6" + wire width 4 $0\LDST_dec31_dec_sub21_ldst_len[3:0] + attribute \src "issuer_ls180.v:11768.3-11816.6" + wire width 2 $0\LDST_dec31_dec_sub21_rc_sel[1:0] + attribute \src "issuer_ls180.v:11376.3-11424.6" + wire $0\LDST_dec31_dec_sub21_sgn[0:0] + attribute \src "issuer_ls180.v:11278.3-11326.6" + wire $0\LDST_dec31_dec_sub21_sgn_ext[0:0] + attribute \src "issuer_ls180.v:11719.3-11767.6" + wire width 2 $0\LDST_dec31_dec_sub21_upd[1:0] + attribute \src "issuer_ls180.v:10999.7-10999.20" + wire $0\initial[0:0] + attribute \src "issuer_ls180.v:11229.3-11277.6" + wire $1\LDST_dec31_dec_sub21_br[0:0] + attribute \src "issuer_ls180.v:11572.3-11620.6" + wire width 3 $1\LDST_dec31_dec_sub21_cr_in[2:0] + attribute \src "issuer_ls180.v:11621.3-11669.6" + wire width 3 $1\LDST_dec31_dec_sub21_cr_out[2:0] + attribute \src "issuer_ls180.v:11180.3-11228.6" + wire width 12 $1\LDST_dec31_dec_sub21_function_unit[11:0] + attribute \src "issuer_ls180.v:11474.3-11522.6" + wire width 3 $1\LDST_dec31_dec_sub21_in1_sel[2:0] + attribute \src "issuer_ls180.v:11523.3-11571.6" + wire width 4 $1\LDST_dec31_dec_sub21_in2_sel[3:0] + attribute \src "issuer_ls180.v:11425.3-11473.6" + wire width 7 $1\LDST_dec31_dec_sub21_internal_op[6:0] + attribute \src "issuer_ls180.v:11327.3-11375.6" + wire $1\LDST_dec31_dec_sub21_is_32b[0:0] + attribute \src "issuer_ls180.v:11670.3-11718.6" + wire width 4 $1\LDST_dec31_dec_sub21_ldst_len[3:0] + attribute \src "issuer_ls180.v:11768.3-11816.6" + wire width 2 $1\LDST_dec31_dec_sub21_rc_sel[1:0] + attribute \src "issuer_ls180.v:11376.3-11424.6" + wire $1\LDST_dec31_dec_sub21_sgn[0:0] + attribute \src "issuer_ls180.v:11278.3-11326.6" + wire $1\LDST_dec31_dec_sub21_sgn_ext[0:0] + attribute \src "issuer_ls180.v:11719.3-11767.6" + wire width 2 $1\LDST_dec31_dec_sub21_upd[1:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 10 \LDST_dec31_dec_sub21_br + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 5 \LDST_dec31_dec_sub21_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 6 \LDST_dec31_dec_sub21_cr_out + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 12 output 1 \LDST_dec31_dec_sub21_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 3 \LDST_dec31_dec_sub21_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 output 4 \LDST_dec31_dec_sub21_in2_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 7 output 2 \LDST_dec31_dec_sub21_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 12 \LDST_dec31_dec_sub21_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 output 7 \LDST_dec31_dec_sub21_ldst_len + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 9 \LDST_dec31_dec_sub21_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 13 \LDST_dec31_dec_sub21_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 11 \LDST_dec31_dec_sub21_sgn_ext + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 8 \LDST_dec31_dec_sub21_upd + attribute \src "issuer_ls180.v:10999.7-10999.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + wire width 32 input 14 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:320" + wire width 5 \opcode_switch + attribute \src "issuer_ls180.v:10999.7-10999.20" + process $proc$issuer_ls180.v:10999$237 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "issuer_ls180.v:11180.3-11228.6" + process $proc$issuer_ls180.v:11180$224 + assign { } { } + assign { } { } + assign $0\LDST_dec31_dec_sub21_function_unit[11:0] $1\LDST_dec31_dec_sub21_function_unit[11:0] + attribute \src "issuer_ls180.v:11181.5-11181.29" + switch \initial + attribute \src "issuer_ls180.v:11181.9-11181.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\LDST_dec31_dec_sub21_function_unit[11:0] 12'000000000100 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\LDST_dec31_dec_sub21_function_unit[11:0] 12'000000000100 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\LDST_dec31_dec_sub21_function_unit[11:0] 12'000000000100 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\LDST_dec31_dec_sub21_function_unit[11:0] 12'000000000100 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\LDST_dec31_dec_sub21_function_unit[11:0] 12'000000000100 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\LDST_dec31_dec_sub21_function_unit[11:0] 12'000000000100 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\LDST_dec31_dec_sub21_function_unit[11:0] 12'000000000100 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\LDST_dec31_dec_sub21_function_unit[11:0] 12'000000000100 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\LDST_dec31_dec_sub21_function_unit[11:0] 12'000000000100 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\LDST_dec31_dec_sub21_function_unit[11:0] 12'000000000100 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\LDST_dec31_dec_sub21_function_unit[11:0] 12'000000000100 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\LDST_dec31_dec_sub21_function_unit[11:0] 12'000000000100 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\LDST_dec31_dec_sub21_function_unit[11:0] 12'000000000100 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\LDST_dec31_dec_sub21_function_unit[11:0] 12'000000000100 + case + assign $1\LDST_dec31_dec_sub21_function_unit[11:0] 12'000000000000 + end + sync always + update \LDST_dec31_dec_sub21_function_unit $0\LDST_dec31_dec_sub21_function_unit[11:0] + end + attribute \src "issuer_ls180.v:11229.3-11277.6" + process $proc$issuer_ls180.v:11229$225 + assign { } { } + assign { } { } + assign $0\LDST_dec31_dec_sub21_br[0:0] $1\LDST_dec31_dec_sub21_br[0:0] + attribute \src "issuer_ls180.v:11230.5-11230.29" + switch \initial + attribute \src "issuer_ls180.v:11230.9-11230.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\LDST_dec31_dec_sub21_br[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\LDST_dec31_dec_sub21_br[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\LDST_dec31_dec_sub21_br[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\LDST_dec31_dec_sub21_br[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\LDST_dec31_dec_sub21_br[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\LDST_dec31_dec_sub21_br[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\LDST_dec31_dec_sub21_br[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\LDST_dec31_dec_sub21_br[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\LDST_dec31_dec_sub21_br[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\LDST_dec31_dec_sub21_br[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\LDST_dec31_dec_sub21_br[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\LDST_dec31_dec_sub21_br[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\LDST_dec31_dec_sub21_br[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\LDST_dec31_dec_sub21_br[0:0] 1'0 + case + assign $1\LDST_dec31_dec_sub21_br[0:0] 1'0 + end + sync always + update \LDST_dec31_dec_sub21_br $0\LDST_dec31_dec_sub21_br[0:0] + end + attribute \src "issuer_ls180.v:11278.3-11326.6" + process $proc$issuer_ls180.v:11278$226 + assign { } { } + assign { } { } + assign $0\LDST_dec31_dec_sub21_sgn_ext[0:0] $1\LDST_dec31_dec_sub21_sgn_ext[0:0] + attribute \src "issuer_ls180.v:11279.5-11279.29" + switch \initial + attribute \src "issuer_ls180.v:11279.9-11279.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\LDST_dec31_dec_sub21_sgn_ext[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\LDST_dec31_dec_sub21_sgn_ext[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\LDST_dec31_dec_sub21_sgn_ext[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\LDST_dec31_dec_sub21_sgn_ext[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\LDST_dec31_dec_sub21_sgn_ext[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\LDST_dec31_dec_sub21_sgn_ext[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\LDST_dec31_dec_sub21_sgn_ext[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\LDST_dec31_dec_sub21_sgn_ext[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\LDST_dec31_dec_sub21_sgn_ext[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\LDST_dec31_dec_sub21_sgn_ext[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\LDST_dec31_dec_sub21_sgn_ext[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\LDST_dec31_dec_sub21_sgn_ext[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\LDST_dec31_dec_sub21_sgn_ext[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\LDST_dec31_dec_sub21_sgn_ext[0:0] 1'0 + case + assign $1\LDST_dec31_dec_sub21_sgn_ext[0:0] 1'0 + end + sync always + update \LDST_dec31_dec_sub21_sgn_ext $0\LDST_dec31_dec_sub21_sgn_ext[0:0] + end + attribute \src "issuer_ls180.v:11327.3-11375.6" + process $proc$issuer_ls180.v:11327$227 + assign { } { } + assign { } { } + assign $0\LDST_dec31_dec_sub21_is_32b[0:0] $1\LDST_dec31_dec_sub21_is_32b[0:0] + attribute \src "issuer_ls180.v:11328.5-11328.29" + switch \initial + attribute \src "issuer_ls180.v:11328.9-11328.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\LDST_dec31_dec_sub21_is_32b[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\LDST_dec31_dec_sub21_is_32b[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\LDST_dec31_dec_sub21_is_32b[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\LDST_dec31_dec_sub21_is_32b[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\LDST_dec31_dec_sub21_is_32b[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\LDST_dec31_dec_sub21_is_32b[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\LDST_dec31_dec_sub21_is_32b[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\LDST_dec31_dec_sub21_is_32b[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\LDST_dec31_dec_sub21_is_32b[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\LDST_dec31_dec_sub21_is_32b[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\LDST_dec31_dec_sub21_is_32b[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\LDST_dec31_dec_sub21_is_32b[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\LDST_dec31_dec_sub21_is_32b[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\LDST_dec31_dec_sub21_is_32b[0:0] 1'0 + case + assign $1\LDST_dec31_dec_sub21_is_32b[0:0] 1'0 + end + sync always + update \LDST_dec31_dec_sub21_is_32b $0\LDST_dec31_dec_sub21_is_32b[0:0] + end + attribute \src "issuer_ls180.v:11376.3-11424.6" + process $proc$issuer_ls180.v:11376$228 + assign { } { } + assign { } { } + assign $0\LDST_dec31_dec_sub21_sgn[0:0] $1\LDST_dec31_dec_sub21_sgn[0:0] + attribute \src "issuer_ls180.v:11377.5-11377.29" + switch \initial + attribute \src "issuer_ls180.v:11377.9-11377.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\LDST_dec31_dec_sub21_sgn[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\LDST_dec31_dec_sub21_sgn[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\LDST_dec31_dec_sub21_sgn[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\LDST_dec31_dec_sub21_sgn[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\LDST_dec31_dec_sub21_sgn[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\LDST_dec31_dec_sub21_sgn[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\LDST_dec31_dec_sub21_sgn[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\LDST_dec31_dec_sub21_sgn[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\LDST_dec31_dec_sub21_sgn[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\LDST_dec31_dec_sub21_sgn[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\LDST_dec31_dec_sub21_sgn[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\LDST_dec31_dec_sub21_sgn[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\LDST_dec31_dec_sub21_sgn[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\LDST_dec31_dec_sub21_sgn[0:0] 1'0 + case + assign $1\LDST_dec31_dec_sub21_sgn[0:0] 1'0 + end + sync always + update \LDST_dec31_dec_sub21_sgn $0\LDST_dec31_dec_sub21_sgn[0:0] + end + attribute \src "issuer_ls180.v:11425.3-11473.6" + process $proc$issuer_ls180.v:11425$229 + assign { } { } + assign { } { } + assign $0\LDST_dec31_dec_sub21_internal_op[6:0] $1\LDST_dec31_dec_sub21_internal_op[6:0] + attribute \src "issuer_ls180.v:11426.5-11426.29" + switch \initial + attribute \src "issuer_ls180.v:11426.9-11426.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\LDST_dec31_dec_sub21_internal_op[6:0] 7'0100101 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\LDST_dec31_dec_sub21_internal_op[6:0] 7'0100101 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\LDST_dec31_dec_sub21_internal_op[6:0] 7'0100101 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\LDST_dec31_dec_sub21_internal_op[6:0] 7'0100101 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\LDST_dec31_dec_sub21_internal_op[6:0] 7'0100101 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\LDST_dec31_dec_sub21_internal_op[6:0] 7'0100101 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\LDST_dec31_dec_sub21_internal_op[6:0] 7'0100101 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\LDST_dec31_dec_sub21_internal_op[6:0] 7'0100101 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\LDST_dec31_dec_sub21_internal_op[6:0] 7'0100110 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\LDST_dec31_dec_sub21_internal_op[6:0] 7'0100110 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\LDST_dec31_dec_sub21_internal_op[6:0] 7'0100110 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\LDST_dec31_dec_sub21_internal_op[6:0] 7'0100110 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\LDST_dec31_dec_sub21_internal_op[6:0] 7'0100110 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\LDST_dec31_dec_sub21_internal_op[6:0] 7'0100110 + case + assign $1\LDST_dec31_dec_sub21_internal_op[6:0] 7'0000000 + end + sync always + update \LDST_dec31_dec_sub21_internal_op $0\LDST_dec31_dec_sub21_internal_op[6:0] + end + attribute \src "issuer_ls180.v:11474.3-11522.6" + process $proc$issuer_ls180.v:11474$230 + assign { } { } + assign { } { } + assign $0\LDST_dec31_dec_sub21_in1_sel[2:0] $1\LDST_dec31_dec_sub21_in1_sel[2:0] + attribute \src "issuer_ls180.v:11475.5-11475.29" + switch \initial + attribute \src "issuer_ls180.v:11475.9-11475.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\LDST_dec31_dec_sub21_in1_sel[2:0] 3'010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\LDST_dec31_dec_sub21_in1_sel[2:0] 3'010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\LDST_dec31_dec_sub21_in1_sel[2:0] 3'010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\LDST_dec31_dec_sub21_in1_sel[2:0] 3'010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\LDST_dec31_dec_sub21_in1_sel[2:0] 3'010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\LDST_dec31_dec_sub21_in1_sel[2:0] 3'010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\LDST_dec31_dec_sub21_in1_sel[2:0] 3'010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\LDST_dec31_dec_sub21_in1_sel[2:0] 3'010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\LDST_dec31_dec_sub21_in1_sel[2:0] 3'010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\LDST_dec31_dec_sub21_in1_sel[2:0] 3'010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\LDST_dec31_dec_sub21_in1_sel[2:0] 3'010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\LDST_dec31_dec_sub21_in1_sel[2:0] 3'010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\LDST_dec31_dec_sub21_in1_sel[2:0] 3'010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\LDST_dec31_dec_sub21_in1_sel[2:0] 3'010 + case + assign $1\LDST_dec31_dec_sub21_in1_sel[2:0] 3'000 + end + sync always + update \LDST_dec31_dec_sub21_in1_sel $0\LDST_dec31_dec_sub21_in1_sel[2:0] + end + attribute \src "issuer_ls180.v:11523.3-11571.6" + process $proc$issuer_ls180.v:11523$231 + assign { } { } + assign { } { } + assign $0\LDST_dec31_dec_sub21_in2_sel[3:0] $1\LDST_dec31_dec_sub21_in2_sel[3:0] + attribute \src "issuer_ls180.v:11524.5-11524.29" + switch \initial + attribute \src "issuer_ls180.v:11524.9-11524.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\LDST_dec31_dec_sub21_in2_sel[3:0] 4'0001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\LDST_dec31_dec_sub21_in2_sel[3:0] 4'0001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\LDST_dec31_dec_sub21_in2_sel[3:0] 4'0001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\LDST_dec31_dec_sub21_in2_sel[3:0] 4'0001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\LDST_dec31_dec_sub21_in2_sel[3:0] 4'0001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\LDST_dec31_dec_sub21_in2_sel[3:0] 4'0001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\LDST_dec31_dec_sub21_in2_sel[3:0] 4'0001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\LDST_dec31_dec_sub21_in2_sel[3:0] 4'0001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\LDST_dec31_dec_sub21_in2_sel[3:0] 4'0001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\LDST_dec31_dec_sub21_in2_sel[3:0] 4'0001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\LDST_dec31_dec_sub21_in2_sel[3:0] 4'0001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\LDST_dec31_dec_sub21_in2_sel[3:0] 4'0001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\LDST_dec31_dec_sub21_in2_sel[3:0] 4'0001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\LDST_dec31_dec_sub21_in2_sel[3:0] 4'0001 + case + assign $1\LDST_dec31_dec_sub21_in2_sel[3:0] 4'0000 + end + sync always + update \LDST_dec31_dec_sub21_in2_sel $0\LDST_dec31_dec_sub21_in2_sel[3:0] + end + attribute \src "issuer_ls180.v:11572.3-11620.6" + process $proc$issuer_ls180.v:11572$232 + assign { } { } + assign { } { } + assign $0\LDST_dec31_dec_sub21_cr_in[2:0] $1\LDST_dec31_dec_sub21_cr_in[2:0] + attribute \src "issuer_ls180.v:11573.5-11573.29" + switch \initial + attribute \src "issuer_ls180.v:11573.9-11573.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\LDST_dec31_dec_sub21_cr_in[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\LDST_dec31_dec_sub21_cr_in[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\LDST_dec31_dec_sub21_cr_in[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\LDST_dec31_dec_sub21_cr_in[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\LDST_dec31_dec_sub21_cr_in[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\LDST_dec31_dec_sub21_cr_in[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\LDST_dec31_dec_sub21_cr_in[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\LDST_dec31_dec_sub21_cr_in[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\LDST_dec31_dec_sub21_cr_in[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\LDST_dec31_dec_sub21_cr_in[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\LDST_dec31_dec_sub21_cr_in[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\LDST_dec31_dec_sub21_cr_in[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\LDST_dec31_dec_sub21_cr_in[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\LDST_dec31_dec_sub21_cr_in[2:0] 3'000 + case + assign $1\LDST_dec31_dec_sub21_cr_in[2:0] 3'000 + end + sync always + update \LDST_dec31_dec_sub21_cr_in $0\LDST_dec31_dec_sub21_cr_in[2:0] + end + attribute \src "issuer_ls180.v:11621.3-11669.6" + process $proc$issuer_ls180.v:11621$233 + assign { } { } + assign { } { } + assign $0\LDST_dec31_dec_sub21_cr_out[2:0] $1\LDST_dec31_dec_sub21_cr_out[2:0] + attribute \src "issuer_ls180.v:11622.5-11622.29" + switch \initial + attribute \src "issuer_ls180.v:11622.9-11622.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\LDST_dec31_dec_sub21_cr_out[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\LDST_dec31_dec_sub21_cr_out[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\LDST_dec31_dec_sub21_cr_out[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\LDST_dec31_dec_sub21_cr_out[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\LDST_dec31_dec_sub21_cr_out[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\LDST_dec31_dec_sub21_cr_out[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\LDST_dec31_dec_sub21_cr_out[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\LDST_dec31_dec_sub21_cr_out[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\LDST_dec31_dec_sub21_cr_out[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\LDST_dec31_dec_sub21_cr_out[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\LDST_dec31_dec_sub21_cr_out[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\LDST_dec31_dec_sub21_cr_out[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\LDST_dec31_dec_sub21_cr_out[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\LDST_dec31_dec_sub21_cr_out[2:0] 3'000 + case + assign $1\LDST_dec31_dec_sub21_cr_out[2:0] 3'000 + end + sync always + update \LDST_dec31_dec_sub21_cr_out $0\LDST_dec31_dec_sub21_cr_out[2:0] + end + attribute \src "issuer_ls180.v:11670.3-11718.6" + process $proc$issuer_ls180.v:11670$234 + assign { } { } + assign { } { } + assign $0\LDST_dec31_dec_sub21_ldst_len[3:0] $1\LDST_dec31_dec_sub21_ldst_len[3:0] + attribute \src "issuer_ls180.v:11671.5-11671.29" + switch \initial + attribute \src "issuer_ls180.v:11671.9-11671.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\LDST_dec31_dec_sub21_ldst_len[3:0] 4'0001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\LDST_dec31_dec_sub21_ldst_len[3:0] 4'1000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\LDST_dec31_dec_sub21_ldst_len[3:0] 4'1000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\LDST_dec31_dec_sub21_ldst_len[3:0] 4'1000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\LDST_dec31_dec_sub21_ldst_len[3:0] 4'0010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\LDST_dec31_dec_sub21_ldst_len[3:0] 4'0100 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\LDST_dec31_dec_sub21_ldst_len[3:0] 4'0100 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\LDST_dec31_dec_sub21_ldst_len[3:0] 4'0100 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\LDST_dec31_dec_sub21_ldst_len[3:0] 4'0001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\LDST_dec31_dec_sub21_ldst_len[3:0] 4'1000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\LDST_dec31_dec_sub21_ldst_len[3:0] 4'1000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\LDST_dec31_dec_sub21_ldst_len[3:0] 4'1000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\LDST_dec31_dec_sub21_ldst_len[3:0] 4'0010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\LDST_dec31_dec_sub21_ldst_len[3:0] 4'0100 + case + assign $1\LDST_dec31_dec_sub21_ldst_len[3:0] 4'0000 + end + sync always + update \LDST_dec31_dec_sub21_ldst_len $0\LDST_dec31_dec_sub21_ldst_len[3:0] + end + attribute \src "issuer_ls180.v:11719.3-11767.6" + process $proc$issuer_ls180.v:11719$235 + assign { } { } + assign { } { } + assign $0\LDST_dec31_dec_sub21_upd[1:0] $1\LDST_dec31_dec_sub21_upd[1:0] + attribute \src "issuer_ls180.v:11720.5-11720.29" + switch \initial + attribute \src "issuer_ls180.v:11720.9-11720.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\LDST_dec31_dec_sub21_upd[1:0] 2'10 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\LDST_dec31_dec_sub21_upd[1:0] 2'10 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\LDST_dec31_dec_sub21_upd[1:0] 2'01 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\LDST_dec31_dec_sub21_upd[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\LDST_dec31_dec_sub21_upd[1:0] 2'10 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\LDST_dec31_dec_sub21_upd[1:0] 2'01 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\LDST_dec31_dec_sub21_upd[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\LDST_dec31_dec_sub21_upd[1:0] 2'10 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\LDST_dec31_dec_sub21_upd[1:0] 2'10 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\LDST_dec31_dec_sub21_upd[1:0] 2'10 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\LDST_dec31_dec_sub21_upd[1:0] 2'01 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\LDST_dec31_dec_sub21_upd[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\LDST_dec31_dec_sub21_upd[1:0] 2'10 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\LDST_dec31_dec_sub21_upd[1:0] 2'10 + case + assign $1\LDST_dec31_dec_sub21_upd[1:0] 2'00 + end + sync always + update \LDST_dec31_dec_sub21_upd $0\LDST_dec31_dec_sub21_upd[1:0] + end + attribute \src "issuer_ls180.v:11768.3-11816.6" + process $proc$issuer_ls180.v:11768$236 + assign { } { } + assign { } { } + assign $0\LDST_dec31_dec_sub21_rc_sel[1:0] $1\LDST_dec31_dec_sub21_rc_sel[1:0] + attribute \src "issuer_ls180.v:11769.5-11769.29" + switch \initial + attribute \src "issuer_ls180.v:11769.9-11769.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\LDST_dec31_dec_sub21_rc_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\LDST_dec31_dec_sub21_rc_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\LDST_dec31_dec_sub21_rc_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\LDST_dec31_dec_sub21_rc_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\LDST_dec31_dec_sub21_rc_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\LDST_dec31_dec_sub21_rc_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\LDST_dec31_dec_sub21_rc_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\LDST_dec31_dec_sub21_rc_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\LDST_dec31_dec_sub21_rc_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\LDST_dec31_dec_sub21_rc_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\LDST_dec31_dec_sub21_rc_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\LDST_dec31_dec_sub21_rc_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\LDST_dec31_dec_sub21_rc_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\LDST_dec31_dec_sub21_rc_sel[1:0] 2'00 + case + assign $1\LDST_dec31_dec_sub21_rc_sel[1:0] 2'00 + end + sync always + update \LDST_dec31_dec_sub21_rc_sel $0\LDST_dec31_dec_sub21_rc_sel[1:0] + end + connect \opcode_switch \opcode_in [10:6] +end +attribute \src "issuer_ls180.v:11822.1-12447.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.dec_LDST.dec.LDST_dec31.LDST_dec31_dec_sub22" +attribute \generator "nMigen" +module \LDST_dec31_dec_sub22 + attribute \src "issuer_ls180.v:12038.3-12071.6" + wire $0\LDST_dec31_dec_sub22_br[0:0] + attribute \src "issuer_ls180.v:12276.3-12309.6" + wire width 3 $0\LDST_dec31_dec_sub22_cr_in[2:0] + attribute \src "issuer_ls180.v:12310.3-12343.6" + wire width 3 $0\LDST_dec31_dec_sub22_cr_out[2:0] + attribute \src "issuer_ls180.v:12004.3-12037.6" + wire width 12 $0\LDST_dec31_dec_sub22_function_unit[11:0] + attribute \src "issuer_ls180.v:12208.3-12241.6" + wire width 3 $0\LDST_dec31_dec_sub22_in1_sel[2:0] + attribute \src "issuer_ls180.v:12242.3-12275.6" + wire width 4 $0\LDST_dec31_dec_sub22_in2_sel[3:0] + attribute \src "issuer_ls180.v:12174.3-12207.6" + wire width 7 $0\LDST_dec31_dec_sub22_internal_op[6:0] + attribute \src "issuer_ls180.v:12106.3-12139.6" + wire $0\LDST_dec31_dec_sub22_is_32b[0:0] + attribute \src "issuer_ls180.v:12344.3-12377.6" + wire width 4 $0\LDST_dec31_dec_sub22_ldst_len[3:0] + attribute \src "issuer_ls180.v:12412.3-12445.6" + wire width 2 $0\LDST_dec31_dec_sub22_rc_sel[1:0] + attribute \src "issuer_ls180.v:12140.3-12173.6" + wire $0\LDST_dec31_dec_sub22_sgn[0:0] + attribute \src "issuer_ls180.v:12072.3-12105.6" + wire $0\LDST_dec31_dec_sub22_sgn_ext[0:0] + attribute \src "issuer_ls180.v:12378.3-12411.6" + wire width 2 $0\LDST_dec31_dec_sub22_upd[1:0] + attribute \src "issuer_ls180.v:11823.7-11823.20" + wire $0\initial[0:0] + attribute \src "issuer_ls180.v:12038.3-12071.6" + wire $1\LDST_dec31_dec_sub22_br[0:0] + attribute \src "issuer_ls180.v:12276.3-12309.6" + wire width 3 $1\LDST_dec31_dec_sub22_cr_in[2:0] + attribute \src "issuer_ls180.v:12310.3-12343.6" + wire width 3 $1\LDST_dec31_dec_sub22_cr_out[2:0] + attribute \src "issuer_ls180.v:12004.3-12037.6" + wire width 12 $1\LDST_dec31_dec_sub22_function_unit[11:0] + attribute \src "issuer_ls180.v:12208.3-12241.6" + wire width 3 $1\LDST_dec31_dec_sub22_in1_sel[2:0] + attribute \src "issuer_ls180.v:12242.3-12275.6" + wire width 4 $1\LDST_dec31_dec_sub22_in2_sel[3:0] + attribute \src "issuer_ls180.v:12174.3-12207.6" + wire width 7 $1\LDST_dec31_dec_sub22_internal_op[6:0] + attribute \src "issuer_ls180.v:12106.3-12139.6" + wire $1\LDST_dec31_dec_sub22_is_32b[0:0] + attribute \src "issuer_ls180.v:12344.3-12377.6" + wire width 4 $1\LDST_dec31_dec_sub22_ldst_len[3:0] + attribute \src "issuer_ls180.v:12412.3-12445.6" + wire width 2 $1\LDST_dec31_dec_sub22_rc_sel[1:0] + attribute \src "issuer_ls180.v:12140.3-12173.6" + wire $1\LDST_dec31_dec_sub22_sgn[0:0] + attribute \src "issuer_ls180.v:12072.3-12105.6" + wire $1\LDST_dec31_dec_sub22_sgn_ext[0:0] + attribute \src "issuer_ls180.v:12378.3-12411.6" + wire width 2 $1\LDST_dec31_dec_sub22_upd[1:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 10 \LDST_dec31_dec_sub22_br + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 5 \LDST_dec31_dec_sub22_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 6 \LDST_dec31_dec_sub22_cr_out + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 12 output 1 \LDST_dec31_dec_sub22_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 3 \LDST_dec31_dec_sub22_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 output 4 \LDST_dec31_dec_sub22_in2_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 7 output 2 \LDST_dec31_dec_sub22_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 12 \LDST_dec31_dec_sub22_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 output 7 \LDST_dec31_dec_sub22_ldst_len + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 9 \LDST_dec31_dec_sub22_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 13 \LDST_dec31_dec_sub22_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 11 \LDST_dec31_dec_sub22_sgn_ext + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 8 \LDST_dec31_dec_sub22_upd + attribute \src "issuer_ls180.v:11823.7-11823.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + wire width 32 input 14 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:320" + wire width 5 \opcode_switch + attribute \src "issuer_ls180.v:11823.7-11823.20" + process $proc$issuer_ls180.v:11823$251 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "issuer_ls180.v:12004.3-12037.6" + process $proc$issuer_ls180.v:12004$238 + assign { } { } + assign { } { } + assign $0\LDST_dec31_dec_sub22_function_unit[11:0] $1\LDST_dec31_dec_sub22_function_unit[11:0] + attribute \src "issuer_ls180.v:12005.5-12005.29" + switch \initial + attribute \src "issuer_ls180.v:12005.9-12005.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\LDST_dec31_dec_sub22_function_unit[11:0] 12'000000000100 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\LDST_dec31_dec_sub22_function_unit[11:0] 12'000000000100 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\LDST_dec31_dec_sub22_function_unit[11:0] 12'000000000100 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\LDST_dec31_dec_sub22_function_unit[11:0] 12'000000000100 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\LDST_dec31_dec_sub22_function_unit[11:0] 12'000000000100 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\LDST_dec31_dec_sub22_function_unit[11:0] 12'000000000100 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\LDST_dec31_dec_sub22_function_unit[11:0] 12'000000000100 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\LDST_dec31_dec_sub22_function_unit[11:0] 12'000000000100 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\LDST_dec31_dec_sub22_function_unit[11:0] 12'000000000100 + case + assign $1\LDST_dec31_dec_sub22_function_unit[11:0] 12'000000000000 + end + sync always + update \LDST_dec31_dec_sub22_function_unit $0\LDST_dec31_dec_sub22_function_unit[11:0] + end + attribute \src "issuer_ls180.v:12038.3-12071.6" + process $proc$issuer_ls180.v:12038$239 + assign { } { } + assign { } { } + assign $0\LDST_dec31_dec_sub22_br[0:0] $1\LDST_dec31_dec_sub22_br[0:0] + attribute \src "issuer_ls180.v:12039.5-12039.29" + switch \initial + attribute \src "issuer_ls180.v:12039.9-12039.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\LDST_dec31_dec_sub22_br[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\LDST_dec31_dec_sub22_br[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\LDST_dec31_dec_sub22_br[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\LDST_dec31_dec_sub22_br[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\LDST_dec31_dec_sub22_br[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\LDST_dec31_dec_sub22_br[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\LDST_dec31_dec_sub22_br[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\LDST_dec31_dec_sub22_br[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\LDST_dec31_dec_sub22_br[0:0] 1'0 + case + assign $1\LDST_dec31_dec_sub22_br[0:0] 1'0 + end + sync always + update \LDST_dec31_dec_sub22_br $0\LDST_dec31_dec_sub22_br[0:0] + end + attribute \src "issuer_ls180.v:12072.3-12105.6" + process $proc$issuer_ls180.v:12072$240 + assign { } { } + assign { } { } + assign $0\LDST_dec31_dec_sub22_sgn_ext[0:0] $1\LDST_dec31_dec_sub22_sgn_ext[0:0] + attribute \src "issuer_ls180.v:12073.5-12073.29" + switch \initial + attribute \src "issuer_ls180.v:12073.9-12073.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\LDST_dec31_dec_sub22_sgn_ext[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\LDST_dec31_dec_sub22_sgn_ext[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\LDST_dec31_dec_sub22_sgn_ext[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\LDST_dec31_dec_sub22_sgn_ext[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\LDST_dec31_dec_sub22_sgn_ext[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\LDST_dec31_dec_sub22_sgn_ext[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\LDST_dec31_dec_sub22_sgn_ext[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\LDST_dec31_dec_sub22_sgn_ext[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\LDST_dec31_dec_sub22_sgn_ext[0:0] 1'0 + case + assign $1\LDST_dec31_dec_sub22_sgn_ext[0:0] 1'0 + end + sync always + update \LDST_dec31_dec_sub22_sgn_ext $0\LDST_dec31_dec_sub22_sgn_ext[0:0] + end + attribute \src "issuer_ls180.v:12106.3-12139.6" + process $proc$issuer_ls180.v:12106$241 + assign { } { } + assign { } { } + assign $0\LDST_dec31_dec_sub22_is_32b[0:0] $1\LDST_dec31_dec_sub22_is_32b[0:0] + attribute \src "issuer_ls180.v:12107.5-12107.29" + switch \initial + attribute \src "issuer_ls180.v:12107.9-12107.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\LDST_dec31_dec_sub22_is_32b[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\LDST_dec31_dec_sub22_is_32b[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\LDST_dec31_dec_sub22_is_32b[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\LDST_dec31_dec_sub22_is_32b[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\LDST_dec31_dec_sub22_is_32b[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\LDST_dec31_dec_sub22_is_32b[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\LDST_dec31_dec_sub22_is_32b[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\LDST_dec31_dec_sub22_is_32b[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\LDST_dec31_dec_sub22_is_32b[0:0] 1'0 + case + assign $1\LDST_dec31_dec_sub22_is_32b[0:0] 1'0 + end + sync always + update \LDST_dec31_dec_sub22_is_32b $0\LDST_dec31_dec_sub22_is_32b[0:0] + end + attribute \src "issuer_ls180.v:12140.3-12173.6" + process $proc$issuer_ls180.v:12140$242 + assign { } { } + assign { } { } + assign $0\LDST_dec31_dec_sub22_sgn[0:0] $1\LDST_dec31_dec_sub22_sgn[0:0] + attribute \src "issuer_ls180.v:12141.5-12141.29" + switch \initial + attribute \src "issuer_ls180.v:12141.9-12141.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\LDST_dec31_dec_sub22_sgn[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\LDST_dec31_dec_sub22_sgn[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\LDST_dec31_dec_sub22_sgn[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\LDST_dec31_dec_sub22_sgn[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\LDST_dec31_dec_sub22_sgn[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\LDST_dec31_dec_sub22_sgn[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\LDST_dec31_dec_sub22_sgn[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\LDST_dec31_dec_sub22_sgn[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\LDST_dec31_dec_sub22_sgn[0:0] 1'0 + case + assign $1\LDST_dec31_dec_sub22_sgn[0:0] 1'0 + end + sync always + update \LDST_dec31_dec_sub22_sgn $0\LDST_dec31_dec_sub22_sgn[0:0] + end + attribute \src "issuer_ls180.v:12174.3-12207.6" + process $proc$issuer_ls180.v:12174$243 + assign { } { } + assign { } { } + assign $0\LDST_dec31_dec_sub22_internal_op[6:0] $1\LDST_dec31_dec_sub22_internal_op[6:0] + attribute \src "issuer_ls180.v:12175.5-12175.29" + switch \initial + attribute \src "issuer_ls180.v:12175.9-12175.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\LDST_dec31_dec_sub22_internal_op[6:0] 7'0011100 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\LDST_dec31_dec_sub22_internal_op[6:0] 7'0100101 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\LDST_dec31_dec_sub22_internal_op[6:0] 7'0100101 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\LDST_dec31_dec_sub22_internal_op[6:0] 7'0100110 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\LDST_dec31_dec_sub22_internal_op[6:0] 7'0100110 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\LDST_dec31_dec_sub22_internal_op[6:0] 7'0100110 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\LDST_dec31_dec_sub22_internal_op[6:0] 7'0100110 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\LDST_dec31_dec_sub22_internal_op[6:0] 7'0100110 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\LDST_dec31_dec_sub22_internal_op[6:0] 7'0100110 + case + assign $1\LDST_dec31_dec_sub22_internal_op[6:0] 7'0000000 + end + sync always + update \LDST_dec31_dec_sub22_internal_op $0\LDST_dec31_dec_sub22_internal_op[6:0] + end + attribute \src "issuer_ls180.v:12208.3-12241.6" + process $proc$issuer_ls180.v:12208$244 + assign { } { } + assign { } { } + assign $0\LDST_dec31_dec_sub22_in1_sel[2:0] $1\LDST_dec31_dec_sub22_in1_sel[2:0] + attribute \src "issuer_ls180.v:12209.5-12209.29" + switch \initial + attribute \src "issuer_ls180.v:12209.9-12209.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\LDST_dec31_dec_sub22_in1_sel[2:0] 3'010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\LDST_dec31_dec_sub22_in1_sel[2:0] 3'010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\LDST_dec31_dec_sub22_in1_sel[2:0] 3'010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\LDST_dec31_dec_sub22_in1_sel[2:0] 3'010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\LDST_dec31_dec_sub22_in1_sel[2:0] 3'010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\LDST_dec31_dec_sub22_in1_sel[2:0] 3'010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\LDST_dec31_dec_sub22_in1_sel[2:0] 3'010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\LDST_dec31_dec_sub22_in1_sel[2:0] 3'010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\LDST_dec31_dec_sub22_in1_sel[2:0] 3'010 + case + assign $1\LDST_dec31_dec_sub22_in1_sel[2:0] 3'000 + end + sync always + update \LDST_dec31_dec_sub22_in1_sel $0\LDST_dec31_dec_sub22_in1_sel[2:0] + end + attribute \src "issuer_ls180.v:12242.3-12275.6" + process $proc$issuer_ls180.v:12242$245 + assign { } { } + assign { } { } + assign $0\LDST_dec31_dec_sub22_in2_sel[3:0] $1\LDST_dec31_dec_sub22_in2_sel[3:0] + attribute \src "issuer_ls180.v:12243.5-12243.29" + switch \initial + attribute \src "issuer_ls180.v:12243.9-12243.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\LDST_dec31_dec_sub22_in2_sel[3:0] 4'0001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\LDST_dec31_dec_sub22_in2_sel[3:0] 4'0001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\LDST_dec31_dec_sub22_in2_sel[3:0] 4'0001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\LDST_dec31_dec_sub22_in2_sel[3:0] 4'0001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\LDST_dec31_dec_sub22_in2_sel[3:0] 4'0001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\LDST_dec31_dec_sub22_in2_sel[3:0] 4'0001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\LDST_dec31_dec_sub22_in2_sel[3:0] 4'0001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\LDST_dec31_dec_sub22_in2_sel[3:0] 4'0001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\LDST_dec31_dec_sub22_in2_sel[3:0] 4'0001 + case + assign $1\LDST_dec31_dec_sub22_in2_sel[3:0] 4'0000 + end + sync always + update \LDST_dec31_dec_sub22_in2_sel $0\LDST_dec31_dec_sub22_in2_sel[3:0] + end + attribute \src "issuer_ls180.v:12276.3-12309.6" + process $proc$issuer_ls180.v:12276$246 + assign { } { } + assign { } { } + assign $0\LDST_dec31_dec_sub22_cr_in[2:0] $1\LDST_dec31_dec_sub22_cr_in[2:0] + attribute \src "issuer_ls180.v:12277.5-12277.29" + switch \initial + attribute \src "issuer_ls180.v:12277.9-12277.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\LDST_dec31_dec_sub22_cr_in[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\LDST_dec31_dec_sub22_cr_in[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\LDST_dec31_dec_sub22_cr_in[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\LDST_dec31_dec_sub22_cr_in[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\LDST_dec31_dec_sub22_cr_in[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\LDST_dec31_dec_sub22_cr_in[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\LDST_dec31_dec_sub22_cr_in[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\LDST_dec31_dec_sub22_cr_in[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\LDST_dec31_dec_sub22_cr_in[2:0] 3'000 + case + assign $1\LDST_dec31_dec_sub22_cr_in[2:0] 3'000 + end + sync always + update \LDST_dec31_dec_sub22_cr_in $0\LDST_dec31_dec_sub22_cr_in[2:0] + end + attribute \src "issuer_ls180.v:12310.3-12343.6" + process $proc$issuer_ls180.v:12310$247 + assign { } { } + assign { } { } + assign $0\LDST_dec31_dec_sub22_cr_out[2:0] $1\LDST_dec31_dec_sub22_cr_out[2:0] + attribute \src "issuer_ls180.v:12311.5-12311.29" + switch \initial + attribute \src "issuer_ls180.v:12311.9-12311.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\LDST_dec31_dec_sub22_cr_out[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\LDST_dec31_dec_sub22_cr_out[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\LDST_dec31_dec_sub22_cr_out[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\LDST_dec31_dec_sub22_cr_out[2:0] 3'001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\LDST_dec31_dec_sub22_cr_out[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\LDST_dec31_dec_sub22_cr_out[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\LDST_dec31_dec_sub22_cr_out[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\LDST_dec31_dec_sub22_cr_out[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\LDST_dec31_dec_sub22_cr_out[2:0] 3'000 + case + assign $1\LDST_dec31_dec_sub22_cr_out[2:0] 3'000 + end + sync always + update \LDST_dec31_dec_sub22_cr_out $0\LDST_dec31_dec_sub22_cr_out[2:0] + end + attribute \src "issuer_ls180.v:12344.3-12377.6" + process $proc$issuer_ls180.v:12344$248 + assign { } { } + assign { } { } + assign $0\LDST_dec31_dec_sub22_ldst_len[3:0] $1\LDST_dec31_dec_sub22_ldst_len[3:0] + attribute \src "issuer_ls180.v:12345.5-12345.29" + switch \initial + attribute \src "issuer_ls180.v:12345.9-12345.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\LDST_dec31_dec_sub22_ldst_len[3:0] 4'0000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\LDST_dec31_dec_sub22_ldst_len[3:0] 4'0010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\LDST_dec31_dec_sub22_ldst_len[3:0] 4'0100 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\LDST_dec31_dec_sub22_ldst_len[3:0] 4'0001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\LDST_dec31_dec_sub22_ldst_len[3:0] 4'1000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\LDST_dec31_dec_sub22_ldst_len[3:0] 4'0010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\LDST_dec31_dec_sub22_ldst_len[3:0] 4'0010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\LDST_dec31_dec_sub22_ldst_len[3:0] 4'0100 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\LDST_dec31_dec_sub22_ldst_len[3:0] 4'0100 + case + assign $1\LDST_dec31_dec_sub22_ldst_len[3:0] 4'0000 + end + sync always + update \LDST_dec31_dec_sub22_ldst_len $0\LDST_dec31_dec_sub22_ldst_len[3:0] + end + attribute \src "issuer_ls180.v:12378.3-12411.6" + process $proc$issuer_ls180.v:12378$249 + assign { } { } + assign { } { } + assign $0\LDST_dec31_dec_sub22_upd[1:0] $1\LDST_dec31_dec_sub22_upd[1:0] + attribute \src "issuer_ls180.v:12379.5-12379.29" + switch \initial + attribute \src "issuer_ls180.v:12379.9-12379.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\LDST_dec31_dec_sub22_upd[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\LDST_dec31_dec_sub22_upd[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\LDST_dec31_dec_sub22_upd[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\LDST_dec31_dec_sub22_upd[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\LDST_dec31_dec_sub22_upd[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\LDST_dec31_dec_sub22_upd[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\LDST_dec31_dec_sub22_upd[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\LDST_dec31_dec_sub22_upd[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\LDST_dec31_dec_sub22_upd[1:0] 2'00 + case + assign $1\LDST_dec31_dec_sub22_upd[1:0] 2'00 + end + sync always + update \LDST_dec31_dec_sub22_upd $0\LDST_dec31_dec_sub22_upd[1:0] + end + attribute \src "issuer_ls180.v:12412.3-12445.6" + process $proc$issuer_ls180.v:12412$250 + assign { } { } + assign { } { } + assign $0\LDST_dec31_dec_sub22_rc_sel[1:0] $1\LDST_dec31_dec_sub22_rc_sel[1:0] + attribute \src "issuer_ls180.v:12413.5-12413.29" + switch \initial + attribute \src "issuer_ls180.v:12413.9-12413.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\LDST_dec31_dec_sub22_rc_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\LDST_dec31_dec_sub22_rc_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\LDST_dec31_dec_sub22_rc_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\LDST_dec31_dec_sub22_rc_sel[1:0] 2'10 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\LDST_dec31_dec_sub22_rc_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\LDST_dec31_dec_sub22_rc_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\LDST_dec31_dec_sub22_rc_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\LDST_dec31_dec_sub22_rc_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\LDST_dec31_dec_sub22_rc_sel[1:0] 2'00 + case + assign $1\LDST_dec31_dec_sub22_rc_sel[1:0] 2'00 + end + sync always + update \LDST_dec31_dec_sub22_rc_sel $0\LDST_dec31_dec_sub22_rc_sel[1:0] + end + connect \opcode_switch \opcode_in [10:6] +end +attribute \src "issuer_ls180.v:12451.1-13271.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.dec_LDST.dec.LDST_dec31.LDST_dec31_dec_sub23" +attribute \generator "nMigen" +module \LDST_dec31_dec_sub23 + attribute \src "issuer_ls180.v:12682.3-12730.6" + wire $0\LDST_dec31_dec_sub23_br[0:0] + attribute \src "issuer_ls180.v:13025.3-13073.6" + wire width 3 $0\LDST_dec31_dec_sub23_cr_in[2:0] + attribute \src "issuer_ls180.v:13074.3-13122.6" + wire width 3 $0\LDST_dec31_dec_sub23_cr_out[2:0] + attribute \src "issuer_ls180.v:12633.3-12681.6" + wire width 12 $0\LDST_dec31_dec_sub23_function_unit[11:0] + attribute \src "issuer_ls180.v:12927.3-12975.6" + wire width 3 $0\LDST_dec31_dec_sub23_in1_sel[2:0] + attribute \src "issuer_ls180.v:12976.3-13024.6" + wire width 4 $0\LDST_dec31_dec_sub23_in2_sel[3:0] + attribute \src "issuer_ls180.v:12878.3-12926.6" + wire width 7 $0\LDST_dec31_dec_sub23_internal_op[6:0] + attribute \src "issuer_ls180.v:12780.3-12828.6" + wire $0\LDST_dec31_dec_sub23_is_32b[0:0] + attribute \src "issuer_ls180.v:13123.3-13171.6" + wire width 4 $0\LDST_dec31_dec_sub23_ldst_len[3:0] + attribute \src "issuer_ls180.v:13221.3-13269.6" + wire width 2 $0\LDST_dec31_dec_sub23_rc_sel[1:0] + attribute \src "issuer_ls180.v:12829.3-12877.6" + wire $0\LDST_dec31_dec_sub23_sgn[0:0] + attribute \src "issuer_ls180.v:12731.3-12779.6" + wire $0\LDST_dec31_dec_sub23_sgn_ext[0:0] + attribute \src "issuer_ls180.v:13172.3-13220.6" + wire width 2 $0\LDST_dec31_dec_sub23_upd[1:0] + attribute \src "issuer_ls180.v:12452.7-12452.20" + wire $0\initial[0:0] + attribute \src "issuer_ls180.v:12682.3-12730.6" + wire $1\LDST_dec31_dec_sub23_br[0:0] + attribute \src "issuer_ls180.v:13025.3-13073.6" + wire width 3 $1\LDST_dec31_dec_sub23_cr_in[2:0] + attribute \src "issuer_ls180.v:13074.3-13122.6" + wire width 3 $1\LDST_dec31_dec_sub23_cr_out[2:0] + attribute \src "issuer_ls180.v:12633.3-12681.6" + wire width 12 $1\LDST_dec31_dec_sub23_function_unit[11:0] + attribute \src "issuer_ls180.v:12927.3-12975.6" + wire width 3 $1\LDST_dec31_dec_sub23_in1_sel[2:0] + attribute \src "issuer_ls180.v:12976.3-13024.6" + wire width 4 $1\LDST_dec31_dec_sub23_in2_sel[3:0] + attribute \src "issuer_ls180.v:12878.3-12926.6" + wire width 7 $1\LDST_dec31_dec_sub23_internal_op[6:0] + attribute \src "issuer_ls180.v:12780.3-12828.6" + wire $1\LDST_dec31_dec_sub23_is_32b[0:0] + attribute \src "issuer_ls180.v:13123.3-13171.6" + wire width 4 $1\LDST_dec31_dec_sub23_ldst_len[3:0] + attribute \src "issuer_ls180.v:13221.3-13269.6" + wire width 2 $1\LDST_dec31_dec_sub23_rc_sel[1:0] + attribute \src "issuer_ls180.v:12829.3-12877.6" + wire $1\LDST_dec31_dec_sub23_sgn[0:0] + attribute \src "issuer_ls180.v:12731.3-12779.6" + wire $1\LDST_dec31_dec_sub23_sgn_ext[0:0] + attribute \src "issuer_ls180.v:13172.3-13220.6" + wire width 2 $1\LDST_dec31_dec_sub23_upd[1:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 10 \LDST_dec31_dec_sub23_br + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 5 \LDST_dec31_dec_sub23_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 6 \LDST_dec31_dec_sub23_cr_out + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 12 output 1 \LDST_dec31_dec_sub23_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 3 \LDST_dec31_dec_sub23_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 output 4 \LDST_dec31_dec_sub23_in2_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 7 output 2 \LDST_dec31_dec_sub23_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 12 \LDST_dec31_dec_sub23_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 output 7 \LDST_dec31_dec_sub23_ldst_len + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 9 \LDST_dec31_dec_sub23_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 13 \LDST_dec31_dec_sub23_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 11 \LDST_dec31_dec_sub23_sgn_ext + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 8 \LDST_dec31_dec_sub23_upd + attribute \src "issuer_ls180.v:12452.7-12452.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + wire width 32 input 14 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:320" + wire width 5 \opcode_switch + attribute \src "issuer_ls180.v:12452.7-12452.20" + process $proc$issuer_ls180.v:12452$265 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "issuer_ls180.v:12633.3-12681.6" + process $proc$issuer_ls180.v:12633$252 + assign { } { } + assign { } { } + assign $0\LDST_dec31_dec_sub23_function_unit[11:0] $1\LDST_dec31_dec_sub23_function_unit[11:0] + attribute \src "issuer_ls180.v:12634.5-12634.29" + switch \initial + attribute \src "issuer_ls180.v:12634.9-12634.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\LDST_dec31_dec_sub23_function_unit[11:0] 12'000000000100 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\LDST_dec31_dec_sub23_function_unit[11:0] 12'000000000100 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\LDST_dec31_dec_sub23_function_unit[11:0] 12'000000000100 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\LDST_dec31_dec_sub23_function_unit[11:0] 12'000000000100 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\LDST_dec31_dec_sub23_function_unit[11:0] 12'000000000100 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\LDST_dec31_dec_sub23_function_unit[11:0] 12'000000000100 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\LDST_dec31_dec_sub23_function_unit[11:0] 12'000000000100 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\LDST_dec31_dec_sub23_function_unit[11:0] 12'000000000100 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\LDST_dec31_dec_sub23_function_unit[11:0] 12'000000000100 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\LDST_dec31_dec_sub23_function_unit[11:0] 12'000000000100 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\LDST_dec31_dec_sub23_function_unit[11:0] 12'000000000100 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\LDST_dec31_dec_sub23_function_unit[11:0] 12'000000000100 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\LDST_dec31_dec_sub23_function_unit[11:0] 12'000000000100 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\LDST_dec31_dec_sub23_function_unit[11:0] 12'000000000100 + case + assign $1\LDST_dec31_dec_sub23_function_unit[11:0] 12'000000000000 + end + sync always + update \LDST_dec31_dec_sub23_function_unit $0\LDST_dec31_dec_sub23_function_unit[11:0] + end + attribute \src "issuer_ls180.v:12682.3-12730.6" + process $proc$issuer_ls180.v:12682$253 + assign { } { } + assign { } { } + assign $0\LDST_dec31_dec_sub23_br[0:0] $1\LDST_dec31_dec_sub23_br[0:0] + attribute \src "issuer_ls180.v:12683.5-12683.29" + switch \initial + attribute \src "issuer_ls180.v:12683.9-12683.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\LDST_dec31_dec_sub23_br[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\LDST_dec31_dec_sub23_br[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\LDST_dec31_dec_sub23_br[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\LDST_dec31_dec_sub23_br[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\LDST_dec31_dec_sub23_br[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\LDST_dec31_dec_sub23_br[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\LDST_dec31_dec_sub23_br[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\LDST_dec31_dec_sub23_br[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\LDST_dec31_dec_sub23_br[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\LDST_dec31_dec_sub23_br[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\LDST_dec31_dec_sub23_br[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\LDST_dec31_dec_sub23_br[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\LDST_dec31_dec_sub23_br[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\LDST_dec31_dec_sub23_br[0:0] 1'0 + case + assign $1\LDST_dec31_dec_sub23_br[0:0] 1'0 + end + sync always + update \LDST_dec31_dec_sub23_br $0\LDST_dec31_dec_sub23_br[0:0] + end + attribute \src "issuer_ls180.v:12731.3-12779.6" + process $proc$issuer_ls180.v:12731$254 + assign { } { } + assign { } { } + assign $0\LDST_dec31_dec_sub23_sgn_ext[0:0] $1\LDST_dec31_dec_sub23_sgn_ext[0:0] + attribute \src "issuer_ls180.v:12732.5-12732.29" + switch \initial + attribute \src "issuer_ls180.v:12732.9-12732.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\LDST_dec31_dec_sub23_sgn_ext[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\LDST_dec31_dec_sub23_sgn_ext[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\LDST_dec31_dec_sub23_sgn_ext[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\LDST_dec31_dec_sub23_sgn_ext[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\LDST_dec31_dec_sub23_sgn_ext[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\LDST_dec31_dec_sub23_sgn_ext[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\LDST_dec31_dec_sub23_sgn_ext[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\LDST_dec31_dec_sub23_sgn_ext[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\LDST_dec31_dec_sub23_sgn_ext[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\LDST_dec31_dec_sub23_sgn_ext[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\LDST_dec31_dec_sub23_sgn_ext[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\LDST_dec31_dec_sub23_sgn_ext[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\LDST_dec31_dec_sub23_sgn_ext[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\LDST_dec31_dec_sub23_sgn_ext[0:0] 1'0 + case + assign $1\LDST_dec31_dec_sub23_sgn_ext[0:0] 1'0 + end + sync always + update \LDST_dec31_dec_sub23_sgn_ext $0\LDST_dec31_dec_sub23_sgn_ext[0:0] + end + attribute \src "issuer_ls180.v:12780.3-12828.6" + process $proc$issuer_ls180.v:12780$255 + assign { } { } + assign { } { } + assign $0\LDST_dec31_dec_sub23_is_32b[0:0] $1\LDST_dec31_dec_sub23_is_32b[0:0] + attribute \src "issuer_ls180.v:12781.5-12781.29" + switch \initial + attribute \src "issuer_ls180.v:12781.9-12781.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\LDST_dec31_dec_sub23_is_32b[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\LDST_dec31_dec_sub23_is_32b[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\LDST_dec31_dec_sub23_is_32b[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\LDST_dec31_dec_sub23_is_32b[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\LDST_dec31_dec_sub23_is_32b[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\LDST_dec31_dec_sub23_is_32b[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\LDST_dec31_dec_sub23_is_32b[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\LDST_dec31_dec_sub23_is_32b[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\LDST_dec31_dec_sub23_is_32b[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\LDST_dec31_dec_sub23_is_32b[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\LDST_dec31_dec_sub23_is_32b[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\LDST_dec31_dec_sub23_is_32b[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\LDST_dec31_dec_sub23_is_32b[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\LDST_dec31_dec_sub23_is_32b[0:0] 1'0 + case + assign $1\LDST_dec31_dec_sub23_is_32b[0:0] 1'0 + end + sync always + update \LDST_dec31_dec_sub23_is_32b $0\LDST_dec31_dec_sub23_is_32b[0:0] + end + attribute \src "issuer_ls180.v:12829.3-12877.6" + process $proc$issuer_ls180.v:12829$256 + assign { } { } + assign { } { } + assign $0\LDST_dec31_dec_sub23_sgn[0:0] $1\LDST_dec31_dec_sub23_sgn[0:0] + attribute \src "issuer_ls180.v:12830.5-12830.29" + switch \initial + attribute \src "issuer_ls180.v:12830.9-12830.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\LDST_dec31_dec_sub23_sgn[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\LDST_dec31_dec_sub23_sgn[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\LDST_dec31_dec_sub23_sgn[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\LDST_dec31_dec_sub23_sgn[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\LDST_dec31_dec_sub23_sgn[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\LDST_dec31_dec_sub23_sgn[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\LDST_dec31_dec_sub23_sgn[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\LDST_dec31_dec_sub23_sgn[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\LDST_dec31_dec_sub23_sgn[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\LDST_dec31_dec_sub23_sgn[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\LDST_dec31_dec_sub23_sgn[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\LDST_dec31_dec_sub23_sgn[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\LDST_dec31_dec_sub23_sgn[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\LDST_dec31_dec_sub23_sgn[0:0] 1'0 + case + assign $1\LDST_dec31_dec_sub23_sgn[0:0] 1'0 + end + sync always + update \LDST_dec31_dec_sub23_sgn $0\LDST_dec31_dec_sub23_sgn[0:0] + end + attribute \src "issuer_ls180.v:12878.3-12926.6" + process $proc$issuer_ls180.v:12878$257 + assign { } { } + assign { } { } + assign $0\LDST_dec31_dec_sub23_internal_op[6:0] $1\LDST_dec31_dec_sub23_internal_op[6:0] + attribute \src "issuer_ls180.v:12879.5-12879.29" + switch \initial + attribute \src "issuer_ls180.v:12879.9-12879.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\LDST_dec31_dec_sub23_internal_op[6:0] 7'0100101 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\LDST_dec31_dec_sub23_internal_op[6:0] 7'0100101 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\LDST_dec31_dec_sub23_internal_op[6:0] 7'0100101 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\LDST_dec31_dec_sub23_internal_op[6:0] 7'0100101 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\LDST_dec31_dec_sub23_internal_op[6:0] 7'0100101 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\LDST_dec31_dec_sub23_internal_op[6:0] 7'0100101 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\LDST_dec31_dec_sub23_internal_op[6:0] 7'0100101 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\LDST_dec31_dec_sub23_internal_op[6:0] 7'0100101 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\LDST_dec31_dec_sub23_internal_op[6:0] 7'0100110 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\LDST_dec31_dec_sub23_internal_op[6:0] 7'0100110 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\LDST_dec31_dec_sub23_internal_op[6:0] 7'0100110 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\LDST_dec31_dec_sub23_internal_op[6:0] 7'0100110 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\LDST_dec31_dec_sub23_internal_op[6:0] 7'0100110 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\LDST_dec31_dec_sub23_internal_op[6:0] 7'0100110 + case + assign $1\LDST_dec31_dec_sub23_internal_op[6:0] 7'0000000 + end + sync always + update \LDST_dec31_dec_sub23_internal_op $0\LDST_dec31_dec_sub23_internal_op[6:0] + end + attribute \src "issuer_ls180.v:12927.3-12975.6" + process $proc$issuer_ls180.v:12927$258 + assign { } { } + assign { } { } + assign $0\LDST_dec31_dec_sub23_in1_sel[2:0] $1\LDST_dec31_dec_sub23_in1_sel[2:0] + attribute \src "issuer_ls180.v:12928.5-12928.29" + switch \initial + attribute \src "issuer_ls180.v:12928.9-12928.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\LDST_dec31_dec_sub23_in1_sel[2:0] 3'010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\LDST_dec31_dec_sub23_in1_sel[2:0] 3'010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\LDST_dec31_dec_sub23_in1_sel[2:0] 3'010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\LDST_dec31_dec_sub23_in1_sel[2:0] 3'010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\LDST_dec31_dec_sub23_in1_sel[2:0] 3'010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\LDST_dec31_dec_sub23_in1_sel[2:0] 3'010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\LDST_dec31_dec_sub23_in1_sel[2:0] 3'010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\LDST_dec31_dec_sub23_in1_sel[2:0] 3'010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\LDST_dec31_dec_sub23_in1_sel[2:0] 3'010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\LDST_dec31_dec_sub23_in1_sel[2:0] 3'010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\LDST_dec31_dec_sub23_in1_sel[2:0] 3'010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\LDST_dec31_dec_sub23_in1_sel[2:0] 3'010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\LDST_dec31_dec_sub23_in1_sel[2:0] 3'010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\LDST_dec31_dec_sub23_in1_sel[2:0] 3'010 + case + assign $1\LDST_dec31_dec_sub23_in1_sel[2:0] 3'000 + end + sync always + update \LDST_dec31_dec_sub23_in1_sel $0\LDST_dec31_dec_sub23_in1_sel[2:0] + end + attribute \src "issuer_ls180.v:12976.3-13024.6" + process $proc$issuer_ls180.v:12976$259 + assign { } { } + assign { } { } + assign $0\LDST_dec31_dec_sub23_in2_sel[3:0] $1\LDST_dec31_dec_sub23_in2_sel[3:0] + attribute \src "issuer_ls180.v:12977.5-12977.29" + switch \initial + attribute \src "issuer_ls180.v:12977.9-12977.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\LDST_dec31_dec_sub23_in2_sel[3:0] 4'0001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\LDST_dec31_dec_sub23_in2_sel[3:0] 4'0001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\LDST_dec31_dec_sub23_in2_sel[3:0] 4'0001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\LDST_dec31_dec_sub23_in2_sel[3:0] 4'0001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\LDST_dec31_dec_sub23_in2_sel[3:0] 4'0001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\LDST_dec31_dec_sub23_in2_sel[3:0] 4'0001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\LDST_dec31_dec_sub23_in2_sel[3:0] 4'0001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\LDST_dec31_dec_sub23_in2_sel[3:0] 4'0001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\LDST_dec31_dec_sub23_in2_sel[3:0] 4'0001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\LDST_dec31_dec_sub23_in2_sel[3:0] 4'0001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\LDST_dec31_dec_sub23_in2_sel[3:0] 4'0001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\LDST_dec31_dec_sub23_in2_sel[3:0] 4'0001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\LDST_dec31_dec_sub23_in2_sel[3:0] 4'0001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\LDST_dec31_dec_sub23_in2_sel[3:0] 4'0001 + case + assign $1\LDST_dec31_dec_sub23_in2_sel[3:0] 4'0000 + end + sync always + update \LDST_dec31_dec_sub23_in2_sel $0\LDST_dec31_dec_sub23_in2_sel[3:0] + end + attribute \src "issuer_ls180.v:13025.3-13073.6" + process $proc$issuer_ls180.v:13025$260 + assign { } { } + assign { } { } + assign $0\LDST_dec31_dec_sub23_cr_in[2:0] $1\LDST_dec31_dec_sub23_cr_in[2:0] + attribute \src "issuer_ls180.v:13026.5-13026.29" + switch \initial + attribute \src "issuer_ls180.v:13026.9-13026.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\LDST_dec31_dec_sub23_cr_in[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\LDST_dec31_dec_sub23_cr_in[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\LDST_dec31_dec_sub23_cr_in[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\LDST_dec31_dec_sub23_cr_in[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\LDST_dec31_dec_sub23_cr_in[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\LDST_dec31_dec_sub23_cr_in[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\LDST_dec31_dec_sub23_cr_in[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\LDST_dec31_dec_sub23_cr_in[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\LDST_dec31_dec_sub23_cr_in[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\LDST_dec31_dec_sub23_cr_in[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\LDST_dec31_dec_sub23_cr_in[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\LDST_dec31_dec_sub23_cr_in[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\LDST_dec31_dec_sub23_cr_in[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\LDST_dec31_dec_sub23_cr_in[2:0] 3'000 + case + assign $1\LDST_dec31_dec_sub23_cr_in[2:0] 3'000 + end + sync always + update \LDST_dec31_dec_sub23_cr_in $0\LDST_dec31_dec_sub23_cr_in[2:0] + end + attribute \src "issuer_ls180.v:13074.3-13122.6" + process $proc$issuer_ls180.v:13074$261 + assign { } { } + assign { } { } + assign $0\LDST_dec31_dec_sub23_cr_out[2:0] $1\LDST_dec31_dec_sub23_cr_out[2:0] + attribute \src "issuer_ls180.v:13075.5-13075.29" + switch \initial + attribute \src "issuer_ls180.v:13075.9-13075.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\LDST_dec31_dec_sub23_cr_out[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\LDST_dec31_dec_sub23_cr_out[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\LDST_dec31_dec_sub23_cr_out[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\LDST_dec31_dec_sub23_cr_out[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\LDST_dec31_dec_sub23_cr_out[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\LDST_dec31_dec_sub23_cr_out[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\LDST_dec31_dec_sub23_cr_out[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\LDST_dec31_dec_sub23_cr_out[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\LDST_dec31_dec_sub23_cr_out[2:0] 3'001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\LDST_dec31_dec_sub23_cr_out[2:0] 3'001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\LDST_dec31_dec_sub23_cr_out[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\LDST_dec31_dec_sub23_cr_out[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\LDST_dec31_dec_sub23_cr_out[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\LDST_dec31_dec_sub23_cr_out[2:0] 3'000 + case + assign $1\LDST_dec31_dec_sub23_cr_out[2:0] 3'000 + end + sync always + update \LDST_dec31_dec_sub23_cr_out $0\LDST_dec31_dec_sub23_cr_out[2:0] + end + attribute \src "issuer_ls180.v:13123.3-13171.6" + process $proc$issuer_ls180.v:13123$262 + assign { } { } + assign { } { } + assign $0\LDST_dec31_dec_sub23_ldst_len[3:0] $1\LDST_dec31_dec_sub23_ldst_len[3:0] + attribute \src "issuer_ls180.v:13124.5-13124.29" + switch \initial + attribute \src "issuer_ls180.v:13124.9-13124.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\LDST_dec31_dec_sub23_ldst_len[3:0] 4'0001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\LDST_dec31_dec_sub23_ldst_len[3:0] 4'0001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\LDST_dec31_dec_sub23_ldst_len[3:0] 4'0010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\LDST_dec31_dec_sub23_ldst_len[3:0] 4'0010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\LDST_dec31_dec_sub23_ldst_len[3:0] 4'0010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\LDST_dec31_dec_sub23_ldst_len[3:0] 4'0010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\LDST_dec31_dec_sub23_ldst_len[3:0] 4'0100 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\LDST_dec31_dec_sub23_ldst_len[3:0] 4'0100 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\LDST_dec31_dec_sub23_ldst_len[3:0] 4'0001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\LDST_dec31_dec_sub23_ldst_len[3:0] 4'0001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\LDST_dec31_dec_sub23_ldst_len[3:0] 4'0010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\LDST_dec31_dec_sub23_ldst_len[3:0] 4'0010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\LDST_dec31_dec_sub23_ldst_len[3:0] 4'0100 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\LDST_dec31_dec_sub23_ldst_len[3:0] 4'0100 + case + assign $1\LDST_dec31_dec_sub23_ldst_len[3:0] 4'0000 + end + sync always + update \LDST_dec31_dec_sub23_ldst_len $0\LDST_dec31_dec_sub23_ldst_len[3:0] + end + attribute \src "issuer_ls180.v:13172.3-13220.6" + process $proc$issuer_ls180.v:13172$263 + assign { } { } + assign { } { } + assign $0\LDST_dec31_dec_sub23_upd[1:0] $1\LDST_dec31_dec_sub23_upd[1:0] + attribute \src "issuer_ls180.v:13173.5-13173.29" + switch \initial + attribute \src "issuer_ls180.v:13173.9-13173.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\LDST_dec31_dec_sub23_upd[1:0] 2'01 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\LDST_dec31_dec_sub23_upd[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\LDST_dec31_dec_sub23_upd[1:0] 2'01 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\LDST_dec31_dec_sub23_upd[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\LDST_dec31_dec_sub23_upd[1:0] 2'01 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\LDST_dec31_dec_sub23_upd[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\LDST_dec31_dec_sub23_upd[1:0] 2'01 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\LDST_dec31_dec_sub23_upd[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\LDST_dec31_dec_sub23_upd[1:0] 2'01 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\LDST_dec31_dec_sub23_upd[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\LDST_dec31_dec_sub23_upd[1:0] 2'01 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\LDST_dec31_dec_sub23_upd[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\LDST_dec31_dec_sub23_upd[1:0] 2'01 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\LDST_dec31_dec_sub23_upd[1:0] 2'00 + case + assign $1\LDST_dec31_dec_sub23_upd[1:0] 2'00 + end + sync always + update \LDST_dec31_dec_sub23_upd $0\LDST_dec31_dec_sub23_upd[1:0] + end + attribute \src "issuer_ls180.v:13221.3-13269.6" + process $proc$issuer_ls180.v:13221$264 + assign { } { } + assign { } { } + assign $0\LDST_dec31_dec_sub23_rc_sel[1:0] $1\LDST_dec31_dec_sub23_rc_sel[1:0] + attribute \src "issuer_ls180.v:13222.5-13222.29" + switch \initial + attribute \src "issuer_ls180.v:13222.9-13222.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\LDST_dec31_dec_sub23_rc_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\LDST_dec31_dec_sub23_rc_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\LDST_dec31_dec_sub23_rc_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\LDST_dec31_dec_sub23_rc_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\LDST_dec31_dec_sub23_rc_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\LDST_dec31_dec_sub23_rc_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\LDST_dec31_dec_sub23_rc_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\LDST_dec31_dec_sub23_rc_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\LDST_dec31_dec_sub23_rc_sel[1:0] 2'10 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\LDST_dec31_dec_sub23_rc_sel[1:0] 2'10 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\LDST_dec31_dec_sub23_rc_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\LDST_dec31_dec_sub23_rc_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\LDST_dec31_dec_sub23_rc_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\LDST_dec31_dec_sub23_rc_sel[1:0] 2'00 + case + assign $1\LDST_dec31_dec_sub23_rc_sel[1:0] 2'00 + end + sync always + update \LDST_dec31_dec_sub23_rc_sel $0\LDST_dec31_dec_sub23_rc_sel[1:0] + end + connect \opcode_switch \opcode_in [10:6] +end +attribute \src "issuer_ls180.v:13275.1-13666.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.dec_LDST.dec.LDST_dec58" +attribute \generator "nMigen" +module \LDST_dec58 + attribute \src "issuer_ls180.v:13473.3-13488.6" + wire $0\LDST_dec58_br[0:0] + attribute \src "issuer_ls180.v:13585.3-13600.6" + wire width 3 $0\LDST_dec58_cr_in[2:0] + attribute \src "issuer_ls180.v:13601.3-13616.6" + wire width 3 $0\LDST_dec58_cr_out[2:0] + attribute \src "issuer_ls180.v:13457.3-13472.6" + wire width 12 $0\LDST_dec58_function_unit[11:0] + attribute \src "issuer_ls180.v:13553.3-13568.6" + wire width 3 $0\LDST_dec58_in1_sel[2:0] + attribute \src "issuer_ls180.v:13569.3-13584.6" + wire width 4 $0\LDST_dec58_in2_sel[3:0] + attribute \src "issuer_ls180.v:13537.3-13552.6" + wire width 7 $0\LDST_dec58_internal_op[6:0] + attribute \src "issuer_ls180.v:13505.3-13520.6" + wire $0\LDST_dec58_is_32b[0:0] + attribute \src "issuer_ls180.v:13617.3-13632.6" + wire width 4 $0\LDST_dec58_ldst_len[3:0] + attribute \src "issuer_ls180.v:13649.3-13664.6" + wire width 2 $0\LDST_dec58_rc_sel[1:0] + attribute \src "issuer_ls180.v:13521.3-13536.6" + wire $0\LDST_dec58_sgn[0:0] + attribute \src "issuer_ls180.v:13489.3-13504.6" + wire $0\LDST_dec58_sgn_ext[0:0] + attribute \src "issuer_ls180.v:13633.3-13648.6" + wire width 2 $0\LDST_dec58_upd[1:0] + attribute \src "issuer_ls180.v:13276.7-13276.20" + wire $0\initial[0:0] + attribute \src "issuer_ls180.v:13473.3-13488.6" + wire $1\LDST_dec58_br[0:0] + attribute \src "issuer_ls180.v:13585.3-13600.6" + wire width 3 $1\LDST_dec58_cr_in[2:0] + attribute \src "issuer_ls180.v:13601.3-13616.6" + wire width 3 $1\LDST_dec58_cr_out[2:0] + attribute \src "issuer_ls180.v:13457.3-13472.6" + wire width 12 $1\LDST_dec58_function_unit[11:0] + attribute \src "issuer_ls180.v:13553.3-13568.6" + wire width 3 $1\LDST_dec58_in1_sel[2:0] + attribute \src "issuer_ls180.v:13569.3-13584.6" + wire width 4 $1\LDST_dec58_in2_sel[3:0] + attribute \src "issuer_ls180.v:13537.3-13552.6" + wire width 7 $1\LDST_dec58_internal_op[6:0] + attribute \src "issuer_ls180.v:13505.3-13520.6" + wire $1\LDST_dec58_is_32b[0:0] + attribute \src "issuer_ls180.v:13617.3-13632.6" + wire width 4 $1\LDST_dec58_ldst_len[3:0] + attribute \src "issuer_ls180.v:13649.3-13664.6" + wire width 2 $1\LDST_dec58_rc_sel[1:0] + attribute \src "issuer_ls180.v:13521.3-13536.6" + wire $1\LDST_dec58_sgn[0:0] + attribute \src "issuer_ls180.v:13489.3-13504.6" + wire $1\LDST_dec58_sgn_ext[0:0] + attribute \src "issuer_ls180.v:13633.3-13648.6" + wire width 2 $1\LDST_dec58_upd[1:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 10 \LDST_dec58_br + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 5 \LDST_dec58_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 6 \LDST_dec58_cr_out + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 12 output 1 \LDST_dec58_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 3 \LDST_dec58_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 output 4 \LDST_dec58_in2_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 7 output 2 \LDST_dec58_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 12 \LDST_dec58_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 output 7 \LDST_dec58_ldst_len + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 9 \LDST_dec58_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 13 \LDST_dec58_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 11 \LDST_dec58_sgn_ext + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 8 \LDST_dec58_upd + attribute \src "issuer_ls180.v:13276.7-13276.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + wire width 32 input 14 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:320" + wire width 2 \opcode_switch + attribute \src "issuer_ls180.v:13276.7-13276.20" + process $proc$issuer_ls180.v:13276$279 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "issuer_ls180.v:13457.3-13472.6" + process $proc$issuer_ls180.v:13457$266 + assign { } { } + assign { } { } + assign $0\LDST_dec58_function_unit[11:0] $1\LDST_dec58_function_unit[11:0] + attribute \src "issuer_ls180.v:13458.5-13458.29" + switch \initial + attribute \src "issuer_ls180.v:13458.9-13458.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\LDST_dec58_function_unit[11:0] 12'000000000100 + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\LDST_dec58_function_unit[11:0] 12'000000000100 + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\LDST_dec58_function_unit[11:0] 12'000000000100 + case + assign $1\LDST_dec58_function_unit[11:0] 12'000000000000 + end + sync always + update \LDST_dec58_function_unit $0\LDST_dec58_function_unit[11:0] + end + attribute \src "issuer_ls180.v:13473.3-13488.6" + process $proc$issuer_ls180.v:13473$267 + assign { } { } + assign { } { } + assign $0\LDST_dec58_br[0:0] $1\LDST_dec58_br[0:0] + attribute \src "issuer_ls180.v:13474.5-13474.29" + switch \initial + attribute \src "issuer_ls180.v:13474.9-13474.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\LDST_dec58_br[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\LDST_dec58_br[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\LDST_dec58_br[0:0] 1'0 + case + assign $1\LDST_dec58_br[0:0] 1'0 + end + sync always + update \LDST_dec58_br $0\LDST_dec58_br[0:0] + end + attribute \src "issuer_ls180.v:13489.3-13504.6" + process $proc$issuer_ls180.v:13489$268 + assign { } { } + assign { } { } + assign $0\LDST_dec58_sgn_ext[0:0] $1\LDST_dec58_sgn_ext[0:0] + attribute \src "issuer_ls180.v:13490.5-13490.29" + switch \initial + attribute \src "issuer_ls180.v:13490.9-13490.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\LDST_dec58_sgn_ext[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\LDST_dec58_sgn_ext[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\LDST_dec58_sgn_ext[0:0] 1'1 + case + assign $1\LDST_dec58_sgn_ext[0:0] 1'0 + end + sync always + update \LDST_dec58_sgn_ext $0\LDST_dec58_sgn_ext[0:0] + end + attribute \src "issuer_ls180.v:13505.3-13520.6" + process $proc$issuer_ls180.v:13505$269 + assign { } { } + assign { } { } + assign $0\LDST_dec58_is_32b[0:0] $1\LDST_dec58_is_32b[0:0] + attribute \src "issuer_ls180.v:13506.5-13506.29" + switch \initial + attribute \src "issuer_ls180.v:13506.9-13506.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\LDST_dec58_is_32b[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\LDST_dec58_is_32b[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\LDST_dec58_is_32b[0:0] 1'0 + case + assign $1\LDST_dec58_is_32b[0:0] 1'0 + end + sync always + update \LDST_dec58_is_32b $0\LDST_dec58_is_32b[0:0] + end + attribute \src "issuer_ls180.v:13521.3-13536.6" + process $proc$issuer_ls180.v:13521$270 + assign { } { } + assign { } { } + assign $0\LDST_dec58_sgn[0:0] $1\LDST_dec58_sgn[0:0] + attribute \src "issuer_ls180.v:13522.5-13522.29" + switch \initial + attribute \src "issuer_ls180.v:13522.9-13522.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\LDST_dec58_sgn[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\LDST_dec58_sgn[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\LDST_dec58_sgn[0:0] 1'0 + case + assign $1\LDST_dec58_sgn[0:0] 1'0 + end + sync always + update \LDST_dec58_sgn $0\LDST_dec58_sgn[0:0] + end + attribute \src "issuer_ls180.v:13537.3-13552.6" + process $proc$issuer_ls180.v:13537$271 + assign { } { } + assign { } { } + assign $0\LDST_dec58_internal_op[6:0] $1\LDST_dec58_internal_op[6:0] + attribute \src "issuer_ls180.v:13538.5-13538.29" + switch \initial + attribute \src "issuer_ls180.v:13538.9-13538.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\LDST_dec58_internal_op[6:0] 7'0100101 + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\LDST_dec58_internal_op[6:0] 7'0100101 + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\LDST_dec58_internal_op[6:0] 7'0100101 + case + assign $1\LDST_dec58_internal_op[6:0] 7'0000000 + end + sync always + update \LDST_dec58_internal_op $0\LDST_dec58_internal_op[6:0] + end + attribute \src "issuer_ls180.v:13553.3-13568.6" + process $proc$issuer_ls180.v:13553$272 + assign { } { } + assign { } { } + assign $0\LDST_dec58_in1_sel[2:0] $1\LDST_dec58_in1_sel[2:0] + attribute \src "issuer_ls180.v:13554.5-13554.29" + switch \initial + attribute \src "issuer_ls180.v:13554.9-13554.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\LDST_dec58_in1_sel[2:0] 3'010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\LDST_dec58_in1_sel[2:0] 3'010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\LDST_dec58_in1_sel[2:0] 3'010 + case + assign $1\LDST_dec58_in1_sel[2:0] 3'000 + end + sync always + update \LDST_dec58_in1_sel $0\LDST_dec58_in1_sel[2:0] + end + attribute \src "issuer_ls180.v:13569.3-13584.6" + process $proc$issuer_ls180.v:13569$273 + assign { } { } + assign { } { } + assign $0\LDST_dec58_in2_sel[3:0] $1\LDST_dec58_in2_sel[3:0] + attribute \src "issuer_ls180.v:13570.5-13570.29" + switch \initial + attribute \src "issuer_ls180.v:13570.9-13570.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\LDST_dec58_in2_sel[3:0] 4'1000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\LDST_dec58_in2_sel[3:0] 4'1000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\LDST_dec58_in2_sel[3:0] 4'1000 + case + assign $1\LDST_dec58_in2_sel[3:0] 4'0000 + end + sync always + update \LDST_dec58_in2_sel $0\LDST_dec58_in2_sel[3:0] + end + attribute \src "issuer_ls180.v:13585.3-13600.6" + process $proc$issuer_ls180.v:13585$274 + assign { } { } + assign { } { } + assign $0\LDST_dec58_cr_in[2:0] $1\LDST_dec58_cr_in[2:0] + attribute \src "issuer_ls180.v:13586.5-13586.29" + switch \initial + attribute \src "issuer_ls180.v:13586.9-13586.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\LDST_dec58_cr_in[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\LDST_dec58_cr_in[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\LDST_dec58_cr_in[2:0] 3'000 + case + assign $1\LDST_dec58_cr_in[2:0] 3'000 + end + sync always + update \LDST_dec58_cr_in $0\LDST_dec58_cr_in[2:0] + end + attribute \src "issuer_ls180.v:13601.3-13616.6" + process $proc$issuer_ls180.v:13601$275 + assign { } { } + assign { } { } + assign $0\LDST_dec58_cr_out[2:0] $1\LDST_dec58_cr_out[2:0] + attribute \src "issuer_ls180.v:13602.5-13602.29" + switch \initial + attribute \src "issuer_ls180.v:13602.9-13602.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\LDST_dec58_cr_out[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\LDST_dec58_cr_out[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\LDST_dec58_cr_out[2:0] 3'000 + case + assign $1\LDST_dec58_cr_out[2:0] 3'000 + end + sync always + update \LDST_dec58_cr_out $0\LDST_dec58_cr_out[2:0] + end + attribute \src "issuer_ls180.v:13617.3-13632.6" + process $proc$issuer_ls180.v:13617$276 + assign { } { } + assign { } { } + assign $0\LDST_dec58_ldst_len[3:0] $1\LDST_dec58_ldst_len[3:0] + attribute \src "issuer_ls180.v:13618.5-13618.29" + switch \initial + attribute \src "issuer_ls180.v:13618.9-13618.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\LDST_dec58_ldst_len[3:0] 4'1000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\LDST_dec58_ldst_len[3:0] 4'1000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\LDST_dec58_ldst_len[3:0] 4'0100 + case + assign $1\LDST_dec58_ldst_len[3:0] 4'0000 + end + sync always + update \LDST_dec58_ldst_len $0\LDST_dec58_ldst_len[3:0] + end + attribute \src "issuer_ls180.v:13633.3-13648.6" + process $proc$issuer_ls180.v:13633$277 + assign { } { } + assign { } { } + assign $0\LDST_dec58_upd[1:0] $1\LDST_dec58_upd[1:0] + attribute \src "issuer_ls180.v:13634.5-13634.29" + switch \initial + attribute \src "issuer_ls180.v:13634.9-13634.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\LDST_dec58_upd[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\LDST_dec58_upd[1:0] 2'01 + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\LDST_dec58_upd[1:0] 2'00 + case + assign $1\LDST_dec58_upd[1:0] 2'00 + end + sync always + update \LDST_dec58_upd $0\LDST_dec58_upd[1:0] + end + attribute \src "issuer_ls180.v:13649.3-13664.6" + process $proc$issuer_ls180.v:13649$278 + assign { } { } + assign { } { } + assign $0\LDST_dec58_rc_sel[1:0] $1\LDST_dec58_rc_sel[1:0] + attribute \src "issuer_ls180.v:13650.5-13650.29" + switch \initial + attribute \src "issuer_ls180.v:13650.9-13650.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\LDST_dec58_rc_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\LDST_dec58_rc_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\LDST_dec58_rc_sel[1:0] 2'00 + case + assign $1\LDST_dec58_rc_sel[1:0] 2'00 + end + sync always + update \LDST_dec58_rc_sel $0\LDST_dec58_rc_sel[1:0] + end + connect \opcode_switch \opcode_in [1:0] +end +attribute \src "issuer_ls180.v:13670.1-14022.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.dec_LDST.dec.LDST_dec62" +attribute \generator "nMigen" +module \LDST_dec62 + attribute \src "issuer_ls180.v:13865.3-13877.6" + wire $0\LDST_dec62_br[0:0] + attribute \src "issuer_ls180.v:13956.3-13968.6" + wire width 3 $0\LDST_dec62_cr_in[2:0] + attribute \src "issuer_ls180.v:13969.3-13981.6" + wire width 3 $0\LDST_dec62_cr_out[2:0] + attribute \src "issuer_ls180.v:13852.3-13864.6" + wire width 12 $0\LDST_dec62_function_unit[11:0] + attribute \src "issuer_ls180.v:13930.3-13942.6" + wire width 3 $0\LDST_dec62_in1_sel[2:0] + attribute \src "issuer_ls180.v:13943.3-13955.6" + wire width 4 $0\LDST_dec62_in2_sel[3:0] + attribute \src "issuer_ls180.v:13917.3-13929.6" + wire width 7 $0\LDST_dec62_internal_op[6:0] + attribute \src "issuer_ls180.v:13891.3-13903.6" + wire $0\LDST_dec62_is_32b[0:0] + attribute \src "issuer_ls180.v:13982.3-13994.6" + wire width 4 $0\LDST_dec62_ldst_len[3:0] + attribute \src "issuer_ls180.v:14008.3-14020.6" + wire width 2 $0\LDST_dec62_rc_sel[1:0] + attribute \src "issuer_ls180.v:13904.3-13916.6" + wire $0\LDST_dec62_sgn[0:0] + attribute \src "issuer_ls180.v:13878.3-13890.6" + wire $0\LDST_dec62_sgn_ext[0:0] + attribute \src "issuer_ls180.v:13995.3-14007.6" + wire width 2 $0\LDST_dec62_upd[1:0] + attribute \src "issuer_ls180.v:13671.7-13671.20" + wire $0\initial[0:0] + attribute \src "issuer_ls180.v:13865.3-13877.6" + wire $1\LDST_dec62_br[0:0] + attribute \src "issuer_ls180.v:13956.3-13968.6" + wire width 3 $1\LDST_dec62_cr_in[2:0] + attribute \src "issuer_ls180.v:13969.3-13981.6" + wire width 3 $1\LDST_dec62_cr_out[2:0] + attribute \src "issuer_ls180.v:13852.3-13864.6" + wire width 12 $1\LDST_dec62_function_unit[11:0] + attribute \src "issuer_ls180.v:13930.3-13942.6" + wire width 3 $1\LDST_dec62_in1_sel[2:0] + attribute \src "issuer_ls180.v:13943.3-13955.6" + wire width 4 $1\LDST_dec62_in2_sel[3:0] + attribute \src "issuer_ls180.v:13917.3-13929.6" + wire width 7 $1\LDST_dec62_internal_op[6:0] + attribute \src "issuer_ls180.v:13891.3-13903.6" + wire $1\LDST_dec62_is_32b[0:0] + attribute \src "issuer_ls180.v:13982.3-13994.6" + wire width 4 $1\LDST_dec62_ldst_len[3:0] + attribute \src "issuer_ls180.v:14008.3-14020.6" + wire width 2 $1\LDST_dec62_rc_sel[1:0] + attribute \src "issuer_ls180.v:13904.3-13916.6" + wire $1\LDST_dec62_sgn[0:0] + attribute \src "issuer_ls180.v:13878.3-13890.6" + wire $1\LDST_dec62_sgn_ext[0:0] + attribute \src "issuer_ls180.v:13995.3-14007.6" + wire width 2 $1\LDST_dec62_upd[1:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 10 \LDST_dec62_br + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 5 \LDST_dec62_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 6 \LDST_dec62_cr_out + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 12 output 1 \LDST_dec62_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 3 \LDST_dec62_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 output 4 \LDST_dec62_in2_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 7 output 2 \LDST_dec62_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 12 \LDST_dec62_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 output 7 \LDST_dec62_ldst_len + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 9 \LDST_dec62_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 13 \LDST_dec62_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 11 \LDST_dec62_sgn_ext + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 8 \LDST_dec62_upd + attribute \src "issuer_ls180.v:13671.7-13671.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + wire width 32 input 14 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:320" + wire width 2 \opcode_switch + attribute \src "issuer_ls180.v:13671.7-13671.20" + process $proc$issuer_ls180.v:13671$293 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "issuer_ls180.v:13852.3-13864.6" + process $proc$issuer_ls180.v:13852$280 + assign { } { } + assign { } { } + assign $0\LDST_dec62_function_unit[11:0] $1\LDST_dec62_function_unit[11:0] + attribute \src "issuer_ls180.v:13853.5-13853.29" + switch \initial + attribute \src "issuer_ls180.v:13853.9-13853.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\LDST_dec62_function_unit[11:0] 12'000000000100 + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\LDST_dec62_function_unit[11:0] 12'000000000100 + case + assign $1\LDST_dec62_function_unit[11:0] 12'000000000000 + end + sync always + update \LDST_dec62_function_unit $0\LDST_dec62_function_unit[11:0] + end + attribute \src "issuer_ls180.v:13865.3-13877.6" + process $proc$issuer_ls180.v:13865$281 + assign { } { } + assign { } { } + assign $0\LDST_dec62_br[0:0] $1\LDST_dec62_br[0:0] + attribute \src "issuer_ls180.v:13866.5-13866.29" + switch \initial + attribute \src "issuer_ls180.v:13866.9-13866.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\LDST_dec62_br[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\LDST_dec62_br[0:0] 1'0 + case + assign $1\LDST_dec62_br[0:0] 1'0 + end + sync always + update \LDST_dec62_br $0\LDST_dec62_br[0:0] + end + attribute \src "issuer_ls180.v:13878.3-13890.6" + process $proc$issuer_ls180.v:13878$282 + assign { } { } + assign { } { } + assign $0\LDST_dec62_sgn_ext[0:0] $1\LDST_dec62_sgn_ext[0:0] + attribute \src "issuer_ls180.v:13879.5-13879.29" + switch \initial + attribute \src "issuer_ls180.v:13879.9-13879.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\LDST_dec62_sgn_ext[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\LDST_dec62_sgn_ext[0:0] 1'0 + case + assign $1\LDST_dec62_sgn_ext[0:0] 1'0 + end + sync always + update \LDST_dec62_sgn_ext $0\LDST_dec62_sgn_ext[0:0] + end + attribute \src "issuer_ls180.v:13891.3-13903.6" + process $proc$issuer_ls180.v:13891$283 + assign { } { } + assign { } { } + assign $0\LDST_dec62_is_32b[0:0] $1\LDST_dec62_is_32b[0:0] + attribute \src "issuer_ls180.v:13892.5-13892.29" + switch \initial + attribute \src "issuer_ls180.v:13892.9-13892.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\LDST_dec62_is_32b[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\LDST_dec62_is_32b[0:0] 1'0 + case + assign $1\LDST_dec62_is_32b[0:0] 1'0 + end + sync always + update \LDST_dec62_is_32b $0\LDST_dec62_is_32b[0:0] + end + attribute \src "issuer_ls180.v:13904.3-13916.6" + process $proc$issuer_ls180.v:13904$284 + assign { } { } + assign { } { } + assign $0\LDST_dec62_sgn[0:0] $1\LDST_dec62_sgn[0:0] + attribute \src "issuer_ls180.v:13905.5-13905.29" + switch \initial + attribute \src "issuer_ls180.v:13905.9-13905.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\LDST_dec62_sgn[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\LDST_dec62_sgn[0:0] 1'0 + case + assign $1\LDST_dec62_sgn[0:0] 1'0 + end + sync always + update \LDST_dec62_sgn $0\LDST_dec62_sgn[0:0] + end + attribute \src "issuer_ls180.v:13917.3-13929.6" + process $proc$issuer_ls180.v:13917$285 + assign { } { } + assign { } { } + assign $0\LDST_dec62_internal_op[6:0] $1\LDST_dec62_internal_op[6:0] + attribute \src "issuer_ls180.v:13918.5-13918.29" + switch \initial + attribute \src "issuer_ls180.v:13918.9-13918.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\LDST_dec62_internal_op[6:0] 7'0100110 + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\LDST_dec62_internal_op[6:0] 7'0100110 + case + assign $1\LDST_dec62_internal_op[6:0] 7'0000000 + end + sync always + update \LDST_dec62_internal_op $0\LDST_dec62_internal_op[6:0] + end + attribute \src "issuer_ls180.v:13930.3-13942.6" + process $proc$issuer_ls180.v:13930$286 + assign { } { } + assign { } { } + assign $0\LDST_dec62_in1_sel[2:0] $1\LDST_dec62_in1_sel[2:0] + attribute \src "issuer_ls180.v:13931.5-13931.29" + switch \initial + attribute \src "issuer_ls180.v:13931.9-13931.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\LDST_dec62_in1_sel[2:0] 3'010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\LDST_dec62_in1_sel[2:0] 3'010 + case + assign $1\LDST_dec62_in1_sel[2:0] 3'000 + end + sync always + update \LDST_dec62_in1_sel $0\LDST_dec62_in1_sel[2:0] + end + attribute \src "issuer_ls180.v:13943.3-13955.6" + process $proc$issuer_ls180.v:13943$287 + assign { } { } + assign { } { } + assign $0\LDST_dec62_in2_sel[3:0] $1\LDST_dec62_in2_sel[3:0] + attribute \src "issuer_ls180.v:13944.5-13944.29" + switch \initial + attribute \src "issuer_ls180.v:13944.9-13944.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\LDST_dec62_in2_sel[3:0] 4'1000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\LDST_dec62_in2_sel[3:0] 4'1000 + case + assign $1\LDST_dec62_in2_sel[3:0] 4'0000 + end + sync always + update \LDST_dec62_in2_sel $0\LDST_dec62_in2_sel[3:0] + end + attribute \src "issuer_ls180.v:13956.3-13968.6" + process $proc$issuer_ls180.v:13956$288 + assign { } { } + assign { } { } + assign $0\LDST_dec62_cr_in[2:0] $1\LDST_dec62_cr_in[2:0] + attribute \src "issuer_ls180.v:13957.5-13957.29" + switch \initial + attribute \src "issuer_ls180.v:13957.9-13957.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\LDST_dec62_cr_in[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\LDST_dec62_cr_in[2:0] 3'000 + case + assign $1\LDST_dec62_cr_in[2:0] 3'000 + end + sync always + update \LDST_dec62_cr_in $0\LDST_dec62_cr_in[2:0] + end + attribute \src "issuer_ls180.v:13969.3-13981.6" + process $proc$issuer_ls180.v:13969$289 + assign { } { } + assign { } { } + assign $0\LDST_dec62_cr_out[2:0] $1\LDST_dec62_cr_out[2:0] + attribute \src "issuer_ls180.v:13970.5-13970.29" + switch \initial + attribute \src "issuer_ls180.v:13970.9-13970.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\LDST_dec62_cr_out[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\LDST_dec62_cr_out[2:0] 3'000 + case + assign $1\LDST_dec62_cr_out[2:0] 3'000 + end + sync always + update \LDST_dec62_cr_out $0\LDST_dec62_cr_out[2:0] + end + attribute \src "issuer_ls180.v:13982.3-13994.6" + process $proc$issuer_ls180.v:13982$290 + assign { } { } + assign { } { } + assign $0\LDST_dec62_ldst_len[3:0] $1\LDST_dec62_ldst_len[3:0] + attribute \src "issuer_ls180.v:13983.5-13983.29" + switch \initial + attribute \src "issuer_ls180.v:13983.9-13983.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\LDST_dec62_ldst_len[3:0] 4'1000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\LDST_dec62_ldst_len[3:0] 4'1000 + case + assign $1\LDST_dec62_ldst_len[3:0] 4'0000 + end + sync always + update \LDST_dec62_ldst_len $0\LDST_dec62_ldst_len[3:0] + end + attribute \src "issuer_ls180.v:13995.3-14007.6" + process $proc$issuer_ls180.v:13995$291 + assign { } { } + assign { } { } + assign $0\LDST_dec62_upd[1:0] $1\LDST_dec62_upd[1:0] + attribute \src "issuer_ls180.v:13996.5-13996.29" + switch \initial + attribute \src "issuer_ls180.v:13996.9-13996.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\LDST_dec62_upd[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\LDST_dec62_upd[1:0] 2'01 + case + assign $1\LDST_dec62_upd[1:0] 2'00 + end + sync always + update \LDST_dec62_upd $0\LDST_dec62_upd[1:0] + end + attribute \src "issuer_ls180.v:14008.3-14020.6" + process $proc$issuer_ls180.v:14008$292 + assign { } { } + assign { } { } + assign $0\LDST_dec62_rc_sel[1:0] $1\LDST_dec62_rc_sel[1:0] + attribute \src "issuer_ls180.v:14009.5-14009.29" + switch \initial + attribute \src "issuer_ls180.v:14009.9-14009.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\LDST_dec62_rc_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\LDST_dec62_rc_sel[1:0] 2'00 + case + assign $1\LDST_dec62_rc_sel[1:0] 2'00 + end + sync always + update \LDST_dec62_rc_sel $0\LDST_dec62_rc_sel[1:0] + end + connect \opcode_switch \opcode_in [1:0] +end +attribute \src "issuer_ls180.v:14026.1-14764.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.dec_LOGICAL.dec.LOGICAL_dec31" +attribute \generator "nMigen" +module \LOGICAL_dec31 + attribute \src "issuer_ls180.v:14734.3-14746.6" + wire width 3 $0\LOGICAL_dec31_cr_in[2:0] + attribute \src "issuer_ls180.v:14747.3-14759.6" + wire width 3 $0\LOGICAL_dec31_cr_out[2:0] + attribute \src "issuer_ls180.v:14604.3-14616.6" + wire width 2 $0\LOGICAL_dec31_cry_in[1:0] + attribute \src "issuer_ls180.v:14643.3-14655.6" + wire $0\LOGICAL_dec31_cry_out[0:0] + attribute \src "issuer_ls180.v:14682.3-14694.6" + wire width 12 $0\LOGICAL_dec31_function_unit[11:0] + attribute \src "issuer_ls180.v:14708.3-14720.6" + wire width 3 $0\LOGICAL_dec31_in1_sel[2:0] + attribute \src "issuer_ls180.v:14721.3-14733.6" + wire width 4 $0\LOGICAL_dec31_in2_sel[3:0] + attribute \src "issuer_ls180.v:14695.3-14707.6" + wire width 7 $0\LOGICAL_dec31_internal_op[6:0] + attribute \src "issuer_ls180.v:14617.3-14629.6" + wire $0\LOGICAL_dec31_inv_a[0:0] + attribute \src "issuer_ls180.v:14630.3-14642.6" + wire $0\LOGICAL_dec31_inv_out[0:0] + attribute \src "issuer_ls180.v:14656.3-14668.6" + wire $0\LOGICAL_dec31_is_32b[0:0] + attribute \src "issuer_ls180.v:14578.3-14590.6" + wire width 4 $0\LOGICAL_dec31_ldst_len[3:0] + attribute \src "issuer_ls180.v:14591.3-14603.6" + wire width 2 $0\LOGICAL_dec31_rc_sel[1:0] + attribute \src "issuer_ls180.v:14669.3-14681.6" + wire $0\LOGICAL_dec31_sgn[0:0] + attribute \src "issuer_ls180.v:14027.7-14027.20" + wire $0\initial[0:0] + attribute \src "issuer_ls180.v:14734.3-14746.6" + wire width 3 $1\LOGICAL_dec31_cr_in[2:0] + attribute \src "issuer_ls180.v:14747.3-14759.6" + wire width 3 $1\LOGICAL_dec31_cr_out[2:0] + attribute \src "issuer_ls180.v:14604.3-14616.6" + wire width 2 $1\LOGICAL_dec31_cry_in[1:0] + attribute \src "issuer_ls180.v:14643.3-14655.6" + wire $1\LOGICAL_dec31_cry_out[0:0] + attribute \src "issuer_ls180.v:14682.3-14694.6" + wire width 12 $1\LOGICAL_dec31_function_unit[11:0] + attribute \src "issuer_ls180.v:14708.3-14720.6" + wire width 3 $1\LOGICAL_dec31_in1_sel[2:0] + attribute \src "issuer_ls180.v:14721.3-14733.6" + wire width 4 $1\LOGICAL_dec31_in2_sel[3:0] + attribute \src "issuer_ls180.v:14695.3-14707.6" + wire width 7 $1\LOGICAL_dec31_internal_op[6:0] + attribute \src "issuer_ls180.v:14617.3-14629.6" + wire $1\LOGICAL_dec31_inv_a[0:0] + attribute \src "issuer_ls180.v:14630.3-14642.6" + wire $1\LOGICAL_dec31_inv_out[0:0] + attribute \src "issuer_ls180.v:14656.3-14668.6" + wire $1\LOGICAL_dec31_is_32b[0:0] + attribute \src "issuer_ls180.v:14578.3-14590.6" + wire width 4 $1\LOGICAL_dec31_ldst_len[3:0] + attribute \src "issuer_ls180.v:14591.3-14603.6" + wire width 2 $1\LOGICAL_dec31_rc_sel[1:0] + attribute \src "issuer_ls180.v:14669.3-14681.6" + wire $1\LOGICAL_dec31_sgn[0:0] + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 5 \LOGICAL_dec31_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 6 \LOGICAL_dec31_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 9 \LOGICAL_dec31_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 12 \LOGICAL_dec31_cry_out + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 \LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 \LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_cry_out + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 12 \LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 \LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 \LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_in2_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 7 \LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 \LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_ldst_len + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + wire width 32 \LOGICAL_dec31_dec_sub26_opcode_in + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 \LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 \LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_cry_out + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 12 \LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 \LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 \LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_in2_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 7 \LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 \LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_ldst_len + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + wire width 32 \LOGICAL_dec31_dec_sub28_opcode_in + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 12 output 1 \LOGICAL_dec31_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 3 \LOGICAL_dec31_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 output 4 \LOGICAL_dec31_in2_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 7 output 2 \LOGICAL_dec31_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 10 \LOGICAL_dec31_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 11 \LOGICAL_dec31_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 13 \LOGICAL_dec31_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 output 7 \LOGICAL_dec31_ldst_len + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 8 \LOGICAL_dec31_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 14 \LOGICAL_dec31_sgn + attribute \src "issuer_ls180.v:14027.7-14027.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:326" + wire width 5 \opc_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + wire width 32 input 15 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:320" + wire width 10 \opcode_switch + attribute \module_not_derived 1 + attribute \src "issuer_ls180.v:14544.27-14560.4" + cell \LOGICAL_dec31_dec_sub26 \LOGICAL_dec31_dec_sub26 + connect \LOGICAL_dec31_dec_sub26_cr_in \LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_cr_in + connect \LOGICAL_dec31_dec_sub26_cr_out \LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_cr_out + connect \LOGICAL_dec31_dec_sub26_cry_in \LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_cry_in + connect \LOGICAL_dec31_dec_sub26_cry_out \LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_cry_out + connect \LOGICAL_dec31_dec_sub26_function_unit \LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_function_unit + connect \LOGICAL_dec31_dec_sub26_in1_sel \LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_in1_sel + connect \LOGICAL_dec31_dec_sub26_in2_sel \LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_in2_sel + connect \LOGICAL_dec31_dec_sub26_internal_op \LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_internal_op + connect \LOGICAL_dec31_dec_sub26_inv_a \LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_inv_a + connect \LOGICAL_dec31_dec_sub26_inv_out \LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_inv_out + connect \LOGICAL_dec31_dec_sub26_is_32b \LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_is_32b + connect \LOGICAL_dec31_dec_sub26_ldst_len \LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_ldst_len + connect \LOGICAL_dec31_dec_sub26_rc_sel \LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_rc_sel + connect \LOGICAL_dec31_dec_sub26_sgn \LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_sgn + connect \opcode_in \LOGICAL_dec31_dec_sub26_opcode_in + end + attribute \module_not_derived 1 + attribute \src "issuer_ls180.v:14561.27-14577.4" + cell \LOGICAL_dec31_dec_sub28 \LOGICAL_dec31_dec_sub28 + connect \LOGICAL_dec31_dec_sub28_cr_in \LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_cr_in + connect \LOGICAL_dec31_dec_sub28_cr_out \LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_cr_out + connect \LOGICAL_dec31_dec_sub28_cry_in \LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_cry_in + connect \LOGICAL_dec31_dec_sub28_cry_out \LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_cry_out + connect \LOGICAL_dec31_dec_sub28_function_unit \LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_function_unit + connect \LOGICAL_dec31_dec_sub28_in1_sel \LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_in1_sel + connect \LOGICAL_dec31_dec_sub28_in2_sel \LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_in2_sel + connect \LOGICAL_dec31_dec_sub28_internal_op \LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_internal_op + connect \LOGICAL_dec31_dec_sub28_inv_a \LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_inv_a + connect \LOGICAL_dec31_dec_sub28_inv_out \LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_inv_out + connect \LOGICAL_dec31_dec_sub28_is_32b \LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_is_32b + connect \LOGICAL_dec31_dec_sub28_ldst_len \LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_ldst_len + connect \LOGICAL_dec31_dec_sub28_rc_sel \LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_rc_sel + connect \LOGICAL_dec31_dec_sub28_sgn \LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_sgn + connect \opcode_in \LOGICAL_dec31_dec_sub28_opcode_in + end + attribute \src "issuer_ls180.v:14027.7-14027.20" + process $proc$issuer_ls180.v:14027$308 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "issuer_ls180.v:14578.3-14590.6" + process $proc$issuer_ls180.v:14578$294 + assign { } { } + assign { } { } + assign $0\LOGICAL_dec31_ldst_len[3:0] $1\LOGICAL_dec31_ldst_len[3:0] + attribute \src "issuer_ls180.v:14579.5-14579.29" + switch \initial + attribute \src "issuer_ls180.v:14579.9-14579.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opc_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\LOGICAL_dec31_ldst_len[3:0] \LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_ldst_len + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\LOGICAL_dec31_ldst_len[3:0] \LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_ldst_len + case + assign $1\LOGICAL_dec31_ldst_len[3:0] 4'0000 + end + sync always + update \LOGICAL_dec31_ldst_len $0\LOGICAL_dec31_ldst_len[3:0] + end + attribute \src "issuer_ls180.v:14591.3-14603.6" + process $proc$issuer_ls180.v:14591$295 + assign { } { } + assign { } { } + assign $0\LOGICAL_dec31_rc_sel[1:0] $1\LOGICAL_dec31_rc_sel[1:0] + attribute \src "issuer_ls180.v:14592.5-14592.29" + switch \initial + attribute \src "issuer_ls180.v:14592.9-14592.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opc_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\LOGICAL_dec31_rc_sel[1:0] \LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_rc_sel + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\LOGICAL_dec31_rc_sel[1:0] \LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_rc_sel + case + assign $1\LOGICAL_dec31_rc_sel[1:0] 2'00 + end + sync always + update \LOGICAL_dec31_rc_sel $0\LOGICAL_dec31_rc_sel[1:0] + end + attribute \src "issuer_ls180.v:14604.3-14616.6" + process $proc$issuer_ls180.v:14604$296 + assign { } { } + assign { } { } + assign $0\LOGICAL_dec31_cry_in[1:0] $1\LOGICAL_dec31_cry_in[1:0] + attribute \src "issuer_ls180.v:14605.5-14605.29" + switch \initial + attribute \src "issuer_ls180.v:14605.9-14605.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opc_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\LOGICAL_dec31_cry_in[1:0] \LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_cry_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\LOGICAL_dec31_cry_in[1:0] \LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_cry_in + case + assign $1\LOGICAL_dec31_cry_in[1:0] 2'00 + end + sync always + update \LOGICAL_dec31_cry_in $0\LOGICAL_dec31_cry_in[1:0] + end + attribute \src "issuer_ls180.v:14617.3-14629.6" + process $proc$issuer_ls180.v:14617$297 + assign { } { } + assign { } { } + assign $0\LOGICAL_dec31_inv_a[0:0] $1\LOGICAL_dec31_inv_a[0:0] + attribute \src "issuer_ls180.v:14618.5-14618.29" + switch \initial + attribute \src "issuer_ls180.v:14618.9-14618.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opc_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\LOGICAL_dec31_inv_a[0:0] \LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_inv_a + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\LOGICAL_dec31_inv_a[0:0] \LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_inv_a + case + assign $1\LOGICAL_dec31_inv_a[0:0] 1'0 + end + sync always + update \LOGICAL_dec31_inv_a $0\LOGICAL_dec31_inv_a[0:0] + end + attribute \src "issuer_ls180.v:14630.3-14642.6" + process $proc$issuer_ls180.v:14630$298 + assign { } { } + assign { } { } + assign $0\LOGICAL_dec31_inv_out[0:0] $1\LOGICAL_dec31_inv_out[0:0] + attribute \src "issuer_ls180.v:14631.5-14631.29" + switch \initial + attribute \src "issuer_ls180.v:14631.9-14631.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opc_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\LOGICAL_dec31_inv_out[0:0] \LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_inv_out + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\LOGICAL_dec31_inv_out[0:0] \LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_inv_out + case + assign $1\LOGICAL_dec31_inv_out[0:0] 1'0 + end + sync always + update \LOGICAL_dec31_inv_out $0\LOGICAL_dec31_inv_out[0:0] + end + attribute \src "issuer_ls180.v:14643.3-14655.6" + process $proc$issuer_ls180.v:14643$299 + assign { } { } + assign { } { } + assign $0\LOGICAL_dec31_cry_out[0:0] $1\LOGICAL_dec31_cry_out[0:0] + attribute \src "issuer_ls180.v:14644.5-14644.29" + switch \initial + attribute \src "issuer_ls180.v:14644.9-14644.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opc_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\LOGICAL_dec31_cry_out[0:0] \LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_cry_out + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\LOGICAL_dec31_cry_out[0:0] \LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_cry_out + case + assign $1\LOGICAL_dec31_cry_out[0:0] 1'0 + end + sync always + update \LOGICAL_dec31_cry_out $0\LOGICAL_dec31_cry_out[0:0] + end + attribute \src "issuer_ls180.v:14656.3-14668.6" + process $proc$issuer_ls180.v:14656$300 + assign { } { } + assign { } { } + assign $0\LOGICAL_dec31_is_32b[0:0] $1\LOGICAL_dec31_is_32b[0:0] + attribute \src "issuer_ls180.v:14657.5-14657.29" + switch \initial + attribute \src "issuer_ls180.v:14657.9-14657.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opc_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\LOGICAL_dec31_is_32b[0:0] \LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_is_32b + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\LOGICAL_dec31_is_32b[0:0] \LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_is_32b + case + assign $1\LOGICAL_dec31_is_32b[0:0] 1'0 + end + sync always + update \LOGICAL_dec31_is_32b $0\LOGICAL_dec31_is_32b[0:0] + end + attribute \src "issuer_ls180.v:14669.3-14681.6" + process $proc$issuer_ls180.v:14669$301 + assign { } { } + assign { } { } + assign $0\LOGICAL_dec31_sgn[0:0] $1\LOGICAL_dec31_sgn[0:0] + attribute \src "issuer_ls180.v:14670.5-14670.29" + switch \initial + attribute \src "issuer_ls180.v:14670.9-14670.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opc_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\LOGICAL_dec31_sgn[0:0] \LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_sgn + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\LOGICAL_dec31_sgn[0:0] \LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_sgn + case + assign $1\LOGICAL_dec31_sgn[0:0] 1'0 + end + sync always + update \LOGICAL_dec31_sgn $0\LOGICAL_dec31_sgn[0:0] + end + attribute \src "issuer_ls180.v:14682.3-14694.6" + process $proc$issuer_ls180.v:14682$302 + assign { } { } + assign { } { } + assign $0\LOGICAL_dec31_function_unit[11:0] $1\LOGICAL_dec31_function_unit[11:0] + attribute \src "issuer_ls180.v:14683.5-14683.29" + switch \initial + attribute \src "issuer_ls180.v:14683.9-14683.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opc_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\LOGICAL_dec31_function_unit[11:0] \LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_function_unit + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\LOGICAL_dec31_function_unit[11:0] \LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_function_unit + case + assign $1\LOGICAL_dec31_function_unit[11:0] 12'000000000000 + end + sync always + update \LOGICAL_dec31_function_unit $0\LOGICAL_dec31_function_unit[11:0] + end + attribute \src "issuer_ls180.v:14695.3-14707.6" + process $proc$issuer_ls180.v:14695$303 + assign { } { } + assign { } { } + assign $0\LOGICAL_dec31_internal_op[6:0] $1\LOGICAL_dec31_internal_op[6:0] + attribute \src "issuer_ls180.v:14696.5-14696.29" + switch \initial + attribute \src "issuer_ls180.v:14696.9-14696.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opc_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\LOGICAL_dec31_internal_op[6:0] \LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_internal_op + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\LOGICAL_dec31_internal_op[6:0] \LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_internal_op + case + assign $1\LOGICAL_dec31_internal_op[6:0] 7'0000000 + end + sync always + update \LOGICAL_dec31_internal_op $0\LOGICAL_dec31_internal_op[6:0] + end + attribute \src "issuer_ls180.v:14708.3-14720.6" + process $proc$issuer_ls180.v:14708$304 + assign { } { } + assign { } { } + assign $0\LOGICAL_dec31_in1_sel[2:0] $1\LOGICAL_dec31_in1_sel[2:0] + attribute \src "issuer_ls180.v:14709.5-14709.29" + switch \initial + attribute \src "issuer_ls180.v:14709.9-14709.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opc_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\LOGICAL_dec31_in1_sel[2:0] \LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_in1_sel + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\LOGICAL_dec31_in1_sel[2:0] \LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_in1_sel + case + assign $1\LOGICAL_dec31_in1_sel[2:0] 3'000 + end + sync always + update \LOGICAL_dec31_in1_sel $0\LOGICAL_dec31_in1_sel[2:0] + end + attribute \src "issuer_ls180.v:14721.3-14733.6" + process $proc$issuer_ls180.v:14721$305 + assign { } { } + assign { } { } + assign $0\LOGICAL_dec31_in2_sel[3:0] $1\LOGICAL_dec31_in2_sel[3:0] + attribute \src "issuer_ls180.v:14722.5-14722.29" + switch \initial + attribute \src "issuer_ls180.v:14722.9-14722.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opc_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\LOGICAL_dec31_in2_sel[3:0] \LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_in2_sel + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\LOGICAL_dec31_in2_sel[3:0] \LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_in2_sel + case + assign $1\LOGICAL_dec31_in2_sel[3:0] 4'0000 + end + sync always + update \LOGICAL_dec31_in2_sel $0\LOGICAL_dec31_in2_sel[3:0] + end + attribute \src "issuer_ls180.v:14734.3-14746.6" + process $proc$issuer_ls180.v:14734$306 + assign { } { } + assign { } { } + assign $0\LOGICAL_dec31_cr_in[2:0] $1\LOGICAL_dec31_cr_in[2:0] + attribute \src "issuer_ls180.v:14735.5-14735.29" + switch \initial + attribute \src "issuer_ls180.v:14735.9-14735.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opc_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\LOGICAL_dec31_cr_in[2:0] \LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_cr_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\LOGICAL_dec31_cr_in[2:0] \LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_cr_in + case + assign $1\LOGICAL_dec31_cr_in[2:0] 3'000 + end + sync always + update \LOGICAL_dec31_cr_in $0\LOGICAL_dec31_cr_in[2:0] + end + attribute \src "issuer_ls180.v:14747.3-14759.6" + process $proc$issuer_ls180.v:14747$307 + assign { } { } + assign { } { } + assign $0\LOGICAL_dec31_cr_out[2:0] $1\LOGICAL_dec31_cr_out[2:0] + attribute \src "issuer_ls180.v:14748.5-14748.29" + switch \initial + attribute \src "issuer_ls180.v:14748.9-14748.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opc_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\LOGICAL_dec31_cr_out[2:0] \LOGICAL_dec31_dec_sub28_LOGICAL_dec31_dec_sub28_cr_out + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\LOGICAL_dec31_cr_out[2:0] \LOGICAL_dec31_dec_sub26_LOGICAL_dec31_dec_sub26_cr_out + case + assign $1\LOGICAL_dec31_cr_out[2:0] 3'000 + end + sync always + update \LOGICAL_dec31_cr_out $0\LOGICAL_dec31_cr_out[2:0] + end + connect \LOGICAL_dec31_dec_sub26_opcode_in \opcode_in + connect \LOGICAL_dec31_dec_sub28_opcode_in \opcode_in + connect \opc_in \opcode_switch [4:0] + connect \opcode_switch \opcode_in [10:1] +end +attribute \src "issuer_ls180.v:14768.1-15429.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.dec_LOGICAL.dec.LOGICAL_dec31.LOGICAL_dec31_dec_sub26" +attribute \generator "nMigen" +module \LOGICAL_dec31_dec_sub26 + attribute \src "issuer_ls180.v:15258.3-15291.6" + wire width 3 $0\LOGICAL_dec31_dec_sub26_cr_in[2:0] + attribute \src "issuer_ls180.v:15292.3-15325.6" + wire width 3 $0\LOGICAL_dec31_dec_sub26_cr_out[2:0] + attribute \src "issuer_ls180.v:15394.3-15427.6" + wire width 2 $0\LOGICAL_dec31_dec_sub26_cry_in[1:0] + attribute \src "issuer_ls180.v:15054.3-15087.6" + wire $0\LOGICAL_dec31_dec_sub26_cry_out[0:0] + attribute \src "issuer_ls180.v:14952.3-14985.6" + wire width 12 $0\LOGICAL_dec31_dec_sub26_function_unit[11:0] + attribute \src "issuer_ls180.v:15190.3-15223.6" + wire width 3 $0\LOGICAL_dec31_dec_sub26_in1_sel[2:0] + attribute \src "issuer_ls180.v:15224.3-15257.6" + wire width 4 $0\LOGICAL_dec31_dec_sub26_in2_sel[3:0] + attribute \src "issuer_ls180.v:15156.3-15189.6" + wire width 7 $0\LOGICAL_dec31_dec_sub26_internal_op[6:0] + attribute \src "issuer_ls180.v:14986.3-15019.6" + wire $0\LOGICAL_dec31_dec_sub26_inv_a[0:0] + attribute \src "issuer_ls180.v:15020.3-15053.6" + wire $0\LOGICAL_dec31_dec_sub26_inv_out[0:0] + attribute \src "issuer_ls180.v:15088.3-15121.6" + wire $0\LOGICAL_dec31_dec_sub26_is_32b[0:0] + attribute \src "issuer_ls180.v:15326.3-15359.6" + wire width 4 $0\LOGICAL_dec31_dec_sub26_ldst_len[3:0] + attribute \src "issuer_ls180.v:15360.3-15393.6" + wire width 2 $0\LOGICAL_dec31_dec_sub26_rc_sel[1:0] + attribute \src "issuer_ls180.v:15122.3-15155.6" + wire $0\LOGICAL_dec31_dec_sub26_sgn[0:0] + attribute \src "issuer_ls180.v:14769.7-14769.20" + wire $0\initial[0:0] + attribute \src "issuer_ls180.v:15258.3-15291.6" + wire width 3 $1\LOGICAL_dec31_dec_sub26_cr_in[2:0] + attribute \src "issuer_ls180.v:15292.3-15325.6" + wire width 3 $1\LOGICAL_dec31_dec_sub26_cr_out[2:0] + attribute \src "issuer_ls180.v:15394.3-15427.6" + wire width 2 $1\LOGICAL_dec31_dec_sub26_cry_in[1:0] + attribute \src "issuer_ls180.v:15054.3-15087.6" + wire $1\LOGICAL_dec31_dec_sub26_cry_out[0:0] + attribute \src "issuer_ls180.v:14952.3-14985.6" + wire width 12 $1\LOGICAL_dec31_dec_sub26_function_unit[11:0] + attribute \src "issuer_ls180.v:15190.3-15223.6" + wire width 3 $1\LOGICAL_dec31_dec_sub26_in1_sel[2:0] + attribute \src "issuer_ls180.v:15224.3-15257.6" + wire width 4 $1\LOGICAL_dec31_dec_sub26_in2_sel[3:0] + attribute \src "issuer_ls180.v:15156.3-15189.6" + wire width 7 $1\LOGICAL_dec31_dec_sub26_internal_op[6:0] + attribute \src "issuer_ls180.v:14986.3-15019.6" + wire $1\LOGICAL_dec31_dec_sub26_inv_a[0:0] + attribute \src "issuer_ls180.v:15020.3-15053.6" + wire $1\LOGICAL_dec31_dec_sub26_inv_out[0:0] + attribute \src "issuer_ls180.v:15088.3-15121.6" + wire $1\LOGICAL_dec31_dec_sub26_is_32b[0:0] + attribute \src "issuer_ls180.v:15326.3-15359.6" + wire width 4 $1\LOGICAL_dec31_dec_sub26_ldst_len[3:0] + attribute \src "issuer_ls180.v:15360.3-15393.6" + wire width 2 $1\LOGICAL_dec31_dec_sub26_rc_sel[1:0] + attribute \src "issuer_ls180.v:15122.3-15155.6" + wire $1\LOGICAL_dec31_dec_sub26_sgn[0:0] + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 5 \LOGICAL_dec31_dec_sub26_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 6 \LOGICAL_dec31_dec_sub26_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 9 \LOGICAL_dec31_dec_sub26_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 12 \LOGICAL_dec31_dec_sub26_cry_out + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 12 output 1 \LOGICAL_dec31_dec_sub26_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 3 \LOGICAL_dec31_dec_sub26_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 output 4 \LOGICAL_dec31_dec_sub26_in2_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 7 output 2 \LOGICAL_dec31_dec_sub26_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 10 \LOGICAL_dec31_dec_sub26_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 11 \LOGICAL_dec31_dec_sub26_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 13 \LOGICAL_dec31_dec_sub26_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 output 7 \LOGICAL_dec31_dec_sub26_ldst_len + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 8 \LOGICAL_dec31_dec_sub26_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 14 \LOGICAL_dec31_dec_sub26_sgn + attribute \src "issuer_ls180.v:14769.7-14769.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + wire width 32 input 15 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:320" + wire width 5 \opcode_switch + attribute \src "issuer_ls180.v:14769.7-14769.20" + process $proc$issuer_ls180.v:14769$323 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "issuer_ls180.v:14952.3-14985.6" + process $proc$issuer_ls180.v:14952$309 + assign { } { } + assign { } { } + assign $0\LOGICAL_dec31_dec_sub26_function_unit[11:0] $1\LOGICAL_dec31_dec_sub26_function_unit[11:0] + attribute \src "issuer_ls180.v:14953.5-14953.29" + switch \initial + attribute \src "issuer_ls180.v:14953.9-14953.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_function_unit[11:0] 12'000000010000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_function_unit[11:0] 12'000000010000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_function_unit[11:0] 12'000000010000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_function_unit[11:0] 12'000000010000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_function_unit[11:0] 12'000000010000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_function_unit[11:0] 12'000000010000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_function_unit[11:0] 12'000000010000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_function_unit[11:0] 12'000000010000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_function_unit[11:0] 12'000000010000 + case + assign $1\LOGICAL_dec31_dec_sub26_function_unit[11:0] 12'000000000000 + end + sync always + update \LOGICAL_dec31_dec_sub26_function_unit $0\LOGICAL_dec31_dec_sub26_function_unit[11:0] + end + attribute \src "issuer_ls180.v:14986.3-15019.6" + process $proc$issuer_ls180.v:14986$310 + assign { } { } + assign { } { } + assign $0\LOGICAL_dec31_dec_sub26_inv_a[0:0] $1\LOGICAL_dec31_dec_sub26_inv_a[0:0] + attribute \src "issuer_ls180.v:14987.5-14987.29" + switch \initial + attribute \src "issuer_ls180.v:14987.9-14987.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_inv_a[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_inv_a[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_inv_a[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_inv_a[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_inv_a[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_inv_a[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_inv_a[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_inv_a[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_inv_a[0:0] 1'0 + case + assign $1\LOGICAL_dec31_dec_sub26_inv_a[0:0] 1'0 + end + sync always + update \LOGICAL_dec31_dec_sub26_inv_a $0\LOGICAL_dec31_dec_sub26_inv_a[0:0] + end + attribute \src "issuer_ls180.v:15020.3-15053.6" + process $proc$issuer_ls180.v:15020$311 + assign { } { } + assign { } { } + assign $0\LOGICAL_dec31_dec_sub26_inv_out[0:0] $1\LOGICAL_dec31_dec_sub26_inv_out[0:0] + attribute \src "issuer_ls180.v:15021.5-15021.29" + switch \initial + attribute \src "issuer_ls180.v:15021.9-15021.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_inv_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_inv_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_inv_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_inv_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_inv_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_inv_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_inv_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_inv_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_inv_out[0:0] 1'0 + case + assign $1\LOGICAL_dec31_dec_sub26_inv_out[0:0] 1'0 + end + sync always + update \LOGICAL_dec31_dec_sub26_inv_out $0\LOGICAL_dec31_dec_sub26_inv_out[0:0] + end + attribute \src "issuer_ls180.v:15054.3-15087.6" + process $proc$issuer_ls180.v:15054$312 + assign { } { } + assign { } { } + assign $0\LOGICAL_dec31_dec_sub26_cry_out[0:0] $1\LOGICAL_dec31_dec_sub26_cry_out[0:0] + attribute \src "issuer_ls180.v:15055.5-15055.29" + switch \initial + attribute \src "issuer_ls180.v:15055.9-15055.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_cry_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_cry_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_cry_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_cry_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_cry_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_cry_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_cry_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_cry_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_cry_out[0:0] 1'0 + case + assign $1\LOGICAL_dec31_dec_sub26_cry_out[0:0] 1'0 + end + sync always + update \LOGICAL_dec31_dec_sub26_cry_out $0\LOGICAL_dec31_dec_sub26_cry_out[0:0] + end + attribute \src "issuer_ls180.v:15088.3-15121.6" + process $proc$issuer_ls180.v:15088$313 + assign { } { } + assign { } { } + assign $0\LOGICAL_dec31_dec_sub26_is_32b[0:0] $1\LOGICAL_dec31_dec_sub26_is_32b[0:0] + attribute \src "issuer_ls180.v:15089.5-15089.29" + switch \initial + attribute \src "issuer_ls180.v:15089.9-15089.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_is_32b[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_is_32b[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_is_32b[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_is_32b[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_is_32b[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_is_32b[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_is_32b[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_is_32b[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_is_32b[0:0] 1'0 + case + assign $1\LOGICAL_dec31_dec_sub26_is_32b[0:0] 1'0 + end + sync always + update \LOGICAL_dec31_dec_sub26_is_32b $0\LOGICAL_dec31_dec_sub26_is_32b[0:0] + end + attribute \src "issuer_ls180.v:15122.3-15155.6" + process $proc$issuer_ls180.v:15122$314 + assign { } { } + assign { } { } + assign $0\LOGICAL_dec31_dec_sub26_sgn[0:0] $1\LOGICAL_dec31_dec_sub26_sgn[0:0] + attribute \src "issuer_ls180.v:15123.5-15123.29" + switch \initial + attribute \src "issuer_ls180.v:15123.9-15123.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_sgn[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_sgn[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_sgn[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_sgn[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_sgn[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_sgn[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_sgn[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_sgn[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_sgn[0:0] 1'0 + case + assign $1\LOGICAL_dec31_dec_sub26_sgn[0:0] 1'0 + end + sync always + update \LOGICAL_dec31_dec_sub26_sgn $0\LOGICAL_dec31_dec_sub26_sgn[0:0] + end + attribute \src "issuer_ls180.v:15156.3-15189.6" + process $proc$issuer_ls180.v:15156$315 + assign { } { } + assign { } { } + assign $0\LOGICAL_dec31_dec_sub26_internal_op[6:0] $1\LOGICAL_dec31_dec_sub26_internal_op[6:0] + attribute \src "issuer_ls180.v:15157.5-15157.29" + switch \initial + attribute \src "issuer_ls180.v:15157.9-15157.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_internal_op[6:0] 7'0001110 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_internal_op[6:0] 7'0001110 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_internal_op[6:0] 7'0001110 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_internal_op[6:0] 7'0001110 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_internal_op[6:0] 7'0110110 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_internal_op[6:0] 7'0110110 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_internal_op[6:0] 7'0110110 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_internal_op[6:0] 7'0110111 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_internal_op[6:0] 7'0110111 + case + assign $1\LOGICAL_dec31_dec_sub26_internal_op[6:0] 7'0000000 + end + sync always + update \LOGICAL_dec31_dec_sub26_internal_op $0\LOGICAL_dec31_dec_sub26_internal_op[6:0] + end + attribute \src "issuer_ls180.v:15190.3-15223.6" + process $proc$issuer_ls180.v:15190$316 + assign { } { } + assign { } { } + assign $0\LOGICAL_dec31_dec_sub26_in1_sel[2:0] $1\LOGICAL_dec31_dec_sub26_in1_sel[2:0] + attribute \src "issuer_ls180.v:15191.5-15191.29" + switch \initial + attribute \src "issuer_ls180.v:15191.9-15191.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_in1_sel[2:0] 3'100 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_in1_sel[2:0] 3'100 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_in1_sel[2:0] 3'100 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_in1_sel[2:0] 3'100 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_in1_sel[2:0] 3'100 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_in1_sel[2:0] 3'100 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_in1_sel[2:0] 3'100 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_in1_sel[2:0] 3'100 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_in1_sel[2:0] 3'100 + case + assign $1\LOGICAL_dec31_dec_sub26_in1_sel[2:0] 3'000 + end + sync always + update \LOGICAL_dec31_dec_sub26_in1_sel $0\LOGICAL_dec31_dec_sub26_in1_sel[2:0] + end + attribute \src "issuer_ls180.v:15224.3-15257.6" + process $proc$issuer_ls180.v:15224$317 + assign { } { } + assign { } { } + assign $0\LOGICAL_dec31_dec_sub26_in2_sel[3:0] $1\LOGICAL_dec31_dec_sub26_in2_sel[3:0] + attribute \src "issuer_ls180.v:15225.5-15225.29" + switch \initial + attribute \src "issuer_ls180.v:15225.9-15225.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_in2_sel[3:0] 4'0000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_in2_sel[3:0] 4'0000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_in2_sel[3:0] 4'0000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_in2_sel[3:0] 4'0000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_in2_sel[3:0] 4'0000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_in2_sel[3:0] 4'0000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_in2_sel[3:0] 4'0000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_in2_sel[3:0] 4'0000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_in2_sel[3:0] 4'0000 + case + assign $1\LOGICAL_dec31_dec_sub26_in2_sel[3:0] 4'0000 + end + sync always + update \LOGICAL_dec31_dec_sub26_in2_sel $0\LOGICAL_dec31_dec_sub26_in2_sel[3:0] + end + attribute \src "issuer_ls180.v:15258.3-15291.6" + process $proc$issuer_ls180.v:15258$318 + assign { } { } + assign { } { } + assign $0\LOGICAL_dec31_dec_sub26_cr_in[2:0] $1\LOGICAL_dec31_dec_sub26_cr_in[2:0] + attribute \src "issuer_ls180.v:15259.5-15259.29" + switch \initial + attribute \src "issuer_ls180.v:15259.9-15259.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_cr_in[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_cr_in[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_cr_in[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_cr_in[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_cr_in[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_cr_in[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_cr_in[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_cr_in[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_cr_in[2:0] 3'000 + case + assign $1\LOGICAL_dec31_dec_sub26_cr_in[2:0] 3'000 + end + sync always + update \LOGICAL_dec31_dec_sub26_cr_in $0\LOGICAL_dec31_dec_sub26_cr_in[2:0] + end + attribute \src "issuer_ls180.v:15292.3-15325.6" + process $proc$issuer_ls180.v:15292$319 + assign { } { } + assign { } { } + assign $0\LOGICAL_dec31_dec_sub26_cr_out[2:0] $1\LOGICAL_dec31_dec_sub26_cr_out[2:0] + attribute \src "issuer_ls180.v:15293.5-15293.29" + switch \initial + attribute \src "issuer_ls180.v:15293.9-15293.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_cr_out[2:0] 3'001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_cr_out[2:0] 3'001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_cr_out[2:0] 3'001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_cr_out[2:0] 3'001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_cr_out[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_cr_out[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_cr_out[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_cr_out[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_cr_out[2:0] 3'000 + case + assign $1\LOGICAL_dec31_dec_sub26_cr_out[2:0] 3'000 + end + sync always + update \LOGICAL_dec31_dec_sub26_cr_out $0\LOGICAL_dec31_dec_sub26_cr_out[2:0] + end + attribute \src "issuer_ls180.v:15326.3-15359.6" + process $proc$issuer_ls180.v:15326$320 + assign { } { } + assign { } { } + assign $0\LOGICAL_dec31_dec_sub26_ldst_len[3:0] $1\LOGICAL_dec31_dec_sub26_ldst_len[3:0] + attribute \src "issuer_ls180.v:15327.5-15327.29" + switch \initial + attribute \src "issuer_ls180.v:15327.9-15327.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_ldst_len[3:0] 4'0000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_ldst_len[3:0] 4'0000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_ldst_len[3:0] 4'0000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_ldst_len[3:0] 4'0000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_ldst_len[3:0] 4'0001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_ldst_len[3:0] 4'1000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_ldst_len[3:0] 4'0100 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_ldst_len[3:0] 4'1000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_ldst_len[3:0] 4'0100 + case + assign $1\LOGICAL_dec31_dec_sub26_ldst_len[3:0] 4'0000 + end + sync always + update \LOGICAL_dec31_dec_sub26_ldst_len $0\LOGICAL_dec31_dec_sub26_ldst_len[3:0] + end + attribute \src "issuer_ls180.v:15360.3-15393.6" + process $proc$issuer_ls180.v:15360$321 + assign { } { } + assign { } { } + assign $0\LOGICAL_dec31_dec_sub26_rc_sel[1:0] $1\LOGICAL_dec31_dec_sub26_rc_sel[1:0] + attribute \src "issuer_ls180.v:15361.5-15361.29" + switch \initial + attribute \src "issuer_ls180.v:15361.9-15361.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_rc_sel[1:0] 2'10 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_rc_sel[1:0] 2'10 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_rc_sel[1:0] 2'10 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_rc_sel[1:0] 2'10 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_rc_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_rc_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_rc_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_rc_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_rc_sel[1:0] 2'00 + case + assign $1\LOGICAL_dec31_dec_sub26_rc_sel[1:0] 2'00 + end + sync always + update \LOGICAL_dec31_dec_sub26_rc_sel $0\LOGICAL_dec31_dec_sub26_rc_sel[1:0] + end + attribute \src "issuer_ls180.v:15394.3-15427.6" + process $proc$issuer_ls180.v:15394$322 + assign { } { } + assign { } { } + assign $0\LOGICAL_dec31_dec_sub26_cry_in[1:0] $1\LOGICAL_dec31_dec_sub26_cry_in[1:0] + attribute \src "issuer_ls180.v:15395.5-15395.29" + switch \initial + attribute \src "issuer_ls180.v:15395.9-15395.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_cry_in[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_cry_in[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_cry_in[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_cry_in[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_cry_in[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_cry_in[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_cry_in[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_cry_in[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub26_cry_in[1:0] 2'00 + case + assign $1\LOGICAL_dec31_dec_sub26_cry_in[1:0] 2'00 + end + sync always + update \LOGICAL_dec31_dec_sub26_cry_in $0\LOGICAL_dec31_dec_sub26_cry_in[1:0] + end + connect \opcode_switch \opcode_in [10:6] +end +attribute \src "issuer_ls180.v:15433.1-16136.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.dec_LOGICAL.dec.LOGICAL_dec31.LOGICAL_dec31_dec_sub28" +attribute \generator "nMigen" +module \LOGICAL_dec31_dec_sub28 + attribute \src "issuer_ls180.v:15950.3-15986.6" + wire width 3 $0\LOGICAL_dec31_dec_sub28_cr_in[2:0] + attribute \src "issuer_ls180.v:15987.3-16023.6" + wire width 3 $0\LOGICAL_dec31_dec_sub28_cr_out[2:0] + attribute \src "issuer_ls180.v:16098.3-16134.6" + wire width 2 $0\LOGICAL_dec31_dec_sub28_cry_in[1:0] + attribute \src "issuer_ls180.v:15728.3-15764.6" + wire $0\LOGICAL_dec31_dec_sub28_cry_out[0:0] + attribute \src "issuer_ls180.v:15617.3-15653.6" + wire width 12 $0\LOGICAL_dec31_dec_sub28_function_unit[11:0] + attribute \src "issuer_ls180.v:15876.3-15912.6" + wire width 3 $0\LOGICAL_dec31_dec_sub28_in1_sel[2:0] + attribute \src "issuer_ls180.v:15913.3-15949.6" + wire width 4 $0\LOGICAL_dec31_dec_sub28_in2_sel[3:0] + attribute \src "issuer_ls180.v:15839.3-15875.6" + wire width 7 $0\LOGICAL_dec31_dec_sub28_internal_op[6:0] + attribute \src "issuer_ls180.v:15654.3-15690.6" + wire $0\LOGICAL_dec31_dec_sub28_inv_a[0:0] + attribute \src "issuer_ls180.v:15691.3-15727.6" + wire $0\LOGICAL_dec31_dec_sub28_inv_out[0:0] + attribute \src "issuer_ls180.v:15765.3-15801.6" + wire $0\LOGICAL_dec31_dec_sub28_is_32b[0:0] + attribute \src "issuer_ls180.v:16024.3-16060.6" + wire width 4 $0\LOGICAL_dec31_dec_sub28_ldst_len[3:0] + attribute \src "issuer_ls180.v:16061.3-16097.6" + wire width 2 $0\LOGICAL_dec31_dec_sub28_rc_sel[1:0] + attribute \src "issuer_ls180.v:15802.3-15838.6" + wire $0\LOGICAL_dec31_dec_sub28_sgn[0:0] + attribute \src "issuer_ls180.v:15434.7-15434.20" + wire $0\initial[0:0] + attribute \src "issuer_ls180.v:15950.3-15986.6" + wire width 3 $1\LOGICAL_dec31_dec_sub28_cr_in[2:0] + attribute \src "issuer_ls180.v:15987.3-16023.6" + wire width 3 $1\LOGICAL_dec31_dec_sub28_cr_out[2:0] + attribute \src "issuer_ls180.v:16098.3-16134.6" + wire width 2 $1\LOGICAL_dec31_dec_sub28_cry_in[1:0] + attribute \src "issuer_ls180.v:15728.3-15764.6" + wire $1\LOGICAL_dec31_dec_sub28_cry_out[0:0] + attribute \src "issuer_ls180.v:15617.3-15653.6" + wire width 12 $1\LOGICAL_dec31_dec_sub28_function_unit[11:0] + attribute \src "issuer_ls180.v:15876.3-15912.6" + wire width 3 $1\LOGICAL_dec31_dec_sub28_in1_sel[2:0] + attribute \src "issuer_ls180.v:15913.3-15949.6" + wire width 4 $1\LOGICAL_dec31_dec_sub28_in2_sel[3:0] + attribute \src "issuer_ls180.v:15839.3-15875.6" + wire width 7 $1\LOGICAL_dec31_dec_sub28_internal_op[6:0] + attribute \src "issuer_ls180.v:15654.3-15690.6" + wire $1\LOGICAL_dec31_dec_sub28_inv_a[0:0] + attribute \src "issuer_ls180.v:15691.3-15727.6" + wire $1\LOGICAL_dec31_dec_sub28_inv_out[0:0] + attribute \src "issuer_ls180.v:15765.3-15801.6" + wire $1\LOGICAL_dec31_dec_sub28_is_32b[0:0] + attribute \src "issuer_ls180.v:16024.3-16060.6" + wire width 4 $1\LOGICAL_dec31_dec_sub28_ldst_len[3:0] + attribute \src "issuer_ls180.v:16061.3-16097.6" + wire width 2 $1\LOGICAL_dec31_dec_sub28_rc_sel[1:0] + attribute \src "issuer_ls180.v:15802.3-15838.6" + wire $1\LOGICAL_dec31_dec_sub28_sgn[0:0] + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 5 \LOGICAL_dec31_dec_sub28_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 6 \LOGICAL_dec31_dec_sub28_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 9 \LOGICAL_dec31_dec_sub28_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 12 \LOGICAL_dec31_dec_sub28_cry_out + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 12 output 1 \LOGICAL_dec31_dec_sub28_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 3 \LOGICAL_dec31_dec_sub28_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 output 4 \LOGICAL_dec31_dec_sub28_in2_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 7 output 2 \LOGICAL_dec31_dec_sub28_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 10 \LOGICAL_dec31_dec_sub28_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 11 \LOGICAL_dec31_dec_sub28_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 13 \LOGICAL_dec31_dec_sub28_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 output 7 \LOGICAL_dec31_dec_sub28_ldst_len + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 8 \LOGICAL_dec31_dec_sub28_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 14 \LOGICAL_dec31_dec_sub28_sgn + attribute \src "issuer_ls180.v:15434.7-15434.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + wire width 32 input 15 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:320" + wire width 5 \opcode_switch + attribute \src "issuer_ls180.v:15434.7-15434.20" + process $proc$issuer_ls180.v:15434$338 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "issuer_ls180.v:15617.3-15653.6" + process $proc$issuer_ls180.v:15617$324 + assign { } { } + assign { } { } + assign $0\LOGICAL_dec31_dec_sub28_function_unit[11:0] $1\LOGICAL_dec31_dec_sub28_function_unit[11:0] + attribute \src "issuer_ls180.v:15618.5-15618.29" + switch \initial + attribute \src "issuer_ls180.v:15618.9-15618.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_function_unit[11:0] 12'000000010000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_function_unit[11:0] 12'000000010000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_function_unit[11:0] 12'000000010000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_function_unit[11:0] 12'000000010000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_function_unit[11:0] 12'000000010000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_function_unit[11:0] 12'000000010000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_function_unit[11:0] 12'000000010000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_function_unit[11:0] 12'000000010000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_function_unit[11:0] 12'000000010000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_function_unit[11:0] 12'000000010000 + case + assign $1\LOGICAL_dec31_dec_sub28_function_unit[11:0] 12'000000000000 + end + sync always + update \LOGICAL_dec31_dec_sub28_function_unit $0\LOGICAL_dec31_dec_sub28_function_unit[11:0] + end + attribute \src "issuer_ls180.v:15654.3-15690.6" + process $proc$issuer_ls180.v:15654$325 + assign { } { } + assign { } { } + assign $0\LOGICAL_dec31_dec_sub28_inv_a[0:0] $1\LOGICAL_dec31_dec_sub28_inv_a[0:0] + attribute \src "issuer_ls180.v:15655.5-15655.29" + switch \initial + attribute \src "issuer_ls180.v:15655.9-15655.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_inv_a[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_inv_a[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_inv_a[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_inv_a[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_inv_a[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_inv_a[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_inv_a[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_inv_a[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_inv_a[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_inv_a[0:0] 1'0 + case + assign $1\LOGICAL_dec31_dec_sub28_inv_a[0:0] 1'0 + end + sync always + update \LOGICAL_dec31_dec_sub28_inv_a $0\LOGICAL_dec31_dec_sub28_inv_a[0:0] + end + attribute \src "issuer_ls180.v:15691.3-15727.6" + process $proc$issuer_ls180.v:15691$326 + assign { } { } + assign { } { } + assign $0\LOGICAL_dec31_dec_sub28_inv_out[0:0] $1\LOGICAL_dec31_dec_sub28_inv_out[0:0] + attribute \src "issuer_ls180.v:15692.5-15692.29" + switch \initial + attribute \src "issuer_ls180.v:15692.9-15692.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_inv_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_inv_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_inv_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_inv_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_inv_out[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_inv_out[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_inv_out[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_inv_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_inv_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_inv_out[0:0] 1'0 + case + assign $1\LOGICAL_dec31_dec_sub28_inv_out[0:0] 1'0 + end + sync always + update \LOGICAL_dec31_dec_sub28_inv_out $0\LOGICAL_dec31_dec_sub28_inv_out[0:0] + end + attribute \src "issuer_ls180.v:15728.3-15764.6" + process $proc$issuer_ls180.v:15728$327 + assign { } { } + assign { } { } + assign $0\LOGICAL_dec31_dec_sub28_cry_out[0:0] $1\LOGICAL_dec31_dec_sub28_cry_out[0:0] + attribute \src "issuer_ls180.v:15729.5-15729.29" + switch \initial + attribute \src "issuer_ls180.v:15729.9-15729.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_cry_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_cry_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_cry_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_cry_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_cry_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_cry_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_cry_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_cry_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_cry_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_cry_out[0:0] 1'0 + case + assign $1\LOGICAL_dec31_dec_sub28_cry_out[0:0] 1'0 + end + sync always + update \LOGICAL_dec31_dec_sub28_cry_out $0\LOGICAL_dec31_dec_sub28_cry_out[0:0] + end + attribute \src "issuer_ls180.v:15765.3-15801.6" + process $proc$issuer_ls180.v:15765$328 + assign { } { } + assign { } { } + assign $0\LOGICAL_dec31_dec_sub28_is_32b[0:0] $1\LOGICAL_dec31_dec_sub28_is_32b[0:0] + attribute \src "issuer_ls180.v:15766.5-15766.29" + switch \initial + attribute \src "issuer_ls180.v:15766.9-15766.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_is_32b[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_is_32b[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_is_32b[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_is_32b[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_is_32b[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_is_32b[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_is_32b[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_is_32b[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_is_32b[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_is_32b[0:0] 1'0 + case + assign $1\LOGICAL_dec31_dec_sub28_is_32b[0:0] 1'0 + end + sync always + update \LOGICAL_dec31_dec_sub28_is_32b $0\LOGICAL_dec31_dec_sub28_is_32b[0:0] + end + attribute \src "issuer_ls180.v:15802.3-15838.6" + process $proc$issuer_ls180.v:15802$329 + assign { } { } + assign { } { } + assign $0\LOGICAL_dec31_dec_sub28_sgn[0:0] $1\LOGICAL_dec31_dec_sub28_sgn[0:0] + attribute \src "issuer_ls180.v:15803.5-15803.29" + switch \initial + attribute \src "issuer_ls180.v:15803.9-15803.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_sgn[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_sgn[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_sgn[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_sgn[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_sgn[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_sgn[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_sgn[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_sgn[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_sgn[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_sgn[0:0] 1'0 + case + assign $1\LOGICAL_dec31_dec_sub28_sgn[0:0] 1'0 + end + sync always + update \LOGICAL_dec31_dec_sub28_sgn $0\LOGICAL_dec31_dec_sub28_sgn[0:0] + end + attribute \src "issuer_ls180.v:15839.3-15875.6" + process $proc$issuer_ls180.v:15839$330 + assign { } { } + assign { } { } + assign $0\LOGICAL_dec31_dec_sub28_internal_op[6:0] $1\LOGICAL_dec31_dec_sub28_internal_op[6:0] + attribute \src "issuer_ls180.v:15840.5-15840.29" + switch \initial + attribute \src "issuer_ls180.v:15840.9-15840.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_internal_op[6:0] 7'0000100 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_internal_op[6:0] 7'0000100 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_internal_op[6:0] 7'0001001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_internal_op[6:0] 7'0001011 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_internal_op[6:0] 7'1000011 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_internal_op[6:0] 7'0000100 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_internal_op[6:0] 7'0110101 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_internal_op[6:0] 7'0110101 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_internal_op[6:0] 7'0110101 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_internal_op[6:0] 7'1000011 + case + assign $1\LOGICAL_dec31_dec_sub28_internal_op[6:0] 7'0000000 + end + sync always + update \LOGICAL_dec31_dec_sub28_internal_op $0\LOGICAL_dec31_dec_sub28_internal_op[6:0] + end + attribute \src "issuer_ls180.v:15876.3-15912.6" + process $proc$issuer_ls180.v:15876$331 + assign { } { } + assign { } { } + assign $0\LOGICAL_dec31_dec_sub28_in1_sel[2:0] $1\LOGICAL_dec31_dec_sub28_in1_sel[2:0] + attribute \src "issuer_ls180.v:15877.5-15877.29" + switch \initial + attribute \src "issuer_ls180.v:15877.9-15877.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_in1_sel[2:0] 3'100 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_in1_sel[2:0] 3'100 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_in1_sel[2:0] 3'100 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_in1_sel[2:0] 3'100 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_in1_sel[2:0] 3'100 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_in1_sel[2:0] 3'100 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_in1_sel[2:0] 3'100 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_in1_sel[2:0] 3'100 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_in1_sel[2:0] 3'100 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_in1_sel[2:0] 3'100 + case + assign $1\LOGICAL_dec31_dec_sub28_in1_sel[2:0] 3'000 + end + sync always + update \LOGICAL_dec31_dec_sub28_in1_sel $0\LOGICAL_dec31_dec_sub28_in1_sel[2:0] + end + attribute \src "issuer_ls180.v:15913.3-15949.6" + process $proc$issuer_ls180.v:15913$332 + assign { } { } + assign { } { } + assign $0\LOGICAL_dec31_dec_sub28_in2_sel[3:0] $1\LOGICAL_dec31_dec_sub28_in2_sel[3:0] + attribute \src "issuer_ls180.v:15914.5-15914.29" + switch \initial + attribute \src "issuer_ls180.v:15914.9-15914.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_in2_sel[3:0] 4'0001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_in2_sel[3:0] 4'0001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_in2_sel[3:0] 4'0001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_in2_sel[3:0] 4'0001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_in2_sel[3:0] 4'0001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_in2_sel[3:0] 4'0001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_in2_sel[3:0] 4'0001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_in2_sel[3:0] 4'0001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_in2_sel[3:0] 4'0001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_in2_sel[3:0] 4'0001 + case + assign $1\LOGICAL_dec31_dec_sub28_in2_sel[3:0] 4'0000 + end + sync always + update \LOGICAL_dec31_dec_sub28_in2_sel $0\LOGICAL_dec31_dec_sub28_in2_sel[3:0] + end + attribute \src "issuer_ls180.v:15950.3-15986.6" + process $proc$issuer_ls180.v:15950$333 + assign { } { } + assign { } { } + assign $0\LOGICAL_dec31_dec_sub28_cr_in[2:0] $1\LOGICAL_dec31_dec_sub28_cr_in[2:0] + attribute \src "issuer_ls180.v:15951.5-15951.29" + switch \initial + attribute \src "issuer_ls180.v:15951.9-15951.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_cr_in[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_cr_in[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_cr_in[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_cr_in[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_cr_in[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_cr_in[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_cr_in[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_cr_in[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_cr_in[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_cr_in[2:0] 3'000 + case + assign $1\LOGICAL_dec31_dec_sub28_cr_in[2:0] 3'000 + end + sync always + update \LOGICAL_dec31_dec_sub28_cr_in $0\LOGICAL_dec31_dec_sub28_cr_in[2:0] + end + attribute \src "issuer_ls180.v:15987.3-16023.6" + process $proc$issuer_ls180.v:15987$334 + assign { } { } + assign { } { } + assign $0\LOGICAL_dec31_dec_sub28_cr_out[2:0] $1\LOGICAL_dec31_dec_sub28_cr_out[2:0] + attribute \src "issuer_ls180.v:15988.5-15988.29" + switch \initial + attribute \src "issuer_ls180.v:15988.9-15988.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_cr_out[2:0] 3'001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_cr_out[2:0] 3'001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_cr_out[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_cr_out[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_cr_out[2:0] 3'001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_cr_out[2:0] 3'001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_cr_out[2:0] 3'001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_cr_out[2:0] 3'001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_cr_out[2:0] 3'001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_cr_out[2:0] 3'001 + case + assign $1\LOGICAL_dec31_dec_sub28_cr_out[2:0] 3'000 + end + sync always + update \LOGICAL_dec31_dec_sub28_cr_out $0\LOGICAL_dec31_dec_sub28_cr_out[2:0] + end + attribute \src "issuer_ls180.v:16024.3-16060.6" + process $proc$issuer_ls180.v:16024$335 + assign { } { } + assign { } { } + assign $0\LOGICAL_dec31_dec_sub28_ldst_len[3:0] $1\LOGICAL_dec31_dec_sub28_ldst_len[3:0] + attribute \src "issuer_ls180.v:16025.5-16025.29" + switch \initial + attribute \src "issuer_ls180.v:16025.9-16025.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_ldst_len[3:0] 4'0000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_ldst_len[3:0] 4'0000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_ldst_len[3:0] 4'0000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_ldst_len[3:0] 4'0000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_ldst_len[3:0] 4'0000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_ldst_len[3:0] 4'0000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_ldst_len[3:0] 4'0000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_ldst_len[3:0] 4'0000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_ldst_len[3:0] 4'0000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_ldst_len[3:0] 4'0000 + case + assign $1\LOGICAL_dec31_dec_sub28_ldst_len[3:0] 4'0000 + end + sync always + update \LOGICAL_dec31_dec_sub28_ldst_len $0\LOGICAL_dec31_dec_sub28_ldst_len[3:0] + end + attribute \src "issuer_ls180.v:16061.3-16097.6" + process $proc$issuer_ls180.v:16061$336 + assign { } { } + assign { } { } + assign $0\LOGICAL_dec31_dec_sub28_rc_sel[1:0] $1\LOGICAL_dec31_dec_sub28_rc_sel[1:0] + attribute \src "issuer_ls180.v:16062.5-16062.29" + switch \initial + attribute \src "issuer_ls180.v:16062.9-16062.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_rc_sel[1:0] 2'10 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_rc_sel[1:0] 2'10 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_rc_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_rc_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_rc_sel[1:0] 2'10 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_rc_sel[1:0] 2'10 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_rc_sel[1:0] 2'10 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_rc_sel[1:0] 2'10 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_rc_sel[1:0] 2'10 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_rc_sel[1:0] 2'10 + case + assign $1\LOGICAL_dec31_dec_sub28_rc_sel[1:0] 2'00 + end + sync always + update \LOGICAL_dec31_dec_sub28_rc_sel $0\LOGICAL_dec31_dec_sub28_rc_sel[1:0] + end + attribute \src "issuer_ls180.v:16098.3-16134.6" + process $proc$issuer_ls180.v:16098$337 + assign { } { } + assign { } { } + assign $0\LOGICAL_dec31_dec_sub28_cry_in[1:0] $1\LOGICAL_dec31_dec_sub28_cry_in[1:0] + attribute \src "issuer_ls180.v:16099.5-16099.29" + switch \initial + attribute \src "issuer_ls180.v:16099.9-16099.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_cry_in[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_cry_in[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_cry_in[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_cry_in[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_cry_in[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_cry_in[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_cry_in[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_cry_in[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_cry_in[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\LOGICAL_dec31_dec_sub28_cry_in[1:0] 2'00 + case + assign $1\LOGICAL_dec31_dec_sub28_cry_in[1:0] 2'00 + end + sync always + update \LOGICAL_dec31_dec_sub28_cry_in $0\LOGICAL_dec31_dec_sub28_cry_in[1:0] + end + connect \opcode_switch \opcode_in [10:6] +end +attribute \src "issuer_ls180.v:16140.1-16698.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.dec_MUL.dec.MUL_dec31" +attribute \generator "nMigen" +module \MUL_dec31 + attribute \src "issuer_ls180.v:16655.3-16667.6" + wire width 3 $0\MUL_dec31_cr_in[2:0] + attribute \src "issuer_ls180.v:16668.3-16680.6" + wire width 3 $0\MUL_dec31_cr_out[2:0] + attribute \src "issuer_ls180.v:16616.3-16628.6" + wire width 12 $0\MUL_dec31_function_unit[11:0] + attribute \src "issuer_ls180.v:16642.3-16654.6" + wire width 4 $0\MUL_dec31_in2_sel[3:0] + attribute \src "issuer_ls180.v:16629.3-16641.6" + wire width 7 $0\MUL_dec31_internal_op[6:0] + attribute \src "issuer_ls180.v:16590.3-16602.6" + wire $0\MUL_dec31_is_32b[0:0] + attribute \src "issuer_ls180.v:16681.3-16693.6" + wire width 2 $0\MUL_dec31_rc_sel[1:0] + attribute \src "issuer_ls180.v:16603.3-16615.6" + wire $0\MUL_dec31_sgn[0:0] + attribute \src "issuer_ls180.v:16141.7-16141.20" + wire $0\initial[0:0] + attribute \src "issuer_ls180.v:16655.3-16667.6" + wire width 3 $1\MUL_dec31_cr_in[2:0] + attribute \src "issuer_ls180.v:16668.3-16680.6" + wire width 3 $1\MUL_dec31_cr_out[2:0] + attribute \src "issuer_ls180.v:16616.3-16628.6" + wire width 12 $1\MUL_dec31_function_unit[11:0] + attribute \src "issuer_ls180.v:16642.3-16654.6" + wire width 4 $1\MUL_dec31_in2_sel[3:0] + attribute \src "issuer_ls180.v:16629.3-16641.6" + wire width 7 $1\MUL_dec31_internal_op[6:0] + attribute \src "issuer_ls180.v:16590.3-16602.6" + wire $1\MUL_dec31_is_32b[0:0] + attribute \src "issuer_ls180.v:16681.3-16693.6" + wire width 2 $1\MUL_dec31_rc_sel[1:0] + attribute \src "issuer_ls180.v:16603.3-16615.6" + wire $1\MUL_dec31_sgn[0:0] + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 4 \MUL_dec31_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 5 \MUL_dec31_cr_out + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 \MUL_dec31_dec_sub11_MUL_dec31_dec_sub11_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 \MUL_dec31_dec_sub11_MUL_dec31_dec_sub11_cr_out + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 12 \MUL_dec31_dec_sub11_MUL_dec31_dec_sub11_function_unit + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 \MUL_dec31_dec_sub11_MUL_dec31_dec_sub11_in2_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 7 \MUL_dec31_dec_sub11_MUL_dec31_dec_sub11_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \MUL_dec31_dec_sub11_MUL_dec31_dec_sub11_is_32b + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \MUL_dec31_dec_sub11_MUL_dec31_dec_sub11_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \MUL_dec31_dec_sub11_MUL_dec31_dec_sub11_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + wire width 32 \MUL_dec31_dec_sub11_opcode_in + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 \MUL_dec31_dec_sub9_MUL_dec31_dec_sub9_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 \MUL_dec31_dec_sub9_MUL_dec31_dec_sub9_cr_out + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 12 \MUL_dec31_dec_sub9_MUL_dec31_dec_sub9_function_unit + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 \MUL_dec31_dec_sub9_MUL_dec31_dec_sub9_in2_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 7 \MUL_dec31_dec_sub9_MUL_dec31_dec_sub9_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \MUL_dec31_dec_sub9_MUL_dec31_dec_sub9_is_32b + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \MUL_dec31_dec_sub9_MUL_dec31_dec_sub9_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \MUL_dec31_dec_sub9_MUL_dec31_dec_sub9_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + wire width 32 \MUL_dec31_dec_sub9_opcode_in + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 12 output 1 \MUL_dec31_function_unit + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 output 3 \MUL_dec31_in2_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 7 output 2 \MUL_dec31_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 7 \MUL_dec31_is_32b + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 6 \MUL_dec31_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 8 \MUL_dec31_sgn + attribute \src "issuer_ls180.v:16141.7-16141.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:326" + wire width 5 \opc_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + wire width 32 input 9 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:320" + wire width 10 \opcode_switch + attribute \module_not_derived 1 + attribute \src "issuer_ls180.v:16568.23-16578.4" + cell \MUL_dec31_dec_sub11 \MUL_dec31_dec_sub11 + connect \MUL_dec31_dec_sub11_cr_in \MUL_dec31_dec_sub11_MUL_dec31_dec_sub11_cr_in + connect \MUL_dec31_dec_sub11_cr_out \MUL_dec31_dec_sub11_MUL_dec31_dec_sub11_cr_out + connect \MUL_dec31_dec_sub11_function_unit \MUL_dec31_dec_sub11_MUL_dec31_dec_sub11_function_unit + connect \MUL_dec31_dec_sub11_in2_sel \MUL_dec31_dec_sub11_MUL_dec31_dec_sub11_in2_sel + connect \MUL_dec31_dec_sub11_internal_op \MUL_dec31_dec_sub11_MUL_dec31_dec_sub11_internal_op + connect \MUL_dec31_dec_sub11_is_32b \MUL_dec31_dec_sub11_MUL_dec31_dec_sub11_is_32b + connect \MUL_dec31_dec_sub11_rc_sel \MUL_dec31_dec_sub11_MUL_dec31_dec_sub11_rc_sel + connect \MUL_dec31_dec_sub11_sgn \MUL_dec31_dec_sub11_MUL_dec31_dec_sub11_sgn + connect \opcode_in \MUL_dec31_dec_sub11_opcode_in + end + attribute \module_not_derived 1 + attribute \src "issuer_ls180.v:16579.22-16589.4" + cell \MUL_dec31_dec_sub9 \MUL_dec31_dec_sub9 + connect \MUL_dec31_dec_sub9_cr_in \MUL_dec31_dec_sub9_MUL_dec31_dec_sub9_cr_in + connect \MUL_dec31_dec_sub9_cr_out \MUL_dec31_dec_sub9_MUL_dec31_dec_sub9_cr_out + connect \MUL_dec31_dec_sub9_function_unit \MUL_dec31_dec_sub9_MUL_dec31_dec_sub9_function_unit + connect \MUL_dec31_dec_sub9_in2_sel \MUL_dec31_dec_sub9_MUL_dec31_dec_sub9_in2_sel + connect \MUL_dec31_dec_sub9_internal_op \MUL_dec31_dec_sub9_MUL_dec31_dec_sub9_internal_op + connect \MUL_dec31_dec_sub9_is_32b \MUL_dec31_dec_sub9_MUL_dec31_dec_sub9_is_32b + connect \MUL_dec31_dec_sub9_rc_sel \MUL_dec31_dec_sub9_MUL_dec31_dec_sub9_rc_sel + connect \MUL_dec31_dec_sub9_sgn \MUL_dec31_dec_sub9_MUL_dec31_dec_sub9_sgn + connect \opcode_in \MUL_dec31_dec_sub9_opcode_in + end + attribute \src "issuer_ls180.v:16141.7-16141.20" + process $proc$issuer_ls180.v:16141$347 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "issuer_ls180.v:16590.3-16602.6" + process $proc$issuer_ls180.v:16590$339 + assign { } { } + assign { } { } + assign $0\MUL_dec31_is_32b[0:0] $1\MUL_dec31_is_32b[0:0] + attribute \src "issuer_ls180.v:16591.5-16591.29" + switch \initial + attribute \src "issuer_ls180.v:16591.9-16591.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opc_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\MUL_dec31_is_32b[0:0] \MUL_dec31_dec_sub9_MUL_dec31_dec_sub9_is_32b + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\MUL_dec31_is_32b[0:0] \MUL_dec31_dec_sub11_MUL_dec31_dec_sub11_is_32b + case + assign $1\MUL_dec31_is_32b[0:0] 1'0 + end + sync always + update \MUL_dec31_is_32b $0\MUL_dec31_is_32b[0:0] + end + attribute \src "issuer_ls180.v:16603.3-16615.6" + process $proc$issuer_ls180.v:16603$340 + assign { } { } + assign { } { } + assign $0\MUL_dec31_sgn[0:0] $1\MUL_dec31_sgn[0:0] + attribute \src "issuer_ls180.v:16604.5-16604.29" + switch \initial + attribute \src "issuer_ls180.v:16604.9-16604.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opc_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\MUL_dec31_sgn[0:0] \MUL_dec31_dec_sub9_MUL_dec31_dec_sub9_sgn + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\MUL_dec31_sgn[0:0] \MUL_dec31_dec_sub11_MUL_dec31_dec_sub11_sgn + case + assign $1\MUL_dec31_sgn[0:0] 1'0 + end + sync always + update \MUL_dec31_sgn $0\MUL_dec31_sgn[0:0] + end + attribute \src "issuer_ls180.v:16616.3-16628.6" + process $proc$issuer_ls180.v:16616$341 + assign { } { } + assign { } { } + assign $0\MUL_dec31_function_unit[11:0] $1\MUL_dec31_function_unit[11:0] + attribute \src "issuer_ls180.v:16617.5-16617.29" + switch \initial + attribute \src "issuer_ls180.v:16617.9-16617.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opc_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\MUL_dec31_function_unit[11:0] \MUL_dec31_dec_sub9_MUL_dec31_dec_sub9_function_unit + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\MUL_dec31_function_unit[11:0] \MUL_dec31_dec_sub11_MUL_dec31_dec_sub11_function_unit + case + assign $1\MUL_dec31_function_unit[11:0] 12'000000000000 + end + sync always + update \MUL_dec31_function_unit $0\MUL_dec31_function_unit[11:0] + end + attribute \src "issuer_ls180.v:16629.3-16641.6" + process $proc$issuer_ls180.v:16629$342 + assign { } { } + assign { } { } + assign $0\MUL_dec31_internal_op[6:0] $1\MUL_dec31_internal_op[6:0] + attribute \src "issuer_ls180.v:16630.5-16630.29" + switch \initial + attribute \src "issuer_ls180.v:16630.9-16630.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opc_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\MUL_dec31_internal_op[6:0] \MUL_dec31_dec_sub9_MUL_dec31_dec_sub9_internal_op + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\MUL_dec31_internal_op[6:0] \MUL_dec31_dec_sub11_MUL_dec31_dec_sub11_internal_op + case + assign $1\MUL_dec31_internal_op[6:0] 7'0000000 + end + sync always + update \MUL_dec31_internal_op $0\MUL_dec31_internal_op[6:0] + end + attribute \src "issuer_ls180.v:16642.3-16654.6" + process $proc$issuer_ls180.v:16642$343 + assign { } { } + assign { } { } + assign $0\MUL_dec31_in2_sel[3:0] $1\MUL_dec31_in2_sel[3:0] + attribute \src "issuer_ls180.v:16643.5-16643.29" + switch \initial + attribute \src "issuer_ls180.v:16643.9-16643.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opc_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\MUL_dec31_in2_sel[3:0] \MUL_dec31_dec_sub9_MUL_dec31_dec_sub9_in2_sel + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\MUL_dec31_in2_sel[3:0] \MUL_dec31_dec_sub11_MUL_dec31_dec_sub11_in2_sel + case + assign $1\MUL_dec31_in2_sel[3:0] 4'0000 + end + sync always + update \MUL_dec31_in2_sel $0\MUL_dec31_in2_sel[3:0] + end + attribute \src "issuer_ls180.v:16655.3-16667.6" + process $proc$issuer_ls180.v:16655$344 + assign { } { } + assign { } { } + assign $0\MUL_dec31_cr_in[2:0] $1\MUL_dec31_cr_in[2:0] + attribute \src "issuer_ls180.v:16656.5-16656.29" + switch \initial + attribute \src "issuer_ls180.v:16656.9-16656.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opc_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\MUL_dec31_cr_in[2:0] \MUL_dec31_dec_sub9_MUL_dec31_dec_sub9_cr_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\MUL_dec31_cr_in[2:0] \MUL_dec31_dec_sub11_MUL_dec31_dec_sub11_cr_in + case + assign $1\MUL_dec31_cr_in[2:0] 3'000 + end + sync always + update \MUL_dec31_cr_in $0\MUL_dec31_cr_in[2:0] + end + attribute \src "issuer_ls180.v:16668.3-16680.6" + process $proc$issuer_ls180.v:16668$345 + assign { } { } + assign { } { } + assign $0\MUL_dec31_cr_out[2:0] $1\MUL_dec31_cr_out[2:0] + attribute \src "issuer_ls180.v:16669.5-16669.29" + switch \initial + attribute \src "issuer_ls180.v:16669.9-16669.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opc_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\MUL_dec31_cr_out[2:0] \MUL_dec31_dec_sub9_MUL_dec31_dec_sub9_cr_out + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\MUL_dec31_cr_out[2:0] \MUL_dec31_dec_sub11_MUL_dec31_dec_sub11_cr_out + case + assign $1\MUL_dec31_cr_out[2:0] 3'000 + end + sync always + update \MUL_dec31_cr_out $0\MUL_dec31_cr_out[2:0] + end + attribute \src "issuer_ls180.v:16681.3-16693.6" + process $proc$issuer_ls180.v:16681$346 + assign { } { } + assign { } { } + assign $0\MUL_dec31_rc_sel[1:0] $1\MUL_dec31_rc_sel[1:0] + attribute \src "issuer_ls180.v:16682.5-16682.29" + switch \initial + attribute \src "issuer_ls180.v:16682.9-16682.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opc_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\MUL_dec31_rc_sel[1:0] \MUL_dec31_dec_sub9_MUL_dec31_dec_sub9_rc_sel + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\MUL_dec31_rc_sel[1:0] \MUL_dec31_dec_sub11_MUL_dec31_dec_sub11_rc_sel + case + assign $1\MUL_dec31_rc_sel[1:0] 2'00 + end + sync always + update \MUL_dec31_rc_sel $0\MUL_dec31_rc_sel[1:0] + end + connect \MUL_dec31_dec_sub11_opcode_in \opcode_in + connect \MUL_dec31_dec_sub9_opcode_in \opcode_in + connect \opc_in \opcode_switch [4:0] + connect \opcode_switch \opcode_in [10:1] +end +attribute \src "issuer_ls180.v:16702.1-17053.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.dec_MUL.dec.MUL_dec31.MUL_dec31_dec_sub11" +attribute \generator "nMigen" +module \MUL_dec31_dec_sub11 + attribute \src "issuer_ls180.v:16927.3-16951.6" + wire width 3 $0\MUL_dec31_dec_sub11_cr_in[2:0] + attribute \src "issuer_ls180.v:16952.3-16976.6" + wire width 3 $0\MUL_dec31_dec_sub11_cr_out[2:0] + attribute \src "issuer_ls180.v:16852.3-16876.6" + wire width 12 $0\MUL_dec31_dec_sub11_function_unit[11:0] + attribute \src "issuer_ls180.v:16902.3-16926.6" + wire width 4 $0\MUL_dec31_dec_sub11_in2_sel[3:0] + attribute \src "issuer_ls180.v:16877.3-16901.6" + wire width 7 $0\MUL_dec31_dec_sub11_internal_op[6:0] + attribute \src "issuer_ls180.v:17002.3-17026.6" + wire $0\MUL_dec31_dec_sub11_is_32b[0:0] + attribute \src "issuer_ls180.v:16977.3-17001.6" + wire width 2 $0\MUL_dec31_dec_sub11_rc_sel[1:0] + attribute \src "issuer_ls180.v:17027.3-17051.6" + wire $0\MUL_dec31_dec_sub11_sgn[0:0] + attribute \src "issuer_ls180.v:16703.7-16703.20" + wire $0\initial[0:0] + attribute \src "issuer_ls180.v:16927.3-16951.6" + wire width 3 $1\MUL_dec31_dec_sub11_cr_in[2:0] + attribute \src "issuer_ls180.v:16952.3-16976.6" + wire width 3 $1\MUL_dec31_dec_sub11_cr_out[2:0] + attribute \src "issuer_ls180.v:16852.3-16876.6" + wire width 12 $1\MUL_dec31_dec_sub11_function_unit[11:0] + attribute \src "issuer_ls180.v:16902.3-16926.6" + wire width 4 $1\MUL_dec31_dec_sub11_in2_sel[3:0] + attribute \src "issuer_ls180.v:16877.3-16901.6" + wire width 7 $1\MUL_dec31_dec_sub11_internal_op[6:0] + attribute \src "issuer_ls180.v:17002.3-17026.6" + wire $1\MUL_dec31_dec_sub11_is_32b[0:0] + attribute \src "issuer_ls180.v:16977.3-17001.6" + wire width 2 $1\MUL_dec31_dec_sub11_rc_sel[1:0] + attribute \src "issuer_ls180.v:17027.3-17051.6" + wire $1\MUL_dec31_dec_sub11_sgn[0:0] + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 4 \MUL_dec31_dec_sub11_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 5 \MUL_dec31_dec_sub11_cr_out + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 12 output 1 \MUL_dec31_dec_sub11_function_unit + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 output 3 \MUL_dec31_dec_sub11_in2_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 7 output 2 \MUL_dec31_dec_sub11_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 7 \MUL_dec31_dec_sub11_is_32b + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 6 \MUL_dec31_dec_sub11_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 8 \MUL_dec31_dec_sub11_sgn + attribute \src "issuer_ls180.v:16703.7-16703.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + wire width 32 input 9 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:320" + wire width 5 \opcode_switch + attribute \src "issuer_ls180.v:16703.7-16703.20" + process $proc$issuer_ls180.v:16703$356 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "issuer_ls180.v:16852.3-16876.6" + process $proc$issuer_ls180.v:16852$348 + assign { } { } + assign { } { } + assign $0\MUL_dec31_dec_sub11_function_unit[11:0] $1\MUL_dec31_dec_sub11_function_unit[11:0] + attribute \src "issuer_ls180.v:16853.5-16853.29" + switch \initial + attribute \src "issuer_ls180.v:16853.9-16853.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\MUL_dec31_dec_sub11_function_unit[11:0] 12'000100000000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\MUL_dec31_dec_sub11_function_unit[11:0] 12'000100000000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\MUL_dec31_dec_sub11_function_unit[11:0] 12'000100000000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\MUL_dec31_dec_sub11_function_unit[11:0] 12'000100000000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\MUL_dec31_dec_sub11_function_unit[11:0] 12'000100000000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\MUL_dec31_dec_sub11_function_unit[11:0] 12'000100000000 + case + assign $1\MUL_dec31_dec_sub11_function_unit[11:0] 12'000000000000 + end + sync always + update \MUL_dec31_dec_sub11_function_unit $0\MUL_dec31_dec_sub11_function_unit[11:0] + end + attribute \src "issuer_ls180.v:16877.3-16901.6" + process $proc$issuer_ls180.v:16877$349 + assign { } { } + assign { } { } + assign $0\MUL_dec31_dec_sub11_internal_op[6:0] $1\MUL_dec31_dec_sub11_internal_op[6:0] + attribute \src "issuer_ls180.v:16878.5-16878.29" + switch \initial + attribute \src "issuer_ls180.v:16878.9-16878.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\MUL_dec31_dec_sub11_internal_op[6:0] 7'0110100 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\MUL_dec31_dec_sub11_internal_op[6:0] 7'0110100 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\MUL_dec31_dec_sub11_internal_op[6:0] 7'0110100 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\MUL_dec31_dec_sub11_internal_op[6:0] 7'0110100 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\MUL_dec31_dec_sub11_internal_op[6:0] 7'0110010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\MUL_dec31_dec_sub11_internal_op[6:0] 7'0110010 + case + assign $1\MUL_dec31_dec_sub11_internal_op[6:0] 7'0000000 + end + sync always + update \MUL_dec31_dec_sub11_internal_op $0\MUL_dec31_dec_sub11_internal_op[6:0] + end + attribute \src "issuer_ls180.v:16902.3-16926.6" + process $proc$issuer_ls180.v:16902$350 + assign { } { } + assign { } { } + assign $0\MUL_dec31_dec_sub11_in2_sel[3:0] $1\MUL_dec31_dec_sub11_in2_sel[3:0] + attribute \src "issuer_ls180.v:16903.5-16903.29" + switch \initial + attribute \src "issuer_ls180.v:16903.9-16903.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\MUL_dec31_dec_sub11_in2_sel[3:0] 4'0001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\MUL_dec31_dec_sub11_in2_sel[3:0] 4'0001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\MUL_dec31_dec_sub11_in2_sel[3:0] 4'0001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\MUL_dec31_dec_sub11_in2_sel[3:0] 4'0001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\MUL_dec31_dec_sub11_in2_sel[3:0] 4'0001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\MUL_dec31_dec_sub11_in2_sel[3:0] 4'0001 + case + assign $1\MUL_dec31_dec_sub11_in2_sel[3:0] 4'0000 + end + sync always + update \MUL_dec31_dec_sub11_in2_sel $0\MUL_dec31_dec_sub11_in2_sel[3:0] + end + attribute \src "issuer_ls180.v:16927.3-16951.6" + process $proc$issuer_ls180.v:16927$351 + assign { } { } + assign { } { } + assign $0\MUL_dec31_dec_sub11_cr_in[2:0] $1\MUL_dec31_dec_sub11_cr_in[2:0] + attribute \src "issuer_ls180.v:16928.5-16928.29" + switch \initial + attribute \src "issuer_ls180.v:16928.9-16928.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\MUL_dec31_dec_sub11_cr_in[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\MUL_dec31_dec_sub11_cr_in[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\MUL_dec31_dec_sub11_cr_in[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\MUL_dec31_dec_sub11_cr_in[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\MUL_dec31_dec_sub11_cr_in[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\MUL_dec31_dec_sub11_cr_in[2:0] 3'000 + case + assign $1\MUL_dec31_dec_sub11_cr_in[2:0] 3'000 + end + sync always + update \MUL_dec31_dec_sub11_cr_in $0\MUL_dec31_dec_sub11_cr_in[2:0] + end + attribute \src "issuer_ls180.v:16952.3-16976.6" + process $proc$issuer_ls180.v:16952$352 + assign { } { } + assign { } { } + assign $0\MUL_dec31_dec_sub11_cr_out[2:0] $1\MUL_dec31_dec_sub11_cr_out[2:0] + attribute \src "issuer_ls180.v:16953.5-16953.29" + switch \initial + attribute \src "issuer_ls180.v:16953.9-16953.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\MUL_dec31_dec_sub11_cr_out[2:0] 3'001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\MUL_dec31_dec_sub11_cr_out[2:0] 3'001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\MUL_dec31_dec_sub11_cr_out[2:0] 3'001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\MUL_dec31_dec_sub11_cr_out[2:0] 3'001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\MUL_dec31_dec_sub11_cr_out[2:0] 3'001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\MUL_dec31_dec_sub11_cr_out[2:0] 3'001 + case + assign $1\MUL_dec31_dec_sub11_cr_out[2:0] 3'000 + end + sync always + update \MUL_dec31_dec_sub11_cr_out $0\MUL_dec31_dec_sub11_cr_out[2:0] + end + attribute \src "issuer_ls180.v:16977.3-17001.6" + process $proc$issuer_ls180.v:16977$353 + assign { } { } + assign { } { } + assign $0\MUL_dec31_dec_sub11_rc_sel[1:0] $1\MUL_dec31_dec_sub11_rc_sel[1:0] + attribute \src "issuer_ls180.v:16978.5-16978.29" + switch \initial + attribute \src "issuer_ls180.v:16978.9-16978.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\MUL_dec31_dec_sub11_rc_sel[1:0] 2'10 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\MUL_dec31_dec_sub11_rc_sel[1:0] 2'10 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\MUL_dec31_dec_sub11_rc_sel[1:0] 2'10 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\MUL_dec31_dec_sub11_rc_sel[1:0] 2'10 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\MUL_dec31_dec_sub11_rc_sel[1:0] 2'10 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\MUL_dec31_dec_sub11_rc_sel[1:0] 2'10 + case + assign $1\MUL_dec31_dec_sub11_rc_sel[1:0] 2'00 + end + sync always + update \MUL_dec31_dec_sub11_rc_sel $0\MUL_dec31_dec_sub11_rc_sel[1:0] + end + attribute \src "issuer_ls180.v:17002.3-17026.6" + process $proc$issuer_ls180.v:17002$354 + assign { } { } + assign { } { } + assign $0\MUL_dec31_dec_sub11_is_32b[0:0] $1\MUL_dec31_dec_sub11_is_32b[0:0] + attribute \src "issuer_ls180.v:17003.5-17003.29" + switch \initial + attribute \src "issuer_ls180.v:17003.9-17003.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\MUL_dec31_dec_sub11_is_32b[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\MUL_dec31_dec_sub11_is_32b[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\MUL_dec31_dec_sub11_is_32b[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\MUL_dec31_dec_sub11_is_32b[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\MUL_dec31_dec_sub11_is_32b[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\MUL_dec31_dec_sub11_is_32b[0:0] 1'1 + case + assign $1\MUL_dec31_dec_sub11_is_32b[0:0] 1'0 + end + sync always + update \MUL_dec31_dec_sub11_is_32b $0\MUL_dec31_dec_sub11_is_32b[0:0] + end + attribute \src "issuer_ls180.v:17027.3-17051.6" + process $proc$issuer_ls180.v:17027$355 + assign { } { } + assign { } { } + assign $0\MUL_dec31_dec_sub11_sgn[0:0] $1\MUL_dec31_dec_sub11_sgn[0:0] + attribute \src "issuer_ls180.v:17028.5-17028.29" + switch \initial + attribute \src "issuer_ls180.v:17028.9-17028.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\MUL_dec31_dec_sub11_sgn[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\MUL_dec31_dec_sub11_sgn[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\MUL_dec31_dec_sub11_sgn[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\MUL_dec31_dec_sub11_sgn[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\MUL_dec31_dec_sub11_sgn[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\MUL_dec31_dec_sub11_sgn[0:0] 1'1 + case + assign $1\MUL_dec31_dec_sub11_sgn[0:0] 1'0 + end + sync always + update \MUL_dec31_dec_sub11_sgn $0\MUL_dec31_dec_sub11_sgn[0:0] + end + connect \opcode_switch \opcode_in [10:6] +end +attribute \src "issuer_ls180.v:17057.1-17408.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.dec_MUL.dec.MUL_dec31.MUL_dec31_dec_sub9" +attribute \generator "nMigen" +module \MUL_dec31_dec_sub9 + attribute \src "issuer_ls180.v:17282.3-17306.6" + wire width 3 $0\MUL_dec31_dec_sub9_cr_in[2:0] + attribute \src "issuer_ls180.v:17307.3-17331.6" + wire width 3 $0\MUL_dec31_dec_sub9_cr_out[2:0] + attribute \src "issuer_ls180.v:17207.3-17231.6" + wire width 12 $0\MUL_dec31_dec_sub9_function_unit[11:0] + attribute \src "issuer_ls180.v:17257.3-17281.6" + wire width 4 $0\MUL_dec31_dec_sub9_in2_sel[3:0] + attribute \src "issuer_ls180.v:17232.3-17256.6" + wire width 7 $0\MUL_dec31_dec_sub9_internal_op[6:0] + attribute \src "issuer_ls180.v:17357.3-17381.6" + wire $0\MUL_dec31_dec_sub9_is_32b[0:0] + attribute \src "issuer_ls180.v:17332.3-17356.6" + wire width 2 $0\MUL_dec31_dec_sub9_rc_sel[1:0] + attribute \src "issuer_ls180.v:17382.3-17406.6" + wire $0\MUL_dec31_dec_sub9_sgn[0:0] + attribute \src "issuer_ls180.v:17058.7-17058.20" + wire $0\initial[0:0] + attribute \src "issuer_ls180.v:17282.3-17306.6" + wire width 3 $1\MUL_dec31_dec_sub9_cr_in[2:0] + attribute \src "issuer_ls180.v:17307.3-17331.6" + wire width 3 $1\MUL_dec31_dec_sub9_cr_out[2:0] + attribute \src "issuer_ls180.v:17207.3-17231.6" + wire width 12 $1\MUL_dec31_dec_sub9_function_unit[11:0] + attribute \src "issuer_ls180.v:17257.3-17281.6" + wire width 4 $1\MUL_dec31_dec_sub9_in2_sel[3:0] + attribute \src "issuer_ls180.v:17232.3-17256.6" + wire width 7 $1\MUL_dec31_dec_sub9_internal_op[6:0] + attribute \src "issuer_ls180.v:17357.3-17381.6" + wire $1\MUL_dec31_dec_sub9_is_32b[0:0] + attribute \src "issuer_ls180.v:17332.3-17356.6" + wire width 2 $1\MUL_dec31_dec_sub9_rc_sel[1:0] + attribute \src "issuer_ls180.v:17382.3-17406.6" + wire $1\MUL_dec31_dec_sub9_sgn[0:0] + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 4 \MUL_dec31_dec_sub9_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 5 \MUL_dec31_dec_sub9_cr_out + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 12 output 1 \MUL_dec31_dec_sub9_function_unit + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 output 3 \MUL_dec31_dec_sub9_in2_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 7 output 2 \MUL_dec31_dec_sub9_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 7 \MUL_dec31_dec_sub9_is_32b + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 6 \MUL_dec31_dec_sub9_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 8 \MUL_dec31_dec_sub9_sgn + attribute \src "issuer_ls180.v:17058.7-17058.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + wire width 32 input 9 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:320" + wire width 5 \opcode_switch + attribute \src "issuer_ls180.v:17058.7-17058.20" + process $proc$issuer_ls180.v:17058$365 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "issuer_ls180.v:17207.3-17231.6" + process $proc$issuer_ls180.v:17207$357 + assign { } { } + assign { } { } + assign $0\MUL_dec31_dec_sub9_function_unit[11:0] $1\MUL_dec31_dec_sub9_function_unit[11:0] + attribute \src "issuer_ls180.v:17208.5-17208.29" + switch \initial + attribute \src "issuer_ls180.v:17208.9-17208.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\MUL_dec31_dec_sub9_function_unit[11:0] 12'000100000000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\MUL_dec31_dec_sub9_function_unit[11:0] 12'000100000000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\MUL_dec31_dec_sub9_function_unit[11:0] 12'000100000000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\MUL_dec31_dec_sub9_function_unit[11:0] 12'000100000000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\MUL_dec31_dec_sub9_function_unit[11:0] 12'000100000000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\MUL_dec31_dec_sub9_function_unit[11:0] 12'000100000000 + case + assign $1\MUL_dec31_dec_sub9_function_unit[11:0] 12'000000000000 + end + sync always + update \MUL_dec31_dec_sub9_function_unit $0\MUL_dec31_dec_sub9_function_unit[11:0] + end + attribute \src "issuer_ls180.v:17232.3-17256.6" + process $proc$issuer_ls180.v:17232$358 + assign { } { } + assign { } { } + assign $0\MUL_dec31_dec_sub9_internal_op[6:0] $1\MUL_dec31_dec_sub9_internal_op[6:0] + attribute \src "issuer_ls180.v:17233.5-17233.29" + switch \initial + attribute \src "issuer_ls180.v:17233.9-17233.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\MUL_dec31_dec_sub9_internal_op[6:0] 7'0110011 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\MUL_dec31_dec_sub9_internal_op[6:0] 7'0110011 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\MUL_dec31_dec_sub9_internal_op[6:0] 7'0110011 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\MUL_dec31_dec_sub9_internal_op[6:0] 7'0110011 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\MUL_dec31_dec_sub9_internal_op[6:0] 7'0110010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\MUL_dec31_dec_sub9_internal_op[6:0] 7'0110010 + case + assign $1\MUL_dec31_dec_sub9_internal_op[6:0] 7'0000000 + end + sync always + update \MUL_dec31_dec_sub9_internal_op $0\MUL_dec31_dec_sub9_internal_op[6:0] + end + attribute \src "issuer_ls180.v:17257.3-17281.6" + process $proc$issuer_ls180.v:17257$359 + assign { } { } + assign { } { } + assign $0\MUL_dec31_dec_sub9_in2_sel[3:0] $1\MUL_dec31_dec_sub9_in2_sel[3:0] + attribute \src "issuer_ls180.v:17258.5-17258.29" + switch \initial + attribute \src "issuer_ls180.v:17258.9-17258.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\MUL_dec31_dec_sub9_in2_sel[3:0] 4'0001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\MUL_dec31_dec_sub9_in2_sel[3:0] 4'0001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\MUL_dec31_dec_sub9_in2_sel[3:0] 4'0001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\MUL_dec31_dec_sub9_in2_sel[3:0] 4'0001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\MUL_dec31_dec_sub9_in2_sel[3:0] 4'0001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\MUL_dec31_dec_sub9_in2_sel[3:0] 4'0001 + case + assign $1\MUL_dec31_dec_sub9_in2_sel[3:0] 4'0000 + end + sync always + update \MUL_dec31_dec_sub9_in2_sel $0\MUL_dec31_dec_sub9_in2_sel[3:0] + end + attribute \src "issuer_ls180.v:17282.3-17306.6" + process $proc$issuer_ls180.v:17282$360 + assign { } { } + assign { } { } + assign $0\MUL_dec31_dec_sub9_cr_in[2:0] $1\MUL_dec31_dec_sub9_cr_in[2:0] + attribute \src "issuer_ls180.v:17283.5-17283.29" + switch \initial + attribute \src "issuer_ls180.v:17283.9-17283.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\MUL_dec31_dec_sub9_cr_in[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\MUL_dec31_dec_sub9_cr_in[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\MUL_dec31_dec_sub9_cr_in[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\MUL_dec31_dec_sub9_cr_in[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\MUL_dec31_dec_sub9_cr_in[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\MUL_dec31_dec_sub9_cr_in[2:0] 3'000 + case + assign $1\MUL_dec31_dec_sub9_cr_in[2:0] 3'000 + end + sync always + update \MUL_dec31_dec_sub9_cr_in $0\MUL_dec31_dec_sub9_cr_in[2:0] + end + attribute \src "issuer_ls180.v:17307.3-17331.6" + process $proc$issuer_ls180.v:17307$361 + assign { } { } + assign { } { } + assign $0\MUL_dec31_dec_sub9_cr_out[2:0] $1\MUL_dec31_dec_sub9_cr_out[2:0] + attribute \src "issuer_ls180.v:17308.5-17308.29" + switch \initial + attribute \src "issuer_ls180.v:17308.9-17308.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\MUL_dec31_dec_sub9_cr_out[2:0] 3'001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\MUL_dec31_dec_sub9_cr_out[2:0] 3'001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\MUL_dec31_dec_sub9_cr_out[2:0] 3'001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\MUL_dec31_dec_sub9_cr_out[2:0] 3'001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\MUL_dec31_dec_sub9_cr_out[2:0] 3'001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\MUL_dec31_dec_sub9_cr_out[2:0] 3'001 + case + assign $1\MUL_dec31_dec_sub9_cr_out[2:0] 3'000 + end + sync always + update \MUL_dec31_dec_sub9_cr_out $0\MUL_dec31_dec_sub9_cr_out[2:0] + end + attribute \src "issuer_ls180.v:17332.3-17356.6" + process $proc$issuer_ls180.v:17332$362 + assign { } { } + assign { } { } + assign $0\MUL_dec31_dec_sub9_rc_sel[1:0] $1\MUL_dec31_dec_sub9_rc_sel[1:0] + attribute \src "issuer_ls180.v:17333.5-17333.29" + switch \initial + attribute \src "issuer_ls180.v:17333.9-17333.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\MUL_dec31_dec_sub9_rc_sel[1:0] 2'10 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\MUL_dec31_dec_sub9_rc_sel[1:0] 2'10 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\MUL_dec31_dec_sub9_rc_sel[1:0] 2'10 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\MUL_dec31_dec_sub9_rc_sel[1:0] 2'10 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\MUL_dec31_dec_sub9_rc_sel[1:0] 2'10 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\MUL_dec31_dec_sub9_rc_sel[1:0] 2'10 + case + assign $1\MUL_dec31_dec_sub9_rc_sel[1:0] 2'00 + end + sync always + update \MUL_dec31_dec_sub9_rc_sel $0\MUL_dec31_dec_sub9_rc_sel[1:0] + end + attribute \src "issuer_ls180.v:17357.3-17381.6" + process $proc$issuer_ls180.v:17357$363 + assign { } { } + assign { } { } + assign $0\MUL_dec31_dec_sub9_is_32b[0:0] $1\MUL_dec31_dec_sub9_is_32b[0:0] + attribute \src "issuer_ls180.v:17358.5-17358.29" + switch \initial + attribute \src "issuer_ls180.v:17358.9-17358.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\MUL_dec31_dec_sub9_is_32b[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\MUL_dec31_dec_sub9_is_32b[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\MUL_dec31_dec_sub9_is_32b[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\MUL_dec31_dec_sub9_is_32b[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\MUL_dec31_dec_sub9_is_32b[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\MUL_dec31_dec_sub9_is_32b[0:0] 1'0 + case + assign $1\MUL_dec31_dec_sub9_is_32b[0:0] 1'0 + end + sync always + update \MUL_dec31_dec_sub9_is_32b $0\MUL_dec31_dec_sub9_is_32b[0:0] + end + attribute \src "issuer_ls180.v:17382.3-17406.6" + process $proc$issuer_ls180.v:17382$364 + assign { } { } + assign { } { } + assign $0\MUL_dec31_dec_sub9_sgn[0:0] $1\MUL_dec31_dec_sub9_sgn[0:0] + attribute \src "issuer_ls180.v:17383.5-17383.29" + switch \initial + attribute \src "issuer_ls180.v:17383.9-17383.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\MUL_dec31_dec_sub9_sgn[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\MUL_dec31_dec_sub9_sgn[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\MUL_dec31_dec_sub9_sgn[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\MUL_dec31_dec_sub9_sgn[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\MUL_dec31_dec_sub9_sgn[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\MUL_dec31_dec_sub9_sgn[0:0] 1'1 + case + assign $1\MUL_dec31_dec_sub9_sgn[0:0] 1'0 + end + sync always + update \MUL_dec31_dec_sub9_sgn $0\MUL_dec31_dec_sub9_sgn[0:0] + end + connect \opcode_switch \opcode_in [10:6] +end +attribute \src "issuer_ls180.v:17412.1-17943.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.dec_SHIFT_ROT.dec.SHIFT_ROT_dec30" +attribute \generator "nMigen" +module \SHIFT_ROT_dec30 + attribute \src "issuer_ls180.v:17720.3-17756.6" + wire width 3 $0\SHIFT_ROT_dec30_cr_in[2:0] + attribute \src "issuer_ls180.v:17757.3-17793.6" + wire width 3 $0\SHIFT_ROT_dec30_cr_out[2:0] + attribute \src "issuer_ls180.v:17831.3-17867.6" + wire width 2 $0\SHIFT_ROT_dec30_cry_in[1:0] + attribute \src "issuer_ls180.v:17868.3-17904.6" + wire $0\SHIFT_ROT_dec30_cry_out[0:0] + attribute \src "issuer_ls180.v:17572.3-17608.6" + wire width 12 $0\SHIFT_ROT_dec30_function_unit[11:0] + attribute \src "issuer_ls180.v:17683.3-17719.6" + wire width 4 $0\SHIFT_ROT_dec30_in2_sel[3:0] + attribute \src "issuer_ls180.v:17646.3-17682.6" + wire width 7 $0\SHIFT_ROT_dec30_internal_op[6:0] + attribute \src "issuer_ls180.v:17905.3-17941.6" + wire $0\SHIFT_ROT_dec30_is_32b[0:0] + attribute \src "issuer_ls180.v:17794.3-17830.6" + wire width 2 $0\SHIFT_ROT_dec30_rc_sel[1:0] + attribute \src "issuer_ls180.v:17609.3-17645.6" + wire $0\SHIFT_ROT_dec30_sgn[0:0] + attribute \src "issuer_ls180.v:17413.7-17413.20" + wire $0\initial[0:0] + attribute \src "issuer_ls180.v:17720.3-17756.6" + wire width 3 $1\SHIFT_ROT_dec30_cr_in[2:0] + attribute \src "issuer_ls180.v:17757.3-17793.6" + wire width 3 $1\SHIFT_ROT_dec30_cr_out[2:0] + attribute \src "issuer_ls180.v:17831.3-17867.6" + wire width 2 $1\SHIFT_ROT_dec30_cry_in[1:0] + attribute \src "issuer_ls180.v:17868.3-17904.6" + wire $1\SHIFT_ROT_dec30_cry_out[0:0] + attribute \src "issuer_ls180.v:17572.3-17608.6" + wire width 12 $1\SHIFT_ROT_dec30_function_unit[11:0] + attribute \src "issuer_ls180.v:17683.3-17719.6" + wire width 4 $1\SHIFT_ROT_dec30_in2_sel[3:0] + attribute \src "issuer_ls180.v:17646.3-17682.6" + wire width 7 $1\SHIFT_ROT_dec30_internal_op[6:0] + attribute \src "issuer_ls180.v:17905.3-17941.6" + wire $1\SHIFT_ROT_dec30_is_32b[0:0] + attribute \src "issuer_ls180.v:17794.3-17830.6" + wire width 2 $1\SHIFT_ROT_dec30_rc_sel[1:0] + attribute \src "issuer_ls180.v:17609.3-17645.6" + wire $1\SHIFT_ROT_dec30_sgn[0:0] + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 4 \SHIFT_ROT_dec30_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 5 \SHIFT_ROT_dec30_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 7 \SHIFT_ROT_dec30_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 8 \SHIFT_ROT_dec30_cry_out + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 12 output 1 \SHIFT_ROT_dec30_function_unit + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 output 3 \SHIFT_ROT_dec30_in2_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 7 output 2 \SHIFT_ROT_dec30_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 9 \SHIFT_ROT_dec30_is_32b + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 6 \SHIFT_ROT_dec30_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 10 \SHIFT_ROT_dec30_sgn + attribute \src "issuer_ls180.v:17413.7-17413.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + wire width 32 input 11 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:320" + wire width 4 \opcode_switch + attribute \src "issuer_ls180.v:17413.7-17413.20" + process $proc$issuer_ls180.v:17413$376 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "issuer_ls180.v:17572.3-17608.6" + process $proc$issuer_ls180.v:17572$366 + assign { } { } + assign { } { } + assign $0\SHIFT_ROT_dec30_function_unit[11:0] $1\SHIFT_ROT_dec30_function_unit[11:0] + attribute \src "issuer_ls180.v:17573.5-17573.29" + switch \initial + attribute \src "issuer_ls180.v:17573.9-17573.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0100 + assign { } { } + assign $1\SHIFT_ROT_dec30_function_unit[11:0] 12'000000001000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0101 + assign { } { } + assign $1\SHIFT_ROT_dec30_function_unit[11:0] 12'000000001000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $1\SHIFT_ROT_dec30_function_unit[11:0] 12'000000001000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0001 + assign { } { } + assign $1\SHIFT_ROT_dec30_function_unit[11:0] 12'000000001000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0010 + assign { } { } + assign $1\SHIFT_ROT_dec30_function_unit[11:0] 12'000000001000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0011 + assign { } { } + assign $1\SHIFT_ROT_dec30_function_unit[11:0] 12'000000001000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\SHIFT_ROT_dec30_function_unit[11:0] 12'000000001000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $1\SHIFT_ROT_dec30_function_unit[11:0] 12'000000001000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\SHIFT_ROT_dec30_function_unit[11:0] 12'000000001000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'1001 + assign { } { } + assign $1\SHIFT_ROT_dec30_function_unit[11:0] 12'000000001000 + case + assign $1\SHIFT_ROT_dec30_function_unit[11:0] 12'000000000000 + end + sync always + update \SHIFT_ROT_dec30_function_unit $0\SHIFT_ROT_dec30_function_unit[11:0] + end + attribute \src "issuer_ls180.v:17609.3-17645.6" + process $proc$issuer_ls180.v:17609$367 + assign { } { } + assign { } { } + assign $0\SHIFT_ROT_dec30_sgn[0:0] $1\SHIFT_ROT_dec30_sgn[0:0] + attribute \src "issuer_ls180.v:17610.5-17610.29" + switch \initial + attribute \src "issuer_ls180.v:17610.9-17610.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0100 + assign { } { } + assign $1\SHIFT_ROT_dec30_sgn[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0101 + assign { } { } + assign $1\SHIFT_ROT_dec30_sgn[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $1\SHIFT_ROT_dec30_sgn[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0001 + assign { } { } + assign $1\SHIFT_ROT_dec30_sgn[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0010 + assign { } { } + assign $1\SHIFT_ROT_dec30_sgn[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0011 + assign { } { } + assign $1\SHIFT_ROT_dec30_sgn[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\SHIFT_ROT_dec30_sgn[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $1\SHIFT_ROT_dec30_sgn[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\SHIFT_ROT_dec30_sgn[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'1001 + assign { } { } + assign $1\SHIFT_ROT_dec30_sgn[0:0] 1'0 + case + assign $1\SHIFT_ROT_dec30_sgn[0:0] 1'0 + end + sync always + update \SHIFT_ROT_dec30_sgn $0\SHIFT_ROT_dec30_sgn[0:0] + end + attribute \src "issuer_ls180.v:17646.3-17682.6" + process $proc$issuer_ls180.v:17646$368 + assign { } { } + assign { } { } + assign $0\SHIFT_ROT_dec30_internal_op[6:0] $1\SHIFT_ROT_dec30_internal_op[6:0] + attribute \src "issuer_ls180.v:17647.5-17647.29" + switch \initial + attribute \src "issuer_ls180.v:17647.9-17647.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0100 + assign { } { } + assign $1\SHIFT_ROT_dec30_internal_op[6:0] 7'0111000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0101 + assign { } { } + assign $1\SHIFT_ROT_dec30_internal_op[6:0] 7'0111000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $1\SHIFT_ROT_dec30_internal_op[6:0] 7'0111001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0001 + assign { } { } + assign $1\SHIFT_ROT_dec30_internal_op[6:0] 7'0111001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0010 + assign { } { } + assign $1\SHIFT_ROT_dec30_internal_op[6:0] 7'0111010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0011 + assign { } { } + assign $1\SHIFT_ROT_dec30_internal_op[6:0] 7'0111010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\SHIFT_ROT_dec30_internal_op[6:0] 7'0111000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $1\SHIFT_ROT_dec30_internal_op[6:0] 7'0111000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\SHIFT_ROT_dec30_internal_op[6:0] 7'0111001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'1001 + assign { } { } + assign $1\SHIFT_ROT_dec30_internal_op[6:0] 7'0111010 + case + assign $1\SHIFT_ROT_dec30_internal_op[6:0] 7'0000000 + end + sync always + update \SHIFT_ROT_dec30_internal_op $0\SHIFT_ROT_dec30_internal_op[6:0] + end + attribute \src "issuer_ls180.v:17683.3-17719.6" + process $proc$issuer_ls180.v:17683$369 + assign { } { } + assign { } { } + assign $0\SHIFT_ROT_dec30_in2_sel[3:0] $1\SHIFT_ROT_dec30_in2_sel[3:0] + attribute \src "issuer_ls180.v:17684.5-17684.29" + switch \initial + attribute \src "issuer_ls180.v:17684.9-17684.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0100 + assign { } { } + assign $1\SHIFT_ROT_dec30_in2_sel[3:0] 4'1010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0101 + assign { } { } + assign $1\SHIFT_ROT_dec30_in2_sel[3:0] 4'1010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $1\SHIFT_ROT_dec30_in2_sel[3:0] 4'1010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0001 + assign { } { } + assign $1\SHIFT_ROT_dec30_in2_sel[3:0] 4'1010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0010 + assign { } { } + assign $1\SHIFT_ROT_dec30_in2_sel[3:0] 4'1010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0011 + assign { } { } + assign $1\SHIFT_ROT_dec30_in2_sel[3:0] 4'1010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\SHIFT_ROT_dec30_in2_sel[3:0] 4'1010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $1\SHIFT_ROT_dec30_in2_sel[3:0] 4'1010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\SHIFT_ROT_dec30_in2_sel[3:0] 4'0001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'1001 + assign { } { } + assign $1\SHIFT_ROT_dec30_in2_sel[3:0] 4'0001 + case + assign $1\SHIFT_ROT_dec30_in2_sel[3:0] 4'0000 + end + sync always + update \SHIFT_ROT_dec30_in2_sel $0\SHIFT_ROT_dec30_in2_sel[3:0] + end + attribute \src "issuer_ls180.v:17720.3-17756.6" + process $proc$issuer_ls180.v:17720$370 + assign { } { } + assign { } { } + assign $0\SHIFT_ROT_dec30_cr_in[2:0] $1\SHIFT_ROT_dec30_cr_in[2:0] + attribute \src "issuer_ls180.v:17721.5-17721.29" + switch \initial + attribute \src "issuer_ls180.v:17721.9-17721.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0100 + assign { } { } + assign $1\SHIFT_ROT_dec30_cr_in[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0101 + assign { } { } + assign $1\SHIFT_ROT_dec30_cr_in[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $1\SHIFT_ROT_dec30_cr_in[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0001 + assign { } { } + assign $1\SHIFT_ROT_dec30_cr_in[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0010 + assign { } { } + assign $1\SHIFT_ROT_dec30_cr_in[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0011 + assign { } { } + assign $1\SHIFT_ROT_dec30_cr_in[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\SHIFT_ROT_dec30_cr_in[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $1\SHIFT_ROT_dec30_cr_in[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\SHIFT_ROT_dec30_cr_in[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'1001 + assign { } { } + assign $1\SHIFT_ROT_dec30_cr_in[2:0] 3'000 + case + assign $1\SHIFT_ROT_dec30_cr_in[2:0] 3'000 + end + sync always + update \SHIFT_ROT_dec30_cr_in $0\SHIFT_ROT_dec30_cr_in[2:0] + end + attribute \src "issuer_ls180.v:17757.3-17793.6" + process $proc$issuer_ls180.v:17757$371 + assign { } { } + assign { } { } + assign $0\SHIFT_ROT_dec30_cr_out[2:0] $1\SHIFT_ROT_dec30_cr_out[2:0] + attribute \src "issuer_ls180.v:17758.5-17758.29" + switch \initial + attribute \src "issuer_ls180.v:17758.9-17758.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0100 + assign { } { } + assign $1\SHIFT_ROT_dec30_cr_out[2:0] 3'001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0101 + assign { } { } + assign $1\SHIFT_ROT_dec30_cr_out[2:0] 3'001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $1\SHIFT_ROT_dec30_cr_out[2:0] 3'001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0001 + assign { } { } + assign $1\SHIFT_ROT_dec30_cr_out[2:0] 3'001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0010 + assign { } { } + assign $1\SHIFT_ROT_dec30_cr_out[2:0] 3'001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0011 + assign { } { } + assign $1\SHIFT_ROT_dec30_cr_out[2:0] 3'001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\SHIFT_ROT_dec30_cr_out[2:0] 3'001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $1\SHIFT_ROT_dec30_cr_out[2:0] 3'001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\SHIFT_ROT_dec30_cr_out[2:0] 3'001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'1001 + assign { } { } + assign $1\SHIFT_ROT_dec30_cr_out[2:0] 3'001 + case + assign $1\SHIFT_ROT_dec30_cr_out[2:0] 3'000 + end + sync always + update \SHIFT_ROT_dec30_cr_out $0\SHIFT_ROT_dec30_cr_out[2:0] + end + attribute \src "issuer_ls180.v:17794.3-17830.6" + process $proc$issuer_ls180.v:17794$372 + assign { } { } + assign { } { } + assign $0\SHIFT_ROT_dec30_rc_sel[1:0] $1\SHIFT_ROT_dec30_rc_sel[1:0] + attribute \src "issuer_ls180.v:17795.5-17795.29" + switch \initial + attribute \src "issuer_ls180.v:17795.9-17795.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0100 + assign { } { } + assign $1\SHIFT_ROT_dec30_rc_sel[1:0] 2'10 + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0101 + assign { } { } + assign $1\SHIFT_ROT_dec30_rc_sel[1:0] 2'10 + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $1\SHIFT_ROT_dec30_rc_sel[1:0] 2'10 + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0001 + assign { } { } + assign $1\SHIFT_ROT_dec30_rc_sel[1:0] 2'10 + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0010 + assign { } { } + assign $1\SHIFT_ROT_dec30_rc_sel[1:0] 2'10 + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0011 + assign { } { } + assign $1\SHIFT_ROT_dec30_rc_sel[1:0] 2'10 + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\SHIFT_ROT_dec30_rc_sel[1:0] 2'10 + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $1\SHIFT_ROT_dec30_rc_sel[1:0] 2'10 + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\SHIFT_ROT_dec30_rc_sel[1:0] 2'10 + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'1001 + assign { } { } + assign $1\SHIFT_ROT_dec30_rc_sel[1:0] 2'10 + case + assign $1\SHIFT_ROT_dec30_rc_sel[1:0] 2'00 + end + sync always + update \SHIFT_ROT_dec30_rc_sel $0\SHIFT_ROT_dec30_rc_sel[1:0] + end + attribute \src "issuer_ls180.v:17831.3-17867.6" + process $proc$issuer_ls180.v:17831$373 + assign { } { } + assign { } { } + assign $0\SHIFT_ROT_dec30_cry_in[1:0] $1\SHIFT_ROT_dec30_cry_in[1:0] + attribute \src "issuer_ls180.v:17832.5-17832.29" + switch \initial + attribute \src "issuer_ls180.v:17832.9-17832.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0100 + assign { } { } + assign $1\SHIFT_ROT_dec30_cry_in[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0101 + assign { } { } + assign $1\SHIFT_ROT_dec30_cry_in[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $1\SHIFT_ROT_dec30_cry_in[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0001 + assign { } { } + assign $1\SHIFT_ROT_dec30_cry_in[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0010 + assign { } { } + assign $1\SHIFT_ROT_dec30_cry_in[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0011 + assign { } { } + assign $1\SHIFT_ROT_dec30_cry_in[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\SHIFT_ROT_dec30_cry_in[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $1\SHIFT_ROT_dec30_cry_in[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\SHIFT_ROT_dec30_cry_in[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'1001 + assign { } { } + assign $1\SHIFT_ROT_dec30_cry_in[1:0] 2'00 + case + assign $1\SHIFT_ROT_dec30_cry_in[1:0] 2'00 + end + sync always + update \SHIFT_ROT_dec30_cry_in $0\SHIFT_ROT_dec30_cry_in[1:0] + end + attribute \src "issuer_ls180.v:17868.3-17904.6" + process $proc$issuer_ls180.v:17868$374 + assign { } { } + assign { } { } + assign $0\SHIFT_ROT_dec30_cry_out[0:0] $1\SHIFT_ROT_dec30_cry_out[0:0] + attribute \src "issuer_ls180.v:17869.5-17869.29" + switch \initial + attribute \src "issuer_ls180.v:17869.9-17869.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0100 + assign { } { } + assign $1\SHIFT_ROT_dec30_cry_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0101 + assign { } { } + assign $1\SHIFT_ROT_dec30_cry_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $1\SHIFT_ROT_dec30_cry_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0001 + assign { } { } + assign $1\SHIFT_ROT_dec30_cry_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0010 + assign { } { } + assign $1\SHIFT_ROT_dec30_cry_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0011 + assign { } { } + assign $1\SHIFT_ROT_dec30_cry_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\SHIFT_ROT_dec30_cry_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $1\SHIFT_ROT_dec30_cry_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\SHIFT_ROT_dec30_cry_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'1001 + assign { } { } + assign $1\SHIFT_ROT_dec30_cry_out[0:0] 1'0 + case + assign $1\SHIFT_ROT_dec30_cry_out[0:0] 1'0 + end + sync always + update \SHIFT_ROT_dec30_cry_out $0\SHIFT_ROT_dec30_cry_out[0:0] + end + attribute \src "issuer_ls180.v:17905.3-17941.6" + process $proc$issuer_ls180.v:17905$375 + assign { } { } + assign { } { } + assign $0\SHIFT_ROT_dec30_is_32b[0:0] $1\SHIFT_ROT_dec30_is_32b[0:0] + attribute \src "issuer_ls180.v:17906.5-17906.29" + switch \initial + attribute \src "issuer_ls180.v:17906.9-17906.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0100 + assign { } { } + assign $1\SHIFT_ROT_dec30_is_32b[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0101 + assign { } { } + assign $1\SHIFT_ROT_dec30_is_32b[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $1\SHIFT_ROT_dec30_is_32b[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0001 + assign { } { } + assign $1\SHIFT_ROT_dec30_is_32b[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0010 + assign { } { } + assign $1\SHIFT_ROT_dec30_is_32b[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0011 + assign { } { } + assign $1\SHIFT_ROT_dec30_is_32b[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\SHIFT_ROT_dec30_is_32b[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $1\SHIFT_ROT_dec30_is_32b[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\SHIFT_ROT_dec30_is_32b[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'1001 + assign { } { } + assign $1\SHIFT_ROT_dec30_is_32b[0:0] 1'0 + case + assign $1\SHIFT_ROT_dec30_is_32b[0:0] 1'0 + end + sync always + update \SHIFT_ROT_dec30_is_32b $0\SHIFT_ROT_dec30_is_32b[0:0] + end + connect \opcode_switch \opcode_in [4:1] +end +attribute \src "issuer_ls180.v:17947.1-18751.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.dec_SHIFT_ROT.dec.SHIFT_ROT_dec31" +attribute \generator "nMigen" +module \SHIFT_ROT_dec31 + attribute \src "issuer_ls180.v:18714.3-18729.6" + wire width 3 $0\SHIFT_ROT_dec31_cr_in[2:0] + attribute \src "issuer_ls180.v:18730.3-18745.6" + wire width 3 $0\SHIFT_ROT_dec31_cr_out[2:0] + attribute \src "issuer_ls180.v:18602.3-18617.6" + wire width 2 $0\SHIFT_ROT_dec31_cry_in[1:0] + attribute \src "issuer_ls180.v:18618.3-18633.6" + wire $0\SHIFT_ROT_dec31_cry_out[0:0] + attribute \src "issuer_ls180.v:18666.3-18681.6" + wire width 12 $0\SHIFT_ROT_dec31_function_unit[11:0] + attribute \src "issuer_ls180.v:18698.3-18713.6" + wire width 4 $0\SHIFT_ROT_dec31_in2_sel[3:0] + attribute \src "issuer_ls180.v:18682.3-18697.6" + wire width 7 $0\SHIFT_ROT_dec31_internal_op[6:0] + attribute \src "issuer_ls180.v:18634.3-18649.6" + wire $0\SHIFT_ROT_dec31_is_32b[0:0] + attribute \src "issuer_ls180.v:18586.3-18601.6" + wire width 2 $0\SHIFT_ROT_dec31_rc_sel[1:0] + attribute \src "issuer_ls180.v:18650.3-18665.6" + wire $0\SHIFT_ROT_dec31_sgn[0:0] + attribute \src "issuer_ls180.v:17948.7-17948.20" + wire $0\initial[0:0] + attribute \src "issuer_ls180.v:18714.3-18729.6" + wire width 3 $1\SHIFT_ROT_dec31_cr_in[2:0] + attribute \src "issuer_ls180.v:18730.3-18745.6" + wire width 3 $1\SHIFT_ROT_dec31_cr_out[2:0] + attribute \src "issuer_ls180.v:18602.3-18617.6" + wire width 2 $1\SHIFT_ROT_dec31_cry_in[1:0] + attribute \src "issuer_ls180.v:18618.3-18633.6" + wire $1\SHIFT_ROT_dec31_cry_out[0:0] + attribute \src "issuer_ls180.v:18666.3-18681.6" + wire width 12 $1\SHIFT_ROT_dec31_function_unit[11:0] + attribute \src "issuer_ls180.v:18698.3-18713.6" + wire width 4 $1\SHIFT_ROT_dec31_in2_sel[3:0] + attribute \src "issuer_ls180.v:18682.3-18697.6" + wire width 7 $1\SHIFT_ROT_dec31_internal_op[6:0] + attribute \src "issuer_ls180.v:18634.3-18649.6" + wire $1\SHIFT_ROT_dec31_is_32b[0:0] + attribute \src "issuer_ls180.v:18586.3-18601.6" + wire width 2 $1\SHIFT_ROT_dec31_rc_sel[1:0] + attribute \src "issuer_ls180.v:18650.3-18665.6" + wire $1\SHIFT_ROT_dec31_sgn[0:0] + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 4 \SHIFT_ROT_dec31_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 5 \SHIFT_ROT_dec31_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 7 \SHIFT_ROT_dec31_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 8 \SHIFT_ROT_dec31_cry_out + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 \SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 \SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_cry_out + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 12 \SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_function_unit + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 \SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_in2_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 7 \SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_is_32b + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + wire width 32 \SHIFT_ROT_dec31_dec_sub24_opcode_in + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 \SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 \SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_cry_out + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 12 \SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_function_unit + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 \SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_in2_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 7 \SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_is_32b + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + wire width 32 \SHIFT_ROT_dec31_dec_sub26_opcode_in + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 \SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 \SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_cry_out + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 12 \SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_function_unit + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 \SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_in2_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 7 \SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_is_32b + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + wire width 32 \SHIFT_ROT_dec31_dec_sub27_opcode_in + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 12 output 1 \SHIFT_ROT_dec31_function_unit + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 output 3 \SHIFT_ROT_dec31_in2_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 7 output 2 \SHIFT_ROT_dec31_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 9 \SHIFT_ROT_dec31_is_32b + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 6 \SHIFT_ROT_dec31_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 10 \SHIFT_ROT_dec31_sgn + attribute \src "issuer_ls180.v:17948.7-17948.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:326" + wire width 5 \opc_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + wire width 32 input 11 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:320" + wire width 10 \opcode_switch + attribute \module_not_derived 1 + attribute \src "issuer_ls180.v:18547.29-18559.4" + cell \SHIFT_ROT_dec31_dec_sub24 \SHIFT_ROT_dec31_dec_sub24 + connect \SHIFT_ROT_dec31_dec_sub24_cr_in \SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_cr_in + connect \SHIFT_ROT_dec31_dec_sub24_cr_out \SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_cr_out + connect \SHIFT_ROT_dec31_dec_sub24_cry_in \SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_cry_in + connect \SHIFT_ROT_dec31_dec_sub24_cry_out \SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_cry_out + connect \SHIFT_ROT_dec31_dec_sub24_function_unit \SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_function_unit + connect \SHIFT_ROT_dec31_dec_sub24_in2_sel \SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_in2_sel + connect \SHIFT_ROT_dec31_dec_sub24_internal_op \SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_internal_op + connect \SHIFT_ROT_dec31_dec_sub24_is_32b \SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_is_32b + connect \SHIFT_ROT_dec31_dec_sub24_rc_sel \SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_rc_sel + connect \SHIFT_ROT_dec31_dec_sub24_sgn \SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_sgn + connect \opcode_in \SHIFT_ROT_dec31_dec_sub24_opcode_in + end + attribute \module_not_derived 1 + attribute \src "issuer_ls180.v:18560.29-18572.4" + cell \SHIFT_ROT_dec31_dec_sub26 \SHIFT_ROT_dec31_dec_sub26 + connect \SHIFT_ROT_dec31_dec_sub26_cr_in \SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_cr_in + connect \SHIFT_ROT_dec31_dec_sub26_cr_out \SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_cr_out + connect \SHIFT_ROT_dec31_dec_sub26_cry_in \SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_cry_in + connect \SHIFT_ROT_dec31_dec_sub26_cry_out \SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_cry_out + connect \SHIFT_ROT_dec31_dec_sub26_function_unit \SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_function_unit + connect \SHIFT_ROT_dec31_dec_sub26_in2_sel \SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_in2_sel + connect \SHIFT_ROT_dec31_dec_sub26_internal_op \SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_internal_op + connect \SHIFT_ROT_dec31_dec_sub26_is_32b \SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_is_32b + connect \SHIFT_ROT_dec31_dec_sub26_rc_sel \SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_rc_sel + connect \SHIFT_ROT_dec31_dec_sub26_sgn \SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_sgn + connect \opcode_in \SHIFT_ROT_dec31_dec_sub26_opcode_in + end + attribute \module_not_derived 1 + attribute \src "issuer_ls180.v:18573.29-18585.4" + cell \SHIFT_ROT_dec31_dec_sub27 \SHIFT_ROT_dec31_dec_sub27 + connect \SHIFT_ROT_dec31_dec_sub27_cr_in \SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_cr_in + connect \SHIFT_ROT_dec31_dec_sub27_cr_out \SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_cr_out + connect \SHIFT_ROT_dec31_dec_sub27_cry_in \SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_cry_in + connect \SHIFT_ROT_dec31_dec_sub27_cry_out \SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_cry_out + connect \SHIFT_ROT_dec31_dec_sub27_function_unit \SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_function_unit + connect \SHIFT_ROT_dec31_dec_sub27_in2_sel \SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_in2_sel + connect \SHIFT_ROT_dec31_dec_sub27_internal_op \SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_internal_op + connect \SHIFT_ROT_dec31_dec_sub27_is_32b \SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_is_32b + connect \SHIFT_ROT_dec31_dec_sub27_rc_sel \SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_rc_sel + connect \SHIFT_ROT_dec31_dec_sub27_sgn \SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_sgn + connect \opcode_in \SHIFT_ROT_dec31_dec_sub27_opcode_in + end + attribute \src "issuer_ls180.v:17948.7-17948.20" + process $proc$issuer_ls180.v:17948$387 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "issuer_ls180.v:18586.3-18601.6" + process $proc$issuer_ls180.v:18586$377 + assign { } { } + assign { } { } + assign $0\SHIFT_ROT_dec31_rc_sel[1:0] $1\SHIFT_ROT_dec31_rc_sel[1:0] + attribute \src "issuer_ls180.v:18587.5-18587.29" + switch \initial + attribute \src "issuer_ls180.v:18587.9-18587.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opc_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\SHIFT_ROT_dec31_rc_sel[1:0] \SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_rc_sel + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\SHIFT_ROT_dec31_rc_sel[1:0] \SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_rc_sel + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\SHIFT_ROT_dec31_rc_sel[1:0] \SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_rc_sel + case + assign $1\SHIFT_ROT_dec31_rc_sel[1:0] 2'00 + end + sync always + update \SHIFT_ROT_dec31_rc_sel $0\SHIFT_ROT_dec31_rc_sel[1:0] + end + attribute \src "issuer_ls180.v:18602.3-18617.6" + process $proc$issuer_ls180.v:18602$378 + assign { } { } + assign { } { } + assign $0\SHIFT_ROT_dec31_cry_in[1:0] $1\SHIFT_ROT_dec31_cry_in[1:0] + attribute \src "issuer_ls180.v:18603.5-18603.29" + switch \initial + attribute \src "issuer_ls180.v:18603.9-18603.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opc_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\SHIFT_ROT_dec31_cry_in[1:0] \SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_cry_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\SHIFT_ROT_dec31_cry_in[1:0] \SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_cry_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\SHIFT_ROT_dec31_cry_in[1:0] \SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_cry_in + case + assign $1\SHIFT_ROT_dec31_cry_in[1:0] 2'00 + end + sync always + update \SHIFT_ROT_dec31_cry_in $0\SHIFT_ROT_dec31_cry_in[1:0] + end + attribute \src "issuer_ls180.v:18618.3-18633.6" + process $proc$issuer_ls180.v:18618$379 + assign { } { } + assign { } { } + assign $0\SHIFT_ROT_dec31_cry_out[0:0] $1\SHIFT_ROT_dec31_cry_out[0:0] + attribute \src "issuer_ls180.v:18619.5-18619.29" + switch \initial + attribute \src "issuer_ls180.v:18619.9-18619.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opc_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\SHIFT_ROT_dec31_cry_out[0:0] \SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_cry_out + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\SHIFT_ROT_dec31_cry_out[0:0] \SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_cry_out + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\SHIFT_ROT_dec31_cry_out[0:0] \SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_cry_out + case + assign $1\SHIFT_ROT_dec31_cry_out[0:0] 1'0 + end + sync always + update \SHIFT_ROT_dec31_cry_out $0\SHIFT_ROT_dec31_cry_out[0:0] + end + attribute \src "issuer_ls180.v:18634.3-18649.6" + process $proc$issuer_ls180.v:18634$380 + assign { } { } + assign { } { } + assign $0\SHIFT_ROT_dec31_is_32b[0:0] $1\SHIFT_ROT_dec31_is_32b[0:0] + attribute \src "issuer_ls180.v:18635.5-18635.29" + switch \initial + attribute \src "issuer_ls180.v:18635.9-18635.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opc_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\SHIFT_ROT_dec31_is_32b[0:0] \SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_is_32b + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\SHIFT_ROT_dec31_is_32b[0:0] \SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_is_32b + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\SHIFT_ROT_dec31_is_32b[0:0] \SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_is_32b + case + assign $1\SHIFT_ROT_dec31_is_32b[0:0] 1'0 + end + sync always + update \SHIFT_ROT_dec31_is_32b $0\SHIFT_ROT_dec31_is_32b[0:0] + end + attribute \src "issuer_ls180.v:18650.3-18665.6" + process $proc$issuer_ls180.v:18650$381 + assign { } { } + assign { } { } + assign $0\SHIFT_ROT_dec31_sgn[0:0] $1\SHIFT_ROT_dec31_sgn[0:0] + attribute \src "issuer_ls180.v:18651.5-18651.29" + switch \initial + attribute \src "issuer_ls180.v:18651.9-18651.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opc_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\SHIFT_ROT_dec31_sgn[0:0] \SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_sgn + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\SHIFT_ROT_dec31_sgn[0:0] \SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_sgn + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\SHIFT_ROT_dec31_sgn[0:0] \SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_sgn + case + assign $1\SHIFT_ROT_dec31_sgn[0:0] 1'0 + end + sync always + update \SHIFT_ROT_dec31_sgn $0\SHIFT_ROT_dec31_sgn[0:0] + end + attribute \src "issuer_ls180.v:18666.3-18681.6" + process $proc$issuer_ls180.v:18666$382 + assign { } { } + assign { } { } + assign $0\SHIFT_ROT_dec31_function_unit[11:0] $1\SHIFT_ROT_dec31_function_unit[11:0] + attribute \src "issuer_ls180.v:18667.5-18667.29" + switch \initial + attribute \src "issuer_ls180.v:18667.9-18667.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opc_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\SHIFT_ROT_dec31_function_unit[11:0] \SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_function_unit + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\SHIFT_ROT_dec31_function_unit[11:0] \SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_function_unit + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\SHIFT_ROT_dec31_function_unit[11:0] \SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_function_unit + case + assign $1\SHIFT_ROT_dec31_function_unit[11:0] 12'000000000000 + end + sync always + update \SHIFT_ROT_dec31_function_unit $0\SHIFT_ROT_dec31_function_unit[11:0] + end + attribute \src "issuer_ls180.v:18682.3-18697.6" + process $proc$issuer_ls180.v:18682$383 + assign { } { } + assign { } { } + assign $0\SHIFT_ROT_dec31_internal_op[6:0] $1\SHIFT_ROT_dec31_internal_op[6:0] + attribute \src "issuer_ls180.v:18683.5-18683.29" + switch \initial + attribute \src "issuer_ls180.v:18683.9-18683.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opc_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\SHIFT_ROT_dec31_internal_op[6:0] \SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_internal_op + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\SHIFT_ROT_dec31_internal_op[6:0] \SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_internal_op + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\SHIFT_ROT_dec31_internal_op[6:0] \SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_internal_op + case + assign $1\SHIFT_ROT_dec31_internal_op[6:0] 7'0000000 + end + sync always + update \SHIFT_ROT_dec31_internal_op $0\SHIFT_ROT_dec31_internal_op[6:0] + end + attribute \src "issuer_ls180.v:18698.3-18713.6" + process $proc$issuer_ls180.v:18698$384 + assign { } { } + assign { } { } + assign $0\SHIFT_ROT_dec31_in2_sel[3:0] $1\SHIFT_ROT_dec31_in2_sel[3:0] + attribute \src "issuer_ls180.v:18699.5-18699.29" + switch \initial + attribute \src "issuer_ls180.v:18699.9-18699.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opc_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\SHIFT_ROT_dec31_in2_sel[3:0] \SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_in2_sel + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\SHIFT_ROT_dec31_in2_sel[3:0] \SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_in2_sel + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\SHIFT_ROT_dec31_in2_sel[3:0] \SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_in2_sel + case + assign $1\SHIFT_ROT_dec31_in2_sel[3:0] 4'0000 + end + sync always + update \SHIFT_ROT_dec31_in2_sel $0\SHIFT_ROT_dec31_in2_sel[3:0] + end + attribute \src "issuer_ls180.v:18714.3-18729.6" + process $proc$issuer_ls180.v:18714$385 + assign { } { } + assign { } { } + assign $0\SHIFT_ROT_dec31_cr_in[2:0] $1\SHIFT_ROT_dec31_cr_in[2:0] + attribute \src "issuer_ls180.v:18715.5-18715.29" + switch \initial + attribute \src "issuer_ls180.v:18715.9-18715.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opc_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\SHIFT_ROT_dec31_cr_in[2:0] \SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_cr_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\SHIFT_ROT_dec31_cr_in[2:0] \SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_cr_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\SHIFT_ROT_dec31_cr_in[2:0] \SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_cr_in + case + assign $1\SHIFT_ROT_dec31_cr_in[2:0] 3'000 + end + sync always + update \SHIFT_ROT_dec31_cr_in $0\SHIFT_ROT_dec31_cr_in[2:0] + end + attribute \src "issuer_ls180.v:18730.3-18745.6" + process $proc$issuer_ls180.v:18730$386 + assign { } { } + assign { } { } + assign $0\SHIFT_ROT_dec31_cr_out[2:0] $1\SHIFT_ROT_dec31_cr_out[2:0] + attribute \src "issuer_ls180.v:18731.5-18731.29" + switch \initial + attribute \src "issuer_ls180.v:18731.9-18731.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opc_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\SHIFT_ROT_dec31_cr_out[2:0] \SHIFT_ROT_dec31_dec_sub26_SHIFT_ROT_dec31_dec_sub26_cr_out + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\SHIFT_ROT_dec31_cr_out[2:0] \SHIFT_ROT_dec31_dec_sub27_SHIFT_ROT_dec31_dec_sub27_cr_out + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\SHIFT_ROT_dec31_cr_out[2:0] \SHIFT_ROT_dec31_dec_sub24_SHIFT_ROT_dec31_dec_sub24_cr_out + case + assign $1\SHIFT_ROT_dec31_cr_out[2:0] 3'000 + end + sync always + update \SHIFT_ROT_dec31_cr_out $0\SHIFT_ROT_dec31_cr_out[2:0] + end + connect \SHIFT_ROT_dec31_dec_sub24_opcode_in \opcode_in + connect \SHIFT_ROT_dec31_dec_sub27_opcode_in \opcode_in + connect \SHIFT_ROT_dec31_dec_sub26_opcode_in \opcode_in + connect \opc_in \opcode_switch [4:0] + connect \opcode_switch \opcode_in [10:1] +end +attribute \src "issuer_ls180.v:18755.1-19106.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.dec_SHIFT_ROT.dec.SHIFT_ROT_dec31.SHIFT_ROT_dec31_dec_sub24" +attribute \generator "nMigen" +module \SHIFT_ROT_dec31_dec_sub24 + attribute \src "issuer_ls180.v:18991.3-19009.6" + wire width 3 $0\SHIFT_ROT_dec31_dec_sub24_cr_in[2:0] + attribute \src "issuer_ls180.v:19010.3-19028.6" + wire width 3 $0\SHIFT_ROT_dec31_dec_sub24_cr_out[2:0] + attribute \src "issuer_ls180.v:19048.3-19066.6" + wire width 2 $0\SHIFT_ROT_dec31_dec_sub24_cry_in[1:0] + attribute \src "issuer_ls180.v:19067.3-19085.6" + wire $0\SHIFT_ROT_dec31_dec_sub24_cry_out[0:0] + attribute \src "issuer_ls180.v:18915.3-18933.6" + wire width 12 $0\SHIFT_ROT_dec31_dec_sub24_function_unit[11:0] + attribute \src "issuer_ls180.v:18972.3-18990.6" + wire width 4 $0\SHIFT_ROT_dec31_dec_sub24_in2_sel[3:0] + attribute \src "issuer_ls180.v:18953.3-18971.6" + wire width 7 $0\SHIFT_ROT_dec31_dec_sub24_internal_op[6:0] + attribute \src "issuer_ls180.v:19086.3-19104.6" + wire $0\SHIFT_ROT_dec31_dec_sub24_is_32b[0:0] + attribute \src "issuer_ls180.v:19029.3-19047.6" + wire width 2 $0\SHIFT_ROT_dec31_dec_sub24_rc_sel[1:0] + attribute \src "issuer_ls180.v:18934.3-18952.6" + wire $0\SHIFT_ROT_dec31_dec_sub24_sgn[0:0] + attribute \src "issuer_ls180.v:18756.7-18756.20" + wire $0\initial[0:0] + attribute \src "issuer_ls180.v:18991.3-19009.6" + wire width 3 $1\SHIFT_ROT_dec31_dec_sub24_cr_in[2:0] + attribute \src "issuer_ls180.v:19010.3-19028.6" + wire width 3 $1\SHIFT_ROT_dec31_dec_sub24_cr_out[2:0] + attribute \src "issuer_ls180.v:19048.3-19066.6" + wire width 2 $1\SHIFT_ROT_dec31_dec_sub24_cry_in[1:0] + attribute \src "issuer_ls180.v:19067.3-19085.6" + wire $1\SHIFT_ROT_dec31_dec_sub24_cry_out[0:0] + attribute \src "issuer_ls180.v:18915.3-18933.6" + wire width 12 $1\SHIFT_ROT_dec31_dec_sub24_function_unit[11:0] + attribute \src "issuer_ls180.v:18972.3-18990.6" + wire width 4 $1\SHIFT_ROT_dec31_dec_sub24_in2_sel[3:0] + attribute \src "issuer_ls180.v:18953.3-18971.6" + wire width 7 $1\SHIFT_ROT_dec31_dec_sub24_internal_op[6:0] + attribute \src "issuer_ls180.v:19086.3-19104.6" + wire $1\SHIFT_ROT_dec31_dec_sub24_is_32b[0:0] + attribute \src "issuer_ls180.v:19029.3-19047.6" + wire width 2 $1\SHIFT_ROT_dec31_dec_sub24_rc_sel[1:0] + attribute \src "issuer_ls180.v:18934.3-18952.6" + wire $1\SHIFT_ROT_dec31_dec_sub24_sgn[0:0] + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 4 \SHIFT_ROT_dec31_dec_sub24_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 5 \SHIFT_ROT_dec31_dec_sub24_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 7 \SHIFT_ROT_dec31_dec_sub24_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 8 \SHIFT_ROT_dec31_dec_sub24_cry_out + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 12 output 1 \SHIFT_ROT_dec31_dec_sub24_function_unit + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 output 3 \SHIFT_ROT_dec31_dec_sub24_in2_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 7 output 2 \SHIFT_ROT_dec31_dec_sub24_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 9 \SHIFT_ROT_dec31_dec_sub24_is_32b + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 6 \SHIFT_ROT_dec31_dec_sub24_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 10 \SHIFT_ROT_dec31_dec_sub24_sgn + attribute \src "issuer_ls180.v:18756.7-18756.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + wire width 32 input 11 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:320" + wire width 5 \opcode_switch + attribute \src "issuer_ls180.v:18756.7-18756.20" + process $proc$issuer_ls180.v:18756$398 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "issuer_ls180.v:18915.3-18933.6" + process $proc$issuer_ls180.v:18915$388 + assign { } { } + assign { } { } + assign $0\SHIFT_ROT_dec31_dec_sub24_function_unit[11:0] $1\SHIFT_ROT_dec31_dec_sub24_function_unit[11:0] + attribute \src "issuer_ls180.v:18916.5-18916.29" + switch \initial + attribute \src "issuer_ls180.v:18916.9-18916.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub24_function_unit[11:0] 12'000000001000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub24_function_unit[11:0] 12'000000001000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub24_function_unit[11:0] 12'000000001000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub24_function_unit[11:0] 12'000000001000 + case + assign $1\SHIFT_ROT_dec31_dec_sub24_function_unit[11:0] 12'000000000000 + end + sync always + update \SHIFT_ROT_dec31_dec_sub24_function_unit $0\SHIFT_ROT_dec31_dec_sub24_function_unit[11:0] + end + attribute \src "issuer_ls180.v:18934.3-18952.6" + process $proc$issuer_ls180.v:18934$389 + assign { } { } + assign { } { } + assign $0\SHIFT_ROT_dec31_dec_sub24_sgn[0:0] $1\SHIFT_ROT_dec31_dec_sub24_sgn[0:0] + attribute \src "issuer_ls180.v:18935.5-18935.29" + switch \initial + attribute \src "issuer_ls180.v:18935.9-18935.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub24_sgn[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub24_sgn[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub24_sgn[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub24_sgn[0:0] 1'0 + case + assign $1\SHIFT_ROT_dec31_dec_sub24_sgn[0:0] 1'0 + end + sync always + update \SHIFT_ROT_dec31_dec_sub24_sgn $0\SHIFT_ROT_dec31_dec_sub24_sgn[0:0] + end + attribute \src "issuer_ls180.v:18953.3-18971.6" + process $proc$issuer_ls180.v:18953$390 + assign { } { } + assign { } { } + assign $0\SHIFT_ROT_dec31_dec_sub24_internal_op[6:0] $1\SHIFT_ROT_dec31_dec_sub24_internal_op[6:0] + attribute \src "issuer_ls180.v:18954.5-18954.29" + switch \initial + attribute \src "issuer_ls180.v:18954.9-18954.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub24_internal_op[6:0] 7'0111100 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub24_internal_op[6:0] 7'0111101 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub24_internal_op[6:0] 7'0111101 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub24_internal_op[6:0] 7'0111101 + case + assign $1\SHIFT_ROT_dec31_dec_sub24_internal_op[6:0] 7'0000000 + end + sync always + update \SHIFT_ROT_dec31_dec_sub24_internal_op $0\SHIFT_ROT_dec31_dec_sub24_internal_op[6:0] + end + attribute \src "issuer_ls180.v:18972.3-18990.6" + process $proc$issuer_ls180.v:18972$391 + assign { } { } + assign { } { } + assign $0\SHIFT_ROT_dec31_dec_sub24_in2_sel[3:0] $1\SHIFT_ROT_dec31_dec_sub24_in2_sel[3:0] + attribute \src "issuer_ls180.v:18973.5-18973.29" + switch \initial + attribute \src "issuer_ls180.v:18973.9-18973.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub24_in2_sel[3:0] 4'0001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub24_in2_sel[3:0] 4'0001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub24_in2_sel[3:0] 4'1011 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub24_in2_sel[3:0] 4'0001 + case + assign $1\SHIFT_ROT_dec31_dec_sub24_in2_sel[3:0] 4'0000 + end + sync always + update \SHIFT_ROT_dec31_dec_sub24_in2_sel $0\SHIFT_ROT_dec31_dec_sub24_in2_sel[3:0] + end + attribute \src "issuer_ls180.v:18991.3-19009.6" + process $proc$issuer_ls180.v:18991$392 + assign { } { } + assign { } { } + assign $0\SHIFT_ROT_dec31_dec_sub24_cr_in[2:0] $1\SHIFT_ROT_dec31_dec_sub24_cr_in[2:0] + attribute \src "issuer_ls180.v:18992.5-18992.29" + switch \initial + attribute \src "issuer_ls180.v:18992.9-18992.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub24_cr_in[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub24_cr_in[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub24_cr_in[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub24_cr_in[2:0] 3'000 + case + assign $1\SHIFT_ROT_dec31_dec_sub24_cr_in[2:0] 3'000 + end + sync always + update \SHIFT_ROT_dec31_dec_sub24_cr_in $0\SHIFT_ROT_dec31_dec_sub24_cr_in[2:0] + end + attribute \src "issuer_ls180.v:19010.3-19028.6" + process $proc$issuer_ls180.v:19010$393 + assign { } { } + assign { } { } + assign $0\SHIFT_ROT_dec31_dec_sub24_cr_out[2:0] $1\SHIFT_ROT_dec31_dec_sub24_cr_out[2:0] + attribute \src "issuer_ls180.v:19011.5-19011.29" + switch \initial + attribute \src "issuer_ls180.v:19011.9-19011.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub24_cr_out[2:0] 3'001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub24_cr_out[2:0] 3'001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub24_cr_out[2:0] 3'001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub24_cr_out[2:0] 3'001 + case + assign $1\SHIFT_ROT_dec31_dec_sub24_cr_out[2:0] 3'000 + end + sync always + update \SHIFT_ROT_dec31_dec_sub24_cr_out $0\SHIFT_ROT_dec31_dec_sub24_cr_out[2:0] + end + attribute \src "issuer_ls180.v:19029.3-19047.6" + process $proc$issuer_ls180.v:19029$394 + assign { } { } + assign { } { } + assign $0\SHIFT_ROT_dec31_dec_sub24_rc_sel[1:0] $1\SHIFT_ROT_dec31_dec_sub24_rc_sel[1:0] + attribute \src "issuer_ls180.v:19030.5-19030.29" + switch \initial + attribute \src "issuer_ls180.v:19030.9-19030.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub24_rc_sel[1:0] 2'10 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub24_rc_sel[1:0] 2'10 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub24_rc_sel[1:0] 2'10 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub24_rc_sel[1:0] 2'10 + case + assign $1\SHIFT_ROT_dec31_dec_sub24_rc_sel[1:0] 2'00 + end + sync always + update \SHIFT_ROT_dec31_dec_sub24_rc_sel $0\SHIFT_ROT_dec31_dec_sub24_rc_sel[1:0] + end + attribute \src "issuer_ls180.v:19048.3-19066.6" + process $proc$issuer_ls180.v:19048$395 + assign { } { } + assign { } { } + assign $0\SHIFT_ROT_dec31_dec_sub24_cry_in[1:0] $1\SHIFT_ROT_dec31_dec_sub24_cry_in[1:0] + attribute \src "issuer_ls180.v:19049.5-19049.29" + switch \initial + attribute \src "issuer_ls180.v:19049.9-19049.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub24_cry_in[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub24_cry_in[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub24_cry_in[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub24_cry_in[1:0] 2'00 + case + assign $1\SHIFT_ROT_dec31_dec_sub24_cry_in[1:0] 2'00 + end + sync always + update \SHIFT_ROT_dec31_dec_sub24_cry_in $0\SHIFT_ROT_dec31_dec_sub24_cry_in[1:0] + end + attribute \src "issuer_ls180.v:19067.3-19085.6" + process $proc$issuer_ls180.v:19067$396 + assign { } { } + assign { } { } + assign $0\SHIFT_ROT_dec31_dec_sub24_cry_out[0:0] $1\SHIFT_ROT_dec31_dec_sub24_cry_out[0:0] + attribute \src "issuer_ls180.v:19068.5-19068.29" + switch \initial + attribute \src "issuer_ls180.v:19068.9-19068.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub24_cry_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub24_cry_out[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub24_cry_out[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub24_cry_out[0:0] 1'0 + case + assign $1\SHIFT_ROT_dec31_dec_sub24_cry_out[0:0] 1'0 + end + sync always + update \SHIFT_ROT_dec31_dec_sub24_cry_out $0\SHIFT_ROT_dec31_dec_sub24_cry_out[0:0] + end + attribute \src "issuer_ls180.v:19086.3-19104.6" + process $proc$issuer_ls180.v:19086$397 + assign { } { } + assign { } { } + assign $0\SHIFT_ROT_dec31_dec_sub24_is_32b[0:0] $1\SHIFT_ROT_dec31_dec_sub24_is_32b[0:0] + attribute \src "issuer_ls180.v:19087.5-19087.29" + switch \initial + attribute \src "issuer_ls180.v:19087.9-19087.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub24_is_32b[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub24_is_32b[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub24_is_32b[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub24_is_32b[0:0] 1'1 + case + assign $1\SHIFT_ROT_dec31_dec_sub24_is_32b[0:0] 1'0 + end + sync always + update \SHIFT_ROT_dec31_dec_sub24_is_32b $0\SHIFT_ROT_dec31_dec_sub24_is_32b[0:0] + end + connect \opcode_switch \opcode_in [10:6] +end +attribute \src "issuer_ls180.v:19110.1-19431.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.dec_SHIFT_ROT.dec.SHIFT_ROT_dec31.SHIFT_ROT_dec31_dec_sub26" +attribute \generator "nMigen" +module \SHIFT_ROT_dec31_dec_sub26 + attribute \src "issuer_ls180.v:19334.3-19349.6" + wire width 3 $0\SHIFT_ROT_dec31_dec_sub26_cr_in[2:0] + attribute \src "issuer_ls180.v:19350.3-19365.6" + wire width 3 $0\SHIFT_ROT_dec31_dec_sub26_cr_out[2:0] + attribute \src "issuer_ls180.v:19382.3-19397.6" + wire width 2 $0\SHIFT_ROT_dec31_dec_sub26_cry_in[1:0] + attribute \src "issuer_ls180.v:19398.3-19413.6" + wire $0\SHIFT_ROT_dec31_dec_sub26_cry_out[0:0] + attribute \src "issuer_ls180.v:19270.3-19285.6" + wire width 12 $0\SHIFT_ROT_dec31_dec_sub26_function_unit[11:0] + attribute \src "issuer_ls180.v:19318.3-19333.6" + wire width 4 $0\SHIFT_ROT_dec31_dec_sub26_in2_sel[3:0] + attribute \src "issuer_ls180.v:19302.3-19317.6" + wire width 7 $0\SHIFT_ROT_dec31_dec_sub26_internal_op[6:0] + attribute \src "issuer_ls180.v:19414.3-19429.6" + wire $0\SHIFT_ROT_dec31_dec_sub26_is_32b[0:0] + attribute \src "issuer_ls180.v:19366.3-19381.6" + wire width 2 $0\SHIFT_ROT_dec31_dec_sub26_rc_sel[1:0] + attribute \src "issuer_ls180.v:19286.3-19301.6" + wire $0\SHIFT_ROT_dec31_dec_sub26_sgn[0:0] + attribute \src "issuer_ls180.v:19111.7-19111.20" + wire $0\initial[0:0] + attribute \src "issuer_ls180.v:19334.3-19349.6" + wire width 3 $1\SHIFT_ROT_dec31_dec_sub26_cr_in[2:0] + attribute \src "issuer_ls180.v:19350.3-19365.6" + wire width 3 $1\SHIFT_ROT_dec31_dec_sub26_cr_out[2:0] + attribute \src "issuer_ls180.v:19382.3-19397.6" + wire width 2 $1\SHIFT_ROT_dec31_dec_sub26_cry_in[1:0] + attribute \src "issuer_ls180.v:19398.3-19413.6" + wire $1\SHIFT_ROT_dec31_dec_sub26_cry_out[0:0] + attribute \src "issuer_ls180.v:19270.3-19285.6" + wire width 12 $1\SHIFT_ROT_dec31_dec_sub26_function_unit[11:0] + attribute \src "issuer_ls180.v:19318.3-19333.6" + wire width 4 $1\SHIFT_ROT_dec31_dec_sub26_in2_sel[3:0] + attribute \src "issuer_ls180.v:19302.3-19317.6" + wire width 7 $1\SHIFT_ROT_dec31_dec_sub26_internal_op[6:0] + attribute \src "issuer_ls180.v:19414.3-19429.6" + wire $1\SHIFT_ROT_dec31_dec_sub26_is_32b[0:0] + attribute \src "issuer_ls180.v:19366.3-19381.6" + wire width 2 $1\SHIFT_ROT_dec31_dec_sub26_rc_sel[1:0] + attribute \src "issuer_ls180.v:19286.3-19301.6" + wire $1\SHIFT_ROT_dec31_dec_sub26_sgn[0:0] + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 4 \SHIFT_ROT_dec31_dec_sub26_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 5 \SHIFT_ROT_dec31_dec_sub26_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 7 \SHIFT_ROT_dec31_dec_sub26_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 8 \SHIFT_ROT_dec31_dec_sub26_cry_out + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 12 output 1 \SHIFT_ROT_dec31_dec_sub26_function_unit + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 output 3 \SHIFT_ROT_dec31_dec_sub26_in2_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 7 output 2 \SHIFT_ROT_dec31_dec_sub26_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 9 \SHIFT_ROT_dec31_dec_sub26_is_32b + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 6 \SHIFT_ROT_dec31_dec_sub26_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 10 \SHIFT_ROT_dec31_dec_sub26_sgn + attribute \src "issuer_ls180.v:19111.7-19111.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + wire width 32 input 11 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:320" + wire width 5 \opcode_switch + attribute \src "issuer_ls180.v:19111.7-19111.20" + process $proc$issuer_ls180.v:19111$409 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "issuer_ls180.v:19270.3-19285.6" + process $proc$issuer_ls180.v:19270$399 + assign { } { } + assign { } { } + assign $0\SHIFT_ROT_dec31_dec_sub26_function_unit[11:0] $1\SHIFT_ROT_dec31_dec_sub26_function_unit[11:0] + attribute \src "issuer_ls180.v:19271.5-19271.29" + switch \initial + attribute \src "issuer_ls180.v:19271.9-19271.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub26_function_unit[11:0] 12'000000001000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub26_function_unit[11:0] 12'000000001000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub26_function_unit[11:0] 12'000000001000 + case + assign $1\SHIFT_ROT_dec31_dec_sub26_function_unit[11:0] 12'000000000000 + end + sync always + update \SHIFT_ROT_dec31_dec_sub26_function_unit $0\SHIFT_ROT_dec31_dec_sub26_function_unit[11:0] + end + attribute \src "issuer_ls180.v:19286.3-19301.6" + process $proc$issuer_ls180.v:19286$400 + assign { } { } + assign { } { } + assign $0\SHIFT_ROT_dec31_dec_sub26_sgn[0:0] $1\SHIFT_ROT_dec31_dec_sub26_sgn[0:0] + attribute \src "issuer_ls180.v:19287.5-19287.29" + switch \initial + attribute \src "issuer_ls180.v:19287.9-19287.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub26_sgn[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub26_sgn[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub26_sgn[0:0] 1'1 + case + assign $1\SHIFT_ROT_dec31_dec_sub26_sgn[0:0] 1'0 + end + sync always + update \SHIFT_ROT_dec31_dec_sub26_sgn $0\SHIFT_ROT_dec31_dec_sub26_sgn[0:0] + end + attribute \src "issuer_ls180.v:19302.3-19317.6" + process $proc$issuer_ls180.v:19302$401 + assign { } { } + assign { } { } + assign $0\SHIFT_ROT_dec31_dec_sub26_internal_op[6:0] $1\SHIFT_ROT_dec31_dec_sub26_internal_op[6:0] + attribute \src "issuer_ls180.v:19303.5-19303.29" + switch \initial + attribute \src "issuer_ls180.v:19303.9-19303.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub26_internal_op[6:0] 7'0100000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub26_internal_op[6:0] 7'0111101 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub26_internal_op[6:0] 7'0111101 + case + assign $1\SHIFT_ROT_dec31_dec_sub26_internal_op[6:0] 7'0000000 + end + sync always + update \SHIFT_ROT_dec31_dec_sub26_internal_op $0\SHIFT_ROT_dec31_dec_sub26_internal_op[6:0] + end + attribute \src "issuer_ls180.v:19318.3-19333.6" + process $proc$issuer_ls180.v:19318$402 + assign { } { } + assign { } { } + assign $0\SHIFT_ROT_dec31_dec_sub26_in2_sel[3:0] $1\SHIFT_ROT_dec31_dec_sub26_in2_sel[3:0] + attribute \src "issuer_ls180.v:19319.5-19319.29" + switch \initial + attribute \src "issuer_ls180.v:19319.9-19319.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub26_in2_sel[3:0] 4'1010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub26_in2_sel[3:0] 4'0001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub26_in2_sel[3:0] 4'1010 + case + assign $1\SHIFT_ROT_dec31_dec_sub26_in2_sel[3:0] 4'0000 + end + sync always + update \SHIFT_ROT_dec31_dec_sub26_in2_sel $0\SHIFT_ROT_dec31_dec_sub26_in2_sel[3:0] + end + attribute \src "issuer_ls180.v:19334.3-19349.6" + process $proc$issuer_ls180.v:19334$403 + assign { } { } + assign { } { } + assign $0\SHIFT_ROT_dec31_dec_sub26_cr_in[2:0] $1\SHIFT_ROT_dec31_dec_sub26_cr_in[2:0] + attribute \src "issuer_ls180.v:19335.5-19335.29" + switch \initial + attribute \src "issuer_ls180.v:19335.9-19335.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub26_cr_in[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub26_cr_in[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub26_cr_in[2:0] 3'000 + case + assign $1\SHIFT_ROT_dec31_dec_sub26_cr_in[2:0] 3'000 + end + sync always + update \SHIFT_ROT_dec31_dec_sub26_cr_in $0\SHIFT_ROT_dec31_dec_sub26_cr_in[2:0] + end + attribute \src "issuer_ls180.v:19350.3-19365.6" + process $proc$issuer_ls180.v:19350$404 + assign { } { } + assign { } { } + assign $0\SHIFT_ROT_dec31_dec_sub26_cr_out[2:0] $1\SHIFT_ROT_dec31_dec_sub26_cr_out[2:0] + attribute \src "issuer_ls180.v:19351.5-19351.29" + switch \initial + attribute \src "issuer_ls180.v:19351.9-19351.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub26_cr_out[2:0] 3'001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub26_cr_out[2:0] 3'001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub26_cr_out[2:0] 3'001 + case + assign $1\SHIFT_ROT_dec31_dec_sub26_cr_out[2:0] 3'000 + end + sync always + update \SHIFT_ROT_dec31_dec_sub26_cr_out $0\SHIFT_ROT_dec31_dec_sub26_cr_out[2:0] + end + attribute \src "issuer_ls180.v:19366.3-19381.6" + process $proc$issuer_ls180.v:19366$405 + assign { } { } + assign { } { } + assign $0\SHIFT_ROT_dec31_dec_sub26_rc_sel[1:0] $1\SHIFT_ROT_dec31_dec_sub26_rc_sel[1:0] + attribute \src "issuer_ls180.v:19367.5-19367.29" + switch \initial + attribute \src "issuer_ls180.v:19367.9-19367.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub26_rc_sel[1:0] 2'10 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub26_rc_sel[1:0] 2'10 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub26_rc_sel[1:0] 2'10 + case + assign $1\SHIFT_ROT_dec31_dec_sub26_rc_sel[1:0] 2'00 + end + sync always + update \SHIFT_ROT_dec31_dec_sub26_rc_sel $0\SHIFT_ROT_dec31_dec_sub26_rc_sel[1:0] + end + attribute \src "issuer_ls180.v:19382.3-19397.6" + process $proc$issuer_ls180.v:19382$406 + assign { } { } + assign { } { } + assign $0\SHIFT_ROT_dec31_dec_sub26_cry_in[1:0] $1\SHIFT_ROT_dec31_dec_sub26_cry_in[1:0] + attribute \src "issuer_ls180.v:19383.5-19383.29" + switch \initial + attribute \src "issuer_ls180.v:19383.9-19383.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub26_cry_in[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub26_cry_in[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub26_cry_in[1:0] 2'00 + case + assign $1\SHIFT_ROT_dec31_dec_sub26_cry_in[1:0] 2'00 + end + sync always + update \SHIFT_ROT_dec31_dec_sub26_cry_in $0\SHIFT_ROT_dec31_dec_sub26_cry_in[1:0] + end + attribute \src "issuer_ls180.v:19398.3-19413.6" + process $proc$issuer_ls180.v:19398$407 + assign { } { } + assign { } { } + assign $0\SHIFT_ROT_dec31_dec_sub26_cry_out[0:0] $1\SHIFT_ROT_dec31_dec_sub26_cry_out[0:0] + attribute \src "issuer_ls180.v:19399.5-19399.29" + switch \initial + attribute \src "issuer_ls180.v:19399.9-19399.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub26_cry_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub26_cry_out[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub26_cry_out[0:0] 1'1 + case + assign $1\SHIFT_ROT_dec31_dec_sub26_cry_out[0:0] 1'0 + end + sync always + update \SHIFT_ROT_dec31_dec_sub26_cry_out $0\SHIFT_ROT_dec31_dec_sub26_cry_out[0:0] + end + attribute \src "issuer_ls180.v:19414.3-19429.6" + process $proc$issuer_ls180.v:19414$408 + assign { } { } + assign { } { } + assign $0\SHIFT_ROT_dec31_dec_sub26_is_32b[0:0] $1\SHIFT_ROT_dec31_dec_sub26_is_32b[0:0] + attribute \src "issuer_ls180.v:19415.5-19415.29" + switch \initial + attribute \src "issuer_ls180.v:19415.9-19415.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub26_is_32b[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub26_is_32b[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub26_is_32b[0:0] 1'0 + case + assign $1\SHIFT_ROT_dec31_dec_sub26_is_32b[0:0] 1'0 + end + sync always + update \SHIFT_ROT_dec31_dec_sub26_is_32b $0\SHIFT_ROT_dec31_dec_sub26_is_32b[0:0] + end + connect \opcode_switch \opcode_in [10:6] +end +attribute \src "issuer_ls180.v:19435.1-19786.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.dec_SHIFT_ROT.dec.SHIFT_ROT_dec31.SHIFT_ROT_dec31_dec_sub27" +attribute \generator "nMigen" +module \SHIFT_ROT_dec31_dec_sub27 + attribute \src "issuer_ls180.v:19671.3-19689.6" + wire width 3 $0\SHIFT_ROT_dec31_dec_sub27_cr_in[2:0] + attribute \src "issuer_ls180.v:19690.3-19708.6" + wire width 3 $0\SHIFT_ROT_dec31_dec_sub27_cr_out[2:0] + attribute \src "issuer_ls180.v:19728.3-19746.6" + wire width 2 $0\SHIFT_ROT_dec31_dec_sub27_cry_in[1:0] + attribute \src "issuer_ls180.v:19747.3-19765.6" + wire $0\SHIFT_ROT_dec31_dec_sub27_cry_out[0:0] + attribute \src "issuer_ls180.v:19595.3-19613.6" + wire width 12 $0\SHIFT_ROT_dec31_dec_sub27_function_unit[11:0] + attribute \src "issuer_ls180.v:19652.3-19670.6" + wire width 4 $0\SHIFT_ROT_dec31_dec_sub27_in2_sel[3:0] + attribute \src "issuer_ls180.v:19633.3-19651.6" + wire width 7 $0\SHIFT_ROT_dec31_dec_sub27_internal_op[6:0] + attribute \src "issuer_ls180.v:19766.3-19784.6" + wire $0\SHIFT_ROT_dec31_dec_sub27_is_32b[0:0] + attribute \src "issuer_ls180.v:19709.3-19727.6" + wire width 2 $0\SHIFT_ROT_dec31_dec_sub27_rc_sel[1:0] + attribute \src "issuer_ls180.v:19614.3-19632.6" + wire $0\SHIFT_ROT_dec31_dec_sub27_sgn[0:0] + attribute \src "issuer_ls180.v:19436.7-19436.20" + wire $0\initial[0:0] + attribute \src "issuer_ls180.v:19671.3-19689.6" + wire width 3 $1\SHIFT_ROT_dec31_dec_sub27_cr_in[2:0] + attribute \src "issuer_ls180.v:19690.3-19708.6" + wire width 3 $1\SHIFT_ROT_dec31_dec_sub27_cr_out[2:0] + attribute \src "issuer_ls180.v:19728.3-19746.6" + wire width 2 $1\SHIFT_ROT_dec31_dec_sub27_cry_in[1:0] + attribute \src "issuer_ls180.v:19747.3-19765.6" + wire $1\SHIFT_ROT_dec31_dec_sub27_cry_out[0:0] + attribute \src "issuer_ls180.v:19595.3-19613.6" + wire width 12 $1\SHIFT_ROT_dec31_dec_sub27_function_unit[11:0] + attribute \src "issuer_ls180.v:19652.3-19670.6" + wire width 4 $1\SHIFT_ROT_dec31_dec_sub27_in2_sel[3:0] + attribute \src "issuer_ls180.v:19633.3-19651.6" + wire width 7 $1\SHIFT_ROT_dec31_dec_sub27_internal_op[6:0] + attribute \src "issuer_ls180.v:19766.3-19784.6" + wire $1\SHIFT_ROT_dec31_dec_sub27_is_32b[0:0] + attribute \src "issuer_ls180.v:19709.3-19727.6" + wire width 2 $1\SHIFT_ROT_dec31_dec_sub27_rc_sel[1:0] + attribute \src "issuer_ls180.v:19614.3-19632.6" + wire $1\SHIFT_ROT_dec31_dec_sub27_sgn[0:0] + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 4 \SHIFT_ROT_dec31_dec_sub27_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 5 \SHIFT_ROT_dec31_dec_sub27_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 7 \SHIFT_ROT_dec31_dec_sub27_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 8 \SHIFT_ROT_dec31_dec_sub27_cry_out + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 12 output 1 \SHIFT_ROT_dec31_dec_sub27_function_unit + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 output 3 \SHIFT_ROT_dec31_dec_sub27_in2_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 7 output 2 \SHIFT_ROT_dec31_dec_sub27_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 9 \SHIFT_ROT_dec31_dec_sub27_is_32b + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 6 \SHIFT_ROT_dec31_dec_sub27_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 10 \SHIFT_ROT_dec31_dec_sub27_sgn + attribute \src "issuer_ls180.v:19436.7-19436.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + wire width 32 input 11 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:320" + wire width 5 \opcode_switch + attribute \src "issuer_ls180.v:19436.7-19436.20" + process $proc$issuer_ls180.v:19436$420 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "issuer_ls180.v:19595.3-19613.6" + process $proc$issuer_ls180.v:19595$410 + assign { } { } + assign { } { } + assign $0\SHIFT_ROT_dec31_dec_sub27_function_unit[11:0] $1\SHIFT_ROT_dec31_dec_sub27_function_unit[11:0] + attribute \src "issuer_ls180.v:19596.5-19596.29" + switch \initial + attribute \src "issuer_ls180.v:19596.9-19596.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub27_function_unit[11:0] 12'000000001000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub27_function_unit[11:0] 12'000000001000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub27_function_unit[11:0] 12'000000001000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub27_function_unit[11:0] 12'000000001000 + case + assign $1\SHIFT_ROT_dec31_dec_sub27_function_unit[11:0] 12'000000000000 + end + sync always + update \SHIFT_ROT_dec31_dec_sub27_function_unit $0\SHIFT_ROT_dec31_dec_sub27_function_unit[11:0] + end + attribute \src "issuer_ls180.v:19614.3-19632.6" + process $proc$issuer_ls180.v:19614$411 + assign { } { } + assign { } { } + assign $0\SHIFT_ROT_dec31_dec_sub27_sgn[0:0] $1\SHIFT_ROT_dec31_dec_sub27_sgn[0:0] + attribute \src "issuer_ls180.v:19615.5-19615.29" + switch \initial + attribute \src "issuer_ls180.v:19615.9-19615.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub27_sgn[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub27_sgn[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub27_sgn[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub27_sgn[0:0] 1'0 + case + assign $1\SHIFT_ROT_dec31_dec_sub27_sgn[0:0] 1'0 + end + sync always + update \SHIFT_ROT_dec31_dec_sub27_sgn $0\SHIFT_ROT_dec31_dec_sub27_sgn[0:0] + end + attribute \src "issuer_ls180.v:19633.3-19651.6" + process $proc$issuer_ls180.v:19633$412 + assign { } { } + assign { } { } + assign $0\SHIFT_ROT_dec31_dec_sub27_internal_op[6:0] $1\SHIFT_ROT_dec31_dec_sub27_internal_op[6:0] + attribute \src "issuer_ls180.v:19634.5-19634.29" + switch \initial + attribute \src "issuer_ls180.v:19634.9-19634.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub27_internal_op[6:0] 7'0100000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub27_internal_op[6:0] 7'0111100 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub27_internal_op[6:0] 7'0111101 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub27_internal_op[6:0] 7'0111101 + case + assign $1\SHIFT_ROT_dec31_dec_sub27_internal_op[6:0] 7'0000000 + end + sync always + update \SHIFT_ROT_dec31_dec_sub27_internal_op $0\SHIFT_ROT_dec31_dec_sub27_internal_op[6:0] + end + attribute \src "issuer_ls180.v:19652.3-19670.6" + process $proc$issuer_ls180.v:19652$413 + assign { } { } + assign { } { } + assign $0\SHIFT_ROT_dec31_dec_sub27_in2_sel[3:0] $1\SHIFT_ROT_dec31_dec_sub27_in2_sel[3:0] + attribute \src "issuer_ls180.v:19653.5-19653.29" + switch \initial + attribute \src "issuer_ls180.v:19653.9-19653.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub27_in2_sel[3:0] 4'1010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub27_in2_sel[3:0] 4'0001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub27_in2_sel[3:0] 4'1010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub27_in2_sel[3:0] 4'0001 + case + assign $1\SHIFT_ROT_dec31_dec_sub27_in2_sel[3:0] 4'0000 + end + sync always + update \SHIFT_ROT_dec31_dec_sub27_in2_sel $0\SHIFT_ROT_dec31_dec_sub27_in2_sel[3:0] + end + attribute \src "issuer_ls180.v:19671.3-19689.6" + process $proc$issuer_ls180.v:19671$414 + assign { } { } + assign { } { } + assign $0\SHIFT_ROT_dec31_dec_sub27_cr_in[2:0] $1\SHIFT_ROT_dec31_dec_sub27_cr_in[2:0] + attribute \src "issuer_ls180.v:19672.5-19672.29" + switch \initial + attribute \src "issuer_ls180.v:19672.9-19672.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub27_cr_in[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub27_cr_in[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub27_cr_in[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub27_cr_in[2:0] 3'000 + case + assign $1\SHIFT_ROT_dec31_dec_sub27_cr_in[2:0] 3'000 + end + sync always + update \SHIFT_ROT_dec31_dec_sub27_cr_in $0\SHIFT_ROT_dec31_dec_sub27_cr_in[2:0] + end + attribute \src "issuer_ls180.v:19690.3-19708.6" + process $proc$issuer_ls180.v:19690$415 + assign { } { } + assign { } { } + assign $0\SHIFT_ROT_dec31_dec_sub27_cr_out[2:0] $1\SHIFT_ROT_dec31_dec_sub27_cr_out[2:0] + attribute \src "issuer_ls180.v:19691.5-19691.29" + switch \initial + attribute \src "issuer_ls180.v:19691.9-19691.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub27_cr_out[2:0] 3'001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub27_cr_out[2:0] 3'001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub27_cr_out[2:0] 3'001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub27_cr_out[2:0] 3'001 + case + assign $1\SHIFT_ROT_dec31_dec_sub27_cr_out[2:0] 3'000 + end + sync always + update \SHIFT_ROT_dec31_dec_sub27_cr_out $0\SHIFT_ROT_dec31_dec_sub27_cr_out[2:0] + end + attribute \src "issuer_ls180.v:19709.3-19727.6" + process $proc$issuer_ls180.v:19709$416 + assign { } { } + assign { } { } + assign $0\SHIFT_ROT_dec31_dec_sub27_rc_sel[1:0] $1\SHIFT_ROT_dec31_dec_sub27_rc_sel[1:0] + attribute \src "issuer_ls180.v:19710.5-19710.29" + switch \initial + attribute \src "issuer_ls180.v:19710.9-19710.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub27_rc_sel[1:0] 2'10 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub27_rc_sel[1:0] 2'10 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub27_rc_sel[1:0] 2'10 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub27_rc_sel[1:0] 2'10 + case + assign $1\SHIFT_ROT_dec31_dec_sub27_rc_sel[1:0] 2'00 + end + sync always + update \SHIFT_ROT_dec31_dec_sub27_rc_sel $0\SHIFT_ROT_dec31_dec_sub27_rc_sel[1:0] + end + attribute \src "issuer_ls180.v:19728.3-19746.6" + process $proc$issuer_ls180.v:19728$417 + assign { } { } + assign { } { } + assign $0\SHIFT_ROT_dec31_dec_sub27_cry_in[1:0] $1\SHIFT_ROT_dec31_dec_sub27_cry_in[1:0] + attribute \src "issuer_ls180.v:19729.5-19729.29" + switch \initial + attribute \src "issuer_ls180.v:19729.9-19729.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub27_cry_in[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub27_cry_in[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub27_cry_in[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub27_cry_in[1:0] 2'00 + case + assign $1\SHIFT_ROT_dec31_dec_sub27_cry_in[1:0] 2'00 + end + sync always + update \SHIFT_ROT_dec31_dec_sub27_cry_in $0\SHIFT_ROT_dec31_dec_sub27_cry_in[1:0] + end + attribute \src "issuer_ls180.v:19747.3-19765.6" + process $proc$issuer_ls180.v:19747$418 + assign { } { } + assign { } { } + assign $0\SHIFT_ROT_dec31_dec_sub27_cry_out[0:0] $1\SHIFT_ROT_dec31_dec_sub27_cry_out[0:0] + attribute \src "issuer_ls180.v:19748.5-19748.29" + switch \initial + attribute \src "issuer_ls180.v:19748.9-19748.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub27_cry_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub27_cry_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub27_cry_out[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub27_cry_out[0:0] 1'0 + case + assign $1\SHIFT_ROT_dec31_dec_sub27_cry_out[0:0] 1'0 + end + sync always + update \SHIFT_ROT_dec31_dec_sub27_cry_out $0\SHIFT_ROT_dec31_dec_sub27_cry_out[0:0] + end + attribute \src "issuer_ls180.v:19766.3-19784.6" + process $proc$issuer_ls180.v:19766$419 + assign { } { } + assign { } { } + assign $0\SHIFT_ROT_dec31_dec_sub27_is_32b[0:0] $1\SHIFT_ROT_dec31_dec_sub27_is_32b[0:0] + attribute \src "issuer_ls180.v:19767.5-19767.29" + switch \initial + attribute \src "issuer_ls180.v:19767.9-19767.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub27_is_32b[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub27_is_32b[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub27_is_32b[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\SHIFT_ROT_dec31_dec_sub27_is_32b[0:0] 1'0 + case + assign $1\SHIFT_ROT_dec31_dec_sub27_is_32b[0:0] 1'0 + end + sync always + update \SHIFT_ROT_dec31_dec_sub27_is_32b $0\SHIFT_ROT_dec31_dec_sub27_is_32b[0:0] + end + connect \opcode_switch \opcode_in [10:6] +end +attribute \src "issuer_ls180.v:19790.1-20112.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.dec_SPR.dec.SPR_dec31" +attribute \generator "nMigen" +module \SPR_dec31 + attribute \src "issuer_ls180.v:20069.3-20078.6" + wire width 3 $0\SPR_dec31_cr_in[2:0] + attribute \src "issuer_ls180.v:20079.3-20088.6" + wire width 3 $0\SPR_dec31_cr_out[2:0] + attribute \src "issuer_ls180.v:20049.3-20058.6" + wire width 12 $0\SPR_dec31_function_unit[11:0] + attribute \src "issuer_ls180.v:20059.3-20068.6" + wire width 7 $0\SPR_dec31_internal_op[6:0] + attribute \src "issuer_ls180.v:20099.3-20108.6" + wire $0\SPR_dec31_is_32b[0:0] + attribute \src "issuer_ls180.v:20089.3-20098.6" + wire width 2 $0\SPR_dec31_rc_sel[1:0] + attribute \src "issuer_ls180.v:19791.7-19791.20" + wire $0\initial[0:0] + attribute \src "issuer_ls180.v:20069.3-20078.6" + wire width 3 $1\SPR_dec31_cr_in[2:0] + attribute \src "issuer_ls180.v:20079.3-20088.6" + wire width 3 $1\SPR_dec31_cr_out[2:0] + attribute \src "issuer_ls180.v:20049.3-20058.6" + wire width 12 $1\SPR_dec31_function_unit[11:0] + attribute \src "issuer_ls180.v:20059.3-20068.6" + wire width 7 $1\SPR_dec31_internal_op[6:0] + attribute \src "issuer_ls180.v:20099.3-20108.6" + wire $1\SPR_dec31_is_32b[0:0] + attribute \src "issuer_ls180.v:20089.3-20098.6" + wire width 2 $1\SPR_dec31_rc_sel[1:0] + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 3 \SPR_dec31_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 4 \SPR_dec31_cr_out + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 \SPR_dec31_dec_sub19_SPR_dec31_dec_sub19_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 \SPR_dec31_dec_sub19_SPR_dec31_dec_sub19_cr_out + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 12 \SPR_dec31_dec_sub19_SPR_dec31_dec_sub19_function_unit + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 7 \SPR_dec31_dec_sub19_SPR_dec31_dec_sub19_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \SPR_dec31_dec_sub19_SPR_dec31_dec_sub19_is_32b + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \SPR_dec31_dec_sub19_SPR_dec31_dec_sub19_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + wire width 32 \SPR_dec31_dec_sub19_opcode_in + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 12 output 1 \SPR_dec31_function_unit + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 7 output 2 \SPR_dec31_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 6 \SPR_dec31_is_32b + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 5 \SPR_dec31_rc_sel + attribute \src "issuer_ls180.v:19791.7-19791.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:326" + wire width 5 \opc_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + wire width 32 input 7 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:320" + wire width 10 \opcode_switch + attribute \module_not_derived 1 + attribute \src "issuer_ls180.v:20040.23-20048.4" + cell \SPR_dec31_dec_sub19 \SPR_dec31_dec_sub19 + connect \SPR_dec31_dec_sub19_cr_in \SPR_dec31_dec_sub19_SPR_dec31_dec_sub19_cr_in + connect \SPR_dec31_dec_sub19_cr_out \SPR_dec31_dec_sub19_SPR_dec31_dec_sub19_cr_out + connect \SPR_dec31_dec_sub19_function_unit \SPR_dec31_dec_sub19_SPR_dec31_dec_sub19_function_unit + connect \SPR_dec31_dec_sub19_internal_op \SPR_dec31_dec_sub19_SPR_dec31_dec_sub19_internal_op + connect \SPR_dec31_dec_sub19_is_32b \SPR_dec31_dec_sub19_SPR_dec31_dec_sub19_is_32b + connect \SPR_dec31_dec_sub19_rc_sel \SPR_dec31_dec_sub19_SPR_dec31_dec_sub19_rc_sel + connect \opcode_in \SPR_dec31_dec_sub19_opcode_in + end + attribute \src "issuer_ls180.v:19791.7-19791.20" + process $proc$issuer_ls180.v:19791$427 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "issuer_ls180.v:20049.3-20058.6" + process $proc$issuer_ls180.v:20049$421 + assign { } { } + assign { } { } + assign $0\SPR_dec31_function_unit[11:0] $1\SPR_dec31_function_unit[11:0] + attribute \src "issuer_ls180.v:20050.5-20050.29" + switch \initial + attribute \src "issuer_ls180.v:20050.9-20050.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opc_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\SPR_dec31_function_unit[11:0] \SPR_dec31_dec_sub19_SPR_dec31_dec_sub19_function_unit + case + assign $1\SPR_dec31_function_unit[11:0] 12'000000000000 + end + sync always + update \SPR_dec31_function_unit $0\SPR_dec31_function_unit[11:0] + end + attribute \src "issuer_ls180.v:20059.3-20068.6" + process $proc$issuer_ls180.v:20059$422 + assign { } { } + assign { } { } + assign $0\SPR_dec31_internal_op[6:0] $1\SPR_dec31_internal_op[6:0] + attribute \src "issuer_ls180.v:20060.5-20060.29" + switch \initial + attribute \src "issuer_ls180.v:20060.9-20060.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opc_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\SPR_dec31_internal_op[6:0] \SPR_dec31_dec_sub19_SPR_dec31_dec_sub19_internal_op + case + assign $1\SPR_dec31_internal_op[6:0] 7'0000000 + end + sync always + update \SPR_dec31_internal_op $0\SPR_dec31_internal_op[6:0] + end + attribute \src "issuer_ls180.v:20069.3-20078.6" + process $proc$issuer_ls180.v:20069$423 + assign { } { } + assign { } { } + assign $0\SPR_dec31_cr_in[2:0] $1\SPR_dec31_cr_in[2:0] + attribute \src "issuer_ls180.v:20070.5-20070.29" + switch \initial + attribute \src "issuer_ls180.v:20070.9-20070.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opc_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\SPR_dec31_cr_in[2:0] \SPR_dec31_dec_sub19_SPR_dec31_dec_sub19_cr_in + case + assign $1\SPR_dec31_cr_in[2:0] 3'000 + end + sync always + update \SPR_dec31_cr_in $0\SPR_dec31_cr_in[2:0] + end + attribute \src "issuer_ls180.v:20079.3-20088.6" + process $proc$issuer_ls180.v:20079$424 + assign { } { } + assign { } { } + assign $0\SPR_dec31_cr_out[2:0] $1\SPR_dec31_cr_out[2:0] + attribute \src "issuer_ls180.v:20080.5-20080.29" + switch \initial + attribute \src "issuer_ls180.v:20080.9-20080.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opc_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\SPR_dec31_cr_out[2:0] \SPR_dec31_dec_sub19_SPR_dec31_dec_sub19_cr_out + case + assign $1\SPR_dec31_cr_out[2:0] 3'000 + end + sync always + update \SPR_dec31_cr_out $0\SPR_dec31_cr_out[2:0] + end + attribute \src "issuer_ls180.v:20089.3-20098.6" + process $proc$issuer_ls180.v:20089$425 + assign { } { } + assign { } { } + assign $0\SPR_dec31_rc_sel[1:0] $1\SPR_dec31_rc_sel[1:0] + attribute \src "issuer_ls180.v:20090.5-20090.29" + switch \initial + attribute \src "issuer_ls180.v:20090.9-20090.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opc_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\SPR_dec31_rc_sel[1:0] \SPR_dec31_dec_sub19_SPR_dec31_dec_sub19_rc_sel + case + assign $1\SPR_dec31_rc_sel[1:0] 2'00 + end + sync always + update \SPR_dec31_rc_sel $0\SPR_dec31_rc_sel[1:0] + end + attribute \src "issuer_ls180.v:20099.3-20108.6" + process $proc$issuer_ls180.v:20099$426 + assign { } { } + assign { } { } + assign $0\SPR_dec31_is_32b[0:0] $1\SPR_dec31_is_32b[0:0] + attribute \src "issuer_ls180.v:20100.5-20100.29" + switch \initial + attribute \src "issuer_ls180.v:20100.9-20100.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opc_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\SPR_dec31_is_32b[0:0] \SPR_dec31_dec_sub19_SPR_dec31_dec_sub19_is_32b + case + assign $1\SPR_dec31_is_32b[0:0] 1'0 + end + sync always + update \SPR_dec31_is_32b $0\SPR_dec31_is_32b[0:0] + end + connect \SPR_dec31_dec_sub19_opcode_in \opcode_in + connect \opc_in \opcode_switch [4:0] + connect \opcode_switch \opcode_in [10:1] +end +attribute \src "issuer_ls180.v:20116.1-20324.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.dec_SPR.dec.SPR_dec31.SPR_dec31_dec_sub19" +attribute \generator "nMigen" +module \SPR_dec31_dec_sub19 + attribute \src "issuer_ls180.v:20271.3-20283.6" + wire width 3 $0\SPR_dec31_dec_sub19_cr_in[2:0] + attribute \src "issuer_ls180.v:20284.3-20296.6" + wire width 3 $0\SPR_dec31_dec_sub19_cr_out[2:0] + attribute \src "issuer_ls180.v:20245.3-20257.6" + wire width 12 $0\SPR_dec31_dec_sub19_function_unit[11:0] + attribute \src "issuer_ls180.v:20258.3-20270.6" + wire width 7 $0\SPR_dec31_dec_sub19_internal_op[6:0] + attribute \src "issuer_ls180.v:20310.3-20322.6" + wire $0\SPR_dec31_dec_sub19_is_32b[0:0] + attribute \src "issuer_ls180.v:20297.3-20309.6" + wire width 2 $0\SPR_dec31_dec_sub19_rc_sel[1:0] + attribute \src "issuer_ls180.v:20117.7-20117.20" + wire $0\initial[0:0] + attribute \src "issuer_ls180.v:20271.3-20283.6" + wire width 3 $1\SPR_dec31_dec_sub19_cr_in[2:0] + attribute \src "issuer_ls180.v:20284.3-20296.6" + wire width 3 $1\SPR_dec31_dec_sub19_cr_out[2:0] + attribute \src "issuer_ls180.v:20245.3-20257.6" + wire width 12 $1\SPR_dec31_dec_sub19_function_unit[11:0] + attribute \src "issuer_ls180.v:20258.3-20270.6" + wire width 7 $1\SPR_dec31_dec_sub19_internal_op[6:0] + attribute \src "issuer_ls180.v:20310.3-20322.6" + wire $1\SPR_dec31_dec_sub19_is_32b[0:0] + attribute \src "issuer_ls180.v:20297.3-20309.6" + wire width 2 $1\SPR_dec31_dec_sub19_rc_sel[1:0] + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 3 \SPR_dec31_dec_sub19_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 4 \SPR_dec31_dec_sub19_cr_out + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 12 output 1 \SPR_dec31_dec_sub19_function_unit + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 7 output 2 \SPR_dec31_dec_sub19_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 6 \SPR_dec31_dec_sub19_is_32b + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 5 \SPR_dec31_dec_sub19_rc_sel + attribute \src "issuer_ls180.v:20117.7-20117.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + wire width 32 input 7 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:320" + wire width 5 \opcode_switch + attribute \src "issuer_ls180.v:20117.7-20117.20" + process $proc$issuer_ls180.v:20117$434 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "issuer_ls180.v:20245.3-20257.6" + process $proc$issuer_ls180.v:20245$428 + assign { } { } + assign { } { } + assign $0\SPR_dec31_dec_sub19_function_unit[11:0] $1\SPR_dec31_dec_sub19_function_unit[11:0] + attribute \src "issuer_ls180.v:20246.5-20246.29" + switch \initial + attribute \src "issuer_ls180.v:20246.9-20246.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\SPR_dec31_dec_sub19_function_unit[11:0] 12'010000000000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\SPR_dec31_dec_sub19_function_unit[11:0] 12'010000000000 + case + assign $1\SPR_dec31_dec_sub19_function_unit[11:0] 12'000000000000 + end + sync always + update \SPR_dec31_dec_sub19_function_unit $0\SPR_dec31_dec_sub19_function_unit[11:0] + end + attribute \src "issuer_ls180.v:20258.3-20270.6" + process $proc$issuer_ls180.v:20258$429 + assign { } { } + assign { } { } + assign $0\SPR_dec31_dec_sub19_internal_op[6:0] $1\SPR_dec31_dec_sub19_internal_op[6:0] + attribute \src "issuer_ls180.v:20259.5-20259.29" + switch \initial + attribute \src "issuer_ls180.v:20259.9-20259.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\SPR_dec31_dec_sub19_internal_op[6:0] 7'0101110 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\SPR_dec31_dec_sub19_internal_op[6:0] 7'0110001 + case + assign $1\SPR_dec31_dec_sub19_internal_op[6:0] 7'0000000 + end + sync always + update \SPR_dec31_dec_sub19_internal_op $0\SPR_dec31_dec_sub19_internal_op[6:0] + end + attribute \src "issuer_ls180.v:20271.3-20283.6" + process $proc$issuer_ls180.v:20271$430 + assign { } { } + assign { } { } + assign $0\SPR_dec31_dec_sub19_cr_in[2:0] $1\SPR_dec31_dec_sub19_cr_in[2:0] + attribute \src "issuer_ls180.v:20272.5-20272.29" + switch \initial + attribute \src "issuer_ls180.v:20272.9-20272.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\SPR_dec31_dec_sub19_cr_in[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\SPR_dec31_dec_sub19_cr_in[2:0] 3'000 + case + assign $1\SPR_dec31_dec_sub19_cr_in[2:0] 3'000 + end + sync always + update \SPR_dec31_dec_sub19_cr_in $0\SPR_dec31_dec_sub19_cr_in[2:0] + end + attribute \src "issuer_ls180.v:20284.3-20296.6" + process $proc$issuer_ls180.v:20284$431 + assign { } { } + assign { } { } + assign $0\SPR_dec31_dec_sub19_cr_out[2:0] $1\SPR_dec31_dec_sub19_cr_out[2:0] + attribute \src "issuer_ls180.v:20285.5-20285.29" + switch \initial + attribute \src "issuer_ls180.v:20285.9-20285.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\SPR_dec31_dec_sub19_cr_out[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\SPR_dec31_dec_sub19_cr_out[2:0] 3'000 + case + assign $1\SPR_dec31_dec_sub19_cr_out[2:0] 3'000 + end + sync always + update \SPR_dec31_dec_sub19_cr_out $0\SPR_dec31_dec_sub19_cr_out[2:0] + end + attribute \src "issuer_ls180.v:20297.3-20309.6" + process $proc$issuer_ls180.v:20297$432 + assign { } { } + assign { } { } + assign $0\SPR_dec31_dec_sub19_rc_sel[1:0] $1\SPR_dec31_dec_sub19_rc_sel[1:0] + attribute \src "issuer_ls180.v:20298.5-20298.29" + switch \initial + attribute \src "issuer_ls180.v:20298.9-20298.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\SPR_dec31_dec_sub19_rc_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\SPR_dec31_dec_sub19_rc_sel[1:0] 2'00 + case + assign $1\SPR_dec31_dec_sub19_rc_sel[1:0] 2'00 + end + sync always + update \SPR_dec31_dec_sub19_rc_sel $0\SPR_dec31_dec_sub19_rc_sel[1:0] + end + attribute \src "issuer_ls180.v:20310.3-20322.6" + process $proc$issuer_ls180.v:20310$433 + assign { } { } + assign { } { } + assign $0\SPR_dec31_dec_sub19_is_32b[0:0] $1\SPR_dec31_dec_sub19_is_32b[0:0] + attribute \src "issuer_ls180.v:20311.5-20311.29" + switch \initial + attribute \src "issuer_ls180.v:20311.9-20311.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\SPR_dec31_dec_sub19_is_32b[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\SPR_dec31_dec_sub19_is_32b[0:0] 1'0 + case + assign $1\SPR_dec31_dec_sub19_is_32b[0:0] 1'0 + end + sync always + update \SPR_dec31_dec_sub19_is_32b $0\SPR_dec31_dec_sub19_is_32b[0:0] + end + connect \opcode_switch \opcode_in [10:6] +end +attribute \src "issuer_ls180.v:20328.1-20386.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.fus.ldst0.adr_l" +attribute \generator "nMigen" +module \adr_l + attribute \src "issuer_ls180.v:20329.7-20329.20" + wire $0\initial[0:0] + attribute \src "issuer_ls180.v:20374.3-20382.6" + wire $0\q_int$next[0:0]$445 + attribute \src "issuer_ls180.v:20372.3-20373.27" + wire $0\q_int[0:0] + attribute \src "issuer_ls180.v:20374.3-20382.6" + wire $1\q_int$next[0:0]$446 + attribute \src "issuer_ls180.v:20353.7-20353.19" + wire $1\q_int[0:0] + attribute \src "issuer_ls180.v:20364.17-20364.96" + wire $and$issuer_ls180.v:20364$435_Y + attribute \src "issuer_ls180.v:20369.17-20369.96" + wire $and$issuer_ls180.v:20369$440_Y + attribute \src "issuer_ls180.v:20366.18-20366.93" + wire $not$issuer_ls180.v:20366$437_Y + attribute \src "issuer_ls180.v:20368.17-20368.92" + wire $not$issuer_ls180.v:20368$439_Y + attribute \src "issuer_ls180.v:20371.17-20371.92" + wire $not$issuer_ls180.v:20371$442_Y + attribute \src "issuer_ls180.v:20365.18-20365.98" + wire $or$issuer_ls180.v:20365$436_Y + attribute \src "issuer_ls180.v:20367.18-20367.99" + wire $or$issuer_ls180.v:20367$438_Y + attribute \src "issuer_ls180.v:20370.17-20370.97" + wire $or$issuer_ls180.v:20370$441_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire \$13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" + wire input 5 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" + wire input 1 \coresync_rst + attribute \src "issuer_ls180.v:20329.7-20329.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire output 4 \q_adr + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" + wire \qlq_adr + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + wire \qn_adr + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire input 3 \r_adr + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire input 2 \s_adr + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $and $and$issuer_ls180.v:20364$435 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$7 + connect \Y $and$issuer_ls180.v:20364$435_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $and $and$issuer_ls180.v:20369$440 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$1 + connect \Y $and$issuer_ls180.v:20369$440_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + cell $not $not$issuer_ls180.v:20366$437 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_adr + connect \Y $not$issuer_ls180.v:20366$437_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $not $not$issuer_ls180.v:20368$439 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_adr + connect \Y $not$issuer_ls180.v:20368$439_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $not $not$issuer_ls180.v:20371$442 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_adr + connect \Y $not$issuer_ls180.v:20371$442_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $or $or$issuer_ls180.v:20365$436 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$9 + connect \B \s_adr + connect \Y $or$issuer_ls180.v:20365$436_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + cell $or $or$issuer_ls180.v:20367$438 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_adr + connect \B \q_int + connect \Y $or$issuer_ls180.v:20367$438_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $or $or$issuer_ls180.v:20370$441 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$3 + connect \B \s_adr + connect \Y $or$issuer_ls180.v:20370$441_Y + end + attribute \src "issuer_ls180.v:20329.7-20329.20" + process $proc$issuer_ls180.v:20329$447 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "issuer_ls180.v:20353.7-20353.19" + process $proc$issuer_ls180.v:20353$448 + assign { } { } + assign $1\q_int[0:0] 1'0 + sync always + sync init + update \q_int $1\q_int[0:0] + end + attribute \src "issuer_ls180.v:20372.3-20373.27" + process $proc$issuer_ls180.v:20372$443 + assign { } { } + assign $0\q_int[0:0] \q_int$next + sync posedge \coresync_clk + update \q_int $0\q_int[0:0] + end + attribute \src "issuer_ls180.v:20374.3-20382.6" + process $proc$issuer_ls180.v:20374$444 + assign { } { } + assign { } { } + assign $0\q_int$next[0:0]$445 $1\q_int$next[0:0]$446 + attribute \src "issuer_ls180.v:20375.5-20375.29" + switch \initial + attribute \src "issuer_ls180.v:20375.9-20375.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\q_int$next[0:0]$446 1'0 + case + assign $1\q_int$next[0:0]$446 \$5 + end + sync always + update \q_int$next $0\q_int$next[0:0]$445 + end + connect \$9 $and$issuer_ls180.v:20364$435_Y + connect \$11 $or$issuer_ls180.v:20365$436_Y + connect \$13 $not$issuer_ls180.v:20366$437_Y + connect \$15 $or$issuer_ls180.v:20367$438_Y + connect \$1 $not$issuer_ls180.v:20368$439_Y + connect \$3 $and$issuer_ls180.v:20369$440_Y + connect \$5 $or$issuer_ls180.v:20370$441_Y + connect \$7 $not$issuer_ls180.v:20371$442_Y + connect \qlq_adr \$15 + connect \qn_adr \$13 + connect \q_adr \$11 +end +attribute \src "issuer_ls180.v:20390.1-20448.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.l0.pimem.adrok_l" +attribute \generator "nMigen" +module \adrok_l + attribute \src "issuer_ls180.v:20391.7-20391.20" + wire $0\initial[0:0] + attribute \src "issuer_ls180.v:20436.3-20444.6" + wire $0\q_int$next[0:0]$459 + attribute \src "issuer_ls180.v:20434.3-20435.27" + wire $0\q_int[0:0] + attribute \src "issuer_ls180.v:20436.3-20444.6" + wire $1\q_int$next[0:0]$460 + attribute \src "issuer_ls180.v:20415.7-20415.19" + wire $1\q_int[0:0] + attribute \src "issuer_ls180.v:20426.17-20426.96" + wire $and$issuer_ls180.v:20426$449_Y + attribute \src "issuer_ls180.v:20431.17-20431.96" + wire $and$issuer_ls180.v:20431$454_Y + attribute \src "issuer_ls180.v:20428.18-20428.100" + wire $not$issuer_ls180.v:20428$451_Y + attribute \src "issuer_ls180.v:20430.17-20430.99" + wire $not$issuer_ls180.v:20430$453_Y + attribute \src "issuer_ls180.v:20433.17-20433.99" + wire $not$issuer_ls180.v:20433$456_Y + attribute \src "issuer_ls180.v:20427.18-20427.105" + wire $or$issuer_ls180.v:20427$450_Y + attribute \src "issuer_ls180.v:20429.18-20429.106" + wire $or$issuer_ls180.v:20429$452_Y + attribute \src "issuer_ls180.v:20432.17-20432.104" + wire $or$issuer_ls180.v:20432$455_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire \$13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" + wire input 6 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" + wire input 1 \coresync_rst + attribute \src "issuer_ls180.v:20391.7-20391.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire output 5 \q_addr_acked + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" + wire \qlq_addr_acked + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + wire output 4 \qn_addr_acked + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire input 3 \r_addr_acked + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire input 2 \s_addr_acked + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $and $and$issuer_ls180.v:20426$449 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$7 + connect \Y $and$issuer_ls180.v:20426$449_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $and $and$issuer_ls180.v:20431$454 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$1 + connect \Y $and$issuer_ls180.v:20431$454_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + cell $not $not$issuer_ls180.v:20428$451 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_addr_acked + connect \Y $not$issuer_ls180.v:20428$451_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $not $not$issuer_ls180.v:20430$453 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_addr_acked + connect \Y $not$issuer_ls180.v:20430$453_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $not $not$issuer_ls180.v:20433$456 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_addr_acked + connect \Y $not$issuer_ls180.v:20433$456_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $or $or$issuer_ls180.v:20427$450 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$9 + connect \B \s_addr_acked + connect \Y $or$issuer_ls180.v:20427$450_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + cell $or $or$issuer_ls180.v:20429$452 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_addr_acked + connect \B \q_int + connect \Y $or$issuer_ls180.v:20429$452_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $or $or$issuer_ls180.v:20432$455 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$3 + connect \B \s_addr_acked + connect \Y $or$issuer_ls180.v:20432$455_Y + end + attribute \src "issuer_ls180.v:20391.7-20391.20" + process $proc$issuer_ls180.v:20391$461 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "issuer_ls180.v:20415.7-20415.19" + process $proc$issuer_ls180.v:20415$462 + assign { } { } + assign $1\q_int[0:0] 1'0 + sync always + sync init + update \q_int $1\q_int[0:0] + end + attribute \src "issuer_ls180.v:20434.3-20435.27" + process $proc$issuer_ls180.v:20434$457 + assign { } { } + assign $0\q_int[0:0] \q_int$next + sync posedge \coresync_clk + update \q_int $0\q_int[0:0] + end + attribute \src "issuer_ls180.v:20436.3-20444.6" + process $proc$issuer_ls180.v:20436$458 + assign { } { } + assign { } { } + assign $0\q_int$next[0:0]$459 $1\q_int$next[0:0]$460 + attribute \src "issuer_ls180.v:20437.5-20437.29" + switch \initial + attribute \src "issuer_ls180.v:20437.9-20437.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\q_int$next[0:0]$460 1'0 + case + assign $1\q_int$next[0:0]$460 \$5 + end + sync always + update \q_int$next $0\q_int$next[0:0]$459 + end + connect \$9 $and$issuer_ls180.v:20426$449_Y + connect \$11 $or$issuer_ls180.v:20427$450_Y + connect \$13 $not$issuer_ls180.v:20428$451_Y + connect \$15 $or$issuer_ls180.v:20429$452_Y + connect \$1 $not$issuer_ls180.v:20430$453_Y + connect \$3 $and$issuer_ls180.v:20431$454_Y + connect \$5 $or$issuer_ls180.v:20432$455_Y + connect \$7 $not$issuer_ls180.v:20433$456_Y + connect \qlq_addr_acked \$15 + connect \qn_addr_acked \$13 + connect \q_addr_acked \$11 +end +attribute \src "issuer_ls180.v:20452.1-21777.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.fus.alu0" +attribute \generator "nMigen" +module \alu0 + attribute \src "issuer_ls180.v:21288.3-21289.25" + wire $0\all_rd_dly[0:0] + attribute \src "issuer_ls180.v:21478.3-21516.6" + wire width 4 $0\alu_alu0_alu_op__data_len$next[3:0]$609 + attribute \src "issuer_ls180.v:21260.3-21261.67" + wire width 4 $0\alu_alu0_alu_op__data_len[3:0] + attribute \src "issuer_ls180.v:21478.3-21516.6" + wire width 12 $0\alu_alu0_alu_op__fn_unit$next[11:0]$610 + attribute \src "issuer_ls180.v:21230.3-21231.65" + wire width 12 $0\alu_alu0_alu_op__fn_unit[11:0] + attribute \src "issuer_ls180.v:21478.3-21516.6" + wire width 64 $0\alu_alu0_alu_op__imm_data__data$next[63:0]$611 + attribute \src "issuer_ls180.v:21232.3-21233.79" + wire width 64 $0\alu_alu0_alu_op__imm_data__data[63:0] + attribute \src "issuer_ls180.v:21478.3-21516.6" + wire $0\alu_alu0_alu_op__imm_data__ok$next[0:0]$612 + attribute \src "issuer_ls180.v:21234.3-21235.75" + wire $0\alu_alu0_alu_op__imm_data__ok[0:0] + attribute \src "issuer_ls180.v:21478.3-21516.6" + wire width 2 $0\alu_alu0_alu_op__input_carry$next[1:0]$613 + attribute \src "issuer_ls180.v:21252.3-21253.73" + wire width 2 $0\alu_alu0_alu_op__input_carry[1:0] + attribute \src "issuer_ls180.v:21478.3-21516.6" + wire width 32 $0\alu_alu0_alu_op__insn$next[31:0]$614 + attribute \src "issuer_ls180.v:21262.3-21263.59" + wire width 32 $0\alu_alu0_alu_op__insn[31:0] + attribute \src "issuer_ls180.v:21478.3-21516.6" + wire width 7 $0\alu_alu0_alu_op__insn_type$next[6:0]$615 + attribute \src "issuer_ls180.v:21228.3-21229.69" + wire width 7 $0\alu_alu0_alu_op__insn_type[6:0] + attribute \src "issuer_ls180.v:21478.3-21516.6" + wire $0\alu_alu0_alu_op__invert_in$next[0:0]$616 + attribute \src "issuer_ls180.v:21244.3-21245.69" + wire $0\alu_alu0_alu_op__invert_in[0:0] + attribute \src "issuer_ls180.v:21478.3-21516.6" + wire $0\alu_alu0_alu_op__invert_out$next[0:0]$617 + attribute \src "issuer_ls180.v:21248.3-21249.71" + wire $0\alu_alu0_alu_op__invert_out[0:0] + attribute \src "issuer_ls180.v:21478.3-21516.6" + wire $0\alu_alu0_alu_op__is_32bit$next[0:0]$618 + attribute \src "issuer_ls180.v:21256.3-21257.67" + wire $0\alu_alu0_alu_op__is_32bit[0:0] + attribute \src "issuer_ls180.v:21478.3-21516.6" + wire $0\alu_alu0_alu_op__is_signed$next[0:0]$619 + attribute \src "issuer_ls180.v:21258.3-21259.69" + wire $0\alu_alu0_alu_op__is_signed[0:0] + attribute \src "issuer_ls180.v:21478.3-21516.6" + wire $0\alu_alu0_alu_op__oe__oe$next[0:0]$620 + attribute \src "issuer_ls180.v:21240.3-21241.63" + wire $0\alu_alu0_alu_op__oe__oe[0:0] + attribute \src "issuer_ls180.v:21478.3-21516.6" + wire $0\alu_alu0_alu_op__oe__ok$next[0:0]$621 + attribute \src "issuer_ls180.v:21242.3-21243.63" + wire $0\alu_alu0_alu_op__oe__ok[0:0] + attribute \src "issuer_ls180.v:21478.3-21516.6" + wire $0\alu_alu0_alu_op__output_carry$next[0:0]$622 + attribute \src "issuer_ls180.v:21254.3-21255.75" + wire $0\alu_alu0_alu_op__output_carry[0:0] + attribute \src "issuer_ls180.v:21478.3-21516.6" + wire $0\alu_alu0_alu_op__rc__ok$next[0:0]$623 + attribute \src "issuer_ls180.v:21238.3-21239.63" + wire $0\alu_alu0_alu_op__rc__ok[0:0] + attribute \src "issuer_ls180.v:21478.3-21516.6" + wire $0\alu_alu0_alu_op__rc__rc$next[0:0]$624 + attribute \src "issuer_ls180.v:21236.3-21237.63" + wire $0\alu_alu0_alu_op__rc__rc[0:0] + attribute \src "issuer_ls180.v:21478.3-21516.6" + wire $0\alu_alu0_alu_op__write_cr0$next[0:0]$625 + attribute \src "issuer_ls180.v:21250.3-21251.69" + wire $0\alu_alu0_alu_op__write_cr0[0:0] + attribute \src "issuer_ls180.v:21478.3-21516.6" + wire $0\alu_alu0_alu_op__zero_a$next[0:0]$626 + attribute \src "issuer_ls180.v:21246.3-21247.63" + wire $0\alu_alu0_alu_op__zero_a[0:0] + attribute \src "issuer_ls180.v:21286.3-21287.40" + wire $0\alu_done_dly[0:0] + attribute \src "issuer_ls180.v:21676.3-21684.6" + wire $0\alu_l_r_alu$next[0:0]$707 + attribute \src "issuer_ls180.v:21196.3-21197.39" + wire $0\alu_l_r_alu[0:0] + attribute \src "issuer_ls180.v:21667.3-21675.6" + wire $0\alui_l_r_alui$next[0:0]$704 + attribute \src "issuer_ls180.v:21198.3-21199.43" + wire $0\alui_l_r_alui[0:0] + attribute \src "issuer_ls180.v:21517.3-21538.6" + wire width 64 $0\data_r0__o$next[63:0]$652 + attribute \src "issuer_ls180.v:21224.3-21225.37" + wire width 64 $0\data_r0__o[63:0] + attribute \src "issuer_ls180.v:21517.3-21538.6" + wire $0\data_r0__o_ok$next[0:0]$653 + attribute \src "issuer_ls180.v:21226.3-21227.43" + wire $0\data_r0__o_ok[0:0] + attribute \src "issuer_ls180.v:21539.3-21560.6" + wire width 4 $0\data_r1__cr_a$next[3:0]$660 + attribute \src "issuer_ls180.v:21220.3-21221.43" + wire width 4 $0\data_r1__cr_a[3:0] + attribute \src "issuer_ls180.v:21539.3-21560.6" + wire $0\data_r1__cr_a_ok$next[0:0]$661 + attribute \src "issuer_ls180.v:21222.3-21223.49" + wire $0\data_r1__cr_a_ok[0:0] + attribute \src "issuer_ls180.v:21561.3-21582.6" + wire width 2 $0\data_r2__xer_ca$next[1:0]$668 + attribute \src "issuer_ls180.v:21216.3-21217.47" + wire width 2 $0\data_r2__xer_ca[1:0] + attribute \src "issuer_ls180.v:21561.3-21582.6" + wire $0\data_r2__xer_ca_ok$next[0:0]$669 + attribute \src "issuer_ls180.v:21218.3-21219.53" + wire $0\data_r2__xer_ca_ok[0:0] + attribute \src "issuer_ls180.v:21583.3-21604.6" + wire width 2 $0\data_r3__xer_ov$next[1:0]$676 + attribute \src "issuer_ls180.v:21212.3-21213.47" + wire width 2 $0\data_r3__xer_ov[1:0] + attribute \src "issuer_ls180.v:21583.3-21604.6" + wire $0\data_r3__xer_ov_ok$next[0:0]$677 + attribute \src "issuer_ls180.v:21214.3-21215.53" + wire $0\data_r3__xer_ov_ok[0:0] + attribute \src "issuer_ls180.v:21605.3-21626.6" + wire $0\data_r4__xer_so$next[0:0]$684 + attribute \src "issuer_ls180.v:21208.3-21209.47" + wire $0\data_r4__xer_so[0:0] + attribute \src "issuer_ls180.v:21605.3-21626.6" + wire $0\data_r4__xer_so_ok$next[0:0]$685 + attribute \src "issuer_ls180.v:21210.3-21211.53" + wire $0\data_r4__xer_so_ok[0:0] + attribute \src "issuer_ls180.v:21685.3-21694.6" + wire width 64 $0\dest1_o[63:0] + attribute \src "issuer_ls180.v:21695.3-21704.6" + wire width 4 $0\dest2_o[3:0] + attribute \src "issuer_ls180.v:21705.3-21714.6" + wire width 2 $0\dest3_o[1:0] + attribute \src "issuer_ls180.v:21715.3-21724.6" + wire width 2 $0\dest4_o[1:0] + attribute \src "issuer_ls180.v:21725.3-21734.6" + wire $0\dest5_o[0:0] + attribute \src "issuer_ls180.v:20453.7-20453.20" + wire $0\initial[0:0] + attribute \src "issuer_ls180.v:21433.3-21441.6" + wire $0\opc_l_r_opc$next[0:0]$594 + attribute \src "issuer_ls180.v:21272.3-21273.39" + wire $0\opc_l_r_opc[0:0] + attribute \src "issuer_ls180.v:21424.3-21432.6" + wire $0\opc_l_s_opc$next[0:0]$591 + attribute \src "issuer_ls180.v:21274.3-21275.39" + wire $0\opc_l_s_opc[0:0] + attribute \src "issuer_ls180.v:21735.3-21743.6" + wire width 5 $0\prev_wr_go$next[4:0]$715 + attribute \src "issuer_ls180.v:21284.3-21285.37" + wire width 5 $0\prev_wr_go[4:0] + attribute \src "issuer_ls180.v:21378.3-21387.6" + wire $0\req_done[0:0] + attribute \src "issuer_ls180.v:21469.3-21477.6" + wire width 5 $0\req_l_r_req$next[4:0]$606 + attribute \src "issuer_ls180.v:21264.3-21265.39" + wire width 5 $0\req_l_r_req[4:0] + attribute \src "issuer_ls180.v:21460.3-21468.6" + wire width 5 $0\req_l_s_req$next[4:0]$603 + attribute \src "issuer_ls180.v:21266.3-21267.39" + wire width 5 $0\req_l_s_req[4:0] + attribute \src "issuer_ls180.v:21397.3-21405.6" + wire $0\rok_l_r_rdok$next[0:0]$582 + attribute \src "issuer_ls180.v:21280.3-21281.41" + wire $0\rok_l_r_rdok[0:0] + attribute \src "issuer_ls180.v:21388.3-21396.6" + wire $0\rok_l_s_rdok$next[0:0]$579 + attribute \src "issuer_ls180.v:21282.3-21283.41" + wire $0\rok_l_s_rdok[0:0] + attribute \src "issuer_ls180.v:21415.3-21423.6" + wire $0\rst_l_r_rst$next[0:0]$588 + attribute \src "issuer_ls180.v:21276.3-21277.39" + wire $0\rst_l_r_rst[0:0] + attribute \src "issuer_ls180.v:21406.3-21414.6" + wire $0\rst_l_s_rst$next[0:0]$585 + attribute \src "issuer_ls180.v:21278.3-21279.39" + wire $0\rst_l_s_rst[0:0] + attribute \src "issuer_ls180.v:21451.3-21459.6" + wire width 4 $0\src_l_r_src$next[3:0]$600 + attribute \src "issuer_ls180.v:21268.3-21269.39" + wire width 4 $0\src_l_r_src[3:0] + attribute \src "issuer_ls180.v:21442.3-21450.6" + wire width 4 $0\src_l_s_src$next[3:0]$597 + attribute \src "issuer_ls180.v:21270.3-21271.39" + wire width 4 $0\src_l_s_src[3:0] + attribute \src "issuer_ls180.v:21627.3-21636.6" + wire width 64 $0\src_r0$next[63:0]$692 + attribute \src "issuer_ls180.v:21206.3-21207.29" + wire width 64 $0\src_r0[63:0] + attribute \src "issuer_ls180.v:21637.3-21646.6" + wire width 64 $0\src_r1$next[63:0]$695 + attribute \src "issuer_ls180.v:21204.3-21205.29" + wire width 64 $0\src_r1[63:0] + attribute \src "issuer_ls180.v:21647.3-21656.6" + wire $0\src_r2$next[0:0]$698 + attribute \src "issuer_ls180.v:21202.3-21203.29" + wire $0\src_r2[0:0] + attribute \src "issuer_ls180.v:21657.3-21666.6" + wire width 2 $0\src_r3$next[1:0]$701 + attribute \src "issuer_ls180.v:21200.3-21201.29" + wire width 2 $0\src_r3[1:0] + attribute \src "issuer_ls180.v:20591.7-20591.24" + wire $1\all_rd_dly[0:0] + attribute \src "issuer_ls180.v:21478.3-21516.6" + wire width 4 $1\alu_alu0_alu_op__data_len$next[3:0]$627 + attribute \src "issuer_ls180.v:20599.13-20599.45" + wire width 4 $1\alu_alu0_alu_op__data_len[3:0] + attribute \src "issuer_ls180.v:21478.3-21516.6" + wire width 12 $1\alu_alu0_alu_op__fn_unit$next[11:0]$628 + attribute \src "issuer_ls180.v:20616.14-20616.48" + wire width 12 $1\alu_alu0_alu_op__fn_unit[11:0] + attribute \src "issuer_ls180.v:21478.3-21516.6" + wire width 64 $1\alu_alu0_alu_op__imm_data__data$next[63:0]$629 + attribute \src "issuer_ls180.v:20620.14-20620.68" + wire width 64 $1\alu_alu0_alu_op__imm_data__data[63:0] + attribute \src "issuer_ls180.v:21478.3-21516.6" + wire $1\alu_alu0_alu_op__imm_data__ok$next[0:0]$630 + attribute \src "issuer_ls180.v:20624.7-20624.43" + wire $1\alu_alu0_alu_op__imm_data__ok[0:0] + attribute \src "issuer_ls180.v:21478.3-21516.6" + wire width 2 $1\alu_alu0_alu_op__input_carry$next[1:0]$631 + attribute \src "issuer_ls180.v:20632.13-20632.48" + wire width 2 $1\alu_alu0_alu_op__input_carry[1:0] + attribute \src "issuer_ls180.v:21478.3-21516.6" + wire width 32 $1\alu_alu0_alu_op__insn$next[31:0]$632 + attribute \src "issuer_ls180.v:20636.14-20636.43" + wire width 32 $1\alu_alu0_alu_op__insn[31:0] + attribute \src "issuer_ls180.v:21478.3-21516.6" + wire width 7 $1\alu_alu0_alu_op__insn_type$next[6:0]$633 + attribute \src "issuer_ls180.v:20714.13-20714.47" + wire width 7 $1\alu_alu0_alu_op__insn_type[6:0] + attribute \src "issuer_ls180.v:21478.3-21516.6" + wire $1\alu_alu0_alu_op__invert_in$next[0:0]$634 + attribute \src "issuer_ls180.v:20718.7-20718.40" + wire $1\alu_alu0_alu_op__invert_in[0:0] + attribute \src "issuer_ls180.v:21478.3-21516.6" + wire $1\alu_alu0_alu_op__invert_out$next[0:0]$635 + attribute \src "issuer_ls180.v:20722.7-20722.41" + wire $1\alu_alu0_alu_op__invert_out[0:0] + attribute \src "issuer_ls180.v:21478.3-21516.6" + wire $1\alu_alu0_alu_op__is_32bit$next[0:0]$636 + attribute \src "issuer_ls180.v:20726.7-20726.39" + wire $1\alu_alu0_alu_op__is_32bit[0:0] + attribute \src "issuer_ls180.v:21478.3-21516.6" + wire $1\alu_alu0_alu_op__is_signed$next[0:0]$637 + attribute \src "issuer_ls180.v:20730.7-20730.40" + wire $1\alu_alu0_alu_op__is_signed[0:0] + attribute \src "issuer_ls180.v:21478.3-21516.6" + wire $1\alu_alu0_alu_op__oe__oe$next[0:0]$638 + attribute \src "issuer_ls180.v:20734.7-20734.37" + wire $1\alu_alu0_alu_op__oe__oe[0:0] + attribute \src "issuer_ls180.v:21478.3-21516.6" + wire $1\alu_alu0_alu_op__oe__ok$next[0:0]$639 + attribute \src "issuer_ls180.v:20738.7-20738.37" + wire $1\alu_alu0_alu_op__oe__ok[0:0] + attribute \src "issuer_ls180.v:21478.3-21516.6" + wire $1\alu_alu0_alu_op__output_carry$next[0:0]$640 + attribute \src "issuer_ls180.v:20742.7-20742.43" + wire $1\alu_alu0_alu_op__output_carry[0:0] + attribute \src "issuer_ls180.v:21478.3-21516.6" + wire $1\alu_alu0_alu_op__rc__ok$next[0:0]$641 + attribute \src "issuer_ls180.v:20746.7-20746.37" + wire $1\alu_alu0_alu_op__rc__ok[0:0] + attribute \src "issuer_ls180.v:21478.3-21516.6" + wire $1\alu_alu0_alu_op__rc__rc$next[0:0]$642 + attribute \src "issuer_ls180.v:20750.7-20750.37" + wire $1\alu_alu0_alu_op__rc__rc[0:0] + attribute \src "issuer_ls180.v:21478.3-21516.6" + wire $1\alu_alu0_alu_op__write_cr0$next[0:0]$643 + attribute \src "issuer_ls180.v:20754.7-20754.40" + wire $1\alu_alu0_alu_op__write_cr0[0:0] + attribute \src "issuer_ls180.v:21478.3-21516.6" + wire $1\alu_alu0_alu_op__zero_a$next[0:0]$644 + attribute \src "issuer_ls180.v:20758.7-20758.37" + wire $1\alu_alu0_alu_op__zero_a[0:0] + attribute \src "issuer_ls180.v:20790.7-20790.26" + wire $1\alu_done_dly[0:0] + attribute \src "issuer_ls180.v:21676.3-21684.6" + wire $1\alu_l_r_alu$next[0:0]$708 + attribute \src "issuer_ls180.v:20798.7-20798.25" + wire $1\alu_l_r_alu[0:0] + attribute \src "issuer_ls180.v:21667.3-21675.6" + wire $1\alui_l_r_alui$next[0:0]$705 + attribute \src "issuer_ls180.v:20810.7-20810.27" + wire $1\alui_l_r_alui[0:0] + attribute \src "issuer_ls180.v:21517.3-21538.6" + wire width 64 $1\data_r0__o$next[63:0]$654 + attribute \src "issuer_ls180.v:20844.14-20844.47" + wire width 64 $1\data_r0__o[63:0] + attribute \src "issuer_ls180.v:21517.3-21538.6" + wire $1\data_r0__o_ok$next[0:0]$655 + attribute \src "issuer_ls180.v:20848.7-20848.27" + wire $1\data_r0__o_ok[0:0] + attribute \src "issuer_ls180.v:21539.3-21560.6" + wire width 4 $1\data_r1__cr_a$next[3:0]$662 + attribute \src "issuer_ls180.v:20852.13-20852.33" + wire width 4 $1\data_r1__cr_a[3:0] + attribute \src "issuer_ls180.v:21539.3-21560.6" + wire $1\data_r1__cr_a_ok$next[0:0]$663 + attribute \src "issuer_ls180.v:20856.7-20856.30" + wire $1\data_r1__cr_a_ok[0:0] + attribute \src "issuer_ls180.v:21561.3-21582.6" + wire width 2 $1\data_r2__xer_ca$next[1:0]$670 + attribute \src "issuer_ls180.v:20860.13-20860.35" + wire width 2 $1\data_r2__xer_ca[1:0] + attribute \src "issuer_ls180.v:21561.3-21582.6" + wire $1\data_r2__xer_ca_ok$next[0:0]$671 + attribute \src "issuer_ls180.v:20864.7-20864.32" + wire $1\data_r2__xer_ca_ok[0:0] + attribute \src "issuer_ls180.v:21583.3-21604.6" + wire width 2 $1\data_r3__xer_ov$next[1:0]$678 + attribute \src "issuer_ls180.v:20868.13-20868.35" + wire width 2 $1\data_r3__xer_ov[1:0] + attribute \src "issuer_ls180.v:21583.3-21604.6" + wire $1\data_r3__xer_ov_ok$next[0:0]$679 + attribute \src "issuer_ls180.v:20872.7-20872.32" + wire $1\data_r3__xer_ov_ok[0:0] + attribute \src "issuer_ls180.v:21605.3-21626.6" + wire $1\data_r4__xer_so$next[0:0]$686 + attribute \src "issuer_ls180.v:20876.7-20876.29" + wire $1\data_r4__xer_so[0:0] + attribute \src "issuer_ls180.v:21605.3-21626.6" + wire $1\data_r4__xer_so_ok$next[0:0]$687 + attribute \src "issuer_ls180.v:20880.7-20880.32" + wire $1\data_r4__xer_so_ok[0:0] + attribute \src "issuer_ls180.v:21685.3-21694.6" + wire width 64 $1\dest1_o[63:0] + attribute \src "issuer_ls180.v:21695.3-21704.6" + wire width 4 $1\dest2_o[3:0] + attribute \src "issuer_ls180.v:21705.3-21714.6" + wire width 2 $1\dest3_o[1:0] + attribute \src "issuer_ls180.v:21715.3-21724.6" + wire width 2 $1\dest4_o[1:0] + attribute \src "issuer_ls180.v:21725.3-21734.6" + wire $1\dest5_o[0:0] + attribute \src "issuer_ls180.v:21433.3-21441.6" + wire $1\opc_l_r_opc$next[0:0]$595 + attribute \src "issuer_ls180.v:20903.7-20903.25" + wire $1\opc_l_r_opc[0:0] + attribute \src "issuer_ls180.v:21424.3-21432.6" + wire $1\opc_l_s_opc$next[0:0]$592 + attribute \src "issuer_ls180.v:20907.7-20907.25" + wire $1\opc_l_s_opc[0:0] + attribute \src "issuer_ls180.v:21735.3-21743.6" + wire width 5 $1\prev_wr_go$next[4:0]$716 + attribute \src "issuer_ls180.v:21038.13-21038.31" + wire width 5 $1\prev_wr_go[4:0] + attribute \src "issuer_ls180.v:21378.3-21387.6" + wire $1\req_done[0:0] + attribute \src "issuer_ls180.v:21469.3-21477.6" + wire width 5 $1\req_l_r_req$next[4:0]$607 + attribute \src "issuer_ls180.v:21046.13-21046.32" + wire width 5 $1\req_l_r_req[4:0] + attribute \src "issuer_ls180.v:21460.3-21468.6" + wire width 5 $1\req_l_s_req$next[4:0]$604 + attribute \src "issuer_ls180.v:21050.13-21050.32" + wire width 5 $1\req_l_s_req[4:0] + attribute \src "issuer_ls180.v:21397.3-21405.6" + wire $1\rok_l_r_rdok$next[0:0]$583 + attribute \src "issuer_ls180.v:21062.7-21062.26" + wire $1\rok_l_r_rdok[0:0] + attribute \src "issuer_ls180.v:21388.3-21396.6" + wire $1\rok_l_s_rdok$next[0:0]$580 + attribute \src "issuer_ls180.v:21066.7-21066.26" + wire $1\rok_l_s_rdok[0:0] + attribute \src "issuer_ls180.v:21415.3-21423.6" + wire $1\rst_l_r_rst$next[0:0]$589 + attribute \src "issuer_ls180.v:21070.7-21070.25" + wire $1\rst_l_r_rst[0:0] + attribute \src "issuer_ls180.v:21406.3-21414.6" + wire $1\rst_l_s_rst$next[0:0]$586 + attribute \src "issuer_ls180.v:21074.7-21074.25" + wire $1\rst_l_s_rst[0:0] + attribute \src "issuer_ls180.v:21451.3-21459.6" + wire width 4 $1\src_l_r_src$next[3:0]$601 + attribute \src "issuer_ls180.v:21090.13-21090.31" + wire width 4 $1\src_l_r_src[3:0] + attribute \src "issuer_ls180.v:21442.3-21450.6" + wire width 4 $1\src_l_s_src$next[3:0]$598 + attribute \src "issuer_ls180.v:21094.13-21094.31" + wire width 4 $1\src_l_s_src[3:0] + attribute \src "issuer_ls180.v:21627.3-21636.6" + wire width 64 $1\src_r0$next[63:0]$693 + attribute \src "issuer_ls180.v:21102.14-21102.43" + wire width 64 $1\src_r0[63:0] + attribute \src "issuer_ls180.v:21637.3-21646.6" + wire width 64 $1\src_r1$next[63:0]$696 + attribute \src "issuer_ls180.v:21106.14-21106.43" + wire width 64 $1\src_r1[63:0] + attribute \src "issuer_ls180.v:21647.3-21656.6" + wire $1\src_r2$next[0:0]$699 + attribute \src "issuer_ls180.v:21110.7-21110.20" + wire $1\src_r2[0:0] + attribute \src "issuer_ls180.v:21657.3-21666.6" + wire width 2 $1\src_r3$next[1:0]$702 + attribute \src "issuer_ls180.v:21114.13-21114.26" + wire width 2 $1\src_r3[1:0] + attribute \src "issuer_ls180.v:21478.3-21516.6" + wire width 64 $2\alu_alu0_alu_op__imm_data__data$next[63:0]$645 + attribute \src "issuer_ls180.v:21478.3-21516.6" + wire $2\alu_alu0_alu_op__imm_data__ok$next[0:0]$646 + attribute \src "issuer_ls180.v:21478.3-21516.6" + wire $2\alu_alu0_alu_op__oe__oe$next[0:0]$647 + attribute \src "issuer_ls180.v:21478.3-21516.6" + wire $2\alu_alu0_alu_op__oe__ok$next[0:0]$648 + attribute \src "issuer_ls180.v:21478.3-21516.6" + wire $2\alu_alu0_alu_op__rc__ok$next[0:0]$649 + attribute \src "issuer_ls180.v:21478.3-21516.6" + wire $2\alu_alu0_alu_op__rc__rc$next[0:0]$650 + attribute \src "issuer_ls180.v:21517.3-21538.6" + wire width 64 $2\data_r0__o$next[63:0]$656 + attribute \src "issuer_ls180.v:21517.3-21538.6" + wire $2\data_r0__o_ok$next[0:0]$657 + attribute \src "issuer_ls180.v:21539.3-21560.6" + wire width 4 $2\data_r1__cr_a$next[3:0]$664 + attribute \src "issuer_ls180.v:21539.3-21560.6" + wire $2\data_r1__cr_a_ok$next[0:0]$665 + attribute \src "issuer_ls180.v:21561.3-21582.6" + wire width 2 $2\data_r2__xer_ca$next[1:0]$672 + attribute \src "issuer_ls180.v:21561.3-21582.6" + wire $2\data_r2__xer_ca_ok$next[0:0]$673 + attribute \src "issuer_ls180.v:21583.3-21604.6" + wire width 2 $2\data_r3__xer_ov$next[1:0]$680 + attribute \src "issuer_ls180.v:21583.3-21604.6" + wire $2\data_r3__xer_ov_ok$next[0:0]$681 + attribute \src "issuer_ls180.v:21605.3-21626.6" + wire $2\data_r4__xer_so$next[0:0]$688 + attribute \src "issuer_ls180.v:21605.3-21626.6" + wire $2\data_r4__xer_so_ok$next[0:0]$689 + attribute \src "issuer_ls180.v:21517.3-21538.6" + wire $3\data_r0__o_ok$next[0:0]$658 + attribute \src "issuer_ls180.v:21539.3-21560.6" + wire $3\data_r1__cr_a_ok$next[0:0]$666 + attribute \src "issuer_ls180.v:21561.3-21582.6" + wire $3\data_r2__xer_ca_ok$next[0:0]$674 + attribute \src "issuer_ls180.v:21583.3-21604.6" + wire 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"/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_alu0_alu_op__invert_out$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_alu0_alu_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_alu0_alu_op__is_32bit$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_alu0_alu_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_alu0_alu_op__is_signed$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_alu0_alu_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_alu0_alu_op__oe__oe$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_alu0_alu_op__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_alu0_alu_op__oe__ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_alu0_alu_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_alu0_alu_op__output_carry$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_alu0_alu_op__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_alu0_alu_op__rc__ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_alu0_alu_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_alu0_alu_op__rc__rc$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_alu0_alu_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_alu0_alu_op__write_cr0$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_alu0_alu_op__zero_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_alu0_alu_op__zero_a$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 4 \alu_alu0_cr_a + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" + wire \alu_alu0_n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" + wire \alu_alu0_n_valid_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 \alu_alu0_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" + wire \alu_alu0_p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" + wire \alu_alu0_p_valid_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \alu_alu0_ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \alu_alu0_rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 2 \alu_alu0_xer_ca + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 2 \alu_alu0_xer_ca$2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 2 \alu_alu0_xer_ov + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \alu_alu0_xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire \alu_alu0_xer_so$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:196" + wire \alu_done + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" + wire \alu_done_dly + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" + wire \alu_done_dly$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" + wire \alu_done_rise + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire \alu_l_q_alu + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire \alu_l_r_alu + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire \alu_l_r_alu$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire \alu_l_s_alu + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:197" + wire \alu_pulse + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:198" + wire width 5 \alu_pulsem + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire \alui_l_q_alui + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire \alui_l_r_alui + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire \alui_l_r_alui$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire \alui_l_s_alui + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" + wire input 41 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" + wire input 40 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 32 \cr_a_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107" + wire output 20 \cu_busy_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:108" + wire \cu_done_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:104" + wire \cu_go_die_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:100" + wire input 19 \cu_issue_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 4 input 23 \cu_rd__go_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 4 output 22 \cu_rd__rel_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96" + wire width 4 input 21 \cu_rdmaskn_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:102" + wire \cu_shadown_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 5 input 30 \cu_wr__go_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 5 output 29 \cu_wr__rel_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:97" + wire width 5 \cu_wrmask_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire width 64 \data_r0__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire width 64 \data_r0__o$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire \data_r0__o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire \data_r0__o_ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire width 4 \data_r1__cr_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire width 4 \data_r1__cr_a$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire \data_r1__cr_a_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire \data_r1__cr_a_ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire width 2 \data_r2__xer_ca + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire width 2 \data_r2__xer_ca$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire \data_r2__xer_ca_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire \data_r2__xer_ca_ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire width 2 \data_r3__xer_ov + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire width 2 \data_r3__xer_ov$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire \data_r3__xer_ov_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire \data_r3__xer_ov_ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire \data_r4__xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire \data_r4__xer_so$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire \data_r4__xer_so_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire \data_r4__xer_so_ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 64 output 31 \dest1_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 4 output 33 \dest2_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 2 output 35 \dest3_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 2 output 37 \dest4_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire output 39 \dest5_o + attribute \src "issuer_ls180.v:20453.7-20453.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 28 \o_ok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire \opc_l_q_opc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire \opc_l_r_opc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire \opc_l_r_opc$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire \opc_l_s_opc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire \opc_l_s_opc$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 input 17 \oper_i_alu_alu0__data_len + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 input 2 \oper_i_alu_alu0__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 input 3 \oper_i_alu_alu0__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 4 \oper_i_alu_alu0__imm_data__ok + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 input 13 \oper_i_alu_alu0__input_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 18 \oper_i_alu_alu0__insn + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 input 1 \oper_i_alu_alu0__insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 9 \oper_i_alu_alu0__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 11 \oper_i_alu_alu0__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 15 \oper_i_alu_alu0__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 16 \oper_i_alu_alu0__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 7 \oper_i_alu_alu0__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 8 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parameter \Y_WIDTH 1 + connect \A \xer_ov_ok + connect \B \cu_busy_o + connect \Y $and$issuer_ls180.v:21185$519_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" + cell $and $and$issuer_ls180.v:21186$520 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \xer_so_ok + connect \B \cu_busy_o + connect \Y $and$issuer_ls180.v:21186$520_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" + cell $eq $eq$issuer_ls180.v:21168$502 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$43 + connect \B 1'0 + connect \Y $eq$issuer_ls180.v:21168$502_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" + cell $eq $eq$issuer_ls180.v:21170$504 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cu_wrmask_o + connect \B 1'0 + connect \Y $eq$issuer_ls180.v:21170$504_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:173" + cell $not $not$issuer_ls180.v:21133$467 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \alu_alu0_alu_op__zero_a + connect \Y $not$issuer_ls180.v:21133$467_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:173" + cell $not $not$issuer_ls180.v:21134$468 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \alu_alu0_alu_op__imm_data__ok + connect \Y $not$issuer_ls180.v:21134$468_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" + cell $not $not$issuer_ls180.v:21136$470 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \cu_rdmaskn_i + connect \Y $not$issuer_ls180.v:21136$470_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + cell $not $not$issuer_ls180.v:21151$485 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \all_rd_dly + connect \Y $not$issuer_ls180.v:21151$485_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + cell $not $not$issuer_ls180.v:21153$487 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \alu_done_dly + connect \Y $not$issuer_ls180.v:21153$487_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" + cell $not $not$issuer_ls180.v:21156$490 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \Y_WIDTH 5 + connect \A \cu_wrmask_o + connect \Y $not$issuer_ls180.v:21156$490_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" + cell $not $not$issuer_ls180.v:21159$493 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$24 + connect \Y $not$issuer_ls180.v:21159$493_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" + cell $not $not$issuer_ls180.v:21165$499 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \alu_alu0_n_ready_i + connect \Y $not$issuer_ls180.v:21165$499_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" + cell $not $not$issuer_ls180.v:21180$514 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \cu_rd__rel_o + connect \Y $not$issuer_ls180.v:21180$514_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" + cell $or $or$issuer_ls180.v:21163$497 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$33 + connect \B \$35 + connect \Y $or$issuer_ls180.v:21163$497_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:230" + cell $or $or$issuer_ls180.v:21174$508 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \req_done + connect \B \cu_go_die_i + connect \Y $or$issuer_ls180.v:21174$508_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:231" + cell $or $or$issuer_ls180.v:21175$509 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cu_issue_i + connect \B \cu_go_die_i + connect \Y $or$issuer_ls180.v:21175$509_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:232" + cell $or $or$issuer_ls180.v:21176$510 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 5 + connect \A \cu_wr__go_i + connect \B { \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i } + connect \Y $or$issuer_ls180.v:21176$510_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:233" + cell $or $or$issuer_ls180.v:21177$511 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \cu_rd__go_i + connect \B { \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i } + connect \Y $or$issuer_ls180.v:21177$511_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:253" + cell $or $or$issuer_ls180.v:21181$515 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 5 + connect \A \reset_w + connect \B \prev_wr_go + connect \Y $or$issuer_ls180.v:21181$515_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" + cell $or $or$issuer_ls180.v:21190$524 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \$6 + connect \B \cu_rd__go_i + connect \Y $or$issuer_ls180.v:21190$524_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" + cell $reduce_and $reduce_and$issuer_ls180.v:21129$463 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \$8 + connect \Y $reduce_and$issuer_ls180.v:21129$463_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" + cell $reduce_or $reduce_or$issuer_ls180.v:21158$492 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \$27 + connect \Y $reduce_or$issuer_ls180.v:21158$492_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" + cell $reduce_or $reduce_or$issuer_ls180.v:21161$495 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \cu_wr__go_i + connect \Y $reduce_or$issuer_ls180.v:21161$495_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" + cell $reduce_or $reduce_or$issuer_ls180.v:21162$496 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \prev_wr_go + connect \Y $reduce_or$issuer_ls180.v:21162$496_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:168" + cell $mux $ternary$issuer_ls180.v:21187$521 + parameter \WIDTH 1 + connect \A \src_l_q_src [0] + connect \B \opc_l_q_opc + connect \S \alu_alu0_alu_op__zero_a + connect \Y $ternary$issuer_ls180.v:21187$521_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:169" + cell $mux $ternary$issuer_ls180.v:21188$522 + parameter \WIDTH 64 + connect \A \src1_i + connect \B 64'0000000000000000000000000000000000000000000000000000000000000000 + connect \S \alu_alu0_alu_op__zero_a + connect \Y $ternary$issuer_ls180.v:21188$522_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:168" + cell $mux $ternary$issuer_ls180.v:21189$523 + parameter \WIDTH 1 + connect \A \src_l_q_src [1] + connect \B \opc_l_q_opc + connect \S \alu_alu0_alu_op__imm_data__ok + connect \Y $ternary$issuer_ls180.v:21189$523_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:169" + cell $mux $ternary$issuer_ls180.v:21191$525 + parameter \WIDTH 64 + connect \A \src2_i + connect \B \alu_alu0_alu_op__imm_data__data + connect \S \alu_alu0_alu_op__imm_data__ok + connect \Y $ternary$issuer_ls180.v:21191$525_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + cell $mux $ternary$issuer_ls180.v:21192$526 + parameter \WIDTH 64 + connect \A \src_r0 + connect \B \src_or_imm + connect \S \src_sel + connect \Y $ternary$issuer_ls180.v:21192$526_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + cell $mux $ternary$issuer_ls180.v:21193$527 + parameter \WIDTH 64 + connect \A \src_r1 + connect \B \src_or_imm$88 + connect \S \src_sel$85 + connect \Y $ternary$issuer_ls180.v:21193$527_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + cell $mux $ternary$issuer_ls180.v:21194$528 + parameter \WIDTH 1 + connect \A \src_r2 + connect \B \src3_i + connect \S \src_l_q_src [2] + connect \Y $ternary$issuer_ls180.v:21194$528_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + cell $mux $ternary$issuer_ls180.v:21195$529 + parameter \WIDTH 2 + connect \A \src_r3 + connect \B \src4_i + connect \S \src_l_q_src [3] + connect \Y $ternary$issuer_ls180.v:21195$529_Y + end + attribute \module_not_derived 1 + attribute \src "issuer_ls180.v:21290.12-21329.4" + cell \alu_alu0 \alu_alu0 + connect \alu_op__data_len \alu_alu0_alu_op__data_len + connect \alu_op__fn_unit \alu_alu0_alu_op__fn_unit + connect \alu_op__imm_data__data \alu_alu0_alu_op__imm_data__data + connect \alu_op__imm_data__ok \alu_alu0_alu_op__imm_data__ok + connect \alu_op__input_carry \alu_alu0_alu_op__input_carry + connect \alu_op__insn \alu_alu0_alu_op__insn + connect \alu_op__insn_type \alu_alu0_alu_op__insn_type + connect \alu_op__invert_in \alu_alu0_alu_op__invert_in + connect \alu_op__invert_out \alu_alu0_alu_op__invert_out + connect \alu_op__is_32bit \alu_alu0_alu_op__is_32bit + connect \alu_op__is_signed \alu_alu0_alu_op__is_signed + connect \alu_op__oe__oe \alu_alu0_alu_op__oe__oe + connect \alu_op__oe__ok \alu_alu0_alu_op__oe__ok + connect \alu_op__output_carry \alu_alu0_alu_op__output_carry + connect \alu_op__rc__ok \alu_alu0_alu_op__rc__ok + connect \alu_op__rc__rc \alu_alu0_alu_op__rc__rc + connect \alu_op__write_cr0 \alu_alu0_alu_op__write_cr0 + connect \alu_op__zero_a \alu_alu0_alu_op__zero_a + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \cr_a \alu_alu0_cr_a + connect \cr_a_ok \cr_a_ok + connect \n_ready_i \alu_alu0_n_ready_i + connect \n_valid_o \alu_alu0_n_valid_o + connect \o \alu_alu0_o + connect \o_ok \o_ok + connect \p_ready_o \alu_alu0_p_ready_o + connect \p_valid_i \alu_alu0_p_valid_i + connect \ra \alu_alu0_ra + connect \rb \alu_alu0_rb + connect \xer_ca \alu_alu0_xer_ca + connect \xer_ca$2 \alu_alu0_xer_ca$2 + connect \xer_ca_ok \xer_ca_ok + connect \xer_ov \alu_alu0_xer_ov + connect \xer_ov_ok \xer_ov_ok + connect \xer_so \alu_alu0_xer_so + connect \xer_so$1 \alu_alu0_xer_so$1 + connect \xer_so_ok \xer_so_ok + end + attribute \module_not_derived 1 + attribute \src "issuer_ls180.v:21330.9-21336.4" + cell \alu_l \alu_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_alu \alu_l_q_alu + connect \r_alu \alu_l_r_alu + connect \s_alu \alu_l_s_alu + end + attribute \module_not_derived 1 + attribute \src "issuer_ls180.v:21337.10-21343.4" + cell \alui_l \alui_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_alui \alui_l_q_alui + connect \r_alui \alui_l_r_alui + connect \s_alui \alui_l_s_alui + end + attribute \module_not_derived 1 + attribute \src "issuer_ls180.v:21344.9-21350.4" + cell \opc_l \opc_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_opc \opc_l_q_opc + connect \r_opc \opc_l_r_opc + connect \s_opc \opc_l_s_opc + end + attribute \module_not_derived 1 + attribute \src "issuer_ls180.v:21351.9-21357.4" + cell \req_l \req_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_req \req_l_q_req + connect \r_req \req_l_r_req + connect \s_req \req_l_s_req + end + attribute \module_not_derived 1 + attribute \src "issuer_ls180.v:21358.9-21364.4" + cell \rok_l \rok_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_rdok \rok_l_q_rdok + connect \r_rdok \rok_l_r_rdok + connect \s_rdok \rok_l_s_rdok + end + attribute \module_not_derived 1 + attribute \src "issuer_ls180.v:21365.9-21370.4" + cell \rst_l \rst_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \r_rst \rst_l_r_rst + connect \s_rst \rst_l_s_rst + end + attribute \module_not_derived 1 + attribute \src "issuer_ls180.v:21371.9-21377.4" + cell \src_l \src_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_src \src_l_q_src + connect \r_src \src_l_r_src + connect \s_src \src_l_s_src + end + attribute \src "issuer_ls180.v:20453.7-20453.20" + process $proc$issuer_ls180.v:20453$717 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "issuer_ls180.v:20591.7-20591.24" + process $proc$issuer_ls180.v:20591$718 + assign { } { } + assign $1\all_rd_dly[0:0] 1'0 + sync always + sync init + update \all_rd_dly $1\all_rd_dly[0:0] + end + attribute \src "issuer_ls180.v:20599.13-20599.45" + process $proc$issuer_ls180.v:20599$719 + assign { } { } + assign $1\alu_alu0_alu_op__data_len[3:0] 4'0000 + sync always + sync init + update \alu_alu0_alu_op__data_len $1\alu_alu0_alu_op__data_len[3:0] + end + attribute \src "issuer_ls180.v:20616.14-20616.48" + process $proc$issuer_ls180.v:20616$720 + assign { } { } + assign $1\alu_alu0_alu_op__fn_unit[11:0] 12'000000000000 + sync always + sync init + update \alu_alu0_alu_op__fn_unit $1\alu_alu0_alu_op__fn_unit[11:0] + end + attribute \src "issuer_ls180.v:20620.14-20620.68" + process $proc$issuer_ls180.v:20620$721 + assign { } { } + assign $1\alu_alu0_alu_op__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \alu_alu0_alu_op__imm_data__data $1\alu_alu0_alu_op__imm_data__data[63:0] + end + attribute \src "issuer_ls180.v:20624.7-20624.43" + process $proc$issuer_ls180.v:20624$722 + assign { } { } + assign $1\alu_alu0_alu_op__imm_data__ok[0:0] 1'0 + sync always + sync init + update \alu_alu0_alu_op__imm_data__ok $1\alu_alu0_alu_op__imm_data__ok[0:0] + end + attribute \src "issuer_ls180.v:20632.13-20632.48" + process $proc$issuer_ls180.v:20632$723 + assign { } { } + assign $1\alu_alu0_alu_op__input_carry[1:0] 2'00 + sync always + sync init + update \alu_alu0_alu_op__input_carry $1\alu_alu0_alu_op__input_carry[1:0] + end + attribute \src "issuer_ls180.v:20636.14-20636.43" + process $proc$issuer_ls180.v:20636$724 + assign { } { } + assign $1\alu_alu0_alu_op__insn[31:0] 0 + sync always + sync init + update \alu_alu0_alu_op__insn $1\alu_alu0_alu_op__insn[31:0] + end + attribute \src "issuer_ls180.v:20714.13-20714.47" + process $proc$issuer_ls180.v:20714$725 + assign { } { } + assign $1\alu_alu0_alu_op__insn_type[6:0] 7'0000000 + sync always + sync init + update \alu_alu0_alu_op__insn_type $1\alu_alu0_alu_op__insn_type[6:0] + end + attribute \src "issuer_ls180.v:20718.7-20718.40" + process $proc$issuer_ls180.v:20718$726 + assign { } { } + assign $1\alu_alu0_alu_op__invert_in[0:0] 1'0 + sync always + sync init + update \alu_alu0_alu_op__invert_in $1\alu_alu0_alu_op__invert_in[0:0] + end + attribute \src "issuer_ls180.v:20722.7-20722.41" + process $proc$issuer_ls180.v:20722$727 + assign { } { } + assign $1\alu_alu0_alu_op__invert_out[0:0] 1'0 + sync always + sync init + update \alu_alu0_alu_op__invert_out $1\alu_alu0_alu_op__invert_out[0:0] + end + attribute \src "issuer_ls180.v:20726.7-20726.39" + process $proc$issuer_ls180.v:20726$728 + assign { } { } + assign $1\alu_alu0_alu_op__is_32bit[0:0] 1'0 + sync always + sync init + update \alu_alu0_alu_op__is_32bit $1\alu_alu0_alu_op__is_32bit[0:0] + end + attribute \src "issuer_ls180.v:20730.7-20730.40" + process $proc$issuer_ls180.v:20730$729 + assign { } { } + assign $1\alu_alu0_alu_op__is_signed[0:0] 1'0 + sync always + sync init + update \alu_alu0_alu_op__is_signed $1\alu_alu0_alu_op__is_signed[0:0] + end + attribute \src "issuer_ls180.v:20734.7-20734.37" + process $proc$issuer_ls180.v:20734$730 + assign { } { } + assign $1\alu_alu0_alu_op__oe__oe[0:0] 1'0 + sync always + sync init + update \alu_alu0_alu_op__oe__oe $1\alu_alu0_alu_op__oe__oe[0:0] + end + attribute \src "issuer_ls180.v:20738.7-20738.37" + process $proc$issuer_ls180.v:20738$731 + assign { } { } + assign $1\alu_alu0_alu_op__oe__ok[0:0] 1'0 + sync always + sync init + update \alu_alu0_alu_op__oe__ok $1\alu_alu0_alu_op__oe__ok[0:0] + end + attribute \src "issuer_ls180.v:20742.7-20742.43" + process $proc$issuer_ls180.v:20742$732 + assign { } { } + assign $1\alu_alu0_alu_op__output_carry[0:0] 1'0 + sync always + sync init + update \alu_alu0_alu_op__output_carry $1\alu_alu0_alu_op__output_carry[0:0] + end + attribute \src "issuer_ls180.v:20746.7-20746.37" + process $proc$issuer_ls180.v:20746$733 + assign { } { } + assign $1\alu_alu0_alu_op__rc__ok[0:0] 1'0 + sync always + sync init + update \alu_alu0_alu_op__rc__ok $1\alu_alu0_alu_op__rc__ok[0:0] + end + attribute \src "issuer_ls180.v:20750.7-20750.37" + process $proc$issuer_ls180.v:20750$734 + assign { } { } + assign $1\alu_alu0_alu_op__rc__rc[0:0] 1'0 + sync always + sync init + update \alu_alu0_alu_op__rc__rc $1\alu_alu0_alu_op__rc__rc[0:0] + end + attribute \src "issuer_ls180.v:20754.7-20754.40" + process $proc$issuer_ls180.v:20754$735 + assign { } { } + assign $1\alu_alu0_alu_op__write_cr0[0:0] 1'0 + sync always + sync init + update \alu_alu0_alu_op__write_cr0 $1\alu_alu0_alu_op__write_cr0[0:0] + end + attribute \src "issuer_ls180.v:20758.7-20758.37" + process $proc$issuer_ls180.v:20758$736 + assign { } { } + assign $1\alu_alu0_alu_op__zero_a[0:0] 1'0 + sync always + sync init + update \alu_alu0_alu_op__zero_a $1\alu_alu0_alu_op__zero_a[0:0] + end + attribute \src "issuer_ls180.v:20790.7-20790.26" + process $proc$issuer_ls180.v:20790$737 + assign { } { } + assign $1\alu_done_dly[0:0] 1'0 + sync always + sync init + update \alu_done_dly $1\alu_done_dly[0:0] + end + attribute \src "issuer_ls180.v:20798.7-20798.25" + process $proc$issuer_ls180.v:20798$738 + assign { } { } + assign $1\alu_l_r_alu[0:0] 1'1 + sync always + sync init + update \alu_l_r_alu $1\alu_l_r_alu[0:0] + end + attribute \src "issuer_ls180.v:20810.7-20810.27" + process $proc$issuer_ls180.v:20810$739 + assign { } { } + assign $1\alui_l_r_alui[0:0] 1'1 + sync always + sync init + update \alui_l_r_alui $1\alui_l_r_alui[0:0] + end + attribute \src "issuer_ls180.v:20844.14-20844.47" + process $proc$issuer_ls180.v:20844$740 + assign { } { } + assign $1\data_r0__o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \data_r0__o $1\data_r0__o[63:0] + end + attribute \src "issuer_ls180.v:20848.7-20848.27" + process $proc$issuer_ls180.v:20848$741 + assign { } { } + assign $1\data_r0__o_ok[0:0] 1'0 + sync always + sync init + update \data_r0__o_ok $1\data_r0__o_ok[0:0] + end + attribute \src "issuer_ls180.v:20852.13-20852.33" + process $proc$issuer_ls180.v:20852$742 + assign { } { } + assign $1\data_r1__cr_a[3:0] 4'0000 + sync always + sync init + update \data_r1__cr_a $1\data_r1__cr_a[3:0] + end + attribute \src "issuer_ls180.v:20856.7-20856.30" + process $proc$issuer_ls180.v:20856$743 + assign { } { } + assign $1\data_r1__cr_a_ok[0:0] 1'0 + sync always + sync init + update \data_r1__cr_a_ok $1\data_r1__cr_a_ok[0:0] + end + attribute \src "issuer_ls180.v:20860.13-20860.35" + process $proc$issuer_ls180.v:20860$744 + assign { } { } + assign $1\data_r2__xer_ca[1:0] 2'00 + sync always + sync init + update \data_r2__xer_ca $1\data_r2__xer_ca[1:0] + end + attribute \src "issuer_ls180.v:20864.7-20864.32" + process $proc$issuer_ls180.v:20864$745 + assign { } { } + assign $1\data_r2__xer_ca_ok[0:0] 1'0 + sync always + sync init + update \data_r2__xer_ca_ok $1\data_r2__xer_ca_ok[0:0] + end + attribute \src "issuer_ls180.v:20868.13-20868.35" + process $proc$issuer_ls180.v:20868$746 + assign { } { } + assign $1\data_r3__xer_ov[1:0] 2'00 + sync always + sync init + update \data_r3__xer_ov $1\data_r3__xer_ov[1:0] + end + attribute \src "issuer_ls180.v:20872.7-20872.32" + process $proc$issuer_ls180.v:20872$747 + assign { } { } + assign $1\data_r3__xer_ov_ok[0:0] 1'0 + sync always + sync init + update \data_r3__xer_ov_ok $1\data_r3__xer_ov_ok[0:0] + end + attribute \src "issuer_ls180.v:20876.7-20876.29" + process $proc$issuer_ls180.v:20876$748 + assign { } { } + assign $1\data_r4__xer_so[0:0] 1'0 + sync always + sync init + update \data_r4__xer_so $1\data_r4__xer_so[0:0] + end + attribute \src "issuer_ls180.v:20880.7-20880.32" + process $proc$issuer_ls180.v:20880$749 + assign { } { } + assign $1\data_r4__xer_so_ok[0:0] 1'0 + sync always + sync init + update \data_r4__xer_so_ok $1\data_r4__xer_so_ok[0:0] + end + attribute \src "issuer_ls180.v:20903.7-20903.25" + process $proc$issuer_ls180.v:20903$750 + assign { } { } + assign $1\opc_l_r_opc[0:0] 1'1 + sync always + sync init + update \opc_l_r_opc $1\opc_l_r_opc[0:0] + end + attribute \src "issuer_ls180.v:20907.7-20907.25" + process $proc$issuer_ls180.v:20907$751 + assign { } { } + assign $1\opc_l_s_opc[0:0] 1'0 + sync always + sync init + update \opc_l_s_opc $1\opc_l_s_opc[0:0] + end + attribute \src "issuer_ls180.v:21038.13-21038.31" + process $proc$issuer_ls180.v:21038$752 + assign { } { } + assign $1\prev_wr_go[4:0] 5'00000 + sync always + sync init + update \prev_wr_go $1\prev_wr_go[4:0] + end + attribute \src "issuer_ls180.v:21046.13-21046.32" + process $proc$issuer_ls180.v:21046$753 + assign { } { } + assign $1\req_l_r_req[4:0] 5'11111 + sync always + sync init + update \req_l_r_req $1\req_l_r_req[4:0] + end + attribute \src "issuer_ls180.v:21050.13-21050.32" + process $proc$issuer_ls180.v:21050$754 + assign { } { } + assign $1\req_l_s_req[4:0] 5'00000 + sync always + sync init + update \req_l_s_req $1\req_l_s_req[4:0] + end + attribute \src "issuer_ls180.v:21062.7-21062.26" + process $proc$issuer_ls180.v:21062$755 + assign { } { } + assign $1\rok_l_r_rdok[0:0] 1'1 + sync always + sync init + update \rok_l_r_rdok $1\rok_l_r_rdok[0:0] + end + attribute \src "issuer_ls180.v:21066.7-21066.26" + process $proc$issuer_ls180.v:21066$756 + assign { } { } + assign $1\rok_l_s_rdok[0:0] 1'0 + sync always + sync init + update \rok_l_s_rdok $1\rok_l_s_rdok[0:0] + end + attribute \src "issuer_ls180.v:21070.7-21070.25" + process $proc$issuer_ls180.v:21070$757 + assign { } { } + assign $1\rst_l_r_rst[0:0] 1'1 + sync always + sync init + update \rst_l_r_rst $1\rst_l_r_rst[0:0] + end + attribute \src "issuer_ls180.v:21074.7-21074.25" + process $proc$issuer_ls180.v:21074$758 + assign { } { } + assign $1\rst_l_s_rst[0:0] 1'0 + sync always + sync init + update \rst_l_s_rst $1\rst_l_s_rst[0:0] + end + attribute \src "issuer_ls180.v:21090.13-21090.31" + process $proc$issuer_ls180.v:21090$759 + assign { } { } + assign $1\src_l_r_src[3:0] 4'1111 + sync always + sync init + update \src_l_r_src $1\src_l_r_src[3:0] + end + attribute \src "issuer_ls180.v:21094.13-21094.31" + process $proc$issuer_ls180.v:21094$760 + assign { } { } + assign $1\src_l_s_src[3:0] 4'0000 + sync always + sync init + update \src_l_s_src $1\src_l_s_src[3:0] + end + attribute \src "issuer_ls180.v:21102.14-21102.43" + process $proc$issuer_ls180.v:21102$761 + assign { } { } + assign $1\src_r0[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \src_r0 $1\src_r0[63:0] + end + attribute \src "issuer_ls180.v:21106.14-21106.43" + process $proc$issuer_ls180.v:21106$762 + assign { } { } + assign $1\src_r1[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \src_r1 $1\src_r1[63:0] + end + attribute \src "issuer_ls180.v:21110.7-21110.20" + process $proc$issuer_ls180.v:21110$763 + assign { } { } + assign $1\src_r2[0:0] 1'0 + sync always + sync init + update \src_r2 $1\src_r2[0:0] + end + attribute \src "issuer_ls180.v:21114.13-21114.26" + process $proc$issuer_ls180.v:21114$764 + assign { } { } + assign $1\src_r3[1:0] 2'00 + sync always + sync init + update \src_r3 $1\src_r3[1:0] + end + attribute \src "issuer_ls180.v:21196.3-21197.39" + process $proc$issuer_ls180.v:21196$530 + assign { } { } + assign $0\alu_l_r_alu[0:0] \alu_l_r_alu$next + sync posedge \coresync_clk + update \alu_l_r_alu $0\alu_l_r_alu[0:0] + end + attribute \src "issuer_ls180.v:21198.3-21199.43" + process $proc$issuer_ls180.v:21198$531 + assign { } { } + assign $0\alui_l_r_alui[0:0] \alui_l_r_alui$next + sync posedge \coresync_clk + update \alui_l_r_alui $0\alui_l_r_alui[0:0] + end + attribute \src "issuer_ls180.v:21200.3-21201.29" + process $proc$issuer_ls180.v:21200$532 + assign { } { } + assign $0\src_r3[1:0] \src_r3$next + sync posedge \coresync_clk + update \src_r3 $0\src_r3[1:0] + end + attribute \src "issuer_ls180.v:21202.3-21203.29" + process $proc$issuer_ls180.v:21202$533 + assign { } { } + assign $0\src_r2[0:0] \src_r2$next + sync posedge \coresync_clk + update \src_r2 $0\src_r2[0:0] + end + attribute \src "issuer_ls180.v:21204.3-21205.29" + process $proc$issuer_ls180.v:21204$534 + assign { } { } + assign $0\src_r1[63:0] \src_r1$next + sync posedge \coresync_clk + update \src_r1 $0\src_r1[63:0] + end + attribute \src "issuer_ls180.v:21206.3-21207.29" + process $proc$issuer_ls180.v:21206$535 + assign { } { } + assign $0\src_r0[63:0] \src_r0$next + sync posedge \coresync_clk + update \src_r0 $0\src_r0[63:0] + end + attribute \src "issuer_ls180.v:21208.3-21209.47" + process $proc$issuer_ls180.v:21208$536 + assign { } { } + assign $0\data_r4__xer_so[0:0] \data_r4__xer_so$next + sync posedge \coresync_clk + update \data_r4__xer_so $0\data_r4__xer_so[0:0] + end + attribute \src "issuer_ls180.v:21210.3-21211.53" + process $proc$issuer_ls180.v:21210$537 + assign { } { } + assign $0\data_r4__xer_so_ok[0:0] \data_r4__xer_so_ok$next + sync posedge \coresync_clk + update \data_r4__xer_so_ok $0\data_r4__xer_so_ok[0:0] + end + attribute \src "issuer_ls180.v:21212.3-21213.47" + process $proc$issuer_ls180.v:21212$538 + assign { } { } + assign $0\data_r3__xer_ov[1:0] \data_r3__xer_ov$next + sync posedge \coresync_clk + update \data_r3__xer_ov $0\data_r3__xer_ov[1:0] + end + attribute \src "issuer_ls180.v:21214.3-21215.53" + process $proc$issuer_ls180.v:21214$539 + assign { } { } + assign $0\data_r3__xer_ov_ok[0:0] \data_r3__xer_ov_ok$next + sync posedge \coresync_clk + update \data_r3__xer_ov_ok $0\data_r3__xer_ov_ok[0:0] + end + attribute \src "issuer_ls180.v:21216.3-21217.47" + process $proc$issuer_ls180.v:21216$540 + assign { } { } + assign $0\data_r2__xer_ca[1:0] \data_r2__xer_ca$next + sync posedge \coresync_clk + update \data_r2__xer_ca $0\data_r2__xer_ca[1:0] + end + attribute \src "issuer_ls180.v:21218.3-21219.53" + process $proc$issuer_ls180.v:21218$541 + assign { } { } + assign $0\data_r2__xer_ca_ok[0:0] \data_r2__xer_ca_ok$next + sync posedge \coresync_clk + update \data_r2__xer_ca_ok $0\data_r2__xer_ca_ok[0:0] + end + attribute \src "issuer_ls180.v:21220.3-21221.43" + process $proc$issuer_ls180.v:21220$542 + assign { } { } + assign $0\data_r1__cr_a[3:0] \data_r1__cr_a$next + sync posedge \coresync_clk + update \data_r1__cr_a $0\data_r1__cr_a[3:0] + end + attribute \src "issuer_ls180.v:21222.3-21223.49" + process $proc$issuer_ls180.v:21222$543 + assign { } { } + assign $0\data_r1__cr_a_ok[0:0] \data_r1__cr_a_ok$next + sync posedge \coresync_clk + update \data_r1__cr_a_ok $0\data_r1__cr_a_ok[0:0] + end + attribute \src "issuer_ls180.v:21224.3-21225.37" + process $proc$issuer_ls180.v:21224$544 + assign { } { } + assign $0\data_r0__o[63:0] \data_r0__o$next + sync posedge \coresync_clk + update \data_r0__o $0\data_r0__o[63:0] + end + attribute \src "issuer_ls180.v:21226.3-21227.43" + process $proc$issuer_ls180.v:21226$545 + assign { } { } + assign $0\data_r0__o_ok[0:0] \data_r0__o_ok$next + sync posedge \coresync_clk + update \data_r0__o_ok $0\data_r0__o_ok[0:0] + end + attribute \src "issuer_ls180.v:21228.3-21229.69" + process $proc$issuer_ls180.v:21228$546 + assign { } { } + assign $0\alu_alu0_alu_op__insn_type[6:0] \alu_alu0_alu_op__insn_type$next + sync posedge \coresync_clk + update \alu_alu0_alu_op__insn_type $0\alu_alu0_alu_op__insn_type[6:0] + end + attribute \src "issuer_ls180.v:21230.3-21231.65" + process $proc$issuer_ls180.v:21230$547 + assign { } { } + assign $0\alu_alu0_alu_op__fn_unit[11:0] \alu_alu0_alu_op__fn_unit$next + sync posedge \coresync_clk + update \alu_alu0_alu_op__fn_unit $0\alu_alu0_alu_op__fn_unit[11:0] + end + attribute \src "issuer_ls180.v:21232.3-21233.79" + process $proc$issuer_ls180.v:21232$548 + assign { } { } + assign $0\alu_alu0_alu_op__imm_data__data[63:0] \alu_alu0_alu_op__imm_data__data$next + sync posedge \coresync_clk + update \alu_alu0_alu_op__imm_data__data $0\alu_alu0_alu_op__imm_data__data[63:0] + end + attribute \src "issuer_ls180.v:21234.3-21235.75" + process $proc$issuer_ls180.v:21234$549 + assign { } { } + assign $0\alu_alu0_alu_op__imm_data__ok[0:0] \alu_alu0_alu_op__imm_data__ok$next + sync posedge \coresync_clk + update \alu_alu0_alu_op__imm_data__ok $0\alu_alu0_alu_op__imm_data__ok[0:0] + end + attribute \src "issuer_ls180.v:21236.3-21237.63" + process $proc$issuer_ls180.v:21236$550 + assign { } { } + assign $0\alu_alu0_alu_op__rc__rc[0:0] \alu_alu0_alu_op__rc__rc$next + sync posedge \coresync_clk + update \alu_alu0_alu_op__rc__rc $0\alu_alu0_alu_op__rc__rc[0:0] + end + attribute \src "issuer_ls180.v:21238.3-21239.63" + process $proc$issuer_ls180.v:21238$551 + assign { } { } + assign $0\alu_alu0_alu_op__rc__ok[0:0] \alu_alu0_alu_op__rc__ok$next + sync posedge \coresync_clk + update \alu_alu0_alu_op__rc__ok $0\alu_alu0_alu_op__rc__ok[0:0] + end + attribute \src "issuer_ls180.v:21240.3-21241.63" + process $proc$issuer_ls180.v:21240$552 + assign { } { } + assign $0\alu_alu0_alu_op__oe__oe[0:0] \alu_alu0_alu_op__oe__oe$next + sync posedge \coresync_clk + update \alu_alu0_alu_op__oe__oe $0\alu_alu0_alu_op__oe__oe[0:0] + end + attribute \src "issuer_ls180.v:21242.3-21243.63" + process $proc$issuer_ls180.v:21242$553 + assign { } { } + assign $0\alu_alu0_alu_op__oe__ok[0:0] \alu_alu0_alu_op__oe__ok$next + sync posedge \coresync_clk + update \alu_alu0_alu_op__oe__ok $0\alu_alu0_alu_op__oe__ok[0:0] + end + attribute \src "issuer_ls180.v:21244.3-21245.69" + process $proc$issuer_ls180.v:21244$554 + assign { } { } + assign $0\alu_alu0_alu_op__invert_in[0:0] \alu_alu0_alu_op__invert_in$next + sync posedge \coresync_clk + update \alu_alu0_alu_op__invert_in $0\alu_alu0_alu_op__invert_in[0:0] + end + attribute \src "issuer_ls180.v:21246.3-21247.63" + process $proc$issuer_ls180.v:21246$555 + assign { } { } + assign $0\alu_alu0_alu_op__zero_a[0:0] \alu_alu0_alu_op__zero_a$next + sync posedge \coresync_clk + update \alu_alu0_alu_op__zero_a $0\alu_alu0_alu_op__zero_a[0:0] + end + attribute \src "issuer_ls180.v:21248.3-21249.71" + process $proc$issuer_ls180.v:21248$556 + assign { } { } + assign $0\alu_alu0_alu_op__invert_out[0:0] \alu_alu0_alu_op__invert_out$next + sync posedge \coresync_clk + update \alu_alu0_alu_op__invert_out $0\alu_alu0_alu_op__invert_out[0:0] + end + attribute \src "issuer_ls180.v:21250.3-21251.69" + process $proc$issuer_ls180.v:21250$557 + assign { } { } + assign $0\alu_alu0_alu_op__write_cr0[0:0] \alu_alu0_alu_op__write_cr0$next + sync posedge \coresync_clk + update \alu_alu0_alu_op__write_cr0 $0\alu_alu0_alu_op__write_cr0[0:0] + end + attribute \src "issuer_ls180.v:21252.3-21253.73" + process $proc$issuer_ls180.v:21252$558 + assign { } { } + assign $0\alu_alu0_alu_op__input_carry[1:0] \alu_alu0_alu_op__input_carry$next + sync posedge \coresync_clk + update \alu_alu0_alu_op__input_carry $0\alu_alu0_alu_op__input_carry[1:0] + end + attribute \src "issuer_ls180.v:21254.3-21255.75" + process $proc$issuer_ls180.v:21254$559 + assign { } { } + assign $0\alu_alu0_alu_op__output_carry[0:0] \alu_alu0_alu_op__output_carry$next + sync posedge \coresync_clk + update \alu_alu0_alu_op__output_carry $0\alu_alu0_alu_op__output_carry[0:0] + end + attribute \src "issuer_ls180.v:21256.3-21257.67" + process $proc$issuer_ls180.v:21256$560 + assign { } { } + assign $0\alu_alu0_alu_op__is_32bit[0:0] \alu_alu0_alu_op__is_32bit$next + sync posedge \coresync_clk + update \alu_alu0_alu_op__is_32bit $0\alu_alu0_alu_op__is_32bit[0:0] + end + attribute \src "issuer_ls180.v:21258.3-21259.69" + process $proc$issuer_ls180.v:21258$561 + assign { } { } + assign $0\alu_alu0_alu_op__is_signed[0:0] \alu_alu0_alu_op__is_signed$next + sync posedge \coresync_clk + update \alu_alu0_alu_op__is_signed $0\alu_alu0_alu_op__is_signed[0:0] + end + attribute \src "issuer_ls180.v:21260.3-21261.67" + process $proc$issuer_ls180.v:21260$562 + assign { } { } + assign $0\alu_alu0_alu_op__data_len[3:0] \alu_alu0_alu_op__data_len$next + sync posedge \coresync_clk + update \alu_alu0_alu_op__data_len $0\alu_alu0_alu_op__data_len[3:0] + end + attribute \src "issuer_ls180.v:21262.3-21263.59" + process $proc$issuer_ls180.v:21262$563 + assign { } { } + assign $0\alu_alu0_alu_op__insn[31:0] \alu_alu0_alu_op__insn$next + sync posedge \coresync_clk + update \alu_alu0_alu_op__insn $0\alu_alu0_alu_op__insn[31:0] + end + attribute \src "issuer_ls180.v:21264.3-21265.39" + process $proc$issuer_ls180.v:21264$564 + assign { } { } + assign $0\req_l_r_req[4:0] \req_l_r_req$next + sync posedge \coresync_clk + update \req_l_r_req $0\req_l_r_req[4:0] + end + attribute \src "issuer_ls180.v:21266.3-21267.39" + process $proc$issuer_ls180.v:21266$565 + assign { } { } + assign $0\req_l_s_req[4:0] \req_l_s_req$next + sync posedge \coresync_clk + update \req_l_s_req $0\req_l_s_req[4:0] + end + attribute \src "issuer_ls180.v:21268.3-21269.39" + process $proc$issuer_ls180.v:21268$566 + assign { } { } + assign $0\src_l_r_src[3:0] \src_l_r_src$next + sync posedge \coresync_clk + update \src_l_r_src $0\src_l_r_src[3:0] + end + attribute \src "issuer_ls180.v:21270.3-21271.39" + process $proc$issuer_ls180.v:21270$567 + assign { } { } + assign $0\src_l_s_src[3:0] \src_l_s_src$next + sync posedge \coresync_clk + update \src_l_s_src $0\src_l_s_src[3:0] + end + attribute \src "issuer_ls180.v:21272.3-21273.39" + process $proc$issuer_ls180.v:21272$568 + assign { } { } + assign $0\opc_l_r_opc[0:0] \opc_l_r_opc$next + sync posedge \coresync_clk + update \opc_l_r_opc $0\opc_l_r_opc[0:0] + end + attribute \src "issuer_ls180.v:21274.3-21275.39" + process $proc$issuer_ls180.v:21274$569 + assign { } { } + assign $0\opc_l_s_opc[0:0] \opc_l_s_opc$next + sync posedge \coresync_clk + update \opc_l_s_opc $0\opc_l_s_opc[0:0] + end + attribute \src "issuer_ls180.v:21276.3-21277.39" + process $proc$issuer_ls180.v:21276$570 + assign { } { } + assign $0\rst_l_r_rst[0:0] \rst_l_r_rst$next + sync posedge \coresync_clk + update \rst_l_r_rst $0\rst_l_r_rst[0:0] + end + attribute \src "issuer_ls180.v:21278.3-21279.39" + process $proc$issuer_ls180.v:21278$571 + assign { } { } + assign $0\rst_l_s_rst[0:0] \rst_l_s_rst$next + sync posedge \coresync_clk + update \rst_l_s_rst $0\rst_l_s_rst[0:0] + end + attribute \src "issuer_ls180.v:21280.3-21281.41" + process $proc$issuer_ls180.v:21280$572 + assign { } { } + assign $0\rok_l_r_rdok[0:0] \rok_l_r_rdok$next + sync posedge \coresync_clk + update \rok_l_r_rdok $0\rok_l_r_rdok[0:0] + end + attribute \src "issuer_ls180.v:21282.3-21283.41" + process $proc$issuer_ls180.v:21282$573 + assign { } { } + assign $0\rok_l_s_rdok[0:0] \rok_l_s_rdok$next + sync posedge \coresync_clk + update \rok_l_s_rdok $0\rok_l_s_rdok[0:0] + end + attribute \src "issuer_ls180.v:21284.3-21285.37" + process $proc$issuer_ls180.v:21284$574 + assign { } { } + assign $0\prev_wr_go[4:0] \prev_wr_go$next + sync posedge \coresync_clk + update \prev_wr_go $0\prev_wr_go[4:0] + end + attribute \src "issuer_ls180.v:21286.3-21287.40" + process $proc$issuer_ls180.v:21286$575 + assign { } { } + assign $0\alu_done_dly[0:0] \alu_alu0_n_valid_o + sync posedge \coresync_clk + update \alu_done_dly $0\alu_done_dly[0:0] + end + attribute \src "issuer_ls180.v:21288.3-21289.25" + process $proc$issuer_ls180.v:21288$576 + assign { } { } + assign $0\all_rd_dly[0:0] \$11 + sync posedge \coresync_clk + update \all_rd_dly $0\all_rd_dly[0:0] + end + attribute \src "issuer_ls180.v:21378.3-21387.6" + process $proc$issuer_ls180.v:21378$577 + assign { } { } + assign { } { } + assign $0\req_done[0:0] $1\req_done[0:0] + attribute \src "issuer_ls180.v:21379.5-21379.29" + switch \initial + attribute \src "issuer_ls180.v:21379.9-21379.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" + switch \$55 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\req_done[0:0] 1'1 + case + assign $1\req_done[0:0] \$47 + end + sync always + update \req_done $0\req_done[0:0] + end + attribute \src "issuer_ls180.v:21388.3-21396.6" + process $proc$issuer_ls180.v:21388$578 + assign { } { } + assign { } { } + assign $0\rok_l_s_rdok$next[0:0]$579 $1\rok_l_s_rdok$next[0:0]$580 + attribute \src "issuer_ls180.v:21389.5-21389.29" + switch \initial + attribute \src "issuer_ls180.v:21389.9-21389.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\rok_l_s_rdok$next[0:0]$580 1'0 + case + assign $1\rok_l_s_rdok$next[0:0]$580 \cu_issue_i + end + sync always + update \rok_l_s_rdok$next $0\rok_l_s_rdok$next[0:0]$579 + end + attribute \src "issuer_ls180.v:21397.3-21405.6" + process $proc$issuer_ls180.v:21397$581 + assign { } { } + assign { } { } + assign $0\rok_l_r_rdok$next[0:0]$582 $1\rok_l_r_rdok$next[0:0]$583 + attribute \src "issuer_ls180.v:21398.5-21398.29" + switch \initial + attribute \src "issuer_ls180.v:21398.9-21398.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\rok_l_r_rdok$next[0:0]$583 1'1 + case + assign $1\rok_l_r_rdok$next[0:0]$583 \$65 + end + sync always + update \rok_l_r_rdok$next $0\rok_l_r_rdok$next[0:0]$582 + end + attribute \src "issuer_ls180.v:21406.3-21414.6" + process $proc$issuer_ls180.v:21406$584 + assign { } { } + assign { } { } + assign $0\rst_l_s_rst$next[0:0]$585 $1\rst_l_s_rst$next[0:0]$586 + attribute \src "issuer_ls180.v:21407.5-21407.29" + switch \initial + attribute \src "issuer_ls180.v:21407.9-21407.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\rst_l_s_rst$next[0:0]$586 1'0 + case + assign $1\rst_l_s_rst$next[0:0]$586 \all_rd + end + sync always + update \rst_l_s_rst$next $0\rst_l_s_rst$next[0:0]$585 + end + attribute \src "issuer_ls180.v:21415.3-21423.6" + process $proc$issuer_ls180.v:21415$587 + assign { } { } + assign { } { } + assign $0\rst_l_r_rst$next[0:0]$588 $1\rst_l_r_rst$next[0:0]$589 + attribute \src "issuer_ls180.v:21416.5-21416.29" + switch \initial + attribute \src "issuer_ls180.v:21416.9-21416.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\rst_l_r_rst$next[0:0]$589 1'1 + case + assign $1\rst_l_r_rst$next[0:0]$589 \rst_r + end + sync always + update \rst_l_r_rst$next $0\rst_l_r_rst$next[0:0]$588 + end + attribute \src "issuer_ls180.v:21424.3-21432.6" + process $proc$issuer_ls180.v:21424$590 + assign { } { } + assign { } { } + assign $0\opc_l_s_opc$next[0:0]$591 $1\opc_l_s_opc$next[0:0]$592 + attribute \src "issuer_ls180.v:21425.5-21425.29" + switch \initial + attribute \src "issuer_ls180.v:21425.9-21425.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\opc_l_s_opc$next[0:0]$592 1'0 + case + assign $1\opc_l_s_opc$next[0:0]$592 \cu_issue_i + end + sync always + update \opc_l_s_opc$next $0\opc_l_s_opc$next[0:0]$591 + end + attribute \src "issuer_ls180.v:21433.3-21441.6" + process $proc$issuer_ls180.v:21433$593 + assign { } { } + assign { } { } + assign $0\opc_l_r_opc$next[0:0]$594 $1\opc_l_r_opc$next[0:0]$595 + attribute \src "issuer_ls180.v:21434.5-21434.29" + switch \initial + attribute \src "issuer_ls180.v:21434.9-21434.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\opc_l_r_opc$next[0:0]$595 1'1 + case + assign $1\opc_l_r_opc$next[0:0]$595 \req_done + end + sync always + update \opc_l_r_opc$next $0\opc_l_r_opc$next[0:0]$594 + end + attribute \src "issuer_ls180.v:21442.3-21450.6" + process $proc$issuer_ls180.v:21442$596 + assign { } { } + assign { } { } + assign $0\src_l_s_src$next[3:0]$597 $1\src_l_s_src$next[3:0]$598 + attribute \src "issuer_ls180.v:21443.5-21443.29" + switch \initial + attribute \src "issuer_ls180.v:21443.9-21443.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\src_l_s_src$next[3:0]$598 4'0000 + case + assign $1\src_l_s_src$next[3:0]$598 { \cu_issue_i \cu_issue_i \cu_issue_i \cu_issue_i } + end + sync always + update \src_l_s_src$next $0\src_l_s_src$next[3:0]$597 + end + attribute \src "issuer_ls180.v:21451.3-21459.6" + process $proc$issuer_ls180.v:21451$599 + assign { } { } + assign { } { } + assign $0\src_l_r_src$next[3:0]$600 $1\src_l_r_src$next[3:0]$601 + attribute \src "issuer_ls180.v:21452.5-21452.29" + switch \initial + attribute \src "issuer_ls180.v:21452.9-21452.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\src_l_r_src$next[3:0]$601 4'1111 + case + assign $1\src_l_r_src$next[3:0]$601 \reset_r + end + sync always + update \src_l_r_src$next $0\src_l_r_src$next[3:0]$600 + end + attribute \src "issuer_ls180.v:21460.3-21468.6" + process $proc$issuer_ls180.v:21460$602 + assign { } { } + assign { } { } + assign $0\req_l_s_req$next[4:0]$603 $1\req_l_s_req$next[4:0]$604 + attribute \src "issuer_ls180.v:21461.5-21461.29" + switch \initial + attribute \src "issuer_ls180.v:21461.9-21461.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\req_l_s_req$next[4:0]$604 5'00000 + case + assign $1\req_l_s_req$next[4:0]$604 \$67 + end + sync always + update \req_l_s_req$next $0\req_l_s_req$next[4:0]$603 + end + attribute \src "issuer_ls180.v:21469.3-21477.6" + process $proc$issuer_ls180.v:21469$605 + assign { } { } + assign { } { } + assign $0\req_l_r_req$next[4:0]$606 $1\req_l_r_req$next[4:0]$607 + attribute \src "issuer_ls180.v:21470.5-21470.29" + switch \initial + attribute \src "issuer_ls180.v:21470.9-21470.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\req_l_r_req$next[4:0]$607 5'11111 + case + assign $1\req_l_r_req$next[4:0]$607 \$69 + end + sync always + update \req_l_r_req$next $0\req_l_r_req$next[4:0]$606 + end + attribute \src "issuer_ls180.v:21478.3-21516.6" + process $proc$issuer_ls180.v:21478$608 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\alu_alu0_alu_op__data_len$next[3:0]$609 $1\alu_alu0_alu_op__data_len$next[3:0]$627 + assign $0\alu_alu0_alu_op__fn_unit$next[11:0]$610 $1\alu_alu0_alu_op__fn_unit$next[11:0]$628 + assign { } { } + assign { } { } + assign $0\alu_alu0_alu_op__input_carry$next[1:0]$613 $1\alu_alu0_alu_op__input_carry$next[1:0]$631 + assign $0\alu_alu0_alu_op__insn$next[31:0]$614 $1\alu_alu0_alu_op__insn$next[31:0]$632 + assign $0\alu_alu0_alu_op__insn_type$next[6:0]$615 $1\alu_alu0_alu_op__insn_type$next[6:0]$633 + assign $0\alu_alu0_alu_op__invert_in$next[0:0]$616 $1\alu_alu0_alu_op__invert_in$next[0:0]$634 + assign $0\alu_alu0_alu_op__invert_out$next[0:0]$617 $1\alu_alu0_alu_op__invert_out$next[0:0]$635 + assign $0\alu_alu0_alu_op__is_32bit$next[0:0]$618 $1\alu_alu0_alu_op__is_32bit$next[0:0]$636 + assign $0\alu_alu0_alu_op__is_signed$next[0:0]$619 $1\alu_alu0_alu_op__is_signed$next[0:0]$637 + assign { } { } + assign { } { } + assign $0\alu_alu0_alu_op__output_carry$next[0:0]$622 $1\alu_alu0_alu_op__output_carry$next[0:0]$640 + assign { } { } + assign { } { } + assign $0\alu_alu0_alu_op__write_cr0$next[0:0]$625 $1\alu_alu0_alu_op__write_cr0$next[0:0]$643 + assign $0\alu_alu0_alu_op__zero_a$next[0:0]$626 $1\alu_alu0_alu_op__zero_a$next[0:0]$644 + assign $0\alu_alu0_alu_op__imm_data__data$next[63:0]$611 $2\alu_alu0_alu_op__imm_data__data$next[63:0]$645 + assign $0\alu_alu0_alu_op__imm_data__ok$next[0:0]$612 $2\alu_alu0_alu_op__imm_data__ok$next[0:0]$646 + assign $0\alu_alu0_alu_op__oe__oe$next[0:0]$620 $2\alu_alu0_alu_op__oe__oe$next[0:0]$647 + assign $0\alu_alu0_alu_op__oe__ok$next[0:0]$621 $2\alu_alu0_alu_op__oe__ok$next[0:0]$648 + assign $0\alu_alu0_alu_op__rc__ok$next[0:0]$623 $2\alu_alu0_alu_op__rc__ok$next[0:0]$649 + assign $0\alu_alu0_alu_op__rc__rc$next[0:0]$624 $2\alu_alu0_alu_op__rc__rc$next[0:0]$650 + attribute \src "issuer_ls180.v:21479.5-21479.29" + switch \initial + attribute \src "issuer_ls180.v:21479.9-21479.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:257" + switch \cu_issue_i + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { $1\alu_alu0_alu_op__insn$next[31:0]$632 $1\alu_alu0_alu_op__data_len$next[3:0]$627 $1\alu_alu0_alu_op__is_signed$next[0:0]$637 $1\alu_alu0_alu_op__is_32bit$next[0:0]$636 $1\alu_alu0_alu_op__output_carry$next[0:0]$640 $1\alu_alu0_alu_op__input_carry$next[1:0]$631 $1\alu_alu0_alu_op__write_cr0$next[0:0]$643 $1\alu_alu0_alu_op__invert_out$next[0:0]$635 $1\alu_alu0_alu_op__zero_a$next[0:0]$644 $1\alu_alu0_alu_op__invert_in$next[0:0]$634 $1\alu_alu0_alu_op__oe__ok$next[0:0]$639 $1\alu_alu0_alu_op__oe__oe$next[0:0]$638 $1\alu_alu0_alu_op__rc__ok$next[0:0]$641 $1\alu_alu0_alu_op__rc__rc$next[0:0]$642 $1\alu_alu0_alu_op__imm_data__ok$next[0:0]$630 $1\alu_alu0_alu_op__imm_data__data$next[63:0]$629 $1\alu_alu0_alu_op__fn_unit$next[11:0]$628 $1\alu_alu0_alu_op__insn_type$next[6:0]$633 } { \oper_i_alu_alu0__insn \oper_i_alu_alu0__data_len \oper_i_alu_alu0__is_signed \oper_i_alu_alu0__is_32bit \oper_i_alu_alu0__output_carry \oper_i_alu_alu0__input_carry \oper_i_alu_alu0__write_cr0 \oper_i_alu_alu0__invert_out \oper_i_alu_alu0__zero_a \oper_i_alu_alu0__invert_in \oper_i_alu_alu0__oe__ok \oper_i_alu_alu0__oe__oe \oper_i_alu_alu0__rc__ok \oper_i_alu_alu0__rc__rc \oper_i_alu_alu0__imm_data__ok \oper_i_alu_alu0__imm_data__data \oper_i_alu_alu0__fn_unit \oper_i_alu_alu0__insn_type } + case + assign $1\alu_alu0_alu_op__data_len$next[3:0]$627 \alu_alu0_alu_op__data_len + assign $1\alu_alu0_alu_op__fn_unit$next[11:0]$628 \alu_alu0_alu_op__fn_unit + assign $1\alu_alu0_alu_op__imm_data__data$next[63:0]$629 \alu_alu0_alu_op__imm_data__data + assign $1\alu_alu0_alu_op__imm_data__ok$next[0:0]$630 \alu_alu0_alu_op__imm_data__ok + assign $1\alu_alu0_alu_op__input_carry$next[1:0]$631 \alu_alu0_alu_op__input_carry + assign $1\alu_alu0_alu_op__insn$next[31:0]$632 \alu_alu0_alu_op__insn + assign $1\alu_alu0_alu_op__insn_type$next[6:0]$633 \alu_alu0_alu_op__insn_type + assign $1\alu_alu0_alu_op__invert_in$next[0:0]$634 \alu_alu0_alu_op__invert_in + assign $1\alu_alu0_alu_op__invert_out$next[0:0]$635 \alu_alu0_alu_op__invert_out + assign $1\alu_alu0_alu_op__is_32bit$next[0:0]$636 \alu_alu0_alu_op__is_32bit + assign $1\alu_alu0_alu_op__is_signed$next[0:0]$637 \alu_alu0_alu_op__is_signed + assign $1\alu_alu0_alu_op__oe__oe$next[0:0]$638 \alu_alu0_alu_op__oe__oe + assign $1\alu_alu0_alu_op__oe__ok$next[0:0]$639 \alu_alu0_alu_op__oe__ok + assign $1\alu_alu0_alu_op__output_carry$next[0:0]$640 \alu_alu0_alu_op__output_carry + assign $1\alu_alu0_alu_op__rc__ok$next[0:0]$641 \alu_alu0_alu_op__rc__ok + assign $1\alu_alu0_alu_op__rc__rc$next[0:0]$642 \alu_alu0_alu_op__rc__rc + assign $1\alu_alu0_alu_op__write_cr0$next[0:0]$643 \alu_alu0_alu_op__write_cr0 + assign $1\alu_alu0_alu_op__zero_a$next[0:0]$644 \alu_alu0_alu_op__zero_a + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $2\alu_alu0_alu_op__imm_data__data$next[63:0]$645 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\alu_alu0_alu_op__imm_data__ok$next[0:0]$646 1'0 + assign $2\alu_alu0_alu_op__rc__rc$next[0:0]$650 1'0 + assign $2\alu_alu0_alu_op__rc__ok$next[0:0]$649 1'0 + assign $2\alu_alu0_alu_op__oe__oe$next[0:0]$647 1'0 + assign $2\alu_alu0_alu_op__oe__ok$next[0:0]$648 1'0 + case + assign $2\alu_alu0_alu_op__imm_data__data$next[63:0]$645 $1\alu_alu0_alu_op__imm_data__data$next[63:0]$629 + assign $2\alu_alu0_alu_op__imm_data__ok$next[0:0]$646 $1\alu_alu0_alu_op__imm_data__ok$next[0:0]$630 + assign $2\alu_alu0_alu_op__oe__oe$next[0:0]$647 $1\alu_alu0_alu_op__oe__oe$next[0:0]$638 + assign $2\alu_alu0_alu_op__oe__ok$next[0:0]$648 $1\alu_alu0_alu_op__oe__ok$next[0:0]$639 + assign $2\alu_alu0_alu_op__rc__ok$next[0:0]$649 $1\alu_alu0_alu_op__rc__ok$next[0:0]$641 + assign $2\alu_alu0_alu_op__rc__rc$next[0:0]$650 $1\alu_alu0_alu_op__rc__rc$next[0:0]$642 + end + sync always + update \alu_alu0_alu_op__data_len$next $0\alu_alu0_alu_op__data_len$next[3:0]$609 + update \alu_alu0_alu_op__fn_unit$next $0\alu_alu0_alu_op__fn_unit$next[11:0]$610 + update \alu_alu0_alu_op__imm_data__data$next $0\alu_alu0_alu_op__imm_data__data$next[63:0]$611 + update \alu_alu0_alu_op__imm_data__ok$next $0\alu_alu0_alu_op__imm_data__ok$next[0:0]$612 + update \alu_alu0_alu_op__input_carry$next $0\alu_alu0_alu_op__input_carry$next[1:0]$613 + update \alu_alu0_alu_op__insn$next $0\alu_alu0_alu_op__insn$next[31:0]$614 + update \alu_alu0_alu_op__insn_type$next $0\alu_alu0_alu_op__insn_type$next[6:0]$615 + update \alu_alu0_alu_op__invert_in$next $0\alu_alu0_alu_op__invert_in$next[0:0]$616 + update \alu_alu0_alu_op__invert_out$next $0\alu_alu0_alu_op__invert_out$next[0:0]$617 + update \alu_alu0_alu_op__is_32bit$next $0\alu_alu0_alu_op__is_32bit$next[0:0]$618 + update \alu_alu0_alu_op__is_signed$next $0\alu_alu0_alu_op__is_signed$next[0:0]$619 + update \alu_alu0_alu_op__oe__oe$next $0\alu_alu0_alu_op__oe__oe$next[0:0]$620 + update \alu_alu0_alu_op__oe__ok$next $0\alu_alu0_alu_op__oe__ok$next[0:0]$621 + update \alu_alu0_alu_op__output_carry$next $0\alu_alu0_alu_op__output_carry$next[0:0]$622 + update \alu_alu0_alu_op__rc__ok$next $0\alu_alu0_alu_op__rc__ok$next[0:0]$623 + update \alu_alu0_alu_op__rc__rc$next $0\alu_alu0_alu_op__rc__rc$next[0:0]$624 + update \alu_alu0_alu_op__write_cr0$next $0\alu_alu0_alu_op__write_cr0$next[0:0]$625 + update \alu_alu0_alu_op__zero_a$next $0\alu_alu0_alu_op__zero_a$next[0:0]$626 + end + attribute \src "issuer_ls180.v:21517.3-21538.6" + process $proc$issuer_ls180.v:21517$651 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\data_r0__o$next[63:0]$652 $2\data_r0__o$next[63:0]$656 + assign { } { } + assign $0\data_r0__o_ok$next[0:0]$653 $3\data_r0__o_ok$next[0:0]$658 + attribute \src "issuer_ls180.v:21518.5-21518.29" + switch \initial + attribute \src "issuer_ls180.v:21518.9-21518.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" + switch \alu_pulse + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $1\data_r0__o_ok$next[0:0]$655 $1\data_r0__o$next[63:0]$654 } { \o_ok \alu_alu0_o } + case + assign $1\data_r0__o$next[63:0]$654 \data_r0__o + assign $1\data_r0__o_ok$next[0:0]$655 \data_r0__o_ok + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" + switch \cu_issue_i + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $2\data_r0__o_ok$next[0:0]$657 $2\data_r0__o$next[63:0]$656 } 65'00000000000000000000000000000000000000000000000000000000000000000 + case + assign $2\data_r0__o$next[63:0]$656 $1\data_r0__o$next[63:0]$654 + assign $2\data_r0__o_ok$next[0:0]$657 $1\data_r0__o_ok$next[0:0]$655 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\data_r0__o_ok$next[0:0]$658 1'0 + case + assign $3\data_r0__o_ok$next[0:0]$658 $2\data_r0__o_ok$next[0:0]$657 + end + sync always + update \data_r0__o$next $0\data_r0__o$next[63:0]$652 + update \data_r0__o_ok$next $0\data_r0__o_ok$next[0:0]$653 + end + attribute \src "issuer_ls180.v:21539.3-21560.6" + process $proc$issuer_ls180.v:21539$659 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\data_r1__cr_a$next[3:0]$660 $2\data_r1__cr_a$next[3:0]$664 + assign { } { } + assign $0\data_r1__cr_a_ok$next[0:0]$661 $3\data_r1__cr_a_ok$next[0:0]$666 + attribute \src "issuer_ls180.v:21540.5-21540.29" + switch \initial + attribute \src "issuer_ls180.v:21540.9-21540.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" + switch \alu_pulse + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $1\data_r1__cr_a_ok$next[0:0]$663 $1\data_r1__cr_a$next[3:0]$662 } { \cr_a_ok \alu_alu0_cr_a } + case + assign $1\data_r1__cr_a$next[3:0]$662 \data_r1__cr_a + assign $1\data_r1__cr_a_ok$next[0:0]$663 \data_r1__cr_a_ok + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" + switch \cu_issue_i + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $2\data_r1__cr_a_ok$next[0:0]$665 $2\data_r1__cr_a$next[3:0]$664 } 5'00000 + case + assign $2\data_r1__cr_a$next[3:0]$664 $1\data_r1__cr_a$next[3:0]$662 + assign $2\data_r1__cr_a_ok$next[0:0]$665 $1\data_r1__cr_a_ok$next[0:0]$663 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\data_r1__cr_a_ok$next[0:0]$666 1'0 + case + assign $3\data_r1__cr_a_ok$next[0:0]$666 $2\data_r1__cr_a_ok$next[0:0]$665 + end + sync always + update \data_r1__cr_a$next $0\data_r1__cr_a$next[3:0]$660 + update \data_r1__cr_a_ok$next $0\data_r1__cr_a_ok$next[0:0]$661 + end + attribute \src "issuer_ls180.v:21561.3-21582.6" + process $proc$issuer_ls180.v:21561$667 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\data_r2__xer_ca$next[1:0]$668 $2\data_r2__xer_ca$next[1:0]$672 + assign { } { } + assign $0\data_r2__xer_ca_ok$next[0:0]$669 $3\data_r2__xer_ca_ok$next[0:0]$674 + attribute \src "issuer_ls180.v:21562.5-21562.29" + switch \initial + attribute \src "issuer_ls180.v:21562.9-21562.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" + switch \alu_pulse + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $1\data_r2__xer_ca_ok$next[0:0]$671 $1\data_r2__xer_ca$next[1:0]$670 } { \xer_ca_ok \alu_alu0_xer_ca } + case + assign $1\data_r2__xer_ca$next[1:0]$670 \data_r2__xer_ca + assign $1\data_r2__xer_ca_ok$next[0:0]$671 \data_r2__xer_ca_ok + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" + switch \cu_issue_i + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $2\data_r2__xer_ca_ok$next[0:0]$673 $2\data_r2__xer_ca$next[1:0]$672 } 3'000 + case + assign $2\data_r2__xer_ca$next[1:0]$672 $1\data_r2__xer_ca$next[1:0]$670 + assign $2\data_r2__xer_ca_ok$next[0:0]$673 $1\data_r2__xer_ca_ok$next[0:0]$671 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\data_r2__xer_ca_ok$next[0:0]$674 1'0 + case + assign $3\data_r2__xer_ca_ok$next[0:0]$674 $2\data_r2__xer_ca_ok$next[0:0]$673 + end + sync always + update \data_r2__xer_ca$next $0\data_r2__xer_ca$next[1:0]$668 + update \data_r2__xer_ca_ok$next $0\data_r2__xer_ca_ok$next[0:0]$669 + end + attribute \src "issuer_ls180.v:21583.3-21604.6" + process $proc$issuer_ls180.v:21583$675 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\data_r3__xer_ov$next[1:0]$676 $2\data_r3__xer_ov$next[1:0]$680 + assign { } { } + assign $0\data_r3__xer_ov_ok$next[0:0]$677 $3\data_r3__xer_ov_ok$next[0:0]$682 + attribute \src "issuer_ls180.v:21584.5-21584.29" + switch \initial + attribute \src "issuer_ls180.v:21584.9-21584.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" + switch \alu_pulse + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $1\data_r3__xer_ov_ok$next[0:0]$679 $1\data_r3__xer_ov$next[1:0]$678 } { \xer_ov_ok \alu_alu0_xer_ov } + case + assign $1\data_r3__xer_ov$next[1:0]$678 \data_r3__xer_ov + assign $1\data_r3__xer_ov_ok$next[0:0]$679 \data_r3__xer_ov_ok + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" + switch \cu_issue_i + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $2\data_r3__xer_ov_ok$next[0:0]$681 $2\data_r3__xer_ov$next[1:0]$680 } 3'000 + case + assign $2\data_r3__xer_ov$next[1:0]$680 $1\data_r3__xer_ov$next[1:0]$678 + assign $2\data_r3__xer_ov_ok$next[0:0]$681 $1\data_r3__xer_ov_ok$next[0:0]$679 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\data_r3__xer_ov_ok$next[0:0]$682 1'0 + case + assign $3\data_r3__xer_ov_ok$next[0:0]$682 $2\data_r3__xer_ov_ok$next[0:0]$681 + end + sync always + update \data_r3__xer_ov$next $0\data_r3__xer_ov$next[1:0]$676 + update \data_r3__xer_ov_ok$next $0\data_r3__xer_ov_ok$next[0:0]$677 + end + attribute \src "issuer_ls180.v:21605.3-21626.6" + process $proc$issuer_ls180.v:21605$683 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\data_r4__xer_so$next[0:0]$684 $2\data_r4__xer_so$next[0:0]$688 + assign { } { } + assign $0\data_r4__xer_so_ok$next[0:0]$685 $3\data_r4__xer_so_ok$next[0:0]$690 + attribute \src "issuer_ls180.v:21606.5-21606.29" + switch \initial + attribute \src "issuer_ls180.v:21606.9-21606.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" + switch \alu_pulse + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $1\data_r4__xer_so_ok$next[0:0]$687 $1\data_r4__xer_so$next[0:0]$686 } { \xer_so_ok \alu_alu0_xer_so } + case + assign $1\data_r4__xer_so$next[0:0]$686 \data_r4__xer_so + assign $1\data_r4__xer_so_ok$next[0:0]$687 \data_r4__xer_so_ok + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" + switch \cu_issue_i + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $2\data_r4__xer_so_ok$next[0:0]$689 $2\data_r4__xer_so$next[0:0]$688 } 2'00 + case + assign $2\data_r4__xer_so$next[0:0]$688 $1\data_r4__xer_so$next[0:0]$686 + assign $2\data_r4__xer_so_ok$next[0:0]$689 $1\data_r4__xer_so_ok$next[0:0]$687 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\data_r4__xer_so_ok$next[0:0]$690 1'0 + case + assign $3\data_r4__xer_so_ok$next[0:0]$690 $2\data_r4__xer_so_ok$next[0:0]$689 + end + sync always + update \data_r4__xer_so$next $0\data_r4__xer_so$next[0:0]$684 + update \data_r4__xer_so_ok$next $0\data_r4__xer_so_ok$next[0:0]$685 + end + attribute \src "issuer_ls180.v:21627.3-21636.6" + process $proc$issuer_ls180.v:21627$691 + assign { } { } + assign { } { } + assign $0\src_r0$next[63:0]$692 $1\src_r0$next[63:0]$693 + attribute \src "issuer_ls180.v:21628.5-21628.29" + switch \initial + attribute \src "issuer_ls180.v:21628.9-21628.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" + switch \src_sel + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\src_r0$next[63:0]$693 \src_or_imm + case + assign $1\src_r0$next[63:0]$693 \src_r0 + end + sync always + update \src_r0$next $0\src_r0$next[63:0]$692 + end + attribute \src "issuer_ls180.v:21637.3-21646.6" + process $proc$issuer_ls180.v:21637$694 + assign { } { } + assign { } { } + assign $0\src_r1$next[63:0]$695 $1\src_r1$next[63:0]$696 + attribute \src "issuer_ls180.v:21638.5-21638.29" + switch \initial + attribute \src "issuer_ls180.v:21638.9-21638.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" + switch \src_sel$85 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\src_r1$next[63:0]$696 \src_or_imm$88 + case + assign $1\src_r1$next[63:0]$696 \src_r1 + end + sync always + update \src_r1$next $0\src_r1$next[63:0]$695 + end + attribute \src "issuer_ls180.v:21647.3-21656.6" + process $proc$issuer_ls180.v:21647$697 + assign { } { } + assign { } { } + assign $0\src_r2$next[0:0]$698 $1\src_r2$next[0:0]$699 + attribute \src "issuer_ls180.v:21648.5-21648.29" + switch \initial + attribute \src "issuer_ls180.v:21648.9-21648.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" + switch \src_l_q_src [2] + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\src_r2$next[0:0]$699 \src3_i + case + assign $1\src_r2$next[0:0]$699 \src_r2 + end + sync always + update \src_r2$next $0\src_r2$next[0:0]$698 + end + attribute \src "issuer_ls180.v:21657.3-21666.6" + process $proc$issuer_ls180.v:21657$700 + assign { } { } + assign { } { } + assign $0\src_r3$next[1:0]$701 $1\src_r3$next[1:0]$702 + attribute \src "issuer_ls180.v:21658.5-21658.29" + switch \initial + attribute \src "issuer_ls180.v:21658.9-21658.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" + switch \src_l_q_src [3] + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\src_r3$next[1:0]$702 \src4_i + case + assign $1\src_r3$next[1:0]$702 \src_r3 + end + sync always + update \src_r3$next $0\src_r3$next[1:0]$701 + end + attribute \src "issuer_ls180.v:21667.3-21675.6" + process $proc$issuer_ls180.v:21667$703 + assign { } { } + assign { } { } + assign $0\alui_l_r_alui$next[0:0]$704 $1\alui_l_r_alui$next[0:0]$705 + attribute \src "issuer_ls180.v:21668.5-21668.29" + switch \initial + attribute \src "issuer_ls180.v:21668.9-21668.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\alui_l_r_alui$next[0:0]$705 1'1 + case + assign $1\alui_l_r_alui$next[0:0]$705 \$99 + end + sync always + update \alui_l_r_alui$next $0\alui_l_r_alui$next[0:0]$704 + end + attribute \src "issuer_ls180.v:21676.3-21684.6" + process $proc$issuer_ls180.v:21676$706 + assign { } { } + assign { } { } + assign $0\alu_l_r_alu$next[0:0]$707 $1\alu_l_r_alu$next[0:0]$708 + attribute \src "issuer_ls180.v:21677.5-21677.29" + switch \initial + attribute \src "issuer_ls180.v:21677.9-21677.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\alu_l_r_alu$next[0:0]$708 1'1 + case + assign $1\alu_l_r_alu$next[0:0]$708 \$101 + end + sync always + update \alu_l_r_alu$next $0\alu_l_r_alu$next[0:0]$707 + end + attribute \src "issuer_ls180.v:21685.3-21694.6" + process $proc$issuer_ls180.v:21685$709 + assign { } { } + assign { } { } + assign $0\dest1_o[63:0] $1\dest1_o[63:0] + attribute \src "issuer_ls180.v:21686.5-21686.29" + switch \initial + attribute \src "issuer_ls180.v:21686.9-21686.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" + switch \$129 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dest1_o[63:0] \data_r0__o + case + assign $1\dest1_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \dest1_o $0\dest1_o[63:0] + end + attribute \src "issuer_ls180.v:21695.3-21704.6" + process $proc$issuer_ls180.v:21695$710 + assign { } { } + assign { } { } + assign $0\dest2_o[3:0] $1\dest2_o[3:0] + attribute \src "issuer_ls180.v:21696.5-21696.29" + switch \initial + attribute \src "issuer_ls180.v:21696.9-21696.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" + switch \$131 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dest2_o[3:0] \data_r1__cr_a + case + assign $1\dest2_o[3:0] 4'0000 + end + sync always + update \dest2_o $0\dest2_o[3:0] + end + attribute \src "issuer_ls180.v:21705.3-21714.6" + process $proc$issuer_ls180.v:21705$711 + assign { } { } + assign { } { } + assign $0\dest3_o[1:0] $1\dest3_o[1:0] + attribute \src "issuer_ls180.v:21706.5-21706.29" + switch \initial + attribute \src "issuer_ls180.v:21706.9-21706.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" + switch \$133 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dest3_o[1:0] \data_r2__xer_ca + case + assign $1\dest3_o[1:0] 2'00 + end + sync always + update \dest3_o $0\dest3_o[1:0] + end + attribute \src "issuer_ls180.v:21715.3-21724.6" + process $proc$issuer_ls180.v:21715$712 + assign { } { } + assign { } { } + assign $0\dest4_o[1:0] $1\dest4_o[1:0] + attribute \src "issuer_ls180.v:21716.5-21716.29" + switch \initial + attribute \src "issuer_ls180.v:21716.9-21716.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" + switch \$135 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dest4_o[1:0] \data_r3__xer_ov + case + assign $1\dest4_o[1:0] 2'00 + end + sync always + update \dest4_o $0\dest4_o[1:0] + end + attribute \src "issuer_ls180.v:21725.3-21734.6" + process $proc$issuer_ls180.v:21725$713 + assign { } { } + assign { } { } + assign $0\dest5_o[0:0] $1\dest5_o[0:0] + attribute \src "issuer_ls180.v:21726.5-21726.29" + switch \initial + attribute \src "issuer_ls180.v:21726.9-21726.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" + switch \$137 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dest5_o[0:0] \data_r4__xer_so + case + assign $1\dest5_o[0:0] 1'0 + end + sync always + update \dest5_o $0\dest5_o[0:0] + end + attribute \src "issuer_ls180.v:21735.3-21743.6" + process $proc$issuer_ls180.v:21735$714 + assign { } { } + assign { } { } + assign $0\prev_wr_go$next[4:0]$715 $1\prev_wr_go$next[4:0]$716 + attribute \src "issuer_ls180.v:21736.5-21736.29" + switch \initial + attribute \src "issuer_ls180.v:21736.9-21736.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\prev_wr_go$next[4:0]$716 5'00000 + case + assign $1\prev_wr_go$next[4:0]$716 \$21 + end + sync always + update \prev_wr_go$next $0\prev_wr_go$next[4:0]$715 + end + connect \$5 $reduce_and$issuer_ls180.v:21129$463_Y + connect \$99 $and$issuer_ls180.v:21130$464_Y + connect \$101 $and$issuer_ls180.v:21131$465_Y + connect \$103 $and$issuer_ls180.v:21132$466_Y + connect \$105 $not$issuer_ls180.v:21133$467_Y + connect \$107 $not$issuer_ls180.v:21134$468_Y + connect \$109 $and$issuer_ls180.v:21135$469_Y + connect \$111 $not$issuer_ls180.v:21136$470_Y + connect \$113 $and$issuer_ls180.v:21137$471_Y + connect \$115 $and$issuer_ls180.v:21138$472_Y + connect \$117 $and$issuer_ls180.v:21139$473_Y + connect \$11 $and$issuer_ls180.v:21140$474_Y + connect \$119 $and$issuer_ls180.v:21141$475_Y + connect \$121 $and$issuer_ls180.v:21142$476_Y + connect \$123 $and$issuer_ls180.v:21143$477_Y + connect \$125 $and$issuer_ls180.v:21144$478_Y + connect \$127 $and$issuer_ls180.v:21145$479_Y + connect \$129 $and$issuer_ls180.v:21146$480_Y + connect \$131 $and$issuer_ls180.v:21147$481_Y + connect \$133 $and$issuer_ls180.v:21148$482_Y + connect \$135 $and$issuer_ls180.v:21149$483_Y + connect \$137 $and$issuer_ls180.v:21150$484_Y + connect \$13 $not$issuer_ls180.v:21151$485_Y + connect \$15 $and$issuer_ls180.v:21152$486_Y + connect \$17 $not$issuer_ls180.v:21153$487_Y + connect \$19 $and$issuer_ls180.v:21154$488_Y + connect \$21 $and$issuer_ls180.v:21155$489_Y + connect \$25 $not$issuer_ls180.v:21156$490_Y + connect \$27 $and$issuer_ls180.v:21157$491_Y + connect \$24 $reduce_or$issuer_ls180.v:21158$492_Y + connect \$23 $not$issuer_ls180.v:21159$493_Y + connect \$31 $and$issuer_ls180.v:21160$494_Y + connect \$33 $reduce_or$issuer_ls180.v:21161$495_Y + connect \$35 $reduce_or$issuer_ls180.v:21162$496_Y + connect \$37 $or$issuer_ls180.v:21163$497_Y + connect \$3 $and$issuer_ls180.v:21164$498_Y + connect \$39 $not$issuer_ls180.v:21165$499_Y + connect \$41 $and$issuer_ls180.v:21166$500_Y + connect \$43 $and$issuer_ls180.v:21167$501_Y + connect \$45 $eq$issuer_ls180.v:21168$502_Y + connect \$47 $and$issuer_ls180.v:21169$503_Y + connect \$49 $eq$issuer_ls180.v:21170$504_Y + connect \$51 $and$issuer_ls180.v:21171$505_Y + connect \$53 $and$issuer_ls180.v:21172$506_Y + connect \$55 $and$issuer_ls180.v:21173$507_Y + connect \$57 $or$issuer_ls180.v:21174$508_Y + connect \$59 $or$issuer_ls180.v:21175$509_Y + connect \$61 $or$issuer_ls180.v:21176$510_Y + connect \$63 $or$issuer_ls180.v:21177$511_Y + connect \$65 $and$issuer_ls180.v:21178$512_Y + connect \$67 $and$issuer_ls180.v:21179$513_Y + connect \$6 $not$issuer_ls180.v:21180$514_Y + connect \$69 $or$issuer_ls180.v:21181$515_Y + connect \$71 $and$issuer_ls180.v:21182$516_Y + connect \$73 $and$issuer_ls180.v:21183$517_Y + connect \$75 $and$issuer_ls180.v:21184$518_Y + connect \$77 $and$issuer_ls180.v:21185$519_Y + connect \$79 $and$issuer_ls180.v:21186$520_Y + connect \$81 $ternary$issuer_ls180.v:21187$521_Y + connect \$83 $ternary$issuer_ls180.v:21188$522_Y + connect \$86 $ternary$issuer_ls180.v:21189$523_Y + connect \$8 $or$issuer_ls180.v:21190$524_Y + connect \$89 $ternary$issuer_ls180.v:21191$525_Y + connect \$91 $ternary$issuer_ls180.v:21192$526_Y + connect \$93 $ternary$issuer_ls180.v:21193$527_Y + connect \$95 $ternary$issuer_ls180.v:21194$528_Y + connect \$97 $ternary$issuer_ls180.v:21195$529_Y + connect \cu_go_die_i 1'0 + connect \cu_shadown_i 1'1 + connect \cu_wr__rel_o \$127 + connect \cu_rd__rel_o \$113 + connect \cu_busy_o \opc_l_q_opc + connect \alu_l_s_alu \all_rd_pulse + connect \alu_alu0_n_ready_i \alu_l_q_alu + connect \alui_l_s_alui \all_rd_pulse + connect \alu_alu0_p_valid_i \alui_l_q_alui + connect \alu_alu0_xer_ca$2 \$97 + connect \alu_alu0_xer_so$1 \$95 + connect \alu_alu0_rb \$93 + connect \alu_alu0_ra \$91 + connect \src_or_imm$88 \$89 + connect \src_sel$85 \$86 + connect \src_or_imm \$83 + connect \src_sel \$81 + connect \cu_wrmask_o { \$79 \$77 \$75 \$73 \$71 } + connect \reset_r \$63 + connect \reset_w \$61 + connect \rst_r \$59 + connect \reset \$57 + connect \wr_any \$37 + connect \cu_done_o \$31 + connect \alu_pulsem { \alu_pulse \alu_pulse \alu_pulse \alu_pulse \alu_pulse } + connect \alu_pulse \alu_done_rise + connect \alu_done_rise \$19 + connect \alu_done_dly$next \alu_done + connect \alu_done \alu_alu0_n_valid_o + connect \all_rd_pulse \all_rd_rise + connect \all_rd_rise \$15 + connect \all_rd_dly$next \all_rd + connect \all_rd \$11 +end +attribute \src "issuer_ls180.v:21781.1-22841.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.fus.alu0.alu_alu0" +attribute \generator "nMigen" +module \alu_alu0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 input 25 \alu_op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \alu_op__data_len$70 + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 input 10 \alu_op__fn_unit + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 \alu_op__fn_unit$55 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 input 11 \alu_op__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \alu_op__imm_data__data$56 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 12 \alu_op__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__imm_data__ok$57 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 input 21 \alu_op__input_carry + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \alu_op__input_carry$66 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 26 \alu_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \alu_op__insn$71 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 input 9 \alu_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \alu_op__insn_type$54 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 17 \alu_op__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__invert_in$62 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 19 \alu_op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__invert_out$64 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 23 \alu_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__is_32bit$68 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 24 \alu_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__is_signed$69 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 15 \alu_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__oe__oe$60 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 16 \alu_op__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__oe__ok$61 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 22 \alu_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__output_carry$67 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 14 \alu_op__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__rc__ok$59 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 13 \alu_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__rc__rc$58 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 20 \alu_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__write_cr0$65 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 18 \alu_op__zero_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__zero_a$63 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" + wire input 38 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" + wire input 6 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 4 output 28 \cr_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 2 \cr_a_ok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \muxid$53 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" + wire input 8 \n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" + wire output 7 \n_valid_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 output 27 \o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 1 \o_ok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" + wire output 37 \p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" + wire input 36 \p_valid_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \pipe1_alu_op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \pipe1_alu_op__data_len$20 + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 \pipe1_alu_op__fn_unit + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 \pipe1_alu_op__fn_unit$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \pipe1_alu_op__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \pipe1_alu_op__imm_data__data$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe1_alu_op__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe1_alu_op__imm_data__ok$7 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \pipe1_alu_op__input_carry + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \pipe1_alu_op__input_carry$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \pipe1_alu_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \pipe1_alu_op__insn$21 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \pipe1_alu_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \pipe1_alu_op__insn_type$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe1_alu_op__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe1_alu_op__invert_in$12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe1_alu_op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe1_alu_op__invert_out$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe1_alu_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe1_alu_op__is_32bit$18 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe1_alu_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe1_alu_op__is_signed$19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe1_alu_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe1_alu_op__oe__oe$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe1_alu_op__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe1_alu_op__oe__ok$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe1_alu_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe1_alu_op__output_carry$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe1_alu_op__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe1_alu_op__rc__ok$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe1_alu_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe1_alu_op__rc__rc$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe1_alu_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe1_alu_op__write_cr0$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe1_alu_op__zero_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe1_alu_op__zero_a$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 4 \pipe1_cr_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \pipe1_cr_a_ok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \pipe1_muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \pipe1_muxid$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" + wire \pipe1_n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" + wire \pipe1_n_valid_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 \pipe1_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \pipe1_o_ok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" + wire \pipe1_p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" + wire \pipe1_p_valid_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \pipe1_ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \pipe1_rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 2 \pipe1_xer_ca + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 2 \pipe1_xer_ca$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \pipe1_xer_ca_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 2 \pipe1_xer_ov + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \pipe1_xer_ov_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \pipe1_xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire \pipe1_xer_so$22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \pipe1_xer_so_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \pipe2_alu_op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \pipe2_alu_op__data_len$41 + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 \pipe2_alu_op__fn_unit + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 \pipe2_alu_op__fn_unit$26 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \pipe2_alu_op__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \pipe2_alu_op__imm_data__data$27 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe2_alu_op__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe2_alu_op__imm_data__ok$28 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \pipe2_alu_op__input_carry + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \pipe2_alu_op__input_carry$37 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \pipe2_alu_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \pipe2_alu_op__insn$42 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \pipe2_alu_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \pipe2_alu_op__insn_type$25 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe2_alu_op__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe2_alu_op__invert_in$33 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe2_alu_op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe2_alu_op__invert_out$35 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe2_alu_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe2_alu_op__is_32bit$39 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe2_alu_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe2_alu_op__is_signed$40 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe2_alu_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe2_alu_op__oe__oe$31 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe2_alu_op__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe2_alu_op__oe__ok$32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe2_alu_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe2_alu_op__output_carry$38 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe2_alu_op__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe2_alu_op__rc__ok$30 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe2_alu_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe2_alu_op__rc__rc$29 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe2_alu_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe2_alu_op__write_cr0$36 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe2_alu_op__zero_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe2_alu_op__zero_a$34 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 4 \pipe2_cr_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 4 \pipe2_cr_a$45 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \pipe2_cr_a_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \pipe2_cr_a_ok$46 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \pipe2_muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \pipe2_muxid$24 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" + wire \pipe2_n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" + wire \pipe2_n_valid_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 \pipe2_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 \pipe2_o$43 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \pipe2_o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \pipe2_o_ok$44 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" + wire \pipe2_p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" + wire \pipe2_p_valid_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 2 \pipe2_xer_ca + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 2 \pipe2_xer_ca$47 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \pipe2_xer_ca_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \pipe2_xer_ca_ok$48 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 2 \pipe2_xer_ov + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 2 \pipe2_xer_ov$49 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \pipe2_xer_ov_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \pipe2_xer_ov_ok$50 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \pipe2_xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \pipe2_xer_so$51 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \pipe2_xer_so_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \pipe2_xer_so_ok$52 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 32 \ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 33 \rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 2 output 29 \xer_ca + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 2 input 35 \xer_ca$2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 3 \xer_ca_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 2 output 30 \xer_ov + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 4 \xer_ov_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 31 \xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire input 34 \xer_so$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 5 \xer_so_ok + attribute \module_not_derived 1 + attribute \src "issuer_ls180.v:22680.5-22683.4" + cell \n \n + connect \n_ready_i \n_ready_i + connect \n_valid_o \n_valid_o + end + attribute \module_not_derived 1 + attribute \src "issuer_ls180.v:22684.5-22687.4" + cell \p \p + connect \p_ready_o \p_ready_o + connect \p_valid_i \p_valid_i + end + attribute \module_not_derived 1 + attribute \src "issuer_ls180.v:22688.9-22747.4" + cell \pipe1 \pipe1 + connect \alu_op__data_len \pipe1_alu_op__data_len + connect \alu_op__data_len$18 \pipe1_alu_op__data_len$20 + connect \alu_op__fn_unit \pipe1_alu_op__fn_unit + connect \alu_op__fn_unit$3 \pipe1_alu_op__fn_unit$5 + connect \alu_op__imm_data__data \pipe1_alu_op__imm_data__data + connect \alu_op__imm_data__data$4 \pipe1_alu_op__imm_data__data$6 + connect \alu_op__imm_data__ok \pipe1_alu_op__imm_data__ok + connect \alu_op__imm_data__ok$5 \pipe1_alu_op__imm_data__ok$7 + connect \alu_op__input_carry \pipe1_alu_op__input_carry + connect \alu_op__input_carry$14 \pipe1_alu_op__input_carry$16 + connect \alu_op__insn \pipe1_alu_op__insn + connect \alu_op__insn$19 \pipe1_alu_op__insn$21 + connect \alu_op__insn_type \pipe1_alu_op__insn_type + connect \alu_op__insn_type$2 \pipe1_alu_op__insn_type$4 + connect \alu_op__invert_in \pipe1_alu_op__invert_in + connect \alu_op__invert_in$10 \pipe1_alu_op__invert_in$12 + connect \alu_op__invert_out \pipe1_alu_op__invert_out + connect \alu_op__invert_out$12 \pipe1_alu_op__invert_out$14 + connect \alu_op__is_32bit \pipe1_alu_op__is_32bit + connect \alu_op__is_32bit$16 \pipe1_alu_op__is_32bit$18 + connect \alu_op__is_signed \pipe1_alu_op__is_signed + connect \alu_op__is_signed$17 \pipe1_alu_op__is_signed$19 + connect \alu_op__oe__oe \pipe1_alu_op__oe__oe + connect \alu_op__oe__oe$8 \pipe1_alu_op__oe__oe$10 + connect \alu_op__oe__ok \pipe1_alu_op__oe__ok + connect \alu_op__oe__ok$9 \pipe1_alu_op__oe__ok$11 + connect \alu_op__output_carry \pipe1_alu_op__output_carry + connect \alu_op__output_carry$15 \pipe1_alu_op__output_carry$17 + connect \alu_op__rc__ok \pipe1_alu_op__rc__ok + connect \alu_op__rc__ok$7 \pipe1_alu_op__rc__ok$9 + connect \alu_op__rc__rc \pipe1_alu_op__rc__rc + connect \alu_op__rc__rc$6 \pipe1_alu_op__rc__rc$8 + connect \alu_op__write_cr0 \pipe1_alu_op__write_cr0 + connect \alu_op__write_cr0$13 \pipe1_alu_op__write_cr0$15 + connect \alu_op__zero_a \pipe1_alu_op__zero_a + connect \alu_op__zero_a$11 \pipe1_alu_op__zero_a$13 + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \cr_a \pipe1_cr_a + connect \cr_a_ok \pipe1_cr_a_ok + connect \muxid \pipe1_muxid + connect \muxid$1 \pipe1_muxid$3 + connect \n_ready_i \pipe1_n_ready_i + connect \n_valid_o \pipe1_n_valid_o + connect \o \pipe1_o + connect \o_ok \pipe1_o_ok + connect \p_ready_o \pipe1_p_ready_o + connect \p_valid_i \pipe1_p_valid_i + connect \ra \pipe1_ra + connect \rb \pipe1_rb + connect \xer_ca \pipe1_xer_ca + connect \xer_ca$21 \pipe1_xer_ca$23 + connect \xer_ca_ok \pipe1_xer_ca_ok + connect \xer_ov \pipe1_xer_ov + connect \xer_ov_ok \pipe1_xer_ov_ok + connect \xer_so \pipe1_xer_so + connect \xer_so$20 \pipe1_xer_so$22 + connect \xer_so_ok \pipe1_xer_so_ok + end + attribute \module_not_derived 1 + attribute \src "issuer_ls180.v:22748.9-22813.4" + cell \pipe2 \pipe2 + connect \alu_op__data_len \pipe2_alu_op__data_len + connect \alu_op__data_len$18 \pipe2_alu_op__data_len$41 + connect \alu_op__fn_unit \pipe2_alu_op__fn_unit + connect \alu_op__fn_unit$3 \pipe2_alu_op__fn_unit$26 + connect \alu_op__imm_data__data \pipe2_alu_op__imm_data__data + connect \alu_op__imm_data__data$4 \pipe2_alu_op__imm_data__data$27 + connect \alu_op__imm_data__ok \pipe2_alu_op__imm_data__ok + connect \alu_op__imm_data__ok$5 \pipe2_alu_op__imm_data__ok$28 + connect \alu_op__input_carry \pipe2_alu_op__input_carry + connect \alu_op__input_carry$14 \pipe2_alu_op__input_carry$37 + connect \alu_op__insn \pipe2_alu_op__insn + connect \alu_op__insn$19 \pipe2_alu_op__insn$42 + connect \alu_op__insn_type \pipe2_alu_op__insn_type + connect \alu_op__insn_type$2 \pipe2_alu_op__insn_type$25 + connect \alu_op__invert_in \pipe2_alu_op__invert_in + connect \alu_op__invert_in$10 \pipe2_alu_op__invert_in$33 + connect \alu_op__invert_out \pipe2_alu_op__invert_out + connect \alu_op__invert_out$12 \pipe2_alu_op__invert_out$35 + connect \alu_op__is_32bit \pipe2_alu_op__is_32bit + connect \alu_op__is_32bit$16 \pipe2_alu_op__is_32bit$39 + connect \alu_op__is_signed \pipe2_alu_op__is_signed + connect \alu_op__is_signed$17 \pipe2_alu_op__is_signed$40 + connect \alu_op__oe__oe \pipe2_alu_op__oe__oe + connect \alu_op__oe__oe$8 \pipe2_alu_op__oe__oe$31 + connect \alu_op__oe__ok \pipe2_alu_op__oe__ok + connect \alu_op__oe__ok$9 \pipe2_alu_op__oe__ok$32 + connect \alu_op__output_carry \pipe2_alu_op__output_carry + connect \alu_op__output_carry$15 \pipe2_alu_op__output_carry$38 + connect \alu_op__rc__ok \pipe2_alu_op__rc__ok + connect \alu_op__rc__ok$7 \pipe2_alu_op__rc__ok$30 + connect \alu_op__rc__rc \pipe2_alu_op__rc__rc + connect \alu_op__rc__rc$6 \pipe2_alu_op__rc__rc$29 + connect \alu_op__write_cr0 \pipe2_alu_op__write_cr0 + connect \alu_op__write_cr0$13 \pipe2_alu_op__write_cr0$36 + connect \alu_op__zero_a \pipe2_alu_op__zero_a + connect \alu_op__zero_a$11 \pipe2_alu_op__zero_a$34 + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \cr_a \pipe2_cr_a + connect \cr_a$22 \pipe2_cr_a$45 + connect \cr_a_ok \pipe2_cr_a_ok + connect \cr_a_ok$23 \pipe2_cr_a_ok$46 + connect \muxid \pipe2_muxid + connect \muxid$1 \pipe2_muxid$24 + connect \n_ready_i \pipe2_n_ready_i + connect \n_valid_o \pipe2_n_valid_o + connect \o \pipe2_o + connect \o$20 \pipe2_o$43 + connect \o_ok \pipe2_o_ok + connect \o_ok$21 \pipe2_o_ok$44 + connect \p_ready_o \pipe2_p_ready_o + connect \p_valid_i \pipe2_p_valid_i + connect \xer_ca \pipe2_xer_ca + connect \xer_ca$24 \pipe2_xer_ca$47 + connect \xer_ca_ok \pipe2_xer_ca_ok + connect \xer_ca_ok$25 \pipe2_xer_ca_ok$48 + connect \xer_ov \pipe2_xer_ov + connect \xer_ov$26 \pipe2_xer_ov$49 + connect \xer_ov_ok \pipe2_xer_ov_ok + connect \xer_ov_ok$27 \pipe2_xer_ov_ok$50 + connect \xer_so \pipe2_xer_so + connect \xer_so$28 \pipe2_xer_so$51 + connect \xer_so_ok \pipe2_xer_so_ok + connect \xer_so_ok$29 \pipe2_xer_so_ok$52 + end + connect \muxid 2'00 + connect { \xer_so_ok \xer_so } { \pipe2_xer_so_ok$52 \pipe2_xer_so$51 } + connect { \xer_ov_ok \xer_ov } { \pipe2_xer_ov_ok$50 \pipe2_xer_ov$49 } + connect { \xer_ca_ok \xer_ca } { \pipe2_xer_ca_ok$48 \pipe2_xer_ca$47 } + connect { \cr_a_ok \cr_a } { \pipe2_cr_a_ok$46 \pipe2_cr_a$45 } + connect { \o_ok \o } { \pipe2_o_ok$44 \pipe2_o$43 } + connect { \alu_op__insn$71 \alu_op__data_len$70 \alu_op__is_signed$69 \alu_op__is_32bit$68 \alu_op__output_carry$67 \alu_op__input_carry$66 \alu_op__write_cr0$65 \alu_op__invert_out$64 \alu_op__zero_a$63 \alu_op__invert_in$62 \alu_op__oe__ok$61 \alu_op__oe__oe$60 \alu_op__rc__ok$59 \alu_op__rc__rc$58 \alu_op__imm_data__ok$57 \alu_op__imm_data__data$56 \alu_op__fn_unit$55 \alu_op__insn_type$54 } { \pipe2_alu_op__insn$42 \pipe2_alu_op__data_len$41 \pipe2_alu_op__is_signed$40 \pipe2_alu_op__is_32bit$39 \pipe2_alu_op__output_carry$38 \pipe2_alu_op__input_carry$37 \pipe2_alu_op__write_cr0$36 \pipe2_alu_op__invert_out$35 \pipe2_alu_op__zero_a$34 \pipe2_alu_op__invert_in$33 \pipe2_alu_op__oe__ok$32 \pipe2_alu_op__oe__oe$31 \pipe2_alu_op__rc__ok$30 \pipe2_alu_op__rc__rc$29 \pipe2_alu_op__imm_data__ok$28 \pipe2_alu_op__imm_data__data$27 \pipe2_alu_op__fn_unit$26 \pipe2_alu_op__insn_type$25 } + connect \muxid$53 \pipe2_muxid$24 + connect \pipe2_n_ready_i \n_ready_i + connect \n_valid_o \pipe2_n_valid_o + connect \pipe1_xer_ca$23 \xer_ca$2 + connect \pipe1_xer_so$22 \xer_so$1 + connect \pipe1_rb \rb + connect \pipe1_ra \ra + connect { \pipe1_alu_op__insn$21 \pipe1_alu_op__data_len$20 \pipe1_alu_op__is_signed$19 \pipe1_alu_op__is_32bit$18 \pipe1_alu_op__output_carry$17 \pipe1_alu_op__input_carry$16 \pipe1_alu_op__write_cr0$15 \pipe1_alu_op__invert_out$14 \pipe1_alu_op__zero_a$13 \pipe1_alu_op__invert_in$12 \pipe1_alu_op__oe__ok$11 \pipe1_alu_op__oe__oe$10 \pipe1_alu_op__rc__ok$9 \pipe1_alu_op__rc__rc$8 \pipe1_alu_op__imm_data__ok$7 \pipe1_alu_op__imm_data__data$6 \pipe1_alu_op__fn_unit$5 \pipe1_alu_op__insn_type$4 } { \alu_op__insn \alu_op__data_len \alu_op__is_signed \alu_op__is_32bit \alu_op__output_carry \alu_op__input_carry \alu_op__write_cr0 \alu_op__invert_out \alu_op__zero_a \alu_op__invert_in \alu_op__oe__ok \alu_op__oe__oe \alu_op__rc__ok \alu_op__rc__rc \alu_op__imm_data__ok \alu_op__imm_data__data \alu_op__fn_unit \alu_op__insn_type } + connect \pipe1_muxid$3 2'00 + connect \p_ready_o \pipe1_p_ready_o + connect \pipe1_p_valid_i \p_valid_i + connect { \pipe2_xer_so_ok \pipe2_xer_so } { \pipe1_xer_so_ok \pipe1_xer_so } + connect { \pipe2_xer_ov_ok \pipe2_xer_ov } { \pipe1_xer_ov_ok \pipe1_xer_ov } + connect { \pipe2_xer_ca_ok \pipe2_xer_ca } { \pipe1_xer_ca_ok \pipe1_xer_ca } + connect { \pipe2_cr_a_ok \pipe2_cr_a } { \pipe1_cr_a_ok \pipe1_cr_a } + connect { \pipe2_o_ok \pipe2_o } { \pipe1_o_ok \pipe1_o } + connect { \pipe2_alu_op__insn \pipe2_alu_op__data_len \pipe2_alu_op__is_signed \pipe2_alu_op__is_32bit \pipe2_alu_op__output_carry \pipe2_alu_op__input_carry \pipe2_alu_op__write_cr0 \pipe2_alu_op__invert_out \pipe2_alu_op__zero_a \pipe2_alu_op__invert_in \pipe2_alu_op__oe__ok \pipe2_alu_op__oe__oe \pipe2_alu_op__rc__ok \pipe2_alu_op__rc__rc \pipe2_alu_op__imm_data__ok \pipe2_alu_op__imm_data__data \pipe2_alu_op__fn_unit \pipe2_alu_op__insn_type } { \pipe1_alu_op__insn \pipe1_alu_op__data_len \pipe1_alu_op__is_signed \pipe1_alu_op__is_32bit \pipe1_alu_op__output_carry \pipe1_alu_op__input_carry \pipe1_alu_op__write_cr0 \pipe1_alu_op__invert_out \pipe1_alu_op__zero_a \pipe1_alu_op__invert_in \pipe1_alu_op__oe__ok \pipe1_alu_op__oe__oe \pipe1_alu_op__rc__ok \pipe1_alu_op__rc__rc \pipe1_alu_op__imm_data__ok \pipe1_alu_op__imm_data__data \pipe1_alu_op__fn_unit \pipe1_alu_op__insn_type } + connect \pipe2_muxid \pipe1_muxid + connect \pipe1_n_ready_i \pipe2_p_ready_o + connect \pipe2_p_valid_i \pipe1_n_valid_o +end +attribute \src "issuer_ls180.v:22845.1-23380.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.fus.branch0.alu_branch0" +attribute \generator "nMigen" +module \alu_branch0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 input 7 \br_op__cia + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \br_op__cia$15 + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 input 9 \br_op__fn_unit + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 \br_op__fn_unit$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 input 11 \br_op__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \br_op__imm_data__data$19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 12 \br_op__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \br_op__imm_data__ok$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 10 \br_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \br_op__insn$18 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 input 8 \br_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \br_op__insn_type$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 14 \br_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \br_op__is_32bit$22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 13 \br_op__lk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \br_op__lk$21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" + wire input 23 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" + wire input 4 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 4 input 20 \cr_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 output 15 \fast1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 18 \fast1$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 1 \fast1_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 output 16 \fast2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 19 \fast2$2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 2 \fast2_ok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \muxid$14 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" + wire input 6 \n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" + wire output 5 \n_valid_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 output 17 \nia + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 3 \nia_ok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" + wire output 22 \p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" + wire input 21 \p_valid_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \pipe_br_op__cia + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \pipe_br_op__cia$4 + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 \pipe_br_op__fn_unit + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 \pipe_br_op__fn_unit$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \pipe_br_op__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \pipe_br_op__imm_data__data$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe_br_op__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe_br_op__imm_data__ok$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \pipe_br_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \pipe_br_op__insn$7 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \pipe_br_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \pipe_br_op__insn_type$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe_br_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe_br_op__is_32bit$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe_br_op__lk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe_br_op__lk$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 4 \pipe_cr_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \pipe_fast1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 \pipe_fast1$12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \pipe_fast1_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \pipe_fast2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 \pipe_fast2$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \pipe_fast2_ok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \pipe_muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \pipe_muxid$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" + wire \pipe_n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" + wire \pipe_n_valid_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 \pipe_nia + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \pipe_nia_ok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" + wire \pipe_p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" + wire \pipe_p_valid_i + attribute \module_not_derived 1 + attribute \src "issuer_ls180.v:23322.10-23325.4" + cell \n$18 \n + connect \n_ready_i \n_ready_i + connect \n_valid_o \n_valid_o + end + attribute \module_not_derived 1 + attribute \src "issuer_ls180.v:23326.10-23329.4" + cell \p$17 \p + connect \p_ready_o \p_ready_o + connect \p_valid_i \p_valid_i + end + attribute \module_not_derived 1 + attribute \src "issuer_ls180.v:23330.13-23364.4" + cell \pipe$19 \pipe + connect \br_op__cia \pipe_br_op__cia + connect \br_op__cia$2 \pipe_br_op__cia$4 + connect \br_op__fn_unit \pipe_br_op__fn_unit + connect \br_op__fn_unit$4 \pipe_br_op__fn_unit$6 + connect \br_op__imm_data__data \pipe_br_op__imm_data__data + connect \br_op__imm_data__data$6 \pipe_br_op__imm_data__data$8 + connect \br_op__imm_data__ok \pipe_br_op__imm_data__ok + connect \br_op__imm_data__ok$7 \pipe_br_op__imm_data__ok$9 + connect \br_op__insn \pipe_br_op__insn + connect \br_op__insn$5 \pipe_br_op__insn$7 + connect \br_op__insn_type \pipe_br_op__insn_type + connect \br_op__insn_type$3 \pipe_br_op__insn_type$5 + connect \br_op__is_32bit \pipe_br_op__is_32bit + connect \br_op__is_32bit$9 \pipe_br_op__is_32bit$11 + connect \br_op__lk \pipe_br_op__lk + connect \br_op__lk$8 \pipe_br_op__lk$10 + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \cr_a \pipe_cr_a + connect \fast1 \pipe_fast1 + connect \fast1$10 \pipe_fast1$12 + connect \fast1_ok \pipe_fast1_ok + connect \fast2 \pipe_fast2 + connect \fast2$11 \pipe_fast2$13 + connect \fast2_ok \pipe_fast2_ok + connect \muxid \pipe_muxid + connect \muxid$1 \pipe_muxid$3 + connect \n_ready_i \pipe_n_ready_i + connect \n_valid_o \pipe_n_valid_o + connect \nia \pipe_nia + connect \nia_ok \pipe_nia_ok + connect \p_ready_o \pipe_p_ready_o + connect \p_valid_i \pipe_p_valid_i + end + connect \muxid 2'00 + connect { \nia_ok \nia } { \pipe_nia_ok \pipe_nia } + connect { \fast2_ok \fast2 } { \pipe_fast2_ok \pipe_fast2$13 } + connect { \fast1_ok \fast1 } { \pipe_fast1_ok \pipe_fast1$12 } + connect { \br_op__is_32bit$22 \br_op__lk$21 \br_op__imm_data__ok$20 \br_op__imm_data__data$19 \br_op__insn$18 \br_op__fn_unit$17 \br_op__insn_type$16 \br_op__cia$15 } { \pipe_br_op__is_32bit$11 \pipe_br_op__lk$10 \pipe_br_op__imm_data__ok$9 \pipe_br_op__imm_data__data$8 \pipe_br_op__insn$7 \pipe_br_op__fn_unit$6 \pipe_br_op__insn_type$5 \pipe_br_op__cia$4 } + connect \muxid$14 \pipe_muxid$3 + connect \pipe_n_ready_i \n_ready_i + connect \n_valid_o \pipe_n_valid_o + connect \pipe_cr_a \cr_a + connect \pipe_fast2 \fast2$2 + connect \pipe_fast1 \fast1$1 + connect { \pipe_br_op__is_32bit \pipe_br_op__lk \pipe_br_op__imm_data__ok \pipe_br_op__imm_data__data \pipe_br_op__insn \pipe_br_op__fn_unit \pipe_br_op__insn_type \pipe_br_op__cia } { \br_op__is_32bit \br_op__lk \br_op__imm_data__ok \br_op__imm_data__data \br_op__insn \br_op__fn_unit \br_op__insn_type \br_op__cia } + connect \pipe_muxid 2'00 + connect \p_ready_o \pipe_p_ready_o + connect \pipe_p_valid_i \p_valid_i +end +attribute \src "issuer_ls180.v:23384.1-23887.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.fus.cr0.alu_cr0" +attribute \generator "nMigen" +module \alu_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" + wire input 21 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" + wire input 4 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 4 output 12 \cr_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 4 input 16 \cr_a$2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 3 \cr_a_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 4 input 17 \cr_b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 4 input 18 \cr_c + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 input 8 \cr_op__fn_unit + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 \cr_op__fn_unit$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 9 \cr_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \cr_op__insn$12 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 input 7 \cr_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \cr_op__insn_type$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 32 output 11 \full_cr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 32 input 15 \full_cr$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 2 \full_cr_ok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \muxid$9 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" + wire input 6 \n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" + wire output 5 \n_valid_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 output 10 \o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 1 \o_ok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" + wire output 20 \p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" + wire input 19 \p_valid_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 4 \pipe_cr_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 4 \pipe_cr_a$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \pipe_cr_a_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 4 \pipe_cr_b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 4 \pipe_cr_c + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 \pipe_cr_op__fn_unit + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 \pipe_cr_op__fn_unit$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \pipe_cr_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \pipe_cr_op__insn$6 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \pipe_cr_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \pipe_cr_op__insn_type$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 32 \pipe_full_cr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 32 \pipe_full_cr$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \pipe_full_cr_ok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \pipe_muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \pipe_muxid$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" + wire \pipe_n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" + wire \pipe_n_valid_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 \pipe_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \pipe_o_ok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" + wire \pipe_p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" + wire \pipe_p_valid_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \pipe_ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \pipe_rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 13 \ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 14 \rb + attribute \module_not_derived 1 + attribute \src "issuer_ls180.v:23833.9-23836.4" + cell \n$6 \n + connect \n_ready_i \n_ready_i + connect \n_valid_o \n_valid_o + end + attribute \module_not_derived 1 + attribute \src "issuer_ls180.v:23837.9-23840.4" + cell \p$5 \p + connect \p_ready_o \p_ready_o + connect \p_valid_i \p_valid_i + end + attribute \module_not_derived 1 + attribute \src "issuer_ls180.v:23841.8-23868.4" + cell \pipe \pipe + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \cr_a \pipe_cr_a + connect \cr_a$6 \pipe_cr_a$8 + connect \cr_a_ok \pipe_cr_a_ok + connect \cr_b \pipe_cr_b + connect \cr_c \pipe_cr_c + connect \cr_op__fn_unit \pipe_cr_op__fn_unit + connect \cr_op__fn_unit$3 \pipe_cr_op__fn_unit$5 + connect \cr_op__insn \pipe_cr_op__insn + connect \cr_op__insn$4 \pipe_cr_op__insn$6 + connect \cr_op__insn_type \pipe_cr_op__insn_type + connect \cr_op__insn_type$2 \pipe_cr_op__insn_type$4 + connect \full_cr \pipe_full_cr + connect \full_cr$5 \pipe_full_cr$7 + connect \full_cr_ok \pipe_full_cr_ok + connect \muxid \pipe_muxid + connect \muxid$1 \pipe_muxid$3 + connect \n_ready_i \pipe_n_ready_i + connect \n_valid_o \pipe_n_valid_o + connect \o \pipe_o + connect \o_ok \pipe_o_ok + connect \p_ready_o \pipe_p_ready_o + connect \p_valid_i \pipe_p_valid_i + connect \ra \pipe_ra + connect \rb \pipe_rb + end + connect \muxid 2'00 + connect { \cr_a_ok \cr_a } { \pipe_cr_a_ok \pipe_cr_a$8 } + connect { \full_cr_ok \full_cr } { \pipe_full_cr_ok \pipe_full_cr$7 } + connect { \o_ok \o } { \pipe_o_ok \pipe_o } + connect { \cr_op__insn$12 \cr_op__fn_unit$11 \cr_op__insn_type$10 } { \pipe_cr_op__insn$6 \pipe_cr_op__fn_unit$5 \pipe_cr_op__insn_type$4 } + connect \muxid$9 \pipe_muxid$3 + connect \pipe_n_ready_i \n_ready_i + connect \n_valid_o \pipe_n_valid_o + connect \pipe_cr_c \cr_c + connect \pipe_cr_b \cr_b + connect \pipe_cr_a \cr_a$2 + connect \pipe_full_cr \full_cr$1 + connect \pipe_rb \rb + connect \pipe_ra \ra + connect { \pipe_cr_op__insn \pipe_cr_op__fn_unit \pipe_cr_op__insn_type } { \cr_op__insn \cr_op__fn_unit \cr_op__insn_type } + connect \pipe_muxid 2'00 + connect \p_ready_o \pipe_p_ready_o + connect \pipe_p_valid_i \p_valid_i +end +attribute \src "issuer_ls180.v:23891.1-25332.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0" +attribute \generator "nMigen" +module \alu_div0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" + wire input 35 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" + wire input 5 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 4 output 27 \cr_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 2 \cr_a_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 input 24 \logical_op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \logical_op__data_len$88 + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 input 9 \logical_op__fn_unit + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 \logical_op__fn_unit$73 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 input 10 \logical_op__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \logical_op__imm_data__data$74 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 11 \logical_op__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__imm_data__ok$75 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 input 18 \logical_op__input_carry + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \logical_op__input_carry$82 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 25 \logical_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \logical_op__insn$89 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 input 8 \logical_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \logical_op__insn_type$72 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 16 \logical_op__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__invert_in$80 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 19 \logical_op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__invert_out$83 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 22 \logical_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__is_32bit$86 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 23 \logical_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__is_signed$87 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 14 \logical_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__oe__oe$78 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 15 \logical_op__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__oe__ok$79 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 21 \logical_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__output_carry$85 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 13 \logical_op__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__rc__ok$77 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 12 \logical_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__rc__rc$76 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 20 \logical_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__write_cr0$84 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 17 \logical_op__zero_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__zero_a$81 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \muxid$71 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" + wire input 7 \n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" + wire output 6 \n_valid_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 output 26 \o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 1 \o_ok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" + wire output 34 \p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" + wire input 33 \p_valid_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 4 \pipe_end_cr_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \pipe_end_cr_a_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire \pipe_end_div_by_zero + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire \pipe_end_dive_abs_ov32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire \pipe_end_dive_abs_ov64 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire \pipe_end_dividend_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire \pipe_end_divisor_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \pipe_end_logical_op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \pipe_end_logical_op__data_len$68 + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 \pipe_end_logical_op__fn_unit + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 \pipe_end_logical_op__fn_unit$53 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \pipe_end_logical_op__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \pipe_end_logical_op__imm_data__data$54 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe_end_logical_op__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe_end_logical_op__imm_data__ok$55 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \pipe_end_logical_op__input_carry + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \pipe_end_logical_op__input_carry$62 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \pipe_end_logical_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \pipe_end_logical_op__insn$69 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \pipe_end_logical_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \pipe_end_logical_op__insn_type$52 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe_end_logical_op__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe_end_logical_op__invert_in$60 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe_end_logical_op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe_end_logical_op__invert_out$63 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe_end_logical_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe_end_logical_op__is_32bit$66 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe_end_logical_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe_end_logical_op__is_signed$67 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe_end_logical_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe_end_logical_op__oe__oe$58 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe_end_logical_op__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe_end_logical_op__oe__ok$59 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe_end_logical_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe_end_logical_op__output_carry$65 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe_end_logical_op__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe_end_logical_op__rc__ok$57 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe_end_logical_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe_end_logical_op__rc__rc$56 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe_end_logical_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe_end_logical_op__write_cr0$64 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe_end_logical_op__zero_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe_end_logical_op__zero_a$61 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \pipe_end_muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \pipe_end_muxid$51 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" + wire \pipe_end_n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" + wire \pipe_end_n_valid_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 \pipe_end_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \pipe_end_o_ok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" + wire \pipe_end_p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" + wire \pipe_end_p_valid_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:40" + wire width 64 \pipe_end_quotient_root + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \pipe_end_ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \pipe_end_rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:41" + wire width 192 \pipe_end_remainder + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 2 \pipe_end_xer_ov + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \pipe_end_xer_ov_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire \pipe_end_xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \pipe_end_xer_so$70 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \pipe_end_xer_so_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire \pipe_middle_0_div_by_zero + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire \pipe_middle_0_div_by_zero$50 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire \pipe_middle_0_dive_abs_ov32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire \pipe_middle_0_dive_abs_ov32$48 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire \pipe_middle_0_dive_abs_ov64 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire \pipe_middle_0_dive_abs_ov64$49 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:18" + wire width 128 \pipe_middle_0_dividend + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire \pipe_middle_0_dividend_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire \pipe_middle_0_dividend_neg$47 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire \pipe_middle_0_divisor_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire \pipe_middle_0_divisor_neg$46 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:19" + wire width 64 \pipe_middle_0_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \pipe_middle_0_logical_op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \pipe_middle_0_logical_op__data_len$41 + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 \pipe_middle_0_logical_op__fn_unit + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 \pipe_middle_0_logical_op__fn_unit$26 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \pipe_middle_0_logical_op__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \pipe_middle_0_logical_op__imm_data__data$27 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe_middle_0_logical_op__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe_middle_0_logical_op__imm_data__ok$28 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \pipe_middle_0_logical_op__input_carry + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \pipe_middle_0_logical_op__input_carry$35 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \pipe_middle_0_logical_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \pipe_middle_0_logical_op__insn$42 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute 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"OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \pipe_middle_0_logical_op__insn_type$25 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe_middle_0_logical_op__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe_middle_0_logical_op__invert_in$33 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe_middle_0_logical_op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe_middle_0_logical_op__invert_out$36 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe_middle_0_logical_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe_middle_0_logical_op__is_32bit$39 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe_middle_0_logical_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe_middle_0_logical_op__is_signed$40 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe_middle_0_logical_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe_middle_0_logical_op__oe__oe$31 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe_middle_0_logical_op__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe_middle_0_logical_op__oe__ok$32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe_middle_0_logical_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe_middle_0_logical_op__output_carry$38 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe_middle_0_logical_op__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe_middle_0_logical_op__rc__ok$30 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe_middle_0_logical_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe_middle_0_logical_op__rc__rc$29 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe_middle_0_logical_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe_middle_0_logical_op__write_cr0$37 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe_middle_0_logical_op__zero_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe_middle_0_logical_op__zero_a$34 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \pipe_middle_0_muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \pipe_middle_0_muxid$24 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" + wire \pipe_middle_0_n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" + wire \pipe_middle_0_n_valid_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:21" + wire width 2 \pipe_middle_0_operation + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" + wire \pipe_middle_0_p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" + wire \pipe_middle_0_p_valid_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:40" + wire width 64 \pipe_middle_0_quotient_root + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \pipe_middle_0_ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \pipe_middle_0_ra$43 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \pipe_middle_0_rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \pipe_middle_0_rb$44 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:41" + wire width 192 \pipe_middle_0_remainder + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire \pipe_middle_0_xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire \pipe_middle_0_xer_so$45 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire \pipe_start_div_by_zero + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire \pipe_start_dive_abs_ov32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire \pipe_start_dive_abs_ov64 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:18" + wire width 128 \pipe_start_dividend + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire \pipe_start_dividend_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire \pipe_start_divisor_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:19" + wire width 64 \pipe_start_divisor_radicand + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \pipe_start_logical_op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \pipe_start_logical_op__data_len$19 + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 \pipe_start_logical_op__fn_unit + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 \pipe_start_logical_op__fn_unit$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \pipe_start_logical_op__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \pipe_start_logical_op__imm_data__data$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe_start_logical_op__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe_start_logical_op__imm_data__ok$6 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \pipe_start_logical_op__input_carry + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \pipe_start_logical_op__input_carry$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \pipe_start_logical_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \pipe_start_logical_op__insn$20 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \pipe_start_logical_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \pipe_start_logical_op__insn_type$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe_start_logical_op__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe_start_logical_op__invert_in$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe_start_logical_op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe_start_logical_op__invert_out$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe_start_logical_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe_start_logical_op__is_32bit$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe_start_logical_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe_start_logical_op__is_signed$18 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe_start_logical_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe_start_logical_op__oe__oe$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe_start_logical_op__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe_start_logical_op__oe__ok$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe_start_logical_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe_start_logical_op__output_carry$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe_start_logical_op__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe_start_logical_op__rc__ok$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe_start_logical_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe_start_logical_op__rc__rc$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe_start_logical_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe_start_logical_op__write_cr0$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe_start_logical_op__zero_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe_start_logical_op__zero_a$12 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \pipe_start_muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \pipe_start_muxid$2 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" + wire \pipe_start_n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" + wire \pipe_start_n_valid_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:21" + wire width 2 \pipe_start_operation + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" + wire \pipe_start_p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" + wire \pipe_start_p_valid_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \pipe_start_ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \pipe_start_ra$21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \pipe_start_rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \pipe_start_rb$22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire \pipe_start_xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire \pipe_start_xer_so$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 30 \ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 31 \rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 2 output 28 \xer_ov + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 3 \xer_ov_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 29 \xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire input 32 \xer_so$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 4 \xer_so_ok + attribute \module_not_derived 1 + attribute \src "issuer_ls180.v:25088.10-25091.4" + cell \n$72 \n + connect \n_ready_i \n_ready_i + connect \n_valid_o \n_valid_o + end + attribute \module_not_derived 1 + attribute \src "issuer_ls180.v:25092.10-25095.4" + cell \p$71 \p + connect \p_ready_o \p_ready_o + connect \p_valid_i \p_valid_i + end + attribute \module_not_derived 1 + attribute \src "issuer_ls180.v:25096.12-25159.4" + cell \pipe_end \pipe_end + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \cr_a \pipe_end_cr_a + connect \cr_a_ok \pipe_end_cr_a_ok + connect \div_by_zero \pipe_end_div_by_zero + connect \dive_abs_ov32 \pipe_end_dive_abs_ov32 + connect \dive_abs_ov64 \pipe_end_dive_abs_ov64 + connect \dividend_neg \pipe_end_dividend_neg + connect \divisor_neg \pipe_end_divisor_neg + connect \logical_op__data_len \pipe_end_logical_op__data_len + connect \logical_op__data_len$18 \pipe_end_logical_op__data_len$68 + connect \logical_op__fn_unit \pipe_end_logical_op__fn_unit + connect \logical_op__fn_unit$3 \pipe_end_logical_op__fn_unit$53 + connect \logical_op__imm_data__data \pipe_end_logical_op__imm_data__data + connect \logical_op__imm_data__data$4 \pipe_end_logical_op__imm_data__data$54 + connect \logical_op__imm_data__ok \pipe_end_logical_op__imm_data__ok + connect \logical_op__imm_data__ok$5 \pipe_end_logical_op__imm_data__ok$55 + connect \logical_op__input_carry \pipe_end_logical_op__input_carry + connect \logical_op__input_carry$12 \pipe_end_logical_op__input_carry$62 + connect \logical_op__insn \pipe_end_logical_op__insn + connect \logical_op__insn$19 \pipe_end_logical_op__insn$69 + connect \logical_op__insn_type \pipe_end_logical_op__insn_type + connect \logical_op__insn_type$2 \pipe_end_logical_op__insn_type$52 + connect \logical_op__invert_in \pipe_end_logical_op__invert_in + connect \logical_op__invert_in$10 \pipe_end_logical_op__invert_in$60 + connect \logical_op__invert_out \pipe_end_logical_op__invert_out + connect \logical_op__invert_out$13 \pipe_end_logical_op__invert_out$63 + connect \logical_op__is_32bit \pipe_end_logical_op__is_32bit + connect \logical_op__is_32bit$16 \pipe_end_logical_op__is_32bit$66 + connect \logical_op__is_signed \pipe_end_logical_op__is_signed + connect \logical_op__is_signed$17 \pipe_end_logical_op__is_signed$67 + connect \logical_op__oe__oe \pipe_end_logical_op__oe__oe + connect \logical_op__oe__oe$8 \pipe_end_logical_op__oe__oe$58 + connect \logical_op__oe__ok \pipe_end_logical_op__oe__ok + connect \logical_op__oe__ok$9 \pipe_end_logical_op__oe__ok$59 + connect \logical_op__output_carry \pipe_end_logical_op__output_carry + connect \logical_op__output_carry$15 \pipe_end_logical_op__output_carry$65 + connect \logical_op__rc__ok \pipe_end_logical_op__rc__ok + connect \logical_op__rc__ok$7 \pipe_end_logical_op__rc__ok$57 + connect \logical_op__rc__rc \pipe_end_logical_op__rc__rc + connect \logical_op__rc__rc$6 \pipe_end_logical_op__rc__rc$56 + connect \logical_op__write_cr0 \pipe_end_logical_op__write_cr0 + connect \logical_op__write_cr0$14 \pipe_end_logical_op__write_cr0$64 + connect \logical_op__zero_a \pipe_end_logical_op__zero_a + connect \logical_op__zero_a$11 \pipe_end_logical_op__zero_a$61 + connect \muxid \pipe_end_muxid + connect \muxid$1 \pipe_end_muxid$51 + connect \n_ready_i \pipe_end_n_ready_i + connect \n_valid_o \pipe_end_n_valid_o + connect \o \pipe_end_o + connect \o_ok \pipe_end_o_ok + connect \p_ready_o \pipe_end_p_ready_o + connect \p_valid_i \pipe_end_p_valid_i + connect \quotient_root \pipe_end_quotient_root + connect \ra \pipe_end_ra + connect \rb \pipe_end_rb + connect \remainder \pipe_end_remainder + connect \xer_ov \pipe_end_xer_ov + connect \xer_ov_ok \pipe_end_xer_ov_ok + connect \xer_so \pipe_end_xer_so + connect \xer_so$20 \pipe_end_xer_so$70 + connect \xer_so_ok \pipe_end_xer_so_ok + end + attribute \module_not_derived 1 + attribute \src "issuer_ls180.v:25160.17-25226.4" + cell \pipe_middle_0 \pipe_middle_0 + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \div_by_zero \pipe_middle_0_div_by_zero + connect \div_by_zero$27 \pipe_middle_0_div_by_zero$50 + connect \dive_abs_ov32 \pipe_middle_0_dive_abs_ov32 + connect \dive_abs_ov32$25 \pipe_middle_0_dive_abs_ov32$48 + connect \dive_abs_ov64 \pipe_middle_0_dive_abs_ov64 + connect \dive_abs_ov64$26 \pipe_middle_0_dive_abs_ov64$49 + connect \dividend \pipe_middle_0_dividend + connect \dividend_neg \pipe_middle_0_dividend_neg + connect \dividend_neg$24 \pipe_middle_0_dividend_neg$47 + connect \divisor_neg \pipe_middle_0_divisor_neg + connect \divisor_neg$23 \pipe_middle_0_divisor_neg$46 + connect \divisor_radicand \pipe_middle_0_divisor_radicand + connect \logical_op__data_len \pipe_middle_0_logical_op__data_len + connect \logical_op__data_len$18 \pipe_middle_0_logical_op__data_len$41 + connect \logical_op__fn_unit \pipe_middle_0_logical_op__fn_unit + connect \logical_op__fn_unit$3 \pipe_middle_0_logical_op__fn_unit$26 + connect \logical_op__imm_data__data \pipe_middle_0_logical_op__imm_data__data + connect \logical_op__imm_data__data$4 \pipe_middle_0_logical_op__imm_data__data$27 + connect \logical_op__imm_data__ok \pipe_middle_0_logical_op__imm_data__ok + connect \logical_op__imm_data__ok$5 \pipe_middle_0_logical_op__imm_data__ok$28 + connect \logical_op__input_carry \pipe_middle_0_logical_op__input_carry + connect \logical_op__input_carry$12 \pipe_middle_0_logical_op__input_carry$35 + connect \logical_op__insn \pipe_middle_0_logical_op__insn + connect \logical_op__insn$19 \pipe_middle_0_logical_op__insn$42 + connect \logical_op__insn_type \pipe_middle_0_logical_op__insn_type + connect \logical_op__insn_type$2 \pipe_middle_0_logical_op__insn_type$25 + connect \logical_op__invert_in \pipe_middle_0_logical_op__invert_in + connect \logical_op__invert_in$10 \pipe_middle_0_logical_op__invert_in$33 + connect \logical_op__invert_out \pipe_middle_0_logical_op__invert_out + connect \logical_op__invert_out$13 \pipe_middle_0_logical_op__invert_out$36 + connect \logical_op__is_32bit \pipe_middle_0_logical_op__is_32bit + connect \logical_op__is_32bit$16 \pipe_middle_0_logical_op__is_32bit$39 + connect \logical_op__is_signed \pipe_middle_0_logical_op__is_signed + connect \logical_op__is_signed$17 \pipe_middle_0_logical_op__is_signed$40 + connect \logical_op__oe__oe \pipe_middle_0_logical_op__oe__oe + connect \logical_op__oe__oe$8 \pipe_middle_0_logical_op__oe__oe$31 + connect \logical_op__oe__ok \pipe_middle_0_logical_op__oe__ok + connect \logical_op__oe__ok$9 \pipe_middle_0_logical_op__oe__ok$32 + connect \logical_op__output_carry \pipe_middle_0_logical_op__output_carry + connect \logical_op__output_carry$15 \pipe_middle_0_logical_op__output_carry$38 + connect \logical_op__rc__ok \pipe_middle_0_logical_op__rc__ok + connect \logical_op__rc__ok$7 \pipe_middle_0_logical_op__rc__ok$30 + connect \logical_op__rc__rc \pipe_middle_0_logical_op__rc__rc + connect \logical_op__rc__rc$6 \pipe_middle_0_logical_op__rc__rc$29 + connect \logical_op__write_cr0 \pipe_middle_0_logical_op__write_cr0 + connect \logical_op__write_cr0$14 \pipe_middle_0_logical_op__write_cr0$37 + connect \logical_op__zero_a \pipe_middle_0_logical_op__zero_a + connect \logical_op__zero_a$11 \pipe_middle_0_logical_op__zero_a$34 + connect \muxid \pipe_middle_0_muxid + connect \muxid$1 \pipe_middle_0_muxid$24 + connect \n_ready_i \pipe_middle_0_n_ready_i + connect \n_valid_o \pipe_middle_0_n_valid_o + connect \operation \pipe_middle_0_operation + connect \p_ready_o \pipe_middle_0_p_ready_o + connect \p_valid_i \pipe_middle_0_p_valid_i + connect \quotient_root \pipe_middle_0_quotient_root + connect \ra \pipe_middle_0_ra + connect \ra$20 \pipe_middle_0_ra$43 + connect \rb \pipe_middle_0_rb + connect \rb$21 \pipe_middle_0_rb$44 + connect \remainder \pipe_middle_0_remainder + connect \xer_so \pipe_middle_0_xer_so + connect \xer_so$22 \pipe_middle_0_xer_so$45 + end + attribute \module_not_derived 1 + attribute \src "issuer_ls180.v:25227.14-25286.4" + cell \pipe_start \pipe_start + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \div_by_zero \pipe_start_div_by_zero + connect \dive_abs_ov32 \pipe_start_dive_abs_ov32 + connect \dive_abs_ov64 \pipe_start_dive_abs_ov64 + connect \dividend \pipe_start_dividend + connect \dividend_neg \pipe_start_dividend_neg + connect \divisor_neg \pipe_start_divisor_neg + connect \divisor_radicand \pipe_start_divisor_radicand + connect \logical_op__data_len \pipe_start_logical_op__data_len + connect \logical_op__data_len$18 \pipe_start_logical_op__data_len$19 + connect \logical_op__fn_unit \pipe_start_logical_op__fn_unit + connect \logical_op__fn_unit$3 \pipe_start_logical_op__fn_unit$4 + connect \logical_op__imm_data__data \pipe_start_logical_op__imm_data__data + connect \logical_op__imm_data__data$4 \pipe_start_logical_op__imm_data__data$5 + connect \logical_op__imm_data__ok \pipe_start_logical_op__imm_data__ok + connect \logical_op__imm_data__ok$5 \pipe_start_logical_op__imm_data__ok$6 + connect \logical_op__input_carry \pipe_start_logical_op__input_carry + connect \logical_op__input_carry$12 \pipe_start_logical_op__input_carry$13 + connect \logical_op__insn \pipe_start_logical_op__insn + connect \logical_op__insn$19 \pipe_start_logical_op__insn$20 + connect \logical_op__insn_type \pipe_start_logical_op__insn_type + connect \logical_op__insn_type$2 \pipe_start_logical_op__insn_type$3 + connect \logical_op__invert_in \pipe_start_logical_op__invert_in + connect \logical_op__invert_in$10 \pipe_start_logical_op__invert_in$11 + connect \logical_op__invert_out \pipe_start_logical_op__invert_out + connect \logical_op__invert_out$13 \pipe_start_logical_op__invert_out$14 + connect \logical_op__is_32bit \pipe_start_logical_op__is_32bit + connect \logical_op__is_32bit$16 \pipe_start_logical_op__is_32bit$17 + connect \logical_op__is_signed \pipe_start_logical_op__is_signed + connect \logical_op__is_signed$17 \pipe_start_logical_op__is_signed$18 + connect \logical_op__oe__oe \pipe_start_logical_op__oe__oe + connect \logical_op__oe__oe$8 \pipe_start_logical_op__oe__oe$9 + connect \logical_op__oe__ok \pipe_start_logical_op__oe__ok + connect \logical_op__oe__ok$9 \pipe_start_logical_op__oe__ok$10 + connect \logical_op__output_carry \pipe_start_logical_op__output_carry + connect \logical_op__output_carry$15 \pipe_start_logical_op__output_carry$16 + connect \logical_op__rc__ok \pipe_start_logical_op__rc__ok + connect \logical_op__rc__ok$7 \pipe_start_logical_op__rc__ok$8 + connect \logical_op__rc__rc \pipe_start_logical_op__rc__rc + connect \logical_op__rc__rc$6 \pipe_start_logical_op__rc__rc$7 + connect \logical_op__write_cr0 \pipe_start_logical_op__write_cr0 + connect \logical_op__write_cr0$14 \pipe_start_logical_op__write_cr0$15 + connect \logical_op__zero_a \pipe_start_logical_op__zero_a + connect \logical_op__zero_a$11 \pipe_start_logical_op__zero_a$12 + connect \muxid \pipe_start_muxid + connect \muxid$1 \pipe_start_muxid$2 + connect \n_ready_i \pipe_start_n_ready_i + connect \n_valid_o \pipe_start_n_valid_o + connect \operation \pipe_start_operation + connect \p_ready_o \pipe_start_p_ready_o + connect \p_valid_i \pipe_start_p_valid_i + connect \ra \pipe_start_ra + connect \ra$20 \pipe_start_ra$21 + connect \rb \pipe_start_rb + connect \rb$21 \pipe_start_rb$22 + connect \xer_so \pipe_start_xer_so + connect \xer_so$22 \pipe_start_xer_so$23 + end + connect \muxid 2'00 + connect { \xer_so_ok \xer_so } { \pipe_end_xer_so_ok \pipe_end_xer_so$70 } + connect { \xer_ov_ok \xer_ov } { \pipe_end_xer_ov_ok \pipe_end_xer_ov } + connect { \cr_a_ok \cr_a } { \pipe_end_cr_a_ok \pipe_end_cr_a } + connect { \o_ok \o } { \pipe_end_o_ok \pipe_end_o } + connect { \logical_op__insn$89 \logical_op__data_len$88 \logical_op__is_signed$87 \logical_op__is_32bit$86 \logical_op__output_carry$85 \logical_op__write_cr0$84 \logical_op__invert_out$83 \logical_op__input_carry$82 \logical_op__zero_a$81 \logical_op__invert_in$80 \logical_op__oe__ok$79 \logical_op__oe__oe$78 \logical_op__rc__ok$77 \logical_op__rc__rc$76 \logical_op__imm_data__ok$75 \logical_op__imm_data__data$74 \logical_op__fn_unit$73 \logical_op__insn_type$72 } { \pipe_end_logical_op__insn$69 \pipe_end_logical_op__data_len$68 \pipe_end_logical_op__is_signed$67 \pipe_end_logical_op__is_32bit$66 \pipe_end_logical_op__output_carry$65 \pipe_end_logical_op__write_cr0$64 \pipe_end_logical_op__invert_out$63 \pipe_end_logical_op__input_carry$62 \pipe_end_logical_op__zero_a$61 \pipe_end_logical_op__invert_in$60 \pipe_end_logical_op__oe__ok$59 \pipe_end_logical_op__oe__oe$58 \pipe_end_logical_op__rc__ok$57 \pipe_end_logical_op__rc__rc$56 \pipe_end_logical_op__imm_data__ok$55 \pipe_end_logical_op__imm_data__data$54 \pipe_end_logical_op__fn_unit$53 \pipe_end_logical_op__insn_type$52 } + connect \muxid$71 \pipe_end_muxid$51 + connect \pipe_end_n_ready_i \n_ready_i + connect \n_valid_o \pipe_end_n_valid_o + connect \pipe_start_xer_so$23 \xer_so$1 + connect \pipe_start_rb$22 \rb + connect \pipe_start_ra$21 \ra + connect { \pipe_start_logical_op__insn$20 \pipe_start_logical_op__data_len$19 \pipe_start_logical_op__is_signed$18 \pipe_start_logical_op__is_32bit$17 \pipe_start_logical_op__output_carry$16 \pipe_start_logical_op__write_cr0$15 \pipe_start_logical_op__invert_out$14 \pipe_start_logical_op__input_carry$13 \pipe_start_logical_op__zero_a$12 \pipe_start_logical_op__invert_in$11 \pipe_start_logical_op__oe__ok$10 \pipe_start_logical_op__oe__oe$9 \pipe_start_logical_op__rc__ok$8 \pipe_start_logical_op__rc__rc$7 \pipe_start_logical_op__imm_data__ok$6 \pipe_start_logical_op__imm_data__data$5 \pipe_start_logical_op__fn_unit$4 \pipe_start_logical_op__insn_type$3 } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in \logical_op__oe__ok \logical_op__oe__oe \logical_op__rc__ok \logical_op__rc__rc \logical_op__imm_data__ok \logical_op__imm_data__data \logical_op__fn_unit \logical_op__insn_type } + connect \pipe_start_muxid$2 2'00 + connect \p_ready_o \pipe_start_p_ready_o + connect \pipe_start_p_valid_i \p_valid_i + connect \pipe_end_remainder \pipe_middle_0_remainder + connect \pipe_end_quotient_root \pipe_middle_0_quotient_root + connect \pipe_end_div_by_zero \pipe_middle_0_div_by_zero$50 + connect \pipe_end_dive_abs_ov64 \pipe_middle_0_dive_abs_ov64$49 + connect \pipe_end_dive_abs_ov32 \pipe_middle_0_dive_abs_ov32$48 + connect \pipe_end_dividend_neg \pipe_middle_0_dividend_neg$47 + connect \pipe_end_divisor_neg \pipe_middle_0_divisor_neg$46 + connect \pipe_end_xer_so \pipe_middle_0_xer_so$45 + connect \pipe_end_rb \pipe_middle_0_rb$44 + connect \pipe_end_ra \pipe_middle_0_ra$43 + connect { \pipe_end_logical_op__insn \pipe_end_logical_op__data_len \pipe_end_logical_op__is_signed \pipe_end_logical_op__is_32bit \pipe_end_logical_op__output_carry \pipe_end_logical_op__write_cr0 \pipe_end_logical_op__invert_out \pipe_end_logical_op__input_carry \pipe_end_logical_op__zero_a \pipe_end_logical_op__invert_in \pipe_end_logical_op__oe__ok \pipe_end_logical_op__oe__oe \pipe_end_logical_op__rc__ok \pipe_end_logical_op__rc__rc \pipe_end_logical_op__imm_data__ok \pipe_end_logical_op__imm_data__data \pipe_end_logical_op__fn_unit \pipe_end_logical_op__insn_type } { \pipe_middle_0_logical_op__insn$42 \pipe_middle_0_logical_op__data_len$41 \pipe_middle_0_logical_op__is_signed$40 \pipe_middle_0_logical_op__is_32bit$39 \pipe_middle_0_logical_op__output_carry$38 \pipe_middle_0_logical_op__write_cr0$37 \pipe_middle_0_logical_op__invert_out$36 \pipe_middle_0_logical_op__input_carry$35 \pipe_middle_0_logical_op__zero_a$34 \pipe_middle_0_logical_op__invert_in$33 \pipe_middle_0_logical_op__oe__ok$32 \pipe_middle_0_logical_op__oe__oe$31 \pipe_middle_0_logical_op__rc__ok$30 \pipe_middle_0_logical_op__rc__rc$29 \pipe_middle_0_logical_op__imm_data__ok$28 \pipe_middle_0_logical_op__imm_data__data$27 \pipe_middle_0_logical_op__fn_unit$26 \pipe_middle_0_logical_op__insn_type$25 } + connect \pipe_end_muxid \pipe_middle_0_muxid$24 + connect \pipe_middle_0_n_ready_i \pipe_end_p_ready_o + connect \pipe_end_p_valid_i \pipe_middle_0_n_valid_o + connect \pipe_middle_0_operation \pipe_start_operation + connect \pipe_middle_0_divisor_radicand \pipe_start_divisor_radicand + connect \pipe_middle_0_dividend \pipe_start_dividend + connect \pipe_middle_0_div_by_zero \pipe_start_div_by_zero + connect \pipe_middle_0_dive_abs_ov64 \pipe_start_dive_abs_ov64 + connect \pipe_middle_0_dive_abs_ov32 \pipe_start_dive_abs_ov32 + connect \pipe_middle_0_dividend_neg \pipe_start_dividend_neg + connect \pipe_middle_0_divisor_neg \pipe_start_divisor_neg + connect \pipe_middle_0_xer_so \pipe_start_xer_so + connect \pipe_middle_0_rb \pipe_start_rb + connect \pipe_middle_0_ra \pipe_start_ra + connect { \pipe_middle_0_logical_op__insn \pipe_middle_0_logical_op__data_len \pipe_middle_0_logical_op__is_signed \pipe_middle_0_logical_op__is_32bit \pipe_middle_0_logical_op__output_carry \pipe_middle_0_logical_op__write_cr0 \pipe_middle_0_logical_op__invert_out \pipe_middle_0_logical_op__input_carry \pipe_middle_0_logical_op__zero_a \pipe_middle_0_logical_op__invert_in \pipe_middle_0_logical_op__oe__ok \pipe_middle_0_logical_op__oe__oe \pipe_middle_0_logical_op__rc__ok \pipe_middle_0_logical_op__rc__rc \pipe_middle_0_logical_op__imm_data__ok \pipe_middle_0_logical_op__imm_data__data \pipe_middle_0_logical_op__fn_unit \pipe_middle_0_logical_op__insn_type } { \pipe_start_logical_op__insn \pipe_start_logical_op__data_len \pipe_start_logical_op__is_signed \pipe_start_logical_op__is_32bit \pipe_start_logical_op__output_carry \pipe_start_logical_op__write_cr0 \pipe_start_logical_op__invert_out \pipe_start_logical_op__input_carry \pipe_start_logical_op__zero_a \pipe_start_logical_op__invert_in \pipe_start_logical_op__oe__ok \pipe_start_logical_op__oe__oe \pipe_start_logical_op__rc__ok \pipe_start_logical_op__rc__rc \pipe_start_logical_op__imm_data__ok \pipe_start_logical_op__imm_data__data \pipe_start_logical_op__fn_unit \pipe_start_logical_op__insn_type } + connect \pipe_middle_0_muxid \pipe_start_muxid + connect \pipe_start_n_ready_i \pipe_middle_0_p_ready_o + connect \pipe_middle_0_p_valid_i \pipe_start_n_valid_o +end +attribute \src "issuer_ls180.v:25336.1-25394.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.fus.alu0.alu_l" +attribute \generator "nMigen" +module \alu_l + attribute \src "issuer_ls180.v:25337.7-25337.20" + wire $0\initial[0:0] + attribute \src "issuer_ls180.v:25382.3-25390.6" + wire $0\q_int$next[0:0]$775 + attribute \src "issuer_ls180.v:25380.3-25381.27" + wire $0\q_int[0:0] + attribute \src "issuer_ls180.v:25382.3-25390.6" + wire $1\q_int$next[0:0]$776 + attribute \src "issuer_ls180.v:25361.7-25361.19" + wire $1\q_int[0:0] + attribute \src "issuer_ls180.v:25372.17-25372.96" + wire $and$issuer_ls180.v:25372$765_Y + attribute \src "issuer_ls180.v:25377.17-25377.96" + wire $and$issuer_ls180.v:25377$770_Y + attribute \src "issuer_ls180.v:25374.18-25374.93" + wire $not$issuer_ls180.v:25374$767_Y + attribute \src "issuer_ls180.v:25376.17-25376.92" + wire $not$issuer_ls180.v:25376$769_Y + attribute \src "issuer_ls180.v:25379.17-25379.92" + wire $not$issuer_ls180.v:25379$772_Y + attribute \src "issuer_ls180.v:25373.18-25373.98" + wire $or$issuer_ls180.v:25373$766_Y + attribute \src "issuer_ls180.v:25375.18-25375.99" + wire $or$issuer_ls180.v:25375$768_Y + attribute \src "issuer_ls180.v:25378.17-25378.97" + wire $or$issuer_ls180.v:25378$771_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire \$13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" + wire input 5 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" + wire input 1 \coresync_rst + attribute \src "issuer_ls180.v:25337.7-25337.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire output 2 \q_alu + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" + wire \qlq_alu + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + wire \qn_alu + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire input 3 \r_alu + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire input 4 \s_alu + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $and $and$issuer_ls180.v:25372$765 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$7 + connect \Y $and$issuer_ls180.v:25372$765_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $and $and$issuer_ls180.v:25377$770 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$1 + connect \Y $and$issuer_ls180.v:25377$770_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + cell $not $not$issuer_ls180.v:25374$767 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_alu + connect \Y $not$issuer_ls180.v:25374$767_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $not $not$issuer_ls180.v:25376$769 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_alu + connect \Y $not$issuer_ls180.v:25376$769_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $not $not$issuer_ls180.v:25379$772 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_alu + connect \Y $not$issuer_ls180.v:25379$772_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $or $or$issuer_ls180.v:25373$766 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$9 + connect \B \s_alu + connect \Y $or$issuer_ls180.v:25373$766_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + cell $or $or$issuer_ls180.v:25375$768 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_alu + connect \B \q_int + connect \Y $or$issuer_ls180.v:25375$768_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $or $or$issuer_ls180.v:25378$771 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$3 + connect \B \s_alu + connect \Y $or$issuer_ls180.v:25378$771_Y + end + attribute \src "issuer_ls180.v:25337.7-25337.20" + process $proc$issuer_ls180.v:25337$777 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "issuer_ls180.v:25361.7-25361.19" + process $proc$issuer_ls180.v:25361$778 + assign { } { } + assign $1\q_int[0:0] 1'0 + sync always + sync init + update \q_int $1\q_int[0:0] + end + attribute \src "issuer_ls180.v:25380.3-25381.27" + process $proc$issuer_ls180.v:25380$773 + assign { } { } + assign $0\q_int[0:0] \q_int$next + sync posedge \coresync_clk + update \q_int $0\q_int[0:0] + end + attribute \src "issuer_ls180.v:25382.3-25390.6" + process $proc$issuer_ls180.v:25382$774 + assign { } { } + assign { } { } + assign $0\q_int$next[0:0]$775 $1\q_int$next[0:0]$776 + attribute \src "issuer_ls180.v:25383.5-25383.29" + switch \initial + attribute \src "issuer_ls180.v:25383.9-25383.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\q_int$next[0:0]$776 1'0 + case + assign $1\q_int$next[0:0]$776 \$5 + end + sync always + update \q_int$next $0\q_int$next[0:0]$775 + end + connect \$9 $and$issuer_ls180.v:25372$765_Y + connect \$11 $or$issuer_ls180.v:25373$766_Y + connect \$13 $not$issuer_ls180.v:25374$767_Y + connect \$15 $or$issuer_ls180.v:25375$768_Y + connect \$1 $not$issuer_ls180.v:25376$769_Y + connect \$3 $and$issuer_ls180.v:25377$770_Y + connect \$5 $or$issuer_ls180.v:25378$771_Y + connect \$7 $not$issuer_ls180.v:25379$772_Y + connect \qlq_alu \$15 + connect \qn_alu \$13 + connect \q_alu \$11 +end +attribute \src "issuer_ls180.v:25398.1-25456.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.fus.mul0.alu_l" +attribute \generator "nMigen" +module \alu_l$104 + attribute \src "issuer_ls180.v:25399.7-25399.20" + wire $0\initial[0:0] + attribute \src "issuer_ls180.v:25444.3-25452.6" + wire $0\q_int$next[0:0]$789 + attribute \src "issuer_ls180.v:25442.3-25443.27" + wire $0\q_int[0:0] + attribute \src "issuer_ls180.v:25444.3-25452.6" + wire $1\q_int$next[0:0]$790 + attribute \src "issuer_ls180.v:25423.7-25423.19" + wire $1\q_int[0:0] + attribute \src "issuer_ls180.v:25434.17-25434.96" + wire $and$issuer_ls180.v:25434$779_Y + attribute \src "issuer_ls180.v:25439.17-25439.96" + wire $and$issuer_ls180.v:25439$784_Y + attribute \src "issuer_ls180.v:25436.18-25436.93" + wire $not$issuer_ls180.v:25436$781_Y + attribute \src "issuer_ls180.v:25438.17-25438.92" + wire $not$issuer_ls180.v:25438$783_Y + attribute \src "issuer_ls180.v:25441.17-25441.92" + wire $not$issuer_ls180.v:25441$786_Y + attribute \src "issuer_ls180.v:25435.18-25435.98" + wire $or$issuer_ls180.v:25435$780_Y + attribute \src "issuer_ls180.v:25437.18-25437.99" + wire $or$issuer_ls180.v:25437$782_Y + attribute \src "issuer_ls180.v:25440.17-25440.97" + wire $or$issuer_ls180.v:25440$785_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire \$13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" + wire input 5 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" + wire input 1 \coresync_rst + attribute \src "issuer_ls180.v:25399.7-25399.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire output 2 \q_alu + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" + wire \qlq_alu + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + wire \qn_alu + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire input 3 \r_alu + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire input 4 \s_alu + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $and $and$issuer_ls180.v:25434$779 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$7 + connect \Y $and$issuer_ls180.v:25434$779_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $and $and$issuer_ls180.v:25439$784 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$1 + connect \Y $and$issuer_ls180.v:25439$784_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + cell $not $not$issuer_ls180.v:25436$781 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_alu + connect \Y $not$issuer_ls180.v:25436$781_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $not $not$issuer_ls180.v:25438$783 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_alu + connect \Y $not$issuer_ls180.v:25438$783_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $not $not$issuer_ls180.v:25441$786 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_alu + connect \Y $not$issuer_ls180.v:25441$786_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $or $or$issuer_ls180.v:25435$780 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$9 + connect \B \s_alu + connect \Y $or$issuer_ls180.v:25435$780_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + cell $or $or$issuer_ls180.v:25437$782 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_alu + connect \B \q_int + connect \Y $or$issuer_ls180.v:25437$782_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $or $or$issuer_ls180.v:25440$785 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$3 + connect \B \s_alu + connect \Y $or$issuer_ls180.v:25440$785_Y + end + attribute \src "issuer_ls180.v:25399.7-25399.20" + process $proc$issuer_ls180.v:25399$791 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "issuer_ls180.v:25423.7-25423.19" + process $proc$issuer_ls180.v:25423$792 + assign { } { } + assign $1\q_int[0:0] 1'0 + sync always + sync init + update \q_int $1\q_int[0:0] + end + attribute \src "issuer_ls180.v:25442.3-25443.27" + process $proc$issuer_ls180.v:25442$787 + assign { } { } + assign $0\q_int[0:0] \q_int$next + sync posedge \coresync_clk + update \q_int $0\q_int[0:0] + end + attribute \src "issuer_ls180.v:25444.3-25452.6" + process $proc$issuer_ls180.v:25444$788 + assign { } { } + assign { } { } + assign $0\q_int$next[0:0]$789 $1\q_int$next[0:0]$790 + attribute \src "issuer_ls180.v:25445.5-25445.29" + switch \initial + attribute \src "issuer_ls180.v:25445.9-25445.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\q_int$next[0:0]$790 1'0 + case + assign $1\q_int$next[0:0]$790 \$5 + end + sync always + update \q_int$next $0\q_int$next[0:0]$789 + end + connect \$9 $and$issuer_ls180.v:25434$779_Y + connect \$11 $or$issuer_ls180.v:25435$780_Y + connect \$13 $not$issuer_ls180.v:25436$781_Y + connect \$15 $or$issuer_ls180.v:25437$782_Y + connect \$1 $not$issuer_ls180.v:25438$783_Y + connect \$3 $and$issuer_ls180.v:25439$784_Y + connect \$5 $or$issuer_ls180.v:25440$785_Y + connect \$7 $not$issuer_ls180.v:25441$786_Y + connect \qlq_alu \$15 + connect \qn_alu \$13 + connect \q_alu \$11 +end +attribute \src "issuer_ls180.v:25460.1-25518.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.fus.shiftrot0.alu_l" +attribute \generator "nMigen" +module \alu_l$122 + attribute \src "issuer_ls180.v:25461.7-25461.20" + wire $0\initial[0:0] + attribute \src "issuer_ls180.v:25506.3-25514.6" + wire $0\q_int$next[0:0]$803 + attribute \src "issuer_ls180.v:25504.3-25505.27" + wire $0\q_int[0:0] + attribute \src "issuer_ls180.v:25506.3-25514.6" + wire $1\q_int$next[0:0]$804 + attribute \src "issuer_ls180.v:25485.7-25485.19" + wire $1\q_int[0:0] + attribute \src "issuer_ls180.v:25496.17-25496.96" + wire $and$issuer_ls180.v:25496$793_Y + attribute \src "issuer_ls180.v:25501.17-25501.96" + wire $and$issuer_ls180.v:25501$798_Y + attribute \src "issuer_ls180.v:25498.18-25498.93" + wire $not$issuer_ls180.v:25498$795_Y + attribute \src "issuer_ls180.v:25500.17-25500.92" + wire $not$issuer_ls180.v:25500$797_Y + attribute \src "issuer_ls180.v:25503.17-25503.92" + wire $not$issuer_ls180.v:25503$800_Y + attribute \src "issuer_ls180.v:25497.18-25497.98" + wire $or$issuer_ls180.v:25497$794_Y + attribute \src "issuer_ls180.v:25499.18-25499.99" + wire $or$issuer_ls180.v:25499$796_Y + attribute \src "issuer_ls180.v:25502.17-25502.97" + wire $or$issuer_ls180.v:25502$799_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire \$13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" + wire input 5 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" + wire input 1 \coresync_rst + attribute \src "issuer_ls180.v:25461.7-25461.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire output 2 \q_alu + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" + wire \qlq_alu + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + wire \qn_alu + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire input 3 \r_alu + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire input 4 \s_alu + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $and $and$issuer_ls180.v:25496$793 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$7 + connect \Y $and$issuer_ls180.v:25496$793_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $and $and$issuer_ls180.v:25501$798 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$1 + connect \Y $and$issuer_ls180.v:25501$798_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + cell $not $not$issuer_ls180.v:25498$795 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_alu + connect \Y $not$issuer_ls180.v:25498$795_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $not $not$issuer_ls180.v:25500$797 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_alu + connect \Y $not$issuer_ls180.v:25500$797_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $not $not$issuer_ls180.v:25503$800 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_alu + connect \Y $not$issuer_ls180.v:25503$800_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $or $or$issuer_ls180.v:25497$794 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$9 + connect \B \s_alu + connect \Y $or$issuer_ls180.v:25497$794_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + cell $or $or$issuer_ls180.v:25499$796 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_alu + connect \B \q_int + connect \Y $or$issuer_ls180.v:25499$796_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $or $or$issuer_ls180.v:25502$799 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$3 + connect \B \s_alu + connect \Y $or$issuer_ls180.v:25502$799_Y + end + attribute \src "issuer_ls180.v:25461.7-25461.20" + process $proc$issuer_ls180.v:25461$805 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "issuer_ls180.v:25485.7-25485.19" + process $proc$issuer_ls180.v:25485$806 + assign { } { } + assign $1\q_int[0:0] 1'0 + sync always + sync init + update \q_int $1\q_int[0:0] + end + attribute \src "issuer_ls180.v:25504.3-25505.27" + process $proc$issuer_ls180.v:25504$801 + assign { } { } + assign $0\q_int[0:0] \q_int$next + sync posedge \coresync_clk + update \q_int $0\q_int[0:0] + end + attribute \src "issuer_ls180.v:25506.3-25514.6" + process $proc$issuer_ls180.v:25506$802 + assign { } { } + assign { } { } + assign $0\q_int$next[0:0]$803 $1\q_int$next[0:0]$804 + attribute \src "issuer_ls180.v:25507.5-25507.29" + switch \initial + attribute \src "issuer_ls180.v:25507.9-25507.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\q_int$next[0:0]$804 1'0 + case + assign $1\q_int$next[0:0]$804 \$5 + end + sync always + update \q_int$next $0\q_int$next[0:0]$803 + end + connect \$9 $and$issuer_ls180.v:25496$793_Y + connect \$11 $or$issuer_ls180.v:25497$794_Y + connect \$13 $not$issuer_ls180.v:25498$795_Y + connect \$15 $or$issuer_ls180.v:25499$796_Y + connect \$1 $not$issuer_ls180.v:25500$797_Y + connect \$3 $and$issuer_ls180.v:25501$798_Y + connect \$5 $or$issuer_ls180.v:25502$799_Y + connect \$7 $not$issuer_ls180.v:25503$800_Y + connect \qlq_alu \$15 + connect \qn_alu \$13 + connect \q_alu \$11 +end +attribute \src "issuer_ls180.v:25522.1-25580.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.fus.ldst0.alu_l" +attribute \generator "nMigen" +module \alu_l$125 + attribute \src "issuer_ls180.v:25523.7-25523.20" + wire $0\initial[0:0] + attribute \src "issuer_ls180.v:25568.3-25576.6" + wire $0\q_int$next[0:0]$817 + attribute \src "issuer_ls180.v:25566.3-25567.27" + wire $0\q_int[0:0] + attribute \src "issuer_ls180.v:25568.3-25576.6" + wire $1\q_int$next[0:0]$818 + attribute \src "issuer_ls180.v:25547.7-25547.19" + wire $1\q_int[0:0] + attribute \src "issuer_ls180.v:25558.17-25558.96" + wire $and$issuer_ls180.v:25558$807_Y + attribute \src "issuer_ls180.v:25563.17-25563.96" + wire $and$issuer_ls180.v:25563$812_Y + attribute \src "issuer_ls180.v:25560.18-25560.93" + wire $not$issuer_ls180.v:25560$809_Y + attribute \src "issuer_ls180.v:25562.17-25562.92" + wire $not$issuer_ls180.v:25562$811_Y + attribute \src "issuer_ls180.v:25565.17-25565.92" + wire $not$issuer_ls180.v:25565$814_Y + attribute \src "issuer_ls180.v:25559.18-25559.98" + wire $or$issuer_ls180.v:25559$808_Y + attribute \src "issuer_ls180.v:25561.18-25561.99" + wire $or$issuer_ls180.v:25561$810_Y + attribute \src "issuer_ls180.v:25564.17-25564.97" + wire $or$issuer_ls180.v:25564$813_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire \$13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" + wire input 5 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" + wire input 1 \coresync_rst + attribute \src "issuer_ls180.v:25523.7-25523.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire output 4 \q_alu + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" + wire \qlq_alu + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + wire \qn_alu + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire input 3 \r_alu + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire input 2 \s_alu + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $and $and$issuer_ls180.v:25558$807 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$7 + connect \Y $and$issuer_ls180.v:25558$807_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $and $and$issuer_ls180.v:25563$812 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$1 + connect \Y $and$issuer_ls180.v:25563$812_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + cell $not $not$issuer_ls180.v:25560$809 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_alu + connect \Y $not$issuer_ls180.v:25560$809_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $not $not$issuer_ls180.v:25562$811 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_alu + connect \Y $not$issuer_ls180.v:25562$811_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $not $not$issuer_ls180.v:25565$814 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_alu + connect \Y $not$issuer_ls180.v:25565$814_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $or $or$issuer_ls180.v:25559$808 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$9 + connect \B \s_alu + connect \Y $or$issuer_ls180.v:25559$808_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + cell $or $or$issuer_ls180.v:25561$810 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_alu + connect \B \q_int + connect \Y $or$issuer_ls180.v:25561$810_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $or $or$issuer_ls180.v:25564$813 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$3 + connect \B \s_alu + connect \Y $or$issuer_ls180.v:25564$813_Y + end + attribute \src "issuer_ls180.v:25523.7-25523.20" + process $proc$issuer_ls180.v:25523$819 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "issuer_ls180.v:25547.7-25547.19" + process $proc$issuer_ls180.v:25547$820 + assign { } { } + assign $1\q_int[0:0] 1'0 + sync always + sync init + update \q_int $1\q_int[0:0] + end + attribute \src "issuer_ls180.v:25566.3-25567.27" + process $proc$issuer_ls180.v:25566$815 + assign { } { } + assign $0\q_int[0:0] \q_int$next + sync posedge \coresync_clk + update \q_int $0\q_int[0:0] + end + attribute \src "issuer_ls180.v:25568.3-25576.6" + process $proc$issuer_ls180.v:25568$816 + assign { } { } + assign { } { } + assign $0\q_int$next[0:0]$817 $1\q_int$next[0:0]$818 + attribute \src "issuer_ls180.v:25569.5-25569.29" + switch \initial + attribute \src "issuer_ls180.v:25569.9-25569.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\q_int$next[0:0]$818 1'0 + case + assign $1\q_int$next[0:0]$818 \$5 + end + sync always + update \q_int$next $0\q_int$next[0:0]$817 + end + connect \$9 $and$issuer_ls180.v:25558$807_Y + connect \$11 $or$issuer_ls180.v:25559$808_Y + connect \$13 $not$issuer_ls180.v:25560$809_Y + connect \$15 $or$issuer_ls180.v:25561$810_Y + connect \$1 $not$issuer_ls180.v:25562$811_Y + connect \$3 $and$issuer_ls180.v:25563$812_Y + connect \$5 $or$issuer_ls180.v:25564$813_Y + connect \$7 $not$issuer_ls180.v:25565$814_Y + connect \qlq_alu \$15 + connect \qn_alu \$13 + connect \q_alu \$11 +end +attribute \src "issuer_ls180.v:25584.1-25642.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.fus.cr0.alu_l" +attribute \generator "nMigen" +module \alu_l$16 + attribute \src "issuer_ls180.v:25585.7-25585.20" + wire $0\initial[0:0] + attribute \src "issuer_ls180.v:25630.3-25638.6" + wire $0\q_int$next[0:0]$831 + attribute \src "issuer_ls180.v:25628.3-25629.27" + wire $0\q_int[0:0] + attribute \src "issuer_ls180.v:25630.3-25638.6" + wire $1\q_int$next[0:0]$832 + attribute \src "issuer_ls180.v:25609.7-25609.19" + wire $1\q_int[0:0] + attribute \src "issuer_ls180.v:25620.17-25620.96" + wire $and$issuer_ls180.v:25620$821_Y + attribute \src "issuer_ls180.v:25625.17-25625.96" + wire $and$issuer_ls180.v:25625$826_Y + attribute \src "issuer_ls180.v:25622.18-25622.93" + wire $not$issuer_ls180.v:25622$823_Y + attribute \src "issuer_ls180.v:25624.17-25624.92" + wire $not$issuer_ls180.v:25624$825_Y + attribute \src "issuer_ls180.v:25627.17-25627.92" + wire $not$issuer_ls180.v:25627$828_Y + attribute \src "issuer_ls180.v:25621.18-25621.98" + wire $or$issuer_ls180.v:25621$822_Y + attribute \src "issuer_ls180.v:25623.18-25623.99" + wire $or$issuer_ls180.v:25623$824_Y + attribute \src "issuer_ls180.v:25626.17-25626.97" + wire $or$issuer_ls180.v:25626$827_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire \$13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" + wire input 5 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" + wire input 1 \coresync_rst + attribute \src "issuer_ls180.v:25585.7-25585.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire output 2 \q_alu + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" + wire \qlq_alu + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + wire \qn_alu + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire input 3 \r_alu + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire input 4 \s_alu + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $and $and$issuer_ls180.v:25620$821 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$7 + connect \Y $and$issuer_ls180.v:25620$821_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $and $and$issuer_ls180.v:25625$826 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$1 + connect \Y $and$issuer_ls180.v:25625$826_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + cell $not $not$issuer_ls180.v:25622$823 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_alu + connect \Y $not$issuer_ls180.v:25622$823_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $not $not$issuer_ls180.v:25624$825 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_alu + connect \Y $not$issuer_ls180.v:25624$825_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $not $not$issuer_ls180.v:25627$828 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_alu + connect \Y $not$issuer_ls180.v:25627$828_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $or $or$issuer_ls180.v:25621$822 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$9 + connect \B \s_alu + connect \Y $or$issuer_ls180.v:25621$822_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + cell $or $or$issuer_ls180.v:25623$824 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_alu + connect \B \q_int + connect \Y $or$issuer_ls180.v:25623$824_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $or $or$issuer_ls180.v:25626$827 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$3 + connect \B \s_alu + connect \Y $or$issuer_ls180.v:25626$827_Y + end + attribute \src "issuer_ls180.v:25585.7-25585.20" + process $proc$issuer_ls180.v:25585$833 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "issuer_ls180.v:25609.7-25609.19" + process $proc$issuer_ls180.v:25609$834 + assign { } { } + assign $1\q_int[0:0] 1'0 + sync always + sync init + update \q_int $1\q_int[0:0] + end + attribute \src "issuer_ls180.v:25628.3-25629.27" + process $proc$issuer_ls180.v:25628$829 + assign { } { } + assign $0\q_int[0:0] \q_int$next + sync posedge \coresync_clk + update \q_int $0\q_int[0:0] + end + attribute \src "issuer_ls180.v:25630.3-25638.6" + process $proc$issuer_ls180.v:25630$830 + assign { } { } + assign { } { } + assign $0\q_int$next[0:0]$831 $1\q_int$next[0:0]$832 + attribute \src "issuer_ls180.v:25631.5-25631.29" + switch \initial + attribute \src "issuer_ls180.v:25631.9-25631.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\q_int$next[0:0]$832 1'0 + case + assign $1\q_int$next[0:0]$832 \$5 + end + sync always + update \q_int$next $0\q_int$next[0:0]$831 + end + connect \$9 $and$issuer_ls180.v:25620$821_Y + connect \$11 $or$issuer_ls180.v:25621$822_Y + connect \$13 $not$issuer_ls180.v:25622$823_Y + connect \$15 $or$issuer_ls180.v:25623$824_Y + connect \$1 $not$issuer_ls180.v:25624$825_Y + connect \$3 $and$issuer_ls180.v:25625$826_Y + connect \$5 $or$issuer_ls180.v:25626$827_Y + connect \$7 $not$issuer_ls180.v:25627$828_Y + connect \qlq_alu \$15 + connect \qn_alu \$13 + connect \q_alu \$11 +end +attribute \src "issuer_ls180.v:25646.1-25704.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.fus.branch0.alu_l" +attribute \generator "nMigen" +module \alu_l$29 + attribute \src "issuer_ls180.v:25647.7-25647.20" + wire $0\initial[0:0] + attribute \src "issuer_ls180.v:25692.3-25700.6" + wire $0\q_int$next[0:0]$845 + attribute \src "issuer_ls180.v:25690.3-25691.27" + wire $0\q_int[0:0] + attribute \src "issuer_ls180.v:25692.3-25700.6" + wire $1\q_int$next[0:0]$846 + attribute \src "issuer_ls180.v:25671.7-25671.19" + wire $1\q_int[0:0] + attribute \src "issuer_ls180.v:25682.17-25682.96" + wire $and$issuer_ls180.v:25682$835_Y + attribute \src "issuer_ls180.v:25687.17-25687.96" + wire $and$issuer_ls180.v:25687$840_Y + attribute \src "issuer_ls180.v:25684.18-25684.93" + wire $not$issuer_ls180.v:25684$837_Y + attribute \src "issuer_ls180.v:25686.17-25686.92" + wire $not$issuer_ls180.v:25686$839_Y + attribute \src "issuer_ls180.v:25689.17-25689.92" + wire $not$issuer_ls180.v:25689$842_Y + attribute \src "issuer_ls180.v:25683.18-25683.98" + wire $or$issuer_ls180.v:25683$836_Y + attribute \src "issuer_ls180.v:25685.18-25685.99" + wire $or$issuer_ls180.v:25685$838_Y + attribute \src "issuer_ls180.v:25688.17-25688.97" + wire $or$issuer_ls180.v:25688$841_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire \$13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" + wire input 5 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" + wire input 1 \coresync_rst + attribute \src "issuer_ls180.v:25647.7-25647.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire output 2 \q_alu + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" + wire \qlq_alu + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + wire \qn_alu + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire input 3 \r_alu + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire input 4 \s_alu + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $and $and$issuer_ls180.v:25682$835 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$7 + connect \Y $and$issuer_ls180.v:25682$835_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $and $and$issuer_ls180.v:25687$840 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$1 + connect \Y $and$issuer_ls180.v:25687$840_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + cell $not $not$issuer_ls180.v:25684$837 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_alu + connect \Y $not$issuer_ls180.v:25684$837_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $not $not$issuer_ls180.v:25686$839 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_alu + connect \Y $not$issuer_ls180.v:25686$839_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $not $not$issuer_ls180.v:25689$842 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_alu + connect \Y $not$issuer_ls180.v:25689$842_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $or $or$issuer_ls180.v:25683$836 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$9 + connect \B \s_alu + connect \Y $or$issuer_ls180.v:25683$836_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + cell $or $or$issuer_ls180.v:25685$838 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_alu + connect \B \q_int + connect \Y $or$issuer_ls180.v:25685$838_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $or $or$issuer_ls180.v:25688$841 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$3 + connect \B \s_alu + connect \Y $or$issuer_ls180.v:25688$841_Y + end + attribute \src "issuer_ls180.v:25647.7-25647.20" + process $proc$issuer_ls180.v:25647$847 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "issuer_ls180.v:25671.7-25671.19" + process $proc$issuer_ls180.v:25671$848 + assign { } { } + assign $1\q_int[0:0] 1'0 + sync always + sync init + update \q_int $1\q_int[0:0] + end + attribute \src "issuer_ls180.v:25690.3-25691.27" + process $proc$issuer_ls180.v:25690$843 + assign { } { } + assign $0\q_int[0:0] \q_int$next + sync posedge \coresync_clk + update \q_int $0\q_int[0:0] + end + attribute \src "issuer_ls180.v:25692.3-25700.6" + process $proc$issuer_ls180.v:25692$844 + assign { } { } + assign { } { } + assign $0\q_int$next[0:0]$845 $1\q_int$next[0:0]$846 + attribute \src "issuer_ls180.v:25693.5-25693.29" + switch \initial + attribute \src "issuer_ls180.v:25693.9-25693.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\q_int$next[0:0]$846 1'0 + case + assign $1\q_int$next[0:0]$846 \$5 + end + sync always + update \q_int$next $0\q_int$next[0:0]$845 + end + connect \$9 $and$issuer_ls180.v:25682$835_Y + connect \$11 $or$issuer_ls180.v:25683$836_Y + connect \$13 $not$issuer_ls180.v:25684$837_Y + connect \$15 $or$issuer_ls180.v:25685$838_Y + connect \$1 $not$issuer_ls180.v:25686$839_Y + connect \$3 $and$issuer_ls180.v:25687$840_Y + connect \$5 $or$issuer_ls180.v:25688$841_Y + connect \$7 $not$issuer_ls180.v:25689$842_Y + connect \qlq_alu \$15 + connect \qn_alu \$13 + connect \q_alu \$11 +end +attribute \src "issuer_ls180.v:25708.1-25766.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.fus.trap0.alu_l" +attribute \generator "nMigen" +module \alu_l$42 + attribute \src "issuer_ls180.v:25709.7-25709.20" + wire $0\initial[0:0] + attribute \src "issuer_ls180.v:25754.3-25762.6" + wire $0\q_int$next[0:0]$859 + attribute \src "issuer_ls180.v:25752.3-25753.27" + wire $0\q_int[0:0] + attribute \src "issuer_ls180.v:25754.3-25762.6" + wire $1\q_int$next[0:0]$860 + attribute \src "issuer_ls180.v:25733.7-25733.19" + wire $1\q_int[0:0] + attribute \src "issuer_ls180.v:25744.17-25744.96" + wire $and$issuer_ls180.v:25744$849_Y + attribute \src "issuer_ls180.v:25749.17-25749.96" + wire $and$issuer_ls180.v:25749$854_Y + attribute \src "issuer_ls180.v:25746.18-25746.93" + wire $not$issuer_ls180.v:25746$851_Y + attribute \src "issuer_ls180.v:25748.17-25748.92" + wire $not$issuer_ls180.v:25748$853_Y + attribute \src "issuer_ls180.v:25751.17-25751.92" + wire $not$issuer_ls180.v:25751$856_Y + attribute \src "issuer_ls180.v:25745.18-25745.98" + wire $or$issuer_ls180.v:25745$850_Y + attribute \src "issuer_ls180.v:25747.18-25747.99" + wire $or$issuer_ls180.v:25747$852_Y + attribute \src "issuer_ls180.v:25750.17-25750.97" + wire $or$issuer_ls180.v:25750$855_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire \$13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" + wire input 5 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" + wire input 1 \coresync_rst + attribute \src "issuer_ls180.v:25709.7-25709.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire output 2 \q_alu + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" + wire \qlq_alu + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + wire \qn_alu + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire input 3 \r_alu + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire input 4 \s_alu + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $and $and$issuer_ls180.v:25744$849 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$7 + connect \Y $and$issuer_ls180.v:25744$849_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $and $and$issuer_ls180.v:25749$854 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$1 + connect \Y $and$issuer_ls180.v:25749$854_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + cell $not $not$issuer_ls180.v:25746$851 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_alu + connect \Y $not$issuer_ls180.v:25746$851_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $not $not$issuer_ls180.v:25748$853 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_alu + connect \Y $not$issuer_ls180.v:25748$853_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $not $not$issuer_ls180.v:25751$856 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_alu + connect \Y $not$issuer_ls180.v:25751$856_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $or $or$issuer_ls180.v:25745$850 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$9 + connect \B \s_alu + connect \Y $or$issuer_ls180.v:25745$850_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + cell $or $or$issuer_ls180.v:25747$852 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_alu + connect \B \q_int + connect \Y $or$issuer_ls180.v:25747$852_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $or $or$issuer_ls180.v:25750$855 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$3 + connect \B \s_alu + connect \Y $or$issuer_ls180.v:25750$855_Y + end + attribute \src "issuer_ls180.v:25709.7-25709.20" + process $proc$issuer_ls180.v:25709$861 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "issuer_ls180.v:25733.7-25733.19" + process $proc$issuer_ls180.v:25733$862 + assign { } { } + assign $1\q_int[0:0] 1'0 + sync always + sync init + update \q_int $1\q_int[0:0] + end + attribute \src "issuer_ls180.v:25752.3-25753.27" + process $proc$issuer_ls180.v:25752$857 + assign { } { } + assign $0\q_int[0:0] \q_int$next + sync posedge \coresync_clk + update \q_int $0\q_int[0:0] + end + attribute \src "issuer_ls180.v:25754.3-25762.6" + process $proc$issuer_ls180.v:25754$858 + assign { } { } + assign { } { } + assign $0\q_int$next[0:0]$859 $1\q_int$next[0:0]$860 + attribute \src "issuer_ls180.v:25755.5-25755.29" + switch \initial + attribute \src "issuer_ls180.v:25755.9-25755.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\q_int$next[0:0]$860 1'0 + case + assign $1\q_int$next[0:0]$860 \$5 + end + sync always + update \q_int$next $0\q_int$next[0:0]$859 + end + connect \$9 $and$issuer_ls180.v:25744$849_Y + connect \$11 $or$issuer_ls180.v:25745$850_Y + connect \$13 $not$issuer_ls180.v:25746$851_Y + connect \$15 $or$issuer_ls180.v:25747$852_Y + connect \$1 $not$issuer_ls180.v:25748$853_Y + connect \$3 $and$issuer_ls180.v:25749$854_Y + connect \$5 $or$issuer_ls180.v:25750$855_Y + connect \$7 $not$issuer_ls180.v:25751$856_Y + connect \qlq_alu \$15 + connect \qn_alu \$13 + connect \q_alu \$11 +end +attribute \src "issuer_ls180.v:25770.1-25828.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.fus.logical0.alu_l" +attribute \generator "nMigen" +module \alu_l$58 + attribute \src "issuer_ls180.v:25771.7-25771.20" + wire $0\initial[0:0] + attribute \src "issuer_ls180.v:25816.3-25824.6" + wire $0\q_int$next[0:0]$873 + attribute \src "issuer_ls180.v:25814.3-25815.27" + wire $0\q_int[0:0] + attribute \src "issuer_ls180.v:25816.3-25824.6" + wire $1\q_int$next[0:0]$874 + attribute \src "issuer_ls180.v:25795.7-25795.19" + wire $1\q_int[0:0] + attribute \src "issuer_ls180.v:25806.17-25806.96" + wire $and$issuer_ls180.v:25806$863_Y + attribute \src "issuer_ls180.v:25811.17-25811.96" + wire $and$issuer_ls180.v:25811$868_Y + attribute \src "issuer_ls180.v:25808.18-25808.93" + wire $not$issuer_ls180.v:25808$865_Y + attribute \src "issuer_ls180.v:25810.17-25810.92" + wire $not$issuer_ls180.v:25810$867_Y + attribute \src "issuer_ls180.v:25813.17-25813.92" + wire $not$issuer_ls180.v:25813$870_Y + attribute \src "issuer_ls180.v:25807.18-25807.98" + wire $or$issuer_ls180.v:25807$864_Y + attribute \src "issuer_ls180.v:25809.18-25809.99" + wire $or$issuer_ls180.v:25809$866_Y + attribute \src "issuer_ls180.v:25812.17-25812.97" + wire $or$issuer_ls180.v:25812$869_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire \$13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" + wire input 5 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" + wire input 1 \coresync_rst + attribute \src "issuer_ls180.v:25771.7-25771.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire output 2 \q_alu + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" + wire \qlq_alu + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + wire \qn_alu + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire input 3 \r_alu + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire input 4 \s_alu + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $and $and$issuer_ls180.v:25806$863 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$7 + connect \Y $and$issuer_ls180.v:25806$863_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $and $and$issuer_ls180.v:25811$868 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$1 + connect \Y $and$issuer_ls180.v:25811$868_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + cell $not $not$issuer_ls180.v:25808$865 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_alu + connect \Y $not$issuer_ls180.v:25808$865_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $not $not$issuer_ls180.v:25810$867 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_alu + connect \Y $not$issuer_ls180.v:25810$867_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $not $not$issuer_ls180.v:25813$870 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_alu + connect \Y $not$issuer_ls180.v:25813$870_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $or $or$issuer_ls180.v:25807$864 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$9 + connect \B \s_alu + connect \Y $or$issuer_ls180.v:25807$864_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + cell $or $or$issuer_ls180.v:25809$866 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_alu + connect \B \q_int + connect \Y $or$issuer_ls180.v:25809$866_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $or $or$issuer_ls180.v:25812$869 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$3 + connect \B \s_alu + connect \Y $or$issuer_ls180.v:25812$869_Y + end + attribute \src "issuer_ls180.v:25771.7-25771.20" + process $proc$issuer_ls180.v:25771$875 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "issuer_ls180.v:25795.7-25795.19" + process $proc$issuer_ls180.v:25795$876 + assign { } { } + assign $1\q_int[0:0] 1'0 + sync always + sync init + update \q_int $1\q_int[0:0] + end + attribute \src "issuer_ls180.v:25814.3-25815.27" + process $proc$issuer_ls180.v:25814$871 + assign { } { } + assign $0\q_int[0:0] \q_int$next + sync posedge \coresync_clk + update \q_int $0\q_int[0:0] + end + attribute \src "issuer_ls180.v:25816.3-25824.6" + process $proc$issuer_ls180.v:25816$872 + assign { } { } + assign { } { } + assign $0\q_int$next[0:0]$873 $1\q_int$next[0:0]$874 + attribute \src "issuer_ls180.v:25817.5-25817.29" + switch \initial + attribute \src "issuer_ls180.v:25817.9-25817.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\q_int$next[0:0]$874 1'0 + case + assign $1\q_int$next[0:0]$874 \$5 + end + sync always + update \q_int$next $0\q_int$next[0:0]$873 + end + connect \$9 $and$issuer_ls180.v:25806$863_Y + connect \$11 $or$issuer_ls180.v:25807$864_Y + connect \$13 $not$issuer_ls180.v:25808$865_Y + connect \$15 $or$issuer_ls180.v:25809$866_Y + connect \$1 $not$issuer_ls180.v:25810$867_Y + connect \$3 $and$issuer_ls180.v:25811$868_Y + connect \$5 $or$issuer_ls180.v:25812$869_Y + connect \$7 $not$issuer_ls180.v:25813$870_Y + connect \qlq_alu \$15 + connect \qn_alu \$13 + connect \q_alu \$11 +end +attribute \src "issuer_ls180.v:25832.1-25890.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.fus.spr0.alu_l" +attribute \generator "nMigen" +module \alu_l$70 + attribute \src "issuer_ls180.v:25833.7-25833.20" + wire $0\initial[0:0] + attribute \src "issuer_ls180.v:25878.3-25886.6" + wire $0\q_int$next[0:0]$887 + attribute \src "issuer_ls180.v:25876.3-25877.27" + wire $0\q_int[0:0] + attribute \src "issuer_ls180.v:25878.3-25886.6" + wire $1\q_int$next[0:0]$888 + attribute \src "issuer_ls180.v:25857.7-25857.19" + wire $1\q_int[0:0] + attribute \src "issuer_ls180.v:25868.17-25868.96" + wire $and$issuer_ls180.v:25868$877_Y + attribute \src "issuer_ls180.v:25873.17-25873.96" + wire $and$issuer_ls180.v:25873$882_Y + attribute \src "issuer_ls180.v:25870.18-25870.93" + wire $not$issuer_ls180.v:25870$879_Y + attribute \src "issuer_ls180.v:25872.17-25872.92" + wire $not$issuer_ls180.v:25872$881_Y + attribute \src "issuer_ls180.v:25875.17-25875.92" + wire $not$issuer_ls180.v:25875$884_Y + attribute \src "issuer_ls180.v:25869.18-25869.98" + wire $or$issuer_ls180.v:25869$878_Y + attribute \src "issuer_ls180.v:25871.18-25871.99" + wire $or$issuer_ls180.v:25871$880_Y + attribute \src "issuer_ls180.v:25874.17-25874.97" + wire $or$issuer_ls180.v:25874$883_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire \$13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" + wire input 5 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" + wire input 1 \coresync_rst + attribute \src "issuer_ls180.v:25833.7-25833.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire output 2 \q_alu + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" + wire \qlq_alu + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + wire \qn_alu + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire input 3 \r_alu + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire input 4 \s_alu + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $and $and$issuer_ls180.v:25868$877 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$7 + connect \Y $and$issuer_ls180.v:25868$877_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $and $and$issuer_ls180.v:25873$882 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$1 + connect \Y $and$issuer_ls180.v:25873$882_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + cell $not $not$issuer_ls180.v:25870$879 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_alu + connect \Y $not$issuer_ls180.v:25870$879_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $not $not$issuer_ls180.v:25872$881 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_alu + connect \Y $not$issuer_ls180.v:25872$881_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $not $not$issuer_ls180.v:25875$884 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_alu + connect \Y $not$issuer_ls180.v:25875$884_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $or $or$issuer_ls180.v:25869$878 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$9 + connect \B \s_alu + connect \Y $or$issuer_ls180.v:25869$878_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + cell $or $or$issuer_ls180.v:25871$880 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_alu + connect \B \q_int + connect \Y $or$issuer_ls180.v:25871$880_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $or $or$issuer_ls180.v:25874$883 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$3 + connect \B \s_alu + connect \Y $or$issuer_ls180.v:25874$883_Y + end + attribute \src "issuer_ls180.v:25833.7-25833.20" + process $proc$issuer_ls180.v:25833$889 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "issuer_ls180.v:25857.7-25857.19" + process $proc$issuer_ls180.v:25857$890 + assign { } { } + assign $1\q_int[0:0] 1'0 + sync always + sync init + update \q_int $1\q_int[0:0] + end + attribute \src "issuer_ls180.v:25876.3-25877.27" + process $proc$issuer_ls180.v:25876$885 + assign { } { } + assign $0\q_int[0:0] \q_int$next + sync posedge \coresync_clk + update \q_int $0\q_int[0:0] + end + attribute \src "issuer_ls180.v:25878.3-25886.6" + process $proc$issuer_ls180.v:25878$886 + assign { } { } + assign { } { } + assign $0\q_int$next[0:0]$887 $1\q_int$next[0:0]$888 + attribute \src "issuer_ls180.v:25879.5-25879.29" + switch \initial + attribute \src "issuer_ls180.v:25879.9-25879.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\q_int$next[0:0]$888 1'0 + case + assign $1\q_int$next[0:0]$888 \$5 + end + sync always + update \q_int$next $0\q_int$next[0:0]$887 + end + connect \$9 $and$issuer_ls180.v:25868$877_Y + connect \$11 $or$issuer_ls180.v:25869$878_Y + connect \$13 $not$issuer_ls180.v:25870$879_Y + connect \$15 $or$issuer_ls180.v:25871$880_Y + connect \$1 $not$issuer_ls180.v:25872$881_Y + connect \$3 $and$issuer_ls180.v:25873$882_Y + connect \$5 $or$issuer_ls180.v:25874$883_Y + connect \$7 $not$issuer_ls180.v:25875$884_Y + connect \qlq_alu \$15 + connect \qn_alu \$13 + connect \q_alu \$11 +end +attribute \src "issuer_ls180.v:25894.1-25952.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_l" +attribute \generator "nMigen" +module \alu_l$87 + attribute \src "issuer_ls180.v:25895.7-25895.20" + wire $0\initial[0:0] + attribute \src "issuer_ls180.v:25940.3-25948.6" + wire $0\q_int$next[0:0]$901 + attribute \src "issuer_ls180.v:25938.3-25939.27" + wire $0\q_int[0:0] + attribute \src "issuer_ls180.v:25940.3-25948.6" + wire $1\q_int$next[0:0]$902 + attribute \src "issuer_ls180.v:25919.7-25919.19" + wire $1\q_int[0:0] + attribute \src "issuer_ls180.v:25930.17-25930.96" + wire $and$issuer_ls180.v:25930$891_Y + attribute \src "issuer_ls180.v:25935.17-25935.96" + wire $and$issuer_ls180.v:25935$896_Y + attribute \src "issuer_ls180.v:25932.18-25932.93" + wire $not$issuer_ls180.v:25932$893_Y + attribute \src "issuer_ls180.v:25934.17-25934.92" + wire $not$issuer_ls180.v:25934$895_Y + attribute \src "issuer_ls180.v:25937.17-25937.92" + wire $not$issuer_ls180.v:25937$898_Y + attribute \src "issuer_ls180.v:25931.18-25931.98" + wire $or$issuer_ls180.v:25931$892_Y + attribute \src "issuer_ls180.v:25933.18-25933.99" + wire $or$issuer_ls180.v:25933$894_Y + attribute \src "issuer_ls180.v:25936.17-25936.97" + wire $or$issuer_ls180.v:25936$897_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire \$13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" + wire input 5 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" + wire input 1 \coresync_rst + attribute \src "issuer_ls180.v:25895.7-25895.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire output 2 \q_alu + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" + wire \qlq_alu + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + wire \qn_alu + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire input 3 \r_alu + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire input 4 \s_alu + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $and $and$issuer_ls180.v:25930$891 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$7 + connect \Y $and$issuer_ls180.v:25930$891_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $and $and$issuer_ls180.v:25935$896 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$1 + connect \Y $and$issuer_ls180.v:25935$896_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + cell $not $not$issuer_ls180.v:25932$893 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_alu + connect \Y $not$issuer_ls180.v:25932$893_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $not $not$issuer_ls180.v:25934$895 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_alu + connect \Y $not$issuer_ls180.v:25934$895_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $not $not$issuer_ls180.v:25937$898 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_alu + connect \Y $not$issuer_ls180.v:25937$898_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $or $or$issuer_ls180.v:25931$892 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$9 + connect \B \s_alu + connect \Y $or$issuer_ls180.v:25931$892_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + cell $or $or$issuer_ls180.v:25933$894 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_alu + connect \B \q_int + connect \Y $or$issuer_ls180.v:25933$894_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $or $or$issuer_ls180.v:25936$897 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$3 + connect \B \s_alu + connect \Y $or$issuer_ls180.v:25936$897_Y + end + attribute \src "issuer_ls180.v:25895.7-25895.20" + process $proc$issuer_ls180.v:25895$903 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "issuer_ls180.v:25919.7-25919.19" + process $proc$issuer_ls180.v:25919$904 + assign { } { } + assign $1\q_int[0:0] 1'0 + sync always + sync init + update \q_int $1\q_int[0:0] + end + attribute \src "issuer_ls180.v:25938.3-25939.27" + process $proc$issuer_ls180.v:25938$899 + assign { } { } + assign $0\q_int[0:0] \q_int$next + sync posedge \coresync_clk + update \q_int $0\q_int[0:0] + end + attribute \src "issuer_ls180.v:25940.3-25948.6" + process $proc$issuer_ls180.v:25940$900 + assign { } { } + assign { } { } + assign $0\q_int$next[0:0]$901 $1\q_int$next[0:0]$902 + attribute \src "issuer_ls180.v:25941.5-25941.29" + switch \initial + attribute \src "issuer_ls180.v:25941.9-25941.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\q_int$next[0:0]$902 1'0 + case + assign $1\q_int$next[0:0]$902 \$5 + end + sync always + update \q_int$next $0\q_int$next[0:0]$901 + end + connect \$9 $and$issuer_ls180.v:25930$891_Y + connect \$11 $or$issuer_ls180.v:25931$892_Y + connect \$13 $not$issuer_ls180.v:25932$893_Y + connect \$15 $or$issuer_ls180.v:25933$894_Y + connect \$1 $not$issuer_ls180.v:25934$895_Y + connect \$3 $and$issuer_ls180.v:25935$896_Y + connect \$5 $or$issuer_ls180.v:25936$897_Y + connect \$7 $not$issuer_ls180.v:25937$898_Y + connect \qlq_alu \$15 + connect \qn_alu \$13 + connect \q_alu \$11 +end +attribute \src "issuer_ls180.v:25956.1-26951.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.fus.logical0.alu_logical0" +attribute \generator "nMigen" +module \alu_logical0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" + wire input 31 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" + wire input 3 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 4 output 25 \cr_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 2 \cr_a_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 input 22 \logical_op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \logical_op__data_len$61 + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 input 7 \logical_op__fn_unit + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 \logical_op__fn_unit$46 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 input 8 \logical_op__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \logical_op__imm_data__data$47 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 9 \logical_op__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__imm_data__ok$48 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 input 16 \logical_op__input_carry + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \logical_op__input_carry$55 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 23 \logical_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \logical_op__insn$62 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 input 6 \logical_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \logical_op__insn_type$45 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 14 \logical_op__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__invert_in$53 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 17 \logical_op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__invert_out$56 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 20 \logical_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__is_32bit$59 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 21 \logical_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__is_signed$60 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 12 \logical_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__oe__oe$51 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 13 \logical_op__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__oe__ok$52 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 19 \logical_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__output_carry$58 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 11 \logical_op__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__rc__ok$50 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 10 \logical_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__rc__rc$49 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 18 \logical_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__write_cr0$57 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 15 \logical_op__zero_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__zero_a$54 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 4 \logical_pipe1_cr_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \logical_pipe1_cr_a_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \logical_pipe1_logical_op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \logical_pipe1_logical_op__data_len$18 + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 \logical_pipe1_logical_op__fn_unit + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 \logical_pipe1_logical_op__fn_unit$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \logical_pipe1_logical_op__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \logical_pipe1_logical_op__imm_data__data$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_pipe1_logical_op__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_pipe1_logical_op__imm_data__ok$5 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \logical_pipe1_logical_op__input_carry + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \logical_pipe1_logical_op__input_carry$12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \logical_pipe1_logical_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \logical_pipe1_logical_op__insn$19 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \logical_pipe1_logical_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \logical_pipe1_logical_op__insn_type$2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_pipe1_logical_op__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_pipe1_logical_op__invert_in$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_pipe1_logical_op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_pipe1_logical_op__invert_out$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_pipe1_logical_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_pipe1_logical_op__is_32bit$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_pipe1_logical_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_pipe1_logical_op__is_signed$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_pipe1_logical_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_pipe1_logical_op__oe__oe$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_pipe1_logical_op__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_pipe1_logical_op__oe__ok$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_pipe1_logical_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_pipe1_logical_op__output_carry$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_pipe1_logical_op__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_pipe1_logical_op__rc__ok$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_pipe1_logical_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_pipe1_logical_op__rc__rc$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_pipe1_logical_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_pipe1_logical_op__write_cr0$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_pipe1_logical_op__zero_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_pipe1_logical_op__zero_a$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \logical_pipe1_muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \logical_pipe1_muxid$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" + wire \logical_pipe1_n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" + wire \logical_pipe1_n_valid_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 \logical_pipe1_o + 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attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 \logical_pipe2_logical_op__fn_unit + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + 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"CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \logical_pipe2_logical_op__input_carry$32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \logical_pipe2_logical_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \logical_pipe2_logical_op__insn$39 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \logical_pipe2_logical_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \logical_pipe2_logical_op__insn_type$22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_pipe2_logical_op__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_pipe2_logical_op__invert_in$30 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_pipe2_logical_op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_pipe2_logical_op__invert_out$33 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_pipe2_logical_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_pipe2_logical_op__is_32bit$36 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_pipe2_logical_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_pipe2_logical_op__is_signed$37 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_pipe2_logical_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_pipe2_logical_op__oe__oe$28 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_pipe2_logical_op__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_pipe2_logical_op__oe__ok$29 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_pipe2_logical_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_pipe2_logical_op__output_carry$35 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_pipe2_logical_op__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_pipe2_logical_op__rc__ok$27 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_pipe2_logical_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_pipe2_logical_op__rc__rc$26 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_pipe2_logical_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_pipe2_logical_op__write_cr0$34 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_pipe2_logical_op__zero_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_pipe2_logical_op__zero_a$31 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \logical_pipe2_muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \logical_pipe2_muxid$21 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" + wire \logical_pipe2_n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" + wire \logical_pipe2_n_valid_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 \logical_pipe2_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 \logical_pipe2_o$40 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \logical_pipe2_o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \logical_pipe2_o_ok$41 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" + wire \logical_pipe2_p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" + wire \logical_pipe2_p_valid_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \logical_pipe2_xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \logical_pipe2_xer_so_ok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \muxid$44 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" + wire input 5 \n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" + wire output 4 \n_valid_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 output 24 \o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 1 \o_ok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" + wire output 30 \p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" + wire input 29 \p_valid_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 26 \ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 27 \rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire input 28 \xer_so + attribute \module_not_derived 1 + attribute \src "issuer_ls180.v:26811.17-26865.4" + cell \logical_pipe1 \logical_pipe1 + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \cr_a \logical_pipe1_cr_a + connect \cr_a_ok \logical_pipe1_cr_a_ok + connect \logical_op__data_len \logical_pipe1_logical_op__data_len + connect \logical_op__data_len$18 \logical_pipe1_logical_op__data_len$18 + connect \logical_op__fn_unit \logical_pipe1_logical_op__fn_unit + connect \logical_op__fn_unit$3 \logical_pipe1_logical_op__fn_unit$3 + connect \logical_op__imm_data__data \logical_pipe1_logical_op__imm_data__data + connect \logical_op__imm_data__data$4 \logical_pipe1_logical_op__imm_data__data$4 + connect \logical_op__imm_data__ok \logical_pipe1_logical_op__imm_data__ok + connect \logical_op__imm_data__ok$5 \logical_pipe1_logical_op__imm_data__ok$5 + connect \logical_op__input_carry \logical_pipe1_logical_op__input_carry + connect \logical_op__input_carry$12 \logical_pipe1_logical_op__input_carry$12 + connect \logical_op__insn \logical_pipe1_logical_op__insn + connect \logical_op__insn$19 \logical_pipe1_logical_op__insn$19 + connect \logical_op__insn_type \logical_pipe1_logical_op__insn_type + connect \logical_op__insn_type$2 \logical_pipe1_logical_op__insn_type$2 + connect \logical_op__invert_in \logical_pipe1_logical_op__invert_in + connect \logical_op__invert_in$10 \logical_pipe1_logical_op__invert_in$10 + connect \logical_op__invert_out \logical_pipe1_logical_op__invert_out + connect \logical_op__invert_out$13 \logical_pipe1_logical_op__invert_out$13 + connect \logical_op__is_32bit \logical_pipe1_logical_op__is_32bit + connect \logical_op__is_32bit$16 \logical_pipe1_logical_op__is_32bit$16 + connect \logical_op__is_signed \logical_pipe1_logical_op__is_signed + connect \logical_op__is_signed$17 \logical_pipe1_logical_op__is_signed$17 + connect \logical_op__oe__oe \logical_pipe1_logical_op__oe__oe + connect \logical_op__oe__oe$8 \logical_pipe1_logical_op__oe__oe$8 + connect \logical_op__oe__ok \logical_pipe1_logical_op__oe__ok + connect \logical_op__oe__ok$9 \logical_pipe1_logical_op__oe__ok$9 + connect \logical_op__output_carry \logical_pipe1_logical_op__output_carry + connect \logical_op__output_carry$15 \logical_pipe1_logical_op__output_carry$15 + connect \logical_op__rc__ok \logical_pipe1_logical_op__rc__ok + connect \logical_op__rc__ok$7 \logical_pipe1_logical_op__rc__ok$7 + connect \logical_op__rc__rc \logical_pipe1_logical_op__rc__rc + connect \logical_op__rc__rc$6 \logical_pipe1_logical_op__rc__rc$6 + connect \logical_op__write_cr0 \logical_pipe1_logical_op__write_cr0 + connect \logical_op__write_cr0$14 \logical_pipe1_logical_op__write_cr0$14 + connect \logical_op__zero_a \logical_pipe1_logical_op__zero_a + connect \logical_op__zero_a$11 \logical_pipe1_logical_op__zero_a$11 + connect \muxid \logical_pipe1_muxid + connect \muxid$1 \logical_pipe1_muxid$1 + connect \n_ready_i \logical_pipe1_n_ready_i + connect \n_valid_o \logical_pipe1_n_valid_o + connect \o \logical_pipe1_o + connect \o_ok \logical_pipe1_o_ok + connect \p_ready_o \logical_pipe1_p_ready_o + connect \p_valid_i \logical_pipe1_p_valid_i + connect \ra \logical_pipe1_ra + connect \rb \logical_pipe1_rb + connect \xer_so \logical_pipe1_xer_so + connect \xer_so$20 \logical_pipe1_xer_so$20 + connect \xer_so_ok \logical_pipe1_xer_so_ok + end + attribute \module_not_derived 1 + attribute \src "issuer_ls180.v:26866.17-26921.4" + cell \logical_pipe2 \logical_pipe2 + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \cr_a \logical_pipe2_cr_a + connect \cr_a$22 \logical_pipe2_cr_a$42 + connect \cr_a_ok \logical_pipe2_cr_a_ok + connect \cr_a_ok$23 \logical_pipe2_cr_a_ok$43 + connect \logical_op__data_len \logical_pipe2_logical_op__data_len + connect \logical_op__data_len$18 \logical_pipe2_logical_op__data_len$38 + connect \logical_op__fn_unit \logical_pipe2_logical_op__fn_unit + connect \logical_op__fn_unit$3 \logical_pipe2_logical_op__fn_unit$23 + connect \logical_op__imm_data__data \logical_pipe2_logical_op__imm_data__data + connect \logical_op__imm_data__data$4 \logical_pipe2_logical_op__imm_data__data$24 + connect \logical_op__imm_data__ok \logical_pipe2_logical_op__imm_data__ok + connect \logical_op__imm_data__ok$5 \logical_pipe2_logical_op__imm_data__ok$25 + connect \logical_op__input_carry \logical_pipe2_logical_op__input_carry + connect \logical_op__input_carry$12 \logical_pipe2_logical_op__input_carry$32 + connect \logical_op__insn \logical_pipe2_logical_op__insn + connect \logical_op__insn$19 \logical_pipe2_logical_op__insn$39 + connect \logical_op__insn_type \logical_pipe2_logical_op__insn_type + connect \logical_op__insn_type$2 \logical_pipe2_logical_op__insn_type$22 + connect \logical_op__invert_in \logical_pipe2_logical_op__invert_in + connect \logical_op__invert_in$10 \logical_pipe2_logical_op__invert_in$30 + connect \logical_op__invert_out \logical_pipe2_logical_op__invert_out + connect \logical_op__invert_out$13 \logical_pipe2_logical_op__invert_out$33 + connect \logical_op__is_32bit \logical_pipe2_logical_op__is_32bit + connect \logical_op__is_32bit$16 \logical_pipe2_logical_op__is_32bit$36 + connect \logical_op__is_signed \logical_pipe2_logical_op__is_signed + connect \logical_op__is_signed$17 \logical_pipe2_logical_op__is_signed$37 + connect \logical_op__oe__oe \logical_pipe2_logical_op__oe__oe + connect \logical_op__oe__oe$8 \logical_pipe2_logical_op__oe__oe$28 + connect \logical_op__oe__ok \logical_pipe2_logical_op__oe__ok + connect \logical_op__oe__ok$9 \logical_pipe2_logical_op__oe__ok$29 + connect \logical_op__output_carry \logical_pipe2_logical_op__output_carry + connect \logical_op__output_carry$15 \logical_pipe2_logical_op__output_carry$35 + connect \logical_op__rc__ok \logical_pipe2_logical_op__rc__ok + connect \logical_op__rc__ok$7 \logical_pipe2_logical_op__rc__ok$27 + connect \logical_op__rc__rc \logical_pipe2_logical_op__rc__rc + connect \logical_op__rc__rc$6 \logical_pipe2_logical_op__rc__rc$26 + connect \logical_op__write_cr0 \logical_pipe2_logical_op__write_cr0 + connect \logical_op__write_cr0$14 \logical_pipe2_logical_op__write_cr0$34 + connect \logical_op__zero_a \logical_pipe2_logical_op__zero_a + connect \logical_op__zero_a$11 \logical_pipe2_logical_op__zero_a$31 + connect \muxid \logical_pipe2_muxid + connect \muxid$1 \logical_pipe2_muxid$21 + connect \n_ready_i \logical_pipe2_n_ready_i + connect \n_valid_o \logical_pipe2_n_valid_o + connect \o \logical_pipe2_o + connect \o$20 \logical_pipe2_o$40 + connect \o_ok \logical_pipe2_o_ok + connect \o_ok$21 \logical_pipe2_o_ok$41 + connect \p_ready_o \logical_pipe2_p_ready_o + connect \p_valid_i \logical_pipe2_p_valid_i + connect \xer_so \logical_pipe2_xer_so + connect \xer_so_ok \logical_pipe2_xer_so_ok + end + attribute \module_not_derived 1 + attribute \src "issuer_ls180.v:26922.10-26925.4" + cell \n$44 \n + connect \n_ready_i \n_ready_i + connect \n_valid_o \n_valid_o + end + attribute \module_not_derived 1 + attribute \src "issuer_ls180.v:26926.10-26929.4" + cell \p$43 \p + connect \p_ready_o \p_ready_o + connect \p_valid_i \p_valid_i + end + connect \muxid 2'00 + connect { \cr_a_ok \cr_a } { \logical_pipe2_cr_a_ok$43 \logical_pipe2_cr_a$42 } + connect { \o_ok \o } { \logical_pipe2_o_ok$41 \logical_pipe2_o$40 } + connect { \logical_op__insn$62 \logical_op__data_len$61 \logical_op__is_signed$60 \logical_op__is_32bit$59 \logical_op__output_carry$58 \logical_op__write_cr0$57 \logical_op__invert_out$56 \logical_op__input_carry$55 \logical_op__zero_a$54 \logical_op__invert_in$53 \logical_op__oe__ok$52 \logical_op__oe__oe$51 \logical_op__rc__ok$50 \logical_op__rc__rc$49 \logical_op__imm_data__ok$48 \logical_op__imm_data__data$47 \logical_op__fn_unit$46 \logical_op__insn_type$45 } { \logical_pipe2_logical_op__insn$39 \logical_pipe2_logical_op__data_len$38 \logical_pipe2_logical_op__is_signed$37 \logical_pipe2_logical_op__is_32bit$36 \logical_pipe2_logical_op__output_carry$35 \logical_pipe2_logical_op__write_cr0$34 \logical_pipe2_logical_op__invert_out$33 \logical_pipe2_logical_op__input_carry$32 \logical_pipe2_logical_op__zero_a$31 \logical_pipe2_logical_op__invert_in$30 \logical_pipe2_logical_op__oe__ok$29 \logical_pipe2_logical_op__oe__oe$28 \logical_pipe2_logical_op__rc__ok$27 \logical_pipe2_logical_op__rc__rc$26 \logical_pipe2_logical_op__imm_data__ok$25 \logical_pipe2_logical_op__imm_data__data$24 \logical_pipe2_logical_op__fn_unit$23 \logical_pipe2_logical_op__insn_type$22 } + connect \muxid$44 \logical_pipe2_muxid$21 + connect \logical_pipe2_n_ready_i \n_ready_i + connect \n_valid_o \logical_pipe2_n_valid_o + connect \logical_pipe1_xer_so$20 \xer_so + connect \logical_pipe1_rb \rb + connect \logical_pipe1_ra \ra + connect { \logical_pipe1_logical_op__insn$19 \logical_pipe1_logical_op__data_len$18 \logical_pipe1_logical_op__is_signed$17 \logical_pipe1_logical_op__is_32bit$16 \logical_pipe1_logical_op__output_carry$15 \logical_pipe1_logical_op__write_cr0$14 \logical_pipe1_logical_op__invert_out$13 \logical_pipe1_logical_op__input_carry$12 \logical_pipe1_logical_op__zero_a$11 \logical_pipe1_logical_op__invert_in$10 \logical_pipe1_logical_op__oe__ok$9 \logical_pipe1_logical_op__oe__oe$8 \logical_pipe1_logical_op__rc__ok$7 \logical_pipe1_logical_op__rc__rc$6 \logical_pipe1_logical_op__imm_data__ok$5 \logical_pipe1_logical_op__imm_data__data$4 \logical_pipe1_logical_op__fn_unit$3 \logical_pipe1_logical_op__insn_type$2 } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in \logical_op__oe__ok \logical_op__oe__oe \logical_op__rc__ok \logical_op__rc__rc \logical_op__imm_data__ok \logical_op__imm_data__data \logical_op__fn_unit \logical_op__insn_type } + connect \logical_pipe1_muxid$1 2'00 + connect \p_ready_o \logical_pipe1_p_ready_o + connect \logical_pipe1_p_valid_i \p_valid_i + connect { \logical_pipe2_xer_so_ok \logical_pipe2_xer_so } { \logical_pipe1_xer_so_ok \logical_pipe1_xer_so } + connect { \logical_pipe2_cr_a_ok \logical_pipe2_cr_a } { \logical_pipe1_cr_a_ok \logical_pipe1_cr_a } + connect { \logical_pipe2_o_ok \logical_pipe2_o } { \logical_pipe1_o_ok \logical_pipe1_o } + connect { \logical_pipe2_logical_op__insn \logical_pipe2_logical_op__data_len \logical_pipe2_logical_op__is_signed \logical_pipe2_logical_op__is_32bit \logical_pipe2_logical_op__output_carry \logical_pipe2_logical_op__write_cr0 \logical_pipe2_logical_op__invert_out \logical_pipe2_logical_op__input_carry \logical_pipe2_logical_op__zero_a \logical_pipe2_logical_op__invert_in \logical_pipe2_logical_op__oe__ok \logical_pipe2_logical_op__oe__oe \logical_pipe2_logical_op__rc__ok \logical_pipe2_logical_op__rc__rc \logical_pipe2_logical_op__imm_data__ok \logical_pipe2_logical_op__imm_data__data \logical_pipe2_logical_op__fn_unit \logical_pipe2_logical_op__insn_type } { \logical_pipe1_logical_op__insn \logical_pipe1_logical_op__data_len \logical_pipe1_logical_op__is_signed \logical_pipe1_logical_op__is_32bit \logical_pipe1_logical_op__output_carry \logical_pipe1_logical_op__write_cr0 \logical_pipe1_logical_op__invert_out \logical_pipe1_logical_op__input_carry \logical_pipe1_logical_op__zero_a \logical_pipe1_logical_op__invert_in \logical_pipe1_logical_op__oe__ok \logical_pipe1_logical_op__oe__oe \logical_pipe1_logical_op__rc__ok \logical_pipe1_logical_op__rc__rc \logical_pipe1_logical_op__imm_data__ok \logical_pipe1_logical_op__imm_data__data \logical_pipe1_logical_op__fn_unit \logical_pipe1_logical_op__insn_type } + connect \logical_pipe2_muxid \logical_pipe1_muxid + connect \logical_pipe1_n_ready_i \logical_pipe2_p_ready_o + connect \logical_pipe2_p_valid_i \logical_pipe1_n_valid_o +end +attribute \src "issuer_ls180.v:26955.1-28148.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.fus.mul0.alu_mul0" +attribute \generator "nMigen" +module \alu_mul0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" + wire input 29 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" + wire input 5 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 4 output 21 \cr_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 2 \cr_a_ok + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 input 9 \mul_op__fn_unit + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 \mul_op__fn_unit$51 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 input 10 \mul_op__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \mul_op__imm_data__data$52 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 11 \mul_op__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_op__imm_data__ok$53 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 19 \mul_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \mul_op__insn$61 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 input 8 \mul_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \mul_op__insn_type$50 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 17 \mul_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_op__is_32bit$59 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 18 \mul_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_op__is_signed$60 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 14 \mul_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_op__oe__oe$56 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 15 \mul_op__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_op__oe__ok$57 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 13 \mul_op__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_op__rc__ok$55 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 12 \mul_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_op__rc__rc$54 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 16 \mul_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_op__write_cr0$58 + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 \mul_pipe1_mul_op__fn_unit + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 \mul_pipe1_mul_op__fn_unit$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \mul_pipe1_mul_op__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \mul_pipe1_mul_op__imm_data__data$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_pipe1_mul_op__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_pipe1_mul_op__imm_data__ok$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \mul_pipe1_mul_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \mul_pipe1_mul_op__insn$14 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \mul_pipe1_mul_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \mul_pipe1_mul_op__insn_type$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_pipe1_mul_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_pipe1_mul_op__is_32bit$12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_pipe1_mul_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_pipe1_mul_op__is_signed$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_pipe1_mul_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_pipe1_mul_op__oe__oe$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_pipe1_mul_op__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_pipe1_mul_op__oe__ok$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_pipe1_mul_op__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_pipe1_mul_op__rc__ok$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_pipe1_mul_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_pipe1_mul_op__rc__rc$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_pipe1_mul_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_pipe1_mul_op__write_cr0$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \mul_pipe1_muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \mul_pipe1_muxid$2 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" + wire \mul_pipe1_n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" + wire \mul_pipe1_n_valid_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:11" + wire \mul_pipe1_neg_res + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:12" + wire \mul_pipe1_neg_res32 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" + wire \mul_pipe1_p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" + wire \mul_pipe1_p_valid_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \mul_pipe1_ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \mul_pipe1_ra$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \mul_pipe1_rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \mul_pipe1_rb$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire \mul_pipe1_xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire \mul_pipe1_xer_so$17 + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 \mul_pipe2_mul_op__fn_unit + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 \mul_pipe2_mul_op__fn_unit$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \mul_pipe2_mul_op__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \mul_pipe2_mul_op__imm_data__data$21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_pipe2_mul_op__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_pipe2_mul_op__imm_data__ok$22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \mul_pipe2_mul_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \mul_pipe2_mul_op__insn$30 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \mul_pipe2_mul_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \mul_pipe2_mul_op__insn_type$19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_pipe2_mul_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_pipe2_mul_op__is_32bit$28 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_pipe2_mul_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_pipe2_mul_op__is_signed$29 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_pipe2_mul_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_pipe2_mul_op__oe__oe$25 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_pipe2_mul_op__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_pipe2_mul_op__oe__ok$26 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_pipe2_mul_op__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_pipe2_mul_op__rc__ok$24 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_pipe2_mul_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_pipe2_mul_op__rc__rc$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_pipe2_mul_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_pipe2_mul_op__write_cr0$27 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \mul_pipe2_muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \mul_pipe2_muxid$18 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" + wire \mul_pipe2_n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" + wire \mul_pipe2_n_valid_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:11" + wire \mul_pipe2_neg_res + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:23" + wire \mul_pipe2_neg_res$32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:12" + wire \mul_pipe2_neg_res32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:24" + wire \mul_pipe2_neg_res32$33 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 129 \mul_pipe2_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" + wire \mul_pipe2_p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" + wire \mul_pipe2_p_valid_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \mul_pipe2_ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \mul_pipe2_rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire \mul_pipe2_xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire \mul_pipe2_xer_so$31 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 4 \mul_pipe3_cr_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \mul_pipe3_cr_a_ok + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 \mul_pipe3_mul_op__fn_unit + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 \mul_pipe3_mul_op__fn_unit$36 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \mul_pipe3_mul_op__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \mul_pipe3_mul_op__imm_data__data$37 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_pipe3_mul_op__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_pipe3_mul_op__imm_data__ok$38 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \mul_pipe3_mul_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \mul_pipe3_mul_op__insn$46 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \mul_pipe3_mul_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \mul_pipe3_mul_op__insn_type$35 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_pipe3_mul_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_pipe3_mul_op__is_32bit$44 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_pipe3_mul_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_pipe3_mul_op__is_signed$45 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_pipe3_mul_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_pipe3_mul_op__oe__oe$41 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_pipe3_mul_op__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_pipe3_mul_op__oe__ok$42 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_pipe3_mul_op__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_pipe3_mul_op__rc__ok$40 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_pipe3_mul_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_pipe3_mul_op__rc__rc$39 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_pipe3_mul_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_pipe3_mul_op__write_cr0$43 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \mul_pipe3_muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \mul_pipe3_muxid$34 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" + wire \mul_pipe3_n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" + wire \mul_pipe3_n_valid_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:23" + wire \mul_pipe3_neg_res + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:24" + wire \mul_pipe3_neg_res32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 129 \mul_pipe3_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 \mul_pipe3_o$47 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \mul_pipe3_o_ok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" + wire \mul_pipe3_p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" + wire \mul_pipe3_p_valid_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 2 \mul_pipe3_xer_ov + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \mul_pipe3_xer_ov_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire \mul_pipe3_xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \mul_pipe3_xer_so$48 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \mul_pipe3_xer_so_ok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \muxid$49 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" + wire input 7 \n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" + wire output 6 \n_valid_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 output 20 \o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 1 \o_ok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" + wire output 28 \p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" + wire input 27 \p_valid_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 24 \ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 25 \rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 2 output 22 \xer_ov + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 3 \xer_ov_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 23 \xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire input 26 \xer_so$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 4 \xer_so_ok + attribute \module_not_derived 1 + attribute \src "issuer_ls180.v:27976.13-28017.4" + cell \mul_pipe1 \mul_pipe1 + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \mul_op__fn_unit \mul_pipe1_mul_op__fn_unit + connect \mul_op__fn_unit$3 \mul_pipe1_mul_op__fn_unit$4 + connect \mul_op__imm_data__data \mul_pipe1_mul_op__imm_data__data + connect \mul_op__imm_data__data$4 \mul_pipe1_mul_op__imm_data__data$5 + connect \mul_op__imm_data__ok \mul_pipe1_mul_op__imm_data__ok + connect \mul_op__imm_data__ok$5 \mul_pipe1_mul_op__imm_data__ok$6 + connect \mul_op__insn \mul_pipe1_mul_op__insn + connect \mul_op__insn$13 \mul_pipe1_mul_op__insn$14 + connect \mul_op__insn_type \mul_pipe1_mul_op__insn_type + connect \mul_op__insn_type$2 \mul_pipe1_mul_op__insn_type$3 + connect \mul_op__is_32bit \mul_pipe1_mul_op__is_32bit + connect \mul_op__is_32bit$11 \mul_pipe1_mul_op__is_32bit$12 + connect \mul_op__is_signed \mul_pipe1_mul_op__is_signed + connect \mul_op__is_signed$12 \mul_pipe1_mul_op__is_signed$13 + connect \mul_op__oe__oe \mul_pipe1_mul_op__oe__oe + connect \mul_op__oe__oe$8 \mul_pipe1_mul_op__oe__oe$9 + connect \mul_op__oe__ok \mul_pipe1_mul_op__oe__ok + connect \mul_op__oe__ok$9 \mul_pipe1_mul_op__oe__ok$10 + connect \mul_op__rc__ok \mul_pipe1_mul_op__rc__ok + connect \mul_op__rc__ok$7 \mul_pipe1_mul_op__rc__ok$8 + connect \mul_op__rc__rc \mul_pipe1_mul_op__rc__rc + connect \mul_op__rc__rc$6 \mul_pipe1_mul_op__rc__rc$7 + connect \mul_op__write_cr0 \mul_pipe1_mul_op__write_cr0 + connect \mul_op__write_cr0$10 \mul_pipe1_mul_op__write_cr0$11 + connect \muxid \mul_pipe1_muxid + connect \muxid$1 \mul_pipe1_muxid$2 + connect \n_ready_i \mul_pipe1_n_ready_i + connect \n_valid_o \mul_pipe1_n_valid_o + connect \neg_res \mul_pipe1_neg_res + connect \neg_res32 \mul_pipe1_neg_res32 + connect \p_ready_o \mul_pipe1_p_ready_o + connect \p_valid_i \mul_pipe1_p_valid_i + connect \ra \mul_pipe1_ra + connect \ra$14 \mul_pipe1_ra$15 + connect \rb \mul_pipe1_rb + connect \rb$15 \mul_pipe1_rb$16 + connect \xer_so \mul_pipe1_xer_so + connect \xer_so$16 \mul_pipe1_xer_so$17 + end + attribute \module_not_derived 1 + attribute \src "issuer_ls180.v:28018.13-28060.4" + cell \mul_pipe2 \mul_pipe2 + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \mul_op__fn_unit \mul_pipe2_mul_op__fn_unit + connect \mul_op__fn_unit$3 \mul_pipe2_mul_op__fn_unit$20 + connect \mul_op__imm_data__data \mul_pipe2_mul_op__imm_data__data + connect \mul_op__imm_data__data$4 \mul_pipe2_mul_op__imm_data__data$21 + connect \mul_op__imm_data__ok \mul_pipe2_mul_op__imm_data__ok + connect \mul_op__imm_data__ok$5 \mul_pipe2_mul_op__imm_data__ok$22 + connect \mul_op__insn \mul_pipe2_mul_op__insn + connect \mul_op__insn$13 \mul_pipe2_mul_op__insn$30 + connect \mul_op__insn_type \mul_pipe2_mul_op__insn_type + connect \mul_op__insn_type$2 \mul_pipe2_mul_op__insn_type$19 + connect \mul_op__is_32bit \mul_pipe2_mul_op__is_32bit + connect \mul_op__is_32bit$11 \mul_pipe2_mul_op__is_32bit$28 + connect \mul_op__is_signed \mul_pipe2_mul_op__is_signed + connect \mul_op__is_signed$12 \mul_pipe2_mul_op__is_signed$29 + connect \mul_op__oe__oe \mul_pipe2_mul_op__oe__oe + connect \mul_op__oe__oe$8 \mul_pipe2_mul_op__oe__oe$25 + connect \mul_op__oe__ok \mul_pipe2_mul_op__oe__ok + connect \mul_op__oe__ok$9 \mul_pipe2_mul_op__oe__ok$26 + connect \mul_op__rc__ok \mul_pipe2_mul_op__rc__ok + connect \mul_op__rc__ok$7 \mul_pipe2_mul_op__rc__ok$24 + connect \mul_op__rc__rc \mul_pipe2_mul_op__rc__rc + connect \mul_op__rc__rc$6 \mul_pipe2_mul_op__rc__rc$23 + connect \mul_op__write_cr0 \mul_pipe2_mul_op__write_cr0 + connect \mul_op__write_cr0$10 \mul_pipe2_mul_op__write_cr0$27 + connect \muxid \mul_pipe2_muxid + connect \muxid$1 \mul_pipe2_muxid$18 + connect \n_ready_i \mul_pipe2_n_ready_i + connect \n_valid_o \mul_pipe2_n_valid_o + connect \neg_res \mul_pipe2_neg_res + connect \neg_res$15 \mul_pipe2_neg_res$32 + connect \neg_res32 \mul_pipe2_neg_res32 + connect \neg_res32$16 \mul_pipe2_neg_res32$33 + connect \o \mul_pipe2_o + connect \p_ready_o \mul_pipe2_p_ready_o + connect \p_valid_i \mul_pipe2_p_valid_i + connect \ra \mul_pipe2_ra + connect \rb \mul_pipe2_rb + connect \xer_so \mul_pipe2_xer_so + connect \xer_so$14 \mul_pipe2_xer_so$31 + end + attribute \module_not_derived 1 + attribute \src "issuer_ls180.v:28061.13-28106.4" + cell \mul_pipe3 \mul_pipe3 + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \cr_a \mul_pipe3_cr_a + connect \cr_a_ok \mul_pipe3_cr_a_ok + connect \mul_op__fn_unit \mul_pipe3_mul_op__fn_unit + connect \mul_op__fn_unit$3 \mul_pipe3_mul_op__fn_unit$36 + connect \mul_op__imm_data__data \mul_pipe3_mul_op__imm_data__data + connect \mul_op__imm_data__data$4 \mul_pipe3_mul_op__imm_data__data$37 + connect \mul_op__imm_data__ok \mul_pipe3_mul_op__imm_data__ok + connect \mul_op__imm_data__ok$5 \mul_pipe3_mul_op__imm_data__ok$38 + connect \mul_op__insn \mul_pipe3_mul_op__insn + connect \mul_op__insn$13 \mul_pipe3_mul_op__insn$46 + connect \mul_op__insn_type \mul_pipe3_mul_op__insn_type + connect \mul_op__insn_type$2 \mul_pipe3_mul_op__insn_type$35 + connect \mul_op__is_32bit \mul_pipe3_mul_op__is_32bit + connect \mul_op__is_32bit$11 \mul_pipe3_mul_op__is_32bit$44 + connect \mul_op__is_signed \mul_pipe3_mul_op__is_signed + connect \mul_op__is_signed$12 \mul_pipe3_mul_op__is_signed$45 + connect \mul_op__oe__oe \mul_pipe3_mul_op__oe__oe + connect \mul_op__oe__oe$8 \mul_pipe3_mul_op__oe__oe$41 + connect \mul_op__oe__ok \mul_pipe3_mul_op__oe__ok + connect \mul_op__oe__ok$9 \mul_pipe3_mul_op__oe__ok$42 + connect \mul_op__rc__ok \mul_pipe3_mul_op__rc__ok + connect \mul_op__rc__ok$7 \mul_pipe3_mul_op__rc__ok$40 + connect \mul_op__rc__rc \mul_pipe3_mul_op__rc__rc + connect \mul_op__rc__rc$6 \mul_pipe3_mul_op__rc__rc$39 + connect \mul_op__write_cr0 \mul_pipe3_mul_op__write_cr0 + connect \mul_op__write_cr0$10 \mul_pipe3_mul_op__write_cr0$43 + connect \muxid \mul_pipe3_muxid + connect \muxid$1 \mul_pipe3_muxid$34 + connect \n_ready_i \mul_pipe3_n_ready_i + connect \n_valid_o \mul_pipe3_n_valid_o + connect \neg_res \mul_pipe3_neg_res + connect \neg_res32 \mul_pipe3_neg_res32 + connect \o \mul_pipe3_o + connect \o$14 \mul_pipe3_o$47 + connect \o_ok \mul_pipe3_o_ok + connect \p_ready_o \mul_pipe3_p_ready_o + connect \p_valid_i \mul_pipe3_p_valid_i + connect \xer_ov \mul_pipe3_xer_ov + connect \xer_ov_ok \mul_pipe3_xer_ov_ok + connect \xer_so \mul_pipe3_xer_so + connect \xer_so$15 \mul_pipe3_xer_so$48 + connect \xer_so_ok \mul_pipe3_xer_so_ok + end + attribute \module_not_derived 1 + attribute \src "issuer_ls180.v:28107.10-28110.4" + cell \n$89 \n + connect \n_ready_i \n_ready_i + connect \n_valid_o \n_valid_o + end + attribute \module_not_derived 1 + attribute \src "issuer_ls180.v:28111.10-28114.4" + cell \p$88 \p + connect \p_ready_o \p_ready_o + connect \p_valid_i \p_valid_i + end + connect \muxid 2'00 + connect { \xer_so_ok \xer_so } { \mul_pipe3_xer_so_ok \mul_pipe3_xer_so$48 } + connect { \xer_ov_ok \xer_ov } { \mul_pipe3_xer_ov_ok \mul_pipe3_xer_ov } + connect { \cr_a_ok \cr_a } { \mul_pipe3_cr_a_ok \mul_pipe3_cr_a } + connect { \o_ok \o } { \mul_pipe3_o_ok \mul_pipe3_o$47 } + connect { \mul_op__insn$61 \mul_op__is_signed$60 \mul_op__is_32bit$59 \mul_op__write_cr0$58 \mul_op__oe__ok$57 \mul_op__oe__oe$56 \mul_op__rc__ok$55 \mul_op__rc__rc$54 \mul_op__imm_data__ok$53 \mul_op__imm_data__data$52 \mul_op__fn_unit$51 \mul_op__insn_type$50 } { \mul_pipe3_mul_op__insn$46 \mul_pipe3_mul_op__is_signed$45 \mul_pipe3_mul_op__is_32bit$44 \mul_pipe3_mul_op__write_cr0$43 \mul_pipe3_mul_op__oe__ok$42 \mul_pipe3_mul_op__oe__oe$41 \mul_pipe3_mul_op__rc__ok$40 \mul_pipe3_mul_op__rc__rc$39 \mul_pipe3_mul_op__imm_data__ok$38 \mul_pipe3_mul_op__imm_data__data$37 \mul_pipe3_mul_op__fn_unit$36 \mul_pipe3_mul_op__insn_type$35 } + connect \muxid$49 \mul_pipe3_muxid$34 + connect \mul_pipe3_n_ready_i \n_ready_i + connect \n_valid_o \mul_pipe3_n_valid_o + connect \mul_pipe1_xer_so$17 \xer_so$1 + connect \mul_pipe1_rb$16 \rb + connect \mul_pipe1_ra$15 \ra + connect { \mul_pipe1_mul_op__insn$14 \mul_pipe1_mul_op__is_signed$13 \mul_pipe1_mul_op__is_32bit$12 \mul_pipe1_mul_op__write_cr0$11 \mul_pipe1_mul_op__oe__ok$10 \mul_pipe1_mul_op__oe__oe$9 \mul_pipe1_mul_op__rc__ok$8 \mul_pipe1_mul_op__rc__rc$7 \mul_pipe1_mul_op__imm_data__ok$6 \mul_pipe1_mul_op__imm_data__data$5 \mul_pipe1_mul_op__fn_unit$4 \mul_pipe1_mul_op__insn_type$3 } { \mul_op__insn \mul_op__is_signed \mul_op__is_32bit \mul_op__write_cr0 \mul_op__oe__ok \mul_op__oe__oe \mul_op__rc__ok \mul_op__rc__rc \mul_op__imm_data__ok \mul_op__imm_data__data \mul_op__fn_unit \mul_op__insn_type } + connect \mul_pipe1_muxid$2 2'00 + connect \p_ready_o \mul_pipe1_p_ready_o + connect \mul_pipe1_p_valid_i \p_valid_i + connect \mul_pipe3_neg_res32 \mul_pipe2_neg_res32$33 + connect \mul_pipe3_neg_res \mul_pipe2_neg_res$32 + connect \mul_pipe3_xer_so \mul_pipe2_xer_so$31 + connect \mul_pipe3_o \mul_pipe2_o + connect { \mul_pipe3_mul_op__insn \mul_pipe3_mul_op__is_signed \mul_pipe3_mul_op__is_32bit \mul_pipe3_mul_op__write_cr0 \mul_pipe3_mul_op__oe__ok \mul_pipe3_mul_op__oe__oe \mul_pipe3_mul_op__rc__ok \mul_pipe3_mul_op__rc__rc \mul_pipe3_mul_op__imm_data__ok \mul_pipe3_mul_op__imm_data__data \mul_pipe3_mul_op__fn_unit \mul_pipe3_mul_op__insn_type } { \mul_pipe2_mul_op__insn$30 \mul_pipe2_mul_op__is_signed$29 \mul_pipe2_mul_op__is_32bit$28 \mul_pipe2_mul_op__write_cr0$27 \mul_pipe2_mul_op__oe__ok$26 \mul_pipe2_mul_op__oe__oe$25 \mul_pipe2_mul_op__rc__ok$24 \mul_pipe2_mul_op__rc__rc$23 \mul_pipe2_mul_op__imm_data__ok$22 \mul_pipe2_mul_op__imm_data__data$21 \mul_pipe2_mul_op__fn_unit$20 \mul_pipe2_mul_op__insn_type$19 } + connect \mul_pipe3_muxid \mul_pipe2_muxid$18 + connect \mul_pipe2_n_ready_i \mul_pipe3_p_ready_o + connect \mul_pipe3_p_valid_i \mul_pipe2_n_valid_o + connect \mul_pipe2_neg_res32 \mul_pipe1_neg_res32 + connect \mul_pipe2_neg_res \mul_pipe1_neg_res + connect \mul_pipe2_xer_so \mul_pipe1_xer_so + connect \mul_pipe2_rb \mul_pipe1_rb + connect \mul_pipe2_ra \mul_pipe1_ra + connect { \mul_pipe2_mul_op__insn \mul_pipe2_mul_op__is_signed \mul_pipe2_mul_op__is_32bit \mul_pipe2_mul_op__write_cr0 \mul_pipe2_mul_op__oe__ok \mul_pipe2_mul_op__oe__oe \mul_pipe2_mul_op__rc__ok \mul_pipe2_mul_op__rc__rc \mul_pipe2_mul_op__imm_data__ok \mul_pipe2_mul_op__imm_data__data \mul_pipe2_mul_op__fn_unit \mul_pipe2_mul_op__insn_type } { \mul_pipe1_mul_op__insn \mul_pipe1_mul_op__is_signed \mul_pipe1_mul_op__is_32bit \mul_pipe1_mul_op__write_cr0 \mul_pipe1_mul_op__oe__ok \mul_pipe1_mul_op__oe__oe \mul_pipe1_mul_op__rc__ok \mul_pipe1_mul_op__rc__rc \mul_pipe1_mul_op__imm_data__ok \mul_pipe1_mul_op__imm_data__data \mul_pipe1_mul_op__fn_unit \mul_pipe1_mul_op__insn_type } + connect \mul_pipe2_muxid \mul_pipe1_muxid + connect \mul_pipe1_n_ready_i \mul_pipe2_p_ready_o + connect \mul_pipe2_p_valid_i \mul_pipe1_n_valid_o +end +attribute \src "issuer_ls180.v:28152.1-29151.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.fus.shiftrot0.alu_shift_rot0" +attribute \generator "nMigen" +module \alu_shift_rot0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" + wire input 33 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" + wire input 4 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 4 output 24 \cr_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 2 \cr_a_ok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \muxid$44 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" + wire input 6 \n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" + wire output 5 \n_valid_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 output 23 \o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 1 \o_ok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" + wire output 32 \p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" + wire input 31 \p_valid_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 4 \pipe1_cr_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \pipe1_cr_a_ok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \pipe1_muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \pipe1_muxid$2 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" + wire \pipe1_n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" + wire \pipe1_n_valid_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 \pipe1_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \pipe1_o_ok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" + wire \pipe1_p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" + wire \pipe1_p_valid_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \pipe1_ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \pipe1_rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \pipe1_rc + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 \pipe1_sr_op__fn_unit + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 \pipe1_sr_op__fn_unit$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \pipe1_sr_op__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \pipe1_sr_op__imm_data__data$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe1_sr_op__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe1_sr_op__imm_data__ok$6 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \pipe1_sr_op__input_carry + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \pipe1_sr_op__input_carry$12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe1_sr_op__input_cr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe1_sr_op__input_cr$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \pipe1_sr_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \pipe1_sr_op__insn$18 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \pipe1_sr_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \pipe1_sr_op__insn_type$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe1_sr_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe1_sr_op__is_32bit$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe1_sr_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe1_sr_op__is_signed$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe1_sr_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe1_sr_op__oe__oe$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe1_sr_op__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe1_sr_op__oe__ok$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe1_sr_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe1_sr_op__output_carry$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe1_sr_op__output_cr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe1_sr_op__output_cr$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe1_sr_op__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe1_sr_op__rc__ok$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe1_sr_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe1_sr_op__rc__rc$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe1_sr_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe1_sr_op__write_cr0$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 2 \pipe1_xer_ca + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 2 \pipe1_xer_ca$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \pipe1_xer_ca_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \pipe1_xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire \pipe1_xer_so$19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \pipe1_xer_so_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 4 \pipe2_cr_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 4 \pipe2_cr_a$40 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \pipe2_cr_a_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \pipe2_cr_a_ok$41 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \pipe2_muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \pipe2_muxid$21 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" + wire \pipe2_n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" + wire \pipe2_n_valid_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 \pipe2_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 \pipe2_o$38 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \pipe2_o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \pipe2_o_ok$39 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" + wire \pipe2_p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" + wire \pipe2_p_valid_i + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 \pipe2_sr_op__fn_unit + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 \pipe2_sr_op__fn_unit$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \pipe2_sr_op__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \pipe2_sr_op__imm_data__data$24 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe2_sr_op__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe2_sr_op__imm_data__ok$25 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \pipe2_sr_op__input_carry + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \pipe2_sr_op__input_carry$31 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe2_sr_op__input_cr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe2_sr_op__input_cr$33 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \pipe2_sr_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \pipe2_sr_op__insn$37 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \pipe2_sr_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \pipe2_sr_op__insn_type$22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe2_sr_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe2_sr_op__is_32bit$35 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe2_sr_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe2_sr_op__is_signed$36 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe2_sr_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe2_sr_op__oe__oe$28 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe2_sr_op__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe2_sr_op__oe__ok$29 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe2_sr_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe2_sr_op__output_carry$32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe2_sr_op__output_cr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe2_sr_op__output_cr$34 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe2_sr_op__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe2_sr_op__rc__ok$27 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe2_sr_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe2_sr_op__rc__rc$26 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe2_sr_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe2_sr_op__write_cr0$30 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 2 \pipe2_xer_ca + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 2 \pipe2_xer_ca$42 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \pipe2_xer_ca_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \pipe2_xer_ca_ok$43 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \pipe2_xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \pipe2_xer_so_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 26 \ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 27 \rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 28 \rc + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 input 8 \sr_op__fn_unit + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 \sr_op__fn_unit$46 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 input 9 \sr_op__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \sr_op__imm_data__data$47 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 10 \sr_op__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \sr_op__imm_data__ok$48 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 input 16 \sr_op__input_carry + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \sr_op__input_carry$54 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 18 \sr_op__input_cr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \sr_op__input_cr$56 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 22 \sr_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \sr_op__insn$60 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 input 7 \sr_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \sr_op__insn_type$45 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 20 \sr_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \sr_op__is_32bit$58 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 21 \sr_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \sr_op__is_signed$59 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 13 \sr_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \sr_op__oe__oe$51 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 14 \sr_op__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \sr_op__oe__ok$52 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 17 \sr_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \sr_op__output_carry$55 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 19 \sr_op__output_cr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \sr_op__output_cr$57 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 12 \sr_op__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \sr_op__rc__ok$50 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 11 \sr_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \sr_op__rc__rc$49 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 15 \sr_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \sr_op__write_cr0$53 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 2 output 25 \xer_ca + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 2 input 30 \xer_ca$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 3 \xer_ca_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire input 29 \xer_so + attribute \module_not_derived 1 + attribute \src "issuer_ls180.v:29007.11-29010.4" + cell \n$106 \n + connect \n_ready_i \n_ready_i + connect \n_valid_o \n_valid_o + end + attribute \module_not_derived 1 + attribute \src "issuer_ls180.v:29011.11-29014.4" + cell \p$105 \p + connect \p_ready_o \p_ready_o + connect \p_valid_i \p_valid_i + end + attribute \module_not_derived 1 + attribute \src "issuer_ls180.v:29015.15-29069.4" + cell \pipe1$107 \pipe1 + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \cr_a \pipe1_cr_a + connect \cr_a_ok \pipe1_cr_a_ok + connect \muxid \pipe1_muxid + connect \muxid$1 \pipe1_muxid$2 + connect \n_ready_i \pipe1_n_ready_i + connect \n_valid_o \pipe1_n_valid_o + connect \o \pipe1_o + connect \o_ok \pipe1_o_ok + connect \p_ready_o \pipe1_p_ready_o + connect \p_valid_i \pipe1_p_valid_i + connect \ra \pipe1_ra + connect \rb \pipe1_rb + connect \rc \pipe1_rc + connect \sr_op__fn_unit \pipe1_sr_op__fn_unit + connect \sr_op__fn_unit$3 \pipe1_sr_op__fn_unit$4 + connect \sr_op__imm_data__data \pipe1_sr_op__imm_data__data + connect \sr_op__imm_data__data$4 \pipe1_sr_op__imm_data__data$5 + connect \sr_op__imm_data__ok \pipe1_sr_op__imm_data__ok + connect \sr_op__imm_data__ok$5 \pipe1_sr_op__imm_data__ok$6 + connect \sr_op__input_carry \pipe1_sr_op__input_carry + connect \sr_op__input_carry$11 \pipe1_sr_op__input_carry$12 + connect \sr_op__input_cr \pipe1_sr_op__input_cr + connect \sr_op__input_cr$13 \pipe1_sr_op__input_cr$14 + connect \sr_op__insn \pipe1_sr_op__insn + connect \sr_op__insn$17 \pipe1_sr_op__insn$18 + connect \sr_op__insn_type \pipe1_sr_op__insn_type + connect \sr_op__insn_type$2 \pipe1_sr_op__insn_type$3 + connect \sr_op__is_32bit \pipe1_sr_op__is_32bit + connect \sr_op__is_32bit$15 \pipe1_sr_op__is_32bit$16 + connect \sr_op__is_signed \pipe1_sr_op__is_signed + connect \sr_op__is_signed$16 \pipe1_sr_op__is_signed$17 + connect \sr_op__oe__oe \pipe1_sr_op__oe__oe + connect \sr_op__oe__oe$8 \pipe1_sr_op__oe__oe$9 + connect \sr_op__oe__ok \pipe1_sr_op__oe__ok + connect \sr_op__oe__ok$9 \pipe1_sr_op__oe__ok$10 + connect \sr_op__output_carry \pipe1_sr_op__output_carry + connect \sr_op__output_carry$12 \pipe1_sr_op__output_carry$13 + connect \sr_op__output_cr \pipe1_sr_op__output_cr + connect \sr_op__output_cr$14 \pipe1_sr_op__output_cr$15 + connect \sr_op__rc__ok \pipe1_sr_op__rc__ok + connect \sr_op__rc__ok$7 \pipe1_sr_op__rc__ok$8 + connect \sr_op__rc__rc \pipe1_sr_op__rc__rc + connect \sr_op__rc__rc$6 \pipe1_sr_op__rc__rc$7 + connect \sr_op__write_cr0 \pipe1_sr_op__write_cr0 + connect \sr_op__write_cr0$10 \pipe1_sr_op__write_cr0$11 + connect \xer_ca \pipe1_xer_ca + connect \xer_ca$19 \pipe1_xer_ca$20 + connect \xer_ca_ok \pipe1_xer_ca_ok + connect \xer_so \pipe1_xer_so + connect \xer_so$18 \pipe1_xer_so$19 + connect \xer_so_ok \pipe1_xer_so_ok + end + attribute \module_not_derived 1 + attribute \src "issuer_ls180.v:29070.15-29125.4" + cell \pipe2$112 \pipe2 + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \cr_a \pipe2_cr_a + connect \cr_a$20 \pipe2_cr_a$40 + connect \cr_a_ok \pipe2_cr_a_ok + connect \cr_a_ok$21 \pipe2_cr_a_ok$41 + connect \muxid \pipe2_muxid + connect \muxid$1 \pipe2_muxid$21 + connect \n_ready_i \pipe2_n_ready_i + connect \n_valid_o \pipe2_n_valid_o + connect \o \pipe2_o + connect \o$18 \pipe2_o$38 + connect \o_ok \pipe2_o_ok + connect \o_ok$19 \pipe2_o_ok$39 + connect \p_ready_o \pipe2_p_ready_o + connect \p_valid_i \pipe2_p_valid_i + connect \sr_op__fn_unit \pipe2_sr_op__fn_unit + connect \sr_op__fn_unit$3 \pipe2_sr_op__fn_unit$23 + connect \sr_op__imm_data__data \pipe2_sr_op__imm_data__data + connect \sr_op__imm_data__data$4 \pipe2_sr_op__imm_data__data$24 + connect \sr_op__imm_data__ok \pipe2_sr_op__imm_data__ok + connect \sr_op__imm_data__ok$5 \pipe2_sr_op__imm_data__ok$25 + connect \sr_op__input_carry \pipe2_sr_op__input_carry + connect \sr_op__input_carry$11 \pipe2_sr_op__input_carry$31 + connect \sr_op__input_cr \pipe2_sr_op__input_cr + connect \sr_op__input_cr$13 \pipe2_sr_op__input_cr$33 + connect \sr_op__insn \pipe2_sr_op__insn + connect \sr_op__insn$17 \pipe2_sr_op__insn$37 + connect \sr_op__insn_type \pipe2_sr_op__insn_type + connect \sr_op__insn_type$2 \pipe2_sr_op__insn_type$22 + connect \sr_op__is_32bit \pipe2_sr_op__is_32bit + connect \sr_op__is_32bit$15 \pipe2_sr_op__is_32bit$35 + connect \sr_op__is_signed \pipe2_sr_op__is_signed + connect \sr_op__is_signed$16 \pipe2_sr_op__is_signed$36 + connect \sr_op__oe__oe \pipe2_sr_op__oe__oe + connect \sr_op__oe__oe$8 \pipe2_sr_op__oe__oe$28 + connect \sr_op__oe__ok \pipe2_sr_op__oe__ok + connect \sr_op__oe__ok$9 \pipe2_sr_op__oe__ok$29 + connect \sr_op__output_carry \pipe2_sr_op__output_carry + connect \sr_op__output_carry$12 \pipe2_sr_op__output_carry$32 + connect \sr_op__output_cr \pipe2_sr_op__output_cr + connect \sr_op__output_cr$14 \pipe2_sr_op__output_cr$34 + connect \sr_op__rc__ok \pipe2_sr_op__rc__ok + connect \sr_op__rc__ok$7 \pipe2_sr_op__rc__ok$27 + connect \sr_op__rc__rc \pipe2_sr_op__rc__rc + connect \sr_op__rc__rc$6 \pipe2_sr_op__rc__rc$26 + connect \sr_op__write_cr0 \pipe2_sr_op__write_cr0 + connect \sr_op__write_cr0$10 \pipe2_sr_op__write_cr0$30 + connect \xer_ca \pipe2_xer_ca + connect \xer_ca$22 \pipe2_xer_ca$42 + connect \xer_ca_ok \pipe2_xer_ca_ok + connect \xer_ca_ok$23 \pipe2_xer_ca_ok$43 + connect \xer_so \pipe2_xer_so + connect \xer_so_ok \pipe2_xer_so_ok + end + connect \muxid 2'00 + connect { \xer_ca_ok \xer_ca } { \pipe2_xer_ca_ok$43 \pipe2_xer_ca$42 } + connect { \cr_a_ok \cr_a } { \pipe2_cr_a_ok$41 \pipe2_cr_a$40 } + connect { \o_ok \o } { \pipe2_o_ok$39 \pipe2_o$38 } + connect { \sr_op__insn$60 \sr_op__is_signed$59 \sr_op__is_32bit$58 \sr_op__output_cr$57 \sr_op__input_cr$56 \sr_op__output_carry$55 \sr_op__input_carry$54 \sr_op__write_cr0$53 \sr_op__oe__ok$52 \sr_op__oe__oe$51 \sr_op__rc__ok$50 \sr_op__rc__rc$49 \sr_op__imm_data__ok$48 \sr_op__imm_data__data$47 \sr_op__fn_unit$46 \sr_op__insn_type$45 } { \pipe2_sr_op__insn$37 \pipe2_sr_op__is_signed$36 \pipe2_sr_op__is_32bit$35 \pipe2_sr_op__output_cr$34 \pipe2_sr_op__input_cr$33 \pipe2_sr_op__output_carry$32 \pipe2_sr_op__input_carry$31 \pipe2_sr_op__write_cr0$30 \pipe2_sr_op__oe__ok$29 \pipe2_sr_op__oe__oe$28 \pipe2_sr_op__rc__ok$27 \pipe2_sr_op__rc__rc$26 \pipe2_sr_op__imm_data__ok$25 \pipe2_sr_op__imm_data__data$24 \pipe2_sr_op__fn_unit$23 \pipe2_sr_op__insn_type$22 } + connect \muxid$44 \pipe2_muxid$21 + connect \pipe2_n_ready_i \n_ready_i + connect \n_valid_o \pipe2_n_valid_o + connect \pipe1_xer_ca$20 \xer_ca$1 + connect \pipe1_xer_so$19 \xer_so + connect \pipe1_rc \rc + connect \pipe1_rb \rb + connect \pipe1_ra \ra + connect { \pipe1_sr_op__insn$18 \pipe1_sr_op__is_signed$17 \pipe1_sr_op__is_32bit$16 \pipe1_sr_op__output_cr$15 \pipe1_sr_op__input_cr$14 \pipe1_sr_op__output_carry$13 \pipe1_sr_op__input_carry$12 \pipe1_sr_op__write_cr0$11 \pipe1_sr_op__oe__ok$10 \pipe1_sr_op__oe__oe$9 \pipe1_sr_op__rc__ok$8 \pipe1_sr_op__rc__rc$7 \pipe1_sr_op__imm_data__ok$6 \pipe1_sr_op__imm_data__data$5 \pipe1_sr_op__fn_unit$4 \pipe1_sr_op__insn_type$3 } { \sr_op__insn \sr_op__is_signed \sr_op__is_32bit \sr_op__output_cr \sr_op__input_cr \sr_op__output_carry \sr_op__input_carry \sr_op__write_cr0 \sr_op__oe__ok \sr_op__oe__oe \sr_op__rc__ok \sr_op__rc__rc \sr_op__imm_data__ok \sr_op__imm_data__data \sr_op__fn_unit \sr_op__insn_type } + connect \pipe1_muxid$2 2'00 + connect \p_ready_o \pipe1_p_ready_o + connect \pipe1_p_valid_i \p_valid_i + connect { \pipe2_xer_ca_ok \pipe2_xer_ca } { \pipe1_xer_ca_ok \pipe1_xer_ca } + connect { \pipe2_xer_so_ok \pipe2_xer_so } { \pipe1_xer_so_ok \pipe1_xer_so } + connect { \pipe2_cr_a_ok \pipe2_cr_a } { \pipe1_cr_a_ok \pipe1_cr_a } + connect { \pipe2_o_ok \pipe2_o } { \pipe1_o_ok \pipe1_o } + connect { \pipe2_sr_op__insn \pipe2_sr_op__is_signed \pipe2_sr_op__is_32bit \pipe2_sr_op__output_cr \pipe2_sr_op__input_cr \pipe2_sr_op__output_carry \pipe2_sr_op__input_carry \pipe2_sr_op__write_cr0 \pipe2_sr_op__oe__ok \pipe2_sr_op__oe__oe \pipe2_sr_op__rc__ok \pipe2_sr_op__rc__rc \pipe2_sr_op__imm_data__ok \pipe2_sr_op__imm_data__data \pipe2_sr_op__fn_unit \pipe2_sr_op__insn_type } { \pipe1_sr_op__insn \pipe1_sr_op__is_signed \pipe1_sr_op__is_32bit \pipe1_sr_op__output_cr \pipe1_sr_op__input_cr \pipe1_sr_op__output_carry \pipe1_sr_op__input_carry \pipe1_sr_op__write_cr0 \pipe1_sr_op__oe__ok \pipe1_sr_op__oe__oe \pipe1_sr_op__rc__ok \pipe1_sr_op__rc__rc \pipe1_sr_op__imm_data__ok \pipe1_sr_op__imm_data__data \pipe1_sr_op__fn_unit \pipe1_sr_op__insn_type } + connect \pipe2_muxid \pipe1_muxid + connect \pipe1_n_ready_i \pipe2_p_ready_o + connect \pipe2_p_valid_i \pipe1_n_valid_o +end +attribute \src "issuer_ls180.v:29155.1-29701.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.fus.spr0.alu_spr0" +attribute \generator "nMigen" +module \alu_spr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" + wire input 28 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" + wire input 7 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 output 16 \fast1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 22 \fast1$2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 5 \fast1_ok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \muxid$16 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" + wire input 9 \n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" + wire output 8 \n_valid_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 output 14 \o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 1 \o_ok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" + wire output 27 \p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" + wire input 26 \p_valid_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \pipe_fast1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 \pipe_fast1$12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \pipe_fast1_ok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \pipe_muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \pipe_muxid$6 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" + wire \pipe_n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" + wire \pipe_n_valid_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 \pipe_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \pipe_o_ok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" + wire \pipe_p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" + wire \pipe_p_valid_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \pipe_ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \pipe_spr1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 \pipe_spr1$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \pipe_spr1_ok + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 \pipe_spr_op__fn_unit + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 \pipe_spr_op__fn_unit$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \pipe_spr_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \pipe_spr_op__insn$9 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \pipe_spr_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \pipe_spr_op__insn_type$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe_spr_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe_spr_op__is_32bit$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 2 \pipe_xer_ca + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 2 \pipe_xer_ca$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \pipe_xer_ca_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 2 \pipe_xer_ov + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 2 \pipe_xer_ov$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \pipe_xer_ov_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire \pipe_xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \pipe_xer_so$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \pipe_xer_so_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 20 \ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 output 15 \spr1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 21 \spr1$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 6 \spr1_ok + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 input 11 \spr_op__fn_unit + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 \spr_op__fn_unit$18 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 12 \spr_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \spr_op__insn$19 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 input 10 \spr_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \spr_op__insn_type$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 13 \spr_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \spr_op__is_32bit$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 2 output 19 \xer_ca + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 2 input 25 \xer_ca$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 2 \xer_ca_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 2 output 18 \xer_ov + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 2 input 24 \xer_ov$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 3 \xer_ov_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 17 \xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire input 23 \xer_so$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 4 \xer_so_ok + attribute \module_not_derived 1 + attribute \src "issuer_ls180.v:29636.10-29639.4" + cell \n$60 \n + connect \n_ready_i \n_ready_i + connect \n_valid_o \n_valid_o + end + attribute \module_not_derived 1 + attribute \src "issuer_ls180.v:29640.10-29643.4" + cell \p$59 \p + connect \p_ready_o \p_ready_o + connect \p_valid_i \p_valid_i + end + attribute \module_not_derived 1 + attribute \src "issuer_ls180.v:29644.13-29679.4" + cell \pipe$61 \pipe + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \fast1 \pipe_fast1 + connect \fast1$7 \pipe_fast1$12 + connect \fast1_ok \pipe_fast1_ok + connect \muxid \pipe_muxid + connect \muxid$1 \pipe_muxid$6 + connect \n_ready_i \pipe_n_ready_i + connect \n_valid_o \pipe_n_valid_o + connect \o \pipe_o + connect \o_ok \pipe_o_ok + connect \p_ready_o \pipe_p_ready_o + connect \p_valid_i \pipe_p_valid_i + connect \ra \pipe_ra + connect \spr1 \pipe_spr1 + connect \spr1$6 \pipe_spr1$11 + connect \spr1_ok \pipe_spr1_ok + connect \spr_op__fn_unit \pipe_spr_op__fn_unit + connect \spr_op__fn_unit$3 \pipe_spr_op__fn_unit$8 + connect \spr_op__insn \pipe_spr_op__insn + connect \spr_op__insn$4 \pipe_spr_op__insn$9 + connect \spr_op__insn_type \pipe_spr_op__insn_type + connect \spr_op__insn_type$2 \pipe_spr_op__insn_type$7 + connect \spr_op__is_32bit \pipe_spr_op__is_32bit + connect \spr_op__is_32bit$5 \pipe_spr_op__is_32bit$10 + connect \xer_ca \pipe_xer_ca + connect \xer_ca$10 \pipe_xer_ca$15 + connect \xer_ca_ok \pipe_xer_ca_ok + connect \xer_ov \pipe_xer_ov + connect \xer_ov$9 \pipe_xer_ov$14 + connect \xer_ov_ok \pipe_xer_ov_ok + connect \xer_so \pipe_xer_so + connect \xer_so$8 \pipe_xer_so$13 + connect \xer_so_ok \pipe_xer_so_ok + end + connect \muxid 2'00 + connect { \xer_ca_ok \xer_ca } { \pipe_xer_ca_ok \pipe_xer_ca$15 } + connect { \xer_ov_ok \xer_ov } { \pipe_xer_ov_ok \pipe_xer_ov$14 } + connect { \xer_so_ok \xer_so } { \pipe_xer_so_ok \pipe_xer_so$13 } + connect { \fast1_ok \fast1 } { \pipe_fast1_ok \pipe_fast1$12 } + connect { \spr1_ok \spr1 } { \pipe_spr1_ok \pipe_spr1$11 } + connect { \o_ok \o } { \pipe_o_ok \pipe_o } + connect { \spr_op__is_32bit$20 \spr_op__insn$19 \spr_op__fn_unit$18 \spr_op__insn_type$17 } { \pipe_spr_op__is_32bit$10 \pipe_spr_op__insn$9 \pipe_spr_op__fn_unit$8 \pipe_spr_op__insn_type$7 } + connect \muxid$16 \pipe_muxid$6 + connect \pipe_n_ready_i \n_ready_i + connect \n_valid_o \pipe_n_valid_o + connect \pipe_xer_ca \xer_ca$5 + connect \pipe_xer_ov \xer_ov$4 + connect \pipe_xer_so \xer_so$3 + connect \pipe_fast1 \fast1$2 + connect \pipe_spr1 \spr1$1 + connect \pipe_ra \ra + connect { \pipe_spr_op__is_32bit \pipe_spr_op__insn \pipe_spr_op__fn_unit \pipe_spr_op__insn_type } { \spr_op__is_32bit \spr_op__insn \spr_op__fn_unit \spr_op__insn_type } + connect \pipe_muxid 2'00 + connect \p_ready_o \pipe_p_ready_o + connect \pipe_p_valid_i \p_valid_i +end +attribute \src "issuer_ls180.v:29705.1-30268.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.fus.trap0.alu_trap0" +attribute \generator "nMigen" +module \alu_trap0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" + wire input 28 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" + wire input 6 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 output 18 \fast1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 24 \fast1$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 2 \fast1_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 output 19 \fast2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 25 \fast2$2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 3 \fast2_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 output 21 \msr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 5 \msr_ok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \muxid$14 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" + wire input 8 \n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" + wire output 7 \n_valid_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 output 20 \nia + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 4 \nia_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 output 17 \o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 1 \o_ok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" + wire output 27 \p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" + wire input 26 \p_valid_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \pipe_fast1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 \pipe_fast1$12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \pipe_fast1_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \pipe_fast2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 \pipe_fast2$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \pipe_fast2_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 \pipe_msr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \pipe_msr_ok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \pipe_muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \pipe_muxid$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" + wire \pipe_n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" + wire \pipe_n_valid_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 \pipe_nia + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \pipe_nia_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 \pipe_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \pipe_o_ok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" + wire \pipe_p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" + wire \pipe_p_valid_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \pipe_ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \pipe_rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \pipe_trap_op__cia + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \pipe_trap_op__cia$8 + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 \pipe_trap_op__fn_unit + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 \pipe_trap_op__fn_unit$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \pipe_trap_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \pipe_trap_op__insn$6 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \pipe_trap_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \pipe_trap_op__insn_type$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe_trap_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \pipe_trap_op__is_32bit$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \pipe_trap_op__msr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \pipe_trap_op__msr$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 13 \pipe_trap_op__trapaddr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 13 \pipe_trap_op__trapaddr$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \pipe_trap_op__traptype + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \pipe_trap_op__traptype$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 22 \ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 23 \rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 input 13 \trap_op__cia + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \trap_op__cia$19 + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 input 10 \trap_op__fn_unit + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 \trap_op__fn_unit$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 11 \trap_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \trap_op__insn$17 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 input 9 \trap_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \trap_op__insn_type$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 14 \trap_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \trap_op__is_32bit$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 input 12 \trap_op__msr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \trap_op__msr$18 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 13 input 16 \trap_op__trapaddr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 13 \trap_op__trapaddr$22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 input 15 \trap_op__traptype + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \trap_op__traptype$21 + attribute \module_not_derived 1 + attribute \src "issuer_ls180.v:30202.10-30205.4" + cell \n$31 \n + connect \n_ready_i \n_ready_i + connect \n_valid_o \n_valid_o + end + attribute \module_not_derived 1 + attribute \src "issuer_ls180.v:30206.10-30209.4" + cell \p$30 \p + connect \p_ready_o \p_ready_o + connect \p_valid_i \p_valid_i + end + attribute \module_not_derived 1 + attribute \src "issuer_ls180.v:30210.13-30249.4" + cell \pipe$32 \pipe + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \fast1 \pipe_fast1 + connect \fast1$10 \pipe_fast1$12 + connect \fast1_ok \pipe_fast1_ok + connect \fast2 \pipe_fast2 + connect \fast2$11 \pipe_fast2$13 + connect \fast2_ok \pipe_fast2_ok + connect \msr \pipe_msr + connect \msr_ok \pipe_msr_ok + connect \muxid \pipe_muxid + connect \muxid$1 \pipe_muxid$3 + connect \n_ready_i \pipe_n_ready_i + connect \n_valid_o \pipe_n_valid_o + connect \nia \pipe_nia + connect \nia_ok \pipe_nia_ok + connect \o \pipe_o + connect \o_ok \pipe_o_ok + connect \p_ready_o \pipe_p_ready_o + connect \p_valid_i \pipe_p_valid_i + connect \ra \pipe_ra + connect \rb \pipe_rb + connect \trap_op__cia \pipe_trap_op__cia + connect \trap_op__cia$6 \pipe_trap_op__cia$8 + connect \trap_op__fn_unit \pipe_trap_op__fn_unit + connect \trap_op__fn_unit$3 \pipe_trap_op__fn_unit$5 + connect \trap_op__insn \pipe_trap_op__insn + connect \trap_op__insn$4 \pipe_trap_op__insn$6 + connect \trap_op__insn_type \pipe_trap_op__insn_type + connect \trap_op__insn_type$2 \pipe_trap_op__insn_type$4 + connect \trap_op__is_32bit \pipe_trap_op__is_32bit + connect \trap_op__is_32bit$7 \pipe_trap_op__is_32bit$9 + connect \trap_op__msr \pipe_trap_op__msr + connect \trap_op__msr$5 \pipe_trap_op__msr$7 + connect \trap_op__trapaddr \pipe_trap_op__trapaddr + connect \trap_op__trapaddr$9 \pipe_trap_op__trapaddr$11 + connect \trap_op__traptype \pipe_trap_op__traptype + connect \trap_op__traptype$8 \pipe_trap_op__traptype$10 + end + connect \muxid 2'00 + connect { \msr_ok \msr } { \pipe_msr_ok \pipe_msr } + connect { \nia_ok \nia } { \pipe_nia_ok \pipe_nia } + connect { \fast2_ok \fast2 } { \pipe_fast2_ok \pipe_fast2$13 } + connect { \fast1_ok \fast1 } { \pipe_fast1_ok \pipe_fast1$12 } + connect { \o_ok \o } { \pipe_o_ok \pipe_o } + connect { \trap_op__trapaddr$22 \trap_op__traptype$21 \trap_op__is_32bit$20 \trap_op__cia$19 \trap_op__msr$18 \trap_op__insn$17 \trap_op__fn_unit$16 \trap_op__insn_type$15 } { \pipe_trap_op__trapaddr$11 \pipe_trap_op__traptype$10 \pipe_trap_op__is_32bit$9 \pipe_trap_op__cia$8 \pipe_trap_op__msr$7 \pipe_trap_op__insn$6 \pipe_trap_op__fn_unit$5 \pipe_trap_op__insn_type$4 } + connect \muxid$14 \pipe_muxid$3 + connect \pipe_n_ready_i \n_ready_i + connect \n_valid_o \pipe_n_valid_o + connect \pipe_fast2 \fast2$2 + connect \pipe_fast1 \fast1$1 + connect \pipe_rb \rb + connect \pipe_ra \ra + connect { \pipe_trap_op__trapaddr \pipe_trap_op__traptype \pipe_trap_op__is_32bit \pipe_trap_op__cia \pipe_trap_op__msr \pipe_trap_op__insn \pipe_trap_op__fn_unit \pipe_trap_op__insn_type } { \trap_op__trapaddr \trap_op__traptype \trap_op__is_32bit \trap_op__cia \trap_op__msr \trap_op__insn \trap_op__fn_unit \trap_op__insn_type } + connect \pipe_muxid 2'00 + connect \p_ready_o \pipe_p_ready_o + connect \pipe_p_valid_i \p_valid_i +end +attribute \src "issuer_ls180.v:30272.1-30330.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.fus.alu0.alui_l" +attribute \generator "nMigen" +module \alui_l + attribute \src "issuer_ls180.v:30273.7-30273.20" + wire $0\initial[0:0] + attribute \src "issuer_ls180.v:30318.3-30326.6" + wire $0\q_int$next[0:0]$915 + attribute \src "issuer_ls180.v:30316.3-30317.27" + wire $0\q_int[0:0] + attribute \src "issuer_ls180.v:30318.3-30326.6" + wire $1\q_int$next[0:0]$916 + attribute \src "issuer_ls180.v:30297.7-30297.19" + wire $1\q_int[0:0] + attribute \src "issuer_ls180.v:30308.17-30308.96" + wire $and$issuer_ls180.v:30308$905_Y + attribute \src "issuer_ls180.v:30313.17-30313.96" + wire $and$issuer_ls180.v:30313$910_Y + attribute \src "issuer_ls180.v:30310.18-30310.94" + wire $not$issuer_ls180.v:30310$907_Y + attribute \src "issuer_ls180.v:30312.17-30312.93" + wire $not$issuer_ls180.v:30312$909_Y + attribute \src "issuer_ls180.v:30315.17-30315.93" + wire $not$issuer_ls180.v:30315$912_Y + attribute \src "issuer_ls180.v:30309.18-30309.99" + wire $or$issuer_ls180.v:30309$906_Y + attribute \src "issuer_ls180.v:30311.18-30311.100" + wire $or$issuer_ls180.v:30311$908_Y + attribute \src "issuer_ls180.v:30314.17-30314.98" + wire $or$issuer_ls180.v:30314$911_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire \$13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" + wire input 5 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" + wire input 1 \coresync_rst + attribute \src "issuer_ls180.v:30273.7-30273.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire output 2 \q_alui + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" + wire \qlq_alui + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + wire \qn_alui + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire input 3 \r_alui + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire input 4 \s_alui + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $and $and$issuer_ls180.v:30308$905 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$7 + connect \Y $and$issuer_ls180.v:30308$905_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $and $and$issuer_ls180.v:30313$910 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$1 + connect \Y $and$issuer_ls180.v:30313$910_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + cell $not $not$issuer_ls180.v:30310$907 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_alui + connect \Y $not$issuer_ls180.v:30310$907_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $not $not$issuer_ls180.v:30312$909 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_alui + connect \Y $not$issuer_ls180.v:30312$909_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $not $not$issuer_ls180.v:30315$912 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_alui + connect \Y $not$issuer_ls180.v:30315$912_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $or $or$issuer_ls180.v:30309$906 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$9 + connect \B \s_alui + connect \Y $or$issuer_ls180.v:30309$906_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + cell $or $or$issuer_ls180.v:30311$908 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_alui + connect \B \q_int + connect \Y $or$issuer_ls180.v:30311$908_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $or $or$issuer_ls180.v:30314$911 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$3 + connect \B \s_alui + connect \Y $or$issuer_ls180.v:30314$911_Y + end + attribute \src "issuer_ls180.v:30273.7-30273.20" + process $proc$issuer_ls180.v:30273$917 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "issuer_ls180.v:30297.7-30297.19" + process $proc$issuer_ls180.v:30297$918 + assign { } { } + assign $1\q_int[0:0] 1'0 + sync always + sync init + update \q_int $1\q_int[0:0] + end + attribute \src "issuer_ls180.v:30316.3-30317.27" + process $proc$issuer_ls180.v:30316$913 + assign { } { } + assign $0\q_int[0:0] \q_int$next + sync posedge \coresync_clk + update \q_int $0\q_int[0:0] + end + attribute \src "issuer_ls180.v:30318.3-30326.6" + process $proc$issuer_ls180.v:30318$914 + assign { } { } + assign { } { } + assign $0\q_int$next[0:0]$915 $1\q_int$next[0:0]$916 + attribute \src "issuer_ls180.v:30319.5-30319.29" + switch \initial + attribute \src "issuer_ls180.v:30319.9-30319.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\q_int$next[0:0]$916 1'0 + case + assign $1\q_int$next[0:0]$916 \$5 + end + sync always + update \q_int$next $0\q_int$next[0:0]$915 + end + connect \$9 $and$issuer_ls180.v:30308$905_Y + connect \$11 $or$issuer_ls180.v:30309$906_Y + connect \$13 $not$issuer_ls180.v:30310$907_Y + connect \$15 $or$issuer_ls180.v:30311$908_Y + connect \$1 $not$issuer_ls180.v:30312$909_Y + connect \$3 $and$issuer_ls180.v:30313$910_Y + connect \$5 $or$issuer_ls180.v:30314$911_Y + connect \$7 $not$issuer_ls180.v:30315$912_Y + connect \qlq_alui \$15 + connect \qn_alui \$13 + connect \q_alui \$11 +end +attribute \src "issuer_ls180.v:30334.1-30392.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.fus.mul0.alui_l" +attribute \generator "nMigen" +module \alui_l$103 + attribute \src "issuer_ls180.v:30335.7-30335.20" + wire $0\initial[0:0] + attribute \src "issuer_ls180.v:30380.3-30388.6" + wire $0\q_int$next[0:0]$929 + attribute \src "issuer_ls180.v:30378.3-30379.27" + wire $0\q_int[0:0] + attribute \src "issuer_ls180.v:30380.3-30388.6" + wire $1\q_int$next[0:0]$930 + attribute \src "issuer_ls180.v:30359.7-30359.19" + wire $1\q_int[0:0] + attribute \src "issuer_ls180.v:30370.17-30370.96" + wire $and$issuer_ls180.v:30370$919_Y + attribute \src "issuer_ls180.v:30375.17-30375.96" + wire $and$issuer_ls180.v:30375$924_Y + attribute \src "issuer_ls180.v:30372.18-30372.94" + wire $not$issuer_ls180.v:30372$921_Y + attribute \src "issuer_ls180.v:30374.17-30374.93" + wire $not$issuer_ls180.v:30374$923_Y + attribute \src "issuer_ls180.v:30377.17-30377.93" + wire $not$issuer_ls180.v:30377$926_Y + attribute \src "issuer_ls180.v:30371.18-30371.99" + wire $or$issuer_ls180.v:30371$920_Y + attribute \src "issuer_ls180.v:30373.18-30373.100" + wire $or$issuer_ls180.v:30373$922_Y + attribute \src "issuer_ls180.v:30376.17-30376.98" + wire $or$issuer_ls180.v:30376$925_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire \$13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" + wire input 5 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" + wire input 1 \coresync_rst + attribute \src "issuer_ls180.v:30335.7-30335.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire output 2 \q_alui + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" + wire \qlq_alui + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + wire \qn_alui + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire input 3 \r_alui + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire input 4 \s_alui + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $and $and$issuer_ls180.v:30370$919 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$7 + connect \Y $and$issuer_ls180.v:30370$919_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $and $and$issuer_ls180.v:30375$924 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$1 + connect \Y $and$issuer_ls180.v:30375$924_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + cell $not $not$issuer_ls180.v:30372$921 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_alui + connect \Y $not$issuer_ls180.v:30372$921_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $not $not$issuer_ls180.v:30374$923 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_alui + connect \Y $not$issuer_ls180.v:30374$923_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $not $not$issuer_ls180.v:30377$926 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_alui + connect \Y $not$issuer_ls180.v:30377$926_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $or $or$issuer_ls180.v:30371$920 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$9 + connect \B \s_alui + connect \Y $or$issuer_ls180.v:30371$920_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + cell $or $or$issuer_ls180.v:30373$922 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_alui + connect \B \q_int + connect \Y $or$issuer_ls180.v:30373$922_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $or $or$issuer_ls180.v:30376$925 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$3 + connect \B \s_alui + connect \Y $or$issuer_ls180.v:30376$925_Y + end + attribute \src "issuer_ls180.v:30335.7-30335.20" + process $proc$issuer_ls180.v:30335$931 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "issuer_ls180.v:30359.7-30359.19" + process $proc$issuer_ls180.v:30359$932 + assign { } { } + assign $1\q_int[0:0] 1'0 + sync always + sync init + update \q_int $1\q_int[0:0] + end + attribute \src "issuer_ls180.v:30378.3-30379.27" + process $proc$issuer_ls180.v:30378$927 + assign { } { } + assign $0\q_int[0:0] \q_int$next + sync posedge \coresync_clk + update \q_int $0\q_int[0:0] + end + attribute \src "issuer_ls180.v:30380.3-30388.6" + process $proc$issuer_ls180.v:30380$928 + assign { } { } + assign { } { } + assign $0\q_int$next[0:0]$929 $1\q_int$next[0:0]$930 + attribute \src "issuer_ls180.v:30381.5-30381.29" + switch \initial + attribute \src "issuer_ls180.v:30381.9-30381.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\q_int$next[0:0]$930 1'0 + case + assign $1\q_int$next[0:0]$930 \$5 + end + sync always + update \q_int$next $0\q_int$next[0:0]$929 + end + connect \$9 $and$issuer_ls180.v:30370$919_Y + connect \$11 $or$issuer_ls180.v:30371$920_Y + connect \$13 $not$issuer_ls180.v:30372$921_Y + connect \$15 $or$issuer_ls180.v:30373$922_Y + connect \$1 $not$issuer_ls180.v:30374$923_Y + connect \$3 $and$issuer_ls180.v:30375$924_Y + connect \$5 $or$issuer_ls180.v:30376$925_Y + connect \$7 $not$issuer_ls180.v:30377$926_Y + connect \qlq_alui \$15 + connect \qn_alui \$13 + connect \q_alui \$11 +end +attribute \src "issuer_ls180.v:30396.1-30454.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.fus.shiftrot0.alui_l" +attribute \generator "nMigen" +module \alui_l$121 + attribute \src "issuer_ls180.v:30397.7-30397.20" + wire $0\initial[0:0] + attribute \src "issuer_ls180.v:30442.3-30450.6" + wire $0\q_int$next[0:0]$943 + attribute \src "issuer_ls180.v:30440.3-30441.27" + wire $0\q_int[0:0] + attribute \src "issuer_ls180.v:30442.3-30450.6" + wire $1\q_int$next[0:0]$944 + attribute \src "issuer_ls180.v:30421.7-30421.19" + wire $1\q_int[0:0] + attribute \src "issuer_ls180.v:30432.17-30432.96" + wire $and$issuer_ls180.v:30432$933_Y + attribute \src "issuer_ls180.v:30437.17-30437.96" + wire $and$issuer_ls180.v:30437$938_Y + attribute \src "issuer_ls180.v:30434.18-30434.94" + wire $not$issuer_ls180.v:30434$935_Y + attribute \src "issuer_ls180.v:30436.17-30436.93" + wire $not$issuer_ls180.v:30436$937_Y + attribute \src "issuer_ls180.v:30439.17-30439.93" + wire $not$issuer_ls180.v:30439$940_Y + attribute \src "issuer_ls180.v:30433.18-30433.99" + wire $or$issuer_ls180.v:30433$934_Y + attribute \src "issuer_ls180.v:30435.18-30435.100" + wire $or$issuer_ls180.v:30435$936_Y + attribute \src "issuer_ls180.v:30438.17-30438.98" + wire $or$issuer_ls180.v:30438$939_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire \$13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" + wire input 5 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" + wire input 1 \coresync_rst + attribute \src "issuer_ls180.v:30397.7-30397.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire output 2 \q_alui + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" + wire \qlq_alui + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + wire \qn_alui + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire input 3 \r_alui + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire input 4 \s_alui + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $and $and$issuer_ls180.v:30432$933 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$7 + connect \Y $and$issuer_ls180.v:30432$933_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $and $and$issuer_ls180.v:30437$938 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$1 + connect \Y $and$issuer_ls180.v:30437$938_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + cell $not $not$issuer_ls180.v:30434$935 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_alui + connect \Y $not$issuer_ls180.v:30434$935_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $not $not$issuer_ls180.v:30436$937 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_alui + connect \Y $not$issuer_ls180.v:30436$937_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $not $not$issuer_ls180.v:30439$940 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_alui + connect \Y $not$issuer_ls180.v:30439$940_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $or $or$issuer_ls180.v:30433$934 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$9 + connect \B \s_alui + connect \Y $or$issuer_ls180.v:30433$934_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + cell $or $or$issuer_ls180.v:30435$936 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_alui + connect \B \q_int + connect \Y $or$issuer_ls180.v:30435$936_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $or $or$issuer_ls180.v:30438$939 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$3 + connect \B \s_alui + connect \Y $or$issuer_ls180.v:30438$939_Y + end + attribute \src "issuer_ls180.v:30397.7-30397.20" + process $proc$issuer_ls180.v:30397$945 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "issuer_ls180.v:30421.7-30421.19" + process $proc$issuer_ls180.v:30421$946 + assign { } { } + assign $1\q_int[0:0] 1'0 + sync always + sync init + update \q_int $1\q_int[0:0] + end + attribute \src "issuer_ls180.v:30440.3-30441.27" + process $proc$issuer_ls180.v:30440$941 + assign { } { } + assign $0\q_int[0:0] \q_int$next + sync posedge \coresync_clk + update \q_int $0\q_int[0:0] + end + attribute \src "issuer_ls180.v:30442.3-30450.6" + process $proc$issuer_ls180.v:30442$942 + assign { } { } + assign { } { } + assign $0\q_int$next[0:0]$943 $1\q_int$next[0:0]$944 + attribute \src "issuer_ls180.v:30443.5-30443.29" + switch \initial + attribute \src "issuer_ls180.v:30443.9-30443.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\q_int$next[0:0]$944 1'0 + case + assign $1\q_int$next[0:0]$944 \$5 + end + sync always + update \q_int$next $0\q_int$next[0:0]$943 + end + connect \$9 $and$issuer_ls180.v:30432$933_Y + connect \$11 $or$issuer_ls180.v:30433$934_Y + connect \$13 $not$issuer_ls180.v:30434$935_Y + connect \$15 $or$issuer_ls180.v:30435$936_Y + connect \$1 $not$issuer_ls180.v:30436$937_Y + connect \$3 $and$issuer_ls180.v:30437$938_Y + connect \$5 $or$issuer_ls180.v:30438$939_Y + connect \$7 $not$issuer_ls180.v:30439$940_Y + connect \qlq_alui \$15 + connect \qn_alui \$13 + connect \q_alui \$11 +end +attribute \src "issuer_ls180.v:30458.1-30516.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.fus.cr0.alui_l" +attribute \generator "nMigen" +module \alui_l$15 + attribute \src "issuer_ls180.v:30459.7-30459.20" + wire $0\initial[0:0] + attribute \src "issuer_ls180.v:30504.3-30512.6" + wire $0\q_int$next[0:0]$957 + attribute \src "issuer_ls180.v:30502.3-30503.27" + wire $0\q_int[0:0] + attribute \src "issuer_ls180.v:30504.3-30512.6" + wire $1\q_int$next[0:0]$958 + attribute \src "issuer_ls180.v:30483.7-30483.19" + wire $1\q_int[0:0] + attribute \src "issuer_ls180.v:30494.17-30494.96" + wire $and$issuer_ls180.v:30494$947_Y + attribute \src "issuer_ls180.v:30499.17-30499.96" + wire $and$issuer_ls180.v:30499$952_Y + attribute \src "issuer_ls180.v:30496.18-30496.94" + wire $not$issuer_ls180.v:30496$949_Y + attribute \src "issuer_ls180.v:30498.17-30498.93" + wire $not$issuer_ls180.v:30498$951_Y + attribute \src "issuer_ls180.v:30501.17-30501.93" + wire $not$issuer_ls180.v:30501$954_Y + attribute \src "issuer_ls180.v:30495.18-30495.99" + wire $or$issuer_ls180.v:30495$948_Y + attribute \src "issuer_ls180.v:30497.18-30497.100" + wire $or$issuer_ls180.v:30497$950_Y + attribute \src "issuer_ls180.v:30500.17-30500.98" + wire $or$issuer_ls180.v:30500$953_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire \$13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" + wire input 5 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" + wire input 1 \coresync_rst + attribute \src "issuer_ls180.v:30459.7-30459.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire output 2 \q_alui + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" + wire \qlq_alui + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + wire \qn_alui + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire input 3 \r_alui + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire input 4 \s_alui + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $and $and$issuer_ls180.v:30494$947 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$7 + connect \Y $and$issuer_ls180.v:30494$947_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $and $and$issuer_ls180.v:30499$952 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$1 + connect \Y $and$issuer_ls180.v:30499$952_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + cell $not $not$issuer_ls180.v:30496$949 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_alui + connect \Y $not$issuer_ls180.v:30496$949_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $not $not$issuer_ls180.v:30498$951 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_alui + connect \Y $not$issuer_ls180.v:30498$951_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $not $not$issuer_ls180.v:30501$954 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_alui + connect \Y $not$issuer_ls180.v:30501$954_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $or $or$issuer_ls180.v:30495$948 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$9 + connect \B \s_alui + connect \Y $or$issuer_ls180.v:30495$948_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + cell $or $or$issuer_ls180.v:30497$950 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_alui + connect \B \q_int + connect \Y $or$issuer_ls180.v:30497$950_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $or $or$issuer_ls180.v:30500$953 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$3 + connect \B \s_alui + connect \Y $or$issuer_ls180.v:30500$953_Y + end + attribute \src "issuer_ls180.v:30459.7-30459.20" + process $proc$issuer_ls180.v:30459$959 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "issuer_ls180.v:30483.7-30483.19" + process $proc$issuer_ls180.v:30483$960 + assign { } { } + assign $1\q_int[0:0] 1'0 + sync always + sync init + update \q_int $1\q_int[0:0] + end + attribute \src "issuer_ls180.v:30502.3-30503.27" + process $proc$issuer_ls180.v:30502$955 + assign { } { } + assign $0\q_int[0:0] \q_int$next + sync posedge \coresync_clk + update \q_int $0\q_int[0:0] + end + attribute \src "issuer_ls180.v:30504.3-30512.6" + process $proc$issuer_ls180.v:30504$956 + assign { } { } + assign { } { } + assign $0\q_int$next[0:0]$957 $1\q_int$next[0:0]$958 + attribute \src "issuer_ls180.v:30505.5-30505.29" + switch \initial + attribute \src "issuer_ls180.v:30505.9-30505.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\q_int$next[0:0]$958 1'0 + case + assign $1\q_int$next[0:0]$958 \$5 + end + sync always + update \q_int$next $0\q_int$next[0:0]$957 + end + connect \$9 $and$issuer_ls180.v:30494$947_Y + connect \$11 $or$issuer_ls180.v:30495$948_Y + connect \$13 $not$issuer_ls180.v:30496$949_Y + connect \$15 $or$issuer_ls180.v:30497$950_Y + connect \$1 $not$issuer_ls180.v:30498$951_Y + connect \$3 $and$issuer_ls180.v:30499$952_Y + connect \$5 $or$issuer_ls180.v:30500$953_Y + connect \$7 $not$issuer_ls180.v:30501$954_Y + connect \qlq_alui \$15 + connect \qn_alui \$13 + connect \q_alui \$11 +end +attribute \src "issuer_ls180.v:30520.1-30578.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.fus.branch0.alui_l" +attribute \generator "nMigen" +module \alui_l$28 + attribute \src "issuer_ls180.v:30521.7-30521.20" + wire $0\initial[0:0] + attribute \src "issuer_ls180.v:30566.3-30574.6" + wire $0\q_int$next[0:0]$971 + attribute \src "issuer_ls180.v:30564.3-30565.27" + wire $0\q_int[0:0] + attribute \src "issuer_ls180.v:30566.3-30574.6" + wire $1\q_int$next[0:0]$972 + attribute \src "issuer_ls180.v:30545.7-30545.19" + wire $1\q_int[0:0] + attribute \src "issuer_ls180.v:30556.17-30556.96" + wire $and$issuer_ls180.v:30556$961_Y + attribute \src "issuer_ls180.v:30561.17-30561.96" + wire $and$issuer_ls180.v:30561$966_Y + attribute \src "issuer_ls180.v:30558.18-30558.94" + wire $not$issuer_ls180.v:30558$963_Y + attribute \src "issuer_ls180.v:30560.17-30560.93" + wire $not$issuer_ls180.v:30560$965_Y + attribute \src "issuer_ls180.v:30563.17-30563.93" + wire $not$issuer_ls180.v:30563$968_Y + attribute \src "issuer_ls180.v:30557.18-30557.99" + wire $or$issuer_ls180.v:30557$962_Y + attribute \src "issuer_ls180.v:30559.18-30559.100" + wire $or$issuer_ls180.v:30559$964_Y + attribute \src "issuer_ls180.v:30562.17-30562.98" + wire $or$issuer_ls180.v:30562$967_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire \$13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" + wire input 5 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" + wire input 1 \coresync_rst + attribute \src "issuer_ls180.v:30521.7-30521.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire output 2 \q_alui + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" + wire \qlq_alui + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + wire \qn_alui + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire input 3 \r_alui + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire input 4 \s_alui + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $and $and$issuer_ls180.v:30556$961 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$7 + connect \Y $and$issuer_ls180.v:30556$961_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $and $and$issuer_ls180.v:30561$966 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$1 + connect \Y $and$issuer_ls180.v:30561$966_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + cell $not $not$issuer_ls180.v:30558$963 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_alui + connect \Y $not$issuer_ls180.v:30558$963_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $not $not$issuer_ls180.v:30560$965 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_alui + connect \Y $not$issuer_ls180.v:30560$965_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $not $not$issuer_ls180.v:30563$968 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_alui + connect \Y $not$issuer_ls180.v:30563$968_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $or $or$issuer_ls180.v:30557$962 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$9 + connect \B \s_alui + connect \Y $or$issuer_ls180.v:30557$962_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + cell $or $or$issuer_ls180.v:30559$964 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_alui + connect \B \q_int + connect \Y $or$issuer_ls180.v:30559$964_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $or $or$issuer_ls180.v:30562$967 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$3 + connect \B \s_alui + connect \Y $or$issuer_ls180.v:30562$967_Y + end + attribute \src "issuer_ls180.v:30521.7-30521.20" + process $proc$issuer_ls180.v:30521$973 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "issuer_ls180.v:30545.7-30545.19" + process $proc$issuer_ls180.v:30545$974 + assign { } { } + assign $1\q_int[0:0] 1'0 + sync always + sync init + update \q_int $1\q_int[0:0] + end + attribute \src "issuer_ls180.v:30564.3-30565.27" + process $proc$issuer_ls180.v:30564$969 + assign { } { } + assign $0\q_int[0:0] \q_int$next + sync posedge \coresync_clk + update \q_int $0\q_int[0:0] + end + attribute \src "issuer_ls180.v:30566.3-30574.6" + process $proc$issuer_ls180.v:30566$970 + assign { } { } + assign { } { } + assign $0\q_int$next[0:0]$971 $1\q_int$next[0:0]$972 + attribute \src "issuer_ls180.v:30567.5-30567.29" + switch \initial + attribute \src "issuer_ls180.v:30567.9-30567.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\q_int$next[0:0]$972 1'0 + case + assign $1\q_int$next[0:0]$972 \$5 + end + sync always + update \q_int$next $0\q_int$next[0:0]$971 + end + connect \$9 $and$issuer_ls180.v:30556$961_Y + connect \$11 $or$issuer_ls180.v:30557$962_Y + connect \$13 $not$issuer_ls180.v:30558$963_Y + connect \$15 $or$issuer_ls180.v:30559$964_Y + connect \$1 $not$issuer_ls180.v:30560$965_Y + connect \$3 $and$issuer_ls180.v:30561$966_Y + connect \$5 $or$issuer_ls180.v:30562$967_Y + connect \$7 $not$issuer_ls180.v:30563$968_Y + connect \qlq_alui \$15 + connect \qn_alui \$13 + connect \q_alui \$11 +end +attribute \src "issuer_ls180.v:30582.1-30640.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.fus.trap0.alui_l" +attribute \generator "nMigen" +module \alui_l$41 + attribute \src "issuer_ls180.v:30583.7-30583.20" + wire $0\initial[0:0] + attribute \src "issuer_ls180.v:30628.3-30636.6" + wire $0\q_int$next[0:0]$985 + attribute \src "issuer_ls180.v:30626.3-30627.27" + wire $0\q_int[0:0] + attribute \src "issuer_ls180.v:30628.3-30636.6" + wire $1\q_int$next[0:0]$986 + attribute \src "issuer_ls180.v:30607.7-30607.19" + wire $1\q_int[0:0] + attribute \src "issuer_ls180.v:30618.17-30618.96" + wire $and$issuer_ls180.v:30618$975_Y + attribute \src "issuer_ls180.v:30623.17-30623.96" + wire $and$issuer_ls180.v:30623$980_Y + attribute \src "issuer_ls180.v:30620.18-30620.94" + wire $not$issuer_ls180.v:30620$977_Y + attribute \src "issuer_ls180.v:30622.17-30622.93" + wire $not$issuer_ls180.v:30622$979_Y + attribute \src "issuer_ls180.v:30625.17-30625.93" + wire $not$issuer_ls180.v:30625$982_Y + attribute \src "issuer_ls180.v:30619.18-30619.99" + wire $or$issuer_ls180.v:30619$976_Y + attribute \src "issuer_ls180.v:30621.18-30621.100" + wire $or$issuer_ls180.v:30621$978_Y + attribute \src "issuer_ls180.v:30624.17-30624.98" + wire $or$issuer_ls180.v:30624$981_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire \$13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" + wire input 5 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" + wire input 1 \coresync_rst + attribute \src "issuer_ls180.v:30583.7-30583.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire output 2 \q_alui + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" + wire \qlq_alui + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + wire \qn_alui + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire input 3 \r_alui + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire input 4 \s_alui + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $and $and$issuer_ls180.v:30618$975 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$7 + connect \Y $and$issuer_ls180.v:30618$975_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $and $and$issuer_ls180.v:30623$980 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$1 + connect \Y $and$issuer_ls180.v:30623$980_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + cell $not $not$issuer_ls180.v:30620$977 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_alui + connect \Y $not$issuer_ls180.v:30620$977_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $not $not$issuer_ls180.v:30622$979 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_alui + connect \Y $not$issuer_ls180.v:30622$979_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $not $not$issuer_ls180.v:30625$982 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_alui + connect \Y $not$issuer_ls180.v:30625$982_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $or $or$issuer_ls180.v:30619$976 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$9 + connect \B \s_alui + connect \Y $or$issuer_ls180.v:30619$976_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + cell $or $or$issuer_ls180.v:30621$978 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_alui + connect \B \q_int + connect \Y $or$issuer_ls180.v:30621$978_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $or $or$issuer_ls180.v:30624$981 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$3 + connect \B \s_alui + connect \Y $or$issuer_ls180.v:30624$981_Y + end + attribute \src "issuer_ls180.v:30583.7-30583.20" + process $proc$issuer_ls180.v:30583$987 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "issuer_ls180.v:30607.7-30607.19" + process $proc$issuer_ls180.v:30607$988 + assign { } { } + assign $1\q_int[0:0] 1'0 + sync always + sync init + update \q_int $1\q_int[0:0] + end + attribute \src "issuer_ls180.v:30626.3-30627.27" + process $proc$issuer_ls180.v:30626$983 + assign { } { } + assign $0\q_int[0:0] \q_int$next + sync posedge \coresync_clk + update \q_int $0\q_int[0:0] + end + attribute \src "issuer_ls180.v:30628.3-30636.6" + process $proc$issuer_ls180.v:30628$984 + assign { } { } + assign { } { } + assign $0\q_int$next[0:0]$985 $1\q_int$next[0:0]$986 + attribute \src "issuer_ls180.v:30629.5-30629.29" + switch \initial + attribute \src "issuer_ls180.v:30629.9-30629.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\q_int$next[0:0]$986 1'0 + case + assign $1\q_int$next[0:0]$986 \$5 + end + sync always + update \q_int$next $0\q_int$next[0:0]$985 + end + connect \$9 $and$issuer_ls180.v:30618$975_Y + connect \$11 $or$issuer_ls180.v:30619$976_Y + connect \$13 $not$issuer_ls180.v:30620$977_Y + connect \$15 $or$issuer_ls180.v:30621$978_Y + connect \$1 $not$issuer_ls180.v:30622$979_Y + connect \$3 $and$issuer_ls180.v:30623$980_Y + connect \$5 $or$issuer_ls180.v:30624$981_Y + connect \$7 $not$issuer_ls180.v:30625$982_Y + connect \qlq_alui \$15 + connect \qn_alui \$13 + connect \q_alui \$11 +end +attribute \src "issuer_ls180.v:30644.1-30702.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.fus.logical0.alui_l" +attribute \generator "nMigen" +module \alui_l$57 + attribute \src "issuer_ls180.v:30645.7-30645.20" + wire $0\initial[0:0] + attribute \src "issuer_ls180.v:30690.3-30698.6" + wire $0\q_int$next[0:0]$999 + attribute \src "issuer_ls180.v:30688.3-30689.27" + wire $0\q_int[0:0] + attribute \src "issuer_ls180.v:30690.3-30698.6" + wire $1\q_int$next[0:0]$1000 + attribute \src "issuer_ls180.v:30669.7-30669.19" + wire $1\q_int[0:0] + attribute \src "issuer_ls180.v:30680.17-30680.96" + wire $and$issuer_ls180.v:30680$989_Y + attribute \src "issuer_ls180.v:30685.17-30685.96" + wire $and$issuer_ls180.v:30685$994_Y + attribute \src "issuer_ls180.v:30682.18-30682.94" + wire $not$issuer_ls180.v:30682$991_Y + attribute \src "issuer_ls180.v:30684.17-30684.93" + wire $not$issuer_ls180.v:30684$993_Y + attribute \src "issuer_ls180.v:30687.17-30687.93" + wire $not$issuer_ls180.v:30687$996_Y + attribute \src "issuer_ls180.v:30681.18-30681.99" + wire $or$issuer_ls180.v:30681$990_Y + attribute \src "issuer_ls180.v:30683.18-30683.100" + wire $or$issuer_ls180.v:30683$992_Y + attribute \src "issuer_ls180.v:30686.17-30686.98" + wire $or$issuer_ls180.v:30686$995_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire \$13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" + wire input 5 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" + wire input 1 \coresync_rst + attribute \src "issuer_ls180.v:30645.7-30645.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire output 2 \q_alui + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" + wire \qlq_alui + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + wire \qn_alui + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire input 3 \r_alui + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire input 4 \s_alui + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $and $and$issuer_ls180.v:30680$989 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$7 + connect \Y $and$issuer_ls180.v:30680$989_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $and $and$issuer_ls180.v:30685$994 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$1 + connect \Y $and$issuer_ls180.v:30685$994_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + cell $not $not$issuer_ls180.v:30682$991 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_alui + connect \Y $not$issuer_ls180.v:30682$991_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $not $not$issuer_ls180.v:30684$993 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_alui + connect \Y $not$issuer_ls180.v:30684$993_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $not $not$issuer_ls180.v:30687$996 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_alui + connect \Y $not$issuer_ls180.v:30687$996_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $or $or$issuer_ls180.v:30681$990 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$9 + connect \B \s_alui + connect \Y $or$issuer_ls180.v:30681$990_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + cell $or $or$issuer_ls180.v:30683$992 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_alui + connect \B \q_int + connect \Y $or$issuer_ls180.v:30683$992_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $or $or$issuer_ls180.v:30686$995 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$3 + connect \B \s_alui + connect \Y $or$issuer_ls180.v:30686$995_Y + end + attribute \src "issuer_ls180.v:30645.7-30645.20" + process $proc$issuer_ls180.v:30645$1001 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "issuer_ls180.v:30669.7-30669.19" + process $proc$issuer_ls180.v:30669$1002 + assign { } { } + assign $1\q_int[0:0] 1'0 + sync always + sync init + update \q_int $1\q_int[0:0] + end + attribute \src "issuer_ls180.v:30688.3-30689.27" + process $proc$issuer_ls180.v:30688$997 + assign { } { } + assign $0\q_int[0:0] \q_int$next + sync posedge \coresync_clk + update \q_int $0\q_int[0:0] + end + attribute \src "issuer_ls180.v:30690.3-30698.6" + process $proc$issuer_ls180.v:30690$998 + assign { } { } + assign { } { } + assign $0\q_int$next[0:0]$999 $1\q_int$next[0:0]$1000 + attribute \src "issuer_ls180.v:30691.5-30691.29" + switch \initial + attribute \src "issuer_ls180.v:30691.9-30691.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\q_int$next[0:0]$1000 1'0 + case + assign $1\q_int$next[0:0]$1000 \$5 + end + sync always + update \q_int$next $0\q_int$next[0:0]$999 + end + connect \$9 $and$issuer_ls180.v:30680$989_Y + connect \$11 $or$issuer_ls180.v:30681$990_Y + connect \$13 $not$issuer_ls180.v:30682$991_Y + connect \$15 $or$issuer_ls180.v:30683$992_Y + connect \$1 $not$issuer_ls180.v:30684$993_Y + connect \$3 $and$issuer_ls180.v:30685$994_Y + connect \$5 $or$issuer_ls180.v:30686$995_Y + connect \$7 $not$issuer_ls180.v:30687$996_Y + connect \qlq_alui \$15 + connect \qn_alui \$13 + connect \q_alui \$11 +end +attribute \src "issuer_ls180.v:30706.1-30764.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.fus.spr0.alui_l" +attribute \generator "nMigen" +module \alui_l$69 + attribute \src "issuer_ls180.v:30707.7-30707.20" + wire $0\initial[0:0] + attribute \src "issuer_ls180.v:30752.3-30760.6" + wire $0\q_int$next[0:0]$1013 + attribute \src "issuer_ls180.v:30750.3-30751.27" + wire $0\q_int[0:0] + attribute \src "issuer_ls180.v:30752.3-30760.6" + wire $1\q_int$next[0:0]$1014 + attribute \src "issuer_ls180.v:30731.7-30731.19" + wire $1\q_int[0:0] + attribute \src "issuer_ls180.v:30742.17-30742.96" + wire $and$issuer_ls180.v:30742$1003_Y + attribute \src "issuer_ls180.v:30747.17-30747.96" + wire $and$issuer_ls180.v:30747$1008_Y + attribute \src "issuer_ls180.v:30744.18-30744.94" + wire $not$issuer_ls180.v:30744$1005_Y + attribute \src "issuer_ls180.v:30746.17-30746.93" + wire $not$issuer_ls180.v:30746$1007_Y + attribute \src "issuer_ls180.v:30749.17-30749.93" + wire $not$issuer_ls180.v:30749$1010_Y + attribute \src "issuer_ls180.v:30743.18-30743.99" + wire $or$issuer_ls180.v:30743$1004_Y + attribute \src "issuer_ls180.v:30745.18-30745.100" + wire $or$issuer_ls180.v:30745$1006_Y + attribute \src "issuer_ls180.v:30748.17-30748.98" + wire $or$issuer_ls180.v:30748$1009_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire \$13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" + wire input 5 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" + wire input 1 \coresync_rst + attribute \src "issuer_ls180.v:30707.7-30707.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire output 2 \q_alui + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" + wire \qlq_alui + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + wire \qn_alui + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire input 3 \r_alui + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire input 4 \s_alui + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $and $and$issuer_ls180.v:30742$1003 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$7 + connect \Y $and$issuer_ls180.v:30742$1003_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $and $and$issuer_ls180.v:30747$1008 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$1 + connect \Y $and$issuer_ls180.v:30747$1008_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + cell $not $not$issuer_ls180.v:30744$1005 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_alui + connect \Y $not$issuer_ls180.v:30744$1005_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $not $not$issuer_ls180.v:30746$1007 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_alui + connect \Y $not$issuer_ls180.v:30746$1007_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $not $not$issuer_ls180.v:30749$1010 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_alui + connect \Y $not$issuer_ls180.v:30749$1010_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $or $or$issuer_ls180.v:30743$1004 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$9 + connect \B \s_alui + connect \Y $or$issuer_ls180.v:30743$1004_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + cell $or $or$issuer_ls180.v:30745$1006 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_alui + connect \B \q_int + connect \Y $or$issuer_ls180.v:30745$1006_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $or $or$issuer_ls180.v:30748$1009 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$3 + connect \B \s_alui + connect \Y $or$issuer_ls180.v:30748$1009_Y + end + attribute \src "issuer_ls180.v:30707.7-30707.20" + process $proc$issuer_ls180.v:30707$1015 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "issuer_ls180.v:30731.7-30731.19" + process $proc$issuer_ls180.v:30731$1016 + assign { } { } + assign $1\q_int[0:0] 1'0 + sync always + sync init + update \q_int $1\q_int[0:0] + end + attribute \src "issuer_ls180.v:30750.3-30751.27" + process $proc$issuer_ls180.v:30750$1011 + assign { } { } + assign $0\q_int[0:0] \q_int$next + sync posedge \coresync_clk + update \q_int $0\q_int[0:0] + end + attribute \src "issuer_ls180.v:30752.3-30760.6" + process $proc$issuer_ls180.v:30752$1012 + assign { } { } + assign { } { } + assign $0\q_int$next[0:0]$1013 $1\q_int$next[0:0]$1014 + attribute \src "issuer_ls180.v:30753.5-30753.29" + switch \initial + attribute \src "issuer_ls180.v:30753.9-30753.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\q_int$next[0:0]$1014 1'0 + case + assign $1\q_int$next[0:0]$1014 \$5 + end + sync always + update \q_int$next $0\q_int$next[0:0]$1013 + end + connect \$9 $and$issuer_ls180.v:30742$1003_Y + connect \$11 $or$issuer_ls180.v:30743$1004_Y + connect \$13 $not$issuer_ls180.v:30744$1005_Y + connect \$15 $or$issuer_ls180.v:30745$1006_Y + connect \$1 $not$issuer_ls180.v:30746$1007_Y + connect \$3 $and$issuer_ls180.v:30747$1008_Y + connect \$5 $or$issuer_ls180.v:30748$1009_Y + connect \$7 $not$issuer_ls180.v:30749$1010_Y + connect \qlq_alui \$15 + connect \qn_alui \$13 + connect \q_alui \$11 +end +attribute \src "issuer_ls180.v:30768.1-30826.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alui_l" +attribute \generator "nMigen" +module \alui_l$86 + attribute \src "issuer_ls180.v:30769.7-30769.20" + wire $0\initial[0:0] + attribute \src "issuer_ls180.v:30814.3-30822.6" + wire $0\q_int$next[0:0]$1027 + attribute \src "issuer_ls180.v:30812.3-30813.27" + wire $0\q_int[0:0] + attribute \src "issuer_ls180.v:30814.3-30822.6" + wire $1\q_int$next[0:0]$1028 + attribute \src "issuer_ls180.v:30793.7-30793.19" + wire $1\q_int[0:0] + attribute \src "issuer_ls180.v:30804.17-30804.96" + wire $and$issuer_ls180.v:30804$1017_Y + attribute \src "issuer_ls180.v:30809.17-30809.96" + wire $and$issuer_ls180.v:30809$1022_Y + attribute \src "issuer_ls180.v:30806.18-30806.94" + wire $not$issuer_ls180.v:30806$1019_Y + attribute \src "issuer_ls180.v:30808.17-30808.93" + wire $not$issuer_ls180.v:30808$1021_Y + attribute \src "issuer_ls180.v:30811.17-30811.93" + wire $not$issuer_ls180.v:30811$1024_Y + attribute \src "issuer_ls180.v:30805.18-30805.99" + wire $or$issuer_ls180.v:30805$1018_Y + attribute \src "issuer_ls180.v:30807.18-30807.100" + wire $or$issuer_ls180.v:30807$1020_Y + attribute \src "issuer_ls180.v:30810.17-30810.98" + wire $or$issuer_ls180.v:30810$1023_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire \$13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" + wire input 5 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" + wire input 1 \coresync_rst + attribute \src "issuer_ls180.v:30769.7-30769.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire output 2 \q_alui + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" + wire \qlq_alui + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + wire \qn_alui + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire input 3 \r_alui + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire input 4 \s_alui + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $and $and$issuer_ls180.v:30804$1017 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$7 + connect \Y $and$issuer_ls180.v:30804$1017_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $and $and$issuer_ls180.v:30809$1022 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$1 + connect \Y $and$issuer_ls180.v:30809$1022_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + cell $not $not$issuer_ls180.v:30806$1019 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_alui + connect \Y $not$issuer_ls180.v:30806$1019_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $not $not$issuer_ls180.v:30808$1021 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_alui + connect \Y $not$issuer_ls180.v:30808$1021_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $not $not$issuer_ls180.v:30811$1024 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_alui + connect \Y $not$issuer_ls180.v:30811$1024_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $or $or$issuer_ls180.v:30805$1018 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$9 + connect \B \s_alui + connect \Y $or$issuer_ls180.v:30805$1018_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + cell $or $or$issuer_ls180.v:30807$1020 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_alui + connect \B \q_int + connect \Y $or$issuer_ls180.v:30807$1020_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $or $or$issuer_ls180.v:30810$1023 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$3 + connect \B \s_alui + connect \Y $or$issuer_ls180.v:30810$1023_Y + end + attribute \src "issuer_ls180.v:30769.7-30769.20" + process $proc$issuer_ls180.v:30769$1029 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "issuer_ls180.v:30793.7-30793.19" + process $proc$issuer_ls180.v:30793$1030 + assign { } { } + assign $1\q_int[0:0] 1'0 + sync always + sync init + update \q_int $1\q_int[0:0] + end + attribute \src "issuer_ls180.v:30812.3-30813.27" + process $proc$issuer_ls180.v:30812$1025 + assign { } { } + assign $0\q_int[0:0] \q_int$next + sync posedge \coresync_clk + update \q_int $0\q_int[0:0] + end + attribute \src "issuer_ls180.v:30814.3-30822.6" + process $proc$issuer_ls180.v:30814$1026 + assign { } { } + assign { } { } + assign $0\q_int$next[0:0]$1027 $1\q_int$next[0:0]$1028 + attribute \src "issuer_ls180.v:30815.5-30815.29" + switch \initial + attribute \src "issuer_ls180.v:30815.9-30815.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\q_int$next[0:0]$1028 1'0 + case + assign $1\q_int$next[0:0]$1028 \$5 + end + sync always + update \q_int$next $0\q_int$next[0:0]$1027 + end + connect \$9 $and$issuer_ls180.v:30804$1017_Y + connect \$11 $or$issuer_ls180.v:30805$1018_Y + connect \$13 $not$issuer_ls180.v:30806$1019_Y + connect \$15 $or$issuer_ls180.v:30807$1020_Y + connect \$1 $not$issuer_ls180.v:30808$1021_Y + connect \$3 $and$issuer_ls180.v:30809$1022_Y + connect \$5 $or$issuer_ls180.v:30810$1023_Y + connect \$7 $not$issuer_ls180.v:30811$1024_Y + connect \qlq_alui \$15 + connect \qn_alui \$13 + connect \q_alui \$11 +end +attribute \src "issuer_ls180.v:30830.1-32174.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.fus.logical0.alu_logical0.logical_pipe1.main.bpermd" +attribute \generator "nMigen" +module \bpermd + attribute \src "issuer_ls180.v:30831.7-30831.20" + wire $0\initial[0:0] + attribute \src "issuer_ls180.v:31008.3-32099.6" + wire width 64 $0\perm[63:0] + attribute \src "issuer_ls180.v:31008.3-32099.6" + wire $10\perm[4:4] + attribute \src "issuer_ls180.v:31008.3-32099.6" + wire $11\perm[5:5] + attribute \src "issuer_ls180.v:31008.3-32099.6" + wire $12\perm[5:5] + attribute \src "issuer_ls180.v:31008.3-32099.6" + wire $13\perm[6:6] + attribute \src "issuer_ls180.v:31008.3-32099.6" + wire $14\perm[6:6] + attribute \src "issuer_ls180.v:31008.3-32099.6" + wire $15\perm[7:7] + attribute \src "issuer_ls180.v:31008.3-32099.6" + wire $16\perm[7:7] + attribute \src "issuer_ls180.v:31008.3-32099.6" + wire $1\perm[0:0] + attribute \src "issuer_ls180.v:31008.3-32099.6" + wire $2\perm[0:0] + attribute \src "issuer_ls180.v:31008.3-32099.6" + wire $3\perm[1:1] + attribute \src "issuer_ls180.v:31008.3-32099.6" + wire $4\perm[1:1] + attribute \src "issuer_ls180.v:31008.3-32099.6" + wire $5\perm[2:2] + attribute \src "issuer_ls180.v:31008.3-32099.6" + wire $6\perm[2:2] + attribute \src "issuer_ls180.v:31008.3-32099.6" + wire $7\perm[3:3] + attribute \src "issuer_ls180.v:31008.3-32099.6" + wire $8\perm[3:3] + attribute \src "issuer_ls180.v:31008.3-32099.6" + wire $9\perm[4:4] + attribute \src "issuer_ls180.v:31000.17-31000.104" + wire $lt$issuer_ls180.v:31000$1031_Y + attribute \src "issuer_ls180.v:31001.18-31001.105" + wire $lt$issuer_ls180.v:31001$1032_Y + attribute \src "issuer_ls180.v:31002.18-31002.105" + wire $lt$issuer_ls180.v:31002$1033_Y + attribute \src "issuer_ls180.v:31003.18-31003.105" + wire $lt$issuer_ls180.v:31003$1034_Y + attribute \src "issuer_ls180.v:31004.17-31004.104" + wire $lt$issuer_ls180.v:31004$1035_Y + attribute \src "issuer_ls180.v:31005.17-31005.104" + wire $lt$issuer_ls180.v:31005$1036_Y + attribute \src "issuer_ls180.v:31006.17-31006.104" + wire $lt$issuer_ls180.v:31006$1037_Y + attribute \src "issuer_ls180.v:31007.17-31007.104" + wire $lt$issuer_ls180.v:31007$1038_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69" + wire \$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69" + wire \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:67" + wire width 8 \idx_0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:67" + wire width 8 \idx_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:67" + wire width 8 \idx_2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:67" + wire width 8 \idx_3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:67" + wire width 8 \idx_4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:67" + wire width 8 \idx_5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:67" + wire width 8 \idx_6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:67" + wire width 8 \idx_7 + attribute \src "issuer_ls180.v:30831.7-30831.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:60" + wire width 64 \perm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:55" + wire width 64 output 2 \ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:56" + wire width 64 input 1 \rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" + wire \rb64_0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" + wire \rb64_1 + attribute \src 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"/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" + wire \rb64_2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" + wire \rb64_20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" + wire \rb64_21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" + wire \rb64_22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" + wire \rb64_23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" + wire \rb64_24 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" + wire \rb64_25 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" + wire \rb64_26 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" + wire \rb64_27 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" + wire \rb64_28 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" + wire \rb64_29 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" + wire \rb64_3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" + wire \rb64_30 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" + wire \rb64_31 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" + wire \rb64_32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" + wire \rb64_33 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" + wire \rb64_34 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" + wire \rb64_35 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" + wire \rb64_36 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" + wire \rb64_37 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" + wire \rb64_38 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" + wire \rb64_39 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" + wire \rb64_4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" + wire \rb64_40 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" + wire \rb64_41 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" + wire \rb64_42 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" + wire \rb64_43 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" + wire \rb64_44 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" + wire \rb64_45 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" + wire \rb64_46 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" + wire \rb64_47 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" + wire \rb64_48 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" + wire \rb64_49 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" + wire \rb64_5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" + wire \rb64_50 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" + wire \rb64_51 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" + wire \rb64_52 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" + wire \rb64_53 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" + wire \rb64_54 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" + wire \rb64_55 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" + wire \rb64_56 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" + wire \rb64_57 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" + wire \rb64_58 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" + wire \rb64_59 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" + wire \rb64_6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" + wire \rb64_60 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" + wire \rb64_61 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" + wire \rb64_62 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" + wire \rb64_63 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" + wire \rb64_7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" + wire \rb64_8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" + wire \rb64_9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:54" + wire width 64 input 3 \rs + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69" + cell $lt $lt$issuer_ls180.v:31000$1031 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \idx_4 + connect \B 7'1000000 + connect \Y $lt$issuer_ls180.v:31000$1031_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69" + cell $lt $lt$issuer_ls180.v:31001$1032 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \idx_5 + connect \B 7'1000000 + connect \Y $lt$issuer_ls180.v:31001$1032_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69" + cell $lt $lt$issuer_ls180.v:31002$1033 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \idx_6 + connect \B 7'1000000 + connect \Y $lt$issuer_ls180.v:31002$1033_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69" + cell $lt $lt$issuer_ls180.v:31003$1034 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \idx_7 + connect \B 7'1000000 + connect \Y $lt$issuer_ls180.v:31003$1034_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69" + cell $lt $lt$issuer_ls180.v:31004$1035 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \idx_0 + connect \B 7'1000000 + connect \Y $lt$issuer_ls180.v:31004$1035_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69" + cell $lt $lt$issuer_ls180.v:31005$1036 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \idx_1 + connect \B 7'1000000 + connect \Y $lt$issuer_ls180.v:31005$1036_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69" + cell $lt $lt$issuer_ls180.v:31006$1037 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \idx_2 + connect \B 7'1000000 + connect \Y $lt$issuer_ls180.v:31006$1037_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69" + cell $lt $lt$issuer_ls180.v:31007$1038 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \idx_3 + connect \B 7'1000000 + connect \Y $lt$issuer_ls180.v:31007$1038_Y + end + attribute \src "issuer_ls180.v:30831.7-30831.20" + process $proc$issuer_ls180.v:30831$1040 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "issuer_ls180.v:31008.3-32099.6" + process $proc$issuer_ls180.v:31008$1039 + assign { } { } + assign $0\perm[63:0] [63:8] 56'00000000000000000000000000000000000000000000000000000000 + assign $0\perm[63:0] [0] $1\perm[0:0] + assign $0\perm[63:0] [1] $3\perm[1:1] + assign $0\perm[63:0] [2] $5\perm[2:2] + assign $0\perm[63:0] [3] $7\perm[3:3] + assign $0\perm[63:0] [4] $9\perm[4:4] + assign $0\perm[63:0] [5] $11\perm[5:5] + assign $0\perm[63:0] [6] $13\perm[6:6] + assign $0\perm[63:0] [7] $15\perm[7:7] + attribute \src "issuer_ls180.v:31009.5-31009.29" + switch \initial + attribute \src "issuer_ls180.v:31009.9-31009.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69" + switch \$1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\perm[0:0] $2\perm[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:70" + switch \idx_0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00000000 + assign { } { } + assign $2\perm[0:0] \rb64_0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00000001 + assign { } { } + assign $2\perm[0:0] \rb64_1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00000010 + assign { } { } + assign $2\perm[0:0] \rb64_2 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00000011 + assign { } { } + assign $2\perm[0:0] \rb64_3 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00000100 + assign { } { } + assign $2\perm[0:0] \rb64_4 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00000101 + assign { } { } + assign $2\perm[0:0] \rb64_5 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00000110 + assign { } { } + assign $2\perm[0:0] \rb64_6 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00000111 + assign { } { } + assign $2\perm[0:0] \rb64_7 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00001000 + assign { } { } + assign $2\perm[0:0] \rb64_8 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00001001 + assign { } { } + assign $2\perm[0:0] \rb64_9 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00001010 + assign { } { } + assign $2\perm[0:0] \rb64_10 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00001011 + assign { } { } + assign $2\perm[0:0] \rb64_11 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00001100 + assign { } { } + assign $2\perm[0:0] \rb64_12 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00001101 + assign { } { } + assign $2\perm[0:0] \rb64_13 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00001110 + assign { } { } + assign $2\perm[0:0] \rb64_14 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00001111 + assign { } { } + assign $2\perm[0:0] \rb64_15 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00010000 + assign { } { } + assign $2\perm[0:0] \rb64_16 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00010001 + assign { } { } + assign $2\perm[0:0] \rb64_17 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00010010 + assign { } { } + assign $2\perm[0:0] \rb64_18 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00010011 + assign { } { } + assign $2\perm[0:0] \rb64_19 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00010100 + assign { } { } + assign $2\perm[0:0] \rb64_20 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00010101 + assign { } { } + assign $2\perm[0:0] \rb64_21 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00010110 + assign { } { } + assign $2\perm[0:0] \rb64_22 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00010111 + assign { } { } + assign $2\perm[0:0] \rb64_23 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00011000 + assign { } { } + assign $2\perm[0:0] \rb64_24 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00011001 + assign { } { } + assign $2\perm[0:0] \rb64_25 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00011010 + assign { } { } + assign $2\perm[0:0] \rb64_26 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00011011 + assign { } { } + assign $2\perm[0:0] \rb64_27 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00011100 + assign { } { } + assign $2\perm[0:0] \rb64_28 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00011101 + assign { } { } + assign $2\perm[0:0] \rb64_29 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00011110 + assign { } { } + assign $2\perm[0:0] \rb64_30 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00011111 + assign { } { } + assign $2\perm[0:0] \rb64_31 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00100000 + assign { } { } + assign $2\perm[0:0] \rb64_32 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00100001 + assign { } { } + assign $2\perm[0:0] \rb64_33 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00100010 + assign { } { } + assign $2\perm[0:0] \rb64_34 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00100011 + assign { } { } + assign $2\perm[0:0] \rb64_35 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00100100 + assign { } { } + assign $2\perm[0:0] \rb64_36 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00100101 + assign { } { } + assign $2\perm[0:0] \rb64_37 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00100110 + assign { } { } + assign $2\perm[0:0] \rb64_38 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00100111 + assign { } { } + assign $2\perm[0:0] \rb64_39 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00101000 + assign { } { } + assign $2\perm[0:0] \rb64_40 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00101001 + assign { } { } + assign $2\perm[0:0] \rb64_41 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00101010 + assign { } { } + assign $2\perm[0:0] \rb64_42 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00101011 + assign { } { } + assign $2\perm[0:0] \rb64_43 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00101100 + assign { } { } + assign $2\perm[0:0] \rb64_44 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00101101 + assign { } { } + assign $2\perm[0:0] \rb64_45 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00101110 + assign { } { } + assign $2\perm[0:0] \rb64_46 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00101111 + assign { } { } + assign $2\perm[0:0] \rb64_47 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00110000 + assign { } { } + assign $2\perm[0:0] \rb64_48 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00110001 + assign { } { } + assign $2\perm[0:0] \rb64_49 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00110010 + assign { } { } + assign $2\perm[0:0] \rb64_50 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00110011 + assign { } { } + assign $2\perm[0:0] \rb64_51 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00110100 + assign { } { } + assign $2\perm[0:0] \rb64_52 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00110101 + assign { } { } + assign $2\perm[0:0] \rb64_53 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00110110 + assign { } { } + assign $2\perm[0:0] \rb64_54 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00110111 + assign { } { } + assign $2\perm[0:0] \rb64_55 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00111000 + assign { } { } + assign $2\perm[0:0] \rb64_56 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00111001 + assign { } { } + assign $2\perm[0:0] \rb64_57 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00111010 + assign { } { } + assign $2\perm[0:0] \rb64_58 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00111011 + assign { } { } + assign $2\perm[0:0] \rb64_59 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00111100 + assign { } { } + assign $2\perm[0:0] \rb64_60 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00111101 + assign { } { } + assign $2\perm[0:0] \rb64_61 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00111110 + assign { } { } + assign $2\perm[0:0] \rb64_62 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'-------- + assign { } { } + assign $2\perm[0:0] \rb64_63 + case + assign $2\perm[0:0] 1'0 + end + case + assign $1\perm[0:0] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69" + switch \$3 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\perm[1:1] $4\perm[1:1] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:70" + switch \idx_1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00000000 + assign { } { } + assign $4\perm[1:1] \rb64_0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00000001 + assign { } { } + assign $4\perm[1:1] \rb64_1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00000010 + assign { } { } + assign $4\perm[1:1] \rb64_2 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00000011 + assign { } { } + assign $4\perm[1:1] \rb64_3 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00000100 + assign { } { } + assign $4\perm[1:1] \rb64_4 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00000101 + assign { } { } + assign $4\perm[1:1] \rb64_5 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00000110 + assign { } { } + assign $4\perm[1:1] \rb64_6 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00000111 + assign { } { } + assign $4\perm[1:1] \rb64_7 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00001000 + assign { } { } + assign $4\perm[1:1] \rb64_8 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00001001 + assign { } { } + assign $4\perm[1:1] \rb64_9 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00001010 + assign { } { } + assign $4\perm[1:1] \rb64_10 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00001011 + assign { } { } + assign $4\perm[1:1] \rb64_11 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00001100 + assign { } { } + assign $4\perm[1:1] \rb64_12 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00001101 + assign { } { } + assign $4\perm[1:1] \rb64_13 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00001110 + assign { } { } + assign $4\perm[1:1] \rb64_14 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00001111 + assign { } { } + assign $4\perm[1:1] \rb64_15 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00010000 + assign { } { } + assign $4\perm[1:1] \rb64_16 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00010001 + assign { } { } + assign $4\perm[1:1] \rb64_17 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00010010 + assign { } { } + assign $4\perm[1:1] \rb64_18 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00010011 + assign { } { } + assign $4\perm[1:1] \rb64_19 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00010100 + assign { } { } + assign $4\perm[1:1] \rb64_20 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00010101 + assign { } { } + assign $4\perm[1:1] \rb64_21 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00010110 + assign { } { } + assign $4\perm[1:1] \rb64_22 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00010111 + assign { } { } + assign $4\perm[1:1] \rb64_23 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00011000 + assign { } { } + assign $4\perm[1:1] \rb64_24 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00011001 + assign { } { } + assign $4\perm[1:1] \rb64_25 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00011010 + assign { } { } + assign $4\perm[1:1] \rb64_26 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00011011 + assign { } { } + assign $4\perm[1:1] \rb64_27 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00011100 + assign { } { } + assign $4\perm[1:1] \rb64_28 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00011101 + assign { } { } + assign $4\perm[1:1] \rb64_29 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00011110 + assign { } { } + assign $4\perm[1:1] \rb64_30 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00011111 + assign { } { } + assign $4\perm[1:1] \rb64_31 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00100000 + assign { } { } + assign $4\perm[1:1] \rb64_32 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00100001 + assign { } { } + assign $4\perm[1:1] \rb64_33 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00100010 + assign { } { } + assign $4\perm[1:1] \rb64_34 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00100011 + assign { } { } + assign $4\perm[1:1] \rb64_35 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00100100 + assign { } { } + assign $4\perm[1:1] \rb64_36 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00100101 + assign { } { } + assign $4\perm[1:1] \rb64_37 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00100110 + assign { } { } + assign $4\perm[1:1] \rb64_38 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00100111 + assign { } { } + assign $4\perm[1:1] \rb64_39 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00101000 + assign { } { } + assign $4\perm[1:1] \rb64_40 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00101001 + assign { } { } + assign $4\perm[1:1] \rb64_41 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00101010 + assign { } { } + assign $4\perm[1:1] \rb64_42 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00101011 + assign { } { } + assign $4\perm[1:1] \rb64_43 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00101100 + assign { } { } + assign $4\perm[1:1] \rb64_44 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00101101 + assign { } { } + assign $4\perm[1:1] \rb64_45 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00101110 + assign { } { } + assign $4\perm[1:1] \rb64_46 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00101111 + assign { } { } + assign $4\perm[1:1] \rb64_47 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00110000 + assign { } { } + assign $4\perm[1:1] \rb64_48 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00110001 + assign { } { } + assign $4\perm[1:1] \rb64_49 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00110010 + assign { } { } + assign $4\perm[1:1] \rb64_50 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00110011 + assign { } { } + assign $4\perm[1:1] \rb64_51 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00110100 + assign { } { } + assign $4\perm[1:1] \rb64_52 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00110101 + assign { } { } + assign $4\perm[1:1] \rb64_53 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00110110 + assign { } { } + assign $4\perm[1:1] \rb64_54 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00110111 + assign { } { } + assign $4\perm[1:1] \rb64_55 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00111000 + assign { } { } + assign $4\perm[1:1] \rb64_56 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00111001 + assign { } { } + assign $4\perm[1:1] \rb64_57 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00111010 + assign { } { } + assign $4\perm[1:1] \rb64_58 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00111011 + assign { } { } + assign $4\perm[1:1] \rb64_59 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00111100 + assign { } { } + assign $4\perm[1:1] \rb64_60 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00111101 + assign { } { } + assign $4\perm[1:1] \rb64_61 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00111110 + assign { } { } + assign $4\perm[1:1] \rb64_62 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'-------- + assign { } { } + assign $4\perm[1:1] \rb64_63 + case + assign $4\perm[1:1] 1'0 + end + case + assign $3\perm[1:1] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69" + switch \$5 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\perm[2:2] $6\perm[2:2] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:70" + switch \idx_2 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00000000 + assign { } { } + assign $6\perm[2:2] \rb64_0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00000001 + assign { } { } + assign $6\perm[2:2] \rb64_1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00000010 + assign { } { } + assign $6\perm[2:2] \rb64_2 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00000011 + assign { } { } + assign $6\perm[2:2] \rb64_3 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00000100 + assign { } { } + assign $6\perm[2:2] \rb64_4 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00000101 + assign { } { } + assign $6\perm[2:2] \rb64_5 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00000110 + assign { } { } + assign $6\perm[2:2] \rb64_6 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00000111 + assign { } { } + assign $6\perm[2:2] \rb64_7 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00001000 + assign { } { } + assign $6\perm[2:2] \rb64_8 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00001001 + assign { } { } + assign $6\perm[2:2] \rb64_9 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00001010 + assign { } { } + assign $6\perm[2:2] \rb64_10 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00001011 + assign { } { } + assign $6\perm[2:2] \rb64_11 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00001100 + assign { } { } + assign $6\perm[2:2] \rb64_12 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00001101 + assign { } { } + assign $6\perm[2:2] \rb64_13 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00001110 + assign { } { } + assign $6\perm[2:2] \rb64_14 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00001111 + assign { } { } + assign $6\perm[2:2] \rb64_15 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00010000 + assign { } { } + assign $6\perm[2:2] \rb64_16 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00010001 + assign { } { } + assign $6\perm[2:2] \rb64_17 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00010010 + assign { } { } + assign $6\perm[2:2] \rb64_18 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00010011 + assign { } { } + assign $6\perm[2:2] \rb64_19 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00010100 + assign { } { } + assign $6\perm[2:2] \rb64_20 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00010101 + assign { } { } + assign $6\perm[2:2] \rb64_21 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00010110 + assign { } { } + assign $6\perm[2:2] \rb64_22 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00010111 + assign { } { } + assign $6\perm[2:2] \rb64_23 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00011000 + assign { } { } + assign $6\perm[2:2] \rb64_24 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00011001 + assign { } { } + assign $6\perm[2:2] \rb64_25 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00011010 + assign { } { } + assign $6\perm[2:2] \rb64_26 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00011011 + assign { } { } + assign $6\perm[2:2] \rb64_27 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00011100 + assign { } { } + assign $6\perm[2:2] \rb64_28 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00011101 + assign { } { } + assign $6\perm[2:2] \rb64_29 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00011110 + assign { } { } + assign $6\perm[2:2] \rb64_30 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00011111 + assign { } { } + assign $6\perm[2:2] \rb64_31 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00100000 + assign { } { } + assign $6\perm[2:2] \rb64_32 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00100001 + assign { } { } + assign $6\perm[2:2] \rb64_33 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00100010 + assign { } { } + assign $6\perm[2:2] \rb64_34 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00100011 + assign { } { } + assign $6\perm[2:2] \rb64_35 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00100100 + assign { } { } + assign $6\perm[2:2] \rb64_36 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00100101 + assign { } { } + assign $6\perm[2:2] \rb64_37 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00100110 + assign { } { } + assign $6\perm[2:2] \rb64_38 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00100111 + assign { } { } + assign $6\perm[2:2] \rb64_39 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00101000 + assign { } { } + assign $6\perm[2:2] \rb64_40 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00101001 + assign { } { } + assign $6\perm[2:2] \rb64_41 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00101010 + assign { } { } + assign $6\perm[2:2] \rb64_42 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00101011 + assign { } { } + assign $6\perm[2:2] \rb64_43 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00101100 + assign { } { } + assign $6\perm[2:2] \rb64_44 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00101101 + assign { } { } + assign $6\perm[2:2] \rb64_45 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00101110 + assign { } { } + assign $6\perm[2:2] \rb64_46 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00101111 + assign { } { } + assign $6\perm[2:2] \rb64_47 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00110000 + assign { } { } + assign $6\perm[2:2] \rb64_48 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00110001 + assign { } { } + assign $6\perm[2:2] \rb64_49 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00110010 + assign { } { } + assign $6\perm[2:2] \rb64_50 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00110011 + assign { } { } + assign $6\perm[2:2] \rb64_51 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00110100 + assign { } { } + assign $6\perm[2:2] \rb64_52 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00110101 + assign { } { } + assign $6\perm[2:2] \rb64_53 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00110110 + assign { } { } + assign $6\perm[2:2] \rb64_54 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00110111 + assign { } { } + assign $6\perm[2:2] \rb64_55 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00111000 + assign { } { } + assign $6\perm[2:2] \rb64_56 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00111001 + assign { } { } + assign $6\perm[2:2] \rb64_57 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00111010 + assign { } { } + assign $6\perm[2:2] \rb64_58 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00111011 + assign { } { } + assign $6\perm[2:2] \rb64_59 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00111100 + assign { } { } + assign $6\perm[2:2] \rb64_60 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00111101 + assign { } { } + assign $6\perm[2:2] \rb64_61 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00111110 + assign { } { } + assign $6\perm[2:2] \rb64_62 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'-------- + assign { } { } + assign $6\perm[2:2] \rb64_63 + case + assign $6\perm[2:2] 1'0 + end + case + assign $5\perm[2:2] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69" + switch \$7 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $7\perm[3:3] $8\perm[3:3] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:70" + switch \idx_3 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00000000 + assign { } { } + assign $8\perm[3:3] \rb64_0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00000001 + assign { } { } + assign $8\perm[3:3] \rb64_1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00000010 + assign { } { } + assign $8\perm[3:3] \rb64_2 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00000011 + assign { } { } + assign $8\perm[3:3] \rb64_3 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00000100 + assign { } { } + assign $8\perm[3:3] \rb64_4 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00000101 + assign { } { } + assign $8\perm[3:3] \rb64_5 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00000110 + assign { } { } + assign $8\perm[3:3] \rb64_6 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00000111 + assign { } { } + assign $8\perm[3:3] \rb64_7 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00001000 + assign { } { } + assign $8\perm[3:3] \rb64_8 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00001001 + assign { } { } + assign $8\perm[3:3] \rb64_9 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00001010 + assign { } { } + assign $8\perm[3:3] \rb64_10 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00001011 + assign { } { } + assign $8\perm[3:3] \rb64_11 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00001100 + assign { } { } + assign $8\perm[3:3] \rb64_12 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00001101 + assign { } { } + assign $8\perm[3:3] \rb64_13 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00001110 + assign { } { } + assign $8\perm[3:3] \rb64_14 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00001111 + assign { } { } + assign $8\perm[3:3] \rb64_15 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00010000 + assign { } { } + assign $8\perm[3:3] \rb64_16 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00010001 + assign { } { } + assign $8\perm[3:3] \rb64_17 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00010010 + assign { } { } + assign $8\perm[3:3] \rb64_18 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00010011 + assign { } { } + assign $8\perm[3:3] \rb64_19 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00010100 + assign { } { } + assign $8\perm[3:3] \rb64_20 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00010101 + assign { } { } + assign $8\perm[3:3] \rb64_21 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00010110 + assign { } { } + assign $8\perm[3:3] \rb64_22 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00010111 + assign { } { } + assign $8\perm[3:3] \rb64_23 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00011000 + assign { } { } + assign $8\perm[3:3] \rb64_24 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00011001 + assign { } { } + assign $8\perm[3:3] \rb64_25 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00011010 + assign { } { } + assign $8\perm[3:3] \rb64_26 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00011011 + assign { } { } + assign $8\perm[3:3] \rb64_27 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00011100 + assign { } { } + assign $8\perm[3:3] \rb64_28 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00011101 + assign { } { } + assign $8\perm[3:3] \rb64_29 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00011110 + assign { } { } + assign $8\perm[3:3] \rb64_30 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00011111 + assign { } { } + assign $8\perm[3:3] \rb64_31 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00100000 + assign { } { } + assign $8\perm[3:3] \rb64_32 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00100001 + assign { } { } + assign $8\perm[3:3] \rb64_33 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00100010 + assign { } { } + assign $8\perm[3:3] \rb64_34 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00100011 + assign { } { } + assign $8\perm[3:3] \rb64_35 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00100100 + assign { } { } + assign $8\perm[3:3] \rb64_36 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00100101 + assign { } { } + assign $8\perm[3:3] \rb64_37 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00100110 + assign { } { } + assign $8\perm[3:3] \rb64_38 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00100111 + assign { } { } + assign $8\perm[3:3] \rb64_39 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00101000 + assign { } { } + assign $8\perm[3:3] \rb64_40 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00101001 + assign { } { } + assign $8\perm[3:3] \rb64_41 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00101010 + assign { } { } + assign $8\perm[3:3] \rb64_42 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00101011 + assign { } { } + assign $8\perm[3:3] \rb64_43 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00101100 + assign { } { } + assign $8\perm[3:3] \rb64_44 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00101101 + assign { } { } + assign $8\perm[3:3] \rb64_45 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00101110 + assign { } { } + assign $8\perm[3:3] \rb64_46 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00101111 + assign { } { } + assign $8\perm[3:3] \rb64_47 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00110000 + assign { } { } + assign $8\perm[3:3] \rb64_48 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00110001 + assign { } { } + assign $8\perm[3:3] \rb64_49 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00110010 + assign { } { } + assign $8\perm[3:3] \rb64_50 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00110011 + assign { } { } + assign $8\perm[3:3] \rb64_51 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00110100 + assign { } { } + assign $8\perm[3:3] \rb64_52 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00110101 + assign { } { } + assign $8\perm[3:3] \rb64_53 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00110110 + assign { } { } + assign $8\perm[3:3] \rb64_54 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00110111 + assign { } { } + assign $8\perm[3:3] \rb64_55 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00111000 + assign { } { } + assign $8\perm[3:3] \rb64_56 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00111001 + assign { } { } + assign $8\perm[3:3] \rb64_57 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00111010 + assign { } { } + assign $8\perm[3:3] \rb64_58 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00111011 + assign { } { } + assign $8\perm[3:3] \rb64_59 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00111100 + assign { } { } + assign $8\perm[3:3] \rb64_60 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00111101 + assign { } { } + assign $8\perm[3:3] \rb64_61 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00111110 + assign { } { } + assign $8\perm[3:3] \rb64_62 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'-------- + assign { } { } + assign $8\perm[3:3] \rb64_63 + case + assign $8\perm[3:3] 1'0 + end + case + assign $7\perm[3:3] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69" + switch \$9 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $9\perm[4:4] $10\perm[4:4] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:70" + switch \idx_4 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00000000 + assign { } { } + assign $10\perm[4:4] \rb64_0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00000001 + assign { } { } + assign $10\perm[4:4] \rb64_1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00000010 + assign { } { } + assign $10\perm[4:4] \rb64_2 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00000011 + assign { } { } + assign $10\perm[4:4] \rb64_3 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00000100 + assign { } { } + assign $10\perm[4:4] \rb64_4 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00000101 + assign { } { } + assign $10\perm[4:4] \rb64_5 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00000110 + assign { } { } + assign $10\perm[4:4] \rb64_6 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00000111 + assign { } { } + assign $10\perm[4:4] \rb64_7 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00001000 + assign { } { } + assign $10\perm[4:4] \rb64_8 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00001001 + assign { } { } + assign $10\perm[4:4] \rb64_9 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00001010 + assign { } { } + assign $10\perm[4:4] \rb64_10 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00001011 + assign { } { } + assign $10\perm[4:4] \rb64_11 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00001100 + assign { } { } + assign $10\perm[4:4] \rb64_12 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00001101 + assign { } { } + assign $10\perm[4:4] \rb64_13 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00001110 + assign { } { } + assign $10\perm[4:4] \rb64_14 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00001111 + assign { } { } + assign $10\perm[4:4] \rb64_15 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00010000 + assign { } { } + assign $10\perm[4:4] \rb64_16 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00010001 + assign { } { } + assign $10\perm[4:4] \rb64_17 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00010010 + assign { } { } + assign $10\perm[4:4] \rb64_18 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00010011 + assign { } { } + assign $10\perm[4:4] \rb64_19 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00010100 + assign { } { } + assign $10\perm[4:4] \rb64_20 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00010101 + assign { } { } + assign $10\perm[4:4] \rb64_21 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00010110 + assign { } { } + assign $10\perm[4:4] \rb64_22 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00010111 + assign { } { } + assign $10\perm[4:4] \rb64_23 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00011000 + assign { } { } + assign $10\perm[4:4] \rb64_24 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00011001 + assign { } { } + assign $10\perm[4:4] \rb64_25 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00011010 + assign { } { } + assign $10\perm[4:4] \rb64_26 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00011011 + assign { } { } + assign $10\perm[4:4] \rb64_27 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00011100 + assign { } { } + assign $10\perm[4:4] \rb64_28 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00011101 + assign { } { } + assign $10\perm[4:4] \rb64_29 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00011110 + assign { } { } + assign $10\perm[4:4] \rb64_30 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00011111 + assign { } { } + assign $10\perm[4:4] \rb64_31 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00100000 + assign { } { } + assign $10\perm[4:4] \rb64_32 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00100001 + assign { } { } + assign $10\perm[4:4] \rb64_33 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00100010 + assign { } { } + assign $10\perm[4:4] \rb64_34 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00100011 + assign { } { } + assign $10\perm[4:4] \rb64_35 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00100100 + assign { } { } + assign $10\perm[4:4] \rb64_36 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00100101 + assign { } { } + assign $10\perm[4:4] \rb64_37 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00100110 + assign { } { } + assign $10\perm[4:4] \rb64_38 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00100111 + assign { } { } + assign $10\perm[4:4] \rb64_39 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00101000 + assign { } { } + assign $10\perm[4:4] \rb64_40 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00101001 + assign { } { } + assign $10\perm[4:4] \rb64_41 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00101010 + assign { } { } + assign $10\perm[4:4] \rb64_42 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00101011 + assign { } { } + assign $10\perm[4:4] \rb64_43 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00101100 + assign { } { } + assign $10\perm[4:4] \rb64_44 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00101101 + assign { } { } + assign $10\perm[4:4] \rb64_45 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00101110 + assign { } { } + assign $10\perm[4:4] \rb64_46 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00101111 + assign { } { } + assign $10\perm[4:4] \rb64_47 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00110000 + assign { } { } + assign $10\perm[4:4] \rb64_48 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00110001 + assign { } { } + assign $10\perm[4:4] \rb64_49 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00110010 + assign { } { } + assign $10\perm[4:4] \rb64_50 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00110011 + assign { } { } + assign $10\perm[4:4] \rb64_51 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00110100 + assign { } { } + assign $10\perm[4:4] \rb64_52 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00110101 + assign { } { } + assign $10\perm[4:4] \rb64_53 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00110110 + assign { } { } + assign $10\perm[4:4] \rb64_54 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00110111 + assign { } { } + assign $10\perm[4:4] \rb64_55 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00111000 + assign { } { } + assign $10\perm[4:4] \rb64_56 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00111001 + assign { } { } + assign $10\perm[4:4] \rb64_57 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00111010 + assign { } { } + assign $10\perm[4:4] \rb64_58 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00111011 + assign { } { } + assign $10\perm[4:4] \rb64_59 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00111100 + assign { } { } + assign $10\perm[4:4] \rb64_60 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00111101 + assign { } { } + assign $10\perm[4:4] \rb64_61 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00111110 + assign { } { } + assign $10\perm[4:4] \rb64_62 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'-------- + assign { } { } + assign $10\perm[4:4] \rb64_63 + case + assign $10\perm[4:4] 1'0 + end + case + assign $9\perm[4:4] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69" + switch \$11 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $11\perm[5:5] $12\perm[5:5] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:70" + switch \idx_5 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00000000 + assign { } { } + assign $12\perm[5:5] \rb64_0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00000001 + assign { } { } + assign $12\perm[5:5] \rb64_1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00000010 + assign { } { } + assign $12\perm[5:5] \rb64_2 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00000011 + assign { } { } + assign $12\perm[5:5] \rb64_3 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00000100 + assign { } { } + assign $12\perm[5:5] \rb64_4 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00000101 + assign { } { } + assign $12\perm[5:5] \rb64_5 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00000110 + assign { } { } + assign $12\perm[5:5] \rb64_6 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00000111 + assign { } { } + assign $12\perm[5:5] \rb64_7 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00001000 + assign { } { } + assign $12\perm[5:5] \rb64_8 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00001001 + assign { } { } + assign $12\perm[5:5] \rb64_9 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00001010 + assign { } { } + assign $12\perm[5:5] \rb64_10 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00001011 + assign { } { } + assign $12\perm[5:5] \rb64_11 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00001100 + assign { } { } + assign $12\perm[5:5] \rb64_12 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00001101 + assign { } { } + assign $12\perm[5:5] \rb64_13 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00001110 + assign { } { } + assign $12\perm[5:5] \rb64_14 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00001111 + assign { } { } + assign $12\perm[5:5] \rb64_15 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00010000 + assign { } { } + assign $12\perm[5:5] \rb64_16 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00010001 + assign { } { } + assign $12\perm[5:5] \rb64_17 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00010010 + assign { } { } + assign $12\perm[5:5] \rb64_18 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00010011 + assign { } { } + assign $12\perm[5:5] \rb64_19 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00010100 + assign { } { } + assign $12\perm[5:5] \rb64_20 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00010101 + assign { } { } + assign $12\perm[5:5] \rb64_21 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00010110 + assign { } { } + assign $12\perm[5:5] \rb64_22 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00010111 + assign { } { } + assign $12\perm[5:5] \rb64_23 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00011000 + assign { } { } + assign $12\perm[5:5] \rb64_24 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00011001 + assign { } { } + assign $12\perm[5:5] \rb64_25 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00011010 + assign { } { } + assign $12\perm[5:5] \rb64_26 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00011011 + assign { } { } + assign $12\perm[5:5] \rb64_27 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00011100 + assign { } { } + assign $12\perm[5:5] \rb64_28 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00011101 + assign { } { } + assign $12\perm[5:5] \rb64_29 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00011110 + assign { } { } + assign $12\perm[5:5] \rb64_30 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00011111 + assign { } { } + assign $12\perm[5:5] \rb64_31 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00100000 + assign { } { } + assign $12\perm[5:5] \rb64_32 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00100001 + assign { } { } + assign $12\perm[5:5] \rb64_33 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00100010 + assign { } { } + assign $12\perm[5:5] \rb64_34 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00100011 + assign { } { } + assign $12\perm[5:5] \rb64_35 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00100100 + assign { } { } + assign $12\perm[5:5] \rb64_36 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00100101 + assign { } { } + assign $12\perm[5:5] \rb64_37 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00100110 + assign { } { } + assign $12\perm[5:5] \rb64_38 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00100111 + assign { } { } + assign $12\perm[5:5] \rb64_39 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00101000 + assign { } { } + assign $12\perm[5:5] \rb64_40 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00101001 + assign { } { } + assign $12\perm[5:5] \rb64_41 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00101010 + assign { } { } + assign $12\perm[5:5] \rb64_42 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00101011 + assign { } { } + assign $12\perm[5:5] \rb64_43 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00101100 + assign { } { } + assign $12\perm[5:5] \rb64_44 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00101101 + assign { } { } + assign $12\perm[5:5] \rb64_45 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00101110 + assign { } { } + assign $12\perm[5:5] \rb64_46 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00101111 + assign { } { } + assign $12\perm[5:5] \rb64_47 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00110000 + assign { } { } + assign $12\perm[5:5] \rb64_48 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00110001 + assign { } { } + assign $12\perm[5:5] \rb64_49 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00110010 + assign { } { } + assign $12\perm[5:5] \rb64_50 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00110011 + assign { } { } + assign $12\perm[5:5] \rb64_51 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00110100 + assign { } { } + assign $12\perm[5:5] \rb64_52 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00110101 + assign { } { } + assign $12\perm[5:5] \rb64_53 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00110110 + assign { } { } + assign $12\perm[5:5] \rb64_54 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00110111 + assign { } { } + assign $12\perm[5:5] \rb64_55 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00111000 + assign { } { } + assign $12\perm[5:5] \rb64_56 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00111001 + assign { } { } + assign $12\perm[5:5] \rb64_57 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00111010 + assign { } { } + assign $12\perm[5:5] \rb64_58 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00111011 + assign { } { } + assign $12\perm[5:5] \rb64_59 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00111100 + assign { } { } + assign $12\perm[5:5] \rb64_60 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00111101 + assign { } { } + assign $12\perm[5:5] \rb64_61 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00111110 + assign { } { } + assign $12\perm[5:5] \rb64_62 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'-------- + assign { } { } + assign $12\perm[5:5] \rb64_63 + case + assign $12\perm[5:5] 1'0 + end + case + assign $11\perm[5:5] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69" + switch \$13 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $13\perm[6:6] $14\perm[6:6] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:70" + switch \idx_6 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00000000 + assign { } { } + assign $14\perm[6:6] \rb64_0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00000001 + assign { } { } + assign $14\perm[6:6] \rb64_1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00000010 + assign { } { } + assign $14\perm[6:6] \rb64_2 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00000011 + assign { } { } + assign $14\perm[6:6] \rb64_3 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00000100 + assign { } { } + assign $14\perm[6:6] \rb64_4 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00000101 + assign { } { } + assign $14\perm[6:6] \rb64_5 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00000110 + assign { } { } + assign $14\perm[6:6] \rb64_6 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00000111 + assign { } { } + assign $14\perm[6:6] \rb64_7 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00001000 + assign { } { } + assign $14\perm[6:6] \rb64_8 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00001001 + assign { } { } + assign $14\perm[6:6] \rb64_9 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00001010 + assign { } { } + assign $14\perm[6:6] \rb64_10 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00001011 + assign { } { } + assign $14\perm[6:6] \rb64_11 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00001100 + assign { } { } + assign $14\perm[6:6] \rb64_12 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00001101 + assign { } { } + assign $14\perm[6:6] \rb64_13 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00001110 + assign { } { } + assign $14\perm[6:6] \rb64_14 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00001111 + assign { } { } + assign $14\perm[6:6] \rb64_15 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00010000 + assign { } { } + assign $14\perm[6:6] \rb64_16 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00010001 + assign { } { } + assign $14\perm[6:6] \rb64_17 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00010010 + assign { } { } + assign $14\perm[6:6] \rb64_18 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00010011 + assign { } { } + assign $14\perm[6:6] \rb64_19 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00010100 + assign { } { } + assign $14\perm[6:6] \rb64_20 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00010101 + assign { } { } + assign $14\perm[6:6] \rb64_21 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00010110 + assign { } { } + assign $14\perm[6:6] \rb64_22 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00010111 + assign { } { } + assign $14\perm[6:6] \rb64_23 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00011000 + assign { } { } + assign $14\perm[6:6] \rb64_24 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00011001 + assign { } { } + assign $14\perm[6:6] \rb64_25 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00011010 + assign { } { } + assign $14\perm[6:6] \rb64_26 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00011011 + assign { } { } + assign $14\perm[6:6] \rb64_27 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00011100 + assign { } { } + assign $14\perm[6:6] \rb64_28 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00011101 + assign { } { } + assign $14\perm[6:6] \rb64_29 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00011110 + assign { } { } + assign $14\perm[6:6] \rb64_30 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00011111 + assign { } { } + assign $14\perm[6:6] \rb64_31 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00100000 + assign { } { } + assign $14\perm[6:6] \rb64_32 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00100001 + assign { } { } + assign $14\perm[6:6] \rb64_33 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00100010 + assign { } { } + assign $14\perm[6:6] \rb64_34 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00100011 + assign { } { } + assign $14\perm[6:6] \rb64_35 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00100100 + assign { } { } + assign $14\perm[6:6] \rb64_36 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00100101 + assign { } { } + assign $14\perm[6:6] \rb64_37 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00100110 + assign { } { } + assign $14\perm[6:6] \rb64_38 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00100111 + assign { } { } + assign $14\perm[6:6] \rb64_39 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00101000 + assign { } { } + assign $14\perm[6:6] \rb64_40 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00101001 + assign { } { } + assign $14\perm[6:6] \rb64_41 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00101010 + assign { } { } + assign $14\perm[6:6] \rb64_42 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00101011 + assign { } { } + assign $14\perm[6:6] \rb64_43 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00101100 + assign { } { } + assign $14\perm[6:6] \rb64_44 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00101101 + assign { } { } + assign $14\perm[6:6] \rb64_45 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00101110 + assign { } { } + assign $14\perm[6:6] \rb64_46 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00101111 + assign { } { } + assign $14\perm[6:6] \rb64_47 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00110000 + assign { } { } + assign $14\perm[6:6] \rb64_48 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00110001 + assign { } { } + assign $14\perm[6:6] \rb64_49 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00110010 + assign { } { } + assign $14\perm[6:6] \rb64_50 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00110011 + assign { } { } + assign $14\perm[6:6] \rb64_51 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00110100 + assign { } { } + assign $14\perm[6:6] \rb64_52 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00110101 + assign { } { } + assign $14\perm[6:6] \rb64_53 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00110110 + assign { } { } + assign $14\perm[6:6] \rb64_54 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00110111 + assign { } { } + assign $14\perm[6:6] \rb64_55 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00111000 + assign { } { } + assign $14\perm[6:6] \rb64_56 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00111001 + assign { } { } + assign $14\perm[6:6] \rb64_57 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00111010 + assign { } { } + assign $14\perm[6:6] \rb64_58 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00111011 + assign { } { } + assign $14\perm[6:6] \rb64_59 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00111100 + assign { } { } + assign $14\perm[6:6] \rb64_60 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00111101 + assign { } { } + assign $14\perm[6:6] \rb64_61 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00111110 + assign { } { } + assign $14\perm[6:6] \rb64_62 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'-------- + assign { } { } + assign $14\perm[6:6] \rb64_63 + case + assign $14\perm[6:6] 1'0 + end + case + assign $13\perm[6:6] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69" + switch \$15 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $15\perm[7:7] $16\perm[7:7] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:70" + switch \idx_7 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00000000 + assign { } { } + assign $16\perm[7:7] \rb64_0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00000001 + assign { } { } + assign $16\perm[7:7] \rb64_1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00000010 + assign { } { } + assign $16\perm[7:7] \rb64_2 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00000011 + assign { } { } + assign $16\perm[7:7] \rb64_3 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00000100 + assign { } { } + assign $16\perm[7:7] \rb64_4 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00000101 + assign { } { } + assign $16\perm[7:7] \rb64_5 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00000110 + assign { } { } + assign $16\perm[7:7] \rb64_6 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00000111 + assign { } { } + assign $16\perm[7:7] \rb64_7 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00001000 + assign { } { } + assign $16\perm[7:7] \rb64_8 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00001001 + assign { } { } + assign $16\perm[7:7] \rb64_9 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00001010 + assign { } { } + assign $16\perm[7:7] \rb64_10 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00001011 + assign { } { } + assign $16\perm[7:7] \rb64_11 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00001100 + assign { } { } + assign $16\perm[7:7] \rb64_12 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00001101 + assign { } { } + assign $16\perm[7:7] \rb64_13 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00001110 + assign { } { } + assign $16\perm[7:7] \rb64_14 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00001111 + assign { } { } + assign $16\perm[7:7] \rb64_15 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00010000 + assign { } { } + assign $16\perm[7:7] \rb64_16 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00010001 + assign { } { } + assign $16\perm[7:7] \rb64_17 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00010010 + assign { } { } + assign $16\perm[7:7] \rb64_18 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00010011 + assign { } { } + assign $16\perm[7:7] \rb64_19 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00010100 + assign { } { } + assign $16\perm[7:7] \rb64_20 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00010101 + assign { } { } + assign $16\perm[7:7] \rb64_21 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00010110 + assign { } { } + assign $16\perm[7:7] \rb64_22 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00010111 + assign { } { } + assign $16\perm[7:7] \rb64_23 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00011000 + assign { } { } + assign $16\perm[7:7] \rb64_24 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00011001 + assign { } { } + assign $16\perm[7:7] \rb64_25 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00011010 + assign { } { } + assign $16\perm[7:7] \rb64_26 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00011011 + assign { } { } + assign $16\perm[7:7] \rb64_27 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00011100 + assign { } { } + assign $16\perm[7:7] \rb64_28 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00011101 + assign { } { } + assign $16\perm[7:7] \rb64_29 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00011110 + assign { } { } + assign $16\perm[7:7] \rb64_30 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00011111 + assign { } { } + assign $16\perm[7:7] \rb64_31 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00100000 + assign { } { } + assign $16\perm[7:7] \rb64_32 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00100001 + assign { } { } + assign $16\perm[7:7] \rb64_33 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00100010 + assign { } { } + assign $16\perm[7:7] \rb64_34 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00100011 + assign { } { } + assign $16\perm[7:7] \rb64_35 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00100100 + assign { } { } + assign $16\perm[7:7] \rb64_36 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00100101 + assign { } { } + assign $16\perm[7:7] \rb64_37 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00100110 + assign { } { } + assign $16\perm[7:7] \rb64_38 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00100111 + assign { } { } + assign $16\perm[7:7] \rb64_39 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00101000 + assign { } { } + assign $16\perm[7:7] \rb64_40 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00101001 + assign { } { } + assign $16\perm[7:7] \rb64_41 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00101010 + assign { } { } + assign $16\perm[7:7] \rb64_42 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00101011 + assign { } { } + assign $16\perm[7:7] \rb64_43 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00101100 + assign { } { } + assign $16\perm[7:7] \rb64_44 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00101101 + assign { } { } + assign $16\perm[7:7] \rb64_45 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00101110 + assign { } { } + assign $16\perm[7:7] \rb64_46 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00101111 + assign { } { } + assign $16\perm[7:7] \rb64_47 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00110000 + assign { } { } + assign $16\perm[7:7] \rb64_48 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00110001 + assign { } { } + assign $16\perm[7:7] \rb64_49 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00110010 + assign { } { } + assign $16\perm[7:7] \rb64_50 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00110011 + assign { } { } + assign $16\perm[7:7] \rb64_51 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00110100 + assign { } { } + assign $16\perm[7:7] \rb64_52 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00110101 + assign { } { } + assign $16\perm[7:7] \rb64_53 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00110110 + assign { } { } + assign $16\perm[7:7] \rb64_54 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00110111 + assign { } { } + assign $16\perm[7:7] \rb64_55 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00111000 + assign { } { } + assign $16\perm[7:7] \rb64_56 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00111001 + assign { } { } + assign $16\perm[7:7] \rb64_57 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00111010 + assign { } { } + assign $16\perm[7:7] \rb64_58 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00111011 + assign { } { } + assign $16\perm[7:7] \rb64_59 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00111100 + assign { } { } + assign $16\perm[7:7] \rb64_60 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00111101 + assign { } { } + assign $16\perm[7:7] \rb64_61 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'00111110 + assign { } { } + assign $16\perm[7:7] \rb64_62 + attribute \src "issuer_ls180.v:0.0-0.0" + case 8'-------- + assign { } { } + assign $16\perm[7:7] \rb64_63 + case + assign $16\perm[7:7] 1'0 + end + case + assign $15\perm[7:7] 1'0 + end + sync always + update \perm $0\perm[63:0] + end + connect \$9 $lt$issuer_ls180.v:31000$1031_Y + connect \$11 $lt$issuer_ls180.v:31001$1032_Y + connect \$13 $lt$issuer_ls180.v:31002$1033_Y + connect \$15 $lt$issuer_ls180.v:31003$1034_Y + connect \$1 $lt$issuer_ls180.v:31004$1035_Y + connect \$3 $lt$issuer_ls180.v:31005$1036_Y + connect \$5 $lt$issuer_ls180.v:31006$1037_Y + connect \$7 $lt$issuer_ls180.v:31007$1038_Y + connect \ra [7:0] \perm [7:0] + connect \ra [63:8] 56'00000000000000000000000000000000000000000000000000000000 + connect \idx_7 \rs [63:56] + connect \idx_6 \rs [55:48] + connect \idx_5 \rs [47:40] + connect \idx_4 \rs [39:32] + connect \idx_3 \rs [31:24] + connect \idx_2 \rs [23:16] + connect \idx_1 \rs [15:8] + connect \idx_0 \rs [7:0] + connect \rb64_63 \rb [0] + connect \rb64_62 \rb [1] + connect \rb64_61 \rb [2] + connect \rb64_60 \rb [3] + connect \rb64_59 \rb [4] + connect \rb64_58 \rb [5] + connect \rb64_57 \rb [6] + connect \rb64_56 \rb [7] + connect \rb64_55 \rb [8] + connect \rb64_54 \rb [9] + connect \rb64_53 \rb [10] + connect \rb64_52 \rb [11] + connect \rb64_51 \rb [12] + connect \rb64_50 \rb [13] + connect \rb64_49 \rb [14] + connect \rb64_48 \rb [15] + connect \rb64_47 \rb [16] + connect \rb64_46 \rb [17] + connect \rb64_45 \rb [18] + connect \rb64_44 \rb [19] + connect \rb64_43 \rb [20] + connect \rb64_42 \rb [21] + connect \rb64_41 \rb [22] + connect \rb64_40 \rb [23] + connect \rb64_39 \rb [24] + connect \rb64_38 \rb [25] + connect \rb64_37 \rb [26] + connect \rb64_36 \rb [27] + connect \rb64_35 \rb [28] + connect \rb64_34 \rb [29] + connect \rb64_33 \rb [30] + connect \rb64_32 \rb [31] + connect \rb64_31 \rb [32] + connect \rb64_30 \rb [33] + connect \rb64_29 \rb [34] + connect \rb64_28 \rb [35] + connect \rb64_27 \rb [36] + connect \rb64_26 \rb [37] + connect \rb64_25 \rb [38] + connect \rb64_24 \rb [39] + connect \rb64_23 \rb [40] + connect \rb64_22 \rb [41] + connect \rb64_21 \rb [42] + connect \rb64_20 \rb [43] + connect \rb64_19 \rb [44] + connect \rb64_18 \rb [45] + connect \rb64_17 \rb [46] + connect \rb64_16 \rb [47] + connect \rb64_15 \rb [48] + connect \rb64_14 \rb [49] + connect \rb64_13 \rb [50] + connect \rb64_12 \rb [51] + connect \rb64_11 \rb [52] + connect \rb64_10 \rb [53] + connect \rb64_9 \rb [54] + connect \rb64_8 \rb [55] + connect \rb64_7 \rb [56] + connect \rb64_6 \rb [57] + connect \rb64_5 \rb [58] + connect \rb64_4 \rb [59] + connect \rb64_3 \rb [60] + connect \rb64_2 \rb [61] + connect \rb64_1 \rb [62] + connect \rb64_0 \rb [63] +end +attribute \src "issuer_ls180.v:32178.1-33227.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.fus.branch0" +attribute \generator "nMigen" +module \branch0 + attribute \src "issuer_ls180.v:32844.3-32845.25" + wire $0\all_rd_dly[0:0] + attribute \src "issuer_ls180.v:33019.3-33043.6" + wire width 64 $0\alu_branch0_br_op__cia$next[63:0]$1162 + attribute \src "issuer_ls180.v:32804.3-32805.61" + wire width 64 $0\alu_branch0_br_op__cia[63:0] + attribute \src "issuer_ls180.v:33019.3-33043.6" + wire width 12 $0\alu_branch0_br_op__fn_unit$next[11:0]$1163 + attribute \src "issuer_ls180.v:32808.3-32809.69" + wire width 12 $0\alu_branch0_br_op__fn_unit[11:0] + attribute \src "issuer_ls180.v:33019.3-33043.6" + wire width 64 $0\alu_branch0_br_op__imm_data__data$next[63:0]$1164 + attribute \src "issuer_ls180.v:32812.3-32813.83" + wire width 64 $0\alu_branch0_br_op__imm_data__data[63:0] + attribute \src "issuer_ls180.v:33019.3-33043.6" + wire $0\alu_branch0_br_op__imm_data__ok$next[0:0]$1165 + attribute \src "issuer_ls180.v:32814.3-32815.79" + wire $0\alu_branch0_br_op__imm_data__ok[0:0] + attribute \src "issuer_ls180.v:33019.3-33043.6" + wire width 32 $0\alu_branch0_br_op__insn$next[31:0]$1166 + attribute \src "issuer_ls180.v:32810.3-32811.63" + wire width 32 $0\alu_branch0_br_op__insn[31:0] + attribute \src "issuer_ls180.v:33019.3-33043.6" + wire width 7 $0\alu_branch0_br_op__insn_type$next[6:0]$1167 + attribute \src "issuer_ls180.v:32806.3-32807.73" + wire width 7 $0\alu_branch0_br_op__insn_type[6:0] + attribute \src "issuer_ls180.v:33019.3-33043.6" + wire $0\alu_branch0_br_op__is_32bit$next[0:0]$1168 + attribute \src "issuer_ls180.v:32818.3-32819.71" + wire $0\alu_branch0_br_op__is_32bit[0:0] + attribute \src "issuer_ls180.v:33019.3-33043.6" + wire $0\alu_branch0_br_op__lk$next[0:0]$1169 + attribute \src "issuer_ls180.v:32816.3-32817.59" + wire $0\alu_branch0_br_op__lk[0:0] + attribute \src "issuer_ls180.v:32842.3-32843.43" + wire $0\alu_done_dly[0:0] + attribute \src "issuer_ls180.v:33149.3-33157.6" + wire $0\alu_l_r_alu$next[0:0]$1217 + attribute \src "issuer_ls180.v:32782.3-32783.39" + wire $0\alu_l_r_alu[0:0] + attribute \src "issuer_ls180.v:33140.3-33148.6" + wire $0\alui_l_r_alui$next[0:0]$1214 + attribute \src "issuer_ls180.v:32784.3-32785.43" + wire $0\alui_l_r_alui[0:0] + attribute \src "issuer_ls180.v:33044.3-33065.6" + wire width 64 $0\data_r0__fast1$next[63:0]$1181 + attribute \src "issuer_ls180.v:32800.3-32801.45" + wire width 64 $0\data_r0__fast1[63:0] + attribute \src "issuer_ls180.v:33044.3-33065.6" + wire $0\data_r0__fast1_ok$next[0:0]$1182 + attribute \src "issuer_ls180.v:32802.3-32803.51" + wire $0\data_r0__fast1_ok[0:0] + attribute \src "issuer_ls180.v:33066.3-33087.6" + wire width 64 $0\data_r1__fast2$next[63:0]$1189 + attribute \src "issuer_ls180.v:32796.3-32797.45" + wire width 64 $0\data_r1__fast2[63:0] + attribute \src "issuer_ls180.v:33066.3-33087.6" + wire $0\data_r1__fast2_ok$next[0:0]$1190 + attribute \src "issuer_ls180.v:32798.3-32799.51" + wire $0\data_r1__fast2_ok[0:0] + attribute \src "issuer_ls180.v:33088.3-33109.6" + wire width 64 $0\data_r2__nia$next[63:0]$1197 + attribute \src "issuer_ls180.v:32792.3-32793.41" + wire width 64 $0\data_r2__nia[63:0] + attribute \src "issuer_ls180.v:33088.3-33109.6" + wire $0\data_r2__nia_ok$next[0:0]$1198 + attribute \src "issuer_ls180.v:32794.3-32795.47" + wire $0\data_r2__nia_ok[0:0] + attribute \src "issuer_ls180.v:33158.3-33167.6" + wire width 64 $0\dest1_o[63:0] + attribute \src "issuer_ls180.v:33168.3-33177.6" + wire width 64 $0\dest2_o[63:0] + attribute \src "issuer_ls180.v:33178.3-33187.6" + wire width 64 $0\dest3_o[63:0] + attribute \src "issuer_ls180.v:32179.7-32179.20" + wire $0\initial[0:0] + attribute \src "issuer_ls180.v:32974.3-32982.6" + wire $0\opc_l_r_opc$next[0:0]$1147 + attribute \src "issuer_ls180.v:32828.3-32829.39" + wire $0\opc_l_r_opc[0:0] + attribute \src "issuer_ls180.v:32965.3-32973.6" + wire $0\opc_l_s_opc$next[0:0]$1144 + attribute \src "issuer_ls180.v:32830.3-32831.39" + wire $0\opc_l_s_opc[0:0] + attribute \src "issuer_ls180.v:33188.3-33196.6" + wire width 3 $0\prev_wr_go$next[2:0]$1223 + attribute \src "issuer_ls180.v:32840.3-32841.37" + wire width 3 $0\prev_wr_go[2:0] + attribute \src "issuer_ls180.v:32919.3-32928.6" + wire $0\req_done[0:0] + attribute \src "issuer_ls180.v:33010.3-33018.6" + wire width 3 $0\req_l_r_req$next[2:0]$1159 + attribute \src "issuer_ls180.v:32820.3-32821.39" + wire width 3 $0\req_l_r_req[2:0] + attribute \src "issuer_ls180.v:33001.3-33009.6" + wire width 3 $0\req_l_s_req$next[2:0]$1156 + attribute \src "issuer_ls180.v:32822.3-32823.39" + wire width 3 $0\req_l_s_req[2:0] + attribute \src "issuer_ls180.v:32938.3-32946.6" + wire $0\rok_l_r_rdok$next[0:0]$1135 + attribute \src "issuer_ls180.v:32836.3-32837.41" + wire $0\rok_l_r_rdok[0:0] + attribute \src "issuer_ls180.v:32929.3-32937.6" + wire $0\rok_l_s_rdok$next[0:0]$1132 + attribute \src "issuer_ls180.v:32838.3-32839.41" + wire $0\rok_l_s_rdok[0:0] + attribute \src "issuer_ls180.v:32956.3-32964.6" + wire $0\rst_l_r_rst$next[0:0]$1141 + attribute \src "issuer_ls180.v:32832.3-32833.39" + wire $0\rst_l_r_rst[0:0] + attribute \src "issuer_ls180.v:32947.3-32955.6" + wire $0\rst_l_s_rst$next[0:0]$1138 + attribute \src "issuer_ls180.v:32834.3-32835.39" + wire $0\rst_l_s_rst[0:0] + attribute \src "issuer_ls180.v:32992.3-33000.6" + wire width 3 $0\src_l_r_src$next[2:0]$1153 + attribute \src "issuer_ls180.v:32824.3-32825.39" + wire width 3 $0\src_l_r_src[2:0] + attribute \src "issuer_ls180.v:32983.3-32991.6" + wire width 3 $0\src_l_s_src$next[2:0]$1150 + attribute \src "issuer_ls180.v:32826.3-32827.39" + wire width 3 $0\src_l_s_src[2:0] + attribute \src "issuer_ls180.v:33110.3-33119.6" + wire width 64 $0\src_r0$next[63:0]$1205 + attribute \src "issuer_ls180.v:32790.3-32791.29" + wire width 64 $0\src_r0[63:0] + attribute \src "issuer_ls180.v:33120.3-33129.6" + wire width 64 $0\src_r1$next[63:0]$1208 + attribute \src "issuer_ls180.v:32788.3-32789.29" + wire width 64 $0\src_r1[63:0] + attribute \src "issuer_ls180.v:33130.3-33139.6" + wire width 4 $0\src_r2$next[3:0]$1211 + attribute \src "issuer_ls180.v:32786.3-32787.29" + wire width 4 $0\src_r2[3:0] + attribute \src "issuer_ls180.v:32297.7-32297.24" + wire $1\all_rd_dly[0:0] + attribute \src "issuer_ls180.v:33019.3-33043.6" + wire width 64 $1\alu_branch0_br_op__cia$next[63:0]$1170 + attribute \src "issuer_ls180.v:32305.14-32305.59" + wire width 64 $1\alu_branch0_br_op__cia[63:0] + attribute \src "issuer_ls180.v:33019.3-33043.6" + wire width 12 $1\alu_branch0_br_op__fn_unit$next[11:0]$1171 + attribute \src "issuer_ls180.v:32322.14-32322.50" + wire width 12 $1\alu_branch0_br_op__fn_unit[11:0] + attribute \src "issuer_ls180.v:33019.3-33043.6" + wire width 64 $1\alu_branch0_br_op__imm_data__data$next[63:0]$1172 + attribute \src "issuer_ls180.v:32326.14-32326.70" + wire width 64 $1\alu_branch0_br_op__imm_data__data[63:0] + attribute \src "issuer_ls180.v:33019.3-33043.6" + wire $1\alu_branch0_br_op__imm_data__ok$next[0:0]$1173 + attribute \src "issuer_ls180.v:32330.7-32330.45" + wire $1\alu_branch0_br_op__imm_data__ok[0:0] + attribute \src "issuer_ls180.v:33019.3-33043.6" + wire width 32 $1\alu_branch0_br_op__insn$next[31:0]$1174 + attribute \src "issuer_ls180.v:32334.14-32334.45" + wire width 32 $1\alu_branch0_br_op__insn[31:0] + attribute \src "issuer_ls180.v:33019.3-33043.6" + wire width 7 $1\alu_branch0_br_op__insn_type$next[6:0]$1175 + attribute \src "issuer_ls180.v:32412.13-32412.49" + wire width 7 $1\alu_branch0_br_op__insn_type[6:0] + attribute \src "issuer_ls180.v:33019.3-33043.6" + wire $1\alu_branch0_br_op__is_32bit$next[0:0]$1176 + attribute \src "issuer_ls180.v:32416.7-32416.41" + wire $1\alu_branch0_br_op__is_32bit[0:0] + attribute \src "issuer_ls180.v:33019.3-33043.6" + wire $1\alu_branch0_br_op__lk$next[0:0]$1177 + attribute \src "issuer_ls180.v:32420.7-32420.35" + wire $1\alu_branch0_br_op__lk[0:0] + attribute \src "issuer_ls180.v:32446.7-32446.26" + wire $1\alu_done_dly[0:0] + attribute \src "issuer_ls180.v:33149.3-33157.6" + wire $1\alu_l_r_alu$next[0:0]$1218 + attribute \src "issuer_ls180.v:32454.7-32454.25" + wire $1\alu_l_r_alu[0:0] + attribute \src "issuer_ls180.v:33140.3-33148.6" + wire $1\alui_l_r_alui$next[0:0]$1215 + attribute \src "issuer_ls180.v:32466.7-32466.27" + wire $1\alui_l_r_alui[0:0] + attribute \src "issuer_ls180.v:33044.3-33065.6" + wire width 64 $1\data_r0__fast1$next[63:0]$1183 + attribute \src "issuer_ls180.v:32498.14-32498.51" + wire width 64 $1\data_r0__fast1[63:0] + attribute \src "issuer_ls180.v:33044.3-33065.6" + wire $1\data_r0__fast1_ok$next[0:0]$1184 + attribute \src "issuer_ls180.v:32502.7-32502.31" + wire $1\data_r0__fast1_ok[0:0] + attribute \src "issuer_ls180.v:33066.3-33087.6" + wire width 64 $1\data_r1__fast2$next[63:0]$1191 + attribute \src "issuer_ls180.v:32506.14-32506.51" + wire width 64 $1\data_r1__fast2[63:0] + attribute \src "issuer_ls180.v:33066.3-33087.6" + wire $1\data_r1__fast2_ok$next[0:0]$1192 + attribute \src "issuer_ls180.v:32510.7-32510.31" + wire $1\data_r1__fast2_ok[0:0] + attribute \src "issuer_ls180.v:33088.3-33109.6" + wire width 64 $1\data_r2__nia$next[63:0]$1199 + attribute \src "issuer_ls180.v:32514.14-32514.49" + wire width 64 $1\data_r2__nia[63:0] + attribute \src "issuer_ls180.v:33088.3-33109.6" + wire $1\data_r2__nia_ok$next[0:0]$1200 + attribute \src "issuer_ls180.v:32518.7-32518.29" + wire $1\data_r2__nia_ok[0:0] + attribute \src "issuer_ls180.v:33158.3-33167.6" + wire width 64 $1\dest1_o[63:0] + attribute \src "issuer_ls180.v:33168.3-33177.6" + wire width 64 $1\dest2_o[63:0] + attribute \src "issuer_ls180.v:33178.3-33187.6" + wire width 64 $1\dest3_o[63:0] + attribute \src "issuer_ls180.v:32974.3-32982.6" + wire $1\opc_l_r_opc$next[0:0]$1148 + attribute \src "issuer_ls180.v:32539.7-32539.25" + wire $1\opc_l_r_opc[0:0] + attribute \src "issuer_ls180.v:32965.3-32973.6" + wire $1\opc_l_s_opc$next[0:0]$1145 + attribute \src "issuer_ls180.v:32543.7-32543.25" + wire $1\opc_l_s_opc[0:0] + attribute \src "issuer_ls180.v:33188.3-33196.6" + wire width 3 $1\prev_wr_go$next[2:0]$1224 + attribute \src "issuer_ls180.v:32650.13-32650.30" + wire width 3 $1\prev_wr_go[2:0] + attribute \src "issuer_ls180.v:32919.3-32928.6" + wire $1\req_done[0:0] + attribute \src "issuer_ls180.v:33010.3-33018.6" + wire width 3 $1\req_l_r_req$next[2:0]$1160 + attribute \src "issuer_ls180.v:32658.13-32658.31" + wire width 3 $1\req_l_r_req[2:0] + attribute \src "issuer_ls180.v:33001.3-33009.6" + wire width 3 $1\req_l_s_req$next[2:0]$1157 + attribute \src "issuer_ls180.v:32662.13-32662.31" + wire width 3 $1\req_l_s_req[2:0] + attribute \src "issuer_ls180.v:32938.3-32946.6" + wire $1\rok_l_r_rdok$next[0:0]$1136 + attribute \src "issuer_ls180.v:32674.7-32674.26" + wire $1\rok_l_r_rdok[0:0] + attribute \src "issuer_ls180.v:32929.3-32937.6" + wire $1\rok_l_s_rdok$next[0:0]$1133 + attribute \src "issuer_ls180.v:32678.7-32678.26" + wire $1\rok_l_s_rdok[0:0] + attribute \src "issuer_ls180.v:32956.3-32964.6" + wire $1\rst_l_r_rst$next[0:0]$1142 + attribute \src "issuer_ls180.v:32682.7-32682.25" + wire $1\rst_l_r_rst[0:0] + attribute \src "issuer_ls180.v:32947.3-32955.6" + wire $1\rst_l_s_rst$next[0:0]$1139 + attribute \src "issuer_ls180.v:32686.7-32686.25" + wire $1\rst_l_s_rst[0:0] + attribute \src "issuer_ls180.v:32992.3-33000.6" + wire width 3 $1\src_l_r_src$next[2:0]$1154 + attribute \src "issuer_ls180.v:32700.13-32700.31" + wire width 3 $1\src_l_r_src[2:0] + attribute \src "issuer_ls180.v:32983.3-32991.6" + wire width 3 $1\src_l_s_src$next[2:0]$1151 + attribute \src "issuer_ls180.v:32704.13-32704.31" + wire width 3 $1\src_l_s_src[2:0] + attribute \src "issuer_ls180.v:33110.3-33119.6" + wire width 64 $1\src_r0$next[63:0]$1206 + attribute \src "issuer_ls180.v:32710.14-32710.43" + wire width 64 $1\src_r0[63:0] + attribute \src "issuer_ls180.v:33120.3-33129.6" + wire width 64 $1\src_r1$next[63:0]$1209 + attribute \src "issuer_ls180.v:32714.14-32714.43" + wire width 64 $1\src_r1[63:0] + attribute \src "issuer_ls180.v:33130.3-33139.6" + wire width 4 $1\src_r2$next[3:0]$1212 + attribute \src "issuer_ls180.v:32718.13-32718.26" + wire width 4 $1\src_r2[3:0] + attribute \src "issuer_ls180.v:33019.3-33043.6" + wire width 64 $2\alu_branch0_br_op__imm_data__data$next[63:0]$1178 + attribute \src "issuer_ls180.v:33019.3-33043.6" + wire $2\alu_branch0_br_op__imm_data__ok$next[0:0]$1179 + attribute \src "issuer_ls180.v:33044.3-33065.6" + wire width 64 $2\data_r0__fast1$next[63:0]$1185 + attribute \src "issuer_ls180.v:33044.3-33065.6" + wire $2\data_r0__fast1_ok$next[0:0]$1186 + attribute \src "issuer_ls180.v:33066.3-33087.6" + wire width 64 $2\data_r1__fast2$next[63:0]$1193 + attribute \src "issuer_ls180.v:33066.3-33087.6" + wire $2\data_r1__fast2_ok$next[0:0]$1194 + attribute \src "issuer_ls180.v:33088.3-33109.6" + wire width 64 $2\data_r2__nia$next[63:0]$1201 + attribute \src "issuer_ls180.v:33088.3-33109.6" + wire $2\data_r2__nia_ok$next[0:0]$1202 + attribute \src "issuer_ls180.v:33044.3-33065.6" + wire $3\data_r0__fast1_ok$next[0:0]$1187 + attribute \src "issuer_ls180.v:33066.3-33087.6" + wire $3\data_r1__fast2_ok$next[0:0]$1195 + attribute \src "issuer_ls180.v:33088.3-33109.6" + wire $3\data_r2__nia_ok$next[0:0]$1203 + attribute \src "issuer_ls180.v:32726.18-32726.112" + wire width 3 $and$issuer_ls180.v:32726$1042_Y + attribute \src "issuer_ls180.v:32727.19-32727.125" + wire $and$issuer_ls180.v:32727$1043_Y + attribute \src "issuer_ls180.v:32728.19-32728.125" + wire $and$issuer_ls180.v:32728$1044_Y + attribute \src "issuer_ls180.v:32729.19-32729.125" + wire $and$issuer_ls180.v:32729$1045_Y + attribute \src "issuer_ls180.v:32730.19-32730.141" + wire width 3 $and$issuer_ls180.v:32730$1046_Y + attribute \src "issuer_ls180.v:32731.19-32731.121" + wire width 3 $and$issuer_ls180.v:32731$1047_Y + attribute \src "issuer_ls180.v:32732.19-32732.127" + wire $and$issuer_ls180.v:32732$1048_Y + attribute \src "issuer_ls180.v:32733.19-32733.127" + wire $and$issuer_ls180.v:32733$1049_Y + attribute \src "issuer_ls180.v:32734.19-32734.127" + wire $and$issuer_ls180.v:32734$1050_Y + attribute \src "issuer_ls180.v:32735.18-32735.110" + wire $and$issuer_ls180.v:32735$1051_Y + attribute \src "issuer_ls180.v:32737.18-32737.98" + wire $and$issuer_ls180.v:32737$1053_Y + attribute \src "issuer_ls180.v:32739.18-32739.100" + wire $and$issuer_ls180.v:32739$1055_Y + attribute \src "issuer_ls180.v:32740.18-32740.149" + wire width 3 $and$issuer_ls180.v:32740$1056_Y + attribute \src "issuer_ls180.v:32742.18-32742.119" + wire width 3 $and$issuer_ls180.v:32742$1058_Y + attribute \src "issuer_ls180.v:32745.18-32745.116" + wire $and$issuer_ls180.v:32745$1061_Y + attribute \src "issuer_ls180.v:32749.17-32749.123" + wire $and$issuer_ls180.v:32749$1065_Y + attribute \src "issuer_ls180.v:32751.18-32751.113" + wire $and$issuer_ls180.v:32751$1067_Y + attribute \src "issuer_ls180.v:32752.18-32752.125" + wire width 3 $and$issuer_ls180.v:32752$1068_Y + attribute \src "issuer_ls180.v:32754.18-32754.112" + wire $and$issuer_ls180.v:32754$1070_Y + attribute \src "issuer_ls180.v:32756.18-32756.129" + wire $and$issuer_ls180.v:32756$1072_Y + attribute \src "issuer_ls180.v:32757.18-32757.129" + wire $and$issuer_ls180.v:32757$1073_Y + attribute \src "issuer_ls180.v:32758.18-32758.117" + wire $and$issuer_ls180.v:32758$1074_Y + attribute \src "issuer_ls180.v:32763.18-32763.133" + wire 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\B \alu_branch0_n_ready_i + connect \Y $and$issuer_ls180.v:32756$1072_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" + cell $and $and$issuer_ls180.v:32757$1073 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$51 + connect \B \alu_branch0_n_valid_o + connect \Y $and$issuer_ls180.v:32757$1073_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" + cell $and $and$issuer_ls180.v:32758$1074 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$53 + connect \B \cu_busy_o + connect \Y $and$issuer_ls180.v:32758$1074_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:237" + cell $and $and$issuer_ls180.v:32763$1079 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \alu_branch0_n_valid_o + connect \B \cu_busy_o + connect \Y $and$issuer_ls180.v:32763$1079_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:252" + cell $and $and$issuer_ls180.v:32764$1080 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \alu_pulsem + connect \B \cu_wrmask_o + connect \Y $and$issuer_ls180.v:32764$1080_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" + cell $and $and$issuer_ls180.v:32767$1083 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \fast1_ok + connect \B \cu_busy_o + connect \Y $and$issuer_ls180.v:32767$1083_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" + cell $and $and$issuer_ls180.v:32768$1084 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \fast2_ok + connect \B \cu_busy_o + connect \Y $and$issuer_ls180.v:32768$1084_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" + cell $and $and$issuer_ls180.v:32769$1085 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \nia_ok + connect \B \cu_busy_o + connect \Y $and$issuer_ls180.v:32769$1085_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:327" + cell $and $and$issuer_ls180.v:32775$1091 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \alu_branch0_p_ready_o + connect \B \alui_l_q_alui + connect \Y $and$issuer_ls180.v:32775$1091_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:334" + cell $and $and$issuer_ls180.v:32777$1093 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \alu_branch0_n_valid_o + connect \B \alu_l_q_alu + connect \Y $and$issuer_ls180.v:32777$1093_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" + cell $and $and$issuer_ls180.v:32778$1094 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \src_l_q_src + connect \B { \cu_busy_o \cu_busy_o \cu_busy_o } + connect \Y $and$issuer_ls180.v:32778$1094_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" + cell $and $and$issuer_ls180.v:32780$1096 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \$91 + connect \B { 1'1 \$93 1'1 } + connect \Y $and$issuer_ls180.v:32780$1096_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" + cell $eq $eq$issuer_ls180.v:32753$1069 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$43 + connect \B 1'0 + connect \Y $eq$issuer_ls180.v:32753$1069_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" + cell $eq $eq$issuer_ls180.v:32755$1071 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cu_wrmask_o + connect \B 1'0 + connect \Y $eq$issuer_ls180.v:32755$1071_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + cell $not $not$issuer_ls180.v:32736$1052 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \all_rd_dly + connect \Y $not$issuer_ls180.v:32736$1052_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + cell $not $not$issuer_ls180.v:32738$1054 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \alu_done_dly + connect \Y $not$issuer_ls180.v:32738$1054_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" + cell $not $not$issuer_ls180.v:32741$1057 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \cu_wrmask_o + connect \Y $not$issuer_ls180.v:32741$1057_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" + cell $not $not$issuer_ls180.v:32744$1060 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$24 + connect \Y $not$issuer_ls180.v:32744$1060_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" + cell $not $not$issuer_ls180.v:32750$1066 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \alu_branch0_n_ready_i + connect \Y $not$issuer_ls180.v:32750$1066_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" + cell $not $not$issuer_ls180.v:32765$1081 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \cu_rd__rel_o + connect \Y $not$issuer_ls180.v:32765$1081_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:173" + cell $not $not$issuer_ls180.v:32779$1095 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \alu_branch0_br_op__imm_data__ok + connect \Y $not$issuer_ls180.v:32779$1095_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" + cell $not $not$issuer_ls180.v:32781$1097 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \cu_rdmaskn_i + connect \Y $not$issuer_ls180.v:32781$1097_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" + cell $or $or$issuer_ls180.v:32748$1064 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$33 + connect \B \$35 + connect \Y $or$issuer_ls180.v:32748$1064_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:230" + cell $or $or$issuer_ls180.v:32759$1075 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \req_done + connect \B \cu_go_die_i + connect \Y $or$issuer_ls180.v:32759$1075_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:231" + cell $or $or$issuer_ls180.v:32760$1076 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cu_issue_i + connect \B \cu_go_die_i + connect \Y $or$issuer_ls180.v:32760$1076_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:232" + cell $or $or$issuer_ls180.v:32761$1077 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \cu_wr__go_i + connect \B { \cu_go_die_i \cu_go_die_i \cu_go_die_i } + connect \Y $or$issuer_ls180.v:32761$1077_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:233" + cell $or $or$issuer_ls180.v:32762$1078 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \cu_rd__go_i + connect \B { \cu_go_die_i \cu_go_die_i \cu_go_die_i } + connect \Y $or$issuer_ls180.v:32762$1078_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:253" + cell $or $or$issuer_ls180.v:32766$1082 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \reset_w + connect \B \prev_wr_go + connect \Y $or$issuer_ls180.v:32766$1082_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" + cell $or $or$issuer_ls180.v:32776$1092 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \$6 + connect \B \cu_rd__go_i + connect \Y $or$issuer_ls180.v:32776$1092_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" + cell $reduce_and $reduce_and$issuer_ls180.v:32725$1041 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \$8 + connect \Y $reduce_and$issuer_ls180.v:32725$1041_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" + cell $reduce_or $reduce_or$issuer_ls180.v:32743$1059 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \$27 + connect \Y $reduce_or$issuer_ls180.v:32743$1059_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" + cell $reduce_or $reduce_or$issuer_ls180.v:32746$1062 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \cu_wr__go_i + connect \Y $reduce_or$issuer_ls180.v:32746$1062_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" + cell $reduce_or $reduce_or$issuer_ls180.v:32747$1063 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \prev_wr_go + connect \Y $reduce_or$issuer_ls180.v:32747$1063_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:168" + cell $mux $ternary$issuer_ls180.v:32770$1086 + parameter \WIDTH 1 + connect \A \src_l_q_src [1] + connect \B \opc_l_q_opc + connect \S \alu_branch0_br_op__imm_data__ok + connect \Y $ternary$issuer_ls180.v:32770$1086_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:169" + cell $mux $ternary$issuer_ls180.v:32771$1087 + parameter \WIDTH 64 + connect \A \src2_i + connect \B \alu_branch0_br_op__imm_data__data + connect \S \alu_branch0_br_op__imm_data__ok + connect \Y $ternary$issuer_ls180.v:32771$1087_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + cell $mux $ternary$issuer_ls180.v:32772$1088 + parameter \WIDTH 64 + connect \A \src_r0 + connect \B \src1_i + connect \S \src_l_q_src [0] + connect \Y $ternary$issuer_ls180.v:32772$1088_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + cell $mux $ternary$issuer_ls180.v:32773$1089 + parameter \WIDTH 64 + connect \A \src_r1 + connect \B \src_or_imm + connect \S \src_sel + connect \Y $ternary$issuer_ls180.v:32773$1089_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + cell $mux $ternary$issuer_ls180.v:32774$1090 + parameter \WIDTH 4 + connect \A \src_r2 + connect \B \src3_i + connect \S \src_l_q_src [2] + connect \Y $ternary$issuer_ls180.v:32774$1090_Y + end + attribute \module_not_derived 1 + attribute \src "issuer_ls180.v:32846.15-32870.4" + cell \alu_branch0 \alu_branch0 + connect \br_op__cia \alu_branch0_br_op__cia + connect \br_op__fn_unit \alu_branch0_br_op__fn_unit + connect \br_op__imm_data__data \alu_branch0_br_op__imm_data__data + connect \br_op__imm_data__ok \alu_branch0_br_op__imm_data__ok + connect \br_op__insn \alu_branch0_br_op__insn + connect \br_op__insn_type \alu_branch0_br_op__insn_type + connect \br_op__is_32bit \alu_branch0_br_op__is_32bit + connect \br_op__lk \alu_branch0_br_op__lk + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \cr_a \alu_branch0_cr_a + connect \fast1 \alu_branch0_fast1 + connect \fast1$1 \alu_branch0_fast1$1 + connect \fast1_ok \fast1_ok + connect \fast2 \alu_branch0_fast2 + connect \fast2$2 \alu_branch0_fast2$2 + connect \fast2_ok \fast2_ok + connect \n_ready_i \alu_branch0_n_ready_i + connect \n_valid_o \alu_branch0_n_valid_o + connect \nia \alu_branch0_nia + connect \nia_ok \nia_ok + connect \p_ready_o \alu_branch0_p_ready_o + connect \p_valid_i \alu_branch0_p_valid_i + end + attribute \module_not_derived 1 + attribute \src "issuer_ls180.v:32871.14-32877.4" + cell \alu_l$29 \alu_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_alu \alu_l_q_alu + connect \r_alu \alu_l_r_alu + connect \s_alu \alu_l_s_alu + end + attribute \module_not_derived 1 + attribute \src "issuer_ls180.v:32878.15-32884.4" + cell \alui_l$28 \alui_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_alui \alui_l_q_alui + connect \r_alui \alui_l_r_alui + connect \s_alui \alui_l_s_alui + end + attribute \module_not_derived 1 + attribute \src "issuer_ls180.v:32885.14-32891.4" + cell \opc_l$24 \opc_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_opc \opc_l_q_opc + connect \r_opc \opc_l_r_opc + connect \s_opc \opc_l_s_opc + end + attribute \module_not_derived 1 + attribute \src "issuer_ls180.v:32892.14-32898.4" + cell \req_l$25 \req_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_req \req_l_q_req + connect \r_req \req_l_r_req + connect \s_req \req_l_s_req + end + attribute \module_not_derived 1 + attribute \src "issuer_ls180.v:32899.14-32905.4" + cell \rok_l$27 \rok_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_rdok \rok_l_q_rdok + connect \r_rdok \rok_l_r_rdok + connect \s_rdok \rok_l_s_rdok + end + attribute \module_not_derived 1 + attribute \src "issuer_ls180.v:32906.14-32911.4" + cell \rst_l$26 \rst_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \r_rst \rst_l_r_rst + connect \s_rst \rst_l_s_rst + end + attribute \module_not_derived 1 + attribute \src "issuer_ls180.v:32912.14-32918.4" + cell \src_l$23 \src_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_src \src_l_q_src + connect \r_src \src_l_r_src + connect \s_src \src_l_s_src + end + attribute \src "issuer_ls180.v:32179.7-32179.20" + process $proc$issuer_ls180.v:32179$1225 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "issuer_ls180.v:32297.7-32297.24" + process $proc$issuer_ls180.v:32297$1226 + assign { } { } + assign $1\all_rd_dly[0:0] 1'0 + sync always + sync init + update \all_rd_dly $1\all_rd_dly[0:0] + end + attribute \src "issuer_ls180.v:32305.14-32305.59" + process $proc$issuer_ls180.v:32305$1227 + assign { } { } + assign $1\alu_branch0_br_op__cia[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \alu_branch0_br_op__cia $1\alu_branch0_br_op__cia[63:0] + end + attribute \src "issuer_ls180.v:32322.14-32322.50" + process $proc$issuer_ls180.v:32322$1228 + assign { } { } + assign $1\alu_branch0_br_op__fn_unit[11:0] 12'000000000000 + sync always + sync init + update \alu_branch0_br_op__fn_unit $1\alu_branch0_br_op__fn_unit[11:0] + end + attribute \src "issuer_ls180.v:32326.14-32326.70" + process $proc$issuer_ls180.v:32326$1229 + assign { } { } + assign $1\alu_branch0_br_op__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \alu_branch0_br_op__imm_data__data $1\alu_branch0_br_op__imm_data__data[63:0] + end + attribute \src "issuer_ls180.v:32330.7-32330.45" + process $proc$issuer_ls180.v:32330$1230 + assign { } { } + assign $1\alu_branch0_br_op__imm_data__ok[0:0] 1'0 + sync always + sync init + update \alu_branch0_br_op__imm_data__ok $1\alu_branch0_br_op__imm_data__ok[0:0] + end + attribute \src "issuer_ls180.v:32334.14-32334.45" + process $proc$issuer_ls180.v:32334$1231 + assign { } { } + assign $1\alu_branch0_br_op__insn[31:0] 0 + sync always + sync init + update \alu_branch0_br_op__insn $1\alu_branch0_br_op__insn[31:0] + end + attribute \src "issuer_ls180.v:32412.13-32412.49" + process $proc$issuer_ls180.v:32412$1232 + assign { } { } + assign $1\alu_branch0_br_op__insn_type[6:0] 7'0000000 + sync always + sync init + update \alu_branch0_br_op__insn_type $1\alu_branch0_br_op__insn_type[6:0] + end + attribute \src "issuer_ls180.v:32416.7-32416.41" + process $proc$issuer_ls180.v:32416$1233 + assign { } { } + assign $1\alu_branch0_br_op__is_32bit[0:0] 1'0 + sync always + sync init + update \alu_branch0_br_op__is_32bit $1\alu_branch0_br_op__is_32bit[0:0] + end + attribute \src "issuer_ls180.v:32420.7-32420.35" + process $proc$issuer_ls180.v:32420$1234 + assign { } { } + assign $1\alu_branch0_br_op__lk[0:0] 1'0 + sync always + sync init + update \alu_branch0_br_op__lk $1\alu_branch0_br_op__lk[0:0] + end + attribute \src "issuer_ls180.v:32446.7-32446.26" + process $proc$issuer_ls180.v:32446$1235 + assign { } { } + assign $1\alu_done_dly[0:0] 1'0 + sync always + sync init + update \alu_done_dly $1\alu_done_dly[0:0] + end + attribute \src "issuer_ls180.v:32454.7-32454.25" + process $proc$issuer_ls180.v:32454$1236 + assign { } { } + assign $1\alu_l_r_alu[0:0] 1'1 + sync always + sync init + update \alu_l_r_alu $1\alu_l_r_alu[0:0] + end + attribute \src "issuer_ls180.v:32466.7-32466.27" + process $proc$issuer_ls180.v:32466$1237 + assign { } { } + assign $1\alui_l_r_alui[0:0] 1'1 + sync always + sync init + update \alui_l_r_alui $1\alui_l_r_alui[0:0] + end + attribute \src "issuer_ls180.v:32498.14-32498.51" + process $proc$issuer_ls180.v:32498$1238 + assign { } { } + assign $1\data_r0__fast1[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \data_r0__fast1 $1\data_r0__fast1[63:0] + end + attribute \src "issuer_ls180.v:32502.7-32502.31" + process $proc$issuer_ls180.v:32502$1239 + assign { } { } + assign $1\data_r0__fast1_ok[0:0] 1'0 + sync always + sync init + update \data_r0__fast1_ok $1\data_r0__fast1_ok[0:0] + end + attribute \src "issuer_ls180.v:32506.14-32506.51" + process $proc$issuer_ls180.v:32506$1240 + assign { } { } + assign $1\data_r1__fast2[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \data_r1__fast2 $1\data_r1__fast2[63:0] + end + attribute \src "issuer_ls180.v:32510.7-32510.31" + process $proc$issuer_ls180.v:32510$1241 + assign { } { } + assign $1\data_r1__fast2_ok[0:0] 1'0 + sync always + sync init + update \data_r1__fast2_ok $1\data_r1__fast2_ok[0:0] + end + attribute \src "issuer_ls180.v:32514.14-32514.49" + process $proc$issuer_ls180.v:32514$1242 + assign { } { } + assign $1\data_r2__nia[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \data_r2__nia $1\data_r2__nia[63:0] + end + attribute \src "issuer_ls180.v:32518.7-32518.29" + process $proc$issuer_ls180.v:32518$1243 + assign { } { } + assign $1\data_r2__nia_ok[0:0] 1'0 + sync always + sync init + update \data_r2__nia_ok $1\data_r2__nia_ok[0:0] + end + attribute \src "issuer_ls180.v:32539.7-32539.25" + process $proc$issuer_ls180.v:32539$1244 + assign { } { } + assign $1\opc_l_r_opc[0:0] 1'1 + sync always + sync init + update \opc_l_r_opc $1\opc_l_r_opc[0:0] + end + attribute \src "issuer_ls180.v:32543.7-32543.25" + process $proc$issuer_ls180.v:32543$1245 + assign { } { } + assign $1\opc_l_s_opc[0:0] 1'0 + sync always + sync init + update \opc_l_s_opc $1\opc_l_s_opc[0:0] + end + attribute \src "issuer_ls180.v:32650.13-32650.30" + process $proc$issuer_ls180.v:32650$1246 + assign { } { } + assign $1\prev_wr_go[2:0] 3'000 + sync always + sync init + update \prev_wr_go $1\prev_wr_go[2:0] + end + attribute \src "issuer_ls180.v:32658.13-32658.31" + process $proc$issuer_ls180.v:32658$1247 + assign { } { } + assign $1\req_l_r_req[2:0] 3'111 + sync always + sync init + update \req_l_r_req $1\req_l_r_req[2:0] + end + attribute \src "issuer_ls180.v:32662.13-32662.31" + process $proc$issuer_ls180.v:32662$1248 + assign { } { } + assign $1\req_l_s_req[2:0] 3'000 + sync always + sync init + update \req_l_s_req $1\req_l_s_req[2:0] + end + attribute \src "issuer_ls180.v:32674.7-32674.26" + process $proc$issuer_ls180.v:32674$1249 + assign { } { } + assign $1\rok_l_r_rdok[0:0] 1'1 + sync always + sync init + update \rok_l_r_rdok $1\rok_l_r_rdok[0:0] + end + attribute \src "issuer_ls180.v:32678.7-32678.26" + process $proc$issuer_ls180.v:32678$1250 + assign { } { } + assign $1\rok_l_s_rdok[0:0] 1'0 + sync always + sync init + update \rok_l_s_rdok $1\rok_l_s_rdok[0:0] + end + attribute \src "issuer_ls180.v:32682.7-32682.25" + process $proc$issuer_ls180.v:32682$1251 + assign { } { } + assign $1\rst_l_r_rst[0:0] 1'1 + sync always + sync init + update \rst_l_r_rst $1\rst_l_r_rst[0:0] + end + attribute \src "issuer_ls180.v:32686.7-32686.25" + process $proc$issuer_ls180.v:32686$1252 + assign { } { } + assign $1\rst_l_s_rst[0:0] 1'0 + sync always + sync init + update \rst_l_s_rst $1\rst_l_s_rst[0:0] + end + attribute \src "issuer_ls180.v:32700.13-32700.31" + process $proc$issuer_ls180.v:32700$1253 + assign { } { } + assign $1\src_l_r_src[2:0] 3'111 + sync always + sync init + update \src_l_r_src $1\src_l_r_src[2:0] + end + attribute \src "issuer_ls180.v:32704.13-32704.31" + process $proc$issuer_ls180.v:32704$1254 + assign { } { } + assign $1\src_l_s_src[2:0] 3'000 + sync always + sync init + update \src_l_s_src $1\src_l_s_src[2:0] + end + attribute \src "issuer_ls180.v:32710.14-32710.43" + process $proc$issuer_ls180.v:32710$1255 + assign { } { } + assign $1\src_r0[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \src_r0 $1\src_r0[63:0] + end + attribute \src "issuer_ls180.v:32714.14-32714.43" + process $proc$issuer_ls180.v:32714$1256 + assign { } { } + assign $1\src_r1[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \src_r1 $1\src_r1[63:0] + end + attribute \src "issuer_ls180.v:32718.13-32718.26" + process $proc$issuer_ls180.v:32718$1257 + assign { } { } + assign $1\src_r2[3:0] 4'0000 + sync always + sync init + update \src_r2 $1\src_r2[3:0] + end + attribute \src "issuer_ls180.v:32782.3-32783.39" + process $proc$issuer_ls180.v:32782$1098 + assign { } { } + assign $0\alu_l_r_alu[0:0] \alu_l_r_alu$next + sync posedge \coresync_clk + update \alu_l_r_alu $0\alu_l_r_alu[0:0] + end + attribute \src "issuer_ls180.v:32784.3-32785.43" + process $proc$issuer_ls180.v:32784$1099 + assign { } { } + assign $0\alui_l_r_alui[0:0] \alui_l_r_alui$next + sync posedge \coresync_clk + update \alui_l_r_alui $0\alui_l_r_alui[0:0] + end + attribute \src "issuer_ls180.v:32786.3-32787.29" + process $proc$issuer_ls180.v:32786$1100 + assign { } { } + assign $0\src_r2[3:0] \src_r2$next + sync posedge \coresync_clk + update \src_r2 $0\src_r2[3:0] + end + attribute \src "issuer_ls180.v:32788.3-32789.29" + process $proc$issuer_ls180.v:32788$1101 + assign { } { } + assign $0\src_r1[63:0] \src_r1$next + sync posedge \coresync_clk + update \src_r1 $0\src_r1[63:0] + end + attribute \src "issuer_ls180.v:32790.3-32791.29" + process $proc$issuer_ls180.v:32790$1102 + assign { } { } + assign $0\src_r0[63:0] \src_r0$next + sync posedge \coresync_clk + update \src_r0 $0\src_r0[63:0] + end + attribute \src "issuer_ls180.v:32792.3-32793.41" + process $proc$issuer_ls180.v:32792$1103 + assign { } { } + assign $0\data_r2__nia[63:0] \data_r2__nia$next + sync posedge \coresync_clk + update \data_r2__nia $0\data_r2__nia[63:0] + end + attribute \src "issuer_ls180.v:32794.3-32795.47" + process $proc$issuer_ls180.v:32794$1104 + assign { } { } + assign $0\data_r2__nia_ok[0:0] \data_r2__nia_ok$next + sync posedge \coresync_clk + update \data_r2__nia_ok $0\data_r2__nia_ok[0:0] + end + attribute \src "issuer_ls180.v:32796.3-32797.45" + process $proc$issuer_ls180.v:32796$1105 + assign { } { } + assign $0\data_r1__fast2[63:0] \data_r1__fast2$next + sync posedge \coresync_clk + update \data_r1__fast2 $0\data_r1__fast2[63:0] + end + attribute \src "issuer_ls180.v:32798.3-32799.51" + process $proc$issuer_ls180.v:32798$1106 + assign { } { } + assign $0\data_r1__fast2_ok[0:0] \data_r1__fast2_ok$next + sync posedge \coresync_clk + update \data_r1__fast2_ok $0\data_r1__fast2_ok[0:0] + end + attribute \src "issuer_ls180.v:32800.3-32801.45" + process $proc$issuer_ls180.v:32800$1107 + assign { } { } + assign $0\data_r0__fast1[63:0] \data_r0__fast1$next + sync posedge \coresync_clk + update \data_r0__fast1 $0\data_r0__fast1[63:0] + end + attribute \src "issuer_ls180.v:32802.3-32803.51" + process $proc$issuer_ls180.v:32802$1108 + assign { } { } + assign $0\data_r0__fast1_ok[0:0] \data_r0__fast1_ok$next + sync posedge \coresync_clk + update \data_r0__fast1_ok $0\data_r0__fast1_ok[0:0] + end + attribute \src "issuer_ls180.v:32804.3-32805.61" + process $proc$issuer_ls180.v:32804$1109 + assign { } { } + assign $0\alu_branch0_br_op__cia[63:0] \alu_branch0_br_op__cia$next + sync posedge \coresync_clk + update \alu_branch0_br_op__cia $0\alu_branch0_br_op__cia[63:0] + end + attribute \src "issuer_ls180.v:32806.3-32807.73" + process $proc$issuer_ls180.v:32806$1110 + assign { } { } + assign $0\alu_branch0_br_op__insn_type[6:0] \alu_branch0_br_op__insn_type$next + sync posedge \coresync_clk + update \alu_branch0_br_op__insn_type $0\alu_branch0_br_op__insn_type[6:0] + end + attribute \src "issuer_ls180.v:32808.3-32809.69" + process $proc$issuer_ls180.v:32808$1111 + assign { } { } + assign $0\alu_branch0_br_op__fn_unit[11:0] \alu_branch0_br_op__fn_unit$next + sync posedge \coresync_clk + update \alu_branch0_br_op__fn_unit $0\alu_branch0_br_op__fn_unit[11:0] + end + attribute \src "issuer_ls180.v:32810.3-32811.63" + process $proc$issuer_ls180.v:32810$1112 + assign { } { } + assign $0\alu_branch0_br_op__insn[31:0] \alu_branch0_br_op__insn$next + sync posedge \coresync_clk + update \alu_branch0_br_op__insn $0\alu_branch0_br_op__insn[31:0] + end + attribute \src "issuer_ls180.v:32812.3-32813.83" + process $proc$issuer_ls180.v:32812$1113 + assign { } { } + assign $0\alu_branch0_br_op__imm_data__data[63:0] \alu_branch0_br_op__imm_data__data$next + sync posedge \coresync_clk + update \alu_branch0_br_op__imm_data__data $0\alu_branch0_br_op__imm_data__data[63:0] + end + attribute \src "issuer_ls180.v:32814.3-32815.79" + process $proc$issuer_ls180.v:32814$1114 + assign { } { } + assign $0\alu_branch0_br_op__imm_data__ok[0:0] \alu_branch0_br_op__imm_data__ok$next + sync posedge \coresync_clk + update \alu_branch0_br_op__imm_data__ok $0\alu_branch0_br_op__imm_data__ok[0:0] + end + attribute \src "issuer_ls180.v:32816.3-32817.59" + process $proc$issuer_ls180.v:32816$1115 + assign { } { } + assign $0\alu_branch0_br_op__lk[0:0] \alu_branch0_br_op__lk$next + sync posedge \coresync_clk + update \alu_branch0_br_op__lk $0\alu_branch0_br_op__lk[0:0] + end + attribute \src "issuer_ls180.v:32818.3-32819.71" + process $proc$issuer_ls180.v:32818$1116 + assign { } { } + assign $0\alu_branch0_br_op__is_32bit[0:0] \alu_branch0_br_op__is_32bit$next + sync posedge \coresync_clk + update \alu_branch0_br_op__is_32bit $0\alu_branch0_br_op__is_32bit[0:0] + end + attribute \src "issuer_ls180.v:32820.3-32821.39" + process $proc$issuer_ls180.v:32820$1117 + assign { } { } + assign $0\req_l_r_req[2:0] \req_l_r_req$next + sync posedge \coresync_clk + update \req_l_r_req $0\req_l_r_req[2:0] + end + attribute \src "issuer_ls180.v:32822.3-32823.39" + process $proc$issuer_ls180.v:32822$1118 + assign { } { } + assign $0\req_l_s_req[2:0] \req_l_s_req$next + sync posedge \coresync_clk + update \req_l_s_req $0\req_l_s_req[2:0] + end + attribute \src "issuer_ls180.v:32824.3-32825.39" + process $proc$issuer_ls180.v:32824$1119 + assign { } { } + assign $0\src_l_r_src[2:0] \src_l_r_src$next + sync posedge \coresync_clk + update \src_l_r_src $0\src_l_r_src[2:0] + end + attribute \src "issuer_ls180.v:32826.3-32827.39" + process $proc$issuer_ls180.v:32826$1120 + assign { } { } + assign $0\src_l_s_src[2:0] \src_l_s_src$next + sync posedge \coresync_clk + update \src_l_s_src $0\src_l_s_src[2:0] + end + attribute \src "issuer_ls180.v:32828.3-32829.39" + process $proc$issuer_ls180.v:32828$1121 + assign { } { } + assign $0\opc_l_r_opc[0:0] \opc_l_r_opc$next + sync posedge \coresync_clk + update \opc_l_r_opc $0\opc_l_r_opc[0:0] + end + attribute \src "issuer_ls180.v:32830.3-32831.39" + process $proc$issuer_ls180.v:32830$1122 + assign { } { } + assign $0\opc_l_s_opc[0:0] \opc_l_s_opc$next + sync posedge \coresync_clk + update \opc_l_s_opc $0\opc_l_s_opc[0:0] + end + attribute \src "issuer_ls180.v:32832.3-32833.39" + process $proc$issuer_ls180.v:32832$1123 + assign { } { } + assign $0\rst_l_r_rst[0:0] \rst_l_r_rst$next + sync posedge \coresync_clk + update \rst_l_r_rst $0\rst_l_r_rst[0:0] + end + attribute \src "issuer_ls180.v:32834.3-32835.39" + process $proc$issuer_ls180.v:32834$1124 + assign { } { } + assign $0\rst_l_s_rst[0:0] \rst_l_s_rst$next + sync posedge \coresync_clk + update \rst_l_s_rst $0\rst_l_s_rst[0:0] + end + attribute \src "issuer_ls180.v:32836.3-32837.41" + process $proc$issuer_ls180.v:32836$1125 + assign { } { } + assign $0\rok_l_r_rdok[0:0] \rok_l_r_rdok$next + sync posedge \coresync_clk + update \rok_l_r_rdok $0\rok_l_r_rdok[0:0] + end + attribute \src "issuer_ls180.v:32838.3-32839.41" + process $proc$issuer_ls180.v:32838$1126 + assign { } { } + assign $0\rok_l_s_rdok[0:0] \rok_l_s_rdok$next + sync posedge \coresync_clk + update \rok_l_s_rdok $0\rok_l_s_rdok[0:0] + end + attribute \src "issuer_ls180.v:32840.3-32841.37" + process $proc$issuer_ls180.v:32840$1127 + assign { } { } + assign $0\prev_wr_go[2:0] \prev_wr_go$next + sync posedge \coresync_clk + update \prev_wr_go $0\prev_wr_go[2:0] + end + attribute \src "issuer_ls180.v:32842.3-32843.43" + process $proc$issuer_ls180.v:32842$1128 + assign { } { } + assign $0\alu_done_dly[0:0] \alu_branch0_n_valid_o + sync posedge \coresync_clk + update \alu_done_dly $0\alu_done_dly[0:0] + end + attribute \src "issuer_ls180.v:32844.3-32845.25" + process $proc$issuer_ls180.v:32844$1129 + assign { } { } + assign $0\all_rd_dly[0:0] \$11 + sync posedge \coresync_clk + update \all_rd_dly $0\all_rd_dly[0:0] + end + attribute \src "issuer_ls180.v:32919.3-32928.6" + process $proc$issuer_ls180.v:32919$1130 + assign { } { } + assign { } { } + assign $0\req_done[0:0] $1\req_done[0:0] + attribute \src "issuer_ls180.v:32920.5-32920.29" + switch \initial + attribute \src "issuer_ls180.v:32920.9-32920.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" + switch \$55 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\req_done[0:0] 1'1 + case + assign $1\req_done[0:0] \$47 + end + sync always + update \req_done $0\req_done[0:0] + end + attribute \src "issuer_ls180.v:32929.3-32937.6" + process $proc$issuer_ls180.v:32929$1131 + assign { } { } + assign { } { } + assign $0\rok_l_s_rdok$next[0:0]$1132 $1\rok_l_s_rdok$next[0:0]$1133 + attribute \src "issuer_ls180.v:32930.5-32930.29" + switch \initial + attribute \src "issuer_ls180.v:32930.9-32930.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\rok_l_s_rdok$next[0:0]$1133 1'0 + case + assign $1\rok_l_s_rdok$next[0:0]$1133 \cu_issue_i + end + sync always + update \rok_l_s_rdok$next $0\rok_l_s_rdok$next[0:0]$1132 + end + attribute \src "issuer_ls180.v:32938.3-32946.6" + process $proc$issuer_ls180.v:32938$1134 + assign { } { } + assign { } { } + assign $0\rok_l_r_rdok$next[0:0]$1135 $1\rok_l_r_rdok$next[0:0]$1136 + attribute \src "issuer_ls180.v:32939.5-32939.29" + switch \initial + attribute \src "issuer_ls180.v:32939.9-32939.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\rok_l_r_rdok$next[0:0]$1136 1'1 + case + assign $1\rok_l_r_rdok$next[0:0]$1136 \$65 + end + sync always + update \rok_l_r_rdok$next $0\rok_l_r_rdok$next[0:0]$1135 + end + attribute \src "issuer_ls180.v:32947.3-32955.6" + process $proc$issuer_ls180.v:32947$1137 + assign { } { } + assign { } { } + assign $0\rst_l_s_rst$next[0:0]$1138 $1\rst_l_s_rst$next[0:0]$1139 + attribute \src "issuer_ls180.v:32948.5-32948.29" + switch \initial + attribute \src "issuer_ls180.v:32948.9-32948.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\rst_l_s_rst$next[0:0]$1139 1'0 + case + assign $1\rst_l_s_rst$next[0:0]$1139 \all_rd + end + sync always + update \rst_l_s_rst$next $0\rst_l_s_rst$next[0:0]$1138 + end + attribute \src "issuer_ls180.v:32956.3-32964.6" + process $proc$issuer_ls180.v:32956$1140 + assign { } { } + assign { } { } + assign $0\rst_l_r_rst$next[0:0]$1141 $1\rst_l_r_rst$next[0:0]$1142 + attribute \src "issuer_ls180.v:32957.5-32957.29" + switch \initial + attribute \src "issuer_ls180.v:32957.9-32957.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\rst_l_r_rst$next[0:0]$1142 1'1 + case + assign $1\rst_l_r_rst$next[0:0]$1142 \rst_r + end + sync always + update \rst_l_r_rst$next $0\rst_l_r_rst$next[0:0]$1141 + end + attribute \src "issuer_ls180.v:32965.3-32973.6" + process $proc$issuer_ls180.v:32965$1143 + assign { } { } + assign { } { } + assign $0\opc_l_s_opc$next[0:0]$1144 $1\opc_l_s_opc$next[0:0]$1145 + attribute \src "issuer_ls180.v:32966.5-32966.29" + switch \initial + attribute \src "issuer_ls180.v:32966.9-32966.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\opc_l_s_opc$next[0:0]$1145 1'0 + case + assign $1\opc_l_s_opc$next[0:0]$1145 \cu_issue_i + end + sync always + update \opc_l_s_opc$next $0\opc_l_s_opc$next[0:0]$1144 + end + attribute \src "issuer_ls180.v:32974.3-32982.6" + process $proc$issuer_ls180.v:32974$1146 + assign { } { } + assign { } { } + assign $0\opc_l_r_opc$next[0:0]$1147 $1\opc_l_r_opc$next[0:0]$1148 + attribute \src "issuer_ls180.v:32975.5-32975.29" + switch \initial + attribute \src "issuer_ls180.v:32975.9-32975.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\opc_l_r_opc$next[0:0]$1148 1'1 + case + assign $1\opc_l_r_opc$next[0:0]$1148 \req_done + end + sync always + update \opc_l_r_opc$next $0\opc_l_r_opc$next[0:0]$1147 + end + attribute \src "issuer_ls180.v:32983.3-32991.6" + process $proc$issuer_ls180.v:32983$1149 + assign { } { } + assign { } { } + assign $0\src_l_s_src$next[2:0]$1150 $1\src_l_s_src$next[2:0]$1151 + attribute \src "issuer_ls180.v:32984.5-32984.29" + switch \initial + attribute \src "issuer_ls180.v:32984.9-32984.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\src_l_s_src$next[2:0]$1151 3'000 + case + assign $1\src_l_s_src$next[2:0]$1151 { \cu_issue_i \cu_issue_i \cu_issue_i } + end + sync always + update \src_l_s_src$next $0\src_l_s_src$next[2:0]$1150 + end + attribute \src "issuer_ls180.v:32992.3-33000.6" + process $proc$issuer_ls180.v:32992$1152 + assign { } { } + assign { } { } + assign $0\src_l_r_src$next[2:0]$1153 $1\src_l_r_src$next[2:0]$1154 + attribute \src "issuer_ls180.v:32993.5-32993.29" + switch \initial + attribute \src "issuer_ls180.v:32993.9-32993.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\src_l_r_src$next[2:0]$1154 3'111 + case + assign $1\src_l_r_src$next[2:0]$1154 \reset_r + end + sync always + update \src_l_r_src$next $0\src_l_r_src$next[2:0]$1153 + end + attribute \src "issuer_ls180.v:33001.3-33009.6" + process $proc$issuer_ls180.v:33001$1155 + assign { } { } + assign { } { } + assign $0\req_l_s_req$next[2:0]$1156 $1\req_l_s_req$next[2:0]$1157 + attribute \src "issuer_ls180.v:33002.5-33002.29" + switch \initial + attribute \src "issuer_ls180.v:33002.9-33002.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\req_l_s_req$next[2:0]$1157 3'000 + case + assign $1\req_l_s_req$next[2:0]$1157 \$67 + end + sync always + update \req_l_s_req$next $0\req_l_s_req$next[2:0]$1156 + end + attribute \src "issuer_ls180.v:33010.3-33018.6" + process $proc$issuer_ls180.v:33010$1158 + assign { } { } + assign { } { } + assign $0\req_l_r_req$next[2:0]$1159 $1\req_l_r_req$next[2:0]$1160 + attribute \src "issuer_ls180.v:33011.5-33011.29" + switch \initial + attribute \src "issuer_ls180.v:33011.9-33011.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\req_l_r_req$next[2:0]$1160 3'111 + case + assign $1\req_l_r_req$next[2:0]$1160 \$69 + end + sync always + update \req_l_r_req$next $0\req_l_r_req$next[2:0]$1159 + end + attribute \src "issuer_ls180.v:33019.3-33043.6" + process $proc$issuer_ls180.v:33019$1161 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\alu_branch0_br_op__cia$next[63:0]$1162 $1\alu_branch0_br_op__cia$next[63:0]$1170 + assign $0\alu_branch0_br_op__fn_unit$next[11:0]$1163 $1\alu_branch0_br_op__fn_unit$next[11:0]$1171 + assign { } { } + assign { } { } + assign $0\alu_branch0_br_op__insn$next[31:0]$1166 $1\alu_branch0_br_op__insn$next[31:0]$1174 + assign $0\alu_branch0_br_op__insn_type$next[6:0]$1167 $1\alu_branch0_br_op__insn_type$next[6:0]$1175 + assign $0\alu_branch0_br_op__is_32bit$next[0:0]$1168 $1\alu_branch0_br_op__is_32bit$next[0:0]$1176 + assign $0\alu_branch0_br_op__lk$next[0:0]$1169 $1\alu_branch0_br_op__lk$next[0:0]$1177 + assign $0\alu_branch0_br_op__imm_data__data$next[63:0]$1164 $2\alu_branch0_br_op__imm_data__data$next[63:0]$1178 + assign $0\alu_branch0_br_op__imm_data__ok$next[0:0]$1165 $2\alu_branch0_br_op__imm_data__ok$next[0:0]$1179 + attribute \src "issuer_ls180.v:33020.5-33020.29" + switch \initial + attribute \src "issuer_ls180.v:33020.9-33020.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:257" + switch \cu_issue_i + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { $1\alu_branch0_br_op__is_32bit$next[0:0]$1176 $1\alu_branch0_br_op__lk$next[0:0]$1177 $1\alu_branch0_br_op__imm_data__ok$next[0:0]$1173 $1\alu_branch0_br_op__imm_data__data$next[63:0]$1172 $1\alu_branch0_br_op__insn$next[31:0]$1174 $1\alu_branch0_br_op__fn_unit$next[11:0]$1171 $1\alu_branch0_br_op__insn_type$next[6:0]$1175 $1\alu_branch0_br_op__cia$next[63:0]$1170 } { \oper_i_alu_branch0__is_32bit \oper_i_alu_branch0__lk \oper_i_alu_branch0__imm_data__ok \oper_i_alu_branch0__imm_data__data \oper_i_alu_branch0__insn \oper_i_alu_branch0__fn_unit \oper_i_alu_branch0__insn_type \oper_i_alu_branch0__cia } + case + assign $1\alu_branch0_br_op__cia$next[63:0]$1170 \alu_branch0_br_op__cia + assign $1\alu_branch0_br_op__fn_unit$next[11:0]$1171 \alu_branch0_br_op__fn_unit + assign $1\alu_branch0_br_op__imm_data__data$next[63:0]$1172 \alu_branch0_br_op__imm_data__data + assign $1\alu_branch0_br_op__imm_data__ok$next[0:0]$1173 \alu_branch0_br_op__imm_data__ok + assign $1\alu_branch0_br_op__insn$next[31:0]$1174 \alu_branch0_br_op__insn + assign $1\alu_branch0_br_op__insn_type$next[6:0]$1175 \alu_branch0_br_op__insn_type + assign $1\alu_branch0_br_op__is_32bit$next[0:0]$1176 \alu_branch0_br_op__is_32bit + assign $1\alu_branch0_br_op__lk$next[0:0]$1177 \alu_branch0_br_op__lk + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign $2\alu_branch0_br_op__imm_data__data$next[63:0]$1178 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\alu_branch0_br_op__imm_data__ok$next[0:0]$1179 1'0 + case + assign $2\alu_branch0_br_op__imm_data__data$next[63:0]$1178 $1\alu_branch0_br_op__imm_data__data$next[63:0]$1172 + assign $2\alu_branch0_br_op__imm_data__ok$next[0:0]$1179 $1\alu_branch0_br_op__imm_data__ok$next[0:0]$1173 + end + sync always + update \alu_branch0_br_op__cia$next $0\alu_branch0_br_op__cia$next[63:0]$1162 + update \alu_branch0_br_op__fn_unit$next $0\alu_branch0_br_op__fn_unit$next[11:0]$1163 + update \alu_branch0_br_op__imm_data__data$next $0\alu_branch0_br_op__imm_data__data$next[63:0]$1164 + update \alu_branch0_br_op__imm_data__ok$next $0\alu_branch0_br_op__imm_data__ok$next[0:0]$1165 + update \alu_branch0_br_op__insn$next $0\alu_branch0_br_op__insn$next[31:0]$1166 + update \alu_branch0_br_op__insn_type$next $0\alu_branch0_br_op__insn_type$next[6:0]$1167 + update \alu_branch0_br_op__is_32bit$next $0\alu_branch0_br_op__is_32bit$next[0:0]$1168 + update \alu_branch0_br_op__lk$next $0\alu_branch0_br_op__lk$next[0:0]$1169 + end + attribute \src "issuer_ls180.v:33044.3-33065.6" + process $proc$issuer_ls180.v:33044$1180 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\data_r0__fast1$next[63:0]$1181 $2\data_r0__fast1$next[63:0]$1185 + assign { } { } + assign $0\data_r0__fast1_ok$next[0:0]$1182 $3\data_r0__fast1_ok$next[0:0]$1187 + attribute \src "issuer_ls180.v:33045.5-33045.29" + switch \initial + attribute \src "issuer_ls180.v:33045.9-33045.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" + switch \alu_pulse + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $1\data_r0__fast1_ok$next[0:0]$1184 $1\data_r0__fast1$next[63:0]$1183 } { \fast1_ok \alu_branch0_fast1 } + case + assign $1\data_r0__fast1$next[63:0]$1183 \data_r0__fast1 + assign $1\data_r0__fast1_ok$next[0:0]$1184 \data_r0__fast1_ok + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" + switch \cu_issue_i + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $2\data_r0__fast1_ok$next[0:0]$1186 $2\data_r0__fast1$next[63:0]$1185 } 65'00000000000000000000000000000000000000000000000000000000000000000 + case + assign $2\data_r0__fast1$next[63:0]$1185 $1\data_r0__fast1$next[63:0]$1183 + assign $2\data_r0__fast1_ok$next[0:0]$1186 $1\data_r0__fast1_ok$next[0:0]$1184 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\data_r0__fast1_ok$next[0:0]$1187 1'0 + case + assign $3\data_r0__fast1_ok$next[0:0]$1187 $2\data_r0__fast1_ok$next[0:0]$1186 + end + sync always + update \data_r0__fast1$next $0\data_r0__fast1$next[63:0]$1181 + update \data_r0__fast1_ok$next $0\data_r0__fast1_ok$next[0:0]$1182 + end + attribute \src "issuer_ls180.v:33066.3-33087.6" + process $proc$issuer_ls180.v:33066$1188 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\data_r1__fast2$next[63:0]$1189 $2\data_r1__fast2$next[63:0]$1193 + assign { } { } + assign $0\data_r1__fast2_ok$next[0:0]$1190 $3\data_r1__fast2_ok$next[0:0]$1195 + attribute \src "issuer_ls180.v:33067.5-33067.29" + switch \initial + attribute \src "issuer_ls180.v:33067.9-33067.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" + switch \alu_pulse + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $1\data_r1__fast2_ok$next[0:0]$1192 $1\data_r1__fast2$next[63:0]$1191 } { \fast2_ok \alu_branch0_fast2 } + case + assign $1\data_r1__fast2$next[63:0]$1191 \data_r1__fast2 + assign $1\data_r1__fast2_ok$next[0:0]$1192 \data_r1__fast2_ok + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" + switch \cu_issue_i + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $2\data_r1__fast2_ok$next[0:0]$1194 $2\data_r1__fast2$next[63:0]$1193 } 65'00000000000000000000000000000000000000000000000000000000000000000 + case + assign $2\data_r1__fast2$next[63:0]$1193 $1\data_r1__fast2$next[63:0]$1191 + assign $2\data_r1__fast2_ok$next[0:0]$1194 $1\data_r1__fast2_ok$next[0:0]$1192 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\data_r1__fast2_ok$next[0:0]$1195 1'0 + case + assign $3\data_r1__fast2_ok$next[0:0]$1195 $2\data_r1__fast2_ok$next[0:0]$1194 + end + sync always + update \data_r1__fast2$next $0\data_r1__fast2$next[63:0]$1189 + update \data_r1__fast2_ok$next $0\data_r1__fast2_ok$next[0:0]$1190 + end + attribute \src "issuer_ls180.v:33088.3-33109.6" + process $proc$issuer_ls180.v:33088$1196 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\data_r2__nia$next[63:0]$1197 $2\data_r2__nia$next[63:0]$1201 + assign { } { } + assign $0\data_r2__nia_ok$next[0:0]$1198 $3\data_r2__nia_ok$next[0:0]$1203 + attribute \src "issuer_ls180.v:33089.5-33089.29" + switch \initial + attribute \src "issuer_ls180.v:33089.9-33089.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" + switch \alu_pulse + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $1\data_r2__nia_ok$next[0:0]$1200 $1\data_r2__nia$next[63:0]$1199 } { \nia_ok \alu_branch0_nia } + case + assign $1\data_r2__nia$next[63:0]$1199 \data_r2__nia + assign $1\data_r2__nia_ok$next[0:0]$1200 \data_r2__nia_ok + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" + switch \cu_issue_i + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $2\data_r2__nia_ok$next[0:0]$1202 $2\data_r2__nia$next[63:0]$1201 } 65'00000000000000000000000000000000000000000000000000000000000000000 + case + assign $2\data_r2__nia$next[63:0]$1201 $1\data_r2__nia$next[63:0]$1199 + assign $2\data_r2__nia_ok$next[0:0]$1202 $1\data_r2__nia_ok$next[0:0]$1200 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\data_r2__nia_ok$next[0:0]$1203 1'0 + case + assign $3\data_r2__nia_ok$next[0:0]$1203 $2\data_r2__nia_ok$next[0:0]$1202 + end + sync always + update \data_r2__nia$next $0\data_r2__nia$next[63:0]$1197 + update \data_r2__nia_ok$next $0\data_r2__nia_ok$next[0:0]$1198 + end + attribute \src "issuer_ls180.v:33110.3-33119.6" + process $proc$issuer_ls180.v:33110$1204 + assign { } { } + assign { } { } + assign $0\src_r0$next[63:0]$1205 $1\src_r0$next[63:0]$1206 + attribute \src "issuer_ls180.v:33111.5-33111.29" + switch \initial + attribute \src "issuer_ls180.v:33111.9-33111.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" + switch \src_l_q_src [0] + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\src_r0$next[63:0]$1206 \src1_i + case + assign $1\src_r0$next[63:0]$1206 \src_r0 + end + sync always + update \src_r0$next $0\src_r0$next[63:0]$1205 + end + attribute \src "issuer_ls180.v:33120.3-33129.6" + process $proc$issuer_ls180.v:33120$1207 + assign { } { } + assign { } { } + assign $0\src_r1$next[63:0]$1208 $1\src_r1$next[63:0]$1209 + attribute \src "issuer_ls180.v:33121.5-33121.29" + switch \initial + attribute \src "issuer_ls180.v:33121.9-33121.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" + switch \src_sel + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\src_r1$next[63:0]$1209 \src_or_imm + case + assign $1\src_r1$next[63:0]$1209 \src_r1 + end + sync always + update \src_r1$next $0\src_r1$next[63:0]$1208 + end + attribute \src "issuer_ls180.v:33130.3-33139.6" + process $proc$issuer_ls180.v:33130$1210 + assign { } { } + assign { } { } + assign $0\src_r2$next[3:0]$1211 $1\src_r2$next[3:0]$1212 + attribute \src "issuer_ls180.v:33131.5-33131.29" + switch \initial + attribute \src "issuer_ls180.v:33131.9-33131.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" + switch \src_l_q_src [2] + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\src_r2$next[3:0]$1212 \src3_i + case + assign $1\src_r2$next[3:0]$1212 \src_r2 + end + sync always + update \src_r2$next $0\src_r2$next[3:0]$1211 + end + attribute \src "issuer_ls180.v:33140.3-33148.6" + process $proc$issuer_ls180.v:33140$1213 + assign { } { } + assign { } { } + assign $0\alui_l_r_alui$next[0:0]$1214 $1\alui_l_r_alui$next[0:0]$1215 + attribute \src "issuer_ls180.v:33141.5-33141.29" + switch \initial + attribute \src "issuer_ls180.v:33141.9-33141.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\alui_l_r_alui$next[0:0]$1215 1'1 + case + assign $1\alui_l_r_alui$next[0:0]$1215 \$87 + end + sync always + update \alui_l_r_alui$next $0\alui_l_r_alui$next[0:0]$1214 + end + attribute \src "issuer_ls180.v:33149.3-33157.6" + process $proc$issuer_ls180.v:33149$1216 + assign { } { } + assign { } { } + assign $0\alu_l_r_alu$next[0:0]$1217 $1\alu_l_r_alu$next[0:0]$1218 + attribute \src "issuer_ls180.v:33150.5-33150.29" + switch \initial + attribute \src "issuer_ls180.v:33150.9-33150.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\alu_l_r_alu$next[0:0]$1218 1'1 + case + assign $1\alu_l_r_alu$next[0:0]$1218 \$89 + end + sync always + update \alu_l_r_alu$next $0\alu_l_r_alu$next[0:0]$1217 + end + attribute \src "issuer_ls180.v:33158.3-33167.6" + process $proc$issuer_ls180.v:33158$1219 + assign { } { } + assign { } { } + assign $0\dest1_o[63:0] $1\dest1_o[63:0] + attribute \src "issuer_ls180.v:33159.5-33159.29" + switch \initial + attribute \src "issuer_ls180.v:33159.9-33159.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" + switch \$111 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dest1_o[63:0] \data_r0__fast1 + case + assign $1\dest1_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \dest1_o $0\dest1_o[63:0] + end + attribute \src "issuer_ls180.v:33168.3-33177.6" + process $proc$issuer_ls180.v:33168$1220 + assign { } { } + assign { } { } + assign $0\dest2_o[63:0] $1\dest2_o[63:0] + attribute \src "issuer_ls180.v:33169.5-33169.29" + switch \initial + attribute \src "issuer_ls180.v:33169.9-33169.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" + switch \$113 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dest2_o[63:0] \data_r1__fast2 + case + assign $1\dest2_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \dest2_o $0\dest2_o[63:0] + end + attribute \src "issuer_ls180.v:33178.3-33187.6" + process $proc$issuer_ls180.v:33178$1221 + assign { } { } + assign { } { } + assign $0\dest3_o[63:0] $1\dest3_o[63:0] + attribute \src "issuer_ls180.v:33179.5-33179.29" + switch \initial + attribute \src "issuer_ls180.v:33179.9-33179.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" + switch \$115 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dest3_o[63:0] \data_r2__nia + case + assign $1\dest3_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \dest3_o $0\dest3_o[63:0] + end + attribute \src "issuer_ls180.v:33188.3-33196.6" + process $proc$issuer_ls180.v:33188$1222 + assign { } { } + assign { } { } + assign $0\prev_wr_go$next[2:0]$1223 $1\prev_wr_go$next[2:0]$1224 + attribute \src "issuer_ls180.v:33189.5-33189.29" + switch \initial + attribute \src "issuer_ls180.v:33189.9-33189.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\prev_wr_go$next[2:0]$1224 3'000 + case + assign $1\prev_wr_go$next[2:0]$1224 \$21 + end + sync always + update \prev_wr_go$next $0\prev_wr_go$next[2:0]$1223 + end + connect \$5 $reduce_and$issuer_ls180.v:32725$1041_Y + connect \$99 $and$issuer_ls180.v:32726$1042_Y + connect \$101 $and$issuer_ls180.v:32727$1043_Y + connect \$103 $and$issuer_ls180.v:32728$1044_Y + connect \$105 $and$issuer_ls180.v:32729$1045_Y + connect \$107 $and$issuer_ls180.v:32730$1046_Y + connect \$109 $and$issuer_ls180.v:32731$1047_Y + connect \$111 $and$issuer_ls180.v:32732$1048_Y + connect \$113 $and$issuer_ls180.v:32733$1049_Y + connect \$115 $and$issuer_ls180.v:32734$1050_Y + connect \$11 $and$issuer_ls180.v:32735$1051_Y + connect \$13 $not$issuer_ls180.v:32736$1052_Y + connect \$15 $and$issuer_ls180.v:32737$1053_Y + connect \$17 $not$issuer_ls180.v:32738$1054_Y + connect \$19 $and$issuer_ls180.v:32739$1055_Y + connect \$21 $and$issuer_ls180.v:32740$1056_Y + connect \$25 $not$issuer_ls180.v:32741$1057_Y + connect \$27 $and$issuer_ls180.v:32742$1058_Y + connect \$24 $reduce_or$issuer_ls180.v:32743$1059_Y + connect \$23 $not$issuer_ls180.v:32744$1060_Y + connect \$31 $and$issuer_ls180.v:32745$1061_Y + connect \$33 $reduce_or$issuer_ls180.v:32746$1062_Y + connect \$35 $reduce_or$issuer_ls180.v:32747$1063_Y + connect \$37 $or$issuer_ls180.v:32748$1064_Y + connect \$3 $and$issuer_ls180.v:32749$1065_Y + connect \$39 $not$issuer_ls180.v:32750$1066_Y + connect \$41 $and$issuer_ls180.v:32751$1067_Y + connect \$43 $and$issuer_ls180.v:32752$1068_Y + connect \$45 $eq$issuer_ls180.v:32753$1069_Y + connect \$47 $and$issuer_ls180.v:32754$1070_Y + connect \$49 $eq$issuer_ls180.v:32755$1071_Y + connect \$51 $and$issuer_ls180.v:32756$1072_Y + connect \$53 $and$issuer_ls180.v:32757$1073_Y + connect \$55 $and$issuer_ls180.v:32758$1074_Y + connect \$57 $or$issuer_ls180.v:32759$1075_Y + connect \$59 $or$issuer_ls180.v:32760$1076_Y + connect \$61 $or$issuer_ls180.v:32761$1077_Y + connect \$63 $or$issuer_ls180.v:32762$1078_Y + connect \$65 $and$issuer_ls180.v:32763$1079_Y + connect \$67 $and$issuer_ls180.v:32764$1080_Y + connect \$6 $not$issuer_ls180.v:32765$1081_Y + connect \$69 $or$issuer_ls180.v:32766$1082_Y + connect \$71 $and$issuer_ls180.v:32767$1083_Y + connect \$73 $and$issuer_ls180.v:32768$1084_Y + connect \$75 $and$issuer_ls180.v:32769$1085_Y + connect \$77 $ternary$issuer_ls180.v:32770$1086_Y + connect \$79 $ternary$issuer_ls180.v:32771$1087_Y + connect \$81 $ternary$issuer_ls180.v:32772$1088_Y + connect \$83 $ternary$issuer_ls180.v:32773$1089_Y + connect \$85 $ternary$issuer_ls180.v:32774$1090_Y + connect \$87 $and$issuer_ls180.v:32775$1091_Y + connect \$8 $or$issuer_ls180.v:32776$1092_Y + connect \$89 $and$issuer_ls180.v:32777$1093_Y + connect \$91 $and$issuer_ls180.v:32778$1094_Y + connect \$93 $not$issuer_ls180.v:32779$1095_Y + connect \$95 $and$issuer_ls180.v:32780$1096_Y + connect \$97 $not$issuer_ls180.v:32781$1097_Y + connect \cu_go_die_i 1'0 + connect \cu_shadown_i 1'1 + connect \cu_wr__rel_o \$109 + connect \cu_rd__rel_o \$99 + connect \cu_busy_o \opc_l_q_opc + connect \alu_l_s_alu \all_rd_pulse + connect \alu_branch0_n_ready_i \alu_l_q_alu + connect \alui_l_s_alui \all_rd_pulse + connect \alu_branch0_p_valid_i \alui_l_q_alui + connect \alu_branch0_cr_a \$85 + connect \alu_branch0_fast2$2 \$83 + connect \alu_branch0_fast1$1 \$81 + connect \src_or_imm \$79 + connect \src_sel \$77 + connect \cu_wrmask_o { \$75 \$73 \$71 } + connect \reset_r \$63 + connect \reset_w \$61 + connect \rst_r \$59 + connect \reset \$57 + connect \wr_any \$37 + connect \cu_done_o \$31 + connect \alu_pulsem { \alu_pulse \alu_pulse \alu_pulse } + connect \alu_pulse \alu_done_rise + connect \alu_done_rise \$19 + connect \alu_done_dly$next \alu_done + connect \alu_done \alu_branch0_n_valid_o + connect \all_rd_pulse \all_rd_rise + connect \all_rd_rise \$15 + connect \all_rd_dly$next \all_rd + connect \all_rd \$11 +end +attribute \src "issuer_ls180.v:33231.1-33289.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.l0.pimem.busy_l" +attribute \generator "nMigen" +module \busy_l + attribute \src "issuer_ls180.v:33232.7-33232.20" + wire $0\initial[0:0] + attribute \src "issuer_ls180.v:33277.3-33285.6" + wire $0\q_int$next[0:0]$1268 + attribute \src "issuer_ls180.v:33275.3-33276.27" + wire $0\q_int[0:0] + attribute \src "issuer_ls180.v:33277.3-33285.6" + wire $1\q_int$next[0:0]$1269 + attribute \src "issuer_ls180.v:33256.7-33256.19" + wire $1\q_int[0:0] + attribute \src "issuer_ls180.v:33267.17-33267.96" + wire $and$issuer_ls180.v:33267$1258_Y + attribute \src "issuer_ls180.v:33272.17-33272.96" + wire $and$issuer_ls180.v:33272$1263_Y + attribute \src "issuer_ls180.v:33269.18-33269.94" + wire $not$issuer_ls180.v:33269$1260_Y + attribute \src "issuer_ls180.v:33271.17-33271.93" + wire $not$issuer_ls180.v:33271$1262_Y + attribute \src "issuer_ls180.v:33274.17-33274.93" + wire $not$issuer_ls180.v:33274$1265_Y + attribute \src "issuer_ls180.v:33268.18-33268.99" + wire $or$issuer_ls180.v:33268$1259_Y + attribute \src "issuer_ls180.v:33270.18-33270.100" + wire $or$issuer_ls180.v:33270$1261_Y + attribute \src "issuer_ls180.v:33273.17-33273.98" + wire $or$issuer_ls180.v:33273$1264_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire \$13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" + wire input 5 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" + wire input 1 \coresync_rst + attribute \src "issuer_ls180.v:33232.7-33232.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire output 4 \q_busy + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" + wire \qlq_busy + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + wire \qn_busy + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire input 3 \r_busy + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire input 2 \s_busy + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $and $and$issuer_ls180.v:33267$1258 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$7 + connect \Y $and$issuer_ls180.v:33267$1258_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $and $and$issuer_ls180.v:33272$1263 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$1 + connect \Y $and$issuer_ls180.v:33272$1263_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + cell $not $not$issuer_ls180.v:33269$1260 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_busy + connect \Y $not$issuer_ls180.v:33269$1260_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $not $not$issuer_ls180.v:33271$1262 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_busy + connect \Y $not$issuer_ls180.v:33271$1262_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $not $not$issuer_ls180.v:33274$1265 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_busy + connect \Y $not$issuer_ls180.v:33274$1265_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $or $or$issuer_ls180.v:33268$1259 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$9 + connect \B \s_busy + connect \Y $or$issuer_ls180.v:33268$1259_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + cell $or $or$issuer_ls180.v:33270$1261 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_busy + connect \B \q_int + connect \Y $or$issuer_ls180.v:33270$1261_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $or $or$issuer_ls180.v:33273$1264 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$3 + connect \B \s_busy + connect \Y $or$issuer_ls180.v:33273$1264_Y + end + attribute \src "issuer_ls180.v:33232.7-33232.20" + process $proc$issuer_ls180.v:33232$1270 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "issuer_ls180.v:33256.7-33256.19" + process $proc$issuer_ls180.v:33256$1271 + assign { } { } + assign $1\q_int[0:0] 1'0 + sync always + sync init + update \q_int $1\q_int[0:0] + end + attribute \src "issuer_ls180.v:33275.3-33276.27" + process $proc$issuer_ls180.v:33275$1266 + assign { } { } + assign $0\q_int[0:0] \q_int$next + sync posedge \coresync_clk + update \q_int $0\q_int[0:0] + end + attribute \src "issuer_ls180.v:33277.3-33285.6" + process $proc$issuer_ls180.v:33277$1267 + assign { } { } + assign { } { } + assign $0\q_int$next[0:0]$1268 $1\q_int$next[0:0]$1269 + attribute \src "issuer_ls180.v:33278.5-33278.29" + switch \initial + attribute \src "issuer_ls180.v:33278.9-33278.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\q_int$next[0:0]$1269 1'0 + case + assign $1\q_int$next[0:0]$1269 \$5 + end + sync always + update \q_int$next $0\q_int$next[0:0]$1268 + end + connect \$9 $and$issuer_ls180.v:33267$1258_Y + connect \$11 $or$issuer_ls180.v:33268$1259_Y + connect \$13 $not$issuer_ls180.v:33269$1260_Y + connect \$15 $or$issuer_ls180.v:33270$1261_Y + connect \$1 $not$issuer_ls180.v:33271$1262_Y + connect \$3 $and$issuer_ls180.v:33272$1263_Y + connect \$5 $or$issuer_ls180.v:33273$1264_Y + connect \$7 $not$issuer_ls180.v:33274$1265_Y + connect \qlq_busy \$15 + connect \qn_busy \$13 + connect \q_busy \$11 +end +attribute \src "issuer_ls180.v:33293.1-34901.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.fus.logical0.alu_logical0.logical_pipe1.main.clz" +attribute \generator "nMigen" +module \clz + attribute \src "issuer_ls180.v:33768.3-33782.6" + wire width 2 $0\cnt_1_0[1:0] + attribute \src "issuer_ls180.v:33858.3-33872.6" + wire width 2 $0\cnt_1_10[1:0] + attribute \src "issuer_ls180.v:33873.3-33887.6" + wire width 2 $0\cnt_1_11[1:0] + attribute \src "issuer_ls180.v:33888.3-33902.6" + wire width 2 $0\cnt_1_12[1:0] + attribute \src "issuer_ls180.v:33903.3-33917.6" + wire width 2 $0\cnt_1_13[1:0] + attribute \src "issuer_ls180.v:33918.3-33932.6" + wire width 2 $0\cnt_1_14[1:0] + attribute \src "issuer_ls180.v:33948.3-33962.6" + wire width 2 $0\cnt_1_15[1:0] + attribute \src "issuer_ls180.v:33963.3-33977.6" + wire width 2 $0\cnt_1_16[1:0] + attribute \src "issuer_ls180.v:33978.3-33992.6" + wire width 2 $0\cnt_1_17[1:0] + attribute \src "issuer_ls180.v:33993.3-34007.6" + wire width 2 $0\cnt_1_18[1:0] + attribute \src "issuer_ls180.v:34008.3-34022.6" + wire width 2 $0\cnt_1_19[1:0] + attribute \src "issuer_ls180.v:33933.3-33947.6" + wire width 2 $0\cnt_1_1[1:0] + attribute \src "issuer_ls180.v:34023.3-34037.6" + wire width 2 $0\cnt_1_20[1:0] + attribute \src "issuer_ls180.v:34038.3-34052.6" + wire width 2 $0\cnt_1_21[1:0] + attribute \src "issuer_ls180.v:34053.3-34067.6" + wire width 2 $0\cnt_1_22[1:0] + attribute \src "issuer_ls180.v:34068.3-34082.6" + wire width 2 $0\cnt_1_23[1:0] + attribute \src "issuer_ls180.v:34083.3-34097.6" + wire width 2 $0\cnt_1_24[1:0] + attribute \src "issuer_ls180.v:34113.3-34127.6" + wire width 2 $0\cnt_1_25[1:0] + attribute \src "issuer_ls180.v:34128.3-34142.6" + wire width 2 $0\cnt_1_26[1:0] + attribute \src "issuer_ls180.v:34143.3-34157.6" + wire width 2 $0\cnt_1_27[1:0] + attribute \src "issuer_ls180.v:34158.3-34172.6" + wire width 2 $0\cnt_1_28[1:0] + attribute \src "issuer_ls180.v:34173.3-34187.6" + wire width 2 $0\cnt_1_29[1:0] + attribute \src "issuer_ls180.v:34098.3-34112.6" + wire width 2 $0\cnt_1_2[1:0] + attribute \src "issuer_ls180.v:34188.3-34202.6" + wire width 2 $0\cnt_1_30[1:0] + attribute \src "issuer_ls180.v:34203.3-34217.6" + wire width 2 $0\cnt_1_31[1:0] + attribute \src "issuer_ls180.v:34338.3-34352.6" + wire width 2 $0\cnt_1_3[1:0] + attribute \src "issuer_ls180.v:34753.3-34767.6" + wire width 2 $0\cnt_1_4[1:0] + attribute \src "issuer_ls180.v:33783.3-33797.6" + wire width 2 $0\cnt_1_5[1:0] + attribute \src "issuer_ls180.v:33798.3-33812.6" + wire width 2 $0\cnt_1_6[1:0] + attribute \src "issuer_ls180.v:33813.3-33827.6" + wire width 2 $0\cnt_1_7[1:0] + attribute \src "issuer_ls180.v:33828.3-33842.6" + wire width 2 $0\cnt_1_8[1:0] + attribute \src "issuer_ls180.v:33843.3-33857.6" + wire width 2 $0\cnt_1_9[1:0] + attribute \src "issuer_ls180.v:34218.3-34237.6" + wire width 3 $0\cnt_2_0[2:0] + attribute \src "issuer_ls180.v:34318.3-34337.6" + wire width 3 $0\cnt_2_10[2:0] + attribute \src "issuer_ls180.v:34353.3-34372.6" + wire width 3 $0\cnt_2_12[2:0] + attribute \src "issuer_ls180.v:34373.3-34392.6" + wire width 3 $0\cnt_2_14[2:0] + attribute \src "issuer_ls180.v:34393.3-34412.6" + wire width 3 $0\cnt_2_16[2:0] + attribute \src "issuer_ls180.v:34413.3-34432.6" + wire width 3 $0\cnt_2_18[2:0] + attribute \src "issuer_ls180.v:34433.3-34452.6" + wire width 3 $0\cnt_2_20[2:0] + attribute \src "issuer_ls180.v:34453.3-34472.6" + wire width 3 $0\cnt_2_22[2:0] + attribute \src "issuer_ls180.v:34473.3-34492.6" + wire width 3 $0\cnt_2_24[2:0] + attribute \src "issuer_ls180.v:34493.3-34512.6" + wire width 3 $0\cnt_2_26[2:0] + attribute \src "issuer_ls180.v:34513.3-34532.6" + wire width 3 $0\cnt_2_28[2:0] + attribute \src "issuer_ls180.v:34238.3-34257.6" + wire width 3 $0\cnt_2_2[2:0] + attribute \src "issuer_ls180.v:34533.3-34552.6" + wire width 3 $0\cnt_2_30[2:0] + attribute \src "issuer_ls180.v:34258.3-34277.6" + wire width 3 $0\cnt_2_4[2:0] + attribute \src "issuer_ls180.v:34278.3-34297.6" + wire width 3 $0\cnt_2_6[2:0] + attribute \src "issuer_ls180.v:34298.3-34317.6" + wire width 3 $0\cnt_2_8[2:0] + attribute \src "issuer_ls180.v:34553.3-34572.6" + wire width 4 $0\cnt_3_0[3:0] + attribute \src "issuer_ls180.v:34653.3-34672.6" + wire width 4 $0\cnt_3_10[3:0] + attribute \src "issuer_ls180.v:34673.3-34692.6" + wire width 4 $0\cnt_3_12[3:0] + attribute \src "issuer_ls180.v:34693.3-34712.6" + wire width 4 $0\cnt_3_14[3:0] + attribute \src "issuer_ls180.v:34573.3-34592.6" + wire width 4 $0\cnt_3_2[3:0] + attribute \src "issuer_ls180.v:34593.3-34612.6" + wire width 4 $0\cnt_3_4[3:0] + attribute \src "issuer_ls180.v:34613.3-34632.6" + wire width 4 $0\cnt_3_6[3:0] + attribute \src "issuer_ls180.v:34633.3-34652.6" + wire width 4 $0\cnt_3_8[3:0] + attribute \src "issuer_ls180.v:34713.3-34732.6" + wire width 5 $0\cnt_4_0[4:0] + attribute \src "issuer_ls180.v:34733.3-34752.6" + wire width 5 $0\cnt_4_2[4:0] + attribute \src "issuer_ls180.v:34768.3-34787.6" + wire width 5 $0\cnt_4_4[4:0] + attribute \src "issuer_ls180.v:34788.3-34807.6" + wire width 5 $0\cnt_4_6[4:0] + attribute \src "issuer_ls180.v:34808.3-34827.6" + wire width 6 $0\cnt_5_0[5:0] + attribute \src "issuer_ls180.v:34828.3-34847.6" + wire width 6 $0\cnt_5_2[5:0] + attribute \src "issuer_ls180.v:34848.3-34867.6" + wire width 7 $0\cnt_6_0[6:0] + attribute \src "issuer_ls180.v:33294.7-33294.20" + wire $0\initial[0:0] + attribute \src "issuer_ls180.v:33768.3-33782.6" + wire width 2 $1\cnt_1_0[1:0] + attribute \src "issuer_ls180.v:33858.3-33872.6" + wire width 2 $1\cnt_1_10[1:0] + attribute \src "issuer_ls180.v:33873.3-33887.6" + wire width 2 $1\cnt_1_11[1:0] + attribute \src "issuer_ls180.v:33888.3-33902.6" + wire width 2 $1\cnt_1_12[1:0] + attribute \src "issuer_ls180.v:33903.3-33917.6" + wire width 2 $1\cnt_1_13[1:0] + attribute \src "issuer_ls180.v:33918.3-33932.6" + wire width 2 $1\cnt_1_14[1:0] + attribute \src "issuer_ls180.v:33948.3-33962.6" + wire width 2 $1\cnt_1_15[1:0] + attribute \src "issuer_ls180.v:33963.3-33977.6" + wire width 2 $1\cnt_1_16[1:0] + attribute \src "issuer_ls180.v:33978.3-33992.6" + wire width 2 $1\cnt_1_17[1:0] + attribute \src "issuer_ls180.v:33993.3-34007.6" + wire width 2 $1\cnt_1_18[1:0] + attribute \src "issuer_ls180.v:34008.3-34022.6" + wire width 2 $1\cnt_1_19[1:0] + attribute \src "issuer_ls180.v:33933.3-33947.6" + wire width 2 $1\cnt_1_1[1:0] + attribute \src "issuer_ls180.v:34023.3-34037.6" + wire width 2 $1\cnt_1_20[1:0] + attribute \src "issuer_ls180.v:34038.3-34052.6" + wire width 2 $1\cnt_1_21[1:0] + attribute \src "issuer_ls180.v:34053.3-34067.6" + wire width 2 $1\cnt_1_22[1:0] + attribute \src "issuer_ls180.v:34068.3-34082.6" + wire width 2 $1\cnt_1_23[1:0] + attribute \src "issuer_ls180.v:34083.3-34097.6" + wire width 2 $1\cnt_1_24[1:0] + attribute \src "issuer_ls180.v:34113.3-34127.6" + wire width 2 $1\cnt_1_25[1:0] + attribute \src "issuer_ls180.v:34128.3-34142.6" + wire width 2 $1\cnt_1_26[1:0] + attribute \src "issuer_ls180.v:34143.3-34157.6" + wire width 2 $1\cnt_1_27[1:0] + attribute \src "issuer_ls180.v:34158.3-34172.6" + wire width 2 $1\cnt_1_28[1:0] + attribute \src "issuer_ls180.v:34173.3-34187.6" + wire width 2 $1\cnt_1_29[1:0] + attribute \src "issuer_ls180.v:34098.3-34112.6" + wire width 2 $1\cnt_1_2[1:0] + attribute \src "issuer_ls180.v:34188.3-34202.6" + wire width 2 $1\cnt_1_30[1:0] + attribute \src "issuer_ls180.v:34203.3-34217.6" + wire width 2 $1\cnt_1_31[1:0] + attribute \src "issuer_ls180.v:34338.3-34352.6" + wire width 2 $1\cnt_1_3[1:0] + attribute \src "issuer_ls180.v:34753.3-34767.6" + wire width 2 $1\cnt_1_4[1:0] + attribute \src "issuer_ls180.v:33783.3-33797.6" + wire width 2 $1\cnt_1_5[1:0] + attribute \src "issuer_ls180.v:33798.3-33812.6" + wire width 2 $1\cnt_1_6[1:0] + attribute \src "issuer_ls180.v:33813.3-33827.6" + wire width 2 $1\cnt_1_7[1:0] + attribute \src "issuer_ls180.v:33828.3-33842.6" + wire width 2 $1\cnt_1_8[1:0] + attribute \src "issuer_ls180.v:33843.3-33857.6" + wire width 2 $1\cnt_1_9[1:0] + attribute \src "issuer_ls180.v:34218.3-34237.6" + wire width 3 $1\cnt_2_0[2:0] + attribute \src "issuer_ls180.v:34318.3-34337.6" + wire width 3 $1\cnt_2_10[2:0] + attribute \src "issuer_ls180.v:34353.3-34372.6" + wire width 3 $1\cnt_2_12[2:0] + attribute \src "issuer_ls180.v:34373.3-34392.6" + wire width 3 $1\cnt_2_14[2:0] + attribute \src "issuer_ls180.v:34393.3-34412.6" + wire width 3 $1\cnt_2_16[2:0] + attribute \src "issuer_ls180.v:34413.3-34432.6" + wire width 3 $1\cnt_2_18[2:0] + attribute \src "issuer_ls180.v:34433.3-34452.6" + wire width 3 $1\cnt_2_20[2:0] + attribute \src "issuer_ls180.v:34453.3-34472.6" + wire width 3 $1\cnt_2_22[2:0] + attribute \src "issuer_ls180.v:34473.3-34492.6" + wire width 3 $1\cnt_2_24[2:0] + attribute \src "issuer_ls180.v:34493.3-34512.6" + wire width 3 $1\cnt_2_26[2:0] + attribute \src "issuer_ls180.v:34513.3-34532.6" + wire width 3 $1\cnt_2_28[2:0] + attribute \src "issuer_ls180.v:34238.3-34257.6" + wire width 3 $1\cnt_2_2[2:0] + attribute \src "issuer_ls180.v:34533.3-34552.6" + wire width 3 $1\cnt_2_30[2:0] + attribute \src "issuer_ls180.v:34258.3-34277.6" + wire width 3 $1\cnt_2_4[2:0] + attribute \src "issuer_ls180.v:34278.3-34297.6" + wire width 3 $1\cnt_2_6[2:0] + attribute \src "issuer_ls180.v:34298.3-34317.6" + wire width 3 $1\cnt_2_8[2:0] + attribute \src "issuer_ls180.v:34553.3-34572.6" + wire width 4 $1\cnt_3_0[3:0] + attribute \src "issuer_ls180.v:34653.3-34672.6" + wire width 4 $1\cnt_3_10[3:0] + attribute \src "issuer_ls180.v:34673.3-34692.6" + wire width 4 $1\cnt_3_12[3:0] + attribute \src "issuer_ls180.v:34693.3-34712.6" + wire width 4 $1\cnt_3_14[3:0] + attribute \src "issuer_ls180.v:34573.3-34592.6" + wire width 4 $1\cnt_3_2[3:0] + attribute \src "issuer_ls180.v:34593.3-34612.6" + wire width 4 $1\cnt_3_4[3:0] + attribute \src "issuer_ls180.v:34613.3-34632.6" + wire width 4 $1\cnt_3_6[3:0] + attribute \src "issuer_ls180.v:34633.3-34652.6" + wire width 4 $1\cnt_3_8[3:0] + attribute \src "issuer_ls180.v:34713.3-34732.6" + wire width 5 $1\cnt_4_0[4:0] + attribute \src "issuer_ls180.v:34733.3-34752.6" + wire width 5 $1\cnt_4_2[4:0] + attribute \src "issuer_ls180.v:34768.3-34787.6" + wire width 5 $1\cnt_4_4[4:0] + attribute \src "issuer_ls180.v:34788.3-34807.6" + wire width 5 $1\cnt_4_6[4:0] + attribute \src "issuer_ls180.v:34808.3-34827.6" + wire width 6 $1\cnt_5_0[5:0] + attribute \src "issuer_ls180.v:34828.3-34847.6" + wire width 6 $1\cnt_5_2[5:0] + attribute \src "issuer_ls180.v:34848.3-34867.6" + wire width 7 $1\cnt_6_0[6:0] + attribute \src "issuer_ls180.v:34218.3-34237.6" + wire width 3 $2\cnt_2_0[2:0] + attribute \src "issuer_ls180.v:34318.3-34337.6" + wire width 3 $2\cnt_2_10[2:0] + attribute \src "issuer_ls180.v:34353.3-34372.6" + wire width 3 $2\cnt_2_12[2:0] + attribute \src "issuer_ls180.v:34373.3-34392.6" + wire width 3 $2\cnt_2_14[2:0] + attribute \src "issuer_ls180.v:34393.3-34412.6" + wire width 3 $2\cnt_2_16[2:0] + attribute \src "issuer_ls180.v:34413.3-34432.6" + wire width 3 $2\cnt_2_18[2:0] + attribute \src "issuer_ls180.v:34433.3-34452.6" + wire width 3 $2\cnt_2_20[2:0] + attribute \src "issuer_ls180.v:34453.3-34472.6" + wire width 3 $2\cnt_2_22[2:0] + attribute \src "issuer_ls180.v:34473.3-34492.6" + wire width 3 $2\cnt_2_24[2:0] + attribute \src "issuer_ls180.v:34493.3-34512.6" + wire width 3 $2\cnt_2_26[2:0] + attribute \src "issuer_ls180.v:34513.3-34532.6" + wire width 3 $2\cnt_2_28[2:0] + attribute \src "issuer_ls180.v:34238.3-34257.6" + wire width 3 $2\cnt_2_2[2:0] + attribute \src "issuer_ls180.v:34533.3-34552.6" + wire width 3 $2\cnt_2_30[2:0] + attribute \src "issuer_ls180.v:34258.3-34277.6" + wire width 3 $2\cnt_2_4[2:0] + attribute \src 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width 3 \$89 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" + wire \$9 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + wire \$91 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" + wire \$93 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" + wire width 3 \$95 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + wire \$97 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" + wire \$99 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:27" + wire width 2 \cnt_1_0 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:27" + wire width 2 \cnt_1_1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:27" + wire width 2 \cnt_1_10 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:27" + wire width 2 \cnt_1_11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:27" + wire width 2 \cnt_1_12 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:27" + wire width 2 \cnt_1_13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:27" + wire width 2 \cnt_1_14 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:27" + wire width 2 \cnt_1_15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:27" + wire width 2 \cnt_1_16 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:27" + wire width 2 \cnt_1_17 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:27" + wire width 2 \cnt_1_18 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:27" + wire width 2 \cnt_1_19 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:27" + wire width 2 \cnt_1_2 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:27" + wire width 2 \cnt_1_20 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:27" + wire width 2 \cnt_1_21 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:27" + wire width 2 \cnt_1_22 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:27" + wire width 2 \cnt_1_23 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:27" + wire width 2 \cnt_1_24 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:27" + wire width 2 \cnt_1_25 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:27" + wire width 2 \cnt_1_26 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:27" + wire width 2 \cnt_1_27 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:27" + wire width 2 \cnt_1_28 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:27" + wire width 2 \cnt_1_29 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:27" + wire width 2 \cnt_1_3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:27" + wire width 2 \cnt_1_30 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:27" + wire width 2 \cnt_1_31 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:27" + wire width 2 \cnt_1_4 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:27" + wire width 2 \cnt_1_5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:27" + wire width 2 \cnt_1_6 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:27" + wire width 2 \cnt_1_7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:27" + wire width 2 \cnt_1_8 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:27" + wire width 2 \cnt_1_9 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:53" + wire width 3 \cnt_2_0 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:53" + wire width 3 \cnt_2_10 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:53" + wire width 3 \cnt_2_12 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:53" + wire width 3 \cnt_2_14 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:53" + wire width 3 \cnt_2_16 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:53" + wire width 3 \cnt_2_18 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:53" + wire width 3 \cnt_2_2 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:53" + wire width 3 \cnt_2_20 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:53" + wire width 3 \cnt_2_22 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:53" + wire width 3 \cnt_2_24 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:53" + wire width 3 \cnt_2_26 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:53" + wire width 3 \cnt_2_28 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:53" + wire width 3 \cnt_2_30 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:53" + wire width 3 \cnt_2_4 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:53" + wire width 3 \cnt_2_6 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:53" + wire width 3 \cnt_2_8 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:53" + wire width 4 \cnt_3_0 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:53" + wire width 4 \cnt_3_10 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:53" + wire width 4 \cnt_3_12 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:53" + wire width 4 \cnt_3_14 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:53" + wire width 4 \cnt_3_2 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:53" + wire width 4 \cnt_3_4 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:53" + wire width 4 \cnt_3_6 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:53" + wire width 4 \cnt_3_8 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:53" + wire width 5 \cnt_4_0 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:53" + wire width 5 \cnt_4_2 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:53" + wire width 5 \cnt_4_4 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:53" + wire width 5 \cnt_4_6 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:53" + wire width 6 \cnt_5_0 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:53" + wire width 6 \cnt_5_2 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:53" + wire width 7 \cnt_6_0 + attribute \src "issuer_ls180.v:33294.7-33294.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:13" + wire width 7 output 1 \lz + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:24" + wire width 2 \pair0 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:24" + wire width 2 \pair10 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:24" + wire width 2 \pair12 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:24" + wire width 2 \pair14 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:24" + wire width 2 \pair16 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:24" + wire width 2 \pair18 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:24" + wire width 2 \pair2 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:24" + wire width 2 \pair20 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:24" + wire width 2 \pair22 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:24" + wire width 2 \pair24 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:24" + wire width 2 \pair26 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:24" + wire width 2 \pair28 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:24" + wire width 2 \pair30 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:24" + wire width 2 \pair32 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:24" + wire width 2 \pair34 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:24" + wire width 2 \pair36 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:24" + wire width 2 \pair38 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:24" + wire width 2 \pair4 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:24" + wire width 2 \pair40 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:24" + wire width 2 \pair42 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:24" + wire width 2 \pair44 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:24" + wire width 2 \pair46 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:24" + wire width 2 \pair48 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:24" + wire width 2 \pair50 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:24" + wire width 2 \pair52 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:24" + wire width 2 \pair54 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:24" + wire width 2 \pair56 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:24" + wire width 2 \pair58 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:24" + wire width 2 \pair6 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:24" + wire width 2 \pair60 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:24" + wire width 2 \pair62 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:24" + wire width 2 \pair8 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:11" + wire width 64 input 2 \sig_in + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" + cell $eq $eq$issuer_ls180.v:33675$1272 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cnt_1_2 [1] + connect \B 1'1 + connect \Y $eq$issuer_ls180.v:33675$1272_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" + cell $eq $eq$issuer_ls180.v:33676$1273 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cnt_2_0 [2] + connect \B 1'1 + connect \Y $eq$issuer_ls180.v:33676$1273_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + cell $eq $eq$issuer_ls180.v:33678$1275 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cnt_2_6 [2] + connect \B 1'1 + connect \Y $eq$issuer_ls180.v:33678$1275_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" + cell $eq $eq$issuer_ls180.v:33679$1276 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cnt_2_4 [2] + connect \B 1'1 + connect \Y $eq$issuer_ls180.v:33679$1276_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + cell $eq $eq$issuer_ls180.v:33681$1278 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cnt_2_10 [2] + connect \B 1'1 + connect \Y $eq$issuer_ls180.v:33681$1278_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" + cell $eq $eq$issuer_ls180.v:33682$1279 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cnt_2_8 [2] + connect \B 1'1 + connect \Y $eq$issuer_ls180.v:33682$1279_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + cell $eq $eq$issuer_ls180.v:33684$1281 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cnt_2_14 [2] + connect \B 1'1 + connect \Y $eq$issuer_ls180.v:33684$1281_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" + cell $eq $eq$issuer_ls180.v:33685$1282 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cnt_2_12 [2] + connect \B 1'1 + connect \Y $eq$issuer_ls180.v:33685$1282_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + cell $eq $eq$issuer_ls180.v:33688$1285 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cnt_2_18 [2] + connect \B 1'1 + connect \Y $eq$issuer_ls180.v:33688$1285_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" + cell $eq $eq$issuer_ls180.v:33689$1286 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cnt_2_16 [2] + connect \B 1'1 + connect \Y $eq$issuer_ls180.v:33689$1286_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + cell $eq $eq$issuer_ls180.v:33691$1288 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cnt_2_22 [2] + connect \B 1'1 + connect \Y $eq$issuer_ls180.v:33691$1288_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" + cell $eq $eq$issuer_ls180.v:33692$1289 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cnt_2_20 [2] + connect \B 1'1 + connect \Y $eq$issuer_ls180.v:33692$1289_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + cell $eq $eq$issuer_ls180.v:33694$1291 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cnt_2_26 [2] + connect \B 1'1 + connect \Y $eq$issuer_ls180.v:33694$1291_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" + cell $eq $eq$issuer_ls180.v:33695$1292 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cnt_2_24 [2] + connect \B 1'1 + connect \Y $eq$issuer_ls180.v:33695$1292_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + cell $eq $eq$issuer_ls180.v:33697$1294 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cnt_1_5 [1] + connect \B 1'1 + connect \Y $eq$issuer_ls180.v:33697$1294_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + cell $eq $eq$issuer_ls180.v:33698$1295 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cnt_2_30 [2] + connect \B 1'1 + connect \Y $eq$issuer_ls180.v:33698$1295_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" + cell $eq $eq$issuer_ls180.v:33699$1296 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cnt_2_28 [2] + connect \B 1'1 + connect \Y $eq$issuer_ls180.v:33699$1296_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + cell $eq $eq$issuer_ls180.v:33701$1298 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cnt_3_2 [3] + connect \B 1'1 + connect \Y $eq$issuer_ls180.v:33701$1298_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" + cell $eq $eq$issuer_ls180.v:33702$1299 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cnt_3_0 [3] + connect \B 1'1 + connect \Y $eq$issuer_ls180.v:33702$1299_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + cell $eq $eq$issuer_ls180.v:33704$1301 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cnt_3_6 [3] + connect \B 1'1 + connect \Y $eq$issuer_ls180.v:33704$1301_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" + cell $eq $eq$issuer_ls180.v:33705$1302 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cnt_3_4 [3] + connect \B 1'1 + connect \Y $eq$issuer_ls180.v:33705$1302_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + cell $eq $eq$issuer_ls180.v:33707$1304 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cnt_3_10 [3] + connect \B 1'1 + connect \Y $eq$issuer_ls180.v:33707$1304_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" + cell $eq $eq$issuer_ls180.v:33708$1305 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cnt_1_4 [1] + connect \B 1'1 + connect \Y $eq$issuer_ls180.v:33708$1305_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" + cell $eq $eq$issuer_ls180.v:33709$1306 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cnt_3_8 [3] + connect \B 1'1 + connect \Y $eq$issuer_ls180.v:33709$1306_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + cell $eq $eq$issuer_ls180.v:33711$1308 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cnt_3_14 [3] + connect \B 1'1 + connect \Y $eq$issuer_ls180.v:33711$1308_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" + cell $eq $eq$issuer_ls180.v:33712$1309 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cnt_3_12 [3] + connect \B 1'1 + connect \Y $eq$issuer_ls180.v:33712$1309_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + cell $eq $eq$issuer_ls180.v:33714$1311 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cnt_4_2 [4] + connect \B 1'1 + connect \Y $eq$issuer_ls180.v:33714$1311_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" + cell $eq $eq$issuer_ls180.v:33715$1312 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cnt_4_0 [4] + connect \B 1'1 + connect \Y $eq$issuer_ls180.v:33715$1312_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + cell $eq $eq$issuer_ls180.v:33717$1314 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cnt_4_6 [4] + connect \B 1'1 + connect \Y $eq$issuer_ls180.v:33717$1314_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" + cell $eq $eq$issuer_ls180.v:33718$1315 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cnt_4_4 [4] + connect \B 1'1 + connect \Y $eq$issuer_ls180.v:33718$1315_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + cell $eq $eq$issuer_ls180.v:33721$1318 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cnt_5_2 [5] + connect \B 1'1 + connect \Y $eq$issuer_ls180.v:33721$1318_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" + cell $eq $eq$issuer_ls180.v:33722$1319 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cnt_5_0 [5] + connect \B 1'1 + connect \Y $eq$issuer_ls180.v:33722$1319_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + cell $eq $eq$issuer_ls180.v:33724$1321 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cnt_1_1 [1] + connect \B 1'1 + connect \Y $eq$issuer_ls180.v:33724$1321_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + cell $eq $eq$issuer_ls180.v:33725$1322 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cnt_1_7 [1] + connect \B 1'1 + connect \Y $eq$issuer_ls180.v:33725$1322_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" + cell $eq $eq$issuer_ls180.v:33726$1323 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cnt_1_6 [1] + connect \B 1'1 + connect \Y $eq$issuer_ls180.v:33726$1323_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + cell $eq $eq$issuer_ls180.v:33728$1325 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cnt_1_9 [1] + connect \B 1'1 + connect \Y $eq$issuer_ls180.v:33728$1325_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" + cell $eq $eq$issuer_ls180.v:33729$1326 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cnt_1_8 [1] + connect \B 1'1 + connect \Y $eq$issuer_ls180.v:33729$1326_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + cell $eq $eq$issuer_ls180.v:33731$1328 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cnt_1_11 [1] + connect \B 1'1 + connect \Y $eq$issuer_ls180.v:33731$1328_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" + cell $eq $eq$issuer_ls180.v:33732$1329 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cnt_1_10 [1] + connect \B 1'1 + connect \Y $eq$issuer_ls180.v:33732$1329_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + cell $eq $eq$issuer_ls180.v:33734$1331 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cnt_1_13 [1] + connect \B 1'1 + connect \Y $eq$issuer_ls180.v:33734$1331_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" + cell $eq $eq$issuer_ls180.v:33735$1332 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cnt_1_0 [1] + connect \B 1'1 + connect \Y $eq$issuer_ls180.v:33735$1332_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" + cell $eq $eq$issuer_ls180.v:33736$1333 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cnt_1_12 [1] + connect \B 1'1 + connect \Y $eq$issuer_ls180.v:33736$1333_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + cell $eq $eq$issuer_ls180.v:33738$1335 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cnt_1_15 [1] + connect \B 1'1 + connect \Y $eq$issuer_ls180.v:33738$1335_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" + cell $eq $eq$issuer_ls180.v:33739$1336 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cnt_1_14 [1] + connect \B 1'1 + connect \Y $eq$issuer_ls180.v:33739$1336_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + cell $eq $eq$issuer_ls180.v:33741$1338 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cnt_1_17 [1] + connect \B 1'1 + connect \Y $eq$issuer_ls180.v:33741$1338_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" + cell $eq $eq$issuer_ls180.v:33742$1339 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cnt_1_16 [1] + connect \B 1'1 + connect \Y $eq$issuer_ls180.v:33742$1339_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + cell $eq $eq$issuer_ls180.v:33744$1341 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cnt_1_19 [1] + connect \B 1'1 + connect \Y $eq$issuer_ls180.v:33744$1341_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" + cell $eq $eq$issuer_ls180.v:33745$1342 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cnt_1_18 [1] + connect \B 1'1 + connect \Y $eq$issuer_ls180.v:33745$1342_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + cell $eq $eq$issuer_ls180.v:33748$1345 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cnt_1_21 [1] + connect \B 1'1 + connect \Y $eq$issuer_ls180.v:33748$1345_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" + cell $eq $eq$issuer_ls180.v:33749$1346 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cnt_1_20 [1] + connect \B 1'1 + connect \Y $eq$issuer_ls180.v:33749$1346_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + cell $eq $eq$issuer_ls180.v:33751$1348 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cnt_1_23 [1] + connect \B 1'1 + connect \Y $eq$issuer_ls180.v:33751$1348_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" + cell $eq $eq$issuer_ls180.v:33752$1349 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cnt_1_22 [1] + connect \B 1'1 + connect \Y $eq$issuer_ls180.v:33752$1349_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + cell $eq $eq$issuer_ls180.v:33754$1351 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cnt_1_25 [1] + connect \B 1'1 + connect \Y $eq$issuer_ls180.v:33754$1351_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" + cell $eq $eq$issuer_ls180.v:33755$1352 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cnt_1_24 [1] + connect \B 1'1 + connect \Y $eq$issuer_ls180.v:33755$1352_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + cell $eq $eq$issuer_ls180.v:33757$1354 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cnt_1_3 [1] + connect \B 1'1 + connect \Y $eq$issuer_ls180.v:33757$1354_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + cell $eq $eq$issuer_ls180.v:33758$1355 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cnt_1_27 [1] + connect \B 1'1 + connect \Y $eq$issuer_ls180.v:33758$1355_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" + cell $eq $eq$issuer_ls180.v:33759$1356 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cnt_1_26 [1] + connect \B 1'1 + connect \Y $eq$issuer_ls180.v:33759$1356_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + cell $eq $eq$issuer_ls180.v:33761$1358 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cnt_1_29 [1] + connect \B 1'1 + connect \Y $eq$issuer_ls180.v:33761$1358_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" + cell $eq $eq$issuer_ls180.v:33762$1359 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cnt_1_28 [1] + connect \B 1'1 + connect \Y $eq$issuer_ls180.v:33762$1359_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + cell $eq $eq$issuer_ls180.v:33764$1361 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cnt_1_31 [1] + connect \B 1'1 + connect \Y $eq$issuer_ls180.v:33764$1361_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" + cell $eq $eq$issuer_ls180.v:33765$1362 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cnt_1_30 [1] + connect \B 1'1 + connect \Y $eq$issuer_ls180.v:33765$1362_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + cell $eq $eq$issuer_ls180.v:33767$1364 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cnt_2_2 [2] + connect \B 1'1 + connect \Y $eq$issuer_ls180.v:33767$1364_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" + cell $pos $pos$issuer_ls180.v:33677$1274 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A { 2'01 \cnt_2_0 [1:0] } + connect \Y $pos$issuer_ls180.v:33677$1274_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" + cell $pos $pos$issuer_ls180.v:33680$1277 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A { 2'01 \cnt_2_4 [1:0] } + connect \Y $pos$issuer_ls180.v:33680$1277_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" + cell $pos $pos$issuer_ls180.v:33683$1280 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A { 2'01 \cnt_2_8 [1:0] } + connect \Y $pos$issuer_ls180.v:33683$1280_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" + cell $pos $pos$issuer_ls180.v:33686$1283 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A { 2'01 \cnt_1_2 [0] } + connect \Y $pos$issuer_ls180.v:33686$1283_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" + cell $pos $pos$issuer_ls180.v:33687$1284 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A { 2'01 \cnt_2_12 [1:0] } + connect \Y $pos$issuer_ls180.v:33687$1284_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" + cell $pos $pos$issuer_ls180.v:33690$1287 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A { 2'01 \cnt_2_16 [1:0] } + connect \Y $pos$issuer_ls180.v:33690$1287_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" + cell $pos $pos$issuer_ls180.v:33693$1290 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A { 2'01 \cnt_2_20 [1:0] } + connect \Y $pos$issuer_ls180.v:33693$1290_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" + cell $pos $pos$issuer_ls180.v:33696$1293 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A { 2'01 \cnt_2_24 [1:0] } + connect \Y $pos$issuer_ls180.v:33696$1293_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" + cell $pos $pos$issuer_ls180.v:33700$1297 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A { 2'01 \cnt_2_28 [1:0] } + connect \Y $pos$issuer_ls180.v:33700$1297_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" + cell $pos $pos$issuer_ls180.v:33703$1300 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \Y_WIDTH 5 + connect \A { 2'01 \cnt_3_0 [2:0] } + connect \Y $pos$issuer_ls180.v:33703$1300_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" + cell $pos $pos$issuer_ls180.v:33706$1303 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \Y_WIDTH 5 + connect \A { 2'01 \cnt_3_4 [2:0] } + connect \Y $pos$issuer_ls180.v:33706$1303_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" + cell $pos $pos$issuer_ls180.v:33710$1307 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \Y_WIDTH 5 + connect \A { 2'01 \cnt_3_8 [2:0] } + connect \Y $pos$issuer_ls180.v:33710$1307_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" + cell $pos $pos$issuer_ls180.v:33713$1310 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \Y_WIDTH 5 + connect \A { 2'01 \cnt_3_12 [2:0] } + connect \Y $pos$issuer_ls180.v:33713$1310_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" + cell $pos $pos$issuer_ls180.v:33716$1313 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \Y_WIDTH 6 + connect \A { 2'01 \cnt_4_0 [3:0] } + connect \Y $pos$issuer_ls180.v:33716$1313_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" + cell $pos $pos$issuer_ls180.v:33719$1316 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A { 2'01 \cnt_1_4 [0] } + connect \Y $pos$issuer_ls180.v:33719$1316_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" + cell $pos $pos$issuer_ls180.v:33720$1317 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \Y_WIDTH 6 + connect \A { 2'01 \cnt_4_4 [3:0] } + connect \Y $pos$issuer_ls180.v:33720$1317_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" + cell $pos $pos$issuer_ls180.v:33723$1320 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \Y_WIDTH 7 + connect \A { 2'01 \cnt_5_0 [4:0] } + connect \Y $pos$issuer_ls180.v:33723$1320_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" + cell $pos $pos$issuer_ls180.v:33727$1324 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A { 2'01 \cnt_1_6 [0] } + connect \Y $pos$issuer_ls180.v:33727$1324_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" + cell $pos $pos$issuer_ls180.v:33730$1327 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A { 2'01 \cnt_1_8 [0] } + connect \Y $pos$issuer_ls180.v:33730$1327_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" + cell $pos $pos$issuer_ls180.v:33733$1330 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A { 2'01 \cnt_1_10 [0] } + connect \Y $pos$issuer_ls180.v:33733$1330_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" + cell $pos $pos$issuer_ls180.v:33737$1334 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A { 2'01 \cnt_1_12 [0] } + connect \Y $pos$issuer_ls180.v:33737$1334_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" + cell $pos $pos$issuer_ls180.v:33740$1337 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A { 2'01 \cnt_1_14 [0] } + connect \Y $pos$issuer_ls180.v:33740$1337_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" + cell $pos $pos$issuer_ls180.v:33743$1340 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A { 2'01 \cnt_1_16 [0] } + connect \Y $pos$issuer_ls180.v:33743$1340_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" + cell $pos $pos$issuer_ls180.v:33746$1343 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A { 2'01 \cnt_1_0 [0] } + connect \Y $pos$issuer_ls180.v:33746$1343_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" + cell $pos $pos$issuer_ls180.v:33747$1344 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A { 2'01 \cnt_1_18 [0] } + connect \Y $pos$issuer_ls180.v:33747$1344_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" + cell $pos $pos$issuer_ls180.v:33750$1347 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A { 2'01 \cnt_1_20 [0] } + connect \Y $pos$issuer_ls180.v:33750$1347_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" + cell $pos $pos$issuer_ls180.v:33753$1350 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A { 2'01 \cnt_1_22 [0] } + connect \Y $pos$issuer_ls180.v:33753$1350_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" + cell $pos $pos$issuer_ls180.v:33756$1353 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A { 2'01 \cnt_1_24 [0] } + connect \Y $pos$issuer_ls180.v:33756$1353_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" + cell $pos $pos$issuer_ls180.v:33760$1357 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A { 2'01 \cnt_1_26 [0] } + connect \Y $pos$issuer_ls180.v:33760$1357_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" + cell $pos $pos$issuer_ls180.v:33763$1360 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A { 2'01 \cnt_1_28 [0] } + connect \Y $pos$issuer_ls180.v:33763$1360_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" + cell $pos $pos$issuer_ls180.v:33766$1363 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A { 2'01 \cnt_1_30 [0] } + connect \Y $pos$issuer_ls180.v:33766$1363_Y + end + attribute \src "issuer_ls180.v:33294.7-33294.20" + process $proc$issuer_ls180.v:33294$1428 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "issuer_ls180.v:33768.3-33782.6" + process $proc$issuer_ls180.v:33768$1365 + assign { } { } + assign $0\cnt_1_0[1:0] $1\cnt_1_0[1:0] + attribute \src "issuer_ls180.v:33769.5-33769.29" + switch \initial + attribute \src "issuer_ls180.v:33769.9-33769.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:28" + switch \pair0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\cnt_1_0[1:0] 2'10 + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\cnt_1_0[1:0] 2'01 + attribute \src "issuer_ls180.v:0.0-0.0" + case + assign { } { } + assign $1\cnt_1_0[1:0] 2'00 + end + sync always + update \cnt_1_0 $0\cnt_1_0[1:0] + end + attribute \src "issuer_ls180.v:33783.3-33797.6" + process $proc$issuer_ls180.v:33783$1366 + assign { } { } + assign $0\cnt_1_5[1:0] $1\cnt_1_5[1:0] + attribute \src "issuer_ls180.v:33784.5-33784.29" + switch \initial + attribute \src "issuer_ls180.v:33784.9-33784.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:28" + switch \pair10 + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\cnt_1_5[1:0] 2'10 + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\cnt_1_5[1:0] 2'01 + attribute \src "issuer_ls180.v:0.0-0.0" + case + assign { } { } + assign $1\cnt_1_5[1:0] 2'00 + end + sync always + update \cnt_1_5 $0\cnt_1_5[1:0] + end + attribute \src "issuer_ls180.v:33798.3-33812.6" + process $proc$issuer_ls180.v:33798$1367 + assign { } { } + assign $0\cnt_1_6[1:0] $1\cnt_1_6[1:0] + attribute \src "issuer_ls180.v:33799.5-33799.29" + switch \initial + attribute \src "issuer_ls180.v:33799.9-33799.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:28" + switch \pair12 + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\cnt_1_6[1:0] 2'10 + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\cnt_1_6[1:0] 2'01 + attribute \src "issuer_ls180.v:0.0-0.0" + case + assign { } { } + assign $1\cnt_1_6[1:0] 2'00 + end + sync always + update \cnt_1_6 $0\cnt_1_6[1:0] + end + attribute \src "issuer_ls180.v:33813.3-33827.6" + process $proc$issuer_ls180.v:33813$1368 + assign { } { } + assign $0\cnt_1_7[1:0] $1\cnt_1_7[1:0] + attribute \src "issuer_ls180.v:33814.5-33814.29" + switch \initial + attribute \src "issuer_ls180.v:33814.9-33814.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:28" + switch \pair14 + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\cnt_1_7[1:0] 2'10 + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\cnt_1_7[1:0] 2'01 + attribute \src "issuer_ls180.v:0.0-0.0" + case + assign { } { } + assign $1\cnt_1_7[1:0] 2'00 + end + sync always + update \cnt_1_7 $0\cnt_1_7[1:0] + end + attribute \src "issuer_ls180.v:33828.3-33842.6" + process $proc$issuer_ls180.v:33828$1369 + assign { } { } + assign $0\cnt_1_8[1:0] $1\cnt_1_8[1:0] + attribute \src "issuer_ls180.v:33829.5-33829.29" + switch \initial + attribute \src "issuer_ls180.v:33829.9-33829.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:28" + switch \pair16 + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\cnt_1_8[1:0] 2'10 + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\cnt_1_8[1:0] 2'01 + attribute \src "issuer_ls180.v:0.0-0.0" + case + assign { } { } + assign $1\cnt_1_8[1:0] 2'00 + end + sync always + update \cnt_1_8 $0\cnt_1_8[1:0] + end + attribute \src "issuer_ls180.v:33843.3-33857.6" + process $proc$issuer_ls180.v:33843$1370 + assign { } { } + assign $0\cnt_1_9[1:0] $1\cnt_1_9[1:0] + attribute \src "issuer_ls180.v:33844.5-33844.29" + switch \initial + attribute \src "issuer_ls180.v:33844.9-33844.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:28" + switch \pair18 + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\cnt_1_9[1:0] 2'10 + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\cnt_1_9[1:0] 2'01 + attribute \src "issuer_ls180.v:0.0-0.0" + case + assign { } { } + assign $1\cnt_1_9[1:0] 2'00 + end + sync always + update \cnt_1_9 $0\cnt_1_9[1:0] + end + attribute \src "issuer_ls180.v:33858.3-33872.6" + process $proc$issuer_ls180.v:33858$1371 + assign { } { } + assign $0\cnt_1_10[1:0] $1\cnt_1_10[1:0] + attribute \src "issuer_ls180.v:33859.5-33859.29" + switch \initial + attribute \src "issuer_ls180.v:33859.9-33859.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:28" + switch \pair20 + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\cnt_1_10[1:0] 2'10 + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\cnt_1_10[1:0] 2'01 + attribute \src "issuer_ls180.v:0.0-0.0" + case + assign { } { } + assign $1\cnt_1_10[1:0] 2'00 + end + sync always + update \cnt_1_10 $0\cnt_1_10[1:0] + end + attribute \src "issuer_ls180.v:33873.3-33887.6" + process $proc$issuer_ls180.v:33873$1372 + assign { } { } + assign $0\cnt_1_11[1:0] $1\cnt_1_11[1:0] + attribute \src "issuer_ls180.v:33874.5-33874.29" + switch \initial + attribute \src "issuer_ls180.v:33874.9-33874.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:28" + switch \pair22 + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\cnt_1_11[1:0] 2'10 + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\cnt_1_11[1:0] 2'01 + attribute \src "issuer_ls180.v:0.0-0.0" + case + assign { } { } + assign $1\cnt_1_11[1:0] 2'00 + end + sync always + update \cnt_1_11 $0\cnt_1_11[1:0] + end + attribute \src "issuer_ls180.v:33888.3-33902.6" + process $proc$issuer_ls180.v:33888$1373 + assign { } { } + assign $0\cnt_1_12[1:0] $1\cnt_1_12[1:0] + attribute \src "issuer_ls180.v:33889.5-33889.29" + switch \initial + attribute \src "issuer_ls180.v:33889.9-33889.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:28" + switch \pair24 + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\cnt_1_12[1:0] 2'10 + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\cnt_1_12[1:0] 2'01 + attribute \src "issuer_ls180.v:0.0-0.0" + case + assign { } { } + assign $1\cnt_1_12[1:0] 2'00 + end + sync always + update \cnt_1_12 $0\cnt_1_12[1:0] + end + attribute \src "issuer_ls180.v:33903.3-33917.6" + process $proc$issuer_ls180.v:33903$1374 + assign { } { } + assign $0\cnt_1_13[1:0] $1\cnt_1_13[1:0] + attribute \src "issuer_ls180.v:33904.5-33904.29" + switch \initial + attribute \src "issuer_ls180.v:33904.9-33904.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:28" + switch \pair26 + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\cnt_1_13[1:0] 2'10 + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\cnt_1_13[1:0] 2'01 + attribute \src "issuer_ls180.v:0.0-0.0" + case + assign { } { } + assign $1\cnt_1_13[1:0] 2'00 + end + sync always + update \cnt_1_13 $0\cnt_1_13[1:0] + end + attribute \src "issuer_ls180.v:33918.3-33932.6" + process $proc$issuer_ls180.v:33918$1375 + assign { } { } + assign $0\cnt_1_14[1:0] $1\cnt_1_14[1:0] + attribute \src "issuer_ls180.v:33919.5-33919.29" + switch \initial + attribute \src "issuer_ls180.v:33919.9-33919.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:28" + switch \pair28 + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\cnt_1_14[1:0] 2'10 + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\cnt_1_14[1:0] 2'01 + attribute \src "issuer_ls180.v:0.0-0.0" + case + assign { } { } + assign $1\cnt_1_14[1:0] 2'00 + end + sync always + update \cnt_1_14 $0\cnt_1_14[1:0] + end + attribute \src "issuer_ls180.v:33933.3-33947.6" + process $proc$issuer_ls180.v:33933$1376 + assign { } { } + assign $0\cnt_1_1[1:0] $1\cnt_1_1[1:0] + attribute \src "issuer_ls180.v:33934.5-33934.29" + switch \initial + attribute \src "issuer_ls180.v:33934.9-33934.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:28" + switch \pair2 + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\cnt_1_1[1:0] 2'10 + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\cnt_1_1[1:0] 2'01 + attribute \src "issuer_ls180.v:0.0-0.0" + case + assign { } { } + assign $1\cnt_1_1[1:0] 2'00 + end + sync always + update \cnt_1_1 $0\cnt_1_1[1:0] + end + attribute \src "issuer_ls180.v:33948.3-33962.6" + process $proc$issuer_ls180.v:33948$1377 + assign { } { } + assign $0\cnt_1_15[1:0] $1\cnt_1_15[1:0] + attribute \src "issuer_ls180.v:33949.5-33949.29" + switch \initial + attribute \src "issuer_ls180.v:33949.9-33949.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:28" + switch \pair30 + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\cnt_1_15[1:0] 2'10 + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\cnt_1_15[1:0] 2'01 + attribute \src "issuer_ls180.v:0.0-0.0" + case + assign { } { } + assign $1\cnt_1_15[1:0] 2'00 + end + sync always + update \cnt_1_15 $0\cnt_1_15[1:0] + end + attribute \src "issuer_ls180.v:33963.3-33977.6" + process $proc$issuer_ls180.v:33963$1378 + assign { } { } + assign $0\cnt_1_16[1:0] $1\cnt_1_16[1:0] + attribute \src "issuer_ls180.v:33964.5-33964.29" + switch \initial + attribute \src "issuer_ls180.v:33964.9-33964.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:28" + switch \pair32 + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\cnt_1_16[1:0] 2'10 + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\cnt_1_16[1:0] 2'01 + attribute \src "issuer_ls180.v:0.0-0.0" + case + assign { } { } + assign $1\cnt_1_16[1:0] 2'00 + end + sync always + update \cnt_1_16 $0\cnt_1_16[1:0] + end + attribute \src "issuer_ls180.v:33978.3-33992.6" + process $proc$issuer_ls180.v:33978$1379 + assign { } { } + assign $0\cnt_1_17[1:0] $1\cnt_1_17[1:0] + attribute \src "issuer_ls180.v:33979.5-33979.29" + switch \initial + attribute \src "issuer_ls180.v:33979.9-33979.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:28" + switch \pair34 + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\cnt_1_17[1:0] 2'10 + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\cnt_1_17[1:0] 2'01 + attribute \src "issuer_ls180.v:0.0-0.0" + case + assign { } { } + assign $1\cnt_1_17[1:0] 2'00 + end + sync always + update \cnt_1_17 $0\cnt_1_17[1:0] + end + attribute \src "issuer_ls180.v:33993.3-34007.6" + process $proc$issuer_ls180.v:33993$1380 + assign { } { } + assign $0\cnt_1_18[1:0] $1\cnt_1_18[1:0] + attribute \src "issuer_ls180.v:33994.5-33994.29" + switch \initial + attribute \src "issuer_ls180.v:33994.9-33994.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:28" + switch \pair36 + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\cnt_1_18[1:0] 2'10 + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\cnt_1_18[1:0] 2'01 + attribute \src "issuer_ls180.v:0.0-0.0" + case + assign { } { } + assign $1\cnt_1_18[1:0] 2'00 + end + sync always + update \cnt_1_18 $0\cnt_1_18[1:0] + end + attribute \src "issuer_ls180.v:34008.3-34022.6" + process $proc$issuer_ls180.v:34008$1381 + assign { } { } + assign $0\cnt_1_19[1:0] $1\cnt_1_19[1:0] + attribute \src "issuer_ls180.v:34009.5-34009.29" + switch \initial + attribute \src "issuer_ls180.v:34009.9-34009.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:28" + switch \pair38 + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\cnt_1_19[1:0] 2'10 + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\cnt_1_19[1:0] 2'01 + attribute \src "issuer_ls180.v:0.0-0.0" + case + assign { } { } + assign $1\cnt_1_19[1:0] 2'00 + end + sync always + update \cnt_1_19 $0\cnt_1_19[1:0] + end + attribute \src "issuer_ls180.v:34023.3-34037.6" + process $proc$issuer_ls180.v:34023$1382 + assign { } { } + assign $0\cnt_1_20[1:0] $1\cnt_1_20[1:0] + attribute \src "issuer_ls180.v:34024.5-34024.29" + switch \initial + attribute \src "issuer_ls180.v:34024.9-34024.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:28" + switch \pair40 + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\cnt_1_20[1:0] 2'10 + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\cnt_1_20[1:0] 2'01 + attribute \src "issuer_ls180.v:0.0-0.0" + case + assign { } { } + assign $1\cnt_1_20[1:0] 2'00 + end + sync always + update \cnt_1_20 $0\cnt_1_20[1:0] + end + attribute \src "issuer_ls180.v:34038.3-34052.6" + process $proc$issuer_ls180.v:34038$1383 + assign { } { } + assign $0\cnt_1_21[1:0] $1\cnt_1_21[1:0] + attribute \src "issuer_ls180.v:34039.5-34039.29" + switch \initial + attribute \src "issuer_ls180.v:34039.9-34039.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:28" + switch \pair42 + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\cnt_1_21[1:0] 2'10 + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\cnt_1_21[1:0] 2'01 + attribute \src "issuer_ls180.v:0.0-0.0" + case + assign { } { } + assign $1\cnt_1_21[1:0] 2'00 + end + sync always + update \cnt_1_21 $0\cnt_1_21[1:0] + end + attribute \src "issuer_ls180.v:34053.3-34067.6" + process $proc$issuer_ls180.v:34053$1384 + assign { } { } + assign $0\cnt_1_22[1:0] $1\cnt_1_22[1:0] + attribute \src "issuer_ls180.v:34054.5-34054.29" + switch \initial + attribute \src "issuer_ls180.v:34054.9-34054.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:28" + switch \pair44 + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\cnt_1_22[1:0] 2'10 + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\cnt_1_22[1:0] 2'01 + attribute \src "issuer_ls180.v:0.0-0.0" + case + assign { } { } + assign $1\cnt_1_22[1:0] 2'00 + end + sync always + update \cnt_1_22 $0\cnt_1_22[1:0] + end + attribute \src "issuer_ls180.v:34068.3-34082.6" + process $proc$issuer_ls180.v:34068$1385 + assign { } { } + assign $0\cnt_1_23[1:0] $1\cnt_1_23[1:0] + attribute \src "issuer_ls180.v:34069.5-34069.29" + switch \initial + attribute \src "issuer_ls180.v:34069.9-34069.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:28" + switch \pair46 + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\cnt_1_23[1:0] 2'10 + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\cnt_1_23[1:0] 2'01 + attribute \src "issuer_ls180.v:0.0-0.0" + case + assign { } { } + assign $1\cnt_1_23[1:0] 2'00 + end + sync always + update \cnt_1_23 $0\cnt_1_23[1:0] + end + attribute \src "issuer_ls180.v:34083.3-34097.6" + process $proc$issuer_ls180.v:34083$1386 + assign { } { } + assign $0\cnt_1_24[1:0] $1\cnt_1_24[1:0] + attribute \src "issuer_ls180.v:34084.5-34084.29" + switch \initial + attribute \src "issuer_ls180.v:34084.9-34084.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:28" + switch \pair48 + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\cnt_1_24[1:0] 2'10 + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\cnt_1_24[1:0] 2'01 + attribute \src "issuer_ls180.v:0.0-0.0" + case + assign { } { } + assign $1\cnt_1_24[1:0] 2'00 + end + sync always + update \cnt_1_24 $0\cnt_1_24[1:0] + end + attribute \src "issuer_ls180.v:34098.3-34112.6" + process $proc$issuer_ls180.v:34098$1387 + assign { } { } + assign $0\cnt_1_2[1:0] $1\cnt_1_2[1:0] + attribute \src "issuer_ls180.v:34099.5-34099.29" + switch \initial + attribute \src "issuer_ls180.v:34099.9-34099.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:28" + switch \pair4 + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\cnt_1_2[1:0] 2'10 + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\cnt_1_2[1:0] 2'01 + attribute \src "issuer_ls180.v:0.0-0.0" + case + assign { } { } + assign $1\cnt_1_2[1:0] 2'00 + end + sync always + update \cnt_1_2 $0\cnt_1_2[1:0] + end + attribute \src "issuer_ls180.v:34113.3-34127.6" + process $proc$issuer_ls180.v:34113$1388 + assign { } { } + assign $0\cnt_1_25[1:0] $1\cnt_1_25[1:0] + attribute \src "issuer_ls180.v:34114.5-34114.29" + switch \initial + attribute \src "issuer_ls180.v:34114.9-34114.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:28" + switch \pair50 + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\cnt_1_25[1:0] 2'10 + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\cnt_1_25[1:0] 2'01 + attribute \src "issuer_ls180.v:0.0-0.0" + case + assign { } { } + assign $1\cnt_1_25[1:0] 2'00 + end + sync always + update \cnt_1_25 $0\cnt_1_25[1:0] + end + attribute \src "issuer_ls180.v:34128.3-34142.6" + process $proc$issuer_ls180.v:34128$1389 + assign { } { } + assign $0\cnt_1_26[1:0] $1\cnt_1_26[1:0] + attribute \src "issuer_ls180.v:34129.5-34129.29" + switch \initial + attribute \src "issuer_ls180.v:34129.9-34129.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:28" + switch \pair52 + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\cnt_1_26[1:0] 2'10 + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\cnt_1_26[1:0] 2'01 + attribute \src "issuer_ls180.v:0.0-0.0" + case + assign { } { } + assign $1\cnt_1_26[1:0] 2'00 + end + sync always + update \cnt_1_26 $0\cnt_1_26[1:0] + end + attribute \src "issuer_ls180.v:34143.3-34157.6" + process $proc$issuer_ls180.v:34143$1390 + assign { } { } + assign $0\cnt_1_27[1:0] $1\cnt_1_27[1:0] + attribute \src "issuer_ls180.v:34144.5-34144.29" + switch \initial + attribute \src "issuer_ls180.v:34144.9-34144.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:28" + switch \pair54 + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\cnt_1_27[1:0] 2'10 + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\cnt_1_27[1:0] 2'01 + attribute \src "issuer_ls180.v:0.0-0.0" + case + assign { } { } + assign $1\cnt_1_27[1:0] 2'00 + end + sync always + update \cnt_1_27 $0\cnt_1_27[1:0] + end + attribute \src "issuer_ls180.v:34158.3-34172.6" + process $proc$issuer_ls180.v:34158$1391 + assign { } { } + assign $0\cnt_1_28[1:0] $1\cnt_1_28[1:0] + attribute \src "issuer_ls180.v:34159.5-34159.29" + switch \initial + attribute \src "issuer_ls180.v:34159.9-34159.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:28" + switch \pair56 + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\cnt_1_28[1:0] 2'10 + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\cnt_1_28[1:0] 2'01 + attribute \src "issuer_ls180.v:0.0-0.0" + case + assign { } { } + assign $1\cnt_1_28[1:0] 2'00 + end + sync always + update \cnt_1_28 $0\cnt_1_28[1:0] + end + attribute \src "issuer_ls180.v:34173.3-34187.6" + process $proc$issuer_ls180.v:34173$1392 + assign { } { } + assign $0\cnt_1_29[1:0] $1\cnt_1_29[1:0] + attribute \src "issuer_ls180.v:34174.5-34174.29" + switch \initial + attribute \src "issuer_ls180.v:34174.9-34174.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:28" + switch \pair58 + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\cnt_1_29[1:0] 2'10 + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\cnt_1_29[1:0] 2'01 + attribute \src "issuer_ls180.v:0.0-0.0" + case + assign { } { } + assign $1\cnt_1_29[1:0] 2'00 + end + sync always + update \cnt_1_29 $0\cnt_1_29[1:0] + end + attribute \src "issuer_ls180.v:34188.3-34202.6" + process $proc$issuer_ls180.v:34188$1393 + assign { } { } + assign $0\cnt_1_30[1:0] $1\cnt_1_30[1:0] + attribute \src "issuer_ls180.v:34189.5-34189.29" + switch \initial + attribute \src "issuer_ls180.v:34189.9-34189.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:28" + switch \pair60 + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\cnt_1_30[1:0] 2'10 + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\cnt_1_30[1:0] 2'01 + attribute \src "issuer_ls180.v:0.0-0.0" + case + assign { } { } + assign $1\cnt_1_30[1:0] 2'00 + end + sync always + update \cnt_1_30 $0\cnt_1_30[1:0] + end + attribute \src "issuer_ls180.v:34203.3-34217.6" + process $proc$issuer_ls180.v:34203$1394 + assign { } { } + assign $0\cnt_1_31[1:0] $1\cnt_1_31[1:0] + attribute \src "issuer_ls180.v:34204.5-34204.29" + switch \initial + attribute \src "issuer_ls180.v:34204.9-34204.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:28" + switch \pair62 + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\cnt_1_31[1:0] 2'10 + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\cnt_1_31[1:0] 2'01 + attribute \src "issuer_ls180.v:0.0-0.0" + case + assign { } { } + assign $1\cnt_1_31[1:0] 2'00 + end + sync always + update \cnt_1_31 $0\cnt_1_31[1:0] + end + attribute \src "issuer_ls180.v:34218.3-34237.6" + process $proc$issuer_ls180.v:34218$1395 + assign { } { } + assign $0\cnt_2_0[2:0] $1\cnt_2_0[2:0] + attribute \src "issuer_ls180.v:34219.5-34219.29" + switch \initial + attribute \src "issuer_ls180.v:34219.9-34219.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + switch \$1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\cnt_2_0[2:0] $2\cnt_2_0[2:0] + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" + switch \$3 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\cnt_2_0[2:0] 3'100 + attribute \src "issuer_ls180.v:0.0-0.0" + case + assign { } { } + assign $2\cnt_2_0[2:0] \$5 + end + attribute \src "issuer_ls180.v:0.0-0.0" + case + assign { } { } + assign $1\cnt_2_0[2:0] { 1'0 \cnt_1_1 } + end + sync always + update \cnt_2_0 $0\cnt_2_0[2:0] + end + attribute \src "issuer_ls180.v:34238.3-34257.6" + process $proc$issuer_ls180.v:34238$1396 + assign { } { } + assign $0\cnt_2_2[2:0] $1\cnt_2_2[2:0] + attribute \src "issuer_ls180.v:34239.5-34239.29" + switch \initial + attribute \src "issuer_ls180.v:34239.9-34239.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + switch \$7 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\cnt_2_2[2:0] $2\cnt_2_2[2:0] + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" + switch \$9 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\cnt_2_2[2:0] 3'100 + attribute \src "issuer_ls180.v:0.0-0.0" + case + assign { } { } + assign $2\cnt_2_2[2:0] \$11 + end + attribute \src "issuer_ls180.v:0.0-0.0" + case + assign { } { } + assign $1\cnt_2_2[2:0] { 1'0 \cnt_1_3 } + end + sync always + update \cnt_2_2 $0\cnt_2_2[2:0] + end + attribute \src "issuer_ls180.v:34258.3-34277.6" + process $proc$issuer_ls180.v:34258$1397 + assign { } { } + assign $0\cnt_2_4[2:0] $1\cnt_2_4[2:0] + attribute \src "issuer_ls180.v:34259.5-34259.29" + switch \initial + attribute \src "issuer_ls180.v:34259.9-34259.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + switch \$13 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\cnt_2_4[2:0] $2\cnt_2_4[2:0] + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" + switch \$15 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\cnt_2_4[2:0] 3'100 + attribute \src "issuer_ls180.v:0.0-0.0" + case + assign { } { } + assign $2\cnt_2_4[2:0] \$17 + end + attribute \src "issuer_ls180.v:0.0-0.0" + case + assign { } { } + assign $1\cnt_2_4[2:0] { 1'0 \cnt_1_5 } + end + sync always + update \cnt_2_4 $0\cnt_2_4[2:0] + end + attribute \src "issuer_ls180.v:34278.3-34297.6" + process $proc$issuer_ls180.v:34278$1398 + assign { } { } + assign $0\cnt_2_6[2:0] $1\cnt_2_6[2:0] + attribute \src "issuer_ls180.v:34279.5-34279.29" + switch \initial + attribute \src "issuer_ls180.v:34279.9-34279.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + switch \$19 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\cnt_2_6[2:0] $2\cnt_2_6[2:0] + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" + switch \$21 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\cnt_2_6[2:0] 3'100 + attribute \src "issuer_ls180.v:0.0-0.0" + case + assign { } { } + assign $2\cnt_2_6[2:0] \$23 + end + attribute \src "issuer_ls180.v:0.0-0.0" + case + assign { } { } + assign $1\cnt_2_6[2:0] { 1'0 \cnt_1_7 } + end + sync always + update \cnt_2_6 $0\cnt_2_6[2:0] + end + attribute \src "issuer_ls180.v:34298.3-34317.6" + process $proc$issuer_ls180.v:34298$1399 + assign { } { } + assign $0\cnt_2_8[2:0] $1\cnt_2_8[2:0] + attribute \src "issuer_ls180.v:34299.5-34299.29" + switch \initial + attribute \src "issuer_ls180.v:34299.9-34299.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + switch \$25 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\cnt_2_8[2:0] $2\cnt_2_8[2:0] + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" + switch \$27 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\cnt_2_8[2:0] 3'100 + attribute \src "issuer_ls180.v:0.0-0.0" + case + assign { } { } + assign $2\cnt_2_8[2:0] \$29 + end + attribute \src "issuer_ls180.v:0.0-0.0" + case + assign { } { } + assign $1\cnt_2_8[2:0] { 1'0 \cnt_1_9 } + end + sync always + update \cnt_2_8 $0\cnt_2_8[2:0] + end + attribute \src "issuer_ls180.v:34318.3-34337.6" + process $proc$issuer_ls180.v:34318$1400 + assign { } { } + assign $0\cnt_2_10[2:0] $1\cnt_2_10[2:0] + attribute \src "issuer_ls180.v:34319.5-34319.29" + switch \initial + attribute \src "issuer_ls180.v:34319.9-34319.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + switch \$31 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\cnt_2_10[2:0] $2\cnt_2_10[2:0] + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" + switch \$33 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\cnt_2_10[2:0] 3'100 + attribute \src "issuer_ls180.v:0.0-0.0" + case + assign { } { } + assign $2\cnt_2_10[2:0] \$35 + end + attribute \src "issuer_ls180.v:0.0-0.0" + case + assign { } { } + assign $1\cnt_2_10[2:0] { 1'0 \cnt_1_11 } + end + sync always + update \cnt_2_10 $0\cnt_2_10[2:0] + end + attribute \src "issuer_ls180.v:34338.3-34352.6" + process $proc$issuer_ls180.v:34338$1401 + assign { } { } + assign $0\cnt_1_3[1:0] $1\cnt_1_3[1:0] + attribute \src "issuer_ls180.v:34339.5-34339.29" + switch \initial + attribute \src "issuer_ls180.v:34339.9-34339.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:28" + switch \pair6 + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\cnt_1_3[1:0] 2'10 + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\cnt_1_3[1:0] 2'01 + attribute \src "issuer_ls180.v:0.0-0.0" + case + assign { } { } + assign $1\cnt_1_3[1:0] 2'00 + end + sync always + update \cnt_1_3 $0\cnt_1_3[1:0] + end + attribute \src "issuer_ls180.v:34353.3-34372.6" + process $proc$issuer_ls180.v:34353$1402 + assign { } { } + assign $0\cnt_2_12[2:0] $1\cnt_2_12[2:0] + attribute \src "issuer_ls180.v:34354.5-34354.29" + switch \initial + attribute \src "issuer_ls180.v:34354.9-34354.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + switch \$37 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\cnt_2_12[2:0] $2\cnt_2_12[2:0] + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" + switch \$39 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\cnt_2_12[2:0] 3'100 + attribute \src "issuer_ls180.v:0.0-0.0" + case + assign { } { } + assign $2\cnt_2_12[2:0] \$41 + end + attribute \src "issuer_ls180.v:0.0-0.0" + case + assign { } { } + assign $1\cnt_2_12[2:0] { 1'0 \cnt_1_13 } + end + sync always + update \cnt_2_12 $0\cnt_2_12[2:0] + end + attribute \src "issuer_ls180.v:34373.3-34392.6" + process $proc$issuer_ls180.v:34373$1403 + assign { } { } + assign $0\cnt_2_14[2:0] $1\cnt_2_14[2:0] + attribute \src "issuer_ls180.v:34374.5-34374.29" + switch \initial + attribute \src "issuer_ls180.v:34374.9-34374.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + switch \$43 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\cnt_2_14[2:0] $2\cnt_2_14[2:0] + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" + switch \$45 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\cnt_2_14[2:0] 3'100 + attribute \src "issuer_ls180.v:0.0-0.0" + case + assign { } { } + assign $2\cnt_2_14[2:0] \$47 + end + attribute \src "issuer_ls180.v:0.0-0.0" + case + assign { } { } + assign $1\cnt_2_14[2:0] { 1'0 \cnt_1_15 } + end + sync always + update \cnt_2_14 $0\cnt_2_14[2:0] + end + attribute \src "issuer_ls180.v:34393.3-34412.6" + process $proc$issuer_ls180.v:34393$1404 + assign { } { } + assign $0\cnt_2_16[2:0] $1\cnt_2_16[2:0] + attribute \src "issuer_ls180.v:34394.5-34394.29" + switch \initial + attribute \src "issuer_ls180.v:34394.9-34394.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + switch \$49 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\cnt_2_16[2:0] $2\cnt_2_16[2:0] + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" + switch \$51 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\cnt_2_16[2:0] 3'100 + attribute \src "issuer_ls180.v:0.0-0.0" + case + assign { } { } + assign $2\cnt_2_16[2:0] \$53 + end + attribute \src "issuer_ls180.v:0.0-0.0" + case + assign { } { } + assign $1\cnt_2_16[2:0] { 1'0 \cnt_1_17 } + end + sync always + update \cnt_2_16 $0\cnt_2_16[2:0] + end + attribute \src "issuer_ls180.v:34413.3-34432.6" + process $proc$issuer_ls180.v:34413$1405 + assign { } { } + assign $0\cnt_2_18[2:0] $1\cnt_2_18[2:0] + attribute \src "issuer_ls180.v:34414.5-34414.29" + switch \initial + attribute \src "issuer_ls180.v:34414.9-34414.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + switch \$55 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\cnt_2_18[2:0] $2\cnt_2_18[2:0] + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" + switch \$57 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\cnt_2_18[2:0] 3'100 + attribute \src "issuer_ls180.v:0.0-0.0" + case + assign { } { } + assign $2\cnt_2_18[2:0] \$59 + end + attribute \src "issuer_ls180.v:0.0-0.0" + case + assign { } { } + assign $1\cnt_2_18[2:0] { 1'0 \cnt_1_19 } + end + sync always + update \cnt_2_18 $0\cnt_2_18[2:0] + end + attribute \src "issuer_ls180.v:34433.3-34452.6" + process $proc$issuer_ls180.v:34433$1406 + assign { } { } + assign $0\cnt_2_20[2:0] $1\cnt_2_20[2:0] + attribute \src "issuer_ls180.v:34434.5-34434.29" + switch \initial + attribute \src "issuer_ls180.v:34434.9-34434.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + switch \$61 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\cnt_2_20[2:0] $2\cnt_2_20[2:0] + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" + switch \$63 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\cnt_2_20[2:0] 3'100 + attribute \src "issuer_ls180.v:0.0-0.0" + case + assign { } { } + assign $2\cnt_2_20[2:0] \$65 + end + attribute \src "issuer_ls180.v:0.0-0.0" + case + assign { } { } + assign $1\cnt_2_20[2:0] { 1'0 \cnt_1_21 } + end + sync always + update \cnt_2_20 $0\cnt_2_20[2:0] + end + attribute \src "issuer_ls180.v:34453.3-34472.6" + process $proc$issuer_ls180.v:34453$1407 + assign { } { } + assign $0\cnt_2_22[2:0] $1\cnt_2_22[2:0] + attribute \src "issuer_ls180.v:34454.5-34454.29" + switch \initial + attribute \src "issuer_ls180.v:34454.9-34454.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + switch \$67 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\cnt_2_22[2:0] $2\cnt_2_22[2:0] + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" + switch \$69 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\cnt_2_22[2:0] 3'100 + attribute \src "issuer_ls180.v:0.0-0.0" + case + assign { } { } + assign $2\cnt_2_22[2:0] \$71 + end + attribute \src "issuer_ls180.v:0.0-0.0" + case + assign { } { } + assign $1\cnt_2_22[2:0] { 1'0 \cnt_1_23 } + end + sync always + update \cnt_2_22 $0\cnt_2_22[2:0] + end + attribute \src "issuer_ls180.v:34473.3-34492.6" + process $proc$issuer_ls180.v:34473$1408 + assign { } { } + assign $0\cnt_2_24[2:0] $1\cnt_2_24[2:0] + attribute \src "issuer_ls180.v:34474.5-34474.29" + switch \initial + attribute \src "issuer_ls180.v:34474.9-34474.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + switch \$73 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\cnt_2_24[2:0] $2\cnt_2_24[2:0] + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" + switch \$75 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\cnt_2_24[2:0] 3'100 + attribute \src "issuer_ls180.v:0.0-0.0" + case + assign { } { } + assign $2\cnt_2_24[2:0] \$77 + end + attribute \src "issuer_ls180.v:0.0-0.0" + case + assign { } { } + assign $1\cnt_2_24[2:0] { 1'0 \cnt_1_25 } + end + sync always + update \cnt_2_24 $0\cnt_2_24[2:0] + end + attribute \src "issuer_ls180.v:34493.3-34512.6" + process $proc$issuer_ls180.v:34493$1409 + assign { } { } + assign $0\cnt_2_26[2:0] $1\cnt_2_26[2:0] + attribute \src "issuer_ls180.v:34494.5-34494.29" + switch \initial + attribute \src "issuer_ls180.v:34494.9-34494.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + switch \$79 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\cnt_2_26[2:0] $2\cnt_2_26[2:0] + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" + switch \$81 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\cnt_2_26[2:0] 3'100 + attribute \src "issuer_ls180.v:0.0-0.0" + case + assign { } { } + assign $2\cnt_2_26[2:0] \$83 + end + attribute \src "issuer_ls180.v:0.0-0.0" + case + assign { } { } + assign $1\cnt_2_26[2:0] { 1'0 \cnt_1_27 } + end + sync always + update \cnt_2_26 $0\cnt_2_26[2:0] + end + attribute \src "issuer_ls180.v:34513.3-34532.6" + process $proc$issuer_ls180.v:34513$1410 + assign { } { } + assign $0\cnt_2_28[2:0] $1\cnt_2_28[2:0] + attribute \src "issuer_ls180.v:34514.5-34514.29" + switch \initial + attribute \src "issuer_ls180.v:34514.9-34514.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + switch \$85 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\cnt_2_28[2:0] $2\cnt_2_28[2:0] + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" + switch \$87 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\cnt_2_28[2:0] 3'100 + attribute \src "issuer_ls180.v:0.0-0.0" + case + assign { } { } + assign $2\cnt_2_28[2:0] \$89 + end + attribute \src "issuer_ls180.v:0.0-0.0" + case + assign { } { } + assign $1\cnt_2_28[2:0] { 1'0 \cnt_1_29 } + end + sync always + update \cnt_2_28 $0\cnt_2_28[2:0] + end + attribute \src "issuer_ls180.v:34533.3-34552.6" + process $proc$issuer_ls180.v:34533$1411 + assign { } { } + assign $0\cnt_2_30[2:0] $1\cnt_2_30[2:0] + attribute \src "issuer_ls180.v:34534.5-34534.29" + switch \initial + attribute \src "issuer_ls180.v:34534.9-34534.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + switch \$91 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\cnt_2_30[2:0] $2\cnt_2_30[2:0] + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" + switch \$93 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\cnt_2_30[2:0] 3'100 + attribute \src "issuer_ls180.v:0.0-0.0" + case + assign { } { } + assign $2\cnt_2_30[2:0] \$95 + end + attribute \src "issuer_ls180.v:0.0-0.0" + case + assign { } { } + assign $1\cnt_2_30[2:0] { 1'0 \cnt_1_31 } + end + sync always + update \cnt_2_30 $0\cnt_2_30[2:0] + end + attribute \src "issuer_ls180.v:34553.3-34572.6" + process $proc$issuer_ls180.v:34553$1412 + assign { } { } + assign $0\cnt_3_0[3:0] $1\cnt_3_0[3:0] + attribute \src "issuer_ls180.v:34554.5-34554.29" + switch \initial + attribute \src "issuer_ls180.v:34554.9-34554.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + switch \$97 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\cnt_3_0[3:0] $2\cnt_3_0[3:0] + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" + switch \$99 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\cnt_3_0[3:0] 4'1000 + attribute \src "issuer_ls180.v:0.0-0.0" + case + assign { } { } + assign $2\cnt_3_0[3:0] \$101 + end + attribute \src "issuer_ls180.v:0.0-0.0" + case + assign { } { } + assign $1\cnt_3_0[3:0] { 1'0 \cnt_2_2 } + end + sync always + update \cnt_3_0 $0\cnt_3_0[3:0] + end + attribute \src "issuer_ls180.v:34573.3-34592.6" + process $proc$issuer_ls180.v:34573$1413 + assign { } { } + assign $0\cnt_3_2[3:0] $1\cnt_3_2[3:0] + attribute \src "issuer_ls180.v:34574.5-34574.29" + switch \initial + attribute \src "issuer_ls180.v:34574.9-34574.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + switch \$103 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\cnt_3_2[3:0] $2\cnt_3_2[3:0] + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" + switch \$105 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\cnt_3_2[3:0] 4'1000 + attribute \src "issuer_ls180.v:0.0-0.0" + case + assign { } { } + assign $2\cnt_3_2[3:0] \$107 + end + attribute \src "issuer_ls180.v:0.0-0.0" + case + assign { } { } + assign $1\cnt_3_2[3:0] { 1'0 \cnt_2_6 } + end + sync always + update \cnt_3_2 $0\cnt_3_2[3:0] + end + attribute \src "issuer_ls180.v:34593.3-34612.6" + process $proc$issuer_ls180.v:34593$1414 + assign { } { } + assign $0\cnt_3_4[3:0] $1\cnt_3_4[3:0] + attribute \src "issuer_ls180.v:34594.5-34594.29" + switch \initial + attribute \src "issuer_ls180.v:34594.9-34594.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + switch \$109 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\cnt_3_4[3:0] $2\cnt_3_4[3:0] + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" + switch \$111 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\cnt_3_4[3:0] 4'1000 + attribute \src "issuer_ls180.v:0.0-0.0" + case + assign { } { } + assign $2\cnt_3_4[3:0] \$113 + end + attribute \src "issuer_ls180.v:0.0-0.0" + case + assign { } { } + assign $1\cnt_3_4[3:0] { 1'0 \cnt_2_10 } + end + sync always + update \cnt_3_4 $0\cnt_3_4[3:0] + end + attribute \src "issuer_ls180.v:34613.3-34632.6" + process $proc$issuer_ls180.v:34613$1415 + assign { } { } + assign $0\cnt_3_6[3:0] $1\cnt_3_6[3:0] + attribute \src "issuer_ls180.v:34614.5-34614.29" + switch \initial + attribute \src "issuer_ls180.v:34614.9-34614.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + switch \$115 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\cnt_3_6[3:0] $2\cnt_3_6[3:0] + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" + switch \$117 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\cnt_3_6[3:0] 4'1000 + attribute \src "issuer_ls180.v:0.0-0.0" + case + assign { } { } + assign $2\cnt_3_6[3:0] \$119 + end + attribute \src "issuer_ls180.v:0.0-0.0" + case + assign { } { } + assign $1\cnt_3_6[3:0] { 1'0 \cnt_2_14 } + end + sync always + update \cnt_3_6 $0\cnt_3_6[3:0] + end + attribute \src "issuer_ls180.v:34633.3-34652.6" + process $proc$issuer_ls180.v:34633$1416 + assign { } { } + assign $0\cnt_3_8[3:0] $1\cnt_3_8[3:0] + attribute \src "issuer_ls180.v:34634.5-34634.29" + switch \initial + attribute \src "issuer_ls180.v:34634.9-34634.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + switch \$121 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\cnt_3_8[3:0] $2\cnt_3_8[3:0] + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" + switch \$123 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\cnt_3_8[3:0] 4'1000 + attribute \src "issuer_ls180.v:0.0-0.0" + case + assign { } { } + assign $2\cnt_3_8[3:0] \$125 + end + attribute \src "issuer_ls180.v:0.0-0.0" + case + assign { } { } + assign $1\cnt_3_8[3:0] { 1'0 \cnt_2_18 } + end + sync always + update \cnt_3_8 $0\cnt_3_8[3:0] + end + attribute \src "issuer_ls180.v:34653.3-34672.6" + process $proc$issuer_ls180.v:34653$1417 + assign { } { } + assign $0\cnt_3_10[3:0] $1\cnt_3_10[3:0] + attribute \src "issuer_ls180.v:34654.5-34654.29" + switch \initial + attribute \src "issuer_ls180.v:34654.9-34654.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + switch \$127 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\cnt_3_10[3:0] $2\cnt_3_10[3:0] + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" + switch \$129 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\cnt_3_10[3:0] 4'1000 + attribute \src "issuer_ls180.v:0.0-0.0" + case + assign { } { } + assign $2\cnt_3_10[3:0] \$131 + end + attribute \src "issuer_ls180.v:0.0-0.0" + case + assign { } { } + assign $1\cnt_3_10[3:0] { 1'0 \cnt_2_22 } + end + sync always + update \cnt_3_10 $0\cnt_3_10[3:0] + end + attribute \src "issuer_ls180.v:34673.3-34692.6" + process $proc$issuer_ls180.v:34673$1418 + assign { } { } + assign $0\cnt_3_12[3:0] $1\cnt_3_12[3:0] + attribute \src "issuer_ls180.v:34674.5-34674.29" + switch \initial + attribute \src "issuer_ls180.v:34674.9-34674.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + switch \$133 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\cnt_3_12[3:0] $2\cnt_3_12[3:0] + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" + switch \$135 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\cnt_3_12[3:0] 4'1000 + attribute \src "issuer_ls180.v:0.0-0.0" + case + assign { } { } + assign $2\cnt_3_12[3:0] \$137 + end + attribute \src "issuer_ls180.v:0.0-0.0" + case + assign { } { } + assign $1\cnt_3_12[3:0] { 1'0 \cnt_2_26 } + end + sync always + update \cnt_3_12 $0\cnt_3_12[3:0] + end + attribute \src "issuer_ls180.v:34693.3-34712.6" + process $proc$issuer_ls180.v:34693$1419 + assign { } { } + assign $0\cnt_3_14[3:0] $1\cnt_3_14[3:0] + attribute \src "issuer_ls180.v:34694.5-34694.29" + switch \initial + attribute \src "issuer_ls180.v:34694.9-34694.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + switch \$139 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\cnt_3_14[3:0] $2\cnt_3_14[3:0] + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" + switch \$141 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\cnt_3_14[3:0] 4'1000 + attribute \src "issuer_ls180.v:0.0-0.0" + case + assign { } { } + assign $2\cnt_3_14[3:0] \$143 + end + attribute \src "issuer_ls180.v:0.0-0.0" + case + assign { } { } + assign $1\cnt_3_14[3:0] { 1'0 \cnt_2_30 } + end + sync always + update \cnt_3_14 $0\cnt_3_14[3:0] + end + attribute \src "issuer_ls180.v:34713.3-34732.6" + process $proc$issuer_ls180.v:34713$1420 + assign { } { } + assign $0\cnt_4_0[4:0] $1\cnt_4_0[4:0] + attribute \src "issuer_ls180.v:34714.5-34714.29" + switch \initial + attribute \src "issuer_ls180.v:34714.9-34714.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + switch \$145 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\cnt_4_0[4:0] $2\cnt_4_0[4:0] + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" + switch \$147 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\cnt_4_0[4:0] 5'10000 + attribute \src "issuer_ls180.v:0.0-0.0" + case + assign { } { } + assign $2\cnt_4_0[4:0] \$149 + end + attribute \src "issuer_ls180.v:0.0-0.0" + case + assign { } { } + assign $1\cnt_4_0[4:0] { 1'0 \cnt_3_2 } + end + sync always + update \cnt_4_0 $0\cnt_4_0[4:0] + end + attribute \src "issuer_ls180.v:34733.3-34752.6" + process $proc$issuer_ls180.v:34733$1421 + assign { } { } + assign $0\cnt_4_2[4:0] $1\cnt_4_2[4:0] + attribute \src "issuer_ls180.v:34734.5-34734.29" + switch \initial + attribute \src "issuer_ls180.v:34734.9-34734.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + switch \$151 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\cnt_4_2[4:0] $2\cnt_4_2[4:0] + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" + switch \$153 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\cnt_4_2[4:0] 5'10000 + attribute \src "issuer_ls180.v:0.0-0.0" + case + assign { } { } + assign $2\cnt_4_2[4:0] \$155 + end + attribute \src "issuer_ls180.v:0.0-0.0" + case + assign { } { } + assign $1\cnt_4_2[4:0] { 1'0 \cnt_3_6 } + end + sync always + update \cnt_4_2 $0\cnt_4_2[4:0] + end + attribute \src "issuer_ls180.v:34753.3-34767.6" + process $proc$issuer_ls180.v:34753$1422 + assign { } { } + assign $0\cnt_1_4[1:0] $1\cnt_1_4[1:0] + attribute \src "issuer_ls180.v:34754.5-34754.29" + switch \initial + attribute \src "issuer_ls180.v:34754.9-34754.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:28" + switch \pair8 + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\cnt_1_4[1:0] 2'10 + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\cnt_1_4[1:0] 2'01 + attribute \src "issuer_ls180.v:0.0-0.0" + case + assign { } { } + assign $1\cnt_1_4[1:0] 2'00 + end + sync always + update \cnt_1_4 $0\cnt_1_4[1:0] + end + attribute \src "issuer_ls180.v:34768.3-34787.6" + process $proc$issuer_ls180.v:34768$1423 + assign { } { } + assign $0\cnt_4_4[4:0] $1\cnt_4_4[4:0] + attribute \src "issuer_ls180.v:34769.5-34769.29" + switch \initial + attribute \src "issuer_ls180.v:34769.9-34769.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + switch \$157 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\cnt_4_4[4:0] $2\cnt_4_4[4:0] + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" + switch \$159 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\cnt_4_4[4:0] 5'10000 + attribute \src "issuer_ls180.v:0.0-0.0" + case + assign { } { } + assign $2\cnt_4_4[4:0] \$161 + end + attribute \src "issuer_ls180.v:0.0-0.0" + case + assign { } { } + assign $1\cnt_4_4[4:0] { 1'0 \cnt_3_10 } + end + sync always + update \cnt_4_4 $0\cnt_4_4[4:0] + end + attribute \src "issuer_ls180.v:34788.3-34807.6" + process $proc$issuer_ls180.v:34788$1424 + assign { } { } + assign $0\cnt_4_6[4:0] $1\cnt_4_6[4:0] + attribute \src "issuer_ls180.v:34789.5-34789.29" + switch \initial + attribute \src "issuer_ls180.v:34789.9-34789.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + switch \$163 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\cnt_4_6[4:0] $2\cnt_4_6[4:0] + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" + switch \$165 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\cnt_4_6[4:0] 5'10000 + attribute \src "issuer_ls180.v:0.0-0.0" + case + assign { } { } + assign $2\cnt_4_6[4:0] \$167 + end + attribute \src "issuer_ls180.v:0.0-0.0" + case + assign { } { } + assign $1\cnt_4_6[4:0] { 1'0 \cnt_3_14 } + end + sync always + update \cnt_4_6 $0\cnt_4_6[4:0] + end + attribute \src "issuer_ls180.v:34808.3-34827.6" + process $proc$issuer_ls180.v:34808$1425 + assign { } { } + assign $0\cnt_5_0[5:0] $1\cnt_5_0[5:0] + attribute \src "issuer_ls180.v:34809.5-34809.29" + switch \initial + attribute \src "issuer_ls180.v:34809.9-34809.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + switch \$169 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\cnt_5_0[5:0] $2\cnt_5_0[5:0] + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" + switch \$171 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\cnt_5_0[5:0] 6'100000 + attribute \src "issuer_ls180.v:0.0-0.0" + case + assign { } { } + assign $2\cnt_5_0[5:0] \$173 + end + attribute \src "issuer_ls180.v:0.0-0.0" + case + assign { } { } + assign $1\cnt_5_0[5:0] { 1'0 \cnt_4_2 } + end + sync always + update \cnt_5_0 $0\cnt_5_0[5:0] + end + attribute \src "issuer_ls180.v:34828.3-34847.6" + process $proc$issuer_ls180.v:34828$1426 + assign { } { } + assign $0\cnt_5_2[5:0] $1\cnt_5_2[5:0] + attribute \src "issuer_ls180.v:34829.5-34829.29" + switch \initial + attribute \src "issuer_ls180.v:34829.9-34829.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + switch \$175 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\cnt_5_2[5:0] $2\cnt_5_2[5:0] + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" + switch \$177 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\cnt_5_2[5:0] 6'100000 + attribute \src "issuer_ls180.v:0.0-0.0" + case + assign { } { } + assign $2\cnt_5_2[5:0] \$179 + end + attribute \src "issuer_ls180.v:0.0-0.0" + case + assign { } { } + assign $1\cnt_5_2[5:0] { 1'0 \cnt_4_6 } + end + sync always + update \cnt_5_2 $0\cnt_5_2[5:0] + end + attribute \src "issuer_ls180.v:34848.3-34867.6" + process $proc$issuer_ls180.v:34848$1427 + assign { } { } + assign $0\cnt_6_0[6:0] $1\cnt_6_0[6:0] + attribute \src "issuer_ls180.v:34849.5-34849.29" + switch \initial + attribute \src "issuer_ls180.v:34849.9-34849.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" + switch \$181 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\cnt_6_0[6:0] $2\cnt_6_0[6:0] + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" + switch \$183 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\cnt_6_0[6:0] 7'1000000 + attribute \src "issuer_ls180.v:0.0-0.0" + case + assign { } { } + assign $2\cnt_6_0[6:0] \$185 + end + attribute \src "issuer_ls180.v:0.0-0.0" + case + assign { } { } + assign $1\cnt_6_0[6:0] { 1'0 \cnt_5_2 } + end + sync always + update \cnt_6_0 $0\cnt_6_0[6:0] + end + connect \$9 $eq$issuer_ls180.v:33675$1272_Y + connect \$99 $eq$issuer_ls180.v:33676$1273_Y + connect \$101 $pos$issuer_ls180.v:33677$1274_Y + connect \$103 $eq$issuer_ls180.v:33678$1275_Y + connect \$105 $eq$issuer_ls180.v:33679$1276_Y + connect \$107 $pos$issuer_ls180.v:33680$1277_Y + connect \$109 $eq$issuer_ls180.v:33681$1278_Y + connect \$111 $eq$issuer_ls180.v:33682$1279_Y + connect \$113 $pos$issuer_ls180.v:33683$1280_Y + connect \$115 $eq$issuer_ls180.v:33684$1281_Y + connect \$117 $eq$issuer_ls180.v:33685$1282_Y + connect \$11 $pos$issuer_ls180.v:33686$1283_Y + connect \$119 $pos$issuer_ls180.v:33687$1284_Y + connect \$121 $eq$issuer_ls180.v:33688$1285_Y + connect \$123 $eq$issuer_ls180.v:33689$1286_Y + connect \$125 $pos$issuer_ls180.v:33690$1287_Y + connect \$127 $eq$issuer_ls180.v:33691$1288_Y + connect \$129 $eq$issuer_ls180.v:33692$1289_Y + connect \$131 $pos$issuer_ls180.v:33693$1290_Y + connect \$133 $eq$issuer_ls180.v:33694$1291_Y + connect \$135 $eq$issuer_ls180.v:33695$1292_Y + connect \$137 $pos$issuer_ls180.v:33696$1293_Y + connect \$13 $eq$issuer_ls180.v:33697$1294_Y + connect \$139 $eq$issuer_ls180.v:33698$1295_Y + connect \$141 $eq$issuer_ls180.v:33699$1296_Y + connect \$143 $pos$issuer_ls180.v:33700$1297_Y + connect \$145 $eq$issuer_ls180.v:33701$1298_Y + connect \$147 $eq$issuer_ls180.v:33702$1299_Y + connect \$149 $pos$issuer_ls180.v:33703$1300_Y + connect \$151 $eq$issuer_ls180.v:33704$1301_Y + connect \$153 $eq$issuer_ls180.v:33705$1302_Y + connect \$155 $pos$issuer_ls180.v:33706$1303_Y + connect \$157 $eq$issuer_ls180.v:33707$1304_Y + connect \$15 $eq$issuer_ls180.v:33708$1305_Y + connect \$159 $eq$issuer_ls180.v:33709$1306_Y + connect \$161 $pos$issuer_ls180.v:33710$1307_Y + connect \$163 $eq$issuer_ls180.v:33711$1308_Y + connect \$165 $eq$issuer_ls180.v:33712$1309_Y + connect \$167 $pos$issuer_ls180.v:33713$1310_Y + connect \$169 $eq$issuer_ls180.v:33714$1311_Y + connect \$171 $eq$issuer_ls180.v:33715$1312_Y + connect \$173 $pos$issuer_ls180.v:33716$1313_Y + connect \$175 $eq$issuer_ls180.v:33717$1314_Y + connect \$177 $eq$issuer_ls180.v:33718$1315_Y + connect \$17 $pos$issuer_ls180.v:33719$1316_Y + connect \$179 $pos$issuer_ls180.v:33720$1317_Y + connect \$181 $eq$issuer_ls180.v:33721$1318_Y + connect \$183 $eq$issuer_ls180.v:33722$1319_Y + connect \$185 $pos$issuer_ls180.v:33723$1320_Y + connect \$1 $eq$issuer_ls180.v:33724$1321_Y + connect \$19 $eq$issuer_ls180.v:33725$1322_Y + connect \$21 $eq$issuer_ls180.v:33726$1323_Y + connect \$23 $pos$issuer_ls180.v:33727$1324_Y + connect \$25 $eq$issuer_ls180.v:33728$1325_Y + connect \$27 $eq$issuer_ls180.v:33729$1326_Y + connect \$29 $pos$issuer_ls180.v:33730$1327_Y + connect \$31 $eq$issuer_ls180.v:33731$1328_Y + connect \$33 $eq$issuer_ls180.v:33732$1329_Y + connect \$35 $pos$issuer_ls180.v:33733$1330_Y + connect \$37 $eq$issuer_ls180.v:33734$1331_Y + connect \$3 $eq$issuer_ls180.v:33735$1332_Y + connect \$39 $eq$issuer_ls180.v:33736$1333_Y + connect \$41 $pos$issuer_ls180.v:33737$1334_Y + connect \$43 $eq$issuer_ls180.v:33738$1335_Y + connect \$45 $eq$issuer_ls180.v:33739$1336_Y + connect \$47 $pos$issuer_ls180.v:33740$1337_Y + connect \$49 $eq$issuer_ls180.v:33741$1338_Y + connect \$51 $eq$issuer_ls180.v:33742$1339_Y + connect \$53 $pos$issuer_ls180.v:33743$1340_Y + connect \$55 $eq$issuer_ls180.v:33744$1341_Y + connect \$57 $eq$issuer_ls180.v:33745$1342_Y + connect \$5 $pos$issuer_ls180.v:33746$1343_Y + connect \$59 $pos$issuer_ls180.v:33747$1344_Y + connect \$61 $eq$issuer_ls180.v:33748$1345_Y + connect \$63 $eq$issuer_ls180.v:33749$1346_Y + connect \$65 $pos$issuer_ls180.v:33750$1347_Y + connect \$67 $eq$issuer_ls180.v:33751$1348_Y + connect \$69 $eq$issuer_ls180.v:33752$1349_Y + connect \$71 $pos$issuer_ls180.v:33753$1350_Y + connect \$73 $eq$issuer_ls180.v:33754$1351_Y + connect \$75 $eq$issuer_ls180.v:33755$1352_Y + connect \$77 $pos$issuer_ls180.v:33756$1353_Y + connect \$7 $eq$issuer_ls180.v:33757$1354_Y + connect \$79 $eq$issuer_ls180.v:33758$1355_Y + connect \$81 $eq$issuer_ls180.v:33759$1356_Y + connect \$83 $pos$issuer_ls180.v:33760$1357_Y + connect \$85 $eq$issuer_ls180.v:33761$1358_Y + connect \$87 $eq$issuer_ls180.v:33762$1359_Y + connect \$89 $pos$issuer_ls180.v:33763$1360_Y + connect \$91 $eq$issuer_ls180.v:33764$1361_Y + connect \$93 $eq$issuer_ls180.v:33765$1362_Y + connect \$95 $pos$issuer_ls180.v:33766$1363_Y + connect \$97 $eq$issuer_ls180.v:33767$1364_Y + connect \lz \cnt_6_0 + connect \pair62 \sig_in [63:62] + connect \pair60 \sig_in [61:60] + connect \pair58 \sig_in [59:58] + connect \pair56 \sig_in [57:56] + connect \pair54 \sig_in [55:54] + connect \pair52 \sig_in [53:52] + connect \pair50 \sig_in [51:50] + connect \pair48 \sig_in [49:48] + connect \pair46 \sig_in [47:46] + connect \pair44 \sig_in [45:44] + connect \pair42 \sig_in [43:42] + connect \pair40 \sig_in [41:40] + connect \pair38 \sig_in [39:38] + connect \pair36 \sig_in [37:36] + connect \pair34 \sig_in [35:34] + connect \pair32 \sig_in [33:32] + connect \pair30 \sig_in [31:30] + connect \pair28 \sig_in [29:28] + connect \pair26 \sig_in [27:26] + connect \pair24 \sig_in [25:24] + connect \pair22 \sig_in [23:22] + connect \pair20 \sig_in [21:20] + connect \pair18 \sig_in [19:18] + connect \pair16 \sig_in [17:16] + connect \pair14 \sig_in [15:14] + connect \pair12 \sig_in [13:12] + connect \pair10 \sig_in [11:10] + connect \pair8 \sig_in [9:8] + connect \pair6 \sig_in [7:6] + connect \pair4 \sig_in [5:4] + connect \pair2 \sig_in [3:2] + connect \pair0 \sig_in [1:0] +end +attribute \src "issuer_ls180.v:34905.1-47599.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core" +attribute \generator "nMigen" +module \core + attribute \src "issuer_ls180.v:44577.3-44597.6" + wire $0\core_terminate_o$next[0:0]$2512 + attribute \src "issuer_ls180.v:41536.3-41537.49" + wire $0\core_terminate_o[0:0] + attribute \src "issuer_ls180.v:44448.3-44538.6" + wire $0\corebusy_o[0:0] + attribute \src "issuer_ls180.v:44393.3-44419.6" + wire width 2 $0\counter$next[1:0]$2486 + attribute \src "issuer_ls180.v:41538.3-41539.31" + wire width 2 $0\counter[1:0] + attribute \src "issuer_ls180.v:44878.3-44886.6" + wire $0\dp_CR_cr_a_branch0_1$next[0:0]$2568 + attribute \src "issuer_ls180.v:41472.3-41473.57" + wire $0\dp_CR_cr_a_branch0_1[0:0] + attribute \src "issuer_ls180.v:44859.3-44867.6" + wire $0\dp_CR_cr_a_cr0_0$next[0:0]$2562 + attribute \src "issuer_ls180.v:41474.3-41475.49" + wire $0\dp_CR_cr_a_cr0_0[0:0] + attribute \src "issuer_ls180.v:44897.3-44905.6" + wire $0\dp_CR_cr_b_cr0_0$next[0:0]$2574 + attribute \src "issuer_ls180.v:41470.3-41471.49" + wire $0\dp_CR_cr_b_cr0_0[0:0] + attribute \src "issuer_ls180.v:44946.3-44954.6" + wire $0\dp_CR_cr_c_cr0_0$next[0:0]$2581 + attribute \src "issuer_ls180.v:41468.3-41469.49" + wire $0\dp_CR_cr_c_cr0_0[0:0] + attribute \src "issuer_ls180.v:44810.3-44818.6" + wire $0\dp_CR_full_cr_cr0_0$next[0:0]$2555 + attribute \src "issuer_ls180.v:41476.3-41477.55" + wire $0\dp_CR_full_cr_cr0_0[0:0] + attribute \src "issuer_ls180.v:44965.3-44973.6" + wire $0\dp_FAST_fast1_branch0_0$next[0:0]$2587 + attribute \src "issuer_ls180.v:41466.3-41467.63" + wire $0\dp_FAST_fast1_branch0_0[0:0] + attribute \src "issuer_ls180.v:45032.3-45040.6" + wire $0\dp_FAST_fast1_spr0_2$next[0:0]$2600 + attribute \src "issuer_ls180.v:41462.3-41463.57" + wire $0\dp_FAST_fast1_spr0_2[0:0] + attribute \src "issuer_ls180.v:44984.3-44992.6" + wire $0\dp_FAST_fast1_trap0_1$next[0:0]$2593 + attribute \src "issuer_ls180.v:41464.3-41465.59" + wire $0\dp_FAST_fast1_trap0_1[0:0] + attribute \src "issuer_ls180.v:45051.3-45059.6" + wire $0\dp_FAST_fast2_branch0_0$next[0:0]$2606 + attribute \src "issuer_ls180.v:41460.3-41461.63" + wire $0\dp_FAST_fast2_branch0_0[0:0] + attribute \src "issuer_ls180.v:45099.3-45107.6" + wire $0\dp_FAST_fast2_trap0_1$next[0:0]$2613 + attribute \src "issuer_ls180.v:41458.3-41459.59" + wire $0\dp_FAST_fast2_trap0_1[0:0] + attribute \src "issuer_ls180.v:44032.3-44040.6" + wire $0\dp_INT_ra_alu0_0$next[0:0]$2378 + attribute \src "issuer_ls180.v:41534.3-41535.49" + wire $0\dp_INT_ra_alu0_0[0:0] + attribute \src "issuer_ls180.v:44051.3-44059.6" + wire $0\dp_INT_ra_cr0_1$next[0:0]$2382 + attribute \src "issuer_ls180.v:41532.3-41533.47" + wire $0\dp_INT_ra_cr0_1[0:0] + attribute \src "issuer_ls180.v:44127.3-44135.6" + wire $0\dp_INT_ra_div0_5$next[0:0]$2406 + attribute \src "issuer_ls180.v:41524.3-41525.49" + wire $0\dp_INT_ra_div0_5[0:0] + attribute \src "issuer_ls180.v:44184.3-44192.6" + wire $0\dp_INT_ra_ldst0_8$next[0:0]$2424 + attribute \src "issuer_ls180.v:41518.3-41519.51" + wire $0\dp_INT_ra_ldst0_8[0:0] + attribute \src "issuer_ls180.v:44089.3-44097.6" + wire $0\dp_INT_ra_logical0_3$next[0:0]$2394 + attribute \src "issuer_ls180.v:41528.3-41529.57" + wire $0\dp_INT_ra_logical0_3[0:0] + attribute \src "issuer_ls180.v:44146.3-44154.6" + wire $0\dp_INT_ra_mul0_6$next[0:0]$2412 + attribute \src "issuer_ls180.v:41522.3-41523.49" + wire $0\dp_INT_ra_mul0_6[0:0] + attribute \src "issuer_ls180.v:44165.3-44173.6" + wire $0\dp_INT_ra_shiftrot0_7$next[0:0]$2418 + attribute \src "issuer_ls180.v:41520.3-41521.59" + wire $0\dp_INT_ra_shiftrot0_7[0:0] + attribute \src "issuer_ls180.v:44108.3-44116.6" + wire $0\dp_INT_ra_spr0_4$next[0:0]$2400 + attribute \src "issuer_ls180.v:41526.3-41527.49" + wire $0\dp_INT_ra_spr0_4[0:0] + attribute \src "issuer_ls180.v:44070.3-44078.6" + wire $0\dp_INT_ra_trap0_2$next[0:0]$2388 + attribute \src "issuer_ls180.v:41530.3-41531.51" + wire $0\dp_INT_ra_trap0_2[0:0] + attribute \src "issuer_ls180.v:44203.3-44211.6" + wire $0\dp_INT_rb_alu0_0$next[0:0]$2430 + attribute \src "issuer_ls180.v:41516.3-41517.49" + wire $0\dp_INT_rb_alu0_0[0:0] + attribute \src "issuer_ls180.v:44222.3-44230.6" + wire $0\dp_INT_rb_cr0_1$next[0:0]$2434 + attribute \src "issuer_ls180.v:41514.3-41515.47" + wire $0\dp_INT_rb_cr0_1[0:0] + attribute \src "issuer_ls180.v:44279.3-44287.6" + wire $0\dp_INT_rb_div0_4$next[0:0]$2452 + attribute \src "issuer_ls180.v:41508.3-41509.49" + wire $0\dp_INT_rb_div0_4[0:0] + attribute \src "issuer_ls180.v:44336.3-44344.6" + wire $0\dp_INT_rb_ldst0_7$next[0:0]$2470 + attribute \src "issuer_ls180.v:41502.3-41503.51" + wire $0\dp_INT_rb_ldst0_7[0:0] + attribute \src "issuer_ls180.v:44260.3-44268.6" + wire $0\dp_INT_rb_logical0_3$next[0:0]$2446 + attribute \src "issuer_ls180.v:41510.3-41511.57" + wire $0\dp_INT_rb_logical0_3[0:0] + attribute \src "issuer_ls180.v:44298.3-44306.6" + wire $0\dp_INT_rb_mul0_5$next[0:0]$2458 + attribute \src "issuer_ls180.v:41506.3-41507.49" + wire $0\dp_INT_rb_mul0_5[0:0] + attribute \src "issuer_ls180.v:44317.3-44325.6" + wire $0\dp_INT_rb_shiftrot0_6$next[0:0]$2464 + attribute \src "issuer_ls180.v:41504.3-41505.59" + wire $0\dp_INT_rb_shiftrot0_6[0:0] + attribute \src "issuer_ls180.v:44241.3-44249.6" + wire $0\dp_INT_rb_trap0_2$next[0:0]$2440 + attribute \src "issuer_ls180.v:41512.3-41513.51" + wire $0\dp_INT_rb_trap0_2[0:0] + attribute \src "issuer_ls180.v:44374.3-44382.6" + wire $0\dp_INT_rc_ldst0_1$next[0:0]$2480 + attribute \src "issuer_ls180.v:41498.3-41499.51" + wire $0\dp_INT_rc_ldst0_1[0:0] + attribute \src "issuer_ls180.v:44355.3-44363.6" + wire $0\dp_INT_rc_shiftrot0_0$next[0:0]$2476 + attribute \src "issuer_ls180.v:41500.3-41501.59" + wire $0\dp_INT_rc_shiftrot0_0[0:0] + attribute \src "issuer_ls180.v:45147.3-45155.6" + wire $0\dp_SPR_spr1_spr0_0$next[0:0]$2620 + attribute \src "issuer_ls180.v:41456.3-41457.53" + wire $0\dp_SPR_spr1_spr0_0[0:0] + attribute \src "issuer_ls180.v:44675.3-44683.6" + wire $0\dp_XER_xer_ca_alu0_0$next[0:0]$2533 + attribute \src "issuer_ls180.v:41484.3-41485.57" + wire $0\dp_XER_xer_ca_alu0_0[0:0] + attribute \src "issuer_ls180.v:44742.3-44750.6" + wire $0\dp_XER_xer_ca_shiftrot0_2$next[0:0]$2544 + attribute \src "issuer_ls180.v:41480.3-41481.67" + wire $0\dp_XER_xer_ca_shiftrot0_2[0:0] + attribute \src "issuer_ls180.v:44723.3-44731.6" + wire $0\dp_XER_xer_ca_spr0_1$next[0:0]$2540 + attribute \src "issuer_ls180.v:41482.3-41483.57" + wire $0\dp_XER_xer_ca_spr0_1[0:0] + attribute \src "issuer_ls180.v:44791.3-44799.6" + wire $0\dp_XER_xer_ov_spr0_0$next[0:0]$2549 + attribute \src "issuer_ls180.v:41478.3-41479.57" + wire $0\dp_XER_xer_ov_spr0_0[0:0] + attribute \src "issuer_ls180.v:44420.3-44428.6" + wire $0\dp_XER_xer_so_alu0_0$next[0:0]$2492 + attribute \src "issuer_ls180.v:41496.3-41497.57" + wire $0\dp_XER_xer_so_alu0_0[0:0] + attribute \src "issuer_ls180.v:44568.3-44576.6" + wire $0\dp_XER_xer_so_div0_3$next[0:0]$2509 + attribute \src "issuer_ls180.v:41490.3-41491.57" + wire $0\dp_XER_xer_so_div0_3[0:0] + attribute \src "issuer_ls180.v:44439.3-44447.6" + wire $0\dp_XER_xer_so_logical0_1$next[0:0]$2498 + attribute \src "issuer_ls180.v:41494.3-41495.65" + wire $0\dp_XER_xer_so_logical0_1[0:0] + attribute \src "issuer_ls180.v:44608.3-44616.6" + wire $0\dp_XER_xer_so_mul0_4$next[0:0]$2520 + attribute \src "issuer_ls180.v:41488.3-41489.57" + wire $0\dp_XER_xer_so_mul0_4[0:0] + attribute \src "issuer_ls180.v:44627.3-44635.6" + wire $0\dp_XER_xer_so_shiftrot0_5$next[0:0]$2526 + attribute \src "issuer_ls180.v:41486.3-41487.67" + wire $0\dp_XER_xer_so_shiftrot0_5[0:0] + attribute \src "issuer_ls180.v:44549.3-44557.6" + wire $0\dp_XER_xer_so_spr0_2$next[0:0]$2505 + attribute \src "issuer_ls180.v:41492.3-41493.57" + wire $0\dp_XER_xer_so_spr0_2[0:0] + attribute \src "issuer_ls180.v:46399.3-46427.6" + wire $0\fus_cu_issue_i$10[0:0]$2784 + attribute \src "issuer_ls180.v:46895.3-46923.6" + wire $0\fus_cu_issue_i$13[0:0]$2809 + attribute \src "issuer_ls180.v:42280.3-42308.6" + wire $0\fus_cu_issue_i$16[0:0]$2278 + attribute \src "issuer_ls180.v:42776.3-42804.6" + wire $0\fus_cu_issue_i$19[0:0]$2303 + attribute \src "issuer_ls180.v:43098.3-43126.6" + wire $0\fus_cu_issue_i$22[0:0]$2322 + attribute \src "issuer_ls180.v:43536.3-43564.6" + wire $0\fus_cu_issue_i$25[0:0]$2345 + attribute \src "issuer_ls180.v:43974.3-44002.6" + wire $0\fus_cu_issue_i$28[0:0]$2368 + attribute \src "issuer_ls180.v:45667.3-45695.6" + wire $0\fus_cu_issue_i$4[0:0]$2689 + attribute \src "issuer_ls180.v:46064.3-46092.6" + wire $0\fus_cu_issue_i$7[0:0]$2751 + attribute \src "issuer_ls180.v:45459.3-45487.6" + wire $0\fus_cu_issue_i[0:0] + attribute \src "issuer_ls180.v:46428.3-46456.6" + wire width 4 $0\fus_cu_rdmaskn_i$12[3:0]$2789 + attribute \src "issuer_ls180.v:46924.3-46952.6" + wire width 3 $0\fus_cu_rdmaskn_i$15[2:0]$2814 + attribute \src "issuer_ls180.v:42309.3-42337.6" + wire width 6 $0\fus_cu_rdmaskn_i$18[5:0]$2283 + attribute \src "issuer_ls180.v:42805.3-42833.6" + wire width 3 $0\fus_cu_rdmaskn_i$21[2:0]$2308 + attribute \src "issuer_ls180.v:43127.3-43155.6" + wire width 3 $0\fus_cu_rdmaskn_i$24[2:0]$2327 + attribute \src "issuer_ls180.v:43565.3-43593.6" + wire width 5 $0\fus_cu_rdmaskn_i$27[4:0]$2350 + attribute \src "issuer_ls180.v:44003.3-44031.6" + wire width 3 $0\fus_cu_rdmaskn_i$30[2:0]$2373 + attribute \src "issuer_ls180.v:45714.3-45742.6" + wire width 6 $0\fus_cu_rdmaskn_i$6[5:0]$2700 + attribute \src "issuer_ls180.v:46102.3-46130.6" + wire width 3 $0\fus_cu_rdmaskn_i$9[2:0]$2759 + attribute \src "issuer_ls180.v:45497.3-45525.6" + wire width 4 $0\fus_cu_rdmaskn_i[3:0] + attribute \src "issuer_ls180.v:45374.3-45402.6" + wire width 4 $0\fus_oper_i_alu_alu0__data_len[3:0] + attribute \src "issuer_ls180.v:44694.3-44722.6" + wire width 12 $0\fus_oper_i_alu_alu0__fn_unit[11:0] + attribute \src "issuer_ls180.v:44761.3-44790.6" + wire width 64 $0\fus_oper_i_alu_alu0__imm_data__data[63:0] + attribute \src "issuer_ls180.v:44761.3-44790.6" + wire $0\fus_oper_i_alu_alu0__imm_data__ok[0:0] + attribute \src "issuer_ls180.v:45213.3-45241.6" + wire width 2 $0\fus_oper_i_alu_alu0__input_carry[1:0] + attribute \src "issuer_ls180.v:45421.3-45449.6" + wire width 32 $0\fus_oper_i_alu_alu0__insn[31:0] + attribute \src "issuer_ls180.v:44636.3-44664.6" + wire width 7 $0\fus_oper_i_alu_alu0__insn_type[6:0] + attribute \src "issuer_ls180.v:45003.3-45031.6" + wire $0\fus_oper_i_alu_alu0__invert_in[0:0] + attribute \src "issuer_ls180.v:45118.3-45146.6" + wire $0\fus_oper_i_alu_alu0__invert_out[0:0] + attribute \src "issuer_ls180.v:45298.3-45326.6" + wire $0\fus_oper_i_alu_alu0__is_32bit[0:0] + attribute \src "issuer_ls180.v:45336.3-45364.6" + wire $0\fus_oper_i_alu_alu0__is_signed[0:0] + attribute \src "issuer_ls180.v:44916.3-44945.6" + wire $0\fus_oper_i_alu_alu0__oe__oe[0:0] + attribute \src "issuer_ls180.v:44916.3-44945.6" + wire $0\fus_oper_i_alu_alu0__oe__ok[0:0] + attribute \src "issuer_ls180.v:45251.3-45279.6" + wire $0\fus_oper_i_alu_alu0__output_carry[0:0] + attribute \src "issuer_ls180.v:44829.3-44858.6" + wire $0\fus_oper_i_alu_alu0__rc__ok[0:0] + attribute \src "issuer_ls180.v:44829.3-44858.6" + wire $0\fus_oper_i_alu_alu0__rc__rc[0:0] + attribute \src "issuer_ls180.v:45166.3-45194.6" + wire $0\fus_oper_i_alu_alu0__write_cr0[0:0] + attribute \src "issuer_ls180.v:45060.3-45088.6" + wire $0\fus_oper_i_alu_alu0__zero_a[0:0] + attribute \src "issuer_ls180.v:45752.3-45780.6" + wire width 64 $0\fus_oper_i_alu_branch0__cia[63:0] + attribute \src "issuer_ls180.v:45837.3-45865.6" + wire width 12 $0\fus_oper_i_alu_branch0__fn_unit[11:0] + attribute \src "issuer_ls180.v:45922.3-45951.6" + wire width 64 $0\fus_oper_i_alu_branch0__imm_data__data[63:0] + attribute \src "issuer_ls180.v:45922.3-45951.6" + wire $0\fus_oper_i_alu_branch0__imm_data__ok[0:0] + attribute \src "issuer_ls180.v:45875.3-45903.6" + wire width 32 $0\fus_oper_i_alu_branch0__insn[31:0] + attribute \src "issuer_ls180.v:45799.3-45827.6" + wire width 7 $0\fus_oper_i_alu_branch0__insn_type[6:0] + attribute \src "issuer_ls180.v:46017.3-46045.6" + wire $0\fus_oper_i_alu_branch0__is_32bit[0:0] + attribute \src "issuer_ls180.v:45979.3-46007.6" + wire $0\fus_oper_i_alu_branch0__lk[0:0] + attribute \src "issuer_ls180.v:45582.3-45610.6" + wire width 12 $0\fus_oper_i_alu_cr0__fn_unit[11:0] + attribute \src "issuer_ls180.v:45629.3-45657.6" + wire width 32 $0\fus_oper_i_alu_cr0__insn[31:0] + attribute \src "issuer_ls180.v:45544.3-45572.6" + wire width 7 $0\fus_oper_i_alu_cr0__insn_type[6:0] + attribute \src "issuer_ls180.v:42718.3-42746.6" + wire width 4 $0\fus_oper_i_alu_div0__data_len[3:0] + attribute \src "issuer_ls180.v:42367.3-42395.6" + wire width 12 $0\fus_oper_i_alu_div0__fn_unit[11:0] + attribute \src "issuer_ls180.v:42396.3-42425.6" + wire width 64 $0\fus_oper_i_alu_div0__imm_data__data[63:0] + attribute \src "issuer_ls180.v:42396.3-42425.6" + wire $0\fus_oper_i_alu_div0__imm_data__ok[0:0] + attribute \src "issuer_ls180.v:42544.3-42572.6" + wire width 2 $0\fus_oper_i_alu_div0__input_carry[1:0] + attribute \src "issuer_ls180.v:42747.3-42775.6" + wire width 32 $0\fus_oper_i_alu_div0__insn[31:0] + attribute \src "issuer_ls180.v:42338.3-42366.6" + wire width 7 $0\fus_oper_i_alu_div0__insn_type[6:0] + attribute \src "issuer_ls180.v:42486.3-42514.6" + wire $0\fus_oper_i_alu_div0__invert_in[0:0] + attribute \src "issuer_ls180.v:42573.3-42601.6" + wire $0\fus_oper_i_alu_div0__invert_out[0:0] + attribute \src "issuer_ls180.v:42660.3-42688.6" + wire $0\fus_oper_i_alu_div0__is_32bit[0:0] + attribute \src "issuer_ls180.v:42689.3-42717.6" + wire $0\fus_oper_i_alu_div0__is_signed[0:0] + attribute \src "issuer_ls180.v:42456.3-42485.6" + wire $0\fus_oper_i_alu_div0__oe__oe[0:0] + attribute \src "issuer_ls180.v:42456.3-42485.6" + wire $0\fus_oper_i_alu_div0__oe__ok[0:0] + attribute \src "issuer_ls180.v:42631.3-42659.6" + wire $0\fus_oper_i_alu_div0__output_carry[0:0] + attribute \src "issuer_ls180.v:42426.3-42455.6" + wire $0\fus_oper_i_alu_div0__rc__ok[0:0] + attribute \src "issuer_ls180.v:42426.3-42455.6" + wire $0\fus_oper_i_alu_div0__rc__rc[0:0] + attribute \src "issuer_ls180.v:42602.3-42630.6" + wire $0\fus_oper_i_alu_div0__write_cr0[0:0] + attribute \src "issuer_ls180.v:42515.3-42543.6" + wire $0\fus_oper_i_alu_div0__zero_a[0:0] + attribute \src "issuer_ls180.v:46837.3-46865.6" + wire width 4 $0\fus_oper_i_alu_logical0__data_len[3:0] + attribute \src "issuer_ls180.v:46486.3-46514.6" + wire width 12 $0\fus_oper_i_alu_logical0__fn_unit[11:0] + attribute \src "issuer_ls180.v:46515.3-46544.6" + wire width 64 $0\fus_oper_i_alu_logical0__imm_data__data[63:0] + attribute \src "issuer_ls180.v:46515.3-46544.6" + wire $0\fus_oper_i_alu_logical0__imm_data__ok[0:0] + attribute \src "issuer_ls180.v:46663.3-46691.6" + wire width 2 $0\fus_oper_i_alu_logical0__input_carry[1:0] + attribute \src "issuer_ls180.v:46866.3-46894.6" + wire width 32 $0\fus_oper_i_alu_logical0__insn[31:0] + attribute \src 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"issuer_ls180.v:46721.3-46749.6" + wire $0\fus_oper_i_alu_logical0__write_cr0[0:0] + attribute \src "issuer_ls180.v:46634.3-46662.6" + wire $0\fus_oper_i_alu_logical0__zero_a[0:0] + attribute \src "issuer_ls180.v:42863.3-42891.6" + wire width 12 $0\fus_oper_i_alu_mul0__fn_unit[11:0] + attribute \src "issuer_ls180.v:42892.3-42921.6" + wire width 64 $0\fus_oper_i_alu_mul0__imm_data__data[63:0] + attribute \src "issuer_ls180.v:42892.3-42921.6" + wire $0\fus_oper_i_alu_mul0__imm_data__ok[0:0] + attribute \src "issuer_ls180.v:43069.3-43097.6" + wire width 32 $0\fus_oper_i_alu_mul0__insn[31:0] + attribute \src "issuer_ls180.v:42834.3-42862.6" + wire width 7 $0\fus_oper_i_alu_mul0__insn_type[6:0] + attribute \src "issuer_ls180.v:43011.3-43039.6" + wire $0\fus_oper_i_alu_mul0__is_32bit[0:0] + attribute \src "issuer_ls180.v:43040.3-43068.6" + wire $0\fus_oper_i_alu_mul0__is_signed[0:0] + attribute \src "issuer_ls180.v:42952.3-42981.6" + wire $0\fus_oper_i_alu_mul0__oe__oe[0:0] + attribute \src "issuer_ls180.v:42952.3-42981.6" + wire $0\fus_oper_i_alu_mul0__oe__ok[0:0] + attribute \src "issuer_ls180.v:42922.3-42951.6" + wire $0\fus_oper_i_alu_mul0__rc__ok[0:0] + attribute \src "issuer_ls180.v:42922.3-42951.6" + wire $0\fus_oper_i_alu_mul0__rc__rc[0:0] + attribute \src "issuer_ls180.v:42982.3-43010.6" + wire $0\fus_oper_i_alu_mul0__write_cr0[0:0] + attribute \src "issuer_ls180.v:43185.3-43213.6" + wire width 12 $0\fus_oper_i_alu_shift_rot0__fn_unit[11:0] + attribute \src "issuer_ls180.v:43214.3-43243.6" + wire width 64 $0\fus_oper_i_alu_shift_rot0__imm_data__data[63:0] + attribute \src "issuer_ls180.v:43214.3-43243.6" + wire $0\fus_oper_i_alu_shift_rot0__imm_data__ok[0:0] + attribute \src "issuer_ls180.v:43333.3-43361.6" + wire width 2 $0\fus_oper_i_alu_shift_rot0__input_carry[1:0] + attribute \src "issuer_ls180.v:43391.3-43419.6" + wire $0\fus_oper_i_alu_shift_rot0__input_cr[0:0] + attribute \src "issuer_ls180.v:43507.3-43535.6" + wire width 32 $0\fus_oper_i_alu_shift_rot0__insn[31:0] + attribute \src "issuer_ls180.v:43156.3-43184.6" + wire width 7 $0\fus_oper_i_alu_shift_rot0__insn_type[6:0] + attribute \src "issuer_ls180.v:43449.3-43477.6" + wire $0\fus_oper_i_alu_shift_rot0__is_32bit[0:0] + attribute \src "issuer_ls180.v:43478.3-43506.6" + wire $0\fus_oper_i_alu_shift_rot0__is_signed[0:0] + attribute \src "issuer_ls180.v:43274.3-43303.6" + wire $0\fus_oper_i_alu_shift_rot0__oe__oe[0:0] + attribute \src "issuer_ls180.v:43274.3-43303.6" + wire $0\fus_oper_i_alu_shift_rot0__oe__ok[0:0] + attribute \src "issuer_ls180.v:43362.3-43390.6" + wire $0\fus_oper_i_alu_shift_rot0__output_carry[0:0] + attribute \src "issuer_ls180.v:43420.3-43448.6" + wire $0\fus_oper_i_alu_shift_rot0__output_cr[0:0] + attribute \src "issuer_ls180.v:43244.3-43273.6" + wire $0\fus_oper_i_alu_shift_rot0__rc__ok[0:0] + attribute \src "issuer_ls180.v:43244.3-43273.6" + wire $0\fus_oper_i_alu_shift_rot0__rc__rc[0:0] + attribute \src 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attribute \src "issuer_ls180.v:46254.3-46282.6" + wire width 64 $0\fus_oper_i_alu_trap0__msr[63:0] + attribute \src "issuer_ls180.v:46370.3-46398.6" + wire width 13 $0\fus_oper_i_alu_trap0__trapaddr[12:0] + attribute \src "issuer_ls180.v:46341.3-46369.6" + wire width 7 $0\fus_oper_i_alu_trap0__traptype[6:0] + attribute \src "issuer_ls180.v:43858.3-43886.6" + wire $0\fus_oper_i_ldst_ldst0__byte_reverse[0:0] + attribute \src "issuer_ls180.v:43829.3-43857.6" + wire width 4 $0\fus_oper_i_ldst_ldst0__data_len[3:0] + attribute \src "issuer_ls180.v:43623.3-43651.6" + wire width 12 $0\fus_oper_i_ldst_ldst0__fn_unit[11:0] + attribute \src "issuer_ls180.v:43652.3-43681.6" + wire width 64 $0\fus_oper_i_ldst_ldst0__imm_data__data[63:0] + attribute \src "issuer_ls180.v:43652.3-43681.6" + wire $0\fus_oper_i_ldst_ldst0__imm_data__ok[0:0] + attribute \src "issuer_ls180.v:43945.3-43973.6" + wire width 32 $0\fus_oper_i_ldst_ldst0__insn[31:0] + attribute \src "issuer_ls180.v:43594.3-43622.6" + wire width 7 $0\fus_oper_i_ldst_ldst0__insn_type[6:0] + attribute \src "issuer_ls180.v:43771.3-43799.6" + wire $0\fus_oper_i_ldst_ldst0__is_32bit[0:0] + attribute \src "issuer_ls180.v:43800.3-43828.6" + wire $0\fus_oper_i_ldst_ldst0__is_signed[0:0] + attribute \src "issuer_ls180.v:43916.3-43944.6" + wire width 2 $0\fus_oper_i_ldst_ldst0__ldst_mode[1:0] + attribute \src "issuer_ls180.v:43741.3-43770.6" + wire $0\fus_oper_i_ldst_ldst0__oe__oe[0:0] + attribute \src "issuer_ls180.v:43741.3-43770.6" + wire $0\fus_oper_i_ldst_ldst0__oe__ok[0:0] + attribute \src "issuer_ls180.v:43711.3-43740.6" + wire $0\fus_oper_i_ldst_ldst0__rc__ok[0:0] + attribute \src "issuer_ls180.v:43711.3-43740.6" + wire $0\fus_oper_i_ldst_ldst0__rc__rc[0:0] + attribute \src "issuer_ls180.v:43887.3-43915.6" + wire $0\fus_oper_i_ldst_ldst0__sign_extend[0:0] + attribute \src "issuer_ls180.v:43682.3-43710.6" + wire $0\fus_oper_i_ldst_ldst0__zero_a[0:0] + attribute \src "issuer_ls180.v:44060.3-44069.6" + wire width 64 $0\fus_src1_i$33[63:0]$2385 + attribute \src "issuer_ls180.v:44079.3-44088.6" + wire width 64 $0\fus_src1_i$36[63:0]$2391 + attribute \src "issuer_ls180.v:44098.3-44107.6" + wire width 64 $0\fus_src1_i$39[63:0]$2397 + attribute \src "issuer_ls180.v:44117.3-44126.6" + wire width 64 $0\fus_src1_i$42[63:0]$2403 + attribute \src "issuer_ls180.v:44136.3-44145.6" + wire width 64 $0\fus_src1_i$45[63:0]$2409 + attribute \src "issuer_ls180.v:44155.3-44164.6" + wire width 64 $0\fus_src1_i$48[63:0]$2415 + attribute \src "issuer_ls180.v:44174.3-44183.6" + wire width 64 $0\fus_src1_i$51[63:0]$2421 + attribute \src "issuer_ls180.v:44193.3-44202.6" + wire width 64 $0\fus_src1_i$54[63:0]$2427 + attribute \src "issuer_ls180.v:44974.3-44983.6" + wire width 64 $0\fus_src1_i$77[63:0]$2590 + attribute \src "issuer_ls180.v:44041.3-44050.6" + wire width 64 $0\fus_src1_i[63:0] + attribute \src "issuer_ls180.v:44231.3-44240.6" + wire width 64 $0\fus_src2_i$55[63:0]$2437 + attribute \src "issuer_ls180.v:44250.3-44259.6" + wire width 64 $0\fus_src2_i$56[63:0]$2443 + attribute \src "issuer_ls180.v:44269.3-44278.6" + wire width 64 $0\fus_src2_i$57[63:0]$2449 + attribute \src "issuer_ls180.v:44288.3-44297.6" + wire width 64 $0\fus_src2_i$58[63:0]$2455 + attribute \src "issuer_ls180.v:44307.3-44316.6" + wire width 64 $0\fus_src2_i$59[63:0]$2461 + attribute \src "issuer_ls180.v:44326.3-44335.6" + wire width 64 $0\fus_src2_i$60[63:0]$2467 + attribute \src "issuer_ls180.v:44345.3-44354.6" + wire width 64 $0\fus_src2_i$61[63:0]$2473 + attribute \src "issuer_ls180.v:45089.3-45098.6" + wire width 64 $0\fus_src2_i$80[63:0]$2610 + attribute \src "issuer_ls180.v:45156.3-45165.6" + wire width 64 $0\fus_src2_i$82[63:0]$2623 + attribute \src "issuer_ls180.v:44212.3-44221.6" + wire width 64 $0\fus_src2_i[63:0] + attribute \src "issuer_ls180.v:44383.3-44392.6" + wire width 64 $0\fus_src3_i$62[63:0]$2483 + attribute \src "issuer_ls180.v:44429.3-44438.6" + wire $0\fus_src3_i$63[0:0]$2495 + attribute \src "issuer_ls180.v:44539.3-44548.6" + wire $0\fus_src3_i$64[0:0]$2502 + attribute \src "issuer_ls180.v:44598.3-44607.6" + wire $0\fus_src3_i$65[0:0]$2517 + attribute \src "issuer_ls180.v:44617.3-44626.6" + wire $0\fus_src3_i$66[0:0]$2523 + attribute \src "issuer_ls180.v:44819.3-44828.6" + wire width 32 $0\fus_src3_i$70[31:0]$2558 + attribute \src "issuer_ls180.v:44887.3-44896.6" + wire width 4 $0\fus_src3_i$74[3:0]$2571 + attribute \src "issuer_ls180.v:44993.3-45002.6" + wire width 64 $0\fus_src3_i$78[63:0]$2596 + attribute \src "issuer_ls180.v:45041.3-45050.6" + wire width 64 $0\fus_src3_i$79[63:0]$2603 + attribute \src "issuer_ls180.v:44364.3-44373.6" + wire width 64 $0\fus_src3_i[63:0] + attribute \src "issuer_ls180.v:44665.3-44674.6" + wire $0\fus_src4_i$67[0:0]$2530 + attribute \src "issuer_ls180.v:44684.3-44693.6" + wire width 2 $0\fus_src4_i$68[1:0]$2536 + attribute \src "issuer_ls180.v:44868.3-44877.6" + wire width 4 $0\fus_src4_i$71[3:0]$2565 + attribute \src "issuer_ls180.v:45108.3-45117.6" + wire width 64 $0\fus_src4_i$81[63:0]$2616 + attribute \src "issuer_ls180.v:44558.3-44567.6" + wire $0\fus_src4_i[0:0] + attribute \src "issuer_ls180.v:44800.3-44809.6" + wire width 2 $0\fus_src5_i$69[1:0]$2552 + attribute \src "issuer_ls180.v:44906.3-44915.6" + wire width 4 $0\fus_src5_i$75[3:0]$2577 + attribute \src "issuer_ls180.v:44751.3-44760.6" + wire width 2 $0\fus_src5_i[1:0] + attribute \src "issuer_ls180.v:44955.3-44964.6" + wire width 4 $0\fus_src6_i$76[3:0]$2584 + attribute \src "issuer_ls180.v:44732.3-44741.6" + wire width 2 $0\fus_src6_i[1:0] + attribute \src "issuer_ls180.v:34906.7-34906.20" + wire $0\initial[0:0] + attribute \src "issuer_ls180.v:45280.3-45288.6" + wire $0\wr_pick_dly$1007$next[0:0]$2638 + attribute \src "issuer_ls180.v:41448.3-41449.51" + wire $0\wr_pick_dly$1007[0:0]$2228 + attribute \src "issuer_ls180.v:40280.7-40280.32" + wire $0\wr_pick_dly$1007[0:0]$2866 + attribute \src "issuer_ls180.v:45289.3-45297.6" + wire $0\wr_pick_dly$1025$next[0:0]$2641 + attribute \src "issuer_ls180.v:41446.3-41447.51" + wire $0\wr_pick_dly$1025[0:0]$2226 + attribute \src "issuer_ls180.v:40284.7-40284.32" + wire $0\wr_pick_dly$1025[0:0]$2868 + attribute \src "issuer_ls180.v:45327.3-45335.6" + wire $0\wr_pick_dly$1047$next[0:0]$2645 + attribute \src "issuer_ls180.v:41444.3-41445.51" + wire $0\wr_pick_dly$1047[0:0]$2224 + attribute \src "issuer_ls180.v:40288.7-40288.32" + wire $0\wr_pick_dly$1047[0:0]$2870 + attribute \src "issuer_ls180.v:45365.3-45373.6" + wire $0\wr_pick_dly$1067$next[0:0]$2649 + attribute \src "issuer_ls180.v:41442.3-41443.51" + wire $0\wr_pick_dly$1067[0:0]$2222 + attribute \src "issuer_ls180.v:40292.7-40292.32" + wire $0\wr_pick_dly$1067[0:0]$2872 + attribute \src "issuer_ls180.v:45403.3-45411.6" + wire $0\wr_pick_dly$1087$next[0:0]$2653 + attribute \src "issuer_ls180.v:41440.3-41441.51" + wire $0\wr_pick_dly$1087[0:0]$2220 + attribute \src "issuer_ls180.v:40296.7-40296.32" + wire $0\wr_pick_dly$1087[0:0]$2874 + attribute \src "issuer_ls180.v:45412.3-45420.6" + wire $0\wr_pick_dly$1106$next[0:0]$2656 + attribute \src "issuer_ls180.v:41438.3-41439.51" + wire $0\wr_pick_dly$1106[0:0]$2218 + attribute \src "issuer_ls180.v:40300.7-40300.32" + wire $0\wr_pick_dly$1106[0:0]$2876 + attribute \src "issuer_ls180.v:45450.3-45458.6" + wire $0\wr_pick_dly$1124$next[0:0]$2660 + attribute \src "issuer_ls180.v:41436.3-41437.51" + wire $0\wr_pick_dly$1124[0:0]$2216 + attribute \src "issuer_ls180.v:40304.7-40304.32" + wire $0\wr_pick_dly$1124[0:0]$2878 + attribute \src "issuer_ls180.v:45488.3-45496.6" + wire $0\wr_pick_dly$1197$next[0:0]$2664 + attribute \src "issuer_ls180.v:41434.3-41435.51" + wire $0\wr_pick_dly$1197[0:0]$2214 + attribute \src "issuer_ls180.v:40308.7-40308.32" + wire $0\wr_pick_dly$1197[0:0]$2880 + attribute \src "issuer_ls180.v:45526.3-45534.6" + wire $0\wr_pick_dly$1225$next[0:0]$2668 + attribute \src "issuer_ls180.v:41432.3-41433.51" + wire $0\wr_pick_dly$1225[0:0]$2212 + attribute \src "issuer_ls180.v:40312.7-40312.32" + wire $0\wr_pick_dly$1225[0:0]$2882 + attribute \src "issuer_ls180.v:45535.3-45543.6" + wire $0\wr_pick_dly$1245$next[0:0]$2671 + attribute \src "issuer_ls180.v:41430.3-41431.51" + wire $0\wr_pick_dly$1245[0:0]$2210 + attribute \src "issuer_ls180.v:40316.7-40316.32" + wire $0\wr_pick_dly$1245[0:0]$2884 + attribute \src "issuer_ls180.v:45573.3-45581.6" + wire $0\wr_pick_dly$1265$next[0:0]$2675 + attribute \src "issuer_ls180.v:41428.3-41429.51" + wire $0\wr_pick_dly$1265[0:0]$2208 + attribute \src "issuer_ls180.v:40320.7-40320.32" + wire $0\wr_pick_dly$1265[0:0]$2886 + attribute \src "issuer_ls180.v:45611.3-45619.6" + wire $0\wr_pick_dly$1285$next[0:0]$2679 + attribute \src "issuer_ls180.v:41426.3-41427.51" + wire $0\wr_pick_dly$1285[0:0]$2206 + attribute \src "issuer_ls180.v:40324.7-40324.32" + wire $0\wr_pick_dly$1285[0:0]$2888 + attribute \src "issuer_ls180.v:45620.3-45628.6" + wire $0\wr_pick_dly$1305$next[0:0]$2682 + attribute \src "issuer_ls180.v:41424.3-41425.51" + wire $0\wr_pick_dly$1305[0:0]$2204 + attribute \src "issuer_ls180.v:40328.7-40328.32" + wire $0\wr_pick_dly$1305[0:0]$2890 + attribute \src "issuer_ls180.v:45658.3-45666.6" + wire $0\wr_pick_dly$1325$next[0:0]$2686 + attribute \src "issuer_ls180.v:41422.3-41423.51" + wire $0\wr_pick_dly$1325[0:0]$2202 + attribute \src "issuer_ls180.v:40332.7-40332.32" + wire $0\wr_pick_dly$1325[0:0]$2892 + attribute \src "issuer_ls180.v:45696.3-45704.6" + wire $0\wr_pick_dly$1372$next[0:0]$2694 + attribute \src "issuer_ls180.v:41420.3-41421.51" + wire $0\wr_pick_dly$1372[0:0]$2200 + attribute \src "issuer_ls180.v:40336.7-40336.32" + wire $0\wr_pick_dly$1372[0:0]$2894 + attribute \src "issuer_ls180.v:45705.3-45713.6" + wire $0\wr_pick_dly$1388$next[0:0]$2697 + attribute \src "issuer_ls180.v:41418.3-41419.51" + wire $0\wr_pick_dly$1388[0:0]$2198 + attribute \src "issuer_ls180.v:40340.7-40340.32" + wire $0\wr_pick_dly$1388[0:0]$2896 + attribute \src "issuer_ls180.v:45743.3-45751.6" + wire $0\wr_pick_dly$1404$next[0:0]$2705 + attribute \src "issuer_ls180.v:41416.3-41417.51" + wire $0\wr_pick_dly$1404[0:0]$2196 + attribute \src "issuer_ls180.v:40344.7-40344.32" + wire $0\wr_pick_dly$1404[0:0]$2898 + attribute \src "issuer_ls180.v:45781.3-45789.6" + wire $0\wr_pick_dly$1438$next[0:0]$2709 + attribute \src "issuer_ls180.v:41414.3-41415.51" + wire $0\wr_pick_dly$1438[0:0]$2194 + attribute \src "issuer_ls180.v:40348.7-40348.32" + wire $0\wr_pick_dly$1438[0:0]$2900 + attribute \src "issuer_ls180.v:45790.3-45798.6" + wire $0\wr_pick_dly$1454$next[0:0]$2712 + attribute \src "issuer_ls180.v:41412.3-41413.51" + wire $0\wr_pick_dly$1454[0:0]$2192 + attribute \src "issuer_ls180.v:40352.7-40352.32" + wire $0\wr_pick_dly$1454[0:0]$2902 + attribute \src "issuer_ls180.v:45828.3-45836.6" + wire $0\wr_pick_dly$1470$next[0:0]$2716 + attribute \src "issuer_ls180.v:41410.3-41411.51" + wire $0\wr_pick_dly$1470[0:0]$2190 + attribute \src "issuer_ls180.v:40356.7-40356.32" + wire $0\wr_pick_dly$1470[0:0]$2904 + attribute \src "issuer_ls180.v:45866.3-45874.6" + wire $0\wr_pick_dly$1486$next[0:0]$2720 + attribute \src "issuer_ls180.v:41408.3-41409.51" + wire $0\wr_pick_dly$1486[0:0]$2188 + attribute \src "issuer_ls180.v:40360.7-40360.32" + wire $0\wr_pick_dly$1486[0:0]$2906 + attribute \src "issuer_ls180.v:45904.3-45912.6" + wire $0\wr_pick_dly$1522$next[0:0]$2724 + attribute \src "issuer_ls180.v:41406.3-41407.51" + wire $0\wr_pick_dly$1522[0:0]$2186 + attribute \src "issuer_ls180.v:40364.7-40364.32" + wire $0\wr_pick_dly$1522[0:0]$2908 + attribute \src "issuer_ls180.v:45913.3-45921.6" + wire $0\wr_pick_dly$1538$next[0:0]$2727 + attribute \src "issuer_ls180.v:41404.3-41405.51" + wire $0\wr_pick_dly$1538[0:0]$2184 + attribute \src "issuer_ls180.v:40368.7-40368.32" + wire $0\wr_pick_dly$1538[0:0]$2910 + attribute \src "issuer_ls180.v:45952.3-45960.6" + wire $0\wr_pick_dly$1554$next[0:0]$2731 + attribute \src "issuer_ls180.v:41402.3-41403.51" + wire $0\wr_pick_dly$1554[0:0]$2182 + attribute \src "issuer_ls180.v:40372.7-40372.32" + wire $0\wr_pick_dly$1554[0:0]$2912 + attribute \src "issuer_ls180.v:45961.3-45969.6" + wire $0\wr_pick_dly$1570$next[0:0]$2734 + attribute \src "issuer_ls180.v:41400.3-41401.51" + wire $0\wr_pick_dly$1570[0:0]$2180 + attribute \src "issuer_ls180.v:40376.7-40376.32" + wire $0\wr_pick_dly$1570[0:0]$2914 + attribute \src "issuer_ls180.v:45970.3-45978.6" + wire $0\wr_pick_dly$1612$next[0:0]$2737 + attribute \src "issuer_ls180.v:41398.3-41399.51" + wire $0\wr_pick_dly$1612[0:0]$2178 + attribute \src "issuer_ls180.v:40380.7-40380.32" + wire $0\wr_pick_dly$1612[0:0]$2916 + attribute \src "issuer_ls180.v:46008.3-46016.6" + wire $0\wr_pick_dly$1631$next[0:0]$2741 + attribute \src "issuer_ls180.v:41396.3-41397.51" + wire $0\wr_pick_dly$1631[0:0]$2176 + attribute \src "issuer_ls180.v:40384.7-40384.32" + wire $0\wr_pick_dly$1631[0:0]$2918 + attribute \src "issuer_ls180.v:46046.3-46054.6" + wire $0\wr_pick_dly$1647$next[0:0]$2745 + attribute \src "issuer_ls180.v:41394.3-41395.51" + wire $0\wr_pick_dly$1647[0:0]$2174 + attribute \src "issuer_ls180.v:40388.7-40388.32" + wire $0\wr_pick_dly$1647[0:0]$2920 + attribute \src "issuer_ls180.v:46055.3-46063.6" + wire $0\wr_pick_dly$1663$next[0:0]$2748 + attribute \src "issuer_ls180.v:41392.3-41393.51" + wire $0\wr_pick_dly$1663[0:0]$2172 + attribute \src "issuer_ls180.v:40392.7-40392.32" + wire $0\wr_pick_dly$1663[0:0]$2922 + attribute \src "issuer_ls180.v:46093.3-46101.6" + wire $0\wr_pick_dly$1679$next[0:0]$2756 + attribute \src "issuer_ls180.v:41390.3-41391.51" + wire $0\wr_pick_dly$1679[0:0]$2170 + attribute \src "issuer_ls180.v:40396.7-40396.32" + wire $0\wr_pick_dly$1679[0:0]$2924 + attribute \src "issuer_ls180.v:46131.3-46139.6" + wire $0\wr_pick_dly$1723$next[0:0]$2764 + attribute \src "issuer_ls180.v:41388.3-41389.51" + wire $0\wr_pick_dly$1723[0:0]$2168 + attribute \src "issuer_ls180.v:40400.7-40400.32" + wire $0\wr_pick_dly$1723[0:0]$2926 + attribute \src "issuer_ls180.v:46140.3-46148.6" + wire $0\wr_pick_dly$1739$next[0:0]$2767 + attribute \src "issuer_ls180.v:41386.3-41387.51" + wire $0\wr_pick_dly$1739[0:0]$2166 + attribute \src "issuer_ls180.v:40404.7-40404.32" + wire $0\wr_pick_dly$1739[0:0]$2928 + attribute \src "issuer_ls180.v:46178.3-46186.6" + wire $0\wr_pick_dly$1763$next[0:0]$2771 + attribute \src "issuer_ls180.v:41384.3-41385.51" + wire $0\wr_pick_dly$1763[0:0]$2164 + attribute \src "issuer_ls180.v:40408.7-40408.32" + wire $0\wr_pick_dly$1763[0:0]$2930 + attribute \src "issuer_ls180.v:46216.3-46224.6" + wire $0\wr_pick_dly$1783$next[0:0]$2775 + attribute \src "issuer_ls180.v:41382.3-41383.51" + wire $0\wr_pick_dly$1783[0:0]$2162 + attribute \src "issuer_ls180.v:40412.7-40412.32" + wire $0\wr_pick_dly$1783[0:0]$2932 + attribute \src "issuer_ls180.v:45204.3-45212.6" + wire $0\wr_pick_dly$967$next[0:0]$2630 + attribute \src "issuer_ls180.v:41452.3-41453.49" + wire $0\wr_pick_dly$967[0:0]$2232 + attribute \src "issuer_ls180.v:40416.7-40416.31" + wire $0\wr_pick_dly$967[0:0]$2934 + attribute \src "issuer_ls180.v:45242.3-45250.6" + wire $0\wr_pick_dly$986$next[0:0]$2634 + attribute \src "issuer_ls180.v:41450.3-41451.49" + wire $0\wr_pick_dly$986[0:0]$2230 + attribute \src "issuer_ls180.v:40420.7-40420.31" + wire $0\wr_pick_dly$986[0:0]$2936 + attribute \src "issuer_ls180.v:45195.3-45203.6" + wire $0\wr_pick_dly$next[0:0]$2627 + attribute \src "issuer_ls180.v:41454.3-41455.39" + wire $0\wr_pick_dly[0:0] + attribute \src "issuer_ls180.v:44448.3-44538.6" + wire $10\corebusy_o[0:0] + attribute \src "issuer_ls180.v:44448.3-44538.6" + wire $11\corebusy_o[0:0] + attribute \src "issuer_ls180.v:44448.3-44538.6" + wire $12\corebusy_o[0:0] + attribute \src "issuer_ls180.v:44448.3-44538.6" + wire $13\corebusy_o[0:0] + attribute \src "issuer_ls180.v:44577.3-44597.6" + wire $1\core_terminate_o$next[0:0]$2513 + attribute \src "issuer_ls180.v:36924.7-36924.30" + wire $1\core_terminate_o[0:0] + attribute \src "issuer_ls180.v:44448.3-44538.6" + wire $1\corebusy_o[0:0] + attribute \src "issuer_ls180.v:44393.3-44419.6" + wire width 2 $1\counter$next[1:0]$2487 + attribute \src "issuer_ls180.v:36937.13-36937.27" + wire width 2 $1\counter[1:0] + attribute \src "issuer_ls180.v:44878.3-44886.6" + wire $1\dp_CR_cr_a_branch0_1$next[0:0]$2569 + attribute \src "issuer_ls180.v:38065.7-38065.34" + wire $1\dp_CR_cr_a_branch0_1[0:0] + attribute \src "issuer_ls180.v:44859.3-44867.6" + wire $1\dp_CR_cr_a_cr0_0$next[0:0]$2563 + attribute \src "issuer_ls180.v:38069.7-38069.30" + wire $1\dp_CR_cr_a_cr0_0[0:0] + attribute \src "issuer_ls180.v:44897.3-44905.6" + wire $1\dp_CR_cr_b_cr0_0$next[0:0]$2575 + attribute \src "issuer_ls180.v:38073.7-38073.30" + wire $1\dp_CR_cr_b_cr0_0[0:0] + attribute \src "issuer_ls180.v:44946.3-44954.6" + wire $1\dp_CR_cr_c_cr0_0$next[0:0]$2582 + attribute \src "issuer_ls180.v:38077.7-38077.30" + wire $1\dp_CR_cr_c_cr0_0[0:0] + attribute \src "issuer_ls180.v:44810.3-44818.6" + wire $1\dp_CR_full_cr_cr0_0$next[0:0]$2556 + attribute \src "issuer_ls180.v:38081.7-38081.33" + wire $1\dp_CR_full_cr_cr0_0[0:0] + attribute \src "issuer_ls180.v:44965.3-44973.6" + wire $1\dp_FAST_fast1_branch0_0$next[0:0]$2588 + attribute \src "issuer_ls180.v:38085.7-38085.37" + wire $1\dp_FAST_fast1_branch0_0[0:0] + attribute \src "issuer_ls180.v:45032.3-45040.6" + wire $1\dp_FAST_fast1_spr0_2$next[0:0]$2601 + attribute \src "issuer_ls180.v:38089.7-38089.34" + wire $1\dp_FAST_fast1_spr0_2[0:0] + attribute \src "issuer_ls180.v:44984.3-44992.6" + wire $1\dp_FAST_fast1_trap0_1$next[0:0]$2594 + attribute \src "issuer_ls180.v:38093.7-38093.35" + wire $1\dp_FAST_fast1_trap0_1[0:0] + attribute \src "issuer_ls180.v:45051.3-45059.6" + wire $1\dp_FAST_fast2_branch0_0$next[0:0]$2607 + attribute \src "issuer_ls180.v:38097.7-38097.37" + wire $1\dp_FAST_fast2_branch0_0[0:0] + attribute \src "issuer_ls180.v:45099.3-45107.6" + wire $1\dp_FAST_fast2_trap0_1$next[0:0]$2614 + attribute \src "issuer_ls180.v:38101.7-38101.35" + wire $1\dp_FAST_fast2_trap0_1[0:0] + attribute \src "issuer_ls180.v:44032.3-44040.6" + wire $1\dp_INT_ra_alu0_0$next[0:0]$2379 + attribute \src "issuer_ls180.v:38105.7-38105.30" + wire $1\dp_INT_ra_alu0_0[0:0] + attribute \src "issuer_ls180.v:44051.3-44059.6" + wire $1\dp_INT_ra_cr0_1$next[0:0]$2383 + attribute \src "issuer_ls180.v:38109.7-38109.29" + wire $1\dp_INT_ra_cr0_1[0:0] + attribute \src "issuer_ls180.v:44127.3-44135.6" + wire $1\dp_INT_ra_div0_5$next[0:0]$2407 + attribute \src "issuer_ls180.v:38113.7-38113.30" + wire $1\dp_INT_ra_div0_5[0:0] + attribute \src "issuer_ls180.v:44184.3-44192.6" + wire $1\dp_INT_ra_ldst0_8$next[0:0]$2425 + attribute \src "issuer_ls180.v:38117.7-38117.31" + wire $1\dp_INT_ra_ldst0_8[0:0] + attribute \src "issuer_ls180.v:44089.3-44097.6" + wire $1\dp_INT_ra_logical0_3$next[0:0]$2395 + attribute \src "issuer_ls180.v:38121.7-38121.34" + wire $1\dp_INT_ra_logical0_3[0:0] + attribute \src "issuer_ls180.v:44146.3-44154.6" + wire $1\dp_INT_ra_mul0_6$next[0:0]$2413 + attribute \src "issuer_ls180.v:38125.7-38125.30" + wire $1\dp_INT_ra_mul0_6[0:0] + attribute \src "issuer_ls180.v:44165.3-44173.6" + wire $1\dp_INT_ra_shiftrot0_7$next[0:0]$2419 + attribute \src "issuer_ls180.v:38129.7-38129.35" + wire $1\dp_INT_ra_shiftrot0_7[0:0] + attribute \src "issuer_ls180.v:44108.3-44116.6" + wire $1\dp_INT_ra_spr0_4$next[0:0]$2401 + attribute \src "issuer_ls180.v:38133.7-38133.30" + wire $1\dp_INT_ra_spr0_4[0:0] + attribute \src "issuer_ls180.v:44070.3-44078.6" + wire $1\dp_INT_ra_trap0_2$next[0:0]$2389 + attribute \src "issuer_ls180.v:38137.7-38137.31" + wire $1\dp_INT_ra_trap0_2[0:0] + attribute \src "issuer_ls180.v:44203.3-44211.6" + wire $1\dp_INT_rb_alu0_0$next[0:0]$2431 + attribute \src "issuer_ls180.v:38141.7-38141.30" + wire $1\dp_INT_rb_alu0_0[0:0] + attribute \src "issuer_ls180.v:44222.3-44230.6" + wire $1\dp_INT_rb_cr0_1$next[0:0]$2435 + attribute \src "issuer_ls180.v:38145.7-38145.29" + wire $1\dp_INT_rb_cr0_1[0:0] + attribute \src "issuer_ls180.v:44279.3-44287.6" + wire $1\dp_INT_rb_div0_4$next[0:0]$2453 + attribute \src "issuer_ls180.v:38149.7-38149.30" + wire $1\dp_INT_rb_div0_4[0:0] + attribute \src "issuer_ls180.v:44336.3-44344.6" + wire $1\dp_INT_rb_ldst0_7$next[0:0]$2471 + attribute \src "issuer_ls180.v:38153.7-38153.31" + wire $1\dp_INT_rb_ldst0_7[0:0] + attribute \src "issuer_ls180.v:44260.3-44268.6" + wire $1\dp_INT_rb_logical0_3$next[0:0]$2447 + attribute \src "issuer_ls180.v:38157.7-38157.34" + wire $1\dp_INT_rb_logical0_3[0:0] + attribute \src "issuer_ls180.v:44298.3-44306.6" + wire $1\dp_INT_rb_mul0_5$next[0:0]$2459 + attribute \src "issuer_ls180.v:38161.7-38161.30" + wire $1\dp_INT_rb_mul0_5[0:0] + attribute \src "issuer_ls180.v:44317.3-44325.6" + wire $1\dp_INT_rb_shiftrot0_6$next[0:0]$2465 + attribute \src "issuer_ls180.v:38165.7-38165.35" + wire $1\dp_INT_rb_shiftrot0_6[0:0] + attribute \src "issuer_ls180.v:44241.3-44249.6" + wire $1\dp_INT_rb_trap0_2$next[0:0]$2441 + attribute \src "issuer_ls180.v:38169.7-38169.31" + wire $1\dp_INT_rb_trap0_2[0:0] + attribute \src "issuer_ls180.v:44374.3-44382.6" + wire $1\dp_INT_rc_ldst0_1$next[0:0]$2481 + attribute \src "issuer_ls180.v:38173.7-38173.31" + wire $1\dp_INT_rc_ldst0_1[0:0] + attribute \src "issuer_ls180.v:44355.3-44363.6" + wire $1\dp_INT_rc_shiftrot0_0$next[0:0]$2477 + attribute \src "issuer_ls180.v:38177.7-38177.35" + wire $1\dp_INT_rc_shiftrot0_0[0:0] + attribute \src "issuer_ls180.v:45147.3-45155.6" + wire $1\dp_SPR_spr1_spr0_0$next[0:0]$2621 + attribute \src "issuer_ls180.v:38181.7-38181.32" + wire $1\dp_SPR_spr1_spr0_0[0:0] + attribute \src "issuer_ls180.v:44675.3-44683.6" + wire $1\dp_XER_xer_ca_alu0_0$next[0:0]$2534 + attribute \src "issuer_ls180.v:38185.7-38185.34" + wire $1\dp_XER_xer_ca_alu0_0[0:0] + attribute \src "issuer_ls180.v:44742.3-44750.6" + wire $1\dp_XER_xer_ca_shiftrot0_2$next[0:0]$2545 + attribute \src "issuer_ls180.v:38189.7-38189.39" + wire $1\dp_XER_xer_ca_shiftrot0_2[0:0] + attribute \src "issuer_ls180.v:44723.3-44731.6" + wire $1\dp_XER_xer_ca_spr0_1$next[0:0]$2541 + attribute \src "issuer_ls180.v:38193.7-38193.34" + wire $1\dp_XER_xer_ca_spr0_1[0:0] + attribute \src "issuer_ls180.v:44791.3-44799.6" + wire $1\dp_XER_xer_ov_spr0_0$next[0:0]$2550 + attribute \src "issuer_ls180.v:38197.7-38197.34" + wire $1\dp_XER_xer_ov_spr0_0[0:0] + attribute \src "issuer_ls180.v:44420.3-44428.6" + wire $1\dp_XER_xer_so_alu0_0$next[0:0]$2493 + attribute \src "issuer_ls180.v:38201.7-38201.34" + wire $1\dp_XER_xer_so_alu0_0[0:0] + attribute \src "issuer_ls180.v:44568.3-44576.6" + wire $1\dp_XER_xer_so_div0_3$next[0:0]$2510 + attribute \src "issuer_ls180.v:38205.7-38205.34" + wire $1\dp_XER_xer_so_div0_3[0:0] + attribute \src "issuer_ls180.v:44439.3-44447.6" + wire $1\dp_XER_xer_so_logical0_1$next[0:0]$2499 + attribute \src "issuer_ls180.v:38209.7-38209.38" + wire $1\dp_XER_xer_so_logical0_1[0:0] + attribute \src "issuer_ls180.v:44608.3-44616.6" + wire $1\dp_XER_xer_so_mul0_4$next[0:0]$2521 + attribute \src "issuer_ls180.v:38213.7-38213.34" + wire $1\dp_XER_xer_so_mul0_4[0:0] + attribute \src "issuer_ls180.v:44627.3-44635.6" + wire $1\dp_XER_xer_so_shiftrot0_5$next[0:0]$2527 + attribute \src "issuer_ls180.v:38217.7-38217.39" + wire $1\dp_XER_xer_so_shiftrot0_5[0:0] + attribute \src "issuer_ls180.v:44549.3-44557.6" + wire $1\dp_XER_xer_so_spr0_2$next[0:0]$2506 + attribute \src "issuer_ls180.v:38221.7-38221.34" + wire $1\dp_XER_xer_so_spr0_2[0:0] + attribute \src "issuer_ls180.v:46399.3-46427.6" + wire $1\fus_cu_issue_i$10[0:0]$2785 + attribute \src "issuer_ls180.v:46895.3-46923.6" + wire $1\fus_cu_issue_i$13[0:0]$2810 + attribute \src "issuer_ls180.v:42280.3-42308.6" + wire $1\fus_cu_issue_i$16[0:0]$2279 + attribute \src "issuer_ls180.v:42776.3-42804.6" + wire $1\fus_cu_issue_i$19[0:0]$2304 + attribute \src "issuer_ls180.v:43098.3-43126.6" + wire $1\fus_cu_issue_i$22[0:0]$2323 + attribute \src "issuer_ls180.v:43536.3-43564.6" + wire $1\fus_cu_issue_i$25[0:0]$2346 + attribute \src "issuer_ls180.v:43974.3-44002.6" + wire $1\fus_cu_issue_i$28[0:0]$2369 + attribute \src "issuer_ls180.v:45667.3-45695.6" + wire $1\fus_cu_issue_i$4[0:0]$2690 + attribute \src "issuer_ls180.v:46064.3-46092.6" + wire $1\fus_cu_issue_i$7[0:0]$2752 + attribute \src "issuer_ls180.v:45459.3-45487.6" + wire $1\fus_cu_issue_i[0:0] + attribute \src "issuer_ls180.v:46428.3-46456.6" + wire width 4 $1\fus_cu_rdmaskn_i$12[3:0]$2790 + attribute \src "issuer_ls180.v:46924.3-46952.6" + wire width 3 $1\fus_cu_rdmaskn_i$15[2:0]$2815 + attribute \src "issuer_ls180.v:42309.3-42337.6" + wire width 6 $1\fus_cu_rdmaskn_i$18[5:0]$2284 + attribute \src "issuer_ls180.v:42805.3-42833.6" + wire width 3 $1\fus_cu_rdmaskn_i$21[2:0]$2309 + attribute \src "issuer_ls180.v:43127.3-43155.6" + wire width 3 $1\fus_cu_rdmaskn_i$24[2:0]$2328 + attribute \src "issuer_ls180.v:43565.3-43593.6" + wire width 5 $1\fus_cu_rdmaskn_i$27[4:0]$2351 + attribute \src "issuer_ls180.v:44003.3-44031.6" + wire width 3 $1\fus_cu_rdmaskn_i$30[2:0]$2374 + attribute \src "issuer_ls180.v:45714.3-45742.6" + wire width 6 $1\fus_cu_rdmaskn_i$6[5:0]$2701 + attribute \src "issuer_ls180.v:46102.3-46130.6" + wire width 3 $1\fus_cu_rdmaskn_i$9[2:0]$2760 + attribute \src "issuer_ls180.v:45497.3-45525.6" + wire width 4 $1\fus_cu_rdmaskn_i[3:0] + attribute \src "issuer_ls180.v:45374.3-45402.6" + wire width 4 $1\fus_oper_i_alu_alu0__data_len[3:0] + attribute \src "issuer_ls180.v:44694.3-44722.6" + wire width 12 $1\fus_oper_i_alu_alu0__fn_unit[11:0] + attribute \src "issuer_ls180.v:44761.3-44790.6" + wire width 64 $1\fus_oper_i_alu_alu0__imm_data__data[63:0] + attribute \src "issuer_ls180.v:44761.3-44790.6" + wire $1\fus_oper_i_alu_alu0__imm_data__ok[0:0] + attribute \src "issuer_ls180.v:45213.3-45241.6" + wire width 2 $1\fus_oper_i_alu_alu0__input_carry[1:0] + attribute \src "issuer_ls180.v:45421.3-45449.6" + wire width 32 $1\fus_oper_i_alu_alu0__insn[31:0] + attribute \src "issuer_ls180.v:44636.3-44664.6" + wire width 7 $1\fus_oper_i_alu_alu0__insn_type[6:0] + attribute \src "issuer_ls180.v:45003.3-45031.6" + wire $1\fus_oper_i_alu_alu0__invert_in[0:0] + attribute \src "issuer_ls180.v:45118.3-45146.6" + wire $1\fus_oper_i_alu_alu0__invert_out[0:0] + attribute \src "issuer_ls180.v:45298.3-45326.6" + wire $1\fus_oper_i_alu_alu0__is_32bit[0:0] + attribute \src "issuer_ls180.v:45336.3-45364.6" + wire $1\fus_oper_i_alu_alu0__is_signed[0:0] + attribute \src "issuer_ls180.v:44916.3-44945.6" + wire $1\fus_oper_i_alu_alu0__oe__oe[0:0] + attribute \src "issuer_ls180.v:44916.3-44945.6" + wire $1\fus_oper_i_alu_alu0__oe__ok[0:0] + attribute \src "issuer_ls180.v:45251.3-45279.6" + wire $1\fus_oper_i_alu_alu0__output_carry[0:0] + attribute \src "issuer_ls180.v:44829.3-44858.6" + wire $1\fus_oper_i_alu_alu0__rc__ok[0:0] + attribute \src "issuer_ls180.v:44829.3-44858.6" + wire $1\fus_oper_i_alu_alu0__rc__rc[0:0] + attribute \src "issuer_ls180.v:45166.3-45194.6" + wire $1\fus_oper_i_alu_alu0__write_cr0[0:0] + attribute \src "issuer_ls180.v:45060.3-45088.6" + wire $1\fus_oper_i_alu_alu0__zero_a[0:0] + attribute \src "issuer_ls180.v:45752.3-45780.6" + wire width 64 $1\fus_oper_i_alu_branch0__cia[63:0] + attribute \src "issuer_ls180.v:45837.3-45865.6" + wire width 12 $1\fus_oper_i_alu_branch0__fn_unit[11:0] + attribute \src "issuer_ls180.v:45922.3-45951.6" + wire width 64 $1\fus_oper_i_alu_branch0__imm_data__data[63:0] + attribute \src "issuer_ls180.v:45922.3-45951.6" + wire $1\fus_oper_i_alu_branch0__imm_data__ok[0:0] + attribute \src "issuer_ls180.v:45875.3-45903.6" + wire width 32 $1\fus_oper_i_alu_branch0__insn[31:0] + attribute \src "issuer_ls180.v:45799.3-45827.6" + wire width 7 $1\fus_oper_i_alu_branch0__insn_type[6:0] + attribute \src "issuer_ls180.v:46017.3-46045.6" + wire $1\fus_oper_i_alu_branch0__is_32bit[0:0] + attribute \src "issuer_ls180.v:45979.3-46007.6" + wire $1\fus_oper_i_alu_branch0__lk[0:0] + attribute \src "issuer_ls180.v:45582.3-45610.6" + wire width 12 $1\fus_oper_i_alu_cr0__fn_unit[11:0] + attribute \src "issuer_ls180.v:45629.3-45657.6" + wire width 32 $1\fus_oper_i_alu_cr0__insn[31:0] + attribute \src "issuer_ls180.v:45544.3-45572.6" + wire width 7 $1\fus_oper_i_alu_cr0__insn_type[6:0] + attribute \src "issuer_ls180.v:42718.3-42746.6" + wire width 4 $1\fus_oper_i_alu_div0__data_len[3:0] + attribute \src "issuer_ls180.v:42367.3-42395.6" + wire width 12 $1\fus_oper_i_alu_div0__fn_unit[11:0] + attribute \src "issuer_ls180.v:42396.3-42425.6" + wire width 64 $1\fus_oper_i_alu_div0__imm_data__data[63:0] + attribute \src "issuer_ls180.v:42396.3-42425.6" + wire $1\fus_oper_i_alu_div0__imm_data__ok[0:0] + attribute \src "issuer_ls180.v:42544.3-42572.6" + wire width 2 $1\fus_oper_i_alu_div0__input_carry[1:0] + attribute \src "issuer_ls180.v:42747.3-42775.6" + wire width 32 $1\fus_oper_i_alu_div0__insn[31:0] + attribute \src "issuer_ls180.v:42338.3-42366.6" + wire width 7 $1\fus_oper_i_alu_div0__insn_type[6:0] + attribute \src "issuer_ls180.v:42486.3-42514.6" + wire $1\fus_oper_i_alu_div0__invert_in[0:0] + attribute \src "issuer_ls180.v:42573.3-42601.6" + wire $1\fus_oper_i_alu_div0__invert_out[0:0] + attribute \src "issuer_ls180.v:42660.3-42688.6" + wire $1\fus_oper_i_alu_div0__is_32bit[0:0] + attribute \src "issuer_ls180.v:42689.3-42717.6" + wire $1\fus_oper_i_alu_div0__is_signed[0:0] + attribute \src "issuer_ls180.v:42456.3-42485.6" + wire $1\fus_oper_i_alu_div0__oe__oe[0:0] + attribute \src "issuer_ls180.v:42456.3-42485.6" + wire $1\fus_oper_i_alu_div0__oe__ok[0:0] + attribute \src "issuer_ls180.v:42631.3-42659.6" + wire $1\fus_oper_i_alu_div0__output_carry[0:0] + attribute \src "issuer_ls180.v:42426.3-42455.6" + wire $1\fus_oper_i_alu_div0__rc__ok[0:0] + attribute \src "issuer_ls180.v:42426.3-42455.6" + wire $1\fus_oper_i_alu_div0__rc__rc[0:0] + attribute \src "issuer_ls180.v:42602.3-42630.6" + wire $1\fus_oper_i_alu_div0__write_cr0[0:0] + attribute \src "issuer_ls180.v:42515.3-42543.6" + wire $1\fus_oper_i_alu_div0__zero_a[0:0] + attribute \src "issuer_ls180.v:46837.3-46865.6" + wire width 4 $1\fus_oper_i_alu_logical0__data_len[3:0] + attribute \src "issuer_ls180.v:46486.3-46514.6" + wire width 12 $1\fus_oper_i_alu_logical0__fn_unit[11:0] + attribute \src "issuer_ls180.v:46515.3-46544.6" + wire width 64 $1\fus_oper_i_alu_logical0__imm_data__data[63:0] + attribute \src "issuer_ls180.v:46515.3-46544.6" + wire $1\fus_oper_i_alu_logical0__imm_data__ok[0:0] + attribute \src "issuer_ls180.v:46663.3-46691.6" + wire width 2 $1\fus_oper_i_alu_logical0__input_carry[1:0] + attribute \src "issuer_ls180.v:46866.3-46894.6" + wire width 32 $1\fus_oper_i_alu_logical0__insn[31:0] + attribute \src "issuer_ls180.v:46457.3-46485.6" + wire width 7 $1\fus_oper_i_alu_logical0__insn_type[6:0] + attribute \src "issuer_ls180.v:46605.3-46633.6" + wire $1\fus_oper_i_alu_logical0__invert_in[0:0] + attribute \src "issuer_ls180.v:46692.3-46720.6" + wire $1\fus_oper_i_alu_logical0__invert_out[0:0] + attribute \src "issuer_ls180.v:46779.3-46807.6" + wire $1\fus_oper_i_alu_logical0__is_32bit[0:0] + attribute \src "issuer_ls180.v:46808.3-46836.6" + wire $1\fus_oper_i_alu_logical0__is_signed[0:0] + attribute \src "issuer_ls180.v:46575.3-46604.6" + wire $1\fus_oper_i_alu_logical0__oe__oe[0:0] + attribute \src "issuer_ls180.v:46575.3-46604.6" + wire $1\fus_oper_i_alu_logical0__oe__ok[0:0] + attribute \src "issuer_ls180.v:46750.3-46778.6" + wire $1\fus_oper_i_alu_logical0__output_carry[0:0] + attribute \src "issuer_ls180.v:46545.3-46574.6" + wire $1\fus_oper_i_alu_logical0__rc__ok[0:0] + attribute \src "issuer_ls180.v:46545.3-46574.6" + wire $1\fus_oper_i_alu_logical0__rc__rc[0:0] + attribute \src "issuer_ls180.v:46721.3-46749.6" + wire $1\fus_oper_i_alu_logical0__write_cr0[0:0] + attribute \src "issuer_ls180.v:46634.3-46662.6" + wire $1\fus_oper_i_alu_logical0__zero_a[0:0] + attribute \src "issuer_ls180.v:42863.3-42891.6" + wire width 12 $1\fus_oper_i_alu_mul0__fn_unit[11:0] + attribute \src "issuer_ls180.v:42892.3-42921.6" + wire width 64 $1\fus_oper_i_alu_mul0__imm_data__data[63:0] + attribute \src "issuer_ls180.v:42892.3-42921.6" + wire $1\fus_oper_i_alu_mul0__imm_data__ok[0:0] + attribute \src "issuer_ls180.v:43069.3-43097.6" + wire width 32 $1\fus_oper_i_alu_mul0__insn[31:0] + attribute \src "issuer_ls180.v:42834.3-42862.6" + wire width 7 $1\fus_oper_i_alu_mul0__insn_type[6:0] + attribute \src "issuer_ls180.v:43011.3-43039.6" + wire $1\fus_oper_i_alu_mul0__is_32bit[0:0] + attribute \src "issuer_ls180.v:43040.3-43068.6" + wire $1\fus_oper_i_alu_mul0__is_signed[0:0] + attribute \src "issuer_ls180.v:42952.3-42981.6" + wire $1\fus_oper_i_alu_mul0__oe__oe[0:0] + attribute \src "issuer_ls180.v:42952.3-42981.6" + wire $1\fus_oper_i_alu_mul0__oe__ok[0:0] + attribute \src "issuer_ls180.v:42922.3-42951.6" + wire $1\fus_oper_i_alu_mul0__rc__ok[0:0] + attribute \src "issuer_ls180.v:42922.3-42951.6" + wire $1\fus_oper_i_alu_mul0__rc__rc[0:0] + attribute \src "issuer_ls180.v:42982.3-43010.6" + wire $1\fus_oper_i_alu_mul0__write_cr0[0:0] + attribute \src "issuer_ls180.v:43185.3-43213.6" + wire width 12 $1\fus_oper_i_alu_shift_rot0__fn_unit[11:0] + attribute \src "issuer_ls180.v:43214.3-43243.6" + wire width 64 $1\fus_oper_i_alu_shift_rot0__imm_data__data[63:0] + attribute \src "issuer_ls180.v:43214.3-43243.6" + wire $1\fus_oper_i_alu_shift_rot0__imm_data__ok[0:0] + attribute \src "issuer_ls180.v:43333.3-43361.6" + wire width 2 $1\fus_oper_i_alu_shift_rot0__input_carry[1:0] + attribute \src "issuer_ls180.v:43391.3-43419.6" + wire $1\fus_oper_i_alu_shift_rot0__input_cr[0:0] + attribute \src "issuer_ls180.v:43507.3-43535.6" + wire width 32 $1\fus_oper_i_alu_shift_rot0__insn[31:0] + attribute \src "issuer_ls180.v:43156.3-43184.6" + wire width 7 $1\fus_oper_i_alu_shift_rot0__insn_type[6:0] + attribute \src "issuer_ls180.v:43449.3-43477.6" + wire $1\fus_oper_i_alu_shift_rot0__is_32bit[0:0] + attribute \src "issuer_ls180.v:43478.3-43506.6" + wire $1\fus_oper_i_alu_shift_rot0__is_signed[0:0] + attribute \src "issuer_ls180.v:43274.3-43303.6" + wire $1\fus_oper_i_alu_shift_rot0__oe__oe[0:0] + attribute \src "issuer_ls180.v:43274.3-43303.6" + wire $1\fus_oper_i_alu_shift_rot0__oe__ok[0:0] + attribute \src "issuer_ls180.v:43362.3-43390.6" + wire $1\fus_oper_i_alu_shift_rot0__output_carry[0:0] + attribute \src "issuer_ls180.v:43420.3-43448.6" + wire $1\fus_oper_i_alu_shift_rot0__output_cr[0:0] + attribute \src "issuer_ls180.v:43244.3-43273.6" + wire $1\fus_oper_i_alu_shift_rot0__rc__ok[0:0] + attribute \src "issuer_ls180.v:43244.3-43273.6" + wire $1\fus_oper_i_alu_shift_rot0__rc__rc[0:0] + attribute \src "issuer_ls180.v:43304.3-43332.6" + wire $1\fus_oper_i_alu_shift_rot0__write_cr0[0:0] + attribute \src "issuer_ls180.v:46982.3-47010.6" + wire width 12 $1\fus_oper_i_alu_spr0__fn_unit[11:0] + attribute \src "issuer_ls180.v:47011.3-47039.6" + wire width 32 $1\fus_oper_i_alu_spr0__insn[31:0] + attribute \src "issuer_ls180.v:46953.3-46981.6" + wire width 7 $1\fus_oper_i_alu_spr0__insn_type[6:0] + attribute \src "issuer_ls180.v:42251.3-42279.6" + wire $1\fus_oper_i_alu_spr0__is_32bit[0:0] + attribute \src "issuer_ls180.v:46283.3-46311.6" + wire width 64 $1\fus_oper_i_alu_trap0__cia[63:0] + attribute \src "issuer_ls180.v:46187.3-46215.6" + wire width 12 $1\fus_oper_i_alu_trap0__fn_unit[11:0] + attribute \src "issuer_ls180.v:46225.3-46253.6" + wire width 32 $1\fus_oper_i_alu_trap0__insn[31:0] + attribute \src "issuer_ls180.v:46149.3-46177.6" + wire width 7 $1\fus_oper_i_alu_trap0__insn_type[6:0] + attribute \src "issuer_ls180.v:46312.3-46340.6" + wire $1\fus_oper_i_alu_trap0__is_32bit[0:0] + attribute \src "issuer_ls180.v:46254.3-46282.6" + wire width 64 $1\fus_oper_i_alu_trap0__msr[63:0] + attribute \src "issuer_ls180.v:46370.3-46398.6" + wire width 13 $1\fus_oper_i_alu_trap0__trapaddr[12:0] + attribute \src "issuer_ls180.v:46341.3-46369.6" + wire width 7 $1\fus_oper_i_alu_trap0__traptype[6:0] + attribute \src "issuer_ls180.v:43858.3-43886.6" + wire $1\fus_oper_i_ldst_ldst0__byte_reverse[0:0] + attribute \src "issuer_ls180.v:43829.3-43857.6" + wire width 4 $1\fus_oper_i_ldst_ldst0__data_len[3:0] + attribute \src "issuer_ls180.v:43623.3-43651.6" + wire width 12 $1\fus_oper_i_ldst_ldst0__fn_unit[11:0] + attribute \src "issuer_ls180.v:43652.3-43681.6" + wire width 64 $1\fus_oper_i_ldst_ldst0__imm_data__data[63:0] + attribute \src "issuer_ls180.v:43652.3-43681.6" + wire $1\fus_oper_i_ldst_ldst0__imm_data__ok[0:0] + attribute \src "issuer_ls180.v:43945.3-43973.6" + wire width 32 $1\fus_oper_i_ldst_ldst0__insn[31:0] + attribute \src "issuer_ls180.v:43594.3-43622.6" + wire width 7 $1\fus_oper_i_ldst_ldst0__insn_type[6:0] + attribute \src "issuer_ls180.v:43771.3-43799.6" + wire $1\fus_oper_i_ldst_ldst0__is_32bit[0:0] + attribute \src "issuer_ls180.v:43800.3-43828.6" + wire $1\fus_oper_i_ldst_ldst0__is_signed[0:0] + attribute \src "issuer_ls180.v:43916.3-43944.6" + wire width 2 $1\fus_oper_i_ldst_ldst0__ldst_mode[1:0] + attribute \src "issuer_ls180.v:43741.3-43770.6" + wire $1\fus_oper_i_ldst_ldst0__oe__oe[0:0] + attribute \src "issuer_ls180.v:43741.3-43770.6" + wire $1\fus_oper_i_ldst_ldst0__oe__ok[0:0] + attribute \src "issuer_ls180.v:43711.3-43740.6" + wire $1\fus_oper_i_ldst_ldst0__rc__ok[0:0] + attribute \src "issuer_ls180.v:43711.3-43740.6" + wire $1\fus_oper_i_ldst_ldst0__rc__rc[0:0] + attribute \src "issuer_ls180.v:43887.3-43915.6" + wire $1\fus_oper_i_ldst_ldst0__sign_extend[0:0] + attribute \src "issuer_ls180.v:43682.3-43710.6" + wire $1\fus_oper_i_ldst_ldst0__zero_a[0:0] + attribute \src "issuer_ls180.v:44060.3-44069.6" + wire width 64 $1\fus_src1_i$33[63:0]$2386 + attribute \src "issuer_ls180.v:44079.3-44088.6" + wire width 64 $1\fus_src1_i$36[63:0]$2392 + attribute \src "issuer_ls180.v:44098.3-44107.6" + wire width 64 $1\fus_src1_i$39[63:0]$2398 + attribute \src "issuer_ls180.v:44117.3-44126.6" + wire width 64 $1\fus_src1_i$42[63:0]$2404 + attribute \src "issuer_ls180.v:44136.3-44145.6" + wire width 64 $1\fus_src1_i$45[63:0]$2410 + attribute \src "issuer_ls180.v:44155.3-44164.6" + wire width 64 $1\fus_src1_i$48[63:0]$2416 + attribute \src "issuer_ls180.v:44174.3-44183.6" + wire width 64 $1\fus_src1_i$51[63:0]$2422 + attribute \src "issuer_ls180.v:44193.3-44202.6" + wire width 64 $1\fus_src1_i$54[63:0]$2428 + attribute \src "issuer_ls180.v:44974.3-44983.6" + wire width 64 $1\fus_src1_i$77[63:0]$2591 + attribute \src "issuer_ls180.v:44041.3-44050.6" + wire width 64 $1\fus_src1_i[63:0] + attribute \src "issuer_ls180.v:44231.3-44240.6" + wire width 64 $1\fus_src2_i$55[63:0]$2438 + attribute \src "issuer_ls180.v:44250.3-44259.6" + wire width 64 $1\fus_src2_i$56[63:0]$2444 + attribute \src "issuer_ls180.v:44269.3-44278.6" + wire width 64 $1\fus_src2_i$57[63:0]$2450 + attribute \src "issuer_ls180.v:44288.3-44297.6" + wire width 64 $1\fus_src2_i$58[63:0]$2456 + attribute \src "issuer_ls180.v:44307.3-44316.6" + wire width 64 $1\fus_src2_i$59[63:0]$2462 + attribute \src "issuer_ls180.v:44326.3-44335.6" + wire width 64 $1\fus_src2_i$60[63:0]$2468 + attribute \src "issuer_ls180.v:44345.3-44354.6" + wire width 64 $1\fus_src2_i$61[63:0]$2474 + attribute \src "issuer_ls180.v:45089.3-45098.6" + wire width 64 $1\fus_src2_i$80[63:0]$2611 + attribute \src "issuer_ls180.v:45156.3-45165.6" + wire width 64 $1\fus_src2_i$82[63:0]$2624 + attribute \src "issuer_ls180.v:44212.3-44221.6" + wire width 64 $1\fus_src2_i[63:0] + attribute \src "issuer_ls180.v:44383.3-44392.6" + wire width 64 $1\fus_src3_i$62[63:0]$2484 + attribute \src "issuer_ls180.v:44429.3-44438.6" + wire $1\fus_src3_i$63[0:0]$2496 + attribute \src "issuer_ls180.v:44539.3-44548.6" + wire $1\fus_src3_i$64[0:0]$2503 + attribute \src "issuer_ls180.v:44598.3-44607.6" + wire $1\fus_src3_i$65[0:0]$2518 + attribute \src "issuer_ls180.v:44617.3-44626.6" + wire $1\fus_src3_i$66[0:0]$2524 + attribute \src "issuer_ls180.v:44819.3-44828.6" + wire width 32 $1\fus_src3_i$70[31:0]$2559 + attribute \src "issuer_ls180.v:44887.3-44896.6" + wire width 4 $1\fus_src3_i$74[3:0]$2572 + attribute \src "issuer_ls180.v:44993.3-45002.6" + wire width 64 $1\fus_src3_i$78[63:0]$2597 + attribute \src "issuer_ls180.v:45041.3-45050.6" + wire width 64 $1\fus_src3_i$79[63:0]$2604 + attribute \src "issuer_ls180.v:44364.3-44373.6" + wire width 64 $1\fus_src3_i[63:0] + attribute \src "issuer_ls180.v:44665.3-44674.6" + wire $1\fus_src4_i$67[0:0]$2531 + attribute \src "issuer_ls180.v:44684.3-44693.6" + wire width 2 $1\fus_src4_i$68[1:0]$2537 + attribute \src "issuer_ls180.v:44868.3-44877.6" + wire width 4 $1\fus_src4_i$71[3:0]$2566 + attribute \src "issuer_ls180.v:45108.3-45117.6" + wire width 64 $1\fus_src4_i$81[63:0]$2617 + attribute \src "issuer_ls180.v:44558.3-44567.6" + wire $1\fus_src4_i[0:0] + attribute \src "issuer_ls180.v:44800.3-44809.6" + wire width 2 $1\fus_src5_i$69[1:0]$2553 + attribute \src "issuer_ls180.v:44906.3-44915.6" + wire width 4 $1\fus_src5_i$75[3:0]$2578 + attribute \src "issuer_ls180.v:44751.3-44760.6" + wire width 2 $1\fus_src5_i[1:0] + attribute \src "issuer_ls180.v:44955.3-44964.6" + wire width 4 $1\fus_src6_i$76[3:0]$2585 + attribute \src "issuer_ls180.v:44732.3-44741.6" + wire width 2 $1\fus_src6_i[1:0] + attribute \src "issuer_ls180.v:45280.3-45288.6" + wire $1\wr_pick_dly$1007$next[0:0]$2639 + attribute \src "issuer_ls180.v:45289.3-45297.6" + wire $1\wr_pick_dly$1025$next[0:0]$2642 + attribute \src "issuer_ls180.v:45327.3-45335.6" + wire $1\wr_pick_dly$1047$next[0:0]$2646 + attribute \src "issuer_ls180.v:45365.3-45373.6" + wire $1\wr_pick_dly$1067$next[0:0]$2650 + attribute \src "issuer_ls180.v:45403.3-45411.6" + wire $1\wr_pick_dly$1087$next[0:0]$2654 + attribute \src "issuer_ls180.v:45412.3-45420.6" + wire $1\wr_pick_dly$1106$next[0:0]$2657 + attribute \src "issuer_ls180.v:45450.3-45458.6" + wire $1\wr_pick_dly$1124$next[0:0]$2661 + attribute \src "issuer_ls180.v:45488.3-45496.6" + wire $1\wr_pick_dly$1197$next[0:0]$2665 + attribute \src "issuer_ls180.v:45526.3-45534.6" + wire $1\wr_pick_dly$1225$next[0:0]$2669 + attribute \src "issuer_ls180.v:45535.3-45543.6" + wire $1\wr_pick_dly$1245$next[0:0]$2672 + attribute \src "issuer_ls180.v:45573.3-45581.6" + wire $1\wr_pick_dly$1265$next[0:0]$2676 + attribute \src "issuer_ls180.v:45611.3-45619.6" + wire $1\wr_pick_dly$1285$next[0:0]$2680 + attribute \src "issuer_ls180.v:45620.3-45628.6" + wire $1\wr_pick_dly$1305$next[0:0]$2683 + attribute \src "issuer_ls180.v:45658.3-45666.6" + wire $1\wr_pick_dly$1325$next[0:0]$2687 + attribute \src "issuer_ls180.v:45696.3-45704.6" + wire $1\wr_pick_dly$1372$next[0:0]$2695 + attribute \src "issuer_ls180.v:45705.3-45713.6" + wire $1\wr_pick_dly$1388$next[0:0]$2698 + attribute \src "issuer_ls180.v:45743.3-45751.6" + wire $1\wr_pick_dly$1404$next[0:0]$2706 + attribute \src "issuer_ls180.v:45781.3-45789.6" + wire $1\wr_pick_dly$1438$next[0:0]$2710 + attribute \src "issuer_ls180.v:45790.3-45798.6" + wire $1\wr_pick_dly$1454$next[0:0]$2713 + attribute \src "issuer_ls180.v:45828.3-45836.6" + wire $1\wr_pick_dly$1470$next[0:0]$2717 + attribute \src "issuer_ls180.v:45866.3-45874.6" + wire $1\wr_pick_dly$1486$next[0:0]$2721 + attribute \src "issuer_ls180.v:45904.3-45912.6" + wire $1\wr_pick_dly$1522$next[0:0]$2725 + attribute \src "issuer_ls180.v:45913.3-45921.6" + wire $1\wr_pick_dly$1538$next[0:0]$2728 + attribute \src "issuer_ls180.v:45952.3-45960.6" + wire $1\wr_pick_dly$1554$next[0:0]$2732 + attribute \src "issuer_ls180.v:45961.3-45969.6" + wire $1\wr_pick_dly$1570$next[0:0]$2735 + attribute \src "issuer_ls180.v:45970.3-45978.6" + wire $1\wr_pick_dly$1612$next[0:0]$2738 + attribute \src "issuer_ls180.v:46008.3-46016.6" + wire $1\wr_pick_dly$1631$next[0:0]$2742 + attribute \src "issuer_ls180.v:46046.3-46054.6" + wire $1\wr_pick_dly$1647$next[0:0]$2746 + attribute \src "issuer_ls180.v:46055.3-46063.6" + wire $1\wr_pick_dly$1663$next[0:0]$2749 + attribute \src "issuer_ls180.v:46093.3-46101.6" + wire $1\wr_pick_dly$1679$next[0:0]$2757 + attribute \src "issuer_ls180.v:46131.3-46139.6" + wire $1\wr_pick_dly$1723$next[0:0]$2765 + attribute \src "issuer_ls180.v:46140.3-46148.6" + wire $1\wr_pick_dly$1739$next[0:0]$2768 + attribute \src "issuer_ls180.v:46178.3-46186.6" + wire $1\wr_pick_dly$1763$next[0:0]$2772 + attribute \src "issuer_ls180.v:46216.3-46224.6" + wire $1\wr_pick_dly$1783$next[0:0]$2776 + attribute \src "issuer_ls180.v:45204.3-45212.6" + wire $1\wr_pick_dly$967$next[0:0]$2631 + attribute \src "issuer_ls180.v:45242.3-45250.6" + wire $1\wr_pick_dly$986$next[0:0]$2635 + attribute \src "issuer_ls180.v:45195.3-45203.6" + wire $1\wr_pick_dly$next[0:0]$2628 + attribute \src "issuer_ls180.v:40278.7-40278.25" + wire $1\wr_pick_dly[0:0] + attribute \src "issuer_ls180.v:44577.3-44597.6" + wire $2\core_terminate_o$next[0:0]$2514 + attribute \src "issuer_ls180.v:44448.3-44538.6" + wire $2\corebusy_o[0:0] + attribute \src "issuer_ls180.v:44393.3-44419.6" + wire width 2 $2\counter$next[1:0]$2488 + attribute \src "issuer_ls180.v:46399.3-46427.6" + wire $2\fus_cu_issue_i$10[0:0]$2786 + attribute \src "issuer_ls180.v:46895.3-46923.6" + wire $2\fus_cu_issue_i$13[0:0]$2811 + attribute \src "issuer_ls180.v:42280.3-42308.6" + wire $2\fus_cu_issue_i$16[0:0]$2280 + attribute \src "issuer_ls180.v:42776.3-42804.6" + wire $2\fus_cu_issue_i$19[0:0]$2305 + attribute \src "issuer_ls180.v:43098.3-43126.6" + wire $2\fus_cu_issue_i$22[0:0]$2324 + attribute \src "issuer_ls180.v:43536.3-43564.6" + wire $2\fus_cu_issue_i$25[0:0]$2347 + attribute \src "issuer_ls180.v:43974.3-44002.6" + wire $2\fus_cu_issue_i$28[0:0]$2370 + attribute \src "issuer_ls180.v:45667.3-45695.6" + wire $2\fus_cu_issue_i$4[0:0]$2691 + attribute \src "issuer_ls180.v:46064.3-46092.6" + wire $2\fus_cu_issue_i$7[0:0]$2753 + attribute \src "issuer_ls180.v:45459.3-45487.6" + wire $2\fus_cu_issue_i[0:0] + attribute \src "issuer_ls180.v:46428.3-46456.6" + wire width 4 $2\fus_cu_rdmaskn_i$12[3:0]$2791 + attribute \src "issuer_ls180.v:46924.3-46952.6" + wire width 3 $2\fus_cu_rdmaskn_i$15[2:0]$2816 + attribute \src "issuer_ls180.v:42309.3-42337.6" + wire width 6 $2\fus_cu_rdmaskn_i$18[5:0]$2285 + attribute \src "issuer_ls180.v:42805.3-42833.6" + wire width 3 $2\fus_cu_rdmaskn_i$21[2:0]$2310 + attribute \src "issuer_ls180.v:43127.3-43155.6" + wire width 3 $2\fus_cu_rdmaskn_i$24[2:0]$2329 + attribute \src "issuer_ls180.v:43565.3-43593.6" + wire width 5 $2\fus_cu_rdmaskn_i$27[4:0]$2352 + attribute \src "issuer_ls180.v:44003.3-44031.6" + wire width 3 $2\fus_cu_rdmaskn_i$30[2:0]$2375 + attribute \src "issuer_ls180.v:45714.3-45742.6" + wire width 6 $2\fus_cu_rdmaskn_i$6[5:0]$2702 + attribute \src "issuer_ls180.v:46102.3-46130.6" + wire width 3 $2\fus_cu_rdmaskn_i$9[2:0]$2761 + attribute \src "issuer_ls180.v:45497.3-45525.6" + wire width 4 $2\fus_cu_rdmaskn_i[3:0] + attribute \src "issuer_ls180.v:45374.3-45402.6" + wire width 4 $2\fus_oper_i_alu_alu0__data_len[3:0] + attribute \src "issuer_ls180.v:44694.3-44722.6" + wire width 12 $2\fus_oper_i_alu_alu0__fn_unit[11:0] + attribute \src "issuer_ls180.v:44761.3-44790.6" + wire width 64 $2\fus_oper_i_alu_alu0__imm_data__data[63:0] + attribute \src "issuer_ls180.v:44761.3-44790.6" + wire $2\fus_oper_i_alu_alu0__imm_data__ok[0:0] + attribute \src "issuer_ls180.v:45213.3-45241.6" + wire width 2 $2\fus_oper_i_alu_alu0__input_carry[1:0] + attribute \src "issuer_ls180.v:45421.3-45449.6" + wire width 32 $2\fus_oper_i_alu_alu0__insn[31:0] + attribute \src "issuer_ls180.v:44636.3-44664.6" + wire width 7 $2\fus_oper_i_alu_alu0__insn_type[6:0] + attribute \src "issuer_ls180.v:45003.3-45031.6" + wire $2\fus_oper_i_alu_alu0__invert_in[0:0] + attribute \src "issuer_ls180.v:45118.3-45146.6" + wire $2\fus_oper_i_alu_alu0__invert_out[0:0] + attribute \src "issuer_ls180.v:45298.3-45326.6" + wire $2\fus_oper_i_alu_alu0__is_32bit[0:0] + attribute \src "issuer_ls180.v:45336.3-45364.6" + wire $2\fus_oper_i_alu_alu0__is_signed[0:0] + attribute \src "issuer_ls180.v:44916.3-44945.6" + wire $2\fus_oper_i_alu_alu0__oe__oe[0:0] + attribute \src "issuer_ls180.v:44916.3-44945.6" + wire $2\fus_oper_i_alu_alu0__oe__ok[0:0] + attribute \src "issuer_ls180.v:45251.3-45279.6" + wire $2\fus_oper_i_alu_alu0__output_carry[0:0] + attribute \src "issuer_ls180.v:44829.3-44858.6" + wire $2\fus_oper_i_alu_alu0__rc__ok[0:0] + attribute \src "issuer_ls180.v:44829.3-44858.6" + wire $2\fus_oper_i_alu_alu0__rc__rc[0:0] + attribute \src "issuer_ls180.v:45166.3-45194.6" + wire $2\fus_oper_i_alu_alu0__write_cr0[0:0] + attribute \src "issuer_ls180.v:45060.3-45088.6" + wire $2\fus_oper_i_alu_alu0__zero_a[0:0] + attribute \src "issuer_ls180.v:45752.3-45780.6" + wire width 64 $2\fus_oper_i_alu_branch0__cia[63:0] + attribute \src "issuer_ls180.v:45837.3-45865.6" + wire width 12 $2\fus_oper_i_alu_branch0__fn_unit[11:0] + attribute \src "issuer_ls180.v:45922.3-45951.6" + wire width 64 $2\fus_oper_i_alu_branch0__imm_data__data[63:0] + attribute \src "issuer_ls180.v:45922.3-45951.6" + wire $2\fus_oper_i_alu_branch0__imm_data__ok[0:0] + attribute \src "issuer_ls180.v:45875.3-45903.6" + wire width 32 $2\fus_oper_i_alu_branch0__insn[31:0] + attribute \src "issuer_ls180.v:45799.3-45827.6" + wire width 7 $2\fus_oper_i_alu_branch0__insn_type[6:0] + attribute \src "issuer_ls180.v:46017.3-46045.6" + wire $2\fus_oper_i_alu_branch0__is_32bit[0:0] + attribute \src "issuer_ls180.v:45979.3-46007.6" + wire $2\fus_oper_i_alu_branch0__lk[0:0] + attribute \src "issuer_ls180.v:45582.3-45610.6" + wire width 12 $2\fus_oper_i_alu_cr0__fn_unit[11:0] + attribute \src "issuer_ls180.v:45629.3-45657.6" + wire width 32 $2\fus_oper_i_alu_cr0__insn[31:0] + attribute \src "issuer_ls180.v:45544.3-45572.6" + wire width 7 $2\fus_oper_i_alu_cr0__insn_type[6:0] + attribute \src "issuer_ls180.v:42718.3-42746.6" + wire width 4 $2\fus_oper_i_alu_div0__data_len[3:0] + attribute \src "issuer_ls180.v:42367.3-42395.6" + wire width 12 $2\fus_oper_i_alu_div0__fn_unit[11:0] + attribute \src "issuer_ls180.v:42396.3-42425.6" + wire width 64 $2\fus_oper_i_alu_div0__imm_data__data[63:0] + attribute \src "issuer_ls180.v:42396.3-42425.6" + wire $2\fus_oper_i_alu_div0__imm_data__ok[0:0] + attribute \src "issuer_ls180.v:42544.3-42572.6" + wire width 2 $2\fus_oper_i_alu_div0__input_carry[1:0] + attribute \src "issuer_ls180.v:42747.3-42775.6" + wire width 32 $2\fus_oper_i_alu_div0__insn[31:0] + attribute \src "issuer_ls180.v:42338.3-42366.6" + wire width 7 $2\fus_oper_i_alu_div0__insn_type[6:0] + attribute \src "issuer_ls180.v:42486.3-42514.6" + wire $2\fus_oper_i_alu_div0__invert_in[0:0] + attribute \src "issuer_ls180.v:42573.3-42601.6" + wire $2\fus_oper_i_alu_div0__invert_out[0:0] + attribute \src "issuer_ls180.v:42660.3-42688.6" + wire $2\fus_oper_i_alu_div0__is_32bit[0:0] + attribute \src "issuer_ls180.v:42689.3-42717.6" + wire $2\fus_oper_i_alu_div0__is_signed[0:0] + attribute \src "issuer_ls180.v:42456.3-42485.6" + wire $2\fus_oper_i_alu_div0__oe__oe[0:0] + attribute \src "issuer_ls180.v:42456.3-42485.6" + wire $2\fus_oper_i_alu_div0__oe__ok[0:0] + attribute \src "issuer_ls180.v:42631.3-42659.6" + wire $2\fus_oper_i_alu_div0__output_carry[0:0] + attribute \src "issuer_ls180.v:42426.3-42455.6" + wire $2\fus_oper_i_alu_div0__rc__ok[0:0] + attribute \src "issuer_ls180.v:42426.3-42455.6" + wire $2\fus_oper_i_alu_div0__rc__rc[0:0] + attribute \src "issuer_ls180.v:42602.3-42630.6" + wire $2\fus_oper_i_alu_div0__write_cr0[0:0] + attribute \src "issuer_ls180.v:42515.3-42543.6" + wire $2\fus_oper_i_alu_div0__zero_a[0:0] + attribute \src "issuer_ls180.v:46837.3-46865.6" + wire width 4 $2\fus_oper_i_alu_logical0__data_len[3:0] + attribute \src "issuer_ls180.v:46486.3-46514.6" + wire width 12 $2\fus_oper_i_alu_logical0__fn_unit[11:0] + attribute \src "issuer_ls180.v:46515.3-46544.6" + wire width 64 $2\fus_oper_i_alu_logical0__imm_data__data[63:0] + attribute \src "issuer_ls180.v:46515.3-46544.6" + wire $2\fus_oper_i_alu_logical0__imm_data__ok[0:0] + attribute \src "issuer_ls180.v:46663.3-46691.6" + wire width 2 $2\fus_oper_i_alu_logical0__input_carry[1:0] + attribute \src "issuer_ls180.v:46866.3-46894.6" + wire width 32 $2\fus_oper_i_alu_logical0__insn[31:0] + attribute \src "issuer_ls180.v:46457.3-46485.6" + wire width 7 $2\fus_oper_i_alu_logical0__insn_type[6:0] + attribute \src "issuer_ls180.v:46605.3-46633.6" + wire $2\fus_oper_i_alu_logical0__invert_in[0:0] + attribute \src "issuer_ls180.v:46692.3-46720.6" + wire $2\fus_oper_i_alu_logical0__invert_out[0:0] + attribute \src "issuer_ls180.v:46779.3-46807.6" + wire $2\fus_oper_i_alu_logical0__is_32bit[0:0] + attribute \src "issuer_ls180.v:46808.3-46836.6" + wire $2\fus_oper_i_alu_logical0__is_signed[0:0] + attribute \src "issuer_ls180.v:46575.3-46604.6" + wire $2\fus_oper_i_alu_logical0__oe__oe[0:0] + attribute \src "issuer_ls180.v:46575.3-46604.6" + wire $2\fus_oper_i_alu_logical0__oe__ok[0:0] + attribute \src "issuer_ls180.v:46750.3-46778.6" + wire $2\fus_oper_i_alu_logical0__output_carry[0:0] + attribute \src "issuer_ls180.v:46545.3-46574.6" + wire $2\fus_oper_i_alu_logical0__rc__ok[0:0] + attribute \src "issuer_ls180.v:46545.3-46574.6" + wire $2\fus_oper_i_alu_logical0__rc__rc[0:0] + attribute \src "issuer_ls180.v:46721.3-46749.6" + wire $2\fus_oper_i_alu_logical0__write_cr0[0:0] + attribute \src "issuer_ls180.v:46634.3-46662.6" + wire $2\fus_oper_i_alu_logical0__zero_a[0:0] + attribute \src "issuer_ls180.v:42863.3-42891.6" + wire width 12 $2\fus_oper_i_alu_mul0__fn_unit[11:0] + attribute \src "issuer_ls180.v:42892.3-42921.6" + wire width 64 $2\fus_oper_i_alu_mul0__imm_data__data[63:0] + attribute \src "issuer_ls180.v:42892.3-42921.6" + wire $2\fus_oper_i_alu_mul0__imm_data__ok[0:0] + attribute \src "issuer_ls180.v:43069.3-43097.6" + wire width 32 $2\fus_oper_i_alu_mul0__insn[31:0] + attribute \src "issuer_ls180.v:42834.3-42862.6" + wire width 7 $2\fus_oper_i_alu_mul0__insn_type[6:0] + attribute \src "issuer_ls180.v:43011.3-43039.6" + wire $2\fus_oper_i_alu_mul0__is_32bit[0:0] + attribute \src "issuer_ls180.v:43040.3-43068.6" + wire $2\fus_oper_i_alu_mul0__is_signed[0:0] + attribute \src "issuer_ls180.v:42952.3-42981.6" + wire $2\fus_oper_i_alu_mul0__oe__oe[0:0] + attribute \src "issuer_ls180.v:42952.3-42981.6" + wire $2\fus_oper_i_alu_mul0__oe__ok[0:0] + attribute \src "issuer_ls180.v:42922.3-42951.6" + wire $2\fus_oper_i_alu_mul0__rc__ok[0:0] + attribute \src "issuer_ls180.v:42922.3-42951.6" + wire $2\fus_oper_i_alu_mul0__rc__rc[0:0] + attribute \src "issuer_ls180.v:42982.3-43010.6" + wire $2\fus_oper_i_alu_mul0__write_cr0[0:0] + attribute \src "issuer_ls180.v:43185.3-43213.6" + wire width 12 $2\fus_oper_i_alu_shift_rot0__fn_unit[11:0] + attribute \src "issuer_ls180.v:43214.3-43243.6" + wire width 64 $2\fus_oper_i_alu_shift_rot0__imm_data__data[63:0] + attribute \src "issuer_ls180.v:43214.3-43243.6" + wire $2\fus_oper_i_alu_shift_rot0__imm_data__ok[0:0] + attribute \src "issuer_ls180.v:43333.3-43361.6" + wire width 2 $2\fus_oper_i_alu_shift_rot0__input_carry[1:0] + attribute \src "issuer_ls180.v:43391.3-43419.6" + wire $2\fus_oper_i_alu_shift_rot0__input_cr[0:0] + attribute \src "issuer_ls180.v:43507.3-43535.6" + wire width 32 $2\fus_oper_i_alu_shift_rot0__insn[31:0] + attribute \src "issuer_ls180.v:43156.3-43184.6" + wire width 7 $2\fus_oper_i_alu_shift_rot0__insn_type[6:0] + attribute \src "issuer_ls180.v:43449.3-43477.6" + wire $2\fus_oper_i_alu_shift_rot0__is_32bit[0:0] + attribute \src "issuer_ls180.v:43478.3-43506.6" + wire $2\fus_oper_i_alu_shift_rot0__is_signed[0:0] + attribute \src "issuer_ls180.v:43274.3-43303.6" + wire $2\fus_oper_i_alu_shift_rot0__oe__oe[0:0] + attribute \src "issuer_ls180.v:43274.3-43303.6" + wire $2\fus_oper_i_alu_shift_rot0__oe__ok[0:0] + attribute \src "issuer_ls180.v:43362.3-43390.6" + wire $2\fus_oper_i_alu_shift_rot0__output_carry[0:0] + attribute \src "issuer_ls180.v:43420.3-43448.6" + wire $2\fus_oper_i_alu_shift_rot0__output_cr[0:0] + attribute \src "issuer_ls180.v:43244.3-43273.6" + wire $2\fus_oper_i_alu_shift_rot0__rc__ok[0:0] + attribute \src "issuer_ls180.v:43244.3-43273.6" + wire $2\fus_oper_i_alu_shift_rot0__rc__rc[0:0] + attribute \src "issuer_ls180.v:43304.3-43332.6" + wire $2\fus_oper_i_alu_shift_rot0__write_cr0[0:0] + attribute \src "issuer_ls180.v:46982.3-47010.6" + wire width 12 $2\fus_oper_i_alu_spr0__fn_unit[11:0] + attribute \src "issuer_ls180.v:47011.3-47039.6" + wire width 32 $2\fus_oper_i_alu_spr0__insn[31:0] + attribute \src "issuer_ls180.v:46953.3-46981.6" + wire width 7 $2\fus_oper_i_alu_spr0__insn_type[6:0] + attribute \src "issuer_ls180.v:42251.3-42279.6" + wire $2\fus_oper_i_alu_spr0__is_32bit[0:0] + attribute \src "issuer_ls180.v:46283.3-46311.6" + wire width 64 $2\fus_oper_i_alu_trap0__cia[63:0] + attribute \src "issuer_ls180.v:46187.3-46215.6" + wire width 12 $2\fus_oper_i_alu_trap0__fn_unit[11:0] + attribute \src "issuer_ls180.v:46225.3-46253.6" + wire width 32 $2\fus_oper_i_alu_trap0__insn[31:0] + attribute \src "issuer_ls180.v:46149.3-46177.6" + wire width 7 $2\fus_oper_i_alu_trap0__insn_type[6:0] + attribute \src "issuer_ls180.v:46312.3-46340.6" + wire $2\fus_oper_i_alu_trap0__is_32bit[0:0] + attribute \src "issuer_ls180.v:46254.3-46282.6" + wire width 64 $2\fus_oper_i_alu_trap0__msr[63:0] + attribute \src "issuer_ls180.v:46370.3-46398.6" + wire width 13 $2\fus_oper_i_alu_trap0__trapaddr[12:0] + attribute \src "issuer_ls180.v:46341.3-46369.6" + wire width 7 $2\fus_oper_i_alu_trap0__traptype[6:0] + attribute \src "issuer_ls180.v:43858.3-43886.6" + wire $2\fus_oper_i_ldst_ldst0__byte_reverse[0:0] + attribute \src "issuer_ls180.v:43829.3-43857.6" + wire width 4 $2\fus_oper_i_ldst_ldst0__data_len[3:0] + attribute \src "issuer_ls180.v:43623.3-43651.6" + wire width 12 $2\fus_oper_i_ldst_ldst0__fn_unit[11:0] + attribute \src "issuer_ls180.v:43652.3-43681.6" + wire width 64 $2\fus_oper_i_ldst_ldst0__imm_data__data[63:0] + attribute \src "issuer_ls180.v:43652.3-43681.6" + wire $2\fus_oper_i_ldst_ldst0__imm_data__ok[0:0] + attribute \src "issuer_ls180.v:43945.3-43973.6" + wire width 32 $2\fus_oper_i_ldst_ldst0__insn[31:0] + attribute \src "issuer_ls180.v:43594.3-43622.6" + wire width 7 $2\fus_oper_i_ldst_ldst0__insn_type[6:0] + attribute \src "issuer_ls180.v:43771.3-43799.6" + wire $2\fus_oper_i_ldst_ldst0__is_32bit[0:0] + attribute \src "issuer_ls180.v:43800.3-43828.6" + wire $2\fus_oper_i_ldst_ldst0__is_signed[0:0] + attribute \src "issuer_ls180.v:43916.3-43944.6" + wire width 2 $2\fus_oper_i_ldst_ldst0__ldst_mode[1:0] + attribute \src "issuer_ls180.v:43741.3-43770.6" + wire $2\fus_oper_i_ldst_ldst0__oe__oe[0:0] + attribute \src "issuer_ls180.v:43741.3-43770.6" + wire $2\fus_oper_i_ldst_ldst0__oe__ok[0:0] + attribute \src "issuer_ls180.v:43711.3-43740.6" + wire $2\fus_oper_i_ldst_ldst0__rc__ok[0:0] + attribute \src "issuer_ls180.v:43711.3-43740.6" + wire $2\fus_oper_i_ldst_ldst0__rc__rc[0:0] + attribute \src "issuer_ls180.v:43887.3-43915.6" + wire $2\fus_oper_i_ldst_ldst0__sign_extend[0:0] + attribute \src "issuer_ls180.v:43682.3-43710.6" + wire $2\fus_oper_i_ldst_ldst0__zero_a[0:0] + attribute \src "issuer_ls180.v:44577.3-44597.6" + wire $3\core_terminate_o$next[0:0]$2515 + attribute \src "issuer_ls180.v:44448.3-44538.6" + wire $3\corebusy_o[0:0] + attribute \src "issuer_ls180.v:44393.3-44419.6" + wire width 2 $3\counter$next[1:0]$2489 + attribute \src "issuer_ls180.v:46399.3-46427.6" + wire $3\fus_cu_issue_i$10[0:0]$2787 + attribute \src "issuer_ls180.v:46895.3-46923.6" + wire $3\fus_cu_issue_i$13[0:0]$2812 + attribute \src "issuer_ls180.v:42280.3-42308.6" + wire $3\fus_cu_issue_i$16[0:0]$2281 + attribute \src "issuer_ls180.v:42776.3-42804.6" + wire $3\fus_cu_issue_i$19[0:0]$2306 + attribute \src "issuer_ls180.v:43098.3-43126.6" + wire $3\fus_cu_issue_i$22[0:0]$2325 + attribute \src "issuer_ls180.v:43536.3-43564.6" + wire $3\fus_cu_issue_i$25[0:0]$2348 + attribute \src "issuer_ls180.v:43974.3-44002.6" + wire $3\fus_cu_issue_i$28[0:0]$2371 + attribute \src "issuer_ls180.v:45667.3-45695.6" + wire $3\fus_cu_issue_i$4[0:0]$2692 + attribute \src "issuer_ls180.v:46064.3-46092.6" + wire $3\fus_cu_issue_i$7[0:0]$2754 + attribute \src "issuer_ls180.v:45459.3-45487.6" + wire $3\fus_cu_issue_i[0:0] + attribute \src "issuer_ls180.v:46428.3-46456.6" + wire width 4 $3\fus_cu_rdmaskn_i$12[3:0]$2792 + attribute \src "issuer_ls180.v:46924.3-46952.6" + wire width 3 $3\fus_cu_rdmaskn_i$15[2:0]$2817 + attribute \src "issuer_ls180.v:42309.3-42337.6" + wire width 6 $3\fus_cu_rdmaskn_i$18[5:0]$2286 + attribute \src "issuer_ls180.v:42805.3-42833.6" + wire width 3 $3\fus_cu_rdmaskn_i$21[2:0]$2311 + attribute \src "issuer_ls180.v:43127.3-43155.6" + wire width 3 $3\fus_cu_rdmaskn_i$24[2:0]$2330 + attribute \src "issuer_ls180.v:43565.3-43593.6" + wire width 5 $3\fus_cu_rdmaskn_i$27[4:0]$2353 + attribute \src "issuer_ls180.v:44003.3-44031.6" + wire width 3 $3\fus_cu_rdmaskn_i$30[2:0]$2376 + attribute \src "issuer_ls180.v:45714.3-45742.6" + wire width 6 $3\fus_cu_rdmaskn_i$6[5:0]$2703 + attribute \src "issuer_ls180.v:46102.3-46130.6" + wire width 3 $3\fus_cu_rdmaskn_i$9[2:0]$2762 + attribute \src "issuer_ls180.v:45497.3-45525.6" + wire width 4 $3\fus_cu_rdmaskn_i[3:0] + attribute \src "issuer_ls180.v:45374.3-45402.6" + wire width 4 $3\fus_oper_i_alu_alu0__data_len[3:0] + attribute \src "issuer_ls180.v:44694.3-44722.6" + wire width 12 $3\fus_oper_i_alu_alu0__fn_unit[11:0] + attribute \src "issuer_ls180.v:44761.3-44790.6" + wire width 64 $3\fus_oper_i_alu_alu0__imm_data__data[63:0] + attribute \src "issuer_ls180.v:44761.3-44790.6" + wire $3\fus_oper_i_alu_alu0__imm_data__ok[0:0] + attribute \src "issuer_ls180.v:45213.3-45241.6" + wire width 2 $3\fus_oper_i_alu_alu0__input_carry[1:0] + attribute \src "issuer_ls180.v:45421.3-45449.6" + wire width 32 $3\fus_oper_i_alu_alu0__insn[31:0] + attribute \src "issuer_ls180.v:44636.3-44664.6" + wire width 7 $3\fus_oper_i_alu_alu0__insn_type[6:0] + attribute \src "issuer_ls180.v:45003.3-45031.6" + wire $3\fus_oper_i_alu_alu0__invert_in[0:0] + attribute \src "issuer_ls180.v:45118.3-45146.6" + wire $3\fus_oper_i_alu_alu0__invert_out[0:0] + attribute \src "issuer_ls180.v:45298.3-45326.6" + wire $3\fus_oper_i_alu_alu0__is_32bit[0:0] + attribute \src "issuer_ls180.v:45336.3-45364.6" + wire $3\fus_oper_i_alu_alu0__is_signed[0:0] + attribute \src "issuer_ls180.v:44916.3-44945.6" + wire $3\fus_oper_i_alu_alu0__oe__oe[0:0] + attribute \src "issuer_ls180.v:44916.3-44945.6" + wire $3\fus_oper_i_alu_alu0__oe__ok[0:0] + attribute \src "issuer_ls180.v:45251.3-45279.6" + wire $3\fus_oper_i_alu_alu0__output_carry[0:0] + attribute \src "issuer_ls180.v:44829.3-44858.6" + wire $3\fus_oper_i_alu_alu0__rc__ok[0:0] + attribute \src "issuer_ls180.v:44829.3-44858.6" + wire $3\fus_oper_i_alu_alu0__rc__rc[0:0] + attribute \src "issuer_ls180.v:45166.3-45194.6" + wire $3\fus_oper_i_alu_alu0__write_cr0[0:0] + attribute \src "issuer_ls180.v:45060.3-45088.6" + wire $3\fus_oper_i_alu_alu0__zero_a[0:0] + attribute \src "issuer_ls180.v:45752.3-45780.6" + wire width 64 $3\fus_oper_i_alu_branch0__cia[63:0] + attribute \src "issuer_ls180.v:45837.3-45865.6" + wire width 12 $3\fus_oper_i_alu_branch0__fn_unit[11:0] + attribute \src "issuer_ls180.v:45922.3-45951.6" + wire width 64 $3\fus_oper_i_alu_branch0__imm_data__data[63:0] + attribute \src "issuer_ls180.v:45922.3-45951.6" + wire $3\fus_oper_i_alu_branch0__imm_data__ok[0:0] + attribute \src "issuer_ls180.v:45875.3-45903.6" + wire width 32 $3\fus_oper_i_alu_branch0__insn[31:0] + attribute \src "issuer_ls180.v:45799.3-45827.6" + wire width 7 $3\fus_oper_i_alu_branch0__insn_type[6:0] + attribute \src "issuer_ls180.v:46017.3-46045.6" + wire $3\fus_oper_i_alu_branch0__is_32bit[0:0] + attribute \src "issuer_ls180.v:45979.3-46007.6" + wire $3\fus_oper_i_alu_branch0__lk[0:0] + attribute \src "issuer_ls180.v:45582.3-45610.6" + wire width 12 $3\fus_oper_i_alu_cr0__fn_unit[11:0] + attribute \src "issuer_ls180.v:45629.3-45657.6" + wire width 32 $3\fus_oper_i_alu_cr0__insn[31:0] + attribute \src "issuer_ls180.v:45544.3-45572.6" + wire width 7 $3\fus_oper_i_alu_cr0__insn_type[6:0] + attribute \src "issuer_ls180.v:42718.3-42746.6" + wire width 4 $3\fus_oper_i_alu_div0__data_len[3:0] + attribute \src "issuer_ls180.v:42367.3-42395.6" + wire width 12 $3\fus_oper_i_alu_div0__fn_unit[11:0] + attribute \src "issuer_ls180.v:42396.3-42425.6" + wire width 64 $3\fus_oper_i_alu_div0__imm_data__data[63:0] + attribute \src "issuer_ls180.v:42396.3-42425.6" + wire $3\fus_oper_i_alu_div0__imm_data__ok[0:0] + attribute \src "issuer_ls180.v:42544.3-42572.6" + wire width 2 $3\fus_oper_i_alu_div0__input_carry[1:0] + attribute \src "issuer_ls180.v:42747.3-42775.6" + wire width 32 $3\fus_oper_i_alu_div0__insn[31:0] + attribute \src "issuer_ls180.v:42338.3-42366.6" + wire width 7 $3\fus_oper_i_alu_div0__insn_type[6:0] + attribute \src "issuer_ls180.v:42486.3-42514.6" + wire $3\fus_oper_i_alu_div0__invert_in[0:0] + attribute \src "issuer_ls180.v:42573.3-42601.6" + wire $3\fus_oper_i_alu_div0__invert_out[0:0] + attribute \src "issuer_ls180.v:42660.3-42688.6" + wire $3\fus_oper_i_alu_div0__is_32bit[0:0] + attribute \src "issuer_ls180.v:42689.3-42717.6" + wire $3\fus_oper_i_alu_div0__is_signed[0:0] + attribute \src "issuer_ls180.v:42456.3-42485.6" + wire $3\fus_oper_i_alu_div0__oe__oe[0:0] + attribute \src "issuer_ls180.v:42456.3-42485.6" + wire $3\fus_oper_i_alu_div0__oe__ok[0:0] + attribute \src "issuer_ls180.v:42631.3-42659.6" + wire $3\fus_oper_i_alu_div0__output_carry[0:0] + attribute \src "issuer_ls180.v:42426.3-42455.6" + wire $3\fus_oper_i_alu_div0__rc__ok[0:0] + attribute \src "issuer_ls180.v:42426.3-42455.6" + wire $3\fus_oper_i_alu_div0__rc__rc[0:0] + attribute \src "issuer_ls180.v:42602.3-42630.6" + wire $3\fus_oper_i_alu_div0__write_cr0[0:0] + attribute \src "issuer_ls180.v:42515.3-42543.6" + wire $3\fus_oper_i_alu_div0__zero_a[0:0] + attribute \src "issuer_ls180.v:46837.3-46865.6" + wire width 4 $3\fus_oper_i_alu_logical0__data_len[3:0] + attribute \src "issuer_ls180.v:46486.3-46514.6" + wire width 12 $3\fus_oper_i_alu_logical0__fn_unit[11:0] + attribute \src "issuer_ls180.v:46515.3-46544.6" + wire width 64 $3\fus_oper_i_alu_logical0__imm_data__data[63:0] + attribute \src "issuer_ls180.v:46515.3-46544.6" + wire $3\fus_oper_i_alu_logical0__imm_data__ok[0:0] + attribute \src "issuer_ls180.v:46663.3-46691.6" + wire width 2 $3\fus_oper_i_alu_logical0__input_carry[1:0] + attribute \src "issuer_ls180.v:46866.3-46894.6" + wire width 32 $3\fus_oper_i_alu_logical0__insn[31:0] + attribute \src "issuer_ls180.v:46457.3-46485.6" + wire width 7 $3\fus_oper_i_alu_logical0__insn_type[6:0] + attribute \src "issuer_ls180.v:46605.3-46633.6" + wire $3\fus_oper_i_alu_logical0__invert_in[0:0] + attribute \src "issuer_ls180.v:46692.3-46720.6" + wire $3\fus_oper_i_alu_logical0__invert_out[0:0] + attribute \src "issuer_ls180.v:46779.3-46807.6" + wire $3\fus_oper_i_alu_logical0__is_32bit[0:0] + attribute \src "issuer_ls180.v:46808.3-46836.6" + wire $3\fus_oper_i_alu_logical0__is_signed[0:0] + attribute \src "issuer_ls180.v:46575.3-46604.6" + wire $3\fus_oper_i_alu_logical0__oe__oe[0:0] + attribute \src "issuer_ls180.v:46575.3-46604.6" + wire $3\fus_oper_i_alu_logical0__oe__ok[0:0] + attribute \src "issuer_ls180.v:46750.3-46778.6" + wire $3\fus_oper_i_alu_logical0__output_carry[0:0] + attribute \src "issuer_ls180.v:46545.3-46574.6" + wire $3\fus_oper_i_alu_logical0__rc__ok[0:0] + attribute \src "issuer_ls180.v:46545.3-46574.6" + wire $3\fus_oper_i_alu_logical0__rc__rc[0:0] + attribute \src "issuer_ls180.v:46721.3-46749.6" + wire $3\fus_oper_i_alu_logical0__write_cr0[0:0] + attribute \src "issuer_ls180.v:46634.3-46662.6" + wire $3\fus_oper_i_alu_logical0__zero_a[0:0] + attribute \src "issuer_ls180.v:42863.3-42891.6" + wire width 12 $3\fus_oper_i_alu_mul0__fn_unit[11:0] + attribute \src "issuer_ls180.v:42892.3-42921.6" + wire width 64 $3\fus_oper_i_alu_mul0__imm_data__data[63:0] + attribute \src "issuer_ls180.v:42892.3-42921.6" + wire $3\fus_oper_i_alu_mul0__imm_data__ok[0:0] + attribute \src "issuer_ls180.v:43069.3-43097.6" + wire width 32 $3\fus_oper_i_alu_mul0__insn[31:0] + attribute \src "issuer_ls180.v:42834.3-42862.6" + wire width 7 $3\fus_oper_i_alu_mul0__insn_type[6:0] + attribute \src "issuer_ls180.v:43011.3-43039.6" + wire $3\fus_oper_i_alu_mul0__is_32bit[0:0] + attribute \src "issuer_ls180.v:43040.3-43068.6" + wire $3\fus_oper_i_alu_mul0__is_signed[0:0] + attribute \src "issuer_ls180.v:42952.3-42981.6" + wire $3\fus_oper_i_alu_mul0__oe__oe[0:0] + attribute \src "issuer_ls180.v:42952.3-42981.6" + wire $3\fus_oper_i_alu_mul0__oe__ok[0:0] + attribute \src "issuer_ls180.v:42922.3-42951.6" + wire $3\fus_oper_i_alu_mul0__rc__ok[0:0] + attribute \src "issuer_ls180.v:42922.3-42951.6" + wire $3\fus_oper_i_alu_mul0__rc__rc[0:0] + attribute \src "issuer_ls180.v:42982.3-43010.6" + wire $3\fus_oper_i_alu_mul0__write_cr0[0:0] + attribute \src "issuer_ls180.v:43185.3-43213.6" + wire width 12 $3\fus_oper_i_alu_shift_rot0__fn_unit[11:0] + attribute \src "issuer_ls180.v:43214.3-43243.6" + wire width 64 $3\fus_oper_i_alu_shift_rot0__imm_data__data[63:0] + attribute \src "issuer_ls180.v:43214.3-43243.6" + wire $3\fus_oper_i_alu_shift_rot0__imm_data__ok[0:0] + attribute \src "issuer_ls180.v:43333.3-43361.6" + wire width 2 $3\fus_oper_i_alu_shift_rot0__input_carry[1:0] + attribute \src "issuer_ls180.v:43391.3-43419.6" + wire $3\fus_oper_i_alu_shift_rot0__input_cr[0:0] + attribute \src "issuer_ls180.v:43507.3-43535.6" + wire width 32 $3\fus_oper_i_alu_shift_rot0__insn[31:0] + attribute \src "issuer_ls180.v:43156.3-43184.6" + wire width 7 $3\fus_oper_i_alu_shift_rot0__insn_type[6:0] + attribute \src "issuer_ls180.v:43449.3-43477.6" + wire $3\fus_oper_i_alu_shift_rot0__is_32bit[0:0] + attribute \src "issuer_ls180.v:43478.3-43506.6" + wire $3\fus_oper_i_alu_shift_rot0__is_signed[0:0] + attribute \src "issuer_ls180.v:43274.3-43303.6" + wire $3\fus_oper_i_alu_shift_rot0__oe__oe[0:0] + attribute \src "issuer_ls180.v:43274.3-43303.6" + wire $3\fus_oper_i_alu_shift_rot0__oe__ok[0:0] + attribute \src "issuer_ls180.v:43362.3-43390.6" + wire $3\fus_oper_i_alu_shift_rot0__output_carry[0:0] + attribute \src "issuer_ls180.v:43420.3-43448.6" + wire $3\fus_oper_i_alu_shift_rot0__output_cr[0:0] + attribute \src "issuer_ls180.v:43244.3-43273.6" + wire $3\fus_oper_i_alu_shift_rot0__rc__ok[0:0] + attribute \src "issuer_ls180.v:43244.3-43273.6" + wire $3\fus_oper_i_alu_shift_rot0__rc__rc[0:0] + attribute \src "issuer_ls180.v:43304.3-43332.6" + wire $3\fus_oper_i_alu_shift_rot0__write_cr0[0:0] + attribute \src "issuer_ls180.v:46982.3-47010.6" + wire width 12 $3\fus_oper_i_alu_spr0__fn_unit[11:0] + attribute \src "issuer_ls180.v:47011.3-47039.6" + wire width 32 $3\fus_oper_i_alu_spr0__insn[31:0] + attribute \src "issuer_ls180.v:46953.3-46981.6" + wire width 7 $3\fus_oper_i_alu_spr0__insn_type[6:0] + attribute \src "issuer_ls180.v:42251.3-42279.6" + wire $3\fus_oper_i_alu_spr0__is_32bit[0:0] + attribute \src "issuer_ls180.v:46283.3-46311.6" + wire width 64 $3\fus_oper_i_alu_trap0__cia[63:0] + attribute \src "issuer_ls180.v:46187.3-46215.6" + wire width 12 $3\fus_oper_i_alu_trap0__fn_unit[11:0] + attribute \src "issuer_ls180.v:46225.3-46253.6" + wire width 32 $3\fus_oper_i_alu_trap0__insn[31:0] + attribute \src "issuer_ls180.v:46149.3-46177.6" + wire width 7 $3\fus_oper_i_alu_trap0__insn_type[6:0] + attribute \src "issuer_ls180.v:46312.3-46340.6" + wire $3\fus_oper_i_alu_trap0__is_32bit[0:0] + attribute \src "issuer_ls180.v:46254.3-46282.6" + wire width 64 $3\fus_oper_i_alu_trap0__msr[63:0] + attribute \src "issuer_ls180.v:46370.3-46398.6" + wire width 13 $3\fus_oper_i_alu_trap0__trapaddr[12:0] + attribute \src "issuer_ls180.v:46341.3-46369.6" + wire width 7 $3\fus_oper_i_alu_trap0__traptype[6:0] + attribute \src "issuer_ls180.v:43858.3-43886.6" + wire $3\fus_oper_i_ldst_ldst0__byte_reverse[0:0] + attribute \src "issuer_ls180.v:43829.3-43857.6" + wire width 4 $3\fus_oper_i_ldst_ldst0__data_len[3:0] + attribute \src "issuer_ls180.v:43623.3-43651.6" + wire width 12 $3\fus_oper_i_ldst_ldst0__fn_unit[11:0] + attribute \src "issuer_ls180.v:43652.3-43681.6" + wire width 64 $3\fus_oper_i_ldst_ldst0__imm_data__data[63:0] + attribute \src "issuer_ls180.v:43652.3-43681.6" + wire $3\fus_oper_i_ldst_ldst0__imm_data__ok[0:0] + attribute \src "issuer_ls180.v:43945.3-43973.6" + wire width 32 $3\fus_oper_i_ldst_ldst0__insn[31:0] + attribute \src "issuer_ls180.v:43594.3-43622.6" + wire width 7 $3\fus_oper_i_ldst_ldst0__insn_type[6:0] + attribute \src "issuer_ls180.v:43771.3-43799.6" + wire $3\fus_oper_i_ldst_ldst0__is_32bit[0:0] + attribute \src "issuer_ls180.v:43800.3-43828.6" + wire $3\fus_oper_i_ldst_ldst0__is_signed[0:0] + attribute \src "issuer_ls180.v:43916.3-43944.6" + wire width 2 $3\fus_oper_i_ldst_ldst0__ldst_mode[1:0] + attribute \src "issuer_ls180.v:43741.3-43770.6" + wire $3\fus_oper_i_ldst_ldst0__oe__oe[0:0] + attribute \src "issuer_ls180.v:43741.3-43770.6" + wire $3\fus_oper_i_ldst_ldst0__oe__ok[0:0] + attribute \src "issuer_ls180.v:43711.3-43740.6" + wire $3\fus_oper_i_ldst_ldst0__rc__ok[0:0] + attribute \src "issuer_ls180.v:43711.3-43740.6" + wire $3\fus_oper_i_ldst_ldst0__rc__rc[0:0] + attribute \src "issuer_ls180.v:43887.3-43915.6" + wire $3\fus_oper_i_ldst_ldst0__sign_extend[0:0] + attribute \src "issuer_ls180.v:43682.3-43710.6" + wire $3\fus_oper_i_ldst_ldst0__zero_a[0:0] + attribute \src "issuer_ls180.v:44448.3-44538.6" + wire $4\corebusy_o[0:0] + attribute \src "issuer_ls180.v:44393.3-44419.6" + wire width 2 $4\counter$next[1:0]$2490 + attribute \src "issuer_ls180.v:44448.3-44538.6" + wire $5\corebusy_o[0:0] + attribute \src "issuer_ls180.v:44448.3-44538.6" + wire $6\corebusy_o[0:0] + attribute \src "issuer_ls180.v:44448.3-44538.6" + wire $7\corebusy_o[0:0] + attribute \src "issuer_ls180.v:44448.3-44538.6" + wire $8\corebusy_o[0:0] + attribute \src "issuer_ls180.v:44448.3-44538.6" + wire $9\corebusy_o[0:0] + attribute \src "issuer_ls180.v:40658.20-40658.122" + wire $and$issuer_ls180.v:40658$1430_Y + attribute \src "issuer_ls180.v:40659.20-40659.126" + wire $and$issuer_ls180.v:40659$1431_Y + attribute \src "issuer_ls180.v:40661.20-40661.110" + wire $and$issuer_ls180.v:40661$1433_Y + attribute \src "issuer_ls180.v:40662.20-40662.123" + wire $and$issuer_ls180.v:40662$1434_Y + attribute \src "issuer_ls180.v:40664.20-40664.122" + wire $and$issuer_ls180.v:40664$1436_Y + attribute \src "issuer_ls180.v:40665.20-40665.126" + wire $and$issuer_ls180.v:40665$1437_Y + attribute \src "issuer_ls180.v:40667.20-40667.110" + wire $and$issuer_ls180.v:40667$1439_Y + attribute \src "issuer_ls180.v:40668.20-40668.123" + wire $and$issuer_ls180.v:40668$1440_Y + attribute \src "issuer_ls180.v:40670.20-40670.122" + wire $and$issuer_ls180.v:40670$1442_Y + attribute \src "issuer_ls180.v:40671.20-40671.126" + wire $and$issuer_ls180.v:40671$1443_Y + attribute \src "issuer_ls180.v:40673.20-40673.110" + wire $and$issuer_ls180.v:40673$1445_Y + attribute \src "issuer_ls180.v:40674.20-40674.123" + wire $and$issuer_ls180.v:40674$1446_Y + attribute \src "issuer_ls180.v:40676.20-40676.122" + wire $and$issuer_ls180.v:40676$1448_Y + attribute \src "issuer_ls180.v:40677.20-40677.126" + wire $and$issuer_ls180.v:40677$1449_Y + attribute \src "issuer_ls180.v:40679.20-40679.110" + wire $and$issuer_ls180.v:40679$1451_Y + attribute \src "issuer_ls180.v:40680.20-40680.123" + wire $and$issuer_ls180.v:40680$1452_Y + attribute \src "issuer_ls180.v:40682.20-40682.123" + wire $and$issuer_ls180.v:40682$1454_Y + attribute \src "issuer_ls180.v:40683.20-40683.126" + wire $and$issuer_ls180.v:40683$1455_Y + attribute \src "issuer_ls180.v:40685.20-40685.110" + wire $and$issuer_ls180.v:40685$1457_Y + attribute \src "issuer_ls180.v:40686.20-40686.123" + wire $and$issuer_ls180.v:40686$1458_Y + attribute \src "issuer_ls180.v:40688.20-40688.113" + wire $and$issuer_ls180.v:40688$1460_Y + attribute \src "issuer_ls180.v:40689.20-40689.126" + wire $and$issuer_ls180.v:40689$1461_Y + attribute \src "issuer_ls180.v:40691.20-40691.110" + wire $and$issuer_ls180.v:40691$1463_Y + attribute \src "issuer_ls180.v:40692.20-40692.123" + wire $and$issuer_ls180.v:40692$1464_Y + attribute \src "issuer_ls180.v:40694.20-40694.114" + wire $and$issuer_ls180.v:40694$1466_Y + attribute \src "issuer_ls180.v:40695.20-40695.126" + wire $and$issuer_ls180.v:40695$1467_Y + attribute \src "issuer_ls180.v:40697.20-40697.110" + wire $and$issuer_ls180.v:40697$1469_Y + attribute \src "issuer_ls180.v:40698.20-40698.123" + wire $and$issuer_ls180.v:40698$1470_Y + attribute \src "issuer_ls180.v:40727.20-40727.122" + wire $and$issuer_ls180.v:40727$1499_Y + attribute \src "issuer_ls180.v:40728.20-40728.128" + wire $and$issuer_ls180.v:40728$1500_Y + attribute \src "issuer_ls180.v:40729.20-40729.133" + wire $and$issuer_ls180.v:40729$1501_Y + attribute \src "issuer_ls180.v:40731.20-40731.110" + wire $and$issuer_ls180.v:40731$1503_Y + attribute \src "issuer_ls180.v:40732.20-40732.128" + wire $and$issuer_ls180.v:40732$1504_Y + attribute \src "issuer_ls180.v:40734.20-40734.116" + wire $and$issuer_ls180.v:40734$1506_Y + attribute \src "issuer_ls180.v:40735.20-40735.123" + wire $and$issuer_ls180.v:40735$1507_Y + attribute \src "issuer_ls180.v:40736.20-40736.128" + wire $and$issuer_ls180.v:40736$1508_Y + attribute \src "issuer_ls180.v:40737.20-40737.128" + wire $and$issuer_ls180.v:40737$1509_Y + attribute \src "issuer_ls180.v:40738.20-40738.128" + wire $and$issuer_ls180.v:40738$1510_Y + attribute \src "issuer_ls180.v:40739.20-40739.128" + wire $and$issuer_ls180.v:40739$1511_Y + attribute \src "issuer_ls180.v:40740.20-40740.129" + wire $and$issuer_ls180.v:40740$1512_Y + attribute \src "issuer_ls180.v:40741.20-40741.130" + wire $and$issuer_ls180.v:40741$1513_Y + attribute \src "issuer_ls180.v:40743.20-40743.110" + wire $and$issuer_ls180.v:40743$1515_Y + attribute \src "issuer_ls180.v:40744.20-40744.125" + wire $and$issuer_ls180.v:40744$1516_Y + attribute \src "issuer_ls180.v:40748.20-40748.125" + wire $and$issuer_ls180.v:40748$1520_Y + attribute \src "issuer_ls180.v:40749.20-40749.130" + wire $and$issuer_ls180.v:40749$1521_Y + attribute \src "issuer_ls180.v:40751.20-40751.110" + wire $and$issuer_ls180.v:40751$1523_Y + attribute \src "issuer_ls180.v:40752.20-40752.125" + wire $and$issuer_ls180.v:40752$1524_Y + attribute \src "issuer_ls180.v:40756.20-40756.126" + wire $and$issuer_ls180.v:40756$1528_Y + attribute \src "issuer_ls180.v:40757.20-40757.130" + wire $and$issuer_ls180.v:40757$1529_Y + attribute \src "issuer_ls180.v:40759.20-40759.110" + wire $and$issuer_ls180.v:40759$1531_Y + attribute \src "issuer_ls180.v:40760.20-40760.125" + wire $and$issuer_ls180.v:40760$1532_Y + attribute \src "issuer_ls180.v:40764.20-40764.126" + wire $and$issuer_ls180.v:40764$1536_Y + attribute \src "issuer_ls180.v:40765.20-40765.130" + wire $and$issuer_ls180.v:40765$1537_Y + attribute \src "issuer_ls180.v:40767.20-40767.110" + wire $and$issuer_ls180.v:40767$1539_Y + attribute \src "issuer_ls180.v:40768.20-40768.125" + wire $and$issuer_ls180.v:40768$1540_Y + attribute \src "issuer_ls180.v:40772.20-40772.126" + wire $and$issuer_ls180.v:40772$1544_Y + attribute \src "issuer_ls180.v:40773.20-40773.130" + wire $and$issuer_ls180.v:40773$1545_Y + attribute \src "issuer_ls180.v:40775.20-40775.110" + wire $and$issuer_ls180.v:40775$1547_Y + attribute \src "issuer_ls180.v:40776.20-40776.125" + wire $and$issuer_ls180.v:40776$1548_Y + attribute \src "issuer_ls180.v:40780.20-40780.126" + wire $and$issuer_ls180.v:40780$1552_Y + attribute \src "issuer_ls180.v:40781.20-40781.130" + wire $and$issuer_ls180.v:40781$1553_Y + attribute \src "issuer_ls180.v:40783.20-40783.110" + wire $and$issuer_ls180.v:40783$1555_Y + attribute \src "issuer_ls180.v:40784.20-40784.125" + wire $and$issuer_ls180.v:40784$1556_Y + attribute \src "issuer_ls180.v:40798.20-40798.118" + wire $and$issuer_ls180.v:40798$1570_Y + attribute \src "issuer_ls180.v:40799.20-40799.123" + wire $and$issuer_ls180.v:40799$1571_Y + attribute \src "issuer_ls180.v:40800.20-40800.128" + wire $and$issuer_ls180.v:40800$1572_Y + attribute \src "issuer_ls180.v:40801.20-40801.129" + wire $and$issuer_ls180.v:40801$1573_Y + attribute \src "issuer_ls180.v:40802.20-40802.136" + wire $and$issuer_ls180.v:40802$1574_Y + attribute \src "issuer_ls180.v:40804.20-40804.110" + wire $and$issuer_ls180.v:40804$1576_Y + attribute \src "issuer_ls180.v:40805.20-40805.128" + wire $and$issuer_ls180.v:40805$1577_Y + attribute \src "issuer_ls180.v:40807.20-40807.128" + wire $and$issuer_ls180.v:40807$1579_Y + attribute \src "issuer_ls180.v:40808.20-40808.136" + wire $and$issuer_ls180.v:40808$1580_Y + attribute \src "issuer_ls180.v:40810.20-40810.110" + wire $and$issuer_ls180.v:40810$1582_Y + attribute \src "issuer_ls180.v:40811.20-40811.128" + wire $and$issuer_ls180.v:40811$1583_Y + attribute \src "issuer_ls180.v:40813.20-40813.128" + wire $and$issuer_ls180.v:40813$1585_Y + attribute \src "issuer_ls180.v:40814.20-40814.136" + wire $and$issuer_ls180.v:40814$1586_Y + attribute \src "issuer_ls180.v:40816.20-40816.110" + wire $and$issuer_ls180.v:40816$1588_Y + attribute \src "issuer_ls180.v:40817.20-40817.128" + wire $and$issuer_ls180.v:40817$1589_Y + attribute \src "issuer_ls180.v:40824.20-40824.118" + wire $and$issuer_ls180.v:40824$1597_Y + attribute \src "issuer_ls180.v:40825.20-40825.123" + wire $and$issuer_ls180.v:40825$1598_Y + attribute \src "issuer_ls180.v:40826.20-40826.128" + wire $and$issuer_ls180.v:40826$1599_Y + attribute \src "issuer_ls180.v:40827.20-40827.128" + wire $and$issuer_ls180.v:40827$1600_Y + attribute \src "issuer_ls180.v:40828.20-40828.128" + wire $and$issuer_ls180.v:40828$1601_Y + attribute \src "issuer_ls180.v:40829.20-40829.136" + wire $and$issuer_ls180.v:40829$1602_Y + attribute \src "issuer_ls180.v:40831.20-40831.110" + wire $and$issuer_ls180.v:40831$1604_Y + attribute \src "issuer_ls180.v:40832.20-40832.128" + wire $and$issuer_ls180.v:40832$1605_Y + attribute \src "issuer_ls180.v:40834.20-40834.128" + wire $and$issuer_ls180.v:40834$1607_Y + attribute \src "issuer_ls180.v:40835.20-40835.136" + wire $and$issuer_ls180.v:40835$1608_Y + attribute \src "issuer_ls180.v:40837.20-40837.110" + wire $and$issuer_ls180.v:40837$1610_Y + attribute \src "issuer_ls180.v:40838.20-40838.128" + wire $and$issuer_ls180.v:40838$1611_Y + attribute \src "issuer_ls180.v:40840.20-40840.128" + wire $and$issuer_ls180.v:40840$1613_Y + attribute \src "issuer_ls180.v:40841.20-40841.136" + wire $and$issuer_ls180.v:40841$1614_Y + attribute \src "issuer_ls180.v:40843.20-40843.110" + wire $and$issuer_ls180.v:40843$1616_Y + attribute \src "issuer_ls180.v:40844.20-40844.128" + wire $and$issuer_ls180.v:40844$1617_Y + attribute \src "issuer_ls180.v:40846.20-40846.128" + wire $and$issuer_ls180.v:40846$1619_Y + attribute \src "issuer_ls180.v:40847.20-40847.136" + wire $and$issuer_ls180.v:40847$1620_Y + attribute \src "issuer_ls180.v:40849.20-40849.110" + wire $and$issuer_ls180.v:40849$1622_Y + attribute \src "issuer_ls180.v:40850.20-40850.128" + wire $and$issuer_ls180.v:40850$1623_Y + attribute \src "issuer_ls180.v:40858.20-40858.118" + wire $and$issuer_ls180.v:40858$1631_Y + attribute \src "issuer_ls180.v:40859.20-40859.123" + wire $and$issuer_ls180.v:40859$1632_Y + attribute \src "issuer_ls180.v:40860.20-40860.128" + wire $and$issuer_ls180.v:40860$1633_Y + attribute \src "issuer_ls180.v:40861.20-40861.128" + wire $and$issuer_ls180.v:40861$1634_Y + attribute \src "issuer_ls180.v:40862.20-40862.128" + wire $and$issuer_ls180.v:40862$1635_Y + attribute \src "issuer_ls180.v:40863.20-40863.136" + wire $and$issuer_ls180.v:40863$1636_Y + attribute \src "issuer_ls180.v:40865.20-40865.110" + wire $and$issuer_ls180.v:40865$1638_Y + attribute \src "issuer_ls180.v:40866.20-40866.128" + wire $and$issuer_ls180.v:40866$1639_Y + attribute \src "issuer_ls180.v:40868.20-40868.128" + wire $and$issuer_ls180.v:40868$1641_Y + attribute \src "issuer_ls180.v:40869.20-40869.136" + wire $and$issuer_ls180.v:40869$1642_Y + attribute \src "issuer_ls180.v:40871.20-40871.110" + wire $and$issuer_ls180.v:40871$1644_Y + attribute \src "issuer_ls180.v:40872.20-40872.128" + wire $and$issuer_ls180.v:40872$1645_Y + attribute \src "issuer_ls180.v:40874.20-40874.128" + wire $and$issuer_ls180.v:40874$1647_Y + attribute \src "issuer_ls180.v:40875.20-40875.136" + wire $and$issuer_ls180.v:40875$1648_Y + attribute \src "issuer_ls180.v:40877.20-40877.110" + wire $and$issuer_ls180.v:40877$1650_Y + attribute \src "issuer_ls180.v:40878.20-40878.128" + wire $and$issuer_ls180.v:40878$1651_Y + attribute \src "issuer_ls180.v:40880.20-40880.128" + wire $and$issuer_ls180.v:40880$1653_Y + attribute \src "issuer_ls180.v:40881.20-40881.136" + wire $and$issuer_ls180.v:40881$1654_Y + attribute \src "issuer_ls180.v:40883.20-40883.110" + wire $and$issuer_ls180.v:40883$1656_Y + attribute \src "issuer_ls180.v:40884.20-40884.128" + wire $and$issuer_ls180.v:40884$1657_Y + attribute \src "issuer_ls180.v:40894.20-40894.120" + wire $and$issuer_ls180.v:40894$1669_Y + attribute \src "issuer_ls180.v:40895.20-40895.129" + wire $and$issuer_ls180.v:40895$1670_Y + attribute \src "issuer_ls180.v:40896.20-40896.128" + wire $and$issuer_ls180.v:40896$1671_Y + attribute \src "issuer_ls180.v:40897.20-40897.128" + wire $and$issuer_ls180.v:40897$1672_Y + attribute \src "issuer_ls180.v:40898.20-40898.129" + wire $and$issuer_ls180.v:40898$1673_Y + attribute \src "issuer_ls180.v:40899.20-40899.128" + wire $and$issuer_ls180.v:40899$1674_Y + attribute \src "issuer_ls180.v:40900.20-40900.136" + wire $and$issuer_ls180.v:40900$1675_Y + attribute \src "issuer_ls180.v:40902.20-40902.110" + wire $and$issuer_ls180.v:40902$1677_Y + attribute \src "issuer_ls180.v:40903.19-40903.112" + wire width 12 $and$issuer_ls180.v:40903$1678_Y + attribute \src "issuer_ls180.v:40904.20-40904.128" + wire $and$issuer_ls180.v:40904$1679_Y + attribute \src "issuer_ls180.v:40906.20-40906.127" + wire $and$issuer_ls180.v:40906$1681_Y + attribute \src "issuer_ls180.v:40908.20-40908.136" + wire $and$issuer_ls180.v:40908$1683_Y + attribute \src "issuer_ls180.v:40910.20-40910.110" + wire $and$issuer_ls180.v:40910$1685_Y + attribute \src "issuer_ls180.v:40911.20-40911.128" + wire $and$issuer_ls180.v:40911$1686_Y + attribute \src "issuer_ls180.v:40913.20-40913.127" + wire $and$issuer_ls180.v:40913$1688_Y + attribute \src "issuer_ls180.v:40914.20-40914.136" + wire $and$issuer_ls180.v:40914$1689_Y + attribute \src "issuer_ls180.v:40916.20-40916.110" + wire $and$issuer_ls180.v:40916$1691_Y + attribute \src "issuer_ls180.v:40917.20-40917.128" + wire $and$issuer_ls180.v:40917$1692_Y + attribute \src "issuer_ls180.v:40919.20-40919.120" + wire $and$issuer_ls180.v:40919$1694_Y + attribute \src "issuer_ls180.v:40920.19-40920.113" + wire width 12 $and$issuer_ls180.v:40920$1695_Y + attribute \src "issuer_ls180.v:40921.20-40921.136" + wire $and$issuer_ls180.v:40921$1696_Y + attribute \src "issuer_ls180.v:40923.20-40923.110" + wire $and$issuer_ls180.v:40923$1698_Y + attribute \src "issuer_ls180.v:40925.20-40925.128" + wire $and$issuer_ls180.v:40925$1700_Y + attribute \src "issuer_ls180.v:40927.20-40927.127" + wire $and$issuer_ls180.v:40927$1702_Y + attribute \src "issuer_ls180.v:40928.20-40928.136" + wire $and$issuer_ls180.v:40928$1703_Y + attribute \src "issuer_ls180.v:40930.20-40930.110" + wire $and$issuer_ls180.v:40930$1705_Y + attribute \src "issuer_ls180.v:40931.20-40931.128" + wire $and$issuer_ls180.v:40931$1706_Y + attribute \src "issuer_ls180.v:40938.19-40938.113" + wire width 12 $and$issuer_ls180.v:40938$1713_Y + attribute \src "issuer_ls180.v:40947.20-40947.118" + wire $and$issuer_ls180.v:40947$1722_Y + attribute \src "issuer_ls180.v:40948.20-40948.129" + wire $and$issuer_ls180.v:40948$1723_Y + attribute \src "issuer_ls180.v:40949.20-40949.128" + wire $and$issuer_ls180.v:40949$1724_Y + attribute \src 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$and$issuer_ls180.v:41152$1929_Y + attribute \src "issuer_ls180.v:41154.19-41154.102" + wire $and$issuer_ls180.v:41154$1931_Y + attribute \src "issuer_ls180.v:41155.19-41155.127" + wire $and$issuer_ls180.v:41155$1932_Y + attribute \src "issuer_ls180.v:41157.19-41157.127" + wire $and$issuer_ls180.v:41157$1934_Y + attribute \src "issuer_ls180.v:41158.19-41158.112" + wire $and$issuer_ls180.v:41158$1935_Y + attribute \src "issuer_ls180.v:41160.19-41160.102" + wire $and$issuer_ls180.v:41160$1937_Y + attribute \src "issuer_ls180.v:41161.19-41161.127" + wire $and$issuer_ls180.v:41161$1938_Y + attribute \src "issuer_ls180.v:41163.19-41163.127" + wire $and$issuer_ls180.v:41163$1940_Y + attribute \src "issuer_ls180.v:41164.19-41164.112" + wire $and$issuer_ls180.v:41164$1941_Y + attribute \src "issuer_ls180.v:41166.19-41166.102" + wire $and$issuer_ls180.v:41166$1943_Y + attribute \src "issuer_ls180.v:41167.19-41167.127" + wire $and$issuer_ls180.v:41167$1944_Y + attribute \src "issuer_ls180.v:41177.19-41177.127" + wire $and$issuer_ls180.v:41177$1954_Y + attribute \src "issuer_ls180.v:41178.19-41178.112" + wire $and$issuer_ls180.v:41178$1955_Y + attribute \src "issuer_ls180.v:41180.19-41180.102" + wire $and$issuer_ls180.v:41180$1957_Y + attribute \src "issuer_ls180.v:41181.19-41181.127" + wire $and$issuer_ls180.v:41181$1958_Y + attribute \src "issuer_ls180.v:41183.19-41183.127" + wire $and$issuer_ls180.v:41183$1960_Y + attribute \src "issuer_ls180.v:41184.19-41184.112" + wire $and$issuer_ls180.v:41184$1961_Y + attribute \src "issuer_ls180.v:41186.19-41186.102" + wire $and$issuer_ls180.v:41186$1963_Y + attribute \src "issuer_ls180.v:41187.19-41187.127" + wire $and$issuer_ls180.v:41187$1964_Y + attribute \src "issuer_ls180.v:41191.19-41191.131" + wire $and$issuer_ls180.v:41191$1968_Y + attribute \src "issuer_ls180.v:41192.19-41192.119" + wire width 3 $and$issuer_ls180.v:41192$1969_Y + attribute \src "issuer_ls180.v:41195.19-41195.131" + wire $and$issuer_ls180.v:41195$1972_Y + attribute \src "issuer_ls180.v:41197.19-41197.122" + wire $and$issuer_ls180.v:41197$1974_Y + attribute \src "issuer_ls180.v:41198.19-41198.116" + wire $and$issuer_ls180.v:41198$1975_Y + attribute \src "issuer_ls180.v:41200.19-41200.102" + wire $and$issuer_ls180.v:41200$1977_Y + attribute \src "issuer_ls180.v:41201.19-41201.135" + wire $and$issuer_ls180.v:41201$1978_Y + attribute \src "issuer_ls180.v:41203.19-41203.127" + wire $and$issuer_ls180.v:41203$1980_Y + attribute \src "issuer_ls180.v:41204.19-41204.116" + wire $and$issuer_ls180.v:41204$1981_Y + attribute \src "issuer_ls180.v:41206.19-41206.102" + wire $and$issuer_ls180.v:41206$1983_Y + attribute \src "issuer_ls180.v:41207.19-41207.135" + wire $and$issuer_ls180.v:41207$1984_Y + attribute \src "issuer_ls180.v:41209.19-41209.127" + wire $and$issuer_ls180.v:41209$1986_Y + attribute \src "issuer_ls180.v:41210.19-41210.116" + wire $and$issuer_ls180.v:41210$1987_Y + attribute \src "issuer_ls180.v:41212.19-41212.102" + wire $and$issuer_ls180.v:41212$1989_Y + attribute \src "issuer_ls180.v:41213.19-41213.135" + wire $and$issuer_ls180.v:41213$1990_Y + attribute \src "issuer_ls180.v:41215.19-41215.127" + wire $and$issuer_ls180.v:41215$1992_Y + attribute \src "issuer_ls180.v:41216.19-41216.116" + wire $and$issuer_ls180.v:41216$1993_Y + attribute \src "issuer_ls180.v:41218.19-41218.102" + wire $and$issuer_ls180.v:41218$1995_Y + attribute \src "issuer_ls180.v:41219.19-41219.135" + wire $and$issuer_ls180.v:41219$1996_Y + attribute \src "issuer_ls180.v:41221.19-41221.127" + wire $and$issuer_ls180.v:41221$1998_Y + attribute \src "issuer_ls180.v:41222.19-41222.116" + wire $and$issuer_ls180.v:41222$1999_Y + attribute \src "issuer_ls180.v:41224.19-41224.102" + wire $and$issuer_ls180.v:41224$2001_Y + attribute \src "issuer_ls180.v:41225.19-41225.135" + wire $and$issuer_ls180.v:41225$2002_Y + attribute \src "issuer_ls180.v:41227.19-41227.127" + wire $and$issuer_ls180.v:41227$2004_Y + attribute \src "issuer_ls180.v:41228.19-41228.116" + wire $and$issuer_ls180.v:41228$2005_Y + attribute \src "issuer_ls180.v:41230.19-41230.102" + wire $and$issuer_ls180.v:41230$2007_Y + attribute \src "issuer_ls180.v:41231.19-41231.135" + wire $and$issuer_ls180.v:41231$2008_Y + attribute \src "issuer_ls180.v:41240.19-41240.119" + wire width 3 $and$issuer_ls180.v:41240$2018_Y + attribute \src "issuer_ls180.v:41243.19-41243.122" + wire $and$issuer_ls180.v:41243$2021_Y + attribute \src "issuer_ls180.v:41244.19-41244.116" + wire $and$issuer_ls180.v:41244$2022_Y + attribute \src "issuer_ls180.v:41246.19-41246.102" + wire $and$issuer_ls180.v:41246$2024_Y + attribute \src "issuer_ls180.v:41247.19-41247.135" + wire $and$issuer_ls180.v:41247$2025_Y + attribute \src "issuer_ls180.v:41249.19-41249.127" + wire $and$issuer_ls180.v:41249$2027_Y + attribute \src "issuer_ls180.v:41250.19-41250.116" + wire $and$issuer_ls180.v:41250$2028_Y + attribute \src "issuer_ls180.v:41252.19-41252.102" + wire $and$issuer_ls180.v:41252$2030_Y + attribute \src "issuer_ls180.v:41253.19-41253.135" + wire $and$issuer_ls180.v:41253$2031_Y + attribute \src "issuer_ls180.v:41255.19-41255.127" + wire $and$issuer_ls180.v:41255$2033_Y + attribute \src "issuer_ls180.v:41256.19-41256.116" + wire $and$issuer_ls180.v:41256$2034_Y + attribute \src "issuer_ls180.v:41258.19-41258.102" + wire $and$issuer_ls180.v:41258$2036_Y + attribute \src "issuer_ls180.v:41259.19-41259.135" + wire $and$issuer_ls180.v:41259$2037_Y + attribute \src "issuer_ls180.v:41264.19-41264.131" + wire $and$issuer_ls180.v:41264$2043_Y + attribute \src "issuer_ls180.v:41265.19-41265.119" + wire width 3 $and$issuer_ls180.v:41265$2044_Y + attribute \src "issuer_ls180.v:41268.19-41268.127" + wire $and$issuer_ls180.v:41268$2047_Y + attribute \src "issuer_ls180.v:41269.19-41269.116" + wire $and$issuer_ls180.v:41269$2048_Y + attribute \src "issuer_ls180.v:41271.19-41271.102" + wire $and$issuer_ls180.v:41271$2050_Y + attribute \src "issuer_ls180.v:41272.19-41272.132" + wire $and$issuer_ls180.v:41272$2051_Y + attribute \src "issuer_ls180.v:41274.19-41274.127" + wire $and$issuer_ls180.v:41274$2053_Y + attribute \src "issuer_ls180.v:41275.19-41275.116" + wire $and$issuer_ls180.v:41275$2054_Y + attribute \src "issuer_ls180.v:41277.19-41277.102" + wire $and$issuer_ls180.v:41277$2056_Y + attribute \src "issuer_ls180.v:41278.19-41278.132" + wire $and$issuer_ls180.v:41278$2057_Y + attribute \src "issuer_ls180.v:41280.19-41280.127" + wire $and$issuer_ls180.v:41280$2059_Y + attribute \src "issuer_ls180.v:41281.19-41281.113" + wire $and$issuer_ls180.v:41281$2060_Y + attribute \src "issuer_ls180.v:41283.19-41283.102" + wire $and$issuer_ls180.v:41283$2062_Y + attribute \src "issuer_ls180.v:41284.19-41284.129" + wire $and$issuer_ls180.v:41284$2063_Y + attribute \src "issuer_ls180.v:41288.19-41288.127" + wire $and$issuer_ls180.v:41288$2067_Y + attribute \src "issuer_ls180.v:41289.19-41289.113" + wire $and$issuer_ls180.v:41289$2068_Y + attribute \src "issuer_ls180.v:41291.19-41291.102" + wire $and$issuer_ls180.v:41291$2070_Y + attribute \src "issuer_ls180.v:41292.19-41292.129" + wire $and$issuer_ls180.v:41292$2071_Y + attribute \src "issuer_ls180.v:41297.19-41297.127" + wire $and$issuer_ls180.v:41297$2076_Y + attribute \src "issuer_ls180.v:41298.19-41298.113" + wire $and$issuer_ls180.v:41298$2077_Y + attribute \src "issuer_ls180.v:41300.19-41300.102" + wire $and$issuer_ls180.v:41300$2079_Y + attribute \src "issuer_ls180.v:41301.19-41301.126" + wire $and$issuer_ls180.v:41301$2080_Y + attribute \src "issuer_ls180.v:41305.19-41305.127" + wire $and$issuer_ls180.v:41305$2084_Y + attribute \src "issuer_ls180.v:41306.19-41306.113" + wire $and$issuer_ls180.v:41306$2085_Y + attribute \src "issuer_ls180.v:41308.19-41308.102" + wire $and$issuer_ls180.v:41308$2087_Y + attribute \src "issuer_ls180.v:41309.19-41309.126" + wire $and$issuer_ls180.v:41309$2088_Y + attribute \src "issuer_ls180.v:41313.19-41313.127" + wire $and$issuer_ls180.v:41313$2092_Y + attribute \src "issuer_ls180.v:41314.19-41314.116" + wire $and$issuer_ls180.v:41314$2093_Y + attribute \src "issuer_ls180.v:41316.19-41316.102" + wire $and$issuer_ls180.v:41316$2095_Y + attribute \src "issuer_ls180.v:41317.19-41317.135" + wire $and$issuer_ls180.v:41317$2096_Y + attribute \src "issuer_ls180.v:41319.19-41319.127" + wire $and$issuer_ls180.v:41319$2098_Y + attribute \src "issuer_ls180.v:41320.19-41320.116" + wire $and$issuer_ls180.v:41320$2099_Y + attribute \src "issuer_ls180.v:41322.19-41322.102" + wire $and$issuer_ls180.v:41322$2101_Y + attribute \src "issuer_ls180.v:41323.19-41323.135" + wire $and$issuer_ls180.v:41323$2102_Y + attribute \src "issuer_ls180.v:41325.19-41325.127" + wire $and$issuer_ls180.v:41325$2104_Y + attribute \src "issuer_ls180.v:41326.19-41326.116" + wire $and$issuer_ls180.v:41326$2105_Y + attribute \src "issuer_ls180.v:41328.19-41328.102" + wire $and$issuer_ls180.v:41328$2107_Y + attribute \src "issuer_ls180.v:41329.19-41329.135" + wire $and$issuer_ls180.v:41329$2108_Y + attribute \src "issuer_ls180.v:41334.19-41334.127" + wire $and$issuer_ls180.v:41334$2113_Y + attribute \src "issuer_ls180.v:41335.19-41335.116" + wire $and$issuer_ls180.v:41335$2114_Y + attribute \src "issuer_ls180.v:41337.19-41337.102" + wire $and$issuer_ls180.v:41337$2116_Y + attribute \src "issuer_ls180.v:41338.19-41338.135" + wire $and$issuer_ls180.v:41338$2117_Y + attribute \src "issuer_ls180.v:41340.19-41340.127" + wire $and$issuer_ls180.v:41340$2119_Y + attribute \src "issuer_ls180.v:41341.19-41341.116" + wire $and$issuer_ls180.v:41341$2120_Y + attribute \src "issuer_ls180.v:41343.19-41343.102" + wire $and$issuer_ls180.v:41343$2122_Y + attribute \src "issuer_ls180.v:41344.19-41344.135" + wire $and$issuer_ls180.v:41344$2123_Y + attribute \src "issuer_ls180.v:41348.19-41348.127" + wire $and$issuer_ls180.v:41348$2127_Y + attribute \src "issuer_ls180.v:41349.19-41349.114" + wire $and$issuer_ls180.v:41349$2128_Y + attribute \src "issuer_ls180.v:41351.19-41351.102" + wire $and$issuer_ls180.v:41351$2130_Y + attribute \src "issuer_ls180.v:41352.19-41352.128" + wire $and$issuer_ls180.v:41352$2131_Y + attribute \src "issuer_ls180.v:41355.19-41355.112" + wire $and$issuer_ls180.v:41355$2134_Y + attribute \src "issuer_ls180.v:41356.19-41356.122" + wire $and$issuer_ls180.v:41356$2135_Y + attribute \src "issuer_ls180.v:41357.19-41357.127" + wire $and$issuer_ls180.v:41357$2136_Y + attribute \src "issuer_ls180.v:41358.19-41358.127" + wire $and$issuer_ls180.v:41358$2137_Y + attribute \src "issuer_ls180.v:41359.19-41359.127" + wire $and$issuer_ls180.v:41359$2138_Y + attribute \src "issuer_ls180.v:41360.19-41360.127" + wire $and$issuer_ls180.v:41360$2139_Y + attribute \src "issuer_ls180.v:41361.19-41361.127" + wire $and$issuer_ls180.v:41361$2140_Y + attribute \src "issuer_ls180.v:41362.19-41362.127" + wire $and$issuer_ls180.v:41362$2141_Y + attribute \src "issuer_ls180.v:41363.19-41363.128" + wire $and$issuer_ls180.v:41363$2142_Y + attribute \src "issuer_ls180.v:41364.19-41364.128" + wire $and$issuer_ls180.v:41364$2143_Y + attribute \src "issuer_ls180.v:41365.19-41365.128" + wire $and$issuer_ls180.v:41365$2144_Y + attribute \src "issuer_ls180.v:41366.19-41366.125" + wire $and$issuer_ls180.v:41366$2145_Y + attribute \src "issuer_ls180.v:41368.19-41368.101" + wire $and$issuer_ls180.v:41368$2147_Y + attribute \src "issuer_ls180.v:41369.19-41369.115" + wire $and$issuer_ls180.v:41369$2148_Y + attribute \src "issuer_ls180.v:41371.19-41371.120" + wire $and$issuer_ls180.v:41371$2150_Y + attribute \src "issuer_ls180.v:41372.19-41372.125" + wire $and$issuer_ls180.v:41372$2151_Y + attribute \src "issuer_ls180.v:41374.19-41374.107" + wire $and$issuer_ls180.v:41374$2153_Y + attribute \src "issuer_ls180.v:41375.19-41375.121" + wire $and$issuer_ls180.v:41375$2154_Y + attribute \src "issuer_ls180.v:41377.19-41377.121" + wire $and$issuer_ls180.v:41377$2156_Y + attribute \src "issuer_ls180.v:41378.19-41378.125" + wire $and$issuer_ls180.v:41378$2157_Y + attribute \src "issuer_ls180.v:41380.19-41380.107" + wire $and$issuer_ls180.v:41380$2159_Y + attribute \src "issuer_ls180.v:41381.19-41381.121" + wire $and$issuer_ls180.v:41381$2160_Y + attribute \src "issuer_ls180.v:40998.19-40998.115" + wire $eq$issuer_ls180.v:40998$1775_Y + attribute \src "issuer_ls180.v:41002.19-41002.130" + wire $eq$issuer_ls180.v:41002$1779_Y + attribute \src "issuer_ls180.v:41004.19-41004.115" + wire $eq$issuer_ls180.v:41004$1781_Y + attribute \src "issuer_ls180.v:41012.19-41012.115" + wire $eq$issuer_ls180.v:41012$1789_Y + attribute \src "issuer_ls180.v:41019.19-41019.115" + wire $eq$issuer_ls180.v:41019$1796_Y + attribute \src "issuer_ls180.v:41025.19-41025.115" + wire $eq$issuer_ls180.v:41025$1802_Y + attribute \src "issuer_ls180.v:41027.19-41027.130" + wire $eq$issuer_ls180.v:41027$1804_Y + attribute \src "issuer_ls180.v:41029.19-41029.115" + wire $eq$issuer_ls180.v:41029$1806_Y + attribute \src "issuer_ls180.v:41034.19-41034.115" + wire $eq$issuer_ls180.v:41034$1811_Y + attribute \src "issuer_ls180.v:41041.19-41041.115" + wire $eq$issuer_ls180.v:41041$1818_Y + attribute \src "issuer_ls180.v:41048.19-41048.115" + wire $eq$issuer_ls180.v:41048$1825_Y + attribute \src "issuer_ls180.v:41052.19-41052.130" + wire $eq$issuer_ls180.v:41052$1829_Y + attribute \src "issuer_ls180.v:41054.19-41054.115" + wire $eq$issuer_ls180.v:41054$1831_Y + attribute \src "issuer_ls180.v:41193.19-41193.115" + wire $eq$issuer_ls180.v:41193$1970_Y + attribute \src "issuer_ls180.v:41239.19-41239.130" + wire $eq$issuer_ls180.v:41239$2017_Y + attribute \src "issuer_ls180.v:41241.19-41241.115" + wire $eq$issuer_ls180.v:41241$2019_Y + attribute \src "issuer_ls180.v:41266.19-41266.115" + wire $eq$issuer_ls180.v:41266$2045_Y + attribute \src "issuer_ls180.v:40823.20-40823.95" + wire width 3 $extend$issuer_ls180.v:40823$1595_Y + attribute \src "issuer_ls180.v:40889.20-40889.95" + wire width 2 $extend$issuer_ls180.v:40889$1662_Y + attribute \src "issuer_ls180.v:40893.20-40893.95" + wire width 3 $extend$issuer_ls180.v:40893$1667_Y + attribute \src "issuer_ls180.v:40965.20-40965.95" + wire width 4 $extend$issuer_ls180.v:40965$1740_Y + attribute \src "issuer_ls180.v:40973.20-40973.104" + wire width 4 $extend$issuer_ls180.v:40973$1749_Y + attribute \src "issuer_ls180.v:41238.19-41238.93" + wire width 3 $extend$issuer_ls180.v:41238$2015_Y + attribute \src "issuer_ls180.v:41263.19-41263.93" + wire width 3 $extend$issuer_ls180.v:41263$2041_Y + attribute \src "issuer_ls180.v:40993.19-40993.103" + wire $ne$issuer_ls180.v:40993$1770_Y + attribute \src "issuer_ls180.v:40995.19-40995.103" + wire $ne$issuer_ls180.v:40995$1772_Y + attribute \src "issuer_ls180.v:40660.20-40660.106" + wire $not$issuer_ls180.v:40660$1432_Y + attribute \src "issuer_ls180.v:40666.20-40666.106" + wire $not$issuer_ls180.v:40666$1438_Y + attribute \src "issuer_ls180.v:40672.20-40672.106" + wire $not$issuer_ls180.v:40672$1444_Y + attribute \src "issuer_ls180.v:40678.20-40678.106" + wire $not$issuer_ls180.v:40678$1450_Y + attribute \src "issuer_ls180.v:40684.20-40684.106" + wire $not$issuer_ls180.v:40684$1456_Y + attribute \src "issuer_ls180.v:40690.20-40690.106" + wire $not$issuer_ls180.v:40690$1462_Y + attribute \src "issuer_ls180.v:40696.20-40696.106" + wire $not$issuer_ls180.v:40696$1468_Y + attribute \src "issuer_ls180.v:40730.20-40730.106" + wire $not$issuer_ls180.v:40730$1502_Y + attribute \src "issuer_ls180.v:40742.20-40742.106" + wire $not$issuer_ls180.v:40742$1514_Y + attribute \src "issuer_ls180.v:40750.20-40750.106" + wire $not$issuer_ls180.v:40750$1522_Y + attribute \src "issuer_ls180.v:40758.20-40758.106" + wire $not$issuer_ls180.v:40758$1530_Y + attribute \src "issuer_ls180.v:40766.20-40766.106" + wire $not$issuer_ls180.v:40766$1538_Y + attribute \src "issuer_ls180.v:40774.20-40774.106" + wire $not$issuer_ls180.v:40774$1546_Y + attribute \src "issuer_ls180.v:40782.20-40782.106" + wire $not$issuer_ls180.v:40782$1554_Y + attribute \src "issuer_ls180.v:40803.20-40803.106" + wire $not$issuer_ls180.v:40803$1575_Y + attribute \src "issuer_ls180.v:40809.20-40809.106" + wire $not$issuer_ls180.v:40809$1581_Y + attribute \src "issuer_ls180.v:40815.20-40815.106" + wire $not$issuer_ls180.v:40815$1587_Y + attribute \src "issuer_ls180.v:40830.20-40830.106" + wire $not$issuer_ls180.v:40830$1603_Y + attribute \src "issuer_ls180.v:40836.20-40836.106" + wire $not$issuer_ls180.v:40836$1609_Y + attribute \src "issuer_ls180.v:40842.20-40842.106" + wire $not$issuer_ls180.v:40842$1615_Y + attribute \src "issuer_ls180.v:40848.20-40848.106" + wire $not$issuer_ls180.v:40848$1621_Y + attribute \src "issuer_ls180.v:40864.20-40864.106" + wire $not$issuer_ls180.v:40864$1637_Y + attribute \src "issuer_ls180.v:40870.20-40870.106" + wire $not$issuer_ls180.v:40870$1643_Y + attribute \src "issuer_ls180.v:40876.20-40876.106" + wire $not$issuer_ls180.v:40876$1649_Y + attribute \src "issuer_ls180.v:40882.20-40882.106" + wire $not$issuer_ls180.v:40882$1655_Y + attribute \src "issuer_ls180.v:40901.20-40901.106" + wire $not$issuer_ls180.v:40901$1676_Y + attribute \src "issuer_ls180.v:40909.20-40909.106" + wire $not$issuer_ls180.v:40909$1684_Y + attribute \src "issuer_ls180.v:40915.20-40915.106" + wire $not$issuer_ls180.v:40915$1690_Y + attribute \src "issuer_ls180.v:40922.20-40922.106" + wire $not$issuer_ls180.v:40922$1697_Y + attribute \src "issuer_ls180.v:40929.20-40929.106" + wire $not$issuer_ls180.v:40929$1704_Y + attribute \src "issuer_ls180.v:40951.20-40951.106" + wire $not$issuer_ls180.v:40951$1726_Y + attribute \src "issuer_ls180.v:40958.20-40958.106" + wire $not$issuer_ls180.v:40958$1733_Y + attribute \src "issuer_ls180.v:40969.20-40969.106" + wire $not$issuer_ls180.v:40969$1745_Y + attribute \src "issuer_ls180.v:40978.20-40978.106" + wire $not$issuer_ls180.v:40978$1755_Y + attribute \src "issuer_ls180.v:41006.19-41006.136" + wire width 4 $not$issuer_ls180.v:41006$1783_Y + attribute \src "issuer_ls180.v:41007.19-41007.192" + wire width 6 $not$issuer_ls180.v:41007$1784_Y + attribute \src "issuer_ls180.v:41008.19-41008.138" + wire width 3 $not$issuer_ls180.v:41008$1785_Y + attribute \src "issuer_ls180.v:41009.19-41009.150" + wire width 4 $not$issuer_ls180.v:41009$1786_Y + attribute \src "issuer_ls180.v:41016.19-41016.128" + wire width 3 $not$issuer_ls180.v:41016$1793_Y + attribute \src "issuer_ls180.v:41031.19-41031.159" + wire width 6 $not$issuer_ls180.v:41031$1808_Y + attribute \src "issuer_ls180.v:41038.19-41038.128" + wire width 3 $not$issuer_ls180.v:41038$1815_Y + attribute \src "issuer_ls180.v:41045.19-41045.128" + wire width 3 $not$issuer_ls180.v:41045$1822_Y + attribute \src "issuer_ls180.v:41056.19-41056.150" + wire width 5 $not$issuer_ls180.v:41056$1833_Y + attribute \src "issuer_ls180.v:41057.19-41057.134" + wire width 3 $not$issuer_ls180.v:41057$1834_Y + attribute \src "issuer_ls180.v:41060.19-41060.106" + wire $not$issuer_ls180.v:41060$1837_Y + attribute \src "issuer_ls180.v:41066.19-41066.105" + wire $not$issuer_ls180.v:41066$1843_Y + attribute \src "issuer_ls180.v:41072.19-41072.107" + wire $not$issuer_ls180.v:41072$1849_Y + attribute \src "issuer_ls180.v:41078.19-41078.110" + wire $not$issuer_ls180.v:41078$1855_Y + attribute \src "issuer_ls180.v:41084.19-41084.106" + wire $not$issuer_ls180.v:41084$1861_Y + attribute \src "issuer_ls180.v:41090.19-41090.106" + wire $not$issuer_ls180.v:41090$1867_Y + attribute \src "issuer_ls180.v:41096.19-41096.106" + wire $not$issuer_ls180.v:41096$1873_Y + attribute \src "issuer_ls180.v:41102.19-41102.111" + wire $not$issuer_ls180.v:41102$1879_Y + attribute \src "issuer_ls180.v:41108.19-41108.107" + wire $not$issuer_ls180.v:41108$1885_Y + attribute \src "issuer_ls180.v:41123.19-41123.106" + wire $not$issuer_ls180.v:41123$1900_Y + attribute \src "issuer_ls180.v:41129.19-41129.105" + wire $not$issuer_ls180.v:41129$1906_Y + attribute \src "issuer_ls180.v:41135.19-41135.107" + wire $not$issuer_ls180.v:41135$1912_Y + attribute \src "issuer_ls180.v:41141.19-41141.110" + wire $not$issuer_ls180.v:41141$1918_Y + attribute \src "issuer_ls180.v:41147.19-41147.106" + wire $not$issuer_ls180.v:41147$1924_Y + attribute \src "issuer_ls180.v:41153.19-41153.106" + wire $not$issuer_ls180.v:41153$1930_Y + attribute \src "issuer_ls180.v:41159.19-41159.111" + wire $not$issuer_ls180.v:41159$1936_Y + attribute \src "issuer_ls180.v:41165.19-41165.107" + wire $not$issuer_ls180.v:41165$1942_Y + attribute \src "issuer_ls180.v:41179.19-41179.111" + wire $not$issuer_ls180.v:41179$1956_Y + attribute \src "issuer_ls180.v:41185.19-41185.107" + wire $not$issuer_ls180.v:41185$1962_Y + attribute \src "issuer_ls180.v:41199.19-41199.110" + wire $not$issuer_ls180.v:41199$1976_Y + attribute \src "issuer_ls180.v:41205.19-41205.114" + wire $not$issuer_ls180.v:41205$1982_Y + attribute \src "issuer_ls180.v:41211.19-41211.110" + wire $not$issuer_ls180.v:41211$1988_Y + attribute \src "issuer_ls180.v:41217.19-41217.110" + wire $not$issuer_ls180.v:41217$1994_Y + attribute \src "issuer_ls180.v:41223.19-41223.110" + wire $not$issuer_ls180.v:41223$2000_Y + attribute \src "issuer_ls180.v:41229.19-41229.115" + wire $not$issuer_ls180.v:41229$2006_Y + attribute \src "issuer_ls180.v:41245.19-41245.110" + wire $not$issuer_ls180.v:41245$2023_Y + attribute \src "issuer_ls180.v:41251.19-41251.110" + wire $not$issuer_ls180.v:41251$2029_Y + attribute \src "issuer_ls180.v:41257.19-41257.115" + wire $not$issuer_ls180.v:41257$2035_Y + attribute \src "issuer_ls180.v:41270.19-41270.110" + wire $not$issuer_ls180.v:41270$2049_Y + attribute \src "issuer_ls180.v:41276.19-41276.109" + wire $not$issuer_ls180.v:41276$2055_Y + attribute \src "issuer_ls180.v:41282.19-41282.106" + wire $not$issuer_ls180.v:41282$2061_Y + attribute \src "issuer_ls180.v:41290.19-41290.110" + wire $not$issuer_ls180.v:41290$2069_Y + attribute \src "issuer_ls180.v:41299.19-41299.106" + wire $not$issuer_ls180.v:41299$2078_Y + attribute \src "issuer_ls180.v:41307.19-41307.106" + wire $not$issuer_ls180.v:41307$2086_Y + attribute \src "issuer_ls180.v:41315.19-41315.113" + wire $not$issuer_ls180.v:41315$2094_Y + attribute \src "issuer_ls180.v:41321.19-41321.111" + wire $not$issuer_ls180.v:41321$2100_Y + attribute \src "issuer_ls180.v:41327.19-41327.110" + wire $not$issuer_ls180.v:41327$2106_Y + attribute \src "issuer_ls180.v:41336.19-41336.113" + wire $not$issuer_ls180.v:41336$2115_Y + attribute \src "issuer_ls180.v:41342.19-41342.111" + wire $not$issuer_ls180.v:41342$2121_Y + attribute \src "issuer_ls180.v:41350.19-41350.108" + wire $not$issuer_ls180.v:41350$2129_Y + attribute \src "issuer_ls180.v:41367.19-41367.99" + wire $not$issuer_ls180.v:41367$2146_Y + attribute \src "issuer_ls180.v:41373.19-41373.104" + wire $not$issuer_ls180.v:41373$2152_Y + attribute \src "issuer_ls180.v:41379.19-41379.104" + wire $not$issuer_ls180.v:41379$2158_Y + attribute \src "issuer_ls180.v:40700.20-40700.117" + wire width 64 $or$issuer_ls180.v:40700$1472_Y + attribute \src "issuer_ls180.v:40701.20-40701.123" + wire width 64 $or$issuer_ls180.v:40701$1473_Y + attribute \src "issuer_ls180.v:40702.20-40702.113" + wire width 64 $or$issuer_ls180.v:40702$1474_Y + attribute \src "issuer_ls180.v:40703.20-40703.103" + wire width 64 $or$issuer_ls180.v:40703$1475_Y + attribute \src "issuer_ls180.v:40704.20-40704.123" + wire width 64 $or$issuer_ls180.v:40704$1476_Y + attribute \src "issuer_ls180.v:40705.20-40705.122" + wire width 65 $or$issuer_ls180.v:40705$1477_Y + attribute \src "issuer_ls180.v:40706.20-40706.113" + wire width 65 $or$issuer_ls180.v:40706$1478_Y + attribute \src "issuer_ls180.v:40707.20-40707.103" + wire width 65 $or$issuer_ls180.v:40707$1479_Y + attribute \src "issuer_ls180.v:40708.20-40708.103" + wire width 65 $or$issuer_ls180.v:40708$1480_Y + attribute \src "issuer_ls180.v:40709.20-40709.109" + wire width 5 $or$issuer_ls180.v:40709$1481_Y + attribute \src "issuer_ls180.v:40710.20-40710.117" + wire width 5 $or$issuer_ls180.v:40710$1482_Y + attribute \src "issuer_ls180.v:40711.20-40711.109" + wire width 5 $or$issuer_ls180.v:40711$1483_Y + attribute \src "issuer_ls180.v:40712.20-40712.103" + wire width 5 $or$issuer_ls180.v:40712$1484_Y + attribute \src "issuer_ls180.v:40713.20-40713.117" + wire width 5 $or$issuer_ls180.v:40713$1485_Y + attribute \src "issuer_ls180.v:40714.20-40714.117" + wire width 5 $or$issuer_ls180.v:40714$1486_Y + attribute \src "issuer_ls180.v:40715.20-40715.110" + wire width 5 $or$issuer_ls180.v:40715$1487_Y + attribute \src "issuer_ls180.v:40716.20-40716.103" + wire width 5 $or$issuer_ls180.v:40716$1488_Y + attribute \src "issuer_ls180.v:40717.20-40717.103" + wire width 5 $or$issuer_ls180.v:40717$1489_Y + attribute \src "issuer_ls180.v:40718.20-40718.99" + wire $or$issuer_ls180.v:40718$1490_Y + attribute \src "issuer_ls180.v:40719.20-40719.107" + wire $or$issuer_ls180.v:40719$1491_Y + attribute \src "issuer_ls180.v:40720.20-40720.104" + wire $or$issuer_ls180.v:40720$1492_Y + attribute \src "issuer_ls180.v:40721.20-40721.103" + wire $or$issuer_ls180.v:40721$1493_Y + attribute \src "issuer_ls180.v:40722.20-40722.107" + wire $or$issuer_ls180.v:40722$1494_Y + attribute \src "issuer_ls180.v:40723.20-40723.107" + wire $or$issuer_ls180.v:40723$1495_Y + attribute \src "issuer_ls180.v:40724.20-40724.105" + wire $or$issuer_ls180.v:40724$1496_Y + attribute \src "issuer_ls180.v:40725.20-40725.103" + wire $or$issuer_ls180.v:40725$1497_Y + attribute \src "issuer_ls180.v:40726.20-40726.103" + wire $or$issuer_ls180.v:40726$1498_Y + attribute \src "issuer_ls180.v:40788.20-40788.117" + wire width 4 $or$issuer_ls180.v:40788$1560_Y + attribute \src "issuer_ls180.v:40789.20-40789.113" + wire width 4 $or$issuer_ls180.v:40789$1561_Y + attribute \src "issuer_ls180.v:40790.20-40790.123" + wire width 4 $or$issuer_ls180.v:40790$1562_Y + attribute \src "issuer_ls180.v:40791.20-40791.113" + wire width 4 $or$issuer_ls180.v:40791$1563_Y + attribute \src "issuer_ls180.v:40792.20-40792.103" + wire width 4 $or$issuer_ls180.v:40792$1564_Y + attribute \src "issuer_ls180.v:40793.20-40793.117" + wire width 16 $or$issuer_ls180.v:40793$1565_Y + attribute \src "issuer_ls180.v:40794.20-40794.110" + wire width 16 $or$issuer_ls180.v:40794$1566_Y + attribute \src "issuer_ls180.v:40795.20-40795.117" + wire width 16 $or$issuer_ls180.v:40795$1567_Y + attribute \src "issuer_ls180.v:40796.20-40796.110" + wire width 16 $or$issuer_ls180.v:40796$1568_Y + attribute \src "issuer_ls180.v:40797.20-40797.103" + wire width 16 $or$issuer_ls180.v:40797$1569_Y + attribute \src "issuer_ls180.v:40819.20-40819.117" + wire width 2 $or$issuer_ls180.v:40819$1591_Y + attribute \src "issuer_ls180.v:40820.20-40820.113" + wire width 2 $or$issuer_ls180.v:40820$1592_Y + attribute \src "issuer_ls180.v:40821.20-40821.117" + wire width 2 $or$issuer_ls180.v:40821$1593_Y + attribute \src "issuer_ls180.v:40822.20-40822.110" + wire width 2 $or$issuer_ls180.v:40822$1594_Y + attribute \src "issuer_ls180.v:40852.20-40852.112" + wire width 2 $or$issuer_ls180.v:40852$1625_Y + attribute \src "issuer_ls180.v:40853.20-40853.123" + wire width 2 $or$issuer_ls180.v:40853$1626_Y + attribute \src "issuer_ls180.v:40854.20-40854.103" + wire width 2 $or$issuer_ls180.v:40854$1627_Y + attribute \src "issuer_ls180.v:40855.20-40855.117" + wire width 3 $or$issuer_ls180.v:40855$1628_Y + attribute \src "issuer_ls180.v:40856.20-40856.117" + wire width 3 $or$issuer_ls180.v:40856$1629_Y + attribute \src "issuer_ls180.v:40857.20-40857.103" + wire width 3 $or$issuer_ls180.v:40857$1630_Y + attribute \src "issuer_ls180.v:40886.20-40886.123" + wire $or$issuer_ls180.v:40886$1659_Y + attribute \src "issuer_ls180.v:40887.20-40887.123" + wire $or$issuer_ls180.v:40887$1660_Y + attribute \src "issuer_ls180.v:40888.20-40888.103" + wire $or$issuer_ls180.v:40888$1661_Y + attribute \src "issuer_ls180.v:40890.20-40890.117" + wire $or$issuer_ls180.v:40890$1664_Y + attribute \src "issuer_ls180.v:40891.20-40891.117" + wire $or$issuer_ls180.v:40891$1665_Y + attribute \src "issuer_ls180.v:40892.20-40892.103" + wire $or$issuer_ls180.v:40892$1666_Y + attribute \src "issuer_ls180.v:40933.20-40933.123" + wire width 64 $or$issuer_ls180.v:40933$1708_Y + attribute \src "issuer_ls180.v:40934.20-40934.123" + wire width 64 $or$issuer_ls180.v:40934$1709_Y + attribute \src "issuer_ls180.v:40935.20-40935.113" + wire width 64 $or$issuer_ls180.v:40935$1710_Y + attribute \src "issuer_ls180.v:40936.20-40936.103" + wire width 64 $or$issuer_ls180.v:40936$1711_Y + attribute \src "issuer_ls180.v:40937.20-40937.117" + wire width 3 $or$issuer_ls180.v:40937$1712_Y + attribute \src "issuer_ls180.v:40939.20-40939.117" + wire width 3 $or$issuer_ls180.v:40939$1714_Y + attribute \src "issuer_ls180.v:40940.20-40940.110" + wire width 3 $or$issuer_ls180.v:40940$1715_Y + attribute \src "issuer_ls180.v:40941.20-40941.103" + wire width 3 $or$issuer_ls180.v:40941$1716_Y + attribute \src "issuer_ls180.v:40942.20-40942.107" + wire $or$issuer_ls180.v:40942$1717_Y + attribute \src "issuer_ls180.v:40943.20-40943.107" + wire $or$issuer_ls180.v:40943$1718_Y + attribute \src "issuer_ls180.v:40945.20-40945.105" + wire $or$issuer_ls180.v:40945$1720_Y + attribute \src "issuer_ls180.v:40946.20-40946.103" + wire $or$issuer_ls180.v:40946$1721_Y + attribute \src "issuer_ls180.v:40963.20-40963.123" + wire width 64 $or$issuer_ls180.v:40963$1738_Y + attribute \src "issuer_ls180.v:40964.20-40964.117" + wire $or$issuer_ls180.v:40964$1739_Y + attribute \src "issuer_ls180.v:40999.19-40999.115" + wire $or$issuer_ls180.v:40999$1776_Y + attribute \src "issuer_ls180.v:41001.19-41001.115" + wire $or$issuer_ls180.v:41001$1778_Y + attribute \src "issuer_ls180.v:41005.19-41005.115" + wire $or$issuer_ls180.v:41005$1782_Y + attribute \src "issuer_ls180.v:41013.19-41013.115" + wire $or$issuer_ls180.v:41013$1790_Y + attribute \src "issuer_ls180.v:41015.19-41015.115" + wire $or$issuer_ls180.v:41015$1792_Y + attribute \src "issuer_ls180.v:41020.19-41020.115" + wire $or$issuer_ls180.v:41020$1797_Y + attribute \src "issuer_ls180.v:41022.19-41022.115" + wire $or$issuer_ls180.v:41022$1799_Y + attribute \src "issuer_ls180.v:41026.19-41026.115" + wire $or$issuer_ls180.v:41026$1803_Y + attribute \src "issuer_ls180.v:41030.19-41030.115" + wire $or$issuer_ls180.v:41030$1807_Y + attribute \src "issuer_ls180.v:41035.19-41035.115" + wire $or$issuer_ls180.v:41035$1812_Y + attribute \src "issuer_ls180.v:41037.19-41037.115" + wire $or$issuer_ls180.v:41037$1814_Y + attribute \src "issuer_ls180.v:41042.19-41042.115" + wire $or$issuer_ls180.v:41042$1819_Y + attribute \src "issuer_ls180.v:41044.19-41044.115" + wire $or$issuer_ls180.v:41044$1821_Y + attribute \src "issuer_ls180.v:41049.19-41049.115" + wire $or$issuer_ls180.v:41049$1826_Y + attribute \src "issuer_ls180.v:41051.19-41051.115" + wire $or$issuer_ls180.v:41051$1828_Y + attribute \src "issuer_ls180.v:41055.19-41055.115" + wire $or$issuer_ls180.v:41055$1832_Y + attribute \src "issuer_ls180.v:41112.19-41112.130" + wire width 5 $or$issuer_ls180.v:41112$1889_Y + attribute \src "issuer_ls180.v:41113.19-41113.136" + wire width 5 $or$issuer_ls180.v:41113$1890_Y + attribute \src "issuer_ls180.v:41114.19-41114.100" + wire width 5 $or$issuer_ls180.v:41114$1891_Y + attribute \src "issuer_ls180.v:41115.19-41115.131" + wire width 5 $or$issuer_ls180.v:41115$1892_Y + attribute \src "issuer_ls180.v:41116.19-41116.137" + wire width 5 $or$issuer_ls180.v:41116$1893_Y + attribute \src "issuer_ls180.v:41117.19-41117.115" + wire width 5 $or$issuer_ls180.v:41117$1894_Y + attribute \src "issuer_ls180.v:41118.19-41118.100" + wire width 5 $or$issuer_ls180.v:41118$1895_Y + attribute \src "issuer_ls180.v:41119.19-41119.100" + wire width 5 $or$issuer_ls180.v:41119$1896_Y + attribute \src "issuer_ls180.v:41169.19-41169.130" + wire width 5 $or$issuer_ls180.v:41169$1946_Y + attribute \src "issuer_ls180.v:41170.19-41170.136" + wire width 5 $or$issuer_ls180.v:41170$1947_Y + attribute \src "issuer_ls180.v:41171.19-41171.100" + wire width 5 $or$issuer_ls180.v:41171$1948_Y + attribute \src "issuer_ls180.v:41172.19-41172.131" + wire width 5 $or$issuer_ls180.v:41172$1949_Y + attribute \src "issuer_ls180.v:41173.19-41173.137" + wire width 5 $or$issuer_ls180.v:41173$1950_Y + attribute \src "issuer_ls180.v:41174.19-41174.100" + wire width 5 $or$issuer_ls180.v:41174$1951_Y + attribute \src "issuer_ls180.v:41175.19-41175.100" + wire width 5 $or$issuer_ls180.v:41175$1952_Y + attribute \src "issuer_ls180.v:41189.19-41189.137" + wire width 5 $or$issuer_ls180.v:41189$1966_Y + attribute \src "issuer_ls180.v:41194.19-41194.115" + wire $or$issuer_ls180.v:41194$1971_Y + attribute \src "issuer_ls180.v:41196.19-41196.115" + wire $or$issuer_ls180.v:41196$1973_Y + attribute \src "issuer_ls180.v:41233.19-41233.143" + wire $or$issuer_ls180.v:41233$2010_Y + attribute \src "issuer_ls180.v:41234.19-41234.119" + wire $or$issuer_ls180.v:41234$2011_Y + attribute \src "issuer_ls180.v:41235.19-41235.144" + wire $or$issuer_ls180.v:41235$2012_Y + attribute \src "issuer_ls180.v:41236.19-41236.119" + wire $or$issuer_ls180.v:41236$2013_Y + attribute \src "issuer_ls180.v:41237.19-41237.100" + wire $or$issuer_ls180.v:41237$2014_Y + attribute \src "issuer_ls180.v:41242.19-41242.115" + wire $or$issuer_ls180.v:41242$2020_Y + attribute \src "issuer_ls180.v:41261.19-41261.144" + wire width 2 $or$issuer_ls180.v:41261$2039_Y + attribute \src "issuer_ls180.v:41262.19-41262.119" + wire width 2 $or$issuer_ls180.v:41262$2040_Y + attribute \src "issuer_ls180.v:41267.19-41267.115" + wire $or$issuer_ls180.v:41267$2046_Y + attribute \src "issuer_ls180.v:41296.19-41296.135" + wire width 16 $or$issuer_ls180.v:41296$2075_Y + attribute \src "issuer_ls180.v:41331.19-41331.140" + wire width 3 $or$issuer_ls180.v:41331$2110_Y + attribute \src "issuer_ls180.v:41332.19-41332.122" + wire width 3 $or$issuer_ls180.v:41332$2111_Y + attribute \src "issuer_ls180.v:41346.19-41346.143" + wire width 3 $or$issuer_ls180.v:41346$2125_Y + attribute \src "issuer_ls180.v:40823.20-40823.95" + wire width 3 $pos$issuer_ls180.v:40823$1596_Y + attribute \src "issuer_ls180.v:40889.20-40889.95" + wire width 2 $pos$issuer_ls180.v:40889$1663_Y + attribute \src "issuer_ls180.v:40893.20-40893.95" + wire width 3 $pos$issuer_ls180.v:40893$1668_Y + attribute \src "issuer_ls180.v:40965.20-40965.95" + wire width 4 $pos$issuer_ls180.v:40965$1741_Y + attribute \src "issuer_ls180.v:40973.20-40973.104" + wire width 4 $pos$issuer_ls180.v:40973$1750_Y + attribute \src "issuer_ls180.v:41238.19-41238.93" + wire width 3 $pos$issuer_ls180.v:41238$2016_Y + attribute \src "issuer_ls180.v:41263.19-41263.93" + wire width 3 $pos$issuer_ls180.v:41263$2042_Y + attribute \src "issuer_ls180.v:40907.19-40907.95" + wire $reduce_or$issuer_ls180.v:40907$1682_Y + attribute \src "issuer_ls180.v:40924.19-40924.95" + wire $reduce_or$issuer_ls180.v:40924$1699_Y + attribute \src "issuer_ls180.v:40944.19-40944.95" + wire $reduce_or$issuer_ls180.v:40944$1719_Y + attribute \src "issuer_ls180.v:40962.19-40962.95" + wire $reduce_or$issuer_ls180.v:40962$1737_Y + attribute \src "issuer_ls180.v:40980.19-40980.95" + wire $reduce_or$issuer_ls180.v:40980$1757_Y + attribute \src "issuer_ls180.v:40984.19-40984.95" + wire $reduce_or$issuer_ls180.v:40984$1761_Y + attribute \src "issuer_ls180.v:40986.19-40986.95" + wire $reduce_or$issuer_ls180.v:40986$1763_Y + attribute \src "issuer_ls180.v:40988.19-40988.95" + wire $reduce_or$issuer_ls180.v:40988$1765_Y + attribute \src "issuer_ls180.v:40990.19-40990.95" + wire $reduce_or$issuer_ls180.v:40990$1767_Y + attribute \src "issuer_ls180.v:40992.19-40992.95" + wire $reduce_or$issuer_ls180.v:40992$1769_Y + attribute \src "issuer_ls180.v:41120.19-41120.264" + wire $reduce_or$issuer_ls180.v:41120$1897_Y + attribute \src "issuer_ls180.v:41176.19-41176.246" + wire $reduce_or$issuer_ls180.v:41176$1953_Y + attribute \src "issuer_ls180.v:41190.19-41190.134" + wire $reduce_or$issuer_ls180.v:41190$1967_Y + attribute \src "issuer_ls180.v:41333.19-41333.162" + wire $reduce_or$issuer_ls180.v:41333$2112_Y + attribute \src "issuer_ls180.v:41347.19-41347.140" + wire $reduce_or$issuer_ls180.v:41347$2126_Y + attribute \src "issuer_ls180.v:41354.19-41354.108" + wire $reduce_or$issuer_ls180.v:41354$2133_Y + attribute \src "issuer_ls180.v:40746.20-40746.118" + wire width 16 $sshl$issuer_ls180.v:40746$1518_Y + attribute \src "issuer_ls180.v:40754.20-40754.118" + wire width 16 $sshl$issuer_ls180.v:40754$1526_Y + attribute \src "issuer_ls180.v:40762.20-40762.118" + wire width 16 $sshl$issuer_ls180.v:40762$1534_Y + attribute \src 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"/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 \cr_data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 32 \cr_full_rd__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 8 \cr_full_rd__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 32 \cr_full_wr__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 8 \cr_full_wr__wen + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 \cr_src1__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 8 \cr_src1__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 \cr_src2__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 8 \cr_src2__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 \cr_src3__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 8 \cr_src3__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 8 \cr_wen + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire input 4 \cu_ad__go_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire output 5 \cu_ad__rel_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire input 6 \cu_st__go_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire output 3 \cu_st__rel_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 64 input 10 \data_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" + wire input 75 \dbus__ack + attribute \src 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\enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 \dec_BRANCH_BRANCH_BRANCH__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \dec_BRANCH_BRANCH_BRANCH__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \dec_BRANCH_BRANCH_BRANCH__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \dec_BRANCH_BRANCH_BRANCH__insn + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \dec_BRANCH_BRANCH_BRANCH__insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \dec_BRANCH_BRANCH_BRANCH__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \dec_BRANCH_BRANCH_BRANCH__lk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + wire \dec_BRANCH_bigendian + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:442" + wire width 32 \dec_BRANCH_raw_opcode_in + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 \dec_CR_CR_CR__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \dec_CR_CR_CR__insn + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \dec_CR_CR_CR__insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + wire \dec_CR_bigendian + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:442" + wire width 32 \dec_CR_raw_opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \dec_DIV_DIV_DIV__data_len + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 \dec_DIV_DIV_DIV__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \dec_DIV_DIV_DIV__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \dec_DIV_DIV_DIV__imm_data__ok + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \dec_DIV_DIV_DIV__input_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \dec_DIV_DIV_DIV__insn + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \dec_DIV_DIV_DIV__insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \dec_DIV_DIV_DIV__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \dec_DIV_DIV_DIV__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \dec_DIV_DIV_DIV__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \dec_DIV_DIV_DIV__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \dec_DIV_DIV_DIV__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \dec_DIV_DIV_DIV__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \dec_DIV_DIV_DIV__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \dec_DIV_DIV_DIV__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \dec_DIV_DIV_DIV__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \dec_DIV_DIV_DIV__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \dec_DIV_DIV_DIV__zero_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + wire \dec_DIV_bigendian + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:442" + wire width 32 \dec_DIV_raw_opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \dec_LDST_LDST_LDST__byte_reverse + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \dec_LDST_LDST_LDST__data_len + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 \dec_LDST_LDST_LDST__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \dec_LDST_LDST_LDST__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \dec_LDST_LDST_LDST__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \dec_LDST_LDST_LDST__insn + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \dec_LDST_LDST_LDST__insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \dec_LDST_LDST_LDST__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \dec_LDST_LDST_LDST__is_signed + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \dec_LDST_LDST_LDST__ldst_mode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \dec_LDST_LDST_LDST__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \dec_LDST_LDST_LDST__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \dec_LDST_LDST_LDST__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \dec_LDST_LDST_LDST__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \dec_LDST_LDST_LDST__sign_extend + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \dec_LDST_LDST_LDST__zero_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + wire \dec_LDST_bigendian + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:442" + wire width 32 \dec_LDST_raw_opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \dec_LOGICAL_LOGICAL_LOGICAL__data_len + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 \dec_LOGICAL_LOGICAL_LOGICAL__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \dec_LOGICAL_LOGICAL_LOGICAL__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \dec_LOGICAL_LOGICAL_LOGICAL__imm_data__ok + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \dec_LOGICAL_LOGICAL_LOGICAL__input_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \dec_LOGICAL_LOGICAL_LOGICAL__insn + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \dec_LOGICAL_LOGICAL_LOGICAL__insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \dec_LOGICAL_LOGICAL_LOGICAL__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \dec_LOGICAL_LOGICAL_LOGICAL__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \dec_LOGICAL_LOGICAL_LOGICAL__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \dec_LOGICAL_LOGICAL_LOGICAL__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \dec_LOGICAL_LOGICAL_LOGICAL__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \dec_LOGICAL_LOGICAL_LOGICAL__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \dec_LOGICAL_LOGICAL_LOGICAL__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \dec_LOGICAL_LOGICAL_LOGICAL__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \dec_LOGICAL_LOGICAL_LOGICAL__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \dec_LOGICAL_LOGICAL_LOGICAL__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \dec_LOGICAL_LOGICAL_LOGICAL__zero_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + wire \dec_LOGICAL_bigendian + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:442" + wire width 32 \dec_LOGICAL_raw_opcode_in + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 \dec_MUL_MUL_MUL__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \dec_MUL_MUL_MUL__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \dec_MUL_MUL_MUL__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \dec_MUL_MUL_MUL__insn + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 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attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute 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"/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + wire \dec_MUL_bigendian + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:442" + wire width 32 \dec_MUL_raw_opcode_in + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 \dec_SHIFT_ROT_SHIFT_ROT_SHIFT_ROT__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \dec_SHIFT_ROT_SHIFT_ROT_SHIFT_ROT__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \dec_SHIFT_ROT_SHIFT_ROT_SHIFT_ROT__imm_data__ok + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \dec_SHIFT_ROT_SHIFT_ROT_SHIFT_ROT__input_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \dec_SHIFT_ROT_SHIFT_ROT_SHIFT_ROT__input_cr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \dec_SHIFT_ROT_SHIFT_ROT_SHIFT_ROT__insn + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute 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"OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \dec_SHIFT_ROT_SHIFT_ROT_SHIFT_ROT__insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \dec_SHIFT_ROT_SHIFT_ROT_SHIFT_ROT__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \dec_SHIFT_ROT_SHIFT_ROT_SHIFT_ROT__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \dec_SHIFT_ROT_SHIFT_ROT_SHIFT_ROT__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \dec_SHIFT_ROT_SHIFT_ROT_SHIFT_ROT__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \dec_SHIFT_ROT_SHIFT_ROT_SHIFT_ROT__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \dec_SHIFT_ROT_SHIFT_ROT_SHIFT_ROT__output_cr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \dec_SHIFT_ROT_SHIFT_ROT_SHIFT_ROT__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \dec_SHIFT_ROT_SHIFT_ROT_SHIFT_ROT__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \dec_SHIFT_ROT_SHIFT_ROT_SHIFT_ROT__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + wire \dec_SHIFT_ROT_bigendian + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:442" + wire width 32 \dec_SHIFT_ROT_raw_opcode_in + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 \dec_SPR_SPR_SPR__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \dec_SPR_SPR_SPR__insn + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \dec_SPR_SPR_SPR__insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \dec_SPR_SPR_SPR__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + wire \dec_SPR_bigendian + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:442" + wire width 32 \dec_SPR_raw_opcode_in + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 5 input 61 \dmi__addr + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 64 output 63 \dmi__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire input 62 \dmi__ren + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:266" + wire \dp_CR_cr_a_branch0_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:266" + wire \dp_CR_cr_a_branch0_1$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:266" + wire \dp_CR_cr_a_cr0_0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:266" + wire \dp_CR_cr_a_cr0_0$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:266" + wire \dp_CR_cr_b_cr0_0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:266" + wire \dp_CR_cr_b_cr0_0$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:266" + wire \dp_CR_cr_c_cr0_0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:266" + wire \dp_CR_cr_c_cr0_0$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:266" + wire \dp_CR_full_cr_cr0_0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:266" + wire \dp_CR_full_cr_cr0_0$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:266" + wire \dp_FAST_fast1_branch0_0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:266" + wire \dp_FAST_fast1_branch0_0$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:266" + wire \dp_FAST_fast1_spr0_2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:266" + wire \dp_FAST_fast1_spr0_2$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:266" + wire \dp_FAST_fast1_trap0_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:266" + wire \dp_FAST_fast1_trap0_1$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:266" + wire \dp_FAST_fast2_branch0_0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:266" + wire \dp_FAST_fast2_branch0_0$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:266" + wire \dp_FAST_fast2_trap0_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:266" + wire \dp_FAST_fast2_trap0_1$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:266" + wire \dp_INT_ra_alu0_0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:266" + wire \dp_INT_ra_alu0_0$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:266" + wire \dp_INT_ra_cr0_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:266" + wire \dp_INT_ra_cr0_1$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:266" + wire \dp_INT_ra_div0_5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:266" + wire \dp_INT_ra_div0_5$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:266" + wire \dp_INT_ra_ldst0_8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:266" + wire \dp_INT_ra_ldst0_8$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:266" + wire \dp_INT_ra_logical0_3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:266" + wire \dp_INT_ra_logical0_3$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:266" + wire \dp_INT_ra_mul0_6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:266" + wire \dp_INT_ra_mul0_6$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:266" + wire \dp_INT_ra_shiftrot0_7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:266" + wire \dp_INT_ra_shiftrot0_7$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:266" + wire \dp_INT_ra_spr0_4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:266" + wire \dp_INT_ra_spr0_4$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:266" + wire \dp_INT_ra_trap0_2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:266" + wire \dp_INT_ra_trap0_2$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:266" + wire \dp_INT_rb_alu0_0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:266" + wire \dp_INT_rb_alu0_0$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:266" + wire \dp_INT_rb_cr0_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:266" + wire \dp_INT_rb_cr0_1$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:266" + wire \dp_INT_rb_div0_4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:266" + wire \dp_INT_rb_div0_4$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:266" + wire \dp_INT_rb_ldst0_7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:266" + wire \dp_INT_rb_ldst0_7$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:266" + wire \dp_INT_rb_logical0_3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:266" + wire \dp_INT_rb_logical0_3$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:266" + wire \dp_INT_rb_mul0_5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:266" + wire \dp_INT_rb_mul0_5$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:266" + wire \dp_INT_rb_shiftrot0_6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:266" + wire \dp_INT_rb_shiftrot0_6$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:266" + wire \dp_INT_rb_trap0_2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:266" + wire \dp_INT_rb_trap0_2$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:266" + wire \dp_INT_rc_ldst0_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:266" + wire \dp_INT_rc_ldst0_1$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:266" + wire \dp_INT_rc_shiftrot0_0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:266" + wire \dp_INT_rc_shiftrot0_0$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:266" + wire \dp_SPR_spr1_spr0_0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:266" + wire \dp_SPR_spr1_spr0_0$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:266" + wire \dp_XER_xer_ca_alu0_0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:266" + wire \dp_XER_xer_ca_alu0_0$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:266" + wire \dp_XER_xer_ca_shiftrot0_2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:266" + wire \dp_XER_xer_ca_shiftrot0_2$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:266" + wire \dp_XER_xer_ca_spr0_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:266" + wire \dp_XER_xer_ca_spr0_1$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:266" + wire \dp_XER_xer_ov_spr0_0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:266" + wire \dp_XER_xer_ov_spr0_0$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:266" + wire \dp_XER_xer_so_alu0_0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:266" + wire \dp_XER_xer_so_alu0_0$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:266" + wire \dp_XER_xer_so_div0_3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:266" + wire \dp_XER_xer_so_div0_3$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:266" + wire \dp_XER_xer_so_logical0_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:266" + wire \dp_XER_xer_so_logical0_1$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:266" + wire \dp_XER_xer_so_mul0_4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:266" + wire \dp_XER_xer_so_mul0_4$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:266" + wire \dp_XER_xer_so_shiftrot0_5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:266" + wire \dp_XER_xer_so_shiftrot0_5$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:266" + wire \dp_XER_xer_so_spr0_2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:266" + wire \dp_XER_xer_so_spr0_2$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \ea_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:171" + wire \en_alu0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:171" + wire \en_branch0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:171" + wire \en_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:171" + wire \en_div0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:171" + wire \en_ldst0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:171" + wire \en_logical0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:171" + wire \en_mul0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:171" + wire \en_shiftrot0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:171" + wire \en_spr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:171" + wire \en_trap0 + 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\fus_oper_i_alu_div0__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \fus_oper_i_alu_div0__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \fus_oper_i_alu_div0__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \fus_oper_i_alu_div0__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \fus_oper_i_alu_div0__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \fus_oper_i_alu_div0__zero_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \fus_oper_i_alu_logical0__data_len + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 \fus_oper_i_alu_logical0__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \fus_oper_i_alu_logical0__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \fus_oper_i_alu_logical0__imm_data__ok + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \fus_oper_i_alu_logical0__input_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \fus_oper_i_alu_logical0__insn + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \fus_oper_i_alu_logical0__insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \fus_oper_i_alu_logical0__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \fus_oper_i_alu_logical0__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \fus_oper_i_alu_logical0__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \fus_oper_i_alu_logical0__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \fus_oper_i_alu_logical0__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \fus_oper_i_alu_logical0__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \fus_oper_i_alu_logical0__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \fus_oper_i_alu_logical0__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \fus_oper_i_alu_logical0__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \fus_oper_i_alu_logical0__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \fus_oper_i_alu_logical0__zero_a + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 \fus_oper_i_alu_mul0__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \fus_oper_i_alu_mul0__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \fus_oper_i_alu_mul0__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \fus_oper_i_alu_mul0__insn + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \fus_oper_i_alu_mul0__insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \fus_oper_i_alu_mul0__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \fus_oper_i_alu_mul0__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \fus_oper_i_alu_mul0__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \fus_oper_i_alu_mul0__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \fus_oper_i_alu_mul0__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \fus_oper_i_alu_mul0__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \fus_oper_i_alu_mul0__write_cr0 + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 \fus_oper_i_alu_shift_rot0__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \fus_oper_i_alu_shift_rot0__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \fus_oper_i_alu_shift_rot0__imm_data__ok + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \fus_oper_i_alu_shift_rot0__input_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \fus_oper_i_alu_shift_rot0__input_cr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \fus_oper_i_alu_shift_rot0__insn + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \fus_oper_i_alu_shift_rot0__insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \fus_oper_i_alu_shift_rot0__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \fus_oper_i_alu_shift_rot0__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \fus_oper_i_alu_shift_rot0__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \fus_oper_i_alu_shift_rot0__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \fus_oper_i_alu_shift_rot0__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \fus_oper_i_alu_shift_rot0__output_cr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \fus_oper_i_alu_shift_rot0__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \fus_oper_i_alu_shift_rot0__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \fus_oper_i_alu_shift_rot0__write_cr0 + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 \fus_oper_i_alu_spr0__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \fus_oper_i_alu_spr0__insn + attribute \enum_base_type "MicrOp" + attribute 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attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \fus_oper_i_alu_spr0__insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \fus_oper_i_alu_spr0__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \fus_oper_i_alu_trap0__cia + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute 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attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute 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\fus_oper_i_alu_trap0__trapaddr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \fus_oper_i_alu_trap0__traptype + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \fus_oper_i_ldst_ldst0__byte_reverse + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \fus_oper_i_ldst_ldst0__data_len + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 \fus_oper_i_ldst_ldst0__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \fus_oper_i_ldst_ldst0__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \fus_oper_i_ldst_ldst0__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \fus_oper_i_ldst_ldst0__insn + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute 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+ wire \fus_oper_i_ldst_ldst0__is_signed + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \fus_oper_i_ldst_ldst0__ldst_mode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \fus_oper_i_ldst_ldst0__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \fus_oper_i_ldst_ldst0__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \fus_oper_i_ldst_ldst0__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \fus_oper_i_ldst_ldst0__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \fus_oper_i_ldst_ldst0__sign_extend + attribute \src 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\wrflag_cr0_o_0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:390" + wire \wrflag_div0_cr_a_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:390" + wire \wrflag_div0_o_0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:390" + wire \wrflag_div0_xer_ov_2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:390" + wire \wrflag_div0_xer_so_3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:390" + wire \wrflag_ldst0_o_0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:390" + wire \wrflag_ldst0_o_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:390" + wire \wrflag_logical0_cr_a_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:390" + wire \wrflag_logical0_o_0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:390" + wire \wrflag_mul0_cr_a_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:390" + wire \wrflag_mul0_o_0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:390" + wire \wrflag_mul0_xer_ov_2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:390" + wire \wrflag_mul0_xer_so_3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:390" + wire \wrflag_shiftrot0_cr_a_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:390" + wire \wrflag_shiftrot0_o_0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:390" + wire \wrflag_shiftrot0_xer_ca_2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:390" + wire \wrflag_spr0_fast1_2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:390" + wire \wrflag_spr0_o_0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:390" + wire \wrflag_spr0_spr1_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:390" + wire \wrflag_spr0_xer_ca_5 + attribute \src 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\wrpick_CR_cr_a_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" + wire \wrpick_CR_full_cr_en_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" + wire \wrpick_CR_full_cr_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" + wire \wrpick_CR_full_cr_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" + wire \wrpick_FAST_fast1_en_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" + wire width 5 \wrpick_FAST_fast1_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" + wire width 5 \wrpick_FAST_fast1_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" + wire \wrpick_INT_o_en_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" + wire width 10 \wrpick_INT_o_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" + wire width 10 \wrpick_INT_o_o + attribute \src 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$ternary$issuer_ls180.v:40787$1559 + parameter \WIDTH 16 + connect \A 16'0000000000000000 + connect \B \$1336 + connect \S \wp$1330 + connect \Y $ternary$issuer_ls180.v:40787$1559_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408" + cell $mux $ternary$issuer_ls180.v:40806$1578 + parameter \WIDTH 2 + connect \A 2'00 + connect \B 2'10 + connect \S \wp$1377 + connect \Y $ternary$issuer_ls180.v:40806$1578_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408" + cell $mux $ternary$issuer_ls180.v:40812$1584 + parameter \WIDTH 2 + connect \A 2'00 + connect \B 2'10 + connect \S \wp$1393 + connect \Y $ternary$issuer_ls180.v:40812$1584_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408" + cell $mux $ternary$issuer_ls180.v:40818$1590 + parameter \WIDTH 2 + connect \A 2'00 + connect \B 2'10 + connect \S \wp$1409 + connect \Y $ternary$issuer_ls180.v:40818$1590_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408" + cell $mux $ternary$issuer_ls180.v:40833$1606 + parameter \WIDTH 3 + connect \A 3'000 + connect \B 3'100 + connect \S \wp$1443 + connect \Y $ternary$issuer_ls180.v:40833$1606_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408" + cell $mux $ternary$issuer_ls180.v:40839$1612 + parameter \WIDTH 3 + connect \A 3'000 + connect \B 3'100 + connect \S \wp$1459 + connect \Y $ternary$issuer_ls180.v:40839$1612_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408" + cell $mux $ternary$issuer_ls180.v:40845$1618 + parameter \WIDTH 3 + connect \A 3'000 + connect \B 3'100 + connect \S \wp$1475 + connect \Y $ternary$issuer_ls180.v:40845$1618_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408" + cell $mux $ternary$issuer_ls180.v:40851$1624 + parameter \WIDTH 3 + connect \A 3'000 + connect \B 3'100 + connect \S \wp$1491 + connect \Y $ternary$issuer_ls180.v:40851$1624_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408" + cell $mux $ternary$issuer_ls180.v:40867$1640 + parameter \WIDTH 1 + connect \A 1'0 + connect \B 1'1 + connect \S \wp$1527 + connect \Y $ternary$issuer_ls180.v:40867$1640_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408" + cell $mux $ternary$issuer_ls180.v:40873$1646 + parameter \WIDTH 1 + connect \A 1'0 + connect \B 1'1 + connect \S \wp$1543 + connect \Y $ternary$issuer_ls180.v:40873$1646_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408" + cell $mux $ternary$issuer_ls180.v:40879$1652 + parameter \WIDTH 1 + connect \A 1'0 + connect \B 1'1 + connect \S \wp$1559 + connect \Y $ternary$issuer_ls180.v:40879$1652_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408" + cell $mux $ternary$issuer_ls180.v:40885$1658 + parameter \WIDTH 1 + connect \A 1'0 + connect \B 1'1 + connect \S \wp$1575 + connect \Y $ternary$issuer_ls180.v:40885$1658_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408" + cell $mux $ternary$issuer_ls180.v:40905$1680 + parameter \WIDTH 3 + connect \A 3'000 + connect \B \core_fasto1 + connect \S \wp$1620 + connect \Y $ternary$issuer_ls180.v:40905$1680_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408" + cell $mux $ternary$issuer_ls180.v:40912$1687 + parameter \WIDTH 3 + connect \A 3'000 + connect \B \core_fasto1 + connect \S \wp$1636 + connect \Y $ternary$issuer_ls180.v:40912$1687_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408" + cell $mux $ternary$issuer_ls180.v:40918$1693 + parameter \WIDTH 3 + connect \A 3'000 + connect \B \core_fasto1 + connect \S \wp$1652 + connect \Y $ternary$issuer_ls180.v:40918$1693_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408" + cell $mux $ternary$issuer_ls180.v:40926$1701 + parameter \WIDTH 3 + connect \A 3'000 + connect \B \core_fasto2 + connect \S \wp$1668 + connect \Y $ternary$issuer_ls180.v:40926$1701_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408" + cell $mux $ternary$issuer_ls180.v:40932$1707 + parameter \WIDTH 3 + connect \A 3'000 + connect \B \core_fasto2 + connect \S \wp$1684 + connect \Y $ternary$issuer_ls180.v:40932$1707_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408" + cell $mux $ternary$issuer_ls180.v:40954$1729 + parameter \WIDTH 1 + connect \A 1'0 + connect \B 1'1 + connect \S \wp$1728 + connect \Y $ternary$issuer_ls180.v:40954$1729_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408" + cell $mux $ternary$issuer_ls180.v:40961$1736 + parameter \WIDTH 1 + connect \A 1'0 + connect \B 1'1 + connect \S \wp$1744 + connect \Y $ternary$issuer_ls180.v:40961$1736_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408" + cell $mux $ternary$issuer_ls180.v:40972$1748 + parameter \WIDTH 2 + connect \A 2'00 + connect \B 2'10 + connect \S \wp$1768 + connect \Y $ternary$issuer_ls180.v:40972$1748_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408" + cell $mux $ternary$issuer_ls180.v:40982$1759 + parameter \WIDTH 10 + connect \A 10'0000000000 + connect \B \core_spro + connect \S \wp$1788 + connect \Y $ternary$issuer_ls180.v:40982$1759_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" + cell $mux $ternary$issuer_ls180.v:41063$1840 + parameter \WIDTH 5 + connect \A 5'00000 + connect \B \core_reg1 + connect \S \rp_INT_ra_alu0_0 + connect \Y $ternary$issuer_ls180.v:41063$1840_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" + cell $mux $ternary$issuer_ls180.v:41069$1846 + parameter \WIDTH 5 + connect \A 5'00000 + connect \B \core_reg1 + connect \S \rp_INT_ra_cr0_1 + connect \Y $ternary$issuer_ls180.v:41069$1846_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" + cell $mux $ternary$issuer_ls180.v:41075$1852 + parameter \WIDTH 5 + connect \A 5'00000 + connect \B \core_reg1 + connect \S \rp_INT_ra_trap0_2 + connect \Y $ternary$issuer_ls180.v:41075$1852_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" + cell $mux $ternary$issuer_ls180.v:41081$1858 + parameter \WIDTH 5 + connect \A 5'00000 + connect \B \core_reg1 + connect \S \rp_INT_ra_logical0_3 + connect \Y $ternary$issuer_ls180.v:41081$1858_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" + cell $mux $ternary$issuer_ls180.v:41087$1864 + parameter \WIDTH 5 + connect \A 5'00000 + connect \B \core_reg1 + connect \S \rp_INT_ra_spr0_4 + connect \Y $ternary$issuer_ls180.v:41087$1864_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" + cell $mux $ternary$issuer_ls180.v:41093$1870 + parameter \WIDTH 5 + connect \A 5'00000 + connect \B \core_reg1 + connect \S \rp_INT_ra_div0_5 + connect \Y $ternary$issuer_ls180.v:41093$1870_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" + cell $mux $ternary$issuer_ls180.v:41099$1876 + parameter \WIDTH 5 + connect \A 5'00000 + connect \B \core_reg1 + connect \S \rp_INT_ra_mul0_6 + connect \Y $ternary$issuer_ls180.v:41099$1876_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" + cell $mux $ternary$issuer_ls180.v:41105$1882 + parameter \WIDTH 5 + connect \A 5'00000 + connect \B \core_reg1 + connect \S \rp_INT_ra_shiftrot0_7 + connect \Y $ternary$issuer_ls180.v:41105$1882_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" + cell $mux $ternary$issuer_ls180.v:41111$1888 + parameter \WIDTH 5 + connect \A 5'00000 + connect \B \core_reg1 + connect \S \rp_INT_ra_ldst0_8 + connect \Y $ternary$issuer_ls180.v:41111$1888_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" + cell $mux $ternary$issuer_ls180.v:41126$1903 + parameter \WIDTH 5 + connect \A 5'00000 + connect \B \core_reg2 + connect \S \rp_INT_rb_alu0_0 + connect \Y $ternary$issuer_ls180.v:41126$1903_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" + cell $mux $ternary$issuer_ls180.v:41132$1909 + parameter \WIDTH 5 + connect \A 5'00000 + connect \B \core_reg2 + connect \S \rp_INT_rb_cr0_1 + connect \Y $ternary$issuer_ls180.v:41132$1909_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" + cell $mux $ternary$issuer_ls180.v:41138$1915 + parameter \WIDTH 5 + connect \A 5'00000 + connect \B \core_reg2 + connect \S \rp_INT_rb_trap0_2 + connect \Y $ternary$issuer_ls180.v:41138$1915_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" + cell $mux $ternary$issuer_ls180.v:41144$1921 + parameter \WIDTH 5 + connect \A 5'00000 + connect \B \core_reg2 + connect \S \rp_INT_rb_logical0_3 + connect \Y $ternary$issuer_ls180.v:41144$1921_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" + cell $mux $ternary$issuer_ls180.v:41150$1927 + parameter \WIDTH 5 + connect \A 5'00000 + connect \B \core_reg2 + connect \S \rp_INT_rb_div0_4 + connect \Y $ternary$issuer_ls180.v:41150$1927_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" + cell $mux $ternary$issuer_ls180.v:41156$1933 + parameter \WIDTH 5 + connect \A 5'00000 + connect \B \core_reg2 + connect \S \rp_INT_rb_mul0_5 + connect \Y $ternary$issuer_ls180.v:41156$1933_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" + cell $mux $ternary$issuer_ls180.v:41162$1939 + parameter \WIDTH 5 + connect \A 5'00000 + connect \B \core_reg2 + connect \S \rp_INT_rb_shiftrot0_6 + connect \Y $ternary$issuer_ls180.v:41162$1939_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" + cell $mux $ternary$issuer_ls180.v:41168$1945 + parameter \WIDTH 5 + connect \A 5'00000 + connect \B \core_reg2 + connect \S \rp_INT_rb_ldst0_7 + connect \Y $ternary$issuer_ls180.v:41168$1945_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" + cell $mux $ternary$issuer_ls180.v:41182$1959 + parameter \WIDTH 5 + connect \A 5'00000 + connect \B \core_reg3 + connect \S \rp_INT_rc_shiftrot0_0 + connect \Y $ternary$issuer_ls180.v:41182$1959_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" + cell $mux $ternary$issuer_ls180.v:41188$1965 + parameter \WIDTH 5 + connect \A 5'00000 + connect \B \core_reg3 + connect \S \rp_INT_rc_ldst0_1 + connect \Y $ternary$issuer_ls180.v:41188$1965_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" + cell $mux $ternary$issuer_ls180.v:41202$1979 + parameter \WIDTH 1 + connect \A 1'0 + connect \B 1'1 + connect \S \rp_XER_xer_so_alu0_0 + connect \Y $ternary$issuer_ls180.v:41202$1979_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" + cell $mux $ternary$issuer_ls180.v:41208$1985 + parameter \WIDTH 1 + connect \A 1'0 + connect \B 1'1 + connect \S \rp_XER_xer_so_logical0_1 + connect \Y $ternary$issuer_ls180.v:41208$1985_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" + cell $mux $ternary$issuer_ls180.v:41214$1991 + parameter \WIDTH 1 + connect \A 1'0 + connect \B 1'1 + connect \S \rp_XER_xer_so_spr0_2 + connect \Y $ternary$issuer_ls180.v:41214$1991_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" + cell $mux $ternary$issuer_ls180.v:41220$1997 + parameter \WIDTH 1 + connect \A 1'0 + connect \B 1'1 + connect \S \rp_XER_xer_so_div0_3 + connect \Y $ternary$issuer_ls180.v:41220$1997_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" + cell $mux $ternary$issuer_ls180.v:41226$2003 + parameter \WIDTH 1 + connect \A 1'0 + connect \B 1'1 + connect \S \rp_XER_xer_so_mul0_4 + connect \Y $ternary$issuer_ls180.v:41226$2003_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" + cell $mux $ternary$issuer_ls180.v:41232$2009 + parameter \WIDTH 1 + connect \A 1'0 + connect \B 1'1 + connect \S \rp_XER_xer_so_shiftrot0_5 + connect \Y $ternary$issuer_ls180.v:41232$2009_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" + cell $mux $ternary$issuer_ls180.v:41248$2026 + parameter \WIDTH 2 + connect \A 2'00 + connect \B 2'10 + connect \S \rp_XER_xer_ca_alu0_0 + connect \Y $ternary$issuer_ls180.v:41248$2026_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" + cell $mux $ternary$issuer_ls180.v:41254$2032 + parameter \WIDTH 2 + connect \A 2'00 + connect \B 2'10 + connect \S \rp_XER_xer_ca_spr0_1 + connect \Y $ternary$issuer_ls180.v:41254$2032_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" + cell $mux $ternary$issuer_ls180.v:41260$2038 + parameter \WIDTH 2 + connect \A 2'00 + connect \B 2'10 + connect \S \rp_XER_xer_ca_shiftrot0_2 + connect \Y $ternary$issuer_ls180.v:41260$2038_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" + cell $mux $ternary$issuer_ls180.v:41273$2052 + parameter \WIDTH 3 + connect \A 3'000 + connect \B 3'100 + connect \S \rp_XER_xer_ov_spr0_0 + connect \Y $ternary$issuer_ls180.v:41273$2052_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" + cell $mux $ternary$issuer_ls180.v:41279$2058 + parameter \WIDTH 8 + connect \A 8'00000000 + connect \B \core_core_cr_rd + connect \S \rp_CR_full_cr_cr0_0 + connect \Y $ternary$issuer_ls180.v:41279$2058_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" + cell $mux $ternary$issuer_ls180.v:41287$2066 + parameter \WIDTH 16 + connect \A 16'0000000000000000 + connect \B \$787 + connect \S \rp_CR_cr_a_cr0_0 + connect \Y $ternary$issuer_ls180.v:41287$2066_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" + cell $mux $ternary$issuer_ls180.v:41295$2074 + parameter \WIDTH 16 + connect \A 16'0000000000000000 + connect \B \$803 + connect \S \rp_CR_cr_a_branch0_1 + connect \Y $ternary$issuer_ls180.v:41295$2074_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" + cell $mux $ternary$issuer_ls180.v:41304$2083 + parameter \WIDTH 16 + connect \A 16'0000000000000000 + connect \B \$822 + connect \S \rp_CR_cr_b_cr0_0 + connect \Y $ternary$issuer_ls180.v:41304$2083_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" + cell $mux $ternary$issuer_ls180.v:41312$2091 + parameter \WIDTH 16 + connect \A 16'0000000000000000 + connect \B \$838 + connect \S \rp_CR_cr_c_cr0_0 + connect \Y $ternary$issuer_ls180.v:41312$2091_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" + cell $mux $ternary$issuer_ls180.v:41318$2097 + parameter \WIDTH 3 + connect \A 3'000 + connect \B \core_fast1 + connect \S \rp_FAST_fast1_branch0_0 + connect \Y $ternary$issuer_ls180.v:41318$2097_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" + cell $mux $ternary$issuer_ls180.v:41324$2103 + parameter \WIDTH 3 + connect \A 3'000 + connect \B \core_fast1 + connect \S \rp_FAST_fast1_trap0_1 + connect \Y $ternary$issuer_ls180.v:41324$2103_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" + cell $mux $ternary$issuer_ls180.v:41330$2109 + parameter \WIDTH 3 + connect \A 3'000 + connect \B \core_fast1 + connect \S \rp_FAST_fast1_spr0_2 + connect \Y $ternary$issuer_ls180.v:41330$2109_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" + cell $mux $ternary$issuer_ls180.v:41339$2118 + parameter \WIDTH 3 + connect \A 3'000 + connect \B \core_fast2 + connect \S \rp_FAST_fast2_branch0_0 + connect \Y $ternary$issuer_ls180.v:41339$2118_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" + cell $mux $ternary$issuer_ls180.v:41345$2124 + parameter \WIDTH 3 + connect \A 3'000 + connect \B \core_fast2 + connect \S \rp_FAST_fast2_trap0_1 + connect \Y $ternary$issuer_ls180.v:41345$2124_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" + cell $mux $ternary$issuer_ls180.v:41353$2132 + parameter \WIDTH 10 + connect \A 10'0000000000 + connect \B \core_spr1 + connect \S \rp_SPR_spr1_spr0_0 + connect \Y $ternary$issuer_ls180.v:41353$2132_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408" + cell $mux $ternary$issuer_ls180.v:41370$2149 + parameter \WIDTH 5 + connect \A 5'00000 + connect \B \core_rego + connect \S \wp + connect \Y $ternary$issuer_ls180.v:41370$2149_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408" + cell $mux $ternary$issuer_ls180.v:41376$2155 + parameter \WIDTH 5 + connect \A 5'00000 + connect \B \core_rego + connect \S \wp$975 + connect \Y $ternary$issuer_ls180.v:41376$2155_Y + end + attribute \module_not_derived 1 + attribute \src "issuer_ls180.v:41540.6-41557.4" + cell \cr \cr + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \data_i \cr_data_i + connect \full_rd2__data_o \full_rd2__data_o + connect \full_rd2__ren \full_rd2__ren + connect \full_rd__data_o \cr_full_rd__data_o + connect \full_rd__ren \cr_full_rd__ren + connect \full_wr__data_i \cr_full_wr__data_i + connect \full_wr__wen \cr_full_wr__wen + connect \src1__data_o \cr_src1__data_o + connect \src1__ren \cr_src1__ren + connect \src2__data_o \cr_src2__data_o + connect \src2__ren \cr_src2__ren + connect \src3__data_o \cr_src3__data_o + connect \src3__ren \cr_src3__ren + connect \wen \cr_wen + end + attribute \module_not_derived 1 + attribute \src "issuer_ls180.v:41558.11-41579.4" + cell \dec_ALU \dec_ALU + connect \ALU_ALU__data_len \dec_ALU_ALU_ALU__data_len + connect \ALU_ALU__fn_unit \dec_ALU_ALU_ALU__fn_unit + connect \ALU_ALU__imm_data__data \dec_ALU_ALU_ALU__imm_data__data + connect \ALU_ALU__imm_data__ok \dec_ALU_ALU_ALU__imm_data__ok + connect \ALU_ALU__input_carry \dec_ALU_ALU_ALU__input_carry + connect \ALU_ALU__insn \dec_ALU_ALU_ALU__insn + connect \ALU_ALU__insn_type \dec_ALU_ALU_ALU__insn_type + connect \ALU_ALU__invert_in \dec_ALU_ALU_ALU__invert_in + connect \ALU_ALU__invert_out \dec_ALU_ALU_ALU__invert_out + connect \ALU_ALU__is_32bit \dec_ALU_ALU_ALU__is_32bit + connect \ALU_ALU__is_signed \dec_ALU_ALU_ALU__is_signed + connect \ALU_ALU__oe__oe \dec_ALU_ALU_ALU__oe__oe + connect \ALU_ALU__oe__ok \dec_ALU_ALU_ALU__oe__ok + connect \ALU_ALU__output_carry \dec_ALU_ALU_ALU__output_carry + connect \ALU_ALU__rc__ok \dec_ALU_ALU_ALU__rc__ok + connect \ALU_ALU__rc__rc \dec_ALU_ALU_ALU__rc__rc + connect \ALU_ALU__write_cr0 \dec_ALU_ALU_ALU__write_cr0 + connect \ALU_ALU__zero_a \dec_ALU_ALU_ALU__zero_a + connect \bigendian \dec_ALU_bigendian + connect \raw_opcode_in \dec_ALU_raw_opcode_in + end + attribute \module_not_derived 1 + attribute \src "issuer_ls180.v:41580.14-41592.4" + cell \dec_BRANCH \dec_BRANCH + connect \BRANCH_BRANCH__cia \dec_BRANCH_BRANCH_BRANCH__cia + connect \BRANCH_BRANCH__fn_unit \dec_BRANCH_BRANCH_BRANCH__fn_unit + connect \BRANCH_BRANCH__imm_data__data \dec_BRANCH_BRANCH_BRANCH__imm_data__data + connect \BRANCH_BRANCH__imm_data__ok \dec_BRANCH_BRANCH_BRANCH__imm_data__ok + connect \BRANCH_BRANCH__insn \dec_BRANCH_BRANCH_BRANCH__insn + connect \BRANCH_BRANCH__insn_type \dec_BRANCH_BRANCH_BRANCH__insn_type + connect \BRANCH_BRANCH__is_32bit \dec_BRANCH_BRANCH_BRANCH__is_32bit + connect \BRANCH_BRANCH__lk \dec_BRANCH_BRANCH_BRANCH__lk + connect \bigendian \dec_BRANCH_bigendian + connect \core_pc \core_pc + connect \raw_opcode_in \dec_BRANCH_raw_opcode_in + end + attribute \module_not_derived 1 + attribute \src "issuer_ls180.v:41593.10-41599.4" + cell \dec_CR \dec_CR + connect \CR_CR__fn_unit \dec_CR_CR_CR__fn_unit + connect \CR_CR__insn \dec_CR_CR_CR__insn + connect \CR_CR__insn_type \dec_CR_CR_CR__insn_type + connect \bigendian \dec_CR_bigendian + connect \raw_opcode_in \dec_CR_raw_opcode_in + end + attribute \module_not_derived 1 + attribute \src "issuer_ls180.v:41600.11-41621.4" + cell \dec_DIV \dec_DIV + connect \DIV_DIV__data_len \dec_DIV_DIV_DIV__data_len + connect \DIV_DIV__fn_unit \dec_DIV_DIV_DIV__fn_unit + connect \DIV_DIV__imm_data__data \dec_DIV_DIV_DIV__imm_data__data + connect \DIV_DIV__imm_data__ok \dec_DIV_DIV_DIV__imm_data__ok + connect \DIV_DIV__input_carry \dec_DIV_DIV_DIV__input_carry + connect \DIV_DIV__insn \dec_DIV_DIV_DIV__insn + connect \DIV_DIV__insn_type \dec_DIV_DIV_DIV__insn_type + connect \DIV_DIV__invert_in \dec_DIV_DIV_DIV__invert_in + connect \DIV_DIV__invert_out \dec_DIV_DIV_DIV__invert_out + connect \DIV_DIV__is_32bit \dec_DIV_DIV_DIV__is_32bit + connect \DIV_DIV__is_signed \dec_DIV_DIV_DIV__is_signed + connect \DIV_DIV__oe__oe \dec_DIV_DIV_DIV__oe__oe + connect \DIV_DIV__oe__ok \dec_DIV_DIV_DIV__oe__ok + connect \DIV_DIV__output_carry \dec_DIV_DIV_DIV__output_carry + connect \DIV_DIV__rc__ok \dec_DIV_DIV_DIV__rc__ok + connect \DIV_DIV__rc__rc \dec_DIV_DIV_DIV__rc__rc + connect \DIV_DIV__write_cr0 \dec_DIV_DIV_DIV__write_cr0 + connect \DIV_DIV__zero_a \dec_DIV_DIV_DIV__zero_a + connect \bigendian \dec_DIV_bigendian + connect \raw_opcode_in \dec_DIV_raw_opcode_in + end + attribute \module_not_derived 1 + attribute \src "issuer_ls180.v:41622.12-41641.4" + cell \dec_LDST \dec_LDST + connect \LDST_LDST__byte_reverse \dec_LDST_LDST_LDST__byte_reverse + connect \LDST_LDST__data_len \dec_LDST_LDST_LDST__data_len + connect \LDST_LDST__fn_unit \dec_LDST_LDST_LDST__fn_unit + connect \LDST_LDST__imm_data__data \dec_LDST_LDST_LDST__imm_data__data + connect \LDST_LDST__imm_data__ok \dec_LDST_LDST_LDST__imm_data__ok + connect \LDST_LDST__insn \dec_LDST_LDST_LDST__insn + connect \LDST_LDST__insn_type \dec_LDST_LDST_LDST__insn_type + connect \LDST_LDST__is_32bit \dec_LDST_LDST_LDST__is_32bit + connect \LDST_LDST__is_signed \dec_LDST_LDST_LDST__is_signed + connect \LDST_LDST__ldst_mode \dec_LDST_LDST_LDST__ldst_mode + connect \LDST_LDST__oe__oe \dec_LDST_LDST_LDST__oe__oe + connect \LDST_LDST__oe__ok \dec_LDST_LDST_LDST__oe__ok + connect \LDST_LDST__rc__ok \dec_LDST_LDST_LDST__rc__ok + connect \LDST_LDST__rc__rc \dec_LDST_LDST_LDST__rc__rc + connect \LDST_LDST__sign_extend \dec_LDST_LDST_LDST__sign_extend + connect \LDST_LDST__zero_a \dec_LDST_LDST_LDST__zero_a + connect \bigendian \dec_LDST_bigendian + connect \raw_opcode_in \dec_LDST_raw_opcode_in + end + attribute \module_not_derived 1 + attribute \src "issuer_ls180.v:41642.15-41663.4" + cell \dec_LOGICAL \dec_LOGICAL + connect \LOGICAL_LOGICAL__data_len \dec_LOGICAL_LOGICAL_LOGICAL__data_len + connect \LOGICAL_LOGICAL__fn_unit \dec_LOGICAL_LOGICAL_LOGICAL__fn_unit + connect \LOGICAL_LOGICAL__imm_data__data \dec_LOGICAL_LOGICAL_LOGICAL__imm_data__data + connect \LOGICAL_LOGICAL__imm_data__ok \dec_LOGICAL_LOGICAL_LOGICAL__imm_data__ok + connect \LOGICAL_LOGICAL__input_carry \dec_LOGICAL_LOGICAL_LOGICAL__input_carry + connect \LOGICAL_LOGICAL__insn \dec_LOGICAL_LOGICAL_LOGICAL__insn + connect \LOGICAL_LOGICAL__insn_type \dec_LOGICAL_LOGICAL_LOGICAL__insn_type + connect \LOGICAL_LOGICAL__invert_in \dec_LOGICAL_LOGICAL_LOGICAL__invert_in + connect \LOGICAL_LOGICAL__invert_out \dec_LOGICAL_LOGICAL_LOGICAL__invert_out + connect \LOGICAL_LOGICAL__is_32bit \dec_LOGICAL_LOGICAL_LOGICAL__is_32bit + connect \LOGICAL_LOGICAL__is_signed \dec_LOGICAL_LOGICAL_LOGICAL__is_signed + connect \LOGICAL_LOGICAL__oe__oe \dec_LOGICAL_LOGICAL_LOGICAL__oe__oe + connect \LOGICAL_LOGICAL__oe__ok \dec_LOGICAL_LOGICAL_LOGICAL__oe__ok + connect \LOGICAL_LOGICAL__output_carry \dec_LOGICAL_LOGICAL_LOGICAL__output_carry + connect \LOGICAL_LOGICAL__rc__ok \dec_LOGICAL_LOGICAL_LOGICAL__rc__ok + connect \LOGICAL_LOGICAL__rc__rc \dec_LOGICAL_LOGICAL_LOGICAL__rc__rc + connect \LOGICAL_LOGICAL__write_cr0 \dec_LOGICAL_LOGICAL_LOGICAL__write_cr0 + connect \LOGICAL_LOGICAL__zero_a \dec_LOGICAL_LOGICAL_LOGICAL__zero_a + connect \bigendian \dec_LOGICAL_bigendian + connect \raw_opcode_in \dec_LOGICAL_raw_opcode_in + end + attribute \module_not_derived 1 + attribute \src "issuer_ls180.v:41664.11-41679.4" + cell \dec_MUL \dec_MUL + connect \MUL_MUL__fn_unit \dec_MUL_MUL_MUL__fn_unit + connect \MUL_MUL__imm_data__data \dec_MUL_MUL_MUL__imm_data__data + connect \MUL_MUL__imm_data__ok \dec_MUL_MUL_MUL__imm_data__ok + connect \MUL_MUL__insn \dec_MUL_MUL_MUL__insn + connect \MUL_MUL__insn_type \dec_MUL_MUL_MUL__insn_type + connect \MUL_MUL__is_32bit \dec_MUL_MUL_MUL__is_32bit + connect \MUL_MUL__is_signed \dec_MUL_MUL_MUL__is_signed + connect \MUL_MUL__oe__oe \dec_MUL_MUL_MUL__oe__oe + connect \MUL_MUL__oe__ok \dec_MUL_MUL_MUL__oe__ok + connect \MUL_MUL__rc__ok \dec_MUL_MUL_MUL__rc__ok + connect \MUL_MUL__rc__rc \dec_MUL_MUL_MUL__rc__rc + connect \MUL_MUL__write_cr0 \dec_MUL_MUL_MUL__write_cr0 + connect \bigendian \dec_MUL_bigendian + connect \raw_opcode_in \dec_MUL_raw_opcode_in + end + attribute \module_not_derived 1 + attribute \src "issuer_ls180.v:41680.17-41699.4" + cell \dec_SHIFT_ROT \dec_SHIFT_ROT + connect \SHIFT_ROT_SHIFT_ROT__fn_unit \dec_SHIFT_ROT_SHIFT_ROT_SHIFT_ROT__fn_unit + connect \SHIFT_ROT_SHIFT_ROT__imm_data__data \dec_SHIFT_ROT_SHIFT_ROT_SHIFT_ROT__imm_data__data + connect \SHIFT_ROT_SHIFT_ROT__imm_data__ok \dec_SHIFT_ROT_SHIFT_ROT_SHIFT_ROT__imm_data__ok + connect \SHIFT_ROT_SHIFT_ROT__input_carry \dec_SHIFT_ROT_SHIFT_ROT_SHIFT_ROT__input_carry + connect \SHIFT_ROT_SHIFT_ROT__input_cr \dec_SHIFT_ROT_SHIFT_ROT_SHIFT_ROT__input_cr + connect \SHIFT_ROT_SHIFT_ROT__insn \dec_SHIFT_ROT_SHIFT_ROT_SHIFT_ROT__insn + connect \SHIFT_ROT_SHIFT_ROT__insn_type \dec_SHIFT_ROT_SHIFT_ROT_SHIFT_ROT__insn_type + connect \SHIFT_ROT_SHIFT_ROT__is_32bit \dec_SHIFT_ROT_SHIFT_ROT_SHIFT_ROT__is_32bit + connect \SHIFT_ROT_SHIFT_ROT__is_signed \dec_SHIFT_ROT_SHIFT_ROT_SHIFT_ROT__is_signed + connect \SHIFT_ROT_SHIFT_ROT__oe__oe \dec_SHIFT_ROT_SHIFT_ROT_SHIFT_ROT__oe__oe + connect \SHIFT_ROT_SHIFT_ROT__oe__ok \dec_SHIFT_ROT_SHIFT_ROT_SHIFT_ROT__oe__ok + connect \SHIFT_ROT_SHIFT_ROT__output_carry \dec_SHIFT_ROT_SHIFT_ROT_SHIFT_ROT__output_carry + connect \SHIFT_ROT_SHIFT_ROT__output_cr \dec_SHIFT_ROT_SHIFT_ROT_SHIFT_ROT__output_cr + connect \SHIFT_ROT_SHIFT_ROT__rc__ok \dec_SHIFT_ROT_SHIFT_ROT_SHIFT_ROT__rc__ok + connect \SHIFT_ROT_SHIFT_ROT__rc__rc \dec_SHIFT_ROT_SHIFT_ROT_SHIFT_ROT__rc__rc + connect \SHIFT_ROT_SHIFT_ROT__write_cr0 \dec_SHIFT_ROT_SHIFT_ROT_SHIFT_ROT__write_cr0 + connect \bigendian \dec_SHIFT_ROT_bigendian + connect \raw_opcode_in \dec_SHIFT_ROT_raw_opcode_in + end + attribute \module_not_derived 1 + attribute \src "issuer_ls180.v:41700.11-41707.4" + cell \dec_SPR \dec_SPR + connect \SPR_SPR__fn_unit \dec_SPR_SPR_SPR__fn_unit + connect \SPR_SPR__insn \dec_SPR_SPR_SPR__insn + connect \SPR_SPR__insn_type \dec_SPR_SPR_SPR__insn_type + connect \SPR_SPR__is_32bit \dec_SPR_SPR_SPR__is_32bit + connect \bigendian \dec_SPR_bigendian + connect \raw_opcode_in \dec_SPR_raw_opcode_in + end + attribute \module_not_derived 1 + attribute \src "issuer_ls180.v:41708.8-41726.4" + cell \fast \fast + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \dest1__addr \fast_dest1__addr + connect \dest1__data_i \fast_dest1__data_i + connect \dest1__wen \fast_dest1__wen + connect \issue__addr \issue__addr + connect \issue__addr$1 \issue__addr$3 + connect \issue__data_i \issue__data_i + connect \issue__data_o \issue__data_o + connect \issue__ren \issue__ren + connect \issue__wen \issue__wen + connect \src1__addr \fast_src1__addr + connect \src1__data_o \fast_src1__data_o + connect \src1__ren \fast_src1__ren + connect \src2__addr \fast_src2__addr + connect \src2__data_o \fast_src2__data_o + connect \src2__ren \fast_src2__ren + end + attribute \module_not_derived 1 + attribute \src "issuer_ls180.v:41727.7-42049.4" + cell \fus \fus + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \cr_a_ok \fus_cr_a_ok + connect \cr_a_ok$110 \fus_cr_a_ok$113 + connect \cr_a_ok$111 \fus_cr_a_ok$114 + connect \cr_a_ok$112 \fus_cr_a_ok$115 + connect \cr_a_ok$113 \fus_cr_a_ok$116 + connect \cr_a_ok$114 \fus_cr_a_ok$117 + connect \cu_ad__go_i \cu_ad__go_i + connect \cu_ad__rel_o \cu_ad__rel_o + connect \cu_busy_o \fus_cu_busy_o + connect \cu_busy_o$11 \fus_cu_busy_o$14 + connect \cu_busy_o$14 \fus_cu_busy_o$17 + connect \cu_busy_o$17 \fus_cu_busy_o$20 + connect \cu_busy_o$2 \fus_cu_busy_o$5 + connect \cu_busy_o$20 \fus_cu_busy_o$23 + connect \cu_busy_o$23 \fus_cu_busy_o$26 + connect \cu_busy_o$26 \fus_cu_busy_o$29 + connect \cu_busy_o$5 \fus_cu_busy_o$8 + connect \cu_busy_o$8 \fus_cu_busy_o$11 + connect \cu_issue_i \fus_cu_issue_i + connect \cu_issue_i$1 \fus_cu_issue_i$4 + connect \cu_issue_i$10 \fus_cu_issue_i$13 + connect \cu_issue_i$13 \fus_cu_issue_i$16 + connect \cu_issue_i$16 \fus_cu_issue_i$19 + connect \cu_issue_i$19 \fus_cu_issue_i$22 + connect \cu_issue_i$22 \fus_cu_issue_i$25 + connect \cu_issue_i$25 \fus_cu_issue_i$28 + connect \cu_issue_i$4 \fus_cu_issue_i$7 + connect \cu_issue_i$7 \fus_cu_issue_i$10 + connect \cu_rd__go_i \fus_cu_rd__go_i + connect \cu_rd__go_i$29 \fus_cu_rd__go_i$32 + connect \cu_rd__go_i$32 \fus_cu_rd__go_i$35 + connect \cu_rd__go_i$35 \fus_cu_rd__go_i$38 + connect \cu_rd__go_i$38 \fus_cu_rd__go_i$41 + connect \cu_rd__go_i$41 \fus_cu_rd__go_i$44 + connect \cu_rd__go_i$44 \fus_cu_rd__go_i$47 + connect \cu_rd__go_i$47 \fus_cu_rd__go_i$50 + connect \cu_rd__go_i$50 \fus_cu_rd__go_i$53 + connect \cu_rd__go_i$70 \fus_cu_rd__go_i$73 + connect \cu_rd__rel_o \fus_cu_rd__rel_o + connect \cu_rd__rel_o$28 \fus_cu_rd__rel_o$31 + connect \cu_rd__rel_o$31 \fus_cu_rd__rel_o$34 + connect \cu_rd__rel_o$34 \fus_cu_rd__rel_o$37 + connect \cu_rd__rel_o$37 \fus_cu_rd__rel_o$40 + connect \cu_rd__rel_o$40 \fus_cu_rd__rel_o$43 + connect \cu_rd__rel_o$43 \fus_cu_rd__rel_o$46 + connect \cu_rd__rel_o$46 \fus_cu_rd__rel_o$49 + connect \cu_rd__rel_o$49 \fus_cu_rd__rel_o$52 + connect \cu_rd__rel_o$69 \fus_cu_rd__rel_o$72 + connect \cu_rdmaskn_i \fus_cu_rdmaskn_i + connect \cu_rdmaskn_i$12 \fus_cu_rdmaskn_i$15 + connect \cu_rdmaskn_i$15 \fus_cu_rdmaskn_i$18 + connect \cu_rdmaskn_i$18 \fus_cu_rdmaskn_i$21 + connect \cu_rdmaskn_i$21 \fus_cu_rdmaskn_i$24 + connect \cu_rdmaskn_i$24 \fus_cu_rdmaskn_i$27 + connect \cu_rdmaskn_i$27 \fus_cu_rdmaskn_i$30 + connect \cu_rdmaskn_i$3 \fus_cu_rdmaskn_i$6 + connect \cu_rdmaskn_i$6 \fus_cu_rdmaskn_i$9 + connect \cu_rdmaskn_i$9 \fus_cu_rdmaskn_i$12 + connect \cu_st__go_i \cu_st__go_i + connect \cu_st__rel_o \cu_st__rel_o + connect \cu_wr__go_i \fus_cu_wr__go_i + connect \cu_wr__go_i$100 \fus_cu_wr__go_i$103 + connect \cu_wr__go_i$102 \fus_cu_wr__go_i$105 + connect \cu_wr__go_i$137 \fus_cu_wr__go_i$140 + connect \cu_wr__go_i$82 \fus_cu_wr__go_i$85 + connect \cu_wr__go_i$85 \fus_cu_wr__go_i$88 + connect \cu_wr__go_i$88 \fus_cu_wr__go_i$91 + connect \cu_wr__go_i$91 \fus_cu_wr__go_i$94 + connect \cu_wr__go_i$94 \fus_cu_wr__go_i$97 + connect \cu_wr__go_i$97 \fus_cu_wr__go_i$100 + connect \cu_wr__rel_o \fus_cu_wr__rel_o + connect \cu_wr__rel_o$101 \fus_cu_wr__rel_o$104 + connect \cu_wr__rel_o$136 \fus_cu_wr__rel_o$139 + connect \cu_wr__rel_o$81 \fus_cu_wr__rel_o$84 + connect \cu_wr__rel_o$84 \fus_cu_wr__rel_o$87 + connect \cu_wr__rel_o$87 \fus_cu_wr__rel_o$90 + connect \cu_wr__rel_o$90 \fus_cu_wr__rel_o$93 + connect \cu_wr__rel_o$93 \fus_cu_wr__rel_o$96 + connect \cu_wr__rel_o$96 \fus_cu_wr__rel_o$99 + connect \cu_wr__rel_o$99 \fus_cu_wr__rel_o$102 + connect \dest1_o \fus_dest1_o + connect \dest1_o$103 \fus_dest1_o$106 + connect \dest1_o$104 \fus_dest1_o$107 + connect \dest1_o$105 \fus_dest1_o$108 + connect \dest1_o$106 \fus_dest1_o$109 + connect \dest1_o$107 \fus_dest1_o$110 + connect \dest1_o$108 \fus_dest1_o$111 + connect \dest1_o$109 \fus_dest1_o$112 + connect \dest1_o$141 \fus_dest1_o$144 + connect \dest2_o \fus_dest2_o + connect \dest2_o$115 \fus_dest2_o$118 + connect \dest2_o$116 \fus_dest2_o$119 + connect \dest2_o$117 \fus_dest2_o$120 + connect \dest2_o$118 \fus_dest2_o$121 + connect \dest2_o$119 \fus_dest2_o$122 + connect \dest2_o$142 \fus_dest2_o$145 + connect \dest2_o$144 \fus_dest2_o$147 + connect \dest2_o$150 \fus_dest2_o$153 + connect \dest3_o \fus_dest3_o + connect \dest3_o$122 \fus_dest3_o$125 + connect \dest3_o$123 \fus_dest3_o$126 + connect \dest3_o$127 \fus_dest3_o$130 + connect \dest3_o$128 \fus_dest3_o$131 + connect \dest3_o$143 \fus_dest3_o$146 + connect \dest3_o$145 \fus_dest3_o$148 + connect \dest3_o$147 \fus_dest3_o$150 + connect \dest4_o \fus_dest4_o + connect \dest4_o$133 \fus_dest4_o$136 + connect \dest4_o$134 \fus_dest4_o$137 + connect \dest4_o$135 \fus_dest4_o$138 + connect \dest4_o$148 \fus_dest4_o$151 + connect \dest5_o \fus_dest5_o + connect \dest5_o$132 \fus_dest5_o$135 + connect \dest5_o$149 \fus_dest5_o$152 + connect \dest6_o \fus_dest6_o + connect \ea \fus_ea + connect \fast1_ok \fus_fast1_ok + connect \fast1_ok$138 \fus_fast1_ok$141 + connect \fast1_ok$139 \fus_fast1_ok$142 + connect \fast2_ok \fus_fast2_ok + connect \fast2_ok$140 \fus_fast2_ok$143 + connect \full_cr_ok \fus_full_cr_ok + connect \ldst_port0_addr_exc_o \fus_ldst_port0_addr_exc_o + connect \ldst_port0_addr_i \fus_ldst_port0_addr_i + connect \ldst_port0_addr_i_ok \fus_ldst_port0_addr_i_ok + connect \ldst_port0_addr_ok_o \fus_ldst_port0_addr_ok_o + connect \ldst_port0_busy_o \fus_ldst_port0_busy_o + connect \ldst_port0_data_len \fus_ldst_port0_data_len + connect \ldst_port0_is_ld_i \fus_ldst_port0_is_ld_i + connect \ldst_port0_is_st_i \fus_ldst_port0_is_st_i + connect \ldst_port0_ld_data_o \fus_ldst_port0_ld_data_o + connect \ldst_port0_ld_data_o_ok \fus_ldst_port0_ld_data_o_ok + connect \ldst_port0_st_data_i \fus_ldst_port0_st_data_i + connect \ldst_port0_st_data_i_ok \fus_ldst_port0_st_data_i_ok + connect \msr_ok \fus_msr_ok + connect \nia_ok \fus_nia_ok + connect \nia_ok$146 \fus_nia_ok$149 + connect \o \fus_o + connect \o_ok \fus_o_ok + connect \o_ok$80 \fus_o_ok$83 + connect \o_ok$83 \fus_o_ok$86 + connect \o_ok$86 \fus_o_ok$89 + connect \o_ok$89 \fus_o_ok$92 + connect \o_ok$92 \fus_o_ok$95 + connect \o_ok$95 \fus_o_ok$98 + connect \o_ok$98 \fus_o_ok$101 + connect \oper_i_alu_alu0__data_len \fus_oper_i_alu_alu0__data_len + connect \oper_i_alu_alu0__fn_unit \fus_oper_i_alu_alu0__fn_unit + connect \oper_i_alu_alu0__imm_data__data \fus_oper_i_alu_alu0__imm_data__data + connect \oper_i_alu_alu0__imm_data__ok \fus_oper_i_alu_alu0__imm_data__ok + connect \oper_i_alu_alu0__input_carry \fus_oper_i_alu_alu0__input_carry + connect \oper_i_alu_alu0__insn \fus_oper_i_alu_alu0__insn + connect \oper_i_alu_alu0__insn_type \fus_oper_i_alu_alu0__insn_type + connect \oper_i_alu_alu0__invert_in \fus_oper_i_alu_alu0__invert_in + connect \oper_i_alu_alu0__invert_out \fus_oper_i_alu_alu0__invert_out + connect \oper_i_alu_alu0__is_32bit \fus_oper_i_alu_alu0__is_32bit + connect \oper_i_alu_alu0__is_signed \fus_oper_i_alu_alu0__is_signed + connect \oper_i_alu_alu0__oe__oe \fus_oper_i_alu_alu0__oe__oe + connect \oper_i_alu_alu0__oe__ok \fus_oper_i_alu_alu0__oe__ok + connect \oper_i_alu_alu0__output_carry \fus_oper_i_alu_alu0__output_carry + connect \oper_i_alu_alu0__rc__ok \fus_oper_i_alu_alu0__rc__ok + connect \oper_i_alu_alu0__rc__rc \fus_oper_i_alu_alu0__rc__rc + connect \oper_i_alu_alu0__write_cr0 \fus_oper_i_alu_alu0__write_cr0 + connect \oper_i_alu_alu0__zero_a \fus_oper_i_alu_alu0__zero_a + connect \oper_i_alu_branch0__cia \fus_oper_i_alu_branch0__cia + connect \oper_i_alu_branch0__fn_unit \fus_oper_i_alu_branch0__fn_unit + connect \oper_i_alu_branch0__imm_data__data \fus_oper_i_alu_branch0__imm_data__data + connect \oper_i_alu_branch0__imm_data__ok \fus_oper_i_alu_branch0__imm_data__ok + connect \oper_i_alu_branch0__insn \fus_oper_i_alu_branch0__insn + connect \oper_i_alu_branch0__insn_type \fus_oper_i_alu_branch0__insn_type + connect \oper_i_alu_branch0__is_32bit \fus_oper_i_alu_branch0__is_32bit + connect \oper_i_alu_branch0__lk \fus_oper_i_alu_branch0__lk + connect \oper_i_alu_cr0__fn_unit \fus_oper_i_alu_cr0__fn_unit + connect \oper_i_alu_cr0__insn \fus_oper_i_alu_cr0__insn + connect \oper_i_alu_cr0__insn_type \fus_oper_i_alu_cr0__insn_type + connect \oper_i_alu_div0__data_len \fus_oper_i_alu_div0__data_len + connect \oper_i_alu_div0__fn_unit \fus_oper_i_alu_div0__fn_unit + connect \oper_i_alu_div0__imm_data__data \fus_oper_i_alu_div0__imm_data__data + connect \oper_i_alu_div0__imm_data__ok \fus_oper_i_alu_div0__imm_data__ok + connect \oper_i_alu_div0__input_carry \fus_oper_i_alu_div0__input_carry + connect \oper_i_alu_div0__insn \fus_oper_i_alu_div0__insn + connect \oper_i_alu_div0__insn_type \fus_oper_i_alu_div0__insn_type + connect \oper_i_alu_div0__invert_in \fus_oper_i_alu_div0__invert_in + connect \oper_i_alu_div0__invert_out \fus_oper_i_alu_div0__invert_out + connect \oper_i_alu_div0__is_32bit \fus_oper_i_alu_div0__is_32bit + connect \oper_i_alu_div0__is_signed \fus_oper_i_alu_div0__is_signed + connect \oper_i_alu_div0__oe__oe \fus_oper_i_alu_div0__oe__oe + connect \oper_i_alu_div0__oe__ok \fus_oper_i_alu_div0__oe__ok + connect \oper_i_alu_div0__output_carry \fus_oper_i_alu_div0__output_carry + connect \oper_i_alu_div0__rc__ok \fus_oper_i_alu_div0__rc__ok + connect \oper_i_alu_div0__rc__rc \fus_oper_i_alu_div0__rc__rc + connect \oper_i_alu_div0__write_cr0 \fus_oper_i_alu_div0__write_cr0 + connect \oper_i_alu_div0__zero_a \fus_oper_i_alu_div0__zero_a + connect \oper_i_alu_logical0__data_len \fus_oper_i_alu_logical0__data_len + connect \oper_i_alu_logical0__fn_unit \fus_oper_i_alu_logical0__fn_unit + connect \oper_i_alu_logical0__imm_data__data \fus_oper_i_alu_logical0__imm_data__data + connect \oper_i_alu_logical0__imm_data__ok \fus_oper_i_alu_logical0__imm_data__ok + connect \oper_i_alu_logical0__input_carry \fus_oper_i_alu_logical0__input_carry + connect \oper_i_alu_logical0__insn \fus_oper_i_alu_logical0__insn + connect \oper_i_alu_logical0__insn_type \fus_oper_i_alu_logical0__insn_type + connect \oper_i_alu_logical0__invert_in \fus_oper_i_alu_logical0__invert_in + connect \oper_i_alu_logical0__invert_out \fus_oper_i_alu_logical0__invert_out + connect \oper_i_alu_logical0__is_32bit \fus_oper_i_alu_logical0__is_32bit + connect \oper_i_alu_logical0__is_signed \fus_oper_i_alu_logical0__is_signed + connect \oper_i_alu_logical0__oe__oe \fus_oper_i_alu_logical0__oe__oe + connect \oper_i_alu_logical0__oe__ok \fus_oper_i_alu_logical0__oe__ok + connect \oper_i_alu_logical0__output_carry \fus_oper_i_alu_logical0__output_carry + connect \oper_i_alu_logical0__rc__ok \fus_oper_i_alu_logical0__rc__ok + connect \oper_i_alu_logical0__rc__rc \fus_oper_i_alu_logical0__rc__rc + connect \oper_i_alu_logical0__write_cr0 \fus_oper_i_alu_logical0__write_cr0 + connect \oper_i_alu_logical0__zero_a \fus_oper_i_alu_logical0__zero_a + connect \oper_i_alu_mul0__fn_unit \fus_oper_i_alu_mul0__fn_unit + connect \oper_i_alu_mul0__imm_data__data \fus_oper_i_alu_mul0__imm_data__data + connect \oper_i_alu_mul0__imm_data__ok \fus_oper_i_alu_mul0__imm_data__ok + connect \oper_i_alu_mul0__insn \fus_oper_i_alu_mul0__insn + connect \oper_i_alu_mul0__insn_type \fus_oper_i_alu_mul0__insn_type + connect \oper_i_alu_mul0__is_32bit \fus_oper_i_alu_mul0__is_32bit + connect \oper_i_alu_mul0__is_signed \fus_oper_i_alu_mul0__is_signed + connect \oper_i_alu_mul0__oe__oe \fus_oper_i_alu_mul0__oe__oe + connect \oper_i_alu_mul0__oe__ok \fus_oper_i_alu_mul0__oe__ok + connect \oper_i_alu_mul0__rc__ok \fus_oper_i_alu_mul0__rc__ok + connect \oper_i_alu_mul0__rc__rc \fus_oper_i_alu_mul0__rc__rc + connect \oper_i_alu_mul0__write_cr0 \fus_oper_i_alu_mul0__write_cr0 + connect \oper_i_alu_shift_rot0__fn_unit \fus_oper_i_alu_shift_rot0__fn_unit + connect \oper_i_alu_shift_rot0__imm_data__data \fus_oper_i_alu_shift_rot0__imm_data__data + connect \oper_i_alu_shift_rot0__imm_data__ok \fus_oper_i_alu_shift_rot0__imm_data__ok + connect \oper_i_alu_shift_rot0__input_carry \fus_oper_i_alu_shift_rot0__input_carry + connect \oper_i_alu_shift_rot0__input_cr \fus_oper_i_alu_shift_rot0__input_cr + connect \oper_i_alu_shift_rot0__insn \fus_oper_i_alu_shift_rot0__insn + connect \oper_i_alu_shift_rot0__insn_type \fus_oper_i_alu_shift_rot0__insn_type + connect \oper_i_alu_shift_rot0__is_32bit \fus_oper_i_alu_shift_rot0__is_32bit + connect \oper_i_alu_shift_rot0__is_signed \fus_oper_i_alu_shift_rot0__is_signed + connect \oper_i_alu_shift_rot0__oe__oe \fus_oper_i_alu_shift_rot0__oe__oe + connect \oper_i_alu_shift_rot0__oe__ok \fus_oper_i_alu_shift_rot0__oe__ok + connect \oper_i_alu_shift_rot0__output_carry \fus_oper_i_alu_shift_rot0__output_carry + connect \oper_i_alu_shift_rot0__output_cr \fus_oper_i_alu_shift_rot0__output_cr + connect \oper_i_alu_shift_rot0__rc__ok \fus_oper_i_alu_shift_rot0__rc__ok + connect \oper_i_alu_shift_rot0__rc__rc \fus_oper_i_alu_shift_rot0__rc__rc + connect \oper_i_alu_shift_rot0__write_cr0 \fus_oper_i_alu_shift_rot0__write_cr0 + connect \oper_i_alu_spr0__fn_unit \fus_oper_i_alu_spr0__fn_unit + connect \oper_i_alu_spr0__insn \fus_oper_i_alu_spr0__insn + connect \oper_i_alu_spr0__insn_type \fus_oper_i_alu_spr0__insn_type + connect \oper_i_alu_spr0__is_32bit \fus_oper_i_alu_spr0__is_32bit + connect \oper_i_alu_trap0__cia \fus_oper_i_alu_trap0__cia + connect \oper_i_alu_trap0__fn_unit \fus_oper_i_alu_trap0__fn_unit + connect \oper_i_alu_trap0__insn \fus_oper_i_alu_trap0__insn + connect \oper_i_alu_trap0__insn_type \fus_oper_i_alu_trap0__insn_type + connect \oper_i_alu_trap0__is_32bit \fus_oper_i_alu_trap0__is_32bit + connect \oper_i_alu_trap0__msr \fus_oper_i_alu_trap0__msr + connect \oper_i_alu_trap0__trapaddr \fus_oper_i_alu_trap0__trapaddr + connect \oper_i_alu_trap0__traptype \fus_oper_i_alu_trap0__traptype + connect \oper_i_ldst_ldst0__byte_reverse \fus_oper_i_ldst_ldst0__byte_reverse + connect \oper_i_ldst_ldst0__data_len \fus_oper_i_ldst_ldst0__data_len + connect \oper_i_ldst_ldst0__fn_unit \fus_oper_i_ldst_ldst0__fn_unit + connect \oper_i_ldst_ldst0__imm_data__data \fus_oper_i_ldst_ldst0__imm_data__data + connect \oper_i_ldst_ldst0__imm_data__ok \fus_oper_i_ldst_ldst0__imm_data__ok + connect \oper_i_ldst_ldst0__insn \fus_oper_i_ldst_ldst0__insn + connect \oper_i_ldst_ldst0__insn_type \fus_oper_i_ldst_ldst0__insn_type + connect \oper_i_ldst_ldst0__is_32bit \fus_oper_i_ldst_ldst0__is_32bit + connect \oper_i_ldst_ldst0__is_signed \fus_oper_i_ldst_ldst0__is_signed + connect \oper_i_ldst_ldst0__ldst_mode \fus_oper_i_ldst_ldst0__ldst_mode + connect \oper_i_ldst_ldst0__oe__oe \fus_oper_i_ldst_ldst0__oe__oe + connect \oper_i_ldst_ldst0__oe__ok \fus_oper_i_ldst_ldst0__oe__ok + connect \oper_i_ldst_ldst0__rc__ok \fus_oper_i_ldst_ldst0__rc__ok + connect \oper_i_ldst_ldst0__rc__rc \fus_oper_i_ldst_ldst0__rc__rc + connect \oper_i_ldst_ldst0__sign_extend \fus_oper_i_ldst_ldst0__sign_extend + connect \oper_i_ldst_ldst0__zero_a \fus_oper_i_ldst_ldst0__zero_a + connect \spr1_ok \fus_spr1_ok + connect \src1_i \fus_src1_i + connect \src1_i$30 \fus_src1_i$33 + connect \src1_i$33 \fus_src1_i$36 + connect \src1_i$36 \fus_src1_i$39 + connect \src1_i$39 \fus_src1_i$42 + connect \src1_i$42 \fus_src1_i$45 + connect \src1_i$45 \fus_src1_i$48 + connect \src1_i$48 \fus_src1_i$51 + connect \src1_i$51 \fus_src1_i$54 + connect \src1_i$74 \fus_src1_i$77 + connect \src2_i \fus_src2_i + connect \src2_i$52 \fus_src2_i$55 + connect \src2_i$53 \fus_src2_i$56 + connect \src2_i$54 \fus_src2_i$57 + connect \src2_i$55 \fus_src2_i$58 + connect \src2_i$56 \fus_src2_i$59 + connect \src2_i$57 \fus_src2_i$60 + connect \src2_i$58 \fus_src2_i$61 + connect \src2_i$77 \fus_src2_i$80 + connect \src2_i$79 \fus_src2_i$82 + connect \src3_i \fus_src3_i + connect \src3_i$59 \fus_src3_i$62 + connect \src3_i$60 \fus_src3_i$63 + connect \src3_i$61 \fus_src3_i$64 + connect \src3_i$62 \fus_src3_i$65 + connect \src3_i$63 \fus_src3_i$66 + connect \src3_i$67 \fus_src3_i$70 + connect \src3_i$71 \fus_src3_i$74 + connect \src3_i$75 \fus_src3_i$78 + connect \src3_i$76 \fus_src3_i$79 + connect \src4_i \fus_src4_i + connect \src4_i$64 \fus_src4_i$67 + connect \src4_i$65 \fus_src4_i$68 + connect \src4_i$68 \fus_src4_i$71 + connect \src4_i$78 \fus_src4_i$81 + connect \src5_i \fus_src5_i + connect \src5_i$66 \fus_src5_i$69 + connect \src5_i$72 \fus_src5_i$75 + connect \src6_i \fus_src6_i + connect \src6_i$73 \fus_src6_i$76 + connect \xer_ca_ok \fus_xer_ca_ok + connect \xer_ca_ok$120 \fus_xer_ca_ok$123 + connect \xer_ca_ok$121 \fus_xer_ca_ok$124 + connect \xer_ov_ok \fus_xer_ov_ok + connect \xer_ov_ok$124 \fus_xer_ov_ok$127 + connect \xer_ov_ok$125 \fus_xer_ov_ok$128 + connect \xer_ov_ok$126 \fus_xer_ov_ok$129 + connect \xer_so_ok \fus_xer_so_ok + connect \xer_so_ok$129 \fus_xer_so_ok$132 + connect \xer_so_ok$130 \fus_xer_so_ok$133 + connect \xer_so_ok$131 \fus_xer_so_ok$134 + end + attribute \module_not_derived 1 + attribute \src "issuer_ls180.v:42050.9-42068.4" + cell \int \int + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \dest1__addr \int_dest1__addr + connect \dest1__data_i \int_dest1__data_i + connect \dest1__wen \int_dest1__wen + connect \dmi__addr \dmi__addr + connect \dmi__data_o \dmi__data_o + connect \dmi__ren \dmi__ren + connect \src1__addr \int_src1__addr + connect \src1__data_o \int_src1__data_o + connect \src1__ren \int_src1__ren + connect \src2__addr \int_src2__addr + connect \src2__data_o \int_src2__data_o + connect \src2__ren \int_src2__ren + connect \src3__addr \int_src3__addr + connect \src3__data_o \int_src3__data_o + connect \src3__ren \int_src3__ren + end + attribute \module_not_derived 1 + attribute \src "issuer_ls180.v:42069.6-42093.4" + cell \l0 \l0 + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \dbus__ack \dbus__ack + connect \dbus__adr \dbus__adr + connect \dbus__cyc \dbus__cyc + connect \dbus__dat_r \dbus__dat_r + connect \dbus__dat_w \dbus__dat_w + connect \dbus__err \dbus__err + connect \dbus__sel \dbus__sel + connect \dbus__stb \dbus__stb + connect \dbus__we \dbus__we + connect \ldst_port0_addr_exc_o \fus_ldst_port0_addr_exc_o + connect \ldst_port0_addr_i \fus_ldst_port0_addr_i + connect \ldst_port0_addr_i_ok \fus_ldst_port0_addr_i_ok + connect \ldst_port0_addr_ok_o \fus_ldst_port0_addr_ok_o + connect \ldst_port0_busy_o \fus_ldst_port0_busy_o + connect \ldst_port0_data_len \fus_ldst_port0_data_len + connect \ldst_port0_is_ld_i \fus_ldst_port0_is_ld_i + connect \ldst_port0_is_st_i \fus_ldst_port0_is_st_i + connect \ldst_port0_ld_data_o \fus_ldst_port0_ld_data_o + connect \ldst_port0_ld_data_o_ok \fus_ldst_port0_ld_data_o_ok + connect \ldst_port0_st_data_i \fus_ldst_port0_st_data_i + connect \ldst_port0_st_data_i_ok \fus_ldst_port0_st_data_i_ok + end + attribute \module_not_derived 1 + attribute \src "issuer_ls180.v:42094.18-42098.4" + cell \rdpick_CR_cr_a \rdpick_CR_cr_a + connect \en_o \rdpick_CR_cr_a_en_o + connect \i \rdpick_CR_cr_a_i + connect \o \rdpick_CR_cr_a_o + end + attribute \module_not_derived 1 + attribute \src "issuer_ls180.v:42099.18-42103.4" + cell \rdpick_CR_cr_b \rdpick_CR_cr_b + connect \en_o \rdpick_CR_cr_b_en_o + connect \i \rdpick_CR_cr_b_i + connect \o \rdpick_CR_cr_b_o + end + attribute \module_not_derived 1 + attribute \src "issuer_ls180.v:42104.18-42108.4" + cell \rdpick_CR_cr_c \rdpick_CR_cr_c + connect \en_o \rdpick_CR_cr_c_en_o + connect \i \rdpick_CR_cr_c_i + connect \o \rdpick_CR_cr_c_o + end + attribute \module_not_derived 1 + attribute \src "issuer_ls180.v:42109.21-42113.4" + cell \rdpick_CR_full_cr \rdpick_CR_full_cr + connect \en_o \rdpick_CR_full_cr_en_o + connect \i \rdpick_CR_full_cr_i + connect \o \rdpick_CR_full_cr_o + end + attribute \module_not_derived 1 + attribute \src "issuer_ls180.v:42114.21-42118.4" + cell \rdpick_FAST_fast1 \rdpick_FAST_fast1 + connect \en_o \rdpick_FAST_fast1_en_o + connect \i \rdpick_FAST_fast1_i + connect \o \rdpick_FAST_fast1_o + end + attribute \module_not_derived 1 + attribute \src "issuer_ls180.v:42119.21-42123.4" + cell \rdpick_FAST_fast2 \rdpick_FAST_fast2 + connect \en_o \rdpick_FAST_fast2_en_o + connect \i \rdpick_FAST_fast2_i + connect \o \rdpick_FAST_fast2_o + end + attribute \module_not_derived 1 + attribute \src "issuer_ls180.v:42124.17-42128.4" + cell \rdpick_INT_ra \rdpick_INT_ra + connect \en_o \rdpick_INT_ra_en_o + connect \i \rdpick_INT_ra_i + connect \o \rdpick_INT_ra_o + end + attribute \module_not_derived 1 + attribute \src "issuer_ls180.v:42129.17-42133.4" + cell \rdpick_INT_rb \rdpick_INT_rb + connect \en_o \rdpick_INT_rb_en_o + connect \i \rdpick_INT_rb_i + connect \o \rdpick_INT_rb_o + end + attribute \module_not_derived 1 + attribute \src "issuer_ls180.v:42134.17-42138.4" + cell \rdpick_INT_rc \rdpick_INT_rc + connect \en_o \rdpick_INT_rc_en_o + connect \i \rdpick_INT_rc_i + connect \o \rdpick_INT_rc_o + end + attribute \module_not_derived 1 + attribute \src "issuer_ls180.v:42139.19-42143.4" + cell \rdpick_SPR_spr1 \rdpick_SPR_spr1 + connect \en_o \rdpick_SPR_spr1_en_o + connect \i \rdpick_SPR_spr1_i + connect \o \rdpick_SPR_spr1_o + end + attribute \module_not_derived 1 + attribute \src "issuer_ls180.v:42144.21-42148.4" + cell \rdpick_XER_xer_ca \rdpick_XER_xer_ca + connect \en_o \rdpick_XER_xer_ca_en_o + connect \i \rdpick_XER_xer_ca_i + connect \o \rdpick_XER_xer_ca_o + end + attribute \module_not_derived 1 + attribute \src "issuer_ls180.v:42149.21-42153.4" + cell \rdpick_XER_xer_ov \rdpick_XER_xer_ov + connect \en_o \rdpick_XER_xer_ov_en_o + connect \i \rdpick_XER_xer_ov_i + connect \o \rdpick_XER_xer_ov_o + end + attribute \module_not_derived 1 + attribute \src "issuer_ls180.v:42154.21-42158.4" + cell \rdpick_XER_xer_so \rdpick_XER_xer_so + connect \en_o \rdpick_XER_xer_so_en_o + connect \i \rdpick_XER_xer_so_i + connect \o \rdpick_XER_xer_so_o + end + attribute \module_not_derived 1 + attribute \src "issuer_ls180.v:42159.7-42168.4" + cell \spr \spr + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \spr1__addr \spr_spr1__addr + connect \spr1__addr$1 \spr_spr1__addr$159 + connect \spr1__data_i \spr_spr1__data_i + connect \spr1__data_o \spr_spr1__data_o + connect \spr1__ren \spr_spr1__ren + connect \spr1__wen \spr_spr1__wen + end + attribute \module_not_derived 1 + attribute \src "issuer_ls180.v:42169.9-42182.4" + cell \state \state + connect \cia__data_o \cia__data_o + connect \cia__ren \cia__ren + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \data_i \data_i + connect \data_i$1 \state_data_i + connect \data_i$2 \state_data_i$158 + connect \msr__data_o \msr__data_o + connect \msr__ren \msr__ren + connect \state_nia_wen \state_nia_wen + connect \wen \wen + connect \wen$3 \state_wen + end + attribute \module_not_derived 1 + attribute \src "issuer_ls180.v:42183.18-42187.4" + cell \wrpick_CR_cr_a \wrpick_CR_cr_a + connect \en_o \wrpick_CR_cr_a_en_o + connect \i \wrpick_CR_cr_a_i + connect \o \wrpick_CR_cr_a_o + end + attribute \module_not_derived 1 + attribute \src "issuer_ls180.v:42188.21-42192.4" + cell \wrpick_CR_full_cr \wrpick_CR_full_cr + connect \en_o \wrpick_CR_full_cr_en_o + connect \i \wrpick_CR_full_cr_i + connect \o \wrpick_CR_full_cr_o + end + attribute \module_not_derived 1 + attribute \src "issuer_ls180.v:42193.21-42197.4" + cell \wrpick_FAST_fast1 \wrpick_FAST_fast1 + connect \en_o \wrpick_FAST_fast1_en_o + connect \i \wrpick_FAST_fast1_i + connect \o \wrpick_FAST_fast1_o + end + attribute \module_not_derived 1 + attribute \src "issuer_ls180.v:42198.16-42202.4" + cell \wrpick_INT_o \wrpick_INT_o + connect \en_o \wrpick_INT_o_en_o + connect \i \wrpick_INT_o_i + connect \o \wrpick_INT_o_o + end + attribute \module_not_derived 1 + attribute \src "issuer_ls180.v:42203.19-42207.4" + cell \wrpick_SPR_spr1 \wrpick_SPR_spr1 + connect \en_o \wrpick_SPR_spr1_en_o + connect \i \wrpick_SPR_spr1_i + connect \o \wrpick_SPR_spr1_o + end + attribute \module_not_derived 1 + attribute \src "issuer_ls180.v:42208.20-42212.4" + cell \wrpick_STATE_msr \wrpick_STATE_msr + connect \en_o \wrpick_STATE_msr_en_o + connect \i \wrpick_STATE_msr_i + connect \o \wrpick_STATE_msr_o + end + attribute \module_not_derived 1 + attribute \src "issuer_ls180.v:42213.20-42217.4" + cell \wrpick_STATE_nia \wrpick_STATE_nia + connect \en_o \wrpick_STATE_nia_en_o + connect \i \wrpick_STATE_nia_i + connect \o \wrpick_STATE_nia_o + end + attribute \module_not_derived 1 + attribute \src "issuer_ls180.v:42218.21-42222.4" + cell \wrpick_XER_xer_ca \wrpick_XER_xer_ca + connect \en_o \wrpick_XER_xer_ca_en_o + connect \i \wrpick_XER_xer_ca_i + connect \o \wrpick_XER_xer_ca_o + end + attribute \module_not_derived 1 + attribute \src "issuer_ls180.v:42223.21-42227.4" + cell \wrpick_XER_xer_ov \wrpick_XER_xer_ov + connect \en_o \wrpick_XER_xer_ov_en_o + connect \i \wrpick_XER_xer_ov_i + connect \o \wrpick_XER_xer_ov_o + end + attribute \module_not_derived 1 + attribute \src "issuer_ls180.v:42228.21-42232.4" + cell \wrpick_XER_xer_so \wrpick_XER_xer_so + connect \en_o \wrpick_XER_xer_so_en_o + connect \i \wrpick_XER_xer_so_i + connect \o \wrpick_XER_xer_so_o + end + attribute \module_not_derived 1 + attribute \src "issuer_ls180.v:42233.7-42250.4" + cell \xer \xer + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \data_i \xer_data_i + connect \data_i$1 \xer_data_i$154 + connect \data_i$3 \xer_data_i$156 + connect \full_rd__data_o \full_rd__data_o + connect \full_rd__ren \full_rd__ren + connect \src1__data_o \xer_src1__data_o + connect \src1__ren \xer_src1__ren + connect \src2__data_o \xer_src2__data_o + connect \src2__ren \xer_src2__ren + connect \src3__data_o \xer_src3__data_o + connect \src3__ren \xer_src3__ren + connect \wen \xer_wen + connect \wen$2 \xer_wen$155 + connect \wen$4 \xer_wen$157 + end + attribute \src "issuer_ls180.v:34906.7-34906.20" + process $proc$issuer_ls180.v:34906$2821 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "issuer_ls180.v:36924.7-36924.30" + process $proc$issuer_ls180.v:36924$2822 + assign { } { } + assign $1\core_terminate_o[0:0] 1'0 + sync always + sync init + update \core_terminate_o $1\core_terminate_o[0:0] + end + attribute \src "issuer_ls180.v:36937.13-36937.27" + process $proc$issuer_ls180.v:36937$2823 + assign { } { } + assign $1\counter[1:0] 2'00 + sync always + sync init + update \counter $1\counter[1:0] + end + attribute \src "issuer_ls180.v:38065.7-38065.34" + process $proc$issuer_ls180.v:38065$2824 + assign { } { } + assign $1\dp_CR_cr_a_branch0_1[0:0] 1'0 + sync always + sync init + update \dp_CR_cr_a_branch0_1 $1\dp_CR_cr_a_branch0_1[0:0] + end + attribute \src "issuer_ls180.v:38069.7-38069.30" + process $proc$issuer_ls180.v:38069$2825 + assign { } { } + assign $1\dp_CR_cr_a_cr0_0[0:0] 1'0 + sync always + sync init + update \dp_CR_cr_a_cr0_0 $1\dp_CR_cr_a_cr0_0[0:0] + end + attribute \src "issuer_ls180.v:38073.7-38073.30" + process $proc$issuer_ls180.v:38073$2826 + assign { } { } + assign $1\dp_CR_cr_b_cr0_0[0:0] 1'0 + sync always + sync init + update \dp_CR_cr_b_cr0_0 $1\dp_CR_cr_b_cr0_0[0:0] + end + attribute \src "issuer_ls180.v:38077.7-38077.30" + process $proc$issuer_ls180.v:38077$2827 + assign { } { } + assign $1\dp_CR_cr_c_cr0_0[0:0] 1'0 + sync always + sync init + update \dp_CR_cr_c_cr0_0 $1\dp_CR_cr_c_cr0_0[0:0] + end + attribute \src "issuer_ls180.v:38081.7-38081.33" + process $proc$issuer_ls180.v:38081$2828 + assign { } { } + assign $1\dp_CR_full_cr_cr0_0[0:0] 1'0 + sync always + sync init + update \dp_CR_full_cr_cr0_0 $1\dp_CR_full_cr_cr0_0[0:0] + end + attribute \src "issuer_ls180.v:38085.7-38085.37" + process $proc$issuer_ls180.v:38085$2829 + assign { } { } + assign $1\dp_FAST_fast1_branch0_0[0:0] 1'0 + sync always + sync init + update \dp_FAST_fast1_branch0_0 $1\dp_FAST_fast1_branch0_0[0:0] + end + attribute \src "issuer_ls180.v:38089.7-38089.34" + process $proc$issuer_ls180.v:38089$2830 + assign { } { } + assign $1\dp_FAST_fast1_spr0_2[0:0] 1'0 + sync always + sync init + update \dp_FAST_fast1_spr0_2 $1\dp_FAST_fast1_spr0_2[0:0] + end + attribute \src "issuer_ls180.v:38093.7-38093.35" + process $proc$issuer_ls180.v:38093$2831 + assign { } { } + assign $1\dp_FAST_fast1_trap0_1[0:0] 1'0 + sync always + sync init + update \dp_FAST_fast1_trap0_1 $1\dp_FAST_fast1_trap0_1[0:0] + end + attribute \src "issuer_ls180.v:38097.7-38097.37" + process $proc$issuer_ls180.v:38097$2832 + assign { } { } + assign $1\dp_FAST_fast2_branch0_0[0:0] 1'0 + sync always + sync init + update \dp_FAST_fast2_branch0_0 $1\dp_FAST_fast2_branch0_0[0:0] + end + attribute \src "issuer_ls180.v:38101.7-38101.35" + process $proc$issuer_ls180.v:38101$2833 + assign { } { } + assign $1\dp_FAST_fast2_trap0_1[0:0] 1'0 + sync always + sync init + update \dp_FAST_fast2_trap0_1 $1\dp_FAST_fast2_trap0_1[0:0] + end + attribute \src "issuer_ls180.v:38105.7-38105.30" + process $proc$issuer_ls180.v:38105$2834 + assign { } { } + assign $1\dp_INT_ra_alu0_0[0:0] 1'0 + sync always + sync init + update \dp_INT_ra_alu0_0 $1\dp_INT_ra_alu0_0[0:0] + end + attribute \src "issuer_ls180.v:38109.7-38109.29" + process $proc$issuer_ls180.v:38109$2835 + assign { } { } + assign $1\dp_INT_ra_cr0_1[0:0] 1'0 + sync always + sync init + update \dp_INT_ra_cr0_1 $1\dp_INT_ra_cr0_1[0:0] + end + attribute \src "issuer_ls180.v:38113.7-38113.30" + process $proc$issuer_ls180.v:38113$2836 + assign { } { } + assign $1\dp_INT_ra_div0_5[0:0] 1'0 + sync always + sync init + update \dp_INT_ra_div0_5 $1\dp_INT_ra_div0_5[0:0] + end + attribute \src "issuer_ls180.v:38117.7-38117.31" + process $proc$issuer_ls180.v:38117$2837 + assign { } { } + assign $1\dp_INT_ra_ldst0_8[0:0] 1'0 + sync always + sync init + update \dp_INT_ra_ldst0_8 $1\dp_INT_ra_ldst0_8[0:0] + end + attribute \src "issuer_ls180.v:38121.7-38121.34" + process $proc$issuer_ls180.v:38121$2838 + assign { } { } + assign $1\dp_INT_ra_logical0_3[0:0] 1'0 + sync always + sync init + update \dp_INT_ra_logical0_3 $1\dp_INT_ra_logical0_3[0:0] + end + attribute \src "issuer_ls180.v:38125.7-38125.30" + process $proc$issuer_ls180.v:38125$2839 + assign { } { } + assign $1\dp_INT_ra_mul0_6[0:0] 1'0 + sync always + sync init + update \dp_INT_ra_mul0_6 $1\dp_INT_ra_mul0_6[0:0] + end + attribute \src "issuer_ls180.v:38129.7-38129.35" + process $proc$issuer_ls180.v:38129$2840 + assign { } { } + assign $1\dp_INT_ra_shiftrot0_7[0:0] 1'0 + sync always + sync init + update \dp_INT_ra_shiftrot0_7 $1\dp_INT_ra_shiftrot0_7[0:0] + end + attribute \src "issuer_ls180.v:38133.7-38133.30" + process $proc$issuer_ls180.v:38133$2841 + assign { } { } + assign $1\dp_INT_ra_spr0_4[0:0] 1'0 + sync always + sync init + update \dp_INT_ra_spr0_4 $1\dp_INT_ra_spr0_4[0:0] + end + attribute \src "issuer_ls180.v:38137.7-38137.31" + process $proc$issuer_ls180.v:38137$2842 + assign { } { } + assign $1\dp_INT_ra_trap0_2[0:0] 1'0 + sync always + sync init + update \dp_INT_ra_trap0_2 $1\dp_INT_ra_trap0_2[0:0] + end + attribute \src "issuer_ls180.v:38141.7-38141.30" + process $proc$issuer_ls180.v:38141$2843 + assign { } { } + assign $1\dp_INT_rb_alu0_0[0:0] 1'0 + sync always + sync init + update \dp_INT_rb_alu0_0 $1\dp_INT_rb_alu0_0[0:0] + end + attribute \src "issuer_ls180.v:38145.7-38145.29" + process $proc$issuer_ls180.v:38145$2844 + assign { } { } + assign $1\dp_INT_rb_cr0_1[0:0] 1'0 + sync always + sync init + update \dp_INT_rb_cr0_1 $1\dp_INT_rb_cr0_1[0:0] + end + attribute \src "issuer_ls180.v:38149.7-38149.30" + process $proc$issuer_ls180.v:38149$2845 + assign { } { } + assign $1\dp_INT_rb_div0_4[0:0] 1'0 + sync always + sync init + update \dp_INT_rb_div0_4 $1\dp_INT_rb_div0_4[0:0] + end + attribute \src "issuer_ls180.v:38153.7-38153.31" + process $proc$issuer_ls180.v:38153$2846 + assign { } { } + assign $1\dp_INT_rb_ldst0_7[0:0] 1'0 + sync always + sync init + update \dp_INT_rb_ldst0_7 $1\dp_INT_rb_ldst0_7[0:0] + end + attribute \src "issuer_ls180.v:38157.7-38157.34" + process $proc$issuer_ls180.v:38157$2847 + assign { } { } + assign $1\dp_INT_rb_logical0_3[0:0] 1'0 + sync always + sync init + update \dp_INT_rb_logical0_3 $1\dp_INT_rb_logical0_3[0:0] + end + attribute \src "issuer_ls180.v:38161.7-38161.30" + process $proc$issuer_ls180.v:38161$2848 + assign { } { } + assign $1\dp_INT_rb_mul0_5[0:0] 1'0 + sync always + sync init + update \dp_INT_rb_mul0_5 $1\dp_INT_rb_mul0_5[0:0] + end + attribute \src "issuer_ls180.v:38165.7-38165.35" + process $proc$issuer_ls180.v:38165$2849 + assign { } { } + assign $1\dp_INT_rb_shiftrot0_6[0:0] 1'0 + sync always + sync init + update \dp_INT_rb_shiftrot0_6 $1\dp_INT_rb_shiftrot0_6[0:0] + end + attribute \src "issuer_ls180.v:38169.7-38169.31" + process $proc$issuer_ls180.v:38169$2850 + assign { } { } + assign $1\dp_INT_rb_trap0_2[0:0] 1'0 + sync always + sync init + update \dp_INT_rb_trap0_2 $1\dp_INT_rb_trap0_2[0:0] + end + attribute \src "issuer_ls180.v:38173.7-38173.31" + process $proc$issuer_ls180.v:38173$2851 + assign { } { } + assign $1\dp_INT_rc_ldst0_1[0:0] 1'0 + sync always + sync init + update \dp_INT_rc_ldst0_1 $1\dp_INT_rc_ldst0_1[0:0] + end + attribute \src "issuer_ls180.v:38177.7-38177.35" + process $proc$issuer_ls180.v:38177$2852 + assign { } { } + assign $1\dp_INT_rc_shiftrot0_0[0:0] 1'0 + sync always + sync init + update \dp_INT_rc_shiftrot0_0 $1\dp_INT_rc_shiftrot0_0[0:0] + end + attribute \src "issuer_ls180.v:38181.7-38181.32" + process $proc$issuer_ls180.v:38181$2853 + assign { } { } + assign $1\dp_SPR_spr1_spr0_0[0:0] 1'0 + sync always + sync init + update \dp_SPR_spr1_spr0_0 $1\dp_SPR_spr1_spr0_0[0:0] + end + attribute \src "issuer_ls180.v:38185.7-38185.34" + process $proc$issuer_ls180.v:38185$2854 + assign { } { } + assign $1\dp_XER_xer_ca_alu0_0[0:0] 1'0 + sync always + sync init + update \dp_XER_xer_ca_alu0_0 $1\dp_XER_xer_ca_alu0_0[0:0] + end + attribute \src "issuer_ls180.v:38189.7-38189.39" + process $proc$issuer_ls180.v:38189$2855 + assign { } { } + assign $1\dp_XER_xer_ca_shiftrot0_2[0:0] 1'0 + sync always + sync init + update \dp_XER_xer_ca_shiftrot0_2 $1\dp_XER_xer_ca_shiftrot0_2[0:0] + end + attribute \src "issuer_ls180.v:38193.7-38193.34" + process $proc$issuer_ls180.v:38193$2856 + assign { } { } + assign $1\dp_XER_xer_ca_spr0_1[0:0] 1'0 + sync always + sync init + update \dp_XER_xer_ca_spr0_1 $1\dp_XER_xer_ca_spr0_1[0:0] + end + attribute \src "issuer_ls180.v:38197.7-38197.34" + process $proc$issuer_ls180.v:38197$2857 + assign { } { } + assign $1\dp_XER_xer_ov_spr0_0[0:0] 1'0 + sync always + sync init + update \dp_XER_xer_ov_spr0_0 $1\dp_XER_xer_ov_spr0_0[0:0] + end + attribute \src "issuer_ls180.v:38201.7-38201.34" + process $proc$issuer_ls180.v:38201$2858 + assign { } { } + assign $1\dp_XER_xer_so_alu0_0[0:0] 1'0 + sync always + sync init + update \dp_XER_xer_so_alu0_0 $1\dp_XER_xer_so_alu0_0[0:0] + end + attribute \src "issuer_ls180.v:38205.7-38205.34" + process $proc$issuer_ls180.v:38205$2859 + assign { } { } + assign $1\dp_XER_xer_so_div0_3[0:0] 1'0 + sync always + sync init + update \dp_XER_xer_so_div0_3 $1\dp_XER_xer_so_div0_3[0:0] + end + attribute \src "issuer_ls180.v:38209.7-38209.38" + process $proc$issuer_ls180.v:38209$2860 + assign { } { } + assign $1\dp_XER_xer_so_logical0_1[0:0] 1'0 + sync always + sync init + update \dp_XER_xer_so_logical0_1 $1\dp_XER_xer_so_logical0_1[0:0] + end + attribute \src "issuer_ls180.v:38213.7-38213.34" + process $proc$issuer_ls180.v:38213$2861 + assign { } { } + assign $1\dp_XER_xer_so_mul0_4[0:0] 1'0 + sync always + sync init + update \dp_XER_xer_so_mul0_4 $1\dp_XER_xer_so_mul0_4[0:0] + end + attribute \src "issuer_ls180.v:38217.7-38217.39" + process $proc$issuer_ls180.v:38217$2862 + assign { } { } + assign $1\dp_XER_xer_so_shiftrot0_5[0:0] 1'0 + sync always + sync init + update \dp_XER_xer_so_shiftrot0_5 $1\dp_XER_xer_so_shiftrot0_5[0:0] + end + attribute \src "issuer_ls180.v:38221.7-38221.34" + process $proc$issuer_ls180.v:38221$2863 + assign { } { } + assign $1\dp_XER_xer_so_spr0_2[0:0] 1'0 + sync always + sync init + update \dp_XER_xer_so_spr0_2 $1\dp_XER_xer_so_spr0_2[0:0] + end + attribute \src "issuer_ls180.v:40278.7-40278.25" + process $proc$issuer_ls180.v:40278$2864 + assign { } { } + assign $1\wr_pick_dly[0:0] 1'0 + sync always + sync init + update \wr_pick_dly $1\wr_pick_dly[0:0] + end + attribute \src "issuer_ls180.v:40280.7-40280.32" + process $proc$issuer_ls180.v:40280$2865 + assign { } { } + assign $0\wr_pick_dly$1007[0:0]$2866 1'0 + sync always + sync init + update \wr_pick_dly$1007 $0\wr_pick_dly$1007[0:0]$2866 + end + attribute \src "issuer_ls180.v:40284.7-40284.32" + process $proc$issuer_ls180.v:40284$2867 + assign { } { } + assign $0\wr_pick_dly$1025[0:0]$2868 1'0 + sync always + sync init + update \wr_pick_dly$1025 $0\wr_pick_dly$1025[0:0]$2868 + end + attribute \src "issuer_ls180.v:40288.7-40288.32" + process $proc$issuer_ls180.v:40288$2869 + assign { } { } + assign $0\wr_pick_dly$1047[0:0]$2870 1'0 + sync always + sync init + update \wr_pick_dly$1047 $0\wr_pick_dly$1047[0:0]$2870 + end + attribute \src "issuer_ls180.v:40292.7-40292.32" + process $proc$issuer_ls180.v:40292$2871 + assign { } { } + assign $0\wr_pick_dly$1067[0:0]$2872 1'0 + sync always + sync init + update \wr_pick_dly$1067 $0\wr_pick_dly$1067[0:0]$2872 + end + attribute \src "issuer_ls180.v:40296.7-40296.32" + process $proc$issuer_ls180.v:40296$2873 + assign { } { } + assign $0\wr_pick_dly$1087[0:0]$2874 1'0 + sync always + sync init + update \wr_pick_dly$1087 $0\wr_pick_dly$1087[0:0]$2874 + end + attribute \src "issuer_ls180.v:40300.7-40300.32" + process $proc$issuer_ls180.v:40300$2875 + assign { } { } + assign $0\wr_pick_dly$1106[0:0]$2876 1'0 + sync always + sync init + update \wr_pick_dly$1106 $0\wr_pick_dly$1106[0:0]$2876 + end + attribute \src "issuer_ls180.v:40304.7-40304.32" + process $proc$issuer_ls180.v:40304$2877 + assign { } { } + assign $0\wr_pick_dly$1124[0:0]$2878 1'0 + sync always + sync init + update \wr_pick_dly$1124 $0\wr_pick_dly$1124[0:0]$2878 + end + attribute \src "issuer_ls180.v:40308.7-40308.32" + process $proc$issuer_ls180.v:40308$2879 + assign { } { } + assign $0\wr_pick_dly$1197[0:0]$2880 1'0 + sync always + sync init + update \wr_pick_dly$1197 $0\wr_pick_dly$1197[0:0]$2880 + end + attribute \src "issuer_ls180.v:40312.7-40312.32" + process $proc$issuer_ls180.v:40312$2881 + assign { } { } + assign $0\wr_pick_dly$1225[0:0]$2882 1'0 + sync always + sync init + update \wr_pick_dly$1225 $0\wr_pick_dly$1225[0:0]$2882 + end + attribute \src "issuer_ls180.v:40316.7-40316.32" + process $proc$issuer_ls180.v:40316$2883 + assign { } { } + assign $0\wr_pick_dly$1245[0:0]$2884 1'0 + sync always + sync init + update \wr_pick_dly$1245 $0\wr_pick_dly$1245[0:0]$2884 + end + attribute \src "issuer_ls180.v:40320.7-40320.32" + process $proc$issuer_ls180.v:40320$2885 + assign { } { } + assign $0\wr_pick_dly$1265[0:0]$2886 1'0 + sync always + sync init + update \wr_pick_dly$1265 $0\wr_pick_dly$1265[0:0]$2886 + end + attribute \src "issuer_ls180.v:40324.7-40324.32" + process $proc$issuer_ls180.v:40324$2887 + assign { } { } + assign $0\wr_pick_dly$1285[0:0]$2888 1'0 + sync always + sync init + update \wr_pick_dly$1285 $0\wr_pick_dly$1285[0:0]$2888 + end + attribute \src "issuer_ls180.v:40328.7-40328.32" + process $proc$issuer_ls180.v:40328$2889 + assign { } { } + assign $0\wr_pick_dly$1305[0:0]$2890 1'0 + sync always + sync init + update \wr_pick_dly$1305 $0\wr_pick_dly$1305[0:0]$2890 + end + attribute \src "issuer_ls180.v:40332.7-40332.32" + process $proc$issuer_ls180.v:40332$2891 + assign { } { } + assign $0\wr_pick_dly$1325[0:0]$2892 1'0 + sync always + sync init + update \wr_pick_dly$1325 $0\wr_pick_dly$1325[0:0]$2892 + end + attribute \src "issuer_ls180.v:40336.7-40336.32" + process $proc$issuer_ls180.v:40336$2893 + assign { } { } + assign $0\wr_pick_dly$1372[0:0]$2894 1'0 + sync always + sync init + update \wr_pick_dly$1372 $0\wr_pick_dly$1372[0:0]$2894 + end + attribute \src "issuer_ls180.v:40340.7-40340.32" + process $proc$issuer_ls180.v:40340$2895 + assign { } { } + assign $0\wr_pick_dly$1388[0:0]$2896 1'0 + sync always + sync init + update \wr_pick_dly$1388 $0\wr_pick_dly$1388[0:0]$2896 + end + attribute \src "issuer_ls180.v:40344.7-40344.32" + process $proc$issuer_ls180.v:40344$2897 + assign { } { } + assign $0\wr_pick_dly$1404[0:0]$2898 1'0 + sync always + sync init + update \wr_pick_dly$1404 $0\wr_pick_dly$1404[0:0]$2898 + end + attribute \src "issuer_ls180.v:40348.7-40348.32" + process $proc$issuer_ls180.v:40348$2899 + assign { } { } + assign $0\wr_pick_dly$1438[0:0]$2900 1'0 + sync always + sync init + update \wr_pick_dly$1438 $0\wr_pick_dly$1438[0:0]$2900 + end + attribute \src "issuer_ls180.v:40352.7-40352.32" + process $proc$issuer_ls180.v:40352$2901 + assign { } { } + assign $0\wr_pick_dly$1454[0:0]$2902 1'0 + sync always + sync init + update \wr_pick_dly$1454 $0\wr_pick_dly$1454[0:0]$2902 + end + attribute \src "issuer_ls180.v:40356.7-40356.32" + process $proc$issuer_ls180.v:40356$2903 + assign { } { } + assign $0\wr_pick_dly$1470[0:0]$2904 1'0 + sync always + sync init + update \wr_pick_dly$1470 $0\wr_pick_dly$1470[0:0]$2904 + end + attribute \src "issuer_ls180.v:40360.7-40360.32" + process $proc$issuer_ls180.v:40360$2905 + assign { } { } + assign $0\wr_pick_dly$1486[0:0]$2906 1'0 + sync always + sync init + update \wr_pick_dly$1486 $0\wr_pick_dly$1486[0:0]$2906 + end + attribute \src "issuer_ls180.v:40364.7-40364.32" + process $proc$issuer_ls180.v:40364$2907 + assign { } { } + assign $0\wr_pick_dly$1522[0:0]$2908 1'0 + sync always + sync init + update \wr_pick_dly$1522 $0\wr_pick_dly$1522[0:0]$2908 + end + attribute \src "issuer_ls180.v:40368.7-40368.32" + process $proc$issuer_ls180.v:40368$2909 + assign { } { } + assign $0\wr_pick_dly$1538[0:0]$2910 1'0 + sync always + sync init + update \wr_pick_dly$1538 $0\wr_pick_dly$1538[0:0]$2910 + end + attribute \src "issuer_ls180.v:40372.7-40372.32" + process $proc$issuer_ls180.v:40372$2911 + assign { } { } + assign $0\wr_pick_dly$1554[0:0]$2912 1'0 + sync always + sync init + update \wr_pick_dly$1554 $0\wr_pick_dly$1554[0:0]$2912 + end + attribute \src "issuer_ls180.v:40376.7-40376.32" + process $proc$issuer_ls180.v:40376$2913 + assign { } { } + assign $0\wr_pick_dly$1570[0:0]$2914 1'0 + sync always + sync init + update \wr_pick_dly$1570 $0\wr_pick_dly$1570[0:0]$2914 + end + attribute \src "issuer_ls180.v:40380.7-40380.32" + process $proc$issuer_ls180.v:40380$2915 + assign { } { } + assign $0\wr_pick_dly$1612[0:0]$2916 1'0 + sync always + sync init + update \wr_pick_dly$1612 $0\wr_pick_dly$1612[0:0]$2916 + end + attribute \src "issuer_ls180.v:40384.7-40384.32" + process $proc$issuer_ls180.v:40384$2917 + assign { } { } + assign $0\wr_pick_dly$1631[0:0]$2918 1'0 + sync always + sync init + update \wr_pick_dly$1631 $0\wr_pick_dly$1631[0:0]$2918 + end + attribute \src "issuer_ls180.v:40388.7-40388.32" + process $proc$issuer_ls180.v:40388$2919 + assign { } { } + assign $0\wr_pick_dly$1647[0:0]$2920 1'0 + sync always + sync init + update \wr_pick_dly$1647 $0\wr_pick_dly$1647[0:0]$2920 + end + attribute \src "issuer_ls180.v:40392.7-40392.32" + process $proc$issuer_ls180.v:40392$2921 + assign { } { } + assign $0\wr_pick_dly$1663[0:0]$2922 1'0 + sync always + sync init + update \wr_pick_dly$1663 $0\wr_pick_dly$1663[0:0]$2922 + end + attribute \src "issuer_ls180.v:40396.7-40396.32" + process $proc$issuer_ls180.v:40396$2923 + assign { } { } + assign $0\wr_pick_dly$1679[0:0]$2924 1'0 + sync always + sync init + update \wr_pick_dly$1679 $0\wr_pick_dly$1679[0:0]$2924 + end + attribute \src "issuer_ls180.v:40400.7-40400.32" + process $proc$issuer_ls180.v:40400$2925 + assign { } { } + assign $0\wr_pick_dly$1723[0:0]$2926 1'0 + sync always + sync init + update \wr_pick_dly$1723 $0\wr_pick_dly$1723[0:0]$2926 + end + attribute \src "issuer_ls180.v:40404.7-40404.32" + process $proc$issuer_ls180.v:40404$2927 + assign { } { } + assign $0\wr_pick_dly$1739[0:0]$2928 1'0 + sync always + sync init + update \wr_pick_dly$1739 $0\wr_pick_dly$1739[0:0]$2928 + end + attribute \src "issuer_ls180.v:40408.7-40408.32" + process $proc$issuer_ls180.v:40408$2929 + assign { } { } + assign $0\wr_pick_dly$1763[0:0]$2930 1'0 + sync always + sync init + update \wr_pick_dly$1763 $0\wr_pick_dly$1763[0:0]$2930 + end + attribute \src "issuer_ls180.v:40412.7-40412.32" + process $proc$issuer_ls180.v:40412$2931 + assign { } { } + assign $0\wr_pick_dly$1783[0:0]$2932 1'0 + sync always + sync init + update \wr_pick_dly$1783 $0\wr_pick_dly$1783[0:0]$2932 + end + attribute \src "issuer_ls180.v:40416.7-40416.31" + process $proc$issuer_ls180.v:40416$2933 + assign { } { } + assign $0\wr_pick_dly$967[0:0]$2934 1'0 + sync always + sync init + update \wr_pick_dly$967 $0\wr_pick_dly$967[0:0]$2934 + end + attribute \src "issuer_ls180.v:40420.7-40420.31" + process $proc$issuer_ls180.v:40420$2935 + assign { } { } + assign $0\wr_pick_dly$986[0:0]$2936 1'0 + sync always + sync init + update \wr_pick_dly$986 $0\wr_pick_dly$986[0:0]$2936 + end + attribute \src "issuer_ls180.v:41382.3-41383.51" + process $proc$issuer_ls180.v:41382$2161 + assign { } { } + assign $0\wr_pick_dly$1783[0:0]$2162 \wr_pick_dly$1783$next + sync posedge \coresync_clk + update \wr_pick_dly$1783 $0\wr_pick_dly$1783[0:0]$2162 + end + attribute \src "issuer_ls180.v:41384.3-41385.51" + process $proc$issuer_ls180.v:41384$2163 + assign { } { } + assign $0\wr_pick_dly$1763[0:0]$2164 \wr_pick_dly$1763$next + sync posedge \coresync_clk + update \wr_pick_dly$1763 $0\wr_pick_dly$1763[0:0]$2164 + end + attribute \src "issuer_ls180.v:41386.3-41387.51" + process $proc$issuer_ls180.v:41386$2165 + assign { } { } + assign $0\wr_pick_dly$1739[0:0]$2166 \wr_pick_dly$1739$next + sync posedge \coresync_clk + update \wr_pick_dly$1739 $0\wr_pick_dly$1739[0:0]$2166 + end + attribute \src "issuer_ls180.v:41388.3-41389.51" + process $proc$issuer_ls180.v:41388$2167 + assign { } { } + assign $0\wr_pick_dly$1723[0:0]$2168 \wr_pick_dly$1723$next + sync posedge \coresync_clk + update \wr_pick_dly$1723 $0\wr_pick_dly$1723[0:0]$2168 + end + attribute \src "issuer_ls180.v:41390.3-41391.51" + process $proc$issuer_ls180.v:41390$2169 + assign { } { } + assign $0\wr_pick_dly$1679[0:0]$2170 \wr_pick_dly$1679$next + sync posedge \coresync_clk + update \wr_pick_dly$1679 $0\wr_pick_dly$1679[0:0]$2170 + end + attribute \src "issuer_ls180.v:41392.3-41393.51" + process $proc$issuer_ls180.v:41392$2171 + assign { } { } + assign $0\wr_pick_dly$1663[0:0]$2172 \wr_pick_dly$1663$next + sync posedge \coresync_clk + update \wr_pick_dly$1663 $0\wr_pick_dly$1663[0:0]$2172 + end + attribute \src "issuer_ls180.v:41394.3-41395.51" + process $proc$issuer_ls180.v:41394$2173 + assign { } { } + assign $0\wr_pick_dly$1647[0:0]$2174 \wr_pick_dly$1647$next + sync posedge \coresync_clk + update \wr_pick_dly$1647 $0\wr_pick_dly$1647[0:0]$2174 + end + attribute \src "issuer_ls180.v:41396.3-41397.51" + process $proc$issuer_ls180.v:41396$2175 + assign { } { } + assign $0\wr_pick_dly$1631[0:0]$2176 \wr_pick_dly$1631$next + sync posedge \coresync_clk + update \wr_pick_dly$1631 $0\wr_pick_dly$1631[0:0]$2176 + end + attribute \src "issuer_ls180.v:41398.3-41399.51" + process $proc$issuer_ls180.v:41398$2177 + assign { } { } + assign $0\wr_pick_dly$1612[0:0]$2178 \wr_pick_dly$1612$next + sync posedge \coresync_clk + update \wr_pick_dly$1612 $0\wr_pick_dly$1612[0:0]$2178 + end + attribute \src "issuer_ls180.v:41400.3-41401.51" + process $proc$issuer_ls180.v:41400$2179 + assign { } { } + assign $0\wr_pick_dly$1570[0:0]$2180 \wr_pick_dly$1570$next + sync posedge \coresync_clk + update \wr_pick_dly$1570 $0\wr_pick_dly$1570[0:0]$2180 + end + attribute \src "issuer_ls180.v:41402.3-41403.51" + process $proc$issuer_ls180.v:41402$2181 + assign { } { } + assign $0\wr_pick_dly$1554[0:0]$2182 \wr_pick_dly$1554$next + sync posedge \coresync_clk + update \wr_pick_dly$1554 $0\wr_pick_dly$1554[0:0]$2182 + end + attribute \src "issuer_ls180.v:41404.3-41405.51" + process $proc$issuer_ls180.v:41404$2183 + assign { } { } + assign $0\wr_pick_dly$1538[0:0]$2184 \wr_pick_dly$1538$next + sync posedge \coresync_clk + update \wr_pick_dly$1538 $0\wr_pick_dly$1538[0:0]$2184 + end + attribute \src "issuer_ls180.v:41406.3-41407.51" + process $proc$issuer_ls180.v:41406$2185 + assign { } { } + assign $0\wr_pick_dly$1522[0:0]$2186 \wr_pick_dly$1522$next + sync posedge \coresync_clk + update \wr_pick_dly$1522 $0\wr_pick_dly$1522[0:0]$2186 + end + attribute \src "issuer_ls180.v:41408.3-41409.51" + process $proc$issuer_ls180.v:41408$2187 + assign { } { } + assign $0\wr_pick_dly$1486[0:0]$2188 \wr_pick_dly$1486$next + sync posedge \coresync_clk + update \wr_pick_dly$1486 $0\wr_pick_dly$1486[0:0]$2188 + end + attribute \src "issuer_ls180.v:41410.3-41411.51" + process $proc$issuer_ls180.v:41410$2189 + assign { } { } + assign $0\wr_pick_dly$1470[0:0]$2190 \wr_pick_dly$1470$next + sync posedge \coresync_clk + update \wr_pick_dly$1470 $0\wr_pick_dly$1470[0:0]$2190 + end + attribute \src "issuer_ls180.v:41412.3-41413.51" + process $proc$issuer_ls180.v:41412$2191 + assign { } { } + assign $0\wr_pick_dly$1454[0:0]$2192 \wr_pick_dly$1454$next + sync posedge \coresync_clk + update \wr_pick_dly$1454 $0\wr_pick_dly$1454[0:0]$2192 + end + attribute \src "issuer_ls180.v:41414.3-41415.51" + process $proc$issuer_ls180.v:41414$2193 + assign { } { } + assign $0\wr_pick_dly$1438[0:0]$2194 \wr_pick_dly$1438$next + sync posedge \coresync_clk + update \wr_pick_dly$1438 $0\wr_pick_dly$1438[0:0]$2194 + end + attribute \src "issuer_ls180.v:41416.3-41417.51" + process $proc$issuer_ls180.v:41416$2195 + assign { } { } + assign $0\wr_pick_dly$1404[0:0]$2196 \wr_pick_dly$1404$next + sync posedge \coresync_clk + update \wr_pick_dly$1404 $0\wr_pick_dly$1404[0:0]$2196 + end + attribute \src "issuer_ls180.v:41418.3-41419.51" + process $proc$issuer_ls180.v:41418$2197 + assign { } { } + assign $0\wr_pick_dly$1388[0:0]$2198 \wr_pick_dly$1388$next + sync posedge \coresync_clk + update \wr_pick_dly$1388 $0\wr_pick_dly$1388[0:0]$2198 + end + attribute \src "issuer_ls180.v:41420.3-41421.51" + process $proc$issuer_ls180.v:41420$2199 + assign { } { } + assign $0\wr_pick_dly$1372[0:0]$2200 \wr_pick_dly$1372$next + sync posedge \coresync_clk + update \wr_pick_dly$1372 $0\wr_pick_dly$1372[0:0]$2200 + end + attribute \src "issuer_ls180.v:41422.3-41423.51" + process $proc$issuer_ls180.v:41422$2201 + assign { } { } + assign $0\wr_pick_dly$1325[0:0]$2202 \wr_pick_dly$1325$next + sync posedge \coresync_clk + update \wr_pick_dly$1325 $0\wr_pick_dly$1325[0:0]$2202 + end + attribute \src "issuer_ls180.v:41424.3-41425.51" + process $proc$issuer_ls180.v:41424$2203 + assign { } { } + assign $0\wr_pick_dly$1305[0:0]$2204 \wr_pick_dly$1305$next + sync posedge \coresync_clk + update \wr_pick_dly$1305 $0\wr_pick_dly$1305[0:0]$2204 + end + attribute \src "issuer_ls180.v:41426.3-41427.51" + process $proc$issuer_ls180.v:41426$2205 + assign { } { } + assign $0\wr_pick_dly$1285[0:0]$2206 \wr_pick_dly$1285$next + sync posedge \coresync_clk + update \wr_pick_dly$1285 $0\wr_pick_dly$1285[0:0]$2206 + end + attribute \src "issuer_ls180.v:41428.3-41429.51" + process $proc$issuer_ls180.v:41428$2207 + assign { } { } + assign $0\wr_pick_dly$1265[0:0]$2208 \wr_pick_dly$1265$next + sync posedge \coresync_clk + update \wr_pick_dly$1265 $0\wr_pick_dly$1265[0:0]$2208 + end + attribute \src "issuer_ls180.v:41430.3-41431.51" + process $proc$issuer_ls180.v:41430$2209 + assign { } { } + assign $0\wr_pick_dly$1245[0:0]$2210 \wr_pick_dly$1245$next + sync posedge \coresync_clk + update \wr_pick_dly$1245 $0\wr_pick_dly$1245[0:0]$2210 + end + attribute \src "issuer_ls180.v:41432.3-41433.51" + process $proc$issuer_ls180.v:41432$2211 + assign { } { } + assign $0\wr_pick_dly$1225[0:0]$2212 \wr_pick_dly$1225$next + sync posedge \coresync_clk + update \wr_pick_dly$1225 $0\wr_pick_dly$1225[0:0]$2212 + end + attribute \src "issuer_ls180.v:41434.3-41435.51" + process $proc$issuer_ls180.v:41434$2213 + assign { } { } + assign $0\wr_pick_dly$1197[0:0]$2214 \wr_pick_dly$1197$next + sync posedge \coresync_clk + update \wr_pick_dly$1197 $0\wr_pick_dly$1197[0:0]$2214 + end + attribute \src "issuer_ls180.v:41436.3-41437.51" + process $proc$issuer_ls180.v:41436$2215 + assign { } { } + assign $0\wr_pick_dly$1124[0:0]$2216 \wr_pick_dly$1124$next + sync posedge \coresync_clk + update \wr_pick_dly$1124 $0\wr_pick_dly$1124[0:0]$2216 + end + attribute \src "issuer_ls180.v:41438.3-41439.51" + process $proc$issuer_ls180.v:41438$2217 + assign { } { } + assign $0\wr_pick_dly$1106[0:0]$2218 \wr_pick_dly$1106$next + sync posedge \coresync_clk + update \wr_pick_dly$1106 $0\wr_pick_dly$1106[0:0]$2218 + end + attribute \src "issuer_ls180.v:41440.3-41441.51" + process $proc$issuer_ls180.v:41440$2219 + assign { } { } + assign $0\wr_pick_dly$1087[0:0]$2220 \wr_pick_dly$1087$next + sync posedge \coresync_clk + update \wr_pick_dly$1087 $0\wr_pick_dly$1087[0:0]$2220 + end + attribute \src "issuer_ls180.v:41442.3-41443.51" + process $proc$issuer_ls180.v:41442$2221 + assign { } { } + assign $0\wr_pick_dly$1067[0:0]$2222 \wr_pick_dly$1067$next + sync posedge \coresync_clk + update \wr_pick_dly$1067 $0\wr_pick_dly$1067[0:0]$2222 + end + attribute \src "issuer_ls180.v:41444.3-41445.51" + process $proc$issuer_ls180.v:41444$2223 + assign { } { } + assign $0\wr_pick_dly$1047[0:0]$2224 \wr_pick_dly$1047$next + sync posedge \coresync_clk + update \wr_pick_dly$1047 $0\wr_pick_dly$1047[0:0]$2224 + end + attribute \src "issuer_ls180.v:41446.3-41447.51" + process $proc$issuer_ls180.v:41446$2225 + assign { } { } + assign $0\wr_pick_dly$1025[0:0]$2226 \wr_pick_dly$1025$next + sync posedge \coresync_clk + update \wr_pick_dly$1025 $0\wr_pick_dly$1025[0:0]$2226 + end + attribute \src "issuer_ls180.v:41448.3-41449.51" + process $proc$issuer_ls180.v:41448$2227 + assign { } { } + assign $0\wr_pick_dly$1007[0:0]$2228 \wr_pick_dly$1007$next + sync posedge \coresync_clk + update \wr_pick_dly$1007 $0\wr_pick_dly$1007[0:0]$2228 + end + attribute \src "issuer_ls180.v:41450.3-41451.49" + process $proc$issuer_ls180.v:41450$2229 + assign { } { } + assign $0\wr_pick_dly$986[0:0]$2230 \wr_pick_dly$986$next + sync posedge \coresync_clk + update \wr_pick_dly$986 $0\wr_pick_dly$986[0:0]$2230 + end + attribute \src "issuer_ls180.v:41452.3-41453.49" + process $proc$issuer_ls180.v:41452$2231 + assign { } { } + assign $0\wr_pick_dly$967[0:0]$2232 \wr_pick_dly$967$next + sync posedge \coresync_clk + update \wr_pick_dly$967 $0\wr_pick_dly$967[0:0]$2232 + end + attribute \src "issuer_ls180.v:41454.3-41455.39" + process $proc$issuer_ls180.v:41454$2233 + assign { } { } + assign $0\wr_pick_dly[0:0] \wr_pick_dly$next + sync posedge \coresync_clk + update \wr_pick_dly $0\wr_pick_dly[0:0] + end + attribute \src "issuer_ls180.v:41456.3-41457.53" + process $proc$issuer_ls180.v:41456$2234 + assign { } { } + assign $0\dp_SPR_spr1_spr0_0[0:0] \dp_SPR_spr1_spr0_0$next + sync posedge \coresync_clk + update \dp_SPR_spr1_spr0_0 $0\dp_SPR_spr1_spr0_0[0:0] + end + attribute \src "issuer_ls180.v:41458.3-41459.59" + process $proc$issuer_ls180.v:41458$2235 + assign { } { } + assign $0\dp_FAST_fast2_trap0_1[0:0] \dp_FAST_fast2_trap0_1$next + sync posedge \coresync_clk + update \dp_FAST_fast2_trap0_1 $0\dp_FAST_fast2_trap0_1[0:0] + end + attribute \src "issuer_ls180.v:41460.3-41461.63" + process $proc$issuer_ls180.v:41460$2236 + assign { } { } + assign $0\dp_FAST_fast2_branch0_0[0:0] \dp_FAST_fast2_branch0_0$next + sync posedge \coresync_clk + update \dp_FAST_fast2_branch0_0 $0\dp_FAST_fast2_branch0_0[0:0] + end + attribute \src "issuer_ls180.v:41462.3-41463.57" + process $proc$issuer_ls180.v:41462$2237 + assign { } { } + assign $0\dp_FAST_fast1_spr0_2[0:0] \dp_FAST_fast1_spr0_2$next + sync posedge \coresync_clk + update \dp_FAST_fast1_spr0_2 $0\dp_FAST_fast1_spr0_2[0:0] + end + attribute \src "issuer_ls180.v:41464.3-41465.59" + process $proc$issuer_ls180.v:41464$2238 + assign { } { } + assign $0\dp_FAST_fast1_trap0_1[0:0] \dp_FAST_fast1_trap0_1$next + sync posedge \coresync_clk + update \dp_FAST_fast1_trap0_1 $0\dp_FAST_fast1_trap0_1[0:0] + end + attribute \src "issuer_ls180.v:41466.3-41467.63" + process $proc$issuer_ls180.v:41466$2239 + assign { } { } + assign $0\dp_FAST_fast1_branch0_0[0:0] \dp_FAST_fast1_branch0_0$next + sync posedge \coresync_clk + update \dp_FAST_fast1_branch0_0 $0\dp_FAST_fast1_branch0_0[0:0] + end + attribute \src "issuer_ls180.v:41468.3-41469.49" + process $proc$issuer_ls180.v:41468$2240 + assign { } { } + assign $0\dp_CR_cr_c_cr0_0[0:0] \dp_CR_cr_c_cr0_0$next + sync posedge \coresync_clk + update \dp_CR_cr_c_cr0_0 $0\dp_CR_cr_c_cr0_0[0:0] + end + attribute \src "issuer_ls180.v:41470.3-41471.49" + process $proc$issuer_ls180.v:41470$2241 + assign { } { } + assign $0\dp_CR_cr_b_cr0_0[0:0] \dp_CR_cr_b_cr0_0$next + sync posedge \coresync_clk + update \dp_CR_cr_b_cr0_0 $0\dp_CR_cr_b_cr0_0[0:0] + end + attribute \src "issuer_ls180.v:41472.3-41473.57" + process $proc$issuer_ls180.v:41472$2242 + assign { } { } + assign $0\dp_CR_cr_a_branch0_1[0:0] \dp_CR_cr_a_branch0_1$next + sync posedge \coresync_clk + update \dp_CR_cr_a_branch0_1 $0\dp_CR_cr_a_branch0_1[0:0] + end + attribute \src "issuer_ls180.v:41474.3-41475.49" + process $proc$issuer_ls180.v:41474$2243 + assign { } { } + assign $0\dp_CR_cr_a_cr0_0[0:0] \dp_CR_cr_a_cr0_0$next + sync posedge \coresync_clk + update \dp_CR_cr_a_cr0_0 $0\dp_CR_cr_a_cr0_0[0:0] + end + attribute \src "issuer_ls180.v:41476.3-41477.55" + process $proc$issuer_ls180.v:41476$2244 + assign { } { } + assign $0\dp_CR_full_cr_cr0_0[0:0] \dp_CR_full_cr_cr0_0$next + sync posedge \coresync_clk + update \dp_CR_full_cr_cr0_0 $0\dp_CR_full_cr_cr0_0[0:0] + end + attribute \src "issuer_ls180.v:41478.3-41479.57" + process $proc$issuer_ls180.v:41478$2245 + assign { } { } + assign $0\dp_XER_xer_ov_spr0_0[0:0] \dp_XER_xer_ov_spr0_0$next + sync posedge \coresync_clk + update \dp_XER_xer_ov_spr0_0 $0\dp_XER_xer_ov_spr0_0[0:0] + end + attribute \src "issuer_ls180.v:41480.3-41481.67" + process $proc$issuer_ls180.v:41480$2246 + assign { } { } + assign $0\dp_XER_xer_ca_shiftrot0_2[0:0] \dp_XER_xer_ca_shiftrot0_2$next + sync posedge \coresync_clk + update \dp_XER_xer_ca_shiftrot0_2 $0\dp_XER_xer_ca_shiftrot0_2[0:0] + end + attribute \src "issuer_ls180.v:41482.3-41483.57" + process $proc$issuer_ls180.v:41482$2247 + assign { } { } + assign $0\dp_XER_xer_ca_spr0_1[0:0] \dp_XER_xer_ca_spr0_1$next + sync posedge \coresync_clk + update \dp_XER_xer_ca_spr0_1 $0\dp_XER_xer_ca_spr0_1[0:0] + end + attribute \src "issuer_ls180.v:41484.3-41485.57" + process $proc$issuer_ls180.v:41484$2248 + assign { } { } + assign $0\dp_XER_xer_ca_alu0_0[0:0] \dp_XER_xer_ca_alu0_0$next + sync posedge \coresync_clk + update \dp_XER_xer_ca_alu0_0 $0\dp_XER_xer_ca_alu0_0[0:0] + end + attribute \src "issuer_ls180.v:41486.3-41487.67" + process $proc$issuer_ls180.v:41486$2249 + assign { } { } + assign $0\dp_XER_xer_so_shiftrot0_5[0:0] \dp_XER_xer_so_shiftrot0_5$next + sync posedge \coresync_clk + update \dp_XER_xer_so_shiftrot0_5 $0\dp_XER_xer_so_shiftrot0_5[0:0] + end + attribute \src "issuer_ls180.v:41488.3-41489.57" + process $proc$issuer_ls180.v:41488$2250 + assign { } { } + assign $0\dp_XER_xer_so_mul0_4[0:0] \dp_XER_xer_so_mul0_4$next + sync posedge \coresync_clk + update \dp_XER_xer_so_mul0_4 $0\dp_XER_xer_so_mul0_4[0:0] + end + attribute \src "issuer_ls180.v:41490.3-41491.57" + process $proc$issuer_ls180.v:41490$2251 + assign { } { } + assign $0\dp_XER_xer_so_div0_3[0:0] \dp_XER_xer_so_div0_3$next + sync posedge \coresync_clk + update \dp_XER_xer_so_div0_3 $0\dp_XER_xer_so_div0_3[0:0] + end + attribute \src "issuer_ls180.v:41492.3-41493.57" + process $proc$issuer_ls180.v:41492$2252 + assign { } { } + assign $0\dp_XER_xer_so_spr0_2[0:0] \dp_XER_xer_so_spr0_2$next + sync posedge \coresync_clk + update \dp_XER_xer_so_spr0_2 $0\dp_XER_xer_so_spr0_2[0:0] + end + attribute \src "issuer_ls180.v:41494.3-41495.65" + process $proc$issuer_ls180.v:41494$2253 + assign { } { } + assign $0\dp_XER_xer_so_logical0_1[0:0] \dp_XER_xer_so_logical0_1$next + sync posedge \coresync_clk + update \dp_XER_xer_so_logical0_1 $0\dp_XER_xer_so_logical0_1[0:0] + end + attribute \src "issuer_ls180.v:41496.3-41497.57" + process $proc$issuer_ls180.v:41496$2254 + assign { } { } + assign $0\dp_XER_xer_so_alu0_0[0:0] \dp_XER_xer_so_alu0_0$next + sync posedge \coresync_clk + update \dp_XER_xer_so_alu0_0 $0\dp_XER_xer_so_alu0_0[0:0] + end + attribute \src "issuer_ls180.v:41498.3-41499.51" + process $proc$issuer_ls180.v:41498$2255 + assign { } { } + assign $0\dp_INT_rc_ldst0_1[0:0] \dp_INT_rc_ldst0_1$next + sync posedge \coresync_clk + update \dp_INT_rc_ldst0_1 $0\dp_INT_rc_ldst0_1[0:0] + end + attribute \src "issuer_ls180.v:41500.3-41501.59" + process $proc$issuer_ls180.v:41500$2256 + assign { } { } + assign $0\dp_INT_rc_shiftrot0_0[0:0] \dp_INT_rc_shiftrot0_0$next + sync posedge \coresync_clk + update \dp_INT_rc_shiftrot0_0 $0\dp_INT_rc_shiftrot0_0[0:0] + end + attribute \src "issuer_ls180.v:41502.3-41503.51" + process $proc$issuer_ls180.v:41502$2257 + assign { } { } + assign $0\dp_INT_rb_ldst0_7[0:0] \dp_INT_rb_ldst0_7$next + sync posedge \coresync_clk + update \dp_INT_rb_ldst0_7 $0\dp_INT_rb_ldst0_7[0:0] + end + attribute \src "issuer_ls180.v:41504.3-41505.59" + process $proc$issuer_ls180.v:41504$2258 + assign { } { } + assign $0\dp_INT_rb_shiftrot0_6[0:0] \dp_INT_rb_shiftrot0_6$next + sync posedge \coresync_clk + update \dp_INT_rb_shiftrot0_6 $0\dp_INT_rb_shiftrot0_6[0:0] + end + attribute \src "issuer_ls180.v:41506.3-41507.49" + process $proc$issuer_ls180.v:41506$2259 + assign { } { } + assign $0\dp_INT_rb_mul0_5[0:0] \dp_INT_rb_mul0_5$next + sync posedge \coresync_clk + update \dp_INT_rb_mul0_5 $0\dp_INT_rb_mul0_5[0:0] + end + attribute \src "issuer_ls180.v:41508.3-41509.49" + process $proc$issuer_ls180.v:41508$2260 + assign { } { } + assign $0\dp_INT_rb_div0_4[0:0] \dp_INT_rb_div0_4$next + sync posedge \coresync_clk + update \dp_INT_rb_div0_4 $0\dp_INT_rb_div0_4[0:0] + end + attribute \src "issuer_ls180.v:41510.3-41511.57" + process $proc$issuer_ls180.v:41510$2261 + assign { } { } + assign $0\dp_INT_rb_logical0_3[0:0] \dp_INT_rb_logical0_3$next + sync posedge \coresync_clk + update \dp_INT_rb_logical0_3 $0\dp_INT_rb_logical0_3[0:0] + end + attribute \src "issuer_ls180.v:41512.3-41513.51" + process $proc$issuer_ls180.v:41512$2262 + assign { } { } + assign $0\dp_INT_rb_trap0_2[0:0] \dp_INT_rb_trap0_2$next + sync posedge \coresync_clk + update \dp_INT_rb_trap0_2 $0\dp_INT_rb_trap0_2[0:0] + end + attribute \src "issuer_ls180.v:41514.3-41515.47" + process $proc$issuer_ls180.v:41514$2263 + assign { } { } + assign $0\dp_INT_rb_cr0_1[0:0] \dp_INT_rb_cr0_1$next + sync posedge \coresync_clk + update \dp_INT_rb_cr0_1 $0\dp_INT_rb_cr0_1[0:0] + end + attribute \src "issuer_ls180.v:41516.3-41517.49" + process $proc$issuer_ls180.v:41516$2264 + assign { } { } + assign $0\dp_INT_rb_alu0_0[0:0] \dp_INT_rb_alu0_0$next + sync posedge \coresync_clk + update \dp_INT_rb_alu0_0 $0\dp_INT_rb_alu0_0[0:0] + end + attribute \src "issuer_ls180.v:41518.3-41519.51" + process $proc$issuer_ls180.v:41518$2265 + assign { } { } + assign $0\dp_INT_ra_ldst0_8[0:0] \dp_INT_ra_ldst0_8$next + sync posedge \coresync_clk + update \dp_INT_ra_ldst0_8 $0\dp_INT_ra_ldst0_8[0:0] + end + attribute \src "issuer_ls180.v:41520.3-41521.59" + process $proc$issuer_ls180.v:41520$2266 + assign { } { } + assign $0\dp_INT_ra_shiftrot0_7[0:0] \dp_INT_ra_shiftrot0_7$next + sync posedge \coresync_clk + update \dp_INT_ra_shiftrot0_7 $0\dp_INT_ra_shiftrot0_7[0:0] + end + attribute \src "issuer_ls180.v:41522.3-41523.49" + process $proc$issuer_ls180.v:41522$2267 + assign { } { } + assign $0\dp_INT_ra_mul0_6[0:0] \dp_INT_ra_mul0_6$next + sync posedge \coresync_clk + update \dp_INT_ra_mul0_6 $0\dp_INT_ra_mul0_6[0:0] + end + attribute \src "issuer_ls180.v:41524.3-41525.49" + process $proc$issuer_ls180.v:41524$2268 + assign { } { } + assign $0\dp_INT_ra_div0_5[0:0] \dp_INT_ra_div0_5$next + sync posedge \coresync_clk + update \dp_INT_ra_div0_5 $0\dp_INT_ra_div0_5[0:0] + end + attribute \src "issuer_ls180.v:41526.3-41527.49" + process $proc$issuer_ls180.v:41526$2269 + assign { } { } + assign $0\dp_INT_ra_spr0_4[0:0] \dp_INT_ra_spr0_4$next + sync posedge \coresync_clk + update \dp_INT_ra_spr0_4 $0\dp_INT_ra_spr0_4[0:0] + end + attribute \src "issuer_ls180.v:41528.3-41529.57" + process $proc$issuer_ls180.v:41528$2270 + assign { } { } + assign $0\dp_INT_ra_logical0_3[0:0] \dp_INT_ra_logical0_3$next + sync posedge \coresync_clk + update \dp_INT_ra_logical0_3 $0\dp_INT_ra_logical0_3[0:0] + end + attribute \src "issuer_ls180.v:41530.3-41531.51" + process $proc$issuer_ls180.v:41530$2271 + assign { } { } + assign $0\dp_INT_ra_trap0_2[0:0] \dp_INT_ra_trap0_2$next + sync posedge \coresync_clk + update \dp_INT_ra_trap0_2 $0\dp_INT_ra_trap0_2[0:0] + end + attribute \src "issuer_ls180.v:41532.3-41533.47" + process $proc$issuer_ls180.v:41532$2272 + assign { } { } + assign $0\dp_INT_ra_cr0_1[0:0] \dp_INT_ra_cr0_1$next + sync posedge \coresync_clk + update \dp_INT_ra_cr0_1 $0\dp_INT_ra_cr0_1[0:0] + end + attribute \src "issuer_ls180.v:41534.3-41535.49" + process $proc$issuer_ls180.v:41534$2273 + assign { } { } + assign $0\dp_INT_ra_alu0_0[0:0] \dp_INT_ra_alu0_0$next + sync posedge \coresync_clk + update \dp_INT_ra_alu0_0 $0\dp_INT_ra_alu0_0[0:0] + end + attribute \src "issuer_ls180.v:41536.3-41537.49" + process $proc$issuer_ls180.v:41536$2274 + assign { } { } + assign $0\core_terminate_o[0:0] \core_terminate_o$next + sync posedge \coresync_clk + update \core_terminate_o $0\core_terminate_o[0:0] + end + attribute \src "issuer_ls180.v:41538.3-41539.31" + process $proc$issuer_ls180.v:41538$2275 + assign { } { } + assign $0\counter[1:0] \counter$next + sync posedge \coresync_clk + update \counter $0\counter[1:0] + end + attribute \src "issuer_ls180.v:42251.3-42279.6" + process $proc$issuer_ls180.v:42251$2276 + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_spr0__is_32bit[0:0] $1\fus_oper_i_alu_spr0__is_32bit[0:0] + attribute \src "issuer_ls180.v:42252.5-42252.29" + switch \initial + attribute \src "issuer_ls180.v:42252.9-42252.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" + switch \ivalid_i + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_alu_spr0__is_32bit[0:0] $2\fus_oper_i_alu_spr0__is_32bit[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" + switch \core_core_insn_type + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_spr0__is_32bit[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_spr0__is_32bit[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_alu_spr0__is_32bit[0:0] $3\fus_oper_i_alu_spr0__is_32bit[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" + switch \fu_enable [5] + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_alu_spr0__is_32bit[0:0] \dec_SPR_SPR_SPR__is_32bit + case + assign $3\fus_oper_i_alu_spr0__is_32bit[0:0] 1'0 + end + end + case + assign $1\fus_oper_i_alu_spr0__is_32bit[0:0] 1'0 + end + sync always + update \fus_oper_i_alu_spr0__is_32bit $0\fus_oper_i_alu_spr0__is_32bit[0:0] + end + attribute \src "issuer_ls180.v:42280.3-42308.6" + process $proc$issuer_ls180.v:42280$2277 + assign { } { } + assign { } { } + assign $0\fus_cu_issue_i$16[0:0]$2278 $1\fus_cu_issue_i$16[0:0]$2279 + attribute \src "issuer_ls180.v:42281.5-42281.29" + switch \initial + attribute \src "issuer_ls180.v:42281.9-42281.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" + switch \ivalid_i + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_cu_issue_i$16[0:0]$2279 $2\fus_cu_issue_i$16[0:0]$2280 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" + switch \core_core_insn_type + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'0000101 + assign $2\fus_cu_issue_i$16[0:0]$2280 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'0000001 + assign $2\fus_cu_issue_i$16[0:0]$2280 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case + assign { } { } + assign $2\fus_cu_issue_i$16[0:0]$2280 $3\fus_cu_issue_i$16[0:0]$2281 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" + switch \fu_enable [5] + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_cu_issue_i$16[0:0]$2281 \issue_i + case + assign $3\fus_cu_issue_i$16[0:0]$2281 1'0 + end + end + case + assign $1\fus_cu_issue_i$16[0:0]$2279 1'0 + end + sync always + update \fus_cu_issue_i$16 $0\fus_cu_issue_i$16[0:0]$2278 + end + attribute \src "issuer_ls180.v:42309.3-42337.6" + process $proc$issuer_ls180.v:42309$2282 + assign { } { } + assign { } { } + assign $0\fus_cu_rdmaskn_i$18[5:0]$2283 $1\fus_cu_rdmaskn_i$18[5:0]$2284 + attribute \src "issuer_ls180.v:42310.5-42310.29" + switch \initial + attribute \src "issuer_ls180.v:42310.9-42310.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" + switch \ivalid_i + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_cu_rdmaskn_i$18[5:0]$2284 $2\fus_cu_rdmaskn_i$18[5:0]$2285 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" + switch \core_core_insn_type + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'0000101 + assign $2\fus_cu_rdmaskn_i$18[5:0]$2285 6'000000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'0000001 + assign $2\fus_cu_rdmaskn_i$18[5:0]$2285 6'000000 + attribute \src "issuer_ls180.v:0.0-0.0" + case + assign { } { } + assign $2\fus_cu_rdmaskn_i$18[5:0]$2285 $3\fus_cu_rdmaskn_i$18[5:0]$2286 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" + switch \fu_enable [5] + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_cu_rdmaskn_i$18[5:0]$2286 \$249 + case + assign $3\fus_cu_rdmaskn_i$18[5:0]$2286 6'000000 + end + end + case + assign $1\fus_cu_rdmaskn_i$18[5:0]$2284 6'000000 + end + sync always + update \fus_cu_rdmaskn_i$18 $0\fus_cu_rdmaskn_i$18[5:0]$2283 + end + attribute \src "issuer_ls180.v:42338.3-42366.6" + process $proc$issuer_ls180.v:42338$2287 + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_div0__insn_type[6:0] $1\fus_oper_i_alu_div0__insn_type[6:0] + attribute \src "issuer_ls180.v:42339.5-42339.29" + switch \initial + attribute \src "issuer_ls180.v:42339.9-42339.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" + switch \ivalid_i + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_alu_div0__insn_type[6:0] $2\fus_oper_i_alu_div0__insn_type[6:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" + switch \core_core_insn_type + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_div0__insn_type[6:0] 7'0000000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_div0__insn_type[6:0] 7'0000000 + attribute \src "issuer_ls180.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_alu_div0__insn_type[6:0] $3\fus_oper_i_alu_div0__insn_type[6:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" + switch \fu_enable [6] + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_alu_div0__insn_type[6:0] \dec_DIV_DIV_DIV__insn_type + case + assign $3\fus_oper_i_alu_div0__insn_type[6:0] 7'0000000 + end + end + case + assign $1\fus_oper_i_alu_div0__insn_type[6:0] 7'0000000 + end + sync always + update \fus_oper_i_alu_div0__insn_type $0\fus_oper_i_alu_div0__insn_type[6:0] + end + attribute \src "issuer_ls180.v:42367.3-42395.6" + process $proc$issuer_ls180.v:42367$2288 + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_div0__fn_unit[11:0] $1\fus_oper_i_alu_div0__fn_unit[11:0] + attribute \src "issuer_ls180.v:42368.5-42368.29" + switch \initial + attribute \src "issuer_ls180.v:42368.9-42368.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" + switch \ivalid_i + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_alu_div0__fn_unit[11:0] $2\fus_oper_i_alu_div0__fn_unit[11:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" + switch \core_core_insn_type + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_div0__fn_unit[11:0] 12'000000000000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_div0__fn_unit[11:0] 12'000000000000 + attribute \src "issuer_ls180.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_alu_div0__fn_unit[11:0] $3\fus_oper_i_alu_div0__fn_unit[11:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" + switch \fu_enable [6] + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_alu_div0__fn_unit[11:0] \dec_DIV_DIV_DIV__fn_unit + case + assign $3\fus_oper_i_alu_div0__fn_unit[11:0] 12'000000000000 + end + end + case + assign $1\fus_oper_i_alu_div0__fn_unit[11:0] 12'000000000000 + end + sync always + update \fus_oper_i_alu_div0__fn_unit $0\fus_oper_i_alu_div0__fn_unit[11:0] + end + attribute \src "issuer_ls180.v:42396.3-42425.6" + process $proc$issuer_ls180.v:42396$2289 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_div0__imm_data__data[63:0] $1\fus_oper_i_alu_div0__imm_data__data[63:0] + assign $0\fus_oper_i_alu_div0__imm_data__ok[0:0] $1\fus_oper_i_alu_div0__imm_data__ok[0:0] + attribute \src "issuer_ls180.v:42397.5-42397.29" + switch \initial + attribute \src "issuer_ls180.v:42397.9-42397.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" + switch \ivalid_i + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign $1\fus_oper_i_alu_div0__imm_data__data[63:0] $2\fus_oper_i_alu_div0__imm_data__data[63:0] + assign $1\fus_oper_i_alu_div0__imm_data__ok[0:0] $2\fus_oper_i_alu_div0__imm_data__ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" + switch \core_core_insn_type + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_div0__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\fus_oper_i_alu_div0__imm_data__ok[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_div0__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\fus_oper_i_alu_div0__imm_data__ok[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case + assign { } { } + assign { } { } + assign $2\fus_oper_i_alu_div0__imm_data__data[63:0] $3\fus_oper_i_alu_div0__imm_data__data[63:0] + assign $2\fus_oper_i_alu_div0__imm_data__ok[0:0] $3\fus_oper_i_alu_div0__imm_data__ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" + switch \fu_enable [6] + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $3\fus_oper_i_alu_div0__imm_data__ok[0:0] $3\fus_oper_i_alu_div0__imm_data__data[63:0] } { \dec_DIV_DIV_DIV__imm_data__ok \dec_DIV_DIV_DIV__imm_data__data } + case + assign $3\fus_oper_i_alu_div0__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $3\fus_oper_i_alu_div0__imm_data__ok[0:0] 1'0 + end + end + case + assign $1\fus_oper_i_alu_div0__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\fus_oper_i_alu_div0__imm_data__ok[0:0] 1'0 + end + sync always + update \fus_oper_i_alu_div0__imm_data__data $0\fus_oper_i_alu_div0__imm_data__data[63:0] + update \fus_oper_i_alu_div0__imm_data__ok $0\fus_oper_i_alu_div0__imm_data__ok[0:0] + end + attribute \src "issuer_ls180.v:42426.3-42455.6" + process $proc$issuer_ls180.v:42426$2290 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_div0__rc__ok[0:0] $1\fus_oper_i_alu_div0__rc__ok[0:0] + assign $0\fus_oper_i_alu_div0__rc__rc[0:0] $1\fus_oper_i_alu_div0__rc__rc[0:0] + attribute \src "issuer_ls180.v:42427.5-42427.29" + switch \initial + attribute \src "issuer_ls180.v:42427.9-42427.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" + switch \ivalid_i + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign $1\fus_oper_i_alu_div0__rc__ok[0:0] $2\fus_oper_i_alu_div0__rc__ok[0:0] + assign $1\fus_oper_i_alu_div0__rc__rc[0:0] $2\fus_oper_i_alu_div0__rc__rc[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" + switch \core_core_insn_type + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_div0__rc__ok[0:0] 1'0 + assign $2\fus_oper_i_alu_div0__rc__rc[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_div0__rc__ok[0:0] 1'0 + assign $2\fus_oper_i_alu_div0__rc__rc[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case + assign { } { } + assign { } { } + assign $2\fus_oper_i_alu_div0__rc__ok[0:0] $3\fus_oper_i_alu_div0__rc__ok[0:0] + assign $2\fus_oper_i_alu_div0__rc__rc[0:0] $3\fus_oper_i_alu_div0__rc__rc[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" + switch \fu_enable [6] + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $3\fus_oper_i_alu_div0__rc__ok[0:0] $3\fus_oper_i_alu_div0__rc__rc[0:0] } { \dec_DIV_DIV_DIV__rc__ok \dec_DIV_DIV_DIV__rc__rc } + case + assign $3\fus_oper_i_alu_div0__rc__ok[0:0] 1'0 + assign $3\fus_oper_i_alu_div0__rc__rc[0:0] 1'0 + end + end + case + assign $1\fus_oper_i_alu_div0__rc__ok[0:0] 1'0 + assign $1\fus_oper_i_alu_div0__rc__rc[0:0] 1'0 + end + sync always + update \fus_oper_i_alu_div0__rc__ok $0\fus_oper_i_alu_div0__rc__ok[0:0] + update \fus_oper_i_alu_div0__rc__rc $0\fus_oper_i_alu_div0__rc__rc[0:0] + end + attribute \src "issuer_ls180.v:42456.3-42485.6" + process $proc$issuer_ls180.v:42456$2291 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_div0__oe__oe[0:0] $1\fus_oper_i_alu_div0__oe__oe[0:0] + assign $0\fus_oper_i_alu_div0__oe__ok[0:0] $1\fus_oper_i_alu_div0__oe__ok[0:0] + attribute \src "issuer_ls180.v:42457.5-42457.29" + switch \initial + attribute \src "issuer_ls180.v:42457.9-42457.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" + switch \ivalid_i + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign $1\fus_oper_i_alu_div0__oe__oe[0:0] $2\fus_oper_i_alu_div0__oe__oe[0:0] + assign $1\fus_oper_i_alu_div0__oe__ok[0:0] $2\fus_oper_i_alu_div0__oe__ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" + switch \core_core_insn_type + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_div0__oe__oe[0:0] 1'0 + assign $2\fus_oper_i_alu_div0__oe__ok[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_div0__oe__oe[0:0] 1'0 + assign $2\fus_oper_i_alu_div0__oe__ok[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case + assign { } { } + assign { } { } + assign $2\fus_oper_i_alu_div0__oe__oe[0:0] $3\fus_oper_i_alu_div0__oe__oe[0:0] + assign $2\fus_oper_i_alu_div0__oe__ok[0:0] $3\fus_oper_i_alu_div0__oe__ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" + switch \fu_enable [6] + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $3\fus_oper_i_alu_div0__oe__ok[0:0] $3\fus_oper_i_alu_div0__oe__oe[0:0] } { \dec_DIV_DIV_DIV__oe__ok \dec_DIV_DIV_DIV__oe__oe } + case + assign $3\fus_oper_i_alu_div0__oe__oe[0:0] 1'0 + assign $3\fus_oper_i_alu_div0__oe__ok[0:0] 1'0 + end + end + case + assign $1\fus_oper_i_alu_div0__oe__oe[0:0] 1'0 + assign $1\fus_oper_i_alu_div0__oe__ok[0:0] 1'0 + end + sync always + update \fus_oper_i_alu_div0__oe__oe $0\fus_oper_i_alu_div0__oe__oe[0:0] + update \fus_oper_i_alu_div0__oe__ok $0\fus_oper_i_alu_div0__oe__ok[0:0] + end + attribute \src "issuer_ls180.v:42486.3-42514.6" + process $proc$issuer_ls180.v:42486$2292 + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_div0__invert_in[0:0] $1\fus_oper_i_alu_div0__invert_in[0:0] + attribute \src "issuer_ls180.v:42487.5-42487.29" + switch \initial + attribute \src "issuer_ls180.v:42487.9-42487.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" + switch \ivalid_i + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_alu_div0__invert_in[0:0] $2\fus_oper_i_alu_div0__invert_in[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" + switch \core_core_insn_type + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_div0__invert_in[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_div0__invert_in[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_alu_div0__invert_in[0:0] $3\fus_oper_i_alu_div0__invert_in[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" + switch \fu_enable [6] + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_alu_div0__invert_in[0:0] \dec_DIV_DIV_DIV__invert_in + case + assign $3\fus_oper_i_alu_div0__invert_in[0:0] 1'0 + end + end + case + assign $1\fus_oper_i_alu_div0__invert_in[0:0] 1'0 + end + sync always + update \fus_oper_i_alu_div0__invert_in $0\fus_oper_i_alu_div0__invert_in[0:0] + end + attribute \src "issuer_ls180.v:42515.3-42543.6" + process $proc$issuer_ls180.v:42515$2293 + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_div0__zero_a[0:0] $1\fus_oper_i_alu_div0__zero_a[0:0] + attribute \src "issuer_ls180.v:42516.5-42516.29" + switch \initial + attribute \src "issuer_ls180.v:42516.9-42516.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" + switch \ivalid_i + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_alu_div0__zero_a[0:0] $2\fus_oper_i_alu_div0__zero_a[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" + switch \core_core_insn_type + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_div0__zero_a[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_div0__zero_a[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_alu_div0__zero_a[0:0] $3\fus_oper_i_alu_div0__zero_a[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" + switch \fu_enable [6] + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_alu_div0__zero_a[0:0] \dec_DIV_DIV_DIV__zero_a + case + assign $3\fus_oper_i_alu_div0__zero_a[0:0] 1'0 + end + end + case + assign $1\fus_oper_i_alu_div0__zero_a[0:0] 1'0 + end + sync always + update \fus_oper_i_alu_div0__zero_a $0\fus_oper_i_alu_div0__zero_a[0:0] + end + attribute \src "issuer_ls180.v:42544.3-42572.6" + process $proc$issuer_ls180.v:42544$2294 + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_div0__input_carry[1:0] $1\fus_oper_i_alu_div0__input_carry[1:0] + attribute \src "issuer_ls180.v:42545.5-42545.29" + switch \initial + attribute \src "issuer_ls180.v:42545.9-42545.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" + switch \ivalid_i + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_alu_div0__input_carry[1:0] $2\fus_oper_i_alu_div0__input_carry[1:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" + switch \core_core_insn_type + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_div0__input_carry[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_div0__input_carry[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_alu_div0__input_carry[1:0] $3\fus_oper_i_alu_div0__input_carry[1:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" + switch \fu_enable [6] + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_alu_div0__input_carry[1:0] \dec_DIV_DIV_DIV__input_carry + case + assign $3\fus_oper_i_alu_div0__input_carry[1:0] 2'00 + end + end + case + assign $1\fus_oper_i_alu_div0__input_carry[1:0] 2'00 + end + sync always + update \fus_oper_i_alu_div0__input_carry $0\fus_oper_i_alu_div0__input_carry[1:0] + end + attribute \src "issuer_ls180.v:42573.3-42601.6" + process $proc$issuer_ls180.v:42573$2295 + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_div0__invert_out[0:0] $1\fus_oper_i_alu_div0__invert_out[0:0] + attribute \src "issuer_ls180.v:42574.5-42574.29" + switch \initial + attribute \src "issuer_ls180.v:42574.9-42574.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" + switch \ivalid_i + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_alu_div0__invert_out[0:0] $2\fus_oper_i_alu_div0__invert_out[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" + switch \core_core_insn_type + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_div0__invert_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_div0__invert_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_alu_div0__invert_out[0:0] $3\fus_oper_i_alu_div0__invert_out[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" + switch \fu_enable [6] + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_alu_div0__invert_out[0:0] \dec_DIV_DIV_DIV__invert_out + case + assign $3\fus_oper_i_alu_div0__invert_out[0:0] 1'0 + end + end + case + assign $1\fus_oper_i_alu_div0__invert_out[0:0] 1'0 + end + sync always + update \fus_oper_i_alu_div0__invert_out $0\fus_oper_i_alu_div0__invert_out[0:0] + end + attribute \src "issuer_ls180.v:42602.3-42630.6" + process $proc$issuer_ls180.v:42602$2296 + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_div0__write_cr0[0:0] $1\fus_oper_i_alu_div0__write_cr0[0:0] + attribute \src "issuer_ls180.v:42603.5-42603.29" + switch \initial + attribute \src "issuer_ls180.v:42603.9-42603.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" + switch \ivalid_i + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_alu_div0__write_cr0[0:0] $2\fus_oper_i_alu_div0__write_cr0[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" + switch \core_core_insn_type + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_div0__write_cr0[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_div0__write_cr0[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_alu_div0__write_cr0[0:0] $3\fus_oper_i_alu_div0__write_cr0[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" + switch \fu_enable [6] + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_alu_div0__write_cr0[0:0] \dec_DIV_DIV_DIV__write_cr0 + case + assign $3\fus_oper_i_alu_div0__write_cr0[0:0] 1'0 + end + end + case + assign $1\fus_oper_i_alu_div0__write_cr0[0:0] 1'0 + end + sync always + update \fus_oper_i_alu_div0__write_cr0 $0\fus_oper_i_alu_div0__write_cr0[0:0] + end + attribute \src "issuer_ls180.v:42631.3-42659.6" + process $proc$issuer_ls180.v:42631$2297 + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_div0__output_carry[0:0] $1\fus_oper_i_alu_div0__output_carry[0:0] + attribute \src "issuer_ls180.v:42632.5-42632.29" + switch \initial + attribute \src "issuer_ls180.v:42632.9-42632.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" + switch \ivalid_i + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_alu_div0__output_carry[0:0] $2\fus_oper_i_alu_div0__output_carry[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" + switch \core_core_insn_type + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_div0__output_carry[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_div0__output_carry[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_alu_div0__output_carry[0:0] $3\fus_oper_i_alu_div0__output_carry[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" + switch \fu_enable [6] + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_alu_div0__output_carry[0:0] \dec_DIV_DIV_DIV__output_carry + case + assign $3\fus_oper_i_alu_div0__output_carry[0:0] 1'0 + end + end + case + assign $1\fus_oper_i_alu_div0__output_carry[0:0] 1'0 + end + sync always + update \fus_oper_i_alu_div0__output_carry $0\fus_oper_i_alu_div0__output_carry[0:0] + end + attribute \src "issuer_ls180.v:42660.3-42688.6" + process $proc$issuer_ls180.v:42660$2298 + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_div0__is_32bit[0:0] $1\fus_oper_i_alu_div0__is_32bit[0:0] + attribute \src "issuer_ls180.v:42661.5-42661.29" + switch \initial + attribute \src "issuer_ls180.v:42661.9-42661.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" + switch \ivalid_i + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_alu_div0__is_32bit[0:0] $2\fus_oper_i_alu_div0__is_32bit[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" + switch \core_core_insn_type + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_div0__is_32bit[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_div0__is_32bit[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_alu_div0__is_32bit[0:0] $3\fus_oper_i_alu_div0__is_32bit[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" + switch \fu_enable [6] + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_alu_div0__is_32bit[0:0] \dec_DIV_DIV_DIV__is_32bit + case + assign $3\fus_oper_i_alu_div0__is_32bit[0:0] 1'0 + end + end + case + assign $1\fus_oper_i_alu_div0__is_32bit[0:0] 1'0 + end + sync always + update \fus_oper_i_alu_div0__is_32bit $0\fus_oper_i_alu_div0__is_32bit[0:0] + end + attribute \src "issuer_ls180.v:42689.3-42717.6" + process $proc$issuer_ls180.v:42689$2299 + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_div0__is_signed[0:0] $1\fus_oper_i_alu_div0__is_signed[0:0] + attribute \src "issuer_ls180.v:42690.5-42690.29" + switch \initial + attribute \src "issuer_ls180.v:42690.9-42690.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" + switch \ivalid_i + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_alu_div0__is_signed[0:0] $2\fus_oper_i_alu_div0__is_signed[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" + switch \core_core_insn_type + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_div0__is_signed[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_div0__is_signed[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_alu_div0__is_signed[0:0] $3\fus_oper_i_alu_div0__is_signed[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" + switch \fu_enable [6] + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_alu_div0__is_signed[0:0] \dec_DIV_DIV_DIV__is_signed + case + assign $3\fus_oper_i_alu_div0__is_signed[0:0] 1'0 + end + end + case + assign $1\fus_oper_i_alu_div0__is_signed[0:0] 1'0 + end + sync always + update \fus_oper_i_alu_div0__is_signed $0\fus_oper_i_alu_div0__is_signed[0:0] + end + attribute \src "issuer_ls180.v:42718.3-42746.6" + process $proc$issuer_ls180.v:42718$2300 + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_div0__data_len[3:0] $1\fus_oper_i_alu_div0__data_len[3:0] + attribute \src "issuer_ls180.v:42719.5-42719.29" + switch \initial + attribute \src "issuer_ls180.v:42719.9-42719.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" + switch \ivalid_i + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_alu_div0__data_len[3:0] $2\fus_oper_i_alu_div0__data_len[3:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" + switch \core_core_insn_type + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_div0__data_len[3:0] 4'0000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_div0__data_len[3:0] 4'0000 + attribute \src "issuer_ls180.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_alu_div0__data_len[3:0] $3\fus_oper_i_alu_div0__data_len[3:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" + switch \fu_enable [6] + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_alu_div0__data_len[3:0] \dec_DIV_DIV_DIV__data_len + case + assign $3\fus_oper_i_alu_div0__data_len[3:0] 4'0000 + end + end + case + assign $1\fus_oper_i_alu_div0__data_len[3:0] 4'0000 + end + sync always + update \fus_oper_i_alu_div0__data_len $0\fus_oper_i_alu_div0__data_len[3:0] + end + attribute \src "issuer_ls180.v:42747.3-42775.6" + process $proc$issuer_ls180.v:42747$2301 + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_div0__insn[31:0] $1\fus_oper_i_alu_div0__insn[31:0] + attribute \src "issuer_ls180.v:42748.5-42748.29" + switch \initial + attribute \src "issuer_ls180.v:42748.9-42748.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" + switch \ivalid_i + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_alu_div0__insn[31:0] $2\fus_oper_i_alu_div0__insn[31:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" + switch \core_core_insn_type + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_div0__insn[31:0] 0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_div0__insn[31:0] 0 + attribute \src "issuer_ls180.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_alu_div0__insn[31:0] $3\fus_oper_i_alu_div0__insn[31:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" + switch \fu_enable [6] + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_alu_div0__insn[31:0] \dec_DIV_DIV_DIV__insn + case + assign $3\fus_oper_i_alu_div0__insn[31:0] 0 + end + end + case + assign $1\fus_oper_i_alu_div0__insn[31:0] 0 + end + sync always + update \fus_oper_i_alu_div0__insn $0\fus_oper_i_alu_div0__insn[31:0] + end + attribute \src "issuer_ls180.v:42776.3-42804.6" + process $proc$issuer_ls180.v:42776$2302 + assign { } { } + assign { } { } + assign $0\fus_cu_issue_i$19[0:0]$2303 $1\fus_cu_issue_i$19[0:0]$2304 + attribute \src "issuer_ls180.v:42777.5-42777.29" + switch \initial + attribute \src "issuer_ls180.v:42777.9-42777.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" + switch \ivalid_i + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_cu_issue_i$19[0:0]$2304 $2\fus_cu_issue_i$19[0:0]$2305 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" + switch \core_core_insn_type + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'0000101 + assign $2\fus_cu_issue_i$19[0:0]$2305 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'0000001 + assign $2\fus_cu_issue_i$19[0:0]$2305 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case + assign { } { } + assign $2\fus_cu_issue_i$19[0:0]$2305 $3\fus_cu_issue_i$19[0:0]$2306 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" + switch \fu_enable [6] + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_cu_issue_i$19[0:0]$2306 \issue_i + case + assign $3\fus_cu_issue_i$19[0:0]$2306 1'0 + end + end + case + assign $1\fus_cu_issue_i$19[0:0]$2304 1'0 + end + sync always + update \fus_cu_issue_i$19 $0\fus_cu_issue_i$19[0:0]$2303 + end + attribute \src "issuer_ls180.v:42805.3-42833.6" + process $proc$issuer_ls180.v:42805$2307 + assign { } { } + assign { } { } + assign $0\fus_cu_rdmaskn_i$21[2:0]$2308 $1\fus_cu_rdmaskn_i$21[2:0]$2309 + attribute \src "issuer_ls180.v:42806.5-42806.29" + switch \initial + attribute \src "issuer_ls180.v:42806.9-42806.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" + switch \ivalid_i + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_cu_rdmaskn_i$21[2:0]$2309 $2\fus_cu_rdmaskn_i$21[2:0]$2310 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" + switch \core_core_insn_type + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'0000101 + assign $2\fus_cu_rdmaskn_i$21[2:0]$2310 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'0000001 + assign $2\fus_cu_rdmaskn_i$21[2:0]$2310 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case + assign { } { } + assign $2\fus_cu_rdmaskn_i$21[2:0]$2310 $3\fus_cu_rdmaskn_i$21[2:0]$2311 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" + switch \fu_enable [6] + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_cu_rdmaskn_i$21[2:0]$2311 \$279 + case + assign $3\fus_cu_rdmaskn_i$21[2:0]$2311 3'000 + end + end + case + assign $1\fus_cu_rdmaskn_i$21[2:0]$2309 3'000 + end + sync always + update \fus_cu_rdmaskn_i$21 $0\fus_cu_rdmaskn_i$21[2:0]$2308 + end + attribute \src "issuer_ls180.v:42834.3-42862.6" + process $proc$issuer_ls180.v:42834$2312 + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_mul0__insn_type[6:0] $1\fus_oper_i_alu_mul0__insn_type[6:0] + attribute \src "issuer_ls180.v:42835.5-42835.29" + switch \initial + attribute \src "issuer_ls180.v:42835.9-42835.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" + switch \ivalid_i + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_alu_mul0__insn_type[6:0] $2\fus_oper_i_alu_mul0__insn_type[6:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" + switch \core_core_insn_type + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_mul0__insn_type[6:0] 7'0000000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_mul0__insn_type[6:0] 7'0000000 + attribute \src "issuer_ls180.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_alu_mul0__insn_type[6:0] $3\fus_oper_i_alu_mul0__insn_type[6:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" + switch \fu_enable [7] + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_alu_mul0__insn_type[6:0] \dec_MUL_MUL_MUL__insn_type + case + assign $3\fus_oper_i_alu_mul0__insn_type[6:0] 7'0000000 + end + end + case + assign $1\fus_oper_i_alu_mul0__insn_type[6:0] 7'0000000 + end + sync always + update \fus_oper_i_alu_mul0__insn_type $0\fus_oper_i_alu_mul0__insn_type[6:0] + end + attribute \src "issuer_ls180.v:42863.3-42891.6" + process $proc$issuer_ls180.v:42863$2313 + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_mul0__fn_unit[11:0] $1\fus_oper_i_alu_mul0__fn_unit[11:0] + attribute \src "issuer_ls180.v:42864.5-42864.29" + switch \initial + attribute \src "issuer_ls180.v:42864.9-42864.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" + switch \ivalid_i + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_alu_mul0__fn_unit[11:0] $2\fus_oper_i_alu_mul0__fn_unit[11:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" + switch \core_core_insn_type + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_mul0__fn_unit[11:0] 12'000000000000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_mul0__fn_unit[11:0] 12'000000000000 + attribute \src "issuer_ls180.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_alu_mul0__fn_unit[11:0] $3\fus_oper_i_alu_mul0__fn_unit[11:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" + switch \fu_enable [7] + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_alu_mul0__fn_unit[11:0] \dec_MUL_MUL_MUL__fn_unit + case + assign $3\fus_oper_i_alu_mul0__fn_unit[11:0] 12'000000000000 + end + end + case + assign $1\fus_oper_i_alu_mul0__fn_unit[11:0] 12'000000000000 + end + sync always + update \fus_oper_i_alu_mul0__fn_unit $0\fus_oper_i_alu_mul0__fn_unit[11:0] + end + attribute \src "issuer_ls180.v:42892.3-42921.6" + process $proc$issuer_ls180.v:42892$2314 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_mul0__imm_data__data[63:0] $1\fus_oper_i_alu_mul0__imm_data__data[63:0] + assign $0\fus_oper_i_alu_mul0__imm_data__ok[0:0] $1\fus_oper_i_alu_mul0__imm_data__ok[0:0] + attribute \src "issuer_ls180.v:42893.5-42893.29" + switch \initial + attribute \src "issuer_ls180.v:42893.9-42893.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" + switch \ivalid_i + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign $1\fus_oper_i_alu_mul0__imm_data__data[63:0] $2\fus_oper_i_alu_mul0__imm_data__data[63:0] + assign $1\fus_oper_i_alu_mul0__imm_data__ok[0:0] $2\fus_oper_i_alu_mul0__imm_data__ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" + switch \core_core_insn_type + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_mul0__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\fus_oper_i_alu_mul0__imm_data__ok[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_mul0__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\fus_oper_i_alu_mul0__imm_data__ok[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case + assign { } { } + assign { } { } + assign $2\fus_oper_i_alu_mul0__imm_data__data[63:0] $3\fus_oper_i_alu_mul0__imm_data__data[63:0] + assign $2\fus_oper_i_alu_mul0__imm_data__ok[0:0] $3\fus_oper_i_alu_mul0__imm_data__ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" + switch \fu_enable [7] + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $3\fus_oper_i_alu_mul0__imm_data__ok[0:0] $3\fus_oper_i_alu_mul0__imm_data__data[63:0] } { \dec_MUL_MUL_MUL__imm_data__ok \dec_MUL_MUL_MUL__imm_data__data } + case + assign $3\fus_oper_i_alu_mul0__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $3\fus_oper_i_alu_mul0__imm_data__ok[0:0] 1'0 + end + end + case + assign $1\fus_oper_i_alu_mul0__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\fus_oper_i_alu_mul0__imm_data__ok[0:0] 1'0 + end + sync always + update \fus_oper_i_alu_mul0__imm_data__data $0\fus_oper_i_alu_mul0__imm_data__data[63:0] + update \fus_oper_i_alu_mul0__imm_data__ok $0\fus_oper_i_alu_mul0__imm_data__ok[0:0] + end + attribute \src "issuer_ls180.v:42922.3-42951.6" + process $proc$issuer_ls180.v:42922$2315 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_mul0__rc__ok[0:0] $1\fus_oper_i_alu_mul0__rc__ok[0:0] + assign $0\fus_oper_i_alu_mul0__rc__rc[0:0] $1\fus_oper_i_alu_mul0__rc__rc[0:0] + attribute \src "issuer_ls180.v:42923.5-42923.29" + switch \initial + attribute \src "issuer_ls180.v:42923.9-42923.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" + switch \ivalid_i + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign $1\fus_oper_i_alu_mul0__rc__ok[0:0] $2\fus_oper_i_alu_mul0__rc__ok[0:0] + assign $1\fus_oper_i_alu_mul0__rc__rc[0:0] $2\fus_oper_i_alu_mul0__rc__rc[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" + switch \core_core_insn_type + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_mul0__rc__ok[0:0] 1'0 + assign $2\fus_oper_i_alu_mul0__rc__rc[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_mul0__rc__ok[0:0] 1'0 + assign $2\fus_oper_i_alu_mul0__rc__rc[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case + assign { } { } + assign { } { } + assign $2\fus_oper_i_alu_mul0__rc__ok[0:0] $3\fus_oper_i_alu_mul0__rc__ok[0:0] + assign $2\fus_oper_i_alu_mul0__rc__rc[0:0] $3\fus_oper_i_alu_mul0__rc__rc[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" + switch \fu_enable [7] + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $3\fus_oper_i_alu_mul0__rc__ok[0:0] $3\fus_oper_i_alu_mul0__rc__rc[0:0] } { \dec_MUL_MUL_MUL__rc__ok \dec_MUL_MUL_MUL__rc__rc } + case + assign $3\fus_oper_i_alu_mul0__rc__ok[0:0] 1'0 + assign $3\fus_oper_i_alu_mul0__rc__rc[0:0] 1'0 + end + end + case + assign $1\fus_oper_i_alu_mul0__rc__ok[0:0] 1'0 + assign $1\fus_oper_i_alu_mul0__rc__rc[0:0] 1'0 + end + sync always + update \fus_oper_i_alu_mul0__rc__ok $0\fus_oper_i_alu_mul0__rc__ok[0:0] + update \fus_oper_i_alu_mul0__rc__rc $0\fus_oper_i_alu_mul0__rc__rc[0:0] + end + attribute \src "issuer_ls180.v:42952.3-42981.6" + process $proc$issuer_ls180.v:42952$2316 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_mul0__oe__oe[0:0] $1\fus_oper_i_alu_mul0__oe__oe[0:0] + assign $0\fus_oper_i_alu_mul0__oe__ok[0:0] $1\fus_oper_i_alu_mul0__oe__ok[0:0] + attribute \src "issuer_ls180.v:42953.5-42953.29" + switch \initial + attribute \src "issuer_ls180.v:42953.9-42953.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" + switch \ivalid_i + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign $1\fus_oper_i_alu_mul0__oe__oe[0:0] $2\fus_oper_i_alu_mul0__oe__oe[0:0] + assign $1\fus_oper_i_alu_mul0__oe__ok[0:0] $2\fus_oper_i_alu_mul0__oe__ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" + switch \core_core_insn_type + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_mul0__oe__oe[0:0] 1'0 + assign $2\fus_oper_i_alu_mul0__oe__ok[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_mul0__oe__oe[0:0] 1'0 + assign $2\fus_oper_i_alu_mul0__oe__ok[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case + assign { } { } + assign { } { } + assign $2\fus_oper_i_alu_mul0__oe__oe[0:0] $3\fus_oper_i_alu_mul0__oe__oe[0:0] + assign $2\fus_oper_i_alu_mul0__oe__ok[0:0] $3\fus_oper_i_alu_mul0__oe__ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" + switch \fu_enable [7] + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $3\fus_oper_i_alu_mul0__oe__ok[0:0] $3\fus_oper_i_alu_mul0__oe__oe[0:0] } { \dec_MUL_MUL_MUL__oe__ok \dec_MUL_MUL_MUL__oe__oe } + case + assign $3\fus_oper_i_alu_mul0__oe__oe[0:0] 1'0 + assign $3\fus_oper_i_alu_mul0__oe__ok[0:0] 1'0 + end + end + case + assign $1\fus_oper_i_alu_mul0__oe__oe[0:0] 1'0 + assign $1\fus_oper_i_alu_mul0__oe__ok[0:0] 1'0 + end + sync always + update \fus_oper_i_alu_mul0__oe__oe $0\fus_oper_i_alu_mul0__oe__oe[0:0] + update \fus_oper_i_alu_mul0__oe__ok $0\fus_oper_i_alu_mul0__oe__ok[0:0] + end + attribute \src "issuer_ls180.v:42982.3-43010.6" + process $proc$issuer_ls180.v:42982$2317 + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_mul0__write_cr0[0:0] $1\fus_oper_i_alu_mul0__write_cr0[0:0] + attribute \src "issuer_ls180.v:42983.5-42983.29" + switch \initial + attribute \src "issuer_ls180.v:42983.9-42983.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" + switch \ivalid_i + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_alu_mul0__write_cr0[0:0] $2\fus_oper_i_alu_mul0__write_cr0[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" + switch \core_core_insn_type + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_mul0__write_cr0[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_mul0__write_cr0[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_alu_mul0__write_cr0[0:0] $3\fus_oper_i_alu_mul0__write_cr0[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" + switch \fu_enable [7] + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_alu_mul0__write_cr0[0:0] \dec_MUL_MUL_MUL__write_cr0 + case + assign $3\fus_oper_i_alu_mul0__write_cr0[0:0] 1'0 + end + end + case + assign $1\fus_oper_i_alu_mul0__write_cr0[0:0] 1'0 + end + sync always + update \fus_oper_i_alu_mul0__write_cr0 $0\fus_oper_i_alu_mul0__write_cr0[0:0] + end + attribute \src "issuer_ls180.v:43011.3-43039.6" + process $proc$issuer_ls180.v:43011$2318 + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_mul0__is_32bit[0:0] $1\fus_oper_i_alu_mul0__is_32bit[0:0] + attribute \src "issuer_ls180.v:43012.5-43012.29" + switch \initial + attribute \src "issuer_ls180.v:43012.9-43012.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" + switch \ivalid_i + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_alu_mul0__is_32bit[0:0] $2\fus_oper_i_alu_mul0__is_32bit[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" + switch \core_core_insn_type + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_mul0__is_32bit[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_mul0__is_32bit[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_alu_mul0__is_32bit[0:0] $3\fus_oper_i_alu_mul0__is_32bit[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" + switch \fu_enable [7] + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_alu_mul0__is_32bit[0:0] \dec_MUL_MUL_MUL__is_32bit + case + assign $3\fus_oper_i_alu_mul0__is_32bit[0:0] 1'0 + end + end + case + assign $1\fus_oper_i_alu_mul0__is_32bit[0:0] 1'0 + end + sync always + update \fus_oper_i_alu_mul0__is_32bit $0\fus_oper_i_alu_mul0__is_32bit[0:0] + end + attribute \src "issuer_ls180.v:43040.3-43068.6" + process $proc$issuer_ls180.v:43040$2319 + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_mul0__is_signed[0:0] $1\fus_oper_i_alu_mul0__is_signed[0:0] + attribute \src "issuer_ls180.v:43041.5-43041.29" + switch \initial + attribute \src "issuer_ls180.v:43041.9-43041.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" + switch \ivalid_i + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_alu_mul0__is_signed[0:0] $2\fus_oper_i_alu_mul0__is_signed[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" + switch \core_core_insn_type + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_mul0__is_signed[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_mul0__is_signed[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_alu_mul0__is_signed[0:0] $3\fus_oper_i_alu_mul0__is_signed[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" + switch \fu_enable [7] + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_alu_mul0__is_signed[0:0] \dec_MUL_MUL_MUL__is_signed + case + assign $3\fus_oper_i_alu_mul0__is_signed[0:0] 1'0 + end + end + case + assign $1\fus_oper_i_alu_mul0__is_signed[0:0] 1'0 + end + sync always + update \fus_oper_i_alu_mul0__is_signed $0\fus_oper_i_alu_mul0__is_signed[0:0] + end + attribute \src "issuer_ls180.v:43069.3-43097.6" + process $proc$issuer_ls180.v:43069$2320 + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_mul0__insn[31:0] $1\fus_oper_i_alu_mul0__insn[31:0] + attribute \src "issuer_ls180.v:43070.5-43070.29" + switch \initial + attribute \src "issuer_ls180.v:43070.9-43070.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" + switch \ivalid_i + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_alu_mul0__insn[31:0] $2\fus_oper_i_alu_mul0__insn[31:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" + switch \core_core_insn_type + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_mul0__insn[31:0] 0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_mul0__insn[31:0] 0 + attribute \src "issuer_ls180.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_alu_mul0__insn[31:0] $3\fus_oper_i_alu_mul0__insn[31:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" + switch \fu_enable [7] + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_alu_mul0__insn[31:0] \dec_MUL_MUL_MUL__insn + case + assign $3\fus_oper_i_alu_mul0__insn[31:0] 0 + end + end + case + assign $1\fus_oper_i_alu_mul0__insn[31:0] 0 + end + sync always + update \fus_oper_i_alu_mul0__insn $0\fus_oper_i_alu_mul0__insn[31:0] + end + attribute \src "issuer_ls180.v:43098.3-43126.6" + process $proc$issuer_ls180.v:43098$2321 + assign { } { } + assign { } { } + assign $0\fus_cu_issue_i$22[0:0]$2322 $1\fus_cu_issue_i$22[0:0]$2323 + attribute \src "issuer_ls180.v:43099.5-43099.29" + switch \initial + attribute \src "issuer_ls180.v:43099.9-43099.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" + switch \ivalid_i + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_cu_issue_i$22[0:0]$2323 $2\fus_cu_issue_i$22[0:0]$2324 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" + switch \core_core_insn_type + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'0000101 + assign $2\fus_cu_issue_i$22[0:0]$2324 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'0000001 + assign $2\fus_cu_issue_i$22[0:0]$2324 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case + assign { } { } + assign $2\fus_cu_issue_i$22[0:0]$2324 $3\fus_cu_issue_i$22[0:0]$2325 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" + switch \fu_enable [7] + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_cu_issue_i$22[0:0]$2325 \issue_i + case + assign $3\fus_cu_issue_i$22[0:0]$2325 1'0 + end + end + case + assign $1\fus_cu_issue_i$22[0:0]$2323 1'0 + end + sync always + update \fus_cu_issue_i$22 $0\fus_cu_issue_i$22[0:0]$2322 + end + attribute \src "issuer_ls180.v:43127.3-43155.6" + process $proc$issuer_ls180.v:43127$2326 + assign { } { } + assign { } { } + assign $0\fus_cu_rdmaskn_i$24[2:0]$2327 $1\fus_cu_rdmaskn_i$24[2:0]$2328 + attribute \src "issuer_ls180.v:43128.5-43128.29" + switch \initial + attribute \src "issuer_ls180.v:43128.9-43128.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" + switch \ivalid_i + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_cu_rdmaskn_i$24[2:0]$2328 $2\fus_cu_rdmaskn_i$24[2:0]$2329 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" + switch \core_core_insn_type + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'0000101 + assign $2\fus_cu_rdmaskn_i$24[2:0]$2329 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'0000001 + assign $2\fus_cu_rdmaskn_i$24[2:0]$2329 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case + assign { } { } + assign $2\fus_cu_rdmaskn_i$24[2:0]$2329 $3\fus_cu_rdmaskn_i$24[2:0]$2330 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" + switch \fu_enable [7] + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_cu_rdmaskn_i$24[2:0]$2330 \$293 + case + assign $3\fus_cu_rdmaskn_i$24[2:0]$2330 3'000 + end + end + case + assign $1\fus_cu_rdmaskn_i$24[2:0]$2328 3'000 + end + sync always + update \fus_cu_rdmaskn_i$24 $0\fus_cu_rdmaskn_i$24[2:0]$2327 + end + attribute \src "issuer_ls180.v:43156.3-43184.6" + process $proc$issuer_ls180.v:43156$2331 + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_shift_rot0__insn_type[6:0] $1\fus_oper_i_alu_shift_rot0__insn_type[6:0] + attribute \src "issuer_ls180.v:43157.5-43157.29" + switch \initial + attribute \src "issuer_ls180.v:43157.9-43157.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" + switch \ivalid_i + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_alu_shift_rot0__insn_type[6:0] $2\fus_oper_i_alu_shift_rot0__insn_type[6:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" + switch \core_core_insn_type + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_shift_rot0__insn_type[6:0] 7'0000000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_shift_rot0__insn_type[6:0] 7'0000000 + attribute \src "issuer_ls180.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_alu_shift_rot0__insn_type[6:0] $3\fus_oper_i_alu_shift_rot0__insn_type[6:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" + switch \fu_enable [8] + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_alu_shift_rot0__insn_type[6:0] \dec_SHIFT_ROT_SHIFT_ROT_SHIFT_ROT__insn_type + case + assign $3\fus_oper_i_alu_shift_rot0__insn_type[6:0] 7'0000000 + end + end + case + assign $1\fus_oper_i_alu_shift_rot0__insn_type[6:0] 7'0000000 + end + sync always + update \fus_oper_i_alu_shift_rot0__insn_type $0\fus_oper_i_alu_shift_rot0__insn_type[6:0] + end + attribute \src "issuer_ls180.v:43185.3-43213.6" + process $proc$issuer_ls180.v:43185$2332 + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_shift_rot0__fn_unit[11:0] $1\fus_oper_i_alu_shift_rot0__fn_unit[11:0] + attribute \src "issuer_ls180.v:43186.5-43186.29" + switch \initial + attribute \src "issuer_ls180.v:43186.9-43186.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" + switch \ivalid_i + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_alu_shift_rot0__fn_unit[11:0] $2\fus_oper_i_alu_shift_rot0__fn_unit[11:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" + switch \core_core_insn_type + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_shift_rot0__fn_unit[11:0] 12'000000000000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_shift_rot0__fn_unit[11:0] 12'000000000000 + attribute \src "issuer_ls180.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_alu_shift_rot0__fn_unit[11:0] $3\fus_oper_i_alu_shift_rot0__fn_unit[11:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" + switch \fu_enable [8] + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_alu_shift_rot0__fn_unit[11:0] \dec_SHIFT_ROT_SHIFT_ROT_SHIFT_ROT__fn_unit + case + assign $3\fus_oper_i_alu_shift_rot0__fn_unit[11:0] 12'000000000000 + end + end + case + assign $1\fus_oper_i_alu_shift_rot0__fn_unit[11:0] 12'000000000000 + end + sync always + update \fus_oper_i_alu_shift_rot0__fn_unit $0\fus_oper_i_alu_shift_rot0__fn_unit[11:0] + end + attribute \src "issuer_ls180.v:43214.3-43243.6" + process $proc$issuer_ls180.v:43214$2333 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_shift_rot0__imm_data__data[63:0] $1\fus_oper_i_alu_shift_rot0__imm_data__data[63:0] + assign $0\fus_oper_i_alu_shift_rot0__imm_data__ok[0:0] $1\fus_oper_i_alu_shift_rot0__imm_data__ok[0:0] + attribute \src "issuer_ls180.v:43215.5-43215.29" + switch \initial + attribute \src "issuer_ls180.v:43215.9-43215.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" + switch \ivalid_i + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign $1\fus_oper_i_alu_shift_rot0__imm_data__data[63:0] $2\fus_oper_i_alu_shift_rot0__imm_data__data[63:0] + assign $1\fus_oper_i_alu_shift_rot0__imm_data__ok[0:0] $2\fus_oper_i_alu_shift_rot0__imm_data__ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" + switch \core_core_insn_type + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_shift_rot0__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\fus_oper_i_alu_shift_rot0__imm_data__ok[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_shift_rot0__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\fus_oper_i_alu_shift_rot0__imm_data__ok[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case + assign { } { } + assign { } { } + assign $2\fus_oper_i_alu_shift_rot0__imm_data__data[63:0] $3\fus_oper_i_alu_shift_rot0__imm_data__data[63:0] + assign $2\fus_oper_i_alu_shift_rot0__imm_data__ok[0:0] $3\fus_oper_i_alu_shift_rot0__imm_data__ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" + switch \fu_enable [8] + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $3\fus_oper_i_alu_shift_rot0__imm_data__ok[0:0] $3\fus_oper_i_alu_shift_rot0__imm_data__data[63:0] } { \dec_SHIFT_ROT_SHIFT_ROT_SHIFT_ROT__imm_data__ok \dec_SHIFT_ROT_SHIFT_ROT_SHIFT_ROT__imm_data__data } + case + assign $3\fus_oper_i_alu_shift_rot0__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $3\fus_oper_i_alu_shift_rot0__imm_data__ok[0:0] 1'0 + end + end + case + assign $1\fus_oper_i_alu_shift_rot0__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\fus_oper_i_alu_shift_rot0__imm_data__ok[0:0] 1'0 + end + sync always + update \fus_oper_i_alu_shift_rot0__imm_data__data $0\fus_oper_i_alu_shift_rot0__imm_data__data[63:0] + update \fus_oper_i_alu_shift_rot0__imm_data__ok $0\fus_oper_i_alu_shift_rot0__imm_data__ok[0:0] + end + attribute \src "issuer_ls180.v:43244.3-43273.6" + process $proc$issuer_ls180.v:43244$2334 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_shift_rot0__rc__ok[0:0] $1\fus_oper_i_alu_shift_rot0__rc__ok[0:0] + assign $0\fus_oper_i_alu_shift_rot0__rc__rc[0:0] $1\fus_oper_i_alu_shift_rot0__rc__rc[0:0] + attribute \src "issuer_ls180.v:43245.5-43245.29" + switch \initial + attribute \src "issuer_ls180.v:43245.9-43245.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" + switch \ivalid_i + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign $1\fus_oper_i_alu_shift_rot0__rc__ok[0:0] $2\fus_oper_i_alu_shift_rot0__rc__ok[0:0] + assign $1\fus_oper_i_alu_shift_rot0__rc__rc[0:0] $2\fus_oper_i_alu_shift_rot0__rc__rc[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" + switch \core_core_insn_type + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_shift_rot0__rc__ok[0:0] 1'0 + assign $2\fus_oper_i_alu_shift_rot0__rc__rc[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_shift_rot0__rc__ok[0:0] 1'0 + assign $2\fus_oper_i_alu_shift_rot0__rc__rc[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case + assign { } { } + assign { } { } + assign $2\fus_oper_i_alu_shift_rot0__rc__ok[0:0] $3\fus_oper_i_alu_shift_rot0__rc__ok[0:0] + assign $2\fus_oper_i_alu_shift_rot0__rc__rc[0:0] $3\fus_oper_i_alu_shift_rot0__rc__rc[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" + switch \fu_enable [8] + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $3\fus_oper_i_alu_shift_rot0__rc__ok[0:0] $3\fus_oper_i_alu_shift_rot0__rc__rc[0:0] } { \dec_SHIFT_ROT_SHIFT_ROT_SHIFT_ROT__rc__ok \dec_SHIFT_ROT_SHIFT_ROT_SHIFT_ROT__rc__rc } + case + assign $3\fus_oper_i_alu_shift_rot0__rc__ok[0:0] 1'0 + assign $3\fus_oper_i_alu_shift_rot0__rc__rc[0:0] 1'0 + end + end + case + assign $1\fus_oper_i_alu_shift_rot0__rc__ok[0:0] 1'0 + assign $1\fus_oper_i_alu_shift_rot0__rc__rc[0:0] 1'0 + end + sync always + update \fus_oper_i_alu_shift_rot0__rc__ok $0\fus_oper_i_alu_shift_rot0__rc__ok[0:0] + update \fus_oper_i_alu_shift_rot0__rc__rc $0\fus_oper_i_alu_shift_rot0__rc__rc[0:0] + end + attribute \src "issuer_ls180.v:43274.3-43303.6" + process $proc$issuer_ls180.v:43274$2335 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_shift_rot0__oe__oe[0:0] $1\fus_oper_i_alu_shift_rot0__oe__oe[0:0] + assign $0\fus_oper_i_alu_shift_rot0__oe__ok[0:0] $1\fus_oper_i_alu_shift_rot0__oe__ok[0:0] + attribute \src "issuer_ls180.v:43275.5-43275.29" + switch \initial + attribute \src "issuer_ls180.v:43275.9-43275.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" + switch \ivalid_i + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign $1\fus_oper_i_alu_shift_rot0__oe__oe[0:0] $2\fus_oper_i_alu_shift_rot0__oe__oe[0:0] + assign $1\fus_oper_i_alu_shift_rot0__oe__ok[0:0] $2\fus_oper_i_alu_shift_rot0__oe__ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" + switch \core_core_insn_type + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_shift_rot0__oe__oe[0:0] 1'0 + assign $2\fus_oper_i_alu_shift_rot0__oe__ok[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_shift_rot0__oe__oe[0:0] 1'0 + assign $2\fus_oper_i_alu_shift_rot0__oe__ok[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case + assign { } { } + assign { } { } + assign $2\fus_oper_i_alu_shift_rot0__oe__oe[0:0] $3\fus_oper_i_alu_shift_rot0__oe__oe[0:0] + assign $2\fus_oper_i_alu_shift_rot0__oe__ok[0:0] $3\fus_oper_i_alu_shift_rot0__oe__ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" + switch \fu_enable [8] + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $3\fus_oper_i_alu_shift_rot0__oe__ok[0:0] $3\fus_oper_i_alu_shift_rot0__oe__oe[0:0] } { \dec_SHIFT_ROT_SHIFT_ROT_SHIFT_ROT__oe__ok \dec_SHIFT_ROT_SHIFT_ROT_SHIFT_ROT__oe__oe } + case + assign $3\fus_oper_i_alu_shift_rot0__oe__oe[0:0] 1'0 + assign $3\fus_oper_i_alu_shift_rot0__oe__ok[0:0] 1'0 + end + end + case + assign $1\fus_oper_i_alu_shift_rot0__oe__oe[0:0] 1'0 + assign $1\fus_oper_i_alu_shift_rot0__oe__ok[0:0] 1'0 + end + sync always + update \fus_oper_i_alu_shift_rot0__oe__oe $0\fus_oper_i_alu_shift_rot0__oe__oe[0:0] + update \fus_oper_i_alu_shift_rot0__oe__ok $0\fus_oper_i_alu_shift_rot0__oe__ok[0:0] + end + attribute \src "issuer_ls180.v:43304.3-43332.6" + process $proc$issuer_ls180.v:43304$2336 + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_shift_rot0__write_cr0[0:0] $1\fus_oper_i_alu_shift_rot0__write_cr0[0:0] + attribute \src "issuer_ls180.v:43305.5-43305.29" + switch \initial + attribute \src "issuer_ls180.v:43305.9-43305.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" + switch \ivalid_i + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_alu_shift_rot0__write_cr0[0:0] $2\fus_oper_i_alu_shift_rot0__write_cr0[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" + switch \core_core_insn_type + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_shift_rot0__write_cr0[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_shift_rot0__write_cr0[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_alu_shift_rot0__write_cr0[0:0] $3\fus_oper_i_alu_shift_rot0__write_cr0[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" + switch \fu_enable [8] + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_alu_shift_rot0__write_cr0[0:0] \dec_SHIFT_ROT_SHIFT_ROT_SHIFT_ROT__write_cr0 + case + assign $3\fus_oper_i_alu_shift_rot0__write_cr0[0:0] 1'0 + end + end + case + assign $1\fus_oper_i_alu_shift_rot0__write_cr0[0:0] 1'0 + end + sync always + update \fus_oper_i_alu_shift_rot0__write_cr0 $0\fus_oper_i_alu_shift_rot0__write_cr0[0:0] + end + attribute \src "issuer_ls180.v:43333.3-43361.6" + process $proc$issuer_ls180.v:43333$2337 + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_shift_rot0__input_carry[1:0] $1\fus_oper_i_alu_shift_rot0__input_carry[1:0] + attribute \src "issuer_ls180.v:43334.5-43334.29" + switch \initial + attribute \src "issuer_ls180.v:43334.9-43334.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" + switch \ivalid_i + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_alu_shift_rot0__input_carry[1:0] $2\fus_oper_i_alu_shift_rot0__input_carry[1:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" + switch \core_core_insn_type + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_shift_rot0__input_carry[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_shift_rot0__input_carry[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_alu_shift_rot0__input_carry[1:0] $3\fus_oper_i_alu_shift_rot0__input_carry[1:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" + switch \fu_enable [8] + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_alu_shift_rot0__input_carry[1:0] \dec_SHIFT_ROT_SHIFT_ROT_SHIFT_ROT__input_carry + case + assign $3\fus_oper_i_alu_shift_rot0__input_carry[1:0] 2'00 + end + end + case + assign $1\fus_oper_i_alu_shift_rot0__input_carry[1:0] 2'00 + end + sync always + update \fus_oper_i_alu_shift_rot0__input_carry $0\fus_oper_i_alu_shift_rot0__input_carry[1:0] + end + attribute \src "issuer_ls180.v:43362.3-43390.6" + process $proc$issuer_ls180.v:43362$2338 + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_shift_rot0__output_carry[0:0] $1\fus_oper_i_alu_shift_rot0__output_carry[0:0] + attribute \src "issuer_ls180.v:43363.5-43363.29" + switch \initial + attribute \src "issuer_ls180.v:43363.9-43363.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" + switch \ivalid_i + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_alu_shift_rot0__output_carry[0:0] $2\fus_oper_i_alu_shift_rot0__output_carry[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" + switch \core_core_insn_type + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_shift_rot0__output_carry[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_shift_rot0__output_carry[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_alu_shift_rot0__output_carry[0:0] $3\fus_oper_i_alu_shift_rot0__output_carry[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" + switch \fu_enable [8] + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_alu_shift_rot0__output_carry[0:0] \dec_SHIFT_ROT_SHIFT_ROT_SHIFT_ROT__output_carry + case + assign $3\fus_oper_i_alu_shift_rot0__output_carry[0:0] 1'0 + end + end + case + assign $1\fus_oper_i_alu_shift_rot0__output_carry[0:0] 1'0 + end + sync always + update \fus_oper_i_alu_shift_rot0__output_carry $0\fus_oper_i_alu_shift_rot0__output_carry[0:0] + end + attribute \src "issuer_ls180.v:43391.3-43419.6" + process $proc$issuer_ls180.v:43391$2339 + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_shift_rot0__input_cr[0:0] $1\fus_oper_i_alu_shift_rot0__input_cr[0:0] + attribute \src "issuer_ls180.v:43392.5-43392.29" + switch \initial + attribute \src "issuer_ls180.v:43392.9-43392.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" + switch \ivalid_i + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_alu_shift_rot0__input_cr[0:0] $2\fus_oper_i_alu_shift_rot0__input_cr[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" + switch \core_core_insn_type + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_shift_rot0__input_cr[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_shift_rot0__input_cr[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_alu_shift_rot0__input_cr[0:0] $3\fus_oper_i_alu_shift_rot0__input_cr[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" + switch \fu_enable [8] + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_alu_shift_rot0__input_cr[0:0] \dec_SHIFT_ROT_SHIFT_ROT_SHIFT_ROT__input_cr + case + assign $3\fus_oper_i_alu_shift_rot0__input_cr[0:0] 1'0 + end + end + case + assign $1\fus_oper_i_alu_shift_rot0__input_cr[0:0] 1'0 + end + sync always + update \fus_oper_i_alu_shift_rot0__input_cr $0\fus_oper_i_alu_shift_rot0__input_cr[0:0] + end + attribute \src "issuer_ls180.v:43420.3-43448.6" + process $proc$issuer_ls180.v:43420$2340 + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_shift_rot0__output_cr[0:0] $1\fus_oper_i_alu_shift_rot0__output_cr[0:0] + attribute \src "issuer_ls180.v:43421.5-43421.29" + switch \initial + attribute \src "issuer_ls180.v:43421.9-43421.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" + switch \ivalid_i + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_alu_shift_rot0__output_cr[0:0] $2\fus_oper_i_alu_shift_rot0__output_cr[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" + switch \core_core_insn_type + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_shift_rot0__output_cr[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_shift_rot0__output_cr[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_alu_shift_rot0__output_cr[0:0] $3\fus_oper_i_alu_shift_rot0__output_cr[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" + switch \fu_enable [8] + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_alu_shift_rot0__output_cr[0:0] \dec_SHIFT_ROT_SHIFT_ROT_SHIFT_ROT__output_cr + case + assign $3\fus_oper_i_alu_shift_rot0__output_cr[0:0] 1'0 + end + end + case + assign $1\fus_oper_i_alu_shift_rot0__output_cr[0:0] 1'0 + end + sync always + update \fus_oper_i_alu_shift_rot0__output_cr $0\fus_oper_i_alu_shift_rot0__output_cr[0:0] + end + attribute \src "issuer_ls180.v:43449.3-43477.6" + process $proc$issuer_ls180.v:43449$2341 + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_shift_rot0__is_32bit[0:0] $1\fus_oper_i_alu_shift_rot0__is_32bit[0:0] + attribute \src "issuer_ls180.v:43450.5-43450.29" + switch \initial + attribute \src "issuer_ls180.v:43450.9-43450.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" + switch \ivalid_i + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_alu_shift_rot0__is_32bit[0:0] $2\fus_oper_i_alu_shift_rot0__is_32bit[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" + switch \core_core_insn_type + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_shift_rot0__is_32bit[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_shift_rot0__is_32bit[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_alu_shift_rot0__is_32bit[0:0] $3\fus_oper_i_alu_shift_rot0__is_32bit[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" + switch \fu_enable [8] + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_alu_shift_rot0__is_32bit[0:0] \dec_SHIFT_ROT_SHIFT_ROT_SHIFT_ROT__is_32bit + case + assign $3\fus_oper_i_alu_shift_rot0__is_32bit[0:0] 1'0 + end + end + case + assign $1\fus_oper_i_alu_shift_rot0__is_32bit[0:0] 1'0 + end + sync always + update \fus_oper_i_alu_shift_rot0__is_32bit $0\fus_oper_i_alu_shift_rot0__is_32bit[0:0] + end + attribute \src "issuer_ls180.v:43478.3-43506.6" + process $proc$issuer_ls180.v:43478$2342 + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_shift_rot0__is_signed[0:0] $1\fus_oper_i_alu_shift_rot0__is_signed[0:0] + attribute \src "issuer_ls180.v:43479.5-43479.29" + switch \initial + attribute \src "issuer_ls180.v:43479.9-43479.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" + switch \ivalid_i + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_alu_shift_rot0__is_signed[0:0] $2\fus_oper_i_alu_shift_rot0__is_signed[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" + switch \core_core_insn_type + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_shift_rot0__is_signed[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_shift_rot0__is_signed[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_alu_shift_rot0__is_signed[0:0] $3\fus_oper_i_alu_shift_rot0__is_signed[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" + switch \fu_enable [8] + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_alu_shift_rot0__is_signed[0:0] \dec_SHIFT_ROT_SHIFT_ROT_SHIFT_ROT__is_signed + case + assign $3\fus_oper_i_alu_shift_rot0__is_signed[0:0] 1'0 + end + end + case + assign $1\fus_oper_i_alu_shift_rot0__is_signed[0:0] 1'0 + end + sync always + update \fus_oper_i_alu_shift_rot0__is_signed $0\fus_oper_i_alu_shift_rot0__is_signed[0:0] + end + attribute \src "issuer_ls180.v:43507.3-43535.6" + process $proc$issuer_ls180.v:43507$2343 + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_shift_rot0__insn[31:0] $1\fus_oper_i_alu_shift_rot0__insn[31:0] + attribute \src "issuer_ls180.v:43508.5-43508.29" + switch \initial + attribute \src "issuer_ls180.v:43508.9-43508.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" + switch \ivalid_i + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_alu_shift_rot0__insn[31:0] $2\fus_oper_i_alu_shift_rot0__insn[31:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" + switch \core_core_insn_type + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_shift_rot0__insn[31:0] 0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_shift_rot0__insn[31:0] 0 + attribute \src "issuer_ls180.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_alu_shift_rot0__insn[31:0] $3\fus_oper_i_alu_shift_rot0__insn[31:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" + switch \fu_enable [8] + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_alu_shift_rot0__insn[31:0] \dec_SHIFT_ROT_SHIFT_ROT_SHIFT_ROT__insn + case + assign $3\fus_oper_i_alu_shift_rot0__insn[31:0] 0 + end + end + case + assign $1\fus_oper_i_alu_shift_rot0__insn[31:0] 0 + end + sync always + update \fus_oper_i_alu_shift_rot0__insn $0\fus_oper_i_alu_shift_rot0__insn[31:0] + end + attribute \src "issuer_ls180.v:43536.3-43564.6" + process $proc$issuer_ls180.v:43536$2344 + assign { } { } + assign { } { } + assign $0\fus_cu_issue_i$25[0:0]$2345 $1\fus_cu_issue_i$25[0:0]$2346 + attribute \src "issuer_ls180.v:43537.5-43537.29" + switch \initial + attribute \src "issuer_ls180.v:43537.9-43537.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" + switch \ivalid_i + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_cu_issue_i$25[0:0]$2346 $2\fus_cu_issue_i$25[0:0]$2347 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" + switch \core_core_insn_type + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'0000101 + assign $2\fus_cu_issue_i$25[0:0]$2347 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'0000001 + assign $2\fus_cu_issue_i$25[0:0]$2347 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case + assign { } { } + assign $2\fus_cu_issue_i$25[0:0]$2347 $3\fus_cu_issue_i$25[0:0]$2348 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" + switch \fu_enable [8] + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_cu_issue_i$25[0:0]$2348 \issue_i + case + assign $3\fus_cu_issue_i$25[0:0]$2348 1'0 + end + end + case + assign $1\fus_cu_issue_i$25[0:0]$2346 1'0 + end + sync always + update \fus_cu_issue_i$25 $0\fus_cu_issue_i$25[0:0]$2345 + end + attribute \src "issuer_ls180.v:43565.3-43593.6" + process $proc$issuer_ls180.v:43565$2349 + assign { } { } + assign { } { } + assign $0\fus_cu_rdmaskn_i$27[4:0]$2350 $1\fus_cu_rdmaskn_i$27[4:0]$2351 + attribute \src "issuer_ls180.v:43566.5-43566.29" + switch \initial + attribute \src "issuer_ls180.v:43566.9-43566.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" + switch \ivalid_i + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_cu_rdmaskn_i$27[4:0]$2351 $2\fus_cu_rdmaskn_i$27[4:0]$2352 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" + switch \core_core_insn_type + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'0000101 + assign $2\fus_cu_rdmaskn_i$27[4:0]$2352 5'00000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'0000001 + assign $2\fus_cu_rdmaskn_i$27[4:0]$2352 5'00000 + attribute \src "issuer_ls180.v:0.0-0.0" + case + assign { } { } + assign $2\fus_cu_rdmaskn_i$27[4:0]$2352 $3\fus_cu_rdmaskn_i$27[4:0]$2353 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" + switch \fu_enable [8] + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_cu_rdmaskn_i$27[4:0]$2353 \$307 + case + assign $3\fus_cu_rdmaskn_i$27[4:0]$2353 5'00000 + end + end + case + assign $1\fus_cu_rdmaskn_i$27[4:0]$2351 5'00000 + end + sync always + update \fus_cu_rdmaskn_i$27 $0\fus_cu_rdmaskn_i$27[4:0]$2350 + end + attribute \src "issuer_ls180.v:43594.3-43622.6" + process $proc$issuer_ls180.v:43594$2354 + assign { } { } + assign { } { } + assign $0\fus_oper_i_ldst_ldst0__insn_type[6:0] $1\fus_oper_i_ldst_ldst0__insn_type[6:0] + attribute \src "issuer_ls180.v:43595.5-43595.29" + switch \initial + attribute \src "issuer_ls180.v:43595.9-43595.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" + switch \ivalid_i + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_ldst_ldst0__insn_type[6:0] $2\fus_oper_i_ldst_ldst0__insn_type[6:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" + switch \core_core_insn_type + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_ldst_ldst0__insn_type[6:0] 7'0000000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_ldst_ldst0__insn_type[6:0] 7'0000000 + attribute \src "issuer_ls180.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_ldst_ldst0__insn_type[6:0] $3\fus_oper_i_ldst_ldst0__insn_type[6:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" + switch \fu_enable [9] + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_ldst_ldst0__insn_type[6:0] \dec_LDST_LDST_LDST__insn_type + case + assign $3\fus_oper_i_ldst_ldst0__insn_type[6:0] 7'0000000 + end + end + case + assign $1\fus_oper_i_ldst_ldst0__insn_type[6:0] 7'0000000 + end + sync always + update \fus_oper_i_ldst_ldst0__insn_type $0\fus_oper_i_ldst_ldst0__insn_type[6:0] + end + attribute \src "issuer_ls180.v:43623.3-43651.6" + process $proc$issuer_ls180.v:43623$2355 + assign { } { } + assign { } { } + assign $0\fus_oper_i_ldst_ldst0__fn_unit[11:0] $1\fus_oper_i_ldst_ldst0__fn_unit[11:0] + attribute \src "issuer_ls180.v:43624.5-43624.29" + switch \initial + attribute \src "issuer_ls180.v:43624.9-43624.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" + switch \ivalid_i + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_ldst_ldst0__fn_unit[11:0] $2\fus_oper_i_ldst_ldst0__fn_unit[11:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" + switch \core_core_insn_type + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_ldst_ldst0__fn_unit[11:0] 12'000000000000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_ldst_ldst0__fn_unit[11:0] 12'000000000000 + attribute \src "issuer_ls180.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_ldst_ldst0__fn_unit[11:0] $3\fus_oper_i_ldst_ldst0__fn_unit[11:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" + switch \fu_enable [9] + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_ldst_ldst0__fn_unit[11:0] \dec_LDST_LDST_LDST__fn_unit + case + assign $3\fus_oper_i_ldst_ldst0__fn_unit[11:0] 12'000000000000 + end + end + case + assign $1\fus_oper_i_ldst_ldst0__fn_unit[11:0] 12'000000000000 + end + sync always + update \fus_oper_i_ldst_ldst0__fn_unit $0\fus_oper_i_ldst_ldst0__fn_unit[11:0] + end + attribute \src "issuer_ls180.v:43652.3-43681.6" + process $proc$issuer_ls180.v:43652$2356 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\fus_oper_i_ldst_ldst0__imm_data__data[63:0] $1\fus_oper_i_ldst_ldst0__imm_data__data[63:0] + assign $0\fus_oper_i_ldst_ldst0__imm_data__ok[0:0] $1\fus_oper_i_ldst_ldst0__imm_data__ok[0:0] + attribute \src "issuer_ls180.v:43653.5-43653.29" + switch \initial + attribute \src "issuer_ls180.v:43653.9-43653.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" + switch \ivalid_i + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign $1\fus_oper_i_ldst_ldst0__imm_data__data[63:0] $2\fus_oper_i_ldst_ldst0__imm_data__data[63:0] + assign $1\fus_oper_i_ldst_ldst0__imm_data__ok[0:0] $2\fus_oper_i_ldst_ldst0__imm_data__ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" + switch \core_core_insn_type + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_ldst_ldst0__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\fus_oper_i_ldst_ldst0__imm_data__ok[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_ldst_ldst0__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\fus_oper_i_ldst_ldst0__imm_data__ok[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case + assign { } { } + assign { } { } + assign $2\fus_oper_i_ldst_ldst0__imm_data__data[63:0] $3\fus_oper_i_ldst_ldst0__imm_data__data[63:0] + assign $2\fus_oper_i_ldst_ldst0__imm_data__ok[0:0] $3\fus_oper_i_ldst_ldst0__imm_data__ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" + switch \fu_enable [9] + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $3\fus_oper_i_ldst_ldst0__imm_data__ok[0:0] $3\fus_oper_i_ldst_ldst0__imm_data__data[63:0] } { \dec_LDST_LDST_LDST__imm_data__ok \dec_LDST_LDST_LDST__imm_data__data } + case + assign $3\fus_oper_i_ldst_ldst0__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $3\fus_oper_i_ldst_ldst0__imm_data__ok[0:0] 1'0 + end + end + case + assign $1\fus_oper_i_ldst_ldst0__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\fus_oper_i_ldst_ldst0__imm_data__ok[0:0] 1'0 + end + sync always + update \fus_oper_i_ldst_ldst0__imm_data__data $0\fus_oper_i_ldst_ldst0__imm_data__data[63:0] + update \fus_oper_i_ldst_ldst0__imm_data__ok $0\fus_oper_i_ldst_ldst0__imm_data__ok[0:0] + end + attribute \src "issuer_ls180.v:43682.3-43710.6" + process $proc$issuer_ls180.v:43682$2357 + assign { } { } + assign { } { } + assign $0\fus_oper_i_ldst_ldst0__zero_a[0:0] $1\fus_oper_i_ldst_ldst0__zero_a[0:0] + attribute \src "issuer_ls180.v:43683.5-43683.29" + switch \initial + attribute \src "issuer_ls180.v:43683.9-43683.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" + switch \ivalid_i + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_ldst_ldst0__zero_a[0:0] $2\fus_oper_i_ldst_ldst0__zero_a[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" + switch \core_core_insn_type + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_ldst_ldst0__zero_a[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_ldst_ldst0__zero_a[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_ldst_ldst0__zero_a[0:0] $3\fus_oper_i_ldst_ldst0__zero_a[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" + switch \fu_enable [9] + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_ldst_ldst0__zero_a[0:0] \dec_LDST_LDST_LDST__zero_a + case + assign $3\fus_oper_i_ldst_ldst0__zero_a[0:0] 1'0 + end + end + case + assign $1\fus_oper_i_ldst_ldst0__zero_a[0:0] 1'0 + end + sync always + update \fus_oper_i_ldst_ldst0__zero_a $0\fus_oper_i_ldst_ldst0__zero_a[0:0] + end + attribute \src "issuer_ls180.v:43711.3-43740.6" + process $proc$issuer_ls180.v:43711$2358 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\fus_oper_i_ldst_ldst0__rc__ok[0:0] $1\fus_oper_i_ldst_ldst0__rc__ok[0:0] + assign $0\fus_oper_i_ldst_ldst0__rc__rc[0:0] $1\fus_oper_i_ldst_ldst0__rc__rc[0:0] + attribute \src "issuer_ls180.v:43712.5-43712.29" + switch \initial + attribute \src "issuer_ls180.v:43712.9-43712.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" + switch \ivalid_i + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign $1\fus_oper_i_ldst_ldst0__rc__ok[0:0] $2\fus_oper_i_ldst_ldst0__rc__ok[0:0] + assign $1\fus_oper_i_ldst_ldst0__rc__rc[0:0] $2\fus_oper_i_ldst_ldst0__rc__rc[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" + switch \core_core_insn_type + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_ldst_ldst0__rc__ok[0:0] 1'0 + assign $2\fus_oper_i_ldst_ldst0__rc__rc[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_ldst_ldst0__rc__ok[0:0] 1'0 + assign $2\fus_oper_i_ldst_ldst0__rc__rc[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case + assign { } { } + assign { } { } + assign $2\fus_oper_i_ldst_ldst0__rc__ok[0:0] $3\fus_oper_i_ldst_ldst0__rc__ok[0:0] + assign $2\fus_oper_i_ldst_ldst0__rc__rc[0:0] $3\fus_oper_i_ldst_ldst0__rc__rc[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" + switch \fu_enable [9] + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $3\fus_oper_i_ldst_ldst0__rc__ok[0:0] $3\fus_oper_i_ldst_ldst0__rc__rc[0:0] } { \dec_LDST_LDST_LDST__rc__ok \dec_LDST_LDST_LDST__rc__rc } + case + assign $3\fus_oper_i_ldst_ldst0__rc__ok[0:0] 1'0 + assign $3\fus_oper_i_ldst_ldst0__rc__rc[0:0] 1'0 + end + end + case + assign $1\fus_oper_i_ldst_ldst0__rc__ok[0:0] 1'0 + assign $1\fus_oper_i_ldst_ldst0__rc__rc[0:0] 1'0 + end + sync always + update \fus_oper_i_ldst_ldst0__rc__ok $0\fus_oper_i_ldst_ldst0__rc__ok[0:0] + update \fus_oper_i_ldst_ldst0__rc__rc $0\fus_oper_i_ldst_ldst0__rc__rc[0:0] + end + attribute \src "issuer_ls180.v:43741.3-43770.6" + process $proc$issuer_ls180.v:43741$2359 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\fus_oper_i_ldst_ldst0__oe__oe[0:0] $1\fus_oper_i_ldst_ldst0__oe__oe[0:0] + assign $0\fus_oper_i_ldst_ldst0__oe__ok[0:0] $1\fus_oper_i_ldst_ldst0__oe__ok[0:0] + attribute \src "issuer_ls180.v:43742.5-43742.29" + switch \initial + attribute \src "issuer_ls180.v:43742.9-43742.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" + switch \ivalid_i + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign $1\fus_oper_i_ldst_ldst0__oe__oe[0:0] $2\fus_oper_i_ldst_ldst0__oe__oe[0:0] + assign $1\fus_oper_i_ldst_ldst0__oe__ok[0:0] $2\fus_oper_i_ldst_ldst0__oe__ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" + switch \core_core_insn_type + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_ldst_ldst0__oe__oe[0:0] 1'0 + assign $2\fus_oper_i_ldst_ldst0__oe__ok[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_ldst_ldst0__oe__oe[0:0] 1'0 + assign $2\fus_oper_i_ldst_ldst0__oe__ok[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case + assign { } { } + assign { } { } + assign $2\fus_oper_i_ldst_ldst0__oe__oe[0:0] $3\fus_oper_i_ldst_ldst0__oe__oe[0:0] + assign $2\fus_oper_i_ldst_ldst0__oe__ok[0:0] $3\fus_oper_i_ldst_ldst0__oe__ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" + switch \fu_enable [9] + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $3\fus_oper_i_ldst_ldst0__oe__ok[0:0] $3\fus_oper_i_ldst_ldst0__oe__oe[0:0] } { \dec_LDST_LDST_LDST__oe__ok \dec_LDST_LDST_LDST__oe__oe } + case + assign $3\fus_oper_i_ldst_ldst0__oe__oe[0:0] 1'0 + assign $3\fus_oper_i_ldst_ldst0__oe__ok[0:0] 1'0 + end + end + case + assign $1\fus_oper_i_ldst_ldst0__oe__oe[0:0] 1'0 + assign $1\fus_oper_i_ldst_ldst0__oe__ok[0:0] 1'0 + end + sync always + update \fus_oper_i_ldst_ldst0__oe__oe $0\fus_oper_i_ldst_ldst0__oe__oe[0:0] + update \fus_oper_i_ldst_ldst0__oe__ok $0\fus_oper_i_ldst_ldst0__oe__ok[0:0] + end + attribute \src "issuer_ls180.v:43771.3-43799.6" + process $proc$issuer_ls180.v:43771$2360 + assign { } { } + assign { } { } + assign $0\fus_oper_i_ldst_ldst0__is_32bit[0:0] $1\fus_oper_i_ldst_ldst0__is_32bit[0:0] + attribute \src "issuer_ls180.v:43772.5-43772.29" + switch \initial + attribute \src "issuer_ls180.v:43772.9-43772.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" + switch \ivalid_i + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_ldst_ldst0__is_32bit[0:0] $2\fus_oper_i_ldst_ldst0__is_32bit[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" + switch \core_core_insn_type + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_ldst_ldst0__is_32bit[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_ldst_ldst0__is_32bit[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_ldst_ldst0__is_32bit[0:0] $3\fus_oper_i_ldst_ldst0__is_32bit[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" + switch \fu_enable [9] + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_ldst_ldst0__is_32bit[0:0] \dec_LDST_LDST_LDST__is_32bit + case + assign $3\fus_oper_i_ldst_ldst0__is_32bit[0:0] 1'0 + end + end + case + assign $1\fus_oper_i_ldst_ldst0__is_32bit[0:0] 1'0 + end + sync always + update \fus_oper_i_ldst_ldst0__is_32bit $0\fus_oper_i_ldst_ldst0__is_32bit[0:0] + end + attribute \src "issuer_ls180.v:43800.3-43828.6" + process $proc$issuer_ls180.v:43800$2361 + assign { } { } + assign { } { } + assign $0\fus_oper_i_ldst_ldst0__is_signed[0:0] $1\fus_oper_i_ldst_ldst0__is_signed[0:0] + attribute \src "issuer_ls180.v:43801.5-43801.29" + switch \initial + attribute \src "issuer_ls180.v:43801.9-43801.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" + switch \ivalid_i + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_ldst_ldst0__is_signed[0:0] $2\fus_oper_i_ldst_ldst0__is_signed[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" + switch \core_core_insn_type + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_ldst_ldst0__is_signed[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_ldst_ldst0__is_signed[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_ldst_ldst0__is_signed[0:0] $3\fus_oper_i_ldst_ldst0__is_signed[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" + switch \fu_enable [9] + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_ldst_ldst0__is_signed[0:0] \dec_LDST_LDST_LDST__is_signed + case + assign $3\fus_oper_i_ldst_ldst0__is_signed[0:0] 1'0 + end + end + case + assign $1\fus_oper_i_ldst_ldst0__is_signed[0:0] 1'0 + end + sync always + update \fus_oper_i_ldst_ldst0__is_signed $0\fus_oper_i_ldst_ldst0__is_signed[0:0] + end + attribute \src "issuer_ls180.v:43829.3-43857.6" + process $proc$issuer_ls180.v:43829$2362 + assign { } { } + assign { } { } + assign $0\fus_oper_i_ldst_ldst0__data_len[3:0] $1\fus_oper_i_ldst_ldst0__data_len[3:0] + attribute \src "issuer_ls180.v:43830.5-43830.29" + switch \initial + attribute \src "issuer_ls180.v:43830.9-43830.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" + switch \ivalid_i + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_ldst_ldst0__data_len[3:0] $2\fus_oper_i_ldst_ldst0__data_len[3:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" + switch \core_core_insn_type + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_ldst_ldst0__data_len[3:0] 4'0000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_ldst_ldst0__data_len[3:0] 4'0000 + attribute \src "issuer_ls180.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_ldst_ldst0__data_len[3:0] $3\fus_oper_i_ldst_ldst0__data_len[3:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" + switch \fu_enable [9] + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_ldst_ldst0__data_len[3:0] \dec_LDST_LDST_LDST__data_len + case + assign $3\fus_oper_i_ldst_ldst0__data_len[3:0] 4'0000 + end + end + case + assign $1\fus_oper_i_ldst_ldst0__data_len[3:0] 4'0000 + end + sync always + update \fus_oper_i_ldst_ldst0__data_len $0\fus_oper_i_ldst_ldst0__data_len[3:0] + end + attribute \src "issuer_ls180.v:43858.3-43886.6" + process $proc$issuer_ls180.v:43858$2363 + assign { } { } + assign { } { } + assign $0\fus_oper_i_ldst_ldst0__byte_reverse[0:0] $1\fus_oper_i_ldst_ldst0__byte_reverse[0:0] + attribute \src "issuer_ls180.v:43859.5-43859.29" + switch \initial + attribute \src "issuer_ls180.v:43859.9-43859.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" + switch \ivalid_i + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_ldst_ldst0__byte_reverse[0:0] $2\fus_oper_i_ldst_ldst0__byte_reverse[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" + switch \core_core_insn_type + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_ldst_ldst0__byte_reverse[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_ldst_ldst0__byte_reverse[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_ldst_ldst0__byte_reverse[0:0] $3\fus_oper_i_ldst_ldst0__byte_reverse[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" + switch \fu_enable [9] + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_ldst_ldst0__byte_reverse[0:0] \dec_LDST_LDST_LDST__byte_reverse + case + assign $3\fus_oper_i_ldst_ldst0__byte_reverse[0:0] 1'0 + end + end + case + assign $1\fus_oper_i_ldst_ldst0__byte_reverse[0:0] 1'0 + end + sync always + update \fus_oper_i_ldst_ldst0__byte_reverse $0\fus_oper_i_ldst_ldst0__byte_reverse[0:0] + end + attribute \src "issuer_ls180.v:43887.3-43915.6" + process $proc$issuer_ls180.v:43887$2364 + assign { } { } + assign { } { } + assign $0\fus_oper_i_ldst_ldst0__sign_extend[0:0] $1\fus_oper_i_ldst_ldst0__sign_extend[0:0] + attribute \src "issuer_ls180.v:43888.5-43888.29" + switch \initial + attribute \src "issuer_ls180.v:43888.9-43888.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" + switch \ivalid_i + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_ldst_ldst0__sign_extend[0:0] $2\fus_oper_i_ldst_ldst0__sign_extend[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" + switch \core_core_insn_type + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_ldst_ldst0__sign_extend[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_ldst_ldst0__sign_extend[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_ldst_ldst0__sign_extend[0:0] $3\fus_oper_i_ldst_ldst0__sign_extend[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" + switch \fu_enable [9] + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_ldst_ldst0__sign_extend[0:0] \dec_LDST_LDST_LDST__sign_extend + case + assign $3\fus_oper_i_ldst_ldst0__sign_extend[0:0] 1'0 + end + end + case + assign $1\fus_oper_i_ldst_ldst0__sign_extend[0:0] 1'0 + end + sync always + update \fus_oper_i_ldst_ldst0__sign_extend $0\fus_oper_i_ldst_ldst0__sign_extend[0:0] + end + attribute \src "issuer_ls180.v:43916.3-43944.6" + process $proc$issuer_ls180.v:43916$2365 + assign { } { } + assign { } { } + assign $0\fus_oper_i_ldst_ldst0__ldst_mode[1:0] $1\fus_oper_i_ldst_ldst0__ldst_mode[1:0] + attribute \src "issuer_ls180.v:43917.5-43917.29" + switch \initial + attribute \src "issuer_ls180.v:43917.9-43917.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" + switch \ivalid_i + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_ldst_ldst0__ldst_mode[1:0] $2\fus_oper_i_ldst_ldst0__ldst_mode[1:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" + switch \core_core_insn_type + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_ldst_ldst0__ldst_mode[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_ldst_ldst0__ldst_mode[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_ldst_ldst0__ldst_mode[1:0] $3\fus_oper_i_ldst_ldst0__ldst_mode[1:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" + switch \fu_enable [9] + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_ldst_ldst0__ldst_mode[1:0] \dec_LDST_LDST_LDST__ldst_mode + case + assign $3\fus_oper_i_ldst_ldst0__ldst_mode[1:0] 2'00 + end + end + case + assign $1\fus_oper_i_ldst_ldst0__ldst_mode[1:0] 2'00 + end + sync always + update \fus_oper_i_ldst_ldst0__ldst_mode $0\fus_oper_i_ldst_ldst0__ldst_mode[1:0] + end + attribute \src "issuer_ls180.v:43945.3-43973.6" + process $proc$issuer_ls180.v:43945$2366 + assign { } { } + assign { } { } + assign $0\fus_oper_i_ldst_ldst0__insn[31:0] $1\fus_oper_i_ldst_ldst0__insn[31:0] + attribute \src "issuer_ls180.v:43946.5-43946.29" + switch \initial + attribute \src "issuer_ls180.v:43946.9-43946.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" + switch \ivalid_i + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_ldst_ldst0__insn[31:0] $2\fus_oper_i_ldst_ldst0__insn[31:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" + switch \core_core_insn_type + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_ldst_ldst0__insn[31:0] 0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_ldst_ldst0__insn[31:0] 0 + attribute \src "issuer_ls180.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_ldst_ldst0__insn[31:0] $3\fus_oper_i_ldst_ldst0__insn[31:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" + switch \fu_enable [9] + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_ldst_ldst0__insn[31:0] \dec_LDST_LDST_LDST__insn + case + assign $3\fus_oper_i_ldst_ldst0__insn[31:0] 0 + end + end + case + assign $1\fus_oper_i_ldst_ldst0__insn[31:0] 0 + end + sync always + update \fus_oper_i_ldst_ldst0__insn $0\fus_oper_i_ldst_ldst0__insn[31:0] + end + attribute \src "issuer_ls180.v:43974.3-44002.6" + process $proc$issuer_ls180.v:43974$2367 + assign { } { } + assign { } { } + assign $0\fus_cu_issue_i$28[0:0]$2368 $1\fus_cu_issue_i$28[0:0]$2369 + attribute \src "issuer_ls180.v:43975.5-43975.29" + switch \initial + attribute \src "issuer_ls180.v:43975.9-43975.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" + switch \ivalid_i + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_cu_issue_i$28[0:0]$2369 $2\fus_cu_issue_i$28[0:0]$2370 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" + switch \core_core_insn_type + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'0000101 + assign $2\fus_cu_issue_i$28[0:0]$2370 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'0000001 + assign $2\fus_cu_issue_i$28[0:0]$2370 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case + assign { } { } + assign $2\fus_cu_issue_i$28[0:0]$2370 $3\fus_cu_issue_i$28[0:0]$2371 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" + switch \fu_enable [9] + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_cu_issue_i$28[0:0]$2371 \issue_i + case + assign $3\fus_cu_issue_i$28[0:0]$2371 1'0 + end + end + case + assign $1\fus_cu_issue_i$28[0:0]$2369 1'0 + end + sync always + update \fus_cu_issue_i$28 $0\fus_cu_issue_i$28[0:0]$2368 + end + attribute \src "issuer_ls180.v:44003.3-44031.6" + process $proc$issuer_ls180.v:44003$2372 + assign { } { } + assign { } { } + assign $0\fus_cu_rdmaskn_i$30[2:0]$2373 $1\fus_cu_rdmaskn_i$30[2:0]$2374 + attribute \src "issuer_ls180.v:44004.5-44004.29" + switch \initial + attribute \src "issuer_ls180.v:44004.9-44004.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" + switch \ivalid_i + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_cu_rdmaskn_i$30[2:0]$2374 $2\fus_cu_rdmaskn_i$30[2:0]$2375 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" + switch \core_core_insn_type + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'0000101 + assign $2\fus_cu_rdmaskn_i$30[2:0]$2375 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'0000001 + assign $2\fus_cu_rdmaskn_i$30[2:0]$2375 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case + assign { } { } + assign $2\fus_cu_rdmaskn_i$30[2:0]$2375 $3\fus_cu_rdmaskn_i$30[2:0]$2376 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" + switch \fu_enable [9] + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_cu_rdmaskn_i$30[2:0]$2376 \$329 + case + assign $3\fus_cu_rdmaskn_i$30[2:0]$2376 3'000 + end + end + case + assign $1\fus_cu_rdmaskn_i$30[2:0]$2374 3'000 + end + sync always + update \fus_cu_rdmaskn_i$30 $0\fus_cu_rdmaskn_i$30[2:0]$2373 + end + attribute \src "issuer_ls180.v:44032.3-44040.6" + process $proc$issuer_ls180.v:44032$2377 + assign { } { } + assign { } { } + assign $0\dp_INT_ra_alu0_0$next[0:0]$2378 $1\dp_INT_ra_alu0_0$next[0:0]$2379 + attribute \src "issuer_ls180.v:44033.5-44033.29" + switch \initial + attribute \src "issuer_ls180.v:44033.9-44033.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dp_INT_ra_alu0_0$next[0:0]$2379 1'0 + case + assign $1\dp_INT_ra_alu0_0$next[0:0]$2379 \rp_INT_ra_alu0_0 + end + sync always + update \dp_INT_ra_alu0_0$next $0\dp_INT_ra_alu0_0$next[0:0]$2378 + end + attribute \src "issuer_ls180.v:44041.3-44050.6" + process $proc$issuer_ls180.v:44041$2380 + assign { } { } + assign { } { } + assign $0\fus_src1_i[63:0] $1\fus_src1_i[63:0] + attribute \src "issuer_ls180.v:44042.5-44042.29" + switch \initial + attribute \src "issuer_ls180.v:44042.9-44042.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" + switch \dp_INT_ra_alu0_0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_src1_i[63:0] \int_src1__data_o + case + assign $1\fus_src1_i[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \fus_src1_i $0\fus_src1_i[63:0] + end + attribute \src "issuer_ls180.v:44051.3-44059.6" + process $proc$issuer_ls180.v:44051$2381 + assign { } { } + assign { } { } + assign $0\dp_INT_ra_cr0_1$next[0:0]$2382 $1\dp_INT_ra_cr0_1$next[0:0]$2383 + attribute \src "issuer_ls180.v:44052.5-44052.29" + switch \initial + attribute \src "issuer_ls180.v:44052.9-44052.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dp_INT_ra_cr0_1$next[0:0]$2383 1'0 + case + assign $1\dp_INT_ra_cr0_1$next[0:0]$2383 \rp_INT_ra_cr0_1 + end + sync always + update \dp_INT_ra_cr0_1$next $0\dp_INT_ra_cr0_1$next[0:0]$2382 + end + attribute \src "issuer_ls180.v:44060.3-44069.6" + process $proc$issuer_ls180.v:44060$2384 + assign { } { } + assign { } { } + assign $0\fus_src1_i$33[63:0]$2385 $1\fus_src1_i$33[63:0]$2386 + attribute \src "issuer_ls180.v:44061.5-44061.29" + switch \initial + attribute \src "issuer_ls180.v:44061.9-44061.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" + switch \dp_INT_ra_cr0_1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_src1_i$33[63:0]$2386 \int_src1__data_o + case + assign $1\fus_src1_i$33[63:0]$2386 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \fus_src1_i$33 $0\fus_src1_i$33[63:0]$2385 + end + attribute \src "issuer_ls180.v:44070.3-44078.6" + process $proc$issuer_ls180.v:44070$2387 + assign { } { } + assign { } { } + assign $0\dp_INT_ra_trap0_2$next[0:0]$2388 $1\dp_INT_ra_trap0_2$next[0:0]$2389 + attribute \src "issuer_ls180.v:44071.5-44071.29" + switch \initial + attribute \src "issuer_ls180.v:44071.9-44071.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dp_INT_ra_trap0_2$next[0:0]$2389 1'0 + case + assign $1\dp_INT_ra_trap0_2$next[0:0]$2389 \rp_INT_ra_trap0_2 + end + sync always + update \dp_INT_ra_trap0_2$next $0\dp_INT_ra_trap0_2$next[0:0]$2388 + end + attribute \src "issuer_ls180.v:44079.3-44088.6" + process $proc$issuer_ls180.v:44079$2390 + assign { } { } + assign { } { } + assign $0\fus_src1_i$36[63:0]$2391 $1\fus_src1_i$36[63:0]$2392 + attribute \src "issuer_ls180.v:44080.5-44080.29" + switch \initial + attribute \src "issuer_ls180.v:44080.9-44080.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" + switch \dp_INT_ra_trap0_2 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_src1_i$36[63:0]$2392 \int_src1__data_o + case + assign $1\fus_src1_i$36[63:0]$2392 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \fus_src1_i$36 $0\fus_src1_i$36[63:0]$2391 + end + attribute \src "issuer_ls180.v:44089.3-44097.6" + process $proc$issuer_ls180.v:44089$2393 + assign { } { } + assign { } { } + assign $0\dp_INT_ra_logical0_3$next[0:0]$2394 $1\dp_INT_ra_logical0_3$next[0:0]$2395 + attribute \src "issuer_ls180.v:44090.5-44090.29" + switch \initial + attribute \src "issuer_ls180.v:44090.9-44090.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dp_INT_ra_logical0_3$next[0:0]$2395 1'0 + case + assign $1\dp_INT_ra_logical0_3$next[0:0]$2395 \rp_INT_ra_logical0_3 + end + sync always + update \dp_INT_ra_logical0_3$next $0\dp_INT_ra_logical0_3$next[0:0]$2394 + end + attribute \src "issuer_ls180.v:44098.3-44107.6" + process $proc$issuer_ls180.v:44098$2396 + assign { } { } + assign { } { } + assign $0\fus_src1_i$39[63:0]$2397 $1\fus_src1_i$39[63:0]$2398 + attribute \src "issuer_ls180.v:44099.5-44099.29" + switch \initial + attribute \src "issuer_ls180.v:44099.9-44099.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" + switch \dp_INT_ra_logical0_3 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_src1_i$39[63:0]$2398 \int_src1__data_o + case + assign $1\fus_src1_i$39[63:0]$2398 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \fus_src1_i$39 $0\fus_src1_i$39[63:0]$2397 + end + attribute \src "issuer_ls180.v:44108.3-44116.6" + process $proc$issuer_ls180.v:44108$2399 + assign { } { } + assign { } { } + assign $0\dp_INT_ra_spr0_4$next[0:0]$2400 $1\dp_INT_ra_spr0_4$next[0:0]$2401 + attribute \src "issuer_ls180.v:44109.5-44109.29" + switch \initial + attribute \src "issuer_ls180.v:44109.9-44109.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dp_INT_ra_spr0_4$next[0:0]$2401 1'0 + case + assign $1\dp_INT_ra_spr0_4$next[0:0]$2401 \rp_INT_ra_spr0_4 + end + sync always + update \dp_INT_ra_spr0_4$next $0\dp_INT_ra_spr0_4$next[0:0]$2400 + end + attribute \src "issuer_ls180.v:44117.3-44126.6" + process $proc$issuer_ls180.v:44117$2402 + assign { } { } + assign { } { } + assign $0\fus_src1_i$42[63:0]$2403 $1\fus_src1_i$42[63:0]$2404 + attribute \src "issuer_ls180.v:44118.5-44118.29" + switch \initial + attribute \src "issuer_ls180.v:44118.9-44118.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" + switch \dp_INT_ra_spr0_4 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_src1_i$42[63:0]$2404 \int_src1__data_o + case + assign $1\fus_src1_i$42[63:0]$2404 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \fus_src1_i$42 $0\fus_src1_i$42[63:0]$2403 + end + attribute \src "issuer_ls180.v:44127.3-44135.6" + process $proc$issuer_ls180.v:44127$2405 + assign { } { } + assign { } { } + assign $0\dp_INT_ra_div0_5$next[0:0]$2406 $1\dp_INT_ra_div0_5$next[0:0]$2407 + attribute \src "issuer_ls180.v:44128.5-44128.29" + switch \initial + attribute \src "issuer_ls180.v:44128.9-44128.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dp_INT_ra_div0_5$next[0:0]$2407 1'0 + case + assign $1\dp_INT_ra_div0_5$next[0:0]$2407 \rp_INT_ra_div0_5 + end + sync always + update \dp_INT_ra_div0_5$next $0\dp_INT_ra_div0_5$next[0:0]$2406 + end + attribute \src "issuer_ls180.v:44136.3-44145.6" + process $proc$issuer_ls180.v:44136$2408 + assign { } { } + assign { } { } + assign $0\fus_src1_i$45[63:0]$2409 $1\fus_src1_i$45[63:0]$2410 + attribute \src "issuer_ls180.v:44137.5-44137.29" + switch \initial + attribute \src "issuer_ls180.v:44137.9-44137.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" + switch \dp_INT_ra_div0_5 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_src1_i$45[63:0]$2410 \int_src1__data_o + case + assign $1\fus_src1_i$45[63:0]$2410 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \fus_src1_i$45 $0\fus_src1_i$45[63:0]$2409 + end + attribute \src "issuer_ls180.v:44146.3-44154.6" + process $proc$issuer_ls180.v:44146$2411 + assign { } { } + assign { } { } + assign $0\dp_INT_ra_mul0_6$next[0:0]$2412 $1\dp_INT_ra_mul0_6$next[0:0]$2413 + attribute \src "issuer_ls180.v:44147.5-44147.29" + switch \initial + attribute \src "issuer_ls180.v:44147.9-44147.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dp_INT_ra_mul0_6$next[0:0]$2413 1'0 + case + assign $1\dp_INT_ra_mul0_6$next[0:0]$2413 \rp_INT_ra_mul0_6 + end + sync always + update \dp_INT_ra_mul0_6$next $0\dp_INT_ra_mul0_6$next[0:0]$2412 + end + attribute \src "issuer_ls180.v:44155.3-44164.6" + process $proc$issuer_ls180.v:44155$2414 + assign { } { } + assign { } { } + assign $0\fus_src1_i$48[63:0]$2415 $1\fus_src1_i$48[63:0]$2416 + attribute \src "issuer_ls180.v:44156.5-44156.29" + switch \initial + attribute \src "issuer_ls180.v:44156.9-44156.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" + switch \dp_INT_ra_mul0_6 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_src1_i$48[63:0]$2416 \int_src1__data_o + case + assign $1\fus_src1_i$48[63:0]$2416 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \fus_src1_i$48 $0\fus_src1_i$48[63:0]$2415 + end + attribute \src "issuer_ls180.v:44165.3-44173.6" + process $proc$issuer_ls180.v:44165$2417 + assign { } { } + assign { } { } + assign $0\dp_INT_ra_shiftrot0_7$next[0:0]$2418 $1\dp_INT_ra_shiftrot0_7$next[0:0]$2419 + attribute \src "issuer_ls180.v:44166.5-44166.29" + switch \initial + attribute \src "issuer_ls180.v:44166.9-44166.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dp_INT_ra_shiftrot0_7$next[0:0]$2419 1'0 + case + assign $1\dp_INT_ra_shiftrot0_7$next[0:0]$2419 \rp_INT_ra_shiftrot0_7 + end + sync always + update \dp_INT_ra_shiftrot0_7$next $0\dp_INT_ra_shiftrot0_7$next[0:0]$2418 + end + attribute \src "issuer_ls180.v:44174.3-44183.6" + process $proc$issuer_ls180.v:44174$2420 + assign { } { } + assign { } { } + assign $0\fus_src1_i$51[63:0]$2421 $1\fus_src1_i$51[63:0]$2422 + attribute \src "issuer_ls180.v:44175.5-44175.29" + switch \initial + attribute \src "issuer_ls180.v:44175.9-44175.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" + switch \dp_INT_ra_shiftrot0_7 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_src1_i$51[63:0]$2422 \int_src1__data_o + case + assign $1\fus_src1_i$51[63:0]$2422 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \fus_src1_i$51 $0\fus_src1_i$51[63:0]$2421 + end + attribute \src "issuer_ls180.v:44184.3-44192.6" + process $proc$issuer_ls180.v:44184$2423 + assign { } { } + assign { } { } + assign $0\dp_INT_ra_ldst0_8$next[0:0]$2424 $1\dp_INT_ra_ldst0_8$next[0:0]$2425 + attribute \src "issuer_ls180.v:44185.5-44185.29" + switch \initial + attribute \src "issuer_ls180.v:44185.9-44185.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dp_INT_ra_ldst0_8$next[0:0]$2425 1'0 + case + assign $1\dp_INT_ra_ldst0_8$next[0:0]$2425 \rp_INT_ra_ldst0_8 + end + sync always + update \dp_INT_ra_ldst0_8$next $0\dp_INT_ra_ldst0_8$next[0:0]$2424 + end + attribute \src "issuer_ls180.v:44193.3-44202.6" + process $proc$issuer_ls180.v:44193$2426 + assign { } { } + assign { } { } + assign $0\fus_src1_i$54[63:0]$2427 $1\fus_src1_i$54[63:0]$2428 + attribute \src "issuer_ls180.v:44194.5-44194.29" + switch \initial + attribute \src "issuer_ls180.v:44194.9-44194.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" + switch \dp_INT_ra_ldst0_8 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_src1_i$54[63:0]$2428 \int_src1__data_o + case + assign $1\fus_src1_i$54[63:0]$2428 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \fus_src1_i$54 $0\fus_src1_i$54[63:0]$2427 + end + attribute \src "issuer_ls180.v:44203.3-44211.6" + process $proc$issuer_ls180.v:44203$2429 + assign { } { } + assign { } { } + assign $0\dp_INT_rb_alu0_0$next[0:0]$2430 $1\dp_INT_rb_alu0_0$next[0:0]$2431 + attribute \src "issuer_ls180.v:44204.5-44204.29" + switch \initial + attribute \src "issuer_ls180.v:44204.9-44204.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dp_INT_rb_alu0_0$next[0:0]$2431 1'0 + case + assign $1\dp_INT_rb_alu0_0$next[0:0]$2431 \rp_INT_rb_alu0_0 + end + sync always + update \dp_INT_rb_alu0_0$next $0\dp_INT_rb_alu0_0$next[0:0]$2430 + end + attribute \src "issuer_ls180.v:44212.3-44221.6" + process $proc$issuer_ls180.v:44212$2432 + assign { } { } + assign { } { } + assign $0\fus_src2_i[63:0] $1\fus_src2_i[63:0] + attribute \src "issuer_ls180.v:44213.5-44213.29" + switch \initial + attribute \src "issuer_ls180.v:44213.9-44213.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" + switch \dp_INT_rb_alu0_0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_src2_i[63:0] \int_src2__data_o + case + assign $1\fus_src2_i[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \fus_src2_i $0\fus_src2_i[63:0] + end + attribute \src "issuer_ls180.v:44222.3-44230.6" + process $proc$issuer_ls180.v:44222$2433 + assign { } { } + assign { } { } + assign $0\dp_INT_rb_cr0_1$next[0:0]$2434 $1\dp_INT_rb_cr0_1$next[0:0]$2435 + attribute \src "issuer_ls180.v:44223.5-44223.29" + switch \initial + attribute \src "issuer_ls180.v:44223.9-44223.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dp_INT_rb_cr0_1$next[0:0]$2435 1'0 + case + assign $1\dp_INT_rb_cr0_1$next[0:0]$2435 \rp_INT_rb_cr0_1 + end + sync always + update \dp_INT_rb_cr0_1$next $0\dp_INT_rb_cr0_1$next[0:0]$2434 + end + attribute \src "issuer_ls180.v:44231.3-44240.6" + process $proc$issuer_ls180.v:44231$2436 + assign { } { } + assign { } { } + assign $0\fus_src2_i$55[63:0]$2437 $1\fus_src2_i$55[63:0]$2438 + attribute \src "issuer_ls180.v:44232.5-44232.29" + switch \initial + attribute \src "issuer_ls180.v:44232.9-44232.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" + switch \dp_INT_rb_cr0_1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_src2_i$55[63:0]$2438 \int_src2__data_o + case + assign $1\fus_src2_i$55[63:0]$2438 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \fus_src2_i$55 $0\fus_src2_i$55[63:0]$2437 + end + attribute \src "issuer_ls180.v:44241.3-44249.6" + process $proc$issuer_ls180.v:44241$2439 + assign { } { } + assign { } { } + assign $0\dp_INT_rb_trap0_2$next[0:0]$2440 $1\dp_INT_rb_trap0_2$next[0:0]$2441 + attribute \src "issuer_ls180.v:44242.5-44242.29" + switch \initial + attribute \src "issuer_ls180.v:44242.9-44242.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dp_INT_rb_trap0_2$next[0:0]$2441 1'0 + case + assign $1\dp_INT_rb_trap0_2$next[0:0]$2441 \rp_INT_rb_trap0_2 + end + sync always + update \dp_INT_rb_trap0_2$next $0\dp_INT_rb_trap0_2$next[0:0]$2440 + end + attribute \src "issuer_ls180.v:44250.3-44259.6" + process $proc$issuer_ls180.v:44250$2442 + assign { } { } + assign { } { } + assign $0\fus_src2_i$56[63:0]$2443 $1\fus_src2_i$56[63:0]$2444 + attribute \src "issuer_ls180.v:44251.5-44251.29" + switch \initial + attribute \src "issuer_ls180.v:44251.9-44251.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" + switch \dp_INT_rb_trap0_2 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_src2_i$56[63:0]$2444 \int_src2__data_o + case + assign $1\fus_src2_i$56[63:0]$2444 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \fus_src2_i$56 $0\fus_src2_i$56[63:0]$2443 + end + attribute \src "issuer_ls180.v:44260.3-44268.6" + process $proc$issuer_ls180.v:44260$2445 + assign { } { } + assign { } { } + assign $0\dp_INT_rb_logical0_3$next[0:0]$2446 $1\dp_INT_rb_logical0_3$next[0:0]$2447 + attribute \src "issuer_ls180.v:44261.5-44261.29" + switch \initial + attribute \src "issuer_ls180.v:44261.9-44261.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dp_INT_rb_logical0_3$next[0:0]$2447 1'0 + case + assign $1\dp_INT_rb_logical0_3$next[0:0]$2447 \rp_INT_rb_logical0_3 + end + sync always + update \dp_INT_rb_logical0_3$next $0\dp_INT_rb_logical0_3$next[0:0]$2446 + end + attribute \src "issuer_ls180.v:44269.3-44278.6" + process $proc$issuer_ls180.v:44269$2448 + assign { } { } + assign { } { } + assign $0\fus_src2_i$57[63:0]$2449 $1\fus_src2_i$57[63:0]$2450 + attribute \src "issuer_ls180.v:44270.5-44270.29" + switch \initial + attribute \src "issuer_ls180.v:44270.9-44270.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" + switch \dp_INT_rb_logical0_3 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_src2_i$57[63:0]$2450 \int_src2__data_o + case + assign $1\fus_src2_i$57[63:0]$2450 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \fus_src2_i$57 $0\fus_src2_i$57[63:0]$2449 + end + attribute \src "issuer_ls180.v:44279.3-44287.6" + process $proc$issuer_ls180.v:44279$2451 + assign { } { } + assign { } { } + assign $0\dp_INT_rb_div0_4$next[0:0]$2452 $1\dp_INT_rb_div0_4$next[0:0]$2453 + attribute \src "issuer_ls180.v:44280.5-44280.29" + switch \initial + attribute \src "issuer_ls180.v:44280.9-44280.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dp_INT_rb_div0_4$next[0:0]$2453 1'0 + case + assign $1\dp_INT_rb_div0_4$next[0:0]$2453 \rp_INT_rb_div0_4 + end + sync always + update \dp_INT_rb_div0_4$next $0\dp_INT_rb_div0_4$next[0:0]$2452 + end + attribute \src "issuer_ls180.v:44288.3-44297.6" + process $proc$issuer_ls180.v:44288$2454 + assign { } { } + assign { } { } + assign $0\fus_src2_i$58[63:0]$2455 $1\fus_src2_i$58[63:0]$2456 + attribute \src "issuer_ls180.v:44289.5-44289.29" + switch \initial + attribute \src "issuer_ls180.v:44289.9-44289.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" + switch \dp_INT_rb_div0_4 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_src2_i$58[63:0]$2456 \int_src2__data_o + case + assign $1\fus_src2_i$58[63:0]$2456 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \fus_src2_i$58 $0\fus_src2_i$58[63:0]$2455 + end + attribute \src "issuer_ls180.v:44298.3-44306.6" + process $proc$issuer_ls180.v:44298$2457 + assign { } { } + assign { } { } + assign $0\dp_INT_rb_mul0_5$next[0:0]$2458 $1\dp_INT_rb_mul0_5$next[0:0]$2459 + attribute \src "issuer_ls180.v:44299.5-44299.29" + switch \initial + attribute \src "issuer_ls180.v:44299.9-44299.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dp_INT_rb_mul0_5$next[0:0]$2459 1'0 + case + assign $1\dp_INT_rb_mul0_5$next[0:0]$2459 \rp_INT_rb_mul0_5 + end + sync always + update \dp_INT_rb_mul0_5$next $0\dp_INT_rb_mul0_5$next[0:0]$2458 + end + attribute \src "issuer_ls180.v:44307.3-44316.6" + process $proc$issuer_ls180.v:44307$2460 + assign { } { } + assign { } { } + assign $0\fus_src2_i$59[63:0]$2461 $1\fus_src2_i$59[63:0]$2462 + attribute \src "issuer_ls180.v:44308.5-44308.29" + switch \initial + attribute \src "issuer_ls180.v:44308.9-44308.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" + switch \dp_INT_rb_mul0_5 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_src2_i$59[63:0]$2462 \int_src2__data_o + case + assign $1\fus_src2_i$59[63:0]$2462 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \fus_src2_i$59 $0\fus_src2_i$59[63:0]$2461 + end + attribute \src "issuer_ls180.v:44317.3-44325.6" + process $proc$issuer_ls180.v:44317$2463 + assign { } { } + assign { } { } + assign $0\dp_INT_rb_shiftrot0_6$next[0:0]$2464 $1\dp_INT_rb_shiftrot0_6$next[0:0]$2465 + attribute \src "issuer_ls180.v:44318.5-44318.29" + switch \initial + attribute \src "issuer_ls180.v:44318.9-44318.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dp_INT_rb_shiftrot0_6$next[0:0]$2465 1'0 + case + assign $1\dp_INT_rb_shiftrot0_6$next[0:0]$2465 \rp_INT_rb_shiftrot0_6 + end + sync always + update \dp_INT_rb_shiftrot0_6$next $0\dp_INT_rb_shiftrot0_6$next[0:0]$2464 + end + attribute \src "issuer_ls180.v:44326.3-44335.6" + process $proc$issuer_ls180.v:44326$2466 + assign { } { } + assign { } { } + assign $0\fus_src2_i$60[63:0]$2467 $1\fus_src2_i$60[63:0]$2468 + attribute \src "issuer_ls180.v:44327.5-44327.29" + switch \initial + attribute \src "issuer_ls180.v:44327.9-44327.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" + switch \dp_INT_rb_shiftrot0_6 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_src2_i$60[63:0]$2468 \int_src2__data_o + case + assign $1\fus_src2_i$60[63:0]$2468 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \fus_src2_i$60 $0\fus_src2_i$60[63:0]$2467 + end + attribute \src "issuer_ls180.v:44336.3-44344.6" + process $proc$issuer_ls180.v:44336$2469 + assign { } { } + assign { } { } + assign $0\dp_INT_rb_ldst0_7$next[0:0]$2470 $1\dp_INT_rb_ldst0_7$next[0:0]$2471 + attribute \src "issuer_ls180.v:44337.5-44337.29" + switch \initial + attribute \src "issuer_ls180.v:44337.9-44337.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dp_INT_rb_ldst0_7$next[0:0]$2471 1'0 + case + assign $1\dp_INT_rb_ldst0_7$next[0:0]$2471 \rp_INT_rb_ldst0_7 + end + sync always + update \dp_INT_rb_ldst0_7$next $0\dp_INT_rb_ldst0_7$next[0:0]$2470 + end + attribute \src "issuer_ls180.v:44345.3-44354.6" + process $proc$issuer_ls180.v:44345$2472 + assign { } { } + assign { } { } + assign $0\fus_src2_i$61[63:0]$2473 $1\fus_src2_i$61[63:0]$2474 + attribute \src "issuer_ls180.v:44346.5-44346.29" + switch \initial + attribute \src "issuer_ls180.v:44346.9-44346.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" + switch \dp_INT_rb_ldst0_7 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_src2_i$61[63:0]$2474 \int_src2__data_o + case + assign $1\fus_src2_i$61[63:0]$2474 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \fus_src2_i$61 $0\fus_src2_i$61[63:0]$2473 + end + attribute \src "issuer_ls180.v:44355.3-44363.6" + process $proc$issuer_ls180.v:44355$2475 + assign { } { } + assign { } { } + assign $0\dp_INT_rc_shiftrot0_0$next[0:0]$2476 $1\dp_INT_rc_shiftrot0_0$next[0:0]$2477 + attribute \src "issuer_ls180.v:44356.5-44356.29" + switch \initial + attribute \src "issuer_ls180.v:44356.9-44356.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dp_INT_rc_shiftrot0_0$next[0:0]$2477 1'0 + case + assign $1\dp_INT_rc_shiftrot0_0$next[0:0]$2477 \rp_INT_rc_shiftrot0_0 + end + sync always + update \dp_INT_rc_shiftrot0_0$next $0\dp_INT_rc_shiftrot0_0$next[0:0]$2476 + end + attribute \src "issuer_ls180.v:44364.3-44373.6" + process $proc$issuer_ls180.v:44364$2478 + assign { } { } + assign { } { } + assign $0\fus_src3_i[63:0] $1\fus_src3_i[63:0] + attribute \src "issuer_ls180.v:44365.5-44365.29" + switch \initial + attribute \src "issuer_ls180.v:44365.9-44365.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" + switch \dp_INT_rc_shiftrot0_0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_src3_i[63:0] \int_src3__data_o + case + assign $1\fus_src3_i[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \fus_src3_i $0\fus_src3_i[63:0] + end + attribute \src "issuer_ls180.v:44374.3-44382.6" + process $proc$issuer_ls180.v:44374$2479 + assign { } { } + assign { } { } + assign $0\dp_INT_rc_ldst0_1$next[0:0]$2480 $1\dp_INT_rc_ldst0_1$next[0:0]$2481 + attribute \src "issuer_ls180.v:44375.5-44375.29" + switch \initial + attribute \src "issuer_ls180.v:44375.9-44375.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dp_INT_rc_ldst0_1$next[0:0]$2481 1'0 + case + assign $1\dp_INT_rc_ldst0_1$next[0:0]$2481 \rp_INT_rc_ldst0_1 + end + sync always + update \dp_INT_rc_ldst0_1$next $0\dp_INT_rc_ldst0_1$next[0:0]$2480 + end + attribute \src "issuer_ls180.v:44383.3-44392.6" + process $proc$issuer_ls180.v:44383$2482 + assign { } { } + assign { } { } + assign $0\fus_src3_i$62[63:0]$2483 $1\fus_src3_i$62[63:0]$2484 + attribute \src "issuer_ls180.v:44384.5-44384.29" + switch \initial + attribute \src "issuer_ls180.v:44384.9-44384.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" + switch \dp_INT_rc_ldst0_1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_src3_i$62[63:0]$2484 \int_src3__data_o + case + assign $1\fus_src3_i$62[63:0]$2484 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \fus_src3_i$62 $0\fus_src3_i$62[63:0]$2483 + end + attribute \src "issuer_ls180.v:44393.3-44419.6" + process $proc$issuer_ls180.v:44393$2485 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\counter$next[1:0]$2486 $4\counter$next[1:0]$2490 + attribute \src "issuer_ls180.v:44394.5-44394.29" + switch \initial + attribute \src "issuer_ls180.v:44394.9-44394.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:177" + switch \$200 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\counter$next[1:0]$2487 \$202 [1:0] + case + assign $1\counter$next[1:0]$2487 \counter + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" + switch \ivalid_i + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\counter$next[1:0]$2488 $3\counter$next[1:0]$2489 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" + switch \core_core_insn_type + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'0000001 + assign { } { } + assign $3\counter$next[1:0]$2489 2'10 + case + assign $3\counter$next[1:0]$2489 $1\counter$next[1:0]$2487 + end + case + assign $2\counter$next[1:0]$2488 $1\counter$next[1:0]$2487 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\counter$next[1:0]$2490 2'00 + case + assign $4\counter$next[1:0]$2490 $2\counter$next[1:0]$2488 + end + sync always + update \counter$next $0\counter$next[1:0]$2486 + end + attribute \src "issuer_ls180.v:44420.3-44428.6" + process $proc$issuer_ls180.v:44420$2491 + assign { } { } + assign { } { } + assign $0\dp_XER_xer_so_alu0_0$next[0:0]$2492 $1\dp_XER_xer_so_alu0_0$next[0:0]$2493 + attribute \src "issuer_ls180.v:44421.5-44421.29" + switch \initial + attribute \src "issuer_ls180.v:44421.9-44421.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dp_XER_xer_so_alu0_0$next[0:0]$2493 1'0 + case + assign $1\dp_XER_xer_so_alu0_0$next[0:0]$2493 \rp_XER_xer_so_alu0_0 + end + sync always + update \dp_XER_xer_so_alu0_0$next $0\dp_XER_xer_so_alu0_0$next[0:0]$2492 + end + attribute \src "issuer_ls180.v:44429.3-44438.6" + process $proc$issuer_ls180.v:44429$2494 + assign { } { } + assign { } { } + assign $0\fus_src3_i$63[0:0]$2495 $1\fus_src3_i$63[0:0]$2496 + attribute \src "issuer_ls180.v:44430.5-44430.29" + switch \initial + attribute \src "issuer_ls180.v:44430.9-44430.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" + switch \dp_XER_xer_so_alu0_0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_src3_i$63[0:0]$2496 \xer_src1__data_o [0] + case + assign $1\fus_src3_i$63[0:0]$2496 1'0 + end + sync always + update \fus_src3_i$63 $0\fus_src3_i$63[0:0]$2495 + end + attribute \src "issuer_ls180.v:44439.3-44447.6" + process $proc$issuer_ls180.v:44439$2497 + assign { } { } + assign { } { } + assign $0\dp_XER_xer_so_logical0_1$next[0:0]$2498 $1\dp_XER_xer_so_logical0_1$next[0:0]$2499 + attribute \src "issuer_ls180.v:44440.5-44440.29" + switch \initial + attribute \src "issuer_ls180.v:44440.9-44440.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dp_XER_xer_so_logical0_1$next[0:0]$2499 1'0 + case + assign $1\dp_XER_xer_so_logical0_1$next[0:0]$2499 \rp_XER_xer_so_logical0_1 + end + sync always + update \dp_XER_xer_so_logical0_1$next $0\dp_XER_xer_so_logical0_1$next[0:0]$2498 + end + attribute \src "issuer_ls180.v:44448.3-44538.6" + process $proc$issuer_ls180.v:44448$2500 + assign { } { } + assign { } { } + assign { } { } + assign $0\corebusy_o[0:0] $2\corebusy_o[0:0] + attribute \src "issuer_ls180.v:44449.5-44449.29" + switch \initial + attribute \src "issuer_ls180.v:44449.9-44449.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:177" + switch \$205 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\corebusy_o[0:0] 1'1 + case + assign $1\corebusy_o[0:0] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" + switch \ivalid_i + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\corebusy_o[0:0] $3\corebusy_o[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" + switch \core_core_insn_type + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'0000101 + assign $3\corebusy_o[0:0] $1\corebusy_o[0:0] + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'0000001 + assign { } { } + assign $3\corebusy_o[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $3\corebusy_o[0:0] $13\corebusy_o[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" + switch \fu_enable [0] + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\corebusy_o[0:0] \fus_cu_busy_o + case + assign $4\corebusy_o[0:0] $1\corebusy_o[0:0] + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" + switch \fu_enable [1] + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\corebusy_o[0:0] \fus_cu_busy_o$5 + case + assign $5\corebusy_o[0:0] $4\corebusy_o[0:0] + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" + switch \fu_enable [2] + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $6\corebusy_o[0:0] \fus_cu_busy_o$8 + case + assign $6\corebusy_o[0:0] $5\corebusy_o[0:0] + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" + switch \fu_enable [3] + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $7\corebusy_o[0:0] \fus_cu_busy_o$11 + case + assign $7\corebusy_o[0:0] $6\corebusy_o[0:0] + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" + switch \fu_enable [4] + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $8\corebusy_o[0:0] \fus_cu_busy_o$14 + case + assign $8\corebusy_o[0:0] $7\corebusy_o[0:0] + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" + switch \fu_enable [5] + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $9\corebusy_o[0:0] \fus_cu_busy_o$17 + case + assign $9\corebusy_o[0:0] $8\corebusy_o[0:0] + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" + switch \fu_enable [6] + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $10\corebusy_o[0:0] \fus_cu_busy_o$20 + case + assign $10\corebusy_o[0:0] $9\corebusy_o[0:0] + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" + switch \fu_enable [7] + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $11\corebusy_o[0:0] \fus_cu_busy_o$23 + case + assign $11\corebusy_o[0:0] $10\corebusy_o[0:0] + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" + switch \fu_enable [8] + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $12\corebusy_o[0:0] \fus_cu_busy_o$26 + case + assign $12\corebusy_o[0:0] $11\corebusy_o[0:0] + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" + switch \fu_enable [9] + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $13\corebusy_o[0:0] \fus_cu_busy_o$29 + case + assign $13\corebusy_o[0:0] $12\corebusy_o[0:0] + end + end + case + assign $2\corebusy_o[0:0] $1\corebusy_o[0:0] + end + sync always + update \corebusy_o $0\corebusy_o[0:0] + end + attribute \src "issuer_ls180.v:44539.3-44548.6" + process $proc$issuer_ls180.v:44539$2501 + assign { } { } + assign { } { } + assign $0\fus_src3_i$64[0:0]$2502 $1\fus_src3_i$64[0:0]$2503 + attribute \src "issuer_ls180.v:44540.5-44540.29" + switch \initial + attribute \src "issuer_ls180.v:44540.9-44540.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" + switch \dp_XER_xer_so_logical0_1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_src3_i$64[0:0]$2503 \xer_src1__data_o [0] + case + assign $1\fus_src3_i$64[0:0]$2503 1'0 + end + sync always + update \fus_src3_i$64 $0\fus_src3_i$64[0:0]$2502 + end + attribute \src "issuer_ls180.v:44549.3-44557.6" + process $proc$issuer_ls180.v:44549$2504 + assign { } { } + assign { } { } + assign $0\dp_XER_xer_so_spr0_2$next[0:0]$2505 $1\dp_XER_xer_so_spr0_2$next[0:0]$2506 + attribute \src "issuer_ls180.v:44550.5-44550.29" + switch \initial + attribute \src "issuer_ls180.v:44550.9-44550.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dp_XER_xer_so_spr0_2$next[0:0]$2506 1'0 + case + assign $1\dp_XER_xer_so_spr0_2$next[0:0]$2506 \rp_XER_xer_so_spr0_2 + end + sync always + update \dp_XER_xer_so_spr0_2$next $0\dp_XER_xer_so_spr0_2$next[0:0]$2505 + end + attribute \src "issuer_ls180.v:44558.3-44567.6" + process $proc$issuer_ls180.v:44558$2507 + assign { } { } + assign { } { } + assign $0\fus_src4_i[0:0] $1\fus_src4_i[0:0] + attribute \src "issuer_ls180.v:44559.5-44559.29" + switch \initial + attribute \src "issuer_ls180.v:44559.9-44559.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" + switch \dp_XER_xer_so_spr0_2 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_src4_i[0:0] \xer_src1__data_o [0] + case + assign $1\fus_src4_i[0:0] 1'0 + end + sync always + update \fus_src4_i $0\fus_src4_i[0:0] + end + attribute \src "issuer_ls180.v:44568.3-44576.6" + process $proc$issuer_ls180.v:44568$2508 + assign { } { } + assign { } { } + assign $0\dp_XER_xer_so_div0_3$next[0:0]$2509 $1\dp_XER_xer_so_div0_3$next[0:0]$2510 + attribute \src "issuer_ls180.v:44569.5-44569.29" + switch \initial + attribute \src "issuer_ls180.v:44569.9-44569.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dp_XER_xer_so_div0_3$next[0:0]$2510 1'0 + case + assign $1\dp_XER_xer_so_div0_3$next[0:0]$2510 \rp_XER_xer_so_div0_3 + end + sync always + update \dp_XER_xer_so_div0_3$next $0\dp_XER_xer_so_div0_3$next[0:0]$2509 + end + attribute \src "issuer_ls180.v:44577.3-44597.6" + process $proc$issuer_ls180.v:44577$2511 + assign { } { } + assign { } { } + assign { } { } + assign $0\core_terminate_o$next[0:0]$2512 $3\core_terminate_o$next[0:0]$2515 + attribute \src "issuer_ls180.v:44578.5-44578.29" + switch \initial + attribute \src "issuer_ls180.v:44578.9-44578.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" + switch \ivalid_i + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\core_terminate_o$next[0:0]$2513 $2\core_terminate_o$next[0:0]$2514 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" + switch \core_core_insn_type + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'0000101 + assign { } { } + assign $2\core_terminate_o$next[0:0]$2514 1'1 + case + assign $2\core_terminate_o$next[0:0]$2514 \core_terminate_o + end + case + assign $1\core_terminate_o$next[0:0]$2513 \core_terminate_o + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\core_terminate_o$next[0:0]$2515 1'0 + case + assign $3\core_terminate_o$next[0:0]$2515 $1\core_terminate_o$next[0:0]$2513 + end + sync always + update \core_terminate_o$next $0\core_terminate_o$next[0:0]$2512 + end + attribute \src "issuer_ls180.v:44598.3-44607.6" + process $proc$issuer_ls180.v:44598$2516 + assign { } { } + assign { } { } + assign $0\fus_src3_i$65[0:0]$2517 $1\fus_src3_i$65[0:0]$2518 + attribute \src "issuer_ls180.v:44599.5-44599.29" + switch \initial + attribute \src "issuer_ls180.v:44599.9-44599.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" + switch \dp_XER_xer_so_div0_3 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_src3_i$65[0:0]$2518 \xer_src1__data_o [0] + case + assign $1\fus_src3_i$65[0:0]$2518 1'0 + end + sync always + update \fus_src3_i$65 $0\fus_src3_i$65[0:0]$2517 + end + attribute \src "issuer_ls180.v:44608.3-44616.6" + process $proc$issuer_ls180.v:44608$2519 + assign { } { } + assign { } { } + assign $0\dp_XER_xer_so_mul0_4$next[0:0]$2520 $1\dp_XER_xer_so_mul0_4$next[0:0]$2521 + attribute \src "issuer_ls180.v:44609.5-44609.29" + switch \initial + attribute \src "issuer_ls180.v:44609.9-44609.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dp_XER_xer_so_mul0_4$next[0:0]$2521 1'0 + case + assign $1\dp_XER_xer_so_mul0_4$next[0:0]$2521 \rp_XER_xer_so_mul0_4 + end + sync always + update \dp_XER_xer_so_mul0_4$next $0\dp_XER_xer_so_mul0_4$next[0:0]$2520 + end + attribute \src "issuer_ls180.v:44617.3-44626.6" + process $proc$issuer_ls180.v:44617$2522 + assign { } { } + assign { } { } + assign $0\fus_src3_i$66[0:0]$2523 $1\fus_src3_i$66[0:0]$2524 + attribute \src "issuer_ls180.v:44618.5-44618.29" + switch \initial + attribute \src "issuer_ls180.v:44618.9-44618.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" + switch \dp_XER_xer_so_mul0_4 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_src3_i$66[0:0]$2524 \xer_src1__data_o [0] + case + assign $1\fus_src3_i$66[0:0]$2524 1'0 + end + sync always + update \fus_src3_i$66 $0\fus_src3_i$66[0:0]$2523 + end + attribute \src "issuer_ls180.v:44627.3-44635.6" + process $proc$issuer_ls180.v:44627$2525 + assign { } { } + assign { } { } + assign $0\dp_XER_xer_so_shiftrot0_5$next[0:0]$2526 $1\dp_XER_xer_so_shiftrot0_5$next[0:0]$2527 + attribute \src "issuer_ls180.v:44628.5-44628.29" + switch \initial + attribute \src "issuer_ls180.v:44628.9-44628.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dp_XER_xer_so_shiftrot0_5$next[0:0]$2527 1'0 + case + assign $1\dp_XER_xer_so_shiftrot0_5$next[0:0]$2527 \rp_XER_xer_so_shiftrot0_5 + end + sync always + update \dp_XER_xer_so_shiftrot0_5$next $0\dp_XER_xer_so_shiftrot0_5$next[0:0]$2526 + end + attribute \src "issuer_ls180.v:44636.3-44664.6" + process $proc$issuer_ls180.v:44636$2528 + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_alu0__insn_type[6:0] $1\fus_oper_i_alu_alu0__insn_type[6:0] + attribute \src "issuer_ls180.v:44637.5-44637.29" + switch \initial + attribute \src "issuer_ls180.v:44637.9-44637.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" + switch \ivalid_i + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_alu_alu0__insn_type[6:0] $2\fus_oper_i_alu_alu0__insn_type[6:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" + switch \core_core_insn_type + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_alu0__insn_type[6:0] 7'0000000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_alu0__insn_type[6:0] 7'0000000 + attribute \src "issuer_ls180.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_alu_alu0__insn_type[6:0] $3\fus_oper_i_alu_alu0__insn_type[6:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" + switch \fu_enable [0] + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_alu_alu0__insn_type[6:0] \dec_ALU_ALU_ALU__insn_type + case + assign $3\fus_oper_i_alu_alu0__insn_type[6:0] 7'0000000 + end + end + case + assign $1\fus_oper_i_alu_alu0__insn_type[6:0] 7'0000000 + end + sync always + update \fus_oper_i_alu_alu0__insn_type $0\fus_oper_i_alu_alu0__insn_type[6:0] + end + attribute \src "issuer_ls180.v:44665.3-44674.6" + process $proc$issuer_ls180.v:44665$2529 + assign { } { } + assign { } { } + assign $0\fus_src4_i$67[0:0]$2530 $1\fus_src4_i$67[0:0]$2531 + attribute \src "issuer_ls180.v:44666.5-44666.29" + switch \initial + attribute \src "issuer_ls180.v:44666.9-44666.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" + switch \dp_XER_xer_so_shiftrot0_5 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_src4_i$67[0:0]$2531 \xer_src1__data_o [0] + case + assign $1\fus_src4_i$67[0:0]$2531 1'0 + end + sync always + update \fus_src4_i$67 $0\fus_src4_i$67[0:0]$2530 + end + attribute \src "issuer_ls180.v:44675.3-44683.6" + process $proc$issuer_ls180.v:44675$2532 + assign { } { } + assign { } { } + assign $0\dp_XER_xer_ca_alu0_0$next[0:0]$2533 $1\dp_XER_xer_ca_alu0_0$next[0:0]$2534 + attribute \src "issuer_ls180.v:44676.5-44676.29" + switch \initial + attribute \src "issuer_ls180.v:44676.9-44676.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dp_XER_xer_ca_alu0_0$next[0:0]$2534 1'0 + case + assign $1\dp_XER_xer_ca_alu0_0$next[0:0]$2534 \rp_XER_xer_ca_alu0_0 + end + sync always + update \dp_XER_xer_ca_alu0_0$next $0\dp_XER_xer_ca_alu0_0$next[0:0]$2533 + end + attribute \src "issuer_ls180.v:44684.3-44693.6" + process $proc$issuer_ls180.v:44684$2535 + assign { } { } + assign { } { } + assign $0\fus_src4_i$68[1:0]$2536 $1\fus_src4_i$68[1:0]$2537 + attribute \src "issuer_ls180.v:44685.5-44685.29" + switch \initial + attribute \src "issuer_ls180.v:44685.9-44685.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" + switch \dp_XER_xer_ca_alu0_0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_src4_i$68[1:0]$2537 \xer_src2__data_o + case + assign $1\fus_src4_i$68[1:0]$2537 2'00 + end + sync always + update \fus_src4_i$68 $0\fus_src4_i$68[1:0]$2536 + end + attribute \src "issuer_ls180.v:44694.3-44722.6" + process $proc$issuer_ls180.v:44694$2538 + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_alu0__fn_unit[11:0] $1\fus_oper_i_alu_alu0__fn_unit[11:0] + attribute \src "issuer_ls180.v:44695.5-44695.29" + switch \initial + attribute \src "issuer_ls180.v:44695.9-44695.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" + switch \ivalid_i + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_alu_alu0__fn_unit[11:0] $2\fus_oper_i_alu_alu0__fn_unit[11:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" + switch \core_core_insn_type + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_alu0__fn_unit[11:0] 12'000000000000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_alu0__fn_unit[11:0] 12'000000000000 + attribute \src "issuer_ls180.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_alu_alu0__fn_unit[11:0] $3\fus_oper_i_alu_alu0__fn_unit[11:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" + switch \fu_enable [0] + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_alu_alu0__fn_unit[11:0] \dec_ALU_ALU_ALU__fn_unit + case + assign $3\fus_oper_i_alu_alu0__fn_unit[11:0] 12'000000000000 + end + end + case + assign $1\fus_oper_i_alu_alu0__fn_unit[11:0] 12'000000000000 + end + sync always + update \fus_oper_i_alu_alu0__fn_unit $0\fus_oper_i_alu_alu0__fn_unit[11:0] + end + attribute \src "issuer_ls180.v:44723.3-44731.6" + process $proc$issuer_ls180.v:44723$2539 + assign { } { } + assign { } { } + assign $0\dp_XER_xer_ca_spr0_1$next[0:0]$2540 $1\dp_XER_xer_ca_spr0_1$next[0:0]$2541 + attribute \src "issuer_ls180.v:44724.5-44724.29" + switch \initial + attribute \src "issuer_ls180.v:44724.9-44724.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dp_XER_xer_ca_spr0_1$next[0:0]$2541 1'0 + case + assign $1\dp_XER_xer_ca_spr0_1$next[0:0]$2541 \rp_XER_xer_ca_spr0_1 + end + sync always + update \dp_XER_xer_ca_spr0_1$next $0\dp_XER_xer_ca_spr0_1$next[0:0]$2540 + end + attribute \src "issuer_ls180.v:44732.3-44741.6" + process $proc$issuer_ls180.v:44732$2542 + assign { } { } + assign { } { } + assign $0\fus_src6_i[1:0] $1\fus_src6_i[1:0] + attribute \src "issuer_ls180.v:44733.5-44733.29" + switch \initial + attribute \src "issuer_ls180.v:44733.9-44733.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" + switch \dp_XER_xer_ca_spr0_1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_src6_i[1:0] \xer_src2__data_o + case + assign $1\fus_src6_i[1:0] 2'00 + end + sync always + update \fus_src6_i $0\fus_src6_i[1:0] + end + attribute \src "issuer_ls180.v:44742.3-44750.6" + process $proc$issuer_ls180.v:44742$2543 + assign { } { } + assign { } { } + assign $0\dp_XER_xer_ca_shiftrot0_2$next[0:0]$2544 $1\dp_XER_xer_ca_shiftrot0_2$next[0:0]$2545 + attribute \src "issuer_ls180.v:44743.5-44743.29" + switch \initial + attribute \src "issuer_ls180.v:44743.9-44743.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dp_XER_xer_ca_shiftrot0_2$next[0:0]$2545 1'0 + case + assign $1\dp_XER_xer_ca_shiftrot0_2$next[0:0]$2545 \rp_XER_xer_ca_shiftrot0_2 + end + sync always + update \dp_XER_xer_ca_shiftrot0_2$next $0\dp_XER_xer_ca_shiftrot0_2$next[0:0]$2544 + end + attribute \src "issuer_ls180.v:44751.3-44760.6" + process $proc$issuer_ls180.v:44751$2546 + assign { } { } + assign { } { } + assign $0\fus_src5_i[1:0] $1\fus_src5_i[1:0] + attribute \src "issuer_ls180.v:44752.5-44752.29" + switch \initial + attribute \src "issuer_ls180.v:44752.9-44752.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" + switch \dp_XER_xer_ca_shiftrot0_2 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_src5_i[1:0] \xer_src2__data_o + case + assign $1\fus_src5_i[1:0] 2'00 + end + sync always + update \fus_src5_i $0\fus_src5_i[1:0] + end + attribute \src "issuer_ls180.v:44761.3-44790.6" + process $proc$issuer_ls180.v:44761$2547 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_alu0__imm_data__data[63:0] $1\fus_oper_i_alu_alu0__imm_data__data[63:0] + assign $0\fus_oper_i_alu_alu0__imm_data__ok[0:0] $1\fus_oper_i_alu_alu0__imm_data__ok[0:0] + attribute \src "issuer_ls180.v:44762.5-44762.29" + switch \initial + attribute \src "issuer_ls180.v:44762.9-44762.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" + switch \ivalid_i + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign $1\fus_oper_i_alu_alu0__imm_data__data[63:0] $2\fus_oper_i_alu_alu0__imm_data__data[63:0] + assign $1\fus_oper_i_alu_alu0__imm_data__ok[0:0] $2\fus_oper_i_alu_alu0__imm_data__ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" + switch \core_core_insn_type + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_alu0__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\fus_oper_i_alu_alu0__imm_data__ok[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_alu0__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\fus_oper_i_alu_alu0__imm_data__ok[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case + assign { } { } + assign { } { } + assign $2\fus_oper_i_alu_alu0__imm_data__data[63:0] $3\fus_oper_i_alu_alu0__imm_data__data[63:0] + assign $2\fus_oper_i_alu_alu0__imm_data__ok[0:0] $3\fus_oper_i_alu_alu0__imm_data__ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" + switch \fu_enable [0] + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $3\fus_oper_i_alu_alu0__imm_data__ok[0:0] $3\fus_oper_i_alu_alu0__imm_data__data[63:0] } { \dec_ALU_ALU_ALU__imm_data__ok \dec_ALU_ALU_ALU__imm_data__data } + case + assign $3\fus_oper_i_alu_alu0__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $3\fus_oper_i_alu_alu0__imm_data__ok[0:0] 1'0 + end + end + case + assign $1\fus_oper_i_alu_alu0__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\fus_oper_i_alu_alu0__imm_data__ok[0:0] 1'0 + end + sync always + update \fus_oper_i_alu_alu0__imm_data__data $0\fus_oper_i_alu_alu0__imm_data__data[63:0] + update \fus_oper_i_alu_alu0__imm_data__ok $0\fus_oper_i_alu_alu0__imm_data__ok[0:0] + end + attribute \src "issuer_ls180.v:44791.3-44799.6" + process $proc$issuer_ls180.v:44791$2548 + assign { } { } + assign { } { } + assign $0\dp_XER_xer_ov_spr0_0$next[0:0]$2549 $1\dp_XER_xer_ov_spr0_0$next[0:0]$2550 + attribute \src "issuer_ls180.v:44792.5-44792.29" + switch \initial + attribute \src "issuer_ls180.v:44792.9-44792.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dp_XER_xer_ov_spr0_0$next[0:0]$2550 1'0 + case + assign $1\dp_XER_xer_ov_spr0_0$next[0:0]$2550 \rp_XER_xer_ov_spr0_0 + end + sync always + update \dp_XER_xer_ov_spr0_0$next $0\dp_XER_xer_ov_spr0_0$next[0:0]$2549 + end + attribute \src "issuer_ls180.v:44800.3-44809.6" + process $proc$issuer_ls180.v:44800$2551 + assign { } { } + assign { } { } + assign $0\fus_src5_i$69[1:0]$2552 $1\fus_src5_i$69[1:0]$2553 + attribute \src "issuer_ls180.v:44801.5-44801.29" + switch \initial + attribute \src "issuer_ls180.v:44801.9-44801.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" + switch \dp_XER_xer_ov_spr0_0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_src5_i$69[1:0]$2553 \xer_src3__data_o + case + assign $1\fus_src5_i$69[1:0]$2553 2'00 + end + sync always + update \fus_src5_i$69 $0\fus_src5_i$69[1:0]$2552 + end + attribute \src "issuer_ls180.v:44810.3-44818.6" + process $proc$issuer_ls180.v:44810$2554 + assign { } { } + assign { } { } + assign $0\dp_CR_full_cr_cr0_0$next[0:0]$2555 $1\dp_CR_full_cr_cr0_0$next[0:0]$2556 + attribute \src "issuer_ls180.v:44811.5-44811.29" + switch \initial + attribute \src "issuer_ls180.v:44811.9-44811.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dp_CR_full_cr_cr0_0$next[0:0]$2556 1'0 + case + assign $1\dp_CR_full_cr_cr0_0$next[0:0]$2556 \rp_CR_full_cr_cr0_0 + end + sync always + update \dp_CR_full_cr_cr0_0$next $0\dp_CR_full_cr_cr0_0$next[0:0]$2555 + end + attribute \src "issuer_ls180.v:44819.3-44828.6" + process $proc$issuer_ls180.v:44819$2557 + assign { } { } + assign { } { } + assign $0\fus_src3_i$70[31:0]$2558 $1\fus_src3_i$70[31:0]$2559 + attribute \src "issuer_ls180.v:44820.5-44820.29" + switch \initial + attribute \src "issuer_ls180.v:44820.9-44820.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" + switch \dp_CR_full_cr_cr0_0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_src3_i$70[31:0]$2559 \cr_full_rd__data_o + case + assign $1\fus_src3_i$70[31:0]$2559 0 + end + sync always + update \fus_src3_i$70 $0\fus_src3_i$70[31:0]$2558 + end + attribute \src "issuer_ls180.v:44829.3-44858.6" + process $proc$issuer_ls180.v:44829$2560 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_alu0__rc__ok[0:0] $1\fus_oper_i_alu_alu0__rc__ok[0:0] + assign $0\fus_oper_i_alu_alu0__rc__rc[0:0] $1\fus_oper_i_alu_alu0__rc__rc[0:0] + attribute \src "issuer_ls180.v:44830.5-44830.29" + switch \initial + attribute \src "issuer_ls180.v:44830.9-44830.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" + switch \ivalid_i + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign $1\fus_oper_i_alu_alu0__rc__ok[0:0] $2\fus_oper_i_alu_alu0__rc__ok[0:0] + assign $1\fus_oper_i_alu_alu0__rc__rc[0:0] $2\fus_oper_i_alu_alu0__rc__rc[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" + switch \core_core_insn_type + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_alu0__rc__ok[0:0] 1'0 + assign $2\fus_oper_i_alu_alu0__rc__rc[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_alu0__rc__ok[0:0] 1'0 + assign $2\fus_oper_i_alu_alu0__rc__rc[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case + assign { } { } + assign { } { } + assign $2\fus_oper_i_alu_alu0__rc__ok[0:0] $3\fus_oper_i_alu_alu0__rc__ok[0:0] + assign $2\fus_oper_i_alu_alu0__rc__rc[0:0] $3\fus_oper_i_alu_alu0__rc__rc[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" + switch \fu_enable [0] + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $3\fus_oper_i_alu_alu0__rc__ok[0:0] $3\fus_oper_i_alu_alu0__rc__rc[0:0] } { \dec_ALU_ALU_ALU__rc__ok \dec_ALU_ALU_ALU__rc__rc } + case + assign $3\fus_oper_i_alu_alu0__rc__ok[0:0] 1'0 + assign $3\fus_oper_i_alu_alu0__rc__rc[0:0] 1'0 + end + end + case + assign $1\fus_oper_i_alu_alu0__rc__ok[0:0] 1'0 + assign $1\fus_oper_i_alu_alu0__rc__rc[0:0] 1'0 + end + sync always + update \fus_oper_i_alu_alu0__rc__ok $0\fus_oper_i_alu_alu0__rc__ok[0:0] + update \fus_oper_i_alu_alu0__rc__rc $0\fus_oper_i_alu_alu0__rc__rc[0:0] + end + attribute \src "issuer_ls180.v:44859.3-44867.6" + process $proc$issuer_ls180.v:44859$2561 + assign { } { } + assign { } { } + assign $0\dp_CR_cr_a_cr0_0$next[0:0]$2562 $1\dp_CR_cr_a_cr0_0$next[0:0]$2563 + attribute \src "issuer_ls180.v:44860.5-44860.29" + switch \initial + attribute \src "issuer_ls180.v:44860.9-44860.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dp_CR_cr_a_cr0_0$next[0:0]$2563 1'0 + case + assign $1\dp_CR_cr_a_cr0_0$next[0:0]$2563 \rp_CR_cr_a_cr0_0 + end + sync always + update \dp_CR_cr_a_cr0_0$next $0\dp_CR_cr_a_cr0_0$next[0:0]$2562 + end + attribute \src "issuer_ls180.v:44868.3-44877.6" + process $proc$issuer_ls180.v:44868$2564 + assign { } { } + assign { } { } + assign $0\fus_src4_i$71[3:0]$2565 $1\fus_src4_i$71[3:0]$2566 + attribute \src "issuer_ls180.v:44869.5-44869.29" + switch \initial + attribute \src "issuer_ls180.v:44869.9-44869.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" + switch \dp_CR_cr_a_cr0_0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_src4_i$71[3:0]$2566 \cr_src1__data_o + case + assign $1\fus_src4_i$71[3:0]$2566 4'0000 + end + sync always + update \fus_src4_i$71 $0\fus_src4_i$71[3:0]$2565 + end + attribute \src "issuer_ls180.v:44878.3-44886.6" + process $proc$issuer_ls180.v:44878$2567 + assign { } { } + assign { } { } + assign $0\dp_CR_cr_a_branch0_1$next[0:0]$2568 $1\dp_CR_cr_a_branch0_1$next[0:0]$2569 + attribute \src "issuer_ls180.v:44879.5-44879.29" + switch \initial + attribute \src "issuer_ls180.v:44879.9-44879.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dp_CR_cr_a_branch0_1$next[0:0]$2569 1'0 + case + assign $1\dp_CR_cr_a_branch0_1$next[0:0]$2569 \rp_CR_cr_a_branch0_1 + end + sync always + update \dp_CR_cr_a_branch0_1$next $0\dp_CR_cr_a_branch0_1$next[0:0]$2568 + end + attribute \src "issuer_ls180.v:44887.3-44896.6" + process $proc$issuer_ls180.v:44887$2570 + assign { } { } + assign { } { } + assign $0\fus_src3_i$74[3:0]$2571 $1\fus_src3_i$74[3:0]$2572 + attribute \src "issuer_ls180.v:44888.5-44888.29" + switch \initial + attribute \src "issuer_ls180.v:44888.9-44888.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" + switch \dp_CR_cr_a_branch0_1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_src3_i$74[3:0]$2572 \cr_src1__data_o + case + assign $1\fus_src3_i$74[3:0]$2572 4'0000 + end + sync always + update \fus_src3_i$74 $0\fus_src3_i$74[3:0]$2571 + end + attribute \src "issuer_ls180.v:44897.3-44905.6" + process $proc$issuer_ls180.v:44897$2573 + assign { } { } + assign { } { } + assign $0\dp_CR_cr_b_cr0_0$next[0:0]$2574 $1\dp_CR_cr_b_cr0_0$next[0:0]$2575 + attribute \src "issuer_ls180.v:44898.5-44898.29" + switch \initial + attribute \src "issuer_ls180.v:44898.9-44898.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dp_CR_cr_b_cr0_0$next[0:0]$2575 1'0 + case + assign $1\dp_CR_cr_b_cr0_0$next[0:0]$2575 \rp_CR_cr_b_cr0_0 + end + sync always + update \dp_CR_cr_b_cr0_0$next $0\dp_CR_cr_b_cr0_0$next[0:0]$2574 + end + attribute \src "issuer_ls180.v:44906.3-44915.6" + process $proc$issuer_ls180.v:44906$2576 + assign { } { } + assign { } { } + assign $0\fus_src5_i$75[3:0]$2577 $1\fus_src5_i$75[3:0]$2578 + attribute \src "issuer_ls180.v:44907.5-44907.29" + switch \initial + attribute \src "issuer_ls180.v:44907.9-44907.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" + switch \dp_CR_cr_b_cr0_0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_src5_i$75[3:0]$2578 \cr_src2__data_o + case + assign $1\fus_src5_i$75[3:0]$2578 4'0000 + end + sync always + update \fus_src5_i$75 $0\fus_src5_i$75[3:0]$2577 + end + attribute \src "issuer_ls180.v:44916.3-44945.6" + process $proc$issuer_ls180.v:44916$2579 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_alu0__oe__oe[0:0] $1\fus_oper_i_alu_alu0__oe__oe[0:0] + assign $0\fus_oper_i_alu_alu0__oe__ok[0:0] $1\fus_oper_i_alu_alu0__oe__ok[0:0] + attribute \src "issuer_ls180.v:44917.5-44917.29" + switch \initial + attribute \src "issuer_ls180.v:44917.9-44917.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" + switch \ivalid_i + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign $1\fus_oper_i_alu_alu0__oe__oe[0:0] $2\fus_oper_i_alu_alu0__oe__oe[0:0] + assign $1\fus_oper_i_alu_alu0__oe__ok[0:0] $2\fus_oper_i_alu_alu0__oe__ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" + switch \core_core_insn_type + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_alu0__oe__oe[0:0] 1'0 + assign $2\fus_oper_i_alu_alu0__oe__ok[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_alu0__oe__oe[0:0] 1'0 + assign $2\fus_oper_i_alu_alu0__oe__ok[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case + assign { } { } + assign { } { } + assign $2\fus_oper_i_alu_alu0__oe__oe[0:0] $3\fus_oper_i_alu_alu0__oe__oe[0:0] + assign $2\fus_oper_i_alu_alu0__oe__ok[0:0] $3\fus_oper_i_alu_alu0__oe__ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" + switch \fu_enable [0] + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $3\fus_oper_i_alu_alu0__oe__ok[0:0] $3\fus_oper_i_alu_alu0__oe__oe[0:0] } { \dec_ALU_ALU_ALU__oe__ok \dec_ALU_ALU_ALU__oe__oe } + case + assign $3\fus_oper_i_alu_alu0__oe__oe[0:0] 1'0 + assign $3\fus_oper_i_alu_alu0__oe__ok[0:0] 1'0 + end + end + case + assign $1\fus_oper_i_alu_alu0__oe__oe[0:0] 1'0 + assign $1\fus_oper_i_alu_alu0__oe__ok[0:0] 1'0 + end + sync always + update \fus_oper_i_alu_alu0__oe__oe $0\fus_oper_i_alu_alu0__oe__oe[0:0] + update \fus_oper_i_alu_alu0__oe__ok $0\fus_oper_i_alu_alu0__oe__ok[0:0] + end + attribute \src "issuer_ls180.v:44946.3-44954.6" + process $proc$issuer_ls180.v:44946$2580 + assign { } { } + assign { } { } + assign $0\dp_CR_cr_c_cr0_0$next[0:0]$2581 $1\dp_CR_cr_c_cr0_0$next[0:0]$2582 + attribute \src "issuer_ls180.v:44947.5-44947.29" + switch \initial + attribute \src "issuer_ls180.v:44947.9-44947.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dp_CR_cr_c_cr0_0$next[0:0]$2582 1'0 + case + assign $1\dp_CR_cr_c_cr0_0$next[0:0]$2582 \rp_CR_cr_c_cr0_0 + end + sync always + update \dp_CR_cr_c_cr0_0$next $0\dp_CR_cr_c_cr0_0$next[0:0]$2581 + end + attribute \src "issuer_ls180.v:44955.3-44964.6" + process $proc$issuer_ls180.v:44955$2583 + assign { } { } + assign { } { } + assign $0\fus_src6_i$76[3:0]$2584 $1\fus_src6_i$76[3:0]$2585 + attribute \src "issuer_ls180.v:44956.5-44956.29" + switch \initial + attribute \src "issuer_ls180.v:44956.9-44956.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" + switch \dp_CR_cr_c_cr0_0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_src6_i$76[3:0]$2585 \cr_src3__data_o + case + assign $1\fus_src6_i$76[3:0]$2585 4'0000 + end + sync always + update \fus_src6_i$76 $0\fus_src6_i$76[3:0]$2584 + end + attribute \src "issuer_ls180.v:44965.3-44973.6" + process $proc$issuer_ls180.v:44965$2586 + assign { } { } + assign { } { } + assign $0\dp_FAST_fast1_branch0_0$next[0:0]$2587 $1\dp_FAST_fast1_branch0_0$next[0:0]$2588 + attribute \src "issuer_ls180.v:44966.5-44966.29" + switch \initial + attribute \src "issuer_ls180.v:44966.9-44966.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dp_FAST_fast1_branch0_0$next[0:0]$2588 1'0 + case + assign $1\dp_FAST_fast1_branch0_0$next[0:0]$2588 \rp_FAST_fast1_branch0_0 + end + sync always + update \dp_FAST_fast1_branch0_0$next $0\dp_FAST_fast1_branch0_0$next[0:0]$2587 + end + attribute \src "issuer_ls180.v:44974.3-44983.6" + process $proc$issuer_ls180.v:44974$2589 + assign { } { } + assign { } { } + assign $0\fus_src1_i$77[63:0]$2590 $1\fus_src1_i$77[63:0]$2591 + attribute \src "issuer_ls180.v:44975.5-44975.29" + switch \initial + attribute \src "issuer_ls180.v:44975.9-44975.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" + switch \dp_FAST_fast1_branch0_0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_src1_i$77[63:0]$2591 \fast_src1__data_o + case + assign $1\fus_src1_i$77[63:0]$2591 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \fus_src1_i$77 $0\fus_src1_i$77[63:0]$2590 + end + attribute \src "issuer_ls180.v:44984.3-44992.6" + process $proc$issuer_ls180.v:44984$2592 + assign { } { } + assign { } { } + assign $0\dp_FAST_fast1_trap0_1$next[0:0]$2593 $1\dp_FAST_fast1_trap0_1$next[0:0]$2594 + attribute \src "issuer_ls180.v:44985.5-44985.29" + switch \initial + attribute \src "issuer_ls180.v:44985.9-44985.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dp_FAST_fast1_trap0_1$next[0:0]$2594 1'0 + case + assign $1\dp_FAST_fast1_trap0_1$next[0:0]$2594 \rp_FAST_fast1_trap0_1 + end + sync always + update \dp_FAST_fast1_trap0_1$next $0\dp_FAST_fast1_trap0_1$next[0:0]$2593 + end + attribute \src "issuer_ls180.v:44993.3-45002.6" + process $proc$issuer_ls180.v:44993$2595 + assign { } { } + assign { } { } + assign $0\fus_src3_i$78[63:0]$2596 $1\fus_src3_i$78[63:0]$2597 + attribute \src "issuer_ls180.v:44994.5-44994.29" + switch \initial + attribute \src "issuer_ls180.v:44994.9-44994.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" + switch \dp_FAST_fast1_trap0_1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_src3_i$78[63:0]$2597 \fast_src1__data_o + case + assign $1\fus_src3_i$78[63:0]$2597 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \fus_src3_i$78 $0\fus_src3_i$78[63:0]$2596 + end + attribute \src "issuer_ls180.v:45003.3-45031.6" + process $proc$issuer_ls180.v:45003$2598 + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_alu0__invert_in[0:0] $1\fus_oper_i_alu_alu0__invert_in[0:0] + attribute \src "issuer_ls180.v:45004.5-45004.29" + switch \initial + attribute \src "issuer_ls180.v:45004.9-45004.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" + switch \ivalid_i + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_alu_alu0__invert_in[0:0] $2\fus_oper_i_alu_alu0__invert_in[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" + switch \core_core_insn_type + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_alu0__invert_in[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_alu0__invert_in[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_alu_alu0__invert_in[0:0] $3\fus_oper_i_alu_alu0__invert_in[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" + switch \fu_enable [0] + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_alu_alu0__invert_in[0:0] \dec_ALU_ALU_ALU__invert_in + case + assign $3\fus_oper_i_alu_alu0__invert_in[0:0] 1'0 + end + end + case + assign $1\fus_oper_i_alu_alu0__invert_in[0:0] 1'0 + end + sync always + update \fus_oper_i_alu_alu0__invert_in $0\fus_oper_i_alu_alu0__invert_in[0:0] + end + attribute \src "issuer_ls180.v:45032.3-45040.6" + process $proc$issuer_ls180.v:45032$2599 + assign { } { } + assign { } { } + assign $0\dp_FAST_fast1_spr0_2$next[0:0]$2600 $1\dp_FAST_fast1_spr0_2$next[0:0]$2601 + attribute \src "issuer_ls180.v:45033.5-45033.29" + switch \initial + attribute \src "issuer_ls180.v:45033.9-45033.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dp_FAST_fast1_spr0_2$next[0:0]$2601 1'0 + case + assign $1\dp_FAST_fast1_spr0_2$next[0:0]$2601 \rp_FAST_fast1_spr0_2 + end + sync always + update \dp_FAST_fast1_spr0_2$next $0\dp_FAST_fast1_spr0_2$next[0:0]$2600 + end + attribute \src "issuer_ls180.v:45041.3-45050.6" + process $proc$issuer_ls180.v:45041$2602 + assign { } { } + assign { } { } + assign $0\fus_src3_i$79[63:0]$2603 $1\fus_src3_i$79[63:0]$2604 + attribute \src "issuer_ls180.v:45042.5-45042.29" + switch \initial + attribute \src "issuer_ls180.v:45042.9-45042.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" + switch \dp_FAST_fast1_spr0_2 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_src3_i$79[63:0]$2604 \fast_src1__data_o + case + assign $1\fus_src3_i$79[63:0]$2604 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \fus_src3_i$79 $0\fus_src3_i$79[63:0]$2603 + end + attribute \src "issuer_ls180.v:45051.3-45059.6" + process $proc$issuer_ls180.v:45051$2605 + assign { } { } + assign { } { } + assign $0\dp_FAST_fast2_branch0_0$next[0:0]$2606 $1\dp_FAST_fast2_branch0_0$next[0:0]$2607 + attribute \src "issuer_ls180.v:45052.5-45052.29" + switch \initial + attribute \src "issuer_ls180.v:45052.9-45052.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dp_FAST_fast2_branch0_0$next[0:0]$2607 1'0 + case + assign $1\dp_FAST_fast2_branch0_0$next[0:0]$2607 \rp_FAST_fast2_branch0_0 + end + sync always + update \dp_FAST_fast2_branch0_0$next $0\dp_FAST_fast2_branch0_0$next[0:0]$2606 + end + attribute \src "issuer_ls180.v:45060.3-45088.6" + process $proc$issuer_ls180.v:45060$2608 + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_alu0__zero_a[0:0] $1\fus_oper_i_alu_alu0__zero_a[0:0] + attribute \src "issuer_ls180.v:45061.5-45061.29" + switch \initial + attribute \src "issuer_ls180.v:45061.9-45061.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" + switch \ivalid_i + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_alu_alu0__zero_a[0:0] $2\fus_oper_i_alu_alu0__zero_a[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" + switch \core_core_insn_type + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_alu0__zero_a[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_alu0__zero_a[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_alu_alu0__zero_a[0:0] $3\fus_oper_i_alu_alu0__zero_a[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" + switch \fu_enable [0] + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_alu_alu0__zero_a[0:0] \dec_ALU_ALU_ALU__zero_a + case + assign $3\fus_oper_i_alu_alu0__zero_a[0:0] 1'0 + end + end + case + assign $1\fus_oper_i_alu_alu0__zero_a[0:0] 1'0 + end + sync always + update \fus_oper_i_alu_alu0__zero_a $0\fus_oper_i_alu_alu0__zero_a[0:0] + end + attribute \src "issuer_ls180.v:45089.3-45098.6" + process $proc$issuer_ls180.v:45089$2609 + assign { } { } + assign { } { } + assign $0\fus_src2_i$80[63:0]$2610 $1\fus_src2_i$80[63:0]$2611 + attribute \src "issuer_ls180.v:45090.5-45090.29" + switch \initial + attribute \src "issuer_ls180.v:45090.9-45090.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" + switch \dp_FAST_fast2_branch0_0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_src2_i$80[63:0]$2611 \fast_src2__data_o + case + assign $1\fus_src2_i$80[63:0]$2611 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \fus_src2_i$80 $0\fus_src2_i$80[63:0]$2610 + end + attribute \src "issuer_ls180.v:45099.3-45107.6" + process $proc$issuer_ls180.v:45099$2612 + assign { } { } + assign { } { } + assign $0\dp_FAST_fast2_trap0_1$next[0:0]$2613 $1\dp_FAST_fast2_trap0_1$next[0:0]$2614 + attribute \src "issuer_ls180.v:45100.5-45100.29" + switch \initial + attribute \src "issuer_ls180.v:45100.9-45100.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dp_FAST_fast2_trap0_1$next[0:0]$2614 1'0 + case + assign $1\dp_FAST_fast2_trap0_1$next[0:0]$2614 \rp_FAST_fast2_trap0_1 + end + sync always + update \dp_FAST_fast2_trap0_1$next $0\dp_FAST_fast2_trap0_1$next[0:0]$2613 + end + attribute \src "issuer_ls180.v:45108.3-45117.6" + process $proc$issuer_ls180.v:45108$2615 + assign { } { } + assign { } { } + assign $0\fus_src4_i$81[63:0]$2616 $1\fus_src4_i$81[63:0]$2617 + attribute \src "issuer_ls180.v:45109.5-45109.29" + switch \initial + attribute \src "issuer_ls180.v:45109.9-45109.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" + switch \dp_FAST_fast2_trap0_1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_src4_i$81[63:0]$2617 \fast_src2__data_o + case + assign $1\fus_src4_i$81[63:0]$2617 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \fus_src4_i$81 $0\fus_src4_i$81[63:0]$2616 + end + attribute \src "issuer_ls180.v:45118.3-45146.6" + process $proc$issuer_ls180.v:45118$2618 + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_alu0__invert_out[0:0] $1\fus_oper_i_alu_alu0__invert_out[0:0] + attribute \src "issuer_ls180.v:45119.5-45119.29" + switch \initial + attribute \src "issuer_ls180.v:45119.9-45119.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" + switch \ivalid_i + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_alu_alu0__invert_out[0:0] $2\fus_oper_i_alu_alu0__invert_out[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" + switch \core_core_insn_type + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_alu0__invert_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_alu0__invert_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_alu_alu0__invert_out[0:0] $3\fus_oper_i_alu_alu0__invert_out[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" + switch \fu_enable [0] + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_alu_alu0__invert_out[0:0] \dec_ALU_ALU_ALU__invert_out + case + assign $3\fus_oper_i_alu_alu0__invert_out[0:0] 1'0 + end + end + case + assign $1\fus_oper_i_alu_alu0__invert_out[0:0] 1'0 + end + sync always + update \fus_oper_i_alu_alu0__invert_out $0\fus_oper_i_alu_alu0__invert_out[0:0] + end + attribute \src "issuer_ls180.v:45147.3-45155.6" + process $proc$issuer_ls180.v:45147$2619 + assign { } { } + assign { } { } + assign $0\dp_SPR_spr1_spr0_0$next[0:0]$2620 $1\dp_SPR_spr1_spr0_0$next[0:0]$2621 + attribute \src "issuer_ls180.v:45148.5-45148.29" + switch \initial + attribute \src "issuer_ls180.v:45148.9-45148.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dp_SPR_spr1_spr0_0$next[0:0]$2621 1'0 + case + assign $1\dp_SPR_spr1_spr0_0$next[0:0]$2621 \rp_SPR_spr1_spr0_0 + end + sync always + update \dp_SPR_spr1_spr0_0$next $0\dp_SPR_spr1_spr0_0$next[0:0]$2620 + end + attribute \src "issuer_ls180.v:45156.3-45165.6" + process $proc$issuer_ls180.v:45156$2622 + assign { } { } + assign { } { } + assign $0\fus_src2_i$82[63:0]$2623 $1\fus_src2_i$82[63:0]$2624 + attribute \src "issuer_ls180.v:45157.5-45157.29" + switch \initial + attribute \src "issuer_ls180.v:45157.9-45157.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" + switch \dp_SPR_spr1_spr0_0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_src2_i$82[63:0]$2624 \spr_spr1__data_o + case + assign $1\fus_src2_i$82[63:0]$2624 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \fus_src2_i$82 $0\fus_src2_i$82[63:0]$2623 + end + attribute \src "issuer_ls180.v:45166.3-45194.6" + process $proc$issuer_ls180.v:45166$2625 + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_alu0__write_cr0[0:0] $1\fus_oper_i_alu_alu0__write_cr0[0:0] + attribute \src "issuer_ls180.v:45167.5-45167.29" + switch \initial + attribute \src "issuer_ls180.v:45167.9-45167.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" + switch \ivalid_i + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_alu_alu0__write_cr0[0:0] $2\fus_oper_i_alu_alu0__write_cr0[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" + switch \core_core_insn_type + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_alu0__write_cr0[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_alu0__write_cr0[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_alu_alu0__write_cr0[0:0] $3\fus_oper_i_alu_alu0__write_cr0[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" + switch \fu_enable [0] + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_alu_alu0__write_cr0[0:0] \dec_ALU_ALU_ALU__write_cr0 + case + assign $3\fus_oper_i_alu_alu0__write_cr0[0:0] 1'0 + end + end + case + assign $1\fus_oper_i_alu_alu0__write_cr0[0:0] 1'0 + end + sync always + update \fus_oper_i_alu_alu0__write_cr0 $0\fus_oper_i_alu_alu0__write_cr0[0:0] + end + attribute \src "issuer_ls180.v:45195.3-45203.6" + process $proc$issuer_ls180.v:45195$2626 + assign { } { } + assign { } { } + assign $0\wr_pick_dly$next[0:0]$2627 $1\wr_pick_dly$next[0:0]$2628 + attribute \src "issuer_ls180.v:45196.5-45196.29" + switch \initial + attribute \src "issuer_ls180.v:45196.9-45196.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\wr_pick_dly$next[0:0]$2628 1'0 + case + assign $1\wr_pick_dly$next[0:0]$2628 \wr_pick + end + sync always + update \wr_pick_dly$next $0\wr_pick_dly$next[0:0]$2627 + end + attribute \src "issuer_ls180.v:45204.3-45212.6" + process $proc$issuer_ls180.v:45204$2629 + assign { } { } + assign { } { } + assign $0\wr_pick_dly$967$next[0:0]$2630 $1\wr_pick_dly$967$next[0:0]$2631 + attribute \src "issuer_ls180.v:45205.5-45205.29" + switch \initial + attribute \src "issuer_ls180.v:45205.9-45205.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\wr_pick_dly$967$next[0:0]$2631 1'0 + case + assign $1\wr_pick_dly$967$next[0:0]$2631 \wr_pick$964 + end + sync always + update \wr_pick_dly$967$next $0\wr_pick_dly$967$next[0:0]$2630 + end + attribute \src "issuer_ls180.v:45213.3-45241.6" + process $proc$issuer_ls180.v:45213$2632 + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_alu0__input_carry[1:0] $1\fus_oper_i_alu_alu0__input_carry[1:0] + attribute \src "issuer_ls180.v:45214.5-45214.29" + switch \initial + attribute \src "issuer_ls180.v:45214.9-45214.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" + switch \ivalid_i + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_alu_alu0__input_carry[1:0] $2\fus_oper_i_alu_alu0__input_carry[1:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" + switch \core_core_insn_type + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_alu0__input_carry[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_alu0__input_carry[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_alu_alu0__input_carry[1:0] $3\fus_oper_i_alu_alu0__input_carry[1:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" + switch \fu_enable [0] + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_alu_alu0__input_carry[1:0] \dec_ALU_ALU_ALU__input_carry + case + assign $3\fus_oper_i_alu_alu0__input_carry[1:0] 2'00 + end + end + case + assign $1\fus_oper_i_alu_alu0__input_carry[1:0] 2'00 + end + sync always + update \fus_oper_i_alu_alu0__input_carry $0\fus_oper_i_alu_alu0__input_carry[1:0] + end + attribute \src "issuer_ls180.v:45242.3-45250.6" + process $proc$issuer_ls180.v:45242$2633 + assign { } { } + assign { } { } + assign $0\wr_pick_dly$986$next[0:0]$2634 $1\wr_pick_dly$986$next[0:0]$2635 + attribute \src "issuer_ls180.v:45243.5-45243.29" + switch \initial + attribute \src "issuer_ls180.v:45243.9-45243.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\wr_pick_dly$986$next[0:0]$2635 1'0 + case + assign $1\wr_pick_dly$986$next[0:0]$2635 \wr_pick$983 + end + sync always + update \wr_pick_dly$986$next $0\wr_pick_dly$986$next[0:0]$2634 + end + attribute \src "issuer_ls180.v:45251.3-45279.6" + process $proc$issuer_ls180.v:45251$2636 + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_alu0__output_carry[0:0] $1\fus_oper_i_alu_alu0__output_carry[0:0] + attribute \src "issuer_ls180.v:45252.5-45252.29" + switch \initial + attribute \src "issuer_ls180.v:45252.9-45252.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" + switch \ivalid_i + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_alu_alu0__output_carry[0:0] $2\fus_oper_i_alu_alu0__output_carry[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" + switch \core_core_insn_type + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_alu0__output_carry[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_alu0__output_carry[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_alu_alu0__output_carry[0:0] $3\fus_oper_i_alu_alu0__output_carry[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" + switch \fu_enable [0] + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_alu_alu0__output_carry[0:0] \dec_ALU_ALU_ALU__output_carry + case + assign $3\fus_oper_i_alu_alu0__output_carry[0:0] 1'0 + end + end + case + assign $1\fus_oper_i_alu_alu0__output_carry[0:0] 1'0 + end + sync always + update \fus_oper_i_alu_alu0__output_carry $0\fus_oper_i_alu_alu0__output_carry[0:0] + end + attribute \src "issuer_ls180.v:45280.3-45288.6" + process $proc$issuer_ls180.v:45280$2637 + assign { } { } + assign { } { } + assign $0\wr_pick_dly$1007$next[0:0]$2638 $1\wr_pick_dly$1007$next[0:0]$2639 + attribute \src "issuer_ls180.v:45281.5-45281.29" + switch \initial + attribute \src "issuer_ls180.v:45281.9-45281.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\wr_pick_dly$1007$next[0:0]$2639 1'0 + case + assign $1\wr_pick_dly$1007$next[0:0]$2639 \wr_pick$1004 + end + sync always + update \wr_pick_dly$1007$next $0\wr_pick_dly$1007$next[0:0]$2638 + end + attribute \src "issuer_ls180.v:45289.3-45297.6" + process $proc$issuer_ls180.v:45289$2640 + assign { } { } + assign { } { } + assign $0\wr_pick_dly$1025$next[0:0]$2641 $1\wr_pick_dly$1025$next[0:0]$2642 + attribute \src "issuer_ls180.v:45290.5-45290.29" + switch \initial + attribute \src "issuer_ls180.v:45290.9-45290.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\wr_pick_dly$1025$next[0:0]$2642 1'0 + case + assign $1\wr_pick_dly$1025$next[0:0]$2642 \wr_pick$1022 + end + sync always + update \wr_pick_dly$1025$next $0\wr_pick_dly$1025$next[0:0]$2641 + end + attribute \src "issuer_ls180.v:45298.3-45326.6" + process $proc$issuer_ls180.v:45298$2643 + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_alu0__is_32bit[0:0] $1\fus_oper_i_alu_alu0__is_32bit[0:0] + attribute \src "issuer_ls180.v:45299.5-45299.29" + switch \initial + attribute \src "issuer_ls180.v:45299.9-45299.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" + switch \ivalid_i + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_alu_alu0__is_32bit[0:0] $2\fus_oper_i_alu_alu0__is_32bit[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" + switch \core_core_insn_type + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_alu0__is_32bit[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_alu0__is_32bit[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_alu_alu0__is_32bit[0:0] $3\fus_oper_i_alu_alu0__is_32bit[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" + switch \fu_enable [0] + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_alu_alu0__is_32bit[0:0] \dec_ALU_ALU_ALU__is_32bit + case + assign $3\fus_oper_i_alu_alu0__is_32bit[0:0] 1'0 + end + end + case + assign $1\fus_oper_i_alu_alu0__is_32bit[0:0] 1'0 + end + sync always + update \fus_oper_i_alu_alu0__is_32bit $0\fus_oper_i_alu_alu0__is_32bit[0:0] + end + attribute \src "issuer_ls180.v:45327.3-45335.6" + process $proc$issuer_ls180.v:45327$2644 + assign { } { } + assign { } { } + assign $0\wr_pick_dly$1047$next[0:0]$2645 $1\wr_pick_dly$1047$next[0:0]$2646 + attribute \src "issuer_ls180.v:45328.5-45328.29" + switch \initial + attribute \src "issuer_ls180.v:45328.9-45328.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\wr_pick_dly$1047$next[0:0]$2646 1'0 + case + assign $1\wr_pick_dly$1047$next[0:0]$2646 \wr_pick$1044 + end + sync always + update \wr_pick_dly$1047$next $0\wr_pick_dly$1047$next[0:0]$2645 + end + attribute \src "issuer_ls180.v:45336.3-45364.6" + process $proc$issuer_ls180.v:45336$2647 + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_alu0__is_signed[0:0] $1\fus_oper_i_alu_alu0__is_signed[0:0] + attribute \src "issuer_ls180.v:45337.5-45337.29" + switch \initial + attribute \src "issuer_ls180.v:45337.9-45337.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" + switch \ivalid_i + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_alu_alu0__is_signed[0:0] $2\fus_oper_i_alu_alu0__is_signed[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" + switch \core_core_insn_type + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_alu0__is_signed[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_alu0__is_signed[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_alu_alu0__is_signed[0:0] $3\fus_oper_i_alu_alu0__is_signed[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" + switch \fu_enable [0] + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_alu_alu0__is_signed[0:0] \dec_ALU_ALU_ALU__is_signed + case + assign $3\fus_oper_i_alu_alu0__is_signed[0:0] 1'0 + end + end + case + assign $1\fus_oper_i_alu_alu0__is_signed[0:0] 1'0 + end + sync always + update \fus_oper_i_alu_alu0__is_signed $0\fus_oper_i_alu_alu0__is_signed[0:0] + end + attribute \src "issuer_ls180.v:45365.3-45373.6" + process $proc$issuer_ls180.v:45365$2648 + assign { } { } + assign { } { } + assign $0\wr_pick_dly$1067$next[0:0]$2649 $1\wr_pick_dly$1067$next[0:0]$2650 + attribute \src "issuer_ls180.v:45366.5-45366.29" + switch \initial + attribute \src "issuer_ls180.v:45366.9-45366.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\wr_pick_dly$1067$next[0:0]$2650 1'0 + case + assign $1\wr_pick_dly$1067$next[0:0]$2650 \wr_pick$1064 + end + sync always + update \wr_pick_dly$1067$next $0\wr_pick_dly$1067$next[0:0]$2649 + end + attribute \src "issuer_ls180.v:45374.3-45402.6" + process $proc$issuer_ls180.v:45374$2651 + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_alu0__data_len[3:0] $1\fus_oper_i_alu_alu0__data_len[3:0] + attribute \src "issuer_ls180.v:45375.5-45375.29" + switch \initial + attribute \src "issuer_ls180.v:45375.9-45375.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" + switch \ivalid_i + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_alu_alu0__data_len[3:0] $2\fus_oper_i_alu_alu0__data_len[3:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" + switch \core_core_insn_type + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_alu0__data_len[3:0] 4'0000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_alu0__data_len[3:0] 4'0000 + attribute \src "issuer_ls180.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_alu_alu0__data_len[3:0] $3\fus_oper_i_alu_alu0__data_len[3:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" + switch \fu_enable [0] + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_alu_alu0__data_len[3:0] \dec_ALU_ALU_ALU__data_len + case + assign $3\fus_oper_i_alu_alu0__data_len[3:0] 4'0000 + end + end + case + assign $1\fus_oper_i_alu_alu0__data_len[3:0] 4'0000 + end + sync always + update \fus_oper_i_alu_alu0__data_len $0\fus_oper_i_alu_alu0__data_len[3:0] + end + attribute \src "issuer_ls180.v:45403.3-45411.6" + process $proc$issuer_ls180.v:45403$2652 + assign { } { } + assign { } { } + assign $0\wr_pick_dly$1087$next[0:0]$2653 $1\wr_pick_dly$1087$next[0:0]$2654 + attribute \src "issuer_ls180.v:45404.5-45404.29" + switch \initial + attribute \src "issuer_ls180.v:45404.9-45404.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\wr_pick_dly$1087$next[0:0]$2654 1'0 + case + assign $1\wr_pick_dly$1087$next[0:0]$2654 \wr_pick$1084 + end + sync always + update \wr_pick_dly$1087$next $0\wr_pick_dly$1087$next[0:0]$2653 + end + attribute \src "issuer_ls180.v:45412.3-45420.6" + process $proc$issuer_ls180.v:45412$2655 + assign { } { } + assign { } { } + assign $0\wr_pick_dly$1106$next[0:0]$2656 $1\wr_pick_dly$1106$next[0:0]$2657 + attribute \src "issuer_ls180.v:45413.5-45413.29" + switch \initial + attribute \src "issuer_ls180.v:45413.9-45413.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\wr_pick_dly$1106$next[0:0]$2657 1'0 + case + assign $1\wr_pick_dly$1106$next[0:0]$2657 \wr_pick$1103 + end + sync always + update \wr_pick_dly$1106$next $0\wr_pick_dly$1106$next[0:0]$2656 + end + attribute \src "issuer_ls180.v:45421.3-45449.6" + process $proc$issuer_ls180.v:45421$2658 + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_alu0__insn[31:0] $1\fus_oper_i_alu_alu0__insn[31:0] + attribute \src "issuer_ls180.v:45422.5-45422.29" + switch \initial + attribute \src "issuer_ls180.v:45422.9-45422.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" + switch \ivalid_i + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_alu_alu0__insn[31:0] $2\fus_oper_i_alu_alu0__insn[31:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" + switch \core_core_insn_type + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_alu0__insn[31:0] 0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_alu0__insn[31:0] 0 + attribute \src "issuer_ls180.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_alu_alu0__insn[31:0] $3\fus_oper_i_alu_alu0__insn[31:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" + switch \fu_enable [0] + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_alu_alu0__insn[31:0] \dec_ALU_ALU_ALU__insn + case + assign $3\fus_oper_i_alu_alu0__insn[31:0] 0 + end + end + case + assign $1\fus_oper_i_alu_alu0__insn[31:0] 0 + end + sync always + update \fus_oper_i_alu_alu0__insn $0\fus_oper_i_alu_alu0__insn[31:0] + end + attribute \src "issuer_ls180.v:45450.3-45458.6" + process $proc$issuer_ls180.v:45450$2659 + assign { } { } + assign { } { } + assign $0\wr_pick_dly$1124$next[0:0]$2660 $1\wr_pick_dly$1124$next[0:0]$2661 + attribute \src "issuer_ls180.v:45451.5-45451.29" + switch \initial + attribute \src "issuer_ls180.v:45451.9-45451.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\wr_pick_dly$1124$next[0:0]$2661 1'0 + case + assign $1\wr_pick_dly$1124$next[0:0]$2661 \wr_pick$1121 + end + sync always + update \wr_pick_dly$1124$next $0\wr_pick_dly$1124$next[0:0]$2660 + end + attribute \src "issuer_ls180.v:45459.3-45487.6" + process $proc$issuer_ls180.v:45459$2662 + assign { } { } + assign { } { } + assign $0\fus_cu_issue_i[0:0] $1\fus_cu_issue_i[0:0] + attribute \src "issuer_ls180.v:45460.5-45460.29" + switch \initial + attribute \src "issuer_ls180.v:45460.9-45460.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" + switch \ivalid_i + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_cu_issue_i[0:0] $2\fus_cu_issue_i[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" + switch \core_core_insn_type + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'0000101 + assign $2\fus_cu_issue_i[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'0000001 + assign $2\fus_cu_issue_i[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case + assign { } { } + assign $2\fus_cu_issue_i[0:0] $3\fus_cu_issue_i[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" + switch \fu_enable [0] + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_cu_issue_i[0:0] \issue_i + case + assign $3\fus_cu_issue_i[0:0] 1'0 + end + end + case + assign $1\fus_cu_issue_i[0:0] 1'0 + end + sync always + update \fus_cu_issue_i $0\fus_cu_issue_i[0:0] + end + attribute \src "issuer_ls180.v:45488.3-45496.6" + process $proc$issuer_ls180.v:45488$2663 + assign { } { } + assign { } { } + assign $0\wr_pick_dly$1197$next[0:0]$2664 $1\wr_pick_dly$1197$next[0:0]$2665 + attribute \src "issuer_ls180.v:45489.5-45489.29" + switch \initial + attribute \src "issuer_ls180.v:45489.9-45489.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\wr_pick_dly$1197$next[0:0]$2665 1'0 + case + assign $1\wr_pick_dly$1197$next[0:0]$2665 \wr_pick$1194 + end + sync always + update \wr_pick_dly$1197$next $0\wr_pick_dly$1197$next[0:0]$2664 + end + attribute \src "issuer_ls180.v:45497.3-45525.6" + process $proc$issuer_ls180.v:45497$2666 + assign { } { } + assign { } { } + assign $0\fus_cu_rdmaskn_i[3:0] $1\fus_cu_rdmaskn_i[3:0] + attribute \src "issuer_ls180.v:45498.5-45498.29" + switch \initial + attribute \src "issuer_ls180.v:45498.9-45498.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" + switch \ivalid_i + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_cu_rdmaskn_i[3:0] $2\fus_cu_rdmaskn_i[3:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" + switch \core_core_insn_type + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'0000101 + assign $2\fus_cu_rdmaskn_i[3:0] 4'0000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'0000001 + assign $2\fus_cu_rdmaskn_i[3:0] 4'0000 + attribute \src "issuer_ls180.v:0.0-0.0" + case + assign { } { } + assign $2\fus_cu_rdmaskn_i[3:0] $3\fus_cu_rdmaskn_i[3:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" + switch \fu_enable [0] + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_cu_rdmaskn_i[3:0] \$207 + case + assign $3\fus_cu_rdmaskn_i[3:0] 4'0000 + end + end + case + assign $1\fus_cu_rdmaskn_i[3:0] 4'0000 + end + sync always + update \fus_cu_rdmaskn_i $0\fus_cu_rdmaskn_i[3:0] + end + attribute \src "issuer_ls180.v:45526.3-45534.6" + process $proc$issuer_ls180.v:45526$2667 + assign { } { } + assign { } { } + assign $0\wr_pick_dly$1225$next[0:0]$2668 $1\wr_pick_dly$1225$next[0:0]$2669 + attribute \src "issuer_ls180.v:45527.5-45527.29" + switch \initial + attribute \src "issuer_ls180.v:45527.9-45527.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\wr_pick_dly$1225$next[0:0]$2669 1'0 + case + assign $1\wr_pick_dly$1225$next[0:0]$2669 \wr_pick$1222 + end + sync always + update \wr_pick_dly$1225$next $0\wr_pick_dly$1225$next[0:0]$2668 + end + attribute \src "issuer_ls180.v:45535.3-45543.6" + process $proc$issuer_ls180.v:45535$2670 + assign { } { } + assign { } { } + assign $0\wr_pick_dly$1245$next[0:0]$2671 $1\wr_pick_dly$1245$next[0:0]$2672 + attribute \src "issuer_ls180.v:45536.5-45536.29" + switch \initial + attribute \src "issuer_ls180.v:45536.9-45536.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\wr_pick_dly$1245$next[0:0]$2672 1'0 + case + assign $1\wr_pick_dly$1245$next[0:0]$2672 \wr_pick$1242 + end + sync always + update \wr_pick_dly$1245$next $0\wr_pick_dly$1245$next[0:0]$2671 + end + attribute \src "issuer_ls180.v:45544.3-45572.6" + process $proc$issuer_ls180.v:45544$2673 + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_cr0__insn_type[6:0] $1\fus_oper_i_alu_cr0__insn_type[6:0] + attribute \src "issuer_ls180.v:45545.5-45545.29" + switch \initial + attribute \src "issuer_ls180.v:45545.9-45545.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" + switch \ivalid_i + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_alu_cr0__insn_type[6:0] $2\fus_oper_i_alu_cr0__insn_type[6:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" + switch \core_core_insn_type + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_cr0__insn_type[6:0] 7'0000000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_cr0__insn_type[6:0] 7'0000000 + attribute \src "issuer_ls180.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_alu_cr0__insn_type[6:0] $3\fus_oper_i_alu_cr0__insn_type[6:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" + switch \fu_enable [1] + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_alu_cr0__insn_type[6:0] \dec_CR_CR_CR__insn_type + case + assign $3\fus_oper_i_alu_cr0__insn_type[6:0] 7'0000000 + end + end + case + assign $1\fus_oper_i_alu_cr0__insn_type[6:0] 7'0000000 + end + sync always + update \fus_oper_i_alu_cr0__insn_type $0\fus_oper_i_alu_cr0__insn_type[6:0] + end + attribute \src "issuer_ls180.v:45573.3-45581.6" + process $proc$issuer_ls180.v:45573$2674 + assign { } { } + assign { } { } + assign $0\wr_pick_dly$1265$next[0:0]$2675 $1\wr_pick_dly$1265$next[0:0]$2676 + attribute \src "issuer_ls180.v:45574.5-45574.29" + switch \initial + attribute \src "issuer_ls180.v:45574.9-45574.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\wr_pick_dly$1265$next[0:0]$2676 1'0 + case + assign $1\wr_pick_dly$1265$next[0:0]$2676 \wr_pick$1262 + end + sync always + update \wr_pick_dly$1265$next $0\wr_pick_dly$1265$next[0:0]$2675 + end + attribute \src "issuer_ls180.v:45582.3-45610.6" + process $proc$issuer_ls180.v:45582$2677 + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_cr0__fn_unit[11:0] $1\fus_oper_i_alu_cr0__fn_unit[11:0] + attribute \src "issuer_ls180.v:45583.5-45583.29" + switch \initial + attribute \src "issuer_ls180.v:45583.9-45583.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" + switch \ivalid_i + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_alu_cr0__fn_unit[11:0] $2\fus_oper_i_alu_cr0__fn_unit[11:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" + switch \core_core_insn_type + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_cr0__fn_unit[11:0] 12'000000000000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_cr0__fn_unit[11:0] 12'000000000000 + attribute \src "issuer_ls180.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_alu_cr0__fn_unit[11:0] $3\fus_oper_i_alu_cr0__fn_unit[11:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" + switch \fu_enable [1] + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_alu_cr0__fn_unit[11:0] \dec_CR_CR_CR__fn_unit + case + assign $3\fus_oper_i_alu_cr0__fn_unit[11:0] 12'000000000000 + end + end + case + assign $1\fus_oper_i_alu_cr0__fn_unit[11:0] 12'000000000000 + end + sync always + update \fus_oper_i_alu_cr0__fn_unit $0\fus_oper_i_alu_cr0__fn_unit[11:0] + end + attribute \src "issuer_ls180.v:45611.3-45619.6" + process $proc$issuer_ls180.v:45611$2678 + assign { } { } + assign { } { } + assign $0\wr_pick_dly$1285$next[0:0]$2679 $1\wr_pick_dly$1285$next[0:0]$2680 + attribute \src "issuer_ls180.v:45612.5-45612.29" + switch \initial + attribute \src "issuer_ls180.v:45612.9-45612.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\wr_pick_dly$1285$next[0:0]$2680 1'0 + case + assign $1\wr_pick_dly$1285$next[0:0]$2680 \wr_pick$1282 + end + sync always + update \wr_pick_dly$1285$next $0\wr_pick_dly$1285$next[0:0]$2679 + end + attribute \src "issuer_ls180.v:45620.3-45628.6" + process $proc$issuer_ls180.v:45620$2681 + assign { } { } + assign { } { } + assign $0\wr_pick_dly$1305$next[0:0]$2682 $1\wr_pick_dly$1305$next[0:0]$2683 + attribute \src "issuer_ls180.v:45621.5-45621.29" + switch \initial + attribute \src "issuer_ls180.v:45621.9-45621.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\wr_pick_dly$1305$next[0:0]$2683 1'0 + case + assign $1\wr_pick_dly$1305$next[0:0]$2683 \wr_pick$1302 + end + sync always + update \wr_pick_dly$1305$next $0\wr_pick_dly$1305$next[0:0]$2682 + end + attribute \src "issuer_ls180.v:45629.3-45657.6" + process $proc$issuer_ls180.v:45629$2684 + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_cr0__insn[31:0] $1\fus_oper_i_alu_cr0__insn[31:0] + attribute \src "issuer_ls180.v:45630.5-45630.29" + switch \initial + attribute \src "issuer_ls180.v:45630.9-45630.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" + switch \ivalid_i + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_alu_cr0__insn[31:0] $2\fus_oper_i_alu_cr0__insn[31:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" + switch \core_core_insn_type + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_cr0__insn[31:0] 0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_cr0__insn[31:0] 0 + attribute \src "issuer_ls180.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_alu_cr0__insn[31:0] $3\fus_oper_i_alu_cr0__insn[31:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" + switch \fu_enable [1] + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_alu_cr0__insn[31:0] \dec_CR_CR_CR__insn + case + assign $3\fus_oper_i_alu_cr0__insn[31:0] 0 + end + end + case + assign $1\fus_oper_i_alu_cr0__insn[31:0] 0 + end + sync always + update \fus_oper_i_alu_cr0__insn $0\fus_oper_i_alu_cr0__insn[31:0] + end + attribute \src "issuer_ls180.v:45658.3-45666.6" + process $proc$issuer_ls180.v:45658$2685 + assign { } { } + assign { } { } + assign $0\wr_pick_dly$1325$next[0:0]$2686 $1\wr_pick_dly$1325$next[0:0]$2687 + attribute \src "issuer_ls180.v:45659.5-45659.29" + switch \initial + attribute \src "issuer_ls180.v:45659.9-45659.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\wr_pick_dly$1325$next[0:0]$2687 1'0 + case + assign $1\wr_pick_dly$1325$next[0:0]$2687 \wr_pick$1322 + end + sync always + update \wr_pick_dly$1325$next $0\wr_pick_dly$1325$next[0:0]$2686 + end + attribute \src "issuer_ls180.v:45667.3-45695.6" + process $proc$issuer_ls180.v:45667$2688 + assign { } { } + assign { } { } + assign $0\fus_cu_issue_i$4[0:0]$2689 $1\fus_cu_issue_i$4[0:0]$2690 + attribute \src "issuer_ls180.v:45668.5-45668.29" + switch \initial + attribute \src "issuer_ls180.v:45668.9-45668.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" + switch \ivalid_i + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_cu_issue_i$4[0:0]$2690 $2\fus_cu_issue_i$4[0:0]$2691 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" + switch \core_core_insn_type + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'0000101 + assign $2\fus_cu_issue_i$4[0:0]$2691 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'0000001 + assign $2\fus_cu_issue_i$4[0:0]$2691 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case + assign { } { } + assign $2\fus_cu_issue_i$4[0:0]$2691 $3\fus_cu_issue_i$4[0:0]$2692 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" + switch \fu_enable [1] + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_cu_issue_i$4[0:0]$2692 \issue_i + case + assign $3\fus_cu_issue_i$4[0:0]$2692 1'0 + end + end + case + assign $1\fus_cu_issue_i$4[0:0]$2690 1'0 + end + sync always + update \fus_cu_issue_i$4 $0\fus_cu_issue_i$4[0:0]$2689 + end + attribute \src "issuer_ls180.v:45696.3-45704.6" + process $proc$issuer_ls180.v:45696$2693 + assign { } { } + assign { } { } + assign $0\wr_pick_dly$1372$next[0:0]$2694 $1\wr_pick_dly$1372$next[0:0]$2695 + attribute \src "issuer_ls180.v:45697.5-45697.29" + switch \initial + attribute \src "issuer_ls180.v:45697.9-45697.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\wr_pick_dly$1372$next[0:0]$2695 1'0 + case + assign $1\wr_pick_dly$1372$next[0:0]$2695 \wr_pick$1369 + end + sync always + update \wr_pick_dly$1372$next $0\wr_pick_dly$1372$next[0:0]$2694 + end + attribute \src "issuer_ls180.v:45705.3-45713.6" + process $proc$issuer_ls180.v:45705$2696 + assign { } { } + assign { } { } + assign $0\wr_pick_dly$1388$next[0:0]$2697 $1\wr_pick_dly$1388$next[0:0]$2698 + attribute \src "issuer_ls180.v:45706.5-45706.29" + switch \initial + attribute \src "issuer_ls180.v:45706.9-45706.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\wr_pick_dly$1388$next[0:0]$2698 1'0 + case + assign $1\wr_pick_dly$1388$next[0:0]$2698 \wr_pick$1385 + end + sync always + update \wr_pick_dly$1388$next $0\wr_pick_dly$1388$next[0:0]$2697 + end + attribute \src "issuer_ls180.v:45714.3-45742.6" + process $proc$issuer_ls180.v:45714$2699 + assign { } { } + assign { } { } + assign $0\fus_cu_rdmaskn_i$6[5:0]$2700 $1\fus_cu_rdmaskn_i$6[5:0]$2701 + attribute \src "issuer_ls180.v:45715.5-45715.29" + switch \initial + attribute \src "issuer_ls180.v:45715.9-45715.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" + switch \ivalid_i + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_cu_rdmaskn_i$6[5:0]$2701 $2\fus_cu_rdmaskn_i$6[5:0]$2702 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" + switch \core_core_insn_type + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'0000101 + assign $2\fus_cu_rdmaskn_i$6[5:0]$2702 6'000000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'0000001 + assign $2\fus_cu_rdmaskn_i$6[5:0]$2702 6'000000 + attribute \src "issuer_ls180.v:0.0-0.0" + case + assign { } { } + assign $2\fus_cu_rdmaskn_i$6[5:0]$2702 $3\fus_cu_rdmaskn_i$6[5:0]$2703 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" + switch \fu_enable [1] + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_cu_rdmaskn_i$6[5:0]$2703 \$229 + case + assign $3\fus_cu_rdmaskn_i$6[5:0]$2703 6'000000 + end + end + case + assign $1\fus_cu_rdmaskn_i$6[5:0]$2701 6'000000 + end + sync always + update \fus_cu_rdmaskn_i$6 $0\fus_cu_rdmaskn_i$6[5:0]$2700 + end + attribute \src "issuer_ls180.v:45743.3-45751.6" + process $proc$issuer_ls180.v:45743$2704 + assign { } { } + assign { } { } + assign $0\wr_pick_dly$1404$next[0:0]$2705 $1\wr_pick_dly$1404$next[0:0]$2706 + attribute \src "issuer_ls180.v:45744.5-45744.29" + switch \initial + attribute \src "issuer_ls180.v:45744.9-45744.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\wr_pick_dly$1404$next[0:0]$2706 1'0 + case + assign $1\wr_pick_dly$1404$next[0:0]$2706 \wr_pick$1401 + end + sync always + update \wr_pick_dly$1404$next $0\wr_pick_dly$1404$next[0:0]$2705 + end + attribute \src "issuer_ls180.v:45752.3-45780.6" + process $proc$issuer_ls180.v:45752$2707 + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_branch0__cia[63:0] $1\fus_oper_i_alu_branch0__cia[63:0] + attribute \src "issuer_ls180.v:45753.5-45753.29" + switch \initial + attribute \src "issuer_ls180.v:45753.9-45753.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" + switch \ivalid_i + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_alu_branch0__cia[63:0] $2\fus_oper_i_alu_branch0__cia[63:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" + switch \core_core_insn_type + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_branch0__cia[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_branch0__cia[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "issuer_ls180.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_alu_branch0__cia[63:0] $3\fus_oper_i_alu_branch0__cia[63:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" + switch \fu_enable [2] + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_alu_branch0__cia[63:0] \dec_BRANCH_BRANCH_BRANCH__cia + case + assign $3\fus_oper_i_alu_branch0__cia[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + end + case + assign $1\fus_oper_i_alu_branch0__cia[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \fus_oper_i_alu_branch0__cia $0\fus_oper_i_alu_branch0__cia[63:0] + end + attribute \src "issuer_ls180.v:45781.3-45789.6" + process $proc$issuer_ls180.v:45781$2708 + assign { } { } + assign { } { } + assign $0\wr_pick_dly$1438$next[0:0]$2709 $1\wr_pick_dly$1438$next[0:0]$2710 + attribute \src "issuer_ls180.v:45782.5-45782.29" + switch \initial + attribute \src "issuer_ls180.v:45782.9-45782.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\wr_pick_dly$1438$next[0:0]$2710 1'0 + case + assign $1\wr_pick_dly$1438$next[0:0]$2710 \wr_pick$1435 + end + sync always + update \wr_pick_dly$1438$next $0\wr_pick_dly$1438$next[0:0]$2709 + end + attribute \src "issuer_ls180.v:45790.3-45798.6" + process $proc$issuer_ls180.v:45790$2711 + assign { } { } + assign { } { } + assign $0\wr_pick_dly$1454$next[0:0]$2712 $1\wr_pick_dly$1454$next[0:0]$2713 + attribute \src "issuer_ls180.v:45791.5-45791.29" + switch \initial + attribute \src "issuer_ls180.v:45791.9-45791.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\wr_pick_dly$1454$next[0:0]$2713 1'0 + case + assign $1\wr_pick_dly$1454$next[0:0]$2713 \wr_pick$1451 + end + sync always + update \wr_pick_dly$1454$next $0\wr_pick_dly$1454$next[0:0]$2712 + end + attribute \src "issuer_ls180.v:45799.3-45827.6" + process $proc$issuer_ls180.v:45799$2714 + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_branch0__insn_type[6:0] $1\fus_oper_i_alu_branch0__insn_type[6:0] + attribute \src "issuer_ls180.v:45800.5-45800.29" + switch \initial + attribute \src "issuer_ls180.v:45800.9-45800.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" + switch \ivalid_i + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_alu_branch0__insn_type[6:0] $2\fus_oper_i_alu_branch0__insn_type[6:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" + switch \core_core_insn_type + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_branch0__insn_type[6:0] 7'0000000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_branch0__insn_type[6:0] 7'0000000 + attribute \src "issuer_ls180.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_alu_branch0__insn_type[6:0] $3\fus_oper_i_alu_branch0__insn_type[6:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" + switch \fu_enable [2] + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_alu_branch0__insn_type[6:0] \dec_BRANCH_BRANCH_BRANCH__insn_type + case + assign $3\fus_oper_i_alu_branch0__insn_type[6:0] 7'0000000 + end + end + case + assign $1\fus_oper_i_alu_branch0__insn_type[6:0] 7'0000000 + end + sync always + update \fus_oper_i_alu_branch0__insn_type $0\fus_oper_i_alu_branch0__insn_type[6:0] + end + attribute \src "issuer_ls180.v:45828.3-45836.6" + process $proc$issuer_ls180.v:45828$2715 + assign { } { } + assign { } { } + assign $0\wr_pick_dly$1470$next[0:0]$2716 $1\wr_pick_dly$1470$next[0:0]$2717 + attribute \src "issuer_ls180.v:45829.5-45829.29" + switch \initial + attribute \src "issuer_ls180.v:45829.9-45829.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\wr_pick_dly$1470$next[0:0]$2717 1'0 + case + assign $1\wr_pick_dly$1470$next[0:0]$2717 \wr_pick$1467 + end + sync always + update \wr_pick_dly$1470$next $0\wr_pick_dly$1470$next[0:0]$2716 + end + attribute \src "issuer_ls180.v:45837.3-45865.6" + process $proc$issuer_ls180.v:45837$2718 + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_branch0__fn_unit[11:0] $1\fus_oper_i_alu_branch0__fn_unit[11:0] + attribute \src "issuer_ls180.v:45838.5-45838.29" + switch \initial + attribute \src "issuer_ls180.v:45838.9-45838.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" + switch \ivalid_i + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_alu_branch0__fn_unit[11:0] $2\fus_oper_i_alu_branch0__fn_unit[11:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" + switch \core_core_insn_type + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_branch0__fn_unit[11:0] 12'000000000000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_branch0__fn_unit[11:0] 12'000000000000 + attribute \src "issuer_ls180.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_alu_branch0__fn_unit[11:0] $3\fus_oper_i_alu_branch0__fn_unit[11:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" + switch \fu_enable [2] + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_alu_branch0__fn_unit[11:0] \dec_BRANCH_BRANCH_BRANCH__fn_unit + case + assign $3\fus_oper_i_alu_branch0__fn_unit[11:0] 12'000000000000 + end + end + case + assign $1\fus_oper_i_alu_branch0__fn_unit[11:0] 12'000000000000 + end + sync always + update \fus_oper_i_alu_branch0__fn_unit $0\fus_oper_i_alu_branch0__fn_unit[11:0] + end + attribute \src "issuer_ls180.v:45866.3-45874.6" + process $proc$issuer_ls180.v:45866$2719 + assign { } { } + assign { } { } + assign $0\wr_pick_dly$1486$next[0:0]$2720 $1\wr_pick_dly$1486$next[0:0]$2721 + attribute \src "issuer_ls180.v:45867.5-45867.29" + switch \initial + attribute \src "issuer_ls180.v:45867.9-45867.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\wr_pick_dly$1486$next[0:0]$2721 1'0 + case + assign $1\wr_pick_dly$1486$next[0:0]$2721 \wr_pick$1483 + end + sync always + update \wr_pick_dly$1486$next $0\wr_pick_dly$1486$next[0:0]$2720 + end + attribute \src "issuer_ls180.v:45875.3-45903.6" + process $proc$issuer_ls180.v:45875$2722 + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_branch0__insn[31:0] $1\fus_oper_i_alu_branch0__insn[31:0] + attribute \src "issuer_ls180.v:45876.5-45876.29" + switch \initial + attribute \src "issuer_ls180.v:45876.9-45876.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" + switch \ivalid_i + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_alu_branch0__insn[31:0] $2\fus_oper_i_alu_branch0__insn[31:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" + switch \core_core_insn_type + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_branch0__insn[31:0] 0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_branch0__insn[31:0] 0 + attribute \src "issuer_ls180.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_alu_branch0__insn[31:0] $3\fus_oper_i_alu_branch0__insn[31:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" + switch \fu_enable [2] + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_alu_branch0__insn[31:0] \dec_BRANCH_BRANCH_BRANCH__insn + case + assign $3\fus_oper_i_alu_branch0__insn[31:0] 0 + end + end + case + assign $1\fus_oper_i_alu_branch0__insn[31:0] 0 + end + sync always + update \fus_oper_i_alu_branch0__insn $0\fus_oper_i_alu_branch0__insn[31:0] + end + attribute \src "issuer_ls180.v:45904.3-45912.6" + process $proc$issuer_ls180.v:45904$2723 + assign { } { } + assign { } { } + assign $0\wr_pick_dly$1522$next[0:0]$2724 $1\wr_pick_dly$1522$next[0:0]$2725 + attribute \src "issuer_ls180.v:45905.5-45905.29" + switch \initial + attribute \src "issuer_ls180.v:45905.9-45905.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\wr_pick_dly$1522$next[0:0]$2725 1'0 + case + assign $1\wr_pick_dly$1522$next[0:0]$2725 \wr_pick$1519 + end + sync always + update \wr_pick_dly$1522$next $0\wr_pick_dly$1522$next[0:0]$2724 + end + attribute \src "issuer_ls180.v:45913.3-45921.6" + process $proc$issuer_ls180.v:45913$2726 + assign { } { } + assign { } { } + assign $0\wr_pick_dly$1538$next[0:0]$2727 $1\wr_pick_dly$1538$next[0:0]$2728 + attribute \src "issuer_ls180.v:45914.5-45914.29" + switch \initial + attribute \src "issuer_ls180.v:45914.9-45914.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\wr_pick_dly$1538$next[0:0]$2728 1'0 + case + assign $1\wr_pick_dly$1538$next[0:0]$2728 \wr_pick$1535 + end + sync always + update \wr_pick_dly$1538$next $0\wr_pick_dly$1538$next[0:0]$2727 + end + attribute \src "issuer_ls180.v:45922.3-45951.6" + process $proc$issuer_ls180.v:45922$2729 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_branch0__imm_data__data[63:0] $1\fus_oper_i_alu_branch0__imm_data__data[63:0] + assign $0\fus_oper_i_alu_branch0__imm_data__ok[0:0] $1\fus_oper_i_alu_branch0__imm_data__ok[0:0] + attribute \src "issuer_ls180.v:45923.5-45923.29" + switch \initial + attribute \src "issuer_ls180.v:45923.9-45923.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" + switch \ivalid_i + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign $1\fus_oper_i_alu_branch0__imm_data__data[63:0] $2\fus_oper_i_alu_branch0__imm_data__data[63:0] + assign $1\fus_oper_i_alu_branch0__imm_data__ok[0:0] $2\fus_oper_i_alu_branch0__imm_data__ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" + switch \core_core_insn_type + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_branch0__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\fus_oper_i_alu_branch0__imm_data__ok[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_branch0__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\fus_oper_i_alu_branch0__imm_data__ok[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case + assign { } { } + assign { } { } + assign $2\fus_oper_i_alu_branch0__imm_data__data[63:0] $3\fus_oper_i_alu_branch0__imm_data__data[63:0] + assign $2\fus_oper_i_alu_branch0__imm_data__ok[0:0] $3\fus_oper_i_alu_branch0__imm_data__ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" + switch \fu_enable [2] + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $3\fus_oper_i_alu_branch0__imm_data__ok[0:0] $3\fus_oper_i_alu_branch0__imm_data__data[63:0] } { \dec_BRANCH_BRANCH_BRANCH__imm_data__ok \dec_BRANCH_BRANCH_BRANCH__imm_data__data } + case + assign $3\fus_oper_i_alu_branch0__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $3\fus_oper_i_alu_branch0__imm_data__ok[0:0] 1'0 + end + end + case + assign $1\fus_oper_i_alu_branch0__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\fus_oper_i_alu_branch0__imm_data__ok[0:0] 1'0 + end + sync always + update \fus_oper_i_alu_branch0__imm_data__data $0\fus_oper_i_alu_branch0__imm_data__data[63:0] + update \fus_oper_i_alu_branch0__imm_data__ok $0\fus_oper_i_alu_branch0__imm_data__ok[0:0] + end + attribute \src "issuer_ls180.v:45952.3-45960.6" + process $proc$issuer_ls180.v:45952$2730 + assign { } { } + assign { } { } + assign $0\wr_pick_dly$1554$next[0:0]$2731 $1\wr_pick_dly$1554$next[0:0]$2732 + attribute \src "issuer_ls180.v:45953.5-45953.29" + switch \initial + attribute \src "issuer_ls180.v:45953.9-45953.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\wr_pick_dly$1554$next[0:0]$2732 1'0 + case + assign $1\wr_pick_dly$1554$next[0:0]$2732 \wr_pick$1551 + end + sync always + update \wr_pick_dly$1554$next $0\wr_pick_dly$1554$next[0:0]$2731 + end + attribute \src "issuer_ls180.v:45961.3-45969.6" + process $proc$issuer_ls180.v:45961$2733 + assign { } { } + assign { } { } + assign $0\wr_pick_dly$1570$next[0:0]$2734 $1\wr_pick_dly$1570$next[0:0]$2735 + attribute \src "issuer_ls180.v:45962.5-45962.29" + switch \initial + attribute \src "issuer_ls180.v:45962.9-45962.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\wr_pick_dly$1570$next[0:0]$2735 1'0 + case + assign $1\wr_pick_dly$1570$next[0:0]$2735 \wr_pick$1567 + end + sync always + update \wr_pick_dly$1570$next $0\wr_pick_dly$1570$next[0:0]$2734 + end + attribute \src "issuer_ls180.v:45970.3-45978.6" + process $proc$issuer_ls180.v:45970$2736 + assign { } { } + assign { } { } + assign $0\wr_pick_dly$1612$next[0:0]$2737 $1\wr_pick_dly$1612$next[0:0]$2738 + attribute \src "issuer_ls180.v:45971.5-45971.29" + switch \initial + attribute \src "issuer_ls180.v:45971.9-45971.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\wr_pick_dly$1612$next[0:0]$2738 1'0 + case + assign $1\wr_pick_dly$1612$next[0:0]$2738 \wr_pick$1609 + end + sync always + update \wr_pick_dly$1612$next $0\wr_pick_dly$1612$next[0:0]$2737 + end + attribute \src "issuer_ls180.v:45979.3-46007.6" + process $proc$issuer_ls180.v:45979$2739 + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_branch0__lk[0:0] $1\fus_oper_i_alu_branch0__lk[0:0] + attribute \src "issuer_ls180.v:45980.5-45980.29" + switch \initial + attribute \src "issuer_ls180.v:45980.9-45980.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" + switch \ivalid_i + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_alu_branch0__lk[0:0] $2\fus_oper_i_alu_branch0__lk[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" + switch \core_core_insn_type + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_branch0__lk[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_branch0__lk[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_alu_branch0__lk[0:0] $3\fus_oper_i_alu_branch0__lk[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" + switch \fu_enable [2] + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_alu_branch0__lk[0:0] \dec_BRANCH_BRANCH_BRANCH__lk + case + assign $3\fus_oper_i_alu_branch0__lk[0:0] 1'0 + end + end + case + assign $1\fus_oper_i_alu_branch0__lk[0:0] 1'0 + end + sync always + update \fus_oper_i_alu_branch0__lk $0\fus_oper_i_alu_branch0__lk[0:0] + end + attribute \src "issuer_ls180.v:46008.3-46016.6" + process $proc$issuer_ls180.v:46008$2740 + assign { } { } + assign { } { } + assign $0\wr_pick_dly$1631$next[0:0]$2741 $1\wr_pick_dly$1631$next[0:0]$2742 + attribute \src "issuer_ls180.v:46009.5-46009.29" + switch \initial + attribute \src "issuer_ls180.v:46009.9-46009.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\wr_pick_dly$1631$next[0:0]$2742 1'0 + case + assign $1\wr_pick_dly$1631$next[0:0]$2742 \wr_pick$1628 + end + sync always + update \wr_pick_dly$1631$next $0\wr_pick_dly$1631$next[0:0]$2741 + end + attribute \src "issuer_ls180.v:46017.3-46045.6" + process $proc$issuer_ls180.v:46017$2743 + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_branch0__is_32bit[0:0] $1\fus_oper_i_alu_branch0__is_32bit[0:0] + attribute \src "issuer_ls180.v:46018.5-46018.29" + switch \initial + attribute \src "issuer_ls180.v:46018.9-46018.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" + switch \ivalid_i + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_alu_branch0__is_32bit[0:0] $2\fus_oper_i_alu_branch0__is_32bit[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" + switch \core_core_insn_type + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_branch0__is_32bit[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_branch0__is_32bit[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_alu_branch0__is_32bit[0:0] $3\fus_oper_i_alu_branch0__is_32bit[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" + switch \fu_enable [2] + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_alu_branch0__is_32bit[0:0] \dec_BRANCH_BRANCH_BRANCH__is_32bit + case + assign $3\fus_oper_i_alu_branch0__is_32bit[0:0] 1'0 + end + end + case + assign $1\fus_oper_i_alu_branch0__is_32bit[0:0] 1'0 + end + sync always + update \fus_oper_i_alu_branch0__is_32bit $0\fus_oper_i_alu_branch0__is_32bit[0:0] + end + attribute \src "issuer_ls180.v:46046.3-46054.6" + process $proc$issuer_ls180.v:46046$2744 + assign { } { } + assign { } { } + assign $0\wr_pick_dly$1647$next[0:0]$2745 $1\wr_pick_dly$1647$next[0:0]$2746 + attribute \src "issuer_ls180.v:46047.5-46047.29" + switch \initial + attribute \src "issuer_ls180.v:46047.9-46047.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\wr_pick_dly$1647$next[0:0]$2746 1'0 + case + assign $1\wr_pick_dly$1647$next[0:0]$2746 \wr_pick$1644 + end + sync always + update \wr_pick_dly$1647$next $0\wr_pick_dly$1647$next[0:0]$2745 + end + attribute \src "issuer_ls180.v:46055.3-46063.6" + process $proc$issuer_ls180.v:46055$2747 + assign { } { } + assign { } { } + assign $0\wr_pick_dly$1663$next[0:0]$2748 $1\wr_pick_dly$1663$next[0:0]$2749 + attribute \src "issuer_ls180.v:46056.5-46056.29" + switch \initial + attribute \src "issuer_ls180.v:46056.9-46056.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\wr_pick_dly$1663$next[0:0]$2749 1'0 + case + assign $1\wr_pick_dly$1663$next[0:0]$2749 \wr_pick$1660 + end + sync always + update \wr_pick_dly$1663$next $0\wr_pick_dly$1663$next[0:0]$2748 + end + attribute \src "issuer_ls180.v:46064.3-46092.6" + process $proc$issuer_ls180.v:46064$2750 + assign { } { } + assign { } { } + assign $0\fus_cu_issue_i$7[0:0]$2751 $1\fus_cu_issue_i$7[0:0]$2752 + attribute \src "issuer_ls180.v:46065.5-46065.29" + switch \initial + attribute \src "issuer_ls180.v:46065.9-46065.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" + switch \ivalid_i + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_cu_issue_i$7[0:0]$2752 $2\fus_cu_issue_i$7[0:0]$2753 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" + switch \core_core_insn_type + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'0000101 + assign $2\fus_cu_issue_i$7[0:0]$2753 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'0000001 + assign $2\fus_cu_issue_i$7[0:0]$2753 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case + assign { } { } + assign $2\fus_cu_issue_i$7[0:0]$2753 $3\fus_cu_issue_i$7[0:0]$2754 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" + switch \fu_enable [2] + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_cu_issue_i$7[0:0]$2754 \issue_i + case + assign $3\fus_cu_issue_i$7[0:0]$2754 1'0 + end + end + case + assign $1\fus_cu_issue_i$7[0:0]$2752 1'0 + end + sync always + update \fus_cu_issue_i$7 $0\fus_cu_issue_i$7[0:0]$2751 + end + attribute \src "issuer_ls180.v:46093.3-46101.6" + process $proc$issuer_ls180.v:46093$2755 + assign { } { } + assign { } { } + assign $0\wr_pick_dly$1679$next[0:0]$2756 $1\wr_pick_dly$1679$next[0:0]$2757 + attribute \src "issuer_ls180.v:46094.5-46094.29" + switch \initial + attribute \src "issuer_ls180.v:46094.9-46094.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\wr_pick_dly$1679$next[0:0]$2757 1'0 + case + assign $1\wr_pick_dly$1679$next[0:0]$2757 \wr_pick$1676 + end + sync always + update \wr_pick_dly$1679$next $0\wr_pick_dly$1679$next[0:0]$2756 + end + attribute \src "issuer_ls180.v:46102.3-46130.6" + process $proc$issuer_ls180.v:46102$2758 + assign { } { } + assign { } { } + assign $0\fus_cu_rdmaskn_i$9[2:0]$2759 $1\fus_cu_rdmaskn_i$9[2:0]$2760 + attribute \src "issuer_ls180.v:46103.5-46103.29" + switch \initial + attribute \src "issuer_ls180.v:46103.9-46103.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" + switch \ivalid_i + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_cu_rdmaskn_i$9[2:0]$2760 $2\fus_cu_rdmaskn_i$9[2:0]$2761 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" + switch \core_core_insn_type + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'0000101 + assign $2\fus_cu_rdmaskn_i$9[2:0]$2761 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'0000001 + assign $2\fus_cu_rdmaskn_i$9[2:0]$2761 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case + assign { } { } + assign $2\fus_cu_rdmaskn_i$9[2:0]$2761 $3\fus_cu_rdmaskn_i$9[2:0]$2762 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" + switch \fu_enable [2] + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_cu_rdmaskn_i$9[2:0]$2762 \$231 + case + assign $3\fus_cu_rdmaskn_i$9[2:0]$2762 3'000 + end + end + case + assign $1\fus_cu_rdmaskn_i$9[2:0]$2760 3'000 + end + sync always + update \fus_cu_rdmaskn_i$9 $0\fus_cu_rdmaskn_i$9[2:0]$2759 + end + attribute \src "issuer_ls180.v:46131.3-46139.6" + process $proc$issuer_ls180.v:46131$2763 + assign { } { } + assign { } { } + assign $0\wr_pick_dly$1723$next[0:0]$2764 $1\wr_pick_dly$1723$next[0:0]$2765 + attribute \src "issuer_ls180.v:46132.5-46132.29" + switch \initial + attribute \src "issuer_ls180.v:46132.9-46132.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\wr_pick_dly$1723$next[0:0]$2765 1'0 + case + assign $1\wr_pick_dly$1723$next[0:0]$2765 \wr_pick$1720 + end + sync always + update \wr_pick_dly$1723$next $0\wr_pick_dly$1723$next[0:0]$2764 + end + attribute \src "issuer_ls180.v:46140.3-46148.6" + process $proc$issuer_ls180.v:46140$2766 + assign { } { } + assign { } { } + assign $0\wr_pick_dly$1739$next[0:0]$2767 $1\wr_pick_dly$1739$next[0:0]$2768 + attribute \src "issuer_ls180.v:46141.5-46141.29" + switch \initial + attribute \src "issuer_ls180.v:46141.9-46141.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\wr_pick_dly$1739$next[0:0]$2768 1'0 + case + assign $1\wr_pick_dly$1739$next[0:0]$2768 \wr_pick$1736 + end + sync always + update \wr_pick_dly$1739$next $0\wr_pick_dly$1739$next[0:0]$2767 + end + attribute \src "issuer_ls180.v:46149.3-46177.6" + process $proc$issuer_ls180.v:46149$2769 + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_trap0__insn_type[6:0] $1\fus_oper_i_alu_trap0__insn_type[6:0] + attribute \src "issuer_ls180.v:46150.5-46150.29" + switch \initial + attribute \src "issuer_ls180.v:46150.9-46150.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" + switch \ivalid_i + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_alu_trap0__insn_type[6:0] $2\fus_oper_i_alu_trap0__insn_type[6:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" + switch \core_core_insn_type + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_trap0__insn_type[6:0] 7'0000000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_trap0__insn_type[6:0] 7'0000000 + attribute \src "issuer_ls180.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_alu_trap0__insn_type[6:0] $3\fus_oper_i_alu_trap0__insn_type[6:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" + switch \fu_enable [3] + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_alu_trap0__insn_type[6:0] \core_core_insn_type + case + assign $3\fus_oper_i_alu_trap0__insn_type[6:0] 7'0000000 + end + end + case + assign $1\fus_oper_i_alu_trap0__insn_type[6:0] 7'0000000 + end + sync always + update \fus_oper_i_alu_trap0__insn_type $0\fus_oper_i_alu_trap0__insn_type[6:0] + end + attribute \src "issuer_ls180.v:46178.3-46186.6" + process $proc$issuer_ls180.v:46178$2770 + assign { } { } + assign { } { } + assign $0\wr_pick_dly$1763$next[0:0]$2771 $1\wr_pick_dly$1763$next[0:0]$2772 + attribute \src "issuer_ls180.v:46179.5-46179.29" + switch \initial + attribute \src "issuer_ls180.v:46179.9-46179.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\wr_pick_dly$1763$next[0:0]$2772 1'0 + case + assign $1\wr_pick_dly$1763$next[0:0]$2772 \wr_pick$1760 + end + sync always + update \wr_pick_dly$1763$next $0\wr_pick_dly$1763$next[0:0]$2771 + end + attribute \src "issuer_ls180.v:46187.3-46215.6" + process $proc$issuer_ls180.v:46187$2773 + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_trap0__fn_unit[11:0] $1\fus_oper_i_alu_trap0__fn_unit[11:0] + attribute \src "issuer_ls180.v:46188.5-46188.29" + switch \initial + attribute \src "issuer_ls180.v:46188.9-46188.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" + switch \ivalid_i + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_alu_trap0__fn_unit[11:0] $2\fus_oper_i_alu_trap0__fn_unit[11:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" + switch \core_core_insn_type + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_trap0__fn_unit[11:0] 12'000000000000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_trap0__fn_unit[11:0] 12'000000000000 + attribute \src "issuer_ls180.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_alu_trap0__fn_unit[11:0] $3\fus_oper_i_alu_trap0__fn_unit[11:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" + switch \fu_enable [3] + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_alu_trap0__fn_unit[11:0] \core_core_fn_unit + case + assign $3\fus_oper_i_alu_trap0__fn_unit[11:0] 12'000000000000 + end + end + case + assign $1\fus_oper_i_alu_trap0__fn_unit[11:0] 12'000000000000 + end + sync always + update \fus_oper_i_alu_trap0__fn_unit $0\fus_oper_i_alu_trap0__fn_unit[11:0] + end + attribute \src "issuer_ls180.v:46216.3-46224.6" + process $proc$issuer_ls180.v:46216$2774 + assign { } { } + assign { } { } + assign $0\wr_pick_dly$1783$next[0:0]$2775 $1\wr_pick_dly$1783$next[0:0]$2776 + attribute \src "issuer_ls180.v:46217.5-46217.29" + switch \initial + attribute \src "issuer_ls180.v:46217.9-46217.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\wr_pick_dly$1783$next[0:0]$2776 1'0 + case + assign $1\wr_pick_dly$1783$next[0:0]$2776 \wr_pick$1780 + end + sync always + update \wr_pick_dly$1783$next $0\wr_pick_dly$1783$next[0:0]$2775 + end + attribute \src "issuer_ls180.v:46225.3-46253.6" + process $proc$issuer_ls180.v:46225$2777 + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_trap0__insn[31:0] $1\fus_oper_i_alu_trap0__insn[31:0] + attribute \src "issuer_ls180.v:46226.5-46226.29" + switch \initial + attribute \src "issuer_ls180.v:46226.9-46226.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" + switch \ivalid_i + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_alu_trap0__insn[31:0] $2\fus_oper_i_alu_trap0__insn[31:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" + switch \core_core_insn_type + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_trap0__insn[31:0] 0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_trap0__insn[31:0] 0 + attribute \src "issuer_ls180.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_alu_trap0__insn[31:0] $3\fus_oper_i_alu_trap0__insn[31:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" + switch \fu_enable [3] + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_alu_trap0__insn[31:0] \core_core_insn + case + assign $3\fus_oper_i_alu_trap0__insn[31:0] 0 + end + end + case + assign $1\fus_oper_i_alu_trap0__insn[31:0] 0 + end + sync always + update \fus_oper_i_alu_trap0__insn $0\fus_oper_i_alu_trap0__insn[31:0] + end + attribute \src "issuer_ls180.v:46254.3-46282.6" + process $proc$issuer_ls180.v:46254$2778 + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_trap0__msr[63:0] $1\fus_oper_i_alu_trap0__msr[63:0] + attribute \src "issuer_ls180.v:46255.5-46255.29" + switch \initial + attribute \src "issuer_ls180.v:46255.9-46255.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" + switch \ivalid_i + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_alu_trap0__msr[63:0] $2\fus_oper_i_alu_trap0__msr[63:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" + switch \core_core_insn_type + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_trap0__msr[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_trap0__msr[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "issuer_ls180.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_alu_trap0__msr[63:0] $3\fus_oper_i_alu_trap0__msr[63:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" + switch \fu_enable [3] + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_alu_trap0__msr[63:0] \core_core_msr + case + assign $3\fus_oper_i_alu_trap0__msr[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + end + case + assign $1\fus_oper_i_alu_trap0__msr[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \fus_oper_i_alu_trap0__msr $0\fus_oper_i_alu_trap0__msr[63:0] + end + attribute \src "issuer_ls180.v:46283.3-46311.6" + process $proc$issuer_ls180.v:46283$2779 + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_trap0__cia[63:0] $1\fus_oper_i_alu_trap0__cia[63:0] + attribute \src "issuer_ls180.v:46284.5-46284.29" + switch \initial + attribute \src "issuer_ls180.v:46284.9-46284.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" + switch \ivalid_i + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_alu_trap0__cia[63:0] $2\fus_oper_i_alu_trap0__cia[63:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" + switch \core_core_insn_type + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_trap0__cia[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_trap0__cia[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "issuer_ls180.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_alu_trap0__cia[63:0] $3\fus_oper_i_alu_trap0__cia[63:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" + switch \fu_enable [3] + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_alu_trap0__cia[63:0] \core_core_cia + case + assign $3\fus_oper_i_alu_trap0__cia[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + end + case + assign $1\fus_oper_i_alu_trap0__cia[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \fus_oper_i_alu_trap0__cia $0\fus_oper_i_alu_trap0__cia[63:0] + end + attribute \src "issuer_ls180.v:46312.3-46340.6" + process $proc$issuer_ls180.v:46312$2780 + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_trap0__is_32bit[0:0] $1\fus_oper_i_alu_trap0__is_32bit[0:0] + attribute \src "issuer_ls180.v:46313.5-46313.29" + switch \initial + attribute \src "issuer_ls180.v:46313.9-46313.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" + switch \ivalid_i + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_alu_trap0__is_32bit[0:0] $2\fus_oper_i_alu_trap0__is_32bit[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" + switch \core_core_insn_type + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_trap0__is_32bit[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_trap0__is_32bit[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_alu_trap0__is_32bit[0:0] $3\fus_oper_i_alu_trap0__is_32bit[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" + switch \fu_enable [3] + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_alu_trap0__is_32bit[0:0] \core_core_is_32bit + case + assign $3\fus_oper_i_alu_trap0__is_32bit[0:0] 1'0 + end + end + case + assign $1\fus_oper_i_alu_trap0__is_32bit[0:0] 1'0 + end + sync always + update \fus_oper_i_alu_trap0__is_32bit $0\fus_oper_i_alu_trap0__is_32bit[0:0] + end + attribute \src "issuer_ls180.v:46341.3-46369.6" + process $proc$issuer_ls180.v:46341$2781 + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_trap0__traptype[6:0] $1\fus_oper_i_alu_trap0__traptype[6:0] + attribute \src "issuer_ls180.v:46342.5-46342.29" + switch \initial + attribute \src "issuer_ls180.v:46342.9-46342.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" + switch \ivalid_i + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_alu_trap0__traptype[6:0] $2\fus_oper_i_alu_trap0__traptype[6:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" + switch \core_core_insn_type + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_trap0__traptype[6:0] 7'0000000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_trap0__traptype[6:0] 7'0000000 + attribute \src "issuer_ls180.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_alu_trap0__traptype[6:0] $3\fus_oper_i_alu_trap0__traptype[6:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" + switch \fu_enable [3] + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_alu_trap0__traptype[6:0] \core_core_traptype + case + assign $3\fus_oper_i_alu_trap0__traptype[6:0] 7'0000000 + end + end + case + assign $1\fus_oper_i_alu_trap0__traptype[6:0] 7'0000000 + end + sync always + update \fus_oper_i_alu_trap0__traptype $0\fus_oper_i_alu_trap0__traptype[6:0] + end + attribute \src "issuer_ls180.v:46370.3-46398.6" + process $proc$issuer_ls180.v:46370$2782 + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_trap0__trapaddr[12:0] $1\fus_oper_i_alu_trap0__trapaddr[12:0] + attribute \src "issuer_ls180.v:46371.5-46371.29" + switch \initial + attribute \src "issuer_ls180.v:46371.9-46371.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" + switch \ivalid_i + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_alu_trap0__trapaddr[12:0] $2\fus_oper_i_alu_trap0__trapaddr[12:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" + switch \core_core_insn_type + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_trap0__trapaddr[12:0] 13'0000000000000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_trap0__trapaddr[12:0] 13'0000000000000 + attribute \src "issuer_ls180.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_alu_trap0__trapaddr[12:0] $3\fus_oper_i_alu_trap0__trapaddr[12:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" + switch \fu_enable [3] + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_alu_trap0__trapaddr[12:0] \core_core_trapaddr + case + assign $3\fus_oper_i_alu_trap0__trapaddr[12:0] 13'0000000000000 + end + end + case + assign $1\fus_oper_i_alu_trap0__trapaddr[12:0] 13'0000000000000 + end + sync always + update \fus_oper_i_alu_trap0__trapaddr $0\fus_oper_i_alu_trap0__trapaddr[12:0] + end + attribute \src "issuer_ls180.v:46399.3-46427.6" + process $proc$issuer_ls180.v:46399$2783 + assign { } { } + assign { } { } + assign $0\fus_cu_issue_i$10[0:0]$2784 $1\fus_cu_issue_i$10[0:0]$2785 + attribute \src "issuer_ls180.v:46400.5-46400.29" + switch \initial + attribute \src "issuer_ls180.v:46400.9-46400.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" + switch \ivalid_i + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_cu_issue_i$10[0:0]$2785 $2\fus_cu_issue_i$10[0:0]$2786 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" + switch \core_core_insn_type + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'0000101 + assign $2\fus_cu_issue_i$10[0:0]$2786 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'0000001 + assign $2\fus_cu_issue_i$10[0:0]$2786 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case + assign { } { } + assign $2\fus_cu_issue_i$10[0:0]$2786 $3\fus_cu_issue_i$10[0:0]$2787 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" + switch \fu_enable [3] + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_cu_issue_i$10[0:0]$2787 \issue_i + case + assign $3\fus_cu_issue_i$10[0:0]$2787 1'0 + end + end + case + assign $1\fus_cu_issue_i$10[0:0]$2785 1'0 + end + sync always + update \fus_cu_issue_i$10 $0\fus_cu_issue_i$10[0:0]$2784 + end + attribute \src "issuer_ls180.v:46428.3-46456.6" + process $proc$issuer_ls180.v:46428$2788 + assign { } { } + assign { } { } + assign $0\fus_cu_rdmaskn_i$12[3:0]$2789 $1\fus_cu_rdmaskn_i$12[3:0]$2790 + attribute \src "issuer_ls180.v:46429.5-46429.29" + switch \initial + attribute \src "issuer_ls180.v:46429.9-46429.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" + switch \ivalid_i + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_cu_rdmaskn_i$12[3:0]$2790 $2\fus_cu_rdmaskn_i$12[3:0]$2791 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" + switch \core_core_insn_type + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'0000101 + assign $2\fus_cu_rdmaskn_i$12[3:0]$2791 4'0000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'0000001 + assign $2\fus_cu_rdmaskn_i$12[3:0]$2791 4'0000 + attribute \src "issuer_ls180.v:0.0-0.0" + case + assign { } { } + assign $2\fus_cu_rdmaskn_i$12[3:0]$2791 $3\fus_cu_rdmaskn_i$12[3:0]$2792 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" + switch \fu_enable [3] + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_cu_rdmaskn_i$12[3:0]$2792 \$233 + case + assign $3\fus_cu_rdmaskn_i$12[3:0]$2792 4'0000 + end + end + case + assign $1\fus_cu_rdmaskn_i$12[3:0]$2790 4'0000 + end + sync always + update \fus_cu_rdmaskn_i$12 $0\fus_cu_rdmaskn_i$12[3:0]$2789 + end + attribute \src "issuer_ls180.v:46457.3-46485.6" + process $proc$issuer_ls180.v:46457$2793 + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_logical0__insn_type[6:0] $1\fus_oper_i_alu_logical0__insn_type[6:0] + attribute \src "issuer_ls180.v:46458.5-46458.29" + switch \initial + attribute \src "issuer_ls180.v:46458.9-46458.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" + switch \ivalid_i + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_alu_logical0__insn_type[6:0] $2\fus_oper_i_alu_logical0__insn_type[6:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" + switch \core_core_insn_type + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_logical0__insn_type[6:0] 7'0000000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_logical0__insn_type[6:0] 7'0000000 + attribute \src "issuer_ls180.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_alu_logical0__insn_type[6:0] $3\fus_oper_i_alu_logical0__insn_type[6:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" + switch \fu_enable [4] + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_alu_logical0__insn_type[6:0] \dec_LOGICAL_LOGICAL_LOGICAL__insn_type + case + assign $3\fus_oper_i_alu_logical0__insn_type[6:0] 7'0000000 + end + end + case + assign $1\fus_oper_i_alu_logical0__insn_type[6:0] 7'0000000 + end + sync always + update \fus_oper_i_alu_logical0__insn_type $0\fus_oper_i_alu_logical0__insn_type[6:0] + end + attribute \src "issuer_ls180.v:46486.3-46514.6" + process $proc$issuer_ls180.v:46486$2794 + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_logical0__fn_unit[11:0] $1\fus_oper_i_alu_logical0__fn_unit[11:0] + attribute \src "issuer_ls180.v:46487.5-46487.29" + switch \initial + attribute \src "issuer_ls180.v:46487.9-46487.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" + switch \ivalid_i + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_alu_logical0__fn_unit[11:0] $2\fus_oper_i_alu_logical0__fn_unit[11:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" + switch \core_core_insn_type + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_logical0__fn_unit[11:0] 12'000000000000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_logical0__fn_unit[11:0] 12'000000000000 + attribute \src "issuer_ls180.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_alu_logical0__fn_unit[11:0] $3\fus_oper_i_alu_logical0__fn_unit[11:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" + switch \fu_enable [4] + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_alu_logical0__fn_unit[11:0] \dec_LOGICAL_LOGICAL_LOGICAL__fn_unit + case + assign $3\fus_oper_i_alu_logical0__fn_unit[11:0] 12'000000000000 + end + end + case + assign $1\fus_oper_i_alu_logical0__fn_unit[11:0] 12'000000000000 + end + sync always + update \fus_oper_i_alu_logical0__fn_unit $0\fus_oper_i_alu_logical0__fn_unit[11:0] + end + attribute \src "issuer_ls180.v:46515.3-46544.6" + process $proc$issuer_ls180.v:46515$2795 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_logical0__imm_data__data[63:0] $1\fus_oper_i_alu_logical0__imm_data__data[63:0] + assign $0\fus_oper_i_alu_logical0__imm_data__ok[0:0] $1\fus_oper_i_alu_logical0__imm_data__ok[0:0] + attribute \src "issuer_ls180.v:46516.5-46516.29" + switch \initial + attribute \src "issuer_ls180.v:46516.9-46516.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" + switch \ivalid_i + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign $1\fus_oper_i_alu_logical0__imm_data__data[63:0] $2\fus_oper_i_alu_logical0__imm_data__data[63:0] + assign $1\fus_oper_i_alu_logical0__imm_data__ok[0:0] $2\fus_oper_i_alu_logical0__imm_data__ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" + switch \core_core_insn_type + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_logical0__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\fus_oper_i_alu_logical0__imm_data__ok[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_logical0__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\fus_oper_i_alu_logical0__imm_data__ok[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case + assign { } { } + assign { } { } + assign $2\fus_oper_i_alu_logical0__imm_data__data[63:0] $3\fus_oper_i_alu_logical0__imm_data__data[63:0] + assign $2\fus_oper_i_alu_logical0__imm_data__ok[0:0] $3\fus_oper_i_alu_logical0__imm_data__ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" + switch \fu_enable [4] + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $3\fus_oper_i_alu_logical0__imm_data__ok[0:0] $3\fus_oper_i_alu_logical0__imm_data__data[63:0] } { \dec_LOGICAL_LOGICAL_LOGICAL__imm_data__ok \dec_LOGICAL_LOGICAL_LOGICAL__imm_data__data } + case + assign $3\fus_oper_i_alu_logical0__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $3\fus_oper_i_alu_logical0__imm_data__ok[0:0] 1'0 + end + end + case + assign $1\fus_oper_i_alu_logical0__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\fus_oper_i_alu_logical0__imm_data__ok[0:0] 1'0 + end + sync always + update \fus_oper_i_alu_logical0__imm_data__data $0\fus_oper_i_alu_logical0__imm_data__data[63:0] + update \fus_oper_i_alu_logical0__imm_data__ok $0\fus_oper_i_alu_logical0__imm_data__ok[0:0] + end + attribute \src "issuer_ls180.v:46545.3-46574.6" + process $proc$issuer_ls180.v:46545$2796 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_logical0__rc__ok[0:0] $1\fus_oper_i_alu_logical0__rc__ok[0:0] + assign $0\fus_oper_i_alu_logical0__rc__rc[0:0] $1\fus_oper_i_alu_logical0__rc__rc[0:0] + attribute \src "issuer_ls180.v:46546.5-46546.29" + switch \initial + attribute \src "issuer_ls180.v:46546.9-46546.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" + switch \ivalid_i + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign $1\fus_oper_i_alu_logical0__rc__ok[0:0] $2\fus_oper_i_alu_logical0__rc__ok[0:0] + assign $1\fus_oper_i_alu_logical0__rc__rc[0:0] $2\fus_oper_i_alu_logical0__rc__rc[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" + switch \core_core_insn_type + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_logical0__rc__ok[0:0] 1'0 + assign $2\fus_oper_i_alu_logical0__rc__rc[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_logical0__rc__ok[0:0] 1'0 + assign $2\fus_oper_i_alu_logical0__rc__rc[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case + assign { } { } + assign { } { } + assign $2\fus_oper_i_alu_logical0__rc__ok[0:0] $3\fus_oper_i_alu_logical0__rc__ok[0:0] + assign $2\fus_oper_i_alu_logical0__rc__rc[0:0] $3\fus_oper_i_alu_logical0__rc__rc[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" + switch \fu_enable [4] + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $3\fus_oper_i_alu_logical0__rc__ok[0:0] $3\fus_oper_i_alu_logical0__rc__rc[0:0] } { \dec_LOGICAL_LOGICAL_LOGICAL__rc__ok \dec_LOGICAL_LOGICAL_LOGICAL__rc__rc } + case + assign $3\fus_oper_i_alu_logical0__rc__ok[0:0] 1'0 + assign $3\fus_oper_i_alu_logical0__rc__rc[0:0] 1'0 + end + end + case + assign $1\fus_oper_i_alu_logical0__rc__ok[0:0] 1'0 + assign $1\fus_oper_i_alu_logical0__rc__rc[0:0] 1'0 + end + sync always + update \fus_oper_i_alu_logical0__rc__ok $0\fus_oper_i_alu_logical0__rc__ok[0:0] + update \fus_oper_i_alu_logical0__rc__rc $0\fus_oper_i_alu_logical0__rc__rc[0:0] + end + attribute \src "issuer_ls180.v:46575.3-46604.6" + process $proc$issuer_ls180.v:46575$2797 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_logical0__oe__oe[0:0] $1\fus_oper_i_alu_logical0__oe__oe[0:0] + assign $0\fus_oper_i_alu_logical0__oe__ok[0:0] $1\fus_oper_i_alu_logical0__oe__ok[0:0] + attribute \src "issuer_ls180.v:46576.5-46576.29" + switch \initial + attribute \src "issuer_ls180.v:46576.9-46576.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" + switch \ivalid_i + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign $1\fus_oper_i_alu_logical0__oe__oe[0:0] $2\fus_oper_i_alu_logical0__oe__oe[0:0] + assign $1\fus_oper_i_alu_logical0__oe__ok[0:0] $2\fus_oper_i_alu_logical0__oe__ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" + switch \core_core_insn_type + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_logical0__oe__oe[0:0] 1'0 + assign $2\fus_oper_i_alu_logical0__oe__ok[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_logical0__oe__oe[0:0] 1'0 + assign $2\fus_oper_i_alu_logical0__oe__ok[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case + assign { } { } + assign { } { } + assign $2\fus_oper_i_alu_logical0__oe__oe[0:0] $3\fus_oper_i_alu_logical0__oe__oe[0:0] + assign $2\fus_oper_i_alu_logical0__oe__ok[0:0] $3\fus_oper_i_alu_logical0__oe__ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" + switch \fu_enable [4] + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $3\fus_oper_i_alu_logical0__oe__ok[0:0] $3\fus_oper_i_alu_logical0__oe__oe[0:0] } { \dec_LOGICAL_LOGICAL_LOGICAL__oe__ok \dec_LOGICAL_LOGICAL_LOGICAL__oe__oe } + case + assign $3\fus_oper_i_alu_logical0__oe__oe[0:0] 1'0 + assign $3\fus_oper_i_alu_logical0__oe__ok[0:0] 1'0 + end + end + case + assign $1\fus_oper_i_alu_logical0__oe__oe[0:0] 1'0 + assign $1\fus_oper_i_alu_logical0__oe__ok[0:0] 1'0 + end + sync always + update \fus_oper_i_alu_logical0__oe__oe $0\fus_oper_i_alu_logical0__oe__oe[0:0] + update \fus_oper_i_alu_logical0__oe__ok $0\fus_oper_i_alu_logical0__oe__ok[0:0] + end + attribute \src "issuer_ls180.v:46605.3-46633.6" + process $proc$issuer_ls180.v:46605$2798 + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_logical0__invert_in[0:0] $1\fus_oper_i_alu_logical0__invert_in[0:0] + attribute \src "issuer_ls180.v:46606.5-46606.29" + switch \initial + attribute \src "issuer_ls180.v:46606.9-46606.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" + switch \ivalid_i + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_alu_logical0__invert_in[0:0] $2\fus_oper_i_alu_logical0__invert_in[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" + switch \core_core_insn_type + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_logical0__invert_in[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_logical0__invert_in[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_alu_logical0__invert_in[0:0] $3\fus_oper_i_alu_logical0__invert_in[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" + switch \fu_enable [4] + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_alu_logical0__invert_in[0:0] \dec_LOGICAL_LOGICAL_LOGICAL__invert_in + case + assign $3\fus_oper_i_alu_logical0__invert_in[0:0] 1'0 + end + end + case + assign $1\fus_oper_i_alu_logical0__invert_in[0:0] 1'0 + end + sync always + update \fus_oper_i_alu_logical0__invert_in $0\fus_oper_i_alu_logical0__invert_in[0:0] + end + attribute \src "issuer_ls180.v:46634.3-46662.6" + process $proc$issuer_ls180.v:46634$2799 + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_logical0__zero_a[0:0] $1\fus_oper_i_alu_logical0__zero_a[0:0] + attribute \src "issuer_ls180.v:46635.5-46635.29" + switch \initial + attribute \src "issuer_ls180.v:46635.9-46635.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" + switch \ivalid_i + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_alu_logical0__zero_a[0:0] $2\fus_oper_i_alu_logical0__zero_a[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" + switch \core_core_insn_type + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_logical0__zero_a[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_logical0__zero_a[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_alu_logical0__zero_a[0:0] $3\fus_oper_i_alu_logical0__zero_a[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" + switch \fu_enable [4] + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_alu_logical0__zero_a[0:0] \dec_LOGICAL_LOGICAL_LOGICAL__zero_a + case + assign $3\fus_oper_i_alu_logical0__zero_a[0:0] 1'0 + end + end + case + assign $1\fus_oper_i_alu_logical0__zero_a[0:0] 1'0 + end + sync always + update \fus_oper_i_alu_logical0__zero_a $0\fus_oper_i_alu_logical0__zero_a[0:0] + end + attribute \src "issuer_ls180.v:46663.3-46691.6" + process $proc$issuer_ls180.v:46663$2800 + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_logical0__input_carry[1:0] $1\fus_oper_i_alu_logical0__input_carry[1:0] + attribute \src "issuer_ls180.v:46664.5-46664.29" + switch \initial + attribute \src "issuer_ls180.v:46664.9-46664.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" + switch \ivalid_i + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_alu_logical0__input_carry[1:0] $2\fus_oper_i_alu_logical0__input_carry[1:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" + switch \core_core_insn_type + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_logical0__input_carry[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_logical0__input_carry[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_alu_logical0__input_carry[1:0] $3\fus_oper_i_alu_logical0__input_carry[1:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" + switch \fu_enable [4] + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_alu_logical0__input_carry[1:0] \dec_LOGICAL_LOGICAL_LOGICAL__input_carry + case + assign $3\fus_oper_i_alu_logical0__input_carry[1:0] 2'00 + end + end + case + assign $1\fus_oper_i_alu_logical0__input_carry[1:0] 2'00 + end + sync always + update \fus_oper_i_alu_logical0__input_carry $0\fus_oper_i_alu_logical0__input_carry[1:0] + end + attribute \src "issuer_ls180.v:46692.3-46720.6" + process $proc$issuer_ls180.v:46692$2801 + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_logical0__invert_out[0:0] $1\fus_oper_i_alu_logical0__invert_out[0:0] + attribute \src "issuer_ls180.v:46693.5-46693.29" + switch \initial + attribute \src "issuer_ls180.v:46693.9-46693.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" + switch \ivalid_i + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_alu_logical0__invert_out[0:0] $2\fus_oper_i_alu_logical0__invert_out[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" + switch \core_core_insn_type + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_logical0__invert_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_logical0__invert_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_alu_logical0__invert_out[0:0] $3\fus_oper_i_alu_logical0__invert_out[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" + switch \fu_enable [4] + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_alu_logical0__invert_out[0:0] \dec_LOGICAL_LOGICAL_LOGICAL__invert_out + case + assign $3\fus_oper_i_alu_logical0__invert_out[0:0] 1'0 + end + end + case + assign $1\fus_oper_i_alu_logical0__invert_out[0:0] 1'0 + end + sync always + update \fus_oper_i_alu_logical0__invert_out $0\fus_oper_i_alu_logical0__invert_out[0:0] + end + attribute \src "issuer_ls180.v:46721.3-46749.6" + process $proc$issuer_ls180.v:46721$2802 + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_logical0__write_cr0[0:0] $1\fus_oper_i_alu_logical0__write_cr0[0:0] + attribute \src "issuer_ls180.v:46722.5-46722.29" + switch \initial + attribute \src "issuer_ls180.v:46722.9-46722.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" + switch \ivalid_i + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_alu_logical0__write_cr0[0:0] $2\fus_oper_i_alu_logical0__write_cr0[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" + switch \core_core_insn_type + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_logical0__write_cr0[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_logical0__write_cr0[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_alu_logical0__write_cr0[0:0] $3\fus_oper_i_alu_logical0__write_cr0[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" + switch \fu_enable [4] + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_alu_logical0__write_cr0[0:0] \dec_LOGICAL_LOGICAL_LOGICAL__write_cr0 + case + assign $3\fus_oper_i_alu_logical0__write_cr0[0:0] 1'0 + end + end + case + assign $1\fus_oper_i_alu_logical0__write_cr0[0:0] 1'0 + end + sync always + update \fus_oper_i_alu_logical0__write_cr0 $0\fus_oper_i_alu_logical0__write_cr0[0:0] + end + attribute \src "issuer_ls180.v:46750.3-46778.6" + process $proc$issuer_ls180.v:46750$2803 + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_logical0__output_carry[0:0] $1\fus_oper_i_alu_logical0__output_carry[0:0] + attribute \src "issuer_ls180.v:46751.5-46751.29" + switch \initial + attribute \src "issuer_ls180.v:46751.9-46751.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" + switch \ivalid_i + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_alu_logical0__output_carry[0:0] $2\fus_oper_i_alu_logical0__output_carry[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" + switch \core_core_insn_type + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_logical0__output_carry[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_logical0__output_carry[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_alu_logical0__output_carry[0:0] $3\fus_oper_i_alu_logical0__output_carry[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" + switch \fu_enable [4] + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_alu_logical0__output_carry[0:0] \dec_LOGICAL_LOGICAL_LOGICAL__output_carry + case + assign $3\fus_oper_i_alu_logical0__output_carry[0:0] 1'0 + end + end + case + assign $1\fus_oper_i_alu_logical0__output_carry[0:0] 1'0 + end + sync always + update \fus_oper_i_alu_logical0__output_carry $0\fus_oper_i_alu_logical0__output_carry[0:0] + end + attribute \src "issuer_ls180.v:46779.3-46807.6" + process $proc$issuer_ls180.v:46779$2804 + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_logical0__is_32bit[0:0] $1\fus_oper_i_alu_logical0__is_32bit[0:0] + attribute \src "issuer_ls180.v:46780.5-46780.29" + switch \initial + attribute \src "issuer_ls180.v:46780.9-46780.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" + switch \ivalid_i + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_alu_logical0__is_32bit[0:0] $2\fus_oper_i_alu_logical0__is_32bit[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" + switch \core_core_insn_type + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_logical0__is_32bit[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_logical0__is_32bit[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_alu_logical0__is_32bit[0:0] $3\fus_oper_i_alu_logical0__is_32bit[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" + switch \fu_enable [4] + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_alu_logical0__is_32bit[0:0] \dec_LOGICAL_LOGICAL_LOGICAL__is_32bit + case + assign $3\fus_oper_i_alu_logical0__is_32bit[0:0] 1'0 + end + end + case + assign $1\fus_oper_i_alu_logical0__is_32bit[0:0] 1'0 + end + sync always + update \fus_oper_i_alu_logical0__is_32bit $0\fus_oper_i_alu_logical0__is_32bit[0:0] + end + attribute \src "issuer_ls180.v:46808.3-46836.6" + process $proc$issuer_ls180.v:46808$2805 + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_logical0__is_signed[0:0] $1\fus_oper_i_alu_logical0__is_signed[0:0] + attribute \src "issuer_ls180.v:46809.5-46809.29" + switch \initial + attribute \src "issuer_ls180.v:46809.9-46809.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" + switch \ivalid_i + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_alu_logical0__is_signed[0:0] $2\fus_oper_i_alu_logical0__is_signed[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" + switch \core_core_insn_type + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_logical0__is_signed[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_logical0__is_signed[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_alu_logical0__is_signed[0:0] $3\fus_oper_i_alu_logical0__is_signed[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" + switch \fu_enable [4] + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_alu_logical0__is_signed[0:0] \dec_LOGICAL_LOGICAL_LOGICAL__is_signed + case + assign $3\fus_oper_i_alu_logical0__is_signed[0:0] 1'0 + end + end + case + assign $1\fus_oper_i_alu_logical0__is_signed[0:0] 1'0 + end + sync always + update \fus_oper_i_alu_logical0__is_signed $0\fus_oper_i_alu_logical0__is_signed[0:0] + end + attribute \src "issuer_ls180.v:46837.3-46865.6" + process $proc$issuer_ls180.v:46837$2806 + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_logical0__data_len[3:0] $1\fus_oper_i_alu_logical0__data_len[3:0] + attribute \src "issuer_ls180.v:46838.5-46838.29" + switch \initial + attribute \src "issuer_ls180.v:46838.9-46838.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" + switch \ivalid_i + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_alu_logical0__data_len[3:0] $2\fus_oper_i_alu_logical0__data_len[3:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" + switch \core_core_insn_type + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_logical0__data_len[3:0] 4'0000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_logical0__data_len[3:0] 4'0000 + attribute \src "issuer_ls180.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_alu_logical0__data_len[3:0] $3\fus_oper_i_alu_logical0__data_len[3:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" + switch \fu_enable [4] + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_alu_logical0__data_len[3:0] \dec_LOGICAL_LOGICAL_LOGICAL__data_len + case + assign $3\fus_oper_i_alu_logical0__data_len[3:0] 4'0000 + end + end + case + assign $1\fus_oper_i_alu_logical0__data_len[3:0] 4'0000 + end + sync always + update \fus_oper_i_alu_logical0__data_len $0\fus_oper_i_alu_logical0__data_len[3:0] + end + attribute \src "issuer_ls180.v:46866.3-46894.6" + process $proc$issuer_ls180.v:46866$2807 + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_logical0__insn[31:0] $1\fus_oper_i_alu_logical0__insn[31:0] + attribute \src "issuer_ls180.v:46867.5-46867.29" + switch \initial + attribute \src "issuer_ls180.v:46867.9-46867.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" + switch \ivalid_i + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_alu_logical0__insn[31:0] $2\fus_oper_i_alu_logical0__insn[31:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" + switch \core_core_insn_type + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_logical0__insn[31:0] 0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_logical0__insn[31:0] 0 + attribute \src "issuer_ls180.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_alu_logical0__insn[31:0] $3\fus_oper_i_alu_logical0__insn[31:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" + switch \fu_enable [4] + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_alu_logical0__insn[31:0] \dec_LOGICAL_LOGICAL_LOGICAL__insn + case + assign $3\fus_oper_i_alu_logical0__insn[31:0] 0 + end + end + case + assign $1\fus_oper_i_alu_logical0__insn[31:0] 0 + end + sync always + update \fus_oper_i_alu_logical0__insn $0\fus_oper_i_alu_logical0__insn[31:0] + end + attribute \src "issuer_ls180.v:46895.3-46923.6" + process $proc$issuer_ls180.v:46895$2808 + assign { } { } + assign { } { } + assign $0\fus_cu_issue_i$13[0:0]$2809 $1\fus_cu_issue_i$13[0:0]$2810 + attribute \src "issuer_ls180.v:46896.5-46896.29" + switch \initial + attribute \src "issuer_ls180.v:46896.9-46896.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" + switch \ivalid_i + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_cu_issue_i$13[0:0]$2810 $2\fus_cu_issue_i$13[0:0]$2811 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" + switch \core_core_insn_type + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'0000101 + assign $2\fus_cu_issue_i$13[0:0]$2811 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'0000001 + assign $2\fus_cu_issue_i$13[0:0]$2811 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case + assign { } { } + assign $2\fus_cu_issue_i$13[0:0]$2811 $3\fus_cu_issue_i$13[0:0]$2812 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" + switch \fu_enable [4] + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_cu_issue_i$13[0:0]$2812 \issue_i + case + assign $3\fus_cu_issue_i$13[0:0]$2812 1'0 + end + end + case + assign $1\fus_cu_issue_i$13[0:0]$2810 1'0 + end + sync always + update \fus_cu_issue_i$13 $0\fus_cu_issue_i$13[0:0]$2809 + end + attribute \src "issuer_ls180.v:46924.3-46952.6" + process $proc$issuer_ls180.v:46924$2813 + assign { } { } + assign { } { } + assign $0\fus_cu_rdmaskn_i$15[2:0]$2814 $1\fus_cu_rdmaskn_i$15[2:0]$2815 + attribute \src "issuer_ls180.v:46925.5-46925.29" + switch \initial + attribute \src "issuer_ls180.v:46925.9-46925.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" + switch \ivalid_i + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_cu_rdmaskn_i$15[2:0]$2815 $2\fus_cu_rdmaskn_i$15[2:0]$2816 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" + switch \core_core_insn_type + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'0000101 + assign $2\fus_cu_rdmaskn_i$15[2:0]$2816 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'0000001 + assign $2\fus_cu_rdmaskn_i$15[2:0]$2816 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case + assign { } { } + assign $2\fus_cu_rdmaskn_i$15[2:0]$2816 $3\fus_cu_rdmaskn_i$15[2:0]$2817 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" + switch \fu_enable [4] + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_cu_rdmaskn_i$15[2:0]$2817 \$235 + case + assign $3\fus_cu_rdmaskn_i$15[2:0]$2817 3'000 + end + end + case + assign $1\fus_cu_rdmaskn_i$15[2:0]$2815 3'000 + end + sync always + update \fus_cu_rdmaskn_i$15 $0\fus_cu_rdmaskn_i$15[2:0]$2814 + end + attribute \src "issuer_ls180.v:46953.3-46981.6" + process $proc$issuer_ls180.v:46953$2818 + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_spr0__insn_type[6:0] $1\fus_oper_i_alu_spr0__insn_type[6:0] + attribute \src "issuer_ls180.v:46954.5-46954.29" + switch \initial + attribute \src "issuer_ls180.v:46954.9-46954.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" + switch \ivalid_i + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_alu_spr0__insn_type[6:0] $2\fus_oper_i_alu_spr0__insn_type[6:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" + switch \core_core_insn_type + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_spr0__insn_type[6:0] 7'0000000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_spr0__insn_type[6:0] 7'0000000 + attribute \src "issuer_ls180.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_alu_spr0__insn_type[6:0] $3\fus_oper_i_alu_spr0__insn_type[6:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" + switch \fu_enable [5] + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_alu_spr0__insn_type[6:0] \dec_SPR_SPR_SPR__insn_type + case + assign $3\fus_oper_i_alu_spr0__insn_type[6:0] 7'0000000 + end + end + case + assign $1\fus_oper_i_alu_spr0__insn_type[6:0] 7'0000000 + end + sync always + update \fus_oper_i_alu_spr0__insn_type $0\fus_oper_i_alu_spr0__insn_type[6:0] + end + attribute \src "issuer_ls180.v:46982.3-47010.6" + process $proc$issuer_ls180.v:46982$2819 + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_spr0__fn_unit[11:0] $1\fus_oper_i_alu_spr0__fn_unit[11:0] + attribute \src "issuer_ls180.v:46983.5-46983.29" + switch \initial + attribute \src "issuer_ls180.v:46983.9-46983.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" + switch \ivalid_i + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_alu_spr0__fn_unit[11:0] $2\fus_oper_i_alu_spr0__fn_unit[11:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" + switch \core_core_insn_type + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_spr0__fn_unit[11:0] 12'000000000000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_spr0__fn_unit[11:0] 12'000000000000 + attribute \src "issuer_ls180.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_alu_spr0__fn_unit[11:0] $3\fus_oper_i_alu_spr0__fn_unit[11:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" + switch \fu_enable [5] + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_alu_spr0__fn_unit[11:0] \dec_SPR_SPR_SPR__fn_unit + case + assign $3\fus_oper_i_alu_spr0__fn_unit[11:0] 12'000000000000 + end + end + case + assign $1\fus_oper_i_alu_spr0__fn_unit[11:0] 12'000000000000 + end + sync always + update \fus_oper_i_alu_spr0__fn_unit $0\fus_oper_i_alu_spr0__fn_unit[11:0] + end + attribute \src "issuer_ls180.v:47011.3-47039.6" + process $proc$issuer_ls180.v:47011$2820 + assign { } { } + assign { } { } + assign $0\fus_oper_i_alu_spr0__insn[31:0] $1\fus_oper_i_alu_spr0__insn[31:0] + attribute \src "issuer_ls180.v:47012.5-47012.29" + switch \initial + attribute \src "issuer_ls180.v:47012.9-47012.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" + switch \ivalid_i + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fus_oper_i_alu_spr0__insn[31:0] $2\fus_oper_i_alu_spr0__insn[31:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" + switch \core_core_insn_type + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'0000101 + assign $2\fus_oper_i_alu_spr0__insn[31:0] 0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'0000001 + assign $2\fus_oper_i_alu_spr0__insn[31:0] 0 + attribute \src "issuer_ls180.v:0.0-0.0" + case + assign { } { } + assign $2\fus_oper_i_alu_spr0__insn[31:0] $3\fus_oper_i_alu_spr0__insn[31:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" + switch \fu_enable [5] + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fus_oper_i_alu_spr0__insn[31:0] \dec_SPR_SPR_SPR__insn + case + assign $3\fus_oper_i_alu_spr0__insn[31:0] 0 + end + end + case + assign $1\fus_oper_i_alu_spr0__insn[31:0] 0 + end + sync always + update \fus_oper_i_alu_spr0__insn $0\fus_oper_i_alu_spr0__insn[31:0] + end + connect \$1000 $ternary$issuer_ls180.v:40657$1429_Y + connect \$1002 $and$issuer_ls180.v:40658$1430_Y + connect \$1005 $and$issuer_ls180.v:40659$1431_Y + connect \$1009 $not$issuer_ls180.v:40660$1432_Y + connect \$1011 $and$issuer_ls180.v:40661$1433_Y + connect \$1015 $and$issuer_ls180.v:40662$1434_Y + connect \$1018 $ternary$issuer_ls180.v:40663$1435_Y + connect \$1020 $and$issuer_ls180.v:40664$1436_Y + connect \$1023 $and$issuer_ls180.v:40665$1437_Y + connect \$1027 $not$issuer_ls180.v:40666$1438_Y + connect \$1029 $and$issuer_ls180.v:40667$1439_Y + connect \$1037 $and$issuer_ls180.v:40668$1440_Y + connect \$1040 $ternary$issuer_ls180.v:40669$1441_Y + connect \$1042 $and$issuer_ls180.v:40670$1442_Y + connect \$1045 $and$issuer_ls180.v:40671$1443_Y + connect \$1049 $not$issuer_ls180.v:40672$1444_Y + connect \$1051 $and$issuer_ls180.v:40673$1445_Y + connect \$1057 $and$issuer_ls180.v:40674$1446_Y + connect \$1060 $ternary$issuer_ls180.v:40675$1447_Y + connect \$1062 $and$issuer_ls180.v:40676$1448_Y + connect \$1065 $and$issuer_ls180.v:40677$1449_Y + connect \$1069 $not$issuer_ls180.v:40678$1450_Y + connect \$1071 $and$issuer_ls180.v:40679$1451_Y + connect \$1077 $and$issuer_ls180.v:40680$1452_Y + connect \$1080 $ternary$issuer_ls180.v:40681$1453_Y + connect \$1082 $and$issuer_ls180.v:40682$1454_Y + connect \$1085 $and$issuer_ls180.v:40683$1455_Y + connect \$1089 $not$issuer_ls180.v:40684$1456_Y + connect \$1091 $and$issuer_ls180.v:40685$1457_Y + connect \$1096 $and$issuer_ls180.v:40686$1458_Y + connect \$1099 $ternary$issuer_ls180.v:40687$1459_Y + connect \$1101 $and$issuer_ls180.v:40688$1460_Y + connect \$1104 $and$issuer_ls180.v:40689$1461_Y + connect \$1108 $not$issuer_ls180.v:40690$1462_Y + connect \$1110 $and$issuer_ls180.v:40691$1463_Y + connect \$1114 $and$issuer_ls180.v:40692$1464_Y + connect \$1117 $ternary$issuer_ls180.v:40693$1465_Y + connect \$1119 $and$issuer_ls180.v:40694$1466_Y + connect \$1122 $and$issuer_ls180.v:40695$1467_Y + connect \$1125 $not$issuer_ls180.v:40696$1468_Y + connect \$1127 $and$issuer_ls180.v:40697$1469_Y + connect \$1130 $and$issuer_ls180.v:40698$1470_Y + connect \$1133 $ternary$issuer_ls180.v:40699$1471_Y + connect \$1136 $or$issuer_ls180.v:40700$1472_Y + connect \$1138 $or$issuer_ls180.v:40701$1473_Y + connect \$1140 $or$issuer_ls180.v:40702$1474_Y + connect \$1142 $or$issuer_ls180.v:40703$1475_Y + connect \$1144 $or$issuer_ls180.v:40704$1476_Y + connect \$1146 $or$issuer_ls180.v:40705$1477_Y + connect \$1148 $or$issuer_ls180.v:40706$1478_Y + connect \$1150 $or$issuer_ls180.v:40707$1479_Y + connect \$1152 $or$issuer_ls180.v:40708$1480_Y + connect \$1154 $or$issuer_ls180.v:40709$1481_Y + connect \$1156 $or$issuer_ls180.v:40710$1482_Y + connect \$1158 $or$issuer_ls180.v:40711$1483_Y + connect \$1160 $or$issuer_ls180.v:40712$1484_Y + connect \$1162 $or$issuer_ls180.v:40713$1485_Y + connect \$1164 $or$issuer_ls180.v:40714$1486_Y + connect \$1166 $or$issuer_ls180.v:40715$1487_Y + connect \$1168 $or$issuer_ls180.v:40716$1488_Y + connect \$1170 $or$issuer_ls180.v:40717$1489_Y + connect \$1172 $or$issuer_ls180.v:40718$1490_Y + connect \$1174 $or$issuer_ls180.v:40719$1491_Y + connect \$1176 $or$issuer_ls180.v:40720$1492_Y + connect \$1178 $or$issuer_ls180.v:40721$1493_Y + connect \$1180 $or$issuer_ls180.v:40722$1494_Y + connect \$1182 $or$issuer_ls180.v:40723$1495_Y + connect \$1184 $or$issuer_ls180.v:40724$1496_Y + connect \$1186 $or$issuer_ls180.v:40725$1497_Y + connect \$1188 $or$issuer_ls180.v:40726$1498_Y + connect \$1190 $and$issuer_ls180.v:40727$1499_Y + connect \$1192 $and$issuer_ls180.v:40728$1500_Y + connect \$1195 $and$issuer_ls180.v:40729$1501_Y + connect \$1198 $not$issuer_ls180.v:40730$1502_Y + connect \$1200 $and$issuer_ls180.v:40731$1503_Y + connect \$1203 $and$issuer_ls180.v:40732$1504_Y + connect \$1206 $ternary$issuer_ls180.v:40733$1505_Y + connect \$1208 $and$issuer_ls180.v:40734$1506_Y + connect \$1210 $and$issuer_ls180.v:40735$1507_Y + connect \$1212 $and$issuer_ls180.v:40736$1508_Y + connect \$1214 $and$issuer_ls180.v:40737$1509_Y + connect \$1216 $and$issuer_ls180.v:40738$1510_Y + connect \$1218 $and$issuer_ls180.v:40739$1511_Y + connect \$1220 $and$issuer_ls180.v:40740$1512_Y + connect \$1223 $and$issuer_ls180.v:40741$1513_Y + connect \$1226 $not$issuer_ls180.v:40742$1514_Y + connect \$1228 $and$issuer_ls180.v:40743$1515_Y + connect \$1231 $and$issuer_ls180.v:40744$1516_Y + connect \$1234 $sub$issuer_ls180.v:40745$1517_Y + connect \$1236 $sshl$issuer_ls180.v:40746$1518_Y + connect \$1238 $ternary$issuer_ls180.v:40747$1519_Y + connect \$1240 $and$issuer_ls180.v:40748$1520_Y + connect \$1243 $and$issuer_ls180.v:40749$1521_Y + connect \$1246 $not$issuer_ls180.v:40750$1522_Y + connect \$1248 $and$issuer_ls180.v:40751$1523_Y + connect \$1251 $and$issuer_ls180.v:40752$1524_Y + connect \$1254 $sub$issuer_ls180.v:40753$1525_Y + connect \$1256 $sshl$issuer_ls180.v:40754$1526_Y + connect \$1258 $ternary$issuer_ls180.v:40755$1527_Y + connect \$1260 $and$issuer_ls180.v:40756$1528_Y + connect \$1263 $and$issuer_ls180.v:40757$1529_Y + connect \$1266 $not$issuer_ls180.v:40758$1530_Y + connect \$1268 $and$issuer_ls180.v:40759$1531_Y + connect \$1271 $and$issuer_ls180.v:40760$1532_Y + connect \$1274 $sub$issuer_ls180.v:40761$1533_Y + connect \$1276 $sshl$issuer_ls180.v:40762$1534_Y + connect \$1278 $ternary$issuer_ls180.v:40763$1535_Y + connect \$1280 $and$issuer_ls180.v:40764$1536_Y + connect \$1283 $and$issuer_ls180.v:40765$1537_Y + connect \$1286 $not$issuer_ls180.v:40766$1538_Y + connect \$1288 $and$issuer_ls180.v:40767$1539_Y + connect \$1291 $and$issuer_ls180.v:40768$1540_Y + connect \$1294 $sub$issuer_ls180.v:40769$1541_Y + connect \$1296 $sshl$issuer_ls180.v:40770$1542_Y + connect \$1298 $ternary$issuer_ls180.v:40771$1543_Y + connect \$1300 $and$issuer_ls180.v:40772$1544_Y + connect \$1303 $and$issuer_ls180.v:40773$1545_Y + connect \$1306 $not$issuer_ls180.v:40774$1546_Y + connect \$1308 $and$issuer_ls180.v:40775$1547_Y + connect \$1311 $and$issuer_ls180.v:40776$1548_Y + connect \$1314 $sub$issuer_ls180.v:40777$1549_Y + connect \$1316 $sshl$issuer_ls180.v:40778$1550_Y + connect \$1318 $ternary$issuer_ls180.v:40779$1551_Y + connect \$1320 $and$issuer_ls180.v:40780$1552_Y + connect \$1323 $and$issuer_ls180.v:40781$1553_Y + connect \$1326 $not$issuer_ls180.v:40782$1554_Y + connect \$1328 $and$issuer_ls180.v:40783$1555_Y + connect \$1331 $and$issuer_ls180.v:40784$1556_Y + connect \$1334 $sub$issuer_ls180.v:40785$1557_Y + connect \$1336 $sshl$issuer_ls180.v:40786$1558_Y + connect \$1338 $ternary$issuer_ls180.v:40787$1559_Y + connect \$1340 $or$issuer_ls180.v:40788$1560_Y + connect \$1342 $or$issuer_ls180.v:40789$1561_Y + connect \$1344 $or$issuer_ls180.v:40790$1562_Y + connect \$1346 $or$issuer_ls180.v:40791$1563_Y + connect \$1348 $or$issuer_ls180.v:40792$1564_Y + connect \$1351 $or$issuer_ls180.v:40793$1565_Y + connect \$1353 $or$issuer_ls180.v:40794$1566_Y + connect \$1355 $or$issuer_ls180.v:40795$1567_Y + connect \$1357 $or$issuer_ls180.v:40796$1568_Y + connect \$1359 $or$issuer_ls180.v:40797$1569_Y + connect \$1361 $and$issuer_ls180.v:40798$1570_Y + connect \$1363 $and$issuer_ls180.v:40799$1571_Y + connect \$1365 $and$issuer_ls180.v:40800$1572_Y + connect \$1367 $and$issuer_ls180.v:40801$1573_Y + connect \$1370 $and$issuer_ls180.v:40802$1574_Y + connect \$1373 $not$issuer_ls180.v:40803$1575_Y + connect \$1375 $and$issuer_ls180.v:40804$1576_Y + connect \$1378 $and$issuer_ls180.v:40805$1577_Y + connect \$1381 $ternary$issuer_ls180.v:40806$1578_Y + connect \$1383 $and$issuer_ls180.v:40807$1579_Y + connect \$1386 $and$issuer_ls180.v:40808$1580_Y + connect \$1389 $not$issuer_ls180.v:40809$1581_Y + connect \$1391 $and$issuer_ls180.v:40810$1582_Y + connect \$1394 $and$issuer_ls180.v:40811$1583_Y + connect \$1397 $ternary$issuer_ls180.v:40812$1584_Y + connect \$1399 $and$issuer_ls180.v:40813$1585_Y + connect \$1402 $and$issuer_ls180.v:40814$1586_Y + connect \$1405 $not$issuer_ls180.v:40815$1587_Y + connect \$1407 $and$issuer_ls180.v:40816$1588_Y + connect \$1410 $and$issuer_ls180.v:40817$1589_Y + connect \$1413 $ternary$issuer_ls180.v:40818$1590_Y + connect \$1415 $or$issuer_ls180.v:40819$1591_Y + connect \$1417 $or$issuer_ls180.v:40820$1592_Y + connect \$1420 $or$issuer_ls180.v:40821$1593_Y + connect \$1422 $or$issuer_ls180.v:40822$1594_Y + connect \$1419 $pos$issuer_ls180.v:40823$1596_Y + connect \$1425 $and$issuer_ls180.v:40824$1597_Y + connect \$1427 $and$issuer_ls180.v:40825$1598_Y + connect \$1429 $and$issuer_ls180.v:40826$1599_Y + connect \$1431 $and$issuer_ls180.v:40827$1600_Y + connect \$1433 $and$issuer_ls180.v:40828$1601_Y + connect \$1436 $and$issuer_ls180.v:40829$1602_Y + connect \$1439 $not$issuer_ls180.v:40830$1603_Y + connect \$1441 $and$issuer_ls180.v:40831$1604_Y + connect \$1444 $and$issuer_ls180.v:40832$1605_Y + connect \$1447 $ternary$issuer_ls180.v:40833$1606_Y + connect \$1449 $and$issuer_ls180.v:40834$1607_Y + connect \$1452 $and$issuer_ls180.v:40835$1608_Y + connect \$1455 $not$issuer_ls180.v:40836$1609_Y + connect \$1457 $and$issuer_ls180.v:40837$1610_Y + connect \$1460 $and$issuer_ls180.v:40838$1611_Y + connect \$1463 $ternary$issuer_ls180.v:40839$1612_Y + connect \$1465 $and$issuer_ls180.v:40840$1613_Y + connect \$1468 $and$issuer_ls180.v:40841$1614_Y + connect \$1471 $not$issuer_ls180.v:40842$1615_Y + connect \$1473 $and$issuer_ls180.v:40843$1616_Y + connect \$1476 $and$issuer_ls180.v:40844$1617_Y + connect \$1479 $ternary$issuer_ls180.v:40845$1618_Y + connect \$1481 $and$issuer_ls180.v:40846$1619_Y + connect \$1484 $and$issuer_ls180.v:40847$1620_Y + connect \$1487 $not$issuer_ls180.v:40848$1621_Y + connect \$1489 $and$issuer_ls180.v:40849$1622_Y + connect \$1492 $and$issuer_ls180.v:40850$1623_Y + connect \$1495 $ternary$issuer_ls180.v:40851$1624_Y + connect \$1497 $or$issuer_ls180.v:40852$1625_Y + connect \$1499 $or$issuer_ls180.v:40853$1626_Y + connect \$1501 $or$issuer_ls180.v:40854$1627_Y + connect \$1503 $or$issuer_ls180.v:40855$1628_Y + connect \$1505 $or$issuer_ls180.v:40856$1629_Y + connect \$1507 $or$issuer_ls180.v:40857$1630_Y + connect \$1509 $and$issuer_ls180.v:40858$1631_Y + connect \$1511 $and$issuer_ls180.v:40859$1632_Y + connect \$1513 $and$issuer_ls180.v:40860$1633_Y + connect \$1515 $and$issuer_ls180.v:40861$1634_Y + connect \$1517 $and$issuer_ls180.v:40862$1635_Y + connect \$1520 $and$issuer_ls180.v:40863$1636_Y + connect \$1523 $not$issuer_ls180.v:40864$1637_Y + connect \$1525 $and$issuer_ls180.v:40865$1638_Y + connect \$1528 $and$issuer_ls180.v:40866$1639_Y + connect \$1531 $ternary$issuer_ls180.v:40867$1640_Y + connect \$1533 $and$issuer_ls180.v:40868$1641_Y + connect \$1536 $and$issuer_ls180.v:40869$1642_Y + connect \$1539 $not$issuer_ls180.v:40870$1643_Y + connect \$1541 $and$issuer_ls180.v:40871$1644_Y + connect \$1544 $and$issuer_ls180.v:40872$1645_Y + connect \$1547 $ternary$issuer_ls180.v:40873$1646_Y + connect \$1549 $and$issuer_ls180.v:40874$1647_Y + connect \$1552 $and$issuer_ls180.v:40875$1648_Y + connect \$1555 $not$issuer_ls180.v:40876$1649_Y + connect \$1557 $and$issuer_ls180.v:40877$1650_Y + connect \$1560 $and$issuer_ls180.v:40878$1651_Y + connect \$1563 $ternary$issuer_ls180.v:40879$1652_Y + connect \$1565 $and$issuer_ls180.v:40880$1653_Y + connect \$1568 $and$issuer_ls180.v:40881$1654_Y + connect \$1571 $not$issuer_ls180.v:40882$1655_Y + connect \$1573 $and$issuer_ls180.v:40883$1656_Y + connect \$1576 $and$issuer_ls180.v:40884$1657_Y + connect \$1579 $ternary$issuer_ls180.v:40885$1658_Y + connect \$1582 $or$issuer_ls180.v:40886$1659_Y + connect \$1584 $or$issuer_ls180.v:40887$1660_Y + connect \$1586 $or$issuer_ls180.v:40888$1661_Y + connect \$1581 $pos$issuer_ls180.v:40889$1663_Y + connect \$1590 $or$issuer_ls180.v:40890$1664_Y + connect \$1592 $or$issuer_ls180.v:40891$1665_Y + connect \$1594 $or$issuer_ls180.v:40892$1666_Y + connect \$1589 $pos$issuer_ls180.v:40893$1668_Y + connect \$1597 $and$issuer_ls180.v:40894$1669_Y + connect \$1599 $and$issuer_ls180.v:40895$1670_Y + connect \$1601 $and$issuer_ls180.v:40896$1671_Y + connect \$1603 $and$issuer_ls180.v:40897$1672_Y + connect \$1605 $and$issuer_ls180.v:40898$1673_Y + connect \$1607 $and$issuer_ls180.v:40899$1674_Y + connect \$1610 $and$issuer_ls180.v:40900$1675_Y + connect \$1614 $not$issuer_ls180.v:40901$1676_Y + connect \$1616 $and$issuer_ls180.v:40902$1677_Y + connect \$161 $and$issuer_ls180.v:40903$1678_Y + connect \$1621 $and$issuer_ls180.v:40904$1679_Y + connect \$1624 $ternary$issuer_ls180.v:40905$1680_Y + connect \$1626 $and$issuer_ls180.v:40906$1681_Y + connect \$160 $reduce_or$issuer_ls180.v:40907$1682_Y + connect \$1629 $and$issuer_ls180.v:40908$1683_Y + connect \$1632 $not$issuer_ls180.v:40909$1684_Y + connect \$1634 $and$issuer_ls180.v:40910$1685_Y + connect \$1637 $and$issuer_ls180.v:40911$1686_Y + connect \$1640 $ternary$issuer_ls180.v:40912$1687_Y + connect \$1642 $and$issuer_ls180.v:40913$1688_Y + connect \$1645 $and$issuer_ls180.v:40914$1689_Y + connect \$1648 $not$issuer_ls180.v:40915$1690_Y + connect \$1650 $and$issuer_ls180.v:40916$1691_Y + connect \$1653 $and$issuer_ls180.v:40917$1692_Y + connect \$1656 $ternary$issuer_ls180.v:40918$1693_Y + connect \$1658 $and$issuer_ls180.v:40919$1694_Y + connect \$165 $and$issuer_ls180.v:40920$1695_Y + connect \$1661 $and$issuer_ls180.v:40921$1696_Y + connect \$1664 $not$issuer_ls180.v:40922$1697_Y + connect \$1666 $and$issuer_ls180.v:40923$1698_Y + connect \$164 $reduce_or$issuer_ls180.v:40924$1699_Y + connect \$1669 $and$issuer_ls180.v:40925$1700_Y + connect \$1672 $ternary$issuer_ls180.v:40926$1701_Y + connect \$1674 $and$issuer_ls180.v:40927$1702_Y + connect \$1677 $and$issuer_ls180.v:40928$1703_Y + connect \$1680 $not$issuer_ls180.v:40929$1704_Y + connect \$1682 $and$issuer_ls180.v:40930$1705_Y + connect \$1685 $and$issuer_ls180.v:40931$1706_Y + connect \$1688 $ternary$issuer_ls180.v:40932$1707_Y + connect \$1690 $or$issuer_ls180.v:40933$1708_Y + connect \$1692 $or$issuer_ls180.v:40934$1709_Y + connect \$1694 $or$issuer_ls180.v:40935$1710_Y + connect \$1696 $or$issuer_ls180.v:40936$1711_Y + connect \$1698 $or$issuer_ls180.v:40937$1712_Y + connect \$169 $and$issuer_ls180.v:40938$1713_Y + connect \$1700 $or$issuer_ls180.v:40939$1714_Y + connect \$1702 $or$issuer_ls180.v:40940$1715_Y + connect \$1704 $or$issuer_ls180.v:40941$1716_Y + connect \$1706 $or$issuer_ls180.v:40942$1717_Y + connect \$1708 $or$issuer_ls180.v:40943$1718_Y + connect \$168 $reduce_or$issuer_ls180.v:40944$1719_Y + connect \$1710 $or$issuer_ls180.v:40945$1720_Y + connect \$1712 $or$issuer_ls180.v:40946$1721_Y + connect \$1714 $and$issuer_ls180.v:40947$1722_Y + connect \$1716 $and$issuer_ls180.v:40948$1723_Y + connect \$1718 $and$issuer_ls180.v:40949$1724_Y + connect \$1721 $and$issuer_ls180.v:40950$1725_Y + connect \$1724 $not$issuer_ls180.v:40951$1726_Y + connect \$1726 $and$issuer_ls180.v:40952$1727_Y + connect \$1729 $and$issuer_ls180.v:40953$1728_Y + connect \$1732 $ternary$issuer_ls180.v:40954$1729_Y + connect \$1734 $and$issuer_ls180.v:40955$1730_Y + connect \$1737 $and$issuer_ls180.v:40956$1731_Y + connect \$173 $and$issuer_ls180.v:40957$1732_Y + connect \$1740 $not$issuer_ls180.v:40958$1733_Y + connect \$1742 $and$issuer_ls180.v:40959$1734_Y + connect \$1745 $and$issuer_ls180.v:40960$1735_Y + connect \$1748 $ternary$issuer_ls180.v:40961$1736_Y + connect \$172 $reduce_or$issuer_ls180.v:40962$1737_Y + connect \$1750 $or$issuer_ls180.v:40963$1738_Y + connect \$1753 $or$issuer_ls180.v:40964$1739_Y + connect \$1752 $pos$issuer_ls180.v:40965$1741_Y + connect \$1756 $and$issuer_ls180.v:40966$1742_Y + connect \$1758 $and$issuer_ls180.v:40967$1743_Y + connect \$1761 $and$issuer_ls180.v:40968$1744_Y + connect \$1764 $not$issuer_ls180.v:40969$1745_Y + connect \$1766 $and$issuer_ls180.v:40970$1746_Y + connect \$1769 $and$issuer_ls180.v:40971$1747_Y + connect \$1772 $ternary$issuer_ls180.v:40972$1748_Y + connect \$1774 $pos$issuer_ls180.v:40973$1750_Y + connect \$1776 $and$issuer_ls180.v:40974$1751_Y + connect \$1778 $and$issuer_ls180.v:40975$1752_Y + connect \$177 $and$issuer_ls180.v:40976$1753_Y + connect \$1781 $and$issuer_ls180.v:40977$1754_Y + connect \$1784 $not$issuer_ls180.v:40978$1755_Y + connect \$1786 $and$issuer_ls180.v:40979$1756_Y + connect \$176 $reduce_or$issuer_ls180.v:40980$1757_Y + connect \$1789 $and$issuer_ls180.v:40981$1758_Y + connect \$1792 $ternary$issuer_ls180.v:40982$1759_Y + connect \$181 $and$issuer_ls180.v:40983$1760_Y + connect \$180 $reduce_or$issuer_ls180.v:40984$1761_Y + connect \$185 $and$issuer_ls180.v:40985$1762_Y + connect \$184 $reduce_or$issuer_ls180.v:40986$1763_Y + connect \$189 $and$issuer_ls180.v:40987$1764_Y + connect \$188 $reduce_or$issuer_ls180.v:40988$1765_Y + connect \$193 $and$issuer_ls180.v:40989$1766_Y + connect \$192 $reduce_or$issuer_ls180.v:40990$1767_Y + connect \$197 $and$issuer_ls180.v:40991$1768_Y + connect \$196 $reduce_or$issuer_ls180.v:40992$1769_Y + connect \$200 $ne$issuer_ls180.v:40993$1770_Y + connect \$203 $sub$issuer_ls180.v:40994$1771_Y + connect \$205 $ne$issuer_ls180.v:40995$1772_Y + connect \$208 $and$issuer_ls180.v:40996$1773_Y + connect \$210 $and$issuer_ls180.v:40997$1774_Y + connect \$212 $eq$issuer_ls180.v:40998$1775_Y + connect \$214 $or$issuer_ls180.v:40999$1776_Y + connect \$216 $and$issuer_ls180.v:41000$1777_Y + connect \$218 $or$issuer_ls180.v:41001$1778_Y + connect \$220 $eq$issuer_ls180.v:41002$1779_Y + connect \$222 $and$issuer_ls180.v:41003$1780_Y + connect \$224 $eq$issuer_ls180.v:41004$1781_Y + connect \$226 $or$issuer_ls180.v:41005$1782_Y + connect \$207 $not$issuer_ls180.v:41006$1783_Y + connect \$229 $not$issuer_ls180.v:41007$1784_Y + connect \$231 $not$issuer_ls180.v:41008$1785_Y + connect \$233 $not$issuer_ls180.v:41009$1786_Y + connect \$236 $and$issuer_ls180.v:41010$1787_Y + connect \$238 $and$issuer_ls180.v:41011$1788_Y + connect \$240 $eq$issuer_ls180.v:41012$1789_Y + connect \$242 $or$issuer_ls180.v:41013$1790_Y + connect \$244 $and$issuer_ls180.v:41014$1791_Y + connect \$246 $or$issuer_ls180.v:41015$1792_Y + connect \$235 $not$issuer_ls180.v:41016$1793_Y + connect \$250 $and$issuer_ls180.v:41017$1794_Y + connect \$252 $and$issuer_ls180.v:41018$1795_Y + connect \$254 $eq$issuer_ls180.v:41019$1796_Y + connect \$256 $or$issuer_ls180.v:41020$1797_Y + connect \$258 $and$issuer_ls180.v:41021$1798_Y + connect \$260 $or$issuer_ls180.v:41022$1799_Y + connect \$262 $and$issuer_ls180.v:41023$1800_Y + connect \$264 $and$issuer_ls180.v:41024$1801_Y + connect \$266 $eq$issuer_ls180.v:41025$1802_Y + connect \$268 $or$issuer_ls180.v:41026$1803_Y + connect \$270 $eq$issuer_ls180.v:41027$1804_Y + connect \$272 $and$issuer_ls180.v:41028$1805_Y + connect \$274 $eq$issuer_ls180.v:41029$1806_Y + connect \$276 $or$issuer_ls180.v:41030$1807_Y + connect \$249 $not$issuer_ls180.v:41031$1808_Y + connect \$280 $and$issuer_ls180.v:41032$1809_Y + connect \$282 $and$issuer_ls180.v:41033$1810_Y + connect \$284 $eq$issuer_ls180.v:41034$1811_Y + connect \$286 $or$issuer_ls180.v:41035$1812_Y + connect \$288 $and$issuer_ls180.v:41036$1813_Y + connect \$290 $or$issuer_ls180.v:41037$1814_Y + connect \$279 $not$issuer_ls180.v:41038$1815_Y + connect \$294 $and$issuer_ls180.v:41039$1816_Y + connect \$296 $and$issuer_ls180.v:41040$1817_Y + connect \$298 $eq$issuer_ls180.v:41041$1818_Y + connect \$300 $or$issuer_ls180.v:41042$1819_Y + connect \$302 $and$issuer_ls180.v:41043$1820_Y + connect \$304 $or$issuer_ls180.v:41044$1821_Y + connect \$293 $not$issuer_ls180.v:41045$1822_Y + connect \$308 $and$issuer_ls180.v:41046$1823_Y + connect \$310 $and$issuer_ls180.v:41047$1824_Y + connect \$312 $eq$issuer_ls180.v:41048$1825_Y + connect \$314 $or$issuer_ls180.v:41049$1826_Y + connect \$316 $and$issuer_ls180.v:41050$1827_Y + connect \$318 $or$issuer_ls180.v:41051$1828_Y + connect \$320 $eq$issuer_ls180.v:41052$1829_Y + connect \$322 $and$issuer_ls180.v:41053$1830_Y + connect \$324 $eq$issuer_ls180.v:41054$1831_Y + connect \$326 $or$issuer_ls180.v:41055$1832_Y + connect \$307 $not$issuer_ls180.v:41056$1833_Y + connect \$329 $not$issuer_ls180.v:41057$1834_Y + connect \$331 $and$issuer_ls180.v:41058$1835_Y + connect \$333 $and$issuer_ls180.v:41059$1836_Y + connect \$335 $not$issuer_ls180.v:41060$1837_Y + connect \$337 $and$issuer_ls180.v:41061$1838_Y + connect \$339 $and$issuer_ls180.v:41062$1839_Y + connect \$341 $ternary$issuer_ls180.v:41063$1840_Y + connect \$343 $and$issuer_ls180.v:41064$1841_Y + connect \$345 $and$issuer_ls180.v:41065$1842_Y + connect \$347 $not$issuer_ls180.v:41066$1843_Y + connect \$349 $and$issuer_ls180.v:41067$1844_Y + connect \$351 $and$issuer_ls180.v:41068$1845_Y + connect \$353 $ternary$issuer_ls180.v:41069$1846_Y + connect \$355 $and$issuer_ls180.v:41070$1847_Y + connect \$357 $and$issuer_ls180.v:41071$1848_Y + connect \$359 $not$issuer_ls180.v:41072$1849_Y + connect \$361 $and$issuer_ls180.v:41073$1850_Y + connect \$363 $and$issuer_ls180.v:41074$1851_Y + connect \$365 $ternary$issuer_ls180.v:41075$1852_Y + connect \$367 $and$issuer_ls180.v:41076$1853_Y + connect \$369 $and$issuer_ls180.v:41077$1854_Y + connect \$371 $not$issuer_ls180.v:41078$1855_Y + connect \$373 $and$issuer_ls180.v:41079$1856_Y + connect \$375 $and$issuer_ls180.v:41080$1857_Y + connect \$377 $ternary$issuer_ls180.v:41081$1858_Y + connect \$379 $and$issuer_ls180.v:41082$1859_Y + connect \$381 $and$issuer_ls180.v:41083$1860_Y + connect \$383 $not$issuer_ls180.v:41084$1861_Y + connect \$385 $and$issuer_ls180.v:41085$1862_Y + connect \$387 $and$issuer_ls180.v:41086$1863_Y + connect \$389 $ternary$issuer_ls180.v:41087$1864_Y + connect \$391 $and$issuer_ls180.v:41088$1865_Y + connect \$393 $and$issuer_ls180.v:41089$1866_Y + connect \$395 $not$issuer_ls180.v:41090$1867_Y + connect \$397 $and$issuer_ls180.v:41091$1868_Y + connect \$399 $and$issuer_ls180.v:41092$1869_Y + connect \$401 $ternary$issuer_ls180.v:41093$1870_Y + connect \$403 $and$issuer_ls180.v:41094$1871_Y + connect \$405 $and$issuer_ls180.v:41095$1872_Y + connect \$407 $not$issuer_ls180.v:41096$1873_Y + connect \$409 $and$issuer_ls180.v:41097$1874_Y + connect \$411 $and$issuer_ls180.v:41098$1875_Y + connect \$413 $ternary$issuer_ls180.v:41099$1876_Y + connect \$415 $and$issuer_ls180.v:41100$1877_Y + connect \$417 $and$issuer_ls180.v:41101$1878_Y + connect \$419 $not$issuer_ls180.v:41102$1879_Y + connect \$421 $and$issuer_ls180.v:41103$1880_Y + connect \$423 $and$issuer_ls180.v:41104$1881_Y + connect \$425 $ternary$issuer_ls180.v:41105$1882_Y + connect \$427 $and$issuer_ls180.v:41106$1883_Y + connect \$429 $and$issuer_ls180.v:41107$1884_Y + connect \$431 $not$issuer_ls180.v:41108$1885_Y + connect \$433 $and$issuer_ls180.v:41109$1886_Y + connect \$435 $and$issuer_ls180.v:41110$1887_Y + connect \$437 $ternary$issuer_ls180.v:41111$1888_Y + connect \$439 $or$issuer_ls180.v:41112$1889_Y + connect \$441 $or$issuer_ls180.v:41113$1890_Y + connect \$443 $or$issuer_ls180.v:41114$1891_Y + connect \$445 $or$issuer_ls180.v:41115$1892_Y + connect \$447 $or$issuer_ls180.v:41116$1893_Y + connect \$449 $or$issuer_ls180.v:41117$1894_Y + connect \$451 $or$issuer_ls180.v:41118$1895_Y + connect \$453 $or$issuer_ls180.v:41119$1896_Y + connect \$455 $reduce_or$issuer_ls180.v:41120$1897_Y + connect \$457 $and$issuer_ls180.v:41121$1898_Y + connect \$459 $and$issuer_ls180.v:41122$1899_Y + connect \$461 $not$issuer_ls180.v:41123$1900_Y + connect \$463 $and$issuer_ls180.v:41124$1901_Y + connect \$465 $and$issuer_ls180.v:41125$1902_Y + connect \$467 $ternary$issuer_ls180.v:41126$1903_Y + connect \$469 $and$issuer_ls180.v:41127$1904_Y + connect \$471 $and$issuer_ls180.v:41128$1905_Y + connect \$473 $not$issuer_ls180.v:41129$1906_Y + connect \$475 $and$issuer_ls180.v:41130$1907_Y + connect \$477 $and$issuer_ls180.v:41131$1908_Y + connect \$479 $ternary$issuer_ls180.v:41132$1909_Y + connect \$481 $and$issuer_ls180.v:41133$1910_Y + connect \$483 $and$issuer_ls180.v:41134$1911_Y + connect \$485 $not$issuer_ls180.v:41135$1912_Y + connect \$487 $and$issuer_ls180.v:41136$1913_Y + connect \$489 $and$issuer_ls180.v:41137$1914_Y + connect \$491 $ternary$issuer_ls180.v:41138$1915_Y + connect \$493 $and$issuer_ls180.v:41139$1916_Y + connect \$495 $and$issuer_ls180.v:41140$1917_Y + connect \$497 $not$issuer_ls180.v:41141$1918_Y + connect \$499 $and$issuer_ls180.v:41142$1919_Y + connect \$501 $and$issuer_ls180.v:41143$1920_Y + connect \$503 $ternary$issuer_ls180.v:41144$1921_Y + connect \$505 $and$issuer_ls180.v:41145$1922_Y + connect \$507 $and$issuer_ls180.v:41146$1923_Y + connect \$509 $not$issuer_ls180.v:41147$1924_Y + connect \$511 $and$issuer_ls180.v:41148$1925_Y + connect \$513 $and$issuer_ls180.v:41149$1926_Y + connect \$515 $ternary$issuer_ls180.v:41150$1927_Y + connect \$517 $and$issuer_ls180.v:41151$1928_Y + connect \$519 $and$issuer_ls180.v:41152$1929_Y + connect \$521 $not$issuer_ls180.v:41153$1930_Y + connect \$523 $and$issuer_ls180.v:41154$1931_Y + connect \$525 $and$issuer_ls180.v:41155$1932_Y + connect \$527 $ternary$issuer_ls180.v:41156$1933_Y + connect \$529 $and$issuer_ls180.v:41157$1934_Y + connect \$531 $and$issuer_ls180.v:41158$1935_Y + connect \$533 $not$issuer_ls180.v:41159$1936_Y + connect \$535 $and$issuer_ls180.v:41160$1937_Y + connect \$537 $and$issuer_ls180.v:41161$1938_Y + connect \$539 $ternary$issuer_ls180.v:41162$1939_Y + connect \$541 $and$issuer_ls180.v:41163$1940_Y + connect \$543 $and$issuer_ls180.v:41164$1941_Y + connect \$545 $not$issuer_ls180.v:41165$1942_Y + connect \$547 $and$issuer_ls180.v:41166$1943_Y + connect \$549 $and$issuer_ls180.v:41167$1944_Y + connect \$551 $ternary$issuer_ls180.v:41168$1945_Y + connect \$553 $or$issuer_ls180.v:41169$1946_Y + connect \$555 $or$issuer_ls180.v:41170$1947_Y + connect \$557 $or$issuer_ls180.v:41171$1948_Y + connect \$559 $or$issuer_ls180.v:41172$1949_Y + connect \$561 $or$issuer_ls180.v:41173$1950_Y + connect \$563 $or$issuer_ls180.v:41174$1951_Y + connect \$565 $or$issuer_ls180.v:41175$1952_Y + connect \$567 $reduce_or$issuer_ls180.v:41176$1953_Y + connect \$569 $and$issuer_ls180.v:41177$1954_Y + connect \$571 $and$issuer_ls180.v:41178$1955_Y + connect \$573 $not$issuer_ls180.v:41179$1956_Y + connect \$575 $and$issuer_ls180.v:41180$1957_Y + connect \$577 $and$issuer_ls180.v:41181$1958_Y + connect \$579 $ternary$issuer_ls180.v:41182$1959_Y + connect \$581 $and$issuer_ls180.v:41183$1960_Y + connect \$583 $and$issuer_ls180.v:41184$1961_Y + connect \$585 $not$issuer_ls180.v:41185$1962_Y + connect \$587 $and$issuer_ls180.v:41186$1963_Y + connect \$589 $and$issuer_ls180.v:41187$1964_Y + connect \$591 $ternary$issuer_ls180.v:41188$1965_Y + connect \$593 $or$issuer_ls180.v:41189$1966_Y + connect \$595 $reduce_or$issuer_ls180.v:41190$1967_Y + connect \$597 $and$issuer_ls180.v:41191$1968_Y + connect \$599 $and$issuer_ls180.v:41192$1969_Y + connect \$601 $eq$issuer_ls180.v:41193$1970_Y + connect \$603 $or$issuer_ls180.v:41194$1971_Y + connect \$605 $and$issuer_ls180.v:41195$1972_Y + connect \$607 $or$issuer_ls180.v:41196$1973_Y + connect \$609 $and$issuer_ls180.v:41197$1974_Y + connect \$611 $and$issuer_ls180.v:41198$1975_Y + connect \$613 $not$issuer_ls180.v:41199$1976_Y + connect \$615 $and$issuer_ls180.v:41200$1977_Y + connect \$617 $and$issuer_ls180.v:41201$1978_Y + connect \$619 $ternary$issuer_ls180.v:41202$1979_Y + connect \$621 $and$issuer_ls180.v:41203$1980_Y + connect \$623 $and$issuer_ls180.v:41204$1981_Y + connect \$625 $not$issuer_ls180.v:41205$1982_Y + connect \$627 $and$issuer_ls180.v:41206$1983_Y + connect \$629 $and$issuer_ls180.v:41207$1984_Y + connect \$631 $ternary$issuer_ls180.v:41208$1985_Y + connect \$633 $and$issuer_ls180.v:41209$1986_Y + connect \$635 $and$issuer_ls180.v:41210$1987_Y + connect \$637 $not$issuer_ls180.v:41211$1988_Y + connect \$639 $and$issuer_ls180.v:41212$1989_Y + connect \$641 $and$issuer_ls180.v:41213$1990_Y + connect \$643 $ternary$issuer_ls180.v:41214$1991_Y + connect \$645 $and$issuer_ls180.v:41215$1992_Y + connect \$647 $and$issuer_ls180.v:41216$1993_Y + connect \$649 $not$issuer_ls180.v:41217$1994_Y + connect \$651 $and$issuer_ls180.v:41218$1995_Y + connect \$653 $and$issuer_ls180.v:41219$1996_Y + connect \$655 $ternary$issuer_ls180.v:41220$1997_Y + connect \$657 $and$issuer_ls180.v:41221$1998_Y + connect \$659 $and$issuer_ls180.v:41222$1999_Y + connect \$661 $not$issuer_ls180.v:41223$2000_Y + connect \$663 $and$issuer_ls180.v:41224$2001_Y + connect \$665 $and$issuer_ls180.v:41225$2002_Y + connect \$667 $ternary$issuer_ls180.v:41226$2003_Y + connect \$669 $and$issuer_ls180.v:41227$2004_Y + connect \$671 $and$issuer_ls180.v:41228$2005_Y + connect \$673 $not$issuer_ls180.v:41229$2006_Y + connect \$675 $and$issuer_ls180.v:41230$2007_Y + connect \$677 $and$issuer_ls180.v:41231$2008_Y + connect \$679 $ternary$issuer_ls180.v:41232$2009_Y + connect \$682 $or$issuer_ls180.v:41233$2010_Y + connect \$684 $or$issuer_ls180.v:41234$2011_Y + connect \$686 $or$issuer_ls180.v:41235$2012_Y + connect \$688 $or$issuer_ls180.v:41236$2013_Y + connect \$690 $or$issuer_ls180.v:41237$2014_Y + connect \$681 $pos$issuer_ls180.v:41238$2016_Y + connect \$693 $eq$issuer_ls180.v:41239$2017_Y + connect \$695 $and$issuer_ls180.v:41240$2018_Y + connect \$697 $eq$issuer_ls180.v:41241$2019_Y + connect \$699 $or$issuer_ls180.v:41242$2020_Y + connect \$701 $and$issuer_ls180.v:41243$2021_Y + connect \$703 $and$issuer_ls180.v:41244$2022_Y + connect \$705 $not$issuer_ls180.v:41245$2023_Y + connect \$707 $and$issuer_ls180.v:41246$2024_Y + connect \$709 $and$issuer_ls180.v:41247$2025_Y + connect \$711 $ternary$issuer_ls180.v:41248$2026_Y + connect \$713 $and$issuer_ls180.v:41249$2027_Y + connect \$715 $and$issuer_ls180.v:41250$2028_Y + connect \$717 $not$issuer_ls180.v:41251$2029_Y + connect \$719 $and$issuer_ls180.v:41252$2030_Y + connect \$721 $and$issuer_ls180.v:41253$2031_Y + connect \$723 $ternary$issuer_ls180.v:41254$2032_Y + connect \$725 $and$issuer_ls180.v:41255$2033_Y + connect \$727 $and$issuer_ls180.v:41256$2034_Y + connect \$729 $not$issuer_ls180.v:41257$2035_Y + connect \$731 $and$issuer_ls180.v:41258$2036_Y + connect \$733 $and$issuer_ls180.v:41259$2037_Y + connect \$735 $ternary$issuer_ls180.v:41260$2038_Y + connect \$738 $or$issuer_ls180.v:41261$2039_Y + connect \$740 $or$issuer_ls180.v:41262$2040_Y + connect \$737 $pos$issuer_ls180.v:41263$2042_Y + connect \$743 $and$issuer_ls180.v:41264$2043_Y + connect \$745 $and$issuer_ls180.v:41265$2044_Y + connect \$747 $eq$issuer_ls180.v:41266$2045_Y + connect \$749 $or$issuer_ls180.v:41267$2046_Y + connect \$751 $and$issuer_ls180.v:41268$2047_Y + connect \$753 $and$issuer_ls180.v:41269$2048_Y + connect \$755 $not$issuer_ls180.v:41270$2049_Y + connect \$757 $and$issuer_ls180.v:41271$2050_Y + connect \$759 $and$issuer_ls180.v:41272$2051_Y + connect \$761 $ternary$issuer_ls180.v:41273$2052_Y + connect \$763 $and$issuer_ls180.v:41274$2053_Y + connect \$765 $and$issuer_ls180.v:41275$2054_Y + connect \$767 $not$issuer_ls180.v:41276$2055_Y + connect \$769 $and$issuer_ls180.v:41277$2056_Y + connect \$771 $and$issuer_ls180.v:41278$2057_Y + connect \$773 $ternary$issuer_ls180.v:41279$2058_Y + connect \$775 $and$issuer_ls180.v:41280$2059_Y + connect \$777 $and$issuer_ls180.v:41281$2060_Y + connect \$779 $not$issuer_ls180.v:41282$2061_Y + connect \$781 $and$issuer_ls180.v:41283$2062_Y + connect \$783 $and$issuer_ls180.v:41284$2063_Y + connect \$785 $sub$issuer_ls180.v:41285$2064_Y + connect \$787 $sshl$issuer_ls180.v:41286$2065_Y + connect \$789 $ternary$issuer_ls180.v:41287$2066_Y + connect \$791 $and$issuer_ls180.v:41288$2067_Y + connect \$793 $and$issuer_ls180.v:41289$2068_Y + connect \$795 $not$issuer_ls180.v:41290$2069_Y + connect \$797 $and$issuer_ls180.v:41291$2070_Y + connect \$799 $and$issuer_ls180.v:41292$2071_Y + connect \$801 $sub$issuer_ls180.v:41293$2072_Y + connect \$803 $sshl$issuer_ls180.v:41294$2073_Y + connect \$805 $ternary$issuer_ls180.v:41295$2074_Y + connect \$808 $or$issuer_ls180.v:41296$2075_Y + connect \$810 $and$issuer_ls180.v:41297$2076_Y + connect \$812 $and$issuer_ls180.v:41298$2077_Y + connect \$814 $not$issuer_ls180.v:41299$2078_Y + connect \$816 $and$issuer_ls180.v:41300$2079_Y + connect \$818 $and$issuer_ls180.v:41301$2080_Y + connect \$820 $sub$issuer_ls180.v:41302$2081_Y + connect \$822 $sshl$issuer_ls180.v:41303$2082_Y + connect \$824 $ternary$issuer_ls180.v:41304$2083_Y + connect \$826 $and$issuer_ls180.v:41305$2084_Y + connect \$828 $and$issuer_ls180.v:41306$2085_Y + connect \$830 $not$issuer_ls180.v:41307$2086_Y + connect \$832 $and$issuer_ls180.v:41308$2087_Y + connect \$834 $and$issuer_ls180.v:41309$2088_Y + connect \$836 $sub$issuer_ls180.v:41310$2089_Y + connect \$838 $sshl$issuer_ls180.v:41311$2090_Y + connect \$840 $ternary$issuer_ls180.v:41312$2091_Y + connect \$842 $and$issuer_ls180.v:41313$2092_Y + connect \$844 $and$issuer_ls180.v:41314$2093_Y + connect \$846 $not$issuer_ls180.v:41315$2094_Y + connect \$848 $and$issuer_ls180.v:41316$2095_Y + connect \$850 $and$issuer_ls180.v:41317$2096_Y + connect \$852 $ternary$issuer_ls180.v:41318$2097_Y + connect \$854 $and$issuer_ls180.v:41319$2098_Y + connect \$856 $and$issuer_ls180.v:41320$2099_Y + connect \$858 $not$issuer_ls180.v:41321$2100_Y + connect \$860 $and$issuer_ls180.v:41322$2101_Y + connect \$862 $and$issuer_ls180.v:41323$2102_Y + connect \$864 $ternary$issuer_ls180.v:41324$2103_Y + connect \$866 $and$issuer_ls180.v:41325$2104_Y + connect \$868 $and$issuer_ls180.v:41326$2105_Y + connect \$870 $not$issuer_ls180.v:41327$2106_Y + connect \$872 $and$issuer_ls180.v:41328$2107_Y + connect \$874 $and$issuer_ls180.v:41329$2108_Y + connect \$876 $ternary$issuer_ls180.v:41330$2109_Y + connect \$878 $or$issuer_ls180.v:41331$2110_Y + connect \$880 $or$issuer_ls180.v:41332$2111_Y + connect \$882 $reduce_or$issuer_ls180.v:41333$2112_Y + connect \$884 $and$issuer_ls180.v:41334$2113_Y + connect \$886 $and$issuer_ls180.v:41335$2114_Y + connect \$888 $not$issuer_ls180.v:41336$2115_Y + connect \$890 $and$issuer_ls180.v:41337$2116_Y + connect \$892 $and$issuer_ls180.v:41338$2117_Y + connect \$894 $ternary$issuer_ls180.v:41339$2118_Y + connect \$896 $and$issuer_ls180.v:41340$2119_Y + connect \$898 $and$issuer_ls180.v:41341$2120_Y + connect \$900 $not$issuer_ls180.v:41342$2121_Y + connect \$902 $and$issuer_ls180.v:41343$2122_Y + connect \$904 $and$issuer_ls180.v:41344$2123_Y + connect \$906 $ternary$issuer_ls180.v:41345$2124_Y + connect \$908 $or$issuer_ls180.v:41346$2125_Y + connect \$910 $reduce_or$issuer_ls180.v:41347$2126_Y + connect \$912 $and$issuer_ls180.v:41348$2127_Y + connect \$914 $and$issuer_ls180.v:41349$2128_Y + connect \$916 $not$issuer_ls180.v:41350$2129_Y + connect \$918 $and$issuer_ls180.v:41351$2130_Y + connect \$920 $and$issuer_ls180.v:41352$2131_Y + connect \$922 $ternary$issuer_ls180.v:41353$2132_Y + connect \$924 $reduce_or$issuer_ls180.v:41354$2133_Y + connect \$926 $and$issuer_ls180.v:41355$2134_Y + connect \$928 $and$issuer_ls180.v:41356$2135_Y + connect \$930 $and$issuer_ls180.v:41357$2136_Y + connect \$932 $and$issuer_ls180.v:41358$2137_Y + connect \$934 $and$issuer_ls180.v:41359$2138_Y + connect \$936 $and$issuer_ls180.v:41360$2139_Y + connect \$938 $and$issuer_ls180.v:41361$2140_Y + connect \$940 $and$issuer_ls180.v:41362$2141_Y + connect \$942 $and$issuer_ls180.v:41363$2142_Y + connect \$944 $and$issuer_ls180.v:41364$2143_Y + connect \$946 $and$issuer_ls180.v:41365$2144_Y + connect \$948 $and$issuer_ls180.v:41366$2145_Y + connect \$950 $not$issuer_ls180.v:41367$2146_Y + connect \$952 $and$issuer_ls180.v:41368$2147_Y + connect \$958 $and$issuer_ls180.v:41369$2148_Y + connect \$960 $ternary$issuer_ls180.v:41370$2149_Y + connect \$962 $and$issuer_ls180.v:41371$2150_Y + connect \$965 $and$issuer_ls180.v:41372$2151_Y + connect \$969 $not$issuer_ls180.v:41373$2152_Y + connect \$971 $and$issuer_ls180.v:41374$2153_Y + connect \$976 $and$issuer_ls180.v:41375$2154_Y + connect \$979 $ternary$issuer_ls180.v:41376$2155_Y + connect \$981 $and$issuer_ls180.v:41377$2156_Y + connect \$984 $and$issuer_ls180.v:41378$2157_Y + connect \$988 $not$issuer_ls180.v:41379$2158_Y + connect \$990 $and$issuer_ls180.v:41380$2159_Y + connect \$997 $and$issuer_ls180.v:41381$2160_Y + connect \$202 \$203 + connect \$807 \$808 + connect \$1135 \$1152 + connect \$1350 \$1359 + connect \o_ok 1'0 + connect \ea_ok 1'0 + connect \coresync_rst \core_reset_i + connect \spr_spr1__wen \wp$1788 + connect \spr_spr1__addr$159 \addr_en$1791 [6:0] + connect \spr_spr1__data_i \fus_dest2_o$153 + connect \addr_en$1791 \$1792 + connect \wp$1788 \$1789 + connect \wr_pick_rise$1035 \$1786 + connect \wr_pick$1780 \$1781 + connect \wrpick_SPR_spr1_i \$1778 + connect \wrflag_spr0_spr1_1 \$1776 + connect \state_wen \$1774 + connect \state_data_i$158 \fus_dest5_o$152 + connect \addr_en$1771 \$1772 + connect \wp$1768 \$1769 + connect \wr_pick_rise$995 \$1766 + connect \wr_pick$1760 \$1761 + connect \wrpick_STATE_msr_i \$1758 + connect \wrflag_trap0_msr_4 \$1756 + connect \state_nia_wen \$1752 + connect \state_data_i \$1750 + connect \addr_en$1747 \$1748 + connect \wp$1744 \$1745 + connect \wr_pick_rise$994 \$1742 + connect \wr_pick$1736 \$1737 + connect \wrflag_trap0_nia_3 \$1734 + connect \addr_en$1731 \$1732 + connect \wp$1728 \$1729 + connect \wr_pick_rise$1619 \$1726 + connect \wr_pick$1720 \$1721 + connect \wrpick_STATE_nia_i [1] \$1718 + connect \wrpick_STATE_nia_i [0] \$1716 + connect \wrflag_branch0_nia_2 \$1714 + connect \fast_dest1__wen \$1712 + connect \fast_dest1__addr \$1704 + connect \fast_dest1__data_i \$1696 + connect \addr_en$1687 \$1688 + connect \wp$1684 \$1685 + connect \wr_pick_rise$993 \$1682 + connect \wr_pick$1676 \$1677 + connect \wrflag_trap0_fast1_2 \$1674 + connect \addr_en$1671 \$1672 + connect \wp$1668 \$1669 + connect \wr_pick_rise$1618 \$1666 + connect \wr_pick$1660 \$1661 + connect \wrflag_branch0_fast1_1 \$1658 + connect \addr_en$1655 \$1656 + connect \wp$1652 \$1653 + connect \wr_pick_rise$1034 \$1650 + connect \wr_pick$1644 \$1645 + connect \wrflag_spr0_fast1_2 \$1642 + connect \addr_en$1639 \$1640 + connect \wp$1636 \$1637 + connect \wr_pick_rise$992 \$1634 + connect \wr_pick$1628 \$1629 + connect \wrflag_trap0_fast1_1 \$1626 + connect \addr_en$1623 \$1624 + connect \wp$1620 \$1621 + connect \fus_cu_wr__go_i$140 [2] \wr_pick_rise$1619 + connect \fus_cu_wr__go_i$140 [1] \wr_pick_rise$1618 + connect \fus_cu_wr__go_i$140 [0] \wr_pick_rise$1613 + connect \wr_pick_rise$1613 \$1616 + connect \wr_pick$1609 \$1610 + connect \wrpick_FAST_fast1_i [4] \$1607 + connect \wrpick_FAST_fast1_i [3] \$1605 + connect \wrpick_FAST_fast1_i [2] \$1603 + connect \wrpick_FAST_fast1_i [1] \$1601 + connect \wrpick_FAST_fast1_i [0] \$1599 + connect \wrflag_branch0_fast1_0 \$1597 + connect \xer_wen$157 \$1589 + connect \xer_data_i$156 \$1581 + connect \addr_en$1578 \$1579 + connect \wp$1575 \$1576 + connect \wr_pick_rise$1075 \$1573 + connect \wr_pick$1567 \$1568 + connect \wrflag_mul0_xer_so_3 \$1565 + connect \addr_en$1562 \$1563 + connect \wp$1559 \$1560 + connect \wr_pick_rise$1055 \$1557 + connect \wr_pick$1551 \$1552 + connect \wrflag_div0_xer_so_3 \$1549 + connect \addr_en$1546 \$1547 + connect \wp$1543 \$1544 + connect \wr_pick_rise$1033 \$1541 + connect \wr_pick$1535 \$1536 + connect \wrflag_spr0_xer_so_3 \$1533 + connect \addr_en$1530 \$1531 + connect \wp$1527 \$1528 + connect \wr_pick_rise$957 \$1525 + connect \wr_pick$1519 \$1520 + connect \wrpick_XER_xer_so_i [3] \$1517 + connect \wrpick_XER_xer_so_i [2] \$1515 + connect \wrpick_XER_xer_so_i [1] \$1513 + connect \wrpick_XER_xer_so_i [0] \$1511 + connect \wrflag_alu0_xer_so_4 \$1509 + connect \xer_wen$155 \$1507 + connect \xer_data_i$154 \$1501 + connect \addr_en$1494 \$1495 + connect \wp$1491 \$1492 + connect \wr_pick_rise$1074 \$1489 + connect \wr_pick$1483 \$1484 + connect \wrflag_mul0_xer_ov_2 \$1481 + connect \addr_en$1478 \$1479 + connect \wp$1475 \$1476 + connect \wr_pick_rise$1054 \$1473 + connect \wr_pick$1467 \$1468 + connect \wrflag_div0_xer_ov_2 \$1465 + connect \addr_en$1462 \$1463 + connect \wp$1459 \$1460 + connect \wr_pick_rise$1032 \$1457 + connect \wr_pick$1451 \$1452 + connect \wrflag_spr0_xer_ov_4 \$1449 + connect \addr_en$1446 \$1447 + connect \wp$1443 \$1444 + connect \wr_pick_rise$956 \$1441 + connect \wr_pick$1435 \$1436 + connect \wrpick_XER_xer_ov_i [3] \$1433 + connect \wrpick_XER_xer_ov_i [2] \$1431 + connect \wrpick_XER_xer_ov_i [1] \$1429 + connect \wrpick_XER_xer_ov_i [0] \$1427 + connect \wrflag_alu0_xer_ov_3 \$1425 + connect \xer_wen \$1419 + connect \xer_data_i \$1417 + connect \addr_en$1412 \$1413 + connect \wp$1409 \$1410 + connect \wr_pick_rise$1094 \$1407 + connect \wr_pick$1401 \$1402 + connect \wrflag_shiftrot0_xer_ca_2 \$1399 + connect \addr_en$1396 \$1397 + connect \wp$1393 \$1394 + connect \wr_pick_rise$1031 \$1391 + connect \wr_pick$1385 \$1386 + connect \wrflag_spr0_xer_ca_5 \$1383 + connect \addr_en$1380 \$1381 + connect \wp$1377 \$1378 + connect \wr_pick_rise$955 \$1375 + connect \wr_pick$1369 \$1370 + connect \wrpick_XER_xer_ca_i [2] \$1367 + connect \wrpick_XER_xer_ca_i [1] \$1365 + connect \wrpick_XER_xer_ca_i [0] \$1363 + connect \wrflag_alu0_xer_ca_2 \$1361 + connect \cr_wen \$1359 [7:0] + connect \cr_data_i \$1348 + connect \addr_en$1333 \$1338 + connect \wp$1330 \$1331 + connect \wr_pick_rise$1093 \$1328 + connect \wr_pick$1322 \$1323 + connect \wrflag_shiftrot0_cr_a_1 \$1320 + connect \addr_en$1313 \$1318 + connect \wp$1310 \$1311 + connect \wr_pick_rise$1073 \$1308 + connect \wr_pick$1302 \$1303 + connect \wrflag_mul0_cr_a_1 \$1300 + connect \addr_en$1293 \$1298 + connect \wp$1290 \$1291 + connect \wr_pick_rise$1053 \$1288 + connect \wr_pick$1282 \$1283 + connect \wrflag_div0_cr_a_1 \$1280 + connect \addr_en$1273 \$1278 + connect \wp$1270 \$1271 + connect \wr_pick_rise$1013 \$1268 + connect \wr_pick$1262 \$1263 + connect \wrflag_logical0_cr_a_1 \$1260 + connect \addr_en$1253 \$1258 + connect \wp$1250 \$1251 + connect \wr_pick_rise$974 \$1248 + connect \wr_pick$1242 \$1243 + connect \wrflag_cr0_cr_a_2 \$1240 + connect \addr_en$1233 \$1238 + connect \wp$1230 \$1231 + connect \wr_pick_rise$954 \$1228 + connect \wr_pick$1222 \$1223 + connect \wrpick_CR_cr_a_i [5] \$1220 + connect \wrpick_CR_cr_a_i [4] \$1218 + connect \wrpick_CR_cr_a_i [3] \$1216 + connect \wrpick_CR_cr_a_i [2] \$1214 + connect \wrpick_CR_cr_a_i [1] \$1212 + connect \wrpick_CR_cr_a_i [0] \$1210 + connect \wrflag_alu0_cr_a_1 \$1208 + connect \cr_full_wr__wen \addr_en$1205 + connect \cr_full_wr__data_i \fus_dest2_o + connect \addr_en$1205 \$1206 + connect \wp$1202 \$1203 + connect \wr_pick_rise$973 \$1200 + connect \wr_pick$1194 \$1195 + connect \wrpick_CR_full_cr_i \$1192 + connect \wrflag_cr0_full_cr_1 \$1190 + connect \int_dest1__wen \$1188 + connect \int_dest1__addr \$1170 + connect \int_dest1__data_i \$1152 [63:0] + connect \addr_en$1132 \$1133 + connect \wp$1129 \$1130 + connect \wr_pick_rise$1112 \$1127 + connect \wr_pick$1121 \$1122 + connect \wrflag_ldst0_o_1 \$1119 + connect \addr_en$1116 \$1117 + connect \wp$1113 \$1114 + connect \fus_cu_wr__go_i$105 [1] \wr_pick_rise$1112 + connect \fus_cu_wr__go_i$105 [0] \wr_pick_rise$1107 + connect \wr_pick_rise$1107 \$1110 + connect \wr_pick$1103 \$1104 + connect \wrflag_ldst0_o_0 \$1101 + connect \addr_en$1098 \$1099 + connect \wp$1095 \$1096 + connect \fus_cu_wr__go_i$103 [2] \wr_pick_rise$1094 + connect \fus_cu_wr__go_i$103 [1] \wr_pick_rise$1093 + connect \fus_cu_wr__go_i$103 [0] \wr_pick_rise$1088 + connect \wr_pick_rise$1088 \$1091 + connect \wr_pick$1084 \$1085 + connect \wrflag_shiftrot0_o_0 \$1082 + connect \addr_en$1079 \$1080 + connect \wp$1076 \$1077 + connect \fus_cu_wr__go_i$100 [3] \wr_pick_rise$1075 + connect \fus_cu_wr__go_i$100 [2] \wr_pick_rise$1074 + connect \fus_cu_wr__go_i$100 [1] \wr_pick_rise$1073 + connect \fus_cu_wr__go_i$100 [0] \wr_pick_rise$1068 + connect \wr_pick_rise$1068 \$1071 + connect \wr_pick$1064 \$1065 + connect \wrflag_mul0_o_0 \$1062 + connect \addr_en$1059 \$1060 + connect \wp$1056 \$1057 + connect \fus_cu_wr__go_i$97 [3] \wr_pick_rise$1055 + connect \fus_cu_wr__go_i$97 [2] \wr_pick_rise$1054 + connect \fus_cu_wr__go_i$97 [1] \wr_pick_rise$1053 + connect \fus_cu_wr__go_i$97 [0] \wr_pick_rise$1048 + connect \wr_pick_rise$1048 \$1051 + connect \wr_pick$1044 \$1045 + connect \wrflag_div0_o_0 \$1042 + connect \addr_en$1039 \$1040 + connect \wp$1036 \$1037 + connect \fus_cu_wr__go_i$94 [1] \wr_pick_rise$1035 + connect \fus_cu_wr__go_i$94 [2] \wr_pick_rise$1034 + connect \fus_cu_wr__go_i$94 [3] \wr_pick_rise$1033 + connect \fus_cu_wr__go_i$94 [4] \wr_pick_rise$1032 + connect \fus_cu_wr__go_i$94 [5] \wr_pick_rise$1031 + connect \fus_cu_wr__go_i$94 [0] \wr_pick_rise$1026 + connect \wr_pick_rise$1026 \$1029 + connect \wr_pick$1022 \$1023 + connect \wrflag_spr0_o_0 \$1020 + connect \addr_en$1017 \$1018 + connect \wp$1014 \$1015 + connect \fus_cu_wr__go_i$91 [1] \wr_pick_rise$1013 + connect \fus_cu_wr__go_i$91 [0] \wr_pick_rise$1008 + connect \wr_pick_rise$1008 \$1011 + connect \wr_pick$1004 \$1005 + connect \wrflag_logical0_o_0 \$1002 + connect \addr_en$999 \$1000 + connect \wp$996 \$997 + connect \fus_cu_wr__go_i$88 [4] \wr_pick_rise$995 + connect \fus_cu_wr__go_i$88 [3] \wr_pick_rise$994 + connect \fus_cu_wr__go_i$88 [2] \wr_pick_rise$993 + connect \fus_cu_wr__go_i$88 [1] \wr_pick_rise$992 + connect \fus_cu_wr__go_i$88 [0] \wr_pick_rise$987 + connect \wr_pick_rise$987 \$990 + connect \wr_pick$983 \$984 + connect \wrflag_trap0_o_0 \$981 + connect \addr_en$978 \$979 + connect \wp$975 \$976 + connect \fus_cu_wr__go_i$85 [2] \wr_pick_rise$974 + connect \fus_cu_wr__go_i$85 [1] \wr_pick_rise$973 + connect \fus_cu_wr__go_i$85 [0] \wr_pick_rise$968 + connect \wr_pick_rise$968 \$971 + connect \wr_pick$964 \$965 + connect \wrflag_cr0_o_0 \$962 + connect \addr_en \$960 + connect \wp \$958 + connect \fus_cu_wr__go_i [4] \wr_pick_rise$957 + connect \fus_cu_wr__go_i [3] \wr_pick_rise$956 + connect \fus_cu_wr__go_i [2] \wr_pick_rise$955 + connect \fus_cu_wr__go_i [1] \wr_pick_rise$954 + connect \fus_cu_wr__go_i [0] \wr_pick_rise + connect \wr_pick_rise \$952 + connect \wr_pick \$948 + connect \wrpick_INT_o_i [9] \$946 + connect \wrpick_INT_o_i [8] \$944 + connect \wrpick_INT_o_i [7] \$942 + connect \wrpick_INT_o_i [6] \$940 + connect \wrpick_INT_o_i [5] \$938 + connect \wrpick_INT_o_i [4] \$936 + connect \wrpick_INT_o_i [3] \$934 + connect \wrpick_INT_o_i [2] \$932 + connect \wrpick_INT_o_i [1] \$930 + connect \wrpick_INT_o_i [0] \$928 + connect \wrflag_alu0_o_0 \$926 + connect \spr_spr1__ren \$924 + connect \spr_spr1__addr \addr_en_SPR_spr1_spr0_0 [6:0] + connect \addr_en_SPR_spr1_spr0_0 \$922 + connect \rp_SPR_spr1_spr0_0 \$920 + connect \rdpick_SPR_spr1_i \pick_SPR_spr1_spr0_0 + connect \pick_SPR_spr1_spr0_0 \$918 + connect \rdflag_SPR_spr1_0 \core_spr1_ok + connect \fast_src2__ren \$910 + connect \fast_src2__addr \$908 + connect \addr_en_FAST_fast2_trap0_1 \$906 + connect \rp_FAST_fast2_trap0_1 \$904 + connect \pick_FAST_fast2_trap0_1 \$902 + connect \addr_en_FAST_fast2_branch0_0 \$894 + connect \rp_FAST_fast2_branch0_0 \$892 + connect \rdpick_FAST_fast2_i [1] \pick_FAST_fast2_trap0_1 + connect \rdpick_FAST_fast2_i [0] \pick_FAST_fast2_branch0_0 + connect \pick_FAST_fast2_branch0_0 \$890 + connect \rdflag_FAST_fast2_0 \core_fast2_ok + connect \fast_src1__ren \$882 + connect \fast_src1__addr \$880 + connect \addr_en_FAST_fast1_spr0_2 \$876 + connect \rp_FAST_fast1_spr0_2 \$874 + connect \pick_FAST_fast1_spr0_2 \$872 + connect \addr_en_FAST_fast1_trap0_1 \$864 + connect \rp_FAST_fast1_trap0_1 \$862 + connect \pick_FAST_fast1_trap0_1 \$860 + connect \addr_en_FAST_fast1_branch0_0 \$852 + connect \rp_FAST_fast1_branch0_0 \$850 + connect \rdpick_FAST_fast1_i [2] \pick_FAST_fast1_spr0_2 + connect \rdpick_FAST_fast1_i [1] \pick_FAST_fast1_trap0_1 + connect \rdpick_FAST_fast1_i [0] \pick_FAST_fast1_branch0_0 + connect \pick_FAST_fast1_branch0_0 \$848 + connect \rdflag_FAST_fast1_0 \core_fast1_ok + connect \cr_src3__ren \addr_en_CR_cr_c_cr0_0 [7:0] + connect \addr_en_CR_cr_c_cr0_0 \$840 + connect \rp_CR_cr_c_cr0_0 \$834 + connect \rdpick_CR_cr_c_i \pick_CR_cr_c_cr0_0 + connect \pick_CR_cr_c_cr0_0 \$832 + connect \rdflag_CR_cr_c_0 \core_cr_in2_ok$2 + connect \cr_src2__ren \addr_en_CR_cr_b_cr0_0 [7:0] + connect \addr_en_CR_cr_b_cr0_0 \$824 + connect \rp_CR_cr_b_cr0_0 \$818 + connect \rdpick_CR_cr_b_i \pick_CR_cr_b_cr0_0 + connect \pick_CR_cr_b_cr0_0 \$816 + connect \rdflag_CR_cr_b_0 \core_cr_in2_ok + connect \cr_src1__ren \$808 [7:0] + connect \addr_en_CR_cr_a_branch0_1 \$805 + connect \rp_CR_cr_a_branch0_1 \$799 + connect \fus_cu_rd__go_i$73 [1] \dp_FAST_fast2_branch0_0 + connect \fus_cu_rd__go_i$73 [0] \dp_FAST_fast1_branch0_0 + connect \fus_cu_rd__go_i$73 [2] \dp_CR_cr_a_branch0_1 + connect \pick_CR_cr_a_branch0_1 \$797 + connect \addr_en_CR_cr_a_cr0_0 \$789 + connect \rp_CR_cr_a_cr0_0 \$783 + connect \rdpick_CR_cr_a_i [1] \pick_CR_cr_a_branch0_1 + connect \rdpick_CR_cr_a_i [0] \pick_CR_cr_a_cr0_0 + connect \pick_CR_cr_a_cr0_0 \$781 + connect \rdflag_CR_cr_a_0 \core_cr_in1_ok + connect \cr_full_rd__ren \addr_en_CR_full_cr_cr0_0 + connect \addr_en_CR_full_cr_cr0_0 \$773 + connect \rp_CR_full_cr_cr0_0 \$771 + connect \rdpick_CR_full_cr_i \pick_CR_full_cr_cr0_0 + connect \pick_CR_full_cr_cr0_0 \$769 + connect \rdflag_CR_full_cr_0 \core_core_cr_rd_ok + connect \xer_src3__ren \addr_en_XER_xer_ov_spr0_0 + connect \addr_en_XER_xer_ov_spr0_0 \$761 + connect \rp_XER_xer_ov_spr0_0 \$759 + connect \rdpick_XER_xer_ov_i \pick_XER_xer_ov_spr0_0 + connect \pick_XER_xer_ov_spr0_0 \$757 + connect \rdflag_XER_xer_ov_0 \$749 + connect \xer_src2__ren \$737 + connect \addr_en_XER_xer_ca_shiftrot0_2 \$735 + connect \rp_XER_xer_ca_shiftrot0_2 \$733 + connect \pick_XER_xer_ca_shiftrot0_2 \$731 + connect \addr_en_XER_xer_ca_spr0_1 \$723 + connect \rp_XER_xer_ca_spr0_1 \$721 + connect \pick_XER_xer_ca_spr0_1 \$719 + connect \addr_en_XER_xer_ca_alu0_0 \$711 + connect \rp_XER_xer_ca_alu0_0 \$709 + connect \rdpick_XER_xer_ca_i [2] \pick_XER_xer_ca_shiftrot0_2 + connect \rdpick_XER_xer_ca_i [1] \pick_XER_xer_ca_spr0_1 + connect \rdpick_XER_xer_ca_i [0] \pick_XER_xer_ca_alu0_0 + connect \pick_XER_xer_ca_alu0_0 \$707 + connect \rdflag_XER_xer_ca_0 \$699 + connect \xer_src1__ren \$681 + connect \addr_en_XER_xer_so_shiftrot0_5 \$679 + connect \rp_XER_xer_so_shiftrot0_5 \$677 + connect \pick_XER_xer_so_shiftrot0_5 \$675 + connect \addr_en_XER_xer_so_mul0_4 \$667 + connect \rp_XER_xer_so_mul0_4 \$665 + connect \pick_XER_xer_so_mul0_4 \$663 + connect \addr_en_XER_xer_so_div0_3 \$655 + connect \rp_XER_xer_so_div0_3 \$653 + connect \pick_XER_xer_so_div0_3 \$651 + connect \addr_en_XER_xer_so_spr0_2 \$643 + connect \rp_XER_xer_so_spr0_2 \$641 + connect \pick_XER_xer_so_spr0_2 \$639 + connect \addr_en_XER_xer_so_logical0_1 \$631 + connect \rp_XER_xer_so_logical0_1 \$629 + connect \pick_XER_xer_so_logical0_1 \$627 + connect \addr_en_XER_xer_so_alu0_0 \$619 + connect \rp_XER_xer_so_alu0_0 \$617 + connect \rdpick_XER_xer_so_i [5] \pick_XER_xer_so_shiftrot0_5 + connect \rdpick_XER_xer_so_i [4] \pick_XER_xer_so_mul0_4 + connect \rdpick_XER_xer_so_i [3] \pick_XER_xer_so_div0_3 + connect \rdpick_XER_xer_so_i [2] \pick_XER_xer_so_spr0_2 + connect \rdpick_XER_xer_so_i [1] \pick_XER_xer_so_logical0_1 + connect \rdpick_XER_xer_so_i [0] \pick_XER_xer_so_alu0_0 + connect \pick_XER_xer_so_alu0_0 \$615 + connect \rdflag_XER_xer_so_0 \$607 + connect \int_src3__ren \$595 + connect \int_src3__addr \$593 + connect \addr_en_INT_rc_ldst0_1 \$591 + connect \rp_INT_rc_ldst0_1 \$589 + connect \pick_INT_rc_ldst0_1 \$587 + connect \addr_en_INT_rc_shiftrot0_0 \$579 + connect \rp_INT_rc_shiftrot0_0 \$577 + connect \rdpick_INT_rc_i [1] \pick_INT_rc_ldst0_1 + connect \rdpick_INT_rc_i [0] \pick_INT_rc_shiftrot0_0 + connect \pick_INT_rc_shiftrot0_0 \$575 + connect \rdflag_INT_rc_0 \core_reg3_ok + connect \int_src2__ren \$567 + connect \int_src2__addr \$565 + connect \addr_en_INT_rb_ldst0_7 \$551 + connect \rp_INT_rb_ldst0_7 \$549 + connect \pick_INT_rb_ldst0_7 \$547 + connect \addr_en_INT_rb_shiftrot0_6 \$539 + connect \rp_INT_rb_shiftrot0_6 \$537 + connect \pick_INT_rb_shiftrot0_6 \$535 + connect \addr_en_INT_rb_mul0_5 \$527 + connect \rp_INT_rb_mul0_5 \$525 + connect \pick_INT_rb_mul0_5 \$523 + connect \addr_en_INT_rb_div0_4 \$515 + connect \rp_INT_rb_div0_4 \$513 + connect \pick_INT_rb_div0_4 \$511 + connect \addr_en_INT_rb_logical0_3 \$503 + connect \rp_INT_rb_logical0_3 \$501 + connect \pick_INT_rb_logical0_3 \$499 + connect \addr_en_INT_rb_trap0_2 \$491 + connect \rp_INT_rb_trap0_2 \$489 + connect \pick_INT_rb_trap0_2 \$487 + connect \addr_en_INT_rb_cr0_1 \$479 + connect \rp_INT_rb_cr0_1 \$477 + connect \pick_INT_rb_cr0_1 \$475 + connect \addr_en_INT_rb_alu0_0 \$467 + connect \rp_INT_rb_alu0_0 \$465 + connect \rdpick_INT_rb_i [7] \pick_INT_rb_ldst0_7 + connect \rdpick_INT_rb_i [6] \pick_INT_rb_shiftrot0_6 + connect \rdpick_INT_rb_i [5] \pick_INT_rb_mul0_5 + connect \rdpick_INT_rb_i [4] \pick_INT_rb_div0_4 + connect \rdpick_INT_rb_i [3] \pick_INT_rb_logical0_3 + connect \rdpick_INT_rb_i [2] \pick_INT_rb_trap0_2 + connect \rdpick_INT_rb_i [1] \pick_INT_rb_cr0_1 + connect \rdpick_INT_rb_i [0] \pick_INT_rb_alu0_0 + connect \pick_INT_rb_alu0_0 \$463 + connect \rdflag_INT_rb_0 \core_reg2_ok + connect \int_src1__ren \$455 + connect \int_src1__addr \$453 + connect \addr_en_INT_ra_ldst0_8 \$437 + connect \rp_INT_ra_ldst0_8 \$435 + connect \fus_cu_rd__go_i$53 [2] \dp_INT_rc_ldst0_1 + connect \fus_cu_rd__go_i$53 [1] \dp_INT_rb_ldst0_7 + connect \fus_cu_rd__go_i$53 [0] \dp_INT_ra_ldst0_8 + connect \pick_INT_ra_ldst0_8 \$433 + connect \addr_en_INT_ra_shiftrot0_7 \$425 + connect \rp_INT_ra_shiftrot0_7 \$423 + connect \fus_cu_rd__go_i$50 [4] \dp_XER_xer_ca_shiftrot0_2 + connect \fus_cu_rd__go_i$50 [3] \dp_XER_xer_so_shiftrot0_5 + connect \fus_cu_rd__go_i$50 [2] \dp_INT_rc_shiftrot0_0 + connect \fus_cu_rd__go_i$50 [1] \dp_INT_rb_shiftrot0_6 + connect \fus_cu_rd__go_i$50 [0] \dp_INT_ra_shiftrot0_7 + connect \pick_INT_ra_shiftrot0_7 \$421 + connect \addr_en_INT_ra_mul0_6 \$413 + connect \rp_INT_ra_mul0_6 \$411 + connect \fus_cu_rd__go_i$47 [2] \dp_XER_xer_so_mul0_4 + connect \fus_cu_rd__go_i$47 [1] \dp_INT_rb_mul0_5 + connect \fus_cu_rd__go_i$47 [0] \dp_INT_ra_mul0_6 + connect \pick_INT_ra_mul0_6 \$409 + connect \addr_en_INT_ra_div0_5 \$401 + connect \rp_INT_ra_div0_5 \$399 + connect \fus_cu_rd__go_i$44 [2] \dp_XER_xer_so_div0_3 + connect \fus_cu_rd__go_i$44 [1] \dp_INT_rb_div0_4 + connect \fus_cu_rd__go_i$44 [0] \dp_INT_ra_div0_5 + connect \pick_INT_ra_div0_5 \$397 + connect \addr_en_INT_ra_spr0_4 \$389 + connect \rp_INT_ra_spr0_4 \$387 + connect \fus_cu_rd__go_i$41 [1] \dp_SPR_spr1_spr0_0 + connect \fus_cu_rd__go_i$41 [2] \dp_FAST_fast1_spr0_2 + connect \fus_cu_rd__go_i$41 [4] \dp_XER_xer_ov_spr0_0 + connect \fus_cu_rd__go_i$41 [5] \dp_XER_xer_ca_spr0_1 + connect \fus_cu_rd__go_i$41 [3] \dp_XER_xer_so_spr0_2 + connect \fus_cu_rd__go_i$41 [0] \dp_INT_ra_spr0_4 + connect \pick_INT_ra_spr0_4 \$385 + connect \addr_en_INT_ra_logical0_3 \$377 + connect \rp_INT_ra_logical0_3 \$375 + connect \fus_cu_rd__go_i$38 [2] \dp_XER_xer_so_logical0_1 + connect \fus_cu_rd__go_i$38 [1] \dp_INT_rb_logical0_3 + connect \fus_cu_rd__go_i$38 [0] \dp_INT_ra_logical0_3 + connect \pick_INT_ra_logical0_3 \$373 + connect \addr_en_INT_ra_trap0_2 \$365 + connect \rp_INT_ra_trap0_2 \$363 + connect \fus_cu_rd__go_i$35 [3] \dp_FAST_fast2_trap0_1 + connect \fus_cu_rd__go_i$35 [2] \dp_FAST_fast1_trap0_1 + connect \fus_cu_rd__go_i$35 [1] \dp_INT_rb_trap0_2 + connect \fus_cu_rd__go_i$35 [0] \dp_INT_ra_trap0_2 + connect \pick_INT_ra_trap0_2 \$361 + connect \addr_en_INT_ra_cr0_1 \$353 + connect \rp_INT_ra_cr0_1 \$351 + connect \fus_cu_rd__go_i$32 [5] \dp_CR_cr_c_cr0_0 + connect \fus_cu_rd__go_i$32 [4] \dp_CR_cr_b_cr0_0 + connect \fus_cu_rd__go_i$32 [3] \dp_CR_cr_a_cr0_0 + connect \fus_cu_rd__go_i$32 [2] \dp_CR_full_cr_cr0_0 + connect \fus_cu_rd__go_i$32 [1] \dp_INT_rb_cr0_1 + connect \fus_cu_rd__go_i$32 [0] \dp_INT_ra_cr0_1 + connect \pick_INT_ra_cr0_1 \$349 + connect \addr_en_INT_ra_alu0_0 \$341 + connect \rp_INT_ra_alu0_0 \$339 + connect \fus_cu_rd__go_i [3] \dp_XER_xer_ca_alu0_0 + connect \fus_cu_rd__go_i [2] \dp_XER_xer_so_alu0_0 + connect \fus_cu_rd__go_i [1] \dp_INT_rb_alu0_0 + connect \fus_cu_rd__go_i [0] \dp_INT_ra_alu0_0 + connect \rdpick_INT_ra_i [8] \pick_INT_ra_ldst0_8 + connect \rdpick_INT_ra_i [7] \pick_INT_ra_shiftrot0_7 + connect \rdpick_INT_ra_i [6] \pick_INT_ra_mul0_6 + connect \rdpick_INT_ra_i [5] \pick_INT_ra_div0_5 + connect \rdpick_INT_ra_i [4] \pick_INT_ra_spr0_4 + connect \rdpick_INT_ra_i [3] \pick_INT_ra_logical0_3 + connect \rdpick_INT_ra_i [2] \pick_INT_ra_trap0_2 + connect \rdpick_INT_ra_i [1] \pick_INT_ra_cr0_1 + connect \rdpick_INT_ra_i [0] \pick_INT_ra_alu0_0 + connect \pick_INT_ra_alu0_0 \$337 + connect \rdflag_INT_ra_0 \core_reg1_ok + connect \en_ldst0 \$196 + connect \en_shiftrot0 \$192 + connect \en_mul0 \$188 + connect \en_div0 \$184 + connect \en_spr0 \$180 + connect \en_logical0 \$176 + connect \en_trap0 \$172 + connect \en_branch0 \$168 + connect \en_cr0 \$164 + connect \fu_enable [9] \en_ldst0 + connect \fu_enable [8] \en_shiftrot0 + connect \fu_enable [7] \en_mul0 + connect \fu_enable [6] \en_div0 + connect \fu_enable [5] \en_spr0 + connect \fu_enable [4] \en_logical0 + connect \fu_enable [3] \en_trap0 + connect \fu_enable [2] \en_branch0 + connect \fu_enable [1] \en_cr0 + connect \fu_enable [0] \en_alu0 + connect \en_alu0 \$160 + connect \dec_LDST_bigendian \bigendian_i + connect \dec_LDST_raw_opcode_in \raw_insn_i + connect \dec_SHIFT_ROT_bigendian \bigendian_i + connect \dec_SHIFT_ROT_raw_opcode_in \raw_insn_i + connect \dec_MUL_bigendian \bigendian_i + connect \dec_MUL_raw_opcode_in \raw_insn_i + connect \dec_DIV_bigendian \bigendian_i + connect \dec_DIV_raw_opcode_in \raw_insn_i + connect \dec_SPR_bigendian \bigendian_i + connect \dec_SPR_raw_opcode_in \raw_insn_i + connect \dec_LOGICAL_bigendian \bigendian_i + connect \dec_LOGICAL_raw_opcode_in \raw_insn_i + connect \dec_BRANCH_bigendian \bigendian_i + connect \dec_BRANCH_raw_opcode_in \raw_insn_i + connect \dec_CR_bigendian \bigendian_i + connect \dec_CR_raw_opcode_in \raw_insn_i + connect \dec_ALU_bigendian \bigendian_i + connect \dec_ALU_raw_opcode_in \raw_insn_i +end +attribute \src "issuer_ls180.v:47603.1-48236.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.cr" +attribute \generator "nMigen" +module \cr + attribute \src "issuer_ls180.v:47604.7-47604.20" + wire $0\initial[0:0] + attribute \src "issuer_ls180.v:48150.3-48158.6" + wire width 8 $0\ren_delay$17$next[7:0]$2967 + attribute \src "issuer_ls180.v:47986.3-47987.43" + wire width 8 $0\ren_delay$17[7:0]$2964 + attribute \src "issuer_ls180.v:47932.13-47932.35" + wire width 8 $0\ren_delay$17[7:0]$2981 + attribute \src "issuer_ls180.v:48169.3-48177.6" + wire width 8 $0\ren_delay$34$next[7:0]$2971 + attribute \src "issuer_ls180.v:47984.3-47985.43" + wire width 8 $0\ren_delay$34[7:0]$2962 + attribute \src "issuer_ls180.v:47936.13-47936.35" + wire width 8 $0\ren_delay$34[7:0]$2983 + attribute \src "issuer_ls180.v:48188.3-48196.6" + wire width 8 $0\ren_delay$next[7:0]$2975 + attribute \src "issuer_ls180.v:47988.3-47989.35" + wire width 8 $0\ren_delay[7:0] + attribute \src "issuer_ls180.v:48197.3-48206.6" + wire width 4 $0\src1__data_o[3:0] + attribute \src "issuer_ls180.v:48159.3-48168.6" + wire width 4 $0\src2__data_o[3:0] + attribute \src "issuer_ls180.v:48178.3-48187.6" + wire width 4 $0\src3__data_o[3:0] + attribute \src "issuer_ls180.v:48150.3-48158.6" + wire width 8 $1\ren_delay$17$next[7:0]$2968 + attribute \src "issuer_ls180.v:48169.3-48177.6" + wire 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"/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire \reg_6_src16__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 \reg_6_src26__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire \reg_6_src26__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 \reg_6_src36__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire \reg_6_src36__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 \reg_6_w6__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire \reg_6_w6__wen + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 \reg_7_dest17__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire \reg_7_dest17__wen + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 \reg_7_dest27__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire \reg_7_dest27__wen + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 \reg_7_r27__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire \reg_7_r27__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 \reg_7_r7__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire \reg_7_r7__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 \reg_7_src17__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire \reg_7_src17__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 \reg_7_src27__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire \reg_7_src27__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 \reg_7_src37__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire \reg_7_src37__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 \reg_7_w7__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire \reg_7_w7__wen + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:170" + wire width 8 \ren_delay + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:170" + wire width 8 \ren_delay$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:170" + wire width 8 \ren_delay$17$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:170" + wire width 8 \ren_delay$34 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:170" + wire width 8 \ren_delay$34$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:170" + wire width 8 \ren_delay$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 output 5 \src1__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 8 input 6 \src1__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 output 7 \src2__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 8 input 8 \src2__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 output 9 \src3__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 8 input 10 \src3__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 8 input 14 \wen + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 8 \wen$51 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + cell $or $or$issuer_ls180.v:47960$2937 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \reg_4_src14__data_o + connect \B \reg_5_src15__data_o + connect \Y $or$issuer_ls180.v:47960$2937_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + cell $or $or$issuer_ls180.v:47961$2938 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \reg_6_src16__data_o + connect \B \reg_7_src17__data_o + connect \Y $or$issuer_ls180.v:47961$2938_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" + cell $or $or$issuer_ls180.v:47962$2939 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \$9 + connect \B \$11 + connect \Y $or$issuer_ls180.v:47962$2939_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" + cell $or $or$issuer_ls180.v:47963$2940 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \$7 + connect \B \$13 + connect \Y $or$issuer_ls180.v:47963$2940_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + cell $or $or$issuer_ls180.v:47966$2943 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \reg_0_src20__data_o + connect \B \reg_1_src21__data_o + connect \Y $or$issuer_ls180.v:47966$2943_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + cell $or $or$issuer_ls180.v:47967$2944 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \reg_2_src22__data_o + connect \B \reg_3_src23__data_o + connect \Y $or$issuer_ls180.v:47967$2944_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" + cell $or $or$issuer_ls180.v:47968$2945 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \$20 + connect \B \$22 + connect \Y $or$issuer_ls180.v:47968$2945_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + cell $or $or$issuer_ls180.v:47969$2946 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \reg_4_src24__data_o + connect \B \reg_5_src25__data_o + connect \Y $or$issuer_ls180.v:47969$2946_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + cell $or $or$issuer_ls180.v:47970$2947 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \reg_6_src26__data_o + connect \B \reg_7_src27__data_o + connect \Y $or$issuer_ls180.v:47970$2947_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" + cell $or $or$issuer_ls180.v:47971$2948 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \$26 + connect \B \$28 + connect \Y $or$issuer_ls180.v:47971$2948_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" + cell $or $or$issuer_ls180.v:47972$2949 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \$24 + connect \B \$30 + connect \Y $or$issuer_ls180.v:47972$2949_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + cell $or $or$issuer_ls180.v:47974$2951 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \reg_0_src30__data_o + connect \B \reg_1_src31__data_o + connect \Y $or$issuer_ls180.v:47974$2951_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + cell $or $or$issuer_ls180.v:47975$2952 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \reg_0_src10__data_o + connect \B \reg_1_src11__data_o + connect \Y $or$issuer_ls180.v:47975$2952_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + cell $or $or$issuer_ls180.v:47976$2953 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \reg_2_src32__data_o + connect \B \reg_3_src33__data_o + connect \Y $or$issuer_ls180.v:47976$2953_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" + cell $or $or$issuer_ls180.v:47977$2954 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \$37 + connect \B \$39 + connect \Y $or$issuer_ls180.v:47977$2954_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + cell $or $or$issuer_ls180.v:47978$2955 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \reg_4_src34__data_o + connect \B \reg_5_src35__data_o + connect \Y $or$issuer_ls180.v:47978$2955_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + cell $or $or$issuer_ls180.v:47979$2956 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \reg_6_src36__data_o + connect \B \reg_7_src37__data_o + connect \Y $or$issuer_ls180.v:47979$2956_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" + cell $or $or$issuer_ls180.v:47980$2957 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \$43 + connect \B \$45 + connect \Y $or$issuer_ls180.v:47980$2957_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" + cell $or $or$issuer_ls180.v:47981$2958 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \$41 + connect \B \$47 + connect \Y $or$issuer_ls180.v:47981$2958_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + cell $or $or$issuer_ls180.v:47982$2959 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \reg_2_src12__data_o + connect \B \reg_3_src13__data_o + connect \Y $or$issuer_ls180.v:47982$2959_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" + cell $or $or$issuer_ls180.v:47983$2960 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \$3 + connect \B \$5 + connect \Y $or$issuer_ls180.v:47983$2960_Y + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" + cell $reduce_or $reduce_or$issuer_ls180.v:47964$2941 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \ren_delay$17 + connect \Y $reduce_or$issuer_ls180.v:47964$2941_Y + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" + cell $reduce_or $reduce_or$issuer_ls180.v:47965$2942 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \ren_delay + connect \Y $reduce_or$issuer_ls180.v:47965$2942_Y + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" + cell $reduce_or $reduce_or$issuer_ls180.v:47973$2950 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \ren_delay$34 + connect \Y $reduce_or$issuer_ls180.v:47973$2950_Y + end + attribute \module_not_derived 1 + attribute \src "issuer_ls180.v:47990.9-48009.4" + cell \reg_0 \reg_0 + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \dest10__data_i \reg_0_dest10__data_i + connect \dest10__wen \reg_0_dest10__wen + connect \dest20__data_i \reg_0_dest20__data_i + connect \dest20__wen \reg_0_dest20__wen + connect \r0__data_o \reg_0_r0__data_o + connect \r0__ren \reg_0_r0__ren + connect \r20__data_o \reg_0_r20__data_o + connect \r20__ren \reg_0_r20__ren + connect \src10__data_o \reg_0_src10__data_o + connect \src10__ren \reg_0_src10__ren + connect \src20__data_o \reg_0_src20__data_o + connect \src20__ren \reg_0_src20__ren + connect \src30__data_o \reg_0_src30__data_o + connect \src30__ren \reg_0_src30__ren + connect \w0__data_i \reg_0_w0__data_i + connect \w0__wen \reg_0_w0__wen + end + attribute \module_not_derived 1 + attribute \src "issuer_ls180.v:48010.9-48029.4" + cell \reg_1 \reg_1 + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \dest11__data_i \reg_1_dest11__data_i + connect \dest11__wen \reg_1_dest11__wen + connect \dest21__data_i \reg_1_dest21__data_i + connect \dest21__wen \reg_1_dest21__wen + connect \r1__data_o \reg_1_r1__data_o + connect \r1__ren \reg_1_r1__ren + connect \r21__data_o \reg_1_r21__data_o + connect \r21__ren \reg_1_r21__ren + connect \src11__data_o \reg_1_src11__data_o + connect \src11__ren \reg_1_src11__ren + connect \src21__data_o \reg_1_src21__data_o + connect \src21__ren \reg_1_src21__ren + connect \src31__data_o \reg_1_src31__data_o + connect \src31__ren \reg_1_src31__ren + connect \w1__data_i \reg_1_w1__data_i + connect \w1__wen \reg_1_w1__wen + end + attribute \module_not_derived 1 + attribute \src "issuer_ls180.v:48030.9-48049.4" + cell \reg_2 \reg_2 + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \dest12__data_i \reg_2_dest12__data_i + connect \dest12__wen \reg_2_dest12__wen + connect \dest22__data_i \reg_2_dest22__data_i + connect \dest22__wen \reg_2_dest22__wen + connect \r22__data_o \reg_2_r22__data_o + connect \r22__ren \reg_2_r22__ren + connect \r2__data_o \reg_2_r2__data_o + connect \r2__ren \reg_2_r2__ren + connect \src12__data_o \reg_2_src12__data_o + connect \src12__ren \reg_2_src12__ren + connect \src22__data_o \reg_2_src22__data_o + connect \src22__ren \reg_2_src22__ren + connect \src32__data_o \reg_2_src32__data_o + connect \src32__ren \reg_2_src32__ren + connect \w2__data_i \reg_2_w2__data_i + connect \w2__wen \reg_2_w2__wen + end + attribute \module_not_derived 1 + attribute \src "issuer_ls180.v:48050.9-48069.4" + cell \reg_3 \reg_3 + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \dest13__data_i \reg_3_dest13__data_i + connect \dest13__wen \reg_3_dest13__wen + connect \dest23__data_i \reg_3_dest23__data_i + connect \dest23__wen \reg_3_dest23__wen + connect \r23__data_o \reg_3_r23__data_o + connect \r23__ren \reg_3_r23__ren + connect \r3__data_o \reg_3_r3__data_o + connect \r3__ren \reg_3_r3__ren + connect \src13__data_o \reg_3_src13__data_o + connect \src13__ren \reg_3_src13__ren + connect \src23__data_o \reg_3_src23__data_o + connect \src23__ren \reg_3_src23__ren + connect \src33__data_o \reg_3_src33__data_o + connect \src33__ren \reg_3_src33__ren + connect \w3__data_i \reg_3_w3__data_i + connect \w3__wen \reg_3_w3__wen + end + attribute \module_not_derived 1 + attribute \src "issuer_ls180.v:48070.9-48089.4" + cell \reg_4 \reg_4 + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \dest14__data_i \reg_4_dest14__data_i + connect \dest14__wen \reg_4_dest14__wen + connect \dest24__data_i \reg_4_dest24__data_i + connect \dest24__wen \reg_4_dest24__wen + connect \r24__data_o \reg_4_r24__data_o + connect \r24__ren \reg_4_r24__ren + connect \r4__data_o \reg_4_r4__data_o + connect \r4__ren \reg_4_r4__ren + connect \src14__data_o \reg_4_src14__data_o + connect \src14__ren \reg_4_src14__ren + connect \src24__data_o \reg_4_src24__data_o + connect \src24__ren \reg_4_src24__ren + connect \src34__data_o \reg_4_src34__data_o + connect \src34__ren \reg_4_src34__ren + connect \w4__data_i \reg_4_w4__data_i + connect \w4__wen \reg_4_w4__wen + end + attribute \module_not_derived 1 + attribute \src "issuer_ls180.v:48090.9-48109.4" + cell \reg_5 \reg_5 + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \dest15__data_i \reg_5_dest15__data_i + connect \dest15__wen \reg_5_dest15__wen + connect \dest25__data_i \reg_5_dest25__data_i + connect \dest25__wen \reg_5_dest25__wen + connect \r25__data_o \reg_5_r25__data_o + connect \r25__ren \reg_5_r25__ren + connect \r5__data_o \reg_5_r5__data_o + connect \r5__ren \reg_5_r5__ren + connect \src15__data_o \reg_5_src15__data_o + connect \src15__ren \reg_5_src15__ren + connect \src25__data_o \reg_5_src25__data_o + connect \src25__ren \reg_5_src25__ren + connect \src35__data_o \reg_5_src35__data_o + connect \src35__ren \reg_5_src35__ren + connect \w5__data_i \reg_5_w5__data_i + connect \w5__wen \reg_5_w5__wen + end + attribute \module_not_derived 1 + attribute \src "issuer_ls180.v:48110.9-48129.4" + cell \reg_6 \reg_6 + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \dest16__data_i \reg_6_dest16__data_i + connect \dest16__wen \reg_6_dest16__wen + connect \dest26__data_i \reg_6_dest26__data_i + connect \dest26__wen \reg_6_dest26__wen + connect \r26__data_o \reg_6_r26__data_o + connect \r26__ren \reg_6_r26__ren + connect \r6__data_o \reg_6_r6__data_o + connect \r6__ren \reg_6_r6__ren + connect \src16__data_o \reg_6_src16__data_o + connect \src16__ren \reg_6_src16__ren + connect \src26__data_o \reg_6_src26__data_o + connect \src26__ren \reg_6_src26__ren + connect \src36__data_o \reg_6_src36__data_o + connect \src36__ren \reg_6_src36__ren + connect \w6__data_i \reg_6_w6__data_i + connect \w6__wen \reg_6_w6__wen + end + attribute \module_not_derived 1 + attribute \src "issuer_ls180.v:48130.9-48149.4" + cell \reg_7 \reg_7 + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \dest17__data_i \reg_7_dest17__data_i + connect \dest17__wen \reg_7_dest17__wen + connect \dest27__data_i \reg_7_dest27__data_i + connect \dest27__wen \reg_7_dest27__wen + connect \r27__data_o \reg_7_r27__data_o + connect \r27__ren \reg_7_r27__ren + connect \r7__data_o \reg_7_r7__data_o + connect \r7__ren \reg_7_r7__ren + connect \src17__data_o \reg_7_src17__data_o + connect \src17__ren \reg_7_src17__ren + connect \src27__data_o \reg_7_src27__data_o + connect \src27__ren \reg_7_src27__ren + connect \src37__data_o \reg_7_src37__data_o + connect \src37__ren \reg_7_src37__ren + connect \w7__data_i \reg_7_w7__data_i + connect \w7__wen \reg_7_w7__wen + end + attribute \src "issuer_ls180.v:47604.7-47604.20" + process $proc$issuer_ls180.v:47604$2978 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "issuer_ls180.v:47930.13-47930.30" + process $proc$issuer_ls180.v:47930$2979 + assign { } { } + assign $1\ren_delay[7:0] 8'00000000 + sync always + sync init + update \ren_delay $1\ren_delay[7:0] + end + attribute \src "issuer_ls180.v:47932.13-47932.35" + process $proc$issuer_ls180.v:47932$2980 + assign { } { } + assign $0\ren_delay$17[7:0]$2981 8'00000000 + sync always + sync init + update \ren_delay$17 $0\ren_delay$17[7:0]$2981 + end + attribute \src "issuer_ls180.v:47936.13-47936.35" + process $proc$issuer_ls180.v:47936$2982 + assign { } { } + assign $0\ren_delay$34[7:0]$2983 8'00000000 + sync always + sync init + update \ren_delay$34 $0\ren_delay$34[7:0]$2983 + end + attribute \src "issuer_ls180.v:47984.3-47985.43" + process $proc$issuer_ls180.v:47984$2961 + assign { } { } + assign $0\ren_delay$34[7:0]$2962 \ren_delay$34$next + sync posedge \coresync_clk + update \ren_delay$34 $0\ren_delay$34[7:0]$2962 + end + attribute \src "issuer_ls180.v:47986.3-47987.43" + process $proc$issuer_ls180.v:47986$2963 + assign { } { } + assign $0\ren_delay$17[7:0]$2964 \ren_delay$17$next + sync posedge \coresync_clk + update \ren_delay$17 $0\ren_delay$17[7:0]$2964 + end + attribute \src "issuer_ls180.v:47988.3-47989.35" + process $proc$issuer_ls180.v:47988$2965 + assign { } { } + assign $0\ren_delay[7:0] \ren_delay$next + sync posedge \coresync_clk + update \ren_delay $0\ren_delay[7:0] + end + attribute \src "issuer_ls180.v:48150.3-48158.6" + process $proc$issuer_ls180.v:48150$2966 + assign { } { } + assign { } { } + assign $0\ren_delay$17$next[7:0]$2967 $1\ren_delay$17$next[7:0]$2968 + attribute \src "issuer_ls180.v:48151.5-48151.29" + switch \initial + attribute \src "issuer_ls180.v:48151.9-48151.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\ren_delay$17$next[7:0]$2968 8'00000000 + case + assign $1\ren_delay$17$next[7:0]$2968 \src2__ren + end + sync always + update \ren_delay$17$next $0\ren_delay$17$next[7:0]$2967 + end + attribute \src "issuer_ls180.v:48159.3-48168.6" + process $proc$issuer_ls180.v:48159$2969 + assign { } { } + assign { } { } + assign $0\src2__data_o[3:0] $1\src2__data_o[3:0] + attribute \src "issuer_ls180.v:48160.5-48160.29" + switch \initial + attribute \src "issuer_ls180.v:48160.9-48160.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:172" + switch \$18 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\src2__data_o[3:0] \$32 + case + assign $1\src2__data_o[3:0] 4'0000 + end + sync always + update \src2__data_o $0\src2__data_o[3:0] + end + attribute \src "issuer_ls180.v:48169.3-48177.6" + process $proc$issuer_ls180.v:48169$2970 + assign { } { } + assign { } { } + assign $0\ren_delay$34$next[7:0]$2971 $1\ren_delay$34$next[7:0]$2972 + attribute \src "issuer_ls180.v:48170.5-48170.29" + switch \initial + attribute \src "issuer_ls180.v:48170.9-48170.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\ren_delay$34$next[7:0]$2972 8'00000000 + case + assign $1\ren_delay$34$next[7:0]$2972 \src3__ren + end + sync always + update \ren_delay$34$next $0\ren_delay$34$next[7:0]$2971 + end + attribute \src "issuer_ls180.v:48178.3-48187.6" + process $proc$issuer_ls180.v:48178$2973 + assign { } { } + assign { } { } + assign $0\src3__data_o[3:0] $1\src3__data_o[3:0] + attribute \src "issuer_ls180.v:48179.5-48179.29" + switch \initial + attribute \src "issuer_ls180.v:48179.9-48179.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:172" + switch \$35 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\src3__data_o[3:0] \$49 + case + assign $1\src3__data_o[3:0] 4'0000 + end + sync always + update \src3__data_o $0\src3__data_o[3:0] + end + attribute \src "issuer_ls180.v:48188.3-48196.6" + process $proc$issuer_ls180.v:48188$2974 + assign { } { } + assign { } { } + assign $0\ren_delay$next[7:0]$2975 $1\ren_delay$next[7:0]$2976 + attribute \src "issuer_ls180.v:48189.5-48189.29" + switch \initial + attribute \src "issuer_ls180.v:48189.9-48189.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\ren_delay$next[7:0]$2976 8'00000000 + case + assign $1\ren_delay$next[7:0]$2976 \src1__ren + end + sync always + update \ren_delay$next $0\ren_delay$next[7:0]$2975 + end + attribute \src "issuer_ls180.v:48197.3-48206.6" + process $proc$issuer_ls180.v:48197$2977 + assign { } { } + assign { } { } + assign $0\src1__data_o[3:0] $1\src1__data_o[3:0] + attribute \src "issuer_ls180.v:48198.5-48198.29" + switch \initial + attribute \src "issuer_ls180.v:48198.9-48198.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:172" + switch \$1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\src1__data_o[3:0] \$15 + case + assign $1\src1__data_o[3:0] 4'0000 + end + sync always + update \src1__data_o $0\src1__data_o[3:0] + end + connect \$9 $or$issuer_ls180.v:47960$2937_Y + connect \$11 $or$issuer_ls180.v:47961$2938_Y + connect \$13 $or$issuer_ls180.v:47962$2939_Y + connect \$15 $or$issuer_ls180.v:47963$2940_Y + connect \$18 $reduce_or$issuer_ls180.v:47964$2941_Y + connect \$1 $reduce_or$issuer_ls180.v:47965$2942_Y + connect \$20 $or$issuer_ls180.v:47966$2943_Y + connect \$22 $or$issuer_ls180.v:47967$2944_Y + connect \$24 $or$issuer_ls180.v:47968$2945_Y + connect \$26 $or$issuer_ls180.v:47969$2946_Y + connect \$28 $or$issuer_ls180.v:47970$2947_Y + connect \$30 $or$issuer_ls180.v:47971$2948_Y + connect \$32 $or$issuer_ls180.v:47972$2949_Y + connect \$35 $reduce_or$issuer_ls180.v:47973$2950_Y + connect \$37 $or$issuer_ls180.v:47974$2951_Y + connect \$3 $or$issuer_ls180.v:47975$2952_Y + connect \$39 $or$issuer_ls180.v:47976$2953_Y + connect \$41 $or$issuer_ls180.v:47977$2954_Y + connect \$43 $or$issuer_ls180.v:47978$2955_Y + connect \$45 $or$issuer_ls180.v:47979$2956_Y + connect \$47 $or$issuer_ls180.v:47980$2957_Y + connect \$49 $or$issuer_ls180.v:47981$2958_Y + connect \$5 $or$issuer_ls180.v:47982$2959_Y + connect \$7 $or$issuer_ls180.v:47983$2960_Y + connect \wen$51 8'00000000 + connect \data_i$52 4'0000 + connect { \reg_7_w7__wen \reg_6_w6__wen \reg_5_w5__wen \reg_4_w4__wen \reg_3_w3__wen \reg_2_w2__wen \reg_1_w1__wen \reg_0_w0__wen } \full_wr__wen + connect { \reg_7_w7__data_i \reg_6_w6__data_i \reg_5_w5__data_i \reg_4_w4__data_i \reg_3_w3__data_i \reg_2_w2__data_i \reg_1_w1__data_i \reg_0_w0__data_i } \full_wr__data_i + connect { \reg_7_r27__ren \reg_6_r26__ren \reg_5_r25__ren \reg_4_r24__ren \reg_3_r23__ren \reg_2_r22__ren \reg_1_r21__ren \reg_0_r20__ren } \full_rd2__ren + connect \full_rd2__data_o { \reg_7_r27__data_o \reg_6_r26__data_o \reg_5_r25__data_o \reg_4_r24__data_o \reg_3_r23__data_o \reg_2_r22__data_o \reg_1_r21__data_o \reg_0_r20__data_o } + connect { \reg_7_r7__ren \reg_6_r6__ren \reg_5_r5__ren \reg_4_r4__ren \reg_3_r3__ren \reg_2_r2__ren \reg_1_r1__ren \reg_0_r0__ren } \full_rd__ren + connect \full_rd__data_o { \reg_7_r7__data_o \reg_6_r6__data_o \reg_5_r5__data_o \reg_4_r4__data_o \reg_3_r3__data_o \reg_2_r2__data_o \reg_1_r1__data_o \reg_0_r0__data_o } + connect \reg_7_dest27__data_i 4'0000 + connect \reg_6_dest26__data_i 4'0000 + connect \reg_5_dest25__data_i 4'0000 + connect \reg_4_dest24__data_i 4'0000 + connect \reg_3_dest23__data_i 4'0000 + connect \reg_2_dest22__data_i 4'0000 + connect \reg_1_dest21__data_i 4'0000 + connect \reg_0_dest20__data_i 4'0000 + connect { \reg_7_dest27__wen \reg_6_dest26__wen \reg_5_dest25__wen \reg_4_dest24__wen \reg_3_dest23__wen \reg_2_dest22__wen \reg_1_dest21__wen \reg_0_dest20__wen } 8'00000000 + connect \reg_7_dest17__data_i \data_i + connect \reg_6_dest16__data_i \data_i + connect \reg_5_dest15__data_i \data_i + connect \reg_4_dest14__data_i \data_i + connect \reg_3_dest13__data_i \data_i + connect \reg_2_dest12__data_i \data_i + connect \reg_1_dest11__data_i \data_i + connect \reg_0_dest10__data_i \data_i + connect { \reg_7_dest17__wen \reg_6_dest16__wen \reg_5_dest15__wen \reg_4_dest14__wen \reg_3_dest13__wen \reg_2_dest12__wen \reg_1_dest11__wen \reg_0_dest10__wen } \wen + connect { \reg_7_src37__ren \reg_6_src36__ren \reg_5_src35__ren \reg_4_src34__ren \reg_3_src33__ren \reg_2_src32__ren \reg_1_src31__ren \reg_0_src30__ren } \src3__ren + connect { \reg_7_src27__ren \reg_6_src26__ren \reg_5_src25__ren \reg_4_src24__ren \reg_3_src23__ren \reg_2_src22__ren \reg_1_src21__ren \reg_0_src20__ren } \src2__ren + connect { \reg_7_src17__ren \reg_6_src16__ren \reg_5_src15__ren \reg_4_src14__ren \reg_3_src13__ren \reg_2_src12__ren \reg_1_src11__ren \reg_0_src10__ren } \src1__ren +end +attribute \src "issuer_ls180.v:48240.1-49291.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.fus.cr0" +attribute \generator "nMigen" +module \cr0 + attribute \src "issuer_ls180.v:48868.3-48869.25" + wire $0\all_rd_dly[0:0] + attribute \src "issuer_ls180.v:49065.3-49076.6" + wire width 12 $0\alu_cr0_cr_op__fn_unit$next[11:0]$3103 + attribute \src "issuer_ls180.v:48840.3-48841.61" + wire width 12 $0\alu_cr0_cr_op__fn_unit[11:0] + attribute \src "issuer_ls180.v:49065.3-49076.6" + wire width 32 $0\alu_cr0_cr_op__insn$next[31:0]$3104 + attribute \src "issuer_ls180.v:48842.3-48843.55" + wire width 32 $0\alu_cr0_cr_op__insn[31:0] + attribute \src "issuer_ls180.v:49065.3-49076.6" + wire width 7 $0\alu_cr0_cr_op__insn_type$next[6:0]$3105 + attribute \src "issuer_ls180.v:48838.3-48839.65" + wire width 7 $0\alu_cr0_cr_op__insn_type[6:0] + attribute \src "issuer_ls180.v:48866.3-48867.39" + wire $0\alu_done_dly[0:0] + attribute \src "issuer_ls180.v:49212.3-49220.6" + wire $0\alu_l_r_alu$next[0:0]$3155 + attribute \src "issuer_ls180.v:48870.3-48871.39" + wire $0\alu_l_r_alu[0:0] + attribute \src "issuer_ls180.v:49203.3-49211.6" + wire $0\alui_l_r_alui$next[0:0]$3152 + attribute \src "issuer_ls180.v:48872.3-48873.43" + wire $0\alui_l_r_alui[0:0] + attribute \src "issuer_ls180.v:49077.3-49098.6" + wire width 64 $0\data_r0__o$next[63:0]$3110 + attribute \src "issuer_ls180.v:48834.3-48835.37" + wire width 64 $0\data_r0__o[63:0] + attribute \src "issuer_ls180.v:49077.3-49098.6" + wire $0\data_r0__o_ok$next[0:0]$3111 + attribute \src "issuer_ls180.v:48836.3-48837.43" + wire $0\data_r0__o_ok[0:0] + attribute \src "issuer_ls180.v:49099.3-49120.6" + wire width 32 $0\data_r1__full_cr$next[31:0]$3118 + attribute \src "issuer_ls180.v:48890.3-48891.49" + wire width 32 $0\data_r1__full_cr[31:0] + attribute \src "issuer_ls180.v:49099.3-49120.6" + wire $0\data_r1__full_cr_ok$next[0:0]$3119 + attribute \src "issuer_ls180.v:48892.3-48893.55" + wire $0\data_r1__full_cr_ok[0:0] + attribute \src "issuer_ls180.v:49121.3-49142.6" + wire width 4 $0\data_r2__cr_a$next[3:0]$3126 + attribute \src "issuer_ls180.v:48886.3-48887.43" + wire width 4 $0\data_r2__cr_a[3:0] + attribute \src "issuer_ls180.v:49121.3-49142.6" + wire $0\data_r2__cr_a_ok$next[0:0]$3127 + attribute \src "issuer_ls180.v:48888.3-48889.49" + wire $0\data_r2__cr_a_ok[0:0] + attribute \src "issuer_ls180.v:49221.3-49230.6" + wire width 64 $0\dest1_o[63:0] + attribute \src "issuer_ls180.v:49231.3-49240.6" + wire width 32 $0\dest2_o[31:0] + attribute \src "issuer_ls180.v:49241.3-49250.6" + wire width 4 $0\dest3_o[3:0] + attribute \src "issuer_ls180.v:48241.7-48241.20" + wire $0\initial[0:0] + attribute \src "issuer_ls180.v:49020.3-49028.6" + wire $0\opc_l_r_opc$next[0:0]$3088 + attribute \src "issuer_ls180.v:48852.3-48853.39" + wire $0\opc_l_r_opc[0:0] + attribute \src "issuer_ls180.v:49011.3-49019.6" + wire $0\opc_l_s_opc$next[0:0]$3085 + attribute \src "issuer_ls180.v:48854.3-48855.39" + wire $0\opc_l_s_opc[0:0] + attribute \src "issuer_ls180.v:49251.3-49259.6" + wire width 3 $0\prev_wr_go$next[2:0]$3161 + attribute \src "issuer_ls180.v:48864.3-48865.37" + wire width 3 $0\prev_wr_go[2:0] + attribute \src "issuer_ls180.v:48965.3-48974.6" + wire $0\req_done[0:0] + attribute \src "issuer_ls180.v:49056.3-49064.6" + wire width 3 $0\req_l_r_req$next[2:0]$3100 + attribute \src "issuer_ls180.v:48844.3-48845.39" + wire width 3 $0\req_l_r_req[2:0] + attribute \src "issuer_ls180.v:49047.3-49055.6" + wire width 3 $0\req_l_s_req$next[2:0]$3097 + attribute \src "issuer_ls180.v:48846.3-48847.39" + wire width 3 $0\req_l_s_req[2:0] + attribute \src "issuer_ls180.v:48984.3-48992.6" + wire $0\rok_l_r_rdok$next[0:0]$3076 + attribute \src "issuer_ls180.v:48860.3-48861.41" + wire $0\rok_l_r_rdok[0:0] + attribute \src "issuer_ls180.v:48975.3-48983.6" + wire $0\rok_l_s_rdok$next[0:0]$3073 + attribute \src "issuer_ls180.v:48862.3-48863.41" + wire $0\rok_l_s_rdok[0:0] + attribute \src "issuer_ls180.v:49002.3-49010.6" + wire $0\rst_l_r_rst$next[0:0]$3082 + attribute \src "issuer_ls180.v:48856.3-48857.39" + wire $0\rst_l_r_rst[0:0] + attribute \src "issuer_ls180.v:48993.3-49001.6" + wire $0\rst_l_s_rst$next[0:0]$3079 + attribute \src "issuer_ls180.v:48858.3-48859.39" + wire $0\rst_l_s_rst[0:0] + attribute \src "issuer_ls180.v:49038.3-49046.6" + wire width 6 $0\src_l_r_src$next[5:0]$3094 + attribute \src "issuer_ls180.v:48848.3-48849.39" + wire width 6 $0\src_l_r_src[5:0] + attribute \src "issuer_ls180.v:49029.3-49037.6" + wire width 6 $0\src_l_s_src$next[5:0]$3091 + attribute \src "issuer_ls180.v:48850.3-48851.39" + wire width 6 $0\src_l_s_src[5:0] + attribute \src "issuer_ls180.v:49143.3-49152.6" + wire width 64 $0\src_r0$next[63:0]$3134 + attribute \src "issuer_ls180.v:48884.3-48885.29" + wire width 64 $0\src_r0[63:0] + attribute \src "issuer_ls180.v:49153.3-49162.6" + wire width 64 $0\src_r1$next[63:0]$3137 + attribute \src "issuer_ls180.v:48882.3-48883.29" + wire width 64 $0\src_r1[63:0] + attribute \src "issuer_ls180.v:49163.3-49172.6" + wire width 32 $0\src_r2$next[31:0]$3140 + attribute \src "issuer_ls180.v:48880.3-48881.29" + wire width 32 $0\src_r2[31:0] + attribute \src "issuer_ls180.v:49173.3-49182.6" + wire width 4 $0\src_r3$next[3:0]$3143 + attribute \src "issuer_ls180.v:48878.3-48879.29" + wire width 4 $0\src_r3[3:0] + attribute \src "issuer_ls180.v:49183.3-49192.6" + wire width 4 $0\src_r4$next[3:0]$3146 + attribute \src "issuer_ls180.v:48876.3-48877.29" + wire width 4 $0\src_r4[3:0] + attribute \src "issuer_ls180.v:49193.3-49202.6" + wire width 4 $0\src_r5$next[3:0]$3149 + attribute \src "issuer_ls180.v:48874.3-48875.29" + wire width 4 $0\src_r5[3:0] + attribute \src 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\A \cu_busy_o + connect \B \cu_shadown_i + connect \Y $and$issuer_ls180.v:48779$2986_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" + cell $and $and$issuer_ls180.v:48780$2987 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cu_busy_o + connect \B \cu_shadown_i + connect \Y $and$issuer_ls180.v:48780$2987_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" + cell $and $and$issuer_ls180.v:48781$2988 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cu_busy_o + connect \B \cu_shadown_i + connect \Y $and$issuer_ls180.v:48781$2988_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351" + cell $and $and$issuer_ls180.v:48782$2989 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + 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connect \B \$45 + connect \Y $and$issuer_ls180.v:48806$3013_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" + cell $and $and$issuer_ls180.v:48808$3015 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$49 + connect \B \alu_cr0_n_ready_i + connect \Y $and$issuer_ls180.v:48808$3015_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" + cell $and $and$issuer_ls180.v:48809$3016 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$51 + connect \B \alu_cr0_n_valid_o + connect \Y $and$issuer_ls180.v:48809$3016_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" + cell $and $and$issuer_ls180.v:48810$3017 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + 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parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \o_ok + connect \B \cu_busy_o + connect \Y $and$issuer_ls180.v:48819$3026_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" + cell $and $and$issuer_ls180.v:48820$3027 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \full_cr_ok + connect \B \cu_busy_o + connect \Y $and$issuer_ls180.v:48820$3027_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" + cell $and $and$issuer_ls180.v:48821$3028 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cr_a_ok + connect \B \cu_busy_o + connect \Y $and$issuer_ls180.v:48821$3028_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:327" + cell $and $and$issuer_ls180.v:48829$3036 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \alu_cr0_p_ready_o + connect \B \alui_l_q_alui + connect \Y $and$issuer_ls180.v:48829$3036_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:334" + cell $and $and$issuer_ls180.v:48830$3037 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \alu_cr0_n_valid_o + connect \B \alu_l_q_alu + connect \Y $and$issuer_ls180.v:48830$3037_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" + cell $and $and$issuer_ls180.v:48831$3038 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 6 + connect \A \src_l_q_src + connect \B { \cu_busy_o \cu_busy_o \cu_busy_o \cu_busy_o \cu_busy_o \cu_busy_o } + connect \Y $and$issuer_ls180.v:48831$3038_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" + cell $and $and$issuer_ls180.v:48832$3039 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 6 + connect \A \$93 + connect \B 6'111111 + connect \Y $and$issuer_ls180.v:48832$3039_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" + cell $eq $eq$issuer_ls180.v:48805$3012 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$43 + connect \B 1'0 + connect \Y $eq$issuer_ls180.v:48805$3012_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" + cell $eq $eq$issuer_ls180.v:48807$3014 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cu_wrmask_o + connect \B 1'0 + connect \Y $eq$issuer_ls180.v:48807$3014_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + cell $not $not$issuer_ls180.v:48788$2995 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \all_rd_dly + connect \Y $not$issuer_ls180.v:48788$2995_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + cell $not $not$issuer_ls180.v:48790$2997 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \alu_done_dly + connect \Y $not$issuer_ls180.v:48790$2997_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" + cell $not $not$issuer_ls180.v:48793$3000 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \cu_wrmask_o + connect \Y $not$issuer_ls180.v:48793$3000_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" + cell $not $not$issuer_ls180.v:48796$3003 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$24 + connect \Y $not$issuer_ls180.v:48796$3003_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" + cell $not $not$issuer_ls180.v:48802$3009 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \alu_cr0_n_ready_i + connect \Y $not$issuer_ls180.v:48802$3009_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" + cell $not $not$issuer_ls180.v:48817$3024 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \Y_WIDTH 6 + connect \A \cu_rd__rel_o + connect \Y $not$issuer_ls180.v:48817$3024_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" + cell $not $not$issuer_ls180.v:48833$3040 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \Y_WIDTH 6 + connect \A \cu_rdmaskn_i + connect \Y $not$issuer_ls180.v:48833$3040_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" + cell $or $or$issuer_ls180.v:48800$3007 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$33 + connect \B \$35 + connect \Y $or$issuer_ls180.v:48800$3007_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:230" + cell $or $or$issuer_ls180.v:48811$3018 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \req_done + connect \B \cu_go_die_i + connect \Y $or$issuer_ls180.v:48811$3018_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:231" + cell $or $or$issuer_ls180.v:48812$3019 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cu_issue_i + connect \B \cu_go_die_i + connect \Y $or$issuer_ls180.v:48812$3019_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:232" + cell $or $or$issuer_ls180.v:48813$3020 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \cu_wr__go_i + connect \B { \cu_go_die_i \cu_go_die_i \cu_go_die_i } + connect \Y $or$issuer_ls180.v:48813$3020_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:233" + cell $or $or$issuer_ls180.v:48814$3021 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 6 + connect \A \cu_rd__go_i + connect \B { \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i } + connect \Y $or$issuer_ls180.v:48814$3021_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:253" + cell $or $or$issuer_ls180.v:48818$3025 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \reset_w + connect \B \prev_wr_go + connect \Y $or$issuer_ls180.v:48818$3025_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" + cell $or $or$issuer_ls180.v:48828$3035 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 6 + connect \A \$6 + connect \B \cu_rd__go_i + connect \Y $or$issuer_ls180.v:48828$3035_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" + cell $reduce_and $reduce_and$issuer_ls180.v:48777$2984 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \$8 + connect \Y $reduce_and$issuer_ls180.v:48777$2984_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" + cell $reduce_or $reduce_or$issuer_ls180.v:48795$3002 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \$27 + connect \Y $reduce_or$issuer_ls180.v:48795$3002_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" + cell $reduce_or $reduce_or$issuer_ls180.v:48798$3005 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \cu_wr__go_i + connect \Y $reduce_or$issuer_ls180.v:48798$3005_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" + cell $reduce_or $reduce_or$issuer_ls180.v:48799$3006 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \prev_wr_go + connect \Y $reduce_or$issuer_ls180.v:48799$3006_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + cell $mux $ternary$issuer_ls180.v:48822$3029 + parameter \WIDTH 64 + connect \A \src_r0 + connect \B \src1_i + connect \S \src_l_q_src [0] + connect \Y $ternary$issuer_ls180.v:48822$3029_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + cell $mux $ternary$issuer_ls180.v:48823$3030 + parameter \WIDTH 64 + connect \A \src_r1 + connect \B \src2_i + connect \S \src_l_q_src [1] + connect \Y $ternary$issuer_ls180.v:48823$3030_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + cell $mux $ternary$issuer_ls180.v:48824$3031 + parameter \WIDTH 32 + connect \A \src_r2 + connect \B \src3_i + connect \S \src_l_q_src [2] + connect \Y $ternary$issuer_ls180.v:48824$3031_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + cell $mux $ternary$issuer_ls180.v:48825$3032 + parameter \WIDTH 4 + connect \A \src_r3 + connect \B \src4_i + connect \S \src_l_q_src [3] + connect \Y $ternary$issuer_ls180.v:48825$3032_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + cell $mux $ternary$issuer_ls180.v:48826$3033 + parameter \WIDTH 4 + connect \A \src_r4 + connect \B \src5_i + connect \S \src_l_q_src [4] + connect \Y $ternary$issuer_ls180.v:48826$3033_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + cell $mux $ternary$issuer_ls180.v:48827$3034 + parameter \WIDTH 4 + connect \A \src_r5 + connect \B \src6_i + connect \S \src_l_q_src [5] + connect \Y $ternary$issuer_ls180.v:48827$3034_Y + end + attribute \module_not_derived 1 + attribute \src "issuer_ls180.v:48894.11-48916.4" + cell \alu_cr0 \alu_cr0 + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \cr_a \alu_cr0_cr_a + connect \cr_a$2 \alu_cr0_cr_a$2 + connect \cr_a_ok \cr_a_ok + connect \cr_b \alu_cr0_cr_b + connect \cr_c \alu_cr0_cr_c + connect \cr_op__fn_unit \alu_cr0_cr_op__fn_unit + connect \cr_op__insn \alu_cr0_cr_op__insn + connect \cr_op__insn_type \alu_cr0_cr_op__insn_type + connect \full_cr \alu_cr0_full_cr + connect \full_cr$1 \alu_cr0_full_cr$1 + connect \full_cr_ok \full_cr_ok + connect \n_ready_i \alu_cr0_n_ready_i + connect \n_valid_o \alu_cr0_n_valid_o + connect \o \alu_cr0_o + connect \o_ok \o_ok + connect \p_ready_o \alu_cr0_p_ready_o + connect \p_valid_i \alu_cr0_p_valid_i + connect \ra \alu_cr0_ra + connect \rb \alu_cr0_rb + end + attribute \module_not_derived 1 + attribute \src "issuer_ls180.v:48917.14-48923.4" + cell \alu_l$16 \alu_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_alu \alu_l_q_alu + connect \r_alu \alu_l_r_alu + connect \s_alu \alu_l_s_alu + end + attribute \module_not_derived 1 + attribute \src "issuer_ls180.v:48924.15-48930.4" + cell \alui_l$15 \alui_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_alui \alui_l_q_alui + connect \r_alui \alui_l_r_alui + connect \s_alui \alui_l_s_alui + end + attribute \module_not_derived 1 + attribute \src "issuer_ls180.v:48931.14-48937.4" + cell \opc_l$11 \opc_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_opc \opc_l_q_opc + connect \r_opc \opc_l_r_opc + connect \s_opc \opc_l_s_opc + end + attribute \module_not_derived 1 + attribute \src "issuer_ls180.v:48938.14-48944.4" + cell \req_l$12 \req_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_req \req_l_q_req + connect \r_req \req_l_r_req + connect \s_req \req_l_s_req + end + attribute \module_not_derived 1 + attribute \src "issuer_ls180.v:48945.14-48951.4" + cell \rok_l$14 \rok_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_rdok \rok_l_q_rdok + connect \r_rdok \rok_l_r_rdok + connect \s_rdok \rok_l_s_rdok + end + attribute \module_not_derived 1 + attribute \src "issuer_ls180.v:48952.14-48957.4" + cell \rst_l$13 \rst_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \r_rst \rst_l_r_rst + connect \s_rst \rst_l_s_rst + end + attribute \module_not_derived 1 + attribute \src "issuer_ls180.v:48958.14-48964.4" + cell \src_l$10 \src_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_src \src_l_q_src + connect \r_src \src_l_r_src + connect \s_src \src_l_s_src + end + attribute \src "issuer_ls180.v:48241.7-48241.20" + process $proc$issuer_ls180.v:48241$3163 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "issuer_ls180.v:48359.7-48359.24" + process $proc$issuer_ls180.v:48359$3164 + assign { } { } + assign $1\all_rd_dly[0:0] 1'0 + sync always + sync init + update \all_rd_dly $1\all_rd_dly[0:0] + end + attribute \src "issuer_ls180.v:48388.14-48388.46" + process $proc$issuer_ls180.v:48388$3165 + assign { } { } + assign $1\alu_cr0_cr_op__fn_unit[11:0] 12'000000000000 + sync always + sync init + update \alu_cr0_cr_op__fn_unit $1\alu_cr0_cr_op__fn_unit[11:0] + end + attribute \src "issuer_ls180.v:48392.14-48392.41" + process $proc$issuer_ls180.v:48392$3166 + assign { } { } + assign $1\alu_cr0_cr_op__insn[31:0] 0 + sync always + sync init + update \alu_cr0_cr_op__insn $1\alu_cr0_cr_op__insn[31:0] + end + attribute \src "issuer_ls180.v:48470.13-48470.45" + process $proc$issuer_ls180.v:48470$3167 + assign { } { } + assign $1\alu_cr0_cr_op__insn_type[6:0] 7'0000000 + sync always + sync init + update \alu_cr0_cr_op__insn_type $1\alu_cr0_cr_op__insn_type[6:0] + end + attribute \src "issuer_ls180.v:48494.7-48494.26" + process $proc$issuer_ls180.v:48494$3168 + assign { } { } + assign $1\alu_done_dly[0:0] 1'0 + sync always + sync init + update \alu_done_dly $1\alu_done_dly[0:0] + end + attribute \src "issuer_ls180.v:48502.7-48502.25" + process $proc$issuer_ls180.v:48502$3169 + assign { } { } + assign $1\alu_l_r_alu[0:0] 1'1 + sync always + sync init + update \alu_l_r_alu $1\alu_l_r_alu[0:0] + end + attribute \src "issuer_ls180.v:48514.7-48514.27" + process $proc$issuer_ls180.v:48514$3170 + assign { } { } + assign $1\alui_l_r_alui[0:0] 1'1 + sync always + sync init + update \alui_l_r_alui $1\alui_l_r_alui[0:0] + end + attribute \src "issuer_ls180.v:48548.14-48548.47" + process $proc$issuer_ls180.v:48548$3171 + assign { } { } + assign $1\data_r0__o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \data_r0__o $1\data_r0__o[63:0] + end + attribute \src "issuer_ls180.v:48552.7-48552.27" + process $proc$issuer_ls180.v:48552$3172 + assign { } { } + assign $1\data_r0__o_ok[0:0] 1'0 + sync always + sync init + update \data_r0__o_ok $1\data_r0__o_ok[0:0] + end + attribute \src "issuer_ls180.v:48556.14-48556.38" + process $proc$issuer_ls180.v:48556$3173 + assign { } { } + assign $1\data_r1__full_cr[31:0] 0 + sync always + sync init + update \data_r1__full_cr $1\data_r1__full_cr[31:0] + end + attribute \src "issuer_ls180.v:48560.7-48560.33" + process $proc$issuer_ls180.v:48560$3174 + assign { } { } + assign $1\data_r1__full_cr_ok[0:0] 1'0 + sync always + sync init + update \data_r1__full_cr_ok $1\data_r1__full_cr_ok[0:0] + end + attribute \src "issuer_ls180.v:48564.13-48564.33" + process $proc$issuer_ls180.v:48564$3175 + assign { } { } + assign $1\data_r2__cr_a[3:0] 4'0000 + sync always + sync init + update \data_r2__cr_a $1\data_r2__cr_a[3:0] + end + attribute \src "issuer_ls180.v:48568.7-48568.30" + process $proc$issuer_ls180.v:48568$3176 + assign { } { } + assign $1\data_r2__cr_a_ok[0:0] 1'0 + sync always + sync init + update \data_r2__cr_a_ok $1\data_r2__cr_a_ok[0:0] + end + attribute \src "issuer_ls180.v:48587.7-48587.25" + process $proc$issuer_ls180.v:48587$3177 + assign { } { } + assign $1\opc_l_r_opc[0:0] 1'1 + sync always + sync init + update \opc_l_r_opc $1\opc_l_r_opc[0:0] + end + attribute \src "issuer_ls180.v:48591.7-48591.25" + process $proc$issuer_ls180.v:48591$3178 + assign { } { } + assign $1\opc_l_s_opc[0:0] 1'0 + sync always + sync init + update \opc_l_s_opc $1\opc_l_s_opc[0:0] + end + attribute \src "issuer_ls180.v:48688.13-48688.30" + process $proc$issuer_ls180.v:48688$3179 + assign { } { } + assign $1\prev_wr_go[2:0] 3'000 + sync always + sync init + update \prev_wr_go $1\prev_wr_go[2:0] + end + attribute \src "issuer_ls180.v:48696.13-48696.31" + process $proc$issuer_ls180.v:48696$3180 + assign { } { } + assign $1\req_l_r_req[2:0] 3'111 + sync always + sync init + update \req_l_r_req $1\req_l_r_req[2:0] + end + attribute \src "issuer_ls180.v:48700.13-48700.31" + process $proc$issuer_ls180.v:48700$3181 + assign { } { } + assign $1\req_l_s_req[2:0] 3'000 + sync always + sync init + update \req_l_s_req $1\req_l_s_req[2:0] + end + attribute \src "issuer_ls180.v:48712.7-48712.26" + process $proc$issuer_ls180.v:48712$3182 + assign { } { } + assign $1\rok_l_r_rdok[0:0] 1'1 + sync always + sync init + update \rok_l_r_rdok $1\rok_l_r_rdok[0:0] + end + attribute \src "issuer_ls180.v:48716.7-48716.26" + process $proc$issuer_ls180.v:48716$3183 + assign { } { } + assign $1\rok_l_s_rdok[0:0] 1'0 + sync always + sync init + update \rok_l_s_rdok $1\rok_l_s_rdok[0:0] + end + attribute \src "issuer_ls180.v:48720.7-48720.25" + process $proc$issuer_ls180.v:48720$3184 + assign { } { } + assign $1\rst_l_r_rst[0:0] 1'1 + sync always + sync init + update \rst_l_r_rst $1\rst_l_r_rst[0:0] + end + attribute \src "issuer_ls180.v:48724.7-48724.25" + process $proc$issuer_ls180.v:48724$3185 + assign { } { } + assign $1\rst_l_s_rst[0:0] 1'0 + sync always + sync init + update \rst_l_s_rst $1\rst_l_s_rst[0:0] + end + attribute \src "issuer_ls180.v:48744.13-48744.32" + process $proc$issuer_ls180.v:48744$3186 + assign { } { } + assign $1\src_l_r_src[5:0] 6'111111 + sync always + sync init + update \src_l_r_src $1\src_l_r_src[5:0] + end + attribute \src "issuer_ls180.v:48748.13-48748.32" + process $proc$issuer_ls180.v:48748$3187 + assign { } { } + assign $1\src_l_s_src[5:0] 6'000000 + sync always + sync init + update \src_l_s_src $1\src_l_s_src[5:0] + end + attribute \src "issuer_ls180.v:48752.14-48752.43" + process $proc$issuer_ls180.v:48752$3188 + assign { } { } + assign $1\src_r0[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \src_r0 $1\src_r0[63:0] + end + attribute \src "issuer_ls180.v:48756.14-48756.43" + process $proc$issuer_ls180.v:48756$3189 + assign { } { } + assign $1\src_r1[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \src_r1 $1\src_r1[63:0] + end + attribute \src "issuer_ls180.v:48760.14-48760.28" + process $proc$issuer_ls180.v:48760$3190 + assign { } { } + assign $1\src_r2[31:0] 0 + sync always + sync init + update \src_r2 $1\src_r2[31:0] + end + attribute \src "issuer_ls180.v:48764.13-48764.26" + process $proc$issuer_ls180.v:48764$3191 + assign { } { } + assign $1\src_r3[3:0] 4'0000 + sync always + sync init + update \src_r3 $1\src_r3[3:0] + end + attribute \src "issuer_ls180.v:48768.13-48768.26" + process $proc$issuer_ls180.v:48768$3192 + assign { } { } + assign $1\src_r4[3:0] 4'0000 + sync always + sync init + update \src_r4 $1\src_r4[3:0] + end + attribute \src "issuer_ls180.v:48772.13-48772.26" + process $proc$issuer_ls180.v:48772$3193 + assign { } { } + assign $1\src_r5[3:0] 4'0000 + sync always + sync init + update \src_r5 $1\src_r5[3:0] + end + attribute \src "issuer_ls180.v:48834.3-48835.37" + process $proc$issuer_ls180.v:48834$3041 + assign { } { } + assign $0\data_r0__o[63:0] \data_r0__o$next + sync posedge \coresync_clk + update \data_r0__o $0\data_r0__o[63:0] + end + attribute \src "issuer_ls180.v:48836.3-48837.43" + process $proc$issuer_ls180.v:48836$3042 + assign { } { } + assign $0\data_r0__o_ok[0:0] \data_r0__o_ok$next + sync posedge \coresync_clk + update \data_r0__o_ok $0\data_r0__o_ok[0:0] + end + attribute \src "issuer_ls180.v:48838.3-48839.65" + process $proc$issuer_ls180.v:48838$3043 + assign { } { } + assign $0\alu_cr0_cr_op__insn_type[6:0] \alu_cr0_cr_op__insn_type$next + sync posedge \coresync_clk + update \alu_cr0_cr_op__insn_type $0\alu_cr0_cr_op__insn_type[6:0] + end + attribute \src "issuer_ls180.v:48840.3-48841.61" + process $proc$issuer_ls180.v:48840$3044 + assign { } { } + assign $0\alu_cr0_cr_op__fn_unit[11:0] \alu_cr0_cr_op__fn_unit$next + sync posedge \coresync_clk + update \alu_cr0_cr_op__fn_unit $0\alu_cr0_cr_op__fn_unit[11:0] + end + attribute \src "issuer_ls180.v:48842.3-48843.55" + process $proc$issuer_ls180.v:48842$3045 + assign { } { } + assign $0\alu_cr0_cr_op__insn[31:0] \alu_cr0_cr_op__insn$next + sync posedge \coresync_clk + update \alu_cr0_cr_op__insn $0\alu_cr0_cr_op__insn[31:0] + end + attribute \src "issuer_ls180.v:48844.3-48845.39" + process $proc$issuer_ls180.v:48844$3046 + assign { } { } + assign $0\req_l_r_req[2:0] \req_l_r_req$next + sync posedge \coresync_clk + update \req_l_r_req $0\req_l_r_req[2:0] + end + attribute \src "issuer_ls180.v:48846.3-48847.39" + process $proc$issuer_ls180.v:48846$3047 + assign { } { } + assign $0\req_l_s_req[2:0] \req_l_s_req$next + sync posedge \coresync_clk + update \req_l_s_req $0\req_l_s_req[2:0] + end + attribute \src "issuer_ls180.v:48848.3-48849.39" + process $proc$issuer_ls180.v:48848$3048 + assign { } { } + assign $0\src_l_r_src[5:0] \src_l_r_src$next + sync posedge \coresync_clk + update \src_l_r_src $0\src_l_r_src[5:0] + end + attribute \src "issuer_ls180.v:48850.3-48851.39" + process $proc$issuer_ls180.v:48850$3049 + assign { } { } + assign $0\src_l_s_src[5:0] \src_l_s_src$next + sync posedge \coresync_clk + update \src_l_s_src $0\src_l_s_src[5:0] + end + attribute \src "issuer_ls180.v:48852.3-48853.39" + process $proc$issuer_ls180.v:48852$3050 + assign { } { } + assign $0\opc_l_r_opc[0:0] \opc_l_r_opc$next + sync posedge \coresync_clk + update \opc_l_r_opc $0\opc_l_r_opc[0:0] + end + attribute \src "issuer_ls180.v:48854.3-48855.39" + process $proc$issuer_ls180.v:48854$3051 + assign { } { } + assign $0\opc_l_s_opc[0:0] \opc_l_s_opc$next + sync posedge \coresync_clk + update \opc_l_s_opc $0\opc_l_s_opc[0:0] + end + attribute \src "issuer_ls180.v:48856.3-48857.39" + process $proc$issuer_ls180.v:48856$3052 + assign { } { } + assign $0\rst_l_r_rst[0:0] \rst_l_r_rst$next + sync posedge \coresync_clk + update \rst_l_r_rst $0\rst_l_r_rst[0:0] + end + attribute \src "issuer_ls180.v:48858.3-48859.39" + process $proc$issuer_ls180.v:48858$3053 + assign { } { } + assign $0\rst_l_s_rst[0:0] \rst_l_s_rst$next + sync posedge \coresync_clk + update \rst_l_s_rst $0\rst_l_s_rst[0:0] + end + attribute \src "issuer_ls180.v:48860.3-48861.41" + process $proc$issuer_ls180.v:48860$3054 + assign { } { } + assign $0\rok_l_r_rdok[0:0] \rok_l_r_rdok$next + sync posedge \coresync_clk + update \rok_l_r_rdok $0\rok_l_r_rdok[0:0] + end + attribute \src "issuer_ls180.v:48862.3-48863.41" + process $proc$issuer_ls180.v:48862$3055 + assign { } { } + assign $0\rok_l_s_rdok[0:0] \rok_l_s_rdok$next + sync posedge \coresync_clk + update \rok_l_s_rdok $0\rok_l_s_rdok[0:0] + end + attribute \src "issuer_ls180.v:48864.3-48865.37" + process $proc$issuer_ls180.v:48864$3056 + assign { } { } + assign $0\prev_wr_go[2:0] \prev_wr_go$next + sync posedge \coresync_clk + update \prev_wr_go $0\prev_wr_go[2:0] + end + attribute \src "issuer_ls180.v:48866.3-48867.39" + process $proc$issuer_ls180.v:48866$3057 + assign { } { } + assign $0\alu_done_dly[0:0] \alu_cr0_n_valid_o + sync posedge \coresync_clk + update \alu_done_dly $0\alu_done_dly[0:0] + end + attribute \src "issuer_ls180.v:48868.3-48869.25" + process $proc$issuer_ls180.v:48868$3058 + assign { } { } + assign $0\all_rd_dly[0:0] \$11 + sync posedge \coresync_clk + update \all_rd_dly $0\all_rd_dly[0:0] + end + attribute \src "issuer_ls180.v:48870.3-48871.39" + process $proc$issuer_ls180.v:48870$3059 + assign { } { } + assign $0\alu_l_r_alu[0:0] \alu_l_r_alu$next + sync posedge \coresync_clk + update \alu_l_r_alu $0\alu_l_r_alu[0:0] + end + attribute \src "issuer_ls180.v:48872.3-48873.43" + process $proc$issuer_ls180.v:48872$3060 + assign { } { } + assign $0\alui_l_r_alui[0:0] \alui_l_r_alui$next + sync posedge \coresync_clk + update \alui_l_r_alui $0\alui_l_r_alui[0:0] + end + attribute \src "issuer_ls180.v:48874.3-48875.29" + process $proc$issuer_ls180.v:48874$3061 + assign { } { } + assign $0\src_r5[3:0] \src_r5$next + sync posedge \coresync_clk + update \src_r5 $0\src_r5[3:0] + end + attribute \src "issuer_ls180.v:48876.3-48877.29" + process $proc$issuer_ls180.v:48876$3062 + assign { } { } + assign $0\src_r4[3:0] \src_r4$next + sync posedge \coresync_clk + update \src_r4 $0\src_r4[3:0] + end + attribute \src "issuer_ls180.v:48878.3-48879.29" + process $proc$issuer_ls180.v:48878$3063 + assign { } { } + assign $0\src_r3[3:0] \src_r3$next + sync posedge \coresync_clk + update \src_r3 $0\src_r3[3:0] + end + attribute \src "issuer_ls180.v:48880.3-48881.29" + process $proc$issuer_ls180.v:48880$3064 + assign { } { } + assign $0\src_r2[31:0] \src_r2$next + sync posedge \coresync_clk + update \src_r2 $0\src_r2[31:0] + end + attribute \src "issuer_ls180.v:48882.3-48883.29" + process $proc$issuer_ls180.v:48882$3065 + assign { } { } + assign $0\src_r1[63:0] \src_r1$next + sync posedge \coresync_clk + update \src_r1 $0\src_r1[63:0] + end + attribute \src "issuer_ls180.v:48884.3-48885.29" + process $proc$issuer_ls180.v:48884$3066 + assign { } { } + assign $0\src_r0[63:0] \src_r0$next + sync posedge \coresync_clk + update \src_r0 $0\src_r0[63:0] + end + attribute \src "issuer_ls180.v:48886.3-48887.43" + process $proc$issuer_ls180.v:48886$3067 + assign { } { } + assign $0\data_r2__cr_a[3:0] \data_r2__cr_a$next + sync posedge \coresync_clk + update \data_r2__cr_a $0\data_r2__cr_a[3:0] + end + attribute \src "issuer_ls180.v:48888.3-48889.49" + process $proc$issuer_ls180.v:48888$3068 + assign { } { } + assign $0\data_r2__cr_a_ok[0:0] \data_r2__cr_a_ok$next + sync posedge \coresync_clk + update \data_r2__cr_a_ok $0\data_r2__cr_a_ok[0:0] + end + attribute \src "issuer_ls180.v:48890.3-48891.49" + process $proc$issuer_ls180.v:48890$3069 + assign { } { } + assign $0\data_r1__full_cr[31:0] \data_r1__full_cr$next + sync posedge \coresync_clk + update \data_r1__full_cr $0\data_r1__full_cr[31:0] + end + attribute \src "issuer_ls180.v:48892.3-48893.55" + process $proc$issuer_ls180.v:48892$3070 + assign { } { } + assign $0\data_r1__full_cr_ok[0:0] \data_r1__full_cr_ok$next + sync posedge \coresync_clk + update \data_r1__full_cr_ok $0\data_r1__full_cr_ok[0:0] + end + attribute \src "issuer_ls180.v:48965.3-48974.6" + process $proc$issuer_ls180.v:48965$3071 + assign { } { } + assign { } { } + assign $0\req_done[0:0] $1\req_done[0:0] + attribute \src "issuer_ls180.v:48966.5-48966.29" + switch \initial + attribute \src "issuer_ls180.v:48966.9-48966.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" + switch \$55 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\req_done[0:0] 1'1 + case + assign $1\req_done[0:0] \$47 + end + sync always + update \req_done $0\req_done[0:0] + end + attribute \src "issuer_ls180.v:48975.3-48983.6" + process $proc$issuer_ls180.v:48975$3072 + assign { } { } + assign { } { } + assign $0\rok_l_s_rdok$next[0:0]$3073 $1\rok_l_s_rdok$next[0:0]$3074 + attribute \src "issuer_ls180.v:48976.5-48976.29" + switch \initial + attribute \src "issuer_ls180.v:48976.9-48976.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\rok_l_s_rdok$next[0:0]$3074 1'0 + case + assign $1\rok_l_s_rdok$next[0:0]$3074 \cu_issue_i + end + sync always + update \rok_l_s_rdok$next $0\rok_l_s_rdok$next[0:0]$3073 + end + attribute \src "issuer_ls180.v:48984.3-48992.6" + process $proc$issuer_ls180.v:48984$3075 + assign { } { } + assign { } { } + assign $0\rok_l_r_rdok$next[0:0]$3076 $1\rok_l_r_rdok$next[0:0]$3077 + attribute \src "issuer_ls180.v:48985.5-48985.29" + switch \initial + attribute \src "issuer_ls180.v:48985.9-48985.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\rok_l_r_rdok$next[0:0]$3077 1'1 + case + assign $1\rok_l_r_rdok$next[0:0]$3077 \$65 + end + sync always + update \rok_l_r_rdok$next $0\rok_l_r_rdok$next[0:0]$3076 + end + attribute \src "issuer_ls180.v:48993.3-49001.6" + process $proc$issuer_ls180.v:48993$3078 + assign { } { } + assign { } { } + assign $0\rst_l_s_rst$next[0:0]$3079 $1\rst_l_s_rst$next[0:0]$3080 + attribute \src "issuer_ls180.v:48994.5-48994.29" + switch \initial + attribute \src "issuer_ls180.v:48994.9-48994.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\rst_l_s_rst$next[0:0]$3080 1'0 + case + assign $1\rst_l_s_rst$next[0:0]$3080 \all_rd + end + sync always + update \rst_l_s_rst$next $0\rst_l_s_rst$next[0:0]$3079 + end + attribute \src "issuer_ls180.v:49002.3-49010.6" + process $proc$issuer_ls180.v:49002$3081 + assign { } { } + assign { } { } + assign $0\rst_l_r_rst$next[0:0]$3082 $1\rst_l_r_rst$next[0:0]$3083 + attribute \src "issuer_ls180.v:49003.5-49003.29" + switch \initial + attribute \src "issuer_ls180.v:49003.9-49003.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\rst_l_r_rst$next[0:0]$3083 1'1 + case + assign $1\rst_l_r_rst$next[0:0]$3083 \rst_r + end + sync always + update \rst_l_r_rst$next $0\rst_l_r_rst$next[0:0]$3082 + end + attribute \src "issuer_ls180.v:49011.3-49019.6" + process $proc$issuer_ls180.v:49011$3084 + assign { } { } + assign { } { } + assign $0\opc_l_s_opc$next[0:0]$3085 $1\opc_l_s_opc$next[0:0]$3086 + attribute \src "issuer_ls180.v:49012.5-49012.29" + switch \initial + attribute \src "issuer_ls180.v:49012.9-49012.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\opc_l_s_opc$next[0:0]$3086 1'0 + case + assign $1\opc_l_s_opc$next[0:0]$3086 \cu_issue_i + end + sync always + update \opc_l_s_opc$next $0\opc_l_s_opc$next[0:0]$3085 + end + attribute \src "issuer_ls180.v:49020.3-49028.6" + process $proc$issuer_ls180.v:49020$3087 + assign { } { } + assign { } { } + assign $0\opc_l_r_opc$next[0:0]$3088 $1\opc_l_r_opc$next[0:0]$3089 + attribute \src "issuer_ls180.v:49021.5-49021.29" + switch \initial + attribute \src "issuer_ls180.v:49021.9-49021.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\opc_l_r_opc$next[0:0]$3089 1'1 + case + assign $1\opc_l_r_opc$next[0:0]$3089 \req_done + end + sync always + update \opc_l_r_opc$next $0\opc_l_r_opc$next[0:0]$3088 + end + attribute \src "issuer_ls180.v:49029.3-49037.6" + process $proc$issuer_ls180.v:49029$3090 + assign { } { } + assign { } { } + assign $0\src_l_s_src$next[5:0]$3091 $1\src_l_s_src$next[5:0]$3092 + attribute \src "issuer_ls180.v:49030.5-49030.29" + switch \initial + attribute \src "issuer_ls180.v:49030.9-49030.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\src_l_s_src$next[5:0]$3092 6'000000 + case + assign $1\src_l_s_src$next[5:0]$3092 { \cu_issue_i \cu_issue_i \cu_issue_i \cu_issue_i \cu_issue_i \cu_issue_i } + end + sync always + update \src_l_s_src$next $0\src_l_s_src$next[5:0]$3091 + end + attribute \src "issuer_ls180.v:49038.3-49046.6" + process $proc$issuer_ls180.v:49038$3093 + assign { } { } + assign { } { } + assign $0\src_l_r_src$next[5:0]$3094 $1\src_l_r_src$next[5:0]$3095 + attribute \src "issuer_ls180.v:49039.5-49039.29" + switch \initial + attribute \src "issuer_ls180.v:49039.9-49039.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\src_l_r_src$next[5:0]$3095 6'111111 + case + assign $1\src_l_r_src$next[5:0]$3095 \reset_r + end + sync always + update \src_l_r_src$next $0\src_l_r_src$next[5:0]$3094 + end + attribute \src "issuer_ls180.v:49047.3-49055.6" + process $proc$issuer_ls180.v:49047$3096 + assign { } { } + assign { } { } + assign $0\req_l_s_req$next[2:0]$3097 $1\req_l_s_req$next[2:0]$3098 + attribute \src "issuer_ls180.v:49048.5-49048.29" + switch \initial + attribute \src "issuer_ls180.v:49048.9-49048.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\req_l_s_req$next[2:0]$3098 3'000 + case + assign $1\req_l_s_req$next[2:0]$3098 \$67 + end + sync always + update \req_l_s_req$next $0\req_l_s_req$next[2:0]$3097 + end + attribute \src "issuer_ls180.v:49056.3-49064.6" + process $proc$issuer_ls180.v:49056$3099 + assign { } { } + assign { } { } + assign $0\req_l_r_req$next[2:0]$3100 $1\req_l_r_req$next[2:0]$3101 + attribute \src "issuer_ls180.v:49057.5-49057.29" + switch \initial + attribute \src "issuer_ls180.v:49057.9-49057.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\req_l_r_req$next[2:0]$3101 3'111 + case + assign $1\req_l_r_req$next[2:0]$3101 \$69 + end + sync always + update \req_l_r_req$next $0\req_l_r_req$next[2:0]$3100 + end + attribute \src "issuer_ls180.v:49065.3-49076.6" + process $proc$issuer_ls180.v:49065$3102 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\alu_cr0_cr_op__fn_unit$next[11:0]$3103 $1\alu_cr0_cr_op__fn_unit$next[11:0]$3106 + assign $0\alu_cr0_cr_op__insn$next[31:0]$3104 $1\alu_cr0_cr_op__insn$next[31:0]$3107 + assign $0\alu_cr0_cr_op__insn_type$next[6:0]$3105 $1\alu_cr0_cr_op__insn_type$next[6:0]$3108 + attribute \src "issuer_ls180.v:49066.5-49066.29" + switch \initial + attribute \src "issuer_ls180.v:49066.9-49066.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:257" + switch \cu_issue_i + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { $1\alu_cr0_cr_op__insn$next[31:0]$3107 $1\alu_cr0_cr_op__fn_unit$next[11:0]$3106 $1\alu_cr0_cr_op__insn_type$next[6:0]$3108 } { \oper_i_alu_cr0__insn \oper_i_alu_cr0__fn_unit \oper_i_alu_cr0__insn_type } + case + assign $1\alu_cr0_cr_op__fn_unit$next[11:0]$3106 \alu_cr0_cr_op__fn_unit + assign $1\alu_cr0_cr_op__insn$next[31:0]$3107 \alu_cr0_cr_op__insn + assign $1\alu_cr0_cr_op__insn_type$next[6:0]$3108 \alu_cr0_cr_op__insn_type + end + sync always + update \alu_cr0_cr_op__fn_unit$next $0\alu_cr0_cr_op__fn_unit$next[11:0]$3103 + update \alu_cr0_cr_op__insn$next $0\alu_cr0_cr_op__insn$next[31:0]$3104 + update \alu_cr0_cr_op__insn_type$next $0\alu_cr0_cr_op__insn_type$next[6:0]$3105 + end + attribute \src "issuer_ls180.v:49077.3-49098.6" + process $proc$issuer_ls180.v:49077$3109 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\data_r0__o$next[63:0]$3110 $2\data_r0__o$next[63:0]$3114 + assign { } { } + assign $0\data_r0__o_ok$next[0:0]$3111 $3\data_r0__o_ok$next[0:0]$3116 + attribute \src "issuer_ls180.v:49078.5-49078.29" + switch \initial + attribute \src "issuer_ls180.v:49078.9-49078.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" + switch \alu_pulse + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $1\data_r0__o_ok$next[0:0]$3113 $1\data_r0__o$next[63:0]$3112 } { \o_ok \alu_cr0_o } + case + assign $1\data_r0__o$next[63:0]$3112 \data_r0__o + assign $1\data_r0__o_ok$next[0:0]$3113 \data_r0__o_ok + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" + switch \cu_issue_i + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $2\data_r0__o_ok$next[0:0]$3115 $2\data_r0__o$next[63:0]$3114 } 65'00000000000000000000000000000000000000000000000000000000000000000 + case + assign $2\data_r0__o$next[63:0]$3114 $1\data_r0__o$next[63:0]$3112 + assign $2\data_r0__o_ok$next[0:0]$3115 $1\data_r0__o_ok$next[0:0]$3113 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\data_r0__o_ok$next[0:0]$3116 1'0 + case + assign $3\data_r0__o_ok$next[0:0]$3116 $2\data_r0__o_ok$next[0:0]$3115 + end + sync always + update \data_r0__o$next $0\data_r0__o$next[63:0]$3110 + update \data_r0__o_ok$next $0\data_r0__o_ok$next[0:0]$3111 + end + attribute \src "issuer_ls180.v:49099.3-49120.6" + process $proc$issuer_ls180.v:49099$3117 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\data_r1__full_cr$next[31:0]$3118 $2\data_r1__full_cr$next[31:0]$3122 + assign { } { } + assign $0\data_r1__full_cr_ok$next[0:0]$3119 $3\data_r1__full_cr_ok$next[0:0]$3124 + attribute \src "issuer_ls180.v:49100.5-49100.29" + switch \initial + attribute \src "issuer_ls180.v:49100.9-49100.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" + switch \alu_pulse + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $1\data_r1__full_cr_ok$next[0:0]$3121 $1\data_r1__full_cr$next[31:0]$3120 } { \full_cr_ok \alu_cr0_full_cr } + case + assign $1\data_r1__full_cr$next[31:0]$3120 \data_r1__full_cr + assign $1\data_r1__full_cr_ok$next[0:0]$3121 \data_r1__full_cr_ok + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" + switch \cu_issue_i + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $2\data_r1__full_cr_ok$next[0:0]$3123 $2\data_r1__full_cr$next[31:0]$3122 } 33'000000000000000000000000000000000 + case + assign $2\data_r1__full_cr$next[31:0]$3122 $1\data_r1__full_cr$next[31:0]$3120 + assign $2\data_r1__full_cr_ok$next[0:0]$3123 $1\data_r1__full_cr_ok$next[0:0]$3121 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\data_r1__full_cr_ok$next[0:0]$3124 1'0 + case + assign $3\data_r1__full_cr_ok$next[0:0]$3124 $2\data_r1__full_cr_ok$next[0:0]$3123 + end + sync always + update \data_r1__full_cr$next $0\data_r1__full_cr$next[31:0]$3118 + update \data_r1__full_cr_ok$next $0\data_r1__full_cr_ok$next[0:0]$3119 + end + attribute \src "issuer_ls180.v:49121.3-49142.6" + process $proc$issuer_ls180.v:49121$3125 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\data_r2__cr_a$next[3:0]$3126 $2\data_r2__cr_a$next[3:0]$3130 + assign { } { } + assign $0\data_r2__cr_a_ok$next[0:0]$3127 $3\data_r2__cr_a_ok$next[0:0]$3132 + attribute \src "issuer_ls180.v:49122.5-49122.29" + switch \initial + attribute \src "issuer_ls180.v:49122.9-49122.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" + switch \alu_pulse + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $1\data_r2__cr_a_ok$next[0:0]$3129 $1\data_r2__cr_a$next[3:0]$3128 } { \cr_a_ok \alu_cr0_cr_a } + case + assign $1\data_r2__cr_a$next[3:0]$3128 \data_r2__cr_a + assign $1\data_r2__cr_a_ok$next[0:0]$3129 \data_r2__cr_a_ok + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" + switch \cu_issue_i + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $2\data_r2__cr_a_ok$next[0:0]$3131 $2\data_r2__cr_a$next[3:0]$3130 } 5'00000 + case + assign $2\data_r2__cr_a$next[3:0]$3130 $1\data_r2__cr_a$next[3:0]$3128 + assign $2\data_r2__cr_a_ok$next[0:0]$3131 $1\data_r2__cr_a_ok$next[0:0]$3129 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\data_r2__cr_a_ok$next[0:0]$3132 1'0 + case + assign $3\data_r2__cr_a_ok$next[0:0]$3132 $2\data_r2__cr_a_ok$next[0:0]$3131 + end + sync always + update \data_r2__cr_a$next $0\data_r2__cr_a$next[3:0]$3126 + update \data_r2__cr_a_ok$next $0\data_r2__cr_a_ok$next[0:0]$3127 + end + attribute \src "issuer_ls180.v:49143.3-49152.6" + process $proc$issuer_ls180.v:49143$3133 + assign { } { } + assign { } { } + assign $0\src_r0$next[63:0]$3134 $1\src_r0$next[63:0]$3135 + attribute \src "issuer_ls180.v:49144.5-49144.29" + switch \initial + attribute \src "issuer_ls180.v:49144.9-49144.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" + switch \src_l_q_src [0] + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\src_r0$next[63:0]$3135 \src1_i + case + assign $1\src_r0$next[63:0]$3135 \src_r0 + end + sync always + update \src_r0$next $0\src_r0$next[63:0]$3134 + end + attribute \src "issuer_ls180.v:49153.3-49162.6" + process $proc$issuer_ls180.v:49153$3136 + assign { } { } + assign { } { } + assign $0\src_r1$next[63:0]$3137 $1\src_r1$next[63:0]$3138 + attribute \src "issuer_ls180.v:49154.5-49154.29" + switch \initial + attribute \src "issuer_ls180.v:49154.9-49154.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" + switch \src_l_q_src [1] + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\src_r1$next[63:0]$3138 \src2_i + case + assign $1\src_r1$next[63:0]$3138 \src_r1 + end + sync always + update \src_r1$next $0\src_r1$next[63:0]$3137 + end + attribute \src "issuer_ls180.v:49163.3-49172.6" + process $proc$issuer_ls180.v:49163$3139 + assign { } { } + assign { } { } + assign $0\src_r2$next[31:0]$3140 $1\src_r2$next[31:0]$3141 + attribute \src "issuer_ls180.v:49164.5-49164.29" + switch \initial + attribute \src "issuer_ls180.v:49164.9-49164.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" + switch \src_l_q_src [2] + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\src_r2$next[31:0]$3141 \src3_i + case + assign $1\src_r2$next[31:0]$3141 \src_r2 + end + sync always + update \src_r2$next $0\src_r2$next[31:0]$3140 + end + attribute \src "issuer_ls180.v:49173.3-49182.6" + process $proc$issuer_ls180.v:49173$3142 + assign { } { } + assign { } { } + assign $0\src_r3$next[3:0]$3143 $1\src_r3$next[3:0]$3144 + attribute \src "issuer_ls180.v:49174.5-49174.29" + switch \initial + attribute \src "issuer_ls180.v:49174.9-49174.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" + switch \src_l_q_src [3] + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\src_r3$next[3:0]$3144 \src4_i + case + assign $1\src_r3$next[3:0]$3144 \src_r3 + end + sync always + update \src_r3$next $0\src_r3$next[3:0]$3143 + end + attribute \src "issuer_ls180.v:49183.3-49192.6" + process $proc$issuer_ls180.v:49183$3145 + assign { } { } + assign { } { } + assign $0\src_r4$next[3:0]$3146 $1\src_r4$next[3:0]$3147 + attribute \src "issuer_ls180.v:49184.5-49184.29" + switch \initial + attribute \src "issuer_ls180.v:49184.9-49184.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" + switch \src_l_q_src [4] + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\src_r4$next[3:0]$3147 \src5_i + case + assign $1\src_r4$next[3:0]$3147 \src_r4 + end + sync always + update \src_r4$next $0\src_r4$next[3:0]$3146 + end + attribute \src "issuer_ls180.v:49193.3-49202.6" + process $proc$issuer_ls180.v:49193$3148 + assign { } { } + assign { } { } + assign $0\src_r5$next[3:0]$3149 $1\src_r5$next[3:0]$3150 + attribute \src "issuer_ls180.v:49194.5-49194.29" + switch \initial + attribute \src "issuer_ls180.v:49194.9-49194.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" + switch \src_l_q_src [5] + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\src_r5$next[3:0]$3150 \src6_i + case + assign $1\src_r5$next[3:0]$3150 \src_r5 + end + sync always + update \src_r5$next $0\src_r5$next[3:0]$3149 + end + attribute \src "issuer_ls180.v:49203.3-49211.6" + process $proc$issuer_ls180.v:49203$3151 + assign { } { } + assign { } { } + assign $0\alui_l_r_alui$next[0:0]$3152 $1\alui_l_r_alui$next[0:0]$3153 + attribute \src "issuer_ls180.v:49204.5-49204.29" + switch \initial + attribute \src "issuer_ls180.v:49204.9-49204.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\alui_l_r_alui$next[0:0]$3153 1'1 + case + assign $1\alui_l_r_alui$next[0:0]$3153 \$89 + end + sync always + update \alui_l_r_alui$next $0\alui_l_r_alui$next[0:0]$3152 + end + attribute \src "issuer_ls180.v:49212.3-49220.6" + process $proc$issuer_ls180.v:49212$3154 + assign { } { } + assign { } { } + assign $0\alu_l_r_alu$next[0:0]$3155 $1\alu_l_r_alu$next[0:0]$3156 + attribute \src "issuer_ls180.v:49213.5-49213.29" + switch \initial + attribute \src "issuer_ls180.v:49213.9-49213.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\alu_l_r_alu$next[0:0]$3156 1'1 + case + assign $1\alu_l_r_alu$next[0:0]$3156 \$91 + end + sync always + update \alu_l_r_alu$next $0\alu_l_r_alu$next[0:0]$3155 + end + attribute \src "issuer_ls180.v:49221.3-49230.6" + process $proc$issuer_ls180.v:49221$3157 + assign { } { } + assign { } { } + assign $0\dest1_o[63:0] $1\dest1_o[63:0] + attribute \src "issuer_ls180.v:49222.5-49222.29" + switch \initial + attribute \src "issuer_ls180.v:49222.9-49222.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" + switch \$111 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dest1_o[63:0] \data_r0__o + case + assign $1\dest1_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \dest1_o $0\dest1_o[63:0] + end + attribute \src "issuer_ls180.v:49231.3-49240.6" + process $proc$issuer_ls180.v:49231$3158 + assign { } { } + assign { } { } + assign $0\dest2_o[31:0] $1\dest2_o[31:0] + attribute \src "issuer_ls180.v:49232.5-49232.29" + switch \initial + attribute \src "issuer_ls180.v:49232.9-49232.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" + switch \$113 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dest2_o[31:0] \data_r1__full_cr + case + assign $1\dest2_o[31:0] 0 + end + sync always + update \dest2_o $0\dest2_o[31:0] + end + attribute \src "issuer_ls180.v:49241.3-49250.6" + process $proc$issuer_ls180.v:49241$3159 + assign { } { } + assign { } { } + assign $0\dest3_o[3:0] $1\dest3_o[3:0] + attribute \src "issuer_ls180.v:49242.5-49242.29" + switch \initial + attribute \src "issuer_ls180.v:49242.9-49242.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" + switch \$115 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dest3_o[3:0] \data_r2__cr_a + case + assign $1\dest3_o[3:0] 4'0000 + end + sync always + update \dest3_o $0\dest3_o[3:0] + end + attribute \src "issuer_ls180.v:49251.3-49259.6" + process $proc$issuer_ls180.v:49251$3160 + assign { } { } + assign { } { } + assign $0\prev_wr_go$next[2:0]$3161 $1\prev_wr_go$next[2:0]$3162 + attribute \src "issuer_ls180.v:49252.5-49252.29" + switch \initial + attribute \src "issuer_ls180.v:49252.9-49252.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\prev_wr_go$next[2:0]$3162 3'000 + case + assign $1\prev_wr_go$next[2:0]$3162 \$21 + end + sync always + update \prev_wr_go$next $0\prev_wr_go$next[2:0]$3161 + end + connect \$5 $reduce_and$issuer_ls180.v:48777$2984_Y + connect \$99 $and$issuer_ls180.v:48778$2985_Y + connect \$101 $and$issuer_ls180.v:48779$2986_Y + connect \$103 $and$issuer_ls180.v:48780$2987_Y + connect \$105 $and$issuer_ls180.v:48781$2988_Y + connect \$107 $and$issuer_ls180.v:48782$2989_Y + connect \$109 $and$issuer_ls180.v:48783$2990_Y + connect \$111 $and$issuer_ls180.v:48784$2991_Y + connect \$113 $and$issuer_ls180.v:48785$2992_Y + connect \$115 $and$issuer_ls180.v:48786$2993_Y + connect \$11 $and$issuer_ls180.v:48787$2994_Y + connect \$13 $not$issuer_ls180.v:48788$2995_Y + connect \$15 $and$issuer_ls180.v:48789$2996_Y + connect \$17 $not$issuer_ls180.v:48790$2997_Y + connect \$19 $and$issuer_ls180.v:48791$2998_Y + connect \$21 $and$issuer_ls180.v:48792$2999_Y + connect \$25 $not$issuer_ls180.v:48793$3000_Y + connect \$27 $and$issuer_ls180.v:48794$3001_Y + connect \$24 $reduce_or$issuer_ls180.v:48795$3002_Y + connect \$23 $not$issuer_ls180.v:48796$3003_Y + connect \$31 $and$issuer_ls180.v:48797$3004_Y + connect \$33 $reduce_or$issuer_ls180.v:48798$3005_Y + connect \$35 $reduce_or$issuer_ls180.v:48799$3006_Y + connect \$37 $or$issuer_ls180.v:48800$3007_Y + connect \$3 $and$issuer_ls180.v:48801$3008_Y + connect \$39 $not$issuer_ls180.v:48802$3009_Y + connect \$41 $and$issuer_ls180.v:48803$3010_Y + connect \$43 $and$issuer_ls180.v:48804$3011_Y + connect \$45 $eq$issuer_ls180.v:48805$3012_Y + connect \$47 $and$issuer_ls180.v:48806$3013_Y + connect \$49 $eq$issuer_ls180.v:48807$3014_Y + connect \$51 $and$issuer_ls180.v:48808$3015_Y + connect \$53 $and$issuer_ls180.v:48809$3016_Y + connect \$55 $and$issuer_ls180.v:48810$3017_Y + connect \$57 $or$issuer_ls180.v:48811$3018_Y + connect \$59 $or$issuer_ls180.v:48812$3019_Y + connect \$61 $or$issuer_ls180.v:48813$3020_Y + connect \$63 $or$issuer_ls180.v:48814$3021_Y + connect \$65 $and$issuer_ls180.v:48815$3022_Y + connect \$67 $and$issuer_ls180.v:48816$3023_Y + connect \$6 $not$issuer_ls180.v:48817$3024_Y + connect \$69 $or$issuer_ls180.v:48818$3025_Y + connect \$71 $and$issuer_ls180.v:48819$3026_Y + connect \$73 $and$issuer_ls180.v:48820$3027_Y + connect \$75 $and$issuer_ls180.v:48821$3028_Y + connect \$77 $ternary$issuer_ls180.v:48822$3029_Y + connect \$79 $ternary$issuer_ls180.v:48823$3030_Y + connect \$81 $ternary$issuer_ls180.v:48824$3031_Y + connect \$83 $ternary$issuer_ls180.v:48825$3032_Y + connect \$85 $ternary$issuer_ls180.v:48826$3033_Y + connect \$87 $ternary$issuer_ls180.v:48827$3034_Y + connect \$8 $or$issuer_ls180.v:48828$3035_Y + connect \$89 $and$issuer_ls180.v:48829$3036_Y + connect \$91 $and$issuer_ls180.v:48830$3037_Y + connect \$93 $and$issuer_ls180.v:48831$3038_Y + connect \$95 $and$issuer_ls180.v:48832$3039_Y + connect \$97 $not$issuer_ls180.v:48833$3040_Y + connect \cu_go_die_i 1'0 + connect \cu_shadown_i 1'1 + connect \cu_wr__rel_o \$109 + connect \cu_rd__rel_o \$99 + connect \cu_busy_o \opc_l_q_opc + connect \alu_l_s_alu \all_rd_pulse + connect \alu_cr0_n_ready_i \alu_l_q_alu + connect \alui_l_s_alui \all_rd_pulse + connect \alu_cr0_p_valid_i \alui_l_q_alui + connect \alu_cr0_cr_c \$87 + connect \alu_cr0_cr_b \$85 + connect \alu_cr0_cr_a$2 \$83 + connect \alu_cr0_full_cr$1 \$81 + connect \alu_cr0_rb \$79 + connect \alu_cr0_ra \$77 + connect \cu_wrmask_o { \$75 \$73 \$71 } + connect \reset_r \$63 + connect \reset_w \$61 + connect \rst_r \$59 + connect \reset \$57 + connect \wr_any \$37 + connect \cu_done_o \$31 + connect \alu_pulsem { \alu_pulse \alu_pulse \alu_pulse } + connect \alu_pulse \alu_done_rise + connect \alu_done_rise \$19 + connect \alu_done_dly$next \alu_done + connect \alu_done \alu_cr0_n_valid_o + connect \all_rd_pulse \all_rd_rise + connect \all_rd_rise \$15 + connect \all_rd_dly$next \all_rd + connect \all_rd \$11 +end +attribute \src "issuer_ls180.v:49295.1-49344.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.l0.pimem.cyc_l" +attribute \generator "nMigen" +module \cyc_l + attribute \src "issuer_ls180.v:49296.7-49296.20" + wire $0\initial[0:0] + attribute \src "issuer_ls180.v:49332.3-49340.6" + wire $0\q_int$next[0:0]$3201 + attribute \src "issuer_ls180.v:49330.3-49331.27" + wire $0\q_int[0:0] + attribute \src "issuer_ls180.v:49332.3-49340.6" + wire $1\q_int$next[0:0]$3202 + attribute \src "issuer_ls180.v:49314.7-49314.19" + wire $1\q_int[0:0] + attribute \src "issuer_ls180.v:49327.17-49327.96" + wire $and$issuer_ls180.v:49327$3196_Y + attribute \src "issuer_ls180.v:49326.17-49326.92" + wire $not$issuer_ls180.v:49326$3195_Y + attribute \src "issuer_ls180.v:49329.17-49329.92" + wire $not$issuer_ls180.v:49329$3198_Y + attribute \src "issuer_ls180.v:49325.17-49325.98" + wire $or$issuer_ls180.v:49325$3194_Y + attribute \src "issuer_ls180.v:49328.17-49328.97" + wire $or$issuer_ls180.v:49328$3197_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + wire \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" + wire input 5 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" + wire input 1 \coresync_rst + attribute \src "issuer_ls180.v:49296.7-49296.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire output 4 \q_cyc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" + wire \qlq_cyc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + wire \qn_cyc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire input 3 \r_cyc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire input 2 \s_cyc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $and $and$issuer_ls180.v:49327$3196 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$1 + connect \Y $and$issuer_ls180.v:49327$3196_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $not $not$issuer_ls180.v:49326$3195 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_cyc + connect \Y $not$issuer_ls180.v:49326$3195_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + cell $not $not$issuer_ls180.v:49329$3198 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_cyc + connect \Y $not$issuer_ls180.v:49329$3198_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + cell $or $or$issuer_ls180.v:49325$3194 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_cyc + connect \B \q_int + connect \Y $or$issuer_ls180.v:49325$3194_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $or $or$issuer_ls180.v:49328$3197 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$3 + connect \B \s_cyc + connect \Y $or$issuer_ls180.v:49328$3197_Y + end + attribute \src "issuer_ls180.v:49296.7-49296.20" + process $proc$issuer_ls180.v:49296$3203 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "issuer_ls180.v:49314.7-49314.19" + process $proc$issuer_ls180.v:49314$3204 + assign { } { } + assign $1\q_int[0:0] 1'0 + sync always + sync init + update \q_int $1\q_int[0:0] + end + attribute \src "issuer_ls180.v:49330.3-49331.27" + process $proc$issuer_ls180.v:49330$3199 + assign { } { } + assign $0\q_int[0:0] \q_int$next + sync posedge \coresync_clk + update \q_int $0\q_int[0:0] + end + attribute \src "issuer_ls180.v:49332.3-49340.6" + process $proc$issuer_ls180.v:49332$3200 + assign { } { } + assign { } { } + assign $0\q_int$next[0:0]$3201 $1\q_int$next[0:0]$3202 + attribute \src "issuer_ls180.v:49333.5-49333.29" + switch \initial + attribute \src "issuer_ls180.v:49333.9-49333.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\q_int$next[0:0]$3202 1'0 + case + assign $1\q_int$next[0:0]$3202 \$5 + end + sync always + update \q_int$next $0\q_int$next[0:0]$3201 + end + connect \$9 $or$issuer_ls180.v:49325$3194_Y + connect \$1 $not$issuer_ls180.v:49326$3195_Y + connect \$3 $and$issuer_ls180.v:49327$3196_Y + connect \$5 $or$issuer_ls180.v:49328$3197_Y + connect \$7 $not$issuer_ls180.v:49329$3198_Y + connect \qlq_cyc \$9 + connect \qn_cyc \$7 + connect \q_cyc \q_int +end +attribute \src "issuer_ls180.v:49348.1-50062.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.dbg" +attribute \generator "nMigen" +module \dbg + attribute \src "issuer_ls180.v:49878.3-49887.6" + wire $0\d_cr_req[0:0] + attribute \src "issuer_ls180.v:49685.3-49694.6" + wire $0\d_gpr_req[0:0] + attribute \src "issuer_ls180.v:49888.3-49897.6" + wire $0\d_xer_req[0:0] + attribute \src "issuer_ls180.v:49667.3-49684.6" + wire $0\dmi_ack_o[0:0] + attribute \src "issuer_ls180.v:49898.3-49928.6" + wire width 64 $0\dmi_dout[63:0] + attribute \src "issuer_ls180.v:49869.3-49877.6" + wire $0\dmi_read_log_data$next[0:0]$3318 + attribute \src "issuer_ls180.v:49645.3-49646.51" + wire $0\dmi_read_log_data[0:0] + attribute \src "issuer_ls180.v:49860.3-49868.6" + wire $0\dmi_read_log_data_1$next[0:0]$3315 + attribute \src "issuer_ls180.v:49647.3-49648.55" + wire $0\dmi_read_log_data_1[0:0] + attribute \src "issuer_ls180.v:49695.3-49703.6" + wire $0\dmi_req_i_1$next[0:0]$3281 + attribute \src "issuer_ls180.v:49657.3-49658.39" + wire $0\dmi_req_i_1[0:0] + attribute \src "issuer_ls180.v:50019.3-50052.6" + wire $0\do_dmi_log_rd$next[0:0]$3345 + attribute \src "issuer_ls180.v:49659.3-49660.43" + wire $0\do_dmi_log_rd[0:0] + attribute \src "issuer_ls180.v:49989.3-50018.6" + wire $0\do_icreset$next[0:0]$3338 + attribute \src "issuer_ls180.v:49661.3-49662.37" + wire $0\do_icreset[0:0] + attribute \src "issuer_ls180.v:49959.3-49988.6" + wire $0\do_reset$next[0:0]$3331 + attribute \src "issuer_ls180.v:49663.3-49664.33" + wire $0\do_reset[0:0] + attribute \src "issuer_ls180.v:49929.3-49958.6" + wire $0\do_step$next[0:0]$3324 + attribute \src "issuer_ls180.v:49665.3-49666.31" + wire $0\do_step[0:0] + attribute \src "issuer_ls180.v:49798.3-49825.6" + wire width 7 $0\gspr_index$next[6:0]$3303 + attribute \src "issuer_ls180.v:49651.3-49652.37" + wire width 7 $0\gspr_index[6:0] + attribute \src "issuer_ls180.v:49349.7-49349.20" + wire $0\initial[0:0] + attribute \src "issuer_ls180.v:49826.3-49859.6" + wire width 32 $0\log_dmi_addr$next[31:0]$3309 + attribute \src "issuer_ls180.v:49649.3-49650.41" + wire width 32 $0\log_dmi_addr[31:0] + attribute \src "issuer_ls180.v:49754.3-49797.6" + wire $0\stopping$next[0:0]$3294 + attribute \src "issuer_ls180.v:49653.3-49654.33" + wire $0\stopping[0:0] + attribute \src "issuer_ls180.v:49704.3-49753.6" + wire $0\terminated$next[0:0]$3284 + attribute \src "issuer_ls180.v:49655.3-49656.37" + wire $0\terminated[0:0] + attribute \src "issuer_ls180.v:49878.3-49887.6" + wire $1\d_cr_req[0:0] + attribute \src "issuer_ls180.v:49685.3-49694.6" + wire $1\d_gpr_req[0:0] + attribute \src "issuer_ls180.v:49888.3-49897.6" + wire $1\d_xer_req[0:0] + attribute \src "issuer_ls180.v:49667.3-49684.6" + wire $1\dmi_ack_o[0:0] + attribute \src "issuer_ls180.v:49898.3-49928.6" + wire width 64 $1\dmi_dout[63:0] + attribute \src "issuer_ls180.v:49869.3-49877.6" + wire $1\dmi_read_log_data$next[0:0]$3319 + attribute \src "issuer_ls180.v:49522.7-49522.31" + wire $1\dmi_read_log_data[0:0] + attribute \src "issuer_ls180.v:49860.3-49868.6" + wire $1\dmi_read_log_data_1$next[0:0]$3316 + attribute \src "issuer_ls180.v:49526.7-49526.33" + wire $1\dmi_read_log_data_1[0:0] + attribute \src "issuer_ls180.v:49695.3-49703.6" + wire $1\dmi_req_i_1$next[0:0]$3282 + attribute \src "issuer_ls180.v:49532.7-49532.25" + wire $1\dmi_req_i_1[0:0] + attribute \src "issuer_ls180.v:50019.3-50052.6" + wire $1\do_dmi_log_rd$next[0:0]$3346 + attribute \src "issuer_ls180.v:49538.7-49538.27" + wire $1\do_dmi_log_rd[0:0] + attribute \src "issuer_ls180.v:49989.3-50018.6" + wire $1\do_icreset$next[0:0]$3339 + attribute \src "issuer_ls180.v:49542.7-49542.24" + wire $1\do_icreset[0:0] + attribute \src "issuer_ls180.v:49959.3-49988.6" + wire $1\do_reset$next[0:0]$3332 + attribute \src "issuer_ls180.v:49546.7-49546.22" + wire $1\do_reset[0:0] + attribute \src "issuer_ls180.v:49929.3-49958.6" + wire $1\do_step$next[0:0]$3325 + attribute \src "issuer_ls180.v:49550.7-49550.21" + wire $1\do_step[0:0] + attribute \src "issuer_ls180.v:49798.3-49825.6" + wire width 7 $1\gspr_index$next[6:0]$3304 + attribute \src "issuer_ls180.v:49554.13-49554.31" + wire width 7 $1\gspr_index[6:0] + attribute \src "issuer_ls180.v:49826.3-49859.6" + wire width 32 $1\log_dmi_addr$next[31:0]$3310 + attribute \src "issuer_ls180.v:49560.14-49560.34" + wire width 32 $1\log_dmi_addr[31:0] + attribute \src "issuer_ls180.v:49754.3-49797.6" + wire $1\stopping$next[0:0]$3295 + attribute \src "issuer_ls180.v:49572.7-49572.22" + wire $1\stopping[0:0] + attribute \src "issuer_ls180.v:49704.3-49753.6" + wire $1\terminated$next[0:0]$3285 + attribute \src "issuer_ls180.v:49578.7-49578.24" + wire $1\terminated[0:0] + attribute \src "issuer_ls180.v:50019.3-50052.6" + wire $2\do_dmi_log_rd$next[0:0]$3347 + attribute \src "issuer_ls180.v:49989.3-50018.6" + wire $2\do_icreset$next[0:0]$3340 + attribute \src "issuer_ls180.v:49959.3-49988.6" + wire $2\do_reset$next[0:0]$3333 + attribute \src "issuer_ls180.v:49929.3-49958.6" + wire $2\do_step$next[0:0]$3326 + attribute \src "issuer_ls180.v:49798.3-49825.6" + wire width 7 $2\gspr_index$next[6:0]$3305 + attribute \src "issuer_ls180.v:49826.3-49859.6" + wire width 32 $2\log_dmi_addr$next[31:0]$3311 + attribute \src "issuer_ls180.v:49754.3-49797.6" + wire $2\stopping$next[0:0]$3296 + attribute \src "issuer_ls180.v:49704.3-49753.6" + wire $2\terminated$next[0:0]$3286 + attribute \src "issuer_ls180.v:50019.3-50052.6" + wire $3\do_dmi_log_rd$next[0:0]$3348 + attribute \src "issuer_ls180.v:49989.3-50018.6" + wire $3\do_icreset$next[0:0]$3341 + attribute \src "issuer_ls180.v:49959.3-49988.6" + wire $3\do_reset$next[0:0]$3334 + attribute \src "issuer_ls180.v:49929.3-49958.6" + wire $3\do_step$next[0:0]$3327 + attribute \src "issuer_ls180.v:49798.3-49825.6" + wire width 7 $3\gspr_index$next[6:0]$3306 + attribute \src "issuer_ls180.v:49826.3-49859.6" + wire width 32 $3\log_dmi_addr$next[31:0]$3312 + attribute \src "issuer_ls180.v:49754.3-49797.6" + wire $3\stopping$next[0:0]$3297 + attribute \src "issuer_ls180.v:49704.3-49753.6" + wire $3\terminated$next[0:0]$3287 + attribute \src "issuer_ls180.v:50019.3-50052.6" + wire $4\do_dmi_log_rd$next[0:0]$3349 + attribute \src "issuer_ls180.v:49989.3-50018.6" + wire $4\do_icreset$next[0:0]$3342 + attribute \src "issuer_ls180.v:49959.3-49988.6" + wire $4\do_reset$next[0:0]$3335 + attribute \src "issuer_ls180.v:49929.3-49958.6" + wire $4\do_step$next[0:0]$3328 + attribute \src "issuer_ls180.v:49798.3-49825.6" + wire width 7 $4\gspr_index$next[6:0]$3307 + attribute \src "issuer_ls180.v:49826.3-49859.6" + wire width 32 $4\log_dmi_addr$next[31:0]$3313 + attribute \src "issuer_ls180.v:49754.3-49797.6" + wire $4\stopping$next[0:0]$3298 + attribute \src "issuer_ls180.v:49704.3-49753.6" + wire $4\terminated$next[0:0]$3288 + attribute \src "issuer_ls180.v:49989.3-50018.6" + wire $5\do_icreset$next[0:0]$3343 + attribute \src "issuer_ls180.v:49959.3-49988.6" + wire $5\do_reset$next[0:0]$3336 + attribute \src "issuer_ls180.v:49929.3-49958.6" + wire $5\do_step$next[0:0]$3329 + attribute \src "issuer_ls180.v:49754.3-49797.6" + wire $5\stopping$next[0:0]$3299 + attribute \src "issuer_ls180.v:49704.3-49753.6" + wire $5\terminated$next[0:0]$3289 + attribute \src "issuer_ls180.v:49754.3-49797.6" + wire $6\stopping$next[0:0]$3300 + attribute \src "issuer_ls180.v:49704.3-49753.6" + wire $6\terminated$next[0:0]$3290 + attribute \src "issuer_ls180.v:49754.3-49797.6" + wire $7\stopping$next[0:0]$3301 + attribute \src "issuer_ls180.v:49704.3-49753.6" + wire $7\terminated$next[0:0]$3291 + attribute \src "issuer_ls180.v:49704.3-49753.6" + wire $8\terminated$next[0:0]$3292 + attribute \src "issuer_ls180.v:49592.19-49592.110" + wire width 3 $add$issuer_ls180.v:49592$3214_Y + attribute \src "issuer_ls180.v:49583.17-49583.109" + wire $and$issuer_ls180.v:49583$3205_Y + attribute \src "issuer_ls180.v:49586.19-49586.103" + wire $and$issuer_ls180.v:49586$3208_Y + attribute \src "issuer_ls180.v:49588.19-49588.113" + wire $and$issuer_ls180.v:49588$3210_Y + attribute \src "issuer_ls180.v:49595.19-49595.103" + wire $and$issuer_ls180.v:49595$3217_Y + attribute \src "issuer_ls180.v:49597.19-49597.102" + wire $and$issuer_ls180.v:49597$3219_Y + attribute \src "issuer_ls180.v:49602.18-49602.101" + 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\$87 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:192" + wire \$89 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:226" + wire \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:226" + wire \$91 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:226" + wire \$93 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:199" + wire \$95 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:215" + wire \$97 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:219" + wire \$99 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:140" + wire input 24 \clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:9" + wire width 64 input 4 \core_dbg_msr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:8" + wire width 64 input 3 \core_dbg_pc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:90" + wire output 1 \core_rst_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:89" + wire output 5 \core_stop_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:95" + wire input 6 \core_stopped_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:69" + wire input 13 \d_cr_ack + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:71" + wire width 64 input 12 \d_cr_data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:68" + wire output 11 \d_cr_req + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:69" + wire input 10 \d_gpr_ack + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:70" + wire width 7 output 8 \d_gpr_addr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:71" + wire width 64 input 9 \d_gpr_data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:68" + wire output 7 \d_gpr_req + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:69" + wire input 16 \d_xer_ack + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:71" + wire width 64 input 15 \d_xer_data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:68" + wire output 14 \d_xer_req + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:62" + wire output 19 \dmi_ack_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:57" + wire width 4 input 18 \dmi_addr_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:58" + wire width 64 input 23 \dmi_din + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:59" + wire width 64 output 21 \dmi_dout + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:140" + wire \dmi_read_log_data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:140" + wire \dmi_read_log_data$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:141" + wire \dmi_read_log_data_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:141" + wire \dmi_read_log_data_1$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:60" + wire input 20 \dmi_req_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:123" + wire \dmi_req_i_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:123" + wire \dmi_req_i_1$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:61" + wire input 22 \dmi_we_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:139" + wire \do_dmi_log_rd + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:139" + wire \do_dmi_log_rd$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:132" + wire \do_icreset + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:132" + wire \do_icreset$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:131" + wire \do_reset + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:131" + wire \do_reset$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:130" + wire \do_step + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:130" + wire \do_step$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:135" + wire width 7 \gspr_index + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:135" + wire width 7 \gspr_index$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:91" + wire \icache_rst_o + attribute \src "issuer_ls180.v:49349.7-49349.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:137" + wire width 32 \log_dmi_addr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:137" + wire width 32 \log_dmi_addr$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:138" + wire width 64 \log_dmi_data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:111" + wire width 32 \log_write_addr_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:140" + wire input 17 \rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:126" + wire width 64 \stat_reg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:129" + wire \stopping + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:129" + wire \stopping$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:94" + wire input 2 \terminate_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:133" + wire \terminated + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:133" + wire \terminated$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:114" + wire \terminated_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:229" + cell $add $add$issuer_ls180.v:49592$3214 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 3 + connect \A \log_dmi_addr [1:0] + connect \B 1'1 + connect \Y $add$issuer_ls180.v:49592$3214_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:226" + cell $and $and$issuer_ls180.v:49583$3205 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dmi_read_log_data_1 + connect \B \$7 + connect \Y $and$issuer_ls180.v:49583$3205_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:192" + cell $and $and$issuer_ls180.v:49586$3208 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dmi_req_i + connect \B \$101 + connect \Y $and$issuer_ls180.v:49586$3208_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:226" + cell $and $and$issuer_ls180.v:49588$3210 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dmi_read_log_data_1 + connect \B \$105 + connect \Y $and$issuer_ls180.v:49588$3210_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:234" + cell $and $and$issuer_ls180.v:49595$3217 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dmi_req_i + connect \B \$118 + connect \Y $and$issuer_ls180.v:49595$3217_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:246" + cell $and $and$issuer_ls180.v:49597$3219 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \stopping + connect \B \$122 + connect \Y $and$issuer_ls180.v:49597$3219_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:192" + cell $and $and$issuer_ls180.v:49602$3224 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dmi_req_i + connect \B \$17 + connect \Y $and$issuer_ls180.v:49602$3224_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:226" + cell $and $and$issuer_ls180.v:49604$3226 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dmi_read_log_data_1 + connect \B \$21 + connect \Y $and$issuer_ls180.v:49604$3226_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:192" + cell $and $and$issuer_ls180.v:49609$3231 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dmi_req_i + connect \B \$31 + connect \Y $and$issuer_ls180.v:49609$3231_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:226" + cell $and $and$issuer_ls180.v:49611$3233 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dmi_read_log_data_1 + connect \B \$35 + connect \Y $and$issuer_ls180.v:49611$3233_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:192" + cell $and $and$issuer_ls180.v:49617$3239 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dmi_req_i + connect \B \$45 + connect \Y $and$issuer_ls180.v:49617$3239_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:226" + cell $and $and$issuer_ls180.v:49619$3241 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dmi_read_log_data_1 + connect \B \$49 + connect \Y $and$issuer_ls180.v:49619$3241_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:192" + cell $and $and$issuer_ls180.v:49623$3245 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dmi_req_i + connect \B \$3 + connect \Y $and$issuer_ls180.v:49623$3245_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:192" + cell $and $and$issuer_ls180.v:49625$3247 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dmi_req_i + connect \B \$59 + connect \Y $and$issuer_ls180.v:49625$3247_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:226" + cell $and $and$issuer_ls180.v:49627$3249 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dmi_read_log_data_1 + connect \B \$63 + connect \Y $and$issuer_ls180.v:49627$3249_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:192" + cell $and $and$issuer_ls180.v:49632$3254 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dmi_req_i + connect \B \$73 + connect \Y $and$issuer_ls180.v:49632$3254_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:226" + cell $and $and$issuer_ls180.v:49635$3257 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dmi_read_log_data_1 + connect \B \$77 + connect \Y $and$issuer_ls180.v:49635$3257_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:192" + cell $and $and$issuer_ls180.v:49640$3262 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dmi_req_i + connect \B \$87 + connect \Y $and$issuer_ls180.v:49640$3262_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:226" + cell $and $and$issuer_ls180.v:49642$3264 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dmi_read_log_data_1 + connect \B \$91 + connect \Y $and$issuer_ls180.v:49642$3264_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:219" + cell $eq $eq$issuer_ls180.v:49584$3206 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \dmi_addr_i + connect \B 3'110 + connect \Y $eq$issuer_ls180.v:49584$3206_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:199" + cell $eq $eq$issuer_ls180.v:49589$3211 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dmi_addr_i + connect \B 1'0 + connect \Y $eq$issuer_ls180.v:49589$3211_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:215" + cell $eq $eq$issuer_ls180.v:49590$3212 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \dmi_addr_i + connect \B 3'100 + connect \Y $eq$issuer_ls180.v:49590$3212_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:219" + cell $eq $eq$issuer_ls180.v:49591$3213 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \dmi_addr_i + connect \B 3'110 + connect \Y $eq$issuer_ls180.v:49591$3213_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:234" + cell $eq $eq$issuer_ls180.v:49593$3215 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \dmi_addr_i + connect \B 3'111 + connect \Y $eq$issuer_ls180.v:49593$3215_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:199" + cell $eq $eq$issuer_ls180.v:49594$3216 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dmi_addr_i + connect \B 1'0 + connect \Y $eq$issuer_ls180.v:49594$3216_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:215" + cell $eq $eq$issuer_ls180.v:49598$3220 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \dmi_addr_i + connect \B 3'100 + connect \Y $eq$issuer_ls180.v:49598$3220_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:219" + cell $eq $eq$issuer_ls180.v:49599$3221 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \dmi_addr_i + connect \B 3'110 + connect \Y $eq$issuer_ls180.v:49599$3221_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:199" + cell $eq $eq$issuer_ls180.v:49605$3227 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dmi_addr_i + connect \B 1'0 + connect \Y $eq$issuer_ls180.v:49605$3227_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:215" + cell $eq $eq$issuer_ls180.v:49606$3228 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \dmi_addr_i + connect \B 3'100 + connect \Y $eq$issuer_ls180.v:49606$3228_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:219" + cell $eq $eq$issuer_ls180.v:49607$3229 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \dmi_addr_i + connect \B 3'110 + connect \Y $eq$issuer_ls180.v:49607$3229_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:199" + cell $eq $eq$issuer_ls180.v:49613$3235 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dmi_addr_i + connect \B 1'0 + connect \Y $eq$issuer_ls180.v:49613$3235_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:215" + cell $eq $eq$issuer_ls180.v:49614$3236 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \dmi_addr_i + connect \B 3'100 + connect \Y $eq$issuer_ls180.v:49614$3236_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:219" + cell $eq $eq$issuer_ls180.v:49615$3237 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \dmi_addr_i + connect \B 3'110 + connect \Y $eq$issuer_ls180.v:49615$3237_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:199" + cell $eq $eq$issuer_ls180.v:49620$3242 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dmi_addr_i + connect \B 1'0 + connect \Y $eq$issuer_ls180.v:49620$3242_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:215" + cell $eq $eq$issuer_ls180.v:49621$3243 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \dmi_addr_i + connect \B 3'100 + connect \Y $eq$issuer_ls180.v:49621$3243_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:219" + cell $eq $eq$issuer_ls180.v:49622$3244 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \dmi_addr_i + connect \B 3'110 + connect \Y $eq$issuer_ls180.v:49622$3244_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:199" + cell $eq $eq$issuer_ls180.v:49628$3250 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dmi_addr_i + connect \B 1'0 + connect \Y $eq$issuer_ls180.v:49628$3250_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:215" + cell $eq $eq$issuer_ls180.v:49629$3251 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \dmi_addr_i + connect \B 3'100 + connect \Y $eq$issuer_ls180.v:49629$3251_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:219" + cell $eq $eq$issuer_ls180.v:49630$3252 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \dmi_addr_i + connect \B 3'110 + connect \Y $eq$issuer_ls180.v:49630$3252_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:199" + cell $eq $eq$issuer_ls180.v:49636$3258 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dmi_addr_i + connect \B 1'0 + connect \Y $eq$issuer_ls180.v:49636$3258_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:215" + cell $eq $eq$issuer_ls180.v:49637$3259 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \dmi_addr_i + connect \B 3'100 + connect \Y $eq$issuer_ls180.v:49637$3259_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:219" + cell $eq $eq$issuer_ls180.v:49638$3260 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \dmi_addr_i + connect \B 3'110 + connect \Y $eq$issuer_ls180.v:49638$3260_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:199" + cell $eq $eq$issuer_ls180.v:49643$3265 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dmi_addr_i + connect \B 1'0 + connect \Y $eq$issuer_ls180.v:49643$3265_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:215" + cell $eq $eq$issuer_ls180.v:49644$3266 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \dmi_addr_i + connect \B 3'100 + connect \Y $eq$issuer_ls180.v:49644$3266_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:192" + cell $not $not$issuer_ls180.v:49585$3207 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dmi_req_i_1 + connect \Y $not$issuer_ls180.v:49585$3207_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:226" + cell $not $not$issuer_ls180.v:49587$3209 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dmi_read_log_data + connect \Y $not$issuer_ls180.v:49587$3209_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:246" + cell $not $not$issuer_ls180.v:49596$3218 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \do_step + connect \Y $not$issuer_ls180.v:49596$3218_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:192" + cell $not $not$issuer_ls180.v:49600$3222 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dmi_req_i_1 + connect \Y $not$issuer_ls180.v:49600$3222_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:226" + cell $not $not$issuer_ls180.v:49603$3225 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dmi_read_log_data + connect \Y $not$issuer_ls180.v:49603$3225_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:192" + cell $not $not$issuer_ls180.v:49608$3230 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dmi_req_i_1 + connect \Y $not$issuer_ls180.v:49608$3230_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:226" + cell $not $not$issuer_ls180.v:49610$3232 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dmi_read_log_data + connect \Y $not$issuer_ls180.v:49610$3232_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:192" + cell $not $not$issuer_ls180.v:49612$3234 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dmi_req_i_1 + connect \Y $not$issuer_ls180.v:49612$3234_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:192" + cell $not $not$issuer_ls180.v:49616$3238 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dmi_req_i_1 + connect \Y $not$issuer_ls180.v:49616$3238_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:226" + cell $not $not$issuer_ls180.v:49618$3240 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dmi_read_log_data + connect \Y $not$issuer_ls180.v:49618$3240_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:192" + cell $not $not$issuer_ls180.v:49624$3246 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dmi_req_i_1 + connect \Y $not$issuer_ls180.v:49624$3246_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:226" + cell $not $not$issuer_ls180.v:49626$3248 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dmi_read_log_data + connect \Y $not$issuer_ls180.v:49626$3248_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:192" + cell $not $not$issuer_ls180.v:49631$3253 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dmi_req_i_1 + connect \Y $not$issuer_ls180.v:49631$3253_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:226" + cell $not $not$issuer_ls180.v:49633$3255 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dmi_read_log_data + connect \Y $not$issuer_ls180.v:49633$3255_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:226" + cell $not $not$issuer_ls180.v:49634$3256 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dmi_read_log_data + connect \Y $not$issuer_ls180.v:49634$3256_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:192" + cell $not $not$issuer_ls180.v:49639$3261 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dmi_req_i_1 + connect \Y $not$issuer_ls180.v:49639$3261_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:226" + cell $not $not$issuer_ls180.v:49641$3263 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dmi_read_log_data + connect \Y $not$issuer_ls180.v:49641$3263_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:162" + cell $pos $pos$issuer_ls180.v:49601$3223 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A { 61'0000000000000000000000000000000000000000000000000000000000000 \terminated \core_stopped_i \stopping } + connect \Y $pos$issuer_ls180.v:49601$3223_Y + end + attribute \src "issuer_ls180.v:49349.7-49349.20" + process $proc$issuer_ls180.v:49349$3350 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "issuer_ls180.v:49522.7-49522.31" + process $proc$issuer_ls180.v:49522$3351 + assign { } { } + assign $1\dmi_read_log_data[0:0] 1'0 + sync always + sync init + update \dmi_read_log_data $1\dmi_read_log_data[0:0] + end + attribute \src "issuer_ls180.v:49526.7-49526.33" + process $proc$issuer_ls180.v:49526$3352 + assign { } { } + assign $1\dmi_read_log_data_1[0:0] 1'0 + sync always + sync init + update \dmi_read_log_data_1 $1\dmi_read_log_data_1[0:0] + end + attribute \src "issuer_ls180.v:49532.7-49532.25" + process $proc$issuer_ls180.v:49532$3353 + assign { } { } + assign $1\dmi_req_i_1[0:0] 1'0 + sync always + sync init + update \dmi_req_i_1 $1\dmi_req_i_1[0:0] + end + attribute \src "issuer_ls180.v:49538.7-49538.27" + process $proc$issuer_ls180.v:49538$3354 + assign { } { } + assign $1\do_dmi_log_rd[0:0] 1'0 + sync always + sync init + update \do_dmi_log_rd $1\do_dmi_log_rd[0:0] + end + attribute \src "issuer_ls180.v:49542.7-49542.24" + process $proc$issuer_ls180.v:49542$3355 + assign { } { } + assign $1\do_icreset[0:0] 1'0 + sync always + sync init + update \do_icreset $1\do_icreset[0:0] + end + attribute \src "issuer_ls180.v:49546.7-49546.22" + process $proc$issuer_ls180.v:49546$3356 + assign { } { } + assign $1\do_reset[0:0] 1'0 + sync always + sync init + update \do_reset $1\do_reset[0:0] + end + attribute \src "issuer_ls180.v:49550.7-49550.21" + process $proc$issuer_ls180.v:49550$3357 + assign { } { } + assign $1\do_step[0:0] 1'0 + sync always + sync init + update \do_step $1\do_step[0:0] + end + attribute \src "issuer_ls180.v:49554.13-49554.31" + process $proc$issuer_ls180.v:49554$3358 + assign { } { } + assign $1\gspr_index[6:0] 7'0000000 + sync always + sync init + update \gspr_index $1\gspr_index[6:0] + end + attribute \src "issuer_ls180.v:49560.14-49560.34" + process $proc$issuer_ls180.v:49560$3359 + assign { } { } + assign $1\log_dmi_addr[31:0] 0 + sync always + sync init + update \log_dmi_addr $1\log_dmi_addr[31:0] + end + attribute \src "issuer_ls180.v:49572.7-49572.22" + process $proc$issuer_ls180.v:49572$3360 + assign { } { } + assign $1\stopping[0:0] 1'0 + sync always + sync init + update \stopping $1\stopping[0:0] + end + attribute \src "issuer_ls180.v:49578.7-49578.24" + process $proc$issuer_ls180.v:49578$3361 + assign { } { } + assign $1\terminated[0:0] 1'0 + sync always + sync init + update \terminated $1\terminated[0:0] + end + attribute \src "issuer_ls180.v:49645.3-49646.51" + process $proc$issuer_ls180.v:49645$3267 + assign { } { } + assign $0\dmi_read_log_data[0:0] \dmi_read_log_data$next + sync posedge \clk + update \dmi_read_log_data $0\dmi_read_log_data[0:0] + end + attribute \src "issuer_ls180.v:49647.3-49648.55" + process $proc$issuer_ls180.v:49647$3268 + assign { } { } + assign $0\dmi_read_log_data_1[0:0] \dmi_read_log_data_1$next + sync posedge \clk + update \dmi_read_log_data_1 $0\dmi_read_log_data_1[0:0] + end + attribute \src "issuer_ls180.v:49649.3-49650.41" + process $proc$issuer_ls180.v:49649$3269 + assign { } { } + assign $0\log_dmi_addr[31:0] \log_dmi_addr$next + sync posedge \clk + update \log_dmi_addr $0\log_dmi_addr[31:0] + end + attribute \src "issuer_ls180.v:49651.3-49652.37" + process $proc$issuer_ls180.v:49651$3270 + assign { } { } + assign $0\gspr_index[6:0] \gspr_index$next + sync posedge \clk + update \gspr_index $0\gspr_index[6:0] + end + attribute \src "issuer_ls180.v:49653.3-49654.33" + process $proc$issuer_ls180.v:49653$3271 + assign { } { } + assign $0\stopping[0:0] \stopping$next + sync posedge \clk + update \stopping $0\stopping[0:0] + end + attribute \src "issuer_ls180.v:49655.3-49656.37" + process $proc$issuer_ls180.v:49655$3272 + assign { } { } + assign $0\terminated[0:0] \terminated$next + sync posedge \clk + update \terminated $0\terminated[0:0] + end + attribute \src "issuer_ls180.v:49657.3-49658.39" + process $proc$issuer_ls180.v:49657$3273 + assign { } { } + assign $0\dmi_req_i_1[0:0] \dmi_req_i_1$next + sync posedge \clk + update \dmi_req_i_1 $0\dmi_req_i_1[0:0] + end + attribute \src "issuer_ls180.v:49659.3-49660.43" + process $proc$issuer_ls180.v:49659$3274 + assign { } { } + assign $0\do_dmi_log_rd[0:0] \do_dmi_log_rd$next + sync posedge \clk + update \do_dmi_log_rd $0\do_dmi_log_rd[0:0] + end + attribute \src "issuer_ls180.v:49661.3-49662.37" + process $proc$issuer_ls180.v:49661$3275 + assign { } { } + assign $0\do_icreset[0:0] \do_icreset$next + sync posedge \clk + update \do_icreset $0\do_icreset[0:0] + end + attribute \src "issuer_ls180.v:49663.3-49664.33" + process $proc$issuer_ls180.v:49663$3276 + assign { } { } + assign $0\do_reset[0:0] \do_reset$next + sync posedge \clk + update \do_reset $0\do_reset[0:0] + end + attribute \src "issuer_ls180.v:49665.3-49666.31" + process $proc$issuer_ls180.v:49665$3277 + assign { } { } + assign $0\do_step[0:0] \do_step$next + sync posedge \clk + update \do_step $0\do_step[0:0] + end + attribute \src "issuer_ls180.v:49667.3-49684.6" + process $proc$issuer_ls180.v:49667$3278 + assign { } { } + assign $0\dmi_ack_o[0:0] $1\dmi_ack_o[0:0] + attribute \src "issuer_ls180.v:49668.5-49668.29" + switch \initial + attribute \src "issuer_ls180.v:49668.9-49668.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:146" + switch \dmi_addr_i + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0101 + assign { } { } + assign $1\dmi_ack_o[0:0] \d_gpr_ack + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\dmi_ack_o[0:0] \d_cr_ack + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'1001 + assign { } { } + assign $1\dmi_ack_o[0:0] \d_xer_ack + attribute \src "issuer_ls180.v:0.0-0.0" + case + assign { } { } + assign $1\dmi_ack_o[0:0] \dmi_req_i + end + sync always + update \dmi_ack_o $0\dmi_ack_o[0:0] + end + attribute \src "issuer_ls180.v:49685.3-49694.6" + process $proc$issuer_ls180.v:49685$3279 + assign { } { } + assign { } { } + assign $0\d_gpr_req[0:0] $1\d_gpr_req[0:0] + attribute \src "issuer_ls180.v:49686.5-49686.29" + switch \initial + attribute \src "issuer_ls180.v:49686.9-49686.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:146" + switch \dmi_addr_i + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0101 + assign { } { } + assign $1\d_gpr_req[0:0] \dmi_req_i + case + assign $1\d_gpr_req[0:0] 1'0 + end + sync always + update \d_gpr_req $0\d_gpr_req[0:0] + end + attribute \src "issuer_ls180.v:49695.3-49703.6" + process $proc$issuer_ls180.v:49695$3280 + assign { } { } + assign { } { } + assign $0\dmi_req_i_1$next[0:0]$3281 $1\dmi_req_i_1$next[0:0]$3282 + attribute \src "issuer_ls180.v:49696.5-49696.29" + switch \initial + attribute \src "issuer_ls180.v:49696.9-49696.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dmi_req_i_1$next[0:0]$3282 1'0 + case + assign $1\dmi_req_i_1$next[0:0]$3282 \dmi_req_i + end + sync always + update \dmi_req_i_1$next $0\dmi_req_i_1$next[0:0]$3281 + end + attribute \src "issuer_ls180.v:49704.3-49753.6" + process $proc$issuer_ls180.v:49704$3283 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\terminated$next[0:0]$3284 $8\terminated$next[0:0]$3292 + attribute \src "issuer_ls180.v:49705.5-49705.29" + switch \initial + attribute \src "issuer_ls180.v:49705.9-49705.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:192" + switch { \$65 \$61 } + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\terminated$next[0:0]$3285 $2\terminated$next[0:0]$3286 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:193" + switch \dmi_we_i + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\terminated$next[0:0]$3286 $3\terminated$next[0:0]$3287 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:199" + switch { \$71 \$69 \$67 } + attribute \src "issuer_ls180.v:0.0-0.0" + case 3'--1 + assign { } { } + assign { } { } + assign { } { } + assign $3\terminated$next[0:0]$3287 $6\terminated$next[0:0]$3290 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200" + switch \dmi_din [1] + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\terminated$next[0:0]$3288 1'0 + case + assign $4\terminated$next[0:0]$3288 \terminated + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:205" + switch \dmi_din [3] + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\terminated$next[0:0]$3289 1'0 + case + assign $5\terminated$next[0:0]$3289 $4\terminated$next[0:0]$3288 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:210" + switch \dmi_din [4] + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $6\terminated$next[0:0]$3290 1'0 + case + assign $6\terminated$next[0:0]$3290 $5\terminated$next[0:0]$3289 + end + case + assign $3\terminated$next[0:0]$3287 \terminated + end + case + assign $2\terminated$next[0:0]$3286 \terminated + end + case + assign $1\terminated$next[0:0]$3285 \terminated + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:239" + switch \terminate_i + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $7\terminated$next[0:0]$3291 1'1 + case + assign $7\terminated$next[0:0]$3291 $1\terminated$next[0:0]$3285 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $8\terminated$next[0:0]$3292 1'0 + case + assign $8\terminated$next[0:0]$3292 $7\terminated$next[0:0]$3291 + end + sync always + update \terminated$next $0\terminated$next[0:0]$3284 + end + attribute \src "issuer_ls180.v:49754.3-49797.6" + process $proc$issuer_ls180.v:49754$3293 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\stopping$next[0:0]$3294 $7\stopping$next[0:0]$3301 + attribute \src "issuer_ls180.v:49755.5-49755.29" + switch \initial + attribute \src "issuer_ls180.v:49755.9-49755.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:192" + switch { \$79 \$75 } + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\stopping$next[0:0]$3295 $2\stopping$next[0:0]$3296 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:193" + switch \dmi_we_i + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\stopping$next[0:0]$3296 $3\stopping$next[0:0]$3297 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:199" + switch { \$85 \$83 \$81 } + attribute \src "issuer_ls180.v:0.0-0.0" + case 3'--1 + assign { } { } + assign { } { } + assign $3\stopping$next[0:0]$3297 $5\stopping$next[0:0]$3299 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:203" + switch \dmi_din [0] + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\stopping$next[0:0]$3298 1'1 + case + assign $4\stopping$next[0:0]$3298 \stopping + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:210" + switch \dmi_din [4] + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\stopping$next[0:0]$3299 1'0 + case + assign $5\stopping$next[0:0]$3299 $4\stopping$next[0:0]$3298 + end + case + assign $3\stopping$next[0:0]$3297 \stopping + end + case + assign $2\stopping$next[0:0]$3296 \stopping + end + case + assign $1\stopping$next[0:0]$3295 \stopping + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:239" + switch \terminate_i + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $6\stopping$next[0:0]$3300 1'1 + case + assign $6\stopping$next[0:0]$3300 $1\stopping$next[0:0]$3295 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $7\stopping$next[0:0]$3301 1'0 + case + assign $7\stopping$next[0:0]$3301 $6\stopping$next[0:0]$3300 + end + sync always + update \stopping$next $0\stopping$next[0:0]$3294 + end + attribute \src "issuer_ls180.v:49798.3-49825.6" + process $proc$issuer_ls180.v:49798$3302 + assign { } { } + assign { } { } + assign { } { } + assign $0\gspr_index$next[6:0]$3303 $4\gspr_index$next[6:0]$3307 + attribute \src "issuer_ls180.v:49799.5-49799.29" + switch \initial + attribute \src "issuer_ls180.v:49799.9-49799.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:192" + switch { \$93 \$89 } + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\gspr_index$next[6:0]$3304 $2\gspr_index$next[6:0]$3305 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:193" + switch \dmi_we_i + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\gspr_index$next[6:0]$3305 $3\gspr_index$next[6:0]$3306 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:199" + switch { \$99 \$97 \$95 } + attribute \src "issuer_ls180.v:0.0-0.0" + case 3'--1 + assign $3\gspr_index$next[6:0]$3306 \gspr_index + attribute \src "issuer_ls180.v:0.0-0.0" + case 3'-1- + assign { } { } + assign $3\gspr_index$next[6:0]$3306 \dmi_din [6:0] + case + assign $3\gspr_index$next[6:0]$3306 \gspr_index + end + case + assign $2\gspr_index$next[6:0]$3305 \gspr_index + end + case + assign $1\gspr_index$next[6:0]$3304 \gspr_index + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\gspr_index$next[6:0]$3307 7'0000000 + case + assign $4\gspr_index$next[6:0]$3307 $1\gspr_index$next[6:0]$3304 + end + sync always + update \gspr_index$next $0\gspr_index$next[6:0]$3303 + end + attribute \src "issuer_ls180.v:49826.3-49859.6" + process $proc$issuer_ls180.v:49826$3308 + assign { } { } + assign { } { } + assign { } { } + assign $0\log_dmi_addr$next[31:0]$3309 $4\log_dmi_addr$next[31:0]$3313 + attribute \src "issuer_ls180.v:49827.5-49827.29" + switch \initial + attribute \src "issuer_ls180.v:49827.9-49827.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:192" + switch { \$107 \$103 } + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\log_dmi_addr$next[31:0]$3310 $2\log_dmi_addr$next[31:0]$3311 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:193" + switch \dmi_we_i + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\log_dmi_addr$next[31:0]$3311 $3\log_dmi_addr$next[31:0]$3312 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:199" + switch { \$113 \$111 \$109 } + attribute \src "issuer_ls180.v:0.0-0.0" + case 3'--1 + assign $3\log_dmi_addr$next[31:0]$3312 \log_dmi_addr + attribute \src "issuer_ls180.v:0.0-0.0" + case 3'-1- + assign $3\log_dmi_addr$next[31:0]$3312 \log_dmi_addr + attribute \src "issuer_ls180.v:0.0-0.0" + case 3'1-- + assign { } { } + assign $3\log_dmi_addr$next[31:0]$3312 \dmi_din [31:0] + case + assign $3\log_dmi_addr$next[31:0]$3312 \log_dmi_addr + end + case + assign $2\log_dmi_addr$next[31:0]$3311 \log_dmi_addr + end + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'1- + assign $1\log_dmi_addr$next[31:0]$3310 [31:2] \log_dmi_addr [31:2] + assign $1\log_dmi_addr$next[31:0]$3310 [1:0] \$115 [1:0] + case + assign $1\log_dmi_addr$next[31:0]$3310 \log_dmi_addr + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\log_dmi_addr$next[31:0]$3313 0 + case + assign $4\log_dmi_addr$next[31:0]$3313 $1\log_dmi_addr$next[31:0]$3310 + end + sync always + update \log_dmi_addr$next $0\log_dmi_addr$next[31:0]$3309 + end + attribute \src "issuer_ls180.v:49860.3-49868.6" + process $proc$issuer_ls180.v:49860$3314 + assign { } { } + assign { } { } + assign $0\dmi_read_log_data_1$next[0:0]$3315 $1\dmi_read_log_data_1$next[0:0]$3316 + attribute \src "issuer_ls180.v:49861.5-49861.29" + switch \initial + attribute \src "issuer_ls180.v:49861.9-49861.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dmi_read_log_data_1$next[0:0]$3316 1'0 + case + assign $1\dmi_read_log_data_1$next[0:0]$3316 \dmi_read_log_data + end + sync always + update \dmi_read_log_data_1$next $0\dmi_read_log_data_1$next[0:0]$3315 + end + attribute \src "issuer_ls180.v:49869.3-49877.6" + process $proc$issuer_ls180.v:49869$3317 + assign { } { } + assign { } { } + assign $0\dmi_read_log_data$next[0:0]$3318 $1\dmi_read_log_data$next[0:0]$3319 + attribute \src "issuer_ls180.v:49870.5-49870.29" + switch \initial + attribute \src "issuer_ls180.v:49870.9-49870.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dmi_read_log_data$next[0:0]$3319 1'0 + case + assign $1\dmi_read_log_data$next[0:0]$3319 \$120 + end + sync always + update \dmi_read_log_data$next $0\dmi_read_log_data$next[0:0]$3318 + end + attribute \src "issuer_ls180.v:49878.3-49887.6" + process $proc$issuer_ls180.v:49878$3320 + assign { } { } + assign { } { } + assign $0\d_cr_req[0:0] $1\d_cr_req[0:0] + attribute \src "issuer_ls180.v:49879.5-49879.29" + switch \initial + attribute \src "issuer_ls180.v:49879.9-49879.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:146" + switch \dmi_addr_i + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\d_cr_req[0:0] \dmi_req_i + case + assign $1\d_cr_req[0:0] 1'0 + end + sync always + update \d_cr_req $0\d_cr_req[0:0] + end + attribute \src "issuer_ls180.v:49888.3-49897.6" + process $proc$issuer_ls180.v:49888$3321 + assign { } { } + assign { } { } + assign $0\d_xer_req[0:0] $1\d_xer_req[0:0] + attribute \src "issuer_ls180.v:49889.5-49889.29" + switch \initial + attribute \src "issuer_ls180.v:49889.9-49889.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:146" + switch \dmi_addr_i + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'1001 + assign { } { } + assign $1\d_xer_req[0:0] \dmi_req_i + case + assign $1\d_xer_req[0:0] 1'0 + end + sync always + update \d_xer_req $0\d_xer_req[0:0] + end + attribute \src "issuer_ls180.v:49898.3-49928.6" + process $proc$issuer_ls180.v:49898$3322 + assign { } { } + assign { } { } + assign $0\dmi_dout[63:0] $1\dmi_dout[63:0] + attribute \src "issuer_ls180.v:49899.5-49899.29" + switch \initial + attribute \src "issuer_ls180.v:49899.9-49899.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:165" + switch \dmi_addr_i + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0001 + assign { } { } + assign $1\dmi_dout[63:0] \stat_reg + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0010 + assign { } { } + assign $1\dmi_dout[63:0] \core_dbg_pc + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0011 + assign { } { } + assign $1\dmi_dout[63:0] \core_dbg_msr + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0101 + assign { } { } + assign $1\dmi_dout[63:0] \d_gpr_data + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\dmi_dout[63:0] { \log_write_addr_o \log_dmi_addr } + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $1\dmi_dout[63:0] \log_dmi_data + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\dmi_dout[63:0] \d_cr_data + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'1001 + assign { } { } + assign $1\dmi_dout[63:0] \d_xer_data + case + assign $1\dmi_dout[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \dmi_dout $0\dmi_dout[63:0] + end + attribute \src "issuer_ls180.v:49929.3-49958.6" + process $proc$issuer_ls180.v:49929$3323 + assign { } { } + assign { } { } + assign { } { } + assign $0\do_step$next[0:0]$3324 $5\do_step$next[0:0]$3329 + attribute \src "issuer_ls180.v:49930.5-49930.29" + switch \initial + attribute \src "issuer_ls180.v:49930.9-49930.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:192" + switch { \$9 \$5 } + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\do_step$next[0:0]$3325 $2\do_step$next[0:0]$3326 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:193" + switch \dmi_we_i + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\do_step$next[0:0]$3326 $3\do_step$next[0:0]$3327 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:199" + switch { \$15 \$13 \$11 } + attribute \src "issuer_ls180.v:0.0-0.0" + case 3'--1 + assign { } { } + assign $3\do_step$next[0:0]$3327 $4\do_step$next[0:0]$3328 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:205" + switch \dmi_din [3] + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\do_step$next[0:0]$3328 1'1 + case + assign $4\do_step$next[0:0]$3328 1'0 + end + case + assign $3\do_step$next[0:0]$3327 1'0 + end + case + assign $2\do_step$next[0:0]$3326 1'0 + end + case + assign $1\do_step$next[0:0]$3325 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\do_step$next[0:0]$3329 1'0 + case + assign $5\do_step$next[0:0]$3329 $1\do_step$next[0:0]$3325 + end + sync always + update \do_step$next $0\do_step$next[0:0]$3324 + end + attribute \src "issuer_ls180.v:49959.3-49988.6" + process $proc$issuer_ls180.v:49959$3330 + assign { } { } + assign { } { } + assign { } { } + assign $0\do_reset$next[0:0]$3331 $5\do_reset$next[0:0]$3336 + attribute \src "issuer_ls180.v:49960.5-49960.29" + switch \initial + attribute \src "issuer_ls180.v:49960.9-49960.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:192" + switch { \$23 \$19 } + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\do_reset$next[0:0]$3332 $2\do_reset$next[0:0]$3333 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:193" + switch \dmi_we_i + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\do_reset$next[0:0]$3333 $3\do_reset$next[0:0]$3334 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:199" + switch { \$29 \$27 \$25 } + attribute \src "issuer_ls180.v:0.0-0.0" + case 3'--1 + assign { } { } + assign $3\do_reset$next[0:0]$3334 $4\do_reset$next[0:0]$3335 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200" + switch \dmi_din [1] + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\do_reset$next[0:0]$3335 1'1 + case + assign $4\do_reset$next[0:0]$3335 1'0 + end + case + assign $3\do_reset$next[0:0]$3334 1'0 + end + case + assign $2\do_reset$next[0:0]$3333 1'0 + end + case + assign $1\do_reset$next[0:0]$3332 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\do_reset$next[0:0]$3336 1'0 + case + assign $5\do_reset$next[0:0]$3336 $1\do_reset$next[0:0]$3332 + end + sync always + update \do_reset$next $0\do_reset$next[0:0]$3331 + end + attribute \src "issuer_ls180.v:49989.3-50018.6" + process $proc$issuer_ls180.v:49989$3337 + assign { } { } + assign { } { } + assign { } { } + assign $0\do_icreset$next[0:0]$3338 $5\do_icreset$next[0:0]$3343 + attribute \src "issuer_ls180.v:49990.5-49990.29" + switch \initial + attribute \src "issuer_ls180.v:49990.9-49990.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:192" + switch { \$37 \$33 } + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\do_icreset$next[0:0]$3339 $2\do_icreset$next[0:0]$3340 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:193" + switch \dmi_we_i + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\do_icreset$next[0:0]$3340 $3\do_icreset$next[0:0]$3341 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:199" + switch { \$43 \$41 \$39 } + attribute \src "issuer_ls180.v:0.0-0.0" + case 3'--1 + assign { } { } + assign $3\do_icreset$next[0:0]$3341 $4\do_icreset$next[0:0]$3342 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:208" + switch \dmi_din [2] + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\do_icreset$next[0:0]$3342 1'1 + case + assign $4\do_icreset$next[0:0]$3342 1'0 + end + case + assign $3\do_icreset$next[0:0]$3341 1'0 + end + case + assign $2\do_icreset$next[0:0]$3340 1'0 + end + case + assign $1\do_icreset$next[0:0]$3339 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\do_icreset$next[0:0]$3343 1'0 + case + assign $5\do_icreset$next[0:0]$3343 $1\do_icreset$next[0:0]$3339 + end + sync always + update \do_icreset$next $0\do_icreset$next[0:0]$3338 + end + attribute \src "issuer_ls180.v:50019.3-50052.6" + process $proc$issuer_ls180.v:50019$3344 + assign { } { } + assign { } { } + assign { } { } + assign $0\do_dmi_log_rd$next[0:0]$3345 $4\do_dmi_log_rd$next[0:0]$3349 + attribute \src "issuer_ls180.v:50020.5-50020.29" + switch \initial + attribute \src "issuer_ls180.v:50020.9-50020.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:192" + switch { \$51 \$47 } + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\do_dmi_log_rd$next[0:0]$3346 $2\do_dmi_log_rd$next[0:0]$3347 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:193" + switch \dmi_we_i + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\do_dmi_log_rd$next[0:0]$3347 $3\do_dmi_log_rd$next[0:0]$3348 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:199" + switch { \$57 \$55 \$53 } + attribute \src "issuer_ls180.v:0.0-0.0" + case 3'--1 + assign $3\do_dmi_log_rd$next[0:0]$3348 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 3'-1- + assign $3\do_dmi_log_rd$next[0:0]$3348 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 3'1-- + assign { } { } + assign $3\do_dmi_log_rd$next[0:0]$3348 1'1 + case + assign $3\do_dmi_log_rd$next[0:0]$3348 1'0 + end + case + assign $2\do_dmi_log_rd$next[0:0]$3347 1'0 + end + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\do_dmi_log_rd$next[0:0]$3346 1'1 + case + assign $1\do_dmi_log_rd$next[0:0]$3346 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\do_dmi_log_rd$next[0:0]$3349 1'0 + case + assign $4\do_dmi_log_rd$next[0:0]$3349 $1\do_dmi_log_rd$next[0:0]$3346 + end + sync always + update \do_dmi_log_rd$next $0\do_dmi_log_rd$next[0:0]$3345 + end + connect \$9 $and$issuer_ls180.v:49583$3205_Y + connect \$99 $eq$issuer_ls180.v:49584$3206_Y + connect \$101 $not$issuer_ls180.v:49585$3207_Y + connect \$103 $and$issuer_ls180.v:49586$3208_Y + connect \$105 $not$issuer_ls180.v:49587$3209_Y + connect \$107 $and$issuer_ls180.v:49588$3210_Y + connect \$109 $eq$issuer_ls180.v:49589$3211_Y + connect \$111 $eq$issuer_ls180.v:49590$3212_Y + connect \$113 $eq$issuer_ls180.v:49591$3213_Y + connect \$116 $add$issuer_ls180.v:49592$3214_Y + connect \$118 $eq$issuer_ls180.v:49593$3215_Y + connect \$11 $eq$issuer_ls180.v:49594$3216_Y + connect \$120 $and$issuer_ls180.v:49595$3217_Y + connect \$122 $not$issuer_ls180.v:49596$3218_Y + connect \$124 $and$issuer_ls180.v:49597$3219_Y + connect \$13 $eq$issuer_ls180.v:49598$3220_Y + connect \$15 $eq$issuer_ls180.v:49599$3221_Y + connect \$17 $not$issuer_ls180.v:49600$3222_Y + connect \$1 $pos$issuer_ls180.v:49601$3223_Y + connect \$19 $and$issuer_ls180.v:49602$3224_Y + connect \$21 $not$issuer_ls180.v:49603$3225_Y + connect \$23 $and$issuer_ls180.v:49604$3226_Y + connect \$25 $eq$issuer_ls180.v:49605$3227_Y + connect \$27 $eq$issuer_ls180.v:49606$3228_Y + connect \$29 $eq$issuer_ls180.v:49607$3229_Y + connect \$31 $not$issuer_ls180.v:49608$3230_Y + connect \$33 $and$issuer_ls180.v:49609$3231_Y + connect \$35 $not$issuer_ls180.v:49610$3232_Y + connect \$37 $and$issuer_ls180.v:49611$3233_Y + connect \$3 $not$issuer_ls180.v:49612$3234_Y + connect \$39 $eq$issuer_ls180.v:49613$3235_Y + connect \$41 $eq$issuer_ls180.v:49614$3236_Y + connect \$43 $eq$issuer_ls180.v:49615$3237_Y + connect \$45 $not$issuer_ls180.v:49616$3238_Y + connect \$47 $and$issuer_ls180.v:49617$3239_Y + connect \$49 $not$issuer_ls180.v:49618$3240_Y + connect \$51 $and$issuer_ls180.v:49619$3241_Y + connect \$53 $eq$issuer_ls180.v:49620$3242_Y + connect \$55 $eq$issuer_ls180.v:49621$3243_Y + connect \$57 $eq$issuer_ls180.v:49622$3244_Y + connect \$5 $and$issuer_ls180.v:49623$3245_Y + connect \$59 $not$issuer_ls180.v:49624$3246_Y + connect \$61 $and$issuer_ls180.v:49625$3247_Y + connect \$63 $not$issuer_ls180.v:49626$3248_Y + connect \$65 $and$issuer_ls180.v:49627$3249_Y + connect \$67 $eq$issuer_ls180.v:49628$3250_Y + connect \$69 $eq$issuer_ls180.v:49629$3251_Y + connect \$71 $eq$issuer_ls180.v:49630$3252_Y + connect \$73 $not$issuer_ls180.v:49631$3253_Y + connect \$75 $and$issuer_ls180.v:49632$3254_Y + connect \$77 $not$issuer_ls180.v:49633$3255_Y + connect \$7 $not$issuer_ls180.v:49634$3256_Y + connect \$79 $and$issuer_ls180.v:49635$3257_Y + connect \$81 $eq$issuer_ls180.v:49636$3258_Y + connect \$83 $eq$issuer_ls180.v:49637$3259_Y + connect \$85 $eq$issuer_ls180.v:49638$3260_Y + connect \$87 $not$issuer_ls180.v:49639$3261_Y + connect \$89 $and$issuer_ls180.v:49640$3262_Y + connect \$91 $not$issuer_ls180.v:49641$3263_Y + connect \$93 $and$issuer_ls180.v:49642$3264_Y + connect \$95 $eq$issuer_ls180.v:49643$3265_Y + connect \$97 $eq$issuer_ls180.v:49644$3266_Y + connect \$115 \$116 + connect \log_write_addr_o 0 + connect \log_dmi_data 64'0000000000000000000000000000000000000000000000000000000000000000 + connect \terminated_o \terminated + connect \icache_rst_o \do_icreset + connect \core_rst_o \do_reset + connect \core_stop_o \$124 + connect \d_gpr_addr \gspr_index + connect \stat_reg \$1 +end +attribute \src "issuer_ls180.v:50066.1-52081.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.dec_ALU.dec" +attribute \generator "nMigen" +module \dec + attribute \src "issuer_ls180.v:51649.3-51682.6" + wire width 3 $0\ALU_cr_in[2:0] + attribute \src "issuer_ls180.v:51683.3-51716.6" + wire width 3 $0\ALU_cr_out[2:0] + attribute \src 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\ALU_BD + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 3 \ALU_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 2 \ALU_BH + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 output 30 \ALU_BI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 \ALU_BO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 output 28 \ALU_BT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 10 \ALU_CR + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 16 \ALU_D + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 14 output 31 \ALU_DS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 8 output 29 \ALU_FXM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire \ALU_L + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 24 output 22 \ALU_LI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire \ALU_LK + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 \ALU_MB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 \ALU_MB32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 \ALU_ME + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 \ALU_ME32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire output 24 \ALU_OE + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 output 17 \ALU_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 \ALU_RB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 \ALU_RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 \ALU_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire output 23 \ALU_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 \ALU_SH + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 output 20 \ALU_SH32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 16 output 18 \ALU_SI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 10 \ALU_SPR + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 \ALU_TO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 16 output 19 \ALU_UI + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 4 \ALU_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 5 \ALU_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 13 \ALU_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 14 \ALU_cry_out + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 \ALU_dec19_ALU_dec19_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 \ALU_dec19_ALU_dec19_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \ALU_dec19_ALU_dec19_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \ALU_dec19_ALU_dec19_cry_out + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 12 \ALU_dec19_ALU_dec19_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 \ALU_dec19_ALU_dec19_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 \ALU_dec19_ALU_dec19_in2_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 7 \ALU_dec19_ALU_dec19_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \ALU_dec19_ALU_dec19_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \ALU_dec19_ALU_dec19_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \ALU_dec19_ALU_dec19_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 \ALU_dec19_ALU_dec19_ldst_len + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \ALU_dec19_ALU_dec19_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \ALU_dec19_ALU_dec19_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + wire width 32 \ALU_dec19_opcode_in + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 \ALU_dec31_ALU_dec31_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 \ALU_dec31_ALU_dec31_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \ALU_dec31_ALU_dec31_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \ALU_dec31_ALU_dec31_cry_out + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 12 \ALU_dec31_ALU_dec31_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 \ALU_dec31_ALU_dec31_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 \ALU_dec31_ALU_dec31_in2_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 7 \ALU_dec31_ALU_dec31_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \ALU_dec31_ALU_dec31_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \ALU_dec31_ALU_dec31_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \ALU_dec31_ALU_dec31_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 \ALU_dec31_ALU_dec31_ldst_len + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \ALU_dec31_ALU_dec31_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \ALU_dec31_ALU_dec31_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + wire width 32 \ALU_dec31_opcode_in + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 12 output 7 \ALU_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 8 \ALU_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 output 9 \ALU_in2_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 7 output 6 \ALU_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 11 \ALU_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 12 \ALU_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 15 \ALU_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 output 10 \ALU_ldst_len + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 3 \ALU_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 16 \ALU_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 6 output 21 \ALU_sh + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \A_BC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \A_FRA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \A_FRB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \A_FRC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \A_FRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \A_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \A_RB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \A_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \A_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \A_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \B_AA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 14 \B_BD + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \B_BI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \B_BO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \B_LK + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \DQE_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \DQE_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 2 \DQE_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 12 \DQ_DQ + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 4 \DQ_PT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \DQ_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \DQ_RTp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \DQ_S + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \DQ_SX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \DQ_SX_S + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \DQ_T + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \DQ_TX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \DQ_TX_T + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 3 \DQ_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 14 \DS_DS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \DS_FRSp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \DS_FRTp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \DS_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \DS_RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \DS_RSp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \DS_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \DS_VRS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \DS_VRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 2 \DS_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \DX_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \DX_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 10 \DX_d0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 16 \DX_d0_d1_d2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \DX_d1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \DX_d2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 3 \D_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 16 \D_D + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \D_FRS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \D_FRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \D_L + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \D_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \D_RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \D_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 16 \D_SI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \D_TO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 16 \D_UI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 3 \EVS_BFA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \I_AA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 24 \I_LI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \I_LK + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \MDS_IB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \MDS_IS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \MDS_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \MDS_RB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \MDS_RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \MDS_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 4 \MDS_XBI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 4 \MDS_XBI_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 4 \MDS_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \MDS_mb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \MDS_me + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \MD_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \MD_RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \MD_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 3 \MD_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \MD_mb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \MD_me + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \MD_sh + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \M_MB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \M_ME + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \M_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \M_RB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \M_RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \M_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \M_SH + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 7 \SC_LEV + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \SC_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 2 \SC_XO_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \TX_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \TX_UI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 4 \TX_XBI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \TX_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \VA_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \VA_RB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \VA_RC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \VA_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 4 \VA_SHB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \VA_VRA + attribute \src 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"/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 4 \X_SR + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \X_SX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \X_SX_S + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_T + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 10 \X_TBR + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_TH + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_TO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \X_TX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \X_TX_T + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 4 \X_U + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_UIM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_VRS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_VRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \X_W + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 2 \X_WC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 10 \X_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 8 \X_XO_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 3 \Z22_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \Z22_DCM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \Z22_DGM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \Z22_FRA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \Z22_FRAp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \Z22_FRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \Z22_FRTp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \Z22_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \Z22_SH + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 9 \Z22_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \Z23_FRA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \Z23_FRAp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \Z23_FRB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \Z23_FRBp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \Z23_FRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \Z23_FRTp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \Z23_R + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 2 \Z23_RMC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \Z23_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \Z23_TE + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 8 \Z23_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \all_OPCD + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \all_PO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + wire input 1 \bigendian + attribute \src "issuer_ls180.v:50067.7-50067.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + wire width 32 output 2 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:320" + wire width 6 \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:442" + wire width 32 input 36 \raw_opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:478" + cell $mux $ternary$issuer_ls180.v:51240$3362 + parameter \WIDTH 32 + connect \A \raw_opcode_in + connect \B { \raw_opcode_in [7:0] \raw_opcode_in [15:8] \raw_opcode_in [23:16] \raw_opcode_in [31:24] } + connect \S \bigendian + connect \Y $ternary$issuer_ls180.v:51240$3362_Y + end + attribute \module_not_derived 1 + attribute \src "issuer_ls180.v:51241.13-51257.4" + cell \ALU_dec19 \ALU_dec19 + connect \ALU_dec19_cr_in \ALU_dec19_ALU_dec19_cr_in + connect \ALU_dec19_cr_out \ALU_dec19_ALU_dec19_cr_out + connect \ALU_dec19_cry_in \ALU_dec19_ALU_dec19_cry_in + connect \ALU_dec19_cry_out \ALU_dec19_ALU_dec19_cry_out + connect \ALU_dec19_function_unit \ALU_dec19_ALU_dec19_function_unit + connect \ALU_dec19_in1_sel \ALU_dec19_ALU_dec19_in1_sel + connect \ALU_dec19_in2_sel \ALU_dec19_ALU_dec19_in2_sel + connect \ALU_dec19_internal_op \ALU_dec19_ALU_dec19_internal_op + connect \ALU_dec19_inv_a \ALU_dec19_ALU_dec19_inv_a + connect \ALU_dec19_inv_out \ALU_dec19_ALU_dec19_inv_out + connect \ALU_dec19_is_32b \ALU_dec19_ALU_dec19_is_32b + connect \ALU_dec19_ldst_len \ALU_dec19_ALU_dec19_ldst_len + connect \ALU_dec19_rc_sel \ALU_dec19_ALU_dec19_rc_sel + connect \ALU_dec19_sgn \ALU_dec19_ALU_dec19_sgn + connect \opcode_in \ALU_dec19_opcode_in + end + attribute \module_not_derived 1 + attribute \src "issuer_ls180.v:51258.13-51274.4" + cell \ALU_dec31 \ALU_dec31 + connect \ALU_dec31_cr_in \ALU_dec31_ALU_dec31_cr_in + connect \ALU_dec31_cr_out \ALU_dec31_ALU_dec31_cr_out + connect \ALU_dec31_cry_in \ALU_dec31_ALU_dec31_cry_in + connect \ALU_dec31_cry_out \ALU_dec31_ALU_dec31_cry_out + connect \ALU_dec31_function_unit \ALU_dec31_ALU_dec31_function_unit + connect \ALU_dec31_in1_sel \ALU_dec31_ALU_dec31_in1_sel + connect \ALU_dec31_in2_sel \ALU_dec31_ALU_dec31_in2_sel + connect \ALU_dec31_internal_op \ALU_dec31_ALU_dec31_internal_op + connect \ALU_dec31_inv_a \ALU_dec31_ALU_dec31_inv_a + connect \ALU_dec31_inv_out \ALU_dec31_ALU_dec31_inv_out + connect \ALU_dec31_is_32b \ALU_dec31_ALU_dec31_is_32b + connect \ALU_dec31_ldst_len \ALU_dec31_ALU_dec31_ldst_len + connect \ALU_dec31_rc_sel \ALU_dec31_ALU_dec31_rc_sel + connect \ALU_dec31_sgn \ALU_dec31_ALU_dec31_sgn + connect \opcode_in \ALU_dec31_opcode_in + end + attribute \src "issuer_ls180.v:50067.7-50067.20" + process $proc$issuer_ls180.v:50067$3377 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "issuer_ls180.v:51275.3-51308.6" + process $proc$issuer_ls180.v:51275$3363 + assign { } { } + assign { } { } + assign $0\ALU_rc_sel[1:0] $1\ALU_rc_sel[1:0] + attribute \src "issuer_ls180.v:51276.5-51276.29" + switch \initial + attribute \src "issuer_ls180.v:51276.9-51276.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'010011 + assign { } { } + assign $1\ALU_rc_sel[1:0] \ALU_dec19_ALU_dec19_rc_sel + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\ALU_rc_sel[1:0] \ALU_dec31_ALU_dec31_rc_sel + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'001100 + assign { } { } + assign $1\ALU_rc_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'001101 + assign { } { } + assign $1\ALU_rc_sel[1:0] 2'01 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'001110 + assign { } { } + assign $1\ALU_rc_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'001111 + assign { } { } + assign $1\ALU_rc_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'001011 + assign { } { } + assign $1\ALU_rc_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'001010 + assign { } { } + assign $1\ALU_rc_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'001000 + assign { } { } + assign $1\ALU_rc_sel[1:0] 2'00 + case + assign $1\ALU_rc_sel[1:0] 2'00 + end + sync always + update \ALU_rc_sel $0\ALU_rc_sel[1:0] + end + attribute \src "issuer_ls180.v:51309.3-51342.6" + process $proc$issuer_ls180.v:51309$3364 + assign { } { } + assign { } { } + assign $0\ALU_cry_in[1:0] $1\ALU_cry_in[1:0] + attribute \src "issuer_ls180.v:51310.5-51310.29" + switch \initial + attribute \src "issuer_ls180.v:51310.9-51310.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'010011 + assign { } { } + assign $1\ALU_cry_in[1:0] \ALU_dec19_ALU_dec19_cry_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\ALU_cry_in[1:0] \ALU_dec31_ALU_dec31_cry_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'001100 + assign { } { } + assign $1\ALU_cry_in[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'001101 + assign { } { } + assign $1\ALU_cry_in[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'001110 + assign { } { } + assign $1\ALU_cry_in[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'001111 + assign { } { } + assign $1\ALU_cry_in[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'001011 + assign { } { } + assign $1\ALU_cry_in[1:0] 2'01 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'001010 + assign { } { } + assign $1\ALU_cry_in[1:0] 2'01 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'001000 + assign { } { } + assign $1\ALU_cry_in[1:0] 2'01 + case + assign $1\ALU_cry_in[1:0] 2'00 + end + sync always + update \ALU_cry_in $0\ALU_cry_in[1:0] + end + attribute \src "issuer_ls180.v:51343.3-51376.6" + process $proc$issuer_ls180.v:51343$3365 + assign { } { } + assign { } { } + assign $0\ALU_inv_a[0:0] $1\ALU_inv_a[0:0] + attribute \src "issuer_ls180.v:51344.5-51344.29" + switch \initial + attribute \src "issuer_ls180.v:51344.9-51344.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'010011 + assign { } { } + assign $1\ALU_inv_a[0:0] \ALU_dec19_ALU_dec19_inv_a + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\ALU_inv_a[0:0] \ALU_dec31_ALU_dec31_inv_a + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'001100 + assign { } { } + assign $1\ALU_inv_a[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'001101 + assign { } { } + assign $1\ALU_inv_a[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'001110 + assign { } { } + assign $1\ALU_inv_a[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'001111 + assign { } { } + assign $1\ALU_inv_a[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'001011 + assign { } { } + assign $1\ALU_inv_a[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'001010 + assign { } { } + assign $1\ALU_inv_a[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'001000 + assign { } { } + assign $1\ALU_inv_a[0:0] 1'1 + case + assign $1\ALU_inv_a[0:0] 1'0 + end + sync always + update \ALU_inv_a $0\ALU_inv_a[0:0] + end + attribute \src "issuer_ls180.v:51377.3-51410.6" + process $proc$issuer_ls180.v:51377$3366 + assign { } { } + assign { } { } + assign $0\ALU_inv_out[0:0] $1\ALU_inv_out[0:0] + attribute \src "issuer_ls180.v:51378.5-51378.29" + switch \initial + attribute \src "issuer_ls180.v:51378.9-51378.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'010011 + assign { } { } + assign $1\ALU_inv_out[0:0] \ALU_dec19_ALU_dec19_inv_out + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\ALU_inv_out[0:0] \ALU_dec31_ALU_dec31_inv_out + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'001100 + assign { } { } + assign $1\ALU_inv_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'001101 + assign { } { } + assign $1\ALU_inv_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'001110 + assign { } { } + assign $1\ALU_inv_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'001111 + assign { } { } + assign $1\ALU_inv_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'001011 + assign { } { } + assign $1\ALU_inv_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'001010 + assign { } { } + assign $1\ALU_inv_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'001000 + assign { } { } + assign $1\ALU_inv_out[0:0] 1'0 + case + assign $1\ALU_inv_out[0:0] 1'0 + end + sync always + update \ALU_inv_out $0\ALU_inv_out[0:0] + end + attribute \src "issuer_ls180.v:51411.3-51444.6" + process $proc$issuer_ls180.v:51411$3367 + assign { } { } + assign { } { } + assign $0\ALU_cry_out[0:0] $1\ALU_cry_out[0:0] + attribute \src "issuer_ls180.v:51412.5-51412.29" + switch \initial + attribute \src "issuer_ls180.v:51412.9-51412.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'010011 + assign { } { } + assign $1\ALU_cry_out[0:0] \ALU_dec19_ALU_dec19_cry_out + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\ALU_cry_out[0:0] \ALU_dec31_ALU_dec31_cry_out + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'001100 + assign { } { } + assign $1\ALU_cry_out[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'001101 + assign { } { } + assign $1\ALU_cry_out[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'001110 + assign { } { } + assign $1\ALU_cry_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'001111 + assign { } { } + assign $1\ALU_cry_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'001011 + assign { } { } + assign $1\ALU_cry_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'001010 + assign { } { } + assign $1\ALU_cry_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'001000 + assign { } { } + assign $1\ALU_cry_out[0:0] 1'1 + case + assign $1\ALU_cry_out[0:0] 1'0 + end + sync always + update \ALU_cry_out $0\ALU_cry_out[0:0] + end + attribute \src "issuer_ls180.v:51445.3-51478.6" + process $proc$issuer_ls180.v:51445$3368 + assign { } { } + assign { } { } + assign $0\ALU_is_32b[0:0] $1\ALU_is_32b[0:0] + attribute \src "issuer_ls180.v:51446.5-51446.29" + switch \initial + attribute \src "issuer_ls180.v:51446.9-51446.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'010011 + assign { } { } + assign $1\ALU_is_32b[0:0] \ALU_dec19_ALU_dec19_is_32b + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\ALU_is_32b[0:0] \ALU_dec31_ALU_dec31_is_32b + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'001100 + assign { } { } + assign $1\ALU_is_32b[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'001101 + assign { } { } + assign $1\ALU_is_32b[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'001110 + assign { } { } + assign $1\ALU_is_32b[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'001111 + assign { } { } + assign $1\ALU_is_32b[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'001011 + assign { } { } + assign $1\ALU_is_32b[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'001010 + assign { } { } + assign $1\ALU_is_32b[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'001000 + assign { } { } + assign $1\ALU_is_32b[0:0] 1'0 + case + assign $1\ALU_is_32b[0:0] 1'0 + end + sync always + update \ALU_is_32b $0\ALU_is_32b[0:0] + end + attribute \src "issuer_ls180.v:51479.3-51512.6" + process $proc$issuer_ls180.v:51479$3369 + assign { } { } + assign { } { } + assign $0\ALU_sgn[0:0] $1\ALU_sgn[0:0] + attribute \src "issuer_ls180.v:51480.5-51480.29" + switch \initial + attribute \src "issuer_ls180.v:51480.9-51480.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'010011 + assign { } { } + assign $1\ALU_sgn[0:0] \ALU_dec19_ALU_dec19_sgn + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\ALU_sgn[0:0] \ALU_dec31_ALU_dec31_sgn + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'001100 + assign { } { } + assign $1\ALU_sgn[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'001101 + assign { } { } + assign $1\ALU_sgn[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'001110 + assign { } { } + assign $1\ALU_sgn[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'001111 + assign { } { } + assign $1\ALU_sgn[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'001011 + assign { } { } + assign $1\ALU_sgn[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'001010 + assign { } { } + assign $1\ALU_sgn[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'001000 + assign { } { } + assign $1\ALU_sgn[0:0] 1'0 + case + assign $1\ALU_sgn[0:0] 1'0 + end + sync always + update \ALU_sgn $0\ALU_sgn[0:0] + end + attribute \src "issuer_ls180.v:51513.3-51546.6" + process $proc$issuer_ls180.v:51513$3370 + assign { } { } + assign { } { } + assign $0\ALU_function_unit[11:0] $1\ALU_function_unit[11:0] + attribute \src "issuer_ls180.v:51514.5-51514.29" + switch \initial + attribute \src "issuer_ls180.v:51514.9-51514.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'010011 + assign { } { } + assign $1\ALU_function_unit[11:0] \ALU_dec19_ALU_dec19_function_unit + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\ALU_function_unit[11:0] \ALU_dec31_ALU_dec31_function_unit + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'001100 + assign { } { } + assign $1\ALU_function_unit[11:0] 12'000000000010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'001101 + assign { } { } + assign $1\ALU_function_unit[11:0] 12'000000000010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'001110 + assign { } { } + assign $1\ALU_function_unit[11:0] 12'000000000010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'001111 + assign { } { } + assign $1\ALU_function_unit[11:0] 12'000000000010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'001011 + assign { } { } + assign $1\ALU_function_unit[11:0] 12'000000000010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'001010 + assign { } { } + assign $1\ALU_function_unit[11:0] 12'000000000010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'001000 + assign { } { } + assign $1\ALU_function_unit[11:0] 12'000000000010 + case + assign $1\ALU_function_unit[11:0] 12'000000000000 + end + sync always + update \ALU_function_unit $0\ALU_function_unit[11:0] + end + attribute \src "issuer_ls180.v:51547.3-51580.6" + process $proc$issuer_ls180.v:51547$3371 + assign { } { } + assign { } { } + assign $0\ALU_internal_op[6:0] $1\ALU_internal_op[6:0] + attribute \src "issuer_ls180.v:51548.5-51548.29" + switch \initial + attribute \src "issuer_ls180.v:51548.9-51548.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'010011 + assign { } { } + assign $1\ALU_internal_op[6:0] \ALU_dec19_ALU_dec19_internal_op + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\ALU_internal_op[6:0] \ALU_dec31_ALU_dec31_internal_op + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'001100 + assign { } { } + assign $1\ALU_internal_op[6:0] 7'0000010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'001101 + assign { } { } + assign $1\ALU_internal_op[6:0] 7'0000010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'001110 + assign { } { } + assign $1\ALU_internal_op[6:0] 7'0000010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'001111 + assign { } { } + assign $1\ALU_internal_op[6:0] 7'0000010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'001011 + assign { } { } + assign $1\ALU_internal_op[6:0] 7'0001010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'001010 + assign { } { } + assign $1\ALU_internal_op[6:0] 7'0001010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'001000 + assign { } { } + assign $1\ALU_internal_op[6:0] 7'0000010 + case + assign $1\ALU_internal_op[6:0] 7'0000000 + end + sync always + update \ALU_internal_op $0\ALU_internal_op[6:0] + end + attribute \src "issuer_ls180.v:51581.3-51614.6" + process $proc$issuer_ls180.v:51581$3372 + assign { } { } + assign { } { } + assign $0\ALU_in1_sel[2:0] $1\ALU_in1_sel[2:0] + attribute \src "issuer_ls180.v:51582.5-51582.29" + switch \initial + attribute \src "issuer_ls180.v:51582.9-51582.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'010011 + assign { } { } + assign $1\ALU_in1_sel[2:0] \ALU_dec19_ALU_dec19_in1_sel + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\ALU_in1_sel[2:0] \ALU_dec31_ALU_dec31_in1_sel + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'001100 + assign { } { } + assign $1\ALU_in1_sel[2:0] 3'001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'001101 + assign { } { } + assign $1\ALU_in1_sel[2:0] 3'001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'001110 + assign { } { } + assign $1\ALU_in1_sel[2:0] 3'010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'001111 + assign { } { } + assign $1\ALU_in1_sel[2:0] 3'010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'001011 + assign { } { } + assign $1\ALU_in1_sel[2:0] 3'001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'001010 + assign { } { } + assign $1\ALU_in1_sel[2:0] 3'001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'001000 + assign { } { } + assign $1\ALU_in1_sel[2:0] 3'001 + case + assign $1\ALU_in1_sel[2:0] 3'000 + end + sync always + update \ALU_in1_sel $0\ALU_in1_sel[2:0] + end + attribute \src "issuer_ls180.v:51615.3-51648.6" + process $proc$issuer_ls180.v:51615$3373 + assign { } { } + assign { } { } + assign $0\ALU_in2_sel[3:0] $1\ALU_in2_sel[3:0] + attribute \src "issuer_ls180.v:51616.5-51616.29" + switch \initial + attribute \src "issuer_ls180.v:51616.9-51616.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'010011 + assign { } { } + assign $1\ALU_in2_sel[3:0] \ALU_dec19_ALU_dec19_in2_sel + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\ALU_in2_sel[3:0] \ALU_dec31_ALU_dec31_in2_sel + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'001100 + assign { } { } + assign $1\ALU_in2_sel[3:0] 4'0011 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'001101 + assign { } { } + assign $1\ALU_in2_sel[3:0] 4'0011 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'001110 + assign { } { } + assign $1\ALU_in2_sel[3:0] 4'0011 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'001111 + assign { } { } + assign $1\ALU_in2_sel[3:0] 4'0101 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'001011 + assign { } { } + assign $1\ALU_in2_sel[3:0] 4'0011 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'001010 + assign { } { } + assign $1\ALU_in2_sel[3:0] 4'0010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'001000 + assign { } { } + assign $1\ALU_in2_sel[3:0] 4'0011 + case + assign $1\ALU_in2_sel[3:0] 4'0000 + end + sync always + update \ALU_in2_sel $0\ALU_in2_sel[3:0] + end + attribute \src "issuer_ls180.v:51649.3-51682.6" + process $proc$issuer_ls180.v:51649$3374 + assign { } { } + assign { } { } + assign $0\ALU_cr_in[2:0] $1\ALU_cr_in[2:0] + attribute \src "issuer_ls180.v:51650.5-51650.29" + switch \initial + attribute \src "issuer_ls180.v:51650.9-51650.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'010011 + assign { } { } + assign $1\ALU_cr_in[2:0] \ALU_dec19_ALU_dec19_cr_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\ALU_cr_in[2:0] \ALU_dec31_ALU_dec31_cr_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'001100 + assign { } { } + assign $1\ALU_cr_in[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'001101 + assign { } { } + assign $1\ALU_cr_in[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'001110 + assign { } { } + assign $1\ALU_cr_in[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'001111 + assign { } { } + assign $1\ALU_cr_in[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'001011 + assign { } { } + assign $1\ALU_cr_in[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'001010 + assign { } { } + assign $1\ALU_cr_in[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'001000 + assign { } { } + assign $1\ALU_cr_in[2:0] 3'000 + case + assign $1\ALU_cr_in[2:0] 3'000 + end + sync always + update \ALU_cr_in $0\ALU_cr_in[2:0] + end + attribute \src "issuer_ls180.v:51683.3-51716.6" + process $proc$issuer_ls180.v:51683$3375 + assign { } { } + assign { } { } + assign $0\ALU_cr_out[2:0] $1\ALU_cr_out[2:0] + attribute \src "issuer_ls180.v:51684.5-51684.29" + switch \initial + attribute \src "issuer_ls180.v:51684.9-51684.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'010011 + assign { } { } + assign $1\ALU_cr_out[2:0] \ALU_dec19_ALU_dec19_cr_out + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\ALU_cr_out[2:0] \ALU_dec31_ALU_dec31_cr_out + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'001100 + assign { } { } + assign $1\ALU_cr_out[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'001101 + assign { } { } + assign $1\ALU_cr_out[2:0] 3'001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'001110 + assign { } { } + assign $1\ALU_cr_out[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'001111 + assign { } { } + assign $1\ALU_cr_out[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'001011 + assign { } { } + assign $1\ALU_cr_out[2:0] 3'010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'001010 + assign { } { } + assign $1\ALU_cr_out[2:0] 3'010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'001000 + assign { } { } + assign $1\ALU_cr_out[2:0] 3'000 + case + assign $1\ALU_cr_out[2:0] 3'000 + end + sync always + update \ALU_cr_out $0\ALU_cr_out[2:0] + end + attribute \src "issuer_ls180.v:51717.3-51750.6" + process $proc$issuer_ls180.v:51717$3376 + assign { } { } + assign { } { } + assign $0\ALU_ldst_len[3:0] $1\ALU_ldst_len[3:0] + attribute \src "issuer_ls180.v:51718.5-51718.29" + switch \initial + attribute \src "issuer_ls180.v:51718.9-51718.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'010011 + assign { } { } + assign $1\ALU_ldst_len[3:0] \ALU_dec19_ALU_dec19_ldst_len + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\ALU_ldst_len[3:0] \ALU_dec31_ALU_dec31_ldst_len + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'001100 + assign { } { } + assign $1\ALU_ldst_len[3:0] 4'0000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'001101 + assign { } { } + assign $1\ALU_ldst_len[3:0] 4'0000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'001110 + assign { } { } + assign $1\ALU_ldst_len[3:0] 4'0000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'001111 + assign { } { } + assign $1\ALU_ldst_len[3:0] 4'0000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'001011 + assign { } { } + assign $1\ALU_ldst_len[3:0] 4'0000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'001010 + assign { } { } + assign $1\ALU_ldst_len[3:0] 4'0000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'001000 + assign { } { } + assign $1\ALU_ldst_len[3:0] 4'0000 + case + assign $1\ALU_ldst_len[3:0] 4'0000 + end + sync always + update \ALU_ldst_len $0\ALU_ldst_len[3:0] + end + connect \$1 $ternary$issuer_ls180.v:51240$3362_Y + connect \VC_XO \opcode_in [9:0] + connect \VC_VRT \opcode_in [25:21] + connect \VC_VRB \opcode_in [15:11] + connect \VC_VRA \opcode_in [20:16] + connect \VC_Rc \opcode_in [10] + connect \XS_XO \opcode_in [10:2] + connect \XS_sh { \opcode_in [1] \opcode_in [15:11] } + connect \XS_RS \opcode_in [25:21] + connect \XS_Rc \opcode_in [0] + connect \XS_RA \opcode_in [20:16] + connect \VA_XO \opcode_in [5:0] + connect \VA_VRT \opcode_in [25:21] + connect \VA_VRC \opcode_in [10:6] + connect \VA_VRB \opcode_in [15:11] + connect \VA_VRA \opcode_in [20:16] + connect \VA_SHB \opcode_in [9:6] + connect \VA_RT \opcode_in [25:21] + connect \VA_RC \opcode_in [10:6] + connect \VA_RB \opcode_in [15:11] + connect \VA_RA \opcode_in [20:16] + connect \TX_XO \opcode_in [6:1] + connect \TX_XBI \opcode_in [10:7] + connect \TX_UI \opcode_in [15:11] + connect \TX_RA \opcode_in [20:16] + connect \DQE_XO \opcode_in [1:0] + connect \DQE_RT \opcode_in [25:21] + connect \DQE_RA \opcode_in [20:16] + connect \XO_XO \opcode_in [9:1] + connect \XO_RT \opcode_in [25:21] + connect \XO_Rc \opcode_in [0] + connect \XO_RB \opcode_in [15:11] + connect \XO_RA \opcode_in [20:16] + connect \XO_OE \opcode_in [10] + connect \all_PO \opcode_in [31:26] + connect \all_OPCD \opcode_in [31:26] + connect \MD_XO \opcode_in [4:2] + connect \MD_sh { \opcode_in [1] \opcode_in [15:11] } + connect \MD_RS \opcode_in [25:21] + connect \MD_Rc \opcode_in [0] + connect \MD_RA \opcode_in [20:16] + connect \MD_me \opcode_in [10:5] + connect \MD_mb \opcode_in [10:5] + connect \M_SH \opcode_in [15:11] + connect \M_RS \opcode_in [25:21] + connect \M_Rc \opcode_in [0] + connect \M_RB \opcode_in [15:11] + connect \M_RA \opcode_in [20:16] + connect \M_ME \opcode_in [5:1] + connect \M_MB \opcode_in [10:6] + connect \SC_XO_1 \opcode_in [1:0] + connect \SC_XO \opcode_in [1] + connect \SC_LEV \opcode_in [11:5] + connect \MDS_XO \opcode_in [4:1] + connect \MDS_XBI_1 \opcode_in [10:7] + connect \MDS_XBI \opcode_in [10:7] + connect \MDS_RS \opcode_in [25:21] + connect \MDS_Rc \opcode_in [0] + connect \MDS_RB \opcode_in [15:11] + connect \MDS_RA \opcode_in [20:16] + connect \MDS_me \opcode_in [10:5] + connect \MDS_mb \opcode_in [10:5] + connect \MDS_IS \opcode_in [25:21] + connect \MDS_IB \opcode_in [15:11] + connect \Z23_XO \opcode_in [8:1] + connect \Z23_TE \opcode_in [20:16] + connect \Z23_RMC \opcode_in [10:9] + connect \Z23_Rc \opcode_in [0] + connect \Z23_R \opcode_in [16] + connect \Z23_FRTp \opcode_in [25:21] + connect \Z23_FRT \opcode_in [25:21] + connect \Z23_FRBp \opcode_in [15:11] + connect \Z23_FRB \opcode_in [15:11] + connect \Z23_FRAp \opcode_in [20:16] + connect \Z23_FRA \opcode_in [20:16] + connect \XFL_XO \opcode_in [10:1] + connect \XFL_W \opcode_in [16] + connect \XFL_Rc \opcode_in [0] + connect \XFL_L \opcode_in [25] + connect \XFL_FRB \opcode_in [15:11] + connect \XFL_FLM \opcode_in [24:17] + connect \VX_XO_1 \opcode_in [10:0] + connect \VX_XO { \opcode_in [10] \opcode_in [8:0] } + connect \VX_VRT \opcode_in [25:21] + connect \VX_VRB \opcode_in [15:11] + connect \VX_VRA \opcode_in [20:16] + connect \VX_UIM_3 \opcode_in [17:16] + connect \VX_UIM_2 \opcode_in [18:16] + connect \VX_UIM_1 \opcode_in [19:16] + connect \VX_UIM \opcode_in [20:16] + connect \VX_SIM \opcode_in [20:16] + connect \VX_RT \opcode_in [25:21] + connect \VX_RA \opcode_in [20:16] + connect \VX_PS \opcode_in [9] + connect \VX_EO \opcode_in [20:16] + connect \DS_XO \opcode_in [1:0] + connect \DS_VRT \opcode_in [25:21] + connect \DS_VRS \opcode_in [25:21] + connect \DS_RT \opcode_in [25:21] + connect \DS_RSp \opcode_in [25:21] + connect \DS_RS \opcode_in [25:21] + connect \DS_RA \opcode_in [20:16] + connect \DS_FRTp \opcode_in [25:21] + connect \DS_FRSp \opcode_in [25:21] + connect \DS_DS \opcode_in [15:2] + connect \DQ_XO \opcode_in [2:0] + connect \DQ_TX_T { \opcode_in [3] \opcode_in [25:21] } + connect \DQ_T \opcode_in [25:21] + connect \DQ_TX \opcode_in [3] + connect \DQ_SX_S { \opcode_in [3] \opcode_in [25:21] } + connect \DQ_S \opcode_in [25:21] + connect \DQ_SX \opcode_in [3] + connect \DQ_RTp \opcode_in [25:21] + connect \DQ_RA \opcode_in [20:16] + connect \DQ_PT \opcode_in [3:0] + connect \DQ_DQ \opcode_in [15:4] + connect \DX_XO \opcode_in [5:1] + connect \DX_RT \opcode_in [25:21] + connect \DX_d0_d1_d2 { \opcode_in [15:6] \opcode_in [20:16] \opcode_in [0] } + connect \DX_d2 \opcode_in [0] + connect \DX_d1 \opcode_in [20:16] + connect \DX_d0 \opcode_in [15:6] + connect \XFX_XO \opcode_in [10:1] + connect \XFX_SPR \opcode_in [20:11] + connect \XFX_RT \opcode_in [25:21] + connect \XFX_RS \opcode_in [25:21] + connect \XFX_FXM \opcode_in [19:12] + connect \XFX_DUIS \opcode_in [20:11] + connect \XFX_DUI \opcode_in [25:21] + connect \XFX_BHRBE \opcode_in [20:11] + connect \EVS_BFA \opcode_in [2:0] + connect \Z22_XO \opcode_in [9:1] + connect \Z22_SH \opcode_in [15:10] + connect \Z22_Rc \opcode_in [0] + connect \Z22_FRTp \opcode_in [25:21] + connect \Z22_FRT \opcode_in [25:21] + connect \Z22_FRAp \opcode_in [20:16] + connect \Z22_FRA \opcode_in [20:16] + connect \Z22_DGM \opcode_in [15:10] + connect \Z22_DCM \opcode_in [15:10] + connect \Z22_BF \opcode_in [25:23] + connect \XX2_XO_1 \opcode_in [10:2] + connect \XX2_XO { \opcode_in [10:7] \opcode_in [5:3] } + connect \XX2_UIM_1 \opcode_in [17:16] + connect \XX2_UIM \opcode_in [19:16] + connect \XX2_TX_T { \opcode_in [0] \opcode_in [25:21] } + connect \XX2_T \opcode_in [25:21] + connect \XX2_TX \opcode_in [0] + connect \XX2_RT \opcode_in [25:21] + connect \XX2_EO \opcode_in [20:16] + connect \XX2_DCMX \opcode_in [22:16] + connect \XX2_dc_dm_dx { \opcode_in [6] \opcode_in [2] \opcode_in [20:16] } + connect \XX2_dx \opcode_in [20:16] + connect \XX2_dm \opcode_in [2] + connect \XX2_dc \opcode_in [6] + connect \XX2_BX_B { \opcode_in [1] \opcode_in [15:11] } + connect \XX2_B \opcode_in [15:11] + connect \XX2_BX \opcode_in [1] + connect \XX2_BF \opcode_in [25:23] + connect \D_UI \opcode_in [15:0] + connect \D_TO \opcode_in [25:21] + connect \D_SI \opcode_in [15:0] + connect \D_RT \opcode_in [25:21] + connect \D_RS \opcode_in [25:21] + connect \D_RA \opcode_in [20:16] + connect \D_L \opcode_in [21] + connect \D_FRT \opcode_in [25:21] + connect \D_FRS \opcode_in [25:21] + connect \D_D \opcode_in [15:0] + connect \D_BF \opcode_in [25:23] + connect \A_XO \opcode_in [5:1] + connect \A_RT \opcode_in [25:21] + connect \A_Rc \opcode_in [0] + connect \A_RB \opcode_in [15:11] + connect \A_RA \opcode_in [20:16] + connect \A_FRT \opcode_in [25:21] + connect \A_FRC \opcode_in [10:6] + connect \A_FRB \opcode_in [15:11] + connect \A_FRA \opcode_in [20:16] + connect \A_BC \opcode_in [10:6] + connect \XL_XO \opcode_in [10:1] + connect \XL_S \opcode_in [11] + connect \XL_OC \opcode_in [25:11] + connect \XL_LK \opcode_in [0] + connect \XL_BT \opcode_in [25:21] + connect \XL_BO_1 \opcode_in [25:21] + connect \XL_BO \opcode_in [25:21] + connect \XL_BI \opcode_in [20:16] + connect \XL_BH \opcode_in [12:11] + connect \XL_BFA \opcode_in [20:18] + connect \XL_BF \opcode_in [25:23] + connect \XL_BB \opcode_in [15:11] + connect \XL_BA \opcode_in [20:16] + connect \XX4_XO \opcode_in [5:4] + connect \XX4_TX_T { \opcode_in [0] \opcode_in [25:21] } + connect \XX4_T \opcode_in [25:21] + connect \XX4_TX \opcode_in [0] + connect \XX4_CX_C { \opcode_in [3] \opcode_in [10:6] } + connect \XX4_C \opcode_in [10:6] + connect \XX4_CX \opcode_in [3] + connect \XX4_BX_B { \opcode_in [1] \opcode_in [15:11] } + connect \XX4_B \opcode_in [15:11] + connect \XX4_BX \opcode_in [1] + connect \XX4_AX_A { \opcode_in [2] \opcode_in [20:16] } + connect \XX4_A \opcode_in [20:16] + connect \XX4_AX \opcode_in [2] + connect \XX3_XO_2 \opcode_in [9:1] + connect \XX3_XO_1 \opcode_in [10:3] + connect \XX3_XO \opcode_in [10:7] + connect \XX3_TX_T { \opcode_in [0] \opcode_in [25:21] } + connect \XX3_T \opcode_in [25:21] + connect \XX3_TX \opcode_in [0] + connect \XX3_SHW \opcode_in [9:8] + connect \XX3_Rc \opcode_in [10] + connect \XX3_DM \opcode_in [9:8] + connect \XX3_BX_B { \opcode_in [1] \opcode_in [15:11] } + connect \XX3_B \opcode_in [15:11] + connect \XX3_BX \opcode_in [1] + connect \XX3_BF \opcode_in [25:23] + connect \XX3_AX_A { \opcode_in [2] \opcode_in [20:16] } + connect \XX3_A \opcode_in [20:16] + connect \XX3_AX \opcode_in [2] + connect \I_LK \opcode_in [0] + connect \I_LI \opcode_in [25:2] + connect \I_AA \opcode_in [1] + connect \B_LK \opcode_in [0] + connect \B_BO \opcode_in [25:21] + connect \B_BI \opcode_in [20:16] + connect \B_BD \opcode_in [15:2] + connect \B_AA \opcode_in [1] + connect \X_XO_1 \opcode_in [8:1] + connect \X_XO \opcode_in [10:1] + connect \X_WC \opcode_in [22:21] + connect \X_W \opcode_in [16] + connect \X_VRT \opcode_in [25:21] + connect \X_VRS \opcode_in [25:21] + connect \X_UIM \opcode_in [20:16] + connect \X_U \opcode_in [15:12] + connect \X_TX_T { \opcode_in [0] \opcode_in [25:21] } + connect \X_TX \opcode_in [0] + connect \X_TO \opcode_in [25:21] + connect \X_TH \opcode_in [25:21] + connect \X_TBR \opcode_in [20:11] + connect \X_T \opcode_in [25:21] + connect \X_SX_S { \opcode_in [0] \opcode_in [25:21] } + connect \X_SX \opcode_in [0] + connect \X_SR \opcode_in [19:16] + connect \X_SP \opcode_in [20:19] + connect \X_SI \opcode_in [15:11] + connect \X_SH \opcode_in [15:11] + connect \X_S \opcode_in [25:21] + connect \X_RTp \opcode_in [25:21] + connect \X_RT \opcode_in [25:21] + connect \X_RSp \opcode_in [25:21] + connect \X_RS \opcode_in [25:21] + connect \X_RO \opcode_in [0] + connect \X_RM \opcode_in [12:11] + connect \X_RIC \opcode_in [19:18] + connect \X_Rc \opcode_in [0] + connect \X_RB \opcode_in [15:11] + connect \X_RA \opcode_in [20:16] + connect \X_R_1 \opcode_in [16] + connect \X_R \opcode_in [21] + connect \X_PRS \opcode_in [17] + connect \X_NB \opcode_in [15:11] + connect \X_MO \opcode_in [25:21] + connect \X_L3 \opcode_in [17:16] + connect \X_L1 \opcode_in [16] + connect \X_L \opcode_in [21] + connect \X_L2 \opcode_in [22:21] + connect \X_IMM8 \opcode_in [18:11] + connect \X_IH \opcode_in [23:21] + connect \X_FRTp \opcode_in [25:21] + connect \X_FRT \opcode_in [25:21] + connect \X_FRSp \opcode_in [25:21] + connect \X_FRS \opcode_in [25:21] + connect \X_FRBp \opcode_in [15:11] + connect \X_FRB \opcode_in [15:11] + connect \X_FRAp \opcode_in [20:16] + connect \X_FRA \opcode_in [20:16] + connect \X_FC \opcode_in [15:11] + connect \X_EX \opcode_in [0] + connect \X_EO_1 \opcode_in [20:16] + connect \X_EO \opcode_in [20:19] + connect \X_E_1 \opcode_in [19:16] + connect \X_E \opcode_in [15] + connect \X_DRM \opcode_in [13:11] + connect \X_DCMX \opcode_in [22:16] + connect \X_CT \opcode_in [24:21] + connect \X_BO \opcode_in [25:21] + connect \X_BFA \opcode_in [20:18] + connect \X_BF \opcode_in [25:23] + connect \X_A \opcode_in [25] + connect \ALU_SPR \opcode_in [20:11] + connect \ALU_MB \opcode_in [10:6] + connect \ALU_ME \opcode_in [5:1] + connect \ALU_SH \opcode_in [15:11] + connect \ALU_BC \opcode_in [10:6] + connect \ALU_TO \opcode_in [25:21] + connect \ALU_DS \opcode_in [15:2] + connect \ALU_D \opcode_in [15:0] + connect \ALU_BH \opcode_in [12:11] + connect \ALU_BI \opcode_in [20:16] + connect \ALU_BO \opcode_in [25:21] + connect \ALU_FXM \opcode_in [19:12] + connect \ALU_BT \opcode_in [25:21] + connect \ALU_BA \opcode_in [20:16] + connect \ALU_BB \opcode_in [15:11] + connect \ALU_CR \opcode_in [10:1] + connect \ALU_BF \opcode_in [25:23] + connect \ALU_BD \opcode_in [15:2] + connect \ALU_OE \opcode_in [10] + connect \ALU_Rc \opcode_in [0] + connect \ALU_AA \opcode_in [1] + connect \ALU_LK \opcode_in [0] + connect \ALU_LI \opcode_in [25:2] + connect \ALU_ME32 \opcode_in [5:1] + connect \ALU_MB32 \opcode_in [10:6] + connect \ALU_sh { \opcode_in [1] \opcode_in [15:11] } + connect \ALU_SH32 \opcode_in [15:11] + connect \ALU_L \opcode_in [21] + connect \ALU_UI \opcode_in [15:0] + connect \ALU_SI \opcode_in [15:0] + connect \ALU_RB \opcode_in [15:11] + connect \ALU_RA \opcode_in [20:16] + connect \ALU_RT \opcode_in [25:21] + connect \ALU_RS \opcode_in [25:21] + connect \opcode_in \$1 + connect \ALU_dec31_opcode_in \opcode_in + connect \ALU_dec19_opcode_in \opcode_in + connect \opcode_switch \opcode_in [31:26] +end +attribute \src "issuer_ls180.v:52085.1-53515.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.dec_CR.dec" +attribute \generator "nMigen" +module \dec$137 + attribute \src "issuer_ls180.v:53146.3-53158.6" + wire width 3 $0\CR_cr_in[2:0] + attribute \src "issuer_ls180.v:53159.3-53171.6" + wire width 3 $0\CR_cr_out[2:0] + attribute \src "issuer_ls180.v:53120.3-53132.6" + wire width 12 $0\CR_function_unit[11:0] + attribute \src "issuer_ls180.v:53133.3-53145.6" + wire width 7 $0\CR_internal_op[6:0] + attribute \src "issuer_ls180.v:53172.3-53184.6" + wire width 2 $0\CR_rc_sel[1:0] + attribute \src "issuer_ls180.v:52086.7-52086.20" + wire $0\initial[0:0] + attribute \src "issuer_ls180.v:53146.3-53158.6" + wire width 3 $1\CR_cr_in[2:0] + attribute \src "issuer_ls180.v:53159.3-53171.6" + wire width 3 $1\CR_cr_out[2:0] + attribute \src "issuer_ls180.v:53120.3-53132.6" + wire width 12 $1\CR_function_unit[11:0] + attribute \src "issuer_ls180.v:53133.3-53145.6" + wire width 7 $1\CR_internal_op[6:0] + attribute \src "issuer_ls180.v:53172.3-53184.6" + wire width 2 $1\CR_rc_sel[1:0] + attribute \src "issuer_ls180.v:53103.17-53103.211" + wire width 32 $ternary$issuer_ls180.v:53103$3378_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:478" + wire width 32 \$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \A_BC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \A_FRA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \A_FRB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \A_FRC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \A_FRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \A_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \A_RB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \A_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \A_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \A_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \B_AA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 14 \B_BD + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \B_BI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \B_BO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \B_LK + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire \CR_AA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 output 11 \CR_BA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 output 10 \CR_BB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 output 15 \CR_BC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 14 \CR_BD + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 3 \CR_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 2 \CR_BH + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 output 14 \CR_BI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 \CR_BO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 output 12 \CR_BT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 10 \CR_CR + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 16 \CR_D + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 14 \CR_DS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 8 output 13 \CR_FXM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire \CR_L + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 24 \CR_LI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire \CR_LK + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 \CR_MB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 \CR_MB32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 \CR_ME + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 \CR_ME32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire output 9 \CR_OE + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 \CR_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 \CR_RB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 \CR_RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 \CR_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire output 8 \CR_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 \CR_SH + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 \CR_SH32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 16 \CR_SI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 10 \CR_SPR + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 \CR_TO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 16 \CR_UI + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 4 \CR_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 5 \CR_cr_out + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 \CR_dec19_CR_dec19_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 \CR_dec19_CR_dec19_cr_out + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 12 \CR_dec19_CR_dec19_function_unit + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 7 \CR_dec19_CR_dec19_internal_op + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \CR_dec19_CR_dec19_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + wire width 32 \CR_dec19_opcode_in + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 \CR_dec31_CR_dec31_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 \CR_dec31_CR_dec31_cr_out + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 12 \CR_dec31_CR_dec31_function_unit + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 7 \CR_dec31_CR_dec31_internal_op + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \CR_dec31_CR_dec31_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + wire width 32 \CR_dec31_opcode_in + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 12 output 7 \CR_function_unit + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 7 output 6 \CR_internal_op + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 3 \CR_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 6 \CR_sh + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \DQE_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \DQE_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 2 \DQE_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 12 \DQ_DQ + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 4 \DQ_PT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \DQ_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \DQ_RTp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \DQ_S + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \DQ_SX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \DQ_SX_S + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \DQ_T + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \DQ_TX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \DQ_TX_T + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 3 \DQ_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 14 \DS_DS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \DS_FRSp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \DS_FRTp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \DS_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \DS_RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \DS_RSp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \DS_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \DS_VRS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \DS_VRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 2 \DS_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \DX_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \DX_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 10 \DX_d0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 16 \DX_d0_d1_d2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \DX_d1 + attribute \src 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wire \X_PRS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \X_R + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_RB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 2 \X_RIC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 2 \X_RM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \X_RO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_RSp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_RTp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \X_R_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \X_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_S + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_SH + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_SI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 2 \X_SP + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 4 \X_SR + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \X_SX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \X_SX_S + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_T + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 10 \X_TBR + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_TH + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_TO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \X_TX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \X_TX_T + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 4 \X_U + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_UIM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_VRS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_VRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \X_W + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 2 \X_WC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 10 \X_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 8 \X_XO_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 3 \Z22_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \Z22_DCM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \Z22_DGM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \Z22_FRA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \Z22_FRAp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \Z22_FRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \Z22_FRTp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \Z22_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \Z22_SH + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 9 \Z22_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \Z23_FRA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \Z23_FRAp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \Z23_FRB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \Z23_FRBp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \Z23_FRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \Z23_FRTp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \Z23_R + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 2 \Z23_RMC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \Z23_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \Z23_TE + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 8 \Z23_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \all_OPCD + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \all_PO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + wire input 1 \bigendian + attribute \src "issuer_ls180.v:52086.7-52086.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + wire width 32 output 2 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:320" + wire width 6 \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:442" + wire width 32 input 19 \raw_opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:478" + cell $mux $ternary$issuer_ls180.v:53103$3378 + parameter \WIDTH 32 + connect \A \raw_opcode_in + connect \B { \raw_opcode_in [7:0] \raw_opcode_in [15:8] \raw_opcode_in [23:16] \raw_opcode_in [31:24] } + connect \S \bigendian + connect \Y $ternary$issuer_ls180.v:53103$3378_Y + end + attribute \module_not_derived 1 + attribute \src "issuer_ls180.v:53104.12-53111.4" + cell \CR_dec19 \CR_dec19 + connect \CR_dec19_cr_in \CR_dec19_CR_dec19_cr_in + connect \CR_dec19_cr_out \CR_dec19_CR_dec19_cr_out + connect \CR_dec19_function_unit \CR_dec19_CR_dec19_function_unit + connect \CR_dec19_internal_op \CR_dec19_CR_dec19_internal_op + connect \CR_dec19_rc_sel \CR_dec19_CR_dec19_rc_sel + connect \opcode_in \CR_dec19_opcode_in + end + attribute \module_not_derived 1 + attribute \src "issuer_ls180.v:53112.12-53119.4" + cell \CR_dec31 \CR_dec31 + connect \CR_dec31_cr_in \CR_dec31_CR_dec31_cr_in + connect \CR_dec31_cr_out \CR_dec31_CR_dec31_cr_out + connect \CR_dec31_function_unit \CR_dec31_CR_dec31_function_unit + connect \CR_dec31_internal_op \CR_dec31_CR_dec31_internal_op + connect \CR_dec31_rc_sel \CR_dec31_CR_dec31_rc_sel + connect \opcode_in \CR_dec31_opcode_in + end + attribute \src "issuer_ls180.v:52086.7-52086.20" + process $proc$issuer_ls180.v:52086$3384 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "issuer_ls180.v:53120.3-53132.6" + process $proc$issuer_ls180.v:53120$3379 + assign { } { } + assign { } { } + assign $0\CR_function_unit[11:0] $1\CR_function_unit[11:0] + attribute \src "issuer_ls180.v:53121.5-53121.29" + switch \initial + attribute \src "issuer_ls180.v:53121.9-53121.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'010011 + assign { } { } + assign $1\CR_function_unit[11:0] \CR_dec19_CR_dec19_function_unit + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\CR_function_unit[11:0] \CR_dec31_CR_dec31_function_unit + case + assign $1\CR_function_unit[11:0] 12'000000000000 + end + sync always + update \CR_function_unit $0\CR_function_unit[11:0] + end + attribute \src "issuer_ls180.v:53133.3-53145.6" + process $proc$issuer_ls180.v:53133$3380 + assign { } { } + assign { } { } + assign $0\CR_internal_op[6:0] $1\CR_internal_op[6:0] + attribute \src "issuer_ls180.v:53134.5-53134.29" + switch \initial + attribute \src "issuer_ls180.v:53134.9-53134.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'010011 + assign { } { } + assign $1\CR_internal_op[6:0] \CR_dec19_CR_dec19_internal_op + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\CR_internal_op[6:0] \CR_dec31_CR_dec31_internal_op + case + assign $1\CR_internal_op[6:0] 7'0000000 + end + sync always + update \CR_internal_op $0\CR_internal_op[6:0] + end + attribute \src "issuer_ls180.v:53146.3-53158.6" + process $proc$issuer_ls180.v:53146$3381 + assign { } { } + assign { } { } + assign $0\CR_cr_in[2:0] $1\CR_cr_in[2:0] + attribute \src "issuer_ls180.v:53147.5-53147.29" + switch \initial + attribute \src "issuer_ls180.v:53147.9-53147.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'010011 + assign { } { } + assign $1\CR_cr_in[2:0] \CR_dec19_CR_dec19_cr_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\CR_cr_in[2:0] \CR_dec31_CR_dec31_cr_in + case + assign $1\CR_cr_in[2:0] 3'000 + end + sync always + update \CR_cr_in $0\CR_cr_in[2:0] + end + attribute \src "issuer_ls180.v:53159.3-53171.6" + process $proc$issuer_ls180.v:53159$3382 + assign { } { } + assign { } { } + assign $0\CR_cr_out[2:0] $1\CR_cr_out[2:0] + attribute \src "issuer_ls180.v:53160.5-53160.29" + switch \initial + attribute \src "issuer_ls180.v:53160.9-53160.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'010011 + assign { } { } + assign $1\CR_cr_out[2:0] \CR_dec19_CR_dec19_cr_out + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\CR_cr_out[2:0] \CR_dec31_CR_dec31_cr_out + case + assign $1\CR_cr_out[2:0] 3'000 + end + sync always + update \CR_cr_out $0\CR_cr_out[2:0] + end + attribute \src "issuer_ls180.v:53172.3-53184.6" + process $proc$issuer_ls180.v:53172$3383 + assign { } { } + assign { } { } + assign $0\CR_rc_sel[1:0] $1\CR_rc_sel[1:0] + attribute \src "issuer_ls180.v:53173.5-53173.29" + switch \initial + attribute \src "issuer_ls180.v:53173.9-53173.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'010011 + assign { } { } + assign $1\CR_rc_sel[1:0] \CR_dec19_CR_dec19_rc_sel + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\CR_rc_sel[1:0] \CR_dec31_CR_dec31_rc_sel + case + assign $1\CR_rc_sel[1:0] 2'00 + end + sync always + update \CR_rc_sel $0\CR_rc_sel[1:0] + end + connect \$1 $ternary$issuer_ls180.v:53103$3378_Y + connect \VC_XO \opcode_in [9:0] + connect \VC_VRT \opcode_in [25:21] + connect \VC_VRB \opcode_in [15:11] + connect \VC_VRA \opcode_in [20:16] + connect \VC_Rc \opcode_in [10] + connect \XS_XO \opcode_in [10:2] + connect \XS_sh { \opcode_in [1] \opcode_in [15:11] } + connect \XS_RS \opcode_in [25:21] + connect \XS_Rc \opcode_in [0] + connect \XS_RA \opcode_in [20:16] + connect \VA_XO \opcode_in [5:0] + connect \VA_VRT \opcode_in [25:21] + connect \VA_VRC \opcode_in [10:6] + connect \VA_VRB \opcode_in [15:11] + connect \VA_VRA \opcode_in [20:16] + connect \VA_SHB \opcode_in [9:6] + connect \VA_RT \opcode_in [25:21] + connect \VA_RC \opcode_in [10:6] + connect \VA_RB \opcode_in [15:11] + connect \VA_RA \opcode_in [20:16] + connect \TX_XO \opcode_in [6:1] + connect \TX_XBI \opcode_in [10:7] + connect \TX_UI \opcode_in [15:11] + connect \TX_RA \opcode_in [20:16] + connect \DQE_XO \opcode_in [1:0] + connect \DQE_RT \opcode_in [25:21] + connect \DQE_RA \opcode_in [20:16] + connect \XO_XO \opcode_in [9:1] + connect \XO_RT \opcode_in [25:21] + connect \XO_Rc \opcode_in [0] + connect \XO_RB \opcode_in [15:11] + connect \XO_RA \opcode_in [20:16] + connect \XO_OE \opcode_in [10] + connect \all_PO \opcode_in [31:26] + connect \all_OPCD \opcode_in [31:26] + connect \MD_XO \opcode_in [4:2] + connect \MD_sh { \opcode_in [1] \opcode_in [15:11] } + connect \MD_RS \opcode_in [25:21] + connect \MD_Rc \opcode_in [0] + connect \MD_RA \opcode_in [20:16] + connect \MD_me \opcode_in [10:5] + connect \MD_mb \opcode_in [10:5] + connect \M_SH \opcode_in [15:11] + connect \M_RS \opcode_in [25:21] + connect \M_Rc \opcode_in [0] + connect \M_RB \opcode_in [15:11] + connect \M_RA \opcode_in [20:16] + connect \M_ME \opcode_in [5:1] + connect \M_MB \opcode_in [10:6] + connect \SC_XO_1 \opcode_in [1:0] + connect \SC_XO \opcode_in [1] + connect \SC_LEV \opcode_in [11:5] + connect \MDS_XO \opcode_in [4:1] + connect \MDS_XBI_1 \opcode_in [10:7] + connect \MDS_XBI \opcode_in [10:7] + connect \MDS_RS \opcode_in [25:21] + connect \MDS_Rc \opcode_in [0] + connect \MDS_RB \opcode_in [15:11] + connect \MDS_RA \opcode_in [20:16] + connect \MDS_me \opcode_in [10:5] + connect \MDS_mb \opcode_in [10:5] + connect \MDS_IS \opcode_in [25:21] + connect \MDS_IB \opcode_in [15:11] + connect \Z23_XO \opcode_in [8:1] + connect \Z23_TE \opcode_in [20:16] + connect \Z23_RMC \opcode_in [10:9] + connect \Z23_Rc \opcode_in [0] + connect \Z23_R \opcode_in [16] + connect \Z23_FRTp \opcode_in [25:21] + connect \Z23_FRT \opcode_in [25:21] + connect \Z23_FRBp \opcode_in [15:11] + connect \Z23_FRB \opcode_in [15:11] + connect \Z23_FRAp \opcode_in [20:16] + connect \Z23_FRA \opcode_in [20:16] + connect \XFL_XO \opcode_in [10:1] + connect \XFL_W \opcode_in [16] + connect \XFL_Rc \opcode_in [0] + connect \XFL_L \opcode_in [25] + connect \XFL_FRB \opcode_in [15:11] + connect \XFL_FLM \opcode_in [24:17] + connect \VX_XO_1 \opcode_in [10:0] + connect \VX_XO { \opcode_in [10] \opcode_in [8:0] } + connect \VX_VRT \opcode_in [25:21] + connect \VX_VRB \opcode_in [15:11] + connect \VX_VRA \opcode_in [20:16] + connect \VX_UIM_3 \opcode_in [17:16] + connect \VX_UIM_2 \opcode_in [18:16] + connect \VX_UIM_1 \opcode_in [19:16] + connect \VX_UIM \opcode_in [20:16] + connect \VX_SIM \opcode_in [20:16] + connect \VX_RT \opcode_in [25:21] + connect \VX_RA \opcode_in [20:16] + connect \VX_PS \opcode_in [9] + connect \VX_EO \opcode_in [20:16] + connect \DS_XO \opcode_in [1:0] + connect \DS_VRT \opcode_in [25:21] + connect \DS_VRS \opcode_in [25:21] + connect \DS_RT \opcode_in [25:21] + connect \DS_RSp \opcode_in [25:21] + connect \DS_RS \opcode_in [25:21] + connect \DS_RA \opcode_in [20:16] + connect \DS_FRTp \opcode_in [25:21] + connect \DS_FRSp \opcode_in [25:21] + connect \DS_DS \opcode_in [15:2] + connect \DQ_XO \opcode_in [2:0] + connect \DQ_TX_T { \opcode_in [3] \opcode_in [25:21] } + connect \DQ_T \opcode_in [25:21] + connect \DQ_TX \opcode_in [3] + connect \DQ_SX_S { \opcode_in [3] \opcode_in [25:21] } + connect \DQ_S \opcode_in [25:21] + connect \DQ_SX \opcode_in [3] + connect \DQ_RTp \opcode_in [25:21] + connect \DQ_RA \opcode_in [20:16] + connect \DQ_PT \opcode_in [3:0] + connect \DQ_DQ \opcode_in [15:4] + connect \DX_XO \opcode_in [5:1] + connect \DX_RT \opcode_in [25:21] + connect \DX_d0_d1_d2 { \opcode_in [15:6] \opcode_in [20:16] \opcode_in [0] } + connect \DX_d2 \opcode_in [0] + connect \DX_d1 \opcode_in [20:16] + connect \DX_d0 \opcode_in [15:6] + connect \XFX_XO \opcode_in [10:1] + connect \XFX_SPR \opcode_in [20:11] + connect \XFX_RT \opcode_in [25:21] + connect \XFX_RS \opcode_in [25:21] + connect \XFX_FXM \opcode_in [19:12] + connect \XFX_DUIS \opcode_in [20:11] + connect \XFX_DUI \opcode_in [25:21] + connect \XFX_BHRBE \opcode_in [20:11] + connect \EVS_BFA \opcode_in [2:0] + connect \Z22_XO \opcode_in [9:1] + connect \Z22_SH \opcode_in [15:10] + connect \Z22_Rc \opcode_in [0] + connect \Z22_FRTp \opcode_in [25:21] + connect \Z22_FRT \opcode_in [25:21] + connect \Z22_FRAp \opcode_in [20:16] + connect \Z22_FRA \opcode_in [20:16] + connect \Z22_DGM \opcode_in [15:10] + connect \Z22_DCM \opcode_in [15:10] + connect \Z22_BF \opcode_in [25:23] + connect \XX2_XO_1 \opcode_in [10:2] + connect \XX2_XO { \opcode_in [10:7] \opcode_in [5:3] } + connect \XX2_UIM_1 \opcode_in [17:16] + connect \XX2_UIM \opcode_in [19:16] + connect \XX2_TX_T { \opcode_in [0] \opcode_in [25:21] } + connect \XX2_T \opcode_in [25:21] + connect \XX2_TX \opcode_in [0] + connect \XX2_RT \opcode_in [25:21] + connect \XX2_EO \opcode_in [20:16] + connect \XX2_DCMX \opcode_in [22:16] + connect \XX2_dc_dm_dx { \opcode_in [6] \opcode_in [2] \opcode_in [20:16] } + connect \XX2_dx \opcode_in [20:16] + connect \XX2_dm \opcode_in [2] + connect \XX2_dc \opcode_in [6] + connect \XX2_BX_B { \opcode_in [1] \opcode_in [15:11] } + connect \XX2_B \opcode_in [15:11] + connect \XX2_BX \opcode_in [1] + connect \XX2_BF \opcode_in [25:23] + connect \D_UI \opcode_in [15:0] + connect \D_TO \opcode_in [25:21] + connect \D_SI \opcode_in [15:0] + connect \D_RT \opcode_in [25:21] + connect \D_RS \opcode_in [25:21] + connect \D_RA \opcode_in [20:16] + connect \D_L \opcode_in [21] + connect \D_FRT \opcode_in [25:21] + connect \D_FRS \opcode_in [25:21] + connect \D_D \opcode_in [15:0] + connect \D_BF \opcode_in [25:23] + connect \A_XO \opcode_in [5:1] + connect \A_RT \opcode_in [25:21] + connect \A_Rc \opcode_in [0] + connect \A_RB \opcode_in [15:11] + connect \A_RA \opcode_in [20:16] + connect \A_FRT \opcode_in [25:21] + connect \A_FRC \opcode_in [10:6] + connect \A_FRB \opcode_in [15:11] + connect \A_FRA \opcode_in [20:16] + connect \A_BC \opcode_in [10:6] + connect \XL_XO \opcode_in [10:1] + connect \XL_S \opcode_in [11] + connect \XL_OC \opcode_in [25:11] + connect \XL_LK \opcode_in [0] + connect \XL_BT \opcode_in [25:21] + connect \XL_BO_1 \opcode_in [25:21] + connect \XL_BO \opcode_in [25:21] + connect \XL_BI \opcode_in [20:16] + connect \XL_BH \opcode_in [12:11] + connect \XL_BFA \opcode_in [20:18] + connect \XL_BF \opcode_in [25:23] + connect \XL_BB \opcode_in [15:11] + connect \XL_BA \opcode_in [20:16] + connect \XX4_XO \opcode_in [5:4] + connect \XX4_TX_T { \opcode_in [0] \opcode_in [25:21] } + connect \XX4_T \opcode_in [25:21] + connect \XX4_TX \opcode_in [0] + connect \XX4_CX_C { \opcode_in [3] \opcode_in [10:6] } + connect \XX4_C \opcode_in [10:6] + connect \XX4_CX \opcode_in [3] + connect \XX4_BX_B { \opcode_in [1] \opcode_in [15:11] } + connect \XX4_B \opcode_in [15:11] + connect \XX4_BX \opcode_in [1] + connect \XX4_AX_A { \opcode_in [2] \opcode_in [20:16] } + connect \XX4_A \opcode_in [20:16] + connect \XX4_AX \opcode_in [2] + connect \XX3_XO_2 \opcode_in [9:1] + connect \XX3_XO_1 \opcode_in [10:3] + connect \XX3_XO \opcode_in [10:7] + connect \XX3_TX_T { \opcode_in [0] \opcode_in [25:21] } + connect \XX3_T \opcode_in [25:21] + connect \XX3_TX \opcode_in [0] + connect \XX3_SHW \opcode_in [9:8] + connect \XX3_Rc \opcode_in [10] + connect \XX3_DM \opcode_in [9:8] + connect \XX3_BX_B { \opcode_in [1] \opcode_in [15:11] } + connect \XX3_B \opcode_in [15:11] + connect \XX3_BX \opcode_in [1] + connect \XX3_BF \opcode_in [25:23] + connect \XX3_AX_A { \opcode_in [2] \opcode_in [20:16] } + connect \XX3_A \opcode_in [20:16] + connect \XX3_AX \opcode_in [2] + connect \I_LK \opcode_in [0] + connect \I_LI \opcode_in [25:2] + connect \I_AA \opcode_in [1] + connect \B_LK \opcode_in [0] + connect \B_BO \opcode_in [25:21] + connect \B_BI \opcode_in [20:16] + connect \B_BD \opcode_in [15:2] + connect \B_AA \opcode_in [1] + connect \X_XO_1 \opcode_in [8:1] + connect \X_XO \opcode_in [10:1] + connect \X_WC \opcode_in [22:21] + connect \X_W \opcode_in [16] + connect \X_VRT \opcode_in [25:21] + connect \X_VRS \opcode_in [25:21] + connect \X_UIM \opcode_in [20:16] + connect \X_U \opcode_in [15:12] + connect \X_TX_T { \opcode_in [0] \opcode_in [25:21] } + connect \X_TX \opcode_in [0] + connect \X_TO \opcode_in [25:21] + connect \X_TH \opcode_in [25:21] + connect \X_TBR \opcode_in [20:11] + connect \X_T \opcode_in [25:21] + connect \X_SX_S { \opcode_in [0] \opcode_in [25:21] } + connect \X_SX \opcode_in [0] + connect \X_SR \opcode_in [19:16] + connect \X_SP \opcode_in [20:19] + connect \X_SI \opcode_in [15:11] + connect \X_SH \opcode_in [15:11] + connect \X_S \opcode_in [25:21] + connect \X_RTp \opcode_in [25:21] + connect \X_RT \opcode_in [25:21] + connect \X_RSp \opcode_in [25:21] + connect \X_RS \opcode_in [25:21] + connect \X_RO \opcode_in [0] + connect \X_RM \opcode_in [12:11] + connect \X_RIC \opcode_in [19:18] + connect \X_Rc \opcode_in [0] + connect \X_RB \opcode_in [15:11] + connect \X_RA \opcode_in [20:16] + connect \X_R_1 \opcode_in [16] + connect \X_R \opcode_in [21] + connect \X_PRS \opcode_in [17] + connect \X_NB \opcode_in [15:11] + connect \X_MO \opcode_in [25:21] + connect \X_L3 \opcode_in [17:16] + connect \X_L1 \opcode_in [16] + connect \X_L \opcode_in [21] + connect \X_L2 \opcode_in [22:21] + connect \X_IMM8 \opcode_in [18:11] + connect \X_IH \opcode_in [23:21] + connect \X_FRTp \opcode_in [25:21] + connect \X_FRT \opcode_in [25:21] + connect \X_FRSp \opcode_in [25:21] + connect \X_FRS \opcode_in [25:21] + connect \X_FRBp \opcode_in [15:11] + connect \X_FRB \opcode_in [15:11] + connect \X_FRAp \opcode_in [20:16] + connect \X_FRA \opcode_in [20:16] + connect \X_FC \opcode_in [15:11] + connect \X_EX \opcode_in [0] + connect \X_EO_1 \opcode_in [20:16] + connect \X_EO \opcode_in [20:19] + connect \X_E_1 \opcode_in [19:16] + connect \X_E \opcode_in [15] + connect \X_DRM \opcode_in [13:11] + connect \X_DCMX \opcode_in [22:16] + connect \X_CT \opcode_in [24:21] + connect \X_BO \opcode_in [25:21] + connect \X_BFA \opcode_in [20:18] + connect \X_BF \opcode_in [25:23] + connect \X_A \opcode_in [25] + connect \CR_SPR \opcode_in [20:11] + connect \CR_MB \opcode_in [10:6] + connect \CR_ME \opcode_in [5:1] + connect \CR_SH \opcode_in [15:11] + connect \CR_BC \opcode_in [10:6] + connect \CR_TO \opcode_in [25:21] + connect \CR_DS \opcode_in [15:2] + connect \CR_D \opcode_in [15:0] + connect \CR_BH \opcode_in [12:11] + connect \CR_BI \opcode_in [20:16] + connect \CR_BO \opcode_in [25:21] + connect \CR_FXM \opcode_in [19:12] + connect \CR_BT \opcode_in [25:21] + connect \CR_BA \opcode_in [20:16] + connect \CR_BB \opcode_in [15:11] + connect \CR_CR \opcode_in [10:1] + connect \CR_BF \opcode_in [25:23] + connect \CR_BD \opcode_in [15:2] + connect \CR_OE \opcode_in [10] + connect \CR_Rc \opcode_in [0] + connect \CR_AA \opcode_in [1] + connect \CR_LK \opcode_in [0] + connect \CR_LI \opcode_in [25:2] + connect \CR_ME32 \opcode_in [5:1] + connect \CR_MB32 \opcode_in [10:6] + connect \CR_sh { \opcode_in [1] \opcode_in [15:11] } + connect \CR_SH32 \opcode_in [15:11] + connect \CR_L \opcode_in [21] + connect \CR_UI \opcode_in [15:0] + connect \CR_SI \opcode_in [15:0] + connect \CR_RB \opcode_in [15:11] + connect \CR_RA \opcode_in [20:16] + connect \CR_RT \opcode_in [25:21] + connect \CR_RS \opcode_in [25:21] + connect \opcode_in \$1 + connect \CR_dec31_opcode_in \opcode_in + connect \CR_dec19_opcode_in \opcode_in + connect \opcode_switch \opcode_in [31:26] +end +attribute \src "issuer_ls180.v:53519.1-54934.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.dec_BRANCH.dec" +attribute \generator "nMigen" +module \dec$144 + attribute \src "issuer_ls180.v:54525.3-54540.6" + wire width 3 $0\BRANCH_cr_in[2:0] + attribute \src "issuer_ls180.v:54541.3-54556.6" + wire width 3 $0\BRANCH_cr_out[2:0] + attribute \src "issuer_ls180.v:54477.3-54492.6" + wire width 12 $0\BRANCH_function_unit[11:0] + attribute \src "issuer_ls180.v:54509.3-54524.6" + wire width 4 $0\BRANCH_in2_sel[3:0] + attribute \src "issuer_ls180.v:54493.3-54508.6" + wire width 7 $0\BRANCH_internal_op[6:0] + attribute \src "issuer_ls180.v:54573.3-54588.6" + wire $0\BRANCH_is_32b[0:0] + attribute \src "issuer_ls180.v:54589.3-54604.6" + wire $0\BRANCH_lk[0:0] + attribute \src "issuer_ls180.v:54557.3-54572.6" + wire width 2 $0\BRANCH_rc_sel[1:0] + attribute \src "issuer_ls180.v:53520.7-53520.20" + wire $0\initial[0:0] + attribute \src "issuer_ls180.v:54525.3-54540.6" + wire width 3 $1\BRANCH_cr_in[2:0] + attribute \src "issuer_ls180.v:54541.3-54556.6" + wire width 3 $1\BRANCH_cr_out[2:0] + attribute \src "issuer_ls180.v:54477.3-54492.6" + wire width 12 $1\BRANCH_function_unit[11:0] + attribute \src "issuer_ls180.v:54509.3-54524.6" + wire width 4 $1\BRANCH_in2_sel[3:0] + attribute \src "issuer_ls180.v:54493.3-54508.6" + wire width 7 $1\BRANCH_internal_op[6:0] + attribute \src "issuer_ls180.v:54573.3-54588.6" + wire $1\BRANCH_is_32b[0:0] + attribute \src "issuer_ls180.v:54589.3-54604.6" + wire $1\BRANCH_lk[0:0] + attribute \src "issuer_ls180.v:54557.3-54572.6" + wire width 2 $1\BRANCH_rc_sel[1:0] + attribute \src "issuer_ls180.v:54465.17-54465.211" + wire width 32 $ternary$issuer_ls180.v:54465$3385_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:478" + wire width 32 \$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \A_BC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \A_FRA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \A_FRB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \A_FRC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \A_FRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \A_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \A_RB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \A_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \A_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \A_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire \BRANCH_AA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 output 21 \BRANCH_BA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 output 20 \BRANCH_BB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 output 26 \BRANCH_BC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 14 output 19 \BRANCH_BD + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 3 \BRANCH_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 2 \BRANCH_BH + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 output 24 \BRANCH_BI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 \BRANCH_BO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 output 22 \BRANCH_BT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 10 \BRANCH_CR + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 16 \BRANCH_D + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 14 output 25 \BRANCH_DS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 8 output 23 \BRANCH_FXM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire \BRANCH_L + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 24 output 16 \BRANCH_LI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire output 11 \BRANCH_LK + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 \BRANCH_MB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 \BRANCH_MB32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 \BRANCH_ME + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 \BRANCH_ME32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire output 18 \BRANCH_OE + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 \BRANCH_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 \BRANCH_RB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 \BRANCH_RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 \BRANCH_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire output 17 \BRANCH_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 \BRANCH_SH + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 output 14 \BRANCH_SH32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 16 output 12 \BRANCH_SI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 10 \BRANCH_SPR + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 \BRANCH_TO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 16 output 13 \BRANCH_UI + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 4 \BRANCH_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 5 \BRANCH_cr_out + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 \BRANCH_dec19_BRANCH_dec19_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 \BRANCH_dec19_BRANCH_dec19_cr_out + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 12 \BRANCH_dec19_BRANCH_dec19_function_unit + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 \BRANCH_dec19_BRANCH_dec19_in2_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 7 \BRANCH_dec19_BRANCH_dec19_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \BRANCH_dec19_BRANCH_dec19_is_32b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \BRANCH_dec19_BRANCH_dec19_lk + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \BRANCH_dec19_BRANCH_dec19_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + wire width 32 \BRANCH_dec19_opcode_in + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 12 output 7 \BRANCH_function_unit + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 output 8 \BRANCH_in2_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 7 output 6 \BRANCH_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 9 \BRANCH_is_32b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 10 \BRANCH_lk + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 3 \BRANCH_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 6 output 15 \BRANCH_sh + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \B_AA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 14 \B_BD + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \B_BI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \B_BO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \B_LK + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \DQE_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \DQE_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 2 \DQE_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 12 \DQ_DQ + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 4 \DQ_PT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \DQ_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \DQ_RTp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \DQ_S + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \DQ_SX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \DQ_SX_S + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \DQ_T + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \DQ_TX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \DQ_TX_T + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 3 \DQ_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 14 \DS_DS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \DS_FRSp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \DS_FRTp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \DS_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \DS_RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \DS_RSp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \DS_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \DS_VRS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \DS_VRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 2 \DS_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \DX_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \DX_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 10 \DX_d0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 16 \DX_d0_d1_d2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \DX_d1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \DX_d2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 3 \D_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 16 \D_D + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \D_FRS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \D_FRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \D_L + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \D_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \D_RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \D_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 16 \D_SI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \D_TO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 16 \D_UI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 3 \EVS_BFA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \I_AA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 24 \I_LI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \I_LK + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \MDS_IB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \MDS_IS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \MDS_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \MDS_RB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \MDS_RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \MDS_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 4 \MDS_XBI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 4 \MDS_XBI_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 4 \MDS_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \MDS_mb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \MDS_me + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \MD_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \MD_RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \MD_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 3 \MD_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \MD_mb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \MD_me + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \MD_sh + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \M_MB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \M_ME + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \M_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \M_RB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \M_RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \M_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \M_SH + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 7 \SC_LEV + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \SC_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 2 \SC_XO_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \TX_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \TX_UI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 4 \TX_XBI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \TX_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \VA_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \VA_RB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \VA_RC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \VA_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 4 \VA_SHB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \VA_VRA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \VA_VRB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \VA_VRC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \VA_VRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \VA_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \VC_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \VC_VRA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \VC_VRB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \VC_VRT + attribute \src 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wire width 6 \X_TX_T + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 4 \X_U + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_UIM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_VRS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_VRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \X_W + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 2 \X_WC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 10 \X_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 8 \X_XO_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 3 \Z22_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \Z22_DCM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \Z22_DGM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \Z22_FRA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \Z22_FRAp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \Z22_FRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \Z22_FRTp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \Z22_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \Z22_SH + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 9 \Z22_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \Z23_FRA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \Z23_FRAp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \Z23_FRB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \Z23_FRBp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \Z23_FRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \Z23_FRTp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \Z23_R + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 2 \Z23_RMC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \Z23_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \Z23_TE + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 8 \Z23_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \all_OPCD + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \all_PO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + wire input 1 \bigendian + attribute \src "issuer_ls180.v:53520.7-53520.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + wire width 32 output 2 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:320" + wire width 6 \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:442" + wire width 32 input 30 \raw_opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:478" + cell $mux $ternary$issuer_ls180.v:54465$3385 + parameter \WIDTH 32 + connect \A \raw_opcode_in + connect \B { \raw_opcode_in [7:0] \raw_opcode_in [15:8] \raw_opcode_in [23:16] \raw_opcode_in [31:24] } + connect \S \bigendian + connect \Y $ternary$issuer_ls180.v:54465$3385_Y + end + attribute \module_not_derived 1 + attribute \src "issuer_ls180.v:54466.16-54476.4" + cell \BRANCH_dec19 \BRANCH_dec19 + connect \BRANCH_dec19_cr_in \BRANCH_dec19_BRANCH_dec19_cr_in + connect \BRANCH_dec19_cr_out \BRANCH_dec19_BRANCH_dec19_cr_out + connect \BRANCH_dec19_function_unit \BRANCH_dec19_BRANCH_dec19_function_unit + connect \BRANCH_dec19_in2_sel \BRANCH_dec19_BRANCH_dec19_in2_sel + connect \BRANCH_dec19_internal_op \BRANCH_dec19_BRANCH_dec19_internal_op + connect \BRANCH_dec19_is_32b \BRANCH_dec19_BRANCH_dec19_is_32b + connect \BRANCH_dec19_lk \BRANCH_dec19_BRANCH_dec19_lk + connect \BRANCH_dec19_rc_sel \BRANCH_dec19_BRANCH_dec19_rc_sel + connect \opcode_in \BRANCH_dec19_opcode_in + end + attribute \src "issuer_ls180.v:53520.7-53520.20" + process $proc$issuer_ls180.v:53520$3394 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "issuer_ls180.v:54477.3-54492.6" + process $proc$issuer_ls180.v:54477$3386 + assign { } { } + assign { } { } + assign $0\BRANCH_function_unit[11:0] $1\BRANCH_function_unit[11:0] + attribute \src "issuer_ls180.v:54478.5-54478.29" + switch \initial + attribute \src "issuer_ls180.v:54478.9-54478.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'010011 + assign { } { } + assign $1\BRANCH_function_unit[11:0] \BRANCH_dec19_BRANCH_dec19_function_unit + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'010010 + assign { } { } + assign $1\BRANCH_function_unit[11:0] 12'000000100000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'010000 + assign { } { } + assign $1\BRANCH_function_unit[11:0] 12'000000100000 + case + assign $1\BRANCH_function_unit[11:0] 12'000000000000 + end + sync always + update \BRANCH_function_unit $0\BRANCH_function_unit[11:0] + end + attribute \src "issuer_ls180.v:54493.3-54508.6" + process $proc$issuer_ls180.v:54493$3387 + assign { } { } + assign { } { } + assign $0\BRANCH_internal_op[6:0] $1\BRANCH_internal_op[6:0] + attribute \src "issuer_ls180.v:54494.5-54494.29" + switch \initial + attribute \src "issuer_ls180.v:54494.9-54494.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'010011 + assign { } { } + assign $1\BRANCH_internal_op[6:0] \BRANCH_dec19_BRANCH_dec19_internal_op + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'010010 + assign { } { } + assign $1\BRANCH_internal_op[6:0] 7'0000110 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'010000 + assign { } { } + assign $1\BRANCH_internal_op[6:0] 7'0000111 + case + assign $1\BRANCH_internal_op[6:0] 7'0000000 + end + sync always + update \BRANCH_internal_op $0\BRANCH_internal_op[6:0] + end + attribute \src "issuer_ls180.v:54509.3-54524.6" + process $proc$issuer_ls180.v:54509$3388 + assign { } { } + assign { } { } + assign $0\BRANCH_in2_sel[3:0] $1\BRANCH_in2_sel[3:0] + attribute \src "issuer_ls180.v:54510.5-54510.29" + switch \initial + attribute \src "issuer_ls180.v:54510.9-54510.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'010011 + assign { } { } + assign $1\BRANCH_in2_sel[3:0] \BRANCH_dec19_BRANCH_dec19_in2_sel + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'010010 + assign { } { } + assign $1\BRANCH_in2_sel[3:0] 4'0110 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'010000 + assign { } { } + assign $1\BRANCH_in2_sel[3:0] 4'0111 + case + assign $1\BRANCH_in2_sel[3:0] 4'0000 + end + sync always + update \BRANCH_in2_sel $0\BRANCH_in2_sel[3:0] + end + attribute \src "issuer_ls180.v:54525.3-54540.6" + process $proc$issuer_ls180.v:54525$3389 + assign { } { } + assign { } { } + assign $0\BRANCH_cr_in[2:0] $1\BRANCH_cr_in[2:0] + attribute \src "issuer_ls180.v:54526.5-54526.29" + switch \initial + attribute \src "issuer_ls180.v:54526.9-54526.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'010011 + assign { } { } + assign $1\BRANCH_cr_in[2:0] \BRANCH_dec19_BRANCH_dec19_cr_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'010010 + assign { } { } + assign $1\BRANCH_cr_in[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'010000 + assign { } { } + assign $1\BRANCH_cr_in[2:0] 3'010 + case + assign $1\BRANCH_cr_in[2:0] 3'000 + end + sync always + update \BRANCH_cr_in $0\BRANCH_cr_in[2:0] + end + attribute \src "issuer_ls180.v:54541.3-54556.6" + process $proc$issuer_ls180.v:54541$3390 + assign { } { } + assign { } { } + assign $0\BRANCH_cr_out[2:0] $1\BRANCH_cr_out[2:0] + attribute \src "issuer_ls180.v:54542.5-54542.29" + switch \initial + attribute \src "issuer_ls180.v:54542.9-54542.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'010011 + assign { } { } + assign $1\BRANCH_cr_out[2:0] \BRANCH_dec19_BRANCH_dec19_cr_out + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'010010 + assign { } { } + assign $1\BRANCH_cr_out[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'010000 + assign { } { } + assign $1\BRANCH_cr_out[2:0] 3'000 + case + assign $1\BRANCH_cr_out[2:0] 3'000 + end + sync always + update \BRANCH_cr_out $0\BRANCH_cr_out[2:0] + end + attribute \src "issuer_ls180.v:54557.3-54572.6" + process $proc$issuer_ls180.v:54557$3391 + assign { } { } + assign { } { } + assign $0\BRANCH_rc_sel[1:0] $1\BRANCH_rc_sel[1:0] + attribute \src "issuer_ls180.v:54558.5-54558.29" + switch \initial + attribute \src "issuer_ls180.v:54558.9-54558.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'010011 + assign { } { } + assign $1\BRANCH_rc_sel[1:0] \BRANCH_dec19_BRANCH_dec19_rc_sel + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'010010 + assign { } { } + assign $1\BRANCH_rc_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'010000 + assign { } { } + assign $1\BRANCH_rc_sel[1:0] 2'00 + case + assign $1\BRANCH_rc_sel[1:0] 2'00 + end + sync always + update \BRANCH_rc_sel $0\BRANCH_rc_sel[1:0] + end + attribute \src "issuer_ls180.v:54573.3-54588.6" + process $proc$issuer_ls180.v:54573$3392 + assign { } { } + assign { } { } + assign $0\BRANCH_is_32b[0:0] $1\BRANCH_is_32b[0:0] + attribute \src "issuer_ls180.v:54574.5-54574.29" + switch \initial + attribute \src "issuer_ls180.v:54574.9-54574.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'010011 + assign { } { } + assign $1\BRANCH_is_32b[0:0] \BRANCH_dec19_BRANCH_dec19_is_32b + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'010010 + assign { } { } + assign $1\BRANCH_is_32b[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'010000 + assign { } { } + assign $1\BRANCH_is_32b[0:0] 1'0 + case + assign $1\BRANCH_is_32b[0:0] 1'0 + end + sync always + update \BRANCH_is_32b $0\BRANCH_is_32b[0:0] + end + attribute \src "issuer_ls180.v:54589.3-54604.6" + process $proc$issuer_ls180.v:54589$3393 + assign { } { } + assign { } { } + assign $0\BRANCH_lk[0:0] $1\BRANCH_lk[0:0] + attribute \src "issuer_ls180.v:54590.5-54590.29" + switch \initial + attribute \src "issuer_ls180.v:54590.9-54590.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'010011 + assign { } { } + assign $1\BRANCH_lk[0:0] \BRANCH_dec19_BRANCH_dec19_lk + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'010010 + assign { } { } + assign $1\BRANCH_lk[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'010000 + assign { } { } + assign $1\BRANCH_lk[0:0] 1'1 + case + assign $1\BRANCH_lk[0:0] 1'0 + end + sync always + update \BRANCH_lk $0\BRANCH_lk[0:0] + end + connect \$1 $ternary$issuer_ls180.v:54465$3385_Y + connect \VC_XO \opcode_in [9:0] + connect \VC_VRT \opcode_in [25:21] + connect \VC_VRB \opcode_in [15:11] + connect \VC_VRA \opcode_in [20:16] + connect \VC_Rc \opcode_in [10] + connect \XS_XO \opcode_in [10:2] + connect \XS_sh { \opcode_in [1] \opcode_in [15:11] } + connect \XS_RS \opcode_in [25:21] + connect \XS_Rc \opcode_in [0] + connect \XS_RA \opcode_in [20:16] + connect \VA_XO \opcode_in [5:0] + connect \VA_VRT \opcode_in [25:21] + connect \VA_VRC \opcode_in [10:6] + connect \VA_VRB \opcode_in [15:11] + connect \VA_VRA \opcode_in [20:16] + connect \VA_SHB \opcode_in [9:6] + connect \VA_RT \opcode_in [25:21] + connect \VA_RC \opcode_in [10:6] + connect \VA_RB \opcode_in [15:11] + connect \VA_RA \opcode_in [20:16] + connect \TX_XO \opcode_in [6:1] + connect \TX_XBI \opcode_in [10:7] + connect \TX_UI \opcode_in [15:11] + connect \TX_RA \opcode_in [20:16] + connect \DQE_XO \opcode_in [1:0] + connect \DQE_RT \opcode_in [25:21] + connect \DQE_RA \opcode_in [20:16] + connect \XO_XO \opcode_in [9:1] + connect \XO_RT \opcode_in [25:21] + connect \XO_Rc \opcode_in [0] + connect \XO_RB \opcode_in [15:11] + connect \XO_RA \opcode_in [20:16] + connect \XO_OE \opcode_in [10] + connect \all_PO \opcode_in [31:26] + connect \all_OPCD \opcode_in [31:26] + connect \MD_XO \opcode_in [4:2] + connect \MD_sh { \opcode_in [1] \opcode_in [15:11] } + connect \MD_RS \opcode_in [25:21] + connect \MD_Rc \opcode_in [0] + connect \MD_RA \opcode_in [20:16] + connect \MD_me \opcode_in [10:5] + connect \MD_mb \opcode_in [10:5] + connect \M_SH \opcode_in [15:11] + connect \M_RS \opcode_in [25:21] + connect \M_Rc \opcode_in [0] + connect \M_RB \opcode_in [15:11] + connect \M_RA \opcode_in [20:16] + connect \M_ME \opcode_in [5:1] + connect \M_MB \opcode_in [10:6] + connect \SC_XO_1 \opcode_in [1:0] + connect \SC_XO \opcode_in [1] + connect \SC_LEV \opcode_in [11:5] + connect \MDS_XO \opcode_in [4:1] + connect \MDS_XBI_1 \opcode_in [10:7] + connect \MDS_XBI \opcode_in [10:7] + connect \MDS_RS \opcode_in [25:21] + connect \MDS_Rc \opcode_in [0] + connect \MDS_RB \opcode_in [15:11] + connect \MDS_RA \opcode_in [20:16] + connect \MDS_me \opcode_in [10:5] + connect \MDS_mb \opcode_in [10:5] + connect \MDS_IS \opcode_in [25:21] + connect \MDS_IB \opcode_in [15:11] + connect \Z23_XO \opcode_in [8:1] + connect \Z23_TE \opcode_in [20:16] + connect \Z23_RMC \opcode_in [10:9] + connect \Z23_Rc \opcode_in [0] + connect \Z23_R \opcode_in [16] + connect \Z23_FRTp \opcode_in [25:21] + connect \Z23_FRT \opcode_in [25:21] + connect \Z23_FRBp \opcode_in [15:11] + connect \Z23_FRB \opcode_in [15:11] + connect \Z23_FRAp \opcode_in [20:16] + connect \Z23_FRA \opcode_in [20:16] + connect \XFL_XO \opcode_in [10:1] + connect \XFL_W \opcode_in [16] + connect \XFL_Rc \opcode_in [0] + connect \XFL_L \opcode_in [25] + connect \XFL_FRB \opcode_in [15:11] + connect \XFL_FLM \opcode_in [24:17] + connect \VX_XO_1 \opcode_in [10:0] + connect \VX_XO { \opcode_in [10] \opcode_in [8:0] } + connect \VX_VRT \opcode_in [25:21] + connect \VX_VRB \opcode_in [15:11] + connect \VX_VRA \opcode_in [20:16] + connect \VX_UIM_3 \opcode_in [17:16] + connect \VX_UIM_2 \opcode_in [18:16] + connect \VX_UIM_1 \opcode_in [19:16] + connect \VX_UIM \opcode_in [20:16] + connect \VX_SIM \opcode_in [20:16] + connect \VX_RT \opcode_in [25:21] + connect \VX_RA \opcode_in [20:16] + connect \VX_PS \opcode_in [9] + connect \VX_EO \opcode_in [20:16] + connect \DS_XO \opcode_in [1:0] + connect \DS_VRT \opcode_in [25:21] + connect \DS_VRS \opcode_in [25:21] + connect \DS_RT \opcode_in [25:21] + connect \DS_RSp \opcode_in [25:21] + connect \DS_RS \opcode_in [25:21] + connect \DS_RA \opcode_in [20:16] + connect \DS_FRTp \opcode_in [25:21] + connect \DS_FRSp \opcode_in [25:21] + connect \DS_DS \opcode_in [15:2] + connect \DQ_XO \opcode_in [2:0] + connect \DQ_TX_T { \opcode_in [3] \opcode_in [25:21] } + connect \DQ_T \opcode_in [25:21] + connect \DQ_TX \opcode_in [3] + connect \DQ_SX_S { \opcode_in [3] \opcode_in [25:21] } + connect \DQ_S \opcode_in [25:21] + connect \DQ_SX \opcode_in [3] + connect \DQ_RTp \opcode_in [25:21] + connect \DQ_RA \opcode_in [20:16] + connect \DQ_PT \opcode_in [3:0] + connect \DQ_DQ \opcode_in [15:4] + connect \DX_XO \opcode_in [5:1] + connect \DX_RT \opcode_in [25:21] + connect \DX_d0_d1_d2 { \opcode_in [15:6] \opcode_in [20:16] \opcode_in [0] } + connect \DX_d2 \opcode_in [0] + connect \DX_d1 \opcode_in [20:16] + connect \DX_d0 \opcode_in [15:6] + connect \XFX_XO \opcode_in [10:1] + connect \XFX_SPR \opcode_in [20:11] + connect \XFX_RT \opcode_in [25:21] + connect \XFX_RS \opcode_in [25:21] + connect \XFX_FXM \opcode_in [19:12] + connect \XFX_DUIS \opcode_in [20:11] + connect \XFX_DUI \opcode_in [25:21] + connect \XFX_BHRBE \opcode_in [20:11] + connect \EVS_BFA \opcode_in [2:0] + connect \Z22_XO \opcode_in [9:1] + connect \Z22_SH \opcode_in [15:10] + connect \Z22_Rc \opcode_in [0] + connect \Z22_FRTp \opcode_in [25:21] + connect \Z22_FRT \opcode_in [25:21] + connect \Z22_FRAp \opcode_in [20:16] + connect \Z22_FRA \opcode_in [20:16] + connect \Z22_DGM \opcode_in [15:10] + connect \Z22_DCM \opcode_in [15:10] + connect \Z22_BF \opcode_in [25:23] + connect \XX2_XO_1 \opcode_in [10:2] + connect \XX2_XO { \opcode_in [10:7] \opcode_in [5:3] } + connect \XX2_UIM_1 \opcode_in [17:16] + connect \XX2_UIM \opcode_in [19:16] + connect \XX2_TX_T { \opcode_in [0] \opcode_in [25:21] } + connect \XX2_T \opcode_in [25:21] + connect \XX2_TX \opcode_in [0] + connect \XX2_RT \opcode_in [25:21] + connect \XX2_EO \opcode_in [20:16] + connect \XX2_DCMX \opcode_in [22:16] + connect \XX2_dc_dm_dx { \opcode_in [6] \opcode_in [2] \opcode_in [20:16] } + connect \XX2_dx \opcode_in [20:16] + connect \XX2_dm \opcode_in [2] + connect \XX2_dc \opcode_in [6] + connect \XX2_BX_B { \opcode_in [1] \opcode_in [15:11] } + connect \XX2_B \opcode_in [15:11] + connect \XX2_BX \opcode_in [1] + connect \XX2_BF \opcode_in [25:23] + connect \D_UI \opcode_in [15:0] + connect \D_TO \opcode_in [25:21] + connect \D_SI \opcode_in [15:0] + connect \D_RT \opcode_in [25:21] + connect \D_RS \opcode_in [25:21] + connect \D_RA \opcode_in [20:16] + connect \D_L \opcode_in [21] + connect \D_FRT \opcode_in [25:21] + connect \D_FRS \opcode_in [25:21] + connect \D_D \opcode_in [15:0] + connect \D_BF \opcode_in [25:23] + connect \A_XO \opcode_in [5:1] + connect \A_RT \opcode_in [25:21] + connect \A_Rc \opcode_in [0] + connect \A_RB \opcode_in [15:11] + connect \A_RA \opcode_in [20:16] + connect \A_FRT \opcode_in [25:21] + connect \A_FRC \opcode_in [10:6] + connect \A_FRB \opcode_in [15:11] + connect \A_FRA \opcode_in [20:16] + connect \A_BC \opcode_in [10:6] + connect \XL_XO \opcode_in [10:1] + connect \XL_S \opcode_in [11] + connect \XL_OC \opcode_in [25:11] + connect \XL_LK \opcode_in [0] + connect \XL_BT \opcode_in [25:21] + connect \XL_BO_1 \opcode_in [25:21] + connect \XL_BO \opcode_in [25:21] + connect \XL_BI \opcode_in [20:16] + connect \XL_BH \opcode_in [12:11] + connect \XL_BFA \opcode_in [20:18] + connect \XL_BF \opcode_in [25:23] + connect \XL_BB \opcode_in [15:11] + connect \XL_BA \opcode_in [20:16] + connect \XX4_XO \opcode_in [5:4] + connect \XX4_TX_T { \opcode_in [0] \opcode_in [25:21] } + connect \XX4_T \opcode_in [25:21] + connect \XX4_TX \opcode_in [0] + connect \XX4_CX_C { \opcode_in [3] \opcode_in [10:6] } + connect \XX4_C \opcode_in [10:6] + connect \XX4_CX \opcode_in [3] + connect \XX4_BX_B { \opcode_in [1] \opcode_in [15:11] } + connect \XX4_B \opcode_in [15:11] + connect \XX4_BX \opcode_in [1] + connect \XX4_AX_A { \opcode_in [2] \opcode_in [20:16] } + connect \XX4_A \opcode_in [20:16] + connect \XX4_AX \opcode_in [2] + connect \XX3_XO_2 \opcode_in [9:1] + connect \XX3_XO_1 \opcode_in [10:3] + connect \XX3_XO \opcode_in [10:7] + connect \XX3_TX_T { \opcode_in [0] \opcode_in [25:21] } + connect \XX3_T \opcode_in [25:21] + connect \XX3_TX \opcode_in [0] + connect \XX3_SHW \opcode_in [9:8] + connect \XX3_Rc \opcode_in [10] + connect \XX3_DM \opcode_in [9:8] + connect \XX3_BX_B { \opcode_in [1] \opcode_in [15:11] } + connect \XX3_B \opcode_in [15:11] + connect \XX3_BX \opcode_in [1] + connect \XX3_BF \opcode_in [25:23] + connect \XX3_AX_A { \opcode_in [2] \opcode_in [20:16] } + connect \XX3_A \opcode_in [20:16] + connect \XX3_AX \opcode_in [2] + connect \I_LK \opcode_in [0] + connect \I_LI \opcode_in [25:2] + connect \I_AA \opcode_in [1] + connect \B_LK \opcode_in [0] + connect \B_BO \opcode_in [25:21] + connect \B_BI \opcode_in [20:16] + connect \B_BD \opcode_in [15:2] + connect \B_AA \opcode_in [1] + connect \X_XO_1 \opcode_in [8:1] + connect \X_XO \opcode_in [10:1] + connect \X_WC \opcode_in [22:21] + connect \X_W \opcode_in [16] + connect \X_VRT \opcode_in [25:21] + connect \X_VRS \opcode_in [25:21] + connect \X_UIM \opcode_in [20:16] + connect \X_U \opcode_in [15:12] + connect \X_TX_T { \opcode_in [0] \opcode_in [25:21] } + connect \X_TX \opcode_in [0] + connect \X_TO \opcode_in [25:21] + connect \X_TH \opcode_in [25:21] + connect \X_TBR \opcode_in [20:11] + connect \X_T \opcode_in [25:21] + connect \X_SX_S { \opcode_in [0] \opcode_in [25:21] } + connect \X_SX \opcode_in [0] + connect \X_SR \opcode_in [19:16] + connect \X_SP \opcode_in [20:19] + connect \X_SI \opcode_in [15:11] + connect \X_SH \opcode_in [15:11] + connect \X_S \opcode_in [25:21] + connect \X_RTp \opcode_in [25:21] + connect \X_RT \opcode_in [25:21] + connect \X_RSp \opcode_in [25:21] + connect \X_RS \opcode_in [25:21] + connect \X_RO \opcode_in [0] + connect \X_RM \opcode_in [12:11] + connect \X_RIC \opcode_in [19:18] + connect \X_Rc \opcode_in [0] + connect \X_RB \opcode_in [15:11] + connect \X_RA \opcode_in [20:16] + connect \X_R_1 \opcode_in [16] + connect \X_R \opcode_in [21] + connect \X_PRS \opcode_in [17] + connect \X_NB \opcode_in [15:11] + connect \X_MO \opcode_in [25:21] + connect \X_L3 \opcode_in [17:16] + connect \X_L1 \opcode_in [16] + connect \X_L \opcode_in [21] + connect \X_L2 \opcode_in [22:21] + connect \X_IMM8 \opcode_in [18:11] + connect \X_IH \opcode_in [23:21] + connect \X_FRTp \opcode_in [25:21] + connect \X_FRT \opcode_in [25:21] + connect \X_FRSp \opcode_in [25:21] + connect \X_FRS \opcode_in [25:21] + connect \X_FRBp \opcode_in [15:11] + connect \X_FRB \opcode_in [15:11] + connect \X_FRAp \opcode_in [20:16] + connect \X_FRA \opcode_in [20:16] + connect \X_FC \opcode_in [15:11] + connect \X_EX \opcode_in [0] + connect \X_EO_1 \opcode_in [20:16] + connect \X_EO \opcode_in [20:19] + connect \X_E_1 \opcode_in [19:16] + connect \X_E \opcode_in [15] + connect \X_DRM \opcode_in [13:11] + connect \X_DCMX \opcode_in [22:16] + connect \X_CT \opcode_in [24:21] + connect \X_BO \opcode_in [25:21] + connect \X_BFA \opcode_in [20:18] + connect \X_BF \opcode_in [25:23] + connect \X_A \opcode_in [25] + connect \BRANCH_SPR \opcode_in [20:11] + connect \BRANCH_MB \opcode_in [10:6] + connect \BRANCH_ME \opcode_in [5:1] + connect \BRANCH_SH \opcode_in [15:11] + connect \BRANCH_BC \opcode_in [10:6] + connect \BRANCH_TO \opcode_in [25:21] + connect \BRANCH_DS \opcode_in [15:2] + connect \BRANCH_D \opcode_in [15:0] + connect \BRANCH_BH \opcode_in [12:11] + connect \BRANCH_BI \opcode_in [20:16] + connect \BRANCH_BO \opcode_in [25:21] + connect \BRANCH_FXM \opcode_in [19:12] + connect \BRANCH_BT \opcode_in [25:21] + connect \BRANCH_BA \opcode_in [20:16] + connect \BRANCH_BB \opcode_in [15:11] + connect \BRANCH_CR \opcode_in [10:1] + connect \BRANCH_BF \opcode_in [25:23] + connect \BRANCH_BD \opcode_in [15:2] + connect \BRANCH_OE \opcode_in [10] + connect \BRANCH_Rc \opcode_in [0] + connect \BRANCH_AA \opcode_in [1] + connect \BRANCH_LK \opcode_in [0] + connect \BRANCH_LI \opcode_in [25:2] + connect \BRANCH_ME32 \opcode_in [5:1] + connect \BRANCH_MB32 \opcode_in [10:6] + connect \BRANCH_sh { \opcode_in [1] \opcode_in [15:11] } + connect \BRANCH_SH32 \opcode_in [15:11] + connect \BRANCH_L \opcode_in [21] + connect \BRANCH_UI \opcode_in [15:0] + connect \BRANCH_SI \opcode_in [15:0] + connect \BRANCH_RB \opcode_in [15:11] + connect \BRANCH_RA \opcode_in [20:16] + connect \BRANCH_RT \opcode_in [25:21] + connect \BRANCH_RS \opcode_in [25:21] + connect \opcode_in \$1 + connect \BRANCH_dec19_opcode_in \opcode_in + connect \opcode_switch \opcode_in [31:26] +end +attribute \src "issuer_ls180.v:54938.1-56685.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.dec_LOGICAL.dec" +attribute \generator "nMigen" +module \dec$152 + attribute \src "issuer_ls180.v:56244.3-56271.6" + wire width 3 $0\LOGICAL_cr_in[2:0] + attribute \src "issuer_ls180.v:56272.3-56299.6" + wire width 3 $0\LOGICAL_cr_out[2:0] + attribute \src "issuer_ls180.v:55964.3-55991.6" + wire width 2 $0\LOGICAL_cry_in[1:0] + attribute \src "issuer_ls180.v:56048.3-56075.6" + wire $0\LOGICAL_cry_out[0:0] + attribute \src "issuer_ls180.v:56132.3-56159.6" + wire width 12 $0\LOGICAL_function_unit[11:0] + attribute \src "issuer_ls180.v:56188.3-56215.6" + wire width 3 $0\LOGICAL_in1_sel[2:0] + attribute \src "issuer_ls180.v:56216.3-56243.6" + wire width 4 $0\LOGICAL_in2_sel[3:0] + attribute \src "issuer_ls180.v:56160.3-56187.6" + wire width 7 $0\LOGICAL_internal_op[6:0] + attribute \src "issuer_ls180.v:55992.3-56019.6" + wire $0\LOGICAL_inv_a[0:0] + attribute \src "issuer_ls180.v:56020.3-56047.6" + wire $0\LOGICAL_inv_out[0:0] + attribute \src "issuer_ls180.v:56076.3-56103.6" + wire $0\LOGICAL_is_32b[0:0] + attribute \src "issuer_ls180.v:56300.3-56327.6" + wire width 4 $0\LOGICAL_ldst_len[3:0] + attribute \src "issuer_ls180.v:56328.3-56355.6" + wire width 2 $0\LOGICAL_rc_sel[1:0] + attribute \src "issuer_ls180.v:56104.3-56131.6" + wire $0\LOGICAL_sgn[0:0] + attribute \src "issuer_ls180.v:54939.7-54939.20" + wire $0\initial[0:0] + attribute \src "issuer_ls180.v:56244.3-56271.6" + wire width 3 $1\LOGICAL_cr_in[2:0] + attribute \src "issuer_ls180.v:56272.3-56299.6" + wire width 3 $1\LOGICAL_cr_out[2:0] + attribute \src "issuer_ls180.v:55964.3-55991.6" + wire width 2 $1\LOGICAL_cry_in[1:0] + attribute \src "issuer_ls180.v:56048.3-56075.6" + wire $1\LOGICAL_cry_out[0:0] + attribute \src "issuer_ls180.v:56132.3-56159.6" + wire width 12 $1\LOGICAL_function_unit[11:0] + attribute \src "issuer_ls180.v:56188.3-56215.6" + wire width 3 $1\LOGICAL_in1_sel[2:0] + attribute \src "issuer_ls180.v:56216.3-56243.6" + wire width 4 $1\LOGICAL_in2_sel[3:0] + attribute \src "issuer_ls180.v:56160.3-56187.6" + wire width 7 $1\LOGICAL_internal_op[6:0] + attribute \src "issuer_ls180.v:55992.3-56019.6" + wire $1\LOGICAL_inv_a[0:0] + attribute \src "issuer_ls180.v:56020.3-56047.6" + wire $1\LOGICAL_inv_out[0:0] + attribute \src "issuer_ls180.v:56076.3-56103.6" + wire $1\LOGICAL_is_32b[0:0] + attribute \src "issuer_ls180.v:56300.3-56327.6" + wire width 4 $1\LOGICAL_ldst_len[3:0] + attribute \src "issuer_ls180.v:56328.3-56355.6" + wire width 2 $1\LOGICAL_rc_sel[1:0] + attribute \src "issuer_ls180.v:56104.3-56131.6" + wire $1\LOGICAL_sgn[0:0] + attribute \src "issuer_ls180.v:55946.17-55946.211" + wire width 32 $ternary$issuer_ls180.v:55946$3395_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:478" + wire width 32 \$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \A_BC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \A_FRA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \A_FRB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \A_FRC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \A_FRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \A_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \A_RB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \A_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \A_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \A_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \B_AA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 14 \B_BD + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \B_BI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \B_BO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \B_LK + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \DQE_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \DQE_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 2 \DQE_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 12 \DQ_DQ + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 4 \DQ_PT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \DQ_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \DQ_RTp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \DQ_S + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \DQ_SX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \DQ_SX_S + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \DQ_T + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \DQ_TX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \DQ_TX_T + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 3 \DQ_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 14 \DS_DS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \DS_FRSp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \DS_FRTp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \DS_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \DS_RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \DS_RSp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \DS_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \DS_VRS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \DS_VRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 2 \DS_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \DX_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \DX_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 10 \DX_d0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 16 \DX_d0_d1_d2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \DX_d1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \DX_d2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 3 \D_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 16 \D_D + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \D_FRS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \D_FRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \D_L + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \D_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \D_RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \D_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 16 \D_SI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \D_TO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 16 \D_UI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 3 \EVS_BFA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \I_AA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 24 \I_LI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \I_LK + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire \LOGICAL_AA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 output 27 \LOGICAL_BA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 output 26 \LOGICAL_BB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 output 32 \LOGICAL_BC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 14 output 25 \LOGICAL_BD + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 3 \LOGICAL_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 2 \LOGICAL_BH + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 output 30 \LOGICAL_BI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 \LOGICAL_BO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 output 28 \LOGICAL_BT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 10 \LOGICAL_CR + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 16 \LOGICAL_D + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 14 output 31 \LOGICAL_DS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 8 output 29 \LOGICAL_FXM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire \LOGICAL_L + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 24 output 22 \LOGICAL_LI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire \LOGICAL_LK + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 \LOGICAL_MB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 \LOGICAL_MB32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 \LOGICAL_ME + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 \LOGICAL_ME32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire output 24 \LOGICAL_OE + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 output 17 \LOGICAL_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 \LOGICAL_RB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 \LOGICAL_RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 \LOGICAL_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire output 23 \LOGICAL_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 \LOGICAL_SH + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 output 20 \LOGICAL_SH32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 16 output 18 \LOGICAL_SI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 10 \LOGICAL_SPR + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 \LOGICAL_TO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 16 output 19 \LOGICAL_UI + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 4 \LOGICAL_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 5 \LOGICAL_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 13 \LOGICAL_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 14 \LOGICAL_cry_out + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 \LOGICAL_dec31_LOGICAL_dec31_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 \LOGICAL_dec31_LOGICAL_dec31_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \LOGICAL_dec31_LOGICAL_dec31_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \LOGICAL_dec31_LOGICAL_dec31_cry_out + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 12 \LOGICAL_dec31_LOGICAL_dec31_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 \LOGICAL_dec31_LOGICAL_dec31_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 \LOGICAL_dec31_LOGICAL_dec31_in2_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 7 \LOGICAL_dec31_LOGICAL_dec31_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \LOGICAL_dec31_LOGICAL_dec31_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \LOGICAL_dec31_LOGICAL_dec31_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \LOGICAL_dec31_LOGICAL_dec31_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 \LOGICAL_dec31_LOGICAL_dec31_ldst_len + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \LOGICAL_dec31_LOGICAL_dec31_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \LOGICAL_dec31_LOGICAL_dec31_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + wire width 32 \LOGICAL_dec31_opcode_in + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 12 output 7 \LOGICAL_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 8 \LOGICAL_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 output 9 \LOGICAL_in2_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 7 output 6 \LOGICAL_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 11 \LOGICAL_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 12 \LOGICAL_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 15 \LOGICAL_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 output 10 \LOGICAL_ldst_len + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 3 \LOGICAL_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 16 \LOGICAL_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 6 output 21 \LOGICAL_sh + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \MDS_IB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \MDS_IS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \MDS_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \MDS_RB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \MDS_RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \MDS_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 4 \MDS_XBI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 4 \MDS_XBI_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 4 \MDS_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \MDS_mb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \MDS_me + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \MD_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \MD_RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \MD_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 3 \MD_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \MD_mb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \MD_me + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \MD_sh + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \M_MB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \M_ME + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \M_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \M_RB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \M_RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \M_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \M_SH + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 7 \SC_LEV + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \SC_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 2 \SC_XO_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \TX_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \TX_UI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 4 \TX_XBI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \TX_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \VA_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \VA_RB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \VA_RC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \VA_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 4 \VA_SHB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \VA_VRA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \VA_VRB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \VA_VRC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \VA_VRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \VA_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \VC_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \VC_VRA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \VC_VRB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \VC_VRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 10 \VC_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \VX_EO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \VX_PS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \VX_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \VX_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \VX_SIM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \VX_UIM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 4 \VX_UIM_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 3 \VX_UIM_2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 2 \VX_UIM_3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \VX_VRA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \VX_VRB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \VX_VRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 10 \VX_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 11 \VX_XO_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 8 \XFL_FLM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XFL_FRB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \XFL_L + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \XFL_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \XFL_W + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 10 \XFL_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 10 \XFX_BHRBE + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XFX_DUI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 10 \XFX_DUIS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 8 \XFX_FXM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XFX_RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XFX_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 10 \XFX_SPR + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 10 \XFX_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XL_BA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XL_BB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 3 \XL_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 3 \XL_BFA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 2 \XL_BH + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XL_BI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XL_BO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XL_BO_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 output 35 \XL_BT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \XL_LK + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 15 \XL_OC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \XL_S + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 10 \XL_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \XO_OE + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XO_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XO_RB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XO_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \XO_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 9 \XO_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XS_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XS_RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \XS_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 9 \XS_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \XS_sh + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XX2_B + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 3 \XX2_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \XX2_BX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \XX2_BX_B + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 7 \XX2_DCMX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XX2_EO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XX2_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XX2_T + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \XX2_TX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \XX2_TX_T + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 4 \XX2_UIM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 2 \XX2_UIM_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 7 \XX2_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 9 \XX2_XO_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \XX2_dc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 7 \XX2_dc_dm_dx + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \XX2_dm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XX2_dx + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XX3_A + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \XX3_AX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \XX3_AX_A + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XX3_B + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 3 \XX3_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \XX3_BX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \XX3_BX_B + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 2 \XX3_DM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \XX3_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 2 \XX3_SHW + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XX3_T + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \XX3_TX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \XX3_TX_T + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 4 \XX3_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 8 \XX3_XO_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 9 \XX3_XO_2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XX4_A + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \XX4_AX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \XX4_AX_A + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XX4_B + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \XX4_BX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \XX4_BX_B + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XX4_C + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \XX4_CX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \XX4_CX_C + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XX4_T + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \XX4_TX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \XX4_TX_T + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 2 \XX4_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \X_A + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 3 output 33 \X_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 3 output 34 \X_BFA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_BO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 4 \X_CT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 7 \X_DCMX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 3 \X_DRM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \X_E + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 2 \X_EO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_EO_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \X_EX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 4 \X_E_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_FC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_FRA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_FRAp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_FRB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_FRBp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_FRS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_FRSp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_FRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_FRTp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 3 \X_IH + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 8 \X_IMM8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \X_L + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \X_L1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 2 \X_L2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 2 \X_L3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_MO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_NB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \X_PRS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \X_R + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_RB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 2 \X_RIC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 2 \X_RM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \X_RO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_RSp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_RTp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \X_R_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \X_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_S + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_SH + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_SI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 2 \X_SP + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 4 \X_SR + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \X_SX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \X_SX_S + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_T + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 10 \X_TBR + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_TH + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_TO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \X_TX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \X_TX_T + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 4 \X_U + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_UIM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_VRS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_VRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \X_W + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 2 \X_WC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 10 \X_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 8 \X_XO_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 3 \Z22_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \Z22_DCM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \Z22_DGM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \Z22_FRA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \Z22_FRAp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \Z22_FRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \Z22_FRTp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \Z22_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \Z22_SH + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 9 \Z22_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \Z23_FRA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \Z23_FRAp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \Z23_FRB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \Z23_FRBp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \Z23_FRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \Z23_FRTp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \Z23_R + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 2 \Z23_RMC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \Z23_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \Z23_TE + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 8 \Z23_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \all_OPCD + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \all_PO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + wire input 1 \bigendian + attribute \src "issuer_ls180.v:54939.7-54939.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + wire width 32 output 2 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:320" + wire width 6 \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:442" + wire width 32 input 36 \raw_opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:478" + cell $mux $ternary$issuer_ls180.v:55946$3395 + parameter \WIDTH 32 + connect \A \raw_opcode_in + connect \B { \raw_opcode_in [7:0] \raw_opcode_in [15:8] \raw_opcode_in [23:16] \raw_opcode_in [31:24] } + connect \S \bigendian + connect \Y $ternary$issuer_ls180.v:55946$3395_Y + end + attribute \module_not_derived 1 + attribute \src "issuer_ls180.v:55947.17-55963.4" + cell \LOGICAL_dec31 \LOGICAL_dec31 + connect \LOGICAL_dec31_cr_in \LOGICAL_dec31_LOGICAL_dec31_cr_in + connect \LOGICAL_dec31_cr_out \LOGICAL_dec31_LOGICAL_dec31_cr_out + connect \LOGICAL_dec31_cry_in \LOGICAL_dec31_LOGICAL_dec31_cry_in + connect \LOGICAL_dec31_cry_out \LOGICAL_dec31_LOGICAL_dec31_cry_out + connect \LOGICAL_dec31_function_unit \LOGICAL_dec31_LOGICAL_dec31_function_unit + connect \LOGICAL_dec31_in1_sel \LOGICAL_dec31_LOGICAL_dec31_in1_sel + connect \LOGICAL_dec31_in2_sel \LOGICAL_dec31_LOGICAL_dec31_in2_sel + connect \LOGICAL_dec31_internal_op \LOGICAL_dec31_LOGICAL_dec31_internal_op + connect \LOGICAL_dec31_inv_a \LOGICAL_dec31_LOGICAL_dec31_inv_a + connect \LOGICAL_dec31_inv_out \LOGICAL_dec31_LOGICAL_dec31_inv_out + connect \LOGICAL_dec31_is_32b \LOGICAL_dec31_LOGICAL_dec31_is_32b + connect \LOGICAL_dec31_ldst_len \LOGICAL_dec31_LOGICAL_dec31_ldst_len + connect \LOGICAL_dec31_rc_sel \LOGICAL_dec31_LOGICAL_dec31_rc_sel + connect \LOGICAL_dec31_sgn \LOGICAL_dec31_LOGICAL_dec31_sgn + connect \opcode_in \LOGICAL_dec31_opcode_in + end + attribute \src "issuer_ls180.v:54939.7-54939.20" + process $proc$issuer_ls180.v:54939$3410 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "issuer_ls180.v:55964.3-55991.6" + process $proc$issuer_ls180.v:55964$3396 + assign { } { } + assign { } { } + assign $0\LOGICAL_cry_in[1:0] $1\LOGICAL_cry_in[1:0] + attribute \src "issuer_ls180.v:55965.5-55965.29" + switch \initial + attribute \src "issuer_ls180.v:55965.9-55965.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\LOGICAL_cry_in[1:0] \LOGICAL_dec31_LOGICAL_dec31_cry_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'011100 + assign { } { } + assign $1\LOGICAL_cry_in[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'011101 + assign { } { } + assign $1\LOGICAL_cry_in[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'011000 + assign { } { } + assign $1\LOGICAL_cry_in[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'011001 + assign { } { } + assign $1\LOGICAL_cry_in[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'011010 + assign { } { } + assign $1\LOGICAL_cry_in[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'011011 + assign { } { } + assign $1\LOGICAL_cry_in[1:0] 2'00 + case + assign $1\LOGICAL_cry_in[1:0] 2'00 + end + sync always + update \LOGICAL_cry_in $0\LOGICAL_cry_in[1:0] + end + attribute \src "issuer_ls180.v:55992.3-56019.6" + process $proc$issuer_ls180.v:55992$3397 + assign { } { } + assign { } { } + assign $0\LOGICAL_inv_a[0:0] $1\LOGICAL_inv_a[0:0] + attribute \src "issuer_ls180.v:55993.5-55993.29" + switch \initial + attribute \src "issuer_ls180.v:55993.9-55993.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\LOGICAL_inv_a[0:0] \LOGICAL_dec31_LOGICAL_dec31_inv_a + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'011100 + assign { } { } + assign $1\LOGICAL_inv_a[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'011101 + assign { } { } + assign $1\LOGICAL_inv_a[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'011000 + assign { } { } + assign $1\LOGICAL_inv_a[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'011001 + assign { } { } + assign $1\LOGICAL_inv_a[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'011010 + assign { } { } + assign $1\LOGICAL_inv_a[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'011011 + assign { } { } + assign $1\LOGICAL_inv_a[0:0] 1'0 + case + assign $1\LOGICAL_inv_a[0:0] 1'0 + end + sync always + update \LOGICAL_inv_a $0\LOGICAL_inv_a[0:0] + end + attribute \src "issuer_ls180.v:56020.3-56047.6" + process $proc$issuer_ls180.v:56020$3398 + assign { } { } + assign { } { } + assign $0\LOGICAL_inv_out[0:0] $1\LOGICAL_inv_out[0:0] + attribute \src "issuer_ls180.v:56021.5-56021.29" + switch \initial + attribute \src "issuer_ls180.v:56021.9-56021.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\LOGICAL_inv_out[0:0] \LOGICAL_dec31_LOGICAL_dec31_inv_out + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'011100 + assign { } { } + assign $1\LOGICAL_inv_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'011101 + assign { } { } + assign $1\LOGICAL_inv_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'011000 + assign { } { } + assign $1\LOGICAL_inv_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'011001 + assign { } { } + assign $1\LOGICAL_inv_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'011010 + assign { } { } + assign $1\LOGICAL_inv_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'011011 + assign { } { } + assign $1\LOGICAL_inv_out[0:0] 1'0 + case + assign $1\LOGICAL_inv_out[0:0] 1'0 + end + sync always + update \LOGICAL_inv_out $0\LOGICAL_inv_out[0:0] + end + attribute \src "issuer_ls180.v:56048.3-56075.6" + process $proc$issuer_ls180.v:56048$3399 + assign { } { } + assign { } { } + assign $0\LOGICAL_cry_out[0:0] $1\LOGICAL_cry_out[0:0] + attribute \src "issuer_ls180.v:56049.5-56049.29" + switch \initial + attribute \src "issuer_ls180.v:56049.9-56049.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\LOGICAL_cry_out[0:0] \LOGICAL_dec31_LOGICAL_dec31_cry_out + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'011100 + assign { } { } + assign $1\LOGICAL_cry_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'011101 + assign { } { } + assign $1\LOGICAL_cry_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'011000 + assign { } { } + assign $1\LOGICAL_cry_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'011001 + assign { } { } + assign $1\LOGICAL_cry_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'011010 + assign { } { } + assign $1\LOGICAL_cry_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'011011 + assign { } { } + assign $1\LOGICAL_cry_out[0:0] 1'0 + case + assign $1\LOGICAL_cry_out[0:0] 1'0 + end + sync always + update \LOGICAL_cry_out $0\LOGICAL_cry_out[0:0] + end + attribute \src "issuer_ls180.v:56076.3-56103.6" + process $proc$issuer_ls180.v:56076$3400 + assign { } { } + assign { } { } + assign $0\LOGICAL_is_32b[0:0] $1\LOGICAL_is_32b[0:0] + attribute \src "issuer_ls180.v:56077.5-56077.29" + switch \initial + attribute \src "issuer_ls180.v:56077.9-56077.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\LOGICAL_is_32b[0:0] \LOGICAL_dec31_LOGICAL_dec31_is_32b + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'011100 + assign { } { } + assign $1\LOGICAL_is_32b[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'011101 + assign { } { } + assign $1\LOGICAL_is_32b[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'011000 + assign { } { } + assign $1\LOGICAL_is_32b[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'011001 + assign { } { } + assign $1\LOGICAL_is_32b[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'011010 + assign { } { } + assign $1\LOGICAL_is_32b[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'011011 + assign { } { } + assign $1\LOGICAL_is_32b[0:0] 1'0 + case + assign $1\LOGICAL_is_32b[0:0] 1'0 + end + sync always + update \LOGICAL_is_32b $0\LOGICAL_is_32b[0:0] + end + attribute \src "issuer_ls180.v:56104.3-56131.6" + process $proc$issuer_ls180.v:56104$3401 + assign { } { } + assign { } { } + assign $0\LOGICAL_sgn[0:0] $1\LOGICAL_sgn[0:0] + attribute \src "issuer_ls180.v:56105.5-56105.29" + switch \initial + attribute \src "issuer_ls180.v:56105.9-56105.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\LOGICAL_sgn[0:0] \LOGICAL_dec31_LOGICAL_dec31_sgn + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'011100 + assign { } { } + assign $1\LOGICAL_sgn[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'011101 + assign { } { } + assign $1\LOGICAL_sgn[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'011000 + assign { } { } + assign $1\LOGICAL_sgn[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'011001 + assign { } { } + assign $1\LOGICAL_sgn[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'011010 + assign { } { } + assign $1\LOGICAL_sgn[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'011011 + assign { } { } + assign $1\LOGICAL_sgn[0:0] 1'0 + case + assign $1\LOGICAL_sgn[0:0] 1'0 + end + sync always + update \LOGICAL_sgn $0\LOGICAL_sgn[0:0] + end + attribute \src "issuer_ls180.v:56132.3-56159.6" + process $proc$issuer_ls180.v:56132$3402 + assign { } { } + assign { } { } + assign $0\LOGICAL_function_unit[11:0] $1\LOGICAL_function_unit[11:0] + attribute \src "issuer_ls180.v:56133.5-56133.29" + switch \initial + attribute \src "issuer_ls180.v:56133.9-56133.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\LOGICAL_function_unit[11:0] \LOGICAL_dec31_LOGICAL_dec31_function_unit + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'011100 + assign { } { } + assign $1\LOGICAL_function_unit[11:0] 12'000000010000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'011101 + assign { } { } + assign $1\LOGICAL_function_unit[11:0] 12'000000010000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'011000 + assign { } { } + assign $1\LOGICAL_function_unit[11:0] 12'000000010000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'011001 + assign { } { } + assign $1\LOGICAL_function_unit[11:0] 12'000000010000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'011010 + assign { } { } + assign $1\LOGICAL_function_unit[11:0] 12'000000010000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'011011 + assign { } { } + assign $1\LOGICAL_function_unit[11:0] 12'000000010000 + case + assign $1\LOGICAL_function_unit[11:0] 12'000000000000 + end + sync always + update \LOGICAL_function_unit $0\LOGICAL_function_unit[11:0] + end + attribute \src "issuer_ls180.v:56160.3-56187.6" + process $proc$issuer_ls180.v:56160$3403 + assign { } { } + assign { } { } + assign $0\LOGICAL_internal_op[6:0] $1\LOGICAL_internal_op[6:0] + attribute \src "issuer_ls180.v:56161.5-56161.29" + switch \initial + attribute \src "issuer_ls180.v:56161.9-56161.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\LOGICAL_internal_op[6:0] \LOGICAL_dec31_LOGICAL_dec31_internal_op + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'011100 + assign { } { } + assign $1\LOGICAL_internal_op[6:0] 7'0000100 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'011101 + assign { } { } + assign $1\LOGICAL_internal_op[6:0] 7'0000100 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'011000 + assign { } { } + assign $1\LOGICAL_internal_op[6:0] 7'0110101 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'011001 + assign { } { } + assign $1\LOGICAL_internal_op[6:0] 7'0110101 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'011010 + assign { } { } + assign $1\LOGICAL_internal_op[6:0] 7'1000011 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'011011 + assign { } { } + assign $1\LOGICAL_internal_op[6:0] 7'1000011 + case + assign $1\LOGICAL_internal_op[6:0] 7'0000000 + end + sync always + update \LOGICAL_internal_op $0\LOGICAL_internal_op[6:0] + end + attribute \src "issuer_ls180.v:56188.3-56215.6" + process $proc$issuer_ls180.v:56188$3404 + assign { } { } + assign { } { } + assign $0\LOGICAL_in1_sel[2:0] $1\LOGICAL_in1_sel[2:0] + attribute \src "issuer_ls180.v:56189.5-56189.29" + switch \initial + attribute \src "issuer_ls180.v:56189.9-56189.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\LOGICAL_in1_sel[2:0] \LOGICAL_dec31_LOGICAL_dec31_in1_sel + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'011100 + assign { } { } + assign $1\LOGICAL_in1_sel[2:0] 3'100 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'011101 + assign { } { } + assign $1\LOGICAL_in1_sel[2:0] 3'100 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'011000 + assign { } { } + assign $1\LOGICAL_in1_sel[2:0] 3'100 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'011001 + assign { } { } + assign $1\LOGICAL_in1_sel[2:0] 3'100 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'011010 + assign { } { } + assign $1\LOGICAL_in1_sel[2:0] 3'100 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'011011 + assign { } { } + assign $1\LOGICAL_in1_sel[2:0] 3'100 + case + assign $1\LOGICAL_in1_sel[2:0] 3'000 + end + sync always + update \LOGICAL_in1_sel $0\LOGICAL_in1_sel[2:0] + end + attribute \src "issuer_ls180.v:56216.3-56243.6" + process $proc$issuer_ls180.v:56216$3405 + assign { } { } + assign { } { } + assign $0\LOGICAL_in2_sel[3:0] $1\LOGICAL_in2_sel[3:0] + attribute \src "issuer_ls180.v:56217.5-56217.29" + switch \initial + attribute \src "issuer_ls180.v:56217.9-56217.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\LOGICAL_in2_sel[3:0] \LOGICAL_dec31_LOGICAL_dec31_in2_sel + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'011100 + assign { } { } + assign $1\LOGICAL_in2_sel[3:0] 4'0010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'011101 + assign { } { } + assign $1\LOGICAL_in2_sel[3:0] 4'0100 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'011000 + assign { } { } + assign $1\LOGICAL_in2_sel[3:0] 4'0010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'011001 + assign { } { } + assign $1\LOGICAL_in2_sel[3:0] 4'0100 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'011010 + assign { } { } + assign $1\LOGICAL_in2_sel[3:0] 4'0010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'011011 + assign { } { } + assign $1\LOGICAL_in2_sel[3:0] 4'0100 + case + assign $1\LOGICAL_in2_sel[3:0] 4'0000 + end + sync always + update \LOGICAL_in2_sel $0\LOGICAL_in2_sel[3:0] + end + attribute \src "issuer_ls180.v:56244.3-56271.6" + process $proc$issuer_ls180.v:56244$3406 + assign { } { } + assign { } { } + assign $0\LOGICAL_cr_in[2:0] $1\LOGICAL_cr_in[2:0] + attribute \src "issuer_ls180.v:56245.5-56245.29" + switch \initial + attribute \src "issuer_ls180.v:56245.9-56245.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\LOGICAL_cr_in[2:0] \LOGICAL_dec31_LOGICAL_dec31_cr_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'011100 + assign { } { } + assign $1\LOGICAL_cr_in[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'011101 + assign { } { } + assign $1\LOGICAL_cr_in[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'011000 + assign { } { } + assign $1\LOGICAL_cr_in[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'011001 + assign { } { } + assign $1\LOGICAL_cr_in[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'011010 + assign { } { } + assign $1\LOGICAL_cr_in[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'011011 + assign { } { } + assign $1\LOGICAL_cr_in[2:0] 3'000 + case + assign $1\LOGICAL_cr_in[2:0] 3'000 + end + sync always + update \LOGICAL_cr_in $0\LOGICAL_cr_in[2:0] + end + attribute \src "issuer_ls180.v:56272.3-56299.6" + process $proc$issuer_ls180.v:56272$3407 + assign { } { } + assign { } { } + assign $0\LOGICAL_cr_out[2:0] $1\LOGICAL_cr_out[2:0] + attribute \src "issuer_ls180.v:56273.5-56273.29" + switch \initial + attribute \src "issuer_ls180.v:56273.9-56273.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\LOGICAL_cr_out[2:0] \LOGICAL_dec31_LOGICAL_dec31_cr_out + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'011100 + assign { } { } + assign $1\LOGICAL_cr_out[2:0] 3'001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'011101 + assign { } { } + assign $1\LOGICAL_cr_out[2:0] 3'001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'011000 + assign { } { } + assign $1\LOGICAL_cr_out[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'011001 + assign { } { } + assign $1\LOGICAL_cr_out[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'011010 + assign { } { } + assign $1\LOGICAL_cr_out[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'011011 + assign { } { } + assign $1\LOGICAL_cr_out[2:0] 3'000 + case + assign $1\LOGICAL_cr_out[2:0] 3'000 + end + sync always + update \LOGICAL_cr_out $0\LOGICAL_cr_out[2:0] + end + attribute \src "issuer_ls180.v:56300.3-56327.6" + process $proc$issuer_ls180.v:56300$3408 + assign { } { } + assign { } { } + assign $0\LOGICAL_ldst_len[3:0] $1\LOGICAL_ldst_len[3:0] + attribute \src "issuer_ls180.v:56301.5-56301.29" + switch \initial + attribute \src "issuer_ls180.v:56301.9-56301.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\LOGICAL_ldst_len[3:0] \LOGICAL_dec31_LOGICAL_dec31_ldst_len + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'011100 + assign { } { } + assign $1\LOGICAL_ldst_len[3:0] 4'0000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'011101 + assign { } { } + assign $1\LOGICAL_ldst_len[3:0] 4'0000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'011000 + assign { } { } + assign $1\LOGICAL_ldst_len[3:0] 4'0000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'011001 + assign { } { } + assign $1\LOGICAL_ldst_len[3:0] 4'0000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'011010 + assign { } { } + assign $1\LOGICAL_ldst_len[3:0] 4'0000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'011011 + assign { } { } + assign $1\LOGICAL_ldst_len[3:0] 4'0000 + case + assign $1\LOGICAL_ldst_len[3:0] 4'0000 + end + sync always + update \LOGICAL_ldst_len $0\LOGICAL_ldst_len[3:0] + end + attribute \src "issuer_ls180.v:56328.3-56355.6" + process $proc$issuer_ls180.v:56328$3409 + assign { } { } + assign { } { } + assign $0\LOGICAL_rc_sel[1:0] $1\LOGICAL_rc_sel[1:0] + attribute \src "issuer_ls180.v:56329.5-56329.29" + switch \initial + attribute \src "issuer_ls180.v:56329.9-56329.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\LOGICAL_rc_sel[1:0] \LOGICAL_dec31_LOGICAL_dec31_rc_sel + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'011100 + assign { } { } + assign $1\LOGICAL_rc_sel[1:0] 2'01 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'011101 + assign { } { } + assign $1\LOGICAL_rc_sel[1:0] 2'01 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'011000 + assign { } { } + assign $1\LOGICAL_rc_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'011001 + assign { } { } + assign $1\LOGICAL_rc_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'011010 + assign { } { } + assign $1\LOGICAL_rc_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'011011 + assign { } { } + assign $1\LOGICAL_rc_sel[1:0] 2'00 + case + assign $1\LOGICAL_rc_sel[1:0] 2'00 + end + sync always + update \LOGICAL_rc_sel $0\LOGICAL_rc_sel[1:0] + end + connect \$1 $ternary$issuer_ls180.v:55946$3395_Y + connect \VC_XO \opcode_in [9:0] + connect \VC_VRT \opcode_in [25:21] + connect \VC_VRB \opcode_in [15:11] + connect \VC_VRA \opcode_in [20:16] + connect \VC_Rc \opcode_in [10] + connect \XS_XO \opcode_in [10:2] + connect \XS_sh { \opcode_in [1] \opcode_in [15:11] } + connect \XS_RS \opcode_in [25:21] + connect \XS_Rc \opcode_in [0] + connect \XS_RA \opcode_in [20:16] + connect \VA_XO \opcode_in [5:0] + connect \VA_VRT \opcode_in [25:21] + connect \VA_VRC \opcode_in [10:6] + connect \VA_VRB \opcode_in [15:11] + connect \VA_VRA \opcode_in [20:16] + connect \VA_SHB \opcode_in [9:6] + connect \VA_RT \opcode_in [25:21] + connect \VA_RC \opcode_in [10:6] + connect \VA_RB \opcode_in [15:11] + connect \VA_RA \opcode_in [20:16] + connect \TX_XO \opcode_in [6:1] + connect \TX_XBI \opcode_in [10:7] + connect \TX_UI \opcode_in [15:11] + connect \TX_RA \opcode_in [20:16] + connect \DQE_XO \opcode_in [1:0] + connect \DQE_RT \opcode_in [25:21] + connect \DQE_RA \opcode_in [20:16] + connect \XO_XO \opcode_in [9:1] + connect \XO_RT \opcode_in [25:21] + connect \XO_Rc \opcode_in [0] + connect \XO_RB \opcode_in [15:11] + connect \XO_RA \opcode_in [20:16] + connect \XO_OE \opcode_in [10] + connect \all_PO \opcode_in [31:26] + connect \all_OPCD \opcode_in [31:26] + connect \MD_XO \opcode_in [4:2] + connect \MD_sh { \opcode_in [1] \opcode_in [15:11] } + connect \MD_RS \opcode_in [25:21] + connect \MD_Rc \opcode_in [0] + connect \MD_RA \opcode_in [20:16] + connect \MD_me \opcode_in [10:5] + connect \MD_mb \opcode_in [10:5] + connect \M_SH \opcode_in [15:11] + connect \M_RS \opcode_in [25:21] + connect \M_Rc \opcode_in [0] + connect \M_RB \opcode_in [15:11] + connect \M_RA \opcode_in [20:16] + connect \M_ME \opcode_in [5:1] + connect \M_MB \opcode_in [10:6] + connect \SC_XO_1 \opcode_in [1:0] + connect \SC_XO \opcode_in [1] + connect \SC_LEV \opcode_in [11:5] + connect \MDS_XO \opcode_in [4:1] + connect \MDS_XBI_1 \opcode_in [10:7] + connect \MDS_XBI \opcode_in [10:7] + connect \MDS_RS \opcode_in [25:21] + connect \MDS_Rc \opcode_in [0] + connect \MDS_RB \opcode_in [15:11] + connect \MDS_RA \opcode_in [20:16] + connect \MDS_me \opcode_in [10:5] + connect \MDS_mb \opcode_in [10:5] + connect \MDS_IS \opcode_in [25:21] + connect \MDS_IB \opcode_in [15:11] + connect \Z23_XO \opcode_in [8:1] + connect \Z23_TE \opcode_in [20:16] + connect \Z23_RMC \opcode_in [10:9] + connect \Z23_Rc \opcode_in [0] + connect \Z23_R \opcode_in [16] + connect \Z23_FRTp \opcode_in [25:21] + connect \Z23_FRT \opcode_in [25:21] + connect \Z23_FRBp \opcode_in [15:11] + connect \Z23_FRB \opcode_in [15:11] + connect \Z23_FRAp \opcode_in [20:16] + connect \Z23_FRA \opcode_in [20:16] + connect \XFL_XO \opcode_in [10:1] + connect \XFL_W \opcode_in [16] + connect \XFL_Rc \opcode_in [0] + connect \XFL_L \opcode_in [25] + connect \XFL_FRB \opcode_in [15:11] + connect \XFL_FLM \opcode_in [24:17] + connect \VX_XO_1 \opcode_in [10:0] + connect \VX_XO { \opcode_in [10] \opcode_in [8:0] } + connect \VX_VRT \opcode_in [25:21] + connect \VX_VRB \opcode_in [15:11] + connect \VX_VRA \opcode_in [20:16] + connect \VX_UIM_3 \opcode_in [17:16] + connect \VX_UIM_2 \opcode_in [18:16] + connect \VX_UIM_1 \opcode_in [19:16] + connect \VX_UIM \opcode_in [20:16] + connect \VX_SIM \opcode_in [20:16] + connect \VX_RT \opcode_in [25:21] + connect \VX_RA \opcode_in [20:16] + connect \VX_PS \opcode_in [9] + connect \VX_EO \opcode_in [20:16] + connect \DS_XO \opcode_in [1:0] + connect \DS_VRT \opcode_in [25:21] + connect \DS_VRS \opcode_in [25:21] + connect \DS_RT \opcode_in [25:21] + connect \DS_RSp \opcode_in [25:21] + connect \DS_RS \opcode_in [25:21] + connect \DS_RA \opcode_in [20:16] + connect \DS_FRTp \opcode_in [25:21] + connect \DS_FRSp \opcode_in [25:21] + connect \DS_DS \opcode_in [15:2] + connect \DQ_XO \opcode_in [2:0] + connect \DQ_TX_T { \opcode_in [3] \opcode_in [25:21] } + connect \DQ_T \opcode_in [25:21] + connect \DQ_TX \opcode_in [3] + connect \DQ_SX_S { \opcode_in [3] \opcode_in [25:21] } + connect \DQ_S \opcode_in [25:21] + connect \DQ_SX \opcode_in [3] + connect \DQ_RTp \opcode_in [25:21] + connect \DQ_RA \opcode_in [20:16] + connect \DQ_PT \opcode_in [3:0] + connect \DQ_DQ \opcode_in [15:4] + connect \DX_XO \opcode_in [5:1] + connect \DX_RT \opcode_in [25:21] + connect \DX_d0_d1_d2 { \opcode_in [15:6] \opcode_in [20:16] \opcode_in [0] } + connect \DX_d2 \opcode_in [0] + connect \DX_d1 \opcode_in [20:16] + connect \DX_d0 \opcode_in [15:6] + connect \XFX_XO \opcode_in [10:1] + connect \XFX_SPR \opcode_in [20:11] + connect \XFX_RT \opcode_in [25:21] + connect \XFX_RS \opcode_in [25:21] + connect \XFX_FXM \opcode_in [19:12] + connect \XFX_DUIS \opcode_in [20:11] + connect \XFX_DUI \opcode_in [25:21] + connect \XFX_BHRBE \opcode_in [20:11] + connect \EVS_BFA \opcode_in [2:0] + connect \Z22_XO \opcode_in [9:1] + connect \Z22_SH \opcode_in [15:10] + connect \Z22_Rc \opcode_in [0] + connect \Z22_FRTp \opcode_in [25:21] + connect \Z22_FRT \opcode_in [25:21] + connect \Z22_FRAp \opcode_in [20:16] + connect \Z22_FRA \opcode_in [20:16] + connect \Z22_DGM \opcode_in [15:10] + connect \Z22_DCM \opcode_in [15:10] + connect \Z22_BF \opcode_in [25:23] + connect \XX2_XO_1 \opcode_in [10:2] + connect \XX2_XO { \opcode_in [10:7] \opcode_in [5:3] } + connect \XX2_UIM_1 \opcode_in [17:16] + connect \XX2_UIM \opcode_in [19:16] + connect \XX2_TX_T { \opcode_in [0] \opcode_in [25:21] } + connect \XX2_T \opcode_in [25:21] + connect \XX2_TX \opcode_in [0] + connect \XX2_RT \opcode_in [25:21] + connect \XX2_EO \opcode_in [20:16] + connect \XX2_DCMX \opcode_in [22:16] + connect \XX2_dc_dm_dx { \opcode_in [6] \opcode_in [2] \opcode_in [20:16] } + connect \XX2_dx \opcode_in [20:16] + connect \XX2_dm \opcode_in [2] + connect \XX2_dc \opcode_in [6] + connect \XX2_BX_B { \opcode_in [1] \opcode_in [15:11] } + connect \XX2_B \opcode_in [15:11] + connect \XX2_BX \opcode_in [1] + connect \XX2_BF \opcode_in [25:23] + connect \D_UI \opcode_in [15:0] + connect \D_TO \opcode_in [25:21] + connect \D_SI \opcode_in [15:0] + connect \D_RT \opcode_in [25:21] + connect \D_RS \opcode_in [25:21] + connect \D_RA \opcode_in [20:16] + connect \D_L \opcode_in [21] + connect \D_FRT \opcode_in [25:21] + connect \D_FRS \opcode_in [25:21] + connect \D_D \opcode_in [15:0] + connect \D_BF \opcode_in [25:23] + connect \A_XO \opcode_in [5:1] + connect \A_RT \opcode_in [25:21] + connect \A_Rc \opcode_in [0] + connect \A_RB \opcode_in [15:11] + connect \A_RA \opcode_in [20:16] + connect \A_FRT \opcode_in [25:21] + connect \A_FRC \opcode_in [10:6] + connect \A_FRB \opcode_in [15:11] + connect \A_FRA \opcode_in [20:16] + connect \A_BC \opcode_in [10:6] + connect \XL_XO \opcode_in [10:1] + connect \XL_S \opcode_in [11] + connect \XL_OC \opcode_in [25:11] + connect \XL_LK \opcode_in [0] + connect \XL_BT \opcode_in [25:21] + connect \XL_BO_1 \opcode_in [25:21] + connect \XL_BO \opcode_in [25:21] + connect \XL_BI \opcode_in [20:16] + connect \XL_BH \opcode_in [12:11] + connect \XL_BFA \opcode_in [20:18] + connect \XL_BF \opcode_in [25:23] + connect \XL_BB \opcode_in [15:11] + connect \XL_BA \opcode_in [20:16] + connect \XX4_XO \opcode_in [5:4] + connect \XX4_TX_T { \opcode_in [0] \opcode_in [25:21] } + connect \XX4_T \opcode_in [25:21] + connect \XX4_TX \opcode_in [0] + connect \XX4_CX_C { \opcode_in [3] \opcode_in [10:6] } + connect \XX4_C \opcode_in [10:6] + connect \XX4_CX \opcode_in [3] + connect \XX4_BX_B { \opcode_in [1] \opcode_in [15:11] } + connect \XX4_B \opcode_in [15:11] + connect \XX4_BX \opcode_in [1] + connect \XX4_AX_A { \opcode_in [2] \opcode_in [20:16] } + connect \XX4_A \opcode_in [20:16] + connect \XX4_AX \opcode_in [2] + connect \XX3_XO_2 \opcode_in [9:1] + connect \XX3_XO_1 \opcode_in [10:3] + connect \XX3_XO \opcode_in [10:7] + connect \XX3_TX_T { \opcode_in [0] \opcode_in [25:21] } + connect \XX3_T \opcode_in [25:21] + connect \XX3_TX \opcode_in [0] + connect \XX3_SHW \opcode_in [9:8] + connect \XX3_Rc \opcode_in [10] + connect \XX3_DM \opcode_in [9:8] + connect \XX3_BX_B { \opcode_in [1] \opcode_in [15:11] } + connect \XX3_B \opcode_in [15:11] + connect \XX3_BX \opcode_in [1] + connect \XX3_BF \opcode_in [25:23] + connect \XX3_AX_A { \opcode_in [2] \opcode_in [20:16] } + connect \XX3_A \opcode_in [20:16] + connect \XX3_AX \opcode_in [2] + connect \I_LK \opcode_in [0] + connect \I_LI \opcode_in [25:2] + connect \I_AA \opcode_in [1] + connect \B_LK \opcode_in [0] + connect \B_BO \opcode_in [25:21] + connect \B_BI \opcode_in [20:16] + connect \B_BD \opcode_in [15:2] + connect \B_AA \opcode_in [1] + connect \X_XO_1 \opcode_in [8:1] + connect \X_XO \opcode_in [10:1] + connect \X_WC \opcode_in [22:21] + connect \X_W \opcode_in [16] + connect \X_VRT \opcode_in [25:21] + connect \X_VRS \opcode_in [25:21] + connect \X_UIM \opcode_in [20:16] + connect \X_U \opcode_in [15:12] + connect \X_TX_T { \opcode_in [0] \opcode_in [25:21] } + connect \X_TX \opcode_in [0] + connect \X_TO \opcode_in [25:21] + connect \X_TH \opcode_in [25:21] + connect \X_TBR \opcode_in [20:11] + connect \X_T \opcode_in [25:21] + connect \X_SX_S { \opcode_in [0] \opcode_in [25:21] } + connect \X_SX \opcode_in [0] + connect \X_SR \opcode_in [19:16] + connect \X_SP \opcode_in [20:19] + connect \X_SI \opcode_in [15:11] + connect \X_SH \opcode_in [15:11] + connect \X_S \opcode_in [25:21] + connect \X_RTp \opcode_in [25:21] + connect \X_RT \opcode_in [25:21] + connect \X_RSp \opcode_in [25:21] + connect \X_RS \opcode_in [25:21] + connect \X_RO \opcode_in [0] + connect \X_RM \opcode_in [12:11] + connect \X_RIC \opcode_in [19:18] + connect \X_Rc \opcode_in [0] + connect \X_RB \opcode_in [15:11] + connect \X_RA \opcode_in [20:16] + connect \X_R_1 \opcode_in [16] + connect \X_R \opcode_in [21] + connect \X_PRS \opcode_in [17] + connect \X_NB \opcode_in [15:11] + connect \X_MO \opcode_in [25:21] + connect \X_L3 \opcode_in [17:16] + connect \X_L1 \opcode_in [16] + connect \X_L \opcode_in [21] + connect \X_L2 \opcode_in [22:21] + connect \X_IMM8 \opcode_in [18:11] + connect \X_IH \opcode_in [23:21] + connect \X_FRTp \opcode_in [25:21] + connect \X_FRT \opcode_in [25:21] + connect \X_FRSp \opcode_in [25:21] + connect \X_FRS \opcode_in [25:21] + connect \X_FRBp \opcode_in [15:11] + connect \X_FRB \opcode_in [15:11] + connect \X_FRAp \opcode_in [20:16] + connect \X_FRA \opcode_in [20:16] + connect \X_FC \opcode_in [15:11] + connect \X_EX \opcode_in [0] + connect \X_EO_1 \opcode_in [20:16] + connect \X_EO \opcode_in [20:19] + connect \X_E_1 \opcode_in [19:16] + connect \X_E \opcode_in [15] + connect \X_DRM \opcode_in [13:11] + connect \X_DCMX \opcode_in [22:16] + connect \X_CT \opcode_in [24:21] + connect \X_BO \opcode_in [25:21] + connect \X_BFA \opcode_in [20:18] + connect \X_BF \opcode_in [25:23] + connect \X_A \opcode_in [25] + connect \LOGICAL_SPR \opcode_in [20:11] + connect \LOGICAL_MB \opcode_in [10:6] + connect \LOGICAL_ME \opcode_in [5:1] + connect \LOGICAL_SH \opcode_in [15:11] + connect \LOGICAL_BC \opcode_in [10:6] + connect \LOGICAL_TO \opcode_in [25:21] + connect \LOGICAL_DS \opcode_in [15:2] + connect \LOGICAL_D \opcode_in [15:0] + connect \LOGICAL_BH \opcode_in [12:11] + connect \LOGICAL_BI \opcode_in [20:16] + connect \LOGICAL_BO \opcode_in [25:21] + connect \LOGICAL_FXM \opcode_in [19:12] + connect \LOGICAL_BT \opcode_in [25:21] + connect \LOGICAL_BA \opcode_in [20:16] + connect \LOGICAL_BB \opcode_in [15:11] + connect \LOGICAL_CR \opcode_in [10:1] + connect \LOGICAL_BF \opcode_in [25:23] + connect \LOGICAL_BD \opcode_in [15:2] + connect \LOGICAL_OE \opcode_in [10] + connect \LOGICAL_Rc \opcode_in [0] + connect \LOGICAL_AA \opcode_in [1] + connect \LOGICAL_LK \opcode_in [0] + connect \LOGICAL_LI \opcode_in [25:2] + connect \LOGICAL_ME32 \opcode_in [5:1] + connect \LOGICAL_MB32 \opcode_in [10:6] + connect \LOGICAL_sh { \opcode_in [1] \opcode_in [15:11] } + connect \LOGICAL_SH32 \opcode_in [15:11] + connect \LOGICAL_L \opcode_in [21] + connect \LOGICAL_UI \opcode_in [15:0] + connect \LOGICAL_SI \opcode_in [15:0] + connect \LOGICAL_RB \opcode_in [15:11] + connect \LOGICAL_RA \opcode_in [20:16] + connect \LOGICAL_RT \opcode_in [25:21] + connect \LOGICAL_RS \opcode_in [25:21] + connect \opcode_in \$1 + connect \LOGICAL_dec31_opcode_in \opcode_in + connect \opcode_switch \opcode_in [31:26] +end +attribute \src "issuer_ls180.v:56689.1-57994.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.dec_SPR.dec" +attribute \generator "nMigen" +module \dec$161 + attribute \src "issuer_ls180.v:57625.3-57634.6" + wire width 3 $0\SPR_cr_in[2:0] + attribute \src "issuer_ls180.v:57635.3-57644.6" + wire width 3 $0\SPR_cr_out[2:0] + attribute \src "issuer_ls180.v:57605.3-57614.6" + wire width 12 $0\SPR_function_unit[11:0] + attribute \src "issuer_ls180.v:57615.3-57624.6" + wire width 7 $0\SPR_internal_op[6:0] + attribute \src "issuer_ls180.v:57655.3-57664.6" + wire $0\SPR_is_32b[0:0] + attribute \src "issuer_ls180.v:57645.3-57654.6" + wire width 2 $0\SPR_rc_sel[1:0] + attribute \src "issuer_ls180.v:56690.7-56690.20" + wire $0\initial[0:0] + attribute \src "issuer_ls180.v:57625.3-57634.6" + wire width 3 $1\SPR_cr_in[2:0] + attribute \src "issuer_ls180.v:57635.3-57644.6" + wire width 3 $1\SPR_cr_out[2:0] + attribute \src "issuer_ls180.v:57605.3-57614.6" + wire width 12 $1\SPR_function_unit[11:0] + attribute \src "issuer_ls180.v:57615.3-57624.6" + wire width 7 $1\SPR_internal_op[6:0] + attribute \src "issuer_ls180.v:57655.3-57664.6" + wire $1\SPR_is_32b[0:0] + attribute \src "issuer_ls180.v:57645.3-57654.6" + wire width 2 $1\SPR_rc_sel[1:0] + attribute \src "issuer_ls180.v:57595.17-57595.211" + wire width 32 $ternary$issuer_ls180.v:57595$3411_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:478" + wire width 32 \$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \A_BC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \A_FRA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \A_FRB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \A_FRC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \A_FRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \A_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \A_RB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \A_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \A_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \A_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \B_AA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 14 \B_BD + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \B_BI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \B_BO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \B_LK + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \DQE_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \DQE_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 2 \DQE_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 12 \DQ_DQ + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 4 \DQ_PT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \DQ_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \DQ_RTp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \DQ_S + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \DQ_SX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \DQ_SX_S + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \DQ_T + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \DQ_TX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \DQ_TX_T + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 3 \DQ_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 14 \DS_DS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \DS_FRSp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \DS_FRTp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \DS_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \DS_RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \DS_RSp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \DS_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \DS_VRS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \DS_VRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 2 \DS_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \DX_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \DX_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 10 \DX_d0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 16 \DX_d0_d1_d2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \DX_d1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \DX_d2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 3 \D_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 16 \D_D + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \D_FRS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \D_FRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \D_L + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \D_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \D_RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \D_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 16 \D_SI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \D_TO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 16 \D_UI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 3 \EVS_BFA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \I_AA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 24 \I_LI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \I_LK + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \MDS_IB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \MDS_IS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \MDS_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \MDS_RB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \MDS_RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \MDS_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 4 \MDS_XBI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 4 \MDS_XBI_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 4 \MDS_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \MDS_mb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \MDS_me + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \MD_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \MD_RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \MD_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 3 \MD_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \MD_mb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \MD_me + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \MD_sh + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \M_MB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \M_ME + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \M_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \M_RB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \M_RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \M_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \M_SH + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 7 \SC_LEV + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \SC_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 2 \SC_XO_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire \SPR_AA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 output 12 \SPR_BA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 output 11 \SPR_BB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 output 16 \SPR_BC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 14 \SPR_BD + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 3 \SPR_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 2 \SPR_BH + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 output 15 \SPR_BI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 \SPR_BO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 output 13 \SPR_BT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 10 \SPR_CR + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 16 \SPR_D + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 14 \SPR_DS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 8 output 14 \SPR_FXM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire \SPR_L + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 24 \SPR_LI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire \SPR_LK + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 \SPR_MB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 \SPR_MB32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 \SPR_ME + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 \SPR_ME32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire output 10 \SPR_OE + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 \SPR_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 \SPR_RB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 \SPR_RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 \SPR_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire output 9 \SPR_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 \SPR_SH + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 \SPR_SH32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 16 \SPR_SI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 10 \SPR_SPR + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 \SPR_TO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 16 \SPR_UI + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 4 \SPR_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 5 \SPR_cr_out + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 \SPR_dec31_SPR_dec31_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 \SPR_dec31_SPR_dec31_cr_out + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 12 \SPR_dec31_SPR_dec31_function_unit + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 7 \SPR_dec31_SPR_dec31_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \SPR_dec31_SPR_dec31_is_32b + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \SPR_dec31_SPR_dec31_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + wire width 32 \SPR_dec31_opcode_in + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 12 output 7 \SPR_function_unit + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 7 output 6 \SPR_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 8 \SPR_is_32b + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 3 \SPR_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 6 \SPR_sh + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \TX_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \TX_UI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 4 \TX_XBI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \TX_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \VA_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \VA_RB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \VA_RC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \VA_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 4 \VA_SHB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \VA_VRA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \VA_VRB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \VA_VRC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \VA_VRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \VA_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \VC_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \VC_VRA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \VC_VRB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \VC_VRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 10 \VC_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \VX_EO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \VX_PS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \VX_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \VX_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \VX_SIM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \VX_UIM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 4 \VX_UIM_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 3 \VX_UIM_2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 2 \VX_UIM_3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \VX_VRA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \VX_VRB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \VX_VRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 10 \VX_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 11 \VX_XO_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 8 \XFL_FLM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XFL_FRB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \XFL_L + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \XFL_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \XFL_W + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 10 \XFL_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 10 \XFX_BHRBE + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XFX_DUI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 10 \XFX_DUIS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 8 \XFX_FXM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XFX_RS + attribute \src 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"/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:442" + wire width 32 input 20 \raw_opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:478" + cell $mux $ternary$issuer_ls180.v:57595$3411 + parameter \WIDTH 32 + connect \A \raw_opcode_in + connect \B { \raw_opcode_in [7:0] \raw_opcode_in [15:8] \raw_opcode_in [23:16] \raw_opcode_in [31:24] } + connect \S \bigendian + connect \Y $ternary$issuer_ls180.v:57595$3411_Y + end + attribute \module_not_derived 1 + attribute \src "issuer_ls180.v:57596.13-57604.4" + cell \SPR_dec31 \SPR_dec31 + connect \SPR_dec31_cr_in \SPR_dec31_SPR_dec31_cr_in + connect \SPR_dec31_cr_out \SPR_dec31_SPR_dec31_cr_out + connect \SPR_dec31_function_unit \SPR_dec31_SPR_dec31_function_unit + connect \SPR_dec31_internal_op \SPR_dec31_SPR_dec31_internal_op + connect \SPR_dec31_is_32b \SPR_dec31_SPR_dec31_is_32b + connect \SPR_dec31_rc_sel \SPR_dec31_SPR_dec31_rc_sel + connect \opcode_in \SPR_dec31_opcode_in + end + attribute \src "issuer_ls180.v:56690.7-56690.20" + process $proc$issuer_ls180.v:56690$3418 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "issuer_ls180.v:57605.3-57614.6" + process $proc$issuer_ls180.v:57605$3412 + assign { } { } + assign { } { } + assign $0\SPR_function_unit[11:0] $1\SPR_function_unit[11:0] + attribute \src "issuer_ls180.v:57606.5-57606.29" + switch \initial + attribute \src "issuer_ls180.v:57606.9-57606.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\SPR_function_unit[11:0] \SPR_dec31_SPR_dec31_function_unit + case + assign $1\SPR_function_unit[11:0] 12'000000000000 + end + sync always + update \SPR_function_unit $0\SPR_function_unit[11:0] + end + attribute \src "issuer_ls180.v:57615.3-57624.6" + process $proc$issuer_ls180.v:57615$3413 + assign { } { } + assign { } { } + assign $0\SPR_internal_op[6:0] $1\SPR_internal_op[6:0] + attribute \src "issuer_ls180.v:57616.5-57616.29" + switch \initial + attribute \src "issuer_ls180.v:57616.9-57616.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\SPR_internal_op[6:0] \SPR_dec31_SPR_dec31_internal_op + case + assign $1\SPR_internal_op[6:0] 7'0000000 + end + sync always + update \SPR_internal_op $0\SPR_internal_op[6:0] + end + attribute \src "issuer_ls180.v:57625.3-57634.6" + process $proc$issuer_ls180.v:57625$3414 + assign { } { } + assign { } { } + assign $0\SPR_cr_in[2:0] $1\SPR_cr_in[2:0] + attribute \src "issuer_ls180.v:57626.5-57626.29" + switch \initial + attribute \src "issuer_ls180.v:57626.9-57626.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\SPR_cr_in[2:0] \SPR_dec31_SPR_dec31_cr_in + case + assign $1\SPR_cr_in[2:0] 3'000 + end + sync always + update \SPR_cr_in $0\SPR_cr_in[2:0] + end + attribute \src "issuer_ls180.v:57635.3-57644.6" + process $proc$issuer_ls180.v:57635$3415 + assign { } { } + assign { } { } + assign $0\SPR_cr_out[2:0] $1\SPR_cr_out[2:0] + attribute \src "issuer_ls180.v:57636.5-57636.29" + switch \initial + attribute \src "issuer_ls180.v:57636.9-57636.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\SPR_cr_out[2:0] \SPR_dec31_SPR_dec31_cr_out + case + assign $1\SPR_cr_out[2:0] 3'000 + end + sync always + update \SPR_cr_out $0\SPR_cr_out[2:0] + end + attribute \src "issuer_ls180.v:57645.3-57654.6" + process $proc$issuer_ls180.v:57645$3416 + assign { } { } + assign { } { } + assign $0\SPR_rc_sel[1:0] $1\SPR_rc_sel[1:0] + attribute \src "issuer_ls180.v:57646.5-57646.29" + switch \initial + attribute \src "issuer_ls180.v:57646.9-57646.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\SPR_rc_sel[1:0] \SPR_dec31_SPR_dec31_rc_sel + case + assign $1\SPR_rc_sel[1:0] 2'00 + end + sync always + update \SPR_rc_sel $0\SPR_rc_sel[1:0] + end + attribute \src "issuer_ls180.v:57655.3-57664.6" + process $proc$issuer_ls180.v:57655$3417 + assign { } { } + assign { } { } + assign $0\SPR_is_32b[0:0] $1\SPR_is_32b[0:0] + attribute \src "issuer_ls180.v:57656.5-57656.29" + switch \initial + attribute \src "issuer_ls180.v:57656.9-57656.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\SPR_is_32b[0:0] \SPR_dec31_SPR_dec31_is_32b + case + assign $1\SPR_is_32b[0:0] 1'0 + end + sync always + update \SPR_is_32b $0\SPR_is_32b[0:0] + end + connect \$1 $ternary$issuer_ls180.v:57595$3411_Y + connect \VC_XO \opcode_in [9:0] + connect \VC_VRT \opcode_in [25:21] + connect \VC_VRB \opcode_in [15:11] + connect \VC_VRA \opcode_in [20:16] + connect \VC_Rc \opcode_in [10] + connect \XS_XO \opcode_in [10:2] + connect \XS_sh { \opcode_in [1] \opcode_in [15:11] } + connect \XS_RS \opcode_in [25:21] + connect \XS_Rc \opcode_in [0] + connect \XS_RA \opcode_in [20:16] + connect \VA_XO \opcode_in [5:0] + connect \VA_VRT \opcode_in [25:21] + connect \VA_VRC \opcode_in [10:6] + connect \VA_VRB \opcode_in [15:11] + connect \VA_VRA \opcode_in [20:16] + connect \VA_SHB \opcode_in [9:6] + connect \VA_RT \opcode_in [25:21] + connect \VA_RC \opcode_in [10:6] + connect \VA_RB \opcode_in [15:11] + connect \VA_RA \opcode_in [20:16] + connect \TX_XO \opcode_in [6:1] + connect \TX_XBI \opcode_in [10:7] + connect \TX_UI \opcode_in [15:11] + connect \TX_RA \opcode_in [20:16] + connect \DQE_XO \opcode_in [1:0] + connect \DQE_RT \opcode_in [25:21] + connect \DQE_RA \opcode_in [20:16] + connect \XO_XO \opcode_in [9:1] + connect \XO_RT \opcode_in [25:21] + connect \XO_Rc \opcode_in [0] + connect \XO_RB \opcode_in [15:11] + connect \XO_RA \opcode_in [20:16] + connect \XO_OE \opcode_in [10] + connect \all_PO \opcode_in [31:26] + connect \all_OPCD \opcode_in [31:26] + connect \MD_XO \opcode_in [4:2] + connect \MD_sh { \opcode_in [1] \opcode_in [15:11] } + connect \MD_RS \opcode_in [25:21] + connect \MD_Rc \opcode_in [0] + connect \MD_RA \opcode_in [20:16] + connect \MD_me \opcode_in [10:5] + connect \MD_mb \opcode_in [10:5] + connect \M_SH \opcode_in [15:11] + connect \M_RS \opcode_in [25:21] + connect \M_Rc \opcode_in [0] + connect \M_RB \opcode_in [15:11] + connect \M_RA \opcode_in [20:16] + connect \M_ME \opcode_in [5:1] + connect \M_MB \opcode_in [10:6] + connect \SC_XO_1 \opcode_in [1:0] + connect \SC_XO \opcode_in [1] + connect \SC_LEV \opcode_in [11:5] + connect \MDS_XO \opcode_in [4:1] + connect \MDS_XBI_1 \opcode_in [10:7] + connect \MDS_XBI \opcode_in [10:7] + connect \MDS_RS \opcode_in [25:21] + connect \MDS_Rc \opcode_in [0] + connect \MDS_RB \opcode_in [15:11] + connect \MDS_RA \opcode_in [20:16] + connect \MDS_me \opcode_in [10:5] + connect \MDS_mb \opcode_in [10:5] + connect \MDS_IS \opcode_in [25:21] + connect \MDS_IB \opcode_in [15:11] + connect \Z23_XO \opcode_in [8:1] + connect \Z23_TE \opcode_in [20:16] + connect \Z23_RMC \opcode_in [10:9] + connect \Z23_Rc \opcode_in [0] + connect \Z23_R \opcode_in [16] + connect \Z23_FRTp \opcode_in [25:21] + connect \Z23_FRT \opcode_in [25:21] + connect \Z23_FRBp \opcode_in [15:11] + connect \Z23_FRB \opcode_in [15:11] + connect \Z23_FRAp \opcode_in [20:16] + connect \Z23_FRA \opcode_in [20:16] + connect \XFL_XO \opcode_in [10:1] + connect \XFL_W \opcode_in [16] + connect \XFL_Rc \opcode_in [0] + connect \XFL_L \opcode_in [25] + connect \XFL_FRB \opcode_in [15:11] + connect \XFL_FLM \opcode_in [24:17] + connect \VX_XO_1 \opcode_in [10:0] + connect \VX_XO { \opcode_in [10] \opcode_in [8:0] } + connect \VX_VRT \opcode_in [25:21] + connect \VX_VRB \opcode_in [15:11] + connect \VX_VRA \opcode_in [20:16] + connect \VX_UIM_3 \opcode_in [17:16] + connect \VX_UIM_2 \opcode_in [18:16] + connect \VX_UIM_1 \opcode_in [19:16] + connect \VX_UIM \opcode_in [20:16] + connect \VX_SIM \opcode_in [20:16] + connect \VX_RT \opcode_in [25:21] + connect \VX_RA \opcode_in [20:16] + connect \VX_PS \opcode_in [9] + connect \VX_EO \opcode_in [20:16] + connect \DS_XO \opcode_in [1:0] + connect \DS_VRT \opcode_in [25:21] + connect \DS_VRS \opcode_in [25:21] + connect \DS_RT \opcode_in [25:21] + connect \DS_RSp \opcode_in [25:21] + connect \DS_RS \opcode_in [25:21] + connect \DS_RA \opcode_in [20:16] + connect \DS_FRTp \opcode_in [25:21] + connect \DS_FRSp \opcode_in [25:21] + connect \DS_DS \opcode_in [15:2] + connect \DQ_XO \opcode_in [2:0] + connect \DQ_TX_T { \opcode_in [3] \opcode_in [25:21] } + connect \DQ_T \opcode_in [25:21] + connect \DQ_TX \opcode_in [3] + connect \DQ_SX_S { \opcode_in [3] \opcode_in [25:21] } + connect \DQ_S \opcode_in [25:21] + connect \DQ_SX \opcode_in [3] + connect \DQ_RTp \opcode_in [25:21] + connect \DQ_RA \opcode_in [20:16] + connect \DQ_PT \opcode_in [3:0] + connect \DQ_DQ \opcode_in [15:4] + connect \DX_XO \opcode_in [5:1] + connect \DX_RT \opcode_in [25:21] + connect \DX_d0_d1_d2 { \opcode_in [15:6] \opcode_in [20:16] \opcode_in [0] } + connect \DX_d2 \opcode_in [0] + connect \DX_d1 \opcode_in [20:16] + connect \DX_d0 \opcode_in [15:6] + connect \XFX_XO \opcode_in [10:1] + connect \XFX_SPR \opcode_in [20:11] + connect \XFX_RT \opcode_in [25:21] + connect \XFX_RS \opcode_in [25:21] + connect \XFX_FXM \opcode_in [19:12] + connect \XFX_DUIS \opcode_in [20:11] + connect \XFX_DUI \opcode_in [25:21] + connect \XFX_BHRBE \opcode_in [20:11] + connect \EVS_BFA \opcode_in [2:0] + connect \Z22_XO \opcode_in [9:1] + connect \Z22_SH \opcode_in [15:10] + connect \Z22_Rc \opcode_in [0] + connect \Z22_FRTp \opcode_in [25:21] + connect \Z22_FRT \opcode_in [25:21] + connect \Z22_FRAp \opcode_in [20:16] + connect \Z22_FRA \opcode_in [20:16] + connect \Z22_DGM \opcode_in [15:10] + connect \Z22_DCM \opcode_in [15:10] + connect \Z22_BF \opcode_in [25:23] + connect \XX2_XO_1 \opcode_in [10:2] + connect \XX2_XO { \opcode_in [10:7] \opcode_in [5:3] } + connect \XX2_UIM_1 \opcode_in [17:16] + connect \XX2_UIM \opcode_in [19:16] + connect \XX2_TX_T { \opcode_in [0] \opcode_in [25:21] } + connect \XX2_T \opcode_in [25:21] + connect \XX2_TX \opcode_in [0] + connect \XX2_RT \opcode_in [25:21] + connect \XX2_EO \opcode_in [20:16] + connect \XX2_DCMX \opcode_in [22:16] + connect \XX2_dc_dm_dx { \opcode_in [6] \opcode_in [2] \opcode_in [20:16] } + connect \XX2_dx \opcode_in [20:16] + connect \XX2_dm \opcode_in [2] + connect \XX2_dc \opcode_in [6] + connect \XX2_BX_B { \opcode_in [1] \opcode_in [15:11] } + connect \XX2_B \opcode_in [15:11] + connect \XX2_BX \opcode_in [1] + connect \XX2_BF \opcode_in [25:23] + connect \D_UI \opcode_in [15:0] + connect \D_TO \opcode_in [25:21] + connect \D_SI \opcode_in [15:0] + connect \D_RT \opcode_in [25:21] + connect \D_RS \opcode_in [25:21] + connect \D_RA \opcode_in [20:16] + connect \D_L \opcode_in [21] + connect \D_FRT \opcode_in [25:21] + connect \D_FRS \opcode_in [25:21] + connect \D_D \opcode_in [15:0] + connect \D_BF \opcode_in [25:23] + connect \A_XO \opcode_in [5:1] + connect \A_RT \opcode_in [25:21] + connect \A_Rc \opcode_in [0] + connect \A_RB \opcode_in [15:11] + connect \A_RA \opcode_in [20:16] + connect \A_FRT \opcode_in [25:21] + connect \A_FRC \opcode_in [10:6] + connect \A_FRB \opcode_in [15:11] + connect \A_FRA \opcode_in [20:16] + connect \A_BC \opcode_in [10:6] + connect \XL_XO \opcode_in [10:1] + connect \XL_S \opcode_in [11] + connect \XL_OC \opcode_in [25:11] + connect \XL_LK \opcode_in [0] + connect \XL_BT \opcode_in [25:21] + connect \XL_BO_1 \opcode_in [25:21] + connect \XL_BO \opcode_in [25:21] + connect \XL_BI \opcode_in [20:16] + connect \XL_BH \opcode_in [12:11] + connect \XL_BFA \opcode_in [20:18] + connect \XL_BF \opcode_in [25:23] + connect \XL_BB \opcode_in [15:11] + connect \XL_BA \opcode_in [20:16] + connect \XX4_XO \opcode_in [5:4] + connect \XX4_TX_T { \opcode_in [0] \opcode_in [25:21] } + connect \XX4_T \opcode_in [25:21] + connect \XX4_TX \opcode_in [0] + connect \XX4_CX_C { \opcode_in [3] \opcode_in [10:6] } + connect \XX4_C \opcode_in [10:6] + connect \XX4_CX \opcode_in [3] + connect \XX4_BX_B { \opcode_in [1] \opcode_in [15:11] } + connect \XX4_B \opcode_in [15:11] + connect \XX4_BX \opcode_in [1] + connect \XX4_AX_A { \opcode_in [2] \opcode_in [20:16] } + connect \XX4_A \opcode_in [20:16] + connect \XX4_AX \opcode_in [2] + connect \XX3_XO_2 \opcode_in [9:1] + connect \XX3_XO_1 \opcode_in [10:3] + connect \XX3_XO \opcode_in [10:7] + connect \XX3_TX_T { \opcode_in [0] \opcode_in [25:21] } + connect \XX3_T \opcode_in [25:21] + connect \XX3_TX \opcode_in [0] + connect \XX3_SHW \opcode_in [9:8] + connect \XX3_Rc \opcode_in [10] + connect \XX3_DM \opcode_in [9:8] + connect \XX3_BX_B { \opcode_in [1] \opcode_in [15:11] } + connect \XX3_B \opcode_in [15:11] + connect \XX3_BX \opcode_in [1] + connect \XX3_BF \opcode_in [25:23] + connect \XX3_AX_A { \opcode_in [2] \opcode_in [20:16] } + connect \XX3_A \opcode_in [20:16] + connect \XX3_AX \opcode_in [2] + connect \I_LK \opcode_in [0] + connect \I_LI \opcode_in [25:2] + connect \I_AA \opcode_in [1] + connect \B_LK \opcode_in [0] + connect \B_BO \opcode_in [25:21] + connect \B_BI \opcode_in [20:16] + connect \B_BD \opcode_in [15:2] + connect \B_AA \opcode_in [1] + connect \X_XO_1 \opcode_in [8:1] + connect \X_XO \opcode_in [10:1] + connect \X_WC \opcode_in [22:21] + connect \X_W \opcode_in [16] + connect \X_VRT \opcode_in [25:21] + connect \X_VRS \opcode_in [25:21] + connect \X_UIM \opcode_in [20:16] + connect \X_U \opcode_in [15:12] + connect \X_TX_T { \opcode_in [0] \opcode_in [25:21] } + connect \X_TX \opcode_in [0] + connect \X_TO \opcode_in [25:21] + connect \X_TH \opcode_in [25:21] + connect \X_TBR \opcode_in [20:11] + connect \X_T \opcode_in [25:21] + connect \X_SX_S { \opcode_in [0] \opcode_in [25:21] } + connect \X_SX \opcode_in [0] + connect \X_SR \opcode_in [19:16] + connect \X_SP \opcode_in [20:19] + connect \X_SI \opcode_in [15:11] + connect \X_SH \opcode_in [15:11] + connect \X_S \opcode_in [25:21] + connect \X_RTp \opcode_in [25:21] + connect \X_RT \opcode_in [25:21] + connect \X_RSp \opcode_in [25:21] + connect \X_RS \opcode_in [25:21] + connect \X_RO \opcode_in [0] + connect \X_RM \opcode_in [12:11] + connect \X_RIC \opcode_in [19:18] + connect \X_Rc \opcode_in [0] + connect \X_RB \opcode_in [15:11] + connect \X_RA \opcode_in [20:16] + connect \X_R_1 \opcode_in [16] + connect \X_R \opcode_in [21] + connect \X_PRS \opcode_in [17] + connect \X_NB \opcode_in [15:11] + connect \X_MO \opcode_in [25:21] + connect \X_L3 \opcode_in [17:16] + connect \X_L1 \opcode_in [16] + connect \X_L \opcode_in [21] + connect \X_L2 \opcode_in [22:21] + connect \X_IMM8 \opcode_in [18:11] + connect \X_IH \opcode_in [23:21] + connect \X_FRTp \opcode_in [25:21] + connect \X_FRT \opcode_in [25:21] + connect \X_FRSp \opcode_in [25:21] + connect \X_FRS \opcode_in [25:21] + connect \X_FRBp \opcode_in [15:11] + connect \X_FRB \opcode_in [15:11] + connect \X_FRAp \opcode_in [20:16] + connect \X_FRA \opcode_in [20:16] + connect \X_FC \opcode_in [15:11] + connect \X_EX \opcode_in [0] + connect \X_EO_1 \opcode_in [20:16] + connect \X_EO \opcode_in [20:19] + connect \X_E_1 \opcode_in [19:16] + connect \X_E \opcode_in [15] + connect \X_DRM \opcode_in [13:11] + connect \X_DCMX \opcode_in [22:16] + connect \X_CT \opcode_in [24:21] + connect \X_BO \opcode_in [25:21] + connect \X_BFA \opcode_in [20:18] + connect \X_BF \opcode_in [25:23] + connect \X_A \opcode_in [25] + connect \SPR_SPR \opcode_in [20:11] + connect \SPR_MB \opcode_in [10:6] + connect \SPR_ME \opcode_in [5:1] + connect \SPR_SH \opcode_in [15:11] + connect \SPR_BC \opcode_in [10:6] + connect \SPR_TO \opcode_in [25:21] + connect \SPR_DS \opcode_in [15:2] + connect \SPR_D \opcode_in [15:0] + connect \SPR_BH \opcode_in [12:11] + connect \SPR_BI \opcode_in [20:16] + connect \SPR_BO \opcode_in [25:21] + connect \SPR_FXM \opcode_in [19:12] + connect \SPR_BT \opcode_in [25:21] + connect \SPR_BA \opcode_in [20:16] + connect \SPR_BB \opcode_in [15:11] + connect \SPR_CR \opcode_in [10:1] + connect \SPR_BF \opcode_in [25:23] + connect \SPR_BD \opcode_in [15:2] + connect \SPR_OE \opcode_in [10] + connect \SPR_Rc \opcode_in [0] + connect \SPR_AA \opcode_in [1] + connect \SPR_LK \opcode_in [0] + connect \SPR_LI \opcode_in [25:2] + connect \SPR_ME32 \opcode_in [5:1] + connect \SPR_MB32 \opcode_in [10:6] + connect \SPR_sh { \opcode_in [1] \opcode_in [15:11] } + connect \SPR_SH32 \opcode_in [15:11] + connect \SPR_L \opcode_in [21] + connect \SPR_UI \opcode_in [15:0] + connect \SPR_SI \opcode_in [15:0] + connect \SPR_RB \opcode_in [15:11] + connect \SPR_RA \opcode_in [20:16] + connect \SPR_RT \opcode_in [25:21] + connect \SPR_RS \opcode_in [25:21] + connect \opcode_in \$1 + connect \SPR_dec31_opcode_in \opcode_in + connect \opcode_switch \opcode_in [31:26] +end +attribute \src "issuer_ls180.v:57998.1-59493.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.dec_DIV.dec" +attribute \generator "nMigen" +module \dec$168 + attribute \src "issuer_ls180.v:59124.3-59133.6" + wire width 3 $0\DIV_cr_in[2:0] + attribute \src "issuer_ls180.v:59134.3-59143.6" + wire width 3 $0\DIV_cr_out[2:0] + attribute \src "issuer_ls180.v:59024.3-59033.6" + wire width 2 $0\DIV_cry_in[1:0] + attribute \src "issuer_ls180.v:59054.3-59063.6" + wire $0\DIV_cry_out[0:0] + attribute \src "issuer_ls180.v:59084.3-59093.6" + wire width 12 $0\DIV_function_unit[11:0] + attribute \src "issuer_ls180.v:59104.3-59113.6" + wire width 3 $0\DIV_in1_sel[2:0] + attribute \src "issuer_ls180.v:59114.3-59123.6" + wire width 4 $0\DIV_in2_sel[3:0] + attribute \src "issuer_ls180.v:59094.3-59103.6" + wire width 7 $0\DIV_internal_op[6:0] + attribute \src "issuer_ls180.v:59034.3-59043.6" + wire $0\DIV_inv_a[0:0] + attribute \src "issuer_ls180.v:59044.3-59053.6" + wire $0\DIV_inv_out[0:0] + attribute \src "issuer_ls180.v:59064.3-59073.6" + wire $0\DIV_is_32b[0:0] + attribute \src "issuer_ls180.v:59144.3-59153.6" + wire width 4 $0\DIV_ldst_len[3:0] + attribute \src "issuer_ls180.v:59154.3-59163.6" + wire width 2 $0\DIV_rc_sel[1:0] + attribute \src "issuer_ls180.v:59074.3-59083.6" + wire $0\DIV_sgn[0:0] + attribute \src "issuer_ls180.v:57999.7-57999.20" + wire $0\initial[0:0] + attribute \src "issuer_ls180.v:59124.3-59133.6" + wire width 3 $1\DIV_cr_in[2:0] + attribute \src "issuer_ls180.v:59134.3-59143.6" + wire width 3 $1\DIV_cr_out[2:0] + attribute \src "issuer_ls180.v:59024.3-59033.6" + wire width 2 $1\DIV_cry_in[1:0] + attribute \src "issuer_ls180.v:59054.3-59063.6" + wire $1\DIV_cry_out[0:0] + attribute \src "issuer_ls180.v:59084.3-59093.6" + wire width 12 $1\DIV_function_unit[11:0] + attribute \src "issuer_ls180.v:59104.3-59113.6" + wire width 3 $1\DIV_in1_sel[2:0] + attribute \src "issuer_ls180.v:59114.3-59123.6" + wire width 4 $1\DIV_in2_sel[3:0] + attribute \src "issuer_ls180.v:59094.3-59103.6" + wire width 7 $1\DIV_internal_op[6:0] + attribute \src "issuer_ls180.v:59034.3-59043.6" + wire $1\DIV_inv_a[0:0] + attribute \src "issuer_ls180.v:59044.3-59053.6" + wire $1\DIV_inv_out[0:0] + attribute \src "issuer_ls180.v:59064.3-59073.6" + wire $1\DIV_is_32b[0:0] + attribute \src "issuer_ls180.v:59144.3-59153.6" + wire width 4 $1\DIV_ldst_len[3:0] + attribute \src "issuer_ls180.v:59154.3-59163.6" + wire width 2 $1\DIV_rc_sel[1:0] + attribute \src "issuer_ls180.v:59074.3-59083.6" + wire $1\DIV_sgn[0:0] + attribute \src "issuer_ls180.v:59006.17-59006.211" + wire width 32 $ternary$issuer_ls180.v:59006$3419_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:478" + wire width 32 \$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \A_BC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \A_FRA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \A_FRB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \A_FRC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \A_FRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \A_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \A_RB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \A_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \A_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \A_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \B_AA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 14 \B_BD + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \B_BI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \B_BO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \B_LK + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire \DIV_AA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 output 27 \DIV_BA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 output 26 \DIV_BB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 output 32 \DIV_BC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 14 output 25 \DIV_BD + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 3 \DIV_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 2 \DIV_BH + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 output 30 \DIV_BI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 \DIV_BO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 output 28 \DIV_BT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 10 \DIV_CR + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 16 \DIV_D + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 14 output 31 \DIV_DS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 8 output 29 \DIV_FXM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire \DIV_L + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 24 output 22 \DIV_LI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire \DIV_LK + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 \DIV_MB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 \DIV_MB32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 \DIV_ME + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 \DIV_ME32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire output 24 \DIV_OE + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 output 17 \DIV_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 \DIV_RB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 \DIV_RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 \DIV_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire output 23 \DIV_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 \DIV_SH + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 output 20 \DIV_SH32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 16 output 18 \DIV_SI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 10 \DIV_SPR + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 \DIV_TO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 16 output 19 \DIV_UI + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 4 \DIV_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 5 \DIV_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 13 \DIV_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 14 \DIV_cry_out + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 \DIV_dec31_DIV_dec31_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 \DIV_dec31_DIV_dec31_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \DIV_dec31_DIV_dec31_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \DIV_dec31_DIV_dec31_cry_out + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 12 \DIV_dec31_DIV_dec31_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 \DIV_dec31_DIV_dec31_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 \DIV_dec31_DIV_dec31_in2_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 7 \DIV_dec31_DIV_dec31_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \DIV_dec31_DIV_dec31_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \DIV_dec31_DIV_dec31_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \DIV_dec31_DIV_dec31_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 \DIV_dec31_DIV_dec31_ldst_len + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \DIV_dec31_DIV_dec31_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \DIV_dec31_DIV_dec31_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + wire width 32 \DIV_dec31_opcode_in + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 12 output 7 \DIV_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 8 \DIV_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 output 9 \DIV_in2_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 7 output 6 \DIV_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 11 \DIV_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 12 \DIV_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 15 \DIV_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 output 10 \DIV_ldst_len + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 3 \DIV_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 16 \DIV_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 6 output 21 \DIV_sh + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \DQE_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \DQE_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 2 \DQE_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 12 \DQ_DQ + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 4 \DQ_PT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \DQ_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \DQ_RTp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \DQ_S + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \DQ_SX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \DQ_SX_S + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \DQ_T + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \DQ_TX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \DQ_TX_T + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 3 \DQ_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 14 \DS_DS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \DS_FRSp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \DS_FRTp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \DS_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \DS_RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \DS_RSp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \DS_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \DS_VRS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \DS_VRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 2 \DS_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \DX_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \DX_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 10 \DX_d0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 16 \DX_d0_d1_d2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \DX_d1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \DX_d2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 3 \D_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 16 \D_D + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \D_FRS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \D_FRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \D_L + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \D_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \D_RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \D_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 16 \D_SI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \D_TO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 16 \D_UI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 3 \EVS_BFA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \I_AA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 24 \I_LI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \I_LK + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \MDS_IB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \MDS_IS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \MDS_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \MDS_RB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \MDS_RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \MDS_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 4 \MDS_XBI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 4 \MDS_XBI_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 4 \MDS_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \MDS_mb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \MDS_me + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \MD_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \MD_RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \MD_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 3 \MD_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \MD_mb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \MD_me + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \MD_sh + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \M_MB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \M_ME + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \M_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \M_RB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \M_RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \M_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \M_SH + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 7 \SC_LEV + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \SC_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 2 \SC_XO_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \TX_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \TX_UI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 4 \TX_XBI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \TX_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \VA_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \VA_RB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \VA_RC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \VA_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 4 \VA_SHB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \VA_VRA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \VA_VRB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \VA_VRC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \VA_VRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \VA_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \VC_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \VC_VRA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \VC_VRB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \VC_VRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 10 \VC_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \VX_EO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \VX_PS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \VX_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \VX_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \VX_SIM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \VX_UIM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 4 \VX_UIM_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 3 \VX_UIM_2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 2 \VX_UIM_3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \VX_VRA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \VX_VRB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \VX_VRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 10 \VX_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 11 \VX_XO_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 8 \XFL_FLM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XFL_FRB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \XFL_L + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \XFL_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \XFL_W + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 10 \XFL_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 10 \XFX_BHRBE + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XFX_DUI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 10 \XFX_DUIS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 8 \XFX_FXM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XFX_RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XFX_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 10 \XFX_SPR + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 10 \XFX_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XL_BA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XL_BB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 3 \XL_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 3 \XL_BFA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 2 \XL_BH + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XL_BI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XL_BO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XL_BO_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 output 35 \XL_BT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \XL_LK + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 15 \XL_OC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \XL_S + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 10 \XL_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \XO_OE + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XO_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XO_RB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XO_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \XO_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 9 \XO_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XS_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XS_RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \XS_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 9 \XS_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \XS_sh + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XX2_B + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 3 \XX2_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \XX2_BX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \XX2_BX_B + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 7 \XX2_DCMX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XX2_EO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XX2_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XX2_T + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \XX2_TX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \XX2_TX_T + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 4 \XX2_UIM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 2 \XX2_UIM_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 7 \XX2_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 9 \XX2_XO_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \XX2_dc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 7 \XX2_dc_dm_dx + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \XX2_dm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XX2_dx + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XX3_A + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \XX3_AX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \XX3_AX_A + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XX3_B + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 3 \XX3_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \XX3_BX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \XX3_BX_B + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 2 \XX3_DM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \XX3_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 2 \XX3_SHW + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XX3_T + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \XX3_TX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \XX3_TX_T + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 4 \XX3_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 8 \XX3_XO_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 9 \XX3_XO_2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XX4_A + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \XX4_AX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \XX4_AX_A + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XX4_B + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \XX4_BX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \XX4_BX_B + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XX4_C + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \XX4_CX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \XX4_CX_C + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XX4_T + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \XX4_TX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \XX4_TX_T + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 2 \XX4_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \X_A + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 3 output 33 \X_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 3 output 34 \X_BFA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_BO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 4 \X_CT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 7 \X_DCMX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 3 \X_DRM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \X_E + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 2 \X_EO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_EO_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \X_EX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 4 \X_E_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_FC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_FRA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_FRAp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_FRB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_FRBp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_FRS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_FRSp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_FRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_FRTp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 3 \X_IH + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 8 \X_IMM8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \X_L + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \X_L1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 2 \X_L2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 2 \X_L3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_MO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_NB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \X_PRS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \X_R + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_RB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 2 \X_RIC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 2 \X_RM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \X_RO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_RSp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_RTp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \X_R_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \X_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_S + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_SH + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_SI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 2 \X_SP + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 4 \X_SR + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \X_SX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \X_SX_S + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_T + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 10 \X_TBR + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_TH + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_TO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \X_TX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \X_TX_T + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 4 \X_U + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_UIM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_VRS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_VRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \X_W + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 2 \X_WC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 10 \X_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 8 \X_XO_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 3 \Z22_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \Z22_DCM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \Z22_DGM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \Z22_FRA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \Z22_FRAp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \Z22_FRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \Z22_FRTp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \Z22_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \Z22_SH + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 9 \Z22_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \Z23_FRA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \Z23_FRAp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \Z23_FRB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \Z23_FRBp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \Z23_FRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \Z23_FRTp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \Z23_R + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 2 \Z23_RMC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \Z23_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \Z23_TE + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 8 \Z23_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \all_OPCD + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \all_PO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + wire input 1 \bigendian + attribute \src "issuer_ls180.v:57999.7-57999.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + wire width 32 output 2 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:320" + wire width 6 \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:442" + wire width 32 input 36 \raw_opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:478" + cell $mux $ternary$issuer_ls180.v:59006$3419 + parameter \WIDTH 32 + connect \A \raw_opcode_in + connect \B { \raw_opcode_in [7:0] \raw_opcode_in [15:8] \raw_opcode_in [23:16] \raw_opcode_in [31:24] } + connect \S \bigendian + connect \Y $ternary$issuer_ls180.v:59006$3419_Y + end + attribute \module_not_derived 1 + attribute \src "issuer_ls180.v:59007.13-59023.4" + cell \DIV_dec31 \DIV_dec31 + connect \DIV_dec31_cr_in \DIV_dec31_DIV_dec31_cr_in + connect \DIV_dec31_cr_out \DIV_dec31_DIV_dec31_cr_out + connect \DIV_dec31_cry_in \DIV_dec31_DIV_dec31_cry_in + connect \DIV_dec31_cry_out \DIV_dec31_DIV_dec31_cry_out + connect \DIV_dec31_function_unit \DIV_dec31_DIV_dec31_function_unit + connect \DIV_dec31_in1_sel \DIV_dec31_DIV_dec31_in1_sel + connect \DIV_dec31_in2_sel \DIV_dec31_DIV_dec31_in2_sel + connect \DIV_dec31_internal_op \DIV_dec31_DIV_dec31_internal_op + connect \DIV_dec31_inv_a \DIV_dec31_DIV_dec31_inv_a + connect \DIV_dec31_inv_out \DIV_dec31_DIV_dec31_inv_out + connect \DIV_dec31_is_32b \DIV_dec31_DIV_dec31_is_32b + connect \DIV_dec31_ldst_len \DIV_dec31_DIV_dec31_ldst_len + connect \DIV_dec31_rc_sel \DIV_dec31_DIV_dec31_rc_sel + connect \DIV_dec31_sgn \DIV_dec31_DIV_dec31_sgn + connect \opcode_in \DIV_dec31_opcode_in + end + attribute \src "issuer_ls180.v:57999.7-57999.20" + process $proc$issuer_ls180.v:57999$3434 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "issuer_ls180.v:59024.3-59033.6" + process $proc$issuer_ls180.v:59024$3420 + assign { } { } + assign { } { } + assign $0\DIV_cry_in[1:0] $1\DIV_cry_in[1:0] + attribute \src "issuer_ls180.v:59025.5-59025.29" + switch \initial + attribute \src "issuer_ls180.v:59025.9-59025.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\DIV_cry_in[1:0] \DIV_dec31_DIV_dec31_cry_in + case + assign $1\DIV_cry_in[1:0] 2'00 + end + sync always + update \DIV_cry_in $0\DIV_cry_in[1:0] + end + attribute \src "issuer_ls180.v:59034.3-59043.6" + process $proc$issuer_ls180.v:59034$3421 + assign { } { } + assign { } { } + assign $0\DIV_inv_a[0:0] $1\DIV_inv_a[0:0] + attribute \src "issuer_ls180.v:59035.5-59035.29" + switch \initial + attribute \src "issuer_ls180.v:59035.9-59035.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\DIV_inv_a[0:0] \DIV_dec31_DIV_dec31_inv_a + case + assign $1\DIV_inv_a[0:0] 1'0 + end + sync always + update \DIV_inv_a $0\DIV_inv_a[0:0] + end + attribute \src "issuer_ls180.v:59044.3-59053.6" + process $proc$issuer_ls180.v:59044$3422 + assign { } { } + assign { } { } + assign $0\DIV_inv_out[0:0] $1\DIV_inv_out[0:0] + attribute \src "issuer_ls180.v:59045.5-59045.29" + switch \initial + attribute \src "issuer_ls180.v:59045.9-59045.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\DIV_inv_out[0:0] \DIV_dec31_DIV_dec31_inv_out + case + assign $1\DIV_inv_out[0:0] 1'0 + end + sync always + update \DIV_inv_out $0\DIV_inv_out[0:0] + end + attribute \src "issuer_ls180.v:59054.3-59063.6" + process $proc$issuer_ls180.v:59054$3423 + assign { } { } + assign { } { } + assign $0\DIV_cry_out[0:0] $1\DIV_cry_out[0:0] + attribute \src "issuer_ls180.v:59055.5-59055.29" + switch \initial + attribute \src "issuer_ls180.v:59055.9-59055.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\DIV_cry_out[0:0] \DIV_dec31_DIV_dec31_cry_out + case + assign $1\DIV_cry_out[0:0] 1'0 + end + sync always + update \DIV_cry_out $0\DIV_cry_out[0:0] + end + attribute \src "issuer_ls180.v:59064.3-59073.6" + process $proc$issuer_ls180.v:59064$3424 + assign { } { } + assign { } { } + assign $0\DIV_is_32b[0:0] $1\DIV_is_32b[0:0] + attribute \src "issuer_ls180.v:59065.5-59065.29" + switch \initial + attribute \src "issuer_ls180.v:59065.9-59065.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\DIV_is_32b[0:0] \DIV_dec31_DIV_dec31_is_32b + case + assign $1\DIV_is_32b[0:0] 1'0 + end + sync always + update \DIV_is_32b $0\DIV_is_32b[0:0] + end + attribute \src "issuer_ls180.v:59074.3-59083.6" + process $proc$issuer_ls180.v:59074$3425 + assign { } { } + assign { } { } + assign $0\DIV_sgn[0:0] $1\DIV_sgn[0:0] + attribute \src "issuer_ls180.v:59075.5-59075.29" + switch \initial + attribute \src "issuer_ls180.v:59075.9-59075.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\DIV_sgn[0:0] \DIV_dec31_DIV_dec31_sgn + case + assign $1\DIV_sgn[0:0] 1'0 + end + sync always + update \DIV_sgn $0\DIV_sgn[0:0] + end + attribute \src "issuer_ls180.v:59084.3-59093.6" + process $proc$issuer_ls180.v:59084$3426 + assign { } { } + assign { } { } + assign $0\DIV_function_unit[11:0] $1\DIV_function_unit[11:0] + attribute \src "issuer_ls180.v:59085.5-59085.29" + switch \initial + attribute \src "issuer_ls180.v:59085.9-59085.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\DIV_function_unit[11:0] \DIV_dec31_DIV_dec31_function_unit + case + assign $1\DIV_function_unit[11:0] 12'000000000000 + end + sync always + update \DIV_function_unit $0\DIV_function_unit[11:0] + end + attribute \src "issuer_ls180.v:59094.3-59103.6" + process $proc$issuer_ls180.v:59094$3427 + assign { } { } + assign { } { } + assign $0\DIV_internal_op[6:0] $1\DIV_internal_op[6:0] + attribute \src "issuer_ls180.v:59095.5-59095.29" + switch \initial + attribute \src "issuer_ls180.v:59095.9-59095.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\DIV_internal_op[6:0] \DIV_dec31_DIV_dec31_internal_op + case + assign $1\DIV_internal_op[6:0] 7'0000000 + end + sync always + update \DIV_internal_op $0\DIV_internal_op[6:0] + end + attribute \src "issuer_ls180.v:59104.3-59113.6" + process $proc$issuer_ls180.v:59104$3428 + assign { } { } + assign { } { } + assign $0\DIV_in1_sel[2:0] $1\DIV_in1_sel[2:0] + attribute \src "issuer_ls180.v:59105.5-59105.29" + switch \initial + attribute \src "issuer_ls180.v:59105.9-59105.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\DIV_in1_sel[2:0] \DIV_dec31_DIV_dec31_in1_sel + case + assign $1\DIV_in1_sel[2:0] 3'000 + end + sync always + update \DIV_in1_sel $0\DIV_in1_sel[2:0] + end + attribute \src "issuer_ls180.v:59114.3-59123.6" + process $proc$issuer_ls180.v:59114$3429 + assign { } { } + assign { } { } + assign $0\DIV_in2_sel[3:0] $1\DIV_in2_sel[3:0] + attribute \src "issuer_ls180.v:59115.5-59115.29" + switch \initial + attribute \src "issuer_ls180.v:59115.9-59115.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\DIV_in2_sel[3:0] \DIV_dec31_DIV_dec31_in2_sel + case + assign $1\DIV_in2_sel[3:0] 4'0000 + end + sync always + update \DIV_in2_sel $0\DIV_in2_sel[3:0] + end + attribute \src "issuer_ls180.v:59124.3-59133.6" + process $proc$issuer_ls180.v:59124$3430 + assign { } { } + assign { } { } + assign $0\DIV_cr_in[2:0] $1\DIV_cr_in[2:0] + attribute \src "issuer_ls180.v:59125.5-59125.29" + switch \initial + attribute \src "issuer_ls180.v:59125.9-59125.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\DIV_cr_in[2:0] \DIV_dec31_DIV_dec31_cr_in + case + assign $1\DIV_cr_in[2:0] 3'000 + end + sync always + update \DIV_cr_in $0\DIV_cr_in[2:0] + end + attribute \src "issuer_ls180.v:59134.3-59143.6" + process $proc$issuer_ls180.v:59134$3431 + assign { } { } + assign { } { } + assign $0\DIV_cr_out[2:0] $1\DIV_cr_out[2:0] + attribute \src "issuer_ls180.v:59135.5-59135.29" + switch \initial + attribute \src "issuer_ls180.v:59135.9-59135.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\DIV_cr_out[2:0] \DIV_dec31_DIV_dec31_cr_out + case + assign $1\DIV_cr_out[2:0] 3'000 + end + sync always + update \DIV_cr_out $0\DIV_cr_out[2:0] + end + attribute \src "issuer_ls180.v:59144.3-59153.6" + process $proc$issuer_ls180.v:59144$3432 + assign { } { } + assign { } { } + assign $0\DIV_ldst_len[3:0] $1\DIV_ldst_len[3:0] + attribute \src "issuer_ls180.v:59145.5-59145.29" + switch \initial + attribute \src "issuer_ls180.v:59145.9-59145.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\DIV_ldst_len[3:0] \DIV_dec31_DIV_dec31_ldst_len + case + assign $1\DIV_ldst_len[3:0] 4'0000 + end + sync always + update \DIV_ldst_len $0\DIV_ldst_len[3:0] + end + attribute \src "issuer_ls180.v:59154.3-59163.6" + process $proc$issuer_ls180.v:59154$3433 + assign { } { } + assign { } { } + assign $0\DIV_rc_sel[1:0] $1\DIV_rc_sel[1:0] + attribute \src "issuer_ls180.v:59155.5-59155.29" + switch \initial + attribute \src "issuer_ls180.v:59155.9-59155.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\DIV_rc_sel[1:0] \DIV_dec31_DIV_dec31_rc_sel + case + assign $1\DIV_rc_sel[1:0] 2'00 + end + sync always + update \DIV_rc_sel $0\DIV_rc_sel[1:0] + end + connect \$1 $ternary$issuer_ls180.v:59006$3419_Y + connect \VC_XO \opcode_in [9:0] + connect \VC_VRT \opcode_in [25:21] + connect \VC_VRB \opcode_in [15:11] + connect \VC_VRA \opcode_in [20:16] + connect \VC_Rc \opcode_in [10] + connect \XS_XO \opcode_in [10:2] + connect \XS_sh { \opcode_in [1] \opcode_in [15:11] } + connect \XS_RS \opcode_in [25:21] + connect \XS_Rc \opcode_in [0] + connect \XS_RA \opcode_in [20:16] + connect \VA_XO \opcode_in [5:0] + connect \VA_VRT \opcode_in [25:21] + connect \VA_VRC \opcode_in [10:6] + connect \VA_VRB \opcode_in [15:11] + connect \VA_VRA \opcode_in [20:16] + connect \VA_SHB \opcode_in [9:6] + connect \VA_RT \opcode_in [25:21] + connect \VA_RC \opcode_in [10:6] + connect \VA_RB \opcode_in [15:11] + connect \VA_RA \opcode_in [20:16] + connect \TX_XO \opcode_in [6:1] + connect \TX_XBI \opcode_in [10:7] + connect \TX_UI \opcode_in [15:11] + connect \TX_RA \opcode_in [20:16] + connect \DQE_XO \opcode_in [1:0] + connect \DQE_RT \opcode_in [25:21] + connect \DQE_RA \opcode_in [20:16] + connect \XO_XO \opcode_in [9:1] + connect \XO_RT \opcode_in [25:21] + connect \XO_Rc \opcode_in [0] + connect \XO_RB \opcode_in [15:11] + connect \XO_RA \opcode_in [20:16] + connect \XO_OE \opcode_in [10] + connect \all_PO \opcode_in [31:26] + connect \all_OPCD \opcode_in [31:26] + connect \MD_XO \opcode_in [4:2] + connect \MD_sh { \opcode_in [1] \opcode_in [15:11] } + connect \MD_RS \opcode_in [25:21] + connect \MD_Rc \opcode_in [0] + connect \MD_RA \opcode_in [20:16] + connect \MD_me \opcode_in [10:5] + connect \MD_mb \opcode_in [10:5] + connect \M_SH \opcode_in [15:11] + connect \M_RS \opcode_in [25:21] + connect \M_Rc \opcode_in [0] + connect \M_RB \opcode_in [15:11] + connect \M_RA \opcode_in [20:16] + connect \M_ME \opcode_in [5:1] + connect \M_MB \opcode_in [10:6] + connect \SC_XO_1 \opcode_in [1:0] + connect \SC_XO \opcode_in [1] + connect \SC_LEV \opcode_in [11:5] + connect \MDS_XO \opcode_in [4:1] + connect \MDS_XBI_1 \opcode_in [10:7] + connect \MDS_XBI \opcode_in [10:7] + connect \MDS_RS \opcode_in [25:21] + connect \MDS_Rc \opcode_in [0] + connect \MDS_RB \opcode_in [15:11] + connect \MDS_RA \opcode_in [20:16] + connect \MDS_me \opcode_in [10:5] + connect \MDS_mb \opcode_in [10:5] + connect \MDS_IS \opcode_in [25:21] + connect \MDS_IB \opcode_in [15:11] + connect \Z23_XO \opcode_in [8:1] + connect \Z23_TE \opcode_in [20:16] + connect \Z23_RMC \opcode_in [10:9] + connect \Z23_Rc \opcode_in [0] + connect \Z23_R \opcode_in [16] + connect \Z23_FRTp \opcode_in [25:21] + connect \Z23_FRT \opcode_in [25:21] + connect \Z23_FRBp \opcode_in [15:11] + connect \Z23_FRB \opcode_in [15:11] + connect \Z23_FRAp \opcode_in [20:16] + connect \Z23_FRA \opcode_in [20:16] + connect \XFL_XO \opcode_in [10:1] + connect \XFL_W \opcode_in [16] + connect \XFL_Rc \opcode_in [0] + connect \XFL_L \opcode_in [25] + connect \XFL_FRB \opcode_in [15:11] + connect \XFL_FLM \opcode_in [24:17] + connect \VX_XO_1 \opcode_in [10:0] + connect \VX_XO { \opcode_in [10] \opcode_in [8:0] } + connect \VX_VRT \opcode_in [25:21] + connect \VX_VRB \opcode_in [15:11] + connect \VX_VRA \opcode_in [20:16] + connect \VX_UIM_3 \opcode_in [17:16] + connect \VX_UIM_2 \opcode_in [18:16] + connect \VX_UIM_1 \opcode_in [19:16] + connect \VX_UIM \opcode_in [20:16] + connect \VX_SIM \opcode_in [20:16] + connect \VX_RT \opcode_in [25:21] + connect \VX_RA \opcode_in [20:16] + connect \VX_PS \opcode_in [9] + connect \VX_EO \opcode_in [20:16] + connect \DS_XO \opcode_in [1:0] + connect \DS_VRT \opcode_in [25:21] + connect \DS_VRS \opcode_in [25:21] + connect \DS_RT \opcode_in [25:21] + connect \DS_RSp \opcode_in [25:21] + connect \DS_RS \opcode_in [25:21] + connect \DS_RA \opcode_in [20:16] + connect \DS_FRTp \opcode_in [25:21] + connect \DS_FRSp \opcode_in [25:21] + connect \DS_DS \opcode_in [15:2] + connect \DQ_XO \opcode_in [2:0] + connect \DQ_TX_T { \opcode_in [3] \opcode_in [25:21] } + connect \DQ_T \opcode_in [25:21] + connect \DQ_TX \opcode_in [3] + connect \DQ_SX_S { \opcode_in [3] \opcode_in [25:21] } + connect \DQ_S \opcode_in [25:21] + connect \DQ_SX \opcode_in [3] + connect \DQ_RTp \opcode_in [25:21] + connect \DQ_RA \opcode_in [20:16] + connect \DQ_PT \opcode_in [3:0] + connect \DQ_DQ \opcode_in [15:4] + connect \DX_XO \opcode_in [5:1] + connect \DX_RT \opcode_in [25:21] + connect \DX_d0_d1_d2 { \opcode_in [15:6] \opcode_in [20:16] \opcode_in [0] } + connect \DX_d2 \opcode_in [0] + connect \DX_d1 \opcode_in [20:16] + connect \DX_d0 \opcode_in [15:6] + connect \XFX_XO \opcode_in [10:1] + connect \XFX_SPR \opcode_in [20:11] + connect \XFX_RT \opcode_in [25:21] + connect \XFX_RS \opcode_in [25:21] + connect \XFX_FXM \opcode_in [19:12] + connect \XFX_DUIS \opcode_in [20:11] + connect \XFX_DUI \opcode_in [25:21] + connect \XFX_BHRBE \opcode_in [20:11] + connect \EVS_BFA \opcode_in [2:0] + connect \Z22_XO \opcode_in [9:1] + connect \Z22_SH \opcode_in [15:10] + connect \Z22_Rc \opcode_in [0] + connect \Z22_FRTp \opcode_in [25:21] + connect \Z22_FRT \opcode_in [25:21] + connect \Z22_FRAp \opcode_in [20:16] + connect \Z22_FRA \opcode_in [20:16] + connect \Z22_DGM \opcode_in [15:10] + connect \Z22_DCM \opcode_in [15:10] + connect \Z22_BF \opcode_in [25:23] + connect \XX2_XO_1 \opcode_in [10:2] + connect \XX2_XO { \opcode_in [10:7] \opcode_in [5:3] } + connect \XX2_UIM_1 \opcode_in [17:16] + connect \XX2_UIM \opcode_in [19:16] + connect \XX2_TX_T { \opcode_in [0] \opcode_in [25:21] } + connect \XX2_T \opcode_in [25:21] + connect \XX2_TX \opcode_in [0] + connect \XX2_RT \opcode_in [25:21] + connect \XX2_EO \opcode_in [20:16] + connect \XX2_DCMX \opcode_in [22:16] + connect \XX2_dc_dm_dx { \opcode_in [6] \opcode_in [2] \opcode_in [20:16] } + connect \XX2_dx \opcode_in [20:16] + connect \XX2_dm \opcode_in [2] + connect \XX2_dc \opcode_in [6] + connect \XX2_BX_B { \opcode_in [1] \opcode_in [15:11] } + connect \XX2_B \opcode_in [15:11] + connect \XX2_BX \opcode_in [1] + connect \XX2_BF \opcode_in [25:23] + connect \D_UI \opcode_in [15:0] + connect \D_TO \opcode_in [25:21] + connect \D_SI \opcode_in [15:0] + connect \D_RT \opcode_in [25:21] + connect \D_RS \opcode_in [25:21] + connect \D_RA \opcode_in [20:16] + connect \D_L \opcode_in [21] + connect \D_FRT \opcode_in [25:21] + connect \D_FRS \opcode_in [25:21] + connect \D_D \opcode_in [15:0] + connect \D_BF \opcode_in [25:23] + connect \A_XO \opcode_in [5:1] + connect \A_RT \opcode_in [25:21] + connect \A_Rc \opcode_in [0] + connect \A_RB \opcode_in [15:11] + connect \A_RA \opcode_in [20:16] + connect \A_FRT \opcode_in [25:21] + connect \A_FRC \opcode_in [10:6] + connect \A_FRB \opcode_in [15:11] + connect \A_FRA \opcode_in [20:16] + connect \A_BC \opcode_in [10:6] + connect \XL_XO \opcode_in [10:1] + connect \XL_S \opcode_in [11] + connect \XL_OC \opcode_in [25:11] + connect \XL_LK \opcode_in [0] + connect \XL_BT \opcode_in [25:21] + connect \XL_BO_1 \opcode_in [25:21] + connect \XL_BO \opcode_in [25:21] + connect \XL_BI \opcode_in [20:16] + connect \XL_BH \opcode_in [12:11] + connect \XL_BFA \opcode_in [20:18] + connect \XL_BF \opcode_in [25:23] + connect \XL_BB \opcode_in [15:11] + connect \XL_BA \opcode_in [20:16] + connect \XX4_XO \opcode_in [5:4] + connect \XX4_TX_T { \opcode_in [0] \opcode_in [25:21] } + connect \XX4_T \opcode_in [25:21] + connect \XX4_TX \opcode_in [0] + connect \XX4_CX_C { \opcode_in [3] \opcode_in [10:6] } + connect \XX4_C \opcode_in [10:6] + connect \XX4_CX \opcode_in [3] + connect \XX4_BX_B { \opcode_in [1] \opcode_in [15:11] } + connect \XX4_B \opcode_in [15:11] + connect \XX4_BX \opcode_in [1] + connect \XX4_AX_A { \opcode_in [2] \opcode_in [20:16] } + connect \XX4_A \opcode_in [20:16] + connect \XX4_AX \opcode_in [2] + connect \XX3_XO_2 \opcode_in [9:1] + connect \XX3_XO_1 \opcode_in [10:3] + connect \XX3_XO \opcode_in [10:7] + connect \XX3_TX_T { \opcode_in [0] \opcode_in [25:21] } + connect \XX3_T \opcode_in [25:21] + connect \XX3_TX \opcode_in [0] + connect \XX3_SHW \opcode_in [9:8] + connect \XX3_Rc \opcode_in [10] + connect \XX3_DM \opcode_in [9:8] + connect \XX3_BX_B { \opcode_in [1] \opcode_in [15:11] } + connect \XX3_B \opcode_in [15:11] + connect \XX3_BX \opcode_in [1] + connect \XX3_BF \opcode_in [25:23] + connect \XX3_AX_A { \opcode_in [2] \opcode_in [20:16] } + connect \XX3_A \opcode_in [20:16] + connect \XX3_AX \opcode_in [2] + connect \I_LK \opcode_in [0] + connect \I_LI \opcode_in [25:2] + connect \I_AA \opcode_in [1] + connect \B_LK \opcode_in [0] + connect \B_BO \opcode_in [25:21] + connect \B_BI \opcode_in [20:16] + connect \B_BD \opcode_in [15:2] + connect \B_AA \opcode_in [1] + connect \X_XO_1 \opcode_in [8:1] + connect \X_XO \opcode_in [10:1] + connect \X_WC \opcode_in [22:21] + connect \X_W \opcode_in [16] + connect \X_VRT \opcode_in [25:21] + connect \X_VRS \opcode_in [25:21] + connect \X_UIM \opcode_in [20:16] + connect \X_U \opcode_in [15:12] + connect \X_TX_T { \opcode_in [0] \opcode_in [25:21] } + connect \X_TX \opcode_in [0] + connect \X_TO \opcode_in [25:21] + connect \X_TH \opcode_in [25:21] + connect \X_TBR \opcode_in [20:11] + connect \X_T \opcode_in [25:21] + connect \X_SX_S { \opcode_in [0] \opcode_in [25:21] } + connect \X_SX \opcode_in [0] + connect \X_SR \opcode_in [19:16] + connect \X_SP \opcode_in [20:19] + connect \X_SI \opcode_in [15:11] + connect \X_SH \opcode_in [15:11] + connect \X_S \opcode_in [25:21] + connect \X_RTp \opcode_in [25:21] + connect \X_RT \opcode_in [25:21] + connect \X_RSp \opcode_in [25:21] + connect \X_RS \opcode_in [25:21] + connect \X_RO \opcode_in [0] + connect \X_RM \opcode_in [12:11] + connect \X_RIC \opcode_in [19:18] + connect \X_Rc \opcode_in [0] + connect \X_RB \opcode_in [15:11] + connect \X_RA \opcode_in [20:16] + connect \X_R_1 \opcode_in [16] + connect \X_R \opcode_in [21] + connect \X_PRS \opcode_in [17] + connect \X_NB \opcode_in [15:11] + connect \X_MO \opcode_in [25:21] + connect \X_L3 \opcode_in [17:16] + connect \X_L1 \opcode_in [16] + connect \X_L \opcode_in [21] + connect \X_L2 \opcode_in [22:21] + connect \X_IMM8 \opcode_in [18:11] + connect \X_IH \opcode_in [23:21] + connect \X_FRTp \opcode_in [25:21] + connect \X_FRT \opcode_in [25:21] + connect \X_FRSp \opcode_in [25:21] + connect \X_FRS \opcode_in [25:21] + connect \X_FRBp \opcode_in [15:11] + connect \X_FRB \opcode_in [15:11] + connect \X_FRAp \opcode_in [20:16] + connect \X_FRA \opcode_in [20:16] + connect \X_FC \opcode_in [15:11] + connect \X_EX \opcode_in [0] + connect \X_EO_1 \opcode_in [20:16] + connect \X_EO \opcode_in [20:19] + connect \X_E_1 \opcode_in [19:16] + connect \X_E \opcode_in [15] + connect \X_DRM \opcode_in [13:11] + connect \X_DCMX \opcode_in [22:16] + connect \X_CT \opcode_in [24:21] + connect \X_BO \opcode_in [25:21] + connect \X_BFA \opcode_in [20:18] + connect \X_BF \opcode_in [25:23] + connect \X_A \opcode_in [25] + connect \DIV_SPR \opcode_in [20:11] + connect \DIV_MB \opcode_in [10:6] + connect \DIV_ME \opcode_in [5:1] + connect \DIV_SH \opcode_in [15:11] + connect \DIV_BC \opcode_in [10:6] + connect \DIV_TO \opcode_in [25:21] + connect \DIV_DS \opcode_in [15:2] + connect \DIV_D \opcode_in [15:0] + connect \DIV_BH \opcode_in [12:11] + connect \DIV_BI \opcode_in [20:16] + connect \DIV_BO \opcode_in [25:21] + connect \DIV_FXM \opcode_in [19:12] + connect \DIV_BT \opcode_in [25:21] + connect \DIV_BA \opcode_in [20:16] + connect \DIV_BB \opcode_in [15:11] + connect \DIV_CR \opcode_in [10:1] + connect \DIV_BF \opcode_in [25:23] + connect \DIV_BD \opcode_in [15:2] + connect \DIV_OE \opcode_in [10] + connect \DIV_Rc \opcode_in [0] + connect \DIV_AA \opcode_in [1] + connect \DIV_LK \opcode_in [0] + connect \DIV_LI \opcode_in [25:2] + connect \DIV_ME32 \opcode_in [5:1] + connect \DIV_MB32 \opcode_in [10:6] + connect \DIV_sh { \opcode_in [1] \opcode_in [15:11] } + connect \DIV_SH32 \opcode_in [15:11] + connect \DIV_L \opcode_in [21] + connect \DIV_UI \opcode_in [15:0] + connect \DIV_SI \opcode_in [15:0] + connect \DIV_RB \opcode_in [15:11] + connect \DIV_RA \opcode_in [20:16] + connect \DIV_RT \opcode_in [25:21] + connect \DIV_RS \opcode_in [25:21] + connect \opcode_in \$1 + connect \DIV_dec31_opcode_in \opcode_in + connect \opcode_switch \opcode_in [31:26] +end +attribute \src "issuer_ls180.v:59497.1-60888.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.dec_MUL.dec" +attribute \generator "nMigen" +module \dec$177 + attribute \src "issuer_ls180.v:60494.3-60506.6" + wire width 3 $0\MUL_cr_in[2:0] + attribute \src "issuer_ls180.v:60507.3-60519.6" + wire width 3 $0\MUL_cr_out[2:0] + attribute \src "issuer_ls180.v:60455.3-60467.6" + wire width 12 $0\MUL_function_unit[11:0] + attribute \src "issuer_ls180.v:60481.3-60493.6" + wire width 4 $0\MUL_in2_sel[3:0] + attribute \src "issuer_ls180.v:60468.3-60480.6" + wire width 7 $0\MUL_internal_op[6:0] + attribute \src "issuer_ls180.v:60533.3-60545.6" + wire $0\MUL_is_32b[0:0] + attribute \src "issuer_ls180.v:60520.3-60532.6" + wire width 2 $0\MUL_rc_sel[1:0] + attribute \src "issuer_ls180.v:60546.3-60558.6" + wire $0\MUL_sgn[0:0] + attribute \src "issuer_ls180.v:59498.7-59498.20" + wire $0\initial[0:0] + attribute \src "issuer_ls180.v:60494.3-60506.6" + wire width 3 $1\MUL_cr_in[2:0] + attribute \src "issuer_ls180.v:60507.3-60519.6" + wire width 3 $1\MUL_cr_out[2:0] + attribute \src "issuer_ls180.v:60455.3-60467.6" + wire width 12 $1\MUL_function_unit[11:0] + attribute \src "issuer_ls180.v:60481.3-60493.6" + wire width 4 $1\MUL_in2_sel[3:0] + attribute \src "issuer_ls180.v:60468.3-60480.6" + wire width 7 $1\MUL_internal_op[6:0] + attribute \src "issuer_ls180.v:60533.3-60545.6" + wire $1\MUL_is_32b[0:0] + attribute \src "issuer_ls180.v:60520.3-60532.6" + wire width 2 $1\MUL_rc_sel[1:0] + attribute \src "issuer_ls180.v:60546.3-60558.6" + wire $1\MUL_sgn[0:0] + attribute \src "issuer_ls180.v:60443.17-60443.211" + wire width 32 $ternary$issuer_ls180.v:60443$3435_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:478" + wire width 32 \$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \A_BC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \A_FRA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \A_FRB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \A_FRC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \A_FRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \A_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \A_RB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \A_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \A_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \A_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \B_AA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 14 \B_BD + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \B_BI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \B_BO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \B_LK + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \DQE_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \DQE_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 2 \DQE_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 12 \DQ_DQ + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 4 \DQ_PT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \DQ_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \DQ_RTp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \DQ_S + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \DQ_SX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \DQ_SX_S + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \DQ_T + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \DQ_TX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \DQ_TX_T + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 3 \DQ_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 14 \DS_DS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \DS_FRSp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \DS_FRTp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \DS_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \DS_RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \DS_RSp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \DS_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \DS_VRS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \DS_VRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 2 \DS_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \DX_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \DX_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 10 \DX_d0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 16 \DX_d0_d1_d2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \DX_d1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \DX_d2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 3 \D_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 16 \D_D + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \D_FRS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \D_FRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \D_L + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \D_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \D_RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \D_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 16 \D_SI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \D_TO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 16 \D_UI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 3 \EVS_BFA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \I_AA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 24 \I_LI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \I_LK + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \MDS_IB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \MDS_IS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \MDS_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \MDS_RB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \MDS_RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \MDS_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 4 \MDS_XBI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 4 \MDS_XBI_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 4 \MDS_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \MDS_mb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \MDS_me + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \MD_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \MD_RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \MD_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 3 \MD_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \MD_mb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \MD_me + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \MD_sh + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire \MUL_AA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 output 20 \MUL_BA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 output 19 \MUL_BB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 output 25 \MUL_BC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 14 output 18 \MUL_BD + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 3 \MUL_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 2 \MUL_BH + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 output 23 \MUL_BI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 \MUL_BO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 output 21 \MUL_BT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 10 \MUL_CR + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 16 \MUL_D + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 14 output 24 \MUL_DS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 8 output 22 \MUL_FXM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire \MUL_L + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 24 output 15 \MUL_LI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire \MUL_LK + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 \MUL_MB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 \MUL_MB32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 \MUL_ME + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 \MUL_ME32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire output 17 \MUL_OE + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 \MUL_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 \MUL_RB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 \MUL_RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 \MUL_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire output 16 \MUL_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 \MUL_SH + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 output 13 \MUL_SH32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 16 output 11 \MUL_SI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 10 \MUL_SPR + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 \MUL_TO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 16 output 12 \MUL_UI + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 4 \MUL_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 5 \MUL_cr_out + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 \MUL_dec31_MUL_dec31_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 \MUL_dec31_MUL_dec31_cr_out + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 12 \MUL_dec31_MUL_dec31_function_unit + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 \MUL_dec31_MUL_dec31_in2_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 7 \MUL_dec31_MUL_dec31_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \MUL_dec31_MUL_dec31_is_32b + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \MUL_dec31_MUL_dec31_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \MUL_dec31_MUL_dec31_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + wire width 32 \MUL_dec31_opcode_in + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 12 output 7 \MUL_function_unit + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 output 8 \MUL_in2_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 7 output 6 \MUL_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 9 \MUL_is_32b + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 3 \MUL_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 10 \MUL_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 6 output 14 \MUL_sh + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \M_MB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \M_ME + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \M_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \M_RB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \M_RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \M_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \M_SH + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 7 \SC_LEV + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \SC_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 2 \SC_XO_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \TX_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \TX_UI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 4 \TX_XBI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \TX_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \VA_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \VA_RB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \VA_RC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \VA_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 4 \VA_SHB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \VA_VRA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \VA_VRB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \VA_VRC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \VA_VRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \VA_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \VC_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \VC_VRA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \VC_VRB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \VC_VRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 10 \VC_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \VX_EO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \VX_PS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \VX_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \VX_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \VX_SIM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \VX_UIM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 4 \VX_UIM_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 3 \VX_UIM_2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 2 \VX_UIM_3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \VX_VRA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \VX_VRB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \VX_VRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 10 \VX_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 11 \VX_XO_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 8 \XFL_FLM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XFL_FRB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \XFL_L + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \XFL_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \XFL_W + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 10 \XFL_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 10 \XFX_BHRBE + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XFX_DUI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 10 \XFX_DUIS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 8 \XFX_FXM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XFX_RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XFX_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 10 \XFX_SPR + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 10 \XFX_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XL_BA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XL_BB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 3 \XL_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 3 \XL_BFA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 2 \XL_BH + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XL_BI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XL_BO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XL_BO_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 output 28 \XL_BT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \XL_LK + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 15 \XL_OC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \XL_S + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 10 \XL_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \XO_OE + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XO_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XO_RB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XO_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \XO_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 9 \XO_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XS_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XS_RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \XS_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 9 \XS_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \XS_sh + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XX2_B + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 3 \XX2_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \XX2_BX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \XX2_BX_B + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 7 \XX2_DCMX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XX2_EO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XX2_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XX2_T + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \XX2_TX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \XX2_TX_T + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 4 \XX2_UIM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 2 \XX2_UIM_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 7 \XX2_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 9 \XX2_XO_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \XX2_dc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 7 \XX2_dc_dm_dx + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \XX2_dm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XX2_dx + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XX3_A + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \XX3_AX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \XX3_AX_A + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XX3_B + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 3 \XX3_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \XX3_BX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \XX3_BX_B + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 2 \XX3_DM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \XX3_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 2 \XX3_SHW + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XX3_T + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \XX3_TX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \XX3_TX_T + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 4 \XX3_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 8 \XX3_XO_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 9 \XX3_XO_2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XX4_A + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \XX4_AX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \XX4_AX_A + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XX4_B + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \XX4_BX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \XX4_BX_B + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XX4_C + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \XX4_CX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \XX4_CX_C + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XX4_T + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \XX4_TX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \XX4_TX_T + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 2 \XX4_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \X_A + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 3 output 26 \X_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 3 output 27 \X_BFA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_BO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 4 \X_CT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 7 \X_DCMX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 3 \X_DRM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \X_E + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 2 \X_EO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_EO_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \X_EX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 4 \X_E_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_FC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_FRA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_FRAp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_FRB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_FRBp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_FRS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_FRSp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_FRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_FRTp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 3 \X_IH + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 8 \X_IMM8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \X_L + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \X_L1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 2 \X_L2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 2 \X_L3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_MO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_NB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \X_PRS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \X_R + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_RB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 2 \X_RIC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 2 \X_RM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \X_RO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_RSp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_RTp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \X_R_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \X_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_S + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_SH + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_SI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 2 \X_SP + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 4 \X_SR + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \X_SX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \X_SX_S + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_T + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 10 \X_TBR + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_TH + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_TO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \X_TX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \X_TX_T + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 4 \X_U + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_UIM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_VRS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_VRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \X_W + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 2 \X_WC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 10 \X_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 8 \X_XO_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 3 \Z22_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \Z22_DCM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \Z22_DGM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \Z22_FRA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \Z22_FRAp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \Z22_FRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \Z22_FRTp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \Z22_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \Z22_SH + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 9 \Z22_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \Z23_FRA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \Z23_FRAp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \Z23_FRB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \Z23_FRBp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \Z23_FRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \Z23_FRTp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \Z23_R + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 2 \Z23_RMC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \Z23_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \Z23_TE + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 8 \Z23_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \all_OPCD + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \all_PO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + wire input 1 \bigendian + attribute \src "issuer_ls180.v:59498.7-59498.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + wire width 32 output 2 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:320" + wire width 6 \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:442" + wire width 32 input 29 \raw_opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:478" + cell $mux $ternary$issuer_ls180.v:60443$3435 + parameter \WIDTH 32 + connect \A \raw_opcode_in + connect \B { \raw_opcode_in [7:0] \raw_opcode_in [15:8] \raw_opcode_in [23:16] \raw_opcode_in [31:24] } + connect \S \bigendian + connect \Y $ternary$issuer_ls180.v:60443$3435_Y + end + attribute \module_not_derived 1 + attribute \src "issuer_ls180.v:60444.13-60454.4" + cell \MUL_dec31 \MUL_dec31 + connect \MUL_dec31_cr_in \MUL_dec31_MUL_dec31_cr_in + connect \MUL_dec31_cr_out \MUL_dec31_MUL_dec31_cr_out + connect \MUL_dec31_function_unit \MUL_dec31_MUL_dec31_function_unit + connect \MUL_dec31_in2_sel \MUL_dec31_MUL_dec31_in2_sel + connect \MUL_dec31_internal_op \MUL_dec31_MUL_dec31_internal_op + connect \MUL_dec31_is_32b \MUL_dec31_MUL_dec31_is_32b + connect \MUL_dec31_rc_sel \MUL_dec31_MUL_dec31_rc_sel + connect \MUL_dec31_sgn \MUL_dec31_MUL_dec31_sgn + connect \opcode_in \MUL_dec31_opcode_in + end + attribute \src "issuer_ls180.v:59498.7-59498.20" + process $proc$issuer_ls180.v:59498$3444 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "issuer_ls180.v:60455.3-60467.6" + process $proc$issuer_ls180.v:60455$3436 + assign { } { } + assign { } { } + assign $0\MUL_function_unit[11:0] $1\MUL_function_unit[11:0] + attribute \src "issuer_ls180.v:60456.5-60456.29" + switch \initial + attribute \src "issuer_ls180.v:60456.9-60456.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\MUL_function_unit[11:0] \MUL_dec31_MUL_dec31_function_unit + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'000111 + assign { } { } + assign $1\MUL_function_unit[11:0] 12'000100000000 + case + assign $1\MUL_function_unit[11:0] 12'000000000000 + end + sync always + update \MUL_function_unit $0\MUL_function_unit[11:0] + end + attribute \src "issuer_ls180.v:60468.3-60480.6" + process $proc$issuer_ls180.v:60468$3437 + assign { } { } + assign { } { } + assign $0\MUL_internal_op[6:0] $1\MUL_internal_op[6:0] + attribute \src "issuer_ls180.v:60469.5-60469.29" + switch \initial + attribute \src "issuer_ls180.v:60469.9-60469.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\MUL_internal_op[6:0] \MUL_dec31_MUL_dec31_internal_op + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'000111 + assign { } { } + assign $1\MUL_internal_op[6:0] 7'0110010 + case + assign $1\MUL_internal_op[6:0] 7'0000000 + end + sync always + update \MUL_internal_op $0\MUL_internal_op[6:0] + end + attribute \src "issuer_ls180.v:60481.3-60493.6" + process $proc$issuer_ls180.v:60481$3438 + assign { } { } + assign { } { } + assign $0\MUL_in2_sel[3:0] $1\MUL_in2_sel[3:0] + attribute \src "issuer_ls180.v:60482.5-60482.29" + switch \initial + attribute \src "issuer_ls180.v:60482.9-60482.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\MUL_in2_sel[3:0] \MUL_dec31_MUL_dec31_in2_sel + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'000111 + assign { } { } + assign $1\MUL_in2_sel[3:0] 4'0011 + case + assign $1\MUL_in2_sel[3:0] 4'0000 + end + sync always + update \MUL_in2_sel $0\MUL_in2_sel[3:0] + end + attribute \src "issuer_ls180.v:60494.3-60506.6" + process $proc$issuer_ls180.v:60494$3439 + assign { } { } + assign { } { } + assign $0\MUL_cr_in[2:0] $1\MUL_cr_in[2:0] + attribute \src "issuer_ls180.v:60495.5-60495.29" + switch \initial + attribute \src "issuer_ls180.v:60495.9-60495.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\MUL_cr_in[2:0] \MUL_dec31_MUL_dec31_cr_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'000111 + assign { } { } + assign $1\MUL_cr_in[2:0] 3'000 + case + assign $1\MUL_cr_in[2:0] 3'000 + end + sync always + update \MUL_cr_in $0\MUL_cr_in[2:0] + end + attribute \src "issuer_ls180.v:60507.3-60519.6" + process $proc$issuer_ls180.v:60507$3440 + assign { } { } + assign { } { } + assign $0\MUL_cr_out[2:0] $1\MUL_cr_out[2:0] + attribute \src "issuer_ls180.v:60508.5-60508.29" + switch \initial + attribute \src "issuer_ls180.v:60508.9-60508.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\MUL_cr_out[2:0] \MUL_dec31_MUL_dec31_cr_out + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'000111 + assign { } { } + assign $1\MUL_cr_out[2:0] 3'001 + case + assign $1\MUL_cr_out[2:0] 3'000 + end + sync always + update \MUL_cr_out $0\MUL_cr_out[2:0] + end + attribute \src "issuer_ls180.v:60520.3-60532.6" + process $proc$issuer_ls180.v:60520$3441 + assign { } { } + assign { } { } + assign $0\MUL_rc_sel[1:0] $1\MUL_rc_sel[1:0] + attribute \src "issuer_ls180.v:60521.5-60521.29" + switch \initial + attribute \src "issuer_ls180.v:60521.9-60521.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\MUL_rc_sel[1:0] \MUL_dec31_MUL_dec31_rc_sel + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'000111 + assign { } { } + assign $1\MUL_rc_sel[1:0] 2'00 + case + assign $1\MUL_rc_sel[1:0] 2'00 + end + sync always + update \MUL_rc_sel $0\MUL_rc_sel[1:0] + end + attribute \src "issuer_ls180.v:60533.3-60545.6" + process $proc$issuer_ls180.v:60533$3442 + assign { } { } + assign { } { } + assign $0\MUL_is_32b[0:0] $1\MUL_is_32b[0:0] + attribute \src "issuer_ls180.v:60534.5-60534.29" + switch \initial + attribute \src "issuer_ls180.v:60534.9-60534.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\MUL_is_32b[0:0] \MUL_dec31_MUL_dec31_is_32b + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'000111 + assign { } { } + assign $1\MUL_is_32b[0:0] 1'0 + case + assign $1\MUL_is_32b[0:0] 1'0 + end + sync always + update \MUL_is_32b $0\MUL_is_32b[0:0] + end + attribute \src "issuer_ls180.v:60546.3-60558.6" + process $proc$issuer_ls180.v:60546$3443 + assign { } { } + assign { } { } + assign $0\MUL_sgn[0:0] $1\MUL_sgn[0:0] + attribute \src "issuer_ls180.v:60547.5-60547.29" + switch \initial + attribute \src "issuer_ls180.v:60547.9-60547.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\MUL_sgn[0:0] \MUL_dec31_MUL_dec31_sgn + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'000111 + assign { } { } + assign $1\MUL_sgn[0:0] 1'1 + case + assign $1\MUL_sgn[0:0] 1'0 + end + sync always + update \MUL_sgn $0\MUL_sgn[0:0] + end + connect \$1 $ternary$issuer_ls180.v:60443$3435_Y + connect \VC_XO \opcode_in [9:0] + connect \VC_VRT \opcode_in [25:21] + connect \VC_VRB \opcode_in [15:11] + connect \VC_VRA \opcode_in [20:16] + connect \VC_Rc \opcode_in [10] + connect \XS_XO \opcode_in [10:2] + connect \XS_sh { \opcode_in [1] \opcode_in [15:11] } + connect \XS_RS \opcode_in [25:21] + connect \XS_Rc \opcode_in [0] + connect \XS_RA \opcode_in [20:16] + connect \VA_XO \opcode_in [5:0] + connect \VA_VRT \opcode_in [25:21] + connect \VA_VRC \opcode_in [10:6] + connect \VA_VRB \opcode_in [15:11] + connect \VA_VRA \opcode_in [20:16] + connect \VA_SHB \opcode_in [9:6] + connect \VA_RT \opcode_in [25:21] + connect \VA_RC \opcode_in [10:6] + connect \VA_RB \opcode_in [15:11] + connect \VA_RA \opcode_in [20:16] + connect \TX_XO \opcode_in [6:1] + connect \TX_XBI \opcode_in [10:7] + connect \TX_UI \opcode_in [15:11] + connect \TX_RA \opcode_in [20:16] + connect \DQE_XO \opcode_in [1:0] + connect \DQE_RT \opcode_in [25:21] + connect \DQE_RA \opcode_in [20:16] + connect \XO_XO \opcode_in [9:1] + connect \XO_RT \opcode_in [25:21] + connect \XO_Rc \opcode_in [0] + connect \XO_RB \opcode_in [15:11] + connect \XO_RA \opcode_in [20:16] + connect \XO_OE \opcode_in [10] + connect \all_PO \opcode_in [31:26] + connect \all_OPCD \opcode_in [31:26] + connect \MD_XO \opcode_in [4:2] + connect \MD_sh { \opcode_in [1] \opcode_in [15:11] } + connect \MD_RS \opcode_in [25:21] + connect \MD_Rc \opcode_in [0] + connect \MD_RA \opcode_in [20:16] + connect \MD_me \opcode_in [10:5] + connect \MD_mb \opcode_in [10:5] + connect \M_SH \opcode_in [15:11] + connect \M_RS \opcode_in [25:21] + connect \M_Rc \opcode_in [0] + connect \M_RB \opcode_in [15:11] + connect \M_RA \opcode_in [20:16] + connect \M_ME \opcode_in [5:1] + connect \M_MB \opcode_in [10:6] + connect \SC_XO_1 \opcode_in [1:0] + connect \SC_XO \opcode_in [1] + connect \SC_LEV \opcode_in [11:5] + connect \MDS_XO \opcode_in [4:1] + connect \MDS_XBI_1 \opcode_in [10:7] + connect \MDS_XBI \opcode_in [10:7] + connect \MDS_RS \opcode_in [25:21] + connect \MDS_Rc \opcode_in [0] + connect \MDS_RB \opcode_in [15:11] + connect \MDS_RA \opcode_in [20:16] + connect \MDS_me \opcode_in [10:5] + connect \MDS_mb \opcode_in [10:5] + connect \MDS_IS \opcode_in [25:21] + connect \MDS_IB \opcode_in [15:11] + connect \Z23_XO \opcode_in [8:1] + connect \Z23_TE \opcode_in [20:16] + connect \Z23_RMC \opcode_in [10:9] + connect \Z23_Rc \opcode_in [0] + connect \Z23_R \opcode_in [16] + connect \Z23_FRTp \opcode_in [25:21] + connect \Z23_FRT \opcode_in [25:21] + connect \Z23_FRBp \opcode_in [15:11] + connect \Z23_FRB \opcode_in [15:11] + connect \Z23_FRAp \opcode_in [20:16] + connect \Z23_FRA \opcode_in [20:16] + connect \XFL_XO \opcode_in [10:1] + connect \XFL_W \opcode_in [16] + connect \XFL_Rc \opcode_in [0] + connect \XFL_L \opcode_in [25] + connect \XFL_FRB \opcode_in [15:11] + connect \XFL_FLM \opcode_in [24:17] + connect \VX_XO_1 \opcode_in [10:0] + connect \VX_XO { \opcode_in [10] \opcode_in [8:0] } + connect \VX_VRT \opcode_in [25:21] + connect \VX_VRB \opcode_in [15:11] + connect \VX_VRA \opcode_in [20:16] + connect \VX_UIM_3 \opcode_in [17:16] + connect \VX_UIM_2 \opcode_in [18:16] + connect \VX_UIM_1 \opcode_in [19:16] + connect \VX_UIM \opcode_in [20:16] + connect \VX_SIM \opcode_in [20:16] + connect \VX_RT \opcode_in [25:21] + connect \VX_RA \opcode_in [20:16] + connect \VX_PS \opcode_in [9] + connect \VX_EO \opcode_in [20:16] + connect \DS_XO \opcode_in [1:0] + connect \DS_VRT \opcode_in [25:21] + connect \DS_VRS \opcode_in [25:21] + connect \DS_RT \opcode_in [25:21] + connect \DS_RSp \opcode_in [25:21] + connect \DS_RS \opcode_in [25:21] + connect \DS_RA \opcode_in [20:16] + connect \DS_FRTp \opcode_in [25:21] + connect \DS_FRSp \opcode_in [25:21] + connect \DS_DS \opcode_in [15:2] + connect \DQ_XO \opcode_in [2:0] + connect \DQ_TX_T { \opcode_in [3] \opcode_in [25:21] } + connect \DQ_T \opcode_in [25:21] + connect \DQ_TX \opcode_in [3] + connect \DQ_SX_S { \opcode_in [3] \opcode_in [25:21] } + connect \DQ_S \opcode_in [25:21] + connect \DQ_SX \opcode_in [3] + connect \DQ_RTp \opcode_in [25:21] + connect \DQ_RA \opcode_in [20:16] + connect \DQ_PT \opcode_in [3:0] + connect \DQ_DQ \opcode_in [15:4] + connect \DX_XO \opcode_in [5:1] + connect \DX_RT \opcode_in [25:21] + connect \DX_d0_d1_d2 { \opcode_in [15:6] \opcode_in [20:16] \opcode_in [0] } + connect \DX_d2 \opcode_in [0] + connect \DX_d1 \opcode_in [20:16] + connect \DX_d0 \opcode_in [15:6] + connect \XFX_XO \opcode_in [10:1] + connect \XFX_SPR \opcode_in [20:11] + connect \XFX_RT \opcode_in [25:21] + connect \XFX_RS \opcode_in [25:21] + connect \XFX_FXM \opcode_in [19:12] + connect \XFX_DUIS \opcode_in [20:11] + connect \XFX_DUI \opcode_in [25:21] + connect \XFX_BHRBE \opcode_in [20:11] + connect \EVS_BFA \opcode_in [2:0] + connect \Z22_XO \opcode_in [9:1] + connect \Z22_SH \opcode_in [15:10] + connect \Z22_Rc \opcode_in [0] + connect \Z22_FRTp \opcode_in [25:21] + connect \Z22_FRT \opcode_in [25:21] + connect \Z22_FRAp \opcode_in [20:16] + connect \Z22_FRA \opcode_in [20:16] + connect \Z22_DGM \opcode_in [15:10] + connect \Z22_DCM \opcode_in [15:10] + connect \Z22_BF \opcode_in [25:23] + connect \XX2_XO_1 \opcode_in [10:2] + connect \XX2_XO { \opcode_in [10:7] \opcode_in [5:3] } + connect \XX2_UIM_1 \opcode_in [17:16] + connect \XX2_UIM \opcode_in [19:16] + connect \XX2_TX_T { \opcode_in [0] \opcode_in [25:21] } + connect \XX2_T \opcode_in [25:21] + connect \XX2_TX \opcode_in [0] + connect \XX2_RT \opcode_in [25:21] + connect \XX2_EO \opcode_in [20:16] + connect \XX2_DCMX \opcode_in [22:16] + connect \XX2_dc_dm_dx { \opcode_in [6] \opcode_in [2] \opcode_in [20:16] } + connect \XX2_dx \opcode_in [20:16] + connect \XX2_dm \opcode_in [2] + connect \XX2_dc \opcode_in [6] + connect \XX2_BX_B { \opcode_in [1] \opcode_in [15:11] } + connect \XX2_B \opcode_in [15:11] + connect \XX2_BX \opcode_in [1] + connect \XX2_BF \opcode_in [25:23] + connect \D_UI \opcode_in [15:0] + connect \D_TO \opcode_in [25:21] + connect \D_SI \opcode_in [15:0] + connect \D_RT \opcode_in [25:21] + connect \D_RS \opcode_in [25:21] + connect \D_RA \opcode_in [20:16] + connect \D_L \opcode_in [21] + connect \D_FRT \opcode_in [25:21] + connect \D_FRS \opcode_in [25:21] + connect \D_D \opcode_in [15:0] + connect \D_BF \opcode_in [25:23] + connect \A_XO \opcode_in [5:1] + connect \A_RT \opcode_in [25:21] + connect \A_Rc \opcode_in [0] + connect \A_RB \opcode_in [15:11] + connect \A_RA \opcode_in [20:16] + connect \A_FRT \opcode_in [25:21] + connect \A_FRC \opcode_in [10:6] + connect \A_FRB \opcode_in [15:11] + connect \A_FRA \opcode_in [20:16] + connect \A_BC \opcode_in [10:6] + connect \XL_XO \opcode_in [10:1] + connect \XL_S \opcode_in [11] + connect \XL_OC \opcode_in [25:11] + connect \XL_LK \opcode_in [0] + connect \XL_BT \opcode_in [25:21] + connect \XL_BO_1 \opcode_in [25:21] + connect \XL_BO \opcode_in [25:21] + connect \XL_BI \opcode_in [20:16] + connect \XL_BH \opcode_in [12:11] + connect \XL_BFA \opcode_in [20:18] + connect \XL_BF \opcode_in [25:23] + connect \XL_BB \opcode_in [15:11] + connect \XL_BA \opcode_in [20:16] + connect \XX4_XO \opcode_in [5:4] + connect \XX4_TX_T { \opcode_in [0] \opcode_in [25:21] } + connect \XX4_T \opcode_in [25:21] + connect \XX4_TX \opcode_in [0] + connect \XX4_CX_C { \opcode_in [3] \opcode_in [10:6] } + connect \XX4_C \opcode_in [10:6] + connect \XX4_CX \opcode_in [3] + connect \XX4_BX_B { \opcode_in [1] \opcode_in [15:11] } + connect \XX4_B \opcode_in [15:11] + connect \XX4_BX \opcode_in [1] + connect \XX4_AX_A { \opcode_in [2] \opcode_in [20:16] } + connect \XX4_A \opcode_in [20:16] + connect \XX4_AX \opcode_in [2] + connect \XX3_XO_2 \opcode_in [9:1] + connect \XX3_XO_1 \opcode_in [10:3] + connect \XX3_XO \opcode_in [10:7] + connect \XX3_TX_T { \opcode_in [0] \opcode_in [25:21] } + connect \XX3_T \opcode_in [25:21] + connect \XX3_TX \opcode_in [0] + connect \XX3_SHW \opcode_in [9:8] + connect \XX3_Rc \opcode_in [10] + connect \XX3_DM \opcode_in [9:8] + connect \XX3_BX_B { \opcode_in [1] \opcode_in [15:11] } + connect \XX3_B \opcode_in [15:11] + connect \XX3_BX \opcode_in [1] + connect \XX3_BF \opcode_in [25:23] + connect \XX3_AX_A { \opcode_in [2] \opcode_in [20:16] } + connect \XX3_A \opcode_in [20:16] + connect \XX3_AX \opcode_in [2] + connect \I_LK \opcode_in [0] + connect \I_LI \opcode_in [25:2] + connect \I_AA \opcode_in [1] + connect \B_LK \opcode_in [0] + connect \B_BO \opcode_in [25:21] + connect \B_BI \opcode_in [20:16] + connect \B_BD \opcode_in [15:2] + connect \B_AA \opcode_in [1] + connect \X_XO_1 \opcode_in [8:1] + connect \X_XO \opcode_in [10:1] + connect \X_WC \opcode_in [22:21] + connect \X_W \opcode_in [16] + connect \X_VRT \opcode_in [25:21] + connect \X_VRS \opcode_in [25:21] + connect \X_UIM \opcode_in [20:16] + connect \X_U \opcode_in [15:12] + connect \X_TX_T { \opcode_in [0] \opcode_in [25:21] } + connect \X_TX \opcode_in [0] + connect \X_TO \opcode_in [25:21] + connect \X_TH \opcode_in [25:21] + connect \X_TBR \opcode_in [20:11] + connect \X_T \opcode_in [25:21] + connect \X_SX_S { \opcode_in [0] \opcode_in [25:21] } + connect \X_SX \opcode_in [0] + connect \X_SR \opcode_in [19:16] + connect \X_SP \opcode_in [20:19] + connect \X_SI \opcode_in [15:11] + connect \X_SH \opcode_in [15:11] + connect \X_S \opcode_in [25:21] + connect \X_RTp \opcode_in [25:21] + connect \X_RT \opcode_in [25:21] + connect \X_RSp \opcode_in [25:21] + connect \X_RS \opcode_in [25:21] + connect \X_RO \opcode_in [0] + connect \X_RM \opcode_in [12:11] + connect \X_RIC \opcode_in [19:18] + connect \X_Rc \opcode_in [0] + connect \X_RB \opcode_in [15:11] + connect \X_RA \opcode_in [20:16] + connect \X_R_1 \opcode_in [16] + connect \X_R \opcode_in [21] + connect \X_PRS \opcode_in [17] + connect \X_NB \opcode_in [15:11] + connect \X_MO \opcode_in [25:21] + connect \X_L3 \opcode_in [17:16] + connect \X_L1 \opcode_in [16] + connect \X_L \opcode_in [21] + connect \X_L2 \opcode_in [22:21] + connect \X_IMM8 \opcode_in [18:11] + connect \X_IH \opcode_in [23:21] + connect \X_FRTp \opcode_in [25:21] + connect \X_FRT \opcode_in [25:21] + connect \X_FRSp \opcode_in [25:21] + connect \X_FRS \opcode_in [25:21] + connect \X_FRBp \opcode_in [15:11] + connect \X_FRB \opcode_in [15:11] + connect \X_FRAp \opcode_in [20:16] + connect \X_FRA \opcode_in [20:16] + connect \X_FC \opcode_in [15:11] + connect \X_EX \opcode_in [0] + connect \X_EO_1 \opcode_in [20:16] + connect \X_EO \opcode_in [20:19] + connect \X_E_1 \opcode_in [19:16] + connect \X_E \opcode_in [15] + connect \X_DRM \opcode_in [13:11] + connect \X_DCMX \opcode_in [22:16] + connect \X_CT \opcode_in [24:21] + connect \X_BO \opcode_in [25:21] + connect \X_BFA \opcode_in [20:18] + connect \X_BF \opcode_in [25:23] + connect \X_A \opcode_in [25] + connect \MUL_SPR \opcode_in [20:11] + connect \MUL_MB \opcode_in [10:6] + connect \MUL_ME \opcode_in [5:1] + connect \MUL_SH \opcode_in [15:11] + connect \MUL_BC \opcode_in [10:6] + connect \MUL_TO \opcode_in [25:21] + connect \MUL_DS \opcode_in [15:2] + connect \MUL_D \opcode_in [15:0] + connect \MUL_BH \opcode_in [12:11] + connect \MUL_BI \opcode_in [20:16] + connect \MUL_BO \opcode_in [25:21] + connect \MUL_FXM \opcode_in [19:12] + connect \MUL_BT \opcode_in [25:21] + connect \MUL_BA \opcode_in [20:16] + connect \MUL_BB \opcode_in [15:11] + connect \MUL_CR \opcode_in [10:1] + connect \MUL_BF \opcode_in [25:23] + connect \MUL_BD \opcode_in [15:2] + connect \MUL_OE \opcode_in [10] + connect \MUL_Rc \opcode_in [0] + connect \MUL_AA \opcode_in [1] + connect \MUL_LK \opcode_in [0] + connect \MUL_LI \opcode_in [25:2] + connect \MUL_ME32 \opcode_in [5:1] + connect \MUL_MB32 \opcode_in [10:6] + connect \MUL_sh { \opcode_in [1] \opcode_in [15:11] } + connect \MUL_SH32 \opcode_in [15:11] + connect \MUL_L \opcode_in [21] + connect \MUL_UI \opcode_in [15:0] + connect \MUL_SI \opcode_in [15:0] + connect \MUL_RB \opcode_in [15:11] + connect \MUL_RA \opcode_in [20:16] + connect \MUL_RT \opcode_in [25:21] + connect \MUL_RS \opcode_in [25:21] + connect \opcode_in \$1 + connect \MUL_dec31_opcode_in \opcode_in + connect \opcode_switch \opcode_in [31:26] +end +attribute \src "issuer_ls180.v:60892.1-62579.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.dec_SHIFT_ROT.dec" +attribute \generator "nMigen" +module \dec$185 + attribute \src "issuer_ls180.v:62161.3-62182.6" + wire width 3 $0\SHIFT_ROT_cr_in[2:0] + attribute \src "issuer_ls180.v:62183.3-62204.6" + wire width 3 $0\SHIFT_ROT_cr_out[2:0] + attribute \src "issuer_ls180.v:62227.3-62248.6" + wire width 2 $0\SHIFT_ROT_cry_in[1:0] + attribute \src "issuer_ls180.v:62029.3-62050.6" + wire $0\SHIFT_ROT_cry_out[0:0] + attribute \src "issuer_ls180.v:62095.3-62116.6" + wire width 12 $0\SHIFT_ROT_function_unit[11:0] + attribute \src "issuer_ls180.v:62139.3-62160.6" + wire width 4 $0\SHIFT_ROT_in2_sel[3:0] + attribute \src "issuer_ls180.v:62117.3-62138.6" + wire width 7 $0\SHIFT_ROT_internal_op[6:0] + attribute \src "issuer_ls180.v:62051.3-62072.6" + wire $0\SHIFT_ROT_is_32b[0:0] + attribute \src "issuer_ls180.v:62205.3-62226.6" + wire width 2 $0\SHIFT_ROT_rc_sel[1:0] + attribute \src "issuer_ls180.v:62073.3-62094.6" + wire $0\SHIFT_ROT_sgn[0:0] + attribute \src "issuer_ls180.v:60893.7-60893.20" + wire $0\initial[0:0] + attribute \src "issuer_ls180.v:62161.3-62182.6" + wire width 3 $1\SHIFT_ROT_cr_in[2:0] + attribute \src "issuer_ls180.v:62183.3-62204.6" + wire width 3 $1\SHIFT_ROT_cr_out[2:0] + attribute \src "issuer_ls180.v:62227.3-62248.6" + wire width 2 $1\SHIFT_ROT_cry_in[1:0] + attribute \src "issuer_ls180.v:62029.3-62050.6" + wire $1\SHIFT_ROT_cry_out[0:0] + attribute \src "issuer_ls180.v:62095.3-62116.6" + wire width 12 $1\SHIFT_ROT_function_unit[11:0] + attribute \src "issuer_ls180.v:62139.3-62160.6" + wire width 4 $1\SHIFT_ROT_in2_sel[3:0] + attribute \src "issuer_ls180.v:62117.3-62138.6" + wire width 7 $1\SHIFT_ROT_internal_op[6:0] + attribute \src "issuer_ls180.v:62051.3-62072.6" + wire $1\SHIFT_ROT_is_32b[0:0] + attribute \src "issuer_ls180.v:62205.3-62226.6" + wire width 2 $1\SHIFT_ROT_rc_sel[1:0] + attribute \src "issuer_ls180.v:62073.3-62094.6" + wire $1\SHIFT_ROT_sgn[0:0] + attribute \src "issuer_ls180.v:62002.17-62002.211" + wire width 32 $ternary$issuer_ls180.v:62002$3445_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:478" + wire width 32 \$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \A_BC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \A_FRA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \A_FRB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \A_FRC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \A_FRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \A_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \A_RB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \A_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \A_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \A_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \B_AA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 14 \B_BD + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \B_BI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \B_BO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \B_LK + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \DQE_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \DQE_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 2 \DQE_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 12 \DQ_DQ + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 4 \DQ_PT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \DQ_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \DQ_RTp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \DQ_S + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \DQ_SX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \DQ_SX_S + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \DQ_T + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \DQ_TX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \DQ_TX_T + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 3 \DQ_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 14 \DS_DS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \DS_FRSp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \DS_FRTp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \DS_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \DS_RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \DS_RSp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \DS_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \DS_VRS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \DS_VRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 2 \DS_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \DX_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \DX_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 10 \DX_d0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 16 \DX_d0_d1_d2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \DX_d1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \DX_d2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 3 \D_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 16 \D_D + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \D_FRS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \D_FRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \D_L + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \D_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \D_RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \D_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 16 \D_SI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \D_TO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 16 \D_UI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 3 \EVS_BFA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \I_AA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 24 \I_LI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \I_LK + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \MDS_IB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \MDS_IS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \MDS_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \MDS_RB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \MDS_RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \MDS_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 4 \MDS_XBI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 4 \MDS_XBI_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 4 \MDS_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \MDS_mb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \MDS_me + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \MD_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \MD_RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \MD_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 3 \MD_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \MD_mb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \MD_me + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \MD_sh + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \M_MB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \M_ME + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \M_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \M_RB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \M_RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \M_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \M_SH + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 7 \SC_LEV + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \SC_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 2 \SC_XO_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire \SHIFT_ROT_AA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 output 22 \SHIFT_ROT_BA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 output 21 \SHIFT_ROT_BB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 output 27 \SHIFT_ROT_BC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 14 output 20 \SHIFT_ROT_BD + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 3 \SHIFT_ROT_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 2 \SHIFT_ROT_BH + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 output 25 \SHIFT_ROT_BI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 \SHIFT_ROT_BO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 output 23 \SHIFT_ROT_BT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 10 \SHIFT_ROT_CR + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 16 \SHIFT_ROT_D + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 14 output 26 \SHIFT_ROT_DS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 8 output 24 \SHIFT_ROT_FXM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire \SHIFT_ROT_L + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 24 output 17 \SHIFT_ROT_LI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire \SHIFT_ROT_LK + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 \SHIFT_ROT_MB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 \SHIFT_ROT_MB32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 \SHIFT_ROT_ME + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 \SHIFT_ROT_ME32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire output 19 \SHIFT_ROT_OE + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 \SHIFT_ROT_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 \SHIFT_ROT_RB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 \SHIFT_ROT_RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 \SHIFT_ROT_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire output 18 \SHIFT_ROT_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 \SHIFT_ROT_SH + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 output 15 \SHIFT_ROT_SH32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 16 output 13 \SHIFT_ROT_SI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 10 \SHIFT_ROT_SPR + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 \SHIFT_ROT_TO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 16 output 14 \SHIFT_ROT_UI + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 4 \SHIFT_ROT_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 5 \SHIFT_ROT_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 9 \SHIFT_ROT_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 10 \SHIFT_ROT_cry_out + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 \SHIFT_ROT_dec30_SHIFT_ROT_dec30_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 \SHIFT_ROT_dec30_SHIFT_ROT_dec30_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \SHIFT_ROT_dec30_SHIFT_ROT_dec30_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \SHIFT_ROT_dec30_SHIFT_ROT_dec30_cry_out + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 12 \SHIFT_ROT_dec30_SHIFT_ROT_dec30_function_unit + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 \SHIFT_ROT_dec30_SHIFT_ROT_dec30_in2_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 7 \SHIFT_ROT_dec30_SHIFT_ROT_dec30_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \SHIFT_ROT_dec30_SHIFT_ROT_dec30_is_32b + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \SHIFT_ROT_dec30_SHIFT_ROT_dec30_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \SHIFT_ROT_dec30_SHIFT_ROT_dec30_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + wire width 32 \SHIFT_ROT_dec30_opcode_in + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 \SHIFT_ROT_dec31_SHIFT_ROT_dec31_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 \SHIFT_ROT_dec31_SHIFT_ROT_dec31_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \SHIFT_ROT_dec31_SHIFT_ROT_dec31_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \SHIFT_ROT_dec31_SHIFT_ROT_dec31_cry_out + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 12 \SHIFT_ROT_dec31_SHIFT_ROT_dec31_function_unit + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 \SHIFT_ROT_dec31_SHIFT_ROT_dec31_in2_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 7 \SHIFT_ROT_dec31_SHIFT_ROT_dec31_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \SHIFT_ROT_dec31_SHIFT_ROT_dec31_is_32b + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \SHIFT_ROT_dec31_SHIFT_ROT_dec31_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \SHIFT_ROT_dec31_SHIFT_ROT_dec31_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + wire width 32 \SHIFT_ROT_dec31_opcode_in + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 12 output 7 \SHIFT_ROT_function_unit + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 output 8 \SHIFT_ROT_in2_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 7 output 6 \SHIFT_ROT_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 11 \SHIFT_ROT_is_32b + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 3 \SHIFT_ROT_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 12 \SHIFT_ROT_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 6 output 16 \SHIFT_ROT_sh + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \TX_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \TX_UI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 4 \TX_XBI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \TX_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \VA_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \VA_RB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \VA_RC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \VA_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 4 \VA_SHB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \VA_VRA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \VA_VRB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \VA_VRC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \VA_VRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \VA_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \VC_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \VC_VRA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \VC_VRB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \VC_VRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 10 \VC_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \VX_EO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \VX_PS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \VX_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \VX_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \VX_SIM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \VX_UIM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 4 \VX_UIM_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 3 \VX_UIM_2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 2 \VX_UIM_3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \VX_VRA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \VX_VRB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \VX_VRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 10 \VX_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 11 \VX_XO_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 8 \XFL_FLM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XFL_FRB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \XFL_L + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \XFL_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \XFL_W + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 10 \XFL_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 10 \XFX_BHRBE + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XFX_DUI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 10 \XFX_DUIS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 8 \XFX_FXM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XFX_RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XFX_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 10 \XFX_SPR + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 10 \XFX_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XL_BA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XL_BB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 3 \XL_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 3 \XL_BFA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 2 \XL_BH + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XL_BI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XL_BO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XL_BO_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 output 30 \XL_BT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \XL_LK + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 15 \XL_OC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \XL_S + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 10 \XL_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \XO_OE + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XO_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XO_RB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XO_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \XO_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 9 \XO_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XS_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XS_RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \XS_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 9 \XS_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \XS_sh + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XX2_B + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 3 \XX2_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \XX2_BX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \XX2_BX_B + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 7 \XX2_DCMX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XX2_EO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XX2_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XX2_T + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \XX2_TX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \XX2_TX_T + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 4 \XX2_UIM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 2 \XX2_UIM_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 7 \XX2_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 9 \XX2_XO_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \XX2_dc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 7 \XX2_dc_dm_dx + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \XX2_dm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XX2_dx + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XX3_A + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \XX3_AX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \XX3_AX_A + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XX3_B + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 3 \XX3_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \XX3_BX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \XX3_BX_B + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 2 \XX3_DM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \XX3_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 2 \XX3_SHW + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XX3_T + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \XX3_TX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \XX3_TX_T + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 4 \XX3_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 8 \XX3_XO_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 9 \XX3_XO_2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XX4_A + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \XX4_AX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \XX4_AX_A + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XX4_B + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \XX4_BX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \XX4_BX_B + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XX4_C + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \XX4_CX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \XX4_CX_C + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XX4_T + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \XX4_TX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \XX4_TX_T + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 2 \XX4_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \X_A + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 3 output 28 \X_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 3 output 29 \X_BFA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_BO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 4 \X_CT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 7 \X_DCMX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 3 \X_DRM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \X_E + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 2 \X_EO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_EO_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \X_EX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 4 \X_E_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_FC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_FRA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_FRAp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_FRB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_FRBp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_FRS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_FRSp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_FRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_FRTp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 3 \X_IH + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 8 \X_IMM8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \X_L + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \X_L1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 2 \X_L2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 2 \X_L3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_MO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_NB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \X_PRS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \X_R + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_RB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 2 \X_RIC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 2 \X_RM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \X_RO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_RSp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_RTp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \X_R_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \X_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_S + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_SH + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_SI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 2 \X_SP + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 4 \X_SR + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \X_SX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \X_SX_S + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_T + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 10 \X_TBR + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_TH + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_TO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \X_TX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \X_TX_T + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 4 \X_U + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_UIM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_VRS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_VRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \X_W + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 2 \X_WC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 10 \X_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 8 \X_XO_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 3 \Z22_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \Z22_DCM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \Z22_DGM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \Z22_FRA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \Z22_FRAp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \Z22_FRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \Z22_FRTp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \Z22_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \Z22_SH + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 9 \Z22_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \Z23_FRA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \Z23_FRAp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \Z23_FRB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \Z23_FRBp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \Z23_FRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \Z23_FRTp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \Z23_R + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 2 \Z23_RMC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \Z23_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \Z23_TE + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 8 \Z23_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \all_OPCD + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \all_PO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + wire input 1 \bigendian + attribute \src "issuer_ls180.v:60893.7-60893.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + wire width 32 output 2 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:320" + wire width 6 \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:442" + wire width 32 input 31 \raw_opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:478" + cell $mux $ternary$issuer_ls180.v:62002$3445 + parameter \WIDTH 32 + connect \A \raw_opcode_in + connect \B { \raw_opcode_in [7:0] \raw_opcode_in [15:8] \raw_opcode_in [23:16] \raw_opcode_in [31:24] } + connect \S \bigendian + connect \Y $ternary$issuer_ls180.v:62002$3445_Y + end + attribute \module_not_derived 1 + attribute \src "issuer_ls180.v:62003.19-62015.4" + cell \SHIFT_ROT_dec30 \SHIFT_ROT_dec30 + connect \SHIFT_ROT_dec30_cr_in \SHIFT_ROT_dec30_SHIFT_ROT_dec30_cr_in + connect \SHIFT_ROT_dec30_cr_out \SHIFT_ROT_dec30_SHIFT_ROT_dec30_cr_out + connect \SHIFT_ROT_dec30_cry_in \SHIFT_ROT_dec30_SHIFT_ROT_dec30_cry_in + connect \SHIFT_ROT_dec30_cry_out \SHIFT_ROT_dec30_SHIFT_ROT_dec30_cry_out + connect \SHIFT_ROT_dec30_function_unit \SHIFT_ROT_dec30_SHIFT_ROT_dec30_function_unit + connect \SHIFT_ROT_dec30_in2_sel \SHIFT_ROT_dec30_SHIFT_ROT_dec30_in2_sel + connect \SHIFT_ROT_dec30_internal_op \SHIFT_ROT_dec30_SHIFT_ROT_dec30_internal_op + connect \SHIFT_ROT_dec30_is_32b \SHIFT_ROT_dec30_SHIFT_ROT_dec30_is_32b + connect \SHIFT_ROT_dec30_rc_sel \SHIFT_ROT_dec30_SHIFT_ROT_dec30_rc_sel + connect \SHIFT_ROT_dec30_sgn \SHIFT_ROT_dec30_SHIFT_ROT_dec30_sgn + connect \opcode_in \SHIFT_ROT_dec30_opcode_in + end + attribute \module_not_derived 1 + attribute \src "issuer_ls180.v:62016.19-62028.4" + cell \SHIFT_ROT_dec31 \SHIFT_ROT_dec31 + connect \SHIFT_ROT_dec31_cr_in \SHIFT_ROT_dec31_SHIFT_ROT_dec31_cr_in + connect \SHIFT_ROT_dec31_cr_out \SHIFT_ROT_dec31_SHIFT_ROT_dec31_cr_out + connect \SHIFT_ROT_dec31_cry_in \SHIFT_ROT_dec31_SHIFT_ROT_dec31_cry_in + connect \SHIFT_ROT_dec31_cry_out \SHIFT_ROT_dec31_SHIFT_ROT_dec31_cry_out + connect \SHIFT_ROT_dec31_function_unit \SHIFT_ROT_dec31_SHIFT_ROT_dec31_function_unit + connect \SHIFT_ROT_dec31_in2_sel \SHIFT_ROT_dec31_SHIFT_ROT_dec31_in2_sel + connect \SHIFT_ROT_dec31_internal_op \SHIFT_ROT_dec31_SHIFT_ROT_dec31_internal_op + connect \SHIFT_ROT_dec31_is_32b \SHIFT_ROT_dec31_SHIFT_ROT_dec31_is_32b + connect \SHIFT_ROT_dec31_rc_sel \SHIFT_ROT_dec31_SHIFT_ROT_dec31_rc_sel + connect \SHIFT_ROT_dec31_sgn \SHIFT_ROT_dec31_SHIFT_ROT_dec31_sgn + connect \opcode_in \SHIFT_ROT_dec31_opcode_in + end + attribute \src "issuer_ls180.v:60893.7-60893.20" + process $proc$issuer_ls180.v:60893$3456 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "issuer_ls180.v:62029.3-62050.6" + process $proc$issuer_ls180.v:62029$3446 + assign { } { } + assign { } { } + assign $0\SHIFT_ROT_cry_out[0:0] $1\SHIFT_ROT_cry_out[0:0] + attribute \src "issuer_ls180.v:62030.5-62030.29" + switch \initial + attribute \src "issuer_ls180.v:62030.9-62030.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'011110 + assign { } { } + assign $1\SHIFT_ROT_cry_out[0:0] \SHIFT_ROT_dec30_SHIFT_ROT_dec30_cry_out + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\SHIFT_ROT_cry_out[0:0] \SHIFT_ROT_dec31_SHIFT_ROT_dec31_cry_out + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'010100 + assign { } { } + assign $1\SHIFT_ROT_cry_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'010101 + assign { } { } + assign $1\SHIFT_ROT_cry_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'010111 + assign { } { } + assign $1\SHIFT_ROT_cry_out[0:0] 1'0 + case + assign $1\SHIFT_ROT_cry_out[0:0] 1'0 + end + sync always + update \SHIFT_ROT_cry_out $0\SHIFT_ROT_cry_out[0:0] + end + attribute \src "issuer_ls180.v:62051.3-62072.6" + process $proc$issuer_ls180.v:62051$3447 + assign { } { } + assign { } { } + assign $0\SHIFT_ROT_is_32b[0:0] $1\SHIFT_ROT_is_32b[0:0] + attribute \src "issuer_ls180.v:62052.5-62052.29" + switch \initial + attribute \src "issuer_ls180.v:62052.9-62052.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'011110 + assign { } { } + assign $1\SHIFT_ROT_is_32b[0:0] \SHIFT_ROT_dec30_SHIFT_ROT_dec30_is_32b + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\SHIFT_ROT_is_32b[0:0] \SHIFT_ROT_dec31_SHIFT_ROT_dec31_is_32b + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'010100 + assign { } { } + assign $1\SHIFT_ROT_is_32b[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'010101 + assign { } { } + assign $1\SHIFT_ROT_is_32b[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'010111 + assign { } { } + assign $1\SHIFT_ROT_is_32b[0:0] 1'1 + case + assign $1\SHIFT_ROT_is_32b[0:0] 1'0 + end + sync always + update \SHIFT_ROT_is_32b $0\SHIFT_ROT_is_32b[0:0] + end + attribute \src "issuer_ls180.v:62073.3-62094.6" + process $proc$issuer_ls180.v:62073$3448 + assign { } { } + assign { } { } + assign $0\SHIFT_ROT_sgn[0:0] $1\SHIFT_ROT_sgn[0:0] + attribute \src "issuer_ls180.v:62074.5-62074.29" + switch \initial + attribute \src "issuer_ls180.v:62074.9-62074.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'011110 + assign { } { } + assign $1\SHIFT_ROT_sgn[0:0] \SHIFT_ROT_dec30_SHIFT_ROT_dec30_sgn + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\SHIFT_ROT_sgn[0:0] \SHIFT_ROT_dec31_SHIFT_ROT_dec31_sgn + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'010100 + assign { } { } + assign $1\SHIFT_ROT_sgn[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'010101 + assign { } { } + assign $1\SHIFT_ROT_sgn[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'010111 + assign { } { } + assign $1\SHIFT_ROT_sgn[0:0] 1'0 + case + assign $1\SHIFT_ROT_sgn[0:0] 1'0 + end + sync always + update \SHIFT_ROT_sgn $0\SHIFT_ROT_sgn[0:0] + end + attribute \src "issuer_ls180.v:62095.3-62116.6" + process $proc$issuer_ls180.v:62095$3449 + assign { } { } + assign { } { } + assign $0\SHIFT_ROT_function_unit[11:0] $1\SHIFT_ROT_function_unit[11:0] + attribute \src "issuer_ls180.v:62096.5-62096.29" + switch \initial + attribute \src "issuer_ls180.v:62096.9-62096.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'011110 + assign { } { } + assign $1\SHIFT_ROT_function_unit[11:0] \SHIFT_ROT_dec30_SHIFT_ROT_dec30_function_unit + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\SHIFT_ROT_function_unit[11:0] \SHIFT_ROT_dec31_SHIFT_ROT_dec31_function_unit + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'010100 + assign { } { } + assign $1\SHIFT_ROT_function_unit[11:0] 12'000000001000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'010101 + assign { } { } + assign $1\SHIFT_ROT_function_unit[11:0] 12'000000001000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'010111 + assign { } { } + assign $1\SHIFT_ROT_function_unit[11:0] 12'000000001000 + case + assign $1\SHIFT_ROT_function_unit[11:0] 12'000000000000 + end + sync always + update \SHIFT_ROT_function_unit $0\SHIFT_ROT_function_unit[11:0] + end + attribute \src "issuer_ls180.v:62117.3-62138.6" + process $proc$issuer_ls180.v:62117$3450 + assign { } { } + assign { } { } + assign $0\SHIFT_ROT_internal_op[6:0] $1\SHIFT_ROT_internal_op[6:0] + attribute \src "issuer_ls180.v:62118.5-62118.29" + switch \initial + attribute \src "issuer_ls180.v:62118.9-62118.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'011110 + assign { } { } + assign $1\SHIFT_ROT_internal_op[6:0] \SHIFT_ROT_dec30_SHIFT_ROT_dec30_internal_op + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\SHIFT_ROT_internal_op[6:0] \SHIFT_ROT_dec31_SHIFT_ROT_dec31_internal_op + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'010100 + assign { } { } + assign $1\SHIFT_ROT_internal_op[6:0] 7'0111000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'010101 + assign { } { } + assign $1\SHIFT_ROT_internal_op[6:0] 7'0111000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'010111 + assign { } { } + assign $1\SHIFT_ROT_internal_op[6:0] 7'0111000 + case + assign $1\SHIFT_ROT_internal_op[6:0] 7'0000000 + end + sync always + update \SHIFT_ROT_internal_op $0\SHIFT_ROT_internal_op[6:0] + end + attribute \src "issuer_ls180.v:62139.3-62160.6" + process $proc$issuer_ls180.v:62139$3451 + assign { } { } + assign { } { } + assign $0\SHIFT_ROT_in2_sel[3:0] $1\SHIFT_ROT_in2_sel[3:0] + attribute \src "issuer_ls180.v:62140.5-62140.29" + switch \initial + attribute \src "issuer_ls180.v:62140.9-62140.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'011110 + assign { } { } + assign $1\SHIFT_ROT_in2_sel[3:0] \SHIFT_ROT_dec30_SHIFT_ROT_dec30_in2_sel + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\SHIFT_ROT_in2_sel[3:0] \SHIFT_ROT_dec31_SHIFT_ROT_dec31_in2_sel + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'010100 + assign { } { } + assign $1\SHIFT_ROT_in2_sel[3:0] 4'1011 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'010101 + assign { } { } + assign $1\SHIFT_ROT_in2_sel[3:0] 4'1011 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'010111 + assign { } { } + assign $1\SHIFT_ROT_in2_sel[3:0] 4'0001 + case + assign $1\SHIFT_ROT_in2_sel[3:0] 4'0000 + end + sync always + update \SHIFT_ROT_in2_sel $0\SHIFT_ROT_in2_sel[3:0] + end + attribute \src "issuer_ls180.v:62161.3-62182.6" + process $proc$issuer_ls180.v:62161$3452 + assign { } { } + assign { } { } + assign $0\SHIFT_ROT_cr_in[2:0] $1\SHIFT_ROT_cr_in[2:0] + attribute \src "issuer_ls180.v:62162.5-62162.29" + switch \initial + attribute \src "issuer_ls180.v:62162.9-62162.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'011110 + assign { } { } + assign $1\SHIFT_ROT_cr_in[2:0] \SHIFT_ROT_dec30_SHIFT_ROT_dec30_cr_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\SHIFT_ROT_cr_in[2:0] \SHIFT_ROT_dec31_SHIFT_ROT_dec31_cr_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'010100 + assign { } { } + assign $1\SHIFT_ROT_cr_in[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'010101 + assign { } { } + assign $1\SHIFT_ROT_cr_in[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'010111 + assign { } { } + assign $1\SHIFT_ROT_cr_in[2:0] 3'000 + case + assign $1\SHIFT_ROT_cr_in[2:0] 3'000 + end + sync always + update \SHIFT_ROT_cr_in $0\SHIFT_ROT_cr_in[2:0] + end + attribute \src "issuer_ls180.v:62183.3-62204.6" + process $proc$issuer_ls180.v:62183$3453 + assign { } { } + assign { } { } + assign $0\SHIFT_ROT_cr_out[2:0] $1\SHIFT_ROT_cr_out[2:0] + attribute \src "issuer_ls180.v:62184.5-62184.29" + switch \initial + attribute \src "issuer_ls180.v:62184.9-62184.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'011110 + assign { } { } + assign $1\SHIFT_ROT_cr_out[2:0] \SHIFT_ROT_dec30_SHIFT_ROT_dec30_cr_out + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\SHIFT_ROT_cr_out[2:0] \SHIFT_ROT_dec31_SHIFT_ROT_dec31_cr_out + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'010100 + assign { } { } + assign $1\SHIFT_ROT_cr_out[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'010101 + assign { } { } + assign $1\SHIFT_ROT_cr_out[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'010111 + assign { } { } + assign $1\SHIFT_ROT_cr_out[2:0] 3'000 + case + assign $1\SHIFT_ROT_cr_out[2:0] 3'000 + end + sync always + update \SHIFT_ROT_cr_out $0\SHIFT_ROT_cr_out[2:0] + end + attribute \src "issuer_ls180.v:62205.3-62226.6" + process $proc$issuer_ls180.v:62205$3454 + assign { } { } + assign { } { } + assign $0\SHIFT_ROT_rc_sel[1:0] $1\SHIFT_ROT_rc_sel[1:0] + attribute \src "issuer_ls180.v:62206.5-62206.29" + switch \initial + attribute \src "issuer_ls180.v:62206.9-62206.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'011110 + assign { } { } + assign $1\SHIFT_ROT_rc_sel[1:0] \SHIFT_ROT_dec30_SHIFT_ROT_dec30_rc_sel + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\SHIFT_ROT_rc_sel[1:0] \SHIFT_ROT_dec31_SHIFT_ROT_dec31_rc_sel + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'010100 + assign { } { } + assign $1\SHIFT_ROT_rc_sel[1:0] 2'10 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'010101 + assign { } { } + assign $1\SHIFT_ROT_rc_sel[1:0] 2'10 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'010111 + assign { } { } + assign $1\SHIFT_ROT_rc_sel[1:0] 2'10 + case + assign $1\SHIFT_ROT_rc_sel[1:0] 2'00 + end + sync always + update \SHIFT_ROT_rc_sel $0\SHIFT_ROT_rc_sel[1:0] + end + attribute \src "issuer_ls180.v:62227.3-62248.6" + process $proc$issuer_ls180.v:62227$3455 + assign { } { } + assign { } { } + assign $0\SHIFT_ROT_cry_in[1:0] $1\SHIFT_ROT_cry_in[1:0] + attribute \src "issuer_ls180.v:62228.5-62228.29" + switch \initial + attribute \src "issuer_ls180.v:62228.9-62228.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'011110 + assign { } { } + assign $1\SHIFT_ROT_cry_in[1:0] \SHIFT_ROT_dec30_SHIFT_ROT_dec30_cry_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\SHIFT_ROT_cry_in[1:0] \SHIFT_ROT_dec31_SHIFT_ROT_dec31_cry_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'010100 + assign { } { } + assign $1\SHIFT_ROT_cry_in[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'010101 + assign { } { } + assign $1\SHIFT_ROT_cry_in[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'010111 + assign { } { } + assign $1\SHIFT_ROT_cry_in[1:0] 2'00 + case + assign $1\SHIFT_ROT_cry_in[1:0] 2'00 + end + sync always + update \SHIFT_ROT_cry_in $0\SHIFT_ROT_cry_in[1:0] + end + connect \$1 $ternary$issuer_ls180.v:62002$3445_Y + connect \VC_XO \opcode_in [9:0] + connect \VC_VRT \opcode_in [25:21] + connect \VC_VRB \opcode_in [15:11] + connect \VC_VRA \opcode_in [20:16] + connect \VC_Rc \opcode_in [10] + connect \XS_XO \opcode_in [10:2] + connect \XS_sh { \opcode_in [1] \opcode_in [15:11] } + connect \XS_RS \opcode_in [25:21] + connect \XS_Rc \opcode_in [0] + connect \XS_RA \opcode_in [20:16] + connect \VA_XO \opcode_in [5:0] + connect \VA_VRT \opcode_in [25:21] + connect \VA_VRC \opcode_in [10:6] + connect \VA_VRB \opcode_in [15:11] + connect \VA_VRA \opcode_in [20:16] + connect \VA_SHB \opcode_in [9:6] + connect \VA_RT \opcode_in [25:21] + connect \VA_RC \opcode_in [10:6] + connect \VA_RB \opcode_in [15:11] + connect \VA_RA \opcode_in [20:16] + connect \TX_XO \opcode_in [6:1] + connect \TX_XBI \opcode_in [10:7] + connect \TX_UI \opcode_in [15:11] + connect \TX_RA \opcode_in [20:16] + connect \DQE_XO \opcode_in [1:0] + connect \DQE_RT \opcode_in [25:21] + connect \DQE_RA \opcode_in [20:16] + connect \XO_XO \opcode_in [9:1] + connect \XO_RT \opcode_in [25:21] + connect \XO_Rc \opcode_in [0] + connect \XO_RB \opcode_in [15:11] + connect \XO_RA \opcode_in [20:16] + connect \XO_OE \opcode_in [10] + connect \all_PO \opcode_in [31:26] + connect \all_OPCD \opcode_in [31:26] + connect \MD_XO \opcode_in [4:2] + connect \MD_sh { \opcode_in [1] \opcode_in [15:11] } + connect \MD_RS \opcode_in [25:21] + connect \MD_Rc \opcode_in [0] + connect \MD_RA \opcode_in [20:16] + connect \MD_me \opcode_in [10:5] + connect \MD_mb \opcode_in [10:5] + connect \M_SH \opcode_in [15:11] + connect \M_RS \opcode_in [25:21] + connect \M_Rc \opcode_in [0] + connect \M_RB \opcode_in [15:11] + connect \M_RA \opcode_in [20:16] + connect \M_ME \opcode_in [5:1] + connect \M_MB \opcode_in [10:6] + connect \SC_XO_1 \opcode_in [1:0] + connect \SC_XO \opcode_in [1] + connect \SC_LEV \opcode_in [11:5] + connect \MDS_XO \opcode_in [4:1] + connect \MDS_XBI_1 \opcode_in [10:7] + connect \MDS_XBI \opcode_in [10:7] + connect \MDS_RS \opcode_in [25:21] + connect \MDS_Rc \opcode_in [0] + connect \MDS_RB \opcode_in [15:11] + connect \MDS_RA \opcode_in [20:16] + connect \MDS_me \opcode_in [10:5] + connect \MDS_mb \opcode_in [10:5] + connect \MDS_IS \opcode_in [25:21] + connect \MDS_IB \opcode_in [15:11] + connect \Z23_XO \opcode_in [8:1] + connect \Z23_TE \opcode_in [20:16] + connect \Z23_RMC \opcode_in [10:9] + connect \Z23_Rc \opcode_in [0] + connect \Z23_R \opcode_in [16] + connect \Z23_FRTp \opcode_in [25:21] + connect \Z23_FRT \opcode_in [25:21] + connect \Z23_FRBp \opcode_in [15:11] + connect \Z23_FRB \opcode_in [15:11] + connect \Z23_FRAp \opcode_in [20:16] + connect \Z23_FRA \opcode_in [20:16] + connect \XFL_XO \opcode_in [10:1] + connect \XFL_W \opcode_in [16] + connect \XFL_Rc \opcode_in [0] + connect \XFL_L \opcode_in [25] + connect \XFL_FRB \opcode_in [15:11] + connect \XFL_FLM \opcode_in [24:17] + connect \VX_XO_1 \opcode_in [10:0] + connect \VX_XO { \opcode_in [10] \opcode_in [8:0] } + connect \VX_VRT \opcode_in [25:21] + connect \VX_VRB \opcode_in [15:11] + connect \VX_VRA \opcode_in [20:16] + connect \VX_UIM_3 \opcode_in [17:16] + connect \VX_UIM_2 \opcode_in [18:16] + connect \VX_UIM_1 \opcode_in [19:16] + connect \VX_UIM \opcode_in [20:16] + connect \VX_SIM \opcode_in [20:16] + connect \VX_RT \opcode_in [25:21] + connect \VX_RA \opcode_in [20:16] + connect \VX_PS \opcode_in [9] + connect \VX_EO \opcode_in [20:16] + connect \DS_XO \opcode_in [1:0] + connect \DS_VRT \opcode_in [25:21] + connect \DS_VRS \opcode_in [25:21] + connect \DS_RT \opcode_in [25:21] + connect \DS_RSp \opcode_in [25:21] + connect \DS_RS \opcode_in [25:21] + connect \DS_RA \opcode_in [20:16] + connect \DS_FRTp \opcode_in [25:21] + connect \DS_FRSp \opcode_in [25:21] + connect \DS_DS \opcode_in [15:2] + connect \DQ_XO \opcode_in [2:0] + connect \DQ_TX_T { \opcode_in [3] \opcode_in [25:21] } + connect \DQ_T \opcode_in [25:21] + connect \DQ_TX \opcode_in [3] + connect \DQ_SX_S { \opcode_in [3] \opcode_in [25:21] } + connect \DQ_S \opcode_in [25:21] + connect \DQ_SX \opcode_in [3] + connect \DQ_RTp \opcode_in [25:21] + connect \DQ_RA \opcode_in [20:16] + connect \DQ_PT \opcode_in [3:0] + connect \DQ_DQ \opcode_in [15:4] + connect \DX_XO \opcode_in [5:1] + connect \DX_RT \opcode_in [25:21] + connect \DX_d0_d1_d2 { \opcode_in [15:6] \opcode_in [20:16] \opcode_in [0] } + connect \DX_d2 \opcode_in [0] + connect \DX_d1 \opcode_in [20:16] + connect \DX_d0 \opcode_in [15:6] + connect \XFX_XO \opcode_in [10:1] + connect \XFX_SPR \opcode_in [20:11] + connect \XFX_RT \opcode_in [25:21] + connect \XFX_RS \opcode_in [25:21] + connect \XFX_FXM \opcode_in [19:12] + connect \XFX_DUIS \opcode_in [20:11] + connect \XFX_DUI \opcode_in [25:21] + connect \XFX_BHRBE \opcode_in [20:11] + connect \EVS_BFA \opcode_in [2:0] + connect \Z22_XO \opcode_in [9:1] + connect \Z22_SH \opcode_in [15:10] + connect \Z22_Rc \opcode_in [0] + connect \Z22_FRTp \opcode_in [25:21] + connect \Z22_FRT \opcode_in [25:21] + connect \Z22_FRAp \opcode_in [20:16] + connect \Z22_FRA \opcode_in [20:16] + connect \Z22_DGM \opcode_in [15:10] + connect \Z22_DCM \opcode_in [15:10] + connect \Z22_BF \opcode_in [25:23] + connect \XX2_XO_1 \opcode_in [10:2] + connect \XX2_XO { \opcode_in [10:7] \opcode_in [5:3] } + connect \XX2_UIM_1 \opcode_in [17:16] + connect \XX2_UIM \opcode_in [19:16] + connect \XX2_TX_T { \opcode_in [0] \opcode_in [25:21] } + connect \XX2_T \opcode_in [25:21] + connect \XX2_TX \opcode_in [0] + connect \XX2_RT \opcode_in [25:21] + connect \XX2_EO \opcode_in [20:16] + connect \XX2_DCMX \opcode_in [22:16] + connect \XX2_dc_dm_dx { \opcode_in [6] \opcode_in [2] \opcode_in [20:16] } + connect \XX2_dx \opcode_in [20:16] + connect \XX2_dm \opcode_in [2] + connect \XX2_dc \opcode_in [6] + connect \XX2_BX_B { \opcode_in [1] \opcode_in [15:11] } + connect \XX2_B \opcode_in [15:11] + connect \XX2_BX \opcode_in [1] + connect \XX2_BF \opcode_in [25:23] + connect \D_UI \opcode_in [15:0] + connect \D_TO \opcode_in [25:21] + connect \D_SI \opcode_in [15:0] + connect \D_RT \opcode_in [25:21] + connect \D_RS \opcode_in [25:21] + connect \D_RA \opcode_in [20:16] + connect \D_L \opcode_in [21] + connect \D_FRT \opcode_in [25:21] + connect \D_FRS \opcode_in [25:21] + connect \D_D \opcode_in [15:0] + connect \D_BF \opcode_in [25:23] + connect \A_XO \opcode_in [5:1] + connect \A_RT \opcode_in [25:21] + connect \A_Rc \opcode_in [0] + connect \A_RB \opcode_in [15:11] + connect \A_RA \opcode_in [20:16] + connect \A_FRT \opcode_in [25:21] + connect \A_FRC \opcode_in [10:6] + connect \A_FRB \opcode_in [15:11] + connect \A_FRA \opcode_in [20:16] + connect \A_BC \opcode_in [10:6] + connect \XL_XO \opcode_in [10:1] + connect \XL_S \opcode_in [11] + connect \XL_OC \opcode_in [25:11] + connect \XL_LK \opcode_in [0] + connect \XL_BT \opcode_in [25:21] + connect \XL_BO_1 \opcode_in [25:21] + connect \XL_BO \opcode_in [25:21] + connect \XL_BI \opcode_in [20:16] + connect \XL_BH \opcode_in [12:11] + connect \XL_BFA \opcode_in [20:18] + connect \XL_BF \opcode_in [25:23] + connect \XL_BB \opcode_in [15:11] + connect \XL_BA \opcode_in [20:16] + connect \XX4_XO \opcode_in [5:4] + connect \XX4_TX_T { \opcode_in [0] \opcode_in [25:21] } + connect \XX4_T \opcode_in [25:21] + connect \XX4_TX \opcode_in [0] + connect \XX4_CX_C { \opcode_in [3] \opcode_in [10:6] } + connect \XX4_C \opcode_in [10:6] + connect \XX4_CX \opcode_in [3] + connect \XX4_BX_B { \opcode_in [1] \opcode_in [15:11] } + connect \XX4_B \opcode_in [15:11] + connect \XX4_BX \opcode_in [1] + connect \XX4_AX_A { \opcode_in [2] \opcode_in [20:16] } + connect \XX4_A \opcode_in [20:16] + connect \XX4_AX \opcode_in [2] + connect \XX3_XO_2 \opcode_in [9:1] + connect \XX3_XO_1 \opcode_in [10:3] + connect \XX3_XO \opcode_in [10:7] + connect \XX3_TX_T { \opcode_in [0] \opcode_in [25:21] } + connect \XX3_T \opcode_in [25:21] + connect \XX3_TX \opcode_in [0] + connect \XX3_SHW \opcode_in [9:8] + connect \XX3_Rc \opcode_in [10] + connect \XX3_DM \opcode_in [9:8] + connect \XX3_BX_B { \opcode_in [1] \opcode_in [15:11] } + connect \XX3_B \opcode_in [15:11] + connect \XX3_BX \opcode_in [1] + connect \XX3_BF \opcode_in [25:23] + connect \XX3_AX_A { \opcode_in [2] \opcode_in [20:16] } + connect \XX3_A \opcode_in [20:16] + connect \XX3_AX \opcode_in [2] + connect \I_LK \opcode_in [0] + connect \I_LI \opcode_in [25:2] + connect \I_AA \opcode_in [1] + connect \B_LK \opcode_in [0] + connect \B_BO \opcode_in [25:21] + connect \B_BI \opcode_in [20:16] + connect \B_BD \opcode_in [15:2] + connect \B_AA \opcode_in [1] + connect \X_XO_1 \opcode_in [8:1] + connect \X_XO \opcode_in [10:1] + connect \X_WC \opcode_in [22:21] + connect \X_W \opcode_in [16] + connect \X_VRT \opcode_in [25:21] + connect \X_VRS \opcode_in [25:21] + connect \X_UIM \opcode_in [20:16] + connect \X_U \opcode_in [15:12] + connect \X_TX_T { \opcode_in [0] \opcode_in [25:21] } + connect \X_TX \opcode_in [0] + connect \X_TO \opcode_in [25:21] + connect \X_TH \opcode_in [25:21] + connect \X_TBR \opcode_in [20:11] + connect \X_T \opcode_in [25:21] + connect \X_SX_S { \opcode_in [0] \opcode_in [25:21] } + connect \X_SX \opcode_in [0] + connect \X_SR \opcode_in [19:16] + connect \X_SP \opcode_in [20:19] + connect \X_SI \opcode_in [15:11] + connect \X_SH \opcode_in [15:11] + connect \X_S \opcode_in [25:21] + connect \X_RTp \opcode_in [25:21] + connect \X_RT \opcode_in [25:21] + connect \X_RSp \opcode_in [25:21] + connect \X_RS \opcode_in [25:21] + connect \X_RO \opcode_in [0] + connect \X_RM \opcode_in [12:11] + connect \X_RIC \opcode_in [19:18] + connect \X_Rc \opcode_in [0] + connect \X_RB \opcode_in [15:11] + connect \X_RA \opcode_in [20:16] + connect \X_R_1 \opcode_in [16] + connect \X_R \opcode_in [21] + connect \X_PRS \opcode_in [17] + connect \X_NB \opcode_in [15:11] + connect \X_MO \opcode_in [25:21] + connect \X_L3 \opcode_in [17:16] + connect \X_L1 \opcode_in [16] + connect \X_L \opcode_in [21] + connect \X_L2 \opcode_in [22:21] + connect \X_IMM8 \opcode_in [18:11] + connect \X_IH \opcode_in [23:21] + connect \X_FRTp \opcode_in [25:21] + connect \X_FRT \opcode_in [25:21] + connect \X_FRSp \opcode_in [25:21] + connect \X_FRS \opcode_in [25:21] + connect \X_FRBp \opcode_in [15:11] + connect \X_FRB \opcode_in [15:11] + connect \X_FRAp \opcode_in [20:16] + connect \X_FRA \opcode_in [20:16] + connect \X_FC \opcode_in [15:11] + connect \X_EX \opcode_in [0] + connect \X_EO_1 \opcode_in [20:16] + connect \X_EO \opcode_in [20:19] + connect \X_E_1 \opcode_in [19:16] + connect \X_E \opcode_in [15] + connect \X_DRM \opcode_in [13:11] + connect \X_DCMX \opcode_in [22:16] + connect \X_CT \opcode_in [24:21] + connect \X_BO \opcode_in [25:21] + connect \X_BFA \opcode_in [20:18] + connect \X_BF \opcode_in [25:23] + connect \X_A \opcode_in [25] + connect \SHIFT_ROT_SPR \opcode_in [20:11] + connect \SHIFT_ROT_MB \opcode_in [10:6] + connect \SHIFT_ROT_ME \opcode_in [5:1] + connect \SHIFT_ROT_SH \opcode_in [15:11] + connect \SHIFT_ROT_BC \opcode_in [10:6] + connect \SHIFT_ROT_TO \opcode_in [25:21] + connect \SHIFT_ROT_DS \opcode_in [15:2] + connect \SHIFT_ROT_D \opcode_in [15:0] + connect \SHIFT_ROT_BH \opcode_in [12:11] + connect \SHIFT_ROT_BI \opcode_in [20:16] + connect \SHIFT_ROT_BO \opcode_in [25:21] + connect \SHIFT_ROT_FXM \opcode_in [19:12] + connect \SHIFT_ROT_BT \opcode_in [25:21] + connect \SHIFT_ROT_BA \opcode_in [20:16] + connect \SHIFT_ROT_BB \opcode_in [15:11] + connect \SHIFT_ROT_CR \opcode_in [10:1] + connect \SHIFT_ROT_BF \opcode_in [25:23] + connect \SHIFT_ROT_BD \opcode_in [15:2] + connect \SHIFT_ROT_OE \opcode_in [10] + connect \SHIFT_ROT_Rc \opcode_in [0] + connect \SHIFT_ROT_AA \opcode_in [1] + connect \SHIFT_ROT_LK \opcode_in [0] + connect \SHIFT_ROT_LI \opcode_in [25:2] + connect \SHIFT_ROT_ME32 \opcode_in [5:1] + connect \SHIFT_ROT_MB32 \opcode_in [10:6] + connect \SHIFT_ROT_sh { \opcode_in [1] \opcode_in [15:11] } + connect \SHIFT_ROT_SH32 \opcode_in [15:11] + connect \SHIFT_ROT_L \opcode_in [21] + connect \SHIFT_ROT_UI \opcode_in [15:0] + connect \SHIFT_ROT_SI \opcode_in [15:0] + connect \SHIFT_ROT_RB \opcode_in [15:11] + connect \SHIFT_ROT_RA \opcode_in [20:16] + connect \SHIFT_ROT_RT \opcode_in [25:21] + connect \SHIFT_ROT_RS \opcode_in [25:21] + connect \opcode_in \$1 + connect \SHIFT_ROT_dec31_opcode_in \opcode_in + connect \SHIFT_ROT_dec30_opcode_in \opcode_in + connect \opcode_switch \opcode_in [31:26] +end +attribute \src "issuer_ls180.v:62583.1-65052.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.dec_LDST.dec" +attribute \generator "nMigen" +module \dec$193 + attribute \src "issuer_ls180.v:64141.3-64198.6" + wire $0\LDST_br[0:0] + attribute \src "issuer_ls180.v:64605.3-64662.6" + wire width 3 $0\LDST_cr_in[2:0] + attribute \src "issuer_ls180.v:64663.3-64720.6" + wire width 3 $0\LDST_cr_out[2:0] + attribute \src "issuer_ls180.v:64373.3-64430.6" + wire width 12 $0\LDST_function_unit[11:0] + attribute \src "issuer_ls180.v:64489.3-64546.6" + wire width 3 $0\LDST_in1_sel[2:0] + attribute \src "issuer_ls180.v:64547.3-64604.6" + wire width 4 $0\LDST_in2_sel[3:0] + attribute \src "issuer_ls180.v:64431.3-64488.6" + wire width 7 $0\LDST_internal_op[6:0] + attribute \src "issuer_ls180.v:64257.3-64314.6" + wire $0\LDST_is_32b[0:0] + attribute \src "issuer_ls180.v:63967.3-64024.6" + wire width 4 $0\LDST_ldst_len[3:0] + attribute \src "issuer_ls180.v:64083.3-64140.6" + wire width 2 $0\LDST_rc_sel[1:0] + attribute \src "issuer_ls180.v:64315.3-64372.6" + wire $0\LDST_sgn[0:0] + attribute \src "issuer_ls180.v:64199.3-64256.6" + wire $0\LDST_sgn_ext[0:0] + attribute \src "issuer_ls180.v:64025.3-64082.6" + wire width 2 $0\LDST_upd[1:0] + attribute \src "issuer_ls180.v:62584.7-62584.20" + wire $0\initial[0:0] + attribute \src "issuer_ls180.v:64141.3-64198.6" + wire $1\LDST_br[0:0] + attribute \src "issuer_ls180.v:64605.3-64662.6" + wire width 3 $1\LDST_cr_in[2:0] + attribute \src "issuer_ls180.v:64663.3-64720.6" + wire width 3 $1\LDST_cr_out[2:0] + attribute \src "issuer_ls180.v:64373.3-64430.6" + wire width 12 $1\LDST_function_unit[11:0] + attribute \src "issuer_ls180.v:64489.3-64546.6" + wire width 3 $1\LDST_in1_sel[2:0] + attribute \src "issuer_ls180.v:64547.3-64604.6" + wire width 4 $1\LDST_in2_sel[3:0] + attribute \src "issuer_ls180.v:64431.3-64488.6" + wire width 7 $1\LDST_internal_op[6:0] + attribute \src "issuer_ls180.v:64257.3-64314.6" + wire $1\LDST_is_32b[0:0] + attribute \src "issuer_ls180.v:63967.3-64024.6" + wire width 4 $1\LDST_ldst_len[3:0] + attribute \src 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\src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 \LDST_MB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 \LDST_MB32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 \LDST_ME + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 \LDST_ME32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire output 23 \LDST_OE + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 output 16 \LDST_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 \LDST_RB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 \LDST_RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 \LDST_RT + attribute \src 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\enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 \LDST_dec31_LDST_dec31_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 \LDST_dec31_LDST_dec31_cr_out + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 12 \LDST_dec31_LDST_dec31_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 \LDST_dec31_LDST_dec31_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute 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wire width 4 \LDST_dec62_LDST_dec62_in2_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute 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attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 12 output 7 \LDST_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 8 \LDST_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" 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\enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 7 output 6 \LDST_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 11 \LDST_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 output 10 \LDST_ldst_len + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 3 \LDST_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 12 \LDST_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 14 \LDST_sgn_ext + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 6 output 20 \LDST_sh + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 15 \LDST_upd + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \MDS_IB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \MDS_IS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \MDS_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \MDS_RB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \MDS_RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \MDS_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 4 \MDS_XBI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 4 \MDS_XBI_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 4 \MDS_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \MDS_mb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \MDS_me + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \MD_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \MD_RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \MD_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 3 \MD_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \MD_mb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \MD_me + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \MD_sh + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \M_MB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \M_ME + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \M_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \M_RB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \M_RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \M_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \M_SH + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 7 \SC_LEV + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \SC_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 2 \SC_XO_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \TX_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \TX_UI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 4 \TX_XBI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \TX_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \VA_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \VA_RB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \VA_RC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \VA_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 4 \VA_SHB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \VA_VRA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \VA_VRB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \VA_VRC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \VA_VRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \VA_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \VC_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \VC_VRA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \VC_VRB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \VC_VRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 10 \VC_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \VX_EO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \VX_PS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \VX_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \VX_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \VX_SIM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \VX_UIM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 4 \VX_UIM_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 3 \VX_UIM_2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 2 \VX_UIM_3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \VX_VRA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \VX_VRB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \VX_VRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 10 \VX_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 11 \VX_XO_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 8 \XFL_FLM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XFL_FRB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \XFL_L + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \XFL_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \XFL_W + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 10 \XFL_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 10 \XFX_BHRBE + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XFX_DUI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 10 \XFX_DUIS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 8 \XFX_FXM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XFX_RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XFX_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 10 \XFX_SPR + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 10 \XFX_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XL_BA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XL_BB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 3 \XL_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 3 \XL_BFA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 2 \XL_BH + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XL_BI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XL_BO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XL_BO_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 output 34 \XL_BT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \XL_LK + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 15 \XL_OC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \XL_S + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 10 \XL_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \XO_OE + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XO_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XO_RB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XO_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \XO_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 9 \XO_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XS_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XS_RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \XS_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 9 \XS_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \XS_sh + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XX2_B + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 3 \XX2_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \XX2_BX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \XX2_BX_B + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 7 \XX2_DCMX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XX2_EO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XX2_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XX2_T + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \XX2_TX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \XX2_TX_T + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 4 \XX2_UIM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 2 \XX2_UIM_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 7 \XX2_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 9 \XX2_XO_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \XX2_dc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 7 \XX2_dc_dm_dx + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \XX2_dm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XX2_dx + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XX3_A + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \XX3_AX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \XX3_AX_A + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XX3_B + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 3 \XX3_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \XX3_BX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \XX3_BX_B + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 2 \XX3_DM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \XX3_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 2 \XX3_SHW + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XX3_T + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \XX3_TX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \XX3_TX_T + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 4 \XX3_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 8 \XX3_XO_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 9 \XX3_XO_2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XX4_A + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \XX4_AX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \XX4_AX_A + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XX4_B + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \XX4_BX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \XX4_BX_B + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XX4_C + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \XX4_CX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \XX4_CX_C + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XX4_T + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \XX4_TX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \XX4_TX_T + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 2 \XX4_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \X_A + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 3 output 32 \X_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 3 output 33 \X_BFA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_BO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 4 \X_CT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 7 \X_DCMX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 3 \X_DRM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \X_E + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 2 \X_EO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_EO_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \X_EX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 4 \X_E_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_FC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_FRA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_FRAp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_FRB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_FRBp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_FRS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_FRSp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_FRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_FRTp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 3 \X_IH + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 8 \X_IMM8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \X_L + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \X_L1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 2 \X_L2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 2 \X_L3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_MO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_NB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \X_PRS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \X_R + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_RB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 2 \X_RIC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 2 \X_RM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \X_RO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_RSp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_RTp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \X_R_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \X_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_S + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_SH + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_SI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 2 \X_SP + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 4 \X_SR + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \X_SX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \X_SX_S + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_T + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 10 \X_TBR + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_TH + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_TO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \X_TX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \X_TX_T + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 4 \X_U + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_UIM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_VRS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_VRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \X_W + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 2 \X_WC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 10 \X_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 8 \X_XO_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 3 \Z22_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \Z22_DCM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \Z22_DGM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \Z22_FRA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \Z22_FRAp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \Z22_FRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \Z22_FRTp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \Z22_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \Z22_SH + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 9 \Z22_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \Z23_FRA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \Z23_FRAp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \Z23_FRB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \Z23_FRBp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \Z23_FRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \Z23_FRTp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \Z23_R + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 2 \Z23_RMC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \Z23_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \Z23_TE + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 8 \Z23_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \all_OPCD + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \all_PO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + wire input 1 \bigendian + attribute \src "issuer_ls180.v:62584.7-62584.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + wire width 32 output 2 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:320" + wire width 6 \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:442" + wire width 32 input 35 \raw_opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:478" + cell $mux $ternary$issuer_ls180.v:63918$3457 + parameter \WIDTH 32 + connect \A \raw_opcode_in + connect \B { \raw_opcode_in [7:0] \raw_opcode_in [15:8] \raw_opcode_in [23:16] \raw_opcode_in [31:24] } + connect \S \bigendian + connect \Y $ternary$issuer_ls180.v:63918$3457_Y + end + attribute \module_not_derived 1 + attribute \src "issuer_ls180.v:63919.14-63934.4" + cell \LDST_dec31 \LDST_dec31 + connect \LDST_dec31_br \LDST_dec31_LDST_dec31_br + connect \LDST_dec31_cr_in \LDST_dec31_LDST_dec31_cr_in + connect \LDST_dec31_cr_out \LDST_dec31_LDST_dec31_cr_out + connect \LDST_dec31_function_unit \LDST_dec31_LDST_dec31_function_unit + connect \LDST_dec31_in1_sel \LDST_dec31_LDST_dec31_in1_sel + connect \LDST_dec31_in2_sel \LDST_dec31_LDST_dec31_in2_sel + connect \LDST_dec31_internal_op \LDST_dec31_LDST_dec31_internal_op + connect \LDST_dec31_is_32b \LDST_dec31_LDST_dec31_is_32b + connect \LDST_dec31_ldst_len \LDST_dec31_LDST_dec31_ldst_len + connect \LDST_dec31_rc_sel \LDST_dec31_LDST_dec31_rc_sel + connect \LDST_dec31_sgn \LDST_dec31_LDST_dec31_sgn + connect \LDST_dec31_sgn_ext \LDST_dec31_LDST_dec31_sgn_ext + connect \LDST_dec31_upd \LDST_dec31_LDST_dec31_upd + connect \opcode_in \LDST_dec31_opcode_in + end + attribute \module_not_derived 1 + attribute \src "issuer_ls180.v:63935.14-63950.4" + cell \LDST_dec58 \LDST_dec58 + connect \LDST_dec58_br \LDST_dec58_LDST_dec58_br + connect \LDST_dec58_cr_in \LDST_dec58_LDST_dec58_cr_in + connect \LDST_dec58_cr_out \LDST_dec58_LDST_dec58_cr_out + connect \LDST_dec58_function_unit \LDST_dec58_LDST_dec58_function_unit + connect \LDST_dec58_in1_sel \LDST_dec58_LDST_dec58_in1_sel + connect \LDST_dec58_in2_sel \LDST_dec58_LDST_dec58_in2_sel + connect \LDST_dec58_internal_op \LDST_dec58_LDST_dec58_internal_op + connect \LDST_dec58_is_32b \LDST_dec58_LDST_dec58_is_32b + connect \LDST_dec58_ldst_len \LDST_dec58_LDST_dec58_ldst_len + connect \LDST_dec58_rc_sel \LDST_dec58_LDST_dec58_rc_sel + connect \LDST_dec58_sgn \LDST_dec58_LDST_dec58_sgn + connect \LDST_dec58_sgn_ext \LDST_dec58_LDST_dec58_sgn_ext + connect \LDST_dec58_upd \LDST_dec58_LDST_dec58_upd + connect \opcode_in \LDST_dec58_opcode_in + end + attribute \module_not_derived 1 + attribute \src "issuer_ls180.v:63951.14-63966.4" + cell \LDST_dec62 \LDST_dec62 + connect \LDST_dec62_br \LDST_dec62_LDST_dec62_br + connect \LDST_dec62_cr_in \LDST_dec62_LDST_dec62_cr_in + connect \LDST_dec62_cr_out \LDST_dec62_LDST_dec62_cr_out + connect \LDST_dec62_function_unit \LDST_dec62_LDST_dec62_function_unit + connect \LDST_dec62_in1_sel \LDST_dec62_LDST_dec62_in1_sel + connect \LDST_dec62_in2_sel \LDST_dec62_LDST_dec62_in2_sel + connect \LDST_dec62_internal_op \LDST_dec62_LDST_dec62_internal_op + connect \LDST_dec62_is_32b \LDST_dec62_LDST_dec62_is_32b + connect \LDST_dec62_ldst_len \LDST_dec62_LDST_dec62_ldst_len + connect \LDST_dec62_rc_sel \LDST_dec62_LDST_dec62_rc_sel + connect \LDST_dec62_sgn \LDST_dec62_LDST_dec62_sgn + connect \LDST_dec62_sgn_ext \LDST_dec62_LDST_dec62_sgn_ext + connect \LDST_dec62_upd \LDST_dec62_LDST_dec62_upd + connect \opcode_in \LDST_dec62_opcode_in + end + attribute \src "issuer_ls180.v:62584.7-62584.20" + process $proc$issuer_ls180.v:62584$3471 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "issuer_ls180.v:63967.3-64024.6" + process $proc$issuer_ls180.v:63967$3458 + assign { } { } + assign { } { } + assign $0\LDST_ldst_len[3:0] $1\LDST_ldst_len[3:0] + attribute \src "issuer_ls180.v:63968.5-63968.29" + switch \initial + attribute \src "issuer_ls180.v:63968.9-63968.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\LDST_ldst_len[3:0] \LDST_dec31_LDST_dec31_ldst_len + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'111010 + assign { } { } + assign $1\LDST_ldst_len[3:0] \LDST_dec58_LDST_dec58_ldst_len + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'111110 + assign { } { } + assign $1\LDST_ldst_len[3:0] \LDST_dec62_LDST_dec62_ldst_len + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'100010 + assign { } { } + assign $1\LDST_ldst_len[3:0] 4'0001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'100011 + assign { } { } + assign $1\LDST_ldst_len[3:0] 4'0001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'101010 + assign { } { } + assign $1\LDST_ldst_len[3:0] 4'0010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'101011 + assign { } { } + assign $1\LDST_ldst_len[3:0] 4'0010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'101000 + assign { } { } + assign $1\LDST_ldst_len[3:0] 4'0010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'101001 + assign { } { } + assign $1\LDST_ldst_len[3:0] 4'0010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'100000 + assign { } { } + assign $1\LDST_ldst_len[3:0] 4'0100 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'100001 + assign { } { } + assign $1\LDST_ldst_len[3:0] 4'0100 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'100110 + assign { } { } + assign $1\LDST_ldst_len[3:0] 4'0001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'100111 + assign { } { } + assign $1\LDST_ldst_len[3:0] 4'0001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'101100 + assign { } { } + assign $1\LDST_ldst_len[3:0] 4'0010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'101101 + assign { } { } + assign $1\LDST_ldst_len[3:0] 4'0010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'100100 + assign { } { } + assign $1\LDST_ldst_len[3:0] 4'0100 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'100101 + assign { } { } + assign $1\LDST_ldst_len[3:0] 4'0100 + case + assign $1\LDST_ldst_len[3:0] 4'0000 + end + sync always + update \LDST_ldst_len $0\LDST_ldst_len[3:0] + end + attribute \src "issuer_ls180.v:64025.3-64082.6" + process $proc$issuer_ls180.v:64025$3459 + assign { } { } + assign { } { } + assign $0\LDST_upd[1:0] $1\LDST_upd[1:0] + attribute \src "issuer_ls180.v:64026.5-64026.29" + switch \initial + attribute \src "issuer_ls180.v:64026.9-64026.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\LDST_upd[1:0] \LDST_dec31_LDST_dec31_upd + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'111010 + assign { } { } + assign $1\LDST_upd[1:0] \LDST_dec58_LDST_dec58_upd + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'111110 + assign { } { } + assign $1\LDST_upd[1:0] \LDST_dec62_LDST_dec62_upd + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'100010 + assign { } { } + assign $1\LDST_upd[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'100011 + assign { } { } + assign $1\LDST_upd[1:0] 2'01 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'101010 + assign { } { } + assign $1\LDST_upd[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'101011 + assign { } { } + assign $1\LDST_upd[1:0] 2'01 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'101000 + assign { } { } + assign $1\LDST_upd[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'101001 + assign { } { } + assign $1\LDST_upd[1:0] 2'01 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'100000 + assign { } { } + assign $1\LDST_upd[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'100001 + assign { } { } + assign $1\LDST_upd[1:0] 2'01 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'100110 + assign { } { } + assign $1\LDST_upd[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'100111 + assign { } { } + assign $1\LDST_upd[1:0] 2'01 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'101100 + assign { } { } + assign $1\LDST_upd[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'101101 + assign { } { } + assign $1\LDST_upd[1:0] 2'01 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'100100 + assign { } { } + assign $1\LDST_upd[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'100101 + assign { } { } + assign $1\LDST_upd[1:0] 2'01 + case + assign $1\LDST_upd[1:0] 2'00 + end + sync always + update \LDST_upd $0\LDST_upd[1:0] + end + attribute \src "issuer_ls180.v:64083.3-64140.6" + process $proc$issuer_ls180.v:64083$3460 + assign { } { } + assign { } { } + assign $0\LDST_rc_sel[1:0] $1\LDST_rc_sel[1:0] + attribute \src "issuer_ls180.v:64084.5-64084.29" + switch \initial + attribute \src "issuer_ls180.v:64084.9-64084.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\LDST_rc_sel[1:0] \LDST_dec31_LDST_dec31_rc_sel + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'111010 + assign { } { } + assign $1\LDST_rc_sel[1:0] \LDST_dec58_LDST_dec58_rc_sel + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'111110 + assign { } { } + assign $1\LDST_rc_sel[1:0] \LDST_dec62_LDST_dec62_rc_sel + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'100010 + assign { } { } + assign $1\LDST_rc_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'100011 + assign { } { } + assign $1\LDST_rc_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'101010 + assign { } { } + assign $1\LDST_rc_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'101011 + assign { } { } + assign $1\LDST_rc_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'101000 + assign { } { } + assign $1\LDST_rc_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'101001 + assign { } { } + assign $1\LDST_rc_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'100000 + assign { } { } + assign $1\LDST_rc_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'100001 + assign { } { } + assign $1\LDST_rc_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'100110 + assign { } { } + assign $1\LDST_rc_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'100111 + assign { } { } + assign $1\LDST_rc_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'101100 + assign { } { } + assign $1\LDST_rc_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'101101 + assign { } { } + assign $1\LDST_rc_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'100100 + assign { } { } + assign $1\LDST_rc_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'100101 + assign { } { } + assign $1\LDST_rc_sel[1:0] 2'00 + case + assign $1\LDST_rc_sel[1:0] 2'00 + end + sync always + update \LDST_rc_sel $0\LDST_rc_sel[1:0] + end + attribute \src "issuer_ls180.v:64141.3-64198.6" + process $proc$issuer_ls180.v:64141$3461 + assign { } { } + assign { } { } + assign $0\LDST_br[0:0] $1\LDST_br[0:0] + attribute \src "issuer_ls180.v:64142.5-64142.29" + switch \initial + attribute \src "issuer_ls180.v:64142.9-64142.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\LDST_br[0:0] \LDST_dec31_LDST_dec31_br + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'111010 + assign { } { } + assign $1\LDST_br[0:0] \LDST_dec58_LDST_dec58_br + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'111110 + assign { } { } + assign $1\LDST_br[0:0] \LDST_dec62_LDST_dec62_br + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'100010 + assign { } { } + assign $1\LDST_br[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'100011 + assign { } { } + assign $1\LDST_br[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'101010 + assign { } { } + assign $1\LDST_br[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'101011 + assign { } { } + assign $1\LDST_br[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'101000 + assign { } { } + assign $1\LDST_br[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'101001 + assign { } { } + assign $1\LDST_br[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'100000 + assign { } { } + assign $1\LDST_br[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'100001 + assign { } { } + assign $1\LDST_br[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'100110 + assign { } { } + assign $1\LDST_br[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'100111 + assign { } { } + assign $1\LDST_br[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'101100 + assign { } { } + assign $1\LDST_br[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'101101 + assign { } { } + assign $1\LDST_br[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'100100 + assign { } { } + assign $1\LDST_br[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'100101 + assign { } { } + assign $1\LDST_br[0:0] 1'0 + case + assign $1\LDST_br[0:0] 1'0 + end + sync always + update \LDST_br $0\LDST_br[0:0] + end + attribute \src "issuer_ls180.v:64199.3-64256.6" + process $proc$issuer_ls180.v:64199$3462 + assign { } { } + assign { } { } + assign $0\LDST_sgn_ext[0:0] $1\LDST_sgn_ext[0:0] + attribute \src "issuer_ls180.v:64200.5-64200.29" + switch \initial + attribute \src "issuer_ls180.v:64200.9-64200.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\LDST_sgn_ext[0:0] \LDST_dec31_LDST_dec31_sgn_ext + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'111010 + assign { } { } + assign $1\LDST_sgn_ext[0:0] \LDST_dec58_LDST_dec58_sgn_ext + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'111110 + assign { } { } + assign $1\LDST_sgn_ext[0:0] \LDST_dec62_LDST_dec62_sgn_ext + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'100010 + assign { } { } + assign $1\LDST_sgn_ext[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'100011 + assign { } { } + assign $1\LDST_sgn_ext[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'101010 + assign { } { } + assign $1\LDST_sgn_ext[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'101011 + assign { } { } + assign $1\LDST_sgn_ext[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'101000 + assign { } { } + assign $1\LDST_sgn_ext[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'101001 + assign { } { } + assign $1\LDST_sgn_ext[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'100000 + assign { } { } + assign $1\LDST_sgn_ext[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'100001 + assign { } { } + assign $1\LDST_sgn_ext[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'100110 + assign { } { } + assign $1\LDST_sgn_ext[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'100111 + assign { } { } + assign $1\LDST_sgn_ext[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'101100 + assign { } { } + assign $1\LDST_sgn_ext[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'101101 + assign { } { } + assign $1\LDST_sgn_ext[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'100100 + assign { } { } + assign $1\LDST_sgn_ext[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'100101 + assign { } { } + assign $1\LDST_sgn_ext[0:0] 1'0 + case + assign $1\LDST_sgn_ext[0:0] 1'0 + end + sync always + update \LDST_sgn_ext $0\LDST_sgn_ext[0:0] + end + attribute \src "issuer_ls180.v:64257.3-64314.6" + process $proc$issuer_ls180.v:64257$3463 + assign { } { } + assign { } { } + assign $0\LDST_is_32b[0:0] $1\LDST_is_32b[0:0] + attribute \src "issuer_ls180.v:64258.5-64258.29" + switch \initial + attribute \src "issuer_ls180.v:64258.9-64258.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\LDST_is_32b[0:0] \LDST_dec31_LDST_dec31_is_32b + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'111010 + assign { } { } + assign $1\LDST_is_32b[0:0] \LDST_dec58_LDST_dec58_is_32b + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'111110 + assign { } { } + assign $1\LDST_is_32b[0:0] \LDST_dec62_LDST_dec62_is_32b + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'100010 + assign { } { } + assign $1\LDST_is_32b[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'100011 + assign { } { } + assign $1\LDST_is_32b[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'101010 + assign { } { } + assign $1\LDST_is_32b[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'101011 + assign { } { } + assign $1\LDST_is_32b[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'101000 + assign { } { } + assign $1\LDST_is_32b[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'101001 + assign { } { } + assign $1\LDST_is_32b[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'100000 + assign { } { } + assign $1\LDST_is_32b[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'100001 + assign { } { } + assign $1\LDST_is_32b[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'100110 + assign { } { } + assign $1\LDST_is_32b[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'100111 + assign { } { } + assign $1\LDST_is_32b[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'101100 + assign { } { } + assign $1\LDST_is_32b[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'101101 + assign { } { } + assign $1\LDST_is_32b[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'100100 + assign { } { } + assign $1\LDST_is_32b[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'100101 + assign { } { } + assign $1\LDST_is_32b[0:0] 1'0 + case + assign $1\LDST_is_32b[0:0] 1'0 + end + sync always + update \LDST_is_32b $0\LDST_is_32b[0:0] + end + attribute \src "issuer_ls180.v:64315.3-64372.6" + process $proc$issuer_ls180.v:64315$3464 + assign { } { } + assign { } { } + assign $0\LDST_sgn[0:0] $1\LDST_sgn[0:0] + attribute \src "issuer_ls180.v:64316.5-64316.29" + switch \initial + attribute \src "issuer_ls180.v:64316.9-64316.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\LDST_sgn[0:0] \LDST_dec31_LDST_dec31_sgn + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'111010 + assign { } { } + assign $1\LDST_sgn[0:0] \LDST_dec58_LDST_dec58_sgn + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'111110 + assign { } { } + assign $1\LDST_sgn[0:0] \LDST_dec62_LDST_dec62_sgn + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'100010 + assign { } { } + assign $1\LDST_sgn[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'100011 + assign { } { } + assign $1\LDST_sgn[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'101010 + assign { } { } + assign $1\LDST_sgn[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'101011 + assign { } { } + assign $1\LDST_sgn[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'101000 + assign { } { } + assign $1\LDST_sgn[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'101001 + assign { } { } + assign $1\LDST_sgn[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'100000 + assign { } { } + assign $1\LDST_sgn[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'100001 + assign { } { } + assign $1\LDST_sgn[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'100110 + assign { } { } + assign $1\LDST_sgn[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'100111 + assign { } { } + assign $1\LDST_sgn[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'101100 + assign { } { } + assign $1\LDST_sgn[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'101101 + assign { } { } + assign $1\LDST_sgn[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'100100 + assign { } { } + assign $1\LDST_sgn[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'100101 + assign { } { } + assign $1\LDST_sgn[0:0] 1'0 + case + assign $1\LDST_sgn[0:0] 1'0 + end + sync always + update \LDST_sgn $0\LDST_sgn[0:0] + end + attribute \src "issuer_ls180.v:64373.3-64430.6" + process $proc$issuer_ls180.v:64373$3465 + assign { } { } + assign { } { } + assign $0\LDST_function_unit[11:0] $1\LDST_function_unit[11:0] + attribute \src "issuer_ls180.v:64374.5-64374.29" + switch \initial + attribute \src "issuer_ls180.v:64374.9-64374.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\LDST_function_unit[11:0] \LDST_dec31_LDST_dec31_function_unit + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'111010 + assign { } { } + assign $1\LDST_function_unit[11:0] \LDST_dec58_LDST_dec58_function_unit + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'111110 + assign { } { } + assign $1\LDST_function_unit[11:0] \LDST_dec62_LDST_dec62_function_unit + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'100010 + assign { } { } + assign $1\LDST_function_unit[11:0] 12'000000000100 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'100011 + assign { } { } + assign $1\LDST_function_unit[11:0] 12'000000000100 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'101010 + assign { } { } + assign $1\LDST_function_unit[11:0] 12'000000000100 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'101011 + assign { } { } + assign $1\LDST_function_unit[11:0] 12'000000000100 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'101000 + assign { } { } + assign $1\LDST_function_unit[11:0] 12'000000000100 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'101001 + assign { } { } + assign $1\LDST_function_unit[11:0] 12'000000000100 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'100000 + assign { } { } + assign $1\LDST_function_unit[11:0] 12'000000000100 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'100001 + assign { } { } + assign $1\LDST_function_unit[11:0] 12'000000000100 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'100110 + assign { } { } + assign $1\LDST_function_unit[11:0] 12'000000000100 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'100111 + assign { } { } + assign $1\LDST_function_unit[11:0] 12'000000000100 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'101100 + assign { } { } + assign $1\LDST_function_unit[11:0] 12'000000000100 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'101101 + assign { } { } + assign $1\LDST_function_unit[11:0] 12'000000000100 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'100100 + assign { } { } + assign $1\LDST_function_unit[11:0] 12'000000000100 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'100101 + assign { } { } + assign $1\LDST_function_unit[11:0] 12'000000000100 + case + assign $1\LDST_function_unit[11:0] 12'000000000000 + end + sync always + update \LDST_function_unit $0\LDST_function_unit[11:0] + end + attribute \src "issuer_ls180.v:64431.3-64488.6" + process $proc$issuer_ls180.v:64431$3466 + assign { } { } + assign { } { } + assign $0\LDST_internal_op[6:0] $1\LDST_internal_op[6:0] + attribute \src "issuer_ls180.v:64432.5-64432.29" + switch \initial + attribute \src "issuer_ls180.v:64432.9-64432.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\LDST_internal_op[6:0] \LDST_dec31_LDST_dec31_internal_op + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'111010 + assign { } { } + assign $1\LDST_internal_op[6:0] \LDST_dec58_LDST_dec58_internal_op + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'111110 + assign { } { } + assign $1\LDST_internal_op[6:0] \LDST_dec62_LDST_dec62_internal_op + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'100010 + assign { } { } + assign $1\LDST_internal_op[6:0] 7'0100101 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'100011 + assign { } { } + assign $1\LDST_internal_op[6:0] 7'0100101 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'101010 + assign { } { } + assign $1\LDST_internal_op[6:0] 7'0100101 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'101011 + assign { } { } + assign $1\LDST_internal_op[6:0] 7'0100101 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'101000 + assign { } { } + assign $1\LDST_internal_op[6:0] 7'0100101 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'101001 + assign { } { } + assign $1\LDST_internal_op[6:0] 7'0100101 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'100000 + assign { } { } + assign $1\LDST_internal_op[6:0] 7'0100101 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'100001 + assign { } { } + assign $1\LDST_internal_op[6:0] 7'0100101 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'100110 + assign { } { } + assign $1\LDST_internal_op[6:0] 7'0100110 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'100111 + assign { } { } + assign $1\LDST_internal_op[6:0] 7'0100110 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'101100 + assign { } { } + assign $1\LDST_internal_op[6:0] 7'0100110 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'101101 + assign { } { } + assign $1\LDST_internal_op[6:0] 7'0100110 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'100100 + assign { } { } + assign $1\LDST_internal_op[6:0] 7'0100110 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'100101 + assign { } { } + assign $1\LDST_internal_op[6:0] 7'0100110 + case + assign $1\LDST_internal_op[6:0] 7'0000000 + end + sync always + update \LDST_internal_op $0\LDST_internal_op[6:0] + end + attribute \src "issuer_ls180.v:64489.3-64546.6" + process $proc$issuer_ls180.v:64489$3467 + assign { } { } + assign { } { } + assign $0\LDST_in1_sel[2:0] $1\LDST_in1_sel[2:0] + attribute \src "issuer_ls180.v:64490.5-64490.29" + switch \initial + attribute \src "issuer_ls180.v:64490.9-64490.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\LDST_in1_sel[2:0] \LDST_dec31_LDST_dec31_in1_sel + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'111010 + assign { } { } + assign $1\LDST_in1_sel[2:0] \LDST_dec58_LDST_dec58_in1_sel + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'111110 + assign { } { } + assign $1\LDST_in1_sel[2:0] \LDST_dec62_LDST_dec62_in1_sel + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'100010 + assign { } { } + assign $1\LDST_in1_sel[2:0] 3'010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'100011 + assign { } { } + assign $1\LDST_in1_sel[2:0] 3'010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'101010 + assign { } { } + assign $1\LDST_in1_sel[2:0] 3'010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'101011 + assign { } { } + assign $1\LDST_in1_sel[2:0] 3'010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'101000 + assign { } { } + assign $1\LDST_in1_sel[2:0] 3'010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'101001 + assign { } { } + assign $1\LDST_in1_sel[2:0] 3'010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'100000 + assign { } { } + assign $1\LDST_in1_sel[2:0] 3'010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'100001 + assign { } { } + assign $1\LDST_in1_sel[2:0] 3'010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'100110 + assign { } { } + assign $1\LDST_in1_sel[2:0] 3'010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'100111 + assign { } { } + assign $1\LDST_in1_sel[2:0] 3'010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'101100 + assign { } { } + assign $1\LDST_in1_sel[2:0] 3'010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'101101 + assign { } { } + assign $1\LDST_in1_sel[2:0] 3'010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'100100 + assign { } { } + assign $1\LDST_in1_sel[2:0] 3'010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'100101 + assign { } { } + assign $1\LDST_in1_sel[2:0] 3'010 + case + assign $1\LDST_in1_sel[2:0] 3'000 + end + sync always + update \LDST_in1_sel $0\LDST_in1_sel[2:0] + end + attribute \src "issuer_ls180.v:64547.3-64604.6" + process $proc$issuer_ls180.v:64547$3468 + assign { } { } + assign { } { } + assign $0\LDST_in2_sel[3:0] $1\LDST_in2_sel[3:0] + attribute \src "issuer_ls180.v:64548.5-64548.29" + switch \initial + attribute \src "issuer_ls180.v:64548.9-64548.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\LDST_in2_sel[3:0] \LDST_dec31_LDST_dec31_in2_sel + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'111010 + assign { } { } + assign $1\LDST_in2_sel[3:0] \LDST_dec58_LDST_dec58_in2_sel + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'111110 + assign { } { } + assign $1\LDST_in2_sel[3:0] \LDST_dec62_LDST_dec62_in2_sel + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'100010 + assign { } { } + assign $1\LDST_in2_sel[3:0] 4'0011 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'100011 + assign { } { } + assign $1\LDST_in2_sel[3:0] 4'0011 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'101010 + assign { } { } + assign $1\LDST_in2_sel[3:0] 4'0011 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'101011 + assign { } { } + assign $1\LDST_in2_sel[3:0] 4'0011 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'101000 + assign { } { } + assign $1\LDST_in2_sel[3:0] 4'0011 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'101001 + assign { } { } + assign $1\LDST_in2_sel[3:0] 4'0011 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'100000 + assign { } { } + assign $1\LDST_in2_sel[3:0] 4'0011 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'100001 + assign { } { } + assign $1\LDST_in2_sel[3:0] 4'0011 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'100110 + assign { } { } + assign $1\LDST_in2_sel[3:0] 4'0011 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'100111 + assign { } { } + assign $1\LDST_in2_sel[3:0] 4'0011 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'101100 + assign { } { } + assign $1\LDST_in2_sel[3:0] 4'0011 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'101101 + assign { } { } + assign $1\LDST_in2_sel[3:0] 4'0011 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'100100 + assign { } { } + assign $1\LDST_in2_sel[3:0] 4'0011 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'100101 + assign { } { } + assign $1\LDST_in2_sel[3:0] 4'0011 + case + assign $1\LDST_in2_sel[3:0] 4'0000 + end + sync always + update \LDST_in2_sel $0\LDST_in2_sel[3:0] + end + attribute \src "issuer_ls180.v:64605.3-64662.6" + process $proc$issuer_ls180.v:64605$3469 + assign { } { } + assign { } { } + assign $0\LDST_cr_in[2:0] $1\LDST_cr_in[2:0] + attribute \src "issuer_ls180.v:64606.5-64606.29" + switch \initial + attribute \src "issuer_ls180.v:64606.9-64606.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\LDST_cr_in[2:0] \LDST_dec31_LDST_dec31_cr_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'111010 + assign { } { } + assign $1\LDST_cr_in[2:0] \LDST_dec58_LDST_dec58_cr_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'111110 + assign { } { } + assign $1\LDST_cr_in[2:0] \LDST_dec62_LDST_dec62_cr_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'100010 + assign { } { } + assign $1\LDST_cr_in[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'100011 + assign { } { } + assign $1\LDST_cr_in[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'101010 + assign { } { } + assign $1\LDST_cr_in[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'101011 + assign { } { } + assign $1\LDST_cr_in[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'101000 + assign { } { } + assign $1\LDST_cr_in[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'101001 + assign { } { } + assign $1\LDST_cr_in[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'100000 + assign { } { } + assign $1\LDST_cr_in[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'100001 + assign { } { } + assign $1\LDST_cr_in[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'100110 + assign { } { } + assign $1\LDST_cr_in[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'100111 + assign { } { } + assign $1\LDST_cr_in[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'101100 + assign { } { } + assign $1\LDST_cr_in[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'101101 + assign { } { } + assign $1\LDST_cr_in[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'100100 + assign { } { } + assign $1\LDST_cr_in[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'100101 + assign { } { } + assign $1\LDST_cr_in[2:0] 3'000 + case + assign $1\LDST_cr_in[2:0] 3'000 + end + sync always + update \LDST_cr_in $0\LDST_cr_in[2:0] + end + attribute \src "issuer_ls180.v:64663.3-64720.6" + process $proc$issuer_ls180.v:64663$3470 + assign { } { } + assign { } { } + assign $0\LDST_cr_out[2:0] $1\LDST_cr_out[2:0] + attribute \src "issuer_ls180.v:64664.5-64664.29" + switch \initial + attribute \src "issuer_ls180.v:64664.9-64664.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\LDST_cr_out[2:0] \LDST_dec31_LDST_dec31_cr_out + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'111010 + assign { } { } + assign $1\LDST_cr_out[2:0] \LDST_dec58_LDST_dec58_cr_out + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'111110 + assign { } { } + assign $1\LDST_cr_out[2:0] \LDST_dec62_LDST_dec62_cr_out + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'100010 + assign { } { } + assign $1\LDST_cr_out[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'100011 + assign { } { } + assign $1\LDST_cr_out[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'101010 + assign { } { } + assign $1\LDST_cr_out[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'101011 + assign { } { } + assign $1\LDST_cr_out[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'101000 + assign { } { } + assign $1\LDST_cr_out[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'101001 + assign { } { } + assign $1\LDST_cr_out[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'100000 + assign { } { } + assign $1\LDST_cr_out[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'100001 + assign { } { } + assign $1\LDST_cr_out[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'100110 + assign { } { } + assign $1\LDST_cr_out[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'100111 + assign { } { } + assign $1\LDST_cr_out[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'101100 + assign { } { } + assign $1\LDST_cr_out[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'101101 + assign { } { } + assign $1\LDST_cr_out[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'100100 + assign { } { } + assign $1\LDST_cr_out[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'100101 + assign { } { } + assign $1\LDST_cr_out[2:0] 3'000 + case + assign $1\LDST_cr_out[2:0] 3'000 + end + sync always + update \LDST_cr_out $0\LDST_cr_out[2:0] + end + connect \$1 $ternary$issuer_ls180.v:63918$3457_Y + connect \VC_XO \opcode_in [9:0] + connect \VC_VRT \opcode_in [25:21] + connect \VC_VRB \opcode_in [15:11] + connect \VC_VRA \opcode_in [20:16] + connect \VC_Rc \opcode_in [10] + connect \XS_XO \opcode_in [10:2] + connect \XS_sh { \opcode_in [1] \opcode_in [15:11] } + connect \XS_RS \opcode_in [25:21] + connect \XS_Rc \opcode_in [0] + connect \XS_RA \opcode_in [20:16] + connect \VA_XO \opcode_in [5:0] + connect \VA_VRT \opcode_in [25:21] + connect \VA_VRC \opcode_in [10:6] + connect \VA_VRB \opcode_in [15:11] + connect \VA_VRA \opcode_in [20:16] + connect \VA_SHB \opcode_in [9:6] + connect \VA_RT \opcode_in [25:21] + connect \VA_RC \opcode_in [10:6] + connect \VA_RB \opcode_in [15:11] + connect \VA_RA \opcode_in [20:16] + connect \TX_XO \opcode_in [6:1] + connect \TX_XBI \opcode_in [10:7] + connect \TX_UI \opcode_in [15:11] + connect \TX_RA \opcode_in [20:16] + connect \DQE_XO \opcode_in [1:0] + connect \DQE_RT \opcode_in [25:21] + connect \DQE_RA \opcode_in [20:16] + connect \XO_XO \opcode_in [9:1] + connect \XO_RT \opcode_in [25:21] + connect \XO_Rc \opcode_in [0] + connect \XO_RB \opcode_in [15:11] + connect \XO_RA \opcode_in [20:16] + connect \XO_OE \opcode_in [10] + connect \all_PO \opcode_in [31:26] + connect \all_OPCD \opcode_in [31:26] + connect \MD_XO \opcode_in [4:2] + connect \MD_sh { \opcode_in [1] \opcode_in [15:11] } + connect \MD_RS \opcode_in [25:21] + connect \MD_Rc \opcode_in [0] + connect \MD_RA \opcode_in [20:16] + connect \MD_me \opcode_in [10:5] + connect \MD_mb \opcode_in [10:5] + connect \M_SH \opcode_in [15:11] + connect \M_RS \opcode_in [25:21] + connect \M_Rc \opcode_in [0] + connect \M_RB \opcode_in [15:11] + connect \M_RA \opcode_in [20:16] + connect \M_ME \opcode_in [5:1] + connect \M_MB \opcode_in [10:6] + connect \SC_XO_1 \opcode_in [1:0] + connect \SC_XO \opcode_in [1] + connect \SC_LEV \opcode_in [11:5] + connect \MDS_XO \opcode_in [4:1] + connect \MDS_XBI_1 \opcode_in [10:7] + connect \MDS_XBI \opcode_in [10:7] + connect \MDS_RS \opcode_in [25:21] + connect \MDS_Rc \opcode_in [0] + connect \MDS_RB \opcode_in [15:11] + connect \MDS_RA \opcode_in [20:16] + connect \MDS_me \opcode_in [10:5] + connect \MDS_mb \opcode_in [10:5] + connect \MDS_IS \opcode_in [25:21] + connect \MDS_IB \opcode_in [15:11] + connect \Z23_XO \opcode_in [8:1] + connect \Z23_TE \opcode_in [20:16] + connect \Z23_RMC \opcode_in [10:9] + connect \Z23_Rc \opcode_in [0] + connect \Z23_R \opcode_in [16] + connect \Z23_FRTp \opcode_in [25:21] + connect \Z23_FRT \opcode_in [25:21] + connect \Z23_FRBp \opcode_in [15:11] + connect \Z23_FRB \opcode_in [15:11] + connect \Z23_FRAp \opcode_in [20:16] + connect \Z23_FRA \opcode_in [20:16] + connect \XFL_XO \opcode_in [10:1] + connect \XFL_W \opcode_in [16] + connect \XFL_Rc \opcode_in [0] + connect \XFL_L \opcode_in [25] + connect \XFL_FRB \opcode_in [15:11] + connect \XFL_FLM \opcode_in [24:17] + connect \VX_XO_1 \opcode_in [10:0] + connect \VX_XO { \opcode_in [10] \opcode_in [8:0] } + connect \VX_VRT \opcode_in [25:21] + connect \VX_VRB \opcode_in [15:11] + connect \VX_VRA \opcode_in [20:16] + connect \VX_UIM_3 \opcode_in [17:16] + connect \VX_UIM_2 \opcode_in [18:16] + connect \VX_UIM_1 \opcode_in [19:16] + connect \VX_UIM \opcode_in [20:16] + connect \VX_SIM \opcode_in [20:16] + connect \VX_RT \opcode_in [25:21] + connect \VX_RA \opcode_in [20:16] + connect \VX_PS \opcode_in [9] + connect \VX_EO \opcode_in [20:16] + connect \DS_XO \opcode_in [1:0] + connect \DS_VRT \opcode_in [25:21] + connect \DS_VRS \opcode_in [25:21] + connect \DS_RT \opcode_in [25:21] + connect \DS_RSp \opcode_in [25:21] + connect \DS_RS \opcode_in [25:21] + connect \DS_RA \opcode_in [20:16] + connect \DS_FRTp \opcode_in [25:21] + connect \DS_FRSp \opcode_in [25:21] + connect \DS_DS \opcode_in [15:2] + connect \DQ_XO \opcode_in [2:0] + connect \DQ_TX_T { \opcode_in [3] \opcode_in [25:21] } + connect \DQ_T \opcode_in [25:21] + connect \DQ_TX \opcode_in [3] + connect \DQ_SX_S { \opcode_in [3] \opcode_in [25:21] } + connect \DQ_S \opcode_in [25:21] + connect \DQ_SX \opcode_in [3] + connect \DQ_RTp \opcode_in [25:21] + connect \DQ_RA \opcode_in [20:16] + connect \DQ_PT \opcode_in [3:0] + connect \DQ_DQ \opcode_in [15:4] + connect \DX_XO \opcode_in [5:1] + connect \DX_RT \opcode_in [25:21] + connect \DX_d0_d1_d2 { \opcode_in [15:6] \opcode_in [20:16] \opcode_in [0] } + connect \DX_d2 \opcode_in [0] + connect \DX_d1 \opcode_in [20:16] + connect \DX_d0 \opcode_in [15:6] + connect \XFX_XO \opcode_in [10:1] + connect \XFX_SPR \opcode_in [20:11] + connect \XFX_RT \opcode_in [25:21] + connect \XFX_RS \opcode_in [25:21] + connect \XFX_FXM \opcode_in [19:12] + connect \XFX_DUIS \opcode_in [20:11] + connect \XFX_DUI \opcode_in [25:21] + connect \XFX_BHRBE \opcode_in [20:11] + connect \EVS_BFA \opcode_in [2:0] + connect \Z22_XO \opcode_in [9:1] + connect \Z22_SH \opcode_in [15:10] + connect \Z22_Rc \opcode_in [0] + connect \Z22_FRTp \opcode_in [25:21] + connect \Z22_FRT \opcode_in [25:21] + connect \Z22_FRAp \opcode_in [20:16] + connect \Z22_FRA \opcode_in [20:16] + connect \Z22_DGM \opcode_in [15:10] + connect \Z22_DCM \opcode_in [15:10] + connect \Z22_BF \opcode_in [25:23] + connect \XX2_XO_1 \opcode_in [10:2] + connect \XX2_XO { \opcode_in [10:7] \opcode_in [5:3] } + connect \XX2_UIM_1 \opcode_in [17:16] + connect \XX2_UIM \opcode_in [19:16] + connect \XX2_TX_T { \opcode_in [0] \opcode_in [25:21] } + connect \XX2_T \opcode_in [25:21] + connect \XX2_TX \opcode_in [0] + connect \XX2_RT \opcode_in [25:21] + connect \XX2_EO \opcode_in [20:16] + connect \XX2_DCMX \opcode_in [22:16] + connect \XX2_dc_dm_dx { \opcode_in [6] \opcode_in [2] \opcode_in [20:16] } + connect \XX2_dx \opcode_in [20:16] + connect \XX2_dm \opcode_in [2] + connect \XX2_dc \opcode_in [6] + connect \XX2_BX_B { \opcode_in [1] \opcode_in [15:11] } + connect \XX2_B \opcode_in [15:11] + connect \XX2_BX \opcode_in [1] + connect \XX2_BF \opcode_in [25:23] + connect \D_UI \opcode_in [15:0] + connect \D_TO \opcode_in [25:21] + connect \D_SI \opcode_in [15:0] + connect \D_RT \opcode_in [25:21] + connect \D_RS \opcode_in [25:21] + connect \D_RA \opcode_in [20:16] + connect \D_L \opcode_in [21] + connect \D_FRT \opcode_in [25:21] + connect \D_FRS \opcode_in [25:21] + connect \D_D \opcode_in [15:0] + connect \D_BF \opcode_in [25:23] + connect \A_XO \opcode_in [5:1] + connect \A_RT \opcode_in [25:21] + connect \A_Rc \opcode_in [0] + connect \A_RB \opcode_in [15:11] + connect \A_RA \opcode_in [20:16] + connect \A_FRT \opcode_in [25:21] + connect \A_FRC \opcode_in [10:6] + connect \A_FRB \opcode_in [15:11] + connect \A_FRA \opcode_in [20:16] + connect \A_BC \opcode_in [10:6] + connect \XL_XO \opcode_in [10:1] + connect \XL_S \opcode_in [11] + connect \XL_OC \opcode_in [25:11] + connect \XL_LK \opcode_in [0] + connect \XL_BT \opcode_in [25:21] + connect \XL_BO_1 \opcode_in [25:21] + connect \XL_BO \opcode_in [25:21] + connect \XL_BI \opcode_in [20:16] + connect \XL_BH \opcode_in [12:11] + connect \XL_BFA \opcode_in [20:18] + connect \XL_BF \opcode_in [25:23] + connect \XL_BB \opcode_in [15:11] + connect \XL_BA \opcode_in [20:16] + connect \XX4_XO \opcode_in [5:4] + connect \XX4_TX_T { \opcode_in [0] \opcode_in [25:21] } + connect \XX4_T \opcode_in [25:21] + connect \XX4_TX \opcode_in [0] + connect \XX4_CX_C { \opcode_in [3] \opcode_in [10:6] } + connect \XX4_C \opcode_in [10:6] + connect \XX4_CX \opcode_in [3] + connect \XX4_BX_B { \opcode_in [1] \opcode_in [15:11] } + connect \XX4_B \opcode_in [15:11] + connect \XX4_BX \opcode_in [1] + connect \XX4_AX_A { \opcode_in [2] \opcode_in [20:16] } + connect \XX4_A \opcode_in [20:16] + connect \XX4_AX \opcode_in [2] + connect \XX3_XO_2 \opcode_in [9:1] + connect \XX3_XO_1 \opcode_in [10:3] + connect \XX3_XO \opcode_in [10:7] + connect \XX3_TX_T { \opcode_in [0] \opcode_in [25:21] } + connect \XX3_T \opcode_in [25:21] + connect \XX3_TX \opcode_in [0] + connect \XX3_SHW \opcode_in [9:8] + connect \XX3_Rc \opcode_in [10] + connect \XX3_DM \opcode_in [9:8] + connect \XX3_BX_B { \opcode_in [1] \opcode_in [15:11] } + connect \XX3_B \opcode_in [15:11] + connect \XX3_BX \opcode_in [1] + connect \XX3_BF \opcode_in [25:23] + connect \XX3_AX_A { \opcode_in [2] \opcode_in [20:16] } + connect \XX3_A \opcode_in [20:16] + connect \XX3_AX \opcode_in [2] + connect \I_LK \opcode_in [0] + connect \I_LI \opcode_in [25:2] + connect \I_AA \opcode_in [1] + connect \B_LK \opcode_in [0] + connect \B_BO \opcode_in [25:21] + connect \B_BI \opcode_in [20:16] + connect \B_BD \opcode_in [15:2] + connect \B_AA \opcode_in [1] + connect \X_XO_1 \opcode_in [8:1] + connect \X_XO \opcode_in [10:1] + connect \X_WC \opcode_in [22:21] + connect \X_W \opcode_in [16] + connect \X_VRT \opcode_in [25:21] + connect \X_VRS \opcode_in [25:21] + connect \X_UIM \opcode_in [20:16] + connect \X_U \opcode_in [15:12] + connect \X_TX_T { \opcode_in [0] \opcode_in [25:21] } + connect \X_TX \opcode_in [0] + connect \X_TO \opcode_in [25:21] + connect \X_TH \opcode_in [25:21] + connect \X_TBR \opcode_in [20:11] + connect \X_T \opcode_in [25:21] + connect \X_SX_S { \opcode_in [0] \opcode_in [25:21] } + connect \X_SX \opcode_in [0] + connect \X_SR \opcode_in [19:16] + connect \X_SP \opcode_in [20:19] + connect \X_SI \opcode_in [15:11] + connect \X_SH \opcode_in [15:11] + connect \X_S \opcode_in [25:21] + connect \X_RTp \opcode_in [25:21] + connect \X_RT \opcode_in [25:21] + connect \X_RSp \opcode_in [25:21] + connect \X_RS \opcode_in [25:21] + connect \X_RO \opcode_in [0] + connect \X_RM \opcode_in [12:11] + connect \X_RIC \opcode_in [19:18] + connect \X_Rc \opcode_in [0] + connect \X_RB \opcode_in [15:11] + connect \X_RA \opcode_in [20:16] + connect \X_R_1 \opcode_in [16] + connect \X_R \opcode_in [21] + connect \X_PRS \opcode_in [17] + connect \X_NB \opcode_in [15:11] + connect \X_MO \opcode_in [25:21] + connect \X_L3 \opcode_in [17:16] + connect \X_L1 \opcode_in [16] + connect \X_L \opcode_in [21] + connect \X_L2 \opcode_in [22:21] + connect \X_IMM8 \opcode_in [18:11] + connect \X_IH \opcode_in [23:21] + connect \X_FRTp \opcode_in [25:21] + connect \X_FRT \opcode_in [25:21] + connect \X_FRSp \opcode_in [25:21] + connect \X_FRS \opcode_in [25:21] + connect \X_FRBp \opcode_in [15:11] + connect \X_FRB \opcode_in [15:11] + connect \X_FRAp \opcode_in [20:16] + connect \X_FRA \opcode_in [20:16] + connect \X_FC \opcode_in [15:11] + connect \X_EX \opcode_in [0] + connect \X_EO_1 \opcode_in [20:16] + connect \X_EO \opcode_in [20:19] + connect \X_E_1 \opcode_in [19:16] + connect \X_E \opcode_in [15] + connect \X_DRM \opcode_in [13:11] + connect \X_DCMX \opcode_in [22:16] + connect \X_CT \opcode_in [24:21] + connect \X_BO \opcode_in [25:21] + connect \X_BFA \opcode_in [20:18] + connect \X_BF \opcode_in [25:23] + connect \X_A \opcode_in [25] + connect \LDST_SPR \opcode_in [20:11] + connect \LDST_MB \opcode_in [10:6] + connect \LDST_ME \opcode_in [5:1] + connect \LDST_SH \opcode_in [15:11] + connect \LDST_BC \opcode_in [10:6] + connect \LDST_TO \opcode_in [25:21] + connect \LDST_DS \opcode_in [15:2] + connect \LDST_D \opcode_in [15:0] + connect \LDST_BH \opcode_in [12:11] + connect \LDST_BI \opcode_in [20:16] + connect \LDST_BO \opcode_in [25:21] + connect \LDST_FXM \opcode_in [19:12] + connect \LDST_BT \opcode_in [25:21] + connect \LDST_BA \opcode_in [20:16] + connect \LDST_BB \opcode_in [15:11] + connect \LDST_CR \opcode_in [10:1] + connect \LDST_BF \opcode_in [25:23] + connect \LDST_BD \opcode_in [15:2] + connect \LDST_OE \opcode_in [10] + connect \LDST_Rc \opcode_in [0] + connect \LDST_AA \opcode_in [1] + connect \LDST_LK \opcode_in [0] + connect \LDST_LI \opcode_in [25:2] + connect \LDST_ME32 \opcode_in [5:1] + connect \LDST_MB32 \opcode_in [10:6] + connect \LDST_sh { \opcode_in [1] \opcode_in [15:11] } + connect \LDST_SH32 \opcode_in [15:11] + connect \LDST_L \opcode_in [21] + connect \LDST_UI \opcode_in [15:0] + connect \LDST_SI \opcode_in [15:0] + connect \LDST_RB \opcode_in [15:11] + connect \LDST_RA \opcode_in [20:16] + connect \LDST_RT \opcode_in [25:21] + connect \LDST_RS \opcode_in [25:21] + connect \opcode_in \$1 + connect \LDST_dec62_opcode_in \opcode_in + connect \LDST_dec58_opcode_in \opcode_in + connect \LDST_dec31_opcode_in \opcode_in + connect \opcode_switch \opcode_in [31:26] +end +attribute \src "issuer_ls180.v:65056.1-70988.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.dec2.dec" +attribute \generator "nMigen" +module \dec$202 + attribute \src "issuer_ls180.v:67249.3-67387.6" + wire width 8 $0\asmcode[7:0] + attribute \src "issuer_ls180.v:69234.3-69375.6" + wire $0\br[0:0] + attribute \src "issuer_ls180.v:67956.3-68097.6" + wire width 3 $0\cr_in[2:0] + attribute \src "issuer_ls180.v:68098.3-68239.6" + wire width 3 $0\cr_out[2:0] + attribute \src "issuer_ls180.v:68666.3-68807.6" + wire width 2 $0\cry_in[1:0] + attribute \src "issuer_ls180.v:69092.3-69233.6" + wire $0\cry_out[0:0] + attribute \src "issuer_ls180.v:70512.3-70653.6" + wire width 5 $0\form[4:0] + attribute \src "issuer_ls180.v:70228.3-70369.6" + wire width 12 $0\function_unit[11:0] + attribute \src "issuer_ls180.v:67388.3-67529.6" + wire width 3 $0\in1_sel[2:0] + attribute \src "issuer_ls180.v:67530.3-67671.6" + wire width 4 $0\in2_sel[3:0] + attribute \src "issuer_ls180.v:67672.3-67813.6" + wire width 2 $0\in3_sel[1:0] + attribute \src "issuer_ls180.v:65057.7-65057.20" + wire $0\initial[0:0] + attribute \src "issuer_ls180.v:70370.3-70511.6" + wire width 7 $0\internal_op[6:0] + attribute \src "issuer_ls180.v:68808.3-68949.6" + wire $0\inv_a[0:0] + attribute \src "issuer_ls180.v:68950.3-69091.6" + wire $0\inv_out[0:0] + attribute \src "issuer_ls180.v:69660.3-69801.6" + wire $0\is_32b[0:0] + attribute \src "issuer_ls180.v:68240.3-68381.6" + wire width 4 $0\ldst_len[3:0] + attribute \src "issuer_ls180.v:69944.3-70085.6" + wire $0\lk[0:0] + attribute \src "issuer_ls180.v:67814.3-67955.6" + wire width 2 $0\out_sel[1:0] + attribute \src "issuer_ls180.v:68524.3-68665.6" + wire width 2 $0\rc_sel[1:0] + attribute \src "issuer_ls180.v:69518.3-69659.6" + wire $0\rsrv[0:0] + attribute \src "issuer_ls180.v:70086.3-70227.6" + wire $0\sgl_pipe[0:0] + attribute \src "issuer_ls180.v:69802.3-69943.6" + wire $0\sgn[0:0] + attribute \src "issuer_ls180.v:69376.3-69517.6" + wire $0\sgn_ext[0:0] + attribute \src "issuer_ls180.v:68382.3-68523.6" + wire width 2 $0\upd[1:0] + attribute \src "issuer_ls180.v:67249.3-67387.6" + wire width 8 $1\asmcode[7:0] + attribute \src "issuer_ls180.v:69234.3-69375.6" + wire $1\br[0:0] + attribute \src "issuer_ls180.v:67956.3-68097.6" + wire width 3 $1\cr_in[2:0] + attribute \src "issuer_ls180.v:68098.3-68239.6" + wire width 3 $1\cr_out[2:0] + attribute \src "issuer_ls180.v:68666.3-68807.6" + wire width 2 $1\cry_in[1:0] + attribute \src "issuer_ls180.v:69092.3-69233.6" + wire $1\cry_out[0:0] + attribute \src "issuer_ls180.v:70512.3-70653.6" + wire width 5 $1\form[4:0] + attribute \src "issuer_ls180.v:70228.3-70369.6" + wire width 12 $1\function_unit[11:0] + attribute \src "issuer_ls180.v:67388.3-67529.6" + wire width 3 $1\in1_sel[2:0] + attribute \src "issuer_ls180.v:67530.3-67671.6" + wire width 4 $1\in2_sel[3:0] + attribute \src "issuer_ls180.v:67672.3-67813.6" + wire width 2 $1\in3_sel[1:0] + attribute \src "issuer_ls180.v:70370.3-70511.6" + wire width 7 $1\internal_op[6:0] + attribute \src "issuer_ls180.v:68808.3-68949.6" + wire $1\inv_a[0:0] + attribute \src "issuer_ls180.v:68950.3-69091.6" + wire $1\inv_out[0:0] + attribute \src "issuer_ls180.v:69660.3-69801.6" + wire $1\is_32b[0:0] + attribute \src "issuer_ls180.v:68240.3-68381.6" + wire width 4 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attribute \src "issuer_ls180.v:69092.3-69233.6" + wire $2\cry_out[0:0] + attribute \src "issuer_ls180.v:70512.3-70653.6" + wire width 5 $2\form[4:0] + attribute \src "issuer_ls180.v:70228.3-70369.6" + wire width 12 $2\function_unit[11:0] + attribute \src "issuer_ls180.v:67388.3-67529.6" + wire width 3 $2\in1_sel[2:0] + attribute \src "issuer_ls180.v:67530.3-67671.6" + wire width 4 $2\in2_sel[3:0] + attribute \src "issuer_ls180.v:67672.3-67813.6" + wire width 2 $2\in3_sel[1:0] + attribute \src "issuer_ls180.v:70370.3-70511.6" + wire width 7 $2\internal_op[6:0] + attribute \src "issuer_ls180.v:68808.3-68949.6" + wire $2\inv_a[0:0] + attribute \src "issuer_ls180.v:68950.3-69091.6" + wire $2\inv_out[0:0] + attribute \src "issuer_ls180.v:69660.3-69801.6" + wire $2\is_32b[0:0] + attribute \src "issuer_ls180.v:68240.3-68381.6" + wire width 4 $2\ldst_len[3:0] + attribute \src "issuer_ls180.v:69944.3-70085.6" + wire $2\lk[0:0] + attribute \src "issuer_ls180.v:67814.3-67955.6" + wire width 2 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"/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \DQ_TX_T + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 3 \DQ_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 14 \DS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 14 \DS_DS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \DS_FRSp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \DS_FRTp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \DS_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \DS_RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \DS_RSp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \DS_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \DS_VRS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \DS_VRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 2 \DS_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \DX_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \DX_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 10 \DX_d0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 16 \DX_d0_d1_d2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \DX_d1 + attribute \src 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wire width 16 \D_SI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \D_TO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 16 \D_UI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 3 \EVS_BFA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 8 output 26 \FXM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \I_AA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 24 \I_LI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \I_LK + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire \L + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 24 \LI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire output 11 \LK + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 \MB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 \MB32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \MDS_IB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \MDS_IS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \MDS_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \MDS_RB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \MDS_RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \MDS_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 4 \MDS_XBI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 4 \MDS_XBI_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 4 \MDS_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \MDS_mb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \MDS_me + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \MD_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \MD_RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \MD_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 3 \MD_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \MD_mb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \MD_me + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \MD_sh + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 \ME + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 \ME32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \M_MB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \M_ME + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \M_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \M_RB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \M_RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \M_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \M_SH + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire output 22 \OE + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 output 19 \RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 output 20 \RB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 output 17 \RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 output 18 \RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire output 21 \Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 7 \SC_LEV + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \SC_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 2 \SC_XO_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 \SH + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 \SH32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 16 \SI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 10 output 30 \SPR + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 \TO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \TX_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \TX_UI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 4 \TX_XBI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \TX_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 16 \UI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \VA_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \VA_RB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \VA_RC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \VA_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 4 \VA_SHB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \VA_VRA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \VA_VRB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \VA_VRC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \VA_VRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \VA_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \VC_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \VC_VRA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \VC_VRB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \VC_VRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 10 \VC_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \VX_EO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \VX_PS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \VX_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \VX_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \VX_SIM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \VX_UIM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 4 \VX_UIM_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 3 \VX_UIM_2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 2 \VX_UIM_3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \VX_VRA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \VX_VRB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \VX_VRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 10 \VX_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 11 \VX_XO_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 8 \XFL_FLM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XFL_FRB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \XFL_L + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \XFL_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \XFL_W + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 10 \XFL_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 10 \XFX_BHRBE + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XFX_DUI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 10 \XFX_DUIS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 8 \XFX_FXM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XFX_RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XFX_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 10 \XFX_SPR + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 10 \XFX_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XL_BA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XL_BB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 3 \XL_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 3 \XL_BFA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 2 \XL_BH + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XL_BI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XL_BO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XL_BO_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 output 33 \XL_BT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \XL_LK + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 15 \XL_OC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \XL_S + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 10 output 34 \XL_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \XO_OE + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XO_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XO_RB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XO_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \XO_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 9 \XO_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XS_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XS_RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \XS_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 9 \XS_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \XS_sh + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XX2_B + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 3 \XX2_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \XX2_BX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \XX2_BX_B + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 7 \XX2_DCMX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XX2_EO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XX2_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XX2_T + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \XX2_TX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \XX2_TX_T + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 4 \XX2_UIM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 2 \XX2_UIM_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 7 \XX2_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 9 \XX2_XO_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \XX2_dc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 7 \XX2_dc_dm_dx + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \XX2_dm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XX2_dx + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XX3_A + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \XX3_AX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \XX3_AX_A + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XX3_B + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 3 \XX3_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \XX3_BX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \XX3_BX_B + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 2 \XX3_DM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \XX3_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 2 \XX3_SHW + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XX3_T + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \XX3_TX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \XX3_TX_T + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 4 \XX3_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 8 \XX3_XO_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 9 \XX3_XO_2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XX4_A + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \XX4_AX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \XX4_AX_A + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XX4_B + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \XX4_BX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \XX4_BX_B + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XX4_C + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \XX4_CX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \XX4_CX_C + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \XX4_T + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \XX4_TX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \XX4_TX_T + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 2 \XX4_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \X_A + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 3 output 31 \X_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 3 output 32 \X_BFA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_BO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 4 \X_CT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 7 \X_DCMX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 3 \X_DRM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \X_E + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 2 \X_EO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_EO_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \X_EX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 4 \X_E_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_FC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_FRA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_FRAp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_FRB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_FRBp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_FRS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_FRSp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_FRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_FRTp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 3 \X_IH + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 8 \X_IMM8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \X_L + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \X_L1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 2 \X_L2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 2 \X_L3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_MO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_NB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \X_PRS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \X_R + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_RB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 2 \X_RIC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 2 \X_RM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \X_RO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_RSp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_RTp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \X_R_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \X_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_S + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_SH + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_SI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 2 \X_SP + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 4 \X_SR + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \X_SX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \X_SX_S + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_T + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 10 \X_TBR + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_TH + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_TO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \X_TX + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \X_TX_T + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 4 \X_U + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_UIM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_VRS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \X_VRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \X_W + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 2 \X_WC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 10 \X_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 8 \X_XO_1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 3 \Z22_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \Z22_DCM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \Z22_DGM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \Z22_FRA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \Z22_FRAp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \Z22_FRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \Z22_FRTp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \Z22_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \Z22_SH + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 9 \Z22_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \Z23_FRA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \Z23_FRAp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \Z23_FRB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \Z23_FRBp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \Z23_FRT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \Z23_FRTp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \Z23_R + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 2 \Z23_RMC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire \Z23_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \Z23_TE + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 8 \Z23_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \all_OPCD + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 6 \all_PO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 8 \asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + wire input 35 \bigendian + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \br + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 4 \cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 5 \cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 8 \cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \cry_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 8 \dec19_dec19_asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec19_dec19_br + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 \dec19_dec19_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 \dec19_dec19_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \dec19_dec19_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec19_dec19_cry_out + attribute \enum_base_type "Form" + attribute \enum_value_00000 "NONE" + attribute \enum_value_00001 "I" + attribute \enum_value_00010 "B" + attribute \enum_value_00011 "SC" + attribute \enum_value_00100 "D" + attribute \enum_value_00101 "DS" + attribute \enum_value_00110 "DQ" + attribute \enum_value_00111 "DX" + attribute \enum_value_01000 "X" + attribute \enum_value_01001 "XL" + attribute \enum_value_01010 "XFX" + attribute \enum_value_01011 "XFL" + attribute \enum_value_01100 "XX1" + attribute \enum_value_01101 "XX2" + attribute \enum_value_01110 "XX3" + attribute \enum_value_01111 "XX4" + attribute \enum_value_10000 "XS" + attribute \enum_value_10001 "XO" + attribute \enum_value_10010 "A" + attribute \enum_value_10011 "M" + attribute \enum_value_10100 "MD" + attribute \enum_value_10101 "MDS" + attribute \enum_value_10110 "VA" + attribute \enum_value_10111 "VC" + attribute \enum_value_11000 "VX" + attribute \enum_value_11001 "EVX" + attribute \enum_value_11010 "EVS" + attribute \enum_value_11011 "Z22" + attribute \enum_value_11100 "Z23" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 5 \dec19_dec19_form + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 12 \dec19_dec19_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 \dec19_dec19_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 \dec19_dec19_in2_sel + attribute \enum_base_type "In3Sel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RS" + attribute \enum_value_10 "RB" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \dec19_dec19_in3_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 7 \dec19_dec19_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec19_dec19_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec19_dec19_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec19_dec19_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 \dec19_dec19_ldst_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec19_dec19_lk + attribute \enum_base_type "OutSel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RT" + attribute \enum_value_10 "RA" + attribute \enum_value_11 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \dec19_dec19_out_sel + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \dec19_dec19_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec19_dec19_rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec19_dec19_sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec19_dec19_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec19_dec19_sgn_ext + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \dec19_dec19_upd + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + wire width 32 \dec19_opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 8 \dec30_dec30_asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec30_dec30_br + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 \dec30_dec30_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 \dec30_dec30_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \dec30_dec30_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec30_dec30_cry_out + attribute \enum_base_type "Form" + attribute \enum_value_00000 "NONE" + attribute \enum_value_00001 "I" + attribute \enum_value_00010 "B" + attribute \enum_value_00011 "SC" + attribute \enum_value_00100 "D" + attribute \enum_value_00101 "DS" + attribute \enum_value_00110 "DQ" + attribute \enum_value_00111 "DX" + attribute \enum_value_01000 "X" + attribute \enum_value_01001 "XL" + attribute \enum_value_01010 "XFX" + attribute \enum_value_01011 "XFL" + attribute \enum_value_01100 "XX1" + attribute \enum_value_01101 "XX2" + attribute \enum_value_01110 "XX3" + attribute \enum_value_01111 "XX4" + attribute \enum_value_10000 "XS" + attribute \enum_value_10001 "XO" + attribute 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\enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 12 \dec30_dec30_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 \dec30_dec30_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 \dec30_dec30_in2_sel + attribute \enum_base_type "In3Sel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RS" + attribute \enum_value_10 "RB" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \dec30_dec30_in3_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute 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attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute 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attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute 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\dec58_dec58_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec58_dec58_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 \dec58_dec58_ldst_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec58_dec58_lk + attribute \enum_base_type "OutSel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RT" + attribute \enum_value_10 "RA" + attribute \enum_value_11 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \dec58_dec58_out_sel + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + 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"/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 8 \dec62_dec62_asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec62_dec62_br + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 \dec62_dec62_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 \dec62_dec62_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \dec62_dec62_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec62_dec62_cry_out + attribute \enum_base_type "Form" + attribute \enum_value_00000 "NONE" + attribute \enum_value_00001 "I" + attribute \enum_value_00010 "B" + attribute \enum_value_00011 "SC" + attribute \enum_value_00100 "D" + attribute \enum_value_00101 "DS" + attribute \enum_value_00110 "DQ" + attribute \enum_value_00111 "DX" + attribute \enum_value_01000 "X" + attribute \enum_value_01001 "XL" + attribute \enum_value_01010 "XFX" + attribute \enum_value_01011 "XFL" + attribute \enum_value_01100 "XX1" + attribute \enum_value_01101 "XX2" + attribute \enum_value_01110 "XX3" + attribute \enum_value_01111 "XX4" + attribute \enum_value_10000 "XS" + attribute \enum_value_10001 "XO" + attribute \enum_value_10010 "A" + attribute \enum_value_10011 "M" + attribute \enum_value_10100 "MD" + attribute \enum_value_10101 "MDS" + attribute \enum_value_10110 "VA" + attribute \enum_value_10111 "VC" + attribute \enum_value_11000 "VX" + attribute \enum_value_11001 "EVX" + attribute \enum_value_11010 "EVS" + attribute \enum_value_11011 "Z22" + attribute \enum_value_11100 "Z23" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 5 \dec62_dec62_form + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 12 \dec62_dec62_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 \dec62_dec62_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 \dec62_dec62_in2_sel + attribute \enum_base_type "In3Sel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RS" + attribute \enum_value_10 "RB" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \dec62_dec62_in3_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 7 \dec62_dec62_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec62_dec62_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec62_dec62_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec62_dec62_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 \dec62_dec62_ldst_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec62_dec62_lk + attribute \enum_base_type "OutSel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RT" + attribute \enum_value_10 "RA" + attribute \enum_value_11 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \dec62_dec62_out_sel + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \dec62_dec62_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec62_dec62_rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec62_dec62_sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec62_dec62_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec62_dec62_sgn_ext + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \dec62_dec62_upd + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + wire width 32 \dec62_opcode_in + attribute \enum_base_type "Form" + attribute \enum_value_00000 "NONE" + attribute \enum_value_00001 "I" + attribute \enum_value_00010 "B" + attribute \enum_value_00011 "SC" + attribute \enum_value_00100 "D" + attribute \enum_value_00101 "DS" + attribute \enum_value_00110 "DQ" + attribute \enum_value_00111 "DX" + attribute \enum_value_01000 "X" + attribute \enum_value_01001 "XL" + attribute \enum_value_01010 "XFX" + attribute \enum_value_01011 "XFL" + attribute \enum_value_01100 "XX1" + attribute \enum_value_01101 "XX2" + attribute \enum_value_01110 "XX3" + attribute \enum_value_01111 "XX4" + attribute \enum_value_10000 "XS" + attribute \enum_value_10001 "XO" + attribute \enum_value_10010 "A" + attribute \enum_value_10011 "M" + attribute \enum_value_10100 "MD" + attribute \enum_value_10101 "MDS" + attribute \enum_value_10110 "VA" + attribute \enum_value_10111 "VC" + attribute \enum_value_11000 "VX" + attribute \enum_value_11001 "EVX" + attribute \enum_value_11010 "EVS" + attribute \enum_value_11011 "Z22" + attribute \enum_value_11100 "Z23" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 5 \form + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 12 output 7 \function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 12 \in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 output 13 \in2_sel + attribute \enum_base_type "In3Sel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RS" + attribute \enum_value_10 "RB" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 14 \in3_sel + attribute \src "issuer_ls180.v:65057.7-65057.15" + wire \initial + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 7 output 6 \internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 9 \is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 \ldst_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 10 \lk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + wire width 32 output 2 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:320" + wire width 6 \opcode_switch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:320" + wire width 32 \opcode_switch$1 + attribute \enum_base_type "OutSel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RT" + attribute \enum_value_10 "RA" + attribute \enum_value_11 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 15 \out_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:442" + wire width 32 input 1 \raw_opcode_in + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 3 \rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \sgn_ext + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 6 \sh + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 16 \upd + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:478" + cell $mux $ternary$issuer_ls180.v:67113$3472 + parameter \WIDTH 32 + connect \A \raw_opcode_in + connect \B { \raw_opcode_in [7:0] \raw_opcode_in [15:8] \raw_opcode_in [23:16] \raw_opcode_in [31:24] } + connect \S \bigendian + connect \Y $ternary$issuer_ls180.v:67113$3472_Y + end + attribute \module_not_derived 1 + attribute \src "issuer_ls180.v:67114.9-67140.4" + cell \dec19 \dec19 + connect \dec19_asmcode \dec19_dec19_asmcode + connect \dec19_br \dec19_dec19_br + connect \dec19_cr_in \dec19_dec19_cr_in + connect \dec19_cr_out \dec19_dec19_cr_out + connect \dec19_cry_in \dec19_dec19_cry_in + connect \dec19_cry_out \dec19_dec19_cry_out + connect \dec19_form \dec19_dec19_form + connect \dec19_function_unit \dec19_dec19_function_unit + connect \dec19_in1_sel \dec19_dec19_in1_sel + connect \dec19_in2_sel \dec19_dec19_in2_sel + connect \dec19_in3_sel \dec19_dec19_in3_sel + connect \dec19_internal_op \dec19_dec19_internal_op + connect \dec19_inv_a \dec19_dec19_inv_a + connect \dec19_inv_out \dec19_dec19_inv_out + connect \dec19_is_32b \dec19_dec19_is_32b + connect \dec19_ldst_len \dec19_dec19_ldst_len + connect \dec19_lk \dec19_dec19_lk + connect \dec19_out_sel \dec19_dec19_out_sel + connect \dec19_rc_sel \dec19_dec19_rc_sel + connect \dec19_rsrv \dec19_dec19_rsrv + connect \dec19_sgl_pipe \dec19_dec19_sgl_pipe + connect \dec19_sgn \dec19_dec19_sgn + connect \dec19_sgn_ext \dec19_dec19_sgn_ext + connect \dec19_upd \dec19_dec19_upd + connect \opcode_in \dec19_opcode_in + end + attribute \module_not_derived 1 + attribute \src "issuer_ls180.v:67141.9-67167.4" + cell \dec30 \dec30 + connect \dec30_asmcode \dec30_dec30_asmcode + connect \dec30_br \dec30_dec30_br + connect \dec30_cr_in \dec30_dec30_cr_in + connect \dec30_cr_out \dec30_dec30_cr_out + connect \dec30_cry_in \dec30_dec30_cry_in + connect \dec30_cry_out \dec30_dec30_cry_out + connect \dec30_form \dec30_dec30_form + connect \dec30_function_unit \dec30_dec30_function_unit + connect \dec30_in1_sel \dec30_dec30_in1_sel + connect \dec30_in2_sel \dec30_dec30_in2_sel + connect \dec30_in3_sel \dec30_dec30_in3_sel + connect \dec30_internal_op \dec30_dec30_internal_op + connect \dec30_inv_a \dec30_dec30_inv_a + connect \dec30_inv_out \dec30_dec30_inv_out + connect \dec30_is_32b \dec30_dec30_is_32b + connect \dec30_ldst_len \dec30_dec30_ldst_len + connect \dec30_lk \dec30_dec30_lk + connect \dec30_out_sel \dec30_dec30_out_sel + connect \dec30_rc_sel \dec30_dec30_rc_sel + connect \dec30_rsrv \dec30_dec30_rsrv + connect \dec30_sgl_pipe \dec30_dec30_sgl_pipe + connect \dec30_sgn \dec30_dec30_sgn + connect \dec30_sgn_ext \dec30_dec30_sgn_ext + connect \dec30_upd \dec30_dec30_upd + connect \opcode_in \dec30_opcode_in + end + attribute \module_not_derived 1 + attribute \src "issuer_ls180.v:67168.9-67194.4" + cell \dec31 \dec31 + connect \dec31_asmcode \dec31_dec31_asmcode + connect \dec31_br \dec31_dec31_br + connect \dec31_cr_in \dec31_dec31_cr_in + connect \dec31_cr_out \dec31_dec31_cr_out + connect \dec31_cry_in \dec31_dec31_cry_in + connect \dec31_cry_out \dec31_dec31_cry_out + connect \dec31_form \dec31_dec31_form + connect \dec31_function_unit \dec31_dec31_function_unit + connect \dec31_in1_sel \dec31_dec31_in1_sel + connect \dec31_in2_sel \dec31_dec31_in2_sel + connect \dec31_in3_sel \dec31_dec31_in3_sel + connect \dec31_internal_op \dec31_dec31_internal_op + connect \dec31_inv_a \dec31_dec31_inv_a + connect \dec31_inv_out \dec31_dec31_inv_out + connect \dec31_is_32b \dec31_dec31_is_32b + connect \dec31_ldst_len \dec31_dec31_ldst_len + connect \dec31_lk \dec31_dec31_lk + connect \dec31_out_sel \dec31_dec31_out_sel + connect \dec31_rc_sel \dec31_dec31_rc_sel + connect \dec31_rsrv \dec31_dec31_rsrv + connect \dec31_sgl_pipe \dec31_dec31_sgl_pipe + connect \dec31_sgn \dec31_dec31_sgn + connect \dec31_sgn_ext \dec31_dec31_sgn_ext + connect \dec31_upd \dec31_dec31_upd + connect \opcode_in \dec31_opcode_in + end + attribute \module_not_derived 1 + attribute \src "issuer_ls180.v:67195.9-67221.4" + cell \dec58 \dec58 + connect \dec58_asmcode \dec58_dec58_asmcode + connect \dec58_br \dec58_dec58_br + connect \dec58_cr_in \dec58_dec58_cr_in + connect \dec58_cr_out \dec58_dec58_cr_out + connect \dec58_cry_in \dec58_dec58_cry_in + connect \dec58_cry_out \dec58_dec58_cry_out + connect \dec58_form \dec58_dec58_form + connect \dec58_function_unit \dec58_dec58_function_unit + connect \dec58_in1_sel \dec58_dec58_in1_sel + connect \dec58_in2_sel \dec58_dec58_in2_sel + connect \dec58_in3_sel \dec58_dec58_in3_sel + connect \dec58_internal_op \dec58_dec58_internal_op + connect \dec58_inv_a \dec58_dec58_inv_a + connect \dec58_inv_out \dec58_dec58_inv_out + connect \dec58_is_32b \dec58_dec58_is_32b + connect \dec58_ldst_len \dec58_dec58_ldst_len + connect \dec58_lk \dec58_dec58_lk + connect \dec58_out_sel \dec58_dec58_out_sel + connect \dec58_rc_sel \dec58_dec58_rc_sel + connect \dec58_rsrv \dec58_dec58_rsrv + connect \dec58_sgl_pipe \dec58_dec58_sgl_pipe + connect \dec58_sgn \dec58_dec58_sgn + connect \dec58_sgn_ext \dec58_dec58_sgn_ext + connect \dec58_upd \dec58_dec58_upd + connect \opcode_in \dec58_opcode_in + end + attribute \module_not_derived 1 + attribute \src "issuer_ls180.v:67222.9-67248.4" + cell \dec62 \dec62 + connect \dec62_asmcode \dec62_dec62_asmcode + connect \dec62_br \dec62_dec62_br + connect \dec62_cr_in \dec62_dec62_cr_in + connect \dec62_cr_out \dec62_dec62_cr_out + connect \dec62_cry_in \dec62_dec62_cry_in + connect \dec62_cry_out \dec62_dec62_cry_out + connect \dec62_form \dec62_dec62_form + connect \dec62_function_unit \dec62_dec62_function_unit + connect \dec62_in1_sel \dec62_dec62_in1_sel + connect \dec62_in2_sel \dec62_dec62_in2_sel + connect \dec62_in3_sel \dec62_dec62_in3_sel + connect \dec62_internal_op \dec62_dec62_internal_op + connect \dec62_inv_a \dec62_dec62_inv_a + connect \dec62_inv_out \dec62_dec62_inv_out + connect \dec62_is_32b \dec62_dec62_is_32b + connect \dec62_ldst_len \dec62_dec62_ldst_len + connect \dec62_lk \dec62_dec62_lk + connect \dec62_out_sel \dec62_dec62_out_sel + connect \dec62_rc_sel \dec62_dec62_rc_sel + connect \dec62_rsrv \dec62_dec62_rsrv + connect \dec62_sgl_pipe \dec62_dec62_sgl_pipe + connect \dec62_sgn \dec62_dec62_sgn + connect \dec62_sgn_ext \dec62_dec62_sgn_ext + connect \dec62_upd \dec62_dec62_upd + connect \opcode_in \dec62_opcode_in + end + attribute \src "issuer_ls180.v:65057.7-65057.20" + process $proc$issuer_ls180.v:65057$3497 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "issuer_ls180.v:67249.3-67387.6" + process $proc$issuer_ls180.v:67249$3473 + assign { } { } + assign { } { } + assign { } { } + assign $0\asmcode[7:0] $2\asmcode[7:0] + attribute \src "issuer_ls180.v:67250.5-67250.29" + switch \initial + attribute \src "issuer_ls180.v:67250.9-67250.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'010011 + assign { } { } + assign $1\asmcode[7:0] \dec19_dec19_asmcode + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'011110 + assign { } { } + assign $1\asmcode[7:0] \dec30_dec30_asmcode + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\asmcode[7:0] \dec31_dec31_asmcode + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'111010 + assign { } { } + assign $1\asmcode[7:0] \dec58_dec58_asmcode + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'111110 + assign { } { } + assign $1\asmcode[7:0] \dec62_dec62_asmcode + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'001100 + assign { } { } + assign $1\asmcode[7:0] 8'00000111 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'001101 + assign { } { } + assign $1\asmcode[7:0] 8'00001000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'001110 + assign { } { } + assign $1\asmcode[7:0] 8'00000110 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'001111 + assign { } { } + assign $1\asmcode[7:0] 8'00001001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'011100 + assign { } { } + assign $1\asmcode[7:0] 8'00010001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'011101 + assign { } { } + assign $1\asmcode[7:0] 8'00010010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'010010 + assign { } { } + assign $1\asmcode[7:0] 8'00010100 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'010000 + assign { } { } + assign $1\asmcode[7:0] 8'00010101 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'001011 + assign { } { } + assign $1\asmcode[7:0] 8'00011101 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'001010 + assign { } { } + assign $1\asmcode[7:0] 8'00011111 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'100010 + assign { } { } + assign $1\asmcode[7:0] 8'01001110 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'100011 + assign { } { } + assign $1\asmcode[7:0] 8'01001111 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'101010 + assign { } { } + assign $1\asmcode[7:0] 8'01011000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'101011 + assign { } { } + assign $1\asmcode[7:0] 8'01011010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'101000 + assign { } { } + assign $1\asmcode[7:0] 8'01011110 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'101001 + assign { } { } + assign $1\asmcode[7:0] 8'01011111 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'100000 + assign { } { } + assign $1\asmcode[7:0] 8'01100111 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'100001 + assign { } { } + assign $1\asmcode[7:0] 8'01101001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'000111 + assign { } { } + assign $1\asmcode[7:0] 8'10000000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'011000 + assign { } { } + assign $1\asmcode[7:0] 8'10001010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'011001 + assign { } { } + assign $1\asmcode[7:0] 8'10001011 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'010100 + assign { } { } + assign $1\asmcode[7:0] 8'10011000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'010101 + assign { } { } + assign $1\asmcode[7:0] 8'10011001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'010111 + assign { } { } + assign $1\asmcode[7:0] 8'10011010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'100110 + assign { } { } + assign $1\asmcode[7:0] 8'10100110 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'100111 + assign { } { } + assign $1\asmcode[7:0] 8'10101001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'101100 + assign { } { } + assign $1\asmcode[7:0] 8'10110010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'101101 + assign { } { } + assign $1\asmcode[7:0] 8'10110101 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'100100 + assign { } { } + assign $1\asmcode[7:0] 8'10111000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'100101 + assign { } { } + assign $1\asmcode[7:0] 8'10111011 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'001000 + assign { } { } + assign $1\asmcode[7:0] 8'11000011 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'000010 + assign { } { } + assign $1\asmcode[7:0] 8'11001011 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'000011 + assign { } { } + assign $1\asmcode[7:0] 8'11001111 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'011010 + assign { } { } + assign $1\asmcode[7:0] 8'11010001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'011011 + assign { } { } + assign $1\asmcode[7:0] 8'11010010 + case + assign $1\asmcode[7:0] 8'00000000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch$1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 32'000000---------------0100000000- + assign { } { } + assign $2\asmcode[7:0] 8'00010011 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1610612736 + assign { } { } + assign $2\asmcode[7:0] 8'10000110 + attribute \src "issuer_ls180.v:0.0-0.0" + case 32'000001---------------0000000011- + assign { } { } + assign $2\asmcode[7:0] 8'10011100 + case + assign $2\asmcode[7:0] $1\asmcode[7:0] + end + sync always + update \asmcode $0\asmcode[7:0] + end + attribute \src "issuer_ls180.v:67388.3-67529.6" + process $proc$issuer_ls180.v:67388$3474 + assign { } { } + assign { } { } + assign { } { } + assign $0\in1_sel[2:0] $2\in1_sel[2:0] + attribute \src "issuer_ls180.v:67389.5-67389.29" + switch \initial + attribute \src "issuer_ls180.v:67389.9-67389.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'010011 + assign { } { } + assign $1\in1_sel[2:0] \dec19_dec19_in1_sel + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'011110 + assign { } { } + assign $1\in1_sel[2:0] \dec30_dec30_in1_sel + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\in1_sel[2:0] \dec31_dec31_in1_sel + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'111010 + assign { } { } + assign $1\in1_sel[2:0] \dec58_dec58_in1_sel + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'111110 + assign { } { } + assign $1\in1_sel[2:0] \dec62_dec62_in1_sel + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'001100 + assign { } { } + assign $1\in1_sel[2:0] 3'001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'001101 + assign { } { } + assign $1\in1_sel[2:0] 3'001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'001110 + assign { } { } + assign $1\in1_sel[2:0] 3'010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'001111 + assign { } { } + assign $1\in1_sel[2:0] 3'010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'010001 + assign { } { } + assign $1\in1_sel[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'011100 + assign { } { } + assign $1\in1_sel[2:0] 3'100 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'011101 + assign { } { } + assign $1\in1_sel[2:0] 3'100 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'010010 + assign { } { } + assign $1\in1_sel[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'010000 + assign { } { } + assign $1\in1_sel[2:0] 3'011 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'001011 + assign { } { } + assign $1\in1_sel[2:0] 3'001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'001010 + assign { } { } + assign $1\in1_sel[2:0] 3'001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'100010 + assign { } { } + assign $1\in1_sel[2:0] 3'010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'100011 + assign { } { } + assign $1\in1_sel[2:0] 3'010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'101010 + assign { } { } + assign $1\in1_sel[2:0] 3'010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'101011 + assign { } { } + assign $1\in1_sel[2:0] 3'010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'101000 + assign { } { } + assign $1\in1_sel[2:0] 3'010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'101001 + assign { } { } + assign $1\in1_sel[2:0] 3'010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'100000 + assign { } { } + assign $1\in1_sel[2:0] 3'010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'100001 + assign { } { } + assign $1\in1_sel[2:0] 3'010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'000111 + assign { } { } + assign $1\in1_sel[2:0] 3'001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'011000 + assign { } { } + assign $1\in1_sel[2:0] 3'100 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'011001 + assign { } { } + assign $1\in1_sel[2:0] 3'100 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'010100 + assign { } { } + assign $1\in1_sel[2:0] 3'001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'010101 + assign { } { } + assign $1\in1_sel[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'010111 + assign { } { } + assign $1\in1_sel[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'100110 + assign { } { } + assign $1\in1_sel[2:0] 3'010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'100111 + assign { } { } + assign $1\in1_sel[2:0] 3'010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'101100 + assign { } { } + assign $1\in1_sel[2:0] 3'010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'101101 + assign { } { } + assign $1\in1_sel[2:0] 3'010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'100100 + assign { } { } + assign $1\in1_sel[2:0] 3'010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'100101 + assign { } { } + assign $1\in1_sel[2:0] 3'010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'001000 + assign { } { } + assign $1\in1_sel[2:0] 3'001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'000010 + assign { } { } + assign $1\in1_sel[2:0] 3'001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'000011 + assign { } { } + assign $1\in1_sel[2:0] 3'001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'011010 + assign { } { } + assign $1\in1_sel[2:0] 3'100 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'011011 + assign { } { } + assign $1\in1_sel[2:0] 3'100 + case + assign $1\in1_sel[2:0] 3'000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch$1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 32'000000---------------0100000000- + assign { } { } + assign $2\in1_sel[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1610612736 + assign { } { } + assign $2\in1_sel[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 32'000001---------------0000000011- + assign { } { } + assign $2\in1_sel[2:0] 3'000 + case + assign $2\in1_sel[2:0] $1\in1_sel[2:0] + end + sync always + update \in1_sel $0\in1_sel[2:0] + end + attribute \src "issuer_ls180.v:67530.3-67671.6" + process $proc$issuer_ls180.v:67530$3475 + assign { } { } + assign { } { } + assign { } { } + assign $0\in2_sel[3:0] $2\in2_sel[3:0] + attribute \src "issuer_ls180.v:67531.5-67531.29" + switch \initial + attribute \src "issuer_ls180.v:67531.9-67531.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'010011 + assign { } { } + assign $1\in2_sel[3:0] \dec19_dec19_in2_sel + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'011110 + assign { } { } + assign $1\in2_sel[3:0] \dec30_dec30_in2_sel + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\in2_sel[3:0] \dec31_dec31_in2_sel + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'111010 + assign { } { } + assign $1\in2_sel[3:0] \dec58_dec58_in2_sel + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'111110 + assign { } { } + assign $1\in2_sel[3:0] \dec62_dec62_in2_sel + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'001100 + assign { } { } + assign $1\in2_sel[3:0] 4'0011 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'001101 + assign { } { } + assign $1\in2_sel[3:0] 4'0011 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'001110 + assign { } { } + assign $1\in2_sel[3:0] 4'0011 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'001111 + assign { } { } + assign $1\in2_sel[3:0] 4'0101 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'010001 + assign { } { } + assign $1\in2_sel[3:0] 4'0000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'011100 + assign { } { } + assign $1\in2_sel[3:0] 4'0010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'011101 + assign { } { } + assign $1\in2_sel[3:0] 4'0100 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'010010 + assign { } { } + assign $1\in2_sel[3:0] 4'0110 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'010000 + assign { } { } + assign $1\in2_sel[3:0] 4'0111 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'001011 + assign { } { } + assign $1\in2_sel[3:0] 4'0011 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'001010 + assign { } { } + assign $1\in2_sel[3:0] 4'0010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'100010 + assign { } { } + assign $1\in2_sel[3:0] 4'0011 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'100011 + assign { } { } + assign $1\in2_sel[3:0] 4'0011 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'101010 + assign { } { } + assign $1\in2_sel[3:0] 4'0011 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'101011 + assign { } { } + assign $1\in2_sel[3:0] 4'0011 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'101000 + assign { } { } + assign $1\in2_sel[3:0] 4'0011 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'101001 + assign { } { } + assign $1\in2_sel[3:0] 4'0011 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'100000 + assign { } { } + assign $1\in2_sel[3:0] 4'0011 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'100001 + assign { } { } + assign $1\in2_sel[3:0] 4'0011 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'000111 + assign { } { } + assign $1\in2_sel[3:0] 4'0011 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'011000 + assign { } { } + assign $1\in2_sel[3:0] 4'0010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'011001 + assign { } { } + assign $1\in2_sel[3:0] 4'0100 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'010100 + assign { } { } + assign $1\in2_sel[3:0] 4'1011 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'010101 + assign { } { } + assign $1\in2_sel[3:0] 4'1011 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'010111 + assign { } { } + assign $1\in2_sel[3:0] 4'0001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'100110 + assign { } { } + assign $1\in2_sel[3:0] 4'0011 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'100111 + assign { } { } + assign $1\in2_sel[3:0] 4'0011 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'101100 + assign { } { } + assign $1\in2_sel[3:0] 4'0011 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'101101 + assign { } { } + assign $1\in2_sel[3:0] 4'0011 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'100100 + assign { } { } + assign $1\in2_sel[3:0] 4'0011 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'100101 + assign { } { } + assign $1\in2_sel[3:0] 4'0011 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'001000 + assign { } { } + assign $1\in2_sel[3:0] 4'0011 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'000010 + assign { } { } + assign $1\in2_sel[3:0] 4'0011 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'000011 + assign { } { } + assign $1\in2_sel[3:0] 4'0011 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'011010 + assign { } { } + assign $1\in2_sel[3:0] 4'0010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'011011 + assign { } { } + assign $1\in2_sel[3:0] 4'0100 + case + assign $1\in2_sel[3:0] 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch$1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 32'000000---------------0100000000- + assign { } { } + assign $2\in2_sel[3:0] 4'0000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1610612736 + assign { } { } + assign $2\in2_sel[3:0] 4'0000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 32'000001---------------0000000011- + assign { } { } + assign $2\in2_sel[3:0] 4'0000 + case + assign $2\in2_sel[3:0] $1\in2_sel[3:0] + end + sync always + update \in2_sel $0\in2_sel[3:0] + end + attribute \src "issuer_ls180.v:67672.3-67813.6" + process $proc$issuer_ls180.v:67672$3476 + assign { } { } + assign { } { } + assign { } { } + assign $0\in3_sel[1:0] $2\in3_sel[1:0] + attribute \src "issuer_ls180.v:67673.5-67673.29" + switch \initial + attribute \src "issuer_ls180.v:67673.9-67673.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'010011 + assign { } { } + assign $1\in3_sel[1:0] \dec19_dec19_in3_sel + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'011110 + assign { } { } + assign $1\in3_sel[1:0] \dec30_dec30_in3_sel + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\in3_sel[1:0] \dec31_dec31_in3_sel + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'111010 + assign { } { } + assign $1\in3_sel[1:0] \dec58_dec58_in3_sel + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'111110 + assign { } { } + assign $1\in3_sel[1:0] \dec62_dec62_in3_sel + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'001100 + assign { } { } + assign $1\in3_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'001101 + assign { } { } + assign $1\in3_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'001110 + assign { } { } + assign $1\in3_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'001111 + assign { } { } + assign $1\in3_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'010001 + assign { } { } + assign $1\in3_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'011100 + assign { } { } + assign $1\in3_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'011101 + assign { } { } + assign $1\in3_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'010010 + assign { } { } + assign $1\in3_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'010000 + assign { } { } + assign $1\in3_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'001011 + assign { } { } + assign $1\in3_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'001010 + assign { } { } + assign $1\in3_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'100010 + assign { } { } + assign $1\in3_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'100011 + assign { } { } + assign $1\in3_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'101010 + assign { } { } + assign $1\in3_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'101011 + assign { } { } + assign $1\in3_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'101000 + assign { } { } + assign $1\in3_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'101001 + assign { } { } + assign $1\in3_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'100000 + assign { } { } + assign $1\in3_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'100001 + assign { } { } + assign $1\in3_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'000111 + assign { } { } + assign $1\in3_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'011000 + assign { } { } + assign $1\in3_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'011001 + assign { } { } + assign $1\in3_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'010100 + assign { } { } + assign $1\in3_sel[1:0] 2'01 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'010101 + assign { } { } + assign $1\in3_sel[1:0] 2'01 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'010111 + assign { } { } + assign $1\in3_sel[1:0] 2'01 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'100110 + assign { } { } + assign $1\in3_sel[1:0] 2'01 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'100111 + assign { } { } + assign $1\in3_sel[1:0] 2'01 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'101100 + assign { } { } + assign $1\in3_sel[1:0] 2'01 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'101101 + assign { } { } + assign $1\in3_sel[1:0] 2'01 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'100100 + assign { } { } + assign $1\in3_sel[1:0] 2'01 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'100101 + assign { } { } + assign $1\in3_sel[1:0] 2'01 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'001000 + assign { } { } + assign $1\in3_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'000010 + assign { } { } + assign $1\in3_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'000011 + assign { } { } + assign $1\in3_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'011010 + assign { } { } + assign $1\in3_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'011011 + assign { } { } + assign $1\in3_sel[1:0] 2'00 + case + assign $1\in3_sel[1:0] 2'00 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch$1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 32'000000---------------0100000000- + assign { } { } + assign $2\in3_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1610612736 + assign { } { } + assign $2\in3_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 32'000001---------------0000000011- + assign { } { } + assign $2\in3_sel[1:0] 2'00 + case + assign $2\in3_sel[1:0] $1\in3_sel[1:0] + end + sync always + update \in3_sel $0\in3_sel[1:0] + end + attribute \src "issuer_ls180.v:67814.3-67955.6" + process $proc$issuer_ls180.v:67814$3477 + assign { } { } + assign { } { } + assign { } { } + assign $0\out_sel[1:0] $2\out_sel[1:0] + attribute \src "issuer_ls180.v:67815.5-67815.29" + switch \initial + attribute \src "issuer_ls180.v:67815.9-67815.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'010011 + assign { } { } + assign $1\out_sel[1:0] \dec19_dec19_out_sel + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'011110 + assign { } { } + assign $1\out_sel[1:0] \dec30_dec30_out_sel + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\out_sel[1:0] \dec31_dec31_out_sel + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'111010 + assign { } { } + assign $1\out_sel[1:0] \dec58_dec58_out_sel + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'111110 + assign { } { } + assign $1\out_sel[1:0] \dec62_dec62_out_sel + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'001100 + assign { } { } + assign $1\out_sel[1:0] 2'01 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'001101 + assign { } { } + assign $1\out_sel[1:0] 2'01 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'001110 + assign { } { } + assign $1\out_sel[1:0] 2'01 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'001111 + assign { } { } + assign $1\out_sel[1:0] 2'01 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'010001 + assign { } { } + assign $1\out_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'011100 + assign { } { } + assign $1\out_sel[1:0] 2'10 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'011101 + assign { } { } + assign $1\out_sel[1:0] 2'10 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'010010 + assign { } { } + assign $1\out_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'010000 + assign { } { } + assign $1\out_sel[1:0] 2'11 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'001011 + assign { } { } + assign $1\out_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'001010 + assign { } { } + assign $1\out_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'100010 + assign { } { } + assign $1\out_sel[1:0] 2'01 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'100011 + assign { } { } + assign $1\out_sel[1:0] 2'01 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'101010 + assign { } { } + assign $1\out_sel[1:0] 2'01 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'101011 + assign { } { } + assign $1\out_sel[1:0] 2'01 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'101000 + assign { } { } + assign $1\out_sel[1:0] 2'01 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'101001 + assign { } { } + assign $1\out_sel[1:0] 2'01 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'100000 + assign { } { } + assign $1\out_sel[1:0] 2'01 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'100001 + assign { } { } + assign $1\out_sel[1:0] 2'01 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'000111 + assign { } { } + assign $1\out_sel[1:0] 2'01 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'011000 + assign { } { } + assign $1\out_sel[1:0] 2'10 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'011001 + assign { } { } + assign $1\out_sel[1:0] 2'10 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'010100 + assign { } { } + assign $1\out_sel[1:0] 2'10 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'010101 + assign { } { } + assign $1\out_sel[1:0] 2'10 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'010111 + assign { } { } + assign $1\out_sel[1:0] 2'10 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'100110 + assign { } { } + assign $1\out_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'100111 + assign { } { } + assign $1\out_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'101100 + assign { } { } + assign $1\out_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'101101 + assign { } { } + assign $1\out_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'100100 + assign { } { } + assign $1\out_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'100101 + assign { } { } + assign $1\out_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'001000 + assign { } { } + assign $1\out_sel[1:0] 2'01 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'000010 + assign { } { } + assign $1\out_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'000011 + assign { } { } + assign $1\out_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'011010 + assign { } { } + assign $1\out_sel[1:0] 2'10 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'011011 + assign { } { } + assign $1\out_sel[1:0] 2'10 + case + assign $1\out_sel[1:0] 2'00 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch$1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 32'000000---------------0100000000- + assign { } { } + assign $2\out_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1610612736 + assign { } { } + assign $2\out_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 32'000001---------------0000000011- + assign { } { } + assign $2\out_sel[1:0] 2'01 + case + assign $2\out_sel[1:0] $1\out_sel[1:0] + end + sync always + update \out_sel $0\out_sel[1:0] + end + attribute \src "issuer_ls180.v:67956.3-68097.6" + process $proc$issuer_ls180.v:67956$3478 + assign { } { } + assign { } { } + assign { } { } + assign $0\cr_in[2:0] $2\cr_in[2:0] + attribute \src "issuer_ls180.v:67957.5-67957.29" + switch \initial + attribute \src "issuer_ls180.v:67957.9-67957.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'010011 + assign { } { } + assign $1\cr_in[2:0] \dec19_dec19_cr_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'011110 + assign { } { } + assign $1\cr_in[2:0] \dec30_dec30_cr_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\cr_in[2:0] \dec31_dec31_cr_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'111010 + assign { } { } + assign $1\cr_in[2:0] \dec58_dec58_cr_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'111110 + assign { } { } + assign $1\cr_in[2:0] \dec62_dec62_cr_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'001100 + assign { } { } + assign $1\cr_in[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'001101 + assign { } { } + assign $1\cr_in[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'001110 + assign { } { } + assign $1\cr_in[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'001111 + assign { } { } + assign $1\cr_in[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'010001 + assign { } { } + assign $1\cr_in[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'011100 + assign { } { } + assign $1\cr_in[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'011101 + assign { } { } + assign $1\cr_in[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'010010 + assign { } { } + assign $1\cr_in[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'010000 + assign { } { } + assign $1\cr_in[2:0] 3'010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'001011 + assign { } { } + assign $1\cr_in[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'001010 + assign { } { } + assign $1\cr_in[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'100010 + assign { } { } + assign $1\cr_in[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'100011 + assign { } { } + assign $1\cr_in[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'101010 + assign { } { } + assign $1\cr_in[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'101011 + assign { } { } + assign $1\cr_in[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'101000 + assign { } { } + assign $1\cr_in[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'101001 + assign { } { } + assign $1\cr_in[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'100000 + assign { } { } + assign $1\cr_in[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'100001 + assign { } { } + assign $1\cr_in[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'000111 + assign { } { } + assign $1\cr_in[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'011000 + assign { } { } + assign $1\cr_in[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'011001 + assign { } { } + assign $1\cr_in[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'010100 + assign { } { } + assign $1\cr_in[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'010101 + assign { } { } + assign $1\cr_in[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'010111 + assign { } { } + assign $1\cr_in[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'100110 + assign { } { } + assign $1\cr_in[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'100111 + assign { } { } + assign $1\cr_in[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'101100 + assign { } { } + assign $1\cr_in[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'101101 + assign { } { } + assign $1\cr_in[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'100100 + assign { } { } + assign $1\cr_in[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'100101 + assign { } { } + assign $1\cr_in[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'001000 + assign { } { } + assign $1\cr_in[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'000010 + assign { } { } + assign $1\cr_in[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'000011 + assign { } { } + assign $1\cr_in[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'011010 + assign { } { } + assign $1\cr_in[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'011011 + assign { } { } + assign $1\cr_in[2:0] 3'000 + case + assign $1\cr_in[2:0] 3'000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch$1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 32'000000---------------0100000000- + assign { } { } + assign $2\cr_in[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1610612736 + assign { } { } + assign $2\cr_in[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 32'000001---------------0000000011- + assign { } { } + assign $2\cr_in[2:0] 3'000 + case + assign $2\cr_in[2:0] $1\cr_in[2:0] + end + sync always + update \cr_in $0\cr_in[2:0] + end + attribute \src "issuer_ls180.v:68098.3-68239.6" + process $proc$issuer_ls180.v:68098$3479 + assign { } { } + assign { } { } + assign { } { } + assign $0\cr_out[2:0] $2\cr_out[2:0] + attribute \src "issuer_ls180.v:68099.5-68099.29" + switch \initial + attribute \src "issuer_ls180.v:68099.9-68099.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'010011 + assign { } { } + assign $1\cr_out[2:0] \dec19_dec19_cr_out + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'011110 + assign { } { } + assign $1\cr_out[2:0] \dec30_dec30_cr_out + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\cr_out[2:0] \dec31_dec31_cr_out + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'111010 + assign { } { } + assign $1\cr_out[2:0] \dec58_dec58_cr_out + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'111110 + assign { } { } + assign $1\cr_out[2:0] \dec62_dec62_cr_out + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'001100 + assign { } { } + assign $1\cr_out[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'001101 + assign { } { } + assign $1\cr_out[2:0] 3'001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'001110 + assign { } { } + assign $1\cr_out[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'001111 + assign { } { } + assign $1\cr_out[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'010001 + assign { } { } + assign $1\cr_out[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'011100 + assign { } { } + assign $1\cr_out[2:0] 3'001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'011101 + assign { } { } + assign $1\cr_out[2:0] 3'001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'010010 + assign { } { } + assign $1\cr_out[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'010000 + assign { } { } + assign $1\cr_out[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'001011 + assign { } { } + assign $1\cr_out[2:0] 3'010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'001010 + assign { } { } + assign $1\cr_out[2:0] 3'010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'100010 + assign { } { } + assign $1\cr_out[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'100011 + assign { } { } + assign $1\cr_out[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'101010 + assign { } { } + assign $1\cr_out[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'101011 + assign { } { } + assign $1\cr_out[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'101000 + assign { } { } + assign $1\cr_out[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'101001 + assign { } { } + assign $1\cr_out[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'100000 + assign { } { } + assign $1\cr_out[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'100001 + assign { } { } + assign $1\cr_out[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'000111 + assign { } { } + assign $1\cr_out[2:0] 3'001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'011000 + assign { } { } + assign $1\cr_out[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'011001 + assign { } { } + assign $1\cr_out[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'010100 + assign { } { } + assign $1\cr_out[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'010101 + assign { } { } + assign $1\cr_out[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'010111 + assign { } { } + assign $1\cr_out[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'100110 + assign { } { } + assign $1\cr_out[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'100111 + assign { } { } + assign $1\cr_out[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'101100 + assign { } { } + assign $1\cr_out[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'101101 + assign { } { } + assign $1\cr_out[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'100100 + assign { } { } + assign $1\cr_out[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'100101 + assign { } { } + assign $1\cr_out[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'001000 + assign { } { } + assign $1\cr_out[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'000010 + assign { } { } + assign $1\cr_out[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'000011 + assign { } { } + assign $1\cr_out[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'011010 + assign { } { } + assign $1\cr_out[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'011011 + assign { } { } + assign $1\cr_out[2:0] 3'000 + case + assign $1\cr_out[2:0] 3'000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch$1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 32'000000---------------0100000000- + assign { } { } + assign $2\cr_out[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1610612736 + assign { } { } + assign $2\cr_out[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 32'000001---------------0000000011- + assign { } { } + assign $2\cr_out[2:0] 3'000 + case + assign $2\cr_out[2:0] $1\cr_out[2:0] + end + sync always + update \cr_out $0\cr_out[2:0] + end + attribute \src "issuer_ls180.v:68240.3-68381.6" + process $proc$issuer_ls180.v:68240$3480 + assign { } { } + assign { } { } + assign { } { } + assign $0\ldst_len[3:0] $2\ldst_len[3:0] + attribute \src "issuer_ls180.v:68241.5-68241.29" + switch \initial + attribute \src "issuer_ls180.v:68241.9-68241.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'010011 + assign { } { } + assign $1\ldst_len[3:0] \dec19_dec19_ldst_len + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'011110 + assign { } { } + assign $1\ldst_len[3:0] \dec30_dec30_ldst_len + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\ldst_len[3:0] \dec31_dec31_ldst_len + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'111010 + assign { } { } + assign $1\ldst_len[3:0] \dec58_dec58_ldst_len + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'111110 + assign { } { } + assign $1\ldst_len[3:0] \dec62_dec62_ldst_len + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'001100 + assign { } { } + assign $1\ldst_len[3:0] 4'0000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'001101 + assign { } { } + assign $1\ldst_len[3:0] 4'0000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'001110 + assign { } { } + assign $1\ldst_len[3:0] 4'0000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'001111 + assign { } { } + assign $1\ldst_len[3:0] 4'0000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'010001 + assign { } { } + assign $1\ldst_len[3:0] 4'0000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'011100 + assign { } { } + assign $1\ldst_len[3:0] 4'0000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'011101 + assign { } { } + assign $1\ldst_len[3:0] 4'0000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'010010 + assign { } { } + assign $1\ldst_len[3:0] 4'0000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'010000 + assign { } { } + assign $1\ldst_len[3:0] 4'0000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'001011 + assign { } { } + assign $1\ldst_len[3:0] 4'0000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'001010 + assign { } { } + assign $1\ldst_len[3:0] 4'0000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'100010 + assign { } { } + assign $1\ldst_len[3:0] 4'0001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'100011 + assign { } { } + assign $1\ldst_len[3:0] 4'0001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'101010 + assign { } { } + assign $1\ldst_len[3:0] 4'0010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'101011 + assign { } { } + assign $1\ldst_len[3:0] 4'0010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'101000 + assign { } { } + assign $1\ldst_len[3:0] 4'0010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'101001 + assign { } { } + assign $1\ldst_len[3:0] 4'0010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'100000 + assign { } { } + assign $1\ldst_len[3:0] 4'0100 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'100001 + assign { } { } + assign $1\ldst_len[3:0] 4'0100 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'000111 + assign { } { } + assign $1\ldst_len[3:0] 4'0000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'011000 + assign { } { } + assign $1\ldst_len[3:0] 4'0000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'011001 + assign { } { } + assign $1\ldst_len[3:0] 4'0000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'010100 + assign { } { } + assign $1\ldst_len[3:0] 4'0000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'010101 + assign { } { } + assign $1\ldst_len[3:0] 4'0000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'010111 + assign { } { } + assign $1\ldst_len[3:0] 4'0000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'100110 + assign { } { } + assign $1\ldst_len[3:0] 4'0001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'100111 + assign { } { } + assign $1\ldst_len[3:0] 4'0001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'101100 + assign { } { } + assign $1\ldst_len[3:0] 4'0010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'101101 + assign { } { } + assign $1\ldst_len[3:0] 4'0010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'100100 + assign { } { } + assign $1\ldst_len[3:0] 4'0100 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'100101 + assign { } { } + assign $1\ldst_len[3:0] 4'0100 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'001000 + assign { } { } + assign $1\ldst_len[3:0] 4'0000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'000010 + assign { } { } + assign $1\ldst_len[3:0] 4'0000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'000011 + assign { } { } + assign $1\ldst_len[3:0] 4'0000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'011010 + assign { } { } + assign $1\ldst_len[3:0] 4'0000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'011011 + assign { } { } + assign $1\ldst_len[3:0] 4'0000 + case + assign $1\ldst_len[3:0] 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch$1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 32'000000---------------0100000000- + assign { } { } + assign $2\ldst_len[3:0] 4'0000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1610612736 + assign { } { } + assign $2\ldst_len[3:0] 4'0000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 32'000001---------------0000000011- + assign { } { } + assign $2\ldst_len[3:0] 4'0000 + case + assign $2\ldst_len[3:0] $1\ldst_len[3:0] + end + sync always + update \ldst_len $0\ldst_len[3:0] + end + attribute \src "issuer_ls180.v:68382.3-68523.6" + process $proc$issuer_ls180.v:68382$3481 + assign { } { } + assign { } { } + assign { } { } + assign $0\upd[1:0] $2\upd[1:0] + attribute \src "issuer_ls180.v:68383.5-68383.29" + switch \initial + attribute \src "issuer_ls180.v:68383.9-68383.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'010011 + assign { } { } + assign $1\upd[1:0] \dec19_dec19_upd + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'011110 + assign { } { } + assign $1\upd[1:0] \dec30_dec30_upd + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\upd[1:0] \dec31_dec31_upd + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'111010 + assign { } { } + assign $1\upd[1:0] \dec58_dec58_upd + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'111110 + assign { } { } + assign $1\upd[1:0] \dec62_dec62_upd + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'001100 + assign { } { } + assign $1\upd[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'001101 + assign { } { } + assign $1\upd[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'001110 + assign { } { } + assign $1\upd[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'001111 + assign { } { } + assign $1\upd[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'010001 + assign { } { } + assign $1\upd[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'011100 + assign { } { } + assign $1\upd[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'011101 + assign { } { } + assign $1\upd[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'010010 + assign { } { } + assign $1\upd[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'010000 + assign { } { } + assign $1\upd[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'001011 + assign { } { } + assign $1\upd[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'001010 + assign { } { } + assign $1\upd[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'100010 + assign { } { } + assign $1\upd[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'100011 + assign { } { } + assign $1\upd[1:0] 2'01 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'101010 + assign { } { } + assign $1\upd[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'101011 + assign { } { } + assign $1\upd[1:0] 2'01 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'101000 + assign { } { } + assign $1\upd[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'101001 + assign { } { } + assign $1\upd[1:0] 2'01 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'100000 + assign { } { } + assign $1\upd[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'100001 + assign { } { } + assign $1\upd[1:0] 2'01 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'000111 + assign { } { } + assign $1\upd[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'011000 + assign { } { } + assign $1\upd[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'011001 + assign { } { } + assign $1\upd[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'010100 + assign { } { } + assign $1\upd[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'010101 + assign { } { } + assign $1\upd[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'010111 + assign { } { } + assign $1\upd[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'100110 + assign { } { } + assign $1\upd[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'100111 + assign { } { } + assign $1\upd[1:0] 2'01 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'101100 + assign { } { } + assign $1\upd[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'101101 + assign { } { } + assign $1\upd[1:0] 2'01 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'100100 + assign { } { } + assign $1\upd[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'100101 + assign { } { } + assign $1\upd[1:0] 2'01 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'001000 + assign { } { } + assign $1\upd[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'000010 + assign { } { } + assign $1\upd[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'000011 + assign { } { } + assign $1\upd[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'011010 + assign { } { } + assign $1\upd[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'011011 + assign { } { } + assign $1\upd[1:0] 2'00 + case + assign $1\upd[1:0] 2'00 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch$1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 32'000000---------------0100000000- + assign { } { } + assign $2\upd[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1610612736 + assign { } { } + assign $2\upd[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 32'000001---------------0000000011- + assign { } { } + assign $2\upd[1:0] 2'00 + case + assign $2\upd[1:0] $1\upd[1:0] + end + sync always + update \upd $0\upd[1:0] + end + attribute \src "issuer_ls180.v:68524.3-68665.6" + process $proc$issuer_ls180.v:68524$3482 + assign { } { } + assign { } { } + assign { } { } + assign $0\rc_sel[1:0] $2\rc_sel[1:0] + attribute \src "issuer_ls180.v:68525.5-68525.29" + switch \initial + attribute \src "issuer_ls180.v:68525.9-68525.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'010011 + assign { } { } + assign $1\rc_sel[1:0] \dec19_dec19_rc_sel + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'011110 + assign { } { } + assign $1\rc_sel[1:0] \dec30_dec30_rc_sel + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\rc_sel[1:0] \dec31_dec31_rc_sel + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'111010 + assign { } { } + assign $1\rc_sel[1:0] \dec58_dec58_rc_sel + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'111110 + assign { } { } + assign $1\rc_sel[1:0] \dec62_dec62_rc_sel + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'001100 + assign { } { } + assign $1\rc_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'001101 + assign { } { } + assign $1\rc_sel[1:0] 2'01 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'001110 + assign { } { } + assign $1\rc_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'001111 + assign { } { } + assign $1\rc_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'010001 + assign { } { } + assign $1\rc_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'011100 + assign { } { } + assign $1\rc_sel[1:0] 2'01 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'011101 + assign { } { } + assign $1\rc_sel[1:0] 2'01 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'010010 + assign { } { } + assign $1\rc_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'010000 + assign { } { } + assign $1\rc_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'001011 + assign { } { } + assign $1\rc_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'001010 + assign { } { } + assign $1\rc_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'100010 + assign { } { } + assign $1\rc_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'100011 + assign { } { } + assign $1\rc_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'101010 + assign { } { } + assign $1\rc_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'101011 + assign { } { } + assign $1\rc_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'101000 + assign { } { } + assign $1\rc_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'101001 + assign { } { } + assign $1\rc_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'100000 + assign { } { } + assign $1\rc_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'100001 + assign { } { } + assign $1\rc_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'000111 + assign { } { } + assign $1\rc_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'011000 + assign { } { } + assign $1\rc_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'011001 + assign { } { } + assign $1\rc_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'010100 + assign { } { } + assign $1\rc_sel[1:0] 2'10 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'010101 + assign { } { } + assign $1\rc_sel[1:0] 2'10 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'010111 + assign { } { } + assign $1\rc_sel[1:0] 2'10 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'100110 + assign { } { } + assign $1\rc_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'100111 + assign { } { } + assign $1\rc_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'101100 + assign { } { } + assign $1\rc_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'101101 + assign { } { } + assign $1\rc_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'100100 + assign { } { } + assign $1\rc_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'100101 + assign { } { } + assign $1\rc_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'001000 + assign { } { } + assign $1\rc_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'000010 + assign { } { } + assign $1\rc_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'000011 + assign { } { } + assign $1\rc_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'011010 + assign { } { } + assign $1\rc_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'011011 + assign { } { } + assign $1\rc_sel[1:0] 2'00 + case + assign $1\rc_sel[1:0] 2'00 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch$1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 32'000000---------------0100000000- + assign { } { } + assign $2\rc_sel[1:0] 2'10 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1610612736 + assign { } { } + assign $2\rc_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 32'000001---------------0000000011- + assign { } { } + assign $2\rc_sel[1:0] 2'00 + case + assign $2\rc_sel[1:0] $1\rc_sel[1:0] + end + sync always + update \rc_sel $0\rc_sel[1:0] + end + attribute \src "issuer_ls180.v:68666.3-68807.6" + process $proc$issuer_ls180.v:68666$3483 + assign { } { } + assign { } { } + assign { } { } + assign $0\cry_in[1:0] $2\cry_in[1:0] + attribute \src "issuer_ls180.v:68667.5-68667.29" + switch \initial + attribute \src "issuer_ls180.v:68667.9-68667.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'010011 + assign { } { } + assign $1\cry_in[1:0] \dec19_dec19_cry_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'011110 + assign { } { } + assign $1\cry_in[1:0] \dec30_dec30_cry_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\cry_in[1:0] \dec31_dec31_cry_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'111010 + assign { } { } + assign $1\cry_in[1:0] \dec58_dec58_cry_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'111110 + assign { } { } + assign $1\cry_in[1:0] \dec62_dec62_cry_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'001100 + assign { } { } + assign $1\cry_in[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'001101 + assign { } { } + assign $1\cry_in[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'001110 + assign { } { } + assign $1\cry_in[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'001111 + assign { } { } + assign $1\cry_in[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'010001 + assign { } { } + assign $1\cry_in[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'011100 + assign { } { } + assign $1\cry_in[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'011101 + assign { } { } + assign $1\cry_in[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'010010 + assign { } { } + assign $1\cry_in[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'010000 + assign { } { } + assign $1\cry_in[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'001011 + assign { } { } + assign $1\cry_in[1:0] 2'01 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'001010 + assign { } { } + assign $1\cry_in[1:0] 2'01 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'100010 + assign { } { } + assign $1\cry_in[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'100011 + assign { } { } + assign $1\cry_in[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'101010 + assign { } { } + assign $1\cry_in[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'101011 + assign { } { } + assign $1\cry_in[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'101000 + assign { } { } + assign $1\cry_in[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'101001 + assign { } { } + assign $1\cry_in[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'100000 + assign { } { } + assign $1\cry_in[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'100001 + assign { } { } + assign $1\cry_in[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'000111 + assign { } { } + assign $1\cry_in[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'011000 + assign { } { } + assign $1\cry_in[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'011001 + assign { } { } + assign $1\cry_in[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'010100 + assign { } { } + assign $1\cry_in[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'010101 + assign { } { } + assign $1\cry_in[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'010111 + assign { } { } + assign $1\cry_in[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'100110 + assign { } { } + assign $1\cry_in[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'100111 + assign { } { } + assign $1\cry_in[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'101100 + assign { } { } + assign $1\cry_in[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'101101 + assign { } { } + assign $1\cry_in[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'100100 + assign { } { } + assign $1\cry_in[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'100101 + assign { } { } + assign $1\cry_in[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'001000 + assign { } { } + assign $1\cry_in[1:0] 2'01 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'000010 + assign { } { } + assign $1\cry_in[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'000011 + assign { } { } + assign $1\cry_in[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'011010 + assign { } { } + assign $1\cry_in[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'011011 + assign { } { } + assign $1\cry_in[1:0] 2'00 + case + assign $1\cry_in[1:0] 2'00 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch$1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 32'000000---------------0100000000- + assign { } { } + assign $2\cry_in[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1610612736 + assign { } { } + assign $2\cry_in[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 32'000001---------------0000000011- + assign { } { } + assign $2\cry_in[1:0] 2'00 + case + assign $2\cry_in[1:0] $1\cry_in[1:0] + end + sync always + update \cry_in $0\cry_in[1:0] + end + attribute \src "issuer_ls180.v:68808.3-68949.6" + process $proc$issuer_ls180.v:68808$3484 + assign { } { } + assign { } { } + assign { } { } + assign $0\inv_a[0:0] $2\inv_a[0:0] + attribute \src "issuer_ls180.v:68809.5-68809.29" + switch \initial + attribute \src "issuer_ls180.v:68809.9-68809.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'010011 + assign { } { } + assign $1\inv_a[0:0] \dec19_dec19_inv_a + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'011110 + assign { } { } + assign $1\inv_a[0:0] \dec30_dec30_inv_a + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\inv_a[0:0] \dec31_dec31_inv_a + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'111010 + assign { } { } + assign $1\inv_a[0:0] \dec58_dec58_inv_a + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'111110 + assign { } { } + assign $1\inv_a[0:0] \dec62_dec62_inv_a + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'001100 + assign { } { } + assign $1\inv_a[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'001101 + assign { } { } + assign $1\inv_a[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'001110 + assign { } { } + assign $1\inv_a[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'001111 + assign { } { } + assign $1\inv_a[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'010001 + assign { } { } + assign $1\inv_a[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'011100 + assign { } { } + assign $1\inv_a[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'011101 + assign { } { } + assign $1\inv_a[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'010010 + assign { } { } + assign $1\inv_a[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'010000 + assign { } { } + assign $1\inv_a[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'001011 + assign { } { } + assign $1\inv_a[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'001010 + assign { } { } + assign $1\inv_a[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'100010 + assign { } { } + assign $1\inv_a[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'100011 + assign { } { } + assign $1\inv_a[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'101010 + assign { } { } + assign $1\inv_a[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'101011 + assign { } { } + assign $1\inv_a[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'101000 + assign { } { } + assign $1\inv_a[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'101001 + assign { } { } + assign $1\inv_a[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'100000 + assign { } { } + assign $1\inv_a[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'100001 + assign { } { } + assign $1\inv_a[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'000111 + assign { } { } + assign $1\inv_a[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'011000 + assign { } { } + assign $1\inv_a[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'011001 + assign { } { } + assign $1\inv_a[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'010100 + assign { } { } + assign $1\inv_a[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'010101 + assign { } { } + assign $1\inv_a[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'010111 + assign { } { } + assign $1\inv_a[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'100110 + assign { } { } + assign $1\inv_a[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'100111 + assign { } { } + assign $1\inv_a[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'101100 + assign { } { } + assign $1\inv_a[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'101101 + assign { } { } + assign $1\inv_a[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'100100 + assign { } { } + assign $1\inv_a[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'100101 + assign { } { } + assign $1\inv_a[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'001000 + assign { } { } + assign $1\inv_a[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'000010 + assign { } { } + assign $1\inv_a[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'000011 + assign { } { } + assign $1\inv_a[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'011010 + assign { } { } + assign $1\inv_a[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'011011 + assign { } { } + assign $1\inv_a[0:0] 1'0 + case + assign $1\inv_a[0:0] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch$1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 32'000000---------------0100000000- + assign { } { } + assign $2\inv_a[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1610612736 + assign { } { } + assign $2\inv_a[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 32'000001---------------0000000011- + assign { } { } + assign $2\inv_a[0:0] 1'0 + case + assign $2\inv_a[0:0] $1\inv_a[0:0] + end + sync always + update \inv_a $0\inv_a[0:0] + end + attribute \src "issuer_ls180.v:68950.3-69091.6" + process $proc$issuer_ls180.v:68950$3485 + assign { } { } + assign { } { } + assign { } { } + assign $0\inv_out[0:0] $2\inv_out[0:0] + attribute \src "issuer_ls180.v:68951.5-68951.29" + switch \initial + attribute \src "issuer_ls180.v:68951.9-68951.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'010011 + assign { } { } + assign $1\inv_out[0:0] \dec19_dec19_inv_out + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'011110 + assign { } { } + assign $1\inv_out[0:0] \dec30_dec30_inv_out + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\inv_out[0:0] \dec31_dec31_inv_out + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'111010 + assign { } { } + assign $1\inv_out[0:0] \dec58_dec58_inv_out + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'111110 + assign { } { } + assign $1\inv_out[0:0] \dec62_dec62_inv_out + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'001100 + assign { } { } + assign $1\inv_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'001101 + assign { } { } + assign $1\inv_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'001110 + assign { } { } + assign $1\inv_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'001111 + assign { } { } + assign $1\inv_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'010001 + assign { } { } + assign $1\inv_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'011100 + assign { } { } + assign $1\inv_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'011101 + assign { } { } + assign $1\inv_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'010010 + assign { } { } + assign $1\inv_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'010000 + assign { } { } + assign $1\inv_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'001011 + assign { } { } + assign $1\inv_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'001010 + assign { } { } + assign $1\inv_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'100010 + assign { } { } + assign $1\inv_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'100011 + assign { } { } + assign $1\inv_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'101010 + assign { } { } + assign $1\inv_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'101011 + assign { } { } + assign $1\inv_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'101000 + assign { } { } + assign $1\inv_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'101001 + assign { } { } + assign $1\inv_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'100000 + assign { } { } + assign $1\inv_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'100001 + assign { } { } + assign $1\inv_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'000111 + assign { } { } + assign $1\inv_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'011000 + assign { } { } + assign $1\inv_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'011001 + assign { } { } + assign $1\inv_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'010100 + assign { } { } + assign $1\inv_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'010101 + assign { } { } + assign $1\inv_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'010111 + assign { } { } + assign $1\inv_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'100110 + assign { } { } + assign $1\inv_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'100111 + assign { } { } + assign $1\inv_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'101100 + assign { } { } + assign $1\inv_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'101101 + assign { } { } + assign $1\inv_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'100100 + assign { } { } + assign $1\inv_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'100101 + assign { } { } + assign $1\inv_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'001000 + assign { } { } + assign $1\inv_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'000010 + assign { } { } + assign $1\inv_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'000011 + assign { } { } + assign $1\inv_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'011010 + assign { } { } + assign $1\inv_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'011011 + assign { } { } + assign $1\inv_out[0:0] 1'0 + case + assign $1\inv_out[0:0] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch$1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 32'000000---------------0100000000- + assign { } { } + assign $2\inv_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1610612736 + assign { } { } + assign $2\inv_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 32'000001---------------0000000011- + assign { } { } + assign $2\inv_out[0:0] 1'0 + case + assign $2\inv_out[0:0] $1\inv_out[0:0] + end + sync always + update \inv_out $0\inv_out[0:0] + end + attribute \src "issuer_ls180.v:69092.3-69233.6" + process $proc$issuer_ls180.v:69092$3486 + assign { } { } + assign { } { } + assign { } { } + assign $0\cry_out[0:0] $2\cry_out[0:0] + attribute \src "issuer_ls180.v:69093.5-69093.29" + switch \initial + attribute \src "issuer_ls180.v:69093.9-69093.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'010011 + assign { } { } + assign $1\cry_out[0:0] \dec19_dec19_cry_out + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'011110 + assign { } { } + assign $1\cry_out[0:0] \dec30_dec30_cry_out + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\cry_out[0:0] \dec31_dec31_cry_out + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'111010 + assign { } { } + assign $1\cry_out[0:0] \dec58_dec58_cry_out + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'111110 + assign { } { } + assign $1\cry_out[0:0] \dec62_dec62_cry_out + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'001100 + assign { } { } + assign $1\cry_out[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'001101 + assign { } { } + assign $1\cry_out[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'001110 + assign { } { } + assign $1\cry_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'001111 + assign { } { } + assign $1\cry_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'010001 + assign { } { } + assign $1\cry_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'011100 + assign { } { } + assign $1\cry_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'011101 + assign { } { } + assign $1\cry_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'010010 + assign { } { } + assign $1\cry_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'010000 + assign { } { } + assign $1\cry_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'001011 + assign { } { } + assign $1\cry_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'001010 + assign { } { } + assign $1\cry_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'100010 + assign { } { } + assign $1\cry_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'100011 + assign { } { } + assign $1\cry_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'101010 + assign { } { } + assign $1\cry_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'101011 + assign { } { } + assign $1\cry_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'101000 + assign { } { } + assign $1\cry_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'101001 + assign { } { } + assign $1\cry_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'100000 + assign { } { } + assign $1\cry_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'100001 + assign { } { } + assign $1\cry_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'000111 + assign { } { } + assign $1\cry_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'011000 + assign { } { } + assign $1\cry_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'011001 + assign { } { } + assign $1\cry_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'010100 + assign { } { } + assign $1\cry_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'010101 + assign { } { } + assign $1\cry_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'010111 + assign { } { } + assign $1\cry_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'100110 + assign { } { } + assign $1\cry_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'100111 + assign { } { } + assign $1\cry_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'101100 + assign { } { } + assign $1\cry_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'101101 + assign { } { } + assign $1\cry_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'100100 + assign { } { } + assign $1\cry_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'100101 + assign { } { } + assign $1\cry_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'001000 + assign { } { } + assign $1\cry_out[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'000010 + assign { } { } + assign $1\cry_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'000011 + assign { } { } + assign $1\cry_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'011010 + assign { } { } + assign $1\cry_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'011011 + assign { } { } + assign $1\cry_out[0:0] 1'0 + case + assign $1\cry_out[0:0] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch$1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 32'000000---------------0100000000- + assign { } { } + assign $2\cry_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1610612736 + assign { } { } + assign $2\cry_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 32'000001---------------0000000011- + assign { } { } + assign $2\cry_out[0:0] 1'0 + case + assign $2\cry_out[0:0] $1\cry_out[0:0] + end + sync always + update \cry_out $0\cry_out[0:0] + end + attribute \src "issuer_ls180.v:69234.3-69375.6" + process $proc$issuer_ls180.v:69234$3487 + assign { } { } + assign { } { } + assign { } { } + assign $0\br[0:0] $2\br[0:0] + attribute \src "issuer_ls180.v:69235.5-69235.29" + switch \initial + attribute \src "issuer_ls180.v:69235.9-69235.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'010011 + assign { } { } + assign $1\br[0:0] \dec19_dec19_br + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'011110 + assign { } { } + assign $1\br[0:0] \dec30_dec30_br + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\br[0:0] \dec31_dec31_br + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'111010 + assign { } { } + assign $1\br[0:0] \dec58_dec58_br + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'111110 + assign { } { } + assign $1\br[0:0] \dec62_dec62_br + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'001100 + assign { } { } + assign $1\br[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'001101 + assign { } { } + assign $1\br[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'001110 + assign { } { } + assign $1\br[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'001111 + assign { } { } + assign $1\br[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'010001 + assign { } { } + assign $1\br[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'011100 + assign { } { } + assign $1\br[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'011101 + assign { } { } + assign $1\br[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'010010 + assign { } { } + assign $1\br[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'010000 + assign { } { } + assign $1\br[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'001011 + assign { } { } + assign $1\br[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'001010 + assign { } { } + assign $1\br[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'100010 + assign { } { } + assign $1\br[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'100011 + assign { } { } + assign $1\br[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'101010 + assign { } { } + assign $1\br[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'101011 + assign { } { } + assign $1\br[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'101000 + assign { } { } + assign $1\br[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'101001 + assign { } { } + assign $1\br[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'100000 + assign { } { } + assign $1\br[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'100001 + assign { } { } + assign $1\br[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'000111 + assign { } { } + assign $1\br[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'011000 + assign { } { } + assign $1\br[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'011001 + assign { } { } + assign $1\br[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'010100 + assign { } { } + assign $1\br[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'010101 + assign { } { } + assign $1\br[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'010111 + assign { } { } + assign $1\br[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'100110 + assign { } { } + assign $1\br[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'100111 + assign { } { } + assign $1\br[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'101100 + assign { } { } + assign $1\br[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'101101 + assign { } { } + assign $1\br[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'100100 + assign { } { } + assign $1\br[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'100101 + assign { } { } + assign $1\br[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'001000 + assign { } { } + assign $1\br[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'000010 + assign { } { } + assign $1\br[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'000011 + assign { } { } + assign $1\br[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'011010 + assign { } { } + assign $1\br[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'011011 + assign { } { } + assign $1\br[0:0] 1'0 + case + assign $1\br[0:0] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch$1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 32'000000---------------0100000000- + assign { } { } + assign $2\br[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1610612736 + assign { } { } + assign $2\br[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 32'000001---------------0000000011- + assign { } { } + assign $2\br[0:0] 1'0 + case + assign $2\br[0:0] $1\br[0:0] + end + sync always + update \br $0\br[0:0] + end + attribute \src "issuer_ls180.v:69376.3-69517.6" + process $proc$issuer_ls180.v:69376$3488 + assign { } { } + assign { } { } + assign { } { } + assign $0\sgn_ext[0:0] $2\sgn_ext[0:0] + attribute \src "issuer_ls180.v:69377.5-69377.29" + switch \initial + attribute \src "issuer_ls180.v:69377.9-69377.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'010011 + assign { } { } + assign $1\sgn_ext[0:0] \dec19_dec19_sgn_ext + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'011110 + assign { } { } + assign $1\sgn_ext[0:0] \dec30_dec30_sgn_ext + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\sgn_ext[0:0] \dec31_dec31_sgn_ext + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'111010 + assign { } { } + assign $1\sgn_ext[0:0] \dec58_dec58_sgn_ext + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'111110 + assign { } { } + assign $1\sgn_ext[0:0] \dec62_dec62_sgn_ext + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'001100 + assign { } { } + assign $1\sgn_ext[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'001101 + assign { } { } + assign $1\sgn_ext[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'001110 + assign { } { } + assign $1\sgn_ext[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'001111 + assign { } { } + assign $1\sgn_ext[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'010001 + assign { } { } + assign $1\sgn_ext[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'011100 + assign { } { } + assign $1\sgn_ext[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'011101 + assign { } { } + assign $1\sgn_ext[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'010010 + assign { } { } + assign $1\sgn_ext[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'010000 + assign { } { } + assign $1\sgn_ext[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'001011 + assign { } { } + assign $1\sgn_ext[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'001010 + assign { } { } + assign $1\sgn_ext[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'100010 + assign { } { } + assign $1\sgn_ext[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'100011 + assign { } { } + assign $1\sgn_ext[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'101010 + assign { } { } + assign $1\sgn_ext[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'101011 + assign { } { } + assign $1\sgn_ext[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'101000 + assign { } { } + assign $1\sgn_ext[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'101001 + assign { } { } + assign $1\sgn_ext[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'100000 + assign { } { } + assign $1\sgn_ext[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'100001 + assign { } { } + assign $1\sgn_ext[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'000111 + assign { } { } + assign $1\sgn_ext[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'011000 + assign { } { } + assign $1\sgn_ext[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'011001 + assign { } { } + assign $1\sgn_ext[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'010100 + assign { } { } + assign $1\sgn_ext[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'010101 + assign { } { } + assign $1\sgn_ext[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'010111 + assign { } { } + assign $1\sgn_ext[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'100110 + assign { } { } + assign $1\sgn_ext[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'100111 + assign { } { } + assign $1\sgn_ext[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'101100 + assign { } { } + assign $1\sgn_ext[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'101101 + assign { } { } + assign $1\sgn_ext[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'100100 + assign { } { } + assign $1\sgn_ext[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'100101 + assign { } { } + assign $1\sgn_ext[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'001000 + assign { } { } + assign $1\sgn_ext[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'000010 + assign { } { } + assign $1\sgn_ext[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'000011 + assign { } { } + assign $1\sgn_ext[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'011010 + assign { } { } + assign $1\sgn_ext[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'011011 + assign { } { } + assign $1\sgn_ext[0:0] 1'0 + case + assign $1\sgn_ext[0:0] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch$1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 32'000000---------------0100000000- + assign { } { } + assign $2\sgn_ext[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1610612736 + assign { } { } + assign $2\sgn_ext[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 32'000001---------------0000000011- + assign { } { } + assign $2\sgn_ext[0:0] 1'0 + case + assign $2\sgn_ext[0:0] $1\sgn_ext[0:0] + end + sync always + update \sgn_ext $0\sgn_ext[0:0] + end + attribute \src "issuer_ls180.v:69518.3-69659.6" + process $proc$issuer_ls180.v:69518$3489 + assign { } { } + assign { } { } + assign { } { } + assign $0\rsrv[0:0] $2\rsrv[0:0] + attribute \src "issuer_ls180.v:69519.5-69519.29" + switch \initial + attribute \src "issuer_ls180.v:69519.9-69519.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'010011 + assign { } { } + assign $1\rsrv[0:0] \dec19_dec19_rsrv + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'011110 + assign { } { } + assign $1\rsrv[0:0] \dec30_dec30_rsrv + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\rsrv[0:0] \dec31_dec31_rsrv + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'111010 + assign { } { } + assign $1\rsrv[0:0] \dec58_dec58_rsrv + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'111110 + assign { } { } + assign $1\rsrv[0:0] \dec62_dec62_rsrv + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'001100 + assign { } { } + assign $1\rsrv[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'001101 + assign { } { } + assign $1\rsrv[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'001110 + assign { } { } + assign $1\rsrv[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'001111 + assign { } { } + assign $1\rsrv[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'010001 + assign { } { } + assign $1\rsrv[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'011100 + assign { } { } + assign $1\rsrv[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'011101 + assign { } { } + assign $1\rsrv[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'010010 + assign { } { } + assign $1\rsrv[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'010000 + assign { } { } + assign $1\rsrv[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'001011 + assign { } { } + assign $1\rsrv[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'001010 + assign { } { } + assign $1\rsrv[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'100010 + assign { } { } + assign $1\rsrv[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'100011 + assign { } { } + assign $1\rsrv[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'101010 + assign { } { } + assign $1\rsrv[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'101011 + assign { } { } + assign $1\rsrv[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'101000 + assign { } { } + assign $1\rsrv[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'101001 + assign { } { } + assign $1\rsrv[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'100000 + assign { } { } + assign $1\rsrv[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'100001 + assign { } { } + assign $1\rsrv[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'000111 + assign { } { } + assign $1\rsrv[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'011000 + assign { } { } + assign $1\rsrv[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'011001 + assign { } { } + assign $1\rsrv[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'010100 + assign { } { } + assign $1\rsrv[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'010101 + assign { } { } + assign $1\rsrv[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'010111 + assign { } { } + assign $1\rsrv[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'100110 + assign { } { } + assign $1\rsrv[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'100111 + assign { } { } + assign $1\rsrv[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'101100 + assign { } { } + assign $1\rsrv[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'101101 + assign { } { } + assign $1\rsrv[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'100100 + assign { } { } + assign $1\rsrv[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'100101 + assign { } { } + assign $1\rsrv[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'001000 + assign { } { } + assign $1\rsrv[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'000010 + assign { } { } + assign $1\rsrv[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'000011 + assign { } { } + assign $1\rsrv[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'011010 + assign { } { } + assign $1\rsrv[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'011011 + assign { } { } + assign $1\rsrv[0:0] 1'0 + case + assign $1\rsrv[0:0] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch$1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 32'000000---------------0100000000- + assign { } { } + assign $2\rsrv[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1610612736 + assign { } { } + assign $2\rsrv[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 32'000001---------------0000000011- + assign { } { } + assign $2\rsrv[0:0] 1'0 + case + assign $2\rsrv[0:0] $1\rsrv[0:0] + end + sync always + update \rsrv $0\rsrv[0:0] + end + attribute \src "issuer_ls180.v:69660.3-69801.6" + process $proc$issuer_ls180.v:69660$3490 + assign { } { } + assign { } { } + assign { } { } + assign $0\is_32b[0:0] $2\is_32b[0:0] + attribute \src "issuer_ls180.v:69661.5-69661.29" + switch \initial + attribute \src "issuer_ls180.v:69661.9-69661.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'010011 + assign { } { } + assign $1\is_32b[0:0] \dec19_dec19_is_32b + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'011110 + assign { } { } + assign $1\is_32b[0:0] \dec30_dec30_is_32b + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\is_32b[0:0] \dec31_dec31_is_32b + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'111010 + assign { } { } + assign $1\is_32b[0:0] \dec58_dec58_is_32b + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'111110 + assign { } { } + assign $1\is_32b[0:0] \dec62_dec62_is_32b + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'001100 + assign { } { } + assign $1\is_32b[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'001101 + assign { } { } + assign $1\is_32b[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'001110 + assign { } { } + assign $1\is_32b[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'001111 + assign { } { } + assign $1\is_32b[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'010001 + assign { } { } + assign $1\is_32b[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'011100 + assign { } { } + assign $1\is_32b[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'011101 + assign { } { } + assign $1\is_32b[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'010010 + assign { } { } + assign $1\is_32b[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'010000 + assign { } { } + assign $1\is_32b[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'001011 + assign { } { } + assign $1\is_32b[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'001010 + assign { } { } + assign $1\is_32b[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'100010 + assign { } { } + assign $1\is_32b[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'100011 + assign { } { } + assign $1\is_32b[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'101010 + assign { } { } + assign $1\is_32b[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'101011 + assign { } { } + assign $1\is_32b[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'101000 + assign { } { } + assign $1\is_32b[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'101001 + assign { } { } + assign $1\is_32b[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'100000 + assign { } { } + assign $1\is_32b[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'100001 + assign { } { } + assign $1\is_32b[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'000111 + assign { } { } + assign $1\is_32b[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'011000 + assign { } { } + assign $1\is_32b[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'011001 + assign { } { } + assign $1\is_32b[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'010100 + assign { } { } + assign $1\is_32b[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'010101 + assign { } { } + assign $1\is_32b[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'010111 + assign { } { } + assign $1\is_32b[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'100110 + assign { } { } + assign $1\is_32b[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'100111 + assign { } { } + assign $1\is_32b[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'101100 + assign { } { } + assign $1\is_32b[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'101101 + assign { } { } + assign $1\is_32b[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'100100 + assign { } { } + assign $1\is_32b[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'100101 + assign { } { } + assign $1\is_32b[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'001000 + assign { } { } + assign $1\is_32b[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'000010 + assign { } { } + assign $1\is_32b[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'000011 + assign { } { } + assign $1\is_32b[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'011010 + assign { } { } + assign $1\is_32b[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'011011 + assign { } { } + assign $1\is_32b[0:0] 1'0 + case + assign $1\is_32b[0:0] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch$1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 32'000000---------------0100000000- + assign { } { } + assign $2\is_32b[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1610612736 + assign { } { } + assign $2\is_32b[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 32'000001---------------0000000011- + assign { } { } + assign $2\is_32b[0:0] 1'0 + case + assign $2\is_32b[0:0] $1\is_32b[0:0] + end + sync always + update \is_32b $0\is_32b[0:0] + end + attribute \src "issuer_ls180.v:69802.3-69943.6" + process $proc$issuer_ls180.v:69802$3491 + assign { } { } + assign { } { } + assign { } { } + assign $0\sgn[0:0] $2\sgn[0:0] + attribute \src "issuer_ls180.v:69803.5-69803.29" + switch \initial + attribute \src "issuer_ls180.v:69803.9-69803.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'010011 + assign { } { } + assign $1\sgn[0:0] \dec19_dec19_sgn + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'011110 + assign { } { } + assign $1\sgn[0:0] \dec30_dec30_sgn + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\sgn[0:0] \dec31_dec31_sgn + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'111010 + assign { } { } + assign $1\sgn[0:0] \dec58_dec58_sgn + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'111110 + assign { } { } + assign $1\sgn[0:0] \dec62_dec62_sgn + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'001100 + assign { } { } + assign $1\sgn[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'001101 + assign { } { } + assign $1\sgn[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'001110 + assign { } { } + assign $1\sgn[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'001111 + assign { } { } + assign $1\sgn[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'010001 + assign { } { } + assign $1\sgn[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'011100 + assign { } { } + assign $1\sgn[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'011101 + assign { } { } + assign $1\sgn[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'010010 + assign { } { } + assign $1\sgn[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'010000 + assign { } { } + assign $1\sgn[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'001011 + assign { } { } + assign $1\sgn[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'001010 + assign { } { } + assign $1\sgn[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'100010 + assign { } { } + assign $1\sgn[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'100011 + assign { } { } + assign $1\sgn[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'101010 + assign { } { } + assign $1\sgn[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'101011 + assign { } { } + assign $1\sgn[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'101000 + assign { } { } + assign $1\sgn[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'101001 + assign { } { } + assign $1\sgn[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'100000 + assign { } { } + assign $1\sgn[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'100001 + assign { } { } + assign $1\sgn[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'000111 + assign { } { } + assign $1\sgn[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'011000 + assign { } { } + assign $1\sgn[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'011001 + assign { } { } + assign $1\sgn[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'010100 + assign { } { } + assign $1\sgn[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'010101 + assign { } { } + assign $1\sgn[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'010111 + assign { } { } + assign $1\sgn[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'100110 + assign { } { } + assign $1\sgn[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'100111 + assign { } { } + assign $1\sgn[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'101100 + assign { } { } + assign $1\sgn[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'101101 + assign { } { } + assign $1\sgn[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'100100 + assign { } { } + assign $1\sgn[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'100101 + assign { } { } + assign $1\sgn[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'001000 + assign { } { } + assign $1\sgn[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'000010 + assign { } { } + assign $1\sgn[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'000011 + assign { } { } + assign $1\sgn[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'011010 + assign { } { } + assign $1\sgn[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'011011 + assign { } { } + assign $1\sgn[0:0] 1'0 + case + assign $1\sgn[0:0] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch$1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 32'000000---------------0100000000- + assign { } { } + assign $2\sgn[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1610612736 + assign { } { } + assign $2\sgn[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 32'000001---------------0000000011- + assign { } { } + assign $2\sgn[0:0] 1'0 + case + assign $2\sgn[0:0] $1\sgn[0:0] + end + sync always + update \sgn $0\sgn[0:0] + end + attribute \src "issuer_ls180.v:69944.3-70085.6" + process $proc$issuer_ls180.v:69944$3492 + assign { } { } + assign { } { } + assign { } { } + assign $0\lk[0:0] $2\lk[0:0] + attribute \src "issuer_ls180.v:69945.5-69945.29" + switch \initial + attribute \src "issuer_ls180.v:69945.9-69945.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'010011 + assign { } { } + assign $1\lk[0:0] \dec19_dec19_lk + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'011110 + assign { } { } + assign $1\lk[0:0] \dec30_dec30_lk + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\lk[0:0] \dec31_dec31_lk + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'111010 + assign { } { } + assign $1\lk[0:0] \dec58_dec58_lk + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'111110 + assign { } { } + assign $1\lk[0:0] \dec62_dec62_lk + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'001100 + assign { } { } + assign $1\lk[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'001101 + assign { } { } + assign $1\lk[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'001110 + assign { } { } + assign $1\lk[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'001111 + assign { } { } + assign $1\lk[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'010001 + assign { } { } + assign $1\lk[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'011100 + assign { } { } + assign $1\lk[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'011101 + assign { } { } + assign $1\lk[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'010010 + assign { } { } + assign $1\lk[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'010000 + assign { } { } + assign $1\lk[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'001011 + assign { } { } + assign $1\lk[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'001010 + assign { } { } + assign $1\lk[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'100010 + assign { } { } + assign $1\lk[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'100011 + assign { } { } + assign $1\lk[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'101010 + assign { } { } + assign $1\lk[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'101011 + assign { } { } + assign $1\lk[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'101000 + assign { } { } + assign $1\lk[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'101001 + assign { } { } + assign $1\lk[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'100000 + assign { } { } + assign $1\lk[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'100001 + assign { } { } + assign $1\lk[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'000111 + assign { } { } + assign $1\lk[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'011000 + assign { } { } + assign $1\lk[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'011001 + assign { } { } + assign $1\lk[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'010100 + assign { } { } + assign $1\lk[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'010101 + assign { } { } + assign $1\lk[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'010111 + assign { } { } + assign $1\lk[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'100110 + assign { } { } + assign $1\lk[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'100111 + assign { } { } + assign $1\lk[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'101100 + assign { } { } + assign $1\lk[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'101101 + assign { } { } + assign $1\lk[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'100100 + assign { } { } + assign $1\lk[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'100101 + assign { } { } + assign $1\lk[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'001000 + assign { } { } + assign $1\lk[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'000010 + assign { } { } + assign $1\lk[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'000011 + assign { } { } + assign $1\lk[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'011010 + assign { } { } + assign $1\lk[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'011011 + assign { } { } + assign $1\lk[0:0] 1'0 + case + assign $1\lk[0:0] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch$1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 32'000000---------------0100000000- + assign { } { } + assign $2\lk[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1610612736 + assign { } { } + assign $2\lk[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 32'000001---------------0000000011- + assign { } { } + assign $2\lk[0:0] 1'0 + case + assign $2\lk[0:0] $1\lk[0:0] + end + sync always + update \lk $0\lk[0:0] + end + attribute \src "issuer_ls180.v:70086.3-70227.6" + process $proc$issuer_ls180.v:70086$3493 + assign { } { } + assign { } { } + assign { } { } + assign $0\sgl_pipe[0:0] $2\sgl_pipe[0:0] + attribute \src "issuer_ls180.v:70087.5-70087.29" + switch \initial + attribute \src "issuer_ls180.v:70087.9-70087.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'010011 + assign { } { } + assign $1\sgl_pipe[0:0] \dec19_dec19_sgl_pipe + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'011110 + assign { } { } + assign $1\sgl_pipe[0:0] \dec30_dec30_sgl_pipe + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\sgl_pipe[0:0] \dec31_dec31_sgl_pipe + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'111010 + assign { } { } + assign $1\sgl_pipe[0:0] \dec58_dec58_sgl_pipe + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'111110 + assign { } { } + assign $1\sgl_pipe[0:0] \dec62_dec62_sgl_pipe + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'001100 + assign { } { } + assign $1\sgl_pipe[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'001101 + assign { } { } + assign $1\sgl_pipe[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'001110 + assign { } { } + assign $1\sgl_pipe[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'001111 + assign { } { } + assign $1\sgl_pipe[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'010001 + assign { } { } + assign $1\sgl_pipe[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'011100 + assign { } { } + assign $1\sgl_pipe[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'011101 + assign { } { } + assign $1\sgl_pipe[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'010010 + assign { } { } + assign $1\sgl_pipe[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'010000 + assign { } { } + assign $1\sgl_pipe[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'001011 + assign { } { } + assign $1\sgl_pipe[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'001010 + assign { } { } + assign $1\sgl_pipe[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'100010 + assign { } { } + assign $1\sgl_pipe[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'100011 + assign { } { } + assign $1\sgl_pipe[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'101010 + assign { } { } + assign $1\sgl_pipe[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'101011 + assign { } { } + assign $1\sgl_pipe[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'101000 + assign { } { } + assign $1\sgl_pipe[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'101001 + assign { } { } + assign $1\sgl_pipe[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'100000 + assign { } { } + assign $1\sgl_pipe[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'100001 + assign { } { } + assign $1\sgl_pipe[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'000111 + assign { } { } + assign $1\sgl_pipe[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'011000 + assign { } { } + assign $1\sgl_pipe[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'011001 + assign { } { } + assign $1\sgl_pipe[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'010100 + assign { } { } + assign $1\sgl_pipe[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'010101 + assign { } { } + assign $1\sgl_pipe[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'010111 + assign { } { } + assign $1\sgl_pipe[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'100110 + assign { } { } + assign $1\sgl_pipe[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'100111 + assign { } { } + assign $1\sgl_pipe[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'101100 + assign { } { } + assign $1\sgl_pipe[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'101101 + assign { } { } + assign $1\sgl_pipe[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'100100 + assign { } { } + assign $1\sgl_pipe[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'100101 + assign { } { } + assign $1\sgl_pipe[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'001000 + assign { } { } + assign $1\sgl_pipe[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'000010 + assign { } { } + assign $1\sgl_pipe[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'000011 + assign { } { } + assign $1\sgl_pipe[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'011010 + assign { } { } + assign $1\sgl_pipe[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'011011 + assign { } { } + assign $1\sgl_pipe[0:0] 1'0 + case + assign $1\sgl_pipe[0:0] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch$1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 32'000000---------------0100000000- + assign { } { } + assign $2\sgl_pipe[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1610612736 + assign { } { } + assign $2\sgl_pipe[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 32'000001---------------0000000011- + assign { } { } + assign $2\sgl_pipe[0:0] 1'1 + case + assign $2\sgl_pipe[0:0] $1\sgl_pipe[0:0] + end + sync always + update \sgl_pipe $0\sgl_pipe[0:0] + end + attribute \src "issuer_ls180.v:70228.3-70369.6" + process $proc$issuer_ls180.v:70228$3494 + assign { } { } + assign { } { } + assign { } { } + assign $0\function_unit[11:0] $2\function_unit[11:0] + attribute \src "issuer_ls180.v:70229.5-70229.29" + switch \initial + attribute \src "issuer_ls180.v:70229.9-70229.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'010011 + assign { } { } + assign $1\function_unit[11:0] \dec19_dec19_function_unit + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'011110 + assign { } { } + assign $1\function_unit[11:0] \dec30_dec30_function_unit + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\function_unit[11:0] \dec31_dec31_function_unit + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'111010 + assign { } { } + assign $1\function_unit[11:0] \dec58_dec58_function_unit + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'111110 + assign { } { } + assign $1\function_unit[11:0] \dec62_dec62_function_unit + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'001100 + assign { } { } + assign $1\function_unit[11:0] 12'000000000010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'001101 + assign { } { } + assign $1\function_unit[11:0] 12'000000000010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'001110 + assign { } { } + assign $1\function_unit[11:0] 12'000000000010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'001111 + assign { } { } + assign $1\function_unit[11:0] 12'000000000010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'010001 + assign { } { } + assign $1\function_unit[11:0] 12'000010000000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'011100 + assign { } { } + assign $1\function_unit[11:0] 12'000000010000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'011101 + assign { } { } + assign $1\function_unit[11:0] 12'000000010000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'010010 + assign { } { } + assign $1\function_unit[11:0] 12'000000100000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'010000 + assign { } { } + assign $1\function_unit[11:0] 12'000000100000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'001011 + assign { } { } + assign $1\function_unit[11:0] 12'000000000010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'001010 + assign { } { } + assign $1\function_unit[11:0] 12'000000000010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'100010 + assign { } { } + assign $1\function_unit[11:0] 12'000000000100 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'100011 + assign { } { } + assign $1\function_unit[11:0] 12'000000000100 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'101010 + assign { } { } + assign $1\function_unit[11:0] 12'000000000100 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'101011 + assign { } { } + assign $1\function_unit[11:0] 12'000000000100 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'101000 + assign { } { } + assign $1\function_unit[11:0] 12'000000000100 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'101001 + assign { } { } + assign $1\function_unit[11:0] 12'000000000100 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'100000 + assign { } { } + assign $1\function_unit[11:0] 12'000000000100 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'100001 + assign { } { } + assign $1\function_unit[11:0] 12'000000000100 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'000111 + assign { } { } + assign $1\function_unit[11:0] 12'000100000000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'011000 + assign { } { } + assign $1\function_unit[11:0] 12'000000010000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'011001 + assign { } { } + assign $1\function_unit[11:0] 12'000000010000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'010100 + assign { } { } + assign $1\function_unit[11:0] 12'000000001000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'010101 + assign { } { } + assign $1\function_unit[11:0] 12'000000001000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'010111 + assign { } { } + assign $1\function_unit[11:0] 12'000000001000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'100110 + assign { } { } + assign $1\function_unit[11:0] 12'000000000100 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'100111 + assign { } { } + assign $1\function_unit[11:0] 12'000000000100 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'101100 + assign { } { } + assign $1\function_unit[11:0] 12'000000000100 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'101101 + assign { } { } + assign $1\function_unit[11:0] 12'000000000100 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'100100 + assign { } { } + assign $1\function_unit[11:0] 12'000000000100 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'100101 + assign { } { } + assign $1\function_unit[11:0] 12'000000000100 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'001000 + assign { } { } + assign $1\function_unit[11:0] 12'000000000010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'000010 + assign { } { } + assign $1\function_unit[11:0] 12'000010000000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'000011 + assign { } { } + assign $1\function_unit[11:0] 12'000010000000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'011010 + assign { } { } + assign $1\function_unit[11:0] 12'000000010000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'011011 + assign { } { } + assign $1\function_unit[11:0] 12'000000010000 + case + assign $1\function_unit[11:0] 12'000000000000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch$1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 32'000000---------------0100000000- + assign { } { } + assign $2\function_unit[11:0] 12'000000000000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1610612736 + assign { } { } + assign $2\function_unit[11:0] 12'000000000000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 32'000001---------------0000000011- + assign { } { } + assign $2\function_unit[11:0] 12'000000000000 + case + assign $2\function_unit[11:0] $1\function_unit[11:0] + end + sync always + update \function_unit $0\function_unit[11:0] + end + attribute \src "issuer_ls180.v:70370.3-70511.6" + process $proc$issuer_ls180.v:70370$3495 + assign { } { } + assign { } { } + assign { } { } + assign $0\internal_op[6:0] $2\internal_op[6:0] + attribute \src "issuer_ls180.v:70371.5-70371.29" + switch \initial + attribute \src "issuer_ls180.v:70371.9-70371.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'010011 + assign { } { } + assign $1\internal_op[6:0] \dec19_dec19_internal_op + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'011110 + assign { } { } + assign $1\internal_op[6:0] \dec30_dec30_internal_op + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\internal_op[6:0] \dec31_dec31_internal_op + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'111010 + assign { } { } + assign $1\internal_op[6:0] \dec58_dec58_internal_op + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'111110 + assign { } { } + assign $1\internal_op[6:0] \dec62_dec62_internal_op + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'001100 + assign { } { } + assign $1\internal_op[6:0] 7'0000010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'001101 + assign { } { } + assign $1\internal_op[6:0] 7'0000010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'001110 + assign { } { } + assign $1\internal_op[6:0] 7'0000010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'001111 + assign { } { } + assign $1\internal_op[6:0] 7'0000010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'010001 + assign { } { } + assign $1\internal_op[6:0] 7'1001001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'011100 + assign { } { } + assign $1\internal_op[6:0] 7'0000100 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'011101 + assign { } { } + assign $1\internal_op[6:0] 7'0000100 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'010010 + assign { } { } + assign $1\internal_op[6:0] 7'0000110 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'010000 + assign { } { } + assign $1\internal_op[6:0] 7'0000111 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'001011 + assign { } { } + assign $1\internal_op[6:0] 7'0001010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'001010 + assign { } { } + assign $1\internal_op[6:0] 7'0001010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'100010 + assign { } { } + assign $1\internal_op[6:0] 7'0100101 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'100011 + assign { } { } + assign $1\internal_op[6:0] 7'0100101 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'101010 + assign { } { } + assign $1\internal_op[6:0] 7'0100101 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'101011 + assign { } { } + assign $1\internal_op[6:0] 7'0100101 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'101000 + assign { } { } + assign $1\internal_op[6:0] 7'0100101 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'101001 + assign { } { } + assign $1\internal_op[6:0] 7'0100101 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'100000 + assign { } { } + assign $1\internal_op[6:0] 7'0100101 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'100001 + assign { } { } + assign $1\internal_op[6:0] 7'0100101 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'000111 + assign { } { } + assign $1\internal_op[6:0] 7'0110010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'011000 + assign { } { } + assign $1\internal_op[6:0] 7'0110101 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'011001 + assign { } { } + assign $1\internal_op[6:0] 7'0110101 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'010100 + assign { } { } + assign $1\internal_op[6:0] 7'0111000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'010101 + assign { } { } + assign $1\internal_op[6:0] 7'0111000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'010111 + assign { } { } + assign $1\internal_op[6:0] 7'0111000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'100110 + assign { } { } + assign $1\internal_op[6:0] 7'0100110 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'100111 + assign { } { } + assign $1\internal_op[6:0] 7'0100110 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'101100 + assign { } { } + assign $1\internal_op[6:0] 7'0100110 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'101101 + assign { } { } + assign $1\internal_op[6:0] 7'0100110 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'100100 + assign { } { } + assign $1\internal_op[6:0] 7'0100110 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'100101 + assign { } { } + assign $1\internal_op[6:0] 7'0100110 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'001000 + assign { } { } + assign $1\internal_op[6:0] 7'0000010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'000010 + assign { } { } + assign $1\internal_op[6:0] 7'0111111 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'000011 + assign { } { } + assign $1\internal_op[6:0] 7'0111111 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'011010 + assign { } { } + assign $1\internal_op[6:0] 7'1000011 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'011011 + assign { } { } + assign $1\internal_op[6:0] 7'1000011 + case + assign $1\internal_op[6:0] 7'0000000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch$1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 32'000000---------------0100000000- + assign { } { } + assign $2\internal_op[6:0] 7'0000101 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1610612736 + assign { } { } + assign $2\internal_op[6:0] 7'0000001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 32'000001---------------0000000011- + assign { } { } + assign $2\internal_op[6:0] 7'1000100 + case + assign $2\internal_op[6:0] $1\internal_op[6:0] + end + sync always + update \internal_op $0\internal_op[6:0] + end + attribute \src "issuer_ls180.v:70512.3-70653.6" + process $proc$issuer_ls180.v:70512$3496 + assign { } { } + assign { } { } + assign { } { } + assign $0\form[4:0] $2\form[4:0] + attribute \src "issuer_ls180.v:70513.5-70513.29" + switch \initial + attribute \src "issuer_ls180.v:70513.9-70513.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'010011 + assign { } { } + assign $1\form[4:0] \dec19_dec19_form + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'011110 + assign { } { } + assign $1\form[4:0] \dec30_dec30_form + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'011111 + assign { } { } + assign $1\form[4:0] \dec31_dec31_form + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'111010 + assign { } { } + assign $1\form[4:0] \dec58_dec58_form + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'111110 + assign { } { } + assign $1\form[4:0] \dec62_dec62_form + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'001100 + assign { } { } + assign $1\form[4:0] 5'00100 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'001101 + assign { } { } + assign $1\form[4:0] 5'00100 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'001110 + assign { } { } + assign $1\form[4:0] 5'00100 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'001111 + assign { } { } + assign $1\form[4:0] 5'00100 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'010001 + assign { } { } + assign $1\form[4:0] 5'00011 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'011100 + assign { } { } + assign $1\form[4:0] 5'00010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'011101 + assign { } { } + assign $1\form[4:0] 5'00010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'010010 + assign { } { } + assign $1\form[4:0] 5'00001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'010000 + assign { } { } + assign $1\form[4:0] 5'00010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'001011 + assign { } { } + assign $1\form[4:0] 5'00100 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'001010 + assign { } { } + assign $1\form[4:0] 5'00100 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'100010 + assign { } { } + assign $1\form[4:0] 5'00100 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'100011 + assign { } { } + assign $1\form[4:0] 5'00100 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'101010 + assign { } { } + assign $1\form[4:0] 5'00100 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'101011 + assign { } { } + assign $1\form[4:0] 5'00100 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'101000 + assign { } { } + assign $1\form[4:0] 5'00100 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'101001 + assign { } { } + assign $1\form[4:0] 5'00100 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'100000 + assign { } { } + assign $1\form[4:0] 5'00100 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'100001 + assign { } { } + assign $1\form[4:0] 5'00100 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'000111 + assign { } { } + assign $1\form[4:0] 5'00100 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'011000 + assign { } { } + assign $1\form[4:0] 5'00100 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'011001 + assign { } { } + assign $1\form[4:0] 5'00100 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'010100 + assign { } { } + assign $1\form[4:0] 5'10011 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'010101 + assign { } { } + assign $1\form[4:0] 5'10011 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'010111 + assign { } { } + assign $1\form[4:0] 5'10011 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'100110 + assign { } { } + assign $1\form[4:0] 5'00100 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'100111 + assign { } { } + assign $1\form[4:0] 5'00100 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'101100 + assign { } { } + assign $1\form[4:0] 5'00100 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'101101 + assign { } { } + assign $1\form[4:0] 5'00100 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'100100 + assign { } { } + assign $1\form[4:0] 5'00100 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'100101 + assign { } { } + assign $1\form[4:0] 5'00100 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'001000 + assign { } { } + assign $1\form[4:0] 5'00100 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'000010 + assign { } { } + assign $1\form[4:0] 5'00100 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'000011 + assign { } { } + assign $1\form[4:0] 5'00100 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'011010 + assign { } { } + assign $1\form[4:0] 5'00100 + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'011011 + assign { } { } + assign $1\form[4:0] 5'00100 + case + assign $1\form[4:0] 5'00000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch$1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 32'000000---------------0100000000- + assign { } { } + assign $2\form[4:0] 5'00000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1610612736 + assign { } { } + assign $2\form[4:0] 5'00100 + attribute \src "issuer_ls180.v:0.0-0.0" + case 32'000001---------------0000000011- + assign { } { } + assign $2\form[4:0] 5'00000 + case + assign $2\form[4:0] $1\form[4:0] + end + sync always + update \form $0\form[4:0] + end + connect \$2 $ternary$issuer_ls180.v:67113$3472_Y + connect \VC_XO \opcode_in [9:0] + connect \VC_VRT \opcode_in [25:21] + connect \VC_VRB \opcode_in [15:11] + connect \VC_VRA \opcode_in [20:16] + connect \VC_Rc \opcode_in [10] + connect \XS_XO \opcode_in [10:2] + connect \XS_sh { \opcode_in [1] \opcode_in [15:11] } + connect \XS_RS \opcode_in [25:21] + connect \XS_Rc \opcode_in [0] + connect \XS_RA \opcode_in [20:16] + connect \VA_XO \opcode_in [5:0] + connect \VA_VRT \opcode_in [25:21] + connect \VA_VRC \opcode_in [10:6] + connect \VA_VRB \opcode_in [15:11] + connect \VA_VRA \opcode_in [20:16] + connect \VA_SHB \opcode_in [9:6] + connect \VA_RT \opcode_in [25:21] + connect \VA_RC \opcode_in [10:6] + connect \VA_RB \opcode_in [15:11] + connect \VA_RA \opcode_in [20:16] + connect \TX_XO \opcode_in [6:1] + connect \TX_XBI \opcode_in [10:7] + connect \TX_UI \opcode_in [15:11] + connect \TX_RA \opcode_in [20:16] + connect \DQE_XO \opcode_in [1:0] + connect \DQE_RT \opcode_in [25:21] + connect \DQE_RA \opcode_in [20:16] + connect \XO_XO \opcode_in [9:1] + connect \XO_RT \opcode_in [25:21] + connect \XO_Rc \opcode_in [0] + connect \XO_RB \opcode_in [15:11] + connect \XO_RA \opcode_in [20:16] + connect \XO_OE \opcode_in [10] + connect \all_PO \opcode_in [31:26] + connect \all_OPCD \opcode_in [31:26] + connect \MD_XO \opcode_in [4:2] + connect \MD_sh { \opcode_in [1] \opcode_in [15:11] } + connect \MD_RS \opcode_in [25:21] + connect \MD_Rc \opcode_in [0] + connect \MD_RA \opcode_in [20:16] + connect \MD_me \opcode_in [10:5] + connect \MD_mb \opcode_in [10:5] + connect \M_SH \opcode_in [15:11] + connect \M_RS \opcode_in [25:21] + connect \M_Rc \opcode_in [0] + connect \M_RB \opcode_in [15:11] + connect \M_RA \opcode_in [20:16] + connect \M_ME \opcode_in [5:1] + connect \M_MB \opcode_in [10:6] + connect \SC_XO_1 \opcode_in [1:0] + connect \SC_XO \opcode_in [1] + connect \SC_LEV \opcode_in [11:5] + connect \MDS_XO \opcode_in [4:1] + connect \MDS_XBI_1 \opcode_in [10:7] + connect \MDS_XBI \opcode_in [10:7] + connect \MDS_RS \opcode_in [25:21] + connect \MDS_Rc \opcode_in [0] + connect \MDS_RB \opcode_in [15:11] + connect \MDS_RA \opcode_in [20:16] + connect \MDS_me \opcode_in [10:5] + connect \MDS_mb \opcode_in [10:5] + connect \MDS_IS \opcode_in [25:21] + connect \MDS_IB \opcode_in [15:11] + connect \Z23_XO \opcode_in [8:1] + connect \Z23_TE \opcode_in [20:16] + connect \Z23_RMC \opcode_in [10:9] + connect \Z23_Rc \opcode_in [0] + connect \Z23_R \opcode_in [16] + connect \Z23_FRTp \opcode_in [25:21] + connect \Z23_FRT \opcode_in [25:21] + connect \Z23_FRBp \opcode_in [15:11] + connect \Z23_FRB \opcode_in [15:11] + connect \Z23_FRAp \opcode_in [20:16] + connect \Z23_FRA \opcode_in [20:16] + connect \XFL_XO \opcode_in [10:1] + connect \XFL_W \opcode_in [16] + connect \XFL_Rc \opcode_in [0] + connect \XFL_L \opcode_in [25] + connect \XFL_FRB \opcode_in [15:11] + connect \XFL_FLM \opcode_in [24:17] + connect \VX_XO_1 \opcode_in [10:0] + connect \VX_XO { \opcode_in [10] \opcode_in [8:0] } + connect \VX_VRT \opcode_in [25:21] + connect \VX_VRB \opcode_in [15:11] + connect \VX_VRA \opcode_in [20:16] + connect \VX_UIM_3 \opcode_in [17:16] + connect \VX_UIM_2 \opcode_in [18:16] + connect \VX_UIM_1 \opcode_in [19:16] + connect \VX_UIM \opcode_in [20:16] + connect \VX_SIM \opcode_in [20:16] + connect \VX_RT \opcode_in [25:21] + connect \VX_RA \opcode_in [20:16] + connect \VX_PS \opcode_in [9] + connect \VX_EO \opcode_in [20:16] + connect \DS_XO \opcode_in [1:0] + connect \DS_VRT \opcode_in [25:21] + connect \DS_VRS \opcode_in [25:21] + connect \DS_RT \opcode_in [25:21] + connect \DS_RSp \opcode_in [25:21] + connect \DS_RS \opcode_in [25:21] + connect \DS_RA \opcode_in [20:16] + connect \DS_FRTp \opcode_in [25:21] + connect \DS_FRSp \opcode_in [25:21] + connect \DS_DS \opcode_in [15:2] + connect \DQ_XO \opcode_in [2:0] + connect \DQ_TX_T { \opcode_in [3] \opcode_in [25:21] } + connect \DQ_T \opcode_in [25:21] + connect \DQ_TX \opcode_in [3] + connect \DQ_SX_S { \opcode_in [3] \opcode_in [25:21] } + connect \DQ_S \opcode_in [25:21] + connect \DQ_SX \opcode_in [3] + connect \DQ_RTp \opcode_in [25:21] + connect \DQ_RA \opcode_in [20:16] + connect \DQ_PT \opcode_in [3:0] + connect \DQ_DQ \opcode_in [15:4] + connect \DX_XO \opcode_in [5:1] + connect \DX_RT \opcode_in [25:21] + connect \DX_d0_d1_d2 { \opcode_in [15:6] \opcode_in [20:16] \opcode_in [0] } + connect \DX_d2 \opcode_in [0] + connect \DX_d1 \opcode_in [20:16] + connect \DX_d0 \opcode_in [15:6] + connect \XFX_XO \opcode_in [10:1] + connect \XFX_SPR \opcode_in [20:11] + connect \XFX_RT \opcode_in [25:21] + connect \XFX_RS \opcode_in [25:21] + connect \XFX_FXM \opcode_in [19:12] + connect \XFX_DUIS \opcode_in [20:11] + connect \XFX_DUI \opcode_in [25:21] + connect \XFX_BHRBE \opcode_in [20:11] + connect \EVS_BFA \opcode_in [2:0] + connect \Z22_XO \opcode_in [9:1] + connect \Z22_SH \opcode_in [15:10] + connect \Z22_Rc \opcode_in [0] + connect \Z22_FRTp \opcode_in [25:21] + connect \Z22_FRT \opcode_in [25:21] + connect \Z22_FRAp \opcode_in [20:16] + connect \Z22_FRA \opcode_in [20:16] + connect \Z22_DGM \opcode_in [15:10] + connect \Z22_DCM \opcode_in [15:10] + connect \Z22_BF \opcode_in [25:23] + connect \XX2_XO_1 \opcode_in [10:2] + connect \XX2_XO { \opcode_in [10:7] \opcode_in [5:3] } + connect \XX2_UIM_1 \opcode_in [17:16] + connect \XX2_UIM \opcode_in [19:16] + connect \XX2_TX_T { \opcode_in [0] \opcode_in [25:21] } + connect \XX2_T \opcode_in [25:21] + connect \XX2_TX \opcode_in [0] + connect \XX2_RT \opcode_in [25:21] + connect \XX2_EO \opcode_in [20:16] + connect \XX2_DCMX \opcode_in [22:16] + connect \XX2_dc_dm_dx { \opcode_in [6] \opcode_in [2] \opcode_in [20:16] } + connect \XX2_dx \opcode_in [20:16] + connect \XX2_dm \opcode_in [2] + connect \XX2_dc \opcode_in [6] + connect \XX2_BX_B { \opcode_in [1] \opcode_in [15:11] } + connect \XX2_B \opcode_in [15:11] + connect \XX2_BX \opcode_in [1] + connect \XX2_BF \opcode_in [25:23] + connect \D_UI \opcode_in [15:0] + connect \D_TO \opcode_in [25:21] + connect \D_SI \opcode_in [15:0] + connect \D_RT \opcode_in [25:21] + connect \D_RS \opcode_in [25:21] + connect \D_RA \opcode_in [20:16] + connect \D_L \opcode_in [21] + connect \D_FRT \opcode_in [25:21] + connect \D_FRS \opcode_in [25:21] + connect \D_D \opcode_in [15:0] + connect \D_BF \opcode_in [25:23] + connect \A_XO \opcode_in [5:1] + connect \A_RT \opcode_in [25:21] + connect \A_Rc \opcode_in [0] + connect \A_RB \opcode_in [15:11] + connect \A_RA \opcode_in [20:16] + connect \A_FRT \opcode_in [25:21] + connect \A_FRC \opcode_in [10:6] + connect \A_FRB \opcode_in [15:11] + connect \A_FRA \opcode_in [20:16] + connect \A_BC \opcode_in [10:6] + connect \XL_XO \opcode_in [10:1] + connect \XL_S \opcode_in [11] + connect \XL_OC \opcode_in [25:11] + connect \XL_LK \opcode_in [0] + connect \XL_BT \opcode_in [25:21] + connect \XL_BO_1 \opcode_in [25:21] + connect \XL_BO \opcode_in [25:21] + connect \XL_BI \opcode_in [20:16] + connect \XL_BH \opcode_in [12:11] + connect \XL_BFA \opcode_in [20:18] + connect \XL_BF \opcode_in [25:23] + connect \XL_BB \opcode_in [15:11] + connect \XL_BA \opcode_in [20:16] + connect \XX4_XO \opcode_in [5:4] + connect \XX4_TX_T { \opcode_in [0] \opcode_in [25:21] } + connect \XX4_T \opcode_in [25:21] + connect \XX4_TX \opcode_in [0] + connect \XX4_CX_C { \opcode_in [3] \opcode_in [10:6] } + connect \XX4_C \opcode_in [10:6] + connect \XX4_CX \opcode_in [3] + connect \XX4_BX_B { \opcode_in [1] \opcode_in [15:11] } + connect \XX4_B \opcode_in [15:11] + connect \XX4_BX \opcode_in [1] + connect \XX4_AX_A { \opcode_in [2] \opcode_in [20:16] } + connect \XX4_A \opcode_in [20:16] + connect \XX4_AX \opcode_in [2] + connect \XX3_XO_2 \opcode_in [9:1] + connect \XX3_XO_1 \opcode_in [10:3] + connect \XX3_XO \opcode_in [10:7] + connect \XX3_TX_T { \opcode_in [0] \opcode_in [25:21] } + connect \XX3_T \opcode_in [25:21] + connect \XX3_TX \opcode_in [0] + connect \XX3_SHW \opcode_in [9:8] + connect \XX3_Rc \opcode_in [10] + connect \XX3_DM \opcode_in [9:8] + connect \XX3_BX_B { \opcode_in [1] \opcode_in [15:11] } + connect \XX3_B \opcode_in [15:11] + connect \XX3_BX \opcode_in [1] + connect \XX3_BF \opcode_in [25:23] + connect \XX3_AX_A { \opcode_in [2] \opcode_in [20:16] } + connect \XX3_A \opcode_in [20:16] + connect \XX3_AX \opcode_in [2] + connect \I_LK \opcode_in [0] + connect \I_LI \opcode_in [25:2] + connect \I_AA \opcode_in [1] + connect \B_LK \opcode_in [0] + connect \B_BO \opcode_in [25:21] + connect \B_BI \opcode_in [20:16] + connect \B_BD \opcode_in [15:2] + connect \B_AA \opcode_in [1] + connect \X_XO_1 \opcode_in [8:1] + connect \X_XO \opcode_in [10:1] + connect \X_WC \opcode_in [22:21] + connect \X_W \opcode_in [16] + connect \X_VRT \opcode_in [25:21] + connect \X_VRS \opcode_in [25:21] + connect \X_UIM \opcode_in [20:16] + connect \X_U \opcode_in [15:12] + connect \X_TX_T { \opcode_in [0] \opcode_in [25:21] } + connect \X_TX \opcode_in [0] + connect \X_TO \opcode_in [25:21] + connect \X_TH \opcode_in [25:21] + connect \X_TBR \opcode_in [20:11] + connect \X_T \opcode_in [25:21] + connect \X_SX_S { \opcode_in [0] \opcode_in [25:21] } + connect \X_SX \opcode_in [0] + connect \X_SR \opcode_in [19:16] + connect \X_SP \opcode_in [20:19] + connect \X_SI \opcode_in [15:11] + connect \X_SH \opcode_in [15:11] + connect \X_S \opcode_in [25:21] + connect \X_RTp \opcode_in [25:21] + connect \X_RT \opcode_in [25:21] + connect \X_RSp \opcode_in [25:21] + connect \X_RS \opcode_in [25:21] + connect \X_RO \opcode_in [0] + connect \X_RM \opcode_in [12:11] + connect \X_RIC \opcode_in [19:18] + connect \X_Rc \opcode_in [0] + connect \X_RB \opcode_in [15:11] + connect \X_RA \opcode_in [20:16] + connect \X_R_1 \opcode_in [16] + connect \X_R \opcode_in [21] + connect \X_PRS \opcode_in [17] + connect \X_NB \opcode_in [15:11] + connect \X_MO \opcode_in [25:21] + connect \X_L3 \opcode_in [17:16] + connect \X_L1 \opcode_in [16] + connect \X_L \opcode_in [21] + connect \X_L2 \opcode_in [22:21] + connect \X_IMM8 \opcode_in [18:11] + connect \X_IH \opcode_in [23:21] + connect \X_FRTp \opcode_in [25:21] + connect \X_FRT \opcode_in [25:21] + connect \X_FRSp \opcode_in [25:21] + connect \X_FRS \opcode_in [25:21] + connect \X_FRBp \opcode_in [15:11] + connect \X_FRB \opcode_in [15:11] + connect \X_FRAp \opcode_in [20:16] + connect \X_FRA \opcode_in [20:16] + connect \X_FC \opcode_in [15:11] + connect \X_EX \opcode_in [0] + connect \X_EO_1 \opcode_in [20:16] + connect \X_EO \opcode_in [20:19] + connect \X_E_1 \opcode_in [19:16] + connect \X_E \opcode_in [15] + connect \X_DRM \opcode_in [13:11] + connect \X_DCMX \opcode_in [22:16] + connect \X_CT \opcode_in [24:21] + connect \X_BO \opcode_in [25:21] + connect \X_BFA \opcode_in [20:18] + connect \X_BF \opcode_in [25:23] + connect \X_A \opcode_in [25] + connect \SPR \opcode_in [20:11] + connect \MB \opcode_in [10:6] + connect \ME \opcode_in [5:1] + connect \SH \opcode_in [15:11] + connect \BC \opcode_in [10:6] + connect \TO \opcode_in [25:21] + connect \DS \opcode_in [15:2] + connect \D \opcode_in [15:0] + connect \BH \opcode_in [12:11] + connect \BI \opcode_in [20:16] + connect \BO \opcode_in [25:21] + connect \FXM \opcode_in [19:12] + connect \BT \opcode_in [25:21] + connect \BA \opcode_in [20:16] + connect \BB \opcode_in [15:11] + connect \CR \opcode_in [10:1] + connect \BF \opcode_in [25:23] + connect \BD \opcode_in [15:2] + connect \OE \opcode_in [10] + connect \Rc \opcode_in [0] + connect \AA \opcode_in [1] + connect \LK \opcode_in [0] + connect \LI \opcode_in [25:2] + connect \ME32 \opcode_in [5:1] + connect \MB32 \opcode_in [10:6] + connect \sh { \opcode_in [1] \opcode_in [15:11] } + connect \SH32 \opcode_in [15:11] + connect \L \opcode_in [21] + connect \UI \opcode_in [15:0] + connect \SI \opcode_in [15:0] + connect \RB \opcode_in [15:11] + connect \RA \opcode_in [20:16] + connect \RT \opcode_in [25:21] + connect \RS \opcode_in [25:21] + connect \opcode_in \$2 + connect \opcode_switch$1 \opcode_in + connect \dec62_opcode_in \opcode_in + connect \dec58_opcode_in \opcode_in + connect \dec31_opcode_in \opcode_in + connect \dec30_opcode_in \opcode_in + connect \dec19_opcode_in \opcode_in + connect \opcode_switch \opcode_in [31:26] +end +attribute \src "issuer_ls180.v:70992.1-72499.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.dec2.dec.dec19" +attribute \generator "nMigen" +module \dec19 + attribute \src "issuer_ls180.v:71510.3-71561.6" + wire width 8 $0\dec19_asmcode[7:0] + attribute \src "issuer_ls180.v:71718.3-71769.6" + wire $0\dec19_br[0:0] + attribute \src "issuer_ls180.v:72394.3-72445.6" + wire width 3 $0\dec19_cr_in[2:0] + attribute \src "issuer_ls180.v:72446.3-72497.6" + wire width 3 $0\dec19_cr_out[2:0] + attribute \src "issuer_ls180.v:71458.3-71509.6" + wire width 2 $0\dec19_cry_in[1:0] + attribute \src "issuer_ls180.v:71666.3-71717.6" + wire $0\dec19_cry_out[0:0] + attribute \src "issuer_ls180.v:72134.3-72185.6" + wire width 5 $0\dec19_form[4:0] + attribute \src "issuer_ls180.v:71250.3-71301.6" + wire width 12 $0\dec19_function_unit[11:0] + attribute \src "issuer_ls180.v:72186.3-72237.6" + wire width 3 $0\dec19_in1_sel[2:0] + attribute \src "issuer_ls180.v:72238.3-72289.6" + wire width 4 $0\dec19_in2_sel[3:0] + attribute \src "issuer_ls180.v:72290.3-72341.6" + wire width 2 $0\dec19_in3_sel[1:0] + attribute \src "issuer_ls180.v:71822.3-71873.6" + wire width 7 $0\dec19_internal_op[6:0] + attribute \src "issuer_ls180.v:71562.3-71613.6" + wire $0\dec19_inv_a[0:0] + attribute \src "issuer_ls180.v:71614.3-71665.6" + wire $0\dec19_inv_out[0:0] + attribute \src "issuer_ls180.v:71926.3-71977.6" + wire $0\dec19_is_32b[0:0] + attribute \src "issuer_ls180.v:71302.3-71353.6" + wire width 4 $0\dec19_ldst_len[3:0] + attribute \src "issuer_ls180.v:72030.3-72081.6" + wire $0\dec19_lk[0:0] + attribute \src "issuer_ls180.v:72342.3-72393.6" + wire width 2 $0\dec19_out_sel[1:0] + attribute \src "issuer_ls180.v:71406.3-71457.6" + wire width 2 $0\dec19_rc_sel[1:0] + attribute \src "issuer_ls180.v:71874.3-71925.6" + wire $0\dec19_rsrv[0:0] + attribute \src "issuer_ls180.v:72082.3-72133.6" + wire $0\dec19_sgl_pipe[0:0] + attribute \src "issuer_ls180.v:71978.3-72029.6" + wire $0\dec19_sgn[0:0] + attribute \src "issuer_ls180.v:71770.3-71821.6" + wire $0\dec19_sgn_ext[0:0] + attribute \src "issuer_ls180.v:71354.3-71405.6" + wire width 2 $0\dec19_upd[1:0] + attribute \src "issuer_ls180.v:70993.7-70993.20" + wire $0\initial[0:0] + attribute \src "issuer_ls180.v:71510.3-71561.6" + wire width 8 $1\dec19_asmcode[7:0] + attribute \src "issuer_ls180.v:71718.3-71769.6" + wire $1\dec19_br[0:0] + attribute \src "issuer_ls180.v:72394.3-72445.6" + wire width 3 $1\dec19_cr_in[2:0] + attribute \src "issuer_ls180.v:72446.3-72497.6" + wire width 3 $1\dec19_cr_out[2:0] + attribute \src "issuer_ls180.v:71458.3-71509.6" + wire width 2 $1\dec19_cry_in[1:0] + attribute \src "issuer_ls180.v:71666.3-71717.6" + wire $1\dec19_cry_out[0:0] + attribute \src "issuer_ls180.v:72134.3-72185.6" + wire width 5 $1\dec19_form[4:0] + attribute \src "issuer_ls180.v:71250.3-71301.6" + wire width 12 $1\dec19_function_unit[11:0] + attribute \src "issuer_ls180.v:72186.3-72237.6" + wire width 3 $1\dec19_in1_sel[2:0] + attribute \src "issuer_ls180.v:72238.3-72289.6" + wire width 4 $1\dec19_in2_sel[3:0] + attribute \src "issuer_ls180.v:72290.3-72341.6" + wire width 2 $1\dec19_in3_sel[1:0] + attribute \src "issuer_ls180.v:71822.3-71873.6" + wire width 7 $1\dec19_internal_op[6:0] + attribute \src "issuer_ls180.v:71562.3-71613.6" + wire $1\dec19_inv_a[0:0] + attribute \src "issuer_ls180.v:71614.3-71665.6" + wire $1\dec19_inv_out[0:0] + attribute \src "issuer_ls180.v:71926.3-71977.6" + wire $1\dec19_is_32b[0:0] + attribute \src "issuer_ls180.v:71302.3-71353.6" + wire width 4 $1\dec19_ldst_len[3:0] + attribute \src "issuer_ls180.v:72030.3-72081.6" + wire $1\dec19_lk[0:0] + attribute \src "issuer_ls180.v:72342.3-72393.6" + wire width 2 $1\dec19_out_sel[1:0] + attribute \src "issuer_ls180.v:71406.3-71457.6" + wire width 2 $1\dec19_rc_sel[1:0] + attribute \src "issuer_ls180.v:71874.3-71925.6" + wire $1\dec19_rsrv[0:0] + attribute \src "issuer_ls180.v:72082.3-72133.6" + wire $1\dec19_sgl_pipe[0:0] + attribute \src "issuer_ls180.v:71978.3-72029.6" + wire $1\dec19_sgn[0:0] + attribute \src "issuer_ls180.v:71770.3-71821.6" + wire $1\dec19_sgn_ext[0:0] + attribute \src "issuer_ls180.v:71354.3-71405.6" + wire width 2 $1\dec19_upd[1:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 8 output 4 \dec19_asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 18 \dec19_br + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 9 \dec19_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 10 \dec19_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 14 \dec19_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 17 \dec19_cry_out + attribute \enum_base_type "Form" + attribute \enum_value_00000 "NONE" + attribute \enum_value_00001 "I" + attribute \enum_value_00010 "B" + attribute \enum_value_00011 "SC" + attribute \enum_value_00100 "D" + attribute \enum_value_00101 "DS" + attribute \enum_value_00110 "DQ" + attribute \enum_value_00111 "DX" + attribute \enum_value_01000 "X" + attribute \enum_value_01001 "XL" + attribute \enum_value_01010 "XFX" + attribute \enum_value_01011 "XFL" + attribute \enum_value_01100 "XX1" + attribute \enum_value_01101 "XX2" + attribute \enum_value_01110 "XX3" + attribute \enum_value_01111 "XX4" + attribute \enum_value_10000 "XS" + attribute \enum_value_10001 "XO" + attribute \enum_value_10010 "A" + attribute \enum_value_10011 "M" + attribute \enum_value_10100 "MD" + attribute \enum_value_10101 "MDS" + attribute \enum_value_10110 "VA" + attribute \enum_value_10111 "VC" + attribute \enum_value_11000 "VX" + attribute \enum_value_11001 "EVX" + attribute \enum_value_11010 "EVS" + attribute \enum_value_11011 "Z22" + attribute \enum_value_11100 "Z23" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 5 output 3 \dec19_form + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 12 output 1 \dec19_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 5 \dec19_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 output 6 \dec19_in2_sel + attribute \enum_base_type "In3Sel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RS" + attribute \enum_value_10 "RB" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 7 \dec19_in3_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 7 output 2 \dec19_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 15 \dec19_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 16 \dec19_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 21 \dec19_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 output 11 \dec19_ldst_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 23 \dec19_lk + attribute \enum_base_type "OutSel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RT" + attribute \enum_value_10 "RA" + attribute \enum_value_11 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 8 \dec19_out_sel + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 13 \dec19_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 20 \dec19_rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 24 \dec19_sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 22 \dec19_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 19 \dec19_sgn_ext + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 12 \dec19_upd + attribute \src "issuer_ls180.v:70993.7-70993.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + wire width 32 input 25 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:320" + wire width 10 \opcode_switch + attribute \src "issuer_ls180.v:70993.7-70993.20" + process $proc$issuer_ls180.v:70993$3522 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "issuer_ls180.v:71250.3-71301.6" + process $proc$issuer_ls180.v:71250$3498 + assign { } { } + assign { } { } + assign $0\dec19_function_unit[11:0] $1\dec19_function_unit[11:0] + attribute \src "issuer_ls180.v:71251.5-71251.29" + switch \initial + attribute \src "issuer_ls180.v:71251.9-71251.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0000000000 + assign { } { } + assign $1\dec19_function_unit[11:0] 12'000001000000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0100000001 + assign { } { } + assign $1\dec19_function_unit[11:0] 12'000001000000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0010000001 + assign { } { } + assign $1\dec19_function_unit[11:0] 12'000001000000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0100100001 + assign { } { } + assign $1\dec19_function_unit[11:0] 12'000001000000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0011100001 + assign { } { } + assign $1\dec19_function_unit[11:0] 12'000001000000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0000100001 + assign { } { } + assign $1\dec19_function_unit[11:0] 12'000001000000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0111000001 + assign { } { } + assign $1\dec19_function_unit[11:0] 12'000001000000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0110100001 + assign { } { } + assign $1\dec19_function_unit[11:0] 12'000001000000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0011000001 + assign { } { } + assign $1\dec19_function_unit[11:0] 12'000001000000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'1000010000 + assign { } { } + assign $1\dec19_function_unit[11:0] 12'000000100000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0000010000 + assign { } { } + assign $1\dec19_function_unit[11:0] 12'000000100000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'1000110000 + assign { } { } + assign $1\dec19_function_unit[11:0] 12'000000100000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0010010110 + assign { } { } + assign $1\dec19_function_unit[11:0] 12'000000000010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0000010010 + assign { } { } + assign $1\dec19_function_unit[11:0] 12'000010000000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0100010010 + assign { } { } + assign $1\dec19_function_unit[11:0] 12'000010000000 + case + assign $1\dec19_function_unit[11:0] 12'000000000000 + end + sync always + update \dec19_function_unit $0\dec19_function_unit[11:0] + end + attribute \src "issuer_ls180.v:71302.3-71353.6" + process $proc$issuer_ls180.v:71302$3499 + assign { } { } + assign { } { } + assign $0\dec19_ldst_len[3:0] $1\dec19_ldst_len[3:0] + attribute \src "issuer_ls180.v:71303.5-71303.29" + switch \initial + attribute \src "issuer_ls180.v:71303.9-71303.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0000000000 + assign { } { } + assign $1\dec19_ldst_len[3:0] 4'0000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0100000001 + assign { } { } + assign $1\dec19_ldst_len[3:0] 4'0000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0010000001 + assign { } { } + assign $1\dec19_ldst_len[3:0] 4'0000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0100100001 + assign { } { } + assign $1\dec19_ldst_len[3:0] 4'0000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0011100001 + assign { } { } + assign $1\dec19_ldst_len[3:0] 4'0000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0000100001 + assign { } { } + assign $1\dec19_ldst_len[3:0] 4'0000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0111000001 + assign { } { } + assign $1\dec19_ldst_len[3:0] 4'0000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0110100001 + assign { } { } + assign $1\dec19_ldst_len[3:0] 4'0000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0011000001 + assign { } { } + assign $1\dec19_ldst_len[3:0] 4'0000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'1000010000 + assign { } { } + assign $1\dec19_ldst_len[3:0] 4'0000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0000010000 + assign { } { } + assign $1\dec19_ldst_len[3:0] 4'0000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'1000110000 + assign { } { } + assign $1\dec19_ldst_len[3:0] 4'0000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0010010110 + assign { } { } + assign $1\dec19_ldst_len[3:0] 4'0000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0000010010 + assign { } { } + assign $1\dec19_ldst_len[3:0] 4'0000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0100010010 + assign { } { } + assign $1\dec19_ldst_len[3:0] 4'0000 + case + assign $1\dec19_ldst_len[3:0] 4'0000 + end + sync always + update \dec19_ldst_len $0\dec19_ldst_len[3:0] + end + attribute \src "issuer_ls180.v:71354.3-71405.6" + process $proc$issuer_ls180.v:71354$3500 + assign { } { } + assign { } { } + assign $0\dec19_upd[1:0] $1\dec19_upd[1:0] + attribute \src "issuer_ls180.v:71355.5-71355.29" + switch \initial + attribute \src "issuer_ls180.v:71355.9-71355.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0000000000 + assign { } { } + assign $1\dec19_upd[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0100000001 + assign { } { } + assign $1\dec19_upd[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0010000001 + assign { } { } + assign $1\dec19_upd[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0100100001 + assign { } { } + assign $1\dec19_upd[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0011100001 + assign { } { } + assign $1\dec19_upd[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0000100001 + assign { } { } + assign $1\dec19_upd[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0111000001 + assign { } { } + assign $1\dec19_upd[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0110100001 + assign { } { } + assign $1\dec19_upd[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0011000001 + assign { } { } + assign $1\dec19_upd[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'1000010000 + assign { } { } + assign $1\dec19_upd[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0000010000 + assign { } { } + assign $1\dec19_upd[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'1000110000 + assign { } { } + assign $1\dec19_upd[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0010010110 + assign { } { } + assign $1\dec19_upd[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0000010010 + assign { } { } + assign $1\dec19_upd[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0100010010 + assign { } { } + assign $1\dec19_upd[1:0] 2'00 + case + assign $1\dec19_upd[1:0] 2'00 + end + sync always + update \dec19_upd $0\dec19_upd[1:0] + end + attribute \src "issuer_ls180.v:71406.3-71457.6" + process $proc$issuer_ls180.v:71406$3501 + assign { } { } + assign { } { } + assign $0\dec19_rc_sel[1:0] $1\dec19_rc_sel[1:0] + attribute \src "issuer_ls180.v:71407.5-71407.29" + switch \initial + attribute \src "issuer_ls180.v:71407.9-71407.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0000000000 + assign { } { } + assign $1\dec19_rc_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0100000001 + assign { } { } + assign $1\dec19_rc_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0010000001 + assign { } { } + assign $1\dec19_rc_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0100100001 + assign { } { } + assign $1\dec19_rc_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0011100001 + assign { } { } + assign $1\dec19_rc_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0000100001 + assign { } { } + assign $1\dec19_rc_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0111000001 + assign { } { } + assign $1\dec19_rc_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0110100001 + assign { } { } + assign $1\dec19_rc_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0011000001 + assign { } { } + assign $1\dec19_rc_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'1000010000 + assign { } { } + assign $1\dec19_rc_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0000010000 + assign { } { } + assign $1\dec19_rc_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'1000110000 + assign { } { } + assign $1\dec19_rc_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0010010110 + assign { } { } + assign $1\dec19_rc_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0000010010 + assign { } { } + assign $1\dec19_rc_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0100010010 + assign { } { } + assign $1\dec19_rc_sel[1:0] 2'00 + case + assign $1\dec19_rc_sel[1:0] 2'00 + end + sync always + update \dec19_rc_sel $0\dec19_rc_sel[1:0] + end + attribute \src "issuer_ls180.v:71458.3-71509.6" + process $proc$issuer_ls180.v:71458$3502 + assign { } { } + assign { } { } + assign $0\dec19_cry_in[1:0] $1\dec19_cry_in[1:0] + attribute \src "issuer_ls180.v:71459.5-71459.29" + switch \initial + attribute \src "issuer_ls180.v:71459.9-71459.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0000000000 + assign { } { } + assign $1\dec19_cry_in[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0100000001 + assign { } { } + assign $1\dec19_cry_in[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0010000001 + assign { } { } + assign $1\dec19_cry_in[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0100100001 + assign { } { } + assign $1\dec19_cry_in[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0011100001 + assign { } { } + assign $1\dec19_cry_in[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0000100001 + assign { } { } + assign $1\dec19_cry_in[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0111000001 + assign { } { } + assign $1\dec19_cry_in[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0110100001 + assign { } { } + assign $1\dec19_cry_in[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0011000001 + assign { } { } + assign $1\dec19_cry_in[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'1000010000 + assign { } { } + assign $1\dec19_cry_in[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0000010000 + assign { } { } + assign $1\dec19_cry_in[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'1000110000 + assign { } { } + assign $1\dec19_cry_in[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0010010110 + assign { } { } + assign $1\dec19_cry_in[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0000010010 + assign { } { } + assign $1\dec19_cry_in[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0100010010 + assign { } { } + assign $1\dec19_cry_in[1:0] 2'00 + case + assign $1\dec19_cry_in[1:0] 2'00 + end + sync always + update \dec19_cry_in $0\dec19_cry_in[1:0] + end + attribute \src "issuer_ls180.v:71510.3-71561.6" + process $proc$issuer_ls180.v:71510$3503 + assign { } { } + assign { } { } + assign $0\dec19_asmcode[7:0] $1\dec19_asmcode[7:0] + attribute \src "issuer_ls180.v:71511.5-71511.29" + switch \initial + attribute \src "issuer_ls180.v:71511.9-71511.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0000000000 + assign { } { } + assign $1\dec19_asmcode[7:0] 8'01101100 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0100000001 + assign { } { } + assign $1\dec19_asmcode[7:0] 8'00100101 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0010000001 + assign { } { } + assign $1\dec19_asmcode[7:0] 8'00100110 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0100100001 + assign { } { } + assign $1\dec19_asmcode[7:0] 8'00100111 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0011100001 + assign { } { } + assign $1\dec19_asmcode[7:0] 8'00101000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0000100001 + assign { } { } + assign $1\dec19_asmcode[7:0] 8'00101001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0111000001 + assign { } { } + assign $1\dec19_asmcode[7:0] 8'00101010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0110100001 + assign { } { } + assign $1\dec19_asmcode[7:0] 8'00101011 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0011000001 + assign { } { } + assign $1\dec19_asmcode[7:0] 8'00101100 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'1000010000 + assign { } { } + assign $1\dec19_asmcode[7:0] 8'00010110 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0000010000 + assign { } { } + assign $1\dec19_asmcode[7:0] 8'00010111 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'1000110000 + assign { } { } + assign $1\dec19_asmcode[7:0] 8'00011000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0010010110 + assign { } { } + assign $1\dec19_asmcode[7:0] 8'01001100 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0000010010 + assign { } { } + assign $1\dec19_asmcode[7:0] 8'10010001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0100010010 + assign { } { } + assign $1\dec19_asmcode[7:0] 8'01001000 + case + assign $1\dec19_asmcode[7:0] 8'00000000 + end + sync always + update \dec19_asmcode $0\dec19_asmcode[7:0] + end + attribute \src "issuer_ls180.v:71562.3-71613.6" + process $proc$issuer_ls180.v:71562$3504 + assign { } { } + assign { } { } + assign $0\dec19_inv_a[0:0] $1\dec19_inv_a[0:0] + attribute \src "issuer_ls180.v:71563.5-71563.29" + switch \initial + attribute \src "issuer_ls180.v:71563.9-71563.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0000000000 + assign { } { } + assign $1\dec19_inv_a[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0100000001 + assign { } { } + assign $1\dec19_inv_a[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0010000001 + assign { } { } + assign $1\dec19_inv_a[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0100100001 + assign { } { } + assign $1\dec19_inv_a[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0011100001 + assign { } { } + assign $1\dec19_inv_a[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0000100001 + assign { } { } + assign $1\dec19_inv_a[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0111000001 + assign { } { } + assign $1\dec19_inv_a[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0110100001 + assign { } { } + assign $1\dec19_inv_a[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0011000001 + assign { } { } + assign $1\dec19_inv_a[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'1000010000 + assign { } { } + assign $1\dec19_inv_a[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0000010000 + assign { } { } + assign $1\dec19_inv_a[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'1000110000 + assign { } { } + assign $1\dec19_inv_a[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0010010110 + assign { } { } + assign $1\dec19_inv_a[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0000010010 + assign { } { } + assign $1\dec19_inv_a[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0100010010 + assign { } { } + assign $1\dec19_inv_a[0:0] 1'0 + case + assign $1\dec19_inv_a[0:0] 1'0 + end + sync always + update \dec19_inv_a $0\dec19_inv_a[0:0] + end + attribute \src "issuer_ls180.v:71614.3-71665.6" + process $proc$issuer_ls180.v:71614$3505 + assign { } { } + assign { } { } + assign $0\dec19_inv_out[0:0] $1\dec19_inv_out[0:0] + attribute \src "issuer_ls180.v:71615.5-71615.29" + switch \initial + attribute \src "issuer_ls180.v:71615.9-71615.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0000000000 + assign { } { } + assign $1\dec19_inv_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0100000001 + assign { } { } + assign $1\dec19_inv_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0010000001 + assign { } { } + assign $1\dec19_inv_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0100100001 + assign { } { } + assign $1\dec19_inv_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0011100001 + assign { } { } + assign $1\dec19_inv_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0000100001 + assign { } { } + assign $1\dec19_inv_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0111000001 + assign { } { } + assign $1\dec19_inv_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0110100001 + assign { } { } + assign $1\dec19_inv_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0011000001 + assign { } { } + assign $1\dec19_inv_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'1000010000 + assign { } { } + assign $1\dec19_inv_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0000010000 + assign { } { } + assign $1\dec19_inv_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'1000110000 + assign { } { } + assign $1\dec19_inv_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0010010110 + assign { } { } + assign $1\dec19_inv_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0000010010 + assign { } { } + assign $1\dec19_inv_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0100010010 + assign { } { } + assign $1\dec19_inv_out[0:0] 1'0 + case + assign $1\dec19_inv_out[0:0] 1'0 + end + sync always + update \dec19_inv_out $0\dec19_inv_out[0:0] + end + attribute \src "issuer_ls180.v:71666.3-71717.6" + process $proc$issuer_ls180.v:71666$3506 + assign { } { } + assign { } { } + assign $0\dec19_cry_out[0:0] $1\dec19_cry_out[0:0] + attribute \src "issuer_ls180.v:71667.5-71667.29" + switch \initial + attribute \src "issuer_ls180.v:71667.9-71667.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0000000000 + assign { } { } + assign $1\dec19_cry_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0100000001 + assign { } { } + assign $1\dec19_cry_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0010000001 + assign { } { } + assign $1\dec19_cry_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0100100001 + assign { } { } + assign $1\dec19_cry_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0011100001 + assign { } { } + assign $1\dec19_cry_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0000100001 + assign { } { } + assign $1\dec19_cry_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0111000001 + assign { } { } + assign $1\dec19_cry_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0110100001 + assign { } { } + assign $1\dec19_cry_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0011000001 + assign { } { } + assign $1\dec19_cry_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'1000010000 + assign { } { } + assign $1\dec19_cry_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0000010000 + assign { } { } + assign $1\dec19_cry_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'1000110000 + assign { } { } + assign $1\dec19_cry_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0010010110 + assign { } { } + assign $1\dec19_cry_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0000010010 + assign { } { } + assign $1\dec19_cry_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0100010010 + assign { } { } + assign $1\dec19_cry_out[0:0] 1'0 + case + assign $1\dec19_cry_out[0:0] 1'0 + end + sync always + update \dec19_cry_out $0\dec19_cry_out[0:0] + end + attribute \src "issuer_ls180.v:71718.3-71769.6" + process $proc$issuer_ls180.v:71718$3507 + assign { } { } + assign { } { } + assign $0\dec19_br[0:0] $1\dec19_br[0:0] + attribute \src "issuer_ls180.v:71719.5-71719.29" + switch \initial + attribute \src "issuer_ls180.v:71719.9-71719.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0000000000 + assign { } { } + assign $1\dec19_br[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0100000001 + assign { } { } + assign $1\dec19_br[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0010000001 + assign { } { } + assign $1\dec19_br[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0100100001 + assign { } { } + assign $1\dec19_br[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0011100001 + assign { } { } + assign $1\dec19_br[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0000100001 + assign { } { } + assign $1\dec19_br[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0111000001 + assign { } { } + assign $1\dec19_br[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0110100001 + assign { } { } + assign $1\dec19_br[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0011000001 + assign { } { } + assign $1\dec19_br[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'1000010000 + assign { } { } + assign $1\dec19_br[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0000010000 + assign { } { } + assign $1\dec19_br[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'1000110000 + assign { } { } + assign $1\dec19_br[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0010010110 + assign { } { } + assign $1\dec19_br[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0000010010 + assign { } { } + assign $1\dec19_br[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0100010010 + assign { } { } + assign $1\dec19_br[0:0] 1'0 + case + assign $1\dec19_br[0:0] 1'0 + end + sync always + update \dec19_br $0\dec19_br[0:0] + end + attribute \src "issuer_ls180.v:71770.3-71821.6" + process $proc$issuer_ls180.v:71770$3508 + assign { } { } + assign { } { } + assign $0\dec19_sgn_ext[0:0] $1\dec19_sgn_ext[0:0] + attribute \src "issuer_ls180.v:71771.5-71771.29" + switch \initial + attribute \src "issuer_ls180.v:71771.9-71771.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0000000000 + assign { } { } + assign $1\dec19_sgn_ext[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0100000001 + assign { } { } + assign $1\dec19_sgn_ext[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0010000001 + assign { } { } + assign $1\dec19_sgn_ext[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0100100001 + assign { } { } + assign $1\dec19_sgn_ext[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0011100001 + assign { } { } + assign $1\dec19_sgn_ext[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0000100001 + assign { } { } + assign $1\dec19_sgn_ext[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0111000001 + assign { } { } + assign $1\dec19_sgn_ext[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0110100001 + assign { } { } + assign $1\dec19_sgn_ext[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0011000001 + assign { } { } + assign $1\dec19_sgn_ext[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'1000010000 + assign { } { } + assign $1\dec19_sgn_ext[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0000010000 + assign { } { } + assign $1\dec19_sgn_ext[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'1000110000 + assign { } { } + assign $1\dec19_sgn_ext[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0010010110 + assign { } { } + assign $1\dec19_sgn_ext[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0000010010 + assign { } { } + assign $1\dec19_sgn_ext[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0100010010 + assign { } { } + assign $1\dec19_sgn_ext[0:0] 1'0 + case + assign $1\dec19_sgn_ext[0:0] 1'0 + end + sync always + update \dec19_sgn_ext $0\dec19_sgn_ext[0:0] + end + attribute \src "issuer_ls180.v:71822.3-71873.6" + process $proc$issuer_ls180.v:71822$3509 + assign { } { } + assign { } { } + assign $0\dec19_internal_op[6:0] $1\dec19_internal_op[6:0] + attribute \src "issuer_ls180.v:71823.5-71823.29" + switch \initial + attribute \src "issuer_ls180.v:71823.9-71823.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0000000000 + assign { } { } + assign $1\dec19_internal_op[6:0] 7'0101010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0100000001 + assign { } { } + assign $1\dec19_internal_op[6:0] 7'1000101 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0010000001 + assign { } { } + assign $1\dec19_internal_op[6:0] 7'1000101 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0100100001 + assign { } { } + assign $1\dec19_internal_op[6:0] 7'1000101 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0011100001 + assign { } { } + assign $1\dec19_internal_op[6:0] 7'1000101 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0000100001 + assign { } { } + assign $1\dec19_internal_op[6:0] 7'1000101 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0111000001 + assign { } { } + assign $1\dec19_internal_op[6:0] 7'1000101 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0110100001 + assign { } { } + assign $1\dec19_internal_op[6:0] 7'1000101 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0011000001 + assign { } { } + assign $1\dec19_internal_op[6:0] 7'1000101 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'1000010000 + assign { } { } + assign $1\dec19_internal_op[6:0] 7'0001000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0000010000 + assign { } { } + assign $1\dec19_internal_op[6:0] 7'0001000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'1000110000 + assign { } { } + assign $1\dec19_internal_op[6:0] 7'0001000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0010010110 + assign { } { } + assign $1\dec19_internal_op[6:0] 7'0100100 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0000010010 + assign { } { } + assign $1\dec19_internal_op[6:0] 7'1000110 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0100010010 + assign { } { } + assign $1\dec19_internal_op[6:0] 7'1000110 + case + assign $1\dec19_internal_op[6:0] 7'0000000 + end + sync always + update \dec19_internal_op $0\dec19_internal_op[6:0] + end + attribute \src "issuer_ls180.v:71874.3-71925.6" + process $proc$issuer_ls180.v:71874$3510 + assign { } { } + assign { } { } + assign $0\dec19_rsrv[0:0] $1\dec19_rsrv[0:0] + attribute \src "issuer_ls180.v:71875.5-71875.29" + switch \initial + attribute \src "issuer_ls180.v:71875.9-71875.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0000000000 + assign { } { } + assign $1\dec19_rsrv[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0100000001 + assign { } { } + assign $1\dec19_rsrv[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0010000001 + assign { } { } + assign $1\dec19_rsrv[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0100100001 + assign { } { } + assign $1\dec19_rsrv[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0011100001 + assign { } { } + assign $1\dec19_rsrv[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0000100001 + assign { } { } + assign $1\dec19_rsrv[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0111000001 + assign { } { } + assign $1\dec19_rsrv[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0110100001 + assign { } { } + assign $1\dec19_rsrv[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0011000001 + assign { } { } + assign $1\dec19_rsrv[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'1000010000 + assign { } { } + assign $1\dec19_rsrv[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0000010000 + assign { } { } + assign $1\dec19_rsrv[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'1000110000 + assign { } { } + assign $1\dec19_rsrv[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0010010110 + assign { } { } + assign $1\dec19_rsrv[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0000010010 + assign { } { } + assign $1\dec19_rsrv[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0100010010 + assign { } { } + assign $1\dec19_rsrv[0:0] 1'0 + case + assign $1\dec19_rsrv[0:0] 1'0 + end + sync always + update \dec19_rsrv $0\dec19_rsrv[0:0] + end + attribute \src "issuer_ls180.v:71926.3-71977.6" + process $proc$issuer_ls180.v:71926$3511 + assign { } { } + assign { } { } + assign $0\dec19_is_32b[0:0] $1\dec19_is_32b[0:0] + attribute \src "issuer_ls180.v:71927.5-71927.29" + switch \initial + attribute \src "issuer_ls180.v:71927.9-71927.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0000000000 + assign { } { } + assign $1\dec19_is_32b[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0100000001 + assign { } { } + assign $1\dec19_is_32b[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0010000001 + assign { } { } + assign $1\dec19_is_32b[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0100100001 + assign { } { } + assign $1\dec19_is_32b[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0011100001 + assign { } { } + assign $1\dec19_is_32b[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0000100001 + assign { } { } + assign $1\dec19_is_32b[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0111000001 + assign { } { } + assign $1\dec19_is_32b[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0110100001 + assign { } { } + assign $1\dec19_is_32b[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0011000001 + assign { } { } + assign $1\dec19_is_32b[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'1000010000 + assign { } { } + assign $1\dec19_is_32b[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0000010000 + assign { } { } + assign $1\dec19_is_32b[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'1000110000 + assign { } { } + assign $1\dec19_is_32b[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0010010110 + assign { } { } + assign $1\dec19_is_32b[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0000010010 + assign { } { } + assign $1\dec19_is_32b[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0100010010 + assign { } { } + assign $1\dec19_is_32b[0:0] 1'0 + case + assign $1\dec19_is_32b[0:0] 1'0 + end + sync always + update \dec19_is_32b $0\dec19_is_32b[0:0] + end + attribute \src "issuer_ls180.v:71978.3-72029.6" + process $proc$issuer_ls180.v:71978$3512 + assign { } { } + assign { } { } + assign $0\dec19_sgn[0:0] $1\dec19_sgn[0:0] + attribute \src "issuer_ls180.v:71979.5-71979.29" + switch \initial + attribute \src "issuer_ls180.v:71979.9-71979.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0000000000 + assign { } { } + assign $1\dec19_sgn[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0100000001 + assign { } { } + assign $1\dec19_sgn[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0010000001 + assign { } { } + assign $1\dec19_sgn[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0100100001 + assign { } { } + assign $1\dec19_sgn[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0011100001 + assign { } { } + assign $1\dec19_sgn[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0000100001 + assign { } { } + assign $1\dec19_sgn[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0111000001 + assign { } { } + assign $1\dec19_sgn[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0110100001 + assign { } { } + assign $1\dec19_sgn[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0011000001 + assign { } { } + assign $1\dec19_sgn[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'1000010000 + assign { } { } + assign $1\dec19_sgn[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0000010000 + assign { } { } + assign $1\dec19_sgn[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'1000110000 + assign { } { } + assign $1\dec19_sgn[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0010010110 + assign { } { } + assign $1\dec19_sgn[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0000010010 + assign { } { } + assign $1\dec19_sgn[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0100010010 + assign { } { } + assign $1\dec19_sgn[0:0] 1'0 + case + assign $1\dec19_sgn[0:0] 1'0 + end + sync always + update \dec19_sgn $0\dec19_sgn[0:0] + end + attribute \src "issuer_ls180.v:72030.3-72081.6" + process $proc$issuer_ls180.v:72030$3513 + assign { } { } + assign { } { } + assign $0\dec19_lk[0:0] $1\dec19_lk[0:0] + attribute \src "issuer_ls180.v:72031.5-72031.29" + switch \initial + attribute \src "issuer_ls180.v:72031.9-72031.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0000000000 + assign { } { } + assign $1\dec19_lk[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0100000001 + assign { } { } + assign $1\dec19_lk[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0010000001 + assign { } { } + assign $1\dec19_lk[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0100100001 + assign { } { } + assign $1\dec19_lk[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0011100001 + assign { } { } + assign $1\dec19_lk[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0000100001 + assign { } { } + assign $1\dec19_lk[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0111000001 + assign { } { } + assign $1\dec19_lk[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0110100001 + assign { } { } + assign $1\dec19_lk[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0011000001 + assign { } { } + assign $1\dec19_lk[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'1000010000 + assign { } { } + assign $1\dec19_lk[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0000010000 + assign { } { } + assign $1\dec19_lk[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'1000110000 + assign { } { } + assign $1\dec19_lk[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0010010110 + assign { } { } + assign $1\dec19_lk[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0000010010 + assign { } { } + assign $1\dec19_lk[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0100010010 + assign { } { } + assign $1\dec19_lk[0:0] 1'0 + case + assign $1\dec19_lk[0:0] 1'0 + end + sync always + update \dec19_lk $0\dec19_lk[0:0] + end + attribute \src "issuer_ls180.v:72082.3-72133.6" + process $proc$issuer_ls180.v:72082$3514 + assign { } { } + assign { } { } + assign $0\dec19_sgl_pipe[0:0] $1\dec19_sgl_pipe[0:0] + attribute \src "issuer_ls180.v:72083.5-72083.29" + switch \initial + attribute \src "issuer_ls180.v:72083.9-72083.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0000000000 + assign { } { } + assign $1\dec19_sgl_pipe[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0100000001 + assign { } { } + assign $1\dec19_sgl_pipe[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0010000001 + assign { } { } + assign $1\dec19_sgl_pipe[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0100100001 + assign { } { } + assign $1\dec19_sgl_pipe[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0011100001 + assign { } { } + assign $1\dec19_sgl_pipe[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0000100001 + assign { } { } + assign $1\dec19_sgl_pipe[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0111000001 + assign { } { } + assign $1\dec19_sgl_pipe[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0110100001 + assign { } { } + assign $1\dec19_sgl_pipe[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0011000001 + assign { } { } + assign $1\dec19_sgl_pipe[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'1000010000 + assign { } { } + assign $1\dec19_sgl_pipe[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0000010000 + assign { } { } + assign $1\dec19_sgl_pipe[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'1000110000 + assign { } { } + assign $1\dec19_sgl_pipe[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0010010110 + assign { } { } + assign $1\dec19_sgl_pipe[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0000010010 + assign { } { } + assign $1\dec19_sgl_pipe[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0100010010 + assign { } { } + assign $1\dec19_sgl_pipe[0:0] 1'0 + case + assign $1\dec19_sgl_pipe[0:0] 1'0 + end + sync always + update \dec19_sgl_pipe $0\dec19_sgl_pipe[0:0] + end + attribute \src "issuer_ls180.v:72134.3-72185.6" + process $proc$issuer_ls180.v:72134$3515 + assign { } { } + assign { } { } + assign $0\dec19_form[4:0] $1\dec19_form[4:0] + attribute \src "issuer_ls180.v:72135.5-72135.29" + switch \initial + attribute \src "issuer_ls180.v:72135.9-72135.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0000000000 + assign { } { } + assign $1\dec19_form[4:0] 5'01001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0100000001 + assign { } { } + assign $1\dec19_form[4:0] 5'01001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0010000001 + assign { } { } + assign $1\dec19_form[4:0] 5'01001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0100100001 + assign { } { } + assign $1\dec19_form[4:0] 5'01001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0011100001 + assign { } { } + assign $1\dec19_form[4:0] 5'01001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0000100001 + assign { } { } + assign $1\dec19_form[4:0] 5'01001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0111000001 + assign { } { } + assign $1\dec19_form[4:0] 5'01001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0110100001 + assign { } { } + assign $1\dec19_form[4:0] 5'01001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0011000001 + assign { } { } + assign $1\dec19_form[4:0] 5'01001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'1000010000 + assign { } { } + assign $1\dec19_form[4:0] 5'01001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0000010000 + assign { } { } + assign $1\dec19_form[4:0] 5'01001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'1000110000 + assign { } { } + assign $1\dec19_form[4:0] 5'01001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0010010110 + assign { } { } + assign $1\dec19_form[4:0] 5'01001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0000010010 + assign { } { } + assign $1\dec19_form[4:0] 5'01001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0100010010 + assign { } { } + assign $1\dec19_form[4:0] 5'01001 + case + assign $1\dec19_form[4:0] 5'00000 + end + sync always + update \dec19_form $0\dec19_form[4:0] + end + attribute \src "issuer_ls180.v:72186.3-72237.6" + process $proc$issuer_ls180.v:72186$3516 + assign { } { } + assign { } { } + assign $0\dec19_in1_sel[2:0] $1\dec19_in1_sel[2:0] + attribute \src "issuer_ls180.v:72187.5-72187.29" + switch \initial + attribute \src "issuer_ls180.v:72187.9-72187.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0000000000 + assign { } { } + assign $1\dec19_in1_sel[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0100000001 + assign { } { } + assign $1\dec19_in1_sel[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0010000001 + assign { } { } + assign $1\dec19_in1_sel[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0100100001 + assign { } { } + assign $1\dec19_in1_sel[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0011100001 + assign { } { } + assign $1\dec19_in1_sel[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0000100001 + assign { } { } + assign $1\dec19_in1_sel[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0111000001 + assign { } { } + assign $1\dec19_in1_sel[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0110100001 + assign { } { } + assign $1\dec19_in1_sel[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0011000001 + assign { } { } + assign $1\dec19_in1_sel[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'1000010000 + assign { } { } + assign $1\dec19_in1_sel[2:0] 3'011 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0000010000 + assign { } { } + assign $1\dec19_in1_sel[2:0] 3'011 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'1000110000 + assign { } { } + assign $1\dec19_in1_sel[2:0] 3'011 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0010010110 + assign { } { } + assign $1\dec19_in1_sel[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0000010010 + assign { } { } + assign $1\dec19_in1_sel[2:0] 3'011 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0100010010 + assign { } { } + assign $1\dec19_in1_sel[2:0] 3'011 + case + assign $1\dec19_in1_sel[2:0] 3'000 + end + sync always + update \dec19_in1_sel $0\dec19_in1_sel[2:0] + end + attribute \src "issuer_ls180.v:72238.3-72289.6" + process $proc$issuer_ls180.v:72238$3517 + assign { } { } + assign { } { } + assign $0\dec19_in2_sel[3:0] $1\dec19_in2_sel[3:0] + attribute \src "issuer_ls180.v:72239.5-72239.29" + switch \initial + attribute \src "issuer_ls180.v:72239.9-72239.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0000000000 + assign { } { } + assign $1\dec19_in2_sel[3:0] 4'0000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0100000001 + assign { } { } + assign $1\dec19_in2_sel[3:0] 4'0000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0010000001 + assign { } { } + assign $1\dec19_in2_sel[3:0] 4'0000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0100100001 + assign { } { } + assign $1\dec19_in2_sel[3:0] 4'0000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0011100001 + assign { } { } + assign $1\dec19_in2_sel[3:0] 4'0000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0000100001 + assign { } { } + assign $1\dec19_in2_sel[3:0] 4'0000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0111000001 + assign { } { } + assign $1\dec19_in2_sel[3:0] 4'0000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0110100001 + assign { } { } + assign $1\dec19_in2_sel[3:0] 4'0000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0011000001 + assign { } { } + assign $1\dec19_in2_sel[3:0] 4'0000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'1000010000 + assign { } { } + assign $1\dec19_in2_sel[3:0] 4'1100 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0000010000 + assign { } { } + assign $1\dec19_in2_sel[3:0] 4'1100 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'1000110000 + assign { } { } + assign $1\dec19_in2_sel[3:0] 4'1100 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0010010110 + assign { } { } + assign $1\dec19_in2_sel[3:0] 4'0000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0000010010 + assign { } { } + assign $1\dec19_in2_sel[3:0] 4'1100 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0100010010 + assign { } { } + assign $1\dec19_in2_sel[3:0] 4'1100 + case + assign $1\dec19_in2_sel[3:0] 4'0000 + end + sync always + update \dec19_in2_sel $0\dec19_in2_sel[3:0] + end + attribute \src "issuer_ls180.v:72290.3-72341.6" + process $proc$issuer_ls180.v:72290$3518 + assign { } { } + assign { } { } + assign $0\dec19_in3_sel[1:0] $1\dec19_in3_sel[1:0] + attribute \src "issuer_ls180.v:72291.5-72291.29" + switch \initial + attribute \src "issuer_ls180.v:72291.9-72291.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0000000000 + assign { } { } + assign $1\dec19_in3_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0100000001 + assign { } { } + assign $1\dec19_in3_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0010000001 + assign { } { } + assign $1\dec19_in3_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0100100001 + assign { } { } + assign $1\dec19_in3_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0011100001 + assign { } { } + assign $1\dec19_in3_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0000100001 + assign { } { } + assign $1\dec19_in3_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0111000001 + assign { } { } + assign $1\dec19_in3_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0110100001 + assign { } { } + assign $1\dec19_in3_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0011000001 + assign { } { } + assign $1\dec19_in3_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'1000010000 + assign { } { } + assign $1\dec19_in3_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0000010000 + assign { } { } + assign $1\dec19_in3_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'1000110000 + assign { } { } + assign $1\dec19_in3_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0010010110 + assign { } { } + assign $1\dec19_in3_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0000010010 + assign { } { } + assign $1\dec19_in3_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0100010010 + assign { } { } + assign $1\dec19_in3_sel[1:0] 2'00 + case + assign $1\dec19_in3_sel[1:0] 2'00 + end + sync always + update \dec19_in3_sel $0\dec19_in3_sel[1:0] + end + attribute \src "issuer_ls180.v:72342.3-72393.6" + process $proc$issuer_ls180.v:72342$3519 + assign { } { } + assign { } { } + assign $0\dec19_out_sel[1:0] $1\dec19_out_sel[1:0] + attribute \src "issuer_ls180.v:72343.5-72343.29" + switch \initial + attribute \src "issuer_ls180.v:72343.9-72343.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0000000000 + assign { } { } + assign $1\dec19_out_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0100000001 + assign { } { } + assign $1\dec19_out_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0010000001 + assign { } { } + assign $1\dec19_out_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0100100001 + assign { } { } + assign $1\dec19_out_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0011100001 + assign { } { } + assign $1\dec19_out_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0000100001 + assign { } { } + assign $1\dec19_out_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0111000001 + assign { } { } + assign $1\dec19_out_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0110100001 + assign { } { } + assign $1\dec19_out_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0011000001 + assign { } { } + assign $1\dec19_out_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'1000010000 + assign { } { } + assign $1\dec19_out_sel[1:0] 2'11 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0000010000 + assign { } { } + assign $1\dec19_out_sel[1:0] 2'11 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'1000110000 + assign { } { } + assign $1\dec19_out_sel[1:0] 2'11 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0010010110 + assign { } { } + assign $1\dec19_out_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0000010010 + assign { } { } + assign $1\dec19_out_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0100010010 + assign { } { } + assign $1\dec19_out_sel[1:0] 2'00 + case + assign $1\dec19_out_sel[1:0] 2'00 + end + sync always + update \dec19_out_sel $0\dec19_out_sel[1:0] + end + attribute \src "issuer_ls180.v:72394.3-72445.6" + process $proc$issuer_ls180.v:72394$3520 + assign { } { } + assign { } { } + assign $0\dec19_cr_in[2:0] $1\dec19_cr_in[2:0] + attribute \src "issuer_ls180.v:72395.5-72395.29" + switch \initial + attribute \src "issuer_ls180.v:72395.9-72395.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0000000000 + assign { } { } + assign $1\dec19_cr_in[2:0] 3'011 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0100000001 + assign { } { } + assign $1\dec19_cr_in[2:0] 3'100 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0010000001 + assign { } { } + assign $1\dec19_cr_in[2:0] 3'100 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0100100001 + assign { } { } + assign $1\dec19_cr_in[2:0] 3'100 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0011100001 + assign { } { } + assign $1\dec19_cr_in[2:0] 3'100 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0000100001 + assign { } { } + assign $1\dec19_cr_in[2:0] 3'100 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0111000001 + assign { } { } + assign $1\dec19_cr_in[2:0] 3'100 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0110100001 + assign { } { } + assign $1\dec19_cr_in[2:0] 3'100 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0011000001 + assign { } { } + assign $1\dec19_cr_in[2:0] 3'100 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'1000010000 + assign { } { } + assign $1\dec19_cr_in[2:0] 3'010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0000010000 + assign { } { } + assign $1\dec19_cr_in[2:0] 3'010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'1000110000 + assign { } { } + assign $1\dec19_cr_in[2:0] 3'010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0010010110 + assign { } { } + assign $1\dec19_cr_in[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0000010010 + assign { } { } + assign $1\dec19_cr_in[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0100010010 + assign { } { } + assign $1\dec19_cr_in[2:0] 3'000 + case + assign $1\dec19_cr_in[2:0] 3'000 + end + sync always + update \dec19_cr_in $0\dec19_cr_in[2:0] + end + attribute \src "issuer_ls180.v:72446.3-72497.6" + process $proc$issuer_ls180.v:72446$3521 + assign { } { } + assign { } { } + assign $0\dec19_cr_out[2:0] $1\dec19_cr_out[2:0] + attribute \src "issuer_ls180.v:72447.5-72447.29" + switch \initial + attribute \src "issuer_ls180.v:72447.9-72447.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0000000000 + assign { } { } + assign $1\dec19_cr_out[2:0] 3'010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0100000001 + assign { } { } + assign $1\dec19_cr_out[2:0] 3'011 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0010000001 + assign { } { } + assign $1\dec19_cr_out[2:0] 3'011 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0100100001 + assign { } { } + assign $1\dec19_cr_out[2:0] 3'011 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0011100001 + assign { } { } + assign $1\dec19_cr_out[2:0] 3'011 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0000100001 + assign { } { } + assign $1\dec19_cr_out[2:0] 3'011 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0111000001 + assign { } { } + assign $1\dec19_cr_out[2:0] 3'011 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0110100001 + assign { } { } + assign $1\dec19_cr_out[2:0] 3'011 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0011000001 + assign { } { } + assign $1\dec19_cr_out[2:0] 3'011 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'1000010000 + assign { } { } + assign $1\dec19_cr_out[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0000010000 + assign { } { } + assign $1\dec19_cr_out[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'1000110000 + assign { } { } + assign $1\dec19_cr_out[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0010010110 + assign { } { } + assign $1\dec19_cr_out[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0000010010 + assign { } { } + assign $1\dec19_cr_out[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0100010010 + assign { } { } + assign $1\dec19_cr_out[2:0] 3'000 + case + assign $1\dec19_cr_out[2:0] 3'000 + end + sync always + update \dec19_cr_out $0\dec19_cr_out[2:0] + end + connect \opcode_switch \opcode_in [10:1] +end +attribute \src "issuer_ls180.v:72503.1-74386.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.dec2" +attribute \generator "nMigen" +module \dec2 + attribute \src "issuer_ls180.v:74255.3-74333.6" + wire width 8 $0\asmcode[7:0] + attribute \src "issuer_ls180.v:74255.3-74333.6" + wire width 64 $0\cia[63:0] + attribute \src "issuer_ls180.v:74255.3-74333.6" + wire width 3 $0\cr_in1[2:0] + attribute \src "issuer_ls180.v:74255.3-74333.6" + wire $0\cr_in1_ok[0:0] + attribute \src "issuer_ls180.v:74255.3-74333.6" + wire width 3 $0\cr_in2$1[2:0]$3541 + attribute \src "issuer_ls180.v:74255.3-74333.6" + wire width 3 $0\cr_in2[2:0] + attribute \src "issuer_ls180.v:74255.3-74333.6" + wire $0\cr_in2_ok$2[0:0]$3542 + attribute \src "issuer_ls180.v:74255.3-74333.6" + wire $0\cr_in2_ok[0:0] + attribute \src "issuer_ls180.v:74255.3-74333.6" + wire width 3 $0\cr_out[2:0] + attribute \src "issuer_ls180.v:74255.3-74333.6" + wire $0\cr_out_ok[0:0] + attribute \src "issuer_ls180.v:74255.3-74333.6" + wire width 8 $0\cr_rd[7:0] + attribute \src "issuer_ls180.v:74255.3-74333.6" + wire $0\cr_rd_ok[0:0] + attribute \src "issuer_ls180.v:74255.3-74333.6" + wire width 8 $0\cr_wr[7:0] + attribute \src "issuer_ls180.v:74255.3-74333.6" + wire $0\cr_wr_ok[0:0] + attribute \src "issuer_ls180.v:74255.3-74333.6" + wire width 5 $0\ea[4:0] + attribute \src "issuer_ls180.v:74255.3-74333.6" + wire $0\ea_ok[0:0] + attribute \src "issuer_ls180.v:74255.3-74333.6" + wire width 3 $0\fast1[2:0] + attribute \src "issuer_ls180.v:74255.3-74333.6" + wire $0\fast1_ok[0:0] + attribute \src "issuer_ls180.v:74255.3-74333.6" + wire width 3 $0\fast2[2:0] + attribute \src "issuer_ls180.v:74255.3-74333.6" + wire $0\fast2_ok[0:0] + attribute \src "issuer_ls180.v:74255.3-74333.6" + wire width 3 $0\fasto1[2:0] + attribute \src "issuer_ls180.v:74255.3-74333.6" + wire $0\fasto1_ok[0:0] + attribute \src "issuer_ls180.v:74255.3-74333.6" + wire width 3 $0\fasto2[2:0] + attribute \src "issuer_ls180.v:74255.3-74333.6" + wire $0\fasto2_ok[0:0] + attribute \src "issuer_ls180.v:74255.3-74333.6" + wire width 12 $0\fn_unit[11:0] + attribute \src "issuer_ls180.v:72504.7-72504.20" + wire $0\initial[0:0] + attribute \src "issuer_ls180.v:74255.3-74333.6" + wire width 2 $0\input_carry[1:0] + attribute \src "issuer_ls180.v:74255.3-74333.6" + wire width 32 $0\insn[31:0] + attribute \src "issuer_ls180.v:74255.3-74333.6" + wire width 7 $0\insn_type[6:0] + attribute \src "issuer_ls180.v:74255.3-74333.6" + wire $0\is_32bit[0:0] + attribute \src "issuer_ls180.v:74235.3-74254.6" + wire $0\is_priv_insn[0:0] + attribute \src "issuer_ls180.v:74255.3-74333.6" + wire $0\lk[0:0] + attribute \src "issuer_ls180.v:74255.3-74333.6" + wire width 64 $0\msr[63:0] + attribute \src "issuer_ls180.v:74255.3-74333.6" + wire $0\oe[0:0] + attribute \src "issuer_ls180.v:74255.3-74333.6" + wire $0\oe_ok[0:0] + attribute \src "issuer_ls180.v:74255.3-74333.6" + wire $0\rc[0:0] + attribute \src "issuer_ls180.v:74255.3-74333.6" + wire $0\rc_ok[0:0] + attribute \src "issuer_ls180.v:74255.3-74333.6" + wire width 5 $0\reg1[4:0] + attribute \src "issuer_ls180.v:74255.3-74333.6" + wire $0\reg1_ok[0:0] + attribute \src "issuer_ls180.v:74255.3-74333.6" + wire width 5 $0\reg2[4:0] + attribute \src "issuer_ls180.v:74255.3-74333.6" + wire $0\reg2_ok[0:0] + attribute \src "issuer_ls180.v:74255.3-74333.6" + wire width 5 $0\reg3[4:0] + attribute \src "issuer_ls180.v:74255.3-74333.6" + wire $0\reg3_ok[0:0] + attribute \src "issuer_ls180.v:74255.3-74333.6" + wire width 5 $0\rego[4:0] + attribute \src "issuer_ls180.v:74255.3-74333.6" + wire $0\rego_ok[0:0] + attribute \src "issuer_ls180.v:74255.3-74333.6" + wire width 10 $0\spr1[9:0] + attribute \src "issuer_ls180.v:74255.3-74333.6" + wire $0\spr1_ok[0:0] + attribute \src "issuer_ls180.v:74255.3-74333.6" + wire width 10 $0\spro[9:0] + attribute \src "issuer_ls180.v:74255.3-74333.6" + wire $0\spro_ok[0:0] + attribute \src "issuer_ls180.v:74189.3-74198.6" + wire $0\tmp_tmp_lk[0:0] + attribute \src "issuer_ls180.v:74225.3-74234.6" + wire width 13 $0\tmp_tmp_trapaddr[12:0] + attribute \src "issuer_ls180.v:74199.3-74214.6" + wire width 3 $0\tmp_xer_in[2:0] + attribute \src "issuer_ls180.v:74215.3-74224.6" + wire $0\tmp_xer_out[0:0] + attribute \src "issuer_ls180.v:74255.3-74333.6" + wire width 13 $0\trapaddr[12:0] + attribute \src "issuer_ls180.v:74255.3-74333.6" + wire width 7 $0\traptype[6:0] + attribute \src "issuer_ls180.v:74255.3-74333.6" + wire width 3 $0\xer_in[2:0] + attribute \src "issuer_ls180.v:74255.3-74333.6" + wire $0\xer_out[0:0] + attribute \src "issuer_ls180.v:74255.3-74333.6" + wire width 8 $1\asmcode[7:0] + attribute \src "issuer_ls180.v:74255.3-74333.6" + wire width 64 $1\cia[63:0] + attribute \src "issuer_ls180.v:74255.3-74333.6" + wire width 3 $1\cr_in1[2:0] + attribute \src "issuer_ls180.v:74255.3-74333.6" + wire $1\cr_in1_ok[0:0] + attribute \src "issuer_ls180.v:74255.3-74333.6" + wire width 3 $1\cr_in2$1[2:0]$3543 + attribute \src "issuer_ls180.v:74255.3-74333.6" + wire width 3 $1\cr_in2[2:0] + attribute \src "issuer_ls180.v:74255.3-74333.6" + wire $1\cr_in2_ok$2[0:0]$3544 + attribute \src "issuer_ls180.v:74255.3-74333.6" + wire $1\cr_in2_ok[0:0] + attribute \src "issuer_ls180.v:74255.3-74333.6" + wire width 3 $1\cr_out[2:0] + attribute \src "issuer_ls180.v:74255.3-74333.6" + wire $1\cr_out_ok[0:0] + attribute \src "issuer_ls180.v:74255.3-74333.6" + wire width 8 $1\cr_rd[7:0] + attribute \src "issuer_ls180.v:74255.3-74333.6" + wire $1\cr_rd_ok[0:0] + attribute \src "issuer_ls180.v:74255.3-74333.6" + wire width 8 $1\cr_wr[7:0] + attribute \src "issuer_ls180.v:74255.3-74333.6" + wire $1\cr_wr_ok[0:0] + attribute \src "issuer_ls180.v:74255.3-74333.6" + wire width 5 $1\ea[4:0] + attribute \src "issuer_ls180.v:74255.3-74333.6" + wire $1\ea_ok[0:0] + attribute \src "issuer_ls180.v:74255.3-74333.6" + wire width 3 $1\fast1[2:0] + attribute \src "issuer_ls180.v:74255.3-74333.6" + wire $1\fast1_ok[0:0] + attribute \src "issuer_ls180.v:74255.3-74333.6" + wire width 3 $1\fast2[2:0] + attribute \src "issuer_ls180.v:74255.3-74333.6" + wire $1\fast2_ok[0:0] + attribute \src "issuer_ls180.v:74255.3-74333.6" + wire width 3 $1\fasto1[2:0] + attribute \src "issuer_ls180.v:74255.3-74333.6" + wire $1\fasto1_ok[0:0] + attribute \src "issuer_ls180.v:74255.3-74333.6" + wire width 3 $1\fasto2[2:0] + attribute \src "issuer_ls180.v:74255.3-74333.6" + wire $1\fasto2_ok[0:0] + attribute \src "issuer_ls180.v:74255.3-74333.6" + wire width 12 $1\fn_unit[11:0] + attribute \src "issuer_ls180.v:74255.3-74333.6" + wire width 2 $1\input_carry[1:0] + attribute \src "issuer_ls180.v:74255.3-74333.6" + wire width 32 $1\insn[31:0] + attribute \src "issuer_ls180.v:74255.3-74333.6" + wire width 7 $1\insn_type[6:0] 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"issuer_ls180.v:74255.3-74333.6" + wire $1\reg3_ok[0:0] + attribute \src "issuer_ls180.v:74255.3-74333.6" + wire width 5 $1\rego[4:0] + attribute \src "issuer_ls180.v:74255.3-74333.6" + wire $1\rego_ok[0:0] + attribute \src "issuer_ls180.v:74255.3-74333.6" + wire width 10 $1\spr1[9:0] + attribute \src "issuer_ls180.v:74255.3-74333.6" + wire $1\spr1_ok[0:0] + attribute \src "issuer_ls180.v:74255.3-74333.6" + wire width 10 $1\spro[9:0] + attribute \src "issuer_ls180.v:74255.3-74333.6" + wire $1\spro_ok[0:0] + attribute \src "issuer_ls180.v:74189.3-74198.6" + wire $1\tmp_tmp_lk[0:0] + attribute \src "issuer_ls180.v:74225.3-74234.6" + wire width 13 $1\tmp_tmp_trapaddr[12:0] + attribute \src "issuer_ls180.v:74199.3-74214.6" + wire width 3 $1\tmp_xer_in[2:0] + attribute \src "issuer_ls180.v:74215.3-74224.6" + wire $1\tmp_xer_out[0:0] + attribute \src "issuer_ls180.v:74255.3-74333.6" + wire width 13 $1\trapaddr[12:0] + attribute \src "issuer_ls180.v:74255.3-74333.6" + wire width 7 $1\traptype[6:0] + attribute \src "issuer_ls180.v:74255.3-74333.6" + wire width 3 $1\xer_in[2:0] + attribute \src "issuer_ls180.v:74255.3-74333.6" + wire $1\xer_out[0:0] + attribute \src "issuer_ls180.v:74255.3-74333.6" + wire width 3 $2\fast1[2:0] + attribute \src "issuer_ls180.v:74255.3-74333.6" + wire $2\fast1_ok[0:0] + attribute \src "issuer_ls180.v:74255.3-74333.6" + wire width 3 $2\fast2[2:0] + attribute \src "issuer_ls180.v:74255.3-74333.6" + wire $2\fast2_ok[0:0] + attribute \src "issuer_ls180.v:74255.3-74333.6" + wire width 3 $2\fasto1[2:0] + attribute \src "issuer_ls180.v:74255.3-74333.6" + wire $2\fasto1_ok[0:0] + attribute \src "issuer_ls180.v:74255.3-74333.6" + wire width 3 $2\fasto2[2:0] + attribute \src "issuer_ls180.v:74255.3-74333.6" + wire $2\fasto2_ok[0:0] + attribute \src "issuer_ls180.v:74235.3-74254.6" + wire $2\is_priv_insn[0:0] + attribute \src "issuer_ls180.v:74199.3-74214.6" + wire width 3 $2\tmp_xer_in[2:0] + attribute \src "issuer_ls180.v:74041.18-74041.120" + wire $and$issuer_ls180.v:74041$3527_Y + attribute \src "issuer_ls180.v:74042.18-74042.123" + wire $and$issuer_ls180.v:74042$3528_Y + attribute \src "issuer_ls180.v:74043.18-74043.124" + wire $and$issuer_ls180.v:74043$3529_Y + attribute \src "issuer_ls180.v:74037.18-74037.122" + wire $eq$issuer_ls180.v:74037$3523_Y + attribute \src "issuer_ls180.v:74038.18-74038.122" + wire $eq$issuer_ls180.v:74038$3524_Y + attribute \src "issuer_ls180.v:74039.18-74039.122" + wire $eq$issuer_ls180.v:74039$3525_Y + attribute \src "issuer_ls180.v:74040.18-74040.122" + wire $eq$issuer_ls180.v:74040$3526_Y + attribute \src "issuer_ls180.v:74044.18-74044.122" + wire $eq$issuer_ls180.v:74044$3530_Y + attribute \src "issuer_ls180.v:74045.18-74045.116" + wire $eq$issuer_ls180.v:74045$3531_Y + attribute \src "issuer_ls180.v:74046.18-74046.116" + wire $eq$issuer_ls180.v:74046$3532_Y + attribute \src "issuer_ls180.v:74048.18-74048.116" + wire $eq$issuer_ls180.v:74048$3534_Y + attribute \src "issuer_ls180.v:74047.18-74047.110" + wire $or$issuer_ls180.v:74047$3533_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:856" + wire \$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:858" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:860" + wire \$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:864" + wire \$19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:886" + wire \$21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:887" + wire \$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:888" + wire \$25 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:889" + wire \$27 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:920" + wire \$29 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:921" + wire \$31 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:921" + wire \$33 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:930" + wire \$35 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:92" + wire width 8 output 5 \asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + wire input 1 \bigendian + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:42" + wire width 64 output 39 \cia + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 3 output 30 \cr_in1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 31 \cr_in1_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 3 output 32 \cr_in2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 3 output 34 \cr_in2$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 33 \cr_in2_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 35 \cr_in2_ok$2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 3 output 36 \cr_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 37 \cr_out_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 8 output 51 \cr_rd + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 52 \cr_rd_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 8 output 53 \cr_wr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 54 \cr_wr_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:11" + wire width 64 input 56 \cur_dec + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:10" + wire input 57 \cur_eint + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:9" + wire width 64 input 3 \cur_msr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:8" + wire width 64 input 2 \cur_pc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 \dec_BA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 \dec_BB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 \dec_BC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 \dec_BI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 \dec_BO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 \dec_BT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 8 \dec_FXM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire \dec_LK + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire \dec_OE + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 \dec_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 \dec_RB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 \dec_RS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 \dec_RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire \dec_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 10 \dec_SPR + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \dec_XL_BT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 10 \dec_XL_XO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 3 \dec_X_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 3 \dec_X_BFA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 3 \dec_a_fast_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \dec_a_fast_a_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 5 \dec_a_reg_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \dec_a_reg_a_ok + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:85" + wire width 3 \dec_a_sel_in + attribute \enum_base_type "SPR" + attribute \enum_value_0000000001 "XER" + attribute \enum_value_0000000011 "DSCR" + attribute \enum_value_0000001000 "LR" + attribute \enum_value_0000001001 "CTR" + attribute \enum_value_0000001101 "AMR" + attribute \enum_value_0000010001 "DSCR_priv" + attribute \enum_value_0000010010 "DSISR" + attribute \enum_value_0000010011 "DAR" + attribute \enum_value_0000010110 "DEC" + attribute \enum_value_0000011010 "SRR0" + attribute \enum_value_0000011011 "SRR1" + attribute \enum_value_0000011100 "CFAR" + attribute \enum_value_0000011101 "AMR_priv" + attribute \enum_value_0000110000 "PIDR" + attribute \enum_value_0000111101 "IAMR" + attribute \enum_value_0010000000 "TFHAR" + attribute \enum_value_0010000001 "TFIAR" + attribute \enum_value_0010000010 "TEXASR" + attribute \enum_value_0010000011 "TEXASRU" + attribute \enum_value_0010001000 "CTRL" + attribute \enum_value_0010010000 "TIDR" + attribute \enum_value_0010011000 "CTRL_priv" + attribute \enum_value_0010011001 "FSCR" + attribute \enum_value_0010011101 "UAMOR" + attribute \enum_value_0010011110 "GSR" + attribute \enum_value_0010011111 "PSPB" + attribute \enum_value_0010110000 "DPDES" + attribute \enum_value_0010110100 "DAWR0" + attribute \enum_value_0010111010 "RPR" + attribute \enum_value_0010111011 "CIABR" + attribute \enum_value_0010111100 "DAWRX0" + attribute \enum_value_0010111110 "HFSCR" + attribute \enum_value_0100000000 "VRSAVE" + attribute \enum_value_0100000011 "SPRG3" + attribute \enum_value_0100001100 "TB" + attribute \enum_value_0100001101 "TBU" + attribute \enum_value_0100010000 "SPRG0_priv" + attribute \enum_value_0100010001 "SPRG1_priv" + attribute \enum_value_0100010010 "SPRG2_priv" + attribute \enum_value_0100010011 "SPRG3_priv" + attribute \enum_value_0100011011 "CIR" + attribute \enum_value_0100011100 "TBL" + attribute \enum_value_0100011101 "TBU_hypv" + attribute \enum_value_0100011110 "TBU40" + attribute \enum_value_0100011111 "PVR" + attribute \enum_value_0100110000 "HSPRG0" + attribute \enum_value_0100110001 "HSPRG1" + attribute \enum_value_0100110010 "HDSISR" + attribute \enum_value_0100110011 "HDAR" + attribute \enum_value_0100110100 "SPURR" + attribute \enum_value_0100110101 "PURR" + attribute \enum_value_0100110110 "HDEC" + attribute \enum_value_0100111001 "HRMOR" + attribute \enum_value_0100111010 "HSRR0" + attribute \enum_value_0100111011 "HSRR1" + attribute \enum_value_0100111110 "LPCR" + attribute \enum_value_0100111111 "LPIDR" + attribute \enum_value_0101010000 "HMER" + attribute \enum_value_0101010001 "HMEER" + attribute \enum_value_0101010010 "PCR" + attribute \enum_value_0101010011 "HEIR" + attribute \enum_value_0101011101 "AMOR" + attribute \enum_value_0110111110 "TIR" + attribute \enum_value_0111010000 "PTCR" + attribute \enum_value_1100000000 "SIER" + attribute \enum_value_1100000001 "MMCR2" + attribute \enum_value_1100000010 "MMCRA" + attribute \enum_value_1100000011 "PMC1" + attribute \enum_value_1100000100 "PMC2" + attribute \enum_value_1100000101 "PMC3" + attribute \enum_value_1100000110 "PMC4" + attribute \enum_value_1100000111 "PMC5" + attribute \enum_value_1100001000 "PMC6" + attribute \enum_value_1100001011 "MMCR0" + attribute \enum_value_1100001100 "SIAR" + attribute \enum_value_1100001101 "SDAR" + attribute \enum_value_1100001110 "MMCR1" + attribute \enum_value_1100010000 "SIER_priv" + attribute \enum_value_1100010001 "MMCR2_priv" + attribute \enum_value_1100010010 "MMCRA_priv" + attribute \enum_value_1100010011 "PMC1_priv" + attribute \enum_value_1100010100 "PMC2_priv" + attribute \enum_value_1100010101 "PMC3_priv" + attribute \enum_value_1100010110 "PMC4_priv" + attribute \enum_value_1100010111 "PMC5_priv" + attribute \enum_value_1100011000 "PMC6_priv" + attribute \enum_value_1100011011 "MMCR0_priv" + attribute \enum_value_1100011100 "SIAR_priv" + attribute \enum_value_1100011101 "SDAR_priv" + attribute \enum_value_1100011110 "MMCR1_priv" + attribute \enum_value_1100100000 "BESCRS" + attribute \enum_value_1100100001 "BESCRSU" + attribute \enum_value_1100100010 "BESCRR" + attribute \enum_value_1100100011 "BESCRRU" + attribute \enum_value_1100100100 "EBBHR" + attribute \enum_value_1100100101 "EBBRR" + attribute \enum_value_1100100110 "BESCR" + attribute \enum_value_1100101000 "reserved808" + attribute \enum_value_1100101001 "reserved809" + attribute \enum_value_1100101010 "reserved810" + attribute \enum_value_1100101011 "reserved811" + attribute \enum_value_1100101111 "TAR" + attribute \enum_value_1100110000 "ASDR" + attribute \enum_value_1100110111 "PSSCR" + attribute \enum_value_1101010000 "IC" + attribute \enum_value_1101010001 "VTB" + attribute \enum_value_1101010111 "PSSCR_hypv" + attribute \enum_value_1110000000 "PPR" + attribute \enum_value_1110000010 "PPR32" + attribute \enum_value_1111111111 "PIR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 10 \dec_a_spr_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \dec_a_spr_a_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 3 \dec_b_fast_b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \dec_b_fast_b_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 5 \dec_b_reg_b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \dec_b_reg_b_ok + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:175" + wire width 4 \dec_b_sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 5 \dec_c_reg_c + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \dec_c_reg_c_ok + attribute \enum_base_type "In3Sel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RS" + attribute \enum_value_10 "RB" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:279" + wire width 2 \dec_c_sel_in + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 \dec_cr_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 3 \dec_cr_in_cr_bitfield + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 3 \dec_cr_in_cr_bitfield_b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \dec_cr_in_cr_bitfield_b_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 3 \dec_cr_in_cr_bitfield_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \dec_cr_in_cr_bitfield_o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \dec_cr_in_cr_bitfield_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 8 \dec_cr_in_cr_fxm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \dec_cr_in_cr_fxm_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:485" + wire width 32 \dec_cr_in_insn_in + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:484" + wire width 3 \dec_cr_in_sel_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 \dec_cr_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 3 \dec_cr_out_cr_bitfield + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \dec_cr_out_cr_bitfield_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 8 \dec_cr_out_cr_fxm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \dec_cr_out_cr_fxm_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:550" + wire width 32 \dec_cr_out_insn_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:548" + wire \dec_cr_out_rc_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:549" + wire width 3 \dec_cr_out_sel_in + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \dec_cry_in + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 12 \dec_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 \dec_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 \dec_in2_sel + attribute \enum_base_type "In3Sel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RS" + attribute \enum_value_10 "RB" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \dec_in3_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 7 \dec_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:882" + wire \dec_irq_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec_is_32b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec_lk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 3 \dec_o2_fast_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \dec_o2_fast_o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:363" + wire \dec_o2_lk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 5 \dec_o2_reg_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \dec_o2_reg_o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 3 \dec_o_fast_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \dec_o_fast_o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 5 \dec_o_reg_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \dec_o_reg_o_ok + attribute \enum_base_type "OutSel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RT" + attribute \enum_value_10 "RA" + attribute \enum_value_11 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:308" + wire width 2 \dec_o_sel_in + attribute \enum_base_type "SPR" + attribute \enum_value_0000000001 "XER" + attribute \enum_value_0000000011 "DSCR" + attribute \enum_value_0000001000 "LR" + attribute \enum_value_0000001001 "CTR" + attribute \enum_value_0000001101 "AMR" + attribute \enum_value_0000010001 "DSCR_priv" + attribute \enum_value_0000010010 "DSISR" + attribute \enum_value_0000010011 "DAR" + attribute \enum_value_0000010110 "DEC" + attribute \enum_value_0000011010 "SRR0" + attribute \enum_value_0000011011 "SRR1" + attribute \enum_value_0000011100 "CFAR" + attribute \enum_value_0000011101 "AMR_priv" + attribute \enum_value_0000110000 "PIDR" + attribute \enum_value_0000111101 "IAMR" + attribute \enum_value_0010000000 "TFHAR" + attribute \enum_value_0010000001 "TFIAR" + attribute \enum_value_0010000010 "TEXASR" + attribute \enum_value_0010000011 "TEXASRU" + attribute \enum_value_0010001000 "CTRL" + attribute \enum_value_0010010000 "TIDR" + attribute \enum_value_0010011000 "CTRL_priv" + attribute \enum_value_0010011001 "FSCR" + attribute \enum_value_0010011101 "UAMOR" + attribute \enum_value_0010011110 "GSR" + attribute \enum_value_0010011111 "PSPB" + attribute \enum_value_0010110000 "DPDES" + attribute \enum_value_0010110100 "DAWR0" + attribute \enum_value_0010111010 "RPR" + attribute \enum_value_0010111011 "CIABR" + attribute \enum_value_0010111100 "DAWRX0" + attribute \enum_value_0010111110 "HFSCR" + attribute \enum_value_0100000000 "VRSAVE" + attribute \enum_value_0100000011 "SPRG3" + attribute \enum_value_0100001100 "TB" + attribute \enum_value_0100001101 "TBU" + attribute \enum_value_0100010000 "SPRG0_priv" + attribute \enum_value_0100010001 "SPRG1_priv" + attribute \enum_value_0100010010 "SPRG2_priv" + attribute \enum_value_0100010011 "SPRG3_priv" + attribute \enum_value_0100011011 "CIR" + attribute \enum_value_0100011100 "TBL" + attribute \enum_value_0100011101 "TBU_hypv" + attribute \enum_value_0100011110 "TBU40" + attribute \enum_value_0100011111 "PVR" + attribute \enum_value_0100110000 "HSPRG0" + attribute \enum_value_0100110001 "HSPRG1" + attribute \enum_value_0100110010 "HDSISR" + attribute \enum_value_0100110011 "HDAR" + attribute \enum_value_0100110100 "SPURR" + attribute \enum_value_0100110101 "PURR" + attribute \enum_value_0100110110 "HDEC" + attribute \enum_value_0100111001 "HRMOR" + attribute \enum_value_0100111010 "HSRR0" + attribute \enum_value_0100111011 "HSRR1" + attribute \enum_value_0100111110 "LPCR" + attribute \enum_value_0100111111 "LPIDR" + attribute \enum_value_0101010000 "HMER" + attribute \enum_value_0101010001 "HMEER" + attribute \enum_value_0101010010 "PCR" + attribute \enum_value_0101010011 "HEIR" + attribute \enum_value_0101011101 "AMOR" + attribute \enum_value_0110111110 "TIR" + attribute \enum_value_0111010000 "PTCR" + attribute \enum_value_1100000000 "SIER" + attribute \enum_value_1100000001 "MMCR2" + attribute \enum_value_1100000010 "MMCRA" + attribute \enum_value_1100000011 "PMC1" + attribute \enum_value_1100000100 "PMC2" + attribute \enum_value_1100000101 "PMC3" + attribute \enum_value_1100000110 "PMC4" + attribute \enum_value_1100000111 "PMC5" + attribute \enum_value_1100001000 "PMC6" + attribute \enum_value_1100001011 "MMCR0" + attribute \enum_value_1100001100 "SIAR" + attribute \enum_value_1100001101 "SDAR" + attribute \enum_value_1100001110 "MMCR1" + attribute \enum_value_1100010000 "SIER_priv" + attribute \enum_value_1100010001 "MMCR2_priv" + attribute \enum_value_1100010010 "MMCRA_priv" + attribute \enum_value_1100010011 "PMC1_priv" + attribute \enum_value_1100010100 "PMC2_priv" + attribute \enum_value_1100010101 "PMC3_priv" + attribute \enum_value_1100010110 "PMC4_priv" + attribute \enum_value_1100010111 "PMC5_priv" + attribute \enum_value_1100011000 "PMC6_priv" + attribute \enum_value_1100011011 "MMCR0_priv" + attribute \enum_value_1100011100 "SIAR_priv" + attribute \enum_value_1100011101 "SDAR_priv" + attribute \enum_value_1100011110 "MMCR1_priv" + attribute \enum_value_1100100000 "BESCRS" + attribute \enum_value_1100100001 "BESCRSU" + attribute \enum_value_1100100010 "BESCRR" + attribute \enum_value_1100100011 "BESCRRU" + attribute \enum_value_1100100100 "EBBHR" + attribute \enum_value_1100100101 "EBBRR" + attribute \enum_value_1100100110 "BESCR" + attribute \enum_value_1100101000 "reserved808" + attribute \enum_value_1100101001 "reserved809" + attribute \enum_value_1100101010 "reserved810" + attribute \enum_value_1100101011 "reserved811" + attribute \enum_value_1100101111 "TAR" + attribute \enum_value_1100110000 "ASDR" + attribute \enum_value_1100110111 "PSSCR" + attribute \enum_value_1101010000 "IC" + attribute \enum_value_1101010001 "VTB" + attribute \enum_value_1101010111 "PSSCR_hypv" + attribute \enum_value_1110000000 "PPR" + attribute \enum_value_1110000010 "PPR32" + attribute \enum_value_1111111111 "PIR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 10 \dec_o_spr_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \dec_o_spr_o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \dec_oe_oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \dec_oe_oe_ok + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:441" + wire width 2 \dec_oe_sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + wire width 32 \dec_opcode_in + attribute \enum_base_type "OutSel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RT" + attribute \enum_value_10 "RA" + attribute \enum_value_11 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \dec_out_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \dec_rc_rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \dec_rc_rc_ok + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \dec_rc_sel + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:404" + wire width 2 \dec_rc_sel_in + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \dec_upd + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 5 output 8 \ea + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 9 \ea_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:881" + wire \ext_irq_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 3 output 22 \fast1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 23 \fast1_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 3 output 24 \fast2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 25 \fast2_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 3 output 26 \fasto1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 27 \fasto1_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 3 output 28 \fasto2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 29 \fasto2_ok + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:47" + wire width 12 output 42 \fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:884" + wire \illeg_ok + attribute \src "issuer_ls180.v:72504.7-72504.15" + wire \initial + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:51" + wire width 2 output 48 \input_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:45" + wire width 32 output 40 \insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:405" + wire width 32 \insn_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:364" + wire width 32 \insn_in$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:442" + wire width 32 \insn_in$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:86" + wire width 32 \insn_in$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:176" + wire width 32 \insn_in$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:280" + wire width 32 \insn_in$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:309" + wire width 32 \insn_in$9 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:46" + wire width 7 output 41 \insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:56" + wire output 55 \is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:41" + wire \is_priv_insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:48" + wire output 43 \lk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:41" + wire width 64 output 38 \msr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 46 \oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 47 \oe_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:883" + wire \priv_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:442" + wire width 32 input 4 \raw_opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 44 \rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 45 \rc_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 5 output 10 \reg1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 11 \reg1_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 5 output 12 \reg2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 13 \reg2_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 5 output 14 \reg3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 15 \reg3_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 5 output 6 \rego + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 7 \rego_ok + attribute \enum_base_type "OutSel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RT" + attribute \enum_value_10 "RA" + attribute \enum_value_11 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:362" + wire width 2 \sel_in + attribute \enum_base_type "SPR" + attribute \enum_value_0000000001 "XER" + attribute \enum_value_0000000011 "DSCR" + attribute \enum_value_0000001000 "LR" + attribute \enum_value_0000001001 "CTR" + attribute \enum_value_0000001101 "AMR" + attribute \enum_value_0000010001 "DSCR_priv" + attribute \enum_value_0000010010 "DSISR" + attribute \enum_value_0000010011 "DAR" + attribute \enum_value_0000010110 "DEC" + attribute \enum_value_0000011010 "SRR0" + attribute \enum_value_0000011011 "SRR1" + attribute \enum_value_0000011100 "CFAR" + attribute \enum_value_0000011101 "AMR_priv" + attribute \enum_value_0000110000 "PIDR" + attribute \enum_value_0000111101 "IAMR" + attribute \enum_value_0010000000 "TFHAR" + attribute \enum_value_0010000001 "TFIAR" + attribute \enum_value_0010000010 "TEXASR" + attribute \enum_value_0010000011 "TEXASRU" + attribute \enum_value_0010001000 "CTRL" + attribute \enum_value_0010010000 "TIDR" + attribute \enum_value_0010011000 "CTRL_priv" + attribute \enum_value_0010011001 "FSCR" + attribute \enum_value_0010011101 "UAMOR" + attribute \enum_value_0010011110 "GSR" + attribute \enum_value_0010011111 "PSPB" + attribute \enum_value_0010110000 "DPDES" + attribute \enum_value_0010110100 "DAWR0" + attribute \enum_value_0010111010 "RPR" + attribute \enum_value_0010111011 "CIABR" + attribute \enum_value_0010111100 "DAWRX0" + attribute \enum_value_0010111110 "HFSCR" + attribute \enum_value_0100000000 "VRSAVE" + attribute \enum_value_0100000011 "SPRG3" + attribute \enum_value_0100001100 "TB" + attribute \enum_value_0100001101 "TBU" + attribute \enum_value_0100010000 "SPRG0_priv" + attribute \enum_value_0100010001 "SPRG1_priv" + attribute \enum_value_0100010010 "SPRG2_priv" + attribute \enum_value_0100010011 "SPRG3_priv" + attribute \enum_value_0100011011 "CIR" + attribute \enum_value_0100011100 "TBL" + attribute \enum_value_0100011101 "TBU_hypv" + attribute \enum_value_0100011110 "TBU40" + attribute \enum_value_0100011111 "PVR" + attribute \enum_value_0100110000 "HSPRG0" + attribute \enum_value_0100110001 "HSPRG1" + attribute \enum_value_0100110010 "HDSISR" + attribute \enum_value_0100110011 "HDAR" + attribute \enum_value_0100110100 "SPURR" + attribute \enum_value_0100110101 "PURR" + attribute \enum_value_0100110110 "HDEC" + attribute \enum_value_0100111001 "HRMOR" + attribute \enum_value_0100111010 "HSRR0" + attribute \enum_value_0100111011 "HSRR1" + attribute \enum_value_0100111110 "LPCR" + attribute \enum_value_0100111111 "LPIDR" + attribute \enum_value_0101010000 "HMER" + attribute \enum_value_0101010001 "HMEER" + attribute \enum_value_0101010010 "PCR" + attribute \enum_value_0101010011 "HEIR" + attribute \enum_value_0101011101 "AMOR" + attribute \enum_value_0110111110 "TIR" + attribute \enum_value_0111010000 "PTCR" + attribute \enum_value_1100000000 "SIER" + attribute \enum_value_1100000001 "MMCR2" + attribute \enum_value_1100000010 "MMCRA" + attribute \enum_value_1100000011 "PMC1" + attribute \enum_value_1100000100 "PMC2" + attribute \enum_value_1100000101 "PMC3" + attribute \enum_value_1100000110 "PMC4" + attribute \enum_value_1100000111 "PMC5" + attribute \enum_value_1100001000 "PMC6" + attribute \enum_value_1100001011 "MMCR0" + attribute \enum_value_1100001100 "SIAR" + attribute \enum_value_1100001101 "SDAR" + attribute \enum_value_1100001110 "MMCR1" + attribute \enum_value_1100010000 "SIER_priv" + attribute \enum_value_1100010001 "MMCR2_priv" + attribute \enum_value_1100010010 "MMCRA_priv" + attribute \enum_value_1100010011 "PMC1_priv" + attribute \enum_value_1100010100 "PMC2_priv" + attribute \enum_value_1100010101 "PMC3_priv" + attribute \enum_value_1100010110 "PMC4_priv" + attribute \enum_value_1100010111 "PMC5_priv" + attribute \enum_value_1100011000 "PMC6_priv" + attribute \enum_value_1100011011 "MMCR0_priv" + attribute \enum_value_1100011100 "SIAR_priv" + attribute \enum_value_1100011101 "SDAR_priv" + attribute \enum_value_1100011110 "MMCR1_priv" + attribute \enum_value_1100100000 "BESCRS" + attribute \enum_value_1100100001 "BESCRSU" + attribute \enum_value_1100100010 "BESCRR" + attribute \enum_value_1100100011 "BESCRRU" + attribute \enum_value_1100100100 "EBBHR" + attribute \enum_value_1100100101 "EBBRR" + attribute \enum_value_1100100110 "BESCR" + attribute \enum_value_1100101000 "reserved808" + attribute \enum_value_1100101001 "reserved809" + attribute \enum_value_1100101010 "reserved810" + attribute \enum_value_1100101011 "reserved811" + attribute \enum_value_1100101111 "TAR" + attribute \enum_value_1100110000 "ASDR" + attribute \enum_value_1100110111 "PSSCR" + attribute \enum_value_1101010000 "IC" + attribute \enum_value_1101010001 "VTB" + attribute \enum_value_1101010111 "PSSCR_hypv" + attribute \enum_value_1110000000 "PPR" + attribute \enum_value_1110000010 "PPR32" + attribute \enum_value_1111111111 "PIR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 10 output 18 \spr1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 19 \spr1_ok + attribute \enum_base_type "SPR" + attribute \enum_value_0000000001 "XER" + attribute \enum_value_0000000011 "DSCR" + attribute \enum_value_0000001000 "LR" + attribute \enum_value_0000001001 "CTR" + attribute \enum_value_0000001101 "AMR" + attribute \enum_value_0000010001 "DSCR_priv" + attribute \enum_value_0000010010 "DSISR" + attribute \enum_value_0000010011 "DAR" + attribute \enum_value_0000010110 "DEC" + attribute \enum_value_0000011010 "SRR0" + attribute \enum_value_0000011011 "SRR1" + attribute \enum_value_0000011100 "CFAR" + attribute \enum_value_0000011101 "AMR_priv" + attribute \enum_value_0000110000 "PIDR" + attribute \enum_value_0000111101 "IAMR" + attribute \enum_value_0010000000 "TFHAR" + attribute \enum_value_0010000001 "TFIAR" + attribute \enum_value_0010000010 "TEXASR" + attribute \enum_value_0010000011 "TEXASRU" + attribute \enum_value_0010001000 "CTRL" + attribute \enum_value_0010010000 "TIDR" + attribute \enum_value_0010011000 "CTRL_priv" + attribute \enum_value_0010011001 "FSCR" + attribute \enum_value_0010011101 "UAMOR" + attribute \enum_value_0010011110 "GSR" + attribute \enum_value_0010011111 "PSPB" + attribute \enum_value_0010110000 "DPDES" + attribute \enum_value_0010110100 "DAWR0" + attribute \enum_value_0010111010 "RPR" + attribute \enum_value_0010111011 "CIABR" + attribute \enum_value_0010111100 "DAWRX0" + attribute \enum_value_0010111110 "HFSCR" + attribute \enum_value_0100000000 "VRSAVE" + attribute \enum_value_0100000011 "SPRG3" + attribute \enum_value_0100001100 "TB" + attribute \enum_value_0100001101 "TBU" + attribute \enum_value_0100010000 "SPRG0_priv" + attribute \enum_value_0100010001 "SPRG1_priv" + attribute \enum_value_0100010010 "SPRG2_priv" + attribute \enum_value_0100010011 "SPRG3_priv" + attribute \enum_value_0100011011 "CIR" + attribute \enum_value_0100011100 "TBL" + attribute \enum_value_0100011101 "TBU_hypv" + attribute \enum_value_0100011110 "TBU40" + attribute \enum_value_0100011111 "PVR" + attribute \enum_value_0100110000 "HSPRG0" + attribute \enum_value_0100110001 "HSPRG1" + attribute \enum_value_0100110010 "HDSISR" + attribute \enum_value_0100110011 "HDAR" + attribute \enum_value_0100110100 "SPURR" + attribute \enum_value_0100110101 "PURR" + attribute \enum_value_0100110110 "HDEC" + attribute \enum_value_0100111001 "HRMOR" + attribute \enum_value_0100111010 "HSRR0" + attribute \enum_value_0100111011 "HSRR1" + attribute \enum_value_0100111110 "LPCR" + attribute \enum_value_0100111111 "LPIDR" + attribute \enum_value_0101010000 "HMER" + attribute \enum_value_0101010001 "HMEER" + attribute \enum_value_0101010010 "PCR" + attribute \enum_value_0101010011 "HEIR" + attribute \enum_value_0101011101 "AMOR" + attribute \enum_value_0110111110 "TIR" + attribute \enum_value_0111010000 "PTCR" + attribute \enum_value_1100000000 "SIER" + attribute \enum_value_1100000001 "MMCR2" + attribute \enum_value_1100000010 "MMCRA" + attribute \enum_value_1100000011 "PMC1" + attribute \enum_value_1100000100 "PMC2" + attribute \enum_value_1100000101 "PMC3" + attribute \enum_value_1100000110 "PMC4" + attribute \enum_value_1100000111 "PMC5" + attribute \enum_value_1100001000 "PMC6" + attribute \enum_value_1100001011 "MMCR0" + attribute \enum_value_1100001100 "SIAR" + attribute \enum_value_1100001101 "SDAR" + attribute \enum_value_1100001110 "MMCR1" + attribute \enum_value_1100010000 "SIER_priv" + attribute \enum_value_1100010001 "MMCR2_priv" + attribute \enum_value_1100010010 "MMCRA_priv" + attribute \enum_value_1100010011 "PMC1_priv" + attribute \enum_value_1100010100 "PMC2_priv" + attribute \enum_value_1100010101 "PMC3_priv" + attribute \enum_value_1100010110 "PMC4_priv" + attribute \enum_value_1100010111 "PMC5_priv" + attribute \enum_value_1100011000 "PMC6_priv" + attribute \enum_value_1100011011 "MMCR0_priv" + attribute \enum_value_1100011100 "SIAR_priv" + attribute \enum_value_1100011101 "SDAR_priv" + attribute \enum_value_1100011110 "MMCR1_priv" + attribute \enum_value_1100100000 "BESCRS" + attribute \enum_value_1100100001 "BESCRSU" + attribute \enum_value_1100100010 "BESCRR" + attribute \enum_value_1100100011 "BESCRRU" + attribute \enum_value_1100100100 "EBBHR" + attribute \enum_value_1100100101 "EBBRR" + attribute \enum_value_1100100110 "BESCR" + attribute \enum_value_1100101000 "reserved808" + attribute \enum_value_1100101001 "reserved809" + attribute \enum_value_1100101010 "reserved810" + attribute \enum_value_1100101011 "reserved811" + attribute \enum_value_1100101111 "TAR" + attribute \enum_value_1100110000 "ASDR" + attribute \enum_value_1100110111 "PSSCR" + attribute \enum_value_1101010000 "IC" + attribute \enum_value_1101010001 "VTB" + attribute \enum_value_1101010111 "PSSCR_hypv" + attribute \enum_value_1110000000 "PPR" + attribute \enum_value_1110000010 "PPR32" + attribute \enum_value_1111111111 "PIR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 10 output 16 \spro + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 17 \spro_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:92" + wire width 8 \tmp_asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 3 \tmp_cr_in1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \tmp_cr_in1_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 3 \tmp_cr_in2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 3 \tmp_cr_in2$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \tmp_cr_in2_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \tmp_cr_in2_ok$12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 3 \tmp_cr_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \tmp_cr_out_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 5 \tmp_ea + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \tmp_ea_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 3 \tmp_fast1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \tmp_fast1_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 3 \tmp_fast2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \tmp_fast2_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 3 \tmp_fasto1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \tmp_fasto1_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 3 \tmp_fasto2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \tmp_fasto2_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 5 \tmp_reg1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \tmp_reg1_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 5 \tmp_reg2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \tmp_reg2_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 5 \tmp_reg3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \tmp_reg3_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 5 \tmp_rego + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \tmp_rego_ok + attribute \enum_base_type "SPR" + attribute \enum_value_0000000001 "XER" + attribute \enum_value_0000000011 "DSCR" + attribute \enum_value_0000001000 "LR" + attribute \enum_value_0000001001 "CTR" + attribute \enum_value_0000001101 "AMR" + attribute \enum_value_0000010001 "DSCR_priv" + attribute \enum_value_0000010010 "DSISR" + attribute \enum_value_0000010011 "DAR" + attribute \enum_value_0000010110 "DEC" + attribute \enum_value_0000011010 "SRR0" + attribute \enum_value_0000011011 "SRR1" + attribute \enum_value_0000011100 "CFAR" + attribute \enum_value_0000011101 "AMR_priv" + attribute \enum_value_0000110000 "PIDR" + attribute \enum_value_0000111101 "IAMR" + attribute \enum_value_0010000000 "TFHAR" + attribute \enum_value_0010000001 "TFIAR" + attribute \enum_value_0010000010 "TEXASR" + attribute \enum_value_0010000011 "TEXASRU" + attribute \enum_value_0010001000 "CTRL" + attribute \enum_value_0010010000 "TIDR" + attribute \enum_value_0010011000 "CTRL_priv" + attribute \enum_value_0010011001 "FSCR" + attribute \enum_value_0010011101 "UAMOR" + attribute \enum_value_0010011110 "GSR" + attribute \enum_value_0010011111 "PSPB" + attribute \enum_value_0010110000 "DPDES" + attribute \enum_value_0010110100 "DAWR0" + attribute \enum_value_0010111010 "RPR" + attribute \enum_value_0010111011 "CIABR" + attribute \enum_value_0010111100 "DAWRX0" + attribute \enum_value_0010111110 "HFSCR" + attribute \enum_value_0100000000 "VRSAVE" + attribute \enum_value_0100000011 "SPRG3" + attribute \enum_value_0100001100 "TB" + attribute \enum_value_0100001101 "TBU" + attribute \enum_value_0100010000 "SPRG0_priv" + attribute \enum_value_0100010001 "SPRG1_priv" + attribute \enum_value_0100010010 "SPRG2_priv" + attribute \enum_value_0100010011 "SPRG3_priv" + attribute \enum_value_0100011011 "CIR" + attribute \enum_value_0100011100 "TBL" + attribute \enum_value_0100011101 "TBU_hypv" + attribute \enum_value_0100011110 "TBU40" + attribute \enum_value_0100011111 "PVR" + attribute \enum_value_0100110000 "HSPRG0" + attribute \enum_value_0100110001 "HSPRG1" + attribute \enum_value_0100110010 "HDSISR" + attribute \enum_value_0100110011 "HDAR" + attribute \enum_value_0100110100 "SPURR" + attribute \enum_value_0100110101 "PURR" + attribute \enum_value_0100110110 "HDEC" + attribute \enum_value_0100111001 "HRMOR" + attribute \enum_value_0100111010 "HSRR0" + attribute \enum_value_0100111011 "HSRR1" + attribute \enum_value_0100111110 "LPCR" + attribute \enum_value_0100111111 "LPIDR" + attribute \enum_value_0101010000 "HMER" + attribute \enum_value_0101010001 "HMEER" + attribute \enum_value_0101010010 "PCR" + attribute \enum_value_0101010011 "HEIR" + attribute \enum_value_0101011101 "AMOR" + attribute \enum_value_0110111110 "TIR" + attribute \enum_value_0111010000 "PTCR" + attribute \enum_value_1100000000 "SIER" + attribute \enum_value_1100000001 "MMCR2" + attribute \enum_value_1100000010 "MMCRA" + attribute \enum_value_1100000011 "PMC1" + attribute \enum_value_1100000100 "PMC2" + attribute \enum_value_1100000101 "PMC3" + attribute \enum_value_1100000110 "PMC4" + attribute \enum_value_1100000111 "PMC5" + attribute \enum_value_1100001000 "PMC6" + attribute \enum_value_1100001011 "MMCR0" + attribute \enum_value_1100001100 "SIAR" + attribute \enum_value_1100001101 "SDAR" + attribute \enum_value_1100001110 "MMCR1" + attribute \enum_value_1100010000 "SIER_priv" + attribute \enum_value_1100010001 "MMCR2_priv" + attribute \enum_value_1100010010 "MMCRA_priv" + attribute \enum_value_1100010011 "PMC1_priv" + attribute \enum_value_1100010100 "PMC2_priv" + attribute \enum_value_1100010101 "PMC3_priv" + attribute \enum_value_1100010110 "PMC4_priv" + attribute \enum_value_1100010111 "PMC5_priv" + attribute \enum_value_1100011000 "PMC6_priv" + attribute \enum_value_1100011011 "MMCR0_priv" + attribute \enum_value_1100011100 "SIAR_priv" + attribute \enum_value_1100011101 "SDAR_priv" + attribute \enum_value_1100011110 "MMCR1_priv" + attribute \enum_value_1100100000 "BESCRS" + attribute \enum_value_1100100001 "BESCRSU" + attribute \enum_value_1100100010 "BESCRR" + attribute \enum_value_1100100011 "BESCRRU" + attribute \enum_value_1100100100 "EBBHR" + attribute \enum_value_1100100101 "EBBRR" + attribute \enum_value_1100100110 "BESCR" + attribute \enum_value_1100101000 "reserved808" + attribute \enum_value_1100101001 "reserved809" + attribute \enum_value_1100101010 "reserved810" + attribute \enum_value_1100101011 "reserved811" + attribute \enum_value_1100101111 "TAR" + attribute \enum_value_1100110000 "ASDR" + attribute \enum_value_1100110111 "PSSCR" + attribute \enum_value_1101010000 "IC" + attribute \enum_value_1101010001 "VTB" + attribute \enum_value_1101010111 "PSSCR_hypv" + attribute \enum_value_1110000000 "PPR" + attribute \enum_value_1110000010 "PPR32" + attribute \enum_value_1111111111 "PIR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 10 \tmp_spr1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \tmp_spr1_ok + attribute \enum_base_type "SPR" + attribute \enum_value_0000000001 "XER" + attribute \enum_value_0000000011 "DSCR" + attribute \enum_value_0000001000 "LR" + attribute \enum_value_0000001001 "CTR" + attribute \enum_value_0000001101 "AMR" + attribute \enum_value_0000010001 "DSCR_priv" + attribute \enum_value_0000010010 "DSISR" + attribute \enum_value_0000010011 "DAR" + attribute \enum_value_0000010110 "DEC" + attribute \enum_value_0000011010 "SRR0" + attribute \enum_value_0000011011 "SRR1" + attribute \enum_value_0000011100 "CFAR" + attribute \enum_value_0000011101 "AMR_priv" + attribute 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\enum_value_0100010000 "SPRG0_priv" + attribute \enum_value_0100010001 "SPRG1_priv" + attribute \enum_value_0100010010 "SPRG2_priv" + attribute \enum_value_0100010011 "SPRG3_priv" + attribute \enum_value_0100011011 "CIR" + attribute \enum_value_0100011100 "TBL" + attribute \enum_value_0100011101 "TBU_hypv" + attribute \enum_value_0100011110 "TBU40" + attribute \enum_value_0100011111 "PVR" + attribute \enum_value_0100110000 "HSPRG0" + attribute \enum_value_0100110001 "HSPRG1" + attribute \enum_value_0100110010 "HDSISR" + attribute \enum_value_0100110011 "HDAR" + attribute \enum_value_0100110100 "SPURR" + attribute \enum_value_0100110101 "PURR" + attribute \enum_value_0100110110 "HDEC" + attribute \enum_value_0100111001 "HRMOR" + attribute \enum_value_0100111010 "HSRR0" + attribute \enum_value_0100111011 "HSRR1" + attribute \enum_value_0100111110 "LPCR" + attribute \enum_value_0100111111 "LPIDR" + attribute \enum_value_0101010000 "HMER" + attribute \enum_value_0101010001 "HMEER" + attribute \enum_value_0101010010 "PCR" + attribute \enum_value_0101010011 "HEIR" + attribute \enum_value_0101011101 "AMOR" + attribute \enum_value_0110111110 "TIR" + attribute \enum_value_0111010000 "PTCR" + attribute \enum_value_1100000000 "SIER" + attribute \enum_value_1100000001 "MMCR2" + attribute \enum_value_1100000010 "MMCRA" + attribute \enum_value_1100000011 "PMC1" + attribute \enum_value_1100000100 "PMC2" + attribute \enum_value_1100000101 "PMC3" + attribute \enum_value_1100000110 "PMC4" + attribute \enum_value_1100000111 "PMC5" + attribute \enum_value_1100001000 "PMC6" + attribute \enum_value_1100001011 "MMCR0" + attribute \enum_value_1100001100 "SIAR" + attribute \enum_value_1100001101 "SDAR" + attribute \enum_value_1100001110 "MMCR1" + attribute \enum_value_1100010000 "SIER_priv" + attribute \enum_value_1100010001 "MMCR2_priv" + attribute \enum_value_1100010010 "MMCRA_priv" + attribute \enum_value_1100010011 "PMC1_priv" + attribute \enum_value_1100010100 "PMC2_priv" + attribute \enum_value_1100010101 "PMC3_priv" + attribute \enum_value_1100010110 "PMC4_priv" + attribute \enum_value_1100010111 "PMC5_priv" + attribute \enum_value_1100011000 "PMC6_priv" + attribute \enum_value_1100011011 "MMCR0_priv" + attribute \enum_value_1100011100 "SIAR_priv" + attribute \enum_value_1100011101 "SDAR_priv" + attribute \enum_value_1100011110 "MMCR1_priv" + attribute \enum_value_1100100000 "BESCRS" + attribute \enum_value_1100100001 "BESCRSU" + attribute \enum_value_1100100010 "BESCRR" + attribute \enum_value_1100100011 "BESCRRU" + attribute \enum_value_1100100100 "EBBHR" + attribute \enum_value_1100100101 "EBBRR" + attribute \enum_value_1100100110 "BESCR" + attribute \enum_value_1100101000 "reserved808" + attribute \enum_value_1100101001 "reserved809" + attribute \enum_value_1100101010 "reserved810" + attribute \enum_value_1100101011 "reserved811" + attribute \enum_value_1100101111 "TAR" + attribute \enum_value_1100110000 "ASDR" + attribute \enum_value_1100110111 "PSSCR" + attribute \enum_value_1101010000 "IC" + attribute \enum_value_1101010001 "VTB" + attribute \enum_value_1101010111 "PSSCR_hypv" + attribute \enum_value_1110000000 "PPR" + attribute \enum_value_1110000010 "PPR32" + attribute \enum_value_1111111111 "PIR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 10 \tmp_spro + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \tmp_spro_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:42" + wire width 64 \tmp_tmp_cia + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 8 \tmp_tmp_cr_rd + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \tmp_tmp_cr_rd_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 8 \tmp_tmp_cr_wr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \tmp_tmp_cr_wr_ok + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:47" + wire width 12 \tmp_tmp_fn_unit + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:51" + wire width 2 \tmp_tmp_input_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:45" + wire width 32 \tmp_tmp_insn + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:46" + wire width 7 \tmp_tmp_insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:56" + wire \tmp_tmp_is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:48" + wire \tmp_tmp_lk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:41" + wire width 64 \tmp_tmp_msr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \tmp_tmp_oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \tmp_tmp_oe_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \tmp_tmp_rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \tmp_tmp_rc_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:53" + wire width 13 \tmp_tmp_trapaddr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:52" + wire width 7 \tmp_tmp_traptype + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:102" + wire width 3 \tmp_xer_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:103" + wire \tmp_xer_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:53" + wire width 13 output 50 \trapaddr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:52" + wire width 7 output 49 \traptype + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:102" + wire width 3 output 20 \xer_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:103" + wire output 21 \xer_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:886" + cell $and $and$issuer_ls180.v:74041$3527 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cur_eint + connect \B \cur_msr [15] + connect \Y $and$issuer_ls180.v:74041$3527_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:887" + cell $and $and$issuer_ls180.v:74042$3528 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cur_dec [63] + connect \B \cur_msr [15] + connect \Y $and$issuer_ls180.v:74042$3528_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:888" + cell $and $and$issuer_ls180.v:74043$3529 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \is_priv_insn + connect \B \cur_msr [14] + connect \Y $and$issuer_ls180.v:74043$3529_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:856" + cell $eq $eq$issuer_ls180.v:74037$3523 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \dec_internal_op + connect \B 7'0101110 + connect \Y $eq$issuer_ls180.v:74037$3523_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:858" + cell $eq $eq$issuer_ls180.v:74038$3524 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \dec_internal_op + connect \B 7'0001010 + connect \Y $eq$issuer_ls180.v:74038$3524_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:860" + cell $eq $eq$issuer_ls180.v:74039$3525 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \dec_internal_op + connect \B 7'0110001 + connect \Y $eq$issuer_ls180.v:74039$3525_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:864" + cell $eq $eq$issuer_ls180.v:74040$3526 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \dec_internal_op + connect \B 7'0111111 + connect \Y $eq$issuer_ls180.v:74040$3526_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:889" + cell $eq $eq$issuer_ls180.v:74044$3530 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \dec_internal_op + connect \B 7'0000000 + connect \Y $eq$issuer_ls180.v:74044$3530_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:920" + cell $eq $eq$issuer_ls180.v:74045$3531 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \insn_type + connect \B 7'0111111 + connect \Y $eq$issuer_ls180.v:74045$3531_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:921" + cell $eq $eq$issuer_ls180.v:74046$3532 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \insn_type + connect \B 7'1001001 + connect \Y $eq$issuer_ls180.v:74046$3532_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:930" + cell $eq $eq$issuer_ls180.v:74048$3534 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \insn_type + connect \B 7'1000110 + connect \Y $eq$issuer_ls180.v:74048$3534_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:921" + cell $or $or$issuer_ls180.v:74047$3533 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$29 + connect \B \$31 + connect \Y $or$issuer_ls180.v:74047$3533_Y + end + attribute \module_not_derived 1 + attribute \src "issuer_ls180.v:74049.13-74085.4" + cell \dec$202 \dec + connect \BA \dec_BA + connect \BB \dec_BB + connect \BC \dec_BC + connect \BI \dec_BI + connect \BO \dec_BO + connect \BT \dec_BT + connect \FXM \dec_FXM + connect \LK \dec_LK + connect \OE \dec_OE + connect \RA \dec_RA + connect \RB \dec_RB + connect \RS \dec_RS + connect \RT \dec_RT + connect \Rc \dec_Rc + connect \SPR \dec_SPR + connect \XL_BT \dec_XL_BT + connect \XL_XO \dec_XL_XO + connect \X_BF \dec_X_BF + connect \X_BFA \dec_X_BFA + connect \bigendian \bigendian + connect \cr_in \dec_cr_in + connect \cr_out \dec_cr_out + connect \cry_in \dec_cry_in + connect \function_unit \dec_function_unit + connect \in1_sel \dec_in1_sel + connect \in2_sel \dec_in2_sel + connect \in3_sel \dec_in3_sel + connect \internal_op \dec_internal_op + connect \is_32b \dec_is_32b + connect \lk \dec_lk + connect \opcode_in \dec_opcode_in + connect \out_sel \dec_out_sel + connect \raw_opcode_in \raw_opcode_in + connect \rc_sel \dec_rc_sel + connect \upd \dec_upd + end + attribute \module_not_derived 1 + attribute \src "issuer_ls180.v:74086.9-74100.4" + cell \dec_a \dec_a + connect \BO \dec_BO + connect \RA \dec_RA + connect \RS \dec_RS + connect \SPR \dec_SPR + connect \XL_XO \dec_XL_XO + connect \fast_a \dec_a_fast_a + connect \fast_a_ok \dec_a_fast_a_ok + connect \internal_op \dec_internal_op + connect \reg_a \dec_a_reg_a + connect \reg_a_ok \dec_a_reg_a_ok + connect \sel_in \dec_a_sel_in + connect \spr_a \dec_a_spr_a + connect \spr_a_ok \dec_a_spr_a_ok + end + attribute \module_not_derived 1 + attribute \src "issuer_ls180.v:74101.9-74111.4" + cell \dec_b \dec_b + connect \RB \dec_RB + connect \RS \dec_RS + connect \XL_XO \dec_XL_XO + connect \fast_b \dec_b_fast_b + connect \fast_b_ok \dec_b_fast_b_ok + connect \internal_op \dec_internal_op + connect \reg_b \dec_b_reg_b + connect \reg_b_ok \dec_b_reg_b_ok + connect \sel_in \dec_b_sel_in + end + attribute \module_not_derived 1 + attribute \src "issuer_ls180.v:74112.9-74118.4" + cell \dec_c \dec_c + connect \RB \dec_RB + connect \RS \dec_RS + connect \reg_c \dec_c_reg_c + connect \reg_c_ok \dec_c_reg_c_ok + connect \sel_in \dec_c_sel_in + end + attribute \module_not_derived 1 + attribute \src "issuer_ls180.v:74119.19-74138.4" + cell \dec_cr_in$205 \dec_cr_in$3 + connect \BA \dec_BA + connect \BB \dec_BB + connect \BC \dec_BC + connect \BI \dec_BI + connect \BT \dec_BT + connect \FXM \dec_FXM + connect \X_BFA \dec_X_BFA + connect \cr_bitfield \dec_cr_in_cr_bitfield + connect \cr_bitfield_b \dec_cr_in_cr_bitfield_b + connect \cr_bitfield_b_ok \dec_cr_in_cr_bitfield_b_ok + connect \cr_bitfield_o \dec_cr_in_cr_bitfield_o + connect \cr_bitfield_o_ok \dec_cr_in_cr_bitfield_o_ok + connect \cr_bitfield_ok \dec_cr_in_cr_bitfield_ok + connect \cr_fxm \dec_cr_in_cr_fxm + connect \cr_fxm_ok \dec_cr_in_cr_fxm_ok + connect \insn_in \dec_cr_in_insn_in + connect \internal_op \dec_internal_op + connect \sel_in \dec_cr_in_sel_in + end + attribute \module_not_derived 1 + attribute \src "issuer_ls180.v:74139.20-74151.4" + cell \dec_cr_out$207 \dec_cr_out$4 + connect \FXM \dec_FXM + connect \XL_BT \dec_XL_BT + connect \X_BF \dec_X_BF + connect \cr_bitfield \dec_cr_out_cr_bitfield + connect \cr_bitfield_ok \dec_cr_out_cr_bitfield_ok + connect \cr_fxm \dec_cr_out_cr_fxm + connect \cr_fxm_ok \dec_cr_out_cr_fxm_ok + connect \insn_in \dec_cr_out_insn_in + connect \internal_op \dec_internal_op + connect \rc_in \dec_cr_out_rc_in + connect \sel_in \dec_cr_out_sel_in + end + attribute \module_not_derived 1 + attribute \src "issuer_ls180.v:74152.9-74165.4" + cell \dec_o \dec_o + connect \BO \dec_BO + connect \RA \dec_RA + connect \RT \dec_RT + connect \SPR \dec_SPR + connect \fast_o \dec_o_fast_o + connect \fast_o_ok \dec_o_fast_o_ok + connect \internal_op \dec_internal_op + connect \reg_o \dec_o_reg_o + connect \reg_o_ok \dec_o_reg_o_ok + connect \sel_in \dec_o_sel_in + connect \spr_o \dec_o_spr_o + connect \spr_o_ok \dec_o_spr_o_ok + end + attribute \module_not_derived 1 + attribute \src "issuer_ls180.v:74166.10-74175.4" + cell \dec_o2 \dec_o2 + connect \RA \dec_RA + connect \fast_o \dec_o2_fast_o + connect \fast_o_ok \dec_o2_fast_o_ok + connect \internal_op \dec_internal_op + connect \lk \dec_o2_lk + connect \reg_o \dec_o2_reg_o + connect \reg_o_ok \dec_o2_reg_o_ok + connect \upd \dec_upd + end + attribute \module_not_derived 1 + attribute \src "issuer_ls180.v:74176.16-74182.4" + cell \dec_oe$204 \dec_oe + connect \OE \dec_OE + connect \internal_op \dec_internal_op + connect \oe \dec_oe_oe + connect \oe_ok \dec_oe_oe_ok + connect \sel_in \dec_oe_sel_in + end + attribute \module_not_derived 1 + attribute \src "issuer_ls180.v:74183.16-74188.4" + cell \dec_rc$203 \dec_rc + connect \Rc \dec_Rc + connect \rc \dec_rc_rc + connect \rc_ok \dec_rc_rc_ok + connect \sel_in \dec_rc_sel_in + end + attribute \src "issuer_ls180.v:72504.7-72504.20" + process $proc$issuer_ls180.v:72504$3545 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "issuer_ls180.v:74189.3-74198.6" + process $proc$issuer_ls180.v:74189$3535 + assign { } { } + assign { } { } + assign $0\tmp_tmp_lk[0:0] $1\tmp_tmp_lk[0:0] + attribute \src "issuer_ls180.v:74190.5-74190.29" + switch \initial + attribute \src "issuer_ls180.v:74190.9-74190.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:756" + switch \dec_lk + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\tmp_tmp_lk[0:0] \dec_LK + case + assign $1\tmp_tmp_lk[0:0] 1'0 + end + sync always + update \tmp_tmp_lk $0\tmp_tmp_lk[0:0] + end + attribute \src "issuer_ls180.v:74199.3-74214.6" + process $proc$issuer_ls180.v:74199$3536 + assign { } { } + assign { } { } + assign { } { } + assign $0\tmp_xer_in[2:0] $2\tmp_xer_in[2:0] + attribute \src "issuer_ls180.v:74200.5-74200.29" + switch \initial + attribute \src "issuer_ls180.v:74200.9-74200.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:856" + switch \$13 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\tmp_xer_in[2:0] 3'111 + case + assign $1\tmp_xer_in[2:0] 3'000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:858" + switch \$15 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\tmp_xer_in[2:0] 3'001 + case + assign $2\tmp_xer_in[2:0] $1\tmp_xer_in[2:0] + end + sync always + update \tmp_xer_in $0\tmp_xer_in[2:0] + end + attribute \src "issuer_ls180.v:74215.3-74224.6" + process $proc$issuer_ls180.v:74215$3537 + assign { } { } + assign { } { } + assign $0\tmp_xer_out[0:0] $1\tmp_xer_out[0:0] + attribute \src "issuer_ls180.v:74216.5-74216.29" + switch \initial + attribute \src "issuer_ls180.v:74216.9-74216.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:860" + switch \$17 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\tmp_xer_out[0:0] 1'1 + case + assign $1\tmp_xer_out[0:0] 1'0 + end + sync always + update \tmp_xer_out $0\tmp_xer_out[0:0] + end + attribute \src "issuer_ls180.v:74225.3-74234.6" + process $proc$issuer_ls180.v:74225$3538 + assign { } { } + assign { } { } + assign $0\tmp_tmp_trapaddr[12:0] $1\tmp_tmp_trapaddr[12:0] + attribute \src "issuer_ls180.v:74226.5-74226.29" + switch \initial + attribute \src "issuer_ls180.v:74226.9-74226.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:864" + switch \$19 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\tmp_tmp_trapaddr[12:0] 13'0000001110000 + case + assign $1\tmp_tmp_trapaddr[12:0] 13'0000000000000 + end + sync always + update \tmp_tmp_trapaddr $0\tmp_tmp_trapaddr[12:0] + end + attribute \src "issuer_ls180.v:74235.3-74254.6" + process $proc$issuer_ls180.v:74235$3539 + assign { } { } + assign { } { } + assign $0\is_priv_insn[0:0] $1\is_priv_insn[0:0] + attribute \src "issuer_ls180.v:74236.5-74236.29" + switch \initial + attribute \src "issuer_ls180.v:74236.9-74236.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:42" + switch \dec_internal_op + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'0000101 , 7'1000111 , 7'1001000 , 7'1001010 , 7'1000110 + assign { } { } + assign $1\is_priv_insn[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'0101110 , 7'0110001 + assign { } { } + assign $1\is_priv_insn[0:0] $2\is_priv_insn[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:49" + switch \tmp_tmp_insn [20] + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\is_priv_insn[0:0] 1'1 + case + assign $2\is_priv_insn[0:0] 1'0 + end + case + assign $1\is_priv_insn[0:0] 1'0 + end + sync always + update \is_priv_insn $0\is_priv_insn[0:0] + end + attribute \src "issuer_ls180.v:74255.3-74333.6" + process $proc$issuer_ls180.v:74255$3540 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\rc[0:0] $1\rc[0:0] + assign $0\spr1[9:0] $1\spr1[9:0] + assign $0\spr1_ok[0:0] $1\spr1_ok[0:0] + assign $0\msr[63:0] $1\msr[63:0] + assign $0\ea_ok[0:0] $1\ea_ok[0:0] + assign $0\ea[4:0] $1\ea[4:0] + assign $0\asmcode[7:0] $1\asmcode[7:0] + assign $0\cr_out[2:0] $1\cr_out[2:0] + assign $0\lk[0:0] $1\lk[0:0] + assign $0\cia[63:0] $1\cia[63:0] + assign $0\cr_in1[2:0] $1\cr_in1[2:0] + assign $0\cr_in1_ok[0:0] $1\cr_in1_ok[0:0] + assign $0\cr_in2[2:0] $1\cr_in2[2:0] + assign $0\cr_in2$1[2:0]$3541 $1\cr_in2$1[2:0]$3543 + assign $0\cr_in2_ok[0:0] $1\cr_in2_ok[0:0] + assign $0\cr_in2_ok$2[0:0]$3542 $1\cr_in2_ok$2[0:0]$3544 + assign $0\cr_out_ok[0:0] $1\cr_out_ok[0:0] + assign $0\cr_rd[7:0] $1\cr_rd[7:0] + assign $0\cr_rd_ok[0:0] $1\cr_rd_ok[0:0] + assign $0\cr_wr[7:0] $1\cr_wr[7:0] + assign $0\cr_wr_ok[0:0] $1\cr_wr_ok[0:0] + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\fn_unit[11:0] $1\fn_unit[11:0] + assign $0\input_carry[1:0] $1\input_carry[1:0] + assign $0\insn[31:0] $1\insn[31:0] + assign $0\insn_type[6:0] $1\insn_type[6:0] + assign $0\is_32bit[0:0] $1\is_32bit[0:0] + assign $0\oe[0:0] $1\oe[0:0] + assign $0\oe_ok[0:0] $1\oe_ok[0:0] + assign $0\rc_ok[0:0] $1\rc_ok[0:0] + assign $0\reg1[4:0] $1\reg1[4:0] + assign $0\reg1_ok[0:0] $1\reg1_ok[0:0] + assign $0\reg2[4:0] $1\reg2[4:0] + assign $0\reg2_ok[0:0] $1\reg2_ok[0:0] + assign $0\reg3[4:0] $1\reg3[4:0] + assign $0\reg3_ok[0:0] $1\reg3_ok[0:0] + assign $0\rego[4:0] $1\rego[4:0] + assign $0\rego_ok[0:0] $1\rego_ok[0:0] + assign $0\spro[9:0] $1\spro[9:0] + assign $0\spro_ok[0:0] $1\spro_ok[0:0] + assign $0\trapaddr[12:0] $1\trapaddr[12:0] + assign $0\traptype[6:0] $1\traptype[6:0] + assign $0\xer_in[2:0] $1\xer_in[2:0] + assign $0\xer_out[0:0] $1\xer_out[0:0] + assign $0\fasto1[2:0] $2\fasto1[2:0] + assign $0\fasto1_ok[0:0] $2\fasto1_ok[0:0] + assign $0\fasto2[2:0] $2\fasto2[2:0] + assign $0\fasto2_ok[0:0] $2\fasto2_ok[0:0] + assign $0\fast1[2:0] $2\fast1[2:0] + assign $0\fast1_ok[0:0] $2\fast1_ok[0:0] + assign $0\fast2[2:0] $2\fast2[2:0] + assign $0\fast2_ok[0:0] $2\fast2_ok[0:0] + attribute \src "issuer_ls180.v:74256.5-74256.29" + switch \initial + attribute \src "issuer_ls180.v:74256.9-74256.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:892" + switch { \illeg_ok \priv_ok \ext_irq_ok \dec_irq_ok } + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'---1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { $1\is_32bit[0:0] $1\cr_wr_ok[0:0] $1\cr_wr[7:0] $1\cr_rd_ok[0:0] $1\cr_rd[7:0] $1\input_carry[1:0] $1\oe_ok[0:0] $1\oe[0:0] $1\rc_ok[0:0] $1\rc[0:0] $1\lk[0:0] $1\cr_out_ok[0:0] $1\cr_out[2:0] $1\cr_in2_ok$2[0:0]$3544 $1\cr_in2$1[2:0]$3543 $1\cr_in2_ok[0:0] $1\cr_in2[2:0] $1\cr_in1_ok[0:0] $1\cr_in1[2:0] $1\fasto2_ok[0:0] $1\fasto2[2:0] $1\fasto1_ok[0:0] $1\fasto1[2:0] $1\fast2_ok[0:0] $1\fast2[2:0] $1\fast1_ok[0:0] $1\fast1[2:0] $1\xer_out[0:0] $1\xer_in[2:0] $1\spr1_ok[0:0] $1\spr1[9:0] $1\spro_ok[0:0] $1\spro[9:0] $1\reg3_ok[0:0] $1\reg3[4:0] $1\reg2_ok[0:0] $1\reg2[4:0] $1\reg1_ok[0:0] $1\reg1[4:0] $1\ea_ok[0:0] $1\ea[4:0] $1\rego_ok[0:0] $1\rego[4:0] $1\asmcode[7:0] } 122'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign $1\insn[31:0] \dec_opcode_in + assign $1\insn_type[6:0] 7'0111111 + assign $1\fn_unit[11:0] 12'000010000000 + assign $1\trapaddr[12:0] 13'0000010010000 + assign $1\traptype[6:0] 7'0100000 + assign $1\msr[63:0] \cur_msr + assign $1\cia[63:0] \cur_pc + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'--1- + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { $1\is_32bit[0:0] $1\cr_wr_ok[0:0] $1\cr_wr[7:0] $1\cr_rd_ok[0:0] $1\cr_rd[7:0] $1\input_carry[1:0] $1\oe_ok[0:0] $1\oe[0:0] $1\rc_ok[0:0] $1\rc[0:0] $1\lk[0:0] $1\cr_out_ok[0:0] $1\cr_out[2:0] $1\cr_in2_ok$2[0:0]$3544 $1\cr_in2$1[2:0]$3543 $1\cr_in2_ok[0:0] $1\cr_in2[2:0] $1\cr_in1_ok[0:0] $1\cr_in1[2:0] $1\fasto2_ok[0:0] $1\fasto2[2:0] $1\fasto1_ok[0:0] $1\fasto1[2:0] $1\fast2_ok[0:0] $1\fast2[2:0] $1\fast1_ok[0:0] $1\fast1[2:0] $1\xer_out[0:0] $1\xer_in[2:0] $1\spr1_ok[0:0] $1\spr1[9:0] $1\spro_ok[0:0] $1\spro[9:0] $1\reg3_ok[0:0] $1\reg3[4:0] $1\reg2_ok[0:0] $1\reg2[4:0] $1\reg1_ok[0:0] $1\reg1[4:0] $1\ea_ok[0:0] $1\ea[4:0] $1\rego_ok[0:0] $1\rego[4:0] $1\asmcode[7:0] } 122'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign $1\insn[31:0] \dec_opcode_in + assign $1\insn_type[6:0] 7'0111111 + assign $1\fn_unit[11:0] 12'000010000000 + assign $1\trapaddr[12:0] 13'0000001010000 + assign $1\traptype[6:0] 7'0010000 + assign $1\msr[63:0] \cur_msr + assign $1\cia[63:0] \cur_pc + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'-1-- + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { $1\is_32bit[0:0] $1\cr_wr_ok[0:0] $1\cr_wr[7:0] $1\cr_rd_ok[0:0] $1\cr_rd[7:0] $1\input_carry[1:0] $1\oe_ok[0:0] $1\oe[0:0] $1\rc_ok[0:0] $1\rc[0:0] $1\lk[0:0] $1\cr_out_ok[0:0] $1\cr_out[2:0] $1\cr_in2_ok$2[0:0]$3544 $1\cr_in2$1[2:0]$3543 $1\cr_in2_ok[0:0] $1\cr_in2[2:0] $1\cr_in1_ok[0:0] $1\cr_in1[2:0] $1\fasto2_ok[0:0] $1\fasto2[2:0] $1\fasto1_ok[0:0] $1\fasto1[2:0] $1\fast2_ok[0:0] $1\fast2[2:0] $1\fast1_ok[0:0] $1\fast1[2:0] $1\xer_out[0:0] $1\xer_in[2:0] $1\spr1_ok[0:0] $1\spr1[9:0] $1\spro_ok[0:0] $1\spro[9:0] $1\reg3_ok[0:0] $1\reg3[4:0] $1\reg2_ok[0:0] $1\reg2[4:0] $1\reg1_ok[0:0] $1\reg1[4:0] $1\ea_ok[0:0] $1\ea[4:0] $1\rego_ok[0:0] $1\rego[4:0] $1\asmcode[7:0] } 122'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign $1\insn[31:0] \dec_opcode_in + assign $1\insn_type[6:0] 7'0111111 + assign $1\fn_unit[11:0] 12'000010000000 + assign $1\trapaddr[12:0] 13'0000001110000 + assign $1\traptype[6:0] 7'0000010 + assign $1\msr[63:0] \cur_msr + assign $1\cia[63:0] \cur_pc + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'1--- + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { $1\is_32bit[0:0] $1\cr_wr_ok[0:0] $1\cr_wr[7:0] $1\cr_rd_ok[0:0] $1\cr_rd[7:0] $1\input_carry[1:0] $1\oe_ok[0:0] $1\oe[0:0] $1\rc_ok[0:0] $1\rc[0:0] $1\lk[0:0] $1\cr_out_ok[0:0] $1\cr_out[2:0] $1\cr_in2_ok$2[0:0]$3544 $1\cr_in2$1[2:0]$3543 $1\cr_in2_ok[0:0] $1\cr_in2[2:0] $1\cr_in1_ok[0:0] $1\cr_in1[2:0] $1\fasto2_ok[0:0] $1\fasto2[2:0] $1\fasto1_ok[0:0] $1\fasto1[2:0] $1\fast2_ok[0:0] $1\fast2[2:0] $1\fast1_ok[0:0] $1\fast1[2:0] $1\xer_out[0:0] $1\xer_in[2:0] $1\spr1_ok[0:0] $1\spr1[9:0] $1\spro_ok[0:0] $1\spro[9:0] $1\reg3_ok[0:0] $1\reg3[4:0] $1\reg2_ok[0:0] $1\reg2[4:0] $1\reg1_ok[0:0] $1\reg1[4:0] $1\ea_ok[0:0] $1\ea[4:0] $1\rego_ok[0:0] $1\rego[4:0] $1\asmcode[7:0] } 122'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign $1\insn[31:0] \dec_opcode_in + assign $1\insn_type[6:0] 7'0111111 + assign $1\fn_unit[11:0] 12'000010000000 + assign $1\trapaddr[12:0] 13'0000001110000 + assign $1\traptype[6:0] 7'1000000 + assign $1\msr[63:0] \cur_msr + assign $1\cia[63:0] \cur_pc + attribute \src "issuer_ls180.v:0.0-0.0" + case + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { $1\is_32bit[0:0] $1\cr_wr_ok[0:0] $1\cr_wr[7:0] $1\cr_rd_ok[0:0] $1\cr_rd[7:0] $1\trapaddr[12:0] $1\traptype[6:0] $1\input_carry[1:0] $1\oe_ok[0:0] $1\oe[0:0] $1\rc_ok[0:0] $1\rc[0:0] $1\lk[0:0] $1\fn_unit[11:0] $1\insn_type[6:0] $1\insn[31:0] $1\cia[63:0] $1\msr[63:0] $1\cr_out_ok[0:0] $1\cr_out[2:0] $1\cr_in2_ok$2[0:0]$3544 $1\cr_in2$1[2:0]$3543 $1\cr_in2_ok[0:0] $1\cr_in2[2:0] $1\cr_in1_ok[0:0] $1\cr_in1[2:0] $1\fasto2_ok[0:0] $1\fasto2[2:0] $1\fasto1_ok[0:0] $1\fasto1[2:0] $1\fast2_ok[0:0] $1\fast2[2:0] $1\fast1_ok[0:0] $1\fast1[2:0] $1\xer_out[0:0] $1\xer_in[2:0] $1\spr1_ok[0:0] $1\spr1[9:0] $1\spro_ok[0:0] $1\spro[9:0] $1\reg3_ok[0:0] $1\reg3[4:0] $1\reg2_ok[0:0] $1\reg2[4:0] $1\reg1_ok[0:0] $1\reg1[4:0] $1\ea_ok[0:0] $1\ea[4:0] $1\rego_ok[0:0] $1\rego[4:0] $1\asmcode[7:0] } { \tmp_tmp_is_32bit \tmp_tmp_cr_wr_ok \tmp_tmp_cr_wr \tmp_tmp_cr_rd_ok \tmp_tmp_cr_rd \tmp_tmp_trapaddr \tmp_tmp_traptype \tmp_tmp_input_carry \tmp_tmp_oe_ok \tmp_tmp_oe \tmp_tmp_rc_ok \tmp_tmp_rc \tmp_tmp_lk \tmp_tmp_fn_unit \tmp_tmp_insn_type \tmp_tmp_insn \tmp_tmp_cia \tmp_tmp_msr \tmp_cr_out_ok \tmp_cr_out \tmp_cr_in2_ok$12 \tmp_cr_in2$11 \tmp_cr_in2_ok \tmp_cr_in2 \tmp_cr_in1_ok \tmp_cr_in1 \tmp_fasto2_ok \tmp_fasto2 \tmp_fasto1_ok \tmp_fasto1 \tmp_fast2_ok \tmp_fast2 \tmp_fast1_ok \tmp_fast1 \tmp_xer_out \tmp_xer_in \tmp_spr1_ok \tmp_spr1 \tmp_spro_ok \tmp_spro \tmp_reg3_ok \tmp_reg3 \tmp_reg2_ok \tmp_reg2 \tmp_reg1_ok \tmp_reg1 \tmp_ea_ok \tmp_ea \tmp_rego_ok \tmp_rego \tmp_asmcode } + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:921" + switch \$33 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $2\fasto1[2:0] 3'011 + assign $2\fasto1_ok[0:0] 1'1 + assign $2\fasto2[2:0] 3'100 + assign $2\fasto2_ok[0:0] 1'1 + case + assign $2\fasto1[2:0] $1\fasto1[2:0] + assign $2\fasto1_ok[0:0] $1\fasto1_ok[0:0] + assign $2\fasto2[2:0] $1\fasto2[2:0] + assign $2\fasto2_ok[0:0] $1\fasto2_ok[0:0] + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:930" + switch \$35 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $2\fast1[2:0] 3'011 + assign $2\fast1_ok[0:0] 1'1 + assign $2\fast2[2:0] 3'100 + assign $2\fast2_ok[0:0] 1'1 + case + assign $2\fast1[2:0] $1\fast1[2:0] + assign $2\fast1_ok[0:0] $1\fast1_ok[0:0] + assign $2\fast2[2:0] $1\fast2[2:0] + assign $2\fast2_ok[0:0] $1\fast2_ok[0:0] + end + sync always + update \fast1 $0\fast1[2:0] + update \fast1_ok $0\fast1_ok[0:0] + update \fast2 $0\fast2[2:0] + update \fast2_ok $0\fast2_ok[0:0] + update \rc $0\rc[0:0] + update \spr1 $0\spr1[9:0] + update \spr1_ok $0\spr1_ok[0:0] + update \msr $0\msr[63:0] + update \ea_ok $0\ea_ok[0:0] + update \ea $0\ea[4:0] + update \asmcode $0\asmcode[7:0] + update \cr_out $0\cr_out[2:0] + update \lk $0\lk[0:0] + update \cia $0\cia[63:0] + update \cr_in1 $0\cr_in1[2:0] + update \cr_in1_ok $0\cr_in1_ok[0:0] + update \cr_in2 $0\cr_in2[2:0] + update \cr_in2$1 $0\cr_in2$1[2:0]$3541 + update \cr_in2_ok $0\cr_in2_ok[0:0] + update \cr_in2_ok$2 $0\cr_in2_ok$2[0:0]$3542 + update \cr_out_ok $0\cr_out_ok[0:0] + update \cr_rd $0\cr_rd[7:0] + update \cr_rd_ok $0\cr_rd_ok[0:0] + update \cr_wr $0\cr_wr[7:0] + update \cr_wr_ok $0\cr_wr_ok[0:0] + update \fasto1 $0\fasto1[2:0] + update \fasto1_ok $0\fasto1_ok[0:0] + update \fasto2 $0\fasto2[2:0] + update \fasto2_ok $0\fasto2_ok[0:0] + update \fn_unit $0\fn_unit[11:0] + update \input_carry $0\input_carry[1:0] + update \insn $0\insn[31:0] + update \insn_type $0\insn_type[6:0] + update \is_32bit $0\is_32bit[0:0] + update \oe $0\oe[0:0] + update \oe_ok $0\oe_ok[0:0] + update \rc_ok $0\rc_ok[0:0] + update \reg1 $0\reg1[4:0] + update \reg1_ok $0\reg1_ok[0:0] + update \reg2 $0\reg2[4:0] + update \reg2_ok $0\reg2_ok[0:0] + update \reg3 $0\reg3[4:0] + update \reg3_ok $0\reg3_ok[0:0] + update \rego $0\rego[4:0] + update \rego_ok $0\rego_ok[0:0] + update \spro $0\spro[9:0] + update \spro_ok $0\spro_ok[0:0] + update \trapaddr $0\trapaddr[12:0] + update \traptype $0\traptype[6:0] + update \xer_in $0\xer_in[2:0] + update \xer_out $0\xer_out[0:0] + end + connect \$13 $eq$issuer_ls180.v:74037$3523_Y + connect \$15 $eq$issuer_ls180.v:74038$3524_Y + connect \$17 $eq$issuer_ls180.v:74039$3525_Y + connect \$19 $eq$issuer_ls180.v:74040$3526_Y + connect \$21 $and$issuer_ls180.v:74041$3527_Y + connect \$23 $and$issuer_ls180.v:74042$3528_Y + connect \$25 $and$issuer_ls180.v:74043$3529_Y + connect \$27 $eq$issuer_ls180.v:74044$3530_Y + connect \$29 $eq$issuer_ls180.v:74045$3531_Y + connect \$31 $eq$issuer_ls180.v:74046$3532_Y + connect \$33 $or$issuer_ls180.v:74047$3533_Y + connect \$35 $eq$issuer_ls180.v:74048$3534_Y + connect \tmp_asmcode 8'00000000 + connect \tmp_tmp_traptype 7'0000000 + connect \illeg_ok \$27 + connect \priv_ok \$25 + connect \dec_irq_ok \$23 + connect \ext_irq_ok \$21 + connect { \tmp_cr_out_ok \tmp_cr_out } { \dec_cr_out_cr_bitfield_ok \dec_cr_out_cr_bitfield } + connect { \tmp_cr_in2_ok$12 \tmp_cr_in2$11 } { \dec_cr_in_cr_bitfield_o_ok \dec_cr_in_cr_bitfield_o } + connect { \tmp_cr_in2_ok \tmp_cr_in2 } { \dec_cr_in_cr_bitfield_b_ok \dec_cr_in_cr_bitfield_b } + connect { \tmp_cr_in1_ok \tmp_cr_in1 } { \dec_cr_in_cr_bitfield_ok \dec_cr_in_cr_bitfield } + connect { \tmp_fasto2_ok \tmp_fasto2 } { \dec_o2_fast_o_ok \dec_o2_fast_o } + connect { \tmp_fasto1_ok \tmp_fasto1 } { \dec_o_fast_o_ok \dec_o_fast_o } + connect { \tmp_fast2_ok \tmp_fast2 } { \dec_b_fast_b_ok \dec_b_fast_b } + connect { \tmp_fast1_ok \tmp_fast1 } { \dec_a_fast_a_ok \dec_a_fast_a } + connect { \tmp_spro_ok \tmp_spro } { \dec_o_spr_o_ok \dec_o_spr_o } + connect { \tmp_spr1_ok \tmp_spr1 } { \dec_a_spr_a_ok \dec_a_spr_a } + connect { \tmp_ea_ok \tmp_ea } { \dec_o2_reg_o_ok \dec_o2_reg_o } + connect { \tmp_rego_ok \tmp_rego } { \dec_o_reg_o_ok \dec_o_reg_o } + connect { \tmp_reg3_ok \tmp_reg3 } { \dec_c_reg_c_ok \dec_c_reg_c } + connect { \tmp_reg2_ok \tmp_reg2 } { \dec_b_reg_b_ok \dec_b_reg_b } + connect { \tmp_reg1_ok \tmp_reg1 } { \dec_a_reg_a_ok \dec_a_reg_a } + connect \dec_o2_lk \tmp_tmp_lk + connect \sel_in \dec_out_sel + connect \dec_o_sel_in \dec_out_sel + connect \dec_c_sel_in \dec_in3_sel + connect \dec_b_sel_in \dec_in2_sel + connect \dec_a_sel_in \dec_in1_sel + connect \insn_in$10 \dec_opcode_in + connect \insn_in$9 \dec_opcode_in + connect \insn_in$8 \dec_opcode_in + connect \insn_in$7 \dec_opcode_in + connect \insn_in$6 \dec_opcode_in + connect \tmp_tmp_is_32bit \dec_is_32b + connect \tmp_tmp_input_carry \dec_cry_in + connect { \tmp_tmp_cr_wr_ok \tmp_tmp_cr_wr } { \dec_cr_out_cr_fxm_ok \dec_cr_out_cr_fxm } + connect { \tmp_tmp_cr_rd_ok \tmp_tmp_cr_rd } { \dec_cr_in_cr_fxm_ok \dec_cr_in_cr_fxm } + connect { \tmp_tmp_oe_ok \tmp_tmp_oe } { \dec_oe_oe_ok \dec_oe_oe } + connect { \tmp_tmp_rc_ok \tmp_tmp_rc } { \dec_rc_rc_ok \dec_rc_rc } + connect \tmp_tmp_fn_unit \dec_function_unit + connect \tmp_tmp_insn_type \dec_internal_op + connect \tmp_tmp_cia \cur_pc + connect \tmp_tmp_msr \cur_msr + connect \dec_cr_out_rc_in \dec_rc_rc + connect \dec_cr_out_sel_in \dec_cr_out + connect \dec_cr_in_sel_in \dec_cr_in + connect \dec_oe_sel_in \dec_rc_sel + connect \dec_rc_sel_in \dec_rc_sel + connect \dec_cr_out_insn_in \dec_opcode_in + connect \dec_cr_in_insn_in \dec_opcode_in + connect \insn_in$5 \dec_opcode_in + connect \insn_in \dec_opcode_in + connect \tmp_tmp_insn \dec_opcode_in +end +attribute \src "issuer_ls180.v:74390.1-75537.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.dec2.dec.dec30" +attribute \generator "nMigen" +module \dec30 + attribute \src "issuer_ls180.v:74833.3-74869.6" + wire width 8 $0\dec30_asmcode[7:0] + attribute \src "issuer_ls180.v:74981.3-75017.6" + wire $0\dec30_br[0:0] + attribute \src "issuer_ls180.v:75462.3-75498.6" + wire width 3 $0\dec30_cr_in[2:0] + attribute \src "issuer_ls180.v:75499.3-75535.6" + wire width 3 $0\dec30_cr_out[2:0] + attribute \src "issuer_ls180.v:74796.3-74832.6" + wire width 2 $0\dec30_cry_in[1:0] + attribute \src "issuer_ls180.v:74944.3-74980.6" + wire $0\dec30_cry_out[0:0] + attribute \src "issuer_ls180.v:75277.3-75313.6" + wire width 5 $0\dec30_form[4:0] + attribute \src "issuer_ls180.v:74648.3-74684.6" + wire width 12 $0\dec30_function_unit[11:0] + attribute \src "issuer_ls180.v:75314.3-75350.6" + wire width 3 $0\dec30_in1_sel[2:0] + attribute \src "issuer_ls180.v:75351.3-75387.6" + wire width 4 $0\dec30_in2_sel[3:0] + attribute \src "issuer_ls180.v:75388.3-75424.6" + wire width 2 $0\dec30_in3_sel[1:0] + attribute \src "issuer_ls180.v:75055.3-75091.6" + wire width 7 $0\dec30_internal_op[6:0] + attribute \src "issuer_ls180.v:74870.3-74906.6" + wire $0\dec30_inv_a[0:0] + attribute \src "issuer_ls180.v:74907.3-74943.6" + wire $0\dec30_inv_out[0:0] + attribute \src "issuer_ls180.v:75129.3-75165.6" + wire $0\dec30_is_32b[0:0] + attribute \src "issuer_ls180.v:74685.3-74721.6" + wire width 4 $0\dec30_ldst_len[3:0] + attribute \src "issuer_ls180.v:75203.3-75239.6" + wire $0\dec30_lk[0:0] + attribute \src "issuer_ls180.v:75425.3-75461.6" + wire width 2 $0\dec30_out_sel[1:0] + attribute \src "issuer_ls180.v:74759.3-74795.6" + wire width 2 $0\dec30_rc_sel[1:0] + attribute \src "issuer_ls180.v:75092.3-75128.6" + wire $0\dec30_rsrv[0:0] + attribute \src "issuer_ls180.v:75240.3-75276.6" + wire $0\dec30_sgl_pipe[0:0] + attribute \src "issuer_ls180.v:75166.3-75202.6" + wire $0\dec30_sgn[0:0] + attribute \src "issuer_ls180.v:75018.3-75054.6" + wire $0\dec30_sgn_ext[0:0] + attribute \src "issuer_ls180.v:74722.3-74758.6" + wire width 2 $0\dec30_upd[1:0] + attribute \src "issuer_ls180.v:74391.7-74391.20" + wire $0\initial[0:0] + attribute \src "issuer_ls180.v:74833.3-74869.6" + wire width 8 $1\dec30_asmcode[7:0] + attribute \src "issuer_ls180.v:74981.3-75017.6" + wire $1\dec30_br[0:0] + attribute \src "issuer_ls180.v:75462.3-75498.6" + wire width 3 $1\dec30_cr_in[2:0] + attribute \src "issuer_ls180.v:75499.3-75535.6" + wire width 3 $1\dec30_cr_out[2:0] + attribute \src "issuer_ls180.v:74796.3-74832.6" + wire width 2 $1\dec30_cry_in[1:0] + attribute \src "issuer_ls180.v:74944.3-74980.6" + wire $1\dec30_cry_out[0:0] + attribute \src "issuer_ls180.v:75277.3-75313.6" + wire width 5 $1\dec30_form[4:0] + attribute \src "issuer_ls180.v:74648.3-74684.6" + wire width 12 $1\dec30_function_unit[11:0] + attribute \src "issuer_ls180.v:75314.3-75350.6" + wire width 3 $1\dec30_in1_sel[2:0] + attribute \src "issuer_ls180.v:75351.3-75387.6" + wire width 4 $1\dec30_in2_sel[3:0] + attribute \src "issuer_ls180.v:75388.3-75424.6" + wire width 2 $1\dec30_in3_sel[1:0] + attribute \src "issuer_ls180.v:75055.3-75091.6" + wire width 7 $1\dec30_internal_op[6:0] + attribute \src "issuer_ls180.v:74870.3-74906.6" + wire $1\dec30_inv_a[0:0] + attribute \src "issuer_ls180.v:74907.3-74943.6" + wire $1\dec30_inv_out[0:0] + attribute \src "issuer_ls180.v:75129.3-75165.6" + wire $1\dec30_is_32b[0:0] + attribute \src "issuer_ls180.v:74685.3-74721.6" + wire width 4 $1\dec30_ldst_len[3:0] + attribute \src "issuer_ls180.v:75203.3-75239.6" + wire $1\dec30_lk[0:0] + attribute \src "issuer_ls180.v:75425.3-75461.6" + wire width 2 $1\dec30_out_sel[1:0] + attribute \src "issuer_ls180.v:74759.3-74795.6" + wire width 2 $1\dec30_rc_sel[1:0] + attribute \src "issuer_ls180.v:75092.3-75128.6" + wire $1\dec30_rsrv[0:0] + attribute \src "issuer_ls180.v:75240.3-75276.6" + wire $1\dec30_sgl_pipe[0:0] + attribute \src "issuer_ls180.v:75166.3-75202.6" + wire $1\dec30_sgn[0:0] + attribute \src "issuer_ls180.v:75018.3-75054.6" + wire $1\dec30_sgn_ext[0:0] + attribute \src "issuer_ls180.v:74722.3-74758.6" + wire width 2 $1\dec30_upd[1:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 8 output 4 \dec30_asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 18 \dec30_br + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 9 \dec30_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 10 \dec30_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 14 \dec30_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 17 \dec30_cry_out + attribute \enum_base_type "Form" + attribute \enum_value_00000 "NONE" + attribute \enum_value_00001 "I" + attribute \enum_value_00010 "B" + attribute \enum_value_00011 "SC" + attribute \enum_value_00100 "D" + attribute \enum_value_00101 "DS" + attribute \enum_value_00110 "DQ" + attribute \enum_value_00111 "DX" + attribute \enum_value_01000 "X" + attribute \enum_value_01001 "XL" + attribute \enum_value_01010 "XFX" + attribute \enum_value_01011 "XFL" + attribute \enum_value_01100 "XX1" + attribute \enum_value_01101 "XX2" + attribute \enum_value_01110 "XX3" + attribute \enum_value_01111 "XX4" + attribute \enum_value_10000 "XS" + attribute \enum_value_10001 "XO" + attribute \enum_value_10010 "A" + attribute \enum_value_10011 "M" + attribute \enum_value_10100 "MD" + attribute \enum_value_10101 "MDS" + attribute \enum_value_10110 "VA" + attribute \enum_value_10111 "VC" + attribute \enum_value_11000 "VX" + attribute \enum_value_11001 "EVX" + attribute \enum_value_11010 "EVS" + attribute \enum_value_11011 "Z22" + attribute \enum_value_11100 "Z23" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 5 output 3 \dec30_form + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 12 output 1 \dec30_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 5 \dec30_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 output 6 \dec30_in2_sel + attribute \enum_base_type "In3Sel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RS" + attribute \enum_value_10 "RB" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 7 \dec30_in3_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 7 output 2 \dec30_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 15 \dec30_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 16 \dec30_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 21 \dec30_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 output 11 \dec30_ldst_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 23 \dec30_lk + attribute \enum_base_type "OutSel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RT" + attribute \enum_value_10 "RA" + attribute \enum_value_11 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 8 \dec30_out_sel + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 13 \dec30_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 20 \dec30_rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 24 \dec30_sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 22 \dec30_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 19 \dec30_sgn_ext + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 12 \dec30_upd + attribute \src "issuer_ls180.v:74391.7-74391.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + wire width 32 input 25 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:320" + wire width 4 \opcode_switch + attribute \src "issuer_ls180.v:74391.7-74391.20" + process $proc$issuer_ls180.v:74391$3570 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "issuer_ls180.v:74648.3-74684.6" + process $proc$issuer_ls180.v:74648$3546 + assign { } { } + assign { } { } + assign $0\dec30_function_unit[11:0] $1\dec30_function_unit[11:0] + attribute \src "issuer_ls180.v:74649.5-74649.29" + switch \initial + attribute \src "issuer_ls180.v:74649.9-74649.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0100 + assign { } { } + assign $1\dec30_function_unit[11:0] 12'000000001000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0101 + assign { } { } + assign $1\dec30_function_unit[11:0] 12'000000001000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $1\dec30_function_unit[11:0] 12'000000001000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0001 + assign { } { } + assign $1\dec30_function_unit[11:0] 12'000000001000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0010 + assign { } { } + assign $1\dec30_function_unit[11:0] 12'000000001000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0011 + assign { } { } + assign $1\dec30_function_unit[11:0] 12'000000001000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\dec30_function_unit[11:0] 12'000000001000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $1\dec30_function_unit[11:0] 12'000000001000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\dec30_function_unit[11:0] 12'000000001000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'1001 + assign { } { } + assign $1\dec30_function_unit[11:0] 12'000000001000 + case + assign $1\dec30_function_unit[11:0] 12'000000000000 + end + sync always + update \dec30_function_unit $0\dec30_function_unit[11:0] + end + attribute \src "issuer_ls180.v:74685.3-74721.6" + process $proc$issuer_ls180.v:74685$3547 + assign { } { } + assign { } { } + assign $0\dec30_ldst_len[3:0] $1\dec30_ldst_len[3:0] + attribute \src "issuer_ls180.v:74686.5-74686.29" + switch \initial + attribute \src "issuer_ls180.v:74686.9-74686.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0100 + assign { } { } + assign $1\dec30_ldst_len[3:0] 4'0000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0101 + assign { } { } + assign $1\dec30_ldst_len[3:0] 4'0000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $1\dec30_ldst_len[3:0] 4'0000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0001 + assign { } { } + assign $1\dec30_ldst_len[3:0] 4'0000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0010 + assign { } { } + assign $1\dec30_ldst_len[3:0] 4'0000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0011 + assign { } { } + assign $1\dec30_ldst_len[3:0] 4'0000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\dec30_ldst_len[3:0] 4'0000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $1\dec30_ldst_len[3:0] 4'0000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\dec30_ldst_len[3:0] 4'0000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'1001 + assign { } { } + assign $1\dec30_ldst_len[3:0] 4'0000 + case + assign $1\dec30_ldst_len[3:0] 4'0000 + end + sync always + update \dec30_ldst_len $0\dec30_ldst_len[3:0] + end + attribute \src "issuer_ls180.v:74722.3-74758.6" + process $proc$issuer_ls180.v:74722$3548 + assign { } { } + assign { } { } + assign $0\dec30_upd[1:0] $1\dec30_upd[1:0] + attribute \src "issuer_ls180.v:74723.5-74723.29" + switch \initial + attribute \src "issuer_ls180.v:74723.9-74723.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0100 + assign { } { } + assign $1\dec30_upd[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0101 + assign { } { } + assign $1\dec30_upd[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $1\dec30_upd[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0001 + assign { } { } + assign $1\dec30_upd[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0010 + assign { } { } + assign $1\dec30_upd[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0011 + assign { } { } + assign $1\dec30_upd[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\dec30_upd[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $1\dec30_upd[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\dec30_upd[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'1001 + assign { } { } + assign $1\dec30_upd[1:0] 2'00 + case + assign $1\dec30_upd[1:0] 2'00 + end + sync always + update \dec30_upd $0\dec30_upd[1:0] + end + attribute \src "issuer_ls180.v:74759.3-74795.6" + process $proc$issuer_ls180.v:74759$3549 + assign { } { } + assign { } { } + assign $0\dec30_rc_sel[1:0] $1\dec30_rc_sel[1:0] + attribute \src "issuer_ls180.v:74760.5-74760.29" + switch \initial + attribute \src "issuer_ls180.v:74760.9-74760.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0100 + assign { } { } + assign $1\dec30_rc_sel[1:0] 2'10 + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0101 + assign { } { } + assign $1\dec30_rc_sel[1:0] 2'10 + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $1\dec30_rc_sel[1:0] 2'10 + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0001 + assign { } { } + assign $1\dec30_rc_sel[1:0] 2'10 + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0010 + assign { } { } + assign $1\dec30_rc_sel[1:0] 2'10 + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0011 + assign { } { } + assign $1\dec30_rc_sel[1:0] 2'10 + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\dec30_rc_sel[1:0] 2'10 + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $1\dec30_rc_sel[1:0] 2'10 + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\dec30_rc_sel[1:0] 2'10 + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'1001 + assign { } { } + assign $1\dec30_rc_sel[1:0] 2'10 + case + assign $1\dec30_rc_sel[1:0] 2'00 + end + sync always + update \dec30_rc_sel $0\dec30_rc_sel[1:0] + end + attribute \src "issuer_ls180.v:74796.3-74832.6" + process $proc$issuer_ls180.v:74796$3550 + assign { } { } + assign { } { } + assign $0\dec30_cry_in[1:0] $1\dec30_cry_in[1:0] + attribute \src "issuer_ls180.v:74797.5-74797.29" + switch \initial + attribute \src "issuer_ls180.v:74797.9-74797.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0100 + assign { } { } + assign $1\dec30_cry_in[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0101 + assign { } { } + assign $1\dec30_cry_in[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $1\dec30_cry_in[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0001 + assign { } { } + assign $1\dec30_cry_in[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0010 + assign { } { } + assign $1\dec30_cry_in[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0011 + assign { } { } + assign $1\dec30_cry_in[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\dec30_cry_in[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $1\dec30_cry_in[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\dec30_cry_in[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'1001 + assign { } { } + assign $1\dec30_cry_in[1:0] 2'00 + case + assign $1\dec30_cry_in[1:0] 2'00 + end + sync always + update \dec30_cry_in $0\dec30_cry_in[1:0] + end + attribute \src "issuer_ls180.v:74833.3-74869.6" + process $proc$issuer_ls180.v:74833$3551 + assign { } { } + assign { } { } + assign $0\dec30_asmcode[7:0] $1\dec30_asmcode[7:0] + attribute \src "issuer_ls180.v:74834.5-74834.29" + switch \initial + attribute \src "issuer_ls180.v:74834.9-74834.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0100 + assign { } { } + assign $1\dec30_asmcode[7:0] 8'10010100 + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0101 + assign { } { } + assign $1\dec30_asmcode[7:0] 8'10010100 + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $1\dec30_asmcode[7:0] 8'10010101 + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0001 + assign { } { } + assign $1\dec30_asmcode[7:0] 8'10010101 + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0010 + assign { } { } + assign $1\dec30_asmcode[7:0] 8'10010110 + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0011 + assign { } { } + assign $1\dec30_asmcode[7:0] 8'10010110 + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\dec30_asmcode[7:0] 8'10010111 + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $1\dec30_asmcode[7:0] 8'10010111 + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\dec30_asmcode[7:0] 8'10010010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'1001 + assign { } { } + assign $1\dec30_asmcode[7:0] 8'10010011 + case + assign $1\dec30_asmcode[7:0] 8'00000000 + end + sync always + update \dec30_asmcode $0\dec30_asmcode[7:0] + end + attribute \src "issuer_ls180.v:74870.3-74906.6" + process $proc$issuer_ls180.v:74870$3552 + assign { } { } + assign { } { } + assign $0\dec30_inv_a[0:0] $1\dec30_inv_a[0:0] + attribute \src "issuer_ls180.v:74871.5-74871.29" + switch \initial + attribute \src "issuer_ls180.v:74871.9-74871.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0100 + assign { } { } + assign $1\dec30_inv_a[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0101 + assign { } { } + assign $1\dec30_inv_a[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $1\dec30_inv_a[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0001 + assign { } { } + assign $1\dec30_inv_a[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0010 + assign { } { } + assign $1\dec30_inv_a[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0011 + assign { } { } + assign $1\dec30_inv_a[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\dec30_inv_a[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $1\dec30_inv_a[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\dec30_inv_a[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'1001 + assign { } { } + assign $1\dec30_inv_a[0:0] 1'0 + case + assign $1\dec30_inv_a[0:0] 1'0 + end + sync always + update \dec30_inv_a $0\dec30_inv_a[0:0] + end + attribute \src "issuer_ls180.v:74907.3-74943.6" + process $proc$issuer_ls180.v:74907$3553 + assign { } { } + assign { } { } + assign $0\dec30_inv_out[0:0] $1\dec30_inv_out[0:0] + attribute \src "issuer_ls180.v:74908.5-74908.29" + switch \initial + attribute \src "issuer_ls180.v:74908.9-74908.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0100 + assign { } { } + assign $1\dec30_inv_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0101 + assign { } { } + assign $1\dec30_inv_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $1\dec30_inv_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0001 + assign { } { } + assign $1\dec30_inv_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0010 + assign { } { } + assign $1\dec30_inv_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0011 + assign { } { } + assign $1\dec30_inv_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\dec30_inv_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $1\dec30_inv_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\dec30_inv_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'1001 + assign { } { } + assign $1\dec30_inv_out[0:0] 1'0 + case + assign $1\dec30_inv_out[0:0] 1'0 + end + sync always + update \dec30_inv_out $0\dec30_inv_out[0:0] + end + attribute \src "issuer_ls180.v:74944.3-74980.6" + process $proc$issuer_ls180.v:74944$3554 + assign { } { } + assign { } { } + assign $0\dec30_cry_out[0:0] $1\dec30_cry_out[0:0] + attribute \src "issuer_ls180.v:74945.5-74945.29" + switch \initial + attribute \src "issuer_ls180.v:74945.9-74945.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0100 + assign { } { } + assign $1\dec30_cry_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0101 + assign { } { } + assign $1\dec30_cry_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $1\dec30_cry_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0001 + assign { } { } + assign $1\dec30_cry_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0010 + assign { } { } + assign $1\dec30_cry_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0011 + assign { } { } + assign $1\dec30_cry_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\dec30_cry_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $1\dec30_cry_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\dec30_cry_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'1001 + assign { } { } + assign $1\dec30_cry_out[0:0] 1'0 + case + assign $1\dec30_cry_out[0:0] 1'0 + end + sync always + update \dec30_cry_out $0\dec30_cry_out[0:0] + end + attribute \src "issuer_ls180.v:74981.3-75017.6" + process $proc$issuer_ls180.v:74981$3555 + assign { } { } + assign { } { } + assign $0\dec30_br[0:0] $1\dec30_br[0:0] + attribute \src "issuer_ls180.v:74982.5-74982.29" + switch \initial + attribute \src "issuer_ls180.v:74982.9-74982.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0100 + assign { } { } + assign $1\dec30_br[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0101 + assign { } { } + assign $1\dec30_br[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $1\dec30_br[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0001 + assign { } { } + assign $1\dec30_br[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0010 + assign { } { } + assign $1\dec30_br[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0011 + assign { } { } + assign $1\dec30_br[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\dec30_br[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $1\dec30_br[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\dec30_br[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'1001 + assign { } { } + assign $1\dec30_br[0:0] 1'0 + case + assign $1\dec30_br[0:0] 1'0 + end + sync always + update \dec30_br $0\dec30_br[0:0] + end + attribute \src "issuer_ls180.v:75018.3-75054.6" + process $proc$issuer_ls180.v:75018$3556 + assign { } { } + assign { } { } + assign $0\dec30_sgn_ext[0:0] $1\dec30_sgn_ext[0:0] + attribute \src "issuer_ls180.v:75019.5-75019.29" + switch \initial + attribute \src "issuer_ls180.v:75019.9-75019.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0100 + assign { } { } + assign $1\dec30_sgn_ext[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0101 + assign { } { } + assign $1\dec30_sgn_ext[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $1\dec30_sgn_ext[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0001 + assign { } { } + assign $1\dec30_sgn_ext[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0010 + assign { } { } + assign $1\dec30_sgn_ext[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0011 + assign { } { } + assign $1\dec30_sgn_ext[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\dec30_sgn_ext[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $1\dec30_sgn_ext[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\dec30_sgn_ext[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'1001 + assign { } { } + assign $1\dec30_sgn_ext[0:0] 1'0 + case + assign $1\dec30_sgn_ext[0:0] 1'0 + end + sync always + update \dec30_sgn_ext $0\dec30_sgn_ext[0:0] + end + attribute \src "issuer_ls180.v:75055.3-75091.6" + process $proc$issuer_ls180.v:75055$3557 + assign { } { } + assign { } { } + assign $0\dec30_internal_op[6:0] $1\dec30_internal_op[6:0] + attribute \src "issuer_ls180.v:75056.5-75056.29" + switch \initial + attribute \src "issuer_ls180.v:75056.9-75056.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0100 + assign { } { } + assign $1\dec30_internal_op[6:0] 7'0111000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0101 + assign { } { } + assign $1\dec30_internal_op[6:0] 7'0111000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $1\dec30_internal_op[6:0] 7'0111001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0001 + assign { } { } + assign $1\dec30_internal_op[6:0] 7'0111001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0010 + assign { } { } + assign $1\dec30_internal_op[6:0] 7'0111010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0011 + assign { } { } + assign $1\dec30_internal_op[6:0] 7'0111010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\dec30_internal_op[6:0] 7'0111000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $1\dec30_internal_op[6:0] 7'0111000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\dec30_internal_op[6:0] 7'0111001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'1001 + assign { } { } + assign $1\dec30_internal_op[6:0] 7'0111010 + case + assign $1\dec30_internal_op[6:0] 7'0000000 + end + sync always + update \dec30_internal_op $0\dec30_internal_op[6:0] + end + attribute \src "issuer_ls180.v:75092.3-75128.6" + process $proc$issuer_ls180.v:75092$3558 + assign { } { } + assign { } { } + assign $0\dec30_rsrv[0:0] $1\dec30_rsrv[0:0] + attribute \src "issuer_ls180.v:75093.5-75093.29" + switch \initial + attribute \src "issuer_ls180.v:75093.9-75093.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0100 + assign { } { } + assign $1\dec30_rsrv[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0101 + assign { } { } + assign $1\dec30_rsrv[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $1\dec30_rsrv[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0001 + assign { } { } + assign $1\dec30_rsrv[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0010 + assign { } { } + assign $1\dec30_rsrv[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0011 + assign { } { } + assign $1\dec30_rsrv[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\dec30_rsrv[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $1\dec30_rsrv[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\dec30_rsrv[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'1001 + assign { } { } + assign $1\dec30_rsrv[0:0] 1'0 + case + assign $1\dec30_rsrv[0:0] 1'0 + end + sync always + update \dec30_rsrv $0\dec30_rsrv[0:0] + end + attribute \src "issuer_ls180.v:75129.3-75165.6" + process $proc$issuer_ls180.v:75129$3559 + assign { } { } + assign { } { } + assign $0\dec30_is_32b[0:0] $1\dec30_is_32b[0:0] + attribute \src "issuer_ls180.v:75130.5-75130.29" + switch \initial + attribute \src "issuer_ls180.v:75130.9-75130.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0100 + assign { } { } + assign $1\dec30_is_32b[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0101 + assign { } { } + assign $1\dec30_is_32b[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $1\dec30_is_32b[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0001 + assign { } { } + assign $1\dec30_is_32b[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0010 + assign { } { } + assign $1\dec30_is_32b[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0011 + assign { } { } + assign $1\dec30_is_32b[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\dec30_is_32b[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $1\dec30_is_32b[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\dec30_is_32b[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'1001 + assign { } { } + assign $1\dec30_is_32b[0:0] 1'0 + case + assign $1\dec30_is_32b[0:0] 1'0 + end + sync always + update \dec30_is_32b $0\dec30_is_32b[0:0] + end + attribute \src "issuer_ls180.v:75166.3-75202.6" + process $proc$issuer_ls180.v:75166$3560 + assign { } { } + assign { } { } + assign $0\dec30_sgn[0:0] $1\dec30_sgn[0:0] + attribute \src "issuer_ls180.v:75167.5-75167.29" + switch \initial + attribute \src "issuer_ls180.v:75167.9-75167.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0100 + assign { } { } + assign $1\dec30_sgn[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0101 + assign { } { } + assign $1\dec30_sgn[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $1\dec30_sgn[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0001 + assign { } { } + assign $1\dec30_sgn[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0010 + assign { } { } + assign $1\dec30_sgn[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0011 + assign { } { } + assign $1\dec30_sgn[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\dec30_sgn[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $1\dec30_sgn[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\dec30_sgn[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'1001 + assign { } { } + assign $1\dec30_sgn[0:0] 1'0 + case + assign $1\dec30_sgn[0:0] 1'0 + end + sync always + update \dec30_sgn $0\dec30_sgn[0:0] + end + attribute \src "issuer_ls180.v:75203.3-75239.6" + process $proc$issuer_ls180.v:75203$3561 + assign { } { } + assign { } { } + assign $0\dec30_lk[0:0] $1\dec30_lk[0:0] + attribute \src "issuer_ls180.v:75204.5-75204.29" + switch \initial + attribute \src "issuer_ls180.v:75204.9-75204.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0100 + assign { } { } + assign $1\dec30_lk[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0101 + assign { } { } + assign $1\dec30_lk[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $1\dec30_lk[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0001 + assign { } { } + assign $1\dec30_lk[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0010 + assign { } { } + assign $1\dec30_lk[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0011 + assign { } { } + assign $1\dec30_lk[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\dec30_lk[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $1\dec30_lk[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\dec30_lk[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'1001 + assign { } { } + assign $1\dec30_lk[0:0] 1'0 + case + assign $1\dec30_lk[0:0] 1'0 + end + sync always + update \dec30_lk $0\dec30_lk[0:0] + end + attribute \src "issuer_ls180.v:75240.3-75276.6" + process $proc$issuer_ls180.v:75240$3562 + assign { } { } + assign { } { } + assign $0\dec30_sgl_pipe[0:0] $1\dec30_sgl_pipe[0:0] + attribute \src "issuer_ls180.v:75241.5-75241.29" + switch \initial + attribute \src "issuer_ls180.v:75241.9-75241.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0100 + assign { } { } + assign $1\dec30_sgl_pipe[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0101 + assign { } { } + assign $1\dec30_sgl_pipe[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $1\dec30_sgl_pipe[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0001 + assign { } { } + assign $1\dec30_sgl_pipe[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0010 + assign { } { } + assign $1\dec30_sgl_pipe[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0011 + assign { } { } + assign $1\dec30_sgl_pipe[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\dec30_sgl_pipe[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $1\dec30_sgl_pipe[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\dec30_sgl_pipe[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'1001 + assign { } { } + assign $1\dec30_sgl_pipe[0:0] 1'0 + case + assign $1\dec30_sgl_pipe[0:0] 1'0 + end + sync always + update \dec30_sgl_pipe $0\dec30_sgl_pipe[0:0] + end + attribute \src "issuer_ls180.v:75277.3-75313.6" + process $proc$issuer_ls180.v:75277$3563 + assign { } { } + assign { } { } + assign $0\dec30_form[4:0] $1\dec30_form[4:0] + attribute \src "issuer_ls180.v:75278.5-75278.29" + switch \initial + attribute \src "issuer_ls180.v:75278.9-75278.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0100 + assign { } { } + assign $1\dec30_form[4:0] 5'10100 + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0101 + assign { } { } + assign $1\dec30_form[4:0] 5'10100 + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $1\dec30_form[4:0] 5'10101 + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0001 + assign { } { } + assign $1\dec30_form[4:0] 5'10101 + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0010 + assign { } { } + assign $1\dec30_form[4:0] 5'10100 + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0011 + assign { } { } + assign $1\dec30_form[4:0] 5'10100 + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\dec30_form[4:0] 5'10100 + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $1\dec30_form[4:0] 5'10100 + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\dec30_form[4:0] 5'10100 + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'1001 + assign { } { } + assign $1\dec30_form[4:0] 5'10100 + case + assign $1\dec30_form[4:0] 5'00000 + end + sync always + update \dec30_form $0\dec30_form[4:0] + end + attribute \src "issuer_ls180.v:75314.3-75350.6" + process $proc$issuer_ls180.v:75314$3564 + assign { } { } + assign { } { } + assign $0\dec30_in1_sel[2:0] $1\dec30_in1_sel[2:0] + attribute \src "issuer_ls180.v:75315.5-75315.29" + switch \initial + attribute \src "issuer_ls180.v:75315.9-75315.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0100 + assign { } { } + assign $1\dec30_in1_sel[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0101 + assign { } { } + assign $1\dec30_in1_sel[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $1\dec30_in1_sel[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0001 + assign { } { } + assign $1\dec30_in1_sel[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0010 + assign { } { } + assign $1\dec30_in1_sel[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0011 + assign { } { } + assign $1\dec30_in1_sel[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\dec30_in1_sel[2:0] 3'001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $1\dec30_in1_sel[2:0] 3'001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\dec30_in1_sel[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'1001 + assign { } { } + assign $1\dec30_in1_sel[2:0] 3'000 + case + assign $1\dec30_in1_sel[2:0] 3'000 + end + sync always + update \dec30_in1_sel $0\dec30_in1_sel[2:0] + end + attribute \src "issuer_ls180.v:75351.3-75387.6" + process $proc$issuer_ls180.v:75351$3565 + assign { } { } + assign { } { } + assign $0\dec30_in2_sel[3:0] $1\dec30_in2_sel[3:0] + attribute \src "issuer_ls180.v:75352.5-75352.29" + switch \initial + attribute \src "issuer_ls180.v:75352.9-75352.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0100 + assign { } { } + assign $1\dec30_in2_sel[3:0] 4'1010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0101 + assign { } { } + assign $1\dec30_in2_sel[3:0] 4'1010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $1\dec30_in2_sel[3:0] 4'1010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0001 + assign { } { } + assign $1\dec30_in2_sel[3:0] 4'1010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0010 + assign { } { } + assign $1\dec30_in2_sel[3:0] 4'1010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0011 + assign { } { } + assign $1\dec30_in2_sel[3:0] 4'1010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\dec30_in2_sel[3:0] 4'1010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $1\dec30_in2_sel[3:0] 4'1010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\dec30_in2_sel[3:0] 4'0001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'1001 + assign { } { } + assign $1\dec30_in2_sel[3:0] 4'0001 + case + assign $1\dec30_in2_sel[3:0] 4'0000 + end + sync always + update \dec30_in2_sel $0\dec30_in2_sel[3:0] + end + attribute \src "issuer_ls180.v:75388.3-75424.6" + process $proc$issuer_ls180.v:75388$3566 + assign { } { } + assign { } { } + assign $0\dec30_in3_sel[1:0] $1\dec30_in3_sel[1:0] + attribute \src "issuer_ls180.v:75389.5-75389.29" + switch \initial + attribute \src "issuer_ls180.v:75389.9-75389.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0100 + assign { } { } + assign $1\dec30_in3_sel[1:0] 2'01 + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0101 + assign { } { } + assign $1\dec30_in3_sel[1:0] 2'01 + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $1\dec30_in3_sel[1:0] 2'01 + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0001 + assign { } { } + assign $1\dec30_in3_sel[1:0] 2'01 + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0010 + assign { } { } + assign $1\dec30_in3_sel[1:0] 2'01 + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0011 + assign { } { } + assign $1\dec30_in3_sel[1:0] 2'01 + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\dec30_in3_sel[1:0] 2'01 + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $1\dec30_in3_sel[1:0] 2'01 + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\dec30_in3_sel[1:0] 2'01 + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'1001 + assign { } { } + assign $1\dec30_in3_sel[1:0] 2'01 + case + assign $1\dec30_in3_sel[1:0] 2'00 + end + sync always + update \dec30_in3_sel $0\dec30_in3_sel[1:0] + end + attribute \src "issuer_ls180.v:75425.3-75461.6" + process $proc$issuer_ls180.v:75425$3567 + assign { } { } + assign { } { } + assign $0\dec30_out_sel[1:0] $1\dec30_out_sel[1:0] + attribute \src "issuer_ls180.v:75426.5-75426.29" + switch \initial + attribute \src "issuer_ls180.v:75426.9-75426.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0100 + assign { } { } + assign $1\dec30_out_sel[1:0] 2'10 + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0101 + assign { } { } + assign $1\dec30_out_sel[1:0] 2'10 + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $1\dec30_out_sel[1:0] 2'10 + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0001 + assign { } { } + assign $1\dec30_out_sel[1:0] 2'10 + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0010 + assign { } { } + assign $1\dec30_out_sel[1:0] 2'10 + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0011 + assign { } { } + assign $1\dec30_out_sel[1:0] 2'10 + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\dec30_out_sel[1:0] 2'10 + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $1\dec30_out_sel[1:0] 2'10 + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\dec30_out_sel[1:0] 2'10 + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'1001 + assign { } { } + assign $1\dec30_out_sel[1:0] 2'10 + case + assign $1\dec30_out_sel[1:0] 2'00 + end + sync always + update \dec30_out_sel $0\dec30_out_sel[1:0] + end + attribute \src "issuer_ls180.v:75462.3-75498.6" + process $proc$issuer_ls180.v:75462$3568 + assign { } { } + assign { } { } + assign $0\dec30_cr_in[2:0] $1\dec30_cr_in[2:0] + attribute \src "issuer_ls180.v:75463.5-75463.29" + switch \initial + attribute \src "issuer_ls180.v:75463.9-75463.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0100 + assign { } { } + assign $1\dec30_cr_in[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0101 + assign { } { } + assign $1\dec30_cr_in[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $1\dec30_cr_in[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0001 + assign { } { } + assign $1\dec30_cr_in[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0010 + assign { } { } + assign $1\dec30_cr_in[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0011 + assign { } { } + assign $1\dec30_cr_in[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\dec30_cr_in[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $1\dec30_cr_in[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\dec30_cr_in[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'1001 + assign { } { } + assign $1\dec30_cr_in[2:0] 3'000 + case + assign $1\dec30_cr_in[2:0] 3'000 + end + sync always + update \dec30_cr_in $0\dec30_cr_in[2:0] + end + attribute \src "issuer_ls180.v:75499.3-75535.6" + process $proc$issuer_ls180.v:75499$3569 + assign { } { } + assign { } { } + assign $0\dec30_cr_out[2:0] $1\dec30_cr_out[2:0] + attribute \src "issuer_ls180.v:75500.5-75500.29" + switch \initial + attribute \src "issuer_ls180.v:75500.9-75500.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0100 + assign { } { } + assign $1\dec30_cr_out[2:0] 3'001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0101 + assign { } { } + assign $1\dec30_cr_out[2:0] 3'001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $1\dec30_cr_out[2:0] 3'001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0001 + assign { } { } + assign $1\dec30_cr_out[2:0] 3'001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0010 + assign { } { } + assign $1\dec30_cr_out[2:0] 3'001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0011 + assign { } { } + assign $1\dec30_cr_out[2:0] 3'001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\dec30_cr_out[2:0] 3'001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $1\dec30_cr_out[2:0] 3'001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\dec30_cr_out[2:0] 3'001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'1001 + assign { } { } + assign $1\dec30_cr_out[2:0] 3'001 + case + assign $1\dec30_cr_out[2:0] 3'000 + end + sync always + update \dec30_cr_out $0\dec30_cr_out[2:0] + end + connect \opcode_switch \opcode_in [4:1] +end +attribute \src "issuer_ls180.v:75541.1-81911.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.dec2.dec.dec31" +attribute \generator "nMigen" +module \dec31 + attribute \src "issuer_ls180.v:80610.3-80670.6" + wire width 8 $0\dec31_asmcode[7:0] + attribute \src "issuer_ls180.v:81464.3-81524.6" + wire $0\dec31_br[0:0] + attribute \src "issuer_ls180.v:80915.3-80975.6" + wire width 3 $0\dec31_cr_in[2:0] + attribute \src "issuer_ls180.v:80976.3-81036.6" + wire width 3 $0\dec31_cr_out[2:0] + attribute \src "issuer_ls180.v:81220.3-81280.6" + wire width 2 $0\dec31_cry_in[1:0] + attribute \src "issuer_ls180.v:81403.3-81463.6" + wire $0\dec31_cry_out[0:0] + attribute \src "issuer_ls180.v:80549.3-80609.6" + wire width 5 $0\dec31_form[4:0] + attribute \src "issuer_ls180.v:80427.3-80487.6" + wire width 12 $0\dec31_function_unit[11:0] + attribute \src "issuer_ls180.v:80671.3-80731.6" + wire width 3 $0\dec31_in1_sel[2:0] + attribute \src "issuer_ls180.v:80732.3-80792.6" + wire width 4 $0\dec31_in2_sel[3:0] + attribute \src "issuer_ls180.v:80793.3-80853.6" + wire width 2 $0\dec31_in3_sel[1:0] + attribute \src "issuer_ls180.v:80488.3-80548.6" + wire width 7 $0\dec31_internal_op[6:0] + attribute \src "issuer_ls180.v:81281.3-81341.6" + wire $0\dec31_inv_a[0:0] + attribute \src "issuer_ls180.v:81342.3-81402.6" + wire $0\dec31_inv_out[0:0] + attribute \src "issuer_ls180.v:81647.3-81707.6" + wire $0\dec31_is_32b[0:0] + attribute \src "issuer_ls180.v:81037.3-81097.6" + wire width 4 $0\dec31_ldst_len[3:0] + attribute \src "issuer_ls180.v:81769.3-81829.6" + wire $0\dec31_lk[0:0] + attribute \src "issuer_ls180.v:80854.3-80914.6" + wire width 2 $0\dec31_out_sel[1:0] + attribute \src "issuer_ls180.v:81159.3-81219.6" + wire width 2 $0\dec31_rc_sel[1:0] + attribute \src "issuer_ls180.v:81586.3-81646.6" + wire $0\dec31_rsrv[0:0] + attribute \src "issuer_ls180.v:81830.3-81890.6" + wire $0\dec31_sgl_pipe[0:0] + attribute \src "issuer_ls180.v:81708.3-81768.6" + wire $0\dec31_sgn[0:0] + attribute \src "issuer_ls180.v:81525.3-81585.6" + wire $0\dec31_sgn_ext[0:0] + attribute \src "issuer_ls180.v:81098.3-81158.6" + wire width 2 $0\dec31_upd[1:0] + attribute \src "issuer_ls180.v:75542.7-75542.20" + wire $0\initial[0:0] + attribute \src "issuer_ls180.v:80610.3-80670.6" + wire width 8 $1\dec31_asmcode[7:0] + attribute \src "issuer_ls180.v:81464.3-81524.6" + wire $1\dec31_br[0:0] + attribute \src "issuer_ls180.v:80915.3-80975.6" + wire width 3 $1\dec31_cr_in[2:0] + attribute \src "issuer_ls180.v:80976.3-81036.6" + wire width 3 $1\dec31_cr_out[2:0] + attribute \src "issuer_ls180.v:81220.3-81280.6" + wire width 2 $1\dec31_cry_in[1:0] + attribute \src "issuer_ls180.v:81403.3-81463.6" + wire $1\dec31_cry_out[0:0] + attribute \src "issuer_ls180.v:80549.3-80609.6" + wire width 5 $1\dec31_form[4:0] + attribute \src "issuer_ls180.v:80427.3-80487.6" + wire width 12 $1\dec31_function_unit[11:0] + attribute \src "issuer_ls180.v:80671.3-80731.6" + wire width 3 $1\dec31_in1_sel[2:0] + attribute \src "issuer_ls180.v:80732.3-80792.6" + wire width 4 $1\dec31_in2_sel[3:0] + attribute \src "issuer_ls180.v:80793.3-80853.6" + wire width 2 $1\dec31_in3_sel[1:0] + attribute \src "issuer_ls180.v:80488.3-80548.6" + wire width 7 $1\dec31_internal_op[6:0] + attribute \src "issuer_ls180.v:81281.3-81341.6" + wire $1\dec31_inv_a[0:0] + attribute \src "issuer_ls180.v:81342.3-81402.6" + wire $1\dec31_inv_out[0:0] + attribute \src "issuer_ls180.v:81647.3-81707.6" + wire $1\dec31_is_32b[0:0] + attribute \src "issuer_ls180.v:81037.3-81097.6" + wire width 4 $1\dec31_ldst_len[3:0] + attribute \src "issuer_ls180.v:81769.3-81829.6" + wire $1\dec31_lk[0:0] + attribute \src "issuer_ls180.v:80854.3-80914.6" + wire width 2 $1\dec31_out_sel[1:0] + attribute \src "issuer_ls180.v:81159.3-81219.6" + wire width 2 $1\dec31_rc_sel[1:0] + attribute \src "issuer_ls180.v:81586.3-81646.6" + wire $1\dec31_rsrv[0:0] + attribute \src "issuer_ls180.v:81830.3-81890.6" + wire $1\dec31_sgl_pipe[0:0] + attribute \src "issuer_ls180.v:81708.3-81768.6" + wire $1\dec31_sgn[0:0] + attribute \src "issuer_ls180.v:81525.3-81585.6" + wire $1\dec31_sgn_ext[0:0] + attribute \src "issuer_ls180.v:81098.3-81158.6" + wire width 2 $1\dec31_upd[1:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 8 output 4 \dec31_asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 18 \dec31_br + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 9 \dec31_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 10 \dec31_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 14 \dec31_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 17 \dec31_cry_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 8 \dec31_dec_sub0_dec31_dec_sub0_asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub0_dec31_dec_sub0_br + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 \dec31_dec_sub0_dec31_dec_sub0_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 \dec31_dec_sub0_dec31_dec_sub0_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \dec31_dec_sub0_dec31_dec_sub0_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub0_dec31_dec_sub0_cry_out + attribute \enum_base_type "Form" + attribute \enum_value_00000 "NONE" + attribute \enum_value_00001 "I" + attribute \enum_value_00010 "B" + attribute \enum_value_00011 "SC" + attribute \enum_value_00100 "D" + attribute \enum_value_00101 "DS" + attribute \enum_value_00110 "DQ" + attribute \enum_value_00111 "DX" + attribute \enum_value_01000 "X" + attribute \enum_value_01001 "XL" + attribute \enum_value_01010 "XFX" + attribute \enum_value_01011 "XFL" + attribute \enum_value_01100 "XX1" + attribute \enum_value_01101 "XX2" + attribute \enum_value_01110 "XX3" + attribute \enum_value_01111 "XX4" + attribute \enum_value_10000 "XS" + attribute \enum_value_10001 "XO" + attribute \enum_value_10010 "A" + attribute \enum_value_10011 "M" + attribute \enum_value_10100 "MD" + attribute \enum_value_10101 "MDS" + attribute \enum_value_10110 "VA" + attribute \enum_value_10111 "VC" + attribute \enum_value_11000 "VX" + attribute \enum_value_11001 "EVX" + attribute \enum_value_11010 "EVS" + attribute \enum_value_11011 "Z22" + attribute \enum_value_11100 "Z23" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 5 \dec31_dec_sub0_dec31_dec_sub0_form + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 12 \dec31_dec_sub0_dec31_dec_sub0_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 \dec31_dec_sub0_dec31_dec_sub0_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 \dec31_dec_sub0_dec31_dec_sub0_in2_sel + attribute \enum_base_type "In3Sel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RS" + attribute \enum_value_10 "RB" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \dec31_dec_sub0_dec31_dec_sub0_in3_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 7 \dec31_dec_sub0_dec31_dec_sub0_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub0_dec31_dec_sub0_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub0_dec31_dec_sub0_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub0_dec31_dec_sub0_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 \dec31_dec_sub0_dec31_dec_sub0_ldst_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub0_dec31_dec_sub0_lk + attribute \enum_base_type "OutSel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RT" + attribute \enum_value_10 "RA" + attribute \enum_value_11 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \dec31_dec_sub0_dec31_dec_sub0_out_sel + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \dec31_dec_sub0_dec31_dec_sub0_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub0_dec31_dec_sub0_rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub0_dec31_dec_sub0_sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub0_dec31_dec_sub0_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub0_dec31_dec_sub0_sgn_ext + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \dec31_dec_sub0_dec31_dec_sub0_upd + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + wire width 32 \dec31_dec_sub0_opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 8 \dec31_dec_sub10_dec31_dec_sub10_asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub10_dec31_dec_sub10_br + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 \dec31_dec_sub10_dec31_dec_sub10_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 \dec31_dec_sub10_dec31_dec_sub10_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \dec31_dec_sub10_dec31_dec_sub10_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub10_dec31_dec_sub10_cry_out + attribute \enum_base_type "Form" + attribute \enum_value_00000 "NONE" + attribute \enum_value_00001 "I" + attribute \enum_value_00010 "B" + attribute \enum_value_00011 "SC" + attribute \enum_value_00100 "D" + attribute \enum_value_00101 "DS" + attribute \enum_value_00110 "DQ" + attribute \enum_value_00111 "DX" + attribute \enum_value_01000 "X" + attribute \enum_value_01001 "XL" + attribute \enum_value_01010 "XFX" + attribute \enum_value_01011 "XFL" + attribute \enum_value_01100 "XX1" + attribute \enum_value_01101 "XX2" + attribute \enum_value_01110 "XX3" + attribute \enum_value_01111 "XX4" + attribute \enum_value_10000 "XS" + attribute \enum_value_10001 "XO" + attribute \enum_value_10010 "A" + attribute \enum_value_10011 "M" + attribute \enum_value_10100 "MD" + attribute \enum_value_10101 "MDS" + attribute \enum_value_10110 "VA" + attribute \enum_value_10111 "VC" + attribute \enum_value_11000 "VX" + attribute \enum_value_11001 "EVX" + attribute \enum_value_11010 "EVS" + attribute \enum_value_11011 "Z22" + attribute \enum_value_11100 "Z23" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 5 \dec31_dec_sub10_dec31_dec_sub10_form + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 12 \dec31_dec_sub10_dec31_dec_sub10_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 \dec31_dec_sub10_dec31_dec_sub10_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 \dec31_dec_sub10_dec31_dec_sub10_in2_sel + attribute \enum_base_type "In3Sel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RS" + attribute \enum_value_10 "RB" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \dec31_dec_sub10_dec31_dec_sub10_in3_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute 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attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + wire width 32 \dec31_dec_sub8_opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 8 \dec31_dec_sub9_dec31_dec_sub9_asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub9_dec31_dec_sub9_br + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 \dec31_dec_sub9_dec31_dec_sub9_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute 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+ attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute 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"OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 7 \dec31_dec_sub9_dec31_dec_sub9_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub9_dec31_dec_sub9_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub9_dec31_dec_sub9_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub9_dec31_dec_sub9_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 \dec31_dec_sub9_dec31_dec_sub9_ldst_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub9_dec31_dec_sub9_lk + attribute \enum_base_type "OutSel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RT" + attribute \enum_value_10 "RA" + attribute \enum_value_11 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \dec31_dec_sub9_dec31_dec_sub9_out_sel + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \dec31_dec_sub9_dec31_dec_sub9_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub9_dec31_dec_sub9_rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub9_dec31_dec_sub9_sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub9_dec31_dec_sub9_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec31_dec_sub9_dec31_dec_sub9_sgn_ext + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \dec31_dec_sub9_dec31_dec_sub9_upd + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + wire width 32 \dec31_dec_sub9_opcode_in + attribute \enum_base_type "Form" + attribute \enum_value_00000 "NONE" + attribute \enum_value_00001 "I" + attribute \enum_value_00010 "B" + attribute \enum_value_00011 "SC" + attribute \enum_value_00100 "D" + attribute \enum_value_00101 "DS" + attribute \enum_value_00110 "DQ" + attribute \enum_value_00111 "DX" + attribute \enum_value_01000 "X" + attribute \enum_value_01001 "XL" + attribute \enum_value_01010 "XFX" + attribute \enum_value_01011 "XFL" + attribute \enum_value_01100 "XX1" + attribute \enum_value_01101 "XX2" + attribute \enum_value_01110 "XX3" + attribute \enum_value_01111 "XX4" + attribute \enum_value_10000 "XS" + attribute \enum_value_10001 "XO" + attribute \enum_value_10010 "A" + attribute \enum_value_10011 "M" + attribute \enum_value_10100 "MD" + attribute \enum_value_10101 "MDS" + attribute \enum_value_10110 "VA" + attribute \enum_value_10111 "VC" + attribute \enum_value_11000 "VX" + attribute \enum_value_11001 "EVX" + attribute \enum_value_11010 "EVS" + attribute \enum_value_11011 "Z22" + attribute \enum_value_11100 "Z23" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 5 output 3 \dec31_form + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 12 output 1 \dec31_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 5 \dec31_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 output 6 \dec31_in2_sel + attribute \enum_base_type "In3Sel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RS" + attribute \enum_value_10 "RB" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 7 \dec31_in3_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 7 output 2 \dec31_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 15 \dec31_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 16 \dec31_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 21 \dec31_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 output 11 \dec31_ldst_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 23 \dec31_lk + attribute \enum_base_type "OutSel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RT" + attribute \enum_value_10 "RA" + attribute \enum_value_11 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 8 \dec31_out_sel + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 13 \dec31_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 20 \dec31_rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 24 \dec31_sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 22 \dec31_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 19 \dec31_sgn_ext + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 12 \dec31_upd + attribute \src "issuer_ls180.v:75542.7-75542.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:326" + wire width 5 \opc_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + wire width 32 input 25 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:320" + wire width 10 \opcode_switch + attribute \module_not_derived 1 + attribute \src "issuer_ls180.v:79941.18-79967.4" + cell \dec31_dec_sub0 \dec31_dec_sub0 + connect \dec31_dec_sub0_asmcode \dec31_dec_sub0_dec31_dec_sub0_asmcode + connect \dec31_dec_sub0_br \dec31_dec_sub0_dec31_dec_sub0_br + connect \dec31_dec_sub0_cr_in \dec31_dec_sub0_dec31_dec_sub0_cr_in + connect \dec31_dec_sub0_cr_out \dec31_dec_sub0_dec31_dec_sub0_cr_out + connect \dec31_dec_sub0_cry_in \dec31_dec_sub0_dec31_dec_sub0_cry_in + connect \dec31_dec_sub0_cry_out \dec31_dec_sub0_dec31_dec_sub0_cry_out + connect \dec31_dec_sub0_form \dec31_dec_sub0_dec31_dec_sub0_form + connect \dec31_dec_sub0_function_unit \dec31_dec_sub0_dec31_dec_sub0_function_unit + connect \dec31_dec_sub0_in1_sel \dec31_dec_sub0_dec31_dec_sub0_in1_sel + connect \dec31_dec_sub0_in2_sel \dec31_dec_sub0_dec31_dec_sub0_in2_sel + connect \dec31_dec_sub0_in3_sel \dec31_dec_sub0_dec31_dec_sub0_in3_sel + connect \dec31_dec_sub0_internal_op \dec31_dec_sub0_dec31_dec_sub0_internal_op + connect \dec31_dec_sub0_inv_a \dec31_dec_sub0_dec31_dec_sub0_inv_a + connect \dec31_dec_sub0_inv_out \dec31_dec_sub0_dec31_dec_sub0_inv_out + connect \dec31_dec_sub0_is_32b \dec31_dec_sub0_dec31_dec_sub0_is_32b + connect \dec31_dec_sub0_ldst_len \dec31_dec_sub0_dec31_dec_sub0_ldst_len + connect \dec31_dec_sub0_lk \dec31_dec_sub0_dec31_dec_sub0_lk + connect \dec31_dec_sub0_out_sel \dec31_dec_sub0_dec31_dec_sub0_out_sel + connect \dec31_dec_sub0_rc_sel \dec31_dec_sub0_dec31_dec_sub0_rc_sel + connect \dec31_dec_sub0_rsrv \dec31_dec_sub0_dec31_dec_sub0_rsrv + connect \dec31_dec_sub0_sgl_pipe \dec31_dec_sub0_dec31_dec_sub0_sgl_pipe + connect \dec31_dec_sub0_sgn \dec31_dec_sub0_dec31_dec_sub0_sgn + connect \dec31_dec_sub0_sgn_ext \dec31_dec_sub0_dec31_dec_sub0_sgn_ext + connect \dec31_dec_sub0_upd \dec31_dec_sub0_dec31_dec_sub0_upd + connect \opcode_in \dec31_dec_sub0_opcode_in + end + attribute \module_not_derived 1 + attribute \src "issuer_ls180.v:79968.19-79994.4" + cell \dec31_dec_sub10 \dec31_dec_sub10 + connect \dec31_dec_sub10_asmcode \dec31_dec_sub10_dec31_dec_sub10_asmcode + connect \dec31_dec_sub10_br \dec31_dec_sub10_dec31_dec_sub10_br + connect \dec31_dec_sub10_cr_in \dec31_dec_sub10_dec31_dec_sub10_cr_in + connect \dec31_dec_sub10_cr_out \dec31_dec_sub10_dec31_dec_sub10_cr_out + connect \dec31_dec_sub10_cry_in \dec31_dec_sub10_dec31_dec_sub10_cry_in + connect \dec31_dec_sub10_cry_out \dec31_dec_sub10_dec31_dec_sub10_cry_out + connect \dec31_dec_sub10_form \dec31_dec_sub10_dec31_dec_sub10_form + connect \dec31_dec_sub10_function_unit \dec31_dec_sub10_dec31_dec_sub10_function_unit + connect \dec31_dec_sub10_in1_sel \dec31_dec_sub10_dec31_dec_sub10_in1_sel + connect \dec31_dec_sub10_in2_sel \dec31_dec_sub10_dec31_dec_sub10_in2_sel + connect \dec31_dec_sub10_in3_sel \dec31_dec_sub10_dec31_dec_sub10_in3_sel + connect \dec31_dec_sub10_internal_op \dec31_dec_sub10_dec31_dec_sub10_internal_op + connect \dec31_dec_sub10_inv_a \dec31_dec_sub10_dec31_dec_sub10_inv_a + connect \dec31_dec_sub10_inv_out \dec31_dec_sub10_dec31_dec_sub10_inv_out + connect \dec31_dec_sub10_is_32b \dec31_dec_sub10_dec31_dec_sub10_is_32b + connect \dec31_dec_sub10_ldst_len \dec31_dec_sub10_dec31_dec_sub10_ldst_len + connect \dec31_dec_sub10_lk \dec31_dec_sub10_dec31_dec_sub10_lk + connect \dec31_dec_sub10_out_sel \dec31_dec_sub10_dec31_dec_sub10_out_sel + connect \dec31_dec_sub10_rc_sel \dec31_dec_sub10_dec31_dec_sub10_rc_sel + connect \dec31_dec_sub10_rsrv \dec31_dec_sub10_dec31_dec_sub10_rsrv + connect \dec31_dec_sub10_sgl_pipe \dec31_dec_sub10_dec31_dec_sub10_sgl_pipe + connect \dec31_dec_sub10_sgn \dec31_dec_sub10_dec31_dec_sub10_sgn + connect \dec31_dec_sub10_sgn_ext \dec31_dec_sub10_dec31_dec_sub10_sgn_ext + connect \dec31_dec_sub10_upd \dec31_dec_sub10_dec31_dec_sub10_upd + connect \opcode_in \dec31_dec_sub10_opcode_in + end + attribute \module_not_derived 1 + attribute \src "issuer_ls180.v:79995.19-80021.4" + cell \dec31_dec_sub11 \dec31_dec_sub11 + connect \dec31_dec_sub11_asmcode \dec31_dec_sub11_dec31_dec_sub11_asmcode + connect \dec31_dec_sub11_br \dec31_dec_sub11_dec31_dec_sub11_br + connect \dec31_dec_sub11_cr_in \dec31_dec_sub11_dec31_dec_sub11_cr_in + connect \dec31_dec_sub11_cr_out \dec31_dec_sub11_dec31_dec_sub11_cr_out + connect \dec31_dec_sub11_cry_in \dec31_dec_sub11_dec31_dec_sub11_cry_in + connect \dec31_dec_sub11_cry_out \dec31_dec_sub11_dec31_dec_sub11_cry_out + connect \dec31_dec_sub11_form \dec31_dec_sub11_dec31_dec_sub11_form + connect \dec31_dec_sub11_function_unit \dec31_dec_sub11_dec31_dec_sub11_function_unit + connect \dec31_dec_sub11_in1_sel \dec31_dec_sub11_dec31_dec_sub11_in1_sel + connect \dec31_dec_sub11_in2_sel \dec31_dec_sub11_dec31_dec_sub11_in2_sel + connect \dec31_dec_sub11_in3_sel \dec31_dec_sub11_dec31_dec_sub11_in3_sel + connect \dec31_dec_sub11_internal_op \dec31_dec_sub11_dec31_dec_sub11_internal_op + connect \dec31_dec_sub11_inv_a \dec31_dec_sub11_dec31_dec_sub11_inv_a + connect \dec31_dec_sub11_inv_out \dec31_dec_sub11_dec31_dec_sub11_inv_out + connect \dec31_dec_sub11_is_32b \dec31_dec_sub11_dec31_dec_sub11_is_32b + connect \dec31_dec_sub11_ldst_len \dec31_dec_sub11_dec31_dec_sub11_ldst_len + connect \dec31_dec_sub11_lk \dec31_dec_sub11_dec31_dec_sub11_lk + connect \dec31_dec_sub11_out_sel \dec31_dec_sub11_dec31_dec_sub11_out_sel + connect \dec31_dec_sub11_rc_sel \dec31_dec_sub11_dec31_dec_sub11_rc_sel + connect \dec31_dec_sub11_rsrv \dec31_dec_sub11_dec31_dec_sub11_rsrv + connect \dec31_dec_sub11_sgl_pipe \dec31_dec_sub11_dec31_dec_sub11_sgl_pipe + connect \dec31_dec_sub11_sgn \dec31_dec_sub11_dec31_dec_sub11_sgn + connect \dec31_dec_sub11_sgn_ext \dec31_dec_sub11_dec31_dec_sub11_sgn_ext + connect \dec31_dec_sub11_upd \dec31_dec_sub11_dec31_dec_sub11_upd + connect \opcode_in \dec31_dec_sub11_opcode_in + end + attribute \module_not_derived 1 + attribute \src "issuer_ls180.v:80022.19-80048.4" + cell \dec31_dec_sub15 \dec31_dec_sub15 + connect \dec31_dec_sub15_asmcode \dec31_dec_sub15_dec31_dec_sub15_asmcode + connect \dec31_dec_sub15_br \dec31_dec_sub15_dec31_dec_sub15_br + connect \dec31_dec_sub15_cr_in \dec31_dec_sub15_dec31_dec_sub15_cr_in + connect \dec31_dec_sub15_cr_out \dec31_dec_sub15_dec31_dec_sub15_cr_out + connect \dec31_dec_sub15_cry_in \dec31_dec_sub15_dec31_dec_sub15_cry_in + connect \dec31_dec_sub15_cry_out \dec31_dec_sub15_dec31_dec_sub15_cry_out + connect \dec31_dec_sub15_form \dec31_dec_sub15_dec31_dec_sub15_form + connect \dec31_dec_sub15_function_unit \dec31_dec_sub15_dec31_dec_sub15_function_unit + connect \dec31_dec_sub15_in1_sel \dec31_dec_sub15_dec31_dec_sub15_in1_sel + connect \dec31_dec_sub15_in2_sel \dec31_dec_sub15_dec31_dec_sub15_in2_sel + connect \dec31_dec_sub15_in3_sel \dec31_dec_sub15_dec31_dec_sub15_in3_sel + connect \dec31_dec_sub15_internal_op \dec31_dec_sub15_dec31_dec_sub15_internal_op + connect \dec31_dec_sub15_inv_a \dec31_dec_sub15_dec31_dec_sub15_inv_a + connect \dec31_dec_sub15_inv_out \dec31_dec_sub15_dec31_dec_sub15_inv_out + connect \dec31_dec_sub15_is_32b \dec31_dec_sub15_dec31_dec_sub15_is_32b + connect \dec31_dec_sub15_ldst_len \dec31_dec_sub15_dec31_dec_sub15_ldst_len + connect \dec31_dec_sub15_lk \dec31_dec_sub15_dec31_dec_sub15_lk + connect \dec31_dec_sub15_out_sel \dec31_dec_sub15_dec31_dec_sub15_out_sel + connect \dec31_dec_sub15_rc_sel \dec31_dec_sub15_dec31_dec_sub15_rc_sel + connect \dec31_dec_sub15_rsrv \dec31_dec_sub15_dec31_dec_sub15_rsrv + connect \dec31_dec_sub15_sgl_pipe \dec31_dec_sub15_dec31_dec_sub15_sgl_pipe + connect \dec31_dec_sub15_sgn \dec31_dec_sub15_dec31_dec_sub15_sgn + connect \dec31_dec_sub15_sgn_ext \dec31_dec_sub15_dec31_dec_sub15_sgn_ext + connect \dec31_dec_sub15_upd \dec31_dec_sub15_dec31_dec_sub15_upd + connect \opcode_in \dec31_dec_sub15_opcode_in + end + attribute \module_not_derived 1 + attribute \src "issuer_ls180.v:80049.19-80075.4" + cell \dec31_dec_sub16 \dec31_dec_sub16 + connect \dec31_dec_sub16_asmcode \dec31_dec_sub16_dec31_dec_sub16_asmcode + connect \dec31_dec_sub16_br \dec31_dec_sub16_dec31_dec_sub16_br + connect \dec31_dec_sub16_cr_in \dec31_dec_sub16_dec31_dec_sub16_cr_in + connect \dec31_dec_sub16_cr_out \dec31_dec_sub16_dec31_dec_sub16_cr_out + connect \dec31_dec_sub16_cry_in \dec31_dec_sub16_dec31_dec_sub16_cry_in + connect \dec31_dec_sub16_cry_out \dec31_dec_sub16_dec31_dec_sub16_cry_out + connect \dec31_dec_sub16_form \dec31_dec_sub16_dec31_dec_sub16_form + connect \dec31_dec_sub16_function_unit \dec31_dec_sub16_dec31_dec_sub16_function_unit + connect \dec31_dec_sub16_in1_sel \dec31_dec_sub16_dec31_dec_sub16_in1_sel + connect \dec31_dec_sub16_in2_sel \dec31_dec_sub16_dec31_dec_sub16_in2_sel + connect \dec31_dec_sub16_in3_sel \dec31_dec_sub16_dec31_dec_sub16_in3_sel + connect \dec31_dec_sub16_internal_op \dec31_dec_sub16_dec31_dec_sub16_internal_op + connect \dec31_dec_sub16_inv_a \dec31_dec_sub16_dec31_dec_sub16_inv_a + connect \dec31_dec_sub16_inv_out \dec31_dec_sub16_dec31_dec_sub16_inv_out + connect \dec31_dec_sub16_is_32b \dec31_dec_sub16_dec31_dec_sub16_is_32b + connect \dec31_dec_sub16_ldst_len \dec31_dec_sub16_dec31_dec_sub16_ldst_len + connect \dec31_dec_sub16_lk \dec31_dec_sub16_dec31_dec_sub16_lk + connect \dec31_dec_sub16_out_sel \dec31_dec_sub16_dec31_dec_sub16_out_sel + connect \dec31_dec_sub16_rc_sel \dec31_dec_sub16_dec31_dec_sub16_rc_sel + connect \dec31_dec_sub16_rsrv \dec31_dec_sub16_dec31_dec_sub16_rsrv + connect \dec31_dec_sub16_sgl_pipe \dec31_dec_sub16_dec31_dec_sub16_sgl_pipe + connect \dec31_dec_sub16_sgn \dec31_dec_sub16_dec31_dec_sub16_sgn + connect \dec31_dec_sub16_sgn_ext \dec31_dec_sub16_dec31_dec_sub16_sgn_ext + connect \dec31_dec_sub16_upd \dec31_dec_sub16_dec31_dec_sub16_upd + connect \opcode_in \dec31_dec_sub16_opcode_in + end + attribute \module_not_derived 1 + attribute \src "issuer_ls180.v:80076.19-80102.4" + cell \dec31_dec_sub18 \dec31_dec_sub18 + connect \dec31_dec_sub18_asmcode \dec31_dec_sub18_dec31_dec_sub18_asmcode + connect \dec31_dec_sub18_br \dec31_dec_sub18_dec31_dec_sub18_br + connect \dec31_dec_sub18_cr_in \dec31_dec_sub18_dec31_dec_sub18_cr_in + connect \dec31_dec_sub18_cr_out \dec31_dec_sub18_dec31_dec_sub18_cr_out + connect \dec31_dec_sub18_cry_in \dec31_dec_sub18_dec31_dec_sub18_cry_in + connect \dec31_dec_sub18_cry_out \dec31_dec_sub18_dec31_dec_sub18_cry_out + connect \dec31_dec_sub18_form \dec31_dec_sub18_dec31_dec_sub18_form + connect \dec31_dec_sub18_function_unit \dec31_dec_sub18_dec31_dec_sub18_function_unit + connect \dec31_dec_sub18_in1_sel \dec31_dec_sub18_dec31_dec_sub18_in1_sel + connect \dec31_dec_sub18_in2_sel \dec31_dec_sub18_dec31_dec_sub18_in2_sel + connect \dec31_dec_sub18_in3_sel \dec31_dec_sub18_dec31_dec_sub18_in3_sel + connect \dec31_dec_sub18_internal_op \dec31_dec_sub18_dec31_dec_sub18_internal_op + connect \dec31_dec_sub18_inv_a \dec31_dec_sub18_dec31_dec_sub18_inv_a + connect \dec31_dec_sub18_inv_out \dec31_dec_sub18_dec31_dec_sub18_inv_out + connect \dec31_dec_sub18_is_32b \dec31_dec_sub18_dec31_dec_sub18_is_32b + connect \dec31_dec_sub18_ldst_len \dec31_dec_sub18_dec31_dec_sub18_ldst_len + connect \dec31_dec_sub18_lk \dec31_dec_sub18_dec31_dec_sub18_lk + connect \dec31_dec_sub18_out_sel \dec31_dec_sub18_dec31_dec_sub18_out_sel + connect \dec31_dec_sub18_rc_sel \dec31_dec_sub18_dec31_dec_sub18_rc_sel + connect \dec31_dec_sub18_rsrv \dec31_dec_sub18_dec31_dec_sub18_rsrv + connect \dec31_dec_sub18_sgl_pipe \dec31_dec_sub18_dec31_dec_sub18_sgl_pipe + connect \dec31_dec_sub18_sgn \dec31_dec_sub18_dec31_dec_sub18_sgn + connect \dec31_dec_sub18_sgn_ext \dec31_dec_sub18_dec31_dec_sub18_sgn_ext + connect \dec31_dec_sub18_upd \dec31_dec_sub18_dec31_dec_sub18_upd + connect \opcode_in \dec31_dec_sub18_opcode_in + end + attribute \module_not_derived 1 + attribute \src "issuer_ls180.v:80103.19-80129.4" + cell \dec31_dec_sub19 \dec31_dec_sub19 + connect \dec31_dec_sub19_asmcode \dec31_dec_sub19_dec31_dec_sub19_asmcode + connect \dec31_dec_sub19_br \dec31_dec_sub19_dec31_dec_sub19_br + connect \dec31_dec_sub19_cr_in \dec31_dec_sub19_dec31_dec_sub19_cr_in + connect \dec31_dec_sub19_cr_out \dec31_dec_sub19_dec31_dec_sub19_cr_out + connect \dec31_dec_sub19_cry_in \dec31_dec_sub19_dec31_dec_sub19_cry_in + connect \dec31_dec_sub19_cry_out \dec31_dec_sub19_dec31_dec_sub19_cry_out + connect \dec31_dec_sub19_form \dec31_dec_sub19_dec31_dec_sub19_form + connect \dec31_dec_sub19_function_unit \dec31_dec_sub19_dec31_dec_sub19_function_unit + connect \dec31_dec_sub19_in1_sel \dec31_dec_sub19_dec31_dec_sub19_in1_sel + connect \dec31_dec_sub19_in2_sel \dec31_dec_sub19_dec31_dec_sub19_in2_sel + connect \dec31_dec_sub19_in3_sel \dec31_dec_sub19_dec31_dec_sub19_in3_sel + connect \dec31_dec_sub19_internal_op \dec31_dec_sub19_dec31_dec_sub19_internal_op + connect \dec31_dec_sub19_inv_a \dec31_dec_sub19_dec31_dec_sub19_inv_a + connect \dec31_dec_sub19_inv_out \dec31_dec_sub19_dec31_dec_sub19_inv_out + connect \dec31_dec_sub19_is_32b \dec31_dec_sub19_dec31_dec_sub19_is_32b + connect \dec31_dec_sub19_ldst_len \dec31_dec_sub19_dec31_dec_sub19_ldst_len + connect \dec31_dec_sub19_lk \dec31_dec_sub19_dec31_dec_sub19_lk + connect \dec31_dec_sub19_out_sel \dec31_dec_sub19_dec31_dec_sub19_out_sel + connect \dec31_dec_sub19_rc_sel \dec31_dec_sub19_dec31_dec_sub19_rc_sel + connect \dec31_dec_sub19_rsrv \dec31_dec_sub19_dec31_dec_sub19_rsrv + connect \dec31_dec_sub19_sgl_pipe \dec31_dec_sub19_dec31_dec_sub19_sgl_pipe + connect \dec31_dec_sub19_sgn \dec31_dec_sub19_dec31_dec_sub19_sgn + connect \dec31_dec_sub19_sgn_ext \dec31_dec_sub19_dec31_dec_sub19_sgn_ext + connect \dec31_dec_sub19_upd \dec31_dec_sub19_dec31_dec_sub19_upd + connect \opcode_in \dec31_dec_sub19_opcode_in + end + attribute \module_not_derived 1 + attribute \src "issuer_ls180.v:80130.19-80156.4" + cell \dec31_dec_sub20 \dec31_dec_sub20 + connect \dec31_dec_sub20_asmcode \dec31_dec_sub20_dec31_dec_sub20_asmcode + connect \dec31_dec_sub20_br \dec31_dec_sub20_dec31_dec_sub20_br + connect \dec31_dec_sub20_cr_in \dec31_dec_sub20_dec31_dec_sub20_cr_in + connect \dec31_dec_sub20_cr_out \dec31_dec_sub20_dec31_dec_sub20_cr_out + connect \dec31_dec_sub20_cry_in \dec31_dec_sub20_dec31_dec_sub20_cry_in + connect \dec31_dec_sub20_cry_out \dec31_dec_sub20_dec31_dec_sub20_cry_out + connect \dec31_dec_sub20_form \dec31_dec_sub20_dec31_dec_sub20_form + connect \dec31_dec_sub20_function_unit \dec31_dec_sub20_dec31_dec_sub20_function_unit + connect \dec31_dec_sub20_in1_sel \dec31_dec_sub20_dec31_dec_sub20_in1_sel + connect \dec31_dec_sub20_in2_sel \dec31_dec_sub20_dec31_dec_sub20_in2_sel + connect \dec31_dec_sub20_in3_sel \dec31_dec_sub20_dec31_dec_sub20_in3_sel + connect \dec31_dec_sub20_internal_op \dec31_dec_sub20_dec31_dec_sub20_internal_op + connect \dec31_dec_sub20_inv_a \dec31_dec_sub20_dec31_dec_sub20_inv_a + connect \dec31_dec_sub20_inv_out \dec31_dec_sub20_dec31_dec_sub20_inv_out + connect \dec31_dec_sub20_is_32b \dec31_dec_sub20_dec31_dec_sub20_is_32b + connect \dec31_dec_sub20_ldst_len \dec31_dec_sub20_dec31_dec_sub20_ldst_len + connect \dec31_dec_sub20_lk \dec31_dec_sub20_dec31_dec_sub20_lk + connect \dec31_dec_sub20_out_sel \dec31_dec_sub20_dec31_dec_sub20_out_sel + connect \dec31_dec_sub20_rc_sel \dec31_dec_sub20_dec31_dec_sub20_rc_sel + connect \dec31_dec_sub20_rsrv \dec31_dec_sub20_dec31_dec_sub20_rsrv + connect \dec31_dec_sub20_sgl_pipe \dec31_dec_sub20_dec31_dec_sub20_sgl_pipe + connect \dec31_dec_sub20_sgn \dec31_dec_sub20_dec31_dec_sub20_sgn + connect \dec31_dec_sub20_sgn_ext \dec31_dec_sub20_dec31_dec_sub20_sgn_ext + connect \dec31_dec_sub20_upd \dec31_dec_sub20_dec31_dec_sub20_upd + connect \opcode_in \dec31_dec_sub20_opcode_in + end + attribute \module_not_derived 1 + attribute \src "issuer_ls180.v:80157.19-80183.4" + cell \dec31_dec_sub21 \dec31_dec_sub21 + connect \dec31_dec_sub21_asmcode \dec31_dec_sub21_dec31_dec_sub21_asmcode + connect \dec31_dec_sub21_br \dec31_dec_sub21_dec31_dec_sub21_br + connect \dec31_dec_sub21_cr_in \dec31_dec_sub21_dec31_dec_sub21_cr_in + connect \dec31_dec_sub21_cr_out \dec31_dec_sub21_dec31_dec_sub21_cr_out + connect \dec31_dec_sub21_cry_in \dec31_dec_sub21_dec31_dec_sub21_cry_in + connect \dec31_dec_sub21_cry_out \dec31_dec_sub21_dec31_dec_sub21_cry_out + connect \dec31_dec_sub21_form \dec31_dec_sub21_dec31_dec_sub21_form + connect \dec31_dec_sub21_function_unit \dec31_dec_sub21_dec31_dec_sub21_function_unit + connect \dec31_dec_sub21_in1_sel \dec31_dec_sub21_dec31_dec_sub21_in1_sel + connect \dec31_dec_sub21_in2_sel \dec31_dec_sub21_dec31_dec_sub21_in2_sel + connect \dec31_dec_sub21_in3_sel \dec31_dec_sub21_dec31_dec_sub21_in3_sel + connect \dec31_dec_sub21_internal_op \dec31_dec_sub21_dec31_dec_sub21_internal_op + connect \dec31_dec_sub21_inv_a \dec31_dec_sub21_dec31_dec_sub21_inv_a + connect \dec31_dec_sub21_inv_out \dec31_dec_sub21_dec31_dec_sub21_inv_out + connect \dec31_dec_sub21_is_32b \dec31_dec_sub21_dec31_dec_sub21_is_32b + connect \dec31_dec_sub21_ldst_len \dec31_dec_sub21_dec31_dec_sub21_ldst_len + connect \dec31_dec_sub21_lk \dec31_dec_sub21_dec31_dec_sub21_lk + connect \dec31_dec_sub21_out_sel \dec31_dec_sub21_dec31_dec_sub21_out_sel + connect \dec31_dec_sub21_rc_sel \dec31_dec_sub21_dec31_dec_sub21_rc_sel + connect \dec31_dec_sub21_rsrv \dec31_dec_sub21_dec31_dec_sub21_rsrv + connect \dec31_dec_sub21_sgl_pipe \dec31_dec_sub21_dec31_dec_sub21_sgl_pipe + connect \dec31_dec_sub21_sgn \dec31_dec_sub21_dec31_dec_sub21_sgn + connect \dec31_dec_sub21_sgn_ext \dec31_dec_sub21_dec31_dec_sub21_sgn_ext + connect \dec31_dec_sub21_upd \dec31_dec_sub21_dec31_dec_sub21_upd + connect \opcode_in \dec31_dec_sub21_opcode_in + end + attribute \module_not_derived 1 + attribute \src "issuer_ls180.v:80184.19-80210.4" + cell \dec31_dec_sub22 \dec31_dec_sub22 + connect \dec31_dec_sub22_asmcode \dec31_dec_sub22_dec31_dec_sub22_asmcode + connect \dec31_dec_sub22_br \dec31_dec_sub22_dec31_dec_sub22_br + connect \dec31_dec_sub22_cr_in \dec31_dec_sub22_dec31_dec_sub22_cr_in + connect \dec31_dec_sub22_cr_out \dec31_dec_sub22_dec31_dec_sub22_cr_out + connect \dec31_dec_sub22_cry_in \dec31_dec_sub22_dec31_dec_sub22_cry_in + connect \dec31_dec_sub22_cry_out \dec31_dec_sub22_dec31_dec_sub22_cry_out + connect \dec31_dec_sub22_form \dec31_dec_sub22_dec31_dec_sub22_form + connect \dec31_dec_sub22_function_unit \dec31_dec_sub22_dec31_dec_sub22_function_unit + connect \dec31_dec_sub22_in1_sel \dec31_dec_sub22_dec31_dec_sub22_in1_sel + connect \dec31_dec_sub22_in2_sel \dec31_dec_sub22_dec31_dec_sub22_in2_sel + connect \dec31_dec_sub22_in3_sel \dec31_dec_sub22_dec31_dec_sub22_in3_sel + connect \dec31_dec_sub22_internal_op \dec31_dec_sub22_dec31_dec_sub22_internal_op + connect \dec31_dec_sub22_inv_a \dec31_dec_sub22_dec31_dec_sub22_inv_a + connect \dec31_dec_sub22_inv_out \dec31_dec_sub22_dec31_dec_sub22_inv_out + connect \dec31_dec_sub22_is_32b \dec31_dec_sub22_dec31_dec_sub22_is_32b + connect \dec31_dec_sub22_ldst_len \dec31_dec_sub22_dec31_dec_sub22_ldst_len + connect \dec31_dec_sub22_lk \dec31_dec_sub22_dec31_dec_sub22_lk + connect \dec31_dec_sub22_out_sel \dec31_dec_sub22_dec31_dec_sub22_out_sel + connect \dec31_dec_sub22_rc_sel \dec31_dec_sub22_dec31_dec_sub22_rc_sel + connect \dec31_dec_sub22_rsrv \dec31_dec_sub22_dec31_dec_sub22_rsrv + connect \dec31_dec_sub22_sgl_pipe \dec31_dec_sub22_dec31_dec_sub22_sgl_pipe + connect \dec31_dec_sub22_sgn \dec31_dec_sub22_dec31_dec_sub22_sgn + connect \dec31_dec_sub22_sgn_ext \dec31_dec_sub22_dec31_dec_sub22_sgn_ext + connect \dec31_dec_sub22_upd \dec31_dec_sub22_dec31_dec_sub22_upd + connect \opcode_in \dec31_dec_sub22_opcode_in + end + attribute \module_not_derived 1 + attribute \src "issuer_ls180.v:80211.19-80237.4" + cell \dec31_dec_sub23 \dec31_dec_sub23 + connect \dec31_dec_sub23_asmcode \dec31_dec_sub23_dec31_dec_sub23_asmcode + connect \dec31_dec_sub23_br \dec31_dec_sub23_dec31_dec_sub23_br + connect \dec31_dec_sub23_cr_in \dec31_dec_sub23_dec31_dec_sub23_cr_in + connect \dec31_dec_sub23_cr_out \dec31_dec_sub23_dec31_dec_sub23_cr_out + connect \dec31_dec_sub23_cry_in \dec31_dec_sub23_dec31_dec_sub23_cry_in + connect \dec31_dec_sub23_cry_out \dec31_dec_sub23_dec31_dec_sub23_cry_out + connect \dec31_dec_sub23_form \dec31_dec_sub23_dec31_dec_sub23_form + connect \dec31_dec_sub23_function_unit \dec31_dec_sub23_dec31_dec_sub23_function_unit + connect \dec31_dec_sub23_in1_sel \dec31_dec_sub23_dec31_dec_sub23_in1_sel + connect \dec31_dec_sub23_in2_sel \dec31_dec_sub23_dec31_dec_sub23_in2_sel + connect \dec31_dec_sub23_in3_sel \dec31_dec_sub23_dec31_dec_sub23_in3_sel + connect \dec31_dec_sub23_internal_op \dec31_dec_sub23_dec31_dec_sub23_internal_op + connect \dec31_dec_sub23_inv_a \dec31_dec_sub23_dec31_dec_sub23_inv_a + connect \dec31_dec_sub23_inv_out \dec31_dec_sub23_dec31_dec_sub23_inv_out + connect \dec31_dec_sub23_is_32b \dec31_dec_sub23_dec31_dec_sub23_is_32b + connect \dec31_dec_sub23_ldst_len \dec31_dec_sub23_dec31_dec_sub23_ldst_len + connect \dec31_dec_sub23_lk \dec31_dec_sub23_dec31_dec_sub23_lk + connect \dec31_dec_sub23_out_sel \dec31_dec_sub23_dec31_dec_sub23_out_sel + connect \dec31_dec_sub23_rc_sel \dec31_dec_sub23_dec31_dec_sub23_rc_sel + connect \dec31_dec_sub23_rsrv \dec31_dec_sub23_dec31_dec_sub23_rsrv + connect \dec31_dec_sub23_sgl_pipe \dec31_dec_sub23_dec31_dec_sub23_sgl_pipe + connect \dec31_dec_sub23_sgn \dec31_dec_sub23_dec31_dec_sub23_sgn + connect \dec31_dec_sub23_sgn_ext \dec31_dec_sub23_dec31_dec_sub23_sgn_ext + connect \dec31_dec_sub23_upd \dec31_dec_sub23_dec31_dec_sub23_upd + connect \opcode_in \dec31_dec_sub23_opcode_in + end + attribute \module_not_derived 1 + attribute \src "issuer_ls180.v:80238.19-80264.4" + cell \dec31_dec_sub24 \dec31_dec_sub24 + connect \dec31_dec_sub24_asmcode \dec31_dec_sub24_dec31_dec_sub24_asmcode + connect \dec31_dec_sub24_br \dec31_dec_sub24_dec31_dec_sub24_br + connect \dec31_dec_sub24_cr_in \dec31_dec_sub24_dec31_dec_sub24_cr_in + connect \dec31_dec_sub24_cr_out \dec31_dec_sub24_dec31_dec_sub24_cr_out + connect \dec31_dec_sub24_cry_in \dec31_dec_sub24_dec31_dec_sub24_cry_in + connect \dec31_dec_sub24_cry_out \dec31_dec_sub24_dec31_dec_sub24_cry_out + connect \dec31_dec_sub24_form \dec31_dec_sub24_dec31_dec_sub24_form + connect \dec31_dec_sub24_function_unit \dec31_dec_sub24_dec31_dec_sub24_function_unit + connect \dec31_dec_sub24_in1_sel \dec31_dec_sub24_dec31_dec_sub24_in1_sel + connect \dec31_dec_sub24_in2_sel \dec31_dec_sub24_dec31_dec_sub24_in2_sel + connect \dec31_dec_sub24_in3_sel \dec31_dec_sub24_dec31_dec_sub24_in3_sel + connect \dec31_dec_sub24_internal_op \dec31_dec_sub24_dec31_dec_sub24_internal_op + connect \dec31_dec_sub24_inv_a \dec31_dec_sub24_dec31_dec_sub24_inv_a + connect \dec31_dec_sub24_inv_out \dec31_dec_sub24_dec31_dec_sub24_inv_out + connect \dec31_dec_sub24_is_32b \dec31_dec_sub24_dec31_dec_sub24_is_32b + connect \dec31_dec_sub24_ldst_len \dec31_dec_sub24_dec31_dec_sub24_ldst_len + connect \dec31_dec_sub24_lk \dec31_dec_sub24_dec31_dec_sub24_lk + connect \dec31_dec_sub24_out_sel \dec31_dec_sub24_dec31_dec_sub24_out_sel + connect \dec31_dec_sub24_rc_sel \dec31_dec_sub24_dec31_dec_sub24_rc_sel + connect \dec31_dec_sub24_rsrv \dec31_dec_sub24_dec31_dec_sub24_rsrv + connect \dec31_dec_sub24_sgl_pipe \dec31_dec_sub24_dec31_dec_sub24_sgl_pipe + connect \dec31_dec_sub24_sgn \dec31_dec_sub24_dec31_dec_sub24_sgn + connect \dec31_dec_sub24_sgn_ext \dec31_dec_sub24_dec31_dec_sub24_sgn_ext + connect \dec31_dec_sub24_upd \dec31_dec_sub24_dec31_dec_sub24_upd + connect \opcode_in \dec31_dec_sub24_opcode_in + end + attribute \module_not_derived 1 + attribute \src "issuer_ls180.v:80265.19-80291.4" + cell \dec31_dec_sub26 \dec31_dec_sub26 + connect \dec31_dec_sub26_asmcode \dec31_dec_sub26_dec31_dec_sub26_asmcode + connect \dec31_dec_sub26_br \dec31_dec_sub26_dec31_dec_sub26_br + connect \dec31_dec_sub26_cr_in \dec31_dec_sub26_dec31_dec_sub26_cr_in + connect \dec31_dec_sub26_cr_out \dec31_dec_sub26_dec31_dec_sub26_cr_out + connect \dec31_dec_sub26_cry_in \dec31_dec_sub26_dec31_dec_sub26_cry_in + connect \dec31_dec_sub26_cry_out \dec31_dec_sub26_dec31_dec_sub26_cry_out + connect \dec31_dec_sub26_form \dec31_dec_sub26_dec31_dec_sub26_form + connect \dec31_dec_sub26_function_unit \dec31_dec_sub26_dec31_dec_sub26_function_unit + connect \dec31_dec_sub26_in1_sel \dec31_dec_sub26_dec31_dec_sub26_in1_sel + connect \dec31_dec_sub26_in2_sel \dec31_dec_sub26_dec31_dec_sub26_in2_sel + connect \dec31_dec_sub26_in3_sel \dec31_dec_sub26_dec31_dec_sub26_in3_sel + connect \dec31_dec_sub26_internal_op \dec31_dec_sub26_dec31_dec_sub26_internal_op + connect \dec31_dec_sub26_inv_a \dec31_dec_sub26_dec31_dec_sub26_inv_a + connect \dec31_dec_sub26_inv_out \dec31_dec_sub26_dec31_dec_sub26_inv_out + connect \dec31_dec_sub26_is_32b \dec31_dec_sub26_dec31_dec_sub26_is_32b + connect \dec31_dec_sub26_ldst_len \dec31_dec_sub26_dec31_dec_sub26_ldst_len + connect \dec31_dec_sub26_lk \dec31_dec_sub26_dec31_dec_sub26_lk + connect \dec31_dec_sub26_out_sel \dec31_dec_sub26_dec31_dec_sub26_out_sel + connect \dec31_dec_sub26_rc_sel \dec31_dec_sub26_dec31_dec_sub26_rc_sel + connect \dec31_dec_sub26_rsrv \dec31_dec_sub26_dec31_dec_sub26_rsrv + connect \dec31_dec_sub26_sgl_pipe \dec31_dec_sub26_dec31_dec_sub26_sgl_pipe + connect \dec31_dec_sub26_sgn \dec31_dec_sub26_dec31_dec_sub26_sgn + connect \dec31_dec_sub26_sgn_ext \dec31_dec_sub26_dec31_dec_sub26_sgn_ext + connect \dec31_dec_sub26_upd \dec31_dec_sub26_dec31_dec_sub26_upd + connect \opcode_in \dec31_dec_sub26_opcode_in + end + attribute \module_not_derived 1 + attribute \src "issuer_ls180.v:80292.19-80318.4" + cell \dec31_dec_sub27 \dec31_dec_sub27 + connect \dec31_dec_sub27_asmcode \dec31_dec_sub27_dec31_dec_sub27_asmcode + connect \dec31_dec_sub27_br \dec31_dec_sub27_dec31_dec_sub27_br + connect \dec31_dec_sub27_cr_in \dec31_dec_sub27_dec31_dec_sub27_cr_in + connect \dec31_dec_sub27_cr_out \dec31_dec_sub27_dec31_dec_sub27_cr_out + connect \dec31_dec_sub27_cry_in \dec31_dec_sub27_dec31_dec_sub27_cry_in + connect \dec31_dec_sub27_cry_out \dec31_dec_sub27_dec31_dec_sub27_cry_out + connect \dec31_dec_sub27_form \dec31_dec_sub27_dec31_dec_sub27_form + connect \dec31_dec_sub27_function_unit \dec31_dec_sub27_dec31_dec_sub27_function_unit + connect \dec31_dec_sub27_in1_sel \dec31_dec_sub27_dec31_dec_sub27_in1_sel + connect \dec31_dec_sub27_in2_sel \dec31_dec_sub27_dec31_dec_sub27_in2_sel + connect \dec31_dec_sub27_in3_sel \dec31_dec_sub27_dec31_dec_sub27_in3_sel + connect \dec31_dec_sub27_internal_op \dec31_dec_sub27_dec31_dec_sub27_internal_op + connect \dec31_dec_sub27_inv_a \dec31_dec_sub27_dec31_dec_sub27_inv_a + connect \dec31_dec_sub27_inv_out \dec31_dec_sub27_dec31_dec_sub27_inv_out + connect \dec31_dec_sub27_is_32b \dec31_dec_sub27_dec31_dec_sub27_is_32b + connect \dec31_dec_sub27_ldst_len \dec31_dec_sub27_dec31_dec_sub27_ldst_len + connect \dec31_dec_sub27_lk \dec31_dec_sub27_dec31_dec_sub27_lk + connect \dec31_dec_sub27_out_sel \dec31_dec_sub27_dec31_dec_sub27_out_sel + connect \dec31_dec_sub27_rc_sel \dec31_dec_sub27_dec31_dec_sub27_rc_sel + connect \dec31_dec_sub27_rsrv \dec31_dec_sub27_dec31_dec_sub27_rsrv + connect \dec31_dec_sub27_sgl_pipe \dec31_dec_sub27_dec31_dec_sub27_sgl_pipe + connect \dec31_dec_sub27_sgn \dec31_dec_sub27_dec31_dec_sub27_sgn + connect \dec31_dec_sub27_sgn_ext \dec31_dec_sub27_dec31_dec_sub27_sgn_ext + connect \dec31_dec_sub27_upd \dec31_dec_sub27_dec31_dec_sub27_upd + connect \opcode_in \dec31_dec_sub27_opcode_in + end + attribute \module_not_derived 1 + attribute \src "issuer_ls180.v:80319.19-80345.4" + cell \dec31_dec_sub28 \dec31_dec_sub28 + connect \dec31_dec_sub28_asmcode \dec31_dec_sub28_dec31_dec_sub28_asmcode + connect \dec31_dec_sub28_br \dec31_dec_sub28_dec31_dec_sub28_br + connect \dec31_dec_sub28_cr_in \dec31_dec_sub28_dec31_dec_sub28_cr_in + connect \dec31_dec_sub28_cr_out \dec31_dec_sub28_dec31_dec_sub28_cr_out + connect \dec31_dec_sub28_cry_in \dec31_dec_sub28_dec31_dec_sub28_cry_in + connect \dec31_dec_sub28_cry_out \dec31_dec_sub28_dec31_dec_sub28_cry_out + connect \dec31_dec_sub28_form \dec31_dec_sub28_dec31_dec_sub28_form + connect \dec31_dec_sub28_function_unit \dec31_dec_sub28_dec31_dec_sub28_function_unit + connect \dec31_dec_sub28_in1_sel \dec31_dec_sub28_dec31_dec_sub28_in1_sel + connect \dec31_dec_sub28_in2_sel \dec31_dec_sub28_dec31_dec_sub28_in2_sel + connect \dec31_dec_sub28_in3_sel \dec31_dec_sub28_dec31_dec_sub28_in3_sel + connect \dec31_dec_sub28_internal_op \dec31_dec_sub28_dec31_dec_sub28_internal_op + connect \dec31_dec_sub28_inv_a \dec31_dec_sub28_dec31_dec_sub28_inv_a + connect \dec31_dec_sub28_inv_out \dec31_dec_sub28_dec31_dec_sub28_inv_out + connect \dec31_dec_sub28_is_32b \dec31_dec_sub28_dec31_dec_sub28_is_32b + connect \dec31_dec_sub28_ldst_len \dec31_dec_sub28_dec31_dec_sub28_ldst_len + connect \dec31_dec_sub28_lk \dec31_dec_sub28_dec31_dec_sub28_lk + connect \dec31_dec_sub28_out_sel \dec31_dec_sub28_dec31_dec_sub28_out_sel + connect \dec31_dec_sub28_rc_sel \dec31_dec_sub28_dec31_dec_sub28_rc_sel + connect \dec31_dec_sub28_rsrv \dec31_dec_sub28_dec31_dec_sub28_rsrv + connect \dec31_dec_sub28_sgl_pipe \dec31_dec_sub28_dec31_dec_sub28_sgl_pipe + connect \dec31_dec_sub28_sgn \dec31_dec_sub28_dec31_dec_sub28_sgn + connect \dec31_dec_sub28_sgn_ext \dec31_dec_sub28_dec31_dec_sub28_sgn_ext + connect \dec31_dec_sub28_upd \dec31_dec_sub28_dec31_dec_sub28_upd + connect \opcode_in \dec31_dec_sub28_opcode_in + end + attribute \module_not_derived 1 + attribute \src "issuer_ls180.v:80346.18-80372.4" + cell \dec31_dec_sub4 \dec31_dec_sub4 + connect \dec31_dec_sub4_asmcode \dec31_dec_sub4_dec31_dec_sub4_asmcode + connect \dec31_dec_sub4_br \dec31_dec_sub4_dec31_dec_sub4_br + connect \dec31_dec_sub4_cr_in \dec31_dec_sub4_dec31_dec_sub4_cr_in + connect \dec31_dec_sub4_cr_out \dec31_dec_sub4_dec31_dec_sub4_cr_out + connect \dec31_dec_sub4_cry_in \dec31_dec_sub4_dec31_dec_sub4_cry_in + connect \dec31_dec_sub4_cry_out \dec31_dec_sub4_dec31_dec_sub4_cry_out + connect \dec31_dec_sub4_form \dec31_dec_sub4_dec31_dec_sub4_form + connect \dec31_dec_sub4_function_unit \dec31_dec_sub4_dec31_dec_sub4_function_unit + connect \dec31_dec_sub4_in1_sel \dec31_dec_sub4_dec31_dec_sub4_in1_sel + connect \dec31_dec_sub4_in2_sel \dec31_dec_sub4_dec31_dec_sub4_in2_sel + connect \dec31_dec_sub4_in3_sel \dec31_dec_sub4_dec31_dec_sub4_in3_sel + connect \dec31_dec_sub4_internal_op \dec31_dec_sub4_dec31_dec_sub4_internal_op + connect \dec31_dec_sub4_inv_a \dec31_dec_sub4_dec31_dec_sub4_inv_a + connect \dec31_dec_sub4_inv_out \dec31_dec_sub4_dec31_dec_sub4_inv_out + connect \dec31_dec_sub4_is_32b \dec31_dec_sub4_dec31_dec_sub4_is_32b + connect \dec31_dec_sub4_ldst_len \dec31_dec_sub4_dec31_dec_sub4_ldst_len + connect \dec31_dec_sub4_lk \dec31_dec_sub4_dec31_dec_sub4_lk + connect \dec31_dec_sub4_out_sel \dec31_dec_sub4_dec31_dec_sub4_out_sel + connect \dec31_dec_sub4_rc_sel \dec31_dec_sub4_dec31_dec_sub4_rc_sel + connect \dec31_dec_sub4_rsrv \dec31_dec_sub4_dec31_dec_sub4_rsrv + connect \dec31_dec_sub4_sgl_pipe \dec31_dec_sub4_dec31_dec_sub4_sgl_pipe + connect \dec31_dec_sub4_sgn \dec31_dec_sub4_dec31_dec_sub4_sgn + connect \dec31_dec_sub4_sgn_ext \dec31_dec_sub4_dec31_dec_sub4_sgn_ext + connect \dec31_dec_sub4_upd \dec31_dec_sub4_dec31_dec_sub4_upd + connect \opcode_in \dec31_dec_sub4_opcode_in + end + attribute \module_not_derived 1 + attribute \src "issuer_ls180.v:80373.18-80399.4" + cell \dec31_dec_sub8 \dec31_dec_sub8 + connect \dec31_dec_sub8_asmcode \dec31_dec_sub8_dec31_dec_sub8_asmcode + connect \dec31_dec_sub8_br \dec31_dec_sub8_dec31_dec_sub8_br + connect \dec31_dec_sub8_cr_in \dec31_dec_sub8_dec31_dec_sub8_cr_in + connect \dec31_dec_sub8_cr_out \dec31_dec_sub8_dec31_dec_sub8_cr_out + connect \dec31_dec_sub8_cry_in \dec31_dec_sub8_dec31_dec_sub8_cry_in + connect \dec31_dec_sub8_cry_out \dec31_dec_sub8_dec31_dec_sub8_cry_out + connect \dec31_dec_sub8_form \dec31_dec_sub8_dec31_dec_sub8_form + connect \dec31_dec_sub8_function_unit \dec31_dec_sub8_dec31_dec_sub8_function_unit + connect \dec31_dec_sub8_in1_sel \dec31_dec_sub8_dec31_dec_sub8_in1_sel + connect \dec31_dec_sub8_in2_sel \dec31_dec_sub8_dec31_dec_sub8_in2_sel + connect \dec31_dec_sub8_in3_sel \dec31_dec_sub8_dec31_dec_sub8_in3_sel + connect \dec31_dec_sub8_internal_op \dec31_dec_sub8_dec31_dec_sub8_internal_op + connect \dec31_dec_sub8_inv_a \dec31_dec_sub8_dec31_dec_sub8_inv_a + connect \dec31_dec_sub8_inv_out \dec31_dec_sub8_dec31_dec_sub8_inv_out + connect \dec31_dec_sub8_is_32b \dec31_dec_sub8_dec31_dec_sub8_is_32b + connect \dec31_dec_sub8_ldst_len \dec31_dec_sub8_dec31_dec_sub8_ldst_len + connect \dec31_dec_sub8_lk \dec31_dec_sub8_dec31_dec_sub8_lk + connect \dec31_dec_sub8_out_sel \dec31_dec_sub8_dec31_dec_sub8_out_sel + connect \dec31_dec_sub8_rc_sel \dec31_dec_sub8_dec31_dec_sub8_rc_sel + connect \dec31_dec_sub8_rsrv \dec31_dec_sub8_dec31_dec_sub8_rsrv + connect \dec31_dec_sub8_sgl_pipe \dec31_dec_sub8_dec31_dec_sub8_sgl_pipe + connect \dec31_dec_sub8_sgn \dec31_dec_sub8_dec31_dec_sub8_sgn + connect \dec31_dec_sub8_sgn_ext \dec31_dec_sub8_dec31_dec_sub8_sgn_ext + connect \dec31_dec_sub8_upd \dec31_dec_sub8_dec31_dec_sub8_upd + connect \opcode_in \dec31_dec_sub8_opcode_in + end + attribute \module_not_derived 1 + attribute \src "issuer_ls180.v:80400.18-80426.4" + cell \dec31_dec_sub9 \dec31_dec_sub9 + connect \dec31_dec_sub9_asmcode \dec31_dec_sub9_dec31_dec_sub9_asmcode + connect \dec31_dec_sub9_br \dec31_dec_sub9_dec31_dec_sub9_br + connect \dec31_dec_sub9_cr_in \dec31_dec_sub9_dec31_dec_sub9_cr_in + connect \dec31_dec_sub9_cr_out \dec31_dec_sub9_dec31_dec_sub9_cr_out + connect \dec31_dec_sub9_cry_in \dec31_dec_sub9_dec31_dec_sub9_cry_in + connect \dec31_dec_sub9_cry_out \dec31_dec_sub9_dec31_dec_sub9_cry_out + connect \dec31_dec_sub9_form \dec31_dec_sub9_dec31_dec_sub9_form + connect \dec31_dec_sub9_function_unit \dec31_dec_sub9_dec31_dec_sub9_function_unit + connect \dec31_dec_sub9_in1_sel \dec31_dec_sub9_dec31_dec_sub9_in1_sel + connect \dec31_dec_sub9_in2_sel \dec31_dec_sub9_dec31_dec_sub9_in2_sel + connect \dec31_dec_sub9_in3_sel \dec31_dec_sub9_dec31_dec_sub9_in3_sel + connect \dec31_dec_sub9_internal_op \dec31_dec_sub9_dec31_dec_sub9_internal_op + connect \dec31_dec_sub9_inv_a \dec31_dec_sub9_dec31_dec_sub9_inv_a + connect \dec31_dec_sub9_inv_out \dec31_dec_sub9_dec31_dec_sub9_inv_out + connect \dec31_dec_sub9_is_32b \dec31_dec_sub9_dec31_dec_sub9_is_32b + connect \dec31_dec_sub9_ldst_len \dec31_dec_sub9_dec31_dec_sub9_ldst_len + connect \dec31_dec_sub9_lk \dec31_dec_sub9_dec31_dec_sub9_lk + connect \dec31_dec_sub9_out_sel \dec31_dec_sub9_dec31_dec_sub9_out_sel + connect \dec31_dec_sub9_rc_sel \dec31_dec_sub9_dec31_dec_sub9_rc_sel + connect \dec31_dec_sub9_rsrv \dec31_dec_sub9_dec31_dec_sub9_rsrv + connect \dec31_dec_sub9_sgl_pipe \dec31_dec_sub9_dec31_dec_sub9_sgl_pipe + connect \dec31_dec_sub9_sgn \dec31_dec_sub9_dec31_dec_sub9_sgn + connect \dec31_dec_sub9_sgn_ext \dec31_dec_sub9_dec31_dec_sub9_sgn_ext + connect \dec31_dec_sub9_upd \dec31_dec_sub9_dec31_dec_sub9_upd + connect \opcode_in \dec31_dec_sub9_opcode_in + end + attribute \src "issuer_ls180.v:75542.7-75542.20" + process $proc$issuer_ls180.v:75542$3595 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "issuer_ls180.v:80427.3-80487.6" + process $proc$issuer_ls180.v:80427$3571 + assign { } { } + assign { } { } + assign $0\dec31_function_unit[11:0] $1\dec31_function_unit[11:0] + attribute \src "issuer_ls180.v:80428.5-80428.29" + switch \initial + attribute \src "issuer_ls180.v:80428.9-80428.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opc_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_function_unit[11:0] \dec31_dec_sub10_dec31_dec_sub10_function_unit + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_function_unit[11:0] \dec31_dec_sub28_dec31_dec_sub28_function_unit + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_function_unit[11:0] \dec31_dec_sub0_dec31_dec_sub0_function_unit + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_function_unit[11:0] \dec31_dec_sub26_dec31_dec_sub26_function_unit + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_function_unit[11:0] \dec31_dec_sub19_dec31_dec_sub19_function_unit + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_function_unit[11:0] \dec31_dec_sub22_dec31_dec_sub22_function_unit + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_function_unit[11:0] \dec31_dec_sub9_dec31_dec_sub9_function_unit + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_function_unit[11:0] \dec31_dec_sub11_dec31_dec_sub11_function_unit + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_function_unit[11:0] \dec31_dec_sub27_dec31_dec_sub27_function_unit + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_function_unit[11:0] \dec31_dec_sub15_dec31_dec_sub15_function_unit + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_function_unit[11:0] \dec31_dec_sub20_dec31_dec_sub20_function_unit + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_function_unit[11:0] \dec31_dec_sub21_dec31_dec_sub21_function_unit + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_function_unit[11:0] \dec31_dec_sub23_dec31_dec_sub23_function_unit + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_function_unit[11:0] \dec31_dec_sub16_dec31_dec_sub16_function_unit + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_function_unit[11:0] \dec31_dec_sub18_dec31_dec_sub18_function_unit + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_function_unit[11:0] \dec31_dec_sub8_dec31_dec_sub8_function_unit + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_function_unit[11:0] \dec31_dec_sub24_dec31_dec_sub24_function_unit + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_function_unit[11:0] \dec31_dec_sub4_dec31_dec_sub4_function_unit + case + assign $1\dec31_function_unit[11:0] 12'000000000000 + end + sync always + update \dec31_function_unit $0\dec31_function_unit[11:0] + end + attribute \src "issuer_ls180.v:80488.3-80548.6" + process $proc$issuer_ls180.v:80488$3572 + assign { } { } + assign { } { } + assign $0\dec31_internal_op[6:0] $1\dec31_internal_op[6:0] + attribute \src "issuer_ls180.v:80489.5-80489.29" + switch \initial + attribute \src "issuer_ls180.v:80489.9-80489.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opc_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_internal_op[6:0] \dec31_dec_sub10_dec31_dec_sub10_internal_op + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_internal_op[6:0] \dec31_dec_sub28_dec31_dec_sub28_internal_op + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_internal_op[6:0] \dec31_dec_sub0_dec31_dec_sub0_internal_op + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_internal_op[6:0] \dec31_dec_sub26_dec31_dec_sub26_internal_op + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_internal_op[6:0] \dec31_dec_sub19_dec31_dec_sub19_internal_op + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_internal_op[6:0] \dec31_dec_sub22_dec31_dec_sub22_internal_op + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_internal_op[6:0] \dec31_dec_sub9_dec31_dec_sub9_internal_op + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_internal_op[6:0] \dec31_dec_sub11_dec31_dec_sub11_internal_op + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_internal_op[6:0] \dec31_dec_sub27_dec31_dec_sub27_internal_op + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_internal_op[6:0] \dec31_dec_sub15_dec31_dec_sub15_internal_op + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_internal_op[6:0] \dec31_dec_sub20_dec31_dec_sub20_internal_op + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_internal_op[6:0] \dec31_dec_sub21_dec31_dec_sub21_internal_op + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_internal_op[6:0] \dec31_dec_sub23_dec31_dec_sub23_internal_op + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_internal_op[6:0] \dec31_dec_sub16_dec31_dec_sub16_internal_op + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_internal_op[6:0] \dec31_dec_sub18_dec31_dec_sub18_internal_op + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_internal_op[6:0] \dec31_dec_sub8_dec31_dec_sub8_internal_op + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_internal_op[6:0] \dec31_dec_sub24_dec31_dec_sub24_internal_op + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_internal_op[6:0] \dec31_dec_sub4_dec31_dec_sub4_internal_op + case + assign $1\dec31_internal_op[6:0] 7'0000000 + end + sync always + update \dec31_internal_op $0\dec31_internal_op[6:0] + end + attribute \src "issuer_ls180.v:80549.3-80609.6" + process $proc$issuer_ls180.v:80549$3573 + assign { } { } + assign { } { } + assign $0\dec31_form[4:0] $1\dec31_form[4:0] + attribute \src "issuer_ls180.v:80550.5-80550.29" + switch \initial + attribute \src "issuer_ls180.v:80550.9-80550.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opc_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_form[4:0] \dec31_dec_sub10_dec31_dec_sub10_form + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_form[4:0] \dec31_dec_sub28_dec31_dec_sub28_form + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_form[4:0] \dec31_dec_sub0_dec31_dec_sub0_form + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_form[4:0] \dec31_dec_sub26_dec31_dec_sub26_form + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_form[4:0] \dec31_dec_sub19_dec31_dec_sub19_form + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_form[4:0] \dec31_dec_sub22_dec31_dec_sub22_form + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_form[4:0] \dec31_dec_sub9_dec31_dec_sub9_form + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_form[4:0] \dec31_dec_sub11_dec31_dec_sub11_form + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_form[4:0] \dec31_dec_sub27_dec31_dec_sub27_form + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_form[4:0] \dec31_dec_sub15_dec31_dec_sub15_form + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_form[4:0] \dec31_dec_sub20_dec31_dec_sub20_form + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_form[4:0] \dec31_dec_sub21_dec31_dec_sub21_form + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_form[4:0] \dec31_dec_sub23_dec31_dec_sub23_form + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_form[4:0] \dec31_dec_sub16_dec31_dec_sub16_form + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_form[4:0] \dec31_dec_sub18_dec31_dec_sub18_form + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_form[4:0] \dec31_dec_sub8_dec31_dec_sub8_form + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_form[4:0] \dec31_dec_sub24_dec31_dec_sub24_form + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_form[4:0] \dec31_dec_sub4_dec31_dec_sub4_form + case + assign $1\dec31_form[4:0] 5'00000 + end + sync always + update \dec31_form $0\dec31_form[4:0] + end + attribute \src "issuer_ls180.v:80610.3-80670.6" + process $proc$issuer_ls180.v:80610$3574 + assign { } { } + assign { } { } + assign $0\dec31_asmcode[7:0] $1\dec31_asmcode[7:0] + attribute \src "issuer_ls180.v:80611.5-80611.29" + switch \initial + attribute \src "issuer_ls180.v:80611.9-80611.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opc_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_asmcode[7:0] \dec31_dec_sub10_dec31_dec_sub10_asmcode + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_asmcode[7:0] \dec31_dec_sub28_dec31_dec_sub28_asmcode + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_asmcode[7:0] \dec31_dec_sub0_dec31_dec_sub0_asmcode + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_asmcode[7:0] \dec31_dec_sub26_dec31_dec_sub26_asmcode + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_asmcode[7:0] \dec31_dec_sub19_dec31_dec_sub19_asmcode + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_asmcode[7:0] \dec31_dec_sub22_dec31_dec_sub22_asmcode + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_asmcode[7:0] \dec31_dec_sub9_dec31_dec_sub9_asmcode + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_asmcode[7:0] \dec31_dec_sub11_dec31_dec_sub11_asmcode + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_asmcode[7:0] \dec31_dec_sub27_dec31_dec_sub27_asmcode + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_asmcode[7:0] \dec31_dec_sub15_dec31_dec_sub15_asmcode + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_asmcode[7:0] \dec31_dec_sub20_dec31_dec_sub20_asmcode + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_asmcode[7:0] \dec31_dec_sub21_dec31_dec_sub21_asmcode + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_asmcode[7:0] \dec31_dec_sub23_dec31_dec_sub23_asmcode + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_asmcode[7:0] \dec31_dec_sub16_dec31_dec_sub16_asmcode + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_asmcode[7:0] \dec31_dec_sub18_dec31_dec_sub18_asmcode + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_asmcode[7:0] \dec31_dec_sub8_dec31_dec_sub8_asmcode + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_asmcode[7:0] \dec31_dec_sub24_dec31_dec_sub24_asmcode + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_asmcode[7:0] \dec31_dec_sub4_dec31_dec_sub4_asmcode + case + assign $1\dec31_asmcode[7:0] 8'00000000 + end + sync always + update \dec31_asmcode $0\dec31_asmcode[7:0] + end + attribute \src "issuer_ls180.v:80671.3-80731.6" + process $proc$issuer_ls180.v:80671$3575 + assign { } { } + assign { } { } + assign $0\dec31_in1_sel[2:0] $1\dec31_in1_sel[2:0] + attribute \src "issuer_ls180.v:80672.5-80672.29" + switch \initial + attribute \src "issuer_ls180.v:80672.9-80672.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opc_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_in1_sel[2:0] \dec31_dec_sub10_dec31_dec_sub10_in1_sel + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_in1_sel[2:0] \dec31_dec_sub28_dec31_dec_sub28_in1_sel + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_in1_sel[2:0] \dec31_dec_sub0_dec31_dec_sub0_in1_sel + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_in1_sel[2:0] \dec31_dec_sub26_dec31_dec_sub26_in1_sel + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_in1_sel[2:0] \dec31_dec_sub19_dec31_dec_sub19_in1_sel + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_in1_sel[2:0] \dec31_dec_sub22_dec31_dec_sub22_in1_sel + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_in1_sel[2:0] \dec31_dec_sub9_dec31_dec_sub9_in1_sel + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_in1_sel[2:0] \dec31_dec_sub11_dec31_dec_sub11_in1_sel + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_in1_sel[2:0] \dec31_dec_sub27_dec31_dec_sub27_in1_sel + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_in1_sel[2:0] \dec31_dec_sub15_dec31_dec_sub15_in1_sel + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_in1_sel[2:0] \dec31_dec_sub20_dec31_dec_sub20_in1_sel + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_in1_sel[2:0] \dec31_dec_sub21_dec31_dec_sub21_in1_sel + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_in1_sel[2:0] \dec31_dec_sub23_dec31_dec_sub23_in1_sel + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_in1_sel[2:0] \dec31_dec_sub16_dec31_dec_sub16_in1_sel + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_in1_sel[2:0] \dec31_dec_sub18_dec31_dec_sub18_in1_sel + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_in1_sel[2:0] \dec31_dec_sub8_dec31_dec_sub8_in1_sel + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_in1_sel[2:0] \dec31_dec_sub24_dec31_dec_sub24_in1_sel + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_in1_sel[2:0] \dec31_dec_sub4_dec31_dec_sub4_in1_sel + case + assign $1\dec31_in1_sel[2:0] 3'000 + end + sync always + update \dec31_in1_sel $0\dec31_in1_sel[2:0] + end + attribute \src "issuer_ls180.v:80732.3-80792.6" + process $proc$issuer_ls180.v:80732$3576 + assign { } { } + assign { } { } + assign $0\dec31_in2_sel[3:0] $1\dec31_in2_sel[3:0] + attribute \src "issuer_ls180.v:80733.5-80733.29" + switch \initial + attribute \src "issuer_ls180.v:80733.9-80733.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opc_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_in2_sel[3:0] \dec31_dec_sub10_dec31_dec_sub10_in2_sel + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_in2_sel[3:0] \dec31_dec_sub28_dec31_dec_sub28_in2_sel + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_in2_sel[3:0] \dec31_dec_sub0_dec31_dec_sub0_in2_sel + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_in2_sel[3:0] \dec31_dec_sub26_dec31_dec_sub26_in2_sel + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_in2_sel[3:0] \dec31_dec_sub19_dec31_dec_sub19_in2_sel + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_in2_sel[3:0] \dec31_dec_sub22_dec31_dec_sub22_in2_sel + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_in2_sel[3:0] \dec31_dec_sub9_dec31_dec_sub9_in2_sel + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_in2_sel[3:0] \dec31_dec_sub11_dec31_dec_sub11_in2_sel + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_in2_sel[3:0] \dec31_dec_sub27_dec31_dec_sub27_in2_sel + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_in2_sel[3:0] \dec31_dec_sub15_dec31_dec_sub15_in2_sel + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_in2_sel[3:0] \dec31_dec_sub20_dec31_dec_sub20_in2_sel + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_in2_sel[3:0] \dec31_dec_sub21_dec31_dec_sub21_in2_sel + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_in2_sel[3:0] \dec31_dec_sub23_dec31_dec_sub23_in2_sel + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_in2_sel[3:0] \dec31_dec_sub16_dec31_dec_sub16_in2_sel + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_in2_sel[3:0] \dec31_dec_sub18_dec31_dec_sub18_in2_sel + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_in2_sel[3:0] \dec31_dec_sub8_dec31_dec_sub8_in2_sel + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_in2_sel[3:0] \dec31_dec_sub24_dec31_dec_sub24_in2_sel + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_in2_sel[3:0] \dec31_dec_sub4_dec31_dec_sub4_in2_sel + case + assign $1\dec31_in2_sel[3:0] 4'0000 + end + sync always + update \dec31_in2_sel $0\dec31_in2_sel[3:0] + end + attribute \src "issuer_ls180.v:80793.3-80853.6" + process $proc$issuer_ls180.v:80793$3577 + assign { } { } + assign { } { } + assign $0\dec31_in3_sel[1:0] $1\dec31_in3_sel[1:0] + attribute \src "issuer_ls180.v:80794.5-80794.29" + switch \initial + attribute \src "issuer_ls180.v:80794.9-80794.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opc_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_in3_sel[1:0] \dec31_dec_sub10_dec31_dec_sub10_in3_sel + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_in3_sel[1:0] \dec31_dec_sub28_dec31_dec_sub28_in3_sel + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_in3_sel[1:0] \dec31_dec_sub0_dec31_dec_sub0_in3_sel + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_in3_sel[1:0] \dec31_dec_sub26_dec31_dec_sub26_in3_sel + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_in3_sel[1:0] \dec31_dec_sub19_dec31_dec_sub19_in3_sel + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_in3_sel[1:0] \dec31_dec_sub22_dec31_dec_sub22_in3_sel + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_in3_sel[1:0] \dec31_dec_sub9_dec31_dec_sub9_in3_sel + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_in3_sel[1:0] \dec31_dec_sub11_dec31_dec_sub11_in3_sel + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_in3_sel[1:0] \dec31_dec_sub27_dec31_dec_sub27_in3_sel + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_in3_sel[1:0] \dec31_dec_sub15_dec31_dec_sub15_in3_sel + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_in3_sel[1:0] \dec31_dec_sub20_dec31_dec_sub20_in3_sel + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_in3_sel[1:0] \dec31_dec_sub21_dec31_dec_sub21_in3_sel + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_in3_sel[1:0] \dec31_dec_sub23_dec31_dec_sub23_in3_sel + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_in3_sel[1:0] \dec31_dec_sub16_dec31_dec_sub16_in3_sel + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_in3_sel[1:0] \dec31_dec_sub18_dec31_dec_sub18_in3_sel + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_in3_sel[1:0] \dec31_dec_sub8_dec31_dec_sub8_in3_sel + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_in3_sel[1:0] \dec31_dec_sub24_dec31_dec_sub24_in3_sel + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_in3_sel[1:0] \dec31_dec_sub4_dec31_dec_sub4_in3_sel + case + assign $1\dec31_in3_sel[1:0] 2'00 + end + sync always + update \dec31_in3_sel $0\dec31_in3_sel[1:0] + end + attribute \src "issuer_ls180.v:80854.3-80914.6" + process $proc$issuer_ls180.v:80854$3578 + assign { } { } + assign { } { } + assign $0\dec31_out_sel[1:0] $1\dec31_out_sel[1:0] + attribute \src "issuer_ls180.v:80855.5-80855.29" + switch \initial + attribute \src "issuer_ls180.v:80855.9-80855.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opc_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_out_sel[1:0] \dec31_dec_sub10_dec31_dec_sub10_out_sel + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_out_sel[1:0] \dec31_dec_sub28_dec31_dec_sub28_out_sel + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_out_sel[1:0] \dec31_dec_sub0_dec31_dec_sub0_out_sel + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_out_sel[1:0] \dec31_dec_sub26_dec31_dec_sub26_out_sel + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_out_sel[1:0] \dec31_dec_sub19_dec31_dec_sub19_out_sel + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_out_sel[1:0] \dec31_dec_sub22_dec31_dec_sub22_out_sel + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_out_sel[1:0] \dec31_dec_sub9_dec31_dec_sub9_out_sel + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_out_sel[1:0] \dec31_dec_sub11_dec31_dec_sub11_out_sel + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_out_sel[1:0] \dec31_dec_sub27_dec31_dec_sub27_out_sel + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_out_sel[1:0] \dec31_dec_sub15_dec31_dec_sub15_out_sel + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_out_sel[1:0] \dec31_dec_sub20_dec31_dec_sub20_out_sel + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_out_sel[1:0] \dec31_dec_sub21_dec31_dec_sub21_out_sel + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_out_sel[1:0] \dec31_dec_sub23_dec31_dec_sub23_out_sel + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_out_sel[1:0] \dec31_dec_sub16_dec31_dec_sub16_out_sel + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_out_sel[1:0] \dec31_dec_sub18_dec31_dec_sub18_out_sel + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_out_sel[1:0] \dec31_dec_sub8_dec31_dec_sub8_out_sel + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_out_sel[1:0] \dec31_dec_sub24_dec31_dec_sub24_out_sel + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_out_sel[1:0] \dec31_dec_sub4_dec31_dec_sub4_out_sel + case + assign $1\dec31_out_sel[1:0] 2'00 + end + sync always + update \dec31_out_sel $0\dec31_out_sel[1:0] + end + attribute \src "issuer_ls180.v:80915.3-80975.6" + process $proc$issuer_ls180.v:80915$3579 + assign { } { } + assign { } { } + assign $0\dec31_cr_in[2:0] $1\dec31_cr_in[2:0] + attribute \src "issuer_ls180.v:80916.5-80916.29" + switch \initial + attribute \src "issuer_ls180.v:80916.9-80916.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opc_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_cr_in[2:0] \dec31_dec_sub10_dec31_dec_sub10_cr_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_cr_in[2:0] \dec31_dec_sub28_dec31_dec_sub28_cr_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_cr_in[2:0] \dec31_dec_sub0_dec31_dec_sub0_cr_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_cr_in[2:0] \dec31_dec_sub26_dec31_dec_sub26_cr_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_cr_in[2:0] \dec31_dec_sub19_dec31_dec_sub19_cr_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_cr_in[2:0] \dec31_dec_sub22_dec31_dec_sub22_cr_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_cr_in[2:0] \dec31_dec_sub9_dec31_dec_sub9_cr_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_cr_in[2:0] \dec31_dec_sub11_dec31_dec_sub11_cr_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_cr_in[2:0] \dec31_dec_sub27_dec31_dec_sub27_cr_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_cr_in[2:0] \dec31_dec_sub15_dec31_dec_sub15_cr_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_cr_in[2:0] \dec31_dec_sub20_dec31_dec_sub20_cr_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_cr_in[2:0] \dec31_dec_sub21_dec31_dec_sub21_cr_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_cr_in[2:0] \dec31_dec_sub23_dec31_dec_sub23_cr_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_cr_in[2:0] \dec31_dec_sub16_dec31_dec_sub16_cr_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_cr_in[2:0] \dec31_dec_sub18_dec31_dec_sub18_cr_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_cr_in[2:0] \dec31_dec_sub8_dec31_dec_sub8_cr_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_cr_in[2:0] \dec31_dec_sub24_dec31_dec_sub24_cr_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_cr_in[2:0] \dec31_dec_sub4_dec31_dec_sub4_cr_in + case + assign $1\dec31_cr_in[2:0] 3'000 + end + sync always + update \dec31_cr_in $0\dec31_cr_in[2:0] + end + attribute \src "issuer_ls180.v:80976.3-81036.6" + process $proc$issuer_ls180.v:80976$3580 + assign { } { } + assign { } { } + assign $0\dec31_cr_out[2:0] $1\dec31_cr_out[2:0] + attribute \src "issuer_ls180.v:80977.5-80977.29" + switch \initial + attribute \src "issuer_ls180.v:80977.9-80977.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opc_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_cr_out[2:0] \dec31_dec_sub10_dec31_dec_sub10_cr_out + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_cr_out[2:0] \dec31_dec_sub28_dec31_dec_sub28_cr_out + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_cr_out[2:0] \dec31_dec_sub0_dec31_dec_sub0_cr_out + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_cr_out[2:0] \dec31_dec_sub26_dec31_dec_sub26_cr_out + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_cr_out[2:0] \dec31_dec_sub19_dec31_dec_sub19_cr_out + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_cr_out[2:0] \dec31_dec_sub22_dec31_dec_sub22_cr_out + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_cr_out[2:0] \dec31_dec_sub9_dec31_dec_sub9_cr_out + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_cr_out[2:0] \dec31_dec_sub11_dec31_dec_sub11_cr_out + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_cr_out[2:0] \dec31_dec_sub27_dec31_dec_sub27_cr_out + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_cr_out[2:0] \dec31_dec_sub15_dec31_dec_sub15_cr_out + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_cr_out[2:0] \dec31_dec_sub20_dec31_dec_sub20_cr_out + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_cr_out[2:0] \dec31_dec_sub21_dec31_dec_sub21_cr_out + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_cr_out[2:0] \dec31_dec_sub23_dec31_dec_sub23_cr_out + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_cr_out[2:0] \dec31_dec_sub16_dec31_dec_sub16_cr_out + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_cr_out[2:0] \dec31_dec_sub18_dec31_dec_sub18_cr_out + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_cr_out[2:0] \dec31_dec_sub8_dec31_dec_sub8_cr_out + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_cr_out[2:0] \dec31_dec_sub24_dec31_dec_sub24_cr_out + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_cr_out[2:0] \dec31_dec_sub4_dec31_dec_sub4_cr_out + case + assign $1\dec31_cr_out[2:0] 3'000 + end + sync always + update \dec31_cr_out $0\dec31_cr_out[2:0] + end + attribute \src "issuer_ls180.v:81037.3-81097.6" + process $proc$issuer_ls180.v:81037$3581 + assign { } { } + assign { } { } + assign $0\dec31_ldst_len[3:0] $1\dec31_ldst_len[3:0] + attribute \src "issuer_ls180.v:81038.5-81038.29" + switch \initial + attribute \src "issuer_ls180.v:81038.9-81038.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opc_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_ldst_len[3:0] \dec31_dec_sub10_dec31_dec_sub10_ldst_len + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_ldst_len[3:0] \dec31_dec_sub28_dec31_dec_sub28_ldst_len + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_ldst_len[3:0] \dec31_dec_sub0_dec31_dec_sub0_ldst_len + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_ldst_len[3:0] \dec31_dec_sub26_dec31_dec_sub26_ldst_len + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_ldst_len[3:0] \dec31_dec_sub19_dec31_dec_sub19_ldst_len + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_ldst_len[3:0] \dec31_dec_sub22_dec31_dec_sub22_ldst_len + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_ldst_len[3:0] \dec31_dec_sub9_dec31_dec_sub9_ldst_len + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_ldst_len[3:0] \dec31_dec_sub11_dec31_dec_sub11_ldst_len + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_ldst_len[3:0] \dec31_dec_sub27_dec31_dec_sub27_ldst_len + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_ldst_len[3:0] \dec31_dec_sub15_dec31_dec_sub15_ldst_len + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_ldst_len[3:0] \dec31_dec_sub20_dec31_dec_sub20_ldst_len + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_ldst_len[3:0] \dec31_dec_sub21_dec31_dec_sub21_ldst_len + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_ldst_len[3:0] \dec31_dec_sub23_dec31_dec_sub23_ldst_len + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_ldst_len[3:0] \dec31_dec_sub16_dec31_dec_sub16_ldst_len + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_ldst_len[3:0] \dec31_dec_sub18_dec31_dec_sub18_ldst_len + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_ldst_len[3:0] \dec31_dec_sub8_dec31_dec_sub8_ldst_len + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_ldst_len[3:0] \dec31_dec_sub24_dec31_dec_sub24_ldst_len + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_ldst_len[3:0] \dec31_dec_sub4_dec31_dec_sub4_ldst_len + case + assign $1\dec31_ldst_len[3:0] 4'0000 + end + sync always + update \dec31_ldst_len $0\dec31_ldst_len[3:0] + end + attribute \src "issuer_ls180.v:81098.3-81158.6" + process $proc$issuer_ls180.v:81098$3582 + assign { } { } + assign { } { } + assign $0\dec31_upd[1:0] $1\dec31_upd[1:0] + attribute \src "issuer_ls180.v:81099.5-81099.29" + switch \initial + attribute \src "issuer_ls180.v:81099.9-81099.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opc_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_upd[1:0] \dec31_dec_sub10_dec31_dec_sub10_upd + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_upd[1:0] \dec31_dec_sub28_dec31_dec_sub28_upd + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_upd[1:0] \dec31_dec_sub0_dec31_dec_sub0_upd + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_upd[1:0] \dec31_dec_sub26_dec31_dec_sub26_upd + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_upd[1:0] \dec31_dec_sub19_dec31_dec_sub19_upd + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_upd[1:0] \dec31_dec_sub22_dec31_dec_sub22_upd + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_upd[1:0] \dec31_dec_sub9_dec31_dec_sub9_upd + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_upd[1:0] \dec31_dec_sub11_dec31_dec_sub11_upd + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_upd[1:0] \dec31_dec_sub27_dec31_dec_sub27_upd + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_upd[1:0] \dec31_dec_sub15_dec31_dec_sub15_upd + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_upd[1:0] \dec31_dec_sub20_dec31_dec_sub20_upd + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_upd[1:0] \dec31_dec_sub21_dec31_dec_sub21_upd + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_upd[1:0] \dec31_dec_sub23_dec31_dec_sub23_upd + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_upd[1:0] \dec31_dec_sub16_dec31_dec_sub16_upd + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_upd[1:0] \dec31_dec_sub18_dec31_dec_sub18_upd + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_upd[1:0] \dec31_dec_sub8_dec31_dec_sub8_upd + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_upd[1:0] \dec31_dec_sub24_dec31_dec_sub24_upd + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_upd[1:0] \dec31_dec_sub4_dec31_dec_sub4_upd + case + assign $1\dec31_upd[1:0] 2'00 + end + sync always + update \dec31_upd $0\dec31_upd[1:0] + end + attribute \src "issuer_ls180.v:81159.3-81219.6" + process $proc$issuer_ls180.v:81159$3583 + assign { } { } + assign { } { } + assign $0\dec31_rc_sel[1:0] $1\dec31_rc_sel[1:0] + attribute \src "issuer_ls180.v:81160.5-81160.29" + switch \initial + attribute \src "issuer_ls180.v:81160.9-81160.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opc_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_rc_sel[1:0] \dec31_dec_sub10_dec31_dec_sub10_rc_sel + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_rc_sel[1:0] \dec31_dec_sub28_dec31_dec_sub28_rc_sel + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_rc_sel[1:0] \dec31_dec_sub0_dec31_dec_sub0_rc_sel + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_rc_sel[1:0] \dec31_dec_sub26_dec31_dec_sub26_rc_sel + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_rc_sel[1:0] \dec31_dec_sub19_dec31_dec_sub19_rc_sel + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_rc_sel[1:0] \dec31_dec_sub22_dec31_dec_sub22_rc_sel + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_rc_sel[1:0] \dec31_dec_sub9_dec31_dec_sub9_rc_sel + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_rc_sel[1:0] \dec31_dec_sub11_dec31_dec_sub11_rc_sel + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_rc_sel[1:0] \dec31_dec_sub27_dec31_dec_sub27_rc_sel + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_rc_sel[1:0] \dec31_dec_sub15_dec31_dec_sub15_rc_sel + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_rc_sel[1:0] \dec31_dec_sub20_dec31_dec_sub20_rc_sel + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_rc_sel[1:0] \dec31_dec_sub21_dec31_dec_sub21_rc_sel + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_rc_sel[1:0] \dec31_dec_sub23_dec31_dec_sub23_rc_sel + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_rc_sel[1:0] \dec31_dec_sub16_dec31_dec_sub16_rc_sel + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_rc_sel[1:0] \dec31_dec_sub18_dec31_dec_sub18_rc_sel + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_rc_sel[1:0] \dec31_dec_sub8_dec31_dec_sub8_rc_sel + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_rc_sel[1:0] \dec31_dec_sub24_dec31_dec_sub24_rc_sel + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_rc_sel[1:0] \dec31_dec_sub4_dec31_dec_sub4_rc_sel + case + assign $1\dec31_rc_sel[1:0] 2'00 + end + sync always + update \dec31_rc_sel $0\dec31_rc_sel[1:0] + end + attribute \src "issuer_ls180.v:81220.3-81280.6" + process $proc$issuer_ls180.v:81220$3584 + assign { } { } + assign { } { } + assign $0\dec31_cry_in[1:0] $1\dec31_cry_in[1:0] + attribute \src "issuer_ls180.v:81221.5-81221.29" + switch \initial + attribute \src "issuer_ls180.v:81221.9-81221.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opc_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_cry_in[1:0] \dec31_dec_sub10_dec31_dec_sub10_cry_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_cry_in[1:0] \dec31_dec_sub28_dec31_dec_sub28_cry_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_cry_in[1:0] \dec31_dec_sub0_dec31_dec_sub0_cry_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_cry_in[1:0] \dec31_dec_sub26_dec31_dec_sub26_cry_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_cry_in[1:0] \dec31_dec_sub19_dec31_dec_sub19_cry_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_cry_in[1:0] \dec31_dec_sub22_dec31_dec_sub22_cry_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_cry_in[1:0] \dec31_dec_sub9_dec31_dec_sub9_cry_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_cry_in[1:0] \dec31_dec_sub11_dec31_dec_sub11_cry_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_cry_in[1:0] \dec31_dec_sub27_dec31_dec_sub27_cry_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_cry_in[1:0] \dec31_dec_sub15_dec31_dec_sub15_cry_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_cry_in[1:0] \dec31_dec_sub20_dec31_dec_sub20_cry_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_cry_in[1:0] \dec31_dec_sub21_dec31_dec_sub21_cry_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_cry_in[1:0] \dec31_dec_sub23_dec31_dec_sub23_cry_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_cry_in[1:0] \dec31_dec_sub16_dec31_dec_sub16_cry_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_cry_in[1:0] \dec31_dec_sub18_dec31_dec_sub18_cry_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_cry_in[1:0] \dec31_dec_sub8_dec31_dec_sub8_cry_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_cry_in[1:0] \dec31_dec_sub24_dec31_dec_sub24_cry_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_cry_in[1:0] \dec31_dec_sub4_dec31_dec_sub4_cry_in + case + assign $1\dec31_cry_in[1:0] 2'00 + end + sync always + update \dec31_cry_in $0\dec31_cry_in[1:0] + end + attribute \src "issuer_ls180.v:81281.3-81341.6" + process $proc$issuer_ls180.v:81281$3585 + assign { } { } + assign { } { } + assign $0\dec31_inv_a[0:0] $1\dec31_inv_a[0:0] + attribute \src "issuer_ls180.v:81282.5-81282.29" + switch \initial + attribute \src "issuer_ls180.v:81282.9-81282.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opc_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_inv_a[0:0] \dec31_dec_sub10_dec31_dec_sub10_inv_a + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_inv_a[0:0] \dec31_dec_sub28_dec31_dec_sub28_inv_a + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_inv_a[0:0] \dec31_dec_sub0_dec31_dec_sub0_inv_a + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_inv_a[0:0] \dec31_dec_sub26_dec31_dec_sub26_inv_a + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_inv_a[0:0] \dec31_dec_sub19_dec31_dec_sub19_inv_a + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_inv_a[0:0] \dec31_dec_sub22_dec31_dec_sub22_inv_a + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_inv_a[0:0] \dec31_dec_sub9_dec31_dec_sub9_inv_a + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_inv_a[0:0] \dec31_dec_sub11_dec31_dec_sub11_inv_a + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_inv_a[0:0] \dec31_dec_sub27_dec31_dec_sub27_inv_a + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_inv_a[0:0] \dec31_dec_sub15_dec31_dec_sub15_inv_a + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_inv_a[0:0] \dec31_dec_sub20_dec31_dec_sub20_inv_a + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_inv_a[0:0] \dec31_dec_sub21_dec31_dec_sub21_inv_a + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_inv_a[0:0] \dec31_dec_sub23_dec31_dec_sub23_inv_a + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_inv_a[0:0] \dec31_dec_sub16_dec31_dec_sub16_inv_a + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_inv_a[0:0] \dec31_dec_sub18_dec31_dec_sub18_inv_a + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_inv_a[0:0] \dec31_dec_sub8_dec31_dec_sub8_inv_a + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_inv_a[0:0] \dec31_dec_sub24_dec31_dec_sub24_inv_a + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_inv_a[0:0] \dec31_dec_sub4_dec31_dec_sub4_inv_a + case + assign $1\dec31_inv_a[0:0] 1'0 + end + sync always + update \dec31_inv_a $0\dec31_inv_a[0:0] + end + attribute \src "issuer_ls180.v:81342.3-81402.6" + process $proc$issuer_ls180.v:81342$3586 + assign { } { } + assign { } { } + assign $0\dec31_inv_out[0:0] $1\dec31_inv_out[0:0] + attribute \src "issuer_ls180.v:81343.5-81343.29" + switch \initial + attribute \src "issuer_ls180.v:81343.9-81343.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opc_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_inv_out[0:0] \dec31_dec_sub10_dec31_dec_sub10_inv_out + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_inv_out[0:0] \dec31_dec_sub28_dec31_dec_sub28_inv_out + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_inv_out[0:0] \dec31_dec_sub0_dec31_dec_sub0_inv_out + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_inv_out[0:0] \dec31_dec_sub26_dec31_dec_sub26_inv_out + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_inv_out[0:0] \dec31_dec_sub19_dec31_dec_sub19_inv_out + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_inv_out[0:0] \dec31_dec_sub22_dec31_dec_sub22_inv_out + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_inv_out[0:0] \dec31_dec_sub9_dec31_dec_sub9_inv_out + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_inv_out[0:0] \dec31_dec_sub11_dec31_dec_sub11_inv_out + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_inv_out[0:0] \dec31_dec_sub27_dec31_dec_sub27_inv_out + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_inv_out[0:0] \dec31_dec_sub15_dec31_dec_sub15_inv_out + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_inv_out[0:0] \dec31_dec_sub20_dec31_dec_sub20_inv_out + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_inv_out[0:0] \dec31_dec_sub21_dec31_dec_sub21_inv_out + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_inv_out[0:0] \dec31_dec_sub23_dec31_dec_sub23_inv_out + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_inv_out[0:0] \dec31_dec_sub16_dec31_dec_sub16_inv_out + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_inv_out[0:0] \dec31_dec_sub18_dec31_dec_sub18_inv_out + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_inv_out[0:0] \dec31_dec_sub8_dec31_dec_sub8_inv_out + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_inv_out[0:0] \dec31_dec_sub24_dec31_dec_sub24_inv_out + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_inv_out[0:0] \dec31_dec_sub4_dec31_dec_sub4_inv_out + case + assign $1\dec31_inv_out[0:0] 1'0 + end + sync always + update \dec31_inv_out $0\dec31_inv_out[0:0] + end + attribute \src "issuer_ls180.v:81403.3-81463.6" + process $proc$issuer_ls180.v:81403$3587 + assign { } { } + assign { } { } + assign $0\dec31_cry_out[0:0] $1\dec31_cry_out[0:0] + attribute \src "issuer_ls180.v:81404.5-81404.29" + switch \initial + attribute \src "issuer_ls180.v:81404.9-81404.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opc_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_cry_out[0:0] \dec31_dec_sub10_dec31_dec_sub10_cry_out + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_cry_out[0:0] \dec31_dec_sub28_dec31_dec_sub28_cry_out + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_cry_out[0:0] \dec31_dec_sub0_dec31_dec_sub0_cry_out + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_cry_out[0:0] \dec31_dec_sub26_dec31_dec_sub26_cry_out + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_cry_out[0:0] \dec31_dec_sub19_dec31_dec_sub19_cry_out + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_cry_out[0:0] \dec31_dec_sub22_dec31_dec_sub22_cry_out + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_cry_out[0:0] \dec31_dec_sub9_dec31_dec_sub9_cry_out + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_cry_out[0:0] \dec31_dec_sub11_dec31_dec_sub11_cry_out + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_cry_out[0:0] \dec31_dec_sub27_dec31_dec_sub27_cry_out + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_cry_out[0:0] \dec31_dec_sub15_dec31_dec_sub15_cry_out + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_cry_out[0:0] \dec31_dec_sub20_dec31_dec_sub20_cry_out + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_cry_out[0:0] \dec31_dec_sub21_dec31_dec_sub21_cry_out + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_cry_out[0:0] \dec31_dec_sub23_dec31_dec_sub23_cry_out + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_cry_out[0:0] \dec31_dec_sub16_dec31_dec_sub16_cry_out + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_cry_out[0:0] \dec31_dec_sub18_dec31_dec_sub18_cry_out + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_cry_out[0:0] \dec31_dec_sub8_dec31_dec_sub8_cry_out + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_cry_out[0:0] \dec31_dec_sub24_dec31_dec_sub24_cry_out + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_cry_out[0:0] \dec31_dec_sub4_dec31_dec_sub4_cry_out + case + assign $1\dec31_cry_out[0:0] 1'0 + end + sync always + update \dec31_cry_out $0\dec31_cry_out[0:0] + end + attribute \src "issuer_ls180.v:81464.3-81524.6" + process $proc$issuer_ls180.v:81464$3588 + assign { } { } + assign { } { } + assign $0\dec31_br[0:0] $1\dec31_br[0:0] + attribute \src "issuer_ls180.v:81465.5-81465.29" + switch \initial + attribute \src "issuer_ls180.v:81465.9-81465.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opc_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_br[0:0] \dec31_dec_sub10_dec31_dec_sub10_br + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_br[0:0] \dec31_dec_sub28_dec31_dec_sub28_br + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_br[0:0] \dec31_dec_sub0_dec31_dec_sub0_br + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_br[0:0] \dec31_dec_sub26_dec31_dec_sub26_br + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_br[0:0] \dec31_dec_sub19_dec31_dec_sub19_br + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_br[0:0] \dec31_dec_sub22_dec31_dec_sub22_br + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_br[0:0] \dec31_dec_sub9_dec31_dec_sub9_br + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_br[0:0] \dec31_dec_sub11_dec31_dec_sub11_br + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_br[0:0] \dec31_dec_sub27_dec31_dec_sub27_br + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_br[0:0] \dec31_dec_sub15_dec31_dec_sub15_br + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_br[0:0] \dec31_dec_sub20_dec31_dec_sub20_br + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_br[0:0] \dec31_dec_sub21_dec31_dec_sub21_br + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_br[0:0] \dec31_dec_sub23_dec31_dec_sub23_br + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_br[0:0] \dec31_dec_sub16_dec31_dec_sub16_br + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_br[0:0] \dec31_dec_sub18_dec31_dec_sub18_br + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_br[0:0] \dec31_dec_sub8_dec31_dec_sub8_br + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_br[0:0] \dec31_dec_sub24_dec31_dec_sub24_br + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_br[0:0] \dec31_dec_sub4_dec31_dec_sub4_br + case + assign $1\dec31_br[0:0] 1'0 + end + sync always + update \dec31_br $0\dec31_br[0:0] + end + attribute \src "issuer_ls180.v:81525.3-81585.6" + process $proc$issuer_ls180.v:81525$3589 + assign { } { } + assign { } { } + assign $0\dec31_sgn_ext[0:0] $1\dec31_sgn_ext[0:0] + attribute \src "issuer_ls180.v:81526.5-81526.29" + switch \initial + attribute \src "issuer_ls180.v:81526.9-81526.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opc_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_sgn_ext[0:0] \dec31_dec_sub10_dec31_dec_sub10_sgn_ext + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_sgn_ext[0:0] \dec31_dec_sub28_dec31_dec_sub28_sgn_ext + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_sgn_ext[0:0] \dec31_dec_sub0_dec31_dec_sub0_sgn_ext + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_sgn_ext[0:0] \dec31_dec_sub26_dec31_dec_sub26_sgn_ext + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_sgn_ext[0:0] \dec31_dec_sub19_dec31_dec_sub19_sgn_ext + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_sgn_ext[0:0] \dec31_dec_sub22_dec31_dec_sub22_sgn_ext + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_sgn_ext[0:0] \dec31_dec_sub9_dec31_dec_sub9_sgn_ext + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_sgn_ext[0:0] \dec31_dec_sub11_dec31_dec_sub11_sgn_ext + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_sgn_ext[0:0] \dec31_dec_sub27_dec31_dec_sub27_sgn_ext + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_sgn_ext[0:0] \dec31_dec_sub15_dec31_dec_sub15_sgn_ext + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_sgn_ext[0:0] \dec31_dec_sub20_dec31_dec_sub20_sgn_ext + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_sgn_ext[0:0] \dec31_dec_sub21_dec31_dec_sub21_sgn_ext + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_sgn_ext[0:0] \dec31_dec_sub23_dec31_dec_sub23_sgn_ext + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_sgn_ext[0:0] \dec31_dec_sub16_dec31_dec_sub16_sgn_ext + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_sgn_ext[0:0] \dec31_dec_sub18_dec31_dec_sub18_sgn_ext + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_sgn_ext[0:0] \dec31_dec_sub8_dec31_dec_sub8_sgn_ext + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_sgn_ext[0:0] \dec31_dec_sub24_dec31_dec_sub24_sgn_ext + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_sgn_ext[0:0] \dec31_dec_sub4_dec31_dec_sub4_sgn_ext + case + assign $1\dec31_sgn_ext[0:0] 1'0 + end + sync always + update \dec31_sgn_ext $0\dec31_sgn_ext[0:0] + end + attribute \src "issuer_ls180.v:81586.3-81646.6" + process $proc$issuer_ls180.v:81586$3590 + assign { } { } + assign { } { } + assign $0\dec31_rsrv[0:0] $1\dec31_rsrv[0:0] + attribute \src "issuer_ls180.v:81587.5-81587.29" + switch \initial + attribute \src "issuer_ls180.v:81587.9-81587.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opc_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_rsrv[0:0] \dec31_dec_sub10_dec31_dec_sub10_rsrv + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_rsrv[0:0] \dec31_dec_sub28_dec31_dec_sub28_rsrv + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_rsrv[0:0] \dec31_dec_sub0_dec31_dec_sub0_rsrv + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_rsrv[0:0] \dec31_dec_sub26_dec31_dec_sub26_rsrv + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_rsrv[0:0] \dec31_dec_sub19_dec31_dec_sub19_rsrv + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_rsrv[0:0] \dec31_dec_sub22_dec31_dec_sub22_rsrv + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_rsrv[0:0] \dec31_dec_sub9_dec31_dec_sub9_rsrv + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_rsrv[0:0] \dec31_dec_sub11_dec31_dec_sub11_rsrv + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_rsrv[0:0] \dec31_dec_sub27_dec31_dec_sub27_rsrv + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_rsrv[0:0] \dec31_dec_sub15_dec31_dec_sub15_rsrv + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_rsrv[0:0] \dec31_dec_sub20_dec31_dec_sub20_rsrv + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_rsrv[0:0] \dec31_dec_sub21_dec31_dec_sub21_rsrv + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_rsrv[0:0] \dec31_dec_sub23_dec31_dec_sub23_rsrv + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_rsrv[0:0] \dec31_dec_sub16_dec31_dec_sub16_rsrv + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_rsrv[0:0] \dec31_dec_sub18_dec31_dec_sub18_rsrv + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_rsrv[0:0] \dec31_dec_sub8_dec31_dec_sub8_rsrv + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_rsrv[0:0] \dec31_dec_sub24_dec31_dec_sub24_rsrv + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_rsrv[0:0] \dec31_dec_sub4_dec31_dec_sub4_rsrv + case + assign $1\dec31_rsrv[0:0] 1'0 + end + sync always + update \dec31_rsrv $0\dec31_rsrv[0:0] + end + attribute \src "issuer_ls180.v:81647.3-81707.6" + process $proc$issuer_ls180.v:81647$3591 + assign { } { } + assign { } { } + assign $0\dec31_is_32b[0:0] $1\dec31_is_32b[0:0] + attribute \src "issuer_ls180.v:81648.5-81648.29" + switch \initial + attribute \src "issuer_ls180.v:81648.9-81648.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opc_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_is_32b[0:0] \dec31_dec_sub10_dec31_dec_sub10_is_32b + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_is_32b[0:0] \dec31_dec_sub28_dec31_dec_sub28_is_32b + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_is_32b[0:0] \dec31_dec_sub0_dec31_dec_sub0_is_32b + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_is_32b[0:0] \dec31_dec_sub26_dec31_dec_sub26_is_32b + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_is_32b[0:0] \dec31_dec_sub19_dec31_dec_sub19_is_32b + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_is_32b[0:0] \dec31_dec_sub22_dec31_dec_sub22_is_32b + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_is_32b[0:0] \dec31_dec_sub9_dec31_dec_sub9_is_32b + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_is_32b[0:0] \dec31_dec_sub11_dec31_dec_sub11_is_32b + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_is_32b[0:0] \dec31_dec_sub27_dec31_dec_sub27_is_32b + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_is_32b[0:0] \dec31_dec_sub15_dec31_dec_sub15_is_32b + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_is_32b[0:0] \dec31_dec_sub20_dec31_dec_sub20_is_32b + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_is_32b[0:0] \dec31_dec_sub21_dec31_dec_sub21_is_32b + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_is_32b[0:0] \dec31_dec_sub23_dec31_dec_sub23_is_32b + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_is_32b[0:0] \dec31_dec_sub16_dec31_dec_sub16_is_32b + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_is_32b[0:0] \dec31_dec_sub18_dec31_dec_sub18_is_32b + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_is_32b[0:0] \dec31_dec_sub8_dec31_dec_sub8_is_32b + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_is_32b[0:0] \dec31_dec_sub24_dec31_dec_sub24_is_32b + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_is_32b[0:0] \dec31_dec_sub4_dec31_dec_sub4_is_32b + case + assign $1\dec31_is_32b[0:0] 1'0 + end + sync always + update \dec31_is_32b $0\dec31_is_32b[0:0] + end + attribute \src "issuer_ls180.v:81708.3-81768.6" + process $proc$issuer_ls180.v:81708$3592 + assign { } { } + assign { } { } + assign $0\dec31_sgn[0:0] $1\dec31_sgn[0:0] + attribute \src "issuer_ls180.v:81709.5-81709.29" + switch \initial + attribute \src "issuer_ls180.v:81709.9-81709.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opc_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_sgn[0:0] \dec31_dec_sub10_dec31_dec_sub10_sgn + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_sgn[0:0] \dec31_dec_sub28_dec31_dec_sub28_sgn + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_sgn[0:0] \dec31_dec_sub0_dec31_dec_sub0_sgn + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_sgn[0:0] \dec31_dec_sub26_dec31_dec_sub26_sgn + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_sgn[0:0] \dec31_dec_sub19_dec31_dec_sub19_sgn + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_sgn[0:0] \dec31_dec_sub22_dec31_dec_sub22_sgn + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_sgn[0:0] \dec31_dec_sub9_dec31_dec_sub9_sgn + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_sgn[0:0] \dec31_dec_sub11_dec31_dec_sub11_sgn + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_sgn[0:0] \dec31_dec_sub27_dec31_dec_sub27_sgn + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_sgn[0:0] \dec31_dec_sub15_dec31_dec_sub15_sgn + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_sgn[0:0] \dec31_dec_sub20_dec31_dec_sub20_sgn + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_sgn[0:0] \dec31_dec_sub21_dec31_dec_sub21_sgn + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_sgn[0:0] \dec31_dec_sub23_dec31_dec_sub23_sgn + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_sgn[0:0] \dec31_dec_sub16_dec31_dec_sub16_sgn + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_sgn[0:0] \dec31_dec_sub18_dec31_dec_sub18_sgn + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_sgn[0:0] \dec31_dec_sub8_dec31_dec_sub8_sgn + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_sgn[0:0] \dec31_dec_sub24_dec31_dec_sub24_sgn + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_sgn[0:0] \dec31_dec_sub4_dec31_dec_sub4_sgn + case + assign $1\dec31_sgn[0:0] 1'0 + end + sync always + update \dec31_sgn $0\dec31_sgn[0:0] + end + attribute \src "issuer_ls180.v:81769.3-81829.6" + process $proc$issuer_ls180.v:81769$3593 + assign { } { } + assign { } { } + assign $0\dec31_lk[0:0] $1\dec31_lk[0:0] + attribute \src "issuer_ls180.v:81770.5-81770.29" + switch \initial + attribute \src "issuer_ls180.v:81770.9-81770.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opc_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_lk[0:0] \dec31_dec_sub10_dec31_dec_sub10_lk + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_lk[0:0] \dec31_dec_sub28_dec31_dec_sub28_lk + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_lk[0:0] \dec31_dec_sub0_dec31_dec_sub0_lk + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_lk[0:0] \dec31_dec_sub26_dec31_dec_sub26_lk + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_lk[0:0] \dec31_dec_sub19_dec31_dec_sub19_lk + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_lk[0:0] \dec31_dec_sub22_dec31_dec_sub22_lk + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_lk[0:0] \dec31_dec_sub9_dec31_dec_sub9_lk + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_lk[0:0] \dec31_dec_sub11_dec31_dec_sub11_lk + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_lk[0:0] \dec31_dec_sub27_dec31_dec_sub27_lk + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_lk[0:0] \dec31_dec_sub15_dec31_dec_sub15_lk + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_lk[0:0] \dec31_dec_sub20_dec31_dec_sub20_lk + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_lk[0:0] \dec31_dec_sub21_dec31_dec_sub21_lk + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_lk[0:0] \dec31_dec_sub23_dec31_dec_sub23_lk + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_lk[0:0] \dec31_dec_sub16_dec31_dec_sub16_lk + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_lk[0:0] \dec31_dec_sub18_dec31_dec_sub18_lk + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_lk[0:0] \dec31_dec_sub8_dec31_dec_sub8_lk + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_lk[0:0] \dec31_dec_sub24_dec31_dec_sub24_lk + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_lk[0:0] \dec31_dec_sub4_dec31_dec_sub4_lk + case + assign $1\dec31_lk[0:0] 1'0 + end + sync always + update \dec31_lk $0\dec31_lk[0:0] + end + attribute \src "issuer_ls180.v:81830.3-81890.6" + process $proc$issuer_ls180.v:81830$3594 + assign { } { } + assign { } { } + assign $0\dec31_sgl_pipe[0:0] $1\dec31_sgl_pipe[0:0] + attribute \src "issuer_ls180.v:81831.5-81831.29" + switch \initial + attribute \src "issuer_ls180.v:81831.9-81831.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opc_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_sgl_pipe[0:0] \dec31_dec_sub10_dec31_dec_sub10_sgl_pipe + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_sgl_pipe[0:0] \dec31_dec_sub28_dec31_dec_sub28_sgl_pipe + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_sgl_pipe[0:0] \dec31_dec_sub0_dec31_dec_sub0_sgl_pipe + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_sgl_pipe[0:0] \dec31_dec_sub26_dec31_dec_sub26_sgl_pipe + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_sgl_pipe[0:0] \dec31_dec_sub19_dec31_dec_sub19_sgl_pipe + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_sgl_pipe[0:0] \dec31_dec_sub22_dec31_dec_sub22_sgl_pipe + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_sgl_pipe[0:0] \dec31_dec_sub9_dec31_dec_sub9_sgl_pipe + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_sgl_pipe[0:0] \dec31_dec_sub11_dec31_dec_sub11_sgl_pipe + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_sgl_pipe[0:0] \dec31_dec_sub27_dec31_dec_sub27_sgl_pipe + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_sgl_pipe[0:0] \dec31_dec_sub15_dec31_dec_sub15_sgl_pipe + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_sgl_pipe[0:0] \dec31_dec_sub20_dec31_dec_sub20_sgl_pipe + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_sgl_pipe[0:0] \dec31_dec_sub21_dec31_dec_sub21_sgl_pipe + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_sgl_pipe[0:0] \dec31_dec_sub23_dec31_dec_sub23_sgl_pipe + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_sgl_pipe[0:0] \dec31_dec_sub16_dec31_dec_sub16_sgl_pipe + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_sgl_pipe[0:0] \dec31_dec_sub18_dec31_dec_sub18_sgl_pipe + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_sgl_pipe[0:0] \dec31_dec_sub8_dec31_dec_sub8_sgl_pipe + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_sgl_pipe[0:0] \dec31_dec_sub24_dec31_dec_sub24_sgl_pipe + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_sgl_pipe[0:0] \dec31_dec_sub4_dec31_dec_sub4_sgl_pipe + case + assign $1\dec31_sgl_pipe[0:0] 1'0 + end + sync always + update \dec31_sgl_pipe $0\dec31_sgl_pipe[0:0] + end + connect \dec31_dec_sub4_opcode_in \opcode_in + connect \dec31_dec_sub24_opcode_in \opcode_in + connect \dec31_dec_sub8_opcode_in \opcode_in + connect \dec31_dec_sub18_opcode_in \opcode_in + connect \dec31_dec_sub16_opcode_in \opcode_in + connect \dec31_dec_sub23_opcode_in \opcode_in + connect \dec31_dec_sub21_opcode_in \opcode_in + connect \dec31_dec_sub20_opcode_in \opcode_in + connect \dec31_dec_sub15_opcode_in \opcode_in + connect \dec31_dec_sub27_opcode_in \opcode_in + connect \dec31_dec_sub11_opcode_in \opcode_in + connect \dec31_dec_sub9_opcode_in \opcode_in + connect \dec31_dec_sub22_opcode_in \opcode_in + connect \dec31_dec_sub19_opcode_in \opcode_in + connect \dec31_dec_sub26_opcode_in \opcode_in + connect \dec31_dec_sub0_opcode_in \opcode_in + connect \dec31_dec_sub28_opcode_in \opcode_in + connect \dec31_dec_sub10_opcode_in \opcode_in + connect \opc_in \opcode_switch [4:0] + connect \opcode_switch \opcode_in [10:1] +end +attribute \src "issuer_ls180.v:81915.1-82630.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.dec2.dec.dec31.dec31_dec_sub0" +attribute \generator "nMigen" +module \dec31_dec_sub0 + attribute \src "issuer_ls180.v:82268.3-82286.6" + wire width 8 $0\dec31_dec_sub0_asmcode[7:0] + attribute \src "issuer_ls180.v:82344.3-82362.6" + wire $0\dec31_dec_sub0_br[0:0] + attribute \src "issuer_ls180.v:82591.3-82609.6" + wire width 3 $0\dec31_dec_sub0_cr_in[2:0] + attribute \src "issuer_ls180.v:82610.3-82628.6" + wire width 3 $0\dec31_dec_sub0_cr_out[2:0] + attribute \src "issuer_ls180.v:82249.3-82267.6" + wire width 2 $0\dec31_dec_sub0_cry_in[1:0] + attribute \src "issuer_ls180.v:82325.3-82343.6" + wire $0\dec31_dec_sub0_cry_out[0:0] + attribute \src "issuer_ls180.v:82496.3-82514.6" + wire width 5 $0\dec31_dec_sub0_form[4:0] + attribute \src "issuer_ls180.v:82173.3-82191.6" + wire width 12 $0\dec31_dec_sub0_function_unit[11:0] + attribute \src "issuer_ls180.v:82515.3-82533.6" + wire width 3 $0\dec31_dec_sub0_in1_sel[2:0] + attribute \src "issuer_ls180.v:82534.3-82552.6" + wire width 4 $0\dec31_dec_sub0_in2_sel[3:0] + attribute \src "issuer_ls180.v:82553.3-82571.6" + wire width 2 $0\dec31_dec_sub0_in3_sel[1:0] + attribute \src "issuer_ls180.v:82382.3-82400.6" + wire width 7 $0\dec31_dec_sub0_internal_op[6:0] + attribute \src "issuer_ls180.v:82287.3-82305.6" + wire $0\dec31_dec_sub0_inv_a[0:0] + attribute \src "issuer_ls180.v:82306.3-82324.6" + wire $0\dec31_dec_sub0_inv_out[0:0] + attribute \src "issuer_ls180.v:82420.3-82438.6" + wire $0\dec31_dec_sub0_is_32b[0:0] + attribute \src "issuer_ls180.v:82192.3-82210.6" + wire width 4 $0\dec31_dec_sub0_ldst_len[3:0] + attribute \src "issuer_ls180.v:82458.3-82476.6" + wire $0\dec31_dec_sub0_lk[0:0] + attribute \src "issuer_ls180.v:82572.3-82590.6" + wire width 2 $0\dec31_dec_sub0_out_sel[1:0] + attribute \src "issuer_ls180.v:82230.3-82248.6" + wire width 2 $0\dec31_dec_sub0_rc_sel[1:0] + attribute \src "issuer_ls180.v:82401.3-82419.6" + wire $0\dec31_dec_sub0_rsrv[0:0] + attribute \src "issuer_ls180.v:82477.3-82495.6" + wire $0\dec31_dec_sub0_sgl_pipe[0:0] + attribute \src "issuer_ls180.v:82439.3-82457.6" + wire $0\dec31_dec_sub0_sgn[0:0] + attribute \src "issuer_ls180.v:82363.3-82381.6" + wire $0\dec31_dec_sub0_sgn_ext[0:0] + attribute \src "issuer_ls180.v:82211.3-82229.6" + wire width 2 $0\dec31_dec_sub0_upd[1:0] + attribute \src "issuer_ls180.v:81916.7-81916.20" + wire $0\initial[0:0] + attribute \src "issuer_ls180.v:82268.3-82286.6" + wire width 8 $1\dec31_dec_sub0_asmcode[7:0] + attribute \src "issuer_ls180.v:82344.3-82362.6" + wire $1\dec31_dec_sub0_br[0:0] + attribute \src "issuer_ls180.v:82591.3-82609.6" + wire width 3 $1\dec31_dec_sub0_cr_in[2:0] + attribute \src "issuer_ls180.v:82610.3-82628.6" + wire width 3 $1\dec31_dec_sub0_cr_out[2:0] + attribute \src "issuer_ls180.v:82249.3-82267.6" + wire width 2 $1\dec31_dec_sub0_cry_in[1:0] + attribute \src "issuer_ls180.v:82325.3-82343.6" + wire $1\dec31_dec_sub0_cry_out[0:0] + attribute \src "issuer_ls180.v:82496.3-82514.6" + wire width 5 $1\dec31_dec_sub0_form[4:0] + attribute \src "issuer_ls180.v:82173.3-82191.6" + wire width 12 $1\dec31_dec_sub0_function_unit[11:0] + attribute \src "issuer_ls180.v:82515.3-82533.6" + wire width 3 $1\dec31_dec_sub0_in1_sel[2:0] + attribute \src "issuer_ls180.v:82534.3-82552.6" + wire width 4 $1\dec31_dec_sub0_in2_sel[3:0] + attribute \src "issuer_ls180.v:82553.3-82571.6" + wire width 2 $1\dec31_dec_sub0_in3_sel[1:0] + attribute \src "issuer_ls180.v:82382.3-82400.6" + wire width 7 $1\dec31_dec_sub0_internal_op[6:0] + attribute \src "issuer_ls180.v:82287.3-82305.6" + wire $1\dec31_dec_sub0_inv_a[0:0] + attribute \src "issuer_ls180.v:82306.3-82324.6" + wire $1\dec31_dec_sub0_inv_out[0:0] + attribute \src "issuer_ls180.v:82420.3-82438.6" + wire $1\dec31_dec_sub0_is_32b[0:0] + attribute \src "issuer_ls180.v:82192.3-82210.6" + wire width 4 $1\dec31_dec_sub0_ldst_len[3:0] + attribute \src "issuer_ls180.v:82458.3-82476.6" + wire $1\dec31_dec_sub0_lk[0:0] + attribute \src "issuer_ls180.v:82572.3-82590.6" + wire width 2 $1\dec31_dec_sub0_out_sel[1:0] + attribute \src "issuer_ls180.v:82230.3-82248.6" + wire width 2 $1\dec31_dec_sub0_rc_sel[1:0] + attribute \src "issuer_ls180.v:82401.3-82419.6" + wire $1\dec31_dec_sub0_rsrv[0:0] + attribute \src "issuer_ls180.v:82477.3-82495.6" + wire $1\dec31_dec_sub0_sgl_pipe[0:0] + attribute \src "issuer_ls180.v:82439.3-82457.6" + wire $1\dec31_dec_sub0_sgn[0:0] + attribute \src "issuer_ls180.v:82363.3-82381.6" + wire $1\dec31_dec_sub0_sgn_ext[0:0] + attribute \src "issuer_ls180.v:82211.3-82229.6" + wire width 2 $1\dec31_dec_sub0_upd[1:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 8 output 4 \dec31_dec_sub0_asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 18 \dec31_dec_sub0_br + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 9 \dec31_dec_sub0_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 10 \dec31_dec_sub0_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 14 \dec31_dec_sub0_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 17 \dec31_dec_sub0_cry_out + attribute \enum_base_type "Form" + attribute \enum_value_00000 "NONE" + attribute \enum_value_00001 "I" + attribute \enum_value_00010 "B" + attribute \enum_value_00011 "SC" + attribute \enum_value_00100 "D" + attribute \enum_value_00101 "DS" + attribute \enum_value_00110 "DQ" + attribute \enum_value_00111 "DX" + attribute \enum_value_01000 "X" + attribute \enum_value_01001 "XL" + attribute \enum_value_01010 "XFX" + attribute \enum_value_01011 "XFL" + attribute \enum_value_01100 "XX1" + attribute \enum_value_01101 "XX2" + attribute \enum_value_01110 "XX3" + attribute \enum_value_01111 "XX4" + attribute \enum_value_10000 "XS" + attribute \enum_value_10001 "XO" + attribute \enum_value_10010 "A" + attribute \enum_value_10011 "M" + attribute \enum_value_10100 "MD" + attribute \enum_value_10101 "MDS" + attribute \enum_value_10110 "VA" + attribute \enum_value_10111 "VC" + attribute \enum_value_11000 "VX" + attribute \enum_value_11001 "EVX" + attribute \enum_value_11010 "EVS" + attribute \enum_value_11011 "Z22" + attribute \enum_value_11100 "Z23" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 5 output 3 \dec31_dec_sub0_form + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 12 output 1 \dec31_dec_sub0_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 5 \dec31_dec_sub0_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 output 6 \dec31_dec_sub0_in2_sel + attribute \enum_base_type "In3Sel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RS" + attribute \enum_value_10 "RB" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 7 \dec31_dec_sub0_in3_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 7 output 2 \dec31_dec_sub0_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 15 \dec31_dec_sub0_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 16 \dec31_dec_sub0_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 21 \dec31_dec_sub0_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 output 11 \dec31_dec_sub0_ldst_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 23 \dec31_dec_sub0_lk + attribute \enum_base_type "OutSel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RT" + attribute \enum_value_10 "RA" + attribute \enum_value_11 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 8 \dec31_dec_sub0_out_sel + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 13 \dec31_dec_sub0_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 20 \dec31_dec_sub0_rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 24 \dec31_dec_sub0_sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 22 \dec31_dec_sub0_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 19 \dec31_dec_sub0_sgn_ext + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 12 \dec31_dec_sub0_upd + attribute \src "issuer_ls180.v:81916.7-81916.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + wire width 32 input 25 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:320" + wire width 5 \opcode_switch + attribute \src "issuer_ls180.v:81916.7-81916.20" + process $proc$issuer_ls180.v:81916$3620 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "issuer_ls180.v:82173.3-82191.6" + process $proc$issuer_ls180.v:82173$3596 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub0_function_unit[11:0] $1\dec31_dec_sub0_function_unit[11:0] + attribute \src "issuer_ls180.v:82174.5-82174.29" + switch \initial + attribute \src "issuer_ls180.v:82174.9-82174.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub0_function_unit[11:0] 12'000000000010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub0_function_unit[11:0] 12'000000000010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub0_function_unit[11:0] 12'000000000010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub0_function_unit[11:0] 12'000001000000 + case + assign $1\dec31_dec_sub0_function_unit[11:0] 12'000000000000 + end + sync always + update \dec31_dec_sub0_function_unit $0\dec31_dec_sub0_function_unit[11:0] + end + attribute \src "issuer_ls180.v:82192.3-82210.6" + process $proc$issuer_ls180.v:82192$3597 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub0_ldst_len[3:0] $1\dec31_dec_sub0_ldst_len[3:0] + attribute \src "issuer_ls180.v:82193.5-82193.29" + switch \initial + attribute \src "issuer_ls180.v:82193.9-82193.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub0_ldst_len[3:0] 4'0000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub0_ldst_len[3:0] 4'0000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub0_ldst_len[3:0] 4'0000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub0_ldst_len[3:0] 4'0000 + case + assign $1\dec31_dec_sub0_ldst_len[3:0] 4'0000 + end + sync always + update \dec31_dec_sub0_ldst_len $0\dec31_dec_sub0_ldst_len[3:0] + end + attribute \src "issuer_ls180.v:82211.3-82229.6" + process $proc$issuer_ls180.v:82211$3598 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub0_upd[1:0] $1\dec31_dec_sub0_upd[1:0] + attribute \src "issuer_ls180.v:82212.5-82212.29" + switch \initial + attribute \src "issuer_ls180.v:82212.9-82212.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub0_upd[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub0_upd[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub0_upd[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub0_upd[1:0] 2'00 + case + assign $1\dec31_dec_sub0_upd[1:0] 2'00 + end + sync always + update \dec31_dec_sub0_upd $0\dec31_dec_sub0_upd[1:0] + end + attribute \src "issuer_ls180.v:82230.3-82248.6" + process $proc$issuer_ls180.v:82230$3599 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub0_rc_sel[1:0] $1\dec31_dec_sub0_rc_sel[1:0] + attribute \src "issuer_ls180.v:82231.5-82231.29" + switch \initial + attribute \src "issuer_ls180.v:82231.9-82231.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub0_rc_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub0_rc_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub0_rc_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub0_rc_sel[1:0] 2'00 + case + assign $1\dec31_dec_sub0_rc_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub0_rc_sel $0\dec31_dec_sub0_rc_sel[1:0] + end + attribute \src "issuer_ls180.v:82249.3-82267.6" + process $proc$issuer_ls180.v:82249$3600 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub0_cry_in[1:0] $1\dec31_dec_sub0_cry_in[1:0] + attribute \src "issuer_ls180.v:82250.5-82250.29" + switch \initial + attribute \src "issuer_ls180.v:82250.9-82250.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub0_cry_in[1:0] 2'01 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub0_cry_in[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub0_cry_in[1:0] 2'01 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub0_cry_in[1:0] 2'00 + case + assign $1\dec31_dec_sub0_cry_in[1:0] 2'00 + end + sync always + update \dec31_dec_sub0_cry_in $0\dec31_dec_sub0_cry_in[1:0] + end + attribute \src "issuer_ls180.v:82268.3-82286.6" + process $proc$issuer_ls180.v:82268$3601 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub0_asmcode[7:0] $1\dec31_dec_sub0_asmcode[7:0] + attribute \src "issuer_ls180.v:82269.5-82269.29" + switch \initial + attribute \src "issuer_ls180.v:82269.9-82269.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub0_asmcode[7:0] 8'00011010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub0_asmcode[7:0] 8'00011100 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub0_asmcode[7:0] 8'00011110 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub0_asmcode[7:0] 8'10011011 + case + assign $1\dec31_dec_sub0_asmcode[7:0] 8'00000000 + end + sync always + update \dec31_dec_sub0_asmcode $0\dec31_dec_sub0_asmcode[7:0] + end + attribute \src "issuer_ls180.v:82287.3-82305.6" + process $proc$issuer_ls180.v:82287$3602 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub0_inv_a[0:0] $1\dec31_dec_sub0_inv_a[0:0] + attribute \src "issuer_ls180.v:82288.5-82288.29" + switch \initial + attribute \src "issuer_ls180.v:82288.9-82288.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub0_inv_a[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub0_inv_a[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub0_inv_a[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub0_inv_a[0:0] 1'0 + case + assign $1\dec31_dec_sub0_inv_a[0:0] 1'0 + end + sync always + update \dec31_dec_sub0_inv_a $0\dec31_dec_sub0_inv_a[0:0] + end + attribute \src "issuer_ls180.v:82306.3-82324.6" + process $proc$issuer_ls180.v:82306$3603 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub0_inv_out[0:0] $1\dec31_dec_sub0_inv_out[0:0] + attribute \src "issuer_ls180.v:82307.5-82307.29" + switch \initial + attribute \src "issuer_ls180.v:82307.9-82307.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub0_inv_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub0_inv_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub0_inv_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub0_inv_out[0:0] 1'0 + case + assign $1\dec31_dec_sub0_inv_out[0:0] 1'0 + end + sync always + update \dec31_dec_sub0_inv_out $0\dec31_dec_sub0_inv_out[0:0] + end + attribute \src "issuer_ls180.v:82325.3-82343.6" + process $proc$issuer_ls180.v:82325$3604 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub0_cry_out[0:0] $1\dec31_dec_sub0_cry_out[0:0] + attribute \src "issuer_ls180.v:82326.5-82326.29" + switch \initial + attribute \src "issuer_ls180.v:82326.9-82326.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub0_cry_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub0_cry_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub0_cry_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub0_cry_out[0:0] 1'0 + case + assign $1\dec31_dec_sub0_cry_out[0:0] 1'0 + end + sync always + update \dec31_dec_sub0_cry_out $0\dec31_dec_sub0_cry_out[0:0] + end + attribute \src "issuer_ls180.v:82344.3-82362.6" + process $proc$issuer_ls180.v:82344$3605 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub0_br[0:0] $1\dec31_dec_sub0_br[0:0] + attribute \src "issuer_ls180.v:82345.5-82345.29" + switch \initial + attribute \src "issuer_ls180.v:82345.9-82345.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub0_br[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub0_br[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub0_br[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub0_br[0:0] 1'0 + case + assign $1\dec31_dec_sub0_br[0:0] 1'0 + end + sync always + update \dec31_dec_sub0_br $0\dec31_dec_sub0_br[0:0] + end + attribute \src "issuer_ls180.v:82363.3-82381.6" + process $proc$issuer_ls180.v:82363$3606 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub0_sgn_ext[0:0] $1\dec31_dec_sub0_sgn_ext[0:0] + attribute \src "issuer_ls180.v:82364.5-82364.29" + switch \initial + attribute \src "issuer_ls180.v:82364.9-82364.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub0_sgn_ext[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub0_sgn_ext[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub0_sgn_ext[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub0_sgn_ext[0:0] 1'0 + case + assign $1\dec31_dec_sub0_sgn_ext[0:0] 1'0 + end + sync always + update \dec31_dec_sub0_sgn_ext $0\dec31_dec_sub0_sgn_ext[0:0] + end + attribute \src "issuer_ls180.v:82382.3-82400.6" + process $proc$issuer_ls180.v:82382$3607 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub0_internal_op[6:0] $1\dec31_dec_sub0_internal_op[6:0] + attribute \src "issuer_ls180.v:82383.5-82383.29" + switch \initial + attribute \src "issuer_ls180.v:82383.9-82383.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub0_internal_op[6:0] 7'0001010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub0_internal_op[6:0] 7'0001100 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub0_internal_op[6:0] 7'0001010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub0_internal_op[6:0] 7'0111011 + case + assign $1\dec31_dec_sub0_internal_op[6:0] 7'0000000 + end + sync always + update \dec31_dec_sub0_internal_op $0\dec31_dec_sub0_internal_op[6:0] + end + attribute \src "issuer_ls180.v:82401.3-82419.6" + process $proc$issuer_ls180.v:82401$3608 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub0_rsrv[0:0] $1\dec31_dec_sub0_rsrv[0:0] + attribute \src "issuer_ls180.v:82402.5-82402.29" + switch \initial + attribute \src "issuer_ls180.v:82402.9-82402.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub0_rsrv[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub0_rsrv[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub0_rsrv[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub0_rsrv[0:0] 1'0 + case + assign $1\dec31_dec_sub0_rsrv[0:0] 1'0 + end + sync always + update \dec31_dec_sub0_rsrv $0\dec31_dec_sub0_rsrv[0:0] + end + attribute \src "issuer_ls180.v:82420.3-82438.6" + process $proc$issuer_ls180.v:82420$3609 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub0_is_32b[0:0] $1\dec31_dec_sub0_is_32b[0:0] + attribute \src "issuer_ls180.v:82421.5-82421.29" + switch \initial + attribute \src "issuer_ls180.v:82421.9-82421.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub0_is_32b[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub0_is_32b[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub0_is_32b[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub0_is_32b[0:0] 1'0 + case + assign $1\dec31_dec_sub0_is_32b[0:0] 1'0 + end + sync always + update \dec31_dec_sub0_is_32b $0\dec31_dec_sub0_is_32b[0:0] + end + attribute \src "issuer_ls180.v:82439.3-82457.6" + process $proc$issuer_ls180.v:82439$3610 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub0_sgn[0:0] $1\dec31_dec_sub0_sgn[0:0] + attribute \src "issuer_ls180.v:82440.5-82440.29" + switch \initial + attribute \src "issuer_ls180.v:82440.9-82440.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub0_sgn[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub0_sgn[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub0_sgn[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub0_sgn[0:0] 1'0 + case + assign $1\dec31_dec_sub0_sgn[0:0] 1'0 + end + sync always + update \dec31_dec_sub0_sgn $0\dec31_dec_sub0_sgn[0:0] + end + attribute \src "issuer_ls180.v:82458.3-82476.6" + process $proc$issuer_ls180.v:82458$3611 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub0_lk[0:0] $1\dec31_dec_sub0_lk[0:0] + attribute \src "issuer_ls180.v:82459.5-82459.29" + switch \initial + attribute \src "issuer_ls180.v:82459.9-82459.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub0_lk[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub0_lk[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub0_lk[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub0_lk[0:0] 1'0 + case + assign $1\dec31_dec_sub0_lk[0:0] 1'0 + end + sync always + update \dec31_dec_sub0_lk $0\dec31_dec_sub0_lk[0:0] + end + attribute \src "issuer_ls180.v:82477.3-82495.6" + process $proc$issuer_ls180.v:82477$3612 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub0_sgl_pipe[0:0] $1\dec31_dec_sub0_sgl_pipe[0:0] + attribute \src "issuer_ls180.v:82478.5-82478.29" + switch \initial + attribute \src "issuer_ls180.v:82478.9-82478.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub0_sgl_pipe[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub0_sgl_pipe[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub0_sgl_pipe[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub0_sgl_pipe[0:0] 1'0 + case + assign $1\dec31_dec_sub0_sgl_pipe[0:0] 1'0 + end + sync always + update \dec31_dec_sub0_sgl_pipe $0\dec31_dec_sub0_sgl_pipe[0:0] + end + attribute \src "issuer_ls180.v:82496.3-82514.6" + process $proc$issuer_ls180.v:82496$3613 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub0_form[4:0] $1\dec31_dec_sub0_form[4:0] + attribute \src "issuer_ls180.v:82497.5-82497.29" + switch \initial + attribute \src "issuer_ls180.v:82497.9-82497.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub0_form[4:0] 5'01000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub0_form[4:0] 5'01000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub0_form[4:0] 5'01000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub0_form[4:0] 5'11000 + case + assign $1\dec31_dec_sub0_form[4:0] 5'00000 + end + sync always + update \dec31_dec_sub0_form $0\dec31_dec_sub0_form[4:0] + end + attribute \src "issuer_ls180.v:82515.3-82533.6" + process $proc$issuer_ls180.v:82515$3614 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub0_in1_sel[2:0] $1\dec31_dec_sub0_in1_sel[2:0] + attribute \src "issuer_ls180.v:82516.5-82516.29" + switch \initial + attribute \src "issuer_ls180.v:82516.9-82516.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub0_in1_sel[2:0] 3'001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub0_in1_sel[2:0] 3'001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub0_in1_sel[2:0] 3'001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub0_in1_sel[2:0] 3'000 + case + assign $1\dec31_dec_sub0_in1_sel[2:0] 3'000 + end + sync always + update \dec31_dec_sub0_in1_sel $0\dec31_dec_sub0_in1_sel[2:0] + end + attribute \src "issuer_ls180.v:82534.3-82552.6" + process $proc$issuer_ls180.v:82534$3615 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub0_in2_sel[3:0] $1\dec31_dec_sub0_in2_sel[3:0] + attribute \src "issuer_ls180.v:82535.5-82535.29" + switch \initial + attribute \src "issuer_ls180.v:82535.9-82535.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub0_in2_sel[3:0] 4'0001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub0_in2_sel[3:0] 4'0001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub0_in2_sel[3:0] 4'0001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub0_in2_sel[3:0] 4'0000 + case + assign $1\dec31_dec_sub0_in2_sel[3:0] 4'0000 + end + sync always + update \dec31_dec_sub0_in2_sel $0\dec31_dec_sub0_in2_sel[3:0] + end + attribute \src "issuer_ls180.v:82553.3-82571.6" + process $proc$issuer_ls180.v:82553$3616 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub0_in3_sel[1:0] $1\dec31_dec_sub0_in3_sel[1:0] + attribute \src "issuer_ls180.v:82554.5-82554.29" + switch \initial + attribute \src "issuer_ls180.v:82554.9-82554.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub0_in3_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub0_in3_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub0_in3_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub0_in3_sel[1:0] 2'00 + case + assign $1\dec31_dec_sub0_in3_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub0_in3_sel $0\dec31_dec_sub0_in3_sel[1:0] + end + attribute \src "issuer_ls180.v:82572.3-82590.6" + process $proc$issuer_ls180.v:82572$3617 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub0_out_sel[1:0] $1\dec31_dec_sub0_out_sel[1:0] + attribute \src "issuer_ls180.v:82573.5-82573.29" + switch \initial + attribute \src "issuer_ls180.v:82573.9-82573.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub0_out_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub0_out_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub0_out_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub0_out_sel[1:0] 2'01 + case + assign $1\dec31_dec_sub0_out_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub0_out_sel $0\dec31_dec_sub0_out_sel[1:0] + end + attribute \src "issuer_ls180.v:82591.3-82609.6" + process $proc$issuer_ls180.v:82591$3618 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub0_cr_in[2:0] $1\dec31_dec_sub0_cr_in[2:0] + attribute \src "issuer_ls180.v:82592.5-82592.29" + switch \initial + attribute \src "issuer_ls180.v:82592.9-82592.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub0_cr_in[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub0_cr_in[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub0_cr_in[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub0_cr_in[2:0] 3'011 + case + assign $1\dec31_dec_sub0_cr_in[2:0] 3'000 + end + sync always + update \dec31_dec_sub0_cr_in $0\dec31_dec_sub0_cr_in[2:0] + end + attribute \src "issuer_ls180.v:82610.3-82628.6" + process $proc$issuer_ls180.v:82610$3619 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub0_cr_out[2:0] $1\dec31_dec_sub0_cr_out[2:0] + attribute \src "issuer_ls180.v:82611.5-82611.29" + switch \initial + attribute \src "issuer_ls180.v:82611.9-82611.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub0_cr_out[2:0] 3'010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub0_cr_out[2:0] 3'010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub0_cr_out[2:0] 3'010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub0_cr_out[2:0] 3'000 + case + assign $1\dec31_dec_sub0_cr_out[2:0] 3'000 + end + sync always + update \dec31_dec_sub0_cr_out $0\dec31_dec_sub0_cr_out[2:0] + end + connect \opcode_switch \opcode_in [10:6] +end +attribute \src "issuer_ls180.v:82634.1-83781.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.dec2.dec.dec31.dec31_dec_sub10" +attribute \generator "nMigen" +module \dec31_dec_sub10 + attribute \src "issuer_ls180.v:83077.3-83113.6" + wire width 8 $0\dec31_dec_sub10_asmcode[7:0] + attribute \src "issuer_ls180.v:83225.3-83261.6" + wire $0\dec31_dec_sub10_br[0:0] + attribute \src "issuer_ls180.v:83706.3-83742.6" + wire width 3 $0\dec31_dec_sub10_cr_in[2:0] + attribute \src "issuer_ls180.v:83743.3-83779.6" + wire width 3 $0\dec31_dec_sub10_cr_out[2:0] + attribute \src "issuer_ls180.v:83040.3-83076.6" + wire width 2 $0\dec31_dec_sub10_cry_in[1:0] + attribute \src "issuer_ls180.v:83188.3-83224.6" + wire $0\dec31_dec_sub10_cry_out[0:0] + attribute \src "issuer_ls180.v:83521.3-83557.6" + wire width 5 $0\dec31_dec_sub10_form[4:0] + attribute \src "issuer_ls180.v:82892.3-82928.6" + wire width 12 $0\dec31_dec_sub10_function_unit[11:0] + attribute \src "issuer_ls180.v:83558.3-83594.6" + wire width 3 $0\dec31_dec_sub10_in1_sel[2:0] + attribute \src "issuer_ls180.v:83595.3-83631.6" + wire width 4 $0\dec31_dec_sub10_in2_sel[3:0] + attribute \src "issuer_ls180.v:83632.3-83668.6" + wire width 2 $0\dec31_dec_sub10_in3_sel[1:0] + attribute \src "issuer_ls180.v:83299.3-83335.6" + wire width 7 $0\dec31_dec_sub10_internal_op[6:0] + attribute \src "issuer_ls180.v:83114.3-83150.6" + wire $0\dec31_dec_sub10_inv_a[0:0] + attribute \src "issuer_ls180.v:83151.3-83187.6" + wire $0\dec31_dec_sub10_inv_out[0:0] + attribute \src "issuer_ls180.v:83373.3-83409.6" + wire $0\dec31_dec_sub10_is_32b[0:0] + attribute \src "issuer_ls180.v:82929.3-82965.6" + wire width 4 $0\dec31_dec_sub10_ldst_len[3:0] + attribute \src "issuer_ls180.v:83447.3-83483.6" + wire $0\dec31_dec_sub10_lk[0:0] + attribute \src "issuer_ls180.v:83669.3-83705.6" + wire width 2 $0\dec31_dec_sub10_out_sel[1:0] + attribute \src "issuer_ls180.v:83003.3-83039.6" + wire width 2 $0\dec31_dec_sub10_rc_sel[1:0] + attribute \src "issuer_ls180.v:83336.3-83372.6" + wire $0\dec31_dec_sub10_rsrv[0:0] + attribute \src "issuer_ls180.v:83484.3-83520.6" + wire $0\dec31_dec_sub10_sgl_pipe[0:0] + attribute \src "issuer_ls180.v:83410.3-83446.6" + wire $0\dec31_dec_sub10_sgn[0:0] + attribute \src "issuer_ls180.v:83262.3-83298.6" + wire $0\dec31_dec_sub10_sgn_ext[0:0] + attribute \src "issuer_ls180.v:82966.3-83002.6" + wire width 2 $0\dec31_dec_sub10_upd[1:0] + attribute \src "issuer_ls180.v:82635.7-82635.20" + wire $0\initial[0:0] + attribute \src "issuer_ls180.v:83077.3-83113.6" + wire width 8 $1\dec31_dec_sub10_asmcode[7:0] + attribute \src "issuer_ls180.v:83225.3-83261.6" + wire $1\dec31_dec_sub10_br[0:0] + attribute \src "issuer_ls180.v:83706.3-83742.6" + wire width 3 $1\dec31_dec_sub10_cr_in[2:0] + attribute \src "issuer_ls180.v:83743.3-83779.6" + wire width 3 $1\dec31_dec_sub10_cr_out[2:0] + attribute \src "issuer_ls180.v:83040.3-83076.6" + wire width 2 $1\dec31_dec_sub10_cry_in[1:0] + attribute \src "issuer_ls180.v:83188.3-83224.6" + wire $1\dec31_dec_sub10_cry_out[0:0] + attribute \src "issuer_ls180.v:83521.3-83557.6" + wire width 5 $1\dec31_dec_sub10_form[4:0] + attribute \src "issuer_ls180.v:82892.3-82928.6" + wire width 12 $1\dec31_dec_sub10_function_unit[11:0] + attribute \src "issuer_ls180.v:83558.3-83594.6" + wire width 3 $1\dec31_dec_sub10_in1_sel[2:0] + attribute \src "issuer_ls180.v:83595.3-83631.6" + wire width 4 $1\dec31_dec_sub10_in2_sel[3:0] + attribute \src "issuer_ls180.v:83632.3-83668.6" + wire width 2 $1\dec31_dec_sub10_in3_sel[1:0] + attribute \src "issuer_ls180.v:83299.3-83335.6" + wire width 7 $1\dec31_dec_sub10_internal_op[6:0] + attribute \src "issuer_ls180.v:83114.3-83150.6" + wire $1\dec31_dec_sub10_inv_a[0:0] + attribute \src "issuer_ls180.v:83151.3-83187.6" + wire $1\dec31_dec_sub10_inv_out[0:0] + attribute \src "issuer_ls180.v:83373.3-83409.6" + wire $1\dec31_dec_sub10_is_32b[0:0] + attribute \src "issuer_ls180.v:82929.3-82965.6" + wire width 4 $1\dec31_dec_sub10_ldst_len[3:0] + attribute \src "issuer_ls180.v:83447.3-83483.6" + wire $1\dec31_dec_sub10_lk[0:0] + attribute \src "issuer_ls180.v:83669.3-83705.6" + wire width 2 $1\dec31_dec_sub10_out_sel[1:0] + attribute \src "issuer_ls180.v:83003.3-83039.6" + wire width 2 $1\dec31_dec_sub10_rc_sel[1:0] + attribute \src "issuer_ls180.v:83336.3-83372.6" + wire $1\dec31_dec_sub10_rsrv[0:0] + attribute \src "issuer_ls180.v:83484.3-83520.6" + wire $1\dec31_dec_sub10_sgl_pipe[0:0] + attribute \src "issuer_ls180.v:83410.3-83446.6" + wire $1\dec31_dec_sub10_sgn[0:0] + attribute \src "issuer_ls180.v:83262.3-83298.6" + wire $1\dec31_dec_sub10_sgn_ext[0:0] + attribute \src "issuer_ls180.v:82966.3-83002.6" + wire width 2 $1\dec31_dec_sub10_upd[1:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 8 output 4 \dec31_dec_sub10_asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 18 \dec31_dec_sub10_br + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 9 \dec31_dec_sub10_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 10 \dec31_dec_sub10_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 14 \dec31_dec_sub10_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 17 \dec31_dec_sub10_cry_out + attribute \enum_base_type "Form" + attribute \enum_value_00000 "NONE" + attribute \enum_value_00001 "I" + attribute \enum_value_00010 "B" + attribute \enum_value_00011 "SC" + attribute \enum_value_00100 "D" + attribute \enum_value_00101 "DS" + attribute \enum_value_00110 "DQ" + attribute \enum_value_00111 "DX" + attribute \enum_value_01000 "X" + attribute \enum_value_01001 "XL" + attribute \enum_value_01010 "XFX" + attribute \enum_value_01011 "XFL" + attribute \enum_value_01100 "XX1" + attribute \enum_value_01101 "XX2" + attribute \enum_value_01110 "XX3" + attribute \enum_value_01111 "XX4" + attribute \enum_value_10000 "XS" + attribute \enum_value_10001 "XO" + attribute \enum_value_10010 "A" + attribute \enum_value_10011 "M" + attribute \enum_value_10100 "MD" + attribute \enum_value_10101 "MDS" + attribute \enum_value_10110 "VA" + attribute \enum_value_10111 "VC" + attribute \enum_value_11000 "VX" + attribute \enum_value_11001 "EVX" + attribute \enum_value_11010 "EVS" + attribute \enum_value_11011 "Z22" + attribute \enum_value_11100 "Z23" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 5 output 3 \dec31_dec_sub10_form + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 12 output 1 \dec31_dec_sub10_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 5 \dec31_dec_sub10_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 output 6 \dec31_dec_sub10_in2_sel + attribute \enum_base_type "In3Sel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RS" + attribute \enum_value_10 "RB" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 7 \dec31_dec_sub10_in3_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 7 output 2 \dec31_dec_sub10_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 15 \dec31_dec_sub10_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 16 \dec31_dec_sub10_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 21 \dec31_dec_sub10_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 output 11 \dec31_dec_sub10_ldst_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 23 \dec31_dec_sub10_lk + attribute \enum_base_type "OutSel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RT" + attribute \enum_value_10 "RA" + attribute \enum_value_11 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 8 \dec31_dec_sub10_out_sel + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 13 \dec31_dec_sub10_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 20 \dec31_dec_sub10_rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 24 \dec31_dec_sub10_sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 22 \dec31_dec_sub10_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 19 \dec31_dec_sub10_sgn_ext + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 12 \dec31_dec_sub10_upd + attribute \src "issuer_ls180.v:82635.7-82635.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + wire width 32 input 25 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:320" + wire width 5 \opcode_switch + attribute \src "issuer_ls180.v:82635.7-82635.20" + process $proc$issuer_ls180.v:82635$3645 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "issuer_ls180.v:82892.3-82928.6" + process $proc$issuer_ls180.v:82892$3621 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub10_function_unit[11:0] $1\dec31_dec_sub10_function_unit[11:0] + attribute \src "issuer_ls180.v:82893.5-82893.29" + switch \initial + attribute \src "issuer_ls180.v:82893.9-82893.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub10_function_unit[11:0] 12'000000000010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub10_function_unit[11:0] 12'000000000010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub10_function_unit[11:0] 12'000000000010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub10_function_unit[11:0] 12'000000000010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub10_function_unit[11:0] 12'000000000010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub10_function_unit[11:0] 12'000000000010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub10_function_unit[11:0] 12'000000000010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub10_function_unit[11:0] 12'000000000010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub10_function_unit[11:0] 12'000000000010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub10_function_unit[11:0] 12'000000000010 + case + assign $1\dec31_dec_sub10_function_unit[11:0] 12'000000000000 + end + sync always + update \dec31_dec_sub10_function_unit $0\dec31_dec_sub10_function_unit[11:0] + end + attribute \src "issuer_ls180.v:82929.3-82965.6" + process $proc$issuer_ls180.v:82929$3622 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub10_ldst_len[3:0] $1\dec31_dec_sub10_ldst_len[3:0] + attribute \src "issuer_ls180.v:82930.5-82930.29" + switch \initial + attribute \src "issuer_ls180.v:82930.9-82930.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub10_ldst_len[3:0] 4'0000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub10_ldst_len[3:0] 4'0000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub10_ldst_len[3:0] 4'0000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub10_ldst_len[3:0] 4'0000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub10_ldst_len[3:0] 4'0000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub10_ldst_len[3:0] 4'0000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub10_ldst_len[3:0] 4'0000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub10_ldst_len[3:0] 4'0000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub10_ldst_len[3:0] 4'0000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub10_ldst_len[3:0] 4'0000 + case + assign $1\dec31_dec_sub10_ldst_len[3:0] 4'0000 + end + sync always + update \dec31_dec_sub10_ldst_len $0\dec31_dec_sub10_ldst_len[3:0] + end + attribute \src "issuer_ls180.v:82966.3-83002.6" + process $proc$issuer_ls180.v:82966$3623 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub10_upd[1:0] $1\dec31_dec_sub10_upd[1:0] + attribute \src "issuer_ls180.v:82967.5-82967.29" + switch \initial + attribute \src "issuer_ls180.v:82967.9-82967.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub10_upd[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub10_upd[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub10_upd[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub10_upd[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub10_upd[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub10_upd[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub10_upd[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub10_upd[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub10_upd[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub10_upd[1:0] 2'00 + case + assign $1\dec31_dec_sub10_upd[1:0] 2'00 + end + sync always + update \dec31_dec_sub10_upd $0\dec31_dec_sub10_upd[1:0] + end + attribute \src "issuer_ls180.v:83003.3-83039.6" + process $proc$issuer_ls180.v:83003$3624 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub10_rc_sel[1:0] $1\dec31_dec_sub10_rc_sel[1:0] + attribute \src "issuer_ls180.v:83004.5-83004.29" + switch \initial + attribute \src "issuer_ls180.v:83004.9-83004.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub10_rc_sel[1:0] 2'10 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub10_rc_sel[1:0] 2'10 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub10_rc_sel[1:0] 2'10 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub10_rc_sel[1:0] 2'10 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub10_rc_sel[1:0] 2'10 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub10_rc_sel[1:0] 2'10 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub10_rc_sel[1:0] 2'10 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub10_rc_sel[1:0] 2'10 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub10_rc_sel[1:0] 2'10 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub10_rc_sel[1:0] 2'10 + case + assign $1\dec31_dec_sub10_rc_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub10_rc_sel $0\dec31_dec_sub10_rc_sel[1:0] + end + attribute \src "issuer_ls180.v:83040.3-83076.6" + process $proc$issuer_ls180.v:83040$3625 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub10_cry_in[1:0] $1\dec31_dec_sub10_cry_in[1:0] + attribute \src "issuer_ls180.v:83041.5-83041.29" + switch \initial + attribute \src "issuer_ls180.v:83041.9-83041.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub10_cry_in[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub10_cry_in[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub10_cry_in[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub10_cry_in[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub10_cry_in[1:0] 2'10 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub10_cry_in[1:0] 2'10 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub10_cry_in[1:0] 2'10 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub10_cry_in[1:0] 2'10 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub10_cry_in[1:0] 2'10 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub10_cry_in[1:0] 2'10 + case + assign $1\dec31_dec_sub10_cry_in[1:0] 2'00 + end + sync always + update \dec31_dec_sub10_cry_in $0\dec31_dec_sub10_cry_in[1:0] + end + attribute \src "issuer_ls180.v:83077.3-83113.6" + process $proc$issuer_ls180.v:83077$3626 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub10_asmcode[7:0] $1\dec31_dec_sub10_asmcode[7:0] + attribute \src "issuer_ls180.v:83078.5-83078.29" + switch \initial + attribute \src "issuer_ls180.v:83078.9-83078.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub10_asmcode[7:0] 8'00000001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub10_asmcode[7:0] 8'00001100 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub10_asmcode[7:0] 8'00000010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub10_asmcode[7:0] 8'00000011 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub10_asmcode[7:0] 8'00000100 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub10_asmcode[7:0] 8'00000101 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub10_asmcode[7:0] 8'00001010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub10_asmcode[7:0] 8'00001011 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub10_asmcode[7:0] 8'00001101 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub10_asmcode[7:0] 8'00001110 + case + assign $1\dec31_dec_sub10_asmcode[7:0] 8'00000000 + end + sync always + update \dec31_dec_sub10_asmcode $0\dec31_dec_sub10_asmcode[7:0] + end + attribute \src "issuer_ls180.v:83114.3-83150.6" + process $proc$issuer_ls180.v:83114$3627 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub10_inv_a[0:0] $1\dec31_dec_sub10_inv_a[0:0] + attribute \src "issuer_ls180.v:83115.5-83115.29" + switch \initial + attribute \src "issuer_ls180.v:83115.9-83115.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub10_inv_a[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub10_inv_a[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub10_inv_a[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub10_inv_a[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub10_inv_a[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub10_inv_a[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub10_inv_a[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub10_inv_a[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub10_inv_a[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub10_inv_a[0:0] 1'0 + case + assign $1\dec31_dec_sub10_inv_a[0:0] 1'0 + end + sync always + update \dec31_dec_sub10_inv_a $0\dec31_dec_sub10_inv_a[0:0] + end + attribute \src "issuer_ls180.v:83151.3-83187.6" + process $proc$issuer_ls180.v:83151$3628 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub10_inv_out[0:0] $1\dec31_dec_sub10_inv_out[0:0] + attribute \src "issuer_ls180.v:83152.5-83152.29" + switch \initial + attribute \src "issuer_ls180.v:83152.9-83152.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub10_inv_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub10_inv_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub10_inv_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub10_inv_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub10_inv_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub10_inv_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub10_inv_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub10_inv_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub10_inv_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub10_inv_out[0:0] 1'0 + case + assign $1\dec31_dec_sub10_inv_out[0:0] 1'0 + end + sync always + update \dec31_dec_sub10_inv_out $0\dec31_dec_sub10_inv_out[0:0] + end + attribute \src "issuer_ls180.v:83188.3-83224.6" + process $proc$issuer_ls180.v:83188$3629 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub10_cry_out[0:0] $1\dec31_dec_sub10_cry_out[0:0] + attribute \src "issuer_ls180.v:83189.5-83189.29" + switch \initial + attribute \src "issuer_ls180.v:83189.9-83189.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub10_cry_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub10_cry_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub10_cry_out[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub10_cry_out[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub10_cry_out[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub10_cry_out[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub10_cry_out[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub10_cry_out[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub10_cry_out[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub10_cry_out[0:0] 1'1 + case + assign $1\dec31_dec_sub10_cry_out[0:0] 1'0 + end + sync always + update \dec31_dec_sub10_cry_out $0\dec31_dec_sub10_cry_out[0:0] + end + attribute \src "issuer_ls180.v:83225.3-83261.6" + process $proc$issuer_ls180.v:83225$3630 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub10_br[0:0] $1\dec31_dec_sub10_br[0:0] + attribute \src "issuer_ls180.v:83226.5-83226.29" + switch \initial + attribute \src "issuer_ls180.v:83226.9-83226.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub10_br[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub10_br[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub10_br[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub10_br[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub10_br[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub10_br[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub10_br[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub10_br[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub10_br[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub10_br[0:0] 1'0 + case + assign $1\dec31_dec_sub10_br[0:0] 1'0 + end + sync always + update \dec31_dec_sub10_br $0\dec31_dec_sub10_br[0:0] + end + attribute \src "issuer_ls180.v:83262.3-83298.6" + process $proc$issuer_ls180.v:83262$3631 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub10_sgn_ext[0:0] $1\dec31_dec_sub10_sgn_ext[0:0] + attribute \src "issuer_ls180.v:83263.5-83263.29" + switch \initial + attribute \src "issuer_ls180.v:83263.9-83263.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub10_sgn_ext[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub10_sgn_ext[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub10_sgn_ext[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub10_sgn_ext[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub10_sgn_ext[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub10_sgn_ext[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub10_sgn_ext[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub10_sgn_ext[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub10_sgn_ext[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub10_sgn_ext[0:0] 1'0 + case + assign $1\dec31_dec_sub10_sgn_ext[0:0] 1'0 + end + sync always + update \dec31_dec_sub10_sgn_ext $0\dec31_dec_sub10_sgn_ext[0:0] + end + attribute \src "issuer_ls180.v:83299.3-83335.6" + process $proc$issuer_ls180.v:83299$3632 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub10_internal_op[6:0] $1\dec31_dec_sub10_internal_op[6:0] + attribute \src "issuer_ls180.v:83300.5-83300.29" + switch \initial + attribute \src "issuer_ls180.v:83300.9-83300.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub10_internal_op[6:0] 7'0000010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub10_internal_op[6:0] 7'0000010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub10_internal_op[6:0] 7'0000010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub10_internal_op[6:0] 7'0000010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub10_internal_op[6:0] 7'0000010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub10_internal_op[6:0] 7'0000010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub10_internal_op[6:0] 7'0000010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub10_internal_op[6:0] 7'0000010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub10_internal_op[6:0] 7'0000010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub10_internal_op[6:0] 7'0000010 + case + assign $1\dec31_dec_sub10_internal_op[6:0] 7'0000000 + end + sync always + update \dec31_dec_sub10_internal_op $0\dec31_dec_sub10_internal_op[6:0] + end + attribute \src "issuer_ls180.v:83336.3-83372.6" + process $proc$issuer_ls180.v:83336$3633 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub10_rsrv[0:0] $1\dec31_dec_sub10_rsrv[0:0] + attribute \src "issuer_ls180.v:83337.5-83337.29" + switch \initial + attribute \src "issuer_ls180.v:83337.9-83337.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub10_rsrv[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub10_rsrv[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub10_rsrv[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub10_rsrv[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub10_rsrv[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub10_rsrv[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub10_rsrv[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub10_rsrv[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub10_rsrv[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub10_rsrv[0:0] 1'0 + case + assign $1\dec31_dec_sub10_rsrv[0:0] 1'0 + end + sync always + update \dec31_dec_sub10_rsrv $0\dec31_dec_sub10_rsrv[0:0] + end + attribute \src "issuer_ls180.v:83373.3-83409.6" + process $proc$issuer_ls180.v:83373$3634 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub10_is_32b[0:0] $1\dec31_dec_sub10_is_32b[0:0] + attribute \src "issuer_ls180.v:83374.5-83374.29" + switch \initial + attribute \src "issuer_ls180.v:83374.9-83374.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub10_is_32b[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub10_is_32b[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub10_is_32b[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub10_is_32b[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub10_is_32b[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub10_is_32b[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub10_is_32b[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub10_is_32b[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub10_is_32b[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub10_is_32b[0:0] 1'0 + case + assign $1\dec31_dec_sub10_is_32b[0:0] 1'0 + end + sync always + update \dec31_dec_sub10_is_32b $0\dec31_dec_sub10_is_32b[0:0] + end + attribute \src "issuer_ls180.v:83410.3-83446.6" + process $proc$issuer_ls180.v:83410$3635 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub10_sgn[0:0] $1\dec31_dec_sub10_sgn[0:0] + attribute \src "issuer_ls180.v:83411.5-83411.29" + switch \initial + attribute \src "issuer_ls180.v:83411.9-83411.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub10_sgn[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub10_sgn[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub10_sgn[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub10_sgn[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub10_sgn[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub10_sgn[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub10_sgn[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub10_sgn[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub10_sgn[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub10_sgn[0:0] 1'0 + case + assign $1\dec31_dec_sub10_sgn[0:0] 1'0 + end + sync always + update \dec31_dec_sub10_sgn $0\dec31_dec_sub10_sgn[0:0] + end + attribute \src "issuer_ls180.v:83447.3-83483.6" + process $proc$issuer_ls180.v:83447$3636 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub10_lk[0:0] $1\dec31_dec_sub10_lk[0:0] + attribute \src "issuer_ls180.v:83448.5-83448.29" + switch \initial + attribute \src "issuer_ls180.v:83448.9-83448.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub10_lk[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub10_lk[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub10_lk[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub10_lk[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub10_lk[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub10_lk[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub10_lk[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub10_lk[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub10_lk[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub10_lk[0:0] 1'0 + case + assign $1\dec31_dec_sub10_lk[0:0] 1'0 + end + sync always + update \dec31_dec_sub10_lk $0\dec31_dec_sub10_lk[0:0] + end + attribute \src "issuer_ls180.v:83484.3-83520.6" + process $proc$issuer_ls180.v:83484$3637 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub10_sgl_pipe[0:0] $1\dec31_dec_sub10_sgl_pipe[0:0] + attribute \src "issuer_ls180.v:83485.5-83485.29" + switch \initial + attribute \src "issuer_ls180.v:83485.9-83485.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub10_sgl_pipe[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub10_sgl_pipe[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub10_sgl_pipe[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub10_sgl_pipe[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub10_sgl_pipe[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub10_sgl_pipe[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub10_sgl_pipe[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub10_sgl_pipe[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub10_sgl_pipe[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub10_sgl_pipe[0:0] 1'0 + case + assign $1\dec31_dec_sub10_sgl_pipe[0:0] 1'0 + end + sync always + update \dec31_dec_sub10_sgl_pipe $0\dec31_dec_sub10_sgl_pipe[0:0] + end + attribute \src "issuer_ls180.v:83521.3-83557.6" + process $proc$issuer_ls180.v:83521$3638 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub10_form[4:0] $1\dec31_dec_sub10_form[4:0] + attribute \src "issuer_ls180.v:83522.5-83522.29" + switch \initial + attribute \src "issuer_ls180.v:83522.9-83522.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub10_form[4:0] 5'10001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub10_form[4:0] 5'10001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub10_form[4:0] 5'10001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub10_form[4:0] 5'10001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub10_form[4:0] 5'10001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub10_form[4:0] 5'10001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub10_form[4:0] 5'10001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub10_form[4:0] 5'10001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub10_form[4:0] 5'10001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub10_form[4:0] 5'10001 + case + assign $1\dec31_dec_sub10_form[4:0] 5'00000 + end + sync always + update \dec31_dec_sub10_form $0\dec31_dec_sub10_form[4:0] + end + attribute \src "issuer_ls180.v:83558.3-83594.6" + process $proc$issuer_ls180.v:83558$3639 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub10_in1_sel[2:0] $1\dec31_dec_sub10_in1_sel[2:0] + attribute \src "issuer_ls180.v:83559.5-83559.29" + switch \initial + attribute \src "issuer_ls180.v:83559.9-83559.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub10_in1_sel[2:0] 3'001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub10_in1_sel[2:0] 3'001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub10_in1_sel[2:0] 3'001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub10_in1_sel[2:0] 3'001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub10_in1_sel[2:0] 3'001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub10_in1_sel[2:0] 3'001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub10_in1_sel[2:0] 3'001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub10_in1_sel[2:0] 3'001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub10_in1_sel[2:0] 3'001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub10_in1_sel[2:0] 3'001 + case + assign $1\dec31_dec_sub10_in1_sel[2:0] 3'000 + end + sync always + update \dec31_dec_sub10_in1_sel $0\dec31_dec_sub10_in1_sel[2:0] + end + attribute \src "issuer_ls180.v:83595.3-83631.6" + process $proc$issuer_ls180.v:83595$3640 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub10_in2_sel[3:0] $1\dec31_dec_sub10_in2_sel[3:0] + attribute \src "issuer_ls180.v:83596.5-83596.29" + switch \initial + attribute \src "issuer_ls180.v:83596.9-83596.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub10_in2_sel[3:0] 4'0001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub10_in2_sel[3:0] 4'0001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub10_in2_sel[3:0] 4'0001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub10_in2_sel[3:0] 4'0001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub10_in2_sel[3:0] 4'0001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub10_in2_sel[3:0] 4'0001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub10_in2_sel[3:0] 4'1001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub10_in2_sel[3:0] 4'1001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub10_in2_sel[3:0] 4'0000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub10_in2_sel[3:0] 4'0000 + case + assign $1\dec31_dec_sub10_in2_sel[3:0] 4'0000 + end + sync always + update \dec31_dec_sub10_in2_sel $0\dec31_dec_sub10_in2_sel[3:0] + end + attribute \src "issuer_ls180.v:83632.3-83668.6" + process $proc$issuer_ls180.v:83632$3641 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub10_in3_sel[1:0] $1\dec31_dec_sub10_in3_sel[1:0] + attribute \src "issuer_ls180.v:83633.5-83633.29" + switch \initial + attribute \src "issuer_ls180.v:83633.9-83633.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub10_in3_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub10_in3_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub10_in3_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub10_in3_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub10_in3_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub10_in3_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub10_in3_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub10_in3_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub10_in3_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub10_in3_sel[1:0] 2'00 + case + assign $1\dec31_dec_sub10_in3_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub10_in3_sel $0\dec31_dec_sub10_in3_sel[1:0] + end + attribute \src "issuer_ls180.v:83669.3-83705.6" + process $proc$issuer_ls180.v:83669$3642 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub10_out_sel[1:0] $1\dec31_dec_sub10_out_sel[1:0] + attribute \src "issuer_ls180.v:83670.5-83670.29" + switch \initial + attribute \src "issuer_ls180.v:83670.9-83670.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub10_out_sel[1:0] 2'01 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub10_out_sel[1:0] 2'01 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub10_out_sel[1:0] 2'01 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub10_out_sel[1:0] 2'01 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub10_out_sel[1:0] 2'01 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub10_out_sel[1:0] 2'01 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub10_out_sel[1:0] 2'01 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub10_out_sel[1:0] 2'01 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub10_out_sel[1:0] 2'01 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub10_out_sel[1:0] 2'01 + case + assign $1\dec31_dec_sub10_out_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub10_out_sel $0\dec31_dec_sub10_out_sel[1:0] + end + attribute \src "issuer_ls180.v:83706.3-83742.6" + process $proc$issuer_ls180.v:83706$3643 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub10_cr_in[2:0] $1\dec31_dec_sub10_cr_in[2:0] + attribute \src "issuer_ls180.v:83707.5-83707.29" + switch \initial + attribute \src "issuer_ls180.v:83707.9-83707.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub10_cr_in[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub10_cr_in[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub10_cr_in[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub10_cr_in[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub10_cr_in[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub10_cr_in[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub10_cr_in[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub10_cr_in[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub10_cr_in[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub10_cr_in[2:0] 3'000 + case + assign $1\dec31_dec_sub10_cr_in[2:0] 3'000 + end + sync always + update \dec31_dec_sub10_cr_in $0\dec31_dec_sub10_cr_in[2:0] + end + attribute \src "issuer_ls180.v:83743.3-83779.6" + process $proc$issuer_ls180.v:83743$3644 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub10_cr_out[2:0] $1\dec31_dec_sub10_cr_out[2:0] + attribute \src "issuer_ls180.v:83744.5-83744.29" + switch \initial + attribute \src "issuer_ls180.v:83744.9-83744.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub10_cr_out[2:0] 3'001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub10_cr_out[2:0] 3'001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub10_cr_out[2:0] 3'001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub10_cr_out[2:0] 3'001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub10_cr_out[2:0] 3'001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub10_cr_out[2:0] 3'001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub10_cr_out[2:0] 3'001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub10_cr_out[2:0] 3'001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub10_cr_out[2:0] 3'001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub10_cr_out[2:0] 3'001 + case + assign $1\dec31_dec_sub10_cr_out[2:0] 3'000 + end + sync always + update \dec31_dec_sub10_cr_out $0\dec31_dec_sub10_cr_out[2:0] + end + connect \opcode_switch \opcode_in [10:6] +end +attribute \src "issuer_ls180.v:83785.1-85364.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.dec2.dec.dec31.dec31_dec_sub11" +attribute \generator "nMigen" +module \dec31_dec_sub11 + attribute \src "issuer_ls180.v:84318.3-84372.6" + wire width 8 $0\dec31_dec_sub11_asmcode[7:0] + attribute \src "issuer_ls180.v:84538.3-84592.6" + wire $0\dec31_dec_sub11_br[0:0] + attribute \src "issuer_ls180.v:85253.3-85307.6" + wire width 3 $0\dec31_dec_sub11_cr_in[2:0] + attribute \src "issuer_ls180.v:85308.3-85362.6" + wire width 3 $0\dec31_dec_sub11_cr_out[2:0] + attribute \src "issuer_ls180.v:84263.3-84317.6" + wire width 2 $0\dec31_dec_sub11_cry_in[1:0] + attribute \src "issuer_ls180.v:84483.3-84537.6" + wire $0\dec31_dec_sub11_cry_out[0:0] + attribute \src "issuer_ls180.v:84978.3-85032.6" + wire width 5 $0\dec31_dec_sub11_form[4:0] + attribute \src "issuer_ls180.v:84043.3-84097.6" + wire width 12 $0\dec31_dec_sub11_function_unit[11:0] + attribute \src "issuer_ls180.v:85033.3-85087.6" + wire width 3 $0\dec31_dec_sub11_in1_sel[2:0] + attribute \src "issuer_ls180.v:85088.3-85142.6" + wire width 4 $0\dec31_dec_sub11_in2_sel[3:0] + attribute \src "issuer_ls180.v:85143.3-85197.6" + wire width 2 $0\dec31_dec_sub11_in3_sel[1:0] + attribute \src "issuer_ls180.v:84648.3-84702.6" + wire width 7 $0\dec31_dec_sub11_internal_op[6:0] + attribute \src "issuer_ls180.v:84373.3-84427.6" + wire $0\dec31_dec_sub11_inv_a[0:0] + attribute \src "issuer_ls180.v:84428.3-84482.6" + wire $0\dec31_dec_sub11_inv_out[0:0] + attribute \src "issuer_ls180.v:84758.3-84812.6" + wire $0\dec31_dec_sub11_is_32b[0:0] + attribute \src "issuer_ls180.v:84098.3-84152.6" + wire width 4 $0\dec31_dec_sub11_ldst_len[3:0] + attribute \src "issuer_ls180.v:84868.3-84922.6" + wire $0\dec31_dec_sub11_lk[0:0] + attribute \src "issuer_ls180.v:85198.3-85252.6" + wire width 2 $0\dec31_dec_sub11_out_sel[1:0] + attribute \src "issuer_ls180.v:84208.3-84262.6" + wire width 2 $0\dec31_dec_sub11_rc_sel[1:0] + attribute \src "issuer_ls180.v:84703.3-84757.6" + wire $0\dec31_dec_sub11_rsrv[0:0] + attribute \src "issuer_ls180.v:84923.3-84977.6" + wire $0\dec31_dec_sub11_sgl_pipe[0:0] + attribute \src "issuer_ls180.v:84813.3-84867.6" + wire $0\dec31_dec_sub11_sgn[0:0] + attribute \src "issuer_ls180.v:84593.3-84647.6" + wire $0\dec31_dec_sub11_sgn_ext[0:0] + attribute \src "issuer_ls180.v:84153.3-84207.6" + wire width 2 $0\dec31_dec_sub11_upd[1:0] + attribute \src "issuer_ls180.v:83786.7-83786.20" + wire $0\initial[0:0] + attribute \src "issuer_ls180.v:84318.3-84372.6" + wire width 8 $1\dec31_dec_sub11_asmcode[7:0] + attribute \src "issuer_ls180.v:84538.3-84592.6" + wire $1\dec31_dec_sub11_br[0:0] + attribute \src "issuer_ls180.v:85253.3-85307.6" + wire width 3 $1\dec31_dec_sub11_cr_in[2:0] + attribute \src "issuer_ls180.v:85308.3-85362.6" + wire width 3 $1\dec31_dec_sub11_cr_out[2:0] + attribute \src "issuer_ls180.v:84263.3-84317.6" + wire width 2 $1\dec31_dec_sub11_cry_in[1:0] + attribute \src "issuer_ls180.v:84483.3-84537.6" + wire $1\dec31_dec_sub11_cry_out[0:0] + attribute \src "issuer_ls180.v:84978.3-85032.6" + wire width 5 $1\dec31_dec_sub11_form[4:0] + attribute \src "issuer_ls180.v:84043.3-84097.6" + wire width 12 $1\dec31_dec_sub11_function_unit[11:0] + attribute \src "issuer_ls180.v:85033.3-85087.6" + wire width 3 $1\dec31_dec_sub11_in1_sel[2:0] + attribute \src "issuer_ls180.v:85088.3-85142.6" + wire width 4 $1\dec31_dec_sub11_in2_sel[3:0] + attribute \src "issuer_ls180.v:85143.3-85197.6" + wire width 2 $1\dec31_dec_sub11_in3_sel[1:0] + attribute \src "issuer_ls180.v:84648.3-84702.6" + wire width 7 $1\dec31_dec_sub11_internal_op[6:0] + attribute \src "issuer_ls180.v:84373.3-84427.6" + wire $1\dec31_dec_sub11_inv_a[0:0] + attribute \src "issuer_ls180.v:84428.3-84482.6" + wire $1\dec31_dec_sub11_inv_out[0:0] + attribute \src "issuer_ls180.v:84758.3-84812.6" + wire $1\dec31_dec_sub11_is_32b[0:0] + attribute \src "issuer_ls180.v:84098.3-84152.6" + wire width 4 $1\dec31_dec_sub11_ldst_len[3:0] + attribute \src "issuer_ls180.v:84868.3-84922.6" + wire $1\dec31_dec_sub11_lk[0:0] + attribute \src "issuer_ls180.v:85198.3-85252.6" + wire width 2 $1\dec31_dec_sub11_out_sel[1:0] + attribute \src "issuer_ls180.v:84208.3-84262.6" + wire width 2 $1\dec31_dec_sub11_rc_sel[1:0] + attribute \src "issuer_ls180.v:84703.3-84757.6" + wire $1\dec31_dec_sub11_rsrv[0:0] + attribute \src "issuer_ls180.v:84923.3-84977.6" + wire $1\dec31_dec_sub11_sgl_pipe[0:0] + attribute \src "issuer_ls180.v:84813.3-84867.6" + wire $1\dec31_dec_sub11_sgn[0:0] + attribute \src "issuer_ls180.v:84593.3-84647.6" + wire $1\dec31_dec_sub11_sgn_ext[0:0] + attribute \src "issuer_ls180.v:84153.3-84207.6" + wire width 2 $1\dec31_dec_sub11_upd[1:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 8 output 4 \dec31_dec_sub11_asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 18 \dec31_dec_sub11_br + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 9 \dec31_dec_sub11_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 10 \dec31_dec_sub11_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 14 \dec31_dec_sub11_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 17 \dec31_dec_sub11_cry_out + attribute \enum_base_type "Form" + attribute \enum_value_00000 "NONE" + attribute \enum_value_00001 "I" + attribute \enum_value_00010 "B" + attribute \enum_value_00011 "SC" + attribute \enum_value_00100 "D" + attribute \enum_value_00101 "DS" + attribute \enum_value_00110 "DQ" + attribute \enum_value_00111 "DX" + attribute \enum_value_01000 "X" + attribute \enum_value_01001 "XL" + attribute \enum_value_01010 "XFX" + attribute \enum_value_01011 "XFL" + attribute \enum_value_01100 "XX1" + attribute \enum_value_01101 "XX2" + attribute \enum_value_01110 "XX3" + attribute \enum_value_01111 "XX4" + attribute \enum_value_10000 "XS" + attribute \enum_value_10001 "XO" + attribute \enum_value_10010 "A" + attribute \enum_value_10011 "M" + attribute \enum_value_10100 "MD" + attribute \enum_value_10101 "MDS" + attribute \enum_value_10110 "VA" + attribute \enum_value_10111 "VC" + attribute \enum_value_11000 "VX" + attribute \enum_value_11001 "EVX" + attribute \enum_value_11010 "EVS" + attribute \enum_value_11011 "Z22" + attribute \enum_value_11100 "Z23" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 5 output 3 \dec31_dec_sub11_form + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 12 output 1 \dec31_dec_sub11_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 5 \dec31_dec_sub11_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 output 6 \dec31_dec_sub11_in2_sel + attribute \enum_base_type "In3Sel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RS" + attribute \enum_value_10 "RB" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 7 \dec31_dec_sub11_in3_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 7 output 2 \dec31_dec_sub11_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 15 \dec31_dec_sub11_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 16 \dec31_dec_sub11_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 21 \dec31_dec_sub11_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 output 11 \dec31_dec_sub11_ldst_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 23 \dec31_dec_sub11_lk + attribute \enum_base_type "OutSel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RT" + attribute \enum_value_10 "RA" + attribute \enum_value_11 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 8 \dec31_dec_sub11_out_sel + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 13 \dec31_dec_sub11_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 20 \dec31_dec_sub11_rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 24 \dec31_dec_sub11_sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 22 \dec31_dec_sub11_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 19 \dec31_dec_sub11_sgn_ext + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 12 \dec31_dec_sub11_upd + attribute \src "issuer_ls180.v:83786.7-83786.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + wire width 32 input 25 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:320" + wire width 5 \opcode_switch + attribute \src "issuer_ls180.v:83786.7-83786.20" + process $proc$issuer_ls180.v:83786$3670 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "issuer_ls180.v:84043.3-84097.6" + process $proc$issuer_ls180.v:84043$3646 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub11_function_unit[11:0] $1\dec31_dec_sub11_function_unit[11:0] + attribute \src "issuer_ls180.v:84044.5-84044.29" + switch \initial + attribute \src "issuer_ls180.v:84044.9-84044.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub11_function_unit[11:0] 12'001000000000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub11_function_unit[11:0] 12'001000000000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub11_function_unit[11:0] 12'001000000000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub11_function_unit[11:0] 12'001000000000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub11_function_unit[11:0] 12'001000000000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub11_function_unit[11:0] 12'001000000000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub11_function_unit[11:0] 12'001000000000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub11_function_unit[11:0] 12'001000000000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub11_function_unit[11:0] 12'001000000000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub11_function_unit[11:0] 12'001000000000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub11_function_unit[11:0] 12'000100000000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub11_function_unit[11:0] 12'000100000000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub11_function_unit[11:0] 12'000100000000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub11_function_unit[11:0] 12'000100000000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub11_function_unit[11:0] 12'000100000000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub11_function_unit[11:0] 12'000100000000 + case + assign $1\dec31_dec_sub11_function_unit[11:0] 12'000000000000 + end + sync always + update \dec31_dec_sub11_function_unit $0\dec31_dec_sub11_function_unit[11:0] + end + attribute \src "issuer_ls180.v:84098.3-84152.6" + process $proc$issuer_ls180.v:84098$3647 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub11_ldst_len[3:0] $1\dec31_dec_sub11_ldst_len[3:0] + attribute \src "issuer_ls180.v:84099.5-84099.29" + switch \initial + attribute \src "issuer_ls180.v:84099.9-84099.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub11_ldst_len[3:0] 4'0000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub11_ldst_len[3:0] 4'0000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub11_ldst_len[3:0] 4'0000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub11_ldst_len[3:0] 4'0000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub11_ldst_len[3:0] 4'0000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub11_ldst_len[3:0] 4'0000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub11_ldst_len[3:0] 4'0000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub11_ldst_len[3:0] 4'0000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub11_ldst_len[3:0] 4'0000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub11_ldst_len[3:0] 4'0000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub11_ldst_len[3:0] 4'0000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub11_ldst_len[3:0] 4'0000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub11_ldst_len[3:0] 4'0000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub11_ldst_len[3:0] 4'0000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub11_ldst_len[3:0] 4'0000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub11_ldst_len[3:0] 4'0000 + case + assign $1\dec31_dec_sub11_ldst_len[3:0] 4'0000 + end + sync always + update \dec31_dec_sub11_ldst_len $0\dec31_dec_sub11_ldst_len[3:0] + end + attribute \src "issuer_ls180.v:84153.3-84207.6" + process $proc$issuer_ls180.v:84153$3648 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub11_upd[1:0] $1\dec31_dec_sub11_upd[1:0] + attribute \src "issuer_ls180.v:84154.5-84154.29" + switch \initial + attribute \src "issuer_ls180.v:84154.9-84154.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub11_upd[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub11_upd[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub11_upd[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub11_upd[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub11_upd[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub11_upd[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub11_upd[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub11_upd[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub11_upd[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub11_upd[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub11_upd[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub11_upd[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub11_upd[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub11_upd[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub11_upd[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub11_upd[1:0] 2'00 + case + assign $1\dec31_dec_sub11_upd[1:0] 2'00 + end + sync always + update \dec31_dec_sub11_upd $0\dec31_dec_sub11_upd[1:0] + end + attribute \src "issuer_ls180.v:84208.3-84262.6" + process $proc$issuer_ls180.v:84208$3649 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub11_rc_sel[1:0] $1\dec31_dec_sub11_rc_sel[1:0] + attribute \src "issuer_ls180.v:84209.5-84209.29" + switch \initial + attribute \src "issuer_ls180.v:84209.9-84209.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub11_rc_sel[1:0] 2'10 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub11_rc_sel[1:0] 2'10 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub11_rc_sel[1:0] 2'10 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub11_rc_sel[1:0] 2'10 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub11_rc_sel[1:0] 2'10 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub11_rc_sel[1:0] 2'10 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub11_rc_sel[1:0] 2'10 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub11_rc_sel[1:0] 2'10 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub11_rc_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub11_rc_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub11_rc_sel[1:0] 2'10 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub11_rc_sel[1:0] 2'10 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub11_rc_sel[1:0] 2'10 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub11_rc_sel[1:0] 2'10 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub11_rc_sel[1:0] 2'10 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub11_rc_sel[1:0] 2'10 + case + assign $1\dec31_dec_sub11_rc_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub11_rc_sel $0\dec31_dec_sub11_rc_sel[1:0] + end + attribute \src "issuer_ls180.v:84263.3-84317.6" + process $proc$issuer_ls180.v:84263$3650 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub11_cry_in[1:0] $1\dec31_dec_sub11_cry_in[1:0] + attribute \src "issuer_ls180.v:84264.5-84264.29" + switch \initial + attribute \src "issuer_ls180.v:84264.9-84264.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub11_cry_in[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub11_cry_in[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub11_cry_in[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub11_cry_in[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub11_cry_in[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub11_cry_in[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub11_cry_in[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub11_cry_in[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub11_cry_in[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub11_cry_in[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub11_cry_in[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub11_cry_in[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub11_cry_in[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub11_cry_in[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub11_cry_in[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub11_cry_in[1:0] 2'00 + case + assign $1\dec31_dec_sub11_cry_in[1:0] 2'00 + end + sync always + update \dec31_dec_sub11_cry_in $0\dec31_dec_sub11_cry_in[1:0] + end + attribute \src "issuer_ls180.v:84318.3-84372.6" + process $proc$issuer_ls180.v:84318$3651 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub11_asmcode[7:0] $1\dec31_dec_sub11_asmcode[7:0] + attribute \src "issuer_ls180.v:84319.5-84319.29" + switch \initial + attribute \src "issuer_ls180.v:84319.9-84319.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub11_asmcode[7:0] 8'00111110 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub11_asmcode[7:0] 8'00111111 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub11_asmcode[7:0] 8'00111100 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub11_asmcode[7:0] 8'00111101 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub11_asmcode[7:0] 8'01000001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub11_asmcode[7:0] 8'01000010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub11_asmcode[7:0] 8'00111011 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub11_asmcode[7:0] 8'01000000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub11_asmcode[7:0] 8'01110101 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub11_asmcode[7:0] 8'01110011 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub11_asmcode[7:0] 8'01111100 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub11_asmcode[7:0] 8'01111101 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub11_asmcode[7:0] 8'01111100 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub11_asmcode[7:0] 8'01111101 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub11_asmcode[7:0] 8'10000001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub11_asmcode[7:0] 8'10000010 + case + assign $1\dec31_dec_sub11_asmcode[7:0] 8'00000000 + end + sync always + update \dec31_dec_sub11_asmcode $0\dec31_dec_sub11_asmcode[7:0] + end + attribute \src "issuer_ls180.v:84373.3-84427.6" + process $proc$issuer_ls180.v:84373$3652 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub11_inv_a[0:0] $1\dec31_dec_sub11_inv_a[0:0] + attribute \src "issuer_ls180.v:84374.5-84374.29" + switch \initial + attribute \src "issuer_ls180.v:84374.9-84374.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub11_inv_a[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub11_inv_a[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub11_inv_a[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub11_inv_a[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub11_inv_a[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub11_inv_a[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub11_inv_a[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub11_inv_a[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub11_inv_a[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub11_inv_a[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub11_inv_a[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub11_inv_a[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub11_inv_a[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub11_inv_a[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub11_inv_a[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub11_inv_a[0:0] 1'0 + case + assign $1\dec31_dec_sub11_inv_a[0:0] 1'0 + end + sync always + update \dec31_dec_sub11_inv_a $0\dec31_dec_sub11_inv_a[0:0] + end + attribute \src "issuer_ls180.v:84428.3-84482.6" + process $proc$issuer_ls180.v:84428$3653 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub11_inv_out[0:0] $1\dec31_dec_sub11_inv_out[0:0] + attribute \src "issuer_ls180.v:84429.5-84429.29" + switch \initial + attribute \src "issuer_ls180.v:84429.9-84429.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub11_inv_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub11_inv_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub11_inv_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub11_inv_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub11_inv_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub11_inv_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub11_inv_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub11_inv_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub11_inv_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub11_inv_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub11_inv_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub11_inv_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub11_inv_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub11_inv_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub11_inv_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub11_inv_out[0:0] 1'0 + case + assign $1\dec31_dec_sub11_inv_out[0:0] 1'0 + end + sync always + update \dec31_dec_sub11_inv_out $0\dec31_dec_sub11_inv_out[0:0] + end + attribute \src "issuer_ls180.v:84483.3-84537.6" + process $proc$issuer_ls180.v:84483$3654 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub11_cry_out[0:0] $1\dec31_dec_sub11_cry_out[0:0] + attribute \src "issuer_ls180.v:84484.5-84484.29" + switch \initial + attribute \src "issuer_ls180.v:84484.9-84484.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub11_cry_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub11_cry_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub11_cry_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub11_cry_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub11_cry_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub11_cry_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub11_cry_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub11_cry_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub11_cry_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub11_cry_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub11_cry_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub11_cry_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub11_cry_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub11_cry_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub11_cry_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub11_cry_out[0:0] 1'0 + case + assign $1\dec31_dec_sub11_cry_out[0:0] 1'0 + end + sync always + update \dec31_dec_sub11_cry_out $0\dec31_dec_sub11_cry_out[0:0] + end + attribute \src "issuer_ls180.v:84538.3-84592.6" + process $proc$issuer_ls180.v:84538$3655 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub11_br[0:0] $1\dec31_dec_sub11_br[0:0] + attribute \src "issuer_ls180.v:84539.5-84539.29" + switch \initial + attribute \src "issuer_ls180.v:84539.9-84539.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub11_br[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub11_br[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub11_br[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub11_br[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub11_br[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub11_br[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub11_br[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub11_br[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub11_br[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub11_br[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub11_br[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub11_br[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub11_br[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub11_br[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub11_br[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub11_br[0:0] 1'0 + case + assign $1\dec31_dec_sub11_br[0:0] 1'0 + end + sync always + update \dec31_dec_sub11_br $0\dec31_dec_sub11_br[0:0] + end + attribute \src "issuer_ls180.v:84593.3-84647.6" + process $proc$issuer_ls180.v:84593$3656 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub11_sgn_ext[0:0] $1\dec31_dec_sub11_sgn_ext[0:0] + attribute \src "issuer_ls180.v:84594.5-84594.29" + switch \initial + attribute \src "issuer_ls180.v:84594.9-84594.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub11_sgn_ext[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub11_sgn_ext[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub11_sgn_ext[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub11_sgn_ext[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub11_sgn_ext[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub11_sgn_ext[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub11_sgn_ext[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub11_sgn_ext[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub11_sgn_ext[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub11_sgn_ext[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub11_sgn_ext[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub11_sgn_ext[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub11_sgn_ext[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub11_sgn_ext[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub11_sgn_ext[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub11_sgn_ext[0:0] 1'0 + case + assign $1\dec31_dec_sub11_sgn_ext[0:0] 1'0 + end + sync always + update \dec31_dec_sub11_sgn_ext $0\dec31_dec_sub11_sgn_ext[0:0] + end + attribute \src "issuer_ls180.v:84648.3-84702.6" + process $proc$issuer_ls180.v:84648$3657 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub11_internal_op[6:0] $1\dec31_dec_sub11_internal_op[6:0] + attribute \src "issuer_ls180.v:84649.5-84649.29" + switch \initial + attribute \src "issuer_ls180.v:84649.9-84649.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub11_internal_op[6:0] 7'0011110 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub11_internal_op[6:0] 7'0011110 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub11_internal_op[6:0] 7'0011110 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub11_internal_op[6:0] 7'0011110 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub11_internal_op[6:0] 7'0011101 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub11_internal_op[6:0] 7'0011101 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub11_internal_op[6:0] 7'0011101 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub11_internal_op[6:0] 7'0011101 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub11_internal_op[6:0] 7'0101111 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub11_internal_op[6:0] 7'0101111 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub11_internal_op[6:0] 7'0110100 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub11_internal_op[6:0] 7'0110100 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub11_internal_op[6:0] 7'0110100 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub11_internal_op[6:0] 7'0110100 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub11_internal_op[6:0] 7'0110010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub11_internal_op[6:0] 7'0110010 + case + assign $1\dec31_dec_sub11_internal_op[6:0] 7'0000000 + end + sync always + update \dec31_dec_sub11_internal_op $0\dec31_dec_sub11_internal_op[6:0] + end + attribute \src "issuer_ls180.v:84703.3-84757.6" + process $proc$issuer_ls180.v:84703$3658 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub11_rsrv[0:0] $1\dec31_dec_sub11_rsrv[0:0] + attribute \src "issuer_ls180.v:84704.5-84704.29" + switch \initial + attribute \src "issuer_ls180.v:84704.9-84704.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub11_rsrv[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub11_rsrv[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub11_rsrv[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub11_rsrv[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub11_rsrv[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub11_rsrv[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub11_rsrv[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub11_rsrv[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub11_rsrv[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub11_rsrv[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub11_rsrv[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub11_rsrv[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub11_rsrv[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub11_rsrv[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub11_rsrv[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub11_rsrv[0:0] 1'0 + case + assign $1\dec31_dec_sub11_rsrv[0:0] 1'0 + end + sync always + update \dec31_dec_sub11_rsrv $0\dec31_dec_sub11_rsrv[0:0] + end + attribute \src "issuer_ls180.v:84758.3-84812.6" + process $proc$issuer_ls180.v:84758$3659 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub11_is_32b[0:0] $1\dec31_dec_sub11_is_32b[0:0] + attribute \src "issuer_ls180.v:84759.5-84759.29" + switch \initial + attribute \src "issuer_ls180.v:84759.9-84759.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub11_is_32b[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub11_is_32b[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub11_is_32b[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub11_is_32b[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub11_is_32b[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub11_is_32b[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub11_is_32b[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub11_is_32b[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub11_is_32b[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub11_is_32b[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub11_is_32b[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub11_is_32b[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub11_is_32b[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub11_is_32b[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub11_is_32b[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub11_is_32b[0:0] 1'1 + case + assign $1\dec31_dec_sub11_is_32b[0:0] 1'0 + end + sync always + update \dec31_dec_sub11_is_32b $0\dec31_dec_sub11_is_32b[0:0] + end + attribute \src "issuer_ls180.v:84813.3-84867.6" + process $proc$issuer_ls180.v:84813$3660 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub11_sgn[0:0] $1\dec31_dec_sub11_sgn[0:0] + attribute \src "issuer_ls180.v:84814.5-84814.29" + switch \initial + attribute \src "issuer_ls180.v:84814.9-84814.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub11_sgn[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub11_sgn[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub11_sgn[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub11_sgn[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub11_sgn[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub11_sgn[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub11_sgn[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub11_sgn[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub11_sgn[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub11_sgn[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub11_sgn[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub11_sgn[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub11_sgn[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub11_sgn[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub11_sgn[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub11_sgn[0:0] 1'1 + case + assign $1\dec31_dec_sub11_sgn[0:0] 1'0 + end + sync always + update \dec31_dec_sub11_sgn $0\dec31_dec_sub11_sgn[0:0] + end + attribute \src "issuer_ls180.v:84868.3-84922.6" + process $proc$issuer_ls180.v:84868$3661 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub11_lk[0:0] $1\dec31_dec_sub11_lk[0:0] + attribute \src "issuer_ls180.v:84869.5-84869.29" + switch \initial + attribute \src "issuer_ls180.v:84869.9-84869.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub11_lk[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub11_lk[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub11_lk[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub11_lk[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub11_lk[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub11_lk[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub11_lk[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub11_lk[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub11_lk[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub11_lk[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub11_lk[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub11_lk[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub11_lk[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub11_lk[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub11_lk[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub11_lk[0:0] 1'0 + case + assign $1\dec31_dec_sub11_lk[0:0] 1'0 + end + sync always + update \dec31_dec_sub11_lk $0\dec31_dec_sub11_lk[0:0] + end + attribute \src "issuer_ls180.v:84923.3-84977.6" + process $proc$issuer_ls180.v:84923$3662 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub11_sgl_pipe[0:0] $1\dec31_dec_sub11_sgl_pipe[0:0] + attribute \src "issuer_ls180.v:84924.5-84924.29" + switch \initial + attribute \src "issuer_ls180.v:84924.9-84924.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub11_sgl_pipe[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub11_sgl_pipe[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub11_sgl_pipe[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub11_sgl_pipe[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub11_sgl_pipe[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub11_sgl_pipe[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub11_sgl_pipe[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub11_sgl_pipe[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub11_sgl_pipe[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub11_sgl_pipe[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub11_sgl_pipe[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub11_sgl_pipe[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub11_sgl_pipe[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub11_sgl_pipe[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub11_sgl_pipe[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub11_sgl_pipe[0:0] 1'0 + case + assign $1\dec31_dec_sub11_sgl_pipe[0:0] 1'0 + end + sync always + update \dec31_dec_sub11_sgl_pipe $0\dec31_dec_sub11_sgl_pipe[0:0] + end + attribute \src "issuer_ls180.v:84978.3-85032.6" + process $proc$issuer_ls180.v:84978$3663 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub11_form[4:0] $1\dec31_dec_sub11_form[4:0] + attribute \src "issuer_ls180.v:84979.5-84979.29" + switch \initial + attribute \src "issuer_ls180.v:84979.9-84979.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub11_form[4:0] 5'10001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub11_form[4:0] 5'10001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub11_form[4:0] 5'10001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub11_form[4:0] 5'10001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub11_form[4:0] 5'10001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub11_form[4:0] 5'10001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub11_form[4:0] 5'10001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub11_form[4:0] 5'10001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub11_form[4:0] 5'01000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub11_form[4:0] 5'01000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub11_form[4:0] 5'10001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub11_form[4:0] 5'10001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub11_form[4:0] 5'10001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub11_form[4:0] 5'10001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub11_form[4:0] 5'10001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub11_form[4:0] 5'10001 + case + assign $1\dec31_dec_sub11_form[4:0] 5'00000 + end + sync always + update \dec31_dec_sub11_form $0\dec31_dec_sub11_form[4:0] + end + attribute \src "issuer_ls180.v:85033.3-85087.6" + process $proc$issuer_ls180.v:85033$3664 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub11_in1_sel[2:0] $1\dec31_dec_sub11_in1_sel[2:0] + attribute \src "issuer_ls180.v:85034.5-85034.29" + switch \initial + attribute \src "issuer_ls180.v:85034.9-85034.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub11_in1_sel[2:0] 3'001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub11_in1_sel[2:0] 3'001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub11_in1_sel[2:0] 3'001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub11_in1_sel[2:0] 3'001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub11_in1_sel[2:0] 3'001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub11_in1_sel[2:0] 3'001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub11_in1_sel[2:0] 3'001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub11_in1_sel[2:0] 3'001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub11_in1_sel[2:0] 3'001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub11_in1_sel[2:0] 3'001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub11_in1_sel[2:0] 3'001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub11_in1_sel[2:0] 3'001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub11_in1_sel[2:0] 3'001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub11_in1_sel[2:0] 3'001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub11_in1_sel[2:0] 3'001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub11_in1_sel[2:0] 3'001 + case + assign $1\dec31_dec_sub11_in1_sel[2:0] 3'000 + end + sync always + update \dec31_dec_sub11_in1_sel $0\dec31_dec_sub11_in1_sel[2:0] + end + attribute \src "issuer_ls180.v:85088.3-85142.6" + process $proc$issuer_ls180.v:85088$3665 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub11_in2_sel[3:0] $1\dec31_dec_sub11_in2_sel[3:0] + attribute \src "issuer_ls180.v:85089.5-85089.29" + switch \initial + attribute \src "issuer_ls180.v:85089.9-85089.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub11_in2_sel[3:0] 4'0001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub11_in2_sel[3:0] 4'0001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub11_in2_sel[3:0] 4'0001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub11_in2_sel[3:0] 4'0001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub11_in2_sel[3:0] 4'0001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub11_in2_sel[3:0] 4'0001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub11_in2_sel[3:0] 4'0001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub11_in2_sel[3:0] 4'0001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub11_in2_sel[3:0] 4'0001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub11_in2_sel[3:0] 4'0001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub11_in2_sel[3:0] 4'0001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub11_in2_sel[3:0] 4'0001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub11_in2_sel[3:0] 4'0001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub11_in2_sel[3:0] 4'0001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub11_in2_sel[3:0] 4'0001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub11_in2_sel[3:0] 4'0001 + case + assign $1\dec31_dec_sub11_in2_sel[3:0] 4'0000 + end + sync always + update \dec31_dec_sub11_in2_sel $0\dec31_dec_sub11_in2_sel[3:0] + end + attribute \src "issuer_ls180.v:85143.3-85197.6" + process $proc$issuer_ls180.v:85143$3666 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub11_in3_sel[1:0] $1\dec31_dec_sub11_in3_sel[1:0] + attribute \src "issuer_ls180.v:85144.5-85144.29" + switch \initial + attribute \src "issuer_ls180.v:85144.9-85144.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub11_in3_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub11_in3_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub11_in3_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub11_in3_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub11_in3_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub11_in3_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub11_in3_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub11_in3_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub11_in3_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub11_in3_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub11_in3_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub11_in3_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub11_in3_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub11_in3_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub11_in3_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub11_in3_sel[1:0] 2'00 + case + assign $1\dec31_dec_sub11_in3_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub11_in3_sel $0\dec31_dec_sub11_in3_sel[1:0] + end + attribute \src "issuer_ls180.v:85198.3-85252.6" + process $proc$issuer_ls180.v:85198$3667 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub11_out_sel[1:0] $1\dec31_dec_sub11_out_sel[1:0] + attribute \src "issuer_ls180.v:85199.5-85199.29" + switch \initial + attribute \src "issuer_ls180.v:85199.9-85199.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub11_out_sel[1:0] 2'01 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub11_out_sel[1:0] 2'01 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub11_out_sel[1:0] 2'01 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub11_out_sel[1:0] 2'01 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub11_out_sel[1:0] 2'01 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub11_out_sel[1:0] 2'01 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub11_out_sel[1:0] 2'01 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub11_out_sel[1:0] 2'01 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub11_out_sel[1:0] 2'01 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub11_out_sel[1:0] 2'01 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub11_out_sel[1:0] 2'01 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub11_out_sel[1:0] 2'01 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub11_out_sel[1:0] 2'01 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub11_out_sel[1:0] 2'01 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub11_out_sel[1:0] 2'01 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub11_out_sel[1:0] 2'01 + case + assign $1\dec31_dec_sub11_out_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub11_out_sel $0\dec31_dec_sub11_out_sel[1:0] + end + attribute \src "issuer_ls180.v:85253.3-85307.6" + process $proc$issuer_ls180.v:85253$3668 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub11_cr_in[2:0] $1\dec31_dec_sub11_cr_in[2:0] + attribute \src "issuer_ls180.v:85254.5-85254.29" + switch \initial + attribute \src "issuer_ls180.v:85254.9-85254.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub11_cr_in[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub11_cr_in[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub11_cr_in[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub11_cr_in[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub11_cr_in[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub11_cr_in[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub11_cr_in[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub11_cr_in[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub11_cr_in[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub11_cr_in[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub11_cr_in[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub11_cr_in[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub11_cr_in[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub11_cr_in[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub11_cr_in[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub11_cr_in[2:0] 3'000 + case + assign $1\dec31_dec_sub11_cr_in[2:0] 3'000 + end + sync always + update \dec31_dec_sub11_cr_in $0\dec31_dec_sub11_cr_in[2:0] + end + attribute \src "issuer_ls180.v:85308.3-85362.6" + process $proc$issuer_ls180.v:85308$3669 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub11_cr_out[2:0] $1\dec31_dec_sub11_cr_out[2:0] + attribute \src "issuer_ls180.v:85309.5-85309.29" + switch \initial + attribute \src "issuer_ls180.v:85309.9-85309.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub11_cr_out[2:0] 3'001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub11_cr_out[2:0] 3'001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub11_cr_out[2:0] 3'001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub11_cr_out[2:0] 3'001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub11_cr_out[2:0] 3'001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub11_cr_out[2:0] 3'001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub11_cr_out[2:0] 3'001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub11_cr_out[2:0] 3'001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub11_cr_out[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub11_cr_out[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub11_cr_out[2:0] 3'001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub11_cr_out[2:0] 3'001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub11_cr_out[2:0] 3'001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub11_cr_out[2:0] 3'001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub11_cr_out[2:0] 3'001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub11_cr_out[2:0] 3'001 + case + assign $1\dec31_dec_sub11_cr_out[2:0] 3'000 + end + sync always + update \dec31_dec_sub11_cr_out $0\dec31_dec_sub11_cr_out[2:0] + end + connect \opcode_switch \opcode_in [10:6] +end +attribute \src "issuer_ls180.v:85368.1-88099.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.dec2.dec.dec31.dec31_dec_sub15" +attribute \generator "nMigen" +module \dec31_dec_sub15 + attribute \src "issuer_ls180.v:86141.3-86243.6" + wire width 8 $0\dec31_dec_sub15_asmcode[7:0] + attribute \src "issuer_ls180.v:86553.3-86655.6" + wire $0\dec31_dec_sub15_br[0:0] + attribute \src "issuer_ls180.v:87892.3-87994.6" + wire width 3 $0\dec31_dec_sub15_cr_in[2:0] + attribute \src "issuer_ls180.v:87995.3-88097.6" + wire width 3 $0\dec31_dec_sub15_cr_out[2:0] + attribute \src "issuer_ls180.v:86038.3-86140.6" + wire width 2 $0\dec31_dec_sub15_cry_in[1:0] + attribute \src "issuer_ls180.v:86450.3-86552.6" + wire $0\dec31_dec_sub15_cry_out[0:0] + attribute \src "issuer_ls180.v:87377.3-87479.6" + wire width 5 $0\dec31_dec_sub15_form[4:0] + attribute \src "issuer_ls180.v:85626.3-85728.6" + wire width 12 $0\dec31_dec_sub15_function_unit[11:0] + attribute \src "issuer_ls180.v:87480.3-87582.6" + wire width 3 $0\dec31_dec_sub15_in1_sel[2:0] + attribute \src "issuer_ls180.v:87583.3-87685.6" + wire width 4 $0\dec31_dec_sub15_in2_sel[3:0] + attribute \src "issuer_ls180.v:87686.3-87788.6" + wire width 2 $0\dec31_dec_sub15_in3_sel[1:0] + attribute \src "issuer_ls180.v:86759.3-86861.6" + wire width 7 $0\dec31_dec_sub15_internal_op[6:0] + attribute \src "issuer_ls180.v:86244.3-86346.6" + wire $0\dec31_dec_sub15_inv_a[0:0] + attribute \src "issuer_ls180.v:86347.3-86449.6" + wire $0\dec31_dec_sub15_inv_out[0:0] + attribute \src "issuer_ls180.v:86965.3-87067.6" + wire $0\dec31_dec_sub15_is_32b[0:0] + attribute \src "issuer_ls180.v:85729.3-85831.6" + wire width 4 $0\dec31_dec_sub15_ldst_len[3:0] + attribute \src "issuer_ls180.v:87171.3-87273.6" + wire $0\dec31_dec_sub15_lk[0:0] + attribute \src "issuer_ls180.v:87789.3-87891.6" + wire width 2 $0\dec31_dec_sub15_out_sel[1:0] + attribute \src "issuer_ls180.v:85935.3-86037.6" + wire width 2 $0\dec31_dec_sub15_rc_sel[1:0] + attribute \src "issuer_ls180.v:86862.3-86964.6" + wire $0\dec31_dec_sub15_rsrv[0:0] + attribute \src "issuer_ls180.v:87274.3-87376.6" + wire $0\dec31_dec_sub15_sgl_pipe[0:0] + attribute \src "issuer_ls180.v:87068.3-87170.6" + wire $0\dec31_dec_sub15_sgn[0:0] + attribute \src "issuer_ls180.v:86656.3-86758.6" + wire $0\dec31_dec_sub15_sgn_ext[0:0] + attribute \src "issuer_ls180.v:85832.3-85934.6" + wire width 2 $0\dec31_dec_sub15_upd[1:0] + attribute \src "issuer_ls180.v:85369.7-85369.20" + wire $0\initial[0:0] + attribute \src "issuer_ls180.v:86141.3-86243.6" + wire width 8 $1\dec31_dec_sub15_asmcode[7:0] + attribute \src "issuer_ls180.v:86553.3-86655.6" + wire $1\dec31_dec_sub15_br[0:0] + attribute \src "issuer_ls180.v:87892.3-87994.6" + wire width 3 $1\dec31_dec_sub15_cr_in[2:0] + attribute \src "issuer_ls180.v:87995.3-88097.6" + wire width 3 $1\dec31_dec_sub15_cr_out[2:0] + attribute \src "issuer_ls180.v:86038.3-86140.6" + wire width 2 $1\dec31_dec_sub15_cry_in[1:0] + attribute \src "issuer_ls180.v:86450.3-86552.6" + wire $1\dec31_dec_sub15_cry_out[0:0] + attribute \src "issuer_ls180.v:87377.3-87479.6" + wire width 5 $1\dec31_dec_sub15_form[4:0] + attribute \src "issuer_ls180.v:85626.3-85728.6" + wire width 12 $1\dec31_dec_sub15_function_unit[11:0] + attribute \src "issuer_ls180.v:87480.3-87582.6" + wire width 3 $1\dec31_dec_sub15_in1_sel[2:0] + attribute \src "issuer_ls180.v:87583.3-87685.6" + wire width 4 $1\dec31_dec_sub15_in2_sel[3:0] + attribute \src "issuer_ls180.v:87686.3-87788.6" + wire width 2 $1\dec31_dec_sub15_in3_sel[1:0] + attribute \src "issuer_ls180.v:86759.3-86861.6" + wire width 7 $1\dec31_dec_sub15_internal_op[6:0] + attribute \src "issuer_ls180.v:86244.3-86346.6" + wire $1\dec31_dec_sub15_inv_a[0:0] + attribute \src "issuer_ls180.v:86347.3-86449.6" + wire $1\dec31_dec_sub15_inv_out[0:0] + attribute \src "issuer_ls180.v:86965.3-87067.6" + wire $1\dec31_dec_sub15_is_32b[0:0] + attribute \src "issuer_ls180.v:85729.3-85831.6" + wire width 4 $1\dec31_dec_sub15_ldst_len[3:0] + attribute \src "issuer_ls180.v:87171.3-87273.6" + wire $1\dec31_dec_sub15_lk[0:0] + attribute \src "issuer_ls180.v:87789.3-87891.6" + wire width 2 $1\dec31_dec_sub15_out_sel[1:0] + attribute \src "issuer_ls180.v:85935.3-86037.6" + wire width 2 $1\dec31_dec_sub15_rc_sel[1:0] + attribute \src "issuer_ls180.v:86862.3-86964.6" + wire $1\dec31_dec_sub15_rsrv[0:0] + attribute \src "issuer_ls180.v:87274.3-87376.6" + wire $1\dec31_dec_sub15_sgl_pipe[0:0] + attribute \src "issuer_ls180.v:87068.3-87170.6" + wire $1\dec31_dec_sub15_sgn[0:0] + attribute \src "issuer_ls180.v:86656.3-86758.6" + wire $1\dec31_dec_sub15_sgn_ext[0:0] + attribute \src "issuer_ls180.v:85832.3-85934.6" + wire width 2 $1\dec31_dec_sub15_upd[1:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 8 output 4 \dec31_dec_sub15_asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 18 \dec31_dec_sub15_br + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 9 \dec31_dec_sub15_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 10 \dec31_dec_sub15_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 14 \dec31_dec_sub15_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 17 \dec31_dec_sub15_cry_out + attribute \enum_base_type "Form" + attribute \enum_value_00000 "NONE" + attribute \enum_value_00001 "I" + attribute \enum_value_00010 "B" + attribute \enum_value_00011 "SC" + attribute \enum_value_00100 "D" + attribute \enum_value_00101 "DS" + attribute \enum_value_00110 "DQ" + attribute \enum_value_00111 "DX" + attribute \enum_value_01000 "X" + attribute \enum_value_01001 "XL" + attribute \enum_value_01010 "XFX" + attribute \enum_value_01011 "XFL" + attribute \enum_value_01100 "XX1" + attribute \enum_value_01101 "XX2" + attribute \enum_value_01110 "XX3" + attribute \enum_value_01111 "XX4" + attribute \enum_value_10000 "XS" + attribute \enum_value_10001 "XO" + attribute \enum_value_10010 "A" + attribute \enum_value_10011 "M" + attribute \enum_value_10100 "MD" + attribute \enum_value_10101 "MDS" + attribute \enum_value_10110 "VA" + attribute \enum_value_10111 "VC" + attribute \enum_value_11000 "VX" + attribute \enum_value_11001 "EVX" + attribute \enum_value_11010 "EVS" + attribute \enum_value_11011 "Z22" + attribute \enum_value_11100 "Z23" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 5 output 3 \dec31_dec_sub15_form + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 12 output 1 \dec31_dec_sub15_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 5 \dec31_dec_sub15_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 output 6 \dec31_dec_sub15_in2_sel + attribute \enum_base_type "In3Sel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RS" + attribute \enum_value_10 "RB" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 7 \dec31_dec_sub15_in3_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 7 output 2 \dec31_dec_sub15_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 15 \dec31_dec_sub15_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 16 \dec31_dec_sub15_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 21 \dec31_dec_sub15_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 output 11 \dec31_dec_sub15_ldst_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 23 \dec31_dec_sub15_lk + attribute \enum_base_type "OutSel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RT" + attribute \enum_value_10 "RA" + attribute \enum_value_11 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 8 \dec31_dec_sub15_out_sel + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 13 \dec31_dec_sub15_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 20 \dec31_dec_sub15_rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 24 \dec31_dec_sub15_sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 22 \dec31_dec_sub15_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 19 \dec31_dec_sub15_sgn_ext + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 12 \dec31_dec_sub15_upd + attribute \src "issuer_ls180.v:85369.7-85369.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + wire width 32 input 25 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:320" + wire width 5 \opcode_switch + attribute \src "issuer_ls180.v:85369.7-85369.20" + process $proc$issuer_ls180.v:85369$3695 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "issuer_ls180.v:85626.3-85728.6" + process $proc$issuer_ls180.v:85626$3671 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub15_function_unit[11:0] $1\dec31_dec_sub15_function_unit[11:0] + attribute \src "issuer_ls180.v:85627.5-85627.29" + switch \initial + attribute \src "issuer_ls180.v:85627.9-85627.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub15_function_unit[11:0] 12'000001000000 + case + assign $1\dec31_dec_sub15_function_unit[11:0] 12'000000000000 + end + sync always + update \dec31_dec_sub15_function_unit $0\dec31_dec_sub15_function_unit[11:0] + end + attribute \src "issuer_ls180.v:85729.3-85831.6" + process $proc$issuer_ls180.v:85729$3672 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub15_ldst_len[3:0] $1\dec31_dec_sub15_ldst_len[3:0] + attribute \src "issuer_ls180.v:85730.5-85730.29" + switch \initial + attribute \src "issuer_ls180.v:85730.9-85730.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 + case + assign $1\dec31_dec_sub15_ldst_len[3:0] 4'0000 + end + sync always + update \dec31_dec_sub15_ldst_len $0\dec31_dec_sub15_ldst_len[3:0] + end + attribute \src "issuer_ls180.v:85832.3-85934.6" + process $proc$issuer_ls180.v:85832$3673 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub15_upd[1:0] $1\dec31_dec_sub15_upd[1:0] + attribute \src "issuer_ls180.v:85833.5-85833.29" + switch \initial + attribute \src "issuer_ls180.v:85833.9-85833.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub15_upd[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub15_upd[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub15_upd[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub15_upd[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub15_upd[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub15_upd[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub15_upd[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub15_upd[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub15_upd[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub15_upd[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub15_upd[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub15_upd[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub15_upd[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub15_upd[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub15_upd[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub15_upd[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub15_upd[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub15_upd[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub15_upd[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub15_upd[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub15_upd[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub15_upd[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub15_upd[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub15_upd[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub15_upd[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub15_upd[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub15_upd[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub15_upd[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub15_upd[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub15_upd[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub15_upd[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub15_upd[1:0] 2'00 + case + assign $1\dec31_dec_sub15_upd[1:0] 2'00 + end + sync always + update \dec31_dec_sub15_upd $0\dec31_dec_sub15_upd[1:0] + end + attribute \src "issuer_ls180.v:85935.3-86037.6" + process $proc$issuer_ls180.v:85935$3674 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub15_rc_sel[1:0] $1\dec31_dec_sub15_rc_sel[1:0] + attribute \src "issuer_ls180.v:85936.5-85936.29" + switch \initial + attribute \src "issuer_ls180.v:85936.9-85936.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 + case + assign $1\dec31_dec_sub15_rc_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub15_rc_sel $0\dec31_dec_sub15_rc_sel[1:0] + end + attribute \src "issuer_ls180.v:86038.3-86140.6" + process $proc$issuer_ls180.v:86038$3675 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub15_cry_in[1:0] $1\dec31_dec_sub15_cry_in[1:0] + attribute \src "issuer_ls180.v:86039.5-86039.29" + switch \initial + attribute \src "issuer_ls180.v:86039.9-86039.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 + case + assign $1\dec31_dec_sub15_cry_in[1:0] 2'00 + end + sync always + update \dec31_dec_sub15_cry_in $0\dec31_dec_sub15_cry_in[1:0] + end + attribute \src "issuer_ls180.v:86141.3-86243.6" + process $proc$issuer_ls180.v:86141$3676 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub15_asmcode[7:0] $1\dec31_dec_sub15_asmcode[7:0] + attribute \src "issuer_ls180.v:86142.5-86142.29" + switch \initial + attribute \src "issuer_ls180.v:86142.9-86142.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub15_asmcode[7:0] 8'01001011 + case + assign $1\dec31_dec_sub15_asmcode[7:0] 8'00000000 + end + sync always + update \dec31_dec_sub15_asmcode $0\dec31_dec_sub15_asmcode[7:0] + end + attribute \src "issuer_ls180.v:86244.3-86346.6" + process $proc$issuer_ls180.v:86244$3677 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub15_inv_a[0:0] $1\dec31_dec_sub15_inv_a[0:0] + attribute \src "issuer_ls180.v:86245.5-86245.29" + switch \initial + attribute \src "issuer_ls180.v:86245.9-86245.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 + case + assign $1\dec31_dec_sub15_inv_a[0:0] 1'0 + end + sync always + update \dec31_dec_sub15_inv_a $0\dec31_dec_sub15_inv_a[0:0] + end + attribute \src "issuer_ls180.v:86347.3-86449.6" + process $proc$issuer_ls180.v:86347$3678 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub15_inv_out[0:0] $1\dec31_dec_sub15_inv_out[0:0] + attribute \src "issuer_ls180.v:86348.5-86348.29" + switch \initial + attribute \src "issuer_ls180.v:86348.9-86348.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 + case + assign $1\dec31_dec_sub15_inv_out[0:0] 1'0 + end + sync always + update \dec31_dec_sub15_inv_out $0\dec31_dec_sub15_inv_out[0:0] + end + attribute \src "issuer_ls180.v:86450.3-86552.6" + process $proc$issuer_ls180.v:86450$3679 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub15_cry_out[0:0] $1\dec31_dec_sub15_cry_out[0:0] + attribute \src "issuer_ls180.v:86451.5-86451.29" + switch \initial + attribute \src "issuer_ls180.v:86451.9-86451.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 + case + assign $1\dec31_dec_sub15_cry_out[0:0] 1'0 + end + sync always + update \dec31_dec_sub15_cry_out $0\dec31_dec_sub15_cry_out[0:0] + end + attribute \src "issuer_ls180.v:86553.3-86655.6" + process $proc$issuer_ls180.v:86553$3680 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub15_br[0:0] $1\dec31_dec_sub15_br[0:0] + attribute \src "issuer_ls180.v:86554.5-86554.29" + switch \initial + attribute \src "issuer_ls180.v:86554.9-86554.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub15_br[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub15_br[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub15_br[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub15_br[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub15_br[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub15_br[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub15_br[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub15_br[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub15_br[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub15_br[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub15_br[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub15_br[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub15_br[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub15_br[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub15_br[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub15_br[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub15_br[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub15_br[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub15_br[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub15_br[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub15_br[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub15_br[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub15_br[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub15_br[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub15_br[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub15_br[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub15_br[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub15_br[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub15_br[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub15_br[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub15_br[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub15_br[0:0] 1'0 + case + assign $1\dec31_dec_sub15_br[0:0] 1'0 + end + sync always + update \dec31_dec_sub15_br $0\dec31_dec_sub15_br[0:0] + end + attribute \src "issuer_ls180.v:86656.3-86758.6" + process $proc$issuer_ls180.v:86656$3681 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub15_sgn_ext[0:0] $1\dec31_dec_sub15_sgn_ext[0:0] + attribute \src "issuer_ls180.v:86657.5-86657.29" + switch \initial + attribute \src "issuer_ls180.v:86657.9-86657.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 + case + assign $1\dec31_dec_sub15_sgn_ext[0:0] 1'0 + end + sync always + update \dec31_dec_sub15_sgn_ext $0\dec31_dec_sub15_sgn_ext[0:0] + end + attribute \src "issuer_ls180.v:86759.3-86861.6" + process $proc$issuer_ls180.v:86759$3682 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub15_internal_op[6:0] $1\dec31_dec_sub15_internal_op[6:0] + attribute \src "issuer_ls180.v:86760.5-86760.29" + switch \initial + attribute \src "issuer_ls180.v:86760.9-86760.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub15_internal_op[6:0] 7'0100011 + case + assign $1\dec31_dec_sub15_internal_op[6:0] 7'0000000 + end + sync always + update \dec31_dec_sub15_internal_op $0\dec31_dec_sub15_internal_op[6:0] + end + attribute \src "issuer_ls180.v:86862.3-86964.6" + process $proc$issuer_ls180.v:86862$3683 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub15_rsrv[0:0] $1\dec31_dec_sub15_rsrv[0:0] + attribute \src "issuer_ls180.v:86863.5-86863.29" + switch \initial + attribute \src "issuer_ls180.v:86863.9-86863.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 + case + assign $1\dec31_dec_sub15_rsrv[0:0] 1'0 + end + sync always + update \dec31_dec_sub15_rsrv $0\dec31_dec_sub15_rsrv[0:0] + end + attribute \src "issuer_ls180.v:86965.3-87067.6" + process $proc$issuer_ls180.v:86965$3684 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub15_is_32b[0:0] $1\dec31_dec_sub15_is_32b[0:0] + attribute \src "issuer_ls180.v:86966.5-86966.29" + switch \initial + attribute \src "issuer_ls180.v:86966.9-86966.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 + case + assign $1\dec31_dec_sub15_is_32b[0:0] 1'0 + end + sync always + update \dec31_dec_sub15_is_32b $0\dec31_dec_sub15_is_32b[0:0] + end + attribute \src "issuer_ls180.v:87068.3-87170.6" + process $proc$issuer_ls180.v:87068$3685 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub15_sgn[0:0] $1\dec31_dec_sub15_sgn[0:0] + attribute \src "issuer_ls180.v:87069.5-87069.29" + switch \initial + attribute \src "issuer_ls180.v:87069.9-87069.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub15_sgn[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub15_sgn[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub15_sgn[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub15_sgn[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub15_sgn[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub15_sgn[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub15_sgn[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub15_sgn[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub15_sgn[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub15_sgn[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub15_sgn[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub15_sgn[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub15_sgn[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub15_sgn[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub15_sgn[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub15_sgn[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub15_sgn[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub15_sgn[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub15_sgn[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub15_sgn[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub15_sgn[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub15_sgn[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub15_sgn[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub15_sgn[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub15_sgn[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub15_sgn[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub15_sgn[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub15_sgn[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub15_sgn[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub15_sgn[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub15_sgn[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub15_sgn[0:0] 1'0 + case + assign $1\dec31_dec_sub15_sgn[0:0] 1'0 + end + sync always + update \dec31_dec_sub15_sgn $0\dec31_dec_sub15_sgn[0:0] + end + attribute \src "issuer_ls180.v:87171.3-87273.6" + process $proc$issuer_ls180.v:87171$3686 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub15_lk[0:0] $1\dec31_dec_sub15_lk[0:0] + attribute \src "issuer_ls180.v:87172.5-87172.29" + switch \initial + attribute \src "issuer_ls180.v:87172.9-87172.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub15_lk[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub15_lk[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub15_lk[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub15_lk[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub15_lk[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub15_lk[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub15_lk[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub15_lk[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub15_lk[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub15_lk[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub15_lk[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub15_lk[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub15_lk[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub15_lk[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub15_lk[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub15_lk[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub15_lk[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub15_lk[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub15_lk[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub15_lk[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub15_lk[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub15_lk[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub15_lk[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub15_lk[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub15_lk[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub15_lk[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub15_lk[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub15_lk[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub15_lk[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub15_lk[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub15_lk[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub15_lk[0:0] 1'0 + case + assign $1\dec31_dec_sub15_lk[0:0] 1'0 + end + sync always + update \dec31_dec_sub15_lk $0\dec31_dec_sub15_lk[0:0] + end + attribute \src "issuer_ls180.v:87274.3-87376.6" + process $proc$issuer_ls180.v:87274$3687 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub15_sgl_pipe[0:0] $1\dec31_dec_sub15_sgl_pipe[0:0] + attribute \src "issuer_ls180.v:87275.5-87275.29" + switch \initial + attribute \src "issuer_ls180.v:87275.9-87275.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'1 + case + assign $1\dec31_dec_sub15_sgl_pipe[0:0] 1'0 + end + sync always + update \dec31_dec_sub15_sgl_pipe $0\dec31_dec_sub15_sgl_pipe[0:0] + end + attribute \src "issuer_ls180.v:87377.3-87479.6" + process $proc$issuer_ls180.v:87377$3688 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub15_form[4:0] $1\dec31_dec_sub15_form[4:0] + attribute \src "issuer_ls180.v:87378.5-87378.29" + switch \initial + attribute \src "issuer_ls180.v:87378.9-87378.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub15_form[4:0] 5'10010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub15_form[4:0] 5'10010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub15_form[4:0] 5'10010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub15_form[4:0] 5'10010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub15_form[4:0] 5'10010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub15_form[4:0] 5'10010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub15_form[4:0] 5'10010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub15_form[4:0] 5'10010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub15_form[4:0] 5'10010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub15_form[4:0] 5'10010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub15_form[4:0] 5'10010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub15_form[4:0] 5'10010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub15_form[4:0] 5'10010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub15_form[4:0] 5'10010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub15_form[4:0] 5'10010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub15_form[4:0] 5'10010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub15_form[4:0] 5'10010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub15_form[4:0] 5'10010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub15_form[4:0] 5'10010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub15_form[4:0] 5'10010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub15_form[4:0] 5'10010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub15_form[4:0] 5'10010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub15_form[4:0] 5'10010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub15_form[4:0] 5'10010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub15_form[4:0] 5'10010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub15_form[4:0] 5'10010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub15_form[4:0] 5'10010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub15_form[4:0] 5'10010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub15_form[4:0] 5'10010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub15_form[4:0] 5'10010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub15_form[4:0] 5'10010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub15_form[4:0] 5'10010 + case + assign $1\dec31_dec_sub15_form[4:0] 5'00000 + end + sync always + update \dec31_dec_sub15_form $0\dec31_dec_sub15_form[4:0] + end + attribute \src "issuer_ls180.v:87480.3-87582.6" + process $proc$issuer_ls180.v:87480$3689 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub15_in1_sel[2:0] $1\dec31_dec_sub15_in1_sel[2:0] + attribute \src "issuer_ls180.v:87481.5-87481.29" + switch \initial + attribute \src "issuer_ls180.v:87481.9-87481.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub15_in1_sel[2:0] 3'010 + case + assign $1\dec31_dec_sub15_in1_sel[2:0] 3'000 + end + sync always + update \dec31_dec_sub15_in1_sel $0\dec31_dec_sub15_in1_sel[2:0] + end + attribute \src "issuer_ls180.v:87583.3-87685.6" + process $proc$issuer_ls180.v:87583$3690 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub15_in2_sel[3:0] $1\dec31_dec_sub15_in2_sel[3:0] + attribute \src "issuer_ls180.v:87584.5-87584.29" + switch \initial + attribute \src "issuer_ls180.v:87584.9-87584.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0001 + case + assign $1\dec31_dec_sub15_in2_sel[3:0] 4'0000 + end + sync always + update \dec31_dec_sub15_in2_sel $0\dec31_dec_sub15_in2_sel[3:0] + end + attribute \src "issuer_ls180.v:87686.3-87788.6" + process $proc$issuer_ls180.v:87686$3691 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub15_in3_sel[1:0] $1\dec31_dec_sub15_in3_sel[1:0] + attribute \src "issuer_ls180.v:87687.5-87687.29" + switch \initial + attribute \src "issuer_ls180.v:87687.9-87687.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 + case + assign $1\dec31_dec_sub15_in3_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub15_in3_sel $0\dec31_dec_sub15_in3_sel[1:0] + end + attribute \src "issuer_ls180.v:87789.3-87891.6" + process $proc$issuer_ls180.v:87789$3692 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub15_out_sel[1:0] $1\dec31_dec_sub15_out_sel[1:0] + attribute \src "issuer_ls180.v:87790.5-87790.29" + switch \initial + attribute \src "issuer_ls180.v:87790.9-87790.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub15_out_sel[1:0] 2'01 + case + assign $1\dec31_dec_sub15_out_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub15_out_sel $0\dec31_dec_sub15_out_sel[1:0] + end + attribute \src "issuer_ls180.v:87892.3-87994.6" + process $proc$issuer_ls180.v:87892$3693 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub15_cr_in[2:0] $1\dec31_dec_sub15_cr_in[2:0] + attribute \src "issuer_ls180.v:87893.5-87893.29" + switch \initial + attribute \src "issuer_ls180.v:87893.9-87893.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub15_cr_in[2:0] 3'101 + case + assign $1\dec31_dec_sub15_cr_in[2:0] 3'000 + end + sync always + update \dec31_dec_sub15_cr_in $0\dec31_dec_sub15_cr_in[2:0] + end + attribute \src "issuer_ls180.v:87995.3-88097.6" + process $proc$issuer_ls180.v:87995$3694 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub15_cr_out[2:0] $1\dec31_dec_sub15_cr_out[2:0] + attribute \src "issuer_ls180.v:87996.5-87996.29" + switch \initial + attribute \src "issuer_ls180.v:87996.9-87996.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 + case + assign $1\dec31_dec_sub15_cr_out[2:0] 3'000 + end + sync always + update \dec31_dec_sub15_cr_out $0\dec31_dec_sub15_cr_out[2:0] + end + connect \opcode_switch \opcode_in [10:6] +end +attribute \src "issuer_ls180.v:88103.1-88602.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.dec2.dec.dec31.dec31_dec_sub16" +attribute \generator "nMigen" +module \dec31_dec_sub16 + attribute \src "issuer_ls180.v:88411.3-88420.6" + wire width 8 $0\dec31_dec_sub16_asmcode[7:0] + attribute \src "issuer_ls180.v:88451.3-88460.6" + wire $0\dec31_dec_sub16_br[0:0] + attribute \src "issuer_ls180.v:88581.3-88590.6" + wire width 3 $0\dec31_dec_sub16_cr_in[2:0] + attribute \src "issuer_ls180.v:88591.3-88600.6" + wire width 3 $0\dec31_dec_sub16_cr_out[2:0] + attribute \src "issuer_ls180.v:88401.3-88410.6" + wire width 2 $0\dec31_dec_sub16_cry_in[1:0] + attribute \src "issuer_ls180.v:88441.3-88450.6" + wire $0\dec31_dec_sub16_cry_out[0:0] + attribute \src "issuer_ls180.v:88531.3-88540.6" + wire width 5 $0\dec31_dec_sub16_form[4:0] + attribute \src "issuer_ls180.v:88361.3-88370.6" + wire width 12 $0\dec31_dec_sub16_function_unit[11:0] + attribute \src "issuer_ls180.v:88541.3-88550.6" + wire width 3 $0\dec31_dec_sub16_in1_sel[2:0] + attribute \src "issuer_ls180.v:88551.3-88560.6" + wire width 4 $0\dec31_dec_sub16_in2_sel[3:0] + attribute \src "issuer_ls180.v:88561.3-88570.6" + wire width 2 $0\dec31_dec_sub16_in3_sel[1:0] + attribute \src "issuer_ls180.v:88471.3-88480.6" + wire width 7 $0\dec31_dec_sub16_internal_op[6:0] + attribute \src "issuer_ls180.v:88421.3-88430.6" + wire $0\dec31_dec_sub16_inv_a[0:0] + attribute \src "issuer_ls180.v:88431.3-88440.6" + wire $0\dec31_dec_sub16_inv_out[0:0] + attribute \src "issuer_ls180.v:88491.3-88500.6" + wire $0\dec31_dec_sub16_is_32b[0:0] + attribute \src "issuer_ls180.v:88371.3-88380.6" + wire width 4 $0\dec31_dec_sub16_ldst_len[3:0] + attribute \src "issuer_ls180.v:88511.3-88520.6" + wire $0\dec31_dec_sub16_lk[0:0] + attribute \src "issuer_ls180.v:88571.3-88580.6" + wire width 2 $0\dec31_dec_sub16_out_sel[1:0] + attribute \src "issuer_ls180.v:88391.3-88400.6" + wire width 2 $0\dec31_dec_sub16_rc_sel[1:0] + attribute \src "issuer_ls180.v:88481.3-88490.6" + wire $0\dec31_dec_sub16_rsrv[0:0] + attribute \src "issuer_ls180.v:88521.3-88530.6" + wire $0\dec31_dec_sub16_sgl_pipe[0:0] + attribute \src "issuer_ls180.v:88501.3-88510.6" + wire $0\dec31_dec_sub16_sgn[0:0] + attribute \src "issuer_ls180.v:88461.3-88470.6" + wire $0\dec31_dec_sub16_sgn_ext[0:0] + attribute \src "issuer_ls180.v:88381.3-88390.6" + wire width 2 $0\dec31_dec_sub16_upd[1:0] + attribute \src "issuer_ls180.v:88104.7-88104.20" + wire $0\initial[0:0] + attribute \src "issuer_ls180.v:88411.3-88420.6" + wire width 8 $1\dec31_dec_sub16_asmcode[7:0] + attribute \src "issuer_ls180.v:88451.3-88460.6" + wire $1\dec31_dec_sub16_br[0:0] + attribute \src "issuer_ls180.v:88581.3-88590.6" + wire width 3 $1\dec31_dec_sub16_cr_in[2:0] + attribute \src "issuer_ls180.v:88591.3-88600.6" + wire width 3 $1\dec31_dec_sub16_cr_out[2:0] + attribute \src "issuer_ls180.v:88401.3-88410.6" + wire width 2 $1\dec31_dec_sub16_cry_in[1:0] + attribute \src "issuer_ls180.v:88441.3-88450.6" + wire $1\dec31_dec_sub16_cry_out[0:0] + attribute \src "issuer_ls180.v:88531.3-88540.6" + wire width 5 $1\dec31_dec_sub16_form[4:0] + attribute \src "issuer_ls180.v:88361.3-88370.6" + wire width 12 $1\dec31_dec_sub16_function_unit[11:0] + attribute \src "issuer_ls180.v:88541.3-88550.6" + wire width 3 $1\dec31_dec_sub16_in1_sel[2:0] + attribute \src "issuer_ls180.v:88551.3-88560.6" + wire width 4 $1\dec31_dec_sub16_in2_sel[3:0] + attribute \src "issuer_ls180.v:88561.3-88570.6" + wire width 2 $1\dec31_dec_sub16_in3_sel[1:0] + attribute \src "issuer_ls180.v:88471.3-88480.6" + wire width 7 $1\dec31_dec_sub16_internal_op[6:0] + attribute \src "issuer_ls180.v:88421.3-88430.6" + wire $1\dec31_dec_sub16_inv_a[0:0] + attribute \src "issuer_ls180.v:88431.3-88440.6" + wire $1\dec31_dec_sub16_inv_out[0:0] + attribute \src "issuer_ls180.v:88491.3-88500.6" + wire $1\dec31_dec_sub16_is_32b[0:0] + attribute \src "issuer_ls180.v:88371.3-88380.6" + wire width 4 $1\dec31_dec_sub16_ldst_len[3:0] + attribute \src "issuer_ls180.v:88511.3-88520.6" + wire $1\dec31_dec_sub16_lk[0:0] + attribute \src "issuer_ls180.v:88571.3-88580.6" + wire width 2 $1\dec31_dec_sub16_out_sel[1:0] + attribute \src "issuer_ls180.v:88391.3-88400.6" + wire width 2 $1\dec31_dec_sub16_rc_sel[1:0] + attribute \src "issuer_ls180.v:88481.3-88490.6" + wire $1\dec31_dec_sub16_rsrv[0:0] + attribute \src "issuer_ls180.v:88521.3-88530.6" + wire $1\dec31_dec_sub16_sgl_pipe[0:0] + attribute \src "issuer_ls180.v:88501.3-88510.6" + wire $1\dec31_dec_sub16_sgn[0:0] + attribute \src "issuer_ls180.v:88461.3-88470.6" + wire $1\dec31_dec_sub16_sgn_ext[0:0] + attribute \src "issuer_ls180.v:88381.3-88390.6" + wire width 2 $1\dec31_dec_sub16_upd[1:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 8 output 4 \dec31_dec_sub16_asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 18 \dec31_dec_sub16_br + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 9 \dec31_dec_sub16_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 10 \dec31_dec_sub16_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 14 \dec31_dec_sub16_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 17 \dec31_dec_sub16_cry_out + attribute \enum_base_type "Form" + attribute \enum_value_00000 "NONE" + attribute \enum_value_00001 "I" + attribute \enum_value_00010 "B" + attribute \enum_value_00011 "SC" + attribute \enum_value_00100 "D" + attribute \enum_value_00101 "DS" + attribute \enum_value_00110 "DQ" + attribute \enum_value_00111 "DX" + attribute \enum_value_01000 "X" + attribute \enum_value_01001 "XL" + attribute \enum_value_01010 "XFX" + attribute \enum_value_01011 "XFL" + attribute \enum_value_01100 "XX1" + attribute \enum_value_01101 "XX2" + attribute \enum_value_01110 "XX3" + attribute \enum_value_01111 "XX4" + attribute \enum_value_10000 "XS" + attribute \enum_value_10001 "XO" + attribute \enum_value_10010 "A" + attribute \enum_value_10011 "M" + attribute \enum_value_10100 "MD" + attribute \enum_value_10101 "MDS" + attribute \enum_value_10110 "VA" + attribute \enum_value_10111 "VC" + attribute \enum_value_11000 "VX" + attribute \enum_value_11001 "EVX" + attribute \enum_value_11010 "EVS" + attribute \enum_value_11011 "Z22" + attribute \enum_value_11100 "Z23" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 5 output 3 \dec31_dec_sub16_form + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 12 output 1 \dec31_dec_sub16_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 5 \dec31_dec_sub16_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 output 6 \dec31_dec_sub16_in2_sel + attribute \enum_base_type "In3Sel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RS" + attribute \enum_value_10 "RB" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 7 \dec31_dec_sub16_in3_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 7 output 2 \dec31_dec_sub16_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 15 \dec31_dec_sub16_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 16 \dec31_dec_sub16_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 21 \dec31_dec_sub16_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 output 11 \dec31_dec_sub16_ldst_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 23 \dec31_dec_sub16_lk + attribute \enum_base_type "OutSel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RT" + attribute \enum_value_10 "RA" + attribute \enum_value_11 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 8 \dec31_dec_sub16_out_sel + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 13 \dec31_dec_sub16_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 20 \dec31_dec_sub16_rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 24 \dec31_dec_sub16_sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 22 \dec31_dec_sub16_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 19 \dec31_dec_sub16_sgn_ext + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 12 \dec31_dec_sub16_upd + attribute \src "issuer_ls180.v:88104.7-88104.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + wire width 32 input 25 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:320" + wire width 5 \opcode_switch + attribute \src "issuer_ls180.v:88104.7-88104.20" + process $proc$issuer_ls180.v:88104$3720 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "issuer_ls180.v:88361.3-88370.6" + process $proc$issuer_ls180.v:88361$3696 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub16_function_unit[11:0] $1\dec31_dec_sub16_function_unit[11:0] + attribute \src "issuer_ls180.v:88362.5-88362.29" + switch \initial + attribute \src "issuer_ls180.v:88362.9-88362.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub16_function_unit[11:0] 12'000001000000 + case + assign $1\dec31_dec_sub16_function_unit[11:0] 12'000000000000 + end + sync always + update \dec31_dec_sub16_function_unit $0\dec31_dec_sub16_function_unit[11:0] + end + attribute \src "issuer_ls180.v:88371.3-88380.6" + process $proc$issuer_ls180.v:88371$3697 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub16_ldst_len[3:0] $1\dec31_dec_sub16_ldst_len[3:0] + attribute \src "issuer_ls180.v:88372.5-88372.29" + switch \initial + attribute \src "issuer_ls180.v:88372.9-88372.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub16_ldst_len[3:0] 4'0000 + case + assign $1\dec31_dec_sub16_ldst_len[3:0] 4'0000 + end + sync always + update \dec31_dec_sub16_ldst_len $0\dec31_dec_sub16_ldst_len[3:0] + end + attribute \src "issuer_ls180.v:88381.3-88390.6" + process $proc$issuer_ls180.v:88381$3698 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub16_upd[1:0] $1\dec31_dec_sub16_upd[1:0] + attribute \src "issuer_ls180.v:88382.5-88382.29" + switch \initial + attribute \src "issuer_ls180.v:88382.9-88382.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub16_upd[1:0] 2'00 + case + assign $1\dec31_dec_sub16_upd[1:0] 2'00 + end + sync always + update \dec31_dec_sub16_upd $0\dec31_dec_sub16_upd[1:0] + end + attribute \src "issuer_ls180.v:88391.3-88400.6" + process $proc$issuer_ls180.v:88391$3699 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub16_rc_sel[1:0] $1\dec31_dec_sub16_rc_sel[1:0] + attribute \src "issuer_ls180.v:88392.5-88392.29" + switch \initial + attribute \src "issuer_ls180.v:88392.9-88392.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub16_rc_sel[1:0] 2'00 + case + assign $1\dec31_dec_sub16_rc_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub16_rc_sel $0\dec31_dec_sub16_rc_sel[1:0] + end + attribute \src "issuer_ls180.v:88401.3-88410.6" + process $proc$issuer_ls180.v:88401$3700 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub16_cry_in[1:0] $1\dec31_dec_sub16_cry_in[1:0] + attribute \src "issuer_ls180.v:88402.5-88402.29" + switch \initial + attribute \src "issuer_ls180.v:88402.9-88402.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub16_cry_in[1:0] 2'00 + case + assign $1\dec31_dec_sub16_cry_in[1:0] 2'00 + end + sync always + update \dec31_dec_sub16_cry_in $0\dec31_dec_sub16_cry_in[1:0] + end + attribute \src "issuer_ls180.v:88411.3-88420.6" + process $proc$issuer_ls180.v:88411$3701 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub16_asmcode[7:0] $1\dec31_dec_sub16_asmcode[7:0] + attribute \src "issuer_ls180.v:88412.5-88412.29" + switch \initial + attribute \src "issuer_ls180.v:88412.9-88412.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub16_asmcode[7:0] 8'01110110 + case + assign $1\dec31_dec_sub16_asmcode[7:0] 8'00000000 + end + sync always + update \dec31_dec_sub16_asmcode $0\dec31_dec_sub16_asmcode[7:0] + end + attribute \src "issuer_ls180.v:88421.3-88430.6" + process $proc$issuer_ls180.v:88421$3702 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub16_inv_a[0:0] $1\dec31_dec_sub16_inv_a[0:0] + attribute \src "issuer_ls180.v:88422.5-88422.29" + switch \initial + attribute \src "issuer_ls180.v:88422.9-88422.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub16_inv_a[0:0] 1'0 + case + assign $1\dec31_dec_sub16_inv_a[0:0] 1'0 + end + sync always + update \dec31_dec_sub16_inv_a $0\dec31_dec_sub16_inv_a[0:0] + end + attribute \src "issuer_ls180.v:88431.3-88440.6" + process $proc$issuer_ls180.v:88431$3703 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub16_inv_out[0:0] $1\dec31_dec_sub16_inv_out[0:0] + attribute \src "issuer_ls180.v:88432.5-88432.29" + switch \initial + attribute \src "issuer_ls180.v:88432.9-88432.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub16_inv_out[0:0] 1'0 + case + assign $1\dec31_dec_sub16_inv_out[0:0] 1'0 + end + sync always + update \dec31_dec_sub16_inv_out $0\dec31_dec_sub16_inv_out[0:0] + end + attribute \src "issuer_ls180.v:88441.3-88450.6" + process $proc$issuer_ls180.v:88441$3704 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub16_cry_out[0:0] $1\dec31_dec_sub16_cry_out[0:0] + attribute \src "issuer_ls180.v:88442.5-88442.29" + switch \initial + attribute \src "issuer_ls180.v:88442.9-88442.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub16_cry_out[0:0] 1'0 + case + assign $1\dec31_dec_sub16_cry_out[0:0] 1'0 + end + sync always + update \dec31_dec_sub16_cry_out $0\dec31_dec_sub16_cry_out[0:0] + end + attribute \src "issuer_ls180.v:88451.3-88460.6" + process $proc$issuer_ls180.v:88451$3705 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub16_br[0:0] $1\dec31_dec_sub16_br[0:0] + attribute \src "issuer_ls180.v:88452.5-88452.29" + switch \initial + attribute \src "issuer_ls180.v:88452.9-88452.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub16_br[0:0] 1'0 + case + assign $1\dec31_dec_sub16_br[0:0] 1'0 + end + sync always + update \dec31_dec_sub16_br $0\dec31_dec_sub16_br[0:0] + end + attribute \src "issuer_ls180.v:88461.3-88470.6" + process $proc$issuer_ls180.v:88461$3706 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub16_sgn_ext[0:0] $1\dec31_dec_sub16_sgn_ext[0:0] + attribute \src "issuer_ls180.v:88462.5-88462.29" + switch \initial + attribute \src "issuer_ls180.v:88462.9-88462.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub16_sgn_ext[0:0] 1'0 + case + assign $1\dec31_dec_sub16_sgn_ext[0:0] 1'0 + end + sync always + update \dec31_dec_sub16_sgn_ext $0\dec31_dec_sub16_sgn_ext[0:0] + end + attribute \src "issuer_ls180.v:88471.3-88480.6" + process $proc$issuer_ls180.v:88471$3707 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub16_internal_op[6:0] $1\dec31_dec_sub16_internal_op[6:0] + attribute \src "issuer_ls180.v:88472.5-88472.29" + switch \initial + attribute \src "issuer_ls180.v:88472.9-88472.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub16_internal_op[6:0] 7'0110000 + case + assign $1\dec31_dec_sub16_internal_op[6:0] 7'0000000 + end + sync always + update \dec31_dec_sub16_internal_op $0\dec31_dec_sub16_internal_op[6:0] + end + attribute \src "issuer_ls180.v:88481.3-88490.6" + process $proc$issuer_ls180.v:88481$3708 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub16_rsrv[0:0] $1\dec31_dec_sub16_rsrv[0:0] + attribute \src "issuer_ls180.v:88482.5-88482.29" + switch \initial + attribute \src "issuer_ls180.v:88482.9-88482.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub16_rsrv[0:0] 1'0 + case + assign $1\dec31_dec_sub16_rsrv[0:0] 1'0 + end + sync always + update \dec31_dec_sub16_rsrv $0\dec31_dec_sub16_rsrv[0:0] + end + attribute \src "issuer_ls180.v:88491.3-88500.6" + process $proc$issuer_ls180.v:88491$3709 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub16_is_32b[0:0] $1\dec31_dec_sub16_is_32b[0:0] + attribute \src "issuer_ls180.v:88492.5-88492.29" + switch \initial + attribute \src "issuer_ls180.v:88492.9-88492.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub16_is_32b[0:0] 1'0 + case + assign $1\dec31_dec_sub16_is_32b[0:0] 1'0 + end + sync always + update \dec31_dec_sub16_is_32b $0\dec31_dec_sub16_is_32b[0:0] + end + attribute \src "issuer_ls180.v:88501.3-88510.6" + process $proc$issuer_ls180.v:88501$3710 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub16_sgn[0:0] $1\dec31_dec_sub16_sgn[0:0] + attribute \src "issuer_ls180.v:88502.5-88502.29" + switch \initial + attribute \src "issuer_ls180.v:88502.9-88502.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub16_sgn[0:0] 1'0 + case + assign $1\dec31_dec_sub16_sgn[0:0] 1'0 + end + sync always + update \dec31_dec_sub16_sgn $0\dec31_dec_sub16_sgn[0:0] + end + attribute \src "issuer_ls180.v:88511.3-88520.6" + process $proc$issuer_ls180.v:88511$3711 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub16_lk[0:0] $1\dec31_dec_sub16_lk[0:0] + attribute \src "issuer_ls180.v:88512.5-88512.29" + switch \initial + attribute \src "issuer_ls180.v:88512.9-88512.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub16_lk[0:0] 1'0 + case + assign $1\dec31_dec_sub16_lk[0:0] 1'0 + end + sync always + update \dec31_dec_sub16_lk $0\dec31_dec_sub16_lk[0:0] + end + attribute \src "issuer_ls180.v:88521.3-88530.6" + process $proc$issuer_ls180.v:88521$3712 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub16_sgl_pipe[0:0] $1\dec31_dec_sub16_sgl_pipe[0:0] + attribute \src "issuer_ls180.v:88522.5-88522.29" + switch \initial + attribute \src "issuer_ls180.v:88522.9-88522.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub16_sgl_pipe[0:0] 1'0 + case + assign $1\dec31_dec_sub16_sgl_pipe[0:0] 1'0 + end + sync always + update \dec31_dec_sub16_sgl_pipe $0\dec31_dec_sub16_sgl_pipe[0:0] + end + attribute \src "issuer_ls180.v:88531.3-88540.6" + process $proc$issuer_ls180.v:88531$3713 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub16_form[4:0] $1\dec31_dec_sub16_form[4:0] + attribute \src "issuer_ls180.v:88532.5-88532.29" + switch \initial + attribute \src "issuer_ls180.v:88532.9-88532.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub16_form[4:0] 5'01010 + case + assign $1\dec31_dec_sub16_form[4:0] 5'00000 + end + sync always + update \dec31_dec_sub16_form $0\dec31_dec_sub16_form[4:0] + end + attribute \src "issuer_ls180.v:88541.3-88550.6" + process $proc$issuer_ls180.v:88541$3714 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub16_in1_sel[2:0] $1\dec31_dec_sub16_in1_sel[2:0] + attribute \src "issuer_ls180.v:88542.5-88542.29" + switch \initial + attribute \src "issuer_ls180.v:88542.9-88542.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub16_in1_sel[2:0] 3'100 + case + assign $1\dec31_dec_sub16_in1_sel[2:0] 3'000 + end + sync always + update \dec31_dec_sub16_in1_sel $0\dec31_dec_sub16_in1_sel[2:0] + end + attribute \src "issuer_ls180.v:88551.3-88560.6" + process $proc$issuer_ls180.v:88551$3715 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub16_in2_sel[3:0] $1\dec31_dec_sub16_in2_sel[3:0] + attribute \src "issuer_ls180.v:88552.5-88552.29" + switch \initial + attribute \src "issuer_ls180.v:88552.9-88552.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub16_in2_sel[3:0] 4'0000 + case + assign $1\dec31_dec_sub16_in2_sel[3:0] 4'0000 + end + sync always + update \dec31_dec_sub16_in2_sel $0\dec31_dec_sub16_in2_sel[3:0] + end + attribute \src "issuer_ls180.v:88561.3-88570.6" + process $proc$issuer_ls180.v:88561$3716 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub16_in3_sel[1:0] $1\dec31_dec_sub16_in3_sel[1:0] + attribute \src "issuer_ls180.v:88562.5-88562.29" + switch \initial + attribute \src "issuer_ls180.v:88562.9-88562.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub16_in3_sel[1:0] 2'00 + case + assign $1\dec31_dec_sub16_in3_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub16_in3_sel $0\dec31_dec_sub16_in3_sel[1:0] + end + attribute \src "issuer_ls180.v:88571.3-88580.6" + process $proc$issuer_ls180.v:88571$3717 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub16_out_sel[1:0] $1\dec31_dec_sub16_out_sel[1:0] + attribute \src "issuer_ls180.v:88572.5-88572.29" + switch \initial + attribute \src "issuer_ls180.v:88572.9-88572.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub16_out_sel[1:0] 2'00 + case + assign $1\dec31_dec_sub16_out_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub16_out_sel $0\dec31_dec_sub16_out_sel[1:0] + end + attribute \src "issuer_ls180.v:88581.3-88590.6" + process $proc$issuer_ls180.v:88581$3718 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub16_cr_in[2:0] $1\dec31_dec_sub16_cr_in[2:0] + attribute \src "issuer_ls180.v:88582.5-88582.29" + switch \initial + attribute \src "issuer_ls180.v:88582.9-88582.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub16_cr_in[2:0] 3'110 + case + assign $1\dec31_dec_sub16_cr_in[2:0] 3'000 + end + sync always + update \dec31_dec_sub16_cr_in $0\dec31_dec_sub16_cr_in[2:0] + end + attribute \src "issuer_ls180.v:88591.3-88600.6" + process $proc$issuer_ls180.v:88591$3719 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub16_cr_out[2:0] $1\dec31_dec_sub16_cr_out[2:0] + attribute \src "issuer_ls180.v:88592.5-88592.29" + switch \initial + attribute \src "issuer_ls180.v:88592.9-88592.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub16_cr_out[2:0] 3'100 + case + assign $1\dec31_dec_sub16_cr_out[2:0] 3'000 + end + sync always + update \dec31_dec_sub16_cr_out $0\dec31_dec_sub16_cr_out[2:0] + end + connect \opcode_switch \opcode_in [10:6] +end +attribute \src "issuer_ls180.v:88606.1-89177.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.dec2.dec.dec31.dec31_dec_sub18" +attribute \generator "nMigen" +module \dec31_dec_sub18 + attribute \src "issuer_ls180.v:88929.3-88941.6" + wire width 8 $0\dec31_dec_sub18_asmcode[7:0] + attribute \src "issuer_ls180.v:88981.3-88993.6" + wire $0\dec31_dec_sub18_br[0:0] + attribute \src "issuer_ls180.v:89150.3-89162.6" + wire width 3 $0\dec31_dec_sub18_cr_in[2:0] + attribute \src "issuer_ls180.v:89163.3-89175.6" + wire width 3 $0\dec31_dec_sub18_cr_out[2:0] + attribute \src "issuer_ls180.v:88916.3-88928.6" + wire width 2 $0\dec31_dec_sub18_cry_in[1:0] + attribute \src "issuer_ls180.v:88968.3-88980.6" + wire $0\dec31_dec_sub18_cry_out[0:0] + attribute \src "issuer_ls180.v:89085.3-89097.6" + wire width 5 $0\dec31_dec_sub18_form[4:0] + attribute \src "issuer_ls180.v:88864.3-88876.6" + wire width 12 $0\dec31_dec_sub18_function_unit[11:0] + attribute \src "issuer_ls180.v:89098.3-89110.6" + wire width 3 $0\dec31_dec_sub18_in1_sel[2:0] + attribute \src "issuer_ls180.v:89111.3-89123.6" + wire width 4 $0\dec31_dec_sub18_in2_sel[3:0] + attribute \src "issuer_ls180.v:89124.3-89136.6" + wire width 2 $0\dec31_dec_sub18_in3_sel[1:0] + attribute \src "issuer_ls180.v:89007.3-89019.6" + wire width 7 $0\dec31_dec_sub18_internal_op[6:0] + attribute \src "issuer_ls180.v:88942.3-88954.6" + wire $0\dec31_dec_sub18_inv_a[0:0] + attribute \src "issuer_ls180.v:88955.3-88967.6" + wire $0\dec31_dec_sub18_inv_out[0:0] + attribute \src "issuer_ls180.v:89033.3-89045.6" + wire $0\dec31_dec_sub18_is_32b[0:0] + attribute \src "issuer_ls180.v:88877.3-88889.6" + wire width 4 $0\dec31_dec_sub18_ldst_len[3:0] + attribute \src "issuer_ls180.v:89059.3-89071.6" + wire $0\dec31_dec_sub18_lk[0:0] + attribute \src "issuer_ls180.v:89137.3-89149.6" + wire width 2 $0\dec31_dec_sub18_out_sel[1:0] + attribute \src "issuer_ls180.v:88903.3-88915.6" + wire width 2 $0\dec31_dec_sub18_rc_sel[1:0] + attribute \src "issuer_ls180.v:89020.3-89032.6" + wire $0\dec31_dec_sub18_rsrv[0:0] + attribute \src "issuer_ls180.v:89072.3-89084.6" + wire $0\dec31_dec_sub18_sgl_pipe[0:0] + attribute \src "issuer_ls180.v:89046.3-89058.6" + wire $0\dec31_dec_sub18_sgn[0:0] + attribute \src "issuer_ls180.v:88994.3-89006.6" + wire $0\dec31_dec_sub18_sgn_ext[0:0] + attribute \src "issuer_ls180.v:88890.3-88902.6" + wire width 2 $0\dec31_dec_sub18_upd[1:0] + attribute \src "issuer_ls180.v:88607.7-88607.20" + wire $0\initial[0:0] + attribute \src "issuer_ls180.v:88929.3-88941.6" + wire width 8 $1\dec31_dec_sub18_asmcode[7:0] + attribute \src "issuer_ls180.v:88981.3-88993.6" + wire $1\dec31_dec_sub18_br[0:0] + attribute \src "issuer_ls180.v:89150.3-89162.6" + wire width 3 $1\dec31_dec_sub18_cr_in[2:0] + attribute \src "issuer_ls180.v:89163.3-89175.6" + wire width 3 $1\dec31_dec_sub18_cr_out[2:0] + attribute \src "issuer_ls180.v:88916.3-88928.6" + wire width 2 $1\dec31_dec_sub18_cry_in[1:0] + attribute \src "issuer_ls180.v:88968.3-88980.6" + wire $1\dec31_dec_sub18_cry_out[0:0] + attribute \src "issuer_ls180.v:89085.3-89097.6" + wire width 5 $1\dec31_dec_sub18_form[4:0] + attribute \src "issuer_ls180.v:88864.3-88876.6" + wire width 12 $1\dec31_dec_sub18_function_unit[11:0] + attribute \src "issuer_ls180.v:89098.3-89110.6" + wire width 3 $1\dec31_dec_sub18_in1_sel[2:0] + attribute \src "issuer_ls180.v:89111.3-89123.6" + wire width 4 $1\dec31_dec_sub18_in2_sel[3:0] + attribute \src "issuer_ls180.v:89124.3-89136.6" + wire width 2 $1\dec31_dec_sub18_in3_sel[1:0] + attribute \src "issuer_ls180.v:89007.3-89019.6" + wire width 7 $1\dec31_dec_sub18_internal_op[6:0] + attribute \src "issuer_ls180.v:88942.3-88954.6" + wire $1\dec31_dec_sub18_inv_a[0:0] + attribute \src "issuer_ls180.v:88955.3-88967.6" + wire $1\dec31_dec_sub18_inv_out[0:0] + attribute \src "issuer_ls180.v:89033.3-89045.6" + wire $1\dec31_dec_sub18_is_32b[0:0] + attribute \src "issuer_ls180.v:88877.3-88889.6" + wire width 4 $1\dec31_dec_sub18_ldst_len[3:0] + attribute \src "issuer_ls180.v:89059.3-89071.6" + wire $1\dec31_dec_sub18_lk[0:0] + attribute \src "issuer_ls180.v:89137.3-89149.6" + wire width 2 $1\dec31_dec_sub18_out_sel[1:0] + attribute \src "issuer_ls180.v:88903.3-88915.6" + wire width 2 $1\dec31_dec_sub18_rc_sel[1:0] + attribute \src "issuer_ls180.v:89020.3-89032.6" + wire $1\dec31_dec_sub18_rsrv[0:0] + attribute \src "issuer_ls180.v:89072.3-89084.6" + wire $1\dec31_dec_sub18_sgl_pipe[0:0] + attribute \src "issuer_ls180.v:89046.3-89058.6" + wire $1\dec31_dec_sub18_sgn[0:0] + attribute \src "issuer_ls180.v:88994.3-89006.6" + wire $1\dec31_dec_sub18_sgn_ext[0:0] + attribute \src "issuer_ls180.v:88890.3-88902.6" + wire width 2 $1\dec31_dec_sub18_upd[1:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 8 output 4 \dec31_dec_sub18_asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 18 \dec31_dec_sub18_br + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 9 \dec31_dec_sub18_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 10 \dec31_dec_sub18_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 14 \dec31_dec_sub18_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 17 \dec31_dec_sub18_cry_out + attribute \enum_base_type "Form" + attribute \enum_value_00000 "NONE" + attribute \enum_value_00001 "I" + attribute \enum_value_00010 "B" + attribute \enum_value_00011 "SC" + attribute \enum_value_00100 "D" + attribute \enum_value_00101 "DS" + attribute \enum_value_00110 "DQ" + attribute \enum_value_00111 "DX" + attribute \enum_value_01000 "X" + attribute \enum_value_01001 "XL" + attribute \enum_value_01010 "XFX" + attribute \enum_value_01011 "XFL" + attribute \enum_value_01100 "XX1" + attribute \enum_value_01101 "XX2" + attribute \enum_value_01110 "XX3" + attribute \enum_value_01111 "XX4" + attribute \enum_value_10000 "XS" + attribute \enum_value_10001 "XO" + attribute \enum_value_10010 "A" + attribute \enum_value_10011 "M" + attribute \enum_value_10100 "MD" + attribute \enum_value_10101 "MDS" + attribute \enum_value_10110 "VA" + attribute \enum_value_10111 "VC" + attribute \enum_value_11000 "VX" + attribute \enum_value_11001 "EVX" + attribute \enum_value_11010 "EVS" + attribute \enum_value_11011 "Z22" + attribute \enum_value_11100 "Z23" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 5 output 3 \dec31_dec_sub18_form + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 12 output 1 \dec31_dec_sub18_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 5 \dec31_dec_sub18_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 output 6 \dec31_dec_sub18_in2_sel + attribute \enum_base_type "In3Sel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RS" + attribute \enum_value_10 "RB" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 7 \dec31_dec_sub18_in3_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 7 output 2 \dec31_dec_sub18_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 15 \dec31_dec_sub18_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 16 \dec31_dec_sub18_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 21 \dec31_dec_sub18_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 output 11 \dec31_dec_sub18_ldst_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 23 \dec31_dec_sub18_lk + attribute \enum_base_type "OutSel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RT" + attribute \enum_value_10 "RA" + attribute \enum_value_11 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 8 \dec31_dec_sub18_out_sel + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 13 \dec31_dec_sub18_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 20 \dec31_dec_sub18_rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 24 \dec31_dec_sub18_sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 22 \dec31_dec_sub18_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 19 \dec31_dec_sub18_sgn_ext + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 12 \dec31_dec_sub18_upd + attribute \src "issuer_ls180.v:88607.7-88607.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + wire width 32 input 25 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:320" + wire width 5 \opcode_switch + attribute \src "issuer_ls180.v:88607.7-88607.20" + process $proc$issuer_ls180.v:88607$3745 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "issuer_ls180.v:88864.3-88876.6" + process $proc$issuer_ls180.v:88864$3721 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub18_function_unit[11:0] $1\dec31_dec_sub18_function_unit[11:0] + attribute \src "issuer_ls180.v:88865.5-88865.29" + switch \initial + attribute \src "issuer_ls180.v:88865.9-88865.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub18_function_unit[11:0] 12'000010000000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub18_function_unit[11:0] 12'000010000000 + case + assign $1\dec31_dec_sub18_function_unit[11:0] 12'000000000000 + end + sync always + update \dec31_dec_sub18_function_unit $0\dec31_dec_sub18_function_unit[11:0] + end + attribute \src "issuer_ls180.v:88877.3-88889.6" + process $proc$issuer_ls180.v:88877$3722 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub18_ldst_len[3:0] $1\dec31_dec_sub18_ldst_len[3:0] + attribute \src "issuer_ls180.v:88878.5-88878.29" + switch \initial + attribute \src "issuer_ls180.v:88878.9-88878.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub18_ldst_len[3:0] 4'0000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub18_ldst_len[3:0] 4'0000 + case + assign $1\dec31_dec_sub18_ldst_len[3:0] 4'0000 + end + sync always + update \dec31_dec_sub18_ldst_len $0\dec31_dec_sub18_ldst_len[3:0] + end + attribute \src "issuer_ls180.v:88890.3-88902.6" + process $proc$issuer_ls180.v:88890$3723 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub18_upd[1:0] $1\dec31_dec_sub18_upd[1:0] + attribute \src "issuer_ls180.v:88891.5-88891.29" + switch \initial + attribute \src "issuer_ls180.v:88891.9-88891.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub18_upd[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub18_upd[1:0] 2'00 + case + assign $1\dec31_dec_sub18_upd[1:0] 2'00 + end + sync always + update \dec31_dec_sub18_upd $0\dec31_dec_sub18_upd[1:0] + end + attribute \src "issuer_ls180.v:88903.3-88915.6" + process $proc$issuer_ls180.v:88903$3724 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub18_rc_sel[1:0] $1\dec31_dec_sub18_rc_sel[1:0] + attribute \src "issuer_ls180.v:88904.5-88904.29" + switch \initial + attribute \src "issuer_ls180.v:88904.9-88904.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub18_rc_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub18_rc_sel[1:0] 2'00 + case + assign $1\dec31_dec_sub18_rc_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub18_rc_sel $0\dec31_dec_sub18_rc_sel[1:0] + end + attribute \src "issuer_ls180.v:88916.3-88928.6" + process $proc$issuer_ls180.v:88916$3725 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub18_cry_in[1:0] $1\dec31_dec_sub18_cry_in[1:0] + attribute \src "issuer_ls180.v:88917.5-88917.29" + switch \initial + attribute \src "issuer_ls180.v:88917.9-88917.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub18_cry_in[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub18_cry_in[1:0] 2'00 + case + assign $1\dec31_dec_sub18_cry_in[1:0] 2'00 + end + sync always + update \dec31_dec_sub18_cry_in $0\dec31_dec_sub18_cry_in[1:0] + end + attribute \src "issuer_ls180.v:88929.3-88941.6" + process $proc$issuer_ls180.v:88929$3726 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub18_asmcode[7:0] $1\dec31_dec_sub18_asmcode[7:0] + attribute \src "issuer_ls180.v:88930.5-88930.29" + switch \initial + attribute \src "issuer_ls180.v:88930.9-88930.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub18_asmcode[7:0] 8'01111000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub18_asmcode[7:0] 8'01110111 + case + assign $1\dec31_dec_sub18_asmcode[7:0] 8'00000000 + end + sync always + update \dec31_dec_sub18_asmcode $0\dec31_dec_sub18_asmcode[7:0] + end + attribute \src "issuer_ls180.v:88942.3-88954.6" + process $proc$issuer_ls180.v:88942$3727 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub18_inv_a[0:0] $1\dec31_dec_sub18_inv_a[0:0] + attribute \src "issuer_ls180.v:88943.5-88943.29" + switch \initial + attribute \src "issuer_ls180.v:88943.9-88943.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub18_inv_a[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub18_inv_a[0:0] 1'0 + case + assign $1\dec31_dec_sub18_inv_a[0:0] 1'0 + end + sync always + update \dec31_dec_sub18_inv_a $0\dec31_dec_sub18_inv_a[0:0] + end + attribute \src "issuer_ls180.v:88955.3-88967.6" + process $proc$issuer_ls180.v:88955$3728 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub18_inv_out[0:0] $1\dec31_dec_sub18_inv_out[0:0] + attribute \src "issuer_ls180.v:88956.5-88956.29" + switch \initial + attribute \src "issuer_ls180.v:88956.9-88956.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub18_inv_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub18_inv_out[0:0] 1'0 + case + assign $1\dec31_dec_sub18_inv_out[0:0] 1'0 + end + sync always + update \dec31_dec_sub18_inv_out $0\dec31_dec_sub18_inv_out[0:0] + end + attribute \src "issuer_ls180.v:88968.3-88980.6" + process $proc$issuer_ls180.v:88968$3729 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub18_cry_out[0:0] $1\dec31_dec_sub18_cry_out[0:0] + attribute \src "issuer_ls180.v:88969.5-88969.29" + switch \initial + attribute \src "issuer_ls180.v:88969.9-88969.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub18_cry_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub18_cry_out[0:0] 1'0 + case + assign $1\dec31_dec_sub18_cry_out[0:0] 1'0 + end + sync always + update \dec31_dec_sub18_cry_out $0\dec31_dec_sub18_cry_out[0:0] + end + attribute \src "issuer_ls180.v:88981.3-88993.6" + process $proc$issuer_ls180.v:88981$3730 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub18_br[0:0] $1\dec31_dec_sub18_br[0:0] + attribute \src "issuer_ls180.v:88982.5-88982.29" + switch \initial + attribute \src "issuer_ls180.v:88982.9-88982.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub18_br[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub18_br[0:0] 1'0 + case + assign $1\dec31_dec_sub18_br[0:0] 1'0 + end + sync always + update \dec31_dec_sub18_br $0\dec31_dec_sub18_br[0:0] + end + attribute \src "issuer_ls180.v:88994.3-89006.6" + process $proc$issuer_ls180.v:88994$3731 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub18_sgn_ext[0:0] $1\dec31_dec_sub18_sgn_ext[0:0] + attribute \src "issuer_ls180.v:88995.5-88995.29" + switch \initial + attribute \src "issuer_ls180.v:88995.9-88995.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub18_sgn_ext[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub18_sgn_ext[0:0] 1'0 + case + assign $1\dec31_dec_sub18_sgn_ext[0:0] 1'0 + end + sync always + update \dec31_dec_sub18_sgn_ext $0\dec31_dec_sub18_sgn_ext[0:0] + end + attribute \src "issuer_ls180.v:89007.3-89019.6" + process $proc$issuer_ls180.v:89007$3732 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub18_internal_op[6:0] $1\dec31_dec_sub18_internal_op[6:0] + attribute \src "issuer_ls180.v:89008.5-89008.29" + switch \initial + attribute \src "issuer_ls180.v:89008.9-89008.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub18_internal_op[6:0] 7'1001000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub18_internal_op[6:0] 7'1001010 + case + assign $1\dec31_dec_sub18_internal_op[6:0] 7'0000000 + end + sync always + update \dec31_dec_sub18_internal_op $0\dec31_dec_sub18_internal_op[6:0] + end + attribute \src "issuer_ls180.v:89020.3-89032.6" + process $proc$issuer_ls180.v:89020$3733 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub18_rsrv[0:0] $1\dec31_dec_sub18_rsrv[0:0] + attribute \src "issuer_ls180.v:89021.5-89021.29" + switch \initial + attribute \src "issuer_ls180.v:89021.9-89021.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub18_rsrv[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub18_rsrv[0:0] 1'0 + case + assign $1\dec31_dec_sub18_rsrv[0:0] 1'0 + end + sync always + update \dec31_dec_sub18_rsrv $0\dec31_dec_sub18_rsrv[0:0] + end + attribute \src "issuer_ls180.v:89033.3-89045.6" + process $proc$issuer_ls180.v:89033$3734 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub18_is_32b[0:0] $1\dec31_dec_sub18_is_32b[0:0] + attribute \src "issuer_ls180.v:89034.5-89034.29" + switch \initial + attribute \src "issuer_ls180.v:89034.9-89034.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub18_is_32b[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub18_is_32b[0:0] 1'0 + case + assign $1\dec31_dec_sub18_is_32b[0:0] 1'0 + end + sync always + update \dec31_dec_sub18_is_32b $0\dec31_dec_sub18_is_32b[0:0] + end + attribute \src "issuer_ls180.v:89046.3-89058.6" + process $proc$issuer_ls180.v:89046$3735 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub18_sgn[0:0] $1\dec31_dec_sub18_sgn[0:0] + attribute \src "issuer_ls180.v:89047.5-89047.29" + switch \initial + attribute \src "issuer_ls180.v:89047.9-89047.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub18_sgn[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub18_sgn[0:0] 1'0 + case + assign $1\dec31_dec_sub18_sgn[0:0] 1'0 + end + sync always + update \dec31_dec_sub18_sgn $0\dec31_dec_sub18_sgn[0:0] + end + attribute \src "issuer_ls180.v:89059.3-89071.6" + process $proc$issuer_ls180.v:89059$3736 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub18_lk[0:0] $1\dec31_dec_sub18_lk[0:0] + attribute \src "issuer_ls180.v:89060.5-89060.29" + switch \initial + attribute \src "issuer_ls180.v:89060.9-89060.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub18_lk[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub18_lk[0:0] 1'0 + case + assign $1\dec31_dec_sub18_lk[0:0] 1'0 + end + sync always + update \dec31_dec_sub18_lk $0\dec31_dec_sub18_lk[0:0] + end + attribute \src "issuer_ls180.v:89072.3-89084.6" + process $proc$issuer_ls180.v:89072$3737 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub18_sgl_pipe[0:0] $1\dec31_dec_sub18_sgl_pipe[0:0] + attribute \src "issuer_ls180.v:89073.5-89073.29" + switch \initial + attribute \src "issuer_ls180.v:89073.9-89073.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub18_sgl_pipe[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub18_sgl_pipe[0:0] 1'1 + case + assign $1\dec31_dec_sub18_sgl_pipe[0:0] 1'0 + end + sync always + update \dec31_dec_sub18_sgl_pipe $0\dec31_dec_sub18_sgl_pipe[0:0] + end + attribute \src "issuer_ls180.v:89085.3-89097.6" + process $proc$issuer_ls180.v:89085$3738 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub18_form[4:0] $1\dec31_dec_sub18_form[4:0] + attribute \src "issuer_ls180.v:89086.5-89086.29" + switch \initial + attribute \src "issuer_ls180.v:89086.9-89086.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub18_form[4:0] 5'01000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub18_form[4:0] 5'01000 + case + assign $1\dec31_dec_sub18_form[4:0] 5'00000 + end + sync always + update \dec31_dec_sub18_form $0\dec31_dec_sub18_form[4:0] + end + attribute \src "issuer_ls180.v:89098.3-89110.6" + process $proc$issuer_ls180.v:89098$3739 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub18_in1_sel[2:0] $1\dec31_dec_sub18_in1_sel[2:0] + attribute \src "issuer_ls180.v:89099.5-89099.29" + switch \initial + attribute \src "issuer_ls180.v:89099.9-89099.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub18_in1_sel[2:0] 3'100 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub18_in1_sel[2:0] 3'100 + case + assign $1\dec31_dec_sub18_in1_sel[2:0] 3'000 + end + sync always + update \dec31_dec_sub18_in1_sel $0\dec31_dec_sub18_in1_sel[2:0] + end + attribute \src "issuer_ls180.v:89111.3-89123.6" + process $proc$issuer_ls180.v:89111$3740 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub18_in2_sel[3:0] $1\dec31_dec_sub18_in2_sel[3:0] + attribute \src "issuer_ls180.v:89112.5-89112.29" + switch \initial + attribute \src "issuer_ls180.v:89112.9-89112.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub18_in2_sel[3:0] 4'0000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub18_in2_sel[3:0] 4'0000 + case + assign $1\dec31_dec_sub18_in2_sel[3:0] 4'0000 + end + sync always + update \dec31_dec_sub18_in2_sel $0\dec31_dec_sub18_in2_sel[3:0] + end + attribute \src "issuer_ls180.v:89124.3-89136.6" + process $proc$issuer_ls180.v:89124$3741 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub18_in3_sel[1:0] $1\dec31_dec_sub18_in3_sel[1:0] + attribute \src "issuer_ls180.v:89125.5-89125.29" + switch \initial + attribute \src "issuer_ls180.v:89125.9-89125.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub18_in3_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub18_in3_sel[1:0] 2'00 + case + assign $1\dec31_dec_sub18_in3_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub18_in3_sel $0\dec31_dec_sub18_in3_sel[1:0] + end + attribute \src "issuer_ls180.v:89137.3-89149.6" + process $proc$issuer_ls180.v:89137$3742 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub18_out_sel[1:0] $1\dec31_dec_sub18_out_sel[1:0] + attribute \src "issuer_ls180.v:89138.5-89138.29" + switch \initial + attribute \src "issuer_ls180.v:89138.9-89138.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub18_out_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub18_out_sel[1:0] 2'00 + case + assign $1\dec31_dec_sub18_out_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub18_out_sel $0\dec31_dec_sub18_out_sel[1:0] + end + attribute \src "issuer_ls180.v:89150.3-89162.6" + process $proc$issuer_ls180.v:89150$3743 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub18_cr_in[2:0] $1\dec31_dec_sub18_cr_in[2:0] + attribute \src "issuer_ls180.v:89151.5-89151.29" + switch \initial + attribute \src "issuer_ls180.v:89151.9-89151.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub18_cr_in[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub18_cr_in[2:0] 3'000 + case + assign $1\dec31_dec_sub18_cr_in[2:0] 3'000 + end + sync always + update \dec31_dec_sub18_cr_in $0\dec31_dec_sub18_cr_in[2:0] + end + attribute \src "issuer_ls180.v:89163.3-89175.6" + process $proc$issuer_ls180.v:89163$3744 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub18_cr_out[2:0] $1\dec31_dec_sub18_cr_out[2:0] + attribute \src "issuer_ls180.v:89164.5-89164.29" + switch \initial + attribute \src "issuer_ls180.v:89164.9-89164.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub18_cr_out[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub18_cr_out[2:0] 3'000 + case + assign $1\dec31_dec_sub18_cr_out[2:0] 3'000 + end + sync always + update \dec31_dec_sub18_cr_out $0\dec31_dec_sub18_cr_out[2:0] + end + connect \opcode_switch \opcode_in [10:6] +end +attribute \src "issuer_ls180.v:89181.1-89896.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.dec2.dec.dec31.dec31_dec_sub19" +attribute \generator "nMigen" +module \dec31_dec_sub19 + attribute \src "issuer_ls180.v:89534.3-89552.6" + wire width 8 $0\dec31_dec_sub19_asmcode[7:0] + attribute \src "issuer_ls180.v:89610.3-89628.6" + wire $0\dec31_dec_sub19_br[0:0] + attribute \src "issuer_ls180.v:89857.3-89875.6" + wire width 3 $0\dec31_dec_sub19_cr_in[2:0] + attribute \src "issuer_ls180.v:89876.3-89894.6" + wire width 3 $0\dec31_dec_sub19_cr_out[2:0] + attribute \src "issuer_ls180.v:89515.3-89533.6" + wire width 2 $0\dec31_dec_sub19_cry_in[1:0] + attribute \src "issuer_ls180.v:89591.3-89609.6" + wire $0\dec31_dec_sub19_cry_out[0:0] + attribute \src "issuer_ls180.v:89762.3-89780.6" + wire width 5 $0\dec31_dec_sub19_form[4:0] + attribute \src "issuer_ls180.v:89439.3-89457.6" + wire width 12 $0\dec31_dec_sub19_function_unit[11:0] + attribute \src "issuer_ls180.v:89781.3-89799.6" + wire width 3 $0\dec31_dec_sub19_in1_sel[2:0] + attribute \src "issuer_ls180.v:89800.3-89818.6" + wire width 4 $0\dec31_dec_sub19_in2_sel[3:0] + attribute \src "issuer_ls180.v:89819.3-89837.6" + wire width 2 $0\dec31_dec_sub19_in3_sel[1:0] + attribute \src "issuer_ls180.v:89648.3-89666.6" + wire width 7 $0\dec31_dec_sub19_internal_op[6:0] + attribute \src "issuer_ls180.v:89553.3-89571.6" + wire $0\dec31_dec_sub19_inv_a[0:0] + attribute \src "issuer_ls180.v:89572.3-89590.6" + wire $0\dec31_dec_sub19_inv_out[0:0] + attribute \src "issuer_ls180.v:89686.3-89704.6" + wire $0\dec31_dec_sub19_is_32b[0:0] + attribute \src "issuer_ls180.v:89458.3-89476.6" + wire width 4 $0\dec31_dec_sub19_ldst_len[3:0] + attribute \src "issuer_ls180.v:89724.3-89742.6" + wire $0\dec31_dec_sub19_lk[0:0] + attribute \src "issuer_ls180.v:89838.3-89856.6" + wire width 2 $0\dec31_dec_sub19_out_sel[1:0] + attribute \src "issuer_ls180.v:89496.3-89514.6" + wire width 2 $0\dec31_dec_sub19_rc_sel[1:0] + attribute \src "issuer_ls180.v:89667.3-89685.6" + wire $0\dec31_dec_sub19_rsrv[0:0] + attribute \src "issuer_ls180.v:89743.3-89761.6" + wire $0\dec31_dec_sub19_sgl_pipe[0:0] + attribute \src "issuer_ls180.v:89705.3-89723.6" + wire $0\dec31_dec_sub19_sgn[0:0] + attribute \src "issuer_ls180.v:89629.3-89647.6" + wire $0\dec31_dec_sub19_sgn_ext[0:0] + attribute \src "issuer_ls180.v:89477.3-89495.6" + wire width 2 $0\dec31_dec_sub19_upd[1:0] + attribute \src "issuer_ls180.v:89182.7-89182.20" + wire $0\initial[0:0] + attribute \src "issuer_ls180.v:89534.3-89552.6" + wire width 8 $1\dec31_dec_sub19_asmcode[7:0] + attribute \src "issuer_ls180.v:89610.3-89628.6" + wire $1\dec31_dec_sub19_br[0:0] + attribute \src "issuer_ls180.v:89857.3-89875.6" + wire width 3 $1\dec31_dec_sub19_cr_in[2:0] + attribute \src "issuer_ls180.v:89876.3-89894.6" + wire width 3 $1\dec31_dec_sub19_cr_out[2:0] + attribute \src "issuer_ls180.v:89515.3-89533.6" + wire width 2 $1\dec31_dec_sub19_cry_in[1:0] + attribute \src "issuer_ls180.v:89591.3-89609.6" + wire $1\dec31_dec_sub19_cry_out[0:0] + attribute \src "issuer_ls180.v:89762.3-89780.6" + wire width 5 $1\dec31_dec_sub19_form[4:0] + attribute \src "issuer_ls180.v:89439.3-89457.6" + wire width 12 $1\dec31_dec_sub19_function_unit[11:0] + attribute \src "issuer_ls180.v:89781.3-89799.6" + wire width 3 $1\dec31_dec_sub19_in1_sel[2:0] + attribute \src "issuer_ls180.v:89800.3-89818.6" + wire width 4 $1\dec31_dec_sub19_in2_sel[3:0] + attribute \src "issuer_ls180.v:89819.3-89837.6" + wire width 2 $1\dec31_dec_sub19_in3_sel[1:0] + attribute \src "issuer_ls180.v:89648.3-89666.6" + wire width 7 $1\dec31_dec_sub19_internal_op[6:0] + attribute \src "issuer_ls180.v:89553.3-89571.6" + wire $1\dec31_dec_sub19_inv_a[0:0] + attribute \src "issuer_ls180.v:89572.3-89590.6" + wire $1\dec31_dec_sub19_inv_out[0:0] + attribute \src "issuer_ls180.v:89686.3-89704.6" + wire $1\dec31_dec_sub19_is_32b[0:0] + attribute \src "issuer_ls180.v:89458.3-89476.6" + wire width 4 $1\dec31_dec_sub19_ldst_len[3:0] + attribute \src "issuer_ls180.v:89724.3-89742.6" + wire $1\dec31_dec_sub19_lk[0:0] + attribute \src "issuer_ls180.v:89838.3-89856.6" + wire width 2 $1\dec31_dec_sub19_out_sel[1:0] + attribute \src "issuer_ls180.v:89496.3-89514.6" + wire width 2 $1\dec31_dec_sub19_rc_sel[1:0] + attribute \src "issuer_ls180.v:89667.3-89685.6" + wire $1\dec31_dec_sub19_rsrv[0:0] + attribute \src "issuer_ls180.v:89743.3-89761.6" + wire $1\dec31_dec_sub19_sgl_pipe[0:0] + attribute \src "issuer_ls180.v:89705.3-89723.6" + wire $1\dec31_dec_sub19_sgn[0:0] + attribute \src "issuer_ls180.v:89629.3-89647.6" + wire $1\dec31_dec_sub19_sgn_ext[0:0] + attribute \src "issuer_ls180.v:89477.3-89495.6" + wire width 2 $1\dec31_dec_sub19_upd[1:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 8 output 4 \dec31_dec_sub19_asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 18 \dec31_dec_sub19_br + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 9 \dec31_dec_sub19_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 10 \dec31_dec_sub19_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 14 \dec31_dec_sub19_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 17 \dec31_dec_sub19_cry_out + attribute \enum_base_type "Form" + attribute \enum_value_00000 "NONE" + attribute \enum_value_00001 "I" + attribute \enum_value_00010 "B" + attribute \enum_value_00011 "SC" + attribute \enum_value_00100 "D" + attribute \enum_value_00101 "DS" + attribute \enum_value_00110 "DQ" + attribute \enum_value_00111 "DX" + attribute \enum_value_01000 "X" + attribute \enum_value_01001 "XL" + attribute \enum_value_01010 "XFX" + attribute \enum_value_01011 "XFL" + attribute \enum_value_01100 "XX1" + attribute \enum_value_01101 "XX2" + attribute \enum_value_01110 "XX3" + attribute \enum_value_01111 "XX4" + attribute \enum_value_10000 "XS" + attribute \enum_value_10001 "XO" + attribute \enum_value_10010 "A" + attribute \enum_value_10011 "M" + attribute \enum_value_10100 "MD" + attribute \enum_value_10101 "MDS" + attribute \enum_value_10110 "VA" + attribute \enum_value_10111 "VC" + attribute \enum_value_11000 "VX" + attribute \enum_value_11001 "EVX" + attribute \enum_value_11010 "EVS" + attribute \enum_value_11011 "Z22" + attribute \enum_value_11100 "Z23" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 5 output 3 \dec31_dec_sub19_form + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 12 output 1 \dec31_dec_sub19_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 5 \dec31_dec_sub19_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 output 6 \dec31_dec_sub19_in2_sel + attribute \enum_base_type "In3Sel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RS" + attribute \enum_value_10 "RB" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 7 \dec31_dec_sub19_in3_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 7 output 2 \dec31_dec_sub19_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 15 \dec31_dec_sub19_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 16 \dec31_dec_sub19_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 21 \dec31_dec_sub19_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 output 11 \dec31_dec_sub19_ldst_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 23 \dec31_dec_sub19_lk + attribute \enum_base_type "OutSel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RT" + attribute \enum_value_10 "RA" + attribute \enum_value_11 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 8 \dec31_dec_sub19_out_sel + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 13 \dec31_dec_sub19_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 20 \dec31_dec_sub19_rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 24 \dec31_dec_sub19_sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 22 \dec31_dec_sub19_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 19 \dec31_dec_sub19_sgn_ext + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 12 \dec31_dec_sub19_upd + attribute \src "issuer_ls180.v:89182.7-89182.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + wire width 32 input 25 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:320" + wire width 5 \opcode_switch + attribute \src "issuer_ls180.v:89182.7-89182.20" + process $proc$issuer_ls180.v:89182$3770 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "issuer_ls180.v:89439.3-89457.6" + process $proc$issuer_ls180.v:89439$3746 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub19_function_unit[11:0] $1\dec31_dec_sub19_function_unit[11:0] + attribute \src "issuer_ls180.v:89440.5-89440.29" + switch \initial + attribute \src "issuer_ls180.v:89440.9-89440.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub19_function_unit[11:0] 12'000001000000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub19_function_unit[11:0] 12'000010000000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub19_function_unit[11:0] 12'010000000000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub19_function_unit[11:0] 12'010000000000 + case + assign $1\dec31_dec_sub19_function_unit[11:0] 12'000000000000 + end + sync always + update \dec31_dec_sub19_function_unit $0\dec31_dec_sub19_function_unit[11:0] + end + attribute \src "issuer_ls180.v:89458.3-89476.6" + process $proc$issuer_ls180.v:89458$3747 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub19_ldst_len[3:0] $1\dec31_dec_sub19_ldst_len[3:0] + attribute \src "issuer_ls180.v:89459.5-89459.29" + switch \initial + attribute \src "issuer_ls180.v:89459.9-89459.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub19_ldst_len[3:0] 4'0000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub19_ldst_len[3:0] 4'0000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub19_ldst_len[3:0] 4'0000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub19_ldst_len[3:0] 4'0000 + case + assign $1\dec31_dec_sub19_ldst_len[3:0] 4'0000 + end + sync always + update \dec31_dec_sub19_ldst_len $0\dec31_dec_sub19_ldst_len[3:0] + end + attribute \src "issuer_ls180.v:89477.3-89495.6" + process $proc$issuer_ls180.v:89477$3748 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub19_upd[1:0] $1\dec31_dec_sub19_upd[1:0] + attribute \src "issuer_ls180.v:89478.5-89478.29" + switch \initial + attribute \src "issuer_ls180.v:89478.9-89478.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub19_upd[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub19_upd[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub19_upd[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub19_upd[1:0] 2'00 + case + assign $1\dec31_dec_sub19_upd[1:0] 2'00 + end + sync always + update \dec31_dec_sub19_upd $0\dec31_dec_sub19_upd[1:0] + end + attribute \src "issuer_ls180.v:89496.3-89514.6" + process $proc$issuer_ls180.v:89496$3749 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub19_rc_sel[1:0] $1\dec31_dec_sub19_rc_sel[1:0] + attribute \src "issuer_ls180.v:89497.5-89497.29" + switch \initial + attribute \src "issuer_ls180.v:89497.9-89497.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub19_rc_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub19_rc_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub19_rc_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub19_rc_sel[1:0] 2'00 + case + assign $1\dec31_dec_sub19_rc_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub19_rc_sel $0\dec31_dec_sub19_rc_sel[1:0] + end + attribute \src "issuer_ls180.v:89515.3-89533.6" + process $proc$issuer_ls180.v:89515$3750 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub19_cry_in[1:0] $1\dec31_dec_sub19_cry_in[1:0] + attribute \src "issuer_ls180.v:89516.5-89516.29" + switch \initial + attribute \src "issuer_ls180.v:89516.9-89516.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub19_cry_in[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub19_cry_in[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub19_cry_in[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub19_cry_in[1:0] 2'00 + case + assign $1\dec31_dec_sub19_cry_in[1:0] 2'00 + end + sync always + update \dec31_dec_sub19_cry_in $0\dec31_dec_sub19_cry_in[1:0] + end + attribute \src "issuer_ls180.v:89534.3-89552.6" + process $proc$issuer_ls180.v:89534$3751 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub19_asmcode[7:0] $1\dec31_dec_sub19_asmcode[7:0] + attribute \src "issuer_ls180.v:89535.5-89535.29" + switch \initial + attribute \src "issuer_ls180.v:89535.9-89535.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub19_asmcode[7:0] 8'01101111 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub19_asmcode[7:0] 8'01110000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub19_asmcode[7:0] 8'01110001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub19_asmcode[7:0] 8'01111001 + case + assign $1\dec31_dec_sub19_asmcode[7:0] 8'00000000 + end + sync always + update \dec31_dec_sub19_asmcode $0\dec31_dec_sub19_asmcode[7:0] + end + attribute \src "issuer_ls180.v:89553.3-89571.6" + process $proc$issuer_ls180.v:89553$3752 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub19_inv_a[0:0] $1\dec31_dec_sub19_inv_a[0:0] + attribute \src "issuer_ls180.v:89554.5-89554.29" + switch \initial + attribute \src "issuer_ls180.v:89554.9-89554.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub19_inv_a[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub19_inv_a[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub19_inv_a[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub19_inv_a[0:0] 1'0 + case + assign $1\dec31_dec_sub19_inv_a[0:0] 1'0 + end + sync always + update \dec31_dec_sub19_inv_a $0\dec31_dec_sub19_inv_a[0:0] + end + attribute \src "issuer_ls180.v:89572.3-89590.6" + process $proc$issuer_ls180.v:89572$3753 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub19_inv_out[0:0] $1\dec31_dec_sub19_inv_out[0:0] + attribute \src "issuer_ls180.v:89573.5-89573.29" + switch \initial + attribute \src "issuer_ls180.v:89573.9-89573.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub19_inv_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub19_inv_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub19_inv_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub19_inv_out[0:0] 1'0 + case + assign $1\dec31_dec_sub19_inv_out[0:0] 1'0 + end + sync always + update \dec31_dec_sub19_inv_out $0\dec31_dec_sub19_inv_out[0:0] + end + attribute \src "issuer_ls180.v:89591.3-89609.6" + process $proc$issuer_ls180.v:89591$3754 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub19_cry_out[0:0] $1\dec31_dec_sub19_cry_out[0:0] + attribute \src "issuer_ls180.v:89592.5-89592.29" + switch \initial + attribute \src "issuer_ls180.v:89592.9-89592.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub19_cry_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub19_cry_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub19_cry_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub19_cry_out[0:0] 1'0 + case + assign $1\dec31_dec_sub19_cry_out[0:0] 1'0 + end + sync always + update \dec31_dec_sub19_cry_out $0\dec31_dec_sub19_cry_out[0:0] + end + attribute \src "issuer_ls180.v:89610.3-89628.6" + process $proc$issuer_ls180.v:89610$3755 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub19_br[0:0] $1\dec31_dec_sub19_br[0:0] + attribute \src "issuer_ls180.v:89611.5-89611.29" + switch \initial + attribute \src "issuer_ls180.v:89611.9-89611.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub19_br[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub19_br[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub19_br[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub19_br[0:0] 1'0 + case + assign $1\dec31_dec_sub19_br[0:0] 1'0 + end + sync always + update \dec31_dec_sub19_br $0\dec31_dec_sub19_br[0:0] + end + attribute \src "issuer_ls180.v:89629.3-89647.6" + process $proc$issuer_ls180.v:89629$3756 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub19_sgn_ext[0:0] $1\dec31_dec_sub19_sgn_ext[0:0] + attribute \src "issuer_ls180.v:89630.5-89630.29" + switch \initial + attribute \src "issuer_ls180.v:89630.9-89630.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub19_sgn_ext[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub19_sgn_ext[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub19_sgn_ext[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub19_sgn_ext[0:0] 1'0 + case + assign $1\dec31_dec_sub19_sgn_ext[0:0] 1'0 + end + sync always + update \dec31_dec_sub19_sgn_ext $0\dec31_dec_sub19_sgn_ext[0:0] + end + attribute \src "issuer_ls180.v:89648.3-89666.6" + process $proc$issuer_ls180.v:89648$3757 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub19_internal_op[6:0] $1\dec31_dec_sub19_internal_op[6:0] + attribute \src "issuer_ls180.v:89649.5-89649.29" + switch \initial + attribute \src "issuer_ls180.v:89649.9-89649.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub19_internal_op[6:0] 7'0101101 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub19_internal_op[6:0] 7'1000111 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub19_internal_op[6:0] 7'0101110 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub19_internal_op[6:0] 7'0110001 + case + assign $1\dec31_dec_sub19_internal_op[6:0] 7'0000000 + end + sync always + update \dec31_dec_sub19_internal_op $0\dec31_dec_sub19_internal_op[6:0] + end + attribute \src "issuer_ls180.v:89667.3-89685.6" + process $proc$issuer_ls180.v:89667$3758 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub19_rsrv[0:0] $1\dec31_dec_sub19_rsrv[0:0] + attribute \src "issuer_ls180.v:89668.5-89668.29" + switch \initial + attribute \src "issuer_ls180.v:89668.9-89668.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub19_rsrv[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub19_rsrv[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub19_rsrv[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub19_rsrv[0:0] 1'0 + case + assign $1\dec31_dec_sub19_rsrv[0:0] 1'0 + end + sync always + update \dec31_dec_sub19_rsrv $0\dec31_dec_sub19_rsrv[0:0] + end + attribute \src "issuer_ls180.v:89686.3-89704.6" + process $proc$issuer_ls180.v:89686$3759 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub19_is_32b[0:0] $1\dec31_dec_sub19_is_32b[0:0] + attribute \src "issuer_ls180.v:89687.5-89687.29" + switch \initial + attribute \src "issuer_ls180.v:89687.9-89687.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub19_is_32b[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub19_is_32b[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub19_is_32b[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub19_is_32b[0:0] 1'0 + case + assign $1\dec31_dec_sub19_is_32b[0:0] 1'0 + end + sync always + update \dec31_dec_sub19_is_32b $0\dec31_dec_sub19_is_32b[0:0] + end + attribute \src "issuer_ls180.v:89705.3-89723.6" + process $proc$issuer_ls180.v:89705$3760 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub19_sgn[0:0] $1\dec31_dec_sub19_sgn[0:0] + attribute \src "issuer_ls180.v:89706.5-89706.29" + switch \initial + attribute \src "issuer_ls180.v:89706.9-89706.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub19_sgn[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub19_sgn[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub19_sgn[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub19_sgn[0:0] 1'0 + case + assign $1\dec31_dec_sub19_sgn[0:0] 1'0 + end + sync always + update \dec31_dec_sub19_sgn $0\dec31_dec_sub19_sgn[0:0] + end + attribute \src "issuer_ls180.v:89724.3-89742.6" + process $proc$issuer_ls180.v:89724$3761 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub19_lk[0:0] $1\dec31_dec_sub19_lk[0:0] + attribute \src "issuer_ls180.v:89725.5-89725.29" + switch \initial + attribute \src "issuer_ls180.v:89725.9-89725.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub19_lk[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub19_lk[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub19_lk[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub19_lk[0:0] 1'0 + case + assign $1\dec31_dec_sub19_lk[0:0] 1'0 + end + sync always + update \dec31_dec_sub19_lk $0\dec31_dec_sub19_lk[0:0] + end + attribute \src "issuer_ls180.v:89743.3-89761.6" + process $proc$issuer_ls180.v:89743$3762 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub19_sgl_pipe[0:0] $1\dec31_dec_sub19_sgl_pipe[0:0] + attribute \src "issuer_ls180.v:89744.5-89744.29" + switch \initial + attribute \src "issuer_ls180.v:89744.9-89744.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub19_sgl_pipe[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub19_sgl_pipe[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub19_sgl_pipe[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub19_sgl_pipe[0:0] 1'0 + case + assign $1\dec31_dec_sub19_sgl_pipe[0:0] 1'0 + end + sync always + update \dec31_dec_sub19_sgl_pipe $0\dec31_dec_sub19_sgl_pipe[0:0] + end + attribute \src "issuer_ls180.v:89762.3-89780.6" + process $proc$issuer_ls180.v:89762$3763 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub19_form[4:0] $1\dec31_dec_sub19_form[4:0] + attribute \src "issuer_ls180.v:89763.5-89763.29" + switch \initial + attribute \src "issuer_ls180.v:89763.9-89763.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub19_form[4:0] 5'01010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub19_form[4:0] 5'01000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub19_form[4:0] 5'01010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub19_form[4:0] 5'01010 + case + assign $1\dec31_dec_sub19_form[4:0] 5'00000 + end + sync always + update \dec31_dec_sub19_form $0\dec31_dec_sub19_form[4:0] + end + attribute \src "issuer_ls180.v:89781.3-89799.6" + process $proc$issuer_ls180.v:89781$3764 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub19_in1_sel[2:0] $1\dec31_dec_sub19_in1_sel[2:0] + attribute \src "issuer_ls180.v:89782.5-89782.29" + switch \initial + attribute \src "issuer_ls180.v:89782.9-89782.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub19_in1_sel[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub19_in1_sel[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub19_in1_sel[2:0] 3'011 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub19_in1_sel[2:0] 3'100 + case + assign $1\dec31_dec_sub19_in1_sel[2:0] 3'000 + end + sync always + update \dec31_dec_sub19_in1_sel $0\dec31_dec_sub19_in1_sel[2:0] + end + attribute \src "issuer_ls180.v:89800.3-89818.6" + process $proc$issuer_ls180.v:89800$3765 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub19_in2_sel[3:0] $1\dec31_dec_sub19_in2_sel[3:0] + attribute \src "issuer_ls180.v:89801.5-89801.29" + switch \initial + attribute \src "issuer_ls180.v:89801.9-89801.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub19_in2_sel[3:0] 4'0000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub19_in2_sel[3:0] 4'0000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub19_in2_sel[3:0] 4'0000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub19_in2_sel[3:0] 4'0000 + case + assign $1\dec31_dec_sub19_in2_sel[3:0] 4'0000 + end + sync always + update \dec31_dec_sub19_in2_sel $0\dec31_dec_sub19_in2_sel[3:0] + end + attribute \src "issuer_ls180.v:89819.3-89837.6" + process $proc$issuer_ls180.v:89819$3766 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub19_in3_sel[1:0] $1\dec31_dec_sub19_in3_sel[1:0] + attribute \src "issuer_ls180.v:89820.5-89820.29" + switch \initial + attribute \src "issuer_ls180.v:89820.9-89820.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub19_in3_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub19_in3_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub19_in3_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub19_in3_sel[1:0] 2'00 + case + assign $1\dec31_dec_sub19_in3_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub19_in3_sel $0\dec31_dec_sub19_in3_sel[1:0] + end + attribute \src "issuer_ls180.v:89838.3-89856.6" + process $proc$issuer_ls180.v:89838$3767 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub19_out_sel[1:0] $1\dec31_dec_sub19_out_sel[1:0] + attribute \src "issuer_ls180.v:89839.5-89839.29" + switch \initial + attribute \src "issuer_ls180.v:89839.9-89839.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub19_out_sel[1:0] 2'01 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub19_out_sel[1:0] 2'01 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub19_out_sel[1:0] 2'01 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub19_out_sel[1:0] 2'11 + case + assign $1\dec31_dec_sub19_out_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub19_out_sel $0\dec31_dec_sub19_out_sel[1:0] + end + attribute \src "issuer_ls180.v:89857.3-89875.6" + process $proc$issuer_ls180.v:89857$3768 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub19_cr_in[2:0] $1\dec31_dec_sub19_cr_in[2:0] + attribute \src "issuer_ls180.v:89858.5-89858.29" + switch \initial + attribute \src "issuer_ls180.v:89858.9-89858.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub19_cr_in[2:0] 3'110 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub19_cr_in[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub19_cr_in[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub19_cr_in[2:0] 3'000 + case + assign $1\dec31_dec_sub19_cr_in[2:0] 3'000 + end + sync always + update \dec31_dec_sub19_cr_in $0\dec31_dec_sub19_cr_in[2:0] + end + attribute \src "issuer_ls180.v:89876.3-89894.6" + process $proc$issuer_ls180.v:89876$3769 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub19_cr_out[2:0] $1\dec31_dec_sub19_cr_out[2:0] + attribute \src "issuer_ls180.v:89877.5-89877.29" + switch \initial + attribute \src "issuer_ls180.v:89877.9-89877.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub19_cr_out[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub19_cr_out[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub19_cr_out[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub19_cr_out[2:0] 3'000 + case + assign $1\dec31_dec_sub19_cr_out[2:0] 3'000 + end + sync always + update \dec31_dec_sub19_cr_out $0\dec31_dec_sub19_cr_out[2:0] + end + connect \opcode_switch \opcode_in [10:6] +end +attribute \src "issuer_ls180.v:89900.1-90759.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.dec2.dec.dec31.dec31_dec_sub20" +attribute \generator "nMigen" +module \dec31_dec_sub20 + attribute \src "issuer_ls180.v:90283.3-90307.6" + wire width 8 $0\dec31_dec_sub20_asmcode[7:0] + attribute \src "issuer_ls180.v:90383.3-90407.6" + wire $0\dec31_dec_sub20_br[0:0] + attribute \src "issuer_ls180.v:90708.3-90732.6" + wire width 3 $0\dec31_dec_sub20_cr_in[2:0] + attribute \src "issuer_ls180.v:90733.3-90757.6" + wire width 3 $0\dec31_dec_sub20_cr_out[2:0] + attribute \src "issuer_ls180.v:90258.3-90282.6" + wire width 2 $0\dec31_dec_sub20_cry_in[1:0] + attribute \src "issuer_ls180.v:90358.3-90382.6" + wire $0\dec31_dec_sub20_cry_out[0:0] + attribute \src "issuer_ls180.v:90583.3-90607.6" + wire width 5 $0\dec31_dec_sub20_form[4:0] + attribute \src "issuer_ls180.v:90158.3-90182.6" + wire width 12 $0\dec31_dec_sub20_function_unit[11:0] + attribute \src "issuer_ls180.v:90608.3-90632.6" + wire width 3 $0\dec31_dec_sub20_in1_sel[2:0] + attribute \src "issuer_ls180.v:90633.3-90657.6" + wire width 4 $0\dec31_dec_sub20_in2_sel[3:0] + attribute \src "issuer_ls180.v:90658.3-90682.6" + wire width 2 $0\dec31_dec_sub20_in3_sel[1:0] + attribute \src "issuer_ls180.v:90433.3-90457.6" + wire width 7 $0\dec31_dec_sub20_internal_op[6:0] + attribute \src "issuer_ls180.v:90308.3-90332.6" + wire $0\dec31_dec_sub20_inv_a[0:0] + attribute \src "issuer_ls180.v:90333.3-90357.6" + wire $0\dec31_dec_sub20_inv_out[0:0] + attribute \src "issuer_ls180.v:90483.3-90507.6" + wire $0\dec31_dec_sub20_is_32b[0:0] + attribute \src "issuer_ls180.v:90183.3-90207.6" + wire width 4 $0\dec31_dec_sub20_ldst_len[3:0] + attribute \src "issuer_ls180.v:90533.3-90557.6" + wire $0\dec31_dec_sub20_lk[0:0] + attribute \src "issuer_ls180.v:90683.3-90707.6" + wire width 2 $0\dec31_dec_sub20_out_sel[1:0] + attribute \src "issuer_ls180.v:90233.3-90257.6" + wire width 2 $0\dec31_dec_sub20_rc_sel[1:0] + attribute \src "issuer_ls180.v:90458.3-90482.6" + wire $0\dec31_dec_sub20_rsrv[0:0] + attribute \src "issuer_ls180.v:90558.3-90582.6" + wire $0\dec31_dec_sub20_sgl_pipe[0:0] + attribute \src "issuer_ls180.v:90508.3-90532.6" + wire $0\dec31_dec_sub20_sgn[0:0] + attribute \src "issuer_ls180.v:90408.3-90432.6" + wire $0\dec31_dec_sub20_sgn_ext[0:0] + attribute \src "issuer_ls180.v:90208.3-90232.6" + wire width 2 $0\dec31_dec_sub20_upd[1:0] + attribute \src "issuer_ls180.v:89901.7-89901.20" + wire $0\initial[0:0] + attribute \src "issuer_ls180.v:90283.3-90307.6" + wire width 8 $1\dec31_dec_sub20_asmcode[7:0] + attribute \src "issuer_ls180.v:90383.3-90407.6" + wire $1\dec31_dec_sub20_br[0:0] + attribute \src "issuer_ls180.v:90708.3-90732.6" + wire width 3 $1\dec31_dec_sub20_cr_in[2:0] + attribute \src "issuer_ls180.v:90733.3-90757.6" + wire width 3 $1\dec31_dec_sub20_cr_out[2:0] + attribute \src "issuer_ls180.v:90258.3-90282.6" + wire width 2 $1\dec31_dec_sub20_cry_in[1:0] + attribute \src "issuer_ls180.v:90358.3-90382.6" + wire $1\dec31_dec_sub20_cry_out[0:0] + attribute \src "issuer_ls180.v:90583.3-90607.6" + wire width 5 $1\dec31_dec_sub20_form[4:0] + attribute \src "issuer_ls180.v:90158.3-90182.6" + wire width 12 $1\dec31_dec_sub20_function_unit[11:0] + attribute \src "issuer_ls180.v:90608.3-90632.6" + wire width 3 $1\dec31_dec_sub20_in1_sel[2:0] + attribute \src "issuer_ls180.v:90633.3-90657.6" + wire width 4 $1\dec31_dec_sub20_in2_sel[3:0] + attribute \src "issuer_ls180.v:90658.3-90682.6" + wire width 2 $1\dec31_dec_sub20_in3_sel[1:0] + attribute \src "issuer_ls180.v:90433.3-90457.6" + wire width 7 $1\dec31_dec_sub20_internal_op[6:0] + attribute \src "issuer_ls180.v:90308.3-90332.6" + wire $1\dec31_dec_sub20_inv_a[0:0] + attribute \src "issuer_ls180.v:90333.3-90357.6" + wire $1\dec31_dec_sub20_inv_out[0:0] + attribute \src "issuer_ls180.v:90483.3-90507.6" + wire $1\dec31_dec_sub20_is_32b[0:0] + attribute \src "issuer_ls180.v:90183.3-90207.6" + wire width 4 $1\dec31_dec_sub20_ldst_len[3:0] + attribute \src "issuer_ls180.v:90533.3-90557.6" + wire $1\dec31_dec_sub20_lk[0:0] + attribute \src "issuer_ls180.v:90683.3-90707.6" + wire width 2 $1\dec31_dec_sub20_out_sel[1:0] + attribute \src "issuer_ls180.v:90233.3-90257.6" + wire width 2 $1\dec31_dec_sub20_rc_sel[1:0] + attribute \src "issuer_ls180.v:90458.3-90482.6" + wire $1\dec31_dec_sub20_rsrv[0:0] + attribute \src "issuer_ls180.v:90558.3-90582.6" + wire $1\dec31_dec_sub20_sgl_pipe[0:0] + attribute \src "issuer_ls180.v:90508.3-90532.6" + wire $1\dec31_dec_sub20_sgn[0:0] + attribute \src "issuer_ls180.v:90408.3-90432.6" + wire $1\dec31_dec_sub20_sgn_ext[0:0] + attribute \src "issuer_ls180.v:90208.3-90232.6" + wire width 2 $1\dec31_dec_sub20_upd[1:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 8 output 4 \dec31_dec_sub20_asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 18 \dec31_dec_sub20_br + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 9 \dec31_dec_sub20_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 10 \dec31_dec_sub20_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 14 \dec31_dec_sub20_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 17 \dec31_dec_sub20_cry_out + attribute \enum_base_type "Form" + attribute \enum_value_00000 "NONE" + attribute \enum_value_00001 "I" + attribute \enum_value_00010 "B" + attribute \enum_value_00011 "SC" + attribute \enum_value_00100 "D" + attribute \enum_value_00101 "DS" + attribute \enum_value_00110 "DQ" + attribute \enum_value_00111 "DX" + attribute \enum_value_01000 "X" + attribute \enum_value_01001 "XL" + attribute \enum_value_01010 "XFX" + attribute \enum_value_01011 "XFL" + attribute \enum_value_01100 "XX1" + attribute \enum_value_01101 "XX2" + attribute \enum_value_01110 "XX3" + attribute \enum_value_01111 "XX4" + attribute \enum_value_10000 "XS" + attribute \enum_value_10001 "XO" + attribute \enum_value_10010 "A" + attribute \enum_value_10011 "M" + attribute \enum_value_10100 "MD" + attribute \enum_value_10101 "MDS" + attribute \enum_value_10110 "VA" + attribute \enum_value_10111 "VC" + attribute \enum_value_11000 "VX" + attribute \enum_value_11001 "EVX" + attribute \enum_value_11010 "EVS" + attribute \enum_value_11011 "Z22" + attribute \enum_value_11100 "Z23" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 5 output 3 \dec31_dec_sub20_form + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 12 output 1 \dec31_dec_sub20_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 5 \dec31_dec_sub20_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 output 6 \dec31_dec_sub20_in2_sel + attribute \enum_base_type "In3Sel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RS" + attribute \enum_value_10 "RB" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 7 \dec31_dec_sub20_in3_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 7 output 2 \dec31_dec_sub20_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 15 \dec31_dec_sub20_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 16 \dec31_dec_sub20_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 21 \dec31_dec_sub20_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 output 11 \dec31_dec_sub20_ldst_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 23 \dec31_dec_sub20_lk + attribute \enum_base_type "OutSel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RT" + attribute \enum_value_10 "RA" + attribute \enum_value_11 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 8 \dec31_dec_sub20_out_sel + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 13 \dec31_dec_sub20_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 20 \dec31_dec_sub20_rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 24 \dec31_dec_sub20_sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 22 \dec31_dec_sub20_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 19 \dec31_dec_sub20_sgn_ext + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 12 \dec31_dec_sub20_upd + attribute \src "issuer_ls180.v:89901.7-89901.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + wire width 32 input 25 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:320" + wire width 5 \opcode_switch + attribute \src "issuer_ls180.v:89901.7-89901.20" + process $proc$issuer_ls180.v:89901$3795 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "issuer_ls180.v:90158.3-90182.6" + process $proc$issuer_ls180.v:90158$3771 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub20_function_unit[11:0] $1\dec31_dec_sub20_function_unit[11:0] + attribute \src "issuer_ls180.v:90159.5-90159.29" + switch \initial + attribute \src "issuer_ls180.v:90159.9-90159.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub20_function_unit[11:0] 12'000000000100 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub20_function_unit[11:0] 12'000000000100 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub20_function_unit[11:0] 12'000000000100 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub20_function_unit[11:0] 12'000000000100 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub20_function_unit[11:0] 12'000000000100 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub20_function_unit[11:0] 12'000000000100 + case + assign $1\dec31_dec_sub20_function_unit[11:0] 12'000000000000 + end + sync always + update \dec31_dec_sub20_function_unit $0\dec31_dec_sub20_function_unit[11:0] + end + attribute \src "issuer_ls180.v:90183.3-90207.6" + process $proc$issuer_ls180.v:90183$3772 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub20_ldst_len[3:0] $1\dec31_dec_sub20_ldst_len[3:0] + attribute \src "issuer_ls180.v:90184.5-90184.29" + switch \initial + attribute \src "issuer_ls180.v:90184.9-90184.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub20_ldst_len[3:0] 4'0001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub20_ldst_len[3:0] 4'1000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub20_ldst_len[3:0] 4'1000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub20_ldst_len[3:0] 4'0010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub20_ldst_len[3:0] 4'0100 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub20_ldst_len[3:0] 4'1000 + case + assign $1\dec31_dec_sub20_ldst_len[3:0] 4'0000 + end + sync always + update \dec31_dec_sub20_ldst_len $0\dec31_dec_sub20_ldst_len[3:0] + end + attribute \src "issuer_ls180.v:90208.3-90232.6" + process $proc$issuer_ls180.v:90208$3773 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub20_upd[1:0] $1\dec31_dec_sub20_upd[1:0] + attribute \src "issuer_ls180.v:90209.5-90209.29" + switch \initial + attribute \src "issuer_ls180.v:90209.9-90209.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub20_upd[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub20_upd[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub20_upd[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub20_upd[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub20_upd[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub20_upd[1:0] 2'00 + case + assign $1\dec31_dec_sub20_upd[1:0] 2'00 + end + sync always + update \dec31_dec_sub20_upd $0\dec31_dec_sub20_upd[1:0] + end + attribute \src "issuer_ls180.v:90233.3-90257.6" + process $proc$issuer_ls180.v:90233$3774 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub20_rc_sel[1:0] $1\dec31_dec_sub20_rc_sel[1:0] + attribute \src "issuer_ls180.v:90234.5-90234.29" + switch \initial + attribute \src "issuer_ls180.v:90234.9-90234.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub20_rc_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub20_rc_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub20_rc_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub20_rc_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub20_rc_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub20_rc_sel[1:0] 2'00 + case + assign $1\dec31_dec_sub20_rc_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub20_rc_sel $0\dec31_dec_sub20_rc_sel[1:0] + end + attribute \src "issuer_ls180.v:90258.3-90282.6" + process $proc$issuer_ls180.v:90258$3775 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub20_cry_in[1:0] $1\dec31_dec_sub20_cry_in[1:0] + attribute \src "issuer_ls180.v:90259.5-90259.29" + switch \initial + attribute \src "issuer_ls180.v:90259.9-90259.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub20_cry_in[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub20_cry_in[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub20_cry_in[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub20_cry_in[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub20_cry_in[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub20_cry_in[1:0] 2'00 + case + assign $1\dec31_dec_sub20_cry_in[1:0] 2'00 + end + sync always + update \dec31_dec_sub20_cry_in $0\dec31_dec_sub20_cry_in[1:0] + end + attribute \src "issuer_ls180.v:90283.3-90307.6" + process $proc$issuer_ls180.v:90283$3776 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub20_asmcode[7:0] $1\dec31_dec_sub20_asmcode[7:0] + attribute \src "issuer_ls180.v:90284.5-90284.29" + switch \initial + attribute \src "issuer_ls180.v:90284.9-90284.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub20_asmcode[7:0] 8'01001101 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub20_asmcode[7:0] 8'01010011 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub20_asmcode[7:0] 8'01010100 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub20_asmcode[7:0] 8'01011001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub20_asmcode[7:0] 8'01100011 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub20_asmcode[7:0] 8'10101101 + case + assign $1\dec31_dec_sub20_asmcode[7:0] 8'00000000 + end + sync always + update \dec31_dec_sub20_asmcode $0\dec31_dec_sub20_asmcode[7:0] + end + attribute \src "issuer_ls180.v:90308.3-90332.6" + process $proc$issuer_ls180.v:90308$3777 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub20_inv_a[0:0] $1\dec31_dec_sub20_inv_a[0:0] + attribute \src "issuer_ls180.v:90309.5-90309.29" + switch \initial + attribute \src "issuer_ls180.v:90309.9-90309.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub20_inv_a[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub20_inv_a[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub20_inv_a[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub20_inv_a[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub20_inv_a[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub20_inv_a[0:0] 1'0 + case + assign $1\dec31_dec_sub20_inv_a[0:0] 1'0 + end + sync always + update \dec31_dec_sub20_inv_a $0\dec31_dec_sub20_inv_a[0:0] + end + attribute \src "issuer_ls180.v:90333.3-90357.6" + process $proc$issuer_ls180.v:90333$3778 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub20_inv_out[0:0] $1\dec31_dec_sub20_inv_out[0:0] + attribute \src "issuer_ls180.v:90334.5-90334.29" + switch \initial + attribute \src "issuer_ls180.v:90334.9-90334.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub20_inv_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub20_inv_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub20_inv_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub20_inv_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub20_inv_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub20_inv_out[0:0] 1'0 + case + assign $1\dec31_dec_sub20_inv_out[0:0] 1'0 + end + sync always + update \dec31_dec_sub20_inv_out $0\dec31_dec_sub20_inv_out[0:0] + end + attribute \src "issuer_ls180.v:90358.3-90382.6" + process $proc$issuer_ls180.v:90358$3779 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub20_cry_out[0:0] $1\dec31_dec_sub20_cry_out[0:0] + attribute \src "issuer_ls180.v:90359.5-90359.29" + switch \initial + attribute \src "issuer_ls180.v:90359.9-90359.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub20_cry_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub20_cry_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub20_cry_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub20_cry_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub20_cry_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub20_cry_out[0:0] 1'0 + case + assign $1\dec31_dec_sub20_cry_out[0:0] 1'0 + end + sync always + update \dec31_dec_sub20_cry_out $0\dec31_dec_sub20_cry_out[0:0] + end + attribute \src "issuer_ls180.v:90383.3-90407.6" + process $proc$issuer_ls180.v:90383$3780 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub20_br[0:0] $1\dec31_dec_sub20_br[0:0] + attribute \src "issuer_ls180.v:90384.5-90384.29" + switch \initial + attribute \src "issuer_ls180.v:90384.9-90384.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub20_br[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub20_br[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub20_br[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub20_br[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub20_br[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub20_br[0:0] 1'1 + case + assign $1\dec31_dec_sub20_br[0:0] 1'0 + end + sync always + update \dec31_dec_sub20_br $0\dec31_dec_sub20_br[0:0] + end + attribute \src "issuer_ls180.v:90408.3-90432.6" + process $proc$issuer_ls180.v:90408$3781 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub20_sgn_ext[0:0] $1\dec31_dec_sub20_sgn_ext[0:0] + attribute \src "issuer_ls180.v:90409.5-90409.29" + switch \initial + attribute \src "issuer_ls180.v:90409.9-90409.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub20_sgn_ext[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub20_sgn_ext[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub20_sgn_ext[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub20_sgn_ext[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub20_sgn_ext[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub20_sgn_ext[0:0] 1'0 + case + assign $1\dec31_dec_sub20_sgn_ext[0:0] 1'0 + end + sync always + update \dec31_dec_sub20_sgn_ext $0\dec31_dec_sub20_sgn_ext[0:0] + end + attribute \src "issuer_ls180.v:90433.3-90457.6" + process $proc$issuer_ls180.v:90433$3782 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub20_internal_op[6:0] $1\dec31_dec_sub20_internal_op[6:0] + attribute \src "issuer_ls180.v:90434.5-90434.29" + switch \initial + attribute \src "issuer_ls180.v:90434.9-90434.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub20_internal_op[6:0] 7'0100101 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub20_internal_op[6:0] 7'0100101 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub20_internal_op[6:0] 7'0100101 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub20_internal_op[6:0] 7'0100101 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub20_internal_op[6:0] 7'0100101 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub20_internal_op[6:0] 7'0100110 + case + assign $1\dec31_dec_sub20_internal_op[6:0] 7'0000000 + end + sync always + update \dec31_dec_sub20_internal_op $0\dec31_dec_sub20_internal_op[6:0] + end + attribute \src "issuer_ls180.v:90458.3-90482.6" + process $proc$issuer_ls180.v:90458$3783 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub20_rsrv[0:0] $1\dec31_dec_sub20_rsrv[0:0] + attribute \src "issuer_ls180.v:90459.5-90459.29" + switch \initial + attribute \src "issuer_ls180.v:90459.9-90459.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub20_rsrv[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub20_rsrv[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub20_rsrv[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub20_rsrv[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub20_rsrv[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub20_rsrv[0:0] 1'0 + case + assign $1\dec31_dec_sub20_rsrv[0:0] 1'0 + end + sync always + update \dec31_dec_sub20_rsrv $0\dec31_dec_sub20_rsrv[0:0] + end + attribute \src "issuer_ls180.v:90483.3-90507.6" + process $proc$issuer_ls180.v:90483$3784 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub20_is_32b[0:0] $1\dec31_dec_sub20_is_32b[0:0] + attribute \src "issuer_ls180.v:90484.5-90484.29" + switch \initial + attribute \src "issuer_ls180.v:90484.9-90484.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub20_is_32b[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub20_is_32b[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub20_is_32b[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub20_is_32b[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub20_is_32b[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub20_is_32b[0:0] 1'0 + case + assign $1\dec31_dec_sub20_is_32b[0:0] 1'0 + end + sync always + update \dec31_dec_sub20_is_32b $0\dec31_dec_sub20_is_32b[0:0] + end + attribute \src "issuer_ls180.v:90508.3-90532.6" + process $proc$issuer_ls180.v:90508$3785 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub20_sgn[0:0] $1\dec31_dec_sub20_sgn[0:0] + attribute \src "issuer_ls180.v:90509.5-90509.29" + switch \initial + attribute \src "issuer_ls180.v:90509.9-90509.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub20_sgn[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub20_sgn[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub20_sgn[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub20_sgn[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub20_sgn[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub20_sgn[0:0] 1'0 + case + assign $1\dec31_dec_sub20_sgn[0:0] 1'0 + end + sync always + update \dec31_dec_sub20_sgn $0\dec31_dec_sub20_sgn[0:0] + end + attribute \src "issuer_ls180.v:90533.3-90557.6" + process $proc$issuer_ls180.v:90533$3786 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub20_lk[0:0] $1\dec31_dec_sub20_lk[0:0] + attribute \src "issuer_ls180.v:90534.5-90534.29" + switch \initial + attribute \src "issuer_ls180.v:90534.9-90534.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub20_lk[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub20_lk[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub20_lk[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub20_lk[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub20_lk[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub20_lk[0:0] 1'0 + case + assign $1\dec31_dec_sub20_lk[0:0] 1'0 + end + sync always + update \dec31_dec_sub20_lk $0\dec31_dec_sub20_lk[0:0] + end + attribute \src "issuer_ls180.v:90558.3-90582.6" + process $proc$issuer_ls180.v:90558$3787 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub20_sgl_pipe[0:0] $1\dec31_dec_sub20_sgl_pipe[0:0] + attribute \src "issuer_ls180.v:90559.5-90559.29" + switch \initial + attribute \src "issuer_ls180.v:90559.9-90559.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub20_sgl_pipe[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub20_sgl_pipe[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub20_sgl_pipe[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub20_sgl_pipe[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub20_sgl_pipe[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub20_sgl_pipe[0:0] 1'1 + case + assign $1\dec31_dec_sub20_sgl_pipe[0:0] 1'0 + end + sync always + update \dec31_dec_sub20_sgl_pipe $0\dec31_dec_sub20_sgl_pipe[0:0] + end + attribute \src "issuer_ls180.v:90583.3-90607.6" + process $proc$issuer_ls180.v:90583$3788 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub20_form[4:0] $1\dec31_dec_sub20_form[4:0] + attribute \src "issuer_ls180.v:90584.5-90584.29" + switch \initial + attribute \src "issuer_ls180.v:90584.9-90584.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub20_form[4:0] 5'01000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub20_form[4:0] 5'01000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub20_form[4:0] 5'01000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub20_form[4:0] 5'01000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub20_form[4:0] 5'01000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub20_form[4:0] 5'01000 + case + assign $1\dec31_dec_sub20_form[4:0] 5'00000 + end + sync always + update \dec31_dec_sub20_form $0\dec31_dec_sub20_form[4:0] + end + attribute \src "issuer_ls180.v:90608.3-90632.6" + process $proc$issuer_ls180.v:90608$3789 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub20_in1_sel[2:0] $1\dec31_dec_sub20_in1_sel[2:0] + attribute \src "issuer_ls180.v:90609.5-90609.29" + switch \initial + attribute \src "issuer_ls180.v:90609.9-90609.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub20_in1_sel[2:0] 3'010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub20_in1_sel[2:0] 3'010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub20_in1_sel[2:0] 3'010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub20_in1_sel[2:0] 3'010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub20_in1_sel[2:0] 3'010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub20_in1_sel[2:0] 3'010 + case + assign $1\dec31_dec_sub20_in1_sel[2:0] 3'000 + end + sync always + update \dec31_dec_sub20_in1_sel $0\dec31_dec_sub20_in1_sel[2:0] + end + attribute \src "issuer_ls180.v:90633.3-90657.6" + process $proc$issuer_ls180.v:90633$3790 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub20_in2_sel[3:0] $1\dec31_dec_sub20_in2_sel[3:0] + attribute \src "issuer_ls180.v:90634.5-90634.29" + switch \initial + attribute \src "issuer_ls180.v:90634.9-90634.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub20_in2_sel[3:0] 4'0001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub20_in2_sel[3:0] 4'0001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub20_in2_sel[3:0] 4'0001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub20_in2_sel[3:0] 4'0001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub20_in2_sel[3:0] 4'0001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub20_in2_sel[3:0] 4'0001 + case + assign $1\dec31_dec_sub20_in2_sel[3:0] 4'0000 + end + sync always + update \dec31_dec_sub20_in2_sel $0\dec31_dec_sub20_in2_sel[3:0] + end + attribute \src "issuer_ls180.v:90658.3-90682.6" + process $proc$issuer_ls180.v:90658$3791 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub20_in3_sel[1:0] $1\dec31_dec_sub20_in3_sel[1:0] + attribute \src "issuer_ls180.v:90659.5-90659.29" + switch \initial + attribute \src "issuer_ls180.v:90659.9-90659.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub20_in3_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub20_in3_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub20_in3_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub20_in3_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub20_in3_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub20_in3_sel[1:0] 2'01 + case + assign $1\dec31_dec_sub20_in3_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub20_in3_sel $0\dec31_dec_sub20_in3_sel[1:0] + end + attribute \src "issuer_ls180.v:90683.3-90707.6" + process $proc$issuer_ls180.v:90683$3792 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub20_out_sel[1:0] $1\dec31_dec_sub20_out_sel[1:0] + attribute \src "issuer_ls180.v:90684.5-90684.29" + switch \initial + attribute \src "issuer_ls180.v:90684.9-90684.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub20_out_sel[1:0] 2'01 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub20_out_sel[1:0] 2'01 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub20_out_sel[1:0] 2'01 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub20_out_sel[1:0] 2'01 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub20_out_sel[1:0] 2'01 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub20_out_sel[1:0] 2'00 + case + assign $1\dec31_dec_sub20_out_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub20_out_sel $0\dec31_dec_sub20_out_sel[1:0] + end + attribute \src "issuer_ls180.v:90708.3-90732.6" + process $proc$issuer_ls180.v:90708$3793 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub20_cr_in[2:0] $1\dec31_dec_sub20_cr_in[2:0] + attribute \src "issuer_ls180.v:90709.5-90709.29" + switch \initial + attribute \src "issuer_ls180.v:90709.9-90709.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub20_cr_in[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub20_cr_in[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub20_cr_in[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub20_cr_in[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub20_cr_in[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub20_cr_in[2:0] 3'000 + case + assign $1\dec31_dec_sub20_cr_in[2:0] 3'000 + end + sync always + update \dec31_dec_sub20_cr_in $0\dec31_dec_sub20_cr_in[2:0] + end + attribute \src "issuer_ls180.v:90733.3-90757.6" + process $proc$issuer_ls180.v:90733$3794 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub20_cr_out[2:0] $1\dec31_dec_sub20_cr_out[2:0] + attribute \src "issuer_ls180.v:90734.5-90734.29" + switch \initial + attribute \src "issuer_ls180.v:90734.9-90734.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub20_cr_out[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub20_cr_out[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub20_cr_out[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub20_cr_out[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub20_cr_out[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub20_cr_out[2:0] 3'000 + case + assign $1\dec31_dec_sub20_cr_out[2:0] 3'000 + end + sync always + update \dec31_dec_sub20_cr_out $0\dec31_dec_sub20_cr_out[2:0] + end + connect \opcode_switch \opcode_in [10:6] +end +attribute \src "issuer_ls180.v:90763.1-92180.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.dec2.dec.dec31.dec31_dec_sub21" +attribute \generator "nMigen" +module \dec31_dec_sub21 + attribute \src "issuer_ls180.v:91805.3-91835.6" + wire width 8 $0\dec31_dec_sub21_asmcode[7:0] + attribute \src "issuer_ls180.v:91413.3-91461.6" + wire $0\dec31_dec_sub21_br[0:0] + attribute \src "issuer_ls180.v:92081.3-92129.6" + wire width 3 $0\dec31_dec_sub21_cr_in[2:0] + attribute \src "issuer_ls180.v:92130.3-92178.6" + wire width 3 $0\dec31_dec_sub21_cr_out[2:0] + attribute \src "issuer_ls180.v:91217.3-91265.6" + wire width 2 $0\dec31_dec_sub21_cry_in[1:0] + attribute \src "issuer_ls180.v:91364.3-91412.6" + wire $0\dec31_dec_sub21_cry_out[0:0] + attribute \src "issuer_ls180.v:91836.3-91884.6" + wire width 5 $0\dec31_dec_sub21_form[4:0] + attribute \src "issuer_ls180.v:91021.3-91069.6" + wire width 12 $0\dec31_dec_sub21_function_unit[11:0] + attribute \src "issuer_ls180.v:91885.3-91933.6" + wire width 3 $0\dec31_dec_sub21_in1_sel[2:0] + attribute \src "issuer_ls180.v:91934.3-91982.6" + wire width 4 $0\dec31_dec_sub21_in2_sel[3:0] + attribute \src "issuer_ls180.v:91983.3-92031.6" + wire width 2 $0\dec31_dec_sub21_in3_sel[1:0] + attribute \src "issuer_ls180.v:91560.3-91608.6" + wire width 7 $0\dec31_dec_sub21_internal_op[6:0] + attribute \src "issuer_ls180.v:91266.3-91314.6" + wire $0\dec31_dec_sub21_inv_a[0:0] + attribute \src "issuer_ls180.v:91315.3-91363.6" + wire $0\dec31_dec_sub21_inv_out[0:0] + attribute \src "issuer_ls180.v:91609.3-91657.6" + wire $0\dec31_dec_sub21_is_32b[0:0] + attribute \src "issuer_ls180.v:91070.3-91118.6" + wire width 4 $0\dec31_dec_sub21_ldst_len[3:0] + attribute \src "issuer_ls180.v:91707.3-91755.6" + wire $0\dec31_dec_sub21_lk[0:0] + attribute \src "issuer_ls180.v:92032.3-92080.6" + wire width 2 $0\dec31_dec_sub21_out_sel[1:0] + attribute \src "issuer_ls180.v:91168.3-91216.6" + wire width 2 $0\dec31_dec_sub21_rc_sel[1:0] + attribute \src "issuer_ls180.v:91511.3-91559.6" + wire $0\dec31_dec_sub21_rsrv[0:0] + attribute \src "issuer_ls180.v:91756.3-91804.6" + wire $0\dec31_dec_sub21_sgl_pipe[0:0] + attribute \src "issuer_ls180.v:91658.3-91706.6" + wire $0\dec31_dec_sub21_sgn[0:0] + attribute \src "issuer_ls180.v:91462.3-91510.6" + wire $0\dec31_dec_sub21_sgn_ext[0:0] + attribute \src "issuer_ls180.v:91119.3-91167.6" + wire width 2 $0\dec31_dec_sub21_upd[1:0] + attribute \src "issuer_ls180.v:90764.7-90764.20" + wire $0\initial[0:0] + attribute \src "issuer_ls180.v:91805.3-91835.6" + wire width 8 $1\dec31_dec_sub21_asmcode[7:0] + attribute \src "issuer_ls180.v:91413.3-91461.6" + wire $1\dec31_dec_sub21_br[0:0] + attribute \src "issuer_ls180.v:92081.3-92129.6" + wire width 3 $1\dec31_dec_sub21_cr_in[2:0] + attribute \src "issuer_ls180.v:92130.3-92178.6" + wire width 3 $1\dec31_dec_sub21_cr_out[2:0] + attribute \src "issuer_ls180.v:91217.3-91265.6" + wire width 2 $1\dec31_dec_sub21_cry_in[1:0] + attribute \src "issuer_ls180.v:91364.3-91412.6" + wire $1\dec31_dec_sub21_cry_out[0:0] + attribute \src "issuer_ls180.v:91836.3-91884.6" + wire width 5 $1\dec31_dec_sub21_form[4:0] + attribute \src "issuer_ls180.v:91021.3-91069.6" + wire width 12 $1\dec31_dec_sub21_function_unit[11:0] + attribute \src "issuer_ls180.v:91885.3-91933.6" + wire width 3 $1\dec31_dec_sub21_in1_sel[2:0] + attribute \src "issuer_ls180.v:91934.3-91982.6" + wire width 4 $1\dec31_dec_sub21_in2_sel[3:0] + attribute \src "issuer_ls180.v:91983.3-92031.6" + wire width 2 $1\dec31_dec_sub21_in3_sel[1:0] + attribute \src "issuer_ls180.v:91560.3-91608.6" + wire width 7 $1\dec31_dec_sub21_internal_op[6:0] + attribute \src "issuer_ls180.v:91266.3-91314.6" + wire $1\dec31_dec_sub21_inv_a[0:0] + attribute \src "issuer_ls180.v:91315.3-91363.6" + wire $1\dec31_dec_sub21_inv_out[0:0] + attribute \src "issuer_ls180.v:91609.3-91657.6" + wire $1\dec31_dec_sub21_is_32b[0:0] + attribute \src "issuer_ls180.v:91070.3-91118.6" + wire width 4 $1\dec31_dec_sub21_ldst_len[3:0] + attribute \src "issuer_ls180.v:91707.3-91755.6" + wire $1\dec31_dec_sub21_lk[0:0] + attribute \src "issuer_ls180.v:92032.3-92080.6" + wire width 2 $1\dec31_dec_sub21_out_sel[1:0] + attribute \src "issuer_ls180.v:91168.3-91216.6" + wire width 2 $1\dec31_dec_sub21_rc_sel[1:0] + attribute \src "issuer_ls180.v:91511.3-91559.6" + wire $1\dec31_dec_sub21_rsrv[0:0] + attribute \src "issuer_ls180.v:91756.3-91804.6" + wire $1\dec31_dec_sub21_sgl_pipe[0:0] + attribute \src "issuer_ls180.v:91658.3-91706.6" + wire $1\dec31_dec_sub21_sgn[0:0] + attribute \src "issuer_ls180.v:91462.3-91510.6" + wire $1\dec31_dec_sub21_sgn_ext[0:0] + attribute \src "issuer_ls180.v:91119.3-91167.6" + wire width 2 $1\dec31_dec_sub21_upd[1:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 8 output 4 \dec31_dec_sub21_asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 18 \dec31_dec_sub21_br + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 9 \dec31_dec_sub21_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 10 \dec31_dec_sub21_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 14 \dec31_dec_sub21_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 17 \dec31_dec_sub21_cry_out + attribute \enum_base_type "Form" + attribute \enum_value_00000 "NONE" + attribute \enum_value_00001 "I" + attribute \enum_value_00010 "B" + attribute \enum_value_00011 "SC" + attribute \enum_value_00100 "D" + attribute \enum_value_00101 "DS" + attribute \enum_value_00110 "DQ" + attribute \enum_value_00111 "DX" + attribute \enum_value_01000 "X" + attribute \enum_value_01001 "XL" + attribute \enum_value_01010 "XFX" + attribute \enum_value_01011 "XFL" + attribute \enum_value_01100 "XX1" + attribute \enum_value_01101 "XX2" + attribute \enum_value_01110 "XX3" + attribute \enum_value_01111 "XX4" + attribute \enum_value_10000 "XS" + attribute \enum_value_10001 "XO" + attribute \enum_value_10010 "A" + attribute \enum_value_10011 "M" + attribute \enum_value_10100 "MD" + attribute \enum_value_10101 "MDS" + attribute \enum_value_10110 "VA" + attribute \enum_value_10111 "VC" + attribute \enum_value_11000 "VX" + attribute \enum_value_11001 "EVX" + attribute \enum_value_11010 "EVS" + attribute \enum_value_11011 "Z22" + attribute \enum_value_11100 "Z23" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 5 output 3 \dec31_dec_sub21_form + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 12 output 1 \dec31_dec_sub21_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 5 \dec31_dec_sub21_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 output 6 \dec31_dec_sub21_in2_sel + attribute \enum_base_type "In3Sel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RS" + attribute \enum_value_10 "RB" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 7 \dec31_dec_sub21_in3_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 7 output 2 \dec31_dec_sub21_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 15 \dec31_dec_sub21_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 16 \dec31_dec_sub21_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 21 \dec31_dec_sub21_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 output 11 \dec31_dec_sub21_ldst_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 23 \dec31_dec_sub21_lk + attribute \enum_base_type "OutSel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RT" + attribute \enum_value_10 "RA" + attribute \enum_value_11 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 8 \dec31_dec_sub21_out_sel + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 13 \dec31_dec_sub21_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 20 \dec31_dec_sub21_rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 24 \dec31_dec_sub21_sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 22 \dec31_dec_sub21_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 19 \dec31_dec_sub21_sgn_ext + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 12 \dec31_dec_sub21_upd + attribute \src "issuer_ls180.v:90764.7-90764.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + wire width 32 input 25 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:320" + wire width 5 \opcode_switch + attribute \src "issuer_ls180.v:90764.7-90764.20" + process $proc$issuer_ls180.v:90764$3820 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "issuer_ls180.v:91021.3-91069.6" + process $proc$issuer_ls180.v:91021$3796 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub21_function_unit[11:0] $1\dec31_dec_sub21_function_unit[11:0] + attribute \src "issuer_ls180.v:91022.5-91022.29" + switch \initial + attribute \src "issuer_ls180.v:91022.9-91022.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub21_function_unit[11:0] 12'000000000100 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub21_function_unit[11:0] 12'000000000100 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub21_function_unit[11:0] 12'000000000100 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub21_function_unit[11:0] 12'000000000100 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub21_function_unit[11:0] 12'000000000100 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub21_function_unit[11:0] 12'000000000100 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub21_function_unit[11:0] 12'000000000100 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub21_function_unit[11:0] 12'000000000100 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub21_function_unit[11:0] 12'000000000100 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub21_function_unit[11:0] 12'000000000100 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub21_function_unit[11:0] 12'000000000100 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub21_function_unit[11:0] 12'000000000100 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub21_function_unit[11:0] 12'000000000100 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub21_function_unit[11:0] 12'000000000100 + case + assign $1\dec31_dec_sub21_function_unit[11:0] 12'000000000000 + end + sync always + update \dec31_dec_sub21_function_unit $0\dec31_dec_sub21_function_unit[11:0] + end + attribute \src "issuer_ls180.v:91070.3-91118.6" + process $proc$issuer_ls180.v:91070$3797 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub21_ldst_len[3:0] $1\dec31_dec_sub21_ldst_len[3:0] + attribute \src "issuer_ls180.v:91071.5-91071.29" + switch \initial + attribute \src "issuer_ls180.v:91071.9-91071.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub21_ldst_len[3:0] 4'0001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub21_ldst_len[3:0] 4'1000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub21_ldst_len[3:0] 4'1000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub21_ldst_len[3:0] 4'1000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub21_ldst_len[3:0] 4'0010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub21_ldst_len[3:0] 4'0100 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub21_ldst_len[3:0] 4'0100 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub21_ldst_len[3:0] 4'0100 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub21_ldst_len[3:0] 4'0001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub21_ldst_len[3:0] 4'1000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub21_ldst_len[3:0] 4'1000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub21_ldst_len[3:0] 4'1000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub21_ldst_len[3:0] 4'0010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub21_ldst_len[3:0] 4'0100 + case + assign $1\dec31_dec_sub21_ldst_len[3:0] 4'0000 + end + sync always + update \dec31_dec_sub21_ldst_len $0\dec31_dec_sub21_ldst_len[3:0] + end + attribute \src "issuer_ls180.v:91119.3-91167.6" + process $proc$issuer_ls180.v:91119$3798 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub21_upd[1:0] $1\dec31_dec_sub21_upd[1:0] + attribute \src "issuer_ls180.v:91120.5-91120.29" + switch \initial + attribute \src "issuer_ls180.v:91120.9-91120.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub21_upd[1:0] 2'10 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub21_upd[1:0] 2'10 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub21_upd[1:0] 2'01 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub21_upd[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub21_upd[1:0] 2'10 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub21_upd[1:0] 2'01 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub21_upd[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub21_upd[1:0] 2'10 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub21_upd[1:0] 2'10 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub21_upd[1:0] 2'10 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub21_upd[1:0] 2'01 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub21_upd[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub21_upd[1:0] 2'10 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub21_upd[1:0] 2'10 + case + assign $1\dec31_dec_sub21_upd[1:0] 2'00 + end + sync always + update \dec31_dec_sub21_upd $0\dec31_dec_sub21_upd[1:0] + end + attribute \src "issuer_ls180.v:91168.3-91216.6" + process $proc$issuer_ls180.v:91168$3799 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub21_rc_sel[1:0] $1\dec31_dec_sub21_rc_sel[1:0] + attribute \src "issuer_ls180.v:91169.5-91169.29" + switch \initial + attribute \src "issuer_ls180.v:91169.9-91169.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub21_rc_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub21_rc_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub21_rc_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub21_rc_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub21_rc_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub21_rc_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub21_rc_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub21_rc_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub21_rc_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub21_rc_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub21_rc_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub21_rc_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub21_rc_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub21_rc_sel[1:0] 2'00 + case + assign $1\dec31_dec_sub21_rc_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub21_rc_sel $0\dec31_dec_sub21_rc_sel[1:0] + end + attribute \src "issuer_ls180.v:91217.3-91265.6" + process $proc$issuer_ls180.v:91217$3800 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub21_cry_in[1:0] $1\dec31_dec_sub21_cry_in[1:0] + attribute \src "issuer_ls180.v:91218.5-91218.29" + switch \initial + attribute \src "issuer_ls180.v:91218.9-91218.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub21_cry_in[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub21_cry_in[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub21_cry_in[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub21_cry_in[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub21_cry_in[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub21_cry_in[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub21_cry_in[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub21_cry_in[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub21_cry_in[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub21_cry_in[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub21_cry_in[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub21_cry_in[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub21_cry_in[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub21_cry_in[1:0] 2'00 + case + assign $1\dec31_dec_sub21_cry_in[1:0] 2'00 + end + sync always + update \dec31_dec_sub21_cry_in $0\dec31_dec_sub21_cry_in[1:0] + end + attribute \src "issuer_ls180.v:91266.3-91314.6" + process $proc$issuer_ls180.v:91266$3801 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub21_inv_a[0:0] $1\dec31_dec_sub21_inv_a[0:0] + attribute \src "issuer_ls180.v:91267.5-91267.29" + switch \initial + attribute \src "issuer_ls180.v:91267.9-91267.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub21_inv_a[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub21_inv_a[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub21_inv_a[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub21_inv_a[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub21_inv_a[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub21_inv_a[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub21_inv_a[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub21_inv_a[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub21_inv_a[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub21_inv_a[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub21_inv_a[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub21_inv_a[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub21_inv_a[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub21_inv_a[0:0] 1'0 + case + assign $1\dec31_dec_sub21_inv_a[0:0] 1'0 + end + sync always + update \dec31_dec_sub21_inv_a $0\dec31_dec_sub21_inv_a[0:0] + end + attribute \src "issuer_ls180.v:91315.3-91363.6" + process $proc$issuer_ls180.v:91315$3802 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub21_inv_out[0:0] $1\dec31_dec_sub21_inv_out[0:0] + attribute \src "issuer_ls180.v:91316.5-91316.29" + switch \initial + attribute \src "issuer_ls180.v:91316.9-91316.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub21_inv_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub21_inv_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub21_inv_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub21_inv_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub21_inv_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub21_inv_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub21_inv_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub21_inv_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub21_inv_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub21_inv_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub21_inv_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub21_inv_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub21_inv_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub21_inv_out[0:0] 1'0 + case + assign $1\dec31_dec_sub21_inv_out[0:0] 1'0 + end + sync always + update \dec31_dec_sub21_inv_out $0\dec31_dec_sub21_inv_out[0:0] + end + attribute \src "issuer_ls180.v:91364.3-91412.6" + process $proc$issuer_ls180.v:91364$3803 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub21_cry_out[0:0] $1\dec31_dec_sub21_cry_out[0:0] + attribute \src "issuer_ls180.v:91365.5-91365.29" + switch \initial + attribute \src "issuer_ls180.v:91365.9-91365.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub21_cry_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub21_cry_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub21_cry_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub21_cry_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub21_cry_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub21_cry_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub21_cry_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub21_cry_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub21_cry_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub21_cry_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub21_cry_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub21_cry_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub21_cry_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub21_cry_out[0:0] 1'0 + case + assign $1\dec31_dec_sub21_cry_out[0:0] 1'0 + end + sync always + update \dec31_dec_sub21_cry_out $0\dec31_dec_sub21_cry_out[0:0] + end + attribute \src "issuer_ls180.v:91413.3-91461.6" + process $proc$issuer_ls180.v:91413$3804 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub21_br[0:0] $1\dec31_dec_sub21_br[0:0] + attribute \src "issuer_ls180.v:91414.5-91414.29" + switch \initial + attribute \src "issuer_ls180.v:91414.9-91414.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub21_br[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub21_br[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub21_br[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub21_br[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub21_br[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub21_br[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub21_br[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub21_br[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub21_br[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub21_br[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub21_br[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub21_br[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub21_br[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub21_br[0:0] 1'0 + case + assign $1\dec31_dec_sub21_br[0:0] 1'0 + end + sync always + update \dec31_dec_sub21_br $0\dec31_dec_sub21_br[0:0] + end + attribute \src "issuer_ls180.v:91462.3-91510.6" + process $proc$issuer_ls180.v:91462$3805 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub21_sgn_ext[0:0] $1\dec31_dec_sub21_sgn_ext[0:0] + attribute \src "issuer_ls180.v:91463.5-91463.29" + switch \initial + attribute \src "issuer_ls180.v:91463.9-91463.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub21_sgn_ext[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub21_sgn_ext[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub21_sgn_ext[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub21_sgn_ext[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub21_sgn_ext[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub21_sgn_ext[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub21_sgn_ext[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub21_sgn_ext[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub21_sgn_ext[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub21_sgn_ext[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub21_sgn_ext[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub21_sgn_ext[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub21_sgn_ext[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub21_sgn_ext[0:0] 1'0 + case + assign $1\dec31_dec_sub21_sgn_ext[0:0] 1'0 + end + sync always + update \dec31_dec_sub21_sgn_ext $0\dec31_dec_sub21_sgn_ext[0:0] + end + attribute \src "issuer_ls180.v:91511.3-91559.6" + process $proc$issuer_ls180.v:91511$3806 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub21_rsrv[0:0] $1\dec31_dec_sub21_rsrv[0:0] + attribute \src "issuer_ls180.v:91512.5-91512.29" + switch \initial + attribute \src "issuer_ls180.v:91512.9-91512.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub21_rsrv[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub21_rsrv[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub21_rsrv[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub21_rsrv[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub21_rsrv[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub21_rsrv[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub21_rsrv[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub21_rsrv[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub21_rsrv[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub21_rsrv[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub21_rsrv[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub21_rsrv[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub21_rsrv[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub21_rsrv[0:0] 1'0 + case + assign $1\dec31_dec_sub21_rsrv[0:0] 1'0 + end + sync always + update \dec31_dec_sub21_rsrv $0\dec31_dec_sub21_rsrv[0:0] + end + attribute \src "issuer_ls180.v:91560.3-91608.6" + process $proc$issuer_ls180.v:91560$3807 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub21_internal_op[6:0] $1\dec31_dec_sub21_internal_op[6:0] + attribute \src "issuer_ls180.v:91561.5-91561.29" + switch \initial + attribute \src "issuer_ls180.v:91561.9-91561.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub21_internal_op[6:0] 7'0100101 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub21_internal_op[6:0] 7'0100101 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub21_internal_op[6:0] 7'0100101 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub21_internal_op[6:0] 7'0100101 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub21_internal_op[6:0] 7'0100101 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub21_internal_op[6:0] 7'0100101 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub21_internal_op[6:0] 7'0100101 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub21_internal_op[6:0] 7'0100101 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub21_internal_op[6:0] 7'0100110 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub21_internal_op[6:0] 7'0100110 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub21_internal_op[6:0] 7'0100110 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub21_internal_op[6:0] 7'0100110 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub21_internal_op[6:0] 7'0100110 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub21_internal_op[6:0] 7'0100110 + case + assign $1\dec31_dec_sub21_internal_op[6:0] 7'0000000 + end + sync always + update \dec31_dec_sub21_internal_op $0\dec31_dec_sub21_internal_op[6:0] + end + attribute \src "issuer_ls180.v:91609.3-91657.6" + process $proc$issuer_ls180.v:91609$3808 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub21_is_32b[0:0] $1\dec31_dec_sub21_is_32b[0:0] + attribute \src "issuer_ls180.v:91610.5-91610.29" + switch \initial + attribute \src "issuer_ls180.v:91610.9-91610.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub21_is_32b[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub21_is_32b[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub21_is_32b[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub21_is_32b[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub21_is_32b[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub21_is_32b[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub21_is_32b[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub21_is_32b[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub21_is_32b[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub21_is_32b[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub21_is_32b[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub21_is_32b[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub21_is_32b[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub21_is_32b[0:0] 1'0 + case + assign $1\dec31_dec_sub21_is_32b[0:0] 1'0 + end + sync always + update \dec31_dec_sub21_is_32b $0\dec31_dec_sub21_is_32b[0:0] + end + attribute \src "issuer_ls180.v:91658.3-91706.6" + process $proc$issuer_ls180.v:91658$3809 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub21_sgn[0:0] $1\dec31_dec_sub21_sgn[0:0] + attribute \src "issuer_ls180.v:91659.5-91659.29" + switch \initial + attribute \src "issuer_ls180.v:91659.9-91659.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub21_sgn[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub21_sgn[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub21_sgn[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub21_sgn[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub21_sgn[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub21_sgn[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub21_sgn[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub21_sgn[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub21_sgn[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub21_sgn[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub21_sgn[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub21_sgn[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub21_sgn[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub21_sgn[0:0] 1'0 + case + assign $1\dec31_dec_sub21_sgn[0:0] 1'0 + end + sync always + update \dec31_dec_sub21_sgn $0\dec31_dec_sub21_sgn[0:0] + end + attribute \src "issuer_ls180.v:91707.3-91755.6" + process $proc$issuer_ls180.v:91707$3810 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub21_lk[0:0] $1\dec31_dec_sub21_lk[0:0] + attribute \src "issuer_ls180.v:91708.5-91708.29" + switch \initial + attribute \src "issuer_ls180.v:91708.9-91708.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub21_lk[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub21_lk[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub21_lk[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub21_lk[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub21_lk[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub21_lk[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub21_lk[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub21_lk[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub21_lk[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub21_lk[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub21_lk[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub21_lk[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub21_lk[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub21_lk[0:0] 1'0 + case + assign $1\dec31_dec_sub21_lk[0:0] 1'0 + end + sync always + update \dec31_dec_sub21_lk $0\dec31_dec_sub21_lk[0:0] + end + attribute \src "issuer_ls180.v:91756.3-91804.6" + process $proc$issuer_ls180.v:91756$3811 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub21_sgl_pipe[0:0] $1\dec31_dec_sub21_sgl_pipe[0:0] + attribute \src "issuer_ls180.v:91757.5-91757.29" + switch \initial + attribute \src "issuer_ls180.v:91757.9-91757.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub21_sgl_pipe[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub21_sgl_pipe[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub21_sgl_pipe[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub21_sgl_pipe[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub21_sgl_pipe[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub21_sgl_pipe[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub21_sgl_pipe[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub21_sgl_pipe[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub21_sgl_pipe[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub21_sgl_pipe[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub21_sgl_pipe[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub21_sgl_pipe[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub21_sgl_pipe[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub21_sgl_pipe[0:0] 1'1 + case + assign $1\dec31_dec_sub21_sgl_pipe[0:0] 1'0 + end + sync always + update \dec31_dec_sub21_sgl_pipe $0\dec31_dec_sub21_sgl_pipe[0:0] + end + attribute \src "issuer_ls180.v:91805.3-91835.6" + process $proc$issuer_ls180.v:91805$3812 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub21_asmcode[7:0] $1\dec31_dec_sub21_asmcode[7:0] + attribute \src "issuer_ls180.v:91806.5-91806.29" + switch \initial + attribute \src "issuer_ls180.v:91806.9-91806.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub21_asmcode[7:0] 8'01010110 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub21_asmcode[7:0] 8'01010111 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub21_asmcode[7:0] 8'01100100 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub21_asmcode[7:0] 8'01100101 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub21_asmcode[7:0] 8'01101000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub21_asmcode[7:0] 8'10100111 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub21_asmcode[7:0] 8'10110000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub21_asmcode[7:0] 8'10110001 + case + assign $1\dec31_dec_sub21_asmcode[7:0] 8'00000000 + end + sync always + update \dec31_dec_sub21_asmcode $0\dec31_dec_sub21_asmcode[7:0] + end + attribute \src "issuer_ls180.v:91836.3-91884.6" + process $proc$issuer_ls180.v:91836$3813 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub21_form[4:0] $1\dec31_dec_sub21_form[4:0] + attribute \src "issuer_ls180.v:91837.5-91837.29" + switch \initial + attribute \src "issuer_ls180.v:91837.9-91837.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub21_form[4:0] 5'01000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub21_form[4:0] 5'01000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub21_form[4:0] 5'01000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub21_form[4:0] 5'01000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub21_form[4:0] 5'01000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub21_form[4:0] 5'01000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub21_form[4:0] 5'01000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub21_form[4:0] 5'01000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub21_form[4:0] 5'01000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub21_form[4:0] 5'01000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub21_form[4:0] 5'01000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub21_form[4:0] 5'01000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub21_form[4:0] 5'01000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub21_form[4:0] 5'01000 + case + assign $1\dec31_dec_sub21_form[4:0] 5'00000 + end + sync always + update \dec31_dec_sub21_form $0\dec31_dec_sub21_form[4:0] + end + attribute \src "issuer_ls180.v:91885.3-91933.6" + process $proc$issuer_ls180.v:91885$3814 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub21_in1_sel[2:0] $1\dec31_dec_sub21_in1_sel[2:0] + attribute \src "issuer_ls180.v:91886.5-91886.29" + switch \initial + attribute \src "issuer_ls180.v:91886.9-91886.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub21_in1_sel[2:0] 3'010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub21_in1_sel[2:0] 3'010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub21_in1_sel[2:0] 3'010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub21_in1_sel[2:0] 3'010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub21_in1_sel[2:0] 3'010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub21_in1_sel[2:0] 3'010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub21_in1_sel[2:0] 3'010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub21_in1_sel[2:0] 3'010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub21_in1_sel[2:0] 3'010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub21_in1_sel[2:0] 3'010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub21_in1_sel[2:0] 3'010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub21_in1_sel[2:0] 3'010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub21_in1_sel[2:0] 3'010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub21_in1_sel[2:0] 3'010 + case + assign $1\dec31_dec_sub21_in1_sel[2:0] 3'000 + end + sync always + update \dec31_dec_sub21_in1_sel $0\dec31_dec_sub21_in1_sel[2:0] + end + attribute \src "issuer_ls180.v:91934.3-91982.6" + process $proc$issuer_ls180.v:91934$3815 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub21_in2_sel[3:0] $1\dec31_dec_sub21_in2_sel[3:0] + attribute \src "issuer_ls180.v:91935.5-91935.29" + switch \initial + attribute \src "issuer_ls180.v:91935.9-91935.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub21_in2_sel[3:0] 4'0001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub21_in2_sel[3:0] 4'0001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub21_in2_sel[3:0] 4'0001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub21_in2_sel[3:0] 4'0001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub21_in2_sel[3:0] 4'0001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub21_in2_sel[3:0] 4'0001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub21_in2_sel[3:0] 4'0001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub21_in2_sel[3:0] 4'0001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub21_in2_sel[3:0] 4'0001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub21_in2_sel[3:0] 4'0001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub21_in2_sel[3:0] 4'0001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub21_in2_sel[3:0] 4'0001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub21_in2_sel[3:0] 4'0001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub21_in2_sel[3:0] 4'0001 + case + assign $1\dec31_dec_sub21_in2_sel[3:0] 4'0000 + end + sync always + update \dec31_dec_sub21_in2_sel $0\dec31_dec_sub21_in2_sel[3:0] + end + attribute \src "issuer_ls180.v:91983.3-92031.6" + process $proc$issuer_ls180.v:91983$3816 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub21_in3_sel[1:0] $1\dec31_dec_sub21_in3_sel[1:0] + attribute \src "issuer_ls180.v:91984.5-91984.29" + switch \initial + attribute \src "issuer_ls180.v:91984.9-91984.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub21_in3_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub21_in3_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub21_in3_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub21_in3_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub21_in3_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub21_in3_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub21_in3_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub21_in3_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub21_in3_sel[1:0] 2'01 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub21_in3_sel[1:0] 2'01 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub21_in3_sel[1:0] 2'01 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub21_in3_sel[1:0] 2'01 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub21_in3_sel[1:0] 2'01 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub21_in3_sel[1:0] 2'01 + case + assign $1\dec31_dec_sub21_in3_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub21_in3_sel $0\dec31_dec_sub21_in3_sel[1:0] + end + attribute \src "issuer_ls180.v:92032.3-92080.6" + process $proc$issuer_ls180.v:92032$3817 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub21_out_sel[1:0] $1\dec31_dec_sub21_out_sel[1:0] + attribute \src "issuer_ls180.v:92033.5-92033.29" + switch \initial + attribute \src "issuer_ls180.v:92033.9-92033.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub21_out_sel[1:0] 2'01 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub21_out_sel[1:0] 2'01 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub21_out_sel[1:0] 2'01 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub21_out_sel[1:0] 2'01 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub21_out_sel[1:0] 2'01 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub21_out_sel[1:0] 2'01 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub21_out_sel[1:0] 2'01 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub21_out_sel[1:0] 2'01 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub21_out_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub21_out_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub21_out_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub21_out_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub21_out_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub21_out_sel[1:0] 2'00 + case + assign $1\dec31_dec_sub21_out_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub21_out_sel $0\dec31_dec_sub21_out_sel[1:0] + end + attribute \src "issuer_ls180.v:92081.3-92129.6" + process $proc$issuer_ls180.v:92081$3818 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub21_cr_in[2:0] $1\dec31_dec_sub21_cr_in[2:0] + attribute \src "issuer_ls180.v:92082.5-92082.29" + switch \initial + attribute \src "issuer_ls180.v:92082.9-92082.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub21_cr_in[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub21_cr_in[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub21_cr_in[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub21_cr_in[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub21_cr_in[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub21_cr_in[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub21_cr_in[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub21_cr_in[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub21_cr_in[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub21_cr_in[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub21_cr_in[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub21_cr_in[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub21_cr_in[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub21_cr_in[2:0] 3'000 + case + assign $1\dec31_dec_sub21_cr_in[2:0] 3'000 + end + sync always + update \dec31_dec_sub21_cr_in $0\dec31_dec_sub21_cr_in[2:0] + end + attribute \src "issuer_ls180.v:92130.3-92178.6" + process $proc$issuer_ls180.v:92130$3819 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub21_cr_out[2:0] $1\dec31_dec_sub21_cr_out[2:0] + attribute \src "issuer_ls180.v:92131.5-92131.29" + switch \initial + attribute \src "issuer_ls180.v:92131.9-92131.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11010 + assign { } { } + assign $1\dec31_dec_sub21_cr_out[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub21_cr_out[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub21_cr_out[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub21_cr_out[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub21_cr_out[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub21_cr_out[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub21_cr_out[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub21_cr_out[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub21_cr_out[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub21_cr_out[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub21_cr_out[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub21_cr_out[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub21_cr_out[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub21_cr_out[2:0] 3'000 + case + assign $1\dec31_dec_sub21_cr_out[2:0] 3'000 + end + sync always + update \dec31_dec_sub21_cr_out $0\dec31_dec_sub21_cr_out[2:0] + end + connect \opcode_switch \opcode_in [10:6] +end +attribute \src "issuer_ls180.v:92184.1-93763.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.dec2.dec.dec31.dec31_dec_sub22" +attribute \generator "nMigen" +module \dec31_dec_sub22 + attribute \src "issuer_ls180.v:92717.3-92771.6" + wire width 8 $0\dec31_dec_sub22_asmcode[7:0] + attribute \src "issuer_ls180.v:92937.3-92991.6" + wire $0\dec31_dec_sub22_br[0:0] + attribute \src "issuer_ls180.v:93652.3-93706.6" + wire width 3 $0\dec31_dec_sub22_cr_in[2:0] + attribute \src "issuer_ls180.v:93707.3-93761.6" + wire width 3 $0\dec31_dec_sub22_cr_out[2:0] + attribute \src "issuer_ls180.v:92662.3-92716.6" + wire width 2 $0\dec31_dec_sub22_cry_in[1:0] + attribute \src "issuer_ls180.v:92882.3-92936.6" + wire $0\dec31_dec_sub22_cry_out[0:0] + attribute \src "issuer_ls180.v:93377.3-93431.6" + wire width 5 $0\dec31_dec_sub22_form[4:0] + attribute \src "issuer_ls180.v:92442.3-92496.6" + wire width 12 $0\dec31_dec_sub22_function_unit[11:0] + attribute \src "issuer_ls180.v:93432.3-93486.6" + wire width 3 $0\dec31_dec_sub22_in1_sel[2:0] + attribute \src "issuer_ls180.v:93487.3-93541.6" + wire width 4 $0\dec31_dec_sub22_in2_sel[3:0] + attribute \src "issuer_ls180.v:93542.3-93596.6" + wire width 2 $0\dec31_dec_sub22_in3_sel[1:0] + attribute \src "issuer_ls180.v:93047.3-93101.6" + wire width 7 $0\dec31_dec_sub22_internal_op[6:0] + attribute \src "issuer_ls180.v:92772.3-92826.6" + wire $0\dec31_dec_sub22_inv_a[0:0] + attribute \src "issuer_ls180.v:92827.3-92881.6" + wire $0\dec31_dec_sub22_inv_out[0:0] + attribute \src "issuer_ls180.v:93157.3-93211.6" + wire $0\dec31_dec_sub22_is_32b[0:0] + attribute \src "issuer_ls180.v:92497.3-92551.6" + wire width 4 $0\dec31_dec_sub22_ldst_len[3:0] + attribute \src "issuer_ls180.v:93267.3-93321.6" + wire $0\dec31_dec_sub22_lk[0:0] + attribute \src "issuer_ls180.v:93597.3-93651.6" + wire width 2 $0\dec31_dec_sub22_out_sel[1:0] + attribute \src "issuer_ls180.v:92607.3-92661.6" + wire width 2 $0\dec31_dec_sub22_rc_sel[1:0] + attribute \src "issuer_ls180.v:93102.3-93156.6" + wire $0\dec31_dec_sub22_rsrv[0:0] + attribute \src "issuer_ls180.v:93322.3-93376.6" + wire $0\dec31_dec_sub22_sgl_pipe[0:0] + attribute \src "issuer_ls180.v:93212.3-93266.6" + wire $0\dec31_dec_sub22_sgn[0:0] + attribute \src "issuer_ls180.v:92992.3-93046.6" + wire $0\dec31_dec_sub22_sgn_ext[0:0] + attribute \src "issuer_ls180.v:92552.3-92606.6" + wire width 2 $0\dec31_dec_sub22_upd[1:0] + attribute \src "issuer_ls180.v:92185.7-92185.20" + wire $0\initial[0:0] + attribute \src "issuer_ls180.v:92717.3-92771.6" + wire width 8 $1\dec31_dec_sub22_asmcode[7:0] + attribute \src "issuer_ls180.v:92937.3-92991.6" + wire $1\dec31_dec_sub22_br[0:0] + attribute \src "issuer_ls180.v:93652.3-93706.6" + wire width 3 $1\dec31_dec_sub22_cr_in[2:0] + attribute \src "issuer_ls180.v:93707.3-93761.6" + wire width 3 $1\dec31_dec_sub22_cr_out[2:0] + attribute \src "issuer_ls180.v:92662.3-92716.6" + wire width 2 $1\dec31_dec_sub22_cry_in[1:0] + attribute \src "issuer_ls180.v:92882.3-92936.6" + wire $1\dec31_dec_sub22_cry_out[0:0] + attribute \src "issuer_ls180.v:93377.3-93431.6" + wire width 5 $1\dec31_dec_sub22_form[4:0] + attribute \src "issuer_ls180.v:92442.3-92496.6" + wire width 12 $1\dec31_dec_sub22_function_unit[11:0] + attribute \src "issuer_ls180.v:93432.3-93486.6" + wire width 3 $1\dec31_dec_sub22_in1_sel[2:0] + attribute \src "issuer_ls180.v:93487.3-93541.6" + wire width 4 $1\dec31_dec_sub22_in2_sel[3:0] + attribute \src "issuer_ls180.v:93542.3-93596.6" + wire width 2 $1\dec31_dec_sub22_in3_sel[1:0] + attribute \src "issuer_ls180.v:93047.3-93101.6" + wire width 7 $1\dec31_dec_sub22_internal_op[6:0] + attribute \src "issuer_ls180.v:92772.3-92826.6" + wire $1\dec31_dec_sub22_inv_a[0:0] + attribute \src "issuer_ls180.v:92827.3-92881.6" + wire $1\dec31_dec_sub22_inv_out[0:0] + attribute \src "issuer_ls180.v:93157.3-93211.6" + wire $1\dec31_dec_sub22_is_32b[0:0] + attribute \src "issuer_ls180.v:92497.3-92551.6" + wire width 4 $1\dec31_dec_sub22_ldst_len[3:0] + attribute \src "issuer_ls180.v:93267.3-93321.6" + wire $1\dec31_dec_sub22_lk[0:0] + attribute \src "issuer_ls180.v:93597.3-93651.6" + wire width 2 $1\dec31_dec_sub22_out_sel[1:0] + attribute \src "issuer_ls180.v:92607.3-92661.6" + wire width 2 $1\dec31_dec_sub22_rc_sel[1:0] + attribute \src "issuer_ls180.v:93102.3-93156.6" + wire $1\dec31_dec_sub22_rsrv[0:0] + attribute \src "issuer_ls180.v:93322.3-93376.6" + wire $1\dec31_dec_sub22_sgl_pipe[0:0] + attribute \src "issuer_ls180.v:93212.3-93266.6" + wire $1\dec31_dec_sub22_sgn[0:0] + attribute \src "issuer_ls180.v:92992.3-93046.6" + wire $1\dec31_dec_sub22_sgn_ext[0:0] + attribute \src "issuer_ls180.v:92552.3-92606.6" + wire width 2 $1\dec31_dec_sub22_upd[1:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 8 output 4 \dec31_dec_sub22_asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 18 \dec31_dec_sub22_br + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 9 \dec31_dec_sub22_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 10 \dec31_dec_sub22_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 14 \dec31_dec_sub22_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 17 \dec31_dec_sub22_cry_out + attribute \enum_base_type "Form" + attribute \enum_value_00000 "NONE" + attribute \enum_value_00001 "I" + attribute \enum_value_00010 "B" + attribute \enum_value_00011 "SC" + attribute \enum_value_00100 "D" + attribute \enum_value_00101 "DS" + attribute \enum_value_00110 "DQ" + attribute \enum_value_00111 "DX" + attribute \enum_value_01000 "X" + attribute \enum_value_01001 "XL" + attribute \enum_value_01010 "XFX" + attribute \enum_value_01011 "XFL" + attribute \enum_value_01100 "XX1" + attribute \enum_value_01101 "XX2" + attribute \enum_value_01110 "XX3" + attribute \enum_value_01111 "XX4" + attribute \enum_value_10000 "XS" + attribute \enum_value_10001 "XO" + attribute \enum_value_10010 "A" + attribute \enum_value_10011 "M" + attribute \enum_value_10100 "MD" + attribute \enum_value_10101 "MDS" + attribute \enum_value_10110 "VA" + attribute \enum_value_10111 "VC" + attribute \enum_value_11000 "VX" + attribute \enum_value_11001 "EVX" + attribute \enum_value_11010 "EVS" + attribute \enum_value_11011 "Z22" + attribute \enum_value_11100 "Z23" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 5 output 3 \dec31_dec_sub22_form + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 12 output 1 \dec31_dec_sub22_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 5 \dec31_dec_sub22_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 output 6 \dec31_dec_sub22_in2_sel + attribute \enum_base_type "In3Sel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RS" + attribute \enum_value_10 "RB" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 7 \dec31_dec_sub22_in3_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 7 output 2 \dec31_dec_sub22_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 15 \dec31_dec_sub22_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 16 \dec31_dec_sub22_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 21 \dec31_dec_sub22_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 output 11 \dec31_dec_sub22_ldst_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 23 \dec31_dec_sub22_lk + attribute \enum_base_type "OutSel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RT" + attribute \enum_value_10 "RA" + attribute \enum_value_11 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 8 \dec31_dec_sub22_out_sel + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 13 \dec31_dec_sub22_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 20 \dec31_dec_sub22_rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 24 \dec31_dec_sub22_sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 22 \dec31_dec_sub22_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 19 \dec31_dec_sub22_sgn_ext + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 12 \dec31_dec_sub22_upd + attribute \src "issuer_ls180.v:92185.7-92185.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + wire width 32 input 25 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:320" + wire width 5 \opcode_switch + attribute \src "issuer_ls180.v:92185.7-92185.20" + process $proc$issuer_ls180.v:92185$3845 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "issuer_ls180.v:92442.3-92496.6" + process $proc$issuer_ls180.v:92442$3821 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub22_function_unit[11:0] $1\dec31_dec_sub22_function_unit[11:0] + attribute \src "issuer_ls180.v:92443.5-92443.29" + switch \initial + attribute \src "issuer_ls180.v:92443.9-92443.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub22_function_unit[11:0] 12'000000000010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub22_function_unit[11:0] 12'000000000010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub22_function_unit[11:0] 12'000000000010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub22_function_unit[11:0] 12'000000000010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub22_function_unit[11:0] 12'000000000100 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub22_function_unit[11:0] 12'000000000010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub22_function_unit[11:0] 12'000000000010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub22_function_unit[11:0] 12'000000000100 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub22_function_unit[11:0] 12'000000000100 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub22_function_unit[11:0] 12'000000000100 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub22_function_unit[11:0] 12'000000000100 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub22_function_unit[11:0] 12'000000000100 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub22_function_unit[11:0] 12'000000000100 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub22_function_unit[11:0] 12'000000000100 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub22_function_unit[11:0] 12'000000000100 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub22_function_unit[11:0] 12'000000000010 + case + assign $1\dec31_dec_sub22_function_unit[11:0] 12'000000000000 + end + sync always + update \dec31_dec_sub22_function_unit $0\dec31_dec_sub22_function_unit[11:0] + end + attribute \src "issuer_ls180.v:92497.3-92551.6" + process $proc$issuer_ls180.v:92497$3822 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub22_ldst_len[3:0] $1\dec31_dec_sub22_ldst_len[3:0] + attribute \src "issuer_ls180.v:92498.5-92498.29" + switch \initial + attribute \src "issuer_ls180.v:92498.9-92498.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub22_ldst_len[3:0] 4'0000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub22_ldst_len[3:0] 4'0000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub22_ldst_len[3:0] 4'0000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub22_ldst_len[3:0] 4'0000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub22_ldst_len[3:0] 4'0000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub22_ldst_len[3:0] 4'0000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub22_ldst_len[3:0] 4'0000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub22_ldst_len[3:0] 4'0010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub22_ldst_len[3:0] 4'0100 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub22_ldst_len[3:0] 4'0001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub22_ldst_len[3:0] 4'1000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub22_ldst_len[3:0] 4'0010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub22_ldst_len[3:0] 4'0010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub22_ldst_len[3:0] 4'0100 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub22_ldst_len[3:0] 4'0100 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub22_ldst_len[3:0] 4'0000 + case + assign $1\dec31_dec_sub22_ldst_len[3:0] 4'0000 + end + sync always + update \dec31_dec_sub22_ldst_len $0\dec31_dec_sub22_ldst_len[3:0] + end + attribute \src "issuer_ls180.v:92552.3-92606.6" + process $proc$issuer_ls180.v:92552$3823 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub22_upd[1:0] $1\dec31_dec_sub22_upd[1:0] + attribute \src "issuer_ls180.v:92553.5-92553.29" + switch \initial + attribute \src "issuer_ls180.v:92553.9-92553.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub22_upd[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub22_upd[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub22_upd[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub22_upd[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub22_upd[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub22_upd[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub22_upd[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub22_upd[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub22_upd[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub22_upd[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub22_upd[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub22_upd[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub22_upd[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub22_upd[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub22_upd[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub22_upd[1:0] 2'00 + case + assign $1\dec31_dec_sub22_upd[1:0] 2'00 + end + sync always + update \dec31_dec_sub22_upd $0\dec31_dec_sub22_upd[1:0] + end + attribute \src "issuer_ls180.v:92607.3-92661.6" + process $proc$issuer_ls180.v:92607$3824 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub22_rc_sel[1:0] $1\dec31_dec_sub22_rc_sel[1:0] + attribute \src "issuer_ls180.v:92608.5-92608.29" + switch \initial + attribute \src "issuer_ls180.v:92608.9-92608.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub22_rc_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub22_rc_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub22_rc_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub22_rc_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub22_rc_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub22_rc_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub22_rc_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub22_rc_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub22_rc_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub22_rc_sel[1:0] 2'10 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub22_rc_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub22_rc_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub22_rc_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub22_rc_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub22_rc_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub22_rc_sel[1:0] 2'00 + case + assign $1\dec31_dec_sub22_rc_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub22_rc_sel $0\dec31_dec_sub22_rc_sel[1:0] + end + attribute \src "issuer_ls180.v:92662.3-92716.6" + process $proc$issuer_ls180.v:92662$3825 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub22_cry_in[1:0] $1\dec31_dec_sub22_cry_in[1:0] + attribute \src "issuer_ls180.v:92663.5-92663.29" + switch \initial + attribute \src "issuer_ls180.v:92663.9-92663.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub22_cry_in[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub22_cry_in[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub22_cry_in[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub22_cry_in[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub22_cry_in[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub22_cry_in[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub22_cry_in[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub22_cry_in[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub22_cry_in[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub22_cry_in[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub22_cry_in[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub22_cry_in[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub22_cry_in[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub22_cry_in[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub22_cry_in[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub22_cry_in[1:0] 2'00 + case + assign $1\dec31_dec_sub22_cry_in[1:0] 2'00 + end + sync always + update \dec31_dec_sub22_cry_in $0\dec31_dec_sub22_cry_in[1:0] + end + attribute \src "issuer_ls180.v:92717.3-92771.6" + process $proc$issuer_ls180.v:92717$3826 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub22_asmcode[7:0] $1\dec31_dec_sub22_asmcode[7:0] + attribute \src "issuer_ls180.v:92718.5-92718.29" + switch \initial + attribute \src "issuer_ls180.v:92718.9-92718.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub22_asmcode[7:0] 8'00101110 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub22_asmcode[7:0] 8'00101111 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub22_asmcode[7:0] 8'00110000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub22_asmcode[7:0] 8'00110001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub22_asmcode[7:0] 8'00110010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub22_asmcode[7:0] 8'01001001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub22_asmcode[7:0] 8'01001010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub22_asmcode[7:0] 8'01011101 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub22_asmcode[7:0] 8'01100110 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub22_asmcode[7:0] 8'10101000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub22_asmcode[7:0] 8'10101110 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub22_asmcode[7:0] 8'10110011 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub22_asmcode[7:0] 8'10110100 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub22_asmcode[7:0] 8'10111001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub22_asmcode[7:0] 8'10111010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub22_asmcode[7:0] 8'11001001 + case + assign $1\dec31_dec_sub22_asmcode[7:0] 8'00000000 + end + sync always + update \dec31_dec_sub22_asmcode $0\dec31_dec_sub22_asmcode[7:0] + end + attribute \src "issuer_ls180.v:92772.3-92826.6" + process $proc$issuer_ls180.v:92772$3827 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub22_inv_a[0:0] $1\dec31_dec_sub22_inv_a[0:0] + attribute \src "issuer_ls180.v:92773.5-92773.29" + switch \initial + attribute \src "issuer_ls180.v:92773.9-92773.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub22_inv_a[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub22_inv_a[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub22_inv_a[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub22_inv_a[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub22_inv_a[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub22_inv_a[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub22_inv_a[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub22_inv_a[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub22_inv_a[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub22_inv_a[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub22_inv_a[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub22_inv_a[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub22_inv_a[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub22_inv_a[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub22_inv_a[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub22_inv_a[0:0] 1'0 + case + assign $1\dec31_dec_sub22_inv_a[0:0] 1'0 + end + sync always + update \dec31_dec_sub22_inv_a $0\dec31_dec_sub22_inv_a[0:0] + end + attribute \src "issuer_ls180.v:92827.3-92881.6" + process $proc$issuer_ls180.v:92827$3828 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub22_inv_out[0:0] $1\dec31_dec_sub22_inv_out[0:0] + attribute \src "issuer_ls180.v:92828.5-92828.29" + switch \initial + attribute \src "issuer_ls180.v:92828.9-92828.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub22_inv_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub22_inv_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub22_inv_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub22_inv_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub22_inv_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub22_inv_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub22_inv_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub22_inv_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub22_inv_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub22_inv_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub22_inv_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub22_inv_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub22_inv_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub22_inv_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub22_inv_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub22_inv_out[0:0] 1'0 + case + assign $1\dec31_dec_sub22_inv_out[0:0] 1'0 + end + sync always + update \dec31_dec_sub22_inv_out $0\dec31_dec_sub22_inv_out[0:0] + end + attribute \src "issuer_ls180.v:92882.3-92936.6" + process $proc$issuer_ls180.v:92882$3829 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub22_cry_out[0:0] $1\dec31_dec_sub22_cry_out[0:0] + attribute \src "issuer_ls180.v:92883.5-92883.29" + switch \initial + attribute \src "issuer_ls180.v:92883.9-92883.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub22_cry_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub22_cry_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub22_cry_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub22_cry_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub22_cry_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub22_cry_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub22_cry_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub22_cry_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub22_cry_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub22_cry_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub22_cry_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub22_cry_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub22_cry_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub22_cry_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub22_cry_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub22_cry_out[0:0] 1'0 + case + assign $1\dec31_dec_sub22_cry_out[0:0] 1'0 + end + sync always + update \dec31_dec_sub22_cry_out $0\dec31_dec_sub22_cry_out[0:0] + end + attribute \src "issuer_ls180.v:92937.3-92991.6" + process $proc$issuer_ls180.v:92937$3830 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub22_br[0:0] $1\dec31_dec_sub22_br[0:0] + attribute \src "issuer_ls180.v:92938.5-92938.29" + switch \initial + attribute \src "issuer_ls180.v:92938.9-92938.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub22_br[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub22_br[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub22_br[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub22_br[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub22_br[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub22_br[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub22_br[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub22_br[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub22_br[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub22_br[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub22_br[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub22_br[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub22_br[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub22_br[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub22_br[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub22_br[0:0] 1'0 + case + assign $1\dec31_dec_sub22_br[0:0] 1'0 + end + sync always + update \dec31_dec_sub22_br $0\dec31_dec_sub22_br[0:0] + end + attribute \src "issuer_ls180.v:92992.3-93046.6" + process $proc$issuer_ls180.v:92992$3831 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub22_sgn_ext[0:0] $1\dec31_dec_sub22_sgn_ext[0:0] + attribute \src "issuer_ls180.v:92993.5-92993.29" + switch \initial + attribute \src "issuer_ls180.v:92993.9-92993.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub22_sgn_ext[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub22_sgn_ext[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub22_sgn_ext[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub22_sgn_ext[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub22_sgn_ext[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub22_sgn_ext[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub22_sgn_ext[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub22_sgn_ext[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub22_sgn_ext[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub22_sgn_ext[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub22_sgn_ext[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub22_sgn_ext[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub22_sgn_ext[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub22_sgn_ext[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub22_sgn_ext[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub22_sgn_ext[0:0] 1'0 + case + assign $1\dec31_dec_sub22_sgn_ext[0:0] 1'0 + end + sync always + update \dec31_dec_sub22_sgn_ext $0\dec31_dec_sub22_sgn_ext[0:0] + end + attribute \src "issuer_ls180.v:93047.3-93101.6" + process $proc$issuer_ls180.v:93047$3832 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub22_internal_op[6:0] $1\dec31_dec_sub22_internal_op[6:0] + attribute \src "issuer_ls180.v:93048.5-93048.29" + switch \initial + attribute \src "issuer_ls180.v:93048.9-93048.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub22_internal_op[6:0] 7'0000001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub22_internal_op[6:0] 7'0000001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub22_internal_op[6:0] 7'0000001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub22_internal_op[6:0] 7'0000001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub22_internal_op[6:0] 7'0011100 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub22_internal_op[6:0] 7'0100001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub22_internal_op[6:0] 7'0000001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub22_internal_op[6:0] 7'0100101 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub22_internal_op[6:0] 7'0100101 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub22_internal_op[6:0] 7'0100110 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub22_internal_op[6:0] 7'0100110 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub22_internal_op[6:0] 7'0100110 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub22_internal_op[6:0] 7'0100110 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub22_internal_op[6:0] 7'0100110 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub22_internal_op[6:0] 7'0100110 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub22_internal_op[6:0] 7'0000001 + case + assign $1\dec31_dec_sub22_internal_op[6:0] 7'0000000 + end + sync always + update \dec31_dec_sub22_internal_op $0\dec31_dec_sub22_internal_op[6:0] + end + attribute \src "issuer_ls180.v:93102.3-93156.6" + process $proc$issuer_ls180.v:93102$3833 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub22_rsrv[0:0] $1\dec31_dec_sub22_rsrv[0:0] + attribute \src "issuer_ls180.v:93103.5-93103.29" + switch \initial + attribute \src "issuer_ls180.v:93103.9-93103.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub22_rsrv[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub22_rsrv[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub22_rsrv[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub22_rsrv[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub22_rsrv[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub22_rsrv[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub22_rsrv[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub22_rsrv[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub22_rsrv[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub22_rsrv[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub22_rsrv[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub22_rsrv[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub22_rsrv[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub22_rsrv[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub22_rsrv[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub22_rsrv[0:0] 1'0 + case + assign $1\dec31_dec_sub22_rsrv[0:0] 1'0 + end + sync always + update \dec31_dec_sub22_rsrv $0\dec31_dec_sub22_rsrv[0:0] + end + attribute \src "issuer_ls180.v:93157.3-93211.6" + process $proc$issuer_ls180.v:93157$3834 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub22_is_32b[0:0] $1\dec31_dec_sub22_is_32b[0:0] + attribute \src "issuer_ls180.v:93158.5-93158.29" + switch \initial + attribute \src "issuer_ls180.v:93158.9-93158.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub22_is_32b[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub22_is_32b[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub22_is_32b[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub22_is_32b[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub22_is_32b[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub22_is_32b[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub22_is_32b[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub22_is_32b[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub22_is_32b[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub22_is_32b[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub22_is_32b[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub22_is_32b[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub22_is_32b[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub22_is_32b[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub22_is_32b[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub22_is_32b[0:0] 1'0 + case + assign $1\dec31_dec_sub22_is_32b[0:0] 1'0 + end + sync always + update \dec31_dec_sub22_is_32b $0\dec31_dec_sub22_is_32b[0:0] + end + attribute \src "issuer_ls180.v:93212.3-93266.6" + process $proc$issuer_ls180.v:93212$3835 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub22_sgn[0:0] $1\dec31_dec_sub22_sgn[0:0] + attribute \src "issuer_ls180.v:93213.5-93213.29" + switch \initial + attribute \src "issuer_ls180.v:93213.9-93213.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub22_sgn[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub22_sgn[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub22_sgn[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub22_sgn[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub22_sgn[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub22_sgn[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub22_sgn[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub22_sgn[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub22_sgn[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub22_sgn[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub22_sgn[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub22_sgn[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub22_sgn[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub22_sgn[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub22_sgn[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub22_sgn[0:0] 1'0 + case + assign $1\dec31_dec_sub22_sgn[0:0] 1'0 + end + sync always + update \dec31_dec_sub22_sgn $0\dec31_dec_sub22_sgn[0:0] + end + attribute \src "issuer_ls180.v:93267.3-93321.6" + process $proc$issuer_ls180.v:93267$3836 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub22_lk[0:0] $1\dec31_dec_sub22_lk[0:0] + attribute \src "issuer_ls180.v:93268.5-93268.29" + switch \initial + attribute \src "issuer_ls180.v:93268.9-93268.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub22_lk[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub22_lk[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub22_lk[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub22_lk[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub22_lk[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub22_lk[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub22_lk[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub22_lk[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub22_lk[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub22_lk[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub22_lk[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub22_lk[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub22_lk[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub22_lk[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub22_lk[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub22_lk[0:0] 1'0 + case + assign $1\dec31_dec_sub22_lk[0:0] 1'0 + end + sync always + update \dec31_dec_sub22_lk $0\dec31_dec_sub22_lk[0:0] + end + attribute \src "issuer_ls180.v:93322.3-93376.6" + process $proc$issuer_ls180.v:93322$3837 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub22_sgl_pipe[0:0] $1\dec31_dec_sub22_sgl_pipe[0:0] + attribute \src "issuer_ls180.v:93323.5-93323.29" + switch \initial + attribute \src "issuer_ls180.v:93323.9-93323.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub22_sgl_pipe[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub22_sgl_pipe[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub22_sgl_pipe[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub22_sgl_pipe[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub22_sgl_pipe[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub22_sgl_pipe[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub22_sgl_pipe[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub22_sgl_pipe[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub22_sgl_pipe[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub22_sgl_pipe[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub22_sgl_pipe[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub22_sgl_pipe[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub22_sgl_pipe[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub22_sgl_pipe[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub22_sgl_pipe[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub22_sgl_pipe[0:0] 1'1 + case + assign $1\dec31_dec_sub22_sgl_pipe[0:0] 1'0 + end + sync always + update \dec31_dec_sub22_sgl_pipe $0\dec31_dec_sub22_sgl_pipe[0:0] + end + attribute \src "issuer_ls180.v:93377.3-93431.6" + process $proc$issuer_ls180.v:93377$3838 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub22_form[4:0] $1\dec31_dec_sub22_form[4:0] + attribute \src "issuer_ls180.v:93378.5-93378.29" + switch \initial + attribute \src "issuer_ls180.v:93378.9-93378.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub22_form[4:0] 5'01000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub22_form[4:0] 5'01000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub22_form[4:0] 5'01000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub22_form[4:0] 5'01000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub22_form[4:0] 5'01000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub22_form[4:0] 5'01000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub22_form[4:0] 5'01000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub22_form[4:0] 5'01000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub22_form[4:0] 5'01000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub22_form[4:0] 5'01000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub22_form[4:0] 5'01000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub22_form[4:0] 5'01000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub22_form[4:0] 5'01000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub22_form[4:0] 5'01000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub22_form[4:0] 5'01000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub22_form[4:0] 5'01000 + case + assign $1\dec31_dec_sub22_form[4:0] 5'00000 + end + sync always + update \dec31_dec_sub22_form $0\dec31_dec_sub22_form[4:0] + end + attribute \src "issuer_ls180.v:93432.3-93486.6" + process $proc$issuer_ls180.v:93432$3839 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub22_in1_sel[2:0] $1\dec31_dec_sub22_in1_sel[2:0] + attribute \src "issuer_ls180.v:93433.5-93433.29" + switch \initial + attribute \src "issuer_ls180.v:93433.9-93433.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub22_in1_sel[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub22_in1_sel[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub22_in1_sel[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub22_in1_sel[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub22_in1_sel[2:0] 3'010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub22_in1_sel[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub22_in1_sel[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub22_in1_sel[2:0] 3'010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub22_in1_sel[2:0] 3'010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub22_in1_sel[2:0] 3'010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub22_in1_sel[2:0] 3'010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub22_in1_sel[2:0] 3'010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub22_in1_sel[2:0] 3'010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub22_in1_sel[2:0] 3'010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub22_in1_sel[2:0] 3'010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub22_in1_sel[2:0] 3'000 + case + assign $1\dec31_dec_sub22_in1_sel[2:0] 3'000 + end + sync always + update \dec31_dec_sub22_in1_sel $0\dec31_dec_sub22_in1_sel[2:0] + end + attribute \src "issuer_ls180.v:93487.3-93541.6" + process $proc$issuer_ls180.v:93487$3840 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub22_in2_sel[3:0] $1\dec31_dec_sub22_in2_sel[3:0] + attribute \src "issuer_ls180.v:93488.5-93488.29" + switch \initial + attribute \src "issuer_ls180.v:93488.9-93488.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub22_in2_sel[3:0] 4'0000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub22_in2_sel[3:0] 4'0000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub22_in2_sel[3:0] 4'0000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub22_in2_sel[3:0] 4'0000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub22_in2_sel[3:0] 4'0001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub22_in2_sel[3:0] 4'0000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub22_in2_sel[3:0] 4'0000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub22_in2_sel[3:0] 4'0001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub22_in2_sel[3:0] 4'0001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub22_in2_sel[3:0] 4'0001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub22_in2_sel[3:0] 4'0001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub22_in2_sel[3:0] 4'0001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub22_in2_sel[3:0] 4'0001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub22_in2_sel[3:0] 4'0001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub22_in2_sel[3:0] 4'0001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub22_in2_sel[3:0] 4'0000 + case + assign $1\dec31_dec_sub22_in2_sel[3:0] 4'0000 + end + sync always + update \dec31_dec_sub22_in2_sel $0\dec31_dec_sub22_in2_sel[3:0] + end + attribute \src "issuer_ls180.v:93542.3-93596.6" + process $proc$issuer_ls180.v:93542$3841 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub22_in3_sel[1:0] $1\dec31_dec_sub22_in3_sel[1:0] + attribute \src "issuer_ls180.v:93543.5-93543.29" + switch \initial + attribute \src "issuer_ls180.v:93543.9-93543.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub22_in3_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub22_in3_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub22_in3_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub22_in3_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub22_in3_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub22_in3_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub22_in3_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub22_in3_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub22_in3_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub22_in3_sel[1:0] 2'01 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub22_in3_sel[1:0] 2'01 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub22_in3_sel[1:0] 2'01 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub22_in3_sel[1:0] 2'01 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub22_in3_sel[1:0] 2'01 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub22_in3_sel[1:0] 2'01 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub22_in3_sel[1:0] 2'00 + case + assign $1\dec31_dec_sub22_in3_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub22_in3_sel $0\dec31_dec_sub22_in3_sel[1:0] + end + attribute \src "issuer_ls180.v:93597.3-93651.6" + process $proc$issuer_ls180.v:93597$3842 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub22_out_sel[1:0] $1\dec31_dec_sub22_out_sel[1:0] + attribute \src "issuer_ls180.v:93598.5-93598.29" + switch \initial + attribute \src "issuer_ls180.v:93598.9-93598.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub22_out_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub22_out_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub22_out_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub22_out_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub22_out_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub22_out_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub22_out_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub22_out_sel[1:0] 2'01 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub22_out_sel[1:0] 2'01 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub22_out_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub22_out_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub22_out_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub22_out_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub22_out_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub22_out_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub22_out_sel[1:0] 2'00 + case + assign $1\dec31_dec_sub22_out_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub22_out_sel $0\dec31_dec_sub22_out_sel[1:0] + end + attribute \src "issuer_ls180.v:93652.3-93706.6" + process $proc$issuer_ls180.v:93652$3843 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub22_cr_in[2:0] $1\dec31_dec_sub22_cr_in[2:0] + attribute \src "issuer_ls180.v:93653.5-93653.29" + switch \initial + attribute \src "issuer_ls180.v:93653.9-93653.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub22_cr_in[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub22_cr_in[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub22_cr_in[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub22_cr_in[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub22_cr_in[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub22_cr_in[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub22_cr_in[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub22_cr_in[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub22_cr_in[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub22_cr_in[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub22_cr_in[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub22_cr_in[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub22_cr_in[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub22_cr_in[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub22_cr_in[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub22_cr_in[2:0] 3'000 + case + assign $1\dec31_dec_sub22_cr_in[2:0] 3'000 + end + sync always + update \dec31_dec_sub22_cr_in $0\dec31_dec_sub22_cr_in[2:0] + end + attribute \src "issuer_ls180.v:93707.3-93761.6" + process $proc$issuer_ls180.v:93707$3844 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub22_cr_out[2:0] $1\dec31_dec_sub22_cr_out[2:0] + attribute \src "issuer_ls180.v:93708.5-93708.29" + switch \initial + attribute \src "issuer_ls180.v:93708.9-93708.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub22_cr_out[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub22_cr_out[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub22_cr_out[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub22_cr_out[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub22_cr_out[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub22_cr_out[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub22_cr_out[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub22_cr_out[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub22_cr_out[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10101 + assign { } { } + assign $1\dec31_dec_sub22_cr_out[2:0] 3'001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub22_cr_out[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub22_cr_out[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub22_cr_out[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub22_cr_out[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub22_cr_out[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub22_cr_out[2:0] 3'000 + case + assign $1\dec31_dec_sub22_cr_out[2:0] 3'000 + end + sync always + update \dec31_dec_sub22_cr_out $0\dec31_dec_sub22_cr_out[2:0] + end + connect \opcode_switch \opcode_in [10:6] +end +attribute \src "issuer_ls180.v:93767.1-95202.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.dec2.dec.dec31.dec31_dec_sub23" +attribute \generator "nMigen" +module \dec31_dec_sub23 + attribute \src "issuer_ls180.v:94270.3-94318.6" + wire width 8 $0\dec31_dec_sub23_asmcode[7:0] + attribute \src "issuer_ls180.v:94466.3-94514.6" + wire $0\dec31_dec_sub23_br[0:0] + attribute \src "issuer_ls180.v:95103.3-95151.6" + wire width 3 $0\dec31_dec_sub23_cr_in[2:0] + attribute \src "issuer_ls180.v:95152.3-95200.6" + wire width 3 $0\dec31_dec_sub23_cr_out[2:0] + attribute \src "issuer_ls180.v:94221.3-94269.6" + wire width 2 $0\dec31_dec_sub23_cry_in[1:0] + attribute \src "issuer_ls180.v:94417.3-94465.6" + wire $0\dec31_dec_sub23_cry_out[0:0] + attribute \src "issuer_ls180.v:94858.3-94906.6" + wire width 5 $0\dec31_dec_sub23_form[4:0] + attribute \src "issuer_ls180.v:94025.3-94073.6" + wire width 12 $0\dec31_dec_sub23_function_unit[11:0] + attribute \src "issuer_ls180.v:94907.3-94955.6" + wire width 3 $0\dec31_dec_sub23_in1_sel[2:0] + attribute \src "issuer_ls180.v:94956.3-95004.6" + wire width 4 $0\dec31_dec_sub23_in2_sel[3:0] + attribute \src "issuer_ls180.v:95005.3-95053.6" + wire width 2 $0\dec31_dec_sub23_in3_sel[1:0] + attribute \src "issuer_ls180.v:94564.3-94612.6" + wire width 7 $0\dec31_dec_sub23_internal_op[6:0] + attribute \src "issuer_ls180.v:94319.3-94367.6" + wire $0\dec31_dec_sub23_inv_a[0:0] + attribute \src "issuer_ls180.v:94368.3-94416.6" + wire $0\dec31_dec_sub23_inv_out[0:0] + attribute \src "issuer_ls180.v:94662.3-94710.6" + wire $0\dec31_dec_sub23_is_32b[0:0] + attribute \src "issuer_ls180.v:94074.3-94122.6" + wire width 4 $0\dec31_dec_sub23_ldst_len[3:0] + attribute \src "issuer_ls180.v:94760.3-94808.6" + wire $0\dec31_dec_sub23_lk[0:0] + attribute \src "issuer_ls180.v:95054.3-95102.6" + wire width 2 $0\dec31_dec_sub23_out_sel[1:0] + attribute \src "issuer_ls180.v:94172.3-94220.6" + wire width 2 $0\dec31_dec_sub23_rc_sel[1:0] + attribute \src "issuer_ls180.v:94613.3-94661.6" + wire $0\dec31_dec_sub23_rsrv[0:0] + attribute \src "issuer_ls180.v:94809.3-94857.6" + wire $0\dec31_dec_sub23_sgl_pipe[0:0] + attribute \src "issuer_ls180.v:94711.3-94759.6" + wire $0\dec31_dec_sub23_sgn[0:0] + attribute \src "issuer_ls180.v:94515.3-94563.6" + wire $0\dec31_dec_sub23_sgn_ext[0:0] + attribute \src "issuer_ls180.v:94123.3-94171.6" + wire width 2 $0\dec31_dec_sub23_upd[1:0] + attribute \src "issuer_ls180.v:93768.7-93768.20" + wire $0\initial[0:0] + attribute \src "issuer_ls180.v:94270.3-94318.6" + wire width 8 $1\dec31_dec_sub23_asmcode[7:0] + attribute \src "issuer_ls180.v:94466.3-94514.6" + wire $1\dec31_dec_sub23_br[0:0] + attribute \src "issuer_ls180.v:95103.3-95151.6" + wire width 3 $1\dec31_dec_sub23_cr_in[2:0] + attribute \src "issuer_ls180.v:95152.3-95200.6" + wire width 3 $1\dec31_dec_sub23_cr_out[2:0] + attribute \src "issuer_ls180.v:94221.3-94269.6" + wire width 2 $1\dec31_dec_sub23_cry_in[1:0] + attribute \src "issuer_ls180.v:94417.3-94465.6" + wire $1\dec31_dec_sub23_cry_out[0:0] + attribute \src "issuer_ls180.v:94858.3-94906.6" + wire width 5 $1\dec31_dec_sub23_form[4:0] + attribute \src "issuer_ls180.v:94025.3-94073.6" + wire width 12 $1\dec31_dec_sub23_function_unit[11:0] + attribute \src "issuer_ls180.v:94907.3-94955.6" + wire width 3 $1\dec31_dec_sub23_in1_sel[2:0] + attribute \src "issuer_ls180.v:94956.3-95004.6" + wire width 4 $1\dec31_dec_sub23_in2_sel[3:0] + attribute \src "issuer_ls180.v:95005.3-95053.6" + wire width 2 $1\dec31_dec_sub23_in3_sel[1:0] + attribute \src "issuer_ls180.v:94564.3-94612.6" + wire width 7 $1\dec31_dec_sub23_internal_op[6:0] + attribute \src "issuer_ls180.v:94319.3-94367.6" + wire $1\dec31_dec_sub23_inv_a[0:0] + attribute \src "issuer_ls180.v:94368.3-94416.6" + wire $1\dec31_dec_sub23_inv_out[0:0] + attribute \src "issuer_ls180.v:94662.3-94710.6" + wire $1\dec31_dec_sub23_is_32b[0:0] + attribute \src "issuer_ls180.v:94074.3-94122.6" + wire width 4 $1\dec31_dec_sub23_ldst_len[3:0] + attribute \src "issuer_ls180.v:94760.3-94808.6" + wire $1\dec31_dec_sub23_lk[0:0] + attribute \src "issuer_ls180.v:95054.3-95102.6" + wire width 2 $1\dec31_dec_sub23_out_sel[1:0] + attribute \src "issuer_ls180.v:94172.3-94220.6" + wire width 2 $1\dec31_dec_sub23_rc_sel[1:0] + attribute \src "issuer_ls180.v:94613.3-94661.6" + wire $1\dec31_dec_sub23_rsrv[0:0] + attribute \src "issuer_ls180.v:94809.3-94857.6" + wire $1\dec31_dec_sub23_sgl_pipe[0:0] + attribute \src "issuer_ls180.v:94711.3-94759.6" + wire $1\dec31_dec_sub23_sgn[0:0] + attribute \src "issuer_ls180.v:94515.3-94563.6" + wire $1\dec31_dec_sub23_sgn_ext[0:0] + attribute \src "issuer_ls180.v:94123.3-94171.6" + wire width 2 $1\dec31_dec_sub23_upd[1:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 8 output 4 \dec31_dec_sub23_asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 18 \dec31_dec_sub23_br + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 9 \dec31_dec_sub23_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 10 \dec31_dec_sub23_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 14 \dec31_dec_sub23_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 17 \dec31_dec_sub23_cry_out + attribute \enum_base_type "Form" + attribute \enum_value_00000 "NONE" + attribute \enum_value_00001 "I" + attribute \enum_value_00010 "B" + attribute \enum_value_00011 "SC" + attribute \enum_value_00100 "D" + attribute \enum_value_00101 "DS" + attribute \enum_value_00110 "DQ" + attribute \enum_value_00111 "DX" + attribute \enum_value_01000 "X" + attribute \enum_value_01001 "XL" + attribute \enum_value_01010 "XFX" + attribute \enum_value_01011 "XFL" + attribute \enum_value_01100 "XX1" + attribute \enum_value_01101 "XX2" + attribute \enum_value_01110 "XX3" + attribute \enum_value_01111 "XX4" + attribute \enum_value_10000 "XS" + attribute \enum_value_10001 "XO" + attribute \enum_value_10010 "A" + attribute \enum_value_10011 "M" + attribute \enum_value_10100 "MD" + attribute \enum_value_10101 "MDS" + attribute \enum_value_10110 "VA" + attribute \enum_value_10111 "VC" + attribute \enum_value_11000 "VX" + attribute \enum_value_11001 "EVX" + attribute \enum_value_11010 "EVS" + attribute \enum_value_11011 "Z22" + attribute \enum_value_11100 "Z23" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 5 output 3 \dec31_dec_sub23_form + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 12 output 1 \dec31_dec_sub23_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 5 \dec31_dec_sub23_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 output 6 \dec31_dec_sub23_in2_sel + attribute \enum_base_type "In3Sel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RS" + attribute \enum_value_10 "RB" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 7 \dec31_dec_sub23_in3_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 7 output 2 \dec31_dec_sub23_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 15 \dec31_dec_sub23_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 16 \dec31_dec_sub23_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 21 \dec31_dec_sub23_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 output 11 \dec31_dec_sub23_ldst_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 23 \dec31_dec_sub23_lk + attribute \enum_base_type "OutSel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RT" + attribute \enum_value_10 "RA" + attribute \enum_value_11 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 8 \dec31_dec_sub23_out_sel + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 13 \dec31_dec_sub23_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 20 \dec31_dec_sub23_rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 24 \dec31_dec_sub23_sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 22 \dec31_dec_sub23_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 19 \dec31_dec_sub23_sgn_ext + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 12 \dec31_dec_sub23_upd + attribute \src "issuer_ls180.v:93768.7-93768.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + wire width 32 input 25 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:320" + wire width 5 \opcode_switch + attribute \src "issuer_ls180.v:93768.7-93768.20" + process $proc$issuer_ls180.v:93768$3870 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "issuer_ls180.v:94025.3-94073.6" + process $proc$issuer_ls180.v:94025$3846 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub23_function_unit[11:0] $1\dec31_dec_sub23_function_unit[11:0] + attribute \src "issuer_ls180.v:94026.5-94026.29" + switch \initial + attribute \src "issuer_ls180.v:94026.9-94026.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub23_function_unit[11:0] 12'000000000100 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub23_function_unit[11:0] 12'000000000100 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub23_function_unit[11:0] 12'000000000100 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub23_function_unit[11:0] 12'000000000100 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub23_function_unit[11:0] 12'000000000100 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub23_function_unit[11:0] 12'000000000100 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub23_function_unit[11:0] 12'000000000100 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub23_function_unit[11:0] 12'000000000100 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub23_function_unit[11:0] 12'000000000100 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub23_function_unit[11:0] 12'000000000100 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub23_function_unit[11:0] 12'000000000100 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub23_function_unit[11:0] 12'000000000100 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub23_function_unit[11:0] 12'000000000100 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub23_function_unit[11:0] 12'000000000100 + case + assign $1\dec31_dec_sub23_function_unit[11:0] 12'000000000000 + end + sync always + update \dec31_dec_sub23_function_unit $0\dec31_dec_sub23_function_unit[11:0] + end + attribute \src "issuer_ls180.v:94074.3-94122.6" + process $proc$issuer_ls180.v:94074$3847 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub23_ldst_len[3:0] $1\dec31_dec_sub23_ldst_len[3:0] + attribute \src "issuer_ls180.v:94075.5-94075.29" + switch \initial + attribute \src "issuer_ls180.v:94075.9-94075.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub23_ldst_len[3:0] 4'0001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub23_ldst_len[3:0] 4'0001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub23_ldst_len[3:0] 4'0010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub23_ldst_len[3:0] 4'0010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub23_ldst_len[3:0] 4'0010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub23_ldst_len[3:0] 4'0010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub23_ldst_len[3:0] 4'0100 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub23_ldst_len[3:0] 4'0100 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub23_ldst_len[3:0] 4'0001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub23_ldst_len[3:0] 4'0001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub23_ldst_len[3:0] 4'0010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub23_ldst_len[3:0] 4'0010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub23_ldst_len[3:0] 4'0100 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub23_ldst_len[3:0] 4'0100 + case + assign $1\dec31_dec_sub23_ldst_len[3:0] 4'0000 + end + sync always + update \dec31_dec_sub23_ldst_len $0\dec31_dec_sub23_ldst_len[3:0] + end + attribute \src "issuer_ls180.v:94123.3-94171.6" + process $proc$issuer_ls180.v:94123$3848 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub23_upd[1:0] $1\dec31_dec_sub23_upd[1:0] + attribute \src "issuer_ls180.v:94124.5-94124.29" + switch \initial + attribute \src "issuer_ls180.v:94124.9-94124.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub23_upd[1:0] 2'01 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub23_upd[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub23_upd[1:0] 2'01 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub23_upd[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub23_upd[1:0] 2'01 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub23_upd[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub23_upd[1:0] 2'01 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub23_upd[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub23_upd[1:0] 2'01 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub23_upd[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub23_upd[1:0] 2'01 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub23_upd[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub23_upd[1:0] 2'01 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub23_upd[1:0] 2'00 + case + assign $1\dec31_dec_sub23_upd[1:0] 2'00 + end + sync always + update \dec31_dec_sub23_upd $0\dec31_dec_sub23_upd[1:0] + end + attribute \src "issuer_ls180.v:94172.3-94220.6" + process $proc$issuer_ls180.v:94172$3849 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub23_rc_sel[1:0] $1\dec31_dec_sub23_rc_sel[1:0] + attribute \src "issuer_ls180.v:94173.5-94173.29" + switch \initial + attribute \src "issuer_ls180.v:94173.9-94173.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub23_rc_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub23_rc_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub23_rc_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub23_rc_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub23_rc_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub23_rc_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub23_rc_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub23_rc_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub23_rc_sel[1:0] 2'10 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub23_rc_sel[1:0] 2'10 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub23_rc_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub23_rc_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub23_rc_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub23_rc_sel[1:0] 2'00 + case + assign $1\dec31_dec_sub23_rc_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub23_rc_sel $0\dec31_dec_sub23_rc_sel[1:0] + end + attribute \src "issuer_ls180.v:94221.3-94269.6" + process $proc$issuer_ls180.v:94221$3850 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub23_cry_in[1:0] $1\dec31_dec_sub23_cry_in[1:0] + attribute \src "issuer_ls180.v:94222.5-94222.29" + switch \initial + attribute \src "issuer_ls180.v:94222.9-94222.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub23_cry_in[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub23_cry_in[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub23_cry_in[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub23_cry_in[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub23_cry_in[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub23_cry_in[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub23_cry_in[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub23_cry_in[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub23_cry_in[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub23_cry_in[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub23_cry_in[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub23_cry_in[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub23_cry_in[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub23_cry_in[1:0] 2'00 + case + assign $1\dec31_dec_sub23_cry_in[1:0] 2'00 + end + sync always + update \dec31_dec_sub23_cry_in $0\dec31_dec_sub23_cry_in[1:0] + end + attribute \src "issuer_ls180.v:94270.3-94318.6" + process $proc$issuer_ls180.v:94270$3851 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub23_asmcode[7:0] $1\dec31_dec_sub23_asmcode[7:0] + attribute \src "issuer_ls180.v:94271.5-94271.29" + switch \initial + attribute \src "issuer_ls180.v:94271.9-94271.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub23_asmcode[7:0] 8'01010000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub23_asmcode[7:0] 8'01010001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub23_asmcode[7:0] 8'01011011 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub23_asmcode[7:0] 8'01011100 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub23_asmcode[7:0] 8'01100000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub23_asmcode[7:0] 8'01100001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub23_asmcode[7:0] 8'01101010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub23_asmcode[7:0] 8'01101011 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub23_asmcode[7:0] 8'10101010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub23_asmcode[7:0] 8'10101011 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub23_asmcode[7:0] 8'10110110 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub23_asmcode[7:0] 8'10110111 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub23_asmcode[7:0] 8'10111100 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub23_asmcode[7:0] 8'10111101 + case + assign $1\dec31_dec_sub23_asmcode[7:0] 8'00000000 + end + sync always + update \dec31_dec_sub23_asmcode $0\dec31_dec_sub23_asmcode[7:0] + end + attribute \src "issuer_ls180.v:94319.3-94367.6" + process $proc$issuer_ls180.v:94319$3852 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub23_inv_a[0:0] $1\dec31_dec_sub23_inv_a[0:0] + attribute \src "issuer_ls180.v:94320.5-94320.29" + switch \initial + attribute \src "issuer_ls180.v:94320.9-94320.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub23_inv_a[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub23_inv_a[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub23_inv_a[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub23_inv_a[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub23_inv_a[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub23_inv_a[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub23_inv_a[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub23_inv_a[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub23_inv_a[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub23_inv_a[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub23_inv_a[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub23_inv_a[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub23_inv_a[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub23_inv_a[0:0] 1'0 + case + assign $1\dec31_dec_sub23_inv_a[0:0] 1'0 + end + sync always + update \dec31_dec_sub23_inv_a $0\dec31_dec_sub23_inv_a[0:0] + end + attribute \src "issuer_ls180.v:94368.3-94416.6" + process $proc$issuer_ls180.v:94368$3853 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub23_inv_out[0:0] $1\dec31_dec_sub23_inv_out[0:0] + attribute \src "issuer_ls180.v:94369.5-94369.29" + switch \initial + attribute \src "issuer_ls180.v:94369.9-94369.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub23_inv_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub23_inv_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub23_inv_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub23_inv_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub23_inv_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub23_inv_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub23_inv_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub23_inv_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub23_inv_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub23_inv_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub23_inv_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub23_inv_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub23_inv_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub23_inv_out[0:0] 1'0 + case + assign $1\dec31_dec_sub23_inv_out[0:0] 1'0 + end + sync always + update \dec31_dec_sub23_inv_out $0\dec31_dec_sub23_inv_out[0:0] + end + attribute \src "issuer_ls180.v:94417.3-94465.6" + process $proc$issuer_ls180.v:94417$3854 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub23_cry_out[0:0] $1\dec31_dec_sub23_cry_out[0:0] + attribute \src "issuer_ls180.v:94418.5-94418.29" + switch \initial + attribute \src "issuer_ls180.v:94418.9-94418.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub23_cry_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub23_cry_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub23_cry_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub23_cry_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub23_cry_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub23_cry_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub23_cry_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub23_cry_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub23_cry_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub23_cry_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub23_cry_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub23_cry_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub23_cry_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub23_cry_out[0:0] 1'0 + case + assign $1\dec31_dec_sub23_cry_out[0:0] 1'0 + end + sync always + update \dec31_dec_sub23_cry_out $0\dec31_dec_sub23_cry_out[0:0] + end + attribute \src "issuer_ls180.v:94466.3-94514.6" + process $proc$issuer_ls180.v:94466$3855 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub23_br[0:0] $1\dec31_dec_sub23_br[0:0] + attribute \src "issuer_ls180.v:94467.5-94467.29" + switch \initial + attribute \src "issuer_ls180.v:94467.9-94467.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub23_br[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub23_br[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub23_br[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub23_br[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub23_br[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub23_br[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub23_br[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub23_br[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub23_br[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub23_br[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub23_br[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub23_br[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub23_br[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub23_br[0:0] 1'0 + case + assign $1\dec31_dec_sub23_br[0:0] 1'0 + end + sync always + update \dec31_dec_sub23_br $0\dec31_dec_sub23_br[0:0] + end + attribute \src "issuer_ls180.v:94515.3-94563.6" + process $proc$issuer_ls180.v:94515$3856 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub23_sgn_ext[0:0] $1\dec31_dec_sub23_sgn_ext[0:0] + attribute \src "issuer_ls180.v:94516.5-94516.29" + switch \initial + attribute \src "issuer_ls180.v:94516.9-94516.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub23_sgn_ext[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub23_sgn_ext[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub23_sgn_ext[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub23_sgn_ext[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub23_sgn_ext[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub23_sgn_ext[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub23_sgn_ext[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub23_sgn_ext[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub23_sgn_ext[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub23_sgn_ext[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub23_sgn_ext[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub23_sgn_ext[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub23_sgn_ext[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub23_sgn_ext[0:0] 1'0 + case + assign $1\dec31_dec_sub23_sgn_ext[0:0] 1'0 + end + sync always + update \dec31_dec_sub23_sgn_ext $0\dec31_dec_sub23_sgn_ext[0:0] + end + attribute \src "issuer_ls180.v:94564.3-94612.6" + process $proc$issuer_ls180.v:94564$3857 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub23_internal_op[6:0] $1\dec31_dec_sub23_internal_op[6:0] + attribute \src "issuer_ls180.v:94565.5-94565.29" + switch \initial + attribute \src "issuer_ls180.v:94565.9-94565.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub23_internal_op[6:0] 7'0100101 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub23_internal_op[6:0] 7'0100101 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub23_internal_op[6:0] 7'0100101 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub23_internal_op[6:0] 7'0100101 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub23_internal_op[6:0] 7'0100101 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub23_internal_op[6:0] 7'0100101 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub23_internal_op[6:0] 7'0100101 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub23_internal_op[6:0] 7'0100101 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub23_internal_op[6:0] 7'0100110 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub23_internal_op[6:0] 7'0100110 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub23_internal_op[6:0] 7'0100110 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub23_internal_op[6:0] 7'0100110 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub23_internal_op[6:0] 7'0100110 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub23_internal_op[6:0] 7'0100110 + case + assign $1\dec31_dec_sub23_internal_op[6:0] 7'0000000 + end + sync always + update \dec31_dec_sub23_internal_op $0\dec31_dec_sub23_internal_op[6:0] + end + attribute \src "issuer_ls180.v:94613.3-94661.6" + process $proc$issuer_ls180.v:94613$3858 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub23_rsrv[0:0] $1\dec31_dec_sub23_rsrv[0:0] + attribute \src "issuer_ls180.v:94614.5-94614.29" + switch \initial + attribute \src "issuer_ls180.v:94614.9-94614.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub23_rsrv[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub23_rsrv[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub23_rsrv[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub23_rsrv[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub23_rsrv[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub23_rsrv[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub23_rsrv[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub23_rsrv[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub23_rsrv[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub23_rsrv[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub23_rsrv[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub23_rsrv[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub23_rsrv[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub23_rsrv[0:0] 1'0 + case + assign $1\dec31_dec_sub23_rsrv[0:0] 1'0 + end + sync always + update \dec31_dec_sub23_rsrv $0\dec31_dec_sub23_rsrv[0:0] + end + attribute \src "issuer_ls180.v:94662.3-94710.6" + process $proc$issuer_ls180.v:94662$3859 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub23_is_32b[0:0] $1\dec31_dec_sub23_is_32b[0:0] + attribute \src "issuer_ls180.v:94663.5-94663.29" + switch \initial + attribute \src "issuer_ls180.v:94663.9-94663.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub23_is_32b[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub23_is_32b[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub23_is_32b[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub23_is_32b[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub23_is_32b[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub23_is_32b[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub23_is_32b[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub23_is_32b[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub23_is_32b[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub23_is_32b[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub23_is_32b[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub23_is_32b[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub23_is_32b[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub23_is_32b[0:0] 1'0 + case + assign $1\dec31_dec_sub23_is_32b[0:0] 1'0 + end + sync always + update \dec31_dec_sub23_is_32b $0\dec31_dec_sub23_is_32b[0:0] + end + attribute \src "issuer_ls180.v:94711.3-94759.6" + process $proc$issuer_ls180.v:94711$3860 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub23_sgn[0:0] $1\dec31_dec_sub23_sgn[0:0] + attribute \src "issuer_ls180.v:94712.5-94712.29" + switch \initial + attribute \src "issuer_ls180.v:94712.9-94712.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub23_sgn[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub23_sgn[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub23_sgn[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub23_sgn[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub23_sgn[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub23_sgn[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub23_sgn[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub23_sgn[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub23_sgn[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub23_sgn[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub23_sgn[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub23_sgn[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub23_sgn[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub23_sgn[0:0] 1'0 + case + assign $1\dec31_dec_sub23_sgn[0:0] 1'0 + end + sync always + update \dec31_dec_sub23_sgn $0\dec31_dec_sub23_sgn[0:0] + end + attribute \src "issuer_ls180.v:94760.3-94808.6" + process $proc$issuer_ls180.v:94760$3861 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub23_lk[0:0] $1\dec31_dec_sub23_lk[0:0] + attribute \src "issuer_ls180.v:94761.5-94761.29" + switch \initial + attribute \src "issuer_ls180.v:94761.9-94761.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub23_lk[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub23_lk[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub23_lk[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub23_lk[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub23_lk[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub23_lk[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub23_lk[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub23_lk[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub23_lk[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub23_lk[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub23_lk[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub23_lk[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub23_lk[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub23_lk[0:0] 1'0 + case + assign $1\dec31_dec_sub23_lk[0:0] 1'0 + end + sync always + update \dec31_dec_sub23_lk $0\dec31_dec_sub23_lk[0:0] + end + attribute \src "issuer_ls180.v:94809.3-94857.6" + process $proc$issuer_ls180.v:94809$3862 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub23_sgl_pipe[0:0] $1\dec31_dec_sub23_sgl_pipe[0:0] + attribute \src "issuer_ls180.v:94810.5-94810.29" + switch \initial + attribute \src "issuer_ls180.v:94810.9-94810.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub23_sgl_pipe[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub23_sgl_pipe[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub23_sgl_pipe[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub23_sgl_pipe[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub23_sgl_pipe[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub23_sgl_pipe[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub23_sgl_pipe[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub23_sgl_pipe[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub23_sgl_pipe[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub23_sgl_pipe[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub23_sgl_pipe[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub23_sgl_pipe[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub23_sgl_pipe[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub23_sgl_pipe[0:0] 1'1 + case + assign $1\dec31_dec_sub23_sgl_pipe[0:0] 1'0 + end + sync always + update \dec31_dec_sub23_sgl_pipe $0\dec31_dec_sub23_sgl_pipe[0:0] + end + attribute \src "issuer_ls180.v:94858.3-94906.6" + process $proc$issuer_ls180.v:94858$3863 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub23_form[4:0] $1\dec31_dec_sub23_form[4:0] + attribute \src "issuer_ls180.v:94859.5-94859.29" + switch \initial + attribute \src "issuer_ls180.v:94859.9-94859.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub23_form[4:0] 5'01000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub23_form[4:0] 5'01000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub23_form[4:0] 5'01000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub23_form[4:0] 5'01000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub23_form[4:0] 5'01000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub23_form[4:0] 5'01000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub23_form[4:0] 5'01000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub23_form[4:0] 5'01000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub23_form[4:0] 5'01000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub23_form[4:0] 5'01000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub23_form[4:0] 5'01000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub23_form[4:0] 5'01000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub23_form[4:0] 5'01000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub23_form[4:0] 5'01000 + case + assign $1\dec31_dec_sub23_form[4:0] 5'00000 + end + sync always + update \dec31_dec_sub23_form $0\dec31_dec_sub23_form[4:0] + end + attribute \src "issuer_ls180.v:94907.3-94955.6" + process $proc$issuer_ls180.v:94907$3864 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub23_in1_sel[2:0] $1\dec31_dec_sub23_in1_sel[2:0] + attribute \src "issuer_ls180.v:94908.5-94908.29" + switch \initial + attribute \src "issuer_ls180.v:94908.9-94908.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub23_in1_sel[2:0] 3'010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub23_in1_sel[2:0] 3'010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub23_in1_sel[2:0] 3'010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub23_in1_sel[2:0] 3'010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub23_in1_sel[2:0] 3'010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub23_in1_sel[2:0] 3'010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub23_in1_sel[2:0] 3'010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub23_in1_sel[2:0] 3'010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub23_in1_sel[2:0] 3'010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub23_in1_sel[2:0] 3'010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub23_in1_sel[2:0] 3'010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub23_in1_sel[2:0] 3'010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub23_in1_sel[2:0] 3'010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub23_in1_sel[2:0] 3'010 + case + assign $1\dec31_dec_sub23_in1_sel[2:0] 3'000 + end + sync always + update \dec31_dec_sub23_in1_sel $0\dec31_dec_sub23_in1_sel[2:0] + end + attribute \src "issuer_ls180.v:94956.3-95004.6" + process $proc$issuer_ls180.v:94956$3865 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub23_in2_sel[3:0] $1\dec31_dec_sub23_in2_sel[3:0] + attribute \src "issuer_ls180.v:94957.5-94957.29" + switch \initial + attribute \src "issuer_ls180.v:94957.9-94957.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub23_in2_sel[3:0] 4'0001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub23_in2_sel[3:0] 4'0001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub23_in2_sel[3:0] 4'0001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub23_in2_sel[3:0] 4'0001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub23_in2_sel[3:0] 4'0001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub23_in2_sel[3:0] 4'0001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub23_in2_sel[3:0] 4'0001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub23_in2_sel[3:0] 4'0001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub23_in2_sel[3:0] 4'0001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub23_in2_sel[3:0] 4'0001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub23_in2_sel[3:0] 4'0001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub23_in2_sel[3:0] 4'0001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub23_in2_sel[3:0] 4'0001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub23_in2_sel[3:0] 4'0001 + case + assign $1\dec31_dec_sub23_in2_sel[3:0] 4'0000 + end + sync always + update \dec31_dec_sub23_in2_sel $0\dec31_dec_sub23_in2_sel[3:0] + end + attribute \src "issuer_ls180.v:95005.3-95053.6" + process $proc$issuer_ls180.v:95005$3866 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub23_in3_sel[1:0] $1\dec31_dec_sub23_in3_sel[1:0] + attribute \src "issuer_ls180.v:95006.5-95006.29" + switch \initial + attribute \src "issuer_ls180.v:95006.9-95006.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub23_in3_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub23_in3_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub23_in3_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub23_in3_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub23_in3_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub23_in3_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub23_in3_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub23_in3_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub23_in3_sel[1:0] 2'01 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub23_in3_sel[1:0] 2'01 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub23_in3_sel[1:0] 2'01 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub23_in3_sel[1:0] 2'01 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub23_in3_sel[1:0] 2'01 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub23_in3_sel[1:0] 2'01 + case + assign $1\dec31_dec_sub23_in3_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub23_in3_sel $0\dec31_dec_sub23_in3_sel[1:0] + end + attribute \src "issuer_ls180.v:95054.3-95102.6" + process $proc$issuer_ls180.v:95054$3867 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub23_out_sel[1:0] $1\dec31_dec_sub23_out_sel[1:0] + attribute \src "issuer_ls180.v:95055.5-95055.29" + switch \initial + attribute \src "issuer_ls180.v:95055.9-95055.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub23_out_sel[1:0] 2'01 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub23_out_sel[1:0] 2'01 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub23_out_sel[1:0] 2'01 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub23_out_sel[1:0] 2'01 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub23_out_sel[1:0] 2'01 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub23_out_sel[1:0] 2'01 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub23_out_sel[1:0] 2'01 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub23_out_sel[1:0] 2'01 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub23_out_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub23_out_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub23_out_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub23_out_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub23_out_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub23_out_sel[1:0] 2'00 + case + assign $1\dec31_dec_sub23_out_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub23_out_sel $0\dec31_dec_sub23_out_sel[1:0] + end + attribute \src "issuer_ls180.v:95103.3-95151.6" + process $proc$issuer_ls180.v:95103$3868 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub23_cr_in[2:0] $1\dec31_dec_sub23_cr_in[2:0] + attribute \src "issuer_ls180.v:95104.5-95104.29" + switch \initial + attribute \src "issuer_ls180.v:95104.9-95104.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub23_cr_in[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub23_cr_in[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub23_cr_in[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub23_cr_in[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub23_cr_in[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub23_cr_in[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub23_cr_in[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub23_cr_in[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub23_cr_in[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub23_cr_in[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub23_cr_in[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub23_cr_in[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub23_cr_in[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub23_cr_in[2:0] 3'000 + case + assign $1\dec31_dec_sub23_cr_in[2:0] 3'000 + end + sync always + update \dec31_dec_sub23_cr_in $0\dec31_dec_sub23_cr_in[2:0] + end + attribute \src "issuer_ls180.v:95152.3-95200.6" + process $proc$issuer_ls180.v:95152$3869 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub23_cr_out[2:0] $1\dec31_dec_sub23_cr_out[2:0] + attribute \src "issuer_ls180.v:95153.5-95153.29" + switch \initial + attribute \src "issuer_ls180.v:95153.9-95153.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub23_cr_out[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub23_cr_out[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub23_cr_out[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01010 + assign { } { } + assign $1\dec31_dec_sub23_cr_out[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub23_cr_out[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub23_cr_out[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub23_cr_out[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub23_cr_out[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub23_cr_out[2:0] 3'001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub23_cr_out[2:0] 3'001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub23_cr_out[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub23_cr_out[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub23_cr_out[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub23_cr_out[2:0] 3'000 + case + assign $1\dec31_dec_sub23_cr_out[2:0] 3'000 + end + sync always + update \dec31_dec_sub23_cr_out $0\dec31_dec_sub23_cr_out[2:0] + end + connect \opcode_switch \opcode_in [10:6] +end +attribute \src "issuer_ls180.v:95206.1-95921.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.dec2.dec.dec31.dec31_dec_sub24" +attribute \generator "nMigen" +module \dec31_dec_sub24 + attribute \src "issuer_ls180.v:95559.3-95577.6" + wire width 8 $0\dec31_dec_sub24_asmcode[7:0] + attribute \src "issuer_ls180.v:95635.3-95653.6" + wire $0\dec31_dec_sub24_br[0:0] + attribute \src "issuer_ls180.v:95882.3-95900.6" + wire width 3 $0\dec31_dec_sub24_cr_in[2:0] + attribute \src "issuer_ls180.v:95901.3-95919.6" + wire width 3 $0\dec31_dec_sub24_cr_out[2:0] + attribute \src "issuer_ls180.v:95540.3-95558.6" + wire width 2 $0\dec31_dec_sub24_cry_in[1:0] + attribute \src "issuer_ls180.v:95616.3-95634.6" + wire $0\dec31_dec_sub24_cry_out[0:0] + attribute \src "issuer_ls180.v:95787.3-95805.6" + wire width 5 $0\dec31_dec_sub24_form[4:0] + attribute \src "issuer_ls180.v:95464.3-95482.6" + wire width 12 $0\dec31_dec_sub24_function_unit[11:0] + attribute \src "issuer_ls180.v:95806.3-95824.6" + wire width 3 $0\dec31_dec_sub24_in1_sel[2:0] + attribute \src "issuer_ls180.v:95825.3-95843.6" + wire width 4 $0\dec31_dec_sub24_in2_sel[3:0] + attribute \src "issuer_ls180.v:95844.3-95862.6" + wire width 2 $0\dec31_dec_sub24_in3_sel[1:0] + attribute \src "issuer_ls180.v:95673.3-95691.6" + wire width 7 $0\dec31_dec_sub24_internal_op[6:0] + attribute \src "issuer_ls180.v:95578.3-95596.6" + wire $0\dec31_dec_sub24_inv_a[0:0] + attribute \src "issuer_ls180.v:95597.3-95615.6" + wire $0\dec31_dec_sub24_inv_out[0:0] + attribute \src "issuer_ls180.v:95711.3-95729.6" + wire $0\dec31_dec_sub24_is_32b[0:0] + attribute \src "issuer_ls180.v:95483.3-95501.6" + wire width 4 $0\dec31_dec_sub24_ldst_len[3:0] + attribute \src "issuer_ls180.v:95749.3-95767.6" + wire $0\dec31_dec_sub24_lk[0:0] + attribute \src "issuer_ls180.v:95863.3-95881.6" + wire width 2 $0\dec31_dec_sub24_out_sel[1:0] + attribute \src "issuer_ls180.v:95521.3-95539.6" + wire width 2 $0\dec31_dec_sub24_rc_sel[1:0] + attribute \src "issuer_ls180.v:95692.3-95710.6" + wire $0\dec31_dec_sub24_rsrv[0:0] + attribute \src "issuer_ls180.v:95768.3-95786.6" + wire $0\dec31_dec_sub24_sgl_pipe[0:0] + attribute \src "issuer_ls180.v:95730.3-95748.6" + wire $0\dec31_dec_sub24_sgn[0:0] + attribute \src "issuer_ls180.v:95654.3-95672.6" + wire $0\dec31_dec_sub24_sgn_ext[0:0] + attribute \src "issuer_ls180.v:95502.3-95520.6" + wire width 2 $0\dec31_dec_sub24_upd[1:0] + attribute \src "issuer_ls180.v:95207.7-95207.20" + wire $0\initial[0:0] + attribute \src "issuer_ls180.v:95559.3-95577.6" + wire width 8 $1\dec31_dec_sub24_asmcode[7:0] + attribute \src "issuer_ls180.v:95635.3-95653.6" + wire $1\dec31_dec_sub24_br[0:0] + attribute \src "issuer_ls180.v:95882.3-95900.6" + wire width 3 $1\dec31_dec_sub24_cr_in[2:0] + attribute \src "issuer_ls180.v:95901.3-95919.6" + wire width 3 $1\dec31_dec_sub24_cr_out[2:0] + attribute \src "issuer_ls180.v:95540.3-95558.6" + wire width 2 $1\dec31_dec_sub24_cry_in[1:0] + attribute \src "issuer_ls180.v:95616.3-95634.6" + wire $1\dec31_dec_sub24_cry_out[0:0] + attribute \src "issuer_ls180.v:95787.3-95805.6" + wire width 5 $1\dec31_dec_sub24_form[4:0] + attribute \src "issuer_ls180.v:95464.3-95482.6" + wire width 12 $1\dec31_dec_sub24_function_unit[11:0] + attribute \src "issuer_ls180.v:95806.3-95824.6" + wire width 3 $1\dec31_dec_sub24_in1_sel[2:0] + attribute \src "issuer_ls180.v:95825.3-95843.6" + wire width 4 $1\dec31_dec_sub24_in2_sel[3:0] + attribute \src "issuer_ls180.v:95844.3-95862.6" + wire width 2 $1\dec31_dec_sub24_in3_sel[1:0] + attribute \src "issuer_ls180.v:95673.3-95691.6" + wire width 7 $1\dec31_dec_sub24_internal_op[6:0] + attribute \src "issuer_ls180.v:95578.3-95596.6" + wire $1\dec31_dec_sub24_inv_a[0:0] + attribute \src "issuer_ls180.v:95597.3-95615.6" + wire $1\dec31_dec_sub24_inv_out[0:0] + attribute \src "issuer_ls180.v:95711.3-95729.6" + wire $1\dec31_dec_sub24_is_32b[0:0] + attribute \src "issuer_ls180.v:95483.3-95501.6" + wire width 4 $1\dec31_dec_sub24_ldst_len[3:0] + attribute \src "issuer_ls180.v:95749.3-95767.6" + wire $1\dec31_dec_sub24_lk[0:0] + attribute \src "issuer_ls180.v:95863.3-95881.6" + wire width 2 $1\dec31_dec_sub24_out_sel[1:0] + attribute \src "issuer_ls180.v:95521.3-95539.6" + wire width 2 $1\dec31_dec_sub24_rc_sel[1:0] + attribute \src "issuer_ls180.v:95692.3-95710.6" + wire $1\dec31_dec_sub24_rsrv[0:0] + attribute \src "issuer_ls180.v:95768.3-95786.6" + wire $1\dec31_dec_sub24_sgl_pipe[0:0] + attribute \src "issuer_ls180.v:95730.3-95748.6" + wire $1\dec31_dec_sub24_sgn[0:0] + attribute \src "issuer_ls180.v:95654.3-95672.6" + wire $1\dec31_dec_sub24_sgn_ext[0:0] + attribute \src "issuer_ls180.v:95502.3-95520.6" + wire width 2 $1\dec31_dec_sub24_upd[1:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 8 output 4 \dec31_dec_sub24_asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 18 \dec31_dec_sub24_br + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 9 \dec31_dec_sub24_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 10 \dec31_dec_sub24_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 14 \dec31_dec_sub24_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 17 \dec31_dec_sub24_cry_out + attribute \enum_base_type "Form" + attribute \enum_value_00000 "NONE" + attribute \enum_value_00001 "I" + attribute \enum_value_00010 "B" + attribute \enum_value_00011 "SC" + attribute \enum_value_00100 "D" + attribute \enum_value_00101 "DS" + attribute \enum_value_00110 "DQ" + attribute \enum_value_00111 "DX" + attribute \enum_value_01000 "X" + attribute \enum_value_01001 "XL" + attribute \enum_value_01010 "XFX" + attribute \enum_value_01011 "XFL" + attribute \enum_value_01100 "XX1" + attribute \enum_value_01101 "XX2" + attribute \enum_value_01110 "XX3" + attribute \enum_value_01111 "XX4" + attribute \enum_value_10000 "XS" + attribute \enum_value_10001 "XO" + attribute \enum_value_10010 "A" + attribute \enum_value_10011 "M" + attribute \enum_value_10100 "MD" + attribute \enum_value_10101 "MDS" + attribute \enum_value_10110 "VA" + attribute \enum_value_10111 "VC" + attribute \enum_value_11000 "VX" + attribute \enum_value_11001 "EVX" + attribute \enum_value_11010 "EVS" + attribute \enum_value_11011 "Z22" + attribute \enum_value_11100 "Z23" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 5 output 3 \dec31_dec_sub24_form + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 12 output 1 \dec31_dec_sub24_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 5 \dec31_dec_sub24_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 output 6 \dec31_dec_sub24_in2_sel + attribute \enum_base_type "In3Sel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RS" + attribute \enum_value_10 "RB" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 7 \dec31_dec_sub24_in3_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 7 output 2 \dec31_dec_sub24_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 15 \dec31_dec_sub24_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 16 \dec31_dec_sub24_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 21 \dec31_dec_sub24_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 output 11 \dec31_dec_sub24_ldst_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 23 \dec31_dec_sub24_lk + attribute \enum_base_type "OutSel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RT" + attribute \enum_value_10 "RA" + attribute \enum_value_11 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 8 \dec31_dec_sub24_out_sel + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 13 \dec31_dec_sub24_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 20 \dec31_dec_sub24_rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 24 \dec31_dec_sub24_sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 22 \dec31_dec_sub24_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 19 \dec31_dec_sub24_sgn_ext + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 12 \dec31_dec_sub24_upd + attribute \src "issuer_ls180.v:95207.7-95207.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + wire width 32 input 25 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:320" + wire width 5 \opcode_switch + attribute \src "issuer_ls180.v:95207.7-95207.20" + process $proc$issuer_ls180.v:95207$3895 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "issuer_ls180.v:95464.3-95482.6" + process $proc$issuer_ls180.v:95464$3871 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub24_function_unit[11:0] $1\dec31_dec_sub24_function_unit[11:0] + attribute \src "issuer_ls180.v:95465.5-95465.29" + switch \initial + attribute \src "issuer_ls180.v:95465.9-95465.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub24_function_unit[11:0] 12'000000001000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub24_function_unit[11:0] 12'000000001000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub24_function_unit[11:0] 12'000000001000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub24_function_unit[11:0] 12'000000001000 + case + assign $1\dec31_dec_sub24_function_unit[11:0] 12'000000000000 + end + sync always + update \dec31_dec_sub24_function_unit $0\dec31_dec_sub24_function_unit[11:0] + end + attribute \src "issuer_ls180.v:95483.3-95501.6" + process $proc$issuer_ls180.v:95483$3872 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub24_ldst_len[3:0] $1\dec31_dec_sub24_ldst_len[3:0] + attribute \src "issuer_ls180.v:95484.5-95484.29" + switch \initial + attribute \src "issuer_ls180.v:95484.9-95484.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub24_ldst_len[3:0] 4'0000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub24_ldst_len[3:0] 4'0000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub24_ldst_len[3:0] 4'0000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub24_ldst_len[3:0] 4'0000 + case + assign $1\dec31_dec_sub24_ldst_len[3:0] 4'0000 + end + sync always + update \dec31_dec_sub24_ldst_len $0\dec31_dec_sub24_ldst_len[3:0] + end + attribute \src "issuer_ls180.v:95502.3-95520.6" + process $proc$issuer_ls180.v:95502$3873 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub24_upd[1:0] $1\dec31_dec_sub24_upd[1:0] + attribute \src "issuer_ls180.v:95503.5-95503.29" + switch \initial + attribute \src "issuer_ls180.v:95503.9-95503.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub24_upd[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub24_upd[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub24_upd[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub24_upd[1:0] 2'00 + case + assign $1\dec31_dec_sub24_upd[1:0] 2'00 + end + sync always + update \dec31_dec_sub24_upd $0\dec31_dec_sub24_upd[1:0] + end + attribute \src "issuer_ls180.v:95521.3-95539.6" + process $proc$issuer_ls180.v:95521$3874 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub24_rc_sel[1:0] $1\dec31_dec_sub24_rc_sel[1:0] + attribute \src "issuer_ls180.v:95522.5-95522.29" + switch \initial + attribute \src "issuer_ls180.v:95522.9-95522.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub24_rc_sel[1:0] 2'10 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub24_rc_sel[1:0] 2'10 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub24_rc_sel[1:0] 2'10 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub24_rc_sel[1:0] 2'10 + case + assign $1\dec31_dec_sub24_rc_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub24_rc_sel $0\dec31_dec_sub24_rc_sel[1:0] + end + attribute \src "issuer_ls180.v:95540.3-95558.6" + process $proc$issuer_ls180.v:95540$3875 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub24_cry_in[1:0] $1\dec31_dec_sub24_cry_in[1:0] + attribute \src "issuer_ls180.v:95541.5-95541.29" + switch \initial + attribute \src "issuer_ls180.v:95541.9-95541.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub24_cry_in[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub24_cry_in[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub24_cry_in[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub24_cry_in[1:0] 2'00 + case + assign $1\dec31_dec_sub24_cry_in[1:0] 2'00 + end + sync always + update \dec31_dec_sub24_cry_in $0\dec31_dec_sub24_cry_in[1:0] + end + attribute \src "issuer_ls180.v:95559.3-95577.6" + process $proc$issuer_ls180.v:95559$3876 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub24_asmcode[7:0] $1\dec31_dec_sub24_asmcode[7:0] + attribute \src "issuer_ls180.v:95560.5-95560.29" + switch \initial + attribute \src "issuer_ls180.v:95560.9-95560.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub24_asmcode[7:0] 8'10011111 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub24_asmcode[7:0] 8'10100010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub24_asmcode[7:0] 8'10100011 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub24_asmcode[7:0] 8'10100101 + case + assign $1\dec31_dec_sub24_asmcode[7:0] 8'00000000 + end + sync always + update \dec31_dec_sub24_asmcode $0\dec31_dec_sub24_asmcode[7:0] + end + attribute \src "issuer_ls180.v:95578.3-95596.6" + process $proc$issuer_ls180.v:95578$3877 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub24_inv_a[0:0] $1\dec31_dec_sub24_inv_a[0:0] + attribute \src "issuer_ls180.v:95579.5-95579.29" + switch \initial + attribute \src "issuer_ls180.v:95579.9-95579.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub24_inv_a[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub24_inv_a[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub24_inv_a[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub24_inv_a[0:0] 1'0 + case + assign $1\dec31_dec_sub24_inv_a[0:0] 1'0 + end + sync always + update \dec31_dec_sub24_inv_a $0\dec31_dec_sub24_inv_a[0:0] + end + attribute \src "issuer_ls180.v:95597.3-95615.6" + process $proc$issuer_ls180.v:95597$3878 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub24_inv_out[0:0] $1\dec31_dec_sub24_inv_out[0:0] + attribute \src "issuer_ls180.v:95598.5-95598.29" + switch \initial + attribute \src "issuer_ls180.v:95598.9-95598.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub24_inv_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub24_inv_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub24_inv_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub24_inv_out[0:0] 1'0 + case + assign $1\dec31_dec_sub24_inv_out[0:0] 1'0 + end + sync always + update \dec31_dec_sub24_inv_out $0\dec31_dec_sub24_inv_out[0:0] + end + attribute \src "issuer_ls180.v:95616.3-95634.6" + process $proc$issuer_ls180.v:95616$3879 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub24_cry_out[0:0] $1\dec31_dec_sub24_cry_out[0:0] + attribute \src "issuer_ls180.v:95617.5-95617.29" + switch \initial + attribute \src "issuer_ls180.v:95617.9-95617.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub24_cry_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub24_cry_out[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub24_cry_out[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub24_cry_out[0:0] 1'0 + case + assign $1\dec31_dec_sub24_cry_out[0:0] 1'0 + end + sync always + update \dec31_dec_sub24_cry_out $0\dec31_dec_sub24_cry_out[0:0] + end + attribute \src "issuer_ls180.v:95635.3-95653.6" + process $proc$issuer_ls180.v:95635$3880 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub24_br[0:0] $1\dec31_dec_sub24_br[0:0] + attribute \src "issuer_ls180.v:95636.5-95636.29" + switch \initial + attribute \src "issuer_ls180.v:95636.9-95636.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub24_br[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub24_br[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub24_br[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub24_br[0:0] 1'0 + case + assign $1\dec31_dec_sub24_br[0:0] 1'0 + end + sync always + update \dec31_dec_sub24_br $0\dec31_dec_sub24_br[0:0] + end + attribute \src "issuer_ls180.v:95654.3-95672.6" + process $proc$issuer_ls180.v:95654$3881 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub24_sgn_ext[0:0] $1\dec31_dec_sub24_sgn_ext[0:0] + attribute \src "issuer_ls180.v:95655.5-95655.29" + switch \initial + attribute \src "issuer_ls180.v:95655.9-95655.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub24_sgn_ext[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub24_sgn_ext[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub24_sgn_ext[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub24_sgn_ext[0:0] 1'0 + case + assign $1\dec31_dec_sub24_sgn_ext[0:0] 1'0 + end + sync always + update \dec31_dec_sub24_sgn_ext $0\dec31_dec_sub24_sgn_ext[0:0] + end + attribute \src "issuer_ls180.v:95673.3-95691.6" + process $proc$issuer_ls180.v:95673$3882 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub24_internal_op[6:0] $1\dec31_dec_sub24_internal_op[6:0] + attribute \src "issuer_ls180.v:95674.5-95674.29" + switch \initial + attribute \src "issuer_ls180.v:95674.9-95674.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub24_internal_op[6:0] 7'0111100 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub24_internal_op[6:0] 7'0111101 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub24_internal_op[6:0] 7'0111101 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub24_internal_op[6:0] 7'0111101 + case + assign $1\dec31_dec_sub24_internal_op[6:0] 7'0000000 + end + sync always + update \dec31_dec_sub24_internal_op $0\dec31_dec_sub24_internal_op[6:0] + end + attribute \src "issuer_ls180.v:95692.3-95710.6" + process $proc$issuer_ls180.v:95692$3883 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub24_rsrv[0:0] $1\dec31_dec_sub24_rsrv[0:0] + attribute \src "issuer_ls180.v:95693.5-95693.29" + switch \initial + attribute \src "issuer_ls180.v:95693.9-95693.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub24_rsrv[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub24_rsrv[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub24_rsrv[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub24_rsrv[0:0] 1'0 + case + assign $1\dec31_dec_sub24_rsrv[0:0] 1'0 + end + sync always + update \dec31_dec_sub24_rsrv $0\dec31_dec_sub24_rsrv[0:0] + end + attribute \src "issuer_ls180.v:95711.3-95729.6" + process $proc$issuer_ls180.v:95711$3884 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub24_is_32b[0:0] $1\dec31_dec_sub24_is_32b[0:0] + attribute \src "issuer_ls180.v:95712.5-95712.29" + switch \initial + attribute \src "issuer_ls180.v:95712.9-95712.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub24_is_32b[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub24_is_32b[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub24_is_32b[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub24_is_32b[0:0] 1'1 + case + assign $1\dec31_dec_sub24_is_32b[0:0] 1'0 + end + sync always + update \dec31_dec_sub24_is_32b $0\dec31_dec_sub24_is_32b[0:0] + end + attribute \src "issuer_ls180.v:95730.3-95748.6" + process $proc$issuer_ls180.v:95730$3885 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub24_sgn[0:0] $1\dec31_dec_sub24_sgn[0:0] + attribute \src "issuer_ls180.v:95731.5-95731.29" + switch \initial + attribute \src "issuer_ls180.v:95731.9-95731.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub24_sgn[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub24_sgn[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub24_sgn[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub24_sgn[0:0] 1'0 + case + assign $1\dec31_dec_sub24_sgn[0:0] 1'0 + end + sync always + update \dec31_dec_sub24_sgn $0\dec31_dec_sub24_sgn[0:0] + end + attribute \src "issuer_ls180.v:95749.3-95767.6" + process $proc$issuer_ls180.v:95749$3886 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub24_lk[0:0] $1\dec31_dec_sub24_lk[0:0] + attribute \src "issuer_ls180.v:95750.5-95750.29" + switch \initial + attribute \src "issuer_ls180.v:95750.9-95750.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub24_lk[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub24_lk[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub24_lk[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub24_lk[0:0] 1'0 + case + assign $1\dec31_dec_sub24_lk[0:0] 1'0 + end + sync always + update \dec31_dec_sub24_lk $0\dec31_dec_sub24_lk[0:0] + end + attribute \src "issuer_ls180.v:95768.3-95786.6" + process $proc$issuer_ls180.v:95768$3887 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub24_sgl_pipe[0:0] $1\dec31_dec_sub24_sgl_pipe[0:0] + attribute \src "issuer_ls180.v:95769.5-95769.29" + switch \initial + attribute \src "issuer_ls180.v:95769.9-95769.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub24_sgl_pipe[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub24_sgl_pipe[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub24_sgl_pipe[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub24_sgl_pipe[0:0] 1'0 + case + assign $1\dec31_dec_sub24_sgl_pipe[0:0] 1'0 + end + sync always + update \dec31_dec_sub24_sgl_pipe $0\dec31_dec_sub24_sgl_pipe[0:0] + end + attribute \src "issuer_ls180.v:95787.3-95805.6" + process $proc$issuer_ls180.v:95787$3888 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub24_form[4:0] $1\dec31_dec_sub24_form[4:0] + attribute \src "issuer_ls180.v:95788.5-95788.29" + switch \initial + attribute \src "issuer_ls180.v:95788.9-95788.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub24_form[4:0] 5'01000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub24_form[4:0] 5'01000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub24_form[4:0] 5'01000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub24_form[4:0] 5'01000 + case + assign $1\dec31_dec_sub24_form[4:0] 5'00000 + end + sync always + update \dec31_dec_sub24_form $0\dec31_dec_sub24_form[4:0] + end + attribute \src "issuer_ls180.v:95806.3-95824.6" + process $proc$issuer_ls180.v:95806$3889 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub24_in1_sel[2:0] $1\dec31_dec_sub24_in1_sel[2:0] + attribute \src "issuer_ls180.v:95807.5-95807.29" + switch \initial + attribute \src "issuer_ls180.v:95807.9-95807.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub24_in1_sel[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub24_in1_sel[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub24_in1_sel[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub24_in1_sel[2:0] 3'000 + case + assign $1\dec31_dec_sub24_in1_sel[2:0] 3'000 + end + sync always + update \dec31_dec_sub24_in1_sel $0\dec31_dec_sub24_in1_sel[2:0] + end + attribute \src "issuer_ls180.v:95825.3-95843.6" + process $proc$issuer_ls180.v:95825$3890 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub24_in2_sel[3:0] $1\dec31_dec_sub24_in2_sel[3:0] + attribute \src "issuer_ls180.v:95826.5-95826.29" + switch \initial + attribute \src "issuer_ls180.v:95826.9-95826.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub24_in2_sel[3:0] 4'0001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub24_in2_sel[3:0] 4'0001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub24_in2_sel[3:0] 4'1011 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub24_in2_sel[3:0] 4'0001 + case + assign $1\dec31_dec_sub24_in2_sel[3:0] 4'0000 + end + sync always + update \dec31_dec_sub24_in2_sel $0\dec31_dec_sub24_in2_sel[3:0] + end + attribute \src "issuer_ls180.v:95844.3-95862.6" + process $proc$issuer_ls180.v:95844$3891 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub24_in3_sel[1:0] $1\dec31_dec_sub24_in3_sel[1:0] + attribute \src "issuer_ls180.v:95845.5-95845.29" + switch \initial + attribute \src "issuer_ls180.v:95845.9-95845.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub24_in3_sel[1:0] 2'01 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub24_in3_sel[1:0] 2'01 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub24_in3_sel[1:0] 2'01 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub24_in3_sel[1:0] 2'01 + case + assign $1\dec31_dec_sub24_in3_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub24_in3_sel $0\dec31_dec_sub24_in3_sel[1:0] + end + attribute \src "issuer_ls180.v:95863.3-95881.6" + process $proc$issuer_ls180.v:95863$3892 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub24_out_sel[1:0] $1\dec31_dec_sub24_out_sel[1:0] + attribute \src "issuer_ls180.v:95864.5-95864.29" + switch \initial + attribute \src "issuer_ls180.v:95864.9-95864.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub24_out_sel[1:0] 2'10 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub24_out_sel[1:0] 2'10 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub24_out_sel[1:0] 2'10 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub24_out_sel[1:0] 2'10 + case + assign $1\dec31_dec_sub24_out_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub24_out_sel $0\dec31_dec_sub24_out_sel[1:0] + end + attribute \src "issuer_ls180.v:95882.3-95900.6" + process $proc$issuer_ls180.v:95882$3893 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub24_cr_in[2:0] $1\dec31_dec_sub24_cr_in[2:0] + attribute \src "issuer_ls180.v:95883.5-95883.29" + switch \initial + attribute \src "issuer_ls180.v:95883.9-95883.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub24_cr_in[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub24_cr_in[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub24_cr_in[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub24_cr_in[2:0] 3'000 + case + assign $1\dec31_dec_sub24_cr_in[2:0] 3'000 + end + sync always + update \dec31_dec_sub24_cr_in $0\dec31_dec_sub24_cr_in[2:0] + end + attribute \src "issuer_ls180.v:95901.3-95919.6" + process $proc$issuer_ls180.v:95901$3894 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub24_cr_out[2:0] $1\dec31_dec_sub24_cr_out[2:0] + attribute \src "issuer_ls180.v:95902.5-95902.29" + switch \initial + attribute \src "issuer_ls180.v:95902.9-95902.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub24_cr_out[2:0] 3'001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub24_cr_out[2:0] 3'001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub24_cr_out[2:0] 3'001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub24_cr_out[2:0] 3'001 + case + assign $1\dec31_dec_sub24_cr_out[2:0] 3'000 + end + sync always + update \dec31_dec_sub24_cr_out $0\dec31_dec_sub24_cr_out[2:0] + end + connect \opcode_switch \opcode_in [10:6] +end +attribute \src "issuer_ls180.v:95925.1-97432.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.dec2.dec.dec31.dec31_dec_sub26" +attribute \generator "nMigen" +module \dec31_dec_sub26 + attribute \src "issuer_ls180.v:96443.3-96494.6" + wire width 8 $0\dec31_dec_sub26_asmcode[7:0] + attribute \src "issuer_ls180.v:96651.3-96702.6" + wire $0\dec31_dec_sub26_br[0:0] + attribute \src "issuer_ls180.v:97327.3-97378.6" + wire width 3 $0\dec31_dec_sub26_cr_in[2:0] + attribute \src "issuer_ls180.v:97379.3-97430.6" + wire width 3 $0\dec31_dec_sub26_cr_out[2:0] + attribute \src "issuer_ls180.v:96391.3-96442.6" + wire width 2 $0\dec31_dec_sub26_cry_in[1:0] + attribute \src "issuer_ls180.v:96599.3-96650.6" + wire $0\dec31_dec_sub26_cry_out[0:0] + attribute \src "issuer_ls180.v:97067.3-97118.6" + wire width 5 $0\dec31_dec_sub26_form[4:0] + attribute \src "issuer_ls180.v:96183.3-96234.6" + wire width 12 $0\dec31_dec_sub26_function_unit[11:0] + attribute \src "issuer_ls180.v:97119.3-97170.6" + wire width 3 $0\dec31_dec_sub26_in1_sel[2:0] + attribute \src "issuer_ls180.v:97171.3-97222.6" + wire width 4 $0\dec31_dec_sub26_in2_sel[3:0] + attribute \src "issuer_ls180.v:97223.3-97274.6" + wire width 2 $0\dec31_dec_sub26_in3_sel[1:0] + attribute \src "issuer_ls180.v:96755.3-96806.6" + wire width 7 $0\dec31_dec_sub26_internal_op[6:0] + attribute \src "issuer_ls180.v:96495.3-96546.6" + wire $0\dec31_dec_sub26_inv_a[0:0] + attribute \src "issuer_ls180.v:96547.3-96598.6" + wire $0\dec31_dec_sub26_inv_out[0:0] + attribute \src "issuer_ls180.v:96859.3-96910.6" + wire $0\dec31_dec_sub26_is_32b[0:0] + attribute \src "issuer_ls180.v:96235.3-96286.6" + wire width 4 $0\dec31_dec_sub26_ldst_len[3:0] + attribute \src "issuer_ls180.v:96963.3-97014.6" + wire $0\dec31_dec_sub26_lk[0:0] + attribute \src "issuer_ls180.v:97275.3-97326.6" + wire width 2 $0\dec31_dec_sub26_out_sel[1:0] + attribute \src "issuer_ls180.v:96339.3-96390.6" + wire width 2 $0\dec31_dec_sub26_rc_sel[1:0] + attribute \src "issuer_ls180.v:96807.3-96858.6" + wire $0\dec31_dec_sub26_rsrv[0:0] + attribute \src "issuer_ls180.v:97015.3-97066.6" + wire $0\dec31_dec_sub26_sgl_pipe[0:0] + attribute \src "issuer_ls180.v:96911.3-96962.6" + wire $0\dec31_dec_sub26_sgn[0:0] + attribute \src "issuer_ls180.v:96703.3-96754.6" + wire $0\dec31_dec_sub26_sgn_ext[0:0] + attribute \src "issuer_ls180.v:96287.3-96338.6" + wire width 2 $0\dec31_dec_sub26_upd[1:0] + attribute \src "issuer_ls180.v:95926.7-95926.20" + wire $0\initial[0:0] + attribute \src "issuer_ls180.v:96443.3-96494.6" + wire width 8 $1\dec31_dec_sub26_asmcode[7:0] + attribute \src "issuer_ls180.v:96651.3-96702.6" + wire $1\dec31_dec_sub26_br[0:0] + attribute \src "issuer_ls180.v:97327.3-97378.6" + wire width 3 $1\dec31_dec_sub26_cr_in[2:0] + attribute \src "issuer_ls180.v:97379.3-97430.6" + wire width 3 $1\dec31_dec_sub26_cr_out[2:0] + attribute \src "issuer_ls180.v:96391.3-96442.6" + wire width 2 $1\dec31_dec_sub26_cry_in[1:0] + attribute \src "issuer_ls180.v:96599.3-96650.6" + wire $1\dec31_dec_sub26_cry_out[0:0] + attribute \src "issuer_ls180.v:97067.3-97118.6" + wire width 5 $1\dec31_dec_sub26_form[4:0] + attribute \src "issuer_ls180.v:96183.3-96234.6" + wire width 12 $1\dec31_dec_sub26_function_unit[11:0] + attribute \src "issuer_ls180.v:97119.3-97170.6" + wire width 3 $1\dec31_dec_sub26_in1_sel[2:0] + attribute \src "issuer_ls180.v:97171.3-97222.6" + wire width 4 $1\dec31_dec_sub26_in2_sel[3:0] + attribute \src "issuer_ls180.v:97223.3-97274.6" + wire width 2 $1\dec31_dec_sub26_in3_sel[1:0] + attribute \src "issuer_ls180.v:96755.3-96806.6" + wire width 7 $1\dec31_dec_sub26_internal_op[6:0] + attribute \src "issuer_ls180.v:96495.3-96546.6" + wire $1\dec31_dec_sub26_inv_a[0:0] + attribute \src "issuer_ls180.v:96547.3-96598.6" + wire $1\dec31_dec_sub26_inv_out[0:0] + attribute \src "issuer_ls180.v:96859.3-96910.6" + wire $1\dec31_dec_sub26_is_32b[0:0] + attribute \src "issuer_ls180.v:96235.3-96286.6" + wire width 4 $1\dec31_dec_sub26_ldst_len[3:0] + attribute \src "issuer_ls180.v:96963.3-97014.6" + wire $1\dec31_dec_sub26_lk[0:0] + attribute \src "issuer_ls180.v:97275.3-97326.6" + wire width 2 $1\dec31_dec_sub26_out_sel[1:0] + attribute \src "issuer_ls180.v:96339.3-96390.6" + wire width 2 $1\dec31_dec_sub26_rc_sel[1:0] + attribute \src "issuer_ls180.v:96807.3-96858.6" + wire $1\dec31_dec_sub26_rsrv[0:0] + attribute \src "issuer_ls180.v:97015.3-97066.6" + wire $1\dec31_dec_sub26_sgl_pipe[0:0] + attribute \src "issuer_ls180.v:96911.3-96962.6" + wire $1\dec31_dec_sub26_sgn[0:0] + attribute \src "issuer_ls180.v:96703.3-96754.6" + wire $1\dec31_dec_sub26_sgn_ext[0:0] + attribute \src "issuer_ls180.v:96287.3-96338.6" + wire width 2 $1\dec31_dec_sub26_upd[1:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 8 output 4 \dec31_dec_sub26_asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 18 \dec31_dec_sub26_br + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 9 \dec31_dec_sub26_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 10 \dec31_dec_sub26_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 14 \dec31_dec_sub26_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 17 \dec31_dec_sub26_cry_out + attribute \enum_base_type "Form" + attribute \enum_value_00000 "NONE" + attribute \enum_value_00001 "I" + attribute \enum_value_00010 "B" + attribute \enum_value_00011 "SC" + attribute \enum_value_00100 "D" + attribute \enum_value_00101 "DS" + attribute \enum_value_00110 "DQ" + attribute \enum_value_00111 "DX" + attribute \enum_value_01000 "X" + attribute \enum_value_01001 "XL" + attribute \enum_value_01010 "XFX" + attribute \enum_value_01011 "XFL" + attribute \enum_value_01100 "XX1" + attribute \enum_value_01101 "XX2" + attribute \enum_value_01110 "XX3" + attribute \enum_value_01111 "XX4" + attribute \enum_value_10000 "XS" + attribute \enum_value_10001 "XO" + attribute \enum_value_10010 "A" + attribute \enum_value_10011 "M" + attribute \enum_value_10100 "MD" + attribute \enum_value_10101 "MDS" + attribute \enum_value_10110 "VA" + attribute \enum_value_10111 "VC" + attribute \enum_value_11000 "VX" + attribute \enum_value_11001 "EVX" + attribute \enum_value_11010 "EVS" + attribute \enum_value_11011 "Z22" + attribute \enum_value_11100 "Z23" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 5 output 3 \dec31_dec_sub26_form + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 12 output 1 \dec31_dec_sub26_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 5 \dec31_dec_sub26_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 output 6 \dec31_dec_sub26_in2_sel + attribute \enum_base_type "In3Sel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RS" + attribute \enum_value_10 "RB" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 7 \dec31_dec_sub26_in3_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 7 output 2 \dec31_dec_sub26_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 15 \dec31_dec_sub26_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 16 \dec31_dec_sub26_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 21 \dec31_dec_sub26_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 output 11 \dec31_dec_sub26_ldst_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 23 \dec31_dec_sub26_lk + attribute \enum_base_type "OutSel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RT" + attribute \enum_value_10 "RA" + attribute \enum_value_11 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 8 \dec31_dec_sub26_out_sel + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 13 \dec31_dec_sub26_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 20 \dec31_dec_sub26_rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 24 \dec31_dec_sub26_sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 22 \dec31_dec_sub26_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 19 \dec31_dec_sub26_sgn_ext + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 12 \dec31_dec_sub26_upd + attribute \src "issuer_ls180.v:95926.7-95926.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + wire width 32 input 25 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:320" + wire width 5 \opcode_switch + attribute \src "issuer_ls180.v:95926.7-95926.20" + process $proc$issuer_ls180.v:95926$3920 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "issuer_ls180.v:96183.3-96234.6" + process $proc$issuer_ls180.v:96183$3896 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub26_function_unit[11:0] $1\dec31_dec_sub26_function_unit[11:0] + attribute \src "issuer_ls180.v:96184.5-96184.29" + switch \initial + attribute \src "issuer_ls180.v:96184.9-96184.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub26_function_unit[11:0] 12'000000010000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub26_function_unit[11:0] 12'000000010000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub26_function_unit[11:0] 12'000000010000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub26_function_unit[11:0] 12'000000010000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub26_function_unit[11:0] 12'000000000010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub26_function_unit[11:0] 12'000000000010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub26_function_unit[11:0] 12'000000000010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub26_function_unit[11:0] 12'000000001000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub26_function_unit[11:0] 12'000000010000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub26_function_unit[11:0] 12'000000010000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub26_function_unit[11:0] 12'000000010000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub26_function_unit[11:0] 12'000000010000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub26_function_unit[11:0] 12'000000010000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub26_function_unit[11:0] 12'000000001000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub26_function_unit[11:0] 12'000000001000 + case + assign $1\dec31_dec_sub26_function_unit[11:0] 12'000000000000 + end + sync always + update \dec31_dec_sub26_function_unit $0\dec31_dec_sub26_function_unit[11:0] + end + attribute \src "issuer_ls180.v:96235.3-96286.6" + process $proc$issuer_ls180.v:96235$3897 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub26_ldst_len[3:0] $1\dec31_dec_sub26_ldst_len[3:0] + attribute \src "issuer_ls180.v:96236.5-96236.29" + switch \initial + attribute \src "issuer_ls180.v:96236.9-96236.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub26_ldst_len[3:0] 4'0000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub26_ldst_len[3:0] 4'0000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub26_ldst_len[3:0] 4'0000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub26_ldst_len[3:0] 4'0000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub26_ldst_len[3:0] 4'0001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub26_ldst_len[3:0] 4'0010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub26_ldst_len[3:0] 4'0100 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub26_ldst_len[3:0] 4'0000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub26_ldst_len[3:0] 4'0001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub26_ldst_len[3:0] 4'1000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub26_ldst_len[3:0] 4'0100 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub26_ldst_len[3:0] 4'1000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub26_ldst_len[3:0] 4'0100 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub26_ldst_len[3:0] 4'0000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub26_ldst_len[3:0] 4'0000 + case + assign $1\dec31_dec_sub26_ldst_len[3:0] 4'0000 + end + sync always + update \dec31_dec_sub26_ldst_len $0\dec31_dec_sub26_ldst_len[3:0] + end + attribute \src "issuer_ls180.v:96287.3-96338.6" + process $proc$issuer_ls180.v:96287$3898 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub26_upd[1:0] $1\dec31_dec_sub26_upd[1:0] + attribute \src "issuer_ls180.v:96288.5-96288.29" + switch \initial + attribute \src "issuer_ls180.v:96288.9-96288.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub26_upd[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub26_upd[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub26_upd[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub26_upd[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub26_upd[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub26_upd[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub26_upd[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub26_upd[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub26_upd[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub26_upd[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub26_upd[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub26_upd[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub26_upd[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub26_upd[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub26_upd[1:0] 2'00 + case + assign $1\dec31_dec_sub26_upd[1:0] 2'00 + end + sync always + update \dec31_dec_sub26_upd $0\dec31_dec_sub26_upd[1:0] + end + attribute \src "issuer_ls180.v:96339.3-96390.6" + process $proc$issuer_ls180.v:96339$3899 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub26_rc_sel[1:0] $1\dec31_dec_sub26_rc_sel[1:0] + attribute \src "issuer_ls180.v:96340.5-96340.29" + switch \initial + attribute \src "issuer_ls180.v:96340.9-96340.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub26_rc_sel[1:0] 2'10 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub26_rc_sel[1:0] 2'10 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub26_rc_sel[1:0] 2'10 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub26_rc_sel[1:0] 2'10 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub26_rc_sel[1:0] 2'10 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub26_rc_sel[1:0] 2'10 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub26_rc_sel[1:0] 2'10 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub26_rc_sel[1:0] 2'10 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub26_rc_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub26_rc_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub26_rc_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub26_rc_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub26_rc_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub26_rc_sel[1:0] 2'10 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub26_rc_sel[1:0] 2'10 + case + assign $1\dec31_dec_sub26_rc_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub26_rc_sel $0\dec31_dec_sub26_rc_sel[1:0] + end + attribute \src "issuer_ls180.v:96391.3-96442.6" + process $proc$issuer_ls180.v:96391$3900 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub26_cry_in[1:0] $1\dec31_dec_sub26_cry_in[1:0] + attribute \src "issuer_ls180.v:96392.5-96392.29" + switch \initial + attribute \src "issuer_ls180.v:96392.9-96392.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub26_cry_in[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub26_cry_in[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub26_cry_in[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub26_cry_in[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub26_cry_in[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub26_cry_in[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub26_cry_in[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub26_cry_in[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub26_cry_in[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub26_cry_in[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub26_cry_in[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub26_cry_in[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub26_cry_in[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub26_cry_in[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub26_cry_in[1:0] 2'00 + case + assign $1\dec31_dec_sub26_cry_in[1:0] 2'00 + end + sync always + update \dec31_dec_sub26_cry_in $0\dec31_dec_sub26_cry_in[1:0] + end + attribute \src "issuer_ls180.v:96443.3-96494.6" + process $proc$issuer_ls180.v:96443$3901 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub26_asmcode[7:0] $1\dec31_dec_sub26_asmcode[7:0] + attribute \src "issuer_ls180.v:96444.5-96444.29" + switch \initial + attribute \src "issuer_ls180.v:96444.9-96444.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub26_asmcode[7:0] 8'00100001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub26_asmcode[7:0] 8'00100010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub26_asmcode[7:0] 8'00100011 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub26_asmcode[7:0] 8'00100100 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub26_asmcode[7:0] 8'01000100 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub26_asmcode[7:0] 8'01000101 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub26_asmcode[7:0] 8'01000110 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub26_asmcode[7:0] 8'01000111 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub26_asmcode[7:0] 8'10001100 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub26_asmcode[7:0] 8'10001101 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub26_asmcode[7:0] 8'10001110 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub26_asmcode[7:0] 8'10001111 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub26_asmcode[7:0] 8'10010000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub26_asmcode[7:0] 8'10100000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub26_asmcode[7:0] 8'10100001 + case + assign $1\dec31_dec_sub26_asmcode[7:0] 8'00000000 + end + sync always + update \dec31_dec_sub26_asmcode $0\dec31_dec_sub26_asmcode[7:0] + end + attribute \src "issuer_ls180.v:96495.3-96546.6" + process $proc$issuer_ls180.v:96495$3902 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub26_inv_a[0:0] $1\dec31_dec_sub26_inv_a[0:0] + attribute \src "issuer_ls180.v:96496.5-96496.29" + switch \initial + attribute \src "issuer_ls180.v:96496.9-96496.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub26_inv_a[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub26_inv_a[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub26_inv_a[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub26_inv_a[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub26_inv_a[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub26_inv_a[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub26_inv_a[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub26_inv_a[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub26_inv_a[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub26_inv_a[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub26_inv_a[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub26_inv_a[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub26_inv_a[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub26_inv_a[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub26_inv_a[0:0] 1'0 + case + assign $1\dec31_dec_sub26_inv_a[0:0] 1'0 + end + sync always + update \dec31_dec_sub26_inv_a $0\dec31_dec_sub26_inv_a[0:0] + end + attribute \src "issuer_ls180.v:96547.3-96598.6" + process $proc$issuer_ls180.v:96547$3903 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub26_inv_out[0:0] $1\dec31_dec_sub26_inv_out[0:0] + attribute \src "issuer_ls180.v:96548.5-96548.29" + switch \initial + attribute \src "issuer_ls180.v:96548.9-96548.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub26_inv_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub26_inv_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub26_inv_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub26_inv_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub26_inv_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub26_inv_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub26_inv_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub26_inv_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub26_inv_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub26_inv_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub26_inv_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub26_inv_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub26_inv_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub26_inv_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub26_inv_out[0:0] 1'0 + case + assign $1\dec31_dec_sub26_inv_out[0:0] 1'0 + end + sync always + update \dec31_dec_sub26_inv_out $0\dec31_dec_sub26_inv_out[0:0] + end + attribute \src "issuer_ls180.v:96599.3-96650.6" + process $proc$issuer_ls180.v:96599$3904 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub26_cry_out[0:0] $1\dec31_dec_sub26_cry_out[0:0] + attribute \src "issuer_ls180.v:96600.5-96600.29" + switch \initial + attribute \src "issuer_ls180.v:96600.9-96600.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub26_cry_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub26_cry_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub26_cry_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub26_cry_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub26_cry_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub26_cry_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub26_cry_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub26_cry_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub26_cry_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub26_cry_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub26_cry_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub26_cry_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub26_cry_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub26_cry_out[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub26_cry_out[0:0] 1'1 + case + assign $1\dec31_dec_sub26_cry_out[0:0] 1'0 + end + sync always + update \dec31_dec_sub26_cry_out $0\dec31_dec_sub26_cry_out[0:0] + end + attribute \src "issuer_ls180.v:96651.3-96702.6" + process $proc$issuer_ls180.v:96651$3905 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub26_br[0:0] $1\dec31_dec_sub26_br[0:0] + attribute \src "issuer_ls180.v:96652.5-96652.29" + switch \initial + attribute \src "issuer_ls180.v:96652.9-96652.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub26_br[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub26_br[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub26_br[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub26_br[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub26_br[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub26_br[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub26_br[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub26_br[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub26_br[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub26_br[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub26_br[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub26_br[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub26_br[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub26_br[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub26_br[0:0] 1'0 + case + assign $1\dec31_dec_sub26_br[0:0] 1'0 + end + sync always + update \dec31_dec_sub26_br $0\dec31_dec_sub26_br[0:0] + end + attribute \src "issuer_ls180.v:96703.3-96754.6" + process $proc$issuer_ls180.v:96703$3906 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub26_sgn_ext[0:0] $1\dec31_dec_sub26_sgn_ext[0:0] + attribute \src "issuer_ls180.v:96704.5-96704.29" + switch \initial + attribute \src "issuer_ls180.v:96704.9-96704.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub26_sgn_ext[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub26_sgn_ext[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub26_sgn_ext[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub26_sgn_ext[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub26_sgn_ext[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub26_sgn_ext[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub26_sgn_ext[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub26_sgn_ext[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub26_sgn_ext[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub26_sgn_ext[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub26_sgn_ext[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub26_sgn_ext[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub26_sgn_ext[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub26_sgn_ext[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub26_sgn_ext[0:0] 1'0 + case + assign $1\dec31_dec_sub26_sgn_ext[0:0] 1'0 + end + sync always + update \dec31_dec_sub26_sgn_ext $0\dec31_dec_sub26_sgn_ext[0:0] + end + attribute \src "issuer_ls180.v:96755.3-96806.6" + process $proc$issuer_ls180.v:96755$3907 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub26_internal_op[6:0] $1\dec31_dec_sub26_internal_op[6:0] + attribute \src "issuer_ls180.v:96756.5-96756.29" + switch \initial + attribute \src "issuer_ls180.v:96756.9-96756.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub26_internal_op[6:0] 7'0001110 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub26_internal_op[6:0] 7'0001110 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub26_internal_op[6:0] 7'0001110 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub26_internal_op[6:0] 7'0001110 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub26_internal_op[6:0] 7'0011111 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub26_internal_op[6:0] 7'0011111 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub26_internal_op[6:0] 7'0011111 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub26_internal_op[6:0] 7'0100000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub26_internal_op[6:0] 7'0110110 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub26_internal_op[6:0] 7'0110110 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub26_internal_op[6:0] 7'0110110 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub26_internal_op[6:0] 7'0110111 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub26_internal_op[6:0] 7'0110111 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub26_internal_op[6:0] 7'0111101 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub26_internal_op[6:0] 7'0111101 + case + assign $1\dec31_dec_sub26_internal_op[6:0] 7'0000000 + end + sync always + update \dec31_dec_sub26_internal_op $0\dec31_dec_sub26_internal_op[6:0] + end + attribute \src "issuer_ls180.v:96807.3-96858.6" + process $proc$issuer_ls180.v:96807$3908 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub26_rsrv[0:0] $1\dec31_dec_sub26_rsrv[0:0] + attribute \src "issuer_ls180.v:96808.5-96808.29" + switch \initial + attribute \src "issuer_ls180.v:96808.9-96808.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub26_rsrv[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub26_rsrv[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub26_rsrv[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub26_rsrv[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub26_rsrv[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub26_rsrv[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub26_rsrv[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub26_rsrv[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub26_rsrv[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub26_rsrv[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub26_rsrv[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub26_rsrv[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub26_rsrv[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub26_rsrv[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub26_rsrv[0:0] 1'0 + case + assign $1\dec31_dec_sub26_rsrv[0:0] 1'0 + end + sync always + update \dec31_dec_sub26_rsrv $0\dec31_dec_sub26_rsrv[0:0] + end + attribute \src "issuer_ls180.v:96859.3-96910.6" + process $proc$issuer_ls180.v:96859$3909 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub26_is_32b[0:0] $1\dec31_dec_sub26_is_32b[0:0] + attribute \src "issuer_ls180.v:96860.5-96860.29" + switch \initial + attribute \src "issuer_ls180.v:96860.9-96860.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub26_is_32b[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub26_is_32b[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub26_is_32b[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub26_is_32b[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub26_is_32b[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub26_is_32b[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub26_is_32b[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub26_is_32b[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub26_is_32b[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub26_is_32b[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub26_is_32b[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub26_is_32b[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub26_is_32b[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub26_is_32b[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub26_is_32b[0:0] 1'0 + case + assign $1\dec31_dec_sub26_is_32b[0:0] 1'0 + end + sync always + update \dec31_dec_sub26_is_32b $0\dec31_dec_sub26_is_32b[0:0] + end + attribute \src "issuer_ls180.v:96911.3-96962.6" + process $proc$issuer_ls180.v:96911$3910 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub26_sgn[0:0] $1\dec31_dec_sub26_sgn[0:0] + attribute \src "issuer_ls180.v:96912.5-96912.29" + switch \initial + attribute \src "issuer_ls180.v:96912.9-96912.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub26_sgn[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub26_sgn[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub26_sgn[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub26_sgn[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub26_sgn[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub26_sgn[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub26_sgn[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub26_sgn[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub26_sgn[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub26_sgn[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub26_sgn[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub26_sgn[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub26_sgn[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub26_sgn[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub26_sgn[0:0] 1'1 + case + assign $1\dec31_dec_sub26_sgn[0:0] 1'0 + end + sync always + update \dec31_dec_sub26_sgn $0\dec31_dec_sub26_sgn[0:0] + end + attribute \src "issuer_ls180.v:96963.3-97014.6" + process $proc$issuer_ls180.v:96963$3911 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub26_lk[0:0] $1\dec31_dec_sub26_lk[0:0] + attribute \src "issuer_ls180.v:96964.5-96964.29" + switch \initial + attribute \src "issuer_ls180.v:96964.9-96964.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub26_lk[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub26_lk[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub26_lk[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub26_lk[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub26_lk[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub26_lk[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub26_lk[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub26_lk[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub26_lk[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub26_lk[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub26_lk[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub26_lk[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub26_lk[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub26_lk[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub26_lk[0:0] 1'0 + case + assign $1\dec31_dec_sub26_lk[0:0] 1'0 + end + sync always + update \dec31_dec_sub26_lk $0\dec31_dec_sub26_lk[0:0] + end + attribute \src "issuer_ls180.v:97015.3-97066.6" + process $proc$issuer_ls180.v:97015$3912 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub26_sgl_pipe[0:0] $1\dec31_dec_sub26_sgl_pipe[0:0] + attribute \src "issuer_ls180.v:97016.5-97016.29" + switch \initial + attribute \src "issuer_ls180.v:97016.9-97016.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub26_sgl_pipe[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub26_sgl_pipe[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub26_sgl_pipe[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub26_sgl_pipe[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub26_sgl_pipe[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub26_sgl_pipe[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub26_sgl_pipe[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub26_sgl_pipe[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub26_sgl_pipe[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub26_sgl_pipe[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub26_sgl_pipe[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub26_sgl_pipe[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub26_sgl_pipe[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub26_sgl_pipe[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub26_sgl_pipe[0:0] 1'0 + case + assign $1\dec31_dec_sub26_sgl_pipe[0:0] 1'0 + end + sync always + update \dec31_dec_sub26_sgl_pipe $0\dec31_dec_sub26_sgl_pipe[0:0] + end + attribute \src "issuer_ls180.v:97067.3-97118.6" + process $proc$issuer_ls180.v:97067$3913 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub26_form[4:0] $1\dec31_dec_sub26_form[4:0] + attribute \src "issuer_ls180.v:97068.5-97068.29" + switch \initial + attribute \src "issuer_ls180.v:97068.9-97068.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub26_form[4:0] 5'01000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub26_form[4:0] 5'01000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub26_form[4:0] 5'01000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub26_form[4:0] 5'01000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub26_form[4:0] 5'01000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub26_form[4:0] 5'01000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub26_form[4:0] 5'01000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub26_form[4:0] 5'10000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub26_form[4:0] 5'01000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub26_form[4:0] 5'01000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub26_form[4:0] 5'01000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub26_form[4:0] 5'01000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub26_form[4:0] 5'01000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub26_form[4:0] 5'01000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub26_form[4:0] 5'10000 + case + assign $1\dec31_dec_sub26_form[4:0] 5'00000 + end + sync always + update \dec31_dec_sub26_form $0\dec31_dec_sub26_form[4:0] + end + attribute \src "issuer_ls180.v:97119.3-97170.6" + process $proc$issuer_ls180.v:97119$3914 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub26_in1_sel[2:0] $1\dec31_dec_sub26_in1_sel[2:0] + attribute \src "issuer_ls180.v:97120.5-97120.29" + switch \initial + attribute \src "issuer_ls180.v:97120.9-97120.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub26_in1_sel[2:0] 3'100 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub26_in1_sel[2:0] 3'100 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub26_in1_sel[2:0] 3'100 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub26_in1_sel[2:0] 3'100 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub26_in1_sel[2:0] 3'100 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub26_in1_sel[2:0] 3'100 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub26_in1_sel[2:0] 3'100 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub26_in1_sel[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub26_in1_sel[2:0] 3'100 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub26_in1_sel[2:0] 3'100 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub26_in1_sel[2:0] 3'100 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub26_in1_sel[2:0] 3'100 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub26_in1_sel[2:0] 3'100 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub26_in1_sel[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub26_in1_sel[2:0] 3'000 + case + assign $1\dec31_dec_sub26_in1_sel[2:0] 3'000 + end + sync always + update \dec31_dec_sub26_in1_sel $0\dec31_dec_sub26_in1_sel[2:0] + end + attribute \src "issuer_ls180.v:97171.3-97222.6" + process $proc$issuer_ls180.v:97171$3915 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub26_in2_sel[3:0] $1\dec31_dec_sub26_in2_sel[3:0] + attribute \src "issuer_ls180.v:97172.5-97172.29" + switch \initial + attribute \src "issuer_ls180.v:97172.9-97172.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub26_in2_sel[3:0] 4'0000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub26_in2_sel[3:0] 4'0000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub26_in2_sel[3:0] 4'0000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub26_in2_sel[3:0] 4'0000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub26_in2_sel[3:0] 4'0000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub26_in2_sel[3:0] 4'0000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub26_in2_sel[3:0] 4'0000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub26_in2_sel[3:0] 4'1010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub26_in2_sel[3:0] 4'0000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub26_in2_sel[3:0] 4'0000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub26_in2_sel[3:0] 4'0000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub26_in2_sel[3:0] 4'0000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub26_in2_sel[3:0] 4'0000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub26_in2_sel[3:0] 4'0001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub26_in2_sel[3:0] 4'1010 + case + assign $1\dec31_dec_sub26_in2_sel[3:0] 4'0000 + end + sync always + update \dec31_dec_sub26_in2_sel $0\dec31_dec_sub26_in2_sel[3:0] + end + attribute \src "issuer_ls180.v:97223.3-97274.6" + process $proc$issuer_ls180.v:97223$3916 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub26_in3_sel[1:0] $1\dec31_dec_sub26_in3_sel[1:0] + attribute \src "issuer_ls180.v:97224.5-97224.29" + switch \initial + attribute \src "issuer_ls180.v:97224.9-97224.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub26_in3_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub26_in3_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub26_in3_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub26_in3_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub26_in3_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub26_in3_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub26_in3_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub26_in3_sel[1:0] 2'01 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub26_in3_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub26_in3_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub26_in3_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub26_in3_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub26_in3_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub26_in3_sel[1:0] 2'01 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub26_in3_sel[1:0] 2'01 + case + assign $1\dec31_dec_sub26_in3_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub26_in3_sel $0\dec31_dec_sub26_in3_sel[1:0] + end + attribute \src "issuer_ls180.v:97275.3-97326.6" + process $proc$issuer_ls180.v:97275$3917 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub26_out_sel[1:0] $1\dec31_dec_sub26_out_sel[1:0] + attribute \src "issuer_ls180.v:97276.5-97276.29" + switch \initial + attribute \src "issuer_ls180.v:97276.9-97276.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub26_out_sel[1:0] 2'10 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub26_out_sel[1:0] 2'10 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub26_out_sel[1:0] 2'10 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub26_out_sel[1:0] 2'10 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub26_out_sel[1:0] 2'10 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub26_out_sel[1:0] 2'10 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub26_out_sel[1:0] 2'10 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub26_out_sel[1:0] 2'10 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub26_out_sel[1:0] 2'10 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub26_out_sel[1:0] 2'10 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub26_out_sel[1:0] 2'10 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub26_out_sel[1:0] 2'10 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub26_out_sel[1:0] 2'10 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub26_out_sel[1:0] 2'10 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub26_out_sel[1:0] 2'10 + case + assign $1\dec31_dec_sub26_out_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub26_out_sel $0\dec31_dec_sub26_out_sel[1:0] + end + attribute \src "issuer_ls180.v:97327.3-97378.6" + process $proc$issuer_ls180.v:97327$3918 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub26_cr_in[2:0] $1\dec31_dec_sub26_cr_in[2:0] + attribute \src "issuer_ls180.v:97328.5-97328.29" + switch \initial + attribute \src "issuer_ls180.v:97328.9-97328.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub26_cr_in[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub26_cr_in[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub26_cr_in[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub26_cr_in[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub26_cr_in[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub26_cr_in[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub26_cr_in[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub26_cr_in[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub26_cr_in[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub26_cr_in[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub26_cr_in[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub26_cr_in[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub26_cr_in[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub26_cr_in[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub26_cr_in[2:0] 3'000 + case + assign $1\dec31_dec_sub26_cr_in[2:0] 3'000 + end + sync always + update \dec31_dec_sub26_cr_in $0\dec31_dec_sub26_cr_in[2:0] + end + attribute \src "issuer_ls180.v:97379.3-97430.6" + process $proc$issuer_ls180.v:97379$3919 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub26_cr_out[2:0] $1\dec31_dec_sub26_cr_out[2:0] + attribute \src "issuer_ls180.v:97380.5-97380.29" + switch \initial + attribute \src "issuer_ls180.v:97380.9-97380.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub26_cr_out[2:0] 3'001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub26_cr_out[2:0] 3'001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub26_cr_out[2:0] 3'001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub26_cr_out[2:0] 3'001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub26_cr_out[2:0] 3'001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub26_cr_out[2:0] 3'001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub26_cr_out[2:0] 3'001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub26_cr_out[2:0] 3'001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub26_cr_out[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub26_cr_out[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01011 + assign { } { } + assign $1\dec31_dec_sub26_cr_out[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00101 + assign { } { } + assign $1\dec31_dec_sub26_cr_out[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub26_cr_out[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub26_cr_out[2:0] 3'001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub26_cr_out[2:0] 3'001 + case + assign $1\dec31_dec_sub26_cr_out[2:0] 3'000 + end + sync always + update \dec31_dec_sub26_cr_out $0\dec31_dec_sub26_cr_out[2:0] + end + connect \opcode_switch \opcode_in [10:6] +end +attribute \src "issuer_ls180.v:97436.1-98151.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.dec2.dec.dec31.dec31_dec_sub27" +attribute \generator "nMigen" +module \dec31_dec_sub27 + attribute \src "issuer_ls180.v:97789.3-97807.6" + wire width 8 $0\dec31_dec_sub27_asmcode[7:0] + attribute \src "issuer_ls180.v:97865.3-97883.6" + wire $0\dec31_dec_sub27_br[0:0] + attribute \src "issuer_ls180.v:98112.3-98130.6" + wire width 3 $0\dec31_dec_sub27_cr_in[2:0] + attribute \src "issuer_ls180.v:98131.3-98149.6" + wire width 3 $0\dec31_dec_sub27_cr_out[2:0] + attribute \src "issuer_ls180.v:97770.3-97788.6" + wire width 2 $0\dec31_dec_sub27_cry_in[1:0] + attribute \src "issuer_ls180.v:97846.3-97864.6" + wire $0\dec31_dec_sub27_cry_out[0:0] + attribute \src "issuer_ls180.v:98017.3-98035.6" + wire width 5 $0\dec31_dec_sub27_form[4:0] + attribute \src "issuer_ls180.v:97694.3-97712.6" + wire width 12 $0\dec31_dec_sub27_function_unit[11:0] + attribute \src "issuer_ls180.v:98036.3-98054.6" + wire width 3 $0\dec31_dec_sub27_in1_sel[2:0] + attribute \src "issuer_ls180.v:98055.3-98073.6" + wire width 4 $0\dec31_dec_sub27_in2_sel[3:0] + attribute \src "issuer_ls180.v:98074.3-98092.6" + wire width 2 $0\dec31_dec_sub27_in3_sel[1:0] + attribute \src "issuer_ls180.v:97903.3-97921.6" + wire width 7 $0\dec31_dec_sub27_internal_op[6:0] + attribute \src "issuer_ls180.v:97808.3-97826.6" + wire $0\dec31_dec_sub27_inv_a[0:0] + attribute \src "issuer_ls180.v:97827.3-97845.6" + wire $0\dec31_dec_sub27_inv_out[0:0] + attribute \src "issuer_ls180.v:97941.3-97959.6" + wire $0\dec31_dec_sub27_is_32b[0:0] + attribute \src "issuer_ls180.v:97713.3-97731.6" + wire width 4 $0\dec31_dec_sub27_ldst_len[3:0] + attribute \src "issuer_ls180.v:97979.3-97997.6" + wire $0\dec31_dec_sub27_lk[0:0] + attribute \src "issuer_ls180.v:98093.3-98111.6" + wire width 2 $0\dec31_dec_sub27_out_sel[1:0] + attribute \src "issuer_ls180.v:97751.3-97769.6" + wire width 2 $0\dec31_dec_sub27_rc_sel[1:0] + attribute \src "issuer_ls180.v:97922.3-97940.6" + wire $0\dec31_dec_sub27_rsrv[0:0] + attribute \src "issuer_ls180.v:97998.3-98016.6" + wire $0\dec31_dec_sub27_sgl_pipe[0:0] + attribute \src "issuer_ls180.v:97960.3-97978.6" + wire $0\dec31_dec_sub27_sgn[0:0] + attribute \src "issuer_ls180.v:97884.3-97902.6" + wire $0\dec31_dec_sub27_sgn_ext[0:0] + attribute \src "issuer_ls180.v:97732.3-97750.6" + wire width 2 $0\dec31_dec_sub27_upd[1:0] + attribute \src "issuer_ls180.v:97437.7-97437.20" + wire $0\initial[0:0] + attribute \src "issuer_ls180.v:97789.3-97807.6" + wire width 8 $1\dec31_dec_sub27_asmcode[7:0] + attribute \src "issuer_ls180.v:97865.3-97883.6" + wire $1\dec31_dec_sub27_br[0:0] + attribute \src "issuer_ls180.v:98112.3-98130.6" + wire width 3 $1\dec31_dec_sub27_cr_in[2:0] + attribute \src "issuer_ls180.v:98131.3-98149.6" + wire width 3 $1\dec31_dec_sub27_cr_out[2:0] + attribute \src "issuer_ls180.v:97770.3-97788.6" + wire width 2 $1\dec31_dec_sub27_cry_in[1:0] + attribute \src "issuer_ls180.v:97846.3-97864.6" + wire $1\dec31_dec_sub27_cry_out[0:0] + attribute \src "issuer_ls180.v:98017.3-98035.6" + wire width 5 $1\dec31_dec_sub27_form[4:0] + attribute \src "issuer_ls180.v:97694.3-97712.6" + wire width 12 $1\dec31_dec_sub27_function_unit[11:0] + attribute \src "issuer_ls180.v:98036.3-98054.6" + wire width 3 $1\dec31_dec_sub27_in1_sel[2:0] + attribute \src "issuer_ls180.v:98055.3-98073.6" + wire width 4 $1\dec31_dec_sub27_in2_sel[3:0] + attribute \src "issuer_ls180.v:98074.3-98092.6" + wire width 2 $1\dec31_dec_sub27_in3_sel[1:0] + attribute \src "issuer_ls180.v:97903.3-97921.6" + wire width 7 $1\dec31_dec_sub27_internal_op[6:0] + attribute \src "issuer_ls180.v:97808.3-97826.6" + wire $1\dec31_dec_sub27_inv_a[0:0] + attribute \src "issuer_ls180.v:97827.3-97845.6" + wire $1\dec31_dec_sub27_inv_out[0:0] + attribute \src "issuer_ls180.v:97941.3-97959.6" + wire $1\dec31_dec_sub27_is_32b[0:0] + attribute \src "issuer_ls180.v:97713.3-97731.6" + wire width 4 $1\dec31_dec_sub27_ldst_len[3:0] + attribute \src "issuer_ls180.v:97979.3-97997.6" + wire $1\dec31_dec_sub27_lk[0:0] + attribute \src "issuer_ls180.v:98093.3-98111.6" + wire width 2 $1\dec31_dec_sub27_out_sel[1:0] + attribute \src "issuer_ls180.v:97751.3-97769.6" + wire width 2 $1\dec31_dec_sub27_rc_sel[1:0] + attribute \src "issuer_ls180.v:97922.3-97940.6" + wire $1\dec31_dec_sub27_rsrv[0:0] + attribute \src "issuer_ls180.v:97998.3-98016.6" + wire $1\dec31_dec_sub27_sgl_pipe[0:0] + attribute \src "issuer_ls180.v:97960.3-97978.6" + wire $1\dec31_dec_sub27_sgn[0:0] + attribute \src "issuer_ls180.v:97884.3-97902.6" + wire $1\dec31_dec_sub27_sgn_ext[0:0] + attribute \src "issuer_ls180.v:97732.3-97750.6" + wire width 2 $1\dec31_dec_sub27_upd[1:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 8 output 4 \dec31_dec_sub27_asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 18 \dec31_dec_sub27_br + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 9 \dec31_dec_sub27_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 10 \dec31_dec_sub27_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 14 \dec31_dec_sub27_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 17 \dec31_dec_sub27_cry_out + attribute \enum_base_type "Form" + attribute \enum_value_00000 "NONE" + attribute \enum_value_00001 "I" + attribute \enum_value_00010 "B" + attribute \enum_value_00011 "SC" + attribute \enum_value_00100 "D" + attribute \enum_value_00101 "DS" + attribute \enum_value_00110 "DQ" + attribute \enum_value_00111 "DX" + attribute \enum_value_01000 "X" + attribute \enum_value_01001 "XL" + attribute \enum_value_01010 "XFX" + attribute \enum_value_01011 "XFL" + attribute \enum_value_01100 "XX1" + attribute \enum_value_01101 "XX2" + attribute \enum_value_01110 "XX3" + attribute \enum_value_01111 "XX4" + attribute \enum_value_10000 "XS" + attribute \enum_value_10001 "XO" + attribute \enum_value_10010 "A" + attribute \enum_value_10011 "M" + attribute \enum_value_10100 "MD" + attribute \enum_value_10101 "MDS" + attribute \enum_value_10110 "VA" + attribute \enum_value_10111 "VC" + attribute \enum_value_11000 "VX" + attribute \enum_value_11001 "EVX" + attribute \enum_value_11010 "EVS" + attribute \enum_value_11011 "Z22" + attribute \enum_value_11100 "Z23" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 5 output 3 \dec31_dec_sub27_form + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 12 output 1 \dec31_dec_sub27_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 5 \dec31_dec_sub27_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 output 6 \dec31_dec_sub27_in2_sel + attribute \enum_base_type "In3Sel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RS" + attribute \enum_value_10 "RB" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 7 \dec31_dec_sub27_in3_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 7 output 2 \dec31_dec_sub27_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 15 \dec31_dec_sub27_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 16 \dec31_dec_sub27_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 21 \dec31_dec_sub27_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 output 11 \dec31_dec_sub27_ldst_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 23 \dec31_dec_sub27_lk + attribute \enum_base_type "OutSel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RT" + attribute \enum_value_10 "RA" + attribute \enum_value_11 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 8 \dec31_dec_sub27_out_sel + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 13 \dec31_dec_sub27_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 20 \dec31_dec_sub27_rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 24 \dec31_dec_sub27_sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 22 \dec31_dec_sub27_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 19 \dec31_dec_sub27_sgn_ext + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 12 \dec31_dec_sub27_upd + attribute \src "issuer_ls180.v:97437.7-97437.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + wire width 32 input 25 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:320" + wire width 5 \opcode_switch + attribute \src "issuer_ls180.v:97437.7-97437.20" + process $proc$issuer_ls180.v:97437$3945 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "issuer_ls180.v:97694.3-97712.6" + process $proc$issuer_ls180.v:97694$3921 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub27_function_unit[11:0] $1\dec31_dec_sub27_function_unit[11:0] + attribute \src "issuer_ls180.v:97695.5-97695.29" + switch \initial + attribute \src "issuer_ls180.v:97695.9-97695.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub27_function_unit[11:0] 12'000000001000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub27_function_unit[11:0] 12'000000001000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub27_function_unit[11:0] 12'000000001000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub27_function_unit[11:0] 12'000000001000 + case + assign $1\dec31_dec_sub27_function_unit[11:0] 12'000000000000 + end + sync always + update \dec31_dec_sub27_function_unit $0\dec31_dec_sub27_function_unit[11:0] + end + attribute \src "issuer_ls180.v:97713.3-97731.6" + process $proc$issuer_ls180.v:97713$3922 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub27_ldst_len[3:0] $1\dec31_dec_sub27_ldst_len[3:0] + attribute \src "issuer_ls180.v:97714.5-97714.29" + switch \initial + attribute \src "issuer_ls180.v:97714.9-97714.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub27_ldst_len[3:0] 4'0000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub27_ldst_len[3:0] 4'0000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub27_ldst_len[3:0] 4'0000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub27_ldst_len[3:0] 4'0000 + case + assign $1\dec31_dec_sub27_ldst_len[3:0] 4'0000 + end + sync always + update \dec31_dec_sub27_ldst_len $0\dec31_dec_sub27_ldst_len[3:0] + end + attribute \src "issuer_ls180.v:97732.3-97750.6" + process $proc$issuer_ls180.v:97732$3923 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub27_upd[1:0] $1\dec31_dec_sub27_upd[1:0] + attribute \src "issuer_ls180.v:97733.5-97733.29" + switch \initial + attribute \src "issuer_ls180.v:97733.9-97733.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub27_upd[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub27_upd[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub27_upd[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub27_upd[1:0] 2'00 + case + assign $1\dec31_dec_sub27_upd[1:0] 2'00 + end + sync always + update \dec31_dec_sub27_upd $0\dec31_dec_sub27_upd[1:0] + end + attribute \src "issuer_ls180.v:97751.3-97769.6" + process $proc$issuer_ls180.v:97751$3924 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub27_rc_sel[1:0] $1\dec31_dec_sub27_rc_sel[1:0] + attribute \src "issuer_ls180.v:97752.5-97752.29" + switch \initial + attribute \src "issuer_ls180.v:97752.9-97752.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub27_rc_sel[1:0] 2'10 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub27_rc_sel[1:0] 2'10 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub27_rc_sel[1:0] 2'10 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub27_rc_sel[1:0] 2'10 + case + assign $1\dec31_dec_sub27_rc_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub27_rc_sel $0\dec31_dec_sub27_rc_sel[1:0] + end + attribute \src "issuer_ls180.v:97770.3-97788.6" + process $proc$issuer_ls180.v:97770$3925 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub27_cry_in[1:0] $1\dec31_dec_sub27_cry_in[1:0] + attribute \src "issuer_ls180.v:97771.5-97771.29" + switch \initial + attribute \src "issuer_ls180.v:97771.9-97771.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub27_cry_in[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub27_cry_in[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub27_cry_in[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub27_cry_in[1:0] 2'00 + case + assign $1\dec31_dec_sub27_cry_in[1:0] 2'00 + end + sync always + update \dec31_dec_sub27_cry_in $0\dec31_dec_sub27_cry_in[1:0] + end + attribute \src "issuer_ls180.v:97789.3-97807.6" + process $proc$issuer_ls180.v:97789$3926 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub27_asmcode[7:0] $1\dec31_dec_sub27_asmcode[7:0] + attribute \src "issuer_ls180.v:97790.5-97790.29" + switch \initial + attribute \src "issuer_ls180.v:97790.9-97790.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub27_asmcode[7:0] 8'01000111 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub27_asmcode[7:0] 8'10011110 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub27_asmcode[7:0] 8'10100001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub27_asmcode[7:0] 8'10100100 + case + assign $1\dec31_dec_sub27_asmcode[7:0] 8'00000000 + end + sync always + update \dec31_dec_sub27_asmcode $0\dec31_dec_sub27_asmcode[7:0] + end + attribute \src "issuer_ls180.v:97808.3-97826.6" + process $proc$issuer_ls180.v:97808$3927 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub27_inv_a[0:0] $1\dec31_dec_sub27_inv_a[0:0] + attribute \src "issuer_ls180.v:97809.5-97809.29" + switch \initial + attribute \src "issuer_ls180.v:97809.9-97809.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub27_inv_a[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub27_inv_a[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub27_inv_a[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub27_inv_a[0:0] 1'0 + case + assign $1\dec31_dec_sub27_inv_a[0:0] 1'0 + end + sync always + update \dec31_dec_sub27_inv_a $0\dec31_dec_sub27_inv_a[0:0] + end + attribute \src "issuer_ls180.v:97827.3-97845.6" + process $proc$issuer_ls180.v:97827$3928 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub27_inv_out[0:0] $1\dec31_dec_sub27_inv_out[0:0] + attribute \src "issuer_ls180.v:97828.5-97828.29" + switch \initial + attribute \src "issuer_ls180.v:97828.9-97828.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub27_inv_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub27_inv_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub27_inv_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub27_inv_out[0:0] 1'0 + case + assign $1\dec31_dec_sub27_inv_out[0:0] 1'0 + end + sync always + update \dec31_dec_sub27_inv_out $0\dec31_dec_sub27_inv_out[0:0] + end + attribute \src "issuer_ls180.v:97846.3-97864.6" + process $proc$issuer_ls180.v:97846$3929 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub27_cry_out[0:0] $1\dec31_dec_sub27_cry_out[0:0] + attribute \src "issuer_ls180.v:97847.5-97847.29" + switch \initial + attribute \src "issuer_ls180.v:97847.9-97847.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub27_cry_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub27_cry_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub27_cry_out[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub27_cry_out[0:0] 1'0 + case + assign $1\dec31_dec_sub27_cry_out[0:0] 1'0 + end + sync always + update \dec31_dec_sub27_cry_out $0\dec31_dec_sub27_cry_out[0:0] + end + attribute \src "issuer_ls180.v:97865.3-97883.6" + process $proc$issuer_ls180.v:97865$3930 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub27_br[0:0] $1\dec31_dec_sub27_br[0:0] + attribute \src "issuer_ls180.v:97866.5-97866.29" + switch \initial + attribute \src "issuer_ls180.v:97866.9-97866.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub27_br[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub27_br[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub27_br[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub27_br[0:0] 1'0 + case + assign $1\dec31_dec_sub27_br[0:0] 1'0 + end + sync always + update \dec31_dec_sub27_br $0\dec31_dec_sub27_br[0:0] + end + attribute \src "issuer_ls180.v:97884.3-97902.6" + process $proc$issuer_ls180.v:97884$3931 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub27_sgn_ext[0:0] $1\dec31_dec_sub27_sgn_ext[0:0] + attribute \src "issuer_ls180.v:97885.5-97885.29" + switch \initial + attribute \src "issuer_ls180.v:97885.9-97885.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub27_sgn_ext[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub27_sgn_ext[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub27_sgn_ext[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub27_sgn_ext[0:0] 1'0 + case + assign $1\dec31_dec_sub27_sgn_ext[0:0] 1'0 + end + sync always + update \dec31_dec_sub27_sgn_ext $0\dec31_dec_sub27_sgn_ext[0:0] + end + attribute \src "issuer_ls180.v:97903.3-97921.6" + process $proc$issuer_ls180.v:97903$3932 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub27_internal_op[6:0] $1\dec31_dec_sub27_internal_op[6:0] + attribute \src "issuer_ls180.v:97904.5-97904.29" + switch \initial + attribute \src "issuer_ls180.v:97904.9-97904.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub27_internal_op[6:0] 7'0100000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub27_internal_op[6:0] 7'0111100 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub27_internal_op[6:0] 7'0111101 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub27_internal_op[6:0] 7'0111101 + case + assign $1\dec31_dec_sub27_internal_op[6:0] 7'0000000 + end + sync always + update \dec31_dec_sub27_internal_op $0\dec31_dec_sub27_internal_op[6:0] + end + attribute \src "issuer_ls180.v:97922.3-97940.6" + process $proc$issuer_ls180.v:97922$3933 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub27_rsrv[0:0] $1\dec31_dec_sub27_rsrv[0:0] + attribute \src "issuer_ls180.v:97923.5-97923.29" + switch \initial + attribute \src "issuer_ls180.v:97923.9-97923.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub27_rsrv[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub27_rsrv[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub27_rsrv[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub27_rsrv[0:0] 1'0 + case + assign $1\dec31_dec_sub27_rsrv[0:0] 1'0 + end + sync always + update \dec31_dec_sub27_rsrv $0\dec31_dec_sub27_rsrv[0:0] + end + attribute \src "issuer_ls180.v:97941.3-97959.6" + process $proc$issuer_ls180.v:97941$3934 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub27_is_32b[0:0] $1\dec31_dec_sub27_is_32b[0:0] + attribute \src "issuer_ls180.v:97942.5-97942.29" + switch \initial + attribute \src "issuer_ls180.v:97942.9-97942.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub27_is_32b[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub27_is_32b[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub27_is_32b[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub27_is_32b[0:0] 1'0 + case + assign $1\dec31_dec_sub27_is_32b[0:0] 1'0 + end + sync always + update \dec31_dec_sub27_is_32b $0\dec31_dec_sub27_is_32b[0:0] + end + attribute \src "issuer_ls180.v:97960.3-97978.6" + process $proc$issuer_ls180.v:97960$3935 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub27_sgn[0:0] $1\dec31_dec_sub27_sgn[0:0] + attribute \src "issuer_ls180.v:97961.5-97961.29" + switch \initial + attribute \src "issuer_ls180.v:97961.9-97961.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub27_sgn[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub27_sgn[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub27_sgn[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub27_sgn[0:0] 1'0 + case + assign $1\dec31_dec_sub27_sgn[0:0] 1'0 + end + sync always + update \dec31_dec_sub27_sgn $0\dec31_dec_sub27_sgn[0:0] + end + attribute \src "issuer_ls180.v:97979.3-97997.6" + process $proc$issuer_ls180.v:97979$3936 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub27_lk[0:0] $1\dec31_dec_sub27_lk[0:0] + attribute \src "issuer_ls180.v:97980.5-97980.29" + switch \initial + attribute \src "issuer_ls180.v:97980.9-97980.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub27_lk[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub27_lk[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub27_lk[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub27_lk[0:0] 1'0 + case + assign $1\dec31_dec_sub27_lk[0:0] 1'0 + end + sync always + update \dec31_dec_sub27_lk $0\dec31_dec_sub27_lk[0:0] + end + attribute \src "issuer_ls180.v:97998.3-98016.6" + process $proc$issuer_ls180.v:97998$3937 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub27_sgl_pipe[0:0] $1\dec31_dec_sub27_sgl_pipe[0:0] + attribute \src "issuer_ls180.v:97999.5-97999.29" + switch \initial + attribute \src "issuer_ls180.v:97999.9-97999.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub27_sgl_pipe[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub27_sgl_pipe[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub27_sgl_pipe[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub27_sgl_pipe[0:0] 1'0 + case + assign $1\dec31_dec_sub27_sgl_pipe[0:0] 1'0 + end + sync always + update \dec31_dec_sub27_sgl_pipe $0\dec31_dec_sub27_sgl_pipe[0:0] + end + attribute \src "issuer_ls180.v:98017.3-98035.6" + process $proc$issuer_ls180.v:98017$3938 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub27_form[4:0] $1\dec31_dec_sub27_form[4:0] + attribute \src "issuer_ls180.v:98018.5-98018.29" + switch \initial + attribute \src "issuer_ls180.v:98018.9-98018.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub27_form[4:0] 5'10000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub27_form[4:0] 5'01000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub27_form[4:0] 5'10000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub27_form[4:0] 5'01000 + case + assign $1\dec31_dec_sub27_form[4:0] 5'00000 + end + sync always + update \dec31_dec_sub27_form $0\dec31_dec_sub27_form[4:0] + end + attribute \src "issuer_ls180.v:98036.3-98054.6" + process $proc$issuer_ls180.v:98036$3939 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub27_in1_sel[2:0] $1\dec31_dec_sub27_in1_sel[2:0] + attribute \src "issuer_ls180.v:98037.5-98037.29" + switch \initial + attribute \src "issuer_ls180.v:98037.9-98037.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub27_in1_sel[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub27_in1_sel[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub27_in1_sel[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub27_in1_sel[2:0] 3'000 + case + assign $1\dec31_dec_sub27_in1_sel[2:0] 3'000 + end + sync always + update \dec31_dec_sub27_in1_sel $0\dec31_dec_sub27_in1_sel[2:0] + end + attribute \src "issuer_ls180.v:98055.3-98073.6" + process $proc$issuer_ls180.v:98055$3940 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub27_in2_sel[3:0] $1\dec31_dec_sub27_in2_sel[3:0] + attribute \src "issuer_ls180.v:98056.5-98056.29" + switch \initial + attribute \src "issuer_ls180.v:98056.9-98056.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub27_in2_sel[3:0] 4'1010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub27_in2_sel[3:0] 4'0001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub27_in2_sel[3:0] 4'1010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub27_in2_sel[3:0] 4'0001 + case + assign $1\dec31_dec_sub27_in2_sel[3:0] 4'0000 + end + sync always + update \dec31_dec_sub27_in2_sel $0\dec31_dec_sub27_in2_sel[3:0] + end + attribute \src "issuer_ls180.v:98074.3-98092.6" + process $proc$issuer_ls180.v:98074$3941 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub27_in3_sel[1:0] $1\dec31_dec_sub27_in3_sel[1:0] + attribute \src "issuer_ls180.v:98075.5-98075.29" + switch \initial + attribute \src "issuer_ls180.v:98075.9-98075.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub27_in3_sel[1:0] 2'01 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub27_in3_sel[1:0] 2'01 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub27_in3_sel[1:0] 2'01 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub27_in3_sel[1:0] 2'01 + case + assign $1\dec31_dec_sub27_in3_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub27_in3_sel $0\dec31_dec_sub27_in3_sel[1:0] + end + attribute \src "issuer_ls180.v:98093.3-98111.6" + process $proc$issuer_ls180.v:98093$3942 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub27_out_sel[1:0] $1\dec31_dec_sub27_out_sel[1:0] + attribute \src "issuer_ls180.v:98094.5-98094.29" + switch \initial + attribute \src "issuer_ls180.v:98094.9-98094.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub27_out_sel[1:0] 2'10 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub27_out_sel[1:0] 2'10 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub27_out_sel[1:0] 2'10 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub27_out_sel[1:0] 2'10 + case + assign $1\dec31_dec_sub27_out_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub27_out_sel $0\dec31_dec_sub27_out_sel[1:0] + end + attribute \src "issuer_ls180.v:98112.3-98130.6" + process $proc$issuer_ls180.v:98112$3943 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub27_cr_in[2:0] $1\dec31_dec_sub27_cr_in[2:0] + attribute \src "issuer_ls180.v:98113.5-98113.29" + switch \initial + attribute \src "issuer_ls180.v:98113.9-98113.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub27_cr_in[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub27_cr_in[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub27_cr_in[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub27_cr_in[2:0] 3'000 + case + assign $1\dec31_dec_sub27_cr_in[2:0] 3'000 + end + sync always + update \dec31_dec_sub27_cr_in $0\dec31_dec_sub27_cr_in[2:0] + end + attribute \src "issuer_ls180.v:98131.3-98149.6" + process $proc$issuer_ls180.v:98131$3944 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub27_cr_out[2:0] $1\dec31_dec_sub27_cr_out[2:0] + attribute \src "issuer_ls180.v:98132.5-98132.29" + switch \initial + attribute \src "issuer_ls180.v:98132.9-98132.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11011 + assign { } { } + assign $1\dec31_dec_sub27_cr_out[2:0] 3'001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub27_cr_out[2:0] 3'001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11001 + assign { } { } + assign $1\dec31_dec_sub27_cr_out[2:0] 3'001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub27_cr_out[2:0] 3'001 + case + assign $1\dec31_dec_sub27_cr_out[2:0] 3'000 + end + sync always + update \dec31_dec_sub27_cr_out $0\dec31_dec_sub27_cr_out[2:0] + end + connect \opcode_switch \opcode_in [10:6] +end +attribute \src "issuer_ls180.v:98155.1-99302.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.dec2.dec.dec31.dec31_dec_sub28" +attribute \generator "nMigen" +module \dec31_dec_sub28 + attribute \src "issuer_ls180.v:98598.3-98634.6" + wire width 8 $0\dec31_dec_sub28_asmcode[7:0] + attribute \src "issuer_ls180.v:98746.3-98782.6" + wire $0\dec31_dec_sub28_br[0:0] + attribute \src "issuer_ls180.v:99227.3-99263.6" + wire width 3 $0\dec31_dec_sub28_cr_in[2:0] + attribute \src "issuer_ls180.v:99264.3-99300.6" + wire width 3 $0\dec31_dec_sub28_cr_out[2:0] + attribute \src "issuer_ls180.v:98561.3-98597.6" + wire width 2 $0\dec31_dec_sub28_cry_in[1:0] + attribute \src "issuer_ls180.v:98709.3-98745.6" + wire $0\dec31_dec_sub28_cry_out[0:0] + attribute \src "issuer_ls180.v:99042.3-99078.6" + wire width 5 $0\dec31_dec_sub28_form[4:0] + attribute \src "issuer_ls180.v:98413.3-98449.6" + wire width 12 $0\dec31_dec_sub28_function_unit[11:0] + attribute \src "issuer_ls180.v:99079.3-99115.6" + wire width 3 $0\dec31_dec_sub28_in1_sel[2:0] + attribute \src "issuer_ls180.v:99116.3-99152.6" + wire width 4 $0\dec31_dec_sub28_in2_sel[3:0] + attribute \src "issuer_ls180.v:99153.3-99189.6" + wire width 2 $0\dec31_dec_sub28_in3_sel[1:0] + attribute \src "issuer_ls180.v:98820.3-98856.6" + wire width 7 $0\dec31_dec_sub28_internal_op[6:0] + attribute \src "issuer_ls180.v:98635.3-98671.6" + wire $0\dec31_dec_sub28_inv_a[0:0] + attribute \src "issuer_ls180.v:98672.3-98708.6" + wire $0\dec31_dec_sub28_inv_out[0:0] + attribute \src "issuer_ls180.v:98894.3-98930.6" + wire $0\dec31_dec_sub28_is_32b[0:0] + attribute \src "issuer_ls180.v:98450.3-98486.6" + wire width 4 $0\dec31_dec_sub28_ldst_len[3:0] + attribute \src "issuer_ls180.v:98968.3-99004.6" + wire $0\dec31_dec_sub28_lk[0:0] + attribute \src "issuer_ls180.v:99190.3-99226.6" + wire width 2 $0\dec31_dec_sub28_out_sel[1:0] + attribute \src "issuer_ls180.v:98524.3-98560.6" + wire width 2 $0\dec31_dec_sub28_rc_sel[1:0] + attribute \src "issuer_ls180.v:98857.3-98893.6" + wire $0\dec31_dec_sub28_rsrv[0:0] + attribute \src "issuer_ls180.v:99005.3-99041.6" + wire $0\dec31_dec_sub28_sgl_pipe[0:0] + attribute \src "issuer_ls180.v:98931.3-98967.6" + wire $0\dec31_dec_sub28_sgn[0:0] + attribute \src "issuer_ls180.v:98783.3-98819.6" + wire $0\dec31_dec_sub28_sgn_ext[0:0] + attribute \src "issuer_ls180.v:98487.3-98523.6" + wire width 2 $0\dec31_dec_sub28_upd[1:0] + attribute \src "issuer_ls180.v:98156.7-98156.20" + wire $0\initial[0:0] + attribute \src "issuer_ls180.v:98598.3-98634.6" + wire width 8 $1\dec31_dec_sub28_asmcode[7:0] + attribute \src "issuer_ls180.v:98746.3-98782.6" + wire $1\dec31_dec_sub28_br[0:0] + attribute \src "issuer_ls180.v:99227.3-99263.6" + wire width 3 $1\dec31_dec_sub28_cr_in[2:0] + attribute \src "issuer_ls180.v:99264.3-99300.6" + wire width 3 $1\dec31_dec_sub28_cr_out[2:0] + attribute \src "issuer_ls180.v:98561.3-98597.6" + wire width 2 $1\dec31_dec_sub28_cry_in[1:0] + attribute \src "issuer_ls180.v:98709.3-98745.6" + wire $1\dec31_dec_sub28_cry_out[0:0] + attribute \src "issuer_ls180.v:99042.3-99078.6" + wire width 5 $1\dec31_dec_sub28_form[4:0] + attribute \src "issuer_ls180.v:98413.3-98449.6" + wire width 12 $1\dec31_dec_sub28_function_unit[11:0] + attribute \src "issuer_ls180.v:99079.3-99115.6" + wire width 3 $1\dec31_dec_sub28_in1_sel[2:0] + attribute \src "issuer_ls180.v:99116.3-99152.6" + wire width 4 $1\dec31_dec_sub28_in2_sel[3:0] + attribute \src "issuer_ls180.v:99153.3-99189.6" + wire width 2 $1\dec31_dec_sub28_in3_sel[1:0] + attribute \src "issuer_ls180.v:98820.3-98856.6" + wire width 7 $1\dec31_dec_sub28_internal_op[6:0] + attribute \src "issuer_ls180.v:98635.3-98671.6" + wire $1\dec31_dec_sub28_inv_a[0:0] + attribute \src "issuer_ls180.v:98672.3-98708.6" + wire $1\dec31_dec_sub28_inv_out[0:0] + attribute \src "issuer_ls180.v:98894.3-98930.6" + wire $1\dec31_dec_sub28_is_32b[0:0] + attribute \src "issuer_ls180.v:98450.3-98486.6" + wire width 4 $1\dec31_dec_sub28_ldst_len[3:0] + attribute \src "issuer_ls180.v:98968.3-99004.6" + wire $1\dec31_dec_sub28_lk[0:0] + attribute \src "issuer_ls180.v:99190.3-99226.6" + wire width 2 $1\dec31_dec_sub28_out_sel[1:0] + attribute \src "issuer_ls180.v:98524.3-98560.6" + wire width 2 $1\dec31_dec_sub28_rc_sel[1:0] + attribute \src "issuer_ls180.v:98857.3-98893.6" + wire $1\dec31_dec_sub28_rsrv[0:0] + attribute \src "issuer_ls180.v:99005.3-99041.6" + wire $1\dec31_dec_sub28_sgl_pipe[0:0] + attribute \src "issuer_ls180.v:98931.3-98967.6" + wire $1\dec31_dec_sub28_sgn[0:0] + attribute \src "issuer_ls180.v:98783.3-98819.6" + wire $1\dec31_dec_sub28_sgn_ext[0:0] + attribute \src "issuer_ls180.v:98487.3-98523.6" + wire width 2 $1\dec31_dec_sub28_upd[1:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 8 output 4 \dec31_dec_sub28_asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 18 \dec31_dec_sub28_br + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 9 \dec31_dec_sub28_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 10 \dec31_dec_sub28_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 14 \dec31_dec_sub28_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 17 \dec31_dec_sub28_cry_out + attribute \enum_base_type "Form" + attribute \enum_value_00000 "NONE" + attribute \enum_value_00001 "I" + attribute \enum_value_00010 "B" + attribute \enum_value_00011 "SC" + attribute \enum_value_00100 "D" + attribute \enum_value_00101 "DS" + attribute \enum_value_00110 "DQ" + attribute \enum_value_00111 "DX" + attribute \enum_value_01000 "X" + attribute \enum_value_01001 "XL" + attribute \enum_value_01010 "XFX" + attribute \enum_value_01011 "XFL" + attribute \enum_value_01100 "XX1" + attribute \enum_value_01101 "XX2" + attribute \enum_value_01110 "XX3" + attribute \enum_value_01111 "XX4" + attribute \enum_value_10000 "XS" + attribute \enum_value_10001 "XO" + attribute \enum_value_10010 "A" + attribute \enum_value_10011 "M" + attribute \enum_value_10100 "MD" + attribute \enum_value_10101 "MDS" + attribute \enum_value_10110 "VA" + attribute \enum_value_10111 "VC" + attribute \enum_value_11000 "VX" + attribute \enum_value_11001 "EVX" + attribute \enum_value_11010 "EVS" + attribute \enum_value_11011 "Z22" + attribute \enum_value_11100 "Z23" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 5 output 3 \dec31_dec_sub28_form + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 12 output 1 \dec31_dec_sub28_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 5 \dec31_dec_sub28_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 output 6 \dec31_dec_sub28_in2_sel + attribute \enum_base_type "In3Sel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RS" + attribute \enum_value_10 "RB" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 7 \dec31_dec_sub28_in3_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 7 output 2 \dec31_dec_sub28_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 15 \dec31_dec_sub28_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 16 \dec31_dec_sub28_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 21 \dec31_dec_sub28_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 output 11 \dec31_dec_sub28_ldst_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 23 \dec31_dec_sub28_lk + attribute \enum_base_type "OutSel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RT" + attribute \enum_value_10 "RA" + attribute \enum_value_11 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 8 \dec31_dec_sub28_out_sel + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 13 \dec31_dec_sub28_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 20 \dec31_dec_sub28_rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 24 \dec31_dec_sub28_sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 22 \dec31_dec_sub28_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 19 \dec31_dec_sub28_sgn_ext + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 12 \dec31_dec_sub28_upd + attribute \src "issuer_ls180.v:98156.7-98156.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + wire width 32 input 25 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:320" + wire width 5 \opcode_switch + attribute \src "issuer_ls180.v:98156.7-98156.20" + process $proc$issuer_ls180.v:98156$3970 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "issuer_ls180.v:98413.3-98449.6" + process $proc$issuer_ls180.v:98413$3946 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub28_function_unit[11:0] $1\dec31_dec_sub28_function_unit[11:0] + attribute \src "issuer_ls180.v:98414.5-98414.29" + switch \initial + attribute \src "issuer_ls180.v:98414.9-98414.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub28_function_unit[11:0] 12'000000010000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub28_function_unit[11:0] 12'000000010000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub28_function_unit[11:0] 12'000000010000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub28_function_unit[11:0] 12'000000010000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub28_function_unit[11:0] 12'000000010000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub28_function_unit[11:0] 12'000000010000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub28_function_unit[11:0] 12'000000010000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub28_function_unit[11:0] 12'000000010000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub28_function_unit[11:0] 12'000000010000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub28_function_unit[11:0] 12'000000010000 + case + assign $1\dec31_dec_sub28_function_unit[11:0] 12'000000000000 + end + sync always + update \dec31_dec_sub28_function_unit $0\dec31_dec_sub28_function_unit[11:0] + end + attribute \src "issuer_ls180.v:98450.3-98486.6" + process $proc$issuer_ls180.v:98450$3947 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub28_ldst_len[3:0] $1\dec31_dec_sub28_ldst_len[3:0] + attribute \src "issuer_ls180.v:98451.5-98451.29" + switch \initial + attribute \src "issuer_ls180.v:98451.9-98451.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub28_ldst_len[3:0] 4'0000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub28_ldst_len[3:0] 4'0000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub28_ldst_len[3:0] 4'0000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub28_ldst_len[3:0] 4'0000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub28_ldst_len[3:0] 4'0000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub28_ldst_len[3:0] 4'0000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub28_ldst_len[3:0] 4'0000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub28_ldst_len[3:0] 4'0000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub28_ldst_len[3:0] 4'0000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub28_ldst_len[3:0] 4'0000 + case + assign $1\dec31_dec_sub28_ldst_len[3:0] 4'0000 + end + sync always + update \dec31_dec_sub28_ldst_len $0\dec31_dec_sub28_ldst_len[3:0] + end + attribute \src "issuer_ls180.v:98487.3-98523.6" + process $proc$issuer_ls180.v:98487$3948 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub28_upd[1:0] $1\dec31_dec_sub28_upd[1:0] + attribute \src "issuer_ls180.v:98488.5-98488.29" + switch \initial + attribute \src "issuer_ls180.v:98488.9-98488.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub28_upd[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub28_upd[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub28_upd[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub28_upd[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub28_upd[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub28_upd[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub28_upd[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub28_upd[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub28_upd[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub28_upd[1:0] 2'00 + case + assign $1\dec31_dec_sub28_upd[1:0] 2'00 + end + sync always + update \dec31_dec_sub28_upd $0\dec31_dec_sub28_upd[1:0] + end + attribute \src "issuer_ls180.v:98524.3-98560.6" + process $proc$issuer_ls180.v:98524$3949 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub28_rc_sel[1:0] $1\dec31_dec_sub28_rc_sel[1:0] + attribute \src "issuer_ls180.v:98525.5-98525.29" + switch \initial + attribute \src "issuer_ls180.v:98525.9-98525.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub28_rc_sel[1:0] 2'10 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub28_rc_sel[1:0] 2'10 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub28_rc_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub28_rc_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub28_rc_sel[1:0] 2'10 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub28_rc_sel[1:0] 2'10 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub28_rc_sel[1:0] 2'10 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub28_rc_sel[1:0] 2'10 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub28_rc_sel[1:0] 2'10 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub28_rc_sel[1:0] 2'10 + case + assign $1\dec31_dec_sub28_rc_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub28_rc_sel $0\dec31_dec_sub28_rc_sel[1:0] + end + attribute \src "issuer_ls180.v:98561.3-98597.6" + process $proc$issuer_ls180.v:98561$3950 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub28_cry_in[1:0] $1\dec31_dec_sub28_cry_in[1:0] + attribute \src "issuer_ls180.v:98562.5-98562.29" + switch \initial + attribute \src "issuer_ls180.v:98562.9-98562.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub28_cry_in[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub28_cry_in[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub28_cry_in[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub28_cry_in[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub28_cry_in[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub28_cry_in[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub28_cry_in[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub28_cry_in[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub28_cry_in[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub28_cry_in[1:0] 2'00 + case + assign $1\dec31_dec_sub28_cry_in[1:0] 2'00 + end + sync always + update \dec31_dec_sub28_cry_in $0\dec31_dec_sub28_cry_in[1:0] + end + attribute \src "issuer_ls180.v:98598.3-98634.6" + process $proc$issuer_ls180.v:98598$3951 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub28_asmcode[7:0] $1\dec31_dec_sub28_asmcode[7:0] + attribute \src "issuer_ls180.v:98599.5-98599.29" + switch \initial + attribute \src "issuer_ls180.v:98599.9-98599.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub28_asmcode[7:0] 8'00001111 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub28_asmcode[7:0] 8'00010000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub28_asmcode[7:0] 8'00011001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub28_asmcode[7:0] 8'00011011 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub28_asmcode[7:0] 8'01000011 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub28_asmcode[7:0] 8'10000011 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub28_asmcode[7:0] 8'10000111 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub28_asmcode[7:0] 8'10001000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub28_asmcode[7:0] 8'10001001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub28_asmcode[7:0] 8'11010000 + case + assign $1\dec31_dec_sub28_asmcode[7:0] 8'00000000 + end + sync always + update \dec31_dec_sub28_asmcode $0\dec31_dec_sub28_asmcode[7:0] + end + attribute \src "issuer_ls180.v:98635.3-98671.6" + process $proc$issuer_ls180.v:98635$3952 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub28_inv_a[0:0] $1\dec31_dec_sub28_inv_a[0:0] + attribute \src "issuer_ls180.v:98636.5-98636.29" + switch \initial + attribute \src "issuer_ls180.v:98636.9-98636.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub28_inv_a[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub28_inv_a[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub28_inv_a[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub28_inv_a[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub28_inv_a[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub28_inv_a[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub28_inv_a[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub28_inv_a[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub28_inv_a[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub28_inv_a[0:0] 1'0 + case + assign $1\dec31_dec_sub28_inv_a[0:0] 1'0 + end + sync always + update \dec31_dec_sub28_inv_a $0\dec31_dec_sub28_inv_a[0:0] + end + attribute \src "issuer_ls180.v:98672.3-98708.6" + process $proc$issuer_ls180.v:98672$3953 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub28_inv_out[0:0] $1\dec31_dec_sub28_inv_out[0:0] + attribute \src "issuer_ls180.v:98673.5-98673.29" + switch \initial + attribute \src "issuer_ls180.v:98673.9-98673.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub28_inv_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub28_inv_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub28_inv_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub28_inv_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub28_inv_out[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub28_inv_out[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub28_inv_out[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub28_inv_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub28_inv_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub28_inv_out[0:0] 1'0 + case + assign $1\dec31_dec_sub28_inv_out[0:0] 1'0 + end + sync always + update \dec31_dec_sub28_inv_out $0\dec31_dec_sub28_inv_out[0:0] + end + attribute \src "issuer_ls180.v:98709.3-98745.6" + process $proc$issuer_ls180.v:98709$3954 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub28_cry_out[0:0] $1\dec31_dec_sub28_cry_out[0:0] + attribute \src "issuer_ls180.v:98710.5-98710.29" + switch \initial + attribute \src "issuer_ls180.v:98710.9-98710.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub28_cry_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub28_cry_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub28_cry_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub28_cry_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub28_cry_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub28_cry_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub28_cry_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub28_cry_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub28_cry_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub28_cry_out[0:0] 1'0 + case + assign $1\dec31_dec_sub28_cry_out[0:0] 1'0 + end + sync always + update \dec31_dec_sub28_cry_out $0\dec31_dec_sub28_cry_out[0:0] + end + attribute \src "issuer_ls180.v:98746.3-98782.6" + process $proc$issuer_ls180.v:98746$3955 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub28_br[0:0] $1\dec31_dec_sub28_br[0:0] + attribute \src "issuer_ls180.v:98747.5-98747.29" + switch \initial + attribute \src "issuer_ls180.v:98747.9-98747.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub28_br[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub28_br[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub28_br[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub28_br[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub28_br[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub28_br[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub28_br[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub28_br[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub28_br[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub28_br[0:0] 1'0 + case + assign $1\dec31_dec_sub28_br[0:0] 1'0 + end + sync always + update \dec31_dec_sub28_br $0\dec31_dec_sub28_br[0:0] + end + attribute \src "issuer_ls180.v:98783.3-98819.6" + process $proc$issuer_ls180.v:98783$3956 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub28_sgn_ext[0:0] $1\dec31_dec_sub28_sgn_ext[0:0] + attribute \src "issuer_ls180.v:98784.5-98784.29" + switch \initial + attribute \src "issuer_ls180.v:98784.9-98784.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub28_sgn_ext[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub28_sgn_ext[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub28_sgn_ext[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub28_sgn_ext[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub28_sgn_ext[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub28_sgn_ext[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub28_sgn_ext[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub28_sgn_ext[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub28_sgn_ext[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub28_sgn_ext[0:0] 1'0 + case + assign $1\dec31_dec_sub28_sgn_ext[0:0] 1'0 + end + sync always + update \dec31_dec_sub28_sgn_ext $0\dec31_dec_sub28_sgn_ext[0:0] + end + attribute \src "issuer_ls180.v:98820.3-98856.6" + process $proc$issuer_ls180.v:98820$3957 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub28_internal_op[6:0] $1\dec31_dec_sub28_internal_op[6:0] + attribute \src "issuer_ls180.v:98821.5-98821.29" + switch \initial + attribute \src "issuer_ls180.v:98821.9-98821.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub28_internal_op[6:0] 7'0000100 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub28_internal_op[6:0] 7'0000100 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub28_internal_op[6:0] 7'0001001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub28_internal_op[6:0] 7'0001011 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub28_internal_op[6:0] 7'1000011 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub28_internal_op[6:0] 7'0000100 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub28_internal_op[6:0] 7'0110101 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub28_internal_op[6:0] 7'0110101 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub28_internal_op[6:0] 7'0110101 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub28_internal_op[6:0] 7'1000011 + case + assign $1\dec31_dec_sub28_internal_op[6:0] 7'0000000 + end + sync always + update \dec31_dec_sub28_internal_op $0\dec31_dec_sub28_internal_op[6:0] + end + attribute \src "issuer_ls180.v:98857.3-98893.6" + process $proc$issuer_ls180.v:98857$3958 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub28_rsrv[0:0] $1\dec31_dec_sub28_rsrv[0:0] + attribute \src "issuer_ls180.v:98858.5-98858.29" + switch \initial + attribute \src "issuer_ls180.v:98858.9-98858.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub28_rsrv[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub28_rsrv[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub28_rsrv[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub28_rsrv[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub28_rsrv[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub28_rsrv[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub28_rsrv[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub28_rsrv[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub28_rsrv[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub28_rsrv[0:0] 1'0 + case + assign $1\dec31_dec_sub28_rsrv[0:0] 1'0 + end + sync always + update \dec31_dec_sub28_rsrv $0\dec31_dec_sub28_rsrv[0:0] + end + attribute \src "issuer_ls180.v:98894.3-98930.6" + process $proc$issuer_ls180.v:98894$3959 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub28_is_32b[0:0] $1\dec31_dec_sub28_is_32b[0:0] + attribute \src "issuer_ls180.v:98895.5-98895.29" + switch \initial + attribute \src "issuer_ls180.v:98895.9-98895.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub28_is_32b[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub28_is_32b[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub28_is_32b[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub28_is_32b[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub28_is_32b[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub28_is_32b[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub28_is_32b[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub28_is_32b[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub28_is_32b[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub28_is_32b[0:0] 1'0 + case + assign $1\dec31_dec_sub28_is_32b[0:0] 1'0 + end + sync always + update \dec31_dec_sub28_is_32b $0\dec31_dec_sub28_is_32b[0:0] + end + attribute \src "issuer_ls180.v:98931.3-98967.6" + process $proc$issuer_ls180.v:98931$3960 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub28_sgn[0:0] $1\dec31_dec_sub28_sgn[0:0] + attribute \src "issuer_ls180.v:98932.5-98932.29" + switch \initial + attribute \src "issuer_ls180.v:98932.9-98932.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub28_sgn[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub28_sgn[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub28_sgn[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub28_sgn[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub28_sgn[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub28_sgn[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub28_sgn[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub28_sgn[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub28_sgn[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub28_sgn[0:0] 1'0 + case + assign $1\dec31_dec_sub28_sgn[0:0] 1'0 + end + sync always + update \dec31_dec_sub28_sgn $0\dec31_dec_sub28_sgn[0:0] + end + attribute \src "issuer_ls180.v:98968.3-99004.6" + process $proc$issuer_ls180.v:98968$3961 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub28_lk[0:0] $1\dec31_dec_sub28_lk[0:0] + attribute \src "issuer_ls180.v:98969.5-98969.29" + switch \initial + attribute \src "issuer_ls180.v:98969.9-98969.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub28_lk[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub28_lk[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub28_lk[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub28_lk[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub28_lk[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub28_lk[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub28_lk[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub28_lk[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub28_lk[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub28_lk[0:0] 1'0 + case + assign $1\dec31_dec_sub28_lk[0:0] 1'0 + end + sync always + update \dec31_dec_sub28_lk $0\dec31_dec_sub28_lk[0:0] + end + attribute \src "issuer_ls180.v:99005.3-99041.6" + process $proc$issuer_ls180.v:99005$3962 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub28_sgl_pipe[0:0] $1\dec31_dec_sub28_sgl_pipe[0:0] + attribute \src "issuer_ls180.v:99006.5-99006.29" + switch \initial + attribute \src "issuer_ls180.v:99006.9-99006.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub28_sgl_pipe[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub28_sgl_pipe[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub28_sgl_pipe[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub28_sgl_pipe[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub28_sgl_pipe[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub28_sgl_pipe[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub28_sgl_pipe[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub28_sgl_pipe[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub28_sgl_pipe[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub28_sgl_pipe[0:0] 1'0 + case + assign $1\dec31_dec_sub28_sgl_pipe[0:0] 1'0 + end + sync always + update \dec31_dec_sub28_sgl_pipe $0\dec31_dec_sub28_sgl_pipe[0:0] + end + attribute \src "issuer_ls180.v:99042.3-99078.6" + process $proc$issuer_ls180.v:99042$3963 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub28_form[4:0] $1\dec31_dec_sub28_form[4:0] + attribute \src "issuer_ls180.v:99043.5-99043.29" + switch \initial + attribute \src "issuer_ls180.v:99043.9-99043.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub28_form[4:0] 5'01000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub28_form[4:0] 5'01000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub28_form[4:0] 5'01000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub28_form[4:0] 5'01000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub28_form[4:0] 5'01000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub28_form[4:0] 5'01000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub28_form[4:0] 5'01000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub28_form[4:0] 5'01000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub28_form[4:0] 5'01000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub28_form[4:0] 5'01000 + case + assign $1\dec31_dec_sub28_form[4:0] 5'00000 + end + sync always + update \dec31_dec_sub28_form $0\dec31_dec_sub28_form[4:0] + end + attribute \src "issuer_ls180.v:99079.3-99115.6" + process $proc$issuer_ls180.v:99079$3964 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub28_in1_sel[2:0] $1\dec31_dec_sub28_in1_sel[2:0] + attribute \src "issuer_ls180.v:99080.5-99080.29" + switch \initial + attribute \src "issuer_ls180.v:99080.9-99080.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub28_in1_sel[2:0] 3'100 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub28_in1_sel[2:0] 3'100 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub28_in1_sel[2:0] 3'100 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub28_in1_sel[2:0] 3'100 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub28_in1_sel[2:0] 3'100 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub28_in1_sel[2:0] 3'100 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub28_in1_sel[2:0] 3'100 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub28_in1_sel[2:0] 3'100 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub28_in1_sel[2:0] 3'100 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub28_in1_sel[2:0] 3'100 + case + assign $1\dec31_dec_sub28_in1_sel[2:0] 3'000 + end + sync always + update \dec31_dec_sub28_in1_sel $0\dec31_dec_sub28_in1_sel[2:0] + end + attribute \src "issuer_ls180.v:99116.3-99152.6" + process $proc$issuer_ls180.v:99116$3965 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub28_in2_sel[3:0] $1\dec31_dec_sub28_in2_sel[3:0] + attribute \src "issuer_ls180.v:99117.5-99117.29" + switch \initial + attribute \src "issuer_ls180.v:99117.9-99117.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub28_in2_sel[3:0] 4'0001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub28_in2_sel[3:0] 4'0001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub28_in2_sel[3:0] 4'0001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub28_in2_sel[3:0] 4'0001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub28_in2_sel[3:0] 4'0001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub28_in2_sel[3:0] 4'0001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub28_in2_sel[3:0] 4'0001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub28_in2_sel[3:0] 4'0001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub28_in2_sel[3:0] 4'0001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub28_in2_sel[3:0] 4'0001 + case + assign $1\dec31_dec_sub28_in2_sel[3:0] 4'0000 + end + sync always + update \dec31_dec_sub28_in2_sel $0\dec31_dec_sub28_in2_sel[3:0] + end + attribute \src "issuer_ls180.v:99153.3-99189.6" + process $proc$issuer_ls180.v:99153$3966 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub28_in3_sel[1:0] $1\dec31_dec_sub28_in3_sel[1:0] + attribute \src "issuer_ls180.v:99154.5-99154.29" + switch \initial + attribute \src "issuer_ls180.v:99154.9-99154.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub28_in3_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub28_in3_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub28_in3_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub28_in3_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub28_in3_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub28_in3_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub28_in3_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub28_in3_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub28_in3_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub28_in3_sel[1:0] 2'00 + case + assign $1\dec31_dec_sub28_in3_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub28_in3_sel $0\dec31_dec_sub28_in3_sel[1:0] + end + attribute \src "issuer_ls180.v:99190.3-99226.6" + process $proc$issuer_ls180.v:99190$3967 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub28_out_sel[1:0] $1\dec31_dec_sub28_out_sel[1:0] + attribute \src "issuer_ls180.v:99191.5-99191.29" + switch \initial + attribute \src "issuer_ls180.v:99191.9-99191.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub28_out_sel[1:0] 2'10 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub28_out_sel[1:0] 2'10 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub28_out_sel[1:0] 2'10 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub28_out_sel[1:0] 2'10 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub28_out_sel[1:0] 2'10 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub28_out_sel[1:0] 2'10 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub28_out_sel[1:0] 2'10 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub28_out_sel[1:0] 2'10 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub28_out_sel[1:0] 2'10 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub28_out_sel[1:0] 2'10 + case + assign $1\dec31_dec_sub28_out_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub28_out_sel $0\dec31_dec_sub28_out_sel[1:0] + end + attribute \src "issuer_ls180.v:99227.3-99263.6" + process $proc$issuer_ls180.v:99227$3968 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub28_cr_in[2:0] $1\dec31_dec_sub28_cr_in[2:0] + attribute \src "issuer_ls180.v:99228.5-99228.29" + switch \initial + attribute \src "issuer_ls180.v:99228.9-99228.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub28_cr_in[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub28_cr_in[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub28_cr_in[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub28_cr_in[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub28_cr_in[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub28_cr_in[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub28_cr_in[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub28_cr_in[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub28_cr_in[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub28_cr_in[2:0] 3'000 + case + assign $1\dec31_dec_sub28_cr_in[2:0] 3'000 + end + sync always + update \dec31_dec_sub28_cr_in $0\dec31_dec_sub28_cr_in[2:0] + end + attribute \src "issuer_ls180.v:99264.3-99300.6" + process $proc$issuer_ls180.v:99264$3969 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub28_cr_out[2:0] $1\dec31_dec_sub28_cr_out[2:0] + attribute \src "issuer_ls180.v:99265.5-99265.29" + switch \initial + attribute \src "issuer_ls180.v:99265.9-99265.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub28_cr_out[2:0] 3'001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub28_cr_out[2:0] 3'001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub28_cr_out[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub28_cr_out[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub28_cr_out[2:0] 3'001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub28_cr_out[2:0] 3'001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub28_cr_out[2:0] 3'001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub28_cr_out[2:0] 3'001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub28_cr_out[2:0] 3'001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01001 + assign { } { } + assign $1\dec31_dec_sub28_cr_out[2:0] 3'001 + case + assign $1\dec31_dec_sub28_cr_out[2:0] 3'000 + end + sync always + update \dec31_dec_sub28_cr_out $0\dec31_dec_sub28_cr_out[2:0] + end + connect \opcode_switch \opcode_in [10:6] +end +attribute \src "issuer_ls180.v:99306.1-99877.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.dec2.dec.dec31.dec31_dec_sub4" +attribute \generator "nMigen" +module \dec31_dec_sub4 + attribute \src "issuer_ls180.v:99629.3-99641.6" + wire width 8 $0\dec31_dec_sub4_asmcode[7:0] + attribute \src "issuer_ls180.v:99681.3-99693.6" + wire $0\dec31_dec_sub4_br[0:0] + attribute \src "issuer_ls180.v:99850.3-99862.6" + wire width 3 $0\dec31_dec_sub4_cr_in[2:0] + attribute \src "issuer_ls180.v:99863.3-99875.6" + wire width 3 $0\dec31_dec_sub4_cr_out[2:0] + attribute \src "issuer_ls180.v:99616.3-99628.6" + wire width 2 $0\dec31_dec_sub4_cry_in[1:0] + attribute \src "issuer_ls180.v:99668.3-99680.6" + wire $0\dec31_dec_sub4_cry_out[0:0] + attribute \src "issuer_ls180.v:99785.3-99797.6" + wire width 5 $0\dec31_dec_sub4_form[4:0] + attribute \src "issuer_ls180.v:99564.3-99576.6" + wire width 12 $0\dec31_dec_sub4_function_unit[11:0] + attribute \src "issuer_ls180.v:99798.3-99810.6" + wire width 3 $0\dec31_dec_sub4_in1_sel[2:0] + attribute \src "issuer_ls180.v:99811.3-99823.6" + wire width 4 $0\dec31_dec_sub4_in2_sel[3:0] + attribute \src "issuer_ls180.v:99824.3-99836.6" + wire width 2 $0\dec31_dec_sub4_in3_sel[1:0] + attribute \src "issuer_ls180.v:99707.3-99719.6" + wire width 7 $0\dec31_dec_sub4_internal_op[6:0] + attribute \src "issuer_ls180.v:99642.3-99654.6" + wire $0\dec31_dec_sub4_inv_a[0:0] + attribute \src "issuer_ls180.v:99655.3-99667.6" + wire $0\dec31_dec_sub4_inv_out[0:0] + attribute \src "issuer_ls180.v:99733.3-99745.6" + wire $0\dec31_dec_sub4_is_32b[0:0] + attribute \src "issuer_ls180.v:99577.3-99589.6" + wire width 4 $0\dec31_dec_sub4_ldst_len[3:0] + attribute \src "issuer_ls180.v:99759.3-99771.6" + wire $0\dec31_dec_sub4_lk[0:0] + attribute \src "issuer_ls180.v:99837.3-99849.6" + wire width 2 $0\dec31_dec_sub4_out_sel[1:0] + attribute \src "issuer_ls180.v:99603.3-99615.6" + wire width 2 $0\dec31_dec_sub4_rc_sel[1:0] + attribute \src "issuer_ls180.v:99720.3-99732.6" + wire $0\dec31_dec_sub4_rsrv[0:0] + attribute \src "issuer_ls180.v:99772.3-99784.6" + wire $0\dec31_dec_sub4_sgl_pipe[0:0] + attribute \src "issuer_ls180.v:99746.3-99758.6" + wire $0\dec31_dec_sub4_sgn[0:0] + attribute \src "issuer_ls180.v:99694.3-99706.6" + wire $0\dec31_dec_sub4_sgn_ext[0:0] + attribute \src "issuer_ls180.v:99590.3-99602.6" + wire width 2 $0\dec31_dec_sub4_upd[1:0] + attribute \src "issuer_ls180.v:99307.7-99307.20" + wire $0\initial[0:0] + attribute \src "issuer_ls180.v:99629.3-99641.6" + wire width 8 $1\dec31_dec_sub4_asmcode[7:0] + attribute \src "issuer_ls180.v:99681.3-99693.6" + wire $1\dec31_dec_sub4_br[0:0] + attribute \src "issuer_ls180.v:99850.3-99862.6" + wire width 3 $1\dec31_dec_sub4_cr_in[2:0] + attribute \src "issuer_ls180.v:99863.3-99875.6" + wire width 3 $1\dec31_dec_sub4_cr_out[2:0] + attribute \src "issuer_ls180.v:99616.3-99628.6" + wire width 2 $1\dec31_dec_sub4_cry_in[1:0] + attribute \src "issuer_ls180.v:99668.3-99680.6" + wire $1\dec31_dec_sub4_cry_out[0:0] + attribute \src "issuer_ls180.v:99785.3-99797.6" + wire width 5 $1\dec31_dec_sub4_form[4:0] + attribute \src "issuer_ls180.v:99564.3-99576.6" + wire width 12 $1\dec31_dec_sub4_function_unit[11:0] + attribute \src "issuer_ls180.v:99798.3-99810.6" + wire width 3 $1\dec31_dec_sub4_in1_sel[2:0] + attribute \src "issuer_ls180.v:99811.3-99823.6" + wire width 4 $1\dec31_dec_sub4_in2_sel[3:0] + attribute \src "issuer_ls180.v:99824.3-99836.6" + wire width 2 $1\dec31_dec_sub4_in3_sel[1:0] + attribute \src "issuer_ls180.v:99707.3-99719.6" + wire width 7 $1\dec31_dec_sub4_internal_op[6:0] + attribute \src "issuer_ls180.v:99642.3-99654.6" + wire $1\dec31_dec_sub4_inv_a[0:0] + attribute \src "issuer_ls180.v:99655.3-99667.6" + wire $1\dec31_dec_sub4_inv_out[0:0] + attribute \src "issuer_ls180.v:99733.3-99745.6" + wire $1\dec31_dec_sub4_is_32b[0:0] + attribute \src "issuer_ls180.v:99577.3-99589.6" + wire width 4 $1\dec31_dec_sub4_ldst_len[3:0] + attribute \src "issuer_ls180.v:99759.3-99771.6" + wire $1\dec31_dec_sub4_lk[0:0] + attribute \src "issuer_ls180.v:99837.3-99849.6" + wire width 2 $1\dec31_dec_sub4_out_sel[1:0] + attribute \src "issuer_ls180.v:99603.3-99615.6" + wire width 2 $1\dec31_dec_sub4_rc_sel[1:0] + attribute \src "issuer_ls180.v:99720.3-99732.6" + wire $1\dec31_dec_sub4_rsrv[0:0] + attribute \src "issuer_ls180.v:99772.3-99784.6" + wire $1\dec31_dec_sub4_sgl_pipe[0:0] + attribute \src "issuer_ls180.v:99746.3-99758.6" + wire $1\dec31_dec_sub4_sgn[0:0] + attribute \src "issuer_ls180.v:99694.3-99706.6" + wire $1\dec31_dec_sub4_sgn_ext[0:0] + attribute \src "issuer_ls180.v:99590.3-99602.6" + wire width 2 $1\dec31_dec_sub4_upd[1:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 8 output 4 \dec31_dec_sub4_asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 18 \dec31_dec_sub4_br + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 9 \dec31_dec_sub4_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 10 \dec31_dec_sub4_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 14 \dec31_dec_sub4_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 17 \dec31_dec_sub4_cry_out + attribute \enum_base_type "Form" + attribute \enum_value_00000 "NONE" + attribute \enum_value_00001 "I" + attribute \enum_value_00010 "B" + attribute \enum_value_00011 "SC" + attribute \enum_value_00100 "D" + attribute \enum_value_00101 "DS" + attribute \enum_value_00110 "DQ" + attribute \enum_value_00111 "DX" + attribute \enum_value_01000 "X" + attribute \enum_value_01001 "XL" + attribute \enum_value_01010 "XFX" + attribute \enum_value_01011 "XFL" + attribute \enum_value_01100 "XX1" + attribute \enum_value_01101 "XX2" + attribute \enum_value_01110 "XX3" + attribute \enum_value_01111 "XX4" + attribute \enum_value_10000 "XS" + attribute \enum_value_10001 "XO" + attribute \enum_value_10010 "A" + attribute \enum_value_10011 "M" + attribute \enum_value_10100 "MD" + attribute \enum_value_10101 "MDS" + attribute \enum_value_10110 "VA" + attribute \enum_value_10111 "VC" + attribute \enum_value_11000 "VX" + attribute \enum_value_11001 "EVX" + attribute \enum_value_11010 "EVS" + attribute \enum_value_11011 "Z22" + attribute \enum_value_11100 "Z23" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 5 output 3 \dec31_dec_sub4_form + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 12 output 1 \dec31_dec_sub4_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 5 \dec31_dec_sub4_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 output 6 \dec31_dec_sub4_in2_sel + attribute \enum_base_type "In3Sel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RS" + attribute \enum_value_10 "RB" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 7 \dec31_dec_sub4_in3_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 7 output 2 \dec31_dec_sub4_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 15 \dec31_dec_sub4_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 16 \dec31_dec_sub4_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 21 \dec31_dec_sub4_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 output 11 \dec31_dec_sub4_ldst_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 23 \dec31_dec_sub4_lk + attribute \enum_base_type "OutSel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RT" + attribute \enum_value_10 "RA" + attribute \enum_value_11 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 8 \dec31_dec_sub4_out_sel + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 13 \dec31_dec_sub4_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 20 \dec31_dec_sub4_rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 24 \dec31_dec_sub4_sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 22 \dec31_dec_sub4_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 19 \dec31_dec_sub4_sgn_ext + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 12 \dec31_dec_sub4_upd + attribute \src "issuer_ls180.v:99307.7-99307.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + wire width 32 input 25 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:320" + wire width 5 \opcode_switch + attribute \src "issuer_ls180.v:99307.7-99307.20" + process $proc$issuer_ls180.v:99307$3995 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "issuer_ls180.v:99564.3-99576.6" + process $proc$issuer_ls180.v:99564$3971 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub4_function_unit[11:0] $1\dec31_dec_sub4_function_unit[11:0] + attribute \src "issuer_ls180.v:99565.5-99565.29" + switch \initial + attribute \src "issuer_ls180.v:99565.9-99565.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub4_function_unit[11:0] 12'000010000000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub4_function_unit[11:0] 12'000010000000 + case + assign $1\dec31_dec_sub4_function_unit[11:0] 12'000000000000 + end + sync always + update \dec31_dec_sub4_function_unit $0\dec31_dec_sub4_function_unit[11:0] + end + attribute \src "issuer_ls180.v:99577.3-99589.6" + process $proc$issuer_ls180.v:99577$3972 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub4_ldst_len[3:0] $1\dec31_dec_sub4_ldst_len[3:0] + attribute \src "issuer_ls180.v:99578.5-99578.29" + switch \initial + attribute \src "issuer_ls180.v:99578.9-99578.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub4_ldst_len[3:0] 4'0000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub4_ldst_len[3:0] 4'0000 + case + assign $1\dec31_dec_sub4_ldst_len[3:0] 4'0000 + end + sync always + update \dec31_dec_sub4_ldst_len $0\dec31_dec_sub4_ldst_len[3:0] + end + attribute \src "issuer_ls180.v:99590.3-99602.6" + process $proc$issuer_ls180.v:99590$3973 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub4_upd[1:0] $1\dec31_dec_sub4_upd[1:0] + attribute \src "issuer_ls180.v:99591.5-99591.29" + switch \initial + attribute \src "issuer_ls180.v:99591.9-99591.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub4_upd[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub4_upd[1:0] 2'00 + case + assign $1\dec31_dec_sub4_upd[1:0] 2'00 + end + sync always + update \dec31_dec_sub4_upd $0\dec31_dec_sub4_upd[1:0] + end + attribute \src "issuer_ls180.v:99603.3-99615.6" + process $proc$issuer_ls180.v:99603$3974 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub4_rc_sel[1:0] $1\dec31_dec_sub4_rc_sel[1:0] + attribute \src "issuer_ls180.v:99604.5-99604.29" + switch \initial + attribute \src "issuer_ls180.v:99604.9-99604.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub4_rc_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub4_rc_sel[1:0] 2'00 + case + assign $1\dec31_dec_sub4_rc_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub4_rc_sel $0\dec31_dec_sub4_rc_sel[1:0] + end + attribute \src "issuer_ls180.v:99616.3-99628.6" + process $proc$issuer_ls180.v:99616$3975 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub4_cry_in[1:0] $1\dec31_dec_sub4_cry_in[1:0] + attribute \src "issuer_ls180.v:99617.5-99617.29" + switch \initial + attribute \src "issuer_ls180.v:99617.9-99617.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub4_cry_in[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub4_cry_in[1:0] 2'00 + case + assign $1\dec31_dec_sub4_cry_in[1:0] 2'00 + end + sync always + update \dec31_dec_sub4_cry_in $0\dec31_dec_sub4_cry_in[1:0] + end + attribute \src "issuer_ls180.v:99629.3-99641.6" + process $proc$issuer_ls180.v:99629$3976 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub4_asmcode[7:0] $1\dec31_dec_sub4_asmcode[7:0] + attribute \src "issuer_ls180.v:99630.5-99630.29" + switch \initial + attribute \src "issuer_ls180.v:99630.9-99630.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub4_asmcode[7:0] 8'11001010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub4_asmcode[7:0] 8'11001110 + case + assign $1\dec31_dec_sub4_asmcode[7:0] 8'00000000 + end + sync always + update \dec31_dec_sub4_asmcode $0\dec31_dec_sub4_asmcode[7:0] + end + attribute \src "issuer_ls180.v:99642.3-99654.6" + process $proc$issuer_ls180.v:99642$3977 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub4_inv_a[0:0] $1\dec31_dec_sub4_inv_a[0:0] + attribute \src "issuer_ls180.v:99643.5-99643.29" + switch \initial + attribute \src "issuer_ls180.v:99643.9-99643.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub4_inv_a[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub4_inv_a[0:0] 1'0 + case + assign $1\dec31_dec_sub4_inv_a[0:0] 1'0 + end + sync always + update \dec31_dec_sub4_inv_a $0\dec31_dec_sub4_inv_a[0:0] + end + attribute \src "issuer_ls180.v:99655.3-99667.6" + process $proc$issuer_ls180.v:99655$3978 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub4_inv_out[0:0] $1\dec31_dec_sub4_inv_out[0:0] + attribute \src "issuer_ls180.v:99656.5-99656.29" + switch \initial + attribute \src "issuer_ls180.v:99656.9-99656.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub4_inv_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub4_inv_out[0:0] 1'0 + case + assign $1\dec31_dec_sub4_inv_out[0:0] 1'0 + end + sync always + update \dec31_dec_sub4_inv_out $0\dec31_dec_sub4_inv_out[0:0] + end + attribute \src "issuer_ls180.v:99668.3-99680.6" + process $proc$issuer_ls180.v:99668$3979 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub4_cry_out[0:0] $1\dec31_dec_sub4_cry_out[0:0] + attribute \src "issuer_ls180.v:99669.5-99669.29" + switch \initial + attribute \src "issuer_ls180.v:99669.9-99669.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub4_cry_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub4_cry_out[0:0] 1'0 + case + assign $1\dec31_dec_sub4_cry_out[0:0] 1'0 + end + sync always + update \dec31_dec_sub4_cry_out $0\dec31_dec_sub4_cry_out[0:0] + end + attribute \src "issuer_ls180.v:99681.3-99693.6" + process $proc$issuer_ls180.v:99681$3980 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub4_br[0:0] $1\dec31_dec_sub4_br[0:0] + attribute \src "issuer_ls180.v:99682.5-99682.29" + switch \initial + attribute \src "issuer_ls180.v:99682.9-99682.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub4_br[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub4_br[0:0] 1'0 + case + assign $1\dec31_dec_sub4_br[0:0] 1'0 + end + sync always + update \dec31_dec_sub4_br $0\dec31_dec_sub4_br[0:0] + end + attribute \src "issuer_ls180.v:99694.3-99706.6" + process $proc$issuer_ls180.v:99694$3981 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub4_sgn_ext[0:0] $1\dec31_dec_sub4_sgn_ext[0:0] + attribute \src "issuer_ls180.v:99695.5-99695.29" + switch \initial + attribute \src "issuer_ls180.v:99695.9-99695.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub4_sgn_ext[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub4_sgn_ext[0:0] 1'0 + case + assign $1\dec31_dec_sub4_sgn_ext[0:0] 1'0 + end + sync always + update \dec31_dec_sub4_sgn_ext $0\dec31_dec_sub4_sgn_ext[0:0] + end + attribute \src "issuer_ls180.v:99707.3-99719.6" + process $proc$issuer_ls180.v:99707$3982 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub4_internal_op[6:0] $1\dec31_dec_sub4_internal_op[6:0] + attribute \src "issuer_ls180.v:99708.5-99708.29" + switch \initial + attribute \src "issuer_ls180.v:99708.9-99708.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub4_internal_op[6:0] 7'0111111 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub4_internal_op[6:0] 7'0111111 + case + assign $1\dec31_dec_sub4_internal_op[6:0] 7'0000000 + end + sync always + update \dec31_dec_sub4_internal_op $0\dec31_dec_sub4_internal_op[6:0] + end + attribute \src "issuer_ls180.v:99720.3-99732.6" + process $proc$issuer_ls180.v:99720$3983 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub4_rsrv[0:0] $1\dec31_dec_sub4_rsrv[0:0] + attribute \src "issuer_ls180.v:99721.5-99721.29" + switch \initial + attribute \src "issuer_ls180.v:99721.9-99721.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub4_rsrv[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub4_rsrv[0:0] 1'0 + case + assign $1\dec31_dec_sub4_rsrv[0:0] 1'0 + end + sync always + update \dec31_dec_sub4_rsrv $0\dec31_dec_sub4_rsrv[0:0] + end + attribute \src "issuer_ls180.v:99733.3-99745.6" + process $proc$issuer_ls180.v:99733$3984 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub4_is_32b[0:0] $1\dec31_dec_sub4_is_32b[0:0] + attribute \src "issuer_ls180.v:99734.5-99734.29" + switch \initial + attribute \src "issuer_ls180.v:99734.9-99734.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub4_is_32b[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub4_is_32b[0:0] 1'1 + case + assign $1\dec31_dec_sub4_is_32b[0:0] 1'0 + end + sync always + update \dec31_dec_sub4_is_32b $0\dec31_dec_sub4_is_32b[0:0] + end + attribute \src "issuer_ls180.v:99746.3-99758.6" + process $proc$issuer_ls180.v:99746$3985 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub4_sgn[0:0] $1\dec31_dec_sub4_sgn[0:0] + attribute \src "issuer_ls180.v:99747.5-99747.29" + switch \initial + attribute \src "issuer_ls180.v:99747.9-99747.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub4_sgn[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub4_sgn[0:0] 1'0 + case + assign $1\dec31_dec_sub4_sgn[0:0] 1'0 + end + sync always + update \dec31_dec_sub4_sgn $0\dec31_dec_sub4_sgn[0:0] + end + attribute \src "issuer_ls180.v:99759.3-99771.6" + process $proc$issuer_ls180.v:99759$3986 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub4_lk[0:0] $1\dec31_dec_sub4_lk[0:0] + attribute \src "issuer_ls180.v:99760.5-99760.29" + switch \initial + attribute \src "issuer_ls180.v:99760.9-99760.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub4_lk[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub4_lk[0:0] 1'0 + case + assign $1\dec31_dec_sub4_lk[0:0] 1'0 + end + sync always + update \dec31_dec_sub4_lk $0\dec31_dec_sub4_lk[0:0] + end + attribute \src "issuer_ls180.v:99772.3-99784.6" + process $proc$issuer_ls180.v:99772$3987 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub4_sgl_pipe[0:0] $1\dec31_dec_sub4_sgl_pipe[0:0] + attribute \src "issuer_ls180.v:99773.5-99773.29" + switch \initial + attribute \src "issuer_ls180.v:99773.9-99773.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub4_sgl_pipe[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub4_sgl_pipe[0:0] 1'1 + case + assign $1\dec31_dec_sub4_sgl_pipe[0:0] 1'0 + end + sync always + update \dec31_dec_sub4_sgl_pipe $0\dec31_dec_sub4_sgl_pipe[0:0] + end + attribute \src "issuer_ls180.v:99785.3-99797.6" + process $proc$issuer_ls180.v:99785$3988 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub4_form[4:0] $1\dec31_dec_sub4_form[4:0] + attribute \src "issuer_ls180.v:99786.5-99786.29" + switch \initial + attribute \src "issuer_ls180.v:99786.9-99786.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub4_form[4:0] 5'01000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub4_form[4:0] 5'01000 + case + assign $1\dec31_dec_sub4_form[4:0] 5'00000 + end + sync always + update \dec31_dec_sub4_form $0\dec31_dec_sub4_form[4:0] + end + attribute \src "issuer_ls180.v:99798.3-99810.6" + process $proc$issuer_ls180.v:99798$3989 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub4_in1_sel[2:0] $1\dec31_dec_sub4_in1_sel[2:0] + attribute \src "issuer_ls180.v:99799.5-99799.29" + switch \initial + attribute \src "issuer_ls180.v:99799.9-99799.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub4_in1_sel[2:0] 3'001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub4_in1_sel[2:0] 3'001 + case + assign $1\dec31_dec_sub4_in1_sel[2:0] 3'000 + end + sync always + update \dec31_dec_sub4_in1_sel $0\dec31_dec_sub4_in1_sel[2:0] + end + attribute \src "issuer_ls180.v:99811.3-99823.6" + process $proc$issuer_ls180.v:99811$3990 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub4_in2_sel[3:0] $1\dec31_dec_sub4_in2_sel[3:0] + attribute \src "issuer_ls180.v:99812.5-99812.29" + switch \initial + attribute \src "issuer_ls180.v:99812.9-99812.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub4_in2_sel[3:0] 4'0001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub4_in2_sel[3:0] 4'0001 + case + assign $1\dec31_dec_sub4_in2_sel[3:0] 4'0000 + end + sync always + update \dec31_dec_sub4_in2_sel $0\dec31_dec_sub4_in2_sel[3:0] + end + attribute \src "issuer_ls180.v:99824.3-99836.6" + process $proc$issuer_ls180.v:99824$3991 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub4_in3_sel[1:0] $1\dec31_dec_sub4_in3_sel[1:0] + attribute \src "issuer_ls180.v:99825.5-99825.29" + switch \initial + attribute \src "issuer_ls180.v:99825.9-99825.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub4_in3_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub4_in3_sel[1:0] 2'00 + case + assign $1\dec31_dec_sub4_in3_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub4_in3_sel $0\dec31_dec_sub4_in3_sel[1:0] + end + attribute \src "issuer_ls180.v:99837.3-99849.6" + process $proc$issuer_ls180.v:99837$3992 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub4_out_sel[1:0] $1\dec31_dec_sub4_out_sel[1:0] + attribute \src "issuer_ls180.v:99838.5-99838.29" + switch \initial + attribute \src "issuer_ls180.v:99838.9-99838.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub4_out_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub4_out_sel[1:0] 2'00 + case + assign $1\dec31_dec_sub4_out_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub4_out_sel $0\dec31_dec_sub4_out_sel[1:0] + end + attribute \src "issuer_ls180.v:99850.3-99862.6" + process $proc$issuer_ls180.v:99850$3993 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub4_cr_in[2:0] $1\dec31_dec_sub4_cr_in[2:0] + attribute \src "issuer_ls180.v:99851.5-99851.29" + switch \initial + attribute \src "issuer_ls180.v:99851.9-99851.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub4_cr_in[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub4_cr_in[2:0] 3'000 + case + assign $1\dec31_dec_sub4_cr_in[2:0] 3'000 + end + sync always + update \dec31_dec_sub4_cr_in $0\dec31_dec_sub4_cr_in[2:0] + end + attribute \src "issuer_ls180.v:99863.3-99875.6" + process $proc$issuer_ls180.v:99863$3994 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub4_cr_out[2:0] $1\dec31_dec_sub4_cr_out[2:0] + attribute \src "issuer_ls180.v:99864.5-99864.29" + switch \initial + attribute \src "issuer_ls180.v:99864.9-99864.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub4_cr_out[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub4_cr_out[2:0] 3'000 + case + assign $1\dec31_dec_sub4_cr_out[2:0] 3'000 + end + sync always + update \dec31_dec_sub4_cr_out $0\dec31_dec_sub4_cr_out[2:0] + end + connect \opcode_switch \opcode_in [10:6] +end +attribute \src "issuer_ls180.v:99881.1-101172.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.dec2.dec.dec31.dec31_dec_sub8" +attribute \generator "nMigen" +module \dec31_dec_sub8 + attribute \src "issuer_ls180.v:100354.3-100396.6" + wire width 8 $0\dec31_dec_sub8_asmcode[7:0] + attribute \src "issuer_ls180.v:100526.3-100568.6" + wire $0\dec31_dec_sub8_br[0:0] + attribute \src "issuer_ls180.v:101085.3-101127.6" + wire width 3 $0\dec31_dec_sub8_cr_in[2:0] + attribute \src "issuer_ls180.v:101128.3-101170.6" + wire width 3 $0\dec31_dec_sub8_cr_out[2:0] + attribute \src "issuer_ls180.v:100311.3-100353.6" + wire width 2 $0\dec31_dec_sub8_cry_in[1:0] + attribute \src "issuer_ls180.v:100483.3-100525.6" + wire $0\dec31_dec_sub8_cry_out[0:0] + attribute \src "issuer_ls180.v:100870.3-100912.6" + wire width 5 $0\dec31_dec_sub8_form[4:0] + attribute \src "issuer_ls180.v:100139.3-100181.6" + wire width 12 $0\dec31_dec_sub8_function_unit[11:0] + attribute \src "issuer_ls180.v:100913.3-100955.6" + wire width 3 $0\dec31_dec_sub8_in1_sel[2:0] + attribute \src "issuer_ls180.v:100956.3-100998.6" + wire width 4 $0\dec31_dec_sub8_in2_sel[3:0] + attribute \src "issuer_ls180.v:100999.3-101041.6" + wire width 2 $0\dec31_dec_sub8_in3_sel[1:0] + attribute \src "issuer_ls180.v:100612.3-100654.6" + wire width 7 $0\dec31_dec_sub8_internal_op[6:0] + attribute \src "issuer_ls180.v:100397.3-100439.6" + wire $0\dec31_dec_sub8_inv_a[0:0] + attribute \src "issuer_ls180.v:100440.3-100482.6" + wire $0\dec31_dec_sub8_inv_out[0:0] + attribute \src "issuer_ls180.v:100698.3-100740.6" + wire $0\dec31_dec_sub8_is_32b[0:0] + attribute \src "issuer_ls180.v:100182.3-100224.6" + wire width 4 $0\dec31_dec_sub8_ldst_len[3:0] + attribute \src "issuer_ls180.v:100784.3-100826.6" + wire $0\dec31_dec_sub8_lk[0:0] + attribute \src "issuer_ls180.v:101042.3-101084.6" + wire width 2 $0\dec31_dec_sub8_out_sel[1:0] + attribute \src "issuer_ls180.v:100268.3-100310.6" + wire width 2 $0\dec31_dec_sub8_rc_sel[1:0] + attribute \src "issuer_ls180.v:100655.3-100697.6" + wire $0\dec31_dec_sub8_rsrv[0:0] + attribute \src "issuer_ls180.v:100827.3-100869.6" + wire $0\dec31_dec_sub8_sgl_pipe[0:0] + attribute \src "issuer_ls180.v:100741.3-100783.6" + wire $0\dec31_dec_sub8_sgn[0:0] + attribute \src "issuer_ls180.v:100569.3-100611.6" + wire $0\dec31_dec_sub8_sgn_ext[0:0] + attribute \src "issuer_ls180.v:100225.3-100267.6" + wire width 2 $0\dec31_dec_sub8_upd[1:0] + attribute \src "issuer_ls180.v:99882.7-99882.20" + wire $0\initial[0:0] + attribute \src "issuer_ls180.v:100354.3-100396.6" + wire width 8 $1\dec31_dec_sub8_asmcode[7:0] + attribute \src "issuer_ls180.v:100526.3-100568.6" + wire $1\dec31_dec_sub8_br[0:0] + attribute \src "issuer_ls180.v:101085.3-101127.6" + wire width 3 $1\dec31_dec_sub8_cr_in[2:0] + attribute \src "issuer_ls180.v:101128.3-101170.6" + wire width 3 $1\dec31_dec_sub8_cr_out[2:0] + attribute \src "issuer_ls180.v:100311.3-100353.6" + wire width 2 $1\dec31_dec_sub8_cry_in[1:0] + attribute \src "issuer_ls180.v:100483.3-100525.6" + wire $1\dec31_dec_sub8_cry_out[0:0] + attribute \src "issuer_ls180.v:100870.3-100912.6" + wire width 5 $1\dec31_dec_sub8_form[4:0] + attribute \src "issuer_ls180.v:100139.3-100181.6" + wire width 12 $1\dec31_dec_sub8_function_unit[11:0] + attribute \src "issuer_ls180.v:100913.3-100955.6" + wire width 3 $1\dec31_dec_sub8_in1_sel[2:0] + attribute \src "issuer_ls180.v:100956.3-100998.6" + wire width 4 $1\dec31_dec_sub8_in2_sel[3:0] + attribute \src "issuer_ls180.v:100999.3-101041.6" + wire width 2 $1\dec31_dec_sub8_in3_sel[1:0] + attribute \src "issuer_ls180.v:100612.3-100654.6" + wire width 7 $1\dec31_dec_sub8_internal_op[6:0] + attribute \src "issuer_ls180.v:100397.3-100439.6" + wire $1\dec31_dec_sub8_inv_a[0:0] + attribute \src "issuer_ls180.v:100440.3-100482.6" + wire $1\dec31_dec_sub8_inv_out[0:0] + attribute \src "issuer_ls180.v:100698.3-100740.6" + wire $1\dec31_dec_sub8_is_32b[0:0] + attribute \src "issuer_ls180.v:100182.3-100224.6" + wire width 4 $1\dec31_dec_sub8_ldst_len[3:0] + attribute \src "issuer_ls180.v:100784.3-100826.6" + wire $1\dec31_dec_sub8_lk[0:0] + attribute \src "issuer_ls180.v:101042.3-101084.6" + wire width 2 $1\dec31_dec_sub8_out_sel[1:0] + attribute \src "issuer_ls180.v:100268.3-100310.6" + wire width 2 $1\dec31_dec_sub8_rc_sel[1:0] + attribute \src "issuer_ls180.v:100655.3-100697.6" + wire $1\dec31_dec_sub8_rsrv[0:0] + attribute \src "issuer_ls180.v:100827.3-100869.6" + wire $1\dec31_dec_sub8_sgl_pipe[0:0] + attribute \src "issuer_ls180.v:100741.3-100783.6" + wire $1\dec31_dec_sub8_sgn[0:0] + attribute \src "issuer_ls180.v:100569.3-100611.6" + wire $1\dec31_dec_sub8_sgn_ext[0:0] + attribute \src "issuer_ls180.v:100225.3-100267.6" + wire width 2 $1\dec31_dec_sub8_upd[1:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 8 output 4 \dec31_dec_sub8_asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 18 \dec31_dec_sub8_br + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 9 \dec31_dec_sub8_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 10 \dec31_dec_sub8_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 14 \dec31_dec_sub8_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 17 \dec31_dec_sub8_cry_out + attribute \enum_base_type "Form" + attribute \enum_value_00000 "NONE" + attribute \enum_value_00001 "I" + attribute \enum_value_00010 "B" + attribute \enum_value_00011 "SC" + attribute \enum_value_00100 "D" + attribute \enum_value_00101 "DS" + attribute \enum_value_00110 "DQ" + attribute \enum_value_00111 "DX" + attribute \enum_value_01000 "X" + attribute \enum_value_01001 "XL" + attribute \enum_value_01010 "XFX" + attribute \enum_value_01011 "XFL" + attribute \enum_value_01100 "XX1" + attribute \enum_value_01101 "XX2" + attribute \enum_value_01110 "XX3" + attribute \enum_value_01111 "XX4" + attribute \enum_value_10000 "XS" + attribute \enum_value_10001 "XO" + attribute \enum_value_10010 "A" + attribute \enum_value_10011 "M" + attribute \enum_value_10100 "MD" + attribute \enum_value_10101 "MDS" + attribute \enum_value_10110 "VA" + attribute \enum_value_10111 "VC" + attribute \enum_value_11000 "VX" + attribute \enum_value_11001 "EVX" + attribute \enum_value_11010 "EVS" + attribute \enum_value_11011 "Z22" + attribute \enum_value_11100 "Z23" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 5 output 3 \dec31_dec_sub8_form + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 12 output 1 \dec31_dec_sub8_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 5 \dec31_dec_sub8_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 output 6 \dec31_dec_sub8_in2_sel + attribute \enum_base_type "In3Sel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RS" + attribute \enum_value_10 "RB" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 7 \dec31_dec_sub8_in3_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 7 output 2 \dec31_dec_sub8_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 15 \dec31_dec_sub8_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 16 \dec31_dec_sub8_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 21 \dec31_dec_sub8_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 output 11 \dec31_dec_sub8_ldst_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 23 \dec31_dec_sub8_lk + attribute \enum_base_type "OutSel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RT" + attribute \enum_value_10 "RA" + attribute \enum_value_11 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 8 \dec31_dec_sub8_out_sel + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 13 \dec31_dec_sub8_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 20 \dec31_dec_sub8_rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 24 \dec31_dec_sub8_sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 22 \dec31_dec_sub8_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 19 \dec31_dec_sub8_sgn_ext + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 12 \dec31_dec_sub8_upd + attribute \src "issuer_ls180.v:99882.7-99882.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + wire width 32 input 25 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:320" + wire width 5 \opcode_switch + attribute \src "issuer_ls180.v:100139.3-100181.6" + process $proc$issuer_ls180.v:100139$3996 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub8_function_unit[11:0] $1\dec31_dec_sub8_function_unit[11:0] + attribute \src "issuer_ls180.v:100140.5-100140.29" + switch \initial + attribute \src "issuer_ls180.v:100140.9-100140.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub8_function_unit[11:0] 12'000000000010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub8_function_unit[11:0] 12'000000000010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub8_function_unit[11:0] 12'000000000010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub8_function_unit[11:0] 12'000000000010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub8_function_unit[11:0] 12'000000000010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub8_function_unit[11:0] 12'000000000010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub8_function_unit[11:0] 12'000000000010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub8_function_unit[11:0] 12'000000000010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub8_function_unit[11:0] 12'000000000010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub8_function_unit[11:0] 12'000000000010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub8_function_unit[11:0] 12'000000000010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub8_function_unit[11:0] 12'000000000010 + case + assign $1\dec31_dec_sub8_function_unit[11:0] 12'000000000000 + end + sync always + update \dec31_dec_sub8_function_unit $0\dec31_dec_sub8_function_unit[11:0] + end + attribute \src "issuer_ls180.v:100182.3-100224.6" + process $proc$issuer_ls180.v:100182$3997 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub8_ldst_len[3:0] $1\dec31_dec_sub8_ldst_len[3:0] + attribute \src "issuer_ls180.v:100183.5-100183.29" + switch \initial + attribute \src "issuer_ls180.v:100183.9-100183.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub8_ldst_len[3:0] 4'0000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub8_ldst_len[3:0] 4'0000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub8_ldst_len[3:0] 4'0000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub8_ldst_len[3:0] 4'0000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub8_ldst_len[3:0] 4'0000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub8_ldst_len[3:0] 4'0000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub8_ldst_len[3:0] 4'0000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub8_ldst_len[3:0] 4'0000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub8_ldst_len[3:0] 4'0000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub8_ldst_len[3:0] 4'0000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub8_ldst_len[3:0] 4'0000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub8_ldst_len[3:0] 4'0000 + case + assign $1\dec31_dec_sub8_ldst_len[3:0] 4'0000 + end + sync always + update \dec31_dec_sub8_ldst_len $0\dec31_dec_sub8_ldst_len[3:0] + end + attribute \src "issuer_ls180.v:100225.3-100267.6" + process $proc$issuer_ls180.v:100225$3998 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub8_upd[1:0] $1\dec31_dec_sub8_upd[1:0] + attribute \src "issuer_ls180.v:100226.5-100226.29" + switch \initial + attribute \src "issuer_ls180.v:100226.9-100226.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub8_upd[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub8_upd[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub8_upd[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub8_upd[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub8_upd[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub8_upd[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub8_upd[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub8_upd[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub8_upd[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub8_upd[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub8_upd[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub8_upd[1:0] 2'00 + case + assign $1\dec31_dec_sub8_upd[1:0] 2'00 + end + sync always + update \dec31_dec_sub8_upd $0\dec31_dec_sub8_upd[1:0] + end + attribute \src "issuer_ls180.v:100268.3-100310.6" + process $proc$issuer_ls180.v:100268$3999 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub8_rc_sel[1:0] $1\dec31_dec_sub8_rc_sel[1:0] + attribute \src "issuer_ls180.v:100269.5-100269.29" + switch \initial + attribute \src "issuer_ls180.v:100269.9-100269.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub8_rc_sel[1:0] 2'10 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub8_rc_sel[1:0] 2'10 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub8_rc_sel[1:0] 2'10 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub8_rc_sel[1:0] 2'10 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub8_rc_sel[1:0] 2'10 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub8_rc_sel[1:0] 2'10 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub8_rc_sel[1:0] 2'10 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub8_rc_sel[1:0] 2'10 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub8_rc_sel[1:0] 2'10 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub8_rc_sel[1:0] 2'10 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub8_rc_sel[1:0] 2'10 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub8_rc_sel[1:0] 2'10 + case + assign $1\dec31_dec_sub8_rc_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub8_rc_sel $0\dec31_dec_sub8_rc_sel[1:0] + end + attribute \src "issuer_ls180.v:100311.3-100353.6" + process $proc$issuer_ls180.v:100311$4000 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub8_cry_in[1:0] $1\dec31_dec_sub8_cry_in[1:0] + attribute \src "issuer_ls180.v:100312.5-100312.29" + switch \initial + attribute \src "issuer_ls180.v:100312.9-100312.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub8_cry_in[1:0] 2'01 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub8_cry_in[1:0] 2'01 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub8_cry_in[1:0] 2'01 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub8_cry_in[1:0] 2'01 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub8_cry_in[1:0] 2'01 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub8_cry_in[1:0] 2'01 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub8_cry_in[1:0] 2'10 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub8_cry_in[1:0] 2'10 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub8_cry_in[1:0] 2'10 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub8_cry_in[1:0] 2'10 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub8_cry_in[1:0] 2'10 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub8_cry_in[1:0] 2'10 + case + assign $1\dec31_dec_sub8_cry_in[1:0] 2'00 + end + sync always + update \dec31_dec_sub8_cry_in $0\dec31_dec_sub8_cry_in[1:0] + end + attribute \src "issuer_ls180.v:100354.3-100396.6" + process $proc$issuer_ls180.v:100354$4001 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub8_asmcode[7:0] $1\dec31_dec_sub8_asmcode[7:0] + attribute \src "issuer_ls180.v:100355.5-100355.29" + switch \initial + attribute \src "issuer_ls180.v:100355.9-100355.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub8_asmcode[7:0] 8'10000100 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub8_asmcode[7:0] 8'10000101 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub8_asmcode[7:0] 8'10111110 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub8_asmcode[7:0] 8'11000110 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub8_asmcode[7:0] 8'10111111 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub8_asmcode[7:0] 8'11000000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub8_asmcode[7:0] 8'11000001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub8_asmcode[7:0] 8'11000010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub8_asmcode[7:0] 8'11000100 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub8_asmcode[7:0] 8'11000101 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub8_asmcode[7:0] 8'11000111 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub8_asmcode[7:0] 8'11001000 + case + assign $1\dec31_dec_sub8_asmcode[7:0] 8'00000000 + end + sync always + update \dec31_dec_sub8_asmcode $0\dec31_dec_sub8_asmcode[7:0] + end + attribute \src "issuer_ls180.v:100397.3-100439.6" + process $proc$issuer_ls180.v:100397$4002 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub8_inv_a[0:0] $1\dec31_dec_sub8_inv_a[0:0] + attribute \src "issuer_ls180.v:100398.5-100398.29" + switch \initial + attribute \src "issuer_ls180.v:100398.9-100398.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub8_inv_a[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub8_inv_a[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub8_inv_a[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub8_inv_a[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub8_inv_a[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub8_inv_a[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub8_inv_a[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub8_inv_a[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub8_inv_a[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub8_inv_a[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub8_inv_a[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub8_inv_a[0:0] 1'1 + case + assign $1\dec31_dec_sub8_inv_a[0:0] 1'0 + end + sync always + update \dec31_dec_sub8_inv_a $0\dec31_dec_sub8_inv_a[0:0] + end + attribute \src "issuer_ls180.v:100440.3-100482.6" + process $proc$issuer_ls180.v:100440$4003 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub8_inv_out[0:0] $1\dec31_dec_sub8_inv_out[0:0] + attribute \src "issuer_ls180.v:100441.5-100441.29" + switch \initial + attribute \src "issuer_ls180.v:100441.9-100441.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub8_inv_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub8_inv_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub8_inv_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub8_inv_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub8_inv_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub8_inv_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub8_inv_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub8_inv_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub8_inv_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub8_inv_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub8_inv_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub8_inv_out[0:0] 1'0 + case + assign $1\dec31_dec_sub8_inv_out[0:0] 1'0 + end + sync always + update \dec31_dec_sub8_inv_out $0\dec31_dec_sub8_inv_out[0:0] + end + attribute \src "issuer_ls180.v:100483.3-100525.6" + process $proc$issuer_ls180.v:100483$4004 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub8_cry_out[0:0] $1\dec31_dec_sub8_cry_out[0:0] + attribute \src "issuer_ls180.v:100484.5-100484.29" + switch \initial + attribute \src "issuer_ls180.v:100484.9-100484.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub8_cry_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub8_cry_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub8_cry_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub8_cry_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub8_cry_out[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub8_cry_out[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub8_cry_out[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub8_cry_out[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub8_cry_out[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub8_cry_out[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub8_cry_out[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub8_cry_out[0:0] 1'1 + case + assign $1\dec31_dec_sub8_cry_out[0:0] 1'0 + end + sync always + update \dec31_dec_sub8_cry_out $0\dec31_dec_sub8_cry_out[0:0] + end + attribute \src "issuer_ls180.v:100526.3-100568.6" + process $proc$issuer_ls180.v:100526$4005 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub8_br[0:0] $1\dec31_dec_sub8_br[0:0] + attribute \src "issuer_ls180.v:100527.5-100527.29" + switch \initial + attribute \src "issuer_ls180.v:100527.9-100527.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub8_br[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub8_br[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub8_br[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub8_br[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub8_br[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub8_br[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub8_br[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub8_br[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub8_br[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub8_br[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub8_br[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub8_br[0:0] 1'0 + case + assign $1\dec31_dec_sub8_br[0:0] 1'0 + end + sync always + update \dec31_dec_sub8_br $0\dec31_dec_sub8_br[0:0] + end + attribute \src "issuer_ls180.v:100569.3-100611.6" + process $proc$issuer_ls180.v:100569$4006 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub8_sgn_ext[0:0] $1\dec31_dec_sub8_sgn_ext[0:0] + attribute \src "issuer_ls180.v:100570.5-100570.29" + switch \initial + attribute \src "issuer_ls180.v:100570.9-100570.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub8_sgn_ext[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub8_sgn_ext[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub8_sgn_ext[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub8_sgn_ext[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub8_sgn_ext[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub8_sgn_ext[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub8_sgn_ext[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub8_sgn_ext[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub8_sgn_ext[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub8_sgn_ext[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub8_sgn_ext[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub8_sgn_ext[0:0] 1'0 + case + assign $1\dec31_dec_sub8_sgn_ext[0:0] 1'0 + end + sync always + update \dec31_dec_sub8_sgn_ext $0\dec31_dec_sub8_sgn_ext[0:0] + end + attribute \src "issuer_ls180.v:100612.3-100654.6" + process $proc$issuer_ls180.v:100612$4007 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub8_internal_op[6:0] $1\dec31_dec_sub8_internal_op[6:0] + attribute \src "issuer_ls180.v:100613.5-100613.29" + switch \initial + attribute \src "issuer_ls180.v:100613.9-100613.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub8_internal_op[6:0] 7'0000010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub8_internal_op[6:0] 7'0000010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub8_internal_op[6:0] 7'0000010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub8_internal_op[6:0] 7'0000010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub8_internal_op[6:0] 7'0000010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub8_internal_op[6:0] 7'0000010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub8_internal_op[6:0] 7'0000010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub8_internal_op[6:0] 7'0000010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub8_internal_op[6:0] 7'0000010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub8_internal_op[6:0] 7'0000010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub8_internal_op[6:0] 7'0000010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub8_internal_op[6:0] 7'0000010 + case + assign $1\dec31_dec_sub8_internal_op[6:0] 7'0000000 + end + sync always + update \dec31_dec_sub8_internal_op $0\dec31_dec_sub8_internal_op[6:0] + end + attribute \src "issuer_ls180.v:100655.3-100697.6" + process $proc$issuer_ls180.v:100655$4008 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub8_rsrv[0:0] $1\dec31_dec_sub8_rsrv[0:0] + attribute \src "issuer_ls180.v:100656.5-100656.29" + switch \initial + attribute \src "issuer_ls180.v:100656.9-100656.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub8_rsrv[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub8_rsrv[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub8_rsrv[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub8_rsrv[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub8_rsrv[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub8_rsrv[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub8_rsrv[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub8_rsrv[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub8_rsrv[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub8_rsrv[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub8_rsrv[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub8_rsrv[0:0] 1'0 + case + assign $1\dec31_dec_sub8_rsrv[0:0] 1'0 + end + sync always + update \dec31_dec_sub8_rsrv $0\dec31_dec_sub8_rsrv[0:0] + end + attribute \src "issuer_ls180.v:100698.3-100740.6" + process $proc$issuer_ls180.v:100698$4009 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub8_is_32b[0:0] $1\dec31_dec_sub8_is_32b[0:0] + attribute \src "issuer_ls180.v:100699.5-100699.29" + switch \initial + attribute \src "issuer_ls180.v:100699.9-100699.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub8_is_32b[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub8_is_32b[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub8_is_32b[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub8_is_32b[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub8_is_32b[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub8_is_32b[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub8_is_32b[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub8_is_32b[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub8_is_32b[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub8_is_32b[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub8_is_32b[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub8_is_32b[0:0] 1'0 + case + assign $1\dec31_dec_sub8_is_32b[0:0] 1'0 + end + sync always + update \dec31_dec_sub8_is_32b $0\dec31_dec_sub8_is_32b[0:0] + end + attribute \src "issuer_ls180.v:100741.3-100783.6" + process $proc$issuer_ls180.v:100741$4010 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub8_sgn[0:0] $1\dec31_dec_sub8_sgn[0:0] + attribute \src "issuer_ls180.v:100742.5-100742.29" + switch \initial + attribute \src "issuer_ls180.v:100742.9-100742.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub8_sgn[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub8_sgn[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub8_sgn[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub8_sgn[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub8_sgn[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub8_sgn[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub8_sgn[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub8_sgn[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub8_sgn[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub8_sgn[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub8_sgn[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub8_sgn[0:0] 1'0 + case + assign $1\dec31_dec_sub8_sgn[0:0] 1'0 + end + sync always + update \dec31_dec_sub8_sgn $0\dec31_dec_sub8_sgn[0:0] + end + attribute \src "issuer_ls180.v:100784.3-100826.6" + process $proc$issuer_ls180.v:100784$4011 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub8_lk[0:0] $1\dec31_dec_sub8_lk[0:0] + attribute \src "issuer_ls180.v:100785.5-100785.29" + switch \initial + attribute \src "issuer_ls180.v:100785.9-100785.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub8_lk[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub8_lk[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub8_lk[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub8_lk[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub8_lk[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub8_lk[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub8_lk[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub8_lk[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub8_lk[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub8_lk[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub8_lk[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub8_lk[0:0] 1'0 + case + assign $1\dec31_dec_sub8_lk[0:0] 1'0 + end + sync always + update \dec31_dec_sub8_lk $0\dec31_dec_sub8_lk[0:0] + end + attribute \src "issuer_ls180.v:100827.3-100869.6" + process $proc$issuer_ls180.v:100827$4012 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub8_sgl_pipe[0:0] $1\dec31_dec_sub8_sgl_pipe[0:0] + attribute \src "issuer_ls180.v:100828.5-100828.29" + switch \initial + attribute \src "issuer_ls180.v:100828.9-100828.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub8_sgl_pipe[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub8_sgl_pipe[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub8_sgl_pipe[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub8_sgl_pipe[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub8_sgl_pipe[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub8_sgl_pipe[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub8_sgl_pipe[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub8_sgl_pipe[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub8_sgl_pipe[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub8_sgl_pipe[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub8_sgl_pipe[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub8_sgl_pipe[0:0] 1'0 + case + assign $1\dec31_dec_sub8_sgl_pipe[0:0] 1'0 + end + sync always + update \dec31_dec_sub8_sgl_pipe $0\dec31_dec_sub8_sgl_pipe[0:0] + end + attribute \src "issuer_ls180.v:100870.3-100912.6" + process $proc$issuer_ls180.v:100870$4013 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub8_form[4:0] $1\dec31_dec_sub8_form[4:0] + attribute \src "issuer_ls180.v:100871.5-100871.29" + switch \initial + attribute \src "issuer_ls180.v:100871.9-100871.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub8_form[4:0] 5'10001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub8_form[4:0] 5'10001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub8_form[4:0] 5'10001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub8_form[4:0] 5'10001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub8_form[4:0] 5'10001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub8_form[4:0] 5'10001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub8_form[4:0] 5'10001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub8_form[4:0] 5'10001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub8_form[4:0] 5'10001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub8_form[4:0] 5'10001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub8_form[4:0] 5'10001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub8_form[4:0] 5'10001 + case + assign $1\dec31_dec_sub8_form[4:0] 5'00000 + end + sync always + update \dec31_dec_sub8_form $0\dec31_dec_sub8_form[4:0] + end + attribute \src "issuer_ls180.v:100913.3-100955.6" + process $proc$issuer_ls180.v:100913$4014 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub8_in1_sel[2:0] $1\dec31_dec_sub8_in1_sel[2:0] + attribute \src "issuer_ls180.v:100914.5-100914.29" + switch \initial + attribute \src "issuer_ls180.v:100914.9-100914.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub8_in1_sel[2:0] 3'001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub8_in1_sel[2:0] 3'001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub8_in1_sel[2:0] 3'001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub8_in1_sel[2:0] 3'001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub8_in1_sel[2:0] 3'001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub8_in1_sel[2:0] 3'001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub8_in1_sel[2:0] 3'001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub8_in1_sel[2:0] 3'001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub8_in1_sel[2:0] 3'001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub8_in1_sel[2:0] 3'001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub8_in1_sel[2:0] 3'001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub8_in1_sel[2:0] 3'001 + case + assign $1\dec31_dec_sub8_in1_sel[2:0] 3'000 + end + sync always + update \dec31_dec_sub8_in1_sel $0\dec31_dec_sub8_in1_sel[2:0] + end + attribute \src "issuer_ls180.v:100956.3-100998.6" + process $proc$issuer_ls180.v:100956$4015 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub8_in2_sel[3:0] $1\dec31_dec_sub8_in2_sel[3:0] + attribute \src "issuer_ls180.v:100957.5-100957.29" + switch \initial + attribute \src "issuer_ls180.v:100957.9-100957.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub8_in2_sel[3:0] 4'0000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub8_in2_sel[3:0] 4'0000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub8_in2_sel[3:0] 4'0001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub8_in2_sel[3:0] 4'0001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub8_in2_sel[3:0] 4'0001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub8_in2_sel[3:0] 4'0001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub8_in2_sel[3:0] 4'0001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub8_in2_sel[3:0] 4'0001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub8_in2_sel[3:0] 4'1001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub8_in2_sel[3:0] 4'1001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub8_in2_sel[3:0] 4'0000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub8_in2_sel[3:0] 4'0000 + case + assign $1\dec31_dec_sub8_in2_sel[3:0] 4'0000 + end + sync always + update \dec31_dec_sub8_in2_sel $0\dec31_dec_sub8_in2_sel[3:0] + end + attribute \src "issuer_ls180.v:100999.3-101041.6" + process $proc$issuer_ls180.v:100999$4016 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub8_in3_sel[1:0] $1\dec31_dec_sub8_in3_sel[1:0] + attribute \src "issuer_ls180.v:101000.5-101000.29" + switch \initial + attribute \src "issuer_ls180.v:101000.9-101000.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub8_in3_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub8_in3_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub8_in3_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub8_in3_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub8_in3_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub8_in3_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub8_in3_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub8_in3_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub8_in3_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub8_in3_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub8_in3_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub8_in3_sel[1:0] 2'00 + case + assign $1\dec31_dec_sub8_in3_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub8_in3_sel $0\dec31_dec_sub8_in3_sel[1:0] + end + attribute \src "issuer_ls180.v:101042.3-101084.6" + process $proc$issuer_ls180.v:101042$4017 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub8_out_sel[1:0] $1\dec31_dec_sub8_out_sel[1:0] + attribute \src "issuer_ls180.v:101043.5-101043.29" + switch \initial + attribute \src "issuer_ls180.v:101043.9-101043.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub8_out_sel[1:0] 2'01 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub8_out_sel[1:0] 2'01 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub8_out_sel[1:0] 2'01 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub8_out_sel[1:0] 2'01 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub8_out_sel[1:0] 2'01 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub8_out_sel[1:0] 2'01 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub8_out_sel[1:0] 2'01 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub8_out_sel[1:0] 2'01 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub8_out_sel[1:0] 2'01 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub8_out_sel[1:0] 2'01 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub8_out_sel[1:0] 2'01 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub8_out_sel[1:0] 2'01 + case + assign $1\dec31_dec_sub8_out_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub8_out_sel $0\dec31_dec_sub8_out_sel[1:0] + end + attribute \src "issuer_ls180.v:101085.3-101127.6" + process $proc$issuer_ls180.v:101085$4018 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub8_cr_in[2:0] $1\dec31_dec_sub8_cr_in[2:0] + attribute \src "issuer_ls180.v:101086.5-101086.29" + switch \initial + attribute \src "issuer_ls180.v:101086.9-101086.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub8_cr_in[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub8_cr_in[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub8_cr_in[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub8_cr_in[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub8_cr_in[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub8_cr_in[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub8_cr_in[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub8_cr_in[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub8_cr_in[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub8_cr_in[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub8_cr_in[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub8_cr_in[2:0] 3'000 + case + assign $1\dec31_dec_sub8_cr_in[2:0] 3'000 + end + sync always + update \dec31_dec_sub8_cr_in $0\dec31_dec_sub8_cr_in[2:0] + end + attribute \src "issuer_ls180.v:101128.3-101170.6" + process $proc$issuer_ls180.v:101128$4019 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub8_cr_out[2:0] $1\dec31_dec_sub8_cr_out[2:0] + attribute \src "issuer_ls180.v:101129.5-101129.29" + switch \initial + attribute \src "issuer_ls180.v:101129.9-101129.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00011 + assign { } { } + assign $1\dec31_dec_sub8_cr_out[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10011 + assign { } { } + assign $1\dec31_dec_sub8_cr_out[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00001 + assign { } { } + assign $1\dec31_dec_sub8_cr_out[2:0] 3'001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10001 + assign { } { } + assign $1\dec31_dec_sub8_cr_out[2:0] 3'001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub8_cr_out[2:0] 3'001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub8_cr_out[2:0] 3'001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00100 + assign { } { } + assign $1\dec31_dec_sub8_cr_out[2:0] 3'001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10100 + assign { } { } + assign $1\dec31_dec_sub8_cr_out[2:0] 3'001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub8_cr_out[2:0] 3'001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub8_cr_out[2:0] 3'001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00110 + assign { } { } + assign $1\dec31_dec_sub8_cr_out[2:0] 3'001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10110 + assign { } { } + assign $1\dec31_dec_sub8_cr_out[2:0] 3'001 + case + assign $1\dec31_dec_sub8_cr_out[2:0] 3'000 + end + sync always + update \dec31_dec_sub8_cr_out $0\dec31_dec_sub8_cr_out[2:0] + end + attribute \src "issuer_ls180.v:99882.7-99882.20" + process $proc$issuer_ls180.v:99882$4020 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + connect \opcode_switch \opcode_in [10:6] +end +attribute \src "issuer_ls180.v:101176.1-102755.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.dec2.dec.dec31.dec31_dec_sub9" +attribute \generator "nMigen" +module \dec31_dec_sub9 + attribute \src "issuer_ls180.v:101709.3-101763.6" + wire width 8 $0\dec31_dec_sub9_asmcode[7:0] + attribute \src "issuer_ls180.v:101929.3-101983.6" + wire $0\dec31_dec_sub9_br[0:0] + attribute \src "issuer_ls180.v:102644.3-102698.6" + wire width 3 $0\dec31_dec_sub9_cr_in[2:0] + attribute \src "issuer_ls180.v:102699.3-102753.6" + wire width 3 $0\dec31_dec_sub9_cr_out[2:0] + attribute \src "issuer_ls180.v:101654.3-101708.6" + wire width 2 $0\dec31_dec_sub9_cry_in[1:0] + attribute \src "issuer_ls180.v:101874.3-101928.6" + wire $0\dec31_dec_sub9_cry_out[0:0] + attribute \src "issuer_ls180.v:102369.3-102423.6" + wire width 5 $0\dec31_dec_sub9_form[4:0] + attribute \src "issuer_ls180.v:101434.3-101488.6" + wire width 12 $0\dec31_dec_sub9_function_unit[11:0] + attribute \src "issuer_ls180.v:102424.3-102478.6" + wire width 3 $0\dec31_dec_sub9_in1_sel[2:0] + attribute \src "issuer_ls180.v:102479.3-102533.6" + wire width 4 $0\dec31_dec_sub9_in2_sel[3:0] + attribute \src "issuer_ls180.v:102534.3-102588.6" + wire width 2 $0\dec31_dec_sub9_in3_sel[1:0] + attribute \src "issuer_ls180.v:102039.3-102093.6" + wire width 7 $0\dec31_dec_sub9_internal_op[6:0] + attribute \src "issuer_ls180.v:101764.3-101818.6" + wire $0\dec31_dec_sub9_inv_a[0:0] + attribute \src "issuer_ls180.v:101819.3-101873.6" + wire $0\dec31_dec_sub9_inv_out[0:0] + attribute \src "issuer_ls180.v:102149.3-102203.6" + wire $0\dec31_dec_sub9_is_32b[0:0] + attribute \src "issuer_ls180.v:101489.3-101543.6" + wire width 4 $0\dec31_dec_sub9_ldst_len[3:0] + attribute \src "issuer_ls180.v:102259.3-102313.6" + wire $0\dec31_dec_sub9_lk[0:0] + attribute \src "issuer_ls180.v:102589.3-102643.6" + wire width 2 $0\dec31_dec_sub9_out_sel[1:0] + attribute \src "issuer_ls180.v:101599.3-101653.6" + wire width 2 $0\dec31_dec_sub9_rc_sel[1:0] + attribute \src "issuer_ls180.v:102094.3-102148.6" + wire $0\dec31_dec_sub9_rsrv[0:0] + attribute \src "issuer_ls180.v:102314.3-102368.6" + wire $0\dec31_dec_sub9_sgl_pipe[0:0] + attribute \src "issuer_ls180.v:102204.3-102258.6" + wire $0\dec31_dec_sub9_sgn[0:0] + attribute \src "issuer_ls180.v:101984.3-102038.6" + wire $0\dec31_dec_sub9_sgn_ext[0:0] + attribute \src "issuer_ls180.v:101544.3-101598.6" + wire width 2 $0\dec31_dec_sub9_upd[1:0] + attribute \src "issuer_ls180.v:101177.7-101177.20" + wire $0\initial[0:0] + attribute \src "issuer_ls180.v:101709.3-101763.6" + wire width 8 $1\dec31_dec_sub9_asmcode[7:0] + attribute \src "issuer_ls180.v:101929.3-101983.6" + wire $1\dec31_dec_sub9_br[0:0] + attribute \src "issuer_ls180.v:102644.3-102698.6" + wire width 3 $1\dec31_dec_sub9_cr_in[2:0] + attribute \src "issuer_ls180.v:102699.3-102753.6" + wire width 3 $1\dec31_dec_sub9_cr_out[2:0] + attribute \src "issuer_ls180.v:101654.3-101708.6" + wire width 2 $1\dec31_dec_sub9_cry_in[1:0] + attribute \src "issuer_ls180.v:101874.3-101928.6" + wire $1\dec31_dec_sub9_cry_out[0:0] + attribute \src "issuer_ls180.v:102369.3-102423.6" + wire width 5 $1\dec31_dec_sub9_form[4:0] + attribute \src "issuer_ls180.v:101434.3-101488.6" + wire width 12 $1\dec31_dec_sub9_function_unit[11:0] + attribute \src "issuer_ls180.v:102424.3-102478.6" + wire width 3 $1\dec31_dec_sub9_in1_sel[2:0] + attribute \src "issuer_ls180.v:102479.3-102533.6" + wire width 4 $1\dec31_dec_sub9_in2_sel[3:0] + attribute \src "issuer_ls180.v:102534.3-102588.6" + wire width 2 $1\dec31_dec_sub9_in3_sel[1:0] + attribute \src "issuer_ls180.v:102039.3-102093.6" + wire width 7 $1\dec31_dec_sub9_internal_op[6:0] + attribute \src "issuer_ls180.v:101764.3-101818.6" + wire $1\dec31_dec_sub9_inv_a[0:0] + attribute \src "issuer_ls180.v:101819.3-101873.6" + wire $1\dec31_dec_sub9_inv_out[0:0] + attribute \src "issuer_ls180.v:102149.3-102203.6" + wire $1\dec31_dec_sub9_is_32b[0:0] + attribute \src "issuer_ls180.v:101489.3-101543.6" + wire width 4 $1\dec31_dec_sub9_ldst_len[3:0] + attribute \src "issuer_ls180.v:102259.3-102313.6" + wire $1\dec31_dec_sub9_lk[0:0] + attribute \src "issuer_ls180.v:102589.3-102643.6" + wire width 2 $1\dec31_dec_sub9_out_sel[1:0] + attribute \src "issuer_ls180.v:101599.3-101653.6" + wire width 2 $1\dec31_dec_sub9_rc_sel[1:0] + attribute \src "issuer_ls180.v:102094.3-102148.6" + wire $1\dec31_dec_sub9_rsrv[0:0] + attribute \src "issuer_ls180.v:102314.3-102368.6" + wire $1\dec31_dec_sub9_sgl_pipe[0:0] + attribute \src "issuer_ls180.v:102204.3-102258.6" + wire $1\dec31_dec_sub9_sgn[0:0] + attribute \src "issuer_ls180.v:101984.3-102038.6" + wire $1\dec31_dec_sub9_sgn_ext[0:0] + attribute \src "issuer_ls180.v:101544.3-101598.6" + wire width 2 $1\dec31_dec_sub9_upd[1:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 8 output 4 \dec31_dec_sub9_asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 18 \dec31_dec_sub9_br + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 9 \dec31_dec_sub9_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 10 \dec31_dec_sub9_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 14 \dec31_dec_sub9_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 17 \dec31_dec_sub9_cry_out + attribute \enum_base_type "Form" + attribute \enum_value_00000 "NONE" + attribute \enum_value_00001 "I" + attribute \enum_value_00010 "B" + attribute \enum_value_00011 "SC" + attribute \enum_value_00100 "D" + attribute \enum_value_00101 "DS" + attribute \enum_value_00110 "DQ" + attribute \enum_value_00111 "DX" + attribute \enum_value_01000 "X" + attribute \enum_value_01001 "XL" + attribute \enum_value_01010 "XFX" + attribute \enum_value_01011 "XFL" + attribute \enum_value_01100 "XX1" + attribute \enum_value_01101 "XX2" + attribute \enum_value_01110 "XX3" + attribute \enum_value_01111 "XX4" + attribute \enum_value_10000 "XS" + attribute \enum_value_10001 "XO" + attribute \enum_value_10010 "A" + attribute \enum_value_10011 "M" + attribute \enum_value_10100 "MD" + attribute \enum_value_10101 "MDS" + attribute \enum_value_10110 "VA" + attribute \enum_value_10111 "VC" + attribute \enum_value_11000 "VX" + attribute \enum_value_11001 "EVX" + attribute \enum_value_11010 "EVS" + attribute \enum_value_11011 "Z22" + attribute \enum_value_11100 "Z23" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 5 output 3 \dec31_dec_sub9_form + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 12 output 1 \dec31_dec_sub9_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 5 \dec31_dec_sub9_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 output 6 \dec31_dec_sub9_in2_sel + attribute \enum_base_type "In3Sel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RS" + attribute \enum_value_10 "RB" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 7 \dec31_dec_sub9_in3_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 7 output 2 \dec31_dec_sub9_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 15 \dec31_dec_sub9_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 16 \dec31_dec_sub9_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 21 \dec31_dec_sub9_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 output 11 \dec31_dec_sub9_ldst_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 23 \dec31_dec_sub9_lk + attribute \enum_base_type "OutSel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RT" + attribute \enum_value_10 "RA" + attribute \enum_value_11 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 8 \dec31_dec_sub9_out_sel + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 13 \dec31_dec_sub9_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 20 \dec31_dec_sub9_rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 24 \dec31_dec_sub9_sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 22 \dec31_dec_sub9_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 19 \dec31_dec_sub9_sgn_ext + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 12 \dec31_dec_sub9_upd + attribute \src "issuer_ls180.v:101177.7-101177.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + wire width 32 input 25 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:320" + wire width 5 \opcode_switch + attribute \src "issuer_ls180.v:101177.7-101177.20" + process $proc$issuer_ls180.v:101177$4045 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "issuer_ls180.v:101434.3-101488.6" + process $proc$issuer_ls180.v:101434$4021 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub9_function_unit[11:0] $1\dec31_dec_sub9_function_unit[11:0] + attribute \src "issuer_ls180.v:101435.5-101435.29" + switch \initial + attribute \src "issuer_ls180.v:101435.9-101435.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub9_function_unit[11:0] 12'001000000000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub9_function_unit[11:0] 12'001000000000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub9_function_unit[11:0] 12'001000000000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub9_function_unit[11:0] 12'001000000000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub9_function_unit[11:0] 12'001000000000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub9_function_unit[11:0] 12'001000000000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub9_function_unit[11:0] 12'001000000000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub9_function_unit[11:0] 12'001000000000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub9_function_unit[11:0] 12'001000000000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub9_function_unit[11:0] 12'001000000000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub9_function_unit[11:0] 12'000100000000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub9_function_unit[11:0] 12'000100000000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub9_function_unit[11:0] 12'000100000000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub9_function_unit[11:0] 12'000100000000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub9_function_unit[11:0] 12'000100000000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub9_function_unit[11:0] 12'000100000000 + case + assign $1\dec31_dec_sub9_function_unit[11:0] 12'000000000000 + end + sync always + update \dec31_dec_sub9_function_unit $0\dec31_dec_sub9_function_unit[11:0] + end + attribute \src "issuer_ls180.v:101489.3-101543.6" + process $proc$issuer_ls180.v:101489$4022 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub9_ldst_len[3:0] $1\dec31_dec_sub9_ldst_len[3:0] + attribute \src "issuer_ls180.v:101490.5-101490.29" + switch \initial + attribute \src "issuer_ls180.v:101490.9-101490.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub9_ldst_len[3:0] 4'0000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub9_ldst_len[3:0] 4'0000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub9_ldst_len[3:0] 4'0000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub9_ldst_len[3:0] 4'0000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub9_ldst_len[3:0] 4'0000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub9_ldst_len[3:0] 4'0000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub9_ldst_len[3:0] 4'0000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub9_ldst_len[3:0] 4'0000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub9_ldst_len[3:0] 4'0000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub9_ldst_len[3:0] 4'0000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub9_ldst_len[3:0] 4'0000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub9_ldst_len[3:0] 4'0000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub9_ldst_len[3:0] 4'0000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub9_ldst_len[3:0] 4'0000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub9_ldst_len[3:0] 4'0000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub9_ldst_len[3:0] 4'0000 + case + assign $1\dec31_dec_sub9_ldst_len[3:0] 4'0000 + end + sync always + update \dec31_dec_sub9_ldst_len $0\dec31_dec_sub9_ldst_len[3:0] + end + attribute \src "issuer_ls180.v:101544.3-101598.6" + process $proc$issuer_ls180.v:101544$4023 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub9_upd[1:0] $1\dec31_dec_sub9_upd[1:0] + attribute \src "issuer_ls180.v:101545.5-101545.29" + switch \initial + attribute \src "issuer_ls180.v:101545.9-101545.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub9_upd[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub9_upd[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub9_upd[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub9_upd[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub9_upd[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub9_upd[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub9_upd[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub9_upd[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub9_upd[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub9_upd[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub9_upd[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub9_upd[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub9_upd[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub9_upd[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub9_upd[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub9_upd[1:0] 2'00 + case + assign $1\dec31_dec_sub9_upd[1:0] 2'00 + end + sync always + update \dec31_dec_sub9_upd $0\dec31_dec_sub9_upd[1:0] + end + attribute \src "issuer_ls180.v:101599.3-101653.6" + process $proc$issuer_ls180.v:101599$4024 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub9_rc_sel[1:0] $1\dec31_dec_sub9_rc_sel[1:0] + attribute \src "issuer_ls180.v:101600.5-101600.29" + switch \initial + attribute \src "issuer_ls180.v:101600.9-101600.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub9_rc_sel[1:0] 2'10 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub9_rc_sel[1:0] 2'10 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub9_rc_sel[1:0] 2'10 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub9_rc_sel[1:0] 2'10 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub9_rc_sel[1:0] 2'10 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub9_rc_sel[1:0] 2'10 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub9_rc_sel[1:0] 2'10 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub9_rc_sel[1:0] 2'10 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub9_rc_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub9_rc_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub9_rc_sel[1:0] 2'10 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub9_rc_sel[1:0] 2'10 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub9_rc_sel[1:0] 2'10 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub9_rc_sel[1:0] 2'10 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub9_rc_sel[1:0] 2'10 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub9_rc_sel[1:0] 2'10 + case + assign $1\dec31_dec_sub9_rc_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub9_rc_sel $0\dec31_dec_sub9_rc_sel[1:0] + end + attribute \src "issuer_ls180.v:101654.3-101708.6" + process $proc$issuer_ls180.v:101654$4025 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub9_cry_in[1:0] $1\dec31_dec_sub9_cry_in[1:0] + attribute \src "issuer_ls180.v:101655.5-101655.29" + switch \initial + attribute \src "issuer_ls180.v:101655.9-101655.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub9_cry_in[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub9_cry_in[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub9_cry_in[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub9_cry_in[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub9_cry_in[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub9_cry_in[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub9_cry_in[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub9_cry_in[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub9_cry_in[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub9_cry_in[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub9_cry_in[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub9_cry_in[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub9_cry_in[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub9_cry_in[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub9_cry_in[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub9_cry_in[1:0] 2'00 + case + assign $1\dec31_dec_sub9_cry_in[1:0] 2'00 + end + sync always + update \dec31_dec_sub9_cry_in $0\dec31_dec_sub9_cry_in[1:0] + end + attribute \src "issuer_ls180.v:101709.3-101763.6" + process $proc$issuer_ls180.v:101709$4026 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub9_asmcode[7:0] $1\dec31_dec_sub9_asmcode[7:0] + attribute \src "issuer_ls180.v:101710.5-101710.29" + switch \initial + attribute \src "issuer_ls180.v:101710.9-101710.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub9_asmcode[7:0] 8'00110110 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub9_asmcode[7:0] 8'00110111 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub9_asmcode[7:0] 8'00110100 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub9_asmcode[7:0] 8'00110101 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub9_asmcode[7:0] 8'00111001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub9_asmcode[7:0] 8'00111010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub9_asmcode[7:0] 8'00110011 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub9_asmcode[7:0] 8'00111000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub9_asmcode[7:0] 8'01110100 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub9_asmcode[7:0] 8'01110010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub9_asmcode[7:0] 8'01111010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub9_asmcode[7:0] 8'01111011 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub9_asmcode[7:0] 8'01111010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub9_asmcode[7:0] 8'01111011 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub9_asmcode[7:0] 8'01111110 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub9_asmcode[7:0] 8'01111111 + case + assign $1\dec31_dec_sub9_asmcode[7:0] 8'00000000 + end + sync always + update \dec31_dec_sub9_asmcode $0\dec31_dec_sub9_asmcode[7:0] + end + attribute \src "issuer_ls180.v:101764.3-101818.6" + process $proc$issuer_ls180.v:101764$4027 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub9_inv_a[0:0] $1\dec31_dec_sub9_inv_a[0:0] + attribute \src "issuer_ls180.v:101765.5-101765.29" + switch \initial + attribute \src "issuer_ls180.v:101765.9-101765.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub9_inv_a[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub9_inv_a[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub9_inv_a[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub9_inv_a[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub9_inv_a[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub9_inv_a[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub9_inv_a[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub9_inv_a[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub9_inv_a[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub9_inv_a[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub9_inv_a[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub9_inv_a[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub9_inv_a[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub9_inv_a[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub9_inv_a[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub9_inv_a[0:0] 1'0 + case + assign $1\dec31_dec_sub9_inv_a[0:0] 1'0 + end + sync always + update \dec31_dec_sub9_inv_a $0\dec31_dec_sub9_inv_a[0:0] + end + attribute \src "issuer_ls180.v:101819.3-101873.6" + process $proc$issuer_ls180.v:101819$4028 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub9_inv_out[0:0] $1\dec31_dec_sub9_inv_out[0:0] + attribute \src "issuer_ls180.v:101820.5-101820.29" + switch \initial + attribute \src "issuer_ls180.v:101820.9-101820.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub9_inv_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub9_inv_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub9_inv_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub9_inv_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub9_inv_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub9_inv_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub9_inv_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub9_inv_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub9_inv_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub9_inv_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub9_inv_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub9_inv_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub9_inv_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub9_inv_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub9_inv_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub9_inv_out[0:0] 1'0 + case + assign $1\dec31_dec_sub9_inv_out[0:0] 1'0 + end + sync always + update \dec31_dec_sub9_inv_out $0\dec31_dec_sub9_inv_out[0:0] + end + attribute \src "issuer_ls180.v:101874.3-101928.6" + process $proc$issuer_ls180.v:101874$4029 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub9_cry_out[0:0] $1\dec31_dec_sub9_cry_out[0:0] + attribute \src "issuer_ls180.v:101875.5-101875.29" + switch \initial + attribute \src "issuer_ls180.v:101875.9-101875.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub9_cry_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub9_cry_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub9_cry_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub9_cry_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub9_cry_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub9_cry_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub9_cry_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub9_cry_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub9_cry_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub9_cry_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub9_cry_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub9_cry_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub9_cry_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub9_cry_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub9_cry_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub9_cry_out[0:0] 1'0 + case + assign $1\dec31_dec_sub9_cry_out[0:0] 1'0 + end + sync always + update \dec31_dec_sub9_cry_out $0\dec31_dec_sub9_cry_out[0:0] + end + attribute \src "issuer_ls180.v:101929.3-101983.6" + process $proc$issuer_ls180.v:101929$4030 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub9_br[0:0] $1\dec31_dec_sub9_br[0:0] + attribute \src "issuer_ls180.v:101930.5-101930.29" + switch \initial + attribute \src "issuer_ls180.v:101930.9-101930.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub9_br[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub9_br[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub9_br[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub9_br[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub9_br[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub9_br[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub9_br[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub9_br[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub9_br[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub9_br[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub9_br[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub9_br[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub9_br[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub9_br[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub9_br[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub9_br[0:0] 1'0 + case + assign $1\dec31_dec_sub9_br[0:0] 1'0 + end + sync always + update \dec31_dec_sub9_br $0\dec31_dec_sub9_br[0:0] + end + attribute \src "issuer_ls180.v:101984.3-102038.6" + process $proc$issuer_ls180.v:101984$4031 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub9_sgn_ext[0:0] $1\dec31_dec_sub9_sgn_ext[0:0] + attribute \src "issuer_ls180.v:101985.5-101985.29" + switch \initial + attribute \src "issuer_ls180.v:101985.9-101985.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub9_sgn_ext[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub9_sgn_ext[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub9_sgn_ext[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub9_sgn_ext[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub9_sgn_ext[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub9_sgn_ext[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub9_sgn_ext[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub9_sgn_ext[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub9_sgn_ext[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub9_sgn_ext[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub9_sgn_ext[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub9_sgn_ext[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub9_sgn_ext[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub9_sgn_ext[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub9_sgn_ext[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub9_sgn_ext[0:0] 1'0 + case + assign $1\dec31_dec_sub9_sgn_ext[0:0] 1'0 + end + sync always + update \dec31_dec_sub9_sgn_ext $0\dec31_dec_sub9_sgn_ext[0:0] + end + attribute \src "issuer_ls180.v:102039.3-102093.6" + process $proc$issuer_ls180.v:102039$4032 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub9_internal_op[6:0] $1\dec31_dec_sub9_internal_op[6:0] + attribute \src "issuer_ls180.v:102040.5-102040.29" + switch \initial + attribute \src "issuer_ls180.v:102040.9-102040.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub9_internal_op[6:0] 7'0011110 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub9_internal_op[6:0] 7'0011110 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub9_internal_op[6:0] 7'0011110 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub9_internal_op[6:0] 7'0011110 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub9_internal_op[6:0] 7'0011101 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub9_internal_op[6:0] 7'0011101 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub9_internal_op[6:0] 7'0011101 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub9_internal_op[6:0] 7'0011101 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub9_internal_op[6:0] 7'0101111 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub9_internal_op[6:0] 7'0101111 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub9_internal_op[6:0] 7'0110011 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub9_internal_op[6:0] 7'0110011 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub9_internal_op[6:0] 7'0110011 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub9_internal_op[6:0] 7'0110011 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub9_internal_op[6:0] 7'0110010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub9_internal_op[6:0] 7'0110010 + case + assign $1\dec31_dec_sub9_internal_op[6:0] 7'0000000 + end + sync always + update \dec31_dec_sub9_internal_op $0\dec31_dec_sub9_internal_op[6:0] + end + attribute \src "issuer_ls180.v:102094.3-102148.6" + process $proc$issuer_ls180.v:102094$4033 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub9_rsrv[0:0] $1\dec31_dec_sub9_rsrv[0:0] + attribute \src "issuer_ls180.v:102095.5-102095.29" + switch \initial + attribute \src "issuer_ls180.v:102095.9-102095.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub9_rsrv[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub9_rsrv[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub9_rsrv[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub9_rsrv[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub9_rsrv[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub9_rsrv[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub9_rsrv[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub9_rsrv[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub9_rsrv[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub9_rsrv[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub9_rsrv[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub9_rsrv[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub9_rsrv[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub9_rsrv[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub9_rsrv[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub9_rsrv[0:0] 1'0 + case + assign $1\dec31_dec_sub9_rsrv[0:0] 1'0 + end + sync always + update \dec31_dec_sub9_rsrv $0\dec31_dec_sub9_rsrv[0:0] + end + attribute \src "issuer_ls180.v:102149.3-102203.6" + process $proc$issuer_ls180.v:102149$4034 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub9_is_32b[0:0] $1\dec31_dec_sub9_is_32b[0:0] + attribute \src "issuer_ls180.v:102150.5-102150.29" + switch \initial + attribute \src "issuer_ls180.v:102150.9-102150.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub9_is_32b[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub9_is_32b[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub9_is_32b[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub9_is_32b[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub9_is_32b[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub9_is_32b[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub9_is_32b[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub9_is_32b[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub9_is_32b[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub9_is_32b[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub9_is_32b[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub9_is_32b[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub9_is_32b[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub9_is_32b[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub9_is_32b[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub9_is_32b[0:0] 1'0 + case + assign $1\dec31_dec_sub9_is_32b[0:0] 1'0 + end + sync always + update \dec31_dec_sub9_is_32b $0\dec31_dec_sub9_is_32b[0:0] + end + attribute \src "issuer_ls180.v:102204.3-102258.6" + process $proc$issuer_ls180.v:102204$4035 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub9_sgn[0:0] $1\dec31_dec_sub9_sgn[0:0] + attribute \src "issuer_ls180.v:102205.5-102205.29" + switch \initial + attribute \src "issuer_ls180.v:102205.9-102205.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub9_sgn[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub9_sgn[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub9_sgn[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub9_sgn[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub9_sgn[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub9_sgn[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub9_sgn[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub9_sgn[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub9_sgn[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub9_sgn[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub9_sgn[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub9_sgn[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub9_sgn[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub9_sgn[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub9_sgn[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub9_sgn[0:0] 1'1 + case + assign $1\dec31_dec_sub9_sgn[0:0] 1'0 + end + sync always + update \dec31_dec_sub9_sgn $0\dec31_dec_sub9_sgn[0:0] + end + attribute \src "issuer_ls180.v:102259.3-102313.6" + process $proc$issuer_ls180.v:102259$4036 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub9_lk[0:0] $1\dec31_dec_sub9_lk[0:0] + attribute \src "issuer_ls180.v:102260.5-102260.29" + switch \initial + attribute \src "issuer_ls180.v:102260.9-102260.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub9_lk[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub9_lk[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub9_lk[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub9_lk[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub9_lk[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub9_lk[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub9_lk[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub9_lk[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub9_lk[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub9_lk[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub9_lk[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub9_lk[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub9_lk[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub9_lk[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub9_lk[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub9_lk[0:0] 1'0 + case + assign $1\dec31_dec_sub9_lk[0:0] 1'0 + end + sync always + update \dec31_dec_sub9_lk $0\dec31_dec_sub9_lk[0:0] + end + attribute \src "issuer_ls180.v:102314.3-102368.6" + process $proc$issuer_ls180.v:102314$4037 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub9_sgl_pipe[0:0] $1\dec31_dec_sub9_sgl_pipe[0:0] + attribute \src "issuer_ls180.v:102315.5-102315.29" + switch \initial + attribute \src "issuer_ls180.v:102315.9-102315.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub9_sgl_pipe[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub9_sgl_pipe[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub9_sgl_pipe[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub9_sgl_pipe[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub9_sgl_pipe[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub9_sgl_pipe[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub9_sgl_pipe[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub9_sgl_pipe[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub9_sgl_pipe[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub9_sgl_pipe[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub9_sgl_pipe[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub9_sgl_pipe[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub9_sgl_pipe[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub9_sgl_pipe[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub9_sgl_pipe[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub9_sgl_pipe[0:0] 1'0 + case + assign $1\dec31_dec_sub9_sgl_pipe[0:0] 1'0 + end + sync always + update \dec31_dec_sub9_sgl_pipe $0\dec31_dec_sub9_sgl_pipe[0:0] + end + attribute \src "issuer_ls180.v:102369.3-102423.6" + process $proc$issuer_ls180.v:102369$4038 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub9_form[4:0] $1\dec31_dec_sub9_form[4:0] + attribute \src "issuer_ls180.v:102370.5-102370.29" + switch \initial + attribute \src "issuer_ls180.v:102370.9-102370.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub9_form[4:0] 5'10001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub9_form[4:0] 5'10001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub9_form[4:0] 5'10001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub9_form[4:0] 5'10001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub9_form[4:0] 5'10001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub9_form[4:0] 5'10001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub9_form[4:0] 5'10001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub9_form[4:0] 5'10001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub9_form[4:0] 5'01000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub9_form[4:0] 5'01000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub9_form[4:0] 5'10001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub9_form[4:0] 5'10001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub9_form[4:0] 5'10001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub9_form[4:0] 5'10001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub9_form[4:0] 5'10001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub9_form[4:0] 5'10001 + case + assign $1\dec31_dec_sub9_form[4:0] 5'00000 + end + sync always + update \dec31_dec_sub9_form $0\dec31_dec_sub9_form[4:0] + end + attribute \src "issuer_ls180.v:102424.3-102478.6" + process $proc$issuer_ls180.v:102424$4039 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub9_in1_sel[2:0] $1\dec31_dec_sub9_in1_sel[2:0] + attribute \src "issuer_ls180.v:102425.5-102425.29" + switch \initial + attribute \src "issuer_ls180.v:102425.9-102425.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub9_in1_sel[2:0] 3'001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub9_in1_sel[2:0] 3'001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub9_in1_sel[2:0] 3'001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub9_in1_sel[2:0] 3'001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub9_in1_sel[2:0] 3'001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub9_in1_sel[2:0] 3'001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub9_in1_sel[2:0] 3'001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub9_in1_sel[2:0] 3'001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub9_in1_sel[2:0] 3'001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub9_in1_sel[2:0] 3'001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub9_in1_sel[2:0] 3'001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub9_in1_sel[2:0] 3'001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub9_in1_sel[2:0] 3'001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub9_in1_sel[2:0] 3'001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub9_in1_sel[2:0] 3'001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub9_in1_sel[2:0] 3'001 + case + assign $1\dec31_dec_sub9_in1_sel[2:0] 3'000 + end + sync always + update \dec31_dec_sub9_in1_sel $0\dec31_dec_sub9_in1_sel[2:0] + end + attribute \src "issuer_ls180.v:102479.3-102533.6" + process $proc$issuer_ls180.v:102479$4040 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub9_in2_sel[3:0] $1\dec31_dec_sub9_in2_sel[3:0] + attribute \src "issuer_ls180.v:102480.5-102480.29" + switch \initial + attribute \src "issuer_ls180.v:102480.9-102480.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub9_in2_sel[3:0] 4'0001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub9_in2_sel[3:0] 4'0001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub9_in2_sel[3:0] 4'0001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub9_in2_sel[3:0] 4'0001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub9_in2_sel[3:0] 4'0001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub9_in2_sel[3:0] 4'0001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub9_in2_sel[3:0] 4'0001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub9_in2_sel[3:0] 4'0001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub9_in2_sel[3:0] 4'0001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub9_in2_sel[3:0] 4'0001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub9_in2_sel[3:0] 4'0001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub9_in2_sel[3:0] 4'0001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub9_in2_sel[3:0] 4'0001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub9_in2_sel[3:0] 4'0001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub9_in2_sel[3:0] 4'0001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub9_in2_sel[3:0] 4'0001 + case + assign $1\dec31_dec_sub9_in2_sel[3:0] 4'0000 + end + sync always + update \dec31_dec_sub9_in2_sel $0\dec31_dec_sub9_in2_sel[3:0] + end + attribute \src "issuer_ls180.v:102534.3-102588.6" + process $proc$issuer_ls180.v:102534$4041 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub9_in3_sel[1:0] $1\dec31_dec_sub9_in3_sel[1:0] + attribute \src "issuer_ls180.v:102535.5-102535.29" + switch \initial + attribute \src "issuer_ls180.v:102535.9-102535.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub9_in3_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub9_in3_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub9_in3_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub9_in3_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub9_in3_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub9_in3_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub9_in3_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub9_in3_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub9_in3_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub9_in3_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub9_in3_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub9_in3_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub9_in3_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub9_in3_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub9_in3_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub9_in3_sel[1:0] 2'00 + case + assign $1\dec31_dec_sub9_in3_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub9_in3_sel $0\dec31_dec_sub9_in3_sel[1:0] + end + attribute \src "issuer_ls180.v:102589.3-102643.6" + process $proc$issuer_ls180.v:102589$4042 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub9_out_sel[1:0] $1\dec31_dec_sub9_out_sel[1:0] + attribute \src "issuer_ls180.v:102590.5-102590.29" + switch \initial + attribute \src "issuer_ls180.v:102590.9-102590.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub9_out_sel[1:0] 2'01 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub9_out_sel[1:0] 2'01 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub9_out_sel[1:0] 2'01 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub9_out_sel[1:0] 2'01 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub9_out_sel[1:0] 2'01 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub9_out_sel[1:0] 2'01 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub9_out_sel[1:0] 2'01 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub9_out_sel[1:0] 2'01 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub9_out_sel[1:0] 2'01 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub9_out_sel[1:0] 2'01 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub9_out_sel[1:0] 2'01 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub9_out_sel[1:0] 2'01 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub9_out_sel[1:0] 2'01 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub9_out_sel[1:0] 2'01 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub9_out_sel[1:0] 2'01 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub9_out_sel[1:0] 2'01 + case + assign $1\dec31_dec_sub9_out_sel[1:0] 2'00 + end + sync always + update \dec31_dec_sub9_out_sel $0\dec31_dec_sub9_out_sel[1:0] + end + attribute \src "issuer_ls180.v:102644.3-102698.6" + process $proc$issuer_ls180.v:102644$4043 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub9_cr_in[2:0] $1\dec31_dec_sub9_cr_in[2:0] + attribute \src "issuer_ls180.v:102645.5-102645.29" + switch \initial + attribute \src "issuer_ls180.v:102645.9-102645.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub9_cr_in[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub9_cr_in[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub9_cr_in[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub9_cr_in[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub9_cr_in[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub9_cr_in[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub9_cr_in[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub9_cr_in[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub9_cr_in[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub9_cr_in[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub9_cr_in[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub9_cr_in[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub9_cr_in[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub9_cr_in[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub9_cr_in[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub9_cr_in[2:0] 3'000 + case + assign $1\dec31_dec_sub9_cr_in[2:0] 3'000 + end + sync always + update \dec31_dec_sub9_cr_in $0\dec31_dec_sub9_cr_in[2:0] + end + attribute \src "issuer_ls180.v:102699.3-102753.6" + process $proc$issuer_ls180.v:102699$4044 + assign { } { } + assign { } { } + assign $0\dec31_dec_sub9_cr_out[2:0] $1\dec31_dec_sub9_cr_out[2:0] + attribute \src "issuer_ls180.v:102700.5-102700.29" + switch \initial + attribute \src "issuer_ls180.v:102700.9-102700.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01100 + assign { } { } + assign $1\dec31_dec_sub9_cr_out[2:0] 3'001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11100 + assign { } { } + assign $1\dec31_dec_sub9_cr_out[2:0] 3'001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01101 + assign { } { } + assign $1\dec31_dec_sub9_cr_out[2:0] 3'001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11101 + assign { } { } + assign $1\dec31_dec_sub9_cr_out[2:0] 3'001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01110 + assign { } { } + assign $1\dec31_dec_sub9_cr_out[2:0] 3'001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11110 + assign { } { } + assign $1\dec31_dec_sub9_cr_out[2:0] 3'001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01111 + assign { } { } + assign $1\dec31_dec_sub9_cr_out[2:0] 3'001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11111 + assign { } { } + assign $1\dec31_dec_sub9_cr_out[2:0] 3'001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'01000 + assign { } { } + assign $1\dec31_dec_sub9_cr_out[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'11000 + assign { } { } + assign $1\dec31_dec_sub9_cr_out[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00010 + assign { } { } + assign $1\dec31_dec_sub9_cr_out[2:0] 3'001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00000 + assign { } { } + assign $1\dec31_dec_sub9_cr_out[2:0] 3'001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10010 + assign { } { } + assign $1\dec31_dec_sub9_cr_out[2:0] 3'001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10000 + assign { } { } + assign $1\dec31_dec_sub9_cr_out[2:0] 3'001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'00111 + assign { } { } + assign $1\dec31_dec_sub9_cr_out[2:0] 3'001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 5'10111 + assign { } { } + assign $1\dec31_dec_sub9_cr_out[2:0] 3'001 + case + assign $1\dec31_dec_sub9_cr_out[2:0] 3'000 + end + sync always + update \dec31_dec_sub9_cr_out $0\dec31_dec_sub9_cr_out[2:0] + end + connect \opcode_switch \opcode_in [10:6] +end +attribute \src "issuer_ls180.v:102759.1-103402.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.dec2.dec.dec58" +attribute \generator "nMigen" +module \dec58 + attribute \src "issuer_ls180.v:103097.3-103112.6" + wire width 8 $0\dec58_asmcode[7:0] + attribute \src "issuer_ls180.v:103161.3-103176.6" + wire $0\dec58_br[0:0] + attribute \src "issuer_ls180.v:103369.3-103384.6" + wire width 3 $0\dec58_cr_in[2:0] + attribute \src "issuer_ls180.v:103385.3-103400.6" + wire width 3 $0\dec58_cr_out[2:0] + attribute \src "issuer_ls180.v:103081.3-103096.6" + wire width 2 $0\dec58_cry_in[1:0] + attribute \src "issuer_ls180.v:103145.3-103160.6" + wire $0\dec58_cry_out[0:0] + attribute \src "issuer_ls180.v:103289.3-103304.6" + wire width 5 $0\dec58_form[4:0] + attribute \src "issuer_ls180.v:103017.3-103032.6" + wire width 12 $0\dec58_function_unit[11:0] + attribute \src "issuer_ls180.v:103305.3-103320.6" + wire width 3 $0\dec58_in1_sel[2:0] + attribute \src "issuer_ls180.v:103321.3-103336.6" + wire width 4 $0\dec58_in2_sel[3:0] + attribute \src "issuer_ls180.v:103337.3-103352.6" + wire width 2 $0\dec58_in3_sel[1:0] + attribute \src "issuer_ls180.v:103193.3-103208.6" + wire width 7 $0\dec58_internal_op[6:0] + attribute \src "issuer_ls180.v:103113.3-103128.6" + wire $0\dec58_inv_a[0:0] + attribute \src "issuer_ls180.v:103129.3-103144.6" + wire $0\dec58_inv_out[0:0] + attribute \src "issuer_ls180.v:103225.3-103240.6" + wire $0\dec58_is_32b[0:0] + attribute \src "issuer_ls180.v:103033.3-103048.6" + wire width 4 $0\dec58_ldst_len[3:0] + attribute \src "issuer_ls180.v:103257.3-103272.6" + wire $0\dec58_lk[0:0] + attribute \src "issuer_ls180.v:103353.3-103368.6" + wire width 2 $0\dec58_out_sel[1:0] + attribute \src "issuer_ls180.v:103065.3-103080.6" + wire width 2 $0\dec58_rc_sel[1:0] + attribute \src "issuer_ls180.v:103209.3-103224.6" + wire $0\dec58_rsrv[0:0] + attribute \src "issuer_ls180.v:103273.3-103288.6" + wire $0\dec58_sgl_pipe[0:0] + attribute \src "issuer_ls180.v:103241.3-103256.6" + wire $0\dec58_sgn[0:0] + attribute \src "issuer_ls180.v:103177.3-103192.6" + wire $0\dec58_sgn_ext[0:0] + attribute \src "issuer_ls180.v:103049.3-103064.6" + wire width 2 $0\dec58_upd[1:0] + attribute \src "issuer_ls180.v:102760.7-102760.20" + wire $0\initial[0:0] + attribute \src "issuer_ls180.v:103097.3-103112.6" + wire width 8 $1\dec58_asmcode[7:0] + attribute \src "issuer_ls180.v:103161.3-103176.6" + wire $1\dec58_br[0:0] + attribute \src "issuer_ls180.v:103369.3-103384.6" + wire width 3 $1\dec58_cr_in[2:0] + attribute \src "issuer_ls180.v:103385.3-103400.6" + wire width 3 $1\dec58_cr_out[2:0] + attribute \src "issuer_ls180.v:103081.3-103096.6" + wire width 2 $1\dec58_cry_in[1:0] + attribute \src "issuer_ls180.v:103145.3-103160.6" + wire $1\dec58_cry_out[0:0] + attribute \src "issuer_ls180.v:103289.3-103304.6" + wire width 5 $1\dec58_form[4:0] + attribute \src "issuer_ls180.v:103017.3-103032.6" + wire width 12 $1\dec58_function_unit[11:0] + attribute \src "issuer_ls180.v:103305.3-103320.6" + wire width 3 $1\dec58_in1_sel[2:0] + attribute \src "issuer_ls180.v:103321.3-103336.6" + wire width 4 $1\dec58_in2_sel[3:0] + attribute \src "issuer_ls180.v:103337.3-103352.6" + wire width 2 $1\dec58_in3_sel[1:0] + attribute \src "issuer_ls180.v:103193.3-103208.6" + wire width 7 $1\dec58_internal_op[6:0] + attribute \src "issuer_ls180.v:103113.3-103128.6" + wire $1\dec58_inv_a[0:0] + attribute \src "issuer_ls180.v:103129.3-103144.6" + wire $1\dec58_inv_out[0:0] + attribute \src "issuer_ls180.v:103225.3-103240.6" + wire $1\dec58_is_32b[0:0] + attribute \src "issuer_ls180.v:103033.3-103048.6" + wire width 4 $1\dec58_ldst_len[3:0] + attribute \src "issuer_ls180.v:103257.3-103272.6" + wire $1\dec58_lk[0:0] + attribute \src "issuer_ls180.v:103353.3-103368.6" + wire width 2 $1\dec58_out_sel[1:0] + attribute \src "issuer_ls180.v:103065.3-103080.6" + wire width 2 $1\dec58_rc_sel[1:0] + attribute \src "issuer_ls180.v:103209.3-103224.6" + wire $1\dec58_rsrv[0:0] + attribute \src "issuer_ls180.v:103273.3-103288.6" + wire $1\dec58_sgl_pipe[0:0] + attribute \src "issuer_ls180.v:103241.3-103256.6" + wire $1\dec58_sgn[0:0] + attribute \src "issuer_ls180.v:103177.3-103192.6" + wire $1\dec58_sgn_ext[0:0] + attribute \src "issuer_ls180.v:103049.3-103064.6" + wire width 2 $1\dec58_upd[1:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 8 output 4 \dec58_asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 18 \dec58_br + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 9 \dec58_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 10 \dec58_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 14 \dec58_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 17 \dec58_cry_out + attribute \enum_base_type "Form" + attribute \enum_value_00000 "NONE" + attribute \enum_value_00001 "I" + attribute \enum_value_00010 "B" + attribute \enum_value_00011 "SC" + attribute \enum_value_00100 "D" + attribute \enum_value_00101 "DS" + attribute \enum_value_00110 "DQ" + attribute \enum_value_00111 "DX" + attribute \enum_value_01000 "X" + attribute \enum_value_01001 "XL" + attribute \enum_value_01010 "XFX" + attribute \enum_value_01011 "XFL" + attribute \enum_value_01100 "XX1" + attribute \enum_value_01101 "XX2" + attribute \enum_value_01110 "XX3" + attribute \enum_value_01111 "XX4" + attribute \enum_value_10000 "XS" + attribute \enum_value_10001 "XO" + attribute \enum_value_10010 "A" + attribute \enum_value_10011 "M" + attribute \enum_value_10100 "MD" + attribute \enum_value_10101 "MDS" + attribute \enum_value_10110 "VA" + attribute \enum_value_10111 "VC" + attribute \enum_value_11000 "VX" + attribute \enum_value_11001 "EVX" + attribute \enum_value_11010 "EVS" + attribute \enum_value_11011 "Z22" + attribute \enum_value_11100 "Z23" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 5 output 3 \dec58_form + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 12 output 1 \dec58_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 5 \dec58_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 output 6 \dec58_in2_sel + attribute \enum_base_type "In3Sel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RS" + attribute \enum_value_10 "RB" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 7 \dec58_in3_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 7 output 2 \dec58_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 15 \dec58_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 16 \dec58_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 21 \dec58_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 output 11 \dec58_ldst_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 23 \dec58_lk + attribute \enum_base_type "OutSel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RT" + attribute \enum_value_10 "RA" + attribute \enum_value_11 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 8 \dec58_out_sel + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 13 \dec58_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 20 \dec58_rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 24 \dec58_sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 22 \dec58_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 19 \dec58_sgn_ext + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 12 \dec58_upd + attribute \src "issuer_ls180.v:102760.7-102760.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + wire width 32 input 25 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:320" + wire width 2 \opcode_switch + attribute \src "issuer_ls180.v:102760.7-102760.20" + process $proc$issuer_ls180.v:102760$4070 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "issuer_ls180.v:103017.3-103032.6" + process $proc$issuer_ls180.v:103017$4046 + assign { } { } + assign { } { } + assign $0\dec58_function_unit[11:0] $1\dec58_function_unit[11:0] + attribute \src "issuer_ls180.v:103018.5-103018.29" + switch \initial + attribute \src "issuer_ls180.v:103018.9-103018.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec58_function_unit[11:0] 12'000000000100 + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec58_function_unit[11:0] 12'000000000100 + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\dec58_function_unit[11:0] 12'000000000100 + case + assign $1\dec58_function_unit[11:0] 12'000000000000 + end + sync always + update \dec58_function_unit $0\dec58_function_unit[11:0] + end + attribute \src "issuer_ls180.v:103033.3-103048.6" + process $proc$issuer_ls180.v:103033$4047 + assign { } { } + assign { } { } + assign $0\dec58_ldst_len[3:0] $1\dec58_ldst_len[3:0] + attribute \src "issuer_ls180.v:103034.5-103034.29" + switch \initial + attribute \src "issuer_ls180.v:103034.9-103034.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec58_ldst_len[3:0] 4'1000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec58_ldst_len[3:0] 4'1000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\dec58_ldst_len[3:0] 4'0100 + case + assign $1\dec58_ldst_len[3:0] 4'0000 + end + sync always + update \dec58_ldst_len $0\dec58_ldst_len[3:0] + end + attribute \src "issuer_ls180.v:103049.3-103064.6" + process $proc$issuer_ls180.v:103049$4048 + assign { } { } + assign { } { } + assign $0\dec58_upd[1:0] $1\dec58_upd[1:0] + attribute \src "issuer_ls180.v:103050.5-103050.29" + switch \initial + attribute \src "issuer_ls180.v:103050.9-103050.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec58_upd[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec58_upd[1:0] 2'01 + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\dec58_upd[1:0] 2'00 + case + assign $1\dec58_upd[1:0] 2'00 + end + sync always + update \dec58_upd $0\dec58_upd[1:0] + end + attribute \src "issuer_ls180.v:103065.3-103080.6" + process $proc$issuer_ls180.v:103065$4049 + assign { } { } + assign { } { } + assign $0\dec58_rc_sel[1:0] $1\dec58_rc_sel[1:0] + attribute \src "issuer_ls180.v:103066.5-103066.29" + switch \initial + attribute \src "issuer_ls180.v:103066.9-103066.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec58_rc_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec58_rc_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\dec58_rc_sel[1:0] 2'00 + case + assign $1\dec58_rc_sel[1:0] 2'00 + end + sync always + update \dec58_rc_sel $0\dec58_rc_sel[1:0] + end + attribute \src "issuer_ls180.v:103081.3-103096.6" + process $proc$issuer_ls180.v:103081$4050 + assign { } { } + assign { } { } + assign $0\dec58_cry_in[1:0] $1\dec58_cry_in[1:0] + attribute \src "issuer_ls180.v:103082.5-103082.29" + switch \initial + attribute \src "issuer_ls180.v:103082.9-103082.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec58_cry_in[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec58_cry_in[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\dec58_cry_in[1:0] 2'00 + case + assign $1\dec58_cry_in[1:0] 2'00 + end + sync always + update \dec58_cry_in $0\dec58_cry_in[1:0] + end + attribute \src "issuer_ls180.v:103097.3-103112.6" + process $proc$issuer_ls180.v:103097$4051 + assign { } { } + assign { } { } + assign $0\dec58_asmcode[7:0] $1\dec58_asmcode[7:0] + attribute \src "issuer_ls180.v:103098.5-103098.29" + switch \initial + attribute \src "issuer_ls180.v:103098.9-103098.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec58_asmcode[7:0] 8'01010010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec58_asmcode[7:0] 8'01010101 + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\dec58_asmcode[7:0] 8'01100010 + case + assign $1\dec58_asmcode[7:0] 8'00000000 + end + sync always + update \dec58_asmcode $0\dec58_asmcode[7:0] + end + attribute \src "issuer_ls180.v:103113.3-103128.6" + process $proc$issuer_ls180.v:103113$4052 + assign { } { } + assign { } { } + assign $0\dec58_inv_a[0:0] $1\dec58_inv_a[0:0] + attribute \src "issuer_ls180.v:103114.5-103114.29" + switch \initial + attribute \src "issuer_ls180.v:103114.9-103114.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec58_inv_a[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec58_inv_a[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\dec58_inv_a[0:0] 1'0 + case + assign $1\dec58_inv_a[0:0] 1'0 + end + sync always + update \dec58_inv_a $0\dec58_inv_a[0:0] + end + attribute \src "issuer_ls180.v:103129.3-103144.6" + process $proc$issuer_ls180.v:103129$4053 + assign { } { } + assign { } { } + assign $0\dec58_inv_out[0:0] $1\dec58_inv_out[0:0] + attribute \src "issuer_ls180.v:103130.5-103130.29" + switch \initial + attribute \src "issuer_ls180.v:103130.9-103130.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec58_inv_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec58_inv_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\dec58_inv_out[0:0] 1'0 + case + assign $1\dec58_inv_out[0:0] 1'0 + end + sync always + update \dec58_inv_out $0\dec58_inv_out[0:0] + end + attribute \src "issuer_ls180.v:103145.3-103160.6" + process $proc$issuer_ls180.v:103145$4054 + assign { } { } + assign { } { } + assign $0\dec58_cry_out[0:0] $1\dec58_cry_out[0:0] + attribute \src "issuer_ls180.v:103146.5-103146.29" + switch \initial + attribute \src "issuer_ls180.v:103146.9-103146.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec58_cry_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec58_cry_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\dec58_cry_out[0:0] 1'0 + case + assign $1\dec58_cry_out[0:0] 1'0 + end + sync always + update \dec58_cry_out $0\dec58_cry_out[0:0] + end + attribute \src "issuer_ls180.v:103161.3-103176.6" + process $proc$issuer_ls180.v:103161$4055 + assign { } { } + assign { } { } + assign $0\dec58_br[0:0] $1\dec58_br[0:0] + attribute \src "issuer_ls180.v:103162.5-103162.29" + switch \initial + attribute \src "issuer_ls180.v:103162.9-103162.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec58_br[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec58_br[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\dec58_br[0:0] 1'0 + case + assign $1\dec58_br[0:0] 1'0 + end + sync always + update \dec58_br $0\dec58_br[0:0] + end + attribute \src "issuer_ls180.v:103177.3-103192.6" + process $proc$issuer_ls180.v:103177$4056 + assign { } { } + assign { } { } + assign $0\dec58_sgn_ext[0:0] $1\dec58_sgn_ext[0:0] + attribute \src "issuer_ls180.v:103178.5-103178.29" + switch \initial + attribute \src "issuer_ls180.v:103178.9-103178.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec58_sgn_ext[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec58_sgn_ext[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\dec58_sgn_ext[0:0] 1'1 + case + assign $1\dec58_sgn_ext[0:0] 1'0 + end + sync always + update \dec58_sgn_ext $0\dec58_sgn_ext[0:0] + end + attribute \src "issuer_ls180.v:103193.3-103208.6" + process $proc$issuer_ls180.v:103193$4057 + assign { } { } + assign { } { } + assign $0\dec58_internal_op[6:0] $1\dec58_internal_op[6:0] + attribute \src "issuer_ls180.v:103194.5-103194.29" + switch \initial + attribute \src "issuer_ls180.v:103194.9-103194.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec58_internal_op[6:0] 7'0100101 + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec58_internal_op[6:0] 7'0100101 + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\dec58_internal_op[6:0] 7'0100101 + case + assign $1\dec58_internal_op[6:0] 7'0000000 + end + sync always + update \dec58_internal_op $0\dec58_internal_op[6:0] + end + attribute \src "issuer_ls180.v:103209.3-103224.6" + process $proc$issuer_ls180.v:103209$4058 + assign { } { } + assign { } { } + assign $0\dec58_rsrv[0:0] $1\dec58_rsrv[0:0] + attribute \src "issuer_ls180.v:103210.5-103210.29" + switch \initial + attribute \src "issuer_ls180.v:103210.9-103210.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec58_rsrv[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec58_rsrv[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\dec58_rsrv[0:0] 1'0 + case + assign $1\dec58_rsrv[0:0] 1'0 + end + sync always + update \dec58_rsrv $0\dec58_rsrv[0:0] + end + attribute \src "issuer_ls180.v:103225.3-103240.6" + process $proc$issuer_ls180.v:103225$4059 + assign { } { } + assign { } { } + assign $0\dec58_is_32b[0:0] $1\dec58_is_32b[0:0] + attribute \src "issuer_ls180.v:103226.5-103226.29" + switch \initial + attribute \src "issuer_ls180.v:103226.9-103226.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec58_is_32b[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec58_is_32b[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\dec58_is_32b[0:0] 1'0 + case + assign $1\dec58_is_32b[0:0] 1'0 + end + sync always + update \dec58_is_32b $0\dec58_is_32b[0:0] + end + attribute \src "issuer_ls180.v:103241.3-103256.6" + process $proc$issuer_ls180.v:103241$4060 + assign { } { } + assign { } { } + assign $0\dec58_sgn[0:0] $1\dec58_sgn[0:0] + attribute \src "issuer_ls180.v:103242.5-103242.29" + switch \initial + attribute \src "issuer_ls180.v:103242.9-103242.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec58_sgn[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec58_sgn[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\dec58_sgn[0:0] 1'0 + case + assign $1\dec58_sgn[0:0] 1'0 + end + sync always + update \dec58_sgn $0\dec58_sgn[0:0] + end + attribute \src "issuer_ls180.v:103257.3-103272.6" + process $proc$issuer_ls180.v:103257$4061 + assign { } { } + assign { } { } + assign $0\dec58_lk[0:0] $1\dec58_lk[0:0] + attribute \src "issuer_ls180.v:103258.5-103258.29" + switch \initial + attribute \src "issuer_ls180.v:103258.9-103258.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec58_lk[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec58_lk[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\dec58_lk[0:0] 1'0 + case + assign $1\dec58_lk[0:0] 1'0 + end + sync always + update \dec58_lk $0\dec58_lk[0:0] + end + attribute \src "issuer_ls180.v:103273.3-103288.6" + process $proc$issuer_ls180.v:103273$4062 + assign { } { } + assign { } { } + assign $0\dec58_sgl_pipe[0:0] $1\dec58_sgl_pipe[0:0] + attribute \src "issuer_ls180.v:103274.5-103274.29" + switch \initial + attribute \src "issuer_ls180.v:103274.9-103274.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec58_sgl_pipe[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec58_sgl_pipe[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\dec58_sgl_pipe[0:0] 1'1 + case + assign $1\dec58_sgl_pipe[0:0] 1'0 + end + sync always + update \dec58_sgl_pipe $0\dec58_sgl_pipe[0:0] + end + attribute \src "issuer_ls180.v:103289.3-103304.6" + process $proc$issuer_ls180.v:103289$4063 + assign { } { } + assign { } { } + assign $0\dec58_form[4:0] $1\dec58_form[4:0] + attribute \src "issuer_ls180.v:103290.5-103290.29" + switch \initial + attribute \src "issuer_ls180.v:103290.9-103290.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec58_form[4:0] 5'00101 + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec58_form[4:0] 5'00101 + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\dec58_form[4:0] 5'00101 + case + assign $1\dec58_form[4:0] 5'00000 + end + sync always + update \dec58_form $0\dec58_form[4:0] + end + attribute \src "issuer_ls180.v:103305.3-103320.6" + process $proc$issuer_ls180.v:103305$4064 + assign { } { } + assign { } { } + assign $0\dec58_in1_sel[2:0] $1\dec58_in1_sel[2:0] + attribute \src "issuer_ls180.v:103306.5-103306.29" + switch \initial + attribute \src "issuer_ls180.v:103306.9-103306.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec58_in1_sel[2:0] 3'010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec58_in1_sel[2:0] 3'010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\dec58_in1_sel[2:0] 3'010 + case + assign $1\dec58_in1_sel[2:0] 3'000 + end + sync always + update \dec58_in1_sel $0\dec58_in1_sel[2:0] + end + attribute \src "issuer_ls180.v:103321.3-103336.6" + process $proc$issuer_ls180.v:103321$4065 + assign { } { } + assign { } { } + assign $0\dec58_in2_sel[3:0] $1\dec58_in2_sel[3:0] + attribute \src "issuer_ls180.v:103322.5-103322.29" + switch \initial + attribute \src "issuer_ls180.v:103322.9-103322.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec58_in2_sel[3:0] 4'1000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec58_in2_sel[3:0] 4'1000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\dec58_in2_sel[3:0] 4'1000 + case + assign $1\dec58_in2_sel[3:0] 4'0000 + end + sync always + update \dec58_in2_sel $0\dec58_in2_sel[3:0] + end + attribute \src "issuer_ls180.v:103337.3-103352.6" + process $proc$issuer_ls180.v:103337$4066 + assign { } { } + assign { } { } + assign $0\dec58_in3_sel[1:0] $1\dec58_in3_sel[1:0] + attribute \src "issuer_ls180.v:103338.5-103338.29" + switch \initial + attribute \src "issuer_ls180.v:103338.9-103338.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec58_in3_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec58_in3_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\dec58_in3_sel[1:0] 2'00 + case + assign $1\dec58_in3_sel[1:0] 2'00 + end + sync always + update \dec58_in3_sel $0\dec58_in3_sel[1:0] + end + attribute \src "issuer_ls180.v:103353.3-103368.6" + process $proc$issuer_ls180.v:103353$4067 + assign { } { } + assign { } { } + assign $0\dec58_out_sel[1:0] $1\dec58_out_sel[1:0] + attribute \src "issuer_ls180.v:103354.5-103354.29" + switch \initial + attribute \src "issuer_ls180.v:103354.9-103354.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec58_out_sel[1:0] 2'01 + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec58_out_sel[1:0] 2'01 + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\dec58_out_sel[1:0] 2'01 + case + assign $1\dec58_out_sel[1:0] 2'00 + end + sync always + update \dec58_out_sel $0\dec58_out_sel[1:0] + end + attribute \src "issuer_ls180.v:103369.3-103384.6" + process $proc$issuer_ls180.v:103369$4068 + assign { } { } + assign { } { } + assign $0\dec58_cr_in[2:0] $1\dec58_cr_in[2:0] + attribute \src "issuer_ls180.v:103370.5-103370.29" + switch \initial + attribute \src "issuer_ls180.v:103370.9-103370.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec58_cr_in[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec58_cr_in[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\dec58_cr_in[2:0] 3'000 + case + assign $1\dec58_cr_in[2:0] 3'000 + end + sync always + update \dec58_cr_in $0\dec58_cr_in[2:0] + end + attribute \src "issuer_ls180.v:103385.3-103400.6" + process $proc$issuer_ls180.v:103385$4069 + assign { } { } + assign { } { } + assign $0\dec58_cr_out[2:0] $1\dec58_cr_out[2:0] + attribute \src "issuer_ls180.v:103386.5-103386.29" + switch \initial + attribute \src "issuer_ls180.v:103386.9-103386.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec58_cr_out[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec58_cr_out[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\dec58_cr_out[2:0] 3'000 + case + assign $1\dec58_cr_out[2:0] 3'000 + end + sync always + update \dec58_cr_out $0\dec58_cr_out[2:0] + end + connect \opcode_switch \opcode_in [1:0] +end +attribute \src "issuer_ls180.v:103406.1-103977.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.dec2.dec.dec62" +attribute \generator "nMigen" +module \dec62 + attribute \src "issuer_ls180.v:103729.3-103741.6" + wire width 8 $0\dec62_asmcode[7:0] + attribute \src "issuer_ls180.v:103781.3-103793.6" + wire $0\dec62_br[0:0] + attribute \src "issuer_ls180.v:103950.3-103962.6" + wire width 3 $0\dec62_cr_in[2:0] + attribute \src "issuer_ls180.v:103963.3-103975.6" + wire width 3 $0\dec62_cr_out[2:0] + attribute \src "issuer_ls180.v:103716.3-103728.6" + wire width 2 $0\dec62_cry_in[1:0] + attribute \src "issuer_ls180.v:103768.3-103780.6" + wire $0\dec62_cry_out[0:0] + attribute \src "issuer_ls180.v:103885.3-103897.6" + wire width 5 $0\dec62_form[4:0] + attribute \src "issuer_ls180.v:103664.3-103676.6" + wire width 12 $0\dec62_function_unit[11:0] + attribute \src "issuer_ls180.v:103898.3-103910.6" + wire width 3 $0\dec62_in1_sel[2:0] + attribute \src "issuer_ls180.v:103911.3-103923.6" + wire width 4 $0\dec62_in2_sel[3:0] + attribute \src "issuer_ls180.v:103924.3-103936.6" + wire width 2 $0\dec62_in3_sel[1:0] + attribute \src "issuer_ls180.v:103807.3-103819.6" + wire width 7 $0\dec62_internal_op[6:0] + attribute \src "issuer_ls180.v:103742.3-103754.6" + wire $0\dec62_inv_a[0:0] + attribute \src "issuer_ls180.v:103755.3-103767.6" + wire $0\dec62_inv_out[0:0] + attribute \src "issuer_ls180.v:103833.3-103845.6" + wire $0\dec62_is_32b[0:0] + attribute \src "issuer_ls180.v:103677.3-103689.6" + wire width 4 $0\dec62_ldst_len[3:0] + attribute \src "issuer_ls180.v:103859.3-103871.6" + wire $0\dec62_lk[0:0] + attribute \src "issuer_ls180.v:103937.3-103949.6" + wire width 2 $0\dec62_out_sel[1:0] + attribute \src "issuer_ls180.v:103703.3-103715.6" + wire width 2 $0\dec62_rc_sel[1:0] + attribute \src "issuer_ls180.v:103820.3-103832.6" + wire $0\dec62_rsrv[0:0] + attribute \src "issuer_ls180.v:103872.3-103884.6" + wire $0\dec62_sgl_pipe[0:0] + attribute \src "issuer_ls180.v:103846.3-103858.6" + wire $0\dec62_sgn[0:0] + attribute \src "issuer_ls180.v:103794.3-103806.6" + wire $0\dec62_sgn_ext[0:0] + attribute \src "issuer_ls180.v:103690.3-103702.6" + wire width 2 $0\dec62_upd[1:0] + attribute \src "issuer_ls180.v:103407.7-103407.20" + wire $0\initial[0:0] + attribute \src "issuer_ls180.v:103729.3-103741.6" + wire width 8 $1\dec62_asmcode[7:0] + attribute \src "issuer_ls180.v:103781.3-103793.6" + wire $1\dec62_br[0:0] + attribute \src "issuer_ls180.v:103950.3-103962.6" + wire width 3 $1\dec62_cr_in[2:0] + attribute \src "issuer_ls180.v:103963.3-103975.6" + wire width 3 $1\dec62_cr_out[2:0] + attribute \src "issuer_ls180.v:103716.3-103728.6" + wire width 2 $1\dec62_cry_in[1:0] + attribute \src "issuer_ls180.v:103768.3-103780.6" + wire $1\dec62_cry_out[0:0] + attribute \src "issuer_ls180.v:103885.3-103897.6" + wire width 5 $1\dec62_form[4:0] + attribute \src "issuer_ls180.v:103664.3-103676.6" + wire width 12 $1\dec62_function_unit[11:0] + attribute \src "issuer_ls180.v:103898.3-103910.6" + wire width 3 $1\dec62_in1_sel[2:0] + attribute \src "issuer_ls180.v:103911.3-103923.6" + wire width 4 $1\dec62_in2_sel[3:0] + attribute \src "issuer_ls180.v:103924.3-103936.6" + wire width 2 $1\dec62_in3_sel[1:0] + attribute \src "issuer_ls180.v:103807.3-103819.6" + wire width 7 $1\dec62_internal_op[6:0] + attribute \src "issuer_ls180.v:103742.3-103754.6" + wire $1\dec62_inv_a[0:0] + attribute \src "issuer_ls180.v:103755.3-103767.6" + wire $1\dec62_inv_out[0:0] + attribute \src "issuer_ls180.v:103833.3-103845.6" + wire $1\dec62_is_32b[0:0] + attribute \src "issuer_ls180.v:103677.3-103689.6" + wire width 4 $1\dec62_ldst_len[3:0] + attribute \src "issuer_ls180.v:103859.3-103871.6" + wire $1\dec62_lk[0:0] + attribute \src "issuer_ls180.v:103937.3-103949.6" + wire width 2 $1\dec62_out_sel[1:0] + attribute \src "issuer_ls180.v:103703.3-103715.6" + wire width 2 $1\dec62_rc_sel[1:0] + attribute \src "issuer_ls180.v:103820.3-103832.6" + wire $1\dec62_rsrv[0:0] + attribute \src "issuer_ls180.v:103872.3-103884.6" + wire $1\dec62_sgl_pipe[0:0] + attribute \src "issuer_ls180.v:103846.3-103858.6" + wire $1\dec62_sgn[0:0] + attribute \src "issuer_ls180.v:103794.3-103806.6" + wire $1\dec62_sgn_ext[0:0] + attribute \src "issuer_ls180.v:103690.3-103702.6" + wire width 2 $1\dec62_upd[1:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 8 output 4 \dec62_asmcode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 18 \dec62_br + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 9 \dec62_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 10 \dec62_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 14 \dec62_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 17 \dec62_cry_out + attribute \enum_base_type "Form" + attribute \enum_value_00000 "NONE" + attribute \enum_value_00001 "I" + attribute \enum_value_00010 "B" + attribute \enum_value_00011 "SC" + attribute \enum_value_00100 "D" + attribute \enum_value_00101 "DS" + attribute \enum_value_00110 "DQ" + attribute \enum_value_00111 "DX" + attribute \enum_value_01000 "X" + attribute \enum_value_01001 "XL" + attribute \enum_value_01010 "XFX" + attribute \enum_value_01011 "XFL" + attribute \enum_value_01100 "XX1" + attribute \enum_value_01101 "XX2" + attribute \enum_value_01110 "XX3" + attribute \enum_value_01111 "XX4" + attribute \enum_value_10000 "XS" + attribute \enum_value_10001 "XO" + attribute \enum_value_10010 "A" + attribute \enum_value_10011 "M" + attribute \enum_value_10100 "MD" + attribute \enum_value_10101 "MDS" + attribute \enum_value_10110 "VA" + attribute \enum_value_10111 "VC" + attribute \enum_value_11000 "VX" + attribute \enum_value_11001 "EVX" + attribute \enum_value_11010 "EVS" + attribute \enum_value_11011 "Z22" + attribute \enum_value_11100 "Z23" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 5 output 3 \dec62_form + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 12 output 1 \dec62_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 output 5 \dec62_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 output 6 \dec62_in2_sel + attribute \enum_base_type "In3Sel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RS" + attribute \enum_value_10 "RB" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 7 \dec62_in3_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 7 output 2 \dec62_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 15 \dec62_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 16 \dec62_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 21 \dec62_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 output 11 \dec62_ldst_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 23 \dec62_lk + attribute \enum_base_type "OutSel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RT" + attribute \enum_value_10 "RA" + attribute \enum_value_11 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 8 \dec62_out_sel + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 13 \dec62_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 20 \dec62_rsrv + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 24 \dec62_sgl_pipe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 22 \dec62_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire output 19 \dec62_sgn_ext + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 output 12 \dec62_upd + attribute \src "issuer_ls180.v:103407.7-103407.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + wire width 32 input 25 \opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:320" + wire width 2 \opcode_switch + attribute \src "issuer_ls180.v:103407.7-103407.20" + process $proc$issuer_ls180.v:103407$4095 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "issuer_ls180.v:103664.3-103676.6" + process $proc$issuer_ls180.v:103664$4071 + assign { } { } + assign { } { } + assign $0\dec62_function_unit[11:0] $1\dec62_function_unit[11:0] + attribute \src "issuer_ls180.v:103665.5-103665.29" + switch \initial + attribute \src "issuer_ls180.v:103665.9-103665.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec62_function_unit[11:0] 12'000000000100 + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec62_function_unit[11:0] 12'000000000100 + case + assign $1\dec62_function_unit[11:0] 12'000000000000 + end + sync always + update \dec62_function_unit $0\dec62_function_unit[11:0] + end + attribute \src "issuer_ls180.v:103677.3-103689.6" + process $proc$issuer_ls180.v:103677$4072 + assign { } { } + assign { } { } + assign $0\dec62_ldst_len[3:0] $1\dec62_ldst_len[3:0] + attribute \src "issuer_ls180.v:103678.5-103678.29" + switch \initial + attribute \src "issuer_ls180.v:103678.9-103678.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec62_ldst_len[3:0] 4'1000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec62_ldst_len[3:0] 4'1000 + case + assign $1\dec62_ldst_len[3:0] 4'0000 + end + sync always + update \dec62_ldst_len $0\dec62_ldst_len[3:0] + end + attribute \src "issuer_ls180.v:103690.3-103702.6" + process $proc$issuer_ls180.v:103690$4073 + assign { } { } + assign { } { } + assign $0\dec62_upd[1:0] $1\dec62_upd[1:0] + attribute \src "issuer_ls180.v:103691.5-103691.29" + switch \initial + attribute \src "issuer_ls180.v:103691.9-103691.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec62_upd[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec62_upd[1:0] 2'01 + case + assign $1\dec62_upd[1:0] 2'00 + end + sync always + update \dec62_upd $0\dec62_upd[1:0] + end + attribute \src "issuer_ls180.v:103703.3-103715.6" + process $proc$issuer_ls180.v:103703$4074 + assign { } { } + assign { } { } + assign $0\dec62_rc_sel[1:0] $1\dec62_rc_sel[1:0] + attribute \src "issuer_ls180.v:103704.5-103704.29" + switch \initial + attribute \src "issuer_ls180.v:103704.9-103704.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec62_rc_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec62_rc_sel[1:0] 2'00 + case + assign $1\dec62_rc_sel[1:0] 2'00 + end + sync always + update \dec62_rc_sel $0\dec62_rc_sel[1:0] + end + attribute \src "issuer_ls180.v:103716.3-103728.6" + process $proc$issuer_ls180.v:103716$4075 + assign { } { } + assign { } { } + assign $0\dec62_cry_in[1:0] $1\dec62_cry_in[1:0] + attribute \src "issuer_ls180.v:103717.5-103717.29" + switch \initial + attribute \src "issuer_ls180.v:103717.9-103717.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec62_cry_in[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec62_cry_in[1:0] 2'00 + case + assign $1\dec62_cry_in[1:0] 2'00 + end + sync always + update \dec62_cry_in $0\dec62_cry_in[1:0] + end + attribute \src "issuer_ls180.v:103729.3-103741.6" + process $proc$issuer_ls180.v:103729$4076 + assign { } { } + assign { } { } + assign $0\dec62_asmcode[7:0] $1\dec62_asmcode[7:0] + attribute \src "issuer_ls180.v:103730.5-103730.29" + switch \initial + attribute \src "issuer_ls180.v:103730.9-103730.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec62_asmcode[7:0] 8'10101100 + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec62_asmcode[7:0] 8'10101111 + case + assign $1\dec62_asmcode[7:0] 8'00000000 + end + sync always + update \dec62_asmcode $0\dec62_asmcode[7:0] + end + attribute \src "issuer_ls180.v:103742.3-103754.6" + process $proc$issuer_ls180.v:103742$4077 + assign { } { } + assign { } { } + assign $0\dec62_inv_a[0:0] $1\dec62_inv_a[0:0] + attribute \src "issuer_ls180.v:103743.5-103743.29" + switch \initial + attribute \src "issuer_ls180.v:103743.9-103743.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec62_inv_a[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec62_inv_a[0:0] 1'0 + case + assign $1\dec62_inv_a[0:0] 1'0 + end + sync always + update \dec62_inv_a $0\dec62_inv_a[0:0] + end + attribute \src "issuer_ls180.v:103755.3-103767.6" + process $proc$issuer_ls180.v:103755$4078 + assign { } { } + assign { } { } + assign $0\dec62_inv_out[0:0] $1\dec62_inv_out[0:0] + attribute \src "issuer_ls180.v:103756.5-103756.29" + switch \initial + attribute \src "issuer_ls180.v:103756.9-103756.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec62_inv_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec62_inv_out[0:0] 1'0 + case + assign $1\dec62_inv_out[0:0] 1'0 + end + sync always + update \dec62_inv_out $0\dec62_inv_out[0:0] + end + attribute \src "issuer_ls180.v:103768.3-103780.6" + process $proc$issuer_ls180.v:103768$4079 + assign { } { } + assign { } { } + assign $0\dec62_cry_out[0:0] $1\dec62_cry_out[0:0] + attribute \src "issuer_ls180.v:103769.5-103769.29" + switch \initial + attribute \src "issuer_ls180.v:103769.9-103769.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec62_cry_out[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec62_cry_out[0:0] 1'0 + case + assign $1\dec62_cry_out[0:0] 1'0 + end + sync always + update \dec62_cry_out $0\dec62_cry_out[0:0] + end + attribute \src "issuer_ls180.v:103781.3-103793.6" + process $proc$issuer_ls180.v:103781$4080 + assign { } { } + assign { } { } + assign $0\dec62_br[0:0] $1\dec62_br[0:0] + attribute \src "issuer_ls180.v:103782.5-103782.29" + switch \initial + attribute \src "issuer_ls180.v:103782.9-103782.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec62_br[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec62_br[0:0] 1'0 + case + assign $1\dec62_br[0:0] 1'0 + end + sync always + update \dec62_br $0\dec62_br[0:0] + end + attribute \src "issuer_ls180.v:103794.3-103806.6" + process $proc$issuer_ls180.v:103794$4081 + assign { } { } + assign { } { } + assign $0\dec62_sgn_ext[0:0] $1\dec62_sgn_ext[0:0] + attribute \src "issuer_ls180.v:103795.5-103795.29" + switch \initial + attribute \src "issuer_ls180.v:103795.9-103795.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec62_sgn_ext[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec62_sgn_ext[0:0] 1'0 + case + assign $1\dec62_sgn_ext[0:0] 1'0 + end + sync always + update \dec62_sgn_ext $0\dec62_sgn_ext[0:0] + end + attribute \src "issuer_ls180.v:103807.3-103819.6" + process $proc$issuer_ls180.v:103807$4082 + assign { } { } + assign { } { } + assign $0\dec62_internal_op[6:0] $1\dec62_internal_op[6:0] + attribute \src "issuer_ls180.v:103808.5-103808.29" + switch \initial + attribute \src "issuer_ls180.v:103808.9-103808.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec62_internal_op[6:0] 7'0100110 + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec62_internal_op[6:0] 7'0100110 + case + assign $1\dec62_internal_op[6:0] 7'0000000 + end + sync always + update \dec62_internal_op $0\dec62_internal_op[6:0] + end + attribute \src "issuer_ls180.v:103820.3-103832.6" + process $proc$issuer_ls180.v:103820$4083 + assign { } { } + assign { } { } + assign $0\dec62_rsrv[0:0] $1\dec62_rsrv[0:0] + attribute \src "issuer_ls180.v:103821.5-103821.29" + switch \initial + attribute \src "issuer_ls180.v:103821.9-103821.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec62_rsrv[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec62_rsrv[0:0] 1'0 + case + assign $1\dec62_rsrv[0:0] 1'0 + end + sync always + update \dec62_rsrv $0\dec62_rsrv[0:0] + end + attribute \src "issuer_ls180.v:103833.3-103845.6" + process $proc$issuer_ls180.v:103833$4084 + assign { } { } + assign { } { } + assign $0\dec62_is_32b[0:0] $1\dec62_is_32b[0:0] + attribute \src "issuer_ls180.v:103834.5-103834.29" + switch \initial + attribute \src "issuer_ls180.v:103834.9-103834.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec62_is_32b[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec62_is_32b[0:0] 1'0 + case + assign $1\dec62_is_32b[0:0] 1'0 + end + sync always + update \dec62_is_32b $0\dec62_is_32b[0:0] + end + attribute \src "issuer_ls180.v:103846.3-103858.6" + process $proc$issuer_ls180.v:103846$4085 + assign { } { } + assign { } { } + assign $0\dec62_sgn[0:0] $1\dec62_sgn[0:0] + attribute \src "issuer_ls180.v:103847.5-103847.29" + switch \initial + attribute \src "issuer_ls180.v:103847.9-103847.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec62_sgn[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec62_sgn[0:0] 1'0 + case + assign $1\dec62_sgn[0:0] 1'0 + end + sync always + update \dec62_sgn $0\dec62_sgn[0:0] + end + attribute \src "issuer_ls180.v:103859.3-103871.6" + process $proc$issuer_ls180.v:103859$4086 + assign { } { } + assign { } { } + assign $0\dec62_lk[0:0] $1\dec62_lk[0:0] + attribute \src "issuer_ls180.v:103860.5-103860.29" + switch \initial + attribute \src "issuer_ls180.v:103860.9-103860.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec62_lk[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec62_lk[0:0] 1'0 + case + assign $1\dec62_lk[0:0] 1'0 + end + sync always + update \dec62_lk $0\dec62_lk[0:0] + end + attribute \src "issuer_ls180.v:103872.3-103884.6" + process $proc$issuer_ls180.v:103872$4087 + assign { } { } + assign { } { } + assign $0\dec62_sgl_pipe[0:0] $1\dec62_sgl_pipe[0:0] + attribute \src "issuer_ls180.v:103873.5-103873.29" + switch \initial + attribute \src "issuer_ls180.v:103873.9-103873.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec62_sgl_pipe[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec62_sgl_pipe[0:0] 1'1 + case + assign $1\dec62_sgl_pipe[0:0] 1'0 + end + sync always + update \dec62_sgl_pipe $0\dec62_sgl_pipe[0:0] + end + attribute \src "issuer_ls180.v:103885.3-103897.6" + process $proc$issuer_ls180.v:103885$4088 + assign { } { } + assign { } { } + assign $0\dec62_form[4:0] $1\dec62_form[4:0] + attribute \src "issuer_ls180.v:103886.5-103886.29" + switch \initial + attribute \src "issuer_ls180.v:103886.9-103886.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec62_form[4:0] 5'00101 + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec62_form[4:0] 5'00101 + case + assign $1\dec62_form[4:0] 5'00000 + end + sync always + update \dec62_form $0\dec62_form[4:0] + end + attribute \src "issuer_ls180.v:103898.3-103910.6" + process $proc$issuer_ls180.v:103898$4089 + assign { } { } + assign { } { } + assign $0\dec62_in1_sel[2:0] $1\dec62_in1_sel[2:0] + attribute \src "issuer_ls180.v:103899.5-103899.29" + switch \initial + attribute \src "issuer_ls180.v:103899.9-103899.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec62_in1_sel[2:0] 3'010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec62_in1_sel[2:0] 3'010 + case + assign $1\dec62_in1_sel[2:0] 3'000 + end + sync always + update \dec62_in1_sel $0\dec62_in1_sel[2:0] + end + attribute \src "issuer_ls180.v:103911.3-103923.6" + process $proc$issuer_ls180.v:103911$4090 + assign { } { } + assign { } { } + assign $0\dec62_in2_sel[3:0] $1\dec62_in2_sel[3:0] + attribute \src "issuer_ls180.v:103912.5-103912.29" + switch \initial + attribute \src "issuer_ls180.v:103912.9-103912.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec62_in2_sel[3:0] 4'1000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec62_in2_sel[3:0] 4'1000 + case + assign $1\dec62_in2_sel[3:0] 4'0000 + end + sync always + update \dec62_in2_sel $0\dec62_in2_sel[3:0] + end + attribute \src "issuer_ls180.v:103924.3-103936.6" + process $proc$issuer_ls180.v:103924$4091 + assign { } { } + assign { } { } + assign $0\dec62_in3_sel[1:0] $1\dec62_in3_sel[1:0] + attribute \src "issuer_ls180.v:103925.5-103925.29" + switch \initial + attribute \src "issuer_ls180.v:103925.9-103925.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec62_in3_sel[1:0] 2'01 + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec62_in3_sel[1:0] 2'01 + case + assign $1\dec62_in3_sel[1:0] 2'00 + end + sync always + update \dec62_in3_sel $0\dec62_in3_sel[1:0] + end + attribute \src "issuer_ls180.v:103937.3-103949.6" + process $proc$issuer_ls180.v:103937$4092 + assign { } { } + assign { } { } + assign $0\dec62_out_sel[1:0] $1\dec62_out_sel[1:0] + attribute \src "issuer_ls180.v:103938.5-103938.29" + switch \initial + attribute \src "issuer_ls180.v:103938.9-103938.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec62_out_sel[1:0] 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec62_out_sel[1:0] 2'00 + case + assign $1\dec62_out_sel[1:0] 2'00 + end + sync always + update \dec62_out_sel $0\dec62_out_sel[1:0] + end + attribute \src "issuer_ls180.v:103950.3-103962.6" + process $proc$issuer_ls180.v:103950$4093 + assign { } { } + assign { } { } + assign $0\dec62_cr_in[2:0] $1\dec62_cr_in[2:0] + attribute \src "issuer_ls180.v:103951.5-103951.29" + switch \initial + attribute \src "issuer_ls180.v:103951.9-103951.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec62_cr_in[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec62_cr_in[2:0] 3'000 + case + assign $1\dec62_cr_in[2:0] 3'000 + end + sync always + update \dec62_cr_in $0\dec62_cr_in[2:0] + end + attribute \src "issuer_ls180.v:103963.3-103975.6" + process $proc$issuer_ls180.v:103963$4094 + assign { } { } + assign { } { } + assign $0\dec62_cr_out[2:0] $1\dec62_cr_out[2:0] + attribute \src "issuer_ls180.v:103964.5-103964.29" + switch \initial + attribute \src "issuer_ls180.v:103964.9-103964.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:420" + switch \opcode_switch + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec62_cr_out[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec62_cr_out[2:0] 3'000 + case + assign $1\dec62_cr_out[2:0] 3'000 + end + sync always + update \dec62_cr_out $0\dec62_cr_out[2:0] + end + connect \opcode_switch \opcode_in [1:0] +end +attribute \src "issuer_ls180.v:103981.1-104514.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.dec_ALU" +attribute \generator "nMigen" +module \dec_ALU + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 output 18 \ALU_ALU__data_len + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 output 3 \ALU_ALU__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 output 4 \ALU_ALU__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 5 \ALU_ALU__imm_data__ok + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 output 14 \ALU_ALU__input_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 output 19 \ALU_ALU__insn + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 output 2 \ALU_ALU__insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 10 \ALU_ALU__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 12 \ALU_ALU__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 16 \ALU_ALU__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 17 \ALU_ALU__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 8 \ALU_ALU__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 9 \ALU_ALU__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 15 \ALU_ALU__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 7 \ALU_ALU__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 6 \ALU_ALU__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 13 \ALU_ALU__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 11 \ALU_ALU__zero_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + wire input 1 \bigendian + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 \dec_ALU_BA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 \dec_ALU_BB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 \dec_ALU_BC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 14 \dec_ALU_BD + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 \dec_ALU_BI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 \dec_ALU_BT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 14 \dec_ALU_DS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 8 \dec_ALU_FXM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 24 \dec_ALU_LI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire \dec_ALU_OE + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 \dec_ALU_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire \dec_ALU_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 \dec_ALU_SH32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 16 \dec_ALU_SI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 16 \dec_ALU_UI + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 \dec_ALU_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 \dec_ALU_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \dec_ALU_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec_ALU_cry_out + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 12 \dec_ALU_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 \dec_ALU_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 \dec_ALU_in2_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 7 \dec_ALU_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec_ALU_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec_ALU_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec_ALU_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 \dec_ALU_ldst_len + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \dec_ALU_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec_ALU_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 6 \dec_ALU_sh + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \dec_XL_BT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 3 \dec_X_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 3 \dec_X_BFA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:149" + wire \dec_ai_immz_out + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:148" + wire width 3 \dec_ai_sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 \dec_bi_imm_b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \dec_bi_imm_b_ok + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:216" + wire width 4 \dec_bi_sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:485" + wire width 32 \dec_cr_in_insn_in + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:484" + wire width 3 \dec_cr_in_sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \dec_cr_out_cr_bitfield_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:550" + wire width 32 \dec_cr_out_insn_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:548" + wire \dec_cr_out_rc_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:549" + wire width 3 \dec_cr_out_sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \dec_oe_oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \dec_oe_oe_ok + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:441" + wire width 2 \dec_oe_sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + wire width 32 \dec_opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \dec_rc_rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \dec_rc_rc_ok + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:404" + wire width 2 \dec_rc_sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:405" + wire width 32 \insn_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:442" + wire width 32 \insn_in$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:442" + wire width 32 input 20 \raw_opcode_in + attribute \module_not_derived 1 + attribute \src "issuer_ls180.v:104398.7-104435.4" + cell \dec \dec + connect \ALU_BA \dec_ALU_BA + connect \ALU_BB \dec_ALU_BB + connect \ALU_BC \dec_ALU_BC + connect \ALU_BD \dec_ALU_BD + connect \ALU_BI \dec_ALU_BI + connect \ALU_BT \dec_ALU_BT + connect \ALU_DS \dec_ALU_DS + connect \ALU_FXM \dec_ALU_FXM + connect \ALU_LI \dec_ALU_LI + connect \ALU_OE \dec_ALU_OE + connect \ALU_RA \dec_ALU_RA + connect \ALU_Rc \dec_ALU_Rc + connect \ALU_SH32 \dec_ALU_SH32 + connect \ALU_SI \dec_ALU_SI + connect \ALU_UI \dec_ALU_UI + connect \ALU_cr_in \dec_ALU_cr_in + connect \ALU_cr_out \dec_ALU_cr_out + connect \ALU_cry_in \dec_ALU_cry_in + connect \ALU_cry_out \dec_ALU_cry_out + connect \ALU_function_unit \dec_ALU_function_unit + connect \ALU_in1_sel \dec_ALU_in1_sel + connect \ALU_in2_sel \dec_ALU_in2_sel + connect \ALU_internal_op \dec_ALU_internal_op + connect \ALU_inv_a \dec_ALU_inv_a + connect \ALU_inv_out \dec_ALU_inv_out + connect \ALU_is_32b \dec_ALU_is_32b + connect \ALU_ldst_len \dec_ALU_ldst_len + connect \ALU_rc_sel \dec_ALU_rc_sel + connect \ALU_sgn \dec_ALU_sgn + connect \ALU_sh \dec_ALU_sh + connect \XL_BT \dec_XL_BT + connect \X_BF \dec_X_BF + connect \X_BFA \dec_X_BFA + connect \bigendian \bigendian + connect \opcode_in \dec_opcode_in + connect \raw_opcode_in \raw_opcode_in + end + attribute \module_not_derived 1 + attribute \src "issuer_ls180.v:104436.10-104440.4" + cell \dec_ai \dec_ai + connect \ALU_RA \dec_ALU_RA + connect \immz_out \dec_ai_immz_out + connect \sel_in \dec_ai_sel_in + end + attribute \module_not_derived 1 + attribute \src "issuer_ls180.v:104441.10-104452.4" + cell \dec_bi \dec_bi + connect \ALU_BD \dec_ALU_BD + connect \ALU_DS \dec_ALU_DS + connect \ALU_LI \dec_ALU_LI + connect \ALU_SH32 \dec_ALU_SH32 + connect \ALU_SI \dec_ALU_SI + connect \ALU_UI \dec_ALU_UI + connect \ALU_sh \dec_ALU_sh + connect \imm_b \dec_bi_imm_b + connect \imm_b_ok \dec_bi_imm_b_ok + connect \sel_in \dec_bi_sel_in + end + attribute \module_not_derived 1 + attribute \src "issuer_ls180.v:104453.13-104464.4" + cell \dec_cr_in \dec_cr_in + connect \ALU_BA \dec_ALU_BA + connect \ALU_BB \dec_ALU_BB + connect \ALU_BC \dec_ALU_BC + connect \ALU_BI \dec_ALU_BI + connect \ALU_BT \dec_ALU_BT + connect \ALU_FXM \dec_ALU_FXM + connect \ALU_internal_op \dec_ALU_internal_op + connect \X_BFA \dec_X_BFA + connect \insn_in \dec_cr_in_insn_in + connect \sel_in \dec_cr_in_sel_in + end + attribute \module_not_derived 1 + attribute \src "issuer_ls180.v:104465.14-104474.4" + cell \dec_cr_out \dec_cr_out + connect \ALU_FXM \dec_ALU_FXM + connect \ALU_internal_op \dec_ALU_internal_op + connect \XL_BT \dec_XL_BT + connect \X_BF \dec_X_BF + connect \cr_bitfield_ok \dec_cr_out_cr_bitfield_ok + connect \insn_in \dec_cr_out_insn_in + connect \rc_in \dec_cr_out_rc_in + connect \sel_in \dec_cr_out_sel_in + end + attribute \module_not_derived 1 + attribute \src "issuer_ls180.v:104475.10-104481.4" + cell \dec_oe \dec_oe + connect \ALU_OE \dec_ALU_OE + connect \ALU_internal_op \dec_ALU_internal_op + connect \oe \dec_oe_oe + connect \oe_ok \dec_oe_oe_ok + connect \sel_in \dec_oe_sel_in + end + attribute \module_not_derived 1 + attribute \src "issuer_ls180.v:104482.10-104487.4" + cell \dec_rc \dec_rc + connect \ALU_Rc \dec_ALU_Rc + connect \rc \dec_rc_rc + connect \rc_ok \dec_rc_rc_ok + connect \sel_in \dec_rc_sel_in + end + connect \ALU_ALU__is_signed \dec_ALU_sgn + connect \ALU_ALU__is_32bit \dec_ALU_is_32b + connect \ALU_ALU__output_carry \dec_ALU_cry_out + connect \ALU_ALU__input_carry \dec_ALU_cry_in + connect \ALU_ALU__invert_out \dec_ALU_inv_out + connect \ALU_ALU__invert_in \dec_ALU_inv_a + connect \ALU_ALU__data_len \dec_ALU_ldst_len + connect \ALU_ALU__write_cr0 \dec_cr_out_cr_bitfield_ok + connect { \ALU_ALU__oe__ok \ALU_ALU__oe__oe } { \dec_oe_oe_ok \dec_oe_oe } + connect { \ALU_ALU__rc__ok \ALU_ALU__rc__rc } { \dec_rc_rc_ok \dec_rc_rc } + connect { \ALU_ALU__imm_data__ok \ALU_ALU__imm_data__data } { \dec_bi_imm_b_ok \dec_bi_imm_b } + connect \dec_bi_sel_in \dec_ALU_in2_sel + connect \ALU_ALU__zero_a \dec_ai_immz_out + connect \dec_ai_sel_in \dec_ALU_in1_sel + connect \ALU_ALU__fn_unit \dec_ALU_function_unit + connect \ALU_ALU__insn_type \dec_ALU_internal_op + connect \dec_cr_out_rc_in \dec_rc_rc + connect \dec_cr_out_sel_in \dec_ALU_cr_out + connect \dec_cr_in_sel_in \dec_ALU_cr_in + connect \dec_oe_sel_in \dec_ALU_rc_sel + connect \dec_rc_sel_in \dec_ALU_rc_sel + connect \dec_cr_out_insn_in \dec_opcode_in + connect \dec_cr_in_insn_in \dec_opcode_in + connect \insn_in$1 \dec_opcode_in + connect \insn_in \dec_opcode_in + connect \ALU_ALU__insn \dec_opcode_in +end +attribute \src "issuer_ls180.v:104518.1-104970.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.dec_BRANCH" +attribute \generator "nMigen" +module \dec_BRANCH + attribute \src "issuer_ls180.v:104944.3-104953.6" + wire $0\BRANCH_BRANCH__lk[0:0] + attribute \src "issuer_ls180.v:104519.7-104519.20" + wire $0\initial[0:0] + attribute \src "issuer_ls180.v:104944.3-104953.6" + wire $1\BRANCH_BRANCH__lk[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 output 3 \BRANCH_BRANCH__cia + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 output 5 \BRANCH_BRANCH__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 output 7 \BRANCH_BRANCH__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 8 \BRANCH_BRANCH__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 output 6 \BRANCH_BRANCH__insn + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 output 4 \BRANCH_BRANCH__insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 10 \BRANCH_BRANCH__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 9 \BRANCH_BRANCH__lk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + wire input 2 \bigendian + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:8" + wire width 64 input 11 \core_pc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 \dec_BRANCH_BA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 \dec_BRANCH_BB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 \dec_BRANCH_BC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 14 \dec_BRANCH_BD + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 \dec_BRANCH_BI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 \dec_BRANCH_BT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 14 \dec_BRANCH_DS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 8 \dec_BRANCH_FXM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 24 \dec_BRANCH_LI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire \dec_BRANCH_LK + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire \dec_BRANCH_OE + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire \dec_BRANCH_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 \dec_BRANCH_SH32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 16 \dec_BRANCH_SI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 16 \dec_BRANCH_UI + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 \dec_BRANCH_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 \dec_BRANCH_cr_out + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 12 \dec_BRANCH_function_unit + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 \dec_BRANCH_in2_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 7 \dec_BRANCH_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec_BRANCH_is_32b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec_BRANCH_lk + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \dec_BRANCH_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 6 \dec_BRANCH_sh + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \dec_XL_BT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 3 \dec_X_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 3 \dec_X_BFA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 \dec_bi_imm_b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \dec_bi_imm_b_ok + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:216" + wire width 4 \dec_bi_sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:485" + wire width 32 \dec_cr_in_insn_in + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:484" + wire width 3 \dec_cr_in_sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:550" + wire width 32 \dec_cr_out_insn_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:548" + wire \dec_cr_out_rc_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:549" + wire width 3 \dec_cr_out_sel_in + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:441" + wire width 2 \dec_oe_sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + wire width 32 \dec_opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \dec_rc_rc + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:404" + wire width 2 \dec_rc_sel_in + attribute \src "issuer_ls180.v:104519.7-104519.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:405" + wire width 32 \insn_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:442" + wire width 32 \insn_in$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:442" + wire width 32 input 1 \raw_opcode_in + attribute \module_not_derived 1 + attribute \src "issuer_ls180.v:104869.13-104900.4" + cell \dec$144 \dec + connect \BRANCH_BA \dec_BRANCH_BA + connect \BRANCH_BB \dec_BRANCH_BB + connect \BRANCH_BC \dec_BRANCH_BC + connect \BRANCH_BD \dec_BRANCH_BD + connect \BRANCH_BI \dec_BRANCH_BI + connect \BRANCH_BT \dec_BRANCH_BT + connect \BRANCH_DS \dec_BRANCH_DS + connect \BRANCH_FXM \dec_BRANCH_FXM + connect \BRANCH_LI \dec_BRANCH_LI + connect \BRANCH_LK \dec_BRANCH_LK + connect \BRANCH_OE \dec_BRANCH_OE + connect \BRANCH_Rc \dec_BRANCH_Rc + connect \BRANCH_SH32 \dec_BRANCH_SH32 + connect \BRANCH_SI \dec_BRANCH_SI + connect \BRANCH_UI \dec_BRANCH_UI + connect \BRANCH_cr_in \dec_BRANCH_cr_in + connect \BRANCH_cr_out \dec_BRANCH_cr_out + connect \BRANCH_function_unit \dec_BRANCH_function_unit + connect \BRANCH_in2_sel \dec_BRANCH_in2_sel + connect \BRANCH_internal_op \dec_BRANCH_internal_op + connect \BRANCH_is_32b \dec_BRANCH_is_32b + connect \BRANCH_lk \dec_BRANCH_lk + connect \BRANCH_rc_sel \dec_BRANCH_rc_sel + connect \BRANCH_sh \dec_BRANCH_sh + connect \XL_BT \dec_XL_BT + connect \X_BF \dec_X_BF + connect \X_BFA \dec_X_BFA + connect \bigendian \bigendian + connect \opcode_in \dec_opcode_in + connect \raw_opcode_in \raw_opcode_in + end + attribute \module_not_derived 1 + attribute \src "issuer_ls180.v:104901.16-104912.4" + cell \dec_bi$151 \dec_bi + connect \BRANCH_BD \dec_BRANCH_BD + connect \BRANCH_DS \dec_BRANCH_DS + connect \BRANCH_LI \dec_BRANCH_LI + connect \BRANCH_SH32 \dec_BRANCH_SH32 + connect \BRANCH_SI \dec_BRANCH_SI + connect \BRANCH_UI \dec_BRANCH_UI + connect \BRANCH_sh \dec_BRANCH_sh + connect \imm_b \dec_bi_imm_b + connect \imm_b_ok \dec_bi_imm_b_ok + connect \sel_in \dec_bi_sel_in + end + attribute \module_not_derived 1 + attribute \src "issuer_ls180.v:104913.19-104924.4" + cell \dec_cr_in$147 \dec_cr_in + connect \BRANCH_BA \dec_BRANCH_BA + connect \BRANCH_BB \dec_BRANCH_BB + connect \BRANCH_BC \dec_BRANCH_BC + connect \BRANCH_BI \dec_BRANCH_BI + connect \BRANCH_BT \dec_BRANCH_BT + connect \BRANCH_FXM \dec_BRANCH_FXM + connect \BRANCH_internal_op \dec_BRANCH_internal_op + connect \X_BFA \dec_X_BFA + connect \insn_in \dec_cr_in_insn_in + connect \sel_in \dec_cr_in_sel_in + end + attribute \module_not_derived 1 + attribute \src "issuer_ls180.v:104925.20-104933.4" + cell \dec_cr_out$149 \dec_cr_out + connect \BRANCH_FXM \dec_BRANCH_FXM + connect \BRANCH_internal_op \dec_BRANCH_internal_op + connect \XL_BT \dec_XL_BT + connect \X_BF \dec_X_BF + connect \insn_in \dec_cr_out_insn_in + connect \rc_in \dec_cr_out_rc_in + connect \sel_in \dec_cr_out_sel_in + end + attribute \module_not_derived 1 + attribute \src "issuer_ls180.v:104934.16-104938.4" + cell \dec_oe$146 \dec_oe + connect \BRANCH_OE \dec_BRANCH_OE + connect \BRANCH_internal_op \dec_BRANCH_internal_op + connect \sel_in \dec_oe_sel_in + end + attribute \module_not_derived 1 + attribute \src "issuer_ls180.v:104939.16-104943.4" + cell \dec_rc$145 \dec_rc + connect \BRANCH_Rc \dec_BRANCH_Rc + connect \rc \dec_rc_rc + connect \sel_in \dec_rc_sel_in + end + attribute \src "issuer_ls180.v:104519.7-104519.20" + process $proc$issuer_ls180.v:104519$4097 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "issuer_ls180.v:104944.3-104953.6" + process $proc$issuer_ls180.v:104944$4096 + assign { } { } + assign { } { } + assign $0\BRANCH_BRANCH__lk[0:0] $1\BRANCH_BRANCH__lk[0:0] + attribute \src "issuer_ls180.v:104945.5-104945.29" + switch \initial + attribute \src "issuer_ls180.v:104945.9-104945.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:756" + switch \dec_BRANCH_lk + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\BRANCH_BRANCH__lk[0:0] \dec_BRANCH_LK + case + assign $1\BRANCH_BRANCH__lk[0:0] 1'0 + end + sync always + update \BRANCH_BRANCH__lk $0\BRANCH_BRANCH__lk[0:0] + end + connect \BRANCH_BRANCH__is_32bit \dec_BRANCH_is_32b + connect { \BRANCH_BRANCH__imm_data__ok \BRANCH_BRANCH__imm_data__data } { \dec_bi_imm_b_ok \dec_bi_imm_b } + connect \dec_bi_sel_in \dec_BRANCH_in2_sel + connect \BRANCH_BRANCH__fn_unit \dec_BRANCH_function_unit + connect \BRANCH_BRANCH__insn_type \dec_BRANCH_internal_op + connect \BRANCH_BRANCH__cia \core_pc + connect \dec_cr_out_rc_in \dec_rc_rc + connect \dec_cr_out_sel_in \dec_BRANCH_cr_out + connect \dec_cr_in_sel_in \dec_BRANCH_cr_in + connect \dec_oe_sel_in \dec_BRANCH_rc_sel + connect \dec_rc_sel_in \dec_BRANCH_rc_sel + connect \dec_cr_out_insn_in \dec_opcode_in + connect \dec_cr_in_insn_in \dec_opcode_in + connect \insn_in$1 \dec_opcode_in + connect \insn_in \dec_opcode_in + connect \BRANCH_BRANCH__insn \dec_opcode_in +end +attribute \src "issuer_ls180.v:104974.1-105317.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.dec_CR" +attribute \generator "nMigen" +module \dec_CR + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 output 3 \CR_CR__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 output 4 \CR_CR__insn + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 output 2 \CR_CR__insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + wire input 1 \bigendian + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 \dec_CR_BA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 \dec_CR_BB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 \dec_CR_BC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 \dec_CR_BI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 \dec_CR_BT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 8 \dec_CR_FXM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire \dec_CR_OE + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire \dec_CR_Rc + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 \dec_CR_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 \dec_CR_cr_out + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 12 \dec_CR_function_unit + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 7 \dec_CR_internal_op + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \dec_CR_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \dec_XL_BT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 3 \dec_X_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 3 \dec_X_BFA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:485" + wire width 32 \dec_cr_in_insn_in + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:484" + wire width 3 \dec_cr_in_sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:550" + wire width 32 \dec_cr_out_insn_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:548" + wire \dec_cr_out_rc_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:549" + wire width 3 \dec_cr_out_sel_in + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:441" + wire width 2 \dec_oe_sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + wire width 32 \dec_opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \dec_rc_rc + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:404" + wire width 2 \dec_rc_sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:405" + wire width 32 \insn_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:442" + wire width 32 \insn_in$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:442" + wire width 32 input 5 \raw_opcode_in + attribute \module_not_derived 1 + attribute \src "issuer_ls180.v:105253.13-105273.4" + cell \dec$137 \dec + connect \CR_BA \dec_CR_BA + connect \CR_BB \dec_CR_BB + connect \CR_BC \dec_CR_BC + connect \CR_BI \dec_CR_BI + connect \CR_BT \dec_CR_BT + connect \CR_FXM \dec_CR_FXM + connect \CR_OE \dec_CR_OE + connect \CR_Rc \dec_CR_Rc + connect \CR_cr_in \dec_CR_cr_in + connect \CR_cr_out \dec_CR_cr_out + connect \CR_function_unit \dec_CR_function_unit + connect \CR_internal_op \dec_CR_internal_op + connect \CR_rc_sel \dec_CR_rc_sel + connect \XL_BT \dec_XL_BT + connect \X_BF \dec_X_BF + connect \X_BFA \dec_X_BFA + connect \bigendian \bigendian + connect \opcode_in \dec_opcode_in + connect \raw_opcode_in \raw_opcode_in + end + attribute \module_not_derived 1 + attribute \src "issuer_ls180.v:105274.19-105285.4" + cell \dec_cr_in$140 \dec_cr_in + connect \CR_BA \dec_CR_BA + connect \CR_BB \dec_CR_BB + connect \CR_BC \dec_CR_BC + connect \CR_BI \dec_CR_BI + connect \CR_BT \dec_CR_BT + connect \CR_FXM \dec_CR_FXM + connect \CR_internal_op \dec_CR_internal_op + connect \X_BFA \dec_X_BFA + connect \insn_in \dec_cr_in_insn_in + connect \sel_in \dec_cr_in_sel_in + end + attribute \module_not_derived 1 + attribute \src "issuer_ls180.v:105286.20-105294.4" + cell \dec_cr_out$142 \dec_cr_out + connect \CR_FXM \dec_CR_FXM + connect \CR_internal_op \dec_CR_internal_op + connect \XL_BT \dec_XL_BT + connect \X_BF \dec_X_BF + connect \insn_in \dec_cr_out_insn_in + connect \rc_in \dec_cr_out_rc_in + connect \sel_in \dec_cr_out_sel_in + end + attribute \module_not_derived 1 + attribute \src "issuer_ls180.v:105295.16-105299.4" + cell \dec_oe$139 \dec_oe + connect \CR_OE \dec_CR_OE + connect \CR_internal_op \dec_CR_internal_op + connect \sel_in \dec_oe_sel_in + end + attribute \module_not_derived 1 + attribute \src "issuer_ls180.v:105300.16-105304.4" + cell \dec_rc$138 \dec_rc + connect \CR_Rc \dec_CR_Rc + connect \rc \dec_rc_rc + connect \sel_in \dec_rc_sel_in + end + connect \CR_CR__fn_unit \dec_CR_function_unit + connect \CR_CR__insn_type \dec_CR_internal_op + connect \dec_cr_out_rc_in \dec_rc_rc + connect \dec_cr_out_sel_in \dec_CR_cr_out + connect \dec_cr_in_sel_in \dec_CR_cr_in + connect \dec_oe_sel_in \dec_CR_rc_sel + connect \dec_rc_sel_in \dec_CR_rc_sel + connect \dec_cr_out_insn_in \dec_opcode_in + connect \dec_cr_in_insn_in \dec_opcode_in + connect \insn_in$1 \dec_opcode_in + connect \insn_in \dec_opcode_in + connect \CR_CR__insn \dec_opcode_in +end +attribute \src "issuer_ls180.v:105321.1-105854.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.dec_DIV" +attribute \generator "nMigen" +module \dec_DIV + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 output 18 \DIV_DIV__data_len + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 output 3 \DIV_DIV__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 output 4 \DIV_DIV__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 5 \DIV_DIV__imm_data__ok + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 output 12 \DIV_DIV__input_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 output 19 \DIV_DIV__insn + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 output 2 \DIV_DIV__insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 10 \DIV_DIV__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 13 \DIV_DIV__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 16 \DIV_DIV__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 17 \DIV_DIV__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 8 \DIV_DIV__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 9 \DIV_DIV__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 15 \DIV_DIV__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 7 \DIV_DIV__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 6 \DIV_DIV__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 14 \DIV_DIV__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 11 \DIV_DIV__zero_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + wire input 1 \bigendian + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 \dec_DIV_BA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 \dec_DIV_BB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 \dec_DIV_BC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 14 \dec_DIV_BD + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 \dec_DIV_BI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 \dec_DIV_BT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 14 \dec_DIV_DS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 8 \dec_DIV_FXM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 24 \dec_DIV_LI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire \dec_DIV_OE + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 \dec_DIV_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire \dec_DIV_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 \dec_DIV_SH32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 16 \dec_DIV_SI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 16 \dec_DIV_UI + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 \dec_DIV_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 \dec_DIV_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \dec_DIV_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec_DIV_cry_out + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 12 \dec_DIV_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 \dec_DIV_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 \dec_DIV_in2_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 7 \dec_DIV_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec_DIV_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec_DIV_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec_DIV_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 \dec_DIV_ldst_len + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \dec_DIV_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec_DIV_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 6 \dec_DIV_sh + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \dec_XL_BT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 3 \dec_X_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 3 \dec_X_BFA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:149" + wire \dec_ai_immz_out + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:148" + wire width 3 \dec_ai_sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 \dec_bi_imm_b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \dec_bi_imm_b_ok + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:216" + wire width 4 \dec_bi_sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:485" + wire width 32 \dec_cr_in_insn_in + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:484" + wire width 3 \dec_cr_in_sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \dec_cr_out_cr_bitfield_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:550" + wire width 32 \dec_cr_out_insn_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:548" + wire \dec_cr_out_rc_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:549" + wire width 3 \dec_cr_out_sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \dec_oe_oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \dec_oe_oe_ok + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:441" + wire width 2 \dec_oe_sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + wire width 32 \dec_opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \dec_rc_rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \dec_rc_rc_ok + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:404" + wire width 2 \dec_rc_sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:405" + wire width 32 \insn_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:442" + wire width 32 \insn_in$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:442" + wire width 32 input 20 \raw_opcode_in + attribute \module_not_derived 1 + attribute \src "issuer_ls180.v:105738.13-105775.4" + cell \dec$168 \dec + connect \DIV_BA \dec_DIV_BA + connect \DIV_BB \dec_DIV_BB + connect \DIV_BC \dec_DIV_BC + connect \DIV_BD \dec_DIV_BD + connect \DIV_BI \dec_DIV_BI + connect \DIV_BT \dec_DIV_BT + connect \DIV_DS \dec_DIV_DS + connect \DIV_FXM \dec_DIV_FXM + connect \DIV_LI \dec_DIV_LI + connect \DIV_OE \dec_DIV_OE + connect \DIV_RA \dec_DIV_RA + connect \DIV_Rc \dec_DIV_Rc + connect \DIV_SH32 \dec_DIV_SH32 + connect \DIV_SI \dec_DIV_SI + connect \DIV_UI \dec_DIV_UI + connect \DIV_cr_in \dec_DIV_cr_in + connect \DIV_cr_out \dec_DIV_cr_out + connect \DIV_cry_in \dec_DIV_cry_in + connect \DIV_cry_out \dec_DIV_cry_out + connect \DIV_function_unit \dec_DIV_function_unit + connect \DIV_in1_sel \dec_DIV_in1_sel + connect \DIV_in2_sel \dec_DIV_in2_sel + connect \DIV_internal_op \dec_DIV_internal_op + connect \DIV_inv_a \dec_DIV_inv_a + connect \DIV_inv_out \dec_DIV_inv_out + connect \DIV_is_32b \dec_DIV_is_32b + connect \DIV_ldst_len \dec_DIV_ldst_len + connect \DIV_rc_sel \dec_DIV_rc_sel + connect \DIV_sgn \dec_DIV_sgn + connect \DIV_sh \dec_DIV_sh + connect \XL_BT \dec_XL_BT + connect \X_BF \dec_X_BF + connect \X_BFA \dec_X_BFA + connect \bigendian \bigendian + connect \opcode_in \dec_opcode_in + connect \raw_opcode_in \raw_opcode_in + end + attribute \module_not_derived 1 + attribute \src "issuer_ls180.v:105776.16-105780.4" + cell \dec_ai$175 \dec_ai + connect \DIV_RA \dec_DIV_RA + connect \immz_out \dec_ai_immz_out + connect \sel_in \dec_ai_sel_in + end + attribute \module_not_derived 1 + attribute \src "issuer_ls180.v:105781.16-105792.4" + cell \dec_bi$176 \dec_bi + connect \DIV_BD \dec_DIV_BD + connect \DIV_DS \dec_DIV_DS + connect \DIV_LI \dec_DIV_LI + connect \DIV_SH32 \dec_DIV_SH32 + connect \DIV_SI \dec_DIV_SI + connect \DIV_UI \dec_DIV_UI + connect \DIV_sh \dec_DIV_sh + connect \imm_b \dec_bi_imm_b + connect \imm_b_ok \dec_bi_imm_b_ok + connect \sel_in \dec_bi_sel_in + end + attribute \module_not_derived 1 + attribute \src "issuer_ls180.v:105793.19-105804.4" + cell \dec_cr_in$171 \dec_cr_in + connect \DIV_BA \dec_DIV_BA + connect \DIV_BB \dec_DIV_BB + connect \DIV_BC \dec_DIV_BC + connect \DIV_BI \dec_DIV_BI + connect \DIV_BT \dec_DIV_BT + connect \DIV_FXM \dec_DIV_FXM + connect \DIV_internal_op \dec_DIV_internal_op + connect \X_BFA \dec_X_BFA + connect \insn_in \dec_cr_in_insn_in + connect \sel_in \dec_cr_in_sel_in + end + attribute \module_not_derived 1 + attribute \src "issuer_ls180.v:105805.20-105814.4" + cell \dec_cr_out$173 \dec_cr_out + connect \DIV_FXM \dec_DIV_FXM + connect \DIV_internal_op \dec_DIV_internal_op + connect \XL_BT \dec_XL_BT + connect \X_BF \dec_X_BF + connect \cr_bitfield_ok \dec_cr_out_cr_bitfield_ok + connect \insn_in \dec_cr_out_insn_in + connect \rc_in \dec_cr_out_rc_in + connect \sel_in \dec_cr_out_sel_in + end + attribute \module_not_derived 1 + attribute \src "issuer_ls180.v:105815.16-105821.4" + cell \dec_oe$170 \dec_oe + connect \DIV_OE \dec_DIV_OE + connect \DIV_internal_op \dec_DIV_internal_op + connect \oe \dec_oe_oe + connect \oe_ok \dec_oe_oe_ok + connect \sel_in \dec_oe_sel_in + end + attribute \module_not_derived 1 + attribute \src "issuer_ls180.v:105822.16-105827.4" + cell \dec_rc$169 \dec_rc + connect \DIV_Rc \dec_DIV_Rc + connect \rc \dec_rc_rc + connect \rc_ok \dec_rc_rc_ok + connect \sel_in \dec_rc_sel_in + end + connect \DIV_DIV__is_signed \dec_DIV_sgn + connect \DIV_DIV__is_32bit \dec_DIV_is_32b + connect \DIV_DIV__output_carry \dec_DIV_cry_out + connect \DIV_DIV__input_carry \dec_DIV_cry_in + connect \DIV_DIV__invert_out \dec_DIV_inv_out + connect \DIV_DIV__invert_in \dec_DIV_inv_a + connect \DIV_DIV__data_len \dec_DIV_ldst_len + connect \DIV_DIV__write_cr0 \dec_cr_out_cr_bitfield_ok + connect { \DIV_DIV__oe__ok \DIV_DIV__oe__oe } { \dec_oe_oe_ok \dec_oe_oe } + connect { \DIV_DIV__rc__ok \DIV_DIV__rc__rc } { \dec_rc_rc_ok \dec_rc_rc } + connect { \DIV_DIV__imm_data__ok \DIV_DIV__imm_data__data } { \dec_bi_imm_b_ok \dec_bi_imm_b } + connect \dec_bi_sel_in \dec_DIV_in2_sel + connect \DIV_DIV__zero_a \dec_ai_immz_out + connect \dec_ai_sel_in \dec_DIV_in1_sel + connect \DIV_DIV__fn_unit \dec_DIV_function_unit + connect \DIV_DIV__insn_type \dec_DIV_internal_op + connect \dec_cr_out_rc_in \dec_rc_rc + connect \dec_cr_out_sel_in \dec_DIV_cr_out + connect \dec_cr_in_sel_in \dec_DIV_cr_in + connect \dec_oe_sel_in \dec_DIV_rc_sel + connect \dec_rc_sel_in \dec_DIV_rc_sel + connect \dec_cr_out_insn_in \dec_opcode_in + connect \dec_cr_in_insn_in \dec_opcode_in + connect \insn_in$1 \dec_opcode_in + connect \insn_in \dec_opcode_in + connect \DIV_DIV__insn \dec_opcode_in +end +attribute \src "issuer_ls180.v:105858.1-106381.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.dec_LDST" +attribute \generator "nMigen" +module \dec_LDST + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 14 \LDST_LDST__byte_reverse + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 output 13 \LDST_LDST__data_len + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 output 3 \LDST_LDST__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 output 4 \LDST_LDST__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 5 \LDST_LDST__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 output 17 \LDST_LDST__insn + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 output 2 \LDST_LDST__insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 11 \LDST_LDST__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 12 \LDST_LDST__is_signed + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 output 16 \LDST_LDST__ldst_mode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 9 \LDST_LDST__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 10 \LDST_LDST__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 8 \LDST_LDST__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 7 \LDST_LDST__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 15 \LDST_LDST__sign_extend + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 6 \LDST_LDST__zero_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + wire input 1 \bigendian + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 \dec_LDST_BA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 \dec_LDST_BB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 \dec_LDST_BC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 14 \dec_LDST_BD + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 \dec_LDST_BI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 \dec_LDST_BT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 14 \dec_LDST_DS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 8 \dec_LDST_FXM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 24 \dec_LDST_LI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire \dec_LDST_OE + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 \dec_LDST_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire \dec_LDST_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 \dec_LDST_SH32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 16 \dec_LDST_SI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 16 \dec_LDST_UI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec_LDST_br + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 \dec_LDST_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 \dec_LDST_cr_out + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 12 \dec_LDST_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 \dec_LDST_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 \dec_LDST_in2_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 7 \dec_LDST_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec_LDST_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 \dec_LDST_ldst_len + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \dec_LDST_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec_LDST_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec_LDST_sgn_ext + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 6 \dec_LDST_sh + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \dec_LDST_upd + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \dec_XL_BT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 3 \dec_X_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 3 \dec_X_BFA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:149" + wire \dec_ai_immz_out + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:148" + wire width 3 \dec_ai_sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 \dec_bi_imm_b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \dec_bi_imm_b_ok + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:216" + wire width 4 \dec_bi_sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:485" + wire width 32 \dec_cr_in_insn_in + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:484" + wire width 3 \dec_cr_in_sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:550" + wire width 32 \dec_cr_out_insn_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:548" + wire \dec_cr_out_rc_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:549" + wire width 3 \dec_cr_out_sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \dec_oe_oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \dec_oe_oe_ok + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:441" + wire width 2 \dec_oe_sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + wire width 32 \dec_opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \dec_rc_rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \dec_rc_rc_ok + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:404" + wire width 2 \dec_rc_sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:405" + wire width 32 \insn_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:442" + wire width 32 \insn_in$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:442" + wire width 32 input 18 \raw_opcode_in + attribute \module_not_derived 1 + attribute \src "issuer_ls180.v:106269.13-106305.4" + cell \dec$193 \dec + connect \LDST_BA \dec_LDST_BA + connect \LDST_BB \dec_LDST_BB + connect \LDST_BC \dec_LDST_BC + connect \LDST_BD \dec_LDST_BD + connect \LDST_BI \dec_LDST_BI + connect \LDST_BT \dec_LDST_BT + connect \LDST_DS \dec_LDST_DS + connect \LDST_FXM \dec_LDST_FXM + connect \LDST_LI \dec_LDST_LI + connect \LDST_OE \dec_LDST_OE + connect \LDST_RA \dec_LDST_RA + connect \LDST_Rc \dec_LDST_Rc + connect \LDST_SH32 \dec_LDST_SH32 + connect \LDST_SI \dec_LDST_SI + connect \LDST_UI \dec_LDST_UI + connect \LDST_br \dec_LDST_br + connect \LDST_cr_in \dec_LDST_cr_in + connect \LDST_cr_out \dec_LDST_cr_out + connect \LDST_function_unit \dec_LDST_function_unit + connect \LDST_in1_sel \dec_LDST_in1_sel + connect \LDST_in2_sel \dec_LDST_in2_sel + connect \LDST_internal_op \dec_LDST_internal_op + connect \LDST_is_32b \dec_LDST_is_32b + connect \LDST_ldst_len \dec_LDST_ldst_len + connect \LDST_rc_sel \dec_LDST_rc_sel + connect \LDST_sgn \dec_LDST_sgn + connect \LDST_sgn_ext \dec_LDST_sgn_ext + connect \LDST_sh \dec_LDST_sh + connect \LDST_upd \dec_LDST_upd + connect \XL_BT \dec_XL_BT + connect \X_BF \dec_X_BF + connect \X_BFA \dec_X_BFA + connect \bigendian \bigendian + connect \opcode_in \dec_opcode_in + connect \raw_opcode_in \raw_opcode_in + end + attribute \module_not_derived 1 + attribute \src "issuer_ls180.v:106306.16-106310.4" + cell \dec_ai$200 \dec_ai + connect \LDST_RA \dec_LDST_RA + connect \immz_out \dec_ai_immz_out + connect \sel_in \dec_ai_sel_in + end + attribute \module_not_derived 1 + attribute \src "issuer_ls180.v:106311.16-106322.4" + cell \dec_bi$201 \dec_bi + connect \LDST_BD \dec_LDST_BD + connect \LDST_DS \dec_LDST_DS + connect \LDST_LI \dec_LDST_LI + connect \LDST_SH32 \dec_LDST_SH32 + connect \LDST_SI \dec_LDST_SI + connect \LDST_UI \dec_LDST_UI + connect \LDST_sh \dec_LDST_sh + connect \imm_b \dec_bi_imm_b + connect \imm_b_ok \dec_bi_imm_b_ok + connect \sel_in \dec_bi_sel_in + end + attribute \module_not_derived 1 + attribute \src "issuer_ls180.v:106323.19-106334.4" + cell \dec_cr_in$196 \dec_cr_in + connect \LDST_BA \dec_LDST_BA + connect \LDST_BB \dec_LDST_BB + connect \LDST_BC \dec_LDST_BC + connect \LDST_BI \dec_LDST_BI + connect \LDST_BT \dec_LDST_BT + connect \LDST_FXM \dec_LDST_FXM + connect \LDST_internal_op \dec_LDST_internal_op + connect \X_BFA \dec_X_BFA + connect \insn_in \dec_cr_in_insn_in + connect \sel_in \dec_cr_in_sel_in + end + attribute \module_not_derived 1 + attribute \src "issuer_ls180.v:106335.20-106343.4" + cell \dec_cr_out$198 \dec_cr_out + connect \LDST_FXM \dec_LDST_FXM + connect \LDST_internal_op \dec_LDST_internal_op + connect \XL_BT \dec_XL_BT + connect \X_BF \dec_X_BF + connect \insn_in \dec_cr_out_insn_in + connect \rc_in \dec_cr_out_rc_in + connect \sel_in \dec_cr_out_sel_in + end + attribute \module_not_derived 1 + attribute \src "issuer_ls180.v:106344.16-106350.4" + cell \dec_oe$195 \dec_oe + connect \LDST_OE \dec_LDST_OE + connect \LDST_internal_op \dec_LDST_internal_op + connect \oe \dec_oe_oe + connect \oe_ok \dec_oe_oe_ok + connect \sel_in \dec_oe_sel_in + end + attribute \module_not_derived 1 + attribute \src "issuer_ls180.v:106351.16-106356.4" + cell \dec_rc$194 \dec_rc + connect \LDST_Rc \dec_LDST_Rc + connect \rc \dec_rc_rc + connect \rc_ok \dec_rc_rc_ok + connect \sel_in \dec_rc_sel_in + end + connect \LDST_LDST__ldst_mode \dec_LDST_upd + connect \LDST_LDST__sign_extend \dec_LDST_sgn_ext + connect \LDST_LDST__byte_reverse \dec_LDST_br + connect \LDST_LDST__is_signed \dec_LDST_sgn + connect \LDST_LDST__is_32bit \dec_LDST_is_32b + connect \LDST_LDST__data_len \dec_LDST_ldst_len + connect { \LDST_LDST__oe__ok \LDST_LDST__oe__oe } { \dec_oe_oe_ok \dec_oe_oe } + connect { \LDST_LDST__rc__ok \LDST_LDST__rc__rc } { \dec_rc_rc_ok \dec_rc_rc } + connect { \LDST_LDST__imm_data__ok \LDST_LDST__imm_data__data } { \dec_bi_imm_b_ok \dec_bi_imm_b } + connect \dec_bi_sel_in \dec_LDST_in2_sel + connect \LDST_LDST__zero_a \dec_ai_immz_out + connect \dec_ai_sel_in \dec_LDST_in1_sel + connect \LDST_LDST__fn_unit \dec_LDST_function_unit + connect \LDST_LDST__insn_type \dec_LDST_internal_op + connect \dec_cr_out_rc_in \dec_rc_rc + connect \dec_cr_out_sel_in \dec_LDST_cr_out + connect \dec_cr_in_sel_in \dec_LDST_cr_in + connect \dec_oe_sel_in \dec_LDST_rc_sel + connect \dec_rc_sel_in \dec_LDST_rc_sel + connect \dec_cr_out_insn_in \dec_opcode_in + connect \dec_cr_in_insn_in \dec_opcode_in + connect \insn_in$1 \dec_opcode_in + connect \insn_in \dec_opcode_in + connect \LDST_LDST__insn \dec_opcode_in +end +attribute \src "issuer_ls180.v:106385.1-106918.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.dec_LOGICAL" +attribute \generator "nMigen" +module \dec_LOGICAL + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 output 18 \LOGICAL_LOGICAL__data_len + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 output 3 \LOGICAL_LOGICAL__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 output 4 \LOGICAL_LOGICAL__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 5 \LOGICAL_LOGICAL__imm_data__ok + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 output 12 \LOGICAL_LOGICAL__input_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 output 19 \LOGICAL_LOGICAL__insn + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 output 2 \LOGICAL_LOGICAL__insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 10 \LOGICAL_LOGICAL__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 13 \LOGICAL_LOGICAL__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 16 \LOGICAL_LOGICAL__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 17 \LOGICAL_LOGICAL__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 8 \LOGICAL_LOGICAL__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 9 \LOGICAL_LOGICAL__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 15 \LOGICAL_LOGICAL__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 7 \LOGICAL_LOGICAL__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 6 \LOGICAL_LOGICAL__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 14 \LOGICAL_LOGICAL__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 11 \LOGICAL_LOGICAL__zero_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + wire input 1 \bigendian + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 \dec_LOGICAL_BA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 \dec_LOGICAL_BB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 \dec_LOGICAL_BC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 14 \dec_LOGICAL_BD + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 \dec_LOGICAL_BI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 \dec_LOGICAL_BT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 14 \dec_LOGICAL_DS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 8 \dec_LOGICAL_FXM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 24 \dec_LOGICAL_LI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire \dec_LOGICAL_OE + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 \dec_LOGICAL_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire \dec_LOGICAL_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 \dec_LOGICAL_SH32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 16 \dec_LOGICAL_SI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 16 \dec_LOGICAL_UI + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 \dec_LOGICAL_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 \dec_LOGICAL_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \dec_LOGICAL_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec_LOGICAL_cry_out + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 12 \dec_LOGICAL_function_unit + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 \dec_LOGICAL_in1_sel + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 \dec_LOGICAL_in2_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 7 \dec_LOGICAL_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec_LOGICAL_inv_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec_LOGICAL_inv_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec_LOGICAL_is_32b + attribute \enum_base_type "LdstLen" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "is1B" + attribute \enum_value_0010 "is2B" + attribute \enum_value_0100 "is4B" + attribute \enum_value_1000 "is8B" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 \dec_LOGICAL_ldst_len + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \dec_LOGICAL_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec_LOGICAL_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 6 \dec_LOGICAL_sh + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \dec_XL_BT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 3 \dec_X_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 3 \dec_X_BFA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:149" + wire \dec_ai_immz_out + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:148" + wire width 3 \dec_ai_sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 \dec_bi_imm_b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \dec_bi_imm_b_ok + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:216" + wire width 4 \dec_bi_sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:485" + wire width 32 \dec_cr_in_insn_in + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:484" + wire width 3 \dec_cr_in_sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \dec_cr_out_cr_bitfield_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:550" + wire width 32 \dec_cr_out_insn_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:548" + wire \dec_cr_out_rc_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:549" + wire width 3 \dec_cr_out_sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \dec_oe_oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \dec_oe_oe_ok + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:441" + wire width 2 \dec_oe_sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + wire width 32 \dec_opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \dec_rc_rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \dec_rc_rc_ok + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:404" + wire width 2 \dec_rc_sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:405" + wire width 32 \insn_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:442" + wire width 32 \insn_in$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:442" + wire width 32 input 20 \raw_opcode_in + attribute \module_not_derived 1 + attribute \src "issuer_ls180.v:106802.13-106839.4" + cell \dec$152 \dec + connect \LOGICAL_BA \dec_LOGICAL_BA + connect \LOGICAL_BB \dec_LOGICAL_BB + connect \LOGICAL_BC \dec_LOGICAL_BC + connect \LOGICAL_BD \dec_LOGICAL_BD + connect \LOGICAL_BI \dec_LOGICAL_BI + connect \LOGICAL_BT \dec_LOGICAL_BT + connect \LOGICAL_DS \dec_LOGICAL_DS + connect \LOGICAL_FXM \dec_LOGICAL_FXM + connect \LOGICAL_LI \dec_LOGICAL_LI + connect \LOGICAL_OE \dec_LOGICAL_OE + connect \LOGICAL_RA \dec_LOGICAL_RA + connect \LOGICAL_Rc \dec_LOGICAL_Rc + connect \LOGICAL_SH32 \dec_LOGICAL_SH32 + connect \LOGICAL_SI \dec_LOGICAL_SI + connect \LOGICAL_UI \dec_LOGICAL_UI + connect \LOGICAL_cr_in \dec_LOGICAL_cr_in + connect \LOGICAL_cr_out \dec_LOGICAL_cr_out + connect \LOGICAL_cry_in \dec_LOGICAL_cry_in + connect \LOGICAL_cry_out \dec_LOGICAL_cry_out + connect \LOGICAL_function_unit \dec_LOGICAL_function_unit + connect \LOGICAL_in1_sel \dec_LOGICAL_in1_sel + connect \LOGICAL_in2_sel \dec_LOGICAL_in2_sel + connect \LOGICAL_internal_op \dec_LOGICAL_internal_op + connect \LOGICAL_inv_a \dec_LOGICAL_inv_a + connect \LOGICAL_inv_out \dec_LOGICAL_inv_out + connect \LOGICAL_is_32b \dec_LOGICAL_is_32b + connect \LOGICAL_ldst_len \dec_LOGICAL_ldst_len + connect \LOGICAL_rc_sel \dec_LOGICAL_rc_sel + connect \LOGICAL_sgn \dec_LOGICAL_sgn + connect \LOGICAL_sh \dec_LOGICAL_sh + connect \XL_BT \dec_XL_BT + connect \X_BF \dec_X_BF + connect \X_BFA \dec_X_BFA + connect \bigendian \bigendian + connect \opcode_in \dec_opcode_in + connect \raw_opcode_in \raw_opcode_in + end + attribute \module_not_derived 1 + attribute \src "issuer_ls180.v:106840.16-106844.4" + cell \dec_ai$159 \dec_ai + connect \LOGICAL_RA \dec_LOGICAL_RA + connect \immz_out \dec_ai_immz_out + connect \sel_in \dec_ai_sel_in + end + attribute \module_not_derived 1 + attribute \src "issuer_ls180.v:106845.16-106856.4" + cell \dec_bi$160 \dec_bi + connect \LOGICAL_BD \dec_LOGICAL_BD + connect \LOGICAL_DS \dec_LOGICAL_DS + connect \LOGICAL_LI \dec_LOGICAL_LI + connect \LOGICAL_SH32 \dec_LOGICAL_SH32 + connect \LOGICAL_SI \dec_LOGICAL_SI + connect \LOGICAL_UI \dec_LOGICAL_UI + connect \LOGICAL_sh \dec_LOGICAL_sh + connect \imm_b \dec_bi_imm_b + connect \imm_b_ok \dec_bi_imm_b_ok + connect \sel_in \dec_bi_sel_in + end + attribute \module_not_derived 1 + attribute \src "issuer_ls180.v:106857.19-106868.4" + cell \dec_cr_in$155 \dec_cr_in + connect \LOGICAL_BA \dec_LOGICAL_BA + connect \LOGICAL_BB \dec_LOGICAL_BB + connect \LOGICAL_BC \dec_LOGICAL_BC + connect \LOGICAL_BI \dec_LOGICAL_BI + connect \LOGICAL_BT \dec_LOGICAL_BT + connect \LOGICAL_FXM \dec_LOGICAL_FXM + connect \LOGICAL_internal_op \dec_LOGICAL_internal_op + connect \X_BFA \dec_X_BFA + connect \insn_in \dec_cr_in_insn_in + connect \sel_in \dec_cr_in_sel_in + end + attribute \module_not_derived 1 + attribute \src "issuer_ls180.v:106869.20-106878.4" + cell \dec_cr_out$157 \dec_cr_out + connect \LOGICAL_FXM \dec_LOGICAL_FXM + connect \LOGICAL_internal_op \dec_LOGICAL_internal_op + connect \XL_BT \dec_XL_BT + connect \X_BF \dec_X_BF + connect \cr_bitfield_ok \dec_cr_out_cr_bitfield_ok + connect \insn_in \dec_cr_out_insn_in + connect \rc_in \dec_cr_out_rc_in + connect \sel_in \dec_cr_out_sel_in + end + attribute \module_not_derived 1 + attribute \src "issuer_ls180.v:106879.16-106885.4" + cell \dec_oe$154 \dec_oe + connect \LOGICAL_OE \dec_LOGICAL_OE + connect \LOGICAL_internal_op \dec_LOGICAL_internal_op + connect \oe \dec_oe_oe + connect \oe_ok \dec_oe_oe_ok + connect \sel_in \dec_oe_sel_in + end + attribute \module_not_derived 1 + attribute \src "issuer_ls180.v:106886.16-106891.4" + cell \dec_rc$153 \dec_rc + connect \LOGICAL_Rc \dec_LOGICAL_Rc + connect \rc \dec_rc_rc + connect \rc_ok \dec_rc_rc_ok + connect \sel_in \dec_rc_sel_in + end + connect \LOGICAL_LOGICAL__is_signed \dec_LOGICAL_sgn + connect \LOGICAL_LOGICAL__is_32bit \dec_LOGICAL_is_32b + connect \LOGICAL_LOGICAL__output_carry \dec_LOGICAL_cry_out + connect \LOGICAL_LOGICAL__input_carry \dec_LOGICAL_cry_in + connect \LOGICAL_LOGICAL__invert_out \dec_LOGICAL_inv_out + connect \LOGICAL_LOGICAL__invert_in \dec_LOGICAL_inv_a + connect \LOGICAL_LOGICAL__data_len \dec_LOGICAL_ldst_len + connect \LOGICAL_LOGICAL__write_cr0 \dec_cr_out_cr_bitfield_ok + connect { \LOGICAL_LOGICAL__oe__ok \LOGICAL_LOGICAL__oe__oe } { \dec_oe_oe_ok \dec_oe_oe } + connect { \LOGICAL_LOGICAL__rc__ok \LOGICAL_LOGICAL__rc__rc } { \dec_rc_rc_ok \dec_rc_rc } + connect { \LOGICAL_LOGICAL__imm_data__ok \LOGICAL_LOGICAL__imm_data__data } { \dec_bi_imm_b_ok \dec_bi_imm_b } + connect \dec_bi_sel_in \dec_LOGICAL_in2_sel + connect \LOGICAL_LOGICAL__zero_a \dec_ai_immz_out + connect \dec_ai_sel_in \dec_LOGICAL_in1_sel + connect \LOGICAL_LOGICAL__fn_unit \dec_LOGICAL_function_unit + connect \LOGICAL_LOGICAL__insn_type \dec_LOGICAL_internal_op + connect \dec_cr_out_rc_in \dec_rc_rc + connect \dec_cr_out_sel_in \dec_LOGICAL_cr_out + connect \dec_cr_in_sel_in \dec_LOGICAL_cr_in + connect \dec_oe_sel_in \dec_LOGICAL_rc_sel + connect \dec_rc_sel_in \dec_LOGICAL_rc_sel + connect \dec_cr_out_insn_in \dec_opcode_in + connect \dec_cr_in_insn_in \dec_opcode_in + connect \insn_in$1 \dec_opcode_in + connect \insn_in \dec_opcode_in + connect \LOGICAL_LOGICAL__insn \dec_opcode_in +end +attribute \src "issuer_ls180.v:106922.1-107380.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.dec_MUL" +attribute \generator "nMigen" +module \dec_MUL + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 output 3 \MUL_MUL__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 output 4 \MUL_MUL__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 5 \MUL_MUL__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 output 13 \MUL_MUL__insn + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 output 2 \MUL_MUL__insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 11 \MUL_MUL__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 12 \MUL_MUL__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 8 \MUL_MUL__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 9 \MUL_MUL__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 7 \MUL_MUL__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 6 \MUL_MUL__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 10 \MUL_MUL__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + wire input 1 \bigendian + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 \dec_MUL_BA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 \dec_MUL_BB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 \dec_MUL_BC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 14 \dec_MUL_BD + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 \dec_MUL_BI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 \dec_MUL_BT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 14 \dec_MUL_DS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 8 \dec_MUL_FXM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 24 \dec_MUL_LI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire \dec_MUL_OE + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire \dec_MUL_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 \dec_MUL_SH32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 16 \dec_MUL_SI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 16 \dec_MUL_UI + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 \dec_MUL_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 \dec_MUL_cr_out + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 12 \dec_MUL_function_unit + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 \dec_MUL_in2_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 7 \dec_MUL_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec_MUL_is_32b + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \dec_MUL_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec_MUL_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 6 \dec_MUL_sh + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \dec_XL_BT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 3 \dec_X_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 3 \dec_X_BFA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 \dec_bi_imm_b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \dec_bi_imm_b_ok + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:216" + wire width 4 \dec_bi_sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:485" + wire width 32 \dec_cr_in_insn_in + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:484" + wire width 3 \dec_cr_in_sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \dec_cr_out_cr_bitfield_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:550" + wire width 32 \dec_cr_out_insn_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:548" + wire \dec_cr_out_rc_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:549" + wire width 3 \dec_cr_out_sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \dec_oe_oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \dec_oe_oe_ok + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:441" + wire width 2 \dec_oe_sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + wire width 32 \dec_opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \dec_rc_rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \dec_rc_rc_ok + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:404" + wire width 2 \dec_rc_sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:405" + wire width 32 \insn_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:442" + wire width 32 \insn_in$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:442" + wire width 32 input 14 \raw_opcode_in + attribute \module_not_derived 1 + attribute \src "issuer_ls180.v:107283.13-107313.4" + cell \dec$177 \dec + connect \MUL_BA \dec_MUL_BA + connect \MUL_BB \dec_MUL_BB + connect \MUL_BC \dec_MUL_BC + connect \MUL_BD \dec_MUL_BD + connect \MUL_BI \dec_MUL_BI + connect \MUL_BT \dec_MUL_BT + connect \MUL_DS \dec_MUL_DS + connect \MUL_FXM \dec_MUL_FXM + connect \MUL_LI \dec_MUL_LI + connect \MUL_OE \dec_MUL_OE + connect \MUL_Rc \dec_MUL_Rc + connect \MUL_SH32 \dec_MUL_SH32 + connect \MUL_SI \dec_MUL_SI + connect \MUL_UI \dec_MUL_UI + connect \MUL_cr_in \dec_MUL_cr_in + connect \MUL_cr_out \dec_MUL_cr_out + connect \MUL_function_unit \dec_MUL_function_unit + connect \MUL_in2_sel \dec_MUL_in2_sel + connect \MUL_internal_op \dec_MUL_internal_op + connect \MUL_is_32b \dec_MUL_is_32b + connect \MUL_rc_sel \dec_MUL_rc_sel + connect \MUL_sgn \dec_MUL_sgn + connect \MUL_sh \dec_MUL_sh + connect \XL_BT \dec_XL_BT + connect \X_BF \dec_X_BF + connect \X_BFA \dec_X_BFA + connect \bigendian \bigendian + connect \opcode_in \dec_opcode_in + connect \raw_opcode_in \raw_opcode_in + end + attribute \module_not_derived 1 + attribute \src "issuer_ls180.v:107314.16-107325.4" + cell \dec_bi$184 \dec_bi + connect \MUL_BD \dec_MUL_BD + connect \MUL_DS \dec_MUL_DS + connect \MUL_LI \dec_MUL_LI + connect \MUL_SH32 \dec_MUL_SH32 + connect \MUL_SI \dec_MUL_SI + connect \MUL_UI \dec_MUL_UI + connect \MUL_sh \dec_MUL_sh + connect \imm_b \dec_bi_imm_b + connect \imm_b_ok \dec_bi_imm_b_ok + connect \sel_in \dec_bi_sel_in + end + attribute \module_not_derived 1 + attribute \src "issuer_ls180.v:107326.19-107337.4" + cell \dec_cr_in$180 \dec_cr_in + connect \MUL_BA \dec_MUL_BA + connect \MUL_BB \dec_MUL_BB + connect \MUL_BC \dec_MUL_BC + connect \MUL_BI \dec_MUL_BI + connect \MUL_BT \dec_MUL_BT + connect \MUL_FXM \dec_MUL_FXM + connect \MUL_internal_op \dec_MUL_internal_op + connect \X_BFA \dec_X_BFA + connect \insn_in \dec_cr_in_insn_in + connect \sel_in \dec_cr_in_sel_in + end + attribute \module_not_derived 1 + attribute \src "issuer_ls180.v:107338.20-107347.4" + cell \dec_cr_out$182 \dec_cr_out + connect \MUL_FXM \dec_MUL_FXM + connect \MUL_internal_op \dec_MUL_internal_op + connect \XL_BT \dec_XL_BT + connect \X_BF \dec_X_BF + connect \cr_bitfield_ok \dec_cr_out_cr_bitfield_ok + connect \insn_in \dec_cr_out_insn_in + connect \rc_in \dec_cr_out_rc_in + connect \sel_in \dec_cr_out_sel_in + end + attribute \module_not_derived 1 + attribute \src "issuer_ls180.v:107348.16-107354.4" + cell \dec_oe$179 \dec_oe + connect \MUL_OE \dec_MUL_OE + connect \MUL_internal_op \dec_MUL_internal_op + connect \oe \dec_oe_oe + connect \oe_ok \dec_oe_oe_ok + connect \sel_in \dec_oe_sel_in + end + attribute \module_not_derived 1 + attribute \src "issuer_ls180.v:107355.16-107360.4" + cell \dec_rc$178 \dec_rc + connect \MUL_Rc \dec_MUL_Rc + connect \rc \dec_rc_rc + connect \rc_ok \dec_rc_rc_ok + connect \sel_in \dec_rc_sel_in + end + connect \MUL_MUL__is_signed \dec_MUL_sgn + connect \MUL_MUL__is_32bit \dec_MUL_is_32b + connect \MUL_MUL__write_cr0 \dec_cr_out_cr_bitfield_ok + connect { \MUL_MUL__oe__ok \MUL_MUL__oe__oe } { \dec_oe_oe_ok \dec_oe_oe } + connect { \MUL_MUL__rc__ok \MUL_MUL__rc__rc } { \dec_rc_rc_ok \dec_rc_rc } + connect { \MUL_MUL__imm_data__ok \MUL_MUL__imm_data__data } { \dec_bi_imm_b_ok \dec_bi_imm_b } + connect \dec_bi_sel_in \dec_MUL_in2_sel + connect \MUL_MUL__fn_unit \dec_MUL_function_unit + connect \MUL_MUL__insn_type \dec_MUL_internal_op + connect \dec_cr_out_rc_in \dec_rc_rc + connect \dec_cr_out_sel_in \dec_MUL_cr_out + connect \dec_cr_in_sel_in \dec_MUL_cr_in + connect \dec_oe_sel_in \dec_MUL_rc_sel + connect \dec_rc_sel_in \dec_MUL_rc_sel + connect \dec_cr_out_insn_in \dec_opcode_in + connect \dec_cr_in_insn_in \dec_opcode_in + connect \insn_in$1 \dec_opcode_in + connect \insn_in \dec_opcode_in + connect \MUL_MUL__insn \dec_opcode_in +end +attribute \src "issuer_ls180.v:107384.1-107868.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.dec_SHIFT_ROT" +attribute \generator "nMigen" +module \dec_SHIFT_ROT + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 output 3 \SHIFT_ROT_SHIFT_ROT__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 output 4 \SHIFT_ROT_SHIFT_ROT__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 5 \SHIFT_ROT_SHIFT_ROT__imm_data__ok + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 output 11 \SHIFT_ROT_SHIFT_ROT__input_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 13 \SHIFT_ROT_SHIFT_ROT__input_cr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 output 17 \SHIFT_ROT_SHIFT_ROT__insn + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 output 2 \SHIFT_ROT_SHIFT_ROT__insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 15 \SHIFT_ROT_SHIFT_ROT__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 16 \SHIFT_ROT_SHIFT_ROT__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 8 \SHIFT_ROT_SHIFT_ROT__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 9 \SHIFT_ROT_SHIFT_ROT__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 12 \SHIFT_ROT_SHIFT_ROT__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 14 \SHIFT_ROT_SHIFT_ROT__output_cr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 7 \SHIFT_ROT_SHIFT_ROT__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 6 \SHIFT_ROT_SHIFT_ROT__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 10 \SHIFT_ROT_SHIFT_ROT__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + wire input 1 \bigendian + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 \dec_SHIFT_ROT_BA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 \dec_SHIFT_ROT_BB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 \dec_SHIFT_ROT_BC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 14 \dec_SHIFT_ROT_BD + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 \dec_SHIFT_ROT_BI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 \dec_SHIFT_ROT_BT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 14 \dec_SHIFT_ROT_DS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 8 \dec_SHIFT_ROT_FXM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 24 \dec_SHIFT_ROT_LI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire \dec_SHIFT_ROT_OE + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire \dec_SHIFT_ROT_Rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 \dec_SHIFT_ROT_SH32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 16 \dec_SHIFT_ROT_SI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 16 \dec_SHIFT_ROT_UI + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 \dec_SHIFT_ROT_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 \dec_SHIFT_ROT_cr_out + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \dec_SHIFT_ROT_cry_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec_SHIFT_ROT_cry_out + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 12 \dec_SHIFT_ROT_function_unit + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 4 \dec_SHIFT_ROT_in2_sel + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 7 \dec_SHIFT_ROT_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec_SHIFT_ROT_is_32b + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 \dec_SHIFT_ROT_rc_sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:177" + wire \dec_SHIFT_ROT_sgn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 6 \dec_SHIFT_ROT_sh + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 \dec_XL_BT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 3 \dec_X_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 3 \dec_X_BFA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 \dec_bi_imm_b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \dec_bi_imm_b_ok + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:216" + wire width 4 \dec_bi_sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:485" + wire width 32 \dec_cr_in_insn_in + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:484" + wire width 3 \dec_cr_in_sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \dec_cr_out_cr_bitfield_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:550" + wire width 32 \dec_cr_out_insn_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:548" + wire \dec_cr_out_rc_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:549" + wire width 3 \dec_cr_out_sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \dec_oe_oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \dec_oe_oe_ok + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:441" + wire width 2 \dec_oe_sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + wire width 32 \dec_opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \dec_rc_rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \dec_rc_rc_ok + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:404" + wire width 2 \dec_rc_sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:405" + wire width 32 \insn_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:442" + wire width 32 \insn_in$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:442" + wire width 32 input 18 \raw_opcode_in + attribute \module_not_derived 1 + attribute \src "issuer_ls180.v:107765.13-107797.4" + cell \dec$185 \dec + connect \SHIFT_ROT_BA \dec_SHIFT_ROT_BA + connect \SHIFT_ROT_BB \dec_SHIFT_ROT_BB + connect \SHIFT_ROT_BC \dec_SHIFT_ROT_BC + connect \SHIFT_ROT_BD \dec_SHIFT_ROT_BD + connect \SHIFT_ROT_BI \dec_SHIFT_ROT_BI + connect \SHIFT_ROT_BT \dec_SHIFT_ROT_BT + connect \SHIFT_ROT_DS \dec_SHIFT_ROT_DS + connect \SHIFT_ROT_FXM \dec_SHIFT_ROT_FXM + connect \SHIFT_ROT_LI \dec_SHIFT_ROT_LI + connect \SHIFT_ROT_OE \dec_SHIFT_ROT_OE + connect \SHIFT_ROT_Rc \dec_SHIFT_ROT_Rc + connect \SHIFT_ROT_SH32 \dec_SHIFT_ROT_SH32 + connect \SHIFT_ROT_SI \dec_SHIFT_ROT_SI + connect \SHIFT_ROT_UI \dec_SHIFT_ROT_UI + connect \SHIFT_ROT_cr_in \dec_SHIFT_ROT_cr_in + connect \SHIFT_ROT_cr_out \dec_SHIFT_ROT_cr_out + connect \SHIFT_ROT_cry_in \dec_SHIFT_ROT_cry_in + connect \SHIFT_ROT_cry_out \dec_SHIFT_ROT_cry_out + connect \SHIFT_ROT_function_unit \dec_SHIFT_ROT_function_unit + connect \SHIFT_ROT_in2_sel \dec_SHIFT_ROT_in2_sel + connect \SHIFT_ROT_internal_op \dec_SHIFT_ROT_internal_op + connect \SHIFT_ROT_is_32b \dec_SHIFT_ROT_is_32b + connect \SHIFT_ROT_rc_sel \dec_SHIFT_ROT_rc_sel + connect \SHIFT_ROT_sgn \dec_SHIFT_ROT_sgn + connect \SHIFT_ROT_sh \dec_SHIFT_ROT_sh + connect \XL_BT \dec_XL_BT + connect \X_BF \dec_X_BF + connect \X_BFA \dec_X_BFA + connect \bigendian \bigendian + connect \opcode_in \dec_opcode_in + connect \raw_opcode_in \raw_opcode_in + end + attribute \module_not_derived 1 + attribute \src "issuer_ls180.v:107798.16-107809.4" + cell \dec_bi$192 \dec_bi + connect \SHIFT_ROT_BD \dec_SHIFT_ROT_BD + connect \SHIFT_ROT_DS \dec_SHIFT_ROT_DS + connect \SHIFT_ROT_LI \dec_SHIFT_ROT_LI + connect \SHIFT_ROT_SH32 \dec_SHIFT_ROT_SH32 + connect \SHIFT_ROT_SI \dec_SHIFT_ROT_SI + connect \SHIFT_ROT_UI \dec_SHIFT_ROT_UI + connect \SHIFT_ROT_sh \dec_SHIFT_ROT_sh + connect \imm_b \dec_bi_imm_b + connect \imm_b_ok \dec_bi_imm_b_ok + connect \sel_in \dec_bi_sel_in + end + attribute \module_not_derived 1 + attribute \src "issuer_ls180.v:107810.19-107821.4" + cell \dec_cr_in$188 \dec_cr_in + connect \SHIFT_ROT_BA \dec_SHIFT_ROT_BA + connect \SHIFT_ROT_BB \dec_SHIFT_ROT_BB + connect \SHIFT_ROT_BC \dec_SHIFT_ROT_BC + connect \SHIFT_ROT_BI \dec_SHIFT_ROT_BI + connect \SHIFT_ROT_BT \dec_SHIFT_ROT_BT + connect \SHIFT_ROT_FXM \dec_SHIFT_ROT_FXM + connect \SHIFT_ROT_internal_op \dec_SHIFT_ROT_internal_op + connect \X_BFA \dec_X_BFA + connect \insn_in \dec_cr_in_insn_in + connect \sel_in \dec_cr_in_sel_in + end + attribute \module_not_derived 1 + attribute \src "issuer_ls180.v:107822.20-107831.4" + cell \dec_cr_out$190 \dec_cr_out + connect \SHIFT_ROT_FXM \dec_SHIFT_ROT_FXM + connect \SHIFT_ROT_internal_op \dec_SHIFT_ROT_internal_op + connect \XL_BT \dec_XL_BT + connect \X_BF \dec_X_BF + connect \cr_bitfield_ok \dec_cr_out_cr_bitfield_ok + connect \insn_in \dec_cr_out_insn_in + connect \rc_in \dec_cr_out_rc_in + connect \sel_in \dec_cr_out_sel_in + end + attribute \module_not_derived 1 + attribute \src "issuer_ls180.v:107832.16-107838.4" + cell \dec_oe$187 \dec_oe + connect \SHIFT_ROT_OE \dec_SHIFT_ROT_OE + connect \SHIFT_ROT_internal_op \dec_SHIFT_ROT_internal_op + connect \oe \dec_oe_oe + connect \oe_ok \dec_oe_oe_ok + connect \sel_in \dec_oe_sel_in + end + attribute \module_not_derived 1 + attribute \src "issuer_ls180.v:107839.16-107844.4" + cell \dec_rc$186 \dec_rc + connect \SHIFT_ROT_Rc \dec_SHIFT_ROT_Rc + connect \rc \dec_rc_rc + connect \rc_ok \dec_rc_rc_ok + connect \sel_in \dec_rc_sel_in + end + connect \SHIFT_ROT_SHIFT_ROT__is_signed \dec_SHIFT_ROT_sgn + connect \SHIFT_ROT_SHIFT_ROT__is_32bit \dec_SHIFT_ROT_is_32b + connect \SHIFT_ROT_SHIFT_ROT__output_carry \dec_SHIFT_ROT_cry_out + connect \SHIFT_ROT_SHIFT_ROT__input_carry \dec_SHIFT_ROT_cry_in + connect \SHIFT_ROT_SHIFT_ROT__output_cr \dec_SHIFT_ROT_cr_out [0] + connect \SHIFT_ROT_SHIFT_ROT__input_cr \dec_SHIFT_ROT_cr_in [0] + connect \SHIFT_ROT_SHIFT_ROT__write_cr0 \dec_cr_out_cr_bitfield_ok + connect { \SHIFT_ROT_SHIFT_ROT__oe__ok \SHIFT_ROT_SHIFT_ROT__oe__oe } { \dec_oe_oe_ok \dec_oe_oe } + connect { \SHIFT_ROT_SHIFT_ROT__rc__ok \SHIFT_ROT_SHIFT_ROT__rc__rc } { \dec_rc_rc_ok \dec_rc_rc } + connect { \SHIFT_ROT_SHIFT_ROT__imm_data__ok \SHIFT_ROT_SHIFT_ROT__imm_data__data } { \dec_bi_imm_b_ok \dec_bi_imm_b } + connect \dec_bi_sel_in \dec_SHIFT_ROT_in2_sel + connect \SHIFT_ROT_SHIFT_ROT__fn_unit \dec_SHIFT_ROT_function_unit + connect \SHIFT_ROT_SHIFT_ROT__insn_type \dec_SHIFT_ROT_internal_op + connect \dec_cr_out_rc_in \dec_rc_rc + connect \dec_cr_out_sel_in \dec_SHIFT_ROT_cr_out + connect \dec_cr_in_sel_in \dec_SHIFT_ROT_cr_in + connect \dec_oe_sel_in \dec_SHIFT_ROT_rc_sel + connect \dec_rc_sel_in \dec_SHIFT_ROT_rc_sel + connect \dec_cr_out_insn_in \dec_opcode_in + connect \dec_cr_in_insn_in \dec_opcode_in + connect \insn_in$1 \dec_opcode_in + connect \insn_in \dec_opcode_in + connect \SHIFT_ROT_SHIFT_ROT__insn \dec_opcode_in +end +attribute \src "issuer_ls180.v:107872.1-108221.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.dec_SPR" +attribute \generator "nMigen" +module \dec_SPR + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 output 3 \SPR_SPR__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 output 4 \SPR_SPR__insn + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 output 2 \SPR_SPR__insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 5 \SPR_SPR__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:443" + wire input 1 \bigendian + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 \dec_SPR_BA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 \dec_SPR_BB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 \dec_SPR_BC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 \dec_SPR_BI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 \dec_SPR_BT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 8 \dec_SPR_FXM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire \dec_SPR_OE + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire \dec_SPR_Rc + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 \dec_SPR_cr_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 3 \dec_SPR_cr_out + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 12 \dec_SPR_function_unit + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 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attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:549" + wire width 3 \dec_cr_out_sel_in + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:441" + wire width 2 \dec_oe_sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:283" + wire width 32 \dec_opcode_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \dec_rc_rc + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:404" + wire width 2 \dec_rc_sel_in + attribute \src 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\enum_value_0000000011 "DSCR" + attribute \enum_value_0000001000 "LR" + attribute \enum_value_0000001001 "CTR" + attribute \enum_value_0000001101 "AMR" + attribute \enum_value_0000010001 "DSCR_priv" + attribute \enum_value_0000010010 "DSISR" + attribute \enum_value_0000010011 "DAR" + attribute \enum_value_0000010110 "DEC" + attribute \enum_value_0000011010 "SRR0" + attribute \enum_value_0000011011 "SRR1" + attribute \enum_value_0000011100 "CFAR" + attribute \enum_value_0000011101 "AMR_priv" + attribute \enum_value_0000110000 "PIDR" + attribute \enum_value_0000111101 "IAMR" + attribute \enum_value_0010000000 "TFHAR" + attribute \enum_value_0010000001 "TFIAR" + attribute \enum_value_0010000010 "TEXASR" + attribute \enum_value_0010000011 "TEXASRU" + attribute \enum_value_0010001000 "CTRL" + attribute \enum_value_0010010000 "TIDR" + attribute \enum_value_0010011000 "CTRL_priv" + attribute \enum_value_0010011001 "FSCR" + attribute \enum_value_0010011101 "UAMOR" + attribute \enum_value_0010011110 "GSR" + attribute \enum_value_0010011111 "PSPB" + attribute \enum_value_0010110000 "DPDES" + attribute \enum_value_0010110100 "DAWR0" + attribute \enum_value_0010111010 "RPR" + attribute \enum_value_0010111011 "CIABR" + attribute \enum_value_0010111100 "DAWRX0" + attribute \enum_value_0010111110 "HFSCR" + attribute \enum_value_0100000000 "VRSAVE" + attribute \enum_value_0100000011 "SPRG3" + attribute \enum_value_0100001100 "TB" + attribute \enum_value_0100001101 "TBU" + attribute \enum_value_0100010000 "SPRG0_priv" + attribute \enum_value_0100010001 "SPRG1_priv" + attribute \enum_value_0100010010 "SPRG2_priv" + attribute \enum_value_0100010011 "SPRG3_priv" + attribute \enum_value_0100011011 "CIR" + attribute \enum_value_0100011100 "TBL" + attribute \enum_value_0100011101 "TBU_hypv" + attribute \enum_value_0100011110 "TBU40" + attribute \enum_value_0100011111 "PVR" + attribute \enum_value_0100110000 "HSPRG0" + attribute \enum_value_0100110001 "HSPRG1" + attribute \enum_value_0100110010 "HDSISR" + attribute \enum_value_0100110011 "HDAR" + attribute \enum_value_0100110100 "SPURR" + attribute \enum_value_0100110101 "PURR" + attribute \enum_value_0100110110 "HDEC" + attribute \enum_value_0100111001 "HRMOR" + attribute \enum_value_0100111010 "HSRR0" + attribute \enum_value_0100111011 "HSRR1" + attribute \enum_value_0100111110 "LPCR" + attribute \enum_value_0100111111 "LPIDR" + attribute \enum_value_0101010000 "HMER" + attribute \enum_value_0101010001 "HMEER" + attribute \enum_value_0101010010 "PCR" + attribute \enum_value_0101010011 "HEIR" + attribute \enum_value_0101011101 "AMOR" + attribute \enum_value_0110111110 "TIR" + attribute \enum_value_0111010000 "PTCR" + attribute \enum_value_1100000000 "SIER" + attribute \enum_value_1100000001 "MMCR2" + attribute \enum_value_1100000010 "MMCRA" + attribute \enum_value_1100000011 "PMC1" + attribute \enum_value_1100000100 "PMC2" + attribute \enum_value_1100000101 "PMC3" + attribute \enum_value_1100000110 "PMC4" + attribute \enum_value_1100000111 "PMC5" + attribute \enum_value_1100001000 "PMC6" + attribute \enum_value_1100001011 "MMCR0" + attribute \enum_value_1100001100 "SIAR" + attribute \enum_value_1100001101 "SDAR" + attribute \enum_value_1100001110 "MMCR1" + attribute \enum_value_1100010000 "SIER_priv" + attribute \enum_value_1100010001 "MMCR2_priv" + attribute \enum_value_1100010010 "MMCRA_priv" + attribute \enum_value_1100010011 "PMC1_priv" + attribute \enum_value_1100010100 "PMC2_priv" + attribute \enum_value_1100010101 "PMC3_priv" + attribute \enum_value_1100010110 "PMC4_priv" + attribute \enum_value_1100010111 "PMC5_priv" + attribute \enum_value_1100011000 "PMC6_priv" + attribute \enum_value_1100011011 "MMCR0_priv" + attribute \enum_value_1100011100 "SIAR_priv" + attribute \enum_value_1100011101 "SDAR_priv" + attribute \enum_value_1100011110 "MMCR1_priv" + attribute \enum_value_1100100000 "BESCRS" + attribute \enum_value_1100100001 "BESCRSU" + attribute \enum_value_1100100010 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attribute \enum_value_0010000000 "TFHAR" + attribute \enum_value_0010000001 "TFIAR" + attribute \enum_value_0010000010 "TEXASR" + attribute \enum_value_0010000011 "TEXASRU" + attribute \enum_value_0010001000 "CTRL" + attribute \enum_value_0010010000 "TIDR" + attribute \enum_value_0010011000 "CTRL_priv" + attribute \enum_value_0010011001 "FSCR" + attribute \enum_value_0010011101 "UAMOR" + attribute \enum_value_0010011110 "GSR" + attribute \enum_value_0010011111 "PSPB" + attribute \enum_value_0010110000 "DPDES" + attribute \enum_value_0010110100 "DAWR0" + attribute \enum_value_0010111010 "RPR" + attribute \enum_value_0010111011 "CIABR" + attribute \enum_value_0010111100 "DAWRX0" + attribute \enum_value_0010111110 "HFSCR" + attribute \enum_value_0100000000 "VRSAVE" + attribute \enum_value_0100000011 "SPRG3" + attribute \enum_value_0100001100 "TB" + attribute \enum_value_0100001101 "TBU" + attribute \enum_value_0100010000 "SPRG0_priv" + attribute \enum_value_0100010001 "SPRG1_priv" + attribute \enum_value_0100010010 "SPRG2_priv" + attribute \enum_value_0100010011 "SPRG3_priv" + attribute \enum_value_0100011011 "CIR" + attribute \enum_value_0100011100 "TBL" + attribute \enum_value_0100011101 "TBU_hypv" + attribute \enum_value_0100011110 "TBU40" + attribute \enum_value_0100011111 "PVR" + attribute \enum_value_0100110000 "HSPRG0" + attribute \enum_value_0100110001 "HSPRG1" + attribute \enum_value_0100110010 "HDSISR" + attribute \enum_value_0100110011 "HDAR" + attribute \enum_value_0100110100 "SPURR" + attribute \enum_value_0100110101 "PURR" + attribute \enum_value_0100110110 "HDEC" + attribute \enum_value_0100111001 "HRMOR" + attribute \enum_value_0100111010 "HSRR0" + attribute \enum_value_0100111011 "HSRR1" + attribute \enum_value_0100111110 "LPCR" + attribute \enum_value_0100111111 "LPIDR" + attribute \enum_value_0101010000 "HMER" + attribute \enum_value_0101010001 "HMEER" + attribute \enum_value_0101010010 "PCR" + attribute \enum_value_0101010011 "HEIR" + attribute \enum_value_0101011101 "AMOR" + attribute \enum_value_0110111110 "TIR" + attribute \enum_value_0111010000 "PTCR" + attribute \enum_value_1100000000 "SIER" + attribute \enum_value_1100000001 "MMCR2" + attribute \enum_value_1100000010 "MMCRA" + attribute \enum_value_1100000011 "PMC1" + attribute \enum_value_1100000100 "PMC2" + attribute \enum_value_1100000101 "PMC3" + attribute \enum_value_1100000110 "PMC4" + attribute \enum_value_1100000111 "PMC5" + attribute \enum_value_1100001000 "PMC6" + attribute \enum_value_1100001011 "MMCR0" + attribute \enum_value_1100001100 "SIAR" + attribute \enum_value_1100001101 "SDAR" + attribute \enum_value_1100001110 "MMCR1" + attribute \enum_value_1100010000 "SIER_priv" + attribute \enum_value_1100010001 "MMCR2_priv" + attribute \enum_value_1100010010 "MMCRA_priv" + attribute \enum_value_1100010011 "PMC1_priv" + attribute \enum_value_1100010100 "PMC2_priv" + attribute \enum_value_1100010101 "PMC3_priv" + attribute \enum_value_1100010110 "PMC4_priv" + attribute \enum_value_1100010111 "PMC5_priv" + attribute \enum_value_1100011000 "PMC6_priv" + attribute \enum_value_1100011011 "MMCR0_priv" + attribute \enum_value_1100011100 "SIAR_priv" + attribute \enum_value_1100011101 "SDAR_priv" + attribute \enum_value_1100011110 "MMCR1_priv" + attribute \enum_value_1100100000 "BESCRS" + attribute \enum_value_1100100001 "BESCRSU" + attribute \enum_value_1100100010 "BESCRR" + attribute \enum_value_1100100011 "BESCRRU" + attribute \enum_value_1100100100 "EBBHR" + attribute \enum_value_1100100101 "EBBRR" + attribute \enum_value_1100100110 "BESCR" + attribute \enum_value_1100101000 "reserved808" + attribute \enum_value_1100101001 "reserved809" + attribute \enum_value_1100101010 "reserved810" + attribute \enum_value_1100101011 "reserved811" + attribute \enum_value_1100101111 "TAR" + attribute \enum_value_1100110000 "ASDR" + attribute \enum_value_1100110111 "PSSCR" + attribute \enum_value_1101010000 "IC" + attribute \enum_value_1101010001 "VTB" + attribute \enum_value_1101010111 "PSSCR_hypv" + attribute \enum_value_1110000000 "PPR" + attribute \enum_value_1110000010 "PPR32" + attribute \enum_value_1111111111 "PIR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 10 \sprmap_spr_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \sprmap_spr_o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:101" + cell $and $and$issuer_ls180.v:108611$4104 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$15 + connect \B \$17 + connect \Y $and$issuer_ls180.v:108611$4104_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:123" + cell $and $and$issuer_ls180.v:108616$4109 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \XL_XO [9] + connect \B \$27 + connect \Y $and$issuer_ls180.v:108616$4109_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:101" + cell $and $and$issuer_ls180.v:108619$4112 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$3 + connect \B \$5 + connect \Y $and$issuer_ls180.v:108619$4112_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:106" + cell $eq $eq$issuer_ls180.v:108606$4099 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \sel_in + connect \B 3'100 + connect \Y $eq$issuer_ls180.v:108606$4099_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:99" + cell $eq $eq$issuer_ls180.v:108607$4100 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \sel_in + connect \B 3'001 + connect \Y $eq$issuer_ls180.v:108607$4100_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:100" + cell $eq $eq$issuer_ls180.v:108608$4101 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \sel_in + connect \B 3'010 + connect \Y $eq$issuer_ls180.v:108608$4101_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:99" + cell $eq $eq$issuer_ls180.v:108610$4103 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \sel_in + connect \B 3'001 + connect \Y $eq$issuer_ls180.v:108610$4103_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:106" + cell $eq $eq$issuer_ls180.v:108613$4106 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \sel_in + connect \B 3'100 + connect \Y $eq$issuer_ls180.v:108613$4106_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:100" + cell $eq $eq$issuer_ls180.v:108617$4110 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \sel_in + connect \B 3'010 + connect \Y $eq$issuer_ls180.v:108617$4110_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:101" + cell $ne $ne$issuer_ls180.v:108609$4102 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \ra + connect \B 5'00000 + connect \Y $ne$issuer_ls180.v:108609$4102_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:101" + cell $ne $ne$issuer_ls180.v:108618$4111 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \ra + connect \B 5'00000 + connect \Y $ne$issuer_ls180.v:108618$4111_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:116" + cell $not $not$issuer_ls180.v:108614$4107 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \BO [2] + connect \Y $not$issuer_ls180.v:108614$4107_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:123" + cell $not $not$issuer_ls180.v:108615$4108 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \XL_XO [5] + connect \Y $not$issuer_ls180.v:108615$4108_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:101" + cell $or $or$issuer_ls180.v:108605$4098 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$1 + connect \B \$7 + connect \Y $or$issuer_ls180.v:108605$4098_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:101" + cell $or $or$issuer_ls180.v:108612$4105 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$13 + connect \B \$19 + connect \Y $or$issuer_ls180.v:108612$4105_Y + end + attribute \module_not_derived 1 + attribute \src "issuer_ls180.v:108620.10-108626.4" + cell \sprmap \sprmap + connect \fast_o \sprmap_fast_o + connect \fast_o_ok \sprmap_fast_o_ok + connect \spr_i \sprmap_spr_i + connect \spr_o \sprmap_spr_o + connect \spr_o_ok \sprmap_spr_o_ok + end + attribute \src "issuer_ls180.v:108226.7-108226.20" + process $proc$issuer_ls180.v:108226$4119 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "issuer_ls180.v:108627.3-108642.6" + process $proc$issuer_ls180.v:108627$4113 + assign { } { } + assign { } { } + assign { } { } + assign $0\reg_a[4:0] $2\reg_a[4:0] + attribute \src "issuer_ls180.v:108628.5-108628.29" + switch \initial + attribute \src "issuer_ls180.v:108628.9-108628.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:101" + switch \$9 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\reg_a[4:0] \ra + case + assign $1\reg_a[4:0] 5'00000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:106" + switch \$11 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\reg_a[4:0] \RS + case + assign $2\reg_a[4:0] $1\reg_a[4:0] + end + sync always + update \reg_a $0\reg_a[4:0] + end + attribute \src "issuer_ls180.v:108643.3-108658.6" + process $proc$issuer_ls180.v:108643$4114 + assign { } { } + assign { } { } + assign { } { } + assign $0\reg_a_ok[0:0] $2\reg_a_ok[0:0] + attribute \src "issuer_ls180.v:108644.5-108644.29" + switch \initial + attribute \src "issuer_ls180.v:108644.9-108644.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:101" + switch \$21 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\reg_a_ok[0:0] 1'1 + case + assign $1\reg_a_ok[0:0] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:106" + switch \$23 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\reg_a_ok[0:0] 1'1 + case + assign $2\reg_a_ok[0:0] $1\reg_a_ok[0:0] + end + sync always + update \reg_a_ok $0\reg_a_ok[0:0] + end + attribute \src "issuer_ls180.v:108659.3-108694.6" + process $proc$issuer_ls180.v:108659$4115 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\fast_a[2:0] $1\fast_a[2:0] + assign $0\fast_a_ok[0:0] $1\fast_a_ok[0:0] + attribute \src "issuer_ls180.v:108660.5-108660.29" + switch \initial + attribute \src "issuer_ls180.v:108660.9-108660.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:112" + switch \internal_op + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'0000111 + assign { } { } + assign { } { } + assign $1\fast_a[2:0] $2\fast_a[2:0] + assign $1\fast_a_ok[0:0] $2\fast_a_ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:116" + switch \$25 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign $2\fast_a[2:0] 3'000 + assign $2\fast_a_ok[0:0] 1'1 + case + assign $2\fast_a[2:0] 3'000 + assign $2\fast_a_ok[0:0] 1'0 + end + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'0001000 + assign { } { } + assign { } { } + assign $1\fast_a[2:0] $3\fast_a[2:0] + assign $1\fast_a_ok[0:0] $3\fast_a_ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:123" + switch \$29 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign $3\fast_a[2:0] 3'000 + assign $3\fast_a_ok[0:0] 1'1 + case + assign $3\fast_a[2:0] 3'000 + assign $3\fast_a_ok[0:0] 1'0 + end + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'0101110 + assign { } { } + assign { } { } + assign { $1\fast_a_ok[0:0] $1\fast_a[2:0] } { \sprmap_fast_o_ok \sprmap_fast_o } + case + assign $1\fast_a[2:0] 3'000 + assign $1\fast_a_ok[0:0] 1'0 + end + sync always + update \fast_a $0\fast_a[2:0] + update \fast_a_ok $0\fast_a_ok[0:0] + end + attribute \src "issuer_ls180.v:108695.3-108705.6" + process $proc$issuer_ls180.v:108695$4116 + assign { } { } + assign { } { } + assign $0\spr[9:0] $1\spr[9:0] + attribute \src "issuer_ls180.v:108696.5-108696.29" + switch \initial + attribute \src "issuer_ls180.v:108696.9-108696.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:112" + switch \internal_op + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'0101110 + assign { } { } + assign $1\spr[9:0] { \SPR [4:0] \SPR [9:5] } + case + assign $1\spr[9:0] 10'0000000000 + end + sync always + update \spr $0\spr[9:0] + end + attribute \src "issuer_ls180.v:108706.3-108716.6" + process $proc$issuer_ls180.v:108706$4117 + assign { } { } + assign { } { } + assign $0\sprmap_spr_i[9:0] $1\sprmap_spr_i[9:0] + attribute \src "issuer_ls180.v:108707.5-108707.29" + switch \initial + attribute \src "issuer_ls180.v:108707.9-108707.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:112" + switch \internal_op + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'0101110 + assign { } { } + assign $1\sprmap_spr_i[9:0] \spr + case + assign $1\sprmap_spr_i[9:0] 10'0000000000 + end + sync always + update \sprmap_spr_i $0\sprmap_spr_i[9:0] + end + attribute \src "issuer_ls180.v:108717.3-108728.6" + process $proc$issuer_ls180.v:108717$4118 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\spr_a[9:0] $1\spr_a[9:0] + assign $0\spr_a_ok[0:0] $1\spr_a_ok[0:0] + attribute \src "issuer_ls180.v:108718.5-108718.29" + switch \initial + attribute \src "issuer_ls180.v:108718.9-108718.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:112" + switch \internal_op + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'0101110 + assign { } { } + assign { } { } + assign { $1\spr_a_ok[0:0] $1\spr_a[9:0] } { \sprmap_spr_o_ok \sprmap_spr_o } + case + assign $1\spr_a[9:0] 10'0000000000 + assign $1\spr_a_ok[0:0] 1'0 + end + sync always + update \spr_a $0\spr_a[9:0] + update \spr_a_ok $0\spr_a_ok[0:0] + end + connect \$9 $or$issuer_ls180.v:108605$4098_Y + connect \$11 $eq$issuer_ls180.v:108606$4099_Y + connect \$13 $eq$issuer_ls180.v:108607$4100_Y + connect \$15 $eq$issuer_ls180.v:108608$4101_Y + connect \$17 $ne$issuer_ls180.v:108609$4102_Y + connect \$1 $eq$issuer_ls180.v:108610$4103_Y + connect \$19 $and$issuer_ls180.v:108611$4104_Y + connect \$21 $or$issuer_ls180.v:108612$4105_Y + connect \$23 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"issuer_ls180.v:108758.17-108758.108" + wire $eq$issuer_ls180.v:108758$4121_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:158" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:158" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:158" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 input 2 \ALU_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:149" + wire output 1 \immz_out + attribute \src "issuer_ls180.v:108735.7-108735.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:156" + wire width 5 \ra + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:148" + wire width 3 input 3 \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:158" + cell $and $and$issuer_ls180.v:108759$4122 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$1 + connect \B \$3 + connect \Y $and$issuer_ls180.v:108759$4122_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:158" + cell $eq $eq$issuer_ls180.v:108757$4120 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \sel_in + connect \B 3'010 + connect \Y $eq$issuer_ls180.v:108757$4120_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:158" + cell $eq $eq$issuer_ls180.v:108758$4121 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \ra + connect \B 5'00000 + connect \Y $eq$issuer_ls180.v:108758$4121_Y + end + attribute \src "issuer_ls180.v:108735.7-108735.20" + process $proc$issuer_ls180.v:108735$4124 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "issuer_ls180.v:108760.3-108769.6" + process $proc$issuer_ls180.v:108760$4123 + assign { } { } + assign { } { } + assign $0\immz_out[0:0] $1\immz_out[0:0] + attribute \src "issuer_ls180.v:108761.5-108761.29" + switch \initial + attribute \src "issuer_ls180.v:108761.9-108761.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:158" + switch \$5 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\immz_out[0:0] 1'1 + case + assign $1\immz_out[0:0] 1'0 + end + sync always + update \immz_out $0\immz_out[0:0] + end + connect \$1 $eq$issuer_ls180.v:108757$4120_Y + connect \$3 $eq$issuer_ls180.v:108758$4121_Y + connect \$5 $and$issuer_ls180.v:108759$4122_Y + connect \ra \ALU_RA +end +attribute \src "issuer_ls180.v:108775.1-108812.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.dec_LOGICAL.dec_ai" +attribute \generator "nMigen" +module \dec_ai$159 + attribute \src "issuer_ls180.v:108801.3-108810.6" + wire $0\immz_out[0:0] + attribute \src "issuer_ls180.v:108776.7-108776.20" + wire $0\initial[0:0] + attribute \src "issuer_ls180.v:108801.3-108810.6" + wire $1\immz_out[0:0] + attribute \src "issuer_ls180.v:108800.17-108800.107" + wire $and$issuer_ls180.v:108800$4127_Y + attribute \src "issuer_ls180.v:108798.17-108798.111" + wire $eq$issuer_ls180.v:108798$4125_Y + attribute \src "issuer_ls180.v:108799.17-108799.108" + wire $eq$issuer_ls180.v:108799$4126_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:158" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:158" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:158" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 input 2 \LOGICAL_RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:149" + wire output 1 \immz_out + attribute \src "issuer_ls180.v:108776.7-108776.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:156" + wire width 5 \ra + attribute \enum_base_type "In1Sel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "RA" + attribute \enum_value_010 "RA_OR_ZERO" + attribute \enum_value_011 "SPR" + attribute \enum_value_100 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:148" + wire width 3 input 3 \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:158" + cell $and $and$issuer_ls180.v:108800$4127 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$1 + connect \B \$3 + connect \Y $and$issuer_ls180.v:108800$4127_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:158" + cell $eq $eq$issuer_ls180.v:108798$4125 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \sel_in + connect \B 3'010 + connect \Y $eq$issuer_ls180.v:108798$4125_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:158" + cell $eq $eq$issuer_ls180.v:108799$4126 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \ra + connect \B 5'00000 + connect \Y $eq$issuer_ls180.v:108799$4126_Y + end + attribute \src "issuer_ls180.v:108776.7-108776.20" + process $proc$issuer_ls180.v:108776$4129 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "issuer_ls180.v:108801.3-108810.6" + process $proc$issuer_ls180.v:108801$4128 + assign { } { } + assign { } { } + assign $0\immz_out[0:0] $1\immz_out[0:0] + attribute \src "issuer_ls180.v:108802.5-108802.29" + switch \initial + attribute \src "issuer_ls180.v:108802.9-108802.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:158" + switch \$5 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\immz_out[0:0] 1'1 + case + assign $1\immz_out[0:0] 1'0 + end + sync always + update \immz_out $0\immz_out[0:0] + end + connect \$1 $eq$issuer_ls180.v:108798$4125_Y + connect \$3 $eq$issuer_ls180.v:108799$4126_Y + connect \$5 $and$issuer_ls180.v:108800$4127_Y + connect \ra \LOGICAL_RA +end +attribute \src "issuer_ls180.v:108816.1-108853.10" +attribute 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\Y $and$issuer_ls180.v:108841$4132_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:158" + cell $eq $eq$issuer_ls180.v:108839$4130 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \sel_in + connect \B 3'010 + connect \Y $eq$issuer_ls180.v:108839$4130_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:158" + cell $eq $eq$issuer_ls180.v:108840$4131 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \ra + connect \B 5'00000 + connect \Y $eq$issuer_ls180.v:108840$4131_Y + end + attribute \src "issuer_ls180.v:108817.7-108817.20" + process $proc$issuer_ls180.v:108817$4134 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "issuer_ls180.v:108842.3-108851.6" + process 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"OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 7 input 9 \internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 5 output 2 \reg_b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 3 \reg_b_ok + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" 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wire width 27 $sshl$issuer_ls180.v:109175$4154_Y + attribute \src "issuer_ls180.v:109177.18-109177.113" + wire width 17 $sshl$issuer_ls180.v:109177$4157_Y + attribute \src "issuer_ls180.v:109178.18-109178.113" + wire width 17 $sshl$issuer_ls180.v:109178$4158_Y + attribute \src "issuer_ls180.v:109179.17-109179.109" + wire width 47 $sshl$issuer_ls180.v:109179$4159_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 64 \$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 64 \$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:235" + wire width 47 \$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:235" + wire width 47 \$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:245" + wire width 27 \$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:245" + wire width 27 \$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:250" + wire width 17 \$19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:250" + wire width 17 \$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:255" + wire width 17 \$22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:255" + wire width 17 \$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:241" + wire width 64 \$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:241" + wire width 47 \$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:259" + wire width 64 \$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 64 \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 14 input 8 \ALU_BD + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 14 input 9 \ALU_DS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 24 input 7 \ALU_LI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 input 5 \ALU_SH32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 16 input 3 \ALU_SI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 16 input 4 \ALU_UI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 6 input 6 \ALU_sh + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:249" + wire width 16 \bd + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:254" + wire width 16 \ds + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 output 1 \imm_b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 2 \imm_b_ok + attribute \src "issuer_ls180.v:109094.7-109094.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" + wire width 26 \li + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:216" + wire width 4 input 10 \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:229" + wire width 16 \si + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:234" + wire width 32 \si_hi + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:239" + wire width 16 \ui + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + cell $pos $extend$issuer_ls180.v:109172$4149 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \Y_WIDTH 64 + connect \A \ALU_sh + connect \Y $extend$issuer_ls180.v:109172$4149_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + cell $pos $extend$issuer_ls180.v:109173$4151 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \Y_WIDTH 64 + connect \A \ALU_SH32 + connect \Y $extend$issuer_ls180.v:109173$4151_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + cell $pos $extend$issuer_ls180.v:109176$4155 + parameter \A_SIGNED 0 + parameter \A_WIDTH 16 + parameter \Y_WIDTH 64 + connect \A \ALU_UI + connect \Y $extend$issuer_ls180.v:109176$4155_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:241" + cell $pos $extend$issuer_ls180.v:109180$4160 + parameter \A_SIGNED 0 + parameter \A_WIDTH 47 + parameter \Y_WIDTH 64 + connect \A \$4 + connect \Y $extend$issuer_ls180.v:109180$4160_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + cell $pos $pos$issuer_ls180.v:109172$4150 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A $extend$issuer_ls180.v:109172$4149_Y + connect \Y $pos$issuer_ls180.v:109172$4150_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + cell $pos $pos$issuer_ls180.v:109173$4152 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A $extend$issuer_ls180.v:109173$4151_Y + connect \Y $pos$issuer_ls180.v:109173$4152_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + cell $pos $pos$issuer_ls180.v:109176$4156 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A $extend$issuer_ls180.v:109176$4155_Y + connect \Y $pos$issuer_ls180.v:109176$4156_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:241" + cell $pos $pos$issuer_ls180.v:109180$4161 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A $extend$issuer_ls180.v:109180$4160_Y + connect \Y $pos$issuer_ls180.v:109180$4161_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:235" + cell $sshl $sshl$issuer_ls180.v:109174$4153 + parameter \A_SIGNED 0 + parameter \A_WIDTH 16 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 47 + connect \A \ALU_SI + connect \B 5'10000 + connect \Y $sshl$issuer_ls180.v:109174$4153_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:245" + cell $sshl $sshl$issuer_ls180.v:109175$4154 + parameter \A_SIGNED 0 + parameter \A_WIDTH 24 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 27 + connect \A \ALU_LI + connect \B 2'10 + connect \Y $sshl$issuer_ls180.v:109175$4154_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:250" + cell $sshl $sshl$issuer_ls180.v:109177$4157 + parameter \A_SIGNED 0 + parameter \A_WIDTH 14 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 17 + connect \A \ALU_BD + connect \B 2'10 + connect \Y $sshl$issuer_ls180.v:109177$4157_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:255" + cell $sshl $sshl$issuer_ls180.v:109178$4158 + parameter \A_SIGNED 0 + parameter \A_WIDTH 14 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 17 + connect \A \ALU_DS + connect \B 2'10 + connect \Y $sshl$issuer_ls180.v:109178$4158_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:241" + cell $sshl $sshl$issuer_ls180.v:109179$4159 + parameter \A_SIGNED 0 + parameter \A_WIDTH 16 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 47 + connect \A \ui + connect \B 5'10000 + connect \Y $sshl$issuer_ls180.v:109179$4159_Y + end + attribute \src "issuer_ls180.v:109094.7-109094.20" + process $proc$issuer_ls180.v:109094$4170 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "issuer_ls180.v:109182.3-109228.6" + process $proc$issuer_ls180.v:109182$4162 + assign { } { } + assign { } { } + assign $0\imm_b[63:0] $1\imm_b[63:0] + attribute \src "issuer_ls180.v:109183.5-109183.29" + switch \initial + attribute \src "issuer_ls180.v:109183.9-109183.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:224" + switch \sel_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0010 + assign { } { } + assign $1\imm_b[63:0] \$1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0011 + assign { } { } + assign $1\imm_b[63:0] { \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si } + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0101 + assign { } { } + assign $1\imm_b[63:0] { \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi } + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0100 + assign { } { } + assign $1\imm_b[63:0] \$3 + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\imm_b[63:0] { \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li } + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $1\imm_b[63:0] { \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd } + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\imm_b[63:0] { \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds } + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'1001 + assign { } { } + assign $1\imm_b[63:0] \$7 + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'1010 + assign { } { } + assign $1\imm_b[63:0] \$9 + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'1011 + assign { } { } + assign $1\imm_b[63:0] \$11 + case + assign $1\imm_b[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \imm_b $0\imm_b[63:0] + end + attribute \src "issuer_ls180.v:109229.3-109275.6" + process $proc$issuer_ls180.v:109229$4163 + assign { } { } + assign { } { } + assign $0\imm_b_ok[0:0] $1\imm_b_ok[0:0] + attribute \src "issuer_ls180.v:109230.5-109230.29" + switch \initial + attribute \src "issuer_ls180.v:109230.9-109230.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:224" + switch \sel_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0010 + assign { } { } + assign $1\imm_b_ok[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0011 + assign { } { } + assign $1\imm_b_ok[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0101 + assign { } { } + assign $1\imm_b_ok[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0100 + assign { } { } + assign $1\imm_b_ok[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\imm_b_ok[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $1\imm_b_ok[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\imm_b_ok[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'1001 + assign { } { } + assign $1\imm_b_ok[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'1010 + assign { } { } + assign $1\imm_b_ok[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'1011 + assign { } { } + assign $1\imm_b_ok[0:0] 1'1 + case + assign $1\imm_b_ok[0:0] 1'0 + end + sync always + update \imm_b_ok $0\imm_b_ok[0:0] + end + attribute \src "issuer_ls180.v:109276.3-109286.6" + process $proc$issuer_ls180.v:109276$4164 + assign { } { } + assign { } { } + assign $0\si[15:0] $1\si[15:0] + attribute \src "issuer_ls180.v:109277.5-109277.29" + switch \initial + attribute \src "issuer_ls180.v:109277.9-109277.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:224" + switch \sel_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0011 + assign { } { } + assign $1\si[15:0] \ALU_SI + case + assign $1\si[15:0] 16'0000000000000000 + end + sync always + update \si $0\si[15:0] + end + attribute \src "issuer_ls180.v:109287.3-109297.6" + process $proc$issuer_ls180.v:109287$4165 + assign { } { } + assign { } { } + assign $0\si_hi[31:0] $1\si_hi[31:0] + attribute \src "issuer_ls180.v:109288.5-109288.29" + switch \initial + attribute \src "issuer_ls180.v:109288.9-109288.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:224" + switch \sel_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0101 + assign { } { } + assign $1\si_hi[31:0] \$13 [31:0] + case + assign $1\si_hi[31:0] 0 + end + sync always + update \si_hi $0\si_hi[31:0] + end + attribute \src "issuer_ls180.v:109298.3-109308.6" + process $proc$issuer_ls180.v:109298$4166 + assign { } { } + assign { } { } + assign $0\ui[15:0] $1\ui[15:0] + attribute \src "issuer_ls180.v:109299.5-109299.29" + switch \initial + attribute \src "issuer_ls180.v:109299.9-109299.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:224" + switch \sel_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0100 + assign { } { } + assign $1\ui[15:0] \ALU_UI + case + assign $1\ui[15:0] 16'0000000000000000 + end + sync always + update \ui $0\ui[15:0] + end + attribute \src "issuer_ls180.v:109309.3-109319.6" + process $proc$issuer_ls180.v:109309$4167 + assign { } { } + assign { } { } + assign $0\li[25:0] $1\li[25:0] + attribute \src "issuer_ls180.v:109310.5-109310.29" + switch \initial + attribute \src "issuer_ls180.v:109310.9-109310.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:224" + switch \sel_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\li[25:0] \$16 [25:0] + case + assign $1\li[25:0] 26'00000000000000000000000000 + end + sync always + update \li $0\li[25:0] + end + attribute \src "issuer_ls180.v:109320.3-109330.6" + process $proc$issuer_ls180.v:109320$4168 + assign { } { } + assign { } { } + assign $0\bd[15:0] $1\bd[15:0] + attribute \src "issuer_ls180.v:109321.5-109321.29" + switch \initial + attribute \src "issuer_ls180.v:109321.9-109321.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:224" + switch \sel_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $1\bd[15:0] \$19 [15:0] + case + assign $1\bd[15:0] 16'0000000000000000 + end + sync always + update \bd $0\bd[15:0] + end + attribute \src "issuer_ls180.v:109331.3-109341.6" + process $proc$issuer_ls180.v:109331$4169 + assign { } { } + assign { } { } + assign $0\ds[15:0] $1\ds[15:0] + attribute \src "issuer_ls180.v:109332.5-109332.29" + switch \initial + attribute \src "issuer_ls180.v:109332.9-109332.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:224" + switch \sel_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\ds[15:0] \$22 [15:0] + case + assign $1\ds[15:0] 16'0000000000000000 + end + sync always + update \ds $0\ds[15:0] + end + connect \$9 $pos$issuer_ls180.v:109172$4150_Y + connect \$11 $pos$issuer_ls180.v:109173$4152_Y + connect \$14 $sshl$issuer_ls180.v:109174$4153_Y + connect \$17 $sshl$issuer_ls180.v:109175$4154_Y + connect \$1 $pos$issuer_ls180.v:109176$4156_Y + connect \$20 $sshl$issuer_ls180.v:109177$4157_Y + connect \$23 $sshl$issuer_ls180.v:109178$4158_Y + connect \$4 $sshl$issuer_ls180.v:109179$4159_Y + connect \$3 $pos$issuer_ls180.v:109180$4161_Y + connect \$7 64'1111111111111111111111111111111111111111111111111111111111111111 + connect \$13 \$14 + connect \$16 \$17 + connect \$19 \$20 + connect \$22 \$23 +end +attribute \src "issuer_ls180.v:109350.1-109603.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.dec_BRANCH.dec_bi" +attribute \generator "nMigen" +module \dec_bi$151 + attribute \src "issuer_ls180.v:109577.3-109587.6" + wire width 16 $0\bd[15:0] + attribute \src "issuer_ls180.v:109588.3-109598.6" + wire width 16 $0\ds[15:0] + attribute \src "issuer_ls180.v:109439.3-109485.6" + wire width 64 $0\imm_b[63:0] + attribute \src "issuer_ls180.v:109486.3-109532.6" + wire $0\imm_b_ok[0:0] + attribute \src "issuer_ls180.v:109351.7-109351.20" + wire $0\initial[0:0] + attribute \src "issuer_ls180.v:109566.3-109576.6" + wire width 26 $0\li[25:0] + attribute \src "issuer_ls180.v:109533.3-109543.6" + wire width 16 $0\si[15:0] + attribute \src "issuer_ls180.v:109544.3-109554.6" + wire width 32 $0\si_hi[31:0] + attribute \src "issuer_ls180.v:109555.3-109565.6" + wire width 16 $0\ui[15:0] + attribute \src "issuer_ls180.v:109577.3-109587.6" + wire width 16 $1\bd[15:0] + attribute \src "issuer_ls180.v:109588.3-109598.6" + wire width 16 $1\ds[15:0] + attribute \src "issuer_ls180.v:109439.3-109485.6" + wire width 64 $1\imm_b[63:0] + attribute \src "issuer_ls180.v:109486.3-109532.6" + wire $1\imm_b_ok[0:0] + attribute \src "issuer_ls180.v:109566.3-109576.6" + wire width 26 $1\li[25:0] + attribute \src "issuer_ls180.v:109533.3-109543.6" + wire width 16 $1\si[15:0] + attribute \src "issuer_ls180.v:109544.3-109554.6" + wire width 32 $1\si_hi[31:0] + attribute \src "issuer_ls180.v:109555.3-109565.6" + wire width 16 $1\ui[15:0] + attribute \src "issuer_ls180.v:109429.17-109429.107" + wire width 64 $extend$issuer_ls180.v:109429$4171_Y + attribute \src "issuer_ls180.v:109430.18-109430.110" + wire width 64 $extend$issuer_ls180.v:109430$4173_Y + attribute \src "issuer_ls180.v:109433.17-109433.107" + wire width 64 $extend$issuer_ls180.v:109433$4177_Y + attribute \src "issuer_ls180.v:109437.17-109437.102" + wire width 64 $extend$issuer_ls180.v:109437$4182_Y + attribute \src "issuer_ls180.v:109429.17-109429.107" + wire width 64 $pos$issuer_ls180.v:109429$4172_Y + attribute \src "issuer_ls180.v:109430.18-109430.110" + wire width 64 $pos$issuer_ls180.v:109430$4174_Y + attribute \src "issuer_ls180.v:109433.17-109433.107" + wire width 64 $pos$issuer_ls180.v:109433$4178_Y + attribute \src "issuer_ls180.v:109437.17-109437.102" + wire width 64 $pos$issuer_ls180.v:109437$4183_Y + attribute \src "issuer_ls180.v:109431.18-109431.117" + wire width 47 $sshl$issuer_ls180.v:109431$4175_Y + attribute \src "issuer_ls180.v:109432.18-109432.116" + wire width 27 $sshl$issuer_ls180.v:109432$4176_Y + attribute \src "issuer_ls180.v:109434.18-109434.116" + wire width 17 $sshl$issuer_ls180.v:109434$4179_Y + attribute \src "issuer_ls180.v:109435.18-109435.116" + wire width 17 $sshl$issuer_ls180.v:109435$4180_Y + attribute \src "issuer_ls180.v:109436.17-109436.109" + wire width 47 $sshl$issuer_ls180.v:109436$4181_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 64 \$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 64 \$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:235" + wire width 47 \$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:235" + wire width 47 \$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:245" + wire width 27 \$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:245" + wire width 27 \$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:250" + wire width 17 \$19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:250" + wire width 17 \$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:255" + wire width 17 \$22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:255" + wire width 17 \$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:241" + wire width 64 \$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:241" + wire width 47 \$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:259" + wire width 64 \$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 64 \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 14 input 8 \BRANCH_BD + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 14 input 9 \BRANCH_DS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 24 input 7 \BRANCH_LI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 input 5 \BRANCH_SH32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 16 input 3 \BRANCH_SI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 16 input 4 \BRANCH_UI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 6 input 6 \BRANCH_sh + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:249" + wire width 16 \bd + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:254" + wire width 16 \ds + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 output 1 \imm_b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 2 \imm_b_ok + attribute \src "issuer_ls180.v:109351.7-109351.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" + wire width 26 \li + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:216" + wire width 4 input 10 \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:229" + wire width 16 \si + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:234" + wire width 32 \si_hi + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:239" + wire width 16 \ui + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + cell $pos $extend$issuer_ls180.v:109429$4171 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \Y_WIDTH 64 + connect \A \BRANCH_sh + connect \Y $extend$issuer_ls180.v:109429$4171_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + cell $pos $extend$issuer_ls180.v:109430$4173 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \Y_WIDTH 64 + connect \A \BRANCH_SH32 + connect \Y $extend$issuer_ls180.v:109430$4173_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + cell $pos $extend$issuer_ls180.v:109433$4177 + parameter \A_SIGNED 0 + parameter \A_WIDTH 16 + parameter \Y_WIDTH 64 + connect \A \BRANCH_UI + connect \Y $extend$issuer_ls180.v:109433$4177_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:241" + cell $pos $extend$issuer_ls180.v:109437$4182 + parameter \A_SIGNED 0 + parameter \A_WIDTH 47 + parameter \Y_WIDTH 64 + connect \A \$4 + connect \Y $extend$issuer_ls180.v:109437$4182_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + cell $pos $pos$issuer_ls180.v:109429$4172 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A $extend$issuer_ls180.v:109429$4171_Y + connect \Y $pos$issuer_ls180.v:109429$4172_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + cell $pos $pos$issuer_ls180.v:109430$4174 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A $extend$issuer_ls180.v:109430$4173_Y + connect \Y $pos$issuer_ls180.v:109430$4174_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + cell $pos $pos$issuer_ls180.v:109433$4178 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A $extend$issuer_ls180.v:109433$4177_Y + connect \Y $pos$issuer_ls180.v:109433$4178_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:241" + cell $pos $pos$issuer_ls180.v:109437$4183 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A $extend$issuer_ls180.v:109437$4182_Y + connect \Y $pos$issuer_ls180.v:109437$4183_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:235" + cell $sshl $sshl$issuer_ls180.v:109431$4175 + parameter \A_SIGNED 0 + parameter \A_WIDTH 16 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 47 + connect \A \BRANCH_SI + connect \B 5'10000 + connect \Y $sshl$issuer_ls180.v:109431$4175_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:245" + cell $sshl $sshl$issuer_ls180.v:109432$4176 + parameter \A_SIGNED 0 + parameter \A_WIDTH 24 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 27 + connect \A \BRANCH_LI + connect \B 2'10 + connect \Y $sshl$issuer_ls180.v:109432$4176_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:250" + cell $sshl $sshl$issuer_ls180.v:109434$4179 + parameter \A_SIGNED 0 + parameter \A_WIDTH 14 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 17 + connect \A \BRANCH_BD + connect \B 2'10 + connect \Y $sshl$issuer_ls180.v:109434$4179_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:255" + cell $sshl $sshl$issuer_ls180.v:109435$4180 + parameter \A_SIGNED 0 + parameter \A_WIDTH 14 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 17 + connect \A \BRANCH_DS + connect \B 2'10 + connect \Y $sshl$issuer_ls180.v:109435$4180_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:241" + cell $sshl $sshl$issuer_ls180.v:109436$4181 + parameter \A_SIGNED 0 + parameter \A_WIDTH 16 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 47 + connect \A \ui + connect \B 5'10000 + connect \Y $sshl$issuer_ls180.v:109436$4181_Y + end + attribute \src "issuer_ls180.v:109351.7-109351.20" + process $proc$issuer_ls180.v:109351$4192 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "issuer_ls180.v:109439.3-109485.6" + process $proc$issuer_ls180.v:109439$4184 + assign { } { } + assign { } { } + assign $0\imm_b[63:0] $1\imm_b[63:0] + attribute \src "issuer_ls180.v:109440.5-109440.29" + switch \initial + attribute \src "issuer_ls180.v:109440.9-109440.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:224" + switch \sel_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0010 + assign { } { } + assign $1\imm_b[63:0] \$1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0011 + assign { } { } + assign $1\imm_b[63:0] { \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si } + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0101 + assign { } { } + assign $1\imm_b[63:0] { \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi } + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0100 + assign { } { } + assign $1\imm_b[63:0] \$3 + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\imm_b[63:0] { \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li } + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $1\imm_b[63:0] { \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd } + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\imm_b[63:0] { \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds } + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'1001 + assign { } { } + assign $1\imm_b[63:0] \$7 + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'1010 + assign { } { } + assign $1\imm_b[63:0] \$9 + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'1011 + assign { } { } + assign $1\imm_b[63:0] \$11 + case + assign $1\imm_b[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \imm_b $0\imm_b[63:0] + end + attribute \src "issuer_ls180.v:109486.3-109532.6" + process $proc$issuer_ls180.v:109486$4185 + assign { } { } + assign { } { } + assign $0\imm_b_ok[0:0] $1\imm_b_ok[0:0] + attribute \src "issuer_ls180.v:109487.5-109487.29" + switch \initial + attribute \src "issuer_ls180.v:109487.9-109487.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:224" + switch \sel_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0010 + assign { } { } + assign $1\imm_b_ok[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0011 + assign { } { } + assign $1\imm_b_ok[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0101 + assign { } { } + assign $1\imm_b_ok[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0100 + assign { } { } + assign $1\imm_b_ok[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\imm_b_ok[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $1\imm_b_ok[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\imm_b_ok[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'1001 + assign { } { } + assign $1\imm_b_ok[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'1010 + assign { } { } + assign $1\imm_b_ok[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'1011 + assign { } { } + assign $1\imm_b_ok[0:0] 1'1 + case + assign $1\imm_b_ok[0:0] 1'0 + end + sync always + update \imm_b_ok $0\imm_b_ok[0:0] + end + attribute \src "issuer_ls180.v:109533.3-109543.6" + process $proc$issuer_ls180.v:109533$4186 + assign { } { } + assign { } { } + assign $0\si[15:0] $1\si[15:0] + attribute \src "issuer_ls180.v:109534.5-109534.29" + switch \initial + attribute \src "issuer_ls180.v:109534.9-109534.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:224" + switch \sel_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0011 + assign { } { } + assign $1\si[15:0] \BRANCH_SI + case + assign $1\si[15:0] 16'0000000000000000 + end + sync always + update \si $0\si[15:0] + end + attribute \src "issuer_ls180.v:109544.3-109554.6" + process $proc$issuer_ls180.v:109544$4187 + assign { } { } + assign { } { } + assign $0\si_hi[31:0] $1\si_hi[31:0] + attribute \src "issuer_ls180.v:109545.5-109545.29" + switch \initial + attribute \src "issuer_ls180.v:109545.9-109545.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:224" + switch \sel_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0101 + assign { } { } + assign $1\si_hi[31:0] \$13 [31:0] + case + assign $1\si_hi[31:0] 0 + end + sync always + update \si_hi $0\si_hi[31:0] + end + attribute \src "issuer_ls180.v:109555.3-109565.6" + process $proc$issuer_ls180.v:109555$4188 + assign { } { } + assign { } { } + assign $0\ui[15:0] $1\ui[15:0] + attribute \src "issuer_ls180.v:109556.5-109556.29" + switch \initial + attribute \src "issuer_ls180.v:109556.9-109556.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:224" + switch \sel_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0100 + assign { } { } + assign $1\ui[15:0] \BRANCH_UI + case + assign $1\ui[15:0] 16'0000000000000000 + end + sync always + update \ui $0\ui[15:0] + end + attribute \src "issuer_ls180.v:109566.3-109576.6" + process $proc$issuer_ls180.v:109566$4189 + assign { } { } + assign { } { } + assign $0\li[25:0] $1\li[25:0] + attribute \src "issuer_ls180.v:109567.5-109567.29" + switch \initial + attribute \src "issuer_ls180.v:109567.9-109567.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:224" + switch \sel_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\li[25:0] \$16 [25:0] + case + assign $1\li[25:0] 26'00000000000000000000000000 + end + sync always + update \li $0\li[25:0] + end + attribute \src "issuer_ls180.v:109577.3-109587.6" + process $proc$issuer_ls180.v:109577$4190 + assign { } { } + assign { } { } + assign $0\bd[15:0] $1\bd[15:0] + attribute \src "issuer_ls180.v:109578.5-109578.29" + switch \initial + attribute \src "issuer_ls180.v:109578.9-109578.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:224" + switch \sel_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $1\bd[15:0] \$19 [15:0] + case + assign $1\bd[15:0] 16'0000000000000000 + end + sync always + update \bd $0\bd[15:0] + end + attribute \src "issuer_ls180.v:109588.3-109598.6" + process $proc$issuer_ls180.v:109588$4191 + assign { } { } + assign { } { } + assign $0\ds[15:0] $1\ds[15:0] + attribute \src "issuer_ls180.v:109589.5-109589.29" + switch \initial + attribute \src "issuer_ls180.v:109589.9-109589.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:224" + switch \sel_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\ds[15:0] \$22 [15:0] + case + assign $1\ds[15:0] 16'0000000000000000 + end + sync always + update \ds $0\ds[15:0] + end + connect \$9 $pos$issuer_ls180.v:109429$4172_Y + connect \$11 $pos$issuer_ls180.v:109430$4174_Y + connect \$14 $sshl$issuer_ls180.v:109431$4175_Y + connect \$17 $sshl$issuer_ls180.v:109432$4176_Y + connect \$1 $pos$issuer_ls180.v:109433$4178_Y + connect \$20 $sshl$issuer_ls180.v:109434$4179_Y + connect \$23 $sshl$issuer_ls180.v:109435$4180_Y + connect \$4 $sshl$issuer_ls180.v:109436$4181_Y + connect \$3 $pos$issuer_ls180.v:109437$4183_Y + connect \$7 64'1111111111111111111111111111111111111111111111111111111111111111 + connect \$13 \$14 + connect \$16 \$17 + connect \$19 \$20 + connect \$22 \$23 +end +attribute \src "issuer_ls180.v:109607.1-109860.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.dec_LOGICAL.dec_bi" +attribute \generator "nMigen" +module \dec_bi$160 + attribute \src "issuer_ls180.v:109834.3-109844.6" + wire width 16 $0\bd[15:0] + attribute \src "issuer_ls180.v:109845.3-109855.6" + wire width 16 $0\ds[15:0] + attribute \src "issuer_ls180.v:109696.3-109742.6" + wire width 64 $0\imm_b[63:0] + attribute \src "issuer_ls180.v:109743.3-109789.6" + wire $0\imm_b_ok[0:0] + attribute \src "issuer_ls180.v:109608.7-109608.20" + wire $0\initial[0:0] + attribute \src "issuer_ls180.v:109823.3-109833.6" + wire width 26 $0\li[25:0] + attribute \src "issuer_ls180.v:109790.3-109800.6" + wire width 16 $0\si[15:0] + attribute \src "issuer_ls180.v:109801.3-109811.6" + wire width 32 $0\si_hi[31:0] + attribute \src "issuer_ls180.v:109812.3-109822.6" + wire width 16 $0\ui[15:0] + attribute \src "issuer_ls180.v:109834.3-109844.6" + wire width 16 $1\bd[15:0] + attribute \src "issuer_ls180.v:109845.3-109855.6" + wire width 16 $1\ds[15:0] + attribute \src "issuer_ls180.v:109696.3-109742.6" + wire width 64 $1\imm_b[63:0] + attribute \src "issuer_ls180.v:109743.3-109789.6" + wire $1\imm_b_ok[0:0] + attribute \src "issuer_ls180.v:109823.3-109833.6" + wire width 26 $1\li[25:0] + attribute \src "issuer_ls180.v:109790.3-109800.6" + wire width 16 $1\si[15:0] + attribute \src "issuer_ls180.v:109801.3-109811.6" + wire width 32 $1\si_hi[31:0] + attribute \src "issuer_ls180.v:109812.3-109822.6" + wire width 16 $1\ui[15:0] + attribute \src "issuer_ls180.v:109686.17-109686.108" + wire width 64 $extend$issuer_ls180.v:109686$4193_Y + attribute \src "issuer_ls180.v:109687.18-109687.111" + wire width 64 $extend$issuer_ls180.v:109687$4195_Y + attribute \src "issuer_ls180.v:109690.17-109690.108" + wire width 64 $extend$issuer_ls180.v:109690$4199_Y + attribute \src "issuer_ls180.v:109694.17-109694.102" + wire width 64 $extend$issuer_ls180.v:109694$4204_Y + attribute \src "issuer_ls180.v:109686.17-109686.108" + wire width 64 $pos$issuer_ls180.v:109686$4194_Y + attribute \src "issuer_ls180.v:109687.18-109687.111" + wire width 64 $pos$issuer_ls180.v:109687$4196_Y + attribute \src "issuer_ls180.v:109690.17-109690.108" + wire width 64 $pos$issuer_ls180.v:109690$4200_Y + attribute \src "issuer_ls180.v:109694.17-109694.102" + wire width 64 $pos$issuer_ls180.v:109694$4205_Y + attribute \src "issuer_ls180.v:109688.18-109688.118" + wire width 47 $sshl$issuer_ls180.v:109688$4197_Y + attribute \src "issuer_ls180.v:109689.18-109689.117" + wire width 27 $sshl$issuer_ls180.v:109689$4198_Y + attribute \src "issuer_ls180.v:109691.18-109691.117" + wire width 17 $sshl$issuer_ls180.v:109691$4201_Y + attribute \src "issuer_ls180.v:109692.18-109692.117" + wire width 17 $sshl$issuer_ls180.v:109692$4202_Y + attribute \src "issuer_ls180.v:109693.17-109693.109" + wire width 47 $sshl$issuer_ls180.v:109693$4203_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 64 \$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 64 \$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:235" + wire width 47 \$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:235" + wire width 47 \$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:245" + wire width 27 \$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:245" + wire width 27 \$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:250" + wire width 17 \$19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:250" + wire width 17 \$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:255" + wire width 17 \$22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:255" + wire width 17 \$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:241" + wire width 64 \$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:241" + wire width 47 \$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:259" + wire width 64 \$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 64 \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 14 input 8 \LOGICAL_BD + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 14 input 9 \LOGICAL_DS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 24 input 7 \LOGICAL_LI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 input 5 \LOGICAL_SH32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 16 input 3 \LOGICAL_SI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 16 input 4 \LOGICAL_UI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 6 input 6 \LOGICAL_sh + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:249" + wire width 16 \bd + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:254" + wire width 16 \ds + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 output 1 \imm_b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 2 \imm_b_ok + attribute \src "issuer_ls180.v:109608.7-109608.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" + wire width 26 \li + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:216" + wire width 4 input 10 \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:229" + wire width 16 \si + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:234" + wire width 32 \si_hi + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:239" + wire width 16 \ui + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + cell $pos $extend$issuer_ls180.v:109686$4193 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \Y_WIDTH 64 + connect \A \LOGICAL_sh + connect \Y $extend$issuer_ls180.v:109686$4193_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + cell $pos $extend$issuer_ls180.v:109687$4195 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \Y_WIDTH 64 + connect \A \LOGICAL_SH32 + connect \Y $extend$issuer_ls180.v:109687$4195_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + cell $pos $extend$issuer_ls180.v:109690$4199 + parameter \A_SIGNED 0 + parameter \A_WIDTH 16 + parameter \Y_WIDTH 64 + connect \A \LOGICAL_UI + connect \Y $extend$issuer_ls180.v:109690$4199_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:241" + cell $pos $extend$issuer_ls180.v:109694$4204 + parameter \A_SIGNED 0 + parameter \A_WIDTH 47 + parameter \Y_WIDTH 64 + connect \A \$4 + connect \Y $extend$issuer_ls180.v:109694$4204_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + cell $pos $pos$issuer_ls180.v:109686$4194 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A $extend$issuer_ls180.v:109686$4193_Y + connect \Y $pos$issuer_ls180.v:109686$4194_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + cell $pos $pos$issuer_ls180.v:109687$4196 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A $extend$issuer_ls180.v:109687$4195_Y + connect \Y $pos$issuer_ls180.v:109687$4196_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + cell $pos $pos$issuer_ls180.v:109690$4200 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A $extend$issuer_ls180.v:109690$4199_Y + connect \Y $pos$issuer_ls180.v:109690$4200_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:241" + cell $pos $pos$issuer_ls180.v:109694$4205 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A $extend$issuer_ls180.v:109694$4204_Y + connect \Y $pos$issuer_ls180.v:109694$4205_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:235" + cell $sshl $sshl$issuer_ls180.v:109688$4197 + parameter \A_SIGNED 0 + parameter \A_WIDTH 16 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 47 + connect \A \LOGICAL_SI + connect \B 5'10000 + connect \Y $sshl$issuer_ls180.v:109688$4197_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:245" + cell $sshl $sshl$issuer_ls180.v:109689$4198 + parameter \A_SIGNED 0 + parameter \A_WIDTH 24 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 27 + connect \A \LOGICAL_LI + connect \B 2'10 + connect \Y $sshl$issuer_ls180.v:109689$4198_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:250" + cell $sshl $sshl$issuer_ls180.v:109691$4201 + parameter \A_SIGNED 0 + parameter \A_WIDTH 14 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 17 + connect \A \LOGICAL_BD + connect \B 2'10 + connect \Y $sshl$issuer_ls180.v:109691$4201_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:255" + cell $sshl $sshl$issuer_ls180.v:109692$4202 + parameter \A_SIGNED 0 + parameter \A_WIDTH 14 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 17 + connect \A \LOGICAL_DS + connect \B 2'10 + connect \Y $sshl$issuer_ls180.v:109692$4202_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:241" + cell $sshl $sshl$issuer_ls180.v:109693$4203 + parameter \A_SIGNED 0 + parameter \A_WIDTH 16 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 47 + connect \A \ui + connect \B 5'10000 + connect \Y $sshl$issuer_ls180.v:109693$4203_Y + end + attribute \src "issuer_ls180.v:109608.7-109608.20" + process $proc$issuer_ls180.v:109608$4214 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "issuer_ls180.v:109696.3-109742.6" + process $proc$issuer_ls180.v:109696$4206 + assign { } { } + assign { } { } + assign $0\imm_b[63:0] $1\imm_b[63:0] + attribute \src "issuer_ls180.v:109697.5-109697.29" + switch \initial + attribute \src "issuer_ls180.v:109697.9-109697.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:224" + switch \sel_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0010 + assign { } { } + assign $1\imm_b[63:0] \$1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0011 + assign { } { } + assign $1\imm_b[63:0] { \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si } + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0101 + assign { } { } + assign $1\imm_b[63:0] { \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi } + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0100 + assign { } { } + assign $1\imm_b[63:0] \$3 + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\imm_b[63:0] { \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li } + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $1\imm_b[63:0] { \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd } + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\imm_b[63:0] { \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds } + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'1001 + assign { } { } + assign $1\imm_b[63:0] \$7 + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'1010 + assign { } { } + assign $1\imm_b[63:0] \$9 + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'1011 + assign { } { } + assign $1\imm_b[63:0] \$11 + case + assign $1\imm_b[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \imm_b $0\imm_b[63:0] + end + attribute \src "issuer_ls180.v:109743.3-109789.6" + process $proc$issuer_ls180.v:109743$4207 + assign { } { } + assign { } { } + assign $0\imm_b_ok[0:0] $1\imm_b_ok[0:0] + attribute \src "issuer_ls180.v:109744.5-109744.29" + switch \initial + attribute \src "issuer_ls180.v:109744.9-109744.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:224" + switch \sel_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0010 + assign { } { } + assign $1\imm_b_ok[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0011 + assign { } { } + assign $1\imm_b_ok[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0101 + assign { } { } + assign $1\imm_b_ok[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0100 + assign { } { } + assign $1\imm_b_ok[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\imm_b_ok[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $1\imm_b_ok[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\imm_b_ok[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'1001 + assign { } { } + assign $1\imm_b_ok[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'1010 + assign { } { } + assign $1\imm_b_ok[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'1011 + assign { } { } + assign $1\imm_b_ok[0:0] 1'1 + case + assign $1\imm_b_ok[0:0] 1'0 + end + sync always + update \imm_b_ok $0\imm_b_ok[0:0] + end + attribute \src "issuer_ls180.v:109790.3-109800.6" + process $proc$issuer_ls180.v:109790$4208 + assign { } { } + assign { } { } + assign $0\si[15:0] $1\si[15:0] + attribute \src "issuer_ls180.v:109791.5-109791.29" + switch \initial + attribute \src "issuer_ls180.v:109791.9-109791.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:224" + switch \sel_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0011 + assign { } { } + assign $1\si[15:0] \LOGICAL_SI + case + assign $1\si[15:0] 16'0000000000000000 + end + sync always + update \si $0\si[15:0] + end + attribute \src "issuer_ls180.v:109801.3-109811.6" + process $proc$issuer_ls180.v:109801$4209 + assign { } { } + assign { } { } + assign $0\si_hi[31:0] $1\si_hi[31:0] + attribute \src "issuer_ls180.v:109802.5-109802.29" + switch \initial + attribute \src "issuer_ls180.v:109802.9-109802.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:224" + switch \sel_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0101 + assign { } { } + assign $1\si_hi[31:0] \$13 [31:0] + case + assign $1\si_hi[31:0] 0 + end + sync always + update \si_hi $0\si_hi[31:0] + end + attribute \src "issuer_ls180.v:109812.3-109822.6" + process $proc$issuer_ls180.v:109812$4210 + assign { } { } + assign { } { } + assign $0\ui[15:0] $1\ui[15:0] + attribute \src "issuer_ls180.v:109813.5-109813.29" + switch \initial + attribute \src "issuer_ls180.v:109813.9-109813.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:224" + switch \sel_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0100 + assign { } { } + assign $1\ui[15:0] \LOGICAL_UI + case + assign $1\ui[15:0] 16'0000000000000000 + end + sync always + update \ui $0\ui[15:0] + end + attribute \src "issuer_ls180.v:109823.3-109833.6" + process $proc$issuer_ls180.v:109823$4211 + assign { } { } + assign { } { } + assign $0\li[25:0] $1\li[25:0] + attribute \src "issuer_ls180.v:109824.5-109824.29" + switch \initial + attribute \src "issuer_ls180.v:109824.9-109824.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:224" + switch \sel_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\li[25:0] \$16 [25:0] + case + assign $1\li[25:0] 26'00000000000000000000000000 + end + sync always + update \li $0\li[25:0] + end + attribute \src "issuer_ls180.v:109834.3-109844.6" + process $proc$issuer_ls180.v:109834$4212 + assign { } { } + assign { } { } + assign $0\bd[15:0] $1\bd[15:0] + attribute \src "issuer_ls180.v:109835.5-109835.29" + switch \initial + attribute \src "issuer_ls180.v:109835.9-109835.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:224" + switch \sel_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $1\bd[15:0] \$19 [15:0] + case + assign $1\bd[15:0] 16'0000000000000000 + end + sync always + update \bd $0\bd[15:0] + end + attribute \src "issuer_ls180.v:109845.3-109855.6" + process $proc$issuer_ls180.v:109845$4213 + assign { } { } + assign { } { } + assign $0\ds[15:0] $1\ds[15:0] + attribute \src "issuer_ls180.v:109846.5-109846.29" + switch \initial + attribute \src "issuer_ls180.v:109846.9-109846.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:224" + switch \sel_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\ds[15:0] \$22 [15:0] + case + assign $1\ds[15:0] 16'0000000000000000 + end + sync always + update \ds $0\ds[15:0] + end + connect \$9 $pos$issuer_ls180.v:109686$4194_Y + connect \$11 $pos$issuer_ls180.v:109687$4196_Y + connect \$14 $sshl$issuer_ls180.v:109688$4197_Y + connect \$17 $sshl$issuer_ls180.v:109689$4198_Y + connect \$1 $pos$issuer_ls180.v:109690$4200_Y + connect \$20 $sshl$issuer_ls180.v:109691$4201_Y + connect \$23 $sshl$issuer_ls180.v:109692$4202_Y + connect \$4 $sshl$issuer_ls180.v:109693$4203_Y + connect \$3 $pos$issuer_ls180.v:109694$4205_Y + connect \$7 64'1111111111111111111111111111111111111111111111111111111111111111 + connect \$13 \$14 + connect \$16 \$17 + connect \$19 \$20 + connect \$22 \$23 +end +attribute \src "issuer_ls180.v:109864.1-110117.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.dec_DIV.dec_bi" +attribute \generator "nMigen" +module \dec_bi$176 + attribute \src "issuer_ls180.v:110091.3-110101.6" + wire width 16 $0\bd[15:0] + attribute \src "issuer_ls180.v:110102.3-110112.6" + wire width 16 $0\ds[15:0] + attribute \src "issuer_ls180.v:109953.3-109999.6" + wire width 64 $0\imm_b[63:0] + attribute \src "issuer_ls180.v:110000.3-110046.6" + wire $0\imm_b_ok[0:0] + attribute \src "issuer_ls180.v:109865.7-109865.20" + wire $0\initial[0:0] + attribute \src "issuer_ls180.v:110080.3-110090.6" + wire width 26 $0\li[25:0] + attribute \src "issuer_ls180.v:110047.3-110057.6" + wire width 16 $0\si[15:0] + attribute \src "issuer_ls180.v:110058.3-110068.6" + wire width 32 $0\si_hi[31:0] + attribute \src "issuer_ls180.v:110069.3-110079.6" + wire width 16 $0\ui[15:0] + attribute \src "issuer_ls180.v:110091.3-110101.6" + wire width 16 $1\bd[15:0] + attribute \src "issuer_ls180.v:110102.3-110112.6" + wire width 16 $1\ds[15:0] + attribute \src "issuer_ls180.v:109953.3-109999.6" + wire width 64 $1\imm_b[63:0] + attribute \src "issuer_ls180.v:110000.3-110046.6" + wire $1\imm_b_ok[0:0] + attribute \src "issuer_ls180.v:110080.3-110090.6" + wire width 26 $1\li[25:0] + attribute \src "issuer_ls180.v:110047.3-110057.6" + wire width 16 $1\si[15:0] + attribute \src "issuer_ls180.v:110058.3-110068.6" + wire width 32 $1\si_hi[31:0] + attribute \src "issuer_ls180.v:110069.3-110079.6" + wire width 16 $1\ui[15:0] + attribute \src "issuer_ls180.v:109943.17-109943.104" + wire width 64 $extend$issuer_ls180.v:109943$4215_Y + attribute \src "issuer_ls180.v:109944.18-109944.107" + wire width 64 $extend$issuer_ls180.v:109944$4217_Y + attribute \src "issuer_ls180.v:109947.17-109947.104" + wire width 64 $extend$issuer_ls180.v:109947$4221_Y + attribute \src "issuer_ls180.v:109951.17-109951.102" + wire width 64 $extend$issuer_ls180.v:109951$4226_Y + attribute \src "issuer_ls180.v:109943.17-109943.104" + wire width 64 $pos$issuer_ls180.v:109943$4216_Y + attribute \src "issuer_ls180.v:109944.18-109944.107" + wire width 64 $pos$issuer_ls180.v:109944$4218_Y + attribute \src "issuer_ls180.v:109947.17-109947.104" + wire width 64 $pos$issuer_ls180.v:109947$4222_Y + attribute \src "issuer_ls180.v:109951.17-109951.102" + wire width 64 $pos$issuer_ls180.v:109951$4227_Y + attribute \src "issuer_ls180.v:109945.18-109945.114" + wire width 47 $sshl$issuer_ls180.v:109945$4219_Y + attribute \src "issuer_ls180.v:109946.18-109946.113" + wire width 27 $sshl$issuer_ls180.v:109946$4220_Y + attribute \src "issuer_ls180.v:109948.18-109948.113" + wire width 17 $sshl$issuer_ls180.v:109948$4223_Y + attribute \src "issuer_ls180.v:109949.18-109949.113" + wire width 17 $sshl$issuer_ls180.v:109949$4224_Y + attribute \src "issuer_ls180.v:109950.17-109950.109" + wire width 47 $sshl$issuer_ls180.v:109950$4225_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 64 \$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 64 \$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:235" + wire width 47 \$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:235" + wire width 47 \$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:245" + wire width 27 \$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:245" + wire width 27 \$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:250" + wire width 17 \$19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:250" + wire width 17 \$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:255" + wire width 17 \$22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:255" + wire width 17 \$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:241" + wire width 64 \$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:241" + wire width 47 \$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:259" + wire width 64 \$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 64 \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 14 input 8 \DIV_BD + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 14 input 9 \DIV_DS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 24 input 7 \DIV_LI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 input 5 \DIV_SH32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 16 input 3 \DIV_SI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 16 input 4 \DIV_UI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 6 input 6 \DIV_sh + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:249" + wire width 16 \bd + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:254" + wire width 16 \ds + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 output 1 \imm_b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 2 \imm_b_ok + attribute \src "issuer_ls180.v:109865.7-109865.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" + wire width 26 \li + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:216" + wire width 4 input 10 \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:229" + wire width 16 \si + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:234" + wire width 32 \si_hi + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:239" + wire width 16 \ui + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + cell $pos $extend$issuer_ls180.v:109943$4215 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \Y_WIDTH 64 + connect \A \DIV_sh + connect \Y $extend$issuer_ls180.v:109943$4215_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + cell $pos $extend$issuer_ls180.v:109944$4217 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \Y_WIDTH 64 + connect \A \DIV_SH32 + connect \Y $extend$issuer_ls180.v:109944$4217_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + cell $pos $extend$issuer_ls180.v:109947$4221 + parameter \A_SIGNED 0 + parameter \A_WIDTH 16 + parameter \Y_WIDTH 64 + connect \A \DIV_UI + connect \Y $extend$issuer_ls180.v:109947$4221_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:241" + cell $pos $extend$issuer_ls180.v:109951$4226 + parameter \A_SIGNED 0 + parameter \A_WIDTH 47 + parameter \Y_WIDTH 64 + connect \A \$4 + connect \Y $extend$issuer_ls180.v:109951$4226_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + cell $pos $pos$issuer_ls180.v:109943$4216 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A $extend$issuer_ls180.v:109943$4215_Y + connect \Y $pos$issuer_ls180.v:109943$4216_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + cell $pos $pos$issuer_ls180.v:109944$4218 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A $extend$issuer_ls180.v:109944$4217_Y + connect \Y $pos$issuer_ls180.v:109944$4218_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + cell $pos $pos$issuer_ls180.v:109947$4222 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A $extend$issuer_ls180.v:109947$4221_Y + connect \Y $pos$issuer_ls180.v:109947$4222_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:241" + cell $pos $pos$issuer_ls180.v:109951$4227 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A $extend$issuer_ls180.v:109951$4226_Y + connect \Y $pos$issuer_ls180.v:109951$4227_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:235" + cell $sshl $sshl$issuer_ls180.v:109945$4219 + parameter \A_SIGNED 0 + parameter \A_WIDTH 16 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 47 + connect \A \DIV_SI + connect \B 5'10000 + connect \Y $sshl$issuer_ls180.v:109945$4219_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:245" + cell $sshl $sshl$issuer_ls180.v:109946$4220 + parameter \A_SIGNED 0 + parameter \A_WIDTH 24 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 27 + connect \A \DIV_LI + connect \B 2'10 + connect \Y $sshl$issuer_ls180.v:109946$4220_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:250" + cell $sshl $sshl$issuer_ls180.v:109948$4223 + parameter \A_SIGNED 0 + parameter \A_WIDTH 14 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 17 + connect \A \DIV_BD + connect \B 2'10 + connect \Y $sshl$issuer_ls180.v:109948$4223_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:255" + cell $sshl $sshl$issuer_ls180.v:109949$4224 + parameter \A_SIGNED 0 + parameter \A_WIDTH 14 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 17 + connect \A \DIV_DS + connect \B 2'10 + connect \Y $sshl$issuer_ls180.v:109949$4224_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:241" + cell $sshl $sshl$issuer_ls180.v:109950$4225 + parameter \A_SIGNED 0 + parameter \A_WIDTH 16 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 47 + connect \A \ui + connect \B 5'10000 + connect \Y $sshl$issuer_ls180.v:109950$4225_Y + end + attribute \src "issuer_ls180.v:109865.7-109865.20" + process $proc$issuer_ls180.v:109865$4236 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "issuer_ls180.v:109953.3-109999.6" + process $proc$issuer_ls180.v:109953$4228 + assign { } { } + assign { } { } + assign $0\imm_b[63:0] $1\imm_b[63:0] + attribute \src "issuer_ls180.v:109954.5-109954.29" + switch \initial + attribute \src "issuer_ls180.v:109954.9-109954.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:224" + switch \sel_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0010 + assign { } { } + assign $1\imm_b[63:0] \$1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0011 + assign { } { } + assign $1\imm_b[63:0] { \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si } + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0101 + assign { } { } + assign $1\imm_b[63:0] { \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi } + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0100 + assign { } { } + assign $1\imm_b[63:0] \$3 + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\imm_b[63:0] { \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li } + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $1\imm_b[63:0] { \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd } + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\imm_b[63:0] { \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds } + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'1001 + assign { } { } + assign $1\imm_b[63:0] \$7 + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'1010 + assign { } { } + assign $1\imm_b[63:0] \$9 + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'1011 + assign { } { } + assign $1\imm_b[63:0] \$11 + case + assign $1\imm_b[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \imm_b $0\imm_b[63:0] + end + attribute \src "issuer_ls180.v:110000.3-110046.6" + process $proc$issuer_ls180.v:110000$4229 + assign { } { } + assign { } { } + assign $0\imm_b_ok[0:0] $1\imm_b_ok[0:0] + attribute \src "issuer_ls180.v:110001.5-110001.29" + switch \initial + attribute \src "issuer_ls180.v:110001.9-110001.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:224" + switch \sel_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0010 + assign { } { } + assign $1\imm_b_ok[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0011 + assign { } { } + assign $1\imm_b_ok[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0101 + assign { } { } + assign $1\imm_b_ok[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0100 + assign { } { } + assign $1\imm_b_ok[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\imm_b_ok[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $1\imm_b_ok[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\imm_b_ok[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'1001 + assign { } { } + assign $1\imm_b_ok[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'1010 + assign { } { } + assign $1\imm_b_ok[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'1011 + assign { } { } + assign $1\imm_b_ok[0:0] 1'1 + case + assign $1\imm_b_ok[0:0] 1'0 + end + sync always + update \imm_b_ok $0\imm_b_ok[0:0] + end + attribute \src "issuer_ls180.v:110047.3-110057.6" + process $proc$issuer_ls180.v:110047$4230 + assign { } { } + assign { } { } + assign $0\si[15:0] $1\si[15:0] + attribute \src "issuer_ls180.v:110048.5-110048.29" + switch \initial + attribute \src "issuer_ls180.v:110048.9-110048.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:224" + switch \sel_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0011 + assign { } { } + assign $1\si[15:0] \DIV_SI + case + assign $1\si[15:0] 16'0000000000000000 + end + sync always + update \si $0\si[15:0] + end + attribute \src "issuer_ls180.v:110058.3-110068.6" + process $proc$issuer_ls180.v:110058$4231 + assign { } { } + assign { } { } + assign $0\si_hi[31:0] $1\si_hi[31:0] + attribute \src "issuer_ls180.v:110059.5-110059.29" + switch \initial + attribute \src "issuer_ls180.v:110059.9-110059.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:224" + switch \sel_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0101 + assign { } { } + assign $1\si_hi[31:0] \$13 [31:0] + case + assign $1\si_hi[31:0] 0 + end + sync always + update \si_hi $0\si_hi[31:0] + end + attribute \src "issuer_ls180.v:110069.3-110079.6" + process $proc$issuer_ls180.v:110069$4232 + assign { } { } + assign { } { } + assign $0\ui[15:0] $1\ui[15:0] + attribute \src "issuer_ls180.v:110070.5-110070.29" + switch \initial + attribute \src "issuer_ls180.v:110070.9-110070.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:224" + switch \sel_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0100 + assign { } { } + assign $1\ui[15:0] \DIV_UI + case + assign $1\ui[15:0] 16'0000000000000000 + end + sync always + update \ui $0\ui[15:0] + end + attribute \src "issuer_ls180.v:110080.3-110090.6" + process $proc$issuer_ls180.v:110080$4233 + assign { } { } + assign { } { } + assign $0\li[25:0] $1\li[25:0] + attribute \src "issuer_ls180.v:110081.5-110081.29" + switch \initial + attribute \src "issuer_ls180.v:110081.9-110081.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:224" + switch \sel_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\li[25:0] \$16 [25:0] + case + assign $1\li[25:0] 26'00000000000000000000000000 + end + sync always + update \li $0\li[25:0] + end + attribute \src "issuer_ls180.v:110091.3-110101.6" + process $proc$issuer_ls180.v:110091$4234 + assign { } { } + assign { } { } + assign $0\bd[15:0] $1\bd[15:0] + attribute \src "issuer_ls180.v:110092.5-110092.29" + switch \initial + attribute \src "issuer_ls180.v:110092.9-110092.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:224" + switch \sel_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $1\bd[15:0] \$19 [15:0] + case + assign $1\bd[15:0] 16'0000000000000000 + end + sync always + update \bd $0\bd[15:0] + end + attribute \src "issuer_ls180.v:110102.3-110112.6" + process $proc$issuer_ls180.v:110102$4235 + assign { } { } + assign { } { } + assign $0\ds[15:0] $1\ds[15:0] + attribute \src "issuer_ls180.v:110103.5-110103.29" + switch \initial + attribute \src "issuer_ls180.v:110103.9-110103.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:224" + switch \sel_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\ds[15:0] \$22 [15:0] + case + assign $1\ds[15:0] 16'0000000000000000 + end + sync always + update \ds $0\ds[15:0] + end + connect \$9 $pos$issuer_ls180.v:109943$4216_Y + connect \$11 $pos$issuer_ls180.v:109944$4218_Y + connect \$14 $sshl$issuer_ls180.v:109945$4219_Y + connect \$17 $sshl$issuer_ls180.v:109946$4220_Y + connect \$1 $pos$issuer_ls180.v:109947$4222_Y + connect \$20 $sshl$issuer_ls180.v:109948$4223_Y + connect \$23 $sshl$issuer_ls180.v:109949$4224_Y + connect \$4 $sshl$issuer_ls180.v:109950$4225_Y + connect \$3 $pos$issuer_ls180.v:109951$4227_Y + connect \$7 64'1111111111111111111111111111111111111111111111111111111111111111 + connect \$13 \$14 + connect \$16 \$17 + connect \$19 \$20 + connect \$22 \$23 +end +attribute \src "issuer_ls180.v:110121.1-110374.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.dec_MUL.dec_bi" +attribute \generator "nMigen" +module \dec_bi$184 + attribute \src "issuer_ls180.v:110348.3-110358.6" + wire width 16 $0\bd[15:0] + attribute \src "issuer_ls180.v:110359.3-110369.6" + wire width 16 $0\ds[15:0] + attribute \src "issuer_ls180.v:110210.3-110256.6" + wire width 64 $0\imm_b[63:0] + attribute \src "issuer_ls180.v:110257.3-110303.6" + wire $0\imm_b_ok[0:0] + attribute \src "issuer_ls180.v:110122.7-110122.20" + wire $0\initial[0:0] + attribute \src "issuer_ls180.v:110337.3-110347.6" + wire width 26 $0\li[25:0] + attribute \src "issuer_ls180.v:110304.3-110314.6" + wire width 16 $0\si[15:0] + attribute \src "issuer_ls180.v:110315.3-110325.6" + wire width 32 $0\si_hi[31:0] + attribute \src "issuer_ls180.v:110326.3-110336.6" + wire width 16 $0\ui[15:0] + attribute \src "issuer_ls180.v:110348.3-110358.6" + wire width 16 $1\bd[15:0] + attribute \src "issuer_ls180.v:110359.3-110369.6" + wire width 16 $1\ds[15:0] + attribute \src "issuer_ls180.v:110210.3-110256.6" + wire width 64 $1\imm_b[63:0] + attribute \src "issuer_ls180.v:110257.3-110303.6" + wire $1\imm_b_ok[0:0] + attribute \src "issuer_ls180.v:110337.3-110347.6" + wire width 26 $1\li[25:0] + attribute \src "issuer_ls180.v:110304.3-110314.6" + wire width 16 $1\si[15:0] + attribute \src "issuer_ls180.v:110315.3-110325.6" + wire width 32 $1\si_hi[31:0] + attribute \src "issuer_ls180.v:110326.3-110336.6" + wire width 16 $1\ui[15:0] + attribute \src "issuer_ls180.v:110200.17-110200.104" + wire width 64 $extend$issuer_ls180.v:110200$4237_Y + attribute \src "issuer_ls180.v:110201.18-110201.107" + wire width 64 $extend$issuer_ls180.v:110201$4239_Y + attribute \src "issuer_ls180.v:110204.17-110204.104" + wire width 64 $extend$issuer_ls180.v:110204$4243_Y + attribute \src "issuer_ls180.v:110208.17-110208.102" + wire width 64 $extend$issuer_ls180.v:110208$4248_Y + attribute \src "issuer_ls180.v:110200.17-110200.104" + wire width 64 $pos$issuer_ls180.v:110200$4238_Y + attribute \src "issuer_ls180.v:110201.18-110201.107" + wire width 64 $pos$issuer_ls180.v:110201$4240_Y + attribute \src "issuer_ls180.v:110204.17-110204.104" + wire width 64 $pos$issuer_ls180.v:110204$4244_Y + attribute \src "issuer_ls180.v:110208.17-110208.102" + wire width 64 $pos$issuer_ls180.v:110208$4249_Y + attribute \src "issuer_ls180.v:110202.18-110202.114" + wire width 47 $sshl$issuer_ls180.v:110202$4241_Y + attribute \src "issuer_ls180.v:110203.18-110203.113" + wire width 27 $sshl$issuer_ls180.v:110203$4242_Y + attribute \src "issuer_ls180.v:110205.18-110205.113" + wire width 17 $sshl$issuer_ls180.v:110205$4245_Y + attribute \src "issuer_ls180.v:110206.18-110206.113" + wire width 17 $sshl$issuer_ls180.v:110206$4246_Y + attribute \src "issuer_ls180.v:110207.17-110207.109" + wire width 47 $sshl$issuer_ls180.v:110207$4247_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 64 \$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 64 \$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:235" + wire width 47 \$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:235" + wire width 47 \$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:245" + wire width 27 \$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:245" + wire width 27 \$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:250" + wire width 17 \$19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:250" + wire width 17 \$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:255" + wire width 17 \$22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:255" + wire width 17 \$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:241" + wire width 64 \$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:241" + wire width 47 \$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:259" + wire width 64 \$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 64 \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 14 input 8 \MUL_BD + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 14 input 9 \MUL_DS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 24 input 7 \MUL_LI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 input 5 \MUL_SH32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 16 input 3 \MUL_SI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 16 input 4 \MUL_UI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 6 input 6 \MUL_sh + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:249" + wire width 16 \bd + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:254" + wire width 16 \ds + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 output 1 \imm_b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 2 \imm_b_ok + attribute \src "issuer_ls180.v:110122.7-110122.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" + wire width 26 \li + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:216" + wire width 4 input 10 \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:229" + wire width 16 \si + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:234" + wire width 32 \si_hi + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:239" + wire width 16 \ui + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + cell $pos $extend$issuer_ls180.v:110200$4237 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \Y_WIDTH 64 + connect \A \MUL_sh + connect \Y $extend$issuer_ls180.v:110200$4237_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + cell $pos $extend$issuer_ls180.v:110201$4239 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \Y_WIDTH 64 + connect \A \MUL_SH32 + connect \Y $extend$issuer_ls180.v:110201$4239_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + cell $pos $extend$issuer_ls180.v:110204$4243 + parameter \A_SIGNED 0 + parameter \A_WIDTH 16 + parameter \Y_WIDTH 64 + connect \A \MUL_UI + connect \Y $extend$issuer_ls180.v:110204$4243_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:241" + cell $pos $extend$issuer_ls180.v:110208$4248 + parameter \A_SIGNED 0 + parameter \A_WIDTH 47 + parameter \Y_WIDTH 64 + connect \A \$4 + connect \Y $extend$issuer_ls180.v:110208$4248_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + cell $pos $pos$issuer_ls180.v:110200$4238 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A $extend$issuer_ls180.v:110200$4237_Y + connect \Y $pos$issuer_ls180.v:110200$4238_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + cell $pos $pos$issuer_ls180.v:110201$4240 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A $extend$issuer_ls180.v:110201$4239_Y + connect \Y $pos$issuer_ls180.v:110201$4240_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + cell $pos $pos$issuer_ls180.v:110204$4244 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A $extend$issuer_ls180.v:110204$4243_Y + connect \Y $pos$issuer_ls180.v:110204$4244_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:241" + cell $pos $pos$issuer_ls180.v:110208$4249 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A $extend$issuer_ls180.v:110208$4248_Y + connect \Y $pos$issuer_ls180.v:110208$4249_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:235" + cell $sshl $sshl$issuer_ls180.v:110202$4241 + parameter \A_SIGNED 0 + parameter \A_WIDTH 16 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 47 + connect \A \MUL_SI + connect \B 5'10000 + connect \Y $sshl$issuer_ls180.v:110202$4241_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:245" + cell $sshl $sshl$issuer_ls180.v:110203$4242 + parameter \A_SIGNED 0 + parameter \A_WIDTH 24 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 27 + connect \A \MUL_LI + connect \B 2'10 + connect \Y $sshl$issuer_ls180.v:110203$4242_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:250" + cell $sshl $sshl$issuer_ls180.v:110205$4245 + parameter \A_SIGNED 0 + parameter \A_WIDTH 14 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 17 + connect \A \MUL_BD + connect \B 2'10 + connect \Y $sshl$issuer_ls180.v:110205$4245_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:255" + cell $sshl $sshl$issuer_ls180.v:110206$4246 + parameter \A_SIGNED 0 + parameter \A_WIDTH 14 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 17 + connect \A \MUL_DS + connect \B 2'10 + connect \Y $sshl$issuer_ls180.v:110206$4246_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:241" + cell $sshl $sshl$issuer_ls180.v:110207$4247 + parameter \A_SIGNED 0 + parameter \A_WIDTH 16 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 47 + connect \A \ui + connect \B 5'10000 + connect \Y $sshl$issuer_ls180.v:110207$4247_Y + end + attribute \src "issuer_ls180.v:110122.7-110122.20" + process $proc$issuer_ls180.v:110122$4258 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "issuer_ls180.v:110210.3-110256.6" + process $proc$issuer_ls180.v:110210$4250 + assign { } { } + assign { } { } + assign $0\imm_b[63:0] $1\imm_b[63:0] + attribute \src "issuer_ls180.v:110211.5-110211.29" + switch \initial + attribute \src "issuer_ls180.v:110211.9-110211.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:224" + switch \sel_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0010 + assign { } { } + assign $1\imm_b[63:0] \$1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0011 + assign { } { } + assign $1\imm_b[63:0] { \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si } + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0101 + assign { } { } + assign $1\imm_b[63:0] { \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi } + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0100 + assign { } { } + assign $1\imm_b[63:0] \$3 + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\imm_b[63:0] { \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li } + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $1\imm_b[63:0] { \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd } + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\imm_b[63:0] { \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds } + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'1001 + assign { } { } + assign $1\imm_b[63:0] \$7 + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'1010 + assign { } { } + assign $1\imm_b[63:0] \$9 + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'1011 + assign { } { } + assign $1\imm_b[63:0] \$11 + case + assign $1\imm_b[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \imm_b $0\imm_b[63:0] + end + attribute \src "issuer_ls180.v:110257.3-110303.6" + process $proc$issuer_ls180.v:110257$4251 + assign { } { } + assign { } { } + assign $0\imm_b_ok[0:0] $1\imm_b_ok[0:0] + attribute \src "issuer_ls180.v:110258.5-110258.29" + switch \initial + attribute \src "issuer_ls180.v:110258.9-110258.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:224" + switch \sel_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0010 + assign { } { } + assign $1\imm_b_ok[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0011 + assign { } { } + assign $1\imm_b_ok[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0101 + assign { } { } + assign $1\imm_b_ok[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0100 + assign { } { } + assign $1\imm_b_ok[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\imm_b_ok[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $1\imm_b_ok[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\imm_b_ok[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'1001 + assign { } { } + assign $1\imm_b_ok[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'1010 + assign { } { } + assign $1\imm_b_ok[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'1011 + assign { } { } + assign $1\imm_b_ok[0:0] 1'1 + case + assign $1\imm_b_ok[0:0] 1'0 + end + sync always + update \imm_b_ok $0\imm_b_ok[0:0] + end + attribute \src "issuer_ls180.v:110304.3-110314.6" + process $proc$issuer_ls180.v:110304$4252 + assign { } { } + assign { } { } + assign $0\si[15:0] $1\si[15:0] + attribute \src "issuer_ls180.v:110305.5-110305.29" + switch \initial + attribute \src "issuer_ls180.v:110305.9-110305.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:224" + switch \sel_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0011 + assign { } { } + assign $1\si[15:0] \MUL_SI + case + assign $1\si[15:0] 16'0000000000000000 + end + sync always + update \si $0\si[15:0] + end + attribute \src "issuer_ls180.v:110315.3-110325.6" + process $proc$issuer_ls180.v:110315$4253 + assign { } { } + assign { } { } + assign $0\si_hi[31:0] $1\si_hi[31:0] + attribute \src "issuer_ls180.v:110316.5-110316.29" + switch \initial + attribute \src "issuer_ls180.v:110316.9-110316.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:224" + switch \sel_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0101 + assign { } { } + assign $1\si_hi[31:0] \$13 [31:0] + case + assign $1\si_hi[31:0] 0 + end + sync always + update \si_hi $0\si_hi[31:0] + end + attribute \src "issuer_ls180.v:110326.3-110336.6" + process $proc$issuer_ls180.v:110326$4254 + assign { } { } + assign { } { } + assign $0\ui[15:0] $1\ui[15:0] + attribute \src "issuer_ls180.v:110327.5-110327.29" + switch \initial + attribute \src "issuer_ls180.v:110327.9-110327.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:224" + switch \sel_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0100 + assign { } { } + assign $1\ui[15:0] \MUL_UI + case + assign $1\ui[15:0] 16'0000000000000000 + end + sync always + update \ui $0\ui[15:0] + end + attribute \src "issuer_ls180.v:110337.3-110347.6" + process $proc$issuer_ls180.v:110337$4255 + assign { } { } + assign { } { } + assign $0\li[25:0] $1\li[25:0] + attribute \src "issuer_ls180.v:110338.5-110338.29" + switch \initial + attribute \src "issuer_ls180.v:110338.9-110338.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:224" + switch \sel_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\li[25:0] \$16 [25:0] + case + assign $1\li[25:0] 26'00000000000000000000000000 + end + sync always + update \li $0\li[25:0] + end + attribute \src "issuer_ls180.v:110348.3-110358.6" + process $proc$issuer_ls180.v:110348$4256 + assign { } { } + assign { } { } + assign $0\bd[15:0] $1\bd[15:0] + attribute \src "issuer_ls180.v:110349.5-110349.29" + switch \initial + attribute \src "issuer_ls180.v:110349.9-110349.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:224" + switch \sel_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $1\bd[15:0] \$19 [15:0] + case + assign $1\bd[15:0] 16'0000000000000000 + end + sync always + update \bd $0\bd[15:0] + end + attribute \src "issuer_ls180.v:110359.3-110369.6" + process $proc$issuer_ls180.v:110359$4257 + assign { } { } + assign { } { } + assign $0\ds[15:0] $1\ds[15:0] + attribute \src "issuer_ls180.v:110360.5-110360.29" + switch \initial + attribute \src "issuer_ls180.v:110360.9-110360.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:224" + switch \sel_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\ds[15:0] \$22 [15:0] + case + assign $1\ds[15:0] 16'0000000000000000 + end + sync always + update \ds $0\ds[15:0] + end + connect \$9 $pos$issuer_ls180.v:110200$4238_Y + connect \$11 $pos$issuer_ls180.v:110201$4240_Y + connect \$14 $sshl$issuer_ls180.v:110202$4241_Y + connect \$17 $sshl$issuer_ls180.v:110203$4242_Y + connect \$1 $pos$issuer_ls180.v:110204$4244_Y + connect \$20 $sshl$issuer_ls180.v:110205$4245_Y + connect \$23 $sshl$issuer_ls180.v:110206$4246_Y + connect \$4 $sshl$issuer_ls180.v:110207$4247_Y + connect \$3 $pos$issuer_ls180.v:110208$4249_Y + connect \$7 64'1111111111111111111111111111111111111111111111111111111111111111 + connect \$13 \$14 + connect \$16 \$17 + connect \$19 \$20 + connect \$22 \$23 +end +attribute \src "issuer_ls180.v:110378.1-110631.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.dec_SHIFT_ROT.dec_bi" +attribute \generator "nMigen" +module \dec_bi$192 + attribute \src "issuer_ls180.v:110605.3-110615.6" + wire width 16 $0\bd[15:0] + attribute \src "issuer_ls180.v:110616.3-110626.6" + wire width 16 $0\ds[15:0] + attribute \src "issuer_ls180.v:110467.3-110513.6" + wire width 64 $0\imm_b[63:0] + attribute \src "issuer_ls180.v:110514.3-110560.6" + wire $0\imm_b_ok[0:0] + attribute \src "issuer_ls180.v:110379.7-110379.20" + wire $0\initial[0:0] + attribute \src "issuer_ls180.v:110594.3-110604.6" + wire width 26 $0\li[25:0] + attribute \src "issuer_ls180.v:110561.3-110571.6" + wire width 16 $0\si[15:0] + attribute \src "issuer_ls180.v:110572.3-110582.6" + wire width 32 $0\si_hi[31:0] + attribute \src "issuer_ls180.v:110583.3-110593.6" + wire width 16 $0\ui[15:0] + attribute \src "issuer_ls180.v:110605.3-110615.6" + wire width 16 $1\bd[15:0] + attribute \src "issuer_ls180.v:110616.3-110626.6" + wire width 16 $1\ds[15:0] + attribute \src "issuer_ls180.v:110467.3-110513.6" + wire width 64 $1\imm_b[63:0] + attribute \src "issuer_ls180.v:110514.3-110560.6" + wire $1\imm_b_ok[0:0] + attribute \src "issuer_ls180.v:110594.3-110604.6" + wire width 26 $1\li[25:0] + attribute \src "issuer_ls180.v:110561.3-110571.6" + wire width 16 $1\si[15:0] + attribute \src "issuer_ls180.v:110572.3-110582.6" + wire width 32 $1\si_hi[31:0] + attribute \src "issuer_ls180.v:110583.3-110593.6" + wire width 16 $1\ui[15:0] + attribute \src "issuer_ls180.v:110457.17-110457.110" + wire width 64 $extend$issuer_ls180.v:110457$4259_Y + attribute \src "issuer_ls180.v:110458.18-110458.113" + wire width 64 $extend$issuer_ls180.v:110458$4261_Y + attribute \src "issuer_ls180.v:110461.17-110461.110" + wire width 64 $extend$issuer_ls180.v:110461$4265_Y + attribute \src "issuer_ls180.v:110465.17-110465.102" + wire width 64 $extend$issuer_ls180.v:110465$4270_Y + attribute \src "issuer_ls180.v:110457.17-110457.110" + wire width 64 $pos$issuer_ls180.v:110457$4260_Y + attribute \src "issuer_ls180.v:110458.18-110458.113" + wire width 64 $pos$issuer_ls180.v:110458$4262_Y + attribute \src "issuer_ls180.v:110461.17-110461.110" + wire width 64 $pos$issuer_ls180.v:110461$4266_Y + attribute \src "issuer_ls180.v:110465.17-110465.102" + wire width 64 $pos$issuer_ls180.v:110465$4271_Y + attribute \src "issuer_ls180.v:110459.18-110459.120" + wire width 47 $sshl$issuer_ls180.v:110459$4263_Y + attribute \src "issuer_ls180.v:110460.18-110460.119" + wire width 27 $sshl$issuer_ls180.v:110460$4264_Y + attribute \src "issuer_ls180.v:110462.18-110462.119" + wire width 17 $sshl$issuer_ls180.v:110462$4267_Y + attribute \src "issuer_ls180.v:110463.18-110463.119" + wire width 17 $sshl$issuer_ls180.v:110463$4268_Y + attribute \src "issuer_ls180.v:110464.17-110464.109" + wire width 47 $sshl$issuer_ls180.v:110464$4269_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 64 \$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 64 \$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:235" + wire width 47 \$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:235" + wire width 47 \$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:245" + wire width 27 \$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:245" + wire width 27 \$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:250" + wire width 17 \$19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:250" + wire width 17 \$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:255" + wire width 17 \$22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:255" + wire width 17 \$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:241" + wire width 64 \$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:241" + wire width 47 \$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:259" + wire width 64 \$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 64 \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 14 input 8 \SHIFT_ROT_BD + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 14 input 9 \SHIFT_ROT_DS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 24 input 7 \SHIFT_ROT_LI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 input 5 \SHIFT_ROT_SH32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 16 input 3 \SHIFT_ROT_SI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 16 input 4 \SHIFT_ROT_UI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 6 input 6 \SHIFT_ROT_sh + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:249" + wire width 16 \bd + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:254" + wire width 16 \ds + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 output 1 \imm_b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 2 \imm_b_ok + attribute \src "issuer_ls180.v:110379.7-110379.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" + wire width 26 \li + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:216" + wire width 4 input 10 \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:229" + wire width 16 \si + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:234" + wire width 32 \si_hi + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:239" + wire width 16 \ui + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + cell $pos $extend$issuer_ls180.v:110457$4259 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \Y_WIDTH 64 + connect \A \SHIFT_ROT_sh + connect \Y $extend$issuer_ls180.v:110457$4259_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + cell $pos $extend$issuer_ls180.v:110458$4261 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \Y_WIDTH 64 + connect \A \SHIFT_ROT_SH32 + connect \Y $extend$issuer_ls180.v:110458$4261_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + cell $pos $extend$issuer_ls180.v:110461$4265 + parameter \A_SIGNED 0 + parameter \A_WIDTH 16 + parameter \Y_WIDTH 64 + connect \A \SHIFT_ROT_UI + connect \Y $extend$issuer_ls180.v:110461$4265_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:241" + cell $pos $extend$issuer_ls180.v:110465$4270 + parameter \A_SIGNED 0 + parameter \A_WIDTH 47 + parameter \Y_WIDTH 64 + connect \A \$4 + connect \Y $extend$issuer_ls180.v:110465$4270_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + cell $pos $pos$issuer_ls180.v:110457$4260 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A $extend$issuer_ls180.v:110457$4259_Y + connect \Y $pos$issuer_ls180.v:110457$4260_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + cell $pos $pos$issuer_ls180.v:110458$4262 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A $extend$issuer_ls180.v:110458$4261_Y + connect \Y $pos$issuer_ls180.v:110458$4262_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + cell $pos $pos$issuer_ls180.v:110461$4266 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A $extend$issuer_ls180.v:110461$4265_Y + connect \Y $pos$issuer_ls180.v:110461$4266_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:241" + cell $pos $pos$issuer_ls180.v:110465$4271 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A $extend$issuer_ls180.v:110465$4270_Y + connect \Y $pos$issuer_ls180.v:110465$4271_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:235" + cell $sshl $sshl$issuer_ls180.v:110459$4263 + parameter \A_SIGNED 0 + parameter \A_WIDTH 16 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 47 + connect \A \SHIFT_ROT_SI + connect \B 5'10000 + connect \Y $sshl$issuer_ls180.v:110459$4263_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:245" + cell $sshl $sshl$issuer_ls180.v:110460$4264 + parameter \A_SIGNED 0 + parameter \A_WIDTH 24 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 27 + connect \A \SHIFT_ROT_LI + connect \B 2'10 + connect \Y $sshl$issuer_ls180.v:110460$4264_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:250" + cell $sshl $sshl$issuer_ls180.v:110462$4267 + parameter \A_SIGNED 0 + parameter \A_WIDTH 14 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 17 + connect \A \SHIFT_ROT_BD + connect \B 2'10 + connect \Y $sshl$issuer_ls180.v:110462$4267_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:255" + cell $sshl $sshl$issuer_ls180.v:110463$4268 + parameter \A_SIGNED 0 + parameter \A_WIDTH 14 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 17 + connect \A \SHIFT_ROT_DS + connect \B 2'10 + connect \Y $sshl$issuer_ls180.v:110463$4268_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:241" + cell $sshl $sshl$issuer_ls180.v:110464$4269 + parameter \A_SIGNED 0 + parameter \A_WIDTH 16 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 47 + connect \A \ui + connect \B 5'10000 + connect \Y $sshl$issuer_ls180.v:110464$4269_Y + end + attribute \src "issuer_ls180.v:110379.7-110379.20" + process $proc$issuer_ls180.v:110379$4280 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "issuer_ls180.v:110467.3-110513.6" + process $proc$issuer_ls180.v:110467$4272 + assign { } { } + assign { } { } + assign $0\imm_b[63:0] $1\imm_b[63:0] + attribute \src "issuer_ls180.v:110468.5-110468.29" + switch \initial + attribute \src "issuer_ls180.v:110468.9-110468.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:224" + switch \sel_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0010 + assign { } { } + assign $1\imm_b[63:0] \$1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0011 + assign { } { } + assign $1\imm_b[63:0] { \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si } + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0101 + assign { } { } + assign $1\imm_b[63:0] { \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi } + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0100 + assign { } { } + assign $1\imm_b[63:0] \$3 + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\imm_b[63:0] { \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li } + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $1\imm_b[63:0] { \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd } + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\imm_b[63:0] { \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds } + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'1001 + assign { } { } + assign $1\imm_b[63:0] \$7 + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'1010 + assign { } { } + assign $1\imm_b[63:0] \$9 + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'1011 + assign { } { } + assign $1\imm_b[63:0] \$11 + case + assign $1\imm_b[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \imm_b $0\imm_b[63:0] + end + attribute \src "issuer_ls180.v:110514.3-110560.6" + process $proc$issuer_ls180.v:110514$4273 + assign { } { } + assign { } { } + assign $0\imm_b_ok[0:0] $1\imm_b_ok[0:0] + attribute \src "issuer_ls180.v:110515.5-110515.29" + switch \initial + attribute \src "issuer_ls180.v:110515.9-110515.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:224" + switch \sel_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0010 + assign { } { } + assign $1\imm_b_ok[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0011 + assign { } { } + assign $1\imm_b_ok[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0101 + assign { } { } + assign $1\imm_b_ok[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0100 + assign { } { } + assign $1\imm_b_ok[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\imm_b_ok[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $1\imm_b_ok[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\imm_b_ok[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'1001 + assign { } { } + assign $1\imm_b_ok[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'1010 + assign { } { } + assign $1\imm_b_ok[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'1011 + assign { } { } + assign $1\imm_b_ok[0:0] 1'1 + case + assign $1\imm_b_ok[0:0] 1'0 + end + sync always + update \imm_b_ok $0\imm_b_ok[0:0] + end + attribute \src "issuer_ls180.v:110561.3-110571.6" + process $proc$issuer_ls180.v:110561$4274 + assign { } { } + assign { } { } + assign $0\si[15:0] $1\si[15:0] + attribute \src "issuer_ls180.v:110562.5-110562.29" + switch \initial + attribute \src "issuer_ls180.v:110562.9-110562.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:224" + switch \sel_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0011 + assign { } { } + assign $1\si[15:0] \SHIFT_ROT_SI + case + assign $1\si[15:0] 16'0000000000000000 + end + sync always + update \si $0\si[15:0] + end + attribute \src "issuer_ls180.v:110572.3-110582.6" + process $proc$issuer_ls180.v:110572$4275 + assign { } { } + assign { } { } + assign $0\si_hi[31:0] $1\si_hi[31:0] + attribute \src "issuer_ls180.v:110573.5-110573.29" + switch \initial + attribute \src "issuer_ls180.v:110573.9-110573.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:224" + switch \sel_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0101 + assign { } { } + assign $1\si_hi[31:0] \$13 [31:0] + case + assign $1\si_hi[31:0] 0 + end + sync always + update \si_hi $0\si_hi[31:0] + end + attribute \src "issuer_ls180.v:110583.3-110593.6" + process $proc$issuer_ls180.v:110583$4276 + assign { } { } + assign { } { } + assign $0\ui[15:0] $1\ui[15:0] + attribute \src "issuer_ls180.v:110584.5-110584.29" + switch \initial + attribute \src "issuer_ls180.v:110584.9-110584.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:224" + switch \sel_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0100 + assign { } { } + assign $1\ui[15:0] \SHIFT_ROT_UI + case + assign $1\ui[15:0] 16'0000000000000000 + end + sync always + update \ui $0\ui[15:0] + end + attribute \src "issuer_ls180.v:110594.3-110604.6" + process $proc$issuer_ls180.v:110594$4277 + assign { } { } + assign { } { } + assign $0\li[25:0] $1\li[25:0] + attribute \src "issuer_ls180.v:110595.5-110595.29" + switch \initial + attribute \src "issuer_ls180.v:110595.9-110595.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:224" + switch \sel_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\li[25:0] \$16 [25:0] + case + assign $1\li[25:0] 26'00000000000000000000000000 + end + sync always + update \li $0\li[25:0] + end + attribute \src "issuer_ls180.v:110605.3-110615.6" + process $proc$issuer_ls180.v:110605$4278 + assign { } { } + assign { } { } + assign $0\bd[15:0] $1\bd[15:0] + attribute \src "issuer_ls180.v:110606.5-110606.29" + switch \initial + attribute \src "issuer_ls180.v:110606.9-110606.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:224" + switch \sel_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $1\bd[15:0] \$19 [15:0] + case + assign $1\bd[15:0] 16'0000000000000000 + end + sync always + update \bd $0\bd[15:0] + end + attribute \src "issuer_ls180.v:110616.3-110626.6" + process $proc$issuer_ls180.v:110616$4279 + assign { } { } + assign { } { } + assign $0\ds[15:0] $1\ds[15:0] + attribute \src "issuer_ls180.v:110617.5-110617.29" + switch \initial + attribute \src "issuer_ls180.v:110617.9-110617.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:224" + switch \sel_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\ds[15:0] \$22 [15:0] + case + assign $1\ds[15:0] 16'0000000000000000 + end + sync always + update \ds $0\ds[15:0] + end + connect \$9 $pos$issuer_ls180.v:110457$4260_Y + connect \$11 $pos$issuer_ls180.v:110458$4262_Y + connect \$14 $sshl$issuer_ls180.v:110459$4263_Y + connect \$17 $sshl$issuer_ls180.v:110460$4264_Y + connect \$1 $pos$issuer_ls180.v:110461$4266_Y + connect \$20 $sshl$issuer_ls180.v:110462$4267_Y + connect \$23 $sshl$issuer_ls180.v:110463$4268_Y + connect \$4 $sshl$issuer_ls180.v:110464$4269_Y + connect \$3 $pos$issuer_ls180.v:110465$4271_Y + connect \$7 64'1111111111111111111111111111111111111111111111111111111111111111 + connect \$13 \$14 + connect \$16 \$17 + connect \$19 \$20 + connect \$22 \$23 +end +attribute \src "issuer_ls180.v:110635.1-110888.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.dec_LDST.dec_bi" +attribute \generator "nMigen" +module \dec_bi$201 + attribute \src "issuer_ls180.v:110862.3-110872.6" + wire width 16 $0\bd[15:0] + attribute \src "issuer_ls180.v:110873.3-110883.6" + wire width 16 $0\ds[15:0] + attribute \src "issuer_ls180.v:110724.3-110770.6" + wire width 64 $0\imm_b[63:0] + attribute \src "issuer_ls180.v:110771.3-110817.6" + wire $0\imm_b_ok[0:0] + attribute \src "issuer_ls180.v:110636.7-110636.20" + wire $0\initial[0:0] + attribute \src "issuer_ls180.v:110851.3-110861.6" + wire width 26 $0\li[25:0] + attribute \src "issuer_ls180.v:110818.3-110828.6" + wire width 16 $0\si[15:0] + attribute \src "issuer_ls180.v:110829.3-110839.6" + wire width 32 $0\si_hi[31:0] + attribute \src "issuer_ls180.v:110840.3-110850.6" + wire width 16 $0\ui[15:0] + attribute \src "issuer_ls180.v:110862.3-110872.6" + wire width 16 $1\bd[15:0] + attribute \src "issuer_ls180.v:110873.3-110883.6" + wire width 16 $1\ds[15:0] + attribute \src "issuer_ls180.v:110724.3-110770.6" + wire width 64 $1\imm_b[63:0] + attribute \src "issuer_ls180.v:110771.3-110817.6" + wire $1\imm_b_ok[0:0] + attribute \src "issuer_ls180.v:110851.3-110861.6" + wire width 26 $1\li[25:0] + attribute \src "issuer_ls180.v:110818.3-110828.6" + wire width 16 $1\si[15:0] + attribute \src "issuer_ls180.v:110829.3-110839.6" + wire width 32 $1\si_hi[31:0] + attribute \src "issuer_ls180.v:110840.3-110850.6" + wire width 16 $1\ui[15:0] + attribute \src "issuer_ls180.v:110714.17-110714.105" + wire width 64 $extend$issuer_ls180.v:110714$4281_Y + attribute \src "issuer_ls180.v:110715.18-110715.108" + wire width 64 $extend$issuer_ls180.v:110715$4283_Y + attribute \src "issuer_ls180.v:110718.17-110718.105" + wire width 64 $extend$issuer_ls180.v:110718$4287_Y + attribute \src "issuer_ls180.v:110722.17-110722.102" + wire width 64 $extend$issuer_ls180.v:110722$4292_Y + attribute \src "issuer_ls180.v:110714.17-110714.105" + wire width 64 $pos$issuer_ls180.v:110714$4282_Y + attribute \src "issuer_ls180.v:110715.18-110715.108" + wire width 64 $pos$issuer_ls180.v:110715$4284_Y + attribute \src "issuer_ls180.v:110718.17-110718.105" + wire width 64 $pos$issuer_ls180.v:110718$4288_Y + attribute \src "issuer_ls180.v:110722.17-110722.102" + wire width 64 $pos$issuer_ls180.v:110722$4293_Y + attribute \src "issuer_ls180.v:110716.18-110716.115" + wire width 47 $sshl$issuer_ls180.v:110716$4285_Y + attribute \src "issuer_ls180.v:110717.18-110717.114" + wire width 27 $sshl$issuer_ls180.v:110717$4286_Y + attribute \src "issuer_ls180.v:110719.18-110719.114" + wire width 17 $sshl$issuer_ls180.v:110719$4289_Y + attribute \src "issuer_ls180.v:110720.18-110720.114" + wire width 17 $sshl$issuer_ls180.v:110720$4290_Y + attribute \src "issuer_ls180.v:110721.17-110721.109" + wire width 47 $sshl$issuer_ls180.v:110721$4291_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 64 \$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 64 \$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:235" + wire width 47 \$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:235" + wire width 47 \$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:245" + wire width 27 \$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:245" + wire width 27 \$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:250" + wire width 17 \$19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:250" + wire width 17 \$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:255" + wire width 17 \$22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:255" + wire width 17 \$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:241" + wire width 64 \$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:241" + wire width 47 \$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:259" + wire width 64 \$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 64 \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 14 input 8 \LDST_BD + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 14 input 9 \LDST_DS + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 24 input 7 \LDST_LI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 input 5 \LDST_SH32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 16 input 3 \LDST_SI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 16 input 4 \LDST_UI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 6 input 6 \LDST_sh + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:249" + wire width 16 \bd + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:254" + wire width 16 \ds + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 output 1 \imm_b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 2 \imm_b_ok + attribute \src "issuer_ls180.v:110636.7-110636.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" + wire width 26 \li + attribute \enum_base_type "In2Sel" + attribute \enum_value_0000 "NONE" + attribute \enum_value_0001 "RB" + attribute \enum_value_0010 "CONST_UI" + attribute \enum_value_0011 "CONST_SI" + attribute \enum_value_0100 "CONST_UI_HI" + attribute \enum_value_0101 "CONST_SI_HI" + attribute \enum_value_0110 "CONST_LI" + attribute \enum_value_0111 "CONST_BD" + attribute \enum_value_1000 "CONST_DS" + attribute \enum_value_1001 "CONST_M1" + attribute \enum_value_1010 "CONST_SH" + attribute \enum_value_1011 "CONST_SH32" + attribute \enum_value_1100 "SPR" + attribute \enum_value_1101 "RS" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:216" + wire width 4 input 10 \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:229" + wire width 16 \si + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:234" + wire width 32 \si_hi + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:239" + wire width 16 \ui + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + cell $pos $extend$issuer_ls180.v:110714$4281 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \Y_WIDTH 64 + connect \A \LDST_sh + connect \Y $extend$issuer_ls180.v:110714$4281_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + cell $pos $extend$issuer_ls180.v:110715$4283 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \Y_WIDTH 64 + connect \A \LDST_SH32 + connect \Y $extend$issuer_ls180.v:110715$4283_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + cell $pos $extend$issuer_ls180.v:110718$4287 + parameter \A_SIGNED 0 + parameter \A_WIDTH 16 + parameter \Y_WIDTH 64 + connect \A \LDST_UI + connect \Y $extend$issuer_ls180.v:110718$4287_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:241" + cell $pos $extend$issuer_ls180.v:110722$4292 + parameter \A_SIGNED 0 + parameter \A_WIDTH 47 + parameter \Y_WIDTH 64 + connect \A \$4 + connect \Y $extend$issuer_ls180.v:110722$4292_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + cell $pos $pos$issuer_ls180.v:110714$4282 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A $extend$issuer_ls180.v:110714$4281_Y + connect \Y $pos$issuer_ls180.v:110714$4282_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + cell $pos $pos$issuer_ls180.v:110715$4284 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A $extend$issuer_ls180.v:110715$4283_Y + connect \Y $pos$issuer_ls180.v:110715$4284_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + cell $pos $pos$issuer_ls180.v:110718$4288 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A $extend$issuer_ls180.v:110718$4287_Y + connect \Y $pos$issuer_ls180.v:110718$4288_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:241" + cell $pos $pos$issuer_ls180.v:110722$4293 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A $extend$issuer_ls180.v:110722$4292_Y + connect \Y $pos$issuer_ls180.v:110722$4293_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:235" + cell $sshl $sshl$issuer_ls180.v:110716$4285 + parameter \A_SIGNED 0 + parameter \A_WIDTH 16 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 47 + connect \A \LDST_SI + connect \B 5'10000 + connect \Y $sshl$issuer_ls180.v:110716$4285_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:245" + cell $sshl $sshl$issuer_ls180.v:110717$4286 + parameter \A_SIGNED 0 + parameter \A_WIDTH 24 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 27 + connect \A \LDST_LI + connect \B 2'10 + connect \Y $sshl$issuer_ls180.v:110717$4286_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:250" + cell $sshl $sshl$issuer_ls180.v:110719$4289 + parameter \A_SIGNED 0 + parameter \A_WIDTH 14 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 17 + connect \A \LDST_BD + connect \B 2'10 + connect \Y $sshl$issuer_ls180.v:110719$4289_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:255" + cell $sshl $sshl$issuer_ls180.v:110720$4290 + parameter \A_SIGNED 0 + parameter \A_WIDTH 14 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 17 + connect \A \LDST_DS + connect \B 2'10 + connect \Y $sshl$issuer_ls180.v:110720$4290_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:241" + cell $sshl $sshl$issuer_ls180.v:110721$4291 + parameter \A_SIGNED 0 + parameter \A_WIDTH 16 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 47 + connect \A \ui + connect \B 5'10000 + connect \Y $sshl$issuer_ls180.v:110721$4291_Y + end + attribute \src "issuer_ls180.v:110636.7-110636.20" + process $proc$issuer_ls180.v:110636$4302 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "issuer_ls180.v:110724.3-110770.6" + process $proc$issuer_ls180.v:110724$4294 + assign { } { } + assign { } { } + assign $0\imm_b[63:0] $1\imm_b[63:0] + attribute \src "issuer_ls180.v:110725.5-110725.29" + switch \initial + attribute \src "issuer_ls180.v:110725.9-110725.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:224" + switch \sel_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0010 + assign { } { } + assign $1\imm_b[63:0] \$1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0011 + assign { } { } + assign $1\imm_b[63:0] { \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si } + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0101 + assign { } { } + assign $1\imm_b[63:0] { \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi } + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0100 + assign { } { } + assign $1\imm_b[63:0] \$3 + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\imm_b[63:0] { \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li } + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $1\imm_b[63:0] { \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd } + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\imm_b[63:0] { \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds } + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'1001 + assign { } { } + assign $1\imm_b[63:0] \$7 + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'1010 + assign { } { } + assign $1\imm_b[63:0] \$9 + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'1011 + assign { } { } + assign $1\imm_b[63:0] \$11 + case + assign $1\imm_b[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \imm_b $0\imm_b[63:0] + end + attribute \src "issuer_ls180.v:110771.3-110817.6" + process $proc$issuer_ls180.v:110771$4295 + assign { } { } + assign { } { } + assign $0\imm_b_ok[0:0] $1\imm_b_ok[0:0] + attribute \src "issuer_ls180.v:110772.5-110772.29" + switch \initial + attribute \src "issuer_ls180.v:110772.9-110772.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:224" + switch \sel_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0010 + assign { } { } + assign $1\imm_b_ok[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0011 + assign { } { } + assign $1\imm_b_ok[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0101 + assign { } { } + assign $1\imm_b_ok[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0100 + assign { } { } + assign $1\imm_b_ok[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\imm_b_ok[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $1\imm_b_ok[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\imm_b_ok[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'1001 + assign { } { } + assign $1\imm_b_ok[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'1010 + assign { } { } + assign $1\imm_b_ok[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'1011 + assign { } { } + assign $1\imm_b_ok[0:0] 1'1 + case + assign $1\imm_b_ok[0:0] 1'0 + end + sync always + update \imm_b_ok $0\imm_b_ok[0:0] + end + attribute \src "issuer_ls180.v:110818.3-110828.6" + process $proc$issuer_ls180.v:110818$4296 + assign { } { } + assign { } { } + assign $0\si[15:0] $1\si[15:0] + attribute \src "issuer_ls180.v:110819.5-110819.29" + switch \initial + attribute \src "issuer_ls180.v:110819.9-110819.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:224" + switch \sel_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0011 + assign { } { } + assign $1\si[15:0] \LDST_SI + case + assign $1\si[15:0] 16'0000000000000000 + end + sync always + update \si $0\si[15:0] + end + attribute \src "issuer_ls180.v:110829.3-110839.6" + process $proc$issuer_ls180.v:110829$4297 + assign { } { } + assign { } { } + assign $0\si_hi[31:0] $1\si_hi[31:0] + attribute \src "issuer_ls180.v:110830.5-110830.29" + switch \initial + attribute \src "issuer_ls180.v:110830.9-110830.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:224" + switch \sel_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0101 + assign { } { } + assign $1\si_hi[31:0] \$13 [31:0] + case + assign $1\si_hi[31:0] 0 + end + sync always + update \si_hi $0\si_hi[31:0] + end + attribute \src "issuer_ls180.v:110840.3-110850.6" + process $proc$issuer_ls180.v:110840$4298 + assign { } { } + assign { } { } + assign $0\ui[15:0] $1\ui[15:0] + attribute \src "issuer_ls180.v:110841.5-110841.29" + switch \initial + attribute \src "issuer_ls180.v:110841.9-110841.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:224" + switch \sel_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0100 + assign { } { } + assign $1\ui[15:0] \LDST_UI + case + assign $1\ui[15:0] 16'0000000000000000 + end + sync always + update \ui $0\ui[15:0] + end + attribute \src "issuer_ls180.v:110851.3-110861.6" + process $proc$issuer_ls180.v:110851$4299 + assign { } { } + assign { } { } + assign $0\li[25:0] $1\li[25:0] + attribute \src "issuer_ls180.v:110852.5-110852.29" + switch \initial + attribute \src "issuer_ls180.v:110852.9-110852.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:224" + switch \sel_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $1\li[25:0] \$16 [25:0] + case + assign $1\li[25:0] 26'00000000000000000000000000 + end + sync always + update \li $0\li[25:0] + end + attribute \src "issuer_ls180.v:110862.3-110872.6" + process $proc$issuer_ls180.v:110862$4300 + assign { } { } + assign { } { } + assign $0\bd[15:0] $1\bd[15:0] + attribute \src "issuer_ls180.v:110863.5-110863.29" + switch \initial + attribute \src "issuer_ls180.v:110863.9-110863.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:224" + switch \sel_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $1\bd[15:0] \$19 [15:0] + case + assign $1\bd[15:0] 16'0000000000000000 + end + sync always + update \bd $0\bd[15:0] + end + attribute \src "issuer_ls180.v:110873.3-110883.6" + process $proc$issuer_ls180.v:110873$4301 + assign { } { } + assign { } { } + assign $0\ds[15:0] $1\ds[15:0] + attribute \src "issuer_ls180.v:110874.5-110874.29" + switch \initial + attribute \src "issuer_ls180.v:110874.9-110874.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:224" + switch \sel_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $1\ds[15:0] \$22 [15:0] + case + assign $1\ds[15:0] 16'0000000000000000 + end + sync always + update \ds $0\ds[15:0] + end + connect \$9 $pos$issuer_ls180.v:110714$4282_Y + connect \$11 $pos$issuer_ls180.v:110715$4284_Y + connect \$14 $sshl$issuer_ls180.v:110716$4285_Y + connect \$17 $sshl$issuer_ls180.v:110717$4286_Y + connect \$1 $pos$issuer_ls180.v:110718$4288_Y + connect \$20 $sshl$issuer_ls180.v:110719$4289_Y + connect \$23 $sshl$issuer_ls180.v:110720$4290_Y + connect \$4 $sshl$issuer_ls180.v:110721$4291_Y + connect \$3 $pos$issuer_ls180.v:110722$4293_Y + connect \$7 64'1111111111111111111111111111111111111111111111111111111111111111 + connect \$13 \$14 + connect \$16 \$17 + connect \$19 \$20 + connect \$22 \$23 +end +attribute \src "issuer_ls180.v:110892.1-110940.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.dec2.dec_c" +attribute \generator "nMigen" +module \dec_c + attribute \src "issuer_ls180.v:110893.7-110893.20" + wire $0\initial[0:0] + attribute \src "issuer_ls180.v:110910.3-110924.6" + wire width 5 $0\reg_c[4:0] + attribute \src "issuer_ls180.v:110925.3-110939.6" + wire $0\reg_c_ok[0:0] + attribute \src "issuer_ls180.v:110910.3-110924.6" + wire width 5 $1\reg_c[4:0] + attribute \src "issuer_ls180.v:110925.3-110939.6" + wire $1\reg_c_ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 input 4 \RB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 input 3 \RS + attribute \src "issuer_ls180.v:110893.7-110893.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 5 output 1 \reg_c + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 2 \reg_c_ok + attribute \enum_base_type "In3Sel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RS" + attribute \enum_value_10 "RB" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:279" + wire width 2 input 5 \sel_in + attribute \src "issuer_ls180.v:110893.7-110893.20" + process $proc$issuer_ls180.v:110893$4305 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "issuer_ls180.v:110910.3-110924.6" + process $proc$issuer_ls180.v:110910$4303 + assign { } { } + assign { } { } + assign $0\reg_c[4:0] $1\reg_c[4:0] + attribute \src "issuer_ls180.v:110911.5-110911.29" + switch \initial + attribute \src "issuer_ls180.v:110911.9-110911.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:288" + switch \sel_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\reg_c[4:0] \RB + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\reg_c[4:0] \RS + case + assign $1\reg_c[4:0] 5'00000 + end + sync always + update \reg_c $0\reg_c[4:0] + end + attribute \src "issuer_ls180.v:110925.3-110939.6" + process $proc$issuer_ls180.v:110925$4304 + assign { } { } + assign { } { } + assign $0\reg_c_ok[0:0] $1\reg_c_ok[0:0] + attribute \src "issuer_ls180.v:110926.5-110926.29" + switch \initial + attribute \src "issuer_ls180.v:110926.9-110926.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:288" + switch \sel_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\reg_c_ok[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\reg_c_ok[0:0] 1'1 + case + assign $1\reg_c_ok[0:0] 1'0 + end + sync always + update \reg_c_ok $0\reg_c_ok[0:0] + end +end +attribute \src "issuer_ls180.v:110944.1-111241.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.dec_ALU.dec_cr_in" +attribute \generator "nMigen" +module \dec_cr_in + attribute \src "issuer_ls180.v:111135.3-111161.6" + wire width 3 $0\cr_bitfield[2:0] + attribute \src "issuer_ls180.v:111162.3-111172.6" + wire width 3 $0\cr_bitfield_b[2:0] + attribute \src "issuer_ls180.v:111113.3-111123.6" + wire $0\cr_bitfield_b_ok[0:0] + attribute \src "issuer_ls180.v:111173.3-111183.6" + wire width 3 $0\cr_bitfield_o[2:0] + attribute \src "issuer_ls180.v:111184.3-111194.6" + wire $0\cr_bitfield_o_ok[0:0] + attribute \src "issuer_ls180.v:111086.3-111112.6" + wire $0\cr_bitfield_ok[0:0] + attribute \src "issuer_ls180.v:111222.3-111240.6" + wire width 8 $0\cr_fxm[7:0] + attribute \src "issuer_ls180.v:111124.3-111134.6" + wire $0\cr_fxm_ok[0:0] + attribute \src "issuer_ls180.v:110945.7-110945.20" + wire $0\initial[0:0] + attribute \src "issuer_ls180.v:111195.3-111205.6" + wire $0\move_one[0:0] + attribute \src "issuer_ls180.v:111206.3-111221.6" + wire width 8 $0\ppick_i[7:0] + attribute \src "issuer_ls180.v:111135.3-111161.6" + wire width 3 $1\cr_bitfield[2:0] + attribute \src "issuer_ls180.v:111162.3-111172.6" + wire width 3 $1\cr_bitfield_b[2:0] + attribute \src "issuer_ls180.v:111113.3-111123.6" + wire $1\cr_bitfield_b_ok[0:0] + attribute \src "issuer_ls180.v:111173.3-111183.6" + wire width 3 $1\cr_bitfield_o[2:0] + attribute \src "issuer_ls180.v:111184.3-111194.6" + wire $1\cr_bitfield_o_ok[0:0] + attribute \src "issuer_ls180.v:111086.3-111112.6" + wire $1\cr_bitfield_ok[0:0] + attribute \src "issuer_ls180.v:111222.3-111240.6" + wire width 8 $1\cr_fxm[7:0] + attribute \src "issuer_ls180.v:111124.3-111134.6" + wire $1\cr_fxm_ok[0:0] + attribute \src "issuer_ls180.v:111195.3-111205.6" + wire $1\move_one[0:0] + attribute \src "issuer_ls180.v:111206.3-111221.6" + wire width 8 $1\ppick_i[7:0] + attribute \src "issuer_ls180.v:111222.3-111240.6" + wire width 8 $2\cr_fxm[7:0] + attribute \src "issuer_ls180.v:111206.3-111221.6" + wire width 8 $2\ppick_i[7:0] + attribute \src "issuer_ls180.v:111079.17-111079.112" + wire $and$issuer_ls180.v:111079$4307_Y + attribute \src "issuer_ls180.v:111081.17-111081.112" + wire $and$issuer_ls180.v:111081$4309_Y + attribute \src "issuer_ls180.v:111078.17-111078.121" + wire $eq$issuer_ls180.v:111078$4306_Y + attribute \src "issuer_ls180.v:111080.17-111080.121" + wire $eq$issuer_ls180.v:111080$4308_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 input 4 \ALU_BA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 input 3 \ALU_BB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 input 8 \ALU_BC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 input 7 \ALU_BI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 input 5 \ALU_BT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 8 input 6 \ALU_FXM + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 7 input 2 \ALU_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 3 input 9 \X_BFA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 3 \cr_bitfield + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 3 \cr_bitfield_b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \cr_bitfield_b_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 3 \cr_bitfield_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \cr_bitfield_o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \cr_bitfield_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 8 \cr_fxm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \cr_fxm_ok + attribute \src "issuer_ls180.v:110945.7-110945.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:485" + wire width 32 input 10 \insn_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:526" + wire \move_one + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" + wire width 8 \ppick_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" + wire width 8 \ppick_o + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:484" + wire width 3 input 1 \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" + cell $and $and$issuer_ls180.v:111079$4307 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$1 + connect \B \move_one + connect \Y $and$issuer_ls180.v:111079$4307_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" + cell $and $and$issuer_ls180.v:111081$4309 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$5 + connect \B \move_one + connect \Y $and$issuer_ls180.v:111081$4309_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" + cell $eq $eq$issuer_ls180.v:111078$4306 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \ALU_internal_op + connect \B 7'0101101 + connect \Y $eq$issuer_ls180.v:111078$4306_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" + cell $eq $eq$issuer_ls180.v:111080$4308 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \ALU_internal_op + connect \B 7'0101101 + connect \Y $eq$issuer_ls180.v:111080$4308_Y + end + attribute \module_not_derived 1 + attribute \src "issuer_ls180.v:111082.9-111085.4" + cell \ppick \ppick + connect \i \ppick_i + connect \o \ppick_o + end + attribute \src "issuer_ls180.v:110945.7-110945.20" + process $proc$issuer_ls180.v:110945$4320 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "issuer_ls180.v:111086.3-111112.6" + process $proc$issuer_ls180.v:111086$4310 + assign { } { } + assign { } { } + assign $0\cr_bitfield_ok[0:0] $1\cr_bitfield_ok[0:0] + attribute \src "issuer_ls180.v:111087.5-111087.29" + switch \initial + attribute \src "issuer_ls180.v:111087.9-111087.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" + switch \sel_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 3'001 + assign { } { } + assign $1\cr_bitfield_ok[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 3'010 + assign { } { } + assign $1\cr_bitfield_ok[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 3'011 + assign { } { } + assign $1\cr_bitfield_ok[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 3'100 + assign { } { } + assign $1\cr_bitfield_ok[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 3'101 + assign { } { } + assign $1\cr_bitfield_ok[0:0] 1'1 + case + assign $1\cr_bitfield_ok[0:0] 1'0 + end + sync always + update \cr_bitfield_ok $0\cr_bitfield_ok[0:0] + end + attribute \src "issuer_ls180.v:111113.3-111123.6" + process $proc$issuer_ls180.v:111113$4311 + assign { } { } + assign { } { } + assign $0\cr_bitfield_b_ok[0:0] $1\cr_bitfield_b_ok[0:0] + attribute \src "issuer_ls180.v:111114.5-111114.29" + switch \initial + attribute \src "issuer_ls180.v:111114.9-111114.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" + switch \sel_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 3'100 + assign { } { } + assign $1\cr_bitfield_b_ok[0:0] 1'1 + case + assign $1\cr_bitfield_b_ok[0:0] 1'0 + end + sync always + update \cr_bitfield_b_ok $0\cr_bitfield_b_ok[0:0] + end + attribute \src "issuer_ls180.v:111124.3-111134.6" + process $proc$issuer_ls180.v:111124$4312 + assign { } { } + assign { } { } + assign $0\cr_fxm_ok[0:0] $1\cr_fxm_ok[0:0] + attribute \src "issuer_ls180.v:111125.5-111125.29" + switch \initial + attribute \src "issuer_ls180.v:111125.9-111125.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" + switch \sel_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 3'110 + assign { } { } + assign $1\cr_fxm_ok[0:0] 1'1 + case + assign $1\cr_fxm_ok[0:0] 1'0 + end + sync always + update \cr_fxm_ok $0\cr_fxm_ok[0:0] + end + attribute \src "issuer_ls180.v:111135.3-111161.6" + process $proc$issuer_ls180.v:111135$4313 + assign { } { } + assign { } { } + assign $0\cr_bitfield[2:0] $1\cr_bitfield[2:0] + attribute \src "issuer_ls180.v:111136.5-111136.29" + switch \initial + attribute \src "issuer_ls180.v:111136.9-111136.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" + switch \sel_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 3'001 + assign { } { } + assign $1\cr_bitfield[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 3'010 + assign { } { } + assign $1\cr_bitfield[2:0] \ALU_BI [4:2] + attribute \src "issuer_ls180.v:0.0-0.0" + case 3'011 + assign { } { } + assign $1\cr_bitfield[2:0] \X_BFA + attribute \src "issuer_ls180.v:0.0-0.0" + case 3'100 + assign { } { } + assign $1\cr_bitfield[2:0] \ALU_BA [4:2] + attribute \src "issuer_ls180.v:0.0-0.0" + case 3'101 + assign { } { } + assign $1\cr_bitfield[2:0] \ALU_BC [4:2] + case + assign $1\cr_bitfield[2:0] 3'000 + end + sync always + update \cr_bitfield $0\cr_bitfield[2:0] + end + attribute \src "issuer_ls180.v:111162.3-111172.6" + process $proc$issuer_ls180.v:111162$4314 + assign { } { } + assign { } { } + assign $0\cr_bitfield_b[2:0] $1\cr_bitfield_b[2:0] + attribute \src "issuer_ls180.v:111163.5-111163.29" + switch \initial + attribute \src "issuer_ls180.v:111163.9-111163.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" + switch \sel_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 3'100 + assign { } { } + assign $1\cr_bitfield_b[2:0] \ALU_BB [4:2] + case + assign $1\cr_bitfield_b[2:0] 3'000 + end + sync always + update \cr_bitfield_b $0\cr_bitfield_b[2:0] + end + attribute \src "issuer_ls180.v:111173.3-111183.6" + process $proc$issuer_ls180.v:111173$4315 + assign { } { } + assign { } { } + assign $0\cr_bitfield_o[2:0] $1\cr_bitfield_o[2:0] + attribute \src "issuer_ls180.v:111174.5-111174.29" + switch \initial + attribute \src "issuer_ls180.v:111174.9-111174.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" + switch \sel_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 3'100 + assign { } { } + assign $1\cr_bitfield_o[2:0] \ALU_BT [4:2] + case + assign $1\cr_bitfield_o[2:0] 3'000 + end + sync always + update \cr_bitfield_o $0\cr_bitfield_o[2:0] + end + attribute \src "issuer_ls180.v:111184.3-111194.6" + process $proc$issuer_ls180.v:111184$4316 + assign { } { } + assign { } { } + assign $0\cr_bitfield_o_ok[0:0] $1\cr_bitfield_o_ok[0:0] + attribute \src "issuer_ls180.v:111185.5-111185.29" + switch \initial + attribute \src "issuer_ls180.v:111185.9-111185.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" + switch \sel_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 3'100 + assign { } { } + assign $1\cr_bitfield_o_ok[0:0] 1'1 + case + assign $1\cr_bitfield_o_ok[0:0] 1'0 + end + sync always + update \cr_bitfield_o_ok $0\cr_bitfield_o_ok[0:0] + end + attribute \src "issuer_ls180.v:111195.3-111205.6" + process $proc$issuer_ls180.v:111195$4317 + assign { } { } + assign { } { } + assign $0\move_one[0:0] $1\move_one[0:0] + attribute \src "issuer_ls180.v:111196.5-111196.29" + switch \initial + attribute \src "issuer_ls180.v:111196.9-111196.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" + switch \sel_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 3'110 + assign { } { } + assign $1\move_one[0:0] \insn_in [20] + case + assign $1\move_one[0:0] 1'0 + end + sync always + update \move_one $0\move_one[0:0] + end + attribute \src "issuer_ls180.v:111206.3-111221.6" + process $proc$issuer_ls180.v:111206$4318 + assign { } { } + assign { } { } + assign $0\ppick_i[7:0] $1\ppick_i[7:0] + attribute \src "issuer_ls180.v:111207.5-111207.29" + switch \initial + attribute \src "issuer_ls180.v:111207.9-111207.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" + switch \sel_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 3'110 + assign { } { } + assign $1\ppick_i[7:0] $2\ppick_i[7:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" + switch \$3 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\ppick_i[7:0] \ALU_FXM + case + assign $2\ppick_i[7:0] 8'00000000 + end + case + assign $1\ppick_i[7:0] 8'00000000 + end + sync always + update \ppick_i $0\ppick_i[7:0] + end + attribute \src "issuer_ls180.v:111222.3-111240.6" + process $proc$issuer_ls180.v:111222$4319 + assign { } { } + assign { } { } + assign $0\cr_fxm[7:0] $1\cr_fxm[7:0] + attribute \src "issuer_ls180.v:111223.5-111223.29" + switch \initial + attribute \src "issuer_ls180.v:111223.9-111223.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" + switch \sel_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 3'110 + assign { } { } + assign $1\cr_fxm[7:0] $2\cr_fxm[7:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" + switch \$7 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\cr_fxm[7:0] \ppick_o + attribute \src "issuer_ls180.v:0.0-0.0" + case + assign { } { } + assign $2\cr_fxm[7:0] 8'11111111 + end + case + assign $1\cr_fxm[7:0] 8'00000000 + end + sync always + update \cr_fxm $0\cr_fxm[7:0] + end + connect \$1 $eq$issuer_ls180.v:111078$4306_Y + connect \$3 $and$issuer_ls180.v:111079$4307_Y + connect \$5 $eq$issuer_ls180.v:111080$4308_Y + connect \$7 $and$issuer_ls180.v:111081$4309_Y +end +attribute \src "issuer_ls180.v:111245.1-111542.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.dec_CR.dec_cr_in" +attribute \generator "nMigen" +module \dec_cr_in$140 + attribute \src "issuer_ls180.v:111436.3-111462.6" + wire width 3 $0\cr_bitfield[2:0] + attribute \src "issuer_ls180.v:111463.3-111473.6" + wire width 3 $0\cr_bitfield_b[2:0] + attribute \src "issuer_ls180.v:111414.3-111424.6" + wire $0\cr_bitfield_b_ok[0:0] + attribute \src "issuer_ls180.v:111474.3-111484.6" + wire width 3 $0\cr_bitfield_o[2:0] + attribute \src "issuer_ls180.v:111485.3-111495.6" + wire $0\cr_bitfield_o_ok[0:0] + attribute \src "issuer_ls180.v:111387.3-111413.6" + wire $0\cr_bitfield_ok[0:0] + attribute \src "issuer_ls180.v:111523.3-111541.6" + wire width 8 $0\cr_fxm[7:0] + attribute \src "issuer_ls180.v:111425.3-111435.6" + wire $0\cr_fxm_ok[0:0] + attribute \src "issuer_ls180.v:111246.7-111246.20" + wire $0\initial[0:0] + attribute \src "issuer_ls180.v:111496.3-111506.6" + wire $0\move_one[0:0] + attribute \src "issuer_ls180.v:111507.3-111522.6" + wire width 8 $0\ppick_i[7:0] + attribute \src "issuer_ls180.v:111436.3-111462.6" + wire width 3 $1\cr_bitfield[2:0] + attribute \src "issuer_ls180.v:111463.3-111473.6" + wire width 3 $1\cr_bitfield_b[2:0] + attribute \src "issuer_ls180.v:111414.3-111424.6" + wire $1\cr_bitfield_b_ok[0:0] + attribute \src "issuer_ls180.v:111474.3-111484.6" + wire width 3 $1\cr_bitfield_o[2:0] + attribute \src "issuer_ls180.v:111485.3-111495.6" + wire $1\cr_bitfield_o_ok[0:0] + attribute \src "issuer_ls180.v:111387.3-111413.6" + wire $1\cr_bitfield_ok[0:0] + attribute \src "issuer_ls180.v:111523.3-111541.6" + wire width 8 $1\cr_fxm[7:0] + attribute \src "issuer_ls180.v:111425.3-111435.6" + wire $1\cr_fxm_ok[0:0] + attribute \src "issuer_ls180.v:111496.3-111506.6" + wire $1\move_one[0:0] + attribute \src "issuer_ls180.v:111507.3-111522.6" + wire width 8 $1\ppick_i[7:0] + attribute \src "issuer_ls180.v:111523.3-111541.6" + wire width 8 $2\cr_fxm[7:0] + attribute \src "issuer_ls180.v:111507.3-111522.6" + wire width 8 $2\ppick_i[7:0] + attribute \src "issuer_ls180.v:111380.17-111380.112" + wire $and$issuer_ls180.v:111380$4322_Y + attribute \src "issuer_ls180.v:111382.17-111382.112" + wire $and$issuer_ls180.v:111382$4324_Y + attribute \src "issuer_ls180.v:111379.17-111379.120" + wire $eq$issuer_ls180.v:111379$4321_Y + attribute \src "issuer_ls180.v:111381.17-111381.120" + wire $eq$issuer_ls180.v:111381$4323_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 input 4 \CR_BA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 input 3 \CR_BB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 input 8 \CR_BC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 input 7 \CR_BI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 input 5 \CR_BT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 8 input 6 \CR_FXM + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 7 input 2 \CR_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 3 input 9 \X_BFA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 3 \cr_bitfield + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 3 \cr_bitfield_b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \cr_bitfield_b_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 3 \cr_bitfield_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \cr_bitfield_o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \cr_bitfield_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 8 \cr_fxm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \cr_fxm_ok + attribute \src "issuer_ls180.v:111246.7-111246.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:485" + wire width 32 input 10 \insn_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:526" + wire \move_one + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" + wire width 8 \ppick_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" + wire width 8 \ppick_o + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:484" + wire width 3 input 1 \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" + cell $and $and$issuer_ls180.v:111380$4322 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$1 + connect \B \move_one + connect \Y $and$issuer_ls180.v:111380$4322_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" + cell $and $and$issuer_ls180.v:111382$4324 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$5 + connect \B \move_one + connect \Y $and$issuer_ls180.v:111382$4324_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" + cell $eq $eq$issuer_ls180.v:111379$4321 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \CR_internal_op + connect \B 7'0101101 + connect \Y $eq$issuer_ls180.v:111379$4321_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" + cell $eq $eq$issuer_ls180.v:111381$4323 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \CR_internal_op + connect \B 7'0101101 + connect \Y $eq$issuer_ls180.v:111381$4323_Y + end + attribute \module_not_derived 1 + attribute \src "issuer_ls180.v:111383.15-111386.4" + cell \ppick$141 \ppick + connect \i \ppick_i + connect \o \ppick_o + end + attribute \src "issuer_ls180.v:111246.7-111246.20" + process $proc$issuer_ls180.v:111246$4335 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "issuer_ls180.v:111387.3-111413.6" + process $proc$issuer_ls180.v:111387$4325 + assign { } { } + assign { } { } + assign $0\cr_bitfield_ok[0:0] $1\cr_bitfield_ok[0:0] + attribute \src "issuer_ls180.v:111388.5-111388.29" + switch \initial + attribute \src "issuer_ls180.v:111388.9-111388.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" + switch \sel_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 3'001 + assign { } { } + assign $1\cr_bitfield_ok[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 3'010 + assign { } { } + assign $1\cr_bitfield_ok[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 3'011 + assign { } { } + assign $1\cr_bitfield_ok[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 3'100 + assign { } { } + assign $1\cr_bitfield_ok[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 3'101 + assign { } { } + assign $1\cr_bitfield_ok[0:0] 1'1 + case + assign $1\cr_bitfield_ok[0:0] 1'0 + end + sync always + update \cr_bitfield_ok $0\cr_bitfield_ok[0:0] + end + attribute \src "issuer_ls180.v:111414.3-111424.6" + process $proc$issuer_ls180.v:111414$4326 + assign { } { } + assign { } { } + assign $0\cr_bitfield_b_ok[0:0] $1\cr_bitfield_b_ok[0:0] + attribute \src "issuer_ls180.v:111415.5-111415.29" + switch \initial + attribute \src "issuer_ls180.v:111415.9-111415.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" + switch \sel_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 3'100 + assign { } { } + assign $1\cr_bitfield_b_ok[0:0] 1'1 + case + assign $1\cr_bitfield_b_ok[0:0] 1'0 + end + sync always + update \cr_bitfield_b_ok $0\cr_bitfield_b_ok[0:0] + end + attribute \src "issuer_ls180.v:111425.3-111435.6" + process $proc$issuer_ls180.v:111425$4327 + assign { } { } + assign { } { } + assign $0\cr_fxm_ok[0:0] $1\cr_fxm_ok[0:0] + attribute \src "issuer_ls180.v:111426.5-111426.29" + switch \initial + attribute \src "issuer_ls180.v:111426.9-111426.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" + switch \sel_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 3'110 + assign { } { } + assign $1\cr_fxm_ok[0:0] 1'1 + case + assign $1\cr_fxm_ok[0:0] 1'0 + end + sync always + update \cr_fxm_ok $0\cr_fxm_ok[0:0] + end + attribute \src "issuer_ls180.v:111436.3-111462.6" + process $proc$issuer_ls180.v:111436$4328 + assign { } { } + assign { } { } + assign $0\cr_bitfield[2:0] $1\cr_bitfield[2:0] + attribute \src "issuer_ls180.v:111437.5-111437.29" + switch \initial + attribute \src "issuer_ls180.v:111437.9-111437.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" + switch \sel_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 3'001 + assign { } { } + assign $1\cr_bitfield[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 3'010 + assign { } { } + assign $1\cr_bitfield[2:0] \CR_BI [4:2] + attribute \src "issuer_ls180.v:0.0-0.0" + case 3'011 + assign { } { } + assign $1\cr_bitfield[2:0] \X_BFA + attribute \src "issuer_ls180.v:0.0-0.0" + case 3'100 + assign { } { } + assign $1\cr_bitfield[2:0] \CR_BA [4:2] + attribute \src "issuer_ls180.v:0.0-0.0" + case 3'101 + assign { } { } + assign $1\cr_bitfield[2:0] \CR_BC [4:2] + case + assign $1\cr_bitfield[2:0] 3'000 + end + sync always + update \cr_bitfield $0\cr_bitfield[2:0] + end + attribute \src "issuer_ls180.v:111463.3-111473.6" + process $proc$issuer_ls180.v:111463$4329 + assign { } { } + assign { } { } + assign $0\cr_bitfield_b[2:0] $1\cr_bitfield_b[2:0] + attribute \src "issuer_ls180.v:111464.5-111464.29" + switch \initial + attribute \src "issuer_ls180.v:111464.9-111464.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" + switch \sel_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 3'100 + assign { } { } + assign $1\cr_bitfield_b[2:0] \CR_BB [4:2] + case + assign $1\cr_bitfield_b[2:0] 3'000 + end + sync always + update \cr_bitfield_b $0\cr_bitfield_b[2:0] + end + attribute \src "issuer_ls180.v:111474.3-111484.6" + process $proc$issuer_ls180.v:111474$4330 + assign { } { } + assign { } { } + assign $0\cr_bitfield_o[2:0] $1\cr_bitfield_o[2:0] + attribute \src "issuer_ls180.v:111475.5-111475.29" + switch \initial + attribute \src "issuer_ls180.v:111475.9-111475.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" + switch \sel_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 3'100 + assign { } { } + assign $1\cr_bitfield_o[2:0] \CR_BT [4:2] + case + assign $1\cr_bitfield_o[2:0] 3'000 + end + sync always + update \cr_bitfield_o $0\cr_bitfield_o[2:0] + end + attribute \src "issuer_ls180.v:111485.3-111495.6" + process $proc$issuer_ls180.v:111485$4331 + assign { } { } + assign { } { } + assign $0\cr_bitfield_o_ok[0:0] $1\cr_bitfield_o_ok[0:0] + attribute \src "issuer_ls180.v:111486.5-111486.29" + switch \initial + attribute \src "issuer_ls180.v:111486.9-111486.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" + switch \sel_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 3'100 + assign { } { } + assign $1\cr_bitfield_o_ok[0:0] 1'1 + case + assign $1\cr_bitfield_o_ok[0:0] 1'0 + end + sync always + update \cr_bitfield_o_ok $0\cr_bitfield_o_ok[0:0] + end + attribute \src "issuer_ls180.v:111496.3-111506.6" + process $proc$issuer_ls180.v:111496$4332 + assign { } { } + assign { } { } + assign $0\move_one[0:0] $1\move_one[0:0] + attribute \src "issuer_ls180.v:111497.5-111497.29" + switch \initial + attribute \src "issuer_ls180.v:111497.9-111497.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" + switch \sel_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 3'110 + assign { } { } + assign $1\move_one[0:0] \insn_in [20] + case + assign $1\move_one[0:0] 1'0 + end + sync always + update \move_one $0\move_one[0:0] + end + attribute \src "issuer_ls180.v:111507.3-111522.6" + process $proc$issuer_ls180.v:111507$4333 + assign { } { } + assign { } { } + assign $0\ppick_i[7:0] $1\ppick_i[7:0] + attribute \src "issuer_ls180.v:111508.5-111508.29" + switch \initial + attribute \src "issuer_ls180.v:111508.9-111508.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" + switch \sel_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 3'110 + assign { } { } + assign $1\ppick_i[7:0] $2\ppick_i[7:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" + switch \$3 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\ppick_i[7:0] \CR_FXM + case + assign $2\ppick_i[7:0] 8'00000000 + end + case + assign $1\ppick_i[7:0] 8'00000000 + end + sync always + update \ppick_i $0\ppick_i[7:0] + end + attribute \src "issuer_ls180.v:111523.3-111541.6" + process $proc$issuer_ls180.v:111523$4334 + assign { } { } + assign { } { } + assign $0\cr_fxm[7:0] $1\cr_fxm[7:0] + attribute \src "issuer_ls180.v:111524.5-111524.29" + switch \initial + attribute \src "issuer_ls180.v:111524.9-111524.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" + switch \sel_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 3'110 + assign { } { } + assign $1\cr_fxm[7:0] $2\cr_fxm[7:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" + switch \$7 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\cr_fxm[7:0] \ppick_o + attribute \src "issuer_ls180.v:0.0-0.0" + case + assign { } { } + assign $2\cr_fxm[7:0] 8'11111111 + end + case + assign $1\cr_fxm[7:0] 8'00000000 + end + sync always + update \cr_fxm $0\cr_fxm[7:0] + end + connect \$1 $eq$issuer_ls180.v:111379$4321_Y + connect \$3 $and$issuer_ls180.v:111380$4322_Y + connect \$5 $eq$issuer_ls180.v:111381$4323_Y + connect \$7 $and$issuer_ls180.v:111382$4324_Y +end +attribute \src "issuer_ls180.v:111546.1-111843.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.dec_BRANCH.dec_cr_in" +attribute \generator "nMigen" +module \dec_cr_in$147 + attribute \src "issuer_ls180.v:111737.3-111763.6" + wire width 3 $0\cr_bitfield[2:0] + attribute \src "issuer_ls180.v:111764.3-111774.6" + wire width 3 $0\cr_bitfield_b[2:0] + attribute \src "issuer_ls180.v:111715.3-111725.6" + wire $0\cr_bitfield_b_ok[0:0] + attribute \src "issuer_ls180.v:111775.3-111785.6" + wire width 3 $0\cr_bitfield_o[2:0] + attribute \src "issuer_ls180.v:111786.3-111796.6" + wire $0\cr_bitfield_o_ok[0:0] + attribute \src "issuer_ls180.v:111688.3-111714.6" + wire $0\cr_bitfield_ok[0:0] + attribute \src "issuer_ls180.v:111824.3-111842.6" + wire width 8 $0\cr_fxm[7:0] + attribute \src "issuer_ls180.v:111726.3-111736.6" + wire $0\cr_fxm_ok[0:0] + attribute \src "issuer_ls180.v:111547.7-111547.20" + wire $0\initial[0:0] + attribute \src "issuer_ls180.v:111797.3-111807.6" + wire $0\move_one[0:0] + attribute \src "issuer_ls180.v:111808.3-111823.6" + wire width 8 $0\ppick_i[7:0] + attribute \src "issuer_ls180.v:111737.3-111763.6" + wire width 3 $1\cr_bitfield[2:0] + attribute \src "issuer_ls180.v:111764.3-111774.6" + wire width 3 $1\cr_bitfield_b[2:0] + attribute \src "issuer_ls180.v:111715.3-111725.6" + wire $1\cr_bitfield_b_ok[0:0] + attribute \src "issuer_ls180.v:111775.3-111785.6" + wire width 3 $1\cr_bitfield_o[2:0] + attribute \src "issuer_ls180.v:111786.3-111796.6" + wire $1\cr_bitfield_o_ok[0:0] + attribute \src "issuer_ls180.v:111688.3-111714.6" + wire $1\cr_bitfield_ok[0:0] + attribute \src "issuer_ls180.v:111824.3-111842.6" + wire width 8 $1\cr_fxm[7:0] + attribute \src "issuer_ls180.v:111726.3-111736.6" + wire $1\cr_fxm_ok[0:0] + attribute \src "issuer_ls180.v:111797.3-111807.6" + wire $1\move_one[0:0] + attribute \src "issuer_ls180.v:111808.3-111823.6" + wire width 8 $1\ppick_i[7:0] + attribute \src "issuer_ls180.v:111824.3-111842.6" + wire width 8 $2\cr_fxm[7:0] + attribute \src "issuer_ls180.v:111808.3-111823.6" + wire width 8 $2\ppick_i[7:0] + attribute \src "issuer_ls180.v:111681.17-111681.112" + wire $and$issuer_ls180.v:111681$4337_Y + attribute \src "issuer_ls180.v:111683.17-111683.112" + wire $and$issuer_ls180.v:111683$4339_Y + attribute \src "issuer_ls180.v:111680.17-111680.124" + wire $eq$issuer_ls180.v:111680$4336_Y + attribute \src "issuer_ls180.v:111682.17-111682.124" + wire $eq$issuer_ls180.v:111682$4338_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 input 4 \BRANCH_BA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 input 3 \BRANCH_BB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 input 8 \BRANCH_BC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 input 7 \BRANCH_BI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 input 5 \BRANCH_BT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 8 input 6 \BRANCH_FXM + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 7 input 2 \BRANCH_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 3 input 9 \X_BFA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 3 \cr_bitfield + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 3 \cr_bitfield_b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \cr_bitfield_b_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 3 \cr_bitfield_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \cr_bitfield_o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \cr_bitfield_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 8 \cr_fxm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \cr_fxm_ok + attribute \src "issuer_ls180.v:111547.7-111547.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:485" + wire width 32 input 10 \insn_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:526" + wire \move_one + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" + wire width 8 \ppick_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" + wire width 8 \ppick_o + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:484" + wire width 3 input 1 \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" + cell $and $and$issuer_ls180.v:111681$4337 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$1 + connect \B \move_one + connect \Y $and$issuer_ls180.v:111681$4337_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" + cell $and $and$issuer_ls180.v:111683$4339 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$5 + connect \B \move_one + connect \Y $and$issuer_ls180.v:111683$4339_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" + cell $eq $eq$issuer_ls180.v:111680$4336 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \BRANCH_internal_op + connect \B 7'0101101 + connect \Y $eq$issuer_ls180.v:111680$4336_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" + cell $eq $eq$issuer_ls180.v:111682$4338 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \BRANCH_internal_op + connect \B 7'0101101 + connect \Y $eq$issuer_ls180.v:111682$4338_Y + end + attribute \module_not_derived 1 + attribute \src "issuer_ls180.v:111684.15-111687.4" + cell \ppick$148 \ppick + connect \i \ppick_i + connect \o \ppick_o + end + attribute \src "issuer_ls180.v:111547.7-111547.20" + process $proc$issuer_ls180.v:111547$4350 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "issuer_ls180.v:111688.3-111714.6" + process $proc$issuer_ls180.v:111688$4340 + assign { } { } + assign { } { } + assign $0\cr_bitfield_ok[0:0] $1\cr_bitfield_ok[0:0] + attribute \src "issuer_ls180.v:111689.5-111689.29" + switch \initial + attribute \src "issuer_ls180.v:111689.9-111689.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" + switch \sel_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 3'001 + assign { } { } + assign $1\cr_bitfield_ok[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 3'010 + assign { } { } + assign $1\cr_bitfield_ok[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 3'011 + assign { } { } + assign $1\cr_bitfield_ok[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 3'100 + assign { } { } + assign $1\cr_bitfield_ok[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 3'101 + assign { } { } + assign $1\cr_bitfield_ok[0:0] 1'1 + case + assign $1\cr_bitfield_ok[0:0] 1'0 + end + sync always + update \cr_bitfield_ok $0\cr_bitfield_ok[0:0] + end + attribute \src "issuer_ls180.v:111715.3-111725.6" + process $proc$issuer_ls180.v:111715$4341 + assign { } { } + assign { } { } + assign $0\cr_bitfield_b_ok[0:0] $1\cr_bitfield_b_ok[0:0] + attribute \src "issuer_ls180.v:111716.5-111716.29" + switch \initial + attribute \src "issuer_ls180.v:111716.9-111716.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" + switch \sel_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 3'100 + assign { } { } + assign $1\cr_bitfield_b_ok[0:0] 1'1 + case + assign $1\cr_bitfield_b_ok[0:0] 1'0 + end + sync always + update \cr_bitfield_b_ok $0\cr_bitfield_b_ok[0:0] + end + attribute \src "issuer_ls180.v:111726.3-111736.6" + process $proc$issuer_ls180.v:111726$4342 + assign { } { } + assign { } { } + assign $0\cr_fxm_ok[0:0] $1\cr_fxm_ok[0:0] + attribute \src "issuer_ls180.v:111727.5-111727.29" + switch \initial + attribute \src "issuer_ls180.v:111727.9-111727.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" + switch \sel_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 3'110 + assign { } { } + assign $1\cr_fxm_ok[0:0] 1'1 + case + assign $1\cr_fxm_ok[0:0] 1'0 + end + sync always + update \cr_fxm_ok $0\cr_fxm_ok[0:0] + end + attribute \src "issuer_ls180.v:111737.3-111763.6" + process $proc$issuer_ls180.v:111737$4343 + assign { } { } + assign { } { } + assign $0\cr_bitfield[2:0] $1\cr_bitfield[2:0] + attribute \src "issuer_ls180.v:111738.5-111738.29" + switch \initial + attribute \src "issuer_ls180.v:111738.9-111738.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" + switch \sel_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 3'001 + assign { } { } + assign $1\cr_bitfield[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 3'010 + assign { } { } + assign $1\cr_bitfield[2:0] \BRANCH_BI [4:2] + attribute \src "issuer_ls180.v:0.0-0.0" + case 3'011 + assign { } { } + assign $1\cr_bitfield[2:0] \X_BFA + attribute \src "issuer_ls180.v:0.0-0.0" + case 3'100 + assign { } { } + assign $1\cr_bitfield[2:0] \BRANCH_BA [4:2] + attribute \src "issuer_ls180.v:0.0-0.0" + case 3'101 + assign { } { } + assign $1\cr_bitfield[2:0] \BRANCH_BC [4:2] + case + assign $1\cr_bitfield[2:0] 3'000 + end + sync always + update \cr_bitfield $0\cr_bitfield[2:0] + end + attribute \src "issuer_ls180.v:111764.3-111774.6" + process $proc$issuer_ls180.v:111764$4344 + assign { } { } + assign { } { } + assign $0\cr_bitfield_b[2:0] $1\cr_bitfield_b[2:0] + attribute \src "issuer_ls180.v:111765.5-111765.29" + switch \initial + attribute \src "issuer_ls180.v:111765.9-111765.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" + switch \sel_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 3'100 + assign { } { } + assign $1\cr_bitfield_b[2:0] \BRANCH_BB [4:2] + case + assign $1\cr_bitfield_b[2:0] 3'000 + end + sync always + update \cr_bitfield_b $0\cr_bitfield_b[2:0] + end + attribute \src "issuer_ls180.v:111775.3-111785.6" + process $proc$issuer_ls180.v:111775$4345 + assign { } { } + assign { } { } + assign $0\cr_bitfield_o[2:0] $1\cr_bitfield_o[2:0] + attribute \src "issuer_ls180.v:111776.5-111776.29" + switch \initial + attribute \src "issuer_ls180.v:111776.9-111776.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" + switch \sel_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 3'100 + assign { } { } + assign $1\cr_bitfield_o[2:0] \BRANCH_BT [4:2] + case + assign $1\cr_bitfield_o[2:0] 3'000 + end + sync always + update \cr_bitfield_o $0\cr_bitfield_o[2:0] + end + attribute \src "issuer_ls180.v:111786.3-111796.6" + process $proc$issuer_ls180.v:111786$4346 + assign { } { } + assign { } { } + assign $0\cr_bitfield_o_ok[0:0] $1\cr_bitfield_o_ok[0:0] + attribute \src "issuer_ls180.v:111787.5-111787.29" + switch \initial + attribute \src "issuer_ls180.v:111787.9-111787.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" + switch \sel_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 3'100 + assign { } { } + assign $1\cr_bitfield_o_ok[0:0] 1'1 + case + assign $1\cr_bitfield_o_ok[0:0] 1'0 + end + sync always + update \cr_bitfield_o_ok $0\cr_bitfield_o_ok[0:0] + end + attribute \src "issuer_ls180.v:111797.3-111807.6" + process $proc$issuer_ls180.v:111797$4347 + assign { } { } + assign { } { } + assign $0\move_one[0:0] $1\move_one[0:0] + attribute \src "issuer_ls180.v:111798.5-111798.29" + switch \initial + attribute \src "issuer_ls180.v:111798.9-111798.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" + switch \sel_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 3'110 + assign { } { } + assign $1\move_one[0:0] \insn_in [20] + case + assign $1\move_one[0:0] 1'0 + end + sync always + update \move_one $0\move_one[0:0] + end + attribute \src "issuer_ls180.v:111808.3-111823.6" + process $proc$issuer_ls180.v:111808$4348 + assign { } { } + assign { } { } + assign $0\ppick_i[7:0] $1\ppick_i[7:0] + attribute \src "issuer_ls180.v:111809.5-111809.29" + switch \initial + attribute \src "issuer_ls180.v:111809.9-111809.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" + switch \sel_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 3'110 + assign { } { } + assign $1\ppick_i[7:0] $2\ppick_i[7:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" + switch \$3 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\ppick_i[7:0] \BRANCH_FXM + case + assign $2\ppick_i[7:0] 8'00000000 + end + case + assign $1\ppick_i[7:0] 8'00000000 + end + sync always + update \ppick_i $0\ppick_i[7:0] + end + attribute \src "issuer_ls180.v:111824.3-111842.6" + process $proc$issuer_ls180.v:111824$4349 + assign { } { } + assign { } { } + assign $0\cr_fxm[7:0] $1\cr_fxm[7:0] + attribute \src "issuer_ls180.v:111825.5-111825.29" + switch \initial + attribute \src "issuer_ls180.v:111825.9-111825.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" + switch \sel_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 3'110 + assign { } { } + assign $1\cr_fxm[7:0] $2\cr_fxm[7:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" + switch \$7 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\cr_fxm[7:0] \ppick_o + attribute \src "issuer_ls180.v:0.0-0.0" + case + assign { } { } + assign $2\cr_fxm[7:0] 8'11111111 + end + case + assign $1\cr_fxm[7:0] 8'00000000 + end + sync always + update \cr_fxm $0\cr_fxm[7:0] + end + connect \$1 $eq$issuer_ls180.v:111680$4336_Y + connect \$3 $and$issuer_ls180.v:111681$4337_Y + connect \$5 $eq$issuer_ls180.v:111682$4338_Y + connect \$7 $and$issuer_ls180.v:111683$4339_Y +end +attribute \src "issuer_ls180.v:111847.1-112144.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.dec_LOGICAL.dec_cr_in" +attribute \generator "nMigen" +module \dec_cr_in$155 + attribute \src "issuer_ls180.v:112038.3-112064.6" + wire width 3 $0\cr_bitfield[2:0] + attribute \src "issuer_ls180.v:112065.3-112075.6" + wire width 3 $0\cr_bitfield_b[2:0] + attribute \src "issuer_ls180.v:112016.3-112026.6" + wire $0\cr_bitfield_b_ok[0:0] + attribute \src "issuer_ls180.v:112076.3-112086.6" + wire width 3 $0\cr_bitfield_o[2:0] + attribute \src "issuer_ls180.v:112087.3-112097.6" + wire $0\cr_bitfield_o_ok[0:0] + attribute \src "issuer_ls180.v:111989.3-112015.6" + wire $0\cr_bitfield_ok[0:0] + attribute \src "issuer_ls180.v:112125.3-112143.6" + wire width 8 $0\cr_fxm[7:0] + attribute \src "issuer_ls180.v:112027.3-112037.6" + wire $0\cr_fxm_ok[0:0] + attribute \src "issuer_ls180.v:111848.7-111848.20" + wire $0\initial[0:0] + attribute \src "issuer_ls180.v:112098.3-112108.6" + wire $0\move_one[0:0] + attribute \src "issuer_ls180.v:112109.3-112124.6" + wire width 8 $0\ppick_i[7:0] + attribute \src "issuer_ls180.v:112038.3-112064.6" + wire width 3 $1\cr_bitfield[2:0] + attribute \src "issuer_ls180.v:112065.3-112075.6" + wire width 3 $1\cr_bitfield_b[2:0] + attribute \src "issuer_ls180.v:112016.3-112026.6" + wire $1\cr_bitfield_b_ok[0:0] + attribute \src "issuer_ls180.v:112076.3-112086.6" + wire width 3 $1\cr_bitfield_o[2:0] + attribute \src "issuer_ls180.v:112087.3-112097.6" + wire $1\cr_bitfield_o_ok[0:0] + attribute \src "issuer_ls180.v:111989.3-112015.6" + wire $1\cr_bitfield_ok[0:0] + attribute \src "issuer_ls180.v:112125.3-112143.6" + wire width 8 $1\cr_fxm[7:0] + attribute \src "issuer_ls180.v:112027.3-112037.6" + wire $1\cr_fxm_ok[0:0] + attribute \src "issuer_ls180.v:112098.3-112108.6" + wire $1\move_one[0:0] + attribute \src "issuer_ls180.v:112109.3-112124.6" + wire width 8 $1\ppick_i[7:0] + attribute \src "issuer_ls180.v:112125.3-112143.6" + wire width 8 $2\cr_fxm[7:0] + attribute \src "issuer_ls180.v:112109.3-112124.6" + wire width 8 $2\ppick_i[7:0] + attribute \src "issuer_ls180.v:111982.17-111982.112" + wire $and$issuer_ls180.v:111982$4352_Y + attribute \src "issuer_ls180.v:111984.17-111984.112" + wire $and$issuer_ls180.v:111984$4354_Y + attribute \src "issuer_ls180.v:111981.17-111981.125" + wire $eq$issuer_ls180.v:111981$4351_Y + attribute \src "issuer_ls180.v:111983.17-111983.125" + wire $eq$issuer_ls180.v:111983$4353_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 input 4 \LOGICAL_BA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 input 3 \LOGICAL_BB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 input 8 \LOGICAL_BC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 input 7 \LOGICAL_BI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 input 5 \LOGICAL_BT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 8 input 6 \LOGICAL_FXM + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 7 input 2 \LOGICAL_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 3 input 9 \X_BFA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 3 \cr_bitfield + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 3 \cr_bitfield_b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \cr_bitfield_b_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 3 \cr_bitfield_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \cr_bitfield_o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \cr_bitfield_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 8 \cr_fxm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \cr_fxm_ok + attribute \src "issuer_ls180.v:111848.7-111848.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:485" + wire width 32 input 10 \insn_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:526" + wire \move_one + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" + wire width 8 \ppick_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" + wire width 8 \ppick_o + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:484" + wire width 3 input 1 \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" + cell $and $and$issuer_ls180.v:111982$4352 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$1 + connect \B \move_one + connect \Y $and$issuer_ls180.v:111982$4352_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" + cell $and $and$issuer_ls180.v:111984$4354 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$5 + connect \B \move_one + connect \Y $and$issuer_ls180.v:111984$4354_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" + cell $eq $eq$issuer_ls180.v:111981$4351 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \LOGICAL_internal_op + connect \B 7'0101101 + connect \Y $eq$issuer_ls180.v:111981$4351_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" + cell $eq $eq$issuer_ls180.v:111983$4353 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \LOGICAL_internal_op + connect \B 7'0101101 + connect \Y $eq$issuer_ls180.v:111983$4353_Y + end + attribute \module_not_derived 1 + attribute \src "issuer_ls180.v:111985.15-111988.4" + cell \ppick$156 \ppick + connect \i \ppick_i + connect \o \ppick_o + end + attribute \src "issuer_ls180.v:111848.7-111848.20" + process $proc$issuer_ls180.v:111848$4365 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "issuer_ls180.v:111989.3-112015.6" + process $proc$issuer_ls180.v:111989$4355 + assign { } { } + assign { } { } + assign $0\cr_bitfield_ok[0:0] $1\cr_bitfield_ok[0:0] + attribute \src "issuer_ls180.v:111990.5-111990.29" + switch \initial + attribute \src "issuer_ls180.v:111990.9-111990.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" + switch \sel_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 3'001 + assign { } { } + assign $1\cr_bitfield_ok[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 3'010 + assign { } { } + assign $1\cr_bitfield_ok[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 3'011 + assign { } { } + assign $1\cr_bitfield_ok[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 3'100 + assign { } { } + assign $1\cr_bitfield_ok[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 3'101 + assign { } { } + assign $1\cr_bitfield_ok[0:0] 1'1 + case + assign $1\cr_bitfield_ok[0:0] 1'0 + end + sync always + update \cr_bitfield_ok $0\cr_bitfield_ok[0:0] + end + attribute \src "issuer_ls180.v:112016.3-112026.6" + process $proc$issuer_ls180.v:112016$4356 + assign { } { } + assign { } { } + assign $0\cr_bitfield_b_ok[0:0] $1\cr_bitfield_b_ok[0:0] + attribute \src "issuer_ls180.v:112017.5-112017.29" + switch \initial + attribute \src "issuer_ls180.v:112017.9-112017.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" + switch \sel_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 3'100 + assign { } { } + assign $1\cr_bitfield_b_ok[0:0] 1'1 + case + assign $1\cr_bitfield_b_ok[0:0] 1'0 + end + sync always + update \cr_bitfield_b_ok $0\cr_bitfield_b_ok[0:0] + end + attribute \src "issuer_ls180.v:112027.3-112037.6" + process $proc$issuer_ls180.v:112027$4357 + assign { } { } + assign { } { } + assign $0\cr_fxm_ok[0:0] $1\cr_fxm_ok[0:0] + attribute \src "issuer_ls180.v:112028.5-112028.29" + switch \initial + attribute \src "issuer_ls180.v:112028.9-112028.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" + switch \sel_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 3'110 + assign { } { } + assign $1\cr_fxm_ok[0:0] 1'1 + case + assign $1\cr_fxm_ok[0:0] 1'0 + end + sync always + update \cr_fxm_ok $0\cr_fxm_ok[0:0] + end + attribute \src "issuer_ls180.v:112038.3-112064.6" + process $proc$issuer_ls180.v:112038$4358 + assign { } { } + assign { } { } + assign $0\cr_bitfield[2:0] $1\cr_bitfield[2:0] + attribute \src "issuer_ls180.v:112039.5-112039.29" + switch \initial + attribute \src "issuer_ls180.v:112039.9-112039.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" + switch \sel_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 3'001 + assign { } { } + assign $1\cr_bitfield[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 3'010 + assign { } { } + assign $1\cr_bitfield[2:0] \LOGICAL_BI [4:2] + attribute \src "issuer_ls180.v:0.0-0.0" + case 3'011 + assign { } { } + assign $1\cr_bitfield[2:0] \X_BFA + attribute \src "issuer_ls180.v:0.0-0.0" + case 3'100 + assign { } { } + assign $1\cr_bitfield[2:0] \LOGICAL_BA [4:2] + attribute \src "issuer_ls180.v:0.0-0.0" + case 3'101 + assign { } { } + assign $1\cr_bitfield[2:0] \LOGICAL_BC [4:2] + case + assign $1\cr_bitfield[2:0] 3'000 + end + sync always + update \cr_bitfield $0\cr_bitfield[2:0] + end + attribute \src "issuer_ls180.v:112065.3-112075.6" + process $proc$issuer_ls180.v:112065$4359 + assign { } { } + assign { } { } + assign $0\cr_bitfield_b[2:0] $1\cr_bitfield_b[2:0] + attribute \src "issuer_ls180.v:112066.5-112066.29" + switch \initial + attribute \src "issuer_ls180.v:112066.9-112066.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" + switch \sel_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 3'100 + assign { } { } + assign $1\cr_bitfield_b[2:0] \LOGICAL_BB [4:2] + case + assign $1\cr_bitfield_b[2:0] 3'000 + end + sync always + update \cr_bitfield_b $0\cr_bitfield_b[2:0] + end + attribute \src "issuer_ls180.v:112076.3-112086.6" + process $proc$issuer_ls180.v:112076$4360 + assign { } { } + assign { } { } + assign $0\cr_bitfield_o[2:0] $1\cr_bitfield_o[2:0] + attribute \src "issuer_ls180.v:112077.5-112077.29" + switch \initial + attribute \src "issuer_ls180.v:112077.9-112077.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" + switch \sel_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 3'100 + assign { } { } + assign $1\cr_bitfield_o[2:0] \LOGICAL_BT [4:2] + case + assign $1\cr_bitfield_o[2:0] 3'000 + end + sync always + update \cr_bitfield_o $0\cr_bitfield_o[2:0] + end + attribute \src "issuer_ls180.v:112087.3-112097.6" + process $proc$issuer_ls180.v:112087$4361 + assign { } { } + assign { } { } + assign $0\cr_bitfield_o_ok[0:0] $1\cr_bitfield_o_ok[0:0] + attribute \src "issuer_ls180.v:112088.5-112088.29" + switch \initial + attribute \src "issuer_ls180.v:112088.9-112088.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" + switch \sel_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 3'100 + assign { } { } + assign $1\cr_bitfield_o_ok[0:0] 1'1 + case + assign $1\cr_bitfield_o_ok[0:0] 1'0 + end + sync always + update \cr_bitfield_o_ok $0\cr_bitfield_o_ok[0:0] + end + attribute \src "issuer_ls180.v:112098.3-112108.6" + process $proc$issuer_ls180.v:112098$4362 + assign { } { } + assign { } { } + assign $0\move_one[0:0] $1\move_one[0:0] + attribute \src "issuer_ls180.v:112099.5-112099.29" + switch \initial + attribute \src "issuer_ls180.v:112099.9-112099.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" + switch \sel_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 3'110 + assign { } { } + assign $1\move_one[0:0] \insn_in [20] + case + assign $1\move_one[0:0] 1'0 + end + sync always + update \move_one $0\move_one[0:0] + end + attribute \src "issuer_ls180.v:112109.3-112124.6" + process $proc$issuer_ls180.v:112109$4363 + assign { } { } + assign { } { } + assign $0\ppick_i[7:0] $1\ppick_i[7:0] + attribute \src "issuer_ls180.v:112110.5-112110.29" + switch \initial + attribute \src "issuer_ls180.v:112110.9-112110.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" + switch \sel_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 3'110 + assign { } { } + assign $1\ppick_i[7:0] $2\ppick_i[7:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" + switch \$3 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\ppick_i[7:0] \LOGICAL_FXM + case + assign $2\ppick_i[7:0] 8'00000000 + end + case + assign $1\ppick_i[7:0] 8'00000000 + end + sync always + update \ppick_i $0\ppick_i[7:0] + end + attribute \src "issuer_ls180.v:112125.3-112143.6" + process $proc$issuer_ls180.v:112125$4364 + assign { } { } + assign { } { } + assign $0\cr_fxm[7:0] $1\cr_fxm[7:0] + attribute \src "issuer_ls180.v:112126.5-112126.29" + switch \initial + attribute \src "issuer_ls180.v:112126.9-112126.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" + switch \sel_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 3'110 + assign { } { } + assign $1\cr_fxm[7:0] $2\cr_fxm[7:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" + switch \$7 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\cr_fxm[7:0] \ppick_o + attribute \src "issuer_ls180.v:0.0-0.0" + case + assign { } { } + assign $2\cr_fxm[7:0] 8'11111111 + end + case + assign $1\cr_fxm[7:0] 8'00000000 + end + sync always + update \cr_fxm $0\cr_fxm[7:0] + end + connect \$1 $eq$issuer_ls180.v:111981$4351_Y + connect \$3 $and$issuer_ls180.v:111982$4352_Y + connect \$5 $eq$issuer_ls180.v:111983$4353_Y + connect \$7 $and$issuer_ls180.v:111984$4354_Y +end +attribute \src "issuer_ls180.v:112148.1-112445.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.dec_SPR.dec_cr_in" +attribute \generator "nMigen" +module \dec_cr_in$164 + attribute \src "issuer_ls180.v:112339.3-112365.6" + wire width 3 $0\cr_bitfield[2:0] + attribute \src "issuer_ls180.v:112366.3-112376.6" + wire width 3 $0\cr_bitfield_b[2:0] + attribute \src "issuer_ls180.v:112317.3-112327.6" + wire $0\cr_bitfield_b_ok[0:0] + attribute \src "issuer_ls180.v:112377.3-112387.6" + wire width 3 $0\cr_bitfield_o[2:0] + attribute \src "issuer_ls180.v:112388.3-112398.6" + wire $0\cr_bitfield_o_ok[0:0] + attribute \src "issuer_ls180.v:112290.3-112316.6" + wire $0\cr_bitfield_ok[0:0] + attribute \src "issuer_ls180.v:112426.3-112444.6" + wire width 8 $0\cr_fxm[7:0] + attribute \src "issuer_ls180.v:112328.3-112338.6" + wire $0\cr_fxm_ok[0:0] + attribute \src "issuer_ls180.v:112149.7-112149.20" + wire $0\initial[0:0] + attribute \src "issuer_ls180.v:112399.3-112409.6" + wire $0\move_one[0:0] + attribute \src "issuer_ls180.v:112410.3-112425.6" + wire width 8 $0\ppick_i[7:0] + attribute \src "issuer_ls180.v:112339.3-112365.6" + wire width 3 $1\cr_bitfield[2:0] + attribute \src "issuer_ls180.v:112366.3-112376.6" + wire width 3 $1\cr_bitfield_b[2:0] + attribute \src "issuer_ls180.v:112317.3-112327.6" + wire $1\cr_bitfield_b_ok[0:0] + attribute \src "issuer_ls180.v:112377.3-112387.6" + wire width 3 $1\cr_bitfield_o[2:0] + attribute \src "issuer_ls180.v:112388.3-112398.6" + wire $1\cr_bitfield_o_ok[0:0] + attribute \src "issuer_ls180.v:112290.3-112316.6" + wire $1\cr_bitfield_ok[0:0] + attribute \src "issuer_ls180.v:112426.3-112444.6" + wire width 8 $1\cr_fxm[7:0] + attribute \src "issuer_ls180.v:112328.3-112338.6" + wire $1\cr_fxm_ok[0:0] + attribute \src "issuer_ls180.v:112399.3-112409.6" + wire $1\move_one[0:0] + attribute \src "issuer_ls180.v:112410.3-112425.6" + wire width 8 $1\ppick_i[7:0] + attribute \src "issuer_ls180.v:112426.3-112444.6" + wire width 8 $2\cr_fxm[7:0] + attribute \src "issuer_ls180.v:112410.3-112425.6" + wire width 8 $2\ppick_i[7:0] + attribute \src "issuer_ls180.v:112283.17-112283.112" + wire $and$issuer_ls180.v:112283$4367_Y + attribute \src "issuer_ls180.v:112285.17-112285.112" + wire $and$issuer_ls180.v:112285$4369_Y + attribute \src "issuer_ls180.v:112282.17-112282.121" + wire $eq$issuer_ls180.v:112282$4366_Y + attribute \src "issuer_ls180.v:112284.17-112284.121" + wire $eq$issuer_ls180.v:112284$4368_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 input 4 \SPR_BA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 input 3 \SPR_BB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 input 8 \SPR_BC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 input 7 \SPR_BI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 input 5 \SPR_BT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 8 input 6 \SPR_FXM + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 7 input 2 \SPR_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 3 input 9 \X_BFA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 3 \cr_bitfield + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 3 \cr_bitfield_b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \cr_bitfield_b_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 3 \cr_bitfield_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \cr_bitfield_o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \cr_bitfield_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 8 \cr_fxm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \cr_fxm_ok + attribute \src "issuer_ls180.v:112149.7-112149.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:485" + wire width 32 input 10 \insn_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:526" + wire \move_one + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" + wire width 8 \ppick_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" + wire width 8 \ppick_o + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:484" + wire width 3 input 1 \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" + cell $and $and$issuer_ls180.v:112283$4367 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$1 + connect \B \move_one + connect \Y $and$issuer_ls180.v:112283$4367_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" + cell $and $and$issuer_ls180.v:112285$4369 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$5 + connect \B \move_one + connect \Y $and$issuer_ls180.v:112285$4369_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" + cell $eq $eq$issuer_ls180.v:112282$4366 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \SPR_internal_op + connect \B 7'0101101 + connect \Y $eq$issuer_ls180.v:112282$4366_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" + cell $eq $eq$issuer_ls180.v:112284$4368 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \SPR_internal_op + connect \B 7'0101101 + connect \Y $eq$issuer_ls180.v:112284$4368_Y + end + attribute \module_not_derived 1 + attribute \src "issuer_ls180.v:112286.15-112289.4" + cell \ppick$165 \ppick + connect \i \ppick_i + connect \o \ppick_o + end + attribute \src "issuer_ls180.v:112149.7-112149.20" + process $proc$issuer_ls180.v:112149$4380 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "issuer_ls180.v:112290.3-112316.6" + process $proc$issuer_ls180.v:112290$4370 + assign { } { } + assign { } { } + assign $0\cr_bitfield_ok[0:0] $1\cr_bitfield_ok[0:0] + attribute \src "issuer_ls180.v:112291.5-112291.29" + switch \initial + attribute \src "issuer_ls180.v:112291.9-112291.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" + switch \sel_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 3'001 + assign { } { } + assign $1\cr_bitfield_ok[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 3'010 + assign { } { } + assign $1\cr_bitfield_ok[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 3'011 + assign { } { } + assign $1\cr_bitfield_ok[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 3'100 + assign { } { } + assign $1\cr_bitfield_ok[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 3'101 + assign { } { } + assign $1\cr_bitfield_ok[0:0] 1'1 + case + assign $1\cr_bitfield_ok[0:0] 1'0 + end + sync always + update \cr_bitfield_ok $0\cr_bitfield_ok[0:0] + end + attribute \src "issuer_ls180.v:112317.3-112327.6" + process $proc$issuer_ls180.v:112317$4371 + assign { } { } + assign { } { } + assign $0\cr_bitfield_b_ok[0:0] $1\cr_bitfield_b_ok[0:0] + attribute \src "issuer_ls180.v:112318.5-112318.29" + switch \initial + attribute \src "issuer_ls180.v:112318.9-112318.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" + switch \sel_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 3'100 + assign { } { } + assign $1\cr_bitfield_b_ok[0:0] 1'1 + case + assign $1\cr_bitfield_b_ok[0:0] 1'0 + end + sync always + update \cr_bitfield_b_ok $0\cr_bitfield_b_ok[0:0] + end + attribute \src "issuer_ls180.v:112328.3-112338.6" + process $proc$issuer_ls180.v:112328$4372 + assign { } { } + assign { } { } + assign $0\cr_fxm_ok[0:0] $1\cr_fxm_ok[0:0] + attribute \src "issuer_ls180.v:112329.5-112329.29" + switch \initial + attribute \src "issuer_ls180.v:112329.9-112329.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" + switch \sel_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 3'110 + assign { } { } + assign $1\cr_fxm_ok[0:0] 1'1 + case + assign $1\cr_fxm_ok[0:0] 1'0 + end + sync always + update \cr_fxm_ok $0\cr_fxm_ok[0:0] + end + attribute \src "issuer_ls180.v:112339.3-112365.6" + process $proc$issuer_ls180.v:112339$4373 + assign { } { } + assign { } { } + assign $0\cr_bitfield[2:0] $1\cr_bitfield[2:0] + attribute \src "issuer_ls180.v:112340.5-112340.29" + switch \initial + attribute \src "issuer_ls180.v:112340.9-112340.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" + switch \sel_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 3'001 + assign { } { } + assign $1\cr_bitfield[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 3'010 + assign { } { } + assign $1\cr_bitfield[2:0] \SPR_BI [4:2] + attribute \src "issuer_ls180.v:0.0-0.0" + case 3'011 + assign { } { } + assign $1\cr_bitfield[2:0] \X_BFA + attribute \src "issuer_ls180.v:0.0-0.0" + case 3'100 + assign { } { } + assign $1\cr_bitfield[2:0] \SPR_BA [4:2] + attribute \src "issuer_ls180.v:0.0-0.0" + case 3'101 + assign { } { } + assign $1\cr_bitfield[2:0] \SPR_BC [4:2] + case + assign $1\cr_bitfield[2:0] 3'000 + end + sync always + update \cr_bitfield $0\cr_bitfield[2:0] + end + attribute \src "issuer_ls180.v:112366.3-112376.6" + process $proc$issuer_ls180.v:112366$4374 + assign { } { } + assign { } { } + assign $0\cr_bitfield_b[2:0] $1\cr_bitfield_b[2:0] + attribute \src "issuer_ls180.v:112367.5-112367.29" + switch \initial + attribute \src "issuer_ls180.v:112367.9-112367.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" + switch \sel_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 3'100 + assign { } { } + assign $1\cr_bitfield_b[2:0] \SPR_BB [4:2] + case + assign $1\cr_bitfield_b[2:0] 3'000 + end + sync always + update \cr_bitfield_b $0\cr_bitfield_b[2:0] + end + attribute \src "issuer_ls180.v:112377.3-112387.6" + process $proc$issuer_ls180.v:112377$4375 + assign { } { } + assign { } { } + assign $0\cr_bitfield_o[2:0] $1\cr_bitfield_o[2:0] + attribute \src "issuer_ls180.v:112378.5-112378.29" + switch \initial + attribute \src "issuer_ls180.v:112378.9-112378.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" + switch \sel_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 3'100 + assign { } { } + assign $1\cr_bitfield_o[2:0] \SPR_BT [4:2] + case + assign $1\cr_bitfield_o[2:0] 3'000 + end + sync always + update \cr_bitfield_o $0\cr_bitfield_o[2:0] + end + attribute \src "issuer_ls180.v:112388.3-112398.6" + process $proc$issuer_ls180.v:112388$4376 + assign { } { } + assign { } { } + assign $0\cr_bitfield_o_ok[0:0] $1\cr_bitfield_o_ok[0:0] + attribute \src "issuer_ls180.v:112389.5-112389.29" + switch \initial + attribute \src "issuer_ls180.v:112389.9-112389.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" + switch \sel_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 3'100 + assign { } { } + assign $1\cr_bitfield_o_ok[0:0] 1'1 + case + assign $1\cr_bitfield_o_ok[0:0] 1'0 + end + sync always + update \cr_bitfield_o_ok $0\cr_bitfield_o_ok[0:0] + end + attribute \src "issuer_ls180.v:112399.3-112409.6" + process $proc$issuer_ls180.v:112399$4377 + assign { } { } + assign { } { } + assign $0\move_one[0:0] $1\move_one[0:0] + attribute \src "issuer_ls180.v:112400.5-112400.29" + switch \initial + attribute \src "issuer_ls180.v:112400.9-112400.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" + switch \sel_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 3'110 + assign { } { } + assign $1\move_one[0:0] \insn_in [20] + case + assign $1\move_one[0:0] 1'0 + end + sync always + update \move_one $0\move_one[0:0] + end + attribute \src "issuer_ls180.v:112410.3-112425.6" + process $proc$issuer_ls180.v:112410$4378 + assign { } { } + assign { } { } + assign $0\ppick_i[7:0] $1\ppick_i[7:0] + attribute \src "issuer_ls180.v:112411.5-112411.29" + switch \initial + attribute \src "issuer_ls180.v:112411.9-112411.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" + switch \sel_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 3'110 + assign { } { } + assign $1\ppick_i[7:0] $2\ppick_i[7:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" + switch \$3 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\ppick_i[7:0] \SPR_FXM + case + assign $2\ppick_i[7:0] 8'00000000 + end + case + assign $1\ppick_i[7:0] 8'00000000 + end + sync always + update \ppick_i $0\ppick_i[7:0] + end + attribute \src "issuer_ls180.v:112426.3-112444.6" + process $proc$issuer_ls180.v:112426$4379 + assign { } { } + assign { } { } + assign $0\cr_fxm[7:0] $1\cr_fxm[7:0] + attribute \src "issuer_ls180.v:112427.5-112427.29" + switch \initial + attribute \src "issuer_ls180.v:112427.9-112427.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" + switch \sel_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 3'110 + assign { } { } + assign $1\cr_fxm[7:0] $2\cr_fxm[7:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" + switch \$7 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\cr_fxm[7:0] \ppick_o + attribute \src "issuer_ls180.v:0.0-0.0" + case + assign { } { } + assign $2\cr_fxm[7:0] 8'11111111 + end + case + assign $1\cr_fxm[7:0] 8'00000000 + end + sync always + update \cr_fxm $0\cr_fxm[7:0] + end + connect \$1 $eq$issuer_ls180.v:112282$4366_Y + connect \$3 $and$issuer_ls180.v:112283$4367_Y + connect \$5 $eq$issuer_ls180.v:112284$4368_Y + connect \$7 $and$issuer_ls180.v:112285$4369_Y +end +attribute \src "issuer_ls180.v:112449.1-112746.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.dec_DIV.dec_cr_in" +attribute \generator "nMigen" +module \dec_cr_in$171 + attribute \src "issuer_ls180.v:112640.3-112666.6" + wire width 3 $0\cr_bitfield[2:0] + attribute \src "issuer_ls180.v:112667.3-112677.6" + wire width 3 $0\cr_bitfield_b[2:0] + attribute \src "issuer_ls180.v:112618.3-112628.6" + wire $0\cr_bitfield_b_ok[0:0] + attribute \src "issuer_ls180.v:112678.3-112688.6" + wire width 3 $0\cr_bitfield_o[2:0] + attribute \src "issuer_ls180.v:112689.3-112699.6" + wire $0\cr_bitfield_o_ok[0:0] + attribute \src "issuer_ls180.v:112591.3-112617.6" + wire $0\cr_bitfield_ok[0:0] + attribute \src "issuer_ls180.v:112727.3-112745.6" + wire width 8 $0\cr_fxm[7:0] + attribute \src "issuer_ls180.v:112629.3-112639.6" + wire $0\cr_fxm_ok[0:0] + attribute \src "issuer_ls180.v:112450.7-112450.20" + wire $0\initial[0:0] + attribute \src "issuer_ls180.v:112700.3-112710.6" + wire $0\move_one[0:0] + attribute \src "issuer_ls180.v:112711.3-112726.6" + wire width 8 $0\ppick_i[7:0] + attribute \src "issuer_ls180.v:112640.3-112666.6" + wire width 3 $1\cr_bitfield[2:0] + attribute \src "issuer_ls180.v:112667.3-112677.6" + wire width 3 $1\cr_bitfield_b[2:0] + attribute \src "issuer_ls180.v:112618.3-112628.6" + wire $1\cr_bitfield_b_ok[0:0] + attribute \src "issuer_ls180.v:112678.3-112688.6" + wire width 3 $1\cr_bitfield_o[2:0] + attribute \src "issuer_ls180.v:112689.3-112699.6" + wire $1\cr_bitfield_o_ok[0:0] + attribute \src "issuer_ls180.v:112591.3-112617.6" + wire $1\cr_bitfield_ok[0:0] + attribute \src "issuer_ls180.v:112727.3-112745.6" + wire width 8 $1\cr_fxm[7:0] + attribute \src "issuer_ls180.v:112629.3-112639.6" + wire $1\cr_fxm_ok[0:0] + attribute \src "issuer_ls180.v:112700.3-112710.6" + wire $1\move_one[0:0] + attribute \src "issuer_ls180.v:112711.3-112726.6" + wire width 8 $1\ppick_i[7:0] + attribute \src "issuer_ls180.v:112727.3-112745.6" + wire width 8 $2\cr_fxm[7:0] + attribute \src "issuer_ls180.v:112711.3-112726.6" + wire width 8 $2\ppick_i[7:0] + attribute \src "issuer_ls180.v:112584.17-112584.112" + wire $and$issuer_ls180.v:112584$4382_Y + attribute \src "issuer_ls180.v:112586.17-112586.112" + wire $and$issuer_ls180.v:112586$4384_Y + attribute \src "issuer_ls180.v:112583.17-112583.121" + wire $eq$issuer_ls180.v:112583$4381_Y + attribute \src "issuer_ls180.v:112585.17-112585.121" + wire $eq$issuer_ls180.v:112585$4383_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 input 4 \DIV_BA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 input 3 \DIV_BB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 input 8 \DIV_BC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 input 7 \DIV_BI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 input 5 \DIV_BT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 8 input 6 \DIV_FXM + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 7 input 2 \DIV_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 3 input 9 \X_BFA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 3 \cr_bitfield + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 3 \cr_bitfield_b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \cr_bitfield_b_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 3 \cr_bitfield_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \cr_bitfield_o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \cr_bitfield_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 8 \cr_fxm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \cr_fxm_ok + attribute \src "issuer_ls180.v:112450.7-112450.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:485" + wire width 32 input 10 \insn_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:526" + wire \move_one + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" + wire width 8 \ppick_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" + wire width 8 \ppick_o + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:484" + wire width 3 input 1 \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" + cell $and $and$issuer_ls180.v:112584$4382 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$1 + connect \B \move_one + connect \Y $and$issuer_ls180.v:112584$4382_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" + cell $and $and$issuer_ls180.v:112586$4384 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$5 + connect \B \move_one + connect \Y $and$issuer_ls180.v:112586$4384_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" + cell $eq $eq$issuer_ls180.v:112583$4381 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \DIV_internal_op + connect \B 7'0101101 + connect \Y $eq$issuer_ls180.v:112583$4381_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" + cell $eq $eq$issuer_ls180.v:112585$4383 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \DIV_internal_op + connect \B 7'0101101 + connect \Y $eq$issuer_ls180.v:112585$4383_Y + end + attribute \module_not_derived 1 + attribute \src "issuer_ls180.v:112587.15-112590.4" + cell \ppick$172 \ppick + connect \i \ppick_i + connect \o \ppick_o + end + attribute \src "issuer_ls180.v:112450.7-112450.20" + process $proc$issuer_ls180.v:112450$4395 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "issuer_ls180.v:112591.3-112617.6" + process $proc$issuer_ls180.v:112591$4385 + assign { } { } + assign { } { } + assign $0\cr_bitfield_ok[0:0] $1\cr_bitfield_ok[0:0] + attribute \src "issuer_ls180.v:112592.5-112592.29" + switch \initial + attribute \src "issuer_ls180.v:112592.9-112592.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" + switch \sel_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 3'001 + assign { } { } + assign $1\cr_bitfield_ok[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 3'010 + assign { } { } + assign $1\cr_bitfield_ok[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 3'011 + assign { } { } + assign $1\cr_bitfield_ok[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 3'100 + assign { } { } + assign $1\cr_bitfield_ok[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 3'101 + assign { } { } + assign $1\cr_bitfield_ok[0:0] 1'1 + case + assign $1\cr_bitfield_ok[0:0] 1'0 + end + sync always + update \cr_bitfield_ok $0\cr_bitfield_ok[0:0] + end + attribute \src "issuer_ls180.v:112618.3-112628.6" + process $proc$issuer_ls180.v:112618$4386 + assign { } { } + assign { } { } + assign $0\cr_bitfield_b_ok[0:0] $1\cr_bitfield_b_ok[0:0] + attribute \src "issuer_ls180.v:112619.5-112619.29" + switch \initial + attribute \src "issuer_ls180.v:112619.9-112619.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" + switch \sel_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 3'100 + assign { } { } + assign $1\cr_bitfield_b_ok[0:0] 1'1 + case + assign $1\cr_bitfield_b_ok[0:0] 1'0 + end + sync always + update \cr_bitfield_b_ok $0\cr_bitfield_b_ok[0:0] + end + attribute \src "issuer_ls180.v:112629.3-112639.6" + process $proc$issuer_ls180.v:112629$4387 + assign { } { } + assign { } { } + assign $0\cr_fxm_ok[0:0] $1\cr_fxm_ok[0:0] + attribute \src "issuer_ls180.v:112630.5-112630.29" + switch \initial + attribute \src "issuer_ls180.v:112630.9-112630.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" + switch \sel_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 3'110 + assign { } { } + assign $1\cr_fxm_ok[0:0] 1'1 + case + assign $1\cr_fxm_ok[0:0] 1'0 + end + sync always + update \cr_fxm_ok $0\cr_fxm_ok[0:0] + end + attribute \src "issuer_ls180.v:112640.3-112666.6" + process $proc$issuer_ls180.v:112640$4388 + assign { } { } + assign { } { } + assign $0\cr_bitfield[2:0] $1\cr_bitfield[2:0] + attribute \src "issuer_ls180.v:112641.5-112641.29" + switch \initial + attribute \src "issuer_ls180.v:112641.9-112641.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" + switch \sel_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 3'001 + assign { } { } + assign $1\cr_bitfield[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 3'010 + assign { } { } + assign $1\cr_bitfield[2:0] \DIV_BI [4:2] + attribute \src "issuer_ls180.v:0.0-0.0" + case 3'011 + assign { } { } + assign $1\cr_bitfield[2:0] \X_BFA + attribute \src "issuer_ls180.v:0.0-0.0" + case 3'100 + assign { } { } + assign $1\cr_bitfield[2:0] \DIV_BA [4:2] + attribute \src "issuer_ls180.v:0.0-0.0" + case 3'101 + assign { } { } + assign $1\cr_bitfield[2:0] \DIV_BC [4:2] + case + assign $1\cr_bitfield[2:0] 3'000 + end + sync always + update \cr_bitfield $0\cr_bitfield[2:0] + end + attribute \src "issuer_ls180.v:112667.3-112677.6" + process $proc$issuer_ls180.v:112667$4389 + assign { } { } + assign { } { } + assign $0\cr_bitfield_b[2:0] $1\cr_bitfield_b[2:0] + attribute \src "issuer_ls180.v:112668.5-112668.29" + switch \initial + attribute \src "issuer_ls180.v:112668.9-112668.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" + switch \sel_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 3'100 + assign { } { } + assign $1\cr_bitfield_b[2:0] \DIV_BB [4:2] + case + assign $1\cr_bitfield_b[2:0] 3'000 + end + sync always + update \cr_bitfield_b $0\cr_bitfield_b[2:0] + end + attribute \src "issuer_ls180.v:112678.3-112688.6" + process $proc$issuer_ls180.v:112678$4390 + assign { } { } + assign { } { } + assign $0\cr_bitfield_o[2:0] $1\cr_bitfield_o[2:0] + attribute \src "issuer_ls180.v:112679.5-112679.29" + switch \initial + attribute \src "issuer_ls180.v:112679.9-112679.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" + switch \sel_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 3'100 + assign { } { } + assign $1\cr_bitfield_o[2:0] \DIV_BT [4:2] + case + assign $1\cr_bitfield_o[2:0] 3'000 + end + sync always + update \cr_bitfield_o $0\cr_bitfield_o[2:0] + end + attribute \src "issuer_ls180.v:112689.3-112699.6" + process $proc$issuer_ls180.v:112689$4391 + assign { } { } + assign { } { } + assign $0\cr_bitfield_o_ok[0:0] $1\cr_bitfield_o_ok[0:0] + attribute \src "issuer_ls180.v:112690.5-112690.29" + switch \initial + attribute \src "issuer_ls180.v:112690.9-112690.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" + switch \sel_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 3'100 + assign { } { } + assign $1\cr_bitfield_o_ok[0:0] 1'1 + case + assign $1\cr_bitfield_o_ok[0:0] 1'0 + end + sync always + update \cr_bitfield_o_ok $0\cr_bitfield_o_ok[0:0] + end + attribute \src "issuer_ls180.v:112700.3-112710.6" + process $proc$issuer_ls180.v:112700$4392 + assign { } { } + assign { } { } + assign $0\move_one[0:0] $1\move_one[0:0] + attribute \src "issuer_ls180.v:112701.5-112701.29" + switch \initial + attribute \src "issuer_ls180.v:112701.9-112701.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" + switch \sel_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 3'110 + assign { } { } + assign $1\move_one[0:0] \insn_in [20] + case + assign $1\move_one[0:0] 1'0 + end + sync always + update \move_one $0\move_one[0:0] + end + attribute \src "issuer_ls180.v:112711.3-112726.6" + process $proc$issuer_ls180.v:112711$4393 + assign { } { } + assign { } { } + assign $0\ppick_i[7:0] $1\ppick_i[7:0] + attribute \src "issuer_ls180.v:112712.5-112712.29" + switch \initial + attribute \src "issuer_ls180.v:112712.9-112712.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" + switch \sel_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 3'110 + assign { } { } + assign $1\ppick_i[7:0] $2\ppick_i[7:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" + switch \$3 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\ppick_i[7:0] \DIV_FXM + case + assign $2\ppick_i[7:0] 8'00000000 + end + case + assign $1\ppick_i[7:0] 8'00000000 + end + sync always + update \ppick_i $0\ppick_i[7:0] + end + attribute \src "issuer_ls180.v:112727.3-112745.6" + process $proc$issuer_ls180.v:112727$4394 + assign { } { } + assign { } { } + assign $0\cr_fxm[7:0] $1\cr_fxm[7:0] + attribute \src "issuer_ls180.v:112728.5-112728.29" + switch \initial + attribute \src "issuer_ls180.v:112728.9-112728.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" + switch \sel_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 3'110 + assign { } { } + assign $1\cr_fxm[7:0] $2\cr_fxm[7:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" + switch \$7 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\cr_fxm[7:0] \ppick_o + attribute \src "issuer_ls180.v:0.0-0.0" + case + assign { } { } + assign $2\cr_fxm[7:0] 8'11111111 + end + case + assign $1\cr_fxm[7:0] 8'00000000 + end + sync always + update \cr_fxm $0\cr_fxm[7:0] + end + connect \$1 $eq$issuer_ls180.v:112583$4381_Y + connect \$3 $and$issuer_ls180.v:112584$4382_Y + connect \$5 $eq$issuer_ls180.v:112585$4383_Y + connect \$7 $and$issuer_ls180.v:112586$4384_Y +end +attribute \src "issuer_ls180.v:112750.1-113047.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.dec_MUL.dec_cr_in" +attribute \generator "nMigen" +module \dec_cr_in$180 + attribute \src "issuer_ls180.v:112941.3-112967.6" + wire width 3 $0\cr_bitfield[2:0] + attribute \src "issuer_ls180.v:112968.3-112978.6" + wire width 3 $0\cr_bitfield_b[2:0] + attribute \src "issuer_ls180.v:112919.3-112929.6" + wire $0\cr_bitfield_b_ok[0:0] + attribute \src "issuer_ls180.v:112979.3-112989.6" + wire width 3 $0\cr_bitfield_o[2:0] + attribute \src "issuer_ls180.v:112990.3-113000.6" + wire $0\cr_bitfield_o_ok[0:0] + attribute \src "issuer_ls180.v:112892.3-112918.6" + wire $0\cr_bitfield_ok[0:0] + attribute \src "issuer_ls180.v:113028.3-113046.6" + wire width 8 $0\cr_fxm[7:0] + attribute \src "issuer_ls180.v:112930.3-112940.6" + wire $0\cr_fxm_ok[0:0] + attribute \src "issuer_ls180.v:112751.7-112751.20" + wire $0\initial[0:0] + attribute \src "issuer_ls180.v:113001.3-113011.6" + wire $0\move_one[0:0] + attribute \src "issuer_ls180.v:113012.3-113027.6" + wire width 8 $0\ppick_i[7:0] + attribute \src "issuer_ls180.v:112941.3-112967.6" + wire width 3 $1\cr_bitfield[2:0] + attribute \src "issuer_ls180.v:112968.3-112978.6" + wire width 3 $1\cr_bitfield_b[2:0] + attribute \src "issuer_ls180.v:112919.3-112929.6" + wire $1\cr_bitfield_b_ok[0:0] + attribute \src "issuer_ls180.v:112979.3-112989.6" + wire width 3 $1\cr_bitfield_o[2:0] + attribute \src "issuer_ls180.v:112990.3-113000.6" + wire $1\cr_bitfield_o_ok[0:0] + attribute \src "issuer_ls180.v:112892.3-112918.6" + wire $1\cr_bitfield_ok[0:0] + attribute \src "issuer_ls180.v:113028.3-113046.6" + wire width 8 $1\cr_fxm[7:0] + attribute \src "issuer_ls180.v:112930.3-112940.6" + wire $1\cr_fxm_ok[0:0] + attribute \src "issuer_ls180.v:113001.3-113011.6" + wire $1\move_one[0:0] + attribute \src "issuer_ls180.v:113012.3-113027.6" + wire width 8 $1\ppick_i[7:0] + attribute \src "issuer_ls180.v:113028.3-113046.6" + wire width 8 $2\cr_fxm[7:0] + attribute \src "issuer_ls180.v:113012.3-113027.6" + wire width 8 $2\ppick_i[7:0] + attribute \src "issuer_ls180.v:112885.17-112885.112" + wire $and$issuer_ls180.v:112885$4397_Y + attribute \src "issuer_ls180.v:112887.17-112887.112" + wire $and$issuer_ls180.v:112887$4399_Y + attribute \src "issuer_ls180.v:112884.17-112884.121" + wire $eq$issuer_ls180.v:112884$4396_Y + attribute \src "issuer_ls180.v:112886.17-112886.121" + wire $eq$issuer_ls180.v:112886$4398_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 input 4 \MUL_BA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 input 3 \MUL_BB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 input 8 \MUL_BC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 input 7 \MUL_BI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 input 5 \MUL_BT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 8 input 6 \MUL_FXM + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 7 input 2 \MUL_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 3 input 9 \X_BFA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 3 \cr_bitfield + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 3 \cr_bitfield_b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \cr_bitfield_b_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 3 \cr_bitfield_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \cr_bitfield_o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \cr_bitfield_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 8 \cr_fxm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \cr_fxm_ok + attribute \src "issuer_ls180.v:112751.7-112751.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:485" + wire width 32 input 10 \insn_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:526" + wire \move_one + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" + wire width 8 \ppick_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" + wire width 8 \ppick_o + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:484" + wire width 3 input 1 \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" + cell $and $and$issuer_ls180.v:112885$4397 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$1 + connect \B \move_one + connect \Y $and$issuer_ls180.v:112885$4397_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" + cell $and $and$issuer_ls180.v:112887$4399 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$5 + connect \B \move_one + connect \Y $and$issuer_ls180.v:112887$4399_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" + cell $eq $eq$issuer_ls180.v:112884$4396 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \MUL_internal_op + connect \B 7'0101101 + connect \Y $eq$issuer_ls180.v:112884$4396_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" + cell $eq $eq$issuer_ls180.v:112886$4398 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \MUL_internal_op + connect \B 7'0101101 + connect \Y $eq$issuer_ls180.v:112886$4398_Y + end + attribute \module_not_derived 1 + attribute \src "issuer_ls180.v:112888.15-112891.4" + cell \ppick$181 \ppick + connect \i \ppick_i + connect \o \ppick_o + end + attribute \src "issuer_ls180.v:112751.7-112751.20" + process $proc$issuer_ls180.v:112751$4410 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "issuer_ls180.v:112892.3-112918.6" + process $proc$issuer_ls180.v:112892$4400 + assign { } { } + assign { } { } + assign $0\cr_bitfield_ok[0:0] $1\cr_bitfield_ok[0:0] + attribute \src "issuer_ls180.v:112893.5-112893.29" + switch \initial + attribute \src "issuer_ls180.v:112893.9-112893.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" + switch \sel_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 3'001 + assign { } { } + assign $1\cr_bitfield_ok[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 3'010 + assign { } { } + assign $1\cr_bitfield_ok[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 3'011 + assign { } { } + assign $1\cr_bitfield_ok[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 3'100 + assign { } { } + assign $1\cr_bitfield_ok[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 3'101 + assign { } { } + assign $1\cr_bitfield_ok[0:0] 1'1 + case + assign $1\cr_bitfield_ok[0:0] 1'0 + end + sync always + update \cr_bitfield_ok $0\cr_bitfield_ok[0:0] + end + attribute \src "issuer_ls180.v:112919.3-112929.6" + process $proc$issuer_ls180.v:112919$4401 + assign { } { } + assign { } { } + assign $0\cr_bitfield_b_ok[0:0] $1\cr_bitfield_b_ok[0:0] + attribute \src "issuer_ls180.v:112920.5-112920.29" + switch \initial + attribute \src "issuer_ls180.v:112920.9-112920.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" + switch \sel_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 3'100 + assign { } { } + assign $1\cr_bitfield_b_ok[0:0] 1'1 + case + assign $1\cr_bitfield_b_ok[0:0] 1'0 + end + sync always + update \cr_bitfield_b_ok $0\cr_bitfield_b_ok[0:0] + end + attribute \src "issuer_ls180.v:112930.3-112940.6" + process $proc$issuer_ls180.v:112930$4402 + assign { } { } + assign { } { } + assign $0\cr_fxm_ok[0:0] $1\cr_fxm_ok[0:0] + attribute \src "issuer_ls180.v:112931.5-112931.29" + switch \initial + attribute \src "issuer_ls180.v:112931.9-112931.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" + switch \sel_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 3'110 + assign { } { } + assign $1\cr_fxm_ok[0:0] 1'1 + case + assign $1\cr_fxm_ok[0:0] 1'0 + end + sync always + update \cr_fxm_ok $0\cr_fxm_ok[0:0] + end + attribute \src "issuer_ls180.v:112941.3-112967.6" + process $proc$issuer_ls180.v:112941$4403 + assign { } { } + assign { } { } + assign $0\cr_bitfield[2:0] $1\cr_bitfield[2:0] + attribute \src "issuer_ls180.v:112942.5-112942.29" + switch \initial + attribute \src "issuer_ls180.v:112942.9-112942.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" + switch \sel_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 3'001 + assign { } { } + assign $1\cr_bitfield[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 3'010 + assign { } { } + assign $1\cr_bitfield[2:0] \MUL_BI [4:2] + attribute \src "issuer_ls180.v:0.0-0.0" + case 3'011 + assign { } { } + assign $1\cr_bitfield[2:0] \X_BFA + attribute \src "issuer_ls180.v:0.0-0.0" + case 3'100 + assign { } { } + assign $1\cr_bitfield[2:0] \MUL_BA [4:2] + attribute \src "issuer_ls180.v:0.0-0.0" + case 3'101 + assign { } { } + assign $1\cr_bitfield[2:0] \MUL_BC [4:2] + case + assign $1\cr_bitfield[2:0] 3'000 + end + sync always + update \cr_bitfield $0\cr_bitfield[2:0] + end + attribute \src "issuer_ls180.v:112968.3-112978.6" + process $proc$issuer_ls180.v:112968$4404 + assign { } { } + assign { } { } + assign $0\cr_bitfield_b[2:0] $1\cr_bitfield_b[2:0] + attribute \src "issuer_ls180.v:112969.5-112969.29" + switch \initial + attribute \src "issuer_ls180.v:112969.9-112969.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" + switch \sel_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 3'100 + assign { } { } + assign $1\cr_bitfield_b[2:0] \MUL_BB [4:2] + case + assign $1\cr_bitfield_b[2:0] 3'000 + end + sync always + update \cr_bitfield_b $0\cr_bitfield_b[2:0] + end + attribute \src "issuer_ls180.v:112979.3-112989.6" + process $proc$issuer_ls180.v:112979$4405 + assign { } { } + assign { } { } + assign $0\cr_bitfield_o[2:0] $1\cr_bitfield_o[2:0] + attribute \src "issuer_ls180.v:112980.5-112980.29" + switch \initial + attribute \src "issuer_ls180.v:112980.9-112980.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" + switch \sel_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 3'100 + assign { } { } + assign $1\cr_bitfield_o[2:0] \MUL_BT [4:2] + case + assign $1\cr_bitfield_o[2:0] 3'000 + end + sync always + update \cr_bitfield_o $0\cr_bitfield_o[2:0] + end + attribute \src "issuer_ls180.v:112990.3-113000.6" + process $proc$issuer_ls180.v:112990$4406 + assign { } { } + assign { } { } + assign $0\cr_bitfield_o_ok[0:0] $1\cr_bitfield_o_ok[0:0] + attribute \src "issuer_ls180.v:112991.5-112991.29" + switch \initial + attribute \src "issuer_ls180.v:112991.9-112991.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" + switch \sel_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 3'100 + assign { } { } + assign $1\cr_bitfield_o_ok[0:0] 1'1 + case + assign $1\cr_bitfield_o_ok[0:0] 1'0 + end + sync always + update \cr_bitfield_o_ok $0\cr_bitfield_o_ok[0:0] + end + attribute \src "issuer_ls180.v:113001.3-113011.6" + process $proc$issuer_ls180.v:113001$4407 + assign { } { } + assign { } { } + assign $0\move_one[0:0] $1\move_one[0:0] + attribute \src "issuer_ls180.v:113002.5-113002.29" + switch \initial + attribute \src "issuer_ls180.v:113002.9-113002.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" + switch \sel_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 3'110 + assign { } { } + assign $1\move_one[0:0] \insn_in [20] + case + assign $1\move_one[0:0] 1'0 + end + sync always + update \move_one $0\move_one[0:0] + end + attribute \src "issuer_ls180.v:113012.3-113027.6" + process $proc$issuer_ls180.v:113012$4408 + assign { } { } + assign { } { } + assign $0\ppick_i[7:0] $1\ppick_i[7:0] + attribute \src "issuer_ls180.v:113013.5-113013.29" + switch \initial + attribute \src "issuer_ls180.v:113013.9-113013.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" + switch \sel_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 3'110 + assign { } { } + assign $1\ppick_i[7:0] $2\ppick_i[7:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" + switch \$3 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\ppick_i[7:0] \MUL_FXM + case + assign $2\ppick_i[7:0] 8'00000000 + end + case + assign $1\ppick_i[7:0] 8'00000000 + end + sync always + update \ppick_i $0\ppick_i[7:0] + end + attribute \src "issuer_ls180.v:113028.3-113046.6" + process $proc$issuer_ls180.v:113028$4409 + assign { } { } + assign { } { } + assign $0\cr_fxm[7:0] $1\cr_fxm[7:0] + attribute \src "issuer_ls180.v:113029.5-113029.29" + switch \initial + attribute \src "issuer_ls180.v:113029.9-113029.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" + switch \sel_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 3'110 + assign { } { } + assign $1\cr_fxm[7:0] $2\cr_fxm[7:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" + switch \$7 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\cr_fxm[7:0] \ppick_o + attribute \src "issuer_ls180.v:0.0-0.0" + case + assign { } { } + assign $2\cr_fxm[7:0] 8'11111111 + end + case + assign $1\cr_fxm[7:0] 8'00000000 + end + sync always + update \cr_fxm $0\cr_fxm[7:0] + end + connect \$1 $eq$issuer_ls180.v:112884$4396_Y + connect \$3 $and$issuer_ls180.v:112885$4397_Y + connect \$5 $eq$issuer_ls180.v:112886$4398_Y + connect \$7 $and$issuer_ls180.v:112887$4399_Y +end +attribute \src "issuer_ls180.v:113051.1-113348.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.dec_SHIFT_ROT.dec_cr_in" +attribute \generator "nMigen" +module \dec_cr_in$188 + attribute \src "issuer_ls180.v:113242.3-113268.6" + wire width 3 $0\cr_bitfield[2:0] + attribute \src "issuer_ls180.v:113269.3-113279.6" + wire width 3 $0\cr_bitfield_b[2:0] + attribute \src "issuer_ls180.v:113220.3-113230.6" + wire $0\cr_bitfield_b_ok[0:0] + attribute \src "issuer_ls180.v:113280.3-113290.6" + wire width 3 $0\cr_bitfield_o[2:0] + attribute \src "issuer_ls180.v:113291.3-113301.6" + wire $0\cr_bitfield_o_ok[0:0] + attribute \src "issuer_ls180.v:113193.3-113219.6" + wire $0\cr_bitfield_ok[0:0] + attribute \src "issuer_ls180.v:113329.3-113347.6" + wire width 8 $0\cr_fxm[7:0] + attribute \src "issuer_ls180.v:113231.3-113241.6" + wire $0\cr_fxm_ok[0:0] + attribute \src "issuer_ls180.v:113052.7-113052.20" + wire $0\initial[0:0] + attribute \src "issuer_ls180.v:113302.3-113312.6" + wire $0\move_one[0:0] + attribute \src "issuer_ls180.v:113313.3-113328.6" + wire width 8 $0\ppick_i[7:0] + attribute \src "issuer_ls180.v:113242.3-113268.6" + wire width 3 $1\cr_bitfield[2:0] + attribute \src "issuer_ls180.v:113269.3-113279.6" + wire width 3 $1\cr_bitfield_b[2:0] + attribute \src "issuer_ls180.v:113220.3-113230.6" + wire $1\cr_bitfield_b_ok[0:0] + attribute \src "issuer_ls180.v:113280.3-113290.6" + wire width 3 $1\cr_bitfield_o[2:0] + attribute \src "issuer_ls180.v:113291.3-113301.6" + wire $1\cr_bitfield_o_ok[0:0] + attribute \src "issuer_ls180.v:113193.3-113219.6" + wire $1\cr_bitfield_ok[0:0] + attribute \src "issuer_ls180.v:113329.3-113347.6" + wire width 8 $1\cr_fxm[7:0] + attribute \src "issuer_ls180.v:113231.3-113241.6" + wire $1\cr_fxm_ok[0:0] + attribute \src "issuer_ls180.v:113302.3-113312.6" + wire $1\move_one[0:0] + attribute \src "issuer_ls180.v:113313.3-113328.6" + wire width 8 $1\ppick_i[7:0] + attribute \src "issuer_ls180.v:113329.3-113347.6" + wire width 8 $2\cr_fxm[7:0] + attribute \src "issuer_ls180.v:113313.3-113328.6" + wire width 8 $2\ppick_i[7:0] + attribute \src "issuer_ls180.v:113186.17-113186.112" + wire $and$issuer_ls180.v:113186$4412_Y + attribute \src "issuer_ls180.v:113188.17-113188.112" + wire $and$issuer_ls180.v:113188$4414_Y + attribute \src "issuer_ls180.v:113185.17-113185.127" + wire $eq$issuer_ls180.v:113185$4411_Y + attribute \src "issuer_ls180.v:113187.17-113187.127" + wire $eq$issuer_ls180.v:113187$4413_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 input 4 \SHIFT_ROT_BA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 input 3 \SHIFT_ROT_BB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 input 8 \SHIFT_ROT_BC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 input 7 \SHIFT_ROT_BI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 input 5 \SHIFT_ROT_BT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 8 input 6 \SHIFT_ROT_FXM + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 7 input 2 \SHIFT_ROT_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 3 input 9 \X_BFA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 3 \cr_bitfield + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 3 \cr_bitfield_b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \cr_bitfield_b_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 3 \cr_bitfield_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \cr_bitfield_o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \cr_bitfield_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 8 \cr_fxm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \cr_fxm_ok + attribute \src "issuer_ls180.v:113052.7-113052.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:485" + wire width 32 input 10 \insn_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:526" + wire \move_one + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" + wire width 8 \ppick_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" + wire width 8 \ppick_o + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:484" + wire width 3 input 1 \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" + cell $and $and$issuer_ls180.v:113186$4412 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$1 + connect \B \move_one + connect \Y $and$issuer_ls180.v:113186$4412_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" + cell $and $and$issuer_ls180.v:113188$4414 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$5 + connect \B \move_one + connect \Y $and$issuer_ls180.v:113188$4414_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" + cell $eq $eq$issuer_ls180.v:113185$4411 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \SHIFT_ROT_internal_op + connect \B 7'0101101 + connect \Y $eq$issuer_ls180.v:113185$4411_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" + cell $eq $eq$issuer_ls180.v:113187$4413 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \SHIFT_ROT_internal_op + connect \B 7'0101101 + connect \Y $eq$issuer_ls180.v:113187$4413_Y + end + attribute \module_not_derived 1 + attribute \src "issuer_ls180.v:113189.15-113192.4" + cell \ppick$189 \ppick + connect \i \ppick_i + connect \o \ppick_o + end + attribute \src "issuer_ls180.v:113052.7-113052.20" + process $proc$issuer_ls180.v:113052$4425 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "issuer_ls180.v:113193.3-113219.6" + process $proc$issuer_ls180.v:113193$4415 + assign { } { } + assign { } { } + assign $0\cr_bitfield_ok[0:0] $1\cr_bitfield_ok[0:0] + attribute \src "issuer_ls180.v:113194.5-113194.29" + switch \initial + attribute \src "issuer_ls180.v:113194.9-113194.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" + switch \sel_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 3'001 + assign { } { } + assign $1\cr_bitfield_ok[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 3'010 + assign { } { } + assign $1\cr_bitfield_ok[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 3'011 + assign { } { } + assign $1\cr_bitfield_ok[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 3'100 + assign { } { } + assign $1\cr_bitfield_ok[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 3'101 + assign { } { } + assign $1\cr_bitfield_ok[0:0] 1'1 + case + assign $1\cr_bitfield_ok[0:0] 1'0 + end + sync always + update \cr_bitfield_ok $0\cr_bitfield_ok[0:0] + end + attribute \src "issuer_ls180.v:113220.3-113230.6" + process $proc$issuer_ls180.v:113220$4416 + assign { } { } + assign { } { } + assign $0\cr_bitfield_b_ok[0:0] $1\cr_bitfield_b_ok[0:0] + attribute \src "issuer_ls180.v:113221.5-113221.29" + switch \initial + attribute \src "issuer_ls180.v:113221.9-113221.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" + switch \sel_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 3'100 + assign { } { } + assign $1\cr_bitfield_b_ok[0:0] 1'1 + case + assign $1\cr_bitfield_b_ok[0:0] 1'0 + end + sync always + update \cr_bitfield_b_ok $0\cr_bitfield_b_ok[0:0] + end + attribute \src "issuer_ls180.v:113231.3-113241.6" + process $proc$issuer_ls180.v:113231$4417 + assign { } { } + assign { } { } + assign $0\cr_fxm_ok[0:0] $1\cr_fxm_ok[0:0] + attribute \src "issuer_ls180.v:113232.5-113232.29" + switch \initial + attribute \src "issuer_ls180.v:113232.9-113232.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" + switch \sel_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 3'110 + assign { } { } + assign $1\cr_fxm_ok[0:0] 1'1 + case + assign $1\cr_fxm_ok[0:0] 1'0 + end + sync always + update \cr_fxm_ok $0\cr_fxm_ok[0:0] + end + attribute \src "issuer_ls180.v:113242.3-113268.6" + process $proc$issuer_ls180.v:113242$4418 + assign { } { } + assign { } { } + assign $0\cr_bitfield[2:0] $1\cr_bitfield[2:0] + attribute \src "issuer_ls180.v:113243.5-113243.29" + switch \initial + attribute \src "issuer_ls180.v:113243.9-113243.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" + switch \sel_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 3'001 + assign { } { } + assign $1\cr_bitfield[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 3'010 + assign { } { } + assign $1\cr_bitfield[2:0] \SHIFT_ROT_BI [4:2] + attribute \src "issuer_ls180.v:0.0-0.0" + case 3'011 + assign { } { } + assign $1\cr_bitfield[2:0] \X_BFA + attribute \src "issuer_ls180.v:0.0-0.0" + case 3'100 + assign { } { } + assign $1\cr_bitfield[2:0] \SHIFT_ROT_BA [4:2] + attribute \src "issuer_ls180.v:0.0-0.0" + case 3'101 + assign { } { } + assign $1\cr_bitfield[2:0] \SHIFT_ROT_BC [4:2] + case + assign $1\cr_bitfield[2:0] 3'000 + end + sync always + update \cr_bitfield $0\cr_bitfield[2:0] + end + attribute \src "issuer_ls180.v:113269.3-113279.6" + process $proc$issuer_ls180.v:113269$4419 + assign { } { } + assign { } { } + assign $0\cr_bitfield_b[2:0] $1\cr_bitfield_b[2:0] + attribute \src "issuer_ls180.v:113270.5-113270.29" + switch \initial + attribute \src "issuer_ls180.v:113270.9-113270.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" + switch \sel_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 3'100 + assign { } { } + assign $1\cr_bitfield_b[2:0] \SHIFT_ROT_BB [4:2] + case + assign $1\cr_bitfield_b[2:0] 3'000 + end + sync always + update \cr_bitfield_b $0\cr_bitfield_b[2:0] + end + attribute \src "issuer_ls180.v:113280.3-113290.6" + process $proc$issuer_ls180.v:113280$4420 + assign { } { } + assign { } { } + assign $0\cr_bitfield_o[2:0] $1\cr_bitfield_o[2:0] + attribute \src "issuer_ls180.v:113281.5-113281.29" + switch \initial + attribute \src "issuer_ls180.v:113281.9-113281.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" + switch \sel_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 3'100 + assign { } { } + assign $1\cr_bitfield_o[2:0] \SHIFT_ROT_BT [4:2] + case + assign $1\cr_bitfield_o[2:0] 3'000 + end + sync always + update \cr_bitfield_o $0\cr_bitfield_o[2:0] + end + attribute \src "issuer_ls180.v:113291.3-113301.6" + process $proc$issuer_ls180.v:113291$4421 + assign { } { } + assign { } { } + assign $0\cr_bitfield_o_ok[0:0] $1\cr_bitfield_o_ok[0:0] + attribute \src "issuer_ls180.v:113292.5-113292.29" + switch \initial + attribute \src "issuer_ls180.v:113292.9-113292.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" + switch \sel_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 3'100 + assign { } { } + assign $1\cr_bitfield_o_ok[0:0] 1'1 + case + assign $1\cr_bitfield_o_ok[0:0] 1'0 + end + sync always + update \cr_bitfield_o_ok $0\cr_bitfield_o_ok[0:0] + end + attribute \src "issuer_ls180.v:113302.3-113312.6" + process $proc$issuer_ls180.v:113302$4422 + assign { } { } + assign { } { } + assign $0\move_one[0:0] $1\move_one[0:0] + attribute \src "issuer_ls180.v:113303.5-113303.29" + switch \initial + attribute \src "issuer_ls180.v:113303.9-113303.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" + switch \sel_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 3'110 + assign { } { } + assign $1\move_one[0:0] \insn_in [20] + case + assign $1\move_one[0:0] 1'0 + end + sync always + update \move_one $0\move_one[0:0] + end + attribute \src "issuer_ls180.v:113313.3-113328.6" + process $proc$issuer_ls180.v:113313$4423 + assign { } { } + assign { } { } + assign $0\ppick_i[7:0] $1\ppick_i[7:0] + attribute \src "issuer_ls180.v:113314.5-113314.29" + switch \initial + attribute \src "issuer_ls180.v:113314.9-113314.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" + switch \sel_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 3'110 + assign { } { } + assign $1\ppick_i[7:0] $2\ppick_i[7:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" + switch \$3 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\ppick_i[7:0] \SHIFT_ROT_FXM + case + assign $2\ppick_i[7:0] 8'00000000 + end + case + assign $1\ppick_i[7:0] 8'00000000 + end + sync always + update \ppick_i $0\ppick_i[7:0] + end + attribute \src "issuer_ls180.v:113329.3-113347.6" + process $proc$issuer_ls180.v:113329$4424 + assign { } { } + assign { } { } + assign $0\cr_fxm[7:0] $1\cr_fxm[7:0] + attribute \src "issuer_ls180.v:113330.5-113330.29" + switch \initial + attribute \src "issuer_ls180.v:113330.9-113330.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" + switch \sel_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 3'110 + assign { } { } + assign $1\cr_fxm[7:0] $2\cr_fxm[7:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" + switch \$7 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\cr_fxm[7:0] \ppick_o + attribute \src "issuer_ls180.v:0.0-0.0" + case + assign { } { } + assign $2\cr_fxm[7:0] 8'11111111 + end + case + assign $1\cr_fxm[7:0] 8'00000000 + end + sync always + update \cr_fxm $0\cr_fxm[7:0] + end + connect \$1 $eq$issuer_ls180.v:113185$4411_Y + connect \$3 $and$issuer_ls180.v:113186$4412_Y + connect \$5 $eq$issuer_ls180.v:113187$4413_Y + connect \$7 $and$issuer_ls180.v:113188$4414_Y +end +attribute \src "issuer_ls180.v:113352.1-113649.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.dec_LDST.dec_cr_in" +attribute \generator "nMigen" +module \dec_cr_in$196 + attribute \src "issuer_ls180.v:113543.3-113569.6" + wire width 3 $0\cr_bitfield[2:0] + attribute \src "issuer_ls180.v:113570.3-113580.6" + wire width 3 $0\cr_bitfield_b[2:0] + attribute \src "issuer_ls180.v:113521.3-113531.6" + wire $0\cr_bitfield_b_ok[0:0] + attribute \src "issuer_ls180.v:113581.3-113591.6" + wire width 3 $0\cr_bitfield_o[2:0] + attribute \src "issuer_ls180.v:113592.3-113602.6" + wire $0\cr_bitfield_o_ok[0:0] + attribute \src "issuer_ls180.v:113494.3-113520.6" + wire $0\cr_bitfield_ok[0:0] + attribute \src "issuer_ls180.v:113630.3-113648.6" + wire width 8 $0\cr_fxm[7:0] + attribute \src "issuer_ls180.v:113532.3-113542.6" + wire $0\cr_fxm_ok[0:0] + attribute \src "issuer_ls180.v:113353.7-113353.20" + wire $0\initial[0:0] + attribute \src "issuer_ls180.v:113603.3-113613.6" + wire $0\move_one[0:0] + attribute \src "issuer_ls180.v:113614.3-113629.6" + wire width 8 $0\ppick_i[7:0] + attribute \src "issuer_ls180.v:113543.3-113569.6" + wire width 3 $1\cr_bitfield[2:0] + attribute \src "issuer_ls180.v:113570.3-113580.6" + wire width 3 $1\cr_bitfield_b[2:0] + attribute \src "issuer_ls180.v:113521.3-113531.6" + wire $1\cr_bitfield_b_ok[0:0] + attribute \src "issuer_ls180.v:113581.3-113591.6" + wire width 3 $1\cr_bitfield_o[2:0] + attribute \src "issuer_ls180.v:113592.3-113602.6" + wire $1\cr_bitfield_o_ok[0:0] + attribute \src "issuer_ls180.v:113494.3-113520.6" + wire $1\cr_bitfield_ok[0:0] + attribute \src "issuer_ls180.v:113630.3-113648.6" + wire width 8 $1\cr_fxm[7:0] + attribute \src "issuer_ls180.v:113532.3-113542.6" + wire $1\cr_fxm_ok[0:0] + attribute \src "issuer_ls180.v:113603.3-113613.6" + wire $1\move_one[0:0] + attribute \src "issuer_ls180.v:113614.3-113629.6" + wire width 8 $1\ppick_i[7:0] + attribute \src "issuer_ls180.v:113630.3-113648.6" + wire width 8 $2\cr_fxm[7:0] + attribute \src "issuer_ls180.v:113614.3-113629.6" + wire width 8 $2\ppick_i[7:0] + attribute \src "issuer_ls180.v:113487.17-113487.112" + wire $and$issuer_ls180.v:113487$4427_Y + attribute \src "issuer_ls180.v:113489.17-113489.112" + wire $and$issuer_ls180.v:113489$4429_Y + attribute \src "issuer_ls180.v:113486.17-113486.122" + wire $eq$issuer_ls180.v:113486$4426_Y + attribute \src "issuer_ls180.v:113488.17-113488.122" + wire $eq$issuer_ls180.v:113488$4428_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 input 4 \LDST_BA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 input 3 \LDST_BB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 input 8 \LDST_BC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 input 7 \LDST_BI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 input 5 \LDST_BT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 8 input 6 \LDST_FXM + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 7 input 2 \LDST_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 3 input 9 \X_BFA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 3 \cr_bitfield + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 3 \cr_bitfield_b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \cr_bitfield_b_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 3 \cr_bitfield_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \cr_bitfield_o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \cr_bitfield_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 8 \cr_fxm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \cr_fxm_ok + attribute \src "issuer_ls180.v:113353.7-113353.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:485" + wire width 32 input 10 \insn_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:526" + wire \move_one + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" + wire width 8 \ppick_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" + wire width 8 \ppick_o + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:484" + wire width 3 input 1 \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" + cell $and $and$issuer_ls180.v:113487$4427 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$1 + connect \B \move_one + connect \Y $and$issuer_ls180.v:113487$4427_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" + cell $and $and$issuer_ls180.v:113489$4429 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$5 + connect \B \move_one + connect \Y $and$issuer_ls180.v:113489$4429_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" + cell $eq $eq$issuer_ls180.v:113486$4426 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \LDST_internal_op + connect \B 7'0101101 + connect \Y $eq$issuer_ls180.v:113486$4426_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" + cell $eq $eq$issuer_ls180.v:113488$4428 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \LDST_internal_op + connect \B 7'0101101 + connect \Y $eq$issuer_ls180.v:113488$4428_Y + end + attribute \module_not_derived 1 + attribute \src "issuer_ls180.v:113490.15-113493.4" + cell \ppick$197 \ppick + connect \i \ppick_i + connect \o \ppick_o + end + attribute \src "issuer_ls180.v:113353.7-113353.20" + process $proc$issuer_ls180.v:113353$4440 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "issuer_ls180.v:113494.3-113520.6" + process $proc$issuer_ls180.v:113494$4430 + assign { } { } + assign { } { } + assign $0\cr_bitfield_ok[0:0] $1\cr_bitfield_ok[0:0] + attribute \src "issuer_ls180.v:113495.5-113495.29" + switch \initial + attribute \src "issuer_ls180.v:113495.9-113495.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" + switch \sel_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 3'001 + assign { } { } + assign $1\cr_bitfield_ok[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 3'010 + assign { } { } + assign $1\cr_bitfield_ok[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 3'011 + assign { } { } + assign $1\cr_bitfield_ok[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 3'100 + assign { } { } + assign $1\cr_bitfield_ok[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 3'101 + assign { } { } + assign $1\cr_bitfield_ok[0:0] 1'1 + case + assign $1\cr_bitfield_ok[0:0] 1'0 + end + sync always + update \cr_bitfield_ok $0\cr_bitfield_ok[0:0] + end + attribute \src "issuer_ls180.v:113521.3-113531.6" + process $proc$issuer_ls180.v:113521$4431 + assign { } { } + assign { } { } + assign $0\cr_bitfield_b_ok[0:0] $1\cr_bitfield_b_ok[0:0] + attribute \src "issuer_ls180.v:113522.5-113522.29" + switch \initial + attribute \src "issuer_ls180.v:113522.9-113522.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" + switch \sel_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 3'100 + assign { } { } + assign $1\cr_bitfield_b_ok[0:0] 1'1 + case + assign $1\cr_bitfield_b_ok[0:0] 1'0 + end + sync always + update \cr_bitfield_b_ok $0\cr_bitfield_b_ok[0:0] + end + attribute \src "issuer_ls180.v:113532.3-113542.6" + process $proc$issuer_ls180.v:113532$4432 + assign { } { } + assign { } { } + assign $0\cr_fxm_ok[0:0] $1\cr_fxm_ok[0:0] + attribute \src "issuer_ls180.v:113533.5-113533.29" + switch \initial + attribute \src "issuer_ls180.v:113533.9-113533.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" + switch \sel_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 3'110 + assign { } { } + assign $1\cr_fxm_ok[0:0] 1'1 + case + assign $1\cr_fxm_ok[0:0] 1'0 + end + sync always + update \cr_fxm_ok $0\cr_fxm_ok[0:0] + end + attribute \src "issuer_ls180.v:113543.3-113569.6" + process $proc$issuer_ls180.v:113543$4433 + assign { } { } + assign { } { } + assign $0\cr_bitfield[2:0] $1\cr_bitfield[2:0] + attribute \src "issuer_ls180.v:113544.5-113544.29" + switch \initial + attribute \src "issuer_ls180.v:113544.9-113544.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" + switch \sel_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 3'001 + assign { } { } + assign $1\cr_bitfield[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 3'010 + assign { } { } + assign $1\cr_bitfield[2:0] \LDST_BI [4:2] + attribute \src "issuer_ls180.v:0.0-0.0" + case 3'011 + assign { } { } + assign $1\cr_bitfield[2:0] \X_BFA + attribute \src "issuer_ls180.v:0.0-0.0" + case 3'100 + assign { } { } + assign $1\cr_bitfield[2:0] \LDST_BA [4:2] + attribute \src "issuer_ls180.v:0.0-0.0" + case 3'101 + assign { } { } + assign $1\cr_bitfield[2:0] \LDST_BC [4:2] + case + assign $1\cr_bitfield[2:0] 3'000 + end + sync always + update \cr_bitfield $0\cr_bitfield[2:0] + end + attribute \src "issuer_ls180.v:113570.3-113580.6" + process $proc$issuer_ls180.v:113570$4434 + assign { } { } + assign { } { } + assign $0\cr_bitfield_b[2:0] $1\cr_bitfield_b[2:0] + attribute \src "issuer_ls180.v:113571.5-113571.29" + switch \initial + attribute \src "issuer_ls180.v:113571.9-113571.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" + switch \sel_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 3'100 + assign { } { } + assign $1\cr_bitfield_b[2:0] \LDST_BB [4:2] + case + assign $1\cr_bitfield_b[2:0] 3'000 + end + sync always + update \cr_bitfield_b $0\cr_bitfield_b[2:0] + end + attribute \src "issuer_ls180.v:113581.3-113591.6" + process $proc$issuer_ls180.v:113581$4435 + assign { } { } + assign { } { } + assign $0\cr_bitfield_o[2:0] $1\cr_bitfield_o[2:0] + attribute \src "issuer_ls180.v:113582.5-113582.29" + switch \initial + attribute \src "issuer_ls180.v:113582.9-113582.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" + switch \sel_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 3'100 + assign { } { } + assign $1\cr_bitfield_o[2:0] \LDST_BT [4:2] + case + assign $1\cr_bitfield_o[2:0] 3'000 + end + sync always + update \cr_bitfield_o $0\cr_bitfield_o[2:0] + end + attribute \src "issuer_ls180.v:113592.3-113602.6" + process $proc$issuer_ls180.v:113592$4436 + assign { } { } + assign { } { } + assign $0\cr_bitfield_o_ok[0:0] $1\cr_bitfield_o_ok[0:0] + attribute \src "issuer_ls180.v:113593.5-113593.29" + switch \initial + attribute \src "issuer_ls180.v:113593.9-113593.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" + switch \sel_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 3'100 + assign { } { } + assign $1\cr_bitfield_o_ok[0:0] 1'1 + case + assign $1\cr_bitfield_o_ok[0:0] 1'0 + end + sync always + update \cr_bitfield_o_ok $0\cr_bitfield_o_ok[0:0] + end + attribute \src "issuer_ls180.v:113603.3-113613.6" + process $proc$issuer_ls180.v:113603$4437 + assign { } { } + assign { } { } + assign $0\move_one[0:0] $1\move_one[0:0] + attribute \src "issuer_ls180.v:113604.5-113604.29" + switch \initial + attribute \src "issuer_ls180.v:113604.9-113604.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" + switch \sel_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 3'110 + assign { } { } + assign $1\move_one[0:0] \insn_in [20] + case + assign $1\move_one[0:0] 1'0 + end + sync always + update \move_one $0\move_one[0:0] + end + attribute \src "issuer_ls180.v:113614.3-113629.6" + process $proc$issuer_ls180.v:113614$4438 + assign { } { } + assign { } { } + assign $0\ppick_i[7:0] $1\ppick_i[7:0] + attribute \src "issuer_ls180.v:113615.5-113615.29" + switch \initial + attribute \src "issuer_ls180.v:113615.9-113615.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" + switch \sel_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 3'110 + assign { } { } + assign $1\ppick_i[7:0] $2\ppick_i[7:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" + switch \$3 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\ppick_i[7:0] \LDST_FXM + case + assign $2\ppick_i[7:0] 8'00000000 + end + case + assign $1\ppick_i[7:0] 8'00000000 + end + sync always + update \ppick_i $0\ppick_i[7:0] + end + attribute \src "issuer_ls180.v:113630.3-113648.6" + process $proc$issuer_ls180.v:113630$4439 + assign { } { } + assign { } { } + assign $0\cr_fxm[7:0] $1\cr_fxm[7:0] + attribute \src "issuer_ls180.v:113631.5-113631.29" + switch \initial + attribute \src "issuer_ls180.v:113631.9-113631.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" + switch \sel_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 3'110 + assign { } { } + assign $1\cr_fxm[7:0] $2\cr_fxm[7:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" + switch \$7 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\cr_fxm[7:0] \ppick_o + attribute \src "issuer_ls180.v:0.0-0.0" + case + assign { } { } + assign $2\cr_fxm[7:0] 8'11111111 + end + case + assign $1\cr_fxm[7:0] 8'00000000 + end + sync always + update \cr_fxm $0\cr_fxm[7:0] + end + connect \$1 $eq$issuer_ls180.v:113486$4426_Y + connect \$3 $and$issuer_ls180.v:113487$4427_Y + connect \$5 $eq$issuer_ls180.v:113488$4428_Y + connect \$7 $and$issuer_ls180.v:113489$4429_Y +end +attribute \src "issuer_ls180.v:113653.1-113958.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.dec2.dec_cr_in" +attribute \generator "nMigen" +module \dec_cr_in$205 + attribute \src "issuer_ls180.v:113852.3-113878.6" + wire width 3 $0\cr_bitfield[2:0] + attribute \src "issuer_ls180.v:113879.3-113889.6" + wire width 3 $0\cr_bitfield_b[2:0] + attribute \src "issuer_ls180.v:113830.3-113840.6" + wire $0\cr_bitfield_b_ok[0:0] + attribute \src "issuer_ls180.v:113890.3-113900.6" + wire width 3 $0\cr_bitfield_o[2:0] + attribute \src "issuer_ls180.v:113901.3-113911.6" + wire $0\cr_bitfield_o_ok[0:0] + attribute \src "issuer_ls180.v:113803.3-113829.6" + wire $0\cr_bitfield_ok[0:0] + attribute \src "issuer_ls180.v:113939.3-113957.6" + wire width 8 $0\cr_fxm[7:0] + attribute \src "issuer_ls180.v:113841.3-113851.6" + wire $0\cr_fxm_ok[0:0] + attribute \src "issuer_ls180.v:113654.7-113654.20" + wire $0\initial[0:0] + attribute \src "issuer_ls180.v:113912.3-113922.6" + wire $0\move_one[0:0] + attribute \src "issuer_ls180.v:113923.3-113938.6" + wire width 8 $0\ppick_i[7:0] + attribute \src "issuer_ls180.v:113852.3-113878.6" + wire width 3 $1\cr_bitfield[2:0] + attribute \src "issuer_ls180.v:113879.3-113889.6" + wire width 3 $1\cr_bitfield_b[2:0] + attribute \src "issuer_ls180.v:113830.3-113840.6" + wire $1\cr_bitfield_b_ok[0:0] + attribute \src "issuer_ls180.v:113890.3-113900.6" + wire width 3 $1\cr_bitfield_o[2:0] + attribute \src "issuer_ls180.v:113901.3-113911.6" + wire $1\cr_bitfield_o_ok[0:0] + attribute \src "issuer_ls180.v:113803.3-113829.6" + wire $1\cr_bitfield_ok[0:0] + attribute \src "issuer_ls180.v:113939.3-113957.6" + wire width 8 $1\cr_fxm[7:0] + attribute \src "issuer_ls180.v:113841.3-113851.6" + wire $1\cr_fxm_ok[0:0] + attribute \src "issuer_ls180.v:113912.3-113922.6" + wire $1\move_one[0:0] + attribute \src "issuer_ls180.v:113923.3-113938.6" + wire width 8 $1\ppick_i[7:0] + attribute \src "issuer_ls180.v:113939.3-113957.6" + wire width 8 $2\cr_fxm[7:0] + attribute \src "issuer_ls180.v:113923.3-113938.6" + wire width 8 $2\ppick_i[7:0] + attribute \src "issuer_ls180.v:113796.17-113796.112" + wire $and$issuer_ls180.v:113796$4442_Y + attribute \src "issuer_ls180.v:113798.17-113798.112" + wire $and$issuer_ls180.v:113798$4444_Y + attribute \src "issuer_ls180.v:113795.17-113795.117" + wire $eq$issuer_ls180.v:113795$4441_Y + attribute \src "issuer_ls180.v:113797.17-113797.117" + wire $eq$issuer_ls180.v:113797$4443_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 input 12 \BA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 input 11 \BB + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 input 16 \BC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 input 15 \BI + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 input 13 \BT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 8 input 14 \FXM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 3 input 17 \X_BFA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 3 output 5 \cr_bitfield + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 3 output 7 \cr_bitfield_b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 8 \cr_bitfield_b_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 3 output 9 \cr_bitfield_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 10 \cr_bitfield_o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 6 \cr_bitfield_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 8 output 3 \cr_fxm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 4 \cr_fxm_ok + attribute \src "issuer_ls180.v:113654.7-113654.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:485" + wire width 32 input 18 \insn_in + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 7 input 2 \internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:526" + wire \move_one + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" + wire width 8 \ppick_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" + wire width 8 \ppick_o + attribute \enum_base_type "CRInSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BI" + attribute \enum_value_011 "BFA" + attribute \enum_value_100 "BA_BB" + attribute \enum_value_101 "BC" + attribute \enum_value_110 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:484" + wire width 3 input 1 \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" + cell $and $and$issuer_ls180.v:113796$4442 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$1 + connect \B \move_one + connect \Y $and$issuer_ls180.v:113796$4442_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" + cell $and $and$issuer_ls180.v:113798$4444 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$5 + connect \B \move_one + connect \Y $and$issuer_ls180.v:113798$4444_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" + cell $eq $eq$issuer_ls180.v:113795$4441 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \internal_op + connect \B 7'0101101 + connect \Y $eq$issuer_ls180.v:113795$4441_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" + cell $eq $eq$issuer_ls180.v:113797$4443 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \internal_op + connect \B 7'0101101 + connect \Y $eq$issuer_ls180.v:113797$4443_Y + end + attribute \module_not_derived 1 + attribute \src "issuer_ls180.v:113799.15-113802.4" + cell \ppick$206 \ppick + connect \i \ppick_i + connect \o \ppick_o + end + attribute \src "issuer_ls180.v:113654.7-113654.20" + process $proc$issuer_ls180.v:113654$4455 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "issuer_ls180.v:113803.3-113829.6" + process $proc$issuer_ls180.v:113803$4445 + assign { } { } + assign { } { } + assign $0\cr_bitfield_ok[0:0] $1\cr_bitfield_ok[0:0] + attribute \src "issuer_ls180.v:113804.5-113804.29" + switch \initial + attribute \src "issuer_ls180.v:113804.9-113804.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" + switch \sel_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 3'001 + assign { } { } + assign $1\cr_bitfield_ok[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 3'010 + assign { } { } + assign $1\cr_bitfield_ok[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 3'011 + assign { } { } + assign $1\cr_bitfield_ok[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 3'100 + assign { } { } + assign $1\cr_bitfield_ok[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 3'101 + assign { } { } + assign $1\cr_bitfield_ok[0:0] 1'1 + case + assign $1\cr_bitfield_ok[0:0] 1'0 + end + sync always + update \cr_bitfield_ok $0\cr_bitfield_ok[0:0] + end + attribute \src "issuer_ls180.v:113830.3-113840.6" + process $proc$issuer_ls180.v:113830$4446 + assign { } { } + assign { } { } + assign $0\cr_bitfield_b_ok[0:0] $1\cr_bitfield_b_ok[0:0] + attribute \src "issuer_ls180.v:113831.5-113831.29" + switch \initial + attribute \src "issuer_ls180.v:113831.9-113831.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" + switch \sel_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 3'100 + assign { } { } + assign $1\cr_bitfield_b_ok[0:0] 1'1 + case + assign $1\cr_bitfield_b_ok[0:0] 1'0 + end + sync always + update \cr_bitfield_b_ok $0\cr_bitfield_b_ok[0:0] + end + attribute \src "issuer_ls180.v:113841.3-113851.6" + process $proc$issuer_ls180.v:113841$4447 + assign { } { } + assign { } { } + assign $0\cr_fxm_ok[0:0] $1\cr_fxm_ok[0:0] + attribute \src "issuer_ls180.v:113842.5-113842.29" + switch \initial + attribute \src "issuer_ls180.v:113842.9-113842.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" + switch \sel_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 3'110 + assign { } { } + assign $1\cr_fxm_ok[0:0] 1'1 + case + assign $1\cr_fxm_ok[0:0] 1'0 + end + sync always + update \cr_fxm_ok $0\cr_fxm_ok[0:0] + end + attribute \src "issuer_ls180.v:113852.3-113878.6" + process $proc$issuer_ls180.v:113852$4448 + assign { } { } + assign { } { } + assign $0\cr_bitfield[2:0] $1\cr_bitfield[2:0] + attribute \src "issuer_ls180.v:113853.5-113853.29" + switch \initial + attribute \src "issuer_ls180.v:113853.9-113853.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" + switch \sel_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 3'001 + assign { } { } + assign $1\cr_bitfield[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 3'010 + assign { } { } + assign $1\cr_bitfield[2:0] \BI [4:2] + attribute \src "issuer_ls180.v:0.0-0.0" + case 3'011 + assign { } { } + assign $1\cr_bitfield[2:0] \X_BFA + attribute \src "issuer_ls180.v:0.0-0.0" + case 3'100 + assign { } { } + assign $1\cr_bitfield[2:0] \BA [4:2] + attribute \src "issuer_ls180.v:0.0-0.0" + case 3'101 + assign { } { } + assign $1\cr_bitfield[2:0] \BC [4:2] + case + assign $1\cr_bitfield[2:0] 3'000 + end + sync always + update \cr_bitfield $0\cr_bitfield[2:0] + end + attribute \src "issuer_ls180.v:113879.3-113889.6" + process $proc$issuer_ls180.v:113879$4449 + assign { } { } + assign { } { } + assign $0\cr_bitfield_b[2:0] $1\cr_bitfield_b[2:0] + attribute \src "issuer_ls180.v:113880.5-113880.29" + switch \initial + attribute \src "issuer_ls180.v:113880.9-113880.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" + switch \sel_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 3'100 + assign { } { } + assign $1\cr_bitfield_b[2:0] \BB [4:2] + case + assign $1\cr_bitfield_b[2:0] 3'000 + end + sync always + update \cr_bitfield_b $0\cr_bitfield_b[2:0] + end + attribute \src "issuer_ls180.v:113890.3-113900.6" + process $proc$issuer_ls180.v:113890$4450 + assign { } { } + assign { } { } + assign $0\cr_bitfield_o[2:0] $1\cr_bitfield_o[2:0] + attribute \src "issuer_ls180.v:113891.5-113891.29" + switch \initial + attribute \src "issuer_ls180.v:113891.9-113891.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" + switch \sel_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 3'100 + assign { } { } + assign $1\cr_bitfield_o[2:0] \BT [4:2] + case + assign $1\cr_bitfield_o[2:0] 3'000 + end + sync always + update \cr_bitfield_o $0\cr_bitfield_o[2:0] + end + attribute \src "issuer_ls180.v:113901.3-113911.6" + process $proc$issuer_ls180.v:113901$4451 + assign { } { } + assign { } { } + assign $0\cr_bitfield_o_ok[0:0] $1\cr_bitfield_o_ok[0:0] + attribute \src "issuer_ls180.v:113902.5-113902.29" + switch \initial + attribute \src "issuer_ls180.v:113902.9-113902.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" + switch \sel_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 3'100 + assign { } { } + assign $1\cr_bitfield_o_ok[0:0] 1'1 + case + assign $1\cr_bitfield_o_ok[0:0] 1'0 + end + sync always + update \cr_bitfield_o_ok $0\cr_bitfield_o_ok[0:0] + end + attribute \src "issuer_ls180.v:113912.3-113922.6" + process $proc$issuer_ls180.v:113912$4452 + assign { } { } + assign { } { } + assign $0\move_one[0:0] $1\move_one[0:0] + attribute \src "issuer_ls180.v:113913.5-113913.29" + switch \initial + attribute \src "issuer_ls180.v:113913.9-113913.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" + switch \sel_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 3'110 + assign { } { } + assign $1\move_one[0:0] \insn_in [20] + case + assign $1\move_one[0:0] 1'0 + end + sync always + update \move_one $0\move_one[0:0] + end + attribute \src "issuer_ls180.v:113923.3-113938.6" + process $proc$issuer_ls180.v:113923$4453 + assign { } { } + assign { } { } + assign $0\ppick_i[7:0] $1\ppick_i[7:0] + attribute \src "issuer_ls180.v:113924.5-113924.29" + switch \initial + attribute \src "issuer_ls180.v:113924.9-113924.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" + switch \sel_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 3'110 + assign { } { } + assign $1\ppick_i[7:0] $2\ppick_i[7:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" + switch \$3 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\ppick_i[7:0] \FXM + case + assign $2\ppick_i[7:0] 8'00000000 + end + case + assign $1\ppick_i[7:0] 8'00000000 + end + sync always + update \ppick_i $0\ppick_i[7:0] + end + attribute \src "issuer_ls180.v:113939.3-113957.6" + process $proc$issuer_ls180.v:113939$4454 + assign { } { } + assign { } { } + assign $0\cr_fxm[7:0] $1\cr_fxm[7:0] + attribute \src "issuer_ls180.v:113940.5-113940.29" + switch \initial + attribute \src "issuer_ls180.v:113940.9-113940.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" + switch \sel_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 3'110 + assign { } { } + assign $1\cr_fxm[7:0] $2\cr_fxm[7:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" + switch \$7 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\cr_fxm[7:0] \ppick_o + attribute \src "issuer_ls180.v:0.0-0.0" + case + assign { } { } + assign $2\cr_fxm[7:0] 8'11111111 + end + case + assign $1\cr_fxm[7:0] 8'00000000 + end + sync always + update \cr_fxm $0\cr_fxm[7:0] + end + connect \$1 $eq$issuer_ls180.v:113795$4441_Y + connect \$3 $and$issuer_ls180.v:113796$4442_Y + connect \$5 $eq$issuer_ls180.v:113797$4443_Y + connect \$7 $and$issuer_ls180.v:113798$4444_Y +end +attribute \src "issuer_ls180.v:113962.1-114202.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.dec_ALU.dec_cr_out" +attribute \generator "nMigen" +module \dec_cr_out + attribute \src "issuer_ls180.v:114116.3-114134.6" + wire width 3 $0\cr_bitfield[2:0] + attribute \src "issuer_ls180.v:114086.3-114104.6" + wire $0\cr_bitfield_ok[0:0] + attribute \src "issuer_ls180.v:114167.3-114201.6" + wire width 8 $0\cr_fxm[7:0] + attribute \src "issuer_ls180.v:114105.3-114115.6" + wire $0\cr_fxm_ok[0:0] + attribute \src "issuer_ls180.v:113963.7-113963.20" + wire $0\initial[0:0] + attribute \src "issuer_ls180.v:114135.3-114145.6" + wire $0\move_one[0:0] + attribute \src "issuer_ls180.v:114146.3-114166.6" + wire width 8 $0\ppick_i[7:0] + attribute \src "issuer_ls180.v:114116.3-114134.6" + wire width 3 $1\cr_bitfield[2:0] + attribute \src "issuer_ls180.v:114086.3-114104.6" + wire $1\cr_bitfield_ok[0:0] + attribute \src "issuer_ls180.v:114167.3-114201.6" + wire width 8 $1\cr_fxm[7:0] + attribute \src "issuer_ls180.v:114105.3-114115.6" + wire $1\cr_fxm_ok[0:0] + attribute \src "issuer_ls180.v:114135.3-114145.6" + wire $1\move_one[0:0] + attribute \src "issuer_ls180.v:114146.3-114166.6" + wire width 8 $1\ppick_i[7:0] + attribute \src "issuer_ls180.v:114167.3-114201.6" + wire width 8 $2\cr_fxm[7:0] + attribute \src "issuer_ls180.v:114146.3-114166.6" + wire width 8 $2\ppick_i[7:0] + attribute \src "issuer_ls180.v:114167.3-114201.6" + wire width 8 $3\cr_fxm[7:0] + attribute \src "issuer_ls180.v:114146.3-114166.6" + wire width 8 $3\ppick_i[7:0] + attribute \src "issuer_ls180.v:114167.3-114201.6" + wire width 8 $4\cr_fxm[7:0] + attribute \src "issuer_ls180.v:114079.17-114079.121" + wire $eq$issuer_ls180.v:114079$4456_Y + attribute \src "issuer_ls180.v:114080.17-114080.121" + wire $eq$issuer_ls180.v:114080$4457_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:579" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:579" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 8 input 5 \ALU_FXM + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 7 input 3 \ALU_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 input 7 \XL_BT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 3 input 6 \X_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 3 \cr_bitfield + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 4 \cr_bitfield_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 8 \cr_fxm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \cr_fxm_ok + attribute \src "issuer_ls180.v:113963.7-113963.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:550" + wire width 32 input 8 \insn_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:577" + wire \move_one + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" + wire \ppick_en_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" + wire width 8 \ppick_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" + wire width 8 \ppick_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:548" + wire input 2 \rc_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:549" + wire width 3 input 1 \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:579" + cell $eq $eq$issuer_ls180.v:114079$4456 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \ALU_internal_op + connect \B 7'0110000 + connect \Y $eq$issuer_ls180.v:114079$4456_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:579" + cell $eq $eq$issuer_ls180.v:114080$4457 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \ALU_internal_op + connect \B 7'0110000 + connect \Y $eq$issuer_ls180.v:114080$4457_Y + end + attribute \module_not_derived 1 + attribute \src "issuer_ls180.v:114081.15-114085.4" + cell \ppick$136 \ppick + connect \en_o \ppick_en_o + connect \i \ppick_i + connect \o \ppick_o + end + attribute \src "issuer_ls180.v:113963.7-113963.20" + process $proc$issuer_ls180.v:113963$4464 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "issuer_ls180.v:114086.3-114104.6" + process $proc$issuer_ls180.v:114086$4458 + assign { } { } + assign { } { } + assign $0\cr_bitfield_ok[0:0] $1\cr_bitfield_ok[0:0] + attribute \src "issuer_ls180.v:114087.5-114087.29" + switch \initial + attribute \src "issuer_ls180.v:114087.9-114087.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:563" + switch \sel_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 3'001 + assign { } { } + assign $1\cr_bitfield_ok[0:0] \rc_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 3'010 + assign { } { } + assign $1\cr_bitfield_ok[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 3'011 + assign { } { } + assign $1\cr_bitfield_ok[0:0] 1'1 + case + assign $1\cr_bitfield_ok[0:0] 1'0 + end + sync always + update \cr_bitfield_ok $0\cr_bitfield_ok[0:0] + end + attribute \src "issuer_ls180.v:114105.3-114115.6" + process $proc$issuer_ls180.v:114105$4459 + assign { } { } + assign { } { } + assign $0\cr_fxm_ok[0:0] $1\cr_fxm_ok[0:0] + attribute \src "issuer_ls180.v:114106.5-114106.29" + switch \initial + attribute \src "issuer_ls180.v:114106.9-114106.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:563" + switch \sel_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 3'100 + assign { } { } + assign $1\cr_fxm_ok[0:0] 1'1 + case + assign $1\cr_fxm_ok[0:0] 1'0 + end + sync always + update \cr_fxm_ok $0\cr_fxm_ok[0:0] + end + attribute \src "issuer_ls180.v:114116.3-114134.6" + process $proc$issuer_ls180.v:114116$4460 + assign { } { } + assign { } { } + assign $0\cr_bitfield[2:0] $1\cr_bitfield[2:0] + attribute \src "issuer_ls180.v:114117.5-114117.29" + switch \initial + attribute \src "issuer_ls180.v:114117.9-114117.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:563" + switch \sel_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 3'001 + assign { } { } + assign $1\cr_bitfield[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 3'010 + assign { } { } + assign $1\cr_bitfield[2:0] \X_BF + attribute \src "issuer_ls180.v:0.0-0.0" + case 3'011 + assign { } { } + assign $1\cr_bitfield[2:0] \XL_BT [4:2] + case + assign $1\cr_bitfield[2:0] 3'000 + end + sync always + update \cr_bitfield $0\cr_bitfield[2:0] + end + attribute \src "issuer_ls180.v:114135.3-114145.6" + process $proc$issuer_ls180.v:114135$4461 + assign { } { } + assign { } { } + assign $0\move_one[0:0] $1\move_one[0:0] + attribute \src "issuer_ls180.v:114136.5-114136.29" + switch \initial + attribute \src "issuer_ls180.v:114136.9-114136.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:563" + switch \sel_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 3'100 + assign { } { } + assign $1\move_one[0:0] \insn_in [20] + case + assign $1\move_one[0:0] 1'0 + end + sync always + update \move_one $0\move_one[0:0] + end + attribute \src "issuer_ls180.v:114146.3-114166.6" + process $proc$issuer_ls180.v:114146$4462 + assign { } { } + assign { } { } + assign $0\ppick_i[7:0] $1\ppick_i[7:0] + attribute \src "issuer_ls180.v:114147.5-114147.29" + switch \initial + attribute \src "issuer_ls180.v:114147.9-114147.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:563" + switch \sel_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 3'100 + assign { } { } + assign $1\ppick_i[7:0] $2\ppick_i[7:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:579" + switch \$1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\ppick_i[7:0] $3\ppick_i[7:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:580" + switch \move_one + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\ppick_i[7:0] \ALU_FXM + case + assign $3\ppick_i[7:0] 8'00000000 + end + case + assign $2\ppick_i[7:0] 8'00000000 + end + case + assign $1\ppick_i[7:0] 8'00000000 + end + sync always + update \ppick_i $0\ppick_i[7:0] + end + attribute \src "issuer_ls180.v:114167.3-114201.6" + process $proc$issuer_ls180.v:114167$4463 + assign { } { } + assign { } { } + assign $0\cr_fxm[7:0] $1\cr_fxm[7:0] + attribute \src "issuer_ls180.v:114168.5-114168.29" + switch \initial + attribute \src "issuer_ls180.v:114168.9-114168.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:563" + switch \sel_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 3'100 + assign { } { } + assign $1\cr_fxm[7:0] $2\cr_fxm[7:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:579" + switch \$3 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\cr_fxm[7:0] $3\cr_fxm[7:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:580" + switch \move_one + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\cr_fxm[7:0] $4\cr_fxm[7:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:583" + switch \ppick_en_o + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\cr_fxm[7:0] \ppick_o + attribute \src "issuer_ls180.v:0.0-0.0" + case + assign { } { } + assign $4\cr_fxm[7:0] 8'00000001 + end + attribute \src "issuer_ls180.v:0.0-0.0" + case + assign { } { } + assign $3\cr_fxm[7:0] \ALU_FXM + end + attribute \src "issuer_ls180.v:0.0-0.0" + case + assign { } { } + assign $2\cr_fxm[7:0] 8'11111111 + end + case + assign $1\cr_fxm[7:0] 8'00000000 + end + sync always + update \cr_fxm $0\cr_fxm[7:0] + end + connect \$1 $eq$issuer_ls180.v:114079$4456_Y + connect \$3 $eq$issuer_ls180.v:114080$4457_Y +end +attribute \src "issuer_ls180.v:114206.1-114445.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.dec_CR.dec_cr_out" +attribute \generator "nMigen" +module \dec_cr_out$142 + attribute \src "issuer_ls180.v:114359.3-114377.6" + wire width 3 $0\cr_bitfield[2:0] + attribute \src "issuer_ls180.v:114329.3-114347.6" + wire $0\cr_bitfield_ok[0:0] + attribute \src "issuer_ls180.v:114410.3-114444.6" + wire width 8 $0\cr_fxm[7:0] + attribute \src "issuer_ls180.v:114348.3-114358.6" + wire $0\cr_fxm_ok[0:0] + attribute \src "issuer_ls180.v:114207.7-114207.20" + wire $0\initial[0:0] + attribute \src "issuer_ls180.v:114378.3-114388.6" + wire $0\move_one[0:0] + attribute \src "issuer_ls180.v:114389.3-114409.6" + wire width 8 $0\ppick_i[7:0] + attribute \src "issuer_ls180.v:114359.3-114377.6" + wire width 3 $1\cr_bitfield[2:0] + attribute \src "issuer_ls180.v:114329.3-114347.6" + wire $1\cr_bitfield_ok[0:0] + attribute \src "issuer_ls180.v:114410.3-114444.6" + wire width 8 $1\cr_fxm[7:0] + attribute \src "issuer_ls180.v:114348.3-114358.6" + wire $1\cr_fxm_ok[0:0] + attribute \src "issuer_ls180.v:114378.3-114388.6" + wire $1\move_one[0:0] + attribute \src "issuer_ls180.v:114389.3-114409.6" + wire width 8 $1\ppick_i[7:0] + attribute \src "issuer_ls180.v:114410.3-114444.6" + wire width 8 $2\cr_fxm[7:0] + attribute \src "issuer_ls180.v:114389.3-114409.6" + wire width 8 $2\ppick_i[7:0] + attribute \src "issuer_ls180.v:114410.3-114444.6" + wire width 8 $3\cr_fxm[7:0] + attribute \src "issuer_ls180.v:114389.3-114409.6" + wire width 8 $3\ppick_i[7:0] + attribute \src "issuer_ls180.v:114410.3-114444.6" + wire width 8 $4\cr_fxm[7:0] + attribute \src "issuer_ls180.v:114322.17-114322.120" + wire $eq$issuer_ls180.v:114322$4465_Y + attribute \src "issuer_ls180.v:114323.17-114323.120" + wire $eq$issuer_ls180.v:114323$4466_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:579" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:579" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 8 input 4 \CR_FXM + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 7 input 3 \CR_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 input 6 \XL_BT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 3 input 5 \X_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 3 \cr_bitfield + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \cr_bitfield_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 8 \cr_fxm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \cr_fxm_ok + attribute \src "issuer_ls180.v:114207.7-114207.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:550" + wire width 32 input 7 \insn_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:577" + wire \move_one + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" + wire \ppick_en_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" + wire width 8 \ppick_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" + wire width 8 \ppick_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:548" + wire input 2 \rc_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:549" + wire width 3 input 1 \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:579" + cell $eq $eq$issuer_ls180.v:114322$4465 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \CR_internal_op + connect \B 7'0110000 + connect \Y $eq$issuer_ls180.v:114322$4465_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:579" + cell $eq $eq$issuer_ls180.v:114323$4466 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \CR_internal_op + connect \B 7'0110000 + connect \Y $eq$issuer_ls180.v:114323$4466_Y + end + attribute \module_not_derived 1 + attribute \src "issuer_ls180.v:114324.15-114328.4" + cell \ppick$143 \ppick + connect \en_o \ppick_en_o + connect \i \ppick_i + connect \o \ppick_o + end + attribute \src "issuer_ls180.v:114207.7-114207.20" + process $proc$issuer_ls180.v:114207$4473 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "issuer_ls180.v:114329.3-114347.6" + process $proc$issuer_ls180.v:114329$4467 + assign { } { } + assign { } { } + assign $0\cr_bitfield_ok[0:0] $1\cr_bitfield_ok[0:0] + attribute \src "issuer_ls180.v:114330.5-114330.29" + switch \initial + attribute \src "issuer_ls180.v:114330.9-114330.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:563" + switch \sel_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 3'001 + assign { } { } + assign $1\cr_bitfield_ok[0:0] \rc_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 3'010 + assign { } { } + assign $1\cr_bitfield_ok[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 3'011 + assign { } { } + assign $1\cr_bitfield_ok[0:0] 1'1 + case + assign $1\cr_bitfield_ok[0:0] 1'0 + end + sync always + update \cr_bitfield_ok $0\cr_bitfield_ok[0:0] + end + attribute \src "issuer_ls180.v:114348.3-114358.6" + process $proc$issuer_ls180.v:114348$4468 + assign { } { } + assign { } { } + assign $0\cr_fxm_ok[0:0] $1\cr_fxm_ok[0:0] + attribute \src "issuer_ls180.v:114349.5-114349.29" + switch \initial + attribute \src "issuer_ls180.v:114349.9-114349.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:563" + switch \sel_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 3'100 + assign { } { } + assign $1\cr_fxm_ok[0:0] 1'1 + case + assign $1\cr_fxm_ok[0:0] 1'0 + end + sync always + update \cr_fxm_ok $0\cr_fxm_ok[0:0] + end + attribute \src "issuer_ls180.v:114359.3-114377.6" + process $proc$issuer_ls180.v:114359$4469 + assign { } { } + assign { } { } + assign $0\cr_bitfield[2:0] $1\cr_bitfield[2:0] + attribute \src "issuer_ls180.v:114360.5-114360.29" + switch \initial + attribute \src "issuer_ls180.v:114360.9-114360.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:563" + switch \sel_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 3'001 + assign { } { } + assign $1\cr_bitfield[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 3'010 + assign { } { } + assign $1\cr_bitfield[2:0] \X_BF + attribute \src "issuer_ls180.v:0.0-0.0" + case 3'011 + assign { } { } + assign $1\cr_bitfield[2:0] \XL_BT [4:2] + case + assign $1\cr_bitfield[2:0] 3'000 + end + sync always + update \cr_bitfield $0\cr_bitfield[2:0] + end + attribute \src "issuer_ls180.v:114378.3-114388.6" + process $proc$issuer_ls180.v:114378$4470 + assign { } { } + assign { } { } + assign $0\move_one[0:0] $1\move_one[0:0] + attribute \src "issuer_ls180.v:114379.5-114379.29" + switch \initial + attribute \src "issuer_ls180.v:114379.9-114379.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:563" + switch \sel_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 3'100 + assign { } { } + assign $1\move_one[0:0] \insn_in [20] + case + assign $1\move_one[0:0] 1'0 + end + sync always + update \move_one $0\move_one[0:0] + end + attribute \src "issuer_ls180.v:114389.3-114409.6" + process $proc$issuer_ls180.v:114389$4471 + assign { } { } + assign { } { } + assign $0\ppick_i[7:0] $1\ppick_i[7:0] + attribute \src "issuer_ls180.v:114390.5-114390.29" + switch \initial + attribute \src "issuer_ls180.v:114390.9-114390.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:563" + switch \sel_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 3'100 + assign { } { } + assign $1\ppick_i[7:0] $2\ppick_i[7:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:579" + switch \$1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\ppick_i[7:0] $3\ppick_i[7:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:580" + switch \move_one + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\ppick_i[7:0] \CR_FXM + case + assign $3\ppick_i[7:0] 8'00000000 + end + case + assign $2\ppick_i[7:0] 8'00000000 + end + case + assign $1\ppick_i[7:0] 8'00000000 + end + sync always + update \ppick_i $0\ppick_i[7:0] + end + attribute \src "issuer_ls180.v:114410.3-114444.6" + process $proc$issuer_ls180.v:114410$4472 + assign { } { } + assign { } { } + assign $0\cr_fxm[7:0] $1\cr_fxm[7:0] + attribute \src "issuer_ls180.v:114411.5-114411.29" + switch \initial + attribute \src "issuer_ls180.v:114411.9-114411.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:563" + switch \sel_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 3'100 + assign { } { } + assign $1\cr_fxm[7:0] $2\cr_fxm[7:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:579" + switch \$3 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\cr_fxm[7:0] $3\cr_fxm[7:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:580" + switch \move_one + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\cr_fxm[7:0] $4\cr_fxm[7:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:583" + switch \ppick_en_o + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\cr_fxm[7:0] \ppick_o + attribute \src "issuer_ls180.v:0.0-0.0" + case + assign { } { } + assign $4\cr_fxm[7:0] 8'00000001 + end + attribute \src "issuer_ls180.v:0.0-0.0" + case + assign { } { } + assign $3\cr_fxm[7:0] \CR_FXM + end + attribute \src "issuer_ls180.v:0.0-0.0" + case + assign { } { } + assign $2\cr_fxm[7:0] 8'11111111 + end + case + assign $1\cr_fxm[7:0] 8'00000000 + end + sync always + update \cr_fxm $0\cr_fxm[7:0] + end + connect \$1 $eq$issuer_ls180.v:114322$4465_Y + connect \$3 $eq$issuer_ls180.v:114323$4466_Y +end +attribute \src "issuer_ls180.v:114449.1-114688.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.dec_BRANCH.dec_cr_out" +attribute \generator "nMigen" +module \dec_cr_out$149 + attribute \src "issuer_ls180.v:114602.3-114620.6" + wire width 3 $0\cr_bitfield[2:0] + attribute \src "issuer_ls180.v:114572.3-114590.6" + wire $0\cr_bitfield_ok[0:0] + attribute \src "issuer_ls180.v:114653.3-114687.6" + wire width 8 $0\cr_fxm[7:0] + attribute \src "issuer_ls180.v:114591.3-114601.6" + wire $0\cr_fxm_ok[0:0] + attribute \src "issuer_ls180.v:114450.7-114450.20" + wire $0\initial[0:0] + attribute \src "issuer_ls180.v:114621.3-114631.6" + wire $0\move_one[0:0] + attribute \src "issuer_ls180.v:114632.3-114652.6" + wire width 8 $0\ppick_i[7:0] + attribute \src "issuer_ls180.v:114602.3-114620.6" + wire width 3 $1\cr_bitfield[2:0] + attribute \src "issuer_ls180.v:114572.3-114590.6" + wire $1\cr_bitfield_ok[0:0] + attribute \src "issuer_ls180.v:114653.3-114687.6" + wire width 8 $1\cr_fxm[7:0] + attribute \src "issuer_ls180.v:114591.3-114601.6" + wire $1\cr_fxm_ok[0:0] + attribute \src "issuer_ls180.v:114621.3-114631.6" + wire $1\move_one[0:0] + attribute \src "issuer_ls180.v:114632.3-114652.6" + wire width 8 $1\ppick_i[7:0] + attribute \src "issuer_ls180.v:114653.3-114687.6" + wire width 8 $2\cr_fxm[7:0] + attribute \src "issuer_ls180.v:114632.3-114652.6" + wire width 8 $2\ppick_i[7:0] + attribute \src "issuer_ls180.v:114653.3-114687.6" + wire width 8 $3\cr_fxm[7:0] + attribute \src "issuer_ls180.v:114632.3-114652.6" + wire width 8 $3\ppick_i[7:0] + attribute \src "issuer_ls180.v:114653.3-114687.6" + wire width 8 $4\cr_fxm[7:0] + attribute \src "issuer_ls180.v:114565.17-114565.124" + wire $eq$issuer_ls180.v:114565$4474_Y + attribute \src "issuer_ls180.v:114566.17-114566.124" + wire $eq$issuer_ls180.v:114566$4475_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:579" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:579" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 8 input 4 \BRANCH_FXM + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 7 input 3 \BRANCH_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 input 6 \XL_BT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 3 input 5 \X_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 3 \cr_bitfield + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \cr_bitfield_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 8 \cr_fxm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \cr_fxm_ok + attribute \src "issuer_ls180.v:114450.7-114450.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:550" + wire width 32 input 7 \insn_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:577" + wire \move_one + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" + wire \ppick_en_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" + wire width 8 \ppick_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" + wire width 8 \ppick_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:548" + wire input 2 \rc_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:549" + wire width 3 input 1 \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:579" + cell $eq $eq$issuer_ls180.v:114565$4474 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \BRANCH_internal_op + connect \B 7'0110000 + connect \Y $eq$issuer_ls180.v:114565$4474_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:579" + cell $eq $eq$issuer_ls180.v:114566$4475 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \BRANCH_internal_op + connect \B 7'0110000 + connect \Y $eq$issuer_ls180.v:114566$4475_Y + end + attribute \module_not_derived 1 + attribute \src "issuer_ls180.v:114567.15-114571.4" + cell \ppick$150 \ppick + connect \en_o \ppick_en_o + connect \i \ppick_i + connect \o \ppick_o + end + attribute \src "issuer_ls180.v:114450.7-114450.20" + process $proc$issuer_ls180.v:114450$4482 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "issuer_ls180.v:114572.3-114590.6" + process $proc$issuer_ls180.v:114572$4476 + assign { } { } + assign { } { } + assign $0\cr_bitfield_ok[0:0] $1\cr_bitfield_ok[0:0] + attribute \src "issuer_ls180.v:114573.5-114573.29" + switch \initial + attribute \src "issuer_ls180.v:114573.9-114573.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:563" + switch \sel_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 3'001 + assign { } { } + assign $1\cr_bitfield_ok[0:0] \rc_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 3'010 + assign { } { } + assign $1\cr_bitfield_ok[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 3'011 + assign { } { } + assign $1\cr_bitfield_ok[0:0] 1'1 + case + assign $1\cr_bitfield_ok[0:0] 1'0 + end + sync always + update \cr_bitfield_ok $0\cr_bitfield_ok[0:0] + end + attribute \src "issuer_ls180.v:114591.3-114601.6" + process $proc$issuer_ls180.v:114591$4477 + assign { } { } + assign { } { } + assign $0\cr_fxm_ok[0:0] $1\cr_fxm_ok[0:0] + attribute \src "issuer_ls180.v:114592.5-114592.29" + switch \initial + attribute \src "issuer_ls180.v:114592.9-114592.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:563" + switch \sel_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 3'100 + assign { } { } + assign $1\cr_fxm_ok[0:0] 1'1 + case + assign $1\cr_fxm_ok[0:0] 1'0 + end + sync always + update \cr_fxm_ok $0\cr_fxm_ok[0:0] + end + attribute \src "issuer_ls180.v:114602.3-114620.6" + process $proc$issuer_ls180.v:114602$4478 + assign { } { } + assign { } { } + assign $0\cr_bitfield[2:0] $1\cr_bitfield[2:0] + attribute \src "issuer_ls180.v:114603.5-114603.29" + switch \initial + attribute \src "issuer_ls180.v:114603.9-114603.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:563" + switch \sel_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 3'001 + assign { } { } + assign $1\cr_bitfield[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 3'010 + assign { } { } + assign $1\cr_bitfield[2:0] \X_BF + attribute \src "issuer_ls180.v:0.0-0.0" + case 3'011 + assign { } { } + assign $1\cr_bitfield[2:0] \XL_BT [4:2] + case + assign $1\cr_bitfield[2:0] 3'000 + end + sync always + update \cr_bitfield $0\cr_bitfield[2:0] + end + attribute \src "issuer_ls180.v:114621.3-114631.6" + process $proc$issuer_ls180.v:114621$4479 + assign { } { } + assign { } { } + assign $0\move_one[0:0] $1\move_one[0:0] + attribute \src "issuer_ls180.v:114622.5-114622.29" + switch \initial + attribute \src "issuer_ls180.v:114622.9-114622.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:563" + switch \sel_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 3'100 + assign { } { } + assign $1\move_one[0:0] \insn_in [20] + case + assign $1\move_one[0:0] 1'0 + end + sync always + update \move_one $0\move_one[0:0] + end + attribute \src "issuer_ls180.v:114632.3-114652.6" + process $proc$issuer_ls180.v:114632$4480 + assign { } { } + assign { } { } + assign $0\ppick_i[7:0] $1\ppick_i[7:0] + attribute \src "issuer_ls180.v:114633.5-114633.29" + switch \initial + attribute \src "issuer_ls180.v:114633.9-114633.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:563" + switch \sel_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 3'100 + assign { } { } + assign $1\ppick_i[7:0] $2\ppick_i[7:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:579" + switch \$1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\ppick_i[7:0] $3\ppick_i[7:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:580" + switch \move_one + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\ppick_i[7:0] \BRANCH_FXM + case + assign $3\ppick_i[7:0] 8'00000000 + end + case + assign $2\ppick_i[7:0] 8'00000000 + end + case + assign $1\ppick_i[7:0] 8'00000000 + end + sync always + update \ppick_i $0\ppick_i[7:0] + end + attribute \src "issuer_ls180.v:114653.3-114687.6" + process $proc$issuer_ls180.v:114653$4481 + assign { } { } + assign { } { } + assign $0\cr_fxm[7:0] $1\cr_fxm[7:0] + attribute \src "issuer_ls180.v:114654.5-114654.29" + switch \initial + attribute \src "issuer_ls180.v:114654.9-114654.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:563" + switch \sel_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 3'100 + assign { } { } + assign $1\cr_fxm[7:0] $2\cr_fxm[7:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:579" + switch \$3 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\cr_fxm[7:0] $3\cr_fxm[7:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:580" + switch \move_one + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\cr_fxm[7:0] $4\cr_fxm[7:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:583" + switch \ppick_en_o + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\cr_fxm[7:0] \ppick_o + attribute \src "issuer_ls180.v:0.0-0.0" + case + assign { } { } + assign $4\cr_fxm[7:0] 8'00000001 + end + attribute \src "issuer_ls180.v:0.0-0.0" + case + assign { } { } + assign $3\cr_fxm[7:0] \BRANCH_FXM + end + attribute \src "issuer_ls180.v:0.0-0.0" + case + assign { } { } + assign $2\cr_fxm[7:0] 8'11111111 + end + case + assign $1\cr_fxm[7:0] 8'00000000 + end + sync always + update \cr_fxm $0\cr_fxm[7:0] + end + connect \$1 $eq$issuer_ls180.v:114565$4474_Y + connect \$3 $eq$issuer_ls180.v:114566$4475_Y +end +attribute \src "issuer_ls180.v:114692.1-114932.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.dec_LOGICAL.dec_cr_out" +attribute \generator "nMigen" +module \dec_cr_out$157 + attribute \src "issuer_ls180.v:114846.3-114864.6" + wire width 3 $0\cr_bitfield[2:0] + attribute \src "issuer_ls180.v:114816.3-114834.6" + wire $0\cr_bitfield_ok[0:0] + attribute \src "issuer_ls180.v:114897.3-114931.6" + wire width 8 $0\cr_fxm[7:0] + attribute \src "issuer_ls180.v:114835.3-114845.6" + wire $0\cr_fxm_ok[0:0] + attribute \src "issuer_ls180.v:114693.7-114693.20" + wire $0\initial[0:0] + attribute \src "issuer_ls180.v:114865.3-114875.6" + wire $0\move_one[0:0] + attribute \src "issuer_ls180.v:114876.3-114896.6" + wire width 8 $0\ppick_i[7:0] + attribute \src "issuer_ls180.v:114846.3-114864.6" + wire width 3 $1\cr_bitfield[2:0] + attribute \src "issuer_ls180.v:114816.3-114834.6" + wire $1\cr_bitfield_ok[0:0] + attribute \src "issuer_ls180.v:114897.3-114931.6" + wire width 8 $1\cr_fxm[7:0] + attribute \src "issuer_ls180.v:114835.3-114845.6" + wire $1\cr_fxm_ok[0:0] + attribute \src "issuer_ls180.v:114865.3-114875.6" + wire $1\move_one[0:0] + attribute \src "issuer_ls180.v:114876.3-114896.6" + wire width 8 $1\ppick_i[7:0] + attribute \src "issuer_ls180.v:114897.3-114931.6" + wire width 8 $2\cr_fxm[7:0] + attribute \src "issuer_ls180.v:114876.3-114896.6" + wire width 8 $2\ppick_i[7:0] + attribute \src "issuer_ls180.v:114897.3-114931.6" + wire width 8 $3\cr_fxm[7:0] + attribute \src "issuer_ls180.v:114876.3-114896.6" + wire width 8 $3\ppick_i[7:0] + attribute \src "issuer_ls180.v:114897.3-114931.6" + wire width 8 $4\cr_fxm[7:0] + attribute \src "issuer_ls180.v:114809.17-114809.125" + wire $eq$issuer_ls180.v:114809$4483_Y + attribute \src "issuer_ls180.v:114810.17-114810.125" + wire $eq$issuer_ls180.v:114810$4484_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:579" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:579" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 8 input 5 \LOGICAL_FXM + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 7 input 3 \LOGICAL_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 input 7 \XL_BT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 3 input 6 \X_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 3 \cr_bitfield + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 4 \cr_bitfield_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 8 \cr_fxm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \cr_fxm_ok + attribute \src "issuer_ls180.v:114693.7-114693.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:550" + wire width 32 input 8 \insn_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:577" + wire \move_one + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" + wire \ppick_en_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" + wire width 8 \ppick_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" + wire width 8 \ppick_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:548" + wire input 2 \rc_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:549" + wire width 3 input 1 \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:579" + cell $eq $eq$issuer_ls180.v:114809$4483 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \LOGICAL_internal_op + connect \B 7'0110000 + connect \Y $eq$issuer_ls180.v:114809$4483_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:579" + cell $eq $eq$issuer_ls180.v:114810$4484 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \LOGICAL_internal_op + connect \B 7'0110000 + connect \Y $eq$issuer_ls180.v:114810$4484_Y + end + attribute \module_not_derived 1 + attribute \src "issuer_ls180.v:114811.15-114815.4" + cell \ppick$158 \ppick + connect \en_o \ppick_en_o + connect \i \ppick_i + connect \o \ppick_o + end + attribute \src "issuer_ls180.v:114693.7-114693.20" + process $proc$issuer_ls180.v:114693$4491 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "issuer_ls180.v:114816.3-114834.6" + process $proc$issuer_ls180.v:114816$4485 + assign { } { } + assign { } { } + assign $0\cr_bitfield_ok[0:0] $1\cr_bitfield_ok[0:0] + attribute \src "issuer_ls180.v:114817.5-114817.29" + switch \initial + attribute \src "issuer_ls180.v:114817.9-114817.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:563" + switch \sel_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 3'001 + assign { } { } + assign $1\cr_bitfield_ok[0:0] \rc_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 3'010 + assign { } { } + assign $1\cr_bitfield_ok[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 3'011 + assign { } { } + assign $1\cr_bitfield_ok[0:0] 1'1 + case + assign $1\cr_bitfield_ok[0:0] 1'0 + end + sync always + update \cr_bitfield_ok $0\cr_bitfield_ok[0:0] + end + attribute \src "issuer_ls180.v:114835.3-114845.6" + process $proc$issuer_ls180.v:114835$4486 + assign { } { } + assign { } { } + assign $0\cr_fxm_ok[0:0] $1\cr_fxm_ok[0:0] + attribute \src "issuer_ls180.v:114836.5-114836.29" + switch \initial + attribute \src "issuer_ls180.v:114836.9-114836.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:563" + switch \sel_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 3'100 + assign { } { } + assign $1\cr_fxm_ok[0:0] 1'1 + case + assign $1\cr_fxm_ok[0:0] 1'0 + end + sync always + update \cr_fxm_ok $0\cr_fxm_ok[0:0] + end + attribute \src "issuer_ls180.v:114846.3-114864.6" + process $proc$issuer_ls180.v:114846$4487 + assign { } { } + assign { } { } + assign $0\cr_bitfield[2:0] $1\cr_bitfield[2:0] + attribute \src "issuer_ls180.v:114847.5-114847.29" + switch \initial + attribute \src "issuer_ls180.v:114847.9-114847.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:563" + switch \sel_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 3'001 + assign { } { } + assign $1\cr_bitfield[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 3'010 + assign { } { } + assign $1\cr_bitfield[2:0] \X_BF + attribute \src "issuer_ls180.v:0.0-0.0" + case 3'011 + assign { } { } + assign $1\cr_bitfield[2:0] \XL_BT [4:2] + case + assign $1\cr_bitfield[2:0] 3'000 + end + sync always + update \cr_bitfield $0\cr_bitfield[2:0] + end + attribute \src "issuer_ls180.v:114865.3-114875.6" + process $proc$issuer_ls180.v:114865$4488 + assign { } { } + assign { } { } + assign $0\move_one[0:0] $1\move_one[0:0] + attribute \src "issuer_ls180.v:114866.5-114866.29" + switch \initial + attribute \src "issuer_ls180.v:114866.9-114866.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:563" + switch \sel_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 3'100 + assign { } { } + assign $1\move_one[0:0] \insn_in [20] + case + assign $1\move_one[0:0] 1'0 + end + sync always + update \move_one $0\move_one[0:0] + end + attribute \src "issuer_ls180.v:114876.3-114896.6" + process $proc$issuer_ls180.v:114876$4489 + assign { } { } + assign { } { } + assign $0\ppick_i[7:0] $1\ppick_i[7:0] + attribute \src "issuer_ls180.v:114877.5-114877.29" + switch \initial + attribute \src "issuer_ls180.v:114877.9-114877.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:563" + switch \sel_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 3'100 + assign { } { } + assign $1\ppick_i[7:0] $2\ppick_i[7:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:579" + switch \$1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\ppick_i[7:0] $3\ppick_i[7:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:580" + switch \move_one + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\ppick_i[7:0] \LOGICAL_FXM + case + assign $3\ppick_i[7:0] 8'00000000 + end + case + assign $2\ppick_i[7:0] 8'00000000 + end + case + assign $1\ppick_i[7:0] 8'00000000 + end + sync always + update \ppick_i $0\ppick_i[7:0] + end + attribute \src "issuer_ls180.v:114897.3-114931.6" + process $proc$issuer_ls180.v:114897$4490 + assign { } { } + assign { } { } + assign $0\cr_fxm[7:0] $1\cr_fxm[7:0] + attribute \src "issuer_ls180.v:114898.5-114898.29" + switch \initial + attribute \src "issuer_ls180.v:114898.9-114898.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:563" + switch \sel_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 3'100 + assign { } { } + assign $1\cr_fxm[7:0] $2\cr_fxm[7:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:579" + switch \$3 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\cr_fxm[7:0] $3\cr_fxm[7:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:580" + switch \move_one + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\cr_fxm[7:0] $4\cr_fxm[7:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:583" + switch \ppick_en_o + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\cr_fxm[7:0] \ppick_o + attribute \src "issuer_ls180.v:0.0-0.0" + case + assign { } { } + assign $4\cr_fxm[7:0] 8'00000001 + end + attribute \src "issuer_ls180.v:0.0-0.0" + case + assign { } { } + assign $3\cr_fxm[7:0] \LOGICAL_FXM + end + attribute \src "issuer_ls180.v:0.0-0.0" + case + assign { } { } + assign $2\cr_fxm[7:0] 8'11111111 + end + case + assign $1\cr_fxm[7:0] 8'00000000 + end + sync always + update \cr_fxm $0\cr_fxm[7:0] + end + connect \$1 $eq$issuer_ls180.v:114809$4483_Y + connect \$3 $eq$issuer_ls180.v:114810$4484_Y +end +attribute \src "issuer_ls180.v:114936.1-115175.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.dec_SPR.dec_cr_out" +attribute \generator "nMigen" +module \dec_cr_out$166 + attribute \src "issuer_ls180.v:115089.3-115107.6" + wire width 3 $0\cr_bitfield[2:0] + attribute \src "issuer_ls180.v:115059.3-115077.6" + wire $0\cr_bitfield_ok[0:0] + attribute \src "issuer_ls180.v:115140.3-115174.6" + wire width 8 $0\cr_fxm[7:0] + attribute \src "issuer_ls180.v:115078.3-115088.6" + wire $0\cr_fxm_ok[0:0] + attribute \src "issuer_ls180.v:114937.7-114937.20" + wire $0\initial[0:0] + attribute \src "issuer_ls180.v:115108.3-115118.6" + wire $0\move_one[0:0] + attribute \src "issuer_ls180.v:115119.3-115139.6" + wire width 8 $0\ppick_i[7:0] + attribute \src "issuer_ls180.v:115089.3-115107.6" + wire width 3 $1\cr_bitfield[2:0] + attribute \src "issuer_ls180.v:115059.3-115077.6" + wire $1\cr_bitfield_ok[0:0] + attribute \src "issuer_ls180.v:115140.3-115174.6" + wire width 8 $1\cr_fxm[7:0] + attribute \src "issuer_ls180.v:115078.3-115088.6" + wire $1\cr_fxm_ok[0:0] + attribute \src "issuer_ls180.v:115108.3-115118.6" + wire $1\move_one[0:0] + attribute \src "issuer_ls180.v:115119.3-115139.6" + wire width 8 $1\ppick_i[7:0] + attribute \src "issuer_ls180.v:115140.3-115174.6" + wire width 8 $2\cr_fxm[7:0] + attribute \src "issuer_ls180.v:115119.3-115139.6" + wire width 8 $2\ppick_i[7:0] + attribute \src "issuer_ls180.v:115140.3-115174.6" + wire width 8 $3\cr_fxm[7:0] + attribute \src "issuer_ls180.v:115119.3-115139.6" + wire width 8 $3\ppick_i[7:0] + attribute \src "issuer_ls180.v:115140.3-115174.6" + wire width 8 $4\cr_fxm[7:0] + attribute \src "issuer_ls180.v:115052.17-115052.121" + wire $eq$issuer_ls180.v:115052$4492_Y + attribute \src "issuer_ls180.v:115053.17-115053.121" + wire $eq$issuer_ls180.v:115053$4493_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:579" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:579" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 8 input 4 \SPR_FXM + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 7 input 3 \SPR_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 input 6 \XL_BT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 3 input 5 \X_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 3 \cr_bitfield + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \cr_bitfield_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 8 \cr_fxm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \cr_fxm_ok + attribute \src "issuer_ls180.v:114937.7-114937.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:550" + wire width 32 input 7 \insn_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:577" + wire \move_one + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" + wire \ppick_en_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" + wire width 8 \ppick_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" + wire width 8 \ppick_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:548" + wire input 2 \rc_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:549" + wire width 3 input 1 \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:579" + cell $eq $eq$issuer_ls180.v:115052$4492 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \SPR_internal_op + connect \B 7'0110000 + connect \Y $eq$issuer_ls180.v:115052$4492_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:579" + cell $eq $eq$issuer_ls180.v:115053$4493 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \SPR_internal_op + connect \B 7'0110000 + connect \Y $eq$issuer_ls180.v:115053$4493_Y + end + attribute \module_not_derived 1 + attribute \src "issuer_ls180.v:115054.15-115058.4" + cell \ppick$167 \ppick + connect \en_o \ppick_en_o + connect \i \ppick_i + connect \o \ppick_o + end + attribute \src "issuer_ls180.v:114937.7-114937.20" + process $proc$issuer_ls180.v:114937$4500 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "issuer_ls180.v:115059.3-115077.6" + process $proc$issuer_ls180.v:115059$4494 + assign { } { } + assign { } { } + assign $0\cr_bitfield_ok[0:0] $1\cr_bitfield_ok[0:0] + attribute \src "issuer_ls180.v:115060.5-115060.29" + switch \initial + attribute \src "issuer_ls180.v:115060.9-115060.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:563" + switch \sel_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 3'001 + assign { } { } + assign $1\cr_bitfield_ok[0:0] \rc_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 3'010 + assign { } { } + assign $1\cr_bitfield_ok[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 3'011 + assign { } { } + assign $1\cr_bitfield_ok[0:0] 1'1 + case + assign $1\cr_bitfield_ok[0:0] 1'0 + end + sync always + update \cr_bitfield_ok $0\cr_bitfield_ok[0:0] + end + attribute \src "issuer_ls180.v:115078.3-115088.6" + process $proc$issuer_ls180.v:115078$4495 + assign { } { } + assign { } { } + assign $0\cr_fxm_ok[0:0] $1\cr_fxm_ok[0:0] + attribute \src "issuer_ls180.v:115079.5-115079.29" + switch \initial + attribute \src "issuer_ls180.v:115079.9-115079.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:563" + switch \sel_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 3'100 + assign { } { } + assign $1\cr_fxm_ok[0:0] 1'1 + case + assign $1\cr_fxm_ok[0:0] 1'0 + end + sync always + update \cr_fxm_ok $0\cr_fxm_ok[0:0] + end + attribute \src "issuer_ls180.v:115089.3-115107.6" + process $proc$issuer_ls180.v:115089$4496 + assign { } { } + assign { } { } + assign $0\cr_bitfield[2:0] $1\cr_bitfield[2:0] + attribute \src "issuer_ls180.v:115090.5-115090.29" + switch \initial + attribute \src "issuer_ls180.v:115090.9-115090.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:563" + switch \sel_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 3'001 + assign { } { } + assign $1\cr_bitfield[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 3'010 + assign { } { } + assign $1\cr_bitfield[2:0] \X_BF + attribute \src "issuer_ls180.v:0.0-0.0" + case 3'011 + assign { } { } + assign $1\cr_bitfield[2:0] \XL_BT [4:2] + case + assign $1\cr_bitfield[2:0] 3'000 + end + sync always + update \cr_bitfield $0\cr_bitfield[2:0] + end + attribute \src "issuer_ls180.v:115108.3-115118.6" + process $proc$issuer_ls180.v:115108$4497 + assign { } { } + assign { } { } + assign $0\move_one[0:0] $1\move_one[0:0] + attribute \src "issuer_ls180.v:115109.5-115109.29" + switch \initial + attribute \src "issuer_ls180.v:115109.9-115109.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:563" + switch \sel_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 3'100 + assign { } { } + assign $1\move_one[0:0] \insn_in [20] + case + assign $1\move_one[0:0] 1'0 + end + sync always + update \move_one $0\move_one[0:0] + end + attribute \src "issuer_ls180.v:115119.3-115139.6" + process $proc$issuer_ls180.v:115119$4498 + assign { } { } + assign { } { } + assign $0\ppick_i[7:0] $1\ppick_i[7:0] + attribute \src "issuer_ls180.v:115120.5-115120.29" + switch \initial + attribute \src "issuer_ls180.v:115120.9-115120.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:563" + switch \sel_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 3'100 + assign { } { } + assign $1\ppick_i[7:0] $2\ppick_i[7:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:579" + switch \$1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\ppick_i[7:0] $3\ppick_i[7:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:580" + switch \move_one + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\ppick_i[7:0] \SPR_FXM + case + assign $3\ppick_i[7:0] 8'00000000 + end + case + assign $2\ppick_i[7:0] 8'00000000 + end + case + assign $1\ppick_i[7:0] 8'00000000 + end + sync always + update \ppick_i $0\ppick_i[7:0] + end + attribute \src "issuer_ls180.v:115140.3-115174.6" + process $proc$issuer_ls180.v:115140$4499 + assign { } { } + assign { } { } + assign $0\cr_fxm[7:0] $1\cr_fxm[7:0] + attribute \src "issuer_ls180.v:115141.5-115141.29" + switch \initial + attribute \src "issuer_ls180.v:115141.9-115141.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:563" + switch \sel_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 3'100 + assign { } { } + assign $1\cr_fxm[7:0] $2\cr_fxm[7:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:579" + switch \$3 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\cr_fxm[7:0] $3\cr_fxm[7:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:580" + switch \move_one + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\cr_fxm[7:0] $4\cr_fxm[7:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:583" + switch \ppick_en_o + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\cr_fxm[7:0] \ppick_o + attribute \src "issuer_ls180.v:0.0-0.0" + case + assign { } { } + assign $4\cr_fxm[7:0] 8'00000001 + end + attribute \src "issuer_ls180.v:0.0-0.0" + case + assign { } { } + assign $3\cr_fxm[7:0] \SPR_FXM + end + attribute \src "issuer_ls180.v:0.0-0.0" + case + assign { } { } + assign $2\cr_fxm[7:0] 8'11111111 + end + case + assign $1\cr_fxm[7:0] 8'00000000 + end + sync always + update \cr_fxm $0\cr_fxm[7:0] + end + connect \$1 $eq$issuer_ls180.v:115052$4492_Y + connect \$3 $eq$issuer_ls180.v:115053$4493_Y +end +attribute \src "issuer_ls180.v:115179.1-115419.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.dec_DIV.dec_cr_out" +attribute \generator "nMigen" +module \dec_cr_out$173 + attribute \src "issuer_ls180.v:115333.3-115351.6" + wire width 3 $0\cr_bitfield[2:0] + attribute \src "issuer_ls180.v:115303.3-115321.6" + wire $0\cr_bitfield_ok[0:0] + attribute \src "issuer_ls180.v:115384.3-115418.6" + wire width 8 $0\cr_fxm[7:0] + attribute \src "issuer_ls180.v:115322.3-115332.6" + wire $0\cr_fxm_ok[0:0] + attribute \src "issuer_ls180.v:115180.7-115180.20" + wire $0\initial[0:0] + attribute \src "issuer_ls180.v:115352.3-115362.6" + wire $0\move_one[0:0] + attribute \src "issuer_ls180.v:115363.3-115383.6" + wire width 8 $0\ppick_i[7:0] + attribute \src "issuer_ls180.v:115333.3-115351.6" + wire width 3 $1\cr_bitfield[2:0] + attribute \src "issuer_ls180.v:115303.3-115321.6" + wire $1\cr_bitfield_ok[0:0] + attribute \src "issuer_ls180.v:115384.3-115418.6" + wire width 8 $1\cr_fxm[7:0] + attribute \src "issuer_ls180.v:115322.3-115332.6" + wire $1\cr_fxm_ok[0:0] + attribute \src "issuer_ls180.v:115352.3-115362.6" + wire $1\move_one[0:0] + attribute \src "issuer_ls180.v:115363.3-115383.6" + wire width 8 $1\ppick_i[7:0] + attribute \src "issuer_ls180.v:115384.3-115418.6" + wire width 8 $2\cr_fxm[7:0] + attribute \src "issuer_ls180.v:115363.3-115383.6" + wire width 8 $2\ppick_i[7:0] + attribute \src "issuer_ls180.v:115384.3-115418.6" + wire width 8 $3\cr_fxm[7:0] + attribute \src "issuer_ls180.v:115363.3-115383.6" + wire width 8 $3\ppick_i[7:0] + attribute \src "issuer_ls180.v:115384.3-115418.6" + wire width 8 $4\cr_fxm[7:0] + attribute \src "issuer_ls180.v:115296.17-115296.121" + wire $eq$issuer_ls180.v:115296$4501_Y + attribute \src "issuer_ls180.v:115297.17-115297.121" + wire $eq$issuer_ls180.v:115297$4502_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:579" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:579" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 8 input 5 \DIV_FXM + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 7 input 3 \DIV_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 input 7 \XL_BT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 3 input 6 \X_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 3 \cr_bitfield + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 4 \cr_bitfield_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 8 \cr_fxm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \cr_fxm_ok + attribute \src "issuer_ls180.v:115180.7-115180.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:550" + wire width 32 input 8 \insn_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:577" + wire \move_one + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" + wire \ppick_en_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" + wire width 8 \ppick_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" + wire width 8 \ppick_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:548" + wire input 2 \rc_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:549" + wire width 3 input 1 \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:579" + cell $eq $eq$issuer_ls180.v:115296$4501 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \DIV_internal_op + connect \B 7'0110000 + connect \Y $eq$issuer_ls180.v:115296$4501_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:579" + cell $eq $eq$issuer_ls180.v:115297$4502 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \DIV_internal_op + connect \B 7'0110000 + connect \Y $eq$issuer_ls180.v:115297$4502_Y + end + attribute \module_not_derived 1 + attribute \src "issuer_ls180.v:115298.15-115302.4" + cell \ppick$174 \ppick + connect \en_o \ppick_en_o + connect \i \ppick_i + connect \o \ppick_o + end + attribute \src "issuer_ls180.v:115180.7-115180.20" + process $proc$issuer_ls180.v:115180$4509 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "issuer_ls180.v:115303.3-115321.6" + process $proc$issuer_ls180.v:115303$4503 + assign { } { } + assign { } { } + assign $0\cr_bitfield_ok[0:0] $1\cr_bitfield_ok[0:0] + attribute \src "issuer_ls180.v:115304.5-115304.29" + switch \initial + attribute \src "issuer_ls180.v:115304.9-115304.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:563" + switch \sel_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 3'001 + assign { } { } + assign $1\cr_bitfield_ok[0:0] \rc_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 3'010 + assign { } { } + assign $1\cr_bitfield_ok[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 3'011 + assign { } { } + assign $1\cr_bitfield_ok[0:0] 1'1 + case + assign $1\cr_bitfield_ok[0:0] 1'0 + end + sync always + update \cr_bitfield_ok $0\cr_bitfield_ok[0:0] + end + attribute \src "issuer_ls180.v:115322.3-115332.6" + process $proc$issuer_ls180.v:115322$4504 + assign { } { } + assign { } { } + assign $0\cr_fxm_ok[0:0] $1\cr_fxm_ok[0:0] + attribute \src "issuer_ls180.v:115323.5-115323.29" + switch \initial + attribute \src "issuer_ls180.v:115323.9-115323.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:563" + switch \sel_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 3'100 + assign { } { } + assign $1\cr_fxm_ok[0:0] 1'1 + case + assign $1\cr_fxm_ok[0:0] 1'0 + end + sync always + update \cr_fxm_ok $0\cr_fxm_ok[0:0] + end + attribute \src "issuer_ls180.v:115333.3-115351.6" + process $proc$issuer_ls180.v:115333$4505 + assign { } { } + assign { } { } + assign $0\cr_bitfield[2:0] $1\cr_bitfield[2:0] + attribute \src "issuer_ls180.v:115334.5-115334.29" + switch \initial + attribute \src "issuer_ls180.v:115334.9-115334.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:563" + switch \sel_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 3'001 + assign { } { } + assign $1\cr_bitfield[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 3'010 + assign { } { } + assign $1\cr_bitfield[2:0] \X_BF + attribute \src "issuer_ls180.v:0.0-0.0" + case 3'011 + assign { } { } + assign $1\cr_bitfield[2:0] \XL_BT [4:2] + case + assign $1\cr_bitfield[2:0] 3'000 + end + sync always + update \cr_bitfield $0\cr_bitfield[2:0] + end + attribute \src "issuer_ls180.v:115352.3-115362.6" + process $proc$issuer_ls180.v:115352$4506 + assign { } { } + assign { } { } + assign $0\move_one[0:0] $1\move_one[0:0] + attribute \src "issuer_ls180.v:115353.5-115353.29" + switch \initial + attribute \src "issuer_ls180.v:115353.9-115353.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:563" + switch \sel_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 3'100 + assign { } { } + assign $1\move_one[0:0] \insn_in [20] + case + assign $1\move_one[0:0] 1'0 + end + sync always + update \move_one $0\move_one[0:0] + end + attribute \src "issuer_ls180.v:115363.3-115383.6" + process $proc$issuer_ls180.v:115363$4507 + assign { } { } + assign { } { } + assign $0\ppick_i[7:0] $1\ppick_i[7:0] + attribute \src "issuer_ls180.v:115364.5-115364.29" + switch \initial + attribute \src "issuer_ls180.v:115364.9-115364.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:563" + switch \sel_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 3'100 + assign { } { } + assign $1\ppick_i[7:0] $2\ppick_i[7:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:579" + switch \$1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\ppick_i[7:0] $3\ppick_i[7:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:580" + switch \move_one + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\ppick_i[7:0] \DIV_FXM + case + assign $3\ppick_i[7:0] 8'00000000 + end + case + assign $2\ppick_i[7:0] 8'00000000 + end + case + assign $1\ppick_i[7:0] 8'00000000 + end + sync always + update \ppick_i $0\ppick_i[7:0] + end + attribute \src "issuer_ls180.v:115384.3-115418.6" + process $proc$issuer_ls180.v:115384$4508 + assign { } { } + assign { } { } + assign $0\cr_fxm[7:0] $1\cr_fxm[7:0] + attribute \src "issuer_ls180.v:115385.5-115385.29" + switch \initial + attribute \src "issuer_ls180.v:115385.9-115385.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:563" + switch \sel_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 3'100 + assign { } { } + assign $1\cr_fxm[7:0] $2\cr_fxm[7:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:579" + switch \$3 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\cr_fxm[7:0] $3\cr_fxm[7:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:580" + switch \move_one + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\cr_fxm[7:0] $4\cr_fxm[7:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:583" + switch \ppick_en_o + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\cr_fxm[7:0] \ppick_o + attribute \src "issuer_ls180.v:0.0-0.0" + case + assign { } { } + assign $4\cr_fxm[7:0] 8'00000001 + end + attribute \src "issuer_ls180.v:0.0-0.0" + case + assign { } { } + assign $3\cr_fxm[7:0] \DIV_FXM + end + attribute \src "issuer_ls180.v:0.0-0.0" + case + assign { } { } + assign $2\cr_fxm[7:0] 8'11111111 + end + case + assign $1\cr_fxm[7:0] 8'00000000 + end + sync always + update \cr_fxm $0\cr_fxm[7:0] + end + connect \$1 $eq$issuer_ls180.v:115296$4501_Y + connect \$3 $eq$issuer_ls180.v:115297$4502_Y +end +attribute \src "issuer_ls180.v:115423.1-115663.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.dec_MUL.dec_cr_out" +attribute \generator "nMigen" +module \dec_cr_out$182 + attribute \src "issuer_ls180.v:115577.3-115595.6" + wire width 3 $0\cr_bitfield[2:0] + attribute \src "issuer_ls180.v:115547.3-115565.6" + wire $0\cr_bitfield_ok[0:0] + attribute \src "issuer_ls180.v:115628.3-115662.6" + wire width 8 $0\cr_fxm[7:0] + attribute \src "issuer_ls180.v:115566.3-115576.6" + wire $0\cr_fxm_ok[0:0] + attribute \src "issuer_ls180.v:115424.7-115424.20" + wire $0\initial[0:0] + attribute \src "issuer_ls180.v:115596.3-115606.6" + wire $0\move_one[0:0] + attribute \src "issuer_ls180.v:115607.3-115627.6" + wire width 8 $0\ppick_i[7:0] + attribute \src "issuer_ls180.v:115577.3-115595.6" + wire width 3 $1\cr_bitfield[2:0] + attribute \src "issuer_ls180.v:115547.3-115565.6" + wire $1\cr_bitfield_ok[0:0] + attribute \src "issuer_ls180.v:115628.3-115662.6" + wire width 8 $1\cr_fxm[7:0] + attribute \src "issuer_ls180.v:115566.3-115576.6" + wire $1\cr_fxm_ok[0:0] + attribute \src "issuer_ls180.v:115596.3-115606.6" + wire $1\move_one[0:0] + attribute \src "issuer_ls180.v:115607.3-115627.6" + wire width 8 $1\ppick_i[7:0] + attribute \src "issuer_ls180.v:115628.3-115662.6" + wire width 8 $2\cr_fxm[7:0] + attribute \src "issuer_ls180.v:115607.3-115627.6" + wire width 8 $2\ppick_i[7:0] + attribute \src "issuer_ls180.v:115628.3-115662.6" + wire width 8 $3\cr_fxm[7:0] + attribute \src "issuer_ls180.v:115607.3-115627.6" + wire width 8 $3\ppick_i[7:0] + attribute \src "issuer_ls180.v:115628.3-115662.6" + wire width 8 $4\cr_fxm[7:0] + attribute \src "issuer_ls180.v:115540.17-115540.121" + wire $eq$issuer_ls180.v:115540$4510_Y + attribute \src "issuer_ls180.v:115541.17-115541.121" + wire $eq$issuer_ls180.v:115541$4511_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:579" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:579" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 8 input 5 \MUL_FXM + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 7 input 3 \MUL_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 input 7 \XL_BT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 3 input 6 \X_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 3 \cr_bitfield + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 4 \cr_bitfield_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 8 \cr_fxm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \cr_fxm_ok + attribute \src "issuer_ls180.v:115424.7-115424.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:550" + wire width 32 input 8 \insn_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:577" + wire \move_one + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" + wire \ppick_en_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" + wire width 8 \ppick_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" + wire width 8 \ppick_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:548" + wire input 2 \rc_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:549" + wire width 3 input 1 \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:579" + cell $eq $eq$issuer_ls180.v:115540$4510 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \MUL_internal_op + connect \B 7'0110000 + connect \Y $eq$issuer_ls180.v:115540$4510_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:579" + cell $eq $eq$issuer_ls180.v:115541$4511 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \MUL_internal_op + connect \B 7'0110000 + connect \Y $eq$issuer_ls180.v:115541$4511_Y + end + attribute \module_not_derived 1 + attribute \src "issuer_ls180.v:115542.15-115546.4" + cell \ppick$183 \ppick + connect \en_o \ppick_en_o + connect \i \ppick_i + connect \o \ppick_o + end + attribute \src "issuer_ls180.v:115424.7-115424.20" + process $proc$issuer_ls180.v:115424$4518 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "issuer_ls180.v:115547.3-115565.6" + process $proc$issuer_ls180.v:115547$4512 + assign { } { } + assign { } { } + assign $0\cr_bitfield_ok[0:0] $1\cr_bitfield_ok[0:0] + attribute \src "issuer_ls180.v:115548.5-115548.29" + switch \initial + attribute \src "issuer_ls180.v:115548.9-115548.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:563" + switch \sel_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 3'001 + assign { } { } + assign $1\cr_bitfield_ok[0:0] \rc_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 3'010 + assign { } { } + assign $1\cr_bitfield_ok[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 3'011 + assign { } { } + assign $1\cr_bitfield_ok[0:0] 1'1 + case + assign $1\cr_bitfield_ok[0:0] 1'0 + end + sync always + update \cr_bitfield_ok $0\cr_bitfield_ok[0:0] + end + attribute \src "issuer_ls180.v:115566.3-115576.6" + process $proc$issuer_ls180.v:115566$4513 + assign { } { } + assign { } { } + assign $0\cr_fxm_ok[0:0] $1\cr_fxm_ok[0:0] + attribute \src "issuer_ls180.v:115567.5-115567.29" + switch \initial + attribute \src "issuer_ls180.v:115567.9-115567.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:563" + switch \sel_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 3'100 + assign { } { } + assign $1\cr_fxm_ok[0:0] 1'1 + case + assign $1\cr_fxm_ok[0:0] 1'0 + end + sync always + update \cr_fxm_ok $0\cr_fxm_ok[0:0] + end + attribute \src "issuer_ls180.v:115577.3-115595.6" + process $proc$issuer_ls180.v:115577$4514 + assign { } { } + assign { } { } + assign $0\cr_bitfield[2:0] $1\cr_bitfield[2:0] + attribute \src "issuer_ls180.v:115578.5-115578.29" + switch \initial + attribute \src "issuer_ls180.v:115578.9-115578.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:563" + switch \sel_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 3'001 + assign { } { } + assign $1\cr_bitfield[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 3'010 + assign { } { } + assign $1\cr_bitfield[2:0] \X_BF + attribute \src "issuer_ls180.v:0.0-0.0" + case 3'011 + assign { } { } + assign $1\cr_bitfield[2:0] \XL_BT [4:2] + case + assign $1\cr_bitfield[2:0] 3'000 + end + sync always + update \cr_bitfield $0\cr_bitfield[2:0] + end + attribute \src "issuer_ls180.v:115596.3-115606.6" + process $proc$issuer_ls180.v:115596$4515 + assign { } { } + assign { } { } + assign $0\move_one[0:0] $1\move_one[0:0] + attribute \src "issuer_ls180.v:115597.5-115597.29" + switch \initial + attribute \src "issuer_ls180.v:115597.9-115597.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:563" + switch \sel_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 3'100 + assign { } { } + assign $1\move_one[0:0] \insn_in [20] + case + assign $1\move_one[0:0] 1'0 + end + sync always + update \move_one $0\move_one[0:0] + end + attribute \src "issuer_ls180.v:115607.3-115627.6" + process $proc$issuer_ls180.v:115607$4516 + assign { } { } + assign { } { } + assign $0\ppick_i[7:0] $1\ppick_i[7:0] + attribute \src "issuer_ls180.v:115608.5-115608.29" + switch \initial + attribute \src "issuer_ls180.v:115608.9-115608.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:563" + switch \sel_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 3'100 + assign { } { } + assign $1\ppick_i[7:0] $2\ppick_i[7:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:579" + switch \$1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\ppick_i[7:0] $3\ppick_i[7:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:580" + switch \move_one + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\ppick_i[7:0] \MUL_FXM + case + assign $3\ppick_i[7:0] 8'00000000 + end + case + assign $2\ppick_i[7:0] 8'00000000 + end + case + assign $1\ppick_i[7:0] 8'00000000 + end + sync always + update \ppick_i $0\ppick_i[7:0] + end + attribute \src "issuer_ls180.v:115628.3-115662.6" + process $proc$issuer_ls180.v:115628$4517 + assign { } { } + assign { } { } + assign $0\cr_fxm[7:0] $1\cr_fxm[7:0] + attribute \src "issuer_ls180.v:115629.5-115629.29" + switch \initial + attribute \src "issuer_ls180.v:115629.9-115629.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:563" + switch \sel_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 3'100 + assign { } { } + assign $1\cr_fxm[7:0] $2\cr_fxm[7:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:579" + switch \$3 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\cr_fxm[7:0] $3\cr_fxm[7:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:580" + switch \move_one + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\cr_fxm[7:0] $4\cr_fxm[7:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:583" + switch \ppick_en_o + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\cr_fxm[7:0] \ppick_o + attribute \src "issuer_ls180.v:0.0-0.0" + case + assign { } { } + assign $4\cr_fxm[7:0] 8'00000001 + end + attribute \src "issuer_ls180.v:0.0-0.0" + case + assign { } { } + assign $3\cr_fxm[7:0] \MUL_FXM + end + attribute \src "issuer_ls180.v:0.0-0.0" + case + assign { } { } + assign $2\cr_fxm[7:0] 8'11111111 + end + case + assign $1\cr_fxm[7:0] 8'00000000 + end + sync always + update \cr_fxm $0\cr_fxm[7:0] + end + connect \$1 $eq$issuer_ls180.v:115540$4510_Y + connect \$3 $eq$issuer_ls180.v:115541$4511_Y +end +attribute \src "issuer_ls180.v:115667.1-115907.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.dec_SHIFT_ROT.dec_cr_out" +attribute \generator "nMigen" +module \dec_cr_out$190 + attribute \src "issuer_ls180.v:115821.3-115839.6" + wire width 3 $0\cr_bitfield[2:0] + attribute \src "issuer_ls180.v:115791.3-115809.6" + wire $0\cr_bitfield_ok[0:0] + attribute \src "issuer_ls180.v:115872.3-115906.6" + wire width 8 $0\cr_fxm[7:0] + attribute \src "issuer_ls180.v:115810.3-115820.6" + wire $0\cr_fxm_ok[0:0] + attribute \src "issuer_ls180.v:115668.7-115668.20" + wire $0\initial[0:0] + attribute \src "issuer_ls180.v:115840.3-115850.6" + wire $0\move_one[0:0] + attribute \src "issuer_ls180.v:115851.3-115871.6" + wire width 8 $0\ppick_i[7:0] + attribute \src "issuer_ls180.v:115821.3-115839.6" + wire width 3 $1\cr_bitfield[2:0] + attribute \src "issuer_ls180.v:115791.3-115809.6" + wire $1\cr_bitfield_ok[0:0] + attribute \src "issuer_ls180.v:115872.3-115906.6" + wire width 8 $1\cr_fxm[7:0] + attribute \src "issuer_ls180.v:115810.3-115820.6" + wire $1\cr_fxm_ok[0:0] + attribute \src "issuer_ls180.v:115840.3-115850.6" + wire $1\move_one[0:0] + attribute \src "issuer_ls180.v:115851.3-115871.6" + wire width 8 $1\ppick_i[7:0] + attribute \src "issuer_ls180.v:115872.3-115906.6" + wire width 8 $2\cr_fxm[7:0] + attribute \src "issuer_ls180.v:115851.3-115871.6" + wire width 8 $2\ppick_i[7:0] + attribute \src "issuer_ls180.v:115872.3-115906.6" + wire width 8 $3\cr_fxm[7:0] + attribute \src "issuer_ls180.v:115851.3-115871.6" + wire width 8 $3\ppick_i[7:0] + attribute \src "issuer_ls180.v:115872.3-115906.6" + wire width 8 $4\cr_fxm[7:0] + attribute \src "issuer_ls180.v:115784.17-115784.127" + wire $eq$issuer_ls180.v:115784$4519_Y + attribute \src "issuer_ls180.v:115785.17-115785.127" + wire $eq$issuer_ls180.v:115785$4520_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:579" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:579" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 8 input 5 \SHIFT_ROT_FXM + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 7 input 3 \SHIFT_ROT_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 input 7 \XL_BT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 3 input 6 \X_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 3 \cr_bitfield + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 4 \cr_bitfield_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 8 \cr_fxm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \cr_fxm_ok + attribute \src "issuer_ls180.v:115668.7-115668.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:550" + wire width 32 input 8 \insn_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:577" + wire \move_one + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" + wire \ppick_en_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" + wire width 8 \ppick_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" + wire width 8 \ppick_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:548" + wire input 2 \rc_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:549" + wire width 3 input 1 \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:579" + cell $eq $eq$issuer_ls180.v:115784$4519 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \SHIFT_ROT_internal_op + connect \B 7'0110000 + connect \Y $eq$issuer_ls180.v:115784$4519_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:579" + cell $eq $eq$issuer_ls180.v:115785$4520 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \SHIFT_ROT_internal_op + connect \B 7'0110000 + connect \Y $eq$issuer_ls180.v:115785$4520_Y + end + attribute \module_not_derived 1 + attribute \src "issuer_ls180.v:115786.15-115790.4" + cell \ppick$191 \ppick + connect \en_o \ppick_en_o + connect \i \ppick_i + connect \o \ppick_o + end + attribute \src "issuer_ls180.v:115668.7-115668.20" + process $proc$issuer_ls180.v:115668$4527 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "issuer_ls180.v:115791.3-115809.6" + process $proc$issuer_ls180.v:115791$4521 + assign { } { } + assign { } { } + assign $0\cr_bitfield_ok[0:0] $1\cr_bitfield_ok[0:0] + attribute \src "issuer_ls180.v:115792.5-115792.29" + switch \initial + attribute \src "issuer_ls180.v:115792.9-115792.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:563" + switch \sel_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 3'001 + assign { } { } + assign $1\cr_bitfield_ok[0:0] \rc_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 3'010 + assign { } { } + assign $1\cr_bitfield_ok[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 3'011 + assign { } { } + assign $1\cr_bitfield_ok[0:0] 1'1 + case + assign $1\cr_bitfield_ok[0:0] 1'0 + end + sync always + update \cr_bitfield_ok $0\cr_bitfield_ok[0:0] + end + attribute \src "issuer_ls180.v:115810.3-115820.6" + process $proc$issuer_ls180.v:115810$4522 + assign { } { } + assign { } { } + assign $0\cr_fxm_ok[0:0] $1\cr_fxm_ok[0:0] + attribute \src "issuer_ls180.v:115811.5-115811.29" + switch \initial + attribute \src "issuer_ls180.v:115811.9-115811.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:563" + switch \sel_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 3'100 + assign { } { } + assign $1\cr_fxm_ok[0:0] 1'1 + case + assign $1\cr_fxm_ok[0:0] 1'0 + end + sync always + update \cr_fxm_ok $0\cr_fxm_ok[0:0] + end + attribute \src "issuer_ls180.v:115821.3-115839.6" + process $proc$issuer_ls180.v:115821$4523 + assign { } { } + assign { } { } + assign $0\cr_bitfield[2:0] $1\cr_bitfield[2:0] + attribute \src "issuer_ls180.v:115822.5-115822.29" + switch \initial + attribute \src "issuer_ls180.v:115822.9-115822.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:563" + switch \sel_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 3'001 + assign { } { } + assign $1\cr_bitfield[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 3'010 + assign { } { } + assign $1\cr_bitfield[2:0] \X_BF + attribute \src "issuer_ls180.v:0.0-0.0" + case 3'011 + assign { } { } + assign $1\cr_bitfield[2:0] \XL_BT [4:2] + case + assign $1\cr_bitfield[2:0] 3'000 + end + sync always + update \cr_bitfield $0\cr_bitfield[2:0] + end + attribute \src "issuer_ls180.v:115840.3-115850.6" + process $proc$issuer_ls180.v:115840$4524 + assign { } { } + assign { } { } + assign $0\move_one[0:0] $1\move_one[0:0] + attribute \src "issuer_ls180.v:115841.5-115841.29" + switch \initial + attribute \src "issuer_ls180.v:115841.9-115841.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:563" + switch \sel_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 3'100 + assign { } { } + assign $1\move_one[0:0] \insn_in [20] + case + assign $1\move_one[0:0] 1'0 + end + sync always + update \move_one $0\move_one[0:0] + end + attribute \src "issuer_ls180.v:115851.3-115871.6" + process $proc$issuer_ls180.v:115851$4525 + assign { } { } + assign { } { } + assign $0\ppick_i[7:0] $1\ppick_i[7:0] + attribute \src "issuer_ls180.v:115852.5-115852.29" + switch \initial + attribute \src "issuer_ls180.v:115852.9-115852.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:563" + switch \sel_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 3'100 + assign { } { } + assign $1\ppick_i[7:0] $2\ppick_i[7:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:579" + switch \$1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\ppick_i[7:0] $3\ppick_i[7:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:580" + switch \move_one + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\ppick_i[7:0] \SHIFT_ROT_FXM + case + assign $3\ppick_i[7:0] 8'00000000 + end + case + assign $2\ppick_i[7:0] 8'00000000 + end + case + assign $1\ppick_i[7:0] 8'00000000 + end + sync always + update \ppick_i $0\ppick_i[7:0] + end + attribute \src "issuer_ls180.v:115872.3-115906.6" + process $proc$issuer_ls180.v:115872$4526 + assign { } { } + assign { } { } + assign $0\cr_fxm[7:0] $1\cr_fxm[7:0] + attribute \src "issuer_ls180.v:115873.5-115873.29" + switch \initial + attribute \src "issuer_ls180.v:115873.9-115873.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:563" + switch \sel_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 3'100 + assign { } { } + assign $1\cr_fxm[7:0] $2\cr_fxm[7:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:579" + switch \$3 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\cr_fxm[7:0] $3\cr_fxm[7:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:580" + switch \move_one + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\cr_fxm[7:0] $4\cr_fxm[7:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:583" + switch \ppick_en_o + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\cr_fxm[7:0] \ppick_o + attribute \src "issuer_ls180.v:0.0-0.0" + case + assign { } { } + assign $4\cr_fxm[7:0] 8'00000001 + end + attribute \src "issuer_ls180.v:0.0-0.0" + case + assign { } { } + assign $3\cr_fxm[7:0] \SHIFT_ROT_FXM + end + attribute \src "issuer_ls180.v:0.0-0.0" + case + assign { } { } + assign $2\cr_fxm[7:0] 8'11111111 + end + case + assign $1\cr_fxm[7:0] 8'00000000 + end + sync always + update \cr_fxm $0\cr_fxm[7:0] + end + connect \$1 $eq$issuer_ls180.v:115784$4519_Y + connect \$3 $eq$issuer_ls180.v:115785$4520_Y +end +attribute \src "issuer_ls180.v:115911.1-116150.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.dec_LDST.dec_cr_out" +attribute \generator "nMigen" +module \dec_cr_out$198 + attribute \src "issuer_ls180.v:116064.3-116082.6" + wire width 3 $0\cr_bitfield[2:0] + attribute \src "issuer_ls180.v:116034.3-116052.6" + wire $0\cr_bitfield_ok[0:0] + attribute \src "issuer_ls180.v:116115.3-116149.6" + wire width 8 $0\cr_fxm[7:0] + attribute \src "issuer_ls180.v:116053.3-116063.6" + wire $0\cr_fxm_ok[0:0] + attribute \src "issuer_ls180.v:115912.7-115912.20" + wire $0\initial[0:0] + attribute \src "issuer_ls180.v:116083.3-116093.6" + wire $0\move_one[0:0] + attribute \src "issuer_ls180.v:116094.3-116114.6" + wire width 8 $0\ppick_i[7:0] + attribute \src "issuer_ls180.v:116064.3-116082.6" + wire width 3 $1\cr_bitfield[2:0] + attribute \src "issuer_ls180.v:116034.3-116052.6" + wire $1\cr_bitfield_ok[0:0] + attribute \src "issuer_ls180.v:116115.3-116149.6" + wire width 8 $1\cr_fxm[7:0] + attribute \src "issuer_ls180.v:116053.3-116063.6" + wire $1\cr_fxm_ok[0:0] + attribute \src "issuer_ls180.v:116083.3-116093.6" + wire $1\move_one[0:0] + attribute \src "issuer_ls180.v:116094.3-116114.6" + wire width 8 $1\ppick_i[7:0] + attribute \src "issuer_ls180.v:116115.3-116149.6" + wire width 8 $2\cr_fxm[7:0] + attribute \src "issuer_ls180.v:116094.3-116114.6" + wire width 8 $2\ppick_i[7:0] + attribute \src "issuer_ls180.v:116115.3-116149.6" + wire width 8 $3\cr_fxm[7:0] + attribute \src "issuer_ls180.v:116094.3-116114.6" + wire width 8 $3\ppick_i[7:0] + attribute \src "issuer_ls180.v:116115.3-116149.6" + wire width 8 $4\cr_fxm[7:0] + attribute \src "issuer_ls180.v:116027.17-116027.122" + wire $eq$issuer_ls180.v:116027$4528_Y + attribute \src "issuer_ls180.v:116028.17-116028.122" + wire $eq$issuer_ls180.v:116028$4529_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:579" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:579" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 8 input 4 \LDST_FXM + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 7 input 3 \LDST_internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 input 6 \XL_BT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 3 input 5 \X_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 3 \cr_bitfield + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \cr_bitfield_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 8 \cr_fxm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \cr_fxm_ok + attribute \src "issuer_ls180.v:115912.7-115912.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:550" + wire width 32 input 7 \insn_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:577" + wire \move_one + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" + wire \ppick_en_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" + wire width 8 \ppick_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" + wire width 8 \ppick_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:548" + wire input 2 \rc_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:549" + wire width 3 input 1 \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:579" + cell $eq $eq$issuer_ls180.v:116027$4528 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \LDST_internal_op + connect \B 7'0110000 + connect \Y $eq$issuer_ls180.v:116027$4528_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:579" + cell $eq $eq$issuer_ls180.v:116028$4529 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \LDST_internal_op + connect \B 7'0110000 + connect \Y $eq$issuer_ls180.v:116028$4529_Y + end + attribute \module_not_derived 1 + attribute \src "issuer_ls180.v:116029.15-116033.4" + cell \ppick$199 \ppick + connect \en_o \ppick_en_o + connect \i \ppick_i + connect \o \ppick_o + end + attribute \src "issuer_ls180.v:115912.7-115912.20" + process $proc$issuer_ls180.v:115912$4536 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "issuer_ls180.v:116034.3-116052.6" + process $proc$issuer_ls180.v:116034$4530 + assign { } { } + assign { } { } + assign $0\cr_bitfield_ok[0:0] $1\cr_bitfield_ok[0:0] + attribute \src "issuer_ls180.v:116035.5-116035.29" + switch \initial + attribute \src "issuer_ls180.v:116035.9-116035.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:563" + switch \sel_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 3'001 + assign { } { } + assign $1\cr_bitfield_ok[0:0] \rc_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 3'010 + assign { } { } + assign $1\cr_bitfield_ok[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 3'011 + assign { } { } + assign $1\cr_bitfield_ok[0:0] 1'1 + case + assign $1\cr_bitfield_ok[0:0] 1'0 + end + sync always + update \cr_bitfield_ok $0\cr_bitfield_ok[0:0] + end + attribute \src "issuer_ls180.v:116053.3-116063.6" + process $proc$issuer_ls180.v:116053$4531 + assign { } { } + assign { } { } + assign $0\cr_fxm_ok[0:0] $1\cr_fxm_ok[0:0] + attribute \src "issuer_ls180.v:116054.5-116054.29" + switch \initial + attribute \src "issuer_ls180.v:116054.9-116054.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:563" + switch \sel_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 3'100 + assign { } { } + assign $1\cr_fxm_ok[0:0] 1'1 + case + assign $1\cr_fxm_ok[0:0] 1'0 + end + sync always + update \cr_fxm_ok $0\cr_fxm_ok[0:0] + end + attribute \src "issuer_ls180.v:116064.3-116082.6" + process $proc$issuer_ls180.v:116064$4532 + assign { } { } + assign { } { } + assign $0\cr_bitfield[2:0] $1\cr_bitfield[2:0] + attribute \src "issuer_ls180.v:116065.5-116065.29" + switch \initial + attribute \src "issuer_ls180.v:116065.9-116065.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:563" + switch \sel_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 3'001 + assign { } { } + assign $1\cr_bitfield[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 3'010 + assign { } { } + assign $1\cr_bitfield[2:0] \X_BF + attribute \src "issuer_ls180.v:0.0-0.0" + case 3'011 + assign { } { } + assign $1\cr_bitfield[2:0] \XL_BT [4:2] + case + assign $1\cr_bitfield[2:0] 3'000 + end + sync always + update \cr_bitfield $0\cr_bitfield[2:0] + end + attribute \src "issuer_ls180.v:116083.3-116093.6" + process $proc$issuer_ls180.v:116083$4533 + assign { } { } + assign { } { } + assign $0\move_one[0:0] $1\move_one[0:0] + attribute \src "issuer_ls180.v:116084.5-116084.29" + switch \initial + attribute \src "issuer_ls180.v:116084.9-116084.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:563" + switch \sel_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 3'100 + assign { } { } + assign $1\move_one[0:0] \insn_in [20] + case + assign $1\move_one[0:0] 1'0 + end + sync always + update \move_one $0\move_one[0:0] + end + attribute \src "issuer_ls180.v:116094.3-116114.6" + process $proc$issuer_ls180.v:116094$4534 + assign { } { } + assign { } { } + assign $0\ppick_i[7:0] $1\ppick_i[7:0] + attribute \src "issuer_ls180.v:116095.5-116095.29" + switch \initial + attribute \src "issuer_ls180.v:116095.9-116095.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:563" + switch \sel_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 3'100 + assign { } { } + assign $1\ppick_i[7:0] $2\ppick_i[7:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:579" + switch \$1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\ppick_i[7:0] $3\ppick_i[7:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:580" + switch \move_one + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\ppick_i[7:0] \LDST_FXM + case + assign $3\ppick_i[7:0] 8'00000000 + end + case + assign $2\ppick_i[7:0] 8'00000000 + end + case + assign $1\ppick_i[7:0] 8'00000000 + end + sync always + update \ppick_i $0\ppick_i[7:0] + end + attribute \src "issuer_ls180.v:116115.3-116149.6" + process $proc$issuer_ls180.v:116115$4535 + assign { } { } + assign { } { } + assign $0\cr_fxm[7:0] $1\cr_fxm[7:0] + attribute \src "issuer_ls180.v:116116.5-116116.29" + switch \initial + attribute \src "issuer_ls180.v:116116.9-116116.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:563" + switch \sel_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 3'100 + assign { } { } + assign $1\cr_fxm[7:0] $2\cr_fxm[7:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:579" + switch \$3 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\cr_fxm[7:0] $3\cr_fxm[7:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:580" + switch \move_one + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\cr_fxm[7:0] $4\cr_fxm[7:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:583" + switch \ppick_en_o + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\cr_fxm[7:0] \ppick_o + attribute \src "issuer_ls180.v:0.0-0.0" + case + assign { } { } + assign $4\cr_fxm[7:0] 8'00000001 + end + attribute \src "issuer_ls180.v:0.0-0.0" + case + assign { } { } + assign $3\cr_fxm[7:0] \LDST_FXM + end + attribute \src "issuer_ls180.v:0.0-0.0" + case + assign { } { } + assign $2\cr_fxm[7:0] 8'11111111 + end + case + assign $1\cr_fxm[7:0] 8'00000000 + end + sync always + update \cr_fxm $0\cr_fxm[7:0] + end + connect \$1 $eq$issuer_ls180.v:116027$4528_Y + connect \$3 $eq$issuer_ls180.v:116028$4529_Y +end +attribute \src "issuer_ls180.v:116154.1-116397.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.dec2.dec_cr_out" +attribute \generator "nMigen" +module \dec_cr_out$207 + attribute \src "issuer_ls180.v:116311.3-116329.6" + wire width 3 $0\cr_bitfield[2:0] + attribute \src "issuer_ls180.v:116281.3-116299.6" + wire $0\cr_bitfield_ok[0:0] + attribute \src "issuer_ls180.v:116362.3-116396.6" + wire width 8 $0\cr_fxm[7:0] + attribute \src "issuer_ls180.v:116300.3-116310.6" + wire $0\cr_fxm_ok[0:0] + attribute \src "issuer_ls180.v:116155.7-116155.20" + wire $0\initial[0:0] + attribute \src "issuer_ls180.v:116330.3-116340.6" + wire $0\move_one[0:0] + attribute \src "issuer_ls180.v:116341.3-116361.6" + wire width 8 $0\ppick_i[7:0] + attribute \src "issuer_ls180.v:116311.3-116329.6" + wire width 3 $1\cr_bitfield[2:0] + attribute \src "issuer_ls180.v:116281.3-116299.6" + wire $1\cr_bitfield_ok[0:0] + attribute \src "issuer_ls180.v:116362.3-116396.6" + wire width 8 $1\cr_fxm[7:0] + attribute \src "issuer_ls180.v:116300.3-116310.6" + wire $1\cr_fxm_ok[0:0] + attribute \src "issuer_ls180.v:116330.3-116340.6" + wire $1\move_one[0:0] + attribute \src "issuer_ls180.v:116341.3-116361.6" + wire width 8 $1\ppick_i[7:0] + attribute \src "issuer_ls180.v:116362.3-116396.6" + wire width 8 $2\cr_fxm[7:0] + attribute \src "issuer_ls180.v:116341.3-116361.6" + wire width 8 $2\ppick_i[7:0] + attribute \src "issuer_ls180.v:116362.3-116396.6" + wire width 8 $3\cr_fxm[7:0] + attribute \src "issuer_ls180.v:116341.3-116361.6" + wire width 8 $3\ppick_i[7:0] + attribute \src "issuer_ls180.v:116362.3-116396.6" + wire width 8 $4\cr_fxm[7:0] + attribute \src "issuer_ls180.v:116274.17-116274.117" + wire $eq$issuer_ls180.v:116274$4537_Y + attribute \src "issuer_ls180.v:116275.17-116275.117" + wire $eq$issuer_ls180.v:116275$4538_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:579" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:579" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 8 input 8 \FXM + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 5 input 10 \XL_BT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:460" + wire width 3 input 9 \X_BF + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 3 output 6 \cr_bitfield + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 7 \cr_bitfield_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 8 output 4 \cr_fxm + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 5 \cr_fxm_ok + attribute \src "issuer_ls180.v:116155.7-116155.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:550" + wire width 32 input 11 \insn_in + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 7 input 3 \internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:577" + wire \move_one + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" + wire \ppick_en_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" + wire width 8 \ppick_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" + wire width 8 \ppick_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:548" + wire input 2 \rc_in + attribute \enum_base_type "CROutSel" + attribute \enum_value_000 "NONE" + attribute \enum_value_001 "CR0" + attribute \enum_value_010 "BF" + attribute \enum_value_011 "BT" + attribute \enum_value_100 "WHOLE_REG" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:549" + wire width 3 input 1 \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:579" + cell $eq $eq$issuer_ls180.v:116274$4537 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \internal_op + connect \B 7'0110000 + connect \Y $eq$issuer_ls180.v:116274$4537_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:579" + cell $eq $eq$issuer_ls180.v:116275$4538 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \internal_op + connect \B 7'0110000 + connect \Y $eq$issuer_ls180.v:116275$4538_Y + end + attribute \module_not_derived 1 + attribute \src "issuer_ls180.v:116276.15-116280.4" + cell \ppick$208 \ppick + connect \en_o \ppick_en_o + connect \i \ppick_i + connect \o \ppick_o + end + attribute \src "issuer_ls180.v:116155.7-116155.20" + process $proc$issuer_ls180.v:116155$4545 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "issuer_ls180.v:116281.3-116299.6" + process $proc$issuer_ls180.v:116281$4539 + assign { } { } + assign { } { } + assign $0\cr_bitfield_ok[0:0] $1\cr_bitfield_ok[0:0] + attribute \src "issuer_ls180.v:116282.5-116282.29" + switch \initial + attribute \src "issuer_ls180.v:116282.9-116282.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:563" + switch \sel_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 3'001 + assign { } { } + assign $1\cr_bitfield_ok[0:0] \rc_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 3'010 + assign { } { } + assign $1\cr_bitfield_ok[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 3'011 + assign { } { } + assign $1\cr_bitfield_ok[0:0] 1'1 + case + assign $1\cr_bitfield_ok[0:0] 1'0 + end + sync always + update \cr_bitfield_ok $0\cr_bitfield_ok[0:0] + end + attribute \src "issuer_ls180.v:116300.3-116310.6" + process $proc$issuer_ls180.v:116300$4540 + assign { } { } + assign { } { } + assign $0\cr_fxm_ok[0:0] $1\cr_fxm_ok[0:0] + attribute \src "issuer_ls180.v:116301.5-116301.29" + switch \initial + attribute \src "issuer_ls180.v:116301.9-116301.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:563" + switch \sel_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 3'100 + assign { } { } + assign $1\cr_fxm_ok[0:0] 1'1 + case + assign $1\cr_fxm_ok[0:0] 1'0 + end + sync always + update \cr_fxm_ok $0\cr_fxm_ok[0:0] + end + attribute \src "issuer_ls180.v:116311.3-116329.6" + process $proc$issuer_ls180.v:116311$4541 + assign { } { } + assign { } { } + assign $0\cr_bitfield[2:0] $1\cr_bitfield[2:0] + attribute \src "issuer_ls180.v:116312.5-116312.29" + switch \initial + attribute \src "issuer_ls180.v:116312.9-116312.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:563" + switch \sel_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 3'001 + assign { } { } + assign $1\cr_bitfield[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 3'010 + assign { } { } + assign $1\cr_bitfield[2:0] \X_BF + attribute \src "issuer_ls180.v:0.0-0.0" + case 3'011 + assign { } { } + assign $1\cr_bitfield[2:0] \XL_BT [4:2] + case + assign $1\cr_bitfield[2:0] 3'000 + end + sync always + update \cr_bitfield $0\cr_bitfield[2:0] + end + attribute \src "issuer_ls180.v:116330.3-116340.6" + process $proc$issuer_ls180.v:116330$4542 + assign { } { } + assign { } { } + assign $0\move_one[0:0] $1\move_one[0:0] + attribute \src "issuer_ls180.v:116331.5-116331.29" + switch \initial + attribute \src "issuer_ls180.v:116331.9-116331.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:563" + switch \sel_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 3'100 + assign { } { } + assign $1\move_one[0:0] \insn_in [20] + case + assign $1\move_one[0:0] 1'0 + end + sync always + update \move_one $0\move_one[0:0] + end + attribute \src "issuer_ls180.v:116341.3-116361.6" + process $proc$issuer_ls180.v:116341$4543 + assign { } { } + assign { } { } + assign $0\ppick_i[7:0] $1\ppick_i[7:0] + attribute \src "issuer_ls180.v:116342.5-116342.29" + switch \initial + attribute \src "issuer_ls180.v:116342.9-116342.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:563" + switch \sel_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 3'100 + assign { } { } + assign $1\ppick_i[7:0] $2\ppick_i[7:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:579" + switch \$1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\ppick_i[7:0] $3\ppick_i[7:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:580" + switch \move_one + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\ppick_i[7:0] \FXM + case + assign $3\ppick_i[7:0] 8'00000000 + end + case + assign $2\ppick_i[7:0] 8'00000000 + end + case + assign $1\ppick_i[7:0] 8'00000000 + end + sync always + update \ppick_i $0\ppick_i[7:0] + end + attribute \src "issuer_ls180.v:116362.3-116396.6" + process $proc$issuer_ls180.v:116362$4544 + assign { } { } + assign { } { } + assign $0\cr_fxm[7:0] $1\cr_fxm[7:0] + attribute \src "issuer_ls180.v:116363.5-116363.29" + switch \initial + attribute \src "issuer_ls180.v:116363.9-116363.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:563" + switch \sel_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 3'100 + assign { } { } + assign $1\cr_fxm[7:0] $2\cr_fxm[7:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:579" + switch \$3 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\cr_fxm[7:0] $3\cr_fxm[7:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:580" + switch \move_one + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\cr_fxm[7:0] $4\cr_fxm[7:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:583" + switch \ppick_en_o + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\cr_fxm[7:0] \ppick_o + attribute \src "issuer_ls180.v:0.0-0.0" + case + assign { } { } + assign $4\cr_fxm[7:0] 8'00000001 + end + attribute \src "issuer_ls180.v:0.0-0.0" + case + assign { } { } + assign $3\cr_fxm[7:0] \FXM + end + attribute \src "issuer_ls180.v:0.0-0.0" + case + assign { } { } + assign $2\cr_fxm[7:0] 8'11111111 + end + case + assign $1\cr_fxm[7:0] 8'00000000 + end + sync always + update \cr_fxm $0\cr_fxm[7:0] + end + connect \$1 $eq$issuer_ls180.v:116274$4537_Y + connect \$3 $eq$issuer_ls180.v:116275$4538_Y +end +attribute \src "issuer_ls180.v:116401.1-116878.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.dec2.dec_o" +attribute \generator "nMigen" +module \dec_o + attribute \src "issuer_ls180.v:116839.3-116877.6" + wire width 3 $0\fast_o[2:0] + attribute \src "issuer_ls180.v:116839.3-116877.6" + wire $0\fast_o_ok[0:0] + attribute \src "issuer_ls180.v:116402.7-116402.20" + wire $0\initial[0:0] + attribute \src "issuer_ls180.v:116765.3-116779.6" + wire width 5 $0\reg_o[4:0] + attribute \src "issuer_ls180.v:116780.3-116794.6" + wire $0\reg_o_ok[0:0] + attribute \src "issuer_ls180.v:116795.3-116805.6" + wire width 10 $0\spr[9:0] + attribute \src "issuer_ls180.v:116822.3-116838.6" + wire width 10 $0\spr_o[9:0] + attribute \src "issuer_ls180.v:116822.3-116838.6" + wire $0\spr_o_ok[0:0] + attribute \src "issuer_ls180.v:116806.3-116821.6" + wire width 10 $0\sprmap_spr_i[9:0] + attribute \src "issuer_ls180.v:116839.3-116877.6" + wire width 3 $1\fast_o[2:0] + attribute \src "issuer_ls180.v:116839.3-116877.6" + wire $1\fast_o_ok[0:0] + attribute \src "issuer_ls180.v:116765.3-116779.6" + wire width 5 $1\reg_o[4:0] + attribute \src "issuer_ls180.v:116780.3-116794.6" + wire $1\reg_o_ok[0:0] + attribute \src "issuer_ls180.v:116795.3-116805.6" + wire width 10 $1\spr[9:0] + attribute \src "issuer_ls180.v:116822.3-116838.6" + wire width 10 $1\spr_o[9:0] + attribute \src "issuer_ls180.v:116822.3-116838.6" + wire $1\spr_o_ok[0:0] + attribute \src "issuer_ls180.v:116806.3-116821.6" + wire width 10 $1\sprmap_spr_i[9:0] + attribute \src "issuer_ls180.v:116839.3-116877.6" + wire width 3 $2\fast_o[2:0] + attribute \src "issuer_ls180.v:116839.3-116877.6" + wire $2\fast_o_ok[0:0] + attribute \src "issuer_ls180.v:116822.3-116838.6" + wire width 10 $2\spr_o[9:0] + attribute \src "issuer_ls180.v:116822.3-116838.6" + wire $2\spr_o_ok[0:0] + attribute \src "issuer_ls180.v:116806.3-116821.6" + wire width 10 $2\sprmap_spr_i[9:0] + attribute \src "issuer_ls180.v:116839.3-116877.6" + wire width 3 $3\fast_o[2:0] + attribute \src "issuer_ls180.v:116839.3-116877.6" + wire $3\fast_o_ok[0:0] + attribute \src "issuer_ls180.v:116839.3-116877.6" + wire width 3 $4\fast_o[2:0] + attribute \src "issuer_ls180.v:116839.3-116877.6" + wire $4\fast_o_ok[0:0] + attribute \src "issuer_ls180.v:116754.17-116754.117" + wire $eq$issuer_ls180.v:116754$4546_Y + attribute \src "issuer_ls180.v:116755.17-116755.117" + wire $eq$issuer_ls180.v:116755$4547_Y + attribute \src "issuer_ls180.v:116756.17-116756.117" + wire $eq$issuer_ls180.v:116756$4548_Y + attribute \src "issuer_ls180.v:116757.17-116757.104" + wire $not$issuer_ls180.v:116757$4549_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:332" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:332" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:332" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:341" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 input 10 \BO + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 input 9 \RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 input 8 \RT + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 10 input 11 \SPR + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 3 output 6 \fast_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 7 \fast_o_ok + attribute \src "issuer_ls180.v:116402.7-116402.15" + wire \initial + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 7 input 12 \internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 5 output 2 \reg_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 3 \reg_o_ok + attribute \enum_base_type "OutSel" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "RT" + attribute \enum_value_10 "RA" + attribute \enum_value_11 "SPR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:308" + wire width 2 input 1 \sel_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:329" + wire width 10 \spr + attribute \enum_base_type "SPR" + attribute \enum_value_0000000001 "XER" + attribute \enum_value_0000000011 "DSCR" + attribute \enum_value_0000001000 "LR" + attribute \enum_value_0000001001 "CTR" + attribute \enum_value_0000001101 "AMR" + attribute \enum_value_0000010001 "DSCR_priv" + attribute \enum_value_0000010010 "DSISR" + attribute \enum_value_0000010011 "DAR" + attribute \enum_value_0000010110 "DEC" + attribute \enum_value_0000011010 "SRR0" + attribute \enum_value_0000011011 "SRR1" + attribute \enum_value_0000011100 "CFAR" + attribute \enum_value_0000011101 "AMR_priv" + attribute \enum_value_0000110000 "PIDR" + attribute \enum_value_0000111101 "IAMR" + attribute \enum_value_0010000000 "TFHAR" + attribute \enum_value_0010000001 "TFIAR" + attribute \enum_value_0010000010 "TEXASR" + attribute \enum_value_0010000011 "TEXASRU" + attribute \enum_value_0010001000 "CTRL" + attribute \enum_value_0010010000 "TIDR" + attribute \enum_value_0010011000 "CTRL_priv" + attribute \enum_value_0010011001 "FSCR" + attribute \enum_value_0010011101 "UAMOR" + attribute \enum_value_0010011110 "GSR" + attribute \enum_value_0010011111 "PSPB" + attribute \enum_value_0010110000 "DPDES" + attribute \enum_value_0010110100 "DAWR0" + attribute \enum_value_0010111010 "RPR" + attribute \enum_value_0010111011 "CIABR" + attribute \enum_value_0010111100 "DAWRX0" + attribute \enum_value_0010111110 "HFSCR" + attribute \enum_value_0100000000 "VRSAVE" + attribute \enum_value_0100000011 "SPRG3" + attribute \enum_value_0100001100 "TB" + attribute \enum_value_0100001101 "TBU" + attribute \enum_value_0100010000 "SPRG0_priv" + attribute \enum_value_0100010001 "SPRG1_priv" + attribute \enum_value_0100010010 "SPRG2_priv" + attribute \enum_value_0100010011 "SPRG3_priv" + attribute \enum_value_0100011011 "CIR" + attribute \enum_value_0100011100 "TBL" + attribute \enum_value_0100011101 "TBU_hypv" + attribute \enum_value_0100011110 "TBU40" + attribute \enum_value_0100011111 "PVR" + attribute \enum_value_0100110000 "HSPRG0" + attribute \enum_value_0100110001 "HSPRG1" + attribute \enum_value_0100110010 "HDSISR" + attribute \enum_value_0100110011 "HDAR" + attribute \enum_value_0100110100 "SPURR" + attribute \enum_value_0100110101 "PURR" + attribute \enum_value_0100110110 "HDEC" + attribute \enum_value_0100111001 "HRMOR" + attribute \enum_value_0100111010 "HSRR0" + attribute \enum_value_0100111011 "HSRR1" + attribute \enum_value_0100111110 "LPCR" + attribute \enum_value_0100111111 "LPIDR" + attribute \enum_value_0101010000 "HMER" + attribute \enum_value_0101010001 "HMEER" + attribute \enum_value_0101010010 "PCR" + attribute \enum_value_0101010011 "HEIR" + attribute \enum_value_0101011101 "AMOR" + attribute \enum_value_0110111110 "TIR" + attribute \enum_value_0111010000 "PTCR" + attribute \enum_value_1100000000 "SIER" + attribute \enum_value_1100000001 "MMCR2" + attribute \enum_value_1100000010 "MMCRA" + attribute \enum_value_1100000011 "PMC1" + attribute \enum_value_1100000100 "PMC2" + attribute \enum_value_1100000101 "PMC3" + attribute \enum_value_1100000110 "PMC4" + attribute \enum_value_1100000111 "PMC5" + attribute \enum_value_1100001000 "PMC6" + attribute \enum_value_1100001011 "MMCR0" + attribute \enum_value_1100001100 "SIAR" + attribute \enum_value_1100001101 "SDAR" + attribute \enum_value_1100001110 "MMCR1" + attribute \enum_value_1100010000 "SIER_priv" + attribute \enum_value_1100010001 "MMCR2_priv" + attribute \enum_value_1100010010 "MMCRA_priv" + attribute \enum_value_1100010011 "PMC1_priv" + attribute \enum_value_1100010100 "PMC2_priv" + attribute \enum_value_1100010101 "PMC3_priv" + attribute \enum_value_1100010110 "PMC4_priv" + attribute \enum_value_1100010111 "PMC5_priv" + attribute \enum_value_1100011000 "PMC6_priv" + attribute \enum_value_1100011011 "MMCR0_priv" + attribute \enum_value_1100011100 "SIAR_priv" + attribute \enum_value_1100011101 "SDAR_priv" + attribute \enum_value_1100011110 "MMCR1_priv" + attribute \enum_value_1100100000 "BESCRS" + attribute \enum_value_1100100001 "BESCRSU" + attribute \enum_value_1100100010 "BESCRR" + attribute \enum_value_1100100011 "BESCRRU" + attribute \enum_value_1100100100 "EBBHR" + attribute \enum_value_1100100101 "EBBRR" + attribute \enum_value_1100100110 "BESCR" + attribute \enum_value_1100101000 "reserved808" + attribute \enum_value_1100101001 "reserved809" + attribute \enum_value_1100101010 "reserved810" + attribute \enum_value_1100101011 "reserved811" + attribute \enum_value_1100101111 "TAR" + attribute \enum_value_1100110000 "ASDR" + attribute \enum_value_1100110111 "PSSCR" + attribute \enum_value_1101010000 "IC" + attribute \enum_value_1101010001 "VTB" + attribute \enum_value_1101010111 "PSSCR_hypv" + attribute \enum_value_1110000000 "PPR" + attribute \enum_value_1110000010 "PPR32" + attribute \enum_value_1111111111 "PIR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 10 output 4 \spr_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 5 \spr_o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 3 \sprmap_fast_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \sprmap_fast_o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:59" + wire width 10 \sprmap_spr_i + attribute \enum_base_type "SPR" + attribute \enum_value_0000000001 "XER" + attribute \enum_value_0000000011 "DSCR" + attribute \enum_value_0000001000 "LR" + attribute \enum_value_0000001001 "CTR" + attribute \enum_value_0000001101 "AMR" + attribute \enum_value_0000010001 "DSCR_priv" + attribute \enum_value_0000010010 "DSISR" + attribute \enum_value_0000010011 "DAR" + attribute \enum_value_0000010110 "DEC" + attribute \enum_value_0000011010 "SRR0" + attribute \enum_value_0000011011 "SRR1" + attribute \enum_value_0000011100 "CFAR" + attribute \enum_value_0000011101 "AMR_priv" + attribute \enum_value_0000110000 "PIDR" + attribute \enum_value_0000111101 "IAMR" + attribute \enum_value_0010000000 "TFHAR" + attribute \enum_value_0010000001 "TFIAR" + attribute \enum_value_0010000010 "TEXASR" + attribute \enum_value_0010000011 "TEXASRU" + attribute \enum_value_0010001000 "CTRL" + attribute \enum_value_0010010000 "TIDR" + attribute \enum_value_0010011000 "CTRL_priv" + attribute \enum_value_0010011001 "FSCR" + attribute \enum_value_0010011101 "UAMOR" + attribute \enum_value_0010011110 "GSR" + attribute \enum_value_0010011111 "PSPB" + attribute \enum_value_0010110000 "DPDES" + attribute \enum_value_0010110100 "DAWR0" + attribute \enum_value_0010111010 "RPR" + attribute \enum_value_0010111011 "CIABR" + attribute \enum_value_0010111100 "DAWRX0" + attribute \enum_value_0010111110 "HFSCR" + attribute \enum_value_0100000000 "VRSAVE" + attribute \enum_value_0100000011 "SPRG3" + attribute \enum_value_0100001100 "TB" + attribute \enum_value_0100001101 "TBU" + attribute \enum_value_0100010000 "SPRG0_priv" + attribute \enum_value_0100010001 "SPRG1_priv" + attribute \enum_value_0100010010 "SPRG2_priv" + attribute \enum_value_0100010011 "SPRG3_priv" + attribute \enum_value_0100011011 "CIR" + attribute \enum_value_0100011100 "TBL" + attribute \enum_value_0100011101 "TBU_hypv" + attribute \enum_value_0100011110 "TBU40" + attribute \enum_value_0100011111 "PVR" + attribute \enum_value_0100110000 "HSPRG0" + attribute \enum_value_0100110001 "HSPRG1" + attribute \enum_value_0100110010 "HDSISR" + attribute \enum_value_0100110011 "HDAR" + attribute \enum_value_0100110100 "SPURR" + attribute \enum_value_0100110101 "PURR" + attribute \enum_value_0100110110 "HDEC" + attribute \enum_value_0100111001 "HRMOR" + attribute \enum_value_0100111010 "HSRR0" + attribute \enum_value_0100111011 "HSRR1" + attribute \enum_value_0100111110 "LPCR" + attribute \enum_value_0100111111 "LPIDR" + attribute \enum_value_0101010000 "HMER" + attribute \enum_value_0101010001 "HMEER" + attribute \enum_value_0101010010 "PCR" + attribute \enum_value_0101010011 "HEIR" + attribute \enum_value_0101011101 "AMOR" + attribute \enum_value_0110111110 "TIR" + attribute \enum_value_0111010000 "PTCR" + attribute \enum_value_1100000000 "SIER" + attribute \enum_value_1100000001 "MMCR2" + attribute \enum_value_1100000010 "MMCRA" + attribute \enum_value_1100000011 "PMC1" + attribute \enum_value_1100000100 "PMC2" + attribute \enum_value_1100000101 "PMC3" + attribute \enum_value_1100000110 "PMC4" + attribute \enum_value_1100000111 "PMC5" + attribute \enum_value_1100001000 "PMC6" + attribute \enum_value_1100001011 "MMCR0" + attribute \enum_value_1100001100 "SIAR" + attribute \enum_value_1100001101 "SDAR" + attribute \enum_value_1100001110 "MMCR1" + attribute \enum_value_1100010000 "SIER_priv" + attribute \enum_value_1100010001 "MMCR2_priv" + attribute \enum_value_1100010010 "MMCRA_priv" + attribute \enum_value_1100010011 "PMC1_priv" + attribute \enum_value_1100010100 "PMC2_priv" + attribute \enum_value_1100010101 "PMC3_priv" + attribute \enum_value_1100010110 "PMC4_priv" + attribute \enum_value_1100010111 "PMC5_priv" + attribute \enum_value_1100011000 "PMC6_priv" + attribute \enum_value_1100011011 "MMCR0_priv" + attribute \enum_value_1100011100 "SIAR_priv" + attribute \enum_value_1100011101 "SDAR_priv" + attribute \enum_value_1100011110 "MMCR1_priv" + attribute \enum_value_1100100000 "BESCRS" + attribute \enum_value_1100100001 "BESCRSU" + attribute \enum_value_1100100010 "BESCRR" + attribute \enum_value_1100100011 "BESCRRU" + attribute \enum_value_1100100100 "EBBHR" + attribute \enum_value_1100100101 "EBBRR" + attribute \enum_value_1100100110 "BESCR" + attribute \enum_value_1100101000 "reserved808" + attribute \enum_value_1100101001 "reserved809" + attribute \enum_value_1100101010 "reserved810" + attribute \enum_value_1100101011 "reserved811" + attribute \enum_value_1100101111 "TAR" + attribute \enum_value_1100110000 "ASDR" + attribute \enum_value_1100110111 "PSSCR" + attribute \enum_value_1101010000 "IC" + attribute \enum_value_1101010001 "VTB" + attribute \enum_value_1101010111 "PSSCR_hypv" + attribute \enum_value_1110000000 "PPR" + attribute \enum_value_1110000010 "PPR32" + attribute \enum_value_1111111111 "PIR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 10 \sprmap_spr_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \sprmap_spr_o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:332" + cell $eq $eq$issuer_ls180.v:116754$4546 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \internal_op + connect \B 7'0110001 + connect \Y $eq$issuer_ls180.v:116754$4546_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:332" + cell $eq $eq$issuer_ls180.v:116755$4547 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \internal_op + connect \B 7'0110001 + connect \Y $eq$issuer_ls180.v:116755$4547_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:332" + cell $eq $eq$issuer_ls180.v:116756$4548 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \internal_op + connect \B 7'0110001 + connect \Y $eq$issuer_ls180.v:116756$4548_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:341" + cell $not $not$issuer_ls180.v:116757$4549 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \BO [2] + connect \Y $not$issuer_ls180.v:116757$4549_Y + end + attribute \module_not_derived 1 + attribute \src "issuer_ls180.v:116758.16-116764.4" + cell \sprmap$209 \sprmap + connect \fast_o \sprmap_fast_o + connect \fast_o_ok \sprmap_fast_o_ok + connect \spr_i \sprmap_spr_i + connect \spr_o \sprmap_spr_o + connect \spr_o_ok \sprmap_spr_o_ok + end + attribute \src "issuer_ls180.v:116402.7-116402.20" + process $proc$issuer_ls180.v:116402$4556 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "issuer_ls180.v:116765.3-116779.6" + process $proc$issuer_ls180.v:116765$4550 + assign { } { } + assign { } { } + assign $0\reg_o[4:0] $1\reg_o[4:0] + attribute \src "issuer_ls180.v:116766.5-116766.29" + switch \initial + attribute \src "issuer_ls180.v:116766.9-116766.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:321" + switch \sel_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\reg_o[4:0] \RT + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\reg_o[4:0] \RA + case + assign $1\reg_o[4:0] 5'00000 + end + sync always + update \reg_o $0\reg_o[4:0] + end + attribute \src "issuer_ls180.v:116780.3-116794.6" + process $proc$issuer_ls180.v:116780$4551 + assign { } { } + assign { } { } + assign $0\reg_o_ok[0:0] $1\reg_o_ok[0:0] + attribute \src "issuer_ls180.v:116781.5-116781.29" + switch \initial + attribute \src "issuer_ls180.v:116781.9-116781.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:321" + switch \sel_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\reg_o_ok[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\reg_o_ok[0:0] 1'1 + case + assign $1\reg_o_ok[0:0] 1'0 + end + sync always + update \reg_o_ok $0\reg_o_ok[0:0] + end + attribute \src "issuer_ls180.v:116795.3-116805.6" + process $proc$issuer_ls180.v:116795$4552 + assign { } { } + assign { } { } + assign $0\spr[9:0] $1\spr[9:0] + attribute \src "issuer_ls180.v:116796.5-116796.29" + switch \initial + attribute \src "issuer_ls180.v:116796.9-116796.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:321" + switch \sel_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'11 + assign { } { } + assign $1\spr[9:0] { \SPR [4:0] \SPR [9:5] } + case + assign $1\spr[9:0] 10'0000000000 + end + sync always + update \spr $0\spr[9:0] + end + attribute \src "issuer_ls180.v:116806.3-116821.6" + process $proc$issuer_ls180.v:116806$4553 + assign { } { } + assign { } { } + assign $0\sprmap_spr_i[9:0] $1\sprmap_spr_i[9:0] + attribute \src "issuer_ls180.v:116807.5-116807.29" + switch \initial + attribute \src "issuer_ls180.v:116807.9-116807.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:321" + switch \sel_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'11 + assign { } { } + assign $1\sprmap_spr_i[9:0] $2\sprmap_spr_i[9:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:332" + switch \$1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\sprmap_spr_i[9:0] \spr + case + assign $2\sprmap_spr_i[9:0] 10'0000000000 + end + case + assign $1\sprmap_spr_i[9:0] 10'0000000000 + end + sync always + update \sprmap_spr_i $0\sprmap_spr_i[9:0] + end + attribute \src "issuer_ls180.v:116822.3-116838.6" + process $proc$issuer_ls180.v:116822$4554 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\spr_o[9:0] $1\spr_o[9:0] + assign $0\spr_o_ok[0:0] $1\spr_o_ok[0:0] + attribute \src "issuer_ls180.v:116823.5-116823.29" + switch \initial + attribute \src "issuer_ls180.v:116823.9-116823.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:321" + switch \sel_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'11 + assign { } { } + assign { } { } + assign $1\spr_o[9:0] $2\spr_o[9:0] + assign $1\spr_o_ok[0:0] $2\spr_o_ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:332" + switch \$3 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $2\spr_o_ok[0:0] $2\spr_o[9:0] } { \sprmap_spr_o_ok \sprmap_spr_o } + case + assign $2\spr_o[9:0] 10'0000000000 + assign $2\spr_o_ok[0:0] 1'0 + end + case + assign $1\spr_o[9:0] 10'0000000000 + assign $1\spr_o_ok[0:0] 1'0 + end + sync always + update \spr_o $0\spr_o[9:0] + update \spr_o_ok $0\spr_o_ok[0:0] + end + attribute \src "issuer_ls180.v:116839.3-116877.6" + process $proc$issuer_ls180.v:116839$4555 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\fast_o[2:0] $3\fast_o[2:0] + assign $0\fast_o_ok[0:0] $3\fast_o_ok[0:0] + attribute \src "issuer_ls180.v:116840.5-116840.29" + switch \initial + attribute \src "issuer_ls180.v:116840.9-116840.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:321" + switch \sel_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'11 + assign { } { } + assign { } { } + assign $1\fast_o[2:0] $2\fast_o[2:0] + assign $1\fast_o_ok[0:0] $2\fast_o_ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:332" + switch \$5 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $2\fast_o_ok[0:0] $2\fast_o[2:0] } { \sprmap_fast_o_ok \sprmap_fast_o } + case + assign $2\fast_o[2:0] 3'000 + assign $2\fast_o_ok[0:0] 1'0 + end + case + assign $1\fast_o[2:0] 3'000 + assign $1\fast_o_ok[0:0] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:337" + switch \internal_op + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'0000111 , 7'0001000 + assign { } { } + assign { } { } + assign $3\fast_o[2:0] $4\fast_o[2:0] + assign $3\fast_o_ok[0:0] $4\fast_o_ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:341" + switch \$7 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign $4\fast_o[2:0] 3'000 + assign $4\fast_o_ok[0:0] 1'1 + case + assign $4\fast_o[2:0] $1\fast_o[2:0] + assign $4\fast_o_ok[0:0] $1\fast_o_ok[0:0] + end + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'1000110 + assign { } { } + assign { } { } + assign $3\fast_o[2:0] 3'011 + assign $3\fast_o_ok[0:0] 1'1 + case + assign $3\fast_o[2:0] $1\fast_o[2:0] + assign $3\fast_o_ok[0:0] $1\fast_o_ok[0:0] + end + sync always + update \fast_o $0\fast_o[2:0] + update \fast_o_ok $0\fast_o_ok[0:0] + end + connect \$1 $eq$issuer_ls180.v:116754$4546_Y + connect \$3 $eq$issuer_ls180.v:116755$4547_Y + connect \$5 $eq$issuer_ls180.v:116756$4548_Y + connect \$7 $not$issuer_ls180.v:116757$4549_Y +end +attribute \src "issuer_ls180.v:116882.1-117043.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.dec2.dec_o2" +attribute \generator "nMigen" +module \dec_o2 + attribute \src "issuer_ls180.v:117003.3-117022.6" + wire width 3 $0\fast_o[2:0] + attribute \src "issuer_ls180.v:117023.3-117042.6" + wire $0\fast_o_ok[0:0] + attribute \src "issuer_ls180.v:116883.7-116883.20" + wire $0\initial[0:0] + attribute \src "issuer_ls180.v:116989.3-117002.6" + wire width 5 $0\reg_o[4:0] + attribute \src "issuer_ls180.v:116989.3-117002.6" + wire $0\reg_o_ok[0:0] + attribute \src "issuer_ls180.v:117003.3-117022.6" + wire width 3 $1\fast_o[2:0] + attribute \src "issuer_ls180.v:117023.3-117042.6" + wire $1\fast_o_ok[0:0] + attribute \src "issuer_ls180.v:116989.3-117002.6" + wire width 5 $1\reg_o[4:0] + attribute \src "issuer_ls180.v:116989.3-117002.6" + wire $1\reg_o_ok[0:0] + attribute \src "issuer_ls180.v:117003.3-117022.6" + wire width 3 $2\fast_o[2:0] + attribute \src "issuer_ls180.v:117023.3-117042.6" + wire $2\fast_o_ok[0:0] + attribute \src "issuer_ls180.v:116987.17-116987.108" + wire $eq$issuer_ls180.v:116987$4557_Y + attribute \src "issuer_ls180.v:116988.17-116988.100" + wire width 6 $extend$issuer_ls180.v:116988$4558_Y + attribute \src "issuer_ls180.v:116988.17-116988.100" + wire width 6 $pos$issuer_ls180.v:116988$4559_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:373" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 6 \$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire width 5 input 7 \RA + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 3 output 4 \fast_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 5 \fast_o_ok + attribute \src "issuer_ls180.v:116883.7-116883.15" + wire \initial + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 7 input 8 \internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:363" + wire input 1 \lk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 5 output 2 \reg_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 3 \reg_o_ok + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 2 input 6 \upd + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:373" + cell $eq $eq$issuer_ls180.v:116987$4557 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \upd + connect \B 2'01 + connect \Y $eq$issuer_ls180.v:116987$4557_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + cell $pos $extend$issuer_ls180.v:116988$4558 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \Y_WIDTH 6 + connect \A \RA + connect \Y $extend$issuer_ls180.v:116988$4558_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + cell $pos $pos$issuer_ls180.v:116988$4559 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \Y_WIDTH 6 + connect \A $extend$issuer_ls180.v:116988$4558_Y + connect \Y $pos$issuer_ls180.v:116988$4559_Y + end + attribute \src "issuer_ls180.v:116883.7-116883.20" + process $proc$issuer_ls180.v:116883$4563 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "issuer_ls180.v:116989.3-117002.6" + process $proc$issuer_ls180.v:116989$4560 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\reg_o[4:0] $1\reg_o[4:0] + assign $0\reg_o_ok[0:0] $1\reg_o_ok[0:0] + attribute \src "issuer_ls180.v:116990.5-116990.29" + switch \initial + attribute \src "issuer_ls180.v:116990.9-116990.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:373" + switch \$1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign $1\reg_o[4:0] \$3 [4:0] + assign $1\reg_o_ok[0:0] 1'1 + case + assign $1\reg_o[4:0] 5'00000 + assign $1\reg_o_ok[0:0] 1'0 + end + sync always + update \reg_o $0\reg_o[4:0] + update \reg_o_ok $0\reg_o_ok[0:0] + end + attribute \src "issuer_ls180.v:117003.3-117022.6" + process $proc$issuer_ls180.v:117003$4561 + assign { } { } + assign { } { } + assign $0\fast_o[2:0] $1\fast_o[2:0] + attribute \src "issuer_ls180.v:117004.5-117004.29" + switch \initial + attribute \src "issuer_ls180.v:117004.9-117004.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:380" + switch \internal_op + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'0000111 , 7'0000110 , 7'0001000 + assign { } { } + assign $1\fast_o[2:0] $2\fast_o[2:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:384" + switch \lk + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\fast_o[2:0] 3'001 + case + assign $2\fast_o[2:0] 3'000 + end + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'1000110 + assign { } { } + assign $1\fast_o[2:0] 3'100 + case + assign $1\fast_o[2:0] 3'000 + end + sync always + update \fast_o $0\fast_o[2:0] + end + attribute \src "issuer_ls180.v:117023.3-117042.6" + process $proc$issuer_ls180.v:117023$4562 + assign { } { } + assign { } { } + assign $0\fast_o_ok[0:0] $1\fast_o_ok[0:0] + attribute \src "issuer_ls180.v:117024.5-117024.29" + switch \initial + attribute \src "issuer_ls180.v:117024.9-117024.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:380" + switch \internal_op + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'0000111 , 7'0000110 , 7'0001000 + assign { } { } + assign $1\fast_o_ok[0:0] $2\fast_o_ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:384" + switch \lk + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\fast_o_ok[0:0] 1'1 + case + assign $2\fast_o_ok[0:0] 1'0 + end + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'1000110 + assign { } { } + assign $1\fast_o_ok[0:0] 1'1 + case + assign $1\fast_o_ok[0:0] 1'0 + end + sync always + update \fast_o_ok $0\fast_o_ok[0:0] + end + connect \$1 $eq$issuer_ls180.v:116987$4557_Y + connect \$3 $pos$issuer_ls180.v:116988$4559_Y +end +attribute \src "issuer_ls180.v:117047.1-117181.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.dec_ALU.dec_oe" +attribute \generator "nMigen" +module \dec_oe + attribute \src "issuer_ls180.v:117048.7-117048.20" + wire $0\initial[0:0] + attribute \src "issuer_ls180.v:117139.3-117159.6" + wire $0\oe[0:0] + attribute \src "issuer_ls180.v:117160.3-117180.6" + wire $0\oe_ok[0:0] + attribute \src "issuer_ls180.v:117139.3-117159.6" + wire $1\oe[0:0] + attribute \src "issuer_ls180.v:117160.3-117180.6" + wire $1\oe_ok[0:0] + attribute \src "issuer_ls180.v:117139.3-117159.6" + wire $2\oe[0:0] + attribute \src "issuer_ls180.v:117160.3-117180.6" + wire $2\oe_ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire input 4 \ALU_OE + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 7 input 1 \ALU_internal_op + attribute \src "issuer_ls180.v:117048.7-117048.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 2 \oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 3 \oe_ok + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:441" + wire width 2 input 5 \sel_in + attribute \src "issuer_ls180.v:117048.7-117048.20" + process $proc$issuer_ls180.v:117048$4566 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "issuer_ls180.v:117139.3-117159.6" + process $proc$issuer_ls180.v:117139$4564 + assign { } { } + assign { } { } + assign $0\oe[0:0] $1\oe[0:0] + attribute \src "issuer_ls180.v:117140.5-117140.29" + switch \initial + attribute \src "issuer_ls180.v:117140.9-117140.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:450" + switch \ALU_internal_op + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'0110011 , 7'0110100 , 7'0011111 , 7'0001110 , 7'0111100 , 7'0111101 , 7'0111000 , 7'0100101 , 7'0100110 , 7'0111001 , 7'0111010 , 7'0100000 + assign $1\oe[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case + assign { } { } + assign $1\oe[0:0] $2\oe[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:467" + switch \sel_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'10 + assign { } { } + assign $2\oe[0:0] \ALU_OE + case + assign $2\oe[0:0] 1'0 + end + end + sync always + update \oe $0\oe[0:0] + end + attribute \src "issuer_ls180.v:117160.3-117180.6" + process $proc$issuer_ls180.v:117160$4565 + assign { } { } + assign { } { } + assign $0\oe_ok[0:0] $1\oe_ok[0:0] + attribute \src "issuer_ls180.v:117161.5-117161.29" + switch \initial + attribute \src "issuer_ls180.v:117161.9-117161.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:450" + switch \ALU_internal_op + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'0110011 , 7'0110100 , 7'0011111 , 7'0001110 , 7'0111100 , 7'0111101 , 7'0111000 , 7'0100101 , 7'0100110 , 7'0111001 , 7'0111010 , 7'0100000 + assign $1\oe_ok[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case + assign { } { } + assign $1\oe_ok[0:0] $2\oe_ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:467" + switch \sel_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'10 + assign { } { } + assign $2\oe_ok[0:0] 1'1 + case + assign $2\oe_ok[0:0] 1'0 + end + end + sync always + update \oe_ok $0\oe_ok[0:0] + end +end +attribute \src "issuer_ls180.v:117185.1-117317.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.dec_CR.dec_oe" +attribute \generator "nMigen" +module \dec_oe$139 + attribute \src "issuer_ls180.v:117186.7-117186.20" + wire $0\initial[0:0] + attribute \src "issuer_ls180.v:117275.3-117295.6" + wire $0\oe[0:0] + attribute \src "issuer_ls180.v:117296.3-117316.6" + wire $0\oe_ok[0:0] + attribute \src "issuer_ls180.v:117275.3-117295.6" + wire $1\oe[0:0] + attribute \src "issuer_ls180.v:117296.3-117316.6" + wire $1\oe_ok[0:0] + attribute \src "issuer_ls180.v:117275.3-117295.6" + wire $2\oe[0:0] + attribute \src "issuer_ls180.v:117296.3-117316.6" + wire $2\oe_ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire input 2 \CR_OE + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 7 input 1 \CR_internal_op + attribute \src "issuer_ls180.v:117186.7-117186.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \oe_ok + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:441" + wire width 2 input 3 \sel_in + attribute \src "issuer_ls180.v:117186.7-117186.20" + process $proc$issuer_ls180.v:117186$4569 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "issuer_ls180.v:117275.3-117295.6" + process $proc$issuer_ls180.v:117275$4567 + assign { } { } + assign { } { } + assign $0\oe[0:0] $1\oe[0:0] + attribute \src "issuer_ls180.v:117276.5-117276.29" + switch \initial + attribute \src "issuer_ls180.v:117276.9-117276.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:450" + switch \CR_internal_op + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'0110011 , 7'0110100 , 7'0011111 , 7'0001110 , 7'0111100 , 7'0111101 , 7'0111000 , 7'0100101 , 7'0100110 , 7'0111001 , 7'0111010 , 7'0100000 + assign $1\oe[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case + assign { } { } + assign $1\oe[0:0] $2\oe[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:467" + switch \sel_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'10 + assign { } { } + assign $2\oe[0:0] \CR_OE + case + assign $2\oe[0:0] 1'0 + end + end + sync always + update \oe $0\oe[0:0] + end + attribute \src "issuer_ls180.v:117296.3-117316.6" + process $proc$issuer_ls180.v:117296$4568 + assign { } { } + assign { } { } + assign $0\oe_ok[0:0] $1\oe_ok[0:0] + attribute \src "issuer_ls180.v:117297.5-117297.29" + switch \initial + attribute \src "issuer_ls180.v:117297.9-117297.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:450" + switch \CR_internal_op + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'0110011 , 7'0110100 , 7'0011111 , 7'0001110 , 7'0111100 , 7'0111101 , 7'0111000 , 7'0100101 , 7'0100110 , 7'0111001 , 7'0111010 , 7'0100000 + assign $1\oe_ok[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case + assign { } { } + assign $1\oe_ok[0:0] $2\oe_ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:467" + switch \sel_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'10 + assign { } { } + assign $2\oe_ok[0:0] 1'1 + case + assign $2\oe_ok[0:0] 1'0 + end + end + sync always + update \oe_ok $0\oe_ok[0:0] + end +end +attribute \src "issuer_ls180.v:117321.1-117453.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.dec_BRANCH.dec_oe" +attribute \generator "nMigen" +module \dec_oe$146 + attribute \src "issuer_ls180.v:117322.7-117322.20" + wire $0\initial[0:0] + attribute \src "issuer_ls180.v:117411.3-117431.6" + wire $0\oe[0:0] + attribute \src "issuer_ls180.v:117432.3-117452.6" + wire $0\oe_ok[0:0] + attribute \src "issuer_ls180.v:117411.3-117431.6" + wire $1\oe[0:0] + attribute \src "issuer_ls180.v:117432.3-117452.6" + wire $1\oe_ok[0:0] + attribute \src "issuer_ls180.v:117411.3-117431.6" + wire $2\oe[0:0] + attribute \src "issuer_ls180.v:117432.3-117452.6" + wire $2\oe_ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire input 2 \BRANCH_OE + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 7 input 1 \BRANCH_internal_op + attribute \src "issuer_ls180.v:117322.7-117322.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \oe_ok + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:441" + wire width 2 input 3 \sel_in + attribute \src "issuer_ls180.v:117322.7-117322.20" + process $proc$issuer_ls180.v:117322$4572 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "issuer_ls180.v:117411.3-117431.6" + process $proc$issuer_ls180.v:117411$4570 + assign { } { } + assign { } { } + assign $0\oe[0:0] $1\oe[0:0] + attribute \src "issuer_ls180.v:117412.5-117412.29" + switch \initial + attribute \src "issuer_ls180.v:117412.9-117412.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:450" + switch \BRANCH_internal_op + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'0110011 , 7'0110100 , 7'0011111 , 7'0001110 , 7'0111100 , 7'0111101 , 7'0111000 , 7'0100101 , 7'0100110 , 7'0111001 , 7'0111010 , 7'0100000 + assign $1\oe[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case + assign { } { } + assign $1\oe[0:0] $2\oe[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:467" + switch \sel_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'10 + assign { } { } + assign $2\oe[0:0] \BRANCH_OE + case + assign $2\oe[0:0] 1'0 + end + end + sync always + update \oe $0\oe[0:0] + end + attribute \src "issuer_ls180.v:117432.3-117452.6" + process $proc$issuer_ls180.v:117432$4571 + assign { } { } + assign { } { } + assign $0\oe_ok[0:0] $1\oe_ok[0:0] + attribute \src "issuer_ls180.v:117433.5-117433.29" + switch \initial + attribute \src "issuer_ls180.v:117433.9-117433.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:450" + switch \BRANCH_internal_op + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'0110011 , 7'0110100 , 7'0011111 , 7'0001110 , 7'0111100 , 7'0111101 , 7'0111000 , 7'0100101 , 7'0100110 , 7'0111001 , 7'0111010 , 7'0100000 + assign $1\oe_ok[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case + assign { } { } + assign $1\oe_ok[0:0] $2\oe_ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:467" + switch \sel_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'10 + assign { } { } + assign $2\oe_ok[0:0] 1'1 + case + assign $2\oe_ok[0:0] 1'0 + end + end + sync always + update \oe_ok $0\oe_ok[0:0] + end +end +attribute \src "issuer_ls180.v:117457.1-117591.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.dec_LOGICAL.dec_oe" +attribute \generator "nMigen" +module \dec_oe$154 + attribute \src "issuer_ls180.v:117458.7-117458.20" + wire $0\initial[0:0] + attribute \src "issuer_ls180.v:117549.3-117569.6" + wire $0\oe[0:0] + attribute \src "issuer_ls180.v:117570.3-117590.6" + wire $0\oe_ok[0:0] + attribute \src "issuer_ls180.v:117549.3-117569.6" + wire $1\oe[0:0] + attribute \src "issuer_ls180.v:117570.3-117590.6" + wire $1\oe_ok[0:0] + attribute \src "issuer_ls180.v:117549.3-117569.6" + wire $2\oe[0:0] + attribute \src "issuer_ls180.v:117570.3-117590.6" + wire $2\oe_ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire input 4 \LOGICAL_OE + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 7 input 1 \LOGICAL_internal_op + attribute \src "issuer_ls180.v:117458.7-117458.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 2 \oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 3 \oe_ok + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:441" + wire width 2 input 5 \sel_in + attribute \src "issuer_ls180.v:117458.7-117458.20" + process $proc$issuer_ls180.v:117458$4575 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "issuer_ls180.v:117549.3-117569.6" + process $proc$issuer_ls180.v:117549$4573 + assign { } { } + assign { } { } + assign $0\oe[0:0] $1\oe[0:0] + attribute \src "issuer_ls180.v:117550.5-117550.29" + switch \initial + attribute \src "issuer_ls180.v:117550.9-117550.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:450" + switch \LOGICAL_internal_op + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'0110011 , 7'0110100 , 7'0011111 , 7'0001110 , 7'0111100 , 7'0111101 , 7'0111000 , 7'0100101 , 7'0100110 , 7'0111001 , 7'0111010 , 7'0100000 + assign $1\oe[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case + assign { } { } + assign $1\oe[0:0] $2\oe[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:467" + switch \sel_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'10 + assign { } { } + assign $2\oe[0:0] \LOGICAL_OE + case + assign $2\oe[0:0] 1'0 + end + end + sync always + update \oe $0\oe[0:0] + end + attribute \src "issuer_ls180.v:117570.3-117590.6" + process $proc$issuer_ls180.v:117570$4574 + assign { } { } + assign { } { } + assign $0\oe_ok[0:0] $1\oe_ok[0:0] + attribute \src "issuer_ls180.v:117571.5-117571.29" + switch \initial + attribute \src "issuer_ls180.v:117571.9-117571.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:450" + switch \LOGICAL_internal_op + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'0110011 , 7'0110100 , 7'0011111 , 7'0001110 , 7'0111100 , 7'0111101 , 7'0111000 , 7'0100101 , 7'0100110 , 7'0111001 , 7'0111010 , 7'0100000 + assign $1\oe_ok[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case + assign { } { } + assign $1\oe_ok[0:0] $2\oe_ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:467" + switch \sel_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'10 + assign { } { } + assign $2\oe_ok[0:0] 1'1 + case + assign $2\oe_ok[0:0] 1'0 + end + end + sync always + update \oe_ok $0\oe_ok[0:0] + end +end +attribute \src "issuer_ls180.v:117595.1-117727.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.dec_SPR.dec_oe" +attribute \generator "nMigen" +module \dec_oe$163 + attribute \src "issuer_ls180.v:117596.7-117596.20" + wire $0\initial[0:0] + attribute \src "issuer_ls180.v:117685.3-117705.6" + wire $0\oe[0:0] + attribute \src "issuer_ls180.v:117706.3-117726.6" + wire $0\oe_ok[0:0] + attribute \src "issuer_ls180.v:117685.3-117705.6" + wire $1\oe[0:0] + attribute \src "issuer_ls180.v:117706.3-117726.6" + wire $1\oe_ok[0:0] + attribute \src "issuer_ls180.v:117685.3-117705.6" + wire $2\oe[0:0] + attribute \src "issuer_ls180.v:117706.3-117726.6" + wire $2\oe_ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire input 2 \SPR_OE + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 7 input 1 \SPR_internal_op + attribute \src "issuer_ls180.v:117596.7-117596.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \oe_ok + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:441" + wire width 2 input 3 \sel_in + attribute \src "issuer_ls180.v:117596.7-117596.20" + process $proc$issuer_ls180.v:117596$4578 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "issuer_ls180.v:117685.3-117705.6" + process $proc$issuer_ls180.v:117685$4576 + assign { } { } + assign { } { } + assign $0\oe[0:0] $1\oe[0:0] + attribute \src "issuer_ls180.v:117686.5-117686.29" + switch \initial + attribute \src "issuer_ls180.v:117686.9-117686.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:450" + switch \SPR_internal_op + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'0110011 , 7'0110100 , 7'0011111 , 7'0001110 , 7'0111100 , 7'0111101 , 7'0111000 , 7'0100101 , 7'0100110 , 7'0111001 , 7'0111010 , 7'0100000 + assign $1\oe[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case + assign { } { } + assign $1\oe[0:0] $2\oe[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:467" + switch \sel_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'10 + assign { } { } + assign $2\oe[0:0] \SPR_OE + case + assign $2\oe[0:0] 1'0 + end + end + sync always + update \oe $0\oe[0:0] + end + attribute \src "issuer_ls180.v:117706.3-117726.6" + process $proc$issuer_ls180.v:117706$4577 + assign { } { } + assign { } { } + assign $0\oe_ok[0:0] $1\oe_ok[0:0] + attribute \src "issuer_ls180.v:117707.5-117707.29" + switch \initial + attribute \src "issuer_ls180.v:117707.9-117707.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:450" + switch \SPR_internal_op + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'0110011 , 7'0110100 , 7'0011111 , 7'0001110 , 7'0111100 , 7'0111101 , 7'0111000 , 7'0100101 , 7'0100110 , 7'0111001 , 7'0111010 , 7'0100000 + assign $1\oe_ok[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case + assign { } { } + assign $1\oe_ok[0:0] $2\oe_ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:467" + switch \sel_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'10 + assign { } { } + assign $2\oe_ok[0:0] 1'1 + case + assign $2\oe_ok[0:0] 1'0 + end + end + sync always + update \oe_ok $0\oe_ok[0:0] + end +end +attribute \src "issuer_ls180.v:117731.1-117865.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.dec_DIV.dec_oe" +attribute \generator "nMigen" +module \dec_oe$170 + attribute \src "issuer_ls180.v:117732.7-117732.20" + wire $0\initial[0:0] + attribute \src "issuer_ls180.v:117823.3-117843.6" + wire $0\oe[0:0] + attribute \src "issuer_ls180.v:117844.3-117864.6" + wire $0\oe_ok[0:0] + attribute \src "issuer_ls180.v:117823.3-117843.6" + wire $1\oe[0:0] + attribute \src "issuer_ls180.v:117844.3-117864.6" + wire $1\oe_ok[0:0] + attribute \src "issuer_ls180.v:117823.3-117843.6" + wire $2\oe[0:0] + attribute \src "issuer_ls180.v:117844.3-117864.6" + wire $2\oe_ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire input 4 \DIV_OE + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 7 input 1 \DIV_internal_op + attribute \src "issuer_ls180.v:117732.7-117732.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 2 \oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 3 \oe_ok + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:441" + wire width 2 input 5 \sel_in + attribute \src "issuer_ls180.v:117732.7-117732.20" + process $proc$issuer_ls180.v:117732$4581 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "issuer_ls180.v:117823.3-117843.6" + process $proc$issuer_ls180.v:117823$4579 + assign { } { } + assign { } { } + assign $0\oe[0:0] $1\oe[0:0] + attribute \src "issuer_ls180.v:117824.5-117824.29" + switch \initial + attribute \src "issuer_ls180.v:117824.9-117824.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:450" + switch \DIV_internal_op + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'0110011 , 7'0110100 , 7'0011111 , 7'0001110 , 7'0111100 , 7'0111101 , 7'0111000 , 7'0100101 , 7'0100110 , 7'0111001 , 7'0111010 , 7'0100000 + assign $1\oe[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case + assign { } { } + assign $1\oe[0:0] $2\oe[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:467" + switch \sel_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'10 + assign { } { } + assign $2\oe[0:0] \DIV_OE + case + assign $2\oe[0:0] 1'0 + end + end + sync always + update \oe $0\oe[0:0] + end + attribute \src "issuer_ls180.v:117844.3-117864.6" + process $proc$issuer_ls180.v:117844$4580 + assign { } { } + assign { } { } + assign $0\oe_ok[0:0] $1\oe_ok[0:0] + attribute \src "issuer_ls180.v:117845.5-117845.29" + switch \initial + attribute \src "issuer_ls180.v:117845.9-117845.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:450" + switch \DIV_internal_op + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'0110011 , 7'0110100 , 7'0011111 , 7'0001110 , 7'0111100 , 7'0111101 , 7'0111000 , 7'0100101 , 7'0100110 , 7'0111001 , 7'0111010 , 7'0100000 + assign $1\oe_ok[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case + assign { } { } + assign $1\oe_ok[0:0] $2\oe_ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:467" + switch \sel_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'10 + assign { } { } + assign $2\oe_ok[0:0] 1'1 + case + assign $2\oe_ok[0:0] 1'0 + end + end + sync always + update \oe_ok $0\oe_ok[0:0] + end +end +attribute \src "issuer_ls180.v:117869.1-118003.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.dec_MUL.dec_oe" +attribute \generator "nMigen" +module \dec_oe$179 + attribute \src "issuer_ls180.v:117870.7-117870.20" + wire $0\initial[0:0] + attribute \src "issuer_ls180.v:117961.3-117981.6" + wire $0\oe[0:0] + attribute \src "issuer_ls180.v:117982.3-118002.6" + wire $0\oe_ok[0:0] + attribute \src "issuer_ls180.v:117961.3-117981.6" + wire $1\oe[0:0] + attribute \src "issuer_ls180.v:117982.3-118002.6" + wire $1\oe_ok[0:0] + attribute \src "issuer_ls180.v:117961.3-117981.6" + wire $2\oe[0:0] + attribute \src "issuer_ls180.v:117982.3-118002.6" + wire $2\oe_ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire input 4 \MUL_OE + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 7 input 1 \MUL_internal_op + attribute \src "issuer_ls180.v:117870.7-117870.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 2 \oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 3 \oe_ok + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:441" + wire width 2 input 5 \sel_in + attribute \src "issuer_ls180.v:117870.7-117870.20" + process $proc$issuer_ls180.v:117870$4584 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "issuer_ls180.v:117961.3-117981.6" + process $proc$issuer_ls180.v:117961$4582 + assign { } { } + assign { } { } + assign $0\oe[0:0] $1\oe[0:0] + attribute \src "issuer_ls180.v:117962.5-117962.29" + switch \initial + attribute \src "issuer_ls180.v:117962.9-117962.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:450" + switch \MUL_internal_op + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'0110011 , 7'0110100 , 7'0011111 , 7'0001110 , 7'0111100 , 7'0111101 , 7'0111000 , 7'0100101 , 7'0100110 , 7'0111001 , 7'0111010 , 7'0100000 + assign $1\oe[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case + assign { } { } + assign $1\oe[0:0] $2\oe[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:467" + switch \sel_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'10 + assign { } { } + assign $2\oe[0:0] \MUL_OE + case + assign $2\oe[0:0] 1'0 + end + end + sync always + update \oe $0\oe[0:0] + end + attribute \src "issuer_ls180.v:117982.3-118002.6" + process $proc$issuer_ls180.v:117982$4583 + assign { } { } + assign { } { } + assign $0\oe_ok[0:0] $1\oe_ok[0:0] + attribute \src "issuer_ls180.v:117983.5-117983.29" + switch \initial + attribute \src "issuer_ls180.v:117983.9-117983.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:450" + switch \MUL_internal_op + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'0110011 , 7'0110100 , 7'0011111 , 7'0001110 , 7'0111100 , 7'0111101 , 7'0111000 , 7'0100101 , 7'0100110 , 7'0111001 , 7'0111010 , 7'0100000 + assign $1\oe_ok[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case + assign { } { } + assign $1\oe_ok[0:0] $2\oe_ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:467" + switch \sel_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'10 + assign { } { } + assign $2\oe_ok[0:0] 1'1 + case + assign $2\oe_ok[0:0] 1'0 + end + end + sync always + update \oe_ok $0\oe_ok[0:0] + end +end +attribute \src "issuer_ls180.v:118007.1-118141.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.dec_SHIFT_ROT.dec_oe" +attribute \generator "nMigen" +module \dec_oe$187 + attribute \src "issuer_ls180.v:118008.7-118008.20" + wire $0\initial[0:0] + attribute \src "issuer_ls180.v:118099.3-118119.6" + wire $0\oe[0:0] + attribute \src "issuer_ls180.v:118120.3-118140.6" + wire $0\oe_ok[0:0] + attribute \src "issuer_ls180.v:118099.3-118119.6" + wire $1\oe[0:0] + attribute \src "issuer_ls180.v:118120.3-118140.6" + wire $1\oe_ok[0:0] + attribute \src "issuer_ls180.v:118099.3-118119.6" + wire $2\oe[0:0] + attribute \src "issuer_ls180.v:118120.3-118140.6" + wire $2\oe_ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire input 4 \SHIFT_ROT_OE + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 7 input 1 \SHIFT_ROT_internal_op + attribute \src "issuer_ls180.v:118008.7-118008.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 2 \oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 3 \oe_ok + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:441" + wire width 2 input 5 \sel_in + attribute \src "issuer_ls180.v:118008.7-118008.20" + process $proc$issuer_ls180.v:118008$4587 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "issuer_ls180.v:118099.3-118119.6" + process $proc$issuer_ls180.v:118099$4585 + assign { } { } + assign { } { } + assign $0\oe[0:0] $1\oe[0:0] + attribute \src "issuer_ls180.v:118100.5-118100.29" + switch \initial + attribute \src "issuer_ls180.v:118100.9-118100.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:450" + switch \SHIFT_ROT_internal_op + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'0110011 , 7'0110100 , 7'0011111 , 7'0001110 , 7'0111100 , 7'0111101 , 7'0111000 , 7'0100101 , 7'0100110 , 7'0111001 , 7'0111010 , 7'0100000 + assign $1\oe[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case + assign { } { } + assign $1\oe[0:0] $2\oe[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:467" + switch \sel_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'10 + assign { } { } + assign $2\oe[0:0] \SHIFT_ROT_OE + case + assign $2\oe[0:0] 1'0 + end + end + sync always + update \oe $0\oe[0:0] + end + attribute \src "issuer_ls180.v:118120.3-118140.6" + process $proc$issuer_ls180.v:118120$4586 + assign { } { } + assign { } { } + assign $0\oe_ok[0:0] $1\oe_ok[0:0] + attribute \src "issuer_ls180.v:118121.5-118121.29" + switch \initial + attribute \src "issuer_ls180.v:118121.9-118121.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:450" + switch \SHIFT_ROT_internal_op + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'0110011 , 7'0110100 , 7'0011111 , 7'0001110 , 7'0111100 , 7'0111101 , 7'0111000 , 7'0100101 , 7'0100110 , 7'0111001 , 7'0111010 , 7'0100000 + assign $1\oe_ok[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case + assign { } { } + assign $1\oe_ok[0:0] $2\oe_ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:467" + switch \sel_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'10 + assign { } { } + assign $2\oe_ok[0:0] 1'1 + case + assign $2\oe_ok[0:0] 1'0 + end + end + sync always + update \oe_ok $0\oe_ok[0:0] + end +end +attribute \src "issuer_ls180.v:118145.1-118279.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.dec_LDST.dec_oe" +attribute \generator "nMigen" +module \dec_oe$195 + attribute \src "issuer_ls180.v:118146.7-118146.20" + wire $0\initial[0:0] + attribute \src "issuer_ls180.v:118237.3-118257.6" + wire $0\oe[0:0] + attribute \src "issuer_ls180.v:118258.3-118278.6" + wire $0\oe_ok[0:0] + attribute \src "issuer_ls180.v:118237.3-118257.6" + wire $1\oe[0:0] + attribute \src "issuer_ls180.v:118258.3-118278.6" + wire $1\oe_ok[0:0] + attribute \src "issuer_ls180.v:118237.3-118257.6" + wire $2\oe[0:0] + attribute \src "issuer_ls180.v:118258.3-118278.6" + wire $2\oe_ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire input 4 \LDST_OE + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 7 input 1 \LDST_internal_op + attribute \src "issuer_ls180.v:118146.7-118146.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 2 \oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 3 \oe_ok + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:441" + wire width 2 input 5 \sel_in + attribute \src "issuer_ls180.v:118146.7-118146.20" + process $proc$issuer_ls180.v:118146$4590 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "issuer_ls180.v:118237.3-118257.6" + process $proc$issuer_ls180.v:118237$4588 + assign { } { } + assign { } { } + assign $0\oe[0:0] $1\oe[0:0] + attribute \src "issuer_ls180.v:118238.5-118238.29" + switch \initial + attribute \src "issuer_ls180.v:118238.9-118238.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:450" + switch \LDST_internal_op + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'0110011 , 7'0110100 , 7'0011111 , 7'0001110 , 7'0111100 , 7'0111101 , 7'0111000 , 7'0100101 , 7'0100110 , 7'0111001 , 7'0111010 , 7'0100000 + assign $1\oe[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case + assign { } { } + assign $1\oe[0:0] $2\oe[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:467" + switch \sel_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'10 + assign { } { } + assign $2\oe[0:0] \LDST_OE + case + assign $2\oe[0:0] 1'0 + end + end + sync always + update \oe $0\oe[0:0] + end + attribute \src "issuer_ls180.v:118258.3-118278.6" + process $proc$issuer_ls180.v:118258$4589 + assign { } { } + assign { } { } + assign $0\oe_ok[0:0] $1\oe_ok[0:0] + attribute \src "issuer_ls180.v:118259.5-118259.29" + switch \initial + attribute \src "issuer_ls180.v:118259.9-118259.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:450" + switch \LDST_internal_op + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'0110011 , 7'0110100 , 7'0011111 , 7'0001110 , 7'0111100 , 7'0111101 , 7'0111000 , 7'0100101 , 7'0100110 , 7'0111001 , 7'0111010 , 7'0100000 + assign $1\oe_ok[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case + assign { } { } + assign $1\oe_ok[0:0] $2\oe_ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:467" + switch \sel_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'10 + assign { } { } + assign $2\oe_ok[0:0] 1'1 + case + assign $2\oe_ok[0:0] 1'0 + end + end + sync always + update \oe_ok $0\oe_ok[0:0] + end +end +attribute \src "issuer_ls180.v:118283.1-118417.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.dec2.dec_oe" +attribute \generator "nMigen" +module \dec_oe$204 + attribute \src "issuer_ls180.v:118284.7-118284.20" + wire $0\initial[0:0] + attribute \src "issuer_ls180.v:118375.3-118395.6" + wire $0\oe[0:0] + attribute \src "issuer_ls180.v:118396.3-118416.6" + wire $0\oe_ok[0:0] + attribute \src "issuer_ls180.v:118375.3-118395.6" + wire $1\oe[0:0] + attribute \src "issuer_ls180.v:118396.3-118416.6" + wire $1\oe_ok[0:0] + attribute \src "issuer_ls180.v:118375.3-118395.6" + wire $2\oe[0:0] + attribute \src "issuer_ls180.v:118396.3-118416.6" + wire $2\oe_ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire input 4 \OE + attribute \src "issuer_ls180.v:118284.7-118284.15" + wire \initial + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:168" + wire width 7 input 1 \internal_op + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 2 \oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 3 \oe_ok + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:441" + wire width 2 input 5 \sel_in + attribute \src "issuer_ls180.v:118284.7-118284.20" + process $proc$issuer_ls180.v:118284$4593 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "issuer_ls180.v:118375.3-118395.6" + process $proc$issuer_ls180.v:118375$4591 + assign { } { } + assign { } { } + assign $0\oe[0:0] $1\oe[0:0] + attribute \src "issuer_ls180.v:118376.5-118376.29" + switch \initial + attribute \src "issuer_ls180.v:118376.9-118376.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:450" + switch \internal_op + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'0110011 , 7'0110100 , 7'0011111 , 7'0001110 , 7'0111100 , 7'0111101 , 7'0111000 , 7'0100101 , 7'0100110 , 7'0111001 , 7'0111010 , 7'0100000 + assign $1\oe[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case + assign { } { } + assign $1\oe[0:0] $2\oe[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:467" + switch \sel_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'10 + assign { } { } + assign $2\oe[0:0] \OE + case + assign $2\oe[0:0] 1'0 + end + end + sync always + update \oe $0\oe[0:0] + end + attribute \src "issuer_ls180.v:118396.3-118416.6" + process $proc$issuer_ls180.v:118396$4592 + assign { } { } + assign { } { } + assign $0\oe_ok[0:0] $1\oe_ok[0:0] + attribute \src "issuer_ls180.v:118397.5-118397.29" + switch \initial + attribute \src "issuer_ls180.v:118397.9-118397.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:450" + switch \internal_op + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'0110011 , 7'0110100 , 7'0011111 , 7'0001110 , 7'0111100 , 7'0111101 , 7'0111000 , 7'0100101 , 7'0100110 , 7'0111001 , 7'0111010 , 7'0100000 + assign $1\oe_ok[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case + assign { } { } + assign $1\oe_ok[0:0] $2\oe_ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:467" + switch \sel_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'10 + assign { } { } + assign $2\oe_ok[0:0] 1'1 + case + assign $2\oe_ok[0:0] 1'0 + end + end + sync always + update \oe_ok $0\oe_ok[0:0] + end +end +attribute \src "issuer_ls180.v:118421.1-118475.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.dec_ALU.dec_rc" +attribute \generator "nMigen" +module \dec_rc + attribute \src "issuer_ls180.v:118422.7-118422.20" + wire $0\initial[0:0] + attribute \src "issuer_ls180.v:118437.3-118455.6" + wire $0\rc[0:0] + attribute \src "issuer_ls180.v:118456.3-118474.6" + wire $0\rc_ok[0:0] + attribute \src "issuer_ls180.v:118437.3-118455.6" + wire $1\rc[0:0] + attribute \src "issuer_ls180.v:118456.3-118474.6" + wire $1\rc_ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire input 3 \ALU_Rc + attribute \src "issuer_ls180.v:118422.7-118422.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 1 \rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 2 \rc_ok + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:404" + wire width 2 input 4 \sel_in + attribute \src "issuer_ls180.v:118422.7-118422.20" + process $proc$issuer_ls180.v:118422$4596 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "issuer_ls180.v:118437.3-118455.6" + process $proc$issuer_ls180.v:118437$4594 + assign { } { } + assign { } { } + assign $0\rc[0:0] $1\rc[0:0] + attribute \src "issuer_ls180.v:118438.5-118438.29" + switch \initial + attribute \src "issuer_ls180.v:118438.9-118438.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:413" + switch \sel_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\rc[0:0] \ALU_Rc + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\rc[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\rc[0:0] 1'0 + case + assign $1\rc[0:0] 1'0 + end + sync always + update \rc $0\rc[0:0] + end + attribute \src "issuer_ls180.v:118456.3-118474.6" + process $proc$issuer_ls180.v:118456$4595 + assign { } { } + assign { } { } + assign $0\rc_ok[0:0] $1\rc_ok[0:0] + attribute \src "issuer_ls180.v:118457.5-118457.29" + switch \initial + attribute \src "issuer_ls180.v:118457.9-118457.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:413" + switch \sel_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\rc_ok[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\rc_ok[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\rc_ok[0:0] 1'1 + case + assign $1\rc_ok[0:0] 1'0 + end + sync always + update \rc_ok $0\rc_ok[0:0] + end +end +attribute \src "issuer_ls180.v:118479.1-118532.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.dec_CR.dec_rc" +attribute \generator "nMigen" +module \dec_rc$138 + attribute \src "issuer_ls180.v:118480.7-118480.20" + wire $0\initial[0:0] + attribute \src "issuer_ls180.v:118494.3-118512.6" + wire $0\rc[0:0] + attribute \src "issuer_ls180.v:118513.3-118531.6" + wire $0\rc_ok[0:0] + attribute \src "issuer_ls180.v:118494.3-118512.6" + wire $1\rc[0:0] + attribute \src "issuer_ls180.v:118513.3-118531.6" + wire $1\rc_ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire input 2 \CR_Rc + attribute \src "issuer_ls180.v:118480.7-118480.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 1 \rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \rc_ok + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:404" + wire width 2 input 3 \sel_in + attribute \src "issuer_ls180.v:118480.7-118480.20" + process $proc$issuer_ls180.v:118480$4599 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "issuer_ls180.v:118494.3-118512.6" + process $proc$issuer_ls180.v:118494$4597 + assign { } { } + assign { } { } + assign $0\rc[0:0] $1\rc[0:0] + attribute \src "issuer_ls180.v:118495.5-118495.29" + switch \initial + attribute \src "issuer_ls180.v:118495.9-118495.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:413" + switch \sel_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\rc[0:0] \CR_Rc + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\rc[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\rc[0:0] 1'0 + case + assign $1\rc[0:0] 1'0 + end + sync always + update \rc $0\rc[0:0] + end + attribute \src "issuer_ls180.v:118513.3-118531.6" + process $proc$issuer_ls180.v:118513$4598 + assign { } { } + assign { } { } + assign $0\rc_ok[0:0] $1\rc_ok[0:0] + attribute \src "issuer_ls180.v:118514.5-118514.29" + switch \initial + attribute \src "issuer_ls180.v:118514.9-118514.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:413" + switch \sel_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\rc_ok[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\rc_ok[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\rc_ok[0:0] 1'1 + case + assign $1\rc_ok[0:0] 1'0 + end + sync always + update \rc_ok $0\rc_ok[0:0] + end +end +attribute \src "issuer_ls180.v:118536.1-118589.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.dec_BRANCH.dec_rc" +attribute \generator "nMigen" +module \dec_rc$145 + attribute \src "issuer_ls180.v:118537.7-118537.20" + wire $0\initial[0:0] + attribute \src "issuer_ls180.v:118551.3-118569.6" + wire $0\rc[0:0] + attribute \src "issuer_ls180.v:118570.3-118588.6" + wire $0\rc_ok[0:0] + attribute \src "issuer_ls180.v:118551.3-118569.6" + wire $1\rc[0:0] + attribute \src "issuer_ls180.v:118570.3-118588.6" + wire $1\rc_ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire input 2 \BRANCH_Rc + attribute \src "issuer_ls180.v:118537.7-118537.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 1 \rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \rc_ok + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:404" + wire width 2 input 3 \sel_in + attribute \src "issuer_ls180.v:118537.7-118537.20" + process $proc$issuer_ls180.v:118537$4602 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "issuer_ls180.v:118551.3-118569.6" + process $proc$issuer_ls180.v:118551$4600 + assign { } { } + assign { } { } + assign $0\rc[0:0] $1\rc[0:0] + attribute \src "issuer_ls180.v:118552.5-118552.29" + switch \initial + attribute \src "issuer_ls180.v:118552.9-118552.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:413" + switch \sel_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\rc[0:0] \BRANCH_Rc + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\rc[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\rc[0:0] 1'0 + case + assign $1\rc[0:0] 1'0 + end + sync always + update \rc $0\rc[0:0] + end + attribute \src "issuer_ls180.v:118570.3-118588.6" + process $proc$issuer_ls180.v:118570$4601 + assign { } { } + assign { } { } + assign $0\rc_ok[0:0] $1\rc_ok[0:0] + attribute \src "issuer_ls180.v:118571.5-118571.29" + switch \initial + attribute \src "issuer_ls180.v:118571.9-118571.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:413" + switch \sel_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\rc_ok[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\rc_ok[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\rc_ok[0:0] 1'1 + case + assign $1\rc_ok[0:0] 1'0 + end + sync always + update \rc_ok $0\rc_ok[0:0] + end +end +attribute \src "issuer_ls180.v:118593.1-118647.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.dec_LOGICAL.dec_rc" +attribute \generator "nMigen" +module \dec_rc$153 + attribute \src "issuer_ls180.v:118594.7-118594.20" + wire $0\initial[0:0] + attribute \src "issuer_ls180.v:118609.3-118627.6" + wire $0\rc[0:0] + attribute \src "issuer_ls180.v:118628.3-118646.6" + wire $0\rc_ok[0:0] + attribute \src "issuer_ls180.v:118609.3-118627.6" + wire $1\rc[0:0] + attribute \src "issuer_ls180.v:118628.3-118646.6" + wire $1\rc_ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire input 3 \LOGICAL_Rc + attribute \src "issuer_ls180.v:118594.7-118594.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 1 \rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 2 \rc_ok + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:404" + wire width 2 input 4 \sel_in + attribute \src "issuer_ls180.v:118594.7-118594.20" + process $proc$issuer_ls180.v:118594$4605 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "issuer_ls180.v:118609.3-118627.6" + process $proc$issuer_ls180.v:118609$4603 + assign { } { } + assign { } { } + assign $0\rc[0:0] $1\rc[0:0] + attribute \src "issuer_ls180.v:118610.5-118610.29" + switch \initial + attribute \src "issuer_ls180.v:118610.9-118610.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:413" + switch \sel_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\rc[0:0] \LOGICAL_Rc + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\rc[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\rc[0:0] 1'0 + case + assign $1\rc[0:0] 1'0 + end + sync always + update \rc $0\rc[0:0] + end + attribute \src "issuer_ls180.v:118628.3-118646.6" + process $proc$issuer_ls180.v:118628$4604 + assign { } { } + assign { } { } + assign $0\rc_ok[0:0] $1\rc_ok[0:0] + attribute \src "issuer_ls180.v:118629.5-118629.29" + switch \initial + attribute \src "issuer_ls180.v:118629.9-118629.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:413" + switch \sel_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\rc_ok[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\rc_ok[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\rc_ok[0:0] 1'1 + case + assign $1\rc_ok[0:0] 1'0 + end + sync always + update \rc_ok $0\rc_ok[0:0] + end +end +attribute \src "issuer_ls180.v:118651.1-118704.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.dec_SPR.dec_rc" +attribute \generator "nMigen" +module \dec_rc$162 + attribute \src "issuer_ls180.v:118652.7-118652.20" + wire $0\initial[0:0] + attribute \src "issuer_ls180.v:118666.3-118684.6" + wire $0\rc[0:0] + attribute \src "issuer_ls180.v:118685.3-118703.6" + wire $0\rc_ok[0:0] + attribute \src "issuer_ls180.v:118666.3-118684.6" + wire $1\rc[0:0] + attribute \src "issuer_ls180.v:118685.3-118703.6" + wire $1\rc_ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire input 2 \SPR_Rc + attribute \src "issuer_ls180.v:118652.7-118652.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 1 \rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \rc_ok + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:404" + wire width 2 input 3 \sel_in + attribute \src "issuer_ls180.v:118652.7-118652.20" + process $proc$issuer_ls180.v:118652$4608 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "issuer_ls180.v:118666.3-118684.6" + process $proc$issuer_ls180.v:118666$4606 + assign { } { } + assign { } { } + assign $0\rc[0:0] $1\rc[0:0] + attribute \src "issuer_ls180.v:118667.5-118667.29" + switch \initial + attribute \src "issuer_ls180.v:118667.9-118667.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:413" + switch \sel_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\rc[0:0] \SPR_Rc + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\rc[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\rc[0:0] 1'0 + case + assign $1\rc[0:0] 1'0 + end + sync always + update \rc $0\rc[0:0] + end + attribute \src "issuer_ls180.v:118685.3-118703.6" + process $proc$issuer_ls180.v:118685$4607 + assign { } { } + assign { } { } + assign $0\rc_ok[0:0] $1\rc_ok[0:0] + attribute \src "issuer_ls180.v:118686.5-118686.29" + switch \initial + attribute \src "issuer_ls180.v:118686.9-118686.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:413" + switch \sel_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\rc_ok[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\rc_ok[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\rc_ok[0:0] 1'1 + case + assign $1\rc_ok[0:0] 1'0 + end + sync always + update \rc_ok $0\rc_ok[0:0] + end +end +attribute \src "issuer_ls180.v:118708.1-118762.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.dec_DIV.dec_rc" +attribute \generator "nMigen" +module \dec_rc$169 + attribute \src "issuer_ls180.v:118709.7-118709.20" + wire $0\initial[0:0] + attribute \src "issuer_ls180.v:118724.3-118742.6" + wire $0\rc[0:0] + attribute \src "issuer_ls180.v:118743.3-118761.6" + wire $0\rc_ok[0:0] + attribute \src "issuer_ls180.v:118724.3-118742.6" + wire $1\rc[0:0] + attribute \src "issuer_ls180.v:118743.3-118761.6" + wire $1\rc_ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire input 3 \DIV_Rc + attribute \src "issuer_ls180.v:118709.7-118709.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 1 \rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 2 \rc_ok + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:404" + wire width 2 input 4 \sel_in + attribute \src "issuer_ls180.v:118709.7-118709.20" + process $proc$issuer_ls180.v:118709$4611 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "issuer_ls180.v:118724.3-118742.6" + process $proc$issuer_ls180.v:118724$4609 + assign { } { } + assign { } { } + assign $0\rc[0:0] $1\rc[0:0] + attribute \src "issuer_ls180.v:118725.5-118725.29" + switch \initial + attribute \src "issuer_ls180.v:118725.9-118725.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:413" + switch \sel_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\rc[0:0] \DIV_Rc + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\rc[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\rc[0:0] 1'0 + case + assign $1\rc[0:0] 1'0 + end + sync always + update \rc $0\rc[0:0] + end + attribute \src "issuer_ls180.v:118743.3-118761.6" + process $proc$issuer_ls180.v:118743$4610 + assign { } { } + assign { } { } + assign $0\rc_ok[0:0] $1\rc_ok[0:0] + attribute \src "issuer_ls180.v:118744.5-118744.29" + switch \initial + attribute \src "issuer_ls180.v:118744.9-118744.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:413" + switch \sel_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\rc_ok[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\rc_ok[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\rc_ok[0:0] 1'1 + case + assign $1\rc_ok[0:0] 1'0 + end + sync always + update \rc_ok $0\rc_ok[0:0] + end +end +attribute \src "issuer_ls180.v:118766.1-118820.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.dec_MUL.dec_rc" +attribute \generator "nMigen" +module \dec_rc$178 + attribute \src "issuer_ls180.v:118767.7-118767.20" + wire $0\initial[0:0] + attribute \src "issuer_ls180.v:118782.3-118800.6" + wire $0\rc[0:0] + attribute \src "issuer_ls180.v:118801.3-118819.6" + wire $0\rc_ok[0:0] + attribute \src "issuer_ls180.v:118782.3-118800.6" + wire $1\rc[0:0] + attribute \src "issuer_ls180.v:118801.3-118819.6" + wire $1\rc_ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire input 3 \MUL_Rc + attribute \src "issuer_ls180.v:118767.7-118767.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 1 \rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 2 \rc_ok + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:404" + wire width 2 input 4 \sel_in + attribute \src "issuer_ls180.v:118767.7-118767.20" + process $proc$issuer_ls180.v:118767$4614 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "issuer_ls180.v:118782.3-118800.6" + process $proc$issuer_ls180.v:118782$4612 + assign { } { } + assign { } { } + assign $0\rc[0:0] $1\rc[0:0] + attribute \src "issuer_ls180.v:118783.5-118783.29" + switch \initial + attribute \src "issuer_ls180.v:118783.9-118783.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:413" + switch \sel_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\rc[0:0] \MUL_Rc + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\rc[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\rc[0:0] 1'0 + case + assign $1\rc[0:0] 1'0 + end + sync always + update \rc $0\rc[0:0] + end + attribute \src "issuer_ls180.v:118801.3-118819.6" + process $proc$issuer_ls180.v:118801$4613 + assign { } { } + assign { } { } + assign $0\rc_ok[0:0] $1\rc_ok[0:0] + attribute \src "issuer_ls180.v:118802.5-118802.29" + switch \initial + attribute \src "issuer_ls180.v:118802.9-118802.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:413" + switch \sel_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\rc_ok[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\rc_ok[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\rc_ok[0:0] 1'1 + case + assign $1\rc_ok[0:0] 1'0 + end + sync always + update \rc_ok $0\rc_ok[0:0] + end +end +attribute \src "issuer_ls180.v:118824.1-118878.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.dec_SHIFT_ROT.dec_rc" +attribute \generator "nMigen" +module \dec_rc$186 + attribute \src "issuer_ls180.v:118825.7-118825.20" + wire $0\initial[0:0] + attribute \src "issuer_ls180.v:118840.3-118858.6" + wire $0\rc[0:0] + attribute \src "issuer_ls180.v:118859.3-118877.6" + wire $0\rc_ok[0:0] + attribute \src "issuer_ls180.v:118840.3-118858.6" + wire $1\rc[0:0] + attribute \src "issuer_ls180.v:118859.3-118877.6" + wire $1\rc_ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire input 3 \SHIFT_ROT_Rc + attribute \src "issuer_ls180.v:118825.7-118825.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 1 \rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 2 \rc_ok + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:404" + wire width 2 input 4 \sel_in + attribute \src "issuer_ls180.v:118825.7-118825.20" + process $proc$issuer_ls180.v:118825$4617 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "issuer_ls180.v:118840.3-118858.6" + process $proc$issuer_ls180.v:118840$4615 + assign { } { } + assign { } { } + assign $0\rc[0:0] $1\rc[0:0] + attribute \src "issuer_ls180.v:118841.5-118841.29" + switch \initial + attribute \src "issuer_ls180.v:118841.9-118841.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:413" + switch \sel_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\rc[0:0] \SHIFT_ROT_Rc + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\rc[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\rc[0:0] 1'0 + case + assign $1\rc[0:0] 1'0 + end + sync always + update \rc $0\rc[0:0] + end + attribute \src "issuer_ls180.v:118859.3-118877.6" + process $proc$issuer_ls180.v:118859$4616 + assign { } { } + assign { } { } + assign $0\rc_ok[0:0] $1\rc_ok[0:0] + attribute \src "issuer_ls180.v:118860.5-118860.29" + switch \initial + attribute \src "issuer_ls180.v:118860.9-118860.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:413" + switch \sel_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\rc_ok[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\rc_ok[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\rc_ok[0:0] 1'1 + case + assign $1\rc_ok[0:0] 1'0 + end + sync always + update \rc_ok $0\rc_ok[0:0] + end +end +attribute \src "issuer_ls180.v:118882.1-118936.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.dec_LDST.dec_rc" +attribute \generator "nMigen" +module \dec_rc$194 + attribute \src "issuer_ls180.v:118883.7-118883.20" + wire $0\initial[0:0] + attribute \src "issuer_ls180.v:118898.3-118916.6" + wire $0\rc[0:0] + attribute \src "issuer_ls180.v:118917.3-118935.6" + wire $0\rc_ok[0:0] + attribute \src "issuer_ls180.v:118898.3-118916.6" + wire $1\rc[0:0] + attribute \src "issuer_ls180.v:118917.3-118935.6" + wire $1\rc_ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire input 3 \LDST_Rc + attribute \src "issuer_ls180.v:118883.7-118883.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 1 \rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 2 \rc_ok + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:404" + wire width 2 input 4 \sel_in + attribute \src "issuer_ls180.v:118883.7-118883.20" + process $proc$issuer_ls180.v:118883$4620 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "issuer_ls180.v:118898.3-118916.6" + process $proc$issuer_ls180.v:118898$4618 + assign { } { } + assign { } { } + assign $0\rc[0:0] $1\rc[0:0] + attribute \src "issuer_ls180.v:118899.5-118899.29" + switch \initial + attribute \src "issuer_ls180.v:118899.9-118899.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:413" + switch \sel_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\rc[0:0] \LDST_Rc + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\rc[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\rc[0:0] 1'0 + case + assign $1\rc[0:0] 1'0 + end + sync always + update \rc $0\rc[0:0] + end + attribute \src "issuer_ls180.v:118917.3-118935.6" + process $proc$issuer_ls180.v:118917$4619 + assign { } { } + assign { } { } + assign $0\rc_ok[0:0] $1\rc_ok[0:0] + attribute \src "issuer_ls180.v:118918.5-118918.29" + switch \initial + attribute \src "issuer_ls180.v:118918.9-118918.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:413" + switch \sel_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\rc_ok[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\rc_ok[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\rc_ok[0:0] 1'1 + case + assign $1\rc_ok[0:0] 1'0 + end + sync always + update \rc_ok $0\rc_ok[0:0] + end +end +attribute \src "issuer_ls180.v:118940.1-118994.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.dec2.dec_rc" +attribute \generator "nMigen" +module \dec_rc$203 + attribute \src "issuer_ls180.v:118941.7-118941.20" + wire $0\initial[0:0] + attribute \src "issuer_ls180.v:118956.3-118974.6" + wire $0\rc[0:0] + attribute \src "issuer_ls180.v:118975.3-118993.6" + wire $0\rc_ok[0:0] + attribute \src "issuer_ls180.v:118956.3-118974.6" + wire $1\rc[0:0] + attribute \src "issuer_ls180.v:118975.3-118993.6" + wire $1\rc_ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:447" + wire input 3 \Rc + attribute \src "issuer_ls180.v:118941.7-118941.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 1 \rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 2 \rc_ok + attribute \enum_base_type "RC" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "RC" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:404" + wire width 2 input 4 \sel_in + attribute \src "issuer_ls180.v:118941.7-118941.20" + process $proc$issuer_ls180.v:118941$4623 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "issuer_ls180.v:118956.3-118974.6" + process $proc$issuer_ls180.v:118956$4621 + assign { } { } + assign { } { } + assign $0\rc[0:0] $1\rc[0:0] + attribute \src "issuer_ls180.v:118957.5-118957.29" + switch \initial + attribute \src "issuer_ls180.v:118957.9-118957.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:413" + switch \sel_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\rc[0:0] \Rc + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\rc[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\rc[0:0] 1'0 + case + assign $1\rc[0:0] 1'0 + end + sync always + update \rc $0\rc[0:0] + end + attribute \src "issuer_ls180.v:118975.3-118993.6" + process $proc$issuer_ls180.v:118975$4622 + assign { } { } + assign { } { } + assign $0\rc_ok[0:0] $1\rc_ok[0:0] + attribute \src "issuer_ls180.v:118976.5-118976.29" + switch \initial + attribute \src "issuer_ls180.v:118976.9-118976.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:413" + switch \sel_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\rc_ok[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\rc_ok[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\rc_ok[0:0] 1'1 + case + assign $1\rc_ok[0:0] 1'0 + end + sync always + update \rc_ok $0\rc_ok[0:0] + end +end +attribute \src "issuer_ls180.v:118998.1-120236.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.fus.div0" +attribute \generator "nMigen" +module \div0 + attribute \src "issuer_ls180.v:119793.3-119794.25" + wire $0\all_rd_dly[0:0] + attribute \src "issuer_ls180.v:119980.3-120018.6" + wire width 4 $0\alu_div0_logical_op__data_len$next[3:0]$4763 + attribute \src "issuer_ls180.v:119765.3-119766.75" + wire width 4 $0\alu_div0_logical_op__data_len[3:0] + attribute \src "issuer_ls180.v:119980.3-120018.6" + wire width 12 $0\alu_div0_logical_op__fn_unit$next[11:0]$4764 + attribute \src "issuer_ls180.v:119735.3-119736.73" + wire width 12 $0\alu_div0_logical_op__fn_unit[11:0] + attribute \src "issuer_ls180.v:119980.3-120018.6" + wire width 64 $0\alu_div0_logical_op__imm_data__data$next[63:0]$4765 + attribute \src "issuer_ls180.v:119737.3-119738.87" + wire width 64 $0\alu_div0_logical_op__imm_data__data[63:0] + attribute \src "issuer_ls180.v:119980.3-120018.6" + wire $0\alu_div0_logical_op__imm_data__ok$next[0:0]$4766 + attribute \src "issuer_ls180.v:119739.3-119740.83" + wire $0\alu_div0_logical_op__imm_data__ok[0:0] + attribute \src "issuer_ls180.v:119980.3-120018.6" + wire width 2 $0\alu_div0_logical_op__input_carry$next[1:0]$4767 + attribute \src "issuer_ls180.v:119753.3-119754.81" + wire width 2 $0\alu_div0_logical_op__input_carry[1:0] + attribute \src "issuer_ls180.v:119980.3-120018.6" + wire width 32 $0\alu_div0_logical_op__insn$next[31:0]$4768 + attribute \src "issuer_ls180.v:119767.3-119768.67" + wire width 32 $0\alu_div0_logical_op__insn[31:0] + attribute \src "issuer_ls180.v:119980.3-120018.6" + wire width 7 $0\alu_div0_logical_op__insn_type$next[6:0]$4769 + attribute \src "issuer_ls180.v:119733.3-119734.77" + wire width 7 $0\alu_div0_logical_op__insn_type[6:0] + attribute \src "issuer_ls180.v:119980.3-120018.6" + wire $0\alu_div0_logical_op__invert_in$next[0:0]$4770 + attribute \src "issuer_ls180.v:119749.3-119750.77" + wire $0\alu_div0_logical_op__invert_in[0:0] + attribute \src "issuer_ls180.v:119980.3-120018.6" + wire $0\alu_div0_logical_op__invert_out$next[0:0]$4771 + attribute \src "issuer_ls180.v:119755.3-119756.79" + wire $0\alu_div0_logical_op__invert_out[0:0] + attribute \src "issuer_ls180.v:119980.3-120018.6" + wire $0\alu_div0_logical_op__is_32bit$next[0:0]$4772 + attribute \src "issuer_ls180.v:119761.3-119762.75" + wire $0\alu_div0_logical_op__is_32bit[0:0] + attribute \src "issuer_ls180.v:119980.3-120018.6" + wire $0\alu_div0_logical_op__is_signed$next[0:0]$4773 + attribute \src "issuer_ls180.v:119763.3-119764.77" + wire $0\alu_div0_logical_op__is_signed[0:0] + attribute \src "issuer_ls180.v:119980.3-120018.6" + wire $0\alu_div0_logical_op__oe__oe$next[0:0]$4774 + attribute \src "issuer_ls180.v:119745.3-119746.71" + wire $0\alu_div0_logical_op__oe__oe[0:0] + attribute \src "issuer_ls180.v:119980.3-120018.6" + wire $0\alu_div0_logical_op__oe__ok$next[0:0]$4775 + attribute \src "issuer_ls180.v:119747.3-119748.71" + wire $0\alu_div0_logical_op__oe__ok[0:0] + attribute \src "issuer_ls180.v:119980.3-120018.6" + wire $0\alu_div0_logical_op__output_carry$next[0:0]$4776 + attribute \src "issuer_ls180.v:119759.3-119760.83" + wire $0\alu_div0_logical_op__output_carry[0:0] + attribute \src "issuer_ls180.v:119980.3-120018.6" + wire $0\alu_div0_logical_op__rc__ok$next[0:0]$4777 + attribute \src "issuer_ls180.v:119743.3-119744.71" + wire $0\alu_div0_logical_op__rc__ok[0:0] + attribute \src "issuer_ls180.v:119980.3-120018.6" + wire $0\alu_div0_logical_op__rc__rc$next[0:0]$4778 + attribute \src "issuer_ls180.v:119741.3-119742.71" + wire $0\alu_div0_logical_op__rc__rc[0:0] + attribute \src "issuer_ls180.v:119980.3-120018.6" + wire $0\alu_div0_logical_op__write_cr0$next[0:0]$4779 + attribute \src "issuer_ls180.v:119757.3-119758.77" + wire $0\alu_div0_logical_op__write_cr0[0:0] + attribute \src "issuer_ls180.v:119980.3-120018.6" + wire $0\alu_div0_logical_op__zero_a$next[0:0]$4780 + attribute \src "issuer_ls180.v:119751.3-119752.71" + wire $0\alu_div0_logical_op__zero_a[0:0] + attribute \src "issuer_ls180.v:119791.3-119792.40" + wire $0\alu_done_dly[0:0] + attribute \src "issuer_ls180.v:120146.3-120154.6" + wire $0\alu_l_r_alu$next[0:0]$4850 + attribute \src "issuer_ls180.v:119707.3-119708.39" + wire $0\alu_l_r_alu[0:0] + attribute \src "issuer_ls180.v:120137.3-120145.6" + wire $0\alui_l_r_alui$next[0:0]$4847 + attribute \src "issuer_ls180.v:119709.3-119710.43" + wire $0\alui_l_r_alui[0:0] + attribute \src "issuer_ls180.v:120019.3-120040.6" + wire width 64 $0\data_r0__o$next[63:0]$4806 + attribute \src "issuer_ls180.v:119729.3-119730.37" + wire width 64 $0\data_r0__o[63:0] + attribute \src "issuer_ls180.v:120019.3-120040.6" + wire $0\data_r0__o_ok$next[0:0]$4807 + attribute \src "issuer_ls180.v:119731.3-119732.43" + wire $0\data_r0__o_ok[0:0] + attribute \src "issuer_ls180.v:120041.3-120062.6" + wire width 4 $0\data_r1__cr_a$next[3:0]$4814 + attribute \src "issuer_ls180.v:119725.3-119726.43" + wire width 4 $0\data_r1__cr_a[3:0] + attribute \src "issuer_ls180.v:120041.3-120062.6" + wire $0\data_r1__cr_a_ok$next[0:0]$4815 + attribute \src "issuer_ls180.v:119727.3-119728.49" + wire $0\data_r1__cr_a_ok[0:0] + attribute \src "issuer_ls180.v:120063.3-120084.6" + wire width 2 $0\data_r2__xer_ov$next[1:0]$4822 + attribute \src "issuer_ls180.v:119721.3-119722.47" + wire width 2 $0\data_r2__xer_ov[1:0] + attribute \src "issuer_ls180.v:120063.3-120084.6" + wire $0\data_r2__xer_ov_ok$next[0:0]$4823 + attribute \src "issuer_ls180.v:119723.3-119724.53" + wire $0\data_r2__xer_ov_ok[0:0] + attribute \src "issuer_ls180.v:120085.3-120106.6" + wire $0\data_r3__xer_so$next[0:0]$4830 + attribute \src "issuer_ls180.v:119717.3-119718.47" + wire $0\data_r3__xer_so[0:0] + attribute \src "issuer_ls180.v:120085.3-120106.6" + wire $0\data_r3__xer_so_ok$next[0:0]$4831 + attribute \src "issuer_ls180.v:119719.3-119720.53" + wire $0\data_r3__xer_so_ok[0:0] + attribute \src "issuer_ls180.v:120155.3-120164.6" + wire width 64 $0\dest1_o[63:0] + attribute \src "issuer_ls180.v:120165.3-120174.6" + wire width 4 $0\dest2_o[3:0] + attribute \src "issuer_ls180.v:120175.3-120184.6" + wire width 2 $0\dest3_o[1:0] + attribute \src "issuer_ls180.v:120185.3-120194.6" + wire $0\dest4_o[0:0] + attribute \src "issuer_ls180.v:118999.7-118999.20" + wire $0\initial[0:0] + attribute \src "issuer_ls180.v:119935.3-119943.6" + wire $0\opc_l_r_opc$next[0:0]$4748 + attribute \src "issuer_ls180.v:119777.3-119778.39" + wire $0\opc_l_r_opc[0:0] + attribute \src "issuer_ls180.v:119926.3-119934.6" + wire $0\opc_l_s_opc$next[0:0]$4745 + attribute \src "issuer_ls180.v:119779.3-119780.39" + wire $0\opc_l_s_opc[0:0] + attribute \src "issuer_ls180.v:120195.3-120203.6" + wire width 4 $0\prev_wr_go$next[3:0]$4857 + attribute \src "issuer_ls180.v:119789.3-119790.37" + wire width 4 $0\prev_wr_go[3:0] + attribute \src "issuer_ls180.v:119880.3-119889.6" + wire $0\req_done[0:0] + attribute \src "issuer_ls180.v:119971.3-119979.6" + wire width 4 $0\req_l_r_req$next[3:0]$4760 + attribute \src "issuer_ls180.v:119769.3-119770.39" + wire width 4 $0\req_l_r_req[3:0] + attribute \src "issuer_ls180.v:119962.3-119970.6" + wire width 4 $0\req_l_s_req$next[3:0]$4757 + attribute \src "issuer_ls180.v:119771.3-119772.39" + wire width 4 $0\req_l_s_req[3:0] + attribute \src "issuer_ls180.v:119899.3-119907.6" + wire $0\rok_l_r_rdok$next[0:0]$4736 + attribute \src "issuer_ls180.v:119785.3-119786.41" + wire $0\rok_l_r_rdok[0:0] + attribute \src "issuer_ls180.v:119890.3-119898.6" + wire $0\rok_l_s_rdok$next[0:0]$4733 + attribute \src "issuer_ls180.v:119787.3-119788.41" + wire $0\rok_l_s_rdok[0:0] + attribute \src "issuer_ls180.v:119917.3-119925.6" + wire $0\rst_l_r_rst$next[0:0]$4742 + attribute \src "issuer_ls180.v:119781.3-119782.39" + wire $0\rst_l_r_rst[0:0] + attribute \src "issuer_ls180.v:119908.3-119916.6" + wire $0\rst_l_s_rst$next[0:0]$4739 + attribute \src "issuer_ls180.v:119783.3-119784.39" + wire $0\rst_l_s_rst[0:0] + attribute \src "issuer_ls180.v:119953.3-119961.6" + wire width 3 $0\src_l_r_src$next[2:0]$4754 + attribute \src "issuer_ls180.v:119773.3-119774.39" + wire width 3 $0\src_l_r_src[2:0] + attribute \src "issuer_ls180.v:119944.3-119952.6" + wire width 3 $0\src_l_s_src$next[2:0]$4751 + attribute \src "issuer_ls180.v:119775.3-119776.39" + wire width 3 $0\src_l_s_src[2:0] + attribute \src "issuer_ls180.v:120107.3-120116.6" + wire width 64 $0\src_r0$next[63:0]$4838 + attribute \src "issuer_ls180.v:119715.3-119716.29" + wire width 64 $0\src_r0[63:0] + attribute \src "issuer_ls180.v:120117.3-120126.6" + wire width 64 $0\src_r1$next[63:0]$4841 + attribute \src "issuer_ls180.v:119713.3-119714.29" + wire width 64 $0\src_r1[63:0] + attribute \src "issuer_ls180.v:120127.3-120136.6" + wire $0\src_r2$next[0:0]$4844 + attribute \src "issuer_ls180.v:119711.3-119712.29" + wire $0\src_r2[0:0] + attribute \src "issuer_ls180.v:119129.7-119129.24" + wire $1\all_rd_dly[0:0] + attribute \src "issuer_ls180.v:119980.3-120018.6" + wire width 4 $1\alu_div0_logical_op__data_len$next[3:0]$4781 + attribute \src "issuer_ls180.v:119139.13-119139.49" + wire width 4 $1\alu_div0_logical_op__data_len[3:0] + attribute \src "issuer_ls180.v:119980.3-120018.6" + wire width 12 $1\alu_div0_logical_op__fn_unit$next[11:0]$4782 + attribute \src "issuer_ls180.v:119156.14-119156.52" + wire width 12 $1\alu_div0_logical_op__fn_unit[11:0] + attribute \src "issuer_ls180.v:119980.3-120018.6" + wire width 64 $1\alu_div0_logical_op__imm_data__data$next[63:0]$4783 + attribute \src "issuer_ls180.v:119160.14-119160.72" + wire width 64 $1\alu_div0_logical_op__imm_data__data[63:0] + attribute \src "issuer_ls180.v:119980.3-120018.6" + wire $1\alu_div0_logical_op__imm_data__ok$next[0:0]$4784 + attribute \src "issuer_ls180.v:119164.7-119164.47" + wire $1\alu_div0_logical_op__imm_data__ok[0:0] + attribute \src "issuer_ls180.v:119980.3-120018.6" + wire width 2 $1\alu_div0_logical_op__input_carry$next[1:0]$4785 + attribute \src "issuer_ls180.v:119172.13-119172.52" + wire width 2 $1\alu_div0_logical_op__input_carry[1:0] + attribute \src "issuer_ls180.v:119980.3-120018.6" + wire width 32 $1\alu_div0_logical_op__insn$next[31:0]$4786 + attribute \src "issuer_ls180.v:119176.14-119176.47" + wire width 32 $1\alu_div0_logical_op__insn[31:0] + attribute \src "issuer_ls180.v:119980.3-120018.6" + wire width 7 $1\alu_div0_logical_op__insn_type$next[6:0]$4787 + attribute \src "issuer_ls180.v:119254.13-119254.51" + wire width 7 $1\alu_div0_logical_op__insn_type[6:0] + attribute \src "issuer_ls180.v:119980.3-120018.6" + wire $1\alu_div0_logical_op__invert_in$next[0:0]$4788 + attribute \src "issuer_ls180.v:119258.7-119258.44" + wire $1\alu_div0_logical_op__invert_in[0:0] + attribute \src "issuer_ls180.v:119980.3-120018.6" + wire $1\alu_div0_logical_op__invert_out$next[0:0]$4789 + attribute \src "issuer_ls180.v:119262.7-119262.45" + wire $1\alu_div0_logical_op__invert_out[0:0] + attribute \src "issuer_ls180.v:119980.3-120018.6" + wire $1\alu_div0_logical_op__is_32bit$next[0:0]$4790 + attribute \src "issuer_ls180.v:119266.7-119266.43" + wire $1\alu_div0_logical_op__is_32bit[0:0] + attribute \src "issuer_ls180.v:119980.3-120018.6" + wire $1\alu_div0_logical_op__is_signed$next[0:0]$4791 + attribute \src "issuer_ls180.v:119270.7-119270.44" + wire $1\alu_div0_logical_op__is_signed[0:0] + attribute \src "issuer_ls180.v:119980.3-120018.6" + wire $1\alu_div0_logical_op__oe__oe$next[0:0]$4792 + attribute \src "issuer_ls180.v:119274.7-119274.41" + wire $1\alu_div0_logical_op__oe__oe[0:0] + attribute \src "issuer_ls180.v:119980.3-120018.6" + wire $1\alu_div0_logical_op__oe__ok$next[0:0]$4793 + attribute \src "issuer_ls180.v:119278.7-119278.41" + wire $1\alu_div0_logical_op__oe__ok[0:0] + attribute \src "issuer_ls180.v:119980.3-120018.6" + wire $1\alu_div0_logical_op__output_carry$next[0:0]$4794 + attribute \src "issuer_ls180.v:119282.7-119282.47" + wire $1\alu_div0_logical_op__output_carry[0:0] + attribute \src "issuer_ls180.v:119980.3-120018.6" + wire $1\alu_div0_logical_op__rc__ok$next[0:0]$4795 + attribute \src "issuer_ls180.v:119286.7-119286.41" + wire $1\alu_div0_logical_op__rc__ok[0:0] + attribute \src "issuer_ls180.v:119980.3-120018.6" + wire $1\alu_div0_logical_op__rc__rc$next[0:0]$4796 + attribute \src "issuer_ls180.v:119290.7-119290.41" + wire $1\alu_div0_logical_op__rc__rc[0:0] + attribute \src "issuer_ls180.v:119980.3-120018.6" + wire $1\alu_div0_logical_op__write_cr0$next[0:0]$4797 + attribute \src "issuer_ls180.v:119294.7-119294.44" + wire $1\alu_div0_logical_op__write_cr0[0:0] + attribute \src "issuer_ls180.v:119980.3-120018.6" + wire $1\alu_div0_logical_op__zero_a$next[0:0]$4798 + attribute \src "issuer_ls180.v:119298.7-119298.41" + wire $1\alu_div0_logical_op__zero_a[0:0] + attribute \src "issuer_ls180.v:119324.7-119324.26" + wire $1\alu_done_dly[0:0] + attribute \src "issuer_ls180.v:120146.3-120154.6" + wire $1\alu_l_r_alu$next[0:0]$4851 + attribute \src "issuer_ls180.v:119332.7-119332.25" + wire $1\alu_l_r_alu[0:0] + attribute \src "issuer_ls180.v:120137.3-120145.6" + wire $1\alui_l_r_alui$next[0:0]$4848 + attribute \src "issuer_ls180.v:119344.7-119344.27" + wire $1\alui_l_r_alui[0:0] + attribute \src "issuer_ls180.v:120019.3-120040.6" + wire width 64 $1\data_r0__o$next[63:0]$4808 + attribute \src "issuer_ls180.v:119378.14-119378.47" + wire width 64 $1\data_r0__o[63:0] + attribute \src "issuer_ls180.v:120019.3-120040.6" + wire $1\data_r0__o_ok$next[0:0]$4809 + attribute \src "issuer_ls180.v:119382.7-119382.27" + wire $1\data_r0__o_ok[0:0] + attribute \src "issuer_ls180.v:120041.3-120062.6" + wire width 4 $1\data_r1__cr_a$next[3:0]$4816 + attribute \src "issuer_ls180.v:119386.13-119386.33" + wire width 4 $1\data_r1__cr_a[3:0] + attribute \src "issuer_ls180.v:120041.3-120062.6" + wire $1\data_r1__cr_a_ok$next[0:0]$4817 + attribute \src "issuer_ls180.v:119390.7-119390.30" + wire $1\data_r1__cr_a_ok[0:0] + attribute \src "issuer_ls180.v:120063.3-120084.6" + wire width 2 $1\data_r2__xer_ov$next[1:0]$4824 + attribute \src "issuer_ls180.v:119394.13-119394.35" + wire width 2 $1\data_r2__xer_ov[1:0] + attribute \src "issuer_ls180.v:120063.3-120084.6" + wire $1\data_r2__xer_ov_ok$next[0:0]$4825 + attribute \src "issuer_ls180.v:119398.7-119398.32" + wire $1\data_r2__xer_ov_ok[0:0] + attribute \src "issuer_ls180.v:120085.3-120106.6" + wire $1\data_r3__xer_so$next[0:0]$4832 + attribute \src "issuer_ls180.v:119402.7-119402.29" + wire $1\data_r3__xer_so[0:0] + attribute \src "issuer_ls180.v:120085.3-120106.6" + wire $1\data_r3__xer_so_ok$next[0:0]$4833 + attribute \src "issuer_ls180.v:119406.7-119406.32" + wire $1\data_r3__xer_so_ok[0:0] + attribute \src "issuer_ls180.v:120155.3-120164.6" + wire width 64 $1\dest1_o[63:0] + attribute \src "issuer_ls180.v:120165.3-120174.6" + wire width 4 $1\dest2_o[3:0] + attribute \src "issuer_ls180.v:120175.3-120184.6" + wire width 2 $1\dest3_o[1:0] + attribute \src "issuer_ls180.v:120185.3-120194.6" + wire $1\dest4_o[0:0] + attribute \src "issuer_ls180.v:119935.3-119943.6" + wire $1\opc_l_r_opc$next[0:0]$4749 + attribute \src "issuer_ls180.v:119426.7-119426.25" + wire $1\opc_l_r_opc[0:0] + attribute \src "issuer_ls180.v:119926.3-119934.6" + wire $1\opc_l_s_opc$next[0:0]$4746 + attribute \src "issuer_ls180.v:119430.7-119430.25" + wire $1\opc_l_s_opc[0:0] + attribute \src "issuer_ls180.v:120195.3-120203.6" + wire width 4 $1\prev_wr_go$next[3:0]$4858 + attribute \src "issuer_ls180.v:119561.13-119561.30" + wire width 4 $1\prev_wr_go[3:0] + attribute \src "issuer_ls180.v:119880.3-119889.6" + wire $1\req_done[0:0] + attribute \src "issuer_ls180.v:119971.3-119979.6" + wire width 4 $1\req_l_r_req$next[3:0]$4761 + attribute \src "issuer_ls180.v:119569.13-119569.31" + wire width 4 $1\req_l_r_req[3:0] + attribute \src "issuer_ls180.v:119962.3-119970.6" + wire width 4 $1\req_l_s_req$next[3:0]$4758 + attribute \src "issuer_ls180.v:119573.13-119573.31" + wire width 4 $1\req_l_s_req[3:0] + attribute \src "issuer_ls180.v:119899.3-119907.6" + wire $1\rok_l_r_rdok$next[0:0]$4737 + attribute \src "issuer_ls180.v:119585.7-119585.26" + wire $1\rok_l_r_rdok[0:0] + attribute \src "issuer_ls180.v:119890.3-119898.6" + wire $1\rok_l_s_rdok$next[0:0]$4734 + attribute \src "issuer_ls180.v:119589.7-119589.26" + wire $1\rok_l_s_rdok[0:0] + attribute \src "issuer_ls180.v:119917.3-119925.6" + wire $1\rst_l_r_rst$next[0:0]$4743 + attribute \src "issuer_ls180.v:119593.7-119593.25" + wire $1\rst_l_r_rst[0:0] + attribute \src "issuer_ls180.v:119908.3-119916.6" + wire $1\rst_l_s_rst$next[0:0]$4740 + attribute \src "issuer_ls180.v:119597.7-119597.25" + wire $1\rst_l_s_rst[0:0] + attribute \src "issuer_ls180.v:119953.3-119961.6" + wire width 3 $1\src_l_r_src$next[2:0]$4755 + attribute \src "issuer_ls180.v:119611.13-119611.31" + wire width 3 $1\src_l_r_src[2:0] + attribute \src "issuer_ls180.v:119944.3-119952.6" + wire width 3 $1\src_l_s_src$next[2:0]$4752 + attribute \src "issuer_ls180.v:119615.13-119615.31" + wire width 3 $1\src_l_s_src[2:0] + attribute \src "issuer_ls180.v:120107.3-120116.6" + wire width 64 $1\src_r0$next[63:0]$4839 + attribute \src "issuer_ls180.v:119623.14-119623.43" + wire width 64 $1\src_r0[63:0] + attribute \src "issuer_ls180.v:120117.3-120126.6" + wire width 64 $1\src_r1$next[63:0]$4842 + attribute \src "issuer_ls180.v:119627.14-119627.43" + wire width 64 $1\src_r1[63:0] + attribute \src "issuer_ls180.v:120127.3-120136.6" + wire $1\src_r2$next[0:0]$4845 + attribute \src "issuer_ls180.v:119631.7-119631.20" + wire $1\src_r2[0:0] + attribute \src "issuer_ls180.v:119980.3-120018.6" + wire width 64 $2\alu_div0_logical_op__imm_data__data$next[63:0]$4799 + attribute \src "issuer_ls180.v:119980.3-120018.6" + wire $2\alu_div0_logical_op__imm_data__ok$next[0:0]$4800 + attribute \src "issuer_ls180.v:119980.3-120018.6" + wire $2\alu_div0_logical_op__oe__oe$next[0:0]$4801 + attribute \src "issuer_ls180.v:119980.3-120018.6" + wire $2\alu_div0_logical_op__oe__ok$next[0:0]$4802 + attribute \src "issuer_ls180.v:119980.3-120018.6" + wire $2\alu_div0_logical_op__rc__ok$next[0:0]$4803 + attribute \src "issuer_ls180.v:119980.3-120018.6" + wire $2\alu_div0_logical_op__rc__rc$next[0:0]$4804 + attribute \src "issuer_ls180.v:120019.3-120040.6" + wire width 64 $2\data_r0__o$next[63:0]$4810 + attribute \src "issuer_ls180.v:120019.3-120040.6" + wire $2\data_r0__o_ok$next[0:0]$4811 + attribute \src "issuer_ls180.v:120041.3-120062.6" + wire width 4 $2\data_r1__cr_a$next[3:0]$4818 + attribute \src "issuer_ls180.v:120041.3-120062.6" + wire $2\data_r1__cr_a_ok$next[0:0]$4819 + attribute \src "issuer_ls180.v:120063.3-120084.6" + wire width 2 $2\data_r2__xer_ov$next[1:0]$4826 + attribute \src "issuer_ls180.v:120063.3-120084.6" + wire $2\data_r2__xer_ov_ok$next[0:0]$4827 + attribute \src "issuer_ls180.v:120085.3-120106.6" + wire $2\data_r3__xer_so$next[0:0]$4834 + attribute \src "issuer_ls180.v:120085.3-120106.6" + wire $2\data_r3__xer_so_ok$next[0:0]$4835 + attribute \src "issuer_ls180.v:120019.3-120040.6" + wire $3\data_r0__o_ok$next[0:0]$4812 + attribute \src "issuer_ls180.v:120041.3-120062.6" + wire $3\data_r1__cr_a_ok$next[0:0]$4820 + attribute \src "issuer_ls180.v:120063.3-120084.6" + wire $3\data_r2__xer_ov_ok$next[0:0]$4828 + attribute \src "issuer_ls180.v:120085.3-120106.6" + wire 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"OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \alu_div0_logical_op__insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \alu_div0_logical_op__insn_type$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_div0_logical_op__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_div0_logical_op__invert_in$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_div0_logical_op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_div0_logical_op__invert_out$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_div0_logical_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_div0_logical_op__is_32bit$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_div0_logical_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_div0_logical_op__is_signed$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_div0_logical_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_div0_logical_op__oe__oe$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_div0_logical_op__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_div0_logical_op__oe__ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_div0_logical_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_div0_logical_op__output_carry$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_div0_logical_op__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_div0_logical_op__rc__ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_div0_logical_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_div0_logical_op__rc__rc$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_div0_logical_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_div0_logical_op__write_cr0$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_div0_logical_op__zero_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_div0_logical_op__zero_a$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" + wire \alu_div0_n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" + wire \alu_div0_n_valid_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 \alu_div0_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" + wire \alu_div0_p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" + wire \alu_div0_p_valid_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \alu_div0_ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \alu_div0_rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 2 \alu_div0_xer_ov + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \alu_div0_xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire \alu_div0_xer_so$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:196" + wire \alu_done + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" + wire \alu_done_dly + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" + wire \alu_done_dly$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" + wire \alu_done_rise + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire \alu_l_q_alu + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire \alu_l_r_alu + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire \alu_l_r_alu$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire \alu_l_s_alu + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:197" + wire \alu_pulse + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:198" + wire width 4 \alu_pulsem + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire \alui_l_q_alui + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire \alui_l_r_alui + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire \alui_l_r_alui$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire \alui_l_s_alui + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" + wire input 38 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" + wire input 37 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 31 \cr_a_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107" + wire output 20 \cu_busy_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:108" + wire \cu_done_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:104" + wire \cu_go_die_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:100" + wire input 19 \cu_issue_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 3 input 23 \cu_rd__go_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 3 output 22 \cu_rd__rel_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96" + wire width 3 input 21 \cu_rdmaskn_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:102" + wire \cu_shadown_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 4 input 29 \cu_wr__go_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 4 output 28 \cu_wr__rel_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:97" + wire width 4 \cu_wrmask_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire width 64 \data_r0__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire width 64 \data_r0__o$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire \data_r0__o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire \data_r0__o_ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire width 4 \data_r1__cr_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire width 4 \data_r1__cr_a$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire \data_r1__cr_a_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire \data_r1__cr_a_ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire width 2 \data_r2__xer_ov + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire width 2 \data_r2__xer_ov$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire \data_r2__xer_ov_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire \data_r2__xer_ov_ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire \data_r3__xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire \data_r3__xer_so$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire \data_r3__xer_so_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire \data_r3__xer_so_ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 64 output 30 \dest1_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 4 output 32 \dest2_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 2 output 34 \dest3_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire output 36 \dest4_o + attribute \src "issuer_ls180.v:118999.7-118999.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 27 \o_ok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire \opc_l_q_opc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire \opc_l_r_opc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire \opc_l_r_opc$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire \opc_l_s_opc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire \opc_l_s_opc$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 input 17 \oper_i_alu_div0__data_len + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 input 2 \oper_i_alu_div0__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 input 3 \oper_i_alu_div0__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 4 \oper_i_alu_div0__imm_data__ok + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 input 11 \oper_i_alu_div0__input_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 18 \oper_i_alu_div0__insn + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 input 1 \oper_i_alu_div0__insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 9 \oper_i_alu_div0__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 12 \oper_i_alu_div0__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 15 \oper_i_alu_div0__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 16 \oper_i_alu_div0__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 7 \oper_i_alu_div0__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 8 \oper_i_alu_div0__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 14 \oper_i_alu_div0__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 6 \oper_i_alu_div0__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 5 \oper_i_alu_div0__rc__rc + attribute \src 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$and$issuer_ls180.v:119705$4685 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \alu_div0_n_valid_o + connect \B \alu_l_q_alu + connect \Y $and$issuer_ls180.v:119705$4685_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" + cell $and $and$issuer_ls180.v:119706$4686 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \src_l_q_src + connect \B { \cu_busy_o \cu_busy_o \cu_busy_o } + connect \Y $and$issuer_ls180.v:119706$4686_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" + cell $eq $eq$issuer_ls180.v:119677$4657 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$42 + connect \B 1'0 + connect \Y $eq$issuer_ls180.v:119677$4657_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" + cell $eq $eq$issuer_ls180.v:119679$4659 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cu_wrmask_o + connect \B 1'0 + connect \Y $eq$issuer_ls180.v:119679$4659_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:173" + cell $not $not$issuer_ls180.v:119644$4624 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \alu_div0_logical_op__zero_a + connect \Y $not$issuer_ls180.v:119644$4624_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:173" + cell $not $not$issuer_ls180.v:119645$4625 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \alu_div0_logical_op__imm_data__ok + connect \Y $not$issuer_ls180.v:119645$4625_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" + cell $not $not$issuer_ls180.v:119647$4627 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \cu_rdmaskn_i + connect \Y $not$issuer_ls180.v:119647$4627_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + cell $not $not$issuer_ls180.v:119660$4640 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \all_rd_dly + connect \Y $not$issuer_ls180.v:119660$4640_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + cell $not $not$issuer_ls180.v:119662$4642 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \alu_done_dly + connect \Y $not$issuer_ls180.v:119662$4642_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" + cell $not $not$issuer_ls180.v:119665$4645 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \cu_wrmask_o + connect \Y $not$issuer_ls180.v:119665$4645_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" + cell $not $not$issuer_ls180.v:119668$4648 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$23 + connect \Y $not$issuer_ls180.v:119668$4648_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" + cell $not $not$issuer_ls180.v:119674$4654 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \alu_div0_n_ready_i + connect \Y $not$issuer_ls180.v:119674$4654_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" + cell $not $not$issuer_ls180.v:119685$4665 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \cu_rd__rel_o + connect \Y $not$issuer_ls180.v:119685$4665_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" + cell $or $or$issuer_ls180.v:119673$4653 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$32 + connect \B \$34 + connect \Y $or$issuer_ls180.v:119673$4653_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:230" + cell $or $or$issuer_ls180.v:119683$4663 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \req_done + connect \B \cu_go_die_i + connect \Y $or$issuer_ls180.v:119683$4663_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:231" + cell $or $or$issuer_ls180.v:119684$4664 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cu_issue_i + connect \B \cu_go_die_i + connect \Y $or$issuer_ls180.v:119684$4664_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:232" + cell $or $or$issuer_ls180.v:119686$4666 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \cu_wr__go_i + connect \B { \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i } + connect \Y $or$issuer_ls180.v:119686$4666_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:233" + cell $or $or$issuer_ls180.v:119687$4667 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \cu_rd__go_i + connect \B { \cu_go_die_i \cu_go_die_i \cu_go_die_i } + connect \Y $or$issuer_ls180.v:119687$4667_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:253" + cell $or $or$issuer_ls180.v:119690$4670 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \reset_w + connect \B \prev_wr_go + connect \Y $or$issuer_ls180.v:119690$4670_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" + cell $or $or$issuer_ls180.v:119696$4676 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \$5 + connect \B \cu_rd__go_i + connect \Y $or$issuer_ls180.v:119696$4676_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" + cell $reduce_and $reduce_and$issuer_ls180.v:119701$4681 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \$7 + connect \Y $reduce_and$issuer_ls180.v:119701$4681_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" + cell $reduce_or $reduce_or$issuer_ls180.v:119667$4647 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \$26 + connect \Y $reduce_or$issuer_ls180.v:119667$4647_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" + cell $reduce_or $reduce_or$issuer_ls180.v:119671$4651 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \cu_wr__go_i + connect \Y $reduce_or$issuer_ls180.v:119671$4651_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" + cell $reduce_or $reduce_or$issuer_ls180.v:119672$4652 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \prev_wr_go + connect \Y $reduce_or$issuer_ls180.v:119672$4652_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:168" + cell $mux $ternary$issuer_ls180.v:119695$4675 + parameter \WIDTH 1 + connect \A \src_l_q_src [0] + connect \B \opc_l_q_opc + connect \S \alu_div0_logical_op__zero_a + connect \Y $ternary$issuer_ls180.v:119695$4675_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:169" + cell $mux $ternary$issuer_ls180.v:119697$4677 + parameter \WIDTH 64 + connect \A \src1_i + connect \B 64'0000000000000000000000000000000000000000000000000000000000000000 + connect \S \alu_div0_logical_op__zero_a + connect \Y $ternary$issuer_ls180.v:119697$4677_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:168" + cell $mux $ternary$issuer_ls180.v:119698$4678 + parameter \WIDTH 1 + connect \A \src_l_q_src [1] + connect \B \opc_l_q_opc + connect \S \alu_div0_logical_op__imm_data__ok + connect \Y $ternary$issuer_ls180.v:119698$4678_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:169" + cell $mux $ternary$issuer_ls180.v:119699$4679 + parameter \WIDTH 64 + connect \A \src2_i + connect \B \alu_div0_logical_op__imm_data__data + connect \S \alu_div0_logical_op__imm_data__ok + connect \Y $ternary$issuer_ls180.v:119699$4679_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + cell $mux $ternary$issuer_ls180.v:119700$4680 + parameter \WIDTH 64 + connect \A \src_r0 + connect \B \src_or_imm + connect \S \src_sel + connect \Y $ternary$issuer_ls180.v:119700$4680_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + cell $mux $ternary$issuer_ls180.v:119702$4682 + parameter \WIDTH 64 + connect \A \src_r1 + connect \B \src_or_imm$85 + connect \S \src_sel$82 + connect \Y $ternary$issuer_ls180.v:119702$4682_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + cell $mux $ternary$issuer_ls180.v:119703$4683 + parameter \WIDTH 1 + connect \A \src_r2 + connect \B \src3_i + connect \S \src_l_q_src [2] + connect \Y $ternary$issuer_ls180.v:119703$4683_Y + end + attribute \module_not_derived 1 + attribute \src "issuer_ls180.v:119795.12-119831.4" + cell \alu_div0 \alu_div0 + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \cr_a \alu_div0_cr_a + connect \cr_a_ok \cr_a_ok + connect \logical_op__data_len \alu_div0_logical_op__data_len + connect \logical_op__fn_unit \alu_div0_logical_op__fn_unit + connect \logical_op__imm_data__data \alu_div0_logical_op__imm_data__data + connect \logical_op__imm_data__ok \alu_div0_logical_op__imm_data__ok + connect \logical_op__input_carry \alu_div0_logical_op__input_carry + connect \logical_op__insn \alu_div0_logical_op__insn + connect \logical_op__insn_type \alu_div0_logical_op__insn_type + connect \logical_op__invert_in \alu_div0_logical_op__invert_in + connect \logical_op__invert_out \alu_div0_logical_op__invert_out + connect \logical_op__is_32bit \alu_div0_logical_op__is_32bit + connect \logical_op__is_signed \alu_div0_logical_op__is_signed + connect \logical_op__oe__oe \alu_div0_logical_op__oe__oe + connect \logical_op__oe__ok \alu_div0_logical_op__oe__ok + connect \logical_op__output_carry \alu_div0_logical_op__output_carry + connect \logical_op__rc__ok \alu_div0_logical_op__rc__ok + connect \logical_op__rc__rc \alu_div0_logical_op__rc__rc + connect \logical_op__write_cr0 \alu_div0_logical_op__write_cr0 + connect \logical_op__zero_a \alu_div0_logical_op__zero_a + connect \n_ready_i \alu_div0_n_ready_i + connect \n_valid_o \alu_div0_n_valid_o + connect \o \alu_div0_o + connect \o_ok \o_ok + connect \p_ready_o \alu_div0_p_ready_o + connect \p_valid_i \alu_div0_p_valid_i + connect \ra \alu_div0_ra + connect \rb \alu_div0_rb + connect \xer_ov \alu_div0_xer_ov + connect \xer_ov_ok \xer_ov_ok + connect \xer_so \alu_div0_xer_so + connect \xer_so$1 \alu_div0_xer_so$1 + connect \xer_so_ok \xer_so_ok + end + attribute \module_not_derived 1 + attribute \src "issuer_ls180.v:119832.14-119838.4" + cell \alu_l$87 \alu_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_alu \alu_l_q_alu + connect \r_alu \alu_l_r_alu + connect \s_alu \alu_l_s_alu + end + attribute \module_not_derived 1 + attribute \src "issuer_ls180.v:119839.15-119845.4" + cell \alui_l$86 \alui_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_alui \alui_l_q_alui + connect \r_alui \alui_l_r_alui + connect \s_alui \alui_l_s_alui + end + attribute \module_not_derived 1 + attribute \src "issuer_ls180.v:119846.14-119852.4" + cell \opc_l$82 \opc_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_opc \opc_l_q_opc + connect \r_opc \opc_l_r_opc + connect \s_opc \opc_l_s_opc + end + attribute \module_not_derived 1 + attribute \src "issuer_ls180.v:119853.14-119859.4" + cell \req_l$83 \req_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_req \req_l_q_req + connect \r_req \req_l_r_req + connect \s_req \req_l_s_req + end + attribute \module_not_derived 1 + attribute \src "issuer_ls180.v:119860.14-119866.4" + cell \rok_l$85 \rok_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_rdok \rok_l_q_rdok + connect \r_rdok \rok_l_r_rdok + connect \s_rdok \rok_l_s_rdok + end + attribute \module_not_derived 1 + attribute \src "issuer_ls180.v:119867.14-119872.4" + cell \rst_l$84 \rst_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \r_rst \rst_l_r_rst + connect \s_rst \rst_l_s_rst + end + attribute \module_not_derived 1 + attribute \src "issuer_ls180.v:119873.14-119879.4" + cell \src_l$81 \src_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_src \src_l_q_src + connect \r_src \src_l_r_src + connect \s_src \src_l_s_src + end + attribute \src "issuer_ls180.v:118999.7-118999.20" + process $proc$issuer_ls180.v:118999$4859 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "issuer_ls180.v:119129.7-119129.24" + process $proc$issuer_ls180.v:119129$4860 + assign { } { } + assign $1\all_rd_dly[0:0] 1'0 + sync always + sync init + update \all_rd_dly $1\all_rd_dly[0:0] + end + attribute \src "issuer_ls180.v:119139.13-119139.49" + process $proc$issuer_ls180.v:119139$4861 + assign { } { } + assign $1\alu_div0_logical_op__data_len[3:0] 4'0000 + sync always + sync init + update \alu_div0_logical_op__data_len $1\alu_div0_logical_op__data_len[3:0] + end + attribute \src "issuer_ls180.v:119156.14-119156.52" + process $proc$issuer_ls180.v:119156$4862 + assign { } { } + assign $1\alu_div0_logical_op__fn_unit[11:0] 12'000000000000 + sync always + sync init + update \alu_div0_logical_op__fn_unit $1\alu_div0_logical_op__fn_unit[11:0] + end + attribute \src "issuer_ls180.v:119160.14-119160.72" + process $proc$issuer_ls180.v:119160$4863 + assign { } { } + assign $1\alu_div0_logical_op__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \alu_div0_logical_op__imm_data__data $1\alu_div0_logical_op__imm_data__data[63:0] + end + attribute \src "issuer_ls180.v:119164.7-119164.47" + process $proc$issuer_ls180.v:119164$4864 + assign { } { } + assign $1\alu_div0_logical_op__imm_data__ok[0:0] 1'0 + sync always + sync init + update \alu_div0_logical_op__imm_data__ok $1\alu_div0_logical_op__imm_data__ok[0:0] + end + attribute \src "issuer_ls180.v:119172.13-119172.52" + process $proc$issuer_ls180.v:119172$4865 + assign { } { } + assign $1\alu_div0_logical_op__input_carry[1:0] 2'00 + sync always + sync init + update \alu_div0_logical_op__input_carry $1\alu_div0_logical_op__input_carry[1:0] + end + attribute \src "issuer_ls180.v:119176.14-119176.47" + process $proc$issuer_ls180.v:119176$4866 + assign { } { } + assign $1\alu_div0_logical_op__insn[31:0] 0 + sync always + sync init + update \alu_div0_logical_op__insn $1\alu_div0_logical_op__insn[31:0] + end + attribute \src "issuer_ls180.v:119254.13-119254.51" + process $proc$issuer_ls180.v:119254$4867 + assign { } { } + assign $1\alu_div0_logical_op__insn_type[6:0] 7'0000000 + sync always + sync init + update \alu_div0_logical_op__insn_type $1\alu_div0_logical_op__insn_type[6:0] + end + attribute \src "issuer_ls180.v:119258.7-119258.44" + process $proc$issuer_ls180.v:119258$4868 + assign { } { } + assign $1\alu_div0_logical_op__invert_in[0:0] 1'0 + sync always + sync init + update \alu_div0_logical_op__invert_in $1\alu_div0_logical_op__invert_in[0:0] + end + attribute \src "issuer_ls180.v:119262.7-119262.45" + process $proc$issuer_ls180.v:119262$4869 + assign { } { } + assign $1\alu_div0_logical_op__invert_out[0:0] 1'0 + sync always + sync init + update \alu_div0_logical_op__invert_out $1\alu_div0_logical_op__invert_out[0:0] + end + attribute \src "issuer_ls180.v:119266.7-119266.43" + process $proc$issuer_ls180.v:119266$4870 + assign { } { } + assign $1\alu_div0_logical_op__is_32bit[0:0] 1'0 + sync always + sync init + update \alu_div0_logical_op__is_32bit $1\alu_div0_logical_op__is_32bit[0:0] + end + attribute \src "issuer_ls180.v:119270.7-119270.44" + process $proc$issuer_ls180.v:119270$4871 + assign { } { } + assign $1\alu_div0_logical_op__is_signed[0:0] 1'0 + sync always + sync init + update \alu_div0_logical_op__is_signed $1\alu_div0_logical_op__is_signed[0:0] + end + attribute \src "issuer_ls180.v:119274.7-119274.41" + process $proc$issuer_ls180.v:119274$4872 + assign { } { } + assign $1\alu_div0_logical_op__oe__oe[0:0] 1'0 + sync always + sync init + update \alu_div0_logical_op__oe__oe $1\alu_div0_logical_op__oe__oe[0:0] + end + attribute \src "issuer_ls180.v:119278.7-119278.41" + process $proc$issuer_ls180.v:119278$4873 + assign { } { } + assign $1\alu_div0_logical_op__oe__ok[0:0] 1'0 + sync always + sync init + update \alu_div0_logical_op__oe__ok $1\alu_div0_logical_op__oe__ok[0:0] + end + attribute \src "issuer_ls180.v:119282.7-119282.47" + process $proc$issuer_ls180.v:119282$4874 + assign { } { } + assign $1\alu_div0_logical_op__output_carry[0:0] 1'0 + sync always + sync init + update \alu_div0_logical_op__output_carry $1\alu_div0_logical_op__output_carry[0:0] + end + attribute \src "issuer_ls180.v:119286.7-119286.41" + process $proc$issuer_ls180.v:119286$4875 + assign { } { } + assign $1\alu_div0_logical_op__rc__ok[0:0] 1'0 + sync always + sync init + update \alu_div0_logical_op__rc__ok $1\alu_div0_logical_op__rc__ok[0:0] + end + attribute \src "issuer_ls180.v:119290.7-119290.41" + process $proc$issuer_ls180.v:119290$4876 + assign { } { } + assign $1\alu_div0_logical_op__rc__rc[0:0] 1'0 + sync always + sync init + update \alu_div0_logical_op__rc__rc $1\alu_div0_logical_op__rc__rc[0:0] + end + attribute \src "issuer_ls180.v:119294.7-119294.44" + process $proc$issuer_ls180.v:119294$4877 + assign { } { } + assign $1\alu_div0_logical_op__write_cr0[0:0] 1'0 + sync always + sync init + update \alu_div0_logical_op__write_cr0 $1\alu_div0_logical_op__write_cr0[0:0] + end + attribute \src "issuer_ls180.v:119298.7-119298.41" + process $proc$issuer_ls180.v:119298$4878 + assign { } { } + assign $1\alu_div0_logical_op__zero_a[0:0] 1'0 + sync always + sync init + update \alu_div0_logical_op__zero_a $1\alu_div0_logical_op__zero_a[0:0] + end + attribute \src "issuer_ls180.v:119324.7-119324.26" + process $proc$issuer_ls180.v:119324$4879 + assign { } { } + assign $1\alu_done_dly[0:0] 1'0 + sync always + sync init + update \alu_done_dly $1\alu_done_dly[0:0] + end + attribute \src "issuer_ls180.v:119332.7-119332.25" + process $proc$issuer_ls180.v:119332$4880 + assign { } { } + assign $1\alu_l_r_alu[0:0] 1'1 + sync always + sync init + update \alu_l_r_alu $1\alu_l_r_alu[0:0] + end + attribute \src "issuer_ls180.v:119344.7-119344.27" + process $proc$issuer_ls180.v:119344$4881 + assign { } { } + assign $1\alui_l_r_alui[0:0] 1'1 + sync always + sync init + update \alui_l_r_alui $1\alui_l_r_alui[0:0] + end + attribute \src "issuer_ls180.v:119378.14-119378.47" + process $proc$issuer_ls180.v:119378$4882 + assign { } { } + assign $1\data_r0__o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \data_r0__o $1\data_r0__o[63:0] + end + attribute \src "issuer_ls180.v:119382.7-119382.27" + process $proc$issuer_ls180.v:119382$4883 + assign { } { } + assign $1\data_r0__o_ok[0:0] 1'0 + sync always + sync init + update \data_r0__o_ok $1\data_r0__o_ok[0:0] + end + attribute \src "issuer_ls180.v:119386.13-119386.33" + process $proc$issuer_ls180.v:119386$4884 + assign { } { } + assign $1\data_r1__cr_a[3:0] 4'0000 + sync always + sync init + update \data_r1__cr_a $1\data_r1__cr_a[3:0] + end + attribute \src "issuer_ls180.v:119390.7-119390.30" + process $proc$issuer_ls180.v:119390$4885 + assign { } { } + assign $1\data_r1__cr_a_ok[0:0] 1'0 + sync always + sync init + update \data_r1__cr_a_ok $1\data_r1__cr_a_ok[0:0] + end + attribute \src "issuer_ls180.v:119394.13-119394.35" + process $proc$issuer_ls180.v:119394$4886 + assign { } { } + assign $1\data_r2__xer_ov[1:0] 2'00 + sync always + sync init + update \data_r2__xer_ov $1\data_r2__xer_ov[1:0] + end + attribute \src "issuer_ls180.v:119398.7-119398.32" + process $proc$issuer_ls180.v:119398$4887 + assign { } { } + assign $1\data_r2__xer_ov_ok[0:0] 1'0 + sync always + sync init + update \data_r2__xer_ov_ok $1\data_r2__xer_ov_ok[0:0] + end + attribute \src "issuer_ls180.v:119402.7-119402.29" + process $proc$issuer_ls180.v:119402$4888 + assign { } { } + assign $1\data_r3__xer_so[0:0] 1'0 + sync always + sync init + update \data_r3__xer_so $1\data_r3__xer_so[0:0] + end + attribute \src "issuer_ls180.v:119406.7-119406.32" + process $proc$issuer_ls180.v:119406$4889 + assign { } { } + assign $1\data_r3__xer_so_ok[0:0] 1'0 + sync always + sync init + update \data_r3__xer_so_ok $1\data_r3__xer_so_ok[0:0] + end + attribute \src "issuer_ls180.v:119426.7-119426.25" + process $proc$issuer_ls180.v:119426$4890 + assign { } { } + assign $1\opc_l_r_opc[0:0] 1'1 + sync always + sync init + update \opc_l_r_opc $1\opc_l_r_opc[0:0] + end + attribute \src "issuer_ls180.v:119430.7-119430.25" + process $proc$issuer_ls180.v:119430$4891 + assign { } { } + assign $1\opc_l_s_opc[0:0] 1'0 + sync always + sync init + update \opc_l_s_opc $1\opc_l_s_opc[0:0] + end + attribute \src "issuer_ls180.v:119561.13-119561.30" + process $proc$issuer_ls180.v:119561$4892 + assign { } { } + assign $1\prev_wr_go[3:0] 4'0000 + sync always + sync init + update \prev_wr_go $1\prev_wr_go[3:0] + end + attribute \src "issuer_ls180.v:119569.13-119569.31" + process $proc$issuer_ls180.v:119569$4893 + assign { } { } + assign $1\req_l_r_req[3:0] 4'1111 + sync always + sync init + update \req_l_r_req $1\req_l_r_req[3:0] + end + attribute \src "issuer_ls180.v:119573.13-119573.31" + process $proc$issuer_ls180.v:119573$4894 + assign { } { } + assign $1\req_l_s_req[3:0] 4'0000 + sync always + sync init + update \req_l_s_req $1\req_l_s_req[3:0] + end + attribute \src "issuer_ls180.v:119585.7-119585.26" + process $proc$issuer_ls180.v:119585$4895 + assign { } { } + assign $1\rok_l_r_rdok[0:0] 1'1 + sync always + sync init + update \rok_l_r_rdok $1\rok_l_r_rdok[0:0] + end + attribute \src "issuer_ls180.v:119589.7-119589.26" + process $proc$issuer_ls180.v:119589$4896 + assign { } { } + assign $1\rok_l_s_rdok[0:0] 1'0 + sync always + sync init + update \rok_l_s_rdok $1\rok_l_s_rdok[0:0] + end + attribute \src "issuer_ls180.v:119593.7-119593.25" + process $proc$issuer_ls180.v:119593$4897 + assign { } { } + assign $1\rst_l_r_rst[0:0] 1'1 + sync always + sync init + update \rst_l_r_rst $1\rst_l_r_rst[0:0] + end + attribute \src "issuer_ls180.v:119597.7-119597.25" + process $proc$issuer_ls180.v:119597$4898 + assign { } { } + assign $1\rst_l_s_rst[0:0] 1'0 + sync always + sync init + update \rst_l_s_rst $1\rst_l_s_rst[0:0] + end + attribute \src "issuer_ls180.v:119611.13-119611.31" + process $proc$issuer_ls180.v:119611$4899 + assign { } { } + assign $1\src_l_r_src[2:0] 3'111 + sync always + sync init + update \src_l_r_src $1\src_l_r_src[2:0] + end + attribute \src "issuer_ls180.v:119615.13-119615.31" + process $proc$issuer_ls180.v:119615$4900 + assign { } { } + assign $1\src_l_s_src[2:0] 3'000 + sync always + sync init + update \src_l_s_src $1\src_l_s_src[2:0] + end + attribute \src "issuer_ls180.v:119623.14-119623.43" + process $proc$issuer_ls180.v:119623$4901 + assign { } { } + assign $1\src_r0[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \src_r0 $1\src_r0[63:0] + end + attribute \src "issuer_ls180.v:119627.14-119627.43" + process $proc$issuer_ls180.v:119627$4902 + assign { } { } + assign $1\src_r1[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \src_r1 $1\src_r1[63:0] + end + attribute \src "issuer_ls180.v:119631.7-119631.20" + process $proc$issuer_ls180.v:119631$4903 + assign { } { } + assign $1\src_r2[0:0] 1'0 + sync always + sync init + update \src_r2 $1\src_r2[0:0] + end + attribute \src "issuer_ls180.v:119707.3-119708.39" + process $proc$issuer_ls180.v:119707$4687 + assign { } { } + assign $0\alu_l_r_alu[0:0] \alu_l_r_alu$next + sync posedge \coresync_clk + update \alu_l_r_alu $0\alu_l_r_alu[0:0] + end + attribute \src "issuer_ls180.v:119709.3-119710.43" + process $proc$issuer_ls180.v:119709$4688 + assign { } { } + assign $0\alui_l_r_alui[0:0] \alui_l_r_alui$next + sync posedge \coresync_clk + update \alui_l_r_alui $0\alui_l_r_alui[0:0] + end + attribute \src "issuer_ls180.v:119711.3-119712.29" + process $proc$issuer_ls180.v:119711$4689 + assign { } { } + assign $0\src_r2[0:0] \src_r2$next + sync posedge \coresync_clk + update \src_r2 $0\src_r2[0:0] + end + attribute \src "issuer_ls180.v:119713.3-119714.29" + process $proc$issuer_ls180.v:119713$4690 + assign { } { } + assign $0\src_r1[63:0] \src_r1$next + sync posedge \coresync_clk + update \src_r1 $0\src_r1[63:0] + end + attribute \src "issuer_ls180.v:119715.3-119716.29" + process $proc$issuer_ls180.v:119715$4691 + assign { } { } + assign $0\src_r0[63:0] \src_r0$next + sync posedge \coresync_clk + update \src_r0 $0\src_r0[63:0] + end + attribute \src "issuer_ls180.v:119717.3-119718.47" + process $proc$issuer_ls180.v:119717$4692 + assign { } { } + assign $0\data_r3__xer_so[0:0] \data_r3__xer_so$next + sync posedge \coresync_clk + update \data_r3__xer_so $0\data_r3__xer_so[0:0] + end + attribute \src "issuer_ls180.v:119719.3-119720.53" + process $proc$issuer_ls180.v:119719$4693 + assign { } { } + assign $0\data_r3__xer_so_ok[0:0] \data_r3__xer_so_ok$next + sync posedge \coresync_clk + update \data_r3__xer_so_ok $0\data_r3__xer_so_ok[0:0] + end + attribute \src "issuer_ls180.v:119721.3-119722.47" + process $proc$issuer_ls180.v:119721$4694 + assign { } { } + assign $0\data_r2__xer_ov[1:0] \data_r2__xer_ov$next + sync posedge \coresync_clk + update \data_r2__xer_ov $0\data_r2__xer_ov[1:0] + end + attribute \src "issuer_ls180.v:119723.3-119724.53" + process $proc$issuer_ls180.v:119723$4695 + assign { } { } + assign $0\data_r2__xer_ov_ok[0:0] \data_r2__xer_ov_ok$next + sync posedge \coresync_clk + update \data_r2__xer_ov_ok $0\data_r2__xer_ov_ok[0:0] + end + attribute \src "issuer_ls180.v:119725.3-119726.43" + process $proc$issuer_ls180.v:119725$4696 + assign { } { } + assign $0\data_r1__cr_a[3:0] \data_r1__cr_a$next + sync posedge \coresync_clk + update \data_r1__cr_a $0\data_r1__cr_a[3:0] + end + attribute \src "issuer_ls180.v:119727.3-119728.49" + process $proc$issuer_ls180.v:119727$4697 + assign { } { } + assign $0\data_r1__cr_a_ok[0:0] \data_r1__cr_a_ok$next + sync posedge \coresync_clk + update \data_r1__cr_a_ok $0\data_r1__cr_a_ok[0:0] + end + attribute \src "issuer_ls180.v:119729.3-119730.37" + process $proc$issuer_ls180.v:119729$4698 + assign { } { } + assign $0\data_r0__o[63:0] \data_r0__o$next + sync posedge \coresync_clk + update \data_r0__o $0\data_r0__o[63:0] + end + attribute \src "issuer_ls180.v:119731.3-119732.43" + process $proc$issuer_ls180.v:119731$4699 + assign { } { } + assign $0\data_r0__o_ok[0:0] \data_r0__o_ok$next + sync posedge \coresync_clk + update \data_r0__o_ok $0\data_r0__o_ok[0:0] + end + attribute \src "issuer_ls180.v:119733.3-119734.77" + process $proc$issuer_ls180.v:119733$4700 + assign { } { } + assign $0\alu_div0_logical_op__insn_type[6:0] \alu_div0_logical_op__insn_type$next + sync posedge \coresync_clk + update \alu_div0_logical_op__insn_type $0\alu_div0_logical_op__insn_type[6:0] + end + attribute \src "issuer_ls180.v:119735.3-119736.73" + process $proc$issuer_ls180.v:119735$4701 + assign { } { } + assign $0\alu_div0_logical_op__fn_unit[11:0] \alu_div0_logical_op__fn_unit$next + sync posedge \coresync_clk + update \alu_div0_logical_op__fn_unit $0\alu_div0_logical_op__fn_unit[11:0] + end + attribute \src "issuer_ls180.v:119737.3-119738.87" + process $proc$issuer_ls180.v:119737$4702 + assign { } { } + assign $0\alu_div0_logical_op__imm_data__data[63:0] \alu_div0_logical_op__imm_data__data$next + sync posedge \coresync_clk + update \alu_div0_logical_op__imm_data__data $0\alu_div0_logical_op__imm_data__data[63:0] + end + attribute \src "issuer_ls180.v:119739.3-119740.83" + process $proc$issuer_ls180.v:119739$4703 + assign { } { } + assign $0\alu_div0_logical_op__imm_data__ok[0:0] \alu_div0_logical_op__imm_data__ok$next + sync posedge \coresync_clk + update \alu_div0_logical_op__imm_data__ok $0\alu_div0_logical_op__imm_data__ok[0:0] + end + attribute \src "issuer_ls180.v:119741.3-119742.71" + process $proc$issuer_ls180.v:119741$4704 + assign { } { } + assign $0\alu_div0_logical_op__rc__rc[0:0] \alu_div0_logical_op__rc__rc$next + sync posedge \coresync_clk + update \alu_div0_logical_op__rc__rc $0\alu_div0_logical_op__rc__rc[0:0] + end + attribute \src "issuer_ls180.v:119743.3-119744.71" + process $proc$issuer_ls180.v:119743$4705 + assign { } { } + assign $0\alu_div0_logical_op__rc__ok[0:0] \alu_div0_logical_op__rc__ok$next + sync posedge \coresync_clk + update \alu_div0_logical_op__rc__ok $0\alu_div0_logical_op__rc__ok[0:0] + end + attribute \src "issuer_ls180.v:119745.3-119746.71" + process $proc$issuer_ls180.v:119745$4706 + assign { } { } + assign $0\alu_div0_logical_op__oe__oe[0:0] \alu_div0_logical_op__oe__oe$next + sync posedge \coresync_clk + update \alu_div0_logical_op__oe__oe $0\alu_div0_logical_op__oe__oe[0:0] + end + attribute \src "issuer_ls180.v:119747.3-119748.71" + process $proc$issuer_ls180.v:119747$4707 + assign { } { } + assign $0\alu_div0_logical_op__oe__ok[0:0] \alu_div0_logical_op__oe__ok$next + sync posedge \coresync_clk + update \alu_div0_logical_op__oe__ok $0\alu_div0_logical_op__oe__ok[0:0] + end + attribute \src "issuer_ls180.v:119749.3-119750.77" + process $proc$issuer_ls180.v:119749$4708 + assign { } { } + assign $0\alu_div0_logical_op__invert_in[0:0] \alu_div0_logical_op__invert_in$next + sync posedge \coresync_clk + update \alu_div0_logical_op__invert_in $0\alu_div0_logical_op__invert_in[0:0] + end + attribute \src "issuer_ls180.v:119751.3-119752.71" + process $proc$issuer_ls180.v:119751$4709 + assign { } { } + assign $0\alu_div0_logical_op__zero_a[0:0] \alu_div0_logical_op__zero_a$next + sync posedge \coresync_clk + update \alu_div0_logical_op__zero_a $0\alu_div0_logical_op__zero_a[0:0] + end + attribute \src "issuer_ls180.v:119753.3-119754.81" + process $proc$issuer_ls180.v:119753$4710 + assign { } { } + assign $0\alu_div0_logical_op__input_carry[1:0] \alu_div0_logical_op__input_carry$next + sync posedge \coresync_clk + update \alu_div0_logical_op__input_carry $0\alu_div0_logical_op__input_carry[1:0] + end + attribute \src "issuer_ls180.v:119755.3-119756.79" + process $proc$issuer_ls180.v:119755$4711 + assign { } { } + assign $0\alu_div0_logical_op__invert_out[0:0] \alu_div0_logical_op__invert_out$next + sync posedge \coresync_clk + update \alu_div0_logical_op__invert_out $0\alu_div0_logical_op__invert_out[0:0] + end + attribute \src "issuer_ls180.v:119757.3-119758.77" + process $proc$issuer_ls180.v:119757$4712 + assign { } { } + assign $0\alu_div0_logical_op__write_cr0[0:0] \alu_div0_logical_op__write_cr0$next + sync posedge \coresync_clk + update \alu_div0_logical_op__write_cr0 $0\alu_div0_logical_op__write_cr0[0:0] + end + attribute \src "issuer_ls180.v:119759.3-119760.83" + process $proc$issuer_ls180.v:119759$4713 + assign { } { } + assign $0\alu_div0_logical_op__output_carry[0:0] \alu_div0_logical_op__output_carry$next + sync posedge \coresync_clk + update \alu_div0_logical_op__output_carry $0\alu_div0_logical_op__output_carry[0:0] + end + attribute \src "issuer_ls180.v:119761.3-119762.75" + process $proc$issuer_ls180.v:119761$4714 + assign { } { } + assign $0\alu_div0_logical_op__is_32bit[0:0] \alu_div0_logical_op__is_32bit$next + sync posedge \coresync_clk + update \alu_div0_logical_op__is_32bit $0\alu_div0_logical_op__is_32bit[0:0] + end + attribute \src "issuer_ls180.v:119763.3-119764.77" + process $proc$issuer_ls180.v:119763$4715 + assign { } { } + assign $0\alu_div0_logical_op__is_signed[0:0] \alu_div0_logical_op__is_signed$next + sync posedge \coresync_clk + update \alu_div0_logical_op__is_signed $0\alu_div0_logical_op__is_signed[0:0] + end + attribute \src "issuer_ls180.v:119765.3-119766.75" + process $proc$issuer_ls180.v:119765$4716 + assign { } { } + assign $0\alu_div0_logical_op__data_len[3:0] \alu_div0_logical_op__data_len$next + sync posedge \coresync_clk + update \alu_div0_logical_op__data_len $0\alu_div0_logical_op__data_len[3:0] + end + attribute \src "issuer_ls180.v:119767.3-119768.67" + process $proc$issuer_ls180.v:119767$4717 + assign { } { } + assign $0\alu_div0_logical_op__insn[31:0] \alu_div0_logical_op__insn$next + sync posedge \coresync_clk + update \alu_div0_logical_op__insn $0\alu_div0_logical_op__insn[31:0] + end + attribute \src "issuer_ls180.v:119769.3-119770.39" + process $proc$issuer_ls180.v:119769$4718 + assign { } { } + assign $0\req_l_r_req[3:0] \req_l_r_req$next + sync posedge \coresync_clk + update \req_l_r_req $0\req_l_r_req[3:0] + end + attribute \src "issuer_ls180.v:119771.3-119772.39" + process $proc$issuer_ls180.v:119771$4719 + assign { } { } + assign $0\req_l_s_req[3:0] \req_l_s_req$next + sync posedge \coresync_clk + update \req_l_s_req $0\req_l_s_req[3:0] + end + attribute \src "issuer_ls180.v:119773.3-119774.39" + process $proc$issuer_ls180.v:119773$4720 + assign { } { } + assign $0\src_l_r_src[2:0] \src_l_r_src$next + sync posedge \coresync_clk + update \src_l_r_src $0\src_l_r_src[2:0] + end + attribute \src "issuer_ls180.v:119775.3-119776.39" + process $proc$issuer_ls180.v:119775$4721 + assign { } { } + assign $0\src_l_s_src[2:0] \src_l_s_src$next + sync posedge \coresync_clk + update \src_l_s_src $0\src_l_s_src[2:0] + end + attribute \src "issuer_ls180.v:119777.3-119778.39" + process $proc$issuer_ls180.v:119777$4722 + assign { } { } + assign $0\opc_l_r_opc[0:0] \opc_l_r_opc$next + sync posedge \coresync_clk + update \opc_l_r_opc $0\opc_l_r_opc[0:0] + end + attribute \src "issuer_ls180.v:119779.3-119780.39" + process $proc$issuer_ls180.v:119779$4723 + assign { } { } + assign $0\opc_l_s_opc[0:0] \opc_l_s_opc$next + sync posedge \coresync_clk + update \opc_l_s_opc $0\opc_l_s_opc[0:0] + end + attribute \src "issuer_ls180.v:119781.3-119782.39" + process $proc$issuer_ls180.v:119781$4724 + assign { } { } + assign $0\rst_l_r_rst[0:0] \rst_l_r_rst$next + sync posedge \coresync_clk + update \rst_l_r_rst $0\rst_l_r_rst[0:0] + end + attribute \src "issuer_ls180.v:119783.3-119784.39" + process $proc$issuer_ls180.v:119783$4725 + assign { } { } + assign $0\rst_l_s_rst[0:0] \rst_l_s_rst$next + sync posedge \coresync_clk + update \rst_l_s_rst $0\rst_l_s_rst[0:0] + end + attribute \src "issuer_ls180.v:119785.3-119786.41" + process $proc$issuer_ls180.v:119785$4726 + assign { } { } + assign $0\rok_l_r_rdok[0:0] \rok_l_r_rdok$next + sync posedge \coresync_clk + update \rok_l_r_rdok $0\rok_l_r_rdok[0:0] + end + attribute \src "issuer_ls180.v:119787.3-119788.41" + process $proc$issuer_ls180.v:119787$4727 + assign { } { } + assign $0\rok_l_s_rdok[0:0] \rok_l_s_rdok$next + sync posedge \coresync_clk + update \rok_l_s_rdok $0\rok_l_s_rdok[0:0] + end + attribute \src "issuer_ls180.v:119789.3-119790.37" + process $proc$issuer_ls180.v:119789$4728 + assign { } { } + assign $0\prev_wr_go[3:0] \prev_wr_go$next + sync posedge \coresync_clk + update \prev_wr_go $0\prev_wr_go[3:0] + end + attribute \src "issuer_ls180.v:119791.3-119792.40" + process $proc$issuer_ls180.v:119791$4729 + assign { } { } + assign $0\alu_done_dly[0:0] \alu_div0_n_valid_o + sync posedge \coresync_clk + update \alu_done_dly $0\alu_done_dly[0:0] + end + attribute \src "issuer_ls180.v:119793.3-119794.25" + process $proc$issuer_ls180.v:119793$4730 + assign { } { } + assign $0\all_rd_dly[0:0] \$10 + sync posedge \coresync_clk + update \all_rd_dly $0\all_rd_dly[0:0] + end + attribute \src "issuer_ls180.v:119880.3-119889.6" + process $proc$issuer_ls180.v:119880$4731 + assign { } { } + assign { } { } + assign $0\req_done[0:0] $1\req_done[0:0] + attribute \src "issuer_ls180.v:119881.5-119881.29" + switch \initial + attribute \src "issuer_ls180.v:119881.9-119881.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" + switch \$54 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\req_done[0:0] 1'1 + case + assign $1\req_done[0:0] \$46 + end + sync always + update \req_done $0\req_done[0:0] + end + attribute \src "issuer_ls180.v:119890.3-119898.6" + process $proc$issuer_ls180.v:119890$4732 + assign { } { } + assign { } { } + assign $0\rok_l_s_rdok$next[0:0]$4733 $1\rok_l_s_rdok$next[0:0]$4734 + attribute \src "issuer_ls180.v:119891.5-119891.29" + switch \initial + attribute \src "issuer_ls180.v:119891.9-119891.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\rok_l_s_rdok$next[0:0]$4734 1'0 + case + assign $1\rok_l_s_rdok$next[0:0]$4734 \cu_issue_i + end + sync always + update \rok_l_s_rdok$next $0\rok_l_s_rdok$next[0:0]$4733 + end + attribute \src "issuer_ls180.v:119899.3-119907.6" + process $proc$issuer_ls180.v:119899$4735 + assign { } { } + assign { } { } + assign $0\rok_l_r_rdok$next[0:0]$4736 $1\rok_l_r_rdok$next[0:0]$4737 + attribute \src "issuer_ls180.v:119900.5-119900.29" + switch \initial + attribute \src "issuer_ls180.v:119900.9-119900.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\rok_l_r_rdok$next[0:0]$4737 1'1 + case + assign $1\rok_l_r_rdok$next[0:0]$4737 \$64 + end + sync always + update \rok_l_r_rdok$next $0\rok_l_r_rdok$next[0:0]$4736 + end + attribute \src "issuer_ls180.v:119908.3-119916.6" + process $proc$issuer_ls180.v:119908$4738 + assign { } { } + assign { } { } + assign $0\rst_l_s_rst$next[0:0]$4739 $1\rst_l_s_rst$next[0:0]$4740 + attribute \src "issuer_ls180.v:119909.5-119909.29" + switch \initial + attribute \src "issuer_ls180.v:119909.9-119909.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\rst_l_s_rst$next[0:0]$4740 1'0 + case + assign $1\rst_l_s_rst$next[0:0]$4740 \all_rd + end + sync always + update \rst_l_s_rst$next $0\rst_l_s_rst$next[0:0]$4739 + end + attribute \src "issuer_ls180.v:119917.3-119925.6" + process $proc$issuer_ls180.v:119917$4741 + assign { } { } + assign { } { } + assign $0\rst_l_r_rst$next[0:0]$4742 $1\rst_l_r_rst$next[0:0]$4743 + attribute \src "issuer_ls180.v:119918.5-119918.29" + switch \initial + attribute \src "issuer_ls180.v:119918.9-119918.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\rst_l_r_rst$next[0:0]$4743 1'1 + case + assign $1\rst_l_r_rst$next[0:0]$4743 \rst_r + end + sync always + update \rst_l_r_rst$next $0\rst_l_r_rst$next[0:0]$4742 + end + attribute \src "issuer_ls180.v:119926.3-119934.6" + process $proc$issuer_ls180.v:119926$4744 + assign { } { } + assign { } { } + assign $0\opc_l_s_opc$next[0:0]$4745 $1\opc_l_s_opc$next[0:0]$4746 + attribute \src "issuer_ls180.v:119927.5-119927.29" + switch \initial + attribute \src "issuer_ls180.v:119927.9-119927.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\opc_l_s_opc$next[0:0]$4746 1'0 + case + assign $1\opc_l_s_opc$next[0:0]$4746 \cu_issue_i + end + sync always + update \opc_l_s_opc$next $0\opc_l_s_opc$next[0:0]$4745 + end + attribute \src "issuer_ls180.v:119935.3-119943.6" + process $proc$issuer_ls180.v:119935$4747 + assign { } { } + assign { } { } + assign $0\opc_l_r_opc$next[0:0]$4748 $1\opc_l_r_opc$next[0:0]$4749 + attribute \src "issuer_ls180.v:119936.5-119936.29" + switch \initial + attribute \src "issuer_ls180.v:119936.9-119936.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\opc_l_r_opc$next[0:0]$4749 1'1 + case + assign $1\opc_l_r_opc$next[0:0]$4749 \req_done + end + sync always + update \opc_l_r_opc$next $0\opc_l_r_opc$next[0:0]$4748 + end + attribute \src "issuer_ls180.v:119944.3-119952.6" + process $proc$issuer_ls180.v:119944$4750 + assign { } { } + assign { } { } + assign $0\src_l_s_src$next[2:0]$4751 $1\src_l_s_src$next[2:0]$4752 + attribute \src "issuer_ls180.v:119945.5-119945.29" + switch \initial + attribute \src "issuer_ls180.v:119945.9-119945.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\src_l_s_src$next[2:0]$4752 3'000 + case + assign $1\src_l_s_src$next[2:0]$4752 { \cu_issue_i \cu_issue_i \cu_issue_i } + end + sync always + update \src_l_s_src$next $0\src_l_s_src$next[2:0]$4751 + end + attribute \src "issuer_ls180.v:119953.3-119961.6" + process $proc$issuer_ls180.v:119953$4753 + assign { } { } + assign { } { } + assign $0\src_l_r_src$next[2:0]$4754 $1\src_l_r_src$next[2:0]$4755 + attribute \src "issuer_ls180.v:119954.5-119954.29" + switch \initial + attribute \src "issuer_ls180.v:119954.9-119954.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\src_l_r_src$next[2:0]$4755 3'111 + case + assign $1\src_l_r_src$next[2:0]$4755 \reset_r + end + sync always + update \src_l_r_src$next $0\src_l_r_src$next[2:0]$4754 + end + attribute \src "issuer_ls180.v:119962.3-119970.6" + process $proc$issuer_ls180.v:119962$4756 + assign { } { } + assign { } { } + assign $0\req_l_s_req$next[3:0]$4757 $1\req_l_s_req$next[3:0]$4758 + attribute \src "issuer_ls180.v:119963.5-119963.29" + switch \initial + attribute \src "issuer_ls180.v:119963.9-119963.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\req_l_s_req$next[3:0]$4758 4'0000 + case + assign $1\req_l_s_req$next[3:0]$4758 \$66 + end + sync always + update \req_l_s_req$next $0\req_l_s_req$next[3:0]$4757 + end + attribute \src "issuer_ls180.v:119971.3-119979.6" + process $proc$issuer_ls180.v:119971$4759 + assign { } { } + assign { } { } + assign $0\req_l_r_req$next[3:0]$4760 $1\req_l_r_req$next[3:0]$4761 + attribute \src "issuer_ls180.v:119972.5-119972.29" + switch \initial + attribute \src "issuer_ls180.v:119972.9-119972.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\req_l_r_req$next[3:0]$4761 4'1111 + case + assign $1\req_l_r_req$next[3:0]$4761 \$68 + end + sync always + update \req_l_r_req$next $0\req_l_r_req$next[3:0]$4760 + end + attribute \src "issuer_ls180.v:119980.3-120018.6" + process $proc$issuer_ls180.v:119980$4762 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\alu_div0_logical_op__data_len$next[3:0]$4763 $1\alu_div0_logical_op__data_len$next[3:0]$4781 + assign $0\alu_div0_logical_op__fn_unit$next[11:0]$4764 $1\alu_div0_logical_op__fn_unit$next[11:0]$4782 + assign { } { } + assign { } { } + assign $0\alu_div0_logical_op__input_carry$next[1:0]$4767 $1\alu_div0_logical_op__input_carry$next[1:0]$4785 + assign $0\alu_div0_logical_op__insn$next[31:0]$4768 $1\alu_div0_logical_op__insn$next[31:0]$4786 + assign $0\alu_div0_logical_op__insn_type$next[6:0]$4769 $1\alu_div0_logical_op__insn_type$next[6:0]$4787 + assign $0\alu_div0_logical_op__invert_in$next[0:0]$4770 $1\alu_div0_logical_op__invert_in$next[0:0]$4788 + assign $0\alu_div0_logical_op__invert_out$next[0:0]$4771 $1\alu_div0_logical_op__invert_out$next[0:0]$4789 + assign $0\alu_div0_logical_op__is_32bit$next[0:0]$4772 $1\alu_div0_logical_op__is_32bit$next[0:0]$4790 + assign $0\alu_div0_logical_op__is_signed$next[0:0]$4773 $1\alu_div0_logical_op__is_signed$next[0:0]$4791 + assign { } { } + assign { } { } + assign $0\alu_div0_logical_op__output_carry$next[0:0]$4776 $1\alu_div0_logical_op__output_carry$next[0:0]$4794 + assign { } { } + assign { } { } + assign $0\alu_div0_logical_op__write_cr0$next[0:0]$4779 $1\alu_div0_logical_op__write_cr0$next[0:0]$4797 + assign $0\alu_div0_logical_op__zero_a$next[0:0]$4780 $1\alu_div0_logical_op__zero_a$next[0:0]$4798 + assign $0\alu_div0_logical_op__imm_data__data$next[63:0]$4765 $2\alu_div0_logical_op__imm_data__data$next[63:0]$4799 + assign $0\alu_div0_logical_op__imm_data__ok$next[0:0]$4766 $2\alu_div0_logical_op__imm_data__ok$next[0:0]$4800 + assign $0\alu_div0_logical_op__oe__oe$next[0:0]$4774 $2\alu_div0_logical_op__oe__oe$next[0:0]$4801 + assign $0\alu_div0_logical_op__oe__ok$next[0:0]$4775 $2\alu_div0_logical_op__oe__ok$next[0:0]$4802 + assign $0\alu_div0_logical_op__rc__ok$next[0:0]$4777 $2\alu_div0_logical_op__rc__ok$next[0:0]$4803 + assign $0\alu_div0_logical_op__rc__rc$next[0:0]$4778 $2\alu_div0_logical_op__rc__rc$next[0:0]$4804 + attribute \src "issuer_ls180.v:119981.5-119981.29" + switch \initial + attribute \src "issuer_ls180.v:119981.9-119981.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:257" + switch \cu_issue_i + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { $1\alu_div0_logical_op__insn$next[31:0]$4786 $1\alu_div0_logical_op__data_len$next[3:0]$4781 $1\alu_div0_logical_op__is_signed$next[0:0]$4791 $1\alu_div0_logical_op__is_32bit$next[0:0]$4790 $1\alu_div0_logical_op__output_carry$next[0:0]$4794 $1\alu_div0_logical_op__write_cr0$next[0:0]$4797 $1\alu_div0_logical_op__invert_out$next[0:0]$4789 $1\alu_div0_logical_op__input_carry$next[1:0]$4785 $1\alu_div0_logical_op__zero_a$next[0:0]$4798 $1\alu_div0_logical_op__invert_in$next[0:0]$4788 $1\alu_div0_logical_op__oe__ok$next[0:0]$4793 $1\alu_div0_logical_op__oe__oe$next[0:0]$4792 $1\alu_div0_logical_op__rc__ok$next[0:0]$4795 $1\alu_div0_logical_op__rc__rc$next[0:0]$4796 $1\alu_div0_logical_op__imm_data__ok$next[0:0]$4784 $1\alu_div0_logical_op__imm_data__data$next[63:0]$4783 $1\alu_div0_logical_op__fn_unit$next[11:0]$4782 $1\alu_div0_logical_op__insn_type$next[6:0]$4787 } { \oper_i_alu_div0__insn \oper_i_alu_div0__data_len \oper_i_alu_div0__is_signed \oper_i_alu_div0__is_32bit \oper_i_alu_div0__output_carry \oper_i_alu_div0__write_cr0 \oper_i_alu_div0__invert_out \oper_i_alu_div0__input_carry \oper_i_alu_div0__zero_a \oper_i_alu_div0__invert_in \oper_i_alu_div0__oe__ok \oper_i_alu_div0__oe__oe \oper_i_alu_div0__rc__ok \oper_i_alu_div0__rc__rc \oper_i_alu_div0__imm_data__ok \oper_i_alu_div0__imm_data__data \oper_i_alu_div0__fn_unit \oper_i_alu_div0__insn_type } + case + assign $1\alu_div0_logical_op__data_len$next[3:0]$4781 \alu_div0_logical_op__data_len + assign $1\alu_div0_logical_op__fn_unit$next[11:0]$4782 \alu_div0_logical_op__fn_unit + assign $1\alu_div0_logical_op__imm_data__data$next[63:0]$4783 \alu_div0_logical_op__imm_data__data + assign $1\alu_div0_logical_op__imm_data__ok$next[0:0]$4784 \alu_div0_logical_op__imm_data__ok + assign $1\alu_div0_logical_op__input_carry$next[1:0]$4785 \alu_div0_logical_op__input_carry + assign $1\alu_div0_logical_op__insn$next[31:0]$4786 \alu_div0_logical_op__insn + assign $1\alu_div0_logical_op__insn_type$next[6:0]$4787 \alu_div0_logical_op__insn_type + assign $1\alu_div0_logical_op__invert_in$next[0:0]$4788 \alu_div0_logical_op__invert_in + assign $1\alu_div0_logical_op__invert_out$next[0:0]$4789 \alu_div0_logical_op__invert_out + assign $1\alu_div0_logical_op__is_32bit$next[0:0]$4790 \alu_div0_logical_op__is_32bit + assign $1\alu_div0_logical_op__is_signed$next[0:0]$4791 \alu_div0_logical_op__is_signed + assign $1\alu_div0_logical_op__oe__oe$next[0:0]$4792 \alu_div0_logical_op__oe__oe + assign $1\alu_div0_logical_op__oe__ok$next[0:0]$4793 \alu_div0_logical_op__oe__ok + assign $1\alu_div0_logical_op__output_carry$next[0:0]$4794 \alu_div0_logical_op__output_carry + assign $1\alu_div0_logical_op__rc__ok$next[0:0]$4795 \alu_div0_logical_op__rc__ok + assign $1\alu_div0_logical_op__rc__rc$next[0:0]$4796 \alu_div0_logical_op__rc__rc + assign $1\alu_div0_logical_op__write_cr0$next[0:0]$4797 \alu_div0_logical_op__write_cr0 + assign $1\alu_div0_logical_op__zero_a$next[0:0]$4798 \alu_div0_logical_op__zero_a + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $2\alu_div0_logical_op__imm_data__data$next[63:0]$4799 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\alu_div0_logical_op__imm_data__ok$next[0:0]$4800 1'0 + assign $2\alu_div0_logical_op__rc__rc$next[0:0]$4804 1'0 + assign $2\alu_div0_logical_op__rc__ok$next[0:0]$4803 1'0 + assign $2\alu_div0_logical_op__oe__oe$next[0:0]$4801 1'0 + assign $2\alu_div0_logical_op__oe__ok$next[0:0]$4802 1'0 + case + assign $2\alu_div0_logical_op__imm_data__data$next[63:0]$4799 $1\alu_div0_logical_op__imm_data__data$next[63:0]$4783 + assign $2\alu_div0_logical_op__imm_data__ok$next[0:0]$4800 $1\alu_div0_logical_op__imm_data__ok$next[0:0]$4784 + assign $2\alu_div0_logical_op__oe__oe$next[0:0]$4801 $1\alu_div0_logical_op__oe__oe$next[0:0]$4792 + assign $2\alu_div0_logical_op__oe__ok$next[0:0]$4802 $1\alu_div0_logical_op__oe__ok$next[0:0]$4793 + assign $2\alu_div0_logical_op__rc__ok$next[0:0]$4803 $1\alu_div0_logical_op__rc__ok$next[0:0]$4795 + assign $2\alu_div0_logical_op__rc__rc$next[0:0]$4804 $1\alu_div0_logical_op__rc__rc$next[0:0]$4796 + end + sync always + update \alu_div0_logical_op__data_len$next $0\alu_div0_logical_op__data_len$next[3:0]$4763 + update \alu_div0_logical_op__fn_unit$next $0\alu_div0_logical_op__fn_unit$next[11:0]$4764 + update \alu_div0_logical_op__imm_data__data$next $0\alu_div0_logical_op__imm_data__data$next[63:0]$4765 + update \alu_div0_logical_op__imm_data__ok$next $0\alu_div0_logical_op__imm_data__ok$next[0:0]$4766 + update \alu_div0_logical_op__input_carry$next $0\alu_div0_logical_op__input_carry$next[1:0]$4767 + update \alu_div0_logical_op__insn$next $0\alu_div0_logical_op__insn$next[31:0]$4768 + update \alu_div0_logical_op__insn_type$next $0\alu_div0_logical_op__insn_type$next[6:0]$4769 + update \alu_div0_logical_op__invert_in$next $0\alu_div0_logical_op__invert_in$next[0:0]$4770 + update \alu_div0_logical_op__invert_out$next $0\alu_div0_logical_op__invert_out$next[0:0]$4771 + update \alu_div0_logical_op__is_32bit$next $0\alu_div0_logical_op__is_32bit$next[0:0]$4772 + update \alu_div0_logical_op__is_signed$next $0\alu_div0_logical_op__is_signed$next[0:0]$4773 + update \alu_div0_logical_op__oe__oe$next $0\alu_div0_logical_op__oe__oe$next[0:0]$4774 + update \alu_div0_logical_op__oe__ok$next $0\alu_div0_logical_op__oe__ok$next[0:0]$4775 + update \alu_div0_logical_op__output_carry$next $0\alu_div0_logical_op__output_carry$next[0:0]$4776 + update \alu_div0_logical_op__rc__ok$next $0\alu_div0_logical_op__rc__ok$next[0:0]$4777 + update \alu_div0_logical_op__rc__rc$next $0\alu_div0_logical_op__rc__rc$next[0:0]$4778 + update \alu_div0_logical_op__write_cr0$next $0\alu_div0_logical_op__write_cr0$next[0:0]$4779 + update \alu_div0_logical_op__zero_a$next $0\alu_div0_logical_op__zero_a$next[0:0]$4780 + end + attribute \src "issuer_ls180.v:120019.3-120040.6" + process $proc$issuer_ls180.v:120019$4805 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\data_r0__o$next[63:0]$4806 $2\data_r0__o$next[63:0]$4810 + assign { } { } + assign $0\data_r0__o_ok$next[0:0]$4807 $3\data_r0__o_ok$next[0:0]$4812 + attribute \src "issuer_ls180.v:120020.5-120020.29" + switch \initial + attribute \src "issuer_ls180.v:120020.9-120020.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" + switch \alu_pulse + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $1\data_r0__o_ok$next[0:0]$4809 $1\data_r0__o$next[63:0]$4808 } { \o_ok \alu_div0_o } + case + assign $1\data_r0__o$next[63:0]$4808 \data_r0__o + assign $1\data_r0__o_ok$next[0:0]$4809 \data_r0__o_ok + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" + switch \cu_issue_i + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $2\data_r0__o_ok$next[0:0]$4811 $2\data_r0__o$next[63:0]$4810 } 65'00000000000000000000000000000000000000000000000000000000000000000 + case + assign $2\data_r0__o$next[63:0]$4810 $1\data_r0__o$next[63:0]$4808 + assign $2\data_r0__o_ok$next[0:0]$4811 $1\data_r0__o_ok$next[0:0]$4809 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\data_r0__o_ok$next[0:0]$4812 1'0 + case + assign $3\data_r0__o_ok$next[0:0]$4812 $2\data_r0__o_ok$next[0:0]$4811 + end + sync always + update \data_r0__o$next $0\data_r0__o$next[63:0]$4806 + update \data_r0__o_ok$next $0\data_r0__o_ok$next[0:0]$4807 + end + attribute \src "issuer_ls180.v:120041.3-120062.6" + process $proc$issuer_ls180.v:120041$4813 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\data_r1__cr_a$next[3:0]$4814 $2\data_r1__cr_a$next[3:0]$4818 + assign { } { } + assign $0\data_r1__cr_a_ok$next[0:0]$4815 $3\data_r1__cr_a_ok$next[0:0]$4820 + attribute \src "issuer_ls180.v:120042.5-120042.29" + switch \initial + attribute \src "issuer_ls180.v:120042.9-120042.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" + switch \alu_pulse + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $1\data_r1__cr_a_ok$next[0:0]$4817 $1\data_r1__cr_a$next[3:0]$4816 } { \cr_a_ok \alu_div0_cr_a } + case + assign $1\data_r1__cr_a$next[3:0]$4816 \data_r1__cr_a + assign $1\data_r1__cr_a_ok$next[0:0]$4817 \data_r1__cr_a_ok + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" + switch \cu_issue_i + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $2\data_r1__cr_a_ok$next[0:0]$4819 $2\data_r1__cr_a$next[3:0]$4818 } 5'00000 + case + assign $2\data_r1__cr_a$next[3:0]$4818 $1\data_r1__cr_a$next[3:0]$4816 + assign $2\data_r1__cr_a_ok$next[0:0]$4819 $1\data_r1__cr_a_ok$next[0:0]$4817 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\data_r1__cr_a_ok$next[0:0]$4820 1'0 + case + assign $3\data_r1__cr_a_ok$next[0:0]$4820 $2\data_r1__cr_a_ok$next[0:0]$4819 + end + sync always + update \data_r1__cr_a$next $0\data_r1__cr_a$next[3:0]$4814 + update \data_r1__cr_a_ok$next $0\data_r1__cr_a_ok$next[0:0]$4815 + end + attribute \src "issuer_ls180.v:120063.3-120084.6" + process $proc$issuer_ls180.v:120063$4821 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\data_r2__xer_ov$next[1:0]$4822 $2\data_r2__xer_ov$next[1:0]$4826 + assign { } { } + assign $0\data_r2__xer_ov_ok$next[0:0]$4823 $3\data_r2__xer_ov_ok$next[0:0]$4828 + attribute \src "issuer_ls180.v:120064.5-120064.29" + switch \initial + attribute \src "issuer_ls180.v:120064.9-120064.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" + switch \alu_pulse + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $1\data_r2__xer_ov_ok$next[0:0]$4825 $1\data_r2__xer_ov$next[1:0]$4824 } { \xer_ov_ok \alu_div0_xer_ov } + case + assign $1\data_r2__xer_ov$next[1:0]$4824 \data_r2__xer_ov + assign $1\data_r2__xer_ov_ok$next[0:0]$4825 \data_r2__xer_ov_ok + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" + switch \cu_issue_i + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $2\data_r2__xer_ov_ok$next[0:0]$4827 $2\data_r2__xer_ov$next[1:0]$4826 } 3'000 + case + assign $2\data_r2__xer_ov$next[1:0]$4826 $1\data_r2__xer_ov$next[1:0]$4824 + assign $2\data_r2__xer_ov_ok$next[0:0]$4827 $1\data_r2__xer_ov_ok$next[0:0]$4825 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\data_r2__xer_ov_ok$next[0:0]$4828 1'0 + case + assign $3\data_r2__xer_ov_ok$next[0:0]$4828 $2\data_r2__xer_ov_ok$next[0:0]$4827 + end + sync always + update \data_r2__xer_ov$next $0\data_r2__xer_ov$next[1:0]$4822 + update \data_r2__xer_ov_ok$next $0\data_r2__xer_ov_ok$next[0:0]$4823 + end + attribute \src "issuer_ls180.v:120085.3-120106.6" + process $proc$issuer_ls180.v:120085$4829 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\data_r3__xer_so$next[0:0]$4830 $2\data_r3__xer_so$next[0:0]$4834 + assign { } { } + assign $0\data_r3__xer_so_ok$next[0:0]$4831 $3\data_r3__xer_so_ok$next[0:0]$4836 + attribute \src "issuer_ls180.v:120086.5-120086.29" + switch \initial + attribute \src "issuer_ls180.v:120086.9-120086.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" + switch \alu_pulse + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $1\data_r3__xer_so_ok$next[0:0]$4833 $1\data_r3__xer_so$next[0:0]$4832 } { \xer_so_ok \alu_div0_xer_so } + case + assign $1\data_r3__xer_so$next[0:0]$4832 \data_r3__xer_so + assign $1\data_r3__xer_so_ok$next[0:0]$4833 \data_r3__xer_so_ok + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" + switch \cu_issue_i + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $2\data_r3__xer_so_ok$next[0:0]$4835 $2\data_r3__xer_so$next[0:0]$4834 } 2'00 + case + assign $2\data_r3__xer_so$next[0:0]$4834 $1\data_r3__xer_so$next[0:0]$4832 + assign $2\data_r3__xer_so_ok$next[0:0]$4835 $1\data_r3__xer_so_ok$next[0:0]$4833 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\data_r3__xer_so_ok$next[0:0]$4836 1'0 + case + assign $3\data_r3__xer_so_ok$next[0:0]$4836 $2\data_r3__xer_so_ok$next[0:0]$4835 + end + sync always + update \data_r3__xer_so$next $0\data_r3__xer_so$next[0:0]$4830 + update \data_r3__xer_so_ok$next $0\data_r3__xer_so_ok$next[0:0]$4831 + end + attribute \src "issuer_ls180.v:120107.3-120116.6" + process $proc$issuer_ls180.v:120107$4837 + assign { } { } + assign { } { } + assign $0\src_r0$next[63:0]$4838 $1\src_r0$next[63:0]$4839 + attribute \src "issuer_ls180.v:120108.5-120108.29" + switch \initial + attribute \src "issuer_ls180.v:120108.9-120108.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" + switch \src_sel + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\src_r0$next[63:0]$4839 \src_or_imm + case + assign $1\src_r0$next[63:0]$4839 \src_r0 + end + sync always + update \src_r0$next $0\src_r0$next[63:0]$4838 + end + attribute \src "issuer_ls180.v:120117.3-120126.6" + process $proc$issuer_ls180.v:120117$4840 + assign { } { } + assign { } { } + assign $0\src_r1$next[63:0]$4841 $1\src_r1$next[63:0]$4842 + attribute \src "issuer_ls180.v:120118.5-120118.29" + switch \initial + attribute \src "issuer_ls180.v:120118.9-120118.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" + switch \src_sel$82 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\src_r1$next[63:0]$4842 \src_or_imm$85 + case + assign $1\src_r1$next[63:0]$4842 \src_r1 + end + sync always + update \src_r1$next $0\src_r1$next[63:0]$4841 + end + attribute \src "issuer_ls180.v:120127.3-120136.6" + process $proc$issuer_ls180.v:120127$4843 + assign { } { } + assign { } { } + assign $0\src_r2$next[0:0]$4844 $1\src_r2$next[0:0]$4845 + attribute \src "issuer_ls180.v:120128.5-120128.29" + switch \initial + attribute \src "issuer_ls180.v:120128.9-120128.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" + switch \src_l_q_src [2] + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\src_r2$next[0:0]$4845 \src3_i + case + assign $1\src_r2$next[0:0]$4845 \src_r2 + end + sync always + update \src_r2$next $0\src_r2$next[0:0]$4844 + end + attribute \src "issuer_ls180.v:120137.3-120145.6" + process $proc$issuer_ls180.v:120137$4846 + assign { } { } + assign { } { } + assign $0\alui_l_r_alui$next[0:0]$4847 $1\alui_l_r_alui$next[0:0]$4848 + attribute \src "issuer_ls180.v:120138.5-120138.29" + switch \initial + attribute \src "issuer_ls180.v:120138.9-120138.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\alui_l_r_alui$next[0:0]$4848 1'1 + case + assign $1\alui_l_r_alui$next[0:0]$4848 \$94 + end + sync always + update \alui_l_r_alui$next $0\alui_l_r_alui$next[0:0]$4847 + end + attribute \src "issuer_ls180.v:120146.3-120154.6" + process $proc$issuer_ls180.v:120146$4849 + assign { } { } + assign { } { } + assign $0\alu_l_r_alu$next[0:0]$4850 $1\alu_l_r_alu$next[0:0]$4851 + attribute \src "issuer_ls180.v:120147.5-120147.29" + switch \initial + attribute \src "issuer_ls180.v:120147.9-120147.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\alu_l_r_alu$next[0:0]$4851 1'1 + case + assign $1\alu_l_r_alu$next[0:0]$4851 \$96 + end + sync always + update \alu_l_r_alu$next $0\alu_l_r_alu$next[0:0]$4850 + end + attribute \src "issuer_ls180.v:120155.3-120164.6" + process $proc$issuer_ls180.v:120155$4852 + assign { } { } + assign { } { } + assign $0\dest1_o[63:0] $1\dest1_o[63:0] + attribute \src "issuer_ls180.v:120156.5-120156.29" + switch \initial + attribute \src "issuer_ls180.v:120156.9-120156.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" + switch \$122 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dest1_o[63:0] \data_r0__o + case + assign $1\dest1_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \dest1_o $0\dest1_o[63:0] + end + attribute \src "issuer_ls180.v:120165.3-120174.6" + process $proc$issuer_ls180.v:120165$4853 + assign { } { } + assign { } { } + assign $0\dest2_o[3:0] $1\dest2_o[3:0] + attribute \src "issuer_ls180.v:120166.5-120166.29" + switch \initial + attribute \src "issuer_ls180.v:120166.9-120166.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" + switch \$124 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dest2_o[3:0] \data_r1__cr_a + case + assign $1\dest2_o[3:0] 4'0000 + end + sync always + update \dest2_o $0\dest2_o[3:0] + end + attribute \src "issuer_ls180.v:120175.3-120184.6" + process $proc$issuer_ls180.v:120175$4854 + assign { } { } + assign { } { } + assign $0\dest3_o[1:0] $1\dest3_o[1:0] + attribute \src "issuer_ls180.v:120176.5-120176.29" + switch \initial + attribute \src "issuer_ls180.v:120176.9-120176.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" + switch \$126 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dest3_o[1:0] \data_r2__xer_ov + case + assign $1\dest3_o[1:0] 2'00 + end + sync always + update \dest3_o $0\dest3_o[1:0] + end + attribute \src "issuer_ls180.v:120185.3-120194.6" + process $proc$issuer_ls180.v:120185$4855 + assign { } { } + assign { } { } + assign $0\dest4_o[0:0] $1\dest4_o[0:0] + attribute \src "issuer_ls180.v:120186.5-120186.29" + switch \initial + attribute \src "issuer_ls180.v:120186.9-120186.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" + switch \$128 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dest4_o[0:0] \data_r3__xer_so + case + assign $1\dest4_o[0:0] 1'0 + end + sync always + update \dest4_o $0\dest4_o[0:0] + end + attribute \src "issuer_ls180.v:120195.3-120203.6" + process $proc$issuer_ls180.v:120195$4856 + assign { } { } + assign { } { } + assign $0\prev_wr_go$next[3:0]$4857 $1\prev_wr_go$next[3:0]$4858 + attribute \src "issuer_ls180.v:120196.5-120196.29" + switch \initial + attribute \src "issuer_ls180.v:120196.9-120196.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\prev_wr_go$next[3:0]$4858 4'0000 + case + assign $1\prev_wr_go$next[3:0]$4858 \$20 + end + sync always + update \prev_wr_go$next $0\prev_wr_go$next[3:0]$4857 + end + connect \$100 $not$issuer_ls180.v:119644$4624_Y + connect \$102 $not$issuer_ls180.v:119645$4625_Y + connect \$104 $and$issuer_ls180.v:119646$4626_Y + connect \$106 $not$issuer_ls180.v:119647$4627_Y + connect \$108 $and$issuer_ls180.v:119648$4628_Y + connect \$10 $and$issuer_ls180.v:119649$4629_Y + connect \$110 $and$issuer_ls180.v:119650$4630_Y + connect \$112 $and$issuer_ls180.v:119651$4631_Y + connect \$114 $and$issuer_ls180.v:119652$4632_Y + connect \$116 $and$issuer_ls180.v:119653$4633_Y + connect \$118 $and$issuer_ls180.v:119654$4634_Y + connect \$120 $and$issuer_ls180.v:119655$4635_Y + connect \$122 $and$issuer_ls180.v:119656$4636_Y + connect \$124 $and$issuer_ls180.v:119657$4637_Y + connect \$126 $and$issuer_ls180.v:119658$4638_Y + connect \$128 $and$issuer_ls180.v:119659$4639_Y + connect \$12 $not$issuer_ls180.v:119660$4640_Y + connect \$14 $and$issuer_ls180.v:119661$4641_Y + connect \$16 $not$issuer_ls180.v:119662$4642_Y + connect \$18 $and$issuer_ls180.v:119663$4643_Y + connect \$20 $and$issuer_ls180.v:119664$4644_Y + connect \$24 $not$issuer_ls180.v:119665$4645_Y + connect \$26 $and$issuer_ls180.v:119666$4646_Y + connect \$23 $reduce_or$issuer_ls180.v:119667$4647_Y + connect \$22 $not$issuer_ls180.v:119668$4648_Y + connect \$2 $and$issuer_ls180.v:119669$4649_Y + connect \$30 $and$issuer_ls180.v:119670$4650_Y + connect \$32 $reduce_or$issuer_ls180.v:119671$4651_Y + connect \$34 $reduce_or$issuer_ls180.v:119672$4652_Y + connect \$36 $or$issuer_ls180.v:119673$4653_Y + connect \$38 $not$issuer_ls180.v:119674$4654_Y + connect \$40 $and$issuer_ls180.v:119675$4655_Y + connect \$42 $and$issuer_ls180.v:119676$4656_Y + connect \$44 $eq$issuer_ls180.v:119677$4657_Y + connect \$46 $and$issuer_ls180.v:119678$4658_Y + connect \$48 $eq$issuer_ls180.v:119679$4659_Y + connect \$50 $and$issuer_ls180.v:119680$4660_Y + connect \$52 $and$issuer_ls180.v:119681$4661_Y + connect \$54 $and$issuer_ls180.v:119682$4662_Y + connect \$56 $or$issuer_ls180.v:119683$4663_Y + connect \$58 $or$issuer_ls180.v:119684$4664_Y + connect \$5 $not$issuer_ls180.v:119685$4665_Y + connect \$60 $or$issuer_ls180.v:119686$4666_Y + connect \$62 $or$issuer_ls180.v:119687$4667_Y + connect \$64 $and$issuer_ls180.v:119688$4668_Y + connect \$66 $and$issuer_ls180.v:119689$4669_Y + connect \$68 $or$issuer_ls180.v:119690$4670_Y + connect \$70 $and$issuer_ls180.v:119691$4671_Y + connect \$72 $and$issuer_ls180.v:119692$4672_Y + connect \$74 $and$issuer_ls180.v:119693$4673_Y + connect \$76 $and$issuer_ls180.v:119694$4674_Y + connect \$78 $ternary$issuer_ls180.v:119695$4675_Y + connect \$7 $or$issuer_ls180.v:119696$4676_Y + connect \$80 $ternary$issuer_ls180.v:119697$4677_Y + connect \$83 $ternary$issuer_ls180.v:119698$4678_Y + connect \$86 $ternary$issuer_ls180.v:119699$4679_Y + connect \$88 $ternary$issuer_ls180.v:119700$4680_Y + connect \$4 $reduce_and$issuer_ls180.v:119701$4681_Y + connect \$90 $ternary$issuer_ls180.v:119702$4682_Y + connect \$92 $ternary$issuer_ls180.v:119703$4683_Y + connect \$94 $and$issuer_ls180.v:119704$4684_Y + connect \$96 $and$issuer_ls180.v:119705$4685_Y + connect \$98 $and$issuer_ls180.v:119706$4686_Y + connect \cu_go_die_i 1'0 + connect \cu_shadown_i 1'1 + connect \cu_wr__rel_o \$120 + connect \cu_rd__rel_o \$108 + connect \cu_busy_o \opc_l_q_opc + connect \alu_l_s_alu \all_rd_pulse + connect \alu_div0_n_ready_i \alu_l_q_alu + connect \alui_l_s_alui \all_rd_pulse + connect \alu_div0_p_valid_i \alui_l_q_alui + connect \alu_div0_xer_so$1 \$92 + connect \alu_div0_rb \$90 + connect \alu_div0_ra \$88 + connect \src_or_imm$85 \$86 + connect \src_sel$82 \$83 + connect \src_or_imm \$80 + connect \src_sel \$78 + connect \cu_wrmask_o { \$76 \$74 \$72 \$70 } + connect \reset_r \$62 + connect \reset_w \$60 + connect \rst_r \$58 + connect \reset \$56 + connect \wr_any \$36 + connect \cu_done_o \$30 + connect \alu_pulsem { \alu_pulse \alu_pulse \alu_pulse \alu_pulse } + connect \alu_pulse \alu_done_rise + connect \alu_done_rise \$18 + connect \alu_done_dly$next \alu_done + connect \alu_done \alu_div0_n_valid_o + connect \all_rd_pulse \all_rd_rise + connect \all_rd_rise \$14 + connect \all_rd_dly$next \all_rd + connect \all_rd \$10 +end +attribute \src "issuer_ls180.v:120240.1-120249.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_0.div_state_init" +attribute \generator "nMigen" +module \div_state_init + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:89" + wire width 128 input 3 \dividend + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:105" + wire width 128 output 2 \o_dividend_quotient + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:103" + wire width 7 output 1 \o_q_bits_known + connect \o_dividend_quotient \dividend + connect \o_q_bits_known 7'0000000 +end +attribute \src "issuer_ls180.v:120253.1-120335.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_0.div_state_next" +attribute \generator "nMigen" +module \div_state_next + attribute \src "issuer_ls180.v:120254.7-120254.20" + wire $0\initial[0:0] + attribute \src "issuer_ls180.v:120319.3-120330.6" + wire width 128 $0\o_dividend_quotient[127:0] + attribute \src "issuer_ls180.v:120307.3-120318.6" + wire width 7 $0\o_q_bits_known[6:0] + attribute \src "issuer_ls180.v:120295.3-120306.6" + wire width 128 $0\value[127:0] + attribute \src "issuer_ls180.v:120319.3-120330.6" + wire width 128 $1\o_dividend_quotient[127:0] + attribute \src "issuer_ls180.v:120307.3-120318.6" + wire width 7 $1\o_q_bits_known[6:0] + attribute \src "issuer_ls180.v:120295.3-120306.6" + wire width 128 $1\value[127:0] + attribute \src "issuer_ls180.v:120289.18-120289.106" + wire width 8 $add$issuer_ls180.v:120289$4904_Y + attribute \src "issuer_ls180.v:120290.18-120290.109" + wire $eq$issuer_ls180.v:120290$4905_Y + attribute \src "issuer_ls180.v:120294.17-120294.108" + wire $eq$issuer_ls180.v:120294$4909_Y + attribute \src "issuer_ls180.v:120293.17-120293.101" + wire $not$issuer_ls180.v:120293$4908_Y + attribute \src "issuer_ls180.v:120291.17-120291.101" + wire width 127 $sshl$issuer_ls180.v:120291$4906_Y + attribute \src "issuer_ls180.v:120292.17-120292.109" + wire width 129 $sub$issuer_ls180.v:120292$4907_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:67" + wire width 129 \$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:81" + wire width 8 \$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:81" + wire width 8 \$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:109" + wire \$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:67" + wire width 127 \$2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:67" + wire width 129 \$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:70" + wire \$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:109" + wire \$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:64" + wire width 128 \difference + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:59" + wire width 64 input 4 \divisor + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:105" + wire width 128 input 3 \i_dividend_quotient + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:103" + wire width 7 input 2 \i_q_bits_known + attribute \src "issuer_ls180.v:120254.7-120254.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:68" + wire \next_quotient_bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:105" + wire width 128 output 5 \o_dividend_quotient + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:103" + wire width 7 output 1 \o_q_bits_known + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:71" + wire width 128 \value + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:81" + cell $add $add$issuer_ls180.v:120289$4904 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 8 + connect \A \i_q_bits_known + connect \B 1'1 + connect \Y $add$issuer_ls180.v:120289$4904_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:109" + cell $eq $eq$issuer_ls180.v:120290$4905 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \i_q_bits_known + connect \B 7'1000000 + connect \Y $eq$issuer_ls180.v:120290$4905_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:109" + cell $eq $eq$issuer_ls180.v:120294$4909 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \i_q_bits_known + connect \B 7'1000000 + connect \Y $eq$issuer_ls180.v:120294$4909_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:70" + cell $not $not$issuer_ls180.v:120293$4908 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \difference [127] + connect \Y $not$issuer_ls180.v:120293$4908_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:67" + cell $sshl $sshl$issuer_ls180.v:120291$4906 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 127 + connect \A \divisor + connect \B 6'111111 + connect \Y $sshl$issuer_ls180.v:120291$4906_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:67" + cell $sub $sub$issuer_ls180.v:120292$4907 + parameter \A_SIGNED 0 + parameter \A_WIDTH 128 + parameter \B_SIGNED 0 + parameter \B_WIDTH 127 + parameter \Y_WIDTH 129 + connect \A \i_dividend_quotient + connect \B \$2 + connect \Y $sub$issuer_ls180.v:120292$4907_Y + end + attribute \src "issuer_ls180.v:120254.7-120254.20" + process $proc$issuer_ls180.v:120254$4913 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "issuer_ls180.v:120295.3-120306.6" + process $proc$issuer_ls180.v:120295$4910 + assign { } { } + assign $0\value[127:0] $1\value[127:0] + attribute \src "issuer_ls180.v:120296.5-120296.29" + switch \initial + attribute \src "issuer_ls180.v:120296.9-120296.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:72" + switch \next_quotient_bit + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\value[127:0] \difference + attribute \src "issuer_ls180.v:0.0-0.0" + case + assign { } { } + assign $1\value[127:0] \i_dividend_quotient + end + sync always + update \value $0\value[127:0] + end + attribute \src "issuer_ls180.v:120307.3-120318.6" + process $proc$issuer_ls180.v:120307$4911 + assign { } { } + assign $0\o_q_bits_known[6:0] $1\o_q_bits_known[6:0] + attribute \src "issuer_ls180.v:120308.5-120308.29" + switch \initial + attribute \src "issuer_ls180.v:120308.9-120308.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:77" + switch \$8 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\o_q_bits_known[6:0] \i_q_bits_known + attribute \src "issuer_ls180.v:0.0-0.0" + case + assign { } { } + assign $1\o_q_bits_known[6:0] \$10 [6:0] + end + sync always + update \o_q_bits_known $0\o_q_bits_known[6:0] + end + attribute \src "issuer_ls180.v:120319.3-120330.6" + process $proc$issuer_ls180.v:120319$4912 + assign { } { } + assign $0\o_dividend_quotient[127:0] $1\o_dividend_quotient[127:0] + attribute \src "issuer_ls180.v:120320.5-120320.29" + switch \initial + attribute \src "issuer_ls180.v:120320.9-120320.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:77" + switch \$13 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\o_dividend_quotient[127:0] \i_dividend_quotient + attribute \src "issuer_ls180.v:0.0-0.0" + case + assign { } { } + assign $1\o_dividend_quotient[127:0] { \value [126:0] \next_quotient_bit } + end + sync always + update \o_dividend_quotient $0\o_dividend_quotient[127:0] + end + connect \$11 $add$issuer_ls180.v:120289$4904_Y + connect \$13 $eq$issuer_ls180.v:120290$4905_Y + connect \$2 $sshl$issuer_ls180.v:120291$4906_Y + connect \$4 $sub$issuer_ls180.v:120292$4907_Y + connect \$6 $not$issuer_ls180.v:120293$4908_Y + connect \$8 $eq$issuer_ls180.v:120294$4909_Y + connect \$1 \$4 + connect \$10 \$11 + connect \next_quotient_bit \$6 + connect \difference \$4 [127:0] +end +attribute \src "issuer_ls180.v:120339.1-120510.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.fast" +attribute \generator "nMigen" +module \fast + attribute \src "issuer_ls180.v:120434.3-120440.6" + wire width 3 $0$memwr$\memory$issuer_ls180.v:120438$4922_ADDR[2:0]$4930 + attribute \src "issuer_ls180.v:120434.3-120440.6" + wire width 64 $0$memwr$\memory$issuer_ls180.v:120438$4922_DATA[63:0]$4931 + attribute \src "issuer_ls180.v:120434.3-120440.6" + wire width 64 $0$memwr$\memory$issuer_ls180.v:120438$4922_EN[63:0]$4932 + attribute \src "issuer_ls180.v:120434.3-120440.6" + wire width 3 $0$memwr$\memory$issuer_ls180.v:120439$4923_ADDR[2:0]$4933 + attribute \src "issuer_ls180.v:120434.3-120440.6" + wire width 64 $0$memwr$\memory$issuer_ls180.v:120439$4923_DATA[63:0]$4934 + attribute \src "issuer_ls180.v:120434.3-120440.6" + wire width 64 $0$memwr$\memory$issuer_ls180.v:120439$4923_EN[63:0]$4935 + attribute \src "issuer_ls180.v:120434.3-120440.6" + wire width 3 $0\_0_[2:0] + attribute \src "issuer_ls180.v:120434.3-120440.6" + wire width 3 $0\_1_[2:0] + attribute \src "issuer_ls180.v:120434.3-120440.6" + wire width 3 $0\_2_[2:0] + attribute \src "issuer_ls180.v:120340.7-120340.20" + wire $0\initial[0:0] + attribute \src "issuer_ls180.v:120491.3-120500.6" + wire width 64 $0\issue__data_o[63:0] + attribute \src "issuer_ls180.v:120463.3-120471.6" + wire $0\ren_delay$10$next[0:0]$4944 + attribute \src "issuer_ls180.v:120416.3-120417.43" + wire $0\ren_delay$10[0:0]$4927 + attribute \src "issuer_ls180.v:120391.7-120391.28" + wire $0\ren_delay$10[0:0]$4964 + attribute \src "issuer_ls180.v:120482.3-120490.6" + wire $0\ren_delay$11$next[0:0]$4948 + attribute \src "issuer_ls180.v:120414.3-120415.43" + wire $0\ren_delay$11[0:0]$4925 + attribute \src "issuer_ls180.v:120395.7-120395.28" + wire $0\ren_delay$11[0:0]$4966 + attribute \src "issuer_ls180.v:120444.3-120452.6" + wire $0\ren_delay$next[0:0]$4940 + attribute \src "issuer_ls180.v:120418.3-120419.35" + wire $0\ren_delay[0:0] + attribute \src "issuer_ls180.v:120453.3-120462.6" + wire width 64 $0\src1__data_o[63:0] + attribute \src "issuer_ls180.v:120472.3-120481.6" + wire width 64 $0\src2__data_o[63:0] + attribute \src "issuer_ls180.v:120491.3-120500.6" + wire width 64 $1\issue__data_o[63:0] + attribute \src "issuer_ls180.v:120463.3-120471.6" + wire $1\ren_delay$10$next[0:0]$4945 + attribute \src "issuer_ls180.v:120482.3-120490.6" + wire $1\ren_delay$11$next[0:0]$4949 + attribute \src "issuer_ls180.v:120444.3-120452.6" + wire $1\ren_delay$next[0:0]$4941 + attribute \src "issuer_ls180.v:120389.7-120389.23" + wire $1\ren_delay[0:0] + attribute \src "issuer_ls180.v:120453.3-120462.6" + wire width 64 $1\src1__data_o[63:0] + attribute \src "issuer_ls180.v:120472.3-120481.6" + wire width 64 $1\src2__data_o[63:0] + attribute \src "issuer_ls180.v:120441.26-120441.32" + wire width 64 $memrd$\memory$issuer_ls180.v:120441$4936_DATA + attribute \src "issuer_ls180.v:120442.30-120442.36" + wire width 64 $memrd$\memory$issuer_ls180.v:120442$4937_DATA + attribute \src "issuer_ls180.v:120443.30-120443.36" + wire width 64 $memrd$\memory$issuer_ls180.v:120443$4938_DATA + attribute \src "issuer_ls180.v:0.0-0.0" + wire width 3 $memwr$\memory$issuer_ls180.v:120438$4922_ADDR + attribute \src "issuer_ls180.v:0.0-0.0" + wire width 64 $memwr$\memory$issuer_ls180.v:120438$4922_DATA + attribute \src "issuer_ls180.v:0.0-0.0" + wire width 64 $memwr$\memory$issuer_ls180.v:120438$4922_EN + attribute \src "issuer_ls180.v:0.0-0.0" + wire width 3 $memwr$\memory$issuer_ls180.v:120439$4923_ADDR + attribute \src "issuer_ls180.v:0.0-0.0" + wire width 64 $memwr$\memory$issuer_ls180.v:120439$4923_DATA + attribute \src "issuer_ls180.v:0.0-0.0" + wire width 64 $memwr$\memory$issuer_ls180.v:120439$4923_EN + attribute \src "issuer_ls180.v:120431.13-120431.16" + wire width 3 \_0_ + attribute \src "issuer_ls180.v:120432.13-120432.16" + wire width 3 \_1_ + attribute \src "issuer_ls180.v:120433.13-120433.16" + wire width 3 \_2_ + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" + wire input 17 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" + wire input 16 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 3 input 14 \dest1__addr + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 64 input 13 \dest1__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire input 15 \dest1__wen + attribute \src "issuer_ls180.v:120340.7-120340.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 3 input 1 \issue__addr + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 3 input 4 \issue__addr$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 64 input 6 \issue__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 64 output 3 \issue__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire input 2 \issue__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire input 5 \issue__wen + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:210" + wire width 3 \memory_r_addr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:210" + wire width 3 \memory_r_addr$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:210" + wire width 3 \memory_r_addr$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:210" + wire width 64 \memory_r_data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:210" + wire width 64 \memory_r_data$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:210" + wire width 64 \memory_r_data$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:218" + wire width 3 \memory_w_addr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:218" + wire width 3 \memory_w_addr$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:218" + wire width 64 \memory_w_data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:218" + wire width 64 \memory_w_data$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:218" + wire \memory_w_en + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:218" + wire \memory_w_en$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:243" + wire \ren_delay + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:243" + wire \ren_delay$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:243" + wire \ren_delay$10$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:243" + wire \ren_delay$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:243" + wire \ren_delay$11$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:243" + wire \ren_delay$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 3 input 8 \src1__addr + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 64 output 7 \src1__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire input 9 \src1__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 3 input 11 \src2__addr + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 64 output 10 \src2__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire input 12 \src2__ren + attribute \src "issuer_ls180.v:120420.14-120420.20" + memory width 64 size 8 \memory + attribute \src "issuer_ls180.v:0.0-0.0" + cell $meminit $meminit$\memory$issuer_ls180.v:0$4951 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 4951 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 0 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "issuer_ls180.v:0.0-0.0" + cell $meminit $meminit$\memory$issuer_ls180.v:0$4952 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 4952 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 1 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "issuer_ls180.v:0.0-0.0" + cell $meminit $meminit$\memory$issuer_ls180.v:0$4953 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 4953 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 2 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "issuer_ls180.v:0.0-0.0" + cell $meminit $meminit$\memory$issuer_ls180.v:0$4954 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 4954 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 3 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "issuer_ls180.v:0.0-0.0" + cell $meminit $meminit$\memory$issuer_ls180.v:0$4955 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 4955 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 4 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "issuer_ls180.v:0.0-0.0" + cell $meminit $meminit$\memory$issuer_ls180.v:0$4956 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 4956 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 5 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "issuer_ls180.v:0.0-0.0" + cell $meminit $meminit$\memory$issuer_ls180.v:0$4957 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 4957 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 6 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "issuer_ls180.v:0.0-0.0" + cell $meminit $meminit$\memory$issuer_ls180.v:0$4958 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 4958 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 7 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "issuer_ls180.v:120441.26-120441.32" + cell $memrd $memrd$\memory$issuer_ls180.v:120441$4936 + parameter \ABITS 3 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\memory" + parameter \TRANSPARENT 0 + parameter \WIDTH 64 + connect \ADDR \_0_ + connect \CLK 1'x + connect \DATA $memrd$\memory$issuer_ls180.v:120441$4936_DATA + connect \EN 1'x + end + attribute \src "issuer_ls180.v:120442.30-120442.36" + cell $memrd $memrd$\memory$issuer_ls180.v:120442$4937 + parameter \ABITS 3 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\memory" + parameter \TRANSPARENT 0 + parameter \WIDTH 64 + connect \ADDR \_1_ + connect \CLK 1'x + connect \DATA $memrd$\memory$issuer_ls180.v:120442$4937_DATA + connect \EN 1'x + end + attribute \src "issuer_ls180.v:120443.30-120443.36" + cell $memrd $memrd$\memory$issuer_ls180.v:120443$4938 + parameter \ABITS 3 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\memory" + parameter \TRANSPARENT 0 + parameter \WIDTH 64 + connect \ADDR \_2_ + connect \CLK 1'x + connect \DATA $memrd$\memory$issuer_ls180.v:120443$4938_DATA + connect \EN 1'x + end + attribute \src "issuer_ls180.v:0.0-0.0" + cell $memwr $memwr$\memory$issuer_ls180.v:0$4959 + parameter \ABITS 3 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\memory" + parameter \PRIORITY 4959 + parameter \WIDTH 64 + connect \ADDR $memwr$\memory$issuer_ls180.v:120438$4922_ADDR + connect \CLK 1'x + connect \DATA $memwr$\memory$issuer_ls180.v:120438$4922_DATA + connect \EN $memwr$\memory$issuer_ls180.v:120438$4922_EN + end + attribute \src "issuer_ls180.v:0.0-0.0" + cell $memwr $memwr$\memory$issuer_ls180.v:0$4960 + parameter \ABITS 3 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\memory" + parameter \PRIORITY 4960 + parameter \WIDTH 64 + connect \ADDR $memwr$\memory$issuer_ls180.v:120439$4923_ADDR + connect \CLK 1'x + connect \DATA $memwr$\memory$issuer_ls180.v:120439$4923_DATA + connect \EN $memwr$\memory$issuer_ls180.v:120439$4923_EN + end + attribute \src "issuer_ls180.v:0.0-0.0" + process $proc$issuer_ls180.v:0$4967 + sync always + sync init + end + attribute \src "issuer_ls180.v:120340.7-120340.20" + process $proc$issuer_ls180.v:120340$4961 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "issuer_ls180.v:120389.7-120389.23" + process $proc$issuer_ls180.v:120389$4962 + assign { } { } + assign $1\ren_delay[0:0] 1'0 + sync always + sync init + update \ren_delay $1\ren_delay[0:0] + end + attribute \src "issuer_ls180.v:120391.7-120391.28" + process $proc$issuer_ls180.v:120391$4963 + assign { } { } + assign $0\ren_delay$10[0:0]$4964 1'0 + sync always + sync init + update \ren_delay$10 $0\ren_delay$10[0:0]$4964 + end + attribute \src "issuer_ls180.v:120395.7-120395.28" + process $proc$issuer_ls180.v:120395$4965 + assign { } { } + assign $0\ren_delay$11[0:0]$4966 1'0 + sync always + sync init + update \ren_delay$11 $0\ren_delay$11[0:0]$4966 + end + attribute \src "issuer_ls180.v:120414.3-120415.43" + process $proc$issuer_ls180.v:120414$4924 + assign { } { } + assign $0\ren_delay$11[0:0]$4925 \ren_delay$11$next + sync posedge \coresync_clk + update \ren_delay$11 $0\ren_delay$11[0:0]$4925 + end + attribute \src "issuer_ls180.v:120416.3-120417.43" + process $proc$issuer_ls180.v:120416$4926 + assign { } { } + assign $0\ren_delay$10[0:0]$4927 \ren_delay$10$next + sync posedge \coresync_clk + update \ren_delay$10 $0\ren_delay$10[0:0]$4927 + end + attribute \src "issuer_ls180.v:120418.3-120419.35" + process $proc$issuer_ls180.v:120418$4928 + assign { } { } + assign $0\ren_delay[0:0] \ren_delay$next + sync posedge \coresync_clk + update \ren_delay $0\ren_delay[0:0] + end + attribute \src "issuer_ls180.v:120434.3-120440.6" + process $proc$issuer_ls180.v:120434$4929 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0$memwr$\memory$issuer_ls180.v:120439$4923_ADDR[2:0]$4933 3'xxx + assign $0$memwr$\memory$issuer_ls180.v:120439$4923_DATA[63:0]$4934 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\memory$issuer_ls180.v:120439$4923_EN[63:0]$4935 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0$memwr$\memory$issuer_ls180.v:120438$4922_ADDR[2:0]$4930 3'xxx + assign $0$memwr$\memory$issuer_ls180.v:120438$4922_DATA[63:0]$4931 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\memory$issuer_ls180.v:120438$4922_EN[63:0]$4932 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0\_0_[2:0] \src1__addr + assign $0\_1_[2:0] \src2__addr + assign $0\_2_[2:0] \issue__addr + attribute \src "issuer_ls180.v:120438.5-120438.62" + switch \issue__wen + attribute \src "issuer_ls180.v:120438.9-120438.19" + case 1'1 + assign $0$memwr$\memory$issuer_ls180.v:120438$4922_ADDR[2:0]$4930 \issue__addr$1 + assign $0$memwr$\memory$issuer_ls180.v:120438$4922_DATA[63:0]$4931 \issue__data_i + assign $0$memwr$\memory$issuer_ls180.v:120438$4922_EN[63:0]$4932 64'1111111111111111111111111111111111111111111111111111111111111111 + case + end + attribute \src "issuer_ls180.v:120439.5-120439.58" + switch \dest1__wen + attribute \src "issuer_ls180.v:120439.9-120439.19" + case 1'1 + assign $0$memwr$\memory$issuer_ls180.v:120439$4923_ADDR[2:0]$4933 \dest1__addr + assign $0$memwr$\memory$issuer_ls180.v:120439$4923_DATA[63:0]$4934 \dest1__data_i + assign $0$memwr$\memory$issuer_ls180.v:120439$4923_EN[63:0]$4935 64'1111111111111111111111111111111111111111111111111111111111111111 + case + end + sync posedge \coresync_clk + update \_0_ $0\_0_[2:0] + update \_1_ $0\_1_[2:0] + update \_2_ $0\_2_[2:0] + update $memwr$\memory$issuer_ls180.v:120438$4922_ADDR $0$memwr$\memory$issuer_ls180.v:120438$4922_ADDR[2:0]$4930 + update $memwr$\memory$issuer_ls180.v:120438$4922_DATA $0$memwr$\memory$issuer_ls180.v:120438$4922_DATA[63:0]$4931 + update $memwr$\memory$issuer_ls180.v:120438$4922_EN $0$memwr$\memory$issuer_ls180.v:120438$4922_EN[63:0]$4932 + update $memwr$\memory$issuer_ls180.v:120439$4923_ADDR $0$memwr$\memory$issuer_ls180.v:120439$4923_ADDR[2:0]$4933 + update $memwr$\memory$issuer_ls180.v:120439$4923_DATA $0$memwr$\memory$issuer_ls180.v:120439$4923_DATA[63:0]$4934 + update $memwr$\memory$issuer_ls180.v:120439$4923_EN $0$memwr$\memory$issuer_ls180.v:120439$4923_EN[63:0]$4935 + end + attribute \src "issuer_ls180.v:120444.3-120452.6" + process $proc$issuer_ls180.v:120444$4939 + assign { } { } + assign { } { } + assign $0\ren_delay$next[0:0]$4940 $1\ren_delay$next[0:0]$4941 + attribute \src "issuer_ls180.v:120445.5-120445.29" + switch \initial + attribute \src "issuer_ls180.v:120445.9-120445.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\ren_delay$next[0:0]$4941 1'0 + case + assign $1\ren_delay$next[0:0]$4941 \src1__ren + end + sync always + update \ren_delay$next $0\ren_delay$next[0:0]$4940 + end + attribute \src "issuer_ls180.v:120453.3-120462.6" + process $proc$issuer_ls180.v:120453$4942 + assign { } { } + assign { } { } + assign $0\src1__data_o[63:0] $1\src1__data_o[63:0] + attribute \src "issuer_ls180.v:120454.5-120454.29" + switch \initial + attribute \src "issuer_ls180.v:120454.9-120454.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:245" + switch \ren_delay + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\src1__data_o[63:0] \memory_r_data + case + assign $1\src1__data_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \src1__data_o $0\src1__data_o[63:0] + end + attribute \src "issuer_ls180.v:120463.3-120471.6" + process $proc$issuer_ls180.v:120463$4943 + assign { } { } + assign { } { } + assign $0\ren_delay$10$next[0:0]$4944 $1\ren_delay$10$next[0:0]$4945 + attribute \src "issuer_ls180.v:120464.5-120464.29" + switch \initial + attribute \src "issuer_ls180.v:120464.9-120464.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\ren_delay$10$next[0:0]$4945 1'0 + case + assign $1\ren_delay$10$next[0:0]$4945 \src2__ren + end + sync always + update \ren_delay$10$next $0\ren_delay$10$next[0:0]$4944 + end + attribute \src "issuer_ls180.v:120472.3-120481.6" + process $proc$issuer_ls180.v:120472$4946 + assign { } { } + assign { } { } + assign $0\src2__data_o[63:0] $1\src2__data_o[63:0] + attribute \src "issuer_ls180.v:120473.5-120473.29" + switch \initial + attribute \src "issuer_ls180.v:120473.9-120473.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:245" + switch \ren_delay$10 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\src2__data_o[63:0] \memory_r_data$4 + case + assign $1\src2__data_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \src2__data_o $0\src2__data_o[63:0] + end + attribute \src "issuer_ls180.v:120482.3-120490.6" + process $proc$issuer_ls180.v:120482$4947 + assign { } { } + assign { } { } + assign $0\ren_delay$11$next[0:0]$4948 $1\ren_delay$11$next[0:0]$4949 + attribute \src "issuer_ls180.v:120483.5-120483.29" + switch \initial + attribute \src "issuer_ls180.v:120483.9-120483.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\ren_delay$11$next[0:0]$4949 1'0 + case + assign $1\ren_delay$11$next[0:0]$4949 \issue__ren + end + sync always + update \ren_delay$11$next $0\ren_delay$11$next[0:0]$4948 + end + attribute \src "issuer_ls180.v:120491.3-120500.6" + process $proc$issuer_ls180.v:120491$4950 + assign { } { } + assign { } { } + assign $0\issue__data_o[63:0] $1\issue__data_o[63:0] + attribute \src "issuer_ls180.v:120492.5-120492.29" + switch \initial + attribute \src "issuer_ls180.v:120492.9-120492.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:245" + switch \ren_delay$11 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\issue__data_o[63:0] \memory_r_data$6 + case + assign $1\issue__data_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \issue__data_o $0\issue__data_o[63:0] + end + connect \memory_r_data $memrd$\memory$issuer_ls180.v:120441$4936_DATA + connect \memory_r_data$4 $memrd$\memory$issuer_ls180.v:120442$4937_DATA + connect \memory_r_data$6 $memrd$\memory$issuer_ls180.v:120443$4938_DATA + connect \memory_w_data$9 \issue__data_i + connect \memory_w_en$7 \issue__wen + connect \memory_w_addr$8 \issue__addr$1 + connect \memory_w_data \dest1__data_i + connect \memory_w_en \dest1__wen + connect \memory_w_addr \dest1__addr + connect \memory_r_addr$5 \issue__addr + connect \memory_r_addr$3 \src2__addr + connect \memory_r_addr \src1__addr +end +attribute \src "issuer_ls180.v:120514.1-122407.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.fus" +attribute \generator "nMigen" +module \fus + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" + wire input 321 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" + wire input 308 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 254 \cr_a_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 255 \cr_a_ok$110 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 256 \cr_a_ok$111 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 257 \cr_a_ok$112 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 258 \cr_a_ok$113 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 259 \cr_a_ok$114 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire input 2 \cu_ad__go_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire output 3 \cu_ad__rel_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107" + wire output 24 \cu_busy_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107" + wire output 73 \cu_busy_o$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107" + wire output 80 \cu_busy_o$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107" + wire output 101 \cu_busy_o$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107" + wire output 30 \cu_busy_o$2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107" + wire output 116 \cu_busy_o$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107" + wire output 135 \cu_busy_o$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107" + wire output 154 \cu_busy_o$26 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107" + wire output 41 \cu_busy_o$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107" + wire output 52 \cu_busy_o$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:100" + wire input 23 \cu_issue_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:100" + wire input 29 \cu_issue_i$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:100" + wire input 72 \cu_issue_i$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:100" + wire input 79 \cu_issue_i$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:100" + wire input 100 \cu_issue_i$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:100" + wire input 115 \cu_issue_i$19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:100" + wire input 134 \cu_issue_i$22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:100" + wire input 153 \cu_issue_i$25 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:100" + wire input 40 \cu_issue_i$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:100" + wire input 51 \cu_issue_i$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 4 input 157 \cu_rd__go_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 6 input 160 \cu_rd__go_i$29 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 4 input 163 \cu_rd__go_i$32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 3 input 166 \cu_rd__go_i$35 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 6 input 169 \cu_rd__go_i$38 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 3 input 172 \cu_rd__go_i$41 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 3 input 175 \cu_rd__go_i$44 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 5 input 178 \cu_rd__go_i$47 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 3 input 181 \cu_rd__go_i$50 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 3 input 206 \cu_rd__go_i$70 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 4 output 156 \cu_rd__rel_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 6 output 159 \cu_rd__rel_o$28 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 4 output 162 \cu_rd__rel_o$31 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 3 output 165 \cu_rd__rel_o$34 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 6 output 168 \cu_rd__rel_o$37 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 3 output 171 \cu_rd__rel_o$40 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 3 output 174 \cu_rd__rel_o$43 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 5 output 177 \cu_rd__rel_o$46 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 3 output 180 \cu_rd__rel_o$49 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 3 output 205 \cu_rd__rel_o$69 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96" + wire width 4 input 25 \cu_rdmaskn_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96" + wire width 3 input 74 \cu_rdmaskn_i$12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96" + wire width 6 input 81 \cu_rdmaskn_i$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96" + wire width 3 input 102 \cu_rdmaskn_i$18 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96" + wire width 3 input 117 \cu_rdmaskn_i$21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96" + wire width 5 input 136 \cu_rdmaskn_i$24 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96" + wire width 3 input 155 \cu_rdmaskn_i$27 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96" + wire width 6 input 31 \cu_rdmaskn_i$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96" + wire width 3 input 42 \cu_rdmaskn_i$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96" + wire width 4 input 53 \cu_rdmaskn_i$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire input 4 \cu_st__go_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire output 1 \cu_st__rel_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 5 input 218 \cu_wr__go_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 3 input 239 \cu_wr__go_i$100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 2 input 241 \cu_wr__go_i$102 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 3 input 290 \cu_wr__go_i$137 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 3 input 221 \cu_wr__go_i$82 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 5 input 224 \cu_wr__go_i$85 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 2 input 227 \cu_wr__go_i$88 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 6 input 230 \cu_wr__go_i$91 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 4 input 233 \cu_wr__go_i$94 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 4 input 236 \cu_wr__go_i$97 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 5 output 217 \cu_wr__rel_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 2 output 240 \cu_wr__rel_o$101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 3 output 289 \cu_wr__rel_o$136 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 3 output 220 \cu_wr__rel_o$81 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 5 output 223 \cu_wr__rel_o$84 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 2 output 226 \cu_wr__rel_o$87 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 6 output 229 \cu_wr__rel_o$90 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 4 output 232 \cu_wr__rel_o$93 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 4 output 235 \cu_wr__rel_o$96 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 3 output 238 \cu_wr__rel_o$99 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 64 output 242 \dest1_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 64 output 243 \dest1_o$103 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 64 output 244 \dest1_o$104 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 64 output 245 \dest1_o$105 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 64 output 246 \dest1_o$106 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 64 output 247 \dest1_o$107 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 64 output 248 \dest1_o$108 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 64 output 249 \dest1_o$109 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 64 output 295 \dest1_o$141 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 32 output 253 \dest2_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 4 output 260 \dest2_o$115 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 4 output 262 \dest2_o$116 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 4 output 263 \dest2_o$117 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 4 output 264 \dest2_o$118 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 4 output 265 \dest2_o$119 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 64 output 296 \dest2_o$142 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 64 output 298 \dest2_o$144 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 64 output 307 \dest2_o$150 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 4 output 261 \dest3_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 2 output 269 \dest3_o$122 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 2 output 271 \dest3_o$123 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 2 output 278 \dest3_o$127 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 2 output 279 \dest3_o$128 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 64 output 297 \dest3_o$143 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 64 output 299 \dest3_o$145 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 64 output 302 \dest3_o$147 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 2 output 276 \dest4_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire output 285 \dest4_o$133 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire output 286 \dest4_o$134 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire output 287 \dest4_o$135 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 64 output 303 \dest4_o$148 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 2 output 277 \dest5_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire output 284 \dest5_o$132 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 64 output 305 \dest5_o$149 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 2 output 270 \dest6_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 output 251 \ea + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 288 \fast1_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 291 \fast1_ok$138 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 292 \fast1_ok$139 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 293 \fast2_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 294 \fast2_ok$140 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 252 \full_cr_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:110" + wire input 315 \ldst_port0_addr_exc_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 96 output 313 \ldst_port0_addr_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 314 \ldst_port0_addr_i_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:109" + wire input 316 \ldst_port0_addr_ok_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:105" + wire input 309 \ldst_port0_busy_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:102" + wire width 4 output 312 \ldst_port0_data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:98" + wire output 310 \ldst_port0_is_ld_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:99" + wire output 311 \ldst_port0_is_st_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 input 317 \ldst_port0_ld_data_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire input 318 \ldst_port0_ld_data_o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 output 319 \ldst_port0_st_data_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 320 \ldst_port0_st_data_i_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 304 \msr_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 300 \nia_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 301 \nia_ok$146 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 output 250 \o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 216 \o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 219 \o_ok$80 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 222 \o_ok$83 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 225 \o_ok$86 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 228 \o_ok$89 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 231 \o_ok$92 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 234 \o_ok$95 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 237 \o_ok$98 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 input 21 \oper_i_alu_alu0__data_len + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 input 6 \oper_i_alu_alu0__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 input 7 \oper_i_alu_alu0__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 8 \oper_i_alu_alu0__imm_data__ok + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 input 17 \oper_i_alu_alu0__input_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 22 \oper_i_alu_alu0__insn + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 input 5 \oper_i_alu_alu0__insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 13 \oper_i_alu_alu0__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 15 \oper_i_alu_alu0__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 19 \oper_i_alu_alu0__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 20 \oper_i_alu_alu0__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 11 \oper_i_alu_alu0__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 12 \oper_i_alu_alu0__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 18 \oper_i_alu_alu0__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 10 \oper_i_alu_alu0__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 9 \oper_i_alu_alu0__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 16 \oper_i_alu_alu0__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 14 \oper_i_alu_alu0__zero_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 input 32 \oper_i_alu_branch0__cia + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 input 34 \oper_i_alu_branch0__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 input 36 \oper_i_alu_branch0__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 37 \oper_i_alu_branch0__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 35 \oper_i_alu_branch0__insn + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 input 33 \oper_i_alu_branch0__insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 39 \oper_i_alu_branch0__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 38 \oper_i_alu_branch0__lk + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 input 27 \oper_i_alu_cr0__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 28 \oper_i_alu_cr0__insn + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 input 26 \oper_i_alu_cr0__insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 input 98 \oper_i_alu_div0__data_len + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 input 83 \oper_i_alu_div0__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 input 84 \oper_i_alu_div0__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 85 \oper_i_alu_div0__imm_data__ok + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 input 92 \oper_i_alu_div0__input_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 99 \oper_i_alu_div0__insn + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 input 82 \oper_i_alu_div0__insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 90 \oper_i_alu_div0__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 93 \oper_i_alu_div0__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 96 \oper_i_alu_div0__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 97 \oper_i_alu_div0__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 88 \oper_i_alu_div0__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 89 \oper_i_alu_div0__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 95 \oper_i_alu_div0__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 87 \oper_i_alu_div0__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 86 \oper_i_alu_div0__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 94 \oper_i_alu_div0__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 91 \oper_i_alu_div0__zero_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 input 70 \oper_i_alu_logical0__data_len + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 input 55 \oper_i_alu_logical0__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 input 56 \oper_i_alu_logical0__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 57 \oper_i_alu_logical0__imm_data__ok + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 input 64 \oper_i_alu_logical0__input_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 71 \oper_i_alu_logical0__insn + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 input 54 \oper_i_alu_logical0__insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 62 \oper_i_alu_logical0__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 65 \oper_i_alu_logical0__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 68 \oper_i_alu_logical0__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 69 \oper_i_alu_logical0__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 60 \oper_i_alu_logical0__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 61 \oper_i_alu_logical0__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 67 \oper_i_alu_logical0__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 59 \oper_i_alu_logical0__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 58 \oper_i_alu_logical0__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 66 \oper_i_alu_logical0__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 63 \oper_i_alu_logical0__zero_a + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 input 104 \oper_i_alu_mul0__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 input 105 \oper_i_alu_mul0__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 106 \oper_i_alu_mul0__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 114 \oper_i_alu_mul0__insn + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 input 103 \oper_i_alu_mul0__insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 112 \oper_i_alu_mul0__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 113 \oper_i_alu_mul0__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 109 \oper_i_alu_mul0__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 110 \oper_i_alu_mul0__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 108 \oper_i_alu_mul0__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 107 \oper_i_alu_mul0__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 111 \oper_i_alu_mul0__write_cr0 + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 input 119 \oper_i_alu_shift_rot0__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 input 120 \oper_i_alu_shift_rot0__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 121 \oper_i_alu_shift_rot0__imm_data__ok + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 input 127 \oper_i_alu_shift_rot0__input_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 129 \oper_i_alu_shift_rot0__input_cr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 133 \oper_i_alu_shift_rot0__insn + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 input 118 \oper_i_alu_shift_rot0__insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 131 \oper_i_alu_shift_rot0__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 132 \oper_i_alu_shift_rot0__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 124 \oper_i_alu_shift_rot0__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 125 \oper_i_alu_shift_rot0__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 128 \oper_i_alu_shift_rot0__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 130 \oper_i_alu_shift_rot0__output_cr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 123 \oper_i_alu_shift_rot0__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 122 \oper_i_alu_shift_rot0__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 126 \oper_i_alu_shift_rot0__write_cr0 + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 input 76 \oper_i_alu_spr0__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 77 \oper_i_alu_spr0__insn + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 input 75 \oper_i_alu_spr0__insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 78 \oper_i_alu_spr0__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 input 47 \oper_i_alu_trap0__cia + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 input 44 \oper_i_alu_trap0__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 45 \oper_i_alu_trap0__insn + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 input 43 \oper_i_alu_trap0__insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 48 \oper_i_alu_trap0__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 input 46 \oper_i_alu_trap0__msr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 13 input 50 \oper_i_alu_trap0__trapaddr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 input 49 \oper_i_alu_trap0__traptype + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 149 \oper_i_ldst_ldst0__byte_reverse + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 input 148 \oper_i_ldst_ldst0__data_len + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 input 138 \oper_i_ldst_ldst0__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 input 139 \oper_i_ldst_ldst0__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 140 \oper_i_ldst_ldst0__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 152 \oper_i_ldst_ldst0__insn + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 input 137 \oper_i_ldst_ldst0__insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 146 \oper_i_ldst_ldst0__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 147 \oper_i_ldst_ldst0__is_signed + attribute \enum_base_type "LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 input 151 \oper_i_ldst_ldst0__ldst_mode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 144 \oper_i_ldst_ldst0__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 145 \oper_i_ldst_ldst0__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 143 \oper_i_ldst_ldst0__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 142 \oper_i_ldst_ldst0__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 150 \oper_i_ldst_ldst0__sign_extend + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 141 \oper_i_ldst_ldst0__zero_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 306 \spr1_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire width 64 input 158 \src1_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire width 64 input 161 \src1_i$30 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire width 64 input 164 \src1_i$33 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire width 64 input 167 \src1_i$36 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire width 64 input 170 \src1_i$39 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire width 64 input 173 \src1_i$42 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire width 64 input 176 \src1_i$45 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire width 64 input 179 \src1_i$48 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire width 64 input 182 \src1_i$51 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire width 64 input 210 \src1_i$74 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire width 64 input 183 \src2_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire width 64 input 184 \src2_i$52 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire width 64 input 185 \src2_i$53 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire width 64 input 186 \src2_i$54 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire width 64 input 187 \src2_i$55 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire width 64 input 188 \src2_i$56 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire width 64 input 189 \src2_i$57 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire width 64 input 190 \src2_i$58 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire width 64 input 213 \src2_i$77 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire width 64 input 215 \src2_i$79 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire width 64 input 191 \src3_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire width 64 input 192 \src3_i$59 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire input 193 \src3_i$60 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire input 194 \src3_i$61 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire input 196 \src3_i$62 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire input 197 \src3_i$63 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire width 32 input 203 \src3_i$67 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire width 4 input 207 \src3_i$71 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire width 64 input 211 \src3_i$75 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire width 64 input 212 \src3_i$76 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire input 195 \src4_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire input 198 \src4_i$64 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire width 2 input 199 \src4_i$65 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire width 4 input 204 \src4_i$68 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire width 64 input 214 \src4_i$78 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire width 2 input 201 \src5_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire width 2 input 202 \src5_i$66 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire width 4 input 208 \src5_i$72 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire width 2 input 200 \src6_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" + wire width 4 input 209 \src6_i$73 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 266 \xer_ca_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 267 \xer_ca_ok$120 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 268 \xer_ca_ok$121 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 272 \xer_ov_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 273 \xer_ov_ok$124 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 274 \xer_ov_ok$125 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 275 \xer_ov_ok$126 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 280 \xer_so_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 281 \xer_so_ok$129 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 282 \xer_so_ok$130 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 283 \xer_so_ok$131 + attribute \module_not_derived 1 + attribute \src "issuer_ls180.v:122048.8-122090.4" + cell \alu0 \alu0 + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \cr_a_ok \cr_a_ok + connect \cu_busy_o \cu_busy_o + connect \cu_issue_i \cu_issue_i + connect \cu_rd__go_i \cu_rd__go_i + connect \cu_rd__rel_o \cu_rd__rel_o + connect \cu_rdmaskn_i \cu_rdmaskn_i + connect \cu_wr__go_i \cu_wr__go_i + connect \cu_wr__rel_o \cu_wr__rel_o + connect \dest1_o \dest1_o + connect \dest2_o \dest2_o$115 + connect \dest3_o \dest3_o$122 + connect \dest4_o \dest4_o + connect \dest5_o \dest5_o$132 + connect \o_ok \o_ok + connect \oper_i_alu_alu0__data_len \oper_i_alu_alu0__data_len + connect \oper_i_alu_alu0__fn_unit \oper_i_alu_alu0__fn_unit + connect \oper_i_alu_alu0__imm_data__data \oper_i_alu_alu0__imm_data__data + connect \oper_i_alu_alu0__imm_data__ok \oper_i_alu_alu0__imm_data__ok + connect \oper_i_alu_alu0__input_carry \oper_i_alu_alu0__input_carry + connect \oper_i_alu_alu0__insn \oper_i_alu_alu0__insn + connect \oper_i_alu_alu0__insn_type \oper_i_alu_alu0__insn_type + connect \oper_i_alu_alu0__invert_in \oper_i_alu_alu0__invert_in + connect \oper_i_alu_alu0__invert_out \oper_i_alu_alu0__invert_out + connect \oper_i_alu_alu0__is_32bit \oper_i_alu_alu0__is_32bit + connect \oper_i_alu_alu0__is_signed \oper_i_alu_alu0__is_signed + connect \oper_i_alu_alu0__oe__oe \oper_i_alu_alu0__oe__oe + connect \oper_i_alu_alu0__oe__ok \oper_i_alu_alu0__oe__ok + connect \oper_i_alu_alu0__output_carry \oper_i_alu_alu0__output_carry + connect \oper_i_alu_alu0__rc__ok \oper_i_alu_alu0__rc__ok + connect \oper_i_alu_alu0__rc__rc \oper_i_alu_alu0__rc__rc + connect \oper_i_alu_alu0__write_cr0 \oper_i_alu_alu0__write_cr0 + connect \oper_i_alu_alu0__zero_a \oper_i_alu_alu0__zero_a + connect \src1_i \src1_i + connect \src2_i \src2_i + connect \src3_i \src3_i$60 + connect \src4_i \src4_i$65 + connect \xer_ca_ok \xer_ca_ok + connect \xer_ov_ok \xer_ov_ok + connect \xer_so_ok \xer_so_ok + end + attribute \module_not_derived 1 + attribute \src "issuer_ls180.v:122091.11-122118.4" + cell \branch0 \branch0 + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \cu_busy_o \cu_busy_o$5 + connect \cu_issue_i \cu_issue_i$4 + connect \cu_rd__go_i \cu_rd__go_i$70 + connect \cu_rd__rel_o \cu_rd__rel_o$69 + connect \cu_rdmaskn_i \cu_rdmaskn_i$6 + connect \cu_wr__go_i \cu_wr__go_i$137 + connect \cu_wr__rel_o \cu_wr__rel_o$136 + connect \dest1_o \dest1_o$141 + connect \dest2_o \dest2_o$144 + connect \dest3_o \dest3_o$147 + connect \fast1_ok \fast1_ok + connect \fast2_ok \fast2_ok + connect \nia_ok \nia_ok + connect \oper_i_alu_branch0__cia \oper_i_alu_branch0__cia + connect \oper_i_alu_branch0__fn_unit \oper_i_alu_branch0__fn_unit + connect \oper_i_alu_branch0__imm_data__data \oper_i_alu_branch0__imm_data__data + connect \oper_i_alu_branch0__imm_data__ok \oper_i_alu_branch0__imm_data__ok + connect \oper_i_alu_branch0__insn \oper_i_alu_branch0__insn + connect \oper_i_alu_branch0__insn_type \oper_i_alu_branch0__insn_type + connect \oper_i_alu_branch0__is_32bit \oper_i_alu_branch0__is_32bit + connect \oper_i_alu_branch0__lk \oper_i_alu_branch0__lk + connect \src1_i \src1_i$74 + connect \src2_i \src2_i$77 + connect \src3_i \src3_i$71 + end + attribute \module_not_derived 1 + attribute \src "issuer_ls180.v:122119.7-122144.4" + cell \cr0 \cr0 + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \cr_a_ok \cr_a_ok$110 + connect \cu_busy_o \cu_busy_o$2 + connect \cu_issue_i \cu_issue_i$1 + connect \cu_rd__go_i \cu_rd__go_i$29 + connect \cu_rd__rel_o \cu_rd__rel_o$28 + connect \cu_rdmaskn_i \cu_rdmaskn_i$3 + connect \cu_wr__go_i \cu_wr__go_i$82 + connect \cu_wr__rel_o \cu_wr__rel_o$81 + connect \dest1_o \dest1_o$103 + connect \dest2_o \dest2_o + connect \dest3_o \dest3_o + connect \full_cr_ok \full_cr_ok + connect \o_ok \o_ok$80 + connect \oper_i_alu_cr0__fn_unit \oper_i_alu_cr0__fn_unit + connect \oper_i_alu_cr0__insn \oper_i_alu_cr0__insn + connect \oper_i_alu_cr0__insn_type \oper_i_alu_cr0__insn_type + connect \src1_i \src1_i$30 + connect \src2_i \src2_i$52 + connect \src3_i \src3_i$67 + connect \src4_i \src4_i$68 + connect \src5_i \src5_i$72 + connect \src6_i \src6_i$73 + end + attribute \module_not_derived 1 + attribute \src "issuer_ls180.v:122145.8-122184.4" + cell \div0 \div0 + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \cr_a_ok \cr_a_ok$112 + connect \cu_busy_o \cu_busy_o$17 + connect \cu_issue_i \cu_issue_i$16 + connect \cu_rd__go_i \cu_rd__go_i$41 + connect \cu_rd__rel_o \cu_rd__rel_o$40 + connect \cu_rdmaskn_i \cu_rdmaskn_i$18 + connect \cu_wr__go_i \cu_wr__go_i$94 + connect \cu_wr__rel_o \cu_wr__rel_o$93 + connect \dest1_o \dest1_o$107 + connect \dest2_o \dest2_o$117 + connect \dest3_o \dest3_o$127 + connect \dest4_o \dest4_o$134 + connect \o_ok \o_ok$92 + connect \oper_i_alu_div0__data_len \oper_i_alu_div0__data_len + connect \oper_i_alu_div0__fn_unit \oper_i_alu_div0__fn_unit + connect \oper_i_alu_div0__imm_data__data \oper_i_alu_div0__imm_data__data + connect \oper_i_alu_div0__imm_data__ok \oper_i_alu_div0__imm_data__ok + connect \oper_i_alu_div0__input_carry \oper_i_alu_div0__input_carry + connect \oper_i_alu_div0__insn \oper_i_alu_div0__insn + connect \oper_i_alu_div0__insn_type \oper_i_alu_div0__insn_type + connect \oper_i_alu_div0__invert_in \oper_i_alu_div0__invert_in + connect \oper_i_alu_div0__invert_out \oper_i_alu_div0__invert_out + connect \oper_i_alu_div0__is_32bit \oper_i_alu_div0__is_32bit + connect \oper_i_alu_div0__is_signed \oper_i_alu_div0__is_signed + connect \oper_i_alu_div0__oe__oe \oper_i_alu_div0__oe__oe + connect \oper_i_alu_div0__oe__ok \oper_i_alu_div0__oe__ok + connect \oper_i_alu_div0__output_carry \oper_i_alu_div0__output_carry + connect \oper_i_alu_div0__rc__ok \oper_i_alu_div0__rc__ok + connect \oper_i_alu_div0__rc__rc \oper_i_alu_div0__rc__rc + connect \oper_i_alu_div0__write_cr0 \oper_i_alu_div0__write_cr0 + connect \oper_i_alu_div0__zero_a \oper_i_alu_div0__zero_a + connect \src1_i \src1_i$42 + connect \src2_i \src2_i$55 + connect \src3_i \src3_i$62 + connect \xer_ov_ok \xer_ov_ok$125 + connect \xer_so_ok \xer_so_ok$130 + end + attribute \module_not_derived 1 + attribute \src "issuer_ls180.v:122185.9-122232.4" + cell \ldst0 \ldst0 + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \cu_ad__go_i \cu_ad__go_i + connect \cu_ad__rel_o \cu_ad__rel_o + connect \cu_busy_o \cu_busy_o$26 + connect \cu_issue_i \cu_issue_i$25 + connect \cu_rd__go_i \cu_rd__go_i$50 + connect \cu_rd__rel_o \cu_rd__rel_o$49 + connect \cu_rdmaskn_i \cu_rdmaskn_i$27 + connect \cu_st__go_i \cu_st__go_i + connect \cu_st__rel_o \cu_st__rel_o + connect \cu_wr__go_i \cu_wr__go_i$102 + connect \cu_wr__rel_o \cu_wr__rel_o$101 + connect \ea \ea + connect \ldst_port0_addr_exc_o \ldst_port0_addr_exc_o + connect \ldst_port0_addr_i \ldst_port0_addr_i + connect \ldst_port0_addr_i_ok \ldst_port0_addr_i_ok + connect \ldst_port0_addr_ok_o \ldst_port0_addr_ok_o + connect \ldst_port0_busy_o \ldst_port0_busy_o + connect \ldst_port0_data_len \ldst_port0_data_len + connect \ldst_port0_is_ld_i \ldst_port0_is_ld_i + connect \ldst_port0_is_st_i \ldst_port0_is_st_i + connect \ldst_port0_ld_data_o \ldst_port0_ld_data_o + connect \ldst_port0_ld_data_o_ok \ldst_port0_ld_data_o_ok + connect \ldst_port0_st_data_i \ldst_port0_st_data_i + connect \ldst_port0_st_data_i_ok \ldst_port0_st_data_i_ok + connect \o \o + connect \oper_i_ldst_ldst0__byte_reverse \oper_i_ldst_ldst0__byte_reverse + connect \oper_i_ldst_ldst0__data_len \oper_i_ldst_ldst0__data_len + connect \oper_i_ldst_ldst0__fn_unit \oper_i_ldst_ldst0__fn_unit + connect \oper_i_ldst_ldst0__imm_data__data \oper_i_ldst_ldst0__imm_data__data + connect \oper_i_ldst_ldst0__imm_data__ok \oper_i_ldst_ldst0__imm_data__ok + connect \oper_i_ldst_ldst0__insn \oper_i_ldst_ldst0__insn + connect \oper_i_ldst_ldst0__insn_type \oper_i_ldst_ldst0__insn_type + connect \oper_i_ldst_ldst0__is_32bit \oper_i_ldst_ldst0__is_32bit + connect \oper_i_ldst_ldst0__is_signed \oper_i_ldst_ldst0__is_signed + connect \oper_i_ldst_ldst0__ldst_mode \oper_i_ldst_ldst0__ldst_mode + connect \oper_i_ldst_ldst0__oe__oe \oper_i_ldst_ldst0__oe__oe + connect \oper_i_ldst_ldst0__oe__ok \oper_i_ldst_ldst0__oe__ok + connect \oper_i_ldst_ldst0__rc__ok \oper_i_ldst_ldst0__rc__ok + connect \oper_i_ldst_ldst0__rc__rc \oper_i_ldst_ldst0__rc__rc + connect \oper_i_ldst_ldst0__sign_extend \oper_i_ldst_ldst0__sign_extend + connect \oper_i_ldst_ldst0__zero_a \oper_i_ldst_ldst0__zero_a + connect \src1_i \src1_i$51 + connect \src2_i \src2_i$58 + connect \src3_i \src3_i$59 + end + attribute \module_not_derived 1 + attribute \src "issuer_ls180.v:122233.12-122268.4" + cell \logical0 \logical0 + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \cr_a_ok \cr_a_ok$111 + connect \cu_busy_o \cu_busy_o$11 + connect \cu_issue_i \cu_issue_i$10 + connect \cu_rd__go_i \cu_rd__go_i$35 + connect \cu_rd__rel_o \cu_rd__rel_o$34 + connect \cu_rdmaskn_i \cu_rdmaskn_i$12 + connect \cu_wr__go_i \cu_wr__go_i$88 + connect \cu_wr__rel_o \cu_wr__rel_o$87 + connect \dest1_o \dest1_o$105 + connect \dest2_o \dest2_o$116 + connect \o_ok \o_ok$86 + connect \oper_i_alu_logical0__data_len \oper_i_alu_logical0__data_len + connect \oper_i_alu_logical0__fn_unit \oper_i_alu_logical0__fn_unit + connect \oper_i_alu_logical0__imm_data__data \oper_i_alu_logical0__imm_data__data + connect \oper_i_alu_logical0__imm_data__ok \oper_i_alu_logical0__imm_data__ok + connect \oper_i_alu_logical0__input_carry \oper_i_alu_logical0__input_carry + connect \oper_i_alu_logical0__insn \oper_i_alu_logical0__insn + connect \oper_i_alu_logical0__insn_type \oper_i_alu_logical0__insn_type + connect \oper_i_alu_logical0__invert_in \oper_i_alu_logical0__invert_in + connect \oper_i_alu_logical0__invert_out \oper_i_alu_logical0__invert_out + connect \oper_i_alu_logical0__is_32bit \oper_i_alu_logical0__is_32bit + connect \oper_i_alu_logical0__is_signed \oper_i_alu_logical0__is_signed + connect \oper_i_alu_logical0__oe__oe \oper_i_alu_logical0__oe__oe + connect \oper_i_alu_logical0__oe__ok \oper_i_alu_logical0__oe__ok + connect \oper_i_alu_logical0__output_carry \oper_i_alu_logical0__output_carry + connect \oper_i_alu_logical0__rc__ok \oper_i_alu_logical0__rc__ok + connect \oper_i_alu_logical0__rc__rc \oper_i_alu_logical0__rc__rc + connect \oper_i_alu_logical0__write_cr0 \oper_i_alu_logical0__write_cr0 + connect \oper_i_alu_logical0__zero_a \oper_i_alu_logical0__zero_a + connect \src1_i \src1_i$36 + connect \src2_i \src2_i$54 + connect \src3_i \src3_i$61 + end + attribute \module_not_derived 1 + attribute \src "issuer_ls180.v:122269.8-122302.4" + cell \mul0 \mul0 + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \cr_a_ok \cr_a_ok$113 + connect \cu_busy_o \cu_busy_o$20 + connect \cu_issue_i \cu_issue_i$19 + connect \cu_rd__go_i \cu_rd__go_i$44 + connect \cu_rd__rel_o \cu_rd__rel_o$43 + connect \cu_rdmaskn_i \cu_rdmaskn_i$21 + connect \cu_wr__go_i \cu_wr__go_i$97 + connect \cu_wr__rel_o \cu_wr__rel_o$96 + connect \dest1_o \dest1_o$108 + connect \dest2_o \dest2_o$118 + connect \dest3_o \dest3_o$128 + connect \dest4_o \dest4_o$135 + connect \o_ok \o_ok$95 + connect \oper_i_alu_mul0__fn_unit \oper_i_alu_mul0__fn_unit + connect \oper_i_alu_mul0__imm_data__data \oper_i_alu_mul0__imm_data__data + connect \oper_i_alu_mul0__imm_data__ok \oper_i_alu_mul0__imm_data__ok + connect \oper_i_alu_mul0__insn \oper_i_alu_mul0__insn + connect \oper_i_alu_mul0__insn_type \oper_i_alu_mul0__insn_type + connect \oper_i_alu_mul0__is_32bit \oper_i_alu_mul0__is_32bit + connect \oper_i_alu_mul0__is_signed \oper_i_alu_mul0__is_signed + connect \oper_i_alu_mul0__oe__oe \oper_i_alu_mul0__oe__oe + connect \oper_i_alu_mul0__oe__ok \oper_i_alu_mul0__oe__ok + connect \oper_i_alu_mul0__rc__ok \oper_i_alu_mul0__rc__ok + connect \oper_i_alu_mul0__rc__rc \oper_i_alu_mul0__rc__rc + connect \oper_i_alu_mul0__write_cr0 \oper_i_alu_mul0__write_cr0 + connect \src1_i \src1_i$45 + connect \src2_i \src2_i$56 + connect \src3_i \src3_i$63 + connect \xer_ov_ok \xer_ov_ok$126 + connect \xer_so_ok \xer_so_ok$131 + end + attribute \module_not_derived 1 + attribute \src "issuer_ls180.v:122303.13-122340.4" + cell \shiftrot0 \shiftrot0 + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \cr_a_ok \cr_a_ok$114 + connect \cu_busy_o \cu_busy_o$23 + connect \cu_issue_i \cu_issue_i$22 + connect \cu_rd__go_i \cu_rd__go_i$47 + connect \cu_rd__rel_o \cu_rd__rel_o$46 + connect \cu_rdmaskn_i \cu_rdmaskn_i$24 + connect \cu_wr__go_i \cu_wr__go_i$100 + connect \cu_wr__rel_o \cu_wr__rel_o$99 + connect \dest1_o \dest1_o$109 + connect \dest2_o \dest2_o$119 + connect \dest3_o \dest3_o$123 + connect \o_ok \o_ok$98 + connect \oper_i_alu_shift_rot0__fn_unit \oper_i_alu_shift_rot0__fn_unit + connect \oper_i_alu_shift_rot0__imm_data__data \oper_i_alu_shift_rot0__imm_data__data + connect \oper_i_alu_shift_rot0__imm_data__ok \oper_i_alu_shift_rot0__imm_data__ok + connect \oper_i_alu_shift_rot0__input_carry \oper_i_alu_shift_rot0__input_carry + connect \oper_i_alu_shift_rot0__input_cr \oper_i_alu_shift_rot0__input_cr + connect \oper_i_alu_shift_rot0__insn \oper_i_alu_shift_rot0__insn + connect \oper_i_alu_shift_rot0__insn_type \oper_i_alu_shift_rot0__insn_type + connect \oper_i_alu_shift_rot0__is_32bit \oper_i_alu_shift_rot0__is_32bit + connect \oper_i_alu_shift_rot0__is_signed \oper_i_alu_shift_rot0__is_signed + connect \oper_i_alu_shift_rot0__oe__oe \oper_i_alu_shift_rot0__oe__oe + connect \oper_i_alu_shift_rot0__oe__ok \oper_i_alu_shift_rot0__oe__ok + connect \oper_i_alu_shift_rot0__output_carry \oper_i_alu_shift_rot0__output_carry + connect \oper_i_alu_shift_rot0__output_cr \oper_i_alu_shift_rot0__output_cr + connect \oper_i_alu_shift_rot0__rc__ok \oper_i_alu_shift_rot0__rc__ok + connect \oper_i_alu_shift_rot0__rc__rc \oper_i_alu_shift_rot0__rc__rc + connect \oper_i_alu_shift_rot0__write_cr0 \oper_i_alu_shift_rot0__write_cr0 + connect \src1_i \src1_i$48 + connect \src2_i \src2_i$57 + connect \src3_i \src3_i + connect \src4_i \src4_i$64 + connect \src5_i \src5_i + connect \xer_ca_ok \xer_ca_ok$121 + end + attribute \module_not_derived 1 + attribute \src "issuer_ls180.v:122341.8-122373.4" + cell \spr0 \spr0 + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \cu_busy_o \cu_busy_o$14 + connect \cu_issue_i \cu_issue_i$13 + connect \cu_rd__go_i \cu_rd__go_i$38 + connect \cu_rd__rel_o \cu_rd__rel_o$37 + connect \cu_rdmaskn_i \cu_rdmaskn_i$15 + connect \cu_wr__go_i \cu_wr__go_i$91 + connect \cu_wr__rel_o \cu_wr__rel_o$90 + connect \dest1_o \dest1_o$106 + connect \dest2_o \dest2_o$150 + connect \dest3_o \dest3_o$143 + connect \dest4_o \dest4_o$133 + connect \dest5_o \dest5_o + connect \dest6_o \dest6_o + connect \fast1_ok \fast1_ok$139 + connect \o_ok \o_ok$89 + connect \oper_i_alu_spr0__fn_unit \oper_i_alu_spr0__fn_unit + connect \oper_i_alu_spr0__insn \oper_i_alu_spr0__insn + connect \oper_i_alu_spr0__insn_type \oper_i_alu_spr0__insn_type + connect \oper_i_alu_spr0__is_32bit \oper_i_alu_spr0__is_32bit + connect \spr1_ok \spr1_ok + connect \src1_i \src1_i$39 + connect \src2_i \src2_i$79 + connect \src3_i \src3_i$76 + connect \src4_i \src4_i + connect \src5_i \src5_i$66 + connect \src6_i \src6_i + connect \xer_ca_ok \xer_ca_ok$120 + connect \xer_ov_ok \xer_ov_ok$124 + connect \xer_so_ok \xer_so_ok$129 + end + attribute \module_not_derived 1 + attribute \src "issuer_ls180.v:122374.9-122406.4" + cell \trap0 \trap0 + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \cu_busy_o \cu_busy_o$8 + connect \cu_issue_i \cu_issue_i$7 + connect \cu_rd__go_i \cu_rd__go_i$32 + connect \cu_rd__rel_o \cu_rd__rel_o$31 + connect \cu_rdmaskn_i \cu_rdmaskn_i$9 + connect \cu_wr__go_i \cu_wr__go_i$85 + connect \cu_wr__rel_o \cu_wr__rel_o$84 + connect \dest1_o \dest1_o$104 + connect \dest2_o \dest2_o$142 + connect \dest3_o \dest3_o$145 + connect \dest4_o \dest4_o$148 + connect \dest5_o \dest5_o$149 + connect \fast1_ok \fast1_ok$138 + connect \fast2_ok \fast2_ok$140 + connect \msr_ok \msr_ok + connect \nia_ok \nia_ok$146 + connect \o_ok \o_ok$83 + connect \oper_i_alu_trap0__cia \oper_i_alu_trap0__cia + connect \oper_i_alu_trap0__fn_unit \oper_i_alu_trap0__fn_unit + connect \oper_i_alu_trap0__insn \oper_i_alu_trap0__insn + connect \oper_i_alu_trap0__insn_type \oper_i_alu_trap0__insn_type + connect \oper_i_alu_trap0__is_32bit \oper_i_alu_trap0__is_32bit + connect \oper_i_alu_trap0__msr \oper_i_alu_trap0__msr + connect \oper_i_alu_trap0__trapaddr \oper_i_alu_trap0__trapaddr + connect \oper_i_alu_trap0__traptype \oper_i_alu_trap0__traptype + connect \src1_i \src1_i$33 + connect \src2_i \src2_i$53 + connect \src3_i \src3_i$75 + connect \src4_i \src4_i$78 + end +end +attribute \src "issuer_ls180.v:122411.1-122469.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.l0.l0.idx_l" +attribute \generator "nMigen" +module \idx_l + attribute \src "issuer_ls180.v:122412.7-122412.20" + wire $0\initial[0:0] + attribute \src "issuer_ls180.v:122457.3-122465.6" + wire $0\q_int$next[0:0]$4978 + attribute \src "issuer_ls180.v:122455.3-122456.27" + wire $0\q_int[0:0] + attribute \src "issuer_ls180.v:122457.3-122465.6" + wire $1\q_int$next[0:0]$4979 + attribute \src "issuer_ls180.v:122436.7-122436.19" + wire $1\q_int[0:0] + attribute \src "issuer_ls180.v:122447.17-122447.96" + wire $and$issuer_ls180.v:122447$4968_Y + attribute \src "issuer_ls180.v:122452.17-122452.96" + wire $and$issuer_ls180.v:122452$4973_Y + attribute \src "issuer_ls180.v:122449.18-122449.95" + wire $not$issuer_ls180.v:122449$4970_Y + attribute \src "issuer_ls180.v:122451.17-122451.94" + wire $not$issuer_ls180.v:122451$4972_Y + attribute \src "issuer_ls180.v:122454.17-122454.94" + wire $not$issuer_ls180.v:122454$4975_Y + attribute \src "issuer_ls180.v:122448.18-122448.100" + wire $or$issuer_ls180.v:122448$4969_Y + attribute \src "issuer_ls180.v:122450.18-122450.101" + wire $or$issuer_ls180.v:122450$4971_Y + attribute \src "issuer_ls180.v:122453.17-122453.99" + wire $or$issuer_ls180.v:122453$4974_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire \$13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" + wire input 5 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" + wire input 1 \coresync_rst + attribute \src "issuer_ls180.v:122412.7-122412.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire output 2 \q_idx_l + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" + wire \qlq_idx_l + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + wire \qn_idx_l + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire input 4 \r_idx_l + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire input 3 \s_idx_l + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $and $and$issuer_ls180.v:122447$4968 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$7 + connect \Y $and$issuer_ls180.v:122447$4968_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $and $and$issuer_ls180.v:122452$4973 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$1 + connect \Y $and$issuer_ls180.v:122452$4973_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + cell $not $not$issuer_ls180.v:122449$4970 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_idx_l + connect \Y $not$issuer_ls180.v:122449$4970_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $not $not$issuer_ls180.v:122451$4972 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_idx_l + connect \Y $not$issuer_ls180.v:122451$4972_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $not $not$issuer_ls180.v:122454$4975 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_idx_l + connect \Y $not$issuer_ls180.v:122454$4975_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $or $or$issuer_ls180.v:122448$4969 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$9 + connect \B \s_idx_l + connect \Y $or$issuer_ls180.v:122448$4969_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + cell $or $or$issuer_ls180.v:122450$4971 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_idx_l + connect \B \q_int + connect \Y $or$issuer_ls180.v:122450$4971_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $or $or$issuer_ls180.v:122453$4974 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$3 + connect \B \s_idx_l + connect \Y $or$issuer_ls180.v:122453$4974_Y + end + attribute \src "issuer_ls180.v:122412.7-122412.20" + process $proc$issuer_ls180.v:122412$4980 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "issuer_ls180.v:122436.7-122436.19" + process $proc$issuer_ls180.v:122436$4981 + assign { } { } + assign $1\q_int[0:0] 1'0 + sync always + sync init + update \q_int $1\q_int[0:0] + end + attribute \src "issuer_ls180.v:122455.3-122456.27" + process $proc$issuer_ls180.v:122455$4976 + assign { } { } + assign $0\q_int[0:0] \q_int$next + sync posedge \coresync_clk + update \q_int $0\q_int[0:0] + end + attribute \src "issuer_ls180.v:122457.3-122465.6" + process $proc$issuer_ls180.v:122457$4977 + assign { } { } + assign { } { } + assign $0\q_int$next[0:0]$4978 $1\q_int$next[0:0]$4979 + attribute \src "issuer_ls180.v:122458.5-122458.29" + switch \initial + attribute \src "issuer_ls180.v:122458.9-122458.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\q_int$next[0:0]$4979 1'0 + case + assign $1\q_int$next[0:0]$4979 \$5 + end + sync always + update \q_int$next $0\q_int$next[0:0]$4978 + end + connect \$9 $and$issuer_ls180.v:122447$4968_Y + connect \$11 $or$issuer_ls180.v:122448$4969_Y + connect \$13 $not$issuer_ls180.v:122449$4970_Y + connect \$15 $or$issuer_ls180.v:122450$4971_Y + connect \$1 $not$issuer_ls180.v:122451$4972_Y + connect \$3 $and$issuer_ls180.v:122452$4973_Y + connect \$5 $or$issuer_ls180.v:122453$4974_Y + connect \$7 $not$issuer_ls180.v:122454$4975_Y + connect \qlq_idx_l \$15 + connect \qn_idx_l \$13 + connect \q_idx_l \$11 +end +attribute \src "issuer_ls180.v:122473.1-122795.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.imem" +attribute \generator "nMigen" +module \imem + attribute \src "issuer_ls180.v:122752.3-122766.6" + wire width 45 $0\f_badaddr_o$next[44:0]$5044 + attribute \src "issuer_ls180.v:122613.3-122614.39" + wire width 45 $0\f_badaddr_o[44:0] + attribute \src "issuer_ls180.v:122767.3-122778.6" + wire $0\f_busy_o[0:0] + attribute \src "issuer_ls180.v:122734.3-122751.6" + wire $0\f_fetch_err_o$next[0:0]$5040 + attribute \src "issuer_ls180.v:122615.3-122616.43" + wire $0\f_fetch_err_o[0:0] + attribute \src "issuer_ls180.v:122779.3-122791.6" + wire width 64 $0\f_instr_o[63:0] + attribute \src "issuer_ls180.v:122716.3-122733.6" + wire width 45 $0\ibus__adr$next[44:0]$5036 + attribute \src "issuer_ls180.v:122617.3-122618.35" + wire width 45 $0\ibus__adr[44:0] + attribute \src "issuer_ls180.v:122627.3-122649.6" + wire $0\ibus__cyc$next[0:0]$5016 + attribute \src "issuer_ls180.v:122625.3-122626.35" + wire $0\ibus__cyc[0:0] + attribute \src "issuer_ls180.v:122673.3-122695.6" + wire width 8 $0\ibus__sel$next[7:0]$5026 + attribute \src "issuer_ls180.v:122621.3-122622.35" + wire width 8 $0\ibus__sel[7:0] + attribute \src "issuer_ls180.v:122650.3-122672.6" + wire $0\ibus__stb$next[0:0]$5021 + attribute \src "issuer_ls180.v:122623.3-122624.35" + wire $0\ibus__stb[0:0] + attribute \src "issuer_ls180.v:122696.3-122715.6" + wire width 64 $0\ibus_rdata$next[63:0]$5031 + attribute \src "issuer_ls180.v:122619.3-122620.37" + wire width 64 $0\ibus_rdata[63:0] + attribute \src "issuer_ls180.v:122474.7-122474.20" + wire $0\initial[0:0] + attribute \src "issuer_ls180.v:122752.3-122766.6" + wire width 45 $1\f_badaddr_o$next[44:0]$5045 + attribute \src "issuer_ls180.v:122538.14-122538.44" + wire width 45 $1\f_badaddr_o[44:0] + attribute \src "issuer_ls180.v:122767.3-122778.6" + wire $1\f_busy_o[0:0] + attribute \src "issuer_ls180.v:122734.3-122751.6" + wire $1\f_fetch_err_o$next[0:0]$5041 + attribute \src "issuer_ls180.v:122545.7-122545.27" + wire $1\f_fetch_err_o[0:0] + attribute \src "issuer_ls180.v:122779.3-122791.6" + wire width 64 $1\f_instr_o[63:0] + attribute \src "issuer_ls180.v:122716.3-122733.6" + wire width 45 $1\ibus__adr$next[44:0]$5037 + attribute \src "issuer_ls180.v:122559.14-122559.42" + wire width 45 $1\ibus__adr[44:0] + attribute \src "issuer_ls180.v:122627.3-122649.6" + wire $1\ibus__cyc$next[0:0]$5017 + attribute \src "issuer_ls180.v:122564.7-122564.23" + wire $1\ibus__cyc[0:0] + attribute \src "issuer_ls180.v:122673.3-122695.6" + wire width 8 $1\ibus__sel$next[7:0]$5027 + attribute \src "issuer_ls180.v:122573.13-122573.30" + wire width 8 $1\ibus__sel[7:0] + attribute \src "issuer_ls180.v:122650.3-122672.6" + wire $1\ibus__stb$next[0:0]$5022 + attribute \src "issuer_ls180.v:122578.7-122578.23" + wire $1\ibus__stb[0:0] + attribute \src "issuer_ls180.v:122696.3-122715.6" + wire width 64 $1\ibus_rdata$next[63:0]$5032 + attribute \src "issuer_ls180.v:122582.14-122582.47" + wire width 64 $1\ibus_rdata[63:0] + attribute \src "issuer_ls180.v:122752.3-122766.6" + wire width 45 $2\f_badaddr_o$next[44:0]$5046 + attribute \src "issuer_ls180.v:122734.3-122751.6" + wire $2\f_fetch_err_o$next[0:0]$5042 + attribute \src "issuer_ls180.v:122716.3-122733.6" + wire width 45 $2\ibus__adr$next[44:0]$5038 + attribute \src "issuer_ls180.v:122627.3-122649.6" + wire $2\ibus__cyc$next[0:0]$5018 + attribute \src "issuer_ls180.v:122673.3-122695.6" + wire width 8 $2\ibus__sel$next[7:0]$5028 + attribute \src "issuer_ls180.v:122650.3-122672.6" + wire $2\ibus__stb$next[0:0]$5023 + attribute \src "issuer_ls180.v:122696.3-122715.6" + wire width 64 $2\ibus_rdata$next[63:0]$5033 + attribute \src "issuer_ls180.v:122627.3-122649.6" + wire $3\ibus__cyc$next[0:0]$5019 + attribute \src "issuer_ls180.v:122673.3-122695.6" + wire width 8 $3\ibus__sel$next[7:0]$5029 + attribute \src "issuer_ls180.v:122650.3-122672.6" + wire $3\ibus__stb$next[0:0]$5024 + attribute \src "issuer_ls180.v:122696.3-122715.6" + wire width 64 $3\ibus_rdata$next[63:0]$5034 + attribute \src "issuer_ls180.v:122589.18-122589.110" + wire $and$issuer_ls180.v:122589$4984_Y + attribute \src "issuer_ls180.v:122595.18-122595.110" + wire $and$issuer_ls180.v:122595$4990_Y + attribute \src "issuer_ls180.v:122600.18-122600.110" + wire $and$issuer_ls180.v:122600$4995_Y + attribute \src "issuer_ls180.v:122603.17-122603.108" + wire $and$issuer_ls180.v:122603$4998_Y + attribute \src "issuer_ls180.v:122606.18-122606.110" + wire $and$issuer_ls180.v:122606$5001_Y + attribute \src "issuer_ls180.v:122607.18-122607.115" + wire $and$issuer_ls180.v:122607$5002_Y + attribute \src "issuer_ls180.v:122609.18-122609.115" + wire $and$issuer_ls180.v:122609$5004_Y + attribute \src "issuer_ls180.v:122588.18-122588.105" + wire $not$issuer_ls180.v:122588$4983_Y + attribute \src "issuer_ls180.v:122591.18-122591.105" + wire $not$issuer_ls180.v:122591$4986_Y + attribute \src "issuer_ls180.v:122592.17-122592.104" + wire $not$issuer_ls180.v:122592$4987_Y + attribute \src "issuer_ls180.v:122594.18-122594.105" + wire $not$issuer_ls180.v:122594$4989_Y + attribute \src "issuer_ls180.v:122597.18-122597.105" + wire $not$issuer_ls180.v:122597$4992_Y + attribute \src "issuer_ls180.v:122599.18-122599.105" + wire $not$issuer_ls180.v:122599$4994_Y + attribute \src "issuer_ls180.v:122602.18-122602.105" + wire $not$issuer_ls180.v:122602$4997_Y + attribute \src "issuer_ls180.v:122605.18-122605.105" + wire $not$issuer_ls180.v:122605$5000_Y + attribute \src "issuer_ls180.v:122608.18-122608.105" + wire $not$issuer_ls180.v:122608$5003_Y + attribute \src "issuer_ls180.v:122610.18-122610.105" + wire $not$issuer_ls180.v:122610$5005_Y + attribute \src "issuer_ls180.v:122612.17-122612.104" + wire $not$issuer_ls180.v:122612$5007_Y + attribute \src "issuer_ls180.v:122587.17-122587.103" + wire $or$issuer_ls180.v:122587$4982_Y + attribute \src "issuer_ls180.v:122590.18-122590.115" + wire $or$issuer_ls180.v:122590$4985_Y + attribute \src "issuer_ls180.v:122593.18-122593.106" + wire $or$issuer_ls180.v:122593$4988_Y + attribute \src "issuer_ls180.v:122596.18-122596.115" + wire $or$issuer_ls180.v:122596$4991_Y + attribute \src "issuer_ls180.v:122598.18-122598.106" + wire $or$issuer_ls180.v:122598$4993_Y + attribute \src "issuer_ls180.v:122601.18-122601.115" + wire $or$issuer_ls180.v:122601$4996_Y + attribute \src "issuer_ls180.v:122604.18-122604.106" + wire $or$issuer_ls180.v:122604$4999_Y + attribute \src "issuer_ls180.v:122611.17-122611.114" + wire $or$issuer_ls180.v:122611$5006_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:68" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:68" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:68" + wire \$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:61" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:61" + wire \$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:61" + wire \$19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:68" + wire \$21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:68" + wire \$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:61" + wire \$25 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:61" + wire \$27 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:61" + wire \$29 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:68" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:68" + wire \$31 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:68" + wire \$33 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:61" + wire \$35 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:61" + wire \$37 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:61" + wire \$39 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:68" + wire \$41 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:68" + wire \$43 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:76" + wire \$45 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:81" + wire \$47 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:76" + wire \$49 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:61" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:81" + wire \$51 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:61" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:61" + wire \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:31" + wire \a_busy_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:24" + wire width 48 input 1 \a_pc_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:25" + wire \a_stall_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:26" + wire input 2 \a_valid_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:140" + wire input 14 \clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:35" + wire width 45 \f_badaddr_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:35" + wire width 45 \f_badaddr_o$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:32" + wire output 4 \f_busy_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:34" + wire \f_fetch_err_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:34" + wire \f_fetch_err_o$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:33" + wire width 64 output 5 \f_instr_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:27" + wire \f_stall_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:28" + wire input 3 \f_valid_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" + wire input 8 \ibus__ack + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" + wire width 45 output 13 \ibus__adr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" + wire width 45 \ibus__adr$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" + wire output 7 \ibus__cyc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" + wire \ibus__cyc$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" + wire width 64 input 12 \ibus__dat_r + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" + wire input 9 \ibus__err + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" + wire width 8 output 11 \ibus__sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" + wire width 8 \ibus__sel$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" + wire output 10 \ibus__stb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" + wire \ibus__stb$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:59" + wire width 64 \ibus_rdata + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:59" + wire width 64 \ibus_rdata$next + attribute \src "issuer_ls180.v:122474.7-122474.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:140" + wire input 6 \rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:68" + cell $and $and$issuer_ls180.v:122589$4984 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \a_valid_i + connect \B \$11 + connect \Y $and$issuer_ls180.v:122589$4984_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:68" + cell $and $and$issuer_ls180.v:122595$4990 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \a_valid_i + connect \B \$21 + connect \Y $and$issuer_ls180.v:122595$4990_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:68" + cell $and $and$issuer_ls180.v:122600$4995 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \a_valid_i + connect \B \$31 + connect \Y $and$issuer_ls180.v:122600$4995_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:68" + cell $and $and$issuer_ls180.v:122603$4998 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \a_valid_i + connect \B \$1 + connect \Y $and$issuer_ls180.v:122603$4998_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:68" + cell $and $and$issuer_ls180.v:122606$5001 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \a_valid_i + connect \B \$41 + connect \Y $and$issuer_ls180.v:122606$5001_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:76" + cell $and $and$issuer_ls180.v:122607$5002 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \ibus__cyc + connect \B \ibus__err + connect \Y $and$issuer_ls180.v:122607$5002_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:76" + cell $and $and$issuer_ls180.v:122609$5004 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \ibus__cyc + connect \B \ibus__err + connect \Y $and$issuer_ls180.v:122609$5004_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:68" + cell $not $not$issuer_ls180.v:122588$4983 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \a_stall_i + connect \Y $not$issuer_ls180.v:122588$4983_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:61" + cell $not $not$issuer_ls180.v:122591$4986 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \f_valid_i + connect \Y $not$issuer_ls180.v:122591$4986_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:68" + cell $not $not$issuer_ls180.v:122592$4987 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \a_stall_i + connect \Y $not$issuer_ls180.v:122592$4987_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:68" + cell $not $not$issuer_ls180.v:122594$4989 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \a_stall_i + connect \Y $not$issuer_ls180.v:122594$4989_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:61" + cell $not $not$issuer_ls180.v:122597$4992 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \f_valid_i + connect \Y $not$issuer_ls180.v:122597$4992_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:68" + cell $not $not$issuer_ls180.v:122599$4994 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \a_stall_i + connect \Y $not$issuer_ls180.v:122599$4994_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:61" + cell $not $not$issuer_ls180.v:122602$4997 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \f_valid_i + connect \Y $not$issuer_ls180.v:122602$4997_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:68" + cell $not $not$issuer_ls180.v:122605$5000 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \a_stall_i + connect \Y $not$issuer_ls180.v:122605$5000_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:81" + cell $not $not$issuer_ls180.v:122608$5003 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \f_stall_i + connect \Y $not$issuer_ls180.v:122608$5003_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:81" + cell $not $not$issuer_ls180.v:122610$5005 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \f_stall_i + connect \Y $not$issuer_ls180.v:122610$5005_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:61" + cell $not $not$issuer_ls180.v:122612$5007 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \f_valid_i + connect \Y $not$issuer_ls180.v:122612$5007_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:61" + cell $or $or$issuer_ls180.v:122587$4982 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$5 + connect \B \$7 + connect \Y $or$issuer_ls180.v:122587$4982_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:61" + cell $or $or$issuer_ls180.v:122590$4985 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \ibus__ack + connect \B \ibus__err + connect \Y $or$issuer_ls180.v:122590$4985_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:61" + cell $or $or$issuer_ls180.v:122593$4988 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$15 + connect \B \$17 + connect \Y $or$issuer_ls180.v:122593$4988_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:61" + cell $or $or$issuer_ls180.v:122596$4991 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \ibus__ack + connect \B \ibus__err + connect \Y $or$issuer_ls180.v:122596$4991_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:61" + cell $or $or$issuer_ls180.v:122598$4993 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$25 + connect \B \$27 + connect \Y $or$issuer_ls180.v:122598$4993_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:61" + cell $or $or$issuer_ls180.v:122601$4996 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \ibus__ack + connect \B \ibus__err + connect \Y $or$issuer_ls180.v:122601$4996_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:61" + cell $or $or$issuer_ls180.v:122604$4999 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$35 + connect \B \$37 + connect \Y $or$issuer_ls180.v:122604$4999_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:61" + cell $or $or$issuer_ls180.v:122611$5006 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \ibus__ack + connect \B \ibus__err + connect \Y $or$issuer_ls180.v:122611$5006_Y + end + attribute \src "issuer_ls180.v:122474.7-122474.20" + process $proc$issuer_ls180.v:122474$5049 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "issuer_ls180.v:122538.14-122538.44" + process $proc$issuer_ls180.v:122538$5050 + assign { } { } + assign $1\f_badaddr_o[44:0] 45'000000000000000000000000000000000000000000000 + sync always + sync init + update \f_badaddr_o $1\f_badaddr_o[44:0] + end + attribute \src "issuer_ls180.v:122545.7-122545.27" + process $proc$issuer_ls180.v:122545$5051 + assign { } { } + assign $1\f_fetch_err_o[0:0] 1'0 + sync always + sync init + update \f_fetch_err_o $1\f_fetch_err_o[0:0] + end + attribute \src "issuer_ls180.v:122559.14-122559.42" + process $proc$issuer_ls180.v:122559$5052 + assign { } { } + assign $1\ibus__adr[44:0] 45'000000000000000000000000000000000000000000000 + sync always + sync init + update \ibus__adr $1\ibus__adr[44:0] + end + attribute \src "issuer_ls180.v:122564.7-122564.23" + process $proc$issuer_ls180.v:122564$5053 + assign { } { } + assign $1\ibus__cyc[0:0] 1'0 + sync always + sync init + update \ibus__cyc $1\ibus__cyc[0:0] + end + attribute \src "issuer_ls180.v:122573.13-122573.30" + process $proc$issuer_ls180.v:122573$5054 + assign { } { } + assign $1\ibus__sel[7:0] 8'00000000 + sync always + sync init + update \ibus__sel $1\ibus__sel[7:0] + end + attribute \src "issuer_ls180.v:122578.7-122578.23" + process $proc$issuer_ls180.v:122578$5055 + assign { } { } + assign $1\ibus__stb[0:0] 1'0 + sync always + sync init + update \ibus__stb $1\ibus__stb[0:0] + end + attribute \src "issuer_ls180.v:122582.14-122582.47" + process $proc$issuer_ls180.v:122582$5056 + assign { } { } + assign $1\ibus_rdata[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \ibus_rdata $1\ibus_rdata[63:0] + end + attribute \src "issuer_ls180.v:122613.3-122614.39" + process $proc$issuer_ls180.v:122613$5008 + assign { } { } + assign $0\f_badaddr_o[44:0] \f_badaddr_o$next + sync posedge \clk + update \f_badaddr_o $0\f_badaddr_o[44:0] + end + attribute \src "issuer_ls180.v:122615.3-122616.43" + process $proc$issuer_ls180.v:122615$5009 + assign { } { } + assign $0\f_fetch_err_o[0:0] \f_fetch_err_o$next + sync posedge \clk + update \f_fetch_err_o $0\f_fetch_err_o[0:0] + end + attribute \src "issuer_ls180.v:122617.3-122618.35" + process $proc$issuer_ls180.v:122617$5010 + assign { } { } + assign $0\ibus__adr[44:0] \ibus__adr$next + sync posedge \clk + update \ibus__adr $0\ibus__adr[44:0] + end + attribute \src "issuer_ls180.v:122619.3-122620.37" + process $proc$issuer_ls180.v:122619$5011 + assign { } { } + assign $0\ibus_rdata[63:0] \ibus_rdata$next + sync posedge \clk + update \ibus_rdata $0\ibus_rdata[63:0] + end + attribute \src "issuer_ls180.v:122621.3-122622.35" + process $proc$issuer_ls180.v:122621$5012 + assign { } { } + assign $0\ibus__sel[7:0] \ibus__sel$next + sync posedge \clk + update \ibus__sel $0\ibus__sel[7:0] + end + attribute \src "issuer_ls180.v:122623.3-122624.35" + process $proc$issuer_ls180.v:122623$5013 + assign { } { } + assign $0\ibus__stb[0:0] \ibus__stb$next + sync posedge \clk + update \ibus__stb $0\ibus__stb[0:0] + end + attribute \src "issuer_ls180.v:122625.3-122626.35" + process $proc$issuer_ls180.v:122625$5014 + assign { } { } + assign $0\ibus__cyc[0:0] \ibus__cyc$next + sync posedge \clk + update \ibus__cyc $0\ibus__cyc[0:0] + end + attribute \src "issuer_ls180.v:122627.3-122649.6" + process $proc$issuer_ls180.v:122627$5015 + assign { } { } + assign { } { } + assign { } { } + assign $0\ibus__cyc$next[0:0]$5016 $3\ibus__cyc$next[0:0]$5019 + attribute \src "issuer_ls180.v:122628.5-122628.29" + switch \initial + attribute \src "issuer_ls180.v:122628.9-122628.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:60" + switch { \$3 \ibus__cyc } + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\ibus__cyc$next[0:0]$5017 $2\ibus__cyc$next[0:0]$5018 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:61" + switch \$9 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\ibus__cyc$next[0:0]$5018 1'0 + case + assign $2\ibus__cyc$next[0:0]$5018 \ibus__cyc + end + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\ibus__cyc$next[0:0]$5017 1'1 + case + assign $1\ibus__cyc$next[0:0]$5017 \ibus__cyc + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\ibus__cyc$next[0:0]$5019 1'0 + case + assign $3\ibus__cyc$next[0:0]$5019 $1\ibus__cyc$next[0:0]$5017 + end + sync always + update \ibus__cyc$next $0\ibus__cyc$next[0:0]$5016 + end + attribute \src "issuer_ls180.v:122650.3-122672.6" + process $proc$issuer_ls180.v:122650$5020 + assign { } { } + assign { } { } + assign { } { } + assign $0\ibus__stb$next[0:0]$5021 $3\ibus__stb$next[0:0]$5024 + attribute \src "issuer_ls180.v:122651.5-122651.29" + switch \initial + attribute \src "issuer_ls180.v:122651.9-122651.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:60" + switch { \$13 \ibus__cyc } + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\ibus__stb$next[0:0]$5022 $2\ibus__stb$next[0:0]$5023 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:61" + switch \$19 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\ibus__stb$next[0:0]$5023 1'0 + case + assign $2\ibus__stb$next[0:0]$5023 \ibus__stb + end + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\ibus__stb$next[0:0]$5022 1'1 + case + assign $1\ibus__stb$next[0:0]$5022 \ibus__stb + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\ibus__stb$next[0:0]$5024 1'0 + case + assign $3\ibus__stb$next[0:0]$5024 $1\ibus__stb$next[0:0]$5022 + end + sync always + update \ibus__stb$next $0\ibus__stb$next[0:0]$5021 + end + attribute \src "issuer_ls180.v:122673.3-122695.6" + process $proc$issuer_ls180.v:122673$5025 + assign { } { } + assign { } { } + assign { } { } + assign $0\ibus__sel$next[7:0]$5026 $3\ibus__sel$next[7:0]$5029 + attribute \src "issuer_ls180.v:122674.5-122674.29" + switch \initial + attribute \src "issuer_ls180.v:122674.9-122674.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:60" + switch { \$23 \ibus__cyc } + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\ibus__sel$next[7:0]$5027 $2\ibus__sel$next[7:0]$5028 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:61" + switch \$29 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\ibus__sel$next[7:0]$5028 8'00000000 + case + assign $2\ibus__sel$next[7:0]$5028 \ibus__sel + end + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\ibus__sel$next[7:0]$5027 8'11111111 + case + assign $1\ibus__sel$next[7:0]$5027 \ibus__sel + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\ibus__sel$next[7:0]$5029 8'00000000 + case + assign $3\ibus__sel$next[7:0]$5029 $1\ibus__sel$next[7:0]$5027 + end + sync always + update \ibus__sel$next $0\ibus__sel$next[7:0]$5026 + end + attribute \src "issuer_ls180.v:122696.3-122715.6" + process $proc$issuer_ls180.v:122696$5030 + assign { } { } + assign { } { } + assign { } { } + assign $0\ibus_rdata$next[63:0]$5031 $3\ibus_rdata$next[63:0]$5034 + attribute \src "issuer_ls180.v:122697.5-122697.29" + switch \initial + attribute \src "issuer_ls180.v:122697.9-122697.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:60" + switch { \$33 \ibus__cyc } + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\ibus_rdata$next[63:0]$5032 $2\ibus_rdata$next[63:0]$5033 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:61" + switch \$39 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\ibus_rdata$next[63:0]$5033 \ibus__dat_r + case + assign $2\ibus_rdata$next[63:0]$5033 \ibus_rdata + end + case + assign $1\ibus_rdata$next[63:0]$5032 \ibus_rdata + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\ibus_rdata$next[63:0]$5034 64'0000000000000000000000000000000000000000000000000000000000000000 + case + assign $3\ibus_rdata$next[63:0]$5034 $1\ibus_rdata$next[63:0]$5032 + end + sync always + update \ibus_rdata$next $0\ibus_rdata$next[63:0]$5031 + end + attribute \src "issuer_ls180.v:122716.3-122733.6" + process $proc$issuer_ls180.v:122716$5035 + assign { } { } + assign { } { } + assign { } { } + assign $0\ibus__adr$next[44:0]$5036 $2\ibus__adr$next[44:0]$5038 + attribute \src "issuer_ls180.v:122717.5-122717.29" + switch \initial + attribute \src "issuer_ls180.v:122717.9-122717.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:60" + switch { \$43 \ibus__cyc } + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'-1 + assign $1\ibus__adr$next[44:0]$5037 \ibus__adr + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\ibus__adr$next[44:0]$5037 \a_pc_i [47:3] + case + assign $1\ibus__adr$next[44:0]$5037 \ibus__adr + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\ibus__adr$next[44:0]$5038 45'000000000000000000000000000000000000000000000 + case + assign $2\ibus__adr$next[44:0]$5038 $1\ibus__adr$next[44:0]$5037 + end + sync always + update \ibus__adr$next $0\ibus__adr$next[44:0]$5036 + end + attribute \src "issuer_ls180.v:122734.3-122751.6" + process $proc$issuer_ls180.v:122734$5039 + assign { } { } + assign { } { } + assign { } { } + assign $0\f_fetch_err_o$next[0:0]$5040 $2\f_fetch_err_o$next[0:0]$5042 + attribute \src "issuer_ls180.v:122735.5-122735.29" + switch \initial + attribute \src "issuer_ls180.v:122735.9-122735.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:76" + switch { \$47 \$45 } + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\f_fetch_err_o$next[0:0]$5041 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\f_fetch_err_o$next[0:0]$5041 1'0 + case + assign $1\f_fetch_err_o$next[0:0]$5041 \f_fetch_err_o + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\f_fetch_err_o$next[0:0]$5042 1'0 + case + assign $2\f_fetch_err_o$next[0:0]$5042 $1\f_fetch_err_o$next[0:0]$5041 + end + sync always + update \f_fetch_err_o$next $0\f_fetch_err_o$next[0:0]$5040 + end + attribute \src "issuer_ls180.v:122752.3-122766.6" + process $proc$issuer_ls180.v:122752$5043 + assign { } { } + assign { } { } + assign { } { } + assign $0\f_badaddr_o$next[44:0]$5044 $2\f_badaddr_o$next[44:0]$5046 + attribute \src "issuer_ls180.v:122753.5-122753.29" + switch \initial + attribute \src "issuer_ls180.v:122753.9-122753.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:76" + switch { \$51 \$49 } + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\f_badaddr_o$next[44:0]$5045 \ibus__adr + case + assign $1\f_badaddr_o$next[44:0]$5045 \f_badaddr_o + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\f_badaddr_o$next[44:0]$5046 45'000000000000000000000000000000000000000000000 + case + assign $2\f_badaddr_o$next[44:0]$5046 $1\f_badaddr_o$next[44:0]$5045 + end + sync always + update \f_badaddr_o$next $0\f_badaddr_o$next[44:0]$5044 + end + attribute \src "issuer_ls180.v:122767.3-122778.6" + process $proc$issuer_ls180.v:122767$5047 + assign { } { } + assign $0\f_busy_o[0:0] $1\f_busy_o[0:0] + attribute \src "issuer_ls180.v:122768.5-122768.29" + switch \initial + attribute \src "issuer_ls180.v:122768.9-122768.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:86" + switch \f_fetch_err_o + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\f_busy_o[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case + assign { } { } + assign $1\f_busy_o[0:0] \ibus__cyc + end + sync always + update \f_busy_o $0\f_busy_o[0:0] + end + attribute \src "issuer_ls180.v:122779.3-122791.6" + process $proc$issuer_ls180.v:122779$5048 + assign { } { } + assign { } { } + assign $0\f_instr_o[63:0] $1\f_instr_o[63:0] + attribute \src "issuer_ls180.v:122780.5-122780.29" + switch \initial + attribute \src "issuer_ls180.v:122780.9-122780.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:86" + switch \f_fetch_err_o + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign $1\f_instr_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "issuer_ls180.v:0.0-0.0" + case + assign { } { } + assign $1\f_instr_o[63:0] \ibus_rdata + end + sync always + update \f_instr_o $0\f_instr_o[63:0] + end + connect \$9 $or$issuer_ls180.v:122587$4982_Y + connect \$11 $not$issuer_ls180.v:122588$4983_Y + connect \$13 $and$issuer_ls180.v:122589$4984_Y + connect \$15 $or$issuer_ls180.v:122590$4985_Y + connect \$17 $not$issuer_ls180.v:122591$4986_Y + connect \$1 $not$issuer_ls180.v:122592$4987_Y + connect \$19 $or$issuer_ls180.v:122593$4988_Y + connect \$21 $not$issuer_ls180.v:122594$4989_Y + connect \$23 $and$issuer_ls180.v:122595$4990_Y + connect \$25 $or$issuer_ls180.v:122596$4991_Y + connect \$27 $not$issuer_ls180.v:122597$4992_Y + connect \$29 $or$issuer_ls180.v:122598$4993_Y + connect \$31 $not$issuer_ls180.v:122599$4994_Y + connect \$33 $and$issuer_ls180.v:122600$4995_Y + connect \$35 $or$issuer_ls180.v:122601$4996_Y + connect \$37 $not$issuer_ls180.v:122602$4997_Y + connect \$3 $and$issuer_ls180.v:122603$4998_Y + connect \$39 $or$issuer_ls180.v:122604$4999_Y + connect \$41 $not$issuer_ls180.v:122605$5000_Y + connect \$43 $and$issuer_ls180.v:122606$5001_Y + connect \$45 $and$issuer_ls180.v:122607$5002_Y + connect \$47 $not$issuer_ls180.v:122608$5003_Y + connect \$49 $and$issuer_ls180.v:122609$5004_Y + connect \$51 $not$issuer_ls180.v:122610$5005_Y + connect \$5 $or$issuer_ls180.v:122611$5006_Y + connect \$7 $not$issuer_ls180.v:122612$5007_Y + connect \a_stall_i 1'0 + connect \f_stall_i 1'0 + connect \a_busy_o \ibus__cyc +end +attribute \src "issuer_ls180.v:122799.1-123120.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.fus.alu0.alu_alu0.pipe1.input" +attribute \generator "nMigen" +module \input + attribute \src "issuer_ls180.v:123083.3-123094.6" + wire width 64 $0\a[63:0] + attribute \src "issuer_ls180.v:122800.7-122800.20" + wire $0\initial[0:0] + attribute \src "issuer_ls180.v:123095.3-123113.6" + wire width 2 $0\xer_ca$23[1:0]$5060 + attribute \src "issuer_ls180.v:123083.3-123094.6" + wire width 64 $1\a[63:0] + attribute \src "issuer_ls180.v:123095.3-123113.6" + wire width 2 $1\xer_ca$23[1:0]$5061 + attribute \src "issuer_ls180.v:123082.18-123082.100" + wire width 64 $not$issuer_ls180.v:123082$5057_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:28" + wire width 64 \$24 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:20" + wire width 64 \a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 input 17 \alu_op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 output 40 \alu_op__data_len$18 + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 input 2 \alu_op__fn_unit + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 output 25 \alu_op__fn_unit$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 input 3 \alu_op__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 output 26 \alu_op__imm_data__data$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 4 \alu_op__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 27 \alu_op__imm_data__ok$5 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 input 13 \alu_op__input_carry + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 output 36 \alu_op__input_carry$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 18 \alu_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 output 41 \alu_op__insn$19 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 input 1 \alu_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 output 24 \alu_op__insn_type$2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 9 \alu_op__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 32 \alu_op__invert_in$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 11 \alu_op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 34 \alu_op__invert_out$12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 15 \alu_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 38 \alu_op__is_32bit$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 16 \alu_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 39 \alu_op__is_signed$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 7 \alu_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 30 \alu_op__oe__oe$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 8 \alu_op__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 31 \alu_op__oe__ok$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 14 \alu_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 37 \alu_op__output_carry$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 6 \alu_op__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 29 \alu_op__rc__ok$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 5 \alu_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 28 \alu_op__rc__rc$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 12 \alu_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 35 \alu_op__write_cr0$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 10 \alu_op__zero_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 33 \alu_op__zero_a$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:39" + wire width 64 \b + attribute \src "issuer_ls180.v:122800.7-122800.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 input 46 \muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 output 23 \muxid$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 19 \ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 output 42 \ra$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 20 \rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 output 43 \rb$21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 2 input 22 \xer_ca + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 2 output 45 \xer_ca$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire input 21 \xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire output 44 \xer_so$22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:28" + cell $not $not$issuer_ls180.v:123082$5057 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A \ra + connect \Y $not$issuer_ls180.v:123082$5057_Y + end + attribute \src "issuer_ls180.v:122800.7-122800.20" + process $proc$issuer_ls180.v:122800$5062 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "issuer_ls180.v:123083.3-123094.6" + process $proc$issuer_ls180.v:123083$5058 + assign { } { } + assign $0\a[63:0] $1\a[63:0] + attribute \src "issuer_ls180.v:123084.5-123084.29" + switch \initial + attribute \src "issuer_ls180.v:123084.9-123084.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:27" + switch \alu_op__invert_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\a[63:0] \$24 + attribute \src "issuer_ls180.v:0.0-0.0" + case + assign { } { } + assign $1\a[63:0] \ra + end + sync always + update \a $0\a[63:0] + end + attribute \src "issuer_ls180.v:123095.3-123113.6" + process $proc$issuer_ls180.v:123095$5059 + assign { } { } + assign { } { } + assign $0\xer_ca$23[1:0]$5060 $1\xer_ca$23[1:0]$5061 + attribute \src "issuer_ls180.v:123096.5-123096.29" + switch \initial + attribute \src "issuer_ls180.v:123096.9-123096.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:55" + switch \alu_op__input_carry + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\xer_ca$23[1:0]$5061 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\xer_ca$23[1:0]$5061 2'11 + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\xer_ca$23[1:0]$5061 \xer_ca + case + assign $1\xer_ca$23[1:0]$5061 2'00 + end + sync always + update \xer_ca$23 $0\xer_ca$23[1:0]$5060 + end + connect \$24 $not$issuer_ls180.v:123082$5057_Y + connect { \alu_op__insn$19 \alu_op__data_len$18 \alu_op__is_signed$17 \alu_op__is_32bit$16 \alu_op__output_carry$15 \alu_op__input_carry$14 \alu_op__write_cr0$13 \alu_op__invert_out$12 \alu_op__zero_a$11 \alu_op__invert_in$10 \alu_op__oe__ok$9 \alu_op__oe__oe$8 \alu_op__rc__ok$7 \alu_op__rc__rc$6 \alu_op__imm_data__ok$5 \alu_op__imm_data__data$4 \alu_op__fn_unit$3 \alu_op__insn_type$2 } { \alu_op__insn \alu_op__data_len \alu_op__is_signed \alu_op__is_32bit \alu_op__output_carry \alu_op__input_carry \alu_op__write_cr0 \alu_op__invert_out \alu_op__zero_a \alu_op__invert_in \alu_op__oe__ok \alu_op__oe__oe \alu_op__rc__ok \alu_op__rc__rc \alu_op__imm_data__ok \alu_op__imm_data__data \alu_op__fn_unit \alu_op__insn_type } + connect \muxid$1 \muxid + connect \xer_so$22 \xer_so + connect \rb$21 \rb + connect \b \rb + connect \ra$20 \a +end +attribute \src "issuer_ls180.v:123124.1-123428.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.fus.shiftrot0.alu_shift_rot0.pipe1.input" +attribute \generator "nMigen" +module \input$110 + attribute \src "issuer_ls180.v:123125.7-123125.20" + wire $0\initial[0:0] + attribute \src "issuer_ls180.v:123401.3-123419.6" + wire width 2 $0\xer_ca$22[1:0]$5064 + attribute \src "issuer_ls180.v:123401.3-123419.6" + wire width 2 $1\xer_ca$22[1:0]$5065 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:20" + wire width 64 \a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:39" + wire width 64 \b + attribute \src "issuer_ls180.v:123125.7-123125.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 input 44 \muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 output 22 \muxid$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 17 \ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 output 39 \ra$18 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 18 \rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 output 40 \rb$19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 19 \rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 output 41 \rc$20 + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 input 2 \sr_op__fn_unit + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 output 24 \sr_op__fn_unit$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 input 3 \sr_op__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 output 25 \sr_op__imm_data__data$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 4 \sr_op__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 26 \sr_op__imm_data__ok$5 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 input 10 \sr_op__input_carry + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 output 32 \sr_op__input_carry$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 12 \sr_op__input_cr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 34 \sr_op__input_cr$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 16 \sr_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 output 38 \sr_op__insn$17 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 input 1 \sr_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 output 23 \sr_op__insn_type$2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 14 \sr_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 36 \sr_op__is_32bit$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 15 \sr_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 37 \sr_op__is_signed$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 7 \sr_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 29 \sr_op__oe__oe$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 8 \sr_op__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 30 \sr_op__oe__ok$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 11 \sr_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 33 \sr_op__output_carry$12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 13 \sr_op__output_cr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 35 \sr_op__output_cr$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 6 \sr_op__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 28 \sr_op__rc__ok$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 5 \sr_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 27 \sr_op__rc__rc$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 9 \sr_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 31 \sr_op__write_cr0$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 2 input 21 \xer_ca + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 2 output 43 \xer_ca$22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire input 20 \xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire output 42 \xer_so$21 + attribute \src "issuer_ls180.v:123125.7-123125.20" + process $proc$issuer_ls180.v:123125$5066 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "issuer_ls180.v:123401.3-123419.6" + process $proc$issuer_ls180.v:123401$5063 + assign { } { } + assign { } { } + assign $0\xer_ca$22[1:0]$5064 $1\xer_ca$22[1:0]$5065 + attribute \src "issuer_ls180.v:123402.5-123402.29" + switch \initial + attribute \src "issuer_ls180.v:123402.9-123402.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:55" + switch \sr_op__input_carry + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\xer_ca$22[1:0]$5065 2'00 + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\xer_ca$22[1:0]$5065 2'11 + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\xer_ca$22[1:0]$5065 \xer_ca + case + assign $1\xer_ca$22[1:0]$5065 2'00 + end + sync always + update \xer_ca$22 $0\xer_ca$22[1:0]$5064 + end + connect \rc$20 \rc + connect { \sr_op__insn$17 \sr_op__is_signed$16 \sr_op__is_32bit$15 \sr_op__output_cr$14 \sr_op__input_cr$13 \sr_op__output_carry$12 \sr_op__input_carry$11 \sr_op__write_cr0$10 \sr_op__oe__ok$9 \sr_op__oe__oe$8 \sr_op__rc__ok$7 \sr_op__rc__rc$6 \sr_op__imm_data__ok$5 \sr_op__imm_data__data$4 \sr_op__fn_unit$3 \sr_op__insn_type$2 } { \sr_op__insn \sr_op__is_signed \sr_op__is_32bit \sr_op__output_cr \sr_op__input_cr \sr_op__output_carry \sr_op__input_carry \sr_op__write_cr0 \sr_op__oe__ok \sr_op__oe__oe \sr_op__rc__ok \sr_op__rc__rc \sr_op__imm_data__ok \sr_op__imm_data__data \sr_op__fn_unit \sr_op__insn_type } + connect \muxid$1 \muxid + connect \xer_so$21 \xer_so + connect \rb$19 \b + connect \b \rb + connect \ra$18 \a + connect \a \ra +end +attribute \src "issuer_ls180.v:123432.1-123729.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.fus.logical0.alu_logical0.logical_pipe1.input" +attribute \generator "nMigen" +module \input$47 + attribute \src "issuer_ls180.v:123711.3-123722.6" + wire width 64 $0\b[63:0] + attribute \src "issuer_ls180.v:123433.7-123433.20" + wire $0\initial[0:0] + attribute \src "issuer_ls180.v:123711.3-123722.6" + wire width 64 $1\b[63:0] + attribute \src "issuer_ls180.v:123710.18-123710.100" + wire width 64 $not$issuer_ls180.v:123710$5067_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:43" + wire width 64 \$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:20" + wire width 64 \a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:39" + wire width 64 \b + attribute \src "issuer_ls180.v:123433.7-123433.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 input 17 \logical_op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 output 39 \logical_op__data_len$18 + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 input 2 \logical_op__fn_unit + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 output 24 \logical_op__fn_unit$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 input 3 \logical_op__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 output 25 \logical_op__imm_data__data$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 4 \logical_op__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 26 \logical_op__imm_data__ok$5 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 input 11 \logical_op__input_carry + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 output 33 \logical_op__input_carry$12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 18 \logical_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 output 40 \logical_op__insn$19 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 input 1 \logical_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 output 23 \logical_op__insn_type$2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 9 \logical_op__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 31 \logical_op__invert_in$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 12 \logical_op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 34 \logical_op__invert_out$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 15 \logical_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 37 \logical_op__is_32bit$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 16 \logical_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 38 \logical_op__is_signed$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 7 \logical_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 29 \logical_op__oe__oe$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 8 \logical_op__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 30 \logical_op__oe__ok$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 14 \logical_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 36 \logical_op__output_carry$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 6 \logical_op__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 28 \logical_op__rc__ok$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 5 \logical_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 27 \logical_op__rc__rc$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 13 \logical_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 35 \logical_op__write_cr0$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 10 \logical_op__zero_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 32 \logical_op__zero_a$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 input 44 \muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 output 22 \muxid$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 19 \ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 output 41 \ra$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 20 \rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 output 42 \rb$21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire input 21 \xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire output 43 \xer_so$22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:43" + cell $not $not$issuer_ls180.v:123710$5067 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A \rb + connect \Y $not$issuer_ls180.v:123710$5067_Y + end + attribute \src "issuer_ls180.v:123433.7-123433.20" + process $proc$issuer_ls180.v:123433$5069 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "issuer_ls180.v:123711.3-123722.6" + process $proc$issuer_ls180.v:123711$5068 + assign { } { } + assign $0\b[63:0] $1\b[63:0] + attribute \src "issuer_ls180.v:123712.5-123712.29" + switch \initial + attribute \src "issuer_ls180.v:123712.9-123712.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:42" + switch \logical_op__invert_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\b[63:0] \$23 + attribute \src "issuer_ls180.v:0.0-0.0" + case + assign { } { } + assign $1\b[63:0] \rb + end + sync always + update \b $0\b[63:0] + end + connect \$23 $not$issuer_ls180.v:123710$5067_Y + connect { \logical_op__insn$19 \logical_op__data_len$18 \logical_op__is_signed$17 \logical_op__is_32bit$16 \logical_op__output_carry$15 \logical_op__write_cr0$14 \logical_op__invert_out$13 \logical_op__input_carry$12 \logical_op__zero_a$11 \logical_op__invert_in$10 \logical_op__oe__ok$9 \logical_op__oe__oe$8 \logical_op__rc__ok$7 \logical_op__rc__rc$6 \logical_op__imm_data__ok$5 \logical_op__imm_data__data$4 \logical_op__fn_unit$3 \logical_op__insn_type$2 } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in \logical_op__oe__ok \logical_op__oe__oe \logical_op__rc__ok \logical_op__rc__rc \logical_op__imm_data__ok \logical_op__imm_data__data \logical_op__fn_unit \logical_op__insn_type } + connect \muxid$1 \muxid + connect \xer_so$22 \xer_so + connect \rb$21 \b + connect \ra$20 \a + connect \a \ra +end +attribute \src "issuer_ls180.v:123733.1-124030.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_start.input" +attribute \generator "nMigen" +module \input$75 + attribute \src "issuer_ls180.v:124012.3-124023.6" + wire width 64 $0\a[63:0] + attribute \src "issuer_ls180.v:123734.7-123734.20" + wire $0\initial[0:0] + attribute \src "issuer_ls180.v:124012.3-124023.6" + wire width 64 $1\a[63:0] + attribute \src "issuer_ls180.v:124011.18-124011.100" + wire width 64 $not$issuer_ls180.v:124011$5070_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:28" + wire width 64 \$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:20" + wire width 64 \a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:39" + wire width 64 \b + attribute \src "issuer_ls180.v:123734.7-123734.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 input 17 \logical_op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 output 39 \logical_op__data_len$18 + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 input 2 \logical_op__fn_unit + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 output 24 \logical_op__fn_unit$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 input 3 \logical_op__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 output 25 \logical_op__imm_data__data$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 4 \logical_op__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 26 \logical_op__imm_data__ok$5 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 input 11 \logical_op__input_carry + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 output 33 \logical_op__input_carry$12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 18 \logical_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 output 40 \logical_op__insn$19 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 input 1 \logical_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 output 23 \logical_op__insn_type$2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 9 \logical_op__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 31 \logical_op__invert_in$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 12 \logical_op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 34 \logical_op__invert_out$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 15 \logical_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 37 \logical_op__is_32bit$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 16 \logical_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 38 \logical_op__is_signed$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 7 \logical_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 29 \logical_op__oe__oe$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 8 \logical_op__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 30 \logical_op__oe__ok$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 14 \logical_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 36 \logical_op__output_carry$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 6 \logical_op__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 28 \logical_op__rc__ok$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 5 \logical_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 27 \logical_op__rc__rc$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 13 \logical_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 35 \logical_op__write_cr0$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 10 \logical_op__zero_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 32 \logical_op__zero_a$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 input 44 \muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 output 22 \muxid$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 19 \ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 output 41 \ra$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 20 \rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 output 42 \rb$21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire input 21 \xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire output 43 \xer_so$22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:28" + cell $not $not$issuer_ls180.v:124011$5070 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A \ra + connect \Y $not$issuer_ls180.v:124011$5070_Y + end + attribute \src "issuer_ls180.v:123734.7-123734.20" + process $proc$issuer_ls180.v:123734$5072 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "issuer_ls180.v:124012.3-124023.6" + process $proc$issuer_ls180.v:124012$5071 + assign { } { } + assign $0\a[63:0] $1\a[63:0] + attribute \src "issuer_ls180.v:124013.5-124013.29" + switch \initial + attribute \src "issuer_ls180.v:124013.9-124013.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:27" + switch \logical_op__invert_in + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\a[63:0] \$23 + attribute \src "issuer_ls180.v:0.0-0.0" + case + assign { } { } + assign $1\a[63:0] \ra + end + sync always + update \a $0\a[63:0] + end + connect \$23 $not$issuer_ls180.v:124011$5070_Y + connect { \logical_op__insn$19 \logical_op__data_len$18 \logical_op__is_signed$17 \logical_op__is_32bit$16 \logical_op__output_carry$15 \logical_op__write_cr0$14 \logical_op__invert_out$13 \logical_op__input_carry$12 \logical_op__zero_a$11 \logical_op__invert_in$10 \logical_op__oe__ok$9 \logical_op__oe__oe$8 \logical_op__rc__ok$7 \logical_op__rc__rc$6 \logical_op__imm_data__ok$5 \logical_op__imm_data__data$4 \logical_op__fn_unit$3 \logical_op__insn_type$2 } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in \logical_op__oe__ok \logical_op__oe__oe \logical_op__rc__ok \logical_op__rc__rc \logical_op__imm_data__ok \logical_op__imm_data__data \logical_op__fn_unit \logical_op__insn_type } + connect \muxid$1 \muxid + connect \xer_so$22 \xer_so + connect \rb$21 \rb + connect \b \rb + connect \ra$20 \a +end +attribute \src "issuer_ls180.v:124034.1-124284.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.fus.mul0.alu_mul0.mul_pipe1.input" +attribute \generator "nMigen" +module \input$92 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:20" + wire width 64 \a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:39" + wire width 64 \b + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 input 2 \mul_op__fn_unit + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 output 18 \mul_op__fn_unit$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 input 3 \mul_op__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 output 19 \mul_op__imm_data__data$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 4 \mul_op__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 20 \mul_op__imm_data__ok$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 12 \mul_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 output 28 \mul_op__insn$13 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 input 1 \mul_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 output 17 \mul_op__insn_type$2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 10 \mul_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 26 \mul_op__is_32bit$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 11 \mul_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 27 \mul_op__is_signed$12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 7 \mul_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 23 \mul_op__oe__oe$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 8 \mul_op__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 24 \mul_op__oe__ok$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 6 \mul_op__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 22 \mul_op__rc__ok$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 5 \mul_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 21 \mul_op__rc__rc$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 9 \mul_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 25 \mul_op__write_cr0$10 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 input 32 \muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 output 16 \muxid$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 13 \ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 output 29 \ra$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 14 \rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 output 30 \rb$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire input 15 \xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire output 31 \xer_so$16 + connect { \mul_op__insn$13 \mul_op__is_signed$12 \mul_op__is_32bit$11 \mul_op__write_cr0$10 \mul_op__oe__ok$9 \mul_op__oe__oe$8 \mul_op__rc__ok$7 \mul_op__rc__rc$6 \mul_op__imm_data__ok$5 \mul_op__imm_data__data$4 \mul_op__fn_unit$3 \mul_op__insn_type$2 } { \mul_op__insn \mul_op__is_signed \mul_op__is_32bit \mul_op__write_cr0 \mul_op__oe__ok \mul_op__oe__oe \mul_op__rc__ok \mul_op__rc__rc \mul_op__imm_data__ok \mul_op__imm_data__data \mul_op__fn_unit \mul_op__insn_type } + connect \muxid$1 \muxid + connect \xer_so$16 \xer_so + connect \rb$15 \rb + connect \b \rb + connect \ra$14 \a + connect \a \ra +end +attribute \src "issuer_ls180.v:124288.1-124507.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.int" +attribute \generator "nMigen" +module \int + attribute \src "issuer_ls180.v:124413.3-124419.6" + wire width 5 $0$memwr$\memory$issuer_ls180.v:124418$5105_ADDR[4:0]$5114 + attribute \src "issuer_ls180.v:124413.3-124419.6" + wire width 64 $0$memwr$\memory$issuer_ls180.v:124418$5105_DATA[63:0]$5115 + attribute \src "issuer_ls180.v:124413.3-124419.6" + wire width 64 $0$memwr$\memory$issuer_ls180.v:124418$5105_EN[63:0]$5116 + attribute \src "issuer_ls180.v:124413.3-124419.6" + wire width 5 $0\_0_[4:0] + attribute \src "issuer_ls180.v:124413.3-124419.6" + wire width 5 $0\_1_[4:0] + attribute \src "issuer_ls180.v:124413.3-124419.6" + wire width 5 $0\_2_[4:0] + attribute \src "issuer_ls180.v:124413.3-124419.6" + wire width 5 $0\_3_[4:0] + attribute \src "issuer_ls180.v:124442.3-124451.6" + wire width 64 $0\dmi__data_o[63:0] + attribute \src "issuer_ls180.v:124289.7-124289.20" + wire $0\initial[0:0] + attribute \src "issuer_ls180.v:124433.3-124441.6" + wire $0\ren_delay$10$next[0:0]$5125 + attribute \src "issuer_ls180.v:124366.3-124367.43" + wire $0\ren_delay$10[0:0]$5107 + attribute \src "issuer_ls180.v:124332.7-124332.28" + wire $0\ren_delay$10[0:0]$5173 + attribute \src "issuer_ls180.v:124462.3-124470.6" + wire $0\ren_delay$8$next[0:0]$5130 + attribute \src "issuer_ls180.v:124370.3-124371.41" + wire $0\ren_delay$8[0:0]$5111 + attribute \src "issuer_ls180.v:124336.7-124336.27" + wire $0\ren_delay$8[0:0]$5175 + attribute \src "issuer_ls180.v:124481.3-124489.6" + wire $0\ren_delay$9$next[0:0]$5134 + attribute \src "issuer_ls180.v:124368.3-124369.41" + wire $0\ren_delay$9[0:0]$5109 + attribute \src "issuer_ls180.v:124340.7-124340.27" + wire $0\ren_delay$9[0:0]$5177 + attribute \src "issuer_ls180.v:124424.3-124432.6" + wire $0\ren_delay$next[0:0]$5122 + attribute \src "issuer_ls180.v:124372.3-124373.35" + wire $0\ren_delay[0:0] + attribute \src "issuer_ls180.v:124452.3-124461.6" + wire width 64 $0\src1__data_o[63:0] + attribute \src "issuer_ls180.v:124471.3-124480.6" + wire width 64 $0\src2__data_o[63:0] + attribute \src "issuer_ls180.v:124490.3-124499.6" + wire width 64 $0\src3__data_o[63:0] + attribute \src "issuer_ls180.v:124442.3-124451.6" + wire width 64 $1\dmi__data_o[63:0] + attribute \src "issuer_ls180.v:124433.3-124441.6" + wire $1\ren_delay$10$next[0:0]$5126 + attribute \src "issuer_ls180.v:124462.3-124470.6" + wire $1\ren_delay$8$next[0:0]$5131 + attribute \src "issuer_ls180.v:124481.3-124489.6" + wire $1\ren_delay$9$next[0:0]$5135 + attribute \src "issuer_ls180.v:124424.3-124432.6" + wire $1\ren_delay$next[0:0]$5123 + attribute \src "issuer_ls180.v:124330.7-124330.23" + wire $1\ren_delay[0:0] + attribute \src "issuer_ls180.v:124452.3-124461.6" + wire width 64 $1\src1__data_o[63:0] + attribute \src "issuer_ls180.v:124471.3-124480.6" + wire width 64 $1\src2__data_o[63:0] + attribute \src "issuer_ls180.v:124490.3-124499.6" + wire width 64 $1\src3__data_o[63:0] + attribute \src "issuer_ls180.v:124420.26-124420.32" + wire width 64 $memrd$\memory$issuer_ls180.v:124420$5117_DATA + attribute \src "issuer_ls180.v:124421.30-124421.36" + wire width 64 $memrd$\memory$issuer_ls180.v:124421$5118_DATA + attribute \src "issuer_ls180.v:124422.30-124422.36" + wire width 64 $memrd$\memory$issuer_ls180.v:124422$5119_DATA + attribute \src "issuer_ls180.v:124423.30-124423.36" + wire width 64 $memrd$\memory$issuer_ls180.v:124423$5120_DATA + attribute \src "issuer_ls180.v:0.0-0.0" + wire width 5 $memwr$\memory$issuer_ls180.v:124418$5105_ADDR + attribute \src "issuer_ls180.v:0.0-0.0" + wire width 64 $memwr$\memory$issuer_ls180.v:124418$5105_DATA + attribute \src "issuer_ls180.v:0.0-0.0" + wire width 64 $memwr$\memory$issuer_ls180.v:124418$5105_EN + attribute \src "issuer_ls180.v:124409.13-124409.16" + wire width 5 \_0_ + attribute \src "issuer_ls180.v:124410.13-124410.16" + wire width 5 \_1_ + attribute \src "issuer_ls180.v:124411.13-124411.16" + wire width 5 \_2_ + attribute \src "issuer_ls180.v:124412.13-124412.16" + wire width 5 \_3_ + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" + wire input 17 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" + wire input 16 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 5 input 14 \dest1__addr + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 64 input 13 \dest1__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire input 15 \dest1__wen + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 5 input 1 \dmi__addr + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 64 output 3 \dmi__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire input 2 \dmi__ren + attribute \src "issuer_ls180.v:124289.7-124289.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:210" + wire width 5 \memory_r_addr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:210" + wire width 5 \memory_r_addr$2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:210" + wire width 5 \memory_r_addr$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:210" + wire width 5 \memory_r_addr$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:210" + wire width 64 \memory_r_data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:210" + wire width 64 \memory_r_data$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:210" + wire width 64 \memory_r_data$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:210" + wire width 64 \memory_r_data$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:218" + wire width 5 \memory_w_addr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:218" + wire width 64 \memory_w_data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:218" + wire \memory_w_en + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:243" + wire \ren_delay + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:243" + wire \ren_delay$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:243" + wire \ren_delay$10$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:243" + wire \ren_delay$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:243" + wire \ren_delay$8$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:243" + wire \ren_delay$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:243" + wire \ren_delay$9$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:243" + wire \ren_delay$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 5 input 5 \src1__addr + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 64 output 4 \src1__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire input 6 \src1__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 5 input 8 \src2__addr + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 64 output 7 \src2__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire input 9 \src2__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 5 input 11 \src3__addr + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 64 output 10 \src3__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire input 12 \src3__ren + attribute \src "issuer_ls180.v:124374.14-124374.20" + memory width 64 size 32 \memory + attribute \src "issuer_ls180.v:0.0-0.0" + cell $meminit $meminit$\memory$issuer_ls180.v:0$5137 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 5137 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 0 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "issuer_ls180.v:0.0-0.0" + cell $meminit $meminit$\memory$issuer_ls180.v:0$5138 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 5138 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 1 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "issuer_ls180.v:0.0-0.0" + cell $meminit $meminit$\memory$issuer_ls180.v:0$5139 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 5139 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 2 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "issuer_ls180.v:0.0-0.0" + cell $meminit $meminit$\memory$issuer_ls180.v:0$5140 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 5140 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 3 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "issuer_ls180.v:0.0-0.0" + cell $meminit $meminit$\memory$issuer_ls180.v:0$5141 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 5141 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 4 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "issuer_ls180.v:0.0-0.0" + cell $meminit $meminit$\memory$issuer_ls180.v:0$5142 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 5142 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 5 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "issuer_ls180.v:0.0-0.0" + cell $meminit $meminit$\memory$issuer_ls180.v:0$5143 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 5143 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 6 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "issuer_ls180.v:0.0-0.0" + cell $meminit $meminit$\memory$issuer_ls180.v:0$5144 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 5144 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 7 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "issuer_ls180.v:0.0-0.0" + cell $meminit $meminit$\memory$issuer_ls180.v:0$5145 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 5145 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 8 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "issuer_ls180.v:0.0-0.0" + cell $meminit $meminit$\memory$issuer_ls180.v:0$5146 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 5146 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 9 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "issuer_ls180.v:0.0-0.0" + cell $meminit $meminit$\memory$issuer_ls180.v:0$5147 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 5147 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 10 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "issuer_ls180.v:0.0-0.0" + cell $meminit $meminit$\memory$issuer_ls180.v:0$5148 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 5148 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 11 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "issuer_ls180.v:0.0-0.0" + cell $meminit $meminit$\memory$issuer_ls180.v:0$5149 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 5149 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 12 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "issuer_ls180.v:0.0-0.0" + cell $meminit $meminit$\memory$issuer_ls180.v:0$5150 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 5150 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 13 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "issuer_ls180.v:0.0-0.0" + cell $meminit $meminit$\memory$issuer_ls180.v:0$5151 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 5151 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 14 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "issuer_ls180.v:0.0-0.0" + cell $meminit $meminit$\memory$issuer_ls180.v:0$5152 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 5152 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 15 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "issuer_ls180.v:0.0-0.0" + cell $meminit $meminit$\memory$issuer_ls180.v:0$5153 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 5153 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 16 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "issuer_ls180.v:0.0-0.0" + cell $meminit $meminit$\memory$issuer_ls180.v:0$5154 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 5154 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 17 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "issuer_ls180.v:0.0-0.0" + cell $meminit $meminit$\memory$issuer_ls180.v:0$5155 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 5155 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 18 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "issuer_ls180.v:0.0-0.0" + cell $meminit $meminit$\memory$issuer_ls180.v:0$5156 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 5156 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 19 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "issuer_ls180.v:0.0-0.0" + cell $meminit $meminit$\memory$issuer_ls180.v:0$5157 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 5157 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 20 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "issuer_ls180.v:0.0-0.0" + cell $meminit $meminit$\memory$issuer_ls180.v:0$5158 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 5158 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 21 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "issuer_ls180.v:0.0-0.0" + cell $meminit $meminit$\memory$issuer_ls180.v:0$5159 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 5159 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 22 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "issuer_ls180.v:0.0-0.0" + cell $meminit $meminit$\memory$issuer_ls180.v:0$5160 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 5160 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 23 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "issuer_ls180.v:0.0-0.0" + cell $meminit $meminit$\memory$issuer_ls180.v:0$5161 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 5161 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 24 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "issuer_ls180.v:0.0-0.0" + cell $meminit $meminit$\memory$issuer_ls180.v:0$5162 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 5162 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 25 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "issuer_ls180.v:0.0-0.0" + cell $meminit $meminit$\memory$issuer_ls180.v:0$5163 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 5163 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 26 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "issuer_ls180.v:0.0-0.0" + cell $meminit $meminit$\memory$issuer_ls180.v:0$5164 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 5164 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 27 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "issuer_ls180.v:0.0-0.0" + cell $meminit $meminit$\memory$issuer_ls180.v:0$5165 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 5165 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 28 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "issuer_ls180.v:0.0-0.0" + cell $meminit $meminit$\memory$issuer_ls180.v:0$5166 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 5166 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 29 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "issuer_ls180.v:0.0-0.0" + cell $meminit $meminit$\memory$issuer_ls180.v:0$5167 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 5167 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 30 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "issuer_ls180.v:0.0-0.0" + cell $meminit $meminit$\memory$issuer_ls180.v:0$5168 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 5168 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 31 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "issuer_ls180.v:124420.26-124420.32" + cell $memrd $memrd$\memory$issuer_ls180.v:124420$5117 + parameter \ABITS 5 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\memory" + parameter \TRANSPARENT 0 + parameter \WIDTH 64 + connect \ADDR \_0_ + connect \CLK 1'x + connect \DATA $memrd$\memory$issuer_ls180.v:124420$5117_DATA + connect \EN 1'x + end + attribute \src "issuer_ls180.v:124421.30-124421.36" + cell $memrd $memrd$\memory$issuer_ls180.v:124421$5118 + parameter \ABITS 5 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\memory" + parameter \TRANSPARENT 0 + parameter \WIDTH 64 + connect \ADDR \_1_ + connect \CLK 1'x + connect \DATA $memrd$\memory$issuer_ls180.v:124421$5118_DATA + connect \EN 1'x + end + attribute \src "issuer_ls180.v:124422.30-124422.36" + cell $memrd $memrd$\memory$issuer_ls180.v:124422$5119 + parameter \ABITS 5 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\memory" + parameter \TRANSPARENT 0 + parameter \WIDTH 64 + connect \ADDR \_2_ + connect \CLK 1'x + connect \DATA $memrd$\memory$issuer_ls180.v:124422$5119_DATA + connect \EN 1'x + end + attribute \src "issuer_ls180.v:124423.30-124423.36" + cell $memrd $memrd$\memory$issuer_ls180.v:124423$5120 + parameter \ABITS 5 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\memory" + parameter \TRANSPARENT 0 + parameter \WIDTH 64 + connect \ADDR \_3_ + connect \CLK 1'x + connect \DATA $memrd$\memory$issuer_ls180.v:124423$5120_DATA + connect \EN 1'x + end + attribute \src "issuer_ls180.v:0.0-0.0" + cell $memwr $memwr$\memory$issuer_ls180.v:0$5169 + parameter \ABITS 5 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\memory" + parameter \PRIORITY 5169 + parameter \WIDTH 64 + connect \ADDR $memwr$\memory$issuer_ls180.v:124418$5105_ADDR + connect \CLK 1'x + connect \DATA $memwr$\memory$issuer_ls180.v:124418$5105_DATA + connect \EN $memwr$\memory$issuer_ls180.v:124418$5105_EN + end + attribute \src "issuer_ls180.v:0.0-0.0" + process $proc$issuer_ls180.v:0$5178 + sync always + sync init + end + attribute \src "issuer_ls180.v:124289.7-124289.20" + process $proc$issuer_ls180.v:124289$5170 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "issuer_ls180.v:124330.7-124330.23" + process $proc$issuer_ls180.v:124330$5171 + assign { } { } + assign $1\ren_delay[0:0] 1'0 + sync always + sync init + update \ren_delay $1\ren_delay[0:0] + end + attribute \src "issuer_ls180.v:124332.7-124332.28" + process $proc$issuer_ls180.v:124332$5172 + assign { } { } + assign $0\ren_delay$10[0:0]$5173 1'0 + sync always + sync init + update \ren_delay$10 $0\ren_delay$10[0:0]$5173 + end + attribute \src "issuer_ls180.v:124336.7-124336.27" + process $proc$issuer_ls180.v:124336$5174 + assign { } { } + assign $0\ren_delay$8[0:0]$5175 1'0 + sync always + sync init + update \ren_delay$8 $0\ren_delay$8[0:0]$5175 + end + attribute \src "issuer_ls180.v:124340.7-124340.27" + process $proc$issuer_ls180.v:124340$5176 + assign { } { } + assign $0\ren_delay$9[0:0]$5177 1'0 + sync always + sync init + update \ren_delay$9 $0\ren_delay$9[0:0]$5177 + end + attribute \src "issuer_ls180.v:124366.3-124367.43" + process $proc$issuer_ls180.v:124366$5106 + assign { } { } + assign $0\ren_delay$10[0:0]$5107 \ren_delay$10$next + sync posedge \coresync_clk + update \ren_delay$10 $0\ren_delay$10[0:0]$5107 + end + attribute \src "issuer_ls180.v:124368.3-124369.41" + process $proc$issuer_ls180.v:124368$5108 + assign { } { } + assign $0\ren_delay$9[0:0]$5109 \ren_delay$9$next + sync posedge \coresync_clk + update \ren_delay$9 $0\ren_delay$9[0:0]$5109 + end + attribute \src "issuer_ls180.v:124370.3-124371.41" + process $proc$issuer_ls180.v:124370$5110 + assign { } { } + assign $0\ren_delay$8[0:0]$5111 \ren_delay$8$next + sync posedge \coresync_clk + update \ren_delay$8 $0\ren_delay$8[0:0]$5111 + end + attribute \src "issuer_ls180.v:124372.3-124373.35" + process $proc$issuer_ls180.v:124372$5112 + assign { } { } + assign $0\ren_delay[0:0] \ren_delay$next + sync posedge \coresync_clk + update \ren_delay $0\ren_delay[0:0] + end + attribute \src "issuer_ls180.v:124413.3-124419.6" + process $proc$issuer_ls180.v:124413$5113 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0$memwr$\memory$issuer_ls180.v:124418$5105_ADDR[4:0]$5114 5'xxxxx + assign $0$memwr$\memory$issuer_ls180.v:124418$5105_DATA[63:0]$5115 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\memory$issuer_ls180.v:124418$5105_EN[63:0]$5116 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0\_0_[4:0] \src1__addr + assign $0\_1_[4:0] \src2__addr + assign $0\_2_[4:0] \src3__addr + assign $0\_3_[4:0] \dmi__addr + attribute \src "issuer_ls180.v:124418.5-124418.58" + switch \dest1__wen + attribute \src "issuer_ls180.v:124418.9-124418.19" + case 1'1 + assign $0$memwr$\memory$issuer_ls180.v:124418$5105_ADDR[4:0]$5114 \dest1__addr + assign $0$memwr$\memory$issuer_ls180.v:124418$5105_DATA[63:0]$5115 \dest1__data_i + assign $0$memwr$\memory$issuer_ls180.v:124418$5105_EN[63:0]$5116 64'1111111111111111111111111111111111111111111111111111111111111111 + case + end + sync posedge \coresync_clk + update \_0_ $0\_0_[4:0] + update \_1_ $0\_1_[4:0] + update \_2_ $0\_2_[4:0] + update \_3_ $0\_3_[4:0] + update $memwr$\memory$issuer_ls180.v:124418$5105_ADDR $0$memwr$\memory$issuer_ls180.v:124418$5105_ADDR[4:0]$5114 + update $memwr$\memory$issuer_ls180.v:124418$5105_DATA $0$memwr$\memory$issuer_ls180.v:124418$5105_DATA[63:0]$5115 + update $memwr$\memory$issuer_ls180.v:124418$5105_EN $0$memwr$\memory$issuer_ls180.v:124418$5105_EN[63:0]$5116 + end + attribute \src "issuer_ls180.v:124424.3-124432.6" + process $proc$issuer_ls180.v:124424$5121 + assign { } { } + assign { } { } + assign $0\ren_delay$next[0:0]$5122 $1\ren_delay$next[0:0]$5123 + attribute \src "issuer_ls180.v:124425.5-124425.29" + switch \initial + attribute \src "issuer_ls180.v:124425.9-124425.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\ren_delay$next[0:0]$5123 1'0 + case + assign $1\ren_delay$next[0:0]$5123 \src1__ren + end + sync always + update \ren_delay$next $0\ren_delay$next[0:0]$5122 + end + attribute \src "issuer_ls180.v:124433.3-124441.6" + process $proc$issuer_ls180.v:124433$5124 + assign { } { } + assign { } { } + assign $0\ren_delay$10$next[0:0]$5125 $1\ren_delay$10$next[0:0]$5126 + attribute \src "issuer_ls180.v:124434.5-124434.29" + switch \initial + attribute \src "issuer_ls180.v:124434.9-124434.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\ren_delay$10$next[0:0]$5126 1'0 + case + assign $1\ren_delay$10$next[0:0]$5126 \dmi__ren + end + sync always + update \ren_delay$10$next $0\ren_delay$10$next[0:0]$5125 + end + attribute \src "issuer_ls180.v:124442.3-124451.6" + process $proc$issuer_ls180.v:124442$5127 + assign { } { } + assign { } { } + assign $0\dmi__data_o[63:0] $1\dmi__data_o[63:0] + attribute \src "issuer_ls180.v:124443.5-124443.29" + switch \initial + attribute \src "issuer_ls180.v:124443.9-124443.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:245" + switch \ren_delay$10 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dmi__data_o[63:0] \memory_r_data$7 + case + assign $1\dmi__data_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \dmi__data_o $0\dmi__data_o[63:0] + end + attribute \src "issuer_ls180.v:124452.3-124461.6" + process $proc$issuer_ls180.v:124452$5128 + assign { } { } + assign { } { } + assign $0\src1__data_o[63:0] $1\src1__data_o[63:0] + attribute \src "issuer_ls180.v:124453.5-124453.29" + switch \initial + attribute \src "issuer_ls180.v:124453.9-124453.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:245" + switch \ren_delay + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\src1__data_o[63:0] \memory_r_data + case + assign $1\src1__data_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \src1__data_o $0\src1__data_o[63:0] + end + attribute \src "issuer_ls180.v:124462.3-124470.6" + process $proc$issuer_ls180.v:124462$5129 + assign { } { } + assign { } { } + assign $0\ren_delay$8$next[0:0]$5130 $1\ren_delay$8$next[0:0]$5131 + attribute \src "issuer_ls180.v:124463.5-124463.29" + switch \initial + attribute \src "issuer_ls180.v:124463.9-124463.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\ren_delay$8$next[0:0]$5131 1'0 + case + assign $1\ren_delay$8$next[0:0]$5131 \src2__ren + end + sync always + update \ren_delay$8$next $0\ren_delay$8$next[0:0]$5130 + end + attribute \src "issuer_ls180.v:124471.3-124480.6" + process $proc$issuer_ls180.v:124471$5132 + assign { } { } + assign { } { } + assign $0\src2__data_o[63:0] $1\src2__data_o[63:0] + attribute \src "issuer_ls180.v:124472.5-124472.29" + switch \initial + attribute \src "issuer_ls180.v:124472.9-124472.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:245" + switch \ren_delay$8 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\src2__data_o[63:0] \memory_r_data$3 + case + assign $1\src2__data_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \src2__data_o $0\src2__data_o[63:0] + end + attribute \src "issuer_ls180.v:124481.3-124489.6" + process $proc$issuer_ls180.v:124481$5133 + assign { } { } + assign { } { } + assign $0\ren_delay$9$next[0:0]$5134 $1\ren_delay$9$next[0:0]$5135 + attribute \src "issuer_ls180.v:124482.5-124482.29" + switch \initial + attribute \src "issuer_ls180.v:124482.9-124482.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\ren_delay$9$next[0:0]$5135 1'0 + case + assign $1\ren_delay$9$next[0:0]$5135 \src3__ren + end + sync always + update \ren_delay$9$next $0\ren_delay$9$next[0:0]$5134 + end + attribute \src "issuer_ls180.v:124490.3-124499.6" + process $proc$issuer_ls180.v:124490$5136 + assign { } { } + assign { } { } + assign $0\src3__data_o[63:0] $1\src3__data_o[63:0] + attribute \src "issuer_ls180.v:124491.5-124491.29" + switch \initial + attribute \src "issuer_ls180.v:124491.9-124491.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:245" + switch \ren_delay$9 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\src3__data_o[63:0] \memory_r_data$5 + case + assign $1\src3__data_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \src3__data_o $0\src3__data_o[63:0] + end + connect \memory_r_data $memrd$\memory$issuer_ls180.v:124420$5117_DATA + connect \memory_r_data$3 $memrd$\memory$issuer_ls180.v:124421$5118_DATA + connect \memory_r_data$5 $memrd$\memory$issuer_ls180.v:124422$5119_DATA + connect \memory_r_data$7 $memrd$\memory$issuer_ls180.v:124423$5120_DATA + connect \memory_w_data \dest1__data_i + connect \memory_w_en \dest1__wen + connect \memory_w_addr \dest1__addr + connect \memory_r_addr$6 \dmi__addr + connect \memory_r_addr$4 \src3__addr + connect \memory_r_addr$2 \src2__addr + connect \memory_r_addr \src1__addr +end +attribute \src "issuer_ls180.v:124511.1-124676.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.l0" +attribute \generator "nMigen" +module \l0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" + wire input 23 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" + wire input 1 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" + wire input 15 \dbus__ack + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" + wire width 45 output 20 \dbus__adr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" + wire output 14 \dbus__cyc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" + wire width 64 input 19 \dbus__dat_r + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" + wire width 64 output 22 \dbus__dat_w + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" + wire input 16 \dbus__err + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" + wire width 8 output 18 \dbus__sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" + wire output 17 \dbus__stb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" + wire output 21 \dbus__we + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:110" + wire output 8 \ldst_port0_addr_exc_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 96 input 6 \ldst_port0_addr_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire input 7 \ldst_port0_addr_i_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:109" + wire output 9 \ldst_port0_addr_ok_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:105" + wire output 2 \ldst_port0_busy_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:102" + wire width 4 input 5 \ldst_port0_data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:98" + wire input 3 \ldst_port0_is_ld_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:99" + wire input 4 \ldst_port0_is_st_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 output 10 \ldst_port0_ld_data_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 11 \ldst_port0_ld_data_o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 input 12 \ldst_port0_st_data_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire input 13 \ldst_port0_st_data_i_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:110" + wire \pimem_ldst_port0_addr_exc_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 48 \pimem_ldst_port0_addr_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \pimem_ldst_port0_addr_i_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:109" + wire \pimem_ldst_port0_addr_ok_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:105" + wire \pimem_ldst_port0_busy_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:102" + wire width 4 \pimem_ldst_port0_data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:98" + wire \pimem_ldst_port0_is_ld_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:99" + wire \pimem_ldst_port0_is_st_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 \pimem_ldst_port0_ld_data_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \pimem_ldst_port0_ld_data_o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 \pimem_ldst_port0_st_data_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \pimem_ldst_port0_st_data_i_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:62" + wire width 64 \pimem_m_ld_data_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:54" + wire \pimem_m_valid_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:43" + wire width 48 \pimem_x_addr_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:59" + wire \pimem_x_busy_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:45" + wire \pimem_x_ld_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:44" + wire width 8 \pimem_x_mask_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:47" + wire width 64 \pimem_x_st_data_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:46" + wire \pimem_x_st_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:50" + wire \pimem_x_valid_i + attribute \module_not_derived 1 + attribute \src "issuer_ls180.v:124600.12-124627.4" + cell \l0$127 \l0 + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \ldst_port0_addr_exc_o \ldst_port0_addr_exc_o + connect \ldst_port0_addr_exc_o$12 \pimem_ldst_port0_addr_exc_o + connect \ldst_port0_addr_i \ldst_port0_addr_i + connect \ldst_port0_addr_i$5 \pimem_ldst_port0_addr_i + connect \ldst_port0_addr_i_ok \ldst_port0_addr_i_ok + connect \ldst_port0_addr_i_ok$6 \pimem_ldst_port0_addr_i_ok + connect \ldst_port0_addr_ok_o \ldst_port0_addr_ok_o + connect \ldst_port0_addr_ok_o$7 \pimem_ldst_port0_addr_ok_o + connect \ldst_port0_busy_o \ldst_port0_busy_o + connect \ldst_port0_busy_o$3 \pimem_ldst_port0_busy_o + connect \ldst_port0_data_len \ldst_port0_data_len + connect \ldst_port0_data_len$4 \pimem_ldst_port0_data_len + connect \ldst_port0_is_ld_i \ldst_port0_is_ld_i + connect \ldst_port0_is_ld_i$1 \pimem_ldst_port0_is_ld_i + connect \ldst_port0_is_st_i \ldst_port0_is_st_i + connect \ldst_port0_is_st_i$2 \pimem_ldst_port0_is_st_i + connect \ldst_port0_ld_data_o \ldst_port0_ld_data_o + connect \ldst_port0_ld_data_o$8 \pimem_ldst_port0_ld_data_o + connect \ldst_port0_ld_data_o_ok \ldst_port0_ld_data_o_ok + connect \ldst_port0_ld_data_o_ok$9 \pimem_ldst_port0_ld_data_o_ok + connect \ldst_port0_st_data_i \ldst_port0_st_data_i + connect \ldst_port0_st_data_i$11 \pimem_ldst_port0_st_data_i + connect \ldst_port0_st_data_i_ok \ldst_port0_st_data_i_ok + connect \ldst_port0_st_data_i_ok$10 \pimem_ldst_port0_st_data_i_ok + end + attribute \module_not_derived 1 + attribute \src "issuer_ls180.v:124628.9-124649.4" + cell \lsmem \lsmem + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \dbus__ack \dbus__ack + connect \dbus__adr \dbus__adr + connect \dbus__cyc \dbus__cyc + connect \dbus__dat_r \dbus__dat_r + connect \dbus__dat_w \dbus__dat_w + connect \dbus__err \dbus__err + connect \dbus__sel \dbus__sel + connect \dbus__stb \dbus__stb + connect \dbus__we \dbus__we + connect \m_ld_data_o \pimem_m_ld_data_o + connect \m_valid_i \pimem_m_valid_i + connect \x_addr_i \pimem_x_addr_i + connect \x_busy_o \pimem_x_busy_o + connect \x_ld_i \pimem_x_ld_i + connect \x_mask_i \pimem_x_mask_i + connect \x_st_data_i \pimem_x_st_data_i + connect \x_st_i \pimem_x_st_i + connect \x_valid_i \pimem_x_valid_i + end + attribute \module_not_derived 1 + attribute \src "issuer_ls180.v:124650.9-124674.4" + cell \pimem \pimem + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \ldst_port0_addr_exc_o \pimem_ldst_port0_addr_exc_o + connect \ldst_port0_addr_i \pimem_ldst_port0_addr_i + connect \ldst_port0_addr_i_ok \pimem_ldst_port0_addr_i_ok + connect \ldst_port0_addr_ok_o \pimem_ldst_port0_addr_ok_o + connect \ldst_port0_busy_o \pimem_ldst_port0_busy_o + connect \ldst_port0_data_len \pimem_ldst_port0_data_len + connect \ldst_port0_is_ld_i \pimem_ldst_port0_is_ld_i + connect \ldst_port0_is_st_i \pimem_ldst_port0_is_st_i + connect \ldst_port0_ld_data_o \pimem_ldst_port0_ld_data_o + connect \ldst_port0_ld_data_o_ok \pimem_ldst_port0_ld_data_o_ok + connect \ldst_port0_st_data_i \pimem_ldst_port0_st_data_i + connect \ldst_port0_st_data_i_ok \pimem_ldst_port0_st_data_i_ok + connect \m_ld_data_o \pimem_m_ld_data_o + connect \m_valid_i \pimem_m_valid_i + connect \x_addr_i \pimem_x_addr_i + connect \x_busy_o \pimem_x_busy_o + connect \x_ld_i \pimem_x_ld_i + connect \x_mask_i \pimem_x_mask_i + connect \x_st_data_i \pimem_x_st_data_i + connect \x_st_i \pimem_x_st_i + connect \x_valid_i \pimem_x_valid_i + end + connect \pimem_ldst_port0_addr_exc_o 1'0 +end +attribute \src "issuer_ls180.v:124680.1-124994.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.l0.l0" +attribute \generator "nMigen" +module \l0$127 + attribute \src "issuer_ls180.v:124889.3-124903.6" + wire $0\idx_l$16$next[0:0]$5202 + attribute \src "issuer_ls180.v:124796.3-124797.35" + wire $0\idx_l$16[0:0]$5185 + attribute \src "issuer_ls180.v:124701.7-124701.24" + wire $0\idx_l$16[0:0]$5221 + attribute \src "issuer_ls180.v:124904.3-124913.6" + wire $0\idx_l_r_idx_l[0:0] + attribute \src "issuer_ls180.v:124914.3-124923.6" + wire $0\idx_l_s_idx_l[0:0] + attribute \src "issuer_ls180.v:124681.7-124681.20" + wire $0\initial[0:0] + attribute \src "issuer_ls180.v:124879.3-124888.6" + wire $0\ldst_port0_addr_exc_o[0:0] + attribute \src "issuer_ls180.v:124817.3-124826.6" + wire width 48 $0\ldst_port0_addr_i$5[47:0]$5187 + attribute \src "issuer_ls180.v:124827.3-124836.6" + wire $0\ldst_port0_addr_i_ok$6[0:0]$5190 + attribute \src "issuer_ls180.v:124869.3-124878.6" + wire $0\ldst_port0_addr_ok_o[0:0] + attribute \src "issuer_ls180.v:124859.3-124868.6" + wire $0\ldst_port0_busy_o[0:0] + attribute \src "issuer_ls180.v:124969.3-124978.6" + wire width 4 $0\ldst_port0_data_len$4[3:0]$5216 + attribute \src "issuer_ls180.v:124979.3-124988.6" + wire $0\ldst_port0_go_die_i[0:0] + attribute \src "issuer_ls180.v:124949.3-124958.6" + wire $0\ldst_port0_is_ld_i$1[0:0]$5210 + attribute \src "issuer_ls180.v:124959.3-124968.6" + wire $0\ldst_port0_is_st_i$2[0:0]$5213 + attribute \src "issuer_ls180.v:124848.3-124858.6" + wire width 64 $0\ldst_port0_ld_data_o[63:0] + attribute \src "issuer_ls180.v:124848.3-124858.6" + wire $0\ldst_port0_ld_data_o_ok[0:0] + attribute \src "issuer_ls180.v:124837.3-124847.6" + wire width 64 $0\ldst_port0_st_data_i$11[63:0]$5193 + attribute \src "issuer_ls180.v:124837.3-124847.6" + wire $0\ldst_port0_st_data_i_ok$10[0:0]$5194 + attribute \src "issuer_ls180.v:124794.3-124795.36" + wire $0\reset_delay[0:0] + attribute \src "issuer_ls180.v:124939.3-124948.6" + wire $0\reset_l_r_reset[0:0] + attribute \src "issuer_ls180.v:124924.3-124938.6" + wire $0\reset_l_s_reset[0:0] + attribute \src "issuer_ls180.v:124889.3-124903.6" + wire $1\idx_l$16$next[0:0]$5203 + attribute \src "issuer_ls180.v:124904.3-124913.6" + wire $1\idx_l_r_idx_l[0:0] + attribute \src "issuer_ls180.v:124914.3-124923.6" + wire $1\idx_l_s_idx_l[0:0] + attribute \src "issuer_ls180.v:124879.3-124888.6" + wire $1\ldst_port0_addr_exc_o[0:0] + attribute \src "issuer_ls180.v:124817.3-124826.6" + wire width 48 $1\ldst_port0_addr_i$5[47:0]$5188 + attribute \src "issuer_ls180.v:124827.3-124836.6" + wire $1\ldst_port0_addr_i_ok$6[0:0]$5191 + attribute \src "issuer_ls180.v:124869.3-124878.6" + wire $1\ldst_port0_addr_ok_o[0:0] + attribute \src "issuer_ls180.v:124859.3-124868.6" + wire $1\ldst_port0_busy_o[0:0] + attribute \src "issuer_ls180.v:124969.3-124978.6" + wire width 4 $1\ldst_port0_data_len$4[3:0]$5217 + attribute \src "issuer_ls180.v:124979.3-124988.6" + wire $1\ldst_port0_go_die_i[0:0] + attribute \src "issuer_ls180.v:124949.3-124958.6" + wire $1\ldst_port0_is_ld_i$1[0:0]$5211 + attribute \src "issuer_ls180.v:124959.3-124968.6" + wire $1\ldst_port0_is_st_i$2[0:0]$5214 + attribute \src "issuer_ls180.v:124848.3-124858.6" + wire width 64 $1\ldst_port0_ld_data_o[63:0] + attribute \src "issuer_ls180.v:124848.3-124858.6" + wire $1\ldst_port0_ld_data_o_ok[0:0] + attribute \src "issuer_ls180.v:124837.3-124847.6" + wire width 64 $1\ldst_port0_st_data_i$11[63:0]$5195 + attribute \src "issuer_ls180.v:124837.3-124847.6" + wire $1\ldst_port0_st_data_i_ok$10[0:0]$5196 + attribute \src "issuer_ls180.v:124781.7-124781.25" + wire $1\reset_delay[0:0] + attribute \src "issuer_ls180.v:124939.3-124948.6" + wire $1\reset_l_r_reset[0:0] + attribute \src "issuer_ls180.v:124924.3-124938.6" + wire $1\reset_l_s_reset[0:0] + attribute \src "issuer_ls180.v:124889.3-124903.6" + wire $2\idx_l$16$next[0:0]$5204 + attribute \src "issuer_ls180.v:124924.3-124938.6" + wire $2\reset_l_s_reset[0:0] + attribute \src "issuer_ls180.v:124792.18-124792.103" + wire $not$issuer_ls180.v:124792$5181_Y + attribute \src "issuer_ls180.v:124793.18-124793.117" + wire $not$issuer_ls180.v:124793$5182_Y + attribute \src "issuer_ls180.v:124790.18-124790.134" + wire $or$issuer_ls180.v:124790$5179_Y + attribute \src "issuer_ls180.v:124791.18-124791.120" + wire $ternary$issuer_ls180.v:124791$5180_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:262" + wire \$13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + wire \$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:278" + wire \$19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:288" + wire \$21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:128" + wire width 96 \$24 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:128" + wire width 96 \$25 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" + wire input 26 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" + wire input 1 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + wire \idx_l$16 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + wire \idx_l$16$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire \idx_l_q_idx_l + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire \idx_l_r_idx_l + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire \idx_l_s_idx_l + attribute \src "issuer_ls180.v:124681.7-124681.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:110" + wire output 8 \ldst_port0_addr_exc_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:110" + wire input 25 \ldst_port0_addr_exc_o$12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 96 input 6 \ldst_port0_addr_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 48 output 18 \ldst_port0_addr_i$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire input 7 \ldst_port0_addr_i_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 19 \ldst_port0_addr_i_ok$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:109" + wire output 9 \ldst_port0_addr_ok_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:109" + wire input 20 \ldst_port0_addr_ok_o$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:105" + wire output 2 \ldst_port0_busy_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:105" + wire input 16 \ldst_port0_busy_o$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:102" + wire width 4 input 5 \ldst_port0_data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:102" + wire width 4 output 17 \ldst_port0_data_len$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:106" + wire \ldst_port0_go_die_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:106" + wire \ldst_port0_go_die_i$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:98" + wire input 3 \ldst_port0_is_ld_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:98" + wire output 14 \ldst_port0_is_ld_i$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:99" + wire input 4 \ldst_port0_is_st_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:99" + wire output 15 \ldst_port0_is_st_i$2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 output 10 \ldst_port0_ld_data_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 input 21 \ldst_port0_ld_data_o$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 11 \ldst_port0_ld_data_o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire input 22 \ldst_port0_ld_data_o_ok$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 input 12 \ldst_port0_st_data_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 output 24 \ldst_port0_st_data_i$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire input 13 \ldst_port0_st_data_i_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 23 \ldst_port0_st_data_i_ok$10 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:75" + wire \pick_i + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:77" + wire \pick_n + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:76" + wire \pick_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:292" + wire \reset_delay + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:292" + wire \reset_delay$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire \reset_l_q_reset + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire \reset_l_r_reset + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire \reset_l_s_reset + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:278" + cell $not $not$issuer_ls180.v:124792$5181 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \pick_n + connect \Y $not$issuer_ls180.v:124792$5181_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:288" + cell $not $not$issuer_ls180.v:124793$5182 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \ldst_port0_busy_o$3 + connect \Y $not$issuer_ls180.v:124793$5182_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:262" + cell $or $or$issuer_ls180.v:124790$5179 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \ldst_port0_is_ld_i + connect \B \ldst_port0_is_st_i + connect \Y $or$issuer_ls180.v:124790$5179_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + cell $mux $ternary$issuer_ls180.v:124791$5180 + parameter \WIDTH 1 + connect \A \idx_l$16 + connect \B \pick_o + connect \S \idx_l_q_idx_l + connect \Y $ternary$issuer_ls180.v:124791$5180_Y + end + attribute \module_not_derived 1 + attribute \src "issuer_ls180.v:124798.9-124804.4" + cell \idx_l \idx_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_idx_l \idx_l_q_idx_l + connect \r_idx_l \idx_l_r_idx_l + connect \s_idx_l \idx_l_s_idx_l + end + attribute \module_not_derived 1 + attribute \src "issuer_ls180.v:124805.8-124809.4" + cell \pick \pick + connect \i \pick_i + connect \n \pick_n + connect \o \pick_o + end + attribute \module_not_derived 1 + attribute \src "issuer_ls180.v:124810.17-124816.4" + cell \reset_l$128 \reset_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_reset \reset_l_q_reset + connect \r_reset \reset_l_r_reset + connect \s_reset \reset_l_s_reset + end + attribute \src "issuer_ls180.v:124681.7-124681.20" + process $proc$issuer_ls180.v:124681$5219 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "issuer_ls180.v:124701.7-124701.24" + process $proc$issuer_ls180.v:124701$5220 + assign { } { } + assign $0\idx_l$16[0:0]$5221 1'0 + sync always + sync init + update \idx_l$16 $0\idx_l$16[0:0]$5221 + end + attribute \src "issuer_ls180.v:124781.7-124781.25" + process $proc$issuer_ls180.v:124781$5222 + assign { } { } + assign $1\reset_delay[0:0] 1'0 + sync always + sync init + update \reset_delay $1\reset_delay[0:0] + end + attribute \src "issuer_ls180.v:124794.3-124795.36" + process $proc$issuer_ls180.v:124794$5183 + assign { } { } + assign $0\reset_delay[0:0] \reset_l_q_reset + sync posedge \coresync_clk + update \reset_delay $0\reset_delay[0:0] + end + attribute \src "issuer_ls180.v:124796.3-124797.35" + process $proc$issuer_ls180.v:124796$5184 + assign { } { } + assign $0\idx_l$16[0:0]$5185 \idx_l$16$next + sync posedge \coresync_clk + update \idx_l$16 $0\idx_l$16[0:0]$5185 + end + attribute \src "issuer_ls180.v:124817.3-124826.6" + process $proc$issuer_ls180.v:124817$5186 + assign { } { } + assign { } { } + assign $0\ldst_port0_addr_i$5[47:0]$5187 $1\ldst_port0_addr_i$5[47:0]$5188 + attribute \src "issuer_ls180.v:124818.5-124818.29" + switch \initial + attribute \src "issuer_ls180.v:124818.9-124818.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:286" + switch \idx_l_q_idx_l + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\ldst_port0_addr_i$5[47:0]$5188 \$25 [47:0] + case + assign $1\ldst_port0_addr_i$5[47:0]$5188 48'000000000000000000000000000000000000000000000000 + end + sync always + update \ldst_port0_addr_i$5 $0\ldst_port0_addr_i$5[47:0]$5187 + end + attribute \src "issuer_ls180.v:124827.3-124836.6" + process $proc$issuer_ls180.v:124827$5189 + assign { } { } + assign { } { } + assign $0\ldst_port0_addr_i_ok$6[0:0]$5190 $1\ldst_port0_addr_i_ok$6[0:0]$5191 + attribute \src "issuer_ls180.v:124828.5-124828.29" + switch \initial + attribute \src "issuer_ls180.v:124828.9-124828.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:286" + switch \idx_l_q_idx_l + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\ldst_port0_addr_i_ok$6[0:0]$5191 \ldst_port0_addr_i_ok + case + assign $1\ldst_port0_addr_i_ok$6[0:0]$5191 1'0 + end + sync always + update \ldst_port0_addr_i_ok$6 $0\ldst_port0_addr_i_ok$6[0:0]$5190 + end + attribute \src "issuer_ls180.v:124837.3-124847.6" + process $proc$issuer_ls180.v:124837$5192 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\ldst_port0_st_data_i$11[63:0]$5193 $1\ldst_port0_st_data_i$11[63:0]$5195 + assign $0\ldst_port0_st_data_i_ok$10[0:0]$5194 $1\ldst_port0_st_data_i_ok$10[0:0]$5196 + attribute \src "issuer_ls180.v:124838.5-124838.29" + switch \initial + attribute \src "issuer_ls180.v:124838.9-124838.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:286" + switch \idx_l_q_idx_l + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $1\ldst_port0_st_data_i_ok$10[0:0]$5196 $1\ldst_port0_st_data_i$11[63:0]$5195 } { \ldst_port0_st_data_i_ok \ldst_port0_st_data_i } + case + assign $1\ldst_port0_st_data_i$11[63:0]$5195 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\ldst_port0_st_data_i_ok$10[0:0]$5196 1'0 + end + sync always + update \ldst_port0_st_data_i$11 $0\ldst_port0_st_data_i$11[63:0]$5193 + update \ldst_port0_st_data_i_ok$10 $0\ldst_port0_st_data_i_ok$10[0:0]$5194 + end + attribute \src "issuer_ls180.v:124848.3-124858.6" + process $proc$issuer_ls180.v:124848$5197 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\ldst_port0_ld_data_o[63:0] $1\ldst_port0_ld_data_o[63:0] + assign $0\ldst_port0_ld_data_o_ok[0:0] $1\ldst_port0_ld_data_o_ok[0:0] + attribute \src "issuer_ls180.v:124849.5-124849.29" + switch \initial + attribute \src "issuer_ls180.v:124849.9-124849.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:286" + switch \idx_l_q_idx_l + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $1\ldst_port0_ld_data_o_ok[0:0] $1\ldst_port0_ld_data_o[63:0] } { \ldst_port0_ld_data_o_ok$9 \ldst_port0_ld_data_o$8 } + case + assign $1\ldst_port0_ld_data_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\ldst_port0_ld_data_o_ok[0:0] 1'0 + end + sync always + update \ldst_port0_ld_data_o $0\ldst_port0_ld_data_o[63:0] + update \ldst_port0_ld_data_o_ok $0\ldst_port0_ld_data_o_ok[0:0] + end + attribute \src "issuer_ls180.v:124859.3-124868.6" + process $proc$issuer_ls180.v:124859$5198 + assign { } { } + assign { } { } + assign $0\ldst_port0_busy_o[0:0] $1\ldst_port0_busy_o[0:0] + attribute \src "issuer_ls180.v:124860.5-124860.29" + switch \initial + attribute \src "issuer_ls180.v:124860.9-124860.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:286" + switch \idx_l_q_idx_l + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\ldst_port0_busy_o[0:0] \ldst_port0_busy_o$3 + case + assign $1\ldst_port0_busy_o[0:0] 1'0 + end + sync always + update \ldst_port0_busy_o $0\ldst_port0_busy_o[0:0] + end + attribute \src "issuer_ls180.v:124869.3-124878.6" + process $proc$issuer_ls180.v:124869$5199 + assign { } { } + assign { } { } + assign $0\ldst_port0_addr_ok_o[0:0] $1\ldst_port0_addr_ok_o[0:0] + attribute \src "issuer_ls180.v:124870.5-124870.29" + switch \initial + attribute \src "issuer_ls180.v:124870.9-124870.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:286" + switch \idx_l_q_idx_l + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\ldst_port0_addr_ok_o[0:0] \ldst_port0_addr_ok_o$7 + case + assign $1\ldst_port0_addr_ok_o[0:0] 1'0 + end + sync always + update \ldst_port0_addr_ok_o $0\ldst_port0_addr_ok_o[0:0] + end + attribute \src "issuer_ls180.v:124879.3-124888.6" + process $proc$issuer_ls180.v:124879$5200 + assign { } { } + assign { } { } + assign $0\ldst_port0_addr_exc_o[0:0] $1\ldst_port0_addr_exc_o[0:0] + attribute \src "issuer_ls180.v:124880.5-124880.29" + switch \initial + attribute \src "issuer_ls180.v:124880.9-124880.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:286" + switch \idx_l_q_idx_l + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\ldst_port0_addr_exc_o[0:0] \ldst_port0_addr_exc_o$12 + case + assign $1\ldst_port0_addr_exc_o[0:0] 1'0 + end + sync always + update \ldst_port0_addr_exc_o $0\ldst_port0_addr_exc_o[0:0] + end + attribute \src "issuer_ls180.v:124889.3-124903.6" + process $proc$issuer_ls180.v:124889$5201 + assign { } { } + assign { } { } + assign { } { } + assign $0\idx_l$16$next[0:0]$5202 $2\idx_l$16$next[0:0]$5204 + attribute \src "issuer_ls180.v:124890.5-124890.29" + switch \initial + attribute \src "issuer_ls180.v:124890.9-124890.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" + switch \idx_l_q_idx_l + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\idx_l$16$next[0:0]$5203 \pick_o + case + assign $1\idx_l$16$next[0:0]$5203 \idx_l$16 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\idx_l$16$next[0:0]$5204 1'0 + case + assign $2\idx_l$16$next[0:0]$5204 $1\idx_l$16$next[0:0]$5203 + end + sync always + update \idx_l$16$next $0\idx_l$16$next[0:0]$5202 + end + attribute \src "issuer_ls180.v:124904.3-124913.6" + process $proc$issuer_ls180.v:124904$5205 + assign { } { } + assign { } { } + assign $0\idx_l_r_idx_l[0:0] $1\idx_l_r_idx_l[0:0] + attribute \src "issuer_ls180.v:124905.5-124905.29" + switch \initial + attribute \src "issuer_ls180.v:124905.9-124905.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:296" + switch \reset_l_q_reset + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\idx_l_r_idx_l[0:0] 1'1 + case + assign $1\idx_l_r_idx_l[0:0] 1'1 + end + sync always + update \idx_l_r_idx_l $0\idx_l_r_idx_l[0:0] + end + attribute \src "issuer_ls180.v:124914.3-124923.6" + process $proc$issuer_ls180.v:124914$5206 + assign { } { } + assign { } { } + assign $0\idx_l_s_idx_l[0:0] $1\idx_l_s_idx_l[0:0] + attribute \src "issuer_ls180.v:124915.5-124915.29" + switch \initial + attribute \src "issuer_ls180.v:124915.9-124915.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:278" + switch \$19 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\idx_l_s_idx_l[0:0] 1'1 + case + assign $1\idx_l_s_idx_l[0:0] 1'0 + end + sync always + update \idx_l_s_idx_l $0\idx_l_s_idx_l[0:0] + end + attribute \src "issuer_ls180.v:124924.3-124938.6" + process $proc$issuer_ls180.v:124924$5207 + assign { } { } + assign { } { } + assign $0\reset_l_s_reset[0:0] $1\reset_l_s_reset[0:0] + attribute \src "issuer_ls180.v:124925.5-124925.29" + switch \initial + attribute \src "issuer_ls180.v:124925.9-124925.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:286" + switch \idx_l_q_idx_l + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\reset_l_s_reset[0:0] $2\reset_l_s_reset[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:288" + switch \$21 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\reset_l_s_reset[0:0] 1'1 + case + assign $2\reset_l_s_reset[0:0] 1'0 + end + case + assign $1\reset_l_s_reset[0:0] 1'0 + end + sync always + update \reset_l_s_reset $0\reset_l_s_reset[0:0] + end + attribute \src "issuer_ls180.v:124939.3-124948.6" + process $proc$issuer_ls180.v:124939$5208 + assign { } { } + assign { } { } + assign $0\reset_l_r_reset[0:0] $1\reset_l_r_reset[0:0] + attribute \src "issuer_ls180.v:124940.5-124940.29" + switch \initial + attribute \src "issuer_ls180.v:124940.9-124940.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:296" + switch \reset_l_q_reset + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\reset_l_r_reset[0:0] 1'1 + case + assign $1\reset_l_r_reset[0:0] 1'0 + end + sync always + update \reset_l_r_reset $0\reset_l_r_reset[0:0] + end + attribute \src "issuer_ls180.v:124949.3-124958.6" + process $proc$issuer_ls180.v:124949$5209 + assign { } { } + assign { } { } + assign $0\ldst_port0_is_ld_i$1[0:0]$5210 $1\ldst_port0_is_ld_i$1[0:0]$5211 + attribute \src "issuer_ls180.v:124950.5-124950.29" + switch \initial + attribute \src "issuer_ls180.v:124950.9-124950.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:286" + switch \idx_l_q_idx_l + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\ldst_port0_is_ld_i$1[0:0]$5211 \ldst_port0_is_ld_i + case + assign $1\ldst_port0_is_ld_i$1[0:0]$5211 1'0 + end + sync always + update \ldst_port0_is_ld_i$1 $0\ldst_port0_is_ld_i$1[0:0]$5210 + end + attribute \src "issuer_ls180.v:124959.3-124968.6" + process $proc$issuer_ls180.v:124959$5212 + assign { } { } + assign { } { } + assign $0\ldst_port0_is_st_i$2[0:0]$5213 $1\ldst_port0_is_st_i$2[0:0]$5214 + attribute \src "issuer_ls180.v:124960.5-124960.29" + switch \initial + attribute \src "issuer_ls180.v:124960.9-124960.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:286" + switch \idx_l_q_idx_l + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\ldst_port0_is_st_i$2[0:0]$5214 \ldst_port0_is_st_i + case + assign $1\ldst_port0_is_st_i$2[0:0]$5214 1'0 + end + sync always + update \ldst_port0_is_st_i$2 $0\ldst_port0_is_st_i$2[0:0]$5213 + end + attribute \src "issuer_ls180.v:124969.3-124978.6" + process $proc$issuer_ls180.v:124969$5215 + assign { } { } + assign { } { } + assign $0\ldst_port0_data_len$4[3:0]$5216 $1\ldst_port0_data_len$4[3:0]$5217 + attribute \src "issuer_ls180.v:124970.5-124970.29" + switch \initial + attribute \src "issuer_ls180.v:124970.9-124970.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:286" + switch \idx_l_q_idx_l + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\ldst_port0_data_len$4[3:0]$5217 \ldst_port0_data_len + case + assign $1\ldst_port0_data_len$4[3:0]$5217 4'0000 + end + sync always + update \ldst_port0_data_len$4 $0\ldst_port0_data_len$4[3:0]$5216 + end + attribute \src "issuer_ls180.v:124979.3-124988.6" + process $proc$issuer_ls180.v:124979$5218 + assign { } { } + assign { } { } + assign $0\ldst_port0_go_die_i[0:0] $1\ldst_port0_go_die_i[0:0] + attribute \src "issuer_ls180.v:124980.5-124980.29" + switch \initial + attribute \src "issuer_ls180.v:124980.9-124980.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:286" + switch \idx_l_q_idx_l + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\ldst_port0_go_die_i[0:0] \ldst_port0_go_die_i$23 + case + assign $1\ldst_port0_go_die_i[0:0] 1'0 + end + sync always + update \ldst_port0_go_die_i $0\ldst_port0_go_die_i[0:0] + end + connect \$13 $or$issuer_ls180.v:124790$5179_Y + connect \$17 $ternary$issuer_ls180.v:124791$5180_Y + connect \$19 $not$issuer_ls180.v:124792$5181_Y + connect \$21 $not$issuer_ls180.v:124793$5182_Y + connect \$15 \$17 + connect \$25 \ldst_port0_addr_i + connect \ldst_port0_go_die_i$23 1'0 + connect \reset_delay$next \reset_l_q_reset + connect \pick_i \$13 +end +attribute \src "issuer_ls180.v:124998.1-125056.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.l0.pimem.ld_active" +attribute \generator "nMigen" +module \ld_active + attribute \src "issuer_ls180.v:124999.7-124999.20" + wire $0\initial[0:0] + attribute \src "issuer_ls180.v:125044.3-125052.6" + wire $0\q_int$next[0:0]$5233 + attribute \src "issuer_ls180.v:125042.3-125043.27" + wire $0\q_int[0:0] + attribute \src "issuer_ls180.v:125044.3-125052.6" + wire $1\q_int$next[0:0]$5234 + attribute \src "issuer_ls180.v:125021.7-125021.19" + wire $1\q_int[0:0] + attribute \src "issuer_ls180.v:125034.17-125034.96" + wire $and$issuer_ls180.v:125034$5223_Y + attribute \src "issuer_ls180.v:125039.17-125039.96" + wire $and$issuer_ls180.v:125039$5228_Y + attribute \src "issuer_ls180.v:125036.18-125036.99" + wire $not$issuer_ls180.v:125036$5225_Y + attribute \src "issuer_ls180.v:125038.17-125038.98" + wire $not$issuer_ls180.v:125038$5227_Y + attribute \src "issuer_ls180.v:125041.17-125041.98" + wire $not$issuer_ls180.v:125041$5230_Y + attribute \src "issuer_ls180.v:125035.18-125035.104" + wire $or$issuer_ls180.v:125035$5224_Y + attribute \src "issuer_ls180.v:125037.18-125037.105" + wire $or$issuer_ls180.v:125037$5226_Y + attribute \src "issuer_ls180.v:125040.17-125040.103" + wire $or$issuer_ls180.v:125040$5229_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire \$13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" + wire input 5 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" + wire input 1 \coresync_rst + attribute \src "issuer_ls180.v:124999.7-124999.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire output 4 \q_ld_active + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" + wire \qlq_ld_active + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + wire \qn_ld_active + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire input 2 \r_ld_active + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire input 3 \s_ld_active + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $and $and$issuer_ls180.v:125034$5223 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$7 + connect \Y $and$issuer_ls180.v:125034$5223_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $and $and$issuer_ls180.v:125039$5228 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$1 + connect \Y $and$issuer_ls180.v:125039$5228_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + cell $not $not$issuer_ls180.v:125036$5225 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_ld_active + connect \Y $not$issuer_ls180.v:125036$5225_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $not $not$issuer_ls180.v:125038$5227 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_ld_active + connect \Y $not$issuer_ls180.v:125038$5227_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $not $not$issuer_ls180.v:125041$5230 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_ld_active + connect \Y $not$issuer_ls180.v:125041$5230_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $or $or$issuer_ls180.v:125035$5224 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$9 + connect \B \s_ld_active + connect \Y $or$issuer_ls180.v:125035$5224_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + cell $or $or$issuer_ls180.v:125037$5226 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_ld_active + connect \B \q_int + connect \Y $or$issuer_ls180.v:125037$5226_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $or $or$issuer_ls180.v:125040$5229 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$3 + connect \B \s_ld_active + connect \Y $or$issuer_ls180.v:125040$5229_Y + end + attribute \src "issuer_ls180.v:124999.7-124999.20" + process $proc$issuer_ls180.v:124999$5235 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "issuer_ls180.v:125021.7-125021.19" + process $proc$issuer_ls180.v:125021$5236 + assign { } { } + assign $1\q_int[0:0] 1'0 + sync always + sync init + update \q_int $1\q_int[0:0] + end + attribute \src "issuer_ls180.v:125042.3-125043.27" + process $proc$issuer_ls180.v:125042$5231 + assign { } { } + assign $0\q_int[0:0] \q_int$next + sync posedge \coresync_clk + update \q_int $0\q_int[0:0] + end + attribute \src "issuer_ls180.v:125044.3-125052.6" + process $proc$issuer_ls180.v:125044$5232 + assign { } { } + assign { } { } + assign $0\q_int$next[0:0]$5233 $1\q_int$next[0:0]$5234 + attribute \src "issuer_ls180.v:125045.5-125045.29" + switch \initial + attribute \src "issuer_ls180.v:125045.9-125045.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\q_int$next[0:0]$5234 1'0 + case + assign $1\q_int$next[0:0]$5234 \$5 + end + sync always + update \q_int$next $0\q_int$next[0:0]$5233 + end + connect \$9 $and$issuer_ls180.v:125034$5223_Y + connect \$11 $or$issuer_ls180.v:125035$5224_Y + connect \$13 $not$issuer_ls180.v:125036$5225_Y + connect \$15 $or$issuer_ls180.v:125037$5226_Y + connect \$1 $not$issuer_ls180.v:125038$5227_Y + connect \$3 $and$issuer_ls180.v:125039$5228_Y + connect \$5 $or$issuer_ls180.v:125040$5229_Y + connect \$7 $not$issuer_ls180.v:125041$5230_Y + connect \qlq_ld_active \$15 + connect \qn_ld_active \$13 + connect \q_ld_active \$11 +end +attribute \src "issuer_ls180.v:125060.1-126389.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.fus.ldst0" +attribute \generator "nMigen" +module \ldst0 + attribute \src "issuer_ls180.v:126044.3-126052.6" + wire $0\adr_l_r_adr$next[0:0]$5379 + attribute \src "issuer_ls180.v:125926.3-125927.39" + wire $0\adr_l_r_adr[0:0] + attribute \src "issuer_ls180.v:125872.3-125873.21" + wire $0\alu_ok[0:0] + attribute \src "issuer_ls180.v:126209.3-126218.6" + wire width 64 $0\dest1_o[63:0] + attribute \src "issuer_ls180.v:126219.3-126228.6" + wire width 64 $0\dest2_o[63:0] + attribute \src "issuer_ls180.v:126199.3-126208.6" + wire width 64 $0\ea_r$next[63:0]$5467 + attribute \src "issuer_ls180.v:125874.3-125875.25" + wire width 64 $0\ea_r[63:0] + attribute \src "issuer_ls180.v:125061.7-125061.20" + wire $0\initial[0:0] + attribute \src "issuer_ls180.v:126274.3-126293.6" + wire width 64 $0\ldd_o[63:0] + attribute \src "issuer_ls180.v:126238.3-126261.6" + wire width 64 $0\lddata_r[63:0] + attribute \src "issuer_ls180.v:126141.3-126150.6" + wire width 64 $0\ldo_r$next[63:0]$5452 + attribute \src "issuer_ls180.v:125882.3-125883.27" + wire width 64 $0\ldo_r[63:0] + attribute \src "issuer_ls180.v:125870.3-125871.33" + wire width 96 $0\ldst_port0_addr_i[95:0] + attribute \src "issuer_ls180.v:126229.3-126237.6" + wire $0\ldst_port0_addr_i_ok$next[0:0]$5472 + attribute \src "issuer_ls180.v:125868.3-125869.57" + wire $0\ldst_port0_addr_i_ok[0:0] + attribute \src "issuer_ls180.v:126318.3-126329.6" + wire width 64 $0\ldst_port0_st_data_i[63:0] + attribute \src "issuer_ls180.v:126089.3-126097.6" + wire $0\lsd_l_r_lsd$next[0:0]$5394 + attribute \src "issuer_ls180.v:125916.3-125917.39" + wire $0\lsd_l_r_lsd[0:0] + attribute \src "issuer_ls180.v:126017.3-126025.6" + wire $0\opc_l_r_opc$next[0:0]$5370 + attribute \src "issuer_ls180.v:125932.3-125933.39" + wire $0\opc_l_r_opc[0:0] + attribute \src "issuer_ls180.v:126008.3-126016.6" + wire $0\opc_l_s_opc$next[0:0]$5367 + attribute \src "issuer_ls180.v:125934.3-125935.39" + wire $0\opc_l_s_opc[0:0] + attribute \src "issuer_ls180.v:126098.3-126140.6" + wire $0\oper_r__byte_reverse$next[0:0]$5397 + attribute \src "issuer_ls180.v:125908.3-125909.57" + wire $0\oper_r__byte_reverse[0:0] + attribute \src "issuer_ls180.v:126098.3-126140.6" + wire width 4 $0\oper_r__data_len$next[3:0]$5398 + attribute \src "issuer_ls180.v:125906.3-125907.49" + wire width 4 $0\oper_r__data_len[3:0] + attribute \src "issuer_ls180.v:126098.3-126140.6" + wire width 12 $0\oper_r__fn_unit$next[11:0]$5399 + attribute \src "issuer_ls180.v:125886.3-125887.47" + wire width 12 $0\oper_r__fn_unit[11:0] + attribute \src "issuer_ls180.v:126098.3-126140.6" + wire width 64 $0\oper_r__imm_data__data$next[63:0]$5400 + attribute \src "issuer_ls180.v:125888.3-125889.61" + wire width 64 $0\oper_r__imm_data__data[63:0] + attribute \src "issuer_ls180.v:126098.3-126140.6" + wire $0\oper_r__imm_data__ok$next[0:0]$5401 + attribute \src "issuer_ls180.v:125890.3-125891.57" + wire $0\oper_r__imm_data__ok[0:0] + attribute \src "issuer_ls180.v:126098.3-126140.6" + wire width 32 $0\oper_r__insn$next[31:0]$5402 + attribute \src "issuer_ls180.v:125914.3-125915.41" + wire width 32 $0\oper_r__insn[31:0] + attribute \src "issuer_ls180.v:126098.3-126140.6" + wire width 7 $0\oper_r__insn_type$next[6:0]$5403 + attribute \src "issuer_ls180.v:125884.3-125885.51" + wire width 7 $0\oper_r__insn_type[6:0] + attribute \src "issuer_ls180.v:126098.3-126140.6" + wire $0\oper_r__is_32bit$next[0:0]$5404 + attribute \src "issuer_ls180.v:125902.3-125903.49" + wire $0\oper_r__is_32bit[0:0] + attribute \src "issuer_ls180.v:126098.3-126140.6" + wire $0\oper_r__is_signed$next[0:0]$5405 + attribute \src "issuer_ls180.v:125904.3-125905.51" + wire $0\oper_r__is_signed[0:0] + attribute \src "issuer_ls180.v:126098.3-126140.6" + wire width 2 $0\oper_r__ldst_mode$next[1:0]$5406 + attribute \src "issuer_ls180.v:125912.3-125913.51" + wire width 2 $0\oper_r__ldst_mode[1:0] + attribute \src "issuer_ls180.v:126098.3-126140.6" + wire $0\oper_r__oe__oe$next[0:0]$5407 + attribute \src "issuer_ls180.v:125898.3-125899.45" + wire $0\oper_r__oe__oe[0:0] + attribute \src "issuer_ls180.v:126098.3-126140.6" + wire $0\oper_r__oe__ok$next[0:0]$5408 + attribute \src "issuer_ls180.v:125900.3-125901.45" + wire $0\oper_r__oe__ok[0:0] + attribute \src "issuer_ls180.v:126098.3-126140.6" + wire $0\oper_r__rc__ok$next[0:0]$5409 + attribute \src "issuer_ls180.v:125896.3-125897.45" + wire $0\oper_r__rc__ok[0:0] + attribute \src "issuer_ls180.v:126098.3-126140.6" + wire $0\oper_r__rc__rc$next[0:0]$5410 + attribute \src "issuer_ls180.v:125894.3-125895.45" + wire $0\oper_r__rc__rc[0:0] + attribute \src "issuer_ls180.v:126098.3-126140.6" + wire $0\oper_r__sign_extend$next[0:0]$5411 + attribute \src "issuer_ls180.v:125910.3-125911.55" + wire $0\oper_r__sign_extend[0:0] + attribute \src "issuer_ls180.v:126098.3-126140.6" + wire $0\oper_r__zero_a$next[0:0]$5412 + attribute \src "issuer_ls180.v:125892.3-125893.45" + wire $0\oper_r__zero_a[0:0] + attribute \src "issuer_ls180.v:125936.3-125937.28" + wire $0\p_st_go[0:0] + attribute \src "issuer_ls180.v:126262.3-126273.6" + wire width 64 $0\revnorev[63:0] + attribute \src "issuer_ls180.v:126035.3-126043.6" + wire width 3 $0\src_l_r_src$next[2:0]$5376 + attribute \src "issuer_ls180.v:125928.3-125929.39" + wire width 3 $0\src_l_r_src[2:0] + attribute \src "issuer_ls180.v:126026.3-126034.6" + wire width 3 $0\src_l_s_src$next[2:0]$5373 + attribute \src "issuer_ls180.v:125930.3-125931.39" + wire width 3 $0\src_l_s_src[2:0] + attribute \src "issuer_ls180.v:126151.3-126166.6" + wire width 64 $0\src_r0$next[63:0]$5455 + attribute \src "issuer_ls180.v:125880.3-125881.29" + wire width 64 $0\src_r0[63:0] + attribute \src "issuer_ls180.v:126167.3-126182.6" + wire width 64 $0\src_r1$next[63:0]$5459 + attribute \src "issuer_ls180.v:125878.3-125879.29" + wire width 64 $0\src_r1[63:0] + attribute \src "issuer_ls180.v:126183.3-126198.6" + wire width 64 $0\src_r2$next[63:0]$5463 + attribute \src "issuer_ls180.v:125876.3-125877.29" + wire width 64 $0\src_r2[63:0] + attribute \src "issuer_ls180.v:126294.3-126317.6" + wire width 64 $0\stdata_r[63:0] + attribute \src "issuer_ls180.v:126080.3-126088.6" + wire $0\sto_l_r_sto$next[0:0]$5391 + attribute \src "issuer_ls180.v:125918.3-125919.39" + wire $0\sto_l_r_sto[0:0] + attribute \src "issuer_ls180.v:126071.3-126079.6" + wire $0\upd_l_r_upd$next[0:0]$5388 + attribute \src "issuer_ls180.v:125920.3-125921.39" + wire $0\upd_l_r_upd[0:0] + attribute \src "issuer_ls180.v:126062.3-126070.6" + wire $0\upd_l_s_upd$next[0:0]$5385 + attribute \src "issuer_ls180.v:125922.3-125923.39" + wire $0\upd_l_s_upd[0:0] + attribute \src "issuer_ls180.v:126053.3-126061.6" + wire $0\wri_l_r_wri$next[0:0]$5382 + attribute \src "issuer_ls180.v:125924.3-125925.39" + wire $0\wri_l_r_wri[0:0] + attribute \src "issuer_ls180.v:126044.3-126052.6" + wire $1\adr_l_r_adr$next[0:0]$5380 + attribute \src "issuer_ls180.v:125259.7-125259.25" + wire $1\adr_l_r_adr[0:0] + attribute \src "issuer_ls180.v:125273.7-125273.20" + wire $1\alu_ok[0:0] + attribute \src "issuer_ls180.v:126209.3-126218.6" + wire width 64 $1\dest1_o[63:0] + attribute \src "issuer_ls180.v:126219.3-126228.6" + wire width 64 $1\dest2_o[63:0] + attribute \src "issuer_ls180.v:126199.3-126208.6" + wire width 64 $1\ea_r$next[63:0]$5468 + attribute \src "issuer_ls180.v:125319.14-125319.41" + wire width 64 $1\ea_r[63:0] + attribute \src "issuer_ls180.v:126274.3-126293.6" + wire width 64 $1\ldd_o[63:0] + attribute \src "issuer_ls180.v:126238.3-126261.6" + wire width 64 $1\lddata_r[63:0] + attribute \src "issuer_ls180.v:126141.3-126150.6" + wire width 64 $1\ldo_r$next[63:0]$5453 + attribute \src "issuer_ls180.v:125333.14-125333.42" + wire width 64 $1\ldo_r[63:0] + attribute \src "issuer_ls180.v:125340.14-125340.62" + wire width 96 $1\ldst_port0_addr_i[95:0] + attribute \src "issuer_ls180.v:126229.3-126237.6" + wire $1\ldst_port0_addr_i_ok$next[0:0]$5473 + attribute \src "issuer_ls180.v:125345.7-125345.34" + wire $1\ldst_port0_addr_i_ok[0:0] + attribute \src "issuer_ls180.v:126318.3-126329.6" + wire width 64 $1\ldst_port0_st_data_i[63:0] + attribute \src "issuer_ls180.v:126089.3-126097.6" + wire $1\lsd_l_r_lsd$next[0:0]$5395 + attribute \src "issuer_ls180.v:125378.7-125378.25" + wire $1\lsd_l_r_lsd[0:0] + attribute \src "issuer_ls180.v:126017.3-126025.6" + wire $1\opc_l_r_opc$next[0:0]$5371 + attribute \src "issuer_ls180.v:125392.7-125392.25" + wire $1\opc_l_r_opc[0:0] + attribute \src "issuer_ls180.v:126008.3-126016.6" + wire $1\opc_l_s_opc$next[0:0]$5368 + attribute \src "issuer_ls180.v:125396.7-125396.25" + wire $1\opc_l_s_opc[0:0] + attribute \src "issuer_ls180.v:126098.3-126140.6" + wire $1\oper_r__byte_reverse$next[0:0]$5413 + attribute \src "issuer_ls180.v:125524.7-125524.34" + wire $1\oper_r__byte_reverse[0:0] + attribute \src "issuer_ls180.v:126098.3-126140.6" + wire width 4 $1\oper_r__data_len$next[3:0]$5414 + attribute \src "issuer_ls180.v:125528.13-125528.36" + wire width 4 $1\oper_r__data_len[3:0] + attribute \src "issuer_ls180.v:126098.3-126140.6" + wire width 12 $1\oper_r__fn_unit$next[11:0]$5415 + attribute \src "issuer_ls180.v:125545.14-125545.39" + wire width 12 $1\oper_r__fn_unit[11:0] + attribute \src "issuer_ls180.v:126098.3-126140.6" + wire width 64 $1\oper_r__imm_data__data$next[63:0]$5416 + attribute \src "issuer_ls180.v:125549.14-125549.59" + wire width 64 $1\oper_r__imm_data__data[63:0] + attribute \src "issuer_ls180.v:126098.3-126140.6" + wire $1\oper_r__imm_data__ok$next[0:0]$5417 + attribute \src "issuer_ls180.v:125553.7-125553.34" + wire $1\oper_r__imm_data__ok[0:0] + attribute \src "issuer_ls180.v:126098.3-126140.6" + wire width 32 $1\oper_r__insn$next[31:0]$5418 + attribute \src "issuer_ls180.v:125557.14-125557.34" + wire width 32 $1\oper_r__insn[31:0] + attribute \src "issuer_ls180.v:126098.3-126140.6" + wire width 7 $1\oper_r__insn_type$next[6:0]$5419 + attribute \src "issuer_ls180.v:125635.13-125635.38" + wire width 7 $1\oper_r__insn_type[6:0] + attribute \src "issuer_ls180.v:126098.3-126140.6" + wire $1\oper_r__is_32bit$next[0:0]$5420 + attribute \src "issuer_ls180.v:125639.7-125639.30" + wire $1\oper_r__is_32bit[0:0] + attribute \src "issuer_ls180.v:126098.3-126140.6" + wire $1\oper_r__is_signed$next[0:0]$5421 + attribute \src "issuer_ls180.v:125643.7-125643.31" + wire $1\oper_r__is_signed[0:0] + attribute \src "issuer_ls180.v:126098.3-126140.6" + wire width 2 $1\oper_r__ldst_mode$next[1:0]$5422 + attribute \src "issuer_ls180.v:125652.13-125652.37" + wire width 2 $1\oper_r__ldst_mode[1:0] + attribute \src "issuer_ls180.v:126098.3-126140.6" + wire $1\oper_r__oe__oe$next[0:0]$5423 + attribute \src "issuer_ls180.v:125656.7-125656.28" + wire $1\oper_r__oe__oe[0:0] + attribute \src "issuer_ls180.v:126098.3-126140.6" + wire $1\oper_r__oe__ok$next[0:0]$5424 + attribute \src "issuer_ls180.v:125660.7-125660.28" + wire $1\oper_r__oe__ok[0:0] + attribute \src "issuer_ls180.v:126098.3-126140.6" + wire $1\oper_r__rc__ok$next[0:0]$5425 + attribute \src "issuer_ls180.v:125664.7-125664.28" + wire $1\oper_r__rc__ok[0:0] + attribute \src "issuer_ls180.v:126098.3-126140.6" + wire $1\oper_r__rc__rc$next[0:0]$5426 + attribute \src "issuer_ls180.v:125668.7-125668.28" + wire $1\oper_r__rc__rc[0:0] + attribute \src "issuer_ls180.v:126098.3-126140.6" + wire $1\oper_r__sign_extend$next[0:0]$5427 + attribute \src "issuer_ls180.v:125672.7-125672.33" + wire $1\oper_r__sign_extend[0:0] + attribute \src "issuer_ls180.v:126098.3-126140.6" + wire $1\oper_r__zero_a$next[0:0]$5428 + attribute \src "issuer_ls180.v:125676.7-125676.28" + wire $1\oper_r__zero_a[0:0] + attribute \src "issuer_ls180.v:125680.7-125680.21" + wire $1\p_st_go[0:0] + attribute \src "issuer_ls180.v:126262.3-126273.6" + wire width 64 $1\revnorev[63:0] + attribute \src "issuer_ls180.v:126035.3-126043.6" + wire width 3 $1\src_l_r_src$next[2:0]$5377 + attribute \src "issuer_ls180.v:125722.13-125722.31" + wire width 3 $1\src_l_r_src[2:0] + attribute \src "issuer_ls180.v:126026.3-126034.6" + wire width 3 $1\src_l_s_src$next[2:0]$5374 + attribute \src "issuer_ls180.v:125726.13-125726.31" + wire width 3 $1\src_l_s_src[2:0] + attribute \src "issuer_ls180.v:126151.3-126166.6" + wire width 64 $1\src_r0$next[63:0]$5456 + attribute \src "issuer_ls180.v:125730.14-125730.43" + wire width 64 $1\src_r0[63:0] + attribute \src "issuer_ls180.v:126167.3-126182.6" + wire width 64 $1\src_r1$next[63:0]$5460 + attribute \src "issuer_ls180.v:125734.14-125734.43" + wire width 64 $1\src_r1[63:0] + attribute \src "issuer_ls180.v:126183.3-126198.6" + wire width 64 $1\src_r2$next[63:0]$5464 + attribute \src "issuer_ls180.v:125738.14-125738.43" + wire width 64 $1\src_r2[63:0] + attribute \src "issuer_ls180.v:126294.3-126317.6" + wire width 64 $1\stdata_r[63:0] + attribute \src "issuer_ls180.v:126080.3-126088.6" + wire $1\sto_l_r_sto$next[0:0]$5392 + attribute \src "issuer_ls180.v:125748.7-125748.25" + wire $1\sto_l_r_sto[0:0] + attribute \src "issuer_ls180.v:126071.3-126079.6" + wire $1\upd_l_r_upd$next[0:0]$5389 + attribute \src "issuer_ls180.v:125758.7-125758.25" + wire $1\upd_l_r_upd[0:0] + attribute \src "issuer_ls180.v:126062.3-126070.6" + wire $1\upd_l_s_upd$next[0:0]$5386 + attribute \src "issuer_ls180.v:125762.7-125762.25" + wire $1\upd_l_s_upd[0:0] + attribute \src "issuer_ls180.v:126053.3-126061.6" + wire $1\wri_l_r_wri$next[0:0]$5383 + attribute \src "issuer_ls180.v:125772.7-125772.25" + wire $1\wri_l_r_wri[0:0] + attribute \src "issuer_ls180.v:126274.3-126293.6" + wire width 64 $2\ldd_o[63:0] + attribute \src "issuer_ls180.v:126238.3-126261.6" + wire width 64 $2\lddata_r[63:0] + attribute \src "issuer_ls180.v:126098.3-126140.6" + wire $2\oper_r__byte_reverse$next[0:0]$5429 + attribute \src "issuer_ls180.v:126098.3-126140.6" + wire width 4 $2\oper_r__data_len$next[3:0]$5430 + attribute \src "issuer_ls180.v:126098.3-126140.6" + wire width 12 $2\oper_r__fn_unit$next[11:0]$5431 + attribute \src "issuer_ls180.v:126098.3-126140.6" + wire width 64 $2\oper_r__imm_data__data$next[63:0]$5432 + attribute \src "issuer_ls180.v:126098.3-126140.6" + wire $2\oper_r__imm_data__ok$next[0:0]$5433 + attribute \src "issuer_ls180.v:126098.3-126140.6" + wire width 32 $2\oper_r__insn$next[31:0]$5434 + attribute \src "issuer_ls180.v:126098.3-126140.6" + wire width 7 $2\oper_r__insn_type$next[6:0]$5435 + attribute \src "issuer_ls180.v:126098.3-126140.6" + wire $2\oper_r__is_32bit$next[0:0]$5436 + attribute \src "issuer_ls180.v:126098.3-126140.6" + wire $2\oper_r__is_signed$next[0:0]$5437 + attribute \src "issuer_ls180.v:126098.3-126140.6" + wire width 2 $2\oper_r__ldst_mode$next[1:0]$5438 + attribute \src "issuer_ls180.v:126098.3-126140.6" + wire $2\oper_r__oe__oe$next[0:0]$5439 + attribute \src "issuer_ls180.v:126098.3-126140.6" + wire $2\oper_r__oe__ok$next[0:0]$5440 + attribute \src "issuer_ls180.v:126098.3-126140.6" + wire $2\oper_r__rc__ok$next[0:0]$5441 + attribute \src "issuer_ls180.v:126098.3-126140.6" + wire $2\oper_r__rc__rc$next[0:0]$5442 + attribute \src "issuer_ls180.v:126098.3-126140.6" + wire $2\oper_r__sign_extend$next[0:0]$5443 + attribute \src "issuer_ls180.v:126098.3-126140.6" + wire $2\oper_r__zero_a$next[0:0]$5444 + attribute \src "issuer_ls180.v:126151.3-126166.6" + wire width 64 $2\src_r0$next[63:0]$5457 + attribute \src "issuer_ls180.v:126167.3-126182.6" + wire width 64 $2\src_r1$next[63:0]$5461 + attribute \src "issuer_ls180.v:126183.3-126198.6" + wire width 64 $2\src_r2$next[63:0]$5465 + attribute \src "issuer_ls180.v:126294.3-126317.6" + wire width 64 $2\stdata_r[63:0] + attribute \src "issuer_ls180.v:126098.3-126140.6" + wire width 64 $3\oper_r__imm_data__data$next[63:0]$5445 + attribute \src "issuer_ls180.v:126098.3-126140.6" + wire $3\oper_r__imm_data__ok$next[0:0]$5446 + attribute \src "issuer_ls180.v:126098.3-126140.6" + wire $3\oper_r__oe__oe$next[0:0]$5447 + attribute \src "issuer_ls180.v:126098.3-126140.6" + wire $3\oper_r__oe__ok$next[0:0]$5448 + attribute \src "issuer_ls180.v:126098.3-126140.6" + wire $3\oper_r__rc__ok$next[0:0]$5449 + attribute \src "issuer_ls180.v:126098.3-126140.6" + wire $3\oper_r__rc__rc$next[0:0]$5450 + attribute \src "issuer_ls180.v:125851.18-125851.124" + wire width 65 $add$issuer_ls180.v:125851$5314_Y + attribute \src "issuer_ls180.v:125778.18-125778.124" + wire $and$issuer_ls180.v:125778$5238_Y + attribute \src "issuer_ls180.v:125779.19-125779.117" + wire $and$issuer_ls180.v:125779$5239_Y + attribute \src "issuer_ls180.v:125780.19-125780.119" + wire $and$issuer_ls180.v:125780$5240_Y + attribute \src "issuer_ls180.v:125781.19-125781.123" + wire $and$issuer_ls180.v:125781$5241_Y + attribute \src "issuer_ls180.v:125782.19-125782.123" + wire $and$issuer_ls180.v:125782$5242_Y + attribute \src "issuer_ls180.v:125783.19-125783.120" + wire $and$issuer_ls180.v:125783$5243_Y + attribute \src "issuer_ls180.v:125784.19-125784.123" + wire $and$issuer_ls180.v:125784$5244_Y + attribute \src "issuer_ls180.v:125785.19-125785.119" + wire $and$issuer_ls180.v:125785$5245_Y + attribute \src "issuer_ls180.v:125786.19-125786.123" + wire $and$issuer_ls180.v:125786$5246_Y + attribute \src "issuer_ls180.v:125787.19-125787.125" + wire $and$issuer_ls180.v:125787$5247_Y + attribute \src "issuer_ls180.v:125790.19-125790.116" + wire $and$issuer_ls180.v:125790$5250_Y + attribute \src "issuer_ls180.v:125791.19-125791.120" + wire $and$issuer_ls180.v:125791$5251_Y + attribute \src "issuer_ls180.v:125792.19-125792.123" + wire $and$issuer_ls180.v:125792$5252_Y + attribute \src "issuer_ls180.v:125796.19-125796.125" + wire $and$issuer_ls180.v:125796$5256_Y + attribute \src "issuer_ls180.v:125797.19-125797.123" + wire $and$issuer_ls180.v:125797$5257_Y + attribute \src "issuer_ls180.v:125802.19-125802.116" + wire $and$issuer_ls180.v:125802$5262_Y + attribute \src "issuer_ls180.v:125804.19-125804.116" + wire $and$issuer_ls180.v:125804$5264_Y + attribute \src "issuer_ls180.v:125807.19-125807.118" + wire $and$issuer_ls180.v:125807$5267_Y + attribute \src "issuer_ls180.v:125809.19-125809.125" + wire $and$issuer_ls180.v:125809$5269_Y + attribute \src "issuer_ls180.v:125812.19-125812.160" + wire width 3 $and$issuer_ls180.v:125812$5272_Y + attribute \src "issuer_ls180.v:125813.19-125813.122" + wire $and$issuer_ls180.v:125813$5273_Y + attribute \src "issuer_ls180.v:125814.19-125814.122" + wire $and$issuer_ls180.v:125814$5274_Y + attribute \src "issuer_ls180.v:125816.19-125816.122" + wire $and$issuer_ls180.v:125816$5277_Y + attribute \src "issuer_ls180.v:125826.18-125826.123" + wire $and$issuer_ls180.v:125826$5289_Y + attribute \src "issuer_ls180.v:125827.18-125827.123" + wire $and$issuer_ls180.v:125827$5290_Y + attribute \src "issuer_ls180.v:125829.18-125829.114" + wire $and$issuer_ls180.v:125829$5292_Y + attribute \src "issuer_ls180.v:125831.18-125831.113" + wire $and$issuer_ls180.v:125831$5294_Y + attribute \src "issuer_ls180.v:125834.18-125834.113" + wire $and$issuer_ls180.v:125834$5297_Y + attribute \src "issuer_ls180.v:125839.18-125839.113" + wire $and$issuer_ls180.v:125839$5302_Y + attribute \src "issuer_ls180.v:125842.18-125842.119" + wire $and$issuer_ls180.v:125842$5305_Y + attribute \src "issuer_ls180.v:125852.18-125852.150" + wire width 3 $and$issuer_ls180.v:125852$5315_Y + attribute \src "issuer_ls180.v:125854.18-125854.113" + wire width 3 $and$issuer_ls180.v:125854$5317_Y + attribute \src "issuer_ls180.v:125856.18-125856.113" + wire width 3 $and$issuer_ls180.v:125856$5319_Y + attribute \src "issuer_ls180.v:125858.18-125858.127" + wire $and$issuer_ls180.v:125858$5321_Y + attribute \src "issuer_ls180.v:125859.18-125859.117" + wire $and$issuer_ls180.v:125859$5322_Y + attribute \src "issuer_ls180.v:125863.18-125863.117" + wire $and$issuer_ls180.v:125863$5326_Y + attribute \src "issuer_ls180.v:125865.18-125865.117" + wire $and$issuer_ls180.v:125865$5328_Y + attribute \src "issuer_ls180.v:125866.18-125866.124" + wire $and$issuer_ls180.v:125866$5329_Y + attribute \src "issuer_ls180.v:125867.18-125867.118" + wire $and$issuer_ls180.v:125867$5330_Y + attribute \src "issuer_ls180.v:125789.19-125789.127" + wire $eq$issuer_ls180.v:125789$5249_Y + attribute \src "issuer_ls180.v:125808.19-125808.127" + wire $eq$issuer_ls180.v:125808$5268_Y + attribute \src "issuer_ls180.v:125810.18-125810.127" + wire $eq$issuer_ls180.v:125810$5270_Y + attribute \src "issuer_ls180.v:125811.19-125811.127" + wire $eq$issuer_ls180.v:125811$5271_Y + attribute \src "issuer_ls180.v:125820.19-125820.126" + wire $eq$issuer_ls180.v:125820$5282_Y + attribute \src "issuer_ls180.v:125821.18-125821.127" + wire $eq$issuer_ls180.v:125821$5283_Y + attribute \src "issuer_ls180.v:125833.18-125833.126" + wire $eq$issuer_ls180.v:125833$5296_Y + attribute \src "issuer_ls180.v:125838.18-125838.126" + wire $eq$issuer_ls180.v:125838$5301_Y + attribute \src "issuer_ls180.v:125815.19-125815.110" + wire width 96 $extend$issuer_ls180.v:125815$5275_Y + attribute \src "issuer_ls180.v:125817.19-125817.116" + wire width 64 $extend$issuer_ls180.v:125817$5278_Y + attribute \src "issuer_ls180.v:125822.19-125822.102" + wire width 64 $extend$issuer_ls180.v:125822$5284_Y + attribute \src "issuer_ls180.v:125801.19-125801.109" + wire $not$issuer_ls180.v:125801$5261_Y + attribute \src "issuer_ls180.v:125805.19-125805.121" + wire $not$issuer_ls180.v:125805$5265_Y + attribute \src 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"/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:272" + wire \ld_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:280" + wire width 64 \ldd_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:384" + wire width 64 \ldd_r + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:11" + wire width 64 \lddata_r + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + wire width 64 \ldo_r + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" + wire width 64 \ldo_r$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:110" + wire input 40 \ldst_port0_addr_exc_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 96 output 38 \ldst_port0_addr_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 96 \ldst_port0_addr_i$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 39 \ldst_port0_addr_i_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \ldst_port0_addr_i_ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:109" + wire input 41 \ldst_port0_addr_ok_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:105" + wire input 34 \ldst_port0_busy_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:102" + wire width 4 output 37 \ldst_port0_data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:98" + wire output 35 \ldst_port0_is_ld_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:99" + wire output 36 \ldst_port0_is_st_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 input 42 \ldst_port0_ld_data_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire input 43 \ldst_port0_ld_data_o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 output 44 \ldst_port0_st_data_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 45 \ldst_port0_st_data_i_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:113" + wire \load_mem_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + wire \lod_l_qn_lod + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire \lod_l_r_lod + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire \lod_l_s_lod + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire \lsd_l_q_lsd + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire \lsd_l_r_lsd + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire \lsd_l_r_lsd$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire \lsd_l_s_lsd + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 output 31 \o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:265" + wire \op_is_ld + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:266" + wire \op_is_st + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire \opc_l_q_opc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire \opc_l_r_opc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire \opc_l_r_opc$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire \opc_l_s_opc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire \opc_l_s_opc$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 17 \oper_i_ldst_ldst0__byte_reverse + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 input 16 \oper_i_ldst_ldst0__data_len + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 input 6 \oper_i_ldst_ldst0__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 input 7 \oper_i_ldst_ldst0__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 8 \oper_i_ldst_ldst0__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 20 \oper_i_ldst_ldst0__insn + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute 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"LDSTMode" + attribute \enum_value_00 "NONE" + attribute \enum_value_01 "update" + attribute \enum_value_10 "cix" + attribute \enum_value_11 "cx" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 input 19 \oper_i_ldst_ldst0__ldst_mode + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 12 \oper_i_ldst_ldst0__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 13 \oper_i_ldst_ldst0__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 11 \oper_i_ldst_ldst0__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 10 \oper_i_ldst_ldst0__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 18 \oper_i_ldst_ldst0__sign_extend + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire 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attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute 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2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \oper_r__ldst_mode + connect \B 2'01 + connect \Y $eq$issuer_ls180.v:125789$5249_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:309" + cell $eq $eq$issuer_ls180.v:125808$5268 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \oper_r__ldst_mode + connect \B 2'01 + connect \Y $eq$issuer_ls180.v:125808$5268_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:307" + cell $eq $eq$issuer_ls180.v:125810$5270 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \oper_r__insn_type + connect \B 7'0100110 + connect \Y $eq$issuer_ls180.v:125810$5270_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:309" + cell $eq $eq$issuer_ls180.v:125811$5271 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \oper_r__ldst_mode + connect \B 2'01 + connect \Y $eq$issuer_ls180.v:125811$5271_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:510" + cell $eq $eq$issuer_ls180.v:125820$5282 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \oper_r__data_len + connect \B 2'10 + connect \Y $eq$issuer_ls180.v:125820$5282_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:308" + cell $eq $eq$issuer_ls180.v:125821$5283 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \oper_r__insn_type + connect \B 7'0100101 + connect \Y $eq$issuer_ls180.v:125821$5283_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:309" + cell $eq $eq$issuer_ls180.v:125833$5296 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \oper_r__ldst_mode + connect \B 2'01 + connect \Y $eq$issuer_ls180.v:125833$5296_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:309" + cell $eq $eq$issuer_ls180.v:125838$5301 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \oper_r__ldst_mode + connect \B 2'01 + connect \Y $eq$issuer_ls180.v:125838$5301_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:399" + cell $pos $extend$issuer_ls180.v:125815$5275 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 96 + connect \A \addr_r + connect \Y $extend$issuer_ls180.v:125815$5275_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:28" + cell $pos $extend$issuer_ls180.v:125817$5278 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 64 + connect \A \ldst_port0_ld_data_o [7:0] + connect \Y $extend$issuer_ls180.v:125817$5278_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:28" + cell $pos $extend$issuer_ls180.v:125822$5284 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 64 + connect \A \src_r2 [7:0] + connect \Y $extend$issuer_ls180.v:125822$5284_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:461" + cell $not $not$issuer_ls180.v:125801$5261 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$140 + connect \Y $not$issuer_ls180.v:125801$5261_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:464" + cell $not $not$issuer_ls180.v:125805$5265 + parameter \A_SIGNED 0 + parameter \A_WIDTH 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"/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:356" + cell $not $not$issuer_ls180.v:125837$5300 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \ldst_port0_busy_o + connect \Y $not$issuer_ls180.v:125837$5300_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:427" + cell $not $not$issuer_ls180.v:125853$5316 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 2 + connect \A { \oper_r__imm_data__ok \oper_r__zero_a } + connect \Y $not$issuer_ls180.v:125853$5316_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:427" + cell $not $not$issuer_ls180.v:125855$5318 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \cu_rdmaskn_i + connect \Y $not$issuer_ls180.v:125855$5318_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:433" + cell $not $not$issuer_ls180.v:125862$5325 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$86 + connect \Y $not$issuer_ls180.v:125862$5325_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:439" + cell $not $not$issuer_ls180.v:125864$5327 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cu_rd__rel_o [2] + connect \Y $not$issuer_ls180.v:125864$5327_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:298" + cell $or $or$issuer_ls180.v:125777$5237 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cu_st__go_i + connect \B \cu_go_die_i + connect \Y $or$issuer_ls180.v:125777$5237_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:299" + cell $or $or$issuer_ls180.v:125788$5248 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \cu_rd__go_i + connect \B { \cu_go_die_i \cu_go_die_i \cu_go_die_i } + connect \Y $or$issuer_ls180.v:125788$5248_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:458" + cell $or $or$issuer_ls180.v:125793$5253 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cu_st__go_i + connect \B \p_st_go + connect \Y $or$issuer_ls180.v:125793$5253_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:458" + cell $or $or$issuer_ls180.v:125794$5254 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$127 + connect \B \cu_wr__go_i [0] + connect \Y $or$issuer_ls180.v:125794$5254_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:458" + cell $or $or$issuer_ls180.v:125795$5255 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$129 + connect \B \cu_wr__go_i [1] + connect \Y $or$issuer_ls180.v:125795$5255_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:461" + cell $or $or$issuer_ls180.v:125798$5258 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cu_st__rel_o + connect \B \cu_wr__rel_o [0] + connect \Y $or$issuer_ls180.v:125798$5258_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:300" + cell $or $or$issuer_ls180.v:125799$5259 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cu_ad__go_i + connect \B \cu_go_die_i + connect \Y $or$issuer_ls180.v:125799$5259_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:461" + cell $or $or$issuer_ls180.v:125800$5260 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$138 + connect \B \cu_wr__rel_o [1] + connect \Y $or$issuer_ls180.v:125800$5260_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:462" + cell $or $or$issuer_ls180.v:125803$5263 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \lod_l_qn_lod + connect \B \op_is_st + connect \Y $or$issuer_ls180.v:125803$5263_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:464" + cell $or $or$issuer_ls180.v:125806$5266 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$149 + connect \B \op_is_ld + connect \Y $or$issuer_ls180.v:125806$5266_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:294" + cell $or $or$issuer_ls180.v:125825$5288 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cu_issue_i + connect \B \cu_go_die_i + connect \Y $or$issuer_ls180.v:125825$5288_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:356" + cell $or $or$issuer_ls180.v:125835$5298 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_reset + connect \B \$36 + connect \Y $or$issuer_ls180.v:125835$5298_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:295" + cell $or $or$issuer_ls180.v:125836$5299 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cu_done_o + connect \B \cu_go_die_i + connect \Y $or$issuer_ls180.v:125836$5299_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:356" + cell $or $or$issuer_ls180.v:125840$5303 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_reset + connect \B \$44 + connect \Y $or$issuer_ls180.v:125840$5303_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:359" + cell $or $or$issuer_ls180.v:125841$5304 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 2 + connect \A \reset_w + connect \B { \$38 \$46 } + connect \Y $or$issuer_ls180.v:125841$5304_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:367" + cell $or $or$issuer_ls180.v:125843$5306 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \reset_s + connect \B \p_st_go + connect \Y $or$issuer_ls180.v:125843$5306_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:371" + cell $or $or$issuer_ls180.v:125844$5307 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \reset_s + connect \B \p_st_go + connect \Y $or$issuer_ls180.v:125844$5307_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:371" + cell $or $or$issuer_ls180.v:125845$5308 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$54 + connect \B \ld_ok + connect \Y $or$issuer_ls180.v:125845$5308_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:296" + cell $or $or$issuer_ls180.v:125847$5310 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cu_wr__go_i [0] + connect \B \cu_go_die_i + connect \Y $or$issuer_ls180.v:125847$5310_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:297" + cell $or $or$issuer_ls180.v:125857$5320 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cu_wr__go_i [1] + connect \B \cu_go_die_i + connect \Y $or$issuer_ls180.v:125857$5320_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:430" + cell $or $or$issuer_ls180.v:125860$5323 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cu_rd__go_i [0] + connect \B \cu_rd__go_i [1] + connect \Y $or$issuer_ls180.v:125860$5323_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:433" + cell $or $or$issuer_ls180.v:125861$5324 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cu_rd__rel_o [0] + connect \B \cu_rd__rel_o [1] + connect \Y $or$issuer_ls180.v:125861$5324_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:399" + cell $pos $pos$issuer_ls180.v:125815$5276 + parameter \A_SIGNED 0 + parameter \A_WIDTH 96 + parameter \Y_WIDTH 96 + connect \A $extend$issuer_ls180.v:125815$5275_Y + connect \Y $pos$issuer_ls180.v:125815$5276_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:28" + cell $pos $pos$issuer_ls180.v:125817$5279 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A $extend$issuer_ls180.v:125817$5278_Y + connect \Y $pos$issuer_ls180.v:125817$5279_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:28" + cell $pos $pos$issuer_ls180.v:125818$5280 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A { 48'000000000000000000000000000000000000000000000000 \ldst_port0_ld_data_o [7:0] \ldst_port0_ld_data_o [15:8] } + connect \Y $pos$issuer_ls180.v:125818$5280_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:28" + cell $pos $pos$issuer_ls180.v:125819$5281 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A { 32'00000000000000000000000000000000 \ldst_port0_ld_data_o [7:0] \ldst_port0_ld_data_o [15:8] \ldst_port0_ld_data_o [23:16] \ldst_port0_ld_data_o [31:24] } + connect \Y $pos$issuer_ls180.v:125819$5281_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:28" + cell $pos $pos$issuer_ls180.v:125822$5285 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A $extend$issuer_ls180.v:125822$5284_Y + connect \Y $pos$issuer_ls180.v:125822$5285_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:28" + cell $pos $pos$issuer_ls180.v:125823$5286 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A { 48'000000000000000000000000000000000000000000000000 \src_r2 [7:0] \src_r2 [15:8] } + connect \Y $pos$issuer_ls180.v:125823$5286_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:28" + cell $pos $pos$issuer_ls180.v:125824$5287 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A { 32'00000000000000000000000000000000 \src_r2 [7:0] \src_r2 [15:8] \src_r2 [23:16] \src_r2 [31:24] } + connect \Y $pos$issuer_ls180.v:125824$5287_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + cell $mux $ternary$issuer_ls180.v:125846$5309 + parameter \WIDTH 64 + connect \A \ldo_r + connect \B \ldd_o + connect \S \ld_ok + connect \Y $ternary$issuer_ls180.v:125846$5309_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + cell $mux $ternary$issuer_ls180.v:125848$5311 + parameter \WIDTH 64 + connect \A \ea_r + connect \B \alu_o + connect \S \alu_l_q_alu + connect \Y $ternary$issuer_ls180.v:125848$5311_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:405" + cell $mux $ternary$issuer_ls180.v:125849$5312 + parameter \WIDTH 64 + connect \A \src_r0 + connect \B 64'0000000000000000000000000000000000000000000000000000000000000000 + connect \S \oper_r__zero_a + connect \Y $ternary$issuer_ls180.v:125849$5312_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:410" + cell $mux $ternary$issuer_ls180.v:125850$5313 + parameter \WIDTH 64 + connect \A \src_r1 + connect \B \oper_r__imm_data__data + connect \S \oper_r__imm_data__ok + connect \Y $ternary$issuer_ls180.v:125850$5313_Y + end + attribute \module_not_derived 1 + attribute \src "issuer_ls180.v:125938.9-125944.4" + cell \adr_l \adr_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_adr \adr_l_q_adr + connect \r_adr \adr_l_r_adr + connect \s_adr \adr_l_s_adr + end + attribute \module_not_derived 1 + attribute \src "issuer_ls180.v:125945.15-125951.4" + cell \alu_l$125 \alu_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_alu \alu_l_q_alu + connect \r_alu \alu_l_r_alu + connect \s_alu \alu_l_s_alu + end + attribute \module_not_derived 1 + attribute \src "issuer_ls180.v:125952.9-125958.4" + cell \lod_l \lod_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \qn_lod \lod_l_qn_lod + connect \r_lod \lod_l_r_lod + connect \s_lod \lod_l_s_lod + end + attribute \module_not_derived 1 + attribute \src "issuer_ls180.v:125959.9-125965.4" + cell \lsd_l \lsd_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_lsd \lsd_l_q_lsd + connect \r_lsd \lsd_l_r_lsd + connect \s_lsd \lsd_l_s_lsd + end + attribute \module_not_derived 1 + attribute \src "issuer_ls180.v:125966.15-125972.4" + cell \opc_l$123 \opc_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_opc \opc_l_q_opc + connect \r_opc \opc_l_r_opc + connect \s_opc \opc_l_s_opc + end + attribute \module_not_derived 1 + attribute \src "issuer_ls180.v:125973.15-125979.4" + cell \rst_l$126 \rst_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_rst \rst_l_q_rst + connect \r_rst \rst_l_r_rst + connect \s_rst \rst_l_s_rst + end + attribute \module_not_derived 1 + attribute \src "issuer_ls180.v:125980.15-125986.4" + cell \src_l$124 \src_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_src \src_l_q_src + connect \r_src \src_l_r_src + connect \s_src \src_l_s_src + end + attribute \module_not_derived 1 + attribute \src "issuer_ls180.v:125987.9-125993.4" + cell \sto_l \sto_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_sto \sto_l_q_sto + connect \r_sto \sto_l_r_sto + connect \s_sto \sto_l_s_sto + end + attribute \module_not_derived 1 + attribute \src "issuer_ls180.v:125994.9-126000.4" + cell \upd_l \upd_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_upd \upd_l_q_upd + connect \r_upd \upd_l_r_upd + connect \s_upd \upd_l_s_upd + end + attribute \module_not_derived 1 + attribute \src "issuer_ls180.v:126001.9-126007.4" + cell \wri_l \wri_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_wri \wri_l_q_wri + connect \r_wri \wri_l_r_wri + connect \s_wri \wri_l_s_wri + end + attribute \src "issuer_ls180.v:125061.7-125061.20" + process $proc$issuer_ls180.v:125061$5479 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "issuer_ls180.v:125259.7-125259.25" + process $proc$issuer_ls180.v:125259$5480 + assign { } { } + assign $1\adr_l_r_adr[0:0] 1'1 + sync always + sync init + update \adr_l_r_adr $1\adr_l_r_adr[0:0] + end + attribute \src "issuer_ls180.v:125273.7-125273.20" + process $proc$issuer_ls180.v:125273$5481 + assign { } { } + assign $1\alu_ok[0:0] 1'0 + sync always + sync init + update \alu_ok $1\alu_ok[0:0] + end + attribute \src "issuer_ls180.v:125319.14-125319.41" + process $proc$issuer_ls180.v:125319$5482 + assign { } { } + assign $1\ea_r[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \ea_r $1\ea_r[63:0] + end + attribute \src "issuer_ls180.v:125333.14-125333.42" + process $proc$issuer_ls180.v:125333$5483 + assign { } { } + assign $1\ldo_r[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \ldo_r $1\ldo_r[63:0] + end + attribute \src "issuer_ls180.v:125340.14-125340.62" + process $proc$issuer_ls180.v:125340$5484 + assign { } { } + assign $1\ldst_port0_addr_i[95:0] 96'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \ldst_port0_addr_i $1\ldst_port0_addr_i[95:0] + end + attribute \src "issuer_ls180.v:125345.7-125345.34" + process $proc$issuer_ls180.v:125345$5485 + assign { } { } + assign $1\ldst_port0_addr_i_ok[0:0] 1'0 + sync always + sync init + update \ldst_port0_addr_i_ok $1\ldst_port0_addr_i_ok[0:0] + end + attribute \src "issuer_ls180.v:125378.7-125378.25" + process $proc$issuer_ls180.v:125378$5486 + assign { } { } + assign $1\lsd_l_r_lsd[0:0] 1'1 + sync always + sync init + update \lsd_l_r_lsd $1\lsd_l_r_lsd[0:0] + end + attribute \src "issuer_ls180.v:125392.7-125392.25" + process $proc$issuer_ls180.v:125392$5487 + assign { } { } + assign $1\opc_l_r_opc[0:0] 1'1 + sync always + sync init + update \opc_l_r_opc $1\opc_l_r_opc[0:0] + end + attribute \src "issuer_ls180.v:125396.7-125396.25" + process $proc$issuer_ls180.v:125396$5488 + assign { } { } + assign $1\opc_l_s_opc[0:0] 1'0 + sync always + sync init + update \opc_l_s_opc $1\opc_l_s_opc[0:0] + end + attribute \src "issuer_ls180.v:125524.7-125524.34" + process $proc$issuer_ls180.v:125524$5489 + assign { } { } + assign $1\oper_r__byte_reverse[0:0] 1'0 + sync always + sync init + update \oper_r__byte_reverse $1\oper_r__byte_reverse[0:0] + end + attribute \src "issuer_ls180.v:125528.13-125528.36" + process $proc$issuer_ls180.v:125528$5490 + assign { } { } + assign $1\oper_r__data_len[3:0] 4'0000 + sync always + sync init + update \oper_r__data_len $1\oper_r__data_len[3:0] + end + attribute \src "issuer_ls180.v:125545.14-125545.39" + process $proc$issuer_ls180.v:125545$5491 + assign { } { } + assign $1\oper_r__fn_unit[11:0] 12'000000000000 + sync always + sync init + update \oper_r__fn_unit $1\oper_r__fn_unit[11:0] + end + attribute \src "issuer_ls180.v:125549.14-125549.59" + process $proc$issuer_ls180.v:125549$5492 + assign { } { } + assign $1\oper_r__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \oper_r__imm_data__data $1\oper_r__imm_data__data[63:0] + end + attribute \src "issuer_ls180.v:125553.7-125553.34" + process $proc$issuer_ls180.v:125553$5493 + assign { } { } + assign $1\oper_r__imm_data__ok[0:0] 1'0 + sync always + sync init + update \oper_r__imm_data__ok $1\oper_r__imm_data__ok[0:0] + end + attribute \src "issuer_ls180.v:125557.14-125557.34" + process $proc$issuer_ls180.v:125557$5494 + assign { } { } + assign $1\oper_r__insn[31:0] 0 + sync always + sync init + update \oper_r__insn $1\oper_r__insn[31:0] + end + attribute \src "issuer_ls180.v:125635.13-125635.38" + process $proc$issuer_ls180.v:125635$5495 + assign { } { } + assign $1\oper_r__insn_type[6:0] 7'0000000 + sync always + sync init + update \oper_r__insn_type $1\oper_r__insn_type[6:0] + end + attribute \src "issuer_ls180.v:125639.7-125639.30" + process $proc$issuer_ls180.v:125639$5496 + assign { } { } + assign $1\oper_r__is_32bit[0:0] 1'0 + sync always + sync init + update \oper_r__is_32bit $1\oper_r__is_32bit[0:0] + end + attribute \src "issuer_ls180.v:125643.7-125643.31" + process $proc$issuer_ls180.v:125643$5497 + assign { } { } + assign $1\oper_r__is_signed[0:0] 1'0 + sync always + sync init + update \oper_r__is_signed $1\oper_r__is_signed[0:0] + end + attribute \src "issuer_ls180.v:125652.13-125652.37" + process $proc$issuer_ls180.v:125652$5498 + assign { } { } + assign $1\oper_r__ldst_mode[1:0] 2'00 + sync always + sync init + update \oper_r__ldst_mode $1\oper_r__ldst_mode[1:0] + end + attribute \src "issuer_ls180.v:125656.7-125656.28" + process $proc$issuer_ls180.v:125656$5499 + assign { } { } + assign $1\oper_r__oe__oe[0:0] 1'0 + sync always + sync init + update \oper_r__oe__oe $1\oper_r__oe__oe[0:0] + end + attribute \src "issuer_ls180.v:125660.7-125660.28" + process $proc$issuer_ls180.v:125660$5500 + assign { } { } + assign $1\oper_r__oe__ok[0:0] 1'0 + sync always + sync init + update \oper_r__oe__ok $1\oper_r__oe__ok[0:0] + end + attribute \src "issuer_ls180.v:125664.7-125664.28" + process $proc$issuer_ls180.v:125664$5501 + assign { } { } + assign $1\oper_r__rc__ok[0:0] 1'0 + sync always + sync init + update \oper_r__rc__ok $1\oper_r__rc__ok[0:0] + end + attribute \src "issuer_ls180.v:125668.7-125668.28" + process $proc$issuer_ls180.v:125668$5502 + assign { } { } + assign $1\oper_r__rc__rc[0:0] 1'0 + sync always + sync init + update \oper_r__rc__rc $1\oper_r__rc__rc[0:0] + end + attribute \src "issuer_ls180.v:125672.7-125672.33" + process $proc$issuer_ls180.v:125672$5503 + assign { } { } + assign $1\oper_r__sign_extend[0:0] 1'0 + sync always + sync init + update \oper_r__sign_extend $1\oper_r__sign_extend[0:0] + end + attribute \src "issuer_ls180.v:125676.7-125676.28" + process $proc$issuer_ls180.v:125676$5504 + assign { } { } + assign $1\oper_r__zero_a[0:0] 1'0 + sync always + sync init + update \oper_r__zero_a $1\oper_r__zero_a[0:0] + end + attribute \src "issuer_ls180.v:125680.7-125680.21" + process $proc$issuer_ls180.v:125680$5505 + assign { } { } + assign $1\p_st_go[0:0] 1'0 + sync always + sync init + update \p_st_go $1\p_st_go[0:0] + end + attribute \src "issuer_ls180.v:125722.13-125722.31" + process $proc$issuer_ls180.v:125722$5506 + assign { } { } + assign $1\src_l_r_src[2:0] 3'111 + sync always + sync init + update \src_l_r_src $1\src_l_r_src[2:0] + end + attribute \src "issuer_ls180.v:125726.13-125726.31" + process $proc$issuer_ls180.v:125726$5507 + assign { } { } + assign $1\src_l_s_src[2:0] 3'000 + sync always + sync init + update \src_l_s_src $1\src_l_s_src[2:0] + end + attribute \src "issuer_ls180.v:125730.14-125730.43" + process $proc$issuer_ls180.v:125730$5508 + assign { } { } + assign $1\src_r0[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \src_r0 $1\src_r0[63:0] + end + attribute \src "issuer_ls180.v:125734.14-125734.43" + process $proc$issuer_ls180.v:125734$5509 + assign { } { } + assign $1\src_r1[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \src_r1 $1\src_r1[63:0] + end + attribute \src "issuer_ls180.v:125738.14-125738.43" + process $proc$issuer_ls180.v:125738$5510 + assign { } { } + assign $1\src_r2[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \src_r2 $1\src_r2[63:0] + end + attribute \src "issuer_ls180.v:125748.7-125748.25" + process $proc$issuer_ls180.v:125748$5511 + assign { } { } + assign $1\sto_l_r_sto[0:0] 1'1 + sync always + sync init + update \sto_l_r_sto $1\sto_l_r_sto[0:0] + end + attribute \src "issuer_ls180.v:125758.7-125758.25" + process $proc$issuer_ls180.v:125758$5512 + assign { } { } + assign $1\upd_l_r_upd[0:0] 1'1 + sync always + sync init + update \upd_l_r_upd $1\upd_l_r_upd[0:0] + end + attribute \src "issuer_ls180.v:125762.7-125762.25" + process $proc$issuer_ls180.v:125762$5513 + assign { } { } + assign $1\upd_l_s_upd[0:0] 1'0 + sync always + sync init + update \upd_l_s_upd $1\upd_l_s_upd[0:0] + end + attribute \src "issuer_ls180.v:125772.7-125772.25" + process $proc$issuer_ls180.v:125772$5514 + assign { } { } + assign $1\wri_l_r_wri[0:0] 1'1 + sync always + sync init + update \wri_l_r_wri $1\wri_l_r_wri[0:0] + end + attribute \src "issuer_ls180.v:125868.3-125869.57" + process $proc$issuer_ls180.v:125868$5331 + assign { } { } + assign $0\ldst_port0_addr_i_ok[0:0] \ldst_port0_addr_i_ok$next + sync posedge \coresync_clk + update \ldst_port0_addr_i_ok $0\ldst_port0_addr_i_ok[0:0] + end + attribute \src "issuer_ls180.v:125870.3-125871.33" + process $proc$issuer_ls180.v:125870$5332 + assign { } { } + assign $0\ldst_port0_addr_i[95:0] \$168 + sync posedge \coresync_clk + update \ldst_port0_addr_i $0\ldst_port0_addr_i[95:0] + end + attribute \src "issuer_ls180.v:125872.3-125873.21" + process $proc$issuer_ls180.v:125872$5333 + assign { } { } + assign $0\alu_ok[0:0] \$89 + sync posedge \coresync_clk + update \alu_ok $0\alu_ok[0:0] + end + attribute \src "issuer_ls180.v:125874.3-125875.25" + process $proc$issuer_ls180.v:125874$5334 + assign { } { } + assign $0\ea_r[63:0] \ea_r$next + sync posedge \coresync_clk + update \ea_r $0\ea_r[63:0] + end + attribute \src "issuer_ls180.v:125876.3-125877.29" + process $proc$issuer_ls180.v:125876$5335 + assign { } { } + assign $0\src_r2[63:0] \src_r2$next + sync posedge \coresync_clk + update \src_r2 $0\src_r2[63:0] + end + attribute \src "issuer_ls180.v:125878.3-125879.29" + process $proc$issuer_ls180.v:125878$5336 + assign { } { } + assign $0\src_r1[63:0] \src_r1$next + sync posedge \coresync_clk + update \src_r1 $0\src_r1[63:0] + end + attribute \src "issuer_ls180.v:125880.3-125881.29" + process $proc$issuer_ls180.v:125880$5337 + assign { } { } + assign $0\src_r0[63:0] \src_r0$next + sync posedge \coresync_clk + update \src_r0 $0\src_r0[63:0] + end + attribute \src "issuer_ls180.v:125882.3-125883.27" + process $proc$issuer_ls180.v:125882$5338 + assign { } { } + assign $0\ldo_r[63:0] \ldo_r$next + sync posedge \coresync_clk + update \ldo_r $0\ldo_r[63:0] + end + attribute \src "issuer_ls180.v:125884.3-125885.51" + process $proc$issuer_ls180.v:125884$5339 + assign { } { } + assign $0\oper_r__insn_type[6:0] \oper_r__insn_type$next + sync posedge \coresync_clk + update \oper_r__insn_type $0\oper_r__insn_type[6:0] + end + attribute \src "issuer_ls180.v:125886.3-125887.47" + process $proc$issuer_ls180.v:125886$5340 + assign { } { } + assign $0\oper_r__fn_unit[11:0] \oper_r__fn_unit$next + sync posedge \coresync_clk + update \oper_r__fn_unit $0\oper_r__fn_unit[11:0] + end + attribute \src "issuer_ls180.v:125888.3-125889.61" + process $proc$issuer_ls180.v:125888$5341 + assign { } { } + assign $0\oper_r__imm_data__data[63:0] \oper_r__imm_data__data$next + sync posedge \coresync_clk + update \oper_r__imm_data__data $0\oper_r__imm_data__data[63:0] + end + attribute \src "issuer_ls180.v:125890.3-125891.57" + process $proc$issuer_ls180.v:125890$5342 + assign { } { } + assign $0\oper_r__imm_data__ok[0:0] \oper_r__imm_data__ok$next + sync posedge \coresync_clk + update \oper_r__imm_data__ok $0\oper_r__imm_data__ok[0:0] + end + attribute \src "issuer_ls180.v:125892.3-125893.45" + process $proc$issuer_ls180.v:125892$5343 + assign { } { } + assign $0\oper_r__zero_a[0:0] \oper_r__zero_a$next + sync posedge \coresync_clk + update \oper_r__zero_a $0\oper_r__zero_a[0:0] + end + attribute \src "issuer_ls180.v:125894.3-125895.45" + process $proc$issuer_ls180.v:125894$5344 + assign { } { } + assign $0\oper_r__rc__rc[0:0] \oper_r__rc__rc$next + sync posedge \coresync_clk + update \oper_r__rc__rc $0\oper_r__rc__rc[0:0] + end + attribute \src "issuer_ls180.v:125896.3-125897.45" + process $proc$issuer_ls180.v:125896$5345 + assign { } { } + assign $0\oper_r__rc__ok[0:0] \oper_r__rc__ok$next + sync posedge \coresync_clk + update \oper_r__rc__ok $0\oper_r__rc__ok[0:0] + end + attribute \src "issuer_ls180.v:125898.3-125899.45" + process $proc$issuer_ls180.v:125898$5346 + assign { } { } + assign $0\oper_r__oe__oe[0:0] \oper_r__oe__oe$next + sync posedge \coresync_clk + update \oper_r__oe__oe $0\oper_r__oe__oe[0:0] + end + attribute \src "issuer_ls180.v:125900.3-125901.45" + process $proc$issuer_ls180.v:125900$5347 + assign { } { } + assign $0\oper_r__oe__ok[0:0] \oper_r__oe__ok$next + sync posedge \coresync_clk + update \oper_r__oe__ok $0\oper_r__oe__ok[0:0] + end + attribute \src "issuer_ls180.v:125902.3-125903.49" + process $proc$issuer_ls180.v:125902$5348 + assign { } { } + assign $0\oper_r__is_32bit[0:0] \oper_r__is_32bit$next + sync posedge \coresync_clk + update \oper_r__is_32bit $0\oper_r__is_32bit[0:0] + end + attribute \src "issuer_ls180.v:125904.3-125905.51" + process $proc$issuer_ls180.v:125904$5349 + assign { } { } + assign $0\oper_r__is_signed[0:0] \oper_r__is_signed$next + sync posedge \coresync_clk + update \oper_r__is_signed $0\oper_r__is_signed[0:0] + end + attribute \src "issuer_ls180.v:125906.3-125907.49" + process $proc$issuer_ls180.v:125906$5350 + assign { } { } + assign $0\oper_r__data_len[3:0] \oper_r__data_len$next + sync posedge \coresync_clk + update \oper_r__data_len $0\oper_r__data_len[3:0] + end + attribute \src "issuer_ls180.v:125908.3-125909.57" + process $proc$issuer_ls180.v:125908$5351 + assign { } { } + assign $0\oper_r__byte_reverse[0:0] \oper_r__byte_reverse$next + sync posedge \coresync_clk + update \oper_r__byte_reverse $0\oper_r__byte_reverse[0:0] + end + attribute \src "issuer_ls180.v:125910.3-125911.55" + process $proc$issuer_ls180.v:125910$5352 + assign { } { } + assign $0\oper_r__sign_extend[0:0] \oper_r__sign_extend$next + sync posedge \coresync_clk + update \oper_r__sign_extend $0\oper_r__sign_extend[0:0] + end + attribute \src "issuer_ls180.v:125912.3-125913.51" + process $proc$issuer_ls180.v:125912$5353 + assign { } { } + assign $0\oper_r__ldst_mode[1:0] \oper_r__ldst_mode$next + sync posedge \coresync_clk + update \oper_r__ldst_mode $0\oper_r__ldst_mode[1:0] + end + attribute \src "issuer_ls180.v:125914.3-125915.41" + process $proc$issuer_ls180.v:125914$5354 + assign { } { } + assign $0\oper_r__insn[31:0] \oper_r__insn$next + sync posedge \coresync_clk + update \oper_r__insn $0\oper_r__insn[31:0] + end + attribute \src "issuer_ls180.v:125916.3-125917.39" + process $proc$issuer_ls180.v:125916$5355 + assign { } { } + assign $0\lsd_l_r_lsd[0:0] \lsd_l_r_lsd$next + sync posedge \coresync_clk + update \lsd_l_r_lsd $0\lsd_l_r_lsd[0:0] + end + attribute \src "issuer_ls180.v:125918.3-125919.39" + process $proc$issuer_ls180.v:125918$5356 + assign { } { } + assign $0\sto_l_r_sto[0:0] \sto_l_r_sto$next + sync posedge \coresync_clk + update \sto_l_r_sto $0\sto_l_r_sto[0:0] + end + attribute \src "issuer_ls180.v:125920.3-125921.39" + process $proc$issuer_ls180.v:125920$5357 + assign { } { } + assign $0\upd_l_r_upd[0:0] \upd_l_r_upd$next + sync posedge \coresync_clk + update \upd_l_r_upd $0\upd_l_r_upd[0:0] + end + attribute \src "issuer_ls180.v:125922.3-125923.39" + process $proc$issuer_ls180.v:125922$5358 + assign { } { } + assign $0\upd_l_s_upd[0:0] \upd_l_s_upd$next + sync posedge \coresync_clk + update \upd_l_s_upd $0\upd_l_s_upd[0:0] + end + attribute \src "issuer_ls180.v:125924.3-125925.39" + process $proc$issuer_ls180.v:125924$5359 + assign { } { } + assign $0\wri_l_r_wri[0:0] \wri_l_r_wri$next + sync posedge \coresync_clk + update \wri_l_r_wri $0\wri_l_r_wri[0:0] + end + attribute \src "issuer_ls180.v:125926.3-125927.39" + process $proc$issuer_ls180.v:125926$5360 + assign { } { } + assign $0\adr_l_r_adr[0:0] \adr_l_r_adr$next + sync posedge \coresync_clk + update \adr_l_r_adr $0\adr_l_r_adr[0:0] + end + attribute \src "issuer_ls180.v:125928.3-125929.39" + process $proc$issuer_ls180.v:125928$5361 + assign { } { } + assign $0\src_l_r_src[2:0] \src_l_r_src$next + sync posedge \coresync_clk + update \src_l_r_src $0\src_l_r_src[2:0] + end + attribute \src "issuer_ls180.v:125930.3-125931.39" + process $proc$issuer_ls180.v:125930$5362 + assign { } { } + assign $0\src_l_s_src[2:0] \src_l_s_src$next + sync posedge \coresync_clk + update \src_l_s_src $0\src_l_s_src[2:0] + end + attribute \src "issuer_ls180.v:125932.3-125933.39" + process $proc$issuer_ls180.v:125932$5363 + assign { } { } + assign $0\opc_l_r_opc[0:0] \opc_l_r_opc$next + sync posedge \coresync_clk + update \opc_l_r_opc $0\opc_l_r_opc[0:0] + end + attribute \src "issuer_ls180.v:125934.3-125935.39" + process $proc$issuer_ls180.v:125934$5364 + assign { } { } + assign $0\opc_l_s_opc[0:0] \opc_l_s_opc$next + sync posedge \coresync_clk + update \opc_l_s_opc $0\opc_l_s_opc[0:0] + end + attribute \src "issuer_ls180.v:125936.3-125937.28" + process $proc$issuer_ls180.v:125936$5365 + assign { } { } + assign $0\p_st_go[0:0] \cu_st__go_i + sync posedge \coresync_clk + update \p_st_go $0\p_st_go[0:0] + end + attribute \src "issuer_ls180.v:126008.3-126016.6" + process $proc$issuer_ls180.v:126008$5366 + assign { } { } + assign { } { } + assign $0\opc_l_s_opc$next[0:0]$5367 $1\opc_l_s_opc$next[0:0]$5368 + attribute \src "issuer_ls180.v:126009.5-126009.29" + switch \initial + attribute \src "issuer_ls180.v:126009.9-126009.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\opc_l_s_opc$next[0:0]$5368 1'0 + case + assign $1\opc_l_s_opc$next[0:0]$5368 \cu_issue_i + end + sync always + update \opc_l_s_opc$next $0\opc_l_s_opc$next[0:0]$5367 + end + attribute \src "issuer_ls180.v:126017.3-126025.6" + process $proc$issuer_ls180.v:126017$5369 + assign { } { } + assign { } { } + assign $0\opc_l_r_opc$next[0:0]$5370 $1\opc_l_r_opc$next[0:0]$5371 + attribute \src "issuer_ls180.v:126018.5-126018.29" + switch \initial + attribute \src "issuer_ls180.v:126018.9-126018.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\opc_l_r_opc$next[0:0]$5371 1'1 + case + assign $1\opc_l_r_opc$next[0:0]$5371 \reset_o + end + sync always + update \opc_l_r_opc$next $0\opc_l_r_opc$next[0:0]$5370 + end + attribute \src "issuer_ls180.v:126026.3-126034.6" + process $proc$issuer_ls180.v:126026$5372 + assign { } { } + assign { } { } + assign $0\src_l_s_src$next[2:0]$5373 $1\src_l_s_src$next[2:0]$5374 + attribute \src "issuer_ls180.v:126027.5-126027.29" + switch \initial + attribute \src "issuer_ls180.v:126027.9-126027.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\src_l_s_src$next[2:0]$5374 3'000 + case + assign $1\src_l_s_src$next[2:0]$5374 { \cu_issue_i \cu_issue_i \cu_issue_i } + end + sync always + update \src_l_s_src$next $0\src_l_s_src$next[2:0]$5373 + end + attribute \src "issuer_ls180.v:126035.3-126043.6" + process $proc$issuer_ls180.v:126035$5375 + assign { } { } + assign { } { } + assign $0\src_l_r_src$next[2:0]$5376 $1\src_l_r_src$next[2:0]$5377 + attribute \src "issuer_ls180.v:126036.5-126036.29" + switch \initial + attribute \src "issuer_ls180.v:126036.9-126036.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\src_l_r_src$next[2:0]$5377 3'111 + case + assign $1\src_l_r_src$next[2:0]$5377 \reset_r + end + sync always + update \src_l_r_src$next $0\src_l_r_src$next[2:0]$5376 + end + attribute \src "issuer_ls180.v:126044.3-126052.6" + process $proc$issuer_ls180.v:126044$5378 + assign { } { } + assign { } { } + assign $0\adr_l_r_adr$next[0:0]$5379 $1\adr_l_r_adr$next[0:0]$5380 + attribute \src "issuer_ls180.v:126045.5-126045.29" + switch \initial + attribute \src "issuer_ls180.v:126045.9-126045.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\adr_l_r_adr$next[0:0]$5380 1'1 + case + assign $1\adr_l_r_adr$next[0:0]$5380 \reset_a + end + sync always + update \adr_l_r_adr$next $0\adr_l_r_adr$next[0:0]$5379 + end + attribute \src "issuer_ls180.v:126053.3-126061.6" + process $proc$issuer_ls180.v:126053$5381 + assign { } { } + assign { } { } + assign $0\wri_l_r_wri$next[0:0]$5382 $1\wri_l_r_wri$next[0:0]$5383 + attribute \src "issuer_ls180.v:126054.5-126054.29" + switch \initial + attribute \src "issuer_ls180.v:126054.9-126054.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\wri_l_r_wri$next[0:0]$5383 1'1 + case + assign $1\wri_l_r_wri$next[0:0]$5383 \$31 [0] + end + sync always + update \wri_l_r_wri$next $0\wri_l_r_wri$next[0:0]$5382 + end + attribute \src "issuer_ls180.v:126062.3-126070.6" + process $proc$issuer_ls180.v:126062$5384 + assign { } { } + assign { } { } + assign $0\upd_l_s_upd$next[0:0]$5385 $1\upd_l_s_upd$next[0:0]$5386 + attribute \src "issuer_ls180.v:126063.5-126063.29" + switch \initial + attribute \src "issuer_ls180.v:126063.9-126063.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\upd_l_s_upd$next[0:0]$5386 1'0 + case + assign $1\upd_l_s_upd$next[0:0]$5386 \reset_i + end + sync always + update \upd_l_s_upd$next $0\upd_l_s_upd$next[0:0]$5385 + end + attribute \src "issuer_ls180.v:126071.3-126079.6" + process $proc$issuer_ls180.v:126071$5387 + assign { } { } + assign { } { } + assign $0\upd_l_r_upd$next[0:0]$5388 $1\upd_l_r_upd$next[0:0]$5389 + attribute \src "issuer_ls180.v:126072.5-126072.29" + switch \initial + attribute \src "issuer_ls180.v:126072.9-126072.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\upd_l_r_upd$next[0:0]$5389 1'1 + case + assign $1\upd_l_r_upd$next[0:0]$5389 \reset_u + end + sync always + update \upd_l_r_upd$next $0\upd_l_r_upd$next[0:0]$5388 + end + attribute \src "issuer_ls180.v:126080.3-126088.6" + process $proc$issuer_ls180.v:126080$5390 + assign { } { } + assign { } { } + assign $0\sto_l_r_sto$next[0:0]$5391 $1\sto_l_r_sto$next[0:0]$5392 + attribute \src "issuer_ls180.v:126081.5-126081.29" + switch \initial + attribute \src "issuer_ls180.v:126081.9-126081.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\sto_l_r_sto$next[0:0]$5392 1'1 + case + assign $1\sto_l_r_sto$next[0:0]$5392 \$52 + end + sync always + update \sto_l_r_sto$next $0\sto_l_r_sto$next[0:0]$5391 + end + attribute \src "issuer_ls180.v:126089.3-126097.6" + process $proc$issuer_ls180.v:126089$5393 + assign { } { } + assign { } { } + assign $0\lsd_l_r_lsd$next[0:0]$5394 $1\lsd_l_r_lsd$next[0:0]$5395 + attribute \src "issuer_ls180.v:126090.5-126090.29" + switch \initial + attribute \src "issuer_ls180.v:126090.9-126090.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\lsd_l_r_lsd$next[0:0]$5395 1'1 + case + assign $1\lsd_l_r_lsd$next[0:0]$5395 \$56 + end + sync always + update \lsd_l_r_lsd$next $0\lsd_l_r_lsd$next[0:0]$5394 + end + attribute \src "issuer_ls180.v:126098.3-126140.6" + process $proc$issuer_ls180.v:126098$5396 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\oper_r__byte_reverse$next[0:0]$5397 $2\oper_r__byte_reverse$next[0:0]$5429 + assign $0\oper_r__data_len$next[3:0]$5398 $2\oper_r__data_len$next[3:0]$5430 + assign $0\oper_r__fn_unit$next[11:0]$5399 $2\oper_r__fn_unit$next[11:0]$5431 + assign { } { } + assign { } { } + assign $0\oper_r__insn$next[31:0]$5402 $2\oper_r__insn$next[31:0]$5434 + assign $0\oper_r__insn_type$next[6:0]$5403 $2\oper_r__insn_type$next[6:0]$5435 + assign $0\oper_r__is_32bit$next[0:0]$5404 $2\oper_r__is_32bit$next[0:0]$5436 + assign $0\oper_r__is_signed$next[0:0]$5405 $2\oper_r__is_signed$next[0:0]$5437 + assign $0\oper_r__ldst_mode$next[1:0]$5406 $2\oper_r__ldst_mode$next[1:0]$5438 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\oper_r__sign_extend$next[0:0]$5411 $2\oper_r__sign_extend$next[0:0]$5443 + assign $0\oper_r__zero_a$next[0:0]$5412 $2\oper_r__zero_a$next[0:0]$5444 + assign $0\oper_r__imm_data__data$next[63:0]$5400 $3\oper_r__imm_data__data$next[63:0]$5445 + assign $0\oper_r__imm_data__ok$next[0:0]$5401 $3\oper_r__imm_data__ok$next[0:0]$5446 + assign $0\oper_r__oe__oe$next[0:0]$5407 $3\oper_r__oe__oe$next[0:0]$5447 + assign $0\oper_r__oe__ok$next[0:0]$5408 $3\oper_r__oe__ok$next[0:0]$5448 + assign $0\oper_r__rc__ok$next[0:0]$5409 $3\oper_r__rc__ok$next[0:0]$5449 + assign $0\oper_r__rc__rc$next[0:0]$5410 $3\oper_r__rc__rc$next[0:0]$5450 + attribute \src "issuer_ls180.v:126099.5-126099.29" + switch \initial + attribute \src "issuer_ls180.v:126099.9-126099.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:378" + switch \cu_issue_i + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { $1\oper_r__insn$next[31:0]$5418 $1\oper_r__ldst_mode$next[1:0]$5422 $1\oper_r__sign_extend$next[0:0]$5427 $1\oper_r__byte_reverse$next[0:0]$5413 $1\oper_r__data_len$next[3:0]$5414 $1\oper_r__is_signed$next[0:0]$5421 $1\oper_r__is_32bit$next[0:0]$5420 $1\oper_r__oe__ok$next[0:0]$5424 $1\oper_r__oe__oe$next[0:0]$5423 $1\oper_r__rc__ok$next[0:0]$5425 $1\oper_r__rc__rc$next[0:0]$5426 $1\oper_r__zero_a$next[0:0]$5428 $1\oper_r__imm_data__ok$next[0:0]$5417 $1\oper_r__imm_data__data$next[63:0]$5416 $1\oper_r__fn_unit$next[11:0]$5415 $1\oper_r__insn_type$next[6:0]$5419 } { \oper_i_ldst_ldst0__insn \oper_i_ldst_ldst0__ldst_mode \oper_i_ldst_ldst0__sign_extend \oper_i_ldst_ldst0__byte_reverse \oper_i_ldst_ldst0__data_len \oper_i_ldst_ldst0__is_signed \oper_i_ldst_ldst0__is_32bit \oper_i_ldst_ldst0__oe__ok \oper_i_ldst_ldst0__oe__oe \oper_i_ldst_ldst0__rc__ok \oper_i_ldst_ldst0__rc__rc \oper_i_ldst_ldst0__zero_a \oper_i_ldst_ldst0__imm_data__ok \oper_i_ldst_ldst0__imm_data__data \oper_i_ldst_ldst0__fn_unit \oper_i_ldst_ldst0__insn_type } + case + assign $1\oper_r__byte_reverse$next[0:0]$5413 \oper_r__byte_reverse + assign $1\oper_r__data_len$next[3:0]$5414 \oper_r__data_len + assign $1\oper_r__fn_unit$next[11:0]$5415 \oper_r__fn_unit + assign $1\oper_r__imm_data__data$next[63:0]$5416 \oper_r__imm_data__data + assign $1\oper_r__imm_data__ok$next[0:0]$5417 \oper_r__imm_data__ok + assign $1\oper_r__insn$next[31:0]$5418 \oper_r__insn + assign $1\oper_r__insn_type$next[6:0]$5419 \oper_r__insn_type + assign $1\oper_r__is_32bit$next[0:0]$5420 \oper_r__is_32bit + assign $1\oper_r__is_signed$next[0:0]$5421 \oper_r__is_signed + assign $1\oper_r__ldst_mode$next[1:0]$5422 \oper_r__ldst_mode + assign $1\oper_r__oe__oe$next[0:0]$5423 \oper_r__oe__oe + assign $1\oper_r__oe__ok$next[0:0]$5424 \oper_r__oe__ok + assign $1\oper_r__rc__ok$next[0:0]$5425 \oper_r__rc__ok + assign $1\oper_r__rc__rc$next[0:0]$5426 \oper_r__rc__rc + assign $1\oper_r__sign_extend$next[0:0]$5427 \oper_r__sign_extend + assign $1\oper_r__zero_a$next[0:0]$5428 \oper_r__zero_a + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:380" + switch \cu_done_o + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { $2\oper_r__insn$next[31:0]$5434 $2\oper_r__ldst_mode$next[1:0]$5438 $2\oper_r__sign_extend$next[0:0]$5443 $2\oper_r__byte_reverse$next[0:0]$5429 $2\oper_r__data_len$next[3:0]$5430 $2\oper_r__is_signed$next[0:0]$5437 $2\oper_r__is_32bit$next[0:0]$5436 $2\oper_r__oe__ok$next[0:0]$5440 $2\oper_r__oe__oe$next[0:0]$5439 $2\oper_r__rc__ok$next[0:0]$5441 $2\oper_r__rc__rc$next[0:0]$5442 $2\oper_r__zero_a$next[0:0]$5444 $2\oper_r__imm_data__ok$next[0:0]$5433 $2\oper_r__imm_data__data$next[63:0]$5432 $2\oper_r__fn_unit$next[11:0]$5431 $2\oper_r__insn_type$next[6:0]$5435 } 131'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + case + assign $2\oper_r__byte_reverse$next[0:0]$5429 $1\oper_r__byte_reverse$next[0:0]$5413 + assign $2\oper_r__data_len$next[3:0]$5430 $1\oper_r__data_len$next[3:0]$5414 + assign $2\oper_r__fn_unit$next[11:0]$5431 $1\oper_r__fn_unit$next[11:0]$5415 + assign $2\oper_r__imm_data__data$next[63:0]$5432 $1\oper_r__imm_data__data$next[63:0]$5416 + assign $2\oper_r__imm_data__ok$next[0:0]$5433 $1\oper_r__imm_data__ok$next[0:0]$5417 + assign $2\oper_r__insn$next[31:0]$5434 $1\oper_r__insn$next[31:0]$5418 + assign $2\oper_r__insn_type$next[6:0]$5435 $1\oper_r__insn_type$next[6:0]$5419 + assign $2\oper_r__is_32bit$next[0:0]$5436 $1\oper_r__is_32bit$next[0:0]$5420 + assign $2\oper_r__is_signed$next[0:0]$5437 $1\oper_r__is_signed$next[0:0]$5421 + assign $2\oper_r__ldst_mode$next[1:0]$5438 $1\oper_r__ldst_mode$next[1:0]$5422 + assign $2\oper_r__oe__oe$next[0:0]$5439 $1\oper_r__oe__oe$next[0:0]$5423 + assign $2\oper_r__oe__ok$next[0:0]$5440 $1\oper_r__oe__ok$next[0:0]$5424 + assign $2\oper_r__rc__ok$next[0:0]$5441 $1\oper_r__rc__ok$next[0:0]$5425 + assign $2\oper_r__rc__rc$next[0:0]$5442 $1\oper_r__rc__rc$next[0:0]$5426 + assign $2\oper_r__sign_extend$next[0:0]$5443 $1\oper_r__sign_extend$next[0:0]$5427 + assign $2\oper_r__zero_a$next[0:0]$5444 $1\oper_r__zero_a$next[0:0]$5428 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $3\oper_r__imm_data__data$next[63:0]$5445 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $3\oper_r__imm_data__ok$next[0:0]$5446 1'0 + assign $3\oper_r__rc__rc$next[0:0]$5450 1'0 + assign $3\oper_r__rc__ok$next[0:0]$5449 1'0 + assign $3\oper_r__oe__oe$next[0:0]$5447 1'0 + assign $3\oper_r__oe__ok$next[0:0]$5448 1'0 + case + assign $3\oper_r__imm_data__data$next[63:0]$5445 $2\oper_r__imm_data__data$next[63:0]$5432 + assign $3\oper_r__imm_data__ok$next[0:0]$5446 $2\oper_r__imm_data__ok$next[0:0]$5433 + assign $3\oper_r__oe__oe$next[0:0]$5447 $2\oper_r__oe__oe$next[0:0]$5439 + assign $3\oper_r__oe__ok$next[0:0]$5448 $2\oper_r__oe__ok$next[0:0]$5440 + assign $3\oper_r__rc__ok$next[0:0]$5449 $2\oper_r__rc__ok$next[0:0]$5441 + assign $3\oper_r__rc__rc$next[0:0]$5450 $2\oper_r__rc__rc$next[0:0]$5442 + end + sync always + update \oper_r__byte_reverse$next $0\oper_r__byte_reverse$next[0:0]$5397 + update \oper_r__data_len$next $0\oper_r__data_len$next[3:0]$5398 + update \oper_r__fn_unit$next $0\oper_r__fn_unit$next[11:0]$5399 + update \oper_r__imm_data__data$next $0\oper_r__imm_data__data$next[63:0]$5400 + update \oper_r__imm_data__ok$next $0\oper_r__imm_data__ok$next[0:0]$5401 + update \oper_r__insn$next $0\oper_r__insn$next[31:0]$5402 + update \oper_r__insn_type$next $0\oper_r__insn_type$next[6:0]$5403 + update \oper_r__is_32bit$next $0\oper_r__is_32bit$next[0:0]$5404 + update \oper_r__is_signed$next $0\oper_r__is_signed$next[0:0]$5405 + update \oper_r__ldst_mode$next $0\oper_r__ldst_mode$next[1:0]$5406 + update \oper_r__oe__oe$next $0\oper_r__oe__oe$next[0:0]$5407 + update \oper_r__oe__ok$next $0\oper_r__oe__ok$next[0:0]$5408 + update \oper_r__rc__ok$next $0\oper_r__rc__ok$next[0:0]$5409 + update \oper_r__rc__rc$next $0\oper_r__rc__rc$next[0:0]$5410 + update \oper_r__sign_extend$next $0\oper_r__sign_extend$next[0:0]$5411 + update \oper_r__zero_a$next $0\oper_r__zero_a$next[0:0]$5412 + end + attribute \src "issuer_ls180.v:126141.3-126150.6" + process $proc$issuer_ls180.v:126141$5451 + assign { } { } + assign { } { } + assign $0\ldo_r$next[63:0]$5452 $1\ldo_r$next[63:0]$5453 + attribute \src "issuer_ls180.v:126142.5-126142.29" + switch \initial + attribute \src "issuer_ls180.v:126142.9-126142.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" + switch \ld_ok + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\ldo_r$next[63:0]$5453 \ldd_o + case + assign $1\ldo_r$next[63:0]$5453 \ldo_r + end + sync always + update \ldo_r$next $0\ldo_r$next[63:0]$5452 + end + attribute \src "issuer_ls180.v:126151.3-126166.6" + process $proc$issuer_ls180.v:126151$5454 + assign { } { } + assign { } { } + assign { } { } + assign $0\src_r0$next[63:0]$5455 $2\src_r0$next[63:0]$5457 + attribute \src "issuer_ls180.v:126152.5-126152.29" + switch \initial + attribute \src "issuer_ls180.v:126152.9-126152.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:392" + switch \cu_rd__go_i [0] + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\src_r0$next[63:0]$5456 \src1_i + case + assign $1\src_r0$next[63:0]$5456 \src_r0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:394" + switch \cu_issue_i + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\src_r0$next[63:0]$5457 64'0000000000000000000000000000000000000000000000000000000000000000 + case + assign $2\src_r0$next[63:0]$5457 $1\src_r0$next[63:0]$5456 + end + sync always + update \src_r0$next $0\src_r0$next[63:0]$5455 + end + attribute \src "issuer_ls180.v:126167.3-126182.6" + process $proc$issuer_ls180.v:126167$5458 + assign { } { } + assign { } { } + assign { } { } + assign $0\src_r1$next[63:0]$5459 $2\src_r1$next[63:0]$5461 + attribute \src "issuer_ls180.v:126168.5-126168.29" + switch \initial + attribute \src "issuer_ls180.v:126168.9-126168.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:392" + switch \cu_rd__go_i [1] + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\src_r1$next[63:0]$5460 \src2_i + case + assign $1\src_r1$next[63:0]$5460 \src_r1 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:394" + switch \cu_issue_i + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\src_r1$next[63:0]$5461 64'0000000000000000000000000000000000000000000000000000000000000000 + case + assign $2\src_r1$next[63:0]$5461 $1\src_r1$next[63:0]$5460 + end + sync always + update \src_r1$next $0\src_r1$next[63:0]$5459 + end + attribute \src "issuer_ls180.v:126183.3-126198.6" + process $proc$issuer_ls180.v:126183$5462 + assign { } { } + assign { } { } + assign { } { } + assign $0\src_r2$next[63:0]$5463 $2\src_r2$next[63:0]$5465 + attribute \src "issuer_ls180.v:126184.5-126184.29" + switch \initial + attribute \src "issuer_ls180.v:126184.9-126184.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:392" + switch \cu_rd__go_i [2] + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\src_r2$next[63:0]$5464 \src3_i + case + assign $1\src_r2$next[63:0]$5464 \src_r2 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:394" + switch \cu_issue_i + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\src_r2$next[63:0]$5465 64'0000000000000000000000000000000000000000000000000000000000000000 + case + assign $2\src_r2$next[63:0]$5465 $1\src_r2$next[63:0]$5464 + end + sync always + update \src_r2$next $0\src_r2$next[63:0]$5463 + end + attribute \src "issuer_ls180.v:126199.3-126208.6" + process $proc$issuer_ls180.v:126199$5466 + assign { } { } + assign { } { } + assign $0\ea_r$next[63:0]$5467 $1\ea_r$next[63:0]$5468 + attribute \src "issuer_ls180.v:126200.5-126200.29" + switch \initial + attribute \src "issuer_ls180.v:126200.9-126200.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" + switch \alu_l_q_alu + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\ea_r$next[63:0]$5468 \alu_o + case + assign $1\ea_r$next[63:0]$5468 \ea_r + end + sync always + update \ea_r$next $0\ea_r$next[63:0]$5467 + end + attribute \src "issuer_ls180.v:126209.3-126218.6" + process $proc$issuer_ls180.v:126209$5469 + assign { } { } + assign { } { } + assign $0\dest1_o[63:0] $1\dest1_o[63:0] + attribute \src "issuer_ls180.v:126210.5-126210.29" + switch \initial + attribute \src "issuer_ls180.v:126210.9-126210.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:471" + switch \cu_wr__go_i [0] + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dest1_o[63:0] \ldd_r + case + assign $1\dest1_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \dest1_o $0\dest1_o[63:0] + end + attribute \src "issuer_ls180.v:126219.3-126228.6" + process $proc$issuer_ls180.v:126219$5470 + assign { } { } + assign { } { } + assign $0\dest2_o[63:0] $1\dest2_o[63:0] + attribute \src "issuer_ls180.v:126220.5-126220.29" + switch \initial + attribute \src "issuer_ls180.v:126220.9-126220.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:476" + switch \$157 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dest2_o[63:0] \addr_r + case + assign $1\dest2_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \dest2_o $0\dest2_o[63:0] + end + attribute \src "issuer_ls180.v:126229.3-126237.6" + process $proc$issuer_ls180.v:126229$5471 + assign { } { } + assign { } { } + assign $0\ldst_port0_addr_i_ok$next[0:0]$5472 $1\ldst_port0_addr_i_ok$next[0:0]$5473 + attribute \src "issuer_ls180.v:126230.5-126230.29" + switch \initial + attribute \src "issuer_ls180.v:126230.9-126230.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\ldst_port0_addr_i_ok$next[0:0]$5473 1'0 + case + assign $1\ldst_port0_addr_i_ok$next[0:0]$5473 \$170 + end + sync always + update \ldst_port0_addr_i_ok$next $0\ldst_port0_addr_i_ok$next[0:0]$5472 + end + attribute \src "issuer_ls180.v:126238.3-126261.6" + process $proc$issuer_ls180.v:126238$5474 + assign { } { } + assign { } { } + assign $0\lddata_r[63:0] $1\lddata_r[63:0] + attribute \src "issuer_ls180.v:126239.5-126239.29" + switch \initial + attribute \src "issuer_ls180.v:126239.9-126239.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:499" + switch \oper_r__byte_reverse + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\lddata_r[63:0] $2\lddata_r[63:0] + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:22" + switch \oper_r__data_len + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0001 + assign { } { } + assign $2\lddata_r[63:0] \$172 + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0010 + assign { } { } + assign $2\lddata_r[63:0] \$174 + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0100 + assign { } { } + assign $2\lddata_r[63:0] \$176 + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $2\lddata_r[63:0] { \ldst_port0_ld_data_o [7:0] \ldst_port0_ld_data_o [15:8] \ldst_port0_ld_data_o [23:16] \ldst_port0_ld_data_o [31:24] \ldst_port0_ld_data_o [39:32] \ldst_port0_ld_data_o [47:40] \ldst_port0_ld_data_o [55:48] \ldst_port0_ld_data_o [63:56] } + case + assign $2\lddata_r[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + case + assign $1\lddata_r[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \lddata_r $0\lddata_r[63:0] + end + attribute \src "issuer_ls180.v:126262.3-126273.6" + process $proc$issuer_ls180.v:126262$5475 + assign { } { } + assign $0\revnorev[63:0] $1\revnorev[63:0] + attribute \src "issuer_ls180.v:126263.5-126263.29" + switch \initial + attribute \src "issuer_ls180.v:126263.9-126263.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:499" + switch \oper_r__byte_reverse + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\revnorev[63:0] \lddata_r + attribute \src "issuer_ls180.v:0.0-0.0" + case + assign { } { } + assign $1\revnorev[63:0] \ldst_port0_ld_data_o + end + sync always + update \revnorev $0\revnorev[63:0] + end + attribute \src "issuer_ls180.v:126274.3-126293.6" + process $proc$issuer_ls180.v:126274$5476 + assign { } { } + assign $0\ldd_o[63:0] $1\ldd_o[63:0] + attribute \src "issuer_ls180.v:126275.5-126275.29" + switch \initial + attribute \src "issuer_ls180.v:126275.9-126275.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:508" + switch \oper_r__sign_extend + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\ldd_o[63:0] $2\ldd_o[63:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:510" + switch \$178 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\ldd_o[63:0] { \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15] \revnorev [15:0] } + attribute \src "issuer_ls180.v:0.0-0.0" + case + assign { } { } + assign $2\ldd_o[63:0] { \revnorev [31] \revnorev [31] \revnorev [31] \revnorev [31] \revnorev [31] \revnorev [31] \revnorev [31] \revnorev [31] \revnorev [31] \revnorev [31] \revnorev [31] \revnorev [31] \revnorev [31] \revnorev [31] \revnorev [31] \revnorev [31] \revnorev [31] \revnorev [31] \revnorev [31] \revnorev [31] \revnorev [31] \revnorev [31] \revnorev [31] \revnorev [31] \revnorev [31] \revnorev [31] \revnorev [31] \revnorev [31] \revnorev [31] \revnorev [31] \revnorev [31] \revnorev [31] \revnorev [31:0] } + end + attribute \src "issuer_ls180.v:0.0-0.0" + case + assign { } { } + assign $1\ldd_o[63:0] \revnorev + end + sync always + update \ldd_o $0\ldd_o[63:0] + end + attribute \src "issuer_ls180.v:126294.3-126317.6" + process $proc$issuer_ls180.v:126294$5477 + assign { } { } + assign { } { } + assign $0\stdata_r[63:0] $1\stdata_r[63:0] + attribute \src "issuer_ls180.v:126295.5-126295.29" + switch \initial + attribute \src "issuer_ls180.v:126295.9-126295.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:522" + switch \oper_r__byte_reverse + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\stdata_r[63:0] $2\stdata_r[63:0] + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:22" + switch \oper_r__data_len + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0001 + assign { } { } + assign $2\stdata_r[63:0] \$180 + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0010 + assign { } { } + assign $2\stdata_r[63:0] \$182 + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0100 + assign { } { } + assign $2\stdata_r[63:0] \$184 + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $2\stdata_r[63:0] { \src_r2 [7:0] \src_r2 [15:8] \src_r2 [23:16] \src_r2 [31:24] \src_r2 [39:32] \src_r2 [47:40] \src_r2 [55:48] \src_r2 [63:56] } + case + assign $2\stdata_r[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + case + assign $1\stdata_r[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \stdata_r $0\stdata_r[63:0] + end + attribute \src "issuer_ls180.v:126318.3-126329.6" + process $proc$issuer_ls180.v:126318$5478 + assign { } { } + assign $0\ldst_port0_st_data_i[63:0] $1\ldst_port0_st_data_i[63:0] + attribute \src "issuer_ls180.v:126319.5-126319.29" + switch \initial + attribute \src "issuer_ls180.v:126319.9-126319.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:522" + switch \oper_r__byte_reverse + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\ldst_port0_st_data_i[63:0] \stdata_r + attribute \src "issuer_ls180.v:0.0-0.0" + case + assign { } { } + assign $1\ldst_port0_st_data_i[63:0] \src_r2 + end + sync always + update \ldst_port0_st_data_i $0\ldst_port0_st_data_i[63:0] + end + connect \$9 $or$issuer_ls180.v:125777$5237_Y + connect \$99 $and$issuer_ls180.v:125778$5238_Y + connect \$101 $and$issuer_ls180.v:125779$5239_Y + connect \$103 $and$issuer_ls180.v:125780$5240_Y + connect \$105 $and$issuer_ls180.v:125781$5241_Y + connect \$107 $and$issuer_ls180.v:125782$5242_Y + connect \$109 $and$issuer_ls180.v:125783$5243_Y + connect \$111 $and$issuer_ls180.v:125784$5244_Y + connect \$113 $and$issuer_ls180.v:125785$5245_Y + connect \$115 $and$issuer_ls180.v:125786$5246_Y + connect \$117 $and$issuer_ls180.v:125787$5247_Y + connect \$11 $or$issuer_ls180.v:125788$5248_Y + connect \$119 $eq$issuer_ls180.v:125789$5249_Y + connect \$121 $and$issuer_ls180.v:125790$5250_Y + connect \$123 $and$issuer_ls180.v:125791$5251_Y + connect \$125 $and$issuer_ls180.v:125792$5252_Y + connect \$127 $or$issuer_ls180.v:125793$5253_Y + connect \$129 $or$issuer_ls180.v:125794$5254_Y + connect \$131 $or$issuer_ls180.v:125795$5255_Y + connect \$133 $and$issuer_ls180.v:125796$5256_Y + connect \$135 $and$issuer_ls180.v:125797$5257_Y + connect \$138 $or$issuer_ls180.v:125798$5258_Y + connect \$13 $or$issuer_ls180.v:125799$5259_Y + connect \$140 $or$issuer_ls180.v:125800$5260_Y + connect \$137 $not$issuer_ls180.v:125801$5261_Y + connect \$143 $and$issuer_ls180.v:125802$5262_Y + connect \$145 $or$issuer_ls180.v:125803$5263_Y + connect \$147 $and$issuer_ls180.v:125804$5264_Y + connect \$149 $not$issuer_ls180.v:125805$5265_Y + connect \$151 $or$issuer_ls180.v:125806$5266_Y + connect \$153 $and$issuer_ls180.v:125807$5267_Y + connect \$155 $eq$issuer_ls180.v:125808$5268_Y + connect \$157 $and$issuer_ls180.v:125809$5269_Y + connect \$15 $eq$issuer_ls180.v:125810$5270_Y + connect \$160 $eq$issuer_ls180.v:125811$5271_Y + connect \$162 $and$issuer_ls180.v:125812$5272_Y + connect \$164 $and$issuer_ls180.v:125813$5273_Y + connect \$166 $and$issuer_ls180.v:125814$5274_Y + connect \$168 $pos$issuer_ls180.v:125815$5276_Y + connect \$170 $and$issuer_ls180.v:125816$5277_Y + connect \$172 $pos$issuer_ls180.v:125817$5279_Y + connect \$174 $pos$issuer_ls180.v:125818$5280_Y + connect \$176 $pos$issuer_ls180.v:125819$5281_Y + connect \$178 $eq$issuer_ls180.v:125820$5282_Y + connect \$17 $eq$issuer_ls180.v:125821$5283_Y + connect \$180 $pos$issuer_ls180.v:125822$5285_Y + connect \$182 $pos$issuer_ls180.v:125823$5286_Y + connect \$184 $pos$issuer_ls180.v:125824$5287_Y + connect \$1 $or$issuer_ls180.v:125825$5288_Y + connect \$19 $and$issuer_ls180.v:125826$5289_Y + connect \$21 $and$issuer_ls180.v:125827$5290_Y + connect \$23 $not$issuer_ls180.v:125828$5291_Y + connect \$25 $and$issuer_ls180.v:125829$5292_Y + connect \$27 $not$issuer_ls180.v:125830$5293_Y + connect \$29 $and$issuer_ls180.v:125831$5294_Y + connect \$32 $not$issuer_ls180.v:125832$5295_Y + connect \$34 $eq$issuer_ls180.v:125833$5296_Y + connect \$36 $and$issuer_ls180.v:125834$5297_Y + connect \$38 $or$issuer_ls180.v:125835$5298_Y + connect \$3 $or$issuer_ls180.v:125836$5299_Y + connect \$40 $not$issuer_ls180.v:125837$5300_Y + connect \$42 $eq$issuer_ls180.v:125838$5301_Y + connect \$44 $and$issuer_ls180.v:125839$5302_Y + connect \$46 $or$issuer_ls180.v:125840$5303_Y + connect \$48 $or$issuer_ls180.v:125841$5304_Y + connect \$50 $and$issuer_ls180.v:125842$5305_Y + connect \$52 $or$issuer_ls180.v:125843$5306_Y + connect \$54 $or$issuer_ls180.v:125844$5307_Y + connect \$56 $or$issuer_ls180.v:125845$5308_Y + connect \$58 $ternary$issuer_ls180.v:125846$5309_Y + connect \$5 $or$issuer_ls180.v:125847$5310_Y + connect \$60 $ternary$issuer_ls180.v:125848$5311_Y + connect \$62 $ternary$issuer_ls180.v:125849$5312_Y + connect \$64 $ternary$issuer_ls180.v:125850$5313_Y + connect \$67 $add$issuer_ls180.v:125851$5314_Y + connect \$69 $and$issuer_ls180.v:125852$5315_Y + connect \$71 $not$issuer_ls180.v:125853$5316_Y + connect \$73 $and$issuer_ls180.v:125854$5317_Y + connect \$75 $not$issuer_ls180.v:125855$5318_Y + connect \$77 $and$issuer_ls180.v:125856$5319_Y + connect \$7 $or$issuer_ls180.v:125857$5320_Y + connect \$79 $and$issuer_ls180.v:125858$5321_Y + connect \$81 $and$issuer_ls180.v:125859$5322_Y + connect \$83 $or$issuer_ls180.v:125860$5323_Y + connect \$86 $or$issuer_ls180.v:125861$5324_Y + connect \$85 $not$issuer_ls180.v:125862$5325_Y + connect \$89 $and$issuer_ls180.v:125863$5326_Y + connect \$91 $not$issuer_ls180.v:125864$5327_Y + connect \$93 $and$issuer_ls180.v:125865$5328_Y + connect \$95 $and$issuer_ls180.v:125866$5329_Y + connect \$97 $and$issuer_ls180.v:125867$5330_Y + connect \$31 \$48 + connect \$66 \$67 + connect \$159 \$162 + connect \cu_go_die_i 1'0 + connect \cu_shadown_i 1'1 + connect \ldst_port0_st_data_i_ok \cu_st__go_i + connect \ld_ok \ldst_port0_ld_data_o_ok + connect \addr_ok \ldst_port0_addr_ok_o + connect \addr_exc_o \ldst_port0_addr_exc_o + connect \ldst_port0_addr_i$next \$168 + connect \ldst_port0_data_len \oper_r__data_len + connect \ldst_port0_is_st_i \$166 + connect \ldst_port0_is_ld_i \$164 + connect \cu_wrmask_o \$162 [1:0] + connect \ea \dest2_o + connect \o \dest1_o + connect \cu_done_o \$153 + connect \wr_reset \$147 + connect \wr_any \$131 + connect \cu_wr__rel_o [1] \$125 + connect \cu_wr__rel_o [0] \$115 + connect \cu_st__rel_o \$105 + connect \cu_ad__rel_o \$97 + connect \rd_done \$93 + connect \alu_valid \$89 + connect \rda_any \$83 + connect \cu_rd__rel_o [2] \$81 + connect \cu_rd__rel_o [1:0] \$77 [1:0] + connect \cu_busy_o \opc_l_q_opc + connect \alu_ok$next \alu_valid + connect \alu_o \$67 [63:0] + connect \src2_or_imm \$64 + connect \src1_or_z \$62 + connect \addr_r \$60 + connect \ldd_r \$58 + connect \rst_l_r_rst \cu_issue_i + connect \rst_l_s_rst \addr_ok + connect \lsd_l_s_lsd \cu_issue_i + connect \sto_l_s_sto \$50 + connect \wri_l_s_wri \cu_issue_i + connect \lod_l_r_lod \ld_ok + connect \lod_l_s_lod \reset_i + connect \adr_l_s_adr \reset_i + connect \alu_l_r_alu \$29 + connect \alu_l_s_alu \reset_i + connect \st_o \op_is_st + connect \ld_o \op_is_ld + connect \stwd_mem_o \$21 + connect \load_mem_o \$19 + connect \op_is_ld \$17 + connect \op_is_st \$15 + connect \p_st_go$next \cu_st__go_i + connect \reset_a \$13 + connect \reset_r \$11 + connect \reset_s \$9 + connect \reset_u \$7 + connect \reset_w \$5 + connect \reset_o \$3 + connect \reset_i \$1 +end +attribute \src "issuer_ls180.v:126393.1-126980.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.fus.shiftrot0.alu_shift_rot0.pipe1.main.rotator.left_mask" +attribute \generator "nMigen" +module \left_mask + attribute \src "issuer_ls180.v:126394.7-126394.20" + wire $0\initial[0:0] + attribute \src "issuer_ls180.v:126592.3-126979.6" + wire width 64 $0\mask[63:0] + attribute \src "issuer_ls180.v:126592.3-126979.6" + wire $10\mask[9:9] + attribute \src "issuer_ls180.v:126592.3-126979.6" + wire $11\mask[10:10] + attribute \src "issuer_ls180.v:126592.3-126979.6" + wire $12\mask[11:11] + attribute \src "issuer_ls180.v:126592.3-126979.6" + wire $13\mask[12:12] + attribute \src "issuer_ls180.v:126592.3-126979.6" + wire $14\mask[13:13] + attribute \src "issuer_ls180.v:126592.3-126979.6" + wire $15\mask[14:14] + attribute \src "issuer_ls180.v:126592.3-126979.6" + wire $16\mask[15:15] + attribute \src "issuer_ls180.v:126592.3-126979.6" + wire $17\mask[16:16] + attribute \src "issuer_ls180.v:126592.3-126979.6" + wire $18\mask[17:17] + attribute \src "issuer_ls180.v:126592.3-126979.6" + wire $19\mask[18:18] + attribute \src "issuer_ls180.v:126592.3-126979.6" + wire $1\mask[0:0] + attribute \src "issuer_ls180.v:126592.3-126979.6" + wire $20\mask[19:19] + attribute \src "issuer_ls180.v:126592.3-126979.6" + wire $21\mask[20:20] + attribute \src "issuer_ls180.v:126592.3-126979.6" + wire $22\mask[21:21] + attribute \src "issuer_ls180.v:126592.3-126979.6" + wire $23\mask[22:22] + attribute \src "issuer_ls180.v:126592.3-126979.6" + wire $24\mask[23:23] + attribute \src "issuer_ls180.v:126592.3-126979.6" + wire $25\mask[24:24] + attribute \src "issuer_ls180.v:126592.3-126979.6" + wire $26\mask[25:25] + attribute \src "issuer_ls180.v:126592.3-126979.6" + wire $27\mask[26:26] + attribute \src "issuer_ls180.v:126592.3-126979.6" + wire $28\mask[27:27] + attribute \src "issuer_ls180.v:126592.3-126979.6" + wire $29\mask[28:28] + attribute \src "issuer_ls180.v:126592.3-126979.6" + wire $2\mask[1:1] + attribute \src "issuer_ls180.v:126592.3-126979.6" + wire $30\mask[29:29] + attribute \src "issuer_ls180.v:126592.3-126979.6" + wire $31\mask[30:30] + attribute \src "issuer_ls180.v:126592.3-126979.6" + wire $32\mask[31:31] + attribute \src "issuer_ls180.v:126592.3-126979.6" + wire $33\mask[32:32] + attribute \src "issuer_ls180.v:126592.3-126979.6" + wire $34\mask[33:33] + attribute \src "issuer_ls180.v:126592.3-126979.6" + wire $35\mask[34:34] + attribute \src "issuer_ls180.v:126592.3-126979.6" + wire $36\mask[35:35] + attribute \src "issuer_ls180.v:126592.3-126979.6" + wire $37\mask[36:36] + attribute \src "issuer_ls180.v:126592.3-126979.6" + wire $38\mask[37:37] + attribute \src "issuer_ls180.v:126592.3-126979.6" + wire $39\mask[38:38] + attribute \src "issuer_ls180.v:126592.3-126979.6" + wire $3\mask[2:2] + attribute \src "issuer_ls180.v:126592.3-126979.6" + wire $40\mask[39:39] + attribute \src "issuer_ls180.v:126592.3-126979.6" + wire $41\mask[40:40] + attribute \src "issuer_ls180.v:126592.3-126979.6" + wire $42\mask[41:41] + attribute \src "issuer_ls180.v:126592.3-126979.6" + wire $43\mask[42:42] + attribute \src "issuer_ls180.v:126592.3-126979.6" + wire $44\mask[43:43] + attribute \src "issuer_ls180.v:126592.3-126979.6" + wire $45\mask[44:44] + attribute \src "issuer_ls180.v:126592.3-126979.6" + wire $46\mask[45:45] + attribute \src "issuer_ls180.v:126592.3-126979.6" + wire $47\mask[46:46] + attribute \src "issuer_ls180.v:126592.3-126979.6" + wire $48\mask[47:47] + attribute \src "issuer_ls180.v:126592.3-126979.6" + wire $49\mask[48:48] + attribute \src "issuer_ls180.v:126592.3-126979.6" + wire $4\mask[3:3] + attribute \src "issuer_ls180.v:126592.3-126979.6" + wire $50\mask[49:49] + attribute \src "issuer_ls180.v:126592.3-126979.6" + wire $51\mask[50:50] + attribute \src "issuer_ls180.v:126592.3-126979.6" + wire $52\mask[51:51] + attribute \src "issuer_ls180.v:126592.3-126979.6" + wire $53\mask[52:52] + attribute \src "issuer_ls180.v:126592.3-126979.6" + wire $54\mask[53:53] + attribute \src "issuer_ls180.v:126592.3-126979.6" + wire $55\mask[54:54] + attribute \src "issuer_ls180.v:126592.3-126979.6" + wire $56\mask[55:55] + attribute \src "issuer_ls180.v:126592.3-126979.6" + wire $57\mask[56:56] + attribute \src "issuer_ls180.v:126592.3-126979.6" + wire $58\mask[57:57] + attribute \src "issuer_ls180.v:126592.3-126979.6" + wire $59\mask[58:58] + attribute \src "issuer_ls180.v:126592.3-126979.6" + wire $5\mask[4:4] + attribute \src "issuer_ls180.v:126592.3-126979.6" + wire $60\mask[59:59] + attribute \src "issuer_ls180.v:126592.3-126979.6" + wire $61\mask[60:60] + attribute \src "issuer_ls180.v:126592.3-126979.6" + wire $62\mask[61:61] + attribute \src "issuer_ls180.v:126592.3-126979.6" + wire $63\mask[62:62] + attribute \src "issuer_ls180.v:126592.3-126979.6" + wire $64\mask[63:63] + attribute \src "issuer_ls180.v:126592.3-126979.6" + wire $6\mask[5:5] + attribute \src "issuer_ls180.v:126592.3-126979.6" + wire $7\mask[6:6] + attribute \src "issuer_ls180.v:126592.3-126979.6" + wire $8\mask[7:7] + attribute \src "issuer_ls180.v:126592.3-126979.6" + wire $9\mask[8:8] + attribute \src "issuer_ls180.v:126528.17-126528.96" + wire $gt$issuer_ls180.v:126528$5515_Y + attribute \src "issuer_ls180.v:126529.18-126529.98" + wire $gt$issuer_ls180.v:126529$5516_Y + attribute \src "issuer_ls180.v:126530.19-126530.99" + wire $gt$issuer_ls180.v:126530$5517_Y + attribute \src "issuer_ls180.v:126531.19-126531.99" + wire $gt$issuer_ls180.v:126531$5518_Y + attribute \src "issuer_ls180.v:126532.19-126532.99" + wire $gt$issuer_ls180.v:126532$5519_Y + attribute \src "issuer_ls180.v:126533.19-126533.99" + wire $gt$issuer_ls180.v:126533$5520_Y + attribute \src "issuer_ls180.v:126534.19-126534.99" + wire $gt$issuer_ls180.v:126534$5521_Y + attribute \src "issuer_ls180.v:126535.19-126535.99" + wire $gt$issuer_ls180.v:126535$5522_Y + attribute \src "issuer_ls180.v:126536.19-126536.99" + wire $gt$issuer_ls180.v:126536$5523_Y + attribute \src "issuer_ls180.v:126537.19-126537.99" + wire $gt$issuer_ls180.v:126537$5524_Y + attribute \src "issuer_ls180.v:126538.19-126538.99" + wire $gt$issuer_ls180.v:126538$5525_Y + attribute \src "issuer_ls180.v:126539.18-126539.97" + wire $gt$issuer_ls180.v:126539$5526_Y + attribute \src "issuer_ls180.v:126540.19-126540.99" + wire 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wire \$91 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + wire \$93 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + wire \$95 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + wire \$97 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + wire \$99 + attribute \src "issuer_ls180.v:126394.7-126394.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:12" + wire width 64 output 1 \mask + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:11" + wire width 7 input 2 \shift + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + cell $gt $gt$issuer_ls180.v:126528$5515 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 3'100 + connect \Y $gt$issuer_ls180.v:126528$5515_Y + end + attribute \src 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"/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + cell $gt $gt$issuer_ls180.v:126532$5519 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 6'110100 + connect \Y $gt$issuer_ls180.v:126532$5519_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + cell $gt $gt$issuer_ls180.v:126533$5520 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 6'110101 + connect \Y $gt$issuer_ls180.v:126533$5520_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + cell $gt $gt$issuer_ls180.v:126534$5521 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 6'110110 + connect \Y $gt$issuer_ls180.v:126534$5521_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + cell $gt $gt$issuer_ls180.v:126535$5522 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 6'110111 + connect \Y $gt$issuer_ls180.v:126535$5522_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + cell $gt $gt$issuer_ls180.v:126536$5523 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 6'111000 + connect \Y $gt$issuer_ls180.v:126536$5523_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + cell $gt $gt$issuer_ls180.v:126537$5524 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 6'111001 + connect \Y $gt$issuer_ls180.v:126537$5524_Y + end + attribute \src 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"/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + cell $gt $gt$issuer_ls180.v:126541$5528 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 6'111100 + connect \Y $gt$issuer_ls180.v:126541$5528_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + cell $gt $gt$issuer_ls180.v:126542$5529 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 6'111101 + connect \Y $gt$issuer_ls180.v:126542$5529_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + cell $gt $gt$issuer_ls180.v:126543$5530 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 6'111110 + connect \Y $gt$issuer_ls180.v:126543$5530_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + cell $gt $gt$issuer_ls180.v:126544$5531 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 6'111111 + connect \Y $gt$issuer_ls180.v:126544$5531_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + cell $gt $gt$issuer_ls180.v:126545$5532 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 3'110 + connect \Y $gt$issuer_ls180.v:126545$5532_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + cell $gt $gt$issuer_ls180.v:126546$5533 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 3'111 + connect \Y $gt$issuer_ls180.v:126546$5533_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + cell $gt $gt$issuer_ls180.v:126547$5534 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 4'1000 + connect \Y $gt$issuer_ls180.v:126547$5534_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + cell $gt $gt$issuer_ls180.v:126548$5535 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 1'0 + connect \Y $gt$issuer_ls180.v:126548$5535_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + cell $gt $gt$issuer_ls180.v:126549$5536 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 4'1001 + connect \Y $gt$issuer_ls180.v:126549$5536_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + cell $gt $gt$issuer_ls180.v:126550$5537 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 4'1010 + connect \Y $gt$issuer_ls180.v:126550$5537_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + cell $gt $gt$issuer_ls180.v:126551$5538 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 4'1011 + connect \Y $gt$issuer_ls180.v:126551$5538_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + cell $gt $gt$issuer_ls180.v:126552$5539 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 4'1100 + connect \Y $gt$issuer_ls180.v:126552$5539_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + cell $gt $gt$issuer_ls180.v:126553$5540 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 4'1101 + connect \Y $gt$issuer_ls180.v:126553$5540_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + cell $gt $gt$issuer_ls180.v:126554$5541 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 4'1110 + connect \Y $gt$issuer_ls180.v:126554$5541_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + cell $gt $gt$issuer_ls180.v:126555$5542 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 4'1111 + connect \Y $gt$issuer_ls180.v:126555$5542_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + cell $gt $gt$issuer_ls180.v:126556$5543 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 5'10000 + connect \Y $gt$issuer_ls180.v:126556$5543_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + cell $gt $gt$issuer_ls180.v:126557$5544 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 5'10001 + connect \Y $gt$issuer_ls180.v:126557$5544_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + cell $gt $gt$issuer_ls180.v:126558$5545 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 5'10010 + connect \Y $gt$issuer_ls180.v:126558$5545_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + cell $gt $gt$issuer_ls180.v:126559$5546 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 1'1 + connect \Y $gt$issuer_ls180.v:126559$5546_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + cell $gt $gt$issuer_ls180.v:126560$5547 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 5'10011 + connect \Y $gt$issuer_ls180.v:126560$5547_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + cell $gt $gt$issuer_ls180.v:126561$5548 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 5'10100 + connect \Y $gt$issuer_ls180.v:126561$5548_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + cell $gt $gt$issuer_ls180.v:126562$5549 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 5'10101 + connect \Y $gt$issuer_ls180.v:126562$5549_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + cell $gt $gt$issuer_ls180.v:126563$5550 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 5'10110 + connect \Y $gt$issuer_ls180.v:126563$5550_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + cell $gt $gt$issuer_ls180.v:126564$5551 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 5'10111 + connect \Y $gt$issuer_ls180.v:126564$5551_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + cell $gt $gt$issuer_ls180.v:126565$5552 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 5'11000 + connect \Y $gt$issuer_ls180.v:126565$5552_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + cell $gt $gt$issuer_ls180.v:126566$5553 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 5'11001 + connect \Y $gt$issuer_ls180.v:126566$5553_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + cell $gt $gt$issuer_ls180.v:126567$5554 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 5'11010 + connect \Y $gt$issuer_ls180.v:126567$5554_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + cell $gt $gt$issuer_ls180.v:126568$5555 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 5'11011 + connect \Y $gt$issuer_ls180.v:126568$5555_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + cell $gt $gt$issuer_ls180.v:126569$5556 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 5'11100 + connect \Y $gt$issuer_ls180.v:126569$5556_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + cell $gt $gt$issuer_ls180.v:126570$5557 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 2'10 + connect \Y $gt$issuer_ls180.v:126570$5557_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + cell $gt $gt$issuer_ls180.v:126571$5558 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 5'11101 + connect \Y $gt$issuer_ls180.v:126571$5558_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + cell $gt $gt$issuer_ls180.v:126572$5559 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 5'11110 + connect \Y $gt$issuer_ls180.v:126572$5559_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + cell $gt $gt$issuer_ls180.v:126573$5560 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 5'11111 + connect \Y $gt$issuer_ls180.v:126573$5560_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + cell $gt $gt$issuer_ls180.v:126574$5561 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 6'100000 + connect \Y $gt$issuer_ls180.v:126574$5561_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + cell $gt $gt$issuer_ls180.v:126575$5562 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 6'100001 + connect \Y $gt$issuer_ls180.v:126575$5562_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + cell $gt $gt$issuer_ls180.v:126576$5563 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 6'100010 + connect \Y $gt$issuer_ls180.v:126576$5563_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + cell $gt $gt$issuer_ls180.v:126577$5564 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 6'100011 + connect \Y $gt$issuer_ls180.v:126577$5564_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + cell $gt $gt$issuer_ls180.v:126578$5565 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 6'100100 + connect \Y $gt$issuer_ls180.v:126578$5565_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + cell $gt $gt$issuer_ls180.v:126579$5566 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 6'100101 + connect \Y $gt$issuer_ls180.v:126579$5566_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + cell $gt $gt$issuer_ls180.v:126580$5567 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 6'100110 + connect \Y $gt$issuer_ls180.v:126580$5567_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + cell $gt $gt$issuer_ls180.v:126581$5568 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 2'11 + connect \Y $gt$issuer_ls180.v:126581$5568_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + cell $gt $gt$issuer_ls180.v:126582$5569 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 6'100111 + connect \Y $gt$issuer_ls180.v:126582$5569_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + cell $gt $gt$issuer_ls180.v:126583$5570 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 6'101000 + connect \Y $gt$issuer_ls180.v:126583$5570_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + cell $gt $gt$issuer_ls180.v:126584$5571 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 6'101001 + connect \Y $gt$issuer_ls180.v:126584$5571_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + cell $gt $gt$issuer_ls180.v:126585$5572 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 6'101010 + connect \Y $gt$issuer_ls180.v:126585$5572_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + cell $gt $gt$issuer_ls180.v:126586$5573 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 6'101011 + connect \Y $gt$issuer_ls180.v:126586$5573_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + cell $gt $gt$issuer_ls180.v:126587$5574 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 6'101100 + connect \Y $gt$issuer_ls180.v:126587$5574_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + cell $gt $gt$issuer_ls180.v:126588$5575 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 6'101101 + connect \Y $gt$issuer_ls180.v:126588$5575_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + cell $gt $gt$issuer_ls180.v:126589$5576 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 6'101110 + connect \Y $gt$issuer_ls180.v:126589$5576_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + cell $gt $gt$issuer_ls180.v:126590$5577 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 6'101111 + connect \Y $gt$issuer_ls180.v:126590$5577_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + cell $gt $gt$issuer_ls180.v:126591$5578 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 6'110000 + connect \Y $gt$issuer_ls180.v:126591$5578_Y + end + attribute \src "issuer_ls180.v:126394.7-126394.20" + process $proc$issuer_ls180.v:126394$5580 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "issuer_ls180.v:126592.3-126979.6" + process $proc$issuer_ls180.v:126592$5579 + assign { } { } + assign { } { } + assign $0\mask[63:0] [0] $1\mask[0:0] + assign $0\mask[63:0] [1] $2\mask[1:1] + assign $0\mask[63:0] [2] $3\mask[2:2] + assign $0\mask[63:0] [3] $4\mask[3:3] + assign $0\mask[63:0] [4] $5\mask[4:4] + assign $0\mask[63:0] [5] $6\mask[5:5] + assign $0\mask[63:0] [6] $7\mask[6:6] + assign $0\mask[63:0] [7] $8\mask[7:7] + assign $0\mask[63:0] [8] $9\mask[8:8] + assign $0\mask[63:0] [9] $10\mask[9:9] + assign $0\mask[63:0] [10] $11\mask[10:10] + assign $0\mask[63:0] [11] $12\mask[11:11] + assign $0\mask[63:0] [12] $13\mask[12:12] + assign $0\mask[63:0] [13] $14\mask[13:13] + assign $0\mask[63:0] [14] $15\mask[14:14] + assign $0\mask[63:0] [15] $16\mask[15:15] + assign $0\mask[63:0] [16] $17\mask[16:16] + assign $0\mask[63:0] [17] $18\mask[17:17] + assign $0\mask[63:0] [18] $19\mask[18:18] + assign $0\mask[63:0] [19] $20\mask[19:19] + assign $0\mask[63:0] [20] $21\mask[20:20] + assign $0\mask[63:0] [21] $22\mask[21:21] + assign $0\mask[63:0] [22] $23\mask[22:22] + assign $0\mask[63:0] [23] $24\mask[23:23] + assign $0\mask[63:0] [24] $25\mask[24:24] + assign $0\mask[63:0] [25] $26\mask[25:25] + assign $0\mask[63:0] [26] $27\mask[26:26] + assign $0\mask[63:0] [27] $28\mask[27:27] + assign $0\mask[63:0] [28] $29\mask[28:28] + assign $0\mask[63:0] [29] $30\mask[29:29] + assign $0\mask[63:0] [30] $31\mask[30:30] + assign $0\mask[63:0] [31] $32\mask[31:31] + assign $0\mask[63:0] [32] $33\mask[32:32] + assign $0\mask[63:0] [33] $34\mask[33:33] + assign $0\mask[63:0] [34] $35\mask[34:34] + assign $0\mask[63:0] [35] $36\mask[35:35] + assign $0\mask[63:0] [36] $37\mask[36:36] + assign $0\mask[63:0] [37] $38\mask[37:37] + assign $0\mask[63:0] [38] $39\mask[38:38] + assign $0\mask[63:0] [39] $40\mask[39:39] + assign $0\mask[63:0] [40] $41\mask[40:40] + assign $0\mask[63:0] [41] $42\mask[41:41] + assign $0\mask[63:0] [42] $43\mask[42:42] + assign $0\mask[63:0] [43] $44\mask[43:43] + assign $0\mask[63:0] [44] $45\mask[44:44] + assign $0\mask[63:0] [45] $46\mask[45:45] + assign $0\mask[63:0] [46] $47\mask[46:46] + assign $0\mask[63:0] [47] $48\mask[47:47] + assign $0\mask[63:0] [48] $49\mask[48:48] + assign $0\mask[63:0] [49] $50\mask[49:49] + assign $0\mask[63:0] [50] $51\mask[50:50] + assign $0\mask[63:0] [51] $52\mask[51:51] + assign $0\mask[63:0] [52] $53\mask[52:52] + assign $0\mask[63:0] [53] $54\mask[53:53] + assign $0\mask[63:0] [54] $55\mask[54:54] + assign $0\mask[63:0] [55] $56\mask[55:55] + assign $0\mask[63:0] [56] $57\mask[56:56] + assign $0\mask[63:0] [57] $58\mask[57:57] + assign $0\mask[63:0] [58] $59\mask[58:58] + assign $0\mask[63:0] [59] $60\mask[59:59] + assign $0\mask[63:0] [60] $61\mask[60:60] + assign $0\mask[63:0] [61] $62\mask[61:61] + assign $0\mask[63:0] [62] $63\mask[62:62] + assign $0\mask[63:0] [63] $64\mask[63:63] + attribute \src "issuer_ls180.v:126593.5-126593.29" + switch \initial + attribute \src "issuer_ls180.v:126593.9-126593.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + switch \$1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\mask[0:0] 1'1 + case + assign $1\mask[0:0] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + switch \$3 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\mask[1:1] 1'1 + case + assign $2\mask[1:1] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + switch \$5 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\mask[2:2] 1'1 + case + assign $3\mask[2:2] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + switch \$7 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\mask[3:3] 1'1 + case + assign $4\mask[3:3] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + switch \$9 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\mask[4:4] 1'1 + case + assign $5\mask[4:4] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + switch \$11 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $6\mask[5:5] 1'1 + case + assign $6\mask[5:5] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + switch \$13 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $7\mask[6:6] 1'1 + case + assign $7\mask[6:6] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + switch \$15 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $8\mask[7:7] 1'1 + case + assign $8\mask[7:7] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + switch \$17 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $9\mask[8:8] 1'1 + case + assign $9\mask[8:8] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + switch \$19 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $10\mask[9:9] 1'1 + case + assign $10\mask[9:9] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + switch \$21 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $11\mask[10:10] 1'1 + case + assign $11\mask[10:10] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + switch \$23 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $12\mask[11:11] 1'1 + case + assign $12\mask[11:11] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + switch \$25 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $13\mask[12:12] 1'1 + case + assign $13\mask[12:12] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + switch \$27 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $14\mask[13:13] 1'1 + case + assign $14\mask[13:13] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + switch \$29 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $15\mask[14:14] 1'1 + case + assign $15\mask[14:14] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + switch \$31 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $16\mask[15:15] 1'1 + case + assign $16\mask[15:15] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + switch \$33 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $17\mask[16:16] 1'1 + case + assign $17\mask[16:16] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + switch \$35 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $18\mask[17:17] 1'1 + case + assign $18\mask[17:17] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + switch \$37 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $19\mask[18:18] 1'1 + case + assign $19\mask[18:18] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + switch \$39 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $20\mask[19:19] 1'1 + case + assign $20\mask[19:19] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + switch \$41 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $21\mask[20:20] 1'1 + case + assign $21\mask[20:20] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + switch \$43 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $22\mask[21:21] 1'1 + case + assign $22\mask[21:21] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + switch \$45 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $23\mask[22:22] 1'1 + case + assign $23\mask[22:22] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + switch \$47 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $24\mask[23:23] 1'1 + case + assign $24\mask[23:23] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + switch \$49 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $25\mask[24:24] 1'1 + case + assign $25\mask[24:24] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + switch \$51 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $26\mask[25:25] 1'1 + case + assign $26\mask[25:25] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + switch \$53 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $27\mask[26:26] 1'1 + case + assign $27\mask[26:26] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + switch \$55 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $28\mask[27:27] 1'1 + case + assign $28\mask[27:27] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + switch \$57 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $29\mask[28:28] 1'1 + case + assign $29\mask[28:28] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + switch \$59 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $30\mask[29:29] 1'1 + case + assign $30\mask[29:29] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + switch \$61 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $31\mask[30:30] 1'1 + case + assign $31\mask[30:30] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + switch \$63 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $32\mask[31:31] 1'1 + case + assign $32\mask[31:31] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + switch \$65 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $33\mask[32:32] 1'1 + case + assign $33\mask[32:32] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + switch \$67 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $34\mask[33:33] 1'1 + case + assign $34\mask[33:33] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + switch \$69 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $35\mask[34:34] 1'1 + case + assign $35\mask[34:34] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + switch \$71 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $36\mask[35:35] 1'1 + case + assign $36\mask[35:35] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + switch \$73 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $37\mask[36:36] 1'1 + case + assign $37\mask[36:36] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + switch \$75 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $38\mask[37:37] 1'1 + case + assign $38\mask[37:37] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + switch \$77 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $39\mask[38:38] 1'1 + case + assign $39\mask[38:38] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + switch \$79 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $40\mask[39:39] 1'1 + case + assign $40\mask[39:39] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + switch \$81 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $41\mask[40:40] 1'1 + case + assign $41\mask[40:40] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + switch \$83 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $42\mask[41:41] 1'1 + case + assign $42\mask[41:41] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + switch \$85 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $43\mask[42:42] 1'1 + case + assign $43\mask[42:42] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + switch \$87 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $44\mask[43:43] 1'1 + case + assign $44\mask[43:43] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + switch \$89 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $45\mask[44:44] 1'1 + case + assign $45\mask[44:44] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + switch \$91 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $46\mask[45:45] 1'1 + case + assign $46\mask[45:45] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + switch \$93 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $47\mask[46:46] 1'1 + case + assign $47\mask[46:46] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + switch \$95 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $48\mask[47:47] 1'1 + case + assign $48\mask[47:47] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + switch \$97 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $49\mask[48:48] 1'1 + case + assign $49\mask[48:48] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + switch \$99 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $50\mask[49:49] 1'1 + case + assign $50\mask[49:49] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + switch \$101 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $51\mask[50:50] 1'1 + case + assign $51\mask[50:50] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + switch \$103 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $52\mask[51:51] 1'1 + case + assign $52\mask[51:51] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + switch \$105 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $53\mask[52:52] 1'1 + case + assign $53\mask[52:52] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + switch \$107 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $54\mask[53:53] 1'1 + case + assign $54\mask[53:53] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + switch \$109 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $55\mask[54:54] 1'1 + case + assign $55\mask[54:54] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + switch \$111 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $56\mask[55:55] 1'1 + case + assign $56\mask[55:55] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + switch \$113 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $57\mask[56:56] 1'1 + case + assign $57\mask[56:56] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + switch \$115 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $58\mask[57:57] 1'1 + case + assign $58\mask[57:57] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + switch \$117 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $59\mask[58:58] 1'1 + case + assign $59\mask[58:58] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + switch \$119 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $60\mask[59:59] 1'1 + case + assign $60\mask[59:59] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + switch \$121 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $61\mask[60:60] 1'1 + case + assign $61\mask[60:60] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + switch \$123 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $62\mask[61:61] 1'1 + case + assign $62\mask[61:61] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + switch \$125 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $63\mask[62:62] 1'1 + case + assign $63\mask[62:62] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + switch \$127 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $64\mask[63:63] 1'1 + case + assign $64\mask[63:63] 1'0 + end + sync always + update \mask $0\mask[63:0] + end + connect \$9 $gt$issuer_ls180.v:126528$5515_Y + connect \$99 $gt$issuer_ls180.v:126529$5516_Y + connect \$101 $gt$issuer_ls180.v:126530$5517_Y + connect \$103 $gt$issuer_ls180.v:126531$5518_Y + connect \$105 $gt$issuer_ls180.v:126532$5519_Y + connect \$107 $gt$issuer_ls180.v:126533$5520_Y + connect \$109 $gt$issuer_ls180.v:126534$5521_Y + connect \$111 $gt$issuer_ls180.v:126535$5522_Y + connect \$113 $gt$issuer_ls180.v:126536$5523_Y + connect \$115 $gt$issuer_ls180.v:126537$5524_Y + connect \$117 $gt$issuer_ls180.v:126538$5525_Y + connect \$11 $gt$issuer_ls180.v:126539$5526_Y + connect \$119 $gt$issuer_ls180.v:126540$5527_Y + connect \$121 $gt$issuer_ls180.v:126541$5528_Y + connect \$123 $gt$issuer_ls180.v:126542$5529_Y + connect \$125 $gt$issuer_ls180.v:126543$5530_Y + connect \$127 $gt$issuer_ls180.v:126544$5531_Y + connect \$13 $gt$issuer_ls180.v:126545$5532_Y + connect \$15 $gt$issuer_ls180.v:126546$5533_Y + connect \$17 $gt$issuer_ls180.v:126547$5534_Y + connect \$1 $gt$issuer_ls180.v:126548$5535_Y + connect \$19 $gt$issuer_ls180.v:126549$5536_Y + connect \$21 $gt$issuer_ls180.v:126550$5537_Y + connect \$23 $gt$issuer_ls180.v:126551$5538_Y + connect \$25 $gt$issuer_ls180.v:126552$5539_Y + connect \$27 $gt$issuer_ls180.v:126553$5540_Y + connect \$29 $gt$issuer_ls180.v:126554$5541_Y + connect \$31 $gt$issuer_ls180.v:126555$5542_Y + connect \$33 $gt$issuer_ls180.v:126556$5543_Y + connect \$35 $gt$issuer_ls180.v:126557$5544_Y + connect \$37 $gt$issuer_ls180.v:126558$5545_Y + connect \$3 $gt$issuer_ls180.v:126559$5546_Y + connect \$39 $gt$issuer_ls180.v:126560$5547_Y + connect \$41 $gt$issuer_ls180.v:126561$5548_Y + connect \$43 $gt$issuer_ls180.v:126562$5549_Y + connect \$45 $gt$issuer_ls180.v:126563$5550_Y + connect \$47 $gt$issuer_ls180.v:126564$5551_Y + connect \$49 $gt$issuer_ls180.v:126565$5552_Y + connect \$51 $gt$issuer_ls180.v:126566$5553_Y + connect \$53 $gt$issuer_ls180.v:126567$5554_Y + connect \$55 $gt$issuer_ls180.v:126568$5555_Y + connect \$57 $gt$issuer_ls180.v:126569$5556_Y + connect \$5 $gt$issuer_ls180.v:126570$5557_Y + connect \$59 $gt$issuer_ls180.v:126571$5558_Y + connect \$61 $gt$issuer_ls180.v:126572$5559_Y + connect \$63 $gt$issuer_ls180.v:126573$5560_Y + connect \$65 $gt$issuer_ls180.v:126574$5561_Y + connect \$67 $gt$issuer_ls180.v:126575$5562_Y + connect \$69 $gt$issuer_ls180.v:126576$5563_Y + connect \$71 $gt$issuer_ls180.v:126577$5564_Y + connect \$73 $gt$issuer_ls180.v:126578$5565_Y + connect \$75 $gt$issuer_ls180.v:126579$5566_Y + connect \$77 $gt$issuer_ls180.v:126580$5567_Y + connect \$7 $gt$issuer_ls180.v:126581$5568_Y + connect \$79 $gt$issuer_ls180.v:126582$5569_Y + connect \$81 $gt$issuer_ls180.v:126583$5570_Y + connect \$83 $gt$issuer_ls180.v:126584$5571_Y + connect \$85 $gt$issuer_ls180.v:126585$5572_Y + connect \$87 $gt$issuer_ls180.v:126586$5573_Y + connect \$89 $gt$issuer_ls180.v:126587$5574_Y + connect \$91 $gt$issuer_ls180.v:126588$5575_Y + connect \$93 $gt$issuer_ls180.v:126589$5576_Y + connect \$95 $gt$issuer_ls180.v:126590$5577_Y + connect \$97 $gt$issuer_ls180.v:126591$5578_Y +end +attribute \src "issuer_ls180.v:126984.1-127013.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.l0.pimem.lenexp" +attribute \generator "nMigen" +module \lenexp + attribute \src "issuer_ls180.v:127008.17-127008.101" + wire width 64 $extend$issuer_ls180.v:127008$5584_Y + attribute \src "issuer_ls180.v:127008.17-127008.101" + wire width 64 $pos$issuer_ls180.v:127008$5585_Y + attribute \src "issuer_ls180.v:127005.17-127005.111" + wire width 20 $sshl$issuer_ls180.v:127005$5581_Y + attribute \src "issuer_ls180.v:127007.17-127007.113" + wire width 32 $sshl$issuer_ls180.v:127007$5583_Y + attribute \src "issuer_ls180.v:127006.17-127006.107" + wire width 21 $sub$issuer_ls180.v:127006$5582_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:150" + wire width 21 \$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:150" + wire width 20 \$2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:150" + wire width 21 \$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:151" + wire width 64 \$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:151" + wire width 32 \$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:131" + wire width 4 input 1 \addr_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:148" + wire width 17 \binlen + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:130" + wire width 4 input 4 \len_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:132" + wire width 64 output 2 \lexp_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:134" + wire width 176 output 3 \rexp_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:151" + cell $pos $extend$issuer_ls180.v:127008$5584 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \Y_WIDTH 64 + connect \A \$7 + connect \Y $extend$issuer_ls180.v:127008$5584_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:151" + cell $pos $pos$issuer_ls180.v:127008$5585 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A $extend$issuer_ls180.v:127008$5584_Y + connect \Y $pos$issuer_ls180.v:127008$5585_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:150" + cell $sshl $sshl$issuer_ls180.v:127005$5581 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 20 + connect \A 5'00001 + connect \B \len_i + connect \Y $sshl$issuer_ls180.v:127005$5581_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:151" + cell $sshl $sshl$issuer_ls180.v:127007$5583 + parameter \A_SIGNED 0 + parameter \A_WIDTH 17 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 32 + connect \A \binlen + connect \B \addr_i + connect \Y $sshl$issuer_ls180.v:127007$5583_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:150" + cell $sub $sub$issuer_ls180.v:127006$5582 + parameter \A_SIGNED 0 + parameter \A_WIDTH 20 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 21 + connect \A \$2 + connect \B 1'1 + connect \Y $sub$issuer_ls180.v:127006$5582_Y + end + connect \$2 $sshl$issuer_ls180.v:127005$5581_Y + connect \$4 $sub$issuer_ls180.v:127006$5582_Y + connect \$7 $sshl$issuer_ls180.v:127007$5583_Y + connect \$6 $pos$issuer_ls180.v:127008$5585_Y + connect \$1 \$4 + connect \rexp_o { \lexp_o [21] \lexp_o [21] \lexp_o [21] \lexp_o [21] \lexp_o [21] \lexp_o [21] \lexp_o [21] \lexp_o [21:20] \lexp_o [20] \lexp_o [20] \lexp_o [20] \lexp_o [20] \lexp_o [20] \lexp_o [20] \lexp_o [20:19] \lexp_o [19] \lexp_o [19] \lexp_o [19] \lexp_o [19] \lexp_o [19] \lexp_o [19] \lexp_o [19:18] \lexp_o [18] \lexp_o [18] \lexp_o [18] \lexp_o [18] \lexp_o [18] \lexp_o [18] \lexp_o [18:17] \lexp_o [17] \lexp_o [17] \lexp_o [17] \lexp_o [17] \lexp_o [17] \lexp_o [17] \lexp_o [17:16] \lexp_o [16] \lexp_o [16] \lexp_o [16] \lexp_o [16] \lexp_o [16] \lexp_o [16] \lexp_o [16:15] \lexp_o [15] \lexp_o [15] \lexp_o [15] \lexp_o [15] \lexp_o [15] \lexp_o [15] \lexp_o [15:14] \lexp_o [14] \lexp_o [14] \lexp_o [14] \lexp_o [14] \lexp_o [14] \lexp_o [14] \lexp_o [14:13] \lexp_o [13] \lexp_o [13] \lexp_o [13] \lexp_o [13] \lexp_o [13] \lexp_o [13] \lexp_o [13:12] \lexp_o [12] \lexp_o [12] \lexp_o [12] \lexp_o [12] \lexp_o [12] \lexp_o [12] \lexp_o [12:11] \lexp_o [11] \lexp_o [11] \lexp_o [11] \lexp_o [11] \lexp_o [11] \lexp_o [11] \lexp_o [11:10] \lexp_o [10] \lexp_o [10] \lexp_o [10] \lexp_o [10] \lexp_o [10] \lexp_o [10] \lexp_o [10:9] \lexp_o [9] \lexp_o [9] \lexp_o [9] \lexp_o [9] \lexp_o [9] \lexp_o [9] \lexp_o [9:8] \lexp_o [8] \lexp_o [8] \lexp_o [8] \lexp_o [8] \lexp_o [8] \lexp_o [8] \lexp_o [8:7] \lexp_o [7] \lexp_o [7] \lexp_o [7] \lexp_o [7] \lexp_o [7] \lexp_o [7] \lexp_o [7:6] \lexp_o [6] \lexp_o [6] \lexp_o [6] \lexp_o [6] \lexp_o [6] \lexp_o [6] \lexp_o [6:5] \lexp_o [5] \lexp_o [5] \lexp_o [5] \lexp_o [5] \lexp_o [5] \lexp_o [5] \lexp_o [5:4] \lexp_o [4] \lexp_o [4] \lexp_o [4] \lexp_o [4] \lexp_o [4] \lexp_o [4] \lexp_o [4:3] \lexp_o [3] \lexp_o [3] \lexp_o [3] \lexp_o [3] \lexp_o [3] \lexp_o [3] \lexp_o [3:2] \lexp_o [2] \lexp_o [2] \lexp_o [2] \lexp_o [2] \lexp_o [2] \lexp_o [2] \lexp_o [2:1] \lexp_o [1] \lexp_o [1] \lexp_o [1] \lexp_o [1] \lexp_o [1] \lexp_o [1] \lexp_o [1:0] \lexp_o [0] \lexp_o [0] \lexp_o [0] \lexp_o [0] \lexp_o [0] \lexp_o [0] \lexp_o [0] } + connect \lexp_o \$6 + connect \binlen \$4 [16:0] +end +attribute \src "issuer_ls180.v:127017.1-127075.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.fus.ldst0.lod_l" +attribute \generator "nMigen" +module \lod_l + attribute \src "issuer_ls180.v:127018.7-127018.20" + wire $0\initial[0:0] + attribute \src "issuer_ls180.v:127063.3-127071.6" + wire $0\q_int$next[0:0]$5596 + attribute \src "issuer_ls180.v:127061.3-127062.27" + wire $0\q_int[0:0] + attribute \src "issuer_ls180.v:127063.3-127071.6" + wire $1\q_int$next[0:0]$5597 + attribute \src "issuer_ls180.v:127040.7-127040.19" + wire $1\q_int[0:0] + attribute \src "issuer_ls180.v:127053.17-127053.96" + wire $and$issuer_ls180.v:127053$5586_Y + attribute \src "issuer_ls180.v:127058.17-127058.96" + wire $and$issuer_ls180.v:127058$5591_Y + attribute \src "issuer_ls180.v:127055.18-127055.93" + wire $not$issuer_ls180.v:127055$5588_Y + attribute \src "issuer_ls180.v:127057.17-127057.92" + wire $not$issuer_ls180.v:127057$5590_Y + attribute \src "issuer_ls180.v:127060.17-127060.92" + wire $not$issuer_ls180.v:127060$5593_Y + attribute \src "issuer_ls180.v:127054.18-127054.98" + wire $or$issuer_ls180.v:127054$5587_Y + attribute \src "issuer_ls180.v:127056.18-127056.99" + wire $or$issuer_ls180.v:127056$5589_Y + attribute \src "issuer_ls180.v:127059.17-127059.97" + wire $or$issuer_ls180.v:127059$5592_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire \$13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" + wire input 5 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" + wire input 1 \coresync_rst + attribute \src "issuer_ls180.v:127018.7-127018.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire \q_lod + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" + wire \qlq_lod + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + wire output 4 \qn_lod + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire input 3 \r_lod + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire input 2 \s_lod + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $and $and$issuer_ls180.v:127053$5586 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$7 + connect \Y $and$issuer_ls180.v:127053$5586_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $and $and$issuer_ls180.v:127058$5591 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$1 + connect \Y $and$issuer_ls180.v:127058$5591_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + cell $not $not$issuer_ls180.v:127055$5588 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_lod + connect \Y $not$issuer_ls180.v:127055$5588_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $not $not$issuer_ls180.v:127057$5590 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_lod + connect \Y $not$issuer_ls180.v:127057$5590_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $not $not$issuer_ls180.v:127060$5593 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_lod + connect \Y $not$issuer_ls180.v:127060$5593_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $or $or$issuer_ls180.v:127054$5587 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$9 + connect \B \s_lod + connect \Y $or$issuer_ls180.v:127054$5587_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + cell $or $or$issuer_ls180.v:127056$5589 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_lod + connect \B \q_int + connect \Y $or$issuer_ls180.v:127056$5589_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $or $or$issuer_ls180.v:127059$5592 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$3 + connect \B \s_lod + connect \Y $or$issuer_ls180.v:127059$5592_Y + end + attribute \src "issuer_ls180.v:127018.7-127018.20" + process $proc$issuer_ls180.v:127018$5598 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "issuer_ls180.v:127040.7-127040.19" + process $proc$issuer_ls180.v:127040$5599 + assign { } { } + assign $1\q_int[0:0] 1'0 + sync always + sync init + update \q_int $1\q_int[0:0] + end + attribute \src "issuer_ls180.v:127061.3-127062.27" + process $proc$issuer_ls180.v:127061$5594 + assign { } { } + assign $0\q_int[0:0] \q_int$next + sync posedge \coresync_clk + update \q_int $0\q_int[0:0] + end + attribute \src "issuer_ls180.v:127063.3-127071.6" + process $proc$issuer_ls180.v:127063$5595 + assign { } { } + assign { } { } + assign $0\q_int$next[0:0]$5596 $1\q_int$next[0:0]$5597 + attribute \src "issuer_ls180.v:127064.5-127064.29" + switch \initial + attribute \src "issuer_ls180.v:127064.9-127064.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\q_int$next[0:0]$5597 1'0 + case + assign $1\q_int$next[0:0]$5597 \$5 + end + sync always + update \q_int$next $0\q_int$next[0:0]$5596 + end + connect \$9 $and$issuer_ls180.v:127053$5586_Y + connect \$11 $or$issuer_ls180.v:127054$5587_Y + connect \$13 $not$issuer_ls180.v:127055$5588_Y + connect \$15 $or$issuer_ls180.v:127056$5589_Y + connect \$1 $not$issuer_ls180.v:127057$5590_Y + connect \$3 $and$issuer_ls180.v:127058$5591_Y + connect \$5 $or$issuer_ls180.v:127059$5592_Y + connect \$7 $not$issuer_ls180.v:127060$5593_Y + connect \qlq_lod \$15 + connect \qn_lod \$13 + connect \q_lod \$11 +end +attribute \src "issuer_ls180.v:127079.1-128193.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.fus.logical0" +attribute \generator "nMigen" +module \logical0 + attribute \src "issuer_ls180.v:127818.3-127819.24" + wire $0\all_rd_dly[0:0] + attribute \src "issuer_ls180.v:127816.3-127817.44" + wire $0\alu_done_dly[0:0] + attribute \src "issuer_ls180.v:128123.3-128131.6" + wire $0\alu_l_r_alu$next[0:0]$5800 + attribute \src "issuer_ls180.v:127740.3-127741.39" + wire $0\alu_l_r_alu[0:0] + attribute \src "issuer_ls180.v:128001.3-128039.6" + wire width 4 $0\alu_logical0_logical_op__data_len$next[3:0]$5729 + attribute \src "issuer_ls180.v:127790.3-127791.83" + wire width 4 $0\alu_logical0_logical_op__data_len[3:0] + attribute \src "issuer_ls180.v:128001.3-128039.6" + wire width 12 $0\alu_logical0_logical_op__fn_unit$next[11:0]$5730 + attribute \src "issuer_ls180.v:127760.3-127761.81" + wire width 12 $0\alu_logical0_logical_op__fn_unit[11:0] + attribute \src "issuer_ls180.v:128001.3-128039.6" + wire width 64 $0\alu_logical0_logical_op__imm_data__data$next[63:0]$5731 + attribute \src "issuer_ls180.v:127762.3-127763.95" + wire width 64 $0\alu_logical0_logical_op__imm_data__data[63:0] + attribute \src "issuer_ls180.v:128001.3-128039.6" + wire $0\alu_logical0_logical_op__imm_data__ok$next[0:0]$5732 + attribute \src "issuer_ls180.v:127764.3-127765.91" + wire $0\alu_logical0_logical_op__imm_data__ok[0:0] + attribute \src "issuer_ls180.v:128001.3-128039.6" + wire width 2 $0\alu_logical0_logical_op__input_carry$next[1:0]$5733 + attribute \src "issuer_ls180.v:127778.3-127779.89" + wire width 2 $0\alu_logical0_logical_op__input_carry[1:0] + attribute \src "issuer_ls180.v:128001.3-128039.6" + wire width 32 $0\alu_logical0_logical_op__insn$next[31:0]$5734 + attribute \src "issuer_ls180.v:127792.3-127793.75" + wire width 32 $0\alu_logical0_logical_op__insn[31:0] + attribute \src "issuer_ls180.v:128001.3-128039.6" + wire width 7 $0\alu_logical0_logical_op__insn_type$next[6:0]$5735 + attribute \src "issuer_ls180.v:127758.3-127759.85" + wire width 7 $0\alu_logical0_logical_op__insn_type[6:0] + attribute \src "issuer_ls180.v:128001.3-128039.6" + wire $0\alu_logical0_logical_op__invert_in$next[0:0]$5736 + attribute \src "issuer_ls180.v:127774.3-127775.85" + wire $0\alu_logical0_logical_op__invert_in[0:0] + attribute \src "issuer_ls180.v:128001.3-128039.6" + wire $0\alu_logical0_logical_op__invert_out$next[0:0]$5737 + attribute \src "issuer_ls180.v:127780.3-127781.87" + wire $0\alu_logical0_logical_op__invert_out[0:0] + attribute \src "issuer_ls180.v:128001.3-128039.6" + wire $0\alu_logical0_logical_op__is_32bit$next[0:0]$5738 + attribute \src "issuer_ls180.v:127786.3-127787.83" + wire $0\alu_logical0_logical_op__is_32bit[0:0] + attribute \src "issuer_ls180.v:128001.3-128039.6" + wire $0\alu_logical0_logical_op__is_signed$next[0:0]$5739 + attribute \src "issuer_ls180.v:127788.3-127789.85" + wire $0\alu_logical0_logical_op__is_signed[0:0] + attribute \src "issuer_ls180.v:128001.3-128039.6" + wire $0\alu_logical0_logical_op__oe__oe$next[0:0]$5740 + attribute \src "issuer_ls180.v:127770.3-127771.79" + wire $0\alu_logical0_logical_op__oe__oe[0:0] + attribute \src "issuer_ls180.v:128001.3-128039.6" + wire $0\alu_logical0_logical_op__oe__ok$next[0:0]$5741 + attribute \src "issuer_ls180.v:127772.3-127773.79" + wire $0\alu_logical0_logical_op__oe__ok[0:0] + attribute \src "issuer_ls180.v:128001.3-128039.6" + wire $0\alu_logical0_logical_op__output_carry$next[0:0]$5742 + attribute \src "issuer_ls180.v:127784.3-127785.91" + wire $0\alu_logical0_logical_op__output_carry[0:0] + attribute \src "issuer_ls180.v:128001.3-128039.6" + wire $0\alu_logical0_logical_op__rc__ok$next[0:0]$5743 + attribute \src "issuer_ls180.v:127768.3-127769.79" + wire $0\alu_logical0_logical_op__rc__ok[0:0] + attribute \src "issuer_ls180.v:128001.3-128039.6" + wire $0\alu_logical0_logical_op__rc__rc$next[0:0]$5744 + attribute \src "issuer_ls180.v:127766.3-127767.79" + wire $0\alu_logical0_logical_op__rc__rc[0:0] + attribute \src "issuer_ls180.v:128001.3-128039.6" + wire $0\alu_logical0_logical_op__write_cr0$next[0:0]$5745 + attribute \src "issuer_ls180.v:127782.3-127783.85" + wire $0\alu_logical0_logical_op__write_cr0[0:0] + attribute \src "issuer_ls180.v:128001.3-128039.6" + wire $0\alu_logical0_logical_op__zero_a$next[0:0]$5746 + attribute \src "issuer_ls180.v:127776.3-127777.79" + wire $0\alu_logical0_logical_op__zero_a[0:0] + attribute \src "issuer_ls180.v:128114.3-128122.6" + wire $0\alui_l_r_alui$next[0:0]$5797 + attribute \src "issuer_ls180.v:127742.3-127743.43" + wire $0\alui_l_r_alui[0:0] + attribute \src "issuer_ls180.v:128040.3-128061.6" + wire width 64 $0\data_r0__o$next[63:0]$5772 + attribute \src "issuer_ls180.v:127754.3-127755.37" + wire width 64 $0\data_r0__o[63:0] + attribute \src "issuer_ls180.v:128040.3-128061.6" + wire $0\data_r0__o_ok$next[0:0]$5773 + attribute \src "issuer_ls180.v:127756.3-127757.43" + wire $0\data_r0__o_ok[0:0] + attribute \src "issuer_ls180.v:128062.3-128083.6" + wire width 4 $0\data_r1__cr_a$next[3:0]$5780 + attribute \src "issuer_ls180.v:127750.3-127751.43" + wire width 4 $0\data_r1__cr_a[3:0] + attribute \src "issuer_ls180.v:128062.3-128083.6" + wire $0\data_r1__cr_a_ok$next[0:0]$5781 + attribute \src "issuer_ls180.v:127752.3-127753.49" + wire $0\data_r1__cr_a_ok[0:0] + attribute \src "issuer_ls180.v:128132.3-128141.6" + wire width 64 $0\dest1_o[63:0] + attribute \src "issuer_ls180.v:128142.3-128151.6" + wire width 4 $0\dest2_o[3:0] + attribute \src "issuer_ls180.v:127080.7-127080.20" + wire $0\initial[0:0] + attribute \src "issuer_ls180.v:127956.3-127964.6" + wire $0\opc_l_r_opc$next[0:0]$5714 + attribute \src "issuer_ls180.v:127802.3-127803.39" + wire $0\opc_l_r_opc[0:0] + attribute \src "issuer_ls180.v:127947.3-127955.6" + wire $0\opc_l_s_opc$next[0:0]$5711 + attribute \src "issuer_ls180.v:127804.3-127805.39" + wire $0\opc_l_s_opc[0:0] + attribute \src "issuer_ls180.v:128152.3-128160.6" + wire width 2 $0\prev_wr_go$next[1:0]$5805 + attribute \src "issuer_ls180.v:127814.3-127815.37" + wire width 2 $0\prev_wr_go[1:0] + attribute \src "issuer_ls180.v:127901.3-127910.6" + wire $0\req_done[0:0] + attribute \src "issuer_ls180.v:127992.3-128000.6" + wire width 2 $0\req_l_r_req$next[1:0]$5726 + attribute \src "issuer_ls180.v:127794.3-127795.39" + wire width 2 $0\req_l_r_req[1:0] + attribute \src "issuer_ls180.v:127983.3-127991.6" + wire width 2 $0\req_l_s_req$next[1:0]$5723 + attribute \src "issuer_ls180.v:127796.3-127797.39" + wire width 2 $0\req_l_s_req[1:0] + attribute \src "issuer_ls180.v:127920.3-127928.6" + wire $0\rok_l_r_rdok$next[0:0]$5702 + attribute \src "issuer_ls180.v:127810.3-127811.41" + wire $0\rok_l_r_rdok[0:0] + attribute \src "issuer_ls180.v:127911.3-127919.6" + wire $0\rok_l_s_rdok$next[0:0]$5699 + attribute \src "issuer_ls180.v:127812.3-127813.41" + wire $0\rok_l_s_rdok[0:0] + attribute \src "issuer_ls180.v:127938.3-127946.6" + wire $0\rst_l_r_rst$next[0:0]$5708 + attribute \src "issuer_ls180.v:127806.3-127807.39" + wire $0\rst_l_r_rst[0:0] + attribute \src "issuer_ls180.v:127929.3-127937.6" + wire $0\rst_l_s_rst$next[0:0]$5705 + attribute \src "issuer_ls180.v:127808.3-127809.39" + wire $0\rst_l_s_rst[0:0] + attribute \src "issuer_ls180.v:127974.3-127982.6" + wire width 3 $0\src_l_r_src$next[2:0]$5720 + attribute \src "issuer_ls180.v:127798.3-127799.39" + wire width 3 $0\src_l_r_src[2:0] + attribute \src "issuer_ls180.v:127965.3-127973.6" + wire width 3 $0\src_l_s_src$next[2:0]$5717 + attribute \src "issuer_ls180.v:127800.3-127801.39" + wire width 3 $0\src_l_s_src[2:0] + attribute \src "issuer_ls180.v:128084.3-128093.6" + wire width 64 $0\src_r0$next[63:0]$5788 + attribute \src "issuer_ls180.v:127748.3-127749.29" + wire width 64 $0\src_r0[63:0] + attribute \src "issuer_ls180.v:128094.3-128103.6" + wire width 64 $0\src_r1$next[63:0]$5791 + attribute \src "issuer_ls180.v:127746.3-127747.29" + wire width 64 $0\src_r1[63:0] + attribute \src "issuer_ls180.v:128104.3-128113.6" + wire $0\src_r2$next[0:0]$5794 + attribute \src "issuer_ls180.v:127744.3-127745.29" + wire $0\src_r2[0:0] + attribute \src "issuer_ls180.v:127198.7-127198.24" + wire $1\all_rd_dly[0:0] + attribute \src "issuer_ls180.v:127208.7-127208.26" + wire $1\alu_done_dly[0:0] + attribute \src "issuer_ls180.v:128123.3-128131.6" + wire $1\alu_l_r_alu$next[0:0]$5801 + attribute \src "issuer_ls180.v:127216.7-127216.25" + wire $1\alu_l_r_alu[0:0] + attribute \src "issuer_ls180.v:128001.3-128039.6" + wire width 4 $1\alu_logical0_logical_op__data_len$next[3:0]$5747 + attribute \src "issuer_ls180.v:127224.13-127224.53" + wire width 4 $1\alu_logical0_logical_op__data_len[3:0] + attribute \src "issuer_ls180.v:128001.3-128039.6" + wire width 12 $1\alu_logical0_logical_op__fn_unit$next[11:0]$5748 + attribute \src "issuer_ls180.v:127241.14-127241.56" + wire width 12 $1\alu_logical0_logical_op__fn_unit[11:0] + attribute \src "issuer_ls180.v:128001.3-128039.6" + wire width 64 $1\alu_logical0_logical_op__imm_data__data$next[63:0]$5749 + attribute \src "issuer_ls180.v:127245.14-127245.76" + wire width 64 $1\alu_logical0_logical_op__imm_data__data[63:0] + attribute \src "issuer_ls180.v:128001.3-128039.6" + wire $1\alu_logical0_logical_op__imm_data__ok$next[0:0]$5750 + attribute \src "issuer_ls180.v:127249.7-127249.51" + wire $1\alu_logical0_logical_op__imm_data__ok[0:0] + attribute \src "issuer_ls180.v:128001.3-128039.6" + wire width 2 $1\alu_logical0_logical_op__input_carry$next[1:0]$5751 + attribute \src "issuer_ls180.v:127257.13-127257.56" + wire width 2 $1\alu_logical0_logical_op__input_carry[1:0] + attribute \src "issuer_ls180.v:128001.3-128039.6" + wire width 32 $1\alu_logical0_logical_op__insn$next[31:0]$5752 + attribute \src "issuer_ls180.v:127261.14-127261.51" + wire width 32 $1\alu_logical0_logical_op__insn[31:0] + attribute \src "issuer_ls180.v:128001.3-128039.6" + wire width 7 $1\alu_logical0_logical_op__insn_type$next[6:0]$5753 + attribute \src "issuer_ls180.v:127339.13-127339.55" + wire width 7 $1\alu_logical0_logical_op__insn_type[6:0] + attribute \src "issuer_ls180.v:128001.3-128039.6" + wire $1\alu_logical0_logical_op__invert_in$next[0:0]$5754 + attribute \src "issuer_ls180.v:127343.7-127343.48" + wire $1\alu_logical0_logical_op__invert_in[0:0] + attribute \src "issuer_ls180.v:128001.3-128039.6" + wire $1\alu_logical0_logical_op__invert_out$next[0:0]$5755 + attribute \src "issuer_ls180.v:127347.7-127347.49" + wire $1\alu_logical0_logical_op__invert_out[0:0] + attribute \src "issuer_ls180.v:128001.3-128039.6" + wire $1\alu_logical0_logical_op__is_32bit$next[0:0]$5756 + attribute \src "issuer_ls180.v:127351.7-127351.47" + wire $1\alu_logical0_logical_op__is_32bit[0:0] + attribute \src "issuer_ls180.v:128001.3-128039.6" + wire $1\alu_logical0_logical_op__is_signed$next[0:0]$5757 + attribute \src "issuer_ls180.v:127355.7-127355.48" + wire $1\alu_logical0_logical_op__is_signed[0:0] + attribute \src "issuer_ls180.v:128001.3-128039.6" + wire $1\alu_logical0_logical_op__oe__oe$next[0:0]$5758 + attribute \src "issuer_ls180.v:127359.7-127359.45" + wire $1\alu_logical0_logical_op__oe__oe[0:0] + attribute \src "issuer_ls180.v:128001.3-128039.6" + wire $1\alu_logical0_logical_op__oe__ok$next[0:0]$5759 + attribute \src "issuer_ls180.v:127363.7-127363.45" + wire $1\alu_logical0_logical_op__oe__ok[0:0] + attribute \src "issuer_ls180.v:128001.3-128039.6" + wire $1\alu_logical0_logical_op__output_carry$next[0:0]$5760 + attribute \src "issuer_ls180.v:127367.7-127367.51" + wire $1\alu_logical0_logical_op__output_carry[0:0] + attribute \src "issuer_ls180.v:128001.3-128039.6" + wire $1\alu_logical0_logical_op__rc__ok$next[0:0]$5761 + attribute \src "issuer_ls180.v:127371.7-127371.45" + wire $1\alu_logical0_logical_op__rc__ok[0:0] + attribute \src "issuer_ls180.v:128001.3-128039.6" + wire $1\alu_logical0_logical_op__rc__rc$next[0:0]$5762 + attribute \src "issuer_ls180.v:127375.7-127375.45" + wire $1\alu_logical0_logical_op__rc__rc[0:0] + attribute \src "issuer_ls180.v:128001.3-128039.6" + wire $1\alu_logical0_logical_op__write_cr0$next[0:0]$5763 + attribute \src "issuer_ls180.v:127379.7-127379.48" + wire $1\alu_logical0_logical_op__write_cr0[0:0] + attribute \src "issuer_ls180.v:128001.3-128039.6" + wire $1\alu_logical0_logical_op__zero_a$next[0:0]$5764 + attribute \src "issuer_ls180.v:127383.7-127383.45" + wire $1\alu_logical0_logical_op__zero_a[0:0] + attribute \src "issuer_ls180.v:128114.3-128122.6" + wire $1\alui_l_r_alui$next[0:0]$5798 + attribute \src "issuer_ls180.v:127409.7-127409.27" + wire $1\alui_l_r_alui[0:0] + attribute \src "issuer_ls180.v:128040.3-128061.6" + wire width 64 $1\data_r0__o$next[63:0]$5774 + attribute \src "issuer_ls180.v:127443.14-127443.47" + wire width 64 $1\data_r0__o[63:0] + attribute \src "issuer_ls180.v:128040.3-128061.6" + wire $1\data_r0__o_ok$next[0:0]$5775 + attribute \src "issuer_ls180.v:127447.7-127447.27" + wire $1\data_r0__o_ok[0:0] + attribute \src "issuer_ls180.v:128062.3-128083.6" + wire width 4 $1\data_r1__cr_a$next[3:0]$5782 + attribute \src "issuer_ls180.v:127451.13-127451.33" + wire width 4 $1\data_r1__cr_a[3:0] + attribute \src "issuer_ls180.v:128062.3-128083.6" + wire $1\data_r1__cr_a_ok$next[0:0]$5783 + attribute \src "issuer_ls180.v:127455.7-127455.30" + wire $1\data_r1__cr_a_ok[0:0] + attribute \src "issuer_ls180.v:128132.3-128141.6" + wire width 64 $1\dest1_o[63:0] + attribute \src "issuer_ls180.v:128142.3-128151.6" + wire width 4 $1\dest2_o[3:0] + attribute \src "issuer_ls180.v:127956.3-127964.6" + wire $1\opc_l_r_opc$next[0:0]$5715 + attribute \src "issuer_ls180.v:127469.7-127469.25" + wire $1\opc_l_r_opc[0:0] + attribute \src "issuer_ls180.v:127947.3-127955.6" + wire $1\opc_l_s_opc$next[0:0]$5712 + attribute \src "issuer_ls180.v:127473.7-127473.25" + wire $1\opc_l_s_opc[0:0] + attribute \src "issuer_ls180.v:128152.3-128160.6" + wire width 2 $1\prev_wr_go$next[1:0]$5806 + attribute \src "issuer_ls180.v:127604.13-127604.30" + wire width 2 $1\prev_wr_go[1:0] + attribute \src "issuer_ls180.v:127901.3-127910.6" + wire $1\req_done[0:0] + attribute \src "issuer_ls180.v:127992.3-128000.6" + wire width 2 $1\req_l_r_req$next[1:0]$5727 + attribute \src "issuer_ls180.v:127612.13-127612.31" + wire width 2 $1\req_l_r_req[1:0] + attribute \src "issuer_ls180.v:127983.3-127991.6" + wire width 2 $1\req_l_s_req$next[1:0]$5724 + attribute \src "issuer_ls180.v:127616.13-127616.31" + wire width 2 $1\req_l_s_req[1:0] + attribute \src "issuer_ls180.v:127920.3-127928.6" + wire $1\rok_l_r_rdok$next[0:0]$5703 + attribute \src "issuer_ls180.v:127628.7-127628.26" + wire $1\rok_l_r_rdok[0:0] + attribute \src "issuer_ls180.v:127911.3-127919.6" + wire $1\rok_l_s_rdok$next[0:0]$5700 + attribute \src "issuer_ls180.v:127632.7-127632.26" + wire $1\rok_l_s_rdok[0:0] + attribute \src "issuer_ls180.v:127938.3-127946.6" + wire $1\rst_l_r_rst$next[0:0]$5709 + attribute \src "issuer_ls180.v:127636.7-127636.25" + wire $1\rst_l_r_rst[0:0] + attribute \src "issuer_ls180.v:127929.3-127937.6" + wire $1\rst_l_s_rst$next[0:0]$5706 + attribute \src "issuer_ls180.v:127640.7-127640.25" + wire $1\rst_l_s_rst[0:0] + attribute \src "issuer_ls180.v:127974.3-127982.6" + wire width 3 $1\src_l_r_src$next[2:0]$5721 + attribute \src "issuer_ls180.v:127654.13-127654.31" + wire width 3 $1\src_l_r_src[2:0] + attribute \src "issuer_ls180.v:127965.3-127973.6" + wire width 3 $1\src_l_s_src$next[2:0]$5718 + attribute \src "issuer_ls180.v:127658.13-127658.31" + wire width 3 $1\src_l_s_src[2:0] + attribute \src "issuer_ls180.v:128084.3-128093.6" + wire width 64 $1\src_r0$next[63:0]$5789 + attribute \src "issuer_ls180.v:127666.14-127666.43" + wire width 64 $1\src_r0[63:0] + attribute \src "issuer_ls180.v:128094.3-128103.6" + wire width 64 $1\src_r1$next[63:0]$5792 + attribute \src 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"OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute 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"OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \alu_logical0_logical_op__insn_type + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \alu_logical0_logical_op__insn_type$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_logical0_logical_op__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_logical0_logical_op__invert_in$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_logical0_logical_op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_logical0_logical_op__invert_out$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_logical0_logical_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_logical0_logical_op__is_32bit$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_logical0_logical_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_logical0_logical_op__is_signed$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_logical0_logical_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_logical0_logical_op__oe__oe$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_logical0_logical_op__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_logical0_logical_op__oe__ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_logical0_logical_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_logical0_logical_op__output_carry$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_logical0_logical_op__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_logical0_logical_op__rc__ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_logical0_logical_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_logical0_logical_op__rc__rc$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_logical0_logical_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_logical0_logical_op__write_cr0$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_logical0_logical_op__zero_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_logical0_logical_op__zero_a$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" + wire \alu_logical0_n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" + wire \alu_logical0_n_valid_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 \alu_logical0_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" + wire \alu_logical0_p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" + wire \alu_logical0_p_valid_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \alu_logical0_ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \alu_logical0_rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire \alu_logical0_xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:197" + wire \alu_pulse + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:198" + wire width 2 \alu_pulsem + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire \alui_l_q_alui + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire \alui_l_r_alui + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire \alui_l_r_alui$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire \alui_l_s_alui + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" + wire input 34 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" + wire input 33 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 31 \cr_a_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107" + wire output 20 \cu_busy_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:108" + wire \cu_done_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:104" + wire \cu_go_die_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:100" + wire input 19 \cu_issue_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 3 input 23 \cu_rd__go_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 3 output 22 \cu_rd__rel_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96" + wire width 3 input 21 \cu_rdmaskn_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:102" + wire \cu_shadown_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 2 input 29 \cu_wr__go_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" + wire width 2 output 28 \cu_wr__rel_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:97" + wire width 2 \cu_wrmask_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire width 64 \data_r0__o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire width 64 \data_r0__o$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire \data_r0__o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire \data_r0__o_ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire width 4 \data_r1__cr_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire width 4 \data_r1__cr_a$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire \data_r1__cr_a_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" + wire \data_r1__cr_a_ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 64 output 30 \dest1_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" + wire width 4 output 32 \dest2_o + attribute \src "issuer_ls180.v:127080.7-127080.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 27 \o_ok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire \opc_l_q_opc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire \opc_l_r_opc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire \opc_l_r_opc$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire \opc_l_s_opc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire \opc_l_s_opc$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 input 17 \oper_i_alu_logical0__data_len + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 input 2 \oper_i_alu_logical0__fn_unit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 input 3 \oper_i_alu_logical0__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 4 \oper_i_alu_logical0__imm_data__ok + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 input 11 \oper_i_alu_logical0__input_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 18 \oper_i_alu_logical0__insn + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 input 1 \oper_i_alu_logical0__insn_type + attribute \src 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"/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" + cell $not $not$issuer_ls180.v:127713$5630 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \cu_rd__rel_o + connect \Y $not$issuer_ls180.v:127713$5630_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:173" + cell $not $not$issuer_ls180.v:127738$5655 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \alu_logical0_logical_op__zero_a + connect \Y $not$issuer_ls180.v:127738$5655_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:173" + cell $not $not$issuer_ls180.v:127739$5656 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \alu_logical0_logical_op__imm_data__ok + connect \Y $not$issuer_ls180.v:127739$5656_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" + cell $or $or$issuer_ls180.v:127706$5623 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$31 + connect \B \$33 + connect \Y $or$issuer_ls180.v:127706$5623_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:230" + cell $or $or$issuer_ls180.v:127717$5634 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \req_done + connect \B \cu_go_die_i + connect \Y $or$issuer_ls180.v:127717$5634_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:231" + cell $or $or$issuer_ls180.v:127718$5635 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cu_issue_i + connect \B \cu_go_die_i + connect \Y $or$issuer_ls180.v:127718$5635_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:232" + cell $or $or$issuer_ls180.v:127719$5636 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 2 + connect \A \cu_wr__go_i + connect \B { \cu_go_die_i \cu_go_die_i } + connect \Y $or$issuer_ls180.v:127719$5636_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:233" + cell $or $or$issuer_ls180.v:127720$5637 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \cu_rd__go_i + connect \B { \cu_go_die_i \cu_go_die_i \cu_go_die_i } + connect \Y $or$issuer_ls180.v:127720$5637_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:253" + cell $or $or$issuer_ls180.v:127723$5640 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 2 + connect \A \reset_w + connect \B \prev_wr_go + connect \Y $or$issuer_ls180.v:127723$5640_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" + cell $or $or$issuer_ls180.v:127724$5641 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \$4 + connect \B \cu_rd__go_i + connect \Y $or$issuer_ls180.v:127724$5641_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" + cell $reduce_and $reduce_and$issuer_ls180.v:127730$5647 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \$6 + connect \Y $reduce_and$issuer_ls180.v:127730$5647_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" + cell $reduce_or $reduce_or$issuer_ls180.v:127701$5618 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \$25 + connect \Y $reduce_or$issuer_ls180.v:127701$5618_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" + cell $reduce_or $reduce_or$issuer_ls180.v:127704$5621 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \cu_wr__go_i + connect \Y $reduce_or$issuer_ls180.v:127704$5621_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" + cell $reduce_or $reduce_or$issuer_ls180.v:127705$5622 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \prev_wr_go + connect \Y $reduce_or$issuer_ls180.v:127705$5622_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:168" + cell $mux $ternary$issuer_ls180.v:127727$5644 + parameter \WIDTH 1 + connect \A \src_l_q_src [0] + connect \B \opc_l_q_opc + connect \S \alu_logical0_logical_op__zero_a + connect \Y $ternary$issuer_ls180.v:127727$5644_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:169" + cell $mux $ternary$issuer_ls180.v:127728$5645 + parameter \WIDTH 64 + connect \A \src1_i + connect \B 64'0000000000000000000000000000000000000000000000000000000000000000 + connect \S \alu_logical0_logical_op__zero_a + connect \Y $ternary$issuer_ls180.v:127728$5645_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:168" + cell $mux $ternary$issuer_ls180.v:127729$5646 + parameter \WIDTH 1 + connect \A \src_l_q_src [1] + connect \B \opc_l_q_opc + connect \S \alu_logical0_logical_op__imm_data__ok + connect \Y $ternary$issuer_ls180.v:127729$5646_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:169" + cell $mux $ternary$issuer_ls180.v:127731$5648 + parameter \WIDTH 64 + connect \A \src2_i + connect \B \alu_logical0_logical_op__imm_data__data + connect \S \alu_logical0_logical_op__imm_data__ok + connect \Y $ternary$issuer_ls180.v:127731$5648_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + cell $mux $ternary$issuer_ls180.v:127732$5649 + parameter \WIDTH 64 + connect \A \src_r0 + connect \B \src_or_imm + connect \S \src_sel + connect \Y $ternary$issuer_ls180.v:127732$5649_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + cell $mux $ternary$issuer_ls180.v:127733$5650 + parameter \WIDTH 64 + connect \A \src_r1 + connect \B \src_or_imm$80 + connect \S \src_sel$77 + connect \Y $ternary$issuer_ls180.v:127733$5650_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + cell $mux $ternary$issuer_ls180.v:127734$5651 + parameter \WIDTH 1 + connect \A \src_r2 + connect \B \src3_i + connect \S \src_l_q_src [2] + connect \Y $ternary$issuer_ls180.v:127734$5651_Y + end + attribute \module_not_derived 1 + attribute \src "issuer_ls180.v:127820.14-127826.4" + cell \alu_l$58 \alu_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_alu \alu_l_q_alu + connect \r_alu \alu_l_r_alu + connect \s_alu \alu_l_s_alu + end + attribute \module_not_derived 1 + attribute \src "issuer_ls180.v:127827.16-127859.4" + cell \alu_logical0 \alu_logical0 + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \cr_a \alu_logical0_cr_a + connect \cr_a_ok \cr_a_ok + connect \logical_op__data_len \alu_logical0_logical_op__data_len + connect \logical_op__fn_unit \alu_logical0_logical_op__fn_unit + connect \logical_op__imm_data__data \alu_logical0_logical_op__imm_data__data + connect \logical_op__imm_data__ok \alu_logical0_logical_op__imm_data__ok + connect \logical_op__input_carry \alu_logical0_logical_op__input_carry + connect \logical_op__insn \alu_logical0_logical_op__insn + connect \logical_op__insn_type \alu_logical0_logical_op__insn_type + connect \logical_op__invert_in \alu_logical0_logical_op__invert_in + connect \logical_op__invert_out \alu_logical0_logical_op__invert_out + connect \logical_op__is_32bit \alu_logical0_logical_op__is_32bit + connect \logical_op__is_signed \alu_logical0_logical_op__is_signed + connect \logical_op__oe__oe \alu_logical0_logical_op__oe__oe + connect \logical_op__oe__ok \alu_logical0_logical_op__oe__ok + connect \logical_op__output_carry \alu_logical0_logical_op__output_carry + connect \logical_op__rc__ok \alu_logical0_logical_op__rc__ok + connect \logical_op__rc__rc \alu_logical0_logical_op__rc__rc + connect \logical_op__write_cr0 \alu_logical0_logical_op__write_cr0 + connect \logical_op__zero_a \alu_logical0_logical_op__zero_a + connect \n_ready_i \alu_logical0_n_ready_i + connect \n_valid_o \alu_logical0_n_valid_o + connect \o \alu_logical0_o + connect \o_ok \o_ok + connect \p_ready_o \alu_logical0_p_ready_o + connect \p_valid_i \alu_logical0_p_valid_i + connect \ra \alu_logical0_ra + connect \rb \alu_logical0_rb + connect \xer_so \alu_logical0_xer_so + end + attribute \module_not_derived 1 + attribute \src "issuer_ls180.v:127860.15-127866.4" + cell \alui_l$57 \alui_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_alui \alui_l_q_alui + connect \r_alui \alui_l_r_alui + connect \s_alui \alui_l_s_alui + end + attribute \module_not_derived 1 + attribute \src "issuer_ls180.v:127867.14-127873.4" + cell \opc_l$53 \opc_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_opc \opc_l_q_opc + connect \r_opc \opc_l_r_opc + connect \s_opc \opc_l_s_opc + end + attribute \module_not_derived 1 + attribute \src "issuer_ls180.v:127874.14-127880.4" + cell \req_l$54 \req_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_req \req_l_q_req + connect \r_req \req_l_r_req + connect \s_req \req_l_s_req + end + attribute \module_not_derived 1 + attribute \src "issuer_ls180.v:127881.14-127887.4" + cell \rok_l$56 \rok_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_rdok \rok_l_q_rdok + connect \r_rdok \rok_l_r_rdok + connect \s_rdok \rok_l_s_rdok + end + attribute \module_not_derived 1 + attribute \src "issuer_ls180.v:127888.14-127893.4" + cell \rst_l$55 \rst_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \r_rst \rst_l_r_rst + connect \s_rst \rst_l_s_rst + end + attribute \module_not_derived 1 + attribute \src "issuer_ls180.v:127894.14-127900.4" + cell \src_l$52 \src_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_src \src_l_q_src + connect \r_src \src_l_r_src + connect \s_src \src_l_s_src + end + attribute \src "issuer_ls180.v:127080.7-127080.20" + process $proc$issuer_ls180.v:127080$5807 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "issuer_ls180.v:127198.7-127198.24" + process $proc$issuer_ls180.v:127198$5808 + assign { } { } + assign $1\all_rd_dly[0:0] 1'0 + sync always + sync init + update \all_rd_dly $1\all_rd_dly[0:0] + end + attribute \src "issuer_ls180.v:127208.7-127208.26" + process $proc$issuer_ls180.v:127208$5809 + assign { } { } + assign $1\alu_done_dly[0:0] 1'0 + sync always + sync init + update \alu_done_dly $1\alu_done_dly[0:0] + end + attribute \src "issuer_ls180.v:127216.7-127216.25" + process $proc$issuer_ls180.v:127216$5810 + assign { } { } + assign $1\alu_l_r_alu[0:0] 1'1 + sync always + sync init + update \alu_l_r_alu $1\alu_l_r_alu[0:0] + end + attribute \src "issuer_ls180.v:127224.13-127224.53" + process $proc$issuer_ls180.v:127224$5811 + assign { } { } + assign $1\alu_logical0_logical_op__data_len[3:0] 4'0000 + sync always + sync init + update \alu_logical0_logical_op__data_len $1\alu_logical0_logical_op__data_len[3:0] + end + attribute \src "issuer_ls180.v:127241.14-127241.56" + process $proc$issuer_ls180.v:127241$5812 + assign { } { } + assign $1\alu_logical0_logical_op__fn_unit[11:0] 12'000000000000 + sync always + sync init + update \alu_logical0_logical_op__fn_unit $1\alu_logical0_logical_op__fn_unit[11:0] + end + attribute \src "issuer_ls180.v:127245.14-127245.76" + process $proc$issuer_ls180.v:127245$5813 + assign { } { } + assign $1\alu_logical0_logical_op__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \alu_logical0_logical_op__imm_data__data $1\alu_logical0_logical_op__imm_data__data[63:0] + end + attribute \src "issuer_ls180.v:127249.7-127249.51" + process $proc$issuer_ls180.v:127249$5814 + assign { } { } + assign $1\alu_logical0_logical_op__imm_data__ok[0:0] 1'0 + sync always + sync init + update \alu_logical0_logical_op__imm_data__ok $1\alu_logical0_logical_op__imm_data__ok[0:0] + end + attribute \src "issuer_ls180.v:127257.13-127257.56" + process $proc$issuer_ls180.v:127257$5815 + assign { } { } + assign $1\alu_logical0_logical_op__input_carry[1:0] 2'00 + sync always + sync init + update \alu_logical0_logical_op__input_carry $1\alu_logical0_logical_op__input_carry[1:0] + end + attribute \src "issuer_ls180.v:127261.14-127261.51" + process $proc$issuer_ls180.v:127261$5816 + assign { } { } + assign $1\alu_logical0_logical_op__insn[31:0] 0 + sync always + sync init + update \alu_logical0_logical_op__insn $1\alu_logical0_logical_op__insn[31:0] + end + attribute \src "issuer_ls180.v:127339.13-127339.55" + process $proc$issuer_ls180.v:127339$5817 + assign { } { } + assign $1\alu_logical0_logical_op__insn_type[6:0] 7'0000000 + sync always + sync init + update \alu_logical0_logical_op__insn_type $1\alu_logical0_logical_op__insn_type[6:0] + end + attribute \src "issuer_ls180.v:127343.7-127343.48" + process $proc$issuer_ls180.v:127343$5818 + assign { } { } + assign $1\alu_logical0_logical_op__invert_in[0:0] 1'0 + sync always + sync init + update \alu_logical0_logical_op__invert_in $1\alu_logical0_logical_op__invert_in[0:0] + end + attribute \src "issuer_ls180.v:127347.7-127347.49" + process $proc$issuer_ls180.v:127347$5819 + assign { } { } + assign $1\alu_logical0_logical_op__invert_out[0:0] 1'0 + sync always + sync init + update \alu_logical0_logical_op__invert_out $1\alu_logical0_logical_op__invert_out[0:0] + end + attribute \src "issuer_ls180.v:127351.7-127351.47" + process $proc$issuer_ls180.v:127351$5820 + assign { } { } + assign $1\alu_logical0_logical_op__is_32bit[0:0] 1'0 + sync always + sync init + update \alu_logical0_logical_op__is_32bit $1\alu_logical0_logical_op__is_32bit[0:0] + end + attribute \src "issuer_ls180.v:127355.7-127355.48" + process $proc$issuer_ls180.v:127355$5821 + assign { } { } + assign $1\alu_logical0_logical_op__is_signed[0:0] 1'0 + sync always + sync init + update \alu_logical0_logical_op__is_signed $1\alu_logical0_logical_op__is_signed[0:0] + end + attribute \src "issuer_ls180.v:127359.7-127359.45" + process $proc$issuer_ls180.v:127359$5822 + assign { } { } + assign $1\alu_logical0_logical_op__oe__oe[0:0] 1'0 + sync always + sync init + update \alu_logical0_logical_op__oe__oe $1\alu_logical0_logical_op__oe__oe[0:0] + end + attribute \src "issuer_ls180.v:127363.7-127363.45" + process $proc$issuer_ls180.v:127363$5823 + assign { } { } + assign $1\alu_logical0_logical_op__oe__ok[0:0] 1'0 + sync always + sync init + update \alu_logical0_logical_op__oe__ok $1\alu_logical0_logical_op__oe__ok[0:0] + end + attribute \src "issuer_ls180.v:127367.7-127367.51" + process $proc$issuer_ls180.v:127367$5824 + assign { } { } + assign $1\alu_logical0_logical_op__output_carry[0:0] 1'0 + sync always + sync init + update \alu_logical0_logical_op__output_carry $1\alu_logical0_logical_op__output_carry[0:0] + end + attribute \src "issuer_ls180.v:127371.7-127371.45" + process $proc$issuer_ls180.v:127371$5825 + assign { } { } + assign $1\alu_logical0_logical_op__rc__ok[0:0] 1'0 + sync always + sync init + update \alu_logical0_logical_op__rc__ok $1\alu_logical0_logical_op__rc__ok[0:0] + end + attribute \src "issuer_ls180.v:127375.7-127375.45" + process $proc$issuer_ls180.v:127375$5826 + assign { } { } + assign $1\alu_logical0_logical_op__rc__rc[0:0] 1'0 + sync always + sync init + update \alu_logical0_logical_op__rc__rc $1\alu_logical0_logical_op__rc__rc[0:0] + end + attribute \src "issuer_ls180.v:127379.7-127379.48" + process $proc$issuer_ls180.v:127379$5827 + assign { } { } + assign $1\alu_logical0_logical_op__write_cr0[0:0] 1'0 + sync always + sync init + update \alu_logical0_logical_op__write_cr0 $1\alu_logical0_logical_op__write_cr0[0:0] + end + attribute \src "issuer_ls180.v:127383.7-127383.45" + process $proc$issuer_ls180.v:127383$5828 + assign { } { } + assign $1\alu_logical0_logical_op__zero_a[0:0] 1'0 + sync always + sync init + update \alu_logical0_logical_op__zero_a $1\alu_logical0_logical_op__zero_a[0:0] + end + attribute \src "issuer_ls180.v:127409.7-127409.27" + process $proc$issuer_ls180.v:127409$5829 + assign { } { } + assign $1\alui_l_r_alui[0:0] 1'1 + sync always + sync init + update \alui_l_r_alui $1\alui_l_r_alui[0:0] + end + attribute \src "issuer_ls180.v:127443.14-127443.47" + process $proc$issuer_ls180.v:127443$5830 + assign { } { } + assign $1\data_r0__o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \data_r0__o $1\data_r0__o[63:0] + end + attribute \src "issuer_ls180.v:127447.7-127447.27" + process $proc$issuer_ls180.v:127447$5831 + assign { } { } + assign $1\data_r0__o_ok[0:0] 1'0 + sync always + sync init + update \data_r0__o_ok $1\data_r0__o_ok[0:0] + end + attribute \src "issuer_ls180.v:127451.13-127451.33" + process $proc$issuer_ls180.v:127451$5832 + assign { } { } + assign $1\data_r1__cr_a[3:0] 4'0000 + sync always + sync init + update \data_r1__cr_a $1\data_r1__cr_a[3:0] + end + attribute \src "issuer_ls180.v:127455.7-127455.30" + process $proc$issuer_ls180.v:127455$5833 + assign { } { } + assign $1\data_r1__cr_a_ok[0:0] 1'0 + sync always + sync init + update \data_r1__cr_a_ok $1\data_r1__cr_a_ok[0:0] + end + attribute \src "issuer_ls180.v:127469.7-127469.25" + process $proc$issuer_ls180.v:127469$5834 + assign { } { } + assign $1\opc_l_r_opc[0:0] 1'1 + sync always + sync init + update \opc_l_r_opc $1\opc_l_r_opc[0:0] + end + attribute \src "issuer_ls180.v:127473.7-127473.25" + process $proc$issuer_ls180.v:127473$5835 + assign { } { } + assign $1\opc_l_s_opc[0:0] 1'0 + sync always + sync init + update \opc_l_s_opc $1\opc_l_s_opc[0:0] + end + attribute \src "issuer_ls180.v:127604.13-127604.30" + process $proc$issuer_ls180.v:127604$5836 + assign { } { } + assign $1\prev_wr_go[1:0] 2'00 + sync always + sync init + update \prev_wr_go $1\prev_wr_go[1:0] + end + attribute \src "issuer_ls180.v:127612.13-127612.31" + process $proc$issuer_ls180.v:127612$5837 + assign { } { } + assign $1\req_l_r_req[1:0] 2'11 + sync always + sync init + update \req_l_r_req $1\req_l_r_req[1:0] + end + attribute \src "issuer_ls180.v:127616.13-127616.31" + process $proc$issuer_ls180.v:127616$5838 + assign { } { } + assign $1\req_l_s_req[1:0] 2'00 + sync always + sync init + update \req_l_s_req $1\req_l_s_req[1:0] + end + attribute \src "issuer_ls180.v:127628.7-127628.26" + process $proc$issuer_ls180.v:127628$5839 + assign { } { } + assign $1\rok_l_r_rdok[0:0] 1'1 + sync always + sync init + update \rok_l_r_rdok $1\rok_l_r_rdok[0:0] + end + attribute \src "issuer_ls180.v:127632.7-127632.26" + process $proc$issuer_ls180.v:127632$5840 + assign { } { } + assign $1\rok_l_s_rdok[0:0] 1'0 + sync always + sync init + update \rok_l_s_rdok $1\rok_l_s_rdok[0:0] + end + attribute \src "issuer_ls180.v:127636.7-127636.25" + process $proc$issuer_ls180.v:127636$5841 + assign { } { } + assign $1\rst_l_r_rst[0:0] 1'1 + sync always + sync init + update \rst_l_r_rst $1\rst_l_r_rst[0:0] + end + attribute \src "issuer_ls180.v:127640.7-127640.25" + process $proc$issuer_ls180.v:127640$5842 + assign { } { } + assign $1\rst_l_s_rst[0:0] 1'0 + sync always + sync init + update \rst_l_s_rst $1\rst_l_s_rst[0:0] + end + attribute \src "issuer_ls180.v:127654.13-127654.31" + process $proc$issuer_ls180.v:127654$5843 + assign { } { } + assign $1\src_l_r_src[2:0] 3'111 + sync always + sync init + update \src_l_r_src $1\src_l_r_src[2:0] + end + attribute \src "issuer_ls180.v:127658.13-127658.31" + process $proc$issuer_ls180.v:127658$5844 + assign { } { } + assign $1\src_l_s_src[2:0] 3'000 + sync always + sync init + update \src_l_s_src $1\src_l_s_src[2:0] + end + attribute \src "issuer_ls180.v:127666.14-127666.43" + process $proc$issuer_ls180.v:127666$5845 + assign { } { } + assign $1\src_r0[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \src_r0 $1\src_r0[63:0] + end + attribute \src "issuer_ls180.v:127670.14-127670.43" + process $proc$issuer_ls180.v:127670$5846 + assign { } { } + assign $1\src_r1[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \src_r1 $1\src_r1[63:0] + end + attribute \src "issuer_ls180.v:127674.7-127674.20" + process $proc$issuer_ls180.v:127674$5847 + assign { } { } + assign $1\src_r2[0:0] 1'0 + sync always + sync init + update \src_r2 $1\src_r2[0:0] + end + attribute \src "issuer_ls180.v:127740.3-127741.39" + process $proc$issuer_ls180.v:127740$5657 + assign { } { } + assign $0\alu_l_r_alu[0:0] \alu_l_r_alu$next + sync posedge \coresync_clk + update \alu_l_r_alu $0\alu_l_r_alu[0:0] + end + attribute \src "issuer_ls180.v:127742.3-127743.43" + process $proc$issuer_ls180.v:127742$5658 + assign { } { } + assign $0\alui_l_r_alui[0:0] \alui_l_r_alui$next + sync posedge \coresync_clk + update \alui_l_r_alui $0\alui_l_r_alui[0:0] + end + attribute \src "issuer_ls180.v:127744.3-127745.29" + process $proc$issuer_ls180.v:127744$5659 + assign { } { } + assign $0\src_r2[0:0] \src_r2$next + sync posedge \coresync_clk + update \src_r2 $0\src_r2[0:0] + end + attribute \src "issuer_ls180.v:127746.3-127747.29" + process $proc$issuer_ls180.v:127746$5660 + assign { } { } + assign $0\src_r1[63:0] \src_r1$next + sync posedge \coresync_clk + update \src_r1 $0\src_r1[63:0] + end + attribute \src "issuer_ls180.v:127748.3-127749.29" + process $proc$issuer_ls180.v:127748$5661 + assign { } { } + assign $0\src_r0[63:0] \src_r0$next + sync posedge \coresync_clk + update \src_r0 $0\src_r0[63:0] + end + attribute \src "issuer_ls180.v:127750.3-127751.43" + process $proc$issuer_ls180.v:127750$5662 + assign { } { } + assign $0\data_r1__cr_a[3:0] \data_r1__cr_a$next + sync posedge \coresync_clk + update \data_r1__cr_a $0\data_r1__cr_a[3:0] + end + attribute \src "issuer_ls180.v:127752.3-127753.49" + process $proc$issuer_ls180.v:127752$5663 + assign { } { } + assign $0\data_r1__cr_a_ok[0:0] \data_r1__cr_a_ok$next + sync posedge \coresync_clk + update \data_r1__cr_a_ok $0\data_r1__cr_a_ok[0:0] + end + attribute \src "issuer_ls180.v:127754.3-127755.37" + process $proc$issuer_ls180.v:127754$5664 + assign { } { } + assign $0\data_r0__o[63:0] \data_r0__o$next + sync posedge \coresync_clk + update \data_r0__o $0\data_r0__o[63:0] + end + attribute \src "issuer_ls180.v:127756.3-127757.43" + process $proc$issuer_ls180.v:127756$5665 + assign { } { } + assign $0\data_r0__o_ok[0:0] \data_r0__o_ok$next + sync posedge \coresync_clk + update \data_r0__o_ok $0\data_r0__o_ok[0:0] + end + attribute \src "issuer_ls180.v:127758.3-127759.85" + process $proc$issuer_ls180.v:127758$5666 + assign { } { } + assign $0\alu_logical0_logical_op__insn_type[6:0] \alu_logical0_logical_op__insn_type$next + sync posedge \coresync_clk + update \alu_logical0_logical_op__insn_type $0\alu_logical0_logical_op__insn_type[6:0] + end + attribute \src "issuer_ls180.v:127760.3-127761.81" + process $proc$issuer_ls180.v:127760$5667 + assign { } { } + assign $0\alu_logical0_logical_op__fn_unit[11:0] \alu_logical0_logical_op__fn_unit$next + sync posedge \coresync_clk + update \alu_logical0_logical_op__fn_unit $0\alu_logical0_logical_op__fn_unit[11:0] + end + attribute \src "issuer_ls180.v:127762.3-127763.95" + process $proc$issuer_ls180.v:127762$5668 + assign { } { } + assign $0\alu_logical0_logical_op__imm_data__data[63:0] \alu_logical0_logical_op__imm_data__data$next + sync posedge \coresync_clk + update \alu_logical0_logical_op__imm_data__data $0\alu_logical0_logical_op__imm_data__data[63:0] + end + attribute \src "issuer_ls180.v:127764.3-127765.91" + process $proc$issuer_ls180.v:127764$5669 + assign { } { } + assign $0\alu_logical0_logical_op__imm_data__ok[0:0] \alu_logical0_logical_op__imm_data__ok$next + sync posedge \coresync_clk + update \alu_logical0_logical_op__imm_data__ok $0\alu_logical0_logical_op__imm_data__ok[0:0] + end + attribute \src "issuer_ls180.v:127766.3-127767.79" + process $proc$issuer_ls180.v:127766$5670 + assign { } { } + assign $0\alu_logical0_logical_op__rc__rc[0:0] \alu_logical0_logical_op__rc__rc$next + sync posedge \coresync_clk + update \alu_logical0_logical_op__rc__rc $0\alu_logical0_logical_op__rc__rc[0:0] + end + attribute \src "issuer_ls180.v:127768.3-127769.79" + process $proc$issuer_ls180.v:127768$5671 + assign { } { } + assign $0\alu_logical0_logical_op__rc__ok[0:0] \alu_logical0_logical_op__rc__ok$next + sync posedge \coresync_clk + update \alu_logical0_logical_op__rc__ok $0\alu_logical0_logical_op__rc__ok[0:0] + end + attribute \src "issuer_ls180.v:127770.3-127771.79" + process $proc$issuer_ls180.v:127770$5672 + assign { } { } + assign $0\alu_logical0_logical_op__oe__oe[0:0] \alu_logical0_logical_op__oe__oe$next + sync posedge \coresync_clk + update \alu_logical0_logical_op__oe__oe $0\alu_logical0_logical_op__oe__oe[0:0] + end + attribute \src "issuer_ls180.v:127772.3-127773.79" + process $proc$issuer_ls180.v:127772$5673 + assign { } { } + assign $0\alu_logical0_logical_op__oe__ok[0:0] \alu_logical0_logical_op__oe__ok$next + sync posedge \coresync_clk + update \alu_logical0_logical_op__oe__ok $0\alu_logical0_logical_op__oe__ok[0:0] + end + attribute \src "issuer_ls180.v:127774.3-127775.85" + process $proc$issuer_ls180.v:127774$5674 + assign { } { } + assign $0\alu_logical0_logical_op__invert_in[0:0] \alu_logical0_logical_op__invert_in$next + sync posedge \coresync_clk + update \alu_logical0_logical_op__invert_in $0\alu_logical0_logical_op__invert_in[0:0] + end + attribute \src "issuer_ls180.v:127776.3-127777.79" + process $proc$issuer_ls180.v:127776$5675 + assign { } { } + assign $0\alu_logical0_logical_op__zero_a[0:0] \alu_logical0_logical_op__zero_a$next + sync posedge \coresync_clk + update \alu_logical0_logical_op__zero_a $0\alu_logical0_logical_op__zero_a[0:0] + end + attribute \src "issuer_ls180.v:127778.3-127779.89" + process $proc$issuer_ls180.v:127778$5676 + assign { } { } + assign $0\alu_logical0_logical_op__input_carry[1:0] \alu_logical0_logical_op__input_carry$next + sync posedge \coresync_clk + update \alu_logical0_logical_op__input_carry $0\alu_logical0_logical_op__input_carry[1:0] + end + attribute \src "issuer_ls180.v:127780.3-127781.87" + process $proc$issuer_ls180.v:127780$5677 + assign { } { } + assign $0\alu_logical0_logical_op__invert_out[0:0] \alu_logical0_logical_op__invert_out$next + sync posedge \coresync_clk + update \alu_logical0_logical_op__invert_out $0\alu_logical0_logical_op__invert_out[0:0] + end + attribute \src "issuer_ls180.v:127782.3-127783.85" + process $proc$issuer_ls180.v:127782$5678 + assign { } { } + assign $0\alu_logical0_logical_op__write_cr0[0:0] \alu_logical0_logical_op__write_cr0$next + sync posedge \coresync_clk + update \alu_logical0_logical_op__write_cr0 $0\alu_logical0_logical_op__write_cr0[0:0] + end + attribute \src "issuer_ls180.v:127784.3-127785.91" + process $proc$issuer_ls180.v:127784$5679 + assign { } { } + assign $0\alu_logical0_logical_op__output_carry[0:0] \alu_logical0_logical_op__output_carry$next + sync posedge \coresync_clk + update \alu_logical0_logical_op__output_carry $0\alu_logical0_logical_op__output_carry[0:0] + end + attribute \src "issuer_ls180.v:127786.3-127787.83" + process $proc$issuer_ls180.v:127786$5680 + assign { } { } + assign $0\alu_logical0_logical_op__is_32bit[0:0] \alu_logical0_logical_op__is_32bit$next + sync posedge \coresync_clk + update \alu_logical0_logical_op__is_32bit $0\alu_logical0_logical_op__is_32bit[0:0] + end + attribute \src "issuer_ls180.v:127788.3-127789.85" + process $proc$issuer_ls180.v:127788$5681 + assign { } { } + assign $0\alu_logical0_logical_op__is_signed[0:0] \alu_logical0_logical_op__is_signed$next + sync posedge \coresync_clk + update \alu_logical0_logical_op__is_signed $0\alu_logical0_logical_op__is_signed[0:0] + end + attribute \src "issuer_ls180.v:127790.3-127791.83" + process $proc$issuer_ls180.v:127790$5682 + assign { } { } + assign $0\alu_logical0_logical_op__data_len[3:0] \alu_logical0_logical_op__data_len$next + sync posedge \coresync_clk + update \alu_logical0_logical_op__data_len $0\alu_logical0_logical_op__data_len[3:0] + end + attribute \src "issuer_ls180.v:127792.3-127793.75" + process $proc$issuer_ls180.v:127792$5683 + assign { } { } + assign $0\alu_logical0_logical_op__insn[31:0] \alu_logical0_logical_op__insn$next + sync posedge \coresync_clk + update \alu_logical0_logical_op__insn $0\alu_logical0_logical_op__insn[31:0] + end + attribute \src "issuer_ls180.v:127794.3-127795.39" + process $proc$issuer_ls180.v:127794$5684 + assign { } { } + assign $0\req_l_r_req[1:0] \req_l_r_req$next + sync posedge \coresync_clk + update \req_l_r_req $0\req_l_r_req[1:0] + end + attribute \src "issuer_ls180.v:127796.3-127797.39" + process $proc$issuer_ls180.v:127796$5685 + assign { } { } + assign $0\req_l_s_req[1:0] \req_l_s_req$next + sync posedge \coresync_clk + update \req_l_s_req $0\req_l_s_req[1:0] + end + attribute \src "issuer_ls180.v:127798.3-127799.39" + process $proc$issuer_ls180.v:127798$5686 + assign { } { } + assign $0\src_l_r_src[2:0] \src_l_r_src$next + sync posedge \coresync_clk + update \src_l_r_src $0\src_l_r_src[2:0] + end + attribute \src "issuer_ls180.v:127800.3-127801.39" + process $proc$issuer_ls180.v:127800$5687 + assign { } { } + assign $0\src_l_s_src[2:0] \src_l_s_src$next + sync posedge \coresync_clk + update \src_l_s_src $0\src_l_s_src[2:0] + end + attribute \src "issuer_ls180.v:127802.3-127803.39" + process $proc$issuer_ls180.v:127802$5688 + assign { } { } + assign $0\opc_l_r_opc[0:0] \opc_l_r_opc$next + sync posedge \coresync_clk + update \opc_l_r_opc $0\opc_l_r_opc[0:0] + end + attribute \src "issuer_ls180.v:127804.3-127805.39" + process $proc$issuer_ls180.v:127804$5689 + assign { } { } + assign $0\opc_l_s_opc[0:0] \opc_l_s_opc$next + sync posedge \coresync_clk + update \opc_l_s_opc $0\opc_l_s_opc[0:0] + end + attribute \src "issuer_ls180.v:127806.3-127807.39" + process $proc$issuer_ls180.v:127806$5690 + assign { } { } + assign $0\rst_l_r_rst[0:0] \rst_l_r_rst$next + sync posedge \coresync_clk + update \rst_l_r_rst $0\rst_l_r_rst[0:0] + end + attribute \src "issuer_ls180.v:127808.3-127809.39" + process $proc$issuer_ls180.v:127808$5691 + assign { } { } + assign $0\rst_l_s_rst[0:0] \rst_l_s_rst$next + sync posedge \coresync_clk + update \rst_l_s_rst $0\rst_l_s_rst[0:0] + end + attribute \src "issuer_ls180.v:127810.3-127811.41" + process $proc$issuer_ls180.v:127810$5692 + assign { } { } + assign $0\rok_l_r_rdok[0:0] \rok_l_r_rdok$next + sync posedge \coresync_clk + update \rok_l_r_rdok $0\rok_l_r_rdok[0:0] + end + attribute \src "issuer_ls180.v:127812.3-127813.41" + process $proc$issuer_ls180.v:127812$5693 + assign { } { } + assign $0\rok_l_s_rdok[0:0] \rok_l_s_rdok$next + sync posedge \coresync_clk + update \rok_l_s_rdok $0\rok_l_s_rdok[0:0] + end + attribute \src "issuer_ls180.v:127814.3-127815.37" + process $proc$issuer_ls180.v:127814$5694 + assign { } { } + assign $0\prev_wr_go[1:0] \prev_wr_go$next + sync posedge \coresync_clk + update \prev_wr_go $0\prev_wr_go[1:0] + end + attribute \src "issuer_ls180.v:127816.3-127817.44" + process $proc$issuer_ls180.v:127816$5695 + assign { } { } + assign $0\alu_done_dly[0:0] \alu_logical0_n_valid_o + sync posedge \coresync_clk + update \alu_done_dly $0\alu_done_dly[0:0] + end + attribute \src "issuer_ls180.v:127818.3-127819.24" + process $proc$issuer_ls180.v:127818$5696 + assign { } { } + assign $0\all_rd_dly[0:0] \$9 + sync posedge \coresync_clk + update \all_rd_dly $0\all_rd_dly[0:0] + end + attribute \src "issuer_ls180.v:127901.3-127910.6" + process $proc$issuer_ls180.v:127901$5697 + assign { } { } + assign { } { } + assign $0\req_done[0:0] $1\req_done[0:0] + attribute \src "issuer_ls180.v:127902.5-127902.29" + switch \initial + attribute \src "issuer_ls180.v:127902.9-127902.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" + switch \$53 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\req_done[0:0] 1'1 + case + assign $1\req_done[0:0] \$45 + end + sync always + update \req_done $0\req_done[0:0] + end + attribute \src "issuer_ls180.v:127911.3-127919.6" + process $proc$issuer_ls180.v:127911$5698 + assign { } { } + assign { } { } + assign $0\rok_l_s_rdok$next[0:0]$5699 $1\rok_l_s_rdok$next[0:0]$5700 + attribute \src "issuer_ls180.v:127912.5-127912.29" + switch \initial + attribute \src "issuer_ls180.v:127912.9-127912.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\rok_l_s_rdok$next[0:0]$5700 1'0 + case + assign $1\rok_l_s_rdok$next[0:0]$5700 \cu_issue_i + end + sync always + update \rok_l_s_rdok$next $0\rok_l_s_rdok$next[0:0]$5699 + end + attribute \src "issuer_ls180.v:127920.3-127928.6" + process $proc$issuer_ls180.v:127920$5701 + assign { } { } + assign { } { } + assign $0\rok_l_r_rdok$next[0:0]$5702 $1\rok_l_r_rdok$next[0:0]$5703 + attribute \src "issuer_ls180.v:127921.5-127921.29" + switch \initial + attribute \src "issuer_ls180.v:127921.9-127921.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\rok_l_r_rdok$next[0:0]$5703 1'1 + case + assign $1\rok_l_r_rdok$next[0:0]$5703 \$63 + end + sync always + update \rok_l_r_rdok$next $0\rok_l_r_rdok$next[0:0]$5702 + end + attribute \src "issuer_ls180.v:127929.3-127937.6" + process $proc$issuer_ls180.v:127929$5704 + assign { } { } + assign { } { } + assign $0\rst_l_s_rst$next[0:0]$5705 $1\rst_l_s_rst$next[0:0]$5706 + attribute \src "issuer_ls180.v:127930.5-127930.29" + switch \initial + attribute \src "issuer_ls180.v:127930.9-127930.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\rst_l_s_rst$next[0:0]$5706 1'0 + case + assign $1\rst_l_s_rst$next[0:0]$5706 \all_rd + end + sync always + update \rst_l_s_rst$next $0\rst_l_s_rst$next[0:0]$5705 + end + attribute \src "issuer_ls180.v:127938.3-127946.6" + process $proc$issuer_ls180.v:127938$5707 + assign { } { } + assign { } { } + assign $0\rst_l_r_rst$next[0:0]$5708 $1\rst_l_r_rst$next[0:0]$5709 + attribute \src "issuer_ls180.v:127939.5-127939.29" + switch \initial + attribute \src "issuer_ls180.v:127939.9-127939.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\rst_l_r_rst$next[0:0]$5709 1'1 + case + assign $1\rst_l_r_rst$next[0:0]$5709 \rst_r + end + sync always + update \rst_l_r_rst$next $0\rst_l_r_rst$next[0:0]$5708 + end + attribute \src "issuer_ls180.v:127947.3-127955.6" + process $proc$issuer_ls180.v:127947$5710 + assign { } { } + assign { } { } + assign $0\opc_l_s_opc$next[0:0]$5711 $1\opc_l_s_opc$next[0:0]$5712 + attribute \src "issuer_ls180.v:127948.5-127948.29" + switch \initial + attribute \src "issuer_ls180.v:127948.9-127948.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\opc_l_s_opc$next[0:0]$5712 1'0 + case + assign $1\opc_l_s_opc$next[0:0]$5712 \cu_issue_i + end + sync always + update \opc_l_s_opc$next $0\opc_l_s_opc$next[0:0]$5711 + end + attribute \src "issuer_ls180.v:127956.3-127964.6" + process $proc$issuer_ls180.v:127956$5713 + assign { } { } + assign { } { } + assign $0\opc_l_r_opc$next[0:0]$5714 $1\opc_l_r_opc$next[0:0]$5715 + attribute \src "issuer_ls180.v:127957.5-127957.29" + switch \initial + attribute \src "issuer_ls180.v:127957.9-127957.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\opc_l_r_opc$next[0:0]$5715 1'1 + case + assign $1\opc_l_r_opc$next[0:0]$5715 \req_done + end + sync always + update \opc_l_r_opc$next $0\opc_l_r_opc$next[0:0]$5714 + end + attribute \src "issuer_ls180.v:127965.3-127973.6" + process $proc$issuer_ls180.v:127965$5716 + assign { } { } + assign { } { } + assign $0\src_l_s_src$next[2:0]$5717 $1\src_l_s_src$next[2:0]$5718 + attribute \src "issuer_ls180.v:127966.5-127966.29" + switch \initial + attribute \src "issuer_ls180.v:127966.9-127966.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\src_l_s_src$next[2:0]$5718 3'000 + case + assign $1\src_l_s_src$next[2:0]$5718 { \cu_issue_i \cu_issue_i \cu_issue_i } + end + sync always + update \src_l_s_src$next $0\src_l_s_src$next[2:0]$5717 + end + attribute \src "issuer_ls180.v:127974.3-127982.6" + process $proc$issuer_ls180.v:127974$5719 + assign { } { } + assign { } { } + assign $0\src_l_r_src$next[2:0]$5720 $1\src_l_r_src$next[2:0]$5721 + attribute \src "issuer_ls180.v:127975.5-127975.29" + switch \initial + attribute \src "issuer_ls180.v:127975.9-127975.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\src_l_r_src$next[2:0]$5721 3'111 + case + assign $1\src_l_r_src$next[2:0]$5721 \reset_r + end + sync always + update \src_l_r_src$next $0\src_l_r_src$next[2:0]$5720 + end + attribute \src "issuer_ls180.v:127983.3-127991.6" + process $proc$issuer_ls180.v:127983$5722 + assign { } { } + assign { } { } + assign $0\req_l_s_req$next[1:0]$5723 $1\req_l_s_req$next[1:0]$5724 + attribute \src "issuer_ls180.v:127984.5-127984.29" + switch \initial + attribute \src "issuer_ls180.v:127984.9-127984.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\req_l_s_req$next[1:0]$5724 2'00 + case + assign $1\req_l_s_req$next[1:0]$5724 \$65 + end + sync always + update \req_l_s_req$next $0\req_l_s_req$next[1:0]$5723 + end + attribute \src "issuer_ls180.v:127992.3-128000.6" + process $proc$issuer_ls180.v:127992$5725 + assign { } { } + assign { } { } + assign $0\req_l_r_req$next[1:0]$5726 $1\req_l_r_req$next[1:0]$5727 + attribute \src "issuer_ls180.v:127993.5-127993.29" + switch \initial + attribute \src "issuer_ls180.v:127993.9-127993.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\req_l_r_req$next[1:0]$5727 2'11 + case + assign $1\req_l_r_req$next[1:0]$5727 \$67 + end + sync always + update \req_l_r_req$next $0\req_l_r_req$next[1:0]$5726 + end + attribute \src "issuer_ls180.v:128001.3-128039.6" + process $proc$issuer_ls180.v:128001$5728 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\alu_logical0_logical_op__data_len$next[3:0]$5729 $1\alu_logical0_logical_op__data_len$next[3:0]$5747 + assign $0\alu_logical0_logical_op__fn_unit$next[11:0]$5730 $1\alu_logical0_logical_op__fn_unit$next[11:0]$5748 + assign { } { } + assign { } { } + assign $0\alu_logical0_logical_op__input_carry$next[1:0]$5733 $1\alu_logical0_logical_op__input_carry$next[1:0]$5751 + assign $0\alu_logical0_logical_op__insn$next[31:0]$5734 $1\alu_logical0_logical_op__insn$next[31:0]$5752 + assign $0\alu_logical0_logical_op__insn_type$next[6:0]$5735 $1\alu_logical0_logical_op__insn_type$next[6:0]$5753 + assign $0\alu_logical0_logical_op__invert_in$next[0:0]$5736 $1\alu_logical0_logical_op__invert_in$next[0:0]$5754 + assign $0\alu_logical0_logical_op__invert_out$next[0:0]$5737 $1\alu_logical0_logical_op__invert_out$next[0:0]$5755 + assign $0\alu_logical0_logical_op__is_32bit$next[0:0]$5738 $1\alu_logical0_logical_op__is_32bit$next[0:0]$5756 + assign $0\alu_logical0_logical_op__is_signed$next[0:0]$5739 $1\alu_logical0_logical_op__is_signed$next[0:0]$5757 + assign { } { } + assign { } { } + assign $0\alu_logical0_logical_op__output_carry$next[0:0]$5742 $1\alu_logical0_logical_op__output_carry$next[0:0]$5760 + assign { } { } + assign { } { } + assign $0\alu_logical0_logical_op__write_cr0$next[0:0]$5745 $1\alu_logical0_logical_op__write_cr0$next[0:0]$5763 + assign $0\alu_logical0_logical_op__zero_a$next[0:0]$5746 $1\alu_logical0_logical_op__zero_a$next[0:0]$5764 + assign $0\alu_logical0_logical_op__imm_data__data$next[63:0]$5731 $2\alu_logical0_logical_op__imm_data__data$next[63:0]$5765 + assign $0\alu_logical0_logical_op__imm_data__ok$next[0:0]$5732 $2\alu_logical0_logical_op__imm_data__ok$next[0:0]$5766 + assign $0\alu_logical0_logical_op__oe__oe$next[0:0]$5740 $2\alu_logical0_logical_op__oe__oe$next[0:0]$5767 + assign $0\alu_logical0_logical_op__oe__ok$next[0:0]$5741 $2\alu_logical0_logical_op__oe__ok$next[0:0]$5768 + assign $0\alu_logical0_logical_op__rc__ok$next[0:0]$5743 $2\alu_logical0_logical_op__rc__ok$next[0:0]$5769 + assign $0\alu_logical0_logical_op__rc__rc$next[0:0]$5744 $2\alu_logical0_logical_op__rc__rc$next[0:0]$5770 + attribute \src "issuer_ls180.v:128002.5-128002.29" + switch \initial + attribute \src "issuer_ls180.v:128002.9-128002.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:257" + switch \cu_issue_i + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { $1\alu_logical0_logical_op__insn$next[31:0]$5752 $1\alu_logical0_logical_op__data_len$next[3:0]$5747 $1\alu_logical0_logical_op__is_signed$next[0:0]$5757 $1\alu_logical0_logical_op__is_32bit$next[0:0]$5756 $1\alu_logical0_logical_op__output_carry$next[0:0]$5760 $1\alu_logical0_logical_op__write_cr0$next[0:0]$5763 $1\alu_logical0_logical_op__invert_out$next[0:0]$5755 $1\alu_logical0_logical_op__input_carry$next[1:0]$5751 $1\alu_logical0_logical_op__zero_a$next[0:0]$5764 $1\alu_logical0_logical_op__invert_in$next[0:0]$5754 $1\alu_logical0_logical_op__oe__ok$next[0:0]$5759 $1\alu_logical0_logical_op__oe__oe$next[0:0]$5758 $1\alu_logical0_logical_op__rc__ok$next[0:0]$5761 $1\alu_logical0_logical_op__rc__rc$next[0:0]$5762 $1\alu_logical0_logical_op__imm_data__ok$next[0:0]$5750 $1\alu_logical0_logical_op__imm_data__data$next[63:0]$5749 $1\alu_logical0_logical_op__fn_unit$next[11:0]$5748 $1\alu_logical0_logical_op__insn_type$next[6:0]$5753 } { \oper_i_alu_logical0__insn \oper_i_alu_logical0__data_len \oper_i_alu_logical0__is_signed \oper_i_alu_logical0__is_32bit \oper_i_alu_logical0__output_carry \oper_i_alu_logical0__write_cr0 \oper_i_alu_logical0__invert_out \oper_i_alu_logical0__input_carry \oper_i_alu_logical0__zero_a \oper_i_alu_logical0__invert_in \oper_i_alu_logical0__oe__ok \oper_i_alu_logical0__oe__oe \oper_i_alu_logical0__rc__ok \oper_i_alu_logical0__rc__rc \oper_i_alu_logical0__imm_data__ok \oper_i_alu_logical0__imm_data__data \oper_i_alu_logical0__fn_unit \oper_i_alu_logical0__insn_type } + case + assign $1\alu_logical0_logical_op__data_len$next[3:0]$5747 \alu_logical0_logical_op__data_len + assign $1\alu_logical0_logical_op__fn_unit$next[11:0]$5748 \alu_logical0_logical_op__fn_unit + assign $1\alu_logical0_logical_op__imm_data__data$next[63:0]$5749 \alu_logical0_logical_op__imm_data__data + assign $1\alu_logical0_logical_op__imm_data__ok$next[0:0]$5750 \alu_logical0_logical_op__imm_data__ok + assign $1\alu_logical0_logical_op__input_carry$next[1:0]$5751 \alu_logical0_logical_op__input_carry + assign $1\alu_logical0_logical_op__insn$next[31:0]$5752 \alu_logical0_logical_op__insn + assign $1\alu_logical0_logical_op__insn_type$next[6:0]$5753 \alu_logical0_logical_op__insn_type + assign $1\alu_logical0_logical_op__invert_in$next[0:0]$5754 \alu_logical0_logical_op__invert_in + assign $1\alu_logical0_logical_op__invert_out$next[0:0]$5755 \alu_logical0_logical_op__invert_out + assign $1\alu_logical0_logical_op__is_32bit$next[0:0]$5756 \alu_logical0_logical_op__is_32bit + assign $1\alu_logical0_logical_op__is_signed$next[0:0]$5757 \alu_logical0_logical_op__is_signed + assign $1\alu_logical0_logical_op__oe__oe$next[0:0]$5758 \alu_logical0_logical_op__oe__oe + assign $1\alu_logical0_logical_op__oe__ok$next[0:0]$5759 \alu_logical0_logical_op__oe__ok + assign $1\alu_logical0_logical_op__output_carry$next[0:0]$5760 \alu_logical0_logical_op__output_carry + assign $1\alu_logical0_logical_op__rc__ok$next[0:0]$5761 \alu_logical0_logical_op__rc__ok + assign $1\alu_logical0_logical_op__rc__rc$next[0:0]$5762 \alu_logical0_logical_op__rc__rc + assign $1\alu_logical0_logical_op__write_cr0$next[0:0]$5763 \alu_logical0_logical_op__write_cr0 + assign $1\alu_logical0_logical_op__zero_a$next[0:0]$5764 \alu_logical0_logical_op__zero_a + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $2\alu_logical0_logical_op__imm_data__data$next[63:0]$5765 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\alu_logical0_logical_op__imm_data__ok$next[0:0]$5766 1'0 + assign $2\alu_logical0_logical_op__rc__rc$next[0:0]$5770 1'0 + assign $2\alu_logical0_logical_op__rc__ok$next[0:0]$5769 1'0 + assign $2\alu_logical0_logical_op__oe__oe$next[0:0]$5767 1'0 + assign $2\alu_logical0_logical_op__oe__ok$next[0:0]$5768 1'0 + case + assign $2\alu_logical0_logical_op__imm_data__data$next[63:0]$5765 $1\alu_logical0_logical_op__imm_data__data$next[63:0]$5749 + assign $2\alu_logical0_logical_op__imm_data__ok$next[0:0]$5766 $1\alu_logical0_logical_op__imm_data__ok$next[0:0]$5750 + assign $2\alu_logical0_logical_op__oe__oe$next[0:0]$5767 $1\alu_logical0_logical_op__oe__oe$next[0:0]$5758 + assign $2\alu_logical0_logical_op__oe__ok$next[0:0]$5768 $1\alu_logical0_logical_op__oe__ok$next[0:0]$5759 + assign $2\alu_logical0_logical_op__rc__ok$next[0:0]$5769 $1\alu_logical0_logical_op__rc__ok$next[0:0]$5761 + assign $2\alu_logical0_logical_op__rc__rc$next[0:0]$5770 $1\alu_logical0_logical_op__rc__rc$next[0:0]$5762 + end + sync always + update \alu_logical0_logical_op__data_len$next $0\alu_logical0_logical_op__data_len$next[3:0]$5729 + update \alu_logical0_logical_op__fn_unit$next $0\alu_logical0_logical_op__fn_unit$next[11:0]$5730 + update \alu_logical0_logical_op__imm_data__data$next $0\alu_logical0_logical_op__imm_data__data$next[63:0]$5731 + update \alu_logical0_logical_op__imm_data__ok$next $0\alu_logical0_logical_op__imm_data__ok$next[0:0]$5732 + update \alu_logical0_logical_op__input_carry$next $0\alu_logical0_logical_op__input_carry$next[1:0]$5733 + update \alu_logical0_logical_op__insn$next $0\alu_logical0_logical_op__insn$next[31:0]$5734 + update \alu_logical0_logical_op__insn_type$next $0\alu_logical0_logical_op__insn_type$next[6:0]$5735 + update \alu_logical0_logical_op__invert_in$next $0\alu_logical0_logical_op__invert_in$next[0:0]$5736 + update \alu_logical0_logical_op__invert_out$next $0\alu_logical0_logical_op__invert_out$next[0:0]$5737 + update \alu_logical0_logical_op__is_32bit$next $0\alu_logical0_logical_op__is_32bit$next[0:0]$5738 + update \alu_logical0_logical_op__is_signed$next $0\alu_logical0_logical_op__is_signed$next[0:0]$5739 + update \alu_logical0_logical_op__oe__oe$next $0\alu_logical0_logical_op__oe__oe$next[0:0]$5740 + update \alu_logical0_logical_op__oe__ok$next $0\alu_logical0_logical_op__oe__ok$next[0:0]$5741 + update \alu_logical0_logical_op__output_carry$next $0\alu_logical0_logical_op__output_carry$next[0:0]$5742 + update \alu_logical0_logical_op__rc__ok$next $0\alu_logical0_logical_op__rc__ok$next[0:0]$5743 + update \alu_logical0_logical_op__rc__rc$next $0\alu_logical0_logical_op__rc__rc$next[0:0]$5744 + update \alu_logical0_logical_op__write_cr0$next $0\alu_logical0_logical_op__write_cr0$next[0:0]$5745 + update \alu_logical0_logical_op__zero_a$next $0\alu_logical0_logical_op__zero_a$next[0:0]$5746 + end + attribute \src "issuer_ls180.v:128040.3-128061.6" + process $proc$issuer_ls180.v:128040$5771 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\data_r0__o$next[63:0]$5772 $2\data_r0__o$next[63:0]$5776 + assign { } { } + assign $0\data_r0__o_ok$next[0:0]$5773 $3\data_r0__o_ok$next[0:0]$5778 + attribute \src "issuer_ls180.v:128041.5-128041.29" + switch \initial + attribute \src "issuer_ls180.v:128041.9-128041.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" + switch \alu_pulse + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $1\data_r0__o_ok$next[0:0]$5775 $1\data_r0__o$next[63:0]$5774 } { \o_ok \alu_logical0_o } + case + assign $1\data_r0__o$next[63:0]$5774 \data_r0__o + assign $1\data_r0__o_ok$next[0:0]$5775 \data_r0__o_ok + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" + switch \cu_issue_i + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $2\data_r0__o_ok$next[0:0]$5777 $2\data_r0__o$next[63:0]$5776 } 65'00000000000000000000000000000000000000000000000000000000000000000 + case + assign $2\data_r0__o$next[63:0]$5776 $1\data_r0__o$next[63:0]$5774 + assign $2\data_r0__o_ok$next[0:0]$5777 $1\data_r0__o_ok$next[0:0]$5775 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\data_r0__o_ok$next[0:0]$5778 1'0 + case + assign $3\data_r0__o_ok$next[0:0]$5778 $2\data_r0__o_ok$next[0:0]$5777 + end + sync always + update \data_r0__o$next $0\data_r0__o$next[63:0]$5772 + update \data_r0__o_ok$next $0\data_r0__o_ok$next[0:0]$5773 + end + attribute \src "issuer_ls180.v:128062.3-128083.6" + process $proc$issuer_ls180.v:128062$5779 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\data_r1__cr_a$next[3:0]$5780 $2\data_r1__cr_a$next[3:0]$5784 + assign { } { } + assign $0\data_r1__cr_a_ok$next[0:0]$5781 $3\data_r1__cr_a_ok$next[0:0]$5786 + attribute \src "issuer_ls180.v:128063.5-128063.29" + switch \initial + attribute \src "issuer_ls180.v:128063.9-128063.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" + switch \alu_pulse + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $1\data_r1__cr_a_ok$next[0:0]$5783 $1\data_r1__cr_a$next[3:0]$5782 } { \cr_a_ok \alu_logical0_cr_a } + case + assign $1\data_r1__cr_a$next[3:0]$5782 \data_r1__cr_a + assign $1\data_r1__cr_a_ok$next[0:0]$5783 \data_r1__cr_a_ok + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" + switch \cu_issue_i + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $2\data_r1__cr_a_ok$next[0:0]$5785 $2\data_r1__cr_a$next[3:0]$5784 } 5'00000 + case + assign $2\data_r1__cr_a$next[3:0]$5784 $1\data_r1__cr_a$next[3:0]$5782 + assign $2\data_r1__cr_a_ok$next[0:0]$5785 $1\data_r1__cr_a_ok$next[0:0]$5783 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\data_r1__cr_a_ok$next[0:0]$5786 1'0 + case + assign $3\data_r1__cr_a_ok$next[0:0]$5786 $2\data_r1__cr_a_ok$next[0:0]$5785 + end + sync always + update \data_r1__cr_a$next $0\data_r1__cr_a$next[3:0]$5780 + update \data_r1__cr_a_ok$next $0\data_r1__cr_a_ok$next[0:0]$5781 + end + attribute \src "issuer_ls180.v:128084.3-128093.6" + process $proc$issuer_ls180.v:128084$5787 + assign { } { } + assign { } { } + assign $0\src_r0$next[63:0]$5788 $1\src_r0$next[63:0]$5789 + attribute \src "issuer_ls180.v:128085.5-128085.29" + switch \initial + attribute \src "issuer_ls180.v:128085.9-128085.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" + switch \src_sel + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\src_r0$next[63:0]$5789 \src_or_imm + case + assign $1\src_r0$next[63:0]$5789 \src_r0 + end + sync always + update \src_r0$next $0\src_r0$next[63:0]$5788 + end + attribute \src "issuer_ls180.v:128094.3-128103.6" + process $proc$issuer_ls180.v:128094$5790 + assign { } { } + assign { } { } + assign $0\src_r1$next[63:0]$5791 $1\src_r1$next[63:0]$5792 + attribute \src "issuer_ls180.v:128095.5-128095.29" + switch \initial + attribute \src "issuer_ls180.v:128095.9-128095.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" + switch \src_sel$77 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\src_r1$next[63:0]$5792 \src_or_imm$80 + case + assign $1\src_r1$next[63:0]$5792 \src_r1 + end + sync always + update \src_r1$next $0\src_r1$next[63:0]$5791 + end + attribute \src "issuer_ls180.v:128104.3-128113.6" + process $proc$issuer_ls180.v:128104$5793 + assign { } { } + assign { } { } + assign $0\src_r2$next[0:0]$5794 $1\src_r2$next[0:0]$5795 + attribute \src "issuer_ls180.v:128105.5-128105.29" + switch \initial + attribute \src "issuer_ls180.v:128105.9-128105.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" + switch \src_l_q_src [2] + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\src_r2$next[0:0]$5795 \src3_i + case + assign $1\src_r2$next[0:0]$5795 \src_r2 + end + sync always + update \src_r2$next $0\src_r2$next[0:0]$5794 + end + attribute \src "issuer_ls180.v:128114.3-128122.6" + process $proc$issuer_ls180.v:128114$5796 + assign { } { } + assign { } { } + assign $0\alui_l_r_alui$next[0:0]$5797 $1\alui_l_r_alui$next[0:0]$5798 + attribute \src "issuer_ls180.v:128115.5-128115.29" + switch \initial + attribute \src "issuer_ls180.v:128115.9-128115.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\alui_l_r_alui$next[0:0]$5798 1'1 + case + assign $1\alui_l_r_alui$next[0:0]$5798 \$89 + end + sync always + update \alui_l_r_alui$next $0\alui_l_r_alui$next[0:0]$5797 + end + attribute \src "issuer_ls180.v:128123.3-128131.6" + process $proc$issuer_ls180.v:128123$5799 + assign { } { } + assign { } { } + assign $0\alu_l_r_alu$next[0:0]$5800 $1\alu_l_r_alu$next[0:0]$5801 + attribute \src "issuer_ls180.v:128124.5-128124.29" + switch \initial + attribute \src "issuer_ls180.v:128124.9-128124.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\alu_l_r_alu$next[0:0]$5801 1'1 + case + assign $1\alu_l_r_alu$next[0:0]$5801 \$91 + end + sync always + update \alu_l_r_alu$next $0\alu_l_r_alu$next[0:0]$5800 + end + attribute \src "issuer_ls180.v:128132.3-128141.6" + process $proc$issuer_ls180.v:128132$5802 + assign { } { } + assign { } { } + assign $0\dest1_o[63:0] $1\dest1_o[63:0] + attribute \src "issuer_ls180.v:128133.5-128133.29" + switch \initial + attribute \src "issuer_ls180.v:128133.9-128133.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" + switch \$113 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dest1_o[63:0] \data_r0__o + case + assign $1\dest1_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \dest1_o $0\dest1_o[63:0] + end + attribute \src "issuer_ls180.v:128142.3-128151.6" + process $proc$issuer_ls180.v:128142$5803 + assign { } { } + assign { } { } + assign $0\dest2_o[3:0] $1\dest2_o[3:0] + attribute \src "issuer_ls180.v:128143.5-128143.29" + switch \initial + attribute \src "issuer_ls180.v:128143.9-128143.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" + switch \$115 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dest2_o[3:0] \data_r1__cr_a + case + assign $1\dest2_o[3:0] 4'0000 + end + sync always + update \dest2_o $0\dest2_o[3:0] + end + attribute \src "issuer_ls180.v:128152.3-128160.6" + process $proc$issuer_ls180.v:128152$5804 + assign { } { } + assign { } { } + assign $0\prev_wr_go$next[1:0]$5805 $1\prev_wr_go$next[1:0]$5806 + attribute \src "issuer_ls180.v:128153.5-128153.29" + switch \initial + attribute \src "issuer_ls180.v:128153.9-128153.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\prev_wr_go$next[1:0]$5806 2'00 + case + assign $1\prev_wr_go$next[1:0]$5806 \$19 + end + sync always + update \prev_wr_go$next $0\prev_wr_go$next[1:0]$5805 + end + connect \$9 $and$issuer_ls180.v:127683$5600_Y + connect \$99 $and$issuer_ls180.v:127684$5601_Y + connect \$101 $not$issuer_ls180.v:127685$5602_Y + connect \$103 $and$issuer_ls180.v:127686$5603_Y + connect \$105 $and$issuer_ls180.v:127687$5604_Y + connect \$107 $and$issuer_ls180.v:127688$5605_Y + connect \$109 $and$issuer_ls180.v:127689$5606_Y + connect \$111 $and$issuer_ls180.v:127690$5607_Y + connect \$113 $and$issuer_ls180.v:127691$5608_Y + connect \$115 $and$issuer_ls180.v:127692$5609_Y + connect \$11 $not$issuer_ls180.v:127693$5610_Y + connect \$13 $and$issuer_ls180.v:127694$5611_Y + connect \$15 $not$issuer_ls180.v:127695$5612_Y + connect \$17 $and$issuer_ls180.v:127696$5613_Y + connect \$1 $and$issuer_ls180.v:127697$5614_Y + connect \$19 $and$issuer_ls180.v:127698$5615_Y + connect \$23 $not$issuer_ls180.v:127699$5616_Y + connect \$25 $and$issuer_ls180.v:127700$5617_Y + connect \$22 $reduce_or$issuer_ls180.v:127701$5618_Y + connect \$21 $not$issuer_ls180.v:127702$5619_Y + connect \$29 $and$issuer_ls180.v:127703$5620_Y + connect \$31 $reduce_or$issuer_ls180.v:127704$5621_Y + connect \$33 $reduce_or$issuer_ls180.v:127705$5622_Y + connect \$35 $or$issuer_ls180.v:127706$5623_Y + connect \$37 $not$issuer_ls180.v:127707$5624_Y + connect \$39 $and$issuer_ls180.v:127708$5625_Y + connect \$41 $and$issuer_ls180.v:127709$5626_Y + connect \$43 $eq$issuer_ls180.v:127710$5627_Y + connect \$45 $and$issuer_ls180.v:127711$5628_Y + connect \$47 $eq$issuer_ls180.v:127712$5629_Y + connect \$4 $not$issuer_ls180.v:127713$5630_Y + connect \$49 $and$issuer_ls180.v:127714$5631_Y + connect \$51 $and$issuer_ls180.v:127715$5632_Y + connect \$53 $and$issuer_ls180.v:127716$5633_Y + connect \$55 $or$issuer_ls180.v:127717$5634_Y + connect \$57 $or$issuer_ls180.v:127718$5635_Y + connect \$59 $or$issuer_ls180.v:127719$5636_Y + connect \$61 $or$issuer_ls180.v:127720$5637_Y + connect \$63 $and$issuer_ls180.v:127721$5638_Y + connect \$65 $and$issuer_ls180.v:127722$5639_Y + connect \$67 $or$issuer_ls180.v:127723$5640_Y + connect \$6 $or$issuer_ls180.v:127724$5641_Y + connect \$69 $and$issuer_ls180.v:127725$5642_Y + connect \$71 $and$issuer_ls180.v:127726$5643_Y + connect \$73 $ternary$issuer_ls180.v:127727$5644_Y + connect \$75 $ternary$issuer_ls180.v:127728$5645_Y + connect \$78 $ternary$issuer_ls180.v:127729$5646_Y + connect \$3 $reduce_and$issuer_ls180.v:127730$5647_Y + connect \$81 $ternary$issuer_ls180.v:127731$5648_Y + connect \$83 $ternary$issuer_ls180.v:127732$5649_Y + connect \$85 $ternary$issuer_ls180.v:127733$5650_Y + connect \$87 $ternary$issuer_ls180.v:127734$5651_Y + connect \$89 $and$issuer_ls180.v:127735$5652_Y + connect \$91 $and$issuer_ls180.v:127736$5653_Y + connect \$93 $and$issuer_ls180.v:127737$5654_Y + connect \$95 $not$issuer_ls180.v:127738$5655_Y + connect \$97 $not$issuer_ls180.v:127739$5656_Y + connect \cu_go_die_i 1'0 + connect \cu_shadown_i 1'1 + connect \cu_wr__rel_o \$111 + connect \cu_rd__rel_o \$103 + connect \cu_busy_o \opc_l_q_opc + connect \alu_l_s_alu \all_rd_pulse + connect \alu_logical0_n_ready_i \alu_l_q_alu + connect \alui_l_s_alui \all_rd_pulse + connect \alu_logical0_p_valid_i \alui_l_q_alui + connect \alu_logical0_xer_so \$87 + connect \alu_logical0_rb \$85 + connect \alu_logical0_ra \$83 + connect \src_or_imm$80 \$81 + connect \src_sel$77 \$78 + connect \src_or_imm \$75 + connect \src_sel \$73 + connect \cu_wrmask_o { \$71 \$69 } + connect \reset_r \$61 + connect \reset_w \$59 + connect \rst_r \$57 + connect \reset \$55 + connect \wr_any \$35 + connect \cu_done_o \$29 + connect \alu_pulsem { \alu_pulse \alu_pulse } + connect \alu_pulse \alu_done_rise + connect \alu_done_rise \$17 + connect \alu_done_dly$next \alu_done + connect \alu_done \alu_logical0_n_valid_o + connect \all_rd_pulse \all_rd_rise + connect \all_rd_rise \$13 + connect \all_rd_dly$next \all_rd + connect \all_rd \$9 +end +attribute \src "issuer_ls180.v:128197.1-129567.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.fus.logical0.alu_logical0.logical_pipe1" +attribute \generator "nMigen" +module \logical_pipe1 + attribute \src "issuer_ls180.v:129506.3-129524.6" + wire width 4 $0\cr_a$next[3:0]$5932 + attribute \src "issuer_ls180.v:129266.3-129267.25" + wire width 4 $0\cr_a[3:0] + attribute \src "issuer_ls180.v:129506.3-129524.6" + wire $0\cr_a_ok$next[0:0]$5933 + attribute \src "issuer_ls180.v:129268.3-129269.31" + wire $0\cr_a_ok[0:0] + attribute \src "issuer_ls180.v:128198.7-128198.20" + wire $0\initial[0:0] + attribute \src "issuer_ls180.v:129445.3-129486.6" + wire width 4 $0\logical_op__data_len$next[3:0]$5883 + attribute \src "issuer_ls180.v:129306.3-129307.57" + wire width 4 $0\logical_op__data_len[3:0] + attribute \src "issuer_ls180.v:129445.3-129486.6" + wire width 12 $0\logical_op__fn_unit$next[11:0]$5884 + attribute \src "issuer_ls180.v:129276.3-129277.55" + wire width 12 $0\logical_op__fn_unit[11:0] + attribute \src "issuer_ls180.v:129445.3-129486.6" + wire width 64 $0\logical_op__imm_data__data$next[63:0]$5885 + attribute \src "issuer_ls180.v:129278.3-129279.69" + wire width 64 $0\logical_op__imm_data__data[63:0] + attribute \src "issuer_ls180.v:129445.3-129486.6" + wire $0\logical_op__imm_data__ok$next[0:0]$5886 + attribute \src "issuer_ls180.v:129280.3-129281.65" + wire $0\logical_op__imm_data__ok[0:0] + attribute \src "issuer_ls180.v:129445.3-129486.6" + wire width 2 $0\logical_op__input_carry$next[1:0]$5887 + attribute \src "issuer_ls180.v:129294.3-129295.63" + wire width 2 $0\logical_op__input_carry[1:0] + attribute \src "issuer_ls180.v:129445.3-129486.6" + wire width 32 $0\logical_op__insn$next[31:0]$5888 + attribute \src "issuer_ls180.v:129308.3-129309.49" + wire width 32 $0\logical_op__insn[31:0] + attribute \src "issuer_ls180.v:129445.3-129486.6" + wire width 7 $0\logical_op__insn_type$next[6:0]$5889 + attribute \src "issuer_ls180.v:129274.3-129275.59" + wire width 7 $0\logical_op__insn_type[6:0] + attribute \src "issuer_ls180.v:129445.3-129486.6" + wire $0\logical_op__invert_in$next[0:0]$5890 + attribute \src "issuer_ls180.v:129290.3-129291.59" + wire $0\logical_op__invert_in[0:0] + attribute \src "issuer_ls180.v:129445.3-129486.6" + wire $0\logical_op__invert_out$next[0:0]$5891 + attribute \src "issuer_ls180.v:129296.3-129297.61" + wire $0\logical_op__invert_out[0:0] + attribute \src "issuer_ls180.v:129445.3-129486.6" + wire $0\logical_op__is_32bit$next[0:0]$5892 + attribute \src "issuer_ls180.v:129302.3-129303.57" + wire $0\logical_op__is_32bit[0:0] + attribute \src "issuer_ls180.v:129445.3-129486.6" + wire $0\logical_op__is_signed$next[0:0]$5893 + attribute \src "issuer_ls180.v:129304.3-129305.59" + wire $0\logical_op__is_signed[0:0] + attribute \src "issuer_ls180.v:129445.3-129486.6" + wire $0\logical_op__oe__oe$next[0:0]$5894 + attribute \src "issuer_ls180.v:129286.3-129287.53" + wire $0\logical_op__oe__oe[0:0] + attribute \src "issuer_ls180.v:129445.3-129486.6" + wire $0\logical_op__oe__ok$next[0:0]$5895 + attribute \src "issuer_ls180.v:129288.3-129289.53" + wire $0\logical_op__oe__ok[0:0] + attribute \src "issuer_ls180.v:129445.3-129486.6" + wire $0\logical_op__output_carry$next[0:0]$5896 + attribute \src "issuer_ls180.v:129300.3-129301.65" + wire $0\logical_op__output_carry[0:0] + attribute \src "issuer_ls180.v:129445.3-129486.6" + wire $0\logical_op__rc__ok$next[0:0]$5897 + attribute \src "issuer_ls180.v:129284.3-129285.53" + wire $0\logical_op__rc__ok[0:0] + attribute \src "issuer_ls180.v:129445.3-129486.6" + wire $0\logical_op__rc__rc$next[0:0]$5898 + attribute \src "issuer_ls180.v:129282.3-129283.53" + wire $0\logical_op__rc__rc[0:0] + attribute \src "issuer_ls180.v:129445.3-129486.6" + wire $0\logical_op__write_cr0$next[0:0]$5899 + attribute \src "issuer_ls180.v:129298.3-129299.59" + wire $0\logical_op__write_cr0[0:0] + attribute \src "issuer_ls180.v:129445.3-129486.6" + wire $0\logical_op__zero_a$next[0:0]$5900 + attribute \src "issuer_ls180.v:129292.3-129293.53" + wire $0\logical_op__zero_a[0:0] + attribute \src "issuer_ls180.v:129432.3-129444.6" + wire width 2 $0\muxid$next[1:0]$5880 + attribute \src "issuer_ls180.v:129310.3-129311.27" + wire width 2 $0\muxid[1:0] + attribute \src "issuer_ls180.v:129487.3-129505.6" + wire width 64 $0\o$next[63:0]$5926 + attribute \src "issuer_ls180.v:129270.3-129271.19" + wire width 64 $0\o[63:0] + attribute \src "issuer_ls180.v:129487.3-129505.6" + wire $0\o_ok$next[0:0]$5927 + attribute \src "issuer_ls180.v:129272.3-129273.25" + wire $0\o_ok[0:0] + attribute \src "issuer_ls180.v:129414.3-129431.6" + wire $0\r_busy$next[0:0]$5876 + attribute \src "issuer_ls180.v:129312.3-129313.29" + wire $0\r_busy[0:0] + attribute \src "issuer_ls180.v:129525.3-129543.6" + wire $0\xer_so$next[0:0]$5938 + attribute \src "issuer_ls180.v:129262.3-129263.29" + wire $0\xer_so[0:0] + attribute \src "issuer_ls180.v:129525.3-129543.6" + wire $0\xer_so_ok$next[0:0]$5939 + attribute \src "issuer_ls180.v:129264.3-129265.35" + wire $0\xer_so_ok[0:0] + attribute \src "issuer_ls180.v:129506.3-129524.6" + wire width 4 $1\cr_a$next[3:0]$5934 + attribute \src "issuer_ls180.v:128207.13-128207.24" + wire width 4 $1\cr_a[3:0] + attribute \src "issuer_ls180.v:129506.3-129524.6" + wire $1\cr_a_ok$next[0:0]$5935 + attribute \src "issuer_ls180.v:128216.7-128216.21" + wire $1\cr_a_ok[0:0] + attribute \src "issuer_ls180.v:129445.3-129486.6" + wire width 4 $1\logical_op__data_len$next[3:0]$5901 + attribute \src "issuer_ls180.v:128495.13-128495.40" + wire width 4 $1\logical_op__data_len[3:0] + attribute \src "issuer_ls180.v:129445.3-129486.6" + wire width 12 $1\logical_op__fn_unit$next[11:0]$5902 + attribute \src "issuer_ls180.v:128517.14-128517.43" + wire width 12 $1\logical_op__fn_unit[11:0] + attribute \src "issuer_ls180.v:129445.3-129486.6" + wire width 64 $1\logical_op__imm_data__data$next[63:0]$5903 + attribute \src "issuer_ls180.v:128552.14-128552.63" + wire width 64 $1\logical_op__imm_data__data[63:0] + attribute \src "issuer_ls180.v:129445.3-129486.6" + wire $1\logical_op__imm_data__ok$next[0:0]$5904 + attribute \src "issuer_ls180.v:128561.7-128561.38" + wire $1\logical_op__imm_data__ok[0:0] + attribute \src "issuer_ls180.v:129445.3-129486.6" + wire width 2 $1\logical_op__input_carry$next[1:0]$5905 + attribute \src "issuer_ls180.v:128574.13-128574.43" + wire width 2 $1\logical_op__input_carry[1:0] + attribute \src "issuer_ls180.v:129445.3-129486.6" + wire width 32 $1\logical_op__insn$next[31:0]$5906 + attribute \src "issuer_ls180.v:128591.14-128591.38" + wire width 32 $1\logical_op__insn[31:0] + attribute \src "issuer_ls180.v:129445.3-129486.6" + wire width 7 $1\logical_op__insn_type$next[6:0]$5907 + attribute \src "issuer_ls180.v:128674.13-128674.42" + wire width 7 $1\logical_op__insn_type[6:0] + attribute \src "issuer_ls180.v:129445.3-129486.6" + wire $1\logical_op__invert_in$next[0:0]$5908 + attribute \src "issuer_ls180.v:128831.7-128831.35" + wire $1\logical_op__invert_in[0:0] + attribute \src "issuer_ls180.v:129445.3-129486.6" + wire $1\logical_op__invert_out$next[0:0]$5909 + attribute \src "issuer_ls180.v:128840.7-128840.36" + wire $1\logical_op__invert_out[0:0] + attribute \src "issuer_ls180.v:129445.3-129486.6" + wire $1\logical_op__is_32bit$next[0:0]$5910 + attribute \src "issuer_ls180.v:128849.7-128849.34" + wire $1\logical_op__is_32bit[0:0] + attribute \src "issuer_ls180.v:129445.3-129486.6" + wire $1\logical_op__is_signed$next[0:0]$5911 + attribute \src "issuer_ls180.v:128858.7-128858.35" + wire $1\logical_op__is_signed[0:0] + attribute \src "issuer_ls180.v:129445.3-129486.6" + wire $1\logical_op__oe__oe$next[0:0]$5912 + attribute \src "issuer_ls180.v:128867.7-128867.32" + wire $1\logical_op__oe__oe[0:0] + attribute \src "issuer_ls180.v:129445.3-129486.6" + wire $1\logical_op__oe__ok$next[0:0]$5913 + attribute \src "issuer_ls180.v:128876.7-128876.32" + wire $1\logical_op__oe__ok[0:0] + attribute \src "issuer_ls180.v:129445.3-129486.6" + wire $1\logical_op__output_carry$next[0:0]$5914 + attribute \src "issuer_ls180.v:128885.7-128885.38" + wire $1\logical_op__output_carry[0:0] + attribute \src "issuer_ls180.v:129445.3-129486.6" + wire $1\logical_op__rc__ok$next[0:0]$5915 + attribute \src "issuer_ls180.v:128894.7-128894.32" + wire $1\logical_op__rc__ok[0:0] + attribute \src "issuer_ls180.v:129445.3-129486.6" + wire $1\logical_op__rc__rc$next[0:0]$5916 + attribute \src "issuer_ls180.v:128903.7-128903.32" + wire $1\logical_op__rc__rc[0:0] + attribute \src "issuer_ls180.v:129445.3-129486.6" + wire $1\logical_op__write_cr0$next[0:0]$5917 + attribute \src "issuer_ls180.v:128912.7-128912.35" + wire $1\logical_op__write_cr0[0:0] + attribute \src "issuer_ls180.v:129445.3-129486.6" + wire $1\logical_op__zero_a$next[0:0]$5918 + attribute \src "issuer_ls180.v:128921.7-128921.32" + wire $1\logical_op__zero_a[0:0] + attribute \src "issuer_ls180.v:129432.3-129444.6" + wire width 2 $1\muxid$next[1:0]$5881 + attribute \src "issuer_ls180.v:129200.13-129200.25" + wire width 2 $1\muxid[1:0] + attribute \src "issuer_ls180.v:129487.3-129505.6" + wire width 64 $1\o$next[63:0]$5928 + attribute \src "issuer_ls180.v:129215.14-129215.38" + wire width 64 $1\o[63:0] + attribute \src "issuer_ls180.v:129487.3-129505.6" + wire $1\o_ok$next[0:0]$5929 + attribute \src "issuer_ls180.v:129222.7-129222.18" + wire $1\o_ok[0:0] + attribute \src "issuer_ls180.v:129414.3-129431.6" + wire $1\r_busy$next[0:0]$5877 + attribute \src "issuer_ls180.v:129236.7-129236.20" + wire $1\r_busy[0:0] + attribute \src "issuer_ls180.v:129525.3-129543.6" + wire $1\xer_so$next[0:0]$5940 + attribute \src "issuer_ls180.v:129245.7-129245.20" + wire $1\xer_so[0:0] + attribute \src "issuer_ls180.v:129525.3-129543.6" + wire $1\xer_so_ok$next[0:0]$5941 + attribute \src "issuer_ls180.v:129254.7-129254.23" + wire $1\xer_so_ok[0:0] + attribute \src "issuer_ls180.v:129506.3-129524.6" + wire $2\cr_a_ok$next[0:0]$5936 + attribute \src "issuer_ls180.v:129445.3-129486.6" + wire width 64 $2\logical_op__imm_data__data$next[63:0]$5919 + attribute \src "issuer_ls180.v:129445.3-129486.6" + wire $2\logical_op__imm_data__ok$next[0:0]$5920 + attribute \src "issuer_ls180.v:129445.3-129486.6" + wire $2\logical_op__oe__oe$next[0:0]$5921 + attribute \src "issuer_ls180.v:129445.3-129486.6" + wire $2\logical_op__oe__ok$next[0:0]$5922 + attribute \src "issuer_ls180.v:129445.3-129486.6" + wire $2\logical_op__rc__ok$next[0:0]$5923 + attribute \src "issuer_ls180.v:129445.3-129486.6" + wire $2\logical_op__rc__rc$next[0:0]$5924 + attribute \src "issuer_ls180.v:129487.3-129505.6" + wire $2\o_ok$next[0:0]$5930 + attribute \src "issuer_ls180.v:129414.3-129431.6" + wire $2\r_busy$next[0:0]$5878 + attribute \src "issuer_ls180.v:129525.3-129543.6" + wire $2\xer_so_ok$next[0:0]$5942 + attribute \src "issuer_ls180.v:129261.18-129261.118" + wire $and$issuer_ls180.v:129261$5848_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" + wire \$64 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" + wire input 53 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" + wire input 1 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 4 output 25 \cr_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 4 \cr_a$87 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 4 \cr_a$89 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 4 \cr_a$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 26 \cr_a_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \cr_a_ok$88 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \cr_a_ok$90 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \cr_a_ok$next + attribute \src "issuer_ls180.v:128198.7-128198.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \input_logical_op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \input_logical_op__data_len$38 + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 \input_logical_op__fn_unit + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 \input_logical_op__fn_unit$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \input_logical_op__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \input_logical_op__imm_data__data$24 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_logical_op__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_logical_op__imm_data__ok$25 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \input_logical_op__input_carry + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \input_logical_op__input_carry$32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \input_logical_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \input_logical_op__insn$39 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \input_logical_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \input_logical_op__insn_type$22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_logical_op__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_logical_op__invert_in$30 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_logical_op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_logical_op__invert_out$33 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_logical_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_logical_op__is_32bit$36 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_logical_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_logical_op__is_signed$37 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_logical_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_logical_op__oe__oe$28 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_logical_op__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_logical_op__oe__ok$29 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_logical_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_logical_op__output_carry$35 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_logical_op__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_logical_op__rc__ok$27 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_logical_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_logical_op__rc__rc$26 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_logical_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_logical_op__write_cr0$34 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_logical_op__zero_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_logical_op__zero_a$31 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \input_muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \input_muxid$21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \input_ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \input_ra$40 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \input_rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \input_rb$41 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire \input_xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire \input_xer_so$42 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 output 21 \logical_op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 input 48 \logical_op__data_len$18 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \logical_op__data_len$83 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \logical_op__data_len$next + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 output 6 \logical_op__fn_unit + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 input 33 \logical_op__fn_unit$3 + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 \logical_op__fn_unit$68 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 \logical_op__fn_unit$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 output 7 \logical_op__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 input 34 \logical_op__imm_data__data$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \logical_op__imm_data__data$69 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \logical_op__imm_data__data$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 8 \logical_op__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 35 \logical_op__imm_data__ok$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__imm_data__ok$70 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__imm_data__ok$next + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 output 15 \logical_op__input_carry + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 input 42 \logical_op__input_carry$12 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \logical_op__input_carry$77 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \logical_op__input_carry$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 output 22 \logical_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 49 \logical_op__insn$19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \logical_op__insn$84 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \logical_op__insn$next + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 output 5 \logical_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 input 32 \logical_op__insn_type$2 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \logical_op__insn_type$67 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \logical_op__insn_type$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 13 \logical_op__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 40 \logical_op__invert_in$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__invert_in$75 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__invert_in$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 16 \logical_op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 43 \logical_op__invert_out$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__invert_out$78 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__invert_out$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 19 \logical_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 46 \logical_op__is_32bit$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__is_32bit$81 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__is_32bit$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 20 \logical_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 47 \logical_op__is_signed$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__is_signed$82 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__is_signed$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 11 \logical_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__oe__oe$73 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 38 \logical_op__oe__oe$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__oe__oe$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 12 \logical_op__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__oe__ok$74 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 39 \logical_op__oe__ok$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__oe__ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 18 \logical_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 45 \logical_op__output_carry$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__output_carry$80 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__output_carry$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 10 \logical_op__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 37 \logical_op__rc__ok$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__rc__ok$72 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__rc__ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 9 \logical_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 36 \logical_op__rc__rc$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__rc__rc$71 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__rc__rc$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 17 \logical_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 44 \logical_op__write_cr0$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__write_cr0$79 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__write_cr0$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 14 \logical_op__zero_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 41 \logical_op__zero_a$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__zero_a$76 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__zero_a$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \main_logical_op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \main_logical_op__data_len$60 + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 \main_logical_op__fn_unit + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 \main_logical_op__fn_unit$45 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \main_logical_op__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \main_logical_op__imm_data__data$46 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_logical_op__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_logical_op__imm_data__ok$47 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \main_logical_op__input_carry + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \main_logical_op__input_carry$54 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \main_logical_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \main_logical_op__insn$61 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \main_logical_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \main_logical_op__insn_type$44 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_logical_op__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_logical_op__invert_in$52 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_logical_op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_logical_op__invert_out$55 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_logical_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_logical_op__is_32bit$58 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_logical_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_logical_op__is_signed$59 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_logical_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_logical_op__oe__oe$50 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_logical_op__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_logical_op__oe__ok$51 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_logical_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_logical_op__output_carry$57 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_logical_op__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_logical_op__rc__ok$49 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_logical_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_logical_op__rc__rc$48 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_logical_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_logical_op__write_cr0$56 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_logical_op__zero_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_logical_op__zero_a$53 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \main_muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \main_muxid$43 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 \main_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \main_o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \main_ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \main_rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire \main_xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \main_xer_so$62 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 output 4 \muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 input 31 \muxid$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \muxid$66 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \muxid$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:619" + wire \n_i_rdy_data + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" + wire input 3 \n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" + wire output 2 \n_valid_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 output 23 \o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 \o$85 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 \o$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 24 \o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \o_ok$86 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \o_ok$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" + wire output 30 \p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" + wire input 29 \p_valid_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:621" + wire \p_valid_i$63 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" + wire \p_valid_i_p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615" + wire \r_busy + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615" + wire \r_busy$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 50 \ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 51 \rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 27 \xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire input 52 \xer_so$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \xer_so$91 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \xer_so$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 28 \xer_so_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \xer_so_ok$92 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \xer_so_ok$93 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \xer_so_ok$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" + cell $and $and$issuer_ls180.v:129261$5848 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \p_valid_i$63 + connect \B \p_ready_o + connect \Y $and$issuer_ls180.v:129261$5848_Y + end + attribute \module_not_derived 1 + attribute \src "issuer_ls180.v:129314.14-129359.4" + cell \input$47 \input + connect \logical_op__data_len \input_logical_op__data_len + connect \logical_op__data_len$18 \input_logical_op__data_len$38 + connect \logical_op__fn_unit \input_logical_op__fn_unit + connect \logical_op__fn_unit$3 \input_logical_op__fn_unit$23 + connect \logical_op__imm_data__data \input_logical_op__imm_data__data + connect \logical_op__imm_data__data$4 \input_logical_op__imm_data__data$24 + connect \logical_op__imm_data__ok \input_logical_op__imm_data__ok + connect \logical_op__imm_data__ok$5 \input_logical_op__imm_data__ok$25 + connect \logical_op__input_carry \input_logical_op__input_carry + connect \logical_op__input_carry$12 \input_logical_op__input_carry$32 + connect \logical_op__insn \input_logical_op__insn + connect \logical_op__insn$19 \input_logical_op__insn$39 + connect \logical_op__insn_type \input_logical_op__insn_type + connect \logical_op__insn_type$2 \input_logical_op__insn_type$22 + connect \logical_op__invert_in \input_logical_op__invert_in + connect \logical_op__invert_in$10 \input_logical_op__invert_in$30 + connect \logical_op__invert_out \input_logical_op__invert_out + connect \logical_op__invert_out$13 \input_logical_op__invert_out$33 + connect \logical_op__is_32bit \input_logical_op__is_32bit + connect \logical_op__is_32bit$16 \input_logical_op__is_32bit$36 + connect \logical_op__is_signed \input_logical_op__is_signed + connect \logical_op__is_signed$17 \input_logical_op__is_signed$37 + connect \logical_op__oe__oe \input_logical_op__oe__oe + connect \logical_op__oe__oe$8 \input_logical_op__oe__oe$28 + connect \logical_op__oe__ok \input_logical_op__oe__ok + connect \logical_op__oe__ok$9 \input_logical_op__oe__ok$29 + connect \logical_op__output_carry \input_logical_op__output_carry + connect \logical_op__output_carry$15 \input_logical_op__output_carry$35 + connect \logical_op__rc__ok \input_logical_op__rc__ok + connect \logical_op__rc__ok$7 \input_logical_op__rc__ok$27 + connect \logical_op__rc__rc \input_logical_op__rc__rc + connect \logical_op__rc__rc$6 \input_logical_op__rc__rc$26 + connect \logical_op__write_cr0 \input_logical_op__write_cr0 + connect \logical_op__write_cr0$14 \input_logical_op__write_cr0$34 + connect \logical_op__zero_a \input_logical_op__zero_a + connect \logical_op__zero_a$11 \input_logical_op__zero_a$31 + connect \muxid \input_muxid + connect \muxid$1 \input_muxid$21 + connect \ra \input_ra + connect \ra$20 \input_ra$40 + connect \rb \input_rb + connect \rb$21 \input_rb$41 + connect \xer_so \input_xer_so + connect \xer_so$22 \input_xer_so$42 + end + attribute \module_not_derived 1 + attribute \src "issuer_ls180.v:129360.13-129405.4" + cell \main$48 \main + connect \logical_op__data_len \main_logical_op__data_len + connect \logical_op__data_len$18 \main_logical_op__data_len$60 + connect \logical_op__fn_unit \main_logical_op__fn_unit + connect \logical_op__fn_unit$3 \main_logical_op__fn_unit$45 + connect \logical_op__imm_data__data \main_logical_op__imm_data__data + connect \logical_op__imm_data__data$4 \main_logical_op__imm_data__data$46 + connect \logical_op__imm_data__ok \main_logical_op__imm_data__ok + connect \logical_op__imm_data__ok$5 \main_logical_op__imm_data__ok$47 + connect \logical_op__input_carry \main_logical_op__input_carry + connect \logical_op__input_carry$12 \main_logical_op__input_carry$54 + connect \logical_op__insn \main_logical_op__insn + connect \logical_op__insn$19 \main_logical_op__insn$61 + connect \logical_op__insn_type \main_logical_op__insn_type + connect \logical_op__insn_type$2 \main_logical_op__insn_type$44 + connect \logical_op__invert_in \main_logical_op__invert_in + connect \logical_op__invert_in$10 \main_logical_op__invert_in$52 + connect \logical_op__invert_out \main_logical_op__invert_out + connect \logical_op__invert_out$13 \main_logical_op__invert_out$55 + connect \logical_op__is_32bit \main_logical_op__is_32bit + connect \logical_op__is_32bit$16 \main_logical_op__is_32bit$58 + connect \logical_op__is_signed \main_logical_op__is_signed + connect \logical_op__is_signed$17 \main_logical_op__is_signed$59 + connect \logical_op__oe__oe \main_logical_op__oe__oe + connect \logical_op__oe__oe$8 \main_logical_op__oe__oe$50 + connect \logical_op__oe__ok \main_logical_op__oe__ok + connect \logical_op__oe__ok$9 \main_logical_op__oe__ok$51 + connect \logical_op__output_carry \main_logical_op__output_carry + connect \logical_op__output_carry$15 \main_logical_op__output_carry$57 + connect \logical_op__rc__ok \main_logical_op__rc__ok + connect \logical_op__rc__ok$7 \main_logical_op__rc__ok$49 + connect \logical_op__rc__rc \main_logical_op__rc__rc + connect \logical_op__rc__rc$6 \main_logical_op__rc__rc$48 + connect \logical_op__write_cr0 \main_logical_op__write_cr0 + connect \logical_op__write_cr0$14 \main_logical_op__write_cr0$56 + connect \logical_op__zero_a \main_logical_op__zero_a + connect \logical_op__zero_a$11 \main_logical_op__zero_a$53 + connect \muxid \main_muxid + connect \muxid$1 \main_muxid$43 + connect \o \main_o + connect \o_ok \main_o_ok + connect \ra \main_ra + connect \rb \main_rb + connect \xer_so \main_xer_so + connect \xer_so$20 \main_xer_so$62 + end + attribute \module_not_derived 1 + attribute \src "issuer_ls180.v:129406.10-129409.4" + cell \n$46 \n + connect \n_ready_i \n_ready_i + connect \n_valid_o \n_valid_o + end + attribute \module_not_derived 1 + attribute \src "issuer_ls180.v:129410.10-129413.4" + cell \p$45 \p + connect \p_ready_o \p_ready_o + connect \p_valid_i \p_valid_i + end + attribute \src "issuer_ls180.v:128198.7-128198.20" + process $proc$issuer_ls180.v:128198$5943 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "issuer_ls180.v:128207.13-128207.24" + process $proc$issuer_ls180.v:128207$5944 + assign { } { } + assign $1\cr_a[3:0] 4'0000 + sync always + sync init + update \cr_a $1\cr_a[3:0] + end + attribute \src "issuer_ls180.v:128216.7-128216.21" + process $proc$issuer_ls180.v:128216$5945 + assign { } { } + assign $1\cr_a_ok[0:0] 1'0 + sync always + sync init + update \cr_a_ok $1\cr_a_ok[0:0] + end + attribute \src "issuer_ls180.v:128495.13-128495.40" + process $proc$issuer_ls180.v:128495$5946 + assign { } { } + assign $1\logical_op__data_len[3:0] 4'0000 + sync always + sync init + update \logical_op__data_len $1\logical_op__data_len[3:0] + end + attribute \src "issuer_ls180.v:128517.14-128517.43" + process $proc$issuer_ls180.v:128517$5947 + assign { } { } + assign $1\logical_op__fn_unit[11:0] 12'000000000000 + sync always + sync init + update \logical_op__fn_unit $1\logical_op__fn_unit[11:0] + end + attribute \src "issuer_ls180.v:128552.14-128552.63" + process $proc$issuer_ls180.v:128552$5948 + assign { } { } + assign $1\logical_op__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \logical_op__imm_data__data $1\logical_op__imm_data__data[63:0] + end + attribute \src "issuer_ls180.v:128561.7-128561.38" + process $proc$issuer_ls180.v:128561$5949 + assign { } { } + assign $1\logical_op__imm_data__ok[0:0] 1'0 + sync always + sync init + update \logical_op__imm_data__ok $1\logical_op__imm_data__ok[0:0] + end + attribute \src "issuer_ls180.v:128574.13-128574.43" + process $proc$issuer_ls180.v:128574$5950 + assign { } { } + assign $1\logical_op__input_carry[1:0] 2'00 + sync always + sync init + update \logical_op__input_carry $1\logical_op__input_carry[1:0] + end + attribute \src "issuer_ls180.v:128591.14-128591.38" + process $proc$issuer_ls180.v:128591$5951 + assign { } { } + assign $1\logical_op__insn[31:0] 0 + sync always + sync init + update \logical_op__insn $1\logical_op__insn[31:0] + end + attribute \src "issuer_ls180.v:128674.13-128674.42" + process $proc$issuer_ls180.v:128674$5952 + assign { } { } + assign $1\logical_op__insn_type[6:0] 7'0000000 + sync always + sync init + update \logical_op__insn_type $1\logical_op__insn_type[6:0] + end + attribute \src "issuer_ls180.v:128831.7-128831.35" + process $proc$issuer_ls180.v:128831$5953 + assign { } { } + assign $1\logical_op__invert_in[0:0] 1'0 + sync always + sync init + update \logical_op__invert_in $1\logical_op__invert_in[0:0] + end + attribute \src "issuer_ls180.v:128840.7-128840.36" + process $proc$issuer_ls180.v:128840$5954 + assign { } { } + assign $1\logical_op__invert_out[0:0] 1'0 + sync always + sync init + update \logical_op__invert_out $1\logical_op__invert_out[0:0] + end + attribute \src "issuer_ls180.v:128849.7-128849.34" + process $proc$issuer_ls180.v:128849$5955 + assign { } { } + assign $1\logical_op__is_32bit[0:0] 1'0 + sync always + sync init + update \logical_op__is_32bit $1\logical_op__is_32bit[0:0] + end + attribute \src "issuer_ls180.v:128858.7-128858.35" + process $proc$issuer_ls180.v:128858$5956 + assign { } { } + assign $1\logical_op__is_signed[0:0] 1'0 + sync always + sync init + update \logical_op__is_signed $1\logical_op__is_signed[0:0] + end + attribute \src "issuer_ls180.v:128867.7-128867.32" + process $proc$issuer_ls180.v:128867$5957 + assign { } { } + assign $1\logical_op__oe__oe[0:0] 1'0 + sync always + sync init + update \logical_op__oe__oe $1\logical_op__oe__oe[0:0] + end + attribute \src "issuer_ls180.v:128876.7-128876.32" + process $proc$issuer_ls180.v:128876$5958 + assign { } { } + assign $1\logical_op__oe__ok[0:0] 1'0 + sync always + sync init + update \logical_op__oe__ok $1\logical_op__oe__ok[0:0] + end + attribute \src "issuer_ls180.v:128885.7-128885.38" + process $proc$issuer_ls180.v:128885$5959 + assign { } { } + assign $1\logical_op__output_carry[0:0] 1'0 + sync always + sync init + update \logical_op__output_carry $1\logical_op__output_carry[0:0] + end + attribute \src "issuer_ls180.v:128894.7-128894.32" + process $proc$issuer_ls180.v:128894$5960 + assign { } { } + assign $1\logical_op__rc__ok[0:0] 1'0 + sync always + sync init + update \logical_op__rc__ok $1\logical_op__rc__ok[0:0] + end + attribute \src "issuer_ls180.v:128903.7-128903.32" + process $proc$issuer_ls180.v:128903$5961 + assign { } { } + assign $1\logical_op__rc__rc[0:0] 1'0 + sync always + sync init + update \logical_op__rc__rc $1\logical_op__rc__rc[0:0] + end + attribute \src "issuer_ls180.v:128912.7-128912.35" + process $proc$issuer_ls180.v:128912$5962 + assign { } { } + assign $1\logical_op__write_cr0[0:0] 1'0 + sync always + sync init + update \logical_op__write_cr0 $1\logical_op__write_cr0[0:0] + end + attribute \src "issuer_ls180.v:128921.7-128921.32" + process $proc$issuer_ls180.v:128921$5963 + assign { } { } + assign $1\logical_op__zero_a[0:0] 1'0 + sync always + sync init + update \logical_op__zero_a $1\logical_op__zero_a[0:0] + end + attribute \src "issuer_ls180.v:129200.13-129200.25" + process $proc$issuer_ls180.v:129200$5964 + assign { } { } + assign $1\muxid[1:0] 2'00 + sync always + sync init + update \muxid $1\muxid[1:0] + end + attribute \src "issuer_ls180.v:129215.14-129215.38" + process $proc$issuer_ls180.v:129215$5965 + assign { } { } + assign $1\o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \o $1\o[63:0] + end + attribute \src "issuer_ls180.v:129222.7-129222.18" + process $proc$issuer_ls180.v:129222$5966 + assign { } { } + assign $1\o_ok[0:0] 1'0 + sync always + sync init + update \o_ok $1\o_ok[0:0] + end + attribute \src "issuer_ls180.v:129236.7-129236.20" + process $proc$issuer_ls180.v:129236$5967 + assign { } { } + assign $1\r_busy[0:0] 1'0 + sync always + sync init + update \r_busy $1\r_busy[0:0] + end + attribute \src "issuer_ls180.v:129245.7-129245.20" + process $proc$issuer_ls180.v:129245$5968 + assign { } { } + assign $1\xer_so[0:0] 1'0 + sync always + sync init + update \xer_so $1\xer_so[0:0] + end + attribute \src "issuer_ls180.v:129254.7-129254.23" + process $proc$issuer_ls180.v:129254$5969 + assign { } { } + assign $1\xer_so_ok[0:0] 1'0 + sync always + sync init + update \xer_so_ok $1\xer_so_ok[0:0] + end + attribute \src "issuer_ls180.v:129262.3-129263.29" + process $proc$issuer_ls180.v:129262$5849 + assign { } { } + assign $0\xer_so[0:0] \xer_so$next + sync posedge \coresync_clk + update \xer_so $0\xer_so[0:0] + end + attribute \src "issuer_ls180.v:129264.3-129265.35" + process $proc$issuer_ls180.v:129264$5850 + assign { } { } + assign $0\xer_so_ok[0:0] \xer_so_ok$next + sync posedge \coresync_clk + update \xer_so_ok $0\xer_so_ok[0:0] + end + attribute \src "issuer_ls180.v:129266.3-129267.25" + process $proc$issuer_ls180.v:129266$5851 + assign { } { } + assign $0\cr_a[3:0] \cr_a$next + sync posedge \coresync_clk + update \cr_a $0\cr_a[3:0] + end + attribute \src "issuer_ls180.v:129268.3-129269.31" + process $proc$issuer_ls180.v:129268$5852 + assign { } { } + assign $0\cr_a_ok[0:0] \cr_a_ok$next + sync posedge \coresync_clk + update \cr_a_ok $0\cr_a_ok[0:0] + end + attribute \src "issuer_ls180.v:129270.3-129271.19" + process $proc$issuer_ls180.v:129270$5853 + assign { } { } + assign $0\o[63:0] \o$next + sync posedge \coresync_clk + update \o $0\o[63:0] + end + attribute \src "issuer_ls180.v:129272.3-129273.25" + process $proc$issuer_ls180.v:129272$5854 + assign { } { } + assign $0\o_ok[0:0] \o_ok$next + sync posedge \coresync_clk + update \o_ok $0\o_ok[0:0] + end + attribute \src "issuer_ls180.v:129274.3-129275.59" + process $proc$issuer_ls180.v:129274$5855 + assign { } { } + assign $0\logical_op__insn_type[6:0] \logical_op__insn_type$next + sync posedge \coresync_clk + update \logical_op__insn_type $0\logical_op__insn_type[6:0] + end + attribute \src "issuer_ls180.v:129276.3-129277.55" + process $proc$issuer_ls180.v:129276$5856 + assign { } { } + assign $0\logical_op__fn_unit[11:0] \logical_op__fn_unit$next + sync posedge \coresync_clk + update \logical_op__fn_unit $0\logical_op__fn_unit[11:0] + end + attribute \src "issuer_ls180.v:129278.3-129279.69" + process $proc$issuer_ls180.v:129278$5857 + assign { } { } + assign $0\logical_op__imm_data__data[63:0] \logical_op__imm_data__data$next + sync posedge \coresync_clk + update \logical_op__imm_data__data $0\logical_op__imm_data__data[63:0] + end + attribute \src "issuer_ls180.v:129280.3-129281.65" + process $proc$issuer_ls180.v:129280$5858 + assign { } { } + assign $0\logical_op__imm_data__ok[0:0] \logical_op__imm_data__ok$next + sync posedge \coresync_clk + update \logical_op__imm_data__ok $0\logical_op__imm_data__ok[0:0] + end + attribute \src "issuer_ls180.v:129282.3-129283.53" + process $proc$issuer_ls180.v:129282$5859 + assign { } { } + assign $0\logical_op__rc__rc[0:0] \logical_op__rc__rc$next + sync posedge \coresync_clk + update \logical_op__rc__rc $0\logical_op__rc__rc[0:0] + end + attribute \src "issuer_ls180.v:129284.3-129285.53" + process $proc$issuer_ls180.v:129284$5860 + assign { } { } + assign $0\logical_op__rc__ok[0:0] \logical_op__rc__ok$next + sync posedge \coresync_clk + update \logical_op__rc__ok $0\logical_op__rc__ok[0:0] + end + attribute \src "issuer_ls180.v:129286.3-129287.53" + process $proc$issuer_ls180.v:129286$5861 + assign { } { } + assign $0\logical_op__oe__oe[0:0] \logical_op__oe__oe$next + sync posedge \coresync_clk + update \logical_op__oe__oe $0\logical_op__oe__oe[0:0] + end + attribute \src "issuer_ls180.v:129288.3-129289.53" + process $proc$issuer_ls180.v:129288$5862 + assign { } { } + assign $0\logical_op__oe__ok[0:0] \logical_op__oe__ok$next + sync posedge \coresync_clk + update \logical_op__oe__ok $0\logical_op__oe__ok[0:0] + end + attribute \src "issuer_ls180.v:129290.3-129291.59" + process $proc$issuer_ls180.v:129290$5863 + assign { } { } + assign $0\logical_op__invert_in[0:0] \logical_op__invert_in$next + sync posedge \coresync_clk + update \logical_op__invert_in $0\logical_op__invert_in[0:0] + end + attribute \src "issuer_ls180.v:129292.3-129293.53" + process $proc$issuer_ls180.v:129292$5864 + assign { } { } + assign $0\logical_op__zero_a[0:0] \logical_op__zero_a$next + sync posedge \coresync_clk + update \logical_op__zero_a $0\logical_op__zero_a[0:0] + end + attribute \src "issuer_ls180.v:129294.3-129295.63" + process $proc$issuer_ls180.v:129294$5865 + assign { } { } + assign $0\logical_op__input_carry[1:0] \logical_op__input_carry$next + sync posedge \coresync_clk + update \logical_op__input_carry $0\logical_op__input_carry[1:0] + end + attribute \src "issuer_ls180.v:129296.3-129297.61" + process $proc$issuer_ls180.v:129296$5866 + assign { } { } + assign $0\logical_op__invert_out[0:0] \logical_op__invert_out$next + sync posedge \coresync_clk + update \logical_op__invert_out $0\logical_op__invert_out[0:0] + end + attribute \src "issuer_ls180.v:129298.3-129299.59" + process $proc$issuer_ls180.v:129298$5867 + assign { } { } + assign $0\logical_op__write_cr0[0:0] \logical_op__write_cr0$next + sync posedge \coresync_clk + update \logical_op__write_cr0 $0\logical_op__write_cr0[0:0] + end + attribute \src "issuer_ls180.v:129300.3-129301.65" + process $proc$issuer_ls180.v:129300$5868 + assign { } { } + assign $0\logical_op__output_carry[0:0] \logical_op__output_carry$next + sync posedge \coresync_clk + update \logical_op__output_carry $0\logical_op__output_carry[0:0] + end + attribute \src "issuer_ls180.v:129302.3-129303.57" + process $proc$issuer_ls180.v:129302$5869 + assign { } { } + assign $0\logical_op__is_32bit[0:0] \logical_op__is_32bit$next + sync posedge \coresync_clk + update \logical_op__is_32bit $0\logical_op__is_32bit[0:0] + end + attribute \src "issuer_ls180.v:129304.3-129305.59" + process $proc$issuer_ls180.v:129304$5870 + assign { } { } + assign $0\logical_op__is_signed[0:0] \logical_op__is_signed$next + sync posedge \coresync_clk + update \logical_op__is_signed $0\logical_op__is_signed[0:0] + end + attribute \src "issuer_ls180.v:129306.3-129307.57" + process $proc$issuer_ls180.v:129306$5871 + assign { } { } + assign $0\logical_op__data_len[3:0] \logical_op__data_len$next + sync posedge \coresync_clk + update \logical_op__data_len $0\logical_op__data_len[3:0] + end + attribute \src "issuer_ls180.v:129308.3-129309.49" + process $proc$issuer_ls180.v:129308$5872 + assign { } { } + assign $0\logical_op__insn[31:0] \logical_op__insn$next + sync posedge \coresync_clk + update \logical_op__insn $0\logical_op__insn[31:0] + end + attribute \src "issuer_ls180.v:129310.3-129311.27" + process $proc$issuer_ls180.v:129310$5873 + assign { } { } + assign $0\muxid[1:0] \muxid$next + sync posedge \coresync_clk + update \muxid $0\muxid[1:0] + end + attribute \src "issuer_ls180.v:129312.3-129313.29" + process $proc$issuer_ls180.v:129312$5874 + assign { } { } + assign $0\r_busy[0:0] \r_busy$next + sync posedge \coresync_clk + update \r_busy $0\r_busy[0:0] + end + attribute \src "issuer_ls180.v:129414.3-129431.6" + process $proc$issuer_ls180.v:129414$5875 + assign { } { } + assign { } { } + assign { } { } + assign $0\r_busy$next[0:0]$5876 $2\r_busy$next[0:0]$5878 + attribute \src "issuer_ls180.v:129415.5-129415.29" + switch \initial + attribute \src "issuer_ls180.v:129415.9-129415.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\r_busy$next[0:0]$5877 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\r_busy$next[0:0]$5877 1'0 + case + assign $1\r_busy$next[0:0]$5877 \r_busy + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\r_busy$next[0:0]$5878 1'0 + case + assign $2\r_busy$next[0:0]$5878 $1\r_busy$next[0:0]$5877 + end + sync always + update \r_busy$next $0\r_busy$next[0:0]$5876 + end + attribute \src "issuer_ls180.v:129432.3-129444.6" + process $proc$issuer_ls180.v:129432$5879 + assign { } { } + assign { } { } + assign $0\muxid$next[1:0]$5880 $1\muxid$next[1:0]$5881 + attribute \src "issuer_ls180.v:129433.5-129433.29" + switch \initial + attribute \src "issuer_ls180.v:129433.9-129433.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\muxid$next[1:0]$5881 \muxid$66 + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\muxid$next[1:0]$5881 \muxid$66 + case + assign $1\muxid$next[1:0]$5881 \muxid + end + sync always + update \muxid$next $0\muxid$next[1:0]$5880 + end + attribute \src "issuer_ls180.v:129445.3-129486.6" + process $proc$issuer_ls180.v:129445$5882 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\logical_op__data_len$next[3:0]$5883 $1\logical_op__data_len$next[3:0]$5901 + assign $0\logical_op__fn_unit$next[11:0]$5884 $1\logical_op__fn_unit$next[11:0]$5902 + assign { } { } + assign { } { } + assign $0\logical_op__input_carry$next[1:0]$5887 $1\logical_op__input_carry$next[1:0]$5905 + assign $0\logical_op__insn$next[31:0]$5888 $1\logical_op__insn$next[31:0]$5906 + assign $0\logical_op__insn_type$next[6:0]$5889 $1\logical_op__insn_type$next[6:0]$5907 + assign $0\logical_op__invert_in$next[0:0]$5890 $1\logical_op__invert_in$next[0:0]$5908 + assign $0\logical_op__invert_out$next[0:0]$5891 $1\logical_op__invert_out$next[0:0]$5909 + assign $0\logical_op__is_32bit$next[0:0]$5892 $1\logical_op__is_32bit$next[0:0]$5910 + assign $0\logical_op__is_signed$next[0:0]$5893 $1\logical_op__is_signed$next[0:0]$5911 + assign { } { } + assign { } { } + assign $0\logical_op__output_carry$next[0:0]$5896 $1\logical_op__output_carry$next[0:0]$5914 + assign { } { } + assign { } { } + assign $0\logical_op__write_cr0$next[0:0]$5899 $1\logical_op__write_cr0$next[0:0]$5917 + assign $0\logical_op__zero_a$next[0:0]$5900 $1\logical_op__zero_a$next[0:0]$5918 + assign $0\logical_op__imm_data__data$next[63:0]$5885 $2\logical_op__imm_data__data$next[63:0]$5919 + assign $0\logical_op__imm_data__ok$next[0:0]$5886 $2\logical_op__imm_data__ok$next[0:0]$5920 + assign $0\logical_op__oe__oe$next[0:0]$5894 $2\logical_op__oe__oe$next[0:0]$5921 + assign $0\logical_op__oe__ok$next[0:0]$5895 $2\logical_op__oe__ok$next[0:0]$5922 + assign $0\logical_op__rc__ok$next[0:0]$5897 $2\logical_op__rc__ok$next[0:0]$5923 + assign $0\logical_op__rc__rc$next[0:0]$5898 $2\logical_op__rc__rc$next[0:0]$5924 + attribute \src "issuer_ls180.v:129446.5-129446.29" + switch \initial + attribute \src "issuer_ls180.v:129446.9-129446.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'-1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { $1\logical_op__insn$next[31:0]$5906 $1\logical_op__data_len$next[3:0]$5901 $1\logical_op__is_signed$next[0:0]$5911 $1\logical_op__is_32bit$next[0:0]$5910 $1\logical_op__output_carry$next[0:0]$5914 $1\logical_op__write_cr0$next[0:0]$5917 $1\logical_op__invert_out$next[0:0]$5909 $1\logical_op__input_carry$next[1:0]$5905 $1\logical_op__zero_a$next[0:0]$5918 $1\logical_op__invert_in$next[0:0]$5908 $1\logical_op__oe__ok$next[0:0]$5913 $1\logical_op__oe__oe$next[0:0]$5912 $1\logical_op__rc__ok$next[0:0]$5915 $1\logical_op__rc__rc$next[0:0]$5916 $1\logical_op__imm_data__ok$next[0:0]$5904 $1\logical_op__imm_data__data$next[63:0]$5903 $1\logical_op__fn_unit$next[11:0]$5902 $1\logical_op__insn_type$next[6:0]$5907 } { \logical_op__insn$84 \logical_op__data_len$83 \logical_op__is_signed$82 \logical_op__is_32bit$81 \logical_op__output_carry$80 \logical_op__write_cr0$79 \logical_op__invert_out$78 \logical_op__input_carry$77 \logical_op__zero_a$76 \logical_op__invert_in$75 \logical_op__oe__ok$74 \logical_op__oe__oe$73 \logical_op__rc__ok$72 \logical_op__rc__rc$71 \logical_op__imm_data__ok$70 \logical_op__imm_data__data$69 \logical_op__fn_unit$68 \logical_op__insn_type$67 } + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'1- + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { $1\logical_op__insn$next[31:0]$5906 $1\logical_op__data_len$next[3:0]$5901 $1\logical_op__is_signed$next[0:0]$5911 $1\logical_op__is_32bit$next[0:0]$5910 $1\logical_op__output_carry$next[0:0]$5914 $1\logical_op__write_cr0$next[0:0]$5917 $1\logical_op__invert_out$next[0:0]$5909 $1\logical_op__input_carry$next[1:0]$5905 $1\logical_op__zero_a$next[0:0]$5918 $1\logical_op__invert_in$next[0:0]$5908 $1\logical_op__oe__ok$next[0:0]$5913 $1\logical_op__oe__oe$next[0:0]$5912 $1\logical_op__rc__ok$next[0:0]$5915 $1\logical_op__rc__rc$next[0:0]$5916 $1\logical_op__imm_data__ok$next[0:0]$5904 $1\logical_op__imm_data__data$next[63:0]$5903 $1\logical_op__fn_unit$next[11:0]$5902 $1\logical_op__insn_type$next[6:0]$5907 } { \logical_op__insn$84 \logical_op__data_len$83 \logical_op__is_signed$82 \logical_op__is_32bit$81 \logical_op__output_carry$80 \logical_op__write_cr0$79 \logical_op__invert_out$78 \logical_op__input_carry$77 \logical_op__zero_a$76 \logical_op__invert_in$75 \logical_op__oe__ok$74 \logical_op__oe__oe$73 \logical_op__rc__ok$72 \logical_op__rc__rc$71 \logical_op__imm_data__ok$70 \logical_op__imm_data__data$69 \logical_op__fn_unit$68 \logical_op__insn_type$67 } + case + assign $1\logical_op__data_len$next[3:0]$5901 \logical_op__data_len + assign $1\logical_op__fn_unit$next[11:0]$5902 \logical_op__fn_unit + assign $1\logical_op__imm_data__data$next[63:0]$5903 \logical_op__imm_data__data + assign $1\logical_op__imm_data__ok$next[0:0]$5904 \logical_op__imm_data__ok + assign $1\logical_op__input_carry$next[1:0]$5905 \logical_op__input_carry + assign $1\logical_op__insn$next[31:0]$5906 \logical_op__insn + assign $1\logical_op__insn_type$next[6:0]$5907 \logical_op__insn_type + assign $1\logical_op__invert_in$next[0:0]$5908 \logical_op__invert_in + assign $1\logical_op__invert_out$next[0:0]$5909 \logical_op__invert_out + assign $1\logical_op__is_32bit$next[0:0]$5910 \logical_op__is_32bit + assign $1\logical_op__is_signed$next[0:0]$5911 \logical_op__is_signed + assign $1\logical_op__oe__oe$next[0:0]$5912 \logical_op__oe__oe + assign $1\logical_op__oe__ok$next[0:0]$5913 \logical_op__oe__ok + assign $1\logical_op__output_carry$next[0:0]$5914 \logical_op__output_carry + assign $1\logical_op__rc__ok$next[0:0]$5915 \logical_op__rc__ok + assign $1\logical_op__rc__rc$next[0:0]$5916 \logical_op__rc__rc + assign $1\logical_op__write_cr0$next[0:0]$5917 \logical_op__write_cr0 + assign $1\logical_op__zero_a$next[0:0]$5918 \logical_op__zero_a + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $2\logical_op__imm_data__data$next[63:0]$5919 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\logical_op__imm_data__ok$next[0:0]$5920 1'0 + assign $2\logical_op__rc__rc$next[0:0]$5924 1'0 + assign $2\logical_op__rc__ok$next[0:0]$5923 1'0 + assign $2\logical_op__oe__oe$next[0:0]$5921 1'0 + assign $2\logical_op__oe__ok$next[0:0]$5922 1'0 + case + assign $2\logical_op__imm_data__data$next[63:0]$5919 $1\logical_op__imm_data__data$next[63:0]$5903 + assign $2\logical_op__imm_data__ok$next[0:0]$5920 $1\logical_op__imm_data__ok$next[0:0]$5904 + assign $2\logical_op__oe__oe$next[0:0]$5921 $1\logical_op__oe__oe$next[0:0]$5912 + assign $2\logical_op__oe__ok$next[0:0]$5922 $1\logical_op__oe__ok$next[0:0]$5913 + assign $2\logical_op__rc__ok$next[0:0]$5923 $1\logical_op__rc__ok$next[0:0]$5915 + assign $2\logical_op__rc__rc$next[0:0]$5924 $1\logical_op__rc__rc$next[0:0]$5916 + end + sync always + update \logical_op__data_len$next $0\logical_op__data_len$next[3:0]$5883 + update \logical_op__fn_unit$next $0\logical_op__fn_unit$next[11:0]$5884 + update \logical_op__imm_data__data$next $0\logical_op__imm_data__data$next[63:0]$5885 + update \logical_op__imm_data__ok$next $0\logical_op__imm_data__ok$next[0:0]$5886 + update \logical_op__input_carry$next $0\logical_op__input_carry$next[1:0]$5887 + update \logical_op__insn$next $0\logical_op__insn$next[31:0]$5888 + update \logical_op__insn_type$next $0\logical_op__insn_type$next[6:0]$5889 + update \logical_op__invert_in$next $0\logical_op__invert_in$next[0:0]$5890 + update \logical_op__invert_out$next $0\logical_op__invert_out$next[0:0]$5891 + update \logical_op__is_32bit$next $0\logical_op__is_32bit$next[0:0]$5892 + update \logical_op__is_signed$next $0\logical_op__is_signed$next[0:0]$5893 + update \logical_op__oe__oe$next $0\logical_op__oe__oe$next[0:0]$5894 + update \logical_op__oe__ok$next $0\logical_op__oe__ok$next[0:0]$5895 + update \logical_op__output_carry$next $0\logical_op__output_carry$next[0:0]$5896 + update \logical_op__rc__ok$next $0\logical_op__rc__ok$next[0:0]$5897 + update \logical_op__rc__rc$next $0\logical_op__rc__rc$next[0:0]$5898 + update \logical_op__write_cr0$next $0\logical_op__write_cr0$next[0:0]$5899 + update \logical_op__zero_a$next $0\logical_op__zero_a$next[0:0]$5900 + end + attribute \src "issuer_ls180.v:129487.3-129505.6" + process $proc$issuer_ls180.v:129487$5925 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\o$next[63:0]$5926 $1\o$next[63:0]$5928 + assign { } { } + assign $0\o_ok$next[0:0]$5927 $2\o_ok$next[0:0]$5930 + attribute \src "issuer_ls180.v:129488.5-129488.29" + switch \initial + attribute \src "issuer_ls180.v:129488.9-129488.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'-1 + assign { } { } + assign { } { } + assign { $1\o_ok$next[0:0]$5929 $1\o$next[63:0]$5928 } { \o_ok$86 \o$85 } + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'1- + assign { } { } + assign { } { } + assign { $1\o_ok$next[0:0]$5929 $1\o$next[63:0]$5928 } { \o_ok$86 \o$85 } + case + assign $1\o$next[63:0]$5928 \o + assign $1\o_ok$next[0:0]$5929 \o_ok + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\o_ok$next[0:0]$5930 1'0 + case + assign $2\o_ok$next[0:0]$5930 $1\o_ok$next[0:0]$5929 + end + sync always + update \o$next $0\o$next[63:0]$5926 + update \o_ok$next $0\o_ok$next[0:0]$5927 + end + attribute \src "issuer_ls180.v:129506.3-129524.6" + process $proc$issuer_ls180.v:129506$5931 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\cr_a$next[3:0]$5932 $1\cr_a$next[3:0]$5934 + assign { } { } + assign $0\cr_a_ok$next[0:0]$5933 $2\cr_a_ok$next[0:0]$5936 + attribute \src "issuer_ls180.v:129507.5-129507.29" + switch \initial + attribute \src "issuer_ls180.v:129507.9-129507.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'-1 + assign { } { } + assign { } { } + assign { $1\cr_a_ok$next[0:0]$5935 $1\cr_a$next[3:0]$5934 } { \cr_a_ok$88 \cr_a$87 } + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'1- + assign { } { } + assign { } { } + assign { $1\cr_a_ok$next[0:0]$5935 $1\cr_a$next[3:0]$5934 } { \cr_a_ok$88 \cr_a$87 } + case + assign $1\cr_a$next[3:0]$5934 \cr_a + assign $1\cr_a_ok$next[0:0]$5935 \cr_a_ok + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\cr_a_ok$next[0:0]$5936 1'0 + case + assign $2\cr_a_ok$next[0:0]$5936 $1\cr_a_ok$next[0:0]$5935 + end + sync always + update \cr_a$next $0\cr_a$next[3:0]$5932 + update \cr_a_ok$next $0\cr_a_ok$next[0:0]$5933 + end + attribute \src "issuer_ls180.v:129525.3-129543.6" + process $proc$issuer_ls180.v:129525$5937 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\xer_so$next[0:0]$5938 $1\xer_so$next[0:0]$5940 + assign { } { } + assign $0\xer_so_ok$next[0:0]$5939 $2\xer_so_ok$next[0:0]$5942 + attribute \src "issuer_ls180.v:129526.5-129526.29" + switch \initial + attribute \src "issuer_ls180.v:129526.9-129526.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'-1 + assign { } { } + assign { } { } + assign { $1\xer_so_ok$next[0:0]$5941 $1\xer_so$next[0:0]$5940 } { \xer_so_ok$92 \xer_so$91 } + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'1- + assign { } { } + assign { } { } + assign { $1\xer_so_ok$next[0:0]$5941 $1\xer_so$next[0:0]$5940 } { \xer_so_ok$92 \xer_so$91 } + case + assign $1\xer_so$next[0:0]$5940 \xer_so + assign $1\xer_so_ok$next[0:0]$5941 \xer_so_ok + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\xer_so_ok$next[0:0]$5942 1'0 + case + assign $2\xer_so_ok$next[0:0]$5942 $1\xer_so_ok$next[0:0]$5941 + end + sync always + update \xer_so$next $0\xer_so$next[0:0]$5938 + update \xer_so_ok$next $0\xer_so_ok$next[0:0]$5939 + end + connect \$64 $and$issuer_ls180.v:129261$5848_Y + connect \cr_a$89 4'0000 + connect \cr_a_ok$90 1'0 + connect \xer_so_ok$93 1'0 + connect \p_ready_o \n_i_rdy_data + connect \n_valid_o \r_busy + connect { \xer_so_ok$92 \xer_so$91 } { 1'0 \main_xer_so$62 } + connect { \cr_a_ok$88 \cr_a$87 } 5'00000 + connect { \o_ok$86 \o$85 } { \main_o_ok \main_o } + connect { \logical_op__insn$84 \logical_op__data_len$83 \logical_op__is_signed$82 \logical_op__is_32bit$81 \logical_op__output_carry$80 \logical_op__write_cr0$79 \logical_op__invert_out$78 \logical_op__input_carry$77 \logical_op__zero_a$76 \logical_op__invert_in$75 \logical_op__oe__ok$74 \logical_op__oe__oe$73 \logical_op__rc__ok$72 \logical_op__rc__rc$71 \logical_op__imm_data__ok$70 \logical_op__imm_data__data$69 \logical_op__fn_unit$68 \logical_op__insn_type$67 } { \main_logical_op__insn$61 \main_logical_op__data_len$60 \main_logical_op__is_signed$59 \main_logical_op__is_32bit$58 \main_logical_op__output_carry$57 \main_logical_op__write_cr0$56 \main_logical_op__invert_out$55 \main_logical_op__input_carry$54 \main_logical_op__zero_a$53 \main_logical_op__invert_in$52 \main_logical_op__oe__ok$51 \main_logical_op__oe__oe$50 \main_logical_op__rc__ok$49 \main_logical_op__rc__rc$48 \main_logical_op__imm_data__ok$47 \main_logical_op__imm_data__data$46 \main_logical_op__fn_unit$45 \main_logical_op__insn_type$44 } + connect \muxid$66 \main_muxid$43 + connect \p_valid_i_p_ready_o \$64 + connect \n_i_rdy_data \n_ready_i + connect \p_valid_i$63 \p_valid_i + connect \main_xer_so \input_xer_so$42 + connect \main_rb \input_rb$41 + connect \main_ra \input_ra$40 + connect { \main_logical_op__insn \main_logical_op__data_len \main_logical_op__is_signed \main_logical_op__is_32bit \main_logical_op__output_carry \main_logical_op__write_cr0 \main_logical_op__invert_out \main_logical_op__input_carry \main_logical_op__zero_a \main_logical_op__invert_in \main_logical_op__oe__ok \main_logical_op__oe__oe \main_logical_op__rc__ok \main_logical_op__rc__rc \main_logical_op__imm_data__ok \main_logical_op__imm_data__data \main_logical_op__fn_unit \main_logical_op__insn_type } { \input_logical_op__insn$39 \input_logical_op__data_len$38 \input_logical_op__is_signed$37 \input_logical_op__is_32bit$36 \input_logical_op__output_carry$35 \input_logical_op__write_cr0$34 \input_logical_op__invert_out$33 \input_logical_op__input_carry$32 \input_logical_op__zero_a$31 \input_logical_op__invert_in$30 \input_logical_op__oe__ok$29 \input_logical_op__oe__oe$28 \input_logical_op__rc__ok$27 \input_logical_op__rc__rc$26 \input_logical_op__imm_data__ok$25 \input_logical_op__imm_data__data$24 \input_logical_op__fn_unit$23 \input_logical_op__insn_type$22 } + connect \main_muxid \input_muxid$21 + connect \input_xer_so \xer_so$20 + connect \input_rb \rb + connect \input_ra \ra + connect { \input_logical_op__insn \input_logical_op__data_len \input_logical_op__is_signed \input_logical_op__is_32bit \input_logical_op__output_carry \input_logical_op__write_cr0 \input_logical_op__invert_out \input_logical_op__input_carry \input_logical_op__zero_a \input_logical_op__invert_in \input_logical_op__oe__ok \input_logical_op__oe__oe \input_logical_op__rc__ok \input_logical_op__rc__rc \input_logical_op__imm_data__ok \input_logical_op__imm_data__data \input_logical_op__fn_unit \input_logical_op__insn_type } { \logical_op__insn$19 \logical_op__data_len$18 \logical_op__is_signed$17 \logical_op__is_32bit$16 \logical_op__output_carry$15 \logical_op__write_cr0$14 \logical_op__invert_out$13 \logical_op__input_carry$12 \logical_op__zero_a$11 \logical_op__invert_in$10 \logical_op__oe__ok$9 \logical_op__oe__oe$8 \logical_op__rc__ok$7 \logical_op__rc__rc$6 \logical_op__imm_data__ok$5 \logical_op__imm_data__data$4 \logical_op__fn_unit$3 \logical_op__insn_type$2 } + connect \input_muxid \muxid$1 +end +attribute \src "issuer_ls180.v:129571.1-130589.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.fus.logical0.alu_logical0.logical_pipe2" +attribute \generator "nMigen" +module \logical_pipe2 + attribute \src "issuer_ls180.v:130556.3-130574.6" + wire width 4 $0\cr_a$22$next[3:0]$6075 + attribute \src "issuer_ls180.v:130360.3-130361.33" + wire width 4 $0\cr_a$22[3:0]$5972 + attribute \src "issuer_ls180.v:129583.13-129583.29" + wire width 4 $0\cr_a$22[3:0]$6082 + attribute \src "issuer_ls180.v:130556.3-130574.6" + wire $0\cr_a_ok$23$next[0:0]$6076 + attribute \src "issuer_ls180.v:130362.3-130363.39" + wire $0\cr_a_ok$23[0:0]$5974 + attribute \src "issuer_ls180.v:129592.7-129592.26" + wire $0\cr_a_ok$23[0:0]$6084 + attribute \src "issuer_ls180.v:129572.7-129572.20" + wire $0\initial[0:0] + attribute \src "issuer_ls180.v:130495.3-130536.6" + wire width 4 $0\logical_op__data_len$18$next[3:0]$6026 + attribute \src "issuer_ls180.v:130400.3-130401.65" + wire width 4 $0\logical_op__data_len$18[3:0]$6012 + attribute \src "issuer_ls180.v:129603.13-129603.45" + wire width 4 $0\logical_op__data_len$18[3:0]$6086 + attribute \src "issuer_ls180.v:130495.3-130536.6" + wire width 12 $0\logical_op__fn_unit$3$next[11:0]$6027 + attribute \src "issuer_ls180.v:130370.3-130371.61" + wire width 12 $0\logical_op__fn_unit$3[11:0]$5982 + attribute \src "issuer_ls180.v:129638.14-129638.47" + wire width 12 $0\logical_op__fn_unit$3[11:0]$6088 + attribute \src "issuer_ls180.v:130495.3-130536.6" + wire width 64 $0\logical_op__imm_data__data$4$next[63:0]$6028 + attribute \src "issuer_ls180.v:130372.3-130373.75" + wire width 64 $0\logical_op__imm_data__data$4[63:0]$5984 + attribute \src "issuer_ls180.v:129660.14-129660.67" + wire width 64 $0\logical_op__imm_data__data$4[63:0]$6090 + attribute \src "issuer_ls180.v:130495.3-130536.6" + wire $0\logical_op__imm_data__ok$5$next[0:0]$6029 + attribute \src "issuer_ls180.v:130374.3-130375.71" + wire $0\logical_op__imm_data__ok$5[0:0]$5986 + attribute \src "issuer_ls180.v:129669.7-129669.42" + wire $0\logical_op__imm_data__ok$5[0:0]$6092 + attribute \src "issuer_ls180.v:130495.3-130536.6" + wire width 2 $0\logical_op__input_carry$12$next[1:0]$6030 + attribute \src "issuer_ls180.v:130388.3-130389.71" + wire width 2 $0\logical_op__input_carry$12[1:0]$6000 + attribute \src "issuer_ls180.v:129686.13-129686.48" + wire width 2 $0\logical_op__input_carry$12[1:0]$6094 + attribute \src "issuer_ls180.v:130495.3-130536.6" + wire width 32 $0\logical_op__insn$19$next[31:0]$6031 + attribute \src "issuer_ls180.v:130402.3-130403.57" + wire width 32 $0\logical_op__insn$19[31:0]$6014 + attribute \src "issuer_ls180.v:129699.14-129699.43" + wire width 32 $0\logical_op__insn$19[31:0]$6096 + attribute \src "issuer_ls180.v:130495.3-130536.6" + wire width 7 $0\logical_op__insn_type$2$next[6:0]$6032 + attribute \src "issuer_ls180.v:130368.3-130369.65" + wire width 7 $0\logical_op__insn_type$2[6:0]$5980 + attribute \src "issuer_ls180.v:129856.13-129856.46" + wire width 7 $0\logical_op__insn_type$2[6:0]$6098 + attribute \src "issuer_ls180.v:130495.3-130536.6" + wire $0\logical_op__invert_in$10$next[0:0]$6033 + attribute \src "issuer_ls180.v:130384.3-130385.67" + wire $0\logical_op__invert_in$10[0:0]$5996 + attribute \src "issuer_ls180.v:129939.7-129939.40" + wire $0\logical_op__invert_in$10[0:0]$6100 + attribute \src "issuer_ls180.v:130495.3-130536.6" + wire $0\logical_op__invert_out$13$next[0:0]$6034 + attribute \src "issuer_ls180.v:130390.3-130391.69" + wire $0\logical_op__invert_out$13[0:0]$6002 + attribute \src "issuer_ls180.v:129948.7-129948.41" + wire $0\logical_op__invert_out$13[0:0]$6102 + attribute \src "issuer_ls180.v:130495.3-130536.6" + wire $0\logical_op__is_32bit$16$next[0:0]$6035 + attribute \src "issuer_ls180.v:130396.3-130397.65" + wire $0\logical_op__is_32bit$16[0:0]$6008 + attribute \src "issuer_ls180.v:129957.7-129957.39" + wire $0\logical_op__is_32bit$16[0:0]$6104 + attribute \src "issuer_ls180.v:130495.3-130536.6" + wire $0\logical_op__is_signed$17$next[0:0]$6036 + attribute \src "issuer_ls180.v:130398.3-130399.67" + wire $0\logical_op__is_signed$17[0:0]$6010 + attribute \src "issuer_ls180.v:129966.7-129966.40" + wire $0\logical_op__is_signed$17[0:0]$6106 + attribute \src "issuer_ls180.v:130495.3-130536.6" + wire $0\logical_op__oe__oe$8$next[0:0]$6037 + attribute \src "issuer_ls180.v:130380.3-130381.59" + wire $0\logical_op__oe__oe$8[0:0]$5992 + attribute \src "issuer_ls180.v:129977.7-129977.36" + wire $0\logical_op__oe__oe$8[0:0]$6108 + attribute \src "issuer_ls180.v:130495.3-130536.6" + wire $0\logical_op__oe__ok$9$next[0:0]$6038 + attribute \src "issuer_ls180.v:130382.3-130383.59" + wire $0\logical_op__oe__ok$9[0:0]$5994 + attribute \src "issuer_ls180.v:129986.7-129986.36" + wire $0\logical_op__oe__ok$9[0:0]$6110 + attribute \src "issuer_ls180.v:130495.3-130536.6" + wire $0\logical_op__output_carry$15$next[0:0]$6039 + attribute \src "issuer_ls180.v:130394.3-130395.73" + wire $0\logical_op__output_carry$15[0:0]$6006 + attribute \src "issuer_ls180.v:129993.7-129993.43" + wire $0\logical_op__output_carry$15[0:0]$6112 + attribute \src "issuer_ls180.v:130495.3-130536.6" + wire $0\logical_op__rc__ok$7$next[0:0]$6040 + attribute \src "issuer_ls180.v:130378.3-130379.59" + wire $0\logical_op__rc__ok$7[0:0]$5990 + attribute \src "issuer_ls180.v:130004.7-130004.36" + wire $0\logical_op__rc__ok$7[0:0]$6114 + attribute \src "issuer_ls180.v:130495.3-130536.6" + wire $0\logical_op__rc__rc$6$next[0:0]$6041 + attribute \src "issuer_ls180.v:130376.3-130377.59" + wire $0\logical_op__rc__rc$6[0:0]$5988 + attribute \src "issuer_ls180.v:130013.7-130013.36" + wire $0\logical_op__rc__rc$6[0:0]$6116 + attribute \src "issuer_ls180.v:130495.3-130536.6" + wire $0\logical_op__write_cr0$14$next[0:0]$6042 + attribute \src "issuer_ls180.v:130392.3-130393.67" + wire $0\logical_op__write_cr0$14[0:0]$6004 + attribute \src "issuer_ls180.v:130020.7-130020.40" + wire $0\logical_op__write_cr0$14[0:0]$6118 + attribute \src "issuer_ls180.v:130495.3-130536.6" + wire $0\logical_op__zero_a$11$next[0:0]$6043 + attribute \src "issuer_ls180.v:130386.3-130387.61" + wire $0\logical_op__zero_a$11[0:0]$5998 + attribute \src "issuer_ls180.v:130029.7-130029.37" + wire $0\logical_op__zero_a$11[0:0]$6120 + attribute \src "issuer_ls180.v:130482.3-130494.6" + wire width 2 $0\muxid$1$next[1:0]$6023 + attribute \src "issuer_ls180.v:130404.3-130405.33" + wire width 2 $0\muxid$1[1:0]$6016 + attribute \src "issuer_ls180.v:130038.13-130038.29" + wire width 2 $0\muxid$1[1:0]$6122 + attribute \src "issuer_ls180.v:130537.3-130555.6" + wire width 64 $0\o$20$next[63:0]$6069 + attribute \src "issuer_ls180.v:130364.3-130365.27" + wire width 64 $0\o$20[63:0]$5976 + attribute \src "issuer_ls180.v:130053.14-130053.43" + wire width 64 $0\o$20[63:0]$6124 + attribute \src "issuer_ls180.v:130537.3-130555.6" + wire $0\o_ok$21$next[0:0]$6070 + attribute \src "issuer_ls180.v:130366.3-130367.33" + wire $0\o_ok$21[0:0]$5978 + attribute \src "issuer_ls180.v:130062.7-130062.23" + wire $0\o_ok$21[0:0]$6126 + attribute \src "issuer_ls180.v:130464.3-130481.6" + wire $0\r_busy$next[0:0]$6019 + attribute \src "issuer_ls180.v:130406.3-130407.29" + wire $0\r_busy[0:0] + attribute \src "issuer_ls180.v:130556.3-130574.6" + wire width 4 $1\cr_a$22$next[3:0]$6077 + attribute \src "issuer_ls180.v:130556.3-130574.6" + wire $1\cr_a_ok$23$next[0:0]$6078 + attribute \src "issuer_ls180.v:130495.3-130536.6" + wire width 4 $1\logical_op__data_len$18$next[3:0]$6044 + attribute \src "issuer_ls180.v:130495.3-130536.6" + wire width 12 $1\logical_op__fn_unit$3$next[11:0]$6045 + attribute \src "issuer_ls180.v:130495.3-130536.6" + wire width 64 $1\logical_op__imm_data__data$4$next[63:0]$6046 + attribute \src "issuer_ls180.v:130495.3-130536.6" + wire $1\logical_op__imm_data__ok$5$next[0:0]$6047 + attribute \src "issuer_ls180.v:130495.3-130536.6" + wire width 2 $1\logical_op__input_carry$12$next[1:0]$6048 + attribute \src "issuer_ls180.v:130495.3-130536.6" + wire width 32 $1\logical_op__insn$19$next[31:0]$6049 + attribute \src "issuer_ls180.v:130495.3-130536.6" + wire width 7 $1\logical_op__insn_type$2$next[6:0]$6050 + attribute \src "issuer_ls180.v:130495.3-130536.6" + wire $1\logical_op__invert_in$10$next[0:0]$6051 + attribute \src "issuer_ls180.v:130495.3-130536.6" + wire $1\logical_op__invert_out$13$next[0:0]$6052 + attribute \src "issuer_ls180.v:130495.3-130536.6" + wire $1\logical_op__is_32bit$16$next[0:0]$6053 + attribute \src "issuer_ls180.v:130495.3-130536.6" + wire $1\logical_op__is_signed$17$next[0:0]$6054 + attribute \src "issuer_ls180.v:130495.3-130536.6" + wire $1\logical_op__oe__oe$8$next[0:0]$6055 + attribute \src "issuer_ls180.v:130495.3-130536.6" + wire $1\logical_op__oe__ok$9$next[0:0]$6056 + attribute \src "issuer_ls180.v:130495.3-130536.6" + wire $1\logical_op__output_carry$15$next[0:0]$6057 + attribute \src "issuer_ls180.v:130495.3-130536.6" + wire $1\logical_op__rc__ok$7$next[0:0]$6058 + attribute \src "issuer_ls180.v:130495.3-130536.6" + wire $1\logical_op__rc__rc$6$next[0:0]$6059 + attribute \src "issuer_ls180.v:130495.3-130536.6" + wire $1\logical_op__write_cr0$14$next[0:0]$6060 + attribute \src "issuer_ls180.v:130495.3-130536.6" + wire $1\logical_op__zero_a$11$next[0:0]$6061 + attribute \src "issuer_ls180.v:130482.3-130494.6" + wire width 2 $1\muxid$1$next[1:0]$6024 + attribute \src "issuer_ls180.v:130537.3-130555.6" + wire width 64 $1\o$20$next[63:0]$6071 + attribute \src "issuer_ls180.v:130537.3-130555.6" + wire $1\o_ok$21$next[0:0]$6072 + attribute \src "issuer_ls180.v:130464.3-130481.6" + wire $1\r_busy$next[0:0]$6020 + attribute \src "issuer_ls180.v:130350.7-130350.20" + wire $1\r_busy[0:0] + attribute \src "issuer_ls180.v:130556.3-130574.6" + wire $2\cr_a_ok$23$next[0:0]$6079 + attribute \src "issuer_ls180.v:130495.3-130536.6" + wire width 64 $2\logical_op__imm_data__data$4$next[63:0]$6062 + attribute \src "issuer_ls180.v:130495.3-130536.6" + wire $2\logical_op__imm_data__ok$5$next[0:0]$6063 + attribute \src "issuer_ls180.v:130495.3-130536.6" + wire $2\logical_op__oe__oe$8$next[0:0]$6064 + attribute \src "issuer_ls180.v:130495.3-130536.6" + wire $2\logical_op__oe__ok$9$next[0:0]$6065 + attribute \src "issuer_ls180.v:130495.3-130536.6" + wire $2\logical_op__rc__ok$7$next[0:0]$6066 + attribute \src "issuer_ls180.v:130495.3-130536.6" + wire $2\logical_op__rc__rc$6$next[0:0]$6067 + attribute \src "issuer_ls180.v:130537.3-130555.6" + wire $2\o_ok$21$next[0:0]$6073 + attribute \src "issuer_ls180.v:130464.3-130481.6" + wire $2\r_busy$next[0:0]$6021 + attribute \src "issuer_ls180.v:130359.18-130359.118" + wire $and$issuer_ls180.v:130359$5970_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" + wire \$49 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" + wire input 54 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" + wire input 1 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 4 input 25 \cr_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 4 output 52 \cr_a$22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 4 \cr_a$22$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 4 \cr_a$72 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire input 26 \cr_a_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 53 \cr_a_ok$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \cr_a_ok$23$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \cr_a_ok$46 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \cr_a_ok$73 + attribute \src "issuer_ls180.v:129572.7-129572.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 input 21 \logical_op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 output 48 \logical_op__data_len$18 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \logical_op__data_len$18$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \logical_op__data_len$68 + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 input 6 \logical_op__fn_unit + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 output 33 \logical_op__fn_unit$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 \logical_op__fn_unit$3$next + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 \logical_op__fn_unit$53 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 input 7 \logical_op__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 output 34 \logical_op__imm_data__data$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \logical_op__imm_data__data$4$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \logical_op__imm_data__data$54 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 8 \logical_op__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 35 \logical_op__imm_data__ok$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__imm_data__ok$5$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__imm_data__ok$55 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 input 15 \logical_op__input_carry + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 output 42 \logical_op__input_carry$12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \logical_op__input_carry$12$next + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \logical_op__input_carry$62 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 22 \logical_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 output 49 \logical_op__insn$19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \logical_op__insn$19$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \logical_op__insn$69 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 input 5 \logical_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 output 32 \logical_op__insn_type$2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \logical_op__insn_type$2$next + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \logical_op__insn_type$52 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 13 \logical_op__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 40 \logical_op__invert_in$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__invert_in$10$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__invert_in$60 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 16 \logical_op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 43 \logical_op__invert_out$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__invert_out$13$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__invert_out$63 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 19 \logical_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 46 \logical_op__is_32bit$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__is_32bit$16$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__is_32bit$66 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 20 \logical_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 47 \logical_op__is_signed$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__is_signed$17$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__is_signed$67 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 11 \logical_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__oe__oe$58 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 38 \logical_op__oe__oe$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__oe__oe$8$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 12 \logical_op__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__oe__ok$59 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 39 \logical_op__oe__ok$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__oe__ok$9$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 18 \logical_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 45 \logical_op__output_carry$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__output_carry$15$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__output_carry$65 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 10 \logical_op__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__rc__ok$57 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 37 \logical_op__rc__ok$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__rc__ok$7$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 9 \logical_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__rc__rc$56 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 36 \logical_op__rc__rc$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__rc__rc$6$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 17 \logical_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 44 \logical_op__write_cr0$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__write_cr0$14$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__write_cr0$64 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 14 \logical_op__zero_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 41 \logical_op__zero_a$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__zero_a$11$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__zero_a$61 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 input 4 \muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 output 31 \muxid$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \muxid$1$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \muxid$51 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:619" + wire \n_i_rdy_data + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" + wire input 30 \n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" + wire output 29 \n_valid_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 input 23 \o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 output 50 \o$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 \o$20$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 \o$70 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire input 24 \o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 51 \o_ok$21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \o_ok$21$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \o_ok$71 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 4 \output_cr_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 4 \output_cr_a$45 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \output_cr_a_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \output_logical_op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \output_logical_op__data_len$41 + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 \output_logical_op__fn_unit + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 \output_logical_op__fn_unit$26 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \output_logical_op__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \output_logical_op__imm_data__data$27 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_logical_op__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_logical_op__imm_data__ok$28 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \output_logical_op__input_carry + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \output_logical_op__input_carry$35 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \output_logical_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \output_logical_op__insn$42 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \output_logical_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \output_logical_op__insn_type$25 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_logical_op__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_logical_op__invert_in$33 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_logical_op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_logical_op__invert_out$36 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_logical_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_logical_op__is_32bit$39 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_logical_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_logical_op__is_signed$40 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_logical_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_logical_op__oe__oe$31 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_logical_op__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_logical_op__oe__ok$32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_logical_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_logical_op__output_carry$38 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_logical_op__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_logical_op__rc__ok$30 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_logical_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_logical_op__rc__rc$29 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_logical_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_logical_op__write_cr0$37 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_logical_op__zero_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_logical_op__zero_a$34 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \output_muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \output_muxid$24 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 \output_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 \output_o$43 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \output_o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \output_o_ok$44 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \output_xer_so + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" + wire output 3 \p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" + wire input 2 \p_valid_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:621" + wire \p_valid_i$48 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" + wire \p_valid_i_p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615" + wire \r_busy + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615" + wire \r_busy$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire input 27 \xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire input 28 \xer_so_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \xer_so_ok$47 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" + cell $and $and$issuer_ls180.v:130359$5970 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \p_valid_i$48 + connect \B \p_ready_o + connect \Y $and$issuer_ls180.v:130359$5970_Y + end + attribute \module_not_derived 1 + attribute \src "issuer_ls180.v:130408.10-130411.4" + cell \n$50 \n + connect \n_ready_i \n_ready_i + connect \n_valid_o \n_valid_o + end + attribute \module_not_derived 1 + attribute \src "issuer_ls180.v:130412.15-130459.4" + cell \output$51 \output + connect \cr_a \output_cr_a + connect \cr_a$22 \output_cr_a$45 + connect \cr_a_ok \output_cr_a_ok + connect \logical_op__data_len \output_logical_op__data_len + connect \logical_op__data_len$18 \output_logical_op__data_len$41 + connect \logical_op__fn_unit \output_logical_op__fn_unit + connect \logical_op__fn_unit$3 \output_logical_op__fn_unit$26 + connect \logical_op__imm_data__data \output_logical_op__imm_data__data + connect \logical_op__imm_data__data$4 \output_logical_op__imm_data__data$27 + connect \logical_op__imm_data__ok \output_logical_op__imm_data__ok + connect \logical_op__imm_data__ok$5 \output_logical_op__imm_data__ok$28 + connect \logical_op__input_carry \output_logical_op__input_carry + connect \logical_op__input_carry$12 \output_logical_op__input_carry$35 + connect \logical_op__insn \output_logical_op__insn + connect \logical_op__insn$19 \output_logical_op__insn$42 + connect \logical_op__insn_type \output_logical_op__insn_type + connect \logical_op__insn_type$2 \output_logical_op__insn_type$25 + connect \logical_op__invert_in \output_logical_op__invert_in + connect \logical_op__invert_in$10 \output_logical_op__invert_in$33 + connect \logical_op__invert_out \output_logical_op__invert_out + connect \logical_op__invert_out$13 \output_logical_op__invert_out$36 + connect \logical_op__is_32bit \output_logical_op__is_32bit + connect \logical_op__is_32bit$16 \output_logical_op__is_32bit$39 + connect \logical_op__is_signed \output_logical_op__is_signed + connect \logical_op__is_signed$17 \output_logical_op__is_signed$40 + connect \logical_op__oe__oe \output_logical_op__oe__oe + connect \logical_op__oe__oe$8 \output_logical_op__oe__oe$31 + connect \logical_op__oe__ok \output_logical_op__oe__ok + connect \logical_op__oe__ok$9 \output_logical_op__oe__ok$32 + connect \logical_op__output_carry \output_logical_op__output_carry + connect \logical_op__output_carry$15 \output_logical_op__output_carry$38 + connect \logical_op__rc__ok \output_logical_op__rc__ok + connect \logical_op__rc__ok$7 \output_logical_op__rc__ok$30 + connect \logical_op__rc__rc \output_logical_op__rc__rc + connect \logical_op__rc__rc$6 \output_logical_op__rc__rc$29 + connect \logical_op__write_cr0 \output_logical_op__write_cr0 + connect \logical_op__write_cr0$14 \output_logical_op__write_cr0$37 + connect \logical_op__zero_a \output_logical_op__zero_a + connect \logical_op__zero_a$11 \output_logical_op__zero_a$34 + connect \muxid \output_muxid + connect \muxid$1 \output_muxid$24 + connect \o \output_o + connect \o$20 \output_o$43 + connect \o_ok \output_o_ok + connect \o_ok$21 \output_o_ok$44 + connect \xer_so \output_xer_so + end + attribute \module_not_derived 1 + attribute \src "issuer_ls180.v:130460.10-130463.4" + cell \p$49 \p + connect \p_ready_o \p_ready_o + connect \p_valid_i \p_valid_i + end + attribute \src "issuer_ls180.v:129572.7-129572.20" + process $proc$issuer_ls180.v:129572$6080 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "issuer_ls180.v:129583.13-129583.29" + process $proc$issuer_ls180.v:129583$6081 + assign { } { } + assign $0\cr_a$22[3:0]$6082 4'0000 + sync always + sync init + update \cr_a$22 $0\cr_a$22[3:0]$6082 + end + attribute \src "issuer_ls180.v:129592.7-129592.26" + process $proc$issuer_ls180.v:129592$6083 + assign { } { } + assign $0\cr_a_ok$23[0:0]$6084 1'0 + sync always + sync init + update \cr_a_ok$23 $0\cr_a_ok$23[0:0]$6084 + end + attribute \src "issuer_ls180.v:129603.13-129603.45" + process $proc$issuer_ls180.v:129603$6085 + assign { } { } + assign $0\logical_op__data_len$18[3:0]$6086 4'0000 + sync always + sync init + update \logical_op__data_len$18 $0\logical_op__data_len$18[3:0]$6086 + end + attribute \src "issuer_ls180.v:129638.14-129638.47" + process $proc$issuer_ls180.v:129638$6087 + assign { } { } + assign $0\logical_op__fn_unit$3[11:0]$6088 12'000000000000 + sync always + sync init + update \logical_op__fn_unit$3 $0\logical_op__fn_unit$3[11:0]$6088 + end + attribute \src "issuer_ls180.v:129660.14-129660.67" + process $proc$issuer_ls180.v:129660$6089 + assign { } { } + assign $0\logical_op__imm_data__data$4[63:0]$6090 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \logical_op__imm_data__data$4 $0\logical_op__imm_data__data$4[63:0]$6090 + end + attribute \src "issuer_ls180.v:129669.7-129669.42" + process $proc$issuer_ls180.v:129669$6091 + assign { } { } + assign $0\logical_op__imm_data__ok$5[0:0]$6092 1'0 + sync always + sync init + update \logical_op__imm_data__ok$5 $0\logical_op__imm_data__ok$5[0:0]$6092 + end + attribute \src "issuer_ls180.v:129686.13-129686.48" + process $proc$issuer_ls180.v:129686$6093 + assign { } { } + assign $0\logical_op__input_carry$12[1:0]$6094 2'00 + sync always + sync init + update \logical_op__input_carry$12 $0\logical_op__input_carry$12[1:0]$6094 + end + attribute \src "issuer_ls180.v:129699.14-129699.43" + process $proc$issuer_ls180.v:129699$6095 + assign { } { } + assign $0\logical_op__insn$19[31:0]$6096 0 + sync always + sync init + update \logical_op__insn$19 $0\logical_op__insn$19[31:0]$6096 + end + attribute \src "issuer_ls180.v:129856.13-129856.46" + process $proc$issuer_ls180.v:129856$6097 + assign { } { } + assign $0\logical_op__insn_type$2[6:0]$6098 7'0000000 + sync always + sync init + update \logical_op__insn_type$2 $0\logical_op__insn_type$2[6:0]$6098 + end + attribute \src "issuer_ls180.v:129939.7-129939.40" + process $proc$issuer_ls180.v:129939$6099 + assign { } { } + assign $0\logical_op__invert_in$10[0:0]$6100 1'0 + sync always + sync init + update \logical_op__invert_in$10 $0\logical_op__invert_in$10[0:0]$6100 + end + attribute \src "issuer_ls180.v:129948.7-129948.41" + process $proc$issuer_ls180.v:129948$6101 + assign { } { } + assign $0\logical_op__invert_out$13[0:0]$6102 1'0 + sync always + sync init + update \logical_op__invert_out$13 $0\logical_op__invert_out$13[0:0]$6102 + end + attribute \src "issuer_ls180.v:129957.7-129957.39" + process $proc$issuer_ls180.v:129957$6103 + assign { } { } + assign $0\logical_op__is_32bit$16[0:0]$6104 1'0 + sync always + sync init + update \logical_op__is_32bit$16 $0\logical_op__is_32bit$16[0:0]$6104 + end + attribute \src "issuer_ls180.v:129966.7-129966.40" + process $proc$issuer_ls180.v:129966$6105 + assign { } { } + assign $0\logical_op__is_signed$17[0:0]$6106 1'0 + sync always + sync init + update \logical_op__is_signed$17 $0\logical_op__is_signed$17[0:0]$6106 + end + attribute \src "issuer_ls180.v:129977.7-129977.36" + process $proc$issuer_ls180.v:129977$6107 + assign { } { } + assign $0\logical_op__oe__oe$8[0:0]$6108 1'0 + sync always + sync init + update \logical_op__oe__oe$8 $0\logical_op__oe__oe$8[0:0]$6108 + end + attribute \src "issuer_ls180.v:129986.7-129986.36" + process $proc$issuer_ls180.v:129986$6109 + assign { } { } + assign $0\logical_op__oe__ok$9[0:0]$6110 1'0 + sync always + sync init + update \logical_op__oe__ok$9 $0\logical_op__oe__ok$9[0:0]$6110 + end + attribute \src "issuer_ls180.v:129993.7-129993.43" + process $proc$issuer_ls180.v:129993$6111 + assign { } { } + assign $0\logical_op__output_carry$15[0:0]$6112 1'0 + sync always + sync init + update \logical_op__output_carry$15 $0\logical_op__output_carry$15[0:0]$6112 + end + attribute \src "issuer_ls180.v:130004.7-130004.36" + process $proc$issuer_ls180.v:130004$6113 + assign { } { } + assign $0\logical_op__rc__ok$7[0:0]$6114 1'0 + sync always + sync init + update \logical_op__rc__ok$7 $0\logical_op__rc__ok$7[0:0]$6114 + end + attribute \src "issuer_ls180.v:130013.7-130013.36" + process $proc$issuer_ls180.v:130013$6115 + assign { } { } + assign $0\logical_op__rc__rc$6[0:0]$6116 1'0 + sync always + sync init + update \logical_op__rc__rc$6 $0\logical_op__rc__rc$6[0:0]$6116 + end + attribute \src "issuer_ls180.v:130020.7-130020.40" + process $proc$issuer_ls180.v:130020$6117 + assign { } { } + assign $0\logical_op__write_cr0$14[0:0]$6118 1'0 + sync always + sync init + update \logical_op__write_cr0$14 $0\logical_op__write_cr0$14[0:0]$6118 + end + attribute \src "issuer_ls180.v:130029.7-130029.37" + process $proc$issuer_ls180.v:130029$6119 + assign { } { } + assign $0\logical_op__zero_a$11[0:0]$6120 1'0 + sync always + sync init + update \logical_op__zero_a$11 $0\logical_op__zero_a$11[0:0]$6120 + end + attribute \src "issuer_ls180.v:130038.13-130038.29" + process $proc$issuer_ls180.v:130038$6121 + assign { } { } + assign $0\muxid$1[1:0]$6122 2'00 + sync always + sync init + update \muxid$1 $0\muxid$1[1:0]$6122 + end + attribute \src "issuer_ls180.v:130053.14-130053.43" + process $proc$issuer_ls180.v:130053$6123 + assign { } { } + assign $0\o$20[63:0]$6124 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \o$20 $0\o$20[63:0]$6124 + end + attribute \src "issuer_ls180.v:130062.7-130062.23" + process $proc$issuer_ls180.v:130062$6125 + assign { } { } + assign $0\o_ok$21[0:0]$6126 1'0 + sync always + sync init + update \o_ok$21 $0\o_ok$21[0:0]$6126 + end + attribute \src "issuer_ls180.v:130350.7-130350.20" + process $proc$issuer_ls180.v:130350$6127 + assign { } { } + assign $1\r_busy[0:0] 1'0 + sync always + sync init + update \r_busy $1\r_busy[0:0] + end + attribute \src "issuer_ls180.v:130360.3-130361.33" + process $proc$issuer_ls180.v:130360$5971 + assign { } { } + assign $0\cr_a$22[3:0]$5972 \cr_a$22$next + sync posedge \coresync_clk + update \cr_a$22 $0\cr_a$22[3:0]$5972 + end + attribute \src "issuer_ls180.v:130362.3-130363.39" + process $proc$issuer_ls180.v:130362$5973 + assign { } { } + assign $0\cr_a_ok$23[0:0]$5974 \cr_a_ok$23$next + sync posedge \coresync_clk + update \cr_a_ok$23 $0\cr_a_ok$23[0:0]$5974 + end + attribute \src "issuer_ls180.v:130364.3-130365.27" + process $proc$issuer_ls180.v:130364$5975 + assign { } { } + assign $0\o$20[63:0]$5976 \o$20$next + sync posedge \coresync_clk + update \o$20 $0\o$20[63:0]$5976 + end + attribute \src "issuer_ls180.v:130366.3-130367.33" + process $proc$issuer_ls180.v:130366$5977 + assign { } { } + assign $0\o_ok$21[0:0]$5978 \o_ok$21$next + sync posedge \coresync_clk + update \o_ok$21 $0\o_ok$21[0:0]$5978 + end + attribute \src "issuer_ls180.v:130368.3-130369.65" + process $proc$issuer_ls180.v:130368$5979 + assign { } { } + assign $0\logical_op__insn_type$2[6:0]$5980 \logical_op__insn_type$2$next + sync posedge \coresync_clk + update \logical_op__insn_type$2 $0\logical_op__insn_type$2[6:0]$5980 + end + attribute \src "issuer_ls180.v:130370.3-130371.61" + process $proc$issuer_ls180.v:130370$5981 + assign { } { } + assign $0\logical_op__fn_unit$3[11:0]$5982 \logical_op__fn_unit$3$next + sync posedge \coresync_clk + update \logical_op__fn_unit$3 $0\logical_op__fn_unit$3[11:0]$5982 + end + attribute \src "issuer_ls180.v:130372.3-130373.75" + process $proc$issuer_ls180.v:130372$5983 + assign { } { } + assign $0\logical_op__imm_data__data$4[63:0]$5984 \logical_op__imm_data__data$4$next + sync posedge \coresync_clk + update \logical_op__imm_data__data$4 $0\logical_op__imm_data__data$4[63:0]$5984 + end + attribute \src "issuer_ls180.v:130374.3-130375.71" + process $proc$issuer_ls180.v:130374$5985 + assign { } { } + assign $0\logical_op__imm_data__ok$5[0:0]$5986 \logical_op__imm_data__ok$5$next + sync posedge \coresync_clk + update \logical_op__imm_data__ok$5 $0\logical_op__imm_data__ok$5[0:0]$5986 + end + attribute \src "issuer_ls180.v:130376.3-130377.59" + process $proc$issuer_ls180.v:130376$5987 + assign { } { } + assign $0\logical_op__rc__rc$6[0:0]$5988 \logical_op__rc__rc$6$next + sync posedge \coresync_clk + update \logical_op__rc__rc$6 $0\logical_op__rc__rc$6[0:0]$5988 + end + attribute \src "issuer_ls180.v:130378.3-130379.59" + process $proc$issuer_ls180.v:130378$5989 + assign { } { } + assign $0\logical_op__rc__ok$7[0:0]$5990 \logical_op__rc__ok$7$next + sync posedge \coresync_clk + update \logical_op__rc__ok$7 $0\logical_op__rc__ok$7[0:0]$5990 + end + attribute \src "issuer_ls180.v:130380.3-130381.59" + process $proc$issuer_ls180.v:130380$5991 + assign { } { } + assign $0\logical_op__oe__oe$8[0:0]$5992 \logical_op__oe__oe$8$next + sync posedge \coresync_clk + update \logical_op__oe__oe$8 $0\logical_op__oe__oe$8[0:0]$5992 + end + attribute \src "issuer_ls180.v:130382.3-130383.59" + process $proc$issuer_ls180.v:130382$5993 + assign { } { } + assign $0\logical_op__oe__ok$9[0:0]$5994 \logical_op__oe__ok$9$next + sync posedge \coresync_clk + update \logical_op__oe__ok$9 $0\logical_op__oe__ok$9[0:0]$5994 + end + attribute \src "issuer_ls180.v:130384.3-130385.67" + process $proc$issuer_ls180.v:130384$5995 + assign { } { } + assign $0\logical_op__invert_in$10[0:0]$5996 \logical_op__invert_in$10$next + sync posedge \coresync_clk + update \logical_op__invert_in$10 $0\logical_op__invert_in$10[0:0]$5996 + end + attribute \src "issuer_ls180.v:130386.3-130387.61" + process $proc$issuer_ls180.v:130386$5997 + assign { } { } + assign $0\logical_op__zero_a$11[0:0]$5998 \logical_op__zero_a$11$next + sync posedge \coresync_clk + update \logical_op__zero_a$11 $0\logical_op__zero_a$11[0:0]$5998 + end + attribute \src "issuer_ls180.v:130388.3-130389.71" + process $proc$issuer_ls180.v:130388$5999 + assign { } { } + assign $0\logical_op__input_carry$12[1:0]$6000 \logical_op__input_carry$12$next + sync posedge \coresync_clk + update \logical_op__input_carry$12 $0\logical_op__input_carry$12[1:0]$6000 + end + attribute \src "issuer_ls180.v:130390.3-130391.69" + process $proc$issuer_ls180.v:130390$6001 + assign { } { } + assign $0\logical_op__invert_out$13[0:0]$6002 \logical_op__invert_out$13$next + sync posedge \coresync_clk + update \logical_op__invert_out$13 $0\logical_op__invert_out$13[0:0]$6002 + end + attribute \src "issuer_ls180.v:130392.3-130393.67" + process $proc$issuer_ls180.v:130392$6003 + assign { } { } + assign $0\logical_op__write_cr0$14[0:0]$6004 \logical_op__write_cr0$14$next + sync posedge \coresync_clk + update \logical_op__write_cr0$14 $0\logical_op__write_cr0$14[0:0]$6004 + end + attribute \src "issuer_ls180.v:130394.3-130395.73" + process $proc$issuer_ls180.v:130394$6005 + assign { } { } + assign $0\logical_op__output_carry$15[0:0]$6006 \logical_op__output_carry$15$next + sync posedge \coresync_clk + update \logical_op__output_carry$15 $0\logical_op__output_carry$15[0:0]$6006 + end + attribute \src "issuer_ls180.v:130396.3-130397.65" + process $proc$issuer_ls180.v:130396$6007 + assign { } { } + assign $0\logical_op__is_32bit$16[0:0]$6008 \logical_op__is_32bit$16$next + sync posedge \coresync_clk + update \logical_op__is_32bit$16 $0\logical_op__is_32bit$16[0:0]$6008 + end + attribute \src "issuer_ls180.v:130398.3-130399.67" + process $proc$issuer_ls180.v:130398$6009 + assign { } { } + assign $0\logical_op__is_signed$17[0:0]$6010 \logical_op__is_signed$17$next + sync posedge \coresync_clk + update \logical_op__is_signed$17 $0\logical_op__is_signed$17[0:0]$6010 + end + attribute \src "issuer_ls180.v:130400.3-130401.65" + process $proc$issuer_ls180.v:130400$6011 + assign { } { } + assign $0\logical_op__data_len$18[3:0]$6012 \logical_op__data_len$18$next + sync posedge \coresync_clk + update \logical_op__data_len$18 $0\logical_op__data_len$18[3:0]$6012 + end + attribute \src "issuer_ls180.v:130402.3-130403.57" + process $proc$issuer_ls180.v:130402$6013 + assign { } { } + assign $0\logical_op__insn$19[31:0]$6014 \logical_op__insn$19$next + sync posedge \coresync_clk + update \logical_op__insn$19 $0\logical_op__insn$19[31:0]$6014 + end + attribute \src "issuer_ls180.v:130404.3-130405.33" + process $proc$issuer_ls180.v:130404$6015 + assign { } { } + assign $0\muxid$1[1:0]$6016 \muxid$1$next + sync posedge \coresync_clk + update \muxid$1 $0\muxid$1[1:0]$6016 + end + attribute \src "issuer_ls180.v:130406.3-130407.29" + process $proc$issuer_ls180.v:130406$6017 + assign { } { } + assign $0\r_busy[0:0] \r_busy$next + sync posedge \coresync_clk + update \r_busy $0\r_busy[0:0] + end + attribute \src "issuer_ls180.v:130464.3-130481.6" + process $proc$issuer_ls180.v:130464$6018 + assign { } { } + assign { } { } + assign { } { } + assign $0\r_busy$next[0:0]$6019 $2\r_busy$next[0:0]$6021 + attribute \src "issuer_ls180.v:130465.5-130465.29" + switch \initial + attribute \src "issuer_ls180.v:130465.9-130465.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\r_busy$next[0:0]$6020 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\r_busy$next[0:0]$6020 1'0 + case + assign $1\r_busy$next[0:0]$6020 \r_busy + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\r_busy$next[0:0]$6021 1'0 + case + assign $2\r_busy$next[0:0]$6021 $1\r_busy$next[0:0]$6020 + end + sync always + update \r_busy$next $0\r_busy$next[0:0]$6019 + end + attribute \src "issuer_ls180.v:130482.3-130494.6" + process $proc$issuer_ls180.v:130482$6022 + assign { } { } + assign { } { } + assign $0\muxid$1$next[1:0]$6023 $1\muxid$1$next[1:0]$6024 + attribute \src "issuer_ls180.v:130483.5-130483.29" + switch \initial + attribute \src "issuer_ls180.v:130483.9-130483.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\muxid$1$next[1:0]$6024 \muxid$51 + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\muxid$1$next[1:0]$6024 \muxid$51 + case + assign $1\muxid$1$next[1:0]$6024 \muxid$1 + end + sync always + update \muxid$1$next $0\muxid$1$next[1:0]$6023 + end + attribute \src "issuer_ls180.v:130495.3-130536.6" + process $proc$issuer_ls180.v:130495$6025 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\logical_op__data_len$18$next[3:0]$6026 $1\logical_op__data_len$18$next[3:0]$6044 + assign $0\logical_op__fn_unit$3$next[11:0]$6027 $1\logical_op__fn_unit$3$next[11:0]$6045 + assign { } { } + assign { } { } + assign $0\logical_op__input_carry$12$next[1:0]$6030 $1\logical_op__input_carry$12$next[1:0]$6048 + assign $0\logical_op__insn$19$next[31:0]$6031 $1\logical_op__insn$19$next[31:0]$6049 + assign $0\logical_op__insn_type$2$next[6:0]$6032 $1\logical_op__insn_type$2$next[6:0]$6050 + assign $0\logical_op__invert_in$10$next[0:0]$6033 $1\logical_op__invert_in$10$next[0:0]$6051 + assign $0\logical_op__invert_out$13$next[0:0]$6034 $1\logical_op__invert_out$13$next[0:0]$6052 + assign $0\logical_op__is_32bit$16$next[0:0]$6035 $1\logical_op__is_32bit$16$next[0:0]$6053 + assign $0\logical_op__is_signed$17$next[0:0]$6036 $1\logical_op__is_signed$17$next[0:0]$6054 + assign { } { } + assign { } { } + assign $0\logical_op__output_carry$15$next[0:0]$6039 $1\logical_op__output_carry$15$next[0:0]$6057 + assign { } { } + assign { } { } + assign $0\logical_op__write_cr0$14$next[0:0]$6042 $1\logical_op__write_cr0$14$next[0:0]$6060 + assign $0\logical_op__zero_a$11$next[0:0]$6043 $1\logical_op__zero_a$11$next[0:0]$6061 + assign $0\logical_op__imm_data__data$4$next[63:0]$6028 $2\logical_op__imm_data__data$4$next[63:0]$6062 + assign $0\logical_op__imm_data__ok$5$next[0:0]$6029 $2\logical_op__imm_data__ok$5$next[0:0]$6063 + assign $0\logical_op__oe__oe$8$next[0:0]$6037 $2\logical_op__oe__oe$8$next[0:0]$6064 + assign $0\logical_op__oe__ok$9$next[0:0]$6038 $2\logical_op__oe__ok$9$next[0:0]$6065 + assign $0\logical_op__rc__ok$7$next[0:0]$6040 $2\logical_op__rc__ok$7$next[0:0]$6066 + assign $0\logical_op__rc__rc$6$next[0:0]$6041 $2\logical_op__rc__rc$6$next[0:0]$6067 + attribute \src "issuer_ls180.v:130496.5-130496.29" + switch \initial + attribute \src "issuer_ls180.v:130496.9-130496.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'-1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { $1\logical_op__insn$19$next[31:0]$6049 $1\logical_op__data_len$18$next[3:0]$6044 $1\logical_op__is_signed$17$next[0:0]$6054 $1\logical_op__is_32bit$16$next[0:0]$6053 $1\logical_op__output_carry$15$next[0:0]$6057 $1\logical_op__write_cr0$14$next[0:0]$6060 $1\logical_op__invert_out$13$next[0:0]$6052 $1\logical_op__input_carry$12$next[1:0]$6048 $1\logical_op__zero_a$11$next[0:0]$6061 $1\logical_op__invert_in$10$next[0:0]$6051 $1\logical_op__oe__ok$9$next[0:0]$6056 $1\logical_op__oe__oe$8$next[0:0]$6055 $1\logical_op__rc__ok$7$next[0:0]$6058 $1\logical_op__rc__rc$6$next[0:0]$6059 $1\logical_op__imm_data__ok$5$next[0:0]$6047 $1\logical_op__imm_data__data$4$next[63:0]$6046 $1\logical_op__fn_unit$3$next[11:0]$6045 $1\logical_op__insn_type$2$next[6:0]$6050 } { \logical_op__insn$69 \logical_op__data_len$68 \logical_op__is_signed$67 \logical_op__is_32bit$66 \logical_op__output_carry$65 \logical_op__write_cr0$64 \logical_op__invert_out$63 \logical_op__input_carry$62 \logical_op__zero_a$61 \logical_op__invert_in$60 \logical_op__oe__ok$59 \logical_op__oe__oe$58 \logical_op__rc__ok$57 \logical_op__rc__rc$56 \logical_op__imm_data__ok$55 \logical_op__imm_data__data$54 \logical_op__fn_unit$53 \logical_op__insn_type$52 } + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'1- + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { $1\logical_op__insn$19$next[31:0]$6049 $1\logical_op__data_len$18$next[3:0]$6044 $1\logical_op__is_signed$17$next[0:0]$6054 $1\logical_op__is_32bit$16$next[0:0]$6053 $1\logical_op__output_carry$15$next[0:0]$6057 $1\logical_op__write_cr0$14$next[0:0]$6060 $1\logical_op__invert_out$13$next[0:0]$6052 $1\logical_op__input_carry$12$next[1:0]$6048 $1\logical_op__zero_a$11$next[0:0]$6061 $1\logical_op__invert_in$10$next[0:0]$6051 $1\logical_op__oe__ok$9$next[0:0]$6056 $1\logical_op__oe__oe$8$next[0:0]$6055 $1\logical_op__rc__ok$7$next[0:0]$6058 $1\logical_op__rc__rc$6$next[0:0]$6059 $1\logical_op__imm_data__ok$5$next[0:0]$6047 $1\logical_op__imm_data__data$4$next[63:0]$6046 $1\logical_op__fn_unit$3$next[11:0]$6045 $1\logical_op__insn_type$2$next[6:0]$6050 } { \logical_op__insn$69 \logical_op__data_len$68 \logical_op__is_signed$67 \logical_op__is_32bit$66 \logical_op__output_carry$65 \logical_op__write_cr0$64 \logical_op__invert_out$63 \logical_op__input_carry$62 \logical_op__zero_a$61 \logical_op__invert_in$60 \logical_op__oe__ok$59 \logical_op__oe__oe$58 \logical_op__rc__ok$57 \logical_op__rc__rc$56 \logical_op__imm_data__ok$55 \logical_op__imm_data__data$54 \logical_op__fn_unit$53 \logical_op__insn_type$52 } + case + assign $1\logical_op__data_len$18$next[3:0]$6044 \logical_op__data_len$18 + assign $1\logical_op__fn_unit$3$next[11:0]$6045 \logical_op__fn_unit$3 + assign $1\logical_op__imm_data__data$4$next[63:0]$6046 \logical_op__imm_data__data$4 + assign $1\logical_op__imm_data__ok$5$next[0:0]$6047 \logical_op__imm_data__ok$5 + assign $1\logical_op__input_carry$12$next[1:0]$6048 \logical_op__input_carry$12 + assign $1\logical_op__insn$19$next[31:0]$6049 \logical_op__insn$19 + assign $1\logical_op__insn_type$2$next[6:0]$6050 \logical_op__insn_type$2 + assign $1\logical_op__invert_in$10$next[0:0]$6051 \logical_op__invert_in$10 + assign $1\logical_op__invert_out$13$next[0:0]$6052 \logical_op__invert_out$13 + assign $1\logical_op__is_32bit$16$next[0:0]$6053 \logical_op__is_32bit$16 + assign $1\logical_op__is_signed$17$next[0:0]$6054 \logical_op__is_signed$17 + assign $1\logical_op__oe__oe$8$next[0:0]$6055 \logical_op__oe__oe$8 + assign $1\logical_op__oe__ok$9$next[0:0]$6056 \logical_op__oe__ok$9 + assign $1\logical_op__output_carry$15$next[0:0]$6057 \logical_op__output_carry$15 + assign $1\logical_op__rc__ok$7$next[0:0]$6058 \logical_op__rc__ok$7 + assign $1\logical_op__rc__rc$6$next[0:0]$6059 \logical_op__rc__rc$6 + assign $1\logical_op__write_cr0$14$next[0:0]$6060 \logical_op__write_cr0$14 + assign $1\logical_op__zero_a$11$next[0:0]$6061 \logical_op__zero_a$11 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $2\logical_op__imm_data__data$4$next[63:0]$6062 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\logical_op__imm_data__ok$5$next[0:0]$6063 1'0 + assign $2\logical_op__rc__rc$6$next[0:0]$6067 1'0 + assign $2\logical_op__rc__ok$7$next[0:0]$6066 1'0 + assign $2\logical_op__oe__oe$8$next[0:0]$6064 1'0 + assign $2\logical_op__oe__ok$9$next[0:0]$6065 1'0 + case + assign $2\logical_op__imm_data__data$4$next[63:0]$6062 $1\logical_op__imm_data__data$4$next[63:0]$6046 + assign $2\logical_op__imm_data__ok$5$next[0:0]$6063 $1\logical_op__imm_data__ok$5$next[0:0]$6047 + assign $2\logical_op__oe__oe$8$next[0:0]$6064 $1\logical_op__oe__oe$8$next[0:0]$6055 + assign $2\logical_op__oe__ok$9$next[0:0]$6065 $1\logical_op__oe__ok$9$next[0:0]$6056 + assign $2\logical_op__rc__ok$7$next[0:0]$6066 $1\logical_op__rc__ok$7$next[0:0]$6058 + assign $2\logical_op__rc__rc$6$next[0:0]$6067 $1\logical_op__rc__rc$6$next[0:0]$6059 + end + sync always + update \logical_op__data_len$18$next $0\logical_op__data_len$18$next[3:0]$6026 + update \logical_op__fn_unit$3$next $0\logical_op__fn_unit$3$next[11:0]$6027 + update \logical_op__imm_data__data$4$next $0\logical_op__imm_data__data$4$next[63:0]$6028 + update \logical_op__imm_data__ok$5$next $0\logical_op__imm_data__ok$5$next[0:0]$6029 + update \logical_op__input_carry$12$next $0\logical_op__input_carry$12$next[1:0]$6030 + update \logical_op__insn$19$next $0\logical_op__insn$19$next[31:0]$6031 + update \logical_op__insn_type$2$next $0\logical_op__insn_type$2$next[6:0]$6032 + update \logical_op__invert_in$10$next $0\logical_op__invert_in$10$next[0:0]$6033 + update \logical_op__invert_out$13$next $0\logical_op__invert_out$13$next[0:0]$6034 + update \logical_op__is_32bit$16$next $0\logical_op__is_32bit$16$next[0:0]$6035 + update \logical_op__is_signed$17$next $0\logical_op__is_signed$17$next[0:0]$6036 + update \logical_op__oe__oe$8$next $0\logical_op__oe__oe$8$next[0:0]$6037 + update \logical_op__oe__ok$9$next $0\logical_op__oe__ok$9$next[0:0]$6038 + update \logical_op__output_carry$15$next $0\logical_op__output_carry$15$next[0:0]$6039 + update \logical_op__rc__ok$7$next $0\logical_op__rc__ok$7$next[0:0]$6040 + update \logical_op__rc__rc$6$next $0\logical_op__rc__rc$6$next[0:0]$6041 + update \logical_op__write_cr0$14$next $0\logical_op__write_cr0$14$next[0:0]$6042 + update \logical_op__zero_a$11$next $0\logical_op__zero_a$11$next[0:0]$6043 + end + attribute \src "issuer_ls180.v:130537.3-130555.6" + process $proc$issuer_ls180.v:130537$6068 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\o$20$next[63:0]$6069 $1\o$20$next[63:0]$6071 + assign { } { } + assign $0\o_ok$21$next[0:0]$6070 $2\o_ok$21$next[0:0]$6073 + attribute \src "issuer_ls180.v:130538.5-130538.29" + switch \initial + attribute \src "issuer_ls180.v:130538.9-130538.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'-1 + assign { } { } + assign { } { } + assign { $1\o_ok$21$next[0:0]$6072 $1\o$20$next[63:0]$6071 } { \o_ok$71 \o$70 } + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'1- + assign { } { } + assign { } { } + assign { $1\o_ok$21$next[0:0]$6072 $1\o$20$next[63:0]$6071 } { \o_ok$71 \o$70 } + case + assign $1\o$20$next[63:0]$6071 \o$20 + assign $1\o_ok$21$next[0:0]$6072 \o_ok$21 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\o_ok$21$next[0:0]$6073 1'0 + case + assign $2\o_ok$21$next[0:0]$6073 $1\o_ok$21$next[0:0]$6072 + end + sync always + update \o$20$next $0\o$20$next[63:0]$6069 + update \o_ok$21$next $0\o_ok$21$next[0:0]$6070 + end + attribute \src "issuer_ls180.v:130556.3-130574.6" + process $proc$issuer_ls180.v:130556$6074 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\cr_a$22$next[3:0]$6075 $1\cr_a$22$next[3:0]$6077 + assign { } { } + assign $0\cr_a_ok$23$next[0:0]$6076 $2\cr_a_ok$23$next[0:0]$6079 + attribute \src "issuer_ls180.v:130557.5-130557.29" + switch \initial + attribute \src "issuer_ls180.v:130557.9-130557.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'-1 + assign { } { } + assign { } { } + assign { $1\cr_a_ok$23$next[0:0]$6078 $1\cr_a$22$next[3:0]$6077 } { \cr_a_ok$73 \cr_a$72 } + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'1- + assign { } { } + assign { } { } + assign { $1\cr_a_ok$23$next[0:0]$6078 $1\cr_a$22$next[3:0]$6077 } { \cr_a_ok$73 \cr_a$72 } + case + assign $1\cr_a$22$next[3:0]$6077 \cr_a$22 + assign $1\cr_a_ok$23$next[0:0]$6078 \cr_a_ok$23 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\cr_a_ok$23$next[0:0]$6079 1'0 + case + assign $2\cr_a_ok$23$next[0:0]$6079 $1\cr_a_ok$23$next[0:0]$6078 + end + sync always + update \cr_a$22$next $0\cr_a$22$next[3:0]$6075 + update \cr_a_ok$23$next $0\cr_a_ok$23$next[0:0]$6076 + end + connect \$49 $and$issuer_ls180.v:130359$5970_Y + connect \p_ready_o \n_i_rdy_data + connect \n_valid_o \r_busy + connect { \cr_a_ok$73 \cr_a$72 } { \output_cr_a_ok \output_cr_a$45 } + connect { \o_ok$71 \o$70 } { \output_o_ok$44 \output_o$43 } + connect { \logical_op__insn$69 \logical_op__data_len$68 \logical_op__is_signed$67 \logical_op__is_32bit$66 \logical_op__output_carry$65 \logical_op__write_cr0$64 \logical_op__invert_out$63 \logical_op__input_carry$62 \logical_op__zero_a$61 \logical_op__invert_in$60 \logical_op__oe__ok$59 \logical_op__oe__oe$58 \logical_op__rc__ok$57 \logical_op__rc__rc$56 \logical_op__imm_data__ok$55 \logical_op__imm_data__data$54 \logical_op__fn_unit$53 \logical_op__insn_type$52 } { \output_logical_op__insn$42 \output_logical_op__data_len$41 \output_logical_op__is_signed$40 \output_logical_op__is_32bit$39 \output_logical_op__output_carry$38 \output_logical_op__write_cr0$37 \output_logical_op__invert_out$36 \output_logical_op__input_carry$35 \output_logical_op__zero_a$34 \output_logical_op__invert_in$33 \output_logical_op__oe__ok$32 \output_logical_op__oe__oe$31 \output_logical_op__rc__ok$30 \output_logical_op__rc__rc$29 \output_logical_op__imm_data__ok$28 \output_logical_op__imm_data__data$27 \output_logical_op__fn_unit$26 \output_logical_op__insn_type$25 } + connect \muxid$51 \output_muxid$24 + connect \p_valid_i_p_ready_o \$49 + connect \n_i_rdy_data \n_ready_i + connect \p_valid_i$48 \p_valid_i + connect { \xer_so_ok$47 \output_xer_so } { \xer_so_ok \xer_so } + connect { \cr_a_ok$46 \output_cr_a } { \cr_a_ok \cr_a } + connect { \output_o_ok \output_o } { \o_ok \o } + connect { \output_logical_op__insn \output_logical_op__data_len \output_logical_op__is_signed \output_logical_op__is_32bit \output_logical_op__output_carry \output_logical_op__write_cr0 \output_logical_op__invert_out \output_logical_op__input_carry \output_logical_op__zero_a \output_logical_op__invert_in \output_logical_op__oe__ok \output_logical_op__oe__oe \output_logical_op__rc__ok \output_logical_op__rc__rc \output_logical_op__imm_data__ok \output_logical_op__imm_data__data \output_logical_op__fn_unit \output_logical_op__insn_type } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in \logical_op__oe__ok \logical_op__oe__oe \logical_op__rc__ok \logical_op__rc__rc \logical_op__imm_data__ok \logical_op__imm_data__data \logical_op__fn_unit \logical_op__insn_type } + connect \output_muxid \muxid +end +attribute \src "build/ls180/gateware/ls180.v:4.1-9627.10" +attribute \cells_not_processed 1 +attribute \top 1 +module \ls180 + attribute \src "build/ls180/gateware/ls180.v:9367.1-9377.4" + wire width 16 $0$memwr$\mem$build/ls180/gateware/ls180.v:9369$1_ADDR[15:0]$2460 + attribute \src "build/ls180/gateware/ls180.v:9367.1-9377.4" + wire width 32 $0$memwr$\mem$build/ls180/gateware/ls180.v:9369$1_DATA[31:0]$2461 + attribute \src "build/ls180/gateware/ls180.v:9367.1-9377.4" + wire width 32 $0$memwr$\mem$build/ls180/gateware/ls180.v:9369$1_EN[31:0]$2462 + attribute \src "build/ls180/gateware/ls180.v:9367.1-9377.4" + wire width 16 $0$memwr$\mem$build/ls180/gateware/ls180.v:9371$2_ADDR[15:0]$2463 + attribute \src "build/ls180/gateware/ls180.v:9367.1-9377.4" + wire width 32 $0$memwr$\mem$build/ls180/gateware/ls180.v:9371$2_DATA[31:0]$2464 + attribute \src "build/ls180/gateware/ls180.v:9367.1-9377.4" + wire width 32 $0$memwr$\mem$build/ls180/gateware/ls180.v:9371$2_EN[31:0]$2465 + attribute \src "build/ls180/gateware/ls180.v:9367.1-9377.4" + wire width 16 $0$memwr$\mem$build/ls180/gateware/ls180.v:9373$3_ADDR[15:0]$2466 + attribute \src "build/ls180/gateware/ls180.v:9367.1-9377.4" + wire width 32 $0$memwr$\mem$build/ls180/gateware/ls180.v:9373$3_DATA[31:0]$2467 + attribute \src "build/ls180/gateware/ls180.v:9367.1-9377.4" + wire width 32 $0$memwr$\mem$build/ls180/gateware/ls180.v:9373$3_EN[31:0]$2468 + attribute \src "build/ls180/gateware/ls180.v:9367.1-9377.4" + wire width 16 $0$memwr$\mem$build/ls180/gateware/ls180.v:9375$4_ADDR[15:0]$2469 + attribute \src "build/ls180/gateware/ls180.v:9367.1-9377.4" + wire width 32 $0$memwr$\mem$build/ls180/gateware/ls180.v:9375$4_DATA[31:0]$2470 + attribute \src "build/ls180/gateware/ls180.v:9367.1-9377.4" + wire width 32 $0$memwr$\mem$build/ls180/gateware/ls180.v:9375$4_EN[31:0]$2471 + attribute \src "build/ls180/gateware/ls180.v:9388.1-9392.4" + wire width 4 $0$memwr$\storage$build/ls180/gateware/ls180.v:9390$5_ADDR[3:0]$2474 + attribute \src "build/ls180/gateware/ls180.v:9388.1-9392.4" + wire width 10 $0$memwr$\storage$build/ls180/gateware/ls180.v:9390$5_DATA[9:0]$2475 + attribute \src "build/ls180/gateware/ls180.v:9388.1-9392.4" + wire width 10 $0$memwr$\storage$build/ls180/gateware/ls180.v:9390$5_EN[9:0]$2476 + attribute \src "build/ls180/gateware/ls180.v:9405.1-9409.4" + wire width 4 $0$memwr$\storage_1$build/ls180/gateware/ls180.v:9407$6_ADDR[3:0]$2481 + attribute \src "build/ls180/gateware/ls180.v:9405.1-9409.4" + wire width 10 $0$memwr$\storage_1$build/ls180/gateware/ls180.v:9407$6_DATA[9:0]$2482 + attribute \src "build/ls180/gateware/ls180.v:9405.1-9409.4" + wire width 10 $0$memwr$\storage_1$build/ls180/gateware/ls180.v:9407$6_EN[9:0]$2483 + attribute \src "build/ls180/gateware/ls180.v:9421.1-9425.4" + wire width 3 $0$memwr$\storage_2$build/ls180/gateware/ls180.v:9423$7_ADDR[2:0]$2488 + attribute \src "build/ls180/gateware/ls180.v:9421.1-9425.4" + wire width 25 $0$memwr$\storage_2$build/ls180/gateware/ls180.v:9423$7_DATA[24:0]$2489 + attribute \src "build/ls180/gateware/ls180.v:9421.1-9425.4" + wire width 25 $0$memwr$\storage_2$build/ls180/gateware/ls180.v:9423$7_EN[24:0]$2490 + attribute \src "build/ls180/gateware/ls180.v:9435.1-9439.4" + wire width 3 $0$memwr$\storage_3$build/ls180/gateware/ls180.v:9437$8_ADDR[2:0]$2495 + attribute \src "build/ls180/gateware/ls180.v:9435.1-9439.4" + wire width 25 $0$memwr$\storage_3$build/ls180/gateware/ls180.v:9437$8_DATA[24:0]$2496 + attribute \src "build/ls180/gateware/ls180.v:9435.1-9439.4" + wire width 25 $0$memwr$\storage_3$build/ls180/gateware/ls180.v:9437$8_EN[24:0]$2497 + attribute \src "build/ls180/gateware/ls180.v:9449.1-9453.4" + wire width 3 $0$memwr$\storage_4$build/ls180/gateware/ls180.v:9451$9_ADDR[2:0]$2502 + attribute \src "build/ls180/gateware/ls180.v:9449.1-9453.4" + wire width 25 $0$memwr$\storage_4$build/ls180/gateware/ls180.v:9451$9_DATA[24:0]$2503 + attribute \src "build/ls180/gateware/ls180.v:9449.1-9453.4" + wire width 25 $0$memwr$\storage_4$build/ls180/gateware/ls180.v:9451$9_EN[24:0]$2504 + attribute \src "build/ls180/gateware/ls180.v:9463.1-9467.4" + wire width 3 $0$memwr$\storage_5$build/ls180/gateware/ls180.v:9465$10_ADDR[2:0]$2509 + attribute \src "build/ls180/gateware/ls180.v:9463.1-9467.4" + wire width 25 $0$memwr$\storage_5$build/ls180/gateware/ls180.v:9465$10_DATA[24:0]$2510 + attribute \src "build/ls180/gateware/ls180.v:9463.1-9467.4" + wire width 25 $0$memwr$\storage_5$build/ls180/gateware/ls180.v:9465$10_EN[24:0]$2511 + attribute \src "build/ls180/gateware/ls180.v:9477.1-9481.4" + wire width 5 $0$memwr$\storage_6$build/ls180/gateware/ls180.v:9479$11_ADDR[4:0]$2516 + attribute \src "build/ls180/gateware/ls180.v:9477.1-9481.4" + wire width 10 $0$memwr$\storage_6$build/ls180/gateware/ls180.v:9479$11_DATA[9:0]$2517 + attribute \src "build/ls180/gateware/ls180.v:9477.1-9481.4" + wire width 10 $0$memwr$\storage_6$build/ls180/gateware/ls180.v:9479$11_EN[9:0]$2518 + attribute \src "build/ls180/gateware/ls180.v:9491.1-9495.4" + wire width 5 $0$memwr$\storage_7$build/ls180/gateware/ls180.v:9493$12_ADDR[4:0]$2523 + attribute \src "build/ls180/gateware/ls180.v:9491.1-9495.4" + wire width 10 $0$memwr$\storage_7$build/ls180/gateware/ls180.v:9493$12_DATA[9:0]$2524 + attribute \src "build/ls180/gateware/ls180.v:9491.1-9495.4" + wire width 10 $0$memwr$\storage_7$build/ls180/gateware/ls180.v:9493$12_EN[9:0]$2525 + attribute \src "build/ls180/gateware/ls180.v:3102.1-3195.4" + wire width 3 $0\builder_bankmachine0_next_state[2:0] + attribute \src "build/ls180/gateware/ls180.v:7055.1-9363.4" + wire width 3 $0\builder_bankmachine0_state[2:0] + attribute \src "build/ls180/gateware/ls180.v:3259.1-3352.4" + wire width 3 $0\builder_bankmachine1_next_state[2:0] + attribute \src "build/ls180/gateware/ls180.v:7055.1-9363.4" + wire width 3 $0\builder_bankmachine1_state[2:0] + attribute \src "build/ls180/gateware/ls180.v:3416.1-3509.4" + wire width 3 $0\builder_bankmachine2_next_state[2:0] + attribute \src "build/ls180/gateware/ls180.v:7055.1-9363.4" + wire width 3 $0\builder_bankmachine2_state[2:0] + attribute \src "build/ls180/gateware/ls180.v:3573.1-3666.4" + wire width 3 $0\builder_bankmachine3_next_state[2:0] + attribute \src "build/ls180/gateware/ls180.v:7055.1-9363.4" + wire width 3 $0\builder_bankmachine3_state[2:0] + attribute \src "build/ls180/gateware/ls180.v:6161.1-6177.4" + wire $0\builder_comb_rhs_array_muxed0[0:0] + attribute \src "build/ls180/gateware/ls180.v:6382.1-6398.4" + wire $0\builder_comb_rhs_array_muxed10[0:0] + attribute \src "build/ls180/gateware/ls180.v:6399.1-6415.4" + wire $0\builder_comb_rhs_array_muxed11[0:0] + attribute \src "build/ls180/gateware/ls180.v:6467.1-6474.4" + wire width 22 $0\builder_comb_rhs_array_muxed12[21:0] + attribute \src "build/ls180/gateware/ls180.v:6475.1-6482.4" + wire $0\builder_comb_rhs_array_muxed13[0:0] + attribute \src "build/ls180/gateware/ls180.v:6483.1-6490.4" + wire $0\builder_comb_rhs_array_muxed14[0:0] + attribute \src "build/ls180/gateware/ls180.v:6491.1-6498.4" + wire width 22 $0\builder_comb_rhs_array_muxed15[21:0] + attribute \src "build/ls180/gateware/ls180.v:6499.1-6506.4" + wire $0\builder_comb_rhs_array_muxed16[0:0] + attribute \src "build/ls180/gateware/ls180.v:6507.1-6514.4" + wire $0\builder_comb_rhs_array_muxed17[0:0] + attribute \src "build/ls180/gateware/ls180.v:6515.1-6522.4" + wire width 22 $0\builder_comb_rhs_array_muxed18[21:0] + attribute \src "build/ls180/gateware/ls180.v:6523.1-6530.4" + wire $0\builder_comb_rhs_array_muxed19[0:0] + attribute \src "build/ls180/gateware/ls180.v:6178.1-6194.4" + wire width 13 $0\builder_comb_rhs_array_muxed1[12:0] + attribute \src "build/ls180/gateware/ls180.v:6531.1-6538.4" + wire $0\builder_comb_rhs_array_muxed20[0:0] + attribute \src "build/ls180/gateware/ls180.v:6539.1-6546.4" + wire width 22 $0\builder_comb_rhs_array_muxed21[21:0] + attribute \src "build/ls180/gateware/ls180.v:6547.1-6554.4" + wire $0\builder_comb_rhs_array_muxed22[0:0] + attribute \src "build/ls180/gateware/ls180.v:6555.1-6562.4" + wire $0\builder_comb_rhs_array_muxed23[0:0] + attribute \src "build/ls180/gateware/ls180.v:6563.1-6579.4" + wire width 32 $0\builder_comb_rhs_array_muxed24[31:0] + attribute \src "build/ls180/gateware/ls180.v:6580.1-6596.4" + wire width 32 $0\builder_comb_rhs_array_muxed25[31:0] + attribute \src "build/ls180/gateware/ls180.v:6597.1-6613.4" + wire width 4 $0\builder_comb_rhs_array_muxed26[3:0] + attribute \src "build/ls180/gateware/ls180.v:6614.1-6630.4" + wire $0\builder_comb_rhs_array_muxed27[0:0] + attribute \src "build/ls180/gateware/ls180.v:6631.1-6647.4" + wire $0\builder_comb_rhs_array_muxed28[0:0] + attribute \src "build/ls180/gateware/ls180.v:6648.1-6664.4" + wire $0\builder_comb_rhs_array_muxed29[0:0] + attribute \src "build/ls180/gateware/ls180.v:6195.1-6211.4" + wire width 2 $0\builder_comb_rhs_array_muxed2[1:0] + attribute \src "build/ls180/gateware/ls180.v:6665.1-6681.4" + wire width 3 $0\builder_comb_rhs_array_muxed30[2:0] + attribute \src "build/ls180/gateware/ls180.v:6682.1-6698.4" + wire width 2 $0\builder_comb_rhs_array_muxed31[1:0] + attribute \src "build/ls180/gateware/ls180.v:6212.1-6228.4" + wire $0\builder_comb_rhs_array_muxed3[0:0] + attribute \src "build/ls180/gateware/ls180.v:6229.1-6245.4" + wire $0\builder_comb_rhs_array_muxed4[0:0] + attribute \src "build/ls180/gateware/ls180.v:6246.1-6262.4" + wire $0\builder_comb_rhs_array_muxed5[0:0] + attribute \src "build/ls180/gateware/ls180.v:6314.1-6330.4" + wire $0\builder_comb_rhs_array_muxed6[0:0] + attribute \src "build/ls180/gateware/ls180.v:6331.1-6347.4" + wire width 13 $0\builder_comb_rhs_array_muxed7[12:0] + attribute \src "build/ls180/gateware/ls180.v:6348.1-6364.4" + wire width 2 $0\builder_comb_rhs_array_muxed8[1:0] + attribute \src "build/ls180/gateware/ls180.v:6365.1-6381.4" + wire $0\builder_comb_rhs_array_muxed9[0:0] + attribute \src "build/ls180/gateware/ls180.v:6263.1-6279.4" + wire $0\builder_comb_t_array_muxed0[0:0] + attribute \src "build/ls180/gateware/ls180.v:6280.1-6296.4" + wire $0\builder_comb_t_array_muxed1[0:0] + attribute \src "build/ls180/gateware/ls180.v:6297.1-6313.4" + wire $0\builder_comb_t_array_muxed2[0:0] + attribute \src "build/ls180/gateware/ls180.v:6416.1-6432.4" + wire $0\builder_comb_t_array_muxed3[0:0] + attribute \src "build/ls180/gateware/ls180.v:6433.1-6449.4" + wire $0\builder_comb_t_array_muxed4[0:0] + attribute \src "build/ls180/gateware/ls180.v:6450.1-6466.4" + wire $0\builder_comb_t_array_muxed5[0:0] + attribute \src "build/ls180/gateware/ls180.v:2606.1-2652.4" + wire $0\builder_converter0_next_state[0:0] + attribute \src "build/ls180/gateware/ls180.v:7055.1-9363.4" + wire $0\builder_converter0_state[0:0] + attribute \src "build/ls180/gateware/ls180.v:2666.1-2712.4" + wire $0\builder_converter1_next_state[0:0] + attribute \src "build/ls180/gateware/ls180.v:7055.1-9363.4" + wire $0\builder_converter1_state[0:0] + attribute \src "build/ls180/gateware/ls180.v:3919.1-3965.4" + wire $0\builder_converter_next_state[0:0] + attribute \src "build/ls180/gateware/ls180.v:7055.1-9363.4" + wire $0\builder_converter_state[0:0] + attribute \src "build/ls180/gateware/ls180.v:7055.1-9363.4" + wire width 20 $0\builder_count[19:0] + attribute \src "build/ls180/gateware/ls180.v:5509.1-5520.4" + wire $0\builder_error[0:0] + attribute \src "build/ls180/gateware/ls180.v:7055.1-9363.4" + wire width 2 $0\builder_grant[1:0] + attribute \src "build/ls180/gateware/ls180.v:6968.1-7053.4" + wire $0\builder_inferedsdrtristate0__o[0:0] + attribute \src "build/ls180/gateware/ls180.v:6968.1-7053.4" + wire $0\builder_inferedsdrtristate0_oe[0:0] + attribute \src "build/ls180/gateware/ls180.v:6968.1-7053.4" + wire $0\builder_inferedsdrtristate10__o[0:0] + attribute \src "build/ls180/gateware/ls180.v:6968.1-7053.4" + wire $0\builder_inferedsdrtristate10_oe[0:0] + attribute \src "build/ls180/gateware/ls180.v:6968.1-7053.4" + wire $0\builder_inferedsdrtristate11__o[0:0] + attribute \src "build/ls180/gateware/ls180.v:6968.1-7053.4" + wire $0\builder_inferedsdrtristate11_oe[0:0] + attribute \src "build/ls180/gateware/ls180.v:6968.1-7053.4" + wire $0\builder_inferedsdrtristate12__o[0:0] + attribute \src "build/ls180/gateware/ls180.v:6968.1-7053.4" + wire $0\builder_inferedsdrtristate12_oe[0:0] + attribute \src "build/ls180/gateware/ls180.v:6968.1-7053.4" + wire $0\builder_inferedsdrtristate13__o[0:0] + attribute \src "build/ls180/gateware/ls180.v:6968.1-7053.4" + wire $0\builder_inferedsdrtristate13_oe[0:0] + attribute \src "build/ls180/gateware/ls180.v:6968.1-7053.4" + wire $0\builder_inferedsdrtristate14__o[0:0] + attribute \src "build/ls180/gateware/ls180.v:6968.1-7053.4" + wire $0\builder_inferedsdrtristate14_oe[0:0] + attribute \src "build/ls180/gateware/ls180.v:6968.1-7053.4" + wire $0\builder_inferedsdrtristate15__o[0:0] + attribute \src "build/ls180/gateware/ls180.v:6968.1-7053.4" + wire $0\builder_inferedsdrtristate15_oe[0:0] + attribute \src "build/ls180/gateware/ls180.v:6968.1-7053.4" + wire $0\builder_inferedsdrtristate16__o[0:0] + attribute \src "build/ls180/gateware/ls180.v:6968.1-7053.4" + wire $0\builder_inferedsdrtristate16_oe[0:0] + attribute \src "build/ls180/gateware/ls180.v:6968.1-7053.4" + wire $0\builder_inferedsdrtristate17__o[0:0] + attribute \src "build/ls180/gateware/ls180.v:6968.1-7053.4" + wire $0\builder_inferedsdrtristate17_oe[0:0] + attribute \src "build/ls180/gateware/ls180.v:6968.1-7053.4" + wire $0\builder_inferedsdrtristate18__o[0:0] + attribute \src "build/ls180/gateware/ls180.v:6968.1-7053.4" + wire $0\builder_inferedsdrtristate18_oe[0:0] + attribute \src "build/ls180/gateware/ls180.v:6968.1-7053.4" + wire $0\builder_inferedsdrtristate19__o[0:0] + attribute \src "build/ls180/gateware/ls180.v:6968.1-7053.4" + wire $0\builder_inferedsdrtristate19_oe[0:0] + attribute \src "build/ls180/gateware/ls180.v:6968.1-7053.4" + wire $0\builder_inferedsdrtristate1__o[0:0] + attribute \src "build/ls180/gateware/ls180.v:6968.1-7053.4" + wire $0\builder_inferedsdrtristate1_oe[0:0] + attribute \src "build/ls180/gateware/ls180.v:6968.1-7053.4" + wire $0\builder_inferedsdrtristate20__o[0:0] + attribute \src "build/ls180/gateware/ls180.v:6968.1-7053.4" + wire $0\builder_inferedsdrtristate20_oe[0:0] + attribute \src "build/ls180/gateware/ls180.v:6968.1-7053.4" + wire $0\builder_inferedsdrtristate2__o[0:0] + attribute \src "build/ls180/gateware/ls180.v:6968.1-7053.4" + wire $0\builder_inferedsdrtristate2_oe[0:0] + attribute \src "build/ls180/gateware/ls180.v:6968.1-7053.4" + wire $0\builder_inferedsdrtristate3__o[0:0] + attribute \src "build/ls180/gateware/ls180.v:6968.1-7053.4" + wire $0\builder_inferedsdrtristate3_oe[0:0] + attribute \src "build/ls180/gateware/ls180.v:6968.1-7053.4" + wire $0\builder_inferedsdrtristate4__o[0:0] + attribute \src "build/ls180/gateware/ls180.v:6968.1-7053.4" + wire $0\builder_inferedsdrtristate4_oe[0:0] + attribute \src "build/ls180/gateware/ls180.v:6968.1-7053.4" + wire $0\builder_inferedsdrtristate5__o[0:0] + attribute \src "build/ls180/gateware/ls180.v:6968.1-7053.4" + wire $0\builder_inferedsdrtristate5_oe[0:0] + attribute \src "build/ls180/gateware/ls180.v:6968.1-7053.4" + wire $0\builder_inferedsdrtristate6__o[0:0] + attribute \src "build/ls180/gateware/ls180.v:6968.1-7053.4" + wire $0\builder_inferedsdrtristate6_oe[0:0] + attribute \src "build/ls180/gateware/ls180.v:6968.1-7053.4" + wire $0\builder_inferedsdrtristate7__o[0:0] + attribute \src "build/ls180/gateware/ls180.v:6968.1-7053.4" + wire $0\builder_inferedsdrtristate7_oe[0:0] + attribute \src "build/ls180/gateware/ls180.v:6968.1-7053.4" + wire $0\builder_inferedsdrtristate8__o[0:0] + attribute \src "build/ls180/gateware/ls180.v:6968.1-7053.4" + wire $0\builder_inferedsdrtristate8_oe[0:0] + attribute \src "build/ls180/gateware/ls180.v:6968.1-7053.4" + wire $0\builder_inferedsdrtristate9__o[0:0] + attribute \src "build/ls180/gateware/ls180.v:6968.1-7053.4" + wire $0\builder_inferedsdrtristate9_oe[0:0] + attribute \src "build/ls180/gateware/ls180.v:7055.1-9363.4" + wire width 8 $0\builder_interface0_bank_bus_dat_r[7:0] + attribute \src "build/ls180/gateware/ls180.v:7055.1-9363.4" + wire width 8 $0\builder_interface10_bank_bus_dat_r[7:0] + attribute \src "build/ls180/gateware/ls180.v:7055.1-9363.4" + wire width 8 $0\builder_interface11_bank_bus_dat_r[7:0] + attribute \src "build/ls180/gateware/ls180.v:7055.1-9363.4" + wire width 8 $0\builder_interface12_bank_bus_dat_r[7:0] + attribute \src "build/ls180/gateware/ls180.v:7055.1-9363.4" + wire width 8 $0\builder_interface1_bank_bus_dat_r[7:0] + attribute \src "build/ls180/gateware/ls180.v:7055.1-9363.4" + wire width 8 $0\builder_interface2_bank_bus_dat_r[7:0] + attribute \src "build/ls180/gateware/ls180.v:7055.1-9363.4" + wire width 8 $0\builder_interface3_bank_bus_dat_r[7:0] + attribute \src "build/ls180/gateware/ls180.v:7055.1-9363.4" + wire width 8 $0\builder_interface4_bank_bus_dat_r[7:0] + attribute \src "build/ls180/gateware/ls180.v:7055.1-9363.4" + wire width 8 $0\builder_interface5_bank_bus_dat_r[7:0] + attribute \src "build/ls180/gateware/ls180.v:7055.1-9363.4" + wire width 8 $0\builder_interface6_bank_bus_dat_r[7:0] + attribute \src "build/ls180/gateware/ls180.v:7055.1-9363.4" + wire width 8 $0\builder_interface7_bank_bus_dat_r[7:0] + attribute \src "build/ls180/gateware/ls180.v:7055.1-9363.4" + wire width 8 $0\builder_interface8_bank_bus_dat_r[7:0] + attribute \src "build/ls180/gateware/ls180.v:7055.1-9363.4" + wire width 8 $0\builder_interface9_bank_bus_dat_r[7:0] + attribute \src "build/ls180/gateware/ls180.v:7055.1-9363.4" + wire width 14 $0\builder_libresocsim_adr[13:0] + attribute \src "build/ls180/gateware/ls180.v:5401.1-5437.4" + wire width 14 $0\builder_libresocsim_adr_next_value1[13:0] + attribute \src "build/ls180/gateware/ls180.v:5401.1-5437.4" + wire $0\builder_libresocsim_adr_next_value_ce1[0:0] + attribute \src "build/ls180/gateware/ls180.v:7055.1-9363.4" + wire width 8 $0\builder_libresocsim_dat_w[7:0] + attribute \src "build/ls180/gateware/ls180.v:5401.1-5437.4" + wire width 8 $0\builder_libresocsim_dat_w_next_value0[7:0] + attribute \src "build/ls180/gateware/ls180.v:5401.1-5437.4" + wire $0\builder_libresocsim_dat_w_next_value_ce0[0:0] + attribute \src "build/ls180/gateware/ls180.v:7055.1-9363.4" + wire $0\builder_libresocsim_we[0:0] + attribute \src "build/ls180/gateware/ls180.v:5401.1-5437.4" + wire $0\builder_libresocsim_we_next_value2[0:0] + attribute \src "build/ls180/gateware/ls180.v:5401.1-5437.4" + wire $0\builder_libresocsim_we_next_value_ce2[0:0] + attribute \src "build/ls180/gateware/ls180.v:5401.1-5437.4" + wire $0\builder_libresocsim_wishbone_ack[0:0] + attribute \src "build/ls180/gateware/ls180.v:5401.1-5437.4" + wire width 32 $0\builder_libresocsim_wishbone_dat_r[31:0] + attribute \src "build/ls180/gateware/ls180.v:1761.5-1761.44" + wire $0\builder_libresocsim_wishbone_err[0:0] + attribute \src "build/ls180/gateware/ls180.v:1650.5-1650.27" + wire $0\builder_locked0[0:0] + attribute \src "build/ls180/gateware/ls180.v:1651.5-1651.27" + wire $0\builder_locked1[0:0] + attribute \src "build/ls180/gateware/ls180.v:1652.5-1652.27" + wire $0\builder_locked2[0:0] + attribute \src "build/ls180/gateware/ls180.v:1653.5-1653.27" + wire $0\builder_locked3[0:0] + attribute \src "build/ls180/gateware/ls180.v:3791.1-3863.4" + wire width 3 $0\builder_multiplexer_next_state[2:0] + attribute \src "build/ls180/gateware/ls180.v:7055.1-9363.4" + wire width 3 $0\builder_multiplexer_state[2:0] + attribute \src "build/ls180/gateware/ls180.v:7055.1-9363.4" + wire $0\builder_multiregimpl0_regs0[0:0] + attribute \src "build/ls180/gateware/ls180.v:7055.1-9363.4" + wire $0\builder_multiregimpl0_regs1[0:0] + attribute \src "build/ls180/gateware/ls180.v:7055.1-9363.4" + wire width 8 $0\builder_multiregimpl1_regs0[7:0] + attribute \src "build/ls180/gateware/ls180.v:7055.1-9363.4" + wire width 8 $0\builder_multiregimpl1_regs1[7:0] + attribute \src "build/ls180/gateware/ls180.v:7055.1-9363.4" + wire width 8 $0\builder_multiregimpl2_regs0[7:0] + attribute \src "build/ls180/gateware/ls180.v:7055.1-9363.4" + wire width 8 $0\builder_multiregimpl2_regs1[7:0] + attribute \src "build/ls180/gateware/ls180.v:7055.1-9363.4" + wire $0\builder_new_master_rdata_valid0[0:0] + attribute \src "build/ls180/gateware/ls180.v:7055.1-9363.4" + wire $0\builder_new_master_rdata_valid1[0:0] + attribute \src "build/ls180/gateware/ls180.v:7055.1-9363.4" + wire $0\builder_new_master_rdata_valid2[0:0] + attribute \src "build/ls180/gateware/ls180.v:7055.1-9363.4" + wire $0\builder_new_master_rdata_valid3[0:0] + attribute \src "build/ls180/gateware/ls180.v:7055.1-9363.4" + wire $0\builder_new_master_wdata_ready[0:0] + attribute \src "build/ls180/gateware/ls180.v:5401.1-5437.4" + wire width 2 $0\builder_next_state[1:0] + attribute \src "build/ls180/gateware/ls180.v:3008.1-3038.4" + wire width 2 $0\builder_refresher_next_state[1:0] + attribute \src "build/ls180/gateware/ls180.v:7055.1-9363.4" + wire width 2 $0\builder_refresher_state[1:0] + attribute \src "build/ls180/gateware/ls180.v:5152.1-5191.4" + wire width 2 $0\builder_sdblock2memdma_next_state[1:0] + attribute \src "build/ls180/gateware/ls180.v:7055.1-9363.4" + wire width 2 $0\builder_sdblock2memdma_state[1:0] + attribute \src "build/ls180/gateware/ls180.v:4719.1-4798.4" + wire $0\builder_sdcore_crcupstreaminserter_next_state[0:0] + attribute \src "build/ls180/gateware/ls180.v:7055.1-9363.4" + wire $0\builder_sdcore_crcupstreaminserter_state[0:0] + attribute \src "build/ls180/gateware/ls180.v:4901.1-5091.4" + wire width 3 $0\builder_sdcore_fsm_next_state[2:0] + attribute \src "build/ls180/gateware/ls180.v:7055.1-9363.4" + wire width 3 $0\builder_sdcore_fsm_state[2:0] + attribute \src "build/ls180/gateware/ls180.v:5211.1-5248.4" + wire $0\builder_sdmem2blockdma_fsm_next_state[0:0] + attribute \src "build/ls180/gateware/ls180.v:7055.1-9363.4" + wire $0\builder_sdmem2blockdma_fsm_state[0:0] + attribute \src "build/ls180/gateware/ls180.v:5249.1-5285.4" + wire width 2 $0\builder_sdmem2blockdma_resetinserter_next_state[1:0] + attribute \src "build/ls180/gateware/ls180.v:7055.1-9363.4" + wire width 2 $0\builder_sdmem2blockdma_resetinserter_state[1:0] + attribute \src "build/ls180/gateware/ls180.v:4394.1-4466.4" + wire width 3 $0\builder_sdphy_fsm_next_state[2:0] + attribute \src "build/ls180/gateware/ls180.v:7055.1-9363.4" + wire width 3 $0\builder_sdphy_fsm_state[2:0] + attribute \src "build/ls180/gateware/ls180.v:4239.1-4332.4" + wire width 3 $0\builder_sdphy_sdphycmdr_next_state[2:0] + attribute \src "build/ls180/gateware/ls180.v:7055.1-9363.4" + wire width 3 $0\builder_sdphy_sdphycmdr_state[2:0] + attribute \src "build/ls180/gateware/ls180.v:4129.1-4205.4" + wire width 2 $0\builder_sdphy_sdphycmdw_next_state[1:0] + attribute \src "build/ls180/gateware/ls180.v:7055.1-9363.4" + wire width 2 $0\builder_sdphy_sdphycmdw_state[1:0] + attribute \src "build/ls180/gateware/ls180.v:4366.1-4393.4" + wire $0\builder_sdphy_sdphycrcr_next_state[0:0] + attribute \src "build/ls180/gateware/ls180.v:7055.1-9363.4" + wire $0\builder_sdphy_sdphycrcr_state[0:0] + attribute \src "build/ls180/gateware/ls180.v:4500.1-4601.4" + wire width 3 $0\builder_sdphy_sdphydatar_next_state[2:0] + attribute \src "build/ls180/gateware/ls180.v:7055.1-9363.4" + wire width 3 $0\builder_sdphy_sdphydatar_state[2:0] + attribute \src "build/ls180/gateware/ls180.v:4095.1-4128.4" + wire $0\builder_sdphy_sdphyinit_next_state[0:0] + attribute \src "build/ls180/gateware/ls180.v:7055.1-9363.4" + wire $0\builder_sdphy_sdphyinit_state[0:0] + attribute \src "build/ls180/gateware/ls180.v:5509.1-5520.4" + wire $0\builder_shared_ack[0:0] + attribute \src "build/ls180/gateware/ls180.v:5509.1-5520.4" + wire width 32 $0\builder_shared_dat_r[31:0] + attribute \src "build/ls180/gateware/ls180.v:5459.1-5466.4" + wire width 5 $0\builder_slave_sel[4:0] + attribute \src "build/ls180/gateware/ls180.v:7055.1-9363.4" + wire width 5 $0\builder_slave_sel_r[4:0] + attribute \src "build/ls180/gateware/ls180.v:3989.1-4037.4" + wire width 2 $0\builder_spimaster0_next_state[1:0] + attribute \src "build/ls180/gateware/ls180.v:7055.1-9363.4" + wire width 2 $0\builder_spimaster0_state[1:0] + attribute \src "build/ls180/gateware/ls180.v:5352.1-5400.4" + wire width 2 $0\builder_spimaster1_next_state[1:0] + attribute \src "build/ls180/gateware/ls180.v:7055.1-9363.4" + wire width 2 $0\builder_spimaster1_state[1:0] + attribute \src "build/ls180/gateware/ls180.v:7055.1-9363.4" + wire width 2 $0\builder_state[1:0] + attribute \src "build/ls180/gateware/ls180.v:6818.1-6846.4" + wire $0\builder_sync_f_array_muxed0[0:0] + attribute \src "build/ls180/gateware/ls180.v:6847.1-6875.4" + wire $0\builder_sync_f_array_muxed1[0:0] + attribute \src "build/ls180/gateware/ls180.v:6699.1-6715.4" + wire width 2 $0\builder_sync_rhs_array_muxed0[1:0] + attribute \src "build/ls180/gateware/ls180.v:6716.1-6732.4" + wire width 13 $0\builder_sync_rhs_array_muxed1[12:0] + attribute \src "build/ls180/gateware/ls180.v:6733.1-6749.4" + wire $0\builder_sync_rhs_array_muxed2[0:0] + attribute \src "build/ls180/gateware/ls180.v:6750.1-6766.4" + wire $0\builder_sync_rhs_array_muxed3[0:0] + attribute \src "build/ls180/gateware/ls180.v:6767.1-6783.4" + wire $0\builder_sync_rhs_array_muxed4[0:0] + attribute \src "build/ls180/gateware/ls180.v:6784.1-6800.4" + wire $0\builder_sync_rhs_array_muxed5[0:0] + attribute \src "build/ls180/gateware/ls180.v:6801.1-6817.4" + wire $0\builder_sync_rhs_array_muxed6[0:0] + attribute \src "build/ls180/gateware/ls180.v:7055.1-9363.4" + wire width 16 $0\libresocsim_clk_divider1[15:0] + attribute \src "build/ls180/gateware/ls180.v:5352.1-5400.4" + wire $0\libresocsim_clk_enable[0:0] + attribute \src "build/ls180/gateware/ls180.v:7055.1-9363.4" + wire $0\libresocsim_clocker_clk0[0:0] + attribute \src "build/ls180/gateware/ls180.v:4065.1-4093.4" + wire $0\libresocsim_clocker_clk1[0:0] + attribute \src "build/ls180/gateware/ls180.v:7055.1-9363.4" + wire $0\libresocsim_clocker_clk_d[0:0] + attribute \src "build/ls180/gateware/ls180.v:7055.1-9363.4" + wire width 9 $0\libresocsim_clocker_clks[8:0] + attribute \src "build/ls180/gateware/ls180.v:7055.1-9363.4" + wire $0\libresocsim_clocker_re[0:0] + attribute \src "build/ls180/gateware/ls180.v:7055.1-9363.4" + wire width 9 $0\libresocsim_clocker_storage[8:0] + attribute \src "build/ls180/gateware/ls180.v:7055.1-9363.4" + wire $0\libresocsim_cmdr_cmdr_buf_source_first[0:0] + attribute \src "build/ls180/gateware/ls180.v:7055.1-9363.4" + wire $0\libresocsim_cmdr_cmdr_buf_source_last[0:0] + attribute \src "build/ls180/gateware/ls180.v:7055.1-9363.4" + wire width 8 $0\libresocsim_cmdr_cmdr_buf_source_payload_data[7:0] + attribute \src "build/ls180/gateware/ls180.v:7055.1-9363.4" + wire $0\libresocsim_cmdr_cmdr_buf_source_valid[0:0] + attribute \src "build/ls180/gateware/ls180.v:7055.1-9363.4" + wire width 3 $0\libresocsim_cmdr_cmdr_converter_demux[2:0] + attribute \src "build/ls180/gateware/ls180.v:1029.5-1029.54" + wire $0\libresocsim_cmdr_cmdr_converter_sink_first[0:0] + attribute \src "build/ls180/gateware/ls180.v:1030.5-1030.53" + wire $0\libresocsim_cmdr_cmdr_converter_sink_last[0:0] + attribute \src "build/ls180/gateware/ls180.v:7055.1-9363.4" + wire $0\libresocsim_cmdr_cmdr_converter_source_first[0:0] + attribute \src "build/ls180/gateware/ls180.v:7055.1-9363.4" + wire $0\libresocsim_cmdr_cmdr_converter_source_last[0:0] + attribute \src "build/ls180/gateware/ls180.v:7055.1-9363.4" + wire width 8 $0\libresocsim_cmdr_cmdr_converter_source_payload_data[7:0] + attribute \src "build/ls180/gateware/ls180.v:7055.1-9363.4" + wire width 4 $0\libresocsim_cmdr_cmdr_converter_source_payload_valid_token_count[3:0] + attribute \src "build/ls180/gateware/ls180.v:7055.1-9363.4" + wire $0\libresocsim_cmdr_cmdr_converter_strobe_all[0:0] + attribute \src "build/ls180/gateware/ls180.v:1010.5-1010.47" + wire $0\libresocsim_cmdr_cmdr_pads_in_ready[0:0] + attribute \src "build/ls180/gateware/ls180.v:7055.1-9363.4" + wire $0\libresocsim_cmdr_cmdr_reset[0:0] + attribute \src "build/ls180/gateware/ls180.v:4239.1-4332.4" + wire $0\libresocsim_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value2[0:0] + attribute \src "build/ls180/gateware/ls180.v:4239.1-4332.4" + wire $0\libresocsim_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value_ce2[0:0] + attribute \src "build/ls180/gateware/ls180.v:7055.1-9363.4" + wire $0\libresocsim_cmdr_cmdr_run[0:0] + attribute \src "build/ls180/gateware/ls180.v:4239.1-4332.4" + wire $0\libresocsim_cmdr_cmdr_source_source_ready0[0:0] + attribute \src "build/ls180/gateware/ls180.v:7055.1-9363.4" + wire width 8 $0\libresocsim_cmdr_count[7:0] + attribute \src "build/ls180/gateware/ls180.v:4239.1-4332.4" + wire width 8 $0\libresocsim_cmdr_count_sdphy_sdphycmdr_next_value0[7:0] + attribute \src "build/ls180/gateware/ls180.v:4239.1-4332.4" + wire $0\libresocsim_cmdr_count_sdphy_sdphycmdr_next_value_ce0[0:0] + attribute \src "build/ls180/gateware/ls180.v:983.5-983.50" + wire $0\libresocsim_cmdr_pads_in_pads_in_first[0:0] + attribute \src "build/ls180/gateware/ls180.v:984.5-984.49" + wire $0\libresocsim_cmdr_pads_in_pads_in_last[0:0] + attribute \src "build/ls180/gateware/ls180.v:985.5-985.56" + wire $0\libresocsim_cmdr_pads_in_pads_in_payload_clk[0:0] + attribute \src "build/ls180/gateware/ls180.v:987.5-987.58" + wire $0\libresocsim_cmdr_pads_in_pads_in_payload_cmd_o[0:0] + attribute \src "build/ls180/gateware/ls180.v:988.5-988.59" + wire $0\libresocsim_cmdr_pads_in_pads_in_payload_cmd_oe[0:0] + attribute \src "build/ls180/gateware/ls180.v:990.11-990.65" + wire width 4 $0\libresocsim_cmdr_pads_in_pads_in_payload_data_o[3:0] + attribute \src "build/ls180/gateware/ls180.v:991.5-991.60" + wire $0\libresocsim_cmdr_pads_in_pads_in_payload_data_oe[0:0] + attribute \src "build/ls180/gateware/ls180.v:4239.1-4332.4" + wire $0\libresocsim_cmdr_pads_out_payload_clk[0:0] + attribute \src "build/ls180/gateware/ls180.v:4239.1-4332.4" + wire $0\libresocsim_cmdr_pads_out_payload_cmd_o[0:0] + attribute \src "build/ls180/gateware/ls180.v:4239.1-4332.4" + wire $0\libresocsim_cmdr_pads_out_payload_cmd_oe[0:0] + attribute \src "build/ls180/gateware/ls180.v:996.11-996.58" + wire width 4 $0\libresocsim_cmdr_pads_out_payload_data_o[3:0] + attribute \src "build/ls180/gateware/ls180.v:997.5-997.53" + wire $0\libresocsim_cmdr_pads_out_payload_data_oe[0:0] + attribute \src "build/ls180/gateware/ls180.v:4901.1-5091.4" + wire $0\libresocsim_cmdr_sink_last[0:0] + attribute \src "build/ls180/gateware/ls180.v:4901.1-5091.4" + wire width 8 $0\libresocsim_cmdr_sink_payload_length[7:0] + attribute \src "build/ls180/gateware/ls180.v:4239.1-4332.4" + wire $0\libresocsim_cmdr_sink_ready[0:0] + attribute \src "build/ls180/gateware/ls180.v:4901.1-5091.4" + wire $0\libresocsim_cmdr_sink_valid[0:0] + attribute \src "build/ls180/gateware/ls180.v:4239.1-4332.4" + wire $0\libresocsim_cmdr_source_last[0:0] + attribute \src "build/ls180/gateware/ls180.v:4239.1-4332.4" + wire width 8 $0\libresocsim_cmdr_source_payload_data[7:0] + attribute \src "build/ls180/gateware/ls180.v:4239.1-4332.4" + wire width 3 $0\libresocsim_cmdr_source_payload_status[2:0] + attribute \src "build/ls180/gateware/ls180.v:4901.1-5091.4" + wire $0\libresocsim_cmdr_source_ready[0:0] + attribute \src "build/ls180/gateware/ls180.v:4239.1-4332.4" + wire $0\libresocsim_cmdr_source_valid[0:0] + attribute \src "build/ls180/gateware/ls180.v:7055.1-9363.4" + wire width 32 $0\libresocsim_cmdr_timeout[31:0] + attribute \src "build/ls180/gateware/ls180.v:4239.1-4332.4" + wire width 32 $0\libresocsim_cmdr_timeout_sdphy_sdphycmdr_next_value1[31:0] + attribute \src "build/ls180/gateware/ls180.v:4239.1-4332.4" + wire $0\libresocsim_cmdr_timeout_sdphy_sdphycmdr_next_value_ce1[0:0] + attribute \src "build/ls180/gateware/ls180.v:7055.1-9363.4" + wire width 8 $0\libresocsim_cmdw_count[7:0] + attribute \src "build/ls180/gateware/ls180.v:4129.1-4205.4" + wire width 8 $0\libresocsim_cmdw_count_sdphy_sdphycmdw_next_value[7:0] + attribute \src "build/ls180/gateware/ls180.v:4129.1-4205.4" + wire $0\libresocsim_cmdw_count_sdphy_sdphycmdw_next_value_ce[0:0] + attribute \src "build/ls180/gateware/ls180.v:4129.1-4205.4" + wire $0\libresocsim_cmdw_done[0:0] + attribute \src "build/ls180/gateware/ls180.v:4129.1-4205.4" + wire $0\libresocsim_cmdw_pads_out_payload_clk[0:0] + attribute \src "build/ls180/gateware/ls180.v:4129.1-4205.4" + wire $0\libresocsim_cmdw_pads_out_payload_cmd_o[0:0] + attribute \src "build/ls180/gateware/ls180.v:4129.1-4205.4" + wire $0\libresocsim_cmdw_pads_out_payload_cmd_oe[0:0] + attribute \src "build/ls180/gateware/ls180.v:973.11-973.58" + wire width 4 $0\libresocsim_cmdw_pads_out_payload_data_o[3:0] + attribute \src "build/ls180/gateware/ls180.v:974.5-974.53" + wire $0\libresocsim_cmdw_pads_out_payload_data_oe[0:0] + attribute \src "build/ls180/gateware/ls180.v:4901.1-5091.4" + wire $0\libresocsim_cmdw_sink_last[0:0] + attribute \src "build/ls180/gateware/ls180.v:4901.1-5091.4" + wire width 8 $0\libresocsim_cmdw_sink_payload_data[7:0] + attribute \src "build/ls180/gateware/ls180.v:4129.1-4205.4" + wire $0\libresocsim_cmdw_sink_ready[0:0] + attribute \src "build/ls180/gateware/ls180.v:4901.1-5091.4" + wire $0\libresocsim_cmdw_sink_valid[0:0] + attribute \src "build/ls180/gateware/ls180.v:7055.1-9363.4" + wire $0\libresocsim_control_re[0:0] + attribute \src "build/ls180/gateware/ls180.v:7055.1-9363.4" + wire width 16 $0\libresocsim_control_storage[15:0] + attribute \src "build/ls180/gateware/ls180.v:7055.1-9363.4" + wire width 3 $0\libresocsim_count[2:0] + attribute \src "build/ls180/gateware/ls180.v:5352.1-5400.4" + wire width 3 $0\libresocsim_count_spimaster1_next_value[2:0] + attribute \src "build/ls180/gateware/ls180.v:5352.1-5400.4" + wire $0\libresocsim_count_spimaster1_next_value_ce[0:0] + attribute \src "build/ls180/gateware/ls180.v:5352.1-5400.4" + wire $0\libresocsim_cs_enable[0:0] + attribute \src "build/ls180/gateware/ls180.v:7055.1-9363.4" + wire $0\libresocsim_cs_re[0:0] + attribute \src "build/ls180/gateware/ls180.v:7055.1-9363.4" + wire $0\libresocsim_cs_storage[0:0] + attribute \src "build/ls180/gateware/ls180.v:7055.1-9363.4" + wire width 10 $0\libresocsim_datar_count[9:0] + attribute \src "build/ls180/gateware/ls180.v:4500.1-4601.4" + wire width 10 $0\libresocsim_datar_count_sdphy_sdphydatar_next_value0[9:0] + attribute \src "build/ls180/gateware/ls180.v:4500.1-4601.4" + wire $0\libresocsim_datar_count_sdphy_sdphydatar_next_value_ce0[0:0] + attribute \src "build/ls180/gateware/ls180.v:7055.1-9363.4" + wire $0\libresocsim_datar_datar_buf_source_first[0:0] + attribute \src "build/ls180/gateware/ls180.v:7055.1-9363.4" + wire $0\libresocsim_datar_datar_buf_source_last[0:0] + attribute \src "build/ls180/gateware/ls180.v:7055.1-9363.4" + wire width 8 $0\libresocsim_datar_datar_buf_source_payload_data[7:0] + attribute \src "build/ls180/gateware/ls180.v:7055.1-9363.4" + wire $0\libresocsim_datar_datar_buf_source_valid[0:0] + attribute \src "build/ls180/gateware/ls180.v:7055.1-9363.4" + wire $0\libresocsim_datar_datar_converter_demux[0:0] + attribute \src "build/ls180/gateware/ls180.v:1185.5-1185.56" + wire $0\libresocsim_datar_datar_converter_sink_first[0:0] + attribute \src "build/ls180/gateware/ls180.v:1186.5-1186.55" + wire $0\libresocsim_datar_datar_converter_sink_last[0:0] + attribute \src "build/ls180/gateware/ls180.v:7055.1-9363.4" + wire $0\libresocsim_datar_datar_converter_source_first[0:0] + attribute \src "build/ls180/gateware/ls180.v:7055.1-9363.4" + wire $0\libresocsim_datar_datar_converter_source_last[0:0] + attribute \src "build/ls180/gateware/ls180.v:7055.1-9363.4" + wire width 8 $0\libresocsim_datar_datar_converter_source_payload_data[7:0] + attribute \src "build/ls180/gateware/ls180.v:7055.1-9363.4" + wire width 2 $0\libresocsim_datar_datar_converter_source_payload_valid_token_count[1:0] + attribute \src "build/ls180/gateware/ls180.v:7055.1-9363.4" + wire $0\libresocsim_datar_datar_converter_strobe_all[0:0] + attribute \src "build/ls180/gateware/ls180.v:1166.5-1166.49" + wire $0\libresocsim_datar_datar_pads_in_ready[0:0] + attribute \src "build/ls180/gateware/ls180.v:7055.1-9363.4" + wire $0\libresocsim_datar_datar_reset[0:0] + attribute \src "build/ls180/gateware/ls180.v:4500.1-4601.4" + wire $0\libresocsim_datar_datar_reset_sdphy_sdphydatar_next_value2[0:0] + attribute \src "build/ls180/gateware/ls180.v:4500.1-4601.4" + wire $0\libresocsim_datar_datar_reset_sdphy_sdphydatar_next_value_ce2[0:0] + attribute \src "build/ls180/gateware/ls180.v:7055.1-9363.4" + wire $0\libresocsim_datar_datar_run[0:0] + attribute \src "build/ls180/gateware/ls180.v:4500.1-4601.4" + wire $0\libresocsim_datar_datar_source_source_ready0[0:0] + attribute \src "build/ls180/gateware/ls180.v:1137.5-1137.51" + wire $0\libresocsim_datar_pads_in_pads_in_first[0:0] + attribute \src "build/ls180/gateware/ls180.v:1138.5-1138.50" + wire $0\libresocsim_datar_pads_in_pads_in_last[0:0] + attribute \src "build/ls180/gateware/ls180.v:1139.5-1139.57" + wire $0\libresocsim_datar_pads_in_pads_in_payload_clk[0:0] + attribute \src "build/ls180/gateware/ls180.v:1141.5-1141.59" + wire $0\libresocsim_datar_pads_in_pads_in_payload_cmd_o[0:0] + attribute \src "build/ls180/gateware/ls180.v:1142.5-1142.60" + wire $0\libresocsim_datar_pads_in_pads_in_payload_cmd_oe[0:0] + attribute \src "build/ls180/gateware/ls180.v:1144.11-1144.66" + wire width 4 $0\libresocsim_datar_pads_in_pads_in_payload_data_o[3:0] + attribute \src "build/ls180/gateware/ls180.v:1145.5-1145.61" + wire $0\libresocsim_datar_pads_in_pads_in_payload_data_oe[0:0] + attribute \src "build/ls180/gateware/ls180.v:4500.1-4601.4" + wire $0\libresocsim_datar_pads_out_payload_clk[0:0] + attribute \src "build/ls180/gateware/ls180.v:1148.5-1148.52" + wire $0\libresocsim_datar_pads_out_payload_cmd_o[0:0] + attribute \src "build/ls180/gateware/ls180.v:1149.5-1149.53" + wire $0\libresocsim_datar_pads_out_payload_cmd_oe[0:0] + attribute \src "build/ls180/gateware/ls180.v:1150.11-1150.59" + wire width 4 $0\libresocsim_datar_pads_out_payload_data_o[3:0] + attribute \src "build/ls180/gateware/ls180.v:1151.5-1151.54" + wire $0\libresocsim_datar_pads_out_payload_data_oe[0:0] + attribute \src "build/ls180/gateware/ls180.v:4901.1-5091.4" + wire $0\libresocsim_datar_sink_last[0:0] + attribute \src "build/ls180/gateware/ls180.v:4901.1-5091.4" + wire width 10 $0\libresocsim_datar_sink_payload_block_length[9:0] + attribute \src "build/ls180/gateware/ls180.v:4500.1-4601.4" + wire $0\libresocsim_datar_sink_ready[0:0] + attribute \src "build/ls180/gateware/ls180.v:4901.1-5091.4" + wire $0\libresocsim_datar_sink_valid[0:0] + attribute \src "build/ls180/gateware/ls180.v:1158.5-1158.42" + wire $0\libresocsim_datar_source_first[0:0] + attribute \src "build/ls180/gateware/ls180.v:4500.1-4601.4" + wire $0\libresocsim_datar_source_last[0:0] + attribute \src "build/ls180/gateware/ls180.v:4500.1-4601.4" + wire width 8 $0\libresocsim_datar_source_payload_data[7:0] + attribute \src "build/ls180/gateware/ls180.v:4500.1-4601.4" + wire width 3 $0\libresocsim_datar_source_payload_status[2:0] + attribute \src "build/ls180/gateware/ls180.v:4901.1-5091.4" + wire $0\libresocsim_datar_source_ready[0:0] + attribute \src "build/ls180/gateware/ls180.v:4500.1-4601.4" + wire $0\libresocsim_datar_source_valid[0:0] + attribute \src "build/ls180/gateware/ls180.v:4500.1-4601.4" + wire $0\libresocsim_datar_stop[0:0] + attribute \src "build/ls180/gateware/ls180.v:7055.1-9363.4" + wire width 32 $0\libresocsim_datar_timeout[31:0] + attribute \src "build/ls180/gateware/ls180.v:4500.1-4601.4" + wire width 32 $0\libresocsim_datar_timeout_sdphy_sdphydatar_next_value1[31:0] + attribute \src "build/ls180/gateware/ls180.v:4500.1-4601.4" + wire $0\libresocsim_datar_timeout_sdphy_sdphydatar_next_value_ce1[0:0] + attribute \src "build/ls180/gateware/ls180.v:7055.1-9363.4" + wire width 8 $0\libresocsim_dataw_count[7:0] + attribute \src "build/ls180/gateware/ls180.v:4394.1-4466.4" + wire width 8 $0\libresocsim_dataw_count_sdphy_fsm_next_value[7:0] + attribute \src "build/ls180/gateware/ls180.v:4394.1-4466.4" + wire $0\libresocsim_dataw_count_sdphy_fsm_next_value_ce[0:0] + attribute \src "build/ls180/gateware/ls180.v:7055.1-9363.4" + wire $0\libresocsim_dataw_crcr_buf_source_first[0:0] + attribute \src "build/ls180/gateware/ls180.v:7055.1-9363.4" + wire $0\libresocsim_dataw_crcr_buf_source_last[0:0] + attribute \src "build/ls180/gateware/ls180.v:7055.1-9363.4" + wire width 8 $0\libresocsim_dataw_crcr_buf_source_payload_data[7:0] + attribute \src "build/ls180/gateware/ls180.v:7055.1-9363.4" + wire $0\libresocsim_dataw_crcr_buf_source_valid[0:0] + attribute \src "build/ls180/gateware/ls180.v:7055.1-9363.4" + wire width 3 $0\libresocsim_dataw_crcr_converter_demux[2:0] + attribute \src "build/ls180/gateware/ls180.v:1107.5-1107.55" + wire $0\libresocsim_dataw_crcr_converter_sink_first[0:0] + attribute \src "build/ls180/gateware/ls180.v:1108.5-1108.54" + wire $0\libresocsim_dataw_crcr_converter_sink_last[0:0] + attribute \src "build/ls180/gateware/ls180.v:7055.1-9363.4" + wire $0\libresocsim_dataw_crcr_converter_source_first[0:0] + attribute \src "build/ls180/gateware/ls180.v:7055.1-9363.4" + wire $0\libresocsim_dataw_crcr_converter_source_last[0:0] + attribute \src "build/ls180/gateware/ls180.v:7055.1-9363.4" + wire width 8 $0\libresocsim_dataw_crcr_converter_source_payload_data[7:0] + attribute \src "build/ls180/gateware/ls180.v:7055.1-9363.4" + wire width 4 $0\libresocsim_dataw_crcr_converter_source_payload_valid_token_count[3:0] + attribute \src "build/ls180/gateware/ls180.v:7055.1-9363.4" + wire $0\libresocsim_dataw_crcr_converter_strobe_all[0:0] + attribute \src "build/ls180/gateware/ls180.v:1088.5-1088.48" + wire $0\libresocsim_dataw_crcr_pads_in_ready[0:0] + attribute \src "build/ls180/gateware/ls180.v:7055.1-9363.4" + wire $0\libresocsim_dataw_crcr_reset[0:0] + attribute \src "build/ls180/gateware/ls180.v:4366.1-4393.4" + wire $0\libresocsim_dataw_crcr_reset_sdphy_sdphycrcr_next_value[0:0] + attribute \src "build/ls180/gateware/ls180.v:4366.1-4393.4" + wire $0\libresocsim_dataw_crcr_reset_sdphy_sdphycrcr_next_value_ce[0:0] + attribute \src "build/ls180/gateware/ls180.v:7055.1-9363.4" + wire $0\libresocsim_dataw_crcr_run[0:0] + attribute \src "build/ls180/gateware/ls180.v:4366.1-4393.4" + wire $0\libresocsim_dataw_crcr_source_source_ready0[0:0] + attribute \src "build/ls180/gateware/ls180.v:4366.1-4393.4" + wire $0\libresocsim_dataw_error[0:0] + attribute \src "build/ls180/gateware/ls180.v:1075.5-1075.51" + wire $0\libresocsim_dataw_pads_in_pads_in_first[0:0] + attribute \src "build/ls180/gateware/ls180.v:1076.5-1076.50" + wire $0\libresocsim_dataw_pads_in_pads_in_last[0:0] + attribute \src "build/ls180/gateware/ls180.v:1077.5-1077.57" + wire $0\libresocsim_dataw_pads_in_pads_in_payload_clk[0:0] + attribute \src "build/ls180/gateware/ls180.v:1078.5-1078.59" + wire $0\libresocsim_dataw_pads_in_pads_in_payload_cmd_i[0:0] + attribute \src "build/ls180/gateware/ls180.v:1079.5-1079.59" + wire $0\libresocsim_dataw_pads_in_pads_in_payload_cmd_o[0:0] + attribute \src "build/ls180/gateware/ls180.v:1080.5-1080.60" + wire $0\libresocsim_dataw_pads_in_pads_in_payload_cmd_oe[0:0] + attribute \src "build/ls180/gateware/ls180.v:1081.11-1081.66" + wire width 4 $0\libresocsim_dataw_pads_in_pads_in_payload_data_i[3:0] + attribute \src "build/ls180/gateware/ls180.v:1082.11-1082.66" + wire width 4 $0\libresocsim_dataw_pads_in_pads_in_payload_data_o[3:0] + attribute \src "build/ls180/gateware/ls180.v:1083.5-1083.61" + wire $0\libresocsim_dataw_pads_in_pads_in_payload_data_oe[0:0] + attribute \src "build/ls180/gateware/ls180.v:1073.5-1073.51" + wire $0\libresocsim_dataw_pads_in_pads_in_valid[0:0] + attribute \src "build/ls180/gateware/ls180.v:4394.1-4466.4" + wire $0\libresocsim_dataw_pads_out_payload_clk[0:0] + attribute \src "build/ls180/gateware/ls180.v:1062.5-1062.52" + wire $0\libresocsim_dataw_pads_out_payload_cmd_o[0:0] + attribute \src "build/ls180/gateware/ls180.v:1063.5-1063.53" + wire $0\libresocsim_dataw_pads_out_payload_cmd_oe[0:0] + attribute \src "build/ls180/gateware/ls180.v:4394.1-4466.4" + wire width 4 $0\libresocsim_dataw_pads_out_payload_data_o[3:0] + attribute \src "build/ls180/gateware/ls180.v:4394.1-4466.4" + wire $0\libresocsim_dataw_pads_out_payload_data_oe[0:0] + attribute \src "build/ls180/gateware/ls180.v:4901.1-5091.4" + wire $0\libresocsim_dataw_sink_first[0:0] + attribute \src "build/ls180/gateware/ls180.v:4901.1-5091.4" + wire $0\libresocsim_dataw_sink_last[0:0] + attribute \src "build/ls180/gateware/ls180.v:4901.1-5091.4" + wire width 8 $0\libresocsim_dataw_sink_payload_data[7:0] + attribute \src "build/ls180/gateware/ls180.v:4394.1-4466.4" + wire $0\libresocsim_dataw_sink_ready[0:0] + attribute \src "build/ls180/gateware/ls180.v:4901.1-5091.4" + wire $0\libresocsim_dataw_sink_valid[0:0] + attribute \src "build/ls180/gateware/ls180.v:4394.1-4466.4" + wire $0\libresocsim_dataw_start[0:0] + attribute \src "build/ls180/gateware/ls180.v:4394.1-4466.4" + wire $0\libresocsim_dataw_stop[0:0] + attribute \src "build/ls180/gateware/ls180.v:4366.1-4393.4" + wire $0\libresocsim_dataw_valid[0:0] + attribute \src "build/ls180/gateware/ls180.v:5352.1-5400.4" + wire $0\libresocsim_done0[0:0] + attribute \src "build/ls180/gateware/ls180.v:7055.1-9363.4" + wire width 8 $0\libresocsim_init_count[7:0] + attribute \src "build/ls180/gateware/ls180.v:4095.1-4128.4" + wire width 8 $0\libresocsim_init_count_sdphy_sdphyinit_next_value[7:0] + attribute \src "build/ls180/gateware/ls180.v:4095.1-4128.4" + wire $0\libresocsim_init_count_sdphy_sdphyinit_next_value_ce[0:0] + attribute \src "build/ls180/gateware/ls180.v:955.5-955.41" + wire $0\libresocsim_init_initialize_w[0:0] + attribute \src "build/ls180/gateware/ls180.v:4095.1-4128.4" + wire $0\libresocsim_init_pads_out_payload_clk[0:0] + attribute \src "build/ls180/gateware/ls180.v:4095.1-4128.4" + wire $0\libresocsim_init_pads_out_payload_cmd_o[0:0] + attribute \src "build/ls180/gateware/ls180.v:4095.1-4128.4" + wire $0\libresocsim_init_pads_out_payload_cmd_oe[0:0] + attribute \src "build/ls180/gateware/ls180.v:4095.1-4128.4" + wire width 4 $0\libresocsim_init_pads_out_payload_data_o[3:0] + attribute \src "build/ls180/gateware/ls180.v:4095.1-4128.4" + wire $0\libresocsim_init_pads_out_payload_data_oe[0:0] + attribute \src "build/ls180/gateware/ls180.v:1404.11-1404.48" + wire width 2 $0\libresocsim_interface0_bus_bte[1:0] + attribute \src "build/ls180/gateware/ls180.v:1403.11-1403.48" + wire width 3 $0\libresocsim_interface0_bus_cti[2:0] + attribute \src "build/ls180/gateware/ls180.v:5211.1-5248.4" + wire width 32 $0\libresocsim_interface1_bus_adr[31:0] + attribute \src "build/ls180/gateware/ls180.v:1495.11-1495.48" + wire width 2 $0\libresocsim_interface1_bus_bte[1:0] + attribute \src "build/ls180/gateware/ls180.v:1494.11-1494.48" + wire width 3 $0\libresocsim_interface1_bus_cti[2:0] + attribute \src "build/ls180/gateware/ls180.v:5211.1-5248.4" + wire $0\libresocsim_interface1_bus_cyc[0:0] + attribute \src "build/ls180/gateware/ls180.v:1487.12-1487.52" + wire width 32 $0\libresocsim_interface1_bus_dat_w[31:0] + attribute \src "build/ls180/gateware/ls180.v:5211.1-5248.4" + wire width 4 $0\libresocsim_interface1_bus_sel[3:0] + attribute \src "build/ls180/gateware/ls180.v:5211.1-5248.4" + wire $0\libresocsim_interface1_bus_stb[0:0] + attribute \src "build/ls180/gateware/ls180.v:5211.1-5248.4" + wire $0\libresocsim_interface1_bus_we[0:0] + attribute \src "build/ls180/gateware/ls180.v:5352.1-5400.4" + wire $0\libresocsim_irq[0:0] + attribute \src "build/ls180/gateware/ls180.v:7055.1-9363.4" + wire $0\libresocsim_loopback_re[0:0] + attribute \src "build/ls180/gateware/ls180.v:7055.1-9363.4" + wire $0\libresocsim_loopback_storage[0:0] + attribute \src "build/ls180/gateware/ls180.v:7055.1-9363.4" + wire width 8 $0\libresocsim_miso[7:0] + attribute \src "build/ls180/gateware/ls180.v:7055.1-9363.4" + wire width 8 $0\libresocsim_miso_data[7:0] + attribute \src "build/ls180/gateware/ls180.v:5352.1-5400.4" + wire $0\libresocsim_miso_latch[0:0] + attribute \src "build/ls180/gateware/ls180.v:7055.1-9363.4" + wire width 8 $0\libresocsim_mosi_data[7:0] + attribute \src "build/ls180/gateware/ls180.v:5352.1-5400.4" + wire $0\libresocsim_mosi_latch[0:0] + attribute \src "build/ls180/gateware/ls180.v:7055.1-9363.4" + wire $0\libresocsim_mosi_re[0:0] + attribute \src "build/ls180/gateware/ls180.v:7055.1-9363.4" + wire width 3 $0\libresocsim_mosi_sel[2:0] + attribute \src "build/ls180/gateware/ls180.v:7055.1-9363.4" + wire width 8 $0\libresocsim_mosi_storage[7:0] + attribute \src "build/ls180/gateware/ls180.v:7055.1-9363.4" + wire $0\libresocsim_re[0:0] + attribute \src "build/ls180/gateware/ls180.v:7055.1-9363.4" + wire width 2 $0\libresocsim_sdblock2mem_converter_demux[1:0] + attribute \src "build/ls180/gateware/ls180.v:7055.1-9363.4" + wire $0\libresocsim_sdblock2mem_converter_source_first[0:0] + attribute \src "build/ls180/gateware/ls180.v:7055.1-9363.4" + wire $0\libresocsim_sdblock2mem_converter_source_last[0:0] + attribute \src "build/ls180/gateware/ls180.v:7055.1-9363.4" + wire width 32 $0\libresocsim_sdblock2mem_converter_source_payload_data[31:0] + attribute \src "build/ls180/gateware/ls180.v:7055.1-9363.4" + wire width 3 $0\libresocsim_sdblock2mem_converter_source_payload_valid_token_count[2:0] + attribute \src "build/ls180/gateware/ls180.v:7055.1-9363.4" + wire $0\libresocsim_sdblock2mem_converter_strobe_all[0:0] + attribute \src "build/ls180/gateware/ls180.v:7055.1-9363.4" + wire width 5 $0\libresocsim_sdblock2mem_fifo_consume[4:0] + attribute \src "build/ls180/gateware/ls180.v:7055.1-9363.4" + wire width 6 $0\libresocsim_sdblock2mem_fifo_level[5:0] + attribute \src "build/ls180/gateware/ls180.v:7055.1-9363.4" + wire width 5 $0\libresocsim_sdblock2mem_fifo_produce[4:0] + attribute \src "build/ls180/gateware/ls180.v:1428.5-1428.48" + wire $0\libresocsim_sdblock2mem_fifo_replace[0:0] + attribute \src "build/ls180/gateware/ls180.v:5119.1-5126.4" + wire width 5 $0\libresocsim_sdblock2mem_fifo_wrport_adr[4:0] + attribute \src "build/ls180/gateware/ls180.v:5152.1-5191.4" + wire width 32 $0\libresocsim_sdblock2mem_sink_sink_payload_address[31:0] + attribute \src "build/ls180/gateware/ls180.v:5152.1-5191.4" + wire width 32 $0\libresocsim_sdblock2mem_sink_sink_payload_data1[31:0] + attribute \src "build/ls180/gateware/ls180.v:5152.1-5191.4" + wire $0\libresocsim_sdblock2mem_sink_sink_valid1[0:0] + attribute \src "build/ls180/gateware/ls180.v:7055.1-9363.4" + wire $0\libresocsim_sdblock2mem_wishbonedmawriter_base_re[0:0] + attribute \src "build/ls180/gateware/ls180.v:7055.1-9363.4" + wire width 64 $0\libresocsim_sdblock2mem_wishbonedmawriter_base_storage[63:0] + attribute \src "build/ls180/gateware/ls180.v:7055.1-9363.4" + wire $0\libresocsim_sdblock2mem_wishbonedmawriter_enable_re[0:0] + attribute \src "build/ls180/gateware/ls180.v:7055.1-9363.4" + wire $0\libresocsim_sdblock2mem_wishbonedmawriter_enable_storage[0:0] + attribute \src "build/ls180/gateware/ls180.v:7055.1-9363.4" + wire $0\libresocsim_sdblock2mem_wishbonedmawriter_length_re[0:0] + attribute \src "build/ls180/gateware/ls180.v:7055.1-9363.4" + wire width 32 $0\libresocsim_sdblock2mem_wishbonedmawriter_length_storage[31:0] + attribute \src "build/ls180/gateware/ls180.v:7055.1-9363.4" + wire $0\libresocsim_sdblock2mem_wishbonedmawriter_loop_re[0:0] + attribute \src "build/ls180/gateware/ls180.v:7055.1-9363.4" + wire $0\libresocsim_sdblock2mem_wishbonedmawriter_loop_storage[0:0] + attribute \src "build/ls180/gateware/ls180.v:7055.1-9363.4" + wire width 32 $0\libresocsim_sdblock2mem_wishbonedmawriter_offset[31:0] + attribute \src "build/ls180/gateware/ls180.v:5152.1-5191.4" + wire width 32 $0\libresocsim_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value[31:0] + attribute \src "build/ls180/gateware/ls180.v:5152.1-5191.4" + wire $0\libresocsim_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value_ce[0:0] + attribute \src "build/ls180/gateware/ls180.v:5152.1-5191.4" + wire $0\libresocsim_sdblock2mem_wishbonedmawriter_sink_ready[0:0] + attribute \src "build/ls180/gateware/ls180.v:5152.1-5191.4" + wire $0\libresocsim_sdblock2mem_wishbonedmawriter_status[0:0] + attribute \src "build/ls180/gateware/ls180.v:7055.1-9363.4" + wire $0\libresocsim_sdcore_block_count_re[0:0] + attribute \src "build/ls180/gateware/ls180.v:7055.1-9363.4" + wire width 32 $0\libresocsim_sdcore_block_count_storage[31:0] + attribute \src "build/ls180/gateware/ls180.v:7055.1-9363.4" + wire $0\libresocsim_sdcore_block_length_re[0:0] + attribute \src "build/ls180/gateware/ls180.v:7055.1-9363.4" + wire width 10 $0\libresocsim_sdcore_block_length_storage[9:0] + attribute \src "build/ls180/gateware/ls180.v:7055.1-9363.4" + wire $0\libresocsim_sdcore_cmd_argument_re[0:0] + attribute \src "build/ls180/gateware/ls180.v:7055.1-9363.4" + wire width 32 $0\libresocsim_sdcore_cmd_argument_storage[31:0] + attribute \src "build/ls180/gateware/ls180.v:7055.1-9363.4" + wire $0\libresocsim_sdcore_cmd_command_re[0:0] + attribute \src "build/ls180/gateware/ls180.v:7055.1-9363.4" + wire width 32 $0\libresocsim_sdcore_cmd_command_storage[31:0] + attribute \src "build/ls180/gateware/ls180.v:7055.1-9363.4" + wire width 3 $0\libresocsim_sdcore_cmd_count[2:0] + attribute \src "build/ls180/gateware/ls180.v:4901.1-5091.4" + wire width 3 $0\libresocsim_sdcore_cmd_count_sdcore_fsm_next_value2[2:0] + attribute \src "build/ls180/gateware/ls180.v:4901.1-5091.4" + wire $0\libresocsim_sdcore_cmd_count_sdcore_fsm_next_value_ce2[0:0] + attribute \src "build/ls180/gateware/ls180.v:7055.1-9363.4" + wire $0\libresocsim_sdcore_cmd_done[0:0] + attribute \src "build/ls180/gateware/ls180.v:4901.1-5091.4" + wire $0\libresocsim_sdcore_cmd_done_sdcore_fsm_next_value0[0:0] + attribute \src "build/ls180/gateware/ls180.v:4901.1-5091.4" + wire $0\libresocsim_sdcore_cmd_done_sdcore_fsm_next_value_ce0[0:0] + attribute \src "build/ls180/gateware/ls180.v:7055.1-9363.4" + wire $0\libresocsim_sdcore_cmd_error[0:0] + attribute \src "build/ls180/gateware/ls180.v:4901.1-5091.4" + wire $0\libresocsim_sdcore_cmd_error_sdcore_fsm_next_value4[0:0] + attribute \src "build/ls180/gateware/ls180.v:4901.1-5091.4" + wire $0\libresocsim_sdcore_cmd_error_sdcore_fsm_next_value_ce4[0:0] + attribute \src "build/ls180/gateware/ls180.v:7055.1-9363.4" + wire width 128 $0\libresocsim_sdcore_cmd_response_status[127:0] + attribute \src "build/ls180/gateware/ls180.v:4901.1-5091.4" + wire width 128 $0\libresocsim_sdcore_cmd_response_status_sdcore_fsm_next_value8[127:0] + attribute \src "build/ls180/gateware/ls180.v:4901.1-5091.4" + wire $0\libresocsim_sdcore_cmd_response_status_sdcore_fsm_next_value_ce8[0:0] + attribute \src "build/ls180/gateware/ls180.v:1237.5-1237.41" + wire $0\libresocsim_sdcore_cmd_send_w[0:0] + attribute \src "build/ls180/gateware/ls180.v:7055.1-9363.4" + wire $0\libresocsim_sdcore_cmd_timeout[0:0] + attribute \src "build/ls180/gateware/ls180.v:4901.1-5091.4" + wire $0\libresocsim_sdcore_cmd_timeout_sdcore_fsm_next_value5[0:0] + attribute \src "build/ls180/gateware/ls180.v:4901.1-5091.4" + wire $0\libresocsim_sdcore_cmd_timeout_sdcore_fsm_next_value_ce5[0:0] + attribute \src "build/ls180/gateware/ls180.v:7055.1-9363.4" + wire width 4 $0\libresocsim_sdcore_crc16_checker_cnt[3:0] + attribute \src "build/ls180/gateware/ls180.v:4807.1-4814.4" + wire $0\libresocsim_sdcore_crc16_checker_crc0_clr[0:0] + attribute \src "build/ls180/gateware/ls180.v:4863.1-4870.4" + wire width 16 $0\libresocsim_sdcore_crc16_checker_crc0_crc[15:0] + attribute \src "build/ls180/gateware/ls180.v:7055.1-9363.4" + wire width 16 $0\libresocsim_sdcore_crc16_checker_crc0_crcreg0[15:0] + attribute \src "build/ls180/gateware/ls180.v:4817.1-4824.4" + wire $0\libresocsim_sdcore_crc16_checker_crc1_clr[0:0] + attribute \src "build/ls180/gateware/ls180.v:4873.1-4880.4" + wire width 16 $0\libresocsim_sdcore_crc16_checker_crc1_crc[15:0] + attribute \src "build/ls180/gateware/ls180.v:7055.1-9363.4" + wire width 16 $0\libresocsim_sdcore_crc16_checker_crc1_crcreg0[15:0] + attribute \src "build/ls180/gateware/ls180.v:4827.1-4834.4" + wire $0\libresocsim_sdcore_crc16_checker_crc2_clr[0:0] + attribute \src "build/ls180/gateware/ls180.v:4883.1-4890.4" + wire width 16 $0\libresocsim_sdcore_crc16_checker_crc2_crc[15:0] + attribute \src "build/ls180/gateware/ls180.v:7055.1-9363.4" + wire width 16 $0\libresocsim_sdcore_crc16_checker_crc2_crcreg0[15:0] + attribute \src "build/ls180/gateware/ls180.v:4837.1-4844.4" + wire $0\libresocsim_sdcore_crc16_checker_crc3_clr[0:0] + attribute \src "build/ls180/gateware/ls180.v:4893.1-4900.4" + wire width 16 $0\libresocsim_sdcore_crc16_checker_crc3_crc[15:0] + attribute \src "build/ls180/gateware/ls180.v:7055.1-9363.4" + wire width 16 $0\libresocsim_sdcore_crc16_checker_crc3_crcreg0[15:0] + attribute \src "build/ls180/gateware/ls180.v:7055.1-9363.4" + wire width 16 $0\libresocsim_sdcore_crc16_checker_crctmp0[15:0] + attribute \src "build/ls180/gateware/ls180.v:7055.1-9363.4" + wire width 16 $0\libresocsim_sdcore_crc16_checker_crctmp1[15:0] + attribute \src "build/ls180/gateware/ls180.v:7055.1-9363.4" + wire width 16 $0\libresocsim_sdcore_crc16_checker_crctmp2[15:0] + attribute \src "build/ls180/gateware/ls180.v:7055.1-9363.4" + wire width 16 $0\libresocsim_sdcore_crc16_checker_crctmp3[15:0] + attribute \src "build/ls180/gateware/ls180.v:7055.1-9363.4" + wire width 16 $0\libresocsim_sdcore_crc16_checker_fifo0[15:0] + attribute \src "build/ls180/gateware/ls180.v:7055.1-9363.4" + wire width 16 $0\libresocsim_sdcore_crc16_checker_fifo1[15:0] + attribute \src "build/ls180/gateware/ls180.v:7055.1-9363.4" + wire width 16 $0\libresocsim_sdcore_crc16_checker_fifo2[15:0] + attribute \src "build/ls180/gateware/ls180.v:7055.1-9363.4" + wire width 16 $0\libresocsim_sdcore_crc16_checker_fifo3[15:0] + attribute \src "build/ls180/gateware/ls180.v:4901.1-5091.4" + wire $0\libresocsim_sdcore_crc16_checker_sink_first[0:0] + attribute \src "build/ls180/gateware/ls180.v:4901.1-5091.4" + wire $0\libresocsim_sdcore_crc16_checker_sink_last[0:0] + attribute \src "build/ls180/gateware/ls180.v:4901.1-5091.4" + wire width 8 $0\libresocsim_sdcore_crc16_checker_sink_payload_data[7:0] + attribute \src "build/ls180/gateware/ls180.v:4852.1-4859.4" + wire $0\libresocsim_sdcore_crc16_checker_sink_ready[0:0] + attribute \src "build/ls180/gateware/ls180.v:4901.1-5091.4" + wire $0\libresocsim_sdcore_crc16_checker_sink_valid[0:0] + attribute \src "build/ls180/gateware/ls180.v:1343.5-1343.57" + wire $0\libresocsim_sdcore_crc16_checker_source_first[0:0] + attribute \src "build/ls180/gateware/ls180.v:4846.1-4851.4" + wire $0\libresocsim_sdcore_crc16_checker_source_valid[0:0] + attribute \src "build/ls180/gateware/ls180.v:7055.1-9363.4" + wire width 8 $0\libresocsim_sdcore_crc16_checker_val[7:0] + attribute \src "build/ls180/gateware/ls180.v:4799.1-4804.4" + wire $0\libresocsim_sdcore_crc16_checker_valid[0:0] + attribute \src "build/ls180/gateware/ls180.v:7055.1-9363.4" + wire width 3 $0\libresocsim_sdcore_crc16_inserter_cnt[2:0] + attribute \src "build/ls180/gateware/ls180.v:4719.1-4798.4" + wire width 3 $0\libresocsim_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value4[2:0] + attribute \src "build/ls180/gateware/ls180.v:4719.1-4798.4" + wire $0\libresocsim_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value_ce4[0:0] + attribute \src "build/ls180/gateware/ls180.v:4681.1-4688.4" + wire width 16 $0\libresocsim_sdcore_crc16_inserter_crc0_crc[15:0] + attribute \src "build/ls180/gateware/ls180.v:7055.1-9363.4" + wire width 16 $0\libresocsim_sdcore_crc16_inserter_crc0_crcreg0[15:0] + attribute \src "build/ls180/gateware/ls180.v:4691.1-4698.4" + wire width 16 $0\libresocsim_sdcore_crc16_inserter_crc1_crc[15:0] + attribute \src "build/ls180/gateware/ls180.v:7055.1-9363.4" + wire width 16 $0\libresocsim_sdcore_crc16_inserter_crc1_crcreg0[15:0] + attribute \src "build/ls180/gateware/ls180.v:4701.1-4708.4" + wire width 16 $0\libresocsim_sdcore_crc16_inserter_crc2_crc[15:0] + attribute \src "build/ls180/gateware/ls180.v:7055.1-9363.4" + wire width 16 $0\libresocsim_sdcore_crc16_inserter_crc2_crcreg0[15:0] + attribute \src "build/ls180/gateware/ls180.v:4711.1-4718.4" + wire width 16 $0\libresocsim_sdcore_crc16_inserter_crc3_crc[15:0] + attribute \src "build/ls180/gateware/ls180.v:7055.1-9363.4" + wire width 16 $0\libresocsim_sdcore_crc16_inserter_crc3_crcreg0[15:0] + attribute \src "build/ls180/gateware/ls180.v:7055.1-9363.4" + wire width 16 $0\libresocsim_sdcore_crc16_inserter_crctmp0[15:0] + attribute \src "build/ls180/gateware/ls180.v:4719.1-4798.4" + wire width 16 $0\libresocsim_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value0[15:0] + attribute \src "build/ls180/gateware/ls180.v:4719.1-4798.4" + wire $0\libresocsim_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value_ce0[0:0] + attribute \src "build/ls180/gateware/ls180.v:7055.1-9363.4" + wire width 16 $0\libresocsim_sdcore_crc16_inserter_crctmp1[15:0] + attribute \src "build/ls180/gateware/ls180.v:4719.1-4798.4" + wire width 16 $0\libresocsim_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value1[15:0] + attribute \src "build/ls180/gateware/ls180.v:4719.1-4798.4" + wire $0\libresocsim_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value_ce1[0:0] + attribute \src "build/ls180/gateware/ls180.v:7055.1-9363.4" + wire width 16 $0\libresocsim_sdcore_crc16_inserter_crctmp2[15:0] + attribute \src "build/ls180/gateware/ls180.v:4719.1-4798.4" + wire width 16 $0\libresocsim_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value2[15:0] + attribute \src "build/ls180/gateware/ls180.v:4719.1-4798.4" + wire $0\libresocsim_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value_ce2[0:0] + attribute \src "build/ls180/gateware/ls180.v:7055.1-9363.4" + wire width 16 $0\libresocsim_sdcore_crc16_inserter_crctmp3[15:0] + attribute \src "build/ls180/gateware/ls180.v:4719.1-4798.4" + wire width 16 $0\libresocsim_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value3[15:0] + attribute \src "build/ls180/gateware/ls180.v:4719.1-4798.4" + wire $0\libresocsim_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value_ce3[0:0] + attribute \src "build/ls180/gateware/ls180.v:4719.1-4798.4" + wire $0\libresocsim_sdcore_crc16_inserter_sink_ready[0:0] + attribute \src "build/ls180/gateware/ls180.v:1300.5-1300.58" + wire $0\libresocsim_sdcore_crc16_inserter_source_first[0:0] + attribute \src "build/ls180/gateware/ls180.v:4719.1-4798.4" + wire $0\libresocsim_sdcore_crc16_inserter_source_last[0:0] + attribute \src "build/ls180/gateware/ls180.v:4719.1-4798.4" + wire width 8 $0\libresocsim_sdcore_crc16_inserter_source_payload_data[7:0] + attribute \src "build/ls180/gateware/ls180.v:4901.1-5091.4" + wire $0\libresocsim_sdcore_crc16_inserter_source_ready[0:0] + attribute \src "build/ls180/gateware/ls180.v:4719.1-4798.4" + wire $0\libresocsim_sdcore_crc16_inserter_source_valid[0:0] + attribute \src "build/ls180/gateware/ls180.v:4659.1-4666.4" + wire width 7 $0\libresocsim_sdcore_crc7_inserter_crc[6:0] + attribute \src "build/ls180/gateware/ls180.v:7055.1-9363.4" + wire width 7 $0\libresocsim_sdcore_crc7_inserter_crcreg0[6:0] + attribute \src "build/ls180/gateware/ls180.v:7055.1-9363.4" + wire width 32 $0\libresocsim_sdcore_data_count[31:0] + attribute \src "build/ls180/gateware/ls180.v:4901.1-5091.4" + wire width 32 $0\libresocsim_sdcore_data_count_sdcore_fsm_next_value3[31:0] + attribute \src "build/ls180/gateware/ls180.v:4901.1-5091.4" + wire $0\libresocsim_sdcore_data_count_sdcore_fsm_next_value_ce3[0:0] + attribute \src "build/ls180/gateware/ls180.v:7055.1-9363.4" + wire $0\libresocsim_sdcore_data_done[0:0] + attribute \src "build/ls180/gateware/ls180.v:4901.1-5091.4" + wire $0\libresocsim_sdcore_data_done_sdcore_fsm_next_value1[0:0] + attribute \src "build/ls180/gateware/ls180.v:4901.1-5091.4" + wire $0\libresocsim_sdcore_data_done_sdcore_fsm_next_value_ce1[0:0] + attribute \src "build/ls180/gateware/ls180.v:7055.1-9363.4" + wire $0\libresocsim_sdcore_data_error[0:0] + attribute \src "build/ls180/gateware/ls180.v:4901.1-5091.4" + wire $0\libresocsim_sdcore_data_error_sdcore_fsm_next_value6[0:0] + attribute \src "build/ls180/gateware/ls180.v:4901.1-5091.4" + wire $0\libresocsim_sdcore_data_error_sdcore_fsm_next_value_ce6[0:0] + attribute \src "build/ls180/gateware/ls180.v:7055.1-9363.4" + wire $0\libresocsim_sdcore_data_timeout[0:0] + attribute \src "build/ls180/gateware/ls180.v:4901.1-5091.4" + wire $0\libresocsim_sdcore_data_timeout_sdcore_fsm_next_value7[0:0] + attribute \src "build/ls180/gateware/ls180.v:4901.1-5091.4" + wire $0\libresocsim_sdcore_data_timeout_sdcore_fsm_next_value_ce7[0:0] + attribute \src "build/ls180/gateware/ls180.v:7055.1-9363.4" + wire width 2 $0\libresocsim_sdmem2block_converter_mux[1:0] + attribute \src "build/ls180/gateware/ls180.v:5297.1-5313.4" + wire width 8 $0\libresocsim_sdmem2block_converter_source_payload_data[7:0] + attribute \src "build/ls180/gateware/ls180.v:7055.1-9363.4" + wire $0\libresocsim_sdmem2block_dma_base_re[0:0] + attribute \src "build/ls180/gateware/ls180.v:7055.1-9363.4" + wire width 64 $0\libresocsim_sdmem2block_dma_base_storage[63:0] + attribute \src "build/ls180/gateware/ls180.v:7055.1-9363.4" + wire width 32 $0\libresocsim_sdmem2block_dma_data[31:0] + attribute \src "build/ls180/gateware/ls180.v:5211.1-5248.4" + wire width 32 $0\libresocsim_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value[31:0] + attribute \src "build/ls180/gateware/ls180.v:5211.1-5248.4" + wire $0\libresocsim_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value_ce[0:0] + attribute \src "build/ls180/gateware/ls180.v:5249.1-5285.4" + wire $0\libresocsim_sdmem2block_dma_done_status[0:0] + attribute \src "build/ls180/gateware/ls180.v:7055.1-9363.4" + wire $0\libresocsim_sdmem2block_dma_enable_re[0:0] + attribute \src "build/ls180/gateware/ls180.v:7055.1-9363.4" + wire $0\libresocsim_sdmem2block_dma_enable_storage[0:0] + attribute \src "build/ls180/gateware/ls180.v:7055.1-9363.4" + wire $0\libresocsim_sdmem2block_dma_length_re[0:0] + attribute \src "build/ls180/gateware/ls180.v:7055.1-9363.4" + wire width 32 $0\libresocsim_sdmem2block_dma_length_storage[31:0] + attribute \src "build/ls180/gateware/ls180.v:7055.1-9363.4" + wire $0\libresocsim_sdmem2block_dma_loop_re[0:0] + attribute \src "build/ls180/gateware/ls180.v:7055.1-9363.4" + wire $0\libresocsim_sdmem2block_dma_loop_storage[0:0] + attribute \src "build/ls180/gateware/ls180.v:7055.1-9363.4" + wire width 32 $0\libresocsim_sdmem2block_dma_offset[31:0] + attribute \src "build/ls180/gateware/ls180.v:5249.1-5285.4" + wire width 32 $0\libresocsim_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value[31:0] + attribute \src "build/ls180/gateware/ls180.v:5249.1-5285.4" + wire $0\libresocsim_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value_ce[0:0] + attribute \src "build/ls180/gateware/ls180.v:5249.1-5285.4" + wire $0\libresocsim_sdmem2block_dma_sink_last[0:0] + attribute \src "build/ls180/gateware/ls180.v:5249.1-5285.4" + wire width 32 $0\libresocsim_sdmem2block_dma_sink_payload_address[31:0] + attribute \src "build/ls180/gateware/ls180.v:5211.1-5248.4" + wire $0\libresocsim_sdmem2block_dma_sink_ready[0:0] + attribute \src "build/ls180/gateware/ls180.v:5249.1-5285.4" + wire $0\libresocsim_sdmem2block_dma_sink_valid[0:0] + attribute \src "build/ls180/gateware/ls180.v:1508.5-1508.52" + wire $0\libresocsim_sdmem2block_dma_source_first[0:0] + attribute \src "build/ls180/gateware/ls180.v:5211.1-5248.4" + wire $0\libresocsim_sdmem2block_dma_source_last[0:0] + attribute \src "build/ls180/gateware/ls180.v:5211.1-5248.4" + wire width 32 $0\libresocsim_sdmem2block_dma_source_payload_data[31:0] + attribute \src "build/ls180/gateware/ls180.v:5211.1-5248.4" + wire $0\libresocsim_sdmem2block_dma_source_valid[0:0] + attribute \src "build/ls180/gateware/ls180.v:7055.1-9363.4" + wire width 5 $0\libresocsim_sdmem2block_fifo_consume[4:0] + attribute \src "build/ls180/gateware/ls180.v:7055.1-9363.4" + wire width 6 $0\libresocsim_sdmem2block_fifo_level[5:0] + attribute \src "build/ls180/gateware/ls180.v:7055.1-9363.4" + wire width 5 $0\libresocsim_sdmem2block_fifo_produce[4:0] + attribute \src "build/ls180/gateware/ls180.v:1564.5-1564.48" + wire $0\libresocsim_sdmem2block_fifo_replace[0:0] + attribute \src "build/ls180/gateware/ls180.v:5327.1-5334.4" + wire width 5 $0\libresocsim_sdmem2block_fifo_wrport_adr[4:0] + attribute \src "build/ls180/gateware/ls180.v:6968.1-7053.4" + wire $0\libresocsim_sdpads_cmd_i[0:0] + attribute \src "build/ls180/gateware/ls180.v:6968.1-7053.4" + wire width 4 $0\libresocsim_sdpads_data_i[3:0] + attribute \src "build/ls180/gateware/ls180.v:5978.1-5983.4" + wire $0\libresocsim_start1[0:0] + attribute \src "build/ls180/gateware/ls180.v:7055.1-9363.4" + wire width 16 $0\libresocsim_storage[15:0] + attribute \src "build/ls180/gateware/ls180.v:914.12-914.37" + wire width 16 $0\main_clk_divider0[15:0] + attribute \src "build/ls180/gateware/ls180.v:7055.1-9363.4" + wire width 16 $0\main_clk_divider1[15:0] + attribute \src "build/ls180/gateware/ls180.v:3989.1-4037.4" + wire $0\main_clk_enable[0:0] + attribute \src "build/ls180/gateware/ls180.v:7055.1-9363.4" + wire $0\main_cmd_consumed[0:0] + attribute \src "build/ls180/gateware/ls180.v:7055.1-9363.4" + wire $0\main_control_re[0:0] + attribute \src "build/ls180/gateware/ls180.v:7055.1-9363.4" + wire width 16 $0\main_control_storage[15:0] + attribute \src "build/ls180/gateware/ls180.v:7055.1-9363.4" + wire $0\main_converter_counter[0:0] + attribute \src "build/ls180/gateware/ls180.v:3919.1-3965.4" + wire $0\main_converter_counter_converter_next_value[0:0] + attribute \src "build/ls180/gateware/ls180.v:3919.1-3965.4" + wire $0\main_converter_counter_converter_next_value_ce[0:0] + attribute \src "build/ls180/gateware/ls180.v:7055.1-9363.4" + wire width 32 $0\main_converter_dat_r[31:0] + attribute \src "build/ls180/gateware/ls180.v:3919.1-3965.4" + wire $0\main_converter_skip[0:0] + attribute \src "build/ls180/gateware/ls180.v:7055.1-9363.4" + wire width 3 $0\main_count[2:0] + attribute \src "build/ls180/gateware/ls180.v:3989.1-4037.4" + wire width 3 $0\main_count_spimaster0_next_value[2:0] + attribute \src "build/ls180/gateware/ls180.v:3989.1-4037.4" + wire $0\main_count_spimaster0_next_value_ce[0:0] + attribute \src "build/ls180/gateware/ls180.v:3989.1-4037.4" + wire $0\main_cs_enable[0:0] + attribute \src "build/ls180/gateware/ls180.v:7055.1-9363.4" + wire $0\main_cs_re[0:0] + attribute \src "build/ls180/gateware/ls180.v:7055.1-9363.4" + wire $0\main_cs_storage[0:0] + attribute \src "build/ls180/gateware/ls180.v:6968.1-7053.4" + wire width 16 $0\main_dfi_p0_rddata[15:0] + attribute \src "build/ls180/gateware/ls180.v:7055.1-9363.4" + wire $0\main_dfi_p0_rddata_valid[0:0] + attribute \src "build/ls180/gateware/ls180.v:3989.1-4037.4" + wire $0\main_done0[0:0] + attribute \src "build/ls180/gateware/ls180.v:6964.1-6966.4" + wire $0\main_int_rst[0:0] + attribute \src "build/ls180/gateware/ls180.v:3989.1-4037.4" + wire $0\main_irq[0:0] + attribute \src "build/ls180/gateware/ls180.v:7055.1-9363.4" + wire $0\main_libresocsim_converter0_counter[0:0] + attribute \src "build/ls180/gateware/ls180.v:2606.1-2652.4" + wire $0\main_libresocsim_converter0_counter_converter0_next_value[0:0] + attribute \src "build/ls180/gateware/ls180.v:2606.1-2652.4" + wire $0\main_libresocsim_converter0_counter_converter0_next_value_ce[0:0] + attribute \src "build/ls180/gateware/ls180.v:7055.1-9363.4" + wire width 64 $0\main_libresocsim_converter0_dat_r[63:0] + attribute \src "build/ls180/gateware/ls180.v:2606.1-2652.4" + wire $0\main_libresocsim_converter0_skip[0:0] + attribute \src "build/ls180/gateware/ls180.v:7055.1-9363.4" + wire $0\main_libresocsim_converter1_counter[0:0] + attribute \src "build/ls180/gateware/ls180.v:2666.1-2712.4" + wire $0\main_libresocsim_converter1_counter_converter1_next_value[0:0] + attribute \src "build/ls180/gateware/ls180.v:2666.1-2712.4" + wire $0\main_libresocsim_converter1_counter_converter1_next_value_ce[0:0] + attribute \src "build/ls180/gateware/ls180.v:7055.1-9363.4" + wire width 64 $0\main_libresocsim_converter1_dat_r[63:0] + attribute \src "build/ls180/gateware/ls180.v:2666.1-2712.4" + wire $0\main_libresocsim_converter1_skip[0:0] + attribute \src "build/ls180/gateware/ls180.v:2606.1-2652.4" + wire width 30 $0\main_libresocsim_interface0_converted_interface_adr[29:0] + attribute \src "build/ls180/gateware/ls180.v:105.11-105.69" + wire width 2 $0\main_libresocsim_interface0_converted_interface_bte[1:0] + attribute \src "build/ls180/gateware/ls180.v:104.11-104.69" + wire width 3 $0\main_libresocsim_interface0_converted_interface_cti[2:0] + attribute \src "build/ls180/gateware/ls180.v:2606.1-2652.4" + wire $0\main_libresocsim_interface0_converted_interface_cyc[0:0] + attribute \src "build/ls180/gateware/ls180.v:2594.1-2604.4" + wire width 32 $0\main_libresocsim_interface0_converted_interface_dat_w[31:0] + attribute \src "build/ls180/gateware/ls180.v:2606.1-2652.4" + wire width 4 $0\main_libresocsim_interface0_converted_interface_sel[3:0] + attribute \src "build/ls180/gateware/ls180.v:2606.1-2652.4" + wire $0\main_libresocsim_interface0_converted_interface_stb[0:0] + attribute \src "build/ls180/gateware/ls180.v:2606.1-2652.4" + wire $0\main_libresocsim_interface0_converted_interface_we[0:0] + attribute \src "build/ls180/gateware/ls180.v:2666.1-2712.4" + wire width 30 $0\main_libresocsim_interface1_converted_interface_adr[29:0] + attribute \src "build/ls180/gateware/ls180.v:120.11-120.69" + wire width 2 $0\main_libresocsim_interface1_converted_interface_bte[1:0] + attribute \src "build/ls180/gateware/ls180.v:119.11-119.69" + wire width 3 $0\main_libresocsim_interface1_converted_interface_cti[2:0] + attribute \src "build/ls180/gateware/ls180.v:2666.1-2712.4" + wire $0\main_libresocsim_interface1_converted_interface_cyc[0:0] + attribute \src "build/ls180/gateware/ls180.v:2654.1-2664.4" + wire width 32 $0\main_libresocsim_interface1_converted_interface_dat_w[31:0] + attribute \src "build/ls180/gateware/ls180.v:2666.1-2712.4" + wire width 4 $0\main_libresocsim_interface1_converted_interface_sel[3:0] + attribute \src "build/ls180/gateware/ls180.v:2666.1-2712.4" + wire $0\main_libresocsim_interface1_converted_interface_stb[0:0] + attribute \src "build/ls180/gateware/ls180.v:2666.1-2712.4" + wire $0\main_libresocsim_interface1_converted_interface_we[0:0] + attribute \src "build/ls180/gateware/ls180.v:2666.1-2712.4" + wire $0\main_libresocsim_libresoc_dbus_ack[0:0] + attribute \src "build/ls180/gateware/ls180.v:54.5-54.46" + wire $0\main_libresocsim_libresoc_dbus_err[0:0] + attribute \src "build/ls180/gateware/ls180.v:88.11-88.52" + wire width 4 $0\main_libresocsim_libresoc_dmi_addr[3:0] + attribute \src "build/ls180/gateware/ls180.v:89.12-89.53" + wire width 64 $0\main_libresocsim_libresoc_dmi_din[63:0] + attribute \src "build/ls180/gateware/ls180.v:93.5-93.45" + wire $0\main_libresocsim_libresoc_dmi_req[0:0] + attribute \src "build/ls180/gateware/ls180.v:91.5-91.44" + wire $0\main_libresocsim_libresoc_dmi_wr[0:0] + attribute \src "build/ls180/gateware/ls180.v:2606.1-2652.4" + wire $0\main_libresocsim_libresoc_ibus_ack[0:0] + attribute \src "build/ls180/gateware/ls180.v:65.5-65.46" + wire $0\main_libresocsim_libresoc_ibus_err[0:0] + attribute \src "build/ls180/gateware/ls180.v:2587.1-2592.4" + wire width 16 $0\main_libresocsim_libresoc_interrupt[15:0] + attribute \src "build/ls180/gateware/ls180.v:72.5-72.50" + wire $0\main_libresocsim_libresoc_xics_icp_ack[0:0] + attribute \src "build/ls180/gateware/ls180.v:68.12-68.60" + wire width 32 $0\main_libresocsim_libresoc_xics_icp_dat_r[31:0] + attribute \src "build/ls180/gateware/ls180.v:76.5-76.50" + wire $0\main_libresocsim_libresoc_xics_icp_err[0:0] + attribute \src "build/ls180/gateware/ls180.v:83.5-83.50" + wire $0\main_libresocsim_libresoc_xics_ics_ack[0:0] + attribute \src "build/ls180/gateware/ls180.v:79.12-79.60" + wire width 32 $0\main_libresocsim_libresoc_xics_ics_dat_r[31:0] + attribute \src "build/ls180/gateware/ls180.v:87.5-87.50" + wire $0\main_libresocsim_libresoc_xics_ics_err[0:0] + attribute \src "build/ls180/gateware/ls180.v:7055.1-9363.4" + wire width 32 $0\main_libresocsim_phase_accumulator_rx[31:0] + attribute \src "build/ls180/gateware/ls180.v:7055.1-9363.4" + wire width 32 $0\main_libresocsim_phase_accumulator_tx[31:0] + attribute \src "build/ls180/gateware/ls180.v:7055.1-9363.4" + wire $0\main_libresocsim_ram_bus_ack[0:0] + attribute \src "build/ls180/gateware/ls180.v:136.5-136.40" + wire $0\main_libresocsim_ram_bus_err[0:0] + attribute \src "build/ls180/gateware/ls180.v:7055.1-9363.4" + wire $0\main_libresocsim_re[0:0] + attribute \src "build/ls180/gateware/ls180.v:7055.1-9363.4" + wire width 4 $0\main_libresocsim_rx_bitcount[3:0] + attribute \src "build/ls180/gateware/ls180.v:7055.1-9363.4" + wire $0\main_libresocsim_rx_busy[0:0] + attribute \src "build/ls180/gateware/ls180.v:7055.1-9363.4" + wire $0\main_libresocsim_rx_r[0:0] + attribute \src "build/ls180/gateware/ls180.v:7055.1-9363.4" + wire width 8 $0\main_libresocsim_rx_reg[7:0] + attribute \src "build/ls180/gateware/ls180.v:7055.1-9363.4" + wire $0\main_libresocsim_sink_ready[0:0] + attribute \src "build/ls180/gateware/ls180.v:7055.1-9363.4" + wire width 32 $0\main_libresocsim_soccontroller_bus_errors[31:0] + attribute \src "build/ls180/gateware/ls180.v:7055.1-9363.4" + wire $0\main_libresocsim_soccontroller_reset_re[0:0] + attribute \src "build/ls180/gateware/ls180.v:7055.1-9363.4" + wire $0\main_libresocsim_soccontroller_reset_storage[0:0] + attribute \src "build/ls180/gateware/ls180.v:7055.1-9363.4" + wire $0\main_libresocsim_soccontroller_scratch_re[0:0] + attribute \src "build/ls180/gateware/ls180.v:7055.1-9363.4" + wire width 32 $0\main_libresocsim_soccontroller_scratch_storage[31:0] + attribute \src "build/ls180/gateware/ls180.v:155.5-155.41" + wire $0\main_libresocsim_source_first[0:0] + attribute \src "build/ls180/gateware/ls180.v:156.5-156.40" + wire $0\main_libresocsim_source_last[0:0] + attribute \src "build/ls180/gateware/ls180.v:7055.1-9363.4" + wire width 8 $0\main_libresocsim_source_payload_data[7:0] + attribute \src "build/ls180/gateware/ls180.v:7055.1-9363.4" + wire $0\main_libresocsim_source_valid[0:0] + attribute \src "build/ls180/gateware/ls180.v:7055.1-9363.4" + wire width 32 $0\main_libresocsim_storage[31:0] + attribute \src "build/ls180/gateware/ls180.v:7055.1-9363.4" + wire $0\main_libresocsim_timer_en_re[0:0] + attribute \src "build/ls180/gateware/ls180.v:7055.1-9363.4" + wire $0\main_libresocsim_timer_en_storage[0:0] + attribute \src "build/ls180/gateware/ls180.v:7055.1-9363.4" + wire $0\main_libresocsim_timer_eventmanager_re[0:0] + attribute \src "build/ls180/gateware/ls180.v:7055.1-9363.4" + wire $0\main_libresocsim_timer_eventmanager_storage[0:0] + attribute \src "build/ls180/gateware/ls180.v:7055.1-9363.4" + wire $0\main_libresocsim_timer_load_re[0:0] + attribute \src "build/ls180/gateware/ls180.v:7055.1-9363.4" + wire width 32 $0\main_libresocsim_timer_load_storage[31:0] + attribute \src "build/ls180/gateware/ls180.v:7055.1-9363.4" + wire $0\main_libresocsim_timer_reload_re[0:0] + attribute \src "build/ls180/gateware/ls180.v:7055.1-9363.4" + wire width 32 $0\main_libresocsim_timer_reload_storage[31:0] + attribute \src "build/ls180/gateware/ls180.v:7055.1-9363.4" + wire $0\main_libresocsim_timer_update_value_re[0:0] + attribute \src "build/ls180/gateware/ls180.v:7055.1-9363.4" + wire $0\main_libresocsim_timer_update_value_storage[0:0] + attribute \src "build/ls180/gateware/ls180.v:7055.1-9363.4" + wire width 32 $0\main_libresocsim_timer_value[31:0] + attribute \src "build/ls180/gateware/ls180.v:7055.1-9363.4" + wire width 32 $0\main_libresocsim_timer_value_status[31:0] + attribute \src "build/ls180/gateware/ls180.v:2842.1-2847.4" + wire $0\main_libresocsim_timer_zero_clear[0:0] + attribute \src "build/ls180/gateware/ls180.v:7055.1-9363.4" + wire $0\main_libresocsim_timer_zero_old_trigger[0:0] + attribute \src "build/ls180/gateware/ls180.v:7055.1-9363.4" + wire $0\main_libresocsim_timer_zero_pending[0:0] + attribute \src "build/ls180/gateware/ls180.v:7055.1-9363.4" + wire width 4 $0\main_libresocsim_tx_bitcount[3:0] + attribute \src "build/ls180/gateware/ls180.v:7055.1-9363.4" + wire $0\main_libresocsim_tx_busy[0:0] + attribute \src "build/ls180/gateware/ls180.v:7055.1-9363.4" + wire width 8 $0\main_libresocsim_tx_reg[7:0] + attribute \src "build/ls180/gateware/ls180.v:7055.1-9363.4" + wire $0\main_libresocsim_uart_clk_rxen[0:0] + attribute \src "build/ls180/gateware/ls180.v:7055.1-9363.4" + wire $0\main_libresocsim_uart_clk_txen[0:0] + attribute \src "build/ls180/gateware/ls180.v:2772.1-2776.4" + wire width 2 $0\main_libresocsim_uart_eventmanager_pending_w[1:0] + attribute \src "build/ls180/gateware/ls180.v:7055.1-9363.4" + wire $0\main_libresocsim_uart_eventmanager_re[0:0] + attribute \src "build/ls180/gateware/ls180.v:2761.1-2765.4" + wire width 2 $0\main_libresocsim_uart_eventmanager_status_w[1:0] + attribute \src "build/ls180/gateware/ls180.v:7055.1-9363.4" + wire width 2 $0\main_libresocsim_uart_eventmanager_storage[1:0] + attribute \src "build/ls180/gateware/ls180.v:282.5-282.39" + wire $0\main_libresocsim_uart_reset[0:0] + attribute \src "build/ls180/gateware/ls180.v:2766.1-2771.4" + wire $0\main_libresocsim_uart_rx_clear[0:0] + attribute \src "build/ls180/gateware/ls180.v:7055.1-9363.4" + wire width 4 $0\main_libresocsim_uart_rx_fifo_consume[3:0] + attribute \src "build/ls180/gateware/ls180.v:7055.1-9363.4" + wire width 5 $0\main_libresocsim_uart_rx_fifo_level0[4:0] + attribute \src "build/ls180/gateware/ls180.v:7055.1-9363.4" + wire width 4 $0\main_libresocsim_uart_rx_fifo_produce[3:0] + attribute \src "build/ls180/gateware/ls180.v:7055.1-9363.4" + wire $0\main_libresocsim_uart_rx_fifo_readable[0:0] + attribute \src "build/ls180/gateware/ls180.v:264.5-264.49" + wire $0\main_libresocsim_uart_rx_fifo_replace[0:0] + attribute \src "build/ls180/gateware/ls180.v:2824.1-2831.4" + wire width 4 $0\main_libresocsim_uart_rx_fifo_wrport_adr[3:0] + attribute \src "build/ls180/gateware/ls180.v:7055.1-9363.4" + wire $0\main_libresocsim_uart_rx_old_trigger[0:0] + attribute \src "build/ls180/gateware/ls180.v:7055.1-9363.4" + wire $0\main_libresocsim_uart_rx_pending[0:0] + attribute \src "build/ls180/gateware/ls180.v:2755.1-2760.4" + wire $0\main_libresocsim_uart_tx_clear[0:0] + attribute \src "build/ls180/gateware/ls180.v:7055.1-9363.4" + wire width 4 $0\main_libresocsim_uart_tx_fifo_consume[3:0] + attribute \src "build/ls180/gateware/ls180.v:7055.1-9363.4" + wire width 5 $0\main_libresocsim_uart_tx_fifo_level0[4:0] + attribute \src "build/ls180/gateware/ls180.v:7055.1-9363.4" + wire width 4 $0\main_libresocsim_uart_tx_fifo_produce[3:0] + attribute \src "build/ls180/gateware/ls180.v:7055.1-9363.4" + wire $0\main_libresocsim_uart_tx_fifo_readable[0:0] + attribute \src "build/ls180/gateware/ls180.v:227.5-227.49" + wire $0\main_libresocsim_uart_tx_fifo_replace[0:0] + attribute \src "build/ls180/gateware/ls180.v:210.5-210.52" + wire $0\main_libresocsim_uart_tx_fifo_sink_first[0:0] + attribute \src "build/ls180/gateware/ls180.v:211.5-211.51" + wire $0\main_libresocsim_uart_tx_fifo_sink_last[0:0] + attribute \src "build/ls180/gateware/ls180.v:2794.1-2801.4" + wire width 4 $0\main_libresocsim_uart_tx_fifo_wrport_adr[3:0] + attribute \src "build/ls180/gateware/ls180.v:7055.1-9363.4" + wire $0\main_libresocsim_uart_tx_old_trigger[0:0] + attribute \src "build/ls180/gateware/ls180.v:7055.1-9363.4" + wire $0\main_libresocsim_uart_tx_pending[0:0] + attribute \src "build/ls180/gateware/ls180.v:2715.1-2721.4" + wire width 4 $0\main_libresocsim_we[3:0] + attribute \src "build/ls180/gateware/ls180.v:3919.1-3965.4" + wire width 30 $0\main_litedram_wb_adr[29:0] + attribute \src "build/ls180/gateware/ls180.v:3919.1-3965.4" + wire $0\main_litedram_wb_cyc[0:0] + attribute \src "build/ls180/gateware/ls180.v:3907.1-3917.4" + wire width 16 $0\main_litedram_wb_dat_w[15:0] + attribute \src "build/ls180/gateware/ls180.v:3919.1-3965.4" + wire width 2 $0\main_litedram_wb_sel[1:0] + attribute \src "build/ls180/gateware/ls180.v:3919.1-3965.4" + wire $0\main_litedram_wb_stb[0:0] + attribute \src "build/ls180/gateware/ls180.v:3919.1-3965.4" + wire $0\main_litedram_wb_we[0:0] + attribute \src "build/ls180/gateware/ls180.v:7055.1-9363.4" + wire $0\main_loopback_re[0:0] + attribute \src "build/ls180/gateware/ls180.v:7055.1-9363.4" + wire $0\main_loopback_storage[0:0] + attribute \src "build/ls180/gateware/ls180.v:7055.1-9363.4" + wire width 8 $0\main_miso[7:0] + attribute \src "build/ls180/gateware/ls180.v:7055.1-9363.4" + wire width 8 $0\main_miso_data[7:0] + attribute \src "build/ls180/gateware/ls180.v:3989.1-4037.4" + wire $0\main_miso_latch[0:0] + attribute \src "build/ls180/gateware/ls180.v:7055.1-9363.4" + wire width 8 $0\main_mosi_data[7:0] + attribute \src "build/ls180/gateware/ls180.v:3989.1-4037.4" + wire $0\main_mosi_latch[0:0] + attribute \src "build/ls180/gateware/ls180.v:7055.1-9363.4" + wire $0\main_mosi_re[0:0] + attribute \src "build/ls180/gateware/ls180.v:7055.1-9363.4" + wire width 3 $0\main_mosi_sel[2:0] + attribute \src "build/ls180/gateware/ls180.v:7055.1-9363.4" + wire width 8 $0\main_mosi_storage[7:0] + attribute \src "build/ls180/gateware/ls180.v:7055.1-9363.4" + wire width 3 $0\main_rddata_en[2:0] + attribute \src "build/ls180/gateware/ls180.v:7055.1-9363.4" + wire $0\main_sdram_address_re[0:0] + attribute \src "build/ls180/gateware/ls180.v:7055.1-9363.4" + wire width 13 $0\main_sdram_address_storage[12:0] + attribute \src "build/ls180/gateware/ls180.v:7055.1-9363.4" + wire $0\main_sdram_baddress_re[0:0] + attribute \src "build/ls180/gateware/ls180.v:7055.1-9363.4" + wire width 2 $0\main_sdram_baddress_storage[1:0] + attribute \src "build/ls180/gateware/ls180.v:3064.1-3071.4" + wire $0\main_sdram_bankmachine0_auto_precharge[0:0] + attribute \src "build/ls180/gateware/ls180.v:7055.1-9363.4" + wire width 3 $0\main_sdram_bankmachine0_cmd_buffer_lookahead_consume[2:0] + attribute \src "build/ls180/gateware/ls180.v:7055.1-9363.4" + wire width 4 $0\main_sdram_bankmachine0_cmd_buffer_lookahead_level[3:0] + attribute \src "build/ls180/gateware/ls180.v:7055.1-9363.4" + wire width 3 $0\main_sdram_bankmachine0_cmd_buffer_lookahead_produce[2:0] + attribute \src "build/ls180/gateware/ls180.v:510.5-510.64" + wire $0\main_sdram_bankmachine0_cmd_buffer_lookahead_replace[0:0] + attribute \src "build/ls180/gateware/ls180.v:493.5-493.67" + wire $0\main_sdram_bankmachine0_cmd_buffer_lookahead_sink_first[0:0] + attribute \src "build/ls180/gateware/ls180.v:494.5-494.66" + wire $0\main_sdram_bankmachine0_cmd_buffer_lookahead_sink_last[0:0] + attribute \src "build/ls180/gateware/ls180.v:3086.1-3093.4" + wire width 3 $0\main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr[2:0] + attribute \src "build/ls180/gateware/ls180.v:7055.1-9363.4" + wire $0\main_sdram_bankmachine0_cmd_buffer_source_first[0:0] + attribute \src "build/ls180/gateware/ls180.v:7055.1-9363.4" + wire $0\main_sdram_bankmachine0_cmd_buffer_source_last[0:0] + attribute \src "build/ls180/gateware/ls180.v:7055.1-9363.4" + wire width 22 $0\main_sdram_bankmachine0_cmd_buffer_source_payload_addr[21:0] + attribute \src "build/ls180/gateware/ls180.v:7055.1-9363.4" + wire $0\main_sdram_bankmachine0_cmd_buffer_source_payload_we[0:0] + attribute \src "build/ls180/gateware/ls180.v:7055.1-9363.4" + wire $0\main_sdram_bankmachine0_cmd_buffer_source_valid[0:0] + attribute \src "build/ls180/gateware/ls180.v:3053.1-3060.4" + wire width 13 $0\main_sdram_bankmachine0_cmd_payload_a[12:0] + attribute \src "build/ls180/gateware/ls180.v:3102.1-3195.4" + wire $0\main_sdram_bankmachine0_cmd_payload_cas[0:0] + attribute \src "build/ls180/gateware/ls180.v:3102.1-3195.4" + wire $0\main_sdram_bankmachine0_cmd_payload_is_cmd[0:0] + attribute \src "build/ls180/gateware/ls180.v:3102.1-3195.4" + wire $0\main_sdram_bankmachine0_cmd_payload_is_read[0:0] + attribute \src "build/ls180/gateware/ls180.v:3102.1-3195.4" + wire $0\main_sdram_bankmachine0_cmd_payload_is_write[0:0] + attribute \src "build/ls180/gateware/ls180.v:3102.1-3195.4" + wire $0\main_sdram_bankmachine0_cmd_payload_ras[0:0] + attribute \src "build/ls180/gateware/ls180.v:3102.1-3195.4" + wire $0\main_sdram_bankmachine0_cmd_payload_we[0:0] + attribute \src "build/ls180/gateware/ls180.v:3751.1-3759.4" + wire $0\main_sdram_bankmachine0_cmd_ready[0:0] + attribute \src "build/ls180/gateware/ls180.v:3102.1-3195.4" + wire $0\main_sdram_bankmachine0_cmd_valid[0:0] + attribute \src "build/ls180/gateware/ls180.v:3102.1-3195.4" + wire $0\main_sdram_bankmachine0_refresh_gnt[0:0] + attribute \src "build/ls180/gateware/ls180.v:3102.1-3195.4" + wire $0\main_sdram_bankmachine0_req_rdata_valid[0:0] + attribute \src "build/ls180/gateware/ls180.v:3102.1-3195.4" + wire $0\main_sdram_bankmachine0_req_wdata_ready[0:0] + attribute \src "build/ls180/gateware/ls180.v:7055.1-9363.4" + wire width 13 $0\main_sdram_bankmachine0_row[12:0] + attribute \src "build/ls180/gateware/ls180.v:3102.1-3195.4" + wire $0\main_sdram_bankmachine0_row_close[0:0] + attribute \src "build/ls180/gateware/ls180.v:3102.1-3195.4" + wire $0\main_sdram_bankmachine0_row_col_n_addr_sel[0:0] + attribute \src "build/ls180/gateware/ls180.v:3102.1-3195.4" + wire $0\main_sdram_bankmachine0_row_open[0:0] + attribute \src "build/ls180/gateware/ls180.v:7055.1-9363.4" + wire $0\main_sdram_bankmachine0_row_opened[0:0] + attribute \src "build/ls180/gateware/ls180.v:552.32-552.76" + wire $0\main_sdram_bankmachine0_trascon_ready[0:0] + attribute \src "build/ls180/gateware/ls180.v:550.32-550.75" + wire $0\main_sdram_bankmachine0_trccon_ready[0:0] + attribute \src "build/ls180/gateware/ls180.v:7055.1-9363.4" + wire width 3 $0\main_sdram_bankmachine0_twtpcon_count[2:0] + attribute \src "build/ls180/gateware/ls180.v:7055.1-9363.4" + wire $0\main_sdram_bankmachine0_twtpcon_ready[0:0] + attribute \src "build/ls180/gateware/ls180.v:3221.1-3228.4" + wire $0\main_sdram_bankmachine1_auto_precharge[0:0] + attribute \src "build/ls180/gateware/ls180.v:7055.1-9363.4" + wire width 3 $0\main_sdram_bankmachine1_cmd_buffer_lookahead_consume[2:0] + attribute \src "build/ls180/gateware/ls180.v:7055.1-9363.4" + wire width 4 $0\main_sdram_bankmachine1_cmd_buffer_lookahead_level[3:0] + attribute \src "build/ls180/gateware/ls180.v:7055.1-9363.4" + wire width 3 $0\main_sdram_bankmachine1_cmd_buffer_lookahead_produce[2:0] + attribute \src "build/ls180/gateware/ls180.v:592.5-592.64" + wire $0\main_sdram_bankmachine1_cmd_buffer_lookahead_replace[0:0] + attribute \src "build/ls180/gateware/ls180.v:575.5-575.67" + wire $0\main_sdram_bankmachine1_cmd_buffer_lookahead_sink_first[0:0] + attribute \src "build/ls180/gateware/ls180.v:576.5-576.66" + wire $0\main_sdram_bankmachine1_cmd_buffer_lookahead_sink_last[0:0] + attribute \src "build/ls180/gateware/ls180.v:3243.1-3250.4" + wire width 3 $0\main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr[2:0] + attribute \src "build/ls180/gateware/ls180.v:7055.1-9363.4" + wire $0\main_sdram_bankmachine1_cmd_buffer_source_first[0:0] + attribute \src "build/ls180/gateware/ls180.v:7055.1-9363.4" + wire $0\main_sdram_bankmachine1_cmd_buffer_source_last[0:0] + attribute \src "build/ls180/gateware/ls180.v:7055.1-9363.4" + wire width 22 $0\main_sdram_bankmachine1_cmd_buffer_source_payload_addr[21:0] + attribute \src "build/ls180/gateware/ls180.v:7055.1-9363.4" + wire $0\main_sdram_bankmachine1_cmd_buffer_source_payload_we[0:0] + attribute \src "build/ls180/gateware/ls180.v:7055.1-9363.4" + wire $0\main_sdram_bankmachine1_cmd_buffer_source_valid[0:0] + attribute \src "build/ls180/gateware/ls180.v:3210.1-3217.4" + wire width 13 $0\main_sdram_bankmachine1_cmd_payload_a[12:0] + attribute \src "build/ls180/gateware/ls180.v:3259.1-3352.4" + wire $0\main_sdram_bankmachine1_cmd_payload_cas[0:0] + attribute \src "build/ls180/gateware/ls180.v:3259.1-3352.4" + wire $0\main_sdram_bankmachine1_cmd_payload_is_cmd[0:0] + attribute \src "build/ls180/gateware/ls180.v:3259.1-3352.4" + wire $0\main_sdram_bankmachine1_cmd_payload_is_read[0:0] + attribute \src "build/ls180/gateware/ls180.v:3259.1-3352.4" + wire $0\main_sdram_bankmachine1_cmd_payload_is_write[0:0] + attribute \src "build/ls180/gateware/ls180.v:3259.1-3352.4" + wire $0\main_sdram_bankmachine1_cmd_payload_ras[0:0] + attribute \src "build/ls180/gateware/ls180.v:3259.1-3352.4" + wire $0\main_sdram_bankmachine1_cmd_payload_we[0:0] + attribute \src "build/ls180/gateware/ls180.v:3760.1-3768.4" + wire $0\main_sdram_bankmachine1_cmd_ready[0:0] + attribute \src "build/ls180/gateware/ls180.v:3259.1-3352.4" + wire $0\main_sdram_bankmachine1_cmd_valid[0:0] + attribute \src "build/ls180/gateware/ls180.v:3259.1-3352.4" + wire $0\main_sdram_bankmachine1_refresh_gnt[0:0] + attribute \src "build/ls180/gateware/ls180.v:3259.1-3352.4" + wire $0\main_sdram_bankmachine1_req_rdata_valid[0:0] + attribute \src "build/ls180/gateware/ls180.v:3259.1-3352.4" + wire $0\main_sdram_bankmachine1_req_wdata_ready[0:0] + attribute \src "build/ls180/gateware/ls180.v:7055.1-9363.4" + wire width 13 $0\main_sdram_bankmachine1_row[12:0] + attribute \src "build/ls180/gateware/ls180.v:3259.1-3352.4" + wire $0\main_sdram_bankmachine1_row_close[0:0] + attribute \src "build/ls180/gateware/ls180.v:3259.1-3352.4" + wire $0\main_sdram_bankmachine1_row_col_n_addr_sel[0:0] + attribute \src "build/ls180/gateware/ls180.v:3259.1-3352.4" + wire $0\main_sdram_bankmachine1_row_open[0:0] + attribute \src "build/ls180/gateware/ls180.v:7055.1-9363.4" + wire $0\main_sdram_bankmachine1_row_opened[0:0] + attribute \src "build/ls180/gateware/ls180.v:634.32-634.76" + wire $0\main_sdram_bankmachine1_trascon_ready[0:0] + attribute \src "build/ls180/gateware/ls180.v:632.32-632.75" + wire $0\main_sdram_bankmachine1_trccon_ready[0:0] + attribute \src "build/ls180/gateware/ls180.v:7055.1-9363.4" + wire width 3 $0\main_sdram_bankmachine1_twtpcon_count[2:0] + attribute \src "build/ls180/gateware/ls180.v:7055.1-9363.4" + wire $0\main_sdram_bankmachine1_twtpcon_ready[0:0] + attribute \src "build/ls180/gateware/ls180.v:3378.1-3385.4" + wire $0\main_sdram_bankmachine2_auto_precharge[0:0] + attribute \src "build/ls180/gateware/ls180.v:7055.1-9363.4" + wire width 3 $0\main_sdram_bankmachine2_cmd_buffer_lookahead_consume[2:0] + attribute \src "build/ls180/gateware/ls180.v:7055.1-9363.4" + wire width 4 $0\main_sdram_bankmachine2_cmd_buffer_lookahead_level[3:0] + attribute \src "build/ls180/gateware/ls180.v:7055.1-9363.4" + wire width 3 $0\main_sdram_bankmachine2_cmd_buffer_lookahead_produce[2:0] + attribute \src "build/ls180/gateware/ls180.v:674.5-674.64" + wire $0\main_sdram_bankmachine2_cmd_buffer_lookahead_replace[0:0] + attribute \src "build/ls180/gateware/ls180.v:657.5-657.67" + wire $0\main_sdram_bankmachine2_cmd_buffer_lookahead_sink_first[0:0] + attribute \src "build/ls180/gateware/ls180.v:658.5-658.66" + wire $0\main_sdram_bankmachine2_cmd_buffer_lookahead_sink_last[0:0] + attribute \src "build/ls180/gateware/ls180.v:3400.1-3407.4" + wire width 3 $0\main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr[2:0] + attribute \src "build/ls180/gateware/ls180.v:7055.1-9363.4" + wire $0\main_sdram_bankmachine2_cmd_buffer_source_first[0:0] + attribute \src "build/ls180/gateware/ls180.v:7055.1-9363.4" + wire $0\main_sdram_bankmachine2_cmd_buffer_source_last[0:0] + attribute \src "build/ls180/gateware/ls180.v:7055.1-9363.4" + wire width 22 $0\main_sdram_bankmachine2_cmd_buffer_source_payload_addr[21:0] + attribute \src "build/ls180/gateware/ls180.v:7055.1-9363.4" + wire $0\main_sdram_bankmachine2_cmd_buffer_source_payload_we[0:0] + attribute \src "build/ls180/gateware/ls180.v:7055.1-9363.4" + wire $0\main_sdram_bankmachine2_cmd_buffer_source_valid[0:0] + attribute \src "build/ls180/gateware/ls180.v:3367.1-3374.4" + wire width 13 $0\main_sdram_bankmachine2_cmd_payload_a[12:0] + attribute \src "build/ls180/gateware/ls180.v:3416.1-3509.4" + wire $0\main_sdram_bankmachine2_cmd_payload_cas[0:0] + attribute \src "build/ls180/gateware/ls180.v:3416.1-3509.4" + wire $0\main_sdram_bankmachine2_cmd_payload_is_cmd[0:0] + attribute \src "build/ls180/gateware/ls180.v:3416.1-3509.4" + wire $0\main_sdram_bankmachine2_cmd_payload_is_read[0:0] + attribute \src "build/ls180/gateware/ls180.v:3416.1-3509.4" + wire $0\main_sdram_bankmachine2_cmd_payload_is_write[0:0] + attribute \src "build/ls180/gateware/ls180.v:3416.1-3509.4" + wire $0\main_sdram_bankmachine2_cmd_payload_ras[0:0] + attribute \src "build/ls180/gateware/ls180.v:3416.1-3509.4" + wire $0\main_sdram_bankmachine2_cmd_payload_we[0:0] + attribute \src "build/ls180/gateware/ls180.v:3769.1-3777.4" + wire $0\main_sdram_bankmachine2_cmd_ready[0:0] + attribute \src "build/ls180/gateware/ls180.v:3416.1-3509.4" + wire $0\main_sdram_bankmachine2_cmd_valid[0:0] + attribute \src "build/ls180/gateware/ls180.v:3416.1-3509.4" + wire $0\main_sdram_bankmachine2_refresh_gnt[0:0] + attribute \src "build/ls180/gateware/ls180.v:3416.1-3509.4" + wire $0\main_sdram_bankmachine2_req_rdata_valid[0:0] + attribute \src "build/ls180/gateware/ls180.v:3416.1-3509.4" + wire $0\main_sdram_bankmachine2_req_wdata_ready[0:0] + attribute \src "build/ls180/gateware/ls180.v:7055.1-9363.4" + wire width 13 $0\main_sdram_bankmachine2_row[12:0] + attribute \src "build/ls180/gateware/ls180.v:3416.1-3509.4" + wire $0\main_sdram_bankmachine2_row_close[0:0] + attribute \src "build/ls180/gateware/ls180.v:3416.1-3509.4" + wire $0\main_sdram_bankmachine2_row_col_n_addr_sel[0:0] + attribute \src "build/ls180/gateware/ls180.v:3416.1-3509.4" + wire $0\main_sdram_bankmachine2_row_open[0:0] + attribute \src "build/ls180/gateware/ls180.v:7055.1-9363.4" + wire $0\main_sdram_bankmachine2_row_opened[0:0] + attribute \src "build/ls180/gateware/ls180.v:716.32-716.76" + wire $0\main_sdram_bankmachine2_trascon_ready[0:0] + attribute \src "build/ls180/gateware/ls180.v:714.32-714.75" + wire $0\main_sdram_bankmachine2_trccon_ready[0:0] + attribute \src "build/ls180/gateware/ls180.v:7055.1-9363.4" + wire width 3 $0\main_sdram_bankmachine2_twtpcon_count[2:0] + attribute \src "build/ls180/gateware/ls180.v:7055.1-9363.4" + wire $0\main_sdram_bankmachine2_twtpcon_ready[0:0] + attribute \src "build/ls180/gateware/ls180.v:3535.1-3542.4" + wire $0\main_sdram_bankmachine3_auto_precharge[0:0] + attribute \src "build/ls180/gateware/ls180.v:7055.1-9363.4" + wire width 3 $0\main_sdram_bankmachine3_cmd_buffer_lookahead_consume[2:0] + attribute \src "build/ls180/gateware/ls180.v:7055.1-9363.4" + wire width 4 $0\main_sdram_bankmachine3_cmd_buffer_lookahead_level[3:0] + attribute \src "build/ls180/gateware/ls180.v:7055.1-9363.4" + wire width 3 $0\main_sdram_bankmachine3_cmd_buffer_lookahead_produce[2:0] + attribute \src "build/ls180/gateware/ls180.v:756.5-756.64" + wire $0\main_sdram_bankmachine3_cmd_buffer_lookahead_replace[0:0] + attribute \src "build/ls180/gateware/ls180.v:739.5-739.67" + wire $0\main_sdram_bankmachine3_cmd_buffer_lookahead_sink_first[0:0] + attribute \src "build/ls180/gateware/ls180.v:740.5-740.66" + wire $0\main_sdram_bankmachine3_cmd_buffer_lookahead_sink_last[0:0] + attribute \src "build/ls180/gateware/ls180.v:3557.1-3564.4" + wire width 3 $0\main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr[2:0] + attribute \src "build/ls180/gateware/ls180.v:7055.1-9363.4" + wire $0\main_sdram_bankmachine3_cmd_buffer_source_first[0:0] + attribute \src "build/ls180/gateware/ls180.v:7055.1-9363.4" + wire $0\main_sdram_bankmachine3_cmd_buffer_source_last[0:0] + attribute \src "build/ls180/gateware/ls180.v:7055.1-9363.4" + wire width 22 $0\main_sdram_bankmachine3_cmd_buffer_source_payload_addr[21:0] + attribute \src "build/ls180/gateware/ls180.v:7055.1-9363.4" + wire $0\main_sdram_bankmachine3_cmd_buffer_source_payload_we[0:0] + attribute \src "build/ls180/gateware/ls180.v:7055.1-9363.4" + wire $0\main_sdram_bankmachine3_cmd_buffer_source_valid[0:0] + attribute \src "build/ls180/gateware/ls180.v:3524.1-3531.4" + wire width 13 $0\main_sdram_bankmachine3_cmd_payload_a[12:0] + attribute \src "build/ls180/gateware/ls180.v:3573.1-3666.4" + wire $0\main_sdram_bankmachine3_cmd_payload_cas[0:0] + attribute \src "build/ls180/gateware/ls180.v:3573.1-3666.4" + wire $0\main_sdram_bankmachine3_cmd_payload_is_cmd[0:0] + attribute \src "build/ls180/gateware/ls180.v:3573.1-3666.4" + wire $0\main_sdram_bankmachine3_cmd_payload_is_read[0:0] + attribute \src "build/ls180/gateware/ls180.v:3573.1-3666.4" + wire $0\main_sdram_bankmachine3_cmd_payload_is_write[0:0] + attribute \src "build/ls180/gateware/ls180.v:3573.1-3666.4" + wire $0\main_sdram_bankmachine3_cmd_payload_ras[0:0] + attribute \src "build/ls180/gateware/ls180.v:3573.1-3666.4" + wire $0\main_sdram_bankmachine3_cmd_payload_we[0:0] + attribute \src "build/ls180/gateware/ls180.v:3778.1-3786.4" + wire $0\main_sdram_bankmachine3_cmd_ready[0:0] + attribute \src "build/ls180/gateware/ls180.v:3573.1-3666.4" + wire $0\main_sdram_bankmachine3_cmd_valid[0:0] + attribute \src "build/ls180/gateware/ls180.v:3573.1-3666.4" + wire $0\main_sdram_bankmachine3_refresh_gnt[0:0] + attribute \src "build/ls180/gateware/ls180.v:3573.1-3666.4" + wire $0\main_sdram_bankmachine3_req_rdata_valid[0:0] + attribute \src "build/ls180/gateware/ls180.v:3573.1-3666.4" + wire $0\main_sdram_bankmachine3_req_wdata_ready[0:0] + attribute \src "build/ls180/gateware/ls180.v:7055.1-9363.4" + wire width 13 $0\main_sdram_bankmachine3_row[12:0] + attribute \src "build/ls180/gateware/ls180.v:3573.1-3666.4" + wire $0\main_sdram_bankmachine3_row_close[0:0] + attribute \src "build/ls180/gateware/ls180.v:3573.1-3666.4" + wire $0\main_sdram_bankmachine3_row_col_n_addr_sel[0:0] + attribute \src "build/ls180/gateware/ls180.v:3573.1-3666.4" + wire $0\main_sdram_bankmachine3_row_open[0:0] + attribute \src "build/ls180/gateware/ls180.v:7055.1-9363.4" + wire $0\main_sdram_bankmachine3_row_opened[0:0] + attribute \src "build/ls180/gateware/ls180.v:798.32-798.76" + wire $0\main_sdram_bankmachine3_trascon_ready[0:0] + attribute \src "build/ls180/gateware/ls180.v:796.32-796.75" + wire $0\main_sdram_bankmachine3_trccon_ready[0:0] + attribute \src "build/ls180/gateware/ls180.v:7055.1-9363.4" + wire width 3 $0\main_sdram_bankmachine3_twtpcon_count[2:0] + attribute \src "build/ls180/gateware/ls180.v:7055.1-9363.4" + wire $0\main_sdram_bankmachine3_twtpcon_ready[0:0] + attribute \src "build/ls180/gateware/ls180.v:3700.1-3705.4" + wire $0\main_sdram_choose_cmd_cmd_payload_cas[0:0] + attribute \src "build/ls180/gateware/ls180.v:3706.1-3711.4" + wire $0\main_sdram_choose_cmd_cmd_payload_ras[0:0] + attribute \src "build/ls180/gateware/ls180.v:3712.1-3717.4" + wire $0\main_sdram_choose_cmd_cmd_payload_we[0:0] + attribute \src "build/ls180/gateware/ls180.v:806.5-806.43" + wire $0\main_sdram_choose_cmd_cmd_ready[0:0] + attribute \src "build/ls180/gateware/ls180.v:7055.1-9363.4" + wire width 2 $0\main_sdram_choose_cmd_grant[1:0] + attribute \src "build/ls180/gateware/ls180.v:3686.1-3692.4" + wire width 4 $0\main_sdram_choose_cmd_valids[3:0] + attribute \src "build/ls180/gateware/ls180.v:804.5-804.48" + wire $0\main_sdram_choose_cmd_want_activates[0:0] + attribute \src "build/ls180/gateware/ls180.v:803.5-803.43" + wire $0\main_sdram_choose_cmd_want_cmds[0:0] + attribute \src "build/ls180/gateware/ls180.v:801.5-801.44" + wire $0\main_sdram_choose_cmd_want_reads[0:0] + attribute \src "build/ls180/gateware/ls180.v:802.5-802.45" + wire $0\main_sdram_choose_cmd_want_writes[0:0] + attribute \src "build/ls180/gateware/ls180.v:3733.1-3738.4" + wire $0\main_sdram_choose_req_cmd_payload_cas[0:0] + attribute \src "build/ls180/gateware/ls180.v:3739.1-3744.4" + wire $0\main_sdram_choose_req_cmd_payload_ras[0:0] + attribute \src "build/ls180/gateware/ls180.v:3745.1-3750.4" + wire $0\main_sdram_choose_req_cmd_payload_we[0:0] + attribute \src "build/ls180/gateware/ls180.v:3791.1-3863.4" + wire $0\main_sdram_choose_req_cmd_ready[0:0] + attribute \src "build/ls180/gateware/ls180.v:7055.1-9363.4" + wire width 2 $0\main_sdram_choose_req_grant[1:0] + attribute \src "build/ls180/gateware/ls180.v:3719.1-3725.4" + wire width 4 $0\main_sdram_choose_req_valids[3:0] + attribute \src "build/ls180/gateware/ls180.v:3791.1-3863.4" + wire $0\main_sdram_choose_req_want_activates[0:0] + attribute \src "build/ls180/gateware/ls180.v:3791.1-3863.4" + wire $0\main_sdram_choose_req_want_reads[0:0] + attribute \src "build/ls180/gateware/ls180.v:3791.1-3863.4" + wire $0\main_sdram_choose_req_want_writes[0:0] + attribute \src "build/ls180/gateware/ls180.v:3008.1-3038.4" + wire $0\main_sdram_cmd_last[0:0] + attribute \src "build/ls180/gateware/ls180.v:7055.1-9363.4" + wire width 13 $0\main_sdram_cmd_payload_a[12:0] + attribute \src "build/ls180/gateware/ls180.v:7055.1-9363.4" + wire width 2 $0\main_sdram_cmd_payload_ba[1:0] + attribute \src "build/ls180/gateware/ls180.v:7055.1-9363.4" + wire $0\main_sdram_cmd_payload_cas[0:0] + attribute \src "build/ls180/gateware/ls180.v:454.5-454.42" + wire $0\main_sdram_cmd_payload_is_read[0:0] + attribute \src "build/ls180/gateware/ls180.v:455.5-455.43" + wire $0\main_sdram_cmd_payload_is_write[0:0] + attribute \src "build/ls180/gateware/ls180.v:7055.1-9363.4" + wire $0\main_sdram_cmd_payload_ras[0:0] + attribute \src "build/ls180/gateware/ls180.v:7055.1-9363.4" + wire $0\main_sdram_cmd_payload_we[0:0] + attribute \src "build/ls180/gateware/ls180.v:3791.1-3863.4" + wire $0\main_sdram_cmd_ready[0:0] + attribute \src "build/ls180/gateware/ls180.v:3008.1-3038.4" + wire $0\main_sdram_cmd_valid[0:0] + attribute \src "build/ls180/gateware/ls180.v:390.5-390.38" + wire $0\main_sdram_command_issue_w[0:0] + attribute \src "build/ls180/gateware/ls180.v:7055.1-9363.4" + wire $0\main_sdram_command_re[0:0] + attribute \src "build/ls180/gateware/ls180.v:7055.1-9363.4" + wire width 6 $0\main_sdram_command_storage[5:0] + attribute \src "build/ls180/gateware/ls180.v:439.5-439.35" + wire $0\main_sdram_dfi_p0_act_n[0:0] + attribute \src "build/ls180/gateware/ls180.v:7055.1-9363.4" + wire width 13 $0\main_sdram_dfi_p0_address[12:0] + attribute \src "build/ls180/gateware/ls180.v:7055.1-9363.4" + wire width 2 $0\main_sdram_dfi_p0_bank[1:0] + attribute \src "build/ls180/gateware/ls180.v:7055.1-9363.4" + wire $0\main_sdram_dfi_p0_cas_n[0:0] + attribute \src "build/ls180/gateware/ls180.v:7055.1-9363.4" + wire $0\main_sdram_dfi_p0_cs_n[0:0] + attribute \src "build/ls180/gateware/ls180.v:7055.1-9363.4" + wire $0\main_sdram_dfi_p0_ras_n[0:0] + attribute \src "build/ls180/gateware/ls180.v:7055.1-9363.4" + wire $0\main_sdram_dfi_p0_rddata_en[0:0] + attribute \src "build/ls180/gateware/ls180.v:7055.1-9363.4" + wire $0\main_sdram_dfi_p0_we_n[0:0] + attribute \src "build/ls180/gateware/ls180.v:7055.1-9363.4" + wire $0\main_sdram_dfi_p0_wrdata_en[0:0] + attribute \src "build/ls180/gateware/ls180.v:3791.1-3863.4" + wire $0\main_sdram_en0[0:0] + attribute \src "build/ls180/gateware/ls180.v:3791.1-3863.4" + wire $0\main_sdram_en1[0:0] + attribute \src "build/ls180/gateware/ls180.v:3887.1-3900.4" + wire width 16 $0\main_sdram_interface_wdata[15:0] + attribute \src "build/ls180/gateware/ls180.v:3887.1-3900.4" + wire width 2 $0\main_sdram_interface_wdata_we[1:0] + attribute \src "build/ls180/gateware/ls180.v:340.5-340.36" + wire $0\main_sdram_inti_p0_act_n[0:0] + attribute \src "build/ls180/gateware/ls180.v:2949.1-2965.4" + wire $0\main_sdram_inti_p0_cas_n[0:0] + attribute \src "build/ls180/gateware/ls180.v:2949.1-2965.4" + wire $0\main_sdram_inti_p0_cs_n[0:0] + attribute \src "build/ls180/gateware/ls180.v:2949.1-2965.4" + wire $0\main_sdram_inti_p0_ras_n[0:0] + attribute \src "build/ls180/gateware/ls180.v:2891.1-2945.4" + wire width 16 $0\main_sdram_inti_p0_rddata[15:0] + attribute \src "build/ls180/gateware/ls180.v:2891.1-2945.4" + wire $0\main_sdram_inti_p0_rddata_valid[0:0] + attribute \src "build/ls180/gateware/ls180.v:2949.1-2965.4" + wire $0\main_sdram_inti_p0_we_n[0:0] + attribute \src "build/ls180/gateware/ls180.v:2891.1-2945.4" + wire $0\main_sdram_master_p0_act_n[0:0] + attribute \src "build/ls180/gateware/ls180.v:2891.1-2945.4" + wire width 13 $0\main_sdram_master_p0_address[12:0] + attribute \src "build/ls180/gateware/ls180.v:2891.1-2945.4" + wire width 2 $0\main_sdram_master_p0_bank[1:0] + attribute \src "build/ls180/gateware/ls180.v:2891.1-2945.4" + wire $0\main_sdram_master_p0_cas_n[0:0] + attribute \src "build/ls180/gateware/ls180.v:2891.1-2945.4" + wire $0\main_sdram_master_p0_cke[0:0] + attribute \src "build/ls180/gateware/ls180.v:2891.1-2945.4" + wire $0\main_sdram_master_p0_cs_n[0:0] + attribute \src "build/ls180/gateware/ls180.v:2891.1-2945.4" + wire $0\main_sdram_master_p0_odt[0:0] + attribute \src "build/ls180/gateware/ls180.v:2891.1-2945.4" + wire $0\main_sdram_master_p0_ras_n[0:0] + attribute \src "build/ls180/gateware/ls180.v:2891.1-2945.4" + wire $0\main_sdram_master_p0_rddata_en[0:0] + attribute \src "build/ls180/gateware/ls180.v:2891.1-2945.4" + wire $0\main_sdram_master_p0_reset_n[0:0] + attribute \src "build/ls180/gateware/ls180.v:2891.1-2945.4" + wire $0\main_sdram_master_p0_we_n[0:0] + attribute \src "build/ls180/gateware/ls180.v:2891.1-2945.4" + wire width 16 $0\main_sdram_master_p0_wrdata[15:0] + attribute \src "build/ls180/gateware/ls180.v:2891.1-2945.4" + wire $0\main_sdram_master_p0_wrdata_en[0:0] + attribute \src "build/ls180/gateware/ls180.v:2891.1-2945.4" + wire width 2 $0\main_sdram_master_p0_wrdata_mask[1:0] + attribute \src "build/ls180/gateware/ls180.v:837.12-837.36" + wire width 13 $0\main_sdram_nop_a[12:0] + attribute \src "build/ls180/gateware/ls180.v:838.11-838.35" + wire width 2 $0\main_sdram_nop_ba[1:0] + attribute \src "build/ls180/gateware/ls180.v:7055.1-9363.4" + wire $0\main_sdram_postponer_count[0:0] + attribute \src "build/ls180/gateware/ls180.v:7055.1-9363.4" + wire $0\main_sdram_postponer_req_o[0:0] + attribute \src "build/ls180/gateware/ls180.v:7055.1-9363.4" + wire $0\main_sdram_re[0:0] + attribute \src "build/ls180/gateware/ls180.v:7055.1-9363.4" + wire $0\main_sdram_sequencer_count[0:0] + attribute \src "build/ls180/gateware/ls180.v:7055.1-9363.4" + wire width 4 $0\main_sdram_sequencer_counter[3:0] + attribute \src "build/ls180/gateware/ls180.v:7055.1-9363.4" + wire $0\main_sdram_sequencer_done1[0:0] + attribute \src "build/ls180/gateware/ls180.v:3008.1-3038.4" + wire $0\main_sdram_sequencer_start0[0:0] + attribute \src "build/ls180/gateware/ls180.v:2891.1-2945.4" + wire width 16 $0\main_sdram_slave_p0_rddata[15:0] + attribute \src "build/ls180/gateware/ls180.v:2891.1-2945.4" + wire $0\main_sdram_slave_p0_rddata_valid[0:0] + attribute \src "build/ls180/gateware/ls180.v:7055.1-9363.4" + wire width 16 $0\main_sdram_status[15:0] + attribute \src "build/ls180/gateware/ls180.v:840.5-840.31" + wire $0\main_sdram_steerer0[0:0] + attribute \src "build/ls180/gateware/ls180.v:841.5-841.31" + wire $0\main_sdram_steerer1[0:0] + attribute \src "build/ls180/gateware/ls180.v:3791.1-3863.4" + wire width 2 $0\main_sdram_steerer_sel[1:0] + attribute \src "build/ls180/gateware/ls180.v:7055.1-9363.4" + wire width 4 $0\main_sdram_storage[3:0] + attribute \src "build/ls180/gateware/ls180.v:7055.1-9363.4" + wire $0\main_sdram_tccdcon_count[0:0] + attribute \src "build/ls180/gateware/ls180.v:7055.1-9363.4" + wire $0\main_sdram_tccdcon_ready[0:0] + attribute \src "build/ls180/gateware/ls180.v:845.32-845.63" + wire $0\main_sdram_tfawcon_ready[0:0] + attribute \src "build/ls180/gateware/ls180.v:7055.1-9363.4" + wire width 5 $0\main_sdram_time0[4:0] + attribute \src "build/ls180/gateware/ls180.v:7055.1-9363.4" + wire width 4 $0\main_sdram_time1[3:0] + attribute \src "build/ls180/gateware/ls180.v:7055.1-9363.4" + wire width 10 $0\main_sdram_timer_count1[9:0] + attribute \src "build/ls180/gateware/ls180.v:843.32-843.63" + wire $0\main_sdram_trrdcon_ready[0:0] + attribute \src "build/ls180/gateware/ls180.v:7055.1-9363.4" + wire width 3 $0\main_sdram_twtrcon_count[2:0] + attribute \src "build/ls180/gateware/ls180.v:7055.1-9363.4" + wire $0\main_sdram_twtrcon_ready[0:0] + attribute \src "build/ls180/gateware/ls180.v:7055.1-9363.4" + wire $0\main_sdram_wrdata_re[0:0] + attribute \src "build/ls180/gateware/ls180.v:7055.1-9363.4" + wire width 16 $0\main_sdram_wrdata_storage[15:0] + attribute \src "build/ls180/gateware/ls180.v:5932.1-5937.4" + wire $0\main_start1[0:0] + attribute \src "build/ls180/gateware/ls180.v:3919.1-3965.4" + wire $0\main_wb_sdram_ack[0:0] + attribute \src "build/ls180/gateware/ls180.v:884.5-884.29" + wire $0\main_wb_sdram_err[0:0] + attribute \src "build/ls180/gateware/ls180.v:7055.1-9363.4" + wire $0\main_wdata_consumed[0:0] + attribute \src "build/ls180/gateware/ls180.v:9367.1-9377.4" + wire width 16 $0\memadr[15:0] + attribute \src "build/ls180/gateware/ls180.v:9388.1-9392.4" + wire width 10 $0\memdat[9:0] + attribute \src "build/ls180/gateware/ls180.v:9394.1-9397.4" + wire width 10 $0\memdat_1[9:0] + attribute \src "build/ls180/gateware/ls180.v:9405.1-9409.4" + wire width 10 $0\memdat_2[9:0] + attribute \src "build/ls180/gateware/ls180.v:9411.1-9414.4" + wire width 10 $0\memdat_3[9:0] + attribute \src "build/ls180/gateware/ls180.v:9421.1-9425.4" + wire width 25 $0\memdat_4[24:0] + attribute \src "build/ls180/gateware/ls180.v:9435.1-9439.4" + wire width 25 $0\memdat_5[24:0] + attribute \src "build/ls180/gateware/ls180.v:9449.1-9453.4" + wire width 25 $0\memdat_6[24:0] + attribute \src "build/ls180/gateware/ls180.v:9463.1-9467.4" + wire width 25 $0\memdat_7[24:0] + attribute \src "build/ls180/gateware/ls180.v:9477.1-9481.4" + wire width 10 $0\memdat_8[9:0] + attribute \src "build/ls180/gateware/ls180.v:9491.1-9495.4" + wire width 10 $0\memdat_9[9:0] + attribute \src "build/ls180/gateware/ls180.v:6968.1-7053.4" + wire $0\sdcard_clk[0:0] + attribute \src "build/ls180/gateware/ls180.v:6968.1-7053.4" + wire width 13 $0\sdram_a[12:0] + attribute \src "build/ls180/gateware/ls180.v:6968.1-7053.4" + wire width 2 $0\sdram_ba[1:0] + attribute \src "build/ls180/gateware/ls180.v:6968.1-7053.4" + wire $0\sdram_cas_n[0:0] + attribute \src "build/ls180/gateware/ls180.v:6968.1-7053.4" + wire $0\sdram_cke[0:0] + attribute \src "build/ls180/gateware/ls180.v:6968.1-7053.4" + wire $0\sdram_cs_n[0:0] + attribute \src "build/ls180/gateware/ls180.v:2854.1-2858.4" + wire width 2 $0\sdram_dm[1:0] + attribute \src "build/ls180/gateware/ls180.v:6968.1-7053.4" + wire $0\sdram_ras_n[0:0] + attribute \src "build/ls180/gateware/ls180.v:6968.1-7053.4" + wire $0\sdram_we_n[0:0] + attribute \src "build/ls180/gateware/ls180.v:7055.1-9363.4" + wire $0\serial_tx[0:0] + attribute \src "build/ls180/gateware/ls180.v:7055.1-9363.4" + wire $0\spi_master_clk[0:0] + attribute \src "build/ls180/gateware/ls180.v:7055.1-9363.4" + wire $0\spi_master_cs_n[0:0] + attribute \src "build/ls180/gateware/ls180.v:7055.1-9363.4" + wire $0\spi_master_mosi[0:0] + attribute \src "build/ls180/gateware/ls180.v:7055.1-9363.4" + wire $0\spisdcard_clk[0:0] + attribute \src "build/ls180/gateware/ls180.v:7055.1-9363.4" + wire $0\spisdcard_cs_n[0:0] + attribute \src "build/ls180/gateware/ls180.v:7055.1-9363.4" + wire $0\spisdcard_mosi[0:0] + attribute \src "build/ls180/gateware/ls180.v:1629.11-1629.49" + wire width 3 $1\builder_bankmachine0_next_state[2:0] + attribute \src "build/ls180/gateware/ls180.v:1628.11-1628.44" + wire width 3 $1\builder_bankmachine0_state[2:0] + attribute \src "build/ls180/gateware/ls180.v:1631.11-1631.49" + wire width 3 $1\builder_bankmachine1_next_state[2:0] + attribute \src "build/ls180/gateware/ls180.v:1630.11-1630.44" + wire width 3 $1\builder_bankmachine1_state[2:0] + attribute \src "build/ls180/gateware/ls180.v:1633.11-1633.49" + wire width 3 $1\builder_bankmachine2_next_state[2:0] + attribute \src "build/ls180/gateware/ls180.v:1632.11-1632.44" + wire width 3 $1\builder_bankmachine2_state[2:0] + attribute \src "build/ls180/gateware/ls180.v:1635.11-1635.49" + wire width 3 $1\builder_bankmachine3_next_state[2:0] + attribute \src "build/ls180/gateware/ls180.v:1634.11-1634.44" + wire width 3 $1\builder_bankmachine3_state[2:0] + attribute \src "build/ls180/gateware/ls180.v:2374.5-2374.41" + wire $1\builder_comb_rhs_array_muxed0[0:0] + attribute \src "build/ls180/gateware/ls180.v:2387.5-2387.42" + wire $1\builder_comb_rhs_array_muxed10[0:0] + attribute \src "build/ls180/gateware/ls180.v:2388.5-2388.42" + wire $1\builder_comb_rhs_array_muxed11[0:0] + attribute \src "build/ls180/gateware/ls180.v:2392.12-2392.50" + wire width 22 $1\builder_comb_rhs_array_muxed12[21:0] + attribute \src "build/ls180/gateware/ls180.v:2393.5-2393.42" + wire $1\builder_comb_rhs_array_muxed13[0:0] + attribute \src "build/ls180/gateware/ls180.v:2394.5-2394.42" + wire $1\builder_comb_rhs_array_muxed14[0:0] + attribute \src "build/ls180/gateware/ls180.v:2395.12-2395.50" + wire width 22 $1\builder_comb_rhs_array_muxed15[21:0] + attribute \src "build/ls180/gateware/ls180.v:2396.5-2396.42" + wire $1\builder_comb_rhs_array_muxed16[0:0] + attribute \src "build/ls180/gateware/ls180.v:2397.5-2397.42" + wire $1\builder_comb_rhs_array_muxed17[0:0] + attribute \src "build/ls180/gateware/ls180.v:2398.12-2398.50" + wire width 22 $1\builder_comb_rhs_array_muxed18[21:0] + attribute \src "build/ls180/gateware/ls180.v:2399.5-2399.42" + wire $1\builder_comb_rhs_array_muxed19[0:0] + attribute \src "build/ls180/gateware/ls180.v:2375.12-2375.49" + wire width 13 $1\builder_comb_rhs_array_muxed1[12:0] + attribute \src "build/ls180/gateware/ls180.v:2400.5-2400.42" + wire $1\builder_comb_rhs_array_muxed20[0:0] + attribute \src "build/ls180/gateware/ls180.v:2401.12-2401.50" + wire width 22 $1\builder_comb_rhs_array_muxed21[21:0] + attribute \src "build/ls180/gateware/ls180.v:2402.5-2402.42" + wire $1\builder_comb_rhs_array_muxed22[0:0] + attribute \src "build/ls180/gateware/ls180.v:2403.5-2403.42" + wire $1\builder_comb_rhs_array_muxed23[0:0] + attribute \src "build/ls180/gateware/ls180.v:2404.12-2404.50" + wire width 32 $1\builder_comb_rhs_array_muxed24[31:0] + attribute \src "build/ls180/gateware/ls180.v:2405.12-2405.50" + wire width 32 $1\builder_comb_rhs_array_muxed25[31:0] + attribute \src "build/ls180/gateware/ls180.v:2406.11-2406.48" + wire width 4 $1\builder_comb_rhs_array_muxed26[3:0] + attribute \src "build/ls180/gateware/ls180.v:2407.5-2407.42" + wire $1\builder_comb_rhs_array_muxed27[0:0] + attribute \src "build/ls180/gateware/ls180.v:2408.5-2408.42" + wire $1\builder_comb_rhs_array_muxed28[0:0] + attribute \src "build/ls180/gateware/ls180.v:2409.5-2409.42" + wire $1\builder_comb_rhs_array_muxed29[0:0] + attribute \src "build/ls180/gateware/ls180.v:2376.11-2376.47" + wire width 2 $1\builder_comb_rhs_array_muxed2[1:0] + attribute \src "build/ls180/gateware/ls180.v:2410.11-2410.48" + wire width 3 $1\builder_comb_rhs_array_muxed30[2:0] + attribute \src "build/ls180/gateware/ls180.v:2411.11-2411.48" + wire width 2 $1\builder_comb_rhs_array_muxed31[1:0] + attribute \src "build/ls180/gateware/ls180.v:2377.5-2377.41" + wire $1\builder_comb_rhs_array_muxed3[0:0] + attribute \src "build/ls180/gateware/ls180.v:2378.5-2378.41" + wire $1\builder_comb_rhs_array_muxed4[0:0] + attribute \src "build/ls180/gateware/ls180.v:2379.5-2379.41" + wire $1\builder_comb_rhs_array_muxed5[0:0] + attribute \src "build/ls180/gateware/ls180.v:2383.5-2383.41" + wire $1\builder_comb_rhs_array_muxed6[0:0] + attribute \src "build/ls180/gateware/ls180.v:2384.12-2384.49" + wire width 13 $1\builder_comb_rhs_array_muxed7[12:0] + attribute \src "build/ls180/gateware/ls180.v:2385.11-2385.47" + wire width 2 $1\builder_comb_rhs_array_muxed8[1:0] + attribute \src "build/ls180/gateware/ls180.v:2386.5-2386.41" + wire $1\builder_comb_rhs_array_muxed9[0:0] + attribute \src "build/ls180/gateware/ls180.v:2380.5-2380.39" + wire $1\builder_comb_t_array_muxed0[0:0] + attribute \src "build/ls180/gateware/ls180.v:2381.5-2381.39" + wire $1\builder_comb_t_array_muxed1[0:0] + attribute \src "build/ls180/gateware/ls180.v:2382.5-2382.39" + wire $1\builder_comb_t_array_muxed2[0:0] + attribute \src "build/ls180/gateware/ls180.v:2389.5-2389.39" + wire $1\builder_comb_t_array_muxed3[0:0] + attribute \src "build/ls180/gateware/ls180.v:2390.5-2390.39" + wire $1\builder_comb_t_array_muxed4[0:0] + attribute \src "build/ls180/gateware/ls180.v:2391.5-2391.39" + wire $1\builder_comb_t_array_muxed5[0:0] + attribute \src "build/ls180/gateware/ls180.v:1619.5-1619.41" + wire $1\builder_converter0_next_state[0:0] + attribute \src "build/ls180/gateware/ls180.v:1618.5-1618.36" + wire $1\builder_converter0_state[0:0] + attribute \src "build/ls180/gateware/ls180.v:1623.5-1623.41" + wire $1\builder_converter1_next_state[0:0] + attribute \src "build/ls180/gateware/ls180.v:1622.5-1622.36" + wire $1\builder_converter1_state[0:0] + attribute \src "build/ls180/gateware/ls180.v:1660.5-1660.40" + wire $1\builder_converter_next_state[0:0] + attribute \src "build/ls180/gateware/ls180.v:1659.5-1659.35" + wire $1\builder_converter_state[0:0] + attribute \src "build/ls180/gateware/ls180.v:1780.12-1780.39" + wire width 20 $1\builder_count[19:0] + attribute \src "build/ls180/gateware/ls180.v:1777.5-1777.25" + wire $1\builder_error[0:0] + attribute \src "build/ls180/gateware/ls180.v:1774.11-1774.31" + wire width 2 $1\builder_grant[1:0] + attribute \src "build/ls180/gateware/ls180.v:2443.5-2443.42" + wire $1\builder_inferedsdrtristate0__o[0:0] + attribute \src "build/ls180/gateware/ls180.v:2444.5-2444.42" + wire $1\builder_inferedsdrtristate0_oe[0:0] + attribute \src "build/ls180/gateware/ls180.v:2483.5-2483.43" + wire $1\builder_inferedsdrtristate10__o[0:0] + attribute \src "build/ls180/gateware/ls180.v:2484.5-2484.43" + wire $1\builder_inferedsdrtristate10_oe[0:0] + attribute \src "build/ls180/gateware/ls180.v:2487.5-2487.43" + wire $1\builder_inferedsdrtristate11__o[0:0] + attribute \src "build/ls180/gateware/ls180.v:2488.5-2488.43" + wire $1\builder_inferedsdrtristate11_oe[0:0] + attribute \src "build/ls180/gateware/ls180.v:2491.5-2491.43" + wire $1\builder_inferedsdrtristate12__o[0:0] + attribute \src "build/ls180/gateware/ls180.v:2492.5-2492.43" + wire $1\builder_inferedsdrtristate12_oe[0:0] + attribute \src "build/ls180/gateware/ls180.v:2495.5-2495.43" + wire $1\builder_inferedsdrtristate13__o[0:0] + attribute \src "build/ls180/gateware/ls180.v:2496.5-2496.43" + wire $1\builder_inferedsdrtristate13_oe[0:0] + attribute \src "build/ls180/gateware/ls180.v:2499.5-2499.43" + wire $1\builder_inferedsdrtristate14__o[0:0] + attribute \src "build/ls180/gateware/ls180.v:2500.5-2500.43" + wire $1\builder_inferedsdrtristate14_oe[0:0] + attribute \src "build/ls180/gateware/ls180.v:2503.5-2503.43" + wire $1\builder_inferedsdrtristate15__o[0:0] + attribute \src "build/ls180/gateware/ls180.v:2504.5-2504.43" + wire $1\builder_inferedsdrtristate15_oe[0:0] + attribute \src "build/ls180/gateware/ls180.v:2512.5-2512.43" + wire $1\builder_inferedsdrtristate16__o[0:0] + attribute \src "build/ls180/gateware/ls180.v:2513.5-2513.43" + wire $1\builder_inferedsdrtristate16_oe[0:0] + attribute \src "build/ls180/gateware/ls180.v:2516.5-2516.43" + wire $1\builder_inferedsdrtristate17__o[0:0] + attribute \src "build/ls180/gateware/ls180.v:2517.5-2517.43" + wire $1\builder_inferedsdrtristate17_oe[0:0] + attribute \src "build/ls180/gateware/ls180.v:2520.5-2520.43" + wire $1\builder_inferedsdrtristate18__o[0:0] + attribute \src "build/ls180/gateware/ls180.v:2521.5-2521.43" + wire $1\builder_inferedsdrtristate18_oe[0:0] + attribute \src "build/ls180/gateware/ls180.v:2524.5-2524.43" + wire $1\builder_inferedsdrtristate19__o[0:0] + attribute \src "build/ls180/gateware/ls180.v:2525.5-2525.43" + wire $1\builder_inferedsdrtristate19_oe[0:0] + attribute \src "build/ls180/gateware/ls180.v:2447.5-2447.42" + wire $1\builder_inferedsdrtristate1__o[0:0] + attribute \src "build/ls180/gateware/ls180.v:2448.5-2448.42" + wire $1\builder_inferedsdrtristate1_oe[0:0] + attribute \src "build/ls180/gateware/ls180.v:2528.5-2528.43" + wire $1\builder_inferedsdrtristate20__o[0:0] + attribute \src "build/ls180/gateware/ls180.v:2529.5-2529.43" + wire $1\builder_inferedsdrtristate20_oe[0:0] + attribute \src "build/ls180/gateware/ls180.v:2451.5-2451.42" + wire $1\builder_inferedsdrtristate2__o[0:0] + attribute \src "build/ls180/gateware/ls180.v:2452.5-2452.42" + wire $1\builder_inferedsdrtristate2_oe[0:0] + attribute \src "build/ls180/gateware/ls180.v:2455.5-2455.42" + wire $1\builder_inferedsdrtristate3__o[0:0] + attribute \src "build/ls180/gateware/ls180.v:2456.5-2456.42" + wire $1\builder_inferedsdrtristate3_oe[0:0] + attribute \src "build/ls180/gateware/ls180.v:2459.5-2459.42" + wire $1\builder_inferedsdrtristate4__o[0:0] + attribute \src "build/ls180/gateware/ls180.v:2460.5-2460.42" + wire $1\builder_inferedsdrtristate4_oe[0:0] + attribute \src "build/ls180/gateware/ls180.v:2463.5-2463.42" + wire $1\builder_inferedsdrtristate5__o[0:0] + attribute \src "build/ls180/gateware/ls180.v:2464.5-2464.42" + wire $1\builder_inferedsdrtristate5_oe[0:0] + attribute \src "build/ls180/gateware/ls180.v:2467.5-2467.42" + wire $1\builder_inferedsdrtristate6__o[0:0] + attribute \src "build/ls180/gateware/ls180.v:2468.5-2468.42" + wire $1\builder_inferedsdrtristate6_oe[0:0] + attribute \src "build/ls180/gateware/ls180.v:2471.5-2471.42" + wire $1\builder_inferedsdrtristate7__o[0:0] + attribute \src "build/ls180/gateware/ls180.v:2472.5-2472.42" + wire $1\builder_inferedsdrtristate7_oe[0:0] + attribute \src "build/ls180/gateware/ls180.v:2475.5-2475.42" + wire $1\builder_inferedsdrtristate8__o[0:0] + attribute \src "build/ls180/gateware/ls180.v:2476.5-2476.42" + wire $1\builder_inferedsdrtristate8_oe[0:0] + attribute \src "build/ls180/gateware/ls180.v:2479.5-2479.42" + wire $1\builder_inferedsdrtristate9__o[0:0] + attribute \src "build/ls180/gateware/ls180.v:2480.5-2480.42" + wire $1\builder_inferedsdrtristate9_oe[0:0] + attribute \src "build/ls180/gateware/ls180.v:1784.11-1784.51" + wire width 8 $1\builder_interface0_bank_bus_dat_r[7:0] + attribute \src "build/ls180/gateware/ls180.v:2254.11-2254.52" + wire width 8 $1\builder_interface10_bank_bus_dat_r[7:0] + attribute \src "build/ls180/gateware/ls180.v:2319.11-2319.52" + wire width 8 $1\builder_interface11_bank_bus_dat_r[7:0] + attribute \src "build/ls180/gateware/ls180.v:2344.11-2344.52" + wire width 8 $1\builder_interface12_bank_bus_dat_r[7:0] + attribute \src "build/ls180/gateware/ls180.v:1825.11-1825.51" + wire width 8 $1\builder_interface1_bank_bus_dat_r[7:0] + attribute \src "build/ls180/gateware/ls180.v:1834.11-1834.51" + wire width 8 $1\builder_interface2_bank_bus_dat_r[7:0] + attribute \src "build/ls180/gateware/ls180.v:1843.11-1843.51" + wire width 8 $1\builder_interface3_bank_bus_dat_r[7:0] + attribute \src "build/ls180/gateware/ls180.v:1908.11-1908.51" + wire width 8 $1\builder_interface4_bank_bus_dat_r[7:0] + attribute \src "build/ls180/gateware/ls180.v:2041.11-2041.51" + wire width 8 $1\builder_interface5_bank_bus_dat_r[7:0] + attribute \src "build/ls180/gateware/ls180.v:2122.11-2122.51" + wire width 8 $1\builder_interface6_bank_bus_dat_r[7:0] + attribute \src "build/ls180/gateware/ls180.v:2139.11-2139.51" + wire width 8 $1\builder_interface7_bank_bus_dat_r[7:0] + attribute \src "build/ls180/gateware/ls180.v:2180.11-2180.51" + wire width 8 $1\builder_interface8_bank_bus_dat_r[7:0] + attribute \src "build/ls180/gateware/ls180.v:2213.11-2213.51" + wire width 8 $1\builder_interface9_bank_bus_dat_r[7:0] + attribute \src "build/ls180/gateware/ls180.v:1747.12-1747.43" + wire width 14 $1\builder_libresocsim_adr[13:0] + attribute \src "build/ls180/gateware/ls180.v:2370.12-2370.55" + wire width 14 $1\builder_libresocsim_adr_next_value1[13:0] + attribute \src "build/ls180/gateware/ls180.v:2371.5-2371.50" + wire $1\builder_libresocsim_adr_next_value_ce1[0:0] + attribute \src "build/ls180/gateware/ls180.v:1749.11-1749.43" + wire width 8 $1\builder_libresocsim_dat_w[7:0] + attribute \src "build/ls180/gateware/ls180.v:2368.11-2368.55" + wire width 8 $1\builder_libresocsim_dat_w_next_value0[7:0] + attribute \src "build/ls180/gateware/ls180.v:2369.5-2369.52" + wire $1\builder_libresocsim_dat_w_next_value_ce0[0:0] + attribute \src "build/ls180/gateware/ls180.v:1748.5-1748.34" + wire $1\builder_libresocsim_we[0:0] + attribute \src "build/ls180/gateware/ls180.v:2372.5-2372.46" + wire $1\builder_libresocsim_we_next_value2[0:0] + attribute \src "build/ls180/gateware/ls180.v:2373.5-2373.49" + wire $1\builder_libresocsim_we_next_value_ce2[0:0] + attribute \src "build/ls180/gateware/ls180.v:1757.5-1757.44" + wire $1\builder_libresocsim_wishbone_ack[0:0] + attribute \src "build/ls180/gateware/ls180.v:1753.12-1753.54" + wire width 32 $1\builder_libresocsim_wishbone_dat_r[31:0] + attribute \src "build/ls180/gateware/ls180.v:1637.11-1637.48" + wire width 3 $1\builder_multiplexer_next_state[2:0] + attribute \src "build/ls180/gateware/ls180.v:1636.11-1636.43" + wire width 3 $1\builder_multiplexer_state[2:0] + attribute \src "build/ls180/gateware/ls180.v:2421.32-2421.66" + wire $1\builder_multiregimpl0_regs0[0:0] + attribute \src "build/ls180/gateware/ls180.v:2422.32-2422.66" + wire $1\builder_multiregimpl0_regs1[0:0] + attribute \src "build/ls180/gateware/ls180.v:2507.38-2507.72" + wire width 8 $1\builder_multiregimpl1_regs0[7:0] + attribute \src "build/ls180/gateware/ls180.v:2508.38-2508.72" + wire width 8 $1\builder_multiregimpl1_regs1[7:0] + attribute \src "build/ls180/gateware/ls180.v:2509.38-2509.72" + wire width 8 $1\builder_multiregimpl2_regs0[7:0] + attribute \src "build/ls180/gateware/ls180.v:2510.38-2510.72" + wire width 8 $1\builder_multiregimpl2_regs1[7:0] + attribute \src "build/ls180/gateware/ls180.v:1655.5-1655.43" + wire $1\builder_new_master_rdata_valid0[0:0] + attribute \src "build/ls180/gateware/ls180.v:1656.5-1656.43" + wire $1\builder_new_master_rdata_valid1[0:0] + attribute \src "build/ls180/gateware/ls180.v:1657.5-1657.43" + wire $1\builder_new_master_rdata_valid2[0:0] + attribute \src "build/ls180/gateware/ls180.v:1658.5-1658.43" + wire $1\builder_new_master_rdata_valid3[0:0] + attribute \src "build/ls180/gateware/ls180.v:1654.5-1654.42" + wire $1\builder_new_master_wdata_ready[0:0] + attribute \src "build/ls180/gateware/ls180.v:2367.11-2367.36" + wire width 2 $1\builder_next_state[1:0] + attribute \src "build/ls180/gateware/ls180.v:1627.11-1627.46" + wire width 2 $1\builder_refresher_next_state[1:0] + attribute \src "build/ls180/gateware/ls180.v:1626.11-1626.41" + wire width 2 $1\builder_refresher_state[1:0] + attribute \src "build/ls180/gateware/ls180.v:1732.11-1732.51" + wire width 2 $1\builder_sdblock2memdma_next_state[1:0] + attribute \src "build/ls180/gateware/ls180.v:1731.11-1731.46" + wire width 2 $1\builder_sdblock2memdma_state[1:0] + attribute \src "build/ls180/gateware/ls180.v:1700.5-1700.57" + wire $1\builder_sdcore_crcupstreaminserter_next_state[0:0] + attribute \src "build/ls180/gateware/ls180.v:1699.5-1699.52" + wire $1\builder_sdcore_crcupstreaminserter_state[0:0] + attribute \src "build/ls180/gateware/ls180.v:1712.11-1712.47" + wire width 3 $1\builder_sdcore_fsm_next_state[2:0] + attribute \src "build/ls180/gateware/ls180.v:1711.11-1711.42" + wire width 3 $1\builder_sdcore_fsm_state[2:0] + attribute \src "build/ls180/gateware/ls180.v:1736.5-1736.49" + wire $1\builder_sdmem2blockdma_fsm_next_state[0:0] + attribute \src "build/ls180/gateware/ls180.v:1735.5-1735.44" + wire $1\builder_sdmem2blockdma_fsm_state[0:0] + attribute \src "build/ls180/gateware/ls180.v:1740.11-1740.65" + wire width 2 $1\builder_sdmem2blockdma_resetinserter_next_state[1:0] + attribute \src "build/ls180/gateware/ls180.v:1739.11-1739.60" + wire width 2 $1\builder_sdmem2blockdma_resetinserter_state[1:0] + attribute \src "build/ls180/gateware/ls180.v:1688.11-1688.46" + wire width 3 $1\builder_sdphy_fsm_next_state[2:0] + attribute \src "build/ls180/gateware/ls180.v:1687.11-1687.41" + wire width 3 $1\builder_sdphy_fsm_state[2:0] + attribute \src "build/ls180/gateware/ls180.v:1676.11-1676.52" + wire width 3 $1\builder_sdphy_sdphycmdr_next_state[2:0] + attribute \src "build/ls180/gateware/ls180.v:1675.11-1675.47" + wire width 3 $1\builder_sdphy_sdphycmdr_state[2:0] + attribute \src "build/ls180/gateware/ls180.v:1672.11-1672.52" + wire width 2 $1\builder_sdphy_sdphycmdw_next_state[1:0] + attribute \src "build/ls180/gateware/ls180.v:1671.11-1671.47" + wire width 2 $1\builder_sdphy_sdphycmdw_state[1:0] + attribute \src "build/ls180/gateware/ls180.v:1684.5-1684.46" + wire $1\builder_sdphy_sdphycrcr_next_state[0:0] + attribute \src "build/ls180/gateware/ls180.v:1683.5-1683.41" + wire $1\builder_sdphy_sdphycrcr_state[0:0] + attribute \src "build/ls180/gateware/ls180.v:1692.11-1692.53" + wire width 3 $1\builder_sdphy_sdphydatar_next_state[2:0] + attribute \src "build/ls180/gateware/ls180.v:1691.11-1691.48" + wire width 3 $1\builder_sdphy_sdphydatar_state[2:0] + attribute \src "build/ls180/gateware/ls180.v:1668.5-1668.46" + wire $1\builder_sdphy_sdphyinit_next_state[0:0] + attribute \src "build/ls180/gateware/ls180.v:1667.5-1667.41" + wire $1\builder_sdphy_sdphyinit_state[0:0] + attribute \src "build/ls180/gateware/ls180.v:1768.5-1768.30" + wire $1\builder_shared_ack[0:0] + attribute \src "build/ls180/gateware/ls180.v:1764.12-1764.40" + wire width 32 $1\builder_shared_dat_r[31:0] + attribute \src "build/ls180/gateware/ls180.v:1775.11-1775.35" + wire width 5 $1\builder_slave_sel[4:0] + attribute \src "build/ls180/gateware/ls180.v:1776.11-1776.37" + wire width 5 $1\builder_slave_sel_r[4:0] + attribute \src "build/ls180/gateware/ls180.v:1664.11-1664.47" + wire width 2 $1\builder_spimaster0_next_state[1:0] + attribute \src "build/ls180/gateware/ls180.v:1663.11-1663.42" + wire width 2 $1\builder_spimaster0_state[1:0] + attribute \src "build/ls180/gateware/ls180.v:1744.11-1744.47" + wire width 2 $1\builder_spimaster1_next_state[1:0] + attribute \src "build/ls180/gateware/ls180.v:1743.11-1743.42" + wire width 2 $1\builder_spimaster1_state[1:0] + attribute \src "build/ls180/gateware/ls180.v:2366.11-2366.31" + wire width 2 $1\builder_state[1:0] + attribute \src "build/ls180/gateware/ls180.v:2419.5-2419.39" + wire $1\builder_sync_f_array_muxed0[0:0] + attribute \src "build/ls180/gateware/ls180.v:2420.5-2420.39" + wire $1\builder_sync_f_array_muxed1[0:0] + attribute \src "build/ls180/gateware/ls180.v:2412.11-2412.47" + wire width 2 $1\builder_sync_rhs_array_muxed0[1:0] + attribute \src "build/ls180/gateware/ls180.v:2413.12-2413.49" + wire width 13 $1\builder_sync_rhs_array_muxed1[12:0] + attribute \src "build/ls180/gateware/ls180.v:2414.5-2414.41" + wire $1\builder_sync_rhs_array_muxed2[0:0] + attribute \src "build/ls180/gateware/ls180.v:2415.5-2415.41" + wire $1\builder_sync_rhs_array_muxed3[0:0] + attribute \src "build/ls180/gateware/ls180.v:2416.5-2416.41" + wire $1\builder_sync_rhs_array_muxed4[0:0] + attribute \src "build/ls180/gateware/ls180.v:2417.5-2417.41" + wire $1\builder_sync_rhs_array_muxed5[0:0] + attribute \src "build/ls180/gateware/ls180.v:2418.5-2418.41" + wire $1\builder_sync_rhs_array_muxed6[0:0] + attribute \src "build/ls180/gateware/ls180.v:1610.12-1610.44" + wire width 16 $1\libresocsim_clk_divider1[15:0] + attribute \src "build/ls180/gateware/ls180.v:1605.5-1605.34" + wire $1\libresocsim_clk_enable[0:0] + attribute \src "build/ls180/gateware/ls180.v:947.5-947.36" + wire $1\libresocsim_clocker_clk0[0:0] + attribute \src "build/ls180/gateware/ls180.v:950.5-950.36" + wire $1\libresocsim_clocker_clk1[0:0] + attribute \src "build/ls180/gateware/ls180.v:951.5-951.37" + wire $1\libresocsim_clocker_clk_d[0:0] + attribute \src "build/ls180/gateware/ls180.v:949.11-949.42" + wire width 9 $1\libresocsim_clocker_clks[8:0] + attribute \src "build/ls180/gateware/ls180.v:945.5-945.34" + wire $1\libresocsim_clocker_re[0:0] + attribute \src "build/ls180/gateware/ls180.v:944.11-944.47" + wire width 9 $1\libresocsim_clocker_storage[8:0] + attribute \src "build/ls180/gateware/ls180.v:1053.5-1053.50" + wire $1\libresocsim_cmdr_cmdr_buf_source_first[0:0] + attribute \src "build/ls180/gateware/ls180.v:1054.5-1054.49" + wire $1\libresocsim_cmdr_cmdr_buf_source_last[0:0] + attribute \src "build/ls180/gateware/ls180.v:1055.11-1055.63" + wire width 8 $1\libresocsim_cmdr_cmdr_buf_source_payload_data[7:0] + attribute \src "build/ls180/gateware/ls180.v:1051.5-1051.50" + wire $1\libresocsim_cmdr_cmdr_buf_source_valid[0:0] + attribute \src "build/ls180/gateware/ls180.v:1038.11-1038.55" + wire width 3 $1\libresocsim_cmdr_cmdr_converter_demux[2:0] + attribute \src "build/ls180/gateware/ls180.v:1034.5-1034.56" + wire $1\libresocsim_cmdr_cmdr_converter_source_first[0:0] + attribute \src "build/ls180/gateware/ls180.v:1035.5-1035.55" + wire $1\libresocsim_cmdr_cmdr_converter_source_last[0:0] + attribute \src "build/ls180/gateware/ls180.v:1036.11-1036.69" + wire width 8 $1\libresocsim_cmdr_cmdr_converter_source_payload_data[7:0] + attribute \src "build/ls180/gateware/ls180.v:1037.11-1037.82" + wire width 4 $1\libresocsim_cmdr_cmdr_converter_source_payload_valid_token_count[3:0] + attribute \src "build/ls180/gateware/ls180.v:1040.5-1040.54" + wire $1\libresocsim_cmdr_cmdr_converter_strobe_all[0:0] + attribute \src "build/ls180/gateware/ls180.v:1056.5-1056.39" + wire $1\libresocsim_cmdr_cmdr_reset[0:0] + attribute \src "build/ls180/gateware/ls180.v:1681.5-1681.67" + wire $1\libresocsim_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value2[0:0] + attribute \src "build/ls180/gateware/ls180.v:1682.5-1682.70" + wire $1\libresocsim_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value_ce2[0:0] + attribute \src "build/ls180/gateware/ls180.v:1026.5-1026.37" + wire $1\libresocsim_cmdr_cmdr_run[0:0] + attribute \src "build/ls180/gateware/ls180.v:1021.5-1021.54" + wire $1\libresocsim_cmdr_cmdr_source_source_ready0[0:0] + attribute \src "build/ls180/gateware/ls180.v:1008.11-1008.40" + wire width 8 $1\libresocsim_cmdr_count[7:0] + attribute \src "build/ls180/gateware/ls180.v:1677.11-1677.68" + wire width 8 $1\libresocsim_cmdr_count_sdphy_sdphycmdr_next_value0[7:0] + attribute \src "build/ls180/gateware/ls180.v:1678.5-1678.65" + wire $1\libresocsim_cmdr_count_sdphy_sdphycmdr_next_value_ce0[0:0] + attribute \src "build/ls180/gateware/ls180.v:993.5-993.49" + wire $1\libresocsim_cmdr_pads_out_payload_clk[0:0] + attribute \src "build/ls180/gateware/ls180.v:994.5-994.51" + wire $1\libresocsim_cmdr_pads_out_payload_cmd_o[0:0] + attribute \src "build/ls180/gateware/ls180.v:995.5-995.52" + wire $1\libresocsim_cmdr_pads_out_payload_cmd_oe[0:0] + attribute \src "build/ls180/gateware/ls180.v:1000.5-1000.38" + wire $1\libresocsim_cmdr_sink_last[0:0] + attribute \src "build/ls180/gateware/ls180.v:1001.11-1001.54" + wire width 8 $1\libresocsim_cmdr_sink_payload_length[7:0] + attribute \src "build/ls180/gateware/ls180.v:999.5-999.39" + wire $1\libresocsim_cmdr_sink_ready[0:0] + attribute \src "build/ls180/gateware/ls180.v:998.5-998.39" + wire $1\libresocsim_cmdr_sink_valid[0:0] + attribute \src "build/ls180/gateware/ls180.v:1004.5-1004.40" + wire $1\libresocsim_cmdr_source_last[0:0] + attribute \src "build/ls180/gateware/ls180.v:1005.11-1005.54" + wire width 8 $1\libresocsim_cmdr_source_payload_data[7:0] + attribute \src "build/ls180/gateware/ls180.v:1006.11-1006.56" + wire width 3 $1\libresocsim_cmdr_source_payload_status[2:0] + attribute \src "build/ls180/gateware/ls180.v:1003.5-1003.41" + wire $1\libresocsim_cmdr_source_ready[0:0] + attribute \src "build/ls180/gateware/ls180.v:1002.5-1002.41" + wire $1\libresocsim_cmdr_source_valid[0:0] + attribute \src "build/ls180/gateware/ls180.v:1007.12-1007.49" + wire width 32 $1\libresocsim_cmdr_timeout[31:0] + attribute \src "build/ls180/gateware/ls180.v:1679.12-1679.72" + wire width 32 $1\libresocsim_cmdr_timeout_sdphy_sdphycmdr_next_value1[31:0] + attribute \src "build/ls180/gateware/ls180.v:1680.5-1680.67" + wire $1\libresocsim_cmdr_timeout_sdphy_sdphycmdr_next_value_ce1[0:0] + attribute \src "build/ls180/gateware/ls180.v:980.11-980.40" + wire width 8 $1\libresocsim_cmdw_count[7:0] + attribute \src "build/ls180/gateware/ls180.v:1673.11-1673.67" + wire width 8 $1\libresocsim_cmdw_count_sdphy_sdphycmdw_next_value[7:0] + attribute \src "build/ls180/gateware/ls180.v:1674.5-1674.64" + wire $1\libresocsim_cmdw_count_sdphy_sdphycmdw_next_value_ce[0:0] + attribute \src "build/ls180/gateware/ls180.v:979.5-979.33" + wire $1\libresocsim_cmdw_done[0:0] + attribute \src "build/ls180/gateware/ls180.v:970.5-970.49" + wire $1\libresocsim_cmdw_pads_out_payload_clk[0:0] + attribute \src "build/ls180/gateware/ls180.v:971.5-971.51" + wire $1\libresocsim_cmdw_pads_out_payload_cmd_o[0:0] + attribute \src "build/ls180/gateware/ls180.v:972.5-972.52" + wire $1\libresocsim_cmdw_pads_out_payload_cmd_oe[0:0] + attribute \src "build/ls180/gateware/ls180.v:977.5-977.38" + wire $1\libresocsim_cmdw_sink_last[0:0] + attribute \src "build/ls180/gateware/ls180.v:978.11-978.52" + wire width 8 $1\libresocsim_cmdw_sink_payload_data[7:0] + attribute \src "build/ls180/gateware/ls180.v:976.5-976.39" + wire $1\libresocsim_cmdw_sink_ready[0:0] + attribute \src "build/ls180/gateware/ls180.v:975.5-975.39" + wire $1\libresocsim_cmdw_sink_valid[0:0] + attribute \src "build/ls180/gateware/ls180.v:1592.5-1592.34" + wire $1\libresocsim_control_re[0:0] + attribute \src "build/ls180/gateware/ls180.v:1591.12-1591.47" + wire width 16 $1\libresocsim_control_storage[15:0] + attribute \src "build/ls180/gateware/ls180.v:1607.11-1607.35" + wire width 3 $1\libresocsim_count[2:0] + attribute \src "build/ls180/gateware/ls180.v:1745.11-1745.57" + wire width 3 $1\libresocsim_count_spimaster1_next_value[2:0] + attribute \src "build/ls180/gateware/ls180.v:1746.5-1746.54" + wire $1\libresocsim_count_spimaster1_next_value_ce[0:0] + attribute \src "build/ls180/gateware/ls180.v:1606.5-1606.33" + wire $1\libresocsim_cs_enable[0:0] + attribute \src "build/ls180/gateware/ls180.v:1602.5-1602.29" + wire $1\libresocsim_cs_re[0:0] + attribute \src "build/ls180/gateware/ls180.v:1601.5-1601.34" + wire $1\libresocsim_cs_storage[0:0] + attribute \src "build/ls180/gateware/ls180.v:1164.11-1164.42" + wire width 10 $1\libresocsim_datar_count[9:0] + attribute \src "build/ls180/gateware/ls180.v:1693.11-1693.71" + wire width 10 $1\libresocsim_datar_count_sdphy_sdphydatar_next_value0[9:0] + attribute \src "build/ls180/gateware/ls180.v:1694.5-1694.67" + wire $1\libresocsim_datar_count_sdphy_sdphydatar_next_value_ce0[0:0] + attribute \src "build/ls180/gateware/ls180.v:1209.5-1209.52" + wire $1\libresocsim_datar_datar_buf_source_first[0:0] + attribute \src "build/ls180/gateware/ls180.v:1210.5-1210.51" + wire $1\libresocsim_datar_datar_buf_source_last[0:0] + attribute \src "build/ls180/gateware/ls180.v:1211.11-1211.65" + wire width 8 $1\libresocsim_datar_datar_buf_source_payload_data[7:0] + attribute \src "build/ls180/gateware/ls180.v:1207.5-1207.52" + wire $1\libresocsim_datar_datar_buf_source_valid[0:0] + attribute \src "build/ls180/gateware/ls180.v:1194.5-1194.51" + wire $1\libresocsim_datar_datar_converter_demux[0:0] + attribute \src "build/ls180/gateware/ls180.v:1190.5-1190.58" + wire $1\libresocsim_datar_datar_converter_source_first[0:0] + attribute \src "build/ls180/gateware/ls180.v:1191.5-1191.57" + wire $1\libresocsim_datar_datar_converter_source_last[0:0] + attribute \src "build/ls180/gateware/ls180.v:1192.11-1192.71" + wire width 8 $1\libresocsim_datar_datar_converter_source_payload_data[7:0] + attribute \src "build/ls180/gateware/ls180.v:1193.11-1193.84" + wire width 2 $1\libresocsim_datar_datar_converter_source_payload_valid_token_count[1:0] + attribute \src "build/ls180/gateware/ls180.v:1196.5-1196.56" + wire $1\libresocsim_datar_datar_converter_strobe_all[0:0] + attribute \src "build/ls180/gateware/ls180.v:1212.5-1212.41" + wire $1\libresocsim_datar_datar_reset[0:0] + attribute \src "build/ls180/gateware/ls180.v:1697.5-1697.70" + wire $1\libresocsim_datar_datar_reset_sdphy_sdphydatar_next_value2[0:0] + attribute \src "build/ls180/gateware/ls180.v:1698.5-1698.73" + wire $1\libresocsim_datar_datar_reset_sdphy_sdphydatar_next_value_ce2[0:0] + attribute \src "build/ls180/gateware/ls180.v:1182.5-1182.39" + wire $1\libresocsim_datar_datar_run[0:0] + attribute \src "build/ls180/gateware/ls180.v:1177.5-1177.56" + wire $1\libresocsim_datar_datar_source_source_ready0[0:0] + attribute \src "build/ls180/gateware/ls180.v:1147.5-1147.50" + wire $1\libresocsim_datar_pads_out_payload_clk[0:0] + attribute \src "build/ls180/gateware/ls180.v:1154.5-1154.39" + wire $1\libresocsim_datar_sink_last[0:0] + attribute \src "build/ls180/gateware/ls180.v:1155.11-1155.62" + wire width 10 $1\libresocsim_datar_sink_payload_block_length[9:0] + attribute \src "build/ls180/gateware/ls180.v:1153.5-1153.40" + wire $1\libresocsim_datar_sink_ready[0:0] + attribute \src "build/ls180/gateware/ls180.v:1152.5-1152.40" + wire $1\libresocsim_datar_sink_valid[0:0] + attribute \src "build/ls180/gateware/ls180.v:1159.5-1159.41" + wire $1\libresocsim_datar_source_last[0:0] + attribute \src "build/ls180/gateware/ls180.v:1160.11-1160.55" + wire width 8 $1\libresocsim_datar_source_payload_data[7:0] + attribute \src "build/ls180/gateware/ls180.v:1161.11-1161.57" + wire width 3 $1\libresocsim_datar_source_payload_status[2:0] + attribute \src "build/ls180/gateware/ls180.v:1157.5-1157.42" + wire $1\libresocsim_datar_source_ready[0:0] + attribute \src "build/ls180/gateware/ls180.v:1156.5-1156.42" + wire $1\libresocsim_datar_source_valid[0:0] + attribute \src "build/ls180/gateware/ls180.v:1162.5-1162.34" + wire $1\libresocsim_datar_stop[0:0] + attribute \src "build/ls180/gateware/ls180.v:1163.12-1163.50" + wire width 32 $1\libresocsim_datar_timeout[31:0] + attribute \src "build/ls180/gateware/ls180.v:1695.12-1695.74" + wire width 32 $1\libresocsim_datar_timeout_sdphy_sdphydatar_next_value1[31:0] + attribute \src "build/ls180/gateware/ls180.v:1696.5-1696.69" + wire $1\libresocsim_datar_timeout_sdphy_sdphydatar_next_value_ce1[0:0] + attribute \src "build/ls180/gateware/ls180.v:1072.11-1072.41" + wire width 8 $1\libresocsim_dataw_count[7:0] + attribute \src "build/ls180/gateware/ls180.v:1689.11-1689.62" + wire width 8 $1\libresocsim_dataw_count_sdphy_fsm_next_value[7:0] + attribute \src "build/ls180/gateware/ls180.v:1690.5-1690.59" + wire $1\libresocsim_dataw_count_sdphy_fsm_next_value_ce[0:0] + attribute \src "build/ls180/gateware/ls180.v:1131.5-1131.51" + wire $1\libresocsim_dataw_crcr_buf_source_first[0:0] + attribute \src "build/ls180/gateware/ls180.v:1132.5-1132.50" + wire $1\libresocsim_dataw_crcr_buf_source_last[0:0] + attribute \src "build/ls180/gateware/ls180.v:1133.11-1133.64" + wire width 8 $1\libresocsim_dataw_crcr_buf_source_payload_data[7:0] + attribute \src "build/ls180/gateware/ls180.v:1129.5-1129.51" + wire $1\libresocsim_dataw_crcr_buf_source_valid[0:0] + attribute \src "build/ls180/gateware/ls180.v:1116.11-1116.56" + wire width 3 $1\libresocsim_dataw_crcr_converter_demux[2:0] + attribute \src "build/ls180/gateware/ls180.v:1112.5-1112.57" + wire $1\libresocsim_dataw_crcr_converter_source_first[0:0] + attribute \src "build/ls180/gateware/ls180.v:1113.5-1113.56" + wire $1\libresocsim_dataw_crcr_converter_source_last[0:0] + attribute \src "build/ls180/gateware/ls180.v:1114.11-1114.70" + wire width 8 $1\libresocsim_dataw_crcr_converter_source_payload_data[7:0] + attribute \src "build/ls180/gateware/ls180.v:1115.11-1115.83" + wire width 4 $1\libresocsim_dataw_crcr_converter_source_payload_valid_token_count[3:0] + attribute \src "build/ls180/gateware/ls180.v:1118.5-1118.55" + wire $1\libresocsim_dataw_crcr_converter_strobe_all[0:0] + attribute \src "build/ls180/gateware/ls180.v:1134.5-1134.40" + wire $1\libresocsim_dataw_crcr_reset[0:0] + attribute \src "build/ls180/gateware/ls180.v:1685.5-1685.67" + wire $1\libresocsim_dataw_crcr_reset_sdphy_sdphycrcr_next_value[0:0] + attribute \src "build/ls180/gateware/ls180.v:1686.5-1686.70" + wire $1\libresocsim_dataw_crcr_reset_sdphy_sdphycrcr_next_value_ce[0:0] + attribute \src "build/ls180/gateware/ls180.v:1104.5-1104.38" + wire $1\libresocsim_dataw_crcr_run[0:0] + attribute \src "build/ls180/gateware/ls180.v:1099.5-1099.55" + wire $1\libresocsim_dataw_crcr_source_source_ready0[0:0] + attribute \src "build/ls180/gateware/ls180.v:1086.5-1086.35" + wire $1\libresocsim_dataw_error[0:0] + attribute \src "build/ls180/gateware/ls180.v:1061.5-1061.50" + wire $1\libresocsim_dataw_pads_out_payload_clk[0:0] + attribute \src "build/ls180/gateware/ls180.v:1064.11-1064.59" + wire width 4 $1\libresocsim_dataw_pads_out_payload_data_o[3:0] + attribute \src "build/ls180/gateware/ls180.v:1065.5-1065.54" + wire $1\libresocsim_dataw_pads_out_payload_data_oe[0:0] + attribute \src "build/ls180/gateware/ls180.v:1068.5-1068.40" + wire $1\libresocsim_dataw_sink_first[0:0] + attribute \src "build/ls180/gateware/ls180.v:1069.5-1069.39" + wire $1\libresocsim_dataw_sink_last[0:0] + attribute \src "build/ls180/gateware/ls180.v:1070.11-1070.53" + wire width 8 $1\libresocsim_dataw_sink_payload_data[7:0] + attribute \src "build/ls180/gateware/ls180.v:1067.5-1067.40" + wire $1\libresocsim_dataw_sink_ready[0:0] + attribute \src "build/ls180/gateware/ls180.v:1066.5-1066.40" + wire $1\libresocsim_dataw_sink_valid[0:0] + attribute \src "build/ls180/gateware/ls180.v:1084.5-1084.35" + wire $1\libresocsim_dataw_start[0:0] + attribute \src "build/ls180/gateware/ls180.v:1071.5-1071.34" + wire $1\libresocsim_dataw_stop[0:0] + attribute \src "build/ls180/gateware/ls180.v:1085.5-1085.35" + wire $1\libresocsim_dataw_valid[0:0] + attribute \src "build/ls180/gateware/ls180.v:1582.5-1582.29" + wire $1\libresocsim_done0[0:0] + attribute \src "build/ls180/gateware/ls180.v:965.11-965.40" + wire width 8 $1\libresocsim_init_count[7:0] + attribute \src "build/ls180/gateware/ls180.v:1669.11-1669.67" + wire width 8 $1\libresocsim_init_count_sdphy_sdphyinit_next_value[7:0] + attribute \src "build/ls180/gateware/ls180.v:1670.5-1670.64" + wire $1\libresocsim_init_count_sdphy_sdphyinit_next_value_ce[0:0] + attribute \src "build/ls180/gateware/ls180.v:960.5-960.49" + wire $1\libresocsim_init_pads_out_payload_clk[0:0] + attribute \src "build/ls180/gateware/ls180.v:961.5-961.51" + wire $1\libresocsim_init_pads_out_payload_cmd_o[0:0] + attribute \src "build/ls180/gateware/ls180.v:962.5-962.52" + wire $1\libresocsim_init_pads_out_payload_cmd_oe[0:0] + attribute \src "build/ls180/gateware/ls180.v:963.11-963.58" + wire width 4 $1\libresocsim_init_pads_out_payload_data_o[3:0] + attribute \src "build/ls180/gateware/ls180.v:964.5-964.53" + wire $1\libresocsim_init_pads_out_payload_data_oe[0:0] + attribute \src "build/ls180/gateware/ls180.v:1486.12-1486.50" + wire width 32 $1\libresocsim_interface1_bus_adr[31:0] + attribute \src "build/ls180/gateware/ls180.v:1490.5-1490.42" + wire $1\libresocsim_interface1_bus_cyc[0:0] + attribute \src "build/ls180/gateware/ls180.v:1489.11-1489.48" + wire width 4 $1\libresocsim_interface1_bus_sel[3:0] + attribute \src "build/ls180/gateware/ls180.v:1491.5-1491.42" + wire $1\libresocsim_interface1_bus_stb[0:0] + attribute \src "build/ls180/gateware/ls180.v:1493.5-1493.41" + wire $1\libresocsim_interface1_bus_we[0:0] + attribute \src "build/ls180/gateware/ls180.v:1583.5-1583.27" + wire $1\libresocsim_irq[0:0] + attribute \src "build/ls180/gateware/ls180.v:1604.5-1604.35" + wire $1\libresocsim_loopback_re[0:0] + attribute \src "build/ls180/gateware/ls180.v:1603.5-1603.40" + wire $1\libresocsim_loopback_storage[0:0] + attribute \src "build/ls180/gateware/ls180.v:1585.11-1585.34" + wire width 8 $1\libresocsim_miso[7:0] + attribute \src "build/ls180/gateware/ls180.v:1615.11-1615.39" + wire width 8 $1\libresocsim_miso_data[7:0] + attribute \src "build/ls180/gateware/ls180.v:1609.5-1609.34" + wire $1\libresocsim_miso_latch[0:0] + attribute \src "build/ls180/gateware/ls180.v:1613.11-1613.39" + wire width 8 $1\libresocsim_mosi_data[7:0] + attribute \src "build/ls180/gateware/ls180.v:1608.5-1608.34" + wire $1\libresocsim_mosi_latch[0:0] + attribute \src "build/ls180/gateware/ls180.v:1597.5-1597.31" + wire $1\libresocsim_mosi_re[0:0] + attribute \src "build/ls180/gateware/ls180.v:1614.11-1614.38" + wire width 3 $1\libresocsim_mosi_sel[2:0] + attribute \src "build/ls180/gateware/ls180.v:1596.11-1596.42" + wire width 8 $1\libresocsim_mosi_storage[7:0] + attribute \src "build/ls180/gateware/ls180.v:1617.5-1617.26" + wire $1\libresocsim_re[0:0] + attribute \src "build/ls180/gateware/ls180.v:1455.11-1455.57" + wire width 2 $1\libresocsim_sdblock2mem_converter_demux[1:0] + attribute \src "build/ls180/gateware/ls180.v:1451.5-1451.58" + wire $1\libresocsim_sdblock2mem_converter_source_first[0:0] + attribute \src "build/ls180/gateware/ls180.v:1452.5-1452.57" + wire $1\libresocsim_sdblock2mem_converter_source_last[0:0] + attribute \src "build/ls180/gateware/ls180.v:1453.12-1453.73" + wire width 32 $1\libresocsim_sdblock2mem_converter_source_payload_data[31:0] + attribute \src "build/ls180/gateware/ls180.v:1454.11-1454.84" + wire width 3 $1\libresocsim_sdblock2mem_converter_source_payload_valid_token_count[2:0] + attribute \src "build/ls180/gateware/ls180.v:1457.5-1457.56" + wire $1\libresocsim_sdblock2mem_converter_strobe_all[0:0] + attribute \src "build/ls180/gateware/ls180.v:1430.11-1430.54" + wire width 5 $1\libresocsim_sdblock2mem_fifo_consume[4:0] + attribute \src "build/ls180/gateware/ls180.v:1427.11-1427.52" + wire width 6 $1\libresocsim_sdblock2mem_fifo_level[5:0] + attribute \src "build/ls180/gateware/ls180.v:1429.11-1429.54" + wire width 5 $1\libresocsim_sdblock2mem_fifo_produce[4:0] + attribute \src "build/ls180/gateware/ls180.v:1431.11-1431.57" + wire width 5 $1\libresocsim_sdblock2mem_fifo_wrport_adr[4:0] + attribute \src "build/ls180/gateware/ls180.v:1465.12-1465.69" + wire width 32 $1\libresocsim_sdblock2mem_sink_sink_payload_address[31:0] + attribute \src "build/ls180/gateware/ls180.v:1466.12-1466.67" + wire width 32 $1\libresocsim_sdblock2mem_sink_sink_payload_data1[31:0] + attribute \src "build/ls180/gateware/ls180.v:1463.5-1463.52" + wire $1\libresocsim_sdblock2mem_sink_sink_valid1[0:0] + attribute \src "build/ls180/gateware/ls180.v:1473.5-1473.61" + wire $1\libresocsim_sdblock2mem_wishbonedmawriter_base_re[0:0] + attribute \src "build/ls180/gateware/ls180.v:1472.12-1472.74" + wire width 64 $1\libresocsim_sdblock2mem_wishbonedmawriter_base_storage[63:0] + attribute \src "build/ls180/gateware/ls180.v:1477.5-1477.63" + wire $1\libresocsim_sdblock2mem_wishbonedmawriter_enable_re[0:0] + attribute \src "build/ls180/gateware/ls180.v:1476.5-1476.68" + wire $1\libresocsim_sdblock2mem_wishbonedmawriter_enable_storage[0:0] + attribute \src "build/ls180/gateware/ls180.v:1475.5-1475.63" + wire $1\libresocsim_sdblock2mem_wishbonedmawriter_length_re[0:0] + attribute \src "build/ls180/gateware/ls180.v:1474.12-1474.76" + wire width 32 $1\libresocsim_sdblock2mem_wishbonedmawriter_length_storage[31:0] + attribute \src "build/ls180/gateware/ls180.v:1481.5-1481.61" + wire $1\libresocsim_sdblock2mem_wishbonedmawriter_loop_re[0:0] + attribute \src "build/ls180/gateware/ls180.v:1480.5-1480.66" + wire $1\libresocsim_sdblock2mem_wishbonedmawriter_loop_storage[0:0] + attribute \src "build/ls180/gateware/ls180.v:1483.12-1483.68" + wire width 32 $1\libresocsim_sdblock2mem_wishbonedmawriter_offset[31:0] + attribute \src "build/ls180/gateware/ls180.v:1733.12-1733.94" + wire width 32 $1\libresocsim_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value[31:0] + attribute \src "build/ls180/gateware/ls180.v:1734.5-1734.89" + wire $1\libresocsim_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value_ce[0:0] + attribute \src "build/ls180/gateware/ls180.v:1468.5-1468.64" + wire $1\libresocsim_sdblock2mem_wishbonedmawriter_sink_ready[0:0] + attribute \src "build/ls180/gateware/ls180.v:1478.5-1478.60" + wire $1\libresocsim_sdblock2mem_wishbonedmawriter_status[0:0] + attribute \src "build/ls180/gateware/ls180.v:1247.5-1247.45" + wire $1\libresocsim_sdcore_block_count_re[0:0] + attribute \src "build/ls180/gateware/ls180.v:1246.12-1246.58" + wire width 32 $1\libresocsim_sdcore_block_count_storage[31:0] + attribute \src "build/ls180/gateware/ls180.v:1245.5-1245.46" + wire $1\libresocsim_sdcore_block_length_re[0:0] + attribute \src "build/ls180/gateware/ls180.v:1244.11-1244.58" + wire width 10 $1\libresocsim_sdcore_block_length_storage[9:0] + attribute \src "build/ls180/gateware/ls180.v:1231.5-1231.46" + wire $1\libresocsim_sdcore_cmd_argument_re[0:0] + attribute \src "build/ls180/gateware/ls180.v:1230.12-1230.59" + wire width 32 $1\libresocsim_sdcore_cmd_argument_storage[31:0] + attribute \src "build/ls180/gateware/ls180.v:1233.5-1233.45" + wire $1\libresocsim_sdcore_cmd_command_re[0:0] + attribute \src "build/ls180/gateware/ls180.v:1232.12-1232.58" + wire width 32 $1\libresocsim_sdcore_cmd_command_storage[31:0] + attribute \src "build/ls180/gateware/ls180.v:1386.11-1386.46" + wire width 3 $1\libresocsim_sdcore_cmd_count[2:0] + attribute \src "build/ls180/gateware/ls180.v:1717.11-1717.69" + wire width 3 $1\libresocsim_sdcore_cmd_count_sdcore_fsm_next_value2[2:0] + attribute \src "build/ls180/gateware/ls180.v:1718.5-1718.66" + wire $1\libresocsim_sdcore_cmd_count_sdcore_fsm_next_value_ce2[0:0] + attribute \src "build/ls180/gateware/ls180.v:1387.5-1387.39" + wire $1\libresocsim_sdcore_cmd_done[0:0] + attribute \src "build/ls180/gateware/ls180.v:1713.5-1713.62" + wire $1\libresocsim_sdcore_cmd_done_sdcore_fsm_next_value0[0:0] + attribute \src "build/ls180/gateware/ls180.v:1714.5-1714.65" + wire $1\libresocsim_sdcore_cmd_done_sdcore_fsm_next_value_ce0[0:0] + attribute \src "build/ls180/gateware/ls180.v:1388.5-1388.40" + wire $1\libresocsim_sdcore_cmd_error[0:0] + attribute \src "build/ls180/gateware/ls180.v:1721.5-1721.63" + wire $1\libresocsim_sdcore_cmd_error_sdcore_fsm_next_value4[0:0] + attribute \src "build/ls180/gateware/ls180.v:1722.5-1722.66" + wire $1\libresocsim_sdcore_cmd_error_sdcore_fsm_next_value_ce4[0:0] + attribute \src "build/ls180/gateware/ls180.v:1238.13-1238.60" + wire width 128 $1\libresocsim_sdcore_cmd_response_status[127:0] + attribute \src "build/ls180/gateware/ls180.v:1729.13-1729.83" + wire width 128 $1\libresocsim_sdcore_cmd_response_status_sdcore_fsm_next_value8[127:0] + attribute \src "build/ls180/gateware/ls180.v:1730.5-1730.76" + wire $1\libresocsim_sdcore_cmd_response_status_sdcore_fsm_next_value_ce8[0:0] + attribute \src "build/ls180/gateware/ls180.v:1389.5-1389.42" + wire $1\libresocsim_sdcore_cmd_timeout[0:0] + attribute \src "build/ls180/gateware/ls180.v:1723.5-1723.65" + wire $1\libresocsim_sdcore_cmd_timeout_sdcore_fsm_next_value5[0:0] + attribute \src "build/ls180/gateware/ls180.v:1724.5-1724.68" + wire $1\libresocsim_sdcore_cmd_timeout_sdcore_fsm_next_value_ce5[0:0] + attribute \src "build/ls180/gateware/ls180.v:1347.11-1347.54" + wire width 4 $1\libresocsim_sdcore_crc16_checker_cnt[3:0] + attribute \src "build/ls180/gateware/ls180.v:1353.5-1353.53" + wire $1\libresocsim_sdcore_crc16_checker_crc0_clr[0:0] + attribute \src "build/ls180/gateware/ls180.v:1352.12-1352.61" + wire width 16 $1\libresocsim_sdcore_crc16_checker_crc0_crc[15:0] + attribute \src "build/ls180/gateware/ls180.v:1348.12-1348.65" + wire width 16 $1\libresocsim_sdcore_crc16_checker_crc0_crcreg0[15:0] + attribute \src "build/ls180/gateware/ls180.v:1360.5-1360.53" + wire $1\libresocsim_sdcore_crc16_checker_crc1_clr[0:0] + attribute \src "build/ls180/gateware/ls180.v:1359.12-1359.61" + wire width 16 $1\libresocsim_sdcore_crc16_checker_crc1_crc[15:0] + attribute \src "build/ls180/gateware/ls180.v:1355.12-1355.65" + wire width 16 $1\libresocsim_sdcore_crc16_checker_crc1_crcreg0[15:0] + attribute \src "build/ls180/gateware/ls180.v:1367.5-1367.53" + wire $1\libresocsim_sdcore_crc16_checker_crc2_clr[0:0] + attribute \src "build/ls180/gateware/ls180.v:1366.12-1366.61" + wire width 16 $1\libresocsim_sdcore_crc16_checker_crc2_crc[15:0] + attribute \src "build/ls180/gateware/ls180.v:1362.12-1362.65" + wire width 16 $1\libresocsim_sdcore_crc16_checker_crc2_crcreg0[15:0] + attribute \src "build/ls180/gateware/ls180.v:1374.5-1374.53" + wire $1\libresocsim_sdcore_crc16_checker_crc3_clr[0:0] + attribute \src "build/ls180/gateware/ls180.v:1373.12-1373.61" + wire width 16 $1\libresocsim_sdcore_crc16_checker_crc3_crc[15:0] + attribute \src "build/ls180/gateware/ls180.v:1369.12-1369.65" + wire width 16 $1\libresocsim_sdcore_crc16_checker_crc3_crcreg0[15:0] + attribute \src "build/ls180/gateware/ls180.v:1376.12-1376.60" + wire width 16 $1\libresocsim_sdcore_crc16_checker_crctmp0[15:0] + attribute \src "build/ls180/gateware/ls180.v:1377.12-1377.60" + wire width 16 $1\libresocsim_sdcore_crc16_checker_crctmp1[15:0] + attribute \src "build/ls180/gateware/ls180.v:1378.12-1378.60" + wire width 16 $1\libresocsim_sdcore_crc16_checker_crctmp2[15:0] + attribute \src "build/ls180/gateware/ls180.v:1379.12-1379.60" + wire width 16 $1\libresocsim_sdcore_crc16_checker_crctmp3[15:0] + attribute \src "build/ls180/gateware/ls180.v:1381.12-1381.58" + wire width 16 $1\libresocsim_sdcore_crc16_checker_fifo0[15:0] + attribute \src "build/ls180/gateware/ls180.v:1382.12-1382.58" + wire width 16 $1\libresocsim_sdcore_crc16_checker_fifo1[15:0] + attribute \src "build/ls180/gateware/ls180.v:1383.12-1383.58" + wire width 16 $1\libresocsim_sdcore_crc16_checker_fifo2[15:0] + attribute \src "build/ls180/gateware/ls180.v:1384.12-1384.58" + wire width 16 $1\libresocsim_sdcore_crc16_checker_fifo3[15:0] + attribute \src "build/ls180/gateware/ls180.v:1338.5-1338.55" + wire $1\libresocsim_sdcore_crc16_checker_sink_first[0:0] + attribute \src "build/ls180/gateware/ls180.v:1339.5-1339.54" + wire $1\libresocsim_sdcore_crc16_checker_sink_last[0:0] + attribute \src "build/ls180/gateware/ls180.v:1340.11-1340.68" + wire width 8 $1\libresocsim_sdcore_crc16_checker_sink_payload_data[7:0] + attribute \src "build/ls180/gateware/ls180.v:1337.5-1337.55" + wire $1\libresocsim_sdcore_crc16_checker_sink_ready[0:0] + attribute \src "build/ls180/gateware/ls180.v:1336.5-1336.55" + wire $1\libresocsim_sdcore_crc16_checker_sink_valid[0:0] + attribute \src "build/ls180/gateware/ls180.v:1341.5-1341.57" + wire $1\libresocsim_sdcore_crc16_checker_source_valid[0:0] + attribute \src "build/ls180/gateware/ls180.v:1346.11-1346.54" + wire width 8 $1\libresocsim_sdcore_crc16_checker_val[7:0] + attribute \src "build/ls180/gateware/ls180.v:1380.5-1380.50" + wire $1\libresocsim_sdcore_crc16_checker_valid[0:0] + attribute \src "build/ls180/gateware/ls180.v:1303.11-1303.55" + wire width 3 $1\libresocsim_sdcore_crc16_inserter_cnt[2:0] + attribute \src "build/ls180/gateware/ls180.v:1709.11-1709.94" + wire width 3 $1\libresocsim_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value4[2:0] + attribute \src "build/ls180/gateware/ls180.v:1710.5-1710.91" + wire $1\libresocsim_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value_ce4[0:0] + attribute \src "build/ls180/gateware/ls180.v:1308.12-1308.62" + wire width 16 $1\libresocsim_sdcore_crc16_inserter_crc0_crc[15:0] + attribute \src "build/ls180/gateware/ls180.v:1304.12-1304.66" + wire width 16 $1\libresocsim_sdcore_crc16_inserter_crc0_crcreg0[15:0] + attribute \src "build/ls180/gateware/ls180.v:1315.12-1315.62" + wire width 16 $1\libresocsim_sdcore_crc16_inserter_crc1_crc[15:0] + attribute \src "build/ls180/gateware/ls180.v:1311.12-1311.66" + wire width 16 $1\libresocsim_sdcore_crc16_inserter_crc1_crcreg0[15:0] + attribute \src "build/ls180/gateware/ls180.v:1322.12-1322.62" + wire width 16 $1\libresocsim_sdcore_crc16_inserter_crc2_crc[15:0] + attribute \src "build/ls180/gateware/ls180.v:1318.12-1318.66" + wire width 16 $1\libresocsim_sdcore_crc16_inserter_crc2_crcreg0[15:0] + attribute \src "build/ls180/gateware/ls180.v:1329.12-1329.62" + wire width 16 $1\libresocsim_sdcore_crc16_inserter_crc3_crc[15:0] + attribute \src "build/ls180/gateware/ls180.v:1325.12-1325.66" + wire width 16 $1\libresocsim_sdcore_crc16_inserter_crc3_crcreg0[15:0] + attribute \src "build/ls180/gateware/ls180.v:1332.12-1332.61" + wire width 16 $1\libresocsim_sdcore_crc16_inserter_crctmp0[15:0] + attribute \src "build/ls180/gateware/ls180.v:1701.12-1701.100" + wire width 16 $1\libresocsim_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value0[15:0] + attribute \src "build/ls180/gateware/ls180.v:1702.5-1702.95" + wire $1\libresocsim_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value_ce0[0:0] + attribute \src "build/ls180/gateware/ls180.v:1333.12-1333.61" + wire width 16 $1\libresocsim_sdcore_crc16_inserter_crctmp1[15:0] + attribute \src "build/ls180/gateware/ls180.v:1703.12-1703.100" + wire width 16 $1\libresocsim_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value1[15:0] + attribute \src "build/ls180/gateware/ls180.v:1704.5-1704.95" + wire $1\libresocsim_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value_ce1[0:0] + attribute \src "build/ls180/gateware/ls180.v:1334.12-1334.61" + wire width 16 $1\libresocsim_sdcore_crc16_inserter_crctmp2[15:0] + attribute \src "build/ls180/gateware/ls180.v:1705.12-1705.100" + wire width 16 $1\libresocsim_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value2[15:0] + attribute \src "build/ls180/gateware/ls180.v:1706.5-1706.95" + wire $1\libresocsim_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value_ce2[0:0] + attribute \src "build/ls180/gateware/ls180.v:1335.12-1335.61" + wire width 16 $1\libresocsim_sdcore_crc16_inserter_crctmp3[15:0] + attribute \src "build/ls180/gateware/ls180.v:1707.12-1707.100" + wire width 16 $1\libresocsim_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value3[15:0] + attribute \src "build/ls180/gateware/ls180.v:1708.5-1708.95" + wire $1\libresocsim_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value_ce3[0:0] + attribute \src "build/ls180/gateware/ls180.v:1294.5-1294.56" + wire $1\libresocsim_sdcore_crc16_inserter_sink_ready[0:0] + attribute \src "build/ls180/gateware/ls180.v:1301.5-1301.57" + wire $1\libresocsim_sdcore_crc16_inserter_source_last[0:0] + attribute \src "build/ls180/gateware/ls180.v:1302.11-1302.71" + wire width 8 $1\libresocsim_sdcore_crc16_inserter_source_payload_data[7:0] + attribute \src "build/ls180/gateware/ls180.v:1299.5-1299.58" + wire $1\libresocsim_sdcore_crc16_inserter_source_ready[0:0] + attribute \src "build/ls180/gateware/ls180.v:1298.5-1298.58" + wire $1\libresocsim_sdcore_crc16_inserter_source_valid[0:0] + attribute \src "build/ls180/gateware/ls180.v:1290.11-1290.54" + wire width 7 $1\libresocsim_sdcore_crc7_inserter_crc[6:0] + attribute \src "build/ls180/gateware/ls180.v:1248.11-1248.58" + wire width 7 $1\libresocsim_sdcore_crc7_inserter_crcreg0[6:0] + attribute \src "build/ls180/gateware/ls180.v:1391.12-1391.49" + wire width 32 $1\libresocsim_sdcore_data_count[31:0] + attribute \src "build/ls180/gateware/ls180.v:1719.12-1719.72" + wire width 32 $1\libresocsim_sdcore_data_count_sdcore_fsm_next_value3[31:0] + attribute \src "build/ls180/gateware/ls180.v:1720.5-1720.67" + wire $1\libresocsim_sdcore_data_count_sdcore_fsm_next_value_ce3[0:0] + attribute \src "build/ls180/gateware/ls180.v:1392.5-1392.40" + wire $1\libresocsim_sdcore_data_done[0:0] + attribute \src "build/ls180/gateware/ls180.v:1715.5-1715.63" + wire $1\libresocsim_sdcore_data_done_sdcore_fsm_next_value1[0:0] + attribute \src "build/ls180/gateware/ls180.v:1716.5-1716.66" + wire $1\libresocsim_sdcore_data_done_sdcore_fsm_next_value_ce1[0:0] + attribute \src "build/ls180/gateware/ls180.v:1393.5-1393.41" + wire $1\libresocsim_sdcore_data_error[0:0] + attribute \src "build/ls180/gateware/ls180.v:1725.5-1725.64" + wire $1\libresocsim_sdcore_data_error_sdcore_fsm_next_value6[0:0] + attribute \src "build/ls180/gateware/ls180.v:1726.5-1726.67" + wire $1\libresocsim_sdcore_data_error_sdcore_fsm_next_value_ce6[0:0] + attribute \src "build/ls180/gateware/ls180.v:1394.5-1394.43" + wire $1\libresocsim_sdcore_data_timeout[0:0] + attribute \src "build/ls180/gateware/ls180.v:1727.5-1727.66" + wire $1\libresocsim_sdcore_data_timeout_sdcore_fsm_next_value7[0:0] + attribute \src "build/ls180/gateware/ls180.v:1728.5-1728.69" + wire $1\libresocsim_sdcore_data_timeout_sdcore_fsm_next_value_ce7[0:0] + attribute \src "build/ls180/gateware/ls180.v:1539.11-1539.55" + wire width 2 $1\libresocsim_sdmem2block_converter_mux[1:0] + attribute \src "build/ls180/gateware/ls180.v:1537.11-1537.71" + wire width 8 $1\libresocsim_sdmem2block_converter_source_payload_data[7:0] + attribute \src "build/ls180/gateware/ls180.v:1513.5-1513.47" + wire $1\libresocsim_sdmem2block_dma_base_re[0:0] + attribute \src "build/ls180/gateware/ls180.v:1512.12-1512.60" + wire width 64 $1\libresocsim_sdmem2block_dma_base_storage[63:0] + attribute \src "build/ls180/gateware/ls180.v:1511.12-1511.52" + wire width 32 $1\libresocsim_sdmem2block_dma_data[31:0] + attribute \src "build/ls180/gateware/ls180.v:1737.12-1737.82" + wire width 32 $1\libresocsim_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value[31:0] + attribute \src "build/ls180/gateware/ls180.v:1738.5-1738.77" + wire $1\libresocsim_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value_ce[0:0] + attribute \src "build/ls180/gateware/ls180.v:1518.5-1518.51" + wire $1\libresocsim_sdmem2block_dma_done_status[0:0] + attribute \src "build/ls180/gateware/ls180.v:1517.5-1517.49" + wire $1\libresocsim_sdmem2block_dma_enable_re[0:0] + attribute \src "build/ls180/gateware/ls180.v:1516.5-1516.54" + wire $1\libresocsim_sdmem2block_dma_enable_storage[0:0] + attribute \src "build/ls180/gateware/ls180.v:1515.5-1515.49" + wire $1\libresocsim_sdmem2block_dma_length_re[0:0] + attribute \src "build/ls180/gateware/ls180.v:1514.12-1514.62" + wire width 32 $1\libresocsim_sdmem2block_dma_length_storage[31:0] + attribute \src "build/ls180/gateware/ls180.v:1521.5-1521.47" + wire $1\libresocsim_sdmem2block_dma_loop_re[0:0] + attribute \src "build/ls180/gateware/ls180.v:1520.5-1520.52" + wire $1\libresocsim_sdmem2block_dma_loop_storage[0:0] + attribute \src "build/ls180/gateware/ls180.v:1525.12-1525.54" + wire width 32 $1\libresocsim_sdmem2block_dma_offset[31:0] + attribute \src "build/ls180/gateware/ls180.v:1741.12-1741.94" + wire width 32 $1\libresocsim_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value[31:0] + attribute \src "build/ls180/gateware/ls180.v:1742.5-1742.89" + wire $1\libresocsim_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value_ce[0:0] + attribute \src "build/ls180/gateware/ls180.v:1504.5-1504.49" + wire $1\libresocsim_sdmem2block_dma_sink_last[0:0] + attribute \src "build/ls180/gateware/ls180.v:1505.12-1505.68" + wire width 32 $1\libresocsim_sdmem2block_dma_sink_payload_address[31:0] + attribute \src "build/ls180/gateware/ls180.v:1503.5-1503.50" + wire $1\libresocsim_sdmem2block_dma_sink_ready[0:0] + attribute \src "build/ls180/gateware/ls180.v:1502.5-1502.50" + wire $1\libresocsim_sdmem2block_dma_sink_valid[0:0] + attribute \src "build/ls180/gateware/ls180.v:1509.5-1509.51" + wire $1\libresocsim_sdmem2block_dma_source_last[0:0] + attribute \src "build/ls180/gateware/ls180.v:1510.12-1510.67" + wire width 32 $1\libresocsim_sdmem2block_dma_source_payload_data[31:0] + attribute \src "build/ls180/gateware/ls180.v:1506.5-1506.52" + wire $1\libresocsim_sdmem2block_dma_source_valid[0:0] + attribute \src "build/ls180/gateware/ls180.v:1566.11-1566.54" + wire width 5 $1\libresocsim_sdmem2block_fifo_consume[4:0] + attribute \src "build/ls180/gateware/ls180.v:1563.11-1563.52" + wire width 6 $1\libresocsim_sdmem2block_fifo_level[5:0] + attribute \src "build/ls180/gateware/ls180.v:1565.11-1565.54" + wire width 5 $1\libresocsim_sdmem2block_fifo_produce[4:0] + attribute \src "build/ls180/gateware/ls180.v:1567.11-1567.57" + wire width 5 $1\libresocsim_sdmem2block_fifo_wrport_adr[4:0] + attribute \src "build/ls180/gateware/ls180.v:1214.5-1214.36" + wire $1\libresocsim_sdpads_cmd_i[0:0] + attribute \src "build/ls180/gateware/ls180.v:1217.11-1217.43" + wire width 4 $1\libresocsim_sdpads_data_i[3:0] + attribute \src "build/ls180/gateware/ls180.v:1589.5-1589.30" + wire $1\libresocsim_start1[0:0] + attribute \src "build/ls180/gateware/ls180.v:1616.12-1616.41" + wire width 16 $1\libresocsim_storage[15:0] + attribute \src "build/ls180/gateware/ls180.v:936.12-936.37" + wire width 16 $1\main_clk_divider1[15:0] + attribute \src "build/ls180/gateware/ls180.v:931.5-931.27" + wire $1\main_clk_enable[0:0] + attribute \src "build/ls180/gateware/ls180.v:897.5-897.29" + wire $1\main_cmd_consumed[0:0] + attribute \src "build/ls180/gateware/ls180.v:918.5-918.27" + wire $1\main_control_re[0:0] + attribute \src "build/ls180/gateware/ls180.v:917.12-917.40" + wire width 16 $1\main_control_storage[15:0] + attribute \src "build/ls180/gateware/ls180.v:894.5-894.34" + wire $1\main_converter_counter[0:0] + attribute \src "build/ls180/gateware/ls180.v:1661.5-1661.55" + wire $1\main_converter_counter_converter_next_value[0:0] + attribute \src "build/ls180/gateware/ls180.v:1662.5-1662.58" + wire $1\main_converter_counter_converter_next_value_ce[0:0] + attribute \src "build/ls180/gateware/ls180.v:896.12-896.40" + wire width 32 $1\main_converter_dat_r[31:0] + attribute \src "build/ls180/gateware/ls180.v:893.5-893.31" + wire $1\main_converter_skip[0:0] + attribute \src "build/ls180/gateware/ls180.v:933.11-933.28" + wire width 3 $1\main_count[2:0] + attribute \src "build/ls180/gateware/ls180.v:1665.11-1665.50" + wire width 3 $1\main_count_spimaster0_next_value[2:0] + attribute \src "build/ls180/gateware/ls180.v:1666.5-1666.47" + wire $1\main_count_spimaster0_next_value_ce[0:0] + attribute \src "build/ls180/gateware/ls180.v:932.5-932.26" + wire $1\main_cs_enable[0:0] + attribute \src "build/ls180/gateware/ls180.v:928.5-928.22" + wire $1\main_cs_re[0:0] + attribute \src "build/ls180/gateware/ls180.v:927.5-927.27" + wire $1\main_cs_storage[0:0] + attribute \src "build/ls180/gateware/ls180.v:328.12-328.38" + wire width 16 $1\main_dfi_p0_rddata[15:0] + attribute \src "build/ls180/gateware/ls180.v:329.5-329.36" + wire $1\main_dfi_p0_rddata_valid[0:0] + attribute \src "build/ls180/gateware/ls180.v:908.5-908.22" + wire $1\main_done0[0:0] + attribute \src "build/ls180/gateware/ls180.v:313.5-313.24" + wire $1\main_int_rst[0:0] + attribute \src "build/ls180/gateware/ls180.v:909.5-909.20" + wire $1\main_irq[0:0] + attribute \src "build/ls180/gateware/ls180.v:108.5-108.47" + wire $1\main_libresocsim_converter0_counter[0:0] + attribute \src "build/ls180/gateware/ls180.v:1620.5-1620.69" + wire $1\main_libresocsim_converter0_counter_converter0_next_value[0:0] + attribute \src "build/ls180/gateware/ls180.v:1621.5-1621.72" + wire $1\main_libresocsim_converter0_counter_converter0_next_value_ce[0:0] + attribute \src "build/ls180/gateware/ls180.v:110.12-110.53" + wire width 64 $1\main_libresocsim_converter0_dat_r[63:0] + attribute \src "build/ls180/gateware/ls180.v:107.5-107.44" + wire $1\main_libresocsim_converter0_skip[0:0] + attribute \src "build/ls180/gateware/ls180.v:123.5-123.47" + wire $1\main_libresocsim_converter1_counter[0:0] + attribute \src "build/ls180/gateware/ls180.v:1624.5-1624.69" + wire $1\main_libresocsim_converter1_counter_converter1_next_value[0:0] + attribute \src "build/ls180/gateware/ls180.v:1625.5-1625.72" + wire $1\main_libresocsim_converter1_counter_converter1_next_value_ce[0:0] + attribute \src "build/ls180/gateware/ls180.v:125.12-125.53" + wire width 64 $1\main_libresocsim_converter1_dat_r[63:0] + attribute \src "build/ls180/gateware/ls180.v:122.5-122.44" + wire $1\main_libresocsim_converter1_skip[0:0] + attribute \src "build/ls180/gateware/ls180.v:96.12-96.71" + wire width 30 $1\main_libresocsim_interface0_converted_interface_adr[29:0] + attribute \src "build/ls180/gateware/ls180.v:100.5-100.63" + wire $1\main_libresocsim_interface0_converted_interface_cyc[0:0] + attribute \src "build/ls180/gateware/ls180.v:97.12-97.73" + wire width 32 $1\main_libresocsim_interface0_converted_interface_dat_w[31:0] + attribute \src "build/ls180/gateware/ls180.v:99.11-99.69" + wire width 4 $1\main_libresocsim_interface0_converted_interface_sel[3:0] + attribute \src "build/ls180/gateware/ls180.v:101.5-101.63" + wire $1\main_libresocsim_interface0_converted_interface_stb[0:0] + attribute \src "build/ls180/gateware/ls180.v:103.5-103.62" + wire $1\main_libresocsim_interface0_converted_interface_we[0:0] + attribute \src "build/ls180/gateware/ls180.v:111.12-111.71" + wire width 30 $1\main_libresocsim_interface1_converted_interface_adr[29:0] + attribute \src "build/ls180/gateware/ls180.v:115.5-115.63" + wire $1\main_libresocsim_interface1_converted_interface_cyc[0:0] + attribute \src "build/ls180/gateware/ls180.v:112.12-112.73" + wire width 32 $1\main_libresocsim_interface1_converted_interface_dat_w[31:0] + attribute \src "build/ls180/gateware/ls180.v:114.11-114.69" + wire width 4 $1\main_libresocsim_interface1_converted_interface_sel[3:0] + attribute \src "build/ls180/gateware/ls180.v:116.5-116.63" + wire $1\main_libresocsim_interface1_converted_interface_stb[0:0] + attribute \src "build/ls180/gateware/ls180.v:118.5-118.62" + wire $1\main_libresocsim_interface1_converted_interface_we[0:0] + attribute \src "build/ls180/gateware/ls180.v:50.5-50.46" + wire $1\main_libresocsim_libresoc_dbus_ack[0:0] + attribute \src "build/ls180/gateware/ls180.v:61.5-61.46" + wire $1\main_libresocsim_libresoc_ibus_ack[0:0] + attribute \src "build/ls180/gateware/ls180.v:43.12-43.55" + wire width 16 $1\main_libresocsim_libresoc_interrupt[15:0] + attribute \src "build/ls180/gateware/ls180.v:159.12-159.57" + wire width 32 $1\main_libresocsim_phase_accumulator_rx[31:0] + attribute \src "build/ls180/gateware/ls180.v:149.12-149.57" + wire width 32 $1\main_libresocsim_phase_accumulator_tx[31:0] + attribute \src "build/ls180/gateware/ls180.v:132.5-132.40" + wire $1\main_libresocsim_ram_bus_ack[0:0] + attribute \src "build/ls180/gateware/ls180.v:142.5-142.31" + wire $1\main_libresocsim_re[0:0] + attribute \src "build/ls180/gateware/ls180.v:163.11-163.46" + wire width 4 $1\main_libresocsim_rx_bitcount[3:0] + attribute \src "build/ls180/gateware/ls180.v:164.5-164.36" + wire $1\main_libresocsim_rx_busy[0:0] + attribute \src "build/ls180/gateware/ls180.v:161.5-161.33" + wire $1\main_libresocsim_rx_r[0:0] + attribute \src "build/ls180/gateware/ls180.v:162.11-162.41" + wire width 8 $1\main_libresocsim_rx_reg[7:0] + attribute \src "build/ls180/gateware/ls180.v:144.5-144.39" + wire $1\main_libresocsim_sink_ready[0:0] + attribute \src "build/ls180/gateware/ls180.v:41.12-41.61" + wire width 32 $1\main_libresocsim_soccontroller_bus_errors[31:0] + attribute \src "build/ls180/gateware/ls180.v:34.5-34.51" + wire $1\main_libresocsim_soccontroller_reset_re[0:0] + attribute \src "build/ls180/gateware/ls180.v:33.5-33.56" + wire $1\main_libresocsim_soccontroller_reset_storage[0:0] + attribute \src "build/ls180/gateware/ls180.v:36.5-36.53" + wire $1\main_libresocsim_soccontroller_scratch_re[0:0] + attribute \src "build/ls180/gateware/ls180.v:35.12-35.74" + wire width 32 $1\main_libresocsim_soccontroller_scratch_storage[31:0] + attribute \src "build/ls180/gateware/ls180.v:157.11-157.54" + wire width 8 $1\main_libresocsim_source_payload_data[7:0] + attribute \src "build/ls180/gateware/ls180.v:153.5-153.41" + wire $1\main_libresocsim_source_valid[0:0] + attribute \src "build/ls180/gateware/ls180.v:141.12-141.50" + wire width 32 $1\main_libresocsim_storage[31:0] + attribute \src "build/ls180/gateware/ls180.v:288.5-288.40" + wire $1\main_libresocsim_timer_en_re[0:0] + attribute \src "build/ls180/gateware/ls180.v:287.5-287.45" + wire $1\main_libresocsim_timer_en_storage[0:0] + attribute \src "build/ls180/gateware/ls180.v:308.5-308.50" + wire $1\main_libresocsim_timer_eventmanager_re[0:0] + attribute \src "build/ls180/gateware/ls180.v:307.5-307.55" + wire $1\main_libresocsim_timer_eventmanager_storage[0:0] + attribute \src "build/ls180/gateware/ls180.v:284.5-284.42" + wire $1\main_libresocsim_timer_load_re[0:0] + attribute \src "build/ls180/gateware/ls180.v:283.12-283.55" + wire width 32 $1\main_libresocsim_timer_load_storage[31:0] + attribute \src "build/ls180/gateware/ls180.v:286.5-286.44" + wire $1\main_libresocsim_timer_reload_re[0:0] + attribute \src "build/ls180/gateware/ls180.v:285.12-285.57" + wire width 32 $1\main_libresocsim_timer_reload_storage[31:0] + attribute \src "build/ls180/gateware/ls180.v:290.5-290.50" + wire $1\main_libresocsim_timer_update_value_re[0:0] + attribute \src "build/ls180/gateware/ls180.v:289.5-289.55" + wire $1\main_libresocsim_timer_update_value_storage[0:0] + attribute \src "build/ls180/gateware/ls180.v:309.12-309.48" + wire width 32 $1\main_libresocsim_timer_value[31:0] + attribute \src "build/ls180/gateware/ls180.v:291.12-291.55" + wire width 32 $1\main_libresocsim_timer_value_status[31:0] + attribute \src "build/ls180/gateware/ls180.v:297.5-297.45" + wire $1\main_libresocsim_timer_zero_clear[0:0] + attribute \src "build/ls180/gateware/ls180.v:298.5-298.51" + wire $1\main_libresocsim_timer_zero_old_trigger[0:0] + attribute \src "build/ls180/gateware/ls180.v:295.5-295.47" + wire $1\main_libresocsim_timer_zero_pending[0:0] + attribute \src "build/ls180/gateware/ls180.v:151.11-151.46" + wire width 4 $1\main_libresocsim_tx_bitcount[3:0] + attribute \src "build/ls180/gateware/ls180.v:152.5-152.36" + wire $1\main_libresocsim_tx_busy[0:0] + attribute \src "build/ls180/gateware/ls180.v:150.11-150.41" + wire width 8 $1\main_libresocsim_tx_reg[7:0] + attribute \src "build/ls180/gateware/ls180.v:158.5-158.42" + wire $1\main_libresocsim_uart_clk_rxen[0:0] + attribute \src "build/ls180/gateware/ls180.v:148.5-148.42" + wire $1\main_libresocsim_uart_clk_txen[0:0] + attribute \src "build/ls180/gateware/ls180.v:191.11-191.62" + wire width 2 $1\main_libresocsim_uart_eventmanager_pending_w[1:0] + attribute \src "build/ls180/gateware/ls180.v:193.5-193.49" + wire $1\main_libresocsim_uart_eventmanager_re[0:0] + attribute \src "build/ls180/gateware/ls180.v:187.11-187.61" + wire width 2 $1\main_libresocsim_uart_eventmanager_status_w[1:0] + attribute \src "build/ls180/gateware/ls180.v:192.11-192.60" + wire width 2 $1\main_libresocsim_uart_eventmanager_storage[1:0] + attribute \src "build/ls180/gateware/ls180.v:182.5-182.42" + wire $1\main_libresocsim_uart_rx_clear[0:0] + attribute \src "build/ls180/gateware/ls180.v:266.11-266.55" + wire width 4 $1\main_libresocsim_uart_rx_fifo_consume[3:0] + attribute \src "build/ls180/gateware/ls180.v:263.11-263.54" + wire width 5 $1\main_libresocsim_uart_rx_fifo_level0[4:0] + attribute \src "build/ls180/gateware/ls180.v:265.11-265.55" + wire width 4 $1\main_libresocsim_uart_rx_fifo_produce[3:0] + attribute \src "build/ls180/gateware/ls180.v:256.5-256.50" + wire $1\main_libresocsim_uart_rx_fifo_readable[0:0] + attribute \src "build/ls180/gateware/ls180.v:267.11-267.58" + wire width 4 $1\main_libresocsim_uart_rx_fifo_wrport_adr[3:0] + attribute \src "build/ls180/gateware/ls180.v:183.5-183.48" + wire $1\main_libresocsim_uart_rx_old_trigger[0:0] + attribute \src "build/ls180/gateware/ls180.v:180.5-180.44" + wire $1\main_libresocsim_uart_rx_pending[0:0] + attribute \src "build/ls180/gateware/ls180.v:177.5-177.42" + wire $1\main_libresocsim_uart_tx_clear[0:0] + attribute \src "build/ls180/gateware/ls180.v:229.11-229.55" + wire width 4 $1\main_libresocsim_uart_tx_fifo_consume[3:0] + attribute \src "build/ls180/gateware/ls180.v:226.11-226.54" + wire width 5 $1\main_libresocsim_uart_tx_fifo_level0[4:0] + attribute \src "build/ls180/gateware/ls180.v:228.11-228.55" + wire width 4 $1\main_libresocsim_uart_tx_fifo_produce[3:0] + attribute \src "build/ls180/gateware/ls180.v:219.5-219.50" + wire $1\main_libresocsim_uart_tx_fifo_readable[0:0] + attribute \src "build/ls180/gateware/ls180.v:230.11-230.58" + wire width 4 $1\main_libresocsim_uart_tx_fifo_wrport_adr[3:0] + attribute \src "build/ls180/gateware/ls180.v:178.5-178.48" + wire $1\main_libresocsim_uart_tx_old_trigger[0:0] + attribute \src "build/ls180/gateware/ls180.v:175.5-175.44" + wire $1\main_libresocsim_uart_tx_pending[0:0] + attribute \src "build/ls180/gateware/ls180.v:139.11-139.37" + wire width 4 $1\main_libresocsim_we[3:0] + attribute \src "build/ls180/gateware/ls180.v:885.12-885.40" + wire width 30 $1\main_litedram_wb_adr[29:0] + attribute \src "build/ls180/gateware/ls180.v:889.5-889.32" + wire $1\main_litedram_wb_cyc[0:0] + attribute \src "build/ls180/gateware/ls180.v:886.12-886.42" + wire width 16 $1\main_litedram_wb_dat_w[15:0] + attribute \src "build/ls180/gateware/ls180.v:888.11-888.38" + wire width 2 $1\main_litedram_wb_sel[1:0] + attribute \src "build/ls180/gateware/ls180.v:890.5-890.32" + wire $1\main_litedram_wb_stb[0:0] + attribute \src "build/ls180/gateware/ls180.v:892.5-892.31" + wire $1\main_litedram_wb_we[0:0] + attribute \src "build/ls180/gateware/ls180.v:930.5-930.28" + wire $1\main_loopback_re[0:0] + attribute \src "build/ls180/gateware/ls180.v:929.5-929.33" + wire $1\main_loopback_storage[0:0] + attribute \src "build/ls180/gateware/ls180.v:911.11-911.27" + wire width 8 $1\main_miso[7:0] + attribute \src "build/ls180/gateware/ls180.v:941.11-941.32" + wire width 8 $1\main_miso_data[7:0] + attribute \src "build/ls180/gateware/ls180.v:935.5-935.27" + wire $1\main_miso_latch[0:0] + attribute \src "build/ls180/gateware/ls180.v:939.11-939.32" + wire width 8 $1\main_mosi_data[7:0] + attribute \src "build/ls180/gateware/ls180.v:934.5-934.27" + wire $1\main_mosi_latch[0:0] + attribute \src "build/ls180/gateware/ls180.v:923.5-923.24" + wire $1\main_mosi_re[0:0] + attribute \src "build/ls180/gateware/ls180.v:940.11-940.31" + wire width 3 $1\main_mosi_sel[2:0] + attribute \src "build/ls180/gateware/ls180.v:922.11-922.35" + wire width 8 $1\main_mosi_storage[7:0] + attribute \src "build/ls180/gateware/ls180.v:330.11-330.32" + wire width 3 $1\main_rddata_en[2:0] + attribute \src "build/ls180/gateware/ls180.v:392.5-392.33" + wire $1\main_sdram_address_re[0:0] + attribute \src "build/ls180/gateware/ls180.v:391.12-391.46" + wire width 13 $1\main_sdram_address_storage[12:0] + attribute \src "build/ls180/gateware/ls180.v:394.5-394.34" + wire $1\main_sdram_baddress_re[0:0] + attribute \src "build/ls180/gateware/ls180.v:393.11-393.45" + wire width 2 $1\main_sdram_baddress_storage[1:0] + attribute \src "build/ls180/gateware/ls180.v:490.5-490.50" + wire $1\main_sdram_bankmachine0_auto_precharge[0:0] + attribute \src "build/ls180/gateware/ls180.v:512.11-512.70" + wire width 3 $1\main_sdram_bankmachine0_cmd_buffer_lookahead_consume[2:0] + attribute \src "build/ls180/gateware/ls180.v:509.11-509.68" + wire width 4 $1\main_sdram_bankmachine0_cmd_buffer_lookahead_level[3:0] + attribute \src "build/ls180/gateware/ls180.v:511.11-511.70" + wire width 3 $1\main_sdram_bankmachine0_cmd_buffer_lookahead_produce[2:0] + attribute \src "build/ls180/gateware/ls180.v:513.11-513.73" + wire width 3 $1\main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr[2:0] + attribute \src "build/ls180/gateware/ls180.v:536.5-536.59" + wire $1\main_sdram_bankmachine0_cmd_buffer_source_first[0:0] + attribute \src "build/ls180/gateware/ls180.v:537.5-537.58" + wire $1\main_sdram_bankmachine0_cmd_buffer_source_last[0:0] + attribute \src "build/ls180/gateware/ls180.v:539.12-539.74" + wire width 22 $1\main_sdram_bankmachine0_cmd_buffer_source_payload_addr[21:0] + attribute \src "build/ls180/gateware/ls180.v:538.5-538.64" + wire $1\main_sdram_bankmachine0_cmd_buffer_source_payload_we[0:0] + attribute \src "build/ls180/gateware/ls180.v:534.5-534.59" + wire $1\main_sdram_bankmachine0_cmd_buffer_source_valid[0:0] + attribute \src "build/ls180/gateware/ls180.v:482.12-482.57" + wire width 13 $1\main_sdram_bankmachine0_cmd_payload_a[12:0] + attribute \src "build/ls180/gateware/ls180.v:484.5-484.51" + wire $1\main_sdram_bankmachine0_cmd_payload_cas[0:0] + attribute \src "build/ls180/gateware/ls180.v:487.5-487.54" + wire $1\main_sdram_bankmachine0_cmd_payload_is_cmd[0:0] + attribute \src "build/ls180/gateware/ls180.v:488.5-488.55" + wire $1\main_sdram_bankmachine0_cmd_payload_is_read[0:0] + attribute \src "build/ls180/gateware/ls180.v:489.5-489.56" + wire $1\main_sdram_bankmachine0_cmd_payload_is_write[0:0] + attribute \src "build/ls180/gateware/ls180.v:485.5-485.51" + wire $1\main_sdram_bankmachine0_cmd_payload_ras[0:0] + attribute \src "build/ls180/gateware/ls180.v:486.5-486.50" + wire $1\main_sdram_bankmachine0_cmd_payload_we[0:0] + attribute \src "build/ls180/gateware/ls180.v:481.5-481.45" + wire $1\main_sdram_bankmachine0_cmd_ready[0:0] + attribute \src "build/ls180/gateware/ls180.v:480.5-480.45" + wire $1\main_sdram_bankmachine0_cmd_valid[0:0] + attribute \src "build/ls180/gateware/ls180.v:479.5-479.47" + wire $1\main_sdram_bankmachine0_refresh_gnt[0:0] + attribute \src "build/ls180/gateware/ls180.v:477.5-477.51" + wire $1\main_sdram_bankmachine0_req_rdata_valid[0:0] + attribute \src "build/ls180/gateware/ls180.v:476.5-476.51" + wire $1\main_sdram_bankmachine0_req_wdata_ready[0:0] + attribute \src "build/ls180/gateware/ls180.v:540.12-540.47" + wire width 13 $1\main_sdram_bankmachine0_row[12:0] + attribute \src "build/ls180/gateware/ls180.v:544.5-544.45" + wire $1\main_sdram_bankmachine0_row_close[0:0] + attribute \src "build/ls180/gateware/ls180.v:545.5-545.54" + wire $1\main_sdram_bankmachine0_row_col_n_addr_sel[0:0] + attribute \src "build/ls180/gateware/ls180.v:543.5-543.44" + wire $1\main_sdram_bankmachine0_row_open[0:0] + attribute \src "build/ls180/gateware/ls180.v:541.5-541.46" + wire $1\main_sdram_bankmachine0_row_opened[0:0] + attribute \src "build/ls180/gateware/ls180.v:548.11-548.55" + wire width 3 $1\main_sdram_bankmachine0_twtpcon_count[2:0] + attribute \src "build/ls180/gateware/ls180.v:547.32-547.76" + wire $1\main_sdram_bankmachine0_twtpcon_ready[0:0] + attribute \src "build/ls180/gateware/ls180.v:572.5-572.50" + wire $1\main_sdram_bankmachine1_auto_precharge[0:0] + attribute \src "build/ls180/gateware/ls180.v:594.11-594.70" + wire width 3 $1\main_sdram_bankmachine1_cmd_buffer_lookahead_consume[2:0] + attribute \src "build/ls180/gateware/ls180.v:591.11-591.68" + wire width 4 $1\main_sdram_bankmachine1_cmd_buffer_lookahead_level[3:0] + attribute \src "build/ls180/gateware/ls180.v:593.11-593.70" + wire width 3 $1\main_sdram_bankmachine1_cmd_buffer_lookahead_produce[2:0] + attribute \src "build/ls180/gateware/ls180.v:595.11-595.73" + wire width 3 $1\main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr[2:0] + attribute \src "build/ls180/gateware/ls180.v:618.5-618.59" + wire $1\main_sdram_bankmachine1_cmd_buffer_source_first[0:0] + attribute \src "build/ls180/gateware/ls180.v:619.5-619.58" + wire $1\main_sdram_bankmachine1_cmd_buffer_source_last[0:0] + attribute \src "build/ls180/gateware/ls180.v:621.12-621.74" + wire width 22 $1\main_sdram_bankmachine1_cmd_buffer_source_payload_addr[21:0] + attribute \src "build/ls180/gateware/ls180.v:620.5-620.64" + wire $1\main_sdram_bankmachine1_cmd_buffer_source_payload_we[0:0] + attribute \src "build/ls180/gateware/ls180.v:616.5-616.59" + wire $1\main_sdram_bankmachine1_cmd_buffer_source_valid[0:0] + attribute \src "build/ls180/gateware/ls180.v:564.12-564.57" + wire width 13 $1\main_sdram_bankmachine1_cmd_payload_a[12:0] + attribute \src "build/ls180/gateware/ls180.v:566.5-566.51" + wire $1\main_sdram_bankmachine1_cmd_payload_cas[0:0] + attribute \src "build/ls180/gateware/ls180.v:569.5-569.54" + wire $1\main_sdram_bankmachine1_cmd_payload_is_cmd[0:0] + attribute \src "build/ls180/gateware/ls180.v:570.5-570.55" + wire $1\main_sdram_bankmachine1_cmd_payload_is_read[0:0] + attribute \src "build/ls180/gateware/ls180.v:571.5-571.56" + wire $1\main_sdram_bankmachine1_cmd_payload_is_write[0:0] + attribute \src "build/ls180/gateware/ls180.v:567.5-567.51" + wire $1\main_sdram_bankmachine1_cmd_payload_ras[0:0] + attribute \src "build/ls180/gateware/ls180.v:568.5-568.50" + wire $1\main_sdram_bankmachine1_cmd_payload_we[0:0] + attribute \src "build/ls180/gateware/ls180.v:563.5-563.45" + wire $1\main_sdram_bankmachine1_cmd_ready[0:0] + attribute \src "build/ls180/gateware/ls180.v:562.5-562.45" + wire $1\main_sdram_bankmachine1_cmd_valid[0:0] + attribute \src "build/ls180/gateware/ls180.v:561.5-561.47" + wire $1\main_sdram_bankmachine1_refresh_gnt[0:0] + attribute \src "build/ls180/gateware/ls180.v:559.5-559.51" + wire $1\main_sdram_bankmachine1_req_rdata_valid[0:0] + attribute \src "build/ls180/gateware/ls180.v:558.5-558.51" + wire $1\main_sdram_bankmachine1_req_wdata_ready[0:0] + attribute \src "build/ls180/gateware/ls180.v:622.12-622.47" + wire width 13 $1\main_sdram_bankmachine1_row[12:0] + attribute \src "build/ls180/gateware/ls180.v:626.5-626.45" + wire $1\main_sdram_bankmachine1_row_close[0:0] + attribute \src "build/ls180/gateware/ls180.v:627.5-627.54" + wire $1\main_sdram_bankmachine1_row_col_n_addr_sel[0:0] + attribute \src "build/ls180/gateware/ls180.v:625.5-625.44" + wire $1\main_sdram_bankmachine1_row_open[0:0] + attribute \src "build/ls180/gateware/ls180.v:623.5-623.46" + wire $1\main_sdram_bankmachine1_row_opened[0:0] + attribute \src "build/ls180/gateware/ls180.v:630.11-630.55" + wire width 3 $1\main_sdram_bankmachine1_twtpcon_count[2:0] + attribute \src "build/ls180/gateware/ls180.v:629.32-629.76" + wire $1\main_sdram_bankmachine1_twtpcon_ready[0:0] + attribute \src "build/ls180/gateware/ls180.v:654.5-654.50" + wire $1\main_sdram_bankmachine2_auto_precharge[0:0] + attribute \src "build/ls180/gateware/ls180.v:676.11-676.70" + wire width 3 $1\main_sdram_bankmachine2_cmd_buffer_lookahead_consume[2:0] + attribute \src "build/ls180/gateware/ls180.v:673.11-673.68" + wire width 4 $1\main_sdram_bankmachine2_cmd_buffer_lookahead_level[3:0] + attribute \src "build/ls180/gateware/ls180.v:675.11-675.70" + wire width 3 $1\main_sdram_bankmachine2_cmd_buffer_lookahead_produce[2:0] + attribute \src "build/ls180/gateware/ls180.v:677.11-677.73" + wire width 3 $1\main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr[2:0] + attribute \src "build/ls180/gateware/ls180.v:700.5-700.59" + wire $1\main_sdram_bankmachine2_cmd_buffer_source_first[0:0] + attribute \src "build/ls180/gateware/ls180.v:701.5-701.58" + wire $1\main_sdram_bankmachine2_cmd_buffer_source_last[0:0] + attribute \src "build/ls180/gateware/ls180.v:703.12-703.74" + wire width 22 $1\main_sdram_bankmachine2_cmd_buffer_source_payload_addr[21:0] + attribute \src "build/ls180/gateware/ls180.v:702.5-702.64" + wire $1\main_sdram_bankmachine2_cmd_buffer_source_payload_we[0:0] + attribute \src "build/ls180/gateware/ls180.v:698.5-698.59" + wire $1\main_sdram_bankmachine2_cmd_buffer_source_valid[0:0] + attribute \src "build/ls180/gateware/ls180.v:646.12-646.57" + wire width 13 $1\main_sdram_bankmachine2_cmd_payload_a[12:0] + attribute \src "build/ls180/gateware/ls180.v:648.5-648.51" + wire $1\main_sdram_bankmachine2_cmd_payload_cas[0:0] + attribute \src "build/ls180/gateware/ls180.v:651.5-651.54" + wire $1\main_sdram_bankmachine2_cmd_payload_is_cmd[0:0] + attribute \src "build/ls180/gateware/ls180.v:652.5-652.55" + wire $1\main_sdram_bankmachine2_cmd_payload_is_read[0:0] + attribute \src "build/ls180/gateware/ls180.v:653.5-653.56" + wire $1\main_sdram_bankmachine2_cmd_payload_is_write[0:0] + attribute \src "build/ls180/gateware/ls180.v:649.5-649.51" + wire $1\main_sdram_bankmachine2_cmd_payload_ras[0:0] + attribute \src "build/ls180/gateware/ls180.v:650.5-650.50" + wire $1\main_sdram_bankmachine2_cmd_payload_we[0:0] + attribute \src "build/ls180/gateware/ls180.v:645.5-645.45" + wire $1\main_sdram_bankmachine2_cmd_ready[0:0] + attribute \src "build/ls180/gateware/ls180.v:644.5-644.45" + wire $1\main_sdram_bankmachine2_cmd_valid[0:0] + attribute \src "build/ls180/gateware/ls180.v:643.5-643.47" + wire $1\main_sdram_bankmachine2_refresh_gnt[0:0] + attribute \src "build/ls180/gateware/ls180.v:641.5-641.51" + wire $1\main_sdram_bankmachine2_req_rdata_valid[0:0] + attribute \src "build/ls180/gateware/ls180.v:640.5-640.51" + wire $1\main_sdram_bankmachine2_req_wdata_ready[0:0] + attribute \src "build/ls180/gateware/ls180.v:704.12-704.47" + wire width 13 $1\main_sdram_bankmachine2_row[12:0] + attribute \src "build/ls180/gateware/ls180.v:708.5-708.45" + wire $1\main_sdram_bankmachine2_row_close[0:0] + attribute \src "build/ls180/gateware/ls180.v:709.5-709.54" + wire $1\main_sdram_bankmachine2_row_col_n_addr_sel[0:0] + attribute \src "build/ls180/gateware/ls180.v:707.5-707.44" + wire $1\main_sdram_bankmachine2_row_open[0:0] + attribute \src "build/ls180/gateware/ls180.v:705.5-705.46" + wire $1\main_sdram_bankmachine2_row_opened[0:0] + attribute \src "build/ls180/gateware/ls180.v:712.11-712.55" + wire width 3 $1\main_sdram_bankmachine2_twtpcon_count[2:0] + attribute \src "build/ls180/gateware/ls180.v:711.32-711.76" + wire $1\main_sdram_bankmachine2_twtpcon_ready[0:0] + attribute \src "build/ls180/gateware/ls180.v:736.5-736.50" + wire $1\main_sdram_bankmachine3_auto_precharge[0:0] + attribute \src "build/ls180/gateware/ls180.v:758.11-758.70" + wire width 3 $1\main_sdram_bankmachine3_cmd_buffer_lookahead_consume[2:0] + attribute \src "build/ls180/gateware/ls180.v:755.11-755.68" + wire width 4 $1\main_sdram_bankmachine3_cmd_buffer_lookahead_level[3:0] + attribute \src "build/ls180/gateware/ls180.v:757.11-757.70" + wire width 3 $1\main_sdram_bankmachine3_cmd_buffer_lookahead_produce[2:0] + attribute \src "build/ls180/gateware/ls180.v:759.11-759.73" + wire width 3 $1\main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr[2:0] + attribute \src "build/ls180/gateware/ls180.v:782.5-782.59" + wire $1\main_sdram_bankmachine3_cmd_buffer_source_first[0:0] + attribute \src "build/ls180/gateware/ls180.v:783.5-783.58" + wire $1\main_sdram_bankmachine3_cmd_buffer_source_last[0:0] + attribute \src "build/ls180/gateware/ls180.v:785.12-785.74" + wire width 22 $1\main_sdram_bankmachine3_cmd_buffer_source_payload_addr[21:0] + attribute \src "build/ls180/gateware/ls180.v:784.5-784.64" + wire $1\main_sdram_bankmachine3_cmd_buffer_source_payload_we[0:0] + attribute \src "build/ls180/gateware/ls180.v:780.5-780.59" + wire $1\main_sdram_bankmachine3_cmd_buffer_source_valid[0:0] + attribute \src "build/ls180/gateware/ls180.v:728.12-728.57" + wire width 13 $1\main_sdram_bankmachine3_cmd_payload_a[12:0] + attribute \src "build/ls180/gateware/ls180.v:730.5-730.51" + wire $1\main_sdram_bankmachine3_cmd_payload_cas[0:0] + attribute \src "build/ls180/gateware/ls180.v:733.5-733.54" + wire $1\main_sdram_bankmachine3_cmd_payload_is_cmd[0:0] + attribute \src "build/ls180/gateware/ls180.v:734.5-734.55" + wire $1\main_sdram_bankmachine3_cmd_payload_is_read[0:0] + attribute \src "build/ls180/gateware/ls180.v:735.5-735.56" + wire $1\main_sdram_bankmachine3_cmd_payload_is_write[0:0] + attribute \src "build/ls180/gateware/ls180.v:731.5-731.51" + wire $1\main_sdram_bankmachine3_cmd_payload_ras[0:0] + attribute \src "build/ls180/gateware/ls180.v:732.5-732.50" + wire $1\main_sdram_bankmachine3_cmd_payload_we[0:0] + attribute \src "build/ls180/gateware/ls180.v:727.5-727.45" + wire $1\main_sdram_bankmachine3_cmd_ready[0:0] + attribute \src "build/ls180/gateware/ls180.v:726.5-726.45" + wire $1\main_sdram_bankmachine3_cmd_valid[0:0] + attribute \src "build/ls180/gateware/ls180.v:725.5-725.47" + wire $1\main_sdram_bankmachine3_refresh_gnt[0:0] + attribute \src "build/ls180/gateware/ls180.v:723.5-723.51" + wire $1\main_sdram_bankmachine3_req_rdata_valid[0:0] + attribute \src "build/ls180/gateware/ls180.v:722.5-722.51" + wire $1\main_sdram_bankmachine3_req_wdata_ready[0:0] + attribute \src "build/ls180/gateware/ls180.v:786.12-786.47" + wire width 13 $1\main_sdram_bankmachine3_row[12:0] + attribute \src "build/ls180/gateware/ls180.v:790.5-790.45" + wire $1\main_sdram_bankmachine3_row_close[0:0] + attribute \src "build/ls180/gateware/ls180.v:791.5-791.54" + wire $1\main_sdram_bankmachine3_row_col_n_addr_sel[0:0] + attribute \src "build/ls180/gateware/ls180.v:789.5-789.44" + wire $1\main_sdram_bankmachine3_row_open[0:0] + attribute \src "build/ls180/gateware/ls180.v:787.5-787.46" + wire $1\main_sdram_bankmachine3_row_opened[0:0] + attribute \src "build/ls180/gateware/ls180.v:794.11-794.55" + wire width 3 $1\main_sdram_bankmachine3_twtpcon_count[2:0] + attribute \src "build/ls180/gateware/ls180.v:793.32-793.76" + wire $1\main_sdram_bankmachine3_twtpcon_ready[0:0] + attribute \src "build/ls180/gateware/ls180.v:809.5-809.49" + wire $1\main_sdram_choose_cmd_cmd_payload_cas[0:0] + attribute \src "build/ls180/gateware/ls180.v:810.5-810.49" + wire $1\main_sdram_choose_cmd_cmd_payload_ras[0:0] + attribute \src "build/ls180/gateware/ls180.v:811.5-811.48" + wire $1\main_sdram_choose_cmd_cmd_payload_we[0:0] + attribute \src "build/ls180/gateware/ls180.v:817.11-817.45" + wire width 2 $1\main_sdram_choose_cmd_grant[1:0] + attribute \src "build/ls180/gateware/ls180.v:815.11-815.46" + wire width 4 $1\main_sdram_choose_cmd_valids[3:0] + attribute \src "build/ls180/gateware/ls180.v:827.5-827.49" + wire $1\main_sdram_choose_req_cmd_payload_cas[0:0] + attribute \src "build/ls180/gateware/ls180.v:828.5-828.49" + wire $1\main_sdram_choose_req_cmd_payload_ras[0:0] + attribute \src "build/ls180/gateware/ls180.v:829.5-829.48" + wire $1\main_sdram_choose_req_cmd_payload_we[0:0] + attribute \src "build/ls180/gateware/ls180.v:824.5-824.43" + wire $1\main_sdram_choose_req_cmd_ready[0:0] + attribute \src "build/ls180/gateware/ls180.v:835.11-835.45" + wire width 2 $1\main_sdram_choose_req_grant[1:0] + attribute \src "build/ls180/gateware/ls180.v:833.11-833.46" + wire width 4 $1\main_sdram_choose_req_valids[3:0] + attribute \src "build/ls180/gateware/ls180.v:822.5-822.48" + wire $1\main_sdram_choose_req_want_activates[0:0] + attribute \src "build/ls180/gateware/ls180.v:819.5-819.44" + wire $1\main_sdram_choose_req_want_reads[0:0] + attribute \src "build/ls180/gateware/ls180.v:820.5-820.45" + wire $1\main_sdram_choose_req_want_writes[0:0] + attribute \src "build/ls180/gateware/ls180.v:448.5-448.31" + wire $1\main_sdram_cmd_last[0:0] + attribute \src "build/ls180/gateware/ls180.v:449.12-449.44" + wire width 13 $1\main_sdram_cmd_payload_a[12:0] + attribute \src "build/ls180/gateware/ls180.v:450.11-450.43" + wire width 2 $1\main_sdram_cmd_payload_ba[1:0] + attribute \src "build/ls180/gateware/ls180.v:451.5-451.38" + wire $1\main_sdram_cmd_payload_cas[0:0] + attribute \src "build/ls180/gateware/ls180.v:452.5-452.38" + wire $1\main_sdram_cmd_payload_ras[0:0] + attribute \src "build/ls180/gateware/ls180.v:453.5-453.37" + wire $1\main_sdram_cmd_payload_we[0:0] + attribute \src "build/ls180/gateware/ls180.v:447.5-447.32" + wire $1\main_sdram_cmd_ready[0:0] + attribute \src "build/ls180/gateware/ls180.v:446.5-446.32" + wire $1\main_sdram_cmd_valid[0:0] + attribute \src "build/ls180/gateware/ls180.v:386.5-386.33" + wire $1\main_sdram_command_re[0:0] + attribute \src "build/ls180/gateware/ls180.v:385.11-385.44" + wire width 6 $1\main_sdram_command_storage[5:0] + attribute \src "build/ls180/gateware/ls180.v:430.12-430.45" + wire width 13 $1\main_sdram_dfi_p0_address[12:0] + attribute \src "build/ls180/gateware/ls180.v:431.11-431.40" + wire width 2 $1\main_sdram_dfi_p0_bank[1:0] + attribute \src "build/ls180/gateware/ls180.v:432.5-432.35" + wire $1\main_sdram_dfi_p0_cas_n[0:0] + attribute \src "build/ls180/gateware/ls180.v:433.5-433.34" + wire $1\main_sdram_dfi_p0_cs_n[0:0] + attribute \src "build/ls180/gateware/ls180.v:434.5-434.35" + wire $1\main_sdram_dfi_p0_ras_n[0:0] + attribute \src "build/ls180/gateware/ls180.v:443.5-443.39" + wire $1\main_sdram_dfi_p0_rddata_en[0:0] + attribute \src "build/ls180/gateware/ls180.v:435.5-435.34" + wire $1\main_sdram_dfi_p0_we_n[0:0] + attribute \src "build/ls180/gateware/ls180.v:441.5-441.39" + wire $1\main_sdram_dfi_p0_wrdata_en[0:0] + attribute \src "build/ls180/gateware/ls180.v:854.5-854.26" + wire $1\main_sdram_en0[0:0] + attribute \src "build/ls180/gateware/ls180.v:857.5-857.26" + wire $1\main_sdram_en1[0:0] + attribute \src "build/ls180/gateware/ls180.v:427.12-427.46" + wire width 16 $1\main_sdram_interface_wdata[15:0] + attribute \src "build/ls180/gateware/ls180.v:428.11-428.47" + wire width 2 $1\main_sdram_interface_wdata_we[1:0] + attribute \src "build/ls180/gateware/ls180.v:333.5-333.36" + wire $1\main_sdram_inti_p0_cas_n[0:0] + attribute \src "build/ls180/gateware/ls180.v:334.5-334.35" + wire $1\main_sdram_inti_p0_cs_n[0:0] + attribute \src "build/ls180/gateware/ls180.v:335.5-335.36" + wire $1\main_sdram_inti_p0_ras_n[0:0] + attribute \src "build/ls180/gateware/ls180.v:345.12-345.45" + wire width 16 $1\main_sdram_inti_p0_rddata[15:0] + attribute \src "build/ls180/gateware/ls180.v:346.5-346.43" + wire $1\main_sdram_inti_p0_rddata_valid[0:0] + attribute \src "build/ls180/gateware/ls180.v:336.5-336.35" + wire $1\main_sdram_inti_p0_we_n[0:0] + attribute \src "build/ls180/gateware/ls180.v:372.5-372.38" + wire $1\main_sdram_master_p0_act_n[0:0] + attribute \src "build/ls180/gateware/ls180.v:363.12-363.48" + wire width 13 $1\main_sdram_master_p0_address[12:0] + attribute \src "build/ls180/gateware/ls180.v:364.11-364.43" + wire width 2 $1\main_sdram_master_p0_bank[1:0] + attribute \src "build/ls180/gateware/ls180.v:365.5-365.38" + wire $1\main_sdram_master_p0_cas_n[0:0] + attribute \src "build/ls180/gateware/ls180.v:369.5-369.36" + wire $1\main_sdram_master_p0_cke[0:0] + attribute \src "build/ls180/gateware/ls180.v:366.5-366.37" + wire $1\main_sdram_master_p0_cs_n[0:0] + attribute \src "build/ls180/gateware/ls180.v:370.5-370.36" + wire $1\main_sdram_master_p0_odt[0:0] + attribute \src "build/ls180/gateware/ls180.v:367.5-367.38" + wire $1\main_sdram_master_p0_ras_n[0:0] + attribute \src "build/ls180/gateware/ls180.v:376.5-376.42" + wire $1\main_sdram_master_p0_rddata_en[0:0] + attribute \src "build/ls180/gateware/ls180.v:371.5-371.40" + wire $1\main_sdram_master_p0_reset_n[0:0] + attribute \src "build/ls180/gateware/ls180.v:368.5-368.37" + wire $1\main_sdram_master_p0_we_n[0:0] + attribute \src "build/ls180/gateware/ls180.v:373.12-373.47" + wire width 16 $1\main_sdram_master_p0_wrdata[15:0] + attribute \src "build/ls180/gateware/ls180.v:374.5-374.42" + wire $1\main_sdram_master_p0_wrdata_en[0:0] + attribute \src "build/ls180/gateware/ls180.v:375.11-375.50" + wire width 2 $1\main_sdram_master_p0_wrdata_mask[1:0] + attribute \src "build/ls180/gateware/ls180.v:464.5-464.38" + wire $1\main_sdram_postponer_count[0:0] + attribute \src "build/ls180/gateware/ls180.v:463.5-463.38" + wire $1\main_sdram_postponer_req_o[0:0] + attribute \src "build/ls180/gateware/ls180.v:384.5-384.25" + wire $1\main_sdram_re[0:0] + attribute \src "build/ls180/gateware/ls180.v:470.5-470.38" + wire $1\main_sdram_sequencer_count[0:0] + attribute \src "build/ls180/gateware/ls180.v:469.11-469.46" + wire width 4 $1\main_sdram_sequencer_counter[3:0] + attribute \src "build/ls180/gateware/ls180.v:468.5-468.38" + wire $1\main_sdram_sequencer_done1[0:0] + attribute \src "build/ls180/gateware/ls180.v:465.5-465.39" + wire $1\main_sdram_sequencer_start0[0:0] + attribute \src "build/ls180/gateware/ls180.v:361.12-361.46" + wire width 16 $1\main_sdram_slave_p0_rddata[15:0] + attribute \src "build/ls180/gateware/ls180.v:362.5-362.44" + wire $1\main_sdram_slave_p0_rddata_valid[0:0] + attribute \src "build/ls180/gateware/ls180.v:397.12-397.37" + wire width 16 $1\main_sdram_status[15:0] + attribute \src "build/ls180/gateware/ls180.v:839.11-839.40" + wire width 2 $1\main_sdram_steerer_sel[1:0] + attribute \src "build/ls180/gateware/ls180.v:383.11-383.36" + wire width 4 $1\main_sdram_storage[3:0] + attribute \src "build/ls180/gateware/ls180.v:848.5-848.36" + wire $1\main_sdram_tccdcon_count[0:0] + attribute \src "build/ls180/gateware/ls180.v:847.32-847.63" + wire $1\main_sdram_tccdcon_ready[0:0] + attribute \src "build/ls180/gateware/ls180.v:856.11-856.34" + wire width 5 $1\main_sdram_time0[4:0] + attribute \src "build/ls180/gateware/ls180.v:859.11-859.34" + wire width 4 $1\main_sdram_time1[3:0] + attribute \src "build/ls180/gateware/ls180.v:461.11-461.44" + wire width 10 $1\main_sdram_timer_count1[9:0] + attribute \src "build/ls180/gateware/ls180.v:851.11-851.42" + wire width 3 $1\main_sdram_twtrcon_count[2:0] + attribute \src "build/ls180/gateware/ls180.v:850.32-850.63" + wire $1\main_sdram_twtrcon_ready[0:0] + attribute \src "build/ls180/gateware/ls180.v:396.5-396.32" + wire $1\main_sdram_wrdata_re[0:0] + attribute \src "build/ls180/gateware/ls180.v:395.12-395.45" + wire width 16 $1\main_sdram_wrdata_storage[15:0] + attribute \src "build/ls180/gateware/ls180.v:915.5-915.23" + wire $1\main_start1[0:0] + attribute \src "build/ls180/gateware/ls180.v:880.5-880.29" + wire $1\main_wb_sdram_ack[0:0] + attribute \src "build/ls180/gateware/ls180.v:898.5-898.31" + wire $1\main_wdata_consumed[0:0] + attribute \src "build/ls180/gateware/ls180.v:2635.68-2635.110" + wire $add$build/ls180/gateware/ls180.v:2635$22_Y + attribute \src "build/ls180/gateware/ls180.v:2695.68-2695.110" + wire $add$build/ls180/gateware/ls180.v:2695$33_Y + attribute \src "build/ls180/gateware/ls180.v:2793.48-2793.125" + wire width 5 $add$build/ls180/gateware/ls180.v:2793$69_Y + attribute \src "build/ls180/gateware/ls180.v:2823.48-2823.125" + wire width 5 $add$build/ls180/gateware/ls180.v:2823$80_Y + attribute \src "build/ls180/gateware/ls180.v:3948.54-3948.83" + wire $add$build/ls180/gateware/ls180.v:3948$566_Y + attribute \src "build/ls180/gateware/ls180.v:4013.42-4013.59" + wire width 3 $add$build/ls180/gateware/ls180.v:4013$597_Y + attribute \src "build/ls180/gateware/ls180.v:4113.59-4113.88" + wire width 8 $add$build/ls180/gateware/ls180.v:4113$625_Y + attribute \src "build/ls180/gateware/ls180.v:4170.59-4170.88" + wire width 8 $add$build/ls180/gateware/ls180.v:4170$628_Y + attribute \src "build/ls180/gateware/ls180.v:4187.59-4187.88" + wire width 8 $add$build/ls180/gateware/ls180.v:4187$630_Y + attribute \src "build/ls180/gateware/ls180.v:4280.60-4280.89" + wire width 8 $add$build/ls180/gateware/ls180.v:4280$647_Y + attribute \src "build/ls180/gateware/ls180.v:4305.60-4305.89" + wire width 8 $add$build/ls180/gateware/ls180.v:4305$650_Y + attribute \src "build/ls180/gateware/ls180.v:4427.54-4427.84" + wire width 8 $add$build/ls180/gateware/ls180.v:4427$667_Y + attribute \src "build/ls180/gateware/ls180.v:4538.67-4538.117" + wire width 10 $add$build/ls180/gateware/ls180.v:4538$681_Y + attribute \src "build/ls180/gateware/ls180.v:4543.63-4543.93" + wire width 10 $add$build/ls180/gateware/ls180.v:4543$684_Y + attribute \src "build/ls180/gateware/ls180.v:4569.62-4569.92" + wire width 10 $add$build/ls180/gateware/ls180.v:4569$687_Y + attribute \src "build/ls180/gateware/ls180.v:4773.87-4773.131" + wire width 3 $add$build/ls180/gateware/ls180.v:4773$872_Y + attribute \src "build/ls180/gateware/ls180.v:4967.61-4967.96" + wire width 3 $add$build/ls180/gateware/ls180.v:4967$947_Y + attribute \src "build/ls180/gateware/ls180.v:5019.62-5019.98" + wire width 32 $add$build/ls180/gateware/ls180.v:5019$957_Y + attribute \src "build/ls180/gateware/ls180.v:5045.64-5045.100" + wire width 32 $add$build/ls180/gateware/ls180.v:5045$965_Y + attribute \src "build/ls180/gateware/ls180.v:5166.58-5166.155" + wire width 32 $add$build/ls180/gateware/ls180.v:5166$981_Y + attribute \src "build/ls180/gateware/ls180.v:5169.84-5169.139" + wire width 32 $add$build/ls180/gateware/ls180.v:5169$983_Y + attribute \src "build/ls180/gateware/ls180.v:5262.57-5262.126" + wire width 32 $add$build/ls180/gateware/ls180.v:5262$992_Y + attribute \src "build/ls180/gateware/ls180.v:5264.84-5264.125" + wire width 32 $add$build/ls180/gateware/ls180.v:5264$993_Y + attribute \src "build/ls180/gateware/ls180.v:5376.49-5376.73" + wire width 3 $add$build/ls180/gateware/ls180.v:5376$1012_Y + attribute \src "build/ls180/gateware/ls180.v:7080.50-7080.98" + wire width 32 $add$build/ls180/gateware/ls180.v:7080$2191_Y + attribute \src "build/ls180/gateware/ls180.v:7095.37-7095.72" + wire width 4 $add$build/ls180/gateware/ls180.v:7095$2200_Y + attribute \src "build/ls180/gateware/ls180.v:7111.79-7111.143" + wire width 33 $add$build/ls180/gateware/ls180.v:7111$2203_Y + attribute \src "build/ls180/gateware/ls180.v:7124.37-7124.72" + wire width 4 $add$build/ls180/gateware/ls180.v:7124$2207_Y + attribute \src "build/ls180/gateware/ls180.v:7143.79-7143.143" + wire width 33 $add$build/ls180/gateware/ls180.v:7143$2210_Y + attribute \src "build/ls180/gateware/ls180.v:7169.45-7169.89" + wire width 4 $add$build/ls180/gateware/ls180.v:7169$2218_Y + attribute \src "build/ls180/gateware/ls180.v:7172.45-7172.89" + wire width 4 $add$build/ls180/gateware/ls180.v:7172$2219_Y + attribute \src "build/ls180/gateware/ls180.v:7176.45-7176.88" + wire width 5 $add$build/ls180/gateware/ls180.v:7176$2224_Y + attribute \src "build/ls180/gateware/ls180.v:7191.45-7191.89" + wire width 4 $add$build/ls180/gateware/ls180.v:7191$2229_Y + attribute \src "build/ls180/gateware/ls180.v:7194.45-7194.89" + wire width 4 $add$build/ls180/gateware/ls180.v:7194$2230_Y + attribute \src "build/ls180/gateware/ls180.v:7198.45-7198.88" + wire width 5 $add$build/ls180/gateware/ls180.v:7198$2235_Y + attribute \src "build/ls180/gateware/ls180.v:7297.37-7297.72" + wire width 4 $add$build/ls180/gateware/ls180.v:7297$2254_Y + attribute \src "build/ls180/gateware/ls180.v:7314.60-7314.119" + wire width 3 $add$build/ls180/gateware/ls180.v:7314$2258_Y + attribute \src "build/ls180/gateware/ls180.v:7317.60-7317.119" + wire width 3 $add$build/ls180/gateware/ls180.v:7317$2259_Y + attribute \src "build/ls180/gateware/ls180.v:7321.59-7321.116" + wire width 4 $add$build/ls180/gateware/ls180.v:7321$2264_Y + attribute \src "build/ls180/gateware/ls180.v:7360.60-7360.119" + wire width 3 $add$build/ls180/gateware/ls180.v:7360$2274_Y + attribute \src "build/ls180/gateware/ls180.v:7363.60-7363.119" + wire width 3 $add$build/ls180/gateware/ls180.v:7363$2275_Y + attribute \src "build/ls180/gateware/ls180.v:7367.59-7367.116" + wire width 4 $add$build/ls180/gateware/ls180.v:7367$2280_Y + attribute \src "build/ls180/gateware/ls180.v:7406.60-7406.119" + wire width 3 $add$build/ls180/gateware/ls180.v:7406$2290_Y + attribute \src "build/ls180/gateware/ls180.v:7409.60-7409.119" + wire width 3 $add$build/ls180/gateware/ls180.v:7409$2291_Y + attribute \src "build/ls180/gateware/ls180.v:7413.59-7413.116" + wire width 4 $add$build/ls180/gateware/ls180.v:7413$2296_Y + attribute \src "build/ls180/gateware/ls180.v:7452.60-7452.119" + wire width 3 $add$build/ls180/gateware/ls180.v:7452$2306_Y + attribute \src "build/ls180/gateware/ls180.v:7455.60-7455.119" + wire width 3 $add$build/ls180/gateware/ls180.v:7455$2307_Y + attribute \src "build/ls180/gateware/ls180.v:7459.59-7459.116" + wire width 4 $add$build/ls180/gateware/ls180.v:7459$2312_Y + attribute \src "build/ls180/gateware/ls180.v:7681.24-7681.48" + wire width 16 $add$build/ls180/gateware/ls180.v:7681$2361_Y + attribute \src "build/ls180/gateware/ls180.v:7717.32-7717.63" + wire width 9 $add$build/ls180/gateware/ls180.v:7717$2367_Y + attribute \src "build/ls180/gateware/ls180.v:7740.46-7740.90" + wire width 3 $add$build/ls180/gateware/ls180.v:7740$2371_Y + attribute \src "build/ls180/gateware/ls180.v:7786.72-7786.116" + wire width 4 $add$build/ls180/gateware/ls180.v:7786$2377_Y + attribute \src "build/ls180/gateware/ls180.v:7821.47-7821.92" + wire width 3 $add$build/ls180/gateware/ls180.v:7821$2383_Y + attribute \src "build/ls180/gateware/ls180.v:7867.73-7867.118" + wire width 4 $add$build/ls180/gateware/ls180.v:7867$2389_Y + attribute \src "build/ls180/gateware/ls180.v:7900.48-7900.94" + wire $add$build/ls180/gateware/ls180.v:7900$2395_Y + attribute \src "build/ls180/gateware/ls180.v:7928.74-7928.120" + wire width 2 $add$build/ls180/gateware/ls180.v:7928$2401_Y + attribute \src "build/ls180/gateware/ls180.v:8040.46-8040.89" + wire width 4 $add$build/ls180/gateware/ls180.v:8040$2414_Y + attribute \src "build/ls180/gateware/ls180.v:8101.44-8101.87" + wire width 5 $add$build/ls180/gateware/ls180.v:8101$2418_Y + attribute \src "build/ls180/gateware/ls180.v:8104.44-8104.87" + wire width 5 $add$build/ls180/gateware/ls180.v:8104$2419_Y + attribute \src "build/ls180/gateware/ls180.v:8108.43-8108.84" + wire width 6 $add$build/ls180/gateware/ls180.v:8108$2424_Y + attribute \src "build/ls180/gateware/ls180.v:8123.48-8123.94" + wire width 2 $add$build/ls180/gateware/ls180.v:8123$2428_Y + attribute \src "build/ls180/gateware/ls180.v:8157.74-8157.120" + wire width 3 $add$build/ls180/gateware/ls180.v:8157$2434_Y + attribute \src "build/ls180/gateware/ls180.v:8183.46-8183.90" + wire width 2 $add$build/ls180/gateware/ls180.v:8183$2436_Y + attribute \src "build/ls180/gateware/ls180.v:8187.44-8187.87" + wire width 5 $add$build/ls180/gateware/ls180.v:8187$2440_Y + attribute \src "build/ls180/gateware/ls180.v:8190.44-8190.87" + wire width 5 $add$build/ls180/gateware/ls180.v:8190$2441_Y + attribute \src "build/ls180/gateware/ls180.v:8194.43-8194.84" + wire width 6 $add$build/ls180/gateware/ls180.v:8194$2446_Y + attribute \src "build/ls180/gateware/ls180.v:8201.31-8201.62" + wire width 16 $add$build/ls180/gateware/ls180.v:8201$2448_Y + attribute \src "build/ls180/gateware/ls180.v:2629.9-2629.80" + wire $and$build/ls180/gateware/ls180.v:2629$17_Y + attribute \src "build/ls180/gateware/ls180.v:2647.9-2647.80" + wire $and$build/ls180/gateware/ls180.v:2647$24_Y + attribute \src "build/ls180/gateware/ls180.v:2689.9-2689.80" + wire $and$build/ls180/gateware/ls180.v:2689$28_Y + attribute \src "build/ls180/gateware/ls180.v:2707.9-2707.80" + wire $and$build/ls180/gateware/ls180.v:2707$35_Y + attribute \src "build/ls180/gateware/ls180.v:2717.31-2717.90" + wire $and$build/ls180/gateware/ls180.v:2717$37_Y + attribute \src "build/ls180/gateware/ls180.v:2717.30-2717.121" + wire $and$build/ls180/gateware/ls180.v:2717$38_Y + attribute \src "build/ls180/gateware/ls180.v:2717.29-2717.156" + wire $and$build/ls180/gateware/ls180.v:2717$39_Y + attribute \src "build/ls180/gateware/ls180.v:2718.31-2718.90" + wire $and$build/ls180/gateware/ls180.v:2718$40_Y + attribute \src "build/ls180/gateware/ls180.v:2718.30-2718.121" + wire $and$build/ls180/gateware/ls180.v:2718$41_Y + attribute \src "build/ls180/gateware/ls180.v:2718.29-2718.156" + wire $and$build/ls180/gateware/ls180.v:2718$42_Y + attribute \src "build/ls180/gateware/ls180.v:2719.31-2719.90" + wire $and$build/ls180/gateware/ls180.v:2719$43_Y + attribute \src "build/ls180/gateware/ls180.v:2719.30-2719.121" + wire $and$build/ls180/gateware/ls180.v:2719$44_Y + attribute \src "build/ls180/gateware/ls180.v:2719.29-2719.156" + wire $and$build/ls180/gateware/ls180.v:2719$45_Y + attribute \src "build/ls180/gateware/ls180.v:2720.31-2720.90" + wire $and$build/ls180/gateware/ls180.v:2720$46_Y + attribute \src "build/ls180/gateware/ls180.v:2720.30-2720.121" + wire $and$build/ls180/gateware/ls180.v:2720$47_Y + attribute \src "build/ls180/gateware/ls180.v:2720.29-2720.156" + wire $and$build/ls180/gateware/ls180.v:2720$48_Y + attribute \src "build/ls180/gateware/ls180.v:2753.88-2753.124" + wire $and$build/ls180/gateware/ls180.v:2753$54_Y + attribute \src "build/ls180/gateware/ls180.v:2757.7-2757.102" + wire $and$build/ls180/gateware/ls180.v:2757$58_Y + attribute \src "build/ls180/gateware/ls180.v:2768.7-2768.102" + wire $and$build/ls180/gateware/ls180.v:2768$61_Y + attribute \src "build/ls180/gateware/ls180.v:2777.38-2777.133" + wire $and$build/ls180/gateware/ls180.v:2777$63_Y + attribute \src "build/ls180/gateware/ls180.v:2777.138-2777.233" + wire $and$build/ls180/gateware/ls180.v:2777$64_Y + attribute \src "build/ls180/gateware/ls180.v:2792.53-2792.181" + wire $and$build/ls180/gateware/ls180.v:2792$68_Y + attribute \src "build/ls180/gateware/ls180.v:2803.51-2803.184" + wire $and$build/ls180/gateware/ls180.v:2803$73_Y + attribute \src "build/ls180/gateware/ls180.v:2804.49-2804.140" + wire $and$build/ls180/gateware/ls180.v:2804$74_Y + attribute \src "build/ls180/gateware/ls180.v:2822.53-2822.181" + wire $and$build/ls180/gateware/ls180.v:2822$79_Y + attribute \src "build/ls180/gateware/ls180.v:2833.51-2833.184" + wire $and$build/ls180/gateware/ls180.v:2833$84_Y + attribute \src "build/ls180/gateware/ls180.v:2834.49-2834.140" + wire $and$build/ls180/gateware/ls180.v:2834$85_Y + attribute \src "build/ls180/gateware/ls180.v:2844.7-2844.101" + wire $and$build/ls180/gateware/ls180.v:2844$90_Y + attribute \src "build/ls180/gateware/ls180.v:2849.38-2849.129" + wire $and$build/ls180/gateware/ls180.v:2849$91_Y + attribute \src "build/ls180/gateware/ls180.v:2968.40-2968.99" + wire $and$build/ls180/gateware/ls180.v:2968$99_Y + attribute \src "build/ls180/gateware/ls180.v:2969.40-2969.99" + wire $and$build/ls180/gateware/ls180.v:2969$100_Y + attribute \src "build/ls180/gateware/ls180.v:3007.38-3007.103" + wire $and$build/ls180/gateware/ls180.v:3007$106_Y + attribute \src "build/ls180/gateware/ls180.v:3061.50-3061.119" + wire $and$build/ls180/gateware/ls180.v:3061$114_Y + attribute \src "build/ls180/gateware/ls180.v:3061.49-3061.167" + wire $and$build/ls180/gateware/ls180.v:3061$115_Y + attribute \src "build/ls180/gateware/ls180.v:3062.49-3062.118" + wire $and$build/ls180/gateware/ls180.v:3062$116_Y + attribute \src "build/ls180/gateware/ls180.v:3062.48-3062.154" + wire $and$build/ls180/gateware/ls180.v:3062$117_Y + attribute \src "build/ls180/gateware/ls180.v:3063.50-3063.119" + wire $and$build/ls180/gateware/ls180.v:3063$118_Y + attribute \src "build/ls180/gateware/ls180.v:3063.49-3063.155" + wire $and$build/ls180/gateware/ls180.v:3063$119_Y + attribute \src "build/ls180/gateware/ls180.v:3066.7-3066.114" + wire $and$build/ls180/gateware/ls180.v:3066$121_Y + attribute \src "build/ls180/gateware/ls180.v:3095.66-3095.246" + wire $and$build/ls180/gateware/ls180.v:3095$127_Y + attribute \src "build/ls180/gateware/ls180.v:3096.64-3096.187" + wire $and$build/ls180/gateware/ls180.v:3096$128_Y + attribute \src "build/ls180/gateware/ls180.v:3120.9-3120.86" + wire $and$build/ls180/gateware/ls180.v:3120$134_Y + attribute \src "build/ls180/gateware/ls180.v:3132.9-3132.86" + wire $and$build/ls180/gateware/ls180.v:3132$135_Y + attribute \src "build/ls180/gateware/ls180.v:3182.13-3182.87" + wire $and$build/ls180/gateware/ls180.v:3182$137_Y + attribute \src "build/ls180/gateware/ls180.v:3218.50-3218.119" + wire $and$build/ls180/gateware/ls180.v:3218$144_Y + attribute \src "build/ls180/gateware/ls180.v:3218.49-3218.167" + wire $and$build/ls180/gateware/ls180.v:3218$145_Y + attribute \src "build/ls180/gateware/ls180.v:3219.49-3219.118" + wire $and$build/ls180/gateware/ls180.v:3219$146_Y + attribute \src "build/ls180/gateware/ls180.v:3219.48-3219.154" + wire $and$build/ls180/gateware/ls180.v:3219$147_Y + attribute \src "build/ls180/gateware/ls180.v:3220.50-3220.119" + wire $and$build/ls180/gateware/ls180.v:3220$148_Y + attribute \src "build/ls180/gateware/ls180.v:3220.49-3220.155" + wire $and$build/ls180/gateware/ls180.v:3220$149_Y + attribute \src "build/ls180/gateware/ls180.v:3223.7-3223.114" + wire $and$build/ls180/gateware/ls180.v:3223$151_Y + attribute \src "build/ls180/gateware/ls180.v:3252.66-3252.246" + wire $and$build/ls180/gateware/ls180.v:3252$157_Y + attribute \src "build/ls180/gateware/ls180.v:3253.64-3253.187" + wire $and$build/ls180/gateware/ls180.v:3253$158_Y + attribute \src "build/ls180/gateware/ls180.v:3277.9-3277.86" + wire $and$build/ls180/gateware/ls180.v:3277$164_Y + attribute \src "build/ls180/gateware/ls180.v:3289.9-3289.86" + wire $and$build/ls180/gateware/ls180.v:3289$165_Y + attribute \src "build/ls180/gateware/ls180.v:3339.13-3339.87" + wire $and$build/ls180/gateware/ls180.v:3339$167_Y + attribute \src "build/ls180/gateware/ls180.v:3375.50-3375.119" + wire $and$build/ls180/gateware/ls180.v:3375$174_Y + attribute \src "build/ls180/gateware/ls180.v:3375.49-3375.167" + wire $and$build/ls180/gateware/ls180.v:3375$175_Y + attribute \src "build/ls180/gateware/ls180.v:3376.49-3376.118" + wire $and$build/ls180/gateware/ls180.v:3376$176_Y + attribute \src "build/ls180/gateware/ls180.v:3376.48-3376.154" + wire $and$build/ls180/gateware/ls180.v:3376$177_Y + attribute \src "build/ls180/gateware/ls180.v:3377.50-3377.119" + wire $and$build/ls180/gateware/ls180.v:3377$178_Y + attribute \src "build/ls180/gateware/ls180.v:3377.49-3377.155" + wire $and$build/ls180/gateware/ls180.v:3377$179_Y + attribute \src "build/ls180/gateware/ls180.v:3380.7-3380.114" + wire $and$build/ls180/gateware/ls180.v:3380$181_Y + attribute \src "build/ls180/gateware/ls180.v:3409.66-3409.246" + wire $and$build/ls180/gateware/ls180.v:3409$187_Y + attribute \src "build/ls180/gateware/ls180.v:3410.64-3410.187" + wire $and$build/ls180/gateware/ls180.v:3410$188_Y + attribute \src "build/ls180/gateware/ls180.v:3434.9-3434.86" + wire $and$build/ls180/gateware/ls180.v:3434$194_Y + attribute \src "build/ls180/gateware/ls180.v:3446.9-3446.86" + wire $and$build/ls180/gateware/ls180.v:3446$195_Y + attribute \src "build/ls180/gateware/ls180.v:3496.13-3496.87" + wire $and$build/ls180/gateware/ls180.v:3496$197_Y + attribute \src "build/ls180/gateware/ls180.v:3532.50-3532.119" + wire $and$build/ls180/gateware/ls180.v:3532$204_Y + attribute \src "build/ls180/gateware/ls180.v:3532.49-3532.167" + wire $and$build/ls180/gateware/ls180.v:3532$205_Y + attribute \src "build/ls180/gateware/ls180.v:3533.49-3533.118" + wire $and$build/ls180/gateware/ls180.v:3533$206_Y + attribute \src "build/ls180/gateware/ls180.v:3533.48-3533.154" + wire $and$build/ls180/gateware/ls180.v:3533$207_Y + attribute \src "build/ls180/gateware/ls180.v:3534.50-3534.119" + wire $and$build/ls180/gateware/ls180.v:3534$208_Y + attribute \src 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attribute \src "build/ls180/gateware/ls180.v:5851.44-5851.100" + wire $and$build/ls180/gateware/ls180.v:5851$1625_Y + attribute \src "build/ls180/gateware/ls180.v:5851.43-5851.150" + wire $and$build/ls180/gateware/ls180.v:5851$1627_Y + attribute \src "build/ls180/gateware/ls180.v:5853.49-5853.102" + wire $and$build/ls180/gateware/ls180.v:5853$1628_Y + attribute \src "build/ls180/gateware/ls180.v:5853.48-5853.152" + wire $and$build/ls180/gateware/ls180.v:5853$1630_Y + attribute \src "build/ls180/gateware/ls180.v:5854.49-5854.105" + wire $and$build/ls180/gateware/ls180.v:5854$1632_Y + attribute \src "build/ls180/gateware/ls180.v:5854.48-5854.155" + wire $and$build/ls180/gateware/ls180.v:5854$1634_Y + attribute \src "build/ls180/gateware/ls180.v:5856.49-5856.102" + wire $and$build/ls180/gateware/ls180.v:5856$1635_Y + attribute \src "build/ls180/gateware/ls180.v:5856.48-5856.152" + wire $and$build/ls180/gateware/ls180.v:5856$1637_Y + attribute \src "build/ls180/gateware/ls180.v:5857.49-5857.105" + wire $and$build/ls180/gateware/ls180.v:5857$1639_Y + attribute \src "build/ls180/gateware/ls180.v:5857.48-5857.155" + wire $and$build/ls180/gateware/ls180.v:5857$1641_Y + attribute \src "build/ls180/gateware/ls180.v:5859.43-5859.96" + wire $and$build/ls180/gateware/ls180.v:5859$1642_Y + attribute \src "build/ls180/gateware/ls180.v:5859.42-5859.146" + wire $and$build/ls180/gateware/ls180.v:5859$1644_Y + attribute \src "build/ls180/gateware/ls180.v:5860.43-5860.99" + wire $and$build/ls180/gateware/ls180.v:5860$1646_Y + attribute \src "build/ls180/gateware/ls180.v:5860.42-5860.149" + wire $and$build/ls180/gateware/ls180.v:5860$1648_Y + attribute \src "build/ls180/gateware/ls180.v:5867.46-5867.99" + wire $and$build/ls180/gateware/ls180.v:5867$1650_Y + attribute \src "build/ls180/gateware/ls180.v:5867.45-5867.149" + wire $and$build/ls180/gateware/ls180.v:5867$1652_Y + attribute \src "build/ls180/gateware/ls180.v:5868.46-5868.102" + wire $and$build/ls180/gateware/ls180.v:5868$1654_Y + attribute \src "build/ls180/gateware/ls180.v:5868.45-5868.152" + wire $and$build/ls180/gateware/ls180.v:5868$1656_Y + attribute \src "build/ls180/gateware/ls180.v:5870.50-5870.103" + wire $and$build/ls180/gateware/ls180.v:5870$1657_Y + attribute \src "build/ls180/gateware/ls180.v:5870.49-5870.153" + wire $and$build/ls180/gateware/ls180.v:5870$1659_Y + attribute \src "build/ls180/gateware/ls180.v:5871.50-5871.106" + wire $and$build/ls180/gateware/ls180.v:5871$1661_Y + attribute \src "build/ls180/gateware/ls180.v:5871.49-5871.156" + wire $and$build/ls180/gateware/ls180.v:5871$1663_Y + attribute \src "build/ls180/gateware/ls180.v:5873.40-5873.93" + wire $and$build/ls180/gateware/ls180.v:5873$1664_Y + attribute \src "build/ls180/gateware/ls180.v:5873.39-5873.143" + wire $and$build/ls180/gateware/ls180.v:5873$1666_Y + attribute \src "build/ls180/gateware/ls180.v:5874.40-5874.96" + wire $and$build/ls180/gateware/ls180.v:5874$1668_Y + attribute \src "build/ls180/gateware/ls180.v:5874.39-5874.146" + wire $and$build/ls180/gateware/ls180.v:5874$1670_Y + attribute \src "build/ls180/gateware/ls180.v:5876.50-5876.103" + wire $and$build/ls180/gateware/ls180.v:5876$1671_Y + attribute \src "build/ls180/gateware/ls180.v:5876.49-5876.153" + wire $and$build/ls180/gateware/ls180.v:5876$1673_Y + attribute \src "build/ls180/gateware/ls180.v:5877.50-5877.106" + wire $and$build/ls180/gateware/ls180.v:5877$1675_Y + attribute \src "build/ls180/gateware/ls180.v:5877.49-5877.156" + wire $and$build/ls180/gateware/ls180.v:5877$1677_Y + attribute \src "build/ls180/gateware/ls180.v:5879.50-5879.103" + wire $and$build/ls180/gateware/ls180.v:5879$1678_Y + attribute \src "build/ls180/gateware/ls180.v:5879.49-5879.153" + wire $and$build/ls180/gateware/ls180.v:5879$1680_Y + attribute \src "build/ls180/gateware/ls180.v:5880.50-5880.106" + wire $and$build/ls180/gateware/ls180.v:5880$1682_Y + attribute \src "build/ls180/gateware/ls180.v:5880.49-5880.156" + wire $and$build/ls180/gateware/ls180.v:5880$1684_Y + attribute \src "build/ls180/gateware/ls180.v:5882.51-5882.104" + wire $and$build/ls180/gateware/ls180.v:5882$1685_Y + attribute \src "build/ls180/gateware/ls180.v:5882.50-5882.154" + wire $and$build/ls180/gateware/ls180.v:5882$1687_Y + attribute \src "build/ls180/gateware/ls180.v:5883.51-5883.107" + wire $and$build/ls180/gateware/ls180.v:5883$1689_Y + attribute \src "build/ls180/gateware/ls180.v:5883.50-5883.157" + wire $and$build/ls180/gateware/ls180.v:5883$1691_Y + attribute \src "build/ls180/gateware/ls180.v:5885.49-5885.102" + wire $and$build/ls180/gateware/ls180.v:5885$1692_Y + attribute \src "build/ls180/gateware/ls180.v:5885.48-5885.152" + wire $and$build/ls180/gateware/ls180.v:5885$1694_Y + attribute \src "build/ls180/gateware/ls180.v:5886.49-5886.105" + wire $and$build/ls180/gateware/ls180.v:5886$1696_Y + attribute \src "build/ls180/gateware/ls180.v:5886.48-5886.155" + wire $and$build/ls180/gateware/ls180.v:5886$1698_Y + attribute \src "build/ls180/gateware/ls180.v:5888.49-5888.102" + wire $and$build/ls180/gateware/ls180.v:5888$1699_Y + attribute \src "build/ls180/gateware/ls180.v:5888.48-5888.152" + wire $and$build/ls180/gateware/ls180.v:5888$1701_Y + attribute \src "build/ls180/gateware/ls180.v:5889.49-5889.105" + wire $and$build/ls180/gateware/ls180.v:5889$1703_Y + attribute \src "build/ls180/gateware/ls180.v:5889.48-5889.155" + wire $and$build/ls180/gateware/ls180.v:5889$1705_Y + attribute \src "build/ls180/gateware/ls180.v:5891.49-5891.102" + wire $and$build/ls180/gateware/ls180.v:5891$1706_Y + attribute \src "build/ls180/gateware/ls180.v:5891.48-5891.152" + wire $and$build/ls180/gateware/ls180.v:5891$1708_Y + attribute \src "build/ls180/gateware/ls180.v:5892.49-5892.105" + wire $and$build/ls180/gateware/ls180.v:5892$1710_Y + attribute \src "build/ls180/gateware/ls180.v:5892.48-5892.155" + wire $and$build/ls180/gateware/ls180.v:5892$1712_Y + attribute \src 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$and$build/ls180/gateware/ls180.v:5915$1728_Y + attribute \src "build/ls180/gateware/ls180.v:5915.40-5915.144" + wire $and$build/ls180/gateware/ls180.v:5915$1730_Y + attribute \src "build/ls180/gateware/ls180.v:5916.41-5916.97" + wire $and$build/ls180/gateware/ls180.v:5916$1732_Y + attribute \src "build/ls180/gateware/ls180.v:5916.40-5916.147" + wire $and$build/ls180/gateware/ls180.v:5916$1734_Y + attribute \src "build/ls180/gateware/ls180.v:5918.39-5918.92" + wire $and$build/ls180/gateware/ls180.v:5918$1735_Y + attribute \src "build/ls180/gateware/ls180.v:5918.38-5918.142" + wire $and$build/ls180/gateware/ls180.v:5918$1737_Y + attribute \src "build/ls180/gateware/ls180.v:5919.39-5919.95" + wire $and$build/ls180/gateware/ls180.v:5919$1739_Y + attribute \src "build/ls180/gateware/ls180.v:5919.38-5919.145" + wire $and$build/ls180/gateware/ls180.v:5919$1741_Y + attribute \src "build/ls180/gateware/ls180.v:5921.38-5921.91" + wire $and$build/ls180/gateware/ls180.v:5921$1742_Y + attribute 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\src "build/ls180/gateware/ls180.v:5953.41-5953.97" + wire $and$build/ls180/gateware/ls180.v:5953$1776_Y + attribute \src "build/ls180/gateware/ls180.v:5953.40-5953.147" + wire $and$build/ls180/gateware/ls180.v:5953$1778_Y + attribute \src "build/ls180/gateware/ls180.v:5955.41-5955.94" + wire $and$build/ls180/gateware/ls180.v:5955$1779_Y + attribute \src "build/ls180/gateware/ls180.v:5955.40-5955.144" + wire $and$build/ls180/gateware/ls180.v:5955$1781_Y + attribute \src "build/ls180/gateware/ls180.v:5956.41-5956.97" + wire $and$build/ls180/gateware/ls180.v:5956$1783_Y + attribute \src "build/ls180/gateware/ls180.v:5956.40-5956.147" + wire $and$build/ls180/gateware/ls180.v:5956$1785_Y + attribute \src "build/ls180/gateware/ls180.v:5958.39-5958.92" + wire $and$build/ls180/gateware/ls180.v:5958$1786_Y + attribute \src "build/ls180/gateware/ls180.v:5958.38-5958.142" + wire $and$build/ls180/gateware/ls180.v:5958$1788_Y + attribute \src "build/ls180/gateware/ls180.v:5959.39-5959.95" + wire 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\src "build/ls180/gateware/ls180.v:5965.36-5965.143" + wire $and$build/ls180/gateware/ls180.v:5965$1806_Y + attribute \src "build/ls180/gateware/ls180.v:5967.36-5967.89" + wire $and$build/ls180/gateware/ls180.v:5967$1807_Y + attribute \src "build/ls180/gateware/ls180.v:5967.35-5967.139" + wire $and$build/ls180/gateware/ls180.v:5967$1809_Y + attribute \src "build/ls180/gateware/ls180.v:5968.36-5968.92" + wire $and$build/ls180/gateware/ls180.v:5968$1811_Y + attribute \src "build/ls180/gateware/ls180.v:5968.35-5968.142" + wire $and$build/ls180/gateware/ls180.v:5968$1813_Y + attribute \src "build/ls180/gateware/ls180.v:5970.42-5970.95" + wire $and$build/ls180/gateware/ls180.v:5970$1814_Y + attribute \src "build/ls180/gateware/ls180.v:5970.41-5970.145" + wire $and$build/ls180/gateware/ls180.v:5970$1816_Y + attribute \src "build/ls180/gateware/ls180.v:5971.42-5971.98" + wire $and$build/ls180/gateware/ls180.v:5971$1818_Y + attribute \src "build/ls180/gateware/ls180.v:5971.41-5971.148" + wire $and$build/ls180/gateware/ls180.v:5971$1820_Y + attribute \src "build/ls180/gateware/ls180.v:5973.45-5973.98" + wire $and$build/ls180/gateware/ls180.v:5973$1821_Y + attribute \src "build/ls180/gateware/ls180.v:5973.44-5973.148" + wire $and$build/ls180/gateware/ls180.v:5973$1823_Y + attribute \src "build/ls180/gateware/ls180.v:5974.45-5974.101" + wire $and$build/ls180/gateware/ls180.v:5974$1825_Y + attribute \src "build/ls180/gateware/ls180.v:5974.44-5974.151" + wire $and$build/ls180/gateware/ls180.v:5974$1827_Y + attribute \src "build/ls180/gateware/ls180.v:5976.45-5976.98" + wire $and$build/ls180/gateware/ls180.v:5976$1828_Y + attribute \src "build/ls180/gateware/ls180.v:5976.44-5976.148" + wire $and$build/ls180/gateware/ls180.v:5976$1830_Y + attribute \src "build/ls180/gateware/ls180.v:5977.45-5977.101" + wire $and$build/ls180/gateware/ls180.v:5977$1832_Y + attribute \src "build/ls180/gateware/ls180.v:5977.44-5977.151" + wire $and$build/ls180/gateware/ls180.v:5977$1834_Y + attribute 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$and$build/ls180/gateware/ls180.v:6006$1851_Y + attribute \src "build/ls180/gateware/ls180.v:6006.38-6006.145" + wire $and$build/ls180/gateware/ls180.v:6006$1853_Y + attribute \src "build/ls180/gateware/ls180.v:6007.39-6007.97" + wire $and$build/ls180/gateware/ls180.v:6007$1855_Y + attribute \src "build/ls180/gateware/ls180.v:6007.38-6007.148" + wire $and$build/ls180/gateware/ls180.v:6007$1857_Y + attribute \src "build/ls180/gateware/ls180.v:6009.39-6009.94" + wire $and$build/ls180/gateware/ls180.v:6009$1858_Y + attribute \src "build/ls180/gateware/ls180.v:6009.38-6009.145" + wire $and$build/ls180/gateware/ls180.v:6009$1860_Y + attribute \src "build/ls180/gateware/ls180.v:6010.39-6010.97" + wire $and$build/ls180/gateware/ls180.v:6010$1862_Y + attribute \src "build/ls180/gateware/ls180.v:6010.38-6010.148" + wire $and$build/ls180/gateware/ls180.v:6010$1864_Y + attribute \src "build/ls180/gateware/ls180.v:6012.41-6012.96" + wire $and$build/ls180/gateware/ls180.v:6012$1865_Y + attribute \src "build/ls180/gateware/ls180.v:6012.40-6012.147" + wire $and$build/ls180/gateware/ls180.v:6012$1867_Y + attribute \src "build/ls180/gateware/ls180.v:6013.41-6013.99" + wire $and$build/ls180/gateware/ls180.v:6013$1869_Y + attribute \src "build/ls180/gateware/ls180.v:6013.40-6013.150" + wire $and$build/ls180/gateware/ls180.v:6013$1871_Y + attribute \src "build/ls180/gateware/ls180.v:6015.41-6015.96" + wire $and$build/ls180/gateware/ls180.v:6015$1872_Y + attribute \src "build/ls180/gateware/ls180.v:6015.40-6015.147" + wire $and$build/ls180/gateware/ls180.v:6015$1874_Y + attribute \src "build/ls180/gateware/ls180.v:6016.41-6016.99" + wire $and$build/ls180/gateware/ls180.v:6016$1876_Y + attribute \src "build/ls180/gateware/ls180.v:6016.40-6016.150" + wire $and$build/ls180/gateware/ls180.v:6016$1878_Y + attribute \src "build/ls180/gateware/ls180.v:6018.41-6018.96" + wire $and$build/ls180/gateware/ls180.v:6018$1879_Y + attribute \src "build/ls180/gateware/ls180.v:6018.40-6018.147" + wire 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$and$build/ls180/gateware/ls180.v:6031$1911_Y + attribute \src "build/ls180/gateware/ls180.v:6031.39-6031.150" + wire $and$build/ls180/gateware/ls180.v:6031$1913_Y + attribute \src "build/ls180/gateware/ls180.v:6033.40-6033.95" + wire $and$build/ls180/gateware/ls180.v:6033$1914_Y + attribute \src "build/ls180/gateware/ls180.v:6033.39-6033.147" + wire $and$build/ls180/gateware/ls180.v:6033$1916_Y + attribute \src "build/ls180/gateware/ls180.v:6034.40-6034.98" + wire $and$build/ls180/gateware/ls180.v:6034$1918_Y + attribute \src "build/ls180/gateware/ls180.v:6034.39-6034.150" + wire $and$build/ls180/gateware/ls180.v:6034$1920_Y + attribute \src "build/ls180/gateware/ls180.v:6036.40-6036.95" + wire $and$build/ls180/gateware/ls180.v:6036$1921_Y + attribute \src "build/ls180/gateware/ls180.v:6036.39-6036.147" + wire $and$build/ls180/gateware/ls180.v:6036$1923_Y + attribute \src "build/ls180/gateware/ls180.v:6037.40-6037.98" + wire $and$build/ls180/gateware/ls180.v:6037$1925_Y + attribute \src "build/ls180/gateware/ls180.v:6037.39-6037.150" + wire $and$build/ls180/gateware/ls180.v:6037$1927_Y + attribute \src "build/ls180/gateware/ls180.v:6039.40-6039.95" + wire $and$build/ls180/gateware/ls180.v:6039$1928_Y + attribute \src "build/ls180/gateware/ls180.v:6039.39-6039.147" + wire $and$build/ls180/gateware/ls180.v:6039$1930_Y + attribute \src "build/ls180/gateware/ls180.v:6040.40-6040.98" + wire $and$build/ls180/gateware/ls180.v:6040$1932_Y + attribute \src "build/ls180/gateware/ls180.v:6040.39-6040.150" + wire $and$build/ls180/gateware/ls180.v:6040$1934_Y + attribute \src "build/ls180/gateware/ls180.v:6042.58-6042.113" + wire $and$build/ls180/gateware/ls180.v:6042$1935_Y + attribute \src "build/ls180/gateware/ls180.v:6042.57-6042.165" + wire $and$build/ls180/gateware/ls180.v:6042$1937_Y + attribute \src "build/ls180/gateware/ls180.v:6043.58-6043.116" + wire $and$build/ls180/gateware/ls180.v:6043$1939_Y + attribute \src "build/ls180/gateware/ls180.v:6043.57-6043.168" + wire $and$build/ls180/gateware/ls180.v:6043$1941_Y + attribute \src "build/ls180/gateware/ls180.v:6045.59-6045.114" + wire $and$build/ls180/gateware/ls180.v:6045$1942_Y + attribute \src "build/ls180/gateware/ls180.v:6045.58-6045.166" + wire $and$build/ls180/gateware/ls180.v:6045$1944_Y + attribute \src "build/ls180/gateware/ls180.v:6046.59-6046.117" + wire $and$build/ls180/gateware/ls180.v:6046$1946_Y + attribute \src "build/ls180/gateware/ls180.v:6046.58-6046.169" + wire $and$build/ls180/gateware/ls180.v:6046$1948_Y + attribute \src "build/ls180/gateware/ls180.v:6048.44-6048.99" + wire $and$build/ls180/gateware/ls180.v:6048$1949_Y + attribute \src "build/ls180/gateware/ls180.v:6048.43-6048.151" + wire $and$build/ls180/gateware/ls180.v:6048$1951_Y + attribute \src "build/ls180/gateware/ls180.v:6049.44-6049.102" + wire $and$build/ls180/gateware/ls180.v:6049$1953_Y + attribute \src "build/ls180/gateware/ls180.v:6049.43-6049.154" + wire $and$build/ls180/gateware/ls180.v:6049$1955_Y + attribute \src "build/ls180/gateware/ls180.v:6068.42-6068.97" + wire $and$build/ls180/gateware/ls180.v:6068$1957_Y + attribute \src "build/ls180/gateware/ls180.v:6068.41-6068.148" + wire $and$build/ls180/gateware/ls180.v:6068$1959_Y + attribute \src "build/ls180/gateware/ls180.v:6069.42-6069.100" + wire $and$build/ls180/gateware/ls180.v:6069$1961_Y + attribute \src "build/ls180/gateware/ls180.v:6069.41-6069.151" + wire $and$build/ls180/gateware/ls180.v:6069$1963_Y + attribute \src "build/ls180/gateware/ls180.v:6071.40-6071.95" + wire $and$build/ls180/gateware/ls180.v:6071$1964_Y + attribute \src "build/ls180/gateware/ls180.v:6071.39-6071.146" + wire $and$build/ls180/gateware/ls180.v:6071$1966_Y + attribute \src "build/ls180/gateware/ls180.v:6072.40-6072.98" + wire $and$build/ls180/gateware/ls180.v:6072$1968_Y + attribute \src "build/ls180/gateware/ls180.v:6072.39-6072.149" + wire $and$build/ls180/gateware/ls180.v:6072$1970_Y + attribute \src "build/ls180/gateware/ls180.v:6074.41-6074.96" + wire $and$build/ls180/gateware/ls180.v:6074$1971_Y + attribute \src "build/ls180/gateware/ls180.v:6074.40-6074.147" + wire $and$build/ls180/gateware/ls180.v:6074$1973_Y + attribute \src "build/ls180/gateware/ls180.v:6075.41-6075.99" + wire $and$build/ls180/gateware/ls180.v:6075$1975_Y + attribute \src "build/ls180/gateware/ls180.v:6075.40-6075.150" + wire $and$build/ls180/gateware/ls180.v:6075$1977_Y + attribute \src "build/ls180/gateware/ls180.v:6077.57-6077.112" + wire $and$build/ls180/gateware/ls180.v:6077$1978_Y + attribute \src "build/ls180/gateware/ls180.v:6077.56-6077.163" + wire $and$build/ls180/gateware/ls180.v:6077$1980_Y + attribute \src "build/ls180/gateware/ls180.v:6078.57-6078.115" + wire $and$build/ls180/gateware/ls180.v:6078$1982_Y + attribute \src "build/ls180/gateware/ls180.v:6078.56-6078.166" + wire $and$build/ls180/gateware/ls180.v:6078$1984_Y + attribute \src "build/ls180/gateware/ls180.v:6080.58-6080.113" + wire $and$build/ls180/gateware/ls180.v:6080$1985_Y + attribute \src "build/ls180/gateware/ls180.v:6080.57-6080.164" + wire $and$build/ls180/gateware/ls180.v:6080$1987_Y + attribute \src "build/ls180/gateware/ls180.v:6081.58-6081.116" + wire $and$build/ls180/gateware/ls180.v:6081$1989_Y + attribute \src "build/ls180/gateware/ls180.v:6081.57-6081.167" + wire $and$build/ls180/gateware/ls180.v:6081$1991_Y + attribute \src "build/ls180/gateware/ls180.v:6083.44-6083.99" + wire $and$build/ls180/gateware/ls180.v:6083$1992_Y + attribute \src "build/ls180/gateware/ls180.v:6083.43-6083.150" + wire $and$build/ls180/gateware/ls180.v:6083$1994_Y + attribute \src "build/ls180/gateware/ls180.v:6084.44-6084.102" + wire $and$build/ls180/gateware/ls180.v:6084$1996_Y + attribute \src "build/ls180/gateware/ls180.v:6084.43-6084.153" + wire $and$build/ls180/gateware/ls180.v:6084$1998_Y + attribute \src "build/ls180/gateware/ls180.v:6086.41-6086.96" + wire $and$build/ls180/gateware/ls180.v:6086$1999_Y + attribute \src "build/ls180/gateware/ls180.v:6086.40-6086.147" + wire $and$build/ls180/gateware/ls180.v:6086$2001_Y + attribute \src "build/ls180/gateware/ls180.v:6087.41-6087.99" + wire $and$build/ls180/gateware/ls180.v:6087$2003_Y + attribute \src "build/ls180/gateware/ls180.v:6087.40-6087.150" + wire $and$build/ls180/gateware/ls180.v:6087$2005_Y + attribute \src "build/ls180/gateware/ls180.v:6089.40-6089.95" + wire $and$build/ls180/gateware/ls180.v:6089$2006_Y + attribute \src "build/ls180/gateware/ls180.v:6089.39-6089.146" + wire $and$build/ls180/gateware/ls180.v:6089$2008_Y + attribute \src "build/ls180/gateware/ls180.v:6090.40-6090.98" + wire $and$build/ls180/gateware/ls180.v:6090$2010_Y + attribute \src "build/ls180/gateware/ls180.v:6090.39-6090.149" + wire $and$build/ls180/gateware/ls180.v:6090$2012_Y + attribute \src "build/ls180/gateware/ls180.v:6102.46-6102.101" + wire $and$build/ls180/gateware/ls180.v:6102$2014_Y + attribute \src "build/ls180/gateware/ls180.v:6102.45-6102.152" + wire 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attribute \src "build/ls180/gateware/ls180.v:6109.46-6109.104" + wire $and$build/ls180/gateware/ls180.v:6109$2032_Y + attribute \src "build/ls180/gateware/ls180.v:6109.45-6109.155" + wire $and$build/ls180/gateware/ls180.v:6109$2034_Y + attribute \src "build/ls180/gateware/ls180.v:6111.46-6111.101" + wire $and$build/ls180/gateware/ls180.v:6111$2035_Y + attribute \src "build/ls180/gateware/ls180.v:6111.45-6111.152" + wire $and$build/ls180/gateware/ls180.v:6111$2037_Y + attribute \src "build/ls180/gateware/ls180.v:6112.46-6112.104" + wire $and$build/ls180/gateware/ls180.v:6112$2039_Y + attribute \src "build/ls180/gateware/ls180.v:6112.45-6112.155" + wire $and$build/ls180/gateware/ls180.v:6112$2041_Y + attribute \src "build/ls180/gateware/ls180.v:6487.109-6487.178" + wire $and$build/ls180/gateware/ls180.v:6487$2077_Y + attribute \src "build/ls180/gateware/ls180.v:6487.184-6487.253" + wire $and$build/ls180/gateware/ls180.v:6487$2080_Y + attribute \src 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"build/ls180/gateware/ls180.v:6757.38-6757.145" + wire $and$build/ls180/gateware/ls180.v:6757$2155_Y + attribute \src "build/ls180/gateware/ls180.v:6760.39-6760.104" + wire $and$build/ls180/gateware/ls180.v:6760$2156_Y + attribute \src "build/ls180/gateware/ls180.v:6760.38-6760.145" + wire $and$build/ls180/gateware/ls180.v:6760$2157_Y + attribute \src "build/ls180/gateware/ls180.v:6763.39-6763.82" + wire $and$build/ls180/gateware/ls180.v:6763$2158_Y + attribute \src "build/ls180/gateware/ls180.v:6763.38-6763.112" + wire $and$build/ls180/gateware/ls180.v:6763$2159_Y + attribute \src "build/ls180/gateware/ls180.v:6774.39-6774.104" + wire $and$build/ls180/gateware/ls180.v:6774$2161_Y + attribute \src "build/ls180/gateware/ls180.v:6774.38-6774.144" + wire $and$build/ls180/gateware/ls180.v:6774$2162_Y + attribute \src "build/ls180/gateware/ls180.v:6777.39-6777.104" + wire $and$build/ls180/gateware/ls180.v:6777$2163_Y + attribute \src "build/ls180/gateware/ls180.v:6777.38-6777.144" + wire $and$build/ls180/gateware/ls180.v:6777$2164_Y + attribute \src "build/ls180/gateware/ls180.v:6780.39-6780.82" + wire $and$build/ls180/gateware/ls180.v:6780$2165_Y + attribute \src "build/ls180/gateware/ls180.v:6780.38-6780.111" + wire $and$build/ls180/gateware/ls180.v:6780$2166_Y + attribute \src "build/ls180/gateware/ls180.v:6791.39-6791.104" + wire $and$build/ls180/gateware/ls180.v:6791$2168_Y + attribute \src "build/ls180/gateware/ls180.v:6791.38-6791.149" + wire $and$build/ls180/gateware/ls180.v:6791$2169_Y + attribute \src "build/ls180/gateware/ls180.v:6794.39-6794.104" + wire $and$build/ls180/gateware/ls180.v:6794$2170_Y + attribute \src "build/ls180/gateware/ls180.v:6794.38-6794.149" + wire $and$build/ls180/gateware/ls180.v:6794$2171_Y + attribute \src "build/ls180/gateware/ls180.v:6797.39-6797.82" + wire $and$build/ls180/gateware/ls180.v:6797$2172_Y + attribute \src "build/ls180/gateware/ls180.v:6797.38-6797.116" + wire $and$build/ls180/gateware/ls180.v:6797$2173_Y + attribute \src "build/ls180/gateware/ls180.v:6808.39-6808.104" + wire $and$build/ls180/gateware/ls180.v:6808$2175_Y + attribute \src "build/ls180/gateware/ls180.v:6808.38-6808.150" + wire $and$build/ls180/gateware/ls180.v:6808$2176_Y + attribute \src "build/ls180/gateware/ls180.v:6811.39-6811.104" + wire $and$build/ls180/gateware/ls180.v:6811$2177_Y + attribute \src "build/ls180/gateware/ls180.v:6811.38-6811.150" + wire $and$build/ls180/gateware/ls180.v:6811$2178_Y + attribute \src "build/ls180/gateware/ls180.v:6814.39-6814.82" + wire $and$build/ls180/gateware/ls180.v:6814$2179_Y + attribute \src "build/ls180/gateware/ls180.v:6814.38-6814.117" + wire $and$build/ls180/gateware/ls180.v:6814$2180_Y + attribute \src "build/ls180/gateware/ls180.v:7005.17-7005.69" + wire $and$build/ls180/gateware/ls180.v:7005$2186_Y + attribute \src "build/ls180/gateware/ls180.v:7084.8-7084.67" + wire $and$build/ls180/gateware/ls180.v:7084$2192_Y + attribute \src "build/ls180/gateware/ls180.v:7084.7-7084.102" + wire $and$build/ls180/gateware/ls180.v:7084$2194_Y + attribute \src "build/ls180/gateware/ls180.v:7088.8-7088.65" + wire $and$build/ls180/gateware/ls180.v:7088$2196_Y + attribute \src "build/ls180/gateware/ls180.v:7088.7-7088.99" + wire $and$build/ls180/gateware/ls180.v:7088$2198_Y + attribute \src "build/ls180/gateware/ls180.v:7094.8-7094.65" + wire $and$build/ls180/gateware/ls180.v:7094$2199_Y + attribute \src "build/ls180/gateware/ls180.v:7118.8-7118.54" + wire $and$build/ls180/gateware/ls180.v:7118$2206_Y + attribute \src "build/ls180/gateware/ls180.v:7151.7-7151.81" + wire $and$build/ls180/gateware/ls180.v:7151$2212_Y + attribute \src "build/ls180/gateware/ls180.v:7158.7-7158.81" + wire $and$build/ls180/gateware/ls180.v:7158$2214_Y + attribute \src "build/ls180/gateware/ls180.v:7168.8-7168.99" + wire $and$build/ls180/gateware/ls180.v:7168$2215_Y + attribute \src "build/ls180/gateware/ls180.v:7168.7-7168.143" + wire $and$build/ls180/gateware/ls180.v:7168$2217_Y + attribute \src "build/ls180/gateware/ls180.v:7174.8-7174.99" + wire $and$build/ls180/gateware/ls180.v:7174$2220_Y + attribute \src "build/ls180/gateware/ls180.v:7174.7-7174.143" + wire $and$build/ls180/gateware/ls180.v:7174$2222_Y + attribute \src "build/ls180/gateware/ls180.v:7190.8-7190.99" + wire $and$build/ls180/gateware/ls180.v:7190$2226_Y + attribute \src "build/ls180/gateware/ls180.v:7190.7-7190.143" + wire $and$build/ls180/gateware/ls180.v:7190$2228_Y + attribute \src "build/ls180/gateware/ls180.v:7196.8-7196.99" + wire $and$build/ls180/gateware/ls180.v:7196$2231_Y + attribute \src "build/ls180/gateware/ls180.v:7196.7-7196.143" + wire $and$build/ls180/gateware/ls180.v:7196$2233_Y + attribute \src "build/ls180/gateware/ls180.v:7235.7-7235.87" + wire $and$build/ls180/gateware/ls180.v:7235$2240_Y + attribute \src "build/ls180/gateware/ls180.v:7243.7-7243.56" + wire $and$build/ls180/gateware/ls180.v:7243$2242_Y + attribute \src "build/ls180/gateware/ls180.v:7271.7-7271.75" + wire $and$build/ls180/gateware/ls180.v:7271$2249_Y + attribute \src "build/ls180/gateware/ls180.v:7313.8-7313.131" + wire $and$build/ls180/gateware/ls180.v:7313$2255_Y + attribute \src "build/ls180/gateware/ls180.v:7313.7-7313.190" + wire $and$build/ls180/gateware/ls180.v:7313$2257_Y + attribute \src "build/ls180/gateware/ls180.v:7319.8-7319.131" + wire $and$build/ls180/gateware/ls180.v:7319$2260_Y + attribute \src "build/ls180/gateware/ls180.v:7319.7-7319.190" + wire $and$build/ls180/gateware/ls180.v:7319$2262_Y + attribute \src "build/ls180/gateware/ls180.v:7359.8-7359.131" + wire $and$build/ls180/gateware/ls180.v:7359$2271_Y + attribute \src "build/ls180/gateware/ls180.v:7359.7-7359.190" + wire $and$build/ls180/gateware/ls180.v:7359$2273_Y + attribute \src "build/ls180/gateware/ls180.v:7365.8-7365.131" + wire $and$build/ls180/gateware/ls180.v:7365$2276_Y + attribute \src "build/ls180/gateware/ls180.v:7365.7-7365.190" + wire $and$build/ls180/gateware/ls180.v:7365$2278_Y + attribute \src "build/ls180/gateware/ls180.v:7405.8-7405.131" + wire $and$build/ls180/gateware/ls180.v:7405$2287_Y + attribute \src "build/ls180/gateware/ls180.v:7405.7-7405.190" + wire $and$build/ls180/gateware/ls180.v:7405$2289_Y + attribute \src "build/ls180/gateware/ls180.v:7411.8-7411.131" + wire $and$build/ls180/gateware/ls180.v:7411$2292_Y + attribute \src "build/ls180/gateware/ls180.v:7411.7-7411.190" + wire $and$build/ls180/gateware/ls180.v:7411$2294_Y + attribute \src "build/ls180/gateware/ls180.v:7451.8-7451.131" + wire $and$build/ls180/gateware/ls180.v:7451$2303_Y + attribute \src "build/ls180/gateware/ls180.v:7451.7-7451.190" + wire $and$build/ls180/gateware/ls180.v:7451$2305_Y + attribute \src "build/ls180/gateware/ls180.v:7457.8-7457.131" + wire $and$build/ls180/gateware/ls180.v:7457$2308_Y + attribute \src "build/ls180/gateware/ls180.v:7457.7-7457.190" + wire $and$build/ls180/gateware/ls180.v:7457$2310_Y + attribute \src "build/ls180/gateware/ls180.v:7654.48-7654.124" + wire $and$build/ls180/gateware/ls180.v:7654$2335_Y + attribute \src "build/ls180/gateware/ls180.v:7654.130-7654.206" + wire $and$build/ls180/gateware/ls180.v:7654$2338_Y + attribute \src "build/ls180/gateware/ls180.v:7654.212-7654.288" + wire $and$build/ls180/gateware/ls180.v:7654$2341_Y + attribute \src "build/ls180/gateware/ls180.v:7654.294-7654.370" + wire $and$build/ls180/gateware/ls180.v:7654$2344_Y + attribute \src "build/ls180/gateware/ls180.v:7655.49-7655.125" + wire $and$build/ls180/gateware/ls180.v:7655$2347_Y + attribute \src "build/ls180/gateware/ls180.v:7655.131-7655.207" + wire $and$build/ls180/gateware/ls180.v:7655$2350_Y + attribute \src "build/ls180/gateware/ls180.v:7655.213-7655.289" + wire $and$build/ls180/gateware/ls180.v:7655$2353_Y + attribute \src "build/ls180/gateware/ls180.v:7655.295-7655.371" + wire $and$build/ls180/gateware/ls180.v:7655$2356_Y + attribute \src "build/ls180/gateware/ls180.v:7674.8-7674.49" + wire $and$build/ls180/gateware/ls180.v:7674$2359_Y + attribute \src "build/ls180/gateware/ls180.v:7677.8-7677.53" + wire $and$build/ls180/gateware/ls180.v:7677$2360_Y + attribute \src "build/ls180/gateware/ls180.v:7743.7-7743.98" + wire $and$build/ls180/gateware/ls180.v:7743$2372_Y + attribute \src "build/ls180/gateware/ls180.v:7744.8-7744.95" + wire $and$build/ls180/gateware/ls180.v:7744$2373_Y + attribute \src "build/ls180/gateware/ls180.v:7752.8-7752.95" + wire $and$build/ls180/gateware/ls180.v:7752$2374_Y + attribute \src "build/ls180/gateware/ls180.v:7824.7-7824.100" + wire $and$build/ls180/gateware/ls180.v:7824$2384_Y + attribute \src "build/ls180/gateware/ls180.v:7825.8-7825.97" + wire $and$build/ls180/gateware/ls180.v:7825$2385_Y + attribute \src "build/ls180/gateware/ls180.v:7833.8-7833.97" + wire $and$build/ls180/gateware/ls180.v:7833$2386_Y + attribute \src "build/ls180/gateware/ls180.v:7903.7-7903.102" + wire $and$build/ls180/gateware/ls180.v:7903$2396_Y + attribute \src "build/ls180/gateware/ls180.v:7904.8-7904.99" + wire $and$build/ls180/gateware/ls180.v:7904$2397_Y + attribute \src "build/ls180/gateware/ls180.v:7912.8-7912.99" + wire $and$build/ls180/gateware/ls180.v:7912$2398_Y + attribute \src "build/ls180/gateware/ls180.v:8003.7-8003.96" + wire $and$build/ls180/gateware/ls180.v:8003$2404_Y + attribute \src "build/ls180/gateware/ls180.v:8006.7-8006.96" + wire $and$build/ls180/gateware/ls180.v:8006$2405_Y + attribute \src "build/ls180/gateware/ls180.v:8009.7-8009.96" + wire $and$build/ls180/gateware/ls180.v:8009$2406_Y + attribute \src "build/ls180/gateware/ls180.v:8012.7-8012.96" + wire $and$build/ls180/gateware/ls180.v:8012$2407_Y + attribute \src "build/ls180/gateware/ls180.v:8015.7-8015.96" + wire $and$build/ls180/gateware/ls180.v:8015$2408_Y + attribute \src "build/ls180/gateware/ls180.v:8020.7-8020.96" + wire $and$build/ls180/gateware/ls180.v:8020$2409_Y + attribute \src "build/ls180/gateware/ls180.v:8025.7-8025.96" + wire $and$build/ls180/gateware/ls180.v:8025$2410_Y + attribute \src "build/ls180/gateware/ls180.v:8030.7-8030.96" + wire $and$build/ls180/gateware/ls180.v:8030$2411_Y + attribute \src "build/ls180/gateware/ls180.v:8035.7-8035.96" + wire $and$build/ls180/gateware/ls180.v:8035$2412_Y + attribute \src "build/ls180/gateware/ls180.v:8100.8-8100.97" + wire $and$build/ls180/gateware/ls180.v:8100$2415_Y + attribute \src "build/ls180/gateware/ls180.v:8100.7-8100.140" + wire $and$build/ls180/gateware/ls180.v:8100$2417_Y + attribute \src "build/ls180/gateware/ls180.v:8106.8-8106.97" + wire $and$build/ls180/gateware/ls180.v:8106$2420_Y + attribute \src "build/ls180/gateware/ls180.v:8106.7-8106.140" + wire $and$build/ls180/gateware/ls180.v:8106$2422_Y + attribute \src "build/ls180/gateware/ls180.v:8126.7-8126.102" + wire $and$build/ls180/gateware/ls180.v:8126$2429_Y + attribute \src "build/ls180/gateware/ls180.v:8127.8-8127.99" + wire $and$build/ls180/gateware/ls180.v:8127$2430_Y + attribute \src "build/ls180/gateware/ls180.v:8135.8-8135.99" + wire $and$build/ls180/gateware/ls180.v:8135$2431_Y + attribute \src "build/ls180/gateware/ls180.v:8179.7-8179.102" + wire $and$build/ls180/gateware/ls180.v:8179$2435_Y + attribute \src "build/ls180/gateware/ls180.v:8186.8-8186.97" + wire $and$build/ls180/gateware/ls180.v:8186$2437_Y + attribute \src "build/ls180/gateware/ls180.v:8186.7-8186.140" + wire $and$build/ls180/gateware/ls180.v:8186$2439_Y + attribute \src "build/ls180/gateware/ls180.v:8192.8-8192.97" + wire $and$build/ls180/gateware/ls180.v:8192$2442_Y + attribute \src "build/ls180/gateware/ls180.v:8192.7-8192.140" + wire $and$build/ls180/gateware/ls180.v:8192$2444_Y + attribute \src "build/ls180/gateware/ls180.v:2630.42-2630.101" + wire $eq$build/ls180/gateware/ls180.v:2630$18_Y + attribute \src "build/ls180/gateware/ls180.v:2637.11-2637.54" + wire $eq$build/ls180/gateware/ls180.v:2637$23_Y + attribute \src "build/ls180/gateware/ls180.v:2690.42-2690.101" + wire $eq$build/ls180/gateware/ls180.v:2690$29_Y + attribute \src "build/ls180/gateware/ls180.v:2697.11-2697.54" + wire $eq$build/ls180/gateware/ls180.v:2697$34_Y + attribute \src "build/ls180/gateware/ls180.v:3003.34-3003.65" + wire $eq$build/ls180/gateware/ls180.v:3003$102_Y + attribute \src "build/ls180/gateware/ls180.v:3007.68-3007.102" + wire $eq$build/ls180/gateware/ls180.v:3007$105_Y + attribute \src "build/ls180/gateware/ls180.v:3051.43-3051.134" + wire $eq$build/ls180/gateware/ls180.v:3051$110_Y + attribute \src "build/ls180/gateware/ls180.v:3068.47-3068.88" + wire $eq$build/ls180/gateware/ls180.v:3068$123_Y + attribute \src "build/ls180/gateware/ls180.v:3208.43-3208.134" + wire $eq$build/ls180/gateware/ls180.v:3208$140_Y + attribute \src "build/ls180/gateware/ls180.v:3225.47-3225.88" + wire $eq$build/ls180/gateware/ls180.v:3225$153_Y + attribute \src "build/ls180/gateware/ls180.v:3365.43-3365.134" + wire $eq$build/ls180/gateware/ls180.v:3365$170_Y + attribute \src "build/ls180/gateware/ls180.v:3382.47-3382.88" + wire $eq$build/ls180/gateware/ls180.v:3382$183_Y + attribute \src "build/ls180/gateware/ls180.v:3522.43-3522.134" + wire $eq$build/ls180/gateware/ls180.v:3522$200_Y + attribute \src "build/ls180/gateware/ls180.v:3539.47-3539.88" + wire $eq$build/ls180/gateware/ls180.v:3539$213_Y + attribute \src "build/ls180/gateware/ls180.v:3676.32-3676.56" + wire $eq$build/ls180/gateware/ls180.v:3676$260_Y + attribute \src "build/ls180/gateware/ls180.v:3677.32-3677.56" + wire $eq$build/ls180/gateware/ls180.v:3677$261_Y + attribute \src "build/ls180/gateware/ls180.v:3688.339-3688.418" + wire $eq$build/ls180/gateware/ls180.v:3688$275_Y + attribute \src "build/ls180/gateware/ls180.v:3688.423-3688.504" + wire $eq$build/ls180/gateware/ls180.v:3688$276_Y + attribute \src "build/ls180/gateware/ls180.v:3689.339-3689.418" + wire $eq$build/ls180/gateware/ls180.v:3689$288_Y + attribute \src "build/ls180/gateware/ls180.v:3689.423-3689.504" + wire $eq$build/ls180/gateware/ls180.v:3689$289_Y + attribute \src "build/ls180/gateware/ls180.v:3690.339-3690.418" + wire $eq$build/ls180/gateware/ls180.v:3690$301_Y + attribute \src "build/ls180/gateware/ls180.v:3690.423-3690.504" + wire $eq$build/ls180/gateware/ls180.v:3690$302_Y + attribute \src "build/ls180/gateware/ls180.v:3691.339-3691.418" + wire $eq$build/ls180/gateware/ls180.v:3691$314_Y + attribute \src "build/ls180/gateware/ls180.v:3691.423-3691.504" + wire $eq$build/ls180/gateware/ls180.v:3691$315_Y + attribute \src "build/ls180/gateware/ls180.v:3721.339-3721.418" + wire $eq$build/ls180/gateware/ls180.v:3721$333_Y + attribute \src "build/ls180/gateware/ls180.v:3721.423-3721.504" + wire $eq$build/ls180/gateware/ls180.v:3721$334_Y + attribute \src "build/ls180/gateware/ls180.v:3722.339-3722.418" + wire $eq$build/ls180/gateware/ls180.v:3722$346_Y + attribute \src "build/ls180/gateware/ls180.v:3722.423-3722.504" + wire $eq$build/ls180/gateware/ls180.v:3722$347_Y + attribute \src "build/ls180/gateware/ls180.v:3723.339-3723.418" + wire $eq$build/ls180/gateware/ls180.v:3723$359_Y + attribute \src "build/ls180/gateware/ls180.v:3723.423-3723.504" + wire $eq$build/ls180/gateware/ls180.v:3723$360_Y + attribute \src "build/ls180/gateware/ls180.v:3724.339-3724.418" + wire $eq$build/ls180/gateware/ls180.v:3724$372_Y + attribute \src "build/ls180/gateware/ls180.v:3724.423-3724.504" + wire $eq$build/ls180/gateware/ls180.v:3724$373_Y + attribute \src "build/ls180/gateware/ls180.v:3753.78-3753.113" + wire $eq$build/ls180/gateware/ls180.v:3753$382_Y + attribute \src "build/ls180/gateware/ls180.v:3756.78-3756.113" + wire $eq$build/ls180/gateware/ls180.v:3756$385_Y + attribute \src "build/ls180/gateware/ls180.v:3762.78-3762.113" + wire $eq$build/ls180/gateware/ls180.v:3762$389_Y + attribute \src "build/ls180/gateware/ls180.v:3765.78-3765.113" + wire $eq$build/ls180/gateware/ls180.v:3765$392_Y + attribute \src "build/ls180/gateware/ls180.v:3771.78-3771.113" + wire $eq$build/ls180/gateware/ls180.v:3771$396_Y + attribute \src "build/ls180/gateware/ls180.v:3774.78-3774.113" + wire $eq$build/ls180/gateware/ls180.v:3774$399_Y + attribute \src "build/ls180/gateware/ls180.v:3780.78-3780.113" + wire $eq$build/ls180/gateware/ls180.v:3780$403_Y + attribute \src "build/ls180/gateware/ls180.v:3783.78-3783.113" + wire $eq$build/ls180/gateware/ls180.v:3783$406_Y + attribute \src "build/ls180/gateware/ls180.v:3864.42-3864.82" + wire $eq$build/ls180/gateware/ls180.v:3864$429_Y + attribute \src "build/ls180/gateware/ls180.v:3864.145-3864.178" + wire $eq$build/ls180/gateware/ls180.v:3864$430_Y + attribute \src "build/ls180/gateware/ls180.v:3864.220-3864.253" + wire $eq$build/ls180/gateware/ls180.v:3864$433_Y + attribute \src "build/ls180/gateware/ls180.v:3864.295-3864.328" + wire $eq$build/ls180/gateware/ls180.v:3864$436_Y + attribute \src "build/ls180/gateware/ls180.v:3869.42-3869.82" + wire $eq$build/ls180/gateware/ls180.v:3869$445_Y + attribute \src "build/ls180/gateware/ls180.v:3869.145-3869.178" + wire $eq$build/ls180/gateware/ls180.v:3869$446_Y + attribute \src "build/ls180/gateware/ls180.v:3869.220-3869.253" + wire $eq$build/ls180/gateware/ls180.v:3869$449_Y + attribute \src "build/ls180/gateware/ls180.v:3869.295-3869.328" + wire $eq$build/ls180/gateware/ls180.v:3869$452_Y + attribute \src "build/ls180/gateware/ls180.v:3874.42-3874.82" + wire $eq$build/ls180/gateware/ls180.v:3874$461_Y + attribute \src "build/ls180/gateware/ls180.v:3874.145-3874.178" + wire $eq$build/ls180/gateware/ls180.v:3874$462_Y + attribute \src "build/ls180/gateware/ls180.v:3874.220-3874.253" + wire $eq$build/ls180/gateware/ls180.v:3874$465_Y + attribute \src "build/ls180/gateware/ls180.v:3874.295-3874.328" + wire $eq$build/ls180/gateware/ls180.v:3874$468_Y + attribute \src "build/ls180/gateware/ls180.v:3879.42-3879.82" + wire $eq$build/ls180/gateware/ls180.v:3879$477_Y + attribute \src "build/ls180/gateware/ls180.v:3879.145-3879.178" + wire $eq$build/ls180/gateware/ls180.v:3879$478_Y + attribute \src "build/ls180/gateware/ls180.v:3879.220-3879.253" + wire $eq$build/ls180/gateware/ls180.v:3879$481_Y + attribute \src "build/ls180/gateware/ls180.v:3879.295-3879.328" + wire $eq$build/ls180/gateware/ls180.v:3879$484_Y + attribute \src "build/ls180/gateware/ls180.v:3884.44-3884.77" + wire $eq$build/ls180/gateware/ls180.v:3884$493_Y + attribute \src "build/ls180/gateware/ls180.v:3884.83-3884.123" + wire $eq$build/ls180/gateware/ls180.v:3884$494_Y + attribute \src "build/ls180/gateware/ls180.v:3884.186-3884.219" + wire $eq$build/ls180/gateware/ls180.v:3884$495_Y + attribute \src "build/ls180/gateware/ls180.v:3884.261-3884.294" + wire $eq$build/ls180/gateware/ls180.v:3884$498_Y + attribute \src "build/ls180/gateware/ls180.v:3884.336-3884.369" + wire $eq$build/ls180/gateware/ls180.v:3884$501_Y + attribute \src "build/ls180/gateware/ls180.v:3884.418-3884.451" + wire $eq$build/ls180/gateware/ls180.v:3884$509_Y + attribute \src "build/ls180/gateware/ls180.v:3884.457-3884.497" + wire $eq$build/ls180/gateware/ls180.v:3884$510_Y + attribute \src "build/ls180/gateware/ls180.v:3884.560-3884.593" + wire $eq$build/ls180/gateware/ls180.v:3884$511_Y + attribute \src "build/ls180/gateware/ls180.v:3884.635-3884.668" + wire $eq$build/ls180/gateware/ls180.v:3884$514_Y + attribute \src "build/ls180/gateware/ls180.v:3884.710-3884.743" + wire $eq$build/ls180/gateware/ls180.v:3884$517_Y + attribute \src "build/ls180/gateware/ls180.v:3884.792-3884.825" + wire $eq$build/ls180/gateware/ls180.v:3884$525_Y + attribute \src "build/ls180/gateware/ls180.v:3884.831-3884.871" + wire $eq$build/ls180/gateware/ls180.v:3884$526_Y + attribute \src "build/ls180/gateware/ls180.v:3884.934-3884.967" + wire $eq$build/ls180/gateware/ls180.v:3884$527_Y + attribute \src "build/ls180/gateware/ls180.v:3884.1009-3884.1042" + wire $eq$build/ls180/gateware/ls180.v:3884$530_Y + attribute \src "build/ls180/gateware/ls180.v:3884.1084-3884.1117" + wire $eq$build/ls180/gateware/ls180.v:3884$533_Y + attribute \src "build/ls180/gateware/ls180.v:3884.1166-3884.1199" + wire $eq$build/ls180/gateware/ls180.v:3884$541_Y + attribute \src "build/ls180/gateware/ls180.v:3884.1205-3884.1245" + wire $eq$build/ls180/gateware/ls180.v:3884$542_Y + attribute \src "build/ls180/gateware/ls180.v:3884.1308-3884.1341" + wire $eq$build/ls180/gateware/ls180.v:3884$543_Y + attribute \src "build/ls180/gateware/ls180.v:3884.1383-3884.1416" + wire $eq$build/ls180/gateware/ls180.v:3884$546_Y + attribute \src "build/ls180/gateware/ls180.v:3884.1458-3884.1491" + wire $eq$build/ls180/gateware/ls180.v:3884$549_Y + attribute \src "build/ls180/gateware/ls180.v:3943.29-3943.57" + wire $eq$build/ls180/gateware/ls180.v:3943$562_Y + attribute \src "build/ls180/gateware/ls180.v:3950.11-3950.41" + wire $eq$build/ls180/gateware/ls180.v:3950$567_Y + attribute \src "build/ls180/gateware/ls180.v:3987.25-3987.78" + wire $eq$build/ls180/gateware/ls180.v:3987$593_Y + attribute \src "build/ls180/gateware/ls180.v:3988.25-3988.72" + wire $eq$build/ls180/gateware/ls180.v:3988$595_Y + attribute \src "build/ls180/gateware/ls180.v:4015.10-4015.45" + wire $eq$build/ls180/gateware/ls180.v:4015$599_Y + attribute \src "build/ls180/gateware/ls180.v:4115.10-4115.41" + wire $eq$build/ls180/gateware/ls180.v:4115$626_Y + attribute \src "build/ls180/gateware/ls180.v:4172.10-4172.40" + wire $eq$build/ls180/gateware/ls180.v:4172$629_Y + attribute \src "build/ls180/gateware/ls180.v:4189.10-4189.40" + wire $eq$build/ls180/gateware/ls180.v:4189$631_Y + attribute \src "build/ls180/gateware/ls180.v:4217.39-4217.90" + wire $eq$build/ls180/gateware/ls180.v:4217$633_Y + attribute \src "build/ls180/gateware/ls180.v:4267.9-4267.41" + wire $eq$build/ls180/gateware/ls180.v:4267$643_Y + attribute \src "build/ls180/gateware/ls180.v:4276.37-4276.108" + wire $eq$build/ls180/gateware/ls180.v:4276$645_Y + attribute \src "build/ls180/gateware/ls180.v:4295.9-4295.41" + wire $eq$build/ls180/gateware/ls180.v:4295$649_Y + attribute \src "build/ls180/gateware/ls180.v:4307.10-4307.40" + wire $eq$build/ls180/gateware/ls180.v:4307$651_Y + attribute \src "build/ls180/gateware/ls180.v:4344.40-4344.96" + wire $eq$build/ls180/gateware/ls180.v:4344$655_Y + attribute \src "build/ls180/gateware/ls180.v:4381.33-4381.91" + wire $eq$build/ls180/gateware/ls180.v:4381$664_Y + attribute \src "build/ls180/gateware/ls180.v:4429.10-4429.41" + wire $eq$build/ls180/gateware/ls180.v:4429$668_Y + attribute \src "build/ls180/gateware/ls180.v:4478.41-4478.100" + wire $eq$build/ls180/gateware/ls180.v:4478$670_Y + attribute \src "build/ls180/gateware/ls180.v:4529.9-4529.42" + wire $eq$build/ls180/gateware/ls180.v:4529$680_Y + attribute \src "build/ls180/gateware/ls180.v:4538.38-4538.126" + wire $eq$build/ls180/gateware/ls180.v:4538$683_Y + attribute \src "build/ls180/gateware/ls180.v:4561.9-4561.42" + wire $eq$build/ls180/gateware/ls180.v:4561$686_Y + attribute \src "build/ls180/gateware/ls180.v:4571.10-4571.42" + wire $eq$build/ls180/gateware/ls180.v:4571$688_Y + attribute \src "build/ls180/gateware/ls180.v:4740.9-4740.54" + wire $eq$build/ls180/gateware/ls180.v:4740$870_Y + attribute \src "build/ls180/gateware/ls180.v:4770.10-4770.55" + wire $eq$build/ls180/gateware/ls180.v:4770$871_Y + attribute \src "build/ls180/gateware/ls180.v:4801.10-4801.92" + wire $eq$build/ls180/gateware/ls180.v:4801$876_Y + attribute \src "build/ls180/gateware/ls180.v:4801.97-4801.179" + wire $eq$build/ls180/gateware/ls180.v:4801$877_Y + attribute \src "build/ls180/gateware/ls180.v:4801.185-4801.267" + wire $eq$build/ls180/gateware/ls180.v:4801$879_Y + attribute \src "build/ls180/gateware/ls180.v:4801.273-4801.355" + wire $eq$build/ls180/gateware/ls180.v:4801$881_Y + attribute \src "build/ls180/gateware/ls180.v:4809.7-4809.51" + wire $eq$build/ls180/gateware/ls180.v:4809$885_Y + attribute \src "build/ls180/gateware/ls180.v:4819.7-4819.51" + wire $eq$build/ls180/gateware/ls180.v:4819$888_Y + attribute \src "build/ls180/gateware/ls180.v:4829.7-4829.51" + wire $eq$build/ls180/gateware/ls180.v:4829$891_Y + attribute \src "build/ls180/gateware/ls180.v:4839.7-4839.51" + wire $eq$build/ls180/gateware/ls180.v:4839$894_Y + attribute \src "build/ls180/gateware/ls180.v:4963.37-4963.72" + wire $eq$build/ls180/gateware/ls180.v:4963$945_Y + attribute \src "build/ls180/gateware/ls180.v:4969.10-4969.46" + wire $eq$build/ls180/gateware/ls180.v:4969$948_Y + attribute \src "build/ls180/gateware/ls180.v:4970.11-4970.46" + wire $eq$build/ls180/gateware/ls180.v:4970$949_Y + attribute \src "build/ls180/gateware/ls180.v:4982.35-4982.71" + wire $eq$build/ls180/gateware/ls180.v:4982$950_Y + attribute \src "build/ls180/gateware/ls180.v:4983.9-4983.44" + wire $eq$build/ls180/gateware/ls180.v:4983$951_Y + attribute \src "build/ls180/gateware/ls180.v:4990.10-4990.56" + wire $eq$build/ls180/gateware/ls180.v:4990$952_Y + attribute \src "build/ls180/gateware/ls180.v:4996.12-4996.48" + wire $eq$build/ls180/gateware/ls180.v:4996$953_Y + attribute \src "build/ls180/gateware/ls180.v:4999.13-4999.49" + wire $eq$build/ls180/gateware/ls180.v:4999$954_Y + attribute \src "build/ls180/gateware/ls180.v:5021.10-5021.90" + wire $eq$build/ls180/gateware/ls180.v:5021$959_Y + attribute \src "build/ls180/gateware/ls180.v:5036.36-5036.116" + wire $eq$build/ls180/gateware/ls180.v:5036$962_Y + attribute \src "build/ls180/gateware/ls180.v:5038.10-5038.57" + wire $eq$build/ls180/gateware/ls180.v:5038$963_Y + attribute \src "build/ls180/gateware/ls180.v:5047.12-5047.92" + wire $eq$build/ls180/gateware/ls180.v:5047$967_Y + attribute \src "build/ls180/gateware/ls180.v:5054.11-5054.58" + wire $eq$build/ls180/gateware/ls180.v:5054$968_Y + attribute \src "build/ls180/gateware/ls180.v:5171.10-5171.119" + wire $eq$build/ls180/gateware/ls180.v:5171$985_Y + attribute \src "build/ls180/gateware/ls180.v:5261.46-5261.127" + wire $eq$build/ls180/gateware/ls180.v:5261$991_Y + attribute \src "build/ls180/gateware/ls180.v:5291.51-5291.96" + wire $eq$build/ls180/gateware/ls180.v:5291$994_Y + attribute \src "build/ls180/gateware/ls180.v:5292.50-5292.95" + wire $eq$build/ls180/gateware/ls180.v:5292$995_Y + attribute \src "build/ls180/gateware/ls180.v:5349.32-5349.99" + wire $eq$build/ls180/gateware/ls180.v:5349$1008_Y + attribute \src "build/ls180/gateware/ls180.v:5350.32-5350.93" + wire $eq$build/ls180/gateware/ls180.v:5350$1010_Y + attribute \src "build/ls180/gateware/ls180.v:5378.10-5378.59" + wire $eq$build/ls180/gateware/ls180.v:5378$1014_Y + attribute \src "build/ls180/gateware/ls180.v:5450.85-5450.106" + wire $eq$build/ls180/gateware/ls180.v:5450$1019_Y + attribute \src "build/ls180/gateware/ls180.v:5451.85-5451.106" + wire $eq$build/ls180/gateware/ls180.v:5451$1021_Y + attribute \src "build/ls180/gateware/ls180.v:5452.64-5452.85" + wire $eq$build/ls180/gateware/ls180.v:5452$1023_Y + attribute \src "build/ls180/gateware/ls180.v:5453.64-5453.85" + wire $eq$build/ls180/gateware/ls180.v:5453$1025_Y + attribute \src "build/ls180/gateware/ls180.v:5454.85-5454.106" + wire $eq$build/ls180/gateware/ls180.v:5454$1027_Y + attribute \src "build/ls180/gateware/ls180.v:5455.85-5455.106" + wire $eq$build/ls180/gateware/ls180.v:5455$1029_Y + attribute \src "build/ls180/gateware/ls180.v:5456.64-5456.85" + wire $eq$build/ls180/gateware/ls180.v:5456$1031_Y + attribute \src "build/ls180/gateware/ls180.v:5457.64-5457.85" + wire $eq$build/ls180/gateware/ls180.v:5457$1033_Y + attribute \src "build/ls180/gateware/ls180.v:5461.27-5461.64" + wire $eq$build/ls180/gateware/ls180.v:5461$1036_Y + attribute \src "build/ls180/gateware/ls180.v:5462.27-5462.68" + wire $eq$build/ls180/gateware/ls180.v:5462$1037_Y + attribute \src "build/ls180/gateware/ls180.v:5463.27-5463.66" + wire $eq$build/ls180/gateware/ls180.v:5463$1038_Y + attribute \src "build/ls180/gateware/ls180.v:5464.27-5464.60" + wire $eq$build/ls180/gateware/ls180.v:5464$1039_Y + attribute \src "build/ls180/gateware/ls180.v:5465.27-5465.65" + wire $eq$build/ls180/gateware/ls180.v:5465$1040_Y + attribute \src "build/ls180/gateware/ls180.v:5521.24-5521.45" + wire $eq$build/ls180/gateware/ls180.v:5521$1067_Y + attribute \src "build/ls180/gateware/ls180.v:5522.32-5522.77" + wire $eq$build/ls180/gateware/ls180.v:5522$1068_Y + attribute \src "build/ls180/gateware/ls180.v:5524.97-5524.141" + wire $eq$build/ls180/gateware/ls180.v:5524$1070_Y + attribute \src "build/ls180/gateware/ls180.v:5525.100-5525.144" + wire $eq$build/ls180/gateware/ls180.v:5525$1074_Y + attribute \src "build/ls180/gateware/ls180.v:5527.99-5527.143" + wire $eq$build/ls180/gateware/ls180.v:5527$1077_Y + attribute \src "build/ls180/gateware/ls180.v:5528.102-5528.146" + wire $eq$build/ls180/gateware/ls180.v:5528$1081_Y + attribute \src "build/ls180/gateware/ls180.v:5530.99-5530.143" + wire $eq$build/ls180/gateware/ls180.v:5530$1084_Y + attribute \src "build/ls180/gateware/ls180.v:5531.102-5531.146" + wire $eq$build/ls180/gateware/ls180.v:5531$1088_Y + attribute \src "build/ls180/gateware/ls180.v:5533.99-5533.143" + wire $eq$build/ls180/gateware/ls180.v:5533$1091_Y + attribute \src "build/ls180/gateware/ls180.v:5534.102-5534.146" + wire $eq$build/ls180/gateware/ls180.v:5534$1095_Y + attribute \src "build/ls180/gateware/ls180.v:5536.99-5536.143" + wire $eq$build/ls180/gateware/ls180.v:5536$1098_Y + attribute \src "build/ls180/gateware/ls180.v:5537.102-5537.146" + wire $eq$build/ls180/gateware/ls180.v:5537$1102_Y + attribute \src "build/ls180/gateware/ls180.v:5539.102-5539.146" + wire $eq$build/ls180/gateware/ls180.v:5539$1105_Y + attribute \src "build/ls180/gateware/ls180.v:5540.105-5540.149" + wire $eq$build/ls180/gateware/ls180.v:5540$1109_Y + attribute \src "build/ls180/gateware/ls180.v:5542.102-5542.146" + wire $eq$build/ls180/gateware/ls180.v:5542$1112_Y + attribute \src "build/ls180/gateware/ls180.v:5543.105-5543.149" + wire $eq$build/ls180/gateware/ls180.v:5543$1116_Y + attribute \src "build/ls180/gateware/ls180.v:5545.102-5545.146" + wire $eq$build/ls180/gateware/ls180.v:5545$1119_Y + attribute \src "build/ls180/gateware/ls180.v:5546.105-5546.149" + wire $eq$build/ls180/gateware/ls180.v:5546$1123_Y + attribute \src "build/ls180/gateware/ls180.v:5548.102-5548.146" + wire $eq$build/ls180/gateware/ls180.v:5548$1126_Y + attribute \src "build/ls180/gateware/ls180.v:5549.105-5549.149" + wire $eq$build/ls180/gateware/ls180.v:5549$1130_Y + attribute \src "build/ls180/gateware/ls180.v:5560.32-5560.77" + wire $eq$build/ls180/gateware/ls180.v:5560$1132_Y + attribute \src "build/ls180/gateware/ls180.v:5562.93-5562.135" + wire $eq$build/ls180/gateware/ls180.v:5562$1134_Y + attribute \src "build/ls180/gateware/ls180.v:5563.96-5563.138" + wire $eq$build/ls180/gateware/ls180.v:5563$1138_Y + attribute \src "build/ls180/gateware/ls180.v:5566.32-5566.77" + wire $eq$build/ls180/gateware/ls180.v:5566$1140_Y + attribute \src "build/ls180/gateware/ls180.v:5568.93-5568.135" + wire $eq$build/ls180/gateware/ls180.v:5568$1142_Y + attribute \src "build/ls180/gateware/ls180.v:5569.96-5569.138" + wire $eq$build/ls180/gateware/ls180.v:5569$1146_Y + attribute \src "build/ls180/gateware/ls180.v:5572.32-5572.78" + wire $eq$build/ls180/gateware/ls180.v:5572$1148_Y + attribute \src "build/ls180/gateware/ls180.v:5574.100-5574.144" + wire $eq$build/ls180/gateware/ls180.v:5574$1150_Y + attribute \src "build/ls180/gateware/ls180.v:5575.103-5575.147" + wire $eq$build/ls180/gateware/ls180.v:5575$1154_Y + attribute \src "build/ls180/gateware/ls180.v:5577.100-5577.144" + wire $eq$build/ls180/gateware/ls180.v:5577$1157_Y + attribute \src "build/ls180/gateware/ls180.v:5578.103-5578.147" + wire $eq$build/ls180/gateware/ls180.v:5578$1161_Y + attribute \src "build/ls180/gateware/ls180.v:5580.100-5580.144" + wire $eq$build/ls180/gateware/ls180.v:5580$1164_Y + attribute \src "build/ls180/gateware/ls180.v:5581.103-5581.147" + wire $eq$build/ls180/gateware/ls180.v:5581$1168_Y + attribute \src "build/ls180/gateware/ls180.v:5583.100-5583.144" + wire $eq$build/ls180/gateware/ls180.v:5583$1171_Y + attribute \src "build/ls180/gateware/ls180.v:5584.103-5584.147" + wire $eq$build/ls180/gateware/ls180.v:5584$1175_Y + attribute \src "build/ls180/gateware/ls180.v:5586.100-5586.144" + wire $eq$build/ls180/gateware/ls180.v:5586$1178_Y + attribute \src "build/ls180/gateware/ls180.v:5587.103-5587.147" + wire $eq$build/ls180/gateware/ls180.v:5587$1182_Y + attribute \src "build/ls180/gateware/ls180.v:5589.100-5589.144" + wire $eq$build/ls180/gateware/ls180.v:5589$1185_Y + attribute \src "build/ls180/gateware/ls180.v:5590.103-5590.147" + wire $eq$build/ls180/gateware/ls180.v:5590$1189_Y + attribute \src "build/ls180/gateware/ls180.v:5592.100-5592.144" + wire $eq$build/ls180/gateware/ls180.v:5592$1192_Y + attribute \src "build/ls180/gateware/ls180.v:5593.103-5593.147" + wire $eq$build/ls180/gateware/ls180.v:5593$1196_Y + attribute \src "build/ls180/gateware/ls180.v:5595.100-5595.144" + wire $eq$build/ls180/gateware/ls180.v:5595$1199_Y + attribute \src "build/ls180/gateware/ls180.v:5596.103-5596.147" + wire $eq$build/ls180/gateware/ls180.v:5596$1203_Y + attribute \src "build/ls180/gateware/ls180.v:5598.102-5598.146" + wire $eq$build/ls180/gateware/ls180.v:5598$1206_Y + attribute \src "build/ls180/gateware/ls180.v:5599.105-5599.149" + wire $eq$build/ls180/gateware/ls180.v:5599$1210_Y + attribute \src "build/ls180/gateware/ls180.v:5601.102-5601.146" + wire $eq$build/ls180/gateware/ls180.v:5601$1213_Y + attribute \src "build/ls180/gateware/ls180.v:5602.105-5602.149" + wire $eq$build/ls180/gateware/ls180.v:5602$1217_Y + attribute \src "build/ls180/gateware/ls180.v:5604.102-5604.147" + wire $eq$build/ls180/gateware/ls180.v:5604$1220_Y + attribute \src "build/ls180/gateware/ls180.v:5605.105-5605.150" + wire $eq$build/ls180/gateware/ls180.v:5605$1224_Y + attribute \src "build/ls180/gateware/ls180.v:5607.102-5607.147" + wire $eq$build/ls180/gateware/ls180.v:5607$1227_Y + attribute \src "build/ls180/gateware/ls180.v:5608.105-5608.150" + wire $eq$build/ls180/gateware/ls180.v:5608$1231_Y + attribute \src "build/ls180/gateware/ls180.v:5610.102-5610.147" + wire $eq$build/ls180/gateware/ls180.v:5610$1234_Y + attribute \src "build/ls180/gateware/ls180.v:5611.105-5611.150" + wire $eq$build/ls180/gateware/ls180.v:5611$1238_Y + attribute \src "build/ls180/gateware/ls180.v:5613.99-5613.144" + wire $eq$build/ls180/gateware/ls180.v:5613$1241_Y + attribute \src "build/ls180/gateware/ls180.v:5614.102-5614.147" + wire $eq$build/ls180/gateware/ls180.v:5614$1245_Y + attribute \src "build/ls180/gateware/ls180.v:5616.100-5616.145" + wire $eq$build/ls180/gateware/ls180.v:5616$1248_Y + attribute \src "build/ls180/gateware/ls180.v:5617.103-5617.148" + wire $eq$build/ls180/gateware/ls180.v:5617$1252_Y + attribute \src "build/ls180/gateware/ls180.v:5634.32-5634.78" + wire $eq$build/ls180/gateware/ls180.v:5634$1254_Y + attribute \src "build/ls180/gateware/ls180.v:5636.104-5636.148" + wire $eq$build/ls180/gateware/ls180.v:5636$1256_Y + attribute \src "build/ls180/gateware/ls180.v:5637.107-5637.151" + wire $eq$build/ls180/gateware/ls180.v:5637$1260_Y + attribute \src "build/ls180/gateware/ls180.v:5639.104-5639.148" + wire $eq$build/ls180/gateware/ls180.v:5639$1263_Y + attribute \src "build/ls180/gateware/ls180.v:5640.107-5640.151" + wire $eq$build/ls180/gateware/ls180.v:5640$1267_Y + attribute \src "build/ls180/gateware/ls180.v:5642.104-5642.148" + wire $eq$build/ls180/gateware/ls180.v:5642$1270_Y + attribute \src "build/ls180/gateware/ls180.v:5643.107-5643.151" + wire $eq$build/ls180/gateware/ls180.v:5643$1274_Y + attribute \src "build/ls180/gateware/ls180.v:5645.104-5645.148" + wire $eq$build/ls180/gateware/ls180.v:5645$1277_Y + attribute \src "build/ls180/gateware/ls180.v:5646.107-5646.151" + wire $eq$build/ls180/gateware/ls180.v:5646$1281_Y + attribute \src "build/ls180/gateware/ls180.v:5648.103-5648.147" + wire $eq$build/ls180/gateware/ls180.v:5648$1284_Y + attribute \src "build/ls180/gateware/ls180.v:5649.106-5649.150" + wire $eq$build/ls180/gateware/ls180.v:5649$1288_Y + attribute \src "build/ls180/gateware/ls180.v:5651.103-5651.147" + wire $eq$build/ls180/gateware/ls180.v:5651$1291_Y + attribute \src "build/ls180/gateware/ls180.v:5652.106-5652.150" + wire $eq$build/ls180/gateware/ls180.v:5652$1295_Y + attribute \src "build/ls180/gateware/ls180.v:5654.103-5654.147" + wire $eq$build/ls180/gateware/ls180.v:5654$1298_Y + attribute \src "build/ls180/gateware/ls180.v:5655.106-5655.150" + wire $eq$build/ls180/gateware/ls180.v:5655$1302_Y + attribute \src "build/ls180/gateware/ls180.v:5657.103-5657.147" + wire $eq$build/ls180/gateware/ls180.v:5657$1305_Y + attribute \src "build/ls180/gateware/ls180.v:5658.106-5658.150" + wire $eq$build/ls180/gateware/ls180.v:5658$1309_Y + attribute \src "build/ls180/gateware/ls180.v:5660.101-5660.145" + wire $eq$build/ls180/gateware/ls180.v:5660$1312_Y + attribute \src "build/ls180/gateware/ls180.v:5661.104-5661.148" + wire $eq$build/ls180/gateware/ls180.v:5661$1316_Y + attribute \src "build/ls180/gateware/ls180.v:5663.105-5663.149" + wire $eq$build/ls180/gateware/ls180.v:5663$1319_Y + attribute \src "build/ls180/gateware/ls180.v:5664.108-5664.152" + wire $eq$build/ls180/gateware/ls180.v:5664$1323_Y + attribute \src "build/ls180/gateware/ls180.v:5666.105-5666.150" + wire $eq$build/ls180/gateware/ls180.v:5666$1326_Y + attribute \src "build/ls180/gateware/ls180.v:5667.108-5667.153" + wire $eq$build/ls180/gateware/ls180.v:5667$1330_Y + attribute \src "build/ls180/gateware/ls180.v:5669.105-5669.150" + wire $eq$build/ls180/gateware/ls180.v:5669$1333_Y + attribute \src "build/ls180/gateware/ls180.v:5670.108-5670.153" + wire $eq$build/ls180/gateware/ls180.v:5670$1337_Y + attribute \src "build/ls180/gateware/ls180.v:5672.105-5672.150" + wire $eq$build/ls180/gateware/ls180.v:5672$1340_Y + attribute \src "build/ls180/gateware/ls180.v:5673.108-5673.153" + wire $eq$build/ls180/gateware/ls180.v:5673$1344_Y + attribute \src "build/ls180/gateware/ls180.v:5675.105-5675.150" + wire $eq$build/ls180/gateware/ls180.v:5675$1347_Y + attribute \src "build/ls180/gateware/ls180.v:5676.108-5676.153" + wire $eq$build/ls180/gateware/ls180.v:5676$1351_Y + attribute \src "build/ls180/gateware/ls180.v:5678.105-5678.150" + wire $eq$build/ls180/gateware/ls180.v:5678$1354_Y + attribute \src "build/ls180/gateware/ls180.v:5679.108-5679.153" + wire $eq$build/ls180/gateware/ls180.v:5679$1358_Y + attribute \src "build/ls180/gateware/ls180.v:5681.104-5681.149" + wire $eq$build/ls180/gateware/ls180.v:5681$1361_Y + attribute \src "build/ls180/gateware/ls180.v:5682.107-5682.152" + wire $eq$build/ls180/gateware/ls180.v:5682$1365_Y + attribute \src "build/ls180/gateware/ls180.v:5684.104-5684.149" + wire $eq$build/ls180/gateware/ls180.v:5684$1368_Y + attribute \src "build/ls180/gateware/ls180.v:5685.107-5685.152" + wire $eq$build/ls180/gateware/ls180.v:5685$1372_Y + attribute \src "build/ls180/gateware/ls180.v:5687.104-5687.149" + wire $eq$build/ls180/gateware/ls180.v:5687$1375_Y + attribute \src "build/ls180/gateware/ls180.v:5688.107-5688.152" + wire $eq$build/ls180/gateware/ls180.v:5688$1379_Y + attribute \src "build/ls180/gateware/ls180.v:5690.104-5690.149" + wire $eq$build/ls180/gateware/ls180.v:5690$1382_Y + attribute \src "build/ls180/gateware/ls180.v:5691.107-5691.152" + wire $eq$build/ls180/gateware/ls180.v:5691$1386_Y + attribute \src "build/ls180/gateware/ls180.v:5693.104-5693.149" + wire $eq$build/ls180/gateware/ls180.v:5693$1389_Y + attribute \src "build/ls180/gateware/ls180.v:5694.107-5694.152" + wire $eq$build/ls180/gateware/ls180.v:5694$1393_Y + attribute \src "build/ls180/gateware/ls180.v:5696.104-5696.149" + wire $eq$build/ls180/gateware/ls180.v:5696$1396_Y + attribute \src "build/ls180/gateware/ls180.v:5697.107-5697.152" + wire $eq$build/ls180/gateware/ls180.v:5697$1400_Y + attribute \src "build/ls180/gateware/ls180.v:5699.104-5699.149" + wire $eq$build/ls180/gateware/ls180.v:5699$1403_Y + attribute \src "build/ls180/gateware/ls180.v:5700.107-5700.152" + wire $eq$build/ls180/gateware/ls180.v:5700$1407_Y + attribute \src "build/ls180/gateware/ls180.v:5702.104-5702.149" + wire $eq$build/ls180/gateware/ls180.v:5702$1410_Y + attribute \src "build/ls180/gateware/ls180.v:5703.107-5703.152" + wire $eq$build/ls180/gateware/ls180.v:5703$1414_Y + attribute \src "build/ls180/gateware/ls180.v:5705.104-5705.149" + wire $eq$build/ls180/gateware/ls180.v:5705$1417_Y + attribute \src "build/ls180/gateware/ls180.v:5706.107-5706.152" + wire $eq$build/ls180/gateware/ls180.v:5706$1421_Y + attribute \src "build/ls180/gateware/ls180.v:5708.104-5708.149" + wire $eq$build/ls180/gateware/ls180.v:5708$1424_Y + attribute \src "build/ls180/gateware/ls180.v:5709.107-5709.152" + wire $eq$build/ls180/gateware/ls180.v:5709$1428_Y + attribute \src "build/ls180/gateware/ls180.v:5711.100-5711.145" + wire $eq$build/ls180/gateware/ls180.v:5711$1431_Y + attribute \src "build/ls180/gateware/ls180.v:5712.103-5712.148" + wire $eq$build/ls180/gateware/ls180.v:5712$1435_Y + attribute \src "build/ls180/gateware/ls180.v:5714.101-5714.146" + wire $eq$build/ls180/gateware/ls180.v:5714$1438_Y + attribute \src "build/ls180/gateware/ls180.v:5715.104-5715.149" + wire $eq$build/ls180/gateware/ls180.v:5715$1442_Y + attribute \src "build/ls180/gateware/ls180.v:5717.104-5717.149" + wire $eq$build/ls180/gateware/ls180.v:5717$1445_Y + attribute \src "build/ls180/gateware/ls180.v:5718.107-5718.152" + wire $eq$build/ls180/gateware/ls180.v:5718$1449_Y + attribute \src "build/ls180/gateware/ls180.v:5720.104-5720.149" + wire $eq$build/ls180/gateware/ls180.v:5720$1452_Y + attribute \src "build/ls180/gateware/ls180.v:5721.107-5721.152" + wire $eq$build/ls180/gateware/ls180.v:5721$1456_Y + attribute \src "build/ls180/gateware/ls180.v:5723.103-5723.148" + wire $eq$build/ls180/gateware/ls180.v:5723$1459_Y + attribute \src "build/ls180/gateware/ls180.v:5724.106-5724.151" + wire $eq$build/ls180/gateware/ls180.v:5724$1463_Y + attribute \src "build/ls180/gateware/ls180.v:5726.103-5726.148" + wire $eq$build/ls180/gateware/ls180.v:5726$1466_Y + attribute \src "build/ls180/gateware/ls180.v:5727.106-5727.151" + wire $eq$build/ls180/gateware/ls180.v:5727$1470_Y + attribute \src "build/ls180/gateware/ls180.v:5729.103-5729.148" + wire $eq$build/ls180/gateware/ls180.v:5729$1473_Y + attribute \src "build/ls180/gateware/ls180.v:5730.106-5730.151" + wire $eq$build/ls180/gateware/ls180.v:5730$1477_Y + attribute \src "build/ls180/gateware/ls180.v:5732.103-5732.148" + wire $eq$build/ls180/gateware/ls180.v:5732$1480_Y + attribute \src "build/ls180/gateware/ls180.v:5733.106-5733.151" + wire $eq$build/ls180/gateware/ls180.v:5733$1484_Y + attribute \src "build/ls180/gateware/ls180.v:5769.32-5769.78" + wire $eq$build/ls180/gateware/ls180.v:5769$1486_Y + attribute \src "build/ls180/gateware/ls180.v:5771.100-5771.144" + wire $eq$build/ls180/gateware/ls180.v:5771$1488_Y + attribute \src "build/ls180/gateware/ls180.v:5772.103-5772.147" + wire $eq$build/ls180/gateware/ls180.v:5772$1492_Y + attribute \src "build/ls180/gateware/ls180.v:5774.100-5774.144" + wire $eq$build/ls180/gateware/ls180.v:5774$1495_Y + attribute \src "build/ls180/gateware/ls180.v:5775.103-5775.147" + wire $eq$build/ls180/gateware/ls180.v:5775$1499_Y + attribute \src "build/ls180/gateware/ls180.v:5777.100-5777.144" + wire $eq$build/ls180/gateware/ls180.v:5777$1502_Y + attribute \src "build/ls180/gateware/ls180.v:5778.103-5778.147" + wire $eq$build/ls180/gateware/ls180.v:5778$1506_Y + attribute \src "build/ls180/gateware/ls180.v:5780.100-5780.144" + wire $eq$build/ls180/gateware/ls180.v:5780$1509_Y + attribute \src "build/ls180/gateware/ls180.v:5781.103-5781.147" + wire $eq$build/ls180/gateware/ls180.v:5781$1513_Y + attribute \src "build/ls180/gateware/ls180.v:5783.100-5783.144" + wire $eq$build/ls180/gateware/ls180.v:5783$1516_Y + attribute \src "build/ls180/gateware/ls180.v:5784.103-5784.147" + wire $eq$build/ls180/gateware/ls180.v:5784$1520_Y + attribute \src "build/ls180/gateware/ls180.v:5786.100-5786.144" + wire $eq$build/ls180/gateware/ls180.v:5786$1523_Y + attribute \src "build/ls180/gateware/ls180.v:5787.103-5787.147" + wire $eq$build/ls180/gateware/ls180.v:5787$1527_Y + attribute \src "build/ls180/gateware/ls180.v:5789.100-5789.144" + wire $eq$build/ls180/gateware/ls180.v:5789$1530_Y + attribute \src "build/ls180/gateware/ls180.v:5790.103-5790.147" + wire $eq$build/ls180/gateware/ls180.v:5790$1534_Y + attribute \src "build/ls180/gateware/ls180.v:5792.100-5792.144" + wire $eq$build/ls180/gateware/ls180.v:5792$1537_Y + attribute \src "build/ls180/gateware/ls180.v:5793.103-5793.147" + wire $eq$build/ls180/gateware/ls180.v:5793$1541_Y + attribute \src "build/ls180/gateware/ls180.v:5795.102-5795.146" + wire $eq$build/ls180/gateware/ls180.v:5795$1544_Y + attribute \src "build/ls180/gateware/ls180.v:5796.105-5796.149" + wire $eq$build/ls180/gateware/ls180.v:5796$1548_Y + attribute \src "build/ls180/gateware/ls180.v:5798.102-5798.146" + wire $eq$build/ls180/gateware/ls180.v:5798$1551_Y + attribute \src "build/ls180/gateware/ls180.v:5799.105-5799.149" + wire $eq$build/ls180/gateware/ls180.v:5799$1555_Y + attribute \src "build/ls180/gateware/ls180.v:5801.102-5801.147" + wire $eq$build/ls180/gateware/ls180.v:5801$1558_Y + attribute \src "build/ls180/gateware/ls180.v:5802.105-5802.150" + wire $eq$build/ls180/gateware/ls180.v:5802$1562_Y + attribute \src "build/ls180/gateware/ls180.v:5804.102-5804.147" + wire $eq$build/ls180/gateware/ls180.v:5804$1565_Y + attribute \src "build/ls180/gateware/ls180.v:5805.105-5805.150" + wire $eq$build/ls180/gateware/ls180.v:5805$1569_Y + attribute \src "build/ls180/gateware/ls180.v:5807.102-5807.147" + wire $eq$build/ls180/gateware/ls180.v:5807$1572_Y + attribute \src "build/ls180/gateware/ls180.v:5808.105-5808.150" + wire $eq$build/ls180/gateware/ls180.v:5808$1576_Y + attribute \src "build/ls180/gateware/ls180.v:5810.99-5810.144" + wire $eq$build/ls180/gateware/ls180.v:5810$1579_Y + attribute \src "build/ls180/gateware/ls180.v:5811.102-5811.147" + wire $eq$build/ls180/gateware/ls180.v:5811$1583_Y + attribute \src "build/ls180/gateware/ls180.v:5813.100-5813.145" + wire $eq$build/ls180/gateware/ls180.v:5813$1586_Y + attribute \src "build/ls180/gateware/ls180.v:5814.103-5814.148" + wire $eq$build/ls180/gateware/ls180.v:5814$1590_Y + attribute \src "build/ls180/gateware/ls180.v:5816.102-5816.147" + wire $eq$build/ls180/gateware/ls180.v:5816$1593_Y + attribute \src "build/ls180/gateware/ls180.v:5817.105-5817.150" + wire $eq$build/ls180/gateware/ls180.v:5817$1597_Y + attribute \src "build/ls180/gateware/ls180.v:5819.102-5819.147" + wire $eq$build/ls180/gateware/ls180.v:5819$1600_Y + attribute \src "build/ls180/gateware/ls180.v:5820.105-5820.150" + wire $eq$build/ls180/gateware/ls180.v:5820$1604_Y + attribute \src "build/ls180/gateware/ls180.v:5822.102-5822.147" + wire $eq$build/ls180/gateware/ls180.v:5822$1607_Y + attribute \src "build/ls180/gateware/ls180.v:5823.105-5823.150" + wire $eq$build/ls180/gateware/ls180.v:5823$1611_Y + attribute \src "build/ls180/gateware/ls180.v:5825.102-5825.147" + wire $eq$build/ls180/gateware/ls180.v:5825$1614_Y + attribute \src "build/ls180/gateware/ls180.v:5826.105-5826.150" + wire $eq$build/ls180/gateware/ls180.v:5826$1618_Y + attribute \src "build/ls180/gateware/ls180.v:5848.32-5848.77" + wire $eq$build/ls180/gateware/ls180.v:5848$1620_Y + attribute \src "build/ls180/gateware/ls180.v:5850.102-5850.146" + wire $eq$build/ls180/gateware/ls180.v:5850$1622_Y + attribute \src "build/ls180/gateware/ls180.v:5851.105-5851.149" + wire $eq$build/ls180/gateware/ls180.v:5851$1626_Y + attribute \src "build/ls180/gateware/ls180.v:5853.107-5853.151" + wire $eq$build/ls180/gateware/ls180.v:5853$1629_Y + attribute \src "build/ls180/gateware/ls180.v:5854.110-5854.154" + wire $eq$build/ls180/gateware/ls180.v:5854$1633_Y + attribute \src "build/ls180/gateware/ls180.v:5856.107-5856.151" + wire $eq$build/ls180/gateware/ls180.v:5856$1636_Y + attribute \src "build/ls180/gateware/ls180.v:5857.110-5857.154" + wire $eq$build/ls180/gateware/ls180.v:5857$1640_Y + attribute \src "build/ls180/gateware/ls180.v:5859.101-5859.145" + wire $eq$build/ls180/gateware/ls180.v:5859$1643_Y + attribute \src "build/ls180/gateware/ls180.v:5860.104-5860.148" + wire $eq$build/ls180/gateware/ls180.v:5860$1647_Y + attribute \src "build/ls180/gateware/ls180.v:5865.32-5865.77" + wire $eq$build/ls180/gateware/ls180.v:5865$1649_Y + attribute \src "build/ls180/gateware/ls180.v:5867.104-5867.148" + wire $eq$build/ls180/gateware/ls180.v:5867$1651_Y + attribute \src "build/ls180/gateware/ls180.v:5868.107-5868.151" + wire $eq$build/ls180/gateware/ls180.v:5868$1655_Y + attribute \src "build/ls180/gateware/ls180.v:5870.108-5870.152" + wire $eq$build/ls180/gateware/ls180.v:5870$1658_Y + attribute \src "build/ls180/gateware/ls180.v:5871.111-5871.155" + wire $eq$build/ls180/gateware/ls180.v:5871$1662_Y + attribute \src "build/ls180/gateware/ls180.v:5873.98-5873.142" + wire $eq$build/ls180/gateware/ls180.v:5873$1665_Y + attribute \src "build/ls180/gateware/ls180.v:5874.101-5874.145" + wire $eq$build/ls180/gateware/ls180.v:5874$1669_Y + attribute \src "build/ls180/gateware/ls180.v:5876.108-5876.152" + wire $eq$build/ls180/gateware/ls180.v:5876$1672_Y + attribute \src "build/ls180/gateware/ls180.v:5877.111-5877.155" + wire $eq$build/ls180/gateware/ls180.v:5877$1676_Y + attribute \src "build/ls180/gateware/ls180.v:5879.108-5879.152" + wire $eq$build/ls180/gateware/ls180.v:5879$1679_Y + attribute \src "build/ls180/gateware/ls180.v:5880.111-5880.155" + wire $eq$build/ls180/gateware/ls180.v:5880$1683_Y + attribute \src "build/ls180/gateware/ls180.v:5882.109-5882.153" + wire $eq$build/ls180/gateware/ls180.v:5882$1686_Y + attribute \src "build/ls180/gateware/ls180.v:5883.112-5883.156" + wire $eq$build/ls180/gateware/ls180.v:5883$1690_Y + attribute \src "build/ls180/gateware/ls180.v:5885.107-5885.151" + wire $eq$build/ls180/gateware/ls180.v:5885$1693_Y + attribute \src "build/ls180/gateware/ls180.v:5886.110-5886.154" + wire $eq$build/ls180/gateware/ls180.v:5886$1697_Y + attribute \src "build/ls180/gateware/ls180.v:5888.107-5888.151" + wire $eq$build/ls180/gateware/ls180.v:5888$1700_Y + attribute \src "build/ls180/gateware/ls180.v:5889.110-5889.154" + wire $eq$build/ls180/gateware/ls180.v:5889$1704_Y + attribute \src "build/ls180/gateware/ls180.v:5891.107-5891.151" + wire $eq$build/ls180/gateware/ls180.v:5891$1707_Y + attribute \src "build/ls180/gateware/ls180.v:5892.110-5892.154" + wire $eq$build/ls180/gateware/ls180.v:5892$1711_Y + attribute \src "build/ls180/gateware/ls180.v:5894.107-5894.151" + wire $eq$build/ls180/gateware/ls180.v:5894$1714_Y + attribute \src "build/ls180/gateware/ls180.v:5895.110-5895.154" + wire $eq$build/ls180/gateware/ls180.v:5895$1718_Y + attribute \src "build/ls180/gateware/ls180.v:5910.32-5910.77" + wire $eq$build/ls180/gateware/ls180.v:5910$1720_Y + attribute \src "build/ls180/gateware/ls180.v:5912.99-5912.143" + wire $eq$build/ls180/gateware/ls180.v:5912$1722_Y + attribute \src "build/ls180/gateware/ls180.v:5913.102-5913.146" + wire $eq$build/ls180/gateware/ls180.v:5913$1726_Y + attribute \src "build/ls180/gateware/ls180.v:5915.99-5915.143" + wire $eq$build/ls180/gateware/ls180.v:5915$1729_Y + attribute \src "build/ls180/gateware/ls180.v:5916.102-5916.146" + wire $eq$build/ls180/gateware/ls180.v:5916$1733_Y + attribute \src "build/ls180/gateware/ls180.v:5918.97-5918.141" + wire $eq$build/ls180/gateware/ls180.v:5918$1736_Y + attribute \src "build/ls180/gateware/ls180.v:5919.100-5919.144" + wire $eq$build/ls180/gateware/ls180.v:5919$1740_Y + attribute \src "build/ls180/gateware/ls180.v:5921.96-5921.140" + wire $eq$build/ls180/gateware/ls180.v:5921$1743_Y + attribute \src "build/ls180/gateware/ls180.v:5922.99-5922.143" + wire $eq$build/ls180/gateware/ls180.v:5922$1747_Y + attribute \src "build/ls180/gateware/ls180.v:5924.95-5924.139" + wire $eq$build/ls180/gateware/ls180.v:5924$1750_Y + attribute \src "build/ls180/gateware/ls180.v:5925.98-5925.142" + wire $eq$build/ls180/gateware/ls180.v:5925$1754_Y + attribute \src "build/ls180/gateware/ls180.v:5927.94-5927.138" + wire $eq$build/ls180/gateware/ls180.v:5927$1757_Y + attribute \src "build/ls180/gateware/ls180.v:5928.97-5928.141" + wire $eq$build/ls180/gateware/ls180.v:5928$1761_Y + attribute \src "build/ls180/gateware/ls180.v:5930.100-5930.144" + wire $eq$build/ls180/gateware/ls180.v:5930$1764_Y + attribute \src "build/ls180/gateware/ls180.v:5931.103-5931.147" + wire $eq$build/ls180/gateware/ls180.v:5931$1768_Y + attribute \src "build/ls180/gateware/ls180.v:5950.32-5950.78" + wire $eq$build/ls180/gateware/ls180.v:5950$1771_Y + attribute \src "build/ls180/gateware/ls180.v:5952.99-5952.143" + wire $eq$build/ls180/gateware/ls180.v:5952$1773_Y + attribute \src "build/ls180/gateware/ls180.v:5953.102-5953.146" + wire $eq$build/ls180/gateware/ls180.v:5953$1777_Y + attribute \src "build/ls180/gateware/ls180.v:5955.99-5955.143" + wire $eq$build/ls180/gateware/ls180.v:5955$1780_Y + attribute \src "build/ls180/gateware/ls180.v:5956.102-5956.146" + wire $eq$build/ls180/gateware/ls180.v:5956$1784_Y + attribute \src "build/ls180/gateware/ls180.v:5958.97-5958.141" + wire $eq$build/ls180/gateware/ls180.v:5958$1787_Y + attribute \src "build/ls180/gateware/ls180.v:5959.100-5959.144" + wire $eq$build/ls180/gateware/ls180.v:5959$1791_Y + attribute \src "build/ls180/gateware/ls180.v:5961.96-5961.140" + wire $eq$build/ls180/gateware/ls180.v:5961$1794_Y + attribute \src "build/ls180/gateware/ls180.v:5962.99-5962.143" + wire $eq$build/ls180/gateware/ls180.v:5962$1798_Y + attribute \src "build/ls180/gateware/ls180.v:5964.95-5964.139" + wire $eq$build/ls180/gateware/ls180.v:5964$1801_Y + attribute \src "build/ls180/gateware/ls180.v:5965.98-5965.142" + wire $eq$build/ls180/gateware/ls180.v:5965$1805_Y + attribute \src "build/ls180/gateware/ls180.v:5967.94-5967.138" + wire $eq$build/ls180/gateware/ls180.v:5967$1808_Y + attribute \src "build/ls180/gateware/ls180.v:5968.97-5968.141" + wire $eq$build/ls180/gateware/ls180.v:5968$1812_Y + attribute \src "build/ls180/gateware/ls180.v:5970.100-5970.144" + wire $eq$build/ls180/gateware/ls180.v:5970$1815_Y + attribute \src "build/ls180/gateware/ls180.v:5971.103-5971.147" + wire $eq$build/ls180/gateware/ls180.v:5971$1819_Y + attribute \src "build/ls180/gateware/ls180.v:5973.103-5973.147" + wire $eq$build/ls180/gateware/ls180.v:5973$1822_Y + attribute \src "build/ls180/gateware/ls180.v:5974.106-5974.150" + wire $eq$build/ls180/gateware/ls180.v:5974$1826_Y + attribute \src "build/ls180/gateware/ls180.v:5976.103-5976.147" + wire $eq$build/ls180/gateware/ls180.v:5976$1829_Y + attribute \src "build/ls180/gateware/ls180.v:5977.106-5977.150" + wire $eq$build/ls180/gateware/ls180.v:5977$1833_Y + attribute \src "build/ls180/gateware/ls180.v:5998.33-5998.79" + wire $eq$build/ls180/gateware/ls180.v:5998$1836_Y + attribute \src "build/ls180/gateware/ls180.v:6000.99-6000.144" + wire $eq$build/ls180/gateware/ls180.v:6000$1838_Y + attribute \src "build/ls180/gateware/ls180.v:6001.102-6001.147" + wire $eq$build/ls180/gateware/ls180.v:6001$1842_Y + attribute \src "build/ls180/gateware/ls180.v:6003.99-6003.144" + wire $eq$build/ls180/gateware/ls180.v:6003$1845_Y + attribute \src "build/ls180/gateware/ls180.v:6004.102-6004.147" + wire $eq$build/ls180/gateware/ls180.v:6004$1849_Y + attribute \src "build/ls180/gateware/ls180.v:6006.99-6006.144" + wire $eq$build/ls180/gateware/ls180.v:6006$1852_Y + attribute \src "build/ls180/gateware/ls180.v:6007.102-6007.147" + wire $eq$build/ls180/gateware/ls180.v:6007$1856_Y + attribute \src "build/ls180/gateware/ls180.v:6009.99-6009.144" + wire $eq$build/ls180/gateware/ls180.v:6009$1859_Y + attribute \src "build/ls180/gateware/ls180.v:6010.102-6010.147" + wire $eq$build/ls180/gateware/ls180.v:6010$1863_Y + attribute \src "build/ls180/gateware/ls180.v:6012.101-6012.146" + wire $eq$build/ls180/gateware/ls180.v:6012$1866_Y + attribute \src "build/ls180/gateware/ls180.v:6013.104-6013.149" + wire $eq$build/ls180/gateware/ls180.v:6013$1870_Y + attribute \src "build/ls180/gateware/ls180.v:6015.101-6015.146" + wire $eq$build/ls180/gateware/ls180.v:6015$1873_Y + attribute \src "build/ls180/gateware/ls180.v:6016.104-6016.149" + wire $eq$build/ls180/gateware/ls180.v:6016$1877_Y + attribute \src "build/ls180/gateware/ls180.v:6018.101-6018.146" + wire $eq$build/ls180/gateware/ls180.v:6018$1880_Y + attribute \src "build/ls180/gateware/ls180.v:6019.104-6019.149" + wire $eq$build/ls180/gateware/ls180.v:6019$1884_Y + attribute \src "build/ls180/gateware/ls180.v:6021.101-6021.146" + wire $eq$build/ls180/gateware/ls180.v:6021$1887_Y + attribute \src "build/ls180/gateware/ls180.v:6022.104-6022.149" + wire $eq$build/ls180/gateware/ls180.v:6022$1891_Y + attribute \src "build/ls180/gateware/ls180.v:6024.97-6024.142" + wire $eq$build/ls180/gateware/ls180.v:6024$1894_Y + attribute \src "build/ls180/gateware/ls180.v:6025.100-6025.145" + wire $eq$build/ls180/gateware/ls180.v:6025$1898_Y + attribute \src "build/ls180/gateware/ls180.v:6027.107-6027.152" + wire $eq$build/ls180/gateware/ls180.v:6027$1901_Y + attribute \src "build/ls180/gateware/ls180.v:6028.110-6028.155" + wire $eq$build/ls180/gateware/ls180.v:6028$1905_Y + attribute \src "build/ls180/gateware/ls180.v:6030.100-6030.146" + wire $eq$build/ls180/gateware/ls180.v:6030$1908_Y + attribute \src "build/ls180/gateware/ls180.v:6031.103-6031.149" + wire $eq$build/ls180/gateware/ls180.v:6031$1912_Y + attribute \src "build/ls180/gateware/ls180.v:6033.100-6033.146" + wire $eq$build/ls180/gateware/ls180.v:6033$1915_Y + attribute \src "build/ls180/gateware/ls180.v:6034.103-6034.149" + wire $eq$build/ls180/gateware/ls180.v:6034$1919_Y + attribute \src "build/ls180/gateware/ls180.v:6036.100-6036.146" + wire $eq$build/ls180/gateware/ls180.v:6036$1922_Y + attribute \src "build/ls180/gateware/ls180.v:6037.103-6037.149" + wire $eq$build/ls180/gateware/ls180.v:6037$1926_Y + attribute \src "build/ls180/gateware/ls180.v:6039.100-6039.146" + wire $eq$build/ls180/gateware/ls180.v:6039$1929_Y + attribute \src "build/ls180/gateware/ls180.v:6040.103-6040.149" + wire $eq$build/ls180/gateware/ls180.v:6040$1933_Y + attribute \src "build/ls180/gateware/ls180.v:6042.118-6042.164" + wire $eq$build/ls180/gateware/ls180.v:6042$1936_Y + attribute \src "build/ls180/gateware/ls180.v:6043.121-6043.167" + wire $eq$build/ls180/gateware/ls180.v:6043$1940_Y + attribute \src "build/ls180/gateware/ls180.v:6045.119-6045.165" + wire $eq$build/ls180/gateware/ls180.v:6045$1943_Y + attribute \src "build/ls180/gateware/ls180.v:6046.122-6046.168" + wire $eq$build/ls180/gateware/ls180.v:6046$1947_Y + attribute \src "build/ls180/gateware/ls180.v:6048.104-6048.150" + wire $eq$build/ls180/gateware/ls180.v:6048$1950_Y + attribute \src "build/ls180/gateware/ls180.v:6049.107-6049.153" + wire $eq$build/ls180/gateware/ls180.v:6049$1954_Y + attribute \src "build/ls180/gateware/ls180.v:6066.33-6066.79" + wire $eq$build/ls180/gateware/ls180.v:6066$1956_Y + attribute \src "build/ls180/gateware/ls180.v:6068.102-6068.147" + wire $eq$build/ls180/gateware/ls180.v:6068$1958_Y + attribute \src "build/ls180/gateware/ls180.v:6069.105-6069.150" + wire $eq$build/ls180/gateware/ls180.v:6069$1962_Y + attribute \src "build/ls180/gateware/ls180.v:6071.100-6071.145" + wire $eq$build/ls180/gateware/ls180.v:6071$1965_Y + attribute \src "build/ls180/gateware/ls180.v:6072.103-6072.148" + wire $eq$build/ls180/gateware/ls180.v:6072$1969_Y + attribute \src "build/ls180/gateware/ls180.v:6074.101-6074.146" + wire $eq$build/ls180/gateware/ls180.v:6074$1972_Y + attribute \src "build/ls180/gateware/ls180.v:6075.104-6075.149" + wire $eq$build/ls180/gateware/ls180.v:6075$1976_Y + attribute \src "build/ls180/gateware/ls180.v:6077.117-6077.162" + wire $eq$build/ls180/gateware/ls180.v:6077$1979_Y + attribute \src "build/ls180/gateware/ls180.v:6078.120-6078.165" + wire $eq$build/ls180/gateware/ls180.v:6078$1983_Y + attribute \src "build/ls180/gateware/ls180.v:6080.118-6080.163" + wire $eq$build/ls180/gateware/ls180.v:6080$1986_Y + attribute \src "build/ls180/gateware/ls180.v:6081.121-6081.166" + wire $eq$build/ls180/gateware/ls180.v:6081$1990_Y + attribute \src "build/ls180/gateware/ls180.v:6083.104-6083.149" + wire $eq$build/ls180/gateware/ls180.v:6083$1993_Y + attribute \src "build/ls180/gateware/ls180.v:6084.107-6084.152" + wire $eq$build/ls180/gateware/ls180.v:6084$1997_Y + attribute \src "build/ls180/gateware/ls180.v:6086.101-6086.146" + wire $eq$build/ls180/gateware/ls180.v:6086$2000_Y + attribute \src "build/ls180/gateware/ls180.v:6087.104-6087.149" + wire $eq$build/ls180/gateware/ls180.v:6087$2004_Y + attribute \src "build/ls180/gateware/ls180.v:6089.100-6089.145" + wire $eq$build/ls180/gateware/ls180.v:6089$2007_Y + attribute \src "build/ls180/gateware/ls180.v:6090.103-6090.148" + wire $eq$build/ls180/gateware/ls180.v:6090$2011_Y + attribute \src "build/ls180/gateware/ls180.v:6100.33-6100.79" + wire $eq$build/ls180/gateware/ls180.v:6100$2013_Y + attribute \src "build/ls180/gateware/ls180.v:6102.106-6102.151" + wire $eq$build/ls180/gateware/ls180.v:6102$2015_Y + attribute \src "build/ls180/gateware/ls180.v:6103.109-6103.154" + wire $eq$build/ls180/gateware/ls180.v:6103$2019_Y + attribute \src "build/ls180/gateware/ls180.v:6105.106-6105.151" + wire $eq$build/ls180/gateware/ls180.v:6105$2022_Y + attribute \src "build/ls180/gateware/ls180.v:6106.109-6106.154" + wire $eq$build/ls180/gateware/ls180.v:6106$2026_Y + attribute \src "build/ls180/gateware/ls180.v:6108.106-6108.151" + wire $eq$build/ls180/gateware/ls180.v:6108$2029_Y + attribute \src "build/ls180/gateware/ls180.v:6109.109-6109.154" + wire $eq$build/ls180/gateware/ls180.v:6109$2033_Y + attribute \src "build/ls180/gateware/ls180.v:6111.106-6111.151" + wire $eq$build/ls180/gateware/ls180.v:6111$2036_Y + attribute \src "build/ls180/gateware/ls180.v:6112.109-6112.154" + wire $eq$build/ls180/gateware/ls180.v:6112$2040_Y + attribute \src "build/ls180/gateware/ls180.v:6487.41-6487.81" + wire $eq$build/ls180/gateware/ls180.v:6487$2075_Y + attribute \src "build/ls180/gateware/ls180.v:6487.144-6487.177" + wire $eq$build/ls180/gateware/ls180.v:6487$2076_Y + attribute \src "build/ls180/gateware/ls180.v:6487.219-6487.252" + wire $eq$build/ls180/gateware/ls180.v:6487$2079_Y + attribute \src "build/ls180/gateware/ls180.v:6487.294-6487.327" + wire $eq$build/ls180/gateware/ls180.v:6487$2082_Y + attribute \src "build/ls180/gateware/ls180.v:6511.41-6511.81" + wire $eq$build/ls180/gateware/ls180.v:6511$2091_Y + attribute \src "build/ls180/gateware/ls180.v:6511.144-6511.177" + wire $eq$build/ls180/gateware/ls180.v:6511$2092_Y + attribute \src "build/ls180/gateware/ls180.v:6511.219-6511.252" + wire $eq$build/ls180/gateware/ls180.v:6511$2095_Y + attribute \src "build/ls180/gateware/ls180.v:6511.294-6511.327" + wire $eq$build/ls180/gateware/ls180.v:6511$2098_Y + attribute \src "build/ls180/gateware/ls180.v:6535.41-6535.81" + wire $eq$build/ls180/gateware/ls180.v:6535$2107_Y + attribute \src "build/ls180/gateware/ls180.v:6535.144-6535.177" + wire $eq$build/ls180/gateware/ls180.v:6535$2108_Y + attribute \src "build/ls180/gateware/ls180.v:6535.219-6535.252" + wire $eq$build/ls180/gateware/ls180.v:6535$2111_Y + attribute \src "build/ls180/gateware/ls180.v:6535.294-6535.327" + wire $eq$build/ls180/gateware/ls180.v:6535$2114_Y + attribute \src "build/ls180/gateware/ls180.v:6559.41-6559.81" + wire $eq$build/ls180/gateware/ls180.v:6559$2123_Y + attribute \src "build/ls180/gateware/ls180.v:6559.144-6559.177" + wire $eq$build/ls180/gateware/ls180.v:6559$2124_Y + attribute \src "build/ls180/gateware/ls180.v:6559.219-6559.252" + wire $eq$build/ls180/gateware/ls180.v:6559$2127_Y + attribute \src "build/ls180/gateware/ls180.v:6559.294-6559.327" + wire $eq$build/ls180/gateware/ls180.v:6559$2130_Y + attribute \src "build/ls180/gateware/ls180.v:7096.9-7096.45" + wire $eq$build/ls180/gateware/ls180.v:7096$2201_Y + attribute \src "build/ls180/gateware/ls180.v:7099.10-7099.46" + wire $eq$build/ls180/gateware/ls180.v:7099$2202_Y + attribute \src "build/ls180/gateware/ls180.v:7125.9-7125.45" + wire $eq$build/ls180/gateware/ls180.v:7125$2208_Y + attribute \src "build/ls180/gateware/ls180.v:7130.10-7130.46" + wire $eq$build/ls180/gateware/ls180.v:7130$2209_Y + attribute \src "build/ls180/gateware/ls180.v:7220.8-7220.44" + wire $eq$build/ls180/gateware/ls180.v:7220$2237_Y + attribute \src "build/ls180/gateware/ls180.v:7251.8-7251.42" + wire $eq$build/ls180/gateware/ls180.v:7251$2245_Y + attribute \src "build/ls180/gateware/ls180.v:7271.38-7271.74" + wire $eq$build/ls180/gateware/ls180.v:7271$2248_Y + attribute \src "build/ls180/gateware/ls180.v:7278.7-7278.43" + wire $eq$build/ls180/gateware/ls180.v:7278$2250_Y + attribute \src "build/ls180/gateware/ls180.v:7285.7-7285.43" + wire $eq$build/ls180/gateware/ls180.v:7285$2251_Y + attribute \src "build/ls180/gateware/ls180.v:7293.7-7293.43" + wire $eq$build/ls180/gateware/ls180.v:7293$2252_Y + attribute \src "build/ls180/gateware/ls180.v:7345.9-7345.54" + wire $eq$build/ls180/gateware/ls180.v:7345$2270_Y + attribute \src "build/ls180/gateware/ls180.v:7391.9-7391.54" + wire $eq$build/ls180/gateware/ls180.v:7391$2286_Y + attribute \src "build/ls180/gateware/ls180.v:7437.9-7437.54" + wire $eq$build/ls180/gateware/ls180.v:7437$2302_Y + attribute \src "build/ls180/gateware/ls180.v:7483.9-7483.54" + wire $eq$build/ls180/gateware/ls180.v:7483$2318_Y + attribute \src "build/ls180/gateware/ls180.v:7633.9-7633.41" + wire $eq$build/ls180/gateware/ls180.v:7633$2330_Y + attribute \src "build/ls180/gateware/ls180.v:7648.9-7648.41" + wire $eq$build/ls180/gateware/ls180.v:7648$2333_Y + attribute \src "build/ls180/gateware/ls180.v:7654.49-7654.82" + wire $eq$build/ls180/gateware/ls180.v:7654$2334_Y + attribute \src "build/ls180/gateware/ls180.v:7654.131-7654.164" + wire $eq$build/ls180/gateware/ls180.v:7654$2337_Y + attribute \src "build/ls180/gateware/ls180.v:7654.213-7654.246" + wire $eq$build/ls180/gateware/ls180.v:7654$2340_Y + attribute \src "build/ls180/gateware/ls180.v:7654.295-7654.328" + wire $eq$build/ls180/gateware/ls180.v:7654$2343_Y + attribute \src "build/ls180/gateware/ls180.v:7655.50-7655.83" + wire $eq$build/ls180/gateware/ls180.v:7655$2346_Y + attribute \src "build/ls180/gateware/ls180.v:7655.132-7655.165" + wire $eq$build/ls180/gateware/ls180.v:7655$2349_Y + attribute \src "build/ls180/gateware/ls180.v:7655.214-7655.247" + wire $eq$build/ls180/gateware/ls180.v:7655$2352_Y + attribute \src "build/ls180/gateware/ls180.v:7655.296-7655.329" + wire $eq$build/ls180/gateware/ls180.v:7655$2355_Y + attribute \src "build/ls180/gateware/ls180.v:7736.9-7736.54" + wire $eq$build/ls180/gateware/ls180.v:7736$2369_Y + attribute \src "build/ls180/gateware/ls180.v:7817.9-7817.55" + wire $eq$build/ls180/gateware/ls180.v:7817$2381_Y + attribute \src "build/ls180/gateware/ls180.v:7896.9-7896.56" + wire $eq$build/ls180/gateware/ls180.v:7896$2393_Y + attribute \src "build/ls180/gateware/ls180.v:8119.9-8119.56" + wire $eq$build/ls180/gateware/ls180.v:8119$2426_Y + attribute \src "build/ls180/gateware/ls180.v:4848.54-4848.97" + wire $gt$build/ls180/gateware/ls180.v:4848$896_Y + attribute \src "build/ls180/gateware/ls180.v:4854.7-4854.50" + wire $lt$build/ls180/gateware/ls180.v:4854$899_Y + attribute \src "build/ls180/gateware/ls180.v:9379.33-9379.36" + wire width 32 $memrd$\mem$build/ls180/gateware/ls180.v:9379$2472_DATA + attribute \src "build/ls180/gateware/ls180.v:9391.12-9391.19" + wire width 10 $memrd$\storage$build/ls180/gateware/ls180.v:9391$2477_DATA + attribute \src "build/ls180/gateware/ls180.v:9396.15-9396.22" + wire width 10 $memrd$\storage$build/ls180/gateware/ls180.v:9396$2479_DATA + attribute \src "build/ls180/gateware/ls180.v:9408.14-9408.23" + wire width 10 $memrd$\storage_1$build/ls180/gateware/ls180.v:9408$2484_DATA + attribute \src "build/ls180/gateware/ls180.v:9413.15-9413.24" + wire width 10 $memrd$\storage_1$build/ls180/gateware/ls180.v:9413$2486_DATA + attribute \src "build/ls180/gateware/ls180.v:9424.14-9424.23" + wire width 25 $memrd$\storage_2$build/ls180/gateware/ls180.v:9424$2491_DATA + attribute \src "build/ls180/gateware/ls180.v:9431.68-9431.77" + wire width 25 $memrd$\storage_2$build/ls180/gateware/ls180.v:9431$2493_DATA + attribute \src "build/ls180/gateware/ls180.v:9438.14-9438.23" + wire width 25 $memrd$\storage_3$build/ls180/gateware/ls180.v:9438$2498_DATA + attribute \src "build/ls180/gateware/ls180.v:9445.68-9445.77" + wire width 25 $memrd$\storage_3$build/ls180/gateware/ls180.v:9445$2500_DATA + attribute \src "build/ls180/gateware/ls180.v:9452.14-9452.23" + wire width 25 $memrd$\storage_4$build/ls180/gateware/ls180.v:9452$2505_DATA + attribute \src "build/ls180/gateware/ls180.v:9459.68-9459.77" + wire width 25 $memrd$\storage_4$build/ls180/gateware/ls180.v:9459$2507_DATA + attribute \src "build/ls180/gateware/ls180.v:9466.14-9466.23" + wire width 25 $memrd$\storage_5$build/ls180/gateware/ls180.v:9466$2512_DATA + attribute \src "build/ls180/gateware/ls180.v:9473.68-9473.77" + wire width 25 $memrd$\storage_5$build/ls180/gateware/ls180.v:9473$2514_DATA + attribute \src "build/ls180/gateware/ls180.v:9480.14-9480.23" + wire width 10 $memrd$\storage_6$build/ls180/gateware/ls180.v:9480$2519_DATA + attribute \src "build/ls180/gateware/ls180.v:9487.52-9487.61" + wire width 10 $memrd$\storage_6$build/ls180/gateware/ls180.v:9487$2521_DATA + attribute \src "build/ls180/gateware/ls180.v:9494.14-9494.23" + wire width 10 $memrd$\storage_7$build/ls180/gateware/ls180.v:9494$2526_DATA + attribute \src "build/ls180/gateware/ls180.v:9501.52-9501.61" + wire width 10 $memrd$\storage_7$build/ls180/gateware/ls180.v:9501$2528_DATA + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + wire width 16 $memwr$\mem$build/ls180/gateware/ls180.v:9369$1_ADDR + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + wire width 32 $memwr$\mem$build/ls180/gateware/ls180.v:9369$1_DATA + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + wire width 32 $memwr$\mem$build/ls180/gateware/ls180.v:9369$1_EN + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + wire width 16 $memwr$\mem$build/ls180/gateware/ls180.v:9371$2_ADDR + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + wire width 32 $memwr$\mem$build/ls180/gateware/ls180.v:9371$2_DATA + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + wire width 32 $memwr$\mem$build/ls180/gateware/ls180.v:9371$2_EN + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + wire width 16 $memwr$\mem$build/ls180/gateware/ls180.v:9373$3_ADDR + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + wire width 32 $memwr$\mem$build/ls180/gateware/ls180.v:9373$3_DATA + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + wire width 32 $memwr$\mem$build/ls180/gateware/ls180.v:9373$3_EN + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + wire width 16 $memwr$\mem$build/ls180/gateware/ls180.v:9375$4_ADDR + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + wire width 32 $memwr$\mem$build/ls180/gateware/ls180.v:9375$4_DATA + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + wire width 32 $memwr$\mem$build/ls180/gateware/ls180.v:9375$4_EN + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + wire width 4 $memwr$\storage$build/ls180/gateware/ls180.v:9390$5_ADDR + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + wire width 10 $memwr$\storage$build/ls180/gateware/ls180.v:9390$5_DATA + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + wire width 10 $memwr$\storage$build/ls180/gateware/ls180.v:9390$5_EN + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + wire width 4 $memwr$\storage_1$build/ls180/gateware/ls180.v:9407$6_ADDR + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + wire width 10 $memwr$\storage_1$build/ls180/gateware/ls180.v:9407$6_DATA + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + wire width 10 $memwr$\storage_1$build/ls180/gateware/ls180.v:9407$6_EN + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + wire width 3 $memwr$\storage_2$build/ls180/gateware/ls180.v:9423$7_ADDR + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + wire width 25 $memwr$\storage_2$build/ls180/gateware/ls180.v:9423$7_DATA + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + wire width 25 $memwr$\storage_2$build/ls180/gateware/ls180.v:9423$7_EN + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + wire width 3 $memwr$\storage_3$build/ls180/gateware/ls180.v:9437$8_ADDR + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + wire width 25 $memwr$\storage_3$build/ls180/gateware/ls180.v:9437$8_DATA + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + wire width 25 $memwr$\storage_3$build/ls180/gateware/ls180.v:9437$8_EN + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + wire width 3 $memwr$\storage_4$build/ls180/gateware/ls180.v:9451$9_ADDR + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + wire width 25 $memwr$\storage_4$build/ls180/gateware/ls180.v:9451$9_DATA + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + wire width 25 $memwr$\storage_4$build/ls180/gateware/ls180.v:9451$9_EN + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + wire width 3 $memwr$\storage_5$build/ls180/gateware/ls180.v:9465$10_ADDR + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + wire width 25 $memwr$\storage_5$build/ls180/gateware/ls180.v:9465$10_DATA + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + wire width 25 $memwr$\storage_5$build/ls180/gateware/ls180.v:9465$10_EN + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + wire width 5 $memwr$\storage_6$build/ls180/gateware/ls180.v:9479$11_ADDR + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + wire width 10 $memwr$\storage_6$build/ls180/gateware/ls180.v:9479$11_DATA + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + wire width 10 $memwr$\storage_6$build/ls180/gateware/ls180.v:9479$11_EN + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + wire width 5 $memwr$\storage_7$build/ls180/gateware/ls180.v:9493$12_ADDR + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + wire width 10 $memwr$\storage_7$build/ls180/gateware/ls180.v:9493$12_DATA + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + wire width 10 $memwr$\storage_7$build/ls180/gateware/ls180.v:9493$12_EN + attribute \src "build/ls180/gateware/ls180.v:2808.59-2808.104" + wire $ne$build/ls180/gateware/ls180.v:2808$75_Y + attribute \src "build/ls180/gateware/ls180.v:2809.59-2809.103" + wire $ne$build/ls180/gateware/ls180.v:2809$76_Y + attribute \src "build/ls180/gateware/ls180.v:2838.59-2838.104" + wire $ne$build/ls180/gateware/ls180.v:2838$86_Y + attribute \src "build/ls180/gateware/ls180.v:2839.59-2839.103" + wire $ne$build/ls180/gateware/ls180.v:2839$87_Y + attribute \src "build/ls180/gateware/ls180.v:2840.47-2840.83" + wire $ne$build/ls180/gateware/ls180.v:2840$88_Y + attribute \src "build/ls180/gateware/ls180.v:3006.70-3006.104" + wire $ne$build/ls180/gateware/ls180.v:3006$103_Y + attribute \src "build/ls180/gateware/ls180.v:3067.8-3067.142" + wire $ne$build/ls180/gateware/ls180.v:3067$122_Y + attribute \src "build/ls180/gateware/ls180.v:3099.75-3099.133" + wire $ne$build/ls180/gateware/ls180.v:3099$129_Y + attribute \src "build/ls180/gateware/ls180.v:3100.75-3100.133" + wire $ne$build/ls180/gateware/ls180.v:3100$130_Y + attribute \src "build/ls180/gateware/ls180.v:3224.8-3224.142" + wire $ne$build/ls180/gateware/ls180.v:3224$152_Y + attribute \src "build/ls180/gateware/ls180.v:3256.75-3256.133" + wire $ne$build/ls180/gateware/ls180.v:3256$159_Y + attribute \src "build/ls180/gateware/ls180.v:3257.75-3257.133" + wire $ne$build/ls180/gateware/ls180.v:3257$160_Y + attribute \src "build/ls180/gateware/ls180.v:3381.8-3381.142" + wire $ne$build/ls180/gateware/ls180.v:3381$182_Y + attribute \src "build/ls180/gateware/ls180.v:3413.75-3413.133" + wire $ne$build/ls180/gateware/ls180.v:3413$189_Y + attribute \src "build/ls180/gateware/ls180.v:3414.75-3414.133" + wire $ne$build/ls180/gateware/ls180.v:3414$190_Y + attribute \src "build/ls180/gateware/ls180.v:3538.8-3538.142" + wire $ne$build/ls180/gateware/ls180.v:3538$212_Y + attribute \src "build/ls180/gateware/ls180.v:3570.75-3570.133" + wire $ne$build/ls180/gateware/ls180.v:3570$219_Y + attribute \src "build/ls180/gateware/ls180.v:3571.75-3571.133" + wire $ne$build/ls180/gateware/ls180.v:3571$220_Y + attribute \src "build/ls180/gateware/ls180.v:4380.33-4380.91" + wire $ne$build/ls180/gateware/ls180.v:4380$663_Y + attribute \src "build/ls180/gateware/ls180.v:5027.10-5027.57" + wire $ne$build/ls180/gateware/ls180.v:5027$960_Y + attribute \src "build/ls180/gateware/ls180.v:5132.58-5132.101" + wire $ne$build/ls180/gateware/ls180.v:5132$974_Y + attribute \src "build/ls180/gateware/ls180.v:5133.58-5133.100" + wire $ne$build/ls180/gateware/ls180.v:5133$975_Y + attribute \src "build/ls180/gateware/ls180.v:5340.58-5340.101" + wire $ne$build/ls180/gateware/ls180.v:5340$1005_Y + attribute \src "build/ls180/gateware/ls180.v:5341.58-5341.100" + wire $ne$build/ls180/gateware/ls180.v:5341$1006_Y + attribute \src "build/ls180/gateware/ls180.v:5431.79-5431.119" + wire $ne$build/ls180/gateware/ls180.v:5431$1017_Y + attribute \src "build/ls180/gateware/ls180.v:7078.7-7078.66" + wire $ne$build/ls180/gateware/ls180.v:7078$2190_Y + attribute \src "build/ls180/gateware/ls180.v:7260.9-7260.43" + wire $ne$build/ls180/gateware/ls180.v:7260$2246_Y + attribute \src "build/ls180/gateware/ls180.v:7296.8-7296.44" + wire $ne$build/ls180/gateware/ls180.v:7296$2253_Y + attribute \src "build/ls180/gateware/ls180.v:8039.9-8039.54" + wire $ne$build/ls180/gateware/ls180.v:8039$2413_Y + attribute \src "build/ls180/gateware/ls180.v:2593.45-2593.80" + wire $not$build/ls180/gateware/ls180.v:2593$14_Y + attribute \src "build/ls180/gateware/ls180.v:2632.61-2632.94" + wire $not$build/ls180/gateware/ls180.v:2632$19_Y + attribute \src "build/ls180/gateware/ls180.v:2633.61-2633.94" + wire $not$build/ls180/gateware/ls180.v:2633$20_Y + attribute \src "build/ls180/gateware/ls180.v:2653.45-2653.80" + wire $not$build/ls180/gateware/ls180.v:2653$25_Y + attribute \src "build/ls180/gateware/ls180.v:2692.61-2692.94" + wire $not$build/ls180/gateware/ls180.v:2692$30_Y + attribute \src "build/ls180/gateware/ls180.v:2693.61-2693.94" + wire $not$build/ls180/gateware/ls180.v:2693$31_Y + attribute \src "build/ls180/gateware/ls180.v:2737.47-2737.88" + wire $not$build/ls180/gateware/ls180.v:2737$49_Y + attribute \src "build/ls180/gateware/ls180.v:2738.48-2738.91" + wire $not$build/ls180/gateware/ls180.v:2738$50_Y + attribute \src "build/ls180/gateware/ls180.v:2744.44-2744.85" + wire $not$build/ls180/gateware/ls180.v:2744$51_Y + attribute \src "build/ls180/gateware/ls180.v:2750.48-2750.91" + wire $not$build/ls180/gateware/ls180.v:2750$52_Y + attribute \src "build/ls180/gateware/ls180.v:2751.47-2751.88" + wire $not$build/ls180/gateware/ls180.v:2751$53_Y + attribute \src "build/ls180/gateware/ls180.v:2754.44-2754.87" + wire $not$build/ls180/gateware/ls180.v:2754$56_Y + attribute \src "build/ls180/gateware/ls180.v:2792.105-2792.144" + wire $not$build/ls180/gateware/ls180.v:2792$66_Y + attribute \src "build/ls180/gateware/ls180.v:2822.105-2822.144" + wire $not$build/ls180/gateware/ls180.v:2822$77_Y + attribute \src "build/ls180/gateware/ls180.v:2955.34-2955.64" + wire $not$build/ls180/gateware/ls180.v:2955$95_Y + attribute \src "build/ls180/gateware/ls180.v:2956.31-2956.61" + wire $not$build/ls180/gateware/ls180.v:2956$96_Y + attribute \src "build/ls180/gateware/ls180.v:2957.32-2957.62" + wire $not$build/ls180/gateware/ls180.v:2957$97_Y + attribute \src "build/ls180/gateware/ls180.v:2958.32-2958.62" + wire $not$build/ls180/gateware/ls180.v:2958$98_Y + attribute \src "build/ls180/gateware/ls180.v:3000.33-3000.56" + wire $not$build/ls180/gateware/ls180.v:3000$101_Y + attribute \src "build/ls180/gateware/ls180.v:3101.58-3101.106" + wire $not$build/ls180/gateware/ls180.v:3101$131_Y + attribute \src "build/ls180/gateware/ls180.v:3155.9-3155.45" + wire $not$build/ls180/gateware/ls180.v:3155$136_Y + attribute \src "build/ls180/gateware/ls180.v:3258.58-3258.106" + wire $not$build/ls180/gateware/ls180.v:3258$161_Y + attribute \src "build/ls180/gateware/ls180.v:3312.9-3312.45" + wire $not$build/ls180/gateware/ls180.v:3312$166_Y + attribute \src "build/ls180/gateware/ls180.v:3415.58-3415.106" + wire $not$build/ls180/gateware/ls180.v:3415$191_Y + attribute \src "build/ls180/gateware/ls180.v:3469.9-3469.45" + wire $not$build/ls180/gateware/ls180.v:3469$196_Y + attribute \src "build/ls180/gateware/ls180.v:3572.58-3572.106" + wire $not$build/ls180/gateware/ls180.v:3572$221_Y + attribute \src "build/ls180/gateware/ls180.v:3626.9-3626.45" + wire $not$build/ls180/gateware/ls180.v:3626$226_Y + attribute \src "build/ls180/gateware/ls180.v:3668.149-3668.187" + wire $not$build/ls180/gateware/ls180.v:3668$229_Y + attribute \src "build/ls180/gateware/ls180.v:3668.193-3668.230" + wire $not$build/ls180/gateware/ls180.v:3668$231_Y + attribute \src "build/ls180/gateware/ls180.v:3669.149-3669.187" + wire $not$build/ls180/gateware/ls180.v:3669$235_Y + attribute \src "build/ls180/gateware/ls180.v:3669.193-3669.230" + wire $not$build/ls180/gateware/ls180.v:3669$237_Y + attribute \src "build/ls180/gateware/ls180.v:3685.43-3685.73" + wire width 2 $not$build/ls180/gateware/ls180.v:3685$265_Y + attribute \src "build/ls180/gateware/ls180.v:3688.205-3688.245" + wire $not$build/ls180/gateware/ls180.v:3688$268_Y + attribute \src "build/ls180/gateware/ls180.v:3688.251-3688.290" + wire $not$build/ls180/gateware/ls180.v:3688$270_Y + attribute \src "build/ls180/gateware/ls180.v:3688.159-3688.292" + wire $not$build/ls180/gateware/ls180.v:3688$272_Y + attribute \src "build/ls180/gateware/ls180.v:3689.205-3689.245" + wire $not$build/ls180/gateware/ls180.v:3689$281_Y + attribute \src "build/ls180/gateware/ls180.v:3689.251-3689.290" + wire $not$build/ls180/gateware/ls180.v:3689$283_Y + attribute \src "build/ls180/gateware/ls180.v:3689.159-3689.292" + wire $not$build/ls180/gateware/ls180.v:3689$285_Y + attribute \src "build/ls180/gateware/ls180.v:3690.205-3690.245" + wire $not$build/ls180/gateware/ls180.v:3690$294_Y + attribute \src "build/ls180/gateware/ls180.v:3690.251-3690.290" + wire $not$build/ls180/gateware/ls180.v:3690$296_Y + attribute \src "build/ls180/gateware/ls180.v:3690.159-3690.292" + wire $not$build/ls180/gateware/ls180.v:3690$298_Y + attribute \src "build/ls180/gateware/ls180.v:3691.205-3691.245" + wire $not$build/ls180/gateware/ls180.v:3691$307_Y + attribute \src "build/ls180/gateware/ls180.v:3691.251-3691.290" + wire $not$build/ls180/gateware/ls180.v:3691$309_Y + attribute \src "build/ls180/gateware/ls180.v:3691.159-3691.292" + wire $not$build/ls180/gateware/ls180.v:3691$311_Y + attribute \src "build/ls180/gateware/ls180.v:3718.71-3718.103" + wire $not$build/ls180/gateware/ls180.v:3718$322_Y + attribute \src "build/ls180/gateware/ls180.v:3721.205-3721.245" + wire $not$build/ls180/gateware/ls180.v:3721$326_Y + attribute \src "build/ls180/gateware/ls180.v:3721.251-3721.290" + wire $not$build/ls180/gateware/ls180.v:3721$328_Y + attribute \src "build/ls180/gateware/ls180.v:3721.159-3721.292" + wire $not$build/ls180/gateware/ls180.v:3721$330_Y + attribute \src "build/ls180/gateware/ls180.v:3722.205-3722.245" + wire $not$build/ls180/gateware/ls180.v:3722$339_Y + attribute \src "build/ls180/gateware/ls180.v:3722.251-3722.290" + wire $not$build/ls180/gateware/ls180.v:3722$341_Y + attribute \src "build/ls180/gateware/ls180.v:3722.159-3722.292" + wire $not$build/ls180/gateware/ls180.v:3722$343_Y + attribute \src "build/ls180/gateware/ls180.v:3723.205-3723.245" + wire $not$build/ls180/gateware/ls180.v:3723$352_Y + attribute \src "build/ls180/gateware/ls180.v:3723.251-3723.290" + wire $not$build/ls180/gateware/ls180.v:3723$354_Y + attribute \src "build/ls180/gateware/ls180.v:3723.159-3723.292" + wire $not$build/ls180/gateware/ls180.v:3723$356_Y + attribute \src "build/ls180/gateware/ls180.v:3724.205-3724.245" + wire $not$build/ls180/gateware/ls180.v:3724$365_Y + attribute \src "build/ls180/gateware/ls180.v:3724.251-3724.290" + wire $not$build/ls180/gateware/ls180.v:3724$367_Y + attribute \src "build/ls180/gateware/ls180.v:3724.159-3724.292" + wire $not$build/ls180/gateware/ls180.v:3724$369_Y + attribute \src "build/ls180/gateware/ls180.v:3787.71-3787.103" + wire $not$build/ls180/gateware/ls180.v:3787$408_Y + attribute \src "build/ls180/gateware/ls180.v:3808.112-3808.150" + wire $not$build/ls180/gateware/ls180.v:3808$411_Y + attribute \src "build/ls180/gateware/ls180.v:3808.156-3808.193" + wire $not$build/ls180/gateware/ls180.v:3808$413_Y + attribute \src "build/ls180/gateware/ls180.v:3808.68-3808.195" + wire $not$build/ls180/gateware/ls180.v:3808$415_Y + attribute \src "build/ls180/gateware/ls180.v:3816.11-3816.38" + wire $not$build/ls180/gateware/ls180.v:3816$418_Y + attribute \src "build/ls180/gateware/ls180.v:3846.112-3846.150" + wire $not$build/ls180/gateware/ls180.v:3846$420_Y + attribute \src "build/ls180/gateware/ls180.v:3846.156-3846.193" + wire $not$build/ls180/gateware/ls180.v:3846$422_Y + attribute \src "build/ls180/gateware/ls180.v:3846.68-3846.195" + wire $not$build/ls180/gateware/ls180.v:3846$424_Y + attribute \src "build/ls180/gateware/ls180.v:3854.11-3854.37" + wire $not$build/ls180/gateware/ls180.v:3854$427_Y + attribute \src "build/ls180/gateware/ls180.v:3864.87-3864.331" + wire $not$build/ls180/gateware/ls180.v:3864$439_Y + attribute \src "build/ls180/gateware/ls180.v:3865.35-3865.68" + wire $not$build/ls180/gateware/ls180.v:3865$442_Y + attribute \src "build/ls180/gateware/ls180.v:3865.73-3865.105" + wire $not$build/ls180/gateware/ls180.v:3865$443_Y + attribute \src "build/ls180/gateware/ls180.v:3869.87-3869.331" + wire $not$build/ls180/gateware/ls180.v:3869$455_Y + attribute \src "build/ls180/gateware/ls180.v:3870.35-3870.68" + wire $not$build/ls180/gateware/ls180.v:3870$458_Y + attribute \src "build/ls180/gateware/ls180.v:3870.73-3870.105" + wire $not$build/ls180/gateware/ls180.v:3870$459_Y + attribute \src "build/ls180/gateware/ls180.v:3874.87-3874.331" + wire $not$build/ls180/gateware/ls180.v:3874$471_Y + attribute \src "build/ls180/gateware/ls180.v:3875.35-3875.68" + wire $not$build/ls180/gateware/ls180.v:3875$474_Y + attribute \src "build/ls180/gateware/ls180.v:3875.73-3875.105" + wire $not$build/ls180/gateware/ls180.v:3875$475_Y + attribute \src "build/ls180/gateware/ls180.v:3879.87-3879.331" + wire $not$build/ls180/gateware/ls180.v:3879$487_Y + attribute \src "build/ls180/gateware/ls180.v:3880.35-3880.68" + wire $not$build/ls180/gateware/ls180.v:3880$490_Y + attribute \src "build/ls180/gateware/ls180.v:3880.73-3880.105" + wire $not$build/ls180/gateware/ls180.v:3880$491_Y + attribute \src "build/ls180/gateware/ls180.v:3884.128-3884.372" + wire $not$build/ls180/gateware/ls180.v:3884$504_Y + attribute \src "build/ls180/gateware/ls180.v:3884.502-3884.746" + wire $not$build/ls180/gateware/ls180.v:3884$520_Y + attribute \src "build/ls180/gateware/ls180.v:3884.876-3884.1120" + wire $not$build/ls180/gateware/ls180.v:3884$536_Y + attribute \src "build/ls180/gateware/ls180.v:3884.1250-3884.1494" + wire $not$build/ls180/gateware/ls180.v:3884$552_Y + attribute \src "build/ls180/gateware/ls180.v:3906.32-3906.50" + wire $not$build/ls180/gateware/ls180.v:3906$558_Y + attribute \src "build/ls180/gateware/ls180.v:3945.30-3945.50" + wire $not$build/ls180/gateware/ls180.v:3945$563_Y + attribute \src "build/ls180/gateware/ls180.v:3946.30-3946.50" + wire $not$build/ls180/gateware/ls180.v:3946$564_Y + attribute \src "build/ls180/gateware/ls180.v:3971.27-3971.48" + wire $not$build/ls180/gateware/ls180.v:3971$570_Y + attribute \src "build/ls180/gateware/ls180.v:3972.30-3972.50" + wire $not$build/ls180/gateware/ls180.v:3972$571_Y + attribute \src "build/ls180/gateware/ls180.v:3973.80-3973.98" + wire $not$build/ls180/gateware/ls180.v:3973$573_Y + attribute \src "build/ls180/gateware/ls180.v:3974.107-3974.127" + wire $not$build/ls180/gateware/ls180.v:3974$577_Y + attribute \src "build/ls180/gateware/ls180.v:3975.78-3975.103" + wire $not$build/ls180/gateware/ls180.v:3975$580_Y + attribute \src "build/ls180/gateware/ls180.v:3976.91-3976.111" + wire $not$build/ls180/gateware/ls180.v:3976$583_Y + attribute \src "build/ls180/gateware/ls180.v:4094.62-4094.88" + wire $not$build/ls180/gateware/ls180.v:4094$622_Y + attribute \src "build/ls180/gateware/ls180.v:4235.55-4235.98" + wire $not$build/ls180/gateware/ls180.v:4235$636_Y + attribute \src "build/ls180/gateware/ls180.v:4238.49-4238.88" + wire $not$build/ls180/gateware/ls180.v:4238$639_Y + attribute \src "build/ls180/gateware/ls180.v:4362.56-4362.100" + wire $not$build/ls180/gateware/ls180.v:4362$657_Y + attribute \src "build/ls180/gateware/ls180.v:4365.50-4365.90" + wire $not$build/ls180/gateware/ls180.v:4365$660_Y + attribute \src "build/ls180/gateware/ls180.v:4415.31-4415.60" + wire $not$build/ls180/gateware/ls180.v:4415$666_Y + attribute \src "build/ls180/gateware/ls180.v:4496.57-4496.102" + wire $not$build/ls180/gateware/ls180.v:4496$672_Y + attribute \src "build/ls180/gateware/ls180.v:4499.51-4499.92" + wire $not$build/ls180/gateware/ls180.v:4499$675_Y + attribute \src "build/ls180/gateware/ls180.v:4615.49-4615.88" + wire $not$build/ls180/gateware/ls180.v:4615$691_Y + attribute \src "build/ls180/gateware/ls180.v:5139.57-5139.102" + wire $not$build/ls180/gateware/ls180.v:5139$976_Y + attribute \src "build/ls180/gateware/ls180.v:5151.59-5151.116" + wire $not$build/ls180/gateware/ls180.v:5151$979_Y + attribute \src "build/ls180/gateware/ls180.v:5210.45-5210.88" + wire $not$build/ls180/gateware/ls180.v:5210$986_Y + attribute \src "build/ls180/gateware/ls180.v:5508.69-5508.88" + wire $not$build/ls180/gateware/ls180.v:5508$1051_Y + attribute \src "build/ls180/gateware/ls180.v:5525.63-5525.94" + wire $not$build/ls180/gateware/ls180.v:5525$1072_Y + attribute \src "build/ls180/gateware/ls180.v:5528.65-5528.96" + wire $not$build/ls180/gateware/ls180.v:5528$1079_Y + attribute \src "build/ls180/gateware/ls180.v:5531.65-5531.96" + wire $not$build/ls180/gateware/ls180.v:5531$1086_Y + attribute \src "build/ls180/gateware/ls180.v:5534.65-5534.96" + wire $not$build/ls180/gateware/ls180.v:5534$1093_Y + attribute \src "build/ls180/gateware/ls180.v:5537.65-5537.96" + wire $not$build/ls180/gateware/ls180.v:5537$1100_Y + attribute \src "build/ls180/gateware/ls180.v:5540.68-5540.99" + wire $not$build/ls180/gateware/ls180.v:5540$1107_Y + attribute \src "build/ls180/gateware/ls180.v:5543.68-5543.99" + wire $not$build/ls180/gateware/ls180.v:5543$1114_Y + attribute \src "build/ls180/gateware/ls180.v:5546.68-5546.99" + wire $not$build/ls180/gateware/ls180.v:5546$1121_Y + attribute \src "build/ls180/gateware/ls180.v:5549.68-5549.99" + wire $not$build/ls180/gateware/ls180.v:5549$1128_Y + attribute \src "build/ls180/gateware/ls180.v:5563.59-5563.90" + wire $not$build/ls180/gateware/ls180.v:5563$1136_Y + attribute \src "build/ls180/gateware/ls180.v:5569.59-5569.90" + wire $not$build/ls180/gateware/ls180.v:5569$1144_Y + attribute \src "build/ls180/gateware/ls180.v:5575.66-5575.97" + wire $not$build/ls180/gateware/ls180.v:5575$1152_Y + attribute \src "build/ls180/gateware/ls180.v:5578.66-5578.97" + wire $not$build/ls180/gateware/ls180.v:5578$1159_Y + attribute \src "build/ls180/gateware/ls180.v:5581.66-5581.97" + wire $not$build/ls180/gateware/ls180.v:5581$1166_Y + attribute \src "build/ls180/gateware/ls180.v:5584.66-5584.97" + wire $not$build/ls180/gateware/ls180.v:5584$1173_Y + attribute \src "build/ls180/gateware/ls180.v:5587.66-5587.97" + wire $not$build/ls180/gateware/ls180.v:5587$1180_Y + attribute \src "build/ls180/gateware/ls180.v:5590.66-5590.97" + wire $not$build/ls180/gateware/ls180.v:5590$1187_Y + attribute \src "build/ls180/gateware/ls180.v:5593.66-5593.97" + wire $not$build/ls180/gateware/ls180.v:5593$1194_Y + attribute \src "build/ls180/gateware/ls180.v:5596.66-5596.97" + wire $not$build/ls180/gateware/ls180.v:5596$1201_Y + attribute \src "build/ls180/gateware/ls180.v:5599.68-5599.99" + wire $not$build/ls180/gateware/ls180.v:5599$1208_Y + attribute \src "build/ls180/gateware/ls180.v:5602.68-5602.99" + wire $not$build/ls180/gateware/ls180.v:5602$1215_Y + attribute \src "build/ls180/gateware/ls180.v:5605.68-5605.99" + wire $not$build/ls180/gateware/ls180.v:5605$1222_Y + attribute \src "build/ls180/gateware/ls180.v:5608.68-5608.99" + wire $not$build/ls180/gateware/ls180.v:5608$1229_Y + attribute \src "build/ls180/gateware/ls180.v:5611.68-5611.99" + wire $not$build/ls180/gateware/ls180.v:5611$1236_Y + attribute \src "build/ls180/gateware/ls180.v:5614.65-5614.96" + wire $not$build/ls180/gateware/ls180.v:5614$1243_Y + attribute \src "build/ls180/gateware/ls180.v:5617.66-5617.97" + wire $not$build/ls180/gateware/ls180.v:5617$1250_Y + attribute \src "build/ls180/gateware/ls180.v:5637.70-5637.101" + wire $not$build/ls180/gateware/ls180.v:5637$1258_Y + attribute \src "build/ls180/gateware/ls180.v:5640.70-5640.101" + wire $not$build/ls180/gateware/ls180.v:5640$1265_Y + attribute \src "build/ls180/gateware/ls180.v:5643.70-5643.101" + wire $not$build/ls180/gateware/ls180.v:5643$1272_Y + attribute \src "build/ls180/gateware/ls180.v:5646.70-5646.101" + wire $not$build/ls180/gateware/ls180.v:5646$1279_Y + attribute \src "build/ls180/gateware/ls180.v:5649.69-5649.100" + wire $not$build/ls180/gateware/ls180.v:5649$1286_Y + attribute \src "build/ls180/gateware/ls180.v:5652.69-5652.100" + wire $not$build/ls180/gateware/ls180.v:5652$1293_Y + attribute \src "build/ls180/gateware/ls180.v:5655.69-5655.100" + wire $not$build/ls180/gateware/ls180.v:5655$1300_Y + attribute \src "build/ls180/gateware/ls180.v:5658.69-5658.100" + wire $not$build/ls180/gateware/ls180.v:5658$1307_Y + attribute \src "build/ls180/gateware/ls180.v:5661.67-5661.98" + wire $not$build/ls180/gateware/ls180.v:5661$1314_Y + attribute \src "build/ls180/gateware/ls180.v:5664.71-5664.102" + wire $not$build/ls180/gateware/ls180.v:5664$1321_Y + attribute \src "build/ls180/gateware/ls180.v:5667.71-5667.102" + wire $not$build/ls180/gateware/ls180.v:5667$1328_Y + attribute \src "build/ls180/gateware/ls180.v:5670.71-5670.102" + wire $not$build/ls180/gateware/ls180.v:5670$1335_Y + attribute \src "build/ls180/gateware/ls180.v:5673.71-5673.102" + wire $not$build/ls180/gateware/ls180.v:5673$1342_Y + attribute \src "build/ls180/gateware/ls180.v:5676.71-5676.102" + wire $not$build/ls180/gateware/ls180.v:5676$1349_Y + attribute \src "build/ls180/gateware/ls180.v:5679.71-5679.102" + wire $not$build/ls180/gateware/ls180.v:5679$1356_Y + attribute \src "build/ls180/gateware/ls180.v:5682.70-5682.101" + wire $not$build/ls180/gateware/ls180.v:5682$1363_Y + attribute \src "build/ls180/gateware/ls180.v:5685.70-5685.101" + wire $not$build/ls180/gateware/ls180.v:5685$1370_Y + attribute \src "build/ls180/gateware/ls180.v:5688.70-5688.101" + wire $not$build/ls180/gateware/ls180.v:5688$1377_Y + attribute \src "build/ls180/gateware/ls180.v:5691.70-5691.101" + wire $not$build/ls180/gateware/ls180.v:5691$1384_Y + attribute \src "build/ls180/gateware/ls180.v:5694.70-5694.101" + wire $not$build/ls180/gateware/ls180.v:5694$1391_Y + attribute \src "build/ls180/gateware/ls180.v:5697.70-5697.101" + wire $not$build/ls180/gateware/ls180.v:5697$1398_Y + attribute \src "build/ls180/gateware/ls180.v:5700.70-5700.101" + wire $not$build/ls180/gateware/ls180.v:5700$1405_Y + attribute \src "build/ls180/gateware/ls180.v:5703.70-5703.101" + wire $not$build/ls180/gateware/ls180.v:5703$1412_Y + attribute \src "build/ls180/gateware/ls180.v:5706.70-5706.101" + wire $not$build/ls180/gateware/ls180.v:5706$1419_Y + attribute \src "build/ls180/gateware/ls180.v:5709.70-5709.101" + wire $not$build/ls180/gateware/ls180.v:5709$1426_Y + attribute \src "build/ls180/gateware/ls180.v:5712.66-5712.97" + wire $not$build/ls180/gateware/ls180.v:5712$1433_Y + attribute \src "build/ls180/gateware/ls180.v:5715.67-5715.98" + wire $not$build/ls180/gateware/ls180.v:5715$1440_Y + attribute \src "build/ls180/gateware/ls180.v:5718.70-5718.101" + wire $not$build/ls180/gateware/ls180.v:5718$1447_Y + attribute \src "build/ls180/gateware/ls180.v:5721.70-5721.101" + wire $not$build/ls180/gateware/ls180.v:5721$1454_Y + attribute \src "build/ls180/gateware/ls180.v:5724.69-5724.100" + wire $not$build/ls180/gateware/ls180.v:5724$1461_Y + attribute \src "build/ls180/gateware/ls180.v:5727.69-5727.100" + wire $not$build/ls180/gateware/ls180.v:5727$1468_Y + attribute \src "build/ls180/gateware/ls180.v:5730.69-5730.100" + wire $not$build/ls180/gateware/ls180.v:5730$1475_Y + attribute \src "build/ls180/gateware/ls180.v:5733.69-5733.100" + wire $not$build/ls180/gateware/ls180.v:5733$1482_Y + attribute \src "build/ls180/gateware/ls180.v:5772.66-5772.97" + wire $not$build/ls180/gateware/ls180.v:5772$1490_Y + attribute \src "build/ls180/gateware/ls180.v:5775.66-5775.97" + wire $not$build/ls180/gateware/ls180.v:5775$1497_Y + attribute \src "build/ls180/gateware/ls180.v:5778.66-5778.97" + wire $not$build/ls180/gateware/ls180.v:5778$1504_Y + attribute \src "build/ls180/gateware/ls180.v:5781.66-5781.97" + wire $not$build/ls180/gateware/ls180.v:5781$1511_Y + attribute \src "build/ls180/gateware/ls180.v:5784.66-5784.97" + wire $not$build/ls180/gateware/ls180.v:5784$1518_Y + attribute \src "build/ls180/gateware/ls180.v:5787.66-5787.97" + wire $not$build/ls180/gateware/ls180.v:5787$1525_Y + attribute \src "build/ls180/gateware/ls180.v:5790.66-5790.97" + wire $not$build/ls180/gateware/ls180.v:5790$1532_Y + attribute \src "build/ls180/gateware/ls180.v:5793.66-5793.97" + wire $not$build/ls180/gateware/ls180.v:5793$1539_Y + attribute \src "build/ls180/gateware/ls180.v:5796.68-5796.99" + wire $not$build/ls180/gateware/ls180.v:5796$1546_Y + attribute \src "build/ls180/gateware/ls180.v:5799.68-5799.99" + wire $not$build/ls180/gateware/ls180.v:5799$1553_Y + attribute \src "build/ls180/gateware/ls180.v:5802.68-5802.99" + wire $not$build/ls180/gateware/ls180.v:5802$1560_Y + attribute \src "build/ls180/gateware/ls180.v:5805.68-5805.99" + wire $not$build/ls180/gateware/ls180.v:5805$1567_Y + attribute \src "build/ls180/gateware/ls180.v:5808.68-5808.99" + wire $not$build/ls180/gateware/ls180.v:5808$1574_Y + attribute \src "build/ls180/gateware/ls180.v:5811.65-5811.96" + wire $not$build/ls180/gateware/ls180.v:5811$1581_Y + attribute \src "build/ls180/gateware/ls180.v:5814.66-5814.97" + wire $not$build/ls180/gateware/ls180.v:5814$1588_Y + attribute \src "build/ls180/gateware/ls180.v:5817.68-5817.99" + wire $not$build/ls180/gateware/ls180.v:5817$1595_Y + attribute \src "build/ls180/gateware/ls180.v:5820.68-5820.99" + wire $not$build/ls180/gateware/ls180.v:5820$1602_Y + attribute \src "build/ls180/gateware/ls180.v:5823.68-5823.99" + wire $not$build/ls180/gateware/ls180.v:5823$1609_Y + attribute \src "build/ls180/gateware/ls180.v:5826.68-5826.99" + wire $not$build/ls180/gateware/ls180.v:5826$1616_Y + attribute \src "build/ls180/gateware/ls180.v:5851.68-5851.99" + wire $not$build/ls180/gateware/ls180.v:5851$1624_Y + attribute \src "build/ls180/gateware/ls180.v:5854.73-5854.104" + wire $not$build/ls180/gateware/ls180.v:5854$1631_Y + attribute \src "build/ls180/gateware/ls180.v:5857.73-5857.104" + wire $not$build/ls180/gateware/ls180.v:5857$1638_Y + attribute \src "build/ls180/gateware/ls180.v:5860.67-5860.98" + wire $not$build/ls180/gateware/ls180.v:5860$1645_Y + attribute \src "build/ls180/gateware/ls180.v:5868.70-5868.101" + wire $not$build/ls180/gateware/ls180.v:5868$1653_Y + attribute \src "build/ls180/gateware/ls180.v:5871.74-5871.105" + wire $not$build/ls180/gateware/ls180.v:5871$1660_Y + attribute \src "build/ls180/gateware/ls180.v:5874.64-5874.95" + wire $not$build/ls180/gateware/ls180.v:5874$1667_Y + attribute \src "build/ls180/gateware/ls180.v:5877.74-5877.105" + wire $not$build/ls180/gateware/ls180.v:5877$1674_Y + attribute \src "build/ls180/gateware/ls180.v:5880.74-5880.105" + wire $not$build/ls180/gateware/ls180.v:5880$1681_Y + attribute \src "build/ls180/gateware/ls180.v:5883.75-5883.106" + wire $not$build/ls180/gateware/ls180.v:5883$1688_Y + attribute \src "build/ls180/gateware/ls180.v:5886.73-5886.104" + wire $not$build/ls180/gateware/ls180.v:5886$1695_Y + attribute \src "build/ls180/gateware/ls180.v:5889.73-5889.104" + wire $not$build/ls180/gateware/ls180.v:5889$1702_Y + attribute \src "build/ls180/gateware/ls180.v:5892.73-5892.104" + wire $not$build/ls180/gateware/ls180.v:5892$1709_Y + attribute \src "build/ls180/gateware/ls180.v:5895.73-5895.104" + wire $not$build/ls180/gateware/ls180.v:5895$1716_Y + attribute \src "build/ls180/gateware/ls180.v:5913.65-5913.96" + wire $not$build/ls180/gateware/ls180.v:5913$1724_Y + attribute \src "build/ls180/gateware/ls180.v:5916.65-5916.96" + wire $not$build/ls180/gateware/ls180.v:5916$1731_Y + attribute \src "build/ls180/gateware/ls180.v:5919.63-5919.94" + wire $not$build/ls180/gateware/ls180.v:5919$1738_Y + attribute \src "build/ls180/gateware/ls180.v:5922.62-5922.93" + wire $not$build/ls180/gateware/ls180.v:5922$1745_Y + attribute \src "build/ls180/gateware/ls180.v:5925.61-5925.92" + wire $not$build/ls180/gateware/ls180.v:5925$1752_Y + attribute \src "build/ls180/gateware/ls180.v:5928.60-5928.91" + wire $not$build/ls180/gateware/ls180.v:5928$1759_Y + attribute \src "build/ls180/gateware/ls180.v:5931.66-5931.97" + wire $not$build/ls180/gateware/ls180.v:5931$1766_Y + attribute \src "build/ls180/gateware/ls180.v:5953.65-5953.96" + wire $not$build/ls180/gateware/ls180.v:5953$1775_Y + attribute \src "build/ls180/gateware/ls180.v:5956.65-5956.96" + wire $not$build/ls180/gateware/ls180.v:5956$1782_Y + attribute \src "build/ls180/gateware/ls180.v:5959.63-5959.94" + wire $not$build/ls180/gateware/ls180.v:5959$1789_Y + attribute \src "build/ls180/gateware/ls180.v:5962.62-5962.93" + wire $not$build/ls180/gateware/ls180.v:5962$1796_Y + attribute \src "build/ls180/gateware/ls180.v:5965.61-5965.92" + wire $not$build/ls180/gateware/ls180.v:5965$1803_Y + attribute \src "build/ls180/gateware/ls180.v:5968.60-5968.91" + wire $not$build/ls180/gateware/ls180.v:5968$1810_Y + attribute \src "build/ls180/gateware/ls180.v:5971.66-5971.97" + wire $not$build/ls180/gateware/ls180.v:5971$1817_Y + attribute \src "build/ls180/gateware/ls180.v:5974.69-5974.100" + wire $not$build/ls180/gateware/ls180.v:5974$1824_Y + attribute \src "build/ls180/gateware/ls180.v:5977.69-5977.100" + wire $not$build/ls180/gateware/ls180.v:5977$1831_Y + attribute \src "build/ls180/gateware/ls180.v:6001.64-6001.96" + wire $not$build/ls180/gateware/ls180.v:6001$1840_Y + attribute \src "build/ls180/gateware/ls180.v:6004.64-6004.96" + wire $not$build/ls180/gateware/ls180.v:6004$1847_Y + attribute \src "build/ls180/gateware/ls180.v:6007.64-6007.96" + wire $not$build/ls180/gateware/ls180.v:6007$1854_Y + attribute \src "build/ls180/gateware/ls180.v:6010.64-6010.96" + wire $not$build/ls180/gateware/ls180.v:6010$1861_Y + attribute \src "build/ls180/gateware/ls180.v:6013.66-6013.98" + wire $not$build/ls180/gateware/ls180.v:6013$1868_Y + attribute \src "build/ls180/gateware/ls180.v:6016.66-6016.98" + wire $not$build/ls180/gateware/ls180.v:6016$1875_Y + attribute \src "build/ls180/gateware/ls180.v:6019.66-6019.98" + wire $not$build/ls180/gateware/ls180.v:6019$1882_Y + attribute \src "build/ls180/gateware/ls180.v:6022.66-6022.98" + wire $not$build/ls180/gateware/ls180.v:6022$1889_Y + attribute \src "build/ls180/gateware/ls180.v:6025.62-6025.94" + wire $not$build/ls180/gateware/ls180.v:6025$1896_Y + attribute \src "build/ls180/gateware/ls180.v:6028.72-6028.104" + wire $not$build/ls180/gateware/ls180.v:6028$1903_Y + attribute \src "build/ls180/gateware/ls180.v:6031.65-6031.97" + wire $not$build/ls180/gateware/ls180.v:6031$1910_Y + attribute \src "build/ls180/gateware/ls180.v:6034.65-6034.97" + wire $not$build/ls180/gateware/ls180.v:6034$1917_Y + attribute \src "build/ls180/gateware/ls180.v:6037.65-6037.97" + wire $not$build/ls180/gateware/ls180.v:6037$1924_Y + attribute \src "build/ls180/gateware/ls180.v:6040.65-6040.97" + wire $not$build/ls180/gateware/ls180.v:6040$1931_Y + attribute \src "build/ls180/gateware/ls180.v:6043.83-6043.115" + wire $not$build/ls180/gateware/ls180.v:6043$1938_Y + attribute \src "build/ls180/gateware/ls180.v:6046.84-6046.116" + wire $not$build/ls180/gateware/ls180.v:6046$1945_Y + attribute \src "build/ls180/gateware/ls180.v:6049.69-6049.101" + wire $not$build/ls180/gateware/ls180.v:6049$1952_Y + attribute \src "build/ls180/gateware/ls180.v:6069.67-6069.99" + wire $not$build/ls180/gateware/ls180.v:6069$1960_Y + attribute \src "build/ls180/gateware/ls180.v:6072.65-6072.97" + wire $not$build/ls180/gateware/ls180.v:6072$1967_Y + attribute \src "build/ls180/gateware/ls180.v:6075.66-6075.98" + wire $not$build/ls180/gateware/ls180.v:6075$1974_Y + attribute \src "build/ls180/gateware/ls180.v:6078.82-6078.114" + wire $not$build/ls180/gateware/ls180.v:6078$1981_Y + attribute \src "build/ls180/gateware/ls180.v:6081.83-6081.115" + wire $not$build/ls180/gateware/ls180.v:6081$1988_Y + attribute \src "build/ls180/gateware/ls180.v:6084.69-6084.101" + wire $not$build/ls180/gateware/ls180.v:6084$1995_Y + attribute \src "build/ls180/gateware/ls180.v:6087.66-6087.98" + wire $not$build/ls180/gateware/ls180.v:6087$2002_Y + attribute \src "build/ls180/gateware/ls180.v:6090.65-6090.97" + wire $not$build/ls180/gateware/ls180.v:6090$2009_Y + attribute \src "build/ls180/gateware/ls180.v:6103.71-6103.103" + wire $not$build/ls180/gateware/ls180.v:6103$2017_Y + attribute \src "build/ls180/gateware/ls180.v:6106.71-6106.103" + wire $not$build/ls180/gateware/ls180.v:6106$2024_Y + attribute \src "build/ls180/gateware/ls180.v:6109.71-6109.103" + wire $not$build/ls180/gateware/ls180.v:6109$2031_Y + attribute \src "build/ls180/gateware/ls180.v:6112.71-6112.103" + wire $not$build/ls180/gateware/ls180.v:6112$2038_Y + attribute \src "build/ls180/gateware/ls180.v:6487.86-6487.330" + wire $not$build/ls180/gateware/ls180.v:6487$2085_Y + attribute \src "build/ls180/gateware/ls180.v:6511.86-6511.330" + wire $not$build/ls180/gateware/ls180.v:6511$2101_Y + attribute \src "build/ls180/gateware/ls180.v:6535.86-6535.330" + wire $not$build/ls180/gateware/ls180.v:6535$2117_Y + attribute \src "build/ls180/gateware/ls180.v:6559.86-6559.330" + wire $not$build/ls180/gateware/ls180.v:6559$2133_Y + attribute \src "build/ls180/gateware/ls180.v:7005.18-7005.43" + wire $not$build/ls180/gateware/ls180.v:7005$2185_Y + attribute \src "build/ls180/gateware/ls180.v:7084.72-7084.101" + wire $not$build/ls180/gateware/ls180.v:7084$2193_Y + attribute \src "build/ls180/gateware/ls180.v:7088.39-7088.64" + wire $not$build/ls180/gateware/ls180.v:7088$2195_Y + attribute \src "build/ls180/gateware/ls180.v:7088.70-7088.98" + wire $not$build/ls180/gateware/ls180.v:7088$2197_Y + attribute \src "build/ls180/gateware/ls180.v:7117.7-7117.32" + wire $not$build/ls180/gateware/ls180.v:7117$2204_Y + attribute \src "build/ls180/gateware/ls180.v:7118.9-7118.29" + wire $not$build/ls180/gateware/ls180.v:7118$2205_Y + attribute \src "build/ls180/gateware/ls180.v:7151.8-7151.41" + wire $not$build/ls180/gateware/ls180.v:7151$2211_Y + attribute \src "build/ls180/gateware/ls180.v:7158.8-7158.41" + wire $not$build/ls180/gateware/ls180.v:7158$2213_Y + attribute \src "build/ls180/gateware/ls180.v:7168.104-7168.142" + wire $not$build/ls180/gateware/ls180.v:7168$2216_Y + attribute \src "build/ls180/gateware/ls180.v:7174.104-7174.142" + wire $not$build/ls180/gateware/ls180.v:7174$2221_Y + attribute \src "build/ls180/gateware/ls180.v:7175.8-7175.46" + wire $not$build/ls180/gateware/ls180.v:7175$2223_Y + attribute \src "build/ls180/gateware/ls180.v:7190.104-7190.142" + wire $not$build/ls180/gateware/ls180.v:7190$2227_Y + attribute \src "build/ls180/gateware/ls180.v:7196.104-7196.142" + wire $not$build/ls180/gateware/ls180.v:7196$2232_Y + attribute \src "build/ls180/gateware/ls180.v:7197.8-7197.46" + wire $not$build/ls180/gateware/ls180.v:7197$2234_Y + attribute \src "build/ls180/gateware/ls180.v:7235.8-7235.44" + wire $not$build/ls180/gateware/ls180.v:7235$2239_Y + attribute \src "build/ls180/gateware/ls180.v:7243.32-7243.55" + wire $not$build/ls180/gateware/ls180.v:7243$2241_Y + attribute \src "build/ls180/gateware/ls180.v:7313.136-7313.189" + wire $not$build/ls180/gateware/ls180.v:7313$2256_Y + attribute \src "build/ls180/gateware/ls180.v:7319.136-7319.189" + wire $not$build/ls180/gateware/ls180.v:7319$2261_Y + attribute \src "build/ls180/gateware/ls180.v:7320.8-7320.61" + wire $not$build/ls180/gateware/ls180.v:7320$2263_Y + attribute \src "build/ls180/gateware/ls180.v:7328.8-7328.56" + wire $not$build/ls180/gateware/ls180.v:7328$2266_Y + attribute \src "build/ls180/gateware/ls180.v:7343.8-7343.46" + wire $not$build/ls180/gateware/ls180.v:7343$2268_Y + attribute \src "build/ls180/gateware/ls180.v:7359.136-7359.189" + wire $not$build/ls180/gateware/ls180.v:7359$2272_Y + attribute \src "build/ls180/gateware/ls180.v:7365.136-7365.189" + wire $not$build/ls180/gateware/ls180.v:7365$2277_Y + attribute \src "build/ls180/gateware/ls180.v:7366.8-7366.61" + wire $not$build/ls180/gateware/ls180.v:7366$2279_Y + attribute \src "build/ls180/gateware/ls180.v:7374.8-7374.56" + wire $not$build/ls180/gateware/ls180.v:7374$2282_Y + attribute \src "build/ls180/gateware/ls180.v:7389.8-7389.46" + wire $not$build/ls180/gateware/ls180.v:7389$2284_Y + attribute \src "build/ls180/gateware/ls180.v:7405.136-7405.189" + wire $not$build/ls180/gateware/ls180.v:7405$2288_Y + attribute \src "build/ls180/gateware/ls180.v:7411.136-7411.189" + wire $not$build/ls180/gateware/ls180.v:7411$2293_Y + attribute \src "build/ls180/gateware/ls180.v:7412.8-7412.61" + wire $not$build/ls180/gateware/ls180.v:7412$2295_Y + attribute \src "build/ls180/gateware/ls180.v:7420.8-7420.56" + wire $not$build/ls180/gateware/ls180.v:7420$2298_Y + attribute \src "build/ls180/gateware/ls180.v:7435.8-7435.46" + wire $not$build/ls180/gateware/ls180.v:7435$2300_Y + attribute \src "build/ls180/gateware/ls180.v:7451.136-7451.189" + wire $not$build/ls180/gateware/ls180.v:7451$2304_Y + attribute \src "build/ls180/gateware/ls180.v:7457.136-7457.189" + wire $not$build/ls180/gateware/ls180.v:7457$2309_Y + attribute \src "build/ls180/gateware/ls180.v:7458.8-7458.61" + wire $not$build/ls180/gateware/ls180.v:7458$2311_Y + attribute \src "build/ls180/gateware/ls180.v:7466.8-7466.56" + wire $not$build/ls180/gateware/ls180.v:7466$2314_Y + attribute \src "build/ls180/gateware/ls180.v:7481.8-7481.46" + wire $not$build/ls180/gateware/ls180.v:7481$2316_Y + attribute \src "build/ls180/gateware/ls180.v:7489.7-7489.22" + wire $not$build/ls180/gateware/ls180.v:7489$2319_Y + attribute \src "build/ls180/gateware/ls180.v:7492.8-7492.29" + wire $not$build/ls180/gateware/ls180.v:7492$2320_Y + attribute \src "build/ls180/gateware/ls180.v:7496.7-7496.22" + wire $not$build/ls180/gateware/ls180.v:7496$2322_Y + attribute \src "build/ls180/gateware/ls180.v:7499.8-7499.29" + wire $not$build/ls180/gateware/ls180.v:7499$2323_Y + attribute \src "build/ls180/gateware/ls180.v:7618.30-7618.60" + wire $not$build/ls180/gateware/ls180.v:7618$2325_Y + attribute \src "build/ls180/gateware/ls180.v:7619.30-7619.60" + wire $not$build/ls180/gateware/ls180.v:7619$2326_Y + attribute \src "build/ls180/gateware/ls180.v:7620.29-7620.59" + wire $not$build/ls180/gateware/ls180.v:7620$2327_Y + attribute \src "build/ls180/gateware/ls180.v:7631.8-7631.33" + wire $not$build/ls180/gateware/ls180.v:7631$2328_Y + attribute \src "build/ls180/gateware/ls180.v:7646.8-7646.33" + wire $not$build/ls180/gateware/ls180.v:7646$2331_Y + attribute \src "build/ls180/gateware/ls180.v:7690.23-7690.31" + wire $not$build/ls180/gateware/ls180.v:7690$2362_Y + attribute \src "build/ls180/gateware/ls180.v:7690.36-7690.51" + wire $not$build/ls180/gateware/ls180.v:7690$2363_Y + attribute \src "build/ls180/gateware/ls180.v:7716.7-7716.32" + wire $not$build/ls180/gateware/ls180.v:7716$2366_Y + attribute \src "build/ls180/gateware/ls180.v:7788.8-7788.47" + wire $not$build/ls180/gateware/ls180.v:7788$2378_Y + attribute \src "build/ls180/gateware/ls180.v:7869.8-7869.48" + wire $not$build/ls180/gateware/ls180.v:7869$2390_Y + attribute \src "build/ls180/gateware/ls180.v:7930.8-7930.49" + wire $not$build/ls180/gateware/ls180.v:7930$2402_Y + attribute \src "build/ls180/gateware/ls180.v:8100.102-8100.139" + wire $not$build/ls180/gateware/ls180.v:8100$2416_Y + attribute \src "build/ls180/gateware/ls180.v:8106.102-8106.139" + wire $not$build/ls180/gateware/ls180.v:8106$2421_Y + attribute \src "build/ls180/gateware/ls180.v:8107.8-8107.45" + wire $not$build/ls180/gateware/ls180.v:8107$2423_Y + attribute \src "build/ls180/gateware/ls180.v:8186.102-8186.139" + wire $not$build/ls180/gateware/ls180.v:8186$2438_Y + attribute \src "build/ls180/gateware/ls180.v:8192.102-8192.139" + wire $not$build/ls180/gateware/ls180.v:8192$2443_Y + attribute \src "build/ls180/gateware/ls180.v:8193.8-8193.45" + wire $not$build/ls180/gateware/ls180.v:8193$2445_Y + attribute \src "build/ls180/gateware/ls180.v:8210.22-8210.37" + wire $not$build/ls180/gateware/ls180.v:8210$2449_Y + attribute \src "build/ls180/gateware/ls180.v:8210.42-8210.64" + wire $not$build/ls180/gateware/ls180.v:8210$2450_Y + attribute \src "build/ls180/gateware/ls180.v:8248.9-8248.28" + wire $not$build/ls180/gateware/ls180.v:8248$2453_Y + attribute \src "build/ls180/gateware/ls180.v:8263.9-8263.28" + wire $not$build/ls180/gateware/ls180.v:8263$2454_Y + attribute \src "build/ls180/gateware/ls180.v:8278.9-8278.28" + wire $not$build/ls180/gateware/ls180.v:8278$2455_Y + attribute \src "build/ls180/gateware/ls180.v:8293.9-8293.28" + wire $not$build/ls180/gateware/ls180.v:8293$2456_Y + attribute \src "build/ls180/gateware/ls180.v:8310.8-8310.21" + wire $not$build/ls180/gateware/ls180.v:8310$2457_Y + attribute \src "build/ls180/gateware/ls180.v:2634.10-2634.96" + wire $or$build/ls180/gateware/ls180.v:2634$21_Y + attribute \src "build/ls180/gateware/ls180.v:2694.10-2694.96" + wire $or$build/ls180/gateware/ls180.v:2694$32_Y + attribute \src "build/ls180/gateware/ls180.v:2753.54-2753.125" + wire $or$build/ls180/gateware/ls180.v:2753$55_Y + attribute \src "build/ls180/gateware/ls180.v:2777.37-2777.234" + wire $or$build/ls180/gateware/ls180.v:2777$65_Y + attribute \src "build/ls180/gateware/ls180.v:2792.104-2792.180" + wire $or$build/ls180/gateware/ls180.v:2792$67_Y + attribute \src "build/ls180/gateware/ls180.v:2803.96-2803.183" + wire $or$build/ls180/gateware/ls180.v:2803$72_Y + attribute \src "build/ls180/gateware/ls180.v:2822.104-2822.180" + wire $or$build/ls180/gateware/ls180.v:2822$78_Y + attribute \src "build/ls180/gateware/ls180.v:2833.96-2833.183" + wire $or$build/ls180/gateware/ls180.v:2833$83_Y + attribute \src "build/ls180/gateware/ls180.v:3006.39-3006.105" + wire $or$build/ls180/gateware/ls180.v:3006$104_Y + attribute \src "build/ls180/gateware/ls180.v:3049.59-3049.140" + wire $or$build/ls180/gateware/ls180.v:3049$108_Y + attribute \src "build/ls180/gateware/ls180.v:3050.44-3050.151" + wire $or$build/ls180/gateware/ls180.v:3050$109_Y + attribute \src "build/ls180/gateware/ls180.v:3058.45-3058.170" + wire width 13 $or$build/ls180/gateware/ls180.v:3058$113_Y + attribute \src "build/ls180/gateware/ls180.v:3095.127-3095.245" + wire $or$build/ls180/gateware/ls180.v:3095$126_Y + attribute \src "build/ls180/gateware/ls180.v:3101.57-3101.157" + wire $or$build/ls180/gateware/ls180.v:3101$132_Y + attribute \src "build/ls180/gateware/ls180.v:3206.59-3206.140" + wire $or$build/ls180/gateware/ls180.v:3206$138_Y + attribute \src "build/ls180/gateware/ls180.v:3207.44-3207.151" + wire $or$build/ls180/gateware/ls180.v:3207$139_Y + attribute \src "build/ls180/gateware/ls180.v:3215.45-3215.170" + wire width 13 $or$build/ls180/gateware/ls180.v:3215$143_Y + attribute \src "build/ls180/gateware/ls180.v:3252.127-3252.245" + wire $or$build/ls180/gateware/ls180.v:3252$156_Y + attribute \src "build/ls180/gateware/ls180.v:3258.57-3258.157" + wire $or$build/ls180/gateware/ls180.v:3258$162_Y + attribute \src "build/ls180/gateware/ls180.v:3363.59-3363.140" + wire $or$build/ls180/gateware/ls180.v:3363$168_Y + attribute \src "build/ls180/gateware/ls180.v:3364.44-3364.151" + wire $or$build/ls180/gateware/ls180.v:3364$169_Y + attribute \src "build/ls180/gateware/ls180.v:3372.45-3372.170" + wire width 13 $or$build/ls180/gateware/ls180.v:3372$173_Y + attribute \src "build/ls180/gateware/ls180.v:3409.127-3409.245" + wire $or$build/ls180/gateware/ls180.v:3409$186_Y + attribute \src "build/ls180/gateware/ls180.v:3415.57-3415.157" + wire $or$build/ls180/gateware/ls180.v:3415$192_Y + attribute \src "build/ls180/gateware/ls180.v:3520.59-3520.140" + wire $or$build/ls180/gateware/ls180.v:3520$198_Y + attribute \src "build/ls180/gateware/ls180.v:3521.44-3521.151" + wire $or$build/ls180/gateware/ls180.v:3521$199_Y + attribute \src "build/ls180/gateware/ls180.v:3529.45-3529.170" + wire width 13 $or$build/ls180/gateware/ls180.v:3529$203_Y + attribute \src "build/ls180/gateware/ls180.v:3566.127-3566.245" + wire $or$build/ls180/gateware/ls180.v:3566$216_Y + attribute \src "build/ls180/gateware/ls180.v:3572.57-3572.157" + wire $or$build/ls180/gateware/ls180.v:3572$222_Y + attribute \src "build/ls180/gateware/ls180.v:3671.107-3671.193" + wire $or$build/ls180/gateware/ls180.v:3671$242_Y + attribute \src "build/ls180/gateware/ls180.v:3674.39-3674.204" + wire $or$build/ls180/gateware/ls180.v:3674$248_Y + attribute \src "build/ls180/gateware/ls180.v:3674.38-3674.289" + wire $or$build/ls180/gateware/ls180.v:3674$250_Y + attribute \src "build/ls180/gateware/ls180.v:3674.37-3674.374" + wire $or$build/ls180/gateware/ls180.v:3674$252_Y + attribute \src "build/ls180/gateware/ls180.v:3675.40-3675.207" + wire $or$build/ls180/gateware/ls180.v:3675$255_Y + attribute \src "build/ls180/gateware/ls180.v:3675.39-3675.293" + wire $or$build/ls180/gateware/ls180.v:3675$257_Y + attribute \src "build/ls180/gateware/ls180.v:3675.38-3675.379" + wire $or$build/ls180/gateware/ls180.v:3675$259_Y + attribute \src "build/ls180/gateware/ls180.v:3688.158-3688.332" + wire $or$build/ls180/gateware/ls180.v:3688$273_Y + attribute \src "build/ls180/gateware/ls180.v:3688.75-3688.506" + wire $or$build/ls180/gateware/ls180.v:3688$278_Y + attribute \src "build/ls180/gateware/ls180.v:3689.158-3689.332" + wire $or$build/ls180/gateware/ls180.v:3689$286_Y + attribute \src "build/ls180/gateware/ls180.v:3689.75-3689.506" + wire $or$build/ls180/gateware/ls180.v:3689$291_Y + attribute \src "build/ls180/gateware/ls180.v:3690.158-3690.332" + wire $or$build/ls180/gateware/ls180.v:3690$299_Y + attribute \src "build/ls180/gateware/ls180.v:3690.75-3690.506" + wire $or$build/ls180/gateware/ls180.v:3690$304_Y + attribute \src "build/ls180/gateware/ls180.v:3691.158-3691.332" + wire $or$build/ls180/gateware/ls180.v:3691$312_Y + attribute \src "build/ls180/gateware/ls180.v:3691.75-3691.506" + wire $or$build/ls180/gateware/ls180.v:3691$317_Y + attribute \src "build/ls180/gateware/ls180.v:3718.36-3718.104" + wire $or$build/ls180/gateware/ls180.v:3718$323_Y + attribute \src "build/ls180/gateware/ls180.v:3721.158-3721.332" + wire $or$build/ls180/gateware/ls180.v:3721$331_Y + attribute \src "build/ls180/gateware/ls180.v:3721.75-3721.506" + wire $or$build/ls180/gateware/ls180.v:3721$336_Y + attribute \src "build/ls180/gateware/ls180.v:3722.158-3722.332" + wire $or$build/ls180/gateware/ls180.v:3722$344_Y + attribute \src "build/ls180/gateware/ls180.v:3722.75-3722.506" + wire $or$build/ls180/gateware/ls180.v:3722$349_Y + attribute \src "build/ls180/gateware/ls180.v:3723.158-3723.332" + wire $or$build/ls180/gateware/ls180.v:3723$357_Y + attribute \src "build/ls180/gateware/ls180.v:3723.75-3723.506" + wire $or$build/ls180/gateware/ls180.v:3723$362_Y + attribute \src "build/ls180/gateware/ls180.v:3724.158-3724.332" + wire $or$build/ls180/gateware/ls180.v:3724$370_Y + attribute \src "build/ls180/gateware/ls180.v:3724.75-3724.506" + wire $or$build/ls180/gateware/ls180.v:3724$375_Y + attribute \src "build/ls180/gateware/ls180.v:3787.36-3787.104" + wire $or$build/ls180/gateware/ls180.v:3787$409_Y + attribute \src "build/ls180/gateware/ls180.v:3808.67-3808.221" + wire $or$build/ls180/gateware/ls180.v:3808$416_Y + attribute \src "build/ls180/gateware/ls180.v:3816.10-3816.62" + wire $or$build/ls180/gateware/ls180.v:3816$419_Y + attribute \src "build/ls180/gateware/ls180.v:3846.67-3846.221" + wire $or$build/ls180/gateware/ls180.v:3846$425_Y + attribute \src "build/ls180/gateware/ls180.v:3854.10-3854.61" + wire $or$build/ls180/gateware/ls180.v:3854$428_Y + attribute \src "build/ls180/gateware/ls180.v:3864.91-3864.180" + wire $or$build/ls180/gateware/ls180.v:3864$432_Y + attribute \src "build/ls180/gateware/ls180.v:3864.90-3864.255" + wire $or$build/ls180/gateware/ls180.v:3864$435_Y + attribute \src "build/ls180/gateware/ls180.v:3864.89-3864.330" + wire $or$build/ls180/gateware/ls180.v:3864$438_Y + attribute \src "build/ls180/gateware/ls180.v:3869.91-3869.180" + wire $or$build/ls180/gateware/ls180.v:3869$448_Y + attribute \src "build/ls180/gateware/ls180.v:3869.90-3869.255" + wire $or$build/ls180/gateware/ls180.v:3869$451_Y + attribute \src "build/ls180/gateware/ls180.v:3869.89-3869.330" + wire $or$build/ls180/gateware/ls180.v:3869$454_Y + attribute \src "build/ls180/gateware/ls180.v:3874.91-3874.180" + wire $or$build/ls180/gateware/ls180.v:3874$464_Y + attribute \src "build/ls180/gateware/ls180.v:3874.90-3874.255" + wire $or$build/ls180/gateware/ls180.v:3874$467_Y + attribute \src "build/ls180/gateware/ls180.v:3874.89-3874.330" + wire $or$build/ls180/gateware/ls180.v:3874$470_Y + attribute \src "build/ls180/gateware/ls180.v:3879.91-3879.180" + wire $or$build/ls180/gateware/ls180.v:3879$480_Y + attribute \src "build/ls180/gateware/ls180.v:3879.90-3879.255" + wire $or$build/ls180/gateware/ls180.v:3879$483_Y + attribute \src "build/ls180/gateware/ls180.v:3879.89-3879.330" + wire $or$build/ls180/gateware/ls180.v:3879$486_Y + attribute \src "build/ls180/gateware/ls180.v:3884.132-3884.221" + wire $or$build/ls180/gateware/ls180.v:3884$497_Y + attribute \src "build/ls180/gateware/ls180.v:3884.131-3884.296" + wire $or$build/ls180/gateware/ls180.v:3884$500_Y + attribute \src "build/ls180/gateware/ls180.v:3884.130-3884.371" + wire $or$build/ls180/gateware/ls180.v:3884$503_Y + attribute \src "build/ls180/gateware/ls180.v:3884.34-3884.411" + wire $or$build/ls180/gateware/ls180.v:3884$508_Y + attribute \src "build/ls180/gateware/ls180.v:3884.506-3884.595" + wire $or$build/ls180/gateware/ls180.v:3884$513_Y + attribute \src "build/ls180/gateware/ls180.v:3884.505-3884.670" + wire $or$build/ls180/gateware/ls180.v:3884$516_Y + attribute \src "build/ls180/gateware/ls180.v:3884.504-3884.745" + wire $or$build/ls180/gateware/ls180.v:3884$519_Y + attribute \src "build/ls180/gateware/ls180.v:3884.33-3884.785" + wire $or$build/ls180/gateware/ls180.v:3884$524_Y + attribute \src "build/ls180/gateware/ls180.v:3884.880-3884.969" + wire $or$build/ls180/gateware/ls180.v:3884$529_Y + attribute \src "build/ls180/gateware/ls180.v:3884.879-3884.1044" + wire $or$build/ls180/gateware/ls180.v:3884$532_Y + attribute \src "build/ls180/gateware/ls180.v:3884.878-3884.1119" + wire $or$build/ls180/gateware/ls180.v:3884$535_Y + attribute \src "build/ls180/gateware/ls180.v:3884.32-3884.1159" + wire $or$build/ls180/gateware/ls180.v:3884$540_Y + attribute \src "build/ls180/gateware/ls180.v:3884.1254-3884.1343" + wire $or$build/ls180/gateware/ls180.v:3884$545_Y + attribute \src "build/ls180/gateware/ls180.v:3884.1253-3884.1418" + wire $or$build/ls180/gateware/ls180.v:3884$548_Y + attribute \src "build/ls180/gateware/ls180.v:3884.1252-3884.1493" + wire $or$build/ls180/gateware/ls180.v:3884$551_Y + attribute \src "build/ls180/gateware/ls180.v:3884.31-3884.1533" + wire $or$build/ls180/gateware/ls180.v:3884$556_Y + attribute \src "build/ls180/gateware/ls180.v:3947.10-3947.52" + wire $or$build/ls180/gateware/ls180.v:3947$565_Y + attribute \src "build/ls180/gateware/ls180.v:3974.35-3974.74" + wire $or$build/ls180/gateware/ls180.v:3974$575_Y + attribute \src "build/ls180/gateware/ls180.v:3975.34-3975.73" + wire $or$build/ls180/gateware/ls180.v:3975$579_Y + attribute \src "build/ls180/gateware/ls180.v:3976.48-3976.130" + wire $or$build/ls180/gateware/ls180.v:3976$585_Y + attribute \src "build/ls180/gateware/ls180.v:3977.24-3977.87" + wire $or$build/ls180/gateware/ls180.v:3977$588_Y + attribute \src "build/ls180/gateware/ls180.v:3978.26-3978.95" + wire $or$build/ls180/gateware/ls180.v:3978$590_Y + attribute \src "build/ls180/gateware/ls180.v:4039.37-4039.114" + wire $or$build/ls180/gateware/ls180.v:4039$600_Y + attribute \src "build/ls180/gateware/ls180.v:4039.36-4039.155" + wire $or$build/ls180/gateware/ls180.v:4039$601_Y + attribute \src "build/ls180/gateware/ls180.v:4039.35-4039.197" + wire $or$build/ls180/gateware/ls180.v:4039$602_Y + attribute \src "build/ls180/gateware/ls180.v:4039.34-4039.239" + wire $or$build/ls180/gateware/ls180.v:4039$603_Y + attribute \src "build/ls180/gateware/ls180.v:4040.40-4040.123" + wire $or$build/ls180/gateware/ls180.v:4040$604_Y + attribute \src "build/ls180/gateware/ls180.v:4040.39-4040.167" + wire $or$build/ls180/gateware/ls180.v:4040$605_Y + attribute \src "build/ls180/gateware/ls180.v:4040.38-4040.212" + wire $or$build/ls180/gateware/ls180.v:4040$606_Y + attribute \src "build/ls180/gateware/ls180.v:4040.37-4040.257" + wire $or$build/ls180/gateware/ls180.v:4040$607_Y + attribute \src "build/ls180/gateware/ls180.v:4041.39-4041.120" + wire $or$build/ls180/gateware/ls180.v:4041$608_Y + attribute \src "build/ls180/gateware/ls180.v:4041.38-4041.163" + wire $or$build/ls180/gateware/ls180.v:4041$609_Y + attribute \src "build/ls180/gateware/ls180.v:4041.37-4041.207" + wire $or$build/ls180/gateware/ls180.v:4041$610_Y + attribute \src "build/ls180/gateware/ls180.v:4041.36-4041.251" + wire $or$build/ls180/gateware/ls180.v:4041$611_Y + attribute \src "build/ls180/gateware/ls180.v:4042.41-4042.126" + wire $or$build/ls180/gateware/ls180.v:4042$612_Y + attribute \src "build/ls180/gateware/ls180.v:4042.40-4042.171" + wire $or$build/ls180/gateware/ls180.v:4042$613_Y + attribute \src "build/ls180/gateware/ls180.v:4042.39-4042.217" + wire $or$build/ls180/gateware/ls180.v:4042$614_Y + attribute \src "build/ls180/gateware/ls180.v:4042.38-4042.263" + wire $or$build/ls180/gateware/ls180.v:4042$615_Y + attribute \src "build/ls180/gateware/ls180.v:4043.40-4043.123" + wire width 4 $or$build/ls180/gateware/ls180.v:4043$616_Y + attribute \src "build/ls180/gateware/ls180.v:4043.39-4043.167" + wire width 4 $or$build/ls180/gateware/ls180.v:4043$617_Y + attribute \src "build/ls180/gateware/ls180.v:4043.38-4043.212" + wire width 4 $or$build/ls180/gateware/ls180.v:4043$618_Y + attribute \src "build/ls180/gateware/ls180.v:4043.37-4043.257" + wire width 4 $or$build/ls180/gateware/ls180.v:4043$619_Y + attribute \src "build/ls180/gateware/ls180.v:4064.36-4064.83" + wire $or$build/ls180/gateware/ls180.v:4064$620_Y + attribute \src "build/ls180/gateware/ls180.v:4218.93-4218.148" + wire $or$build/ls180/gateware/ls180.v:4218$634_Y + attribute \src "build/ls180/gateware/ls180.v:4235.54-4235.146" + wire $or$build/ls180/gateware/ls180.v:4235$637_Y + attribute \src "build/ls180/gateware/ls180.v:4238.48-4238.130" + wire $or$build/ls180/gateware/ls180.v:4238$640_Y + attribute \src "build/ls180/gateware/ls180.v:4362.55-4362.149" + wire $or$build/ls180/gateware/ls180.v:4362$658_Y + attribute \src "build/ls180/gateware/ls180.v:4365.49-4365.133" + wire $or$build/ls180/gateware/ls180.v:4365$661_Y + attribute \src "build/ls180/gateware/ls180.v:4496.56-4496.152" + wire $or$build/ls180/gateware/ls180.v:4496$673_Y + attribute \src "build/ls180/gateware/ls180.v:4499.50-4499.136" + wire $or$build/ls180/gateware/ls180.v:4499$676_Y + attribute \src "build/ls180/gateware/ls180.v:5128.94-5128.179" + wire $or$build/ls180/gateware/ls180.v:5128$971_Y + attribute \src "build/ls180/gateware/ls180.v:5139.56-5139.152" + wire $or$build/ls180/gateware/ls180.v:5139$977_Y + attribute \src "build/ls180/gateware/ls180.v:5336.94-5336.179" + wire $or$build/ls180/gateware/ls180.v:5336$1002_Y + attribute \src "build/ls180/gateware/ls180.v:5507.33-5507.102" + wire $or$build/ls180/gateware/ls180.v:5507$1046_Y + attribute \src "build/ls180/gateware/ls180.v:5507.32-5507.144" + wire $or$build/ls180/gateware/ls180.v:5507$1047_Y + attribute \src "build/ls180/gateware/ls180.v:5507.31-5507.165" + wire $or$build/ls180/gateware/ls180.v:5507$1048_Y + attribute \src "build/ls180/gateware/ls180.v:5507.30-5507.201" + wire $or$build/ls180/gateware/ls180.v:5507$1049_Y + attribute \src "build/ls180/gateware/ls180.v:5513.28-5513.97" + wire $or$build/ls180/gateware/ls180.v:5513$1054_Y + attribute \src "build/ls180/gateware/ls180.v:5513.27-5513.139" + wire $or$build/ls180/gateware/ls180.v:5513$1055_Y + attribute \src "build/ls180/gateware/ls180.v:5513.26-5513.160" + wire $or$build/ls180/gateware/ls180.v:5513$1056_Y + attribute \src "build/ls180/gateware/ls180.v:5513.25-5513.196" + wire $or$build/ls180/gateware/ls180.v:5513$1057_Y + attribute \src "build/ls180/gateware/ls180.v:5514.30-5514.169" + wire width 32 $or$build/ls180/gateware/ls180.v:5514$1060_Y + attribute \src "build/ls180/gateware/ls180.v:5514.29-5514.246" + wire width 32 $or$build/ls180/gateware/ls180.v:5514$1062_Y + attribute \src "build/ls180/gateware/ls180.v:5514.28-5514.302" + wire width 32 $or$build/ls180/gateware/ls180.v:5514$1064_Y + attribute \src "build/ls180/gateware/ls180.v:5514.27-5514.373" + wire width 32 $or$build/ls180/gateware/ls180.v:5514$1066_Y + attribute \src "build/ls180/gateware/ls180.v:6160.53-6160.122" + wire width 8 $or$build/ls180/gateware/ls180.v:6160$2042_Y + attribute \src "build/ls180/gateware/ls180.v:6160.52-6160.159" + wire width 8 $or$build/ls180/gateware/ls180.v:6160$2043_Y + attribute \src "build/ls180/gateware/ls180.v:6160.51-6160.196" + wire width 8 $or$build/ls180/gateware/ls180.v:6160$2044_Y + attribute \src "build/ls180/gateware/ls180.v:6160.50-6160.233" + wire width 8 $or$build/ls180/gateware/ls180.v:6160$2045_Y + attribute \src "build/ls180/gateware/ls180.v:6160.49-6160.270" + wire width 8 $or$build/ls180/gateware/ls180.v:6160$2046_Y + attribute \src "build/ls180/gateware/ls180.v:6160.48-6160.307" + wire width 8 $or$build/ls180/gateware/ls180.v:6160$2047_Y + attribute \src "build/ls180/gateware/ls180.v:6160.47-6160.344" + wire width 8 $or$build/ls180/gateware/ls180.v:6160$2048_Y + attribute \src "build/ls180/gateware/ls180.v:6160.46-6160.381" + wire width 8 $or$build/ls180/gateware/ls180.v:6160$2049_Y + attribute \src "build/ls180/gateware/ls180.v:6160.45-6160.418" + wire width 8 $or$build/ls180/gateware/ls180.v:6160$2050_Y + attribute \src "build/ls180/gateware/ls180.v:6160.44-6160.456" + wire width 8 $or$build/ls180/gateware/ls180.v:6160$2051_Y + attribute \src "build/ls180/gateware/ls180.v:6160.43-6160.494" + wire width 8 $or$build/ls180/gateware/ls180.v:6160$2052_Y + attribute \src "build/ls180/gateware/ls180.v:6160.42-6160.532" + wire width 8 $or$build/ls180/gateware/ls180.v:6160$2053_Y + attribute \src "build/ls180/gateware/ls180.v:6487.90-6487.179" + wire $or$build/ls180/gateware/ls180.v:6487$2078_Y + attribute \src "build/ls180/gateware/ls180.v:6487.89-6487.254" + wire $or$build/ls180/gateware/ls180.v:6487$2081_Y + attribute \src "build/ls180/gateware/ls180.v:6487.88-6487.329" + wire $or$build/ls180/gateware/ls180.v:6487$2084_Y + attribute \src "build/ls180/gateware/ls180.v:6511.90-6511.179" + wire $or$build/ls180/gateware/ls180.v:6511$2094_Y + attribute \src "build/ls180/gateware/ls180.v:6511.89-6511.254" + wire $or$build/ls180/gateware/ls180.v:6511$2097_Y + attribute \src "build/ls180/gateware/ls180.v:6511.88-6511.329" + wire $or$build/ls180/gateware/ls180.v:6511$2100_Y + attribute \src "build/ls180/gateware/ls180.v:6535.90-6535.179" + wire $or$build/ls180/gateware/ls180.v:6535$2110_Y + attribute \src "build/ls180/gateware/ls180.v:6535.89-6535.254" + wire $or$build/ls180/gateware/ls180.v:6535$2113_Y + attribute \src "build/ls180/gateware/ls180.v:6535.88-6535.329" + wire $or$build/ls180/gateware/ls180.v:6535$2116_Y + attribute \src "build/ls180/gateware/ls180.v:6559.90-6559.179" + wire $or$build/ls180/gateware/ls180.v:6559$2126_Y + attribute \src "build/ls180/gateware/ls180.v:6559.89-6559.254" + wire $or$build/ls180/gateware/ls180.v:6559$2129_Y + attribute \src "build/ls180/gateware/ls180.v:6559.88-6559.329" + wire $or$build/ls180/gateware/ls180.v:6559$2132_Y + attribute \src "build/ls180/gateware/ls180.v:7056.7-7056.93" + wire $or$build/ls180/gateware/ls180.v:7056$2188_Y + attribute \src "build/ls180/gateware/ls180.v:7067.7-7067.93" + wire $or$build/ls180/gateware/ls180.v:7067$2189_Y + attribute \src "build/ls180/gateware/ls180.v:7328.7-7328.107" + wire $or$build/ls180/gateware/ls180.v:7328$2267_Y + attribute \src "build/ls180/gateware/ls180.v:7374.7-7374.107" + wire $or$build/ls180/gateware/ls180.v:7374$2283_Y + attribute \src "build/ls180/gateware/ls180.v:7420.7-7420.107" + wire $or$build/ls180/gateware/ls180.v:7420$2299_Y + attribute \src "build/ls180/gateware/ls180.v:7466.7-7466.107" + wire $or$build/ls180/gateware/ls180.v:7466$2315_Y + attribute \src "build/ls180/gateware/ls180.v:7654.40-7654.125" + wire $or$build/ls180/gateware/ls180.v:7654$2336_Y + attribute \src "build/ls180/gateware/ls180.v:7654.39-7654.207" + wire $or$build/ls180/gateware/ls180.v:7654$2339_Y + attribute \src "build/ls180/gateware/ls180.v:7654.38-7654.289" + wire $or$build/ls180/gateware/ls180.v:7654$2342_Y + attribute \src "build/ls180/gateware/ls180.v:7654.37-7654.371" + wire $or$build/ls180/gateware/ls180.v:7654$2345_Y + attribute \src "build/ls180/gateware/ls180.v:7655.41-7655.126" + wire $or$build/ls180/gateware/ls180.v:7655$2348_Y + attribute \src "build/ls180/gateware/ls180.v:7655.40-7655.208" + wire $or$build/ls180/gateware/ls180.v:7655$2351_Y + attribute \src "build/ls180/gateware/ls180.v:7655.39-7655.290" + wire $or$build/ls180/gateware/ls180.v:7655$2354_Y + attribute \src "build/ls180/gateware/ls180.v:7655.38-7655.372" + wire $or$build/ls180/gateware/ls180.v:7655$2357_Y + attribute \src "build/ls180/gateware/ls180.v:7659.7-7659.49" + wire $or$build/ls180/gateware/ls180.v:7659$2358_Y + attribute \src "build/ls180/gateware/ls180.v:7690.22-7690.52" + wire $or$build/ls180/gateware/ls180.v:7690$2364_Y + attribute \src "build/ls180/gateware/ls180.v:7730.33-7730.88" + wire $or$build/ls180/gateware/ls180.v:7730$2368_Y + attribute \src "build/ls180/gateware/ls180.v:7736.8-7736.99" + wire $or$build/ls180/gateware/ls180.v:7736$2370_Y + attribute \src "build/ls180/gateware/ls180.v:7753.53-7753.142" + wire $or$build/ls180/gateware/ls180.v:7753$2375_Y + attribute \src "build/ls180/gateware/ls180.v:7754.52-7754.139" + wire $or$build/ls180/gateware/ls180.v:7754$2376_Y + attribute \src "build/ls180/gateware/ls180.v:7788.7-7788.89" + wire $or$build/ls180/gateware/ls180.v:7788$2379_Y + attribute \src "build/ls180/gateware/ls180.v:7811.34-7811.91" + wire $or$build/ls180/gateware/ls180.v:7811$2380_Y + attribute \src "build/ls180/gateware/ls180.v:7817.8-7817.101" + wire $or$build/ls180/gateware/ls180.v:7817$2382_Y + attribute \src "build/ls180/gateware/ls180.v:7834.54-7834.145" + wire $or$build/ls180/gateware/ls180.v:7834$2387_Y + attribute \src "build/ls180/gateware/ls180.v:7835.53-7835.142" + wire $or$build/ls180/gateware/ls180.v:7835$2388_Y + attribute \src "build/ls180/gateware/ls180.v:7869.7-7869.91" + wire $or$build/ls180/gateware/ls180.v:7869$2391_Y + attribute \src "build/ls180/gateware/ls180.v:7890.35-7890.94" + wire $or$build/ls180/gateware/ls180.v:7890$2392_Y + attribute \src "build/ls180/gateware/ls180.v:7896.8-7896.103" + wire $or$build/ls180/gateware/ls180.v:7896$2394_Y + attribute \src "build/ls180/gateware/ls180.v:7913.55-7913.148" + wire $or$build/ls180/gateware/ls180.v:7913$2399_Y + attribute \src "build/ls180/gateware/ls180.v:7914.54-7914.145" + wire $or$build/ls180/gateware/ls180.v:7914$2400_Y + attribute \src "build/ls180/gateware/ls180.v:7930.7-7930.93" + wire $or$build/ls180/gateware/ls180.v:7930$2403_Y + attribute \src "build/ls180/gateware/ls180.v:8119.8-8119.103" + wire $or$build/ls180/gateware/ls180.v:8119$2427_Y + attribute \src "build/ls180/gateware/ls180.v:8136.55-8136.148" + wire $or$build/ls180/gateware/ls180.v:8136$2432_Y + attribute \src "build/ls180/gateware/ls180.v:8137.54-8137.145" + wire $or$build/ls180/gateware/ls180.v:8137$2433_Y + attribute \src "build/ls180/gateware/ls180.v:8210.21-8210.65" + wire $or$build/ls180/gateware/ls180.v:8210$2451_Y + attribute \src "build/ls180/gateware/ls180.v:9525.8-9525.49" + wire $or$build/ls180/gateware/ls180.v:9525$2529_Y + attribute \src "build/ls180/gateware/ls180.v:3058.46-3058.94" + wire width 13 $sshl$build/ls180/gateware/ls180.v:3058$112_Y + attribute \src "build/ls180/gateware/ls180.v:3215.46-3215.94" + wire width 13 $sshl$build/ls180/gateware/ls180.v:3215$142_Y + attribute \src "build/ls180/gateware/ls180.v:3372.46-3372.94" + wire width 13 $sshl$build/ls180/gateware/ls180.v:3372$172_Y + attribute \src "build/ls180/gateware/ls180.v:3529.46-3529.94" + wire width 13 $sshl$build/ls180/gateware/ls180.v:3529$202_Y + attribute \src "build/ls180/gateware/ls180.v:2797.48-2797.92" + wire width 4 $sub$build/ls180/gateware/ls180.v:2797$71_Y + attribute \src "build/ls180/gateware/ls180.v:2827.48-2827.92" + wire width 4 $sub$build/ls180/gateware/ls180.v:2827$82_Y + attribute \src "build/ls180/gateware/ls180.v:3089.63-3089.122" + wire width 3 $sub$build/ls180/gateware/ls180.v:3089$125_Y + attribute \src "build/ls180/gateware/ls180.v:3246.63-3246.122" + wire width 3 $sub$build/ls180/gateware/ls180.v:3246$155_Y + attribute \src "build/ls180/gateware/ls180.v:3403.63-3403.122" + wire width 3 $sub$build/ls180/gateware/ls180.v:3403$185_Y + attribute \src "build/ls180/gateware/ls180.v:3560.63-3560.122" + wire width 3 $sub$build/ls180/gateware/ls180.v:3560$215_Y + attribute \src "build/ls180/gateware/ls180.v:3966.38-3966.65" + wire width 30 $sub$build/ls180/gateware/ls180.v:3966$569_Y + attribute \src "build/ls180/gateware/ls180.v:3987.47-3987.77" + wire width 16 $sub$build/ls180/gateware/ls180.v:3987$592_Y + attribute \src "build/ls180/gateware/ls180.v:3988.47-3988.71" + wire width 16 $sub$build/ls180/gateware/ls180.v:3988$594_Y + attribute \src "build/ls180/gateware/ls180.v:4015.25-4015.44" + wire width 8 $sub$build/ls180/gateware/ls180.v:4015$598_Y + attribute \src "build/ls180/gateware/ls180.v:4265.61-4265.92" + wire width 32 $sub$build/ls180/gateware/ls180.v:4265$642_Y + attribute \src "build/ls180/gateware/ls180.v:4276.64-4276.107" + wire width 8 $sub$build/ls180/gateware/ls180.v:4276$644_Y + attribute \src "build/ls180/gateware/ls180.v:4293.61-4293.92" + wire width 32 $sub$build/ls180/gateware/ls180.v:4293$648_Y + attribute \src "build/ls180/gateware/ls180.v:4522.63-4522.95" + wire width 32 $sub$build/ls180/gateware/ls180.v:4522$678_Y + attribute \src "build/ls180/gateware/ls180.v:4527.63-4527.95" + wire width 32 $sub$build/ls180/gateware/ls180.v:4527$679_Y + attribute \src "build/ls180/gateware/ls180.v:4538.66-4538.125" + wire width 10 $sub$build/ls180/gateware/ls180.v:4538$682_Y + attribute \src "build/ls180/gateware/ls180.v:4559.63-4559.95" + wire width 32 $sub$build/ls180/gateware/ls180.v:4559$685_Y + attribute \src "build/ls180/gateware/ls180.v:5021.44-5021.89" + wire width 32 $sub$build/ls180/gateware/ls180.v:5021$958_Y + attribute \src "build/ls180/gateware/ls180.v:5036.70-5036.115" + wire width 32 $sub$build/ls180/gateware/ls180.v:5036$961_Y + attribute \src "build/ls180/gateware/ls180.v:5047.46-5047.91" + wire width 32 $sub$build/ls180/gateware/ls180.v:5047$966_Y + attribute \src "build/ls180/gateware/ls180.v:5122.47-5122.90" + wire width 5 $sub$build/ls180/gateware/ls180.v:5122$970_Y + attribute \src "build/ls180/gateware/ls180.v:5171.63-5171.118" + wire width 32 $sub$build/ls180/gateware/ls180.v:5171$984_Y + attribute \src "build/ls180/gateware/ls180.v:5261.85-5261.126" + wire width 32 $sub$build/ls180/gateware/ls180.v:5261$990_Y + attribute \src "build/ls180/gateware/ls180.v:5330.47-5330.90" + wire width 5 $sub$build/ls180/gateware/ls180.v:5330$1001_Y + attribute \src "build/ls180/gateware/ls180.v:5349.61-5349.98" + wire width 16 $sub$build/ls180/gateware/ls180.v:5349$1007_Y + attribute \src "build/ls180/gateware/ls180.v:5350.61-5350.92" + wire width 16 $sub$build/ls180/gateware/ls180.v:5350$1009_Y + attribute \src "build/ls180/gateware/ls180.v:5378.32-5378.58" + wire width 8 $sub$build/ls180/gateware/ls180.v:5378$1013_Y + attribute \src "build/ls180/gateware/ls180.v:7180.45-7180.88" + wire width 5 $sub$build/ls180/gateware/ls180.v:7180$2225_Y + attribute \src "build/ls180/gateware/ls180.v:7202.45-7202.88" + wire width 5 $sub$build/ls180/gateware/ls180.v:7202$2236_Y + attribute \src "build/ls180/gateware/ls180.v:7223.37-7223.72" + wire width 32 $sub$build/ls180/gateware/ls180.v:7223$2238_Y + attribute \src "build/ls180/gateware/ls180.v:7244.31-7244.61" + wire width 10 $sub$build/ls180/gateware/ls180.v:7244$2243_Y + attribute \src "build/ls180/gateware/ls180.v:7250.34-7250.67" + wire $sub$build/ls180/gateware/ls180.v:7250$2244_Y + attribute \src "build/ls180/gateware/ls180.v:7261.36-7261.69" + wire $sub$build/ls180/gateware/ls180.v:7261$2247_Y + attribute \src "build/ls180/gateware/ls180.v:7325.59-7325.116" + wire width 4 $sub$build/ls180/gateware/ls180.v:7325$2265_Y + attribute \src "build/ls180/gateware/ls180.v:7344.46-7344.90" + wire width 3 $sub$build/ls180/gateware/ls180.v:7344$2269_Y + attribute \src "build/ls180/gateware/ls180.v:7371.59-7371.116" + wire width 4 $sub$build/ls180/gateware/ls180.v:7371$2281_Y + attribute \src "build/ls180/gateware/ls180.v:7390.46-7390.90" + wire width 3 $sub$build/ls180/gateware/ls180.v:7390$2285_Y + attribute \src "build/ls180/gateware/ls180.v:7417.59-7417.116" + wire width 4 $sub$build/ls180/gateware/ls180.v:7417$2297_Y + attribute \src "build/ls180/gateware/ls180.v:7436.46-7436.90" + wire width 3 $sub$build/ls180/gateware/ls180.v:7436$2301_Y + attribute \src "build/ls180/gateware/ls180.v:7463.59-7463.116" + wire width 4 $sub$build/ls180/gateware/ls180.v:7463$2313_Y + attribute \src "build/ls180/gateware/ls180.v:7482.46-7482.90" + wire width 3 $sub$build/ls180/gateware/ls180.v:7482$2317_Y + attribute \src "build/ls180/gateware/ls180.v:7493.25-7493.48" + wire width 5 $sub$build/ls180/gateware/ls180.v:7493$2321_Y + attribute \src "build/ls180/gateware/ls180.v:7500.25-7500.48" + wire width 4 $sub$build/ls180/gateware/ls180.v:7500$2324_Y + attribute \src "build/ls180/gateware/ls180.v:7632.33-7632.64" + wire $sub$build/ls180/gateware/ls180.v:7632$2329_Y + attribute \src "build/ls180/gateware/ls180.v:7647.33-7647.64" + wire width 3 $sub$build/ls180/gateware/ls180.v:7647$2332_Y + attribute \src "build/ls180/gateware/ls180.v:7699.22-7699.42" + wire width 3 $sub$build/ls180/gateware/ls180.v:7699$2365_Y + attribute \src "build/ls180/gateware/ls180.v:8112.43-8112.84" + wire width 6 $sub$build/ls180/gateware/ls180.v:8112$2425_Y + attribute \src "build/ls180/gateware/ls180.v:8198.43-8198.84" + wire width 6 $sub$build/ls180/gateware/ls180.v:8198$2447_Y + attribute \src "build/ls180/gateware/ls180.v:8219.29-8219.56" + wire width 3 $sub$build/ls180/gateware/ls180.v:8219$2452_Y + attribute \src "build/ls180/gateware/ls180.v:8311.22-8311.42" + wire width 20 $sub$build/ls180/gateware/ls180.v:8311$2458_Y + attribute \src "build/ls180/gateware/ls180.v:9564.22-9564.92" + wire $ternary$build/ls180/gateware/ls180.v:9564$2530_Y + attribute \src "build/ls180/gateware/ls180.v:9567.22-9567.92" + wire $ternary$build/ls180/gateware/ls180.v:9567$2531_Y + attribute \src "build/ls180/gateware/ls180.v:9570.22-9570.92" + wire $ternary$build/ls180/gateware/ls180.v:9570$2532_Y + attribute \src "build/ls180/gateware/ls180.v:9573.22-9573.92" + wire $ternary$build/ls180/gateware/ls180.v:9573$2533_Y + attribute \src "build/ls180/gateware/ls180.v:9576.22-9576.92" + wire $ternary$build/ls180/gateware/ls180.v:9576$2534_Y + attribute \src "build/ls180/gateware/ls180.v:9579.22-9579.92" + wire $ternary$build/ls180/gateware/ls180.v:9579$2535_Y + attribute \src "build/ls180/gateware/ls180.v:9582.22-9582.92" + wire $ternary$build/ls180/gateware/ls180.v:9582$2536_Y + attribute \src "build/ls180/gateware/ls180.v:9585.22-9585.92" + wire $ternary$build/ls180/gateware/ls180.v:9585$2537_Y + attribute \src "build/ls180/gateware/ls180.v:9588.22-9588.92" + wire $ternary$build/ls180/gateware/ls180.v:9588$2538_Y + attribute \src "build/ls180/gateware/ls180.v:9591.22-9591.92" + wire $ternary$build/ls180/gateware/ls180.v:9591$2539_Y + attribute \src "build/ls180/gateware/ls180.v:9594.23-9594.95" + wire $ternary$build/ls180/gateware/ls180.v:9594$2540_Y + attribute \src "build/ls180/gateware/ls180.v:9597.23-9597.95" + wire $ternary$build/ls180/gateware/ls180.v:9597$2541_Y + attribute \src "build/ls180/gateware/ls180.v:9600.23-9600.95" + wire $ternary$build/ls180/gateware/ls180.v:9600$2542_Y + attribute \src "build/ls180/gateware/ls180.v:9603.23-9603.95" + wire $ternary$build/ls180/gateware/ls180.v:9603$2543_Y + attribute \src "build/ls180/gateware/ls180.v:9606.23-9606.95" + wire $ternary$build/ls180/gateware/ls180.v:9606$2544_Y + attribute \src "build/ls180/gateware/ls180.v:9609.23-9609.95" + wire $ternary$build/ls180/gateware/ls180.v:9609$2545_Y + attribute \src "build/ls180/gateware/ls180.v:9612.21-9612.93" + wire $ternary$build/ls180/gateware/ls180.v:9612$2546_Y + attribute \src "build/ls180/gateware/ls180.v:9615.25-9615.97" + wire $ternary$build/ls180/gateware/ls180.v:9615$2547_Y + attribute \src "build/ls180/gateware/ls180.v:9618.25-9618.97" + wire $ternary$build/ls180/gateware/ls180.v:9618$2548_Y + attribute \src "build/ls180/gateware/ls180.v:9621.25-9621.97" + wire $ternary$build/ls180/gateware/ls180.v:9621$2549_Y + attribute \src "build/ls180/gateware/ls180.v:9624.25-9624.97" + wire $ternary$build/ls180/gateware/ls180.v:9624$2550_Y + attribute \src "build/ls180/gateware/ls180.v:4619.416-4619.502" + wire $xor$build/ls180/gateware/ls180.v:4619$692_Y + attribute \src "build/ls180/gateware/ls180.v:4619.235-4619.321" + wire $xor$build/ls180/gateware/ls180.v:4619$693_Y + attribute \src "build/ls180/gateware/ls180.v:4619.188-4619.322" + wire $xor$build/ls180/gateware/ls180.v:4619$694_Y + attribute \src "build/ls180/gateware/ls180.v:4620.416-4620.502" + wire $xor$build/ls180/gateware/ls180.v:4620$695_Y + attribute \src "build/ls180/gateware/ls180.v:4620.235-4620.321" + wire $xor$build/ls180/gateware/ls180.v:4620$696_Y + attribute \src "build/ls180/gateware/ls180.v:4620.188-4620.322" + wire $xor$build/ls180/gateware/ls180.v:4620$697_Y + attribute \src "build/ls180/gateware/ls180.v:4621.416-4621.502" + wire $xor$build/ls180/gateware/ls180.v:4621$698_Y + attribute \src "build/ls180/gateware/ls180.v:4621.235-4621.321" + wire $xor$build/ls180/gateware/ls180.v:4621$699_Y + attribute \src "build/ls180/gateware/ls180.v:4621.188-4621.322" + wire $xor$build/ls180/gateware/ls180.v:4621$700_Y + attribute \src "build/ls180/gateware/ls180.v:4622.416-4622.502" + wire $xor$build/ls180/gateware/ls180.v:4622$701_Y + attribute \src "build/ls180/gateware/ls180.v:4622.235-4622.321" + wire $xor$build/ls180/gateware/ls180.v:4622$702_Y + attribute \src "build/ls180/gateware/ls180.v:4622.188-4622.322" + wire $xor$build/ls180/gateware/ls180.v:4622$703_Y + attribute \src "build/ls180/gateware/ls180.v:4623.416-4623.502" + wire $xor$build/ls180/gateware/ls180.v:4623$704_Y + attribute \src "build/ls180/gateware/ls180.v:4623.235-4623.321" + wire $xor$build/ls180/gateware/ls180.v:4623$705_Y + attribute \src "build/ls180/gateware/ls180.v:4623.188-4623.322" + wire $xor$build/ls180/gateware/ls180.v:4623$706_Y + attribute \src "build/ls180/gateware/ls180.v:4624.416-4624.502" + wire $xor$build/ls180/gateware/ls180.v:4624$707_Y + attribute \src "build/ls180/gateware/ls180.v:4624.235-4624.321" + wire $xor$build/ls180/gateware/ls180.v:4624$708_Y + attribute \src "build/ls180/gateware/ls180.v:4624.188-4624.322" + wire $xor$build/ls180/gateware/ls180.v:4624$709_Y + attribute \src "build/ls180/gateware/ls180.v:4625.416-4625.502" + wire $xor$build/ls180/gateware/ls180.v:4625$710_Y + attribute \src "build/ls180/gateware/ls180.v:4625.235-4625.321" + wire $xor$build/ls180/gateware/ls180.v:4625$711_Y + attribute \src "build/ls180/gateware/ls180.v:4625.188-4625.322" + wire $xor$build/ls180/gateware/ls180.v:4625$712_Y + attribute \src "build/ls180/gateware/ls180.v:4626.416-4626.502" + wire $xor$build/ls180/gateware/ls180.v:4626$713_Y + attribute \src "build/ls180/gateware/ls180.v:4626.235-4626.321" + wire $xor$build/ls180/gateware/ls180.v:4626$714_Y + attribute \src "build/ls180/gateware/ls180.v:4626.188-4626.322" + wire $xor$build/ls180/gateware/ls180.v:4626$715_Y + attribute \src "build/ls180/gateware/ls180.v:4627.416-4627.502" + wire $xor$build/ls180/gateware/ls180.v:4627$716_Y + attribute \src "build/ls180/gateware/ls180.v:4627.235-4627.321" + wire $xor$build/ls180/gateware/ls180.v:4627$717_Y + attribute \src "build/ls180/gateware/ls180.v:4627.188-4627.322" + wire $xor$build/ls180/gateware/ls180.v:4627$718_Y + attribute \src "build/ls180/gateware/ls180.v:4628.417-4628.503" + wire $xor$build/ls180/gateware/ls180.v:4628$719_Y + attribute \src "build/ls180/gateware/ls180.v:4628.236-4628.322" + wire $xor$build/ls180/gateware/ls180.v:4628$720_Y + attribute \src "build/ls180/gateware/ls180.v:4628.189-4628.323" + wire $xor$build/ls180/gateware/ls180.v:4628$721_Y + attribute \src "build/ls180/gateware/ls180.v:4629.424-4629.511" + wire $xor$build/ls180/gateware/ls180.v:4629$722_Y + attribute \src "build/ls180/gateware/ls180.v:4629.240-4629.327" + wire $xor$build/ls180/gateware/ls180.v:4629$723_Y + attribute \src "build/ls180/gateware/ls180.v:4629.192-4629.328" + wire $xor$build/ls180/gateware/ls180.v:4629$724_Y + attribute \src "build/ls180/gateware/ls180.v:4630.424-4630.511" + wire $xor$build/ls180/gateware/ls180.v:4630$725_Y + attribute \src "build/ls180/gateware/ls180.v:4630.240-4630.327" + wire $xor$build/ls180/gateware/ls180.v:4630$726_Y + attribute \src "build/ls180/gateware/ls180.v:4630.192-4630.328" + wire $xor$build/ls180/gateware/ls180.v:4630$727_Y + attribute \src "build/ls180/gateware/ls180.v:4631.424-4631.511" + wire $xor$build/ls180/gateware/ls180.v:4631$728_Y + attribute \src "build/ls180/gateware/ls180.v:4631.240-4631.327" + wire $xor$build/ls180/gateware/ls180.v:4631$729_Y + attribute \src "build/ls180/gateware/ls180.v:4631.192-4631.328" + wire $xor$build/ls180/gateware/ls180.v:4631$730_Y + attribute \src "build/ls180/gateware/ls180.v:4632.424-4632.511" + wire $xor$build/ls180/gateware/ls180.v:4632$731_Y + attribute \src "build/ls180/gateware/ls180.v:4632.240-4632.327" + wire $xor$build/ls180/gateware/ls180.v:4632$732_Y + attribute \src "build/ls180/gateware/ls180.v:4632.192-4632.328" + wire $xor$build/ls180/gateware/ls180.v:4632$733_Y + attribute \src "build/ls180/gateware/ls180.v:4633.424-4633.511" + wire $xor$build/ls180/gateware/ls180.v:4633$734_Y + attribute \src "build/ls180/gateware/ls180.v:4633.240-4633.327" + wire $xor$build/ls180/gateware/ls180.v:4633$735_Y + attribute \src "build/ls180/gateware/ls180.v:4633.192-4633.328" + wire $xor$build/ls180/gateware/ls180.v:4633$736_Y + attribute \src "build/ls180/gateware/ls180.v:4634.424-4634.511" + wire $xor$build/ls180/gateware/ls180.v:4634$737_Y + attribute \src "build/ls180/gateware/ls180.v:4634.240-4634.327" + wire $xor$build/ls180/gateware/ls180.v:4634$738_Y + attribute \src "build/ls180/gateware/ls180.v:4634.192-4634.328" + wire $xor$build/ls180/gateware/ls180.v:4634$739_Y + attribute \src "build/ls180/gateware/ls180.v:4635.424-4635.511" + wire $xor$build/ls180/gateware/ls180.v:4635$740_Y + attribute \src "build/ls180/gateware/ls180.v:4635.240-4635.327" + wire $xor$build/ls180/gateware/ls180.v:4635$741_Y + attribute \src "build/ls180/gateware/ls180.v:4635.192-4635.328" + wire $xor$build/ls180/gateware/ls180.v:4635$742_Y + attribute \src "build/ls180/gateware/ls180.v:4636.424-4636.511" + wire $xor$build/ls180/gateware/ls180.v:4636$743_Y + attribute \src "build/ls180/gateware/ls180.v:4636.240-4636.327" + wire $xor$build/ls180/gateware/ls180.v:4636$744_Y + attribute \src "build/ls180/gateware/ls180.v:4636.192-4636.328" + wire $xor$build/ls180/gateware/ls180.v:4636$745_Y + attribute \src "build/ls180/gateware/ls180.v:4637.424-4637.511" + wire $xor$build/ls180/gateware/ls180.v:4637$746_Y + attribute \src "build/ls180/gateware/ls180.v:4637.240-4637.327" + wire $xor$build/ls180/gateware/ls180.v:4637$747_Y + attribute \src "build/ls180/gateware/ls180.v:4637.192-4637.328" + wire $xor$build/ls180/gateware/ls180.v:4637$748_Y + attribute \src "build/ls180/gateware/ls180.v:4638.424-4638.511" + wire $xor$build/ls180/gateware/ls180.v:4638$749_Y + attribute \src "build/ls180/gateware/ls180.v:4638.240-4638.327" + wire $xor$build/ls180/gateware/ls180.v:4638$750_Y + attribute \src "build/ls180/gateware/ls180.v:4638.192-4638.328" + wire $xor$build/ls180/gateware/ls180.v:4638$751_Y + attribute \src "build/ls180/gateware/ls180.v:4639.424-4639.511" + wire $xor$build/ls180/gateware/ls180.v:4639$752_Y + attribute \src "build/ls180/gateware/ls180.v:4639.240-4639.327" + wire $xor$build/ls180/gateware/ls180.v:4639$753_Y + attribute \src "build/ls180/gateware/ls180.v:4639.192-4639.328" + wire $xor$build/ls180/gateware/ls180.v:4639$754_Y + attribute \src "build/ls180/gateware/ls180.v:4640.424-4640.511" + wire $xor$build/ls180/gateware/ls180.v:4640$755_Y + attribute \src "build/ls180/gateware/ls180.v:4640.240-4640.327" + wire $xor$build/ls180/gateware/ls180.v:4640$756_Y + attribute \src "build/ls180/gateware/ls180.v:4640.192-4640.328" + wire $xor$build/ls180/gateware/ls180.v:4640$757_Y + attribute \src "build/ls180/gateware/ls180.v:4641.424-4641.511" + wire $xor$build/ls180/gateware/ls180.v:4641$758_Y + attribute \src "build/ls180/gateware/ls180.v:4641.240-4641.327" + wire $xor$build/ls180/gateware/ls180.v:4641$759_Y + attribute \src "build/ls180/gateware/ls180.v:4641.192-4641.328" + wire $xor$build/ls180/gateware/ls180.v:4641$760_Y + attribute \src "build/ls180/gateware/ls180.v:4642.424-4642.511" + wire $xor$build/ls180/gateware/ls180.v:4642$761_Y + attribute \src "build/ls180/gateware/ls180.v:4642.240-4642.327" + wire $xor$build/ls180/gateware/ls180.v:4642$762_Y + attribute \src "build/ls180/gateware/ls180.v:4642.192-4642.328" + wire $xor$build/ls180/gateware/ls180.v:4642$763_Y + attribute \src "build/ls180/gateware/ls180.v:4643.424-4643.511" + wire $xor$build/ls180/gateware/ls180.v:4643$764_Y + attribute \src "build/ls180/gateware/ls180.v:4643.240-4643.327" + wire $xor$build/ls180/gateware/ls180.v:4643$765_Y + attribute \src "build/ls180/gateware/ls180.v:4643.192-4643.328" + wire $xor$build/ls180/gateware/ls180.v:4643$766_Y + attribute \src "build/ls180/gateware/ls180.v:4644.424-4644.511" + wire $xor$build/ls180/gateware/ls180.v:4644$767_Y + attribute \src "build/ls180/gateware/ls180.v:4644.240-4644.327" + wire $xor$build/ls180/gateware/ls180.v:4644$768_Y + attribute \src "build/ls180/gateware/ls180.v:4644.192-4644.328" + wire $xor$build/ls180/gateware/ls180.v:4644$769_Y + attribute \src "build/ls180/gateware/ls180.v:4645.424-4645.511" + wire $xor$build/ls180/gateware/ls180.v:4645$770_Y + attribute \src "build/ls180/gateware/ls180.v:4645.240-4645.327" + wire $xor$build/ls180/gateware/ls180.v:4645$771_Y + attribute \src "build/ls180/gateware/ls180.v:4645.192-4645.328" + wire $xor$build/ls180/gateware/ls180.v:4645$772_Y + attribute \src "build/ls180/gateware/ls180.v:4646.424-4646.511" + wire $xor$build/ls180/gateware/ls180.v:4646$773_Y + attribute \src "build/ls180/gateware/ls180.v:4646.240-4646.327" + wire $xor$build/ls180/gateware/ls180.v:4646$774_Y + attribute \src "build/ls180/gateware/ls180.v:4646.192-4646.328" + wire $xor$build/ls180/gateware/ls180.v:4646$775_Y + attribute \src "build/ls180/gateware/ls180.v:4647.424-4647.511" + wire $xor$build/ls180/gateware/ls180.v:4647$776_Y + attribute \src "build/ls180/gateware/ls180.v:4647.240-4647.327" + wire $xor$build/ls180/gateware/ls180.v:4647$777_Y + attribute \src "build/ls180/gateware/ls180.v:4647.192-4647.328" + wire $xor$build/ls180/gateware/ls180.v:4647$778_Y + attribute \src "build/ls180/gateware/ls180.v:4648.424-4648.511" + wire $xor$build/ls180/gateware/ls180.v:4648$779_Y + attribute \src "build/ls180/gateware/ls180.v:4648.240-4648.327" + wire $xor$build/ls180/gateware/ls180.v:4648$780_Y + attribute \src "build/ls180/gateware/ls180.v:4648.192-4648.328" + wire $xor$build/ls180/gateware/ls180.v:4648$781_Y + attribute \src "build/ls180/gateware/ls180.v:4649.423-4649.509" + wire $xor$build/ls180/gateware/ls180.v:4649$782_Y + attribute \src "build/ls180/gateware/ls180.v:4649.240-4649.326" + wire $xor$build/ls180/gateware/ls180.v:4649$783_Y + attribute \src "build/ls180/gateware/ls180.v:4649.192-4649.327" + wire $xor$build/ls180/gateware/ls180.v:4649$784_Y + attribute \src "build/ls180/gateware/ls180.v:4650.423-4650.509" + wire $xor$build/ls180/gateware/ls180.v:4650$785_Y + attribute \src "build/ls180/gateware/ls180.v:4650.240-4650.326" + wire $xor$build/ls180/gateware/ls180.v:4650$786_Y + attribute \src "build/ls180/gateware/ls180.v:4650.192-4650.327" + wire $xor$build/ls180/gateware/ls180.v:4650$787_Y + attribute \src "build/ls180/gateware/ls180.v:4651.423-4651.509" + wire $xor$build/ls180/gateware/ls180.v:4651$788_Y + attribute \src "build/ls180/gateware/ls180.v:4651.240-4651.326" + wire $xor$build/ls180/gateware/ls180.v:4651$789_Y + attribute \src "build/ls180/gateware/ls180.v:4651.192-4651.327" + wire $xor$build/ls180/gateware/ls180.v:4651$790_Y + attribute \src "build/ls180/gateware/ls180.v:4652.423-4652.509" + wire $xor$build/ls180/gateware/ls180.v:4652$791_Y + attribute \src "build/ls180/gateware/ls180.v:4652.240-4652.326" + wire $xor$build/ls180/gateware/ls180.v:4652$792_Y + attribute \src "build/ls180/gateware/ls180.v:4652.192-4652.327" + wire $xor$build/ls180/gateware/ls180.v:4652$793_Y + attribute \src "build/ls180/gateware/ls180.v:4653.423-4653.509" + wire $xor$build/ls180/gateware/ls180.v:4653$794_Y + attribute \src "build/ls180/gateware/ls180.v:4653.240-4653.326" + wire $xor$build/ls180/gateware/ls180.v:4653$795_Y + attribute \src "build/ls180/gateware/ls180.v:4653.192-4653.327" + wire $xor$build/ls180/gateware/ls180.v:4653$796_Y + attribute \src "build/ls180/gateware/ls180.v:4654.423-4654.509" + wire $xor$build/ls180/gateware/ls180.v:4654$797_Y + attribute \src "build/ls180/gateware/ls180.v:4654.240-4654.326" + wire $xor$build/ls180/gateware/ls180.v:4654$798_Y + attribute \src "build/ls180/gateware/ls180.v:4654.192-4654.327" + wire $xor$build/ls180/gateware/ls180.v:4654$799_Y + attribute \src "build/ls180/gateware/ls180.v:4655.423-4655.509" + wire $xor$build/ls180/gateware/ls180.v:4655$800_Y + attribute \src "build/ls180/gateware/ls180.v:4655.240-4655.326" + wire $xor$build/ls180/gateware/ls180.v:4655$801_Y + attribute \src "build/ls180/gateware/ls180.v:4655.192-4655.327" + wire $xor$build/ls180/gateware/ls180.v:4655$802_Y + attribute \src "build/ls180/gateware/ls180.v:4656.423-4656.509" + wire $xor$build/ls180/gateware/ls180.v:4656$803_Y + attribute \src "build/ls180/gateware/ls180.v:4656.240-4656.326" + wire $xor$build/ls180/gateware/ls180.v:4656$804_Y + attribute \src "build/ls180/gateware/ls180.v:4656.192-4656.327" + wire $xor$build/ls180/gateware/ls180.v:4656$805_Y + attribute \src "build/ls180/gateware/ls180.v:4657.423-4657.509" + wire $xor$build/ls180/gateware/ls180.v:4657$806_Y + attribute \src "build/ls180/gateware/ls180.v:4657.240-4657.326" + wire $xor$build/ls180/gateware/ls180.v:4657$807_Y + attribute \src "build/ls180/gateware/ls180.v:4657.192-4657.327" + wire $xor$build/ls180/gateware/ls180.v:4657$808_Y + attribute \src "build/ls180/gateware/ls180.v:4658.423-4658.509" + wire $xor$build/ls180/gateware/ls180.v:4658$809_Y + attribute \src "build/ls180/gateware/ls180.v:4658.240-4658.326" + wire $xor$build/ls180/gateware/ls180.v:4658$810_Y + attribute \src "build/ls180/gateware/ls180.v:4658.192-4658.327" + wire $xor$build/ls180/gateware/ls180.v:4658$811_Y + attribute \src "build/ls180/gateware/ls180.v:4679.1039-4679.1137" + wire $xor$build/ls180/gateware/ls180.v:4679$825_Y + attribute \src "build/ls180/gateware/ls180.v:4679.732-4679.830" + wire $xor$build/ls180/gateware/ls180.v:4679$826_Y + attribute \src "build/ls180/gateware/ls180.v:4679.679-4679.831" + wire $xor$build/ls180/gateware/ls180.v:4679$827_Y + attribute \src "build/ls180/gateware/ls180.v:4679.269-4679.367" + wire $xor$build/ls180/gateware/ls180.v:4679$828_Y + attribute \src "build/ls180/gateware/ls180.v:4679.215-4679.368" + wire $xor$build/ls180/gateware/ls180.v:4679$829_Y + attribute \src "build/ls180/gateware/ls180.v:4680.1039-4680.1137" + wire $xor$build/ls180/gateware/ls180.v:4680$830_Y + attribute \src "build/ls180/gateware/ls180.v:4680.732-4680.830" + wire $xor$build/ls180/gateware/ls180.v:4680$831_Y + attribute \src "build/ls180/gateware/ls180.v:4680.679-4680.831" + wire $xor$build/ls180/gateware/ls180.v:4680$832_Y + attribute \src "build/ls180/gateware/ls180.v:4680.269-4680.367" + wire $xor$build/ls180/gateware/ls180.v:4680$833_Y + attribute \src "build/ls180/gateware/ls180.v:4680.215-4680.368" + wire $xor$build/ls180/gateware/ls180.v:4680$834_Y + attribute \src "build/ls180/gateware/ls180.v:4689.1039-4689.1137" + wire $xor$build/ls180/gateware/ls180.v:4689$836_Y + attribute \src "build/ls180/gateware/ls180.v:4689.732-4689.830" + wire $xor$build/ls180/gateware/ls180.v:4689$837_Y + attribute \src "build/ls180/gateware/ls180.v:4689.679-4689.831" + wire $xor$build/ls180/gateware/ls180.v:4689$838_Y + attribute \src "build/ls180/gateware/ls180.v:4689.269-4689.367" + wire $xor$build/ls180/gateware/ls180.v:4689$839_Y + attribute \src "build/ls180/gateware/ls180.v:4689.215-4689.368" + wire $xor$build/ls180/gateware/ls180.v:4689$840_Y + attribute \src "build/ls180/gateware/ls180.v:4690.1039-4690.1137" + wire $xor$build/ls180/gateware/ls180.v:4690$841_Y + attribute \src "build/ls180/gateware/ls180.v:4690.732-4690.830" + wire $xor$build/ls180/gateware/ls180.v:4690$842_Y + attribute \src "build/ls180/gateware/ls180.v:4690.679-4690.831" + wire $xor$build/ls180/gateware/ls180.v:4690$843_Y + attribute \src "build/ls180/gateware/ls180.v:4690.269-4690.367" + wire $xor$build/ls180/gateware/ls180.v:4690$844_Y + attribute \src "build/ls180/gateware/ls180.v:4690.215-4690.368" + wire $xor$build/ls180/gateware/ls180.v:4690$845_Y + attribute \src "build/ls180/gateware/ls180.v:4699.1039-4699.1137" + wire $xor$build/ls180/gateware/ls180.v:4699$847_Y + attribute \src "build/ls180/gateware/ls180.v:4699.732-4699.830" + wire $xor$build/ls180/gateware/ls180.v:4699$848_Y + attribute \src "build/ls180/gateware/ls180.v:4699.679-4699.831" + wire $xor$build/ls180/gateware/ls180.v:4699$849_Y + attribute \src "build/ls180/gateware/ls180.v:4699.269-4699.367" + wire $xor$build/ls180/gateware/ls180.v:4699$850_Y + attribute \src "build/ls180/gateware/ls180.v:4699.215-4699.368" + wire $xor$build/ls180/gateware/ls180.v:4699$851_Y + attribute \src "build/ls180/gateware/ls180.v:4700.1039-4700.1137" + wire $xor$build/ls180/gateware/ls180.v:4700$852_Y + attribute \src "build/ls180/gateware/ls180.v:4700.732-4700.830" + wire $xor$build/ls180/gateware/ls180.v:4700$853_Y + attribute \src "build/ls180/gateware/ls180.v:4700.679-4700.831" + wire $xor$build/ls180/gateware/ls180.v:4700$854_Y + attribute \src "build/ls180/gateware/ls180.v:4700.269-4700.367" + wire $xor$build/ls180/gateware/ls180.v:4700$855_Y + attribute \src "build/ls180/gateware/ls180.v:4700.215-4700.368" + wire $xor$build/ls180/gateware/ls180.v:4700$856_Y + attribute \src "build/ls180/gateware/ls180.v:4709.1039-4709.1137" + wire $xor$build/ls180/gateware/ls180.v:4709$858_Y + attribute \src "build/ls180/gateware/ls180.v:4709.732-4709.830" + wire $xor$build/ls180/gateware/ls180.v:4709$859_Y + attribute \src "build/ls180/gateware/ls180.v:4709.679-4709.831" + wire $xor$build/ls180/gateware/ls180.v:4709$860_Y + attribute \src "build/ls180/gateware/ls180.v:4709.269-4709.367" + wire $xor$build/ls180/gateware/ls180.v:4709$861_Y + attribute \src "build/ls180/gateware/ls180.v:4709.215-4709.368" + wire $xor$build/ls180/gateware/ls180.v:4709$862_Y + attribute \src "build/ls180/gateware/ls180.v:4710.1039-4710.1137" + wire $xor$build/ls180/gateware/ls180.v:4710$863_Y + attribute \src "build/ls180/gateware/ls180.v:4710.732-4710.830" + wire $xor$build/ls180/gateware/ls180.v:4710$864_Y + attribute \src "build/ls180/gateware/ls180.v:4710.679-4710.831" + wire $xor$build/ls180/gateware/ls180.v:4710$865_Y + attribute \src "build/ls180/gateware/ls180.v:4710.269-4710.367" + wire $xor$build/ls180/gateware/ls180.v:4710$866_Y + attribute \src "build/ls180/gateware/ls180.v:4710.215-4710.368" + wire $xor$build/ls180/gateware/ls180.v:4710$867_Y + attribute \src "build/ls180/gateware/ls180.v:4861.1019-4861.1115" + wire $xor$build/ls180/gateware/ls180.v:4861$900_Y + attribute \src "build/ls180/gateware/ls180.v:4861.718-4861.814" + wire $xor$build/ls180/gateware/ls180.v:4861$901_Y + attribute \src "build/ls180/gateware/ls180.v:4861.666-4861.815" + wire $xor$build/ls180/gateware/ls180.v:4861$902_Y + attribute \src "build/ls180/gateware/ls180.v:4861.264-4861.360" + wire $xor$build/ls180/gateware/ls180.v:4861$903_Y + attribute \src "build/ls180/gateware/ls180.v:4861.211-4861.361" + wire $xor$build/ls180/gateware/ls180.v:4861$904_Y + attribute \src "build/ls180/gateware/ls180.v:4862.1019-4862.1115" + wire $xor$build/ls180/gateware/ls180.v:4862$905_Y + attribute \src "build/ls180/gateware/ls180.v:4862.718-4862.814" + wire $xor$build/ls180/gateware/ls180.v:4862$906_Y + attribute \src "build/ls180/gateware/ls180.v:4862.666-4862.815" + wire $xor$build/ls180/gateware/ls180.v:4862$907_Y + attribute \src "build/ls180/gateware/ls180.v:4862.264-4862.360" + wire $xor$build/ls180/gateware/ls180.v:4862$908_Y + attribute \src "build/ls180/gateware/ls180.v:4862.211-4862.361" + wire $xor$build/ls180/gateware/ls180.v:4862$909_Y + attribute \src "build/ls180/gateware/ls180.v:4871.1019-4871.1115" + wire $xor$build/ls180/gateware/ls180.v:4871$911_Y + attribute \src "build/ls180/gateware/ls180.v:4871.718-4871.814" + wire $xor$build/ls180/gateware/ls180.v:4871$912_Y + attribute \src "build/ls180/gateware/ls180.v:4871.666-4871.815" + wire $xor$build/ls180/gateware/ls180.v:4871$913_Y + attribute \src "build/ls180/gateware/ls180.v:4871.264-4871.360" + wire $xor$build/ls180/gateware/ls180.v:4871$914_Y + attribute \src "build/ls180/gateware/ls180.v:4871.211-4871.361" + wire $xor$build/ls180/gateware/ls180.v:4871$915_Y + attribute \src "build/ls180/gateware/ls180.v:4872.1019-4872.1115" + wire $xor$build/ls180/gateware/ls180.v:4872$916_Y + attribute \src "build/ls180/gateware/ls180.v:4872.718-4872.814" + wire $xor$build/ls180/gateware/ls180.v:4872$917_Y + attribute \src "build/ls180/gateware/ls180.v:4872.666-4872.815" + wire $xor$build/ls180/gateware/ls180.v:4872$918_Y + attribute \src "build/ls180/gateware/ls180.v:4872.264-4872.360" + wire $xor$build/ls180/gateware/ls180.v:4872$919_Y + attribute \src "build/ls180/gateware/ls180.v:4872.211-4872.361" + wire $xor$build/ls180/gateware/ls180.v:4872$920_Y + attribute \src "build/ls180/gateware/ls180.v:4881.1019-4881.1115" + wire $xor$build/ls180/gateware/ls180.v:4881$922_Y + attribute \src "build/ls180/gateware/ls180.v:4881.718-4881.814" + wire $xor$build/ls180/gateware/ls180.v:4881$923_Y + attribute \src "build/ls180/gateware/ls180.v:4881.666-4881.815" + wire $xor$build/ls180/gateware/ls180.v:4881$924_Y + attribute \src "build/ls180/gateware/ls180.v:4881.264-4881.360" + wire $xor$build/ls180/gateware/ls180.v:4881$925_Y + attribute \src "build/ls180/gateware/ls180.v:4881.211-4881.361" + wire $xor$build/ls180/gateware/ls180.v:4881$926_Y + attribute \src "build/ls180/gateware/ls180.v:4882.1019-4882.1115" + wire $xor$build/ls180/gateware/ls180.v:4882$927_Y + attribute \src "build/ls180/gateware/ls180.v:4882.718-4882.814" + wire $xor$build/ls180/gateware/ls180.v:4882$928_Y + attribute \src "build/ls180/gateware/ls180.v:4882.666-4882.815" + wire $xor$build/ls180/gateware/ls180.v:4882$929_Y + attribute \src "build/ls180/gateware/ls180.v:4882.264-4882.360" + wire $xor$build/ls180/gateware/ls180.v:4882$930_Y + attribute \src "build/ls180/gateware/ls180.v:4882.211-4882.361" + wire $xor$build/ls180/gateware/ls180.v:4882$931_Y + attribute \src "build/ls180/gateware/ls180.v:4891.1019-4891.1115" + wire $xor$build/ls180/gateware/ls180.v:4891$933_Y + attribute \src "build/ls180/gateware/ls180.v:4891.718-4891.814" + wire $xor$build/ls180/gateware/ls180.v:4891$934_Y + attribute \src "build/ls180/gateware/ls180.v:4891.666-4891.815" + wire $xor$build/ls180/gateware/ls180.v:4891$935_Y + attribute \src "build/ls180/gateware/ls180.v:4891.264-4891.360" + wire $xor$build/ls180/gateware/ls180.v:4891$936_Y + attribute \src "build/ls180/gateware/ls180.v:4891.211-4891.361" + wire $xor$build/ls180/gateware/ls180.v:4891$937_Y + attribute \src "build/ls180/gateware/ls180.v:4892.1019-4892.1115" + wire $xor$build/ls180/gateware/ls180.v:4892$938_Y + attribute \src "build/ls180/gateware/ls180.v:4892.718-4892.814" + wire $xor$build/ls180/gateware/ls180.v:4892$939_Y + attribute \src "build/ls180/gateware/ls180.v:4892.666-4892.815" + wire $xor$build/ls180/gateware/ls180.v:4892$940_Y + attribute \src "build/ls180/gateware/ls180.v:4892.264-4892.360" + wire $xor$build/ls180/gateware/ls180.v:4892$941_Y + attribute \src "build/ls180/gateware/ls180.v:4892.211-4892.361" + wire $xor$build/ls180/gateware/ls180.v:4892$942_Y + attribute \src "build/ls180/gateware/ls180.v:1629.11-1629.42" + wire width 3 \builder_bankmachine0_next_state + attribute \src "build/ls180/gateware/ls180.v:1628.11-1628.37" + wire width 3 \builder_bankmachine0_state + attribute \src "build/ls180/gateware/ls180.v:1631.11-1631.42" + wire width 3 \builder_bankmachine1_next_state + attribute \src "build/ls180/gateware/ls180.v:1630.11-1630.37" + wire width 3 \builder_bankmachine1_state + attribute \src "build/ls180/gateware/ls180.v:1633.11-1633.42" + wire width 3 \builder_bankmachine2_next_state + attribute \src "build/ls180/gateware/ls180.v:1632.11-1632.37" + wire width 3 \builder_bankmachine2_state + attribute \src "build/ls180/gateware/ls180.v:1635.11-1635.42" + wire width 3 \builder_bankmachine3_next_state + attribute \src "build/ls180/gateware/ls180.v:1634.11-1634.37" + wire width 3 \builder_bankmachine3_state + attribute \src "build/ls180/gateware/ls180.v:2374.5-2374.34" + wire \builder_comb_rhs_array_muxed0 + attribute \src "build/ls180/gateware/ls180.v:2375.12-2375.41" + wire width 13 \builder_comb_rhs_array_muxed1 + attribute \src "build/ls180/gateware/ls180.v:2387.5-2387.35" + wire \builder_comb_rhs_array_muxed10 + attribute \src "build/ls180/gateware/ls180.v:2388.5-2388.35" + wire \builder_comb_rhs_array_muxed11 + attribute \src "build/ls180/gateware/ls180.v:2392.12-2392.42" + wire width 22 \builder_comb_rhs_array_muxed12 + attribute \src "build/ls180/gateware/ls180.v:2393.5-2393.35" + wire \builder_comb_rhs_array_muxed13 + attribute \src "build/ls180/gateware/ls180.v:2394.5-2394.35" + wire \builder_comb_rhs_array_muxed14 + attribute \src "build/ls180/gateware/ls180.v:2395.12-2395.42" + wire width 22 \builder_comb_rhs_array_muxed15 + attribute \src "build/ls180/gateware/ls180.v:2396.5-2396.35" + wire \builder_comb_rhs_array_muxed16 + attribute \src "build/ls180/gateware/ls180.v:2397.5-2397.35" + wire \builder_comb_rhs_array_muxed17 + attribute \src "build/ls180/gateware/ls180.v:2398.12-2398.42" + wire width 22 \builder_comb_rhs_array_muxed18 + attribute \src "build/ls180/gateware/ls180.v:2399.5-2399.35" + wire \builder_comb_rhs_array_muxed19 + attribute \src "build/ls180/gateware/ls180.v:2376.11-2376.40" + wire width 2 \builder_comb_rhs_array_muxed2 + attribute \src "build/ls180/gateware/ls180.v:2400.5-2400.35" + wire \builder_comb_rhs_array_muxed20 + attribute \src "build/ls180/gateware/ls180.v:2401.12-2401.42" + wire width 22 \builder_comb_rhs_array_muxed21 + attribute \src "build/ls180/gateware/ls180.v:2402.5-2402.35" + wire \builder_comb_rhs_array_muxed22 + attribute \src "build/ls180/gateware/ls180.v:2403.5-2403.35" + wire \builder_comb_rhs_array_muxed23 + attribute \src "build/ls180/gateware/ls180.v:2404.12-2404.42" + wire width 32 \builder_comb_rhs_array_muxed24 + attribute \src "build/ls180/gateware/ls180.v:2405.12-2405.42" + wire width 32 \builder_comb_rhs_array_muxed25 + attribute \src "build/ls180/gateware/ls180.v:2406.11-2406.41" + wire width 4 \builder_comb_rhs_array_muxed26 + attribute \src "build/ls180/gateware/ls180.v:2407.5-2407.35" + wire \builder_comb_rhs_array_muxed27 + attribute \src "build/ls180/gateware/ls180.v:2408.5-2408.35" + wire \builder_comb_rhs_array_muxed28 + attribute \src "build/ls180/gateware/ls180.v:2409.5-2409.35" + wire \builder_comb_rhs_array_muxed29 + attribute \src "build/ls180/gateware/ls180.v:2377.5-2377.34" + wire \builder_comb_rhs_array_muxed3 + attribute \src "build/ls180/gateware/ls180.v:2410.11-2410.41" + wire width 3 \builder_comb_rhs_array_muxed30 + attribute \src "build/ls180/gateware/ls180.v:2411.11-2411.41" + wire width 2 \builder_comb_rhs_array_muxed31 + attribute \src "build/ls180/gateware/ls180.v:2378.5-2378.34" + wire \builder_comb_rhs_array_muxed4 + attribute \src "build/ls180/gateware/ls180.v:2379.5-2379.34" + wire \builder_comb_rhs_array_muxed5 + attribute \src "build/ls180/gateware/ls180.v:2383.5-2383.34" + wire \builder_comb_rhs_array_muxed6 + attribute \src "build/ls180/gateware/ls180.v:2384.12-2384.41" + wire width 13 \builder_comb_rhs_array_muxed7 + attribute \src "build/ls180/gateware/ls180.v:2385.11-2385.40" + wire width 2 \builder_comb_rhs_array_muxed8 + attribute \src "build/ls180/gateware/ls180.v:2386.5-2386.34" + wire \builder_comb_rhs_array_muxed9 + attribute \src "build/ls180/gateware/ls180.v:2380.5-2380.32" + wire \builder_comb_t_array_muxed0 + attribute \src "build/ls180/gateware/ls180.v:2381.5-2381.32" + wire \builder_comb_t_array_muxed1 + attribute \src "build/ls180/gateware/ls180.v:2382.5-2382.32" + wire \builder_comb_t_array_muxed2 + attribute \src "build/ls180/gateware/ls180.v:2389.5-2389.32" + wire \builder_comb_t_array_muxed3 + attribute \src "build/ls180/gateware/ls180.v:2390.5-2390.32" + wire \builder_comb_t_array_muxed4 + attribute \src "build/ls180/gateware/ls180.v:2391.5-2391.32" + wire \builder_comb_t_array_muxed5 + attribute \src "build/ls180/gateware/ls180.v:1619.5-1619.34" + wire \builder_converter0_next_state + attribute \src "build/ls180/gateware/ls180.v:1618.5-1618.29" + wire \builder_converter0_state + attribute \src "build/ls180/gateware/ls180.v:1623.5-1623.34" + wire \builder_converter1_next_state + attribute \src "build/ls180/gateware/ls180.v:1622.5-1622.29" + wire \builder_converter1_state + attribute \src "build/ls180/gateware/ls180.v:1660.5-1660.33" + wire \builder_converter_next_state + attribute \src "build/ls180/gateware/ls180.v:1659.5-1659.28" + wire \builder_converter_state + attribute \src "build/ls180/gateware/ls180.v:1780.12-1780.25" + wire width 20 \builder_count + attribute \src "build/ls180/gateware/ls180.v:2362.13-2362.41" + wire width 14 \builder_csr_interconnect_adr + attribute \src "build/ls180/gateware/ls180.v:2365.12-2365.42" + wire width 8 \builder_csr_interconnect_dat_r + attribute \src "build/ls180/gateware/ls180.v:2364.12-2364.42" + wire width 8 \builder_csr_interconnect_dat_w + attribute \src "build/ls180/gateware/ls180.v:2363.6-2363.33" + wire \builder_csr_interconnect_we + attribute \src "build/ls180/gateware/ls180.v:1818.12-1818.42" + wire width 8 \builder_csrbank0_bus_errors0_r + attribute \src "build/ls180/gateware/ls180.v:1817.6-1817.37" + wire \builder_csrbank0_bus_errors0_re + attribute \src "build/ls180/gateware/ls180.v:1820.12-1820.42" + wire width 8 \builder_csrbank0_bus_errors0_w + attribute \src "build/ls180/gateware/ls180.v:1819.6-1819.37" + wire \builder_csrbank0_bus_errors0_we + attribute \src "build/ls180/gateware/ls180.v:1814.12-1814.42" + wire width 8 \builder_csrbank0_bus_errors1_r + attribute \src "build/ls180/gateware/ls180.v:1813.6-1813.37" + wire \builder_csrbank0_bus_errors1_re + attribute \src "build/ls180/gateware/ls180.v:1816.12-1816.42" + wire width 8 \builder_csrbank0_bus_errors1_w + attribute \src "build/ls180/gateware/ls180.v:1815.6-1815.37" + wire \builder_csrbank0_bus_errors1_we + attribute \src "build/ls180/gateware/ls180.v:1810.12-1810.42" + wire width 8 \builder_csrbank0_bus_errors2_r + attribute \src "build/ls180/gateware/ls180.v:1809.6-1809.37" + wire \builder_csrbank0_bus_errors2_re + attribute \src "build/ls180/gateware/ls180.v:1812.12-1812.42" + wire width 8 \builder_csrbank0_bus_errors2_w + attribute \src "build/ls180/gateware/ls180.v:1811.6-1811.37" + wire \builder_csrbank0_bus_errors2_we + attribute \src "build/ls180/gateware/ls180.v:1806.12-1806.42" + wire width 8 \builder_csrbank0_bus_errors3_r + attribute \src "build/ls180/gateware/ls180.v:1805.6-1805.37" + wire \builder_csrbank0_bus_errors3_re + attribute \src "build/ls180/gateware/ls180.v:1808.12-1808.42" + wire width 8 \builder_csrbank0_bus_errors3_w + attribute \src "build/ls180/gateware/ls180.v:1807.6-1807.37" + wire \builder_csrbank0_bus_errors3_we + attribute \src "build/ls180/gateware/ls180.v:1786.6-1786.31" + wire \builder_csrbank0_reset0_r + attribute \src "build/ls180/gateware/ls180.v:1785.6-1785.32" + wire \builder_csrbank0_reset0_re + attribute \src "build/ls180/gateware/ls180.v:1788.6-1788.31" + wire \builder_csrbank0_reset0_w + attribute \src "build/ls180/gateware/ls180.v:1787.6-1787.32" + wire \builder_csrbank0_reset0_we + attribute \src "build/ls180/gateware/ls180.v:1802.12-1802.39" + wire width 8 \builder_csrbank0_scratch0_r + attribute \src "build/ls180/gateware/ls180.v:1801.6-1801.34" + wire \builder_csrbank0_scratch0_re + attribute \src "build/ls180/gateware/ls180.v:1804.12-1804.39" + wire width 8 \builder_csrbank0_scratch0_w + attribute \src "build/ls180/gateware/ls180.v:1803.6-1803.34" + wire \builder_csrbank0_scratch0_we + attribute \src "build/ls180/gateware/ls180.v:1798.12-1798.39" + wire width 8 \builder_csrbank0_scratch1_r + attribute \src "build/ls180/gateware/ls180.v:1797.6-1797.34" + wire \builder_csrbank0_scratch1_re + attribute \src "build/ls180/gateware/ls180.v:1800.12-1800.39" + wire width 8 \builder_csrbank0_scratch1_w + attribute \src "build/ls180/gateware/ls180.v:1799.6-1799.34" + wire \builder_csrbank0_scratch1_we + attribute \src "build/ls180/gateware/ls180.v:1794.12-1794.39" + wire width 8 \builder_csrbank0_scratch2_r + attribute \src "build/ls180/gateware/ls180.v:1793.6-1793.34" + wire \builder_csrbank0_scratch2_re + attribute \src "build/ls180/gateware/ls180.v:1796.12-1796.39" + wire width 8 \builder_csrbank0_scratch2_w + attribute \src "build/ls180/gateware/ls180.v:1795.6-1795.34" + wire \builder_csrbank0_scratch2_we + attribute \src "build/ls180/gateware/ls180.v:1790.12-1790.39" + wire width 8 \builder_csrbank0_scratch3_r + attribute \src "build/ls180/gateware/ls180.v:1789.6-1789.34" + wire \builder_csrbank0_scratch3_re + attribute \src "build/ls180/gateware/ls180.v:1792.12-1792.39" + wire width 8 \builder_csrbank0_scratch3_w + attribute \src "build/ls180/gateware/ls180.v:1791.6-1791.34" + wire \builder_csrbank0_scratch3_we + attribute \src "build/ls180/gateware/ls180.v:1821.6-1821.26" + wire \builder_csrbank0_sel + attribute \src "build/ls180/gateware/ls180.v:2288.6-2288.29" + wire \builder_csrbank10_en0_r + attribute \src "build/ls180/gateware/ls180.v:2287.6-2287.30" + wire \builder_csrbank10_en0_re + attribute \src "build/ls180/gateware/ls180.v:2290.6-2290.29" + wire \builder_csrbank10_en0_w + attribute \src "build/ls180/gateware/ls180.v:2289.6-2289.30" + wire \builder_csrbank10_en0_we + attribute \src "build/ls180/gateware/ls180.v:2312.6-2312.36" + wire \builder_csrbank10_ev_enable0_r + attribute \src "build/ls180/gateware/ls180.v:2311.6-2311.37" + wire \builder_csrbank10_ev_enable0_re + attribute \src "build/ls180/gateware/ls180.v:2314.6-2314.36" + wire \builder_csrbank10_ev_enable0_w + attribute \src "build/ls180/gateware/ls180.v:2313.6-2313.37" + wire \builder_csrbank10_ev_enable0_we + attribute \src "build/ls180/gateware/ls180.v:2268.12-2268.37" + wire width 8 \builder_csrbank10_load0_r + attribute \src "build/ls180/gateware/ls180.v:2267.6-2267.32" + wire \builder_csrbank10_load0_re + attribute \src "build/ls180/gateware/ls180.v:2270.12-2270.37" + wire width 8 \builder_csrbank10_load0_w + attribute \src "build/ls180/gateware/ls180.v:2269.6-2269.32" + wire \builder_csrbank10_load0_we + attribute \src "build/ls180/gateware/ls180.v:2264.12-2264.37" + wire width 8 \builder_csrbank10_load1_r + attribute \src "build/ls180/gateware/ls180.v:2263.6-2263.32" + wire \builder_csrbank10_load1_re + attribute \src "build/ls180/gateware/ls180.v:2266.12-2266.37" + wire width 8 \builder_csrbank10_load1_w + attribute \src "build/ls180/gateware/ls180.v:2265.6-2265.32" + wire \builder_csrbank10_load1_we + attribute \src "build/ls180/gateware/ls180.v:2260.12-2260.37" + wire width 8 \builder_csrbank10_load2_r + attribute \src "build/ls180/gateware/ls180.v:2259.6-2259.32" + wire \builder_csrbank10_load2_re + attribute \src "build/ls180/gateware/ls180.v:2262.12-2262.37" + wire width 8 \builder_csrbank10_load2_w + attribute \src "build/ls180/gateware/ls180.v:2261.6-2261.32" + wire \builder_csrbank10_load2_we + attribute \src "build/ls180/gateware/ls180.v:2256.12-2256.37" + wire width 8 \builder_csrbank10_load3_r + attribute \src "build/ls180/gateware/ls180.v:2255.6-2255.32" + wire \builder_csrbank10_load3_re + attribute \src "build/ls180/gateware/ls180.v:2258.12-2258.37" + wire width 8 \builder_csrbank10_load3_w + attribute \src "build/ls180/gateware/ls180.v:2257.6-2257.32" + wire \builder_csrbank10_load3_we + attribute \src "build/ls180/gateware/ls180.v:2284.12-2284.39" + wire width 8 \builder_csrbank10_reload0_r + attribute \src "build/ls180/gateware/ls180.v:2283.6-2283.34" + wire \builder_csrbank10_reload0_re + attribute \src "build/ls180/gateware/ls180.v:2286.12-2286.39" + wire width 8 \builder_csrbank10_reload0_w + attribute \src "build/ls180/gateware/ls180.v:2285.6-2285.34" + wire \builder_csrbank10_reload0_we + attribute \src "build/ls180/gateware/ls180.v:2280.12-2280.39" + wire width 8 \builder_csrbank10_reload1_r + attribute \src "build/ls180/gateware/ls180.v:2279.6-2279.34" + wire \builder_csrbank10_reload1_re + attribute \src "build/ls180/gateware/ls180.v:2282.12-2282.39" + wire width 8 \builder_csrbank10_reload1_w + attribute \src "build/ls180/gateware/ls180.v:2281.6-2281.34" + wire \builder_csrbank10_reload1_we + attribute \src "build/ls180/gateware/ls180.v:2276.12-2276.39" + wire width 8 \builder_csrbank10_reload2_r + attribute \src "build/ls180/gateware/ls180.v:2275.6-2275.34" + wire \builder_csrbank10_reload2_re + attribute \src "build/ls180/gateware/ls180.v:2278.12-2278.39" + wire width 8 \builder_csrbank10_reload2_w + attribute \src "build/ls180/gateware/ls180.v:2277.6-2277.34" + wire \builder_csrbank10_reload2_we + attribute \src "build/ls180/gateware/ls180.v:2272.12-2272.39" + wire width 8 \builder_csrbank10_reload3_r + attribute \src "build/ls180/gateware/ls180.v:2271.6-2271.34" + wire \builder_csrbank10_reload3_re + attribute \src "build/ls180/gateware/ls180.v:2274.12-2274.39" + wire width 8 \builder_csrbank10_reload3_w + attribute \src "build/ls180/gateware/ls180.v:2273.6-2273.34" + wire \builder_csrbank10_reload3_we + attribute \src "build/ls180/gateware/ls180.v:2315.6-2315.27" + wire \builder_csrbank10_sel + attribute \src "build/ls180/gateware/ls180.v:2292.6-2292.39" + wire \builder_csrbank10_update_value0_r + attribute \src "build/ls180/gateware/ls180.v:2291.6-2291.40" + wire \builder_csrbank10_update_value0_re + attribute \src "build/ls180/gateware/ls180.v:2294.6-2294.39" + wire \builder_csrbank10_update_value0_w + attribute \src "build/ls180/gateware/ls180.v:2293.6-2293.40" + wire \builder_csrbank10_update_value0_we + attribute \src "build/ls180/gateware/ls180.v:2308.12-2308.38" + wire width 8 \builder_csrbank10_value0_r + attribute \src "build/ls180/gateware/ls180.v:2307.6-2307.33" + wire \builder_csrbank10_value0_re + attribute \src "build/ls180/gateware/ls180.v:2310.12-2310.38" + wire width 8 \builder_csrbank10_value0_w + attribute \src "build/ls180/gateware/ls180.v:2309.6-2309.33" + wire \builder_csrbank10_value0_we + attribute \src "build/ls180/gateware/ls180.v:2304.12-2304.38" + wire width 8 \builder_csrbank10_value1_r + attribute \src "build/ls180/gateware/ls180.v:2303.6-2303.33" + wire \builder_csrbank10_value1_re + attribute \src "build/ls180/gateware/ls180.v:2306.12-2306.38" + wire width 8 \builder_csrbank10_value1_w + attribute \src "build/ls180/gateware/ls180.v:2305.6-2305.33" + wire \builder_csrbank10_value1_we + attribute \src "build/ls180/gateware/ls180.v:2300.12-2300.38" + wire width 8 \builder_csrbank10_value2_r + attribute \src "build/ls180/gateware/ls180.v:2299.6-2299.33" + wire \builder_csrbank10_value2_re + attribute \src "build/ls180/gateware/ls180.v:2302.12-2302.38" + wire width 8 \builder_csrbank10_value2_w + attribute \src "build/ls180/gateware/ls180.v:2301.6-2301.33" + wire \builder_csrbank10_value2_we + attribute \src "build/ls180/gateware/ls180.v:2296.12-2296.38" + wire width 8 \builder_csrbank10_value3_r + attribute \src "build/ls180/gateware/ls180.v:2295.6-2295.33" + wire \builder_csrbank10_value3_re + attribute \src "build/ls180/gateware/ls180.v:2298.12-2298.38" + wire width 8 \builder_csrbank10_value3_w + attribute \src "build/ls180/gateware/ls180.v:2297.6-2297.33" + wire \builder_csrbank10_value3_we + attribute \src "build/ls180/gateware/ls180.v:2329.12-2329.42" + wire width 2 \builder_csrbank11_ev_enable0_r + attribute \src "build/ls180/gateware/ls180.v:2328.6-2328.37" + wire \builder_csrbank11_ev_enable0_re + attribute \src "build/ls180/gateware/ls180.v:2331.12-2331.42" + wire width 2 \builder_csrbank11_ev_enable0_w + attribute \src "build/ls180/gateware/ls180.v:2330.6-2330.37" + wire \builder_csrbank11_ev_enable0_we + attribute \src "build/ls180/gateware/ls180.v:2325.6-2325.33" + wire \builder_csrbank11_rxempty_r + attribute \src "build/ls180/gateware/ls180.v:2324.6-2324.34" + wire \builder_csrbank11_rxempty_re + attribute \src "build/ls180/gateware/ls180.v:2327.6-2327.33" + wire \builder_csrbank11_rxempty_w + attribute \src "build/ls180/gateware/ls180.v:2326.6-2326.34" + wire \builder_csrbank11_rxempty_we + attribute \src "build/ls180/gateware/ls180.v:2337.6-2337.32" + wire \builder_csrbank11_rxfull_r + attribute \src "build/ls180/gateware/ls180.v:2336.6-2336.33" + wire \builder_csrbank11_rxfull_re + attribute \src "build/ls180/gateware/ls180.v:2339.6-2339.32" + wire \builder_csrbank11_rxfull_w + attribute \src "build/ls180/gateware/ls180.v:2338.6-2338.33" + wire \builder_csrbank11_rxfull_we + attribute \src "build/ls180/gateware/ls180.v:2340.6-2340.27" + wire \builder_csrbank11_sel + attribute \src "build/ls180/gateware/ls180.v:2333.6-2333.33" + wire \builder_csrbank11_txempty_r + attribute \src "build/ls180/gateware/ls180.v:2332.6-2332.34" + wire \builder_csrbank11_txempty_re + attribute \src "build/ls180/gateware/ls180.v:2335.6-2335.33" + wire \builder_csrbank11_txempty_w + attribute \src "build/ls180/gateware/ls180.v:2334.6-2334.34" + wire \builder_csrbank11_txempty_we + attribute \src "build/ls180/gateware/ls180.v:2321.6-2321.32" + wire \builder_csrbank11_txfull_r + attribute \src "build/ls180/gateware/ls180.v:2320.6-2320.33" + wire \builder_csrbank11_txfull_re + attribute \src "build/ls180/gateware/ls180.v:2323.6-2323.32" + wire \builder_csrbank11_txfull_w + attribute \src "build/ls180/gateware/ls180.v:2322.6-2322.33" + wire \builder_csrbank11_txfull_we + attribute \src "build/ls180/gateware/ls180.v:2361.6-2361.27" + wire \builder_csrbank12_sel + attribute \src "build/ls180/gateware/ls180.v:2358.12-2358.44" + wire width 8 \builder_csrbank12_tuning_word0_r + attribute \src "build/ls180/gateware/ls180.v:2357.6-2357.39" + wire \builder_csrbank12_tuning_word0_re + attribute \src "build/ls180/gateware/ls180.v:2360.12-2360.44" + wire width 8 \builder_csrbank12_tuning_word0_w + attribute \src "build/ls180/gateware/ls180.v:2359.6-2359.39" + wire \builder_csrbank12_tuning_word0_we + attribute \src "build/ls180/gateware/ls180.v:2354.12-2354.44" + wire width 8 \builder_csrbank12_tuning_word1_r + attribute \src "build/ls180/gateware/ls180.v:2353.6-2353.39" + wire \builder_csrbank12_tuning_word1_re + attribute \src "build/ls180/gateware/ls180.v:2356.12-2356.44" + wire width 8 \builder_csrbank12_tuning_word1_w + attribute \src "build/ls180/gateware/ls180.v:2355.6-2355.39" + wire \builder_csrbank12_tuning_word1_we + attribute \src "build/ls180/gateware/ls180.v:2350.12-2350.44" + wire width 8 \builder_csrbank12_tuning_word2_r + attribute \src "build/ls180/gateware/ls180.v:2349.6-2349.39" + wire \builder_csrbank12_tuning_word2_re + attribute \src "build/ls180/gateware/ls180.v:2352.12-2352.44" + wire width 8 \builder_csrbank12_tuning_word2_w + attribute \src "build/ls180/gateware/ls180.v:2351.6-2351.39" + wire \builder_csrbank12_tuning_word2_we + attribute \src "build/ls180/gateware/ls180.v:2346.12-2346.44" + wire width 8 \builder_csrbank12_tuning_word3_r + attribute \src "build/ls180/gateware/ls180.v:2345.6-2345.39" + wire \builder_csrbank12_tuning_word3_re + attribute \src "build/ls180/gateware/ls180.v:2348.12-2348.44" + wire width 8 \builder_csrbank12_tuning_word3_w + attribute \src "build/ls180/gateware/ls180.v:2347.6-2347.39" + wire \builder_csrbank12_tuning_word3_we + attribute \src "build/ls180/gateware/ls180.v:1827.12-1827.33" + wire width 8 \builder_csrbank1_in_r + attribute \src "build/ls180/gateware/ls180.v:1826.6-1826.28" + wire \builder_csrbank1_in_re + attribute \src "build/ls180/gateware/ls180.v:1829.12-1829.33" + wire width 8 \builder_csrbank1_in_w + attribute \src "build/ls180/gateware/ls180.v:1828.6-1828.28" + wire \builder_csrbank1_in_we + attribute \src "build/ls180/gateware/ls180.v:1830.6-1830.26" + wire \builder_csrbank1_sel + attribute \src "build/ls180/gateware/ls180.v:1836.12-1836.33" + wire width 8 \builder_csrbank2_in_r + attribute \src "build/ls180/gateware/ls180.v:1835.6-1835.28" + wire \builder_csrbank2_in_re + attribute \src "build/ls180/gateware/ls180.v:1838.12-1838.33" + wire width 8 \builder_csrbank2_in_w + attribute \src "build/ls180/gateware/ls180.v:1837.6-1837.28" + wire \builder_csrbank2_in_we + attribute \src "build/ls180/gateware/ls180.v:1839.6-1839.26" + wire \builder_csrbank2_sel + attribute \src "build/ls180/gateware/ls180.v:1873.12-1873.40" + wire width 8 \builder_csrbank3_dma_base0_r + attribute \src "build/ls180/gateware/ls180.v:1872.6-1872.35" + wire \builder_csrbank3_dma_base0_re + attribute \src "build/ls180/gateware/ls180.v:1875.12-1875.40" + wire width 8 \builder_csrbank3_dma_base0_w + attribute \src "build/ls180/gateware/ls180.v:1874.6-1874.35" + wire \builder_csrbank3_dma_base0_we + attribute \src "build/ls180/gateware/ls180.v:1869.12-1869.40" + wire width 8 \builder_csrbank3_dma_base1_r + attribute \src "build/ls180/gateware/ls180.v:1868.6-1868.35" + wire \builder_csrbank3_dma_base1_re + attribute \src "build/ls180/gateware/ls180.v:1871.12-1871.40" + wire width 8 \builder_csrbank3_dma_base1_w + attribute \src "build/ls180/gateware/ls180.v:1870.6-1870.35" + wire \builder_csrbank3_dma_base1_we + attribute \src "build/ls180/gateware/ls180.v:1865.12-1865.40" + wire width 8 \builder_csrbank3_dma_base2_r + attribute \src "build/ls180/gateware/ls180.v:1864.6-1864.35" + wire \builder_csrbank3_dma_base2_re + attribute \src "build/ls180/gateware/ls180.v:1867.12-1867.40" + wire width 8 \builder_csrbank3_dma_base2_w + attribute \src "build/ls180/gateware/ls180.v:1866.6-1866.35" + wire \builder_csrbank3_dma_base2_we + attribute \src "build/ls180/gateware/ls180.v:1861.12-1861.40" + wire width 8 \builder_csrbank3_dma_base3_r + attribute \src "build/ls180/gateware/ls180.v:1860.6-1860.35" + wire \builder_csrbank3_dma_base3_re + attribute \src "build/ls180/gateware/ls180.v:1863.12-1863.40" + wire width 8 \builder_csrbank3_dma_base3_w + attribute \src "build/ls180/gateware/ls180.v:1862.6-1862.35" + wire \builder_csrbank3_dma_base3_we + attribute \src "build/ls180/gateware/ls180.v:1857.12-1857.40" + wire width 8 \builder_csrbank3_dma_base4_r + attribute \src "build/ls180/gateware/ls180.v:1856.6-1856.35" + wire \builder_csrbank3_dma_base4_re + attribute \src "build/ls180/gateware/ls180.v:1859.12-1859.40" + wire width 8 \builder_csrbank3_dma_base4_w + attribute \src "build/ls180/gateware/ls180.v:1858.6-1858.35" + wire \builder_csrbank3_dma_base4_we + attribute \src "build/ls180/gateware/ls180.v:1853.12-1853.40" + wire width 8 \builder_csrbank3_dma_base5_r + attribute \src "build/ls180/gateware/ls180.v:1852.6-1852.35" + wire \builder_csrbank3_dma_base5_re + attribute \src "build/ls180/gateware/ls180.v:1855.12-1855.40" + wire width 8 \builder_csrbank3_dma_base5_w + attribute \src "build/ls180/gateware/ls180.v:1854.6-1854.35" + wire \builder_csrbank3_dma_base5_we + attribute \src "build/ls180/gateware/ls180.v:1849.12-1849.40" + wire width 8 \builder_csrbank3_dma_base6_r + attribute \src "build/ls180/gateware/ls180.v:1848.6-1848.35" + wire \builder_csrbank3_dma_base6_re + attribute \src "build/ls180/gateware/ls180.v:1851.12-1851.40" + wire width 8 \builder_csrbank3_dma_base6_w + attribute \src "build/ls180/gateware/ls180.v:1850.6-1850.35" + wire \builder_csrbank3_dma_base6_we + attribute \src "build/ls180/gateware/ls180.v:1845.12-1845.40" + wire width 8 \builder_csrbank3_dma_base7_r + attribute \src "build/ls180/gateware/ls180.v:1844.6-1844.35" + wire \builder_csrbank3_dma_base7_re + attribute \src "build/ls180/gateware/ls180.v:1847.12-1847.40" + wire width 8 \builder_csrbank3_dma_base7_w + attribute \src "build/ls180/gateware/ls180.v:1846.6-1846.35" + wire \builder_csrbank3_dma_base7_we + attribute \src "build/ls180/gateware/ls180.v:1897.6-1897.33" + wire \builder_csrbank3_dma_done_r + attribute \src "build/ls180/gateware/ls180.v:1896.6-1896.34" + wire \builder_csrbank3_dma_done_re + attribute \src "build/ls180/gateware/ls180.v:1899.6-1899.33" + wire \builder_csrbank3_dma_done_w + attribute \src "build/ls180/gateware/ls180.v:1898.6-1898.34" + wire \builder_csrbank3_dma_done_we + attribute \src "build/ls180/gateware/ls180.v:1893.6-1893.36" + wire \builder_csrbank3_dma_enable0_r + attribute \src "build/ls180/gateware/ls180.v:1892.6-1892.37" + wire \builder_csrbank3_dma_enable0_re + attribute \src "build/ls180/gateware/ls180.v:1895.6-1895.36" + wire \builder_csrbank3_dma_enable0_w + attribute \src "build/ls180/gateware/ls180.v:1894.6-1894.37" + wire \builder_csrbank3_dma_enable0_we + attribute \src "build/ls180/gateware/ls180.v:1889.12-1889.42" + wire width 8 \builder_csrbank3_dma_length0_r + attribute \src "build/ls180/gateware/ls180.v:1888.6-1888.37" + wire \builder_csrbank3_dma_length0_re + attribute \src "build/ls180/gateware/ls180.v:1891.12-1891.42" + wire width 8 \builder_csrbank3_dma_length0_w + attribute \src "build/ls180/gateware/ls180.v:1890.6-1890.37" + wire \builder_csrbank3_dma_length0_we + attribute \src "build/ls180/gateware/ls180.v:1885.12-1885.42" + wire width 8 \builder_csrbank3_dma_length1_r + attribute \src "build/ls180/gateware/ls180.v:1884.6-1884.37" + wire \builder_csrbank3_dma_length1_re + attribute \src "build/ls180/gateware/ls180.v:1887.12-1887.42" + wire width 8 \builder_csrbank3_dma_length1_w + attribute \src "build/ls180/gateware/ls180.v:1886.6-1886.37" + wire \builder_csrbank3_dma_length1_we + attribute \src "build/ls180/gateware/ls180.v:1881.12-1881.42" + wire width 8 \builder_csrbank3_dma_length2_r + attribute \src "build/ls180/gateware/ls180.v:1880.6-1880.37" + wire \builder_csrbank3_dma_length2_re + attribute \src "build/ls180/gateware/ls180.v:1883.12-1883.42" + wire width 8 \builder_csrbank3_dma_length2_w + attribute \src "build/ls180/gateware/ls180.v:1882.6-1882.37" + wire \builder_csrbank3_dma_length2_we + attribute \src "build/ls180/gateware/ls180.v:1877.12-1877.42" + wire width 8 \builder_csrbank3_dma_length3_r + attribute \src "build/ls180/gateware/ls180.v:1876.6-1876.37" + wire \builder_csrbank3_dma_length3_re + attribute \src "build/ls180/gateware/ls180.v:1879.12-1879.42" + wire width 8 \builder_csrbank3_dma_length3_w + attribute \src "build/ls180/gateware/ls180.v:1878.6-1878.37" + wire \builder_csrbank3_dma_length3_we + attribute \src "build/ls180/gateware/ls180.v:1901.6-1901.34" + wire \builder_csrbank3_dma_loop0_r + attribute \src "build/ls180/gateware/ls180.v:1900.6-1900.35" + wire \builder_csrbank3_dma_loop0_re + attribute \src "build/ls180/gateware/ls180.v:1903.6-1903.34" + wire \builder_csrbank3_dma_loop0_w + attribute \src "build/ls180/gateware/ls180.v:1902.6-1902.35" + wire \builder_csrbank3_dma_loop0_we + attribute \src "build/ls180/gateware/ls180.v:1904.6-1904.26" + wire \builder_csrbank3_sel + attribute \src "build/ls180/gateware/ls180.v:2034.12-2034.43" + wire width 8 \builder_csrbank4_block_count0_r + attribute \src "build/ls180/gateware/ls180.v:2033.6-2033.38" + wire \builder_csrbank4_block_count0_re + attribute \src "build/ls180/gateware/ls180.v:2036.12-2036.43" + wire width 8 \builder_csrbank4_block_count0_w + attribute \src "build/ls180/gateware/ls180.v:2035.6-2035.38" + wire \builder_csrbank4_block_count0_we + attribute \src "build/ls180/gateware/ls180.v:2030.12-2030.43" + wire width 8 \builder_csrbank4_block_count1_r + attribute \src "build/ls180/gateware/ls180.v:2029.6-2029.38" + wire \builder_csrbank4_block_count1_re + attribute \src "build/ls180/gateware/ls180.v:2032.12-2032.43" + wire width 8 \builder_csrbank4_block_count1_w + attribute \src "build/ls180/gateware/ls180.v:2031.6-2031.38" + wire \builder_csrbank4_block_count1_we + attribute \src "build/ls180/gateware/ls180.v:2026.12-2026.43" + wire width 8 \builder_csrbank4_block_count2_r + attribute \src "build/ls180/gateware/ls180.v:2025.6-2025.38" + wire \builder_csrbank4_block_count2_re + attribute \src "build/ls180/gateware/ls180.v:2028.12-2028.43" + wire width 8 \builder_csrbank4_block_count2_w + attribute \src "build/ls180/gateware/ls180.v:2027.6-2027.38" + wire \builder_csrbank4_block_count2_we + attribute \src "build/ls180/gateware/ls180.v:2022.12-2022.43" + wire width 8 \builder_csrbank4_block_count3_r + attribute \src "build/ls180/gateware/ls180.v:2021.6-2021.38" + wire \builder_csrbank4_block_count3_re + attribute \src "build/ls180/gateware/ls180.v:2024.12-2024.43" + wire width 8 \builder_csrbank4_block_count3_w + attribute \src "build/ls180/gateware/ls180.v:2023.6-2023.38" + wire \builder_csrbank4_block_count3_we + attribute \src "build/ls180/gateware/ls180.v:2018.12-2018.44" + wire width 8 \builder_csrbank4_block_length0_r + attribute \src "build/ls180/gateware/ls180.v:2017.6-2017.39" + wire \builder_csrbank4_block_length0_re + attribute \src "build/ls180/gateware/ls180.v:2020.12-2020.44" + wire width 8 \builder_csrbank4_block_length0_w + attribute \src "build/ls180/gateware/ls180.v:2019.6-2019.39" + wire \builder_csrbank4_block_length0_we + attribute \src "build/ls180/gateware/ls180.v:2014.12-2014.44" + wire width 2 \builder_csrbank4_block_length1_r + attribute \src "build/ls180/gateware/ls180.v:2013.6-2013.39" + wire \builder_csrbank4_block_length1_re + attribute \src "build/ls180/gateware/ls180.v:2016.12-2016.44" + wire width 2 \builder_csrbank4_block_length1_w + attribute \src "build/ls180/gateware/ls180.v:2015.6-2015.39" + wire \builder_csrbank4_block_length1_we + attribute \src "build/ls180/gateware/ls180.v:1922.12-1922.44" + wire width 8 \builder_csrbank4_cmd_argument0_r + attribute \src "build/ls180/gateware/ls180.v:1921.6-1921.39" + wire \builder_csrbank4_cmd_argument0_re + attribute \src "build/ls180/gateware/ls180.v:1924.12-1924.44" + wire width 8 \builder_csrbank4_cmd_argument0_w + attribute \src "build/ls180/gateware/ls180.v:1923.6-1923.39" + wire \builder_csrbank4_cmd_argument0_we + attribute \src "build/ls180/gateware/ls180.v:1918.12-1918.44" + wire width 8 \builder_csrbank4_cmd_argument1_r + attribute \src "build/ls180/gateware/ls180.v:1917.6-1917.39" + wire \builder_csrbank4_cmd_argument1_re + attribute \src "build/ls180/gateware/ls180.v:1920.12-1920.44" + wire width 8 \builder_csrbank4_cmd_argument1_w + attribute \src "build/ls180/gateware/ls180.v:1919.6-1919.39" + wire \builder_csrbank4_cmd_argument1_we + attribute \src "build/ls180/gateware/ls180.v:1914.12-1914.44" + wire width 8 \builder_csrbank4_cmd_argument2_r + attribute \src "build/ls180/gateware/ls180.v:1913.6-1913.39" + wire \builder_csrbank4_cmd_argument2_re + attribute \src "build/ls180/gateware/ls180.v:1916.12-1916.44" + wire width 8 \builder_csrbank4_cmd_argument2_w + attribute \src "build/ls180/gateware/ls180.v:1915.6-1915.39" + wire \builder_csrbank4_cmd_argument2_we + attribute \src "build/ls180/gateware/ls180.v:1910.12-1910.44" + wire width 8 \builder_csrbank4_cmd_argument3_r + attribute \src "build/ls180/gateware/ls180.v:1909.6-1909.39" + wire \builder_csrbank4_cmd_argument3_re + attribute \src "build/ls180/gateware/ls180.v:1912.12-1912.44" + wire width 8 \builder_csrbank4_cmd_argument3_w + attribute \src "build/ls180/gateware/ls180.v:1911.6-1911.39" + wire \builder_csrbank4_cmd_argument3_we + attribute \src "build/ls180/gateware/ls180.v:1938.12-1938.43" + wire width 8 \builder_csrbank4_cmd_command0_r + attribute \src "build/ls180/gateware/ls180.v:1937.6-1937.38" + wire \builder_csrbank4_cmd_command0_re + attribute \src "build/ls180/gateware/ls180.v:1940.12-1940.43" + wire width 8 \builder_csrbank4_cmd_command0_w + attribute \src "build/ls180/gateware/ls180.v:1939.6-1939.38" + wire \builder_csrbank4_cmd_command0_we + attribute \src "build/ls180/gateware/ls180.v:1934.12-1934.43" + wire width 8 \builder_csrbank4_cmd_command1_r + attribute \src "build/ls180/gateware/ls180.v:1933.6-1933.38" + wire \builder_csrbank4_cmd_command1_re + attribute \src "build/ls180/gateware/ls180.v:1936.12-1936.43" + wire width 8 \builder_csrbank4_cmd_command1_w + attribute \src "build/ls180/gateware/ls180.v:1935.6-1935.38" + wire \builder_csrbank4_cmd_command1_we + attribute \src "build/ls180/gateware/ls180.v:1930.12-1930.43" + wire width 8 \builder_csrbank4_cmd_command2_r + attribute \src "build/ls180/gateware/ls180.v:1929.6-1929.38" + wire \builder_csrbank4_cmd_command2_re + attribute \src "build/ls180/gateware/ls180.v:1932.12-1932.43" + wire width 8 \builder_csrbank4_cmd_command2_w + attribute \src "build/ls180/gateware/ls180.v:1931.6-1931.38" + wire \builder_csrbank4_cmd_command2_we + attribute \src "build/ls180/gateware/ls180.v:1926.12-1926.43" + wire width 8 \builder_csrbank4_cmd_command3_r + attribute \src "build/ls180/gateware/ls180.v:1925.6-1925.38" + wire \builder_csrbank4_cmd_command3_re + attribute \src "build/ls180/gateware/ls180.v:1928.12-1928.43" + wire width 8 \builder_csrbank4_cmd_command3_w + attribute \src "build/ls180/gateware/ls180.v:1927.6-1927.38" + wire \builder_csrbank4_cmd_command3_we + attribute \src "build/ls180/gateware/ls180.v:2006.12-2006.40" + wire width 4 \builder_csrbank4_cmd_event_r + attribute \src "build/ls180/gateware/ls180.v:2005.6-2005.35" + wire \builder_csrbank4_cmd_event_re + attribute \src "build/ls180/gateware/ls180.v:2008.12-2008.40" + wire width 4 \builder_csrbank4_cmd_event_w + attribute \src "build/ls180/gateware/ls180.v:2007.6-2007.35" + wire \builder_csrbank4_cmd_event_we + attribute \src "build/ls180/gateware/ls180.v:2002.12-2002.44" + wire width 8 \builder_csrbank4_cmd_response0_r + attribute \src "build/ls180/gateware/ls180.v:2001.6-2001.39" + wire \builder_csrbank4_cmd_response0_re + attribute \src "build/ls180/gateware/ls180.v:2004.12-2004.44" + wire width 8 \builder_csrbank4_cmd_response0_w + attribute \src "build/ls180/gateware/ls180.v:2003.6-2003.39" + wire \builder_csrbank4_cmd_response0_we + attribute \src "build/ls180/gateware/ls180.v:1962.12-1962.45" + wire width 8 \builder_csrbank4_cmd_response10_r + attribute \src "build/ls180/gateware/ls180.v:1961.6-1961.40" + wire \builder_csrbank4_cmd_response10_re + attribute \src "build/ls180/gateware/ls180.v:1964.12-1964.45" + wire width 8 \builder_csrbank4_cmd_response10_w + attribute \src "build/ls180/gateware/ls180.v:1963.6-1963.40" + wire \builder_csrbank4_cmd_response10_we + attribute \src "build/ls180/gateware/ls180.v:1958.12-1958.45" + wire width 8 \builder_csrbank4_cmd_response11_r + attribute \src "build/ls180/gateware/ls180.v:1957.6-1957.40" + wire \builder_csrbank4_cmd_response11_re + attribute \src "build/ls180/gateware/ls180.v:1960.12-1960.45" + wire width 8 \builder_csrbank4_cmd_response11_w + attribute \src "build/ls180/gateware/ls180.v:1959.6-1959.40" + wire \builder_csrbank4_cmd_response11_we + attribute \src "build/ls180/gateware/ls180.v:1954.12-1954.45" + wire width 8 \builder_csrbank4_cmd_response12_r + attribute \src "build/ls180/gateware/ls180.v:1953.6-1953.40" + wire \builder_csrbank4_cmd_response12_re + attribute \src "build/ls180/gateware/ls180.v:1956.12-1956.45" + wire width 8 \builder_csrbank4_cmd_response12_w + attribute \src "build/ls180/gateware/ls180.v:1955.6-1955.40" + wire \builder_csrbank4_cmd_response12_we + attribute \src "build/ls180/gateware/ls180.v:1950.12-1950.45" + wire width 8 \builder_csrbank4_cmd_response13_r + attribute \src "build/ls180/gateware/ls180.v:1949.6-1949.40" + wire \builder_csrbank4_cmd_response13_re + attribute \src "build/ls180/gateware/ls180.v:1952.12-1952.45" + wire width 8 \builder_csrbank4_cmd_response13_w + attribute \src "build/ls180/gateware/ls180.v:1951.6-1951.40" + wire \builder_csrbank4_cmd_response13_we + attribute \src "build/ls180/gateware/ls180.v:1946.12-1946.45" + wire width 8 \builder_csrbank4_cmd_response14_r + attribute \src "build/ls180/gateware/ls180.v:1945.6-1945.40" + wire \builder_csrbank4_cmd_response14_re + attribute \src "build/ls180/gateware/ls180.v:1948.12-1948.45" + wire width 8 \builder_csrbank4_cmd_response14_w + attribute \src "build/ls180/gateware/ls180.v:1947.6-1947.40" + wire \builder_csrbank4_cmd_response14_we + attribute \src "build/ls180/gateware/ls180.v:1942.12-1942.45" + wire width 8 \builder_csrbank4_cmd_response15_r + attribute \src "build/ls180/gateware/ls180.v:1941.6-1941.40" + wire \builder_csrbank4_cmd_response15_re + attribute \src "build/ls180/gateware/ls180.v:1944.12-1944.45" + wire width 8 \builder_csrbank4_cmd_response15_w + attribute \src "build/ls180/gateware/ls180.v:1943.6-1943.40" + wire \builder_csrbank4_cmd_response15_we + attribute \src "build/ls180/gateware/ls180.v:1998.12-1998.44" + wire width 8 \builder_csrbank4_cmd_response1_r + attribute \src "build/ls180/gateware/ls180.v:1997.6-1997.39" + wire \builder_csrbank4_cmd_response1_re + attribute \src "build/ls180/gateware/ls180.v:2000.12-2000.44" + wire width 8 \builder_csrbank4_cmd_response1_w + attribute \src "build/ls180/gateware/ls180.v:1999.6-1999.39" + wire \builder_csrbank4_cmd_response1_we + attribute \src "build/ls180/gateware/ls180.v:1994.12-1994.44" + wire width 8 \builder_csrbank4_cmd_response2_r + attribute \src "build/ls180/gateware/ls180.v:1993.6-1993.39" + wire \builder_csrbank4_cmd_response2_re + attribute \src "build/ls180/gateware/ls180.v:1996.12-1996.44" + wire width 8 \builder_csrbank4_cmd_response2_w + attribute \src "build/ls180/gateware/ls180.v:1995.6-1995.39" + wire \builder_csrbank4_cmd_response2_we + attribute \src "build/ls180/gateware/ls180.v:1990.12-1990.44" + wire width 8 \builder_csrbank4_cmd_response3_r + attribute \src "build/ls180/gateware/ls180.v:1989.6-1989.39" + wire \builder_csrbank4_cmd_response3_re + attribute \src "build/ls180/gateware/ls180.v:1992.12-1992.44" + wire width 8 \builder_csrbank4_cmd_response3_w + attribute \src "build/ls180/gateware/ls180.v:1991.6-1991.39" + wire \builder_csrbank4_cmd_response3_we + attribute \src "build/ls180/gateware/ls180.v:1986.12-1986.44" + wire width 8 \builder_csrbank4_cmd_response4_r + attribute \src "build/ls180/gateware/ls180.v:1985.6-1985.39" + wire \builder_csrbank4_cmd_response4_re + attribute \src "build/ls180/gateware/ls180.v:1988.12-1988.44" + wire width 8 \builder_csrbank4_cmd_response4_w + attribute \src "build/ls180/gateware/ls180.v:1987.6-1987.39" + wire \builder_csrbank4_cmd_response4_we + attribute \src "build/ls180/gateware/ls180.v:1982.12-1982.44" + wire width 8 \builder_csrbank4_cmd_response5_r + attribute \src "build/ls180/gateware/ls180.v:1981.6-1981.39" + wire \builder_csrbank4_cmd_response5_re + attribute \src "build/ls180/gateware/ls180.v:1984.12-1984.44" + wire width 8 \builder_csrbank4_cmd_response5_w + attribute \src "build/ls180/gateware/ls180.v:1983.6-1983.39" + wire \builder_csrbank4_cmd_response5_we + attribute \src "build/ls180/gateware/ls180.v:1978.12-1978.44" + wire width 8 \builder_csrbank4_cmd_response6_r + attribute \src "build/ls180/gateware/ls180.v:1977.6-1977.39" + wire \builder_csrbank4_cmd_response6_re + attribute \src "build/ls180/gateware/ls180.v:1980.12-1980.44" + wire width 8 \builder_csrbank4_cmd_response6_w + attribute \src "build/ls180/gateware/ls180.v:1979.6-1979.39" + wire \builder_csrbank4_cmd_response6_we + attribute \src "build/ls180/gateware/ls180.v:1974.12-1974.44" + wire width 8 \builder_csrbank4_cmd_response7_r + attribute \src "build/ls180/gateware/ls180.v:1973.6-1973.39" + wire \builder_csrbank4_cmd_response7_re + attribute \src "build/ls180/gateware/ls180.v:1976.12-1976.44" + wire width 8 \builder_csrbank4_cmd_response7_w + attribute \src "build/ls180/gateware/ls180.v:1975.6-1975.39" + wire \builder_csrbank4_cmd_response7_we + attribute \src "build/ls180/gateware/ls180.v:1970.12-1970.44" + wire width 8 \builder_csrbank4_cmd_response8_r + attribute \src "build/ls180/gateware/ls180.v:1969.6-1969.39" + wire \builder_csrbank4_cmd_response8_re + attribute \src "build/ls180/gateware/ls180.v:1972.12-1972.44" + wire width 8 \builder_csrbank4_cmd_response8_w + attribute \src "build/ls180/gateware/ls180.v:1971.6-1971.39" + wire \builder_csrbank4_cmd_response8_we + attribute \src "build/ls180/gateware/ls180.v:1966.12-1966.44" + wire width 8 \builder_csrbank4_cmd_response9_r + attribute \src "build/ls180/gateware/ls180.v:1965.6-1965.39" + wire \builder_csrbank4_cmd_response9_re + attribute \src "build/ls180/gateware/ls180.v:1968.12-1968.44" + wire width 8 \builder_csrbank4_cmd_response9_w + attribute \src "build/ls180/gateware/ls180.v:1967.6-1967.39" + wire \builder_csrbank4_cmd_response9_we + attribute \src "build/ls180/gateware/ls180.v:2010.12-2010.41" + wire width 4 \builder_csrbank4_data_event_r + attribute \src "build/ls180/gateware/ls180.v:2009.6-2009.36" + wire \builder_csrbank4_data_event_re + attribute \src "build/ls180/gateware/ls180.v:2012.12-2012.41" + wire width 4 \builder_csrbank4_data_event_w + attribute \src "build/ls180/gateware/ls180.v:2011.6-2011.36" + wire \builder_csrbank4_data_event_we + attribute \src "build/ls180/gateware/ls180.v:2037.6-2037.26" + wire \builder_csrbank4_sel + attribute \src "build/ls180/gateware/ls180.v:2071.12-2071.40" + wire width 8 \builder_csrbank5_dma_base0_r + attribute \src "build/ls180/gateware/ls180.v:2070.6-2070.35" + wire \builder_csrbank5_dma_base0_re + attribute \src "build/ls180/gateware/ls180.v:2073.12-2073.40" + wire width 8 \builder_csrbank5_dma_base0_w + attribute \src "build/ls180/gateware/ls180.v:2072.6-2072.35" + wire \builder_csrbank5_dma_base0_we + attribute \src "build/ls180/gateware/ls180.v:2067.12-2067.40" + wire width 8 \builder_csrbank5_dma_base1_r + attribute \src "build/ls180/gateware/ls180.v:2066.6-2066.35" + wire \builder_csrbank5_dma_base1_re + attribute \src "build/ls180/gateware/ls180.v:2069.12-2069.40" + wire width 8 \builder_csrbank5_dma_base1_w + attribute \src "build/ls180/gateware/ls180.v:2068.6-2068.35" + wire \builder_csrbank5_dma_base1_we + attribute \src "build/ls180/gateware/ls180.v:2063.12-2063.40" + wire width 8 \builder_csrbank5_dma_base2_r + attribute \src "build/ls180/gateware/ls180.v:2062.6-2062.35" + wire \builder_csrbank5_dma_base2_re + attribute \src "build/ls180/gateware/ls180.v:2065.12-2065.40" + wire width 8 \builder_csrbank5_dma_base2_w + attribute \src "build/ls180/gateware/ls180.v:2064.6-2064.35" + wire \builder_csrbank5_dma_base2_we + attribute \src "build/ls180/gateware/ls180.v:2059.12-2059.40" + wire width 8 \builder_csrbank5_dma_base3_r + attribute \src "build/ls180/gateware/ls180.v:2058.6-2058.35" + wire \builder_csrbank5_dma_base3_re + attribute \src "build/ls180/gateware/ls180.v:2061.12-2061.40" + wire width 8 \builder_csrbank5_dma_base3_w + attribute \src "build/ls180/gateware/ls180.v:2060.6-2060.35" + wire \builder_csrbank5_dma_base3_we + attribute \src "build/ls180/gateware/ls180.v:2055.12-2055.40" + wire width 8 \builder_csrbank5_dma_base4_r + attribute \src "build/ls180/gateware/ls180.v:2054.6-2054.35" + wire \builder_csrbank5_dma_base4_re + attribute \src "build/ls180/gateware/ls180.v:2057.12-2057.40" + wire width 8 \builder_csrbank5_dma_base4_w + attribute \src "build/ls180/gateware/ls180.v:2056.6-2056.35" + wire \builder_csrbank5_dma_base4_we + attribute \src "build/ls180/gateware/ls180.v:2051.12-2051.40" + wire width 8 \builder_csrbank5_dma_base5_r + attribute \src "build/ls180/gateware/ls180.v:2050.6-2050.35" + wire \builder_csrbank5_dma_base5_re + attribute \src "build/ls180/gateware/ls180.v:2053.12-2053.40" + wire width 8 \builder_csrbank5_dma_base5_w + attribute \src "build/ls180/gateware/ls180.v:2052.6-2052.35" + wire \builder_csrbank5_dma_base5_we + attribute \src "build/ls180/gateware/ls180.v:2047.12-2047.40" + wire width 8 \builder_csrbank5_dma_base6_r + attribute \src "build/ls180/gateware/ls180.v:2046.6-2046.35" + wire \builder_csrbank5_dma_base6_re + attribute \src "build/ls180/gateware/ls180.v:2049.12-2049.40" + wire width 8 \builder_csrbank5_dma_base6_w + attribute \src "build/ls180/gateware/ls180.v:2048.6-2048.35" + wire \builder_csrbank5_dma_base6_we + attribute \src "build/ls180/gateware/ls180.v:2043.12-2043.40" + wire width 8 \builder_csrbank5_dma_base7_r + attribute \src "build/ls180/gateware/ls180.v:2042.6-2042.35" + wire \builder_csrbank5_dma_base7_re + attribute \src "build/ls180/gateware/ls180.v:2045.12-2045.40" + wire width 8 \builder_csrbank5_dma_base7_w + attribute \src "build/ls180/gateware/ls180.v:2044.6-2044.35" + wire \builder_csrbank5_dma_base7_we + attribute \src "build/ls180/gateware/ls180.v:2095.6-2095.33" + wire \builder_csrbank5_dma_done_r + attribute \src "build/ls180/gateware/ls180.v:2094.6-2094.34" + wire \builder_csrbank5_dma_done_re + attribute \src "build/ls180/gateware/ls180.v:2097.6-2097.33" + wire \builder_csrbank5_dma_done_w + attribute \src "build/ls180/gateware/ls180.v:2096.6-2096.34" + wire \builder_csrbank5_dma_done_we + attribute \src "build/ls180/gateware/ls180.v:2091.6-2091.36" + wire \builder_csrbank5_dma_enable0_r + attribute \src "build/ls180/gateware/ls180.v:2090.6-2090.37" + wire \builder_csrbank5_dma_enable0_re + attribute \src "build/ls180/gateware/ls180.v:2093.6-2093.36" + wire \builder_csrbank5_dma_enable0_w + attribute \src "build/ls180/gateware/ls180.v:2092.6-2092.37" + wire \builder_csrbank5_dma_enable0_we + attribute \src "build/ls180/gateware/ls180.v:2087.12-2087.42" + wire width 8 \builder_csrbank5_dma_length0_r + attribute \src "build/ls180/gateware/ls180.v:2086.6-2086.37" + wire \builder_csrbank5_dma_length0_re + attribute \src "build/ls180/gateware/ls180.v:2089.12-2089.42" + wire width 8 \builder_csrbank5_dma_length0_w + attribute \src "build/ls180/gateware/ls180.v:2088.6-2088.37" + wire \builder_csrbank5_dma_length0_we + attribute \src "build/ls180/gateware/ls180.v:2083.12-2083.42" + wire width 8 \builder_csrbank5_dma_length1_r + attribute \src "build/ls180/gateware/ls180.v:2082.6-2082.37" + wire \builder_csrbank5_dma_length1_re + attribute \src "build/ls180/gateware/ls180.v:2085.12-2085.42" + wire width 8 \builder_csrbank5_dma_length1_w + attribute \src "build/ls180/gateware/ls180.v:2084.6-2084.37" + wire \builder_csrbank5_dma_length1_we + attribute \src "build/ls180/gateware/ls180.v:2079.12-2079.42" + wire width 8 \builder_csrbank5_dma_length2_r + attribute \src "build/ls180/gateware/ls180.v:2078.6-2078.37" + wire \builder_csrbank5_dma_length2_re + attribute \src "build/ls180/gateware/ls180.v:2081.12-2081.42" + wire width 8 \builder_csrbank5_dma_length2_w + attribute \src "build/ls180/gateware/ls180.v:2080.6-2080.37" + wire \builder_csrbank5_dma_length2_we + attribute \src "build/ls180/gateware/ls180.v:2075.12-2075.42" + wire width 8 \builder_csrbank5_dma_length3_r + attribute \src "build/ls180/gateware/ls180.v:2074.6-2074.37" + wire \builder_csrbank5_dma_length3_re + attribute \src "build/ls180/gateware/ls180.v:2077.12-2077.42" + wire width 8 \builder_csrbank5_dma_length3_w + attribute \src "build/ls180/gateware/ls180.v:2076.6-2076.37" + wire \builder_csrbank5_dma_length3_we + attribute \src "build/ls180/gateware/ls180.v:2099.6-2099.34" + wire \builder_csrbank5_dma_loop0_r + attribute \src "build/ls180/gateware/ls180.v:2098.6-2098.35" + wire \builder_csrbank5_dma_loop0_re + attribute \src "build/ls180/gateware/ls180.v:2101.6-2101.34" + wire \builder_csrbank5_dma_loop0_w + attribute \src "build/ls180/gateware/ls180.v:2100.6-2100.35" + wire \builder_csrbank5_dma_loop0_we + attribute \src "build/ls180/gateware/ls180.v:2115.12-2115.42" + wire width 8 \builder_csrbank5_dma_offset0_r + attribute \src "build/ls180/gateware/ls180.v:2114.6-2114.37" + wire \builder_csrbank5_dma_offset0_re + attribute \src "build/ls180/gateware/ls180.v:2117.12-2117.42" + wire width 8 \builder_csrbank5_dma_offset0_w + attribute \src "build/ls180/gateware/ls180.v:2116.6-2116.37" + wire \builder_csrbank5_dma_offset0_we + attribute \src "build/ls180/gateware/ls180.v:2111.12-2111.42" + wire width 8 \builder_csrbank5_dma_offset1_r + attribute \src "build/ls180/gateware/ls180.v:2110.6-2110.37" + wire \builder_csrbank5_dma_offset1_re + attribute \src "build/ls180/gateware/ls180.v:2113.12-2113.42" + wire width 8 \builder_csrbank5_dma_offset1_w + attribute \src "build/ls180/gateware/ls180.v:2112.6-2112.37" + wire \builder_csrbank5_dma_offset1_we + attribute \src "build/ls180/gateware/ls180.v:2107.12-2107.42" + wire width 8 \builder_csrbank5_dma_offset2_r + attribute \src "build/ls180/gateware/ls180.v:2106.6-2106.37" + wire \builder_csrbank5_dma_offset2_re + attribute \src "build/ls180/gateware/ls180.v:2109.12-2109.42" + wire width 8 \builder_csrbank5_dma_offset2_w + attribute \src "build/ls180/gateware/ls180.v:2108.6-2108.37" + wire \builder_csrbank5_dma_offset2_we + attribute \src "build/ls180/gateware/ls180.v:2103.12-2103.42" + wire width 8 \builder_csrbank5_dma_offset3_r + attribute \src "build/ls180/gateware/ls180.v:2102.6-2102.37" + wire \builder_csrbank5_dma_offset3_re + attribute \src "build/ls180/gateware/ls180.v:2105.12-2105.42" + wire width 8 \builder_csrbank5_dma_offset3_w + attribute \src "build/ls180/gateware/ls180.v:2104.6-2104.37" + wire \builder_csrbank5_dma_offset3_we + attribute \src "build/ls180/gateware/ls180.v:2118.6-2118.26" + wire \builder_csrbank5_sel + attribute \src "build/ls180/gateware/ls180.v:2124.6-2124.36" + wire \builder_csrbank6_card_detect_r + attribute \src "build/ls180/gateware/ls180.v:2123.6-2123.37" + wire \builder_csrbank6_card_detect_re + attribute \src "build/ls180/gateware/ls180.v:2126.6-2126.36" + wire \builder_csrbank6_card_detect_w + attribute \src "build/ls180/gateware/ls180.v:2125.6-2125.37" + wire \builder_csrbank6_card_detect_we + attribute \src "build/ls180/gateware/ls180.v:2132.12-2132.47" + wire width 8 \builder_csrbank6_clocker_divider0_r + attribute \src "build/ls180/gateware/ls180.v:2131.6-2131.42" + wire \builder_csrbank6_clocker_divider0_re + attribute \src "build/ls180/gateware/ls180.v:2134.12-2134.47" + wire width 8 \builder_csrbank6_clocker_divider0_w + attribute \src "build/ls180/gateware/ls180.v:2133.6-2133.42" + wire \builder_csrbank6_clocker_divider0_we + attribute \src "build/ls180/gateware/ls180.v:2128.6-2128.41" + wire \builder_csrbank6_clocker_divider1_r + attribute \src "build/ls180/gateware/ls180.v:2127.6-2127.42" + wire \builder_csrbank6_clocker_divider1_re + attribute \src "build/ls180/gateware/ls180.v:2130.6-2130.41" + wire \builder_csrbank6_clocker_divider1_w + attribute \src "build/ls180/gateware/ls180.v:2129.6-2129.42" + wire \builder_csrbank6_clocker_divider1_we + attribute \src "build/ls180/gateware/ls180.v:2135.6-2135.26" + wire \builder_csrbank6_sel + attribute \src "build/ls180/gateware/ls180.v:2141.12-2141.44" + wire width 4 \builder_csrbank7_dfii_control0_r + attribute \src "build/ls180/gateware/ls180.v:2140.6-2140.39" + wire \builder_csrbank7_dfii_control0_re + attribute \src "build/ls180/gateware/ls180.v:2143.12-2143.44" + wire width 4 \builder_csrbank7_dfii_control0_w + attribute \src "build/ls180/gateware/ls180.v:2142.6-2142.39" + wire \builder_csrbank7_dfii_control0_we + attribute \src "build/ls180/gateware/ls180.v:2153.12-2153.48" + wire width 8 \builder_csrbank7_dfii_pi0_address0_r + attribute \src "build/ls180/gateware/ls180.v:2152.6-2152.43" + wire \builder_csrbank7_dfii_pi0_address0_re + attribute \src "build/ls180/gateware/ls180.v:2155.12-2155.48" + wire width 8 \builder_csrbank7_dfii_pi0_address0_w + attribute \src "build/ls180/gateware/ls180.v:2154.6-2154.43" + wire \builder_csrbank7_dfii_pi0_address0_we + attribute \src "build/ls180/gateware/ls180.v:2149.12-2149.48" + wire width 5 \builder_csrbank7_dfii_pi0_address1_r + attribute \src "build/ls180/gateware/ls180.v:2148.6-2148.43" + wire \builder_csrbank7_dfii_pi0_address1_re + attribute \src "build/ls180/gateware/ls180.v:2151.12-2151.48" + wire width 5 \builder_csrbank7_dfii_pi0_address1_w + attribute \src "build/ls180/gateware/ls180.v:2150.6-2150.43" + wire \builder_csrbank7_dfii_pi0_address1_we + attribute \src "build/ls180/gateware/ls180.v:2157.12-2157.49" + wire width 2 \builder_csrbank7_dfii_pi0_baddress0_r + attribute \src "build/ls180/gateware/ls180.v:2156.6-2156.44" + wire \builder_csrbank7_dfii_pi0_baddress0_re + attribute \src "build/ls180/gateware/ls180.v:2159.12-2159.49" + wire width 2 \builder_csrbank7_dfii_pi0_baddress0_w + attribute \src "build/ls180/gateware/ls180.v:2158.6-2158.44" + wire \builder_csrbank7_dfii_pi0_baddress0_we + attribute \src "build/ls180/gateware/ls180.v:2145.12-2145.48" + wire width 6 \builder_csrbank7_dfii_pi0_command0_r + attribute \src "build/ls180/gateware/ls180.v:2144.6-2144.43" + wire \builder_csrbank7_dfii_pi0_command0_re + attribute \src "build/ls180/gateware/ls180.v:2147.12-2147.48" + wire width 6 \builder_csrbank7_dfii_pi0_command0_w + attribute \src "build/ls180/gateware/ls180.v:2146.6-2146.43" + wire \builder_csrbank7_dfii_pi0_command0_we + attribute \src "build/ls180/gateware/ls180.v:2173.12-2173.47" + wire width 8 \builder_csrbank7_dfii_pi0_rddata0_r + attribute \src "build/ls180/gateware/ls180.v:2172.6-2172.42" + wire \builder_csrbank7_dfii_pi0_rddata0_re + attribute \src "build/ls180/gateware/ls180.v:2175.12-2175.47" + wire width 8 \builder_csrbank7_dfii_pi0_rddata0_w + attribute \src "build/ls180/gateware/ls180.v:2174.6-2174.42" + wire \builder_csrbank7_dfii_pi0_rddata0_we + attribute \src "build/ls180/gateware/ls180.v:2169.12-2169.47" + wire width 8 \builder_csrbank7_dfii_pi0_rddata1_r + attribute \src "build/ls180/gateware/ls180.v:2168.6-2168.42" + wire \builder_csrbank7_dfii_pi0_rddata1_re + attribute \src "build/ls180/gateware/ls180.v:2171.12-2171.47" + wire width 8 \builder_csrbank7_dfii_pi0_rddata1_w + attribute \src "build/ls180/gateware/ls180.v:2170.6-2170.42" + wire \builder_csrbank7_dfii_pi0_rddata1_we + attribute \src "build/ls180/gateware/ls180.v:2165.12-2165.47" + wire width 8 \builder_csrbank7_dfii_pi0_wrdata0_r + attribute \src "build/ls180/gateware/ls180.v:2164.6-2164.42" + wire \builder_csrbank7_dfii_pi0_wrdata0_re + attribute \src "build/ls180/gateware/ls180.v:2167.12-2167.47" + wire width 8 \builder_csrbank7_dfii_pi0_wrdata0_w + attribute \src "build/ls180/gateware/ls180.v:2166.6-2166.42" + wire \builder_csrbank7_dfii_pi0_wrdata0_we + attribute \src "build/ls180/gateware/ls180.v:2161.12-2161.47" + wire width 8 \builder_csrbank7_dfii_pi0_wrdata1_r + attribute \src "build/ls180/gateware/ls180.v:2160.6-2160.42" + wire \builder_csrbank7_dfii_pi0_wrdata1_re + attribute \src "build/ls180/gateware/ls180.v:2163.12-2163.47" + wire width 8 \builder_csrbank7_dfii_pi0_wrdata1_w + attribute \src "build/ls180/gateware/ls180.v:2162.6-2162.42" + wire \builder_csrbank7_dfii_pi0_wrdata1_we + attribute \src "build/ls180/gateware/ls180.v:2176.6-2176.26" + wire \builder_csrbank7_sel + attribute \src "build/ls180/gateware/ls180.v:2186.12-2186.39" + wire width 8 \builder_csrbank8_control0_r + attribute \src "build/ls180/gateware/ls180.v:2185.6-2185.34" + wire \builder_csrbank8_control0_re + attribute \src "build/ls180/gateware/ls180.v:2188.12-2188.39" + wire width 8 \builder_csrbank8_control0_w + attribute \src "build/ls180/gateware/ls180.v:2187.6-2187.34" + wire \builder_csrbank8_control0_we + attribute \src "build/ls180/gateware/ls180.v:2182.12-2182.39" + wire width 8 \builder_csrbank8_control1_r + attribute \src "build/ls180/gateware/ls180.v:2181.6-2181.34" + wire \builder_csrbank8_control1_re + attribute \src "build/ls180/gateware/ls180.v:2184.12-2184.39" + wire width 8 \builder_csrbank8_control1_w + attribute \src "build/ls180/gateware/ls180.v:2183.6-2183.34" + wire \builder_csrbank8_control1_we + attribute \src "build/ls180/gateware/ls180.v:2202.6-2202.28" + wire \builder_csrbank8_cs0_r + attribute \src "build/ls180/gateware/ls180.v:2201.6-2201.29" + wire \builder_csrbank8_cs0_re + attribute \src "build/ls180/gateware/ls180.v:2204.6-2204.28" + wire \builder_csrbank8_cs0_w + attribute \src "build/ls180/gateware/ls180.v:2203.6-2203.29" + wire \builder_csrbank8_cs0_we + attribute \src "build/ls180/gateware/ls180.v:2206.6-2206.34" + wire \builder_csrbank8_loopback0_r + attribute \src "build/ls180/gateware/ls180.v:2205.6-2205.35" + wire \builder_csrbank8_loopback0_re + attribute \src "build/ls180/gateware/ls180.v:2208.6-2208.34" + wire \builder_csrbank8_loopback0_w + attribute \src "build/ls180/gateware/ls180.v:2207.6-2207.35" + wire \builder_csrbank8_loopback0_we + attribute \src "build/ls180/gateware/ls180.v:2198.12-2198.35" + wire width 8 \builder_csrbank8_miso_r + attribute \src "build/ls180/gateware/ls180.v:2197.6-2197.30" + wire \builder_csrbank8_miso_re + attribute \src "build/ls180/gateware/ls180.v:2200.12-2200.35" + wire width 8 \builder_csrbank8_miso_w + attribute \src "build/ls180/gateware/ls180.v:2199.6-2199.30" + wire \builder_csrbank8_miso_we + attribute \src "build/ls180/gateware/ls180.v:2194.12-2194.36" + wire width 8 \builder_csrbank8_mosi0_r + attribute \src "build/ls180/gateware/ls180.v:2193.6-2193.31" + wire \builder_csrbank8_mosi0_re + attribute \src "build/ls180/gateware/ls180.v:2196.12-2196.36" + wire width 8 \builder_csrbank8_mosi0_w + attribute \src "build/ls180/gateware/ls180.v:2195.6-2195.31" + wire \builder_csrbank8_mosi0_we + attribute \src "build/ls180/gateware/ls180.v:2209.6-2209.26" + wire \builder_csrbank8_sel + attribute \src "build/ls180/gateware/ls180.v:2190.6-2190.31" + wire \builder_csrbank8_status_r + attribute \src "build/ls180/gateware/ls180.v:2189.6-2189.32" + wire \builder_csrbank8_status_re + attribute \src "build/ls180/gateware/ls180.v:2192.6-2192.31" + wire \builder_csrbank8_status_w + attribute \src "build/ls180/gateware/ls180.v:2191.6-2191.32" + wire \builder_csrbank8_status_we + attribute \src "build/ls180/gateware/ls180.v:2247.12-2247.43" + wire width 8 \builder_csrbank9_clk_divider0_r + attribute \src "build/ls180/gateware/ls180.v:2246.6-2246.38" + wire \builder_csrbank9_clk_divider0_re + attribute \src "build/ls180/gateware/ls180.v:2249.12-2249.43" + wire width 8 \builder_csrbank9_clk_divider0_w + attribute \src "build/ls180/gateware/ls180.v:2248.6-2248.38" + wire \builder_csrbank9_clk_divider0_we + attribute \src "build/ls180/gateware/ls180.v:2243.12-2243.43" + wire width 8 \builder_csrbank9_clk_divider1_r + attribute \src "build/ls180/gateware/ls180.v:2242.6-2242.38" + wire \builder_csrbank9_clk_divider1_re + attribute \src "build/ls180/gateware/ls180.v:2245.12-2245.43" + wire width 8 \builder_csrbank9_clk_divider1_w + attribute \src "build/ls180/gateware/ls180.v:2244.6-2244.38" + wire \builder_csrbank9_clk_divider1_we + attribute \src "build/ls180/gateware/ls180.v:2219.12-2219.39" + wire width 8 \builder_csrbank9_control0_r + attribute \src "build/ls180/gateware/ls180.v:2218.6-2218.34" + wire \builder_csrbank9_control0_re + attribute \src "build/ls180/gateware/ls180.v:2221.12-2221.39" + wire width 8 \builder_csrbank9_control0_w + attribute \src "build/ls180/gateware/ls180.v:2220.6-2220.34" + wire \builder_csrbank9_control0_we + attribute \src "build/ls180/gateware/ls180.v:2215.12-2215.39" + wire width 8 \builder_csrbank9_control1_r + attribute \src "build/ls180/gateware/ls180.v:2214.6-2214.34" + wire \builder_csrbank9_control1_re + attribute \src "build/ls180/gateware/ls180.v:2217.12-2217.39" + wire width 8 \builder_csrbank9_control1_w + attribute \src "build/ls180/gateware/ls180.v:2216.6-2216.34" + wire \builder_csrbank9_control1_we + attribute \src "build/ls180/gateware/ls180.v:2235.6-2235.28" + wire \builder_csrbank9_cs0_r + attribute \src "build/ls180/gateware/ls180.v:2234.6-2234.29" + wire \builder_csrbank9_cs0_re + attribute \src "build/ls180/gateware/ls180.v:2237.6-2237.28" + wire \builder_csrbank9_cs0_w + attribute \src "build/ls180/gateware/ls180.v:2236.6-2236.29" + wire \builder_csrbank9_cs0_we + attribute \src "build/ls180/gateware/ls180.v:2239.6-2239.34" + wire \builder_csrbank9_loopback0_r + attribute \src "build/ls180/gateware/ls180.v:2238.6-2238.35" + wire \builder_csrbank9_loopback0_re + attribute \src "build/ls180/gateware/ls180.v:2241.6-2241.34" + wire \builder_csrbank9_loopback0_w + attribute \src "build/ls180/gateware/ls180.v:2240.6-2240.35" + wire \builder_csrbank9_loopback0_we + attribute \src "build/ls180/gateware/ls180.v:2231.12-2231.35" + wire width 8 \builder_csrbank9_miso_r + attribute \src "build/ls180/gateware/ls180.v:2230.6-2230.30" + wire \builder_csrbank9_miso_re + attribute \src "build/ls180/gateware/ls180.v:2233.12-2233.35" + wire width 8 \builder_csrbank9_miso_w + attribute \src "build/ls180/gateware/ls180.v:2232.6-2232.30" + wire \builder_csrbank9_miso_we + attribute \src "build/ls180/gateware/ls180.v:2227.12-2227.36" + wire width 8 \builder_csrbank9_mosi0_r + attribute \src "build/ls180/gateware/ls180.v:2226.6-2226.31" + wire \builder_csrbank9_mosi0_re + attribute \src "build/ls180/gateware/ls180.v:2229.12-2229.36" + wire width 8 \builder_csrbank9_mosi0_w + attribute \src "build/ls180/gateware/ls180.v:2228.6-2228.31" + wire \builder_csrbank9_mosi0_we + attribute \src "build/ls180/gateware/ls180.v:2250.6-2250.26" + wire \builder_csrbank9_sel + attribute \src "build/ls180/gateware/ls180.v:2223.6-2223.31" + wire \builder_csrbank9_status_r + attribute \src "build/ls180/gateware/ls180.v:2222.6-2222.32" + wire \builder_csrbank9_status_re + attribute \src "build/ls180/gateware/ls180.v:2225.6-2225.31" + wire \builder_csrbank9_status_w + attribute \src "build/ls180/gateware/ls180.v:2224.6-2224.32" + wire \builder_csrbank9_status_we + attribute \src "build/ls180/gateware/ls180.v:1779.6-1779.18" + wire \builder_done + attribute \src "build/ls180/gateware/ls180.v:1777.5-1777.18" + wire \builder_error + attribute \src "build/ls180/gateware/ls180.v:1774.11-1774.24" + wire width 2 \builder_grant + attribute \src "build/ls180/gateware/ls180.v:2445.6-2445.36" + wire \builder_inferedsdrtristate0__i + attribute \src "build/ls180/gateware/ls180.v:2443.5-2443.35" + wire \builder_inferedsdrtristate0__o + attribute \src "build/ls180/gateware/ls180.v:2444.5-2444.35" + wire \builder_inferedsdrtristate0_oe + attribute \src "build/ls180/gateware/ls180.v:2485.6-2485.37" + wire \builder_inferedsdrtristate10__i + attribute \src "build/ls180/gateware/ls180.v:2483.5-2483.36" + wire \builder_inferedsdrtristate10__o + attribute \src "build/ls180/gateware/ls180.v:2484.5-2484.36" + wire \builder_inferedsdrtristate10_oe + attribute \src "build/ls180/gateware/ls180.v:2489.6-2489.37" + wire \builder_inferedsdrtristate11__i + attribute \src "build/ls180/gateware/ls180.v:2487.5-2487.36" + wire \builder_inferedsdrtristate11__o + attribute \src "build/ls180/gateware/ls180.v:2488.5-2488.36" + wire \builder_inferedsdrtristate11_oe + attribute \src "build/ls180/gateware/ls180.v:2493.6-2493.37" + wire \builder_inferedsdrtristate12__i + attribute \src "build/ls180/gateware/ls180.v:2491.5-2491.36" + wire \builder_inferedsdrtristate12__o + attribute \src "build/ls180/gateware/ls180.v:2492.5-2492.36" + wire \builder_inferedsdrtristate12_oe + attribute \src "build/ls180/gateware/ls180.v:2497.6-2497.37" + wire \builder_inferedsdrtristate13__i + attribute \src "build/ls180/gateware/ls180.v:2495.5-2495.36" + wire \builder_inferedsdrtristate13__o + attribute \src "build/ls180/gateware/ls180.v:2496.5-2496.36" + wire \builder_inferedsdrtristate13_oe + attribute \src "build/ls180/gateware/ls180.v:2501.6-2501.37" + wire \builder_inferedsdrtristate14__i + attribute \src "build/ls180/gateware/ls180.v:2499.5-2499.36" + wire \builder_inferedsdrtristate14__o + attribute \src "build/ls180/gateware/ls180.v:2500.5-2500.36" + wire \builder_inferedsdrtristate14_oe + attribute \src "build/ls180/gateware/ls180.v:2505.6-2505.37" + wire \builder_inferedsdrtristate15__i + attribute \src "build/ls180/gateware/ls180.v:2503.5-2503.36" + wire \builder_inferedsdrtristate15__o + attribute \src "build/ls180/gateware/ls180.v:2504.5-2504.36" + wire \builder_inferedsdrtristate15_oe + attribute \src "build/ls180/gateware/ls180.v:2514.6-2514.37" + wire \builder_inferedsdrtristate16__i + attribute \src "build/ls180/gateware/ls180.v:2512.5-2512.36" + wire \builder_inferedsdrtristate16__o + attribute \src "build/ls180/gateware/ls180.v:2513.5-2513.36" + wire \builder_inferedsdrtristate16_oe + attribute \src "build/ls180/gateware/ls180.v:2518.6-2518.37" + wire \builder_inferedsdrtristate17__i + attribute \src "build/ls180/gateware/ls180.v:2516.5-2516.36" + wire \builder_inferedsdrtristate17__o + attribute \src "build/ls180/gateware/ls180.v:2517.5-2517.36" + wire \builder_inferedsdrtristate17_oe + attribute \src "build/ls180/gateware/ls180.v:2522.6-2522.37" + wire \builder_inferedsdrtristate18__i + attribute \src "build/ls180/gateware/ls180.v:2520.5-2520.36" + wire \builder_inferedsdrtristate18__o + attribute \src "build/ls180/gateware/ls180.v:2521.5-2521.36" + wire \builder_inferedsdrtristate18_oe + attribute \src "build/ls180/gateware/ls180.v:2526.6-2526.37" + wire \builder_inferedsdrtristate19__i + attribute \src "build/ls180/gateware/ls180.v:2524.5-2524.36" + wire \builder_inferedsdrtristate19__o + attribute \src "build/ls180/gateware/ls180.v:2525.5-2525.36" + wire \builder_inferedsdrtristate19_oe + attribute \src "build/ls180/gateware/ls180.v:2449.6-2449.36" + wire \builder_inferedsdrtristate1__i + attribute \src "build/ls180/gateware/ls180.v:2447.5-2447.35" + wire \builder_inferedsdrtristate1__o + attribute \src "build/ls180/gateware/ls180.v:2448.5-2448.35" + wire \builder_inferedsdrtristate1_oe + attribute \src "build/ls180/gateware/ls180.v:2530.6-2530.37" + wire \builder_inferedsdrtristate20__i + attribute \src "build/ls180/gateware/ls180.v:2528.5-2528.36" + wire \builder_inferedsdrtristate20__o + attribute \src "build/ls180/gateware/ls180.v:2529.5-2529.36" + wire \builder_inferedsdrtristate20_oe + attribute \src "build/ls180/gateware/ls180.v:2453.6-2453.36" + wire \builder_inferedsdrtristate2__i + attribute \src "build/ls180/gateware/ls180.v:2451.5-2451.35" + wire \builder_inferedsdrtristate2__o + attribute \src "build/ls180/gateware/ls180.v:2452.5-2452.35" + wire \builder_inferedsdrtristate2_oe + attribute \src "build/ls180/gateware/ls180.v:2457.6-2457.36" + wire \builder_inferedsdrtristate3__i + attribute \src "build/ls180/gateware/ls180.v:2455.5-2455.35" + wire \builder_inferedsdrtristate3__o + attribute \src "build/ls180/gateware/ls180.v:2456.5-2456.35" + wire \builder_inferedsdrtristate3_oe + attribute \src "build/ls180/gateware/ls180.v:2461.6-2461.36" + wire \builder_inferedsdrtristate4__i + attribute \src "build/ls180/gateware/ls180.v:2459.5-2459.35" + wire \builder_inferedsdrtristate4__o + attribute \src "build/ls180/gateware/ls180.v:2460.5-2460.35" + wire \builder_inferedsdrtristate4_oe + attribute \src "build/ls180/gateware/ls180.v:2465.6-2465.36" + wire \builder_inferedsdrtristate5__i + attribute \src "build/ls180/gateware/ls180.v:2463.5-2463.35" + wire \builder_inferedsdrtristate5__o + attribute \src "build/ls180/gateware/ls180.v:2464.5-2464.35" + wire \builder_inferedsdrtristate5_oe + attribute \src "build/ls180/gateware/ls180.v:2469.6-2469.36" + wire \builder_inferedsdrtristate6__i + attribute \src "build/ls180/gateware/ls180.v:2467.5-2467.35" + wire \builder_inferedsdrtristate6__o + attribute \src "build/ls180/gateware/ls180.v:2468.5-2468.35" + wire \builder_inferedsdrtristate6_oe + attribute \src "build/ls180/gateware/ls180.v:2473.6-2473.36" + wire \builder_inferedsdrtristate7__i + attribute \src "build/ls180/gateware/ls180.v:2471.5-2471.35" + wire \builder_inferedsdrtristate7__o + attribute \src "build/ls180/gateware/ls180.v:2472.5-2472.35" + wire \builder_inferedsdrtristate7_oe + attribute \src "build/ls180/gateware/ls180.v:2477.6-2477.36" + wire \builder_inferedsdrtristate8__i + attribute \src "build/ls180/gateware/ls180.v:2475.5-2475.35" + wire \builder_inferedsdrtristate8__o + attribute \src "build/ls180/gateware/ls180.v:2476.5-2476.35" + wire \builder_inferedsdrtristate8_oe + attribute \src "build/ls180/gateware/ls180.v:2481.6-2481.36" + wire \builder_inferedsdrtristate9__i + attribute \src "build/ls180/gateware/ls180.v:2479.5-2479.35" + wire \builder_inferedsdrtristate9__o + attribute \src "build/ls180/gateware/ls180.v:2480.5-2480.35" + wire \builder_inferedsdrtristate9_oe + attribute \src "build/ls180/gateware/ls180.v:1781.13-1781.44" + wire width 14 \builder_interface0_bank_bus_adr + attribute \src "build/ls180/gateware/ls180.v:1784.11-1784.44" + wire width 8 \builder_interface0_bank_bus_dat_r + attribute \src "build/ls180/gateware/ls180.v:1783.12-1783.45" + wire width 8 \builder_interface0_bank_bus_dat_w + attribute \src "build/ls180/gateware/ls180.v:1782.6-1782.36" + wire \builder_interface0_bank_bus_we + attribute \src "build/ls180/gateware/ls180.v:2251.13-2251.45" + wire width 14 \builder_interface10_bank_bus_adr + attribute \src "build/ls180/gateware/ls180.v:2254.11-2254.45" + wire width 8 \builder_interface10_bank_bus_dat_r + attribute \src "build/ls180/gateware/ls180.v:2253.12-2253.46" + wire width 8 \builder_interface10_bank_bus_dat_w + attribute \src "build/ls180/gateware/ls180.v:2252.6-2252.37" + wire \builder_interface10_bank_bus_we + attribute \src "build/ls180/gateware/ls180.v:2316.13-2316.45" + wire width 14 \builder_interface11_bank_bus_adr + attribute \src "build/ls180/gateware/ls180.v:2319.11-2319.45" + wire width 8 \builder_interface11_bank_bus_dat_r + attribute \src "build/ls180/gateware/ls180.v:2318.12-2318.46" + wire width 8 \builder_interface11_bank_bus_dat_w + attribute \src "build/ls180/gateware/ls180.v:2317.6-2317.37" + wire \builder_interface11_bank_bus_we + attribute \src "build/ls180/gateware/ls180.v:2341.13-2341.45" + wire width 14 \builder_interface12_bank_bus_adr + attribute \src "build/ls180/gateware/ls180.v:2344.11-2344.45" + wire width 8 \builder_interface12_bank_bus_dat_r + attribute \src "build/ls180/gateware/ls180.v:2343.12-2343.46" + wire width 8 \builder_interface12_bank_bus_dat_w + attribute \src "build/ls180/gateware/ls180.v:2342.6-2342.37" + wire \builder_interface12_bank_bus_we + attribute \src "build/ls180/gateware/ls180.v:1822.13-1822.44" + wire width 14 \builder_interface1_bank_bus_adr + attribute \src "build/ls180/gateware/ls180.v:1825.11-1825.44" + wire width 8 \builder_interface1_bank_bus_dat_r + attribute \src "build/ls180/gateware/ls180.v:1824.12-1824.45" + wire width 8 \builder_interface1_bank_bus_dat_w + attribute \src "build/ls180/gateware/ls180.v:1823.6-1823.36" + wire \builder_interface1_bank_bus_we + attribute \src "build/ls180/gateware/ls180.v:1831.13-1831.44" + wire width 14 \builder_interface2_bank_bus_adr + attribute \src "build/ls180/gateware/ls180.v:1834.11-1834.44" + wire width 8 \builder_interface2_bank_bus_dat_r + attribute \src "build/ls180/gateware/ls180.v:1833.12-1833.45" + wire width 8 \builder_interface2_bank_bus_dat_w + attribute \src "build/ls180/gateware/ls180.v:1832.6-1832.36" + wire \builder_interface2_bank_bus_we + attribute \src "build/ls180/gateware/ls180.v:1840.13-1840.44" + wire width 14 \builder_interface3_bank_bus_adr + attribute \src "build/ls180/gateware/ls180.v:1843.11-1843.44" + wire width 8 \builder_interface3_bank_bus_dat_r + attribute \src "build/ls180/gateware/ls180.v:1842.12-1842.45" + wire width 8 \builder_interface3_bank_bus_dat_w + attribute \src "build/ls180/gateware/ls180.v:1841.6-1841.36" + wire \builder_interface3_bank_bus_we + attribute \src "build/ls180/gateware/ls180.v:1905.13-1905.44" + wire width 14 \builder_interface4_bank_bus_adr + attribute \src "build/ls180/gateware/ls180.v:1908.11-1908.44" + wire width 8 \builder_interface4_bank_bus_dat_r + attribute \src "build/ls180/gateware/ls180.v:1907.12-1907.45" + wire width 8 \builder_interface4_bank_bus_dat_w + attribute \src "build/ls180/gateware/ls180.v:1906.6-1906.36" + wire \builder_interface4_bank_bus_we + attribute \src "build/ls180/gateware/ls180.v:2038.13-2038.44" + wire width 14 \builder_interface5_bank_bus_adr + attribute \src "build/ls180/gateware/ls180.v:2041.11-2041.44" + wire width 8 \builder_interface5_bank_bus_dat_r + attribute \src "build/ls180/gateware/ls180.v:2040.12-2040.45" + wire width 8 \builder_interface5_bank_bus_dat_w + attribute \src "build/ls180/gateware/ls180.v:2039.6-2039.36" + wire \builder_interface5_bank_bus_we + attribute \src "build/ls180/gateware/ls180.v:2119.13-2119.44" + wire width 14 \builder_interface6_bank_bus_adr + attribute \src "build/ls180/gateware/ls180.v:2122.11-2122.44" + wire width 8 \builder_interface6_bank_bus_dat_r + attribute \src "build/ls180/gateware/ls180.v:2121.12-2121.45" + wire width 8 \builder_interface6_bank_bus_dat_w + attribute \src "build/ls180/gateware/ls180.v:2120.6-2120.36" + wire \builder_interface6_bank_bus_we + attribute \src "build/ls180/gateware/ls180.v:2136.13-2136.44" + wire width 14 \builder_interface7_bank_bus_adr + attribute \src "build/ls180/gateware/ls180.v:2139.11-2139.44" + wire width 8 \builder_interface7_bank_bus_dat_r + attribute \src "build/ls180/gateware/ls180.v:2138.12-2138.45" + wire width 8 \builder_interface7_bank_bus_dat_w + attribute \src "build/ls180/gateware/ls180.v:2137.6-2137.36" + wire \builder_interface7_bank_bus_we + attribute \src "build/ls180/gateware/ls180.v:2177.13-2177.44" + wire width 14 \builder_interface8_bank_bus_adr + attribute \src "build/ls180/gateware/ls180.v:2180.11-2180.44" + wire width 8 \builder_interface8_bank_bus_dat_r + attribute \src "build/ls180/gateware/ls180.v:2179.12-2179.45" + wire width 8 \builder_interface8_bank_bus_dat_w + attribute \src "build/ls180/gateware/ls180.v:2178.6-2178.36" + wire \builder_interface8_bank_bus_we + attribute \src "build/ls180/gateware/ls180.v:2210.13-2210.44" + wire width 14 \builder_interface9_bank_bus_adr + attribute \src "build/ls180/gateware/ls180.v:2213.11-2213.44" + wire width 8 \builder_interface9_bank_bus_dat_r + attribute \src "build/ls180/gateware/ls180.v:2212.12-2212.45" + wire width 8 \builder_interface9_bank_bus_dat_w + attribute \src "build/ls180/gateware/ls180.v:2211.6-2211.36" + wire \builder_interface9_bank_bus_we + attribute \src "build/ls180/gateware/ls180.v:1747.12-1747.35" + wire width 14 \builder_libresocsim_adr + attribute \src "build/ls180/gateware/ls180.v:2370.12-2370.47" + wire width 14 \builder_libresocsim_adr_next_value1 + attribute \src "build/ls180/gateware/ls180.v:2371.5-2371.43" + wire \builder_libresocsim_adr_next_value_ce1 + attribute \src "build/ls180/gateware/ls180.v:1750.12-1750.37" + wire width 8 \builder_libresocsim_dat_r + attribute \src "build/ls180/gateware/ls180.v:1749.11-1749.36" + wire width 8 \builder_libresocsim_dat_w + attribute \src "build/ls180/gateware/ls180.v:2368.11-2368.48" + wire width 8 \builder_libresocsim_dat_w_next_value0 + attribute \src "build/ls180/gateware/ls180.v:2369.5-2369.45" + wire \builder_libresocsim_dat_w_next_value_ce0 + attribute \src "build/ls180/gateware/ls180.v:1748.5-1748.27" + wire \builder_libresocsim_we + attribute \src "build/ls180/gateware/ls180.v:2372.5-2372.39" + wire \builder_libresocsim_we_next_value2 + attribute \src "build/ls180/gateware/ls180.v:2373.5-2373.42" + wire \builder_libresocsim_we_next_value_ce2 + attribute \src "build/ls180/gateware/ls180.v:1757.5-1757.37" + wire \builder_libresocsim_wishbone_ack + attribute \src "build/ls180/gateware/ls180.v:1751.13-1751.45" + wire width 30 \builder_libresocsim_wishbone_adr + attribute \src "build/ls180/gateware/ls180.v:1760.12-1760.44" + wire width 2 \builder_libresocsim_wishbone_bte + attribute \src "build/ls180/gateware/ls180.v:1759.12-1759.44" + wire width 3 \builder_libresocsim_wishbone_cti + attribute \src "build/ls180/gateware/ls180.v:1755.6-1755.38" + wire \builder_libresocsim_wishbone_cyc + attribute \src "build/ls180/gateware/ls180.v:1753.12-1753.46" + wire width 32 \builder_libresocsim_wishbone_dat_r + attribute \src "build/ls180/gateware/ls180.v:1752.13-1752.47" + wire width 32 \builder_libresocsim_wishbone_dat_w + attribute \src "build/ls180/gateware/ls180.v:1761.5-1761.37" + wire \builder_libresocsim_wishbone_err + attribute \src "build/ls180/gateware/ls180.v:1754.12-1754.44" + wire width 4 \builder_libresocsim_wishbone_sel + attribute \src "build/ls180/gateware/ls180.v:1756.6-1756.38" + wire \builder_libresocsim_wishbone_stb + attribute \src "build/ls180/gateware/ls180.v:1758.6-1758.37" + wire \builder_libresocsim_wishbone_we + attribute \src "build/ls180/gateware/ls180.v:1650.5-1650.20" + wire \builder_locked0 + attribute \src "build/ls180/gateware/ls180.v:1651.5-1651.20" + wire \builder_locked1 + attribute \src "build/ls180/gateware/ls180.v:1652.5-1652.20" + wire \builder_locked2 + attribute \src "build/ls180/gateware/ls180.v:1653.5-1653.20" + wire \builder_locked3 + attribute \src "build/ls180/gateware/ls180.v:1637.11-1637.41" + wire width 3 \builder_multiplexer_next_state + attribute \src "build/ls180/gateware/ls180.v:1636.11-1636.36" + wire width 3 \builder_multiplexer_state + attribute \no_retiming "true" + attribute \src "build/ls180/gateware/ls180.v:2421.32-2421.59" + wire \builder_multiregimpl0_regs0 + attribute \no_retiming "true" + attribute \src "build/ls180/gateware/ls180.v:2422.32-2422.59" + wire \builder_multiregimpl0_regs1 + attribute \no_retiming "true" + attribute \src "build/ls180/gateware/ls180.v:2507.38-2507.65" + wire width 8 \builder_multiregimpl1_regs0 + attribute \no_retiming "true" + attribute \src "build/ls180/gateware/ls180.v:2508.38-2508.65" + wire width 8 \builder_multiregimpl1_regs1 + attribute \no_retiming "true" + attribute \src "build/ls180/gateware/ls180.v:2509.38-2509.65" + wire width 8 \builder_multiregimpl2_regs0 + attribute \no_retiming "true" + attribute \src "build/ls180/gateware/ls180.v:2510.38-2510.65" + wire width 8 \builder_multiregimpl2_regs1 + attribute \src "build/ls180/gateware/ls180.v:1655.5-1655.36" + wire \builder_new_master_rdata_valid0 + attribute \src "build/ls180/gateware/ls180.v:1656.5-1656.36" + wire \builder_new_master_rdata_valid1 + attribute \src "build/ls180/gateware/ls180.v:1657.5-1657.36" + wire \builder_new_master_rdata_valid2 + attribute \src "build/ls180/gateware/ls180.v:1658.5-1658.36" + wire \builder_new_master_rdata_valid3 + attribute \src "build/ls180/gateware/ls180.v:1654.5-1654.35" + wire \builder_new_master_wdata_ready + attribute \src "build/ls180/gateware/ls180.v:2367.11-2367.29" + wire width 2 \builder_next_state + attribute \src "build/ls180/gateware/ls180.v:1627.11-1627.39" + wire width 2 \builder_refresher_next_state + attribute \src "build/ls180/gateware/ls180.v:1626.11-1626.34" + wire width 2 \builder_refresher_state + attribute \src "build/ls180/gateware/ls180.v:1773.12-1773.27" + wire width 4 \builder_request + attribute \src "build/ls180/gateware/ls180.v:1640.6-1640.28" + wire \builder_roundrobin0_ce + attribute \src "build/ls180/gateware/ls180.v:1639.6-1639.31" + wire \builder_roundrobin0_grant + attribute \src "build/ls180/gateware/ls180.v:1638.6-1638.33" + wire \builder_roundrobin0_request + attribute \src "build/ls180/gateware/ls180.v:1643.6-1643.28" + wire \builder_roundrobin1_ce + attribute \src "build/ls180/gateware/ls180.v:1642.6-1642.31" + wire \builder_roundrobin1_grant + attribute \src "build/ls180/gateware/ls180.v:1641.6-1641.33" + wire \builder_roundrobin1_request + attribute \src "build/ls180/gateware/ls180.v:1646.6-1646.28" + wire \builder_roundrobin2_ce + attribute \src "build/ls180/gateware/ls180.v:1645.6-1645.31" + wire \builder_roundrobin2_grant + attribute \src "build/ls180/gateware/ls180.v:1644.6-1644.33" + wire \builder_roundrobin2_request + attribute \src "build/ls180/gateware/ls180.v:1649.6-1649.28" + wire \builder_roundrobin3_ce + attribute \src "build/ls180/gateware/ls180.v:1648.6-1648.31" + wire \builder_roundrobin3_grant + attribute \src "build/ls180/gateware/ls180.v:1647.6-1647.33" + wire \builder_roundrobin3_request + attribute \src "build/ls180/gateware/ls180.v:1732.11-1732.44" + wire width 2 \builder_sdblock2memdma_next_state + attribute \src "build/ls180/gateware/ls180.v:1731.11-1731.39" + wire width 2 \builder_sdblock2memdma_state + attribute \src "build/ls180/gateware/ls180.v:1700.5-1700.50" + wire \builder_sdcore_crcupstreaminserter_next_state + attribute \src "build/ls180/gateware/ls180.v:1699.5-1699.45" + wire \builder_sdcore_crcupstreaminserter_state + attribute \src "build/ls180/gateware/ls180.v:1712.11-1712.40" + wire width 3 \builder_sdcore_fsm_next_state + attribute \src "build/ls180/gateware/ls180.v:1711.11-1711.35" + wire width 3 \builder_sdcore_fsm_state + attribute \src "build/ls180/gateware/ls180.v:1736.5-1736.42" + wire \builder_sdmem2blockdma_fsm_next_state + attribute \src "build/ls180/gateware/ls180.v:1735.5-1735.37" + wire \builder_sdmem2blockdma_fsm_state + attribute \src "build/ls180/gateware/ls180.v:1740.11-1740.58" + wire width 2 \builder_sdmem2blockdma_resetinserter_next_state + attribute \src "build/ls180/gateware/ls180.v:1739.11-1739.53" + wire width 2 \builder_sdmem2blockdma_resetinserter_state + attribute \src "build/ls180/gateware/ls180.v:1688.11-1688.39" + wire width 3 \builder_sdphy_fsm_next_state + attribute \src "build/ls180/gateware/ls180.v:1687.11-1687.34" + wire width 3 \builder_sdphy_fsm_state + attribute \src "build/ls180/gateware/ls180.v:1676.11-1676.45" + wire width 3 \builder_sdphy_sdphycmdr_next_state + attribute \src "build/ls180/gateware/ls180.v:1675.11-1675.40" + wire width 3 \builder_sdphy_sdphycmdr_state + attribute \src "build/ls180/gateware/ls180.v:1672.11-1672.45" + wire width 2 \builder_sdphy_sdphycmdw_next_state + attribute \src "build/ls180/gateware/ls180.v:1671.11-1671.40" + wire width 2 \builder_sdphy_sdphycmdw_state + attribute \src "build/ls180/gateware/ls180.v:1684.5-1684.39" + wire \builder_sdphy_sdphycrcr_next_state + attribute \src "build/ls180/gateware/ls180.v:1683.5-1683.34" + wire \builder_sdphy_sdphycrcr_state + attribute \src "build/ls180/gateware/ls180.v:1692.11-1692.46" + wire width 3 \builder_sdphy_sdphydatar_next_state + attribute \src "build/ls180/gateware/ls180.v:1691.11-1691.41" + wire width 3 \builder_sdphy_sdphydatar_state + attribute \src "build/ls180/gateware/ls180.v:1668.5-1668.39" + wire \builder_sdphy_sdphyinit_next_state + attribute \src "build/ls180/gateware/ls180.v:1667.5-1667.34" + wire \builder_sdphy_sdphyinit_state + attribute \src "build/ls180/gateware/ls180.v:1768.5-1768.23" + wire \builder_shared_ack + attribute \src "build/ls180/gateware/ls180.v:1762.13-1762.31" + wire width 30 \builder_shared_adr + attribute \src "build/ls180/gateware/ls180.v:1771.12-1771.30" + wire width 2 \builder_shared_bte + attribute \src "build/ls180/gateware/ls180.v:1770.12-1770.30" + wire width 3 \builder_shared_cti + attribute \src "build/ls180/gateware/ls180.v:1766.6-1766.24" + wire \builder_shared_cyc + attribute \src "build/ls180/gateware/ls180.v:1764.12-1764.32" + wire width 32 \builder_shared_dat_r + attribute \src "build/ls180/gateware/ls180.v:1763.13-1763.33" + wire width 32 \builder_shared_dat_w + attribute \src "build/ls180/gateware/ls180.v:1772.6-1772.24" + wire \builder_shared_err + attribute \src "build/ls180/gateware/ls180.v:1765.12-1765.30" + wire width 4 \builder_shared_sel + attribute \src "build/ls180/gateware/ls180.v:1767.6-1767.24" + wire \builder_shared_stb + attribute \src "build/ls180/gateware/ls180.v:1769.6-1769.23" + wire \builder_shared_we + attribute \src "build/ls180/gateware/ls180.v:1775.11-1775.28" + wire width 5 \builder_slave_sel + attribute \src "build/ls180/gateware/ls180.v:1776.11-1776.30" + wire width 5 \builder_slave_sel_r + attribute \src "build/ls180/gateware/ls180.v:1664.11-1664.40" + wire width 2 \builder_spimaster0_next_state + attribute \src "build/ls180/gateware/ls180.v:1663.11-1663.35" + wire width 2 \builder_spimaster0_state + attribute \src "build/ls180/gateware/ls180.v:1744.11-1744.40" + wire width 2 \builder_spimaster1_next_state + attribute \src "build/ls180/gateware/ls180.v:1743.11-1743.35" + wire width 2 \builder_spimaster1_state + attribute \src "build/ls180/gateware/ls180.v:2366.11-2366.24" + wire width 2 \builder_state + attribute \src "build/ls180/gateware/ls180.v:2419.5-2419.32" + wire \builder_sync_f_array_muxed0 + attribute \src "build/ls180/gateware/ls180.v:2420.5-2420.32" + wire \builder_sync_f_array_muxed1 + attribute \src "build/ls180/gateware/ls180.v:2412.11-2412.40" + wire width 2 \builder_sync_rhs_array_muxed0 + attribute \src "build/ls180/gateware/ls180.v:2413.12-2413.41" + wire width 13 \builder_sync_rhs_array_muxed1 + attribute \src "build/ls180/gateware/ls180.v:2414.5-2414.34" + wire \builder_sync_rhs_array_muxed2 + attribute \src "build/ls180/gateware/ls180.v:2415.5-2415.34" + wire \builder_sync_rhs_array_muxed3 + attribute \src "build/ls180/gateware/ls180.v:2416.5-2416.34" + wire \builder_sync_rhs_array_muxed4 + attribute \src "build/ls180/gateware/ls180.v:2417.5-2417.34" + wire \builder_sync_rhs_array_muxed5 + attribute \src "build/ls180/gateware/ls180.v:2418.5-2418.34" + wire \builder_sync_rhs_array_muxed6 + attribute \src "build/ls180/gateware/ls180.v:1778.6-1778.18" + wire \builder_wait + attribute \src "build/ls180/gateware/ls180.v:23.19-23.23" + wire width 3 input 19 \eint + attribute \src "build/ls180/gateware/ls180.v:17.19-17.26" + wire width 8 input 13 \gpio_in + attribute \src "build/ls180/gateware/ls180.v:18.19-18.27" + wire width 8 input 14 \gpio_out + attribute \src "build/ls180/gateware/ls180.v:1588.13-1588.37" + wire width 16 \libresocsim_clk_divider0 + attribute \src "build/ls180/gateware/ls180.v:1610.12-1610.36" + wire width 16 \libresocsim_clk_divider1 + attribute \src "build/ls180/gateware/ls180.v:1605.5-1605.27" + wire \libresocsim_clk_enable + attribute \src "build/ls180/gateware/ls180.v:1612.6-1612.26" + wire \libresocsim_clk_fall + attribute \src "build/ls180/gateware/ls180.v:1611.6-1611.26" + wire \libresocsim_clk_rise + attribute \src "build/ls180/gateware/ls180.v:948.6-948.28" + wire \libresocsim_clocker_ce + attribute \src "build/ls180/gateware/ls180.v:947.5-947.29" + wire \libresocsim_clocker_clk0 + attribute \src "build/ls180/gateware/ls180.v:950.5-950.29" + wire \libresocsim_clocker_clk1 + attribute \src "build/ls180/gateware/ls180.v:951.5-951.30" + wire \libresocsim_clocker_clk_d + attribute \src "build/ls180/gateware/ls180.v:949.11-949.35" + wire width 9 \libresocsim_clocker_clks + attribute \src "build/ls180/gateware/ls180.v:945.5-945.27" + wire \libresocsim_clocker_re + attribute \src "build/ls180/gateware/ls180.v:946.6-946.30" + wire \libresocsim_clocker_stop + attribute \src "build/ls180/gateware/ls180.v:944.11-944.38" + wire width 9 \libresocsim_clocker_storage + attribute \src "build/ls180/gateware/ls180.v:1048.6-1048.42" + wire \libresocsim_cmdr_cmdr_buf_sink_first + attribute \src "build/ls180/gateware/ls180.v:1049.6-1049.41" + wire \libresocsim_cmdr_cmdr_buf_sink_last + attribute \src "build/ls180/gateware/ls180.v:1050.12-1050.55" + wire width 8 \libresocsim_cmdr_cmdr_buf_sink_payload_data + attribute \src "build/ls180/gateware/ls180.v:1047.6-1047.42" + wire \libresocsim_cmdr_cmdr_buf_sink_ready + attribute \src "build/ls180/gateware/ls180.v:1046.6-1046.42" + wire \libresocsim_cmdr_cmdr_buf_sink_valid + attribute \src "build/ls180/gateware/ls180.v:1053.5-1053.43" + wire \libresocsim_cmdr_cmdr_buf_source_first + attribute \src "build/ls180/gateware/ls180.v:1054.5-1054.42" + wire \libresocsim_cmdr_cmdr_buf_source_last + attribute \src "build/ls180/gateware/ls180.v:1055.11-1055.56" + wire width 8 \libresocsim_cmdr_cmdr_buf_source_payload_data + attribute \src "build/ls180/gateware/ls180.v:1052.6-1052.44" + wire \libresocsim_cmdr_cmdr_buf_source_ready + attribute \src "build/ls180/gateware/ls180.v:1051.5-1051.43" + wire \libresocsim_cmdr_cmdr_buf_source_valid + attribute \src "build/ls180/gateware/ls180.v:1038.11-1038.48" + wire width 3 \libresocsim_cmdr_cmdr_converter_demux + attribute \src "build/ls180/gateware/ls180.v:1039.6-1039.47" + wire \libresocsim_cmdr_cmdr_converter_load_part + attribute \src "build/ls180/gateware/ls180.v:1029.5-1029.47" + wire \libresocsim_cmdr_cmdr_converter_sink_first + attribute \src "build/ls180/gateware/ls180.v:1030.5-1030.46" + wire \libresocsim_cmdr_cmdr_converter_sink_last + attribute \src "build/ls180/gateware/ls180.v:1031.6-1031.55" + wire \libresocsim_cmdr_cmdr_converter_sink_payload_data + attribute \src "build/ls180/gateware/ls180.v:1028.6-1028.48" + wire \libresocsim_cmdr_cmdr_converter_sink_ready + attribute \src "build/ls180/gateware/ls180.v:1027.6-1027.48" + wire \libresocsim_cmdr_cmdr_converter_sink_valid + attribute \src "build/ls180/gateware/ls180.v:1034.5-1034.49" + wire \libresocsim_cmdr_cmdr_converter_source_first + attribute \src "build/ls180/gateware/ls180.v:1035.5-1035.48" + wire \libresocsim_cmdr_cmdr_converter_source_last + attribute \src "build/ls180/gateware/ls180.v:1036.11-1036.62" + wire width 8 \libresocsim_cmdr_cmdr_converter_source_payload_data + attribute \src "build/ls180/gateware/ls180.v:1037.11-1037.75" + wire width 4 \libresocsim_cmdr_cmdr_converter_source_payload_valid_token_count + attribute \src "build/ls180/gateware/ls180.v:1033.6-1033.50" + wire \libresocsim_cmdr_cmdr_converter_source_ready + attribute \src "build/ls180/gateware/ls180.v:1032.6-1032.50" + wire \libresocsim_cmdr_cmdr_converter_source_valid + attribute \src "build/ls180/gateware/ls180.v:1040.5-1040.47" + wire \libresocsim_cmdr_cmdr_converter_strobe_all + attribute \src "build/ls180/gateware/ls180.v:1011.6-1011.41" + wire \libresocsim_cmdr_cmdr_pads_in_first + attribute \src "build/ls180/gateware/ls180.v:1012.6-1012.40" + wire \libresocsim_cmdr_cmdr_pads_in_last + attribute \src "build/ls180/gateware/ls180.v:1013.6-1013.47" + wire \libresocsim_cmdr_cmdr_pads_in_payload_clk + attribute \src "build/ls180/gateware/ls180.v:1014.6-1014.49" + wire \libresocsim_cmdr_cmdr_pads_in_payload_cmd_i + attribute \src "build/ls180/gateware/ls180.v:1015.6-1015.49" + wire \libresocsim_cmdr_cmdr_pads_in_payload_cmd_o + attribute \src "build/ls180/gateware/ls180.v:1016.6-1016.50" + wire \libresocsim_cmdr_cmdr_pads_in_payload_cmd_oe + attribute \src "build/ls180/gateware/ls180.v:1017.12-1017.56" + wire width 4 \libresocsim_cmdr_cmdr_pads_in_payload_data_i + attribute \src "build/ls180/gateware/ls180.v:1018.12-1018.56" + wire width 4 \libresocsim_cmdr_cmdr_pads_in_payload_data_o + attribute \src "build/ls180/gateware/ls180.v:1019.6-1019.51" + wire \libresocsim_cmdr_cmdr_pads_in_payload_data_oe + attribute \src "build/ls180/gateware/ls180.v:1010.5-1010.40" + wire \libresocsim_cmdr_cmdr_pads_in_ready + attribute \src "build/ls180/gateware/ls180.v:1009.6-1009.41" + wire \libresocsim_cmdr_cmdr_pads_in_valid + attribute \src "build/ls180/gateware/ls180.v:1056.5-1056.32" + wire \libresocsim_cmdr_cmdr_reset + attribute \src "build/ls180/gateware/ls180.v:1681.5-1681.60" + wire \libresocsim_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value2 + attribute \src "build/ls180/gateware/ls180.v:1682.5-1682.63" + wire \libresocsim_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value_ce2 + attribute \src "build/ls180/gateware/ls180.v:1026.5-1026.30" + wire \libresocsim_cmdr_cmdr_run + attribute \src "build/ls180/gateware/ls180.v:1022.6-1022.48" + wire \libresocsim_cmdr_cmdr_source_source_first0 + attribute \src "build/ls180/gateware/ls180.v:1043.6-1043.48" + wire \libresocsim_cmdr_cmdr_source_source_first1 + attribute \src "build/ls180/gateware/ls180.v:1023.6-1023.47" + wire \libresocsim_cmdr_cmdr_source_source_last0 + attribute \src "build/ls180/gateware/ls180.v:1044.6-1044.47" + wire \libresocsim_cmdr_cmdr_source_source_last1 + attribute \src "build/ls180/gateware/ls180.v:1024.12-1024.61" + wire width 8 \libresocsim_cmdr_cmdr_source_source_payload_data0 + attribute \src "build/ls180/gateware/ls180.v:1045.12-1045.61" + wire width 8 \libresocsim_cmdr_cmdr_source_source_payload_data1 + attribute \src "build/ls180/gateware/ls180.v:1021.5-1021.47" + wire \libresocsim_cmdr_cmdr_source_source_ready0 + attribute \src "build/ls180/gateware/ls180.v:1042.6-1042.48" + wire \libresocsim_cmdr_cmdr_source_source_ready1 + attribute \src "build/ls180/gateware/ls180.v:1020.6-1020.48" + wire \libresocsim_cmdr_cmdr_source_source_valid0 + attribute \src "build/ls180/gateware/ls180.v:1041.6-1041.48" + wire \libresocsim_cmdr_cmdr_source_source_valid1 + attribute \src "build/ls180/gateware/ls180.v:1025.6-1025.33" + wire \libresocsim_cmdr_cmdr_start + attribute \src "build/ls180/gateware/ls180.v:1008.11-1008.33" + wire width 8 \libresocsim_cmdr_count + attribute \src "build/ls180/gateware/ls180.v:1677.11-1677.61" + wire width 8 \libresocsim_cmdr_count_sdphy_sdphycmdr_next_value0 + attribute \src "build/ls180/gateware/ls180.v:1678.5-1678.58" + wire \libresocsim_cmdr_count_sdphy_sdphycmdr_next_value_ce0 + attribute \src "build/ls180/gateware/ls180.v:983.5-983.43" + wire \libresocsim_cmdr_pads_in_pads_in_first + attribute \src "build/ls180/gateware/ls180.v:984.5-984.42" + wire \libresocsim_cmdr_pads_in_pads_in_last + attribute \src "build/ls180/gateware/ls180.v:985.5-985.49" + wire \libresocsim_cmdr_pads_in_pads_in_payload_clk + attribute \src "build/ls180/gateware/ls180.v:986.6-986.52" + wire \libresocsim_cmdr_pads_in_pads_in_payload_cmd_i + attribute \src "build/ls180/gateware/ls180.v:987.5-987.51" + wire \libresocsim_cmdr_pads_in_pads_in_payload_cmd_o + attribute \src "build/ls180/gateware/ls180.v:988.5-988.52" + wire \libresocsim_cmdr_pads_in_pads_in_payload_cmd_oe + attribute \src "build/ls180/gateware/ls180.v:989.12-989.59" + wire width 4 \libresocsim_cmdr_pads_in_pads_in_payload_data_i + attribute \src "build/ls180/gateware/ls180.v:990.11-990.58" + wire width 4 \libresocsim_cmdr_pads_in_pads_in_payload_data_o + attribute \src "build/ls180/gateware/ls180.v:991.5-991.53" + wire \libresocsim_cmdr_pads_in_pads_in_payload_data_oe + attribute \src "build/ls180/gateware/ls180.v:982.6-982.44" + wire \libresocsim_cmdr_pads_in_pads_in_ready + attribute \src "build/ls180/gateware/ls180.v:981.6-981.44" + wire \libresocsim_cmdr_pads_in_pads_in_valid + attribute \src "build/ls180/gateware/ls180.v:993.5-993.42" + wire \libresocsim_cmdr_pads_out_payload_clk + attribute \src "build/ls180/gateware/ls180.v:994.5-994.44" + wire \libresocsim_cmdr_pads_out_payload_cmd_o + attribute \src "build/ls180/gateware/ls180.v:995.5-995.45" + wire \libresocsim_cmdr_pads_out_payload_cmd_oe + attribute \src "build/ls180/gateware/ls180.v:996.11-996.51" + wire width 4 \libresocsim_cmdr_pads_out_payload_data_o + attribute \src "build/ls180/gateware/ls180.v:997.5-997.46" + wire \libresocsim_cmdr_pads_out_payload_data_oe + attribute \src "build/ls180/gateware/ls180.v:992.6-992.37" + wire \libresocsim_cmdr_pads_out_ready + attribute \src "build/ls180/gateware/ls180.v:1000.5-1000.31" + wire \libresocsim_cmdr_sink_last + attribute \src "build/ls180/gateware/ls180.v:1001.11-1001.47" + wire width 8 \libresocsim_cmdr_sink_payload_length + attribute \src "build/ls180/gateware/ls180.v:999.5-999.32" + wire \libresocsim_cmdr_sink_ready + attribute \src "build/ls180/gateware/ls180.v:998.5-998.32" + wire \libresocsim_cmdr_sink_valid + attribute \src "build/ls180/gateware/ls180.v:1004.5-1004.33" + wire \libresocsim_cmdr_source_last + attribute \src "build/ls180/gateware/ls180.v:1005.11-1005.47" + wire width 8 \libresocsim_cmdr_source_payload_data + attribute \src "build/ls180/gateware/ls180.v:1006.11-1006.49" + wire width 3 \libresocsim_cmdr_source_payload_status + attribute \src "build/ls180/gateware/ls180.v:1003.5-1003.34" + wire \libresocsim_cmdr_source_ready + attribute \src "build/ls180/gateware/ls180.v:1002.5-1002.34" + wire \libresocsim_cmdr_source_valid + attribute \src "build/ls180/gateware/ls180.v:1007.12-1007.36" + wire width 32 \libresocsim_cmdr_timeout + attribute \src "build/ls180/gateware/ls180.v:1679.12-1679.64" + wire width 32 \libresocsim_cmdr_timeout_sdphy_sdphycmdr_next_value1 + attribute \src "build/ls180/gateware/ls180.v:1680.5-1680.60" + wire \libresocsim_cmdr_timeout_sdphy_sdphycmdr_next_value_ce1 + attribute \src "build/ls180/gateware/ls180.v:980.11-980.33" + wire width 8 \libresocsim_cmdw_count + attribute \src "build/ls180/gateware/ls180.v:1673.11-1673.60" + wire width 8 \libresocsim_cmdw_count_sdphy_sdphycmdw_next_value + attribute \src "build/ls180/gateware/ls180.v:1674.5-1674.57" + wire \libresocsim_cmdw_count_sdphy_sdphycmdw_next_value_ce + attribute \src "build/ls180/gateware/ls180.v:979.5-979.26" + wire \libresocsim_cmdw_done + attribute \src "build/ls180/gateware/ls180.v:967.6-967.44" + wire \libresocsim_cmdw_pads_in_payload_cmd_i + attribute \src "build/ls180/gateware/ls180.v:968.12-968.51" + wire width 4 \libresocsim_cmdw_pads_in_payload_data_i + attribute \src "build/ls180/gateware/ls180.v:966.6-966.36" + wire \libresocsim_cmdw_pads_in_valid + attribute \src "build/ls180/gateware/ls180.v:970.5-970.42" + wire \libresocsim_cmdw_pads_out_payload_clk + attribute \src "build/ls180/gateware/ls180.v:971.5-971.44" + wire \libresocsim_cmdw_pads_out_payload_cmd_o + attribute \src "build/ls180/gateware/ls180.v:972.5-972.45" + wire \libresocsim_cmdw_pads_out_payload_cmd_oe + attribute \src "build/ls180/gateware/ls180.v:973.11-973.51" + wire width 4 \libresocsim_cmdw_pads_out_payload_data_o + attribute \src "build/ls180/gateware/ls180.v:974.5-974.46" + wire \libresocsim_cmdw_pads_out_payload_data_oe + attribute \src "build/ls180/gateware/ls180.v:969.6-969.37" + wire \libresocsim_cmdw_pads_out_ready + attribute \src "build/ls180/gateware/ls180.v:977.5-977.31" + wire \libresocsim_cmdw_sink_last + attribute \src "build/ls180/gateware/ls180.v:978.11-978.45" + wire width 8 \libresocsim_cmdw_sink_payload_data + attribute \src "build/ls180/gateware/ls180.v:976.5-976.32" + wire \libresocsim_cmdw_sink_ready + attribute \src "build/ls180/gateware/ls180.v:975.5-975.32" + wire \libresocsim_cmdw_sink_valid + attribute \src "build/ls180/gateware/ls180.v:1592.5-1592.27" + wire \libresocsim_control_re + attribute \src "build/ls180/gateware/ls180.v:1591.12-1591.39" + wire width 16 \libresocsim_control_storage + attribute \src "build/ls180/gateware/ls180.v:1607.11-1607.28" + wire width 3 \libresocsim_count + attribute \src "build/ls180/gateware/ls180.v:1745.11-1745.50" + wire width 3 \libresocsim_count_spimaster1_next_value + attribute \src "build/ls180/gateware/ls180.v:1746.5-1746.47" + wire \libresocsim_count_spimaster1_next_value_ce + attribute \src "build/ls180/gateware/ls180.v:1586.6-1586.20" + wire \libresocsim_cs + attribute \src "build/ls180/gateware/ls180.v:1606.5-1606.26" + wire \libresocsim_cs_enable + attribute \src "build/ls180/gateware/ls180.v:1602.5-1602.22" + wire \libresocsim_cs_re + attribute \src "build/ls180/gateware/ls180.v:1601.5-1601.27" + wire \libresocsim_cs_storage + attribute \src "build/ls180/gateware/ls180.v:1164.11-1164.34" + wire width 10 \libresocsim_datar_count + attribute \src "build/ls180/gateware/ls180.v:1693.11-1693.63" + wire width 10 \libresocsim_datar_count_sdphy_sdphydatar_next_value0 + attribute \src "build/ls180/gateware/ls180.v:1694.5-1694.60" + wire \libresocsim_datar_count_sdphy_sdphydatar_next_value_ce0 + attribute \src "build/ls180/gateware/ls180.v:1204.6-1204.44" + wire \libresocsim_datar_datar_buf_sink_first + attribute \src "build/ls180/gateware/ls180.v:1205.6-1205.43" + wire \libresocsim_datar_datar_buf_sink_last + attribute \src "build/ls180/gateware/ls180.v:1206.12-1206.57" + wire width 8 \libresocsim_datar_datar_buf_sink_payload_data + attribute \src "build/ls180/gateware/ls180.v:1203.6-1203.44" + wire \libresocsim_datar_datar_buf_sink_ready + attribute \src "build/ls180/gateware/ls180.v:1202.6-1202.44" + wire \libresocsim_datar_datar_buf_sink_valid + attribute \src "build/ls180/gateware/ls180.v:1209.5-1209.45" + wire \libresocsim_datar_datar_buf_source_first + attribute \src "build/ls180/gateware/ls180.v:1210.5-1210.44" + wire \libresocsim_datar_datar_buf_source_last + attribute \src "build/ls180/gateware/ls180.v:1211.11-1211.58" + wire width 8 \libresocsim_datar_datar_buf_source_payload_data + attribute \src "build/ls180/gateware/ls180.v:1208.6-1208.46" + wire \libresocsim_datar_datar_buf_source_ready + attribute \src "build/ls180/gateware/ls180.v:1207.5-1207.45" + wire \libresocsim_datar_datar_buf_source_valid + attribute \src "build/ls180/gateware/ls180.v:1194.5-1194.44" + wire \libresocsim_datar_datar_converter_demux + attribute \src "build/ls180/gateware/ls180.v:1195.6-1195.49" + wire \libresocsim_datar_datar_converter_load_part + attribute \src "build/ls180/gateware/ls180.v:1185.5-1185.49" + wire \libresocsim_datar_datar_converter_sink_first + attribute \src "build/ls180/gateware/ls180.v:1186.5-1186.48" + wire \libresocsim_datar_datar_converter_sink_last + attribute \src "build/ls180/gateware/ls180.v:1187.12-1187.63" + wire width 4 \libresocsim_datar_datar_converter_sink_payload_data + attribute \src "build/ls180/gateware/ls180.v:1184.6-1184.50" + wire \libresocsim_datar_datar_converter_sink_ready + attribute \src "build/ls180/gateware/ls180.v:1183.6-1183.50" + wire \libresocsim_datar_datar_converter_sink_valid + attribute \src "build/ls180/gateware/ls180.v:1190.5-1190.51" + wire \libresocsim_datar_datar_converter_source_first + attribute \src "build/ls180/gateware/ls180.v:1191.5-1191.50" + wire \libresocsim_datar_datar_converter_source_last + attribute \src "build/ls180/gateware/ls180.v:1192.11-1192.64" + wire width 8 \libresocsim_datar_datar_converter_source_payload_data + attribute \src "build/ls180/gateware/ls180.v:1193.11-1193.77" + wire width 2 \libresocsim_datar_datar_converter_source_payload_valid_token_count + attribute \src "build/ls180/gateware/ls180.v:1189.6-1189.52" + wire \libresocsim_datar_datar_converter_source_ready + attribute \src "build/ls180/gateware/ls180.v:1188.6-1188.52" + wire \libresocsim_datar_datar_converter_source_valid + attribute \src "build/ls180/gateware/ls180.v:1196.5-1196.49" + wire \libresocsim_datar_datar_converter_strobe_all + attribute \src "build/ls180/gateware/ls180.v:1167.6-1167.43" + wire \libresocsim_datar_datar_pads_in_first + attribute \src "build/ls180/gateware/ls180.v:1168.6-1168.42" + wire \libresocsim_datar_datar_pads_in_last + attribute \src "build/ls180/gateware/ls180.v:1169.6-1169.49" + wire \libresocsim_datar_datar_pads_in_payload_clk + attribute \src "build/ls180/gateware/ls180.v:1170.6-1170.51" + wire \libresocsim_datar_datar_pads_in_payload_cmd_i + attribute \src "build/ls180/gateware/ls180.v:1171.6-1171.51" + wire \libresocsim_datar_datar_pads_in_payload_cmd_o + attribute \src "build/ls180/gateware/ls180.v:1172.6-1172.52" + wire \libresocsim_datar_datar_pads_in_payload_cmd_oe + attribute \src "build/ls180/gateware/ls180.v:1173.12-1173.58" + wire width 4 \libresocsim_datar_datar_pads_in_payload_data_i + attribute \src "build/ls180/gateware/ls180.v:1174.12-1174.58" + wire width 4 \libresocsim_datar_datar_pads_in_payload_data_o + attribute \src "build/ls180/gateware/ls180.v:1175.6-1175.53" + wire \libresocsim_datar_datar_pads_in_payload_data_oe + attribute \src "build/ls180/gateware/ls180.v:1166.5-1166.42" + wire \libresocsim_datar_datar_pads_in_ready + attribute \src "build/ls180/gateware/ls180.v:1165.6-1165.43" + wire \libresocsim_datar_datar_pads_in_valid + attribute \src "build/ls180/gateware/ls180.v:1212.5-1212.34" + wire \libresocsim_datar_datar_reset + attribute \src "build/ls180/gateware/ls180.v:1697.5-1697.63" + wire \libresocsim_datar_datar_reset_sdphy_sdphydatar_next_value2 + attribute \src "build/ls180/gateware/ls180.v:1698.5-1698.66" + wire \libresocsim_datar_datar_reset_sdphy_sdphydatar_next_value_ce2 + attribute \src "build/ls180/gateware/ls180.v:1182.5-1182.32" + wire \libresocsim_datar_datar_run + attribute \src "build/ls180/gateware/ls180.v:1178.6-1178.50" + wire \libresocsim_datar_datar_source_source_first0 + attribute \src "build/ls180/gateware/ls180.v:1199.6-1199.50" + wire \libresocsim_datar_datar_source_source_first1 + attribute \src "build/ls180/gateware/ls180.v:1179.6-1179.49" + wire \libresocsim_datar_datar_source_source_last0 + attribute \src "build/ls180/gateware/ls180.v:1200.6-1200.49" + wire \libresocsim_datar_datar_source_source_last1 + attribute \src "build/ls180/gateware/ls180.v:1180.12-1180.63" + wire width 8 \libresocsim_datar_datar_source_source_payload_data0 + attribute \src "build/ls180/gateware/ls180.v:1201.12-1201.63" + wire width 8 \libresocsim_datar_datar_source_source_payload_data1 + attribute \src "build/ls180/gateware/ls180.v:1177.5-1177.49" + wire \libresocsim_datar_datar_source_source_ready0 + attribute \src "build/ls180/gateware/ls180.v:1198.6-1198.50" + wire \libresocsim_datar_datar_source_source_ready1 + attribute \src "build/ls180/gateware/ls180.v:1176.6-1176.50" + wire \libresocsim_datar_datar_source_source_valid0 + attribute \src "build/ls180/gateware/ls180.v:1197.6-1197.50" + wire \libresocsim_datar_datar_source_source_valid1 + attribute \src "build/ls180/gateware/ls180.v:1181.6-1181.35" + wire \libresocsim_datar_datar_start + attribute \src "build/ls180/gateware/ls180.v:1137.5-1137.44" + wire \libresocsim_datar_pads_in_pads_in_first + attribute \src "build/ls180/gateware/ls180.v:1138.5-1138.43" + wire \libresocsim_datar_pads_in_pads_in_last + attribute \src "build/ls180/gateware/ls180.v:1139.5-1139.50" + wire \libresocsim_datar_pads_in_pads_in_payload_clk + attribute \src "build/ls180/gateware/ls180.v:1140.6-1140.53" + wire \libresocsim_datar_pads_in_pads_in_payload_cmd_i + attribute \src "build/ls180/gateware/ls180.v:1141.5-1141.52" + wire \libresocsim_datar_pads_in_pads_in_payload_cmd_o + attribute \src "build/ls180/gateware/ls180.v:1142.5-1142.53" + wire \libresocsim_datar_pads_in_pads_in_payload_cmd_oe + attribute \src "build/ls180/gateware/ls180.v:1143.12-1143.60" + wire width 4 \libresocsim_datar_pads_in_pads_in_payload_data_i + attribute \src "build/ls180/gateware/ls180.v:1144.11-1144.59" + wire width 4 \libresocsim_datar_pads_in_pads_in_payload_data_o + attribute \src "build/ls180/gateware/ls180.v:1145.5-1145.54" + wire \libresocsim_datar_pads_in_pads_in_payload_data_oe + attribute \src "build/ls180/gateware/ls180.v:1136.6-1136.45" + wire \libresocsim_datar_pads_in_pads_in_ready + attribute \src "build/ls180/gateware/ls180.v:1135.6-1135.45" + wire \libresocsim_datar_pads_in_pads_in_valid + attribute \src "build/ls180/gateware/ls180.v:1147.5-1147.43" + wire \libresocsim_datar_pads_out_payload_clk + attribute \src "build/ls180/gateware/ls180.v:1148.5-1148.45" + wire \libresocsim_datar_pads_out_payload_cmd_o + attribute \src "build/ls180/gateware/ls180.v:1149.5-1149.46" + wire \libresocsim_datar_pads_out_payload_cmd_oe + attribute \src "build/ls180/gateware/ls180.v:1150.11-1150.52" + wire width 4 \libresocsim_datar_pads_out_payload_data_o + attribute \src "build/ls180/gateware/ls180.v:1151.5-1151.47" + wire \libresocsim_datar_pads_out_payload_data_oe + attribute \src "build/ls180/gateware/ls180.v:1146.6-1146.38" + wire \libresocsim_datar_pads_out_ready + attribute \src "build/ls180/gateware/ls180.v:1154.5-1154.32" + wire \libresocsim_datar_sink_last + attribute \src "build/ls180/gateware/ls180.v:1155.11-1155.54" + wire width 10 \libresocsim_datar_sink_payload_block_length + attribute \src "build/ls180/gateware/ls180.v:1153.5-1153.33" + wire \libresocsim_datar_sink_ready + attribute \src "build/ls180/gateware/ls180.v:1152.5-1152.33" + wire \libresocsim_datar_sink_valid + attribute \src "build/ls180/gateware/ls180.v:1158.5-1158.35" + wire \libresocsim_datar_source_first + attribute \src "build/ls180/gateware/ls180.v:1159.5-1159.34" + wire \libresocsim_datar_source_last + attribute \src "build/ls180/gateware/ls180.v:1160.11-1160.48" + wire width 8 \libresocsim_datar_source_payload_data + attribute \src "build/ls180/gateware/ls180.v:1161.11-1161.50" + wire width 3 \libresocsim_datar_source_payload_status + attribute \src "build/ls180/gateware/ls180.v:1157.5-1157.35" + wire \libresocsim_datar_source_ready + attribute \src "build/ls180/gateware/ls180.v:1156.5-1156.35" + wire \libresocsim_datar_source_valid + attribute \src "build/ls180/gateware/ls180.v:1162.5-1162.27" + wire \libresocsim_datar_stop + attribute \src "build/ls180/gateware/ls180.v:1163.12-1163.37" + wire width 32 \libresocsim_datar_timeout + attribute \src "build/ls180/gateware/ls180.v:1695.12-1695.66" + wire width 32 \libresocsim_datar_timeout_sdphy_sdphydatar_next_value1 + attribute \src "build/ls180/gateware/ls180.v:1696.5-1696.62" + wire \libresocsim_datar_timeout_sdphy_sdphydatar_next_value_ce1 + attribute \src "build/ls180/gateware/ls180.v:1072.11-1072.34" + wire width 8 \libresocsim_dataw_count + attribute \src "build/ls180/gateware/ls180.v:1689.11-1689.55" + wire width 8 \libresocsim_dataw_count_sdphy_fsm_next_value + attribute \src "build/ls180/gateware/ls180.v:1690.5-1690.52" + wire \libresocsim_dataw_count_sdphy_fsm_next_value_ce + attribute \src "build/ls180/gateware/ls180.v:1126.6-1126.43" + wire \libresocsim_dataw_crcr_buf_sink_first + attribute \src "build/ls180/gateware/ls180.v:1127.6-1127.42" + wire \libresocsim_dataw_crcr_buf_sink_last + attribute \src "build/ls180/gateware/ls180.v:1128.12-1128.56" + wire width 8 \libresocsim_dataw_crcr_buf_sink_payload_data + attribute \src "build/ls180/gateware/ls180.v:1125.6-1125.43" + wire \libresocsim_dataw_crcr_buf_sink_ready + attribute \src "build/ls180/gateware/ls180.v:1124.6-1124.43" + wire \libresocsim_dataw_crcr_buf_sink_valid + attribute \src "build/ls180/gateware/ls180.v:1131.5-1131.44" + wire \libresocsim_dataw_crcr_buf_source_first + attribute \src "build/ls180/gateware/ls180.v:1132.5-1132.43" + wire \libresocsim_dataw_crcr_buf_source_last + attribute \src "build/ls180/gateware/ls180.v:1133.11-1133.57" + wire width 8 \libresocsim_dataw_crcr_buf_source_payload_data + attribute \src "build/ls180/gateware/ls180.v:1130.6-1130.45" + wire \libresocsim_dataw_crcr_buf_source_ready + attribute \src "build/ls180/gateware/ls180.v:1129.5-1129.44" + wire \libresocsim_dataw_crcr_buf_source_valid + attribute \src "build/ls180/gateware/ls180.v:1116.11-1116.49" + wire width 3 \libresocsim_dataw_crcr_converter_demux + attribute \src "build/ls180/gateware/ls180.v:1117.6-1117.48" + wire \libresocsim_dataw_crcr_converter_load_part + attribute \src "build/ls180/gateware/ls180.v:1107.5-1107.48" + wire \libresocsim_dataw_crcr_converter_sink_first + attribute \src "build/ls180/gateware/ls180.v:1108.5-1108.47" + wire \libresocsim_dataw_crcr_converter_sink_last + attribute \src "build/ls180/gateware/ls180.v:1109.6-1109.56" + wire \libresocsim_dataw_crcr_converter_sink_payload_data + attribute \src "build/ls180/gateware/ls180.v:1106.6-1106.49" + wire \libresocsim_dataw_crcr_converter_sink_ready + attribute \src "build/ls180/gateware/ls180.v:1105.6-1105.49" + wire \libresocsim_dataw_crcr_converter_sink_valid + attribute \src "build/ls180/gateware/ls180.v:1112.5-1112.50" + wire \libresocsim_dataw_crcr_converter_source_first + attribute \src "build/ls180/gateware/ls180.v:1113.5-1113.49" + wire \libresocsim_dataw_crcr_converter_source_last + attribute \src "build/ls180/gateware/ls180.v:1114.11-1114.63" + wire width 8 \libresocsim_dataw_crcr_converter_source_payload_data + attribute \src "build/ls180/gateware/ls180.v:1115.11-1115.76" + wire width 4 \libresocsim_dataw_crcr_converter_source_payload_valid_token_count + attribute \src "build/ls180/gateware/ls180.v:1111.6-1111.51" + wire \libresocsim_dataw_crcr_converter_source_ready + attribute \src "build/ls180/gateware/ls180.v:1110.6-1110.51" + wire \libresocsim_dataw_crcr_converter_source_valid + attribute \src "build/ls180/gateware/ls180.v:1118.5-1118.48" + wire \libresocsim_dataw_crcr_converter_strobe_all + attribute \src "build/ls180/gateware/ls180.v:1089.6-1089.42" + wire \libresocsim_dataw_crcr_pads_in_first + attribute \src "build/ls180/gateware/ls180.v:1090.6-1090.41" + wire \libresocsim_dataw_crcr_pads_in_last + attribute \src "build/ls180/gateware/ls180.v:1091.6-1091.48" + wire \libresocsim_dataw_crcr_pads_in_payload_clk + attribute \src "build/ls180/gateware/ls180.v:1092.6-1092.50" + wire \libresocsim_dataw_crcr_pads_in_payload_cmd_i + attribute \src "build/ls180/gateware/ls180.v:1093.6-1093.50" + wire \libresocsim_dataw_crcr_pads_in_payload_cmd_o + attribute \src "build/ls180/gateware/ls180.v:1094.6-1094.51" + wire \libresocsim_dataw_crcr_pads_in_payload_cmd_oe + attribute \src "build/ls180/gateware/ls180.v:1095.12-1095.57" + wire width 4 \libresocsim_dataw_crcr_pads_in_payload_data_i + attribute \src "build/ls180/gateware/ls180.v:1096.12-1096.57" + wire width 4 \libresocsim_dataw_crcr_pads_in_payload_data_o + attribute \src "build/ls180/gateware/ls180.v:1097.6-1097.52" + wire \libresocsim_dataw_crcr_pads_in_payload_data_oe + attribute \src "build/ls180/gateware/ls180.v:1088.5-1088.41" + wire \libresocsim_dataw_crcr_pads_in_ready + attribute \src "build/ls180/gateware/ls180.v:1087.6-1087.42" + wire \libresocsim_dataw_crcr_pads_in_valid + attribute \src "build/ls180/gateware/ls180.v:1134.5-1134.33" + wire \libresocsim_dataw_crcr_reset + attribute \src "build/ls180/gateware/ls180.v:1685.5-1685.60" + wire \libresocsim_dataw_crcr_reset_sdphy_sdphycrcr_next_value + attribute \src "build/ls180/gateware/ls180.v:1686.5-1686.63" + wire \libresocsim_dataw_crcr_reset_sdphy_sdphycrcr_next_value_ce + attribute \src "build/ls180/gateware/ls180.v:1104.5-1104.31" + wire \libresocsim_dataw_crcr_run + attribute \src "build/ls180/gateware/ls180.v:1100.6-1100.49" + wire \libresocsim_dataw_crcr_source_source_first0 + attribute \src "build/ls180/gateware/ls180.v:1121.6-1121.49" + wire \libresocsim_dataw_crcr_source_source_first1 + attribute \src "build/ls180/gateware/ls180.v:1101.6-1101.48" + wire \libresocsim_dataw_crcr_source_source_last0 + attribute \src "build/ls180/gateware/ls180.v:1122.6-1122.48" + wire \libresocsim_dataw_crcr_source_source_last1 + attribute \src "build/ls180/gateware/ls180.v:1102.12-1102.62" + wire width 8 \libresocsim_dataw_crcr_source_source_payload_data0 + attribute \src "build/ls180/gateware/ls180.v:1123.12-1123.62" + wire width 8 \libresocsim_dataw_crcr_source_source_payload_data1 + attribute \src "build/ls180/gateware/ls180.v:1099.5-1099.48" + wire \libresocsim_dataw_crcr_source_source_ready0 + attribute \src "build/ls180/gateware/ls180.v:1120.6-1120.49" + wire \libresocsim_dataw_crcr_source_source_ready1 + attribute \src "build/ls180/gateware/ls180.v:1098.6-1098.49" + wire \libresocsim_dataw_crcr_source_source_valid0 + attribute \src "build/ls180/gateware/ls180.v:1119.6-1119.49" + wire \libresocsim_dataw_crcr_source_source_valid1 + attribute \src "build/ls180/gateware/ls180.v:1103.6-1103.34" + wire \libresocsim_dataw_crcr_start + attribute \src "build/ls180/gateware/ls180.v:1086.5-1086.28" + wire \libresocsim_dataw_error + attribute \src "build/ls180/gateware/ls180.v:1075.5-1075.44" + wire \libresocsim_dataw_pads_in_pads_in_first + attribute \src "build/ls180/gateware/ls180.v:1076.5-1076.43" + wire \libresocsim_dataw_pads_in_pads_in_last + attribute \src "build/ls180/gateware/ls180.v:1077.5-1077.50" + wire \libresocsim_dataw_pads_in_pads_in_payload_clk + attribute \src "build/ls180/gateware/ls180.v:1078.5-1078.52" + wire \libresocsim_dataw_pads_in_pads_in_payload_cmd_i + attribute \src "build/ls180/gateware/ls180.v:1079.5-1079.52" + wire \libresocsim_dataw_pads_in_pads_in_payload_cmd_o + attribute \src "build/ls180/gateware/ls180.v:1080.5-1080.53" + wire \libresocsim_dataw_pads_in_pads_in_payload_cmd_oe + attribute \src "build/ls180/gateware/ls180.v:1081.11-1081.59" + wire width 4 \libresocsim_dataw_pads_in_pads_in_payload_data_i + attribute \src "build/ls180/gateware/ls180.v:1082.11-1082.59" + wire width 4 \libresocsim_dataw_pads_in_pads_in_payload_data_o + attribute \src "build/ls180/gateware/ls180.v:1083.5-1083.54" + wire \libresocsim_dataw_pads_in_pads_in_payload_data_oe + attribute \src "build/ls180/gateware/ls180.v:1074.6-1074.45" + wire \libresocsim_dataw_pads_in_pads_in_ready + attribute \src "build/ls180/gateware/ls180.v:1073.5-1073.44" + wire \libresocsim_dataw_pads_in_pads_in_valid + attribute \src "build/ls180/gateware/ls180.v:1058.6-1058.45" + wire \libresocsim_dataw_pads_in_payload_cmd_i + attribute \src "build/ls180/gateware/ls180.v:1059.12-1059.52" + wire width 4 \libresocsim_dataw_pads_in_payload_data_i + attribute \src "build/ls180/gateware/ls180.v:1057.6-1057.37" + wire \libresocsim_dataw_pads_in_valid + attribute \src "build/ls180/gateware/ls180.v:1061.5-1061.43" + wire \libresocsim_dataw_pads_out_payload_clk + attribute \src "build/ls180/gateware/ls180.v:1062.5-1062.45" + wire \libresocsim_dataw_pads_out_payload_cmd_o + attribute \src "build/ls180/gateware/ls180.v:1063.5-1063.46" + wire \libresocsim_dataw_pads_out_payload_cmd_oe + attribute \src "build/ls180/gateware/ls180.v:1064.11-1064.52" + wire width 4 \libresocsim_dataw_pads_out_payload_data_o + attribute \src "build/ls180/gateware/ls180.v:1065.5-1065.47" + wire \libresocsim_dataw_pads_out_payload_data_oe + attribute \src "build/ls180/gateware/ls180.v:1060.6-1060.38" + wire \libresocsim_dataw_pads_out_ready + attribute \src "build/ls180/gateware/ls180.v:1068.5-1068.33" + wire \libresocsim_dataw_sink_first + attribute \src "build/ls180/gateware/ls180.v:1069.5-1069.32" + wire \libresocsim_dataw_sink_last + attribute \src "build/ls180/gateware/ls180.v:1070.11-1070.46" + wire width 8 \libresocsim_dataw_sink_payload_data + attribute \src "build/ls180/gateware/ls180.v:1067.5-1067.33" + wire \libresocsim_dataw_sink_ready + attribute \src "build/ls180/gateware/ls180.v:1066.5-1066.33" + wire \libresocsim_dataw_sink_valid + attribute \src "build/ls180/gateware/ls180.v:1084.5-1084.28" + wire \libresocsim_dataw_start + attribute \src "build/ls180/gateware/ls180.v:1071.5-1071.27" + wire \libresocsim_dataw_stop + attribute \src "build/ls180/gateware/ls180.v:1085.5-1085.28" + wire \libresocsim_dataw_valid + attribute \src "build/ls180/gateware/ls180.v:1582.5-1582.22" + wire \libresocsim_done0 + attribute \src "build/ls180/gateware/ls180.v:1593.6-1593.23" + wire \libresocsim_done1 + attribute \src "build/ls180/gateware/ls180.v:965.11-965.33" + wire width 8 \libresocsim_init_count + attribute \src "build/ls180/gateware/ls180.v:1669.11-1669.60" + wire width 8 \libresocsim_init_count_sdphy_sdphyinit_next_value + attribute \src "build/ls180/gateware/ls180.v:1670.5-1670.57" + wire \libresocsim_init_count_sdphy_sdphyinit_next_value_ce + attribute \src "build/ls180/gateware/ls180.v:953.6-953.35" + wire \libresocsim_init_initialize_r + attribute \src "build/ls180/gateware/ls180.v:952.6-952.36" + wire \libresocsim_init_initialize_re + attribute \src "build/ls180/gateware/ls180.v:955.5-955.34" + wire \libresocsim_init_initialize_w + attribute \src "build/ls180/gateware/ls180.v:954.6-954.36" + wire \libresocsim_init_initialize_we + attribute \src "build/ls180/gateware/ls180.v:957.6-957.44" + wire \libresocsim_init_pads_in_payload_cmd_i + attribute \src "build/ls180/gateware/ls180.v:958.12-958.51" + wire width 4 \libresocsim_init_pads_in_payload_data_i + attribute \src "build/ls180/gateware/ls180.v:956.6-956.36" + wire \libresocsim_init_pads_in_valid + attribute \src "build/ls180/gateware/ls180.v:960.5-960.42" + wire \libresocsim_init_pads_out_payload_clk + attribute \src "build/ls180/gateware/ls180.v:961.5-961.44" + wire \libresocsim_init_pads_out_payload_cmd_o + attribute \src "build/ls180/gateware/ls180.v:962.5-962.45" + wire \libresocsim_init_pads_out_payload_cmd_oe + attribute \src "build/ls180/gateware/ls180.v:963.11-963.51" + wire width 4 \libresocsim_init_pads_out_payload_data_o + attribute \src "build/ls180/gateware/ls180.v:964.5-964.46" + wire \libresocsim_init_pads_out_payload_data_oe + attribute \src "build/ls180/gateware/ls180.v:959.6-959.37" + wire \libresocsim_init_pads_out_ready + attribute \src "build/ls180/gateware/ls180.v:1401.6-1401.36" + wire \libresocsim_interface0_bus_ack + attribute \src "build/ls180/gateware/ls180.v:1395.13-1395.43" + wire width 32 \libresocsim_interface0_bus_adr + attribute \src "build/ls180/gateware/ls180.v:1404.11-1404.41" + wire width 2 \libresocsim_interface0_bus_bte + attribute \src "build/ls180/gateware/ls180.v:1403.11-1403.41" + wire width 3 \libresocsim_interface0_bus_cti + attribute \src "build/ls180/gateware/ls180.v:1399.6-1399.36" + wire \libresocsim_interface0_bus_cyc + attribute \src "build/ls180/gateware/ls180.v:1397.13-1397.45" + wire width 32 \libresocsim_interface0_bus_dat_r + attribute \src "build/ls180/gateware/ls180.v:1396.13-1396.45" + wire width 32 \libresocsim_interface0_bus_dat_w + attribute \src "build/ls180/gateware/ls180.v:1405.6-1405.36" + wire \libresocsim_interface0_bus_err + attribute \src "build/ls180/gateware/ls180.v:1398.12-1398.42" + wire width 4 \libresocsim_interface0_bus_sel + attribute \src "build/ls180/gateware/ls180.v:1400.6-1400.36" + wire \libresocsim_interface0_bus_stb + attribute \src "build/ls180/gateware/ls180.v:1402.6-1402.35" + wire \libresocsim_interface0_bus_we + attribute \src "build/ls180/gateware/ls180.v:1492.6-1492.36" + wire \libresocsim_interface1_bus_ack + attribute \src "build/ls180/gateware/ls180.v:1486.12-1486.42" + wire width 32 \libresocsim_interface1_bus_adr + attribute \src "build/ls180/gateware/ls180.v:1495.11-1495.41" + wire width 2 \libresocsim_interface1_bus_bte + attribute \src "build/ls180/gateware/ls180.v:1494.11-1494.41" + wire width 3 \libresocsim_interface1_bus_cti + attribute \src "build/ls180/gateware/ls180.v:1490.5-1490.35" + wire \libresocsim_interface1_bus_cyc + attribute \src "build/ls180/gateware/ls180.v:1488.13-1488.45" + wire width 32 \libresocsim_interface1_bus_dat_r + attribute \src "build/ls180/gateware/ls180.v:1487.12-1487.44" + wire width 32 \libresocsim_interface1_bus_dat_w + attribute \src "build/ls180/gateware/ls180.v:1496.6-1496.36" + wire \libresocsim_interface1_bus_err + attribute \src "build/ls180/gateware/ls180.v:1489.11-1489.41" + wire width 4 \libresocsim_interface1_bus_sel + attribute \src "build/ls180/gateware/ls180.v:1491.5-1491.35" + wire \libresocsim_interface1_bus_stb + attribute \src "build/ls180/gateware/ls180.v:1493.5-1493.34" + wire \libresocsim_interface1_bus_we + attribute \src "build/ls180/gateware/ls180.v:1583.5-1583.20" + wire \libresocsim_irq + attribute \src "build/ls180/gateware/ls180.v:1581.12-1581.31" + wire width 8 \libresocsim_length0 + attribute \src "build/ls180/gateware/ls180.v:1590.12-1590.31" + wire width 8 \libresocsim_length1 + attribute \src "build/ls180/gateware/ls180.v:1587.6-1587.26" + wire \libresocsim_loopback + attribute \src "build/ls180/gateware/ls180.v:1604.5-1604.28" + wire \libresocsim_loopback_re + attribute \src "build/ls180/gateware/ls180.v:1603.5-1603.33" + wire \libresocsim_loopback_storage + attribute \src "build/ls180/gateware/ls180.v:1585.11-1585.27" + wire width 8 \libresocsim_miso + attribute \src "build/ls180/gateware/ls180.v:1615.11-1615.32" + wire width 8 \libresocsim_miso_data + attribute \src "build/ls180/gateware/ls180.v:1609.5-1609.27" + wire \libresocsim_miso_latch + attribute \src "build/ls180/gateware/ls180.v:1598.12-1598.35" + wire width 8 \libresocsim_miso_status + attribute \src "build/ls180/gateware/ls180.v:1599.6-1599.25" + wire \libresocsim_miso_we + attribute \src "build/ls180/gateware/ls180.v:1584.12-1584.28" + wire width 8 \libresocsim_mosi + attribute \src "build/ls180/gateware/ls180.v:1613.11-1613.32" + wire width 8 \libresocsim_mosi_data + attribute \src "build/ls180/gateware/ls180.v:1608.5-1608.27" + wire \libresocsim_mosi_latch + attribute \src "build/ls180/gateware/ls180.v:1597.5-1597.24" + wire \libresocsim_mosi_re + attribute \src "build/ls180/gateware/ls180.v:1614.11-1614.31" + wire width 3 \libresocsim_mosi_sel + attribute \src "build/ls180/gateware/ls180.v:1596.11-1596.35" + wire width 8 \libresocsim_mosi_storage + attribute \src "build/ls180/gateware/ls180.v:1617.5-1617.19" + wire \libresocsim_re + attribute \src "build/ls180/gateware/ls180.v:1455.11-1455.50" + wire width 2 \libresocsim_sdblock2mem_converter_demux + attribute \src "build/ls180/gateware/ls180.v:1456.6-1456.49" + wire \libresocsim_sdblock2mem_converter_load_part + attribute \src "build/ls180/gateware/ls180.v:1446.6-1446.50" + wire \libresocsim_sdblock2mem_converter_sink_first + attribute \src "build/ls180/gateware/ls180.v:1447.6-1447.49" + wire \libresocsim_sdblock2mem_converter_sink_last + attribute \src "build/ls180/gateware/ls180.v:1448.12-1448.63" + wire width 8 \libresocsim_sdblock2mem_converter_sink_payload_data + attribute \src "build/ls180/gateware/ls180.v:1445.6-1445.50" + wire \libresocsim_sdblock2mem_converter_sink_ready + attribute \src "build/ls180/gateware/ls180.v:1444.6-1444.50" + wire \libresocsim_sdblock2mem_converter_sink_valid + attribute \src "build/ls180/gateware/ls180.v:1451.5-1451.51" + wire \libresocsim_sdblock2mem_converter_source_first + attribute \src "build/ls180/gateware/ls180.v:1452.5-1452.50" + wire \libresocsim_sdblock2mem_converter_source_last + attribute \src "build/ls180/gateware/ls180.v:1453.12-1453.65" + wire width 32 \libresocsim_sdblock2mem_converter_source_payload_data + attribute \src "build/ls180/gateware/ls180.v:1454.11-1454.77" + wire width 3 \libresocsim_sdblock2mem_converter_source_payload_valid_token_count + attribute \src "build/ls180/gateware/ls180.v:1450.6-1450.52" + wire \libresocsim_sdblock2mem_converter_source_ready + attribute \src "build/ls180/gateware/ls180.v:1449.6-1449.52" + wire \libresocsim_sdblock2mem_converter_source_valid + attribute \src "build/ls180/gateware/ls180.v:1457.5-1457.49" + wire \libresocsim_sdblock2mem_converter_strobe_all + attribute \src "build/ls180/gateware/ls180.v:1430.11-1430.47" + wire width 5 \libresocsim_sdblock2mem_fifo_consume + attribute \src "build/ls180/gateware/ls180.v:1435.6-1435.42" + wire \libresocsim_sdblock2mem_fifo_do_read + attribute \src "build/ls180/gateware/ls180.v:1439.6-1439.48" + wire \libresocsim_sdblock2mem_fifo_fifo_in_first + attribute \src "build/ls180/gateware/ls180.v:1440.6-1440.47" + wire \libresocsim_sdblock2mem_fifo_fifo_in_last + attribute \src "build/ls180/gateware/ls180.v:1438.12-1438.61" + wire width 8 \libresocsim_sdblock2mem_fifo_fifo_in_payload_data + attribute \src "build/ls180/gateware/ls180.v:1442.6-1442.49" + wire \libresocsim_sdblock2mem_fifo_fifo_out_first + attribute \src "build/ls180/gateware/ls180.v:1443.6-1443.48" + wire \libresocsim_sdblock2mem_fifo_fifo_out_last + attribute \src "build/ls180/gateware/ls180.v:1441.12-1441.62" + wire width 8 \libresocsim_sdblock2mem_fifo_fifo_out_payload_data + attribute \src "build/ls180/gateware/ls180.v:1427.11-1427.45" + wire width 6 \libresocsim_sdblock2mem_fifo_level + attribute \src "build/ls180/gateware/ls180.v:1429.11-1429.47" + wire width 5 \libresocsim_sdblock2mem_fifo_produce + attribute \src "build/ls180/gateware/ls180.v:1436.12-1436.51" + wire width 5 \libresocsim_sdblock2mem_fifo_rdport_adr + attribute \src "build/ls180/gateware/ls180.v:1437.12-1437.53" + wire width 10 \libresocsim_sdblock2mem_fifo_rdport_dat_r + attribute \src "build/ls180/gateware/ls180.v:1428.5-1428.41" + wire \libresocsim_sdblock2mem_fifo_replace + attribute \src "build/ls180/gateware/ls180.v:1413.6-1413.45" + wire \libresocsim_sdblock2mem_fifo_sink_first + attribute \src "build/ls180/gateware/ls180.v:1414.6-1414.44" + wire \libresocsim_sdblock2mem_fifo_sink_last + attribute \src "build/ls180/gateware/ls180.v:1415.12-1415.58" + wire width 8 \libresocsim_sdblock2mem_fifo_sink_payload_data + attribute \src "build/ls180/gateware/ls180.v:1412.6-1412.45" + wire \libresocsim_sdblock2mem_fifo_sink_ready + attribute \src "build/ls180/gateware/ls180.v:1411.6-1411.45" + wire \libresocsim_sdblock2mem_fifo_sink_valid + attribute \src "build/ls180/gateware/ls180.v:1418.6-1418.47" + wire \libresocsim_sdblock2mem_fifo_source_first + attribute \src "build/ls180/gateware/ls180.v:1419.6-1419.46" + wire \libresocsim_sdblock2mem_fifo_source_last + attribute \src "build/ls180/gateware/ls180.v:1420.12-1420.60" + wire width 8 \libresocsim_sdblock2mem_fifo_source_payload_data + attribute \src "build/ls180/gateware/ls180.v:1417.6-1417.47" + wire \libresocsim_sdblock2mem_fifo_source_ready + attribute \src "build/ls180/gateware/ls180.v:1416.6-1416.47" + wire \libresocsim_sdblock2mem_fifo_source_valid + attribute \src "build/ls180/gateware/ls180.v:1425.12-1425.53" + wire width 10 \libresocsim_sdblock2mem_fifo_syncfifo_din + attribute \src "build/ls180/gateware/ls180.v:1426.12-1426.54" + wire width 10 \libresocsim_sdblock2mem_fifo_syncfifo_dout + attribute \src "build/ls180/gateware/ls180.v:1423.6-1423.46" + wire \libresocsim_sdblock2mem_fifo_syncfifo_re + attribute \src "build/ls180/gateware/ls180.v:1424.6-1424.52" + wire \libresocsim_sdblock2mem_fifo_syncfifo_readable + attribute \src "build/ls180/gateware/ls180.v:1421.6-1421.46" + wire \libresocsim_sdblock2mem_fifo_syncfifo_we + attribute \src "build/ls180/gateware/ls180.v:1422.6-1422.52" + wire \libresocsim_sdblock2mem_fifo_syncfifo_writable + attribute \src "build/ls180/gateware/ls180.v:1431.11-1431.50" + wire width 5 \libresocsim_sdblock2mem_fifo_wrport_adr + attribute \src "build/ls180/gateware/ls180.v:1432.12-1432.53" + wire width 10 \libresocsim_sdblock2mem_fifo_wrport_dat_r + attribute \src "build/ls180/gateware/ls180.v:1434.12-1434.53" + wire width 10 \libresocsim_sdblock2mem_fifo_wrport_dat_w + attribute \src "build/ls180/gateware/ls180.v:1433.6-1433.44" + wire \libresocsim_sdblock2mem_fifo_wrport_we + attribute \src "build/ls180/gateware/ls180.v:1408.6-1408.45" + wire \libresocsim_sdblock2mem_sink_sink_first + attribute \src "build/ls180/gateware/ls180.v:1409.6-1409.44" + wire \libresocsim_sdblock2mem_sink_sink_last + attribute \src "build/ls180/gateware/ls180.v:1465.12-1465.61" + wire width 32 \libresocsim_sdblock2mem_sink_sink_payload_address + attribute \src "build/ls180/gateware/ls180.v:1410.12-1410.59" + wire width 8 \libresocsim_sdblock2mem_sink_sink_payload_data0 + attribute \src "build/ls180/gateware/ls180.v:1466.12-1466.59" + wire width 32 \libresocsim_sdblock2mem_sink_sink_payload_data1 + attribute \src "build/ls180/gateware/ls180.v:1407.6-1407.46" + wire \libresocsim_sdblock2mem_sink_sink_ready0 + attribute \src "build/ls180/gateware/ls180.v:1464.6-1464.46" + wire \libresocsim_sdblock2mem_sink_sink_ready1 + attribute \src "build/ls180/gateware/ls180.v:1406.6-1406.46" + wire \libresocsim_sdblock2mem_sink_sink_valid0 + attribute \src "build/ls180/gateware/ls180.v:1463.5-1463.45" + wire \libresocsim_sdblock2mem_sink_sink_valid1 + attribute \src "build/ls180/gateware/ls180.v:1460.6-1460.49" + wire \libresocsim_sdblock2mem_source_source_first + attribute \src "build/ls180/gateware/ls180.v:1461.6-1461.48" + wire \libresocsim_sdblock2mem_source_source_last + attribute \src "build/ls180/gateware/ls180.v:1462.13-1462.63" + wire width 32 \libresocsim_sdblock2mem_source_source_payload_data + attribute \src "build/ls180/gateware/ls180.v:1459.6-1459.49" + wire \libresocsim_sdblock2mem_source_source_ready + attribute \src "build/ls180/gateware/ls180.v:1458.6-1458.49" + wire \libresocsim_sdblock2mem_source_source_valid + attribute \src "build/ls180/gateware/ls180.v:1482.13-1482.59" + wire width 32 \libresocsim_sdblock2mem_wishbonedmawriter_base + attribute \src "build/ls180/gateware/ls180.v:1473.5-1473.54" + wire \libresocsim_sdblock2mem_wishbonedmawriter_base_re + attribute \src "build/ls180/gateware/ls180.v:1472.12-1472.66" + wire width 64 \libresocsim_sdblock2mem_wishbonedmawriter_base_storage + attribute \src "build/ls180/gateware/ls180.v:1477.5-1477.56" + wire \libresocsim_sdblock2mem_wishbonedmawriter_enable_re + attribute \src "build/ls180/gateware/ls180.v:1476.5-1476.61" + wire \libresocsim_sdblock2mem_wishbonedmawriter_enable_storage + attribute \src "build/ls180/gateware/ls180.v:1484.13-1484.61" + wire width 32 \libresocsim_sdblock2mem_wishbonedmawriter_length + attribute \src "build/ls180/gateware/ls180.v:1475.5-1475.56" + wire \libresocsim_sdblock2mem_wishbonedmawriter_length_re + attribute \src "build/ls180/gateware/ls180.v:1474.12-1474.68" + wire width 32 \libresocsim_sdblock2mem_wishbonedmawriter_length_storage + attribute \src "build/ls180/gateware/ls180.v:1481.5-1481.54" + wire \libresocsim_sdblock2mem_wishbonedmawriter_loop_re + attribute \src "build/ls180/gateware/ls180.v:1480.5-1480.59" + wire \libresocsim_sdblock2mem_wishbonedmawriter_loop_storage + attribute \src "build/ls180/gateware/ls180.v:1483.12-1483.60" + wire width 32 \libresocsim_sdblock2mem_wishbonedmawriter_offset + attribute \src "build/ls180/gateware/ls180.v:1733.12-1733.86" + wire width 32 \libresocsim_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value + attribute \src "build/ls180/gateware/ls180.v:1734.5-1734.82" + wire \libresocsim_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value_ce + attribute \src "build/ls180/gateware/ls180.v:1485.6-1485.53" + wire \libresocsim_sdblock2mem_wishbonedmawriter_reset + attribute \src "build/ls180/gateware/ls180.v:1469.6-1469.58" + wire \libresocsim_sdblock2mem_wishbonedmawriter_sink_first + attribute \src "build/ls180/gateware/ls180.v:1470.6-1470.57" + wire \libresocsim_sdblock2mem_wishbonedmawriter_sink_last + attribute \src "build/ls180/gateware/ls180.v:1471.13-1471.72" + wire width 32 \libresocsim_sdblock2mem_wishbonedmawriter_sink_payload_data + attribute \src "build/ls180/gateware/ls180.v:1468.5-1468.57" + wire \libresocsim_sdblock2mem_wishbonedmawriter_sink_ready + attribute \src "build/ls180/gateware/ls180.v:1467.6-1467.58" + wire \libresocsim_sdblock2mem_wishbonedmawriter_sink_valid + attribute \src "build/ls180/gateware/ls180.v:1478.5-1478.53" + wire \libresocsim_sdblock2mem_wishbonedmawriter_status + attribute \src "build/ls180/gateware/ls180.v:1479.6-1479.50" + wire \libresocsim_sdblock2mem_wishbonedmawriter_we + attribute \src "build/ls180/gateware/ls180.v:1247.5-1247.38" + wire \libresocsim_sdcore_block_count_re + attribute \src "build/ls180/gateware/ls180.v:1246.12-1246.50" + wire width 32 \libresocsim_sdcore_block_count_storage + attribute \src "build/ls180/gateware/ls180.v:1245.5-1245.39" + wire \libresocsim_sdcore_block_length_re + attribute \src "build/ls180/gateware/ls180.v:1244.11-1244.50" + wire width 10 \libresocsim_sdcore_block_length_storage + attribute \src "build/ls180/gateware/ls180.v:1231.5-1231.39" + wire \libresocsim_sdcore_cmd_argument_re + attribute \src "build/ls180/gateware/ls180.v:1230.12-1230.51" + wire width 32 \libresocsim_sdcore_cmd_argument_storage + attribute \src "build/ls180/gateware/ls180.v:1233.5-1233.38" + wire \libresocsim_sdcore_cmd_command_re + attribute \src "build/ls180/gateware/ls180.v:1232.12-1232.50" + wire width 32 \libresocsim_sdcore_cmd_command_storage + attribute \src "build/ls180/gateware/ls180.v:1386.11-1386.39" + wire width 3 \libresocsim_sdcore_cmd_count + attribute \src "build/ls180/gateware/ls180.v:1717.11-1717.62" + wire width 3 \libresocsim_sdcore_cmd_count_sdcore_fsm_next_value2 + attribute \src "build/ls180/gateware/ls180.v:1718.5-1718.59" + wire \libresocsim_sdcore_cmd_count_sdcore_fsm_next_value_ce2 + attribute \src "build/ls180/gateware/ls180.v:1387.5-1387.32" + wire \libresocsim_sdcore_cmd_done + attribute \src "build/ls180/gateware/ls180.v:1713.5-1713.55" + wire \libresocsim_sdcore_cmd_done_sdcore_fsm_next_value0 + attribute \src "build/ls180/gateware/ls180.v:1714.5-1714.58" + wire \libresocsim_sdcore_cmd_done_sdcore_fsm_next_value_ce0 + attribute \src "build/ls180/gateware/ls180.v:1388.5-1388.33" + wire \libresocsim_sdcore_cmd_error + attribute \src "build/ls180/gateware/ls180.v:1721.5-1721.56" + wire \libresocsim_sdcore_cmd_error_sdcore_fsm_next_value4 + attribute \src "build/ls180/gateware/ls180.v:1722.5-1722.59" + wire \libresocsim_sdcore_cmd_error_sdcore_fsm_next_value_ce4 + attribute \src "build/ls180/gateware/ls180.v:1240.12-1240.47" + wire width 4 \libresocsim_sdcore_cmd_event_status + attribute \src "build/ls180/gateware/ls180.v:1241.6-1241.37" + wire \libresocsim_sdcore_cmd_event_we + attribute \src "build/ls180/gateware/ls180.v:1238.13-1238.51" + wire width 128 \libresocsim_sdcore_cmd_response_status + attribute \src "build/ls180/gateware/ls180.v:1729.13-1729.74" + wire width 128 \libresocsim_sdcore_cmd_response_status_sdcore_fsm_next_value8 + attribute \src "build/ls180/gateware/ls180.v:1730.5-1730.69" + wire \libresocsim_sdcore_cmd_response_status_sdcore_fsm_next_value_ce8 + attribute \src "build/ls180/gateware/ls180.v:1239.6-1239.40" + wire \libresocsim_sdcore_cmd_response_we + attribute \src "build/ls180/gateware/ls180.v:1235.6-1235.35" + wire \libresocsim_sdcore_cmd_send_r + attribute \src "build/ls180/gateware/ls180.v:1234.6-1234.36" + wire \libresocsim_sdcore_cmd_send_re + attribute \src "build/ls180/gateware/ls180.v:1237.5-1237.34" + wire \libresocsim_sdcore_cmd_send_w + attribute \src "build/ls180/gateware/ls180.v:1236.6-1236.36" + wire \libresocsim_sdcore_cmd_send_we + attribute \src "build/ls180/gateware/ls180.v:1389.5-1389.35" + wire \libresocsim_sdcore_cmd_timeout + attribute \src "build/ls180/gateware/ls180.v:1723.5-1723.58" + wire \libresocsim_sdcore_cmd_timeout_sdcore_fsm_next_value5 + attribute \src "build/ls180/gateware/ls180.v:1724.5-1724.61" + wire \libresocsim_sdcore_cmd_timeout_sdcore_fsm_next_value_ce5 + attribute \src "build/ls180/gateware/ls180.v:1385.12-1385.39" + wire width 2 \libresocsim_sdcore_cmd_type + attribute \src "build/ls180/gateware/ls180.v:1347.11-1347.47" + wire width 4 \libresocsim_sdcore_crc16_checker_cnt + attribute \src "build/ls180/gateware/ls180.v:1353.5-1353.46" + wire \libresocsim_sdcore_crc16_checker_crc0_clr + attribute \src "build/ls180/gateware/ls180.v:1352.12-1352.53" + wire width 16 \libresocsim_sdcore_crc16_checker_crc0_crc + attribute \src "build/ls180/gateware/ls180.v:1348.12-1348.57" + wire width 16 \libresocsim_sdcore_crc16_checker_crc0_crcreg0 + attribute \src "build/ls180/gateware/ls180.v:1349.13-1349.58" + wire width 16 \libresocsim_sdcore_crc16_checker_crc0_crcreg1 + attribute \src "build/ls180/gateware/ls180.v:1350.13-1350.58" + wire width 16 \libresocsim_sdcore_crc16_checker_crc0_crcreg2 + attribute \src "build/ls180/gateware/ls180.v:1354.6-1354.50" + wire \libresocsim_sdcore_crc16_checker_crc0_enable + attribute \src "build/ls180/gateware/ls180.v:1351.12-1351.53" + wire width 2 \libresocsim_sdcore_crc16_checker_crc0_val + attribute \src "build/ls180/gateware/ls180.v:1360.5-1360.46" + wire \libresocsim_sdcore_crc16_checker_crc1_clr + attribute \src "build/ls180/gateware/ls180.v:1359.12-1359.53" + wire width 16 \libresocsim_sdcore_crc16_checker_crc1_crc + attribute \src "build/ls180/gateware/ls180.v:1355.12-1355.57" + wire width 16 \libresocsim_sdcore_crc16_checker_crc1_crcreg0 + attribute \src "build/ls180/gateware/ls180.v:1356.13-1356.58" + wire width 16 \libresocsim_sdcore_crc16_checker_crc1_crcreg1 + attribute \src "build/ls180/gateware/ls180.v:1357.13-1357.58" + wire width 16 \libresocsim_sdcore_crc16_checker_crc1_crcreg2 + attribute \src "build/ls180/gateware/ls180.v:1361.6-1361.50" + wire \libresocsim_sdcore_crc16_checker_crc1_enable + attribute \src "build/ls180/gateware/ls180.v:1358.12-1358.53" + wire width 2 \libresocsim_sdcore_crc16_checker_crc1_val + attribute \src "build/ls180/gateware/ls180.v:1367.5-1367.46" + wire \libresocsim_sdcore_crc16_checker_crc2_clr + attribute \src "build/ls180/gateware/ls180.v:1366.12-1366.53" + wire width 16 \libresocsim_sdcore_crc16_checker_crc2_crc + attribute \src "build/ls180/gateware/ls180.v:1362.12-1362.57" + wire width 16 \libresocsim_sdcore_crc16_checker_crc2_crcreg0 + attribute \src "build/ls180/gateware/ls180.v:1363.13-1363.58" + wire width 16 \libresocsim_sdcore_crc16_checker_crc2_crcreg1 + attribute \src "build/ls180/gateware/ls180.v:1364.13-1364.58" + wire width 16 \libresocsim_sdcore_crc16_checker_crc2_crcreg2 + attribute \src "build/ls180/gateware/ls180.v:1368.6-1368.50" + wire \libresocsim_sdcore_crc16_checker_crc2_enable + attribute \src "build/ls180/gateware/ls180.v:1365.12-1365.53" + wire width 2 \libresocsim_sdcore_crc16_checker_crc2_val + attribute \src "build/ls180/gateware/ls180.v:1374.5-1374.46" + wire \libresocsim_sdcore_crc16_checker_crc3_clr + attribute \src "build/ls180/gateware/ls180.v:1373.12-1373.53" + wire width 16 \libresocsim_sdcore_crc16_checker_crc3_crc + attribute \src "build/ls180/gateware/ls180.v:1369.12-1369.57" + wire width 16 \libresocsim_sdcore_crc16_checker_crc3_crcreg0 + attribute \src "build/ls180/gateware/ls180.v:1370.13-1370.58" + wire width 16 \libresocsim_sdcore_crc16_checker_crc3_crcreg1 + attribute \src "build/ls180/gateware/ls180.v:1371.13-1371.58" + wire width 16 \libresocsim_sdcore_crc16_checker_crc3_crcreg2 + attribute \src "build/ls180/gateware/ls180.v:1375.6-1375.50" + wire \libresocsim_sdcore_crc16_checker_crc3_enable + attribute \src "build/ls180/gateware/ls180.v:1372.12-1372.53" + wire width 2 \libresocsim_sdcore_crc16_checker_crc3_val + attribute \src "build/ls180/gateware/ls180.v:1376.12-1376.52" + wire width 16 \libresocsim_sdcore_crc16_checker_crctmp0 + attribute \src "build/ls180/gateware/ls180.v:1377.12-1377.52" + wire width 16 \libresocsim_sdcore_crc16_checker_crctmp1 + attribute \src "build/ls180/gateware/ls180.v:1378.12-1378.52" + wire width 16 \libresocsim_sdcore_crc16_checker_crctmp2 + attribute \src "build/ls180/gateware/ls180.v:1379.12-1379.52" + wire width 16 \libresocsim_sdcore_crc16_checker_crctmp3 + attribute \src "build/ls180/gateware/ls180.v:1381.12-1381.50" + wire width 16 \libresocsim_sdcore_crc16_checker_fifo0 + attribute \src "build/ls180/gateware/ls180.v:1382.12-1382.50" + wire width 16 \libresocsim_sdcore_crc16_checker_fifo1 + attribute \src "build/ls180/gateware/ls180.v:1383.12-1383.50" + wire width 16 \libresocsim_sdcore_crc16_checker_fifo2 + attribute \src "build/ls180/gateware/ls180.v:1384.12-1384.50" + wire width 16 \libresocsim_sdcore_crc16_checker_fifo3 + attribute \src "build/ls180/gateware/ls180.v:1338.5-1338.48" + wire \libresocsim_sdcore_crc16_checker_sink_first + attribute \src "build/ls180/gateware/ls180.v:1339.5-1339.47" + wire \libresocsim_sdcore_crc16_checker_sink_last + attribute \src "build/ls180/gateware/ls180.v:1340.11-1340.61" + wire width 8 \libresocsim_sdcore_crc16_checker_sink_payload_data + attribute \src "build/ls180/gateware/ls180.v:1337.5-1337.48" + wire \libresocsim_sdcore_crc16_checker_sink_ready + attribute \src "build/ls180/gateware/ls180.v:1336.5-1336.48" + wire \libresocsim_sdcore_crc16_checker_sink_valid + attribute \src "build/ls180/gateware/ls180.v:1343.5-1343.50" + wire \libresocsim_sdcore_crc16_checker_source_first + attribute \src "build/ls180/gateware/ls180.v:1344.6-1344.50" + wire \libresocsim_sdcore_crc16_checker_source_last + attribute \src "build/ls180/gateware/ls180.v:1345.12-1345.64" + wire width 8 \libresocsim_sdcore_crc16_checker_source_payload_data + attribute \src "build/ls180/gateware/ls180.v:1342.6-1342.51" + wire \libresocsim_sdcore_crc16_checker_source_ready + attribute \src "build/ls180/gateware/ls180.v:1341.5-1341.50" + wire \libresocsim_sdcore_crc16_checker_source_valid + attribute \src "build/ls180/gateware/ls180.v:1346.11-1346.47" + wire width 8 \libresocsim_sdcore_crc16_checker_val + attribute \src "build/ls180/gateware/ls180.v:1380.5-1380.43" + wire \libresocsim_sdcore_crc16_checker_valid + attribute \src "build/ls180/gateware/ls180.v:1303.11-1303.48" + wire width 3 \libresocsim_sdcore_crc16_inserter_cnt + attribute \src "build/ls180/gateware/ls180.v:1709.11-1709.87" + wire width 3 \libresocsim_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value4 + attribute \src "build/ls180/gateware/ls180.v:1710.5-1710.84" + wire \libresocsim_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value_ce4 + attribute \src "build/ls180/gateware/ls180.v:1309.6-1309.48" + wire \libresocsim_sdcore_crc16_inserter_crc0_clr + attribute \src "build/ls180/gateware/ls180.v:1308.12-1308.54" + wire width 16 \libresocsim_sdcore_crc16_inserter_crc0_crc + attribute \src "build/ls180/gateware/ls180.v:1304.12-1304.58" + wire width 16 \libresocsim_sdcore_crc16_inserter_crc0_crcreg0 + attribute \src "build/ls180/gateware/ls180.v:1305.13-1305.59" + wire width 16 \libresocsim_sdcore_crc16_inserter_crc0_crcreg1 + attribute \src "build/ls180/gateware/ls180.v:1306.13-1306.59" + wire width 16 \libresocsim_sdcore_crc16_inserter_crc0_crcreg2 + attribute \src "build/ls180/gateware/ls180.v:1310.6-1310.51" + wire \libresocsim_sdcore_crc16_inserter_crc0_enable + attribute \src "build/ls180/gateware/ls180.v:1307.12-1307.54" + wire width 2 \libresocsim_sdcore_crc16_inserter_crc0_val + attribute \src "build/ls180/gateware/ls180.v:1316.6-1316.48" + wire \libresocsim_sdcore_crc16_inserter_crc1_clr + attribute \src "build/ls180/gateware/ls180.v:1315.12-1315.54" + wire width 16 \libresocsim_sdcore_crc16_inserter_crc1_crc + attribute \src "build/ls180/gateware/ls180.v:1311.12-1311.58" + wire width 16 \libresocsim_sdcore_crc16_inserter_crc1_crcreg0 + attribute \src "build/ls180/gateware/ls180.v:1312.13-1312.59" + wire width 16 \libresocsim_sdcore_crc16_inserter_crc1_crcreg1 + attribute \src "build/ls180/gateware/ls180.v:1313.13-1313.59" + wire width 16 \libresocsim_sdcore_crc16_inserter_crc1_crcreg2 + attribute \src "build/ls180/gateware/ls180.v:1317.6-1317.51" + wire \libresocsim_sdcore_crc16_inserter_crc1_enable + attribute \src "build/ls180/gateware/ls180.v:1314.12-1314.54" + wire width 2 \libresocsim_sdcore_crc16_inserter_crc1_val + attribute \src "build/ls180/gateware/ls180.v:1323.6-1323.48" + wire \libresocsim_sdcore_crc16_inserter_crc2_clr + attribute \src "build/ls180/gateware/ls180.v:1322.12-1322.54" + wire width 16 \libresocsim_sdcore_crc16_inserter_crc2_crc + attribute \src "build/ls180/gateware/ls180.v:1318.12-1318.58" + wire width 16 \libresocsim_sdcore_crc16_inserter_crc2_crcreg0 + attribute \src "build/ls180/gateware/ls180.v:1319.13-1319.59" + wire width 16 \libresocsim_sdcore_crc16_inserter_crc2_crcreg1 + attribute \src "build/ls180/gateware/ls180.v:1320.13-1320.59" + wire width 16 \libresocsim_sdcore_crc16_inserter_crc2_crcreg2 + attribute \src "build/ls180/gateware/ls180.v:1324.6-1324.51" + wire \libresocsim_sdcore_crc16_inserter_crc2_enable + attribute \src "build/ls180/gateware/ls180.v:1321.12-1321.54" + wire width 2 \libresocsim_sdcore_crc16_inserter_crc2_val + attribute \src "build/ls180/gateware/ls180.v:1330.6-1330.48" + wire \libresocsim_sdcore_crc16_inserter_crc3_clr + attribute \src "build/ls180/gateware/ls180.v:1329.12-1329.54" + wire width 16 \libresocsim_sdcore_crc16_inserter_crc3_crc + attribute \src "build/ls180/gateware/ls180.v:1325.12-1325.58" + wire width 16 \libresocsim_sdcore_crc16_inserter_crc3_crcreg0 + attribute \src "build/ls180/gateware/ls180.v:1326.13-1326.59" + wire width 16 \libresocsim_sdcore_crc16_inserter_crc3_crcreg1 + attribute \src "build/ls180/gateware/ls180.v:1327.13-1327.59" + wire width 16 \libresocsim_sdcore_crc16_inserter_crc3_crcreg2 + attribute \src "build/ls180/gateware/ls180.v:1331.6-1331.51" + wire \libresocsim_sdcore_crc16_inserter_crc3_enable + attribute \src "build/ls180/gateware/ls180.v:1328.12-1328.54" + wire width 2 \libresocsim_sdcore_crc16_inserter_crc3_val + attribute \src "build/ls180/gateware/ls180.v:1332.12-1332.53" + wire width 16 \libresocsim_sdcore_crc16_inserter_crctmp0 + attribute \src "build/ls180/gateware/ls180.v:1701.12-1701.92" + wire width 16 \libresocsim_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value0 + attribute \src "build/ls180/gateware/ls180.v:1702.5-1702.88" + wire \libresocsim_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value_ce0 + attribute \src "build/ls180/gateware/ls180.v:1333.12-1333.53" + wire width 16 \libresocsim_sdcore_crc16_inserter_crctmp1 + attribute \src "build/ls180/gateware/ls180.v:1703.12-1703.92" + wire width 16 \libresocsim_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value1 + attribute \src "build/ls180/gateware/ls180.v:1704.5-1704.88" + wire \libresocsim_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value_ce1 + attribute \src "build/ls180/gateware/ls180.v:1334.12-1334.53" + wire width 16 \libresocsim_sdcore_crc16_inserter_crctmp2 + attribute \src "build/ls180/gateware/ls180.v:1705.12-1705.92" + wire width 16 \libresocsim_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value2 + attribute \src "build/ls180/gateware/ls180.v:1706.5-1706.88" + wire \libresocsim_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value_ce2 + attribute \src "build/ls180/gateware/ls180.v:1335.12-1335.53" + wire width 16 \libresocsim_sdcore_crc16_inserter_crctmp3 + attribute \src "build/ls180/gateware/ls180.v:1707.12-1707.92" + wire width 16 \libresocsim_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value3 + attribute \src "build/ls180/gateware/ls180.v:1708.5-1708.88" + wire \libresocsim_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value_ce3 + attribute \src "build/ls180/gateware/ls180.v:1295.6-1295.50" + wire \libresocsim_sdcore_crc16_inserter_sink_first + attribute \src "build/ls180/gateware/ls180.v:1296.6-1296.49" + wire \libresocsim_sdcore_crc16_inserter_sink_last + attribute \src "build/ls180/gateware/ls180.v:1297.12-1297.63" + wire width 8 \libresocsim_sdcore_crc16_inserter_sink_payload_data + attribute \src "build/ls180/gateware/ls180.v:1294.5-1294.49" + wire \libresocsim_sdcore_crc16_inserter_sink_ready + attribute \src "build/ls180/gateware/ls180.v:1293.6-1293.50" + wire \libresocsim_sdcore_crc16_inserter_sink_valid + attribute \src "build/ls180/gateware/ls180.v:1300.5-1300.51" + wire \libresocsim_sdcore_crc16_inserter_source_first + attribute \src "build/ls180/gateware/ls180.v:1301.5-1301.50" + wire \libresocsim_sdcore_crc16_inserter_source_last + attribute \src "build/ls180/gateware/ls180.v:1302.11-1302.64" + wire width 8 \libresocsim_sdcore_crc16_inserter_source_payload_data + attribute \src "build/ls180/gateware/ls180.v:1299.5-1299.51" + wire \libresocsim_sdcore_crc16_inserter_source_ready + attribute \src "build/ls180/gateware/ls180.v:1298.5-1298.51" + wire \libresocsim_sdcore_crc16_inserter_source_valid + attribute \src "build/ls180/gateware/ls180.v:1291.6-1291.42" + wire \libresocsim_sdcore_crc7_inserter_clr + attribute \src "build/ls180/gateware/ls180.v:1290.11-1290.47" + wire width 7 \libresocsim_sdcore_crc7_inserter_crc + attribute \src "build/ls180/gateware/ls180.v:1248.11-1248.51" + wire width 7 \libresocsim_sdcore_crc7_inserter_crcreg0 + attribute \src "build/ls180/gateware/ls180.v:1249.12-1249.52" + wire width 7 \libresocsim_sdcore_crc7_inserter_crcreg1 + attribute \src "build/ls180/gateware/ls180.v:1258.12-1258.53" + wire width 7 \libresocsim_sdcore_crc7_inserter_crcreg10 + attribute \src "build/ls180/gateware/ls180.v:1259.12-1259.53" + wire width 7 \libresocsim_sdcore_crc7_inserter_crcreg11 + attribute \src "build/ls180/gateware/ls180.v:1260.12-1260.53" + wire width 7 \libresocsim_sdcore_crc7_inserter_crcreg12 + attribute \src "build/ls180/gateware/ls180.v:1261.12-1261.53" + wire width 7 \libresocsim_sdcore_crc7_inserter_crcreg13 + attribute \src "build/ls180/gateware/ls180.v:1262.12-1262.53" + wire width 7 \libresocsim_sdcore_crc7_inserter_crcreg14 + attribute \src "build/ls180/gateware/ls180.v:1263.12-1263.53" + wire width 7 \libresocsim_sdcore_crc7_inserter_crcreg15 + attribute \src "build/ls180/gateware/ls180.v:1264.12-1264.53" + wire width 7 \libresocsim_sdcore_crc7_inserter_crcreg16 + attribute \src "build/ls180/gateware/ls180.v:1265.12-1265.53" + wire width 7 \libresocsim_sdcore_crc7_inserter_crcreg17 + attribute \src "build/ls180/gateware/ls180.v:1266.12-1266.53" + wire width 7 \libresocsim_sdcore_crc7_inserter_crcreg18 + attribute \src "build/ls180/gateware/ls180.v:1267.12-1267.53" + wire width 7 \libresocsim_sdcore_crc7_inserter_crcreg19 + attribute \src "build/ls180/gateware/ls180.v:1250.12-1250.52" + wire width 7 \libresocsim_sdcore_crc7_inserter_crcreg2 + attribute \src "build/ls180/gateware/ls180.v:1268.12-1268.53" + wire width 7 \libresocsim_sdcore_crc7_inserter_crcreg20 + attribute \src "build/ls180/gateware/ls180.v:1269.12-1269.53" + wire width 7 \libresocsim_sdcore_crc7_inserter_crcreg21 + attribute \src "build/ls180/gateware/ls180.v:1270.12-1270.53" + wire width 7 \libresocsim_sdcore_crc7_inserter_crcreg22 + attribute \src "build/ls180/gateware/ls180.v:1271.12-1271.53" + wire width 7 \libresocsim_sdcore_crc7_inserter_crcreg23 + attribute \src "build/ls180/gateware/ls180.v:1272.12-1272.53" + wire width 7 \libresocsim_sdcore_crc7_inserter_crcreg24 + attribute \src "build/ls180/gateware/ls180.v:1273.12-1273.53" + wire width 7 \libresocsim_sdcore_crc7_inserter_crcreg25 + attribute \src "build/ls180/gateware/ls180.v:1274.12-1274.53" + wire width 7 \libresocsim_sdcore_crc7_inserter_crcreg26 + attribute \src "build/ls180/gateware/ls180.v:1275.12-1275.53" + wire width 7 \libresocsim_sdcore_crc7_inserter_crcreg27 + attribute \src "build/ls180/gateware/ls180.v:1276.12-1276.53" + wire width 7 \libresocsim_sdcore_crc7_inserter_crcreg28 + attribute \src "build/ls180/gateware/ls180.v:1277.12-1277.53" + wire width 7 \libresocsim_sdcore_crc7_inserter_crcreg29 + attribute \src "build/ls180/gateware/ls180.v:1251.12-1251.52" + wire width 7 \libresocsim_sdcore_crc7_inserter_crcreg3 + attribute \src "build/ls180/gateware/ls180.v:1278.12-1278.53" + wire width 7 \libresocsim_sdcore_crc7_inserter_crcreg30 + attribute \src "build/ls180/gateware/ls180.v:1279.12-1279.53" + wire width 7 \libresocsim_sdcore_crc7_inserter_crcreg31 + attribute \src "build/ls180/gateware/ls180.v:1280.12-1280.53" + wire width 7 \libresocsim_sdcore_crc7_inserter_crcreg32 + attribute \src "build/ls180/gateware/ls180.v:1281.12-1281.53" + wire width 7 \libresocsim_sdcore_crc7_inserter_crcreg33 + attribute \src "build/ls180/gateware/ls180.v:1282.12-1282.53" + wire width 7 \libresocsim_sdcore_crc7_inserter_crcreg34 + attribute \src "build/ls180/gateware/ls180.v:1283.12-1283.53" + wire width 7 \libresocsim_sdcore_crc7_inserter_crcreg35 + attribute \src "build/ls180/gateware/ls180.v:1284.12-1284.53" + wire width 7 \libresocsim_sdcore_crc7_inserter_crcreg36 + attribute \src "build/ls180/gateware/ls180.v:1285.12-1285.53" + wire width 7 \libresocsim_sdcore_crc7_inserter_crcreg37 + attribute \src "build/ls180/gateware/ls180.v:1286.12-1286.53" + wire width 7 \libresocsim_sdcore_crc7_inserter_crcreg38 + attribute \src "build/ls180/gateware/ls180.v:1287.12-1287.53" + wire width 7 \libresocsim_sdcore_crc7_inserter_crcreg39 + attribute \src "build/ls180/gateware/ls180.v:1252.12-1252.52" + wire width 7 \libresocsim_sdcore_crc7_inserter_crcreg4 + attribute \src "build/ls180/gateware/ls180.v:1288.12-1288.53" + wire width 7 \libresocsim_sdcore_crc7_inserter_crcreg40 + attribute \src "build/ls180/gateware/ls180.v:1253.12-1253.52" + wire width 7 \libresocsim_sdcore_crc7_inserter_crcreg5 + attribute \src "build/ls180/gateware/ls180.v:1254.12-1254.52" + wire width 7 \libresocsim_sdcore_crc7_inserter_crcreg6 + attribute \src "build/ls180/gateware/ls180.v:1255.12-1255.52" + wire width 7 \libresocsim_sdcore_crc7_inserter_crcreg7 + attribute \src "build/ls180/gateware/ls180.v:1256.12-1256.52" + wire width 7 \libresocsim_sdcore_crc7_inserter_crcreg8 + attribute \src "build/ls180/gateware/ls180.v:1257.12-1257.52" + wire width 7 \libresocsim_sdcore_crc7_inserter_crcreg9 + attribute \src "build/ls180/gateware/ls180.v:1292.6-1292.45" + wire \libresocsim_sdcore_crc7_inserter_enable + attribute \src "build/ls180/gateware/ls180.v:1289.13-1289.49" + wire width 40 \libresocsim_sdcore_crc7_inserter_val + attribute \src "build/ls180/gateware/ls180.v:1391.12-1391.41" + wire width 32 \libresocsim_sdcore_data_count + attribute \src "build/ls180/gateware/ls180.v:1719.12-1719.64" + wire width 32 \libresocsim_sdcore_data_count_sdcore_fsm_next_value3 + attribute \src "build/ls180/gateware/ls180.v:1720.5-1720.60" + wire \libresocsim_sdcore_data_count_sdcore_fsm_next_value_ce3 + attribute \src "build/ls180/gateware/ls180.v:1392.5-1392.33" + wire \libresocsim_sdcore_data_done + attribute \src "build/ls180/gateware/ls180.v:1715.5-1715.56" + wire \libresocsim_sdcore_data_done_sdcore_fsm_next_value1 + attribute \src "build/ls180/gateware/ls180.v:1716.5-1716.59" + wire \libresocsim_sdcore_data_done_sdcore_fsm_next_value_ce1 + attribute \src "build/ls180/gateware/ls180.v:1393.5-1393.34" + wire \libresocsim_sdcore_data_error + attribute \src "build/ls180/gateware/ls180.v:1725.5-1725.57" + wire \libresocsim_sdcore_data_error_sdcore_fsm_next_value6 + attribute \src "build/ls180/gateware/ls180.v:1726.5-1726.60" + wire \libresocsim_sdcore_data_error_sdcore_fsm_next_value_ce6 + attribute \src "build/ls180/gateware/ls180.v:1242.12-1242.48" + wire width 4 \libresocsim_sdcore_data_event_status + attribute \src "build/ls180/gateware/ls180.v:1243.6-1243.38" + wire \libresocsim_sdcore_data_event_we + attribute \src "build/ls180/gateware/ls180.v:1394.5-1394.36" + wire \libresocsim_sdcore_data_timeout + attribute \src "build/ls180/gateware/ls180.v:1727.5-1727.59" + wire \libresocsim_sdcore_data_timeout_sdcore_fsm_next_value7 + attribute \src "build/ls180/gateware/ls180.v:1728.5-1728.62" + wire \libresocsim_sdcore_data_timeout_sdcore_fsm_next_value_ce7 + attribute \src "build/ls180/gateware/ls180.v:1390.12-1390.40" + wire width 2 \libresocsim_sdcore_data_type + attribute \src "build/ls180/gateware/ls180.v:1222.6-1222.40" + wire \libresocsim_sdcore_sink_sink_first + attribute \src "build/ls180/gateware/ls180.v:1223.6-1223.39" + wire \libresocsim_sdcore_sink_sink_last + attribute \src "build/ls180/gateware/ls180.v:1224.12-1224.53" + wire width 8 \libresocsim_sdcore_sink_sink_payload_data + attribute \src "build/ls180/gateware/ls180.v:1221.6-1221.40" + wire \libresocsim_sdcore_sink_sink_ready + attribute \src "build/ls180/gateware/ls180.v:1220.6-1220.40" + wire \libresocsim_sdcore_sink_sink_valid + attribute \src "build/ls180/gateware/ls180.v:1227.6-1227.44" + wire \libresocsim_sdcore_source_source_first + attribute \src "build/ls180/gateware/ls180.v:1228.6-1228.43" + wire \libresocsim_sdcore_source_source_last + attribute \src "build/ls180/gateware/ls180.v:1229.12-1229.57" + wire width 8 \libresocsim_sdcore_source_source_payload_data + attribute \src "build/ls180/gateware/ls180.v:1226.6-1226.44" + wire \libresocsim_sdcore_source_source_ready + attribute \src "build/ls180/gateware/ls180.v:1225.6-1225.44" + wire \libresocsim_sdcore_source_source_valid + attribute \src "build/ls180/gateware/ls180.v:1540.6-1540.45" + wire \libresocsim_sdmem2block_converter_first + attribute \src "build/ls180/gateware/ls180.v:1541.6-1541.44" + wire \libresocsim_sdmem2block_converter_last + attribute \src "build/ls180/gateware/ls180.v:1539.11-1539.48" + wire width 2 \libresocsim_sdmem2block_converter_mux + attribute \src "build/ls180/gateware/ls180.v:1530.6-1530.50" + wire \libresocsim_sdmem2block_converter_sink_first + attribute \src "build/ls180/gateware/ls180.v:1531.6-1531.49" + wire \libresocsim_sdmem2block_converter_sink_last + attribute \src "build/ls180/gateware/ls180.v:1532.13-1532.64" + wire width 32 \libresocsim_sdmem2block_converter_sink_payload_data + attribute \src "build/ls180/gateware/ls180.v:1529.6-1529.50" + wire \libresocsim_sdmem2block_converter_sink_ready + attribute \src "build/ls180/gateware/ls180.v:1528.6-1528.50" + wire \libresocsim_sdmem2block_converter_sink_valid + attribute \src "build/ls180/gateware/ls180.v:1535.6-1535.52" + wire \libresocsim_sdmem2block_converter_source_first + attribute \src "build/ls180/gateware/ls180.v:1536.6-1536.51" + wire \libresocsim_sdmem2block_converter_source_last + attribute \src "build/ls180/gateware/ls180.v:1537.11-1537.64" + wire width 8 \libresocsim_sdmem2block_converter_source_payload_data + attribute \src "build/ls180/gateware/ls180.v:1538.6-1538.72" + wire \libresocsim_sdmem2block_converter_source_payload_valid_token_count + attribute \src "build/ls180/gateware/ls180.v:1534.6-1534.52" + wire \libresocsim_sdmem2block_converter_source_ready + attribute \src "build/ls180/gateware/ls180.v:1533.6-1533.52" + wire \libresocsim_sdmem2block_converter_source_valid + attribute \src "build/ls180/gateware/ls180.v:1524.13-1524.45" + wire width 32 \libresocsim_sdmem2block_dma_base + attribute \src "build/ls180/gateware/ls180.v:1513.5-1513.40" + wire \libresocsim_sdmem2block_dma_base_re + attribute \src "build/ls180/gateware/ls180.v:1512.12-1512.52" + wire width 64 \libresocsim_sdmem2block_dma_base_storage + attribute \src "build/ls180/gateware/ls180.v:1511.12-1511.44" + wire width 32 \libresocsim_sdmem2block_dma_data + attribute \src "build/ls180/gateware/ls180.v:1737.12-1737.74" + wire width 32 \libresocsim_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value + attribute \src "build/ls180/gateware/ls180.v:1738.5-1738.70" + wire \libresocsim_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value_ce + attribute \src "build/ls180/gateware/ls180.v:1518.5-1518.44" + wire \libresocsim_sdmem2block_dma_done_status + attribute \src "build/ls180/gateware/ls180.v:1519.6-1519.41" + wire \libresocsim_sdmem2block_dma_done_we + attribute \src "build/ls180/gateware/ls180.v:1517.5-1517.42" + wire \libresocsim_sdmem2block_dma_enable_re + attribute \src "build/ls180/gateware/ls180.v:1516.5-1516.47" + wire \libresocsim_sdmem2block_dma_enable_storage + attribute \src "build/ls180/gateware/ls180.v:1526.13-1526.47" + wire width 32 \libresocsim_sdmem2block_dma_length + attribute \src "build/ls180/gateware/ls180.v:1515.5-1515.42" + wire \libresocsim_sdmem2block_dma_length_re + attribute \src "build/ls180/gateware/ls180.v:1514.12-1514.54" + wire width 32 \libresocsim_sdmem2block_dma_length_storage + attribute \src "build/ls180/gateware/ls180.v:1521.5-1521.40" + wire \libresocsim_sdmem2block_dma_loop_re + attribute \src "build/ls180/gateware/ls180.v:1520.5-1520.45" + wire \libresocsim_sdmem2block_dma_loop_storage + attribute \src "build/ls180/gateware/ls180.v:1525.12-1525.46" + wire width 32 \libresocsim_sdmem2block_dma_offset + attribute \src "build/ls180/gateware/ls180.v:1741.12-1741.86" + wire width 32 \libresocsim_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value + attribute \src "build/ls180/gateware/ls180.v:1742.5-1742.82" + wire \libresocsim_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value_ce + attribute \src "build/ls180/gateware/ls180.v:1522.13-1522.54" + wire width 32 \libresocsim_sdmem2block_dma_offset_status + attribute \src "build/ls180/gateware/ls180.v:1523.6-1523.43" + wire \libresocsim_sdmem2block_dma_offset_we + attribute \src "build/ls180/gateware/ls180.v:1527.6-1527.39" + wire \libresocsim_sdmem2block_dma_reset + attribute \src "build/ls180/gateware/ls180.v:1504.5-1504.42" + wire \libresocsim_sdmem2block_dma_sink_last + attribute \src "build/ls180/gateware/ls180.v:1505.12-1505.60" + wire width 32 \libresocsim_sdmem2block_dma_sink_payload_address + attribute \src "build/ls180/gateware/ls180.v:1503.5-1503.43" + wire \libresocsim_sdmem2block_dma_sink_ready + attribute \src "build/ls180/gateware/ls180.v:1502.5-1502.43" + wire \libresocsim_sdmem2block_dma_sink_valid + attribute \src "build/ls180/gateware/ls180.v:1508.5-1508.45" + wire \libresocsim_sdmem2block_dma_source_first + attribute \src "build/ls180/gateware/ls180.v:1509.5-1509.44" + wire \libresocsim_sdmem2block_dma_source_last + attribute \src "build/ls180/gateware/ls180.v:1510.12-1510.59" + wire width 32 \libresocsim_sdmem2block_dma_source_payload_data + attribute \src "build/ls180/gateware/ls180.v:1507.6-1507.46" + wire \libresocsim_sdmem2block_dma_source_ready + attribute \src "build/ls180/gateware/ls180.v:1506.5-1506.45" + wire \libresocsim_sdmem2block_dma_source_valid + attribute \src "build/ls180/gateware/ls180.v:1566.11-1566.47" + wire width 5 \libresocsim_sdmem2block_fifo_consume + attribute \src "build/ls180/gateware/ls180.v:1571.6-1571.42" + wire \libresocsim_sdmem2block_fifo_do_read + attribute \src "build/ls180/gateware/ls180.v:1575.6-1575.48" + wire \libresocsim_sdmem2block_fifo_fifo_in_first + attribute \src "build/ls180/gateware/ls180.v:1576.6-1576.47" + wire \libresocsim_sdmem2block_fifo_fifo_in_last + attribute \src "build/ls180/gateware/ls180.v:1574.12-1574.61" + wire width 8 \libresocsim_sdmem2block_fifo_fifo_in_payload_data + attribute \src "build/ls180/gateware/ls180.v:1578.6-1578.49" + wire \libresocsim_sdmem2block_fifo_fifo_out_first + attribute \src "build/ls180/gateware/ls180.v:1579.6-1579.48" + wire \libresocsim_sdmem2block_fifo_fifo_out_last + attribute \src "build/ls180/gateware/ls180.v:1577.12-1577.62" + wire width 8 \libresocsim_sdmem2block_fifo_fifo_out_payload_data + attribute \src "build/ls180/gateware/ls180.v:1563.11-1563.45" + wire width 6 \libresocsim_sdmem2block_fifo_level + attribute \src "build/ls180/gateware/ls180.v:1565.11-1565.47" + wire width 5 \libresocsim_sdmem2block_fifo_produce + attribute \src "build/ls180/gateware/ls180.v:1572.12-1572.51" + wire width 5 \libresocsim_sdmem2block_fifo_rdport_adr + attribute \src "build/ls180/gateware/ls180.v:1573.12-1573.53" + wire width 10 \libresocsim_sdmem2block_fifo_rdport_dat_r + attribute \src "build/ls180/gateware/ls180.v:1564.5-1564.41" + wire \libresocsim_sdmem2block_fifo_replace + attribute \src "build/ls180/gateware/ls180.v:1549.6-1549.45" + wire \libresocsim_sdmem2block_fifo_sink_first + attribute \src "build/ls180/gateware/ls180.v:1550.6-1550.44" + wire \libresocsim_sdmem2block_fifo_sink_last + attribute \src "build/ls180/gateware/ls180.v:1551.12-1551.58" + wire width 8 \libresocsim_sdmem2block_fifo_sink_payload_data + attribute \src "build/ls180/gateware/ls180.v:1548.6-1548.45" + wire \libresocsim_sdmem2block_fifo_sink_ready + attribute \src "build/ls180/gateware/ls180.v:1547.6-1547.45" + wire \libresocsim_sdmem2block_fifo_sink_valid + attribute \src "build/ls180/gateware/ls180.v:1554.6-1554.47" + wire \libresocsim_sdmem2block_fifo_source_first + attribute \src "build/ls180/gateware/ls180.v:1555.6-1555.46" + wire \libresocsim_sdmem2block_fifo_source_last + attribute \src "build/ls180/gateware/ls180.v:1556.12-1556.60" + wire width 8 \libresocsim_sdmem2block_fifo_source_payload_data + attribute \src "build/ls180/gateware/ls180.v:1553.6-1553.47" + wire \libresocsim_sdmem2block_fifo_source_ready + attribute \src "build/ls180/gateware/ls180.v:1552.6-1552.47" + wire \libresocsim_sdmem2block_fifo_source_valid + attribute \src "build/ls180/gateware/ls180.v:1561.12-1561.53" + wire width 10 \libresocsim_sdmem2block_fifo_syncfifo_din + attribute \src "build/ls180/gateware/ls180.v:1562.12-1562.54" + wire width 10 \libresocsim_sdmem2block_fifo_syncfifo_dout + attribute \src "build/ls180/gateware/ls180.v:1559.6-1559.46" + wire \libresocsim_sdmem2block_fifo_syncfifo_re + attribute \src "build/ls180/gateware/ls180.v:1560.6-1560.52" + wire \libresocsim_sdmem2block_fifo_syncfifo_readable + attribute \src "build/ls180/gateware/ls180.v:1557.6-1557.46" + wire \libresocsim_sdmem2block_fifo_syncfifo_we + attribute \src "build/ls180/gateware/ls180.v:1558.6-1558.52" + wire \libresocsim_sdmem2block_fifo_syncfifo_writable + attribute \src "build/ls180/gateware/ls180.v:1567.11-1567.50" + wire width 5 \libresocsim_sdmem2block_fifo_wrport_adr + attribute \src "build/ls180/gateware/ls180.v:1568.12-1568.53" + wire width 10 \libresocsim_sdmem2block_fifo_wrport_dat_r + attribute \src "build/ls180/gateware/ls180.v:1570.12-1570.53" + wire width 10 \libresocsim_sdmem2block_fifo_wrport_dat_w + attribute \src "build/ls180/gateware/ls180.v:1569.6-1569.44" + wire \libresocsim_sdmem2block_fifo_wrport_we + attribute \src "build/ls180/gateware/ls180.v:1499.6-1499.50" + wire \libresocsim_sdmem2block_source_source_first0 + attribute \src "build/ls180/gateware/ls180.v:1544.6-1544.50" + wire \libresocsim_sdmem2block_source_source_first1 + attribute \src "build/ls180/gateware/ls180.v:1500.6-1500.49" + wire \libresocsim_sdmem2block_source_source_last0 + attribute \src "build/ls180/gateware/ls180.v:1545.6-1545.49" + wire \libresocsim_sdmem2block_source_source_last1 + attribute \src "build/ls180/gateware/ls180.v:1501.12-1501.63" + wire width 8 \libresocsim_sdmem2block_source_source_payload_data0 + attribute \src "build/ls180/gateware/ls180.v:1546.12-1546.63" + wire width 8 \libresocsim_sdmem2block_source_source_payload_data1 + attribute \src "build/ls180/gateware/ls180.v:1498.6-1498.50" + wire \libresocsim_sdmem2block_source_source_ready0 + attribute \src "build/ls180/gateware/ls180.v:1543.6-1543.50" + wire \libresocsim_sdmem2block_source_source_ready1 + attribute \src "build/ls180/gateware/ls180.v:1497.6-1497.50" + wire \libresocsim_sdmem2block_source_source_valid0 + attribute \src "build/ls180/gateware/ls180.v:1542.6-1542.50" + wire \libresocsim_sdmem2block_source_source_valid1 + attribute \src "build/ls180/gateware/ls180.v:1213.6-1213.28" + wire \libresocsim_sdpads_clk + attribute \src "build/ls180/gateware/ls180.v:1214.5-1214.29" + wire \libresocsim_sdpads_cmd_i + attribute \src "build/ls180/gateware/ls180.v:1215.6-1215.30" + wire \libresocsim_sdpads_cmd_o + attribute \src "build/ls180/gateware/ls180.v:1216.6-1216.31" + wire \libresocsim_sdpads_cmd_oe + attribute \src "build/ls180/gateware/ls180.v:1217.11-1217.36" + wire width 4 \libresocsim_sdpads_data_i + attribute \src "build/ls180/gateware/ls180.v:1218.12-1218.37" + wire width 4 \libresocsim_sdpads_data_o + attribute \src "build/ls180/gateware/ls180.v:1219.6-1219.32" + wire \libresocsim_sdpads_data_oe + attribute \src "build/ls180/gateware/ls180.v:1600.6-1600.21" + wire \libresocsim_sel + attribute \src "build/ls180/gateware/ls180.v:1580.6-1580.24" + wire \libresocsim_start0 + attribute \src "build/ls180/gateware/ls180.v:1589.5-1589.23" + wire \libresocsim_start1 + attribute \src "build/ls180/gateware/ls180.v:942.6-942.24" + wire \libresocsim_status + attribute \src "build/ls180/gateware/ls180.v:1594.6-1594.31" + wire \libresocsim_status_status + attribute \src "build/ls180/gateware/ls180.v:1595.6-1595.27" + wire \libresocsim_status_we + attribute \src "build/ls180/gateware/ls180.v:1616.12-1616.31" + wire width 16 \libresocsim_storage + attribute \src "build/ls180/gateware/ls180.v:943.6-943.20" + wire \libresocsim_we + attribute \src "build/ls180/gateware/ls180.v:899.6-899.18" + wire \main_ack_cmd + attribute \src "build/ls180/gateware/ls180.v:901.6-901.20" + wire \main_ack_rdata + attribute \src "build/ls180/gateware/ls180.v:900.6-900.20" + wire \main_ack_wdata + attribute \src "build/ls180/gateware/ls180.v:914.12-914.29" + wire width 16 \main_clk_divider0 + attribute \src "build/ls180/gateware/ls180.v:936.12-936.29" + wire width 16 \main_clk_divider1 + attribute \src "build/ls180/gateware/ls180.v:931.5-931.20" + wire \main_clk_enable + attribute \src "build/ls180/gateware/ls180.v:938.6-938.19" + wire \main_clk_fall + attribute \src "build/ls180/gateware/ls180.v:937.6-937.19" + wire \main_clk_rise + attribute \src "build/ls180/gateware/ls180.v:897.5-897.22" + wire \main_cmd_consumed + attribute \src "build/ls180/gateware/ls180.v:918.5-918.20" + wire \main_control_re + attribute \src "build/ls180/gateware/ls180.v:917.12-917.32" + wire width 16 \main_control_storage + attribute \src "build/ls180/gateware/ls180.v:894.5-894.27" + wire \main_converter_counter + attribute \src "build/ls180/gateware/ls180.v:1661.5-1661.48" + wire \main_converter_counter_converter_next_value + attribute \src "build/ls180/gateware/ls180.v:1662.5-1662.51" + wire \main_converter_counter_converter_next_value_ce + attribute \src "build/ls180/gateware/ls180.v:896.12-896.32" + wire width 32 \main_converter_dat_r + attribute \src "build/ls180/gateware/ls180.v:895.6-895.26" + wire \main_converter_reset + attribute \src "build/ls180/gateware/ls180.v:893.5-893.24" + wire \main_converter_skip + attribute \src "build/ls180/gateware/ls180.v:933.11-933.21" + wire width 3 \main_count + attribute \src "build/ls180/gateware/ls180.v:1665.11-1665.43" + wire width 3 \main_count_spimaster0_next_value + attribute \src "build/ls180/gateware/ls180.v:1666.5-1666.40" + wire \main_count_spimaster0_next_value_ce + attribute \src "build/ls180/gateware/ls180.v:912.6-912.13" + wire \main_cs + attribute \src "build/ls180/gateware/ls180.v:932.5-932.19" + wire \main_cs_enable + attribute \src "build/ls180/gateware/ls180.v:928.5-928.15" + wire \main_cs_re + attribute \src "build/ls180/gateware/ls180.v:927.5-927.20" + wire \main_cs_storage + attribute \src "build/ls180/gateware/ls180.v:323.6-323.23" + wire \main_dfi_p0_act_n + attribute \src "build/ls180/gateware/ls180.v:314.13-314.32" + wire width 13 \main_dfi_p0_address + attribute \src "build/ls180/gateware/ls180.v:315.12-315.28" + wire width 2 \main_dfi_p0_bank + attribute \src "build/ls180/gateware/ls180.v:316.6-316.23" + wire \main_dfi_p0_cas_n + attribute \src "build/ls180/gateware/ls180.v:320.6-320.21" + wire \main_dfi_p0_cke + attribute \src "build/ls180/gateware/ls180.v:317.6-317.22" + wire \main_dfi_p0_cs_n + attribute \src "build/ls180/gateware/ls180.v:321.6-321.21" + wire \main_dfi_p0_odt + attribute \src "build/ls180/gateware/ls180.v:318.6-318.23" + wire \main_dfi_p0_ras_n + attribute \src "build/ls180/gateware/ls180.v:328.12-328.30" + wire width 16 \main_dfi_p0_rddata + attribute \src "build/ls180/gateware/ls180.v:327.6-327.27" + wire \main_dfi_p0_rddata_en + attribute \src "build/ls180/gateware/ls180.v:329.5-329.29" + wire \main_dfi_p0_rddata_valid + attribute \src "build/ls180/gateware/ls180.v:322.6-322.25" + wire \main_dfi_p0_reset_n + attribute \src "build/ls180/gateware/ls180.v:319.6-319.22" + wire \main_dfi_p0_we_n + attribute \src "build/ls180/gateware/ls180.v:324.13-324.31" + wire width 16 \main_dfi_p0_wrdata + attribute \src "build/ls180/gateware/ls180.v:325.6-325.27" + wire \main_dfi_p0_wrdata_en + attribute \src "build/ls180/gateware/ls180.v:326.12-326.35" + wire width 2 \main_dfi_p0_wrdata_mask + attribute \src "build/ls180/gateware/ls180.v:908.5-908.15" + wire \main_done0 + attribute \src "build/ls180/gateware/ls180.v:919.6-919.16" + wire \main_done1 + attribute \src "build/ls180/gateware/ls180.v:902.12-902.31" + wire width 8 \main_gpio_in_status + attribute \src "build/ls180/gateware/ls180.v:903.6-903.21" + wire \main_gpio_in_we + attribute \src "build/ls180/gateware/ls180.v:904.12-904.32" + wire width 8 \main_gpio_out_status + attribute \src "build/ls180/gateware/ls180.v:905.6-905.22" + wire \main_gpio_out_we + attribute \src "build/ls180/gateware/ls180.v:313.5-313.17" + wire \main_int_rst + attribute \src "build/ls180/gateware/ls180.v:909.5-909.13" + wire \main_irq + attribute \src "build/ls180/gateware/ls180.v:907.12-907.24" + wire width 8 \main_length0 + attribute \src "build/ls180/gateware/ls180.v:916.12-916.24" + wire width 8 \main_length1 + attribute \src "build/ls180/gateware/ls180.v:137.13-137.33" + wire width 16 \main_libresocsim_adr + attribute \src "build/ls180/gateware/ls180.v:108.5-108.40" + wire \main_libresocsim_converter0_counter + attribute \src "build/ls180/gateware/ls180.v:1620.5-1620.62" + wire \main_libresocsim_converter0_counter_converter0_next_value + attribute \src "build/ls180/gateware/ls180.v:1621.5-1621.65" + wire \main_libresocsim_converter0_counter_converter0_next_value_ce + attribute \src "build/ls180/gateware/ls180.v:110.12-110.45" + wire width 64 \main_libresocsim_converter0_dat_r + attribute \src "build/ls180/gateware/ls180.v:109.6-109.39" + wire \main_libresocsim_converter0_reset + attribute \src "build/ls180/gateware/ls180.v:107.5-107.37" + wire \main_libresocsim_converter0_skip + attribute \src "build/ls180/gateware/ls180.v:123.5-123.40" + wire \main_libresocsim_converter1_counter + attribute \src "build/ls180/gateware/ls180.v:1624.5-1624.62" + wire \main_libresocsim_converter1_counter_converter1_next_value + attribute \src "build/ls180/gateware/ls180.v:1625.5-1625.65" + wire \main_libresocsim_converter1_counter_converter1_next_value_ce + attribute \src "build/ls180/gateware/ls180.v:125.12-125.45" + wire width 64 \main_libresocsim_converter1_dat_r + attribute \src "build/ls180/gateware/ls180.v:124.6-124.39" + wire \main_libresocsim_converter1_reset + attribute \src "build/ls180/gateware/ls180.v:122.5-122.37" + wire \main_libresocsim_converter1_skip + attribute \src "build/ls180/gateware/ls180.v:138.13-138.35" + wire width 32 \main_libresocsim_dat_r + attribute \src "build/ls180/gateware/ls180.v:140.13-140.35" + wire width 32 \main_libresocsim_dat_w + attribute \src "build/ls180/gateware/ls180.v:102.6-102.57" + wire \main_libresocsim_interface0_converted_interface_ack + attribute \src "build/ls180/gateware/ls180.v:96.12-96.63" + wire width 30 \main_libresocsim_interface0_converted_interface_adr + attribute \src "build/ls180/gateware/ls180.v:105.11-105.62" + wire width 2 \main_libresocsim_interface0_converted_interface_bte + attribute \src "build/ls180/gateware/ls180.v:104.11-104.62" + wire width 3 \main_libresocsim_interface0_converted_interface_cti + attribute \src "build/ls180/gateware/ls180.v:100.5-100.56" + wire \main_libresocsim_interface0_converted_interface_cyc + attribute \src "build/ls180/gateware/ls180.v:98.13-98.66" + wire width 32 \main_libresocsim_interface0_converted_interface_dat_r + attribute \src "build/ls180/gateware/ls180.v:97.12-97.65" + wire width 32 \main_libresocsim_interface0_converted_interface_dat_w + attribute \src "build/ls180/gateware/ls180.v:106.6-106.57" + wire \main_libresocsim_interface0_converted_interface_err + attribute \src "build/ls180/gateware/ls180.v:99.11-99.62" + wire width 4 \main_libresocsim_interface0_converted_interface_sel + attribute \src "build/ls180/gateware/ls180.v:101.5-101.56" + wire \main_libresocsim_interface0_converted_interface_stb + attribute \src "build/ls180/gateware/ls180.v:103.5-103.55" + wire \main_libresocsim_interface0_converted_interface_we + attribute \src "build/ls180/gateware/ls180.v:117.6-117.57" + wire \main_libresocsim_interface1_converted_interface_ack + attribute \src "build/ls180/gateware/ls180.v:111.12-111.63" + wire width 30 \main_libresocsim_interface1_converted_interface_adr + attribute \src "build/ls180/gateware/ls180.v:120.11-120.62" + wire width 2 \main_libresocsim_interface1_converted_interface_bte + attribute \src "build/ls180/gateware/ls180.v:119.11-119.62" + wire width 3 \main_libresocsim_interface1_converted_interface_cti + attribute \src "build/ls180/gateware/ls180.v:115.5-115.56" + wire \main_libresocsim_interface1_converted_interface_cyc + attribute \src "build/ls180/gateware/ls180.v:113.13-113.66" + wire width 32 \main_libresocsim_interface1_converted_interface_dat_r + attribute \src "build/ls180/gateware/ls180.v:112.12-112.65" + wire width 32 \main_libresocsim_interface1_converted_interface_dat_w + attribute \src "build/ls180/gateware/ls180.v:121.6-121.57" + wire \main_libresocsim_interface1_converted_interface_err + attribute \src "build/ls180/gateware/ls180.v:114.11-114.62" + wire width 4 \main_libresocsim_interface1_converted_interface_sel + attribute \src "build/ls180/gateware/ls180.v:116.5-116.56" + wire \main_libresocsim_interface1_converted_interface_stb + attribute \src "build/ls180/gateware/ls180.v:118.5-118.55" + wire \main_libresocsim_interface1_converted_interface_we + attribute \src "build/ls180/gateware/ls180.v:94.6-94.32" + wire \main_libresocsim_libresoc0 + attribute \src "build/ls180/gateware/ls180.v:95.6-95.32" + wire \main_libresocsim_libresoc1 + attribute \src "build/ls180/gateware/ls180.v:50.5-50.39" + wire \main_libresocsim_libresoc_dbus_ack + attribute \src "build/ls180/gateware/ls180.v:44.13-44.47" + wire width 29 \main_libresocsim_libresoc_dbus_adr + attribute \src "build/ls180/gateware/ls180.v:53.12-53.46" + wire width 2 \main_libresocsim_libresoc_dbus_bte + attribute \src "build/ls180/gateware/ls180.v:52.12-52.46" + wire width 3 \main_libresocsim_libresoc_dbus_cti + attribute \src "build/ls180/gateware/ls180.v:48.6-48.40" + wire \main_libresocsim_libresoc_dbus_cyc + attribute \src "build/ls180/gateware/ls180.v:46.13-46.49" + wire width 64 \main_libresocsim_libresoc_dbus_dat_r + attribute \src "build/ls180/gateware/ls180.v:45.13-45.49" + wire width 64 \main_libresocsim_libresoc_dbus_dat_w + attribute \src "build/ls180/gateware/ls180.v:54.5-54.39" + wire \main_libresocsim_libresoc_dbus_err + attribute \src "build/ls180/gateware/ls180.v:47.12-47.46" + wire width 8 \main_libresocsim_libresoc_dbus_sel + attribute \src "build/ls180/gateware/ls180.v:49.6-49.40" + wire \main_libresocsim_libresoc_dbus_stb + attribute \src "build/ls180/gateware/ls180.v:51.6-51.39" + wire \main_libresocsim_libresoc_dbus_we + attribute \src "build/ls180/gateware/ls180.v:92.6-92.39" + wire \main_libresocsim_libresoc_dmi_ack + attribute \src "build/ls180/gateware/ls180.v:88.11-88.45" + wire width 4 \main_libresocsim_libresoc_dmi_addr + attribute \src "build/ls180/gateware/ls180.v:89.12-89.45" + wire width 64 \main_libresocsim_libresoc_dmi_din + attribute \src "build/ls180/gateware/ls180.v:90.13-90.47" + wire width 64 \main_libresocsim_libresoc_dmi_dout + attribute \src "build/ls180/gateware/ls180.v:93.5-93.38" + wire \main_libresocsim_libresoc_dmi_req + attribute \src "build/ls180/gateware/ls180.v:91.5-91.37" + wire \main_libresocsim_libresoc_dmi_wr + attribute \src "build/ls180/gateware/ls180.v:61.5-61.39" + wire \main_libresocsim_libresoc_ibus_ack + attribute \src "build/ls180/gateware/ls180.v:55.13-55.47" + wire width 29 \main_libresocsim_libresoc_ibus_adr + attribute \src "build/ls180/gateware/ls180.v:64.12-64.46" + wire width 2 \main_libresocsim_libresoc_ibus_bte + attribute \src "build/ls180/gateware/ls180.v:63.12-63.46" + wire width 3 \main_libresocsim_libresoc_ibus_cti + attribute \src "build/ls180/gateware/ls180.v:59.6-59.40" + wire \main_libresocsim_libresoc_ibus_cyc + attribute \src "build/ls180/gateware/ls180.v:57.13-57.49" + wire width 64 \main_libresocsim_libresoc_ibus_dat_r + attribute \src "build/ls180/gateware/ls180.v:56.13-56.49" + wire width 64 \main_libresocsim_libresoc_ibus_dat_w + attribute \src "build/ls180/gateware/ls180.v:65.5-65.39" + wire \main_libresocsim_libresoc_ibus_err + attribute \src "build/ls180/gateware/ls180.v:58.12-58.46" + wire width 8 \main_libresocsim_libresoc_ibus_sel + attribute \src "build/ls180/gateware/ls180.v:60.6-60.40" + wire \main_libresocsim_libresoc_ibus_stb + attribute \src "build/ls180/gateware/ls180.v:62.6-62.39" + wire \main_libresocsim_libresoc_ibus_we + attribute \src "build/ls180/gateware/ls180.v:43.12-43.47" + wire width 16 \main_libresocsim_libresoc_interrupt + attribute \src "build/ls180/gateware/ls180.v:42.6-42.37" + wire \main_libresocsim_libresoc_reset + attribute \src "build/ls180/gateware/ls180.v:72.5-72.43" + wire \main_libresocsim_libresoc_xics_icp_ack + attribute \src "build/ls180/gateware/ls180.v:66.13-66.51" + wire width 30 \main_libresocsim_libresoc_xics_icp_adr + attribute \src "build/ls180/gateware/ls180.v:75.12-75.50" + wire width 2 \main_libresocsim_libresoc_xics_icp_bte + attribute \src "build/ls180/gateware/ls180.v:74.12-74.50" + wire width 3 \main_libresocsim_libresoc_xics_icp_cti + attribute \src "build/ls180/gateware/ls180.v:70.6-70.44" + wire \main_libresocsim_libresoc_xics_icp_cyc + attribute \src "build/ls180/gateware/ls180.v:68.12-68.52" + wire width 32 \main_libresocsim_libresoc_xics_icp_dat_r + attribute \src "build/ls180/gateware/ls180.v:67.13-67.53" + wire width 32 \main_libresocsim_libresoc_xics_icp_dat_w + attribute \src "build/ls180/gateware/ls180.v:76.5-76.43" + wire \main_libresocsim_libresoc_xics_icp_err + attribute \src "build/ls180/gateware/ls180.v:69.12-69.50" + wire width 4 \main_libresocsim_libresoc_xics_icp_sel + attribute \src "build/ls180/gateware/ls180.v:71.6-71.44" + wire \main_libresocsim_libresoc_xics_icp_stb + attribute \src "build/ls180/gateware/ls180.v:73.6-73.43" + wire \main_libresocsim_libresoc_xics_icp_we + attribute \src "build/ls180/gateware/ls180.v:83.5-83.43" + wire \main_libresocsim_libresoc_xics_ics_ack + attribute \src "build/ls180/gateware/ls180.v:77.13-77.51" + wire width 30 \main_libresocsim_libresoc_xics_ics_adr + attribute \src "build/ls180/gateware/ls180.v:86.12-86.50" + wire width 2 \main_libresocsim_libresoc_xics_ics_bte + attribute \src "build/ls180/gateware/ls180.v:85.12-85.50" + wire width 3 \main_libresocsim_libresoc_xics_ics_cti + attribute \src "build/ls180/gateware/ls180.v:81.6-81.44" + wire \main_libresocsim_libresoc_xics_ics_cyc + attribute \src "build/ls180/gateware/ls180.v:79.12-79.52" + wire width 32 \main_libresocsim_libresoc_xics_ics_dat_r + attribute \src "build/ls180/gateware/ls180.v:78.13-78.53" + wire width 32 \main_libresocsim_libresoc_xics_ics_dat_w + attribute \src "build/ls180/gateware/ls180.v:87.5-87.43" + wire \main_libresocsim_libresoc_xics_ics_err + attribute \src "build/ls180/gateware/ls180.v:80.12-80.50" + wire width 4 \main_libresocsim_libresoc_xics_ics_sel + attribute \src "build/ls180/gateware/ls180.v:82.6-82.44" + wire \main_libresocsim_libresoc_xics_ics_stb + attribute \src "build/ls180/gateware/ls180.v:84.6-84.43" + wire \main_libresocsim_libresoc_xics_ics_we + attribute \src "build/ls180/gateware/ls180.v:159.12-159.49" + wire width 32 \main_libresocsim_phase_accumulator_rx + attribute \src "build/ls180/gateware/ls180.v:149.12-149.49" + wire width 32 \main_libresocsim_phase_accumulator_tx + attribute \src "build/ls180/gateware/ls180.v:132.5-132.33" + wire \main_libresocsim_ram_bus_ack + attribute \src "build/ls180/gateware/ls180.v:126.13-126.41" + wire width 30 \main_libresocsim_ram_bus_adr + attribute \src "build/ls180/gateware/ls180.v:135.12-135.40" + wire width 2 \main_libresocsim_ram_bus_bte + attribute \src "build/ls180/gateware/ls180.v:134.12-134.40" + wire width 3 \main_libresocsim_ram_bus_cti + attribute \src "build/ls180/gateware/ls180.v:130.6-130.34" + wire \main_libresocsim_ram_bus_cyc + attribute \src "build/ls180/gateware/ls180.v:128.13-128.43" + wire width 32 \main_libresocsim_ram_bus_dat_r + attribute \src "build/ls180/gateware/ls180.v:127.13-127.43" + wire width 32 \main_libresocsim_ram_bus_dat_w + attribute \src "build/ls180/gateware/ls180.v:136.5-136.33" + wire \main_libresocsim_ram_bus_err + attribute \src "build/ls180/gateware/ls180.v:129.12-129.40" + wire width 4 \main_libresocsim_ram_bus_sel + attribute \src "build/ls180/gateware/ls180.v:131.6-131.34" + wire \main_libresocsim_ram_bus_stb + attribute \src "build/ls180/gateware/ls180.v:133.6-133.33" + wire \main_libresocsim_ram_bus_we + attribute \src "build/ls180/gateware/ls180.v:142.5-142.24" + wire \main_libresocsim_re + attribute \src "build/ls180/gateware/ls180.v:160.6-160.25" + wire \main_libresocsim_rx + attribute \src "build/ls180/gateware/ls180.v:163.11-163.39" + wire width 4 \main_libresocsim_rx_bitcount + attribute \src "build/ls180/gateware/ls180.v:164.5-164.29" + wire \main_libresocsim_rx_busy + attribute \src "build/ls180/gateware/ls180.v:161.5-161.26" + wire \main_libresocsim_rx_r + attribute \src "build/ls180/gateware/ls180.v:162.11-162.34" + wire width 8 \main_libresocsim_rx_reg + attribute \src "build/ls180/gateware/ls180.v:145.6-145.33" + wire \main_libresocsim_sink_first + attribute \src "build/ls180/gateware/ls180.v:146.6-146.32" + wire \main_libresocsim_sink_last + attribute \src "build/ls180/gateware/ls180.v:147.12-147.46" + wire width 8 \main_libresocsim_sink_payload_data + attribute \src "build/ls180/gateware/ls180.v:144.5-144.32" + wire \main_libresocsim_sink_ready + attribute \src "build/ls180/gateware/ls180.v:143.6-143.33" + wire \main_libresocsim_sink_valid + attribute \src "build/ls180/gateware/ls180.v:40.6-40.46" + wire \main_libresocsim_soccontroller_bus_error + attribute \src "build/ls180/gateware/ls180.v:41.12-41.53" + wire width 32 \main_libresocsim_soccontroller_bus_errors + attribute \src "build/ls180/gateware/ls180.v:37.13-37.61" + wire width 32 \main_libresocsim_soccontroller_bus_errors_status + attribute \src "build/ls180/gateware/ls180.v:38.6-38.50" + wire \main_libresocsim_soccontroller_bus_errors_we + attribute \src "build/ls180/gateware/ls180.v:39.6-39.42" + wire \main_libresocsim_soccontroller_reset + attribute \src "build/ls180/gateware/ls180.v:34.5-34.44" + wire \main_libresocsim_soccontroller_reset_re + attribute \src "build/ls180/gateware/ls180.v:33.5-33.49" + wire \main_libresocsim_soccontroller_reset_storage + attribute \src "build/ls180/gateware/ls180.v:36.5-36.46" + wire \main_libresocsim_soccontroller_scratch_re + attribute \src "build/ls180/gateware/ls180.v:35.12-35.58" + wire width 32 \main_libresocsim_soccontroller_scratch_storage + attribute \src "build/ls180/gateware/ls180.v:155.5-155.34" + wire \main_libresocsim_source_first + attribute \src "build/ls180/gateware/ls180.v:156.5-156.33" + wire \main_libresocsim_source_last + attribute \src "build/ls180/gateware/ls180.v:157.11-157.47" + wire width 8 \main_libresocsim_source_payload_data + attribute \src "build/ls180/gateware/ls180.v:154.6-154.35" + wire \main_libresocsim_source_ready + attribute \src "build/ls180/gateware/ls180.v:153.5-153.34" + wire \main_libresocsim_source_valid + attribute \src "build/ls180/gateware/ls180.v:141.12-141.36" + wire width 32 \main_libresocsim_storage + attribute \src "build/ls180/gateware/ls180.v:288.5-288.33" + wire \main_libresocsim_timer_en_re + attribute \src "build/ls180/gateware/ls180.v:287.5-287.38" + wire \main_libresocsim_timer_en_storage + attribute \src "build/ls180/gateware/ls180.v:304.6-304.51" + wire \main_libresocsim_timer_eventmanager_pending_r + attribute \src "build/ls180/gateware/ls180.v:303.6-303.52" + wire \main_libresocsim_timer_eventmanager_pending_re + attribute \src "build/ls180/gateware/ls180.v:306.6-306.51" + wire \main_libresocsim_timer_eventmanager_pending_w + attribute \src "build/ls180/gateware/ls180.v:305.6-305.52" + wire \main_libresocsim_timer_eventmanager_pending_we + attribute \src "build/ls180/gateware/ls180.v:308.5-308.43" + wire \main_libresocsim_timer_eventmanager_re + attribute \src "build/ls180/gateware/ls180.v:300.6-300.50" + wire \main_libresocsim_timer_eventmanager_status_r + attribute \src "build/ls180/gateware/ls180.v:299.6-299.51" + wire \main_libresocsim_timer_eventmanager_status_re + attribute \src "build/ls180/gateware/ls180.v:302.6-302.50" + wire \main_libresocsim_timer_eventmanager_status_w + attribute \src "build/ls180/gateware/ls180.v:301.6-301.51" + wire \main_libresocsim_timer_eventmanager_status_we + attribute \src "build/ls180/gateware/ls180.v:307.5-307.48" + wire \main_libresocsim_timer_eventmanager_storage + attribute \src "build/ls180/gateware/ls180.v:293.6-293.32" + wire \main_libresocsim_timer_irq + attribute \src "build/ls180/gateware/ls180.v:284.5-284.35" + wire \main_libresocsim_timer_load_re + attribute \src "build/ls180/gateware/ls180.v:283.12-283.47" + wire width 32 \main_libresocsim_timer_load_storage + attribute \src "build/ls180/gateware/ls180.v:286.5-286.37" + wire \main_libresocsim_timer_reload_re + attribute \src "build/ls180/gateware/ls180.v:285.12-285.49" + wire width 32 \main_libresocsim_timer_reload_storage + attribute \src "build/ls180/gateware/ls180.v:290.5-290.43" + wire \main_libresocsim_timer_update_value_re + attribute \src "build/ls180/gateware/ls180.v:289.5-289.48" + wire \main_libresocsim_timer_update_value_storage + attribute \src "build/ls180/gateware/ls180.v:309.12-309.40" + wire width 32 \main_libresocsim_timer_value + attribute \src "build/ls180/gateware/ls180.v:291.12-291.47" + wire width 32 \main_libresocsim_timer_value_status + attribute \src "build/ls180/gateware/ls180.v:292.6-292.37" + wire \main_libresocsim_timer_value_we + attribute \src "build/ls180/gateware/ls180.v:297.5-297.38" + wire \main_libresocsim_timer_zero_clear + attribute \src "build/ls180/gateware/ls180.v:298.5-298.44" + wire \main_libresocsim_timer_zero_old_trigger + attribute \src "build/ls180/gateware/ls180.v:295.5-295.40" + wire \main_libresocsim_timer_zero_pending + attribute \src "build/ls180/gateware/ls180.v:294.6-294.40" + wire \main_libresocsim_timer_zero_status + attribute \src "build/ls180/gateware/ls180.v:296.6-296.41" + wire \main_libresocsim_timer_zero_trigger + attribute \src "build/ls180/gateware/ls180.v:151.11-151.39" + wire width 4 \main_libresocsim_tx_bitcount + attribute \src "build/ls180/gateware/ls180.v:152.5-152.29" + wire \main_libresocsim_tx_busy + attribute \src "build/ls180/gateware/ls180.v:150.11-150.34" + wire width 8 \main_libresocsim_tx_reg + attribute \src "build/ls180/gateware/ls180.v:158.5-158.35" + wire \main_libresocsim_uart_clk_rxen + attribute \src "build/ls180/gateware/ls180.v:148.5-148.35" + wire \main_libresocsim_uart_clk_txen + attribute \src "build/ls180/gateware/ls180.v:189.12-189.56" + wire width 2 \main_libresocsim_uart_eventmanager_pending_r + attribute \src "build/ls180/gateware/ls180.v:188.6-188.51" + wire \main_libresocsim_uart_eventmanager_pending_re + attribute \src "build/ls180/gateware/ls180.v:191.11-191.55" + wire width 2 \main_libresocsim_uart_eventmanager_pending_w + attribute \src "build/ls180/gateware/ls180.v:190.6-190.51" + wire \main_libresocsim_uart_eventmanager_pending_we + attribute \src "build/ls180/gateware/ls180.v:193.5-193.42" + wire \main_libresocsim_uart_eventmanager_re + attribute \src "build/ls180/gateware/ls180.v:185.12-185.55" + wire width 2 \main_libresocsim_uart_eventmanager_status_r + attribute \src "build/ls180/gateware/ls180.v:184.6-184.50" + wire \main_libresocsim_uart_eventmanager_status_re + attribute \src "build/ls180/gateware/ls180.v:187.11-187.54" + wire width 2 \main_libresocsim_uart_eventmanager_status_w + attribute \src "build/ls180/gateware/ls180.v:186.6-186.50" + wire \main_libresocsim_uart_eventmanager_status_we + attribute \src "build/ls180/gateware/ls180.v:192.11-192.53" + wire width 2 \main_libresocsim_uart_eventmanager_storage + attribute \src "build/ls180/gateware/ls180.v:173.6-173.31" + wire \main_libresocsim_uart_irq + attribute \src "build/ls180/gateware/ls180.v:282.5-282.32" + wire \main_libresocsim_uart_reset + attribute \src "build/ls180/gateware/ls180.v:182.5-182.35" + wire \main_libresocsim_uart_rx_clear + attribute \src "build/ls180/gateware/ls180.v:266.11-266.48" + wire width 4 \main_libresocsim_uart_rx_fifo_consume + attribute \src "build/ls180/gateware/ls180.v:271.6-271.43" + wire \main_libresocsim_uart_rx_fifo_do_read + attribute \src "build/ls180/gateware/ls180.v:277.6-277.49" + wire \main_libresocsim_uart_rx_fifo_fifo_in_first + attribute \src "build/ls180/gateware/ls180.v:278.6-278.48" + wire \main_libresocsim_uart_rx_fifo_fifo_in_last + attribute \src "build/ls180/gateware/ls180.v:276.12-276.62" + wire width 8 \main_libresocsim_uart_rx_fifo_fifo_in_payload_data + attribute \src "build/ls180/gateware/ls180.v:280.6-280.50" + wire \main_libresocsim_uart_rx_fifo_fifo_out_first + attribute \src "build/ls180/gateware/ls180.v:281.6-281.49" + wire \main_libresocsim_uart_rx_fifo_fifo_out_last + attribute \src "build/ls180/gateware/ls180.v:279.12-279.63" + wire width 8 \main_libresocsim_uart_rx_fifo_fifo_out_payload_data + attribute \src "build/ls180/gateware/ls180.v:263.11-263.47" + wire width 5 \main_libresocsim_uart_rx_fifo_level0 + attribute \src "build/ls180/gateware/ls180.v:275.12-275.48" + wire width 5 \main_libresocsim_uart_rx_fifo_level1 + attribute \src "build/ls180/gateware/ls180.v:265.11-265.48" + wire width 4 \main_libresocsim_uart_rx_fifo_produce + attribute \src "build/ls180/gateware/ls180.v:272.12-272.52" + wire width 4 \main_libresocsim_uart_rx_fifo_rdport_adr + attribute \src "build/ls180/gateware/ls180.v:273.12-273.54" + wire width 10 \main_libresocsim_uart_rx_fifo_rdport_dat_r + attribute \src "build/ls180/gateware/ls180.v:274.6-274.45" + wire \main_libresocsim_uart_rx_fifo_rdport_re + attribute \src "build/ls180/gateware/ls180.v:255.6-255.38" + wire \main_libresocsim_uart_rx_fifo_re + attribute \src "build/ls180/gateware/ls180.v:256.5-256.43" + wire \main_libresocsim_uart_rx_fifo_readable + attribute \src "build/ls180/gateware/ls180.v:264.5-264.42" + wire \main_libresocsim_uart_rx_fifo_replace + attribute \src "build/ls180/gateware/ls180.v:247.6-247.46" + wire \main_libresocsim_uart_rx_fifo_sink_first + attribute \src "build/ls180/gateware/ls180.v:248.6-248.45" + wire \main_libresocsim_uart_rx_fifo_sink_last + attribute \src "build/ls180/gateware/ls180.v:249.12-249.59" + wire width 8 \main_libresocsim_uart_rx_fifo_sink_payload_data + attribute \src "build/ls180/gateware/ls180.v:246.6-246.46" + wire \main_libresocsim_uart_rx_fifo_sink_ready + attribute \src "build/ls180/gateware/ls180.v:245.6-245.46" + wire \main_libresocsim_uart_rx_fifo_sink_valid + attribute \src "build/ls180/gateware/ls180.v:252.6-252.48" + wire \main_libresocsim_uart_rx_fifo_source_first + attribute \src "build/ls180/gateware/ls180.v:253.6-253.47" + wire \main_libresocsim_uart_rx_fifo_source_last + attribute \src "build/ls180/gateware/ls180.v:254.12-254.61" + wire width 8 \main_libresocsim_uart_rx_fifo_source_payload_data + attribute \src "build/ls180/gateware/ls180.v:251.6-251.48" + wire \main_libresocsim_uart_rx_fifo_source_ready + attribute \src "build/ls180/gateware/ls180.v:250.6-250.48" + wire \main_libresocsim_uart_rx_fifo_source_valid + attribute \src "build/ls180/gateware/ls180.v:261.12-261.54" + wire width 10 \main_libresocsim_uart_rx_fifo_syncfifo_din + attribute \src "build/ls180/gateware/ls180.v:262.12-262.55" + wire width 10 \main_libresocsim_uart_rx_fifo_syncfifo_dout + attribute \src "build/ls180/gateware/ls180.v:259.6-259.47" + wire \main_libresocsim_uart_rx_fifo_syncfifo_re + attribute \src "build/ls180/gateware/ls180.v:260.6-260.53" + wire \main_libresocsim_uart_rx_fifo_syncfifo_readable + attribute \src "build/ls180/gateware/ls180.v:257.6-257.47" + wire \main_libresocsim_uart_rx_fifo_syncfifo_we + attribute \src "build/ls180/gateware/ls180.v:258.6-258.53" + wire \main_libresocsim_uart_rx_fifo_syncfifo_writable + attribute \src "build/ls180/gateware/ls180.v:267.11-267.51" + wire width 4 \main_libresocsim_uart_rx_fifo_wrport_adr + attribute \src "build/ls180/gateware/ls180.v:268.12-268.54" + wire width 10 \main_libresocsim_uart_rx_fifo_wrport_dat_r + attribute \src "build/ls180/gateware/ls180.v:270.12-270.54" + wire width 10 \main_libresocsim_uart_rx_fifo_wrport_dat_w + attribute \src "build/ls180/gateware/ls180.v:269.6-269.45" + wire \main_libresocsim_uart_rx_fifo_wrport_we + attribute \src "build/ls180/gateware/ls180.v:183.5-183.41" + wire \main_libresocsim_uart_rx_old_trigger + attribute \src "build/ls180/gateware/ls180.v:180.5-180.37" + wire \main_libresocsim_uart_rx_pending + attribute \src "build/ls180/gateware/ls180.v:179.6-179.37" + wire \main_libresocsim_uart_rx_status + attribute \src "build/ls180/gateware/ls180.v:181.6-181.38" + wire \main_libresocsim_uart_rx_trigger + attribute \src "build/ls180/gateware/ls180.v:171.6-171.42" + wire \main_libresocsim_uart_rxempty_status + attribute \src "build/ls180/gateware/ls180.v:172.6-172.38" + wire \main_libresocsim_uart_rxempty_we + attribute \src "build/ls180/gateware/ls180.v:196.6-196.41" + wire \main_libresocsim_uart_rxfull_status + attribute \src "build/ls180/gateware/ls180.v:197.6-197.37" + wire \main_libresocsim_uart_rxfull_we + attribute \src "build/ls180/gateware/ls180.v:166.12-166.40" + wire width 8 \main_libresocsim_uart_rxtx_r + attribute \src "build/ls180/gateware/ls180.v:165.6-165.35" + wire \main_libresocsim_uart_rxtx_re + attribute \src "build/ls180/gateware/ls180.v:168.12-168.40" + wire width 8 \main_libresocsim_uart_rxtx_w + attribute \src "build/ls180/gateware/ls180.v:167.6-167.35" + wire \main_libresocsim_uart_rxtx_we + attribute \src "build/ls180/gateware/ls180.v:177.5-177.35" + wire \main_libresocsim_uart_tx_clear + attribute \src "build/ls180/gateware/ls180.v:229.11-229.48" + wire width 4 \main_libresocsim_uart_tx_fifo_consume + attribute \src "build/ls180/gateware/ls180.v:234.6-234.43" + wire \main_libresocsim_uart_tx_fifo_do_read + attribute \src "build/ls180/gateware/ls180.v:240.6-240.49" + wire \main_libresocsim_uart_tx_fifo_fifo_in_first + attribute \src "build/ls180/gateware/ls180.v:241.6-241.48" + wire \main_libresocsim_uart_tx_fifo_fifo_in_last + attribute \src "build/ls180/gateware/ls180.v:239.12-239.62" + wire width 8 \main_libresocsim_uart_tx_fifo_fifo_in_payload_data + attribute \src "build/ls180/gateware/ls180.v:243.6-243.50" + wire \main_libresocsim_uart_tx_fifo_fifo_out_first + attribute \src "build/ls180/gateware/ls180.v:244.6-244.49" + wire \main_libresocsim_uart_tx_fifo_fifo_out_last + attribute \src "build/ls180/gateware/ls180.v:242.12-242.63" + wire width 8 \main_libresocsim_uart_tx_fifo_fifo_out_payload_data + attribute \src "build/ls180/gateware/ls180.v:226.11-226.47" + wire width 5 \main_libresocsim_uart_tx_fifo_level0 + attribute \src "build/ls180/gateware/ls180.v:238.12-238.48" + wire width 5 \main_libresocsim_uart_tx_fifo_level1 + attribute \src "build/ls180/gateware/ls180.v:228.11-228.48" + wire width 4 \main_libresocsim_uart_tx_fifo_produce + attribute \src "build/ls180/gateware/ls180.v:235.12-235.52" + wire width 4 \main_libresocsim_uart_tx_fifo_rdport_adr + attribute \src "build/ls180/gateware/ls180.v:236.12-236.54" + wire width 10 \main_libresocsim_uart_tx_fifo_rdport_dat_r + attribute \src "build/ls180/gateware/ls180.v:237.6-237.45" + wire \main_libresocsim_uart_tx_fifo_rdport_re + attribute \src "build/ls180/gateware/ls180.v:218.6-218.38" + wire \main_libresocsim_uart_tx_fifo_re + attribute \src "build/ls180/gateware/ls180.v:219.5-219.43" + wire \main_libresocsim_uart_tx_fifo_readable + attribute \src "build/ls180/gateware/ls180.v:227.5-227.42" + wire \main_libresocsim_uart_tx_fifo_replace + attribute \src "build/ls180/gateware/ls180.v:210.5-210.45" + wire \main_libresocsim_uart_tx_fifo_sink_first + attribute \src "build/ls180/gateware/ls180.v:211.5-211.44" + wire \main_libresocsim_uart_tx_fifo_sink_last + attribute \src "build/ls180/gateware/ls180.v:212.12-212.59" + wire width 8 \main_libresocsim_uart_tx_fifo_sink_payload_data + attribute \src "build/ls180/gateware/ls180.v:209.6-209.46" + wire \main_libresocsim_uart_tx_fifo_sink_ready + attribute \src "build/ls180/gateware/ls180.v:208.6-208.46" + wire \main_libresocsim_uart_tx_fifo_sink_valid + attribute \src "build/ls180/gateware/ls180.v:215.6-215.48" + wire \main_libresocsim_uart_tx_fifo_source_first + attribute \src "build/ls180/gateware/ls180.v:216.6-216.47" + wire \main_libresocsim_uart_tx_fifo_source_last + attribute \src "build/ls180/gateware/ls180.v:217.12-217.61" + wire width 8 \main_libresocsim_uart_tx_fifo_source_payload_data + attribute \src "build/ls180/gateware/ls180.v:214.6-214.48" + wire \main_libresocsim_uart_tx_fifo_source_ready + attribute \src "build/ls180/gateware/ls180.v:213.6-213.48" + wire \main_libresocsim_uart_tx_fifo_source_valid + attribute \src "build/ls180/gateware/ls180.v:224.12-224.54" + wire width 10 \main_libresocsim_uart_tx_fifo_syncfifo_din + attribute \src "build/ls180/gateware/ls180.v:225.12-225.55" + wire width 10 \main_libresocsim_uart_tx_fifo_syncfifo_dout + attribute \src "build/ls180/gateware/ls180.v:222.6-222.47" + wire \main_libresocsim_uart_tx_fifo_syncfifo_re + attribute \src "build/ls180/gateware/ls180.v:223.6-223.53" + wire \main_libresocsim_uart_tx_fifo_syncfifo_readable + attribute \src "build/ls180/gateware/ls180.v:220.6-220.47" + wire \main_libresocsim_uart_tx_fifo_syncfifo_we + attribute \src "build/ls180/gateware/ls180.v:221.6-221.53" + wire \main_libresocsim_uart_tx_fifo_syncfifo_writable + attribute \src "build/ls180/gateware/ls180.v:230.11-230.51" + wire width 4 \main_libresocsim_uart_tx_fifo_wrport_adr + attribute \src "build/ls180/gateware/ls180.v:231.12-231.54" + wire width 10 \main_libresocsim_uart_tx_fifo_wrport_dat_r + attribute \src "build/ls180/gateware/ls180.v:233.12-233.54" + wire width 10 \main_libresocsim_uart_tx_fifo_wrport_dat_w + attribute \src "build/ls180/gateware/ls180.v:232.6-232.45" + wire \main_libresocsim_uart_tx_fifo_wrport_we + attribute \src "build/ls180/gateware/ls180.v:178.5-178.41" + wire \main_libresocsim_uart_tx_old_trigger + attribute \src "build/ls180/gateware/ls180.v:175.5-175.37" + wire \main_libresocsim_uart_tx_pending + attribute \src "build/ls180/gateware/ls180.v:174.6-174.37" + wire \main_libresocsim_uart_tx_status + attribute \src "build/ls180/gateware/ls180.v:176.6-176.38" + wire \main_libresocsim_uart_tx_trigger + attribute \src "build/ls180/gateware/ls180.v:194.6-194.42" + wire \main_libresocsim_uart_txempty_status + attribute \src "build/ls180/gateware/ls180.v:195.6-195.38" + wire \main_libresocsim_uart_txempty_we + attribute \src "build/ls180/gateware/ls180.v:169.6-169.41" + wire \main_libresocsim_uart_txfull_status + attribute \src "build/ls180/gateware/ls180.v:170.6-170.37" + wire \main_libresocsim_uart_txfull_we + attribute \src "build/ls180/gateware/ls180.v:200.6-200.43" + wire \main_libresocsim_uart_uart_sink_first + attribute \src "build/ls180/gateware/ls180.v:201.6-201.42" + wire \main_libresocsim_uart_uart_sink_last + attribute \src "build/ls180/gateware/ls180.v:202.12-202.56" + wire width 8 \main_libresocsim_uart_uart_sink_payload_data + attribute \src "build/ls180/gateware/ls180.v:199.6-199.43" + wire \main_libresocsim_uart_uart_sink_ready + attribute \src "build/ls180/gateware/ls180.v:198.6-198.43" + wire \main_libresocsim_uart_uart_sink_valid + attribute \src "build/ls180/gateware/ls180.v:205.6-205.45" + wire \main_libresocsim_uart_uart_source_first + attribute \src "build/ls180/gateware/ls180.v:206.6-206.44" + wire \main_libresocsim_uart_uart_source_last + attribute \src "build/ls180/gateware/ls180.v:207.12-207.58" + wire width 8 \main_libresocsim_uart_uart_source_payload_data + attribute \src "build/ls180/gateware/ls180.v:204.6-204.45" + wire \main_libresocsim_uart_uart_source_ready + attribute \src "build/ls180/gateware/ls180.v:203.6-203.45" + wire \main_libresocsim_uart_uart_source_valid + attribute \src "build/ls180/gateware/ls180.v:139.11-139.30" + wire width 4 \main_libresocsim_we + attribute \src "build/ls180/gateware/ls180.v:891.6-891.26" + wire \main_litedram_wb_ack + attribute \src "build/ls180/gateware/ls180.v:885.12-885.32" + wire width 30 \main_litedram_wb_adr + attribute \src "build/ls180/gateware/ls180.v:889.5-889.25" + wire \main_litedram_wb_cyc + attribute \src "build/ls180/gateware/ls180.v:887.13-887.35" + wire width 16 \main_litedram_wb_dat_r + attribute \src "build/ls180/gateware/ls180.v:886.12-886.34" + wire width 16 \main_litedram_wb_dat_w + attribute \src "build/ls180/gateware/ls180.v:888.11-888.31" + wire width 2 \main_litedram_wb_sel + attribute \src "build/ls180/gateware/ls180.v:890.5-890.25" + wire \main_litedram_wb_stb + attribute \src "build/ls180/gateware/ls180.v:892.5-892.24" + wire \main_litedram_wb_we + attribute \src "build/ls180/gateware/ls180.v:913.6-913.19" + wire \main_loopback + attribute \src "build/ls180/gateware/ls180.v:930.5-930.21" + wire \main_loopback_re + attribute \src "build/ls180/gateware/ls180.v:929.5-929.26" + wire \main_loopback_storage + attribute \src "build/ls180/gateware/ls180.v:911.11-911.20" + wire width 8 \main_miso + attribute \src "build/ls180/gateware/ls180.v:941.11-941.25" + wire width 8 \main_miso_data + attribute \src "build/ls180/gateware/ls180.v:935.5-935.20" + wire \main_miso_latch + attribute \src "build/ls180/gateware/ls180.v:924.12-924.28" + wire width 8 \main_miso_status + attribute \src "build/ls180/gateware/ls180.v:925.6-925.18" + wire \main_miso_we + attribute \src "build/ls180/gateware/ls180.v:910.12-910.21" + wire width 8 \main_mosi + attribute \src "build/ls180/gateware/ls180.v:939.11-939.25" + wire width 8 \main_mosi_data + attribute \src "build/ls180/gateware/ls180.v:934.5-934.20" + wire \main_mosi_latch + attribute \src "build/ls180/gateware/ls180.v:923.5-923.17" + wire \main_mosi_re + attribute \src "build/ls180/gateware/ls180.v:940.11-940.24" + wire width 3 \main_mosi_sel + attribute \src "build/ls180/gateware/ls180.v:922.11-922.28" + wire width 8 \main_mosi_storage + attribute \src "build/ls180/gateware/ls180.v:864.6-864.24" + wire \main_port_cmd_last + attribute \src "build/ls180/gateware/ls180.v:866.13-866.39" + wire width 24 \main_port_cmd_payload_addr + attribute \src "build/ls180/gateware/ls180.v:865.6-865.30" + wire \main_port_cmd_payload_we + attribute \src "build/ls180/gateware/ls180.v:863.6-863.25" + wire \main_port_cmd_ready + attribute \src "build/ls180/gateware/ls180.v:862.6-862.25" + wire \main_port_cmd_valid + attribute \src "build/ls180/gateware/ls180.v:861.6-861.21" + wire \main_port_flush + attribute \src "build/ls180/gateware/ls180.v:873.13-873.41" + wire width 16 \main_port_rdata_payload_data + attribute \src "build/ls180/gateware/ls180.v:872.6-872.27" + wire \main_port_rdata_ready + attribute \src "build/ls180/gateware/ls180.v:871.6-871.27" + wire \main_port_rdata_valid + attribute \src "build/ls180/gateware/ls180.v:869.13-869.41" + wire width 16 \main_port_wdata_payload_data + attribute \src "build/ls180/gateware/ls180.v:870.12-870.38" + wire width 2 \main_port_wdata_payload_we + attribute \src "build/ls180/gateware/ls180.v:868.6-868.27" + wire \main_port_wdata_ready + attribute \src "build/ls180/gateware/ls180.v:867.6-867.27" + wire \main_port_wdata_valid + attribute \src "build/ls180/gateware/ls180.v:330.11-330.25" + wire width 3 \main_rddata_en + attribute \src "build/ls180/gateware/ls180.v:392.5-392.26" + wire \main_sdram_address_re + attribute \src "build/ls180/gateware/ls180.v:391.12-391.38" + wire width 13 \main_sdram_address_storage + attribute \src "build/ls180/gateware/ls180.v:394.5-394.27" + wire \main_sdram_baddress_re + attribute \src "build/ls180/gateware/ls180.v:393.11-393.38" + wire width 2 \main_sdram_baddress_storage + attribute \src "build/ls180/gateware/ls180.v:490.5-490.43" + wire \main_sdram_bankmachine0_auto_precharge + attribute \src "build/ls180/gateware/ls180.v:512.11-512.63" + wire width 3 \main_sdram_bankmachine0_cmd_buffer_lookahead_consume + attribute \src "build/ls180/gateware/ls180.v:517.6-517.58" + wire \main_sdram_bankmachine0_cmd_buffer_lookahead_do_read + attribute \src "build/ls180/gateware/ls180.v:522.6-522.64" + wire \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_first + attribute \src "build/ls180/gateware/ls180.v:523.6-523.63" + wire \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_last + attribute \src "build/ls180/gateware/ls180.v:521.13-521.78" + wire width 22 \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_addr + attribute \src "build/ls180/gateware/ls180.v:520.6-520.69" + wire \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_we + attribute \src "build/ls180/gateware/ls180.v:526.6-526.65" + wire \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_first + attribute \src "build/ls180/gateware/ls180.v:527.6-527.64" + wire \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_last + attribute \src "build/ls180/gateware/ls180.v:525.13-525.79" + wire width 22 \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr + attribute \src "build/ls180/gateware/ls180.v:524.6-524.70" + wire \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we + attribute \src "build/ls180/gateware/ls180.v:509.11-509.61" + wire width 4 \main_sdram_bankmachine0_cmd_buffer_lookahead_level + attribute \src "build/ls180/gateware/ls180.v:511.11-511.63" + wire width 3 \main_sdram_bankmachine0_cmd_buffer_lookahead_produce + attribute \src "build/ls180/gateware/ls180.v:518.12-518.67" + wire width 3 \main_sdram_bankmachine0_cmd_buffer_lookahead_rdport_adr + attribute \src "build/ls180/gateware/ls180.v:519.13-519.70" + wire width 25 \main_sdram_bankmachine0_cmd_buffer_lookahead_rdport_dat_r + attribute \src "build/ls180/gateware/ls180.v:510.5-510.57" + wire \main_sdram_bankmachine0_cmd_buffer_lookahead_replace + attribute \src "build/ls180/gateware/ls180.v:493.5-493.60" + wire \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_first + attribute \src "build/ls180/gateware/ls180.v:494.5-494.59" + wire \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_last + attribute \src "build/ls180/gateware/ls180.v:496.13-496.75" + wire width 22 \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_payload_addr + attribute \src "build/ls180/gateware/ls180.v:495.6-495.66" + wire \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_payload_we + attribute \src "build/ls180/gateware/ls180.v:492.6-492.61" + wire \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_ready + attribute \src "build/ls180/gateware/ls180.v:491.6-491.61" + wire \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_valid + attribute \src "build/ls180/gateware/ls180.v:499.6-499.63" + wire \main_sdram_bankmachine0_cmd_buffer_lookahead_source_first + attribute \src "build/ls180/gateware/ls180.v:500.6-500.62" + wire \main_sdram_bankmachine0_cmd_buffer_lookahead_source_last + attribute \src "build/ls180/gateware/ls180.v:502.13-502.77" + wire width 22 \main_sdram_bankmachine0_cmd_buffer_lookahead_source_payload_addr + attribute \src "build/ls180/gateware/ls180.v:501.6-501.68" + wire \main_sdram_bankmachine0_cmd_buffer_lookahead_source_payload_we + attribute \src "build/ls180/gateware/ls180.v:498.6-498.63" + wire \main_sdram_bankmachine0_cmd_buffer_lookahead_source_ready + attribute \src "build/ls180/gateware/ls180.v:497.6-497.63" + wire \main_sdram_bankmachine0_cmd_buffer_lookahead_source_valid + attribute \src "build/ls180/gateware/ls180.v:507.13-507.71" + wire width 25 \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_din + attribute \src "build/ls180/gateware/ls180.v:508.13-508.72" + wire width 25 \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout + attribute \src "build/ls180/gateware/ls180.v:505.6-505.63" + wire \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_re + attribute \src "build/ls180/gateware/ls180.v:506.6-506.69" + wire \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable + attribute \src "build/ls180/gateware/ls180.v:503.6-503.63" + wire \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_we + attribute \src "build/ls180/gateware/ls180.v:504.6-504.69" + wire \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable + attribute \src "build/ls180/gateware/ls180.v:513.11-513.66" + wire width 3 \main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr + attribute \src "build/ls180/gateware/ls180.v:514.13-514.70" + wire width 25 \main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_dat_r + attribute \src "build/ls180/gateware/ls180.v:516.13-516.70" + wire width 25 \main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_dat_w + attribute \src "build/ls180/gateware/ls180.v:515.6-515.60" + wire \main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_we + attribute \src "build/ls180/gateware/ls180.v:530.6-530.51" + wire \main_sdram_bankmachine0_cmd_buffer_sink_first + attribute \src "build/ls180/gateware/ls180.v:531.6-531.50" + wire \main_sdram_bankmachine0_cmd_buffer_sink_last + attribute \src "build/ls180/gateware/ls180.v:533.13-533.65" + wire width 22 \main_sdram_bankmachine0_cmd_buffer_sink_payload_addr + attribute \src "build/ls180/gateware/ls180.v:532.6-532.56" + wire \main_sdram_bankmachine0_cmd_buffer_sink_payload_we + attribute \src "build/ls180/gateware/ls180.v:529.6-529.51" + wire \main_sdram_bankmachine0_cmd_buffer_sink_ready + attribute \src "build/ls180/gateware/ls180.v:528.6-528.51" + wire \main_sdram_bankmachine0_cmd_buffer_sink_valid + attribute \src "build/ls180/gateware/ls180.v:536.5-536.52" + wire \main_sdram_bankmachine0_cmd_buffer_source_first + attribute \src "build/ls180/gateware/ls180.v:537.5-537.51" + wire \main_sdram_bankmachine0_cmd_buffer_source_last + attribute \src "build/ls180/gateware/ls180.v:539.12-539.66" + wire width 22 \main_sdram_bankmachine0_cmd_buffer_source_payload_addr + attribute \src "build/ls180/gateware/ls180.v:538.5-538.57" + wire \main_sdram_bankmachine0_cmd_buffer_source_payload_we + attribute \src "build/ls180/gateware/ls180.v:535.6-535.53" + wire \main_sdram_bankmachine0_cmd_buffer_source_ready + attribute \src "build/ls180/gateware/ls180.v:534.5-534.52" + wire \main_sdram_bankmachine0_cmd_buffer_source_valid + attribute \src "build/ls180/gateware/ls180.v:482.12-482.49" + wire width 13 \main_sdram_bankmachine0_cmd_payload_a + attribute \src "build/ls180/gateware/ls180.v:483.12-483.50" + wire width 2 \main_sdram_bankmachine0_cmd_payload_ba + attribute \src "build/ls180/gateware/ls180.v:484.5-484.44" + wire \main_sdram_bankmachine0_cmd_payload_cas + attribute \src "build/ls180/gateware/ls180.v:487.5-487.47" + wire \main_sdram_bankmachine0_cmd_payload_is_cmd + attribute \src "build/ls180/gateware/ls180.v:488.5-488.48" + wire \main_sdram_bankmachine0_cmd_payload_is_read + attribute \src "build/ls180/gateware/ls180.v:489.5-489.49" + wire \main_sdram_bankmachine0_cmd_payload_is_write + attribute \src "build/ls180/gateware/ls180.v:485.5-485.44" + wire \main_sdram_bankmachine0_cmd_payload_ras + attribute \src "build/ls180/gateware/ls180.v:486.5-486.43" + wire \main_sdram_bankmachine0_cmd_payload_we + attribute \src "build/ls180/gateware/ls180.v:481.5-481.38" + wire \main_sdram_bankmachine0_cmd_ready + attribute \src "build/ls180/gateware/ls180.v:480.5-480.38" + wire \main_sdram_bankmachine0_cmd_valid + attribute \src "build/ls180/gateware/ls180.v:479.5-479.40" + wire \main_sdram_bankmachine0_refresh_gnt + attribute \src "build/ls180/gateware/ls180.v:478.6-478.41" + wire \main_sdram_bankmachine0_refresh_req + attribute \src "build/ls180/gateware/ls180.v:474.13-474.45" + wire width 22 \main_sdram_bankmachine0_req_addr + attribute \src "build/ls180/gateware/ls180.v:475.6-475.38" + wire \main_sdram_bankmachine0_req_lock + attribute \src "build/ls180/gateware/ls180.v:477.5-477.44" + wire \main_sdram_bankmachine0_req_rdata_valid + attribute \src "build/ls180/gateware/ls180.v:472.6-472.39" + wire \main_sdram_bankmachine0_req_ready + attribute \src "build/ls180/gateware/ls180.v:471.6-471.39" + wire \main_sdram_bankmachine0_req_valid + attribute \src "build/ls180/gateware/ls180.v:476.5-476.44" + wire \main_sdram_bankmachine0_req_wdata_ready + attribute \src "build/ls180/gateware/ls180.v:473.6-473.36" + wire \main_sdram_bankmachine0_req_we + attribute \src "build/ls180/gateware/ls180.v:540.12-540.39" + wire width 13 \main_sdram_bankmachine0_row + attribute \src "build/ls180/gateware/ls180.v:544.5-544.38" + wire \main_sdram_bankmachine0_row_close + attribute \src "build/ls180/gateware/ls180.v:545.5-545.47" + wire \main_sdram_bankmachine0_row_col_n_addr_sel + attribute \src "build/ls180/gateware/ls180.v:542.6-542.37" + wire \main_sdram_bankmachine0_row_hit + attribute \src "build/ls180/gateware/ls180.v:543.5-543.37" + wire \main_sdram_bankmachine0_row_open + attribute \src "build/ls180/gateware/ls180.v:541.5-541.39" + wire \main_sdram_bankmachine0_row_opened + attribute \no_retiming "true" + attribute \src "build/ls180/gateware/ls180.v:552.32-552.69" + wire \main_sdram_bankmachine0_trascon_ready + attribute \src "build/ls180/gateware/ls180.v:551.6-551.43" + wire \main_sdram_bankmachine0_trascon_valid + attribute \no_retiming "true" + attribute \src "build/ls180/gateware/ls180.v:550.32-550.68" + wire \main_sdram_bankmachine0_trccon_ready + attribute \src "build/ls180/gateware/ls180.v:549.6-549.42" + wire \main_sdram_bankmachine0_trccon_valid + attribute \src "build/ls180/gateware/ls180.v:548.11-548.48" + wire width 3 \main_sdram_bankmachine0_twtpcon_count + attribute \no_retiming "true" + attribute \src "build/ls180/gateware/ls180.v:547.32-547.69" + wire \main_sdram_bankmachine0_twtpcon_ready + attribute \src "build/ls180/gateware/ls180.v:546.6-546.43" + wire \main_sdram_bankmachine0_twtpcon_valid + attribute \src "build/ls180/gateware/ls180.v:572.5-572.43" + wire \main_sdram_bankmachine1_auto_precharge + attribute \src "build/ls180/gateware/ls180.v:594.11-594.63" + wire width 3 \main_sdram_bankmachine1_cmd_buffer_lookahead_consume + attribute \src "build/ls180/gateware/ls180.v:599.6-599.58" + wire \main_sdram_bankmachine1_cmd_buffer_lookahead_do_read + attribute \src "build/ls180/gateware/ls180.v:604.6-604.64" + wire \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_first + attribute \src "build/ls180/gateware/ls180.v:605.6-605.63" + wire \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_last + attribute \src "build/ls180/gateware/ls180.v:603.13-603.78" + wire width 22 \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_addr + attribute \src "build/ls180/gateware/ls180.v:602.6-602.69" + wire \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_we + attribute \src "build/ls180/gateware/ls180.v:608.6-608.65" + wire \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_first + attribute \src "build/ls180/gateware/ls180.v:609.6-609.64" + wire \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_last + attribute \src "build/ls180/gateware/ls180.v:607.13-607.79" + wire width 22 \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr + attribute \src "build/ls180/gateware/ls180.v:606.6-606.70" + wire \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we + attribute \src "build/ls180/gateware/ls180.v:591.11-591.61" + wire width 4 \main_sdram_bankmachine1_cmd_buffer_lookahead_level + attribute \src "build/ls180/gateware/ls180.v:593.11-593.63" + wire width 3 \main_sdram_bankmachine1_cmd_buffer_lookahead_produce + attribute \src "build/ls180/gateware/ls180.v:600.12-600.67" + wire width 3 \main_sdram_bankmachine1_cmd_buffer_lookahead_rdport_adr + attribute \src "build/ls180/gateware/ls180.v:601.13-601.70" + wire width 25 \main_sdram_bankmachine1_cmd_buffer_lookahead_rdport_dat_r + attribute \src "build/ls180/gateware/ls180.v:592.5-592.57" + wire \main_sdram_bankmachine1_cmd_buffer_lookahead_replace + attribute \src "build/ls180/gateware/ls180.v:575.5-575.60" + wire \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_first + attribute \src "build/ls180/gateware/ls180.v:576.5-576.59" + wire \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_last + attribute \src "build/ls180/gateware/ls180.v:578.13-578.75" + wire width 22 \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_payload_addr + attribute \src "build/ls180/gateware/ls180.v:577.6-577.66" + wire \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_payload_we + attribute \src "build/ls180/gateware/ls180.v:574.6-574.61" + wire \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_ready + attribute \src "build/ls180/gateware/ls180.v:573.6-573.61" + wire \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_valid + attribute \src "build/ls180/gateware/ls180.v:581.6-581.63" + wire \main_sdram_bankmachine1_cmd_buffer_lookahead_source_first + attribute \src "build/ls180/gateware/ls180.v:582.6-582.62" + wire \main_sdram_bankmachine1_cmd_buffer_lookahead_source_last + attribute \src "build/ls180/gateware/ls180.v:584.13-584.77" + wire width 22 \main_sdram_bankmachine1_cmd_buffer_lookahead_source_payload_addr + attribute \src "build/ls180/gateware/ls180.v:583.6-583.68" + wire \main_sdram_bankmachine1_cmd_buffer_lookahead_source_payload_we + attribute \src "build/ls180/gateware/ls180.v:580.6-580.63" + wire \main_sdram_bankmachine1_cmd_buffer_lookahead_source_ready + attribute \src "build/ls180/gateware/ls180.v:579.6-579.63" + wire \main_sdram_bankmachine1_cmd_buffer_lookahead_source_valid + attribute \src "build/ls180/gateware/ls180.v:589.13-589.71" + wire width 25 \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_din + attribute \src "build/ls180/gateware/ls180.v:590.13-590.72" + wire width 25 \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout + attribute \src "build/ls180/gateware/ls180.v:587.6-587.63" + wire \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_re + attribute \src "build/ls180/gateware/ls180.v:588.6-588.69" + wire \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable + attribute \src "build/ls180/gateware/ls180.v:585.6-585.63" + wire \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_we + attribute \src "build/ls180/gateware/ls180.v:586.6-586.69" + wire \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable + attribute \src "build/ls180/gateware/ls180.v:595.11-595.66" + wire width 3 \main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr + attribute \src "build/ls180/gateware/ls180.v:596.13-596.70" + wire width 25 \main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_dat_r + attribute \src "build/ls180/gateware/ls180.v:598.13-598.70" + wire width 25 \main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_dat_w + attribute \src "build/ls180/gateware/ls180.v:597.6-597.60" + wire \main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_we + attribute \src "build/ls180/gateware/ls180.v:612.6-612.51" + wire \main_sdram_bankmachine1_cmd_buffer_sink_first + attribute \src "build/ls180/gateware/ls180.v:613.6-613.50" + wire \main_sdram_bankmachine1_cmd_buffer_sink_last + attribute \src "build/ls180/gateware/ls180.v:615.13-615.65" + wire width 22 \main_sdram_bankmachine1_cmd_buffer_sink_payload_addr + attribute \src "build/ls180/gateware/ls180.v:614.6-614.56" + wire \main_sdram_bankmachine1_cmd_buffer_sink_payload_we + attribute \src "build/ls180/gateware/ls180.v:611.6-611.51" + wire \main_sdram_bankmachine1_cmd_buffer_sink_ready + attribute \src "build/ls180/gateware/ls180.v:610.6-610.51" + wire \main_sdram_bankmachine1_cmd_buffer_sink_valid + attribute \src "build/ls180/gateware/ls180.v:618.5-618.52" + wire \main_sdram_bankmachine1_cmd_buffer_source_first + attribute \src "build/ls180/gateware/ls180.v:619.5-619.51" + wire \main_sdram_bankmachine1_cmd_buffer_source_last + attribute \src "build/ls180/gateware/ls180.v:621.12-621.66" + wire width 22 \main_sdram_bankmachine1_cmd_buffer_source_payload_addr + attribute \src "build/ls180/gateware/ls180.v:620.5-620.57" + wire \main_sdram_bankmachine1_cmd_buffer_source_payload_we + attribute \src "build/ls180/gateware/ls180.v:617.6-617.53" + wire \main_sdram_bankmachine1_cmd_buffer_source_ready + attribute \src "build/ls180/gateware/ls180.v:616.5-616.52" + wire \main_sdram_bankmachine1_cmd_buffer_source_valid + attribute \src "build/ls180/gateware/ls180.v:564.12-564.49" + wire width 13 \main_sdram_bankmachine1_cmd_payload_a + attribute \src "build/ls180/gateware/ls180.v:565.12-565.50" + wire width 2 \main_sdram_bankmachine1_cmd_payload_ba + attribute \src "build/ls180/gateware/ls180.v:566.5-566.44" + wire \main_sdram_bankmachine1_cmd_payload_cas + attribute \src "build/ls180/gateware/ls180.v:569.5-569.47" + wire \main_sdram_bankmachine1_cmd_payload_is_cmd + attribute \src "build/ls180/gateware/ls180.v:570.5-570.48" + wire \main_sdram_bankmachine1_cmd_payload_is_read + attribute \src "build/ls180/gateware/ls180.v:571.5-571.49" + wire \main_sdram_bankmachine1_cmd_payload_is_write + attribute \src "build/ls180/gateware/ls180.v:567.5-567.44" + wire \main_sdram_bankmachine1_cmd_payload_ras + attribute \src "build/ls180/gateware/ls180.v:568.5-568.43" + wire \main_sdram_bankmachine1_cmd_payload_we + attribute \src "build/ls180/gateware/ls180.v:563.5-563.38" + wire \main_sdram_bankmachine1_cmd_ready + attribute \src "build/ls180/gateware/ls180.v:562.5-562.38" + wire \main_sdram_bankmachine1_cmd_valid + attribute \src "build/ls180/gateware/ls180.v:561.5-561.40" + wire \main_sdram_bankmachine1_refresh_gnt + attribute \src "build/ls180/gateware/ls180.v:560.6-560.41" + wire \main_sdram_bankmachine1_refresh_req + attribute \src "build/ls180/gateware/ls180.v:556.13-556.45" + wire width 22 \main_sdram_bankmachine1_req_addr + attribute \src "build/ls180/gateware/ls180.v:557.6-557.38" + wire \main_sdram_bankmachine1_req_lock + attribute \src "build/ls180/gateware/ls180.v:559.5-559.44" + wire \main_sdram_bankmachine1_req_rdata_valid + attribute \src "build/ls180/gateware/ls180.v:554.6-554.39" + wire \main_sdram_bankmachine1_req_ready + attribute \src "build/ls180/gateware/ls180.v:553.6-553.39" + wire \main_sdram_bankmachine1_req_valid + attribute \src "build/ls180/gateware/ls180.v:558.5-558.44" + wire \main_sdram_bankmachine1_req_wdata_ready + attribute \src "build/ls180/gateware/ls180.v:555.6-555.36" + wire \main_sdram_bankmachine1_req_we + attribute \src "build/ls180/gateware/ls180.v:622.12-622.39" + wire width 13 \main_sdram_bankmachine1_row + attribute \src "build/ls180/gateware/ls180.v:626.5-626.38" + wire \main_sdram_bankmachine1_row_close + attribute \src "build/ls180/gateware/ls180.v:627.5-627.47" + wire \main_sdram_bankmachine1_row_col_n_addr_sel + attribute \src "build/ls180/gateware/ls180.v:624.6-624.37" + wire \main_sdram_bankmachine1_row_hit + attribute \src "build/ls180/gateware/ls180.v:625.5-625.37" + wire \main_sdram_bankmachine1_row_open + attribute \src "build/ls180/gateware/ls180.v:623.5-623.39" + wire \main_sdram_bankmachine1_row_opened + attribute \no_retiming "true" + attribute \src "build/ls180/gateware/ls180.v:634.32-634.69" + wire \main_sdram_bankmachine1_trascon_ready + attribute \src "build/ls180/gateware/ls180.v:633.6-633.43" + wire \main_sdram_bankmachine1_trascon_valid + attribute \no_retiming "true" + attribute \src "build/ls180/gateware/ls180.v:632.32-632.68" + wire \main_sdram_bankmachine1_trccon_ready + attribute \src "build/ls180/gateware/ls180.v:631.6-631.42" + wire \main_sdram_bankmachine1_trccon_valid + attribute \src "build/ls180/gateware/ls180.v:630.11-630.48" + wire width 3 \main_sdram_bankmachine1_twtpcon_count + attribute \no_retiming "true" + attribute \src "build/ls180/gateware/ls180.v:629.32-629.69" + wire \main_sdram_bankmachine1_twtpcon_ready + attribute \src "build/ls180/gateware/ls180.v:628.6-628.43" + wire \main_sdram_bankmachine1_twtpcon_valid + attribute \src "build/ls180/gateware/ls180.v:654.5-654.43" + wire \main_sdram_bankmachine2_auto_precharge + attribute \src "build/ls180/gateware/ls180.v:676.11-676.63" + wire width 3 \main_sdram_bankmachine2_cmd_buffer_lookahead_consume + attribute \src "build/ls180/gateware/ls180.v:681.6-681.58" + wire \main_sdram_bankmachine2_cmd_buffer_lookahead_do_read + attribute \src "build/ls180/gateware/ls180.v:686.6-686.64" + wire \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_first + attribute \src "build/ls180/gateware/ls180.v:687.6-687.63" + wire \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_last + attribute \src "build/ls180/gateware/ls180.v:685.13-685.78" + wire width 22 \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_addr + attribute \src "build/ls180/gateware/ls180.v:684.6-684.69" + wire \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_we + attribute \src "build/ls180/gateware/ls180.v:690.6-690.65" + wire \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_first + attribute \src "build/ls180/gateware/ls180.v:691.6-691.64" + wire \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_last + attribute \src "build/ls180/gateware/ls180.v:689.13-689.79" + wire width 22 \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr + attribute \src "build/ls180/gateware/ls180.v:688.6-688.70" + wire \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we + attribute \src "build/ls180/gateware/ls180.v:673.11-673.61" + wire width 4 \main_sdram_bankmachine2_cmd_buffer_lookahead_level + attribute \src "build/ls180/gateware/ls180.v:675.11-675.63" + wire width 3 \main_sdram_bankmachine2_cmd_buffer_lookahead_produce + attribute \src "build/ls180/gateware/ls180.v:682.12-682.67" + wire width 3 \main_sdram_bankmachine2_cmd_buffer_lookahead_rdport_adr + attribute \src "build/ls180/gateware/ls180.v:683.13-683.70" + wire width 25 \main_sdram_bankmachine2_cmd_buffer_lookahead_rdport_dat_r + attribute \src "build/ls180/gateware/ls180.v:674.5-674.57" + wire \main_sdram_bankmachine2_cmd_buffer_lookahead_replace + attribute \src "build/ls180/gateware/ls180.v:657.5-657.60" + wire \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_first + attribute \src "build/ls180/gateware/ls180.v:658.5-658.59" + wire \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_last + attribute \src "build/ls180/gateware/ls180.v:660.13-660.75" + wire width 22 \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_payload_addr + attribute \src "build/ls180/gateware/ls180.v:659.6-659.66" + wire \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_payload_we + attribute \src "build/ls180/gateware/ls180.v:656.6-656.61" + wire \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_ready + attribute \src "build/ls180/gateware/ls180.v:655.6-655.61" + wire \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_valid + attribute \src "build/ls180/gateware/ls180.v:663.6-663.63" + wire \main_sdram_bankmachine2_cmd_buffer_lookahead_source_first + attribute \src "build/ls180/gateware/ls180.v:664.6-664.62" + wire \main_sdram_bankmachine2_cmd_buffer_lookahead_source_last + attribute \src "build/ls180/gateware/ls180.v:666.13-666.77" + wire width 22 \main_sdram_bankmachine2_cmd_buffer_lookahead_source_payload_addr + attribute \src "build/ls180/gateware/ls180.v:665.6-665.68" + wire \main_sdram_bankmachine2_cmd_buffer_lookahead_source_payload_we + attribute \src "build/ls180/gateware/ls180.v:662.6-662.63" + wire \main_sdram_bankmachine2_cmd_buffer_lookahead_source_ready + attribute \src "build/ls180/gateware/ls180.v:661.6-661.63" + wire \main_sdram_bankmachine2_cmd_buffer_lookahead_source_valid + attribute \src "build/ls180/gateware/ls180.v:671.13-671.71" + wire width 25 \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_din + attribute \src "build/ls180/gateware/ls180.v:672.13-672.72" + wire width 25 \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout + attribute \src "build/ls180/gateware/ls180.v:669.6-669.63" + wire \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_re + attribute \src "build/ls180/gateware/ls180.v:670.6-670.69" + wire \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable + attribute \src "build/ls180/gateware/ls180.v:667.6-667.63" + wire \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_we + attribute \src "build/ls180/gateware/ls180.v:668.6-668.69" + wire \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable + attribute \src "build/ls180/gateware/ls180.v:677.11-677.66" + wire width 3 \main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr + attribute \src "build/ls180/gateware/ls180.v:678.13-678.70" + wire width 25 \main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_dat_r + attribute \src "build/ls180/gateware/ls180.v:680.13-680.70" + wire width 25 \main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_dat_w + attribute \src "build/ls180/gateware/ls180.v:679.6-679.60" + wire \main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_we + attribute \src "build/ls180/gateware/ls180.v:694.6-694.51" + wire \main_sdram_bankmachine2_cmd_buffer_sink_first + attribute \src "build/ls180/gateware/ls180.v:695.6-695.50" + wire \main_sdram_bankmachine2_cmd_buffer_sink_last + attribute \src "build/ls180/gateware/ls180.v:697.13-697.65" + wire width 22 \main_sdram_bankmachine2_cmd_buffer_sink_payload_addr + attribute \src "build/ls180/gateware/ls180.v:696.6-696.56" + wire \main_sdram_bankmachine2_cmd_buffer_sink_payload_we + attribute \src "build/ls180/gateware/ls180.v:693.6-693.51" + wire \main_sdram_bankmachine2_cmd_buffer_sink_ready + attribute \src "build/ls180/gateware/ls180.v:692.6-692.51" + wire \main_sdram_bankmachine2_cmd_buffer_sink_valid + attribute \src "build/ls180/gateware/ls180.v:700.5-700.52" + wire \main_sdram_bankmachine2_cmd_buffer_source_first + attribute \src "build/ls180/gateware/ls180.v:701.5-701.51" + wire \main_sdram_bankmachine2_cmd_buffer_source_last + attribute \src "build/ls180/gateware/ls180.v:703.12-703.66" + wire width 22 \main_sdram_bankmachine2_cmd_buffer_source_payload_addr + attribute \src "build/ls180/gateware/ls180.v:702.5-702.57" + wire \main_sdram_bankmachine2_cmd_buffer_source_payload_we + attribute \src "build/ls180/gateware/ls180.v:699.6-699.53" + wire \main_sdram_bankmachine2_cmd_buffer_source_ready + attribute \src "build/ls180/gateware/ls180.v:698.5-698.52" + wire \main_sdram_bankmachine2_cmd_buffer_source_valid + attribute \src "build/ls180/gateware/ls180.v:646.12-646.49" + wire width 13 \main_sdram_bankmachine2_cmd_payload_a + attribute \src "build/ls180/gateware/ls180.v:647.12-647.50" + wire width 2 \main_sdram_bankmachine2_cmd_payload_ba + attribute \src "build/ls180/gateware/ls180.v:648.5-648.44" + wire \main_sdram_bankmachine2_cmd_payload_cas + attribute \src "build/ls180/gateware/ls180.v:651.5-651.47" + wire \main_sdram_bankmachine2_cmd_payload_is_cmd + attribute \src "build/ls180/gateware/ls180.v:652.5-652.48" + wire \main_sdram_bankmachine2_cmd_payload_is_read + attribute \src "build/ls180/gateware/ls180.v:653.5-653.49" + wire \main_sdram_bankmachine2_cmd_payload_is_write + attribute \src "build/ls180/gateware/ls180.v:649.5-649.44" + wire \main_sdram_bankmachine2_cmd_payload_ras + attribute \src "build/ls180/gateware/ls180.v:650.5-650.43" + wire \main_sdram_bankmachine2_cmd_payload_we + attribute \src "build/ls180/gateware/ls180.v:645.5-645.38" + wire \main_sdram_bankmachine2_cmd_ready + attribute \src "build/ls180/gateware/ls180.v:644.5-644.38" + wire \main_sdram_bankmachine2_cmd_valid + attribute \src "build/ls180/gateware/ls180.v:643.5-643.40" + wire \main_sdram_bankmachine2_refresh_gnt + attribute \src "build/ls180/gateware/ls180.v:642.6-642.41" + wire \main_sdram_bankmachine2_refresh_req + attribute \src "build/ls180/gateware/ls180.v:638.13-638.45" + wire width 22 \main_sdram_bankmachine2_req_addr + attribute \src "build/ls180/gateware/ls180.v:639.6-639.38" + wire \main_sdram_bankmachine2_req_lock + attribute \src "build/ls180/gateware/ls180.v:641.5-641.44" + wire \main_sdram_bankmachine2_req_rdata_valid + attribute \src "build/ls180/gateware/ls180.v:636.6-636.39" + wire \main_sdram_bankmachine2_req_ready + attribute \src "build/ls180/gateware/ls180.v:635.6-635.39" + wire \main_sdram_bankmachine2_req_valid + attribute \src "build/ls180/gateware/ls180.v:640.5-640.44" + wire \main_sdram_bankmachine2_req_wdata_ready + attribute \src "build/ls180/gateware/ls180.v:637.6-637.36" + wire \main_sdram_bankmachine2_req_we + attribute \src "build/ls180/gateware/ls180.v:704.12-704.39" + wire width 13 \main_sdram_bankmachine2_row + attribute \src "build/ls180/gateware/ls180.v:708.5-708.38" + wire \main_sdram_bankmachine2_row_close + attribute \src "build/ls180/gateware/ls180.v:709.5-709.47" + wire \main_sdram_bankmachine2_row_col_n_addr_sel + attribute \src "build/ls180/gateware/ls180.v:706.6-706.37" + wire \main_sdram_bankmachine2_row_hit + attribute \src "build/ls180/gateware/ls180.v:707.5-707.37" + wire \main_sdram_bankmachine2_row_open + attribute \src "build/ls180/gateware/ls180.v:705.5-705.39" + wire \main_sdram_bankmachine2_row_opened + attribute \no_retiming "true" + attribute \src "build/ls180/gateware/ls180.v:716.32-716.69" + wire \main_sdram_bankmachine2_trascon_ready + attribute \src "build/ls180/gateware/ls180.v:715.6-715.43" + wire \main_sdram_bankmachine2_trascon_valid + attribute \no_retiming "true" + attribute \src "build/ls180/gateware/ls180.v:714.32-714.68" + wire \main_sdram_bankmachine2_trccon_ready + attribute \src "build/ls180/gateware/ls180.v:713.6-713.42" + wire \main_sdram_bankmachine2_trccon_valid + attribute \src "build/ls180/gateware/ls180.v:712.11-712.48" + wire width 3 \main_sdram_bankmachine2_twtpcon_count + attribute \no_retiming "true" + attribute \src "build/ls180/gateware/ls180.v:711.32-711.69" + wire \main_sdram_bankmachine2_twtpcon_ready + attribute \src "build/ls180/gateware/ls180.v:710.6-710.43" + wire \main_sdram_bankmachine2_twtpcon_valid + attribute \src "build/ls180/gateware/ls180.v:736.5-736.43" + wire \main_sdram_bankmachine3_auto_precharge + attribute \src "build/ls180/gateware/ls180.v:758.11-758.63" + wire width 3 \main_sdram_bankmachine3_cmd_buffer_lookahead_consume + attribute \src "build/ls180/gateware/ls180.v:763.6-763.58" + wire \main_sdram_bankmachine3_cmd_buffer_lookahead_do_read + attribute \src "build/ls180/gateware/ls180.v:768.6-768.64" + wire \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_first + attribute \src "build/ls180/gateware/ls180.v:769.6-769.63" + wire \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_last + attribute \src "build/ls180/gateware/ls180.v:767.13-767.78" + wire width 22 \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_addr + attribute \src "build/ls180/gateware/ls180.v:766.6-766.69" + wire \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_we + attribute \src "build/ls180/gateware/ls180.v:772.6-772.65" + wire \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_first + attribute \src "build/ls180/gateware/ls180.v:773.6-773.64" + wire \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_last + attribute \src "build/ls180/gateware/ls180.v:771.13-771.79" + wire width 22 \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr + attribute \src "build/ls180/gateware/ls180.v:770.6-770.70" + wire \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we + attribute \src "build/ls180/gateware/ls180.v:755.11-755.61" + wire width 4 \main_sdram_bankmachine3_cmd_buffer_lookahead_level + attribute \src "build/ls180/gateware/ls180.v:757.11-757.63" + wire width 3 \main_sdram_bankmachine3_cmd_buffer_lookahead_produce + attribute \src "build/ls180/gateware/ls180.v:764.12-764.67" + wire width 3 \main_sdram_bankmachine3_cmd_buffer_lookahead_rdport_adr + attribute \src "build/ls180/gateware/ls180.v:765.13-765.70" + wire width 25 \main_sdram_bankmachine3_cmd_buffer_lookahead_rdport_dat_r + attribute \src "build/ls180/gateware/ls180.v:756.5-756.57" + wire \main_sdram_bankmachine3_cmd_buffer_lookahead_replace + attribute \src "build/ls180/gateware/ls180.v:739.5-739.60" + wire \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_first + attribute \src "build/ls180/gateware/ls180.v:740.5-740.59" + wire \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_last + attribute \src "build/ls180/gateware/ls180.v:742.13-742.75" + wire width 22 \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_payload_addr + attribute \src "build/ls180/gateware/ls180.v:741.6-741.66" + wire \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_payload_we + attribute \src "build/ls180/gateware/ls180.v:738.6-738.61" + wire \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_ready + attribute \src "build/ls180/gateware/ls180.v:737.6-737.61" + wire \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_valid + attribute \src "build/ls180/gateware/ls180.v:745.6-745.63" + wire \main_sdram_bankmachine3_cmd_buffer_lookahead_source_first + attribute \src "build/ls180/gateware/ls180.v:746.6-746.62" + wire \main_sdram_bankmachine3_cmd_buffer_lookahead_source_last + attribute \src "build/ls180/gateware/ls180.v:748.13-748.77" + wire width 22 \main_sdram_bankmachine3_cmd_buffer_lookahead_source_payload_addr + attribute \src "build/ls180/gateware/ls180.v:747.6-747.68" + wire \main_sdram_bankmachine3_cmd_buffer_lookahead_source_payload_we + attribute \src "build/ls180/gateware/ls180.v:744.6-744.63" + wire \main_sdram_bankmachine3_cmd_buffer_lookahead_source_ready + attribute \src "build/ls180/gateware/ls180.v:743.6-743.63" + wire \main_sdram_bankmachine3_cmd_buffer_lookahead_source_valid + attribute \src "build/ls180/gateware/ls180.v:753.13-753.71" + wire width 25 \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_din + attribute \src "build/ls180/gateware/ls180.v:754.13-754.72" + wire width 25 \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout + attribute \src "build/ls180/gateware/ls180.v:751.6-751.63" + wire \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_re + attribute \src "build/ls180/gateware/ls180.v:752.6-752.69" + wire \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable + attribute \src "build/ls180/gateware/ls180.v:749.6-749.63" + wire \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_we + attribute \src "build/ls180/gateware/ls180.v:750.6-750.69" + wire \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable + attribute \src "build/ls180/gateware/ls180.v:759.11-759.66" + wire width 3 \main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr + attribute \src "build/ls180/gateware/ls180.v:760.13-760.70" + wire width 25 \main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_dat_r + attribute \src "build/ls180/gateware/ls180.v:762.13-762.70" + wire width 25 \main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_dat_w + attribute \src "build/ls180/gateware/ls180.v:761.6-761.60" + wire \main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_we + attribute \src "build/ls180/gateware/ls180.v:776.6-776.51" + wire \main_sdram_bankmachine3_cmd_buffer_sink_first + attribute \src "build/ls180/gateware/ls180.v:777.6-777.50" + wire \main_sdram_bankmachine3_cmd_buffer_sink_last + attribute \src "build/ls180/gateware/ls180.v:779.13-779.65" + wire width 22 \main_sdram_bankmachine3_cmd_buffer_sink_payload_addr + attribute \src "build/ls180/gateware/ls180.v:778.6-778.56" + wire \main_sdram_bankmachine3_cmd_buffer_sink_payload_we + attribute \src "build/ls180/gateware/ls180.v:775.6-775.51" + wire \main_sdram_bankmachine3_cmd_buffer_sink_ready + attribute \src "build/ls180/gateware/ls180.v:774.6-774.51" + wire \main_sdram_bankmachine3_cmd_buffer_sink_valid + attribute \src "build/ls180/gateware/ls180.v:782.5-782.52" + wire \main_sdram_bankmachine3_cmd_buffer_source_first + attribute \src "build/ls180/gateware/ls180.v:783.5-783.51" + wire \main_sdram_bankmachine3_cmd_buffer_source_last + attribute \src "build/ls180/gateware/ls180.v:785.12-785.66" + wire width 22 \main_sdram_bankmachine3_cmd_buffer_source_payload_addr + attribute \src "build/ls180/gateware/ls180.v:784.5-784.57" + wire \main_sdram_bankmachine3_cmd_buffer_source_payload_we + attribute \src "build/ls180/gateware/ls180.v:781.6-781.53" + wire \main_sdram_bankmachine3_cmd_buffer_source_ready + attribute \src "build/ls180/gateware/ls180.v:780.5-780.52" + wire \main_sdram_bankmachine3_cmd_buffer_source_valid + attribute \src "build/ls180/gateware/ls180.v:728.12-728.49" + wire width 13 \main_sdram_bankmachine3_cmd_payload_a + attribute \src "build/ls180/gateware/ls180.v:729.12-729.50" + wire width 2 \main_sdram_bankmachine3_cmd_payload_ba + attribute \src "build/ls180/gateware/ls180.v:730.5-730.44" + wire \main_sdram_bankmachine3_cmd_payload_cas + attribute \src "build/ls180/gateware/ls180.v:733.5-733.47" + wire \main_sdram_bankmachine3_cmd_payload_is_cmd + attribute \src "build/ls180/gateware/ls180.v:734.5-734.48" + wire \main_sdram_bankmachine3_cmd_payload_is_read + attribute \src "build/ls180/gateware/ls180.v:735.5-735.49" + wire \main_sdram_bankmachine3_cmd_payload_is_write + attribute \src "build/ls180/gateware/ls180.v:731.5-731.44" + wire \main_sdram_bankmachine3_cmd_payload_ras + attribute \src "build/ls180/gateware/ls180.v:732.5-732.43" + wire \main_sdram_bankmachine3_cmd_payload_we + attribute \src "build/ls180/gateware/ls180.v:727.5-727.38" + wire \main_sdram_bankmachine3_cmd_ready + attribute \src "build/ls180/gateware/ls180.v:726.5-726.38" + wire \main_sdram_bankmachine3_cmd_valid + attribute \src "build/ls180/gateware/ls180.v:725.5-725.40" + wire \main_sdram_bankmachine3_refresh_gnt + attribute \src "build/ls180/gateware/ls180.v:724.6-724.41" + wire \main_sdram_bankmachine3_refresh_req + attribute \src "build/ls180/gateware/ls180.v:720.13-720.45" + wire width 22 \main_sdram_bankmachine3_req_addr + attribute \src "build/ls180/gateware/ls180.v:721.6-721.38" + wire \main_sdram_bankmachine3_req_lock + attribute \src "build/ls180/gateware/ls180.v:723.5-723.44" + wire \main_sdram_bankmachine3_req_rdata_valid + attribute \src "build/ls180/gateware/ls180.v:718.6-718.39" + wire \main_sdram_bankmachine3_req_ready + attribute \src "build/ls180/gateware/ls180.v:717.6-717.39" + wire \main_sdram_bankmachine3_req_valid + attribute \src "build/ls180/gateware/ls180.v:722.5-722.44" + wire \main_sdram_bankmachine3_req_wdata_ready + attribute \src "build/ls180/gateware/ls180.v:719.6-719.36" + wire \main_sdram_bankmachine3_req_we + attribute \src "build/ls180/gateware/ls180.v:786.12-786.39" + wire width 13 \main_sdram_bankmachine3_row + attribute \src "build/ls180/gateware/ls180.v:790.5-790.38" + wire \main_sdram_bankmachine3_row_close + attribute \src "build/ls180/gateware/ls180.v:791.5-791.47" + wire \main_sdram_bankmachine3_row_col_n_addr_sel + attribute \src "build/ls180/gateware/ls180.v:788.6-788.37" + wire \main_sdram_bankmachine3_row_hit + attribute \src "build/ls180/gateware/ls180.v:789.5-789.37" + wire \main_sdram_bankmachine3_row_open + attribute \src "build/ls180/gateware/ls180.v:787.5-787.39" + wire \main_sdram_bankmachine3_row_opened + attribute \no_retiming "true" + attribute \src "build/ls180/gateware/ls180.v:798.32-798.69" + wire \main_sdram_bankmachine3_trascon_ready + attribute \src "build/ls180/gateware/ls180.v:797.6-797.43" + wire \main_sdram_bankmachine3_trascon_valid + attribute \no_retiming "true" + attribute \src "build/ls180/gateware/ls180.v:796.32-796.68" + wire \main_sdram_bankmachine3_trccon_ready + attribute \src "build/ls180/gateware/ls180.v:795.6-795.42" + wire \main_sdram_bankmachine3_trccon_valid + attribute \src "build/ls180/gateware/ls180.v:794.11-794.48" + wire width 3 \main_sdram_bankmachine3_twtpcon_count + attribute \no_retiming "true" + attribute \src "build/ls180/gateware/ls180.v:793.32-793.69" + wire \main_sdram_bankmachine3_twtpcon_ready + attribute \src "build/ls180/gateware/ls180.v:792.6-792.43" + wire \main_sdram_bankmachine3_twtpcon_valid + attribute \src "build/ls180/gateware/ls180.v:800.6-800.28" + wire \main_sdram_cas_allowed + attribute \src "build/ls180/gateware/ls180.v:818.6-818.30" + wire \main_sdram_choose_cmd_ce + attribute \src "build/ls180/gateware/ls180.v:807.13-807.48" + wire width 13 \main_sdram_choose_cmd_cmd_payload_a + attribute \src "build/ls180/gateware/ls180.v:808.12-808.48" + wire width 2 \main_sdram_choose_cmd_cmd_payload_ba + attribute \src "build/ls180/gateware/ls180.v:809.5-809.42" + wire \main_sdram_choose_cmd_cmd_payload_cas + attribute \src "build/ls180/gateware/ls180.v:812.6-812.46" + wire \main_sdram_choose_cmd_cmd_payload_is_cmd + attribute \src "build/ls180/gateware/ls180.v:813.6-813.47" + wire \main_sdram_choose_cmd_cmd_payload_is_read + attribute \src "build/ls180/gateware/ls180.v:814.6-814.48" + wire \main_sdram_choose_cmd_cmd_payload_is_write + attribute \src "build/ls180/gateware/ls180.v:810.5-810.42" + wire \main_sdram_choose_cmd_cmd_payload_ras + attribute \src "build/ls180/gateware/ls180.v:811.5-811.41" + wire \main_sdram_choose_cmd_cmd_payload_we + attribute \src "build/ls180/gateware/ls180.v:806.5-806.36" + wire \main_sdram_choose_cmd_cmd_ready + attribute \src "build/ls180/gateware/ls180.v:805.6-805.37" + wire \main_sdram_choose_cmd_cmd_valid + attribute \src "build/ls180/gateware/ls180.v:817.11-817.38" + wire width 2 \main_sdram_choose_cmd_grant + attribute \src "build/ls180/gateware/ls180.v:816.12-816.41" + wire width 4 \main_sdram_choose_cmd_request + attribute \src "build/ls180/gateware/ls180.v:815.11-815.39" + wire width 4 \main_sdram_choose_cmd_valids + attribute \src "build/ls180/gateware/ls180.v:804.5-804.41" + wire \main_sdram_choose_cmd_want_activates + attribute \src "build/ls180/gateware/ls180.v:803.5-803.36" + wire \main_sdram_choose_cmd_want_cmds + attribute \src "build/ls180/gateware/ls180.v:801.5-801.37" + wire \main_sdram_choose_cmd_want_reads + attribute \src "build/ls180/gateware/ls180.v:802.5-802.38" + wire \main_sdram_choose_cmd_want_writes + attribute \src "build/ls180/gateware/ls180.v:836.6-836.30" + wire \main_sdram_choose_req_ce + attribute \src "build/ls180/gateware/ls180.v:825.13-825.48" + wire width 13 \main_sdram_choose_req_cmd_payload_a + attribute \src "build/ls180/gateware/ls180.v:826.12-826.48" + wire width 2 \main_sdram_choose_req_cmd_payload_ba + attribute \src "build/ls180/gateware/ls180.v:827.5-827.42" + wire \main_sdram_choose_req_cmd_payload_cas + attribute \src "build/ls180/gateware/ls180.v:830.6-830.46" + wire \main_sdram_choose_req_cmd_payload_is_cmd + attribute \src "build/ls180/gateware/ls180.v:831.6-831.47" + wire \main_sdram_choose_req_cmd_payload_is_read + attribute \src "build/ls180/gateware/ls180.v:832.6-832.48" + wire \main_sdram_choose_req_cmd_payload_is_write + attribute \src "build/ls180/gateware/ls180.v:828.5-828.42" + wire \main_sdram_choose_req_cmd_payload_ras + attribute \src "build/ls180/gateware/ls180.v:829.5-829.41" + wire \main_sdram_choose_req_cmd_payload_we + attribute \src "build/ls180/gateware/ls180.v:824.5-824.36" + wire \main_sdram_choose_req_cmd_ready + attribute \src "build/ls180/gateware/ls180.v:823.6-823.37" + wire \main_sdram_choose_req_cmd_valid + attribute \src "build/ls180/gateware/ls180.v:835.11-835.38" + wire width 2 \main_sdram_choose_req_grant + attribute \src "build/ls180/gateware/ls180.v:834.12-834.41" + wire width 4 \main_sdram_choose_req_request + attribute \src "build/ls180/gateware/ls180.v:833.11-833.39" + wire width 4 \main_sdram_choose_req_valids + attribute \src "build/ls180/gateware/ls180.v:822.5-822.41" + wire \main_sdram_choose_req_want_activates + attribute \src "build/ls180/gateware/ls180.v:821.6-821.37" + wire \main_sdram_choose_req_want_cmds + attribute \src "build/ls180/gateware/ls180.v:819.5-819.37" + wire \main_sdram_choose_req_want_reads + attribute \src "build/ls180/gateware/ls180.v:820.5-820.38" + wire \main_sdram_choose_req_want_writes + attribute \src "build/ls180/gateware/ls180.v:380.6-380.20" + wire \main_sdram_cke + attribute \src "build/ls180/gateware/ls180.v:448.5-448.24" + wire \main_sdram_cmd_last + attribute \src "build/ls180/gateware/ls180.v:449.12-449.36" + wire width 13 \main_sdram_cmd_payload_a + attribute \src "build/ls180/gateware/ls180.v:450.11-450.36" + wire width 2 \main_sdram_cmd_payload_ba + attribute \src "build/ls180/gateware/ls180.v:451.5-451.31" + wire \main_sdram_cmd_payload_cas + attribute \src "build/ls180/gateware/ls180.v:454.5-454.35" + wire \main_sdram_cmd_payload_is_read + attribute \src "build/ls180/gateware/ls180.v:455.5-455.36" + wire \main_sdram_cmd_payload_is_write + attribute \src "build/ls180/gateware/ls180.v:452.5-452.31" + wire \main_sdram_cmd_payload_ras + attribute \src "build/ls180/gateware/ls180.v:453.5-453.30" + wire \main_sdram_cmd_payload_we + attribute \src "build/ls180/gateware/ls180.v:447.5-447.25" + wire \main_sdram_cmd_ready + attribute \src "build/ls180/gateware/ls180.v:446.5-446.25" + wire \main_sdram_cmd_valid + attribute \src "build/ls180/gateware/ls180.v:388.6-388.32" + wire \main_sdram_command_issue_r + attribute \src "build/ls180/gateware/ls180.v:387.6-387.33" + wire \main_sdram_command_issue_re + attribute \src "build/ls180/gateware/ls180.v:390.5-390.31" + wire \main_sdram_command_issue_w + attribute \src "build/ls180/gateware/ls180.v:389.6-389.33" + wire \main_sdram_command_issue_we + attribute \src "build/ls180/gateware/ls180.v:386.5-386.26" + wire \main_sdram_command_re + attribute \src "build/ls180/gateware/ls180.v:385.11-385.37" + wire width 6 \main_sdram_command_storage + attribute \src "build/ls180/gateware/ls180.v:439.5-439.28" + wire \main_sdram_dfi_p0_act_n + attribute \src "build/ls180/gateware/ls180.v:430.12-430.37" + wire width 13 \main_sdram_dfi_p0_address + attribute \src "build/ls180/gateware/ls180.v:431.11-431.33" + wire width 2 \main_sdram_dfi_p0_bank + attribute \src "build/ls180/gateware/ls180.v:432.5-432.28" + wire \main_sdram_dfi_p0_cas_n + attribute \src "build/ls180/gateware/ls180.v:436.6-436.27" + wire \main_sdram_dfi_p0_cke + attribute \src "build/ls180/gateware/ls180.v:433.5-433.27" + wire \main_sdram_dfi_p0_cs_n + attribute \src "build/ls180/gateware/ls180.v:437.6-437.27" + wire \main_sdram_dfi_p0_odt + attribute \src "build/ls180/gateware/ls180.v:434.5-434.28" + wire \main_sdram_dfi_p0_ras_n + attribute \src "build/ls180/gateware/ls180.v:444.13-444.37" + wire width 16 \main_sdram_dfi_p0_rddata + attribute \src "build/ls180/gateware/ls180.v:443.5-443.32" + wire \main_sdram_dfi_p0_rddata_en + attribute \src "build/ls180/gateware/ls180.v:445.6-445.36" + wire \main_sdram_dfi_p0_rddata_valid + attribute \src "build/ls180/gateware/ls180.v:438.6-438.31" + wire \main_sdram_dfi_p0_reset_n + attribute \src "build/ls180/gateware/ls180.v:435.5-435.27" + wire \main_sdram_dfi_p0_we_n + attribute \src "build/ls180/gateware/ls180.v:440.13-440.37" + wire width 16 \main_sdram_dfi_p0_wrdata + attribute \src "build/ls180/gateware/ls180.v:441.5-441.32" + wire \main_sdram_dfi_p0_wrdata_en + attribute \src "build/ls180/gateware/ls180.v:442.12-442.41" + wire width 2 \main_sdram_dfi_p0_wrdata_mask + attribute \src "build/ls180/gateware/ls180.v:854.5-854.19" + wire \main_sdram_en0 + attribute \src "build/ls180/gateware/ls180.v:857.5-857.19" + wire \main_sdram_en1 + attribute \src "build/ls180/gateware/ls180.v:860.6-860.30" + wire \main_sdram_go_to_refresh + attribute \src "build/ls180/gateware/ls180.v:402.13-402.44" + wire width 22 \main_sdram_interface_bank0_addr + attribute \src "build/ls180/gateware/ls180.v:403.6-403.37" + wire \main_sdram_interface_bank0_lock + attribute \src "build/ls180/gateware/ls180.v:405.6-405.44" + wire \main_sdram_interface_bank0_rdata_valid + attribute \src "build/ls180/gateware/ls180.v:400.6-400.38" + wire \main_sdram_interface_bank0_ready + attribute \src "build/ls180/gateware/ls180.v:399.6-399.38" + wire \main_sdram_interface_bank0_valid + attribute \src "build/ls180/gateware/ls180.v:404.6-404.44" + wire \main_sdram_interface_bank0_wdata_ready + attribute \src "build/ls180/gateware/ls180.v:401.6-401.35" + wire \main_sdram_interface_bank0_we + attribute \src "build/ls180/gateware/ls180.v:409.13-409.44" + wire width 22 \main_sdram_interface_bank1_addr + attribute \src "build/ls180/gateware/ls180.v:410.6-410.37" + wire \main_sdram_interface_bank1_lock + attribute \src "build/ls180/gateware/ls180.v:412.6-412.44" + wire \main_sdram_interface_bank1_rdata_valid + attribute \src "build/ls180/gateware/ls180.v:407.6-407.38" + wire \main_sdram_interface_bank1_ready + attribute \src "build/ls180/gateware/ls180.v:406.6-406.38" + wire \main_sdram_interface_bank1_valid + attribute \src "build/ls180/gateware/ls180.v:411.6-411.44" + wire \main_sdram_interface_bank1_wdata_ready + attribute \src "build/ls180/gateware/ls180.v:408.6-408.35" + wire \main_sdram_interface_bank1_we + attribute \src "build/ls180/gateware/ls180.v:416.13-416.44" + wire width 22 \main_sdram_interface_bank2_addr + attribute \src "build/ls180/gateware/ls180.v:417.6-417.37" + wire \main_sdram_interface_bank2_lock + attribute \src "build/ls180/gateware/ls180.v:419.6-419.44" + wire \main_sdram_interface_bank2_rdata_valid + attribute \src "build/ls180/gateware/ls180.v:414.6-414.38" + wire \main_sdram_interface_bank2_ready + attribute \src "build/ls180/gateware/ls180.v:413.6-413.38" + wire \main_sdram_interface_bank2_valid + attribute \src "build/ls180/gateware/ls180.v:418.6-418.44" + wire \main_sdram_interface_bank2_wdata_ready + attribute \src "build/ls180/gateware/ls180.v:415.6-415.35" + wire \main_sdram_interface_bank2_we + attribute \src "build/ls180/gateware/ls180.v:423.13-423.44" + wire width 22 \main_sdram_interface_bank3_addr + attribute \src "build/ls180/gateware/ls180.v:424.6-424.37" + wire \main_sdram_interface_bank3_lock + attribute \src "build/ls180/gateware/ls180.v:426.6-426.44" + wire \main_sdram_interface_bank3_rdata_valid + attribute \src "build/ls180/gateware/ls180.v:421.6-421.38" + wire \main_sdram_interface_bank3_ready + attribute \src "build/ls180/gateware/ls180.v:420.6-420.38" + wire \main_sdram_interface_bank3_valid + attribute \src "build/ls180/gateware/ls180.v:425.6-425.44" + wire \main_sdram_interface_bank3_wdata_ready + attribute \src "build/ls180/gateware/ls180.v:422.6-422.35" + wire \main_sdram_interface_bank3_we + attribute \src "build/ls180/gateware/ls180.v:429.13-429.39" + wire width 16 \main_sdram_interface_rdata + attribute \src "build/ls180/gateware/ls180.v:427.12-427.38" + wire width 16 \main_sdram_interface_wdata + attribute \src "build/ls180/gateware/ls180.v:428.11-428.40" + wire width 2 \main_sdram_interface_wdata_we + attribute \src "build/ls180/gateware/ls180.v:340.5-340.29" + wire \main_sdram_inti_p0_act_n + attribute \src "build/ls180/gateware/ls180.v:331.13-331.39" + wire width 13 \main_sdram_inti_p0_address + attribute \src "build/ls180/gateware/ls180.v:332.12-332.35" + wire width 2 \main_sdram_inti_p0_bank + attribute \src "build/ls180/gateware/ls180.v:333.5-333.29" + wire \main_sdram_inti_p0_cas_n + attribute \src "build/ls180/gateware/ls180.v:337.6-337.28" + wire \main_sdram_inti_p0_cke + attribute \src "build/ls180/gateware/ls180.v:334.5-334.28" + wire \main_sdram_inti_p0_cs_n + attribute \src "build/ls180/gateware/ls180.v:338.6-338.28" + wire \main_sdram_inti_p0_odt + attribute \src "build/ls180/gateware/ls180.v:335.5-335.29" + wire \main_sdram_inti_p0_ras_n + attribute \src "build/ls180/gateware/ls180.v:345.12-345.37" + wire width 16 \main_sdram_inti_p0_rddata + attribute \src "build/ls180/gateware/ls180.v:344.6-344.34" + wire \main_sdram_inti_p0_rddata_en + attribute \src "build/ls180/gateware/ls180.v:346.5-346.36" + wire \main_sdram_inti_p0_rddata_valid + attribute \src "build/ls180/gateware/ls180.v:339.6-339.32" + wire \main_sdram_inti_p0_reset_n + attribute \src "build/ls180/gateware/ls180.v:336.5-336.28" + wire \main_sdram_inti_p0_we_n + attribute \src "build/ls180/gateware/ls180.v:341.13-341.38" + wire width 16 \main_sdram_inti_p0_wrdata + attribute \src "build/ls180/gateware/ls180.v:342.6-342.34" + wire \main_sdram_inti_p0_wrdata_en + attribute \src "build/ls180/gateware/ls180.v:343.12-343.42" + wire width 2 \main_sdram_inti_p0_wrdata_mask + attribute \src "build/ls180/gateware/ls180.v:372.5-372.31" + wire \main_sdram_master_p0_act_n + attribute \src "build/ls180/gateware/ls180.v:363.12-363.40" + wire width 13 \main_sdram_master_p0_address + attribute \src "build/ls180/gateware/ls180.v:364.11-364.36" + wire width 2 \main_sdram_master_p0_bank + attribute \src "build/ls180/gateware/ls180.v:365.5-365.31" + wire \main_sdram_master_p0_cas_n + attribute \src "build/ls180/gateware/ls180.v:369.5-369.29" + wire \main_sdram_master_p0_cke + attribute \src "build/ls180/gateware/ls180.v:366.5-366.30" + wire \main_sdram_master_p0_cs_n + attribute \src "build/ls180/gateware/ls180.v:370.5-370.29" + wire \main_sdram_master_p0_odt + attribute \src "build/ls180/gateware/ls180.v:367.5-367.31" + wire \main_sdram_master_p0_ras_n + attribute \src "build/ls180/gateware/ls180.v:377.13-377.40" + wire width 16 \main_sdram_master_p0_rddata + attribute \src "build/ls180/gateware/ls180.v:376.5-376.35" + wire \main_sdram_master_p0_rddata_en + attribute \src "build/ls180/gateware/ls180.v:378.6-378.39" + wire \main_sdram_master_p0_rddata_valid + attribute \src "build/ls180/gateware/ls180.v:371.5-371.33" + wire \main_sdram_master_p0_reset_n + attribute \src "build/ls180/gateware/ls180.v:368.5-368.30" + wire \main_sdram_master_p0_we_n + attribute \src "build/ls180/gateware/ls180.v:373.12-373.39" + wire width 16 \main_sdram_master_p0_wrdata + attribute \src "build/ls180/gateware/ls180.v:374.5-374.35" + wire \main_sdram_master_p0_wrdata_en + attribute \src "build/ls180/gateware/ls180.v:375.11-375.43" + wire width 2 \main_sdram_master_p0_wrdata_mask + attribute \src "build/ls180/gateware/ls180.v:855.6-855.26" + wire \main_sdram_max_time0 + attribute \src "build/ls180/gateware/ls180.v:858.6-858.26" + wire \main_sdram_max_time1 + attribute \src "build/ls180/gateware/ls180.v:837.12-837.28" + wire width 13 \main_sdram_nop_a + attribute \src "build/ls180/gateware/ls180.v:838.11-838.28" + wire width 2 \main_sdram_nop_ba + attribute \src "build/ls180/gateware/ls180.v:381.6-381.20" + wire \main_sdram_odt + attribute \src "build/ls180/gateware/ls180.v:464.5-464.31" + wire \main_sdram_postponer_count + attribute \src "build/ls180/gateware/ls180.v:462.6-462.32" + wire \main_sdram_postponer_req_i + attribute \src "build/ls180/gateware/ls180.v:463.5-463.31" + wire \main_sdram_postponer_req_o + attribute \src "build/ls180/gateware/ls180.v:799.6-799.28" + wire \main_sdram_ras_allowed + attribute \src "build/ls180/gateware/ls180.v:384.5-384.18" + wire \main_sdram_re + attribute \src "build/ls180/gateware/ls180.v:852.6-852.31" + wire \main_sdram_read_available + attribute \src "build/ls180/gateware/ls180.v:382.6-382.24" + wire \main_sdram_reset_n + attribute \src "build/ls180/gateware/ls180.v:379.6-379.20" + wire \main_sdram_sel + attribute \src "build/ls180/gateware/ls180.v:470.5-470.31" + wire \main_sdram_sequencer_count + attribute \src "build/ls180/gateware/ls180.v:469.11-469.39" + wire width 4 \main_sdram_sequencer_counter + attribute \src "build/ls180/gateware/ls180.v:466.6-466.32" + wire \main_sdram_sequencer_done0 + attribute \src "build/ls180/gateware/ls180.v:468.5-468.31" + wire \main_sdram_sequencer_done1 + attribute \src "build/ls180/gateware/ls180.v:465.5-465.32" + wire \main_sdram_sequencer_start0 + attribute \src "build/ls180/gateware/ls180.v:467.6-467.33" + wire \main_sdram_sequencer_start1 + attribute \src "build/ls180/gateware/ls180.v:356.6-356.31" + wire \main_sdram_slave_p0_act_n + attribute \src "build/ls180/gateware/ls180.v:347.13-347.40" + wire width 13 \main_sdram_slave_p0_address + attribute \src "build/ls180/gateware/ls180.v:348.12-348.36" + wire width 2 \main_sdram_slave_p0_bank + attribute \src "build/ls180/gateware/ls180.v:349.6-349.31" + wire \main_sdram_slave_p0_cas_n + attribute \src "build/ls180/gateware/ls180.v:353.6-353.29" + wire \main_sdram_slave_p0_cke + attribute \src "build/ls180/gateware/ls180.v:350.6-350.30" + wire \main_sdram_slave_p0_cs_n + attribute \src "build/ls180/gateware/ls180.v:354.6-354.29" + wire \main_sdram_slave_p0_odt + attribute \src "build/ls180/gateware/ls180.v:351.6-351.31" + wire \main_sdram_slave_p0_ras_n + attribute \src "build/ls180/gateware/ls180.v:361.12-361.38" + wire width 16 \main_sdram_slave_p0_rddata + attribute \src "build/ls180/gateware/ls180.v:360.6-360.35" + wire \main_sdram_slave_p0_rddata_en + attribute \src "build/ls180/gateware/ls180.v:362.5-362.37" + wire \main_sdram_slave_p0_rddata_valid + attribute \src "build/ls180/gateware/ls180.v:355.6-355.33" + wire \main_sdram_slave_p0_reset_n + attribute \src "build/ls180/gateware/ls180.v:352.6-352.30" + wire \main_sdram_slave_p0_we_n + attribute \src "build/ls180/gateware/ls180.v:357.13-357.39" + wire width 16 \main_sdram_slave_p0_wrdata + attribute \src "build/ls180/gateware/ls180.v:358.6-358.35" + wire \main_sdram_slave_p0_wrdata_en + attribute \src "build/ls180/gateware/ls180.v:359.12-359.43" + wire width 2 \main_sdram_slave_p0_wrdata_mask + attribute \src "build/ls180/gateware/ls180.v:397.12-397.29" + wire width 16 \main_sdram_status + attribute \src "build/ls180/gateware/ls180.v:840.5-840.24" + wire \main_sdram_steerer0 + attribute \src "build/ls180/gateware/ls180.v:841.5-841.24" + wire \main_sdram_steerer1 + attribute \src "build/ls180/gateware/ls180.v:839.11-839.33" + wire width 2 \main_sdram_steerer_sel + attribute \src "build/ls180/gateware/ls180.v:383.11-383.29" + wire width 4 \main_sdram_storage + attribute \src "build/ls180/gateware/ls180.v:848.5-848.29" + wire \main_sdram_tccdcon_count + attribute \no_retiming "true" + attribute \src "build/ls180/gateware/ls180.v:847.32-847.56" + wire \main_sdram_tccdcon_ready + attribute \src "build/ls180/gateware/ls180.v:846.6-846.30" + wire \main_sdram_tccdcon_valid + attribute \no_retiming "true" + attribute \src "build/ls180/gateware/ls180.v:845.32-845.56" + wire \main_sdram_tfawcon_ready + attribute \src "build/ls180/gateware/ls180.v:844.6-844.30" + wire \main_sdram_tfawcon_valid + attribute \src "build/ls180/gateware/ls180.v:856.11-856.27" + wire width 5 \main_sdram_time0 + attribute \src "build/ls180/gateware/ls180.v:859.11-859.27" + wire width 4 \main_sdram_time1 + attribute \src "build/ls180/gateware/ls180.v:459.12-459.35" + wire width 10 \main_sdram_timer_count0 + attribute \src "build/ls180/gateware/ls180.v:461.11-461.34" + wire width 10 \main_sdram_timer_count1 + attribute \src "build/ls180/gateware/ls180.v:458.6-458.28" + wire \main_sdram_timer_done0 + attribute \src "build/ls180/gateware/ls180.v:460.6-460.28" + wire \main_sdram_timer_done1 + attribute \src "build/ls180/gateware/ls180.v:457.6-457.27" + wire \main_sdram_timer_wait + attribute \no_retiming "true" + attribute \src "build/ls180/gateware/ls180.v:843.32-843.56" + wire \main_sdram_trrdcon_ready + attribute \src "build/ls180/gateware/ls180.v:842.6-842.30" + wire \main_sdram_trrdcon_valid + attribute \src "build/ls180/gateware/ls180.v:851.11-851.35" + wire width 3 \main_sdram_twtrcon_count + attribute \no_retiming "true" + attribute \src "build/ls180/gateware/ls180.v:850.32-850.56" + wire \main_sdram_twtrcon_ready + attribute \src "build/ls180/gateware/ls180.v:849.6-849.30" + wire \main_sdram_twtrcon_valid + attribute \src "build/ls180/gateware/ls180.v:456.6-456.30" + wire \main_sdram_wants_refresh + attribute \src "build/ls180/gateware/ls180.v:398.6-398.19" + wire \main_sdram_we + attribute \src "build/ls180/gateware/ls180.v:396.5-396.25" + wire \main_sdram_wrdata_re + attribute \src "build/ls180/gateware/ls180.v:395.12-395.37" + wire width 16 \main_sdram_wrdata_storage + attribute \src "build/ls180/gateware/ls180.v:853.6-853.32" + wire \main_sdram_write_available + attribute \src "build/ls180/gateware/ls180.v:926.6-926.14" + wire \main_sel + attribute \src "build/ls180/gateware/ls180.v:906.6-906.17" + wire \main_start0 + attribute \src "build/ls180/gateware/ls180.v:915.5-915.16" + wire \main_start1 + attribute \src "build/ls180/gateware/ls180.v:920.6-920.24" + wire \main_status_status + attribute \src "build/ls180/gateware/ls180.v:921.6-921.20" + wire \main_status_we + attribute \src "build/ls180/gateware/ls180.v:880.5-880.22" + wire \main_wb_sdram_ack + attribute \src "build/ls180/gateware/ls180.v:874.13-874.30" + wire width 30 \main_wb_sdram_adr + attribute \src "build/ls180/gateware/ls180.v:883.12-883.29" + wire width 2 \main_wb_sdram_bte + attribute \src "build/ls180/gateware/ls180.v:882.12-882.29" + wire width 3 \main_wb_sdram_cti + attribute \src "build/ls180/gateware/ls180.v:878.6-878.23" + wire \main_wb_sdram_cyc + attribute \src "build/ls180/gateware/ls180.v:876.13-876.32" + wire width 32 \main_wb_sdram_dat_r + attribute \src "build/ls180/gateware/ls180.v:875.13-875.32" + wire width 32 \main_wb_sdram_dat_w + attribute \src "build/ls180/gateware/ls180.v:884.5-884.22" + wire \main_wb_sdram_err + attribute \src "build/ls180/gateware/ls180.v:877.12-877.29" + wire width 4 \main_wb_sdram_sel + attribute \src "build/ls180/gateware/ls180.v:879.6-879.23" + wire \main_wb_sdram_stb + attribute \src "build/ls180/gateware/ls180.v:881.6-881.22" + wire \main_wb_sdram_we + attribute \src "build/ls180/gateware/ls180.v:898.5-898.24" + wire \main_wdata_consumed + attribute \src "build/ls180/gateware/ls180.v:9366.12-9366.18" + wire width 16 \memadr + attribute \src "build/ls180/gateware/ls180.v:9386.11-9386.17" + wire width 10 \memdat + attribute \src "build/ls180/gateware/ls180.v:9387.11-9387.19" + wire width 10 \memdat_1 + attribute \src "build/ls180/gateware/ls180.v:9403.11-9403.19" + wire width 10 \memdat_2 + attribute \src "build/ls180/gateware/ls180.v:9404.11-9404.19" + wire width 10 \memdat_3 + attribute \src "build/ls180/gateware/ls180.v:9420.12-9420.20" + wire width 25 \memdat_4 + attribute \src "build/ls180/gateware/ls180.v:9434.12-9434.20" + wire width 25 \memdat_5 + attribute \src "build/ls180/gateware/ls180.v:9448.12-9448.20" + wire width 25 \memdat_6 + attribute \src "build/ls180/gateware/ls180.v:9462.12-9462.20" + wire width 25 \memdat_7 + attribute \src "build/ls180/gateware/ls180.v:9476.11-9476.19" + wire width 10 \memdat_8 + attribute \src "build/ls180/gateware/ls180.v:9490.11-9490.19" + wire width 10 \memdat_9 + attribute \src "build/ls180/gateware/ls180.v:312.6-312.13" + wire \por_clk + attribute \src "build/ls180/gateware/ls180.v:24.13-24.23" + wire output 20 \sdcard_clk + attribute \src "build/ls180/gateware/ls180.v:25.13-25.23" + wire inout 21 \sdcard_cmd + attribute \src "build/ls180/gateware/ls180.v:26.19-26.30" + wire width 4 inout 22 \sdcard_data + attribute \src "build/ls180/gateware/ls180.v:8.20-8.27" + wire width 13 output 4 \sdram_a + attribute \src "build/ls180/gateware/ls180.v:15.19-15.27" + wire width 2 output 11 \sdram_ba + attribute \src "build/ls180/gateware/ls180.v:12.13-12.24" + wire output 8 \sdram_cas_n + attribute \src "build/ls180/gateware/ls180.v:14.13-14.22" + wire output 10 \sdram_cke + attribute \src "build/ls180/gateware/ls180.v:13.13-13.23" + wire output 9 \sdram_cs_n + attribute \src "build/ls180/gateware/ls180.v:16.19-16.27" + wire width 2 output 12 \sdram_dm + attribute \src "build/ls180/gateware/ls180.v:9.20-9.28" + wire width 16 inout 5 \sdram_dq + attribute \src "build/ls180/gateware/ls180.v:11.13-11.24" + wire output 7 \sdram_ras_n + attribute \src "build/ls180/gateware/ls180.v:10.13-10.23" + wire output 6 \sdram_we_n + attribute \src "build/ls180/gateware/ls180.v:2423.6-2423.15" + wire \sdrio_clk + attribute \src "build/ls180/gateware/ls180.v:2424.6-2424.17" + wire \sdrio_clk_1 + attribute \src "build/ls180/gateware/ls180.v:2433.6-2433.18" + wire \sdrio_clk_10 + attribute \src "build/ls180/gateware/ls180.v:2434.6-2434.18" + wire \sdrio_clk_11 + attribute \src "build/ls180/gateware/ls180.v:2435.6-2435.18" + wire \sdrio_clk_12 + attribute \src "build/ls180/gateware/ls180.v:2436.6-2436.18" + wire \sdrio_clk_13 + attribute \src "build/ls180/gateware/ls180.v:2437.6-2437.18" + wire \sdrio_clk_14 + attribute \src "build/ls180/gateware/ls180.v:2438.6-2438.18" + wire \sdrio_clk_15 + attribute \src "build/ls180/gateware/ls180.v:2439.6-2439.18" + wire \sdrio_clk_16 + attribute \src "build/ls180/gateware/ls180.v:2440.6-2440.18" + wire \sdrio_clk_17 + attribute \src "build/ls180/gateware/ls180.v:2441.6-2441.18" + wire \sdrio_clk_18 + attribute \src "build/ls180/gateware/ls180.v:2442.6-2442.18" + wire \sdrio_clk_19 + attribute \src "build/ls180/gateware/ls180.v:2425.6-2425.17" + wire \sdrio_clk_2 + attribute \src "build/ls180/gateware/ls180.v:2446.6-2446.18" + wire \sdrio_clk_20 + attribute \src "build/ls180/gateware/ls180.v:2450.6-2450.18" + wire \sdrio_clk_21 + attribute \src "build/ls180/gateware/ls180.v:2454.6-2454.18" + wire \sdrio_clk_22 + attribute \src "build/ls180/gateware/ls180.v:2458.6-2458.18" + wire \sdrio_clk_23 + attribute \src "build/ls180/gateware/ls180.v:2462.6-2462.18" + wire \sdrio_clk_24 + attribute \src "build/ls180/gateware/ls180.v:2466.6-2466.18" + wire \sdrio_clk_25 + attribute \src "build/ls180/gateware/ls180.v:2470.6-2470.18" + wire \sdrio_clk_26 + attribute \src "build/ls180/gateware/ls180.v:2474.6-2474.18" + wire \sdrio_clk_27 + attribute \src "build/ls180/gateware/ls180.v:2478.6-2478.18" + wire \sdrio_clk_28 + attribute \src "build/ls180/gateware/ls180.v:2482.6-2482.18" + wire \sdrio_clk_29 + attribute \src "build/ls180/gateware/ls180.v:2426.6-2426.17" + wire \sdrio_clk_3 + attribute \src "build/ls180/gateware/ls180.v:2486.6-2486.18" + wire \sdrio_clk_30 + attribute \src "build/ls180/gateware/ls180.v:2490.6-2490.18" + wire \sdrio_clk_31 + attribute \src "build/ls180/gateware/ls180.v:2494.6-2494.18" + wire \sdrio_clk_32 + attribute \src "build/ls180/gateware/ls180.v:2498.6-2498.18" + wire \sdrio_clk_33 + attribute \src "build/ls180/gateware/ls180.v:2502.6-2502.18" + wire \sdrio_clk_34 + attribute \src "build/ls180/gateware/ls180.v:2506.6-2506.18" + wire \sdrio_clk_35 + attribute \src "build/ls180/gateware/ls180.v:2511.6-2511.18" + wire \sdrio_clk_36 + attribute \src "build/ls180/gateware/ls180.v:2515.6-2515.18" + wire \sdrio_clk_37 + attribute \src "build/ls180/gateware/ls180.v:2519.6-2519.18" + wire \sdrio_clk_38 + attribute \src "build/ls180/gateware/ls180.v:2523.6-2523.18" + wire \sdrio_clk_39 + attribute \src "build/ls180/gateware/ls180.v:2427.6-2427.17" + wire \sdrio_clk_4 + attribute \src "build/ls180/gateware/ls180.v:2527.6-2527.18" + wire \sdrio_clk_40 + attribute \src "build/ls180/gateware/ls180.v:2531.6-2531.18" + wire \sdrio_clk_41 + attribute \src "build/ls180/gateware/ls180.v:2532.6-2532.18" + wire \sdrio_clk_42 + attribute \src "build/ls180/gateware/ls180.v:2533.6-2533.18" + wire \sdrio_clk_43 + attribute \src "build/ls180/gateware/ls180.v:2534.6-2534.18" + wire \sdrio_clk_44 + attribute \src "build/ls180/gateware/ls180.v:2535.6-2535.18" + wire \sdrio_clk_45 + attribute \src "build/ls180/gateware/ls180.v:2536.6-2536.18" + wire \sdrio_clk_46 + attribute \src "build/ls180/gateware/ls180.v:2537.6-2537.18" + wire \sdrio_clk_47 + attribute \src "build/ls180/gateware/ls180.v:2538.6-2538.18" + wire \sdrio_clk_48 + attribute \src "build/ls180/gateware/ls180.v:2539.6-2539.18" + wire \sdrio_clk_49 + attribute \src "build/ls180/gateware/ls180.v:2428.6-2428.17" + wire \sdrio_clk_5 + attribute \src "build/ls180/gateware/ls180.v:2540.6-2540.18" + wire \sdrio_clk_50 + attribute \src "build/ls180/gateware/ls180.v:2541.6-2541.18" + wire \sdrio_clk_51 + attribute \src "build/ls180/gateware/ls180.v:2542.6-2542.18" + wire \sdrio_clk_52 + attribute \src "build/ls180/gateware/ls180.v:2543.6-2543.18" + wire \sdrio_clk_53 + attribute \src "build/ls180/gateware/ls180.v:2544.6-2544.18" + wire \sdrio_clk_54 + attribute \src "build/ls180/gateware/ls180.v:2545.6-2545.18" + wire \sdrio_clk_55 + attribute \src "build/ls180/gateware/ls180.v:2546.6-2546.18" + wire \sdrio_clk_56 + attribute \src "build/ls180/gateware/ls180.v:2547.6-2547.18" + wire \sdrio_clk_57 + attribute \src "build/ls180/gateware/ls180.v:2548.6-2548.18" + wire \sdrio_clk_58 + attribute \src "build/ls180/gateware/ls180.v:2549.6-2549.18" + wire \sdrio_clk_59 + attribute \src "build/ls180/gateware/ls180.v:2429.6-2429.17" + wire \sdrio_clk_6 + attribute \src "build/ls180/gateware/ls180.v:2550.6-2550.18" + wire \sdrio_clk_60 + attribute \src "build/ls180/gateware/ls180.v:2551.6-2551.18" + wire \sdrio_clk_61 + attribute \src "build/ls180/gateware/ls180.v:2552.6-2552.18" + wire \sdrio_clk_62 + attribute \src "build/ls180/gateware/ls180.v:2553.6-2553.18" + wire \sdrio_clk_63 + attribute \src "build/ls180/gateware/ls180.v:2554.6-2554.18" + wire \sdrio_clk_64 + attribute \src "build/ls180/gateware/ls180.v:2555.6-2555.18" + wire \sdrio_clk_65 + attribute \src "build/ls180/gateware/ls180.v:2556.6-2556.18" + wire \sdrio_clk_66 + attribute \src "build/ls180/gateware/ls180.v:2557.6-2557.18" + wire \sdrio_clk_67 + attribute \src "build/ls180/gateware/ls180.v:2558.6-2558.18" + wire \sdrio_clk_68 + attribute \src "build/ls180/gateware/ls180.v:2559.6-2559.18" + wire \sdrio_clk_69 + attribute \src "build/ls180/gateware/ls180.v:2430.6-2430.17" + wire \sdrio_clk_7 + attribute \src "build/ls180/gateware/ls180.v:2560.6-2560.18" + wire \sdrio_clk_70 + attribute \src "build/ls180/gateware/ls180.v:2561.6-2561.18" + wire \sdrio_clk_71 + attribute \src "build/ls180/gateware/ls180.v:2562.6-2562.18" + wire \sdrio_clk_72 + attribute \src "build/ls180/gateware/ls180.v:2563.6-2563.18" + wire \sdrio_clk_73 + attribute \src "build/ls180/gateware/ls180.v:2564.6-2564.18" + wire \sdrio_clk_74 + attribute \src "build/ls180/gateware/ls180.v:2565.6-2565.18" + wire \sdrio_clk_75 + attribute \src "build/ls180/gateware/ls180.v:2566.6-2566.18" + wire \sdrio_clk_76 + attribute \src "build/ls180/gateware/ls180.v:2567.6-2567.18" + wire \sdrio_clk_77 + attribute \src "build/ls180/gateware/ls180.v:2568.6-2568.18" + wire \sdrio_clk_78 + attribute \src "build/ls180/gateware/ls180.v:2569.6-2569.18" + wire \sdrio_clk_79 + attribute \src "build/ls180/gateware/ls180.v:2431.6-2431.17" + wire \sdrio_clk_8 + attribute \src "build/ls180/gateware/ls180.v:2570.6-2570.18" + wire \sdrio_clk_80 + attribute \src "build/ls180/gateware/ls180.v:2571.6-2571.18" + wire \sdrio_clk_81 + attribute \src "build/ls180/gateware/ls180.v:2572.6-2572.18" + wire \sdrio_clk_82 + attribute \src "build/ls180/gateware/ls180.v:2573.6-2573.18" + wire \sdrio_clk_83 + attribute \src "build/ls180/gateware/ls180.v:2432.6-2432.17" + wire \sdrio_clk_9 + attribute \src "build/ls180/gateware/ls180.v:6.13-6.22" + wire input 2 \serial_rx + attribute \src "build/ls180/gateware/ls180.v:5.13-5.22" + wire output 1 \serial_tx + attribute \src "build/ls180/gateware/ls180.v:19.13-19.27" + wire output 15 \spi_master_clk + attribute \src "build/ls180/gateware/ls180.v:21.13-21.28" + wire output 17 \spi_master_cs_n + attribute \src "build/ls180/gateware/ls180.v:22.13-22.28" + wire input 18 \spi_master_miso + attribute \src "build/ls180/gateware/ls180.v:20.13-20.28" + wire output 16 \spi_master_mosi + attribute \src "build/ls180/gateware/ls180.v:27.13-27.26" + wire output 23 \spisdcard_clk + attribute \src "build/ls180/gateware/ls180.v:29.13-29.27" + wire output 25 \spisdcard_cs_n + attribute \src "build/ls180/gateware/ls180.v:30.13-30.27" + wire input 26 \spisdcard_miso + attribute \src "build/ls180/gateware/ls180.v:28.13-28.27" + wire output 24 \spisdcard_mosi + attribute \src "build/ls180/gateware/ls180.v:7.13-7.20" + wire input 3 \sys_clk + attribute \src "build/ls180/gateware/ls180.v:310.6-310.15" + wire \sys_clk_1 + attribute \src "build/ls180/gateware/ls180.v:311.6-311.13" + wire \sys_rst + attribute \src "build/ls180/gateware/ls180.v:9365.12-9365.15" + memory width 32 size 65536 \mem + attribute \src "build/ls180/gateware/ls180.v:9385.11-9385.18" + memory width 10 size 16 \storage + attribute \src "build/ls180/gateware/ls180.v:9402.11-9402.20" + memory width 10 size 16 \storage_1 + attribute \src "build/ls180/gateware/ls180.v:9419.12-9419.21" + memory width 25 size 8 \storage_2 + attribute \src "build/ls180/gateware/ls180.v:9433.12-9433.21" + memory width 25 size 8 \storage_3 + attribute \src "build/ls180/gateware/ls180.v:9447.12-9447.21" + memory width 25 size 8 \storage_4 + attribute \src "build/ls180/gateware/ls180.v:9461.12-9461.21" + memory width 25 size 8 \storage_5 + attribute \src "build/ls180/gateware/ls180.v:9475.11-9475.20" + memory width 10 size 32 \storage_6 + attribute \src "build/ls180/gateware/ls180.v:9489.11-9489.20" + memory width 10 size 32 \storage_7 + attribute \src "build/ls180/gateware/ls180.v:2635.68-2635.110" + cell $add $add$build/ls180/gateware/ls180.v:2635$22 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_libresocsim_converter0_counter + connect \B 1'1 + connect \Y $add$build/ls180/gateware/ls180.v:2635$22_Y + end + attribute \src "build/ls180/gateware/ls180.v:2695.68-2695.110" + cell $add $add$build/ls180/gateware/ls180.v:2695$33 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_libresocsim_converter1_counter + connect \B 1'1 + connect \Y $add$build/ls180/gateware/ls180.v:2695$33_Y + end + attribute \src "build/ls180/gateware/ls180.v:2793.48-2793.125" + cell $add $add$build/ls180/gateware/ls180.v:2793$69 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 5 + connect \A \main_libresocsim_uart_tx_fifo_level0 + connect \B \main_libresocsim_uart_tx_fifo_readable + connect \Y $add$build/ls180/gateware/ls180.v:2793$69_Y + end + attribute \src "build/ls180/gateware/ls180.v:2823.48-2823.125" + cell $add $add$build/ls180/gateware/ls180.v:2823$80 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 5 + connect \A \main_libresocsim_uart_rx_fifo_level0 + connect \B \main_libresocsim_uart_rx_fifo_readable + connect \Y $add$build/ls180/gateware/ls180.v:2823$80_Y + end + attribute \src "build/ls180/gateware/ls180.v:3948.54-3948.83" + cell $add $add$build/ls180/gateware/ls180.v:3948$566 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_converter_counter + connect \B 1'1 + connect \Y $add$build/ls180/gateware/ls180.v:3948$566_Y + end + attribute \src "build/ls180/gateware/ls180.v:4013.42-4013.59" + cell $add $add$build/ls180/gateware/ls180.v:4013$597 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 3 + connect \A \main_count + connect \B 1'1 + connect \Y $add$build/ls180/gateware/ls180.v:4013$597_Y + end + attribute \src "build/ls180/gateware/ls180.v:4113.59-4113.88" + cell $add $add$build/ls180/gateware/ls180.v:4113$625 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 8 + connect \A \libresocsim_init_count + connect \B 1'1 + connect \Y $add$build/ls180/gateware/ls180.v:4113$625_Y + end + attribute \src "build/ls180/gateware/ls180.v:4170.59-4170.88" + cell $add $add$build/ls180/gateware/ls180.v:4170$628 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 8 + connect \A \libresocsim_cmdw_count + connect \B 1'1 + connect \Y $add$build/ls180/gateware/ls180.v:4170$628_Y + end + attribute \src "build/ls180/gateware/ls180.v:4187.59-4187.88" + cell $add $add$build/ls180/gateware/ls180.v:4187$630 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 8 + connect \A \libresocsim_cmdw_count + connect \B 1'1 + connect \Y $add$build/ls180/gateware/ls180.v:4187$630_Y + end + attribute \src "build/ls180/gateware/ls180.v:4280.60-4280.89" + cell $add $add$build/ls180/gateware/ls180.v:4280$647 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 8 + connect \A \libresocsim_cmdr_count + connect \B 1'1 + connect \Y $add$build/ls180/gateware/ls180.v:4280$647_Y + end + attribute \src "build/ls180/gateware/ls180.v:4305.60-4305.89" + cell $add $add$build/ls180/gateware/ls180.v:4305$650 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 8 + connect \A \libresocsim_cmdr_count + connect \B 1'1 + connect \Y $add$build/ls180/gateware/ls180.v:4305$650_Y + end + attribute \src "build/ls180/gateware/ls180.v:4427.54-4427.84" + cell $add $add$build/ls180/gateware/ls180.v:4427$667 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 8 + connect \A \libresocsim_dataw_count + connect \B 1'1 + connect \Y $add$build/ls180/gateware/ls180.v:4427$667_Y + end + attribute \src "build/ls180/gateware/ls180.v:4538.67-4538.117" + cell $add $add$build/ls180/gateware/ls180.v:4538$681 + parameter \A_SIGNED 0 + parameter \A_WIDTH 10 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 10 + connect \A \libresocsim_datar_sink_payload_block_length + connect \B 4'1000 + connect \Y $add$build/ls180/gateware/ls180.v:4538$681_Y + end + attribute \src "build/ls180/gateware/ls180.v:4543.63-4543.93" + cell $add $add$build/ls180/gateware/ls180.v:4543$684 + parameter \A_SIGNED 0 + parameter \A_WIDTH 10 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 10 + connect \A \libresocsim_datar_count + connect \B 1'1 + connect \Y $add$build/ls180/gateware/ls180.v:4543$684_Y + end + attribute \src "build/ls180/gateware/ls180.v:4569.62-4569.92" + cell $add $add$build/ls180/gateware/ls180.v:4569$687 + parameter \A_SIGNED 0 + parameter \A_WIDTH 10 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 10 + connect \A \libresocsim_datar_count + connect \B 1'1 + connect \Y $add$build/ls180/gateware/ls180.v:4569$687_Y + end + attribute \src "build/ls180/gateware/ls180.v:4773.87-4773.131" + cell $add $add$build/ls180/gateware/ls180.v:4773$872 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 3 + connect \A \libresocsim_sdcore_crc16_inserter_cnt + connect \B 1'1 + connect \Y $add$build/ls180/gateware/ls180.v:4773$872_Y + end + attribute \src "build/ls180/gateware/ls180.v:4967.61-4967.96" + cell $add $add$build/ls180/gateware/ls180.v:4967$947 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 3 + connect \A \libresocsim_sdcore_cmd_count + connect \B 1'1 + connect \Y $add$build/ls180/gateware/ls180.v:4967$947_Y + end + attribute \src "build/ls180/gateware/ls180.v:5019.62-5019.98" + cell $add $add$build/ls180/gateware/ls180.v:5019$957 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 32 + connect \A \libresocsim_sdcore_data_count + connect \B 1'1 + connect \Y $add$build/ls180/gateware/ls180.v:5019$957_Y + end + attribute \src "build/ls180/gateware/ls180.v:5045.64-5045.100" + cell $add $add$build/ls180/gateware/ls180.v:5045$965 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 32 + connect \A \libresocsim_sdcore_data_count + connect \B 1'1 + connect \Y $add$build/ls180/gateware/ls180.v:5045$965_Y + end + attribute \src "build/ls180/gateware/ls180.v:5166.58-5166.155" + cell $add $add$build/ls180/gateware/ls180.v:5166$981 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 32 + parameter \Y_WIDTH 32 + connect \A \libresocsim_sdblock2mem_wishbonedmawriter_base + connect \B \libresocsim_sdblock2mem_wishbonedmawriter_offset + connect \Y $add$build/ls180/gateware/ls180.v:5166$981_Y + end + attribute \src "build/ls180/gateware/ls180.v:5169.84-5169.139" + cell $add $add$build/ls180/gateware/ls180.v:5169$983 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 32 + connect \A \libresocsim_sdblock2mem_wishbonedmawriter_offset + connect \B 1'1 + connect \Y $add$build/ls180/gateware/ls180.v:5169$983_Y + end + attribute \src "build/ls180/gateware/ls180.v:5262.57-5262.126" + cell $add $add$build/ls180/gateware/ls180.v:5262$992 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 32 + parameter \Y_WIDTH 32 + connect \A \libresocsim_sdmem2block_dma_base + connect \B \libresocsim_sdmem2block_dma_offset + connect \Y $add$build/ls180/gateware/ls180.v:5262$992_Y + end + attribute \src "build/ls180/gateware/ls180.v:5264.84-5264.125" + cell $add $add$build/ls180/gateware/ls180.v:5264$993 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 32 + connect \A \libresocsim_sdmem2block_dma_offset + connect \B 1'1 + connect \Y $add$build/ls180/gateware/ls180.v:5264$993_Y + end + attribute \src "build/ls180/gateware/ls180.v:5376.49-5376.73" + cell $add $add$build/ls180/gateware/ls180.v:5376$1012 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 3 + connect \A \libresocsim_count + connect \B 1'1 + connect \Y $add$build/ls180/gateware/ls180.v:5376$1012_Y + end + attribute \src "build/ls180/gateware/ls180.v:7080.50-7080.98" + cell $add $add$build/ls180/gateware/ls180.v:7080$2191 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 32 + connect \A \main_libresocsim_soccontroller_bus_errors + connect \B 1'1 + connect \Y $add$build/ls180/gateware/ls180.v:7080$2191_Y + end + attribute \src "build/ls180/gateware/ls180.v:7095.37-7095.72" + cell $add $add$build/ls180/gateware/ls180.v:7095$2200 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 4 + connect \A \main_libresocsim_tx_bitcount + connect \B 1'1 + connect \Y $add$build/ls180/gateware/ls180.v:7095$2200_Y + end + attribute \src "build/ls180/gateware/ls180.v:7111.79-7111.143" + cell $add $add$build/ls180/gateware/ls180.v:7111$2203 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 32 + parameter \Y_WIDTH 33 + connect \A \main_libresocsim_phase_accumulator_tx + connect \B \main_libresocsim_storage + connect \Y $add$build/ls180/gateware/ls180.v:7111$2203_Y + end + attribute \src "build/ls180/gateware/ls180.v:7124.37-7124.72" + cell $add $add$build/ls180/gateware/ls180.v:7124$2207 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 4 + connect \A \main_libresocsim_rx_bitcount + connect \B 1'1 + connect \Y $add$build/ls180/gateware/ls180.v:7124$2207_Y + end + attribute \src "build/ls180/gateware/ls180.v:7143.79-7143.143" + cell $add $add$build/ls180/gateware/ls180.v:7143$2210 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 32 + parameter \Y_WIDTH 33 + connect \A \main_libresocsim_phase_accumulator_rx + connect \B \main_libresocsim_storage + connect \Y $add$build/ls180/gateware/ls180.v:7143$2210_Y + end + attribute \src "build/ls180/gateware/ls180.v:7169.45-7169.89" + cell $add $add$build/ls180/gateware/ls180.v:7169$2218 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 4 + connect \A \main_libresocsim_uart_tx_fifo_produce + connect \B 1'1 + connect \Y $add$build/ls180/gateware/ls180.v:7169$2218_Y + end + attribute \src "build/ls180/gateware/ls180.v:7172.45-7172.89" + cell $add $add$build/ls180/gateware/ls180.v:7172$2219 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 4 + connect \A \main_libresocsim_uart_tx_fifo_consume + connect \B 1'1 + connect \Y $add$build/ls180/gateware/ls180.v:7172$2219_Y + end + attribute \src "build/ls180/gateware/ls180.v:7176.45-7176.88" + cell $add $add$build/ls180/gateware/ls180.v:7176$2224 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 5 + connect \A \main_libresocsim_uart_tx_fifo_level0 + connect \B 1'1 + connect \Y $add$build/ls180/gateware/ls180.v:7176$2224_Y + end + attribute \src "build/ls180/gateware/ls180.v:7191.45-7191.89" + cell $add $add$build/ls180/gateware/ls180.v:7191$2229 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 4 + connect \A \main_libresocsim_uart_rx_fifo_produce + connect \B 1'1 + connect \Y $add$build/ls180/gateware/ls180.v:7191$2229_Y + end + attribute \src "build/ls180/gateware/ls180.v:7194.45-7194.89" + cell $add $add$build/ls180/gateware/ls180.v:7194$2230 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 4 + connect \A \main_libresocsim_uart_rx_fifo_consume + connect \B 1'1 + connect \Y $add$build/ls180/gateware/ls180.v:7194$2230_Y + end + attribute \src "build/ls180/gateware/ls180.v:7198.45-7198.88" + cell $add $add$build/ls180/gateware/ls180.v:7198$2235 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 5 + connect \A \main_libresocsim_uart_rx_fifo_level0 + connect \B 1'1 + connect \Y $add$build/ls180/gateware/ls180.v:7198$2235_Y + end + attribute \src "build/ls180/gateware/ls180.v:7297.37-7297.72" + cell $add $add$build/ls180/gateware/ls180.v:7297$2254 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 4 + connect \A \main_sdram_sequencer_counter + connect \B 1'1 + connect \Y $add$build/ls180/gateware/ls180.v:7297$2254_Y + end + attribute \src "build/ls180/gateware/ls180.v:7314.60-7314.119" + cell $add $add$build/ls180/gateware/ls180.v:7314$2258 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 3 + connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_produce + connect \B 1'1 + connect \Y $add$build/ls180/gateware/ls180.v:7314$2258_Y + end + attribute \src "build/ls180/gateware/ls180.v:7317.60-7317.119" + cell $add $add$build/ls180/gateware/ls180.v:7317$2259 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 3 + connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_consume + connect \B 1'1 + connect \Y $add$build/ls180/gateware/ls180.v:7317$2259_Y + end + attribute \src "build/ls180/gateware/ls180.v:7321.59-7321.116" + cell $add $add$build/ls180/gateware/ls180.v:7321$2264 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 4 + connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_level + connect \B 1'1 + connect \Y $add$build/ls180/gateware/ls180.v:7321$2264_Y + end + attribute \src "build/ls180/gateware/ls180.v:7360.60-7360.119" + cell $add $add$build/ls180/gateware/ls180.v:7360$2274 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 3 + connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_produce + connect \B 1'1 + connect \Y $add$build/ls180/gateware/ls180.v:7360$2274_Y + end + attribute \src "build/ls180/gateware/ls180.v:7363.60-7363.119" + cell $add $add$build/ls180/gateware/ls180.v:7363$2275 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 3 + connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_consume + connect \B 1'1 + connect \Y $add$build/ls180/gateware/ls180.v:7363$2275_Y + end + attribute \src "build/ls180/gateware/ls180.v:7367.59-7367.116" + cell $add $add$build/ls180/gateware/ls180.v:7367$2280 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 4 + connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_level + connect \B 1'1 + connect \Y $add$build/ls180/gateware/ls180.v:7367$2280_Y + end + attribute \src "build/ls180/gateware/ls180.v:7406.60-7406.119" + cell $add $add$build/ls180/gateware/ls180.v:7406$2290 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 3 + connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_produce + connect \B 1'1 + connect \Y $add$build/ls180/gateware/ls180.v:7406$2290_Y + end + attribute \src "build/ls180/gateware/ls180.v:7409.60-7409.119" + cell $add $add$build/ls180/gateware/ls180.v:7409$2291 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 3 + connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_consume + connect \B 1'1 + connect \Y $add$build/ls180/gateware/ls180.v:7409$2291_Y + end + attribute \src "build/ls180/gateware/ls180.v:7413.59-7413.116" + cell $add $add$build/ls180/gateware/ls180.v:7413$2296 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 4 + connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_level + connect \B 1'1 + connect \Y $add$build/ls180/gateware/ls180.v:7413$2296_Y + end + attribute \src "build/ls180/gateware/ls180.v:7452.60-7452.119" + cell $add $add$build/ls180/gateware/ls180.v:7452$2306 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 3 + connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_produce + connect \B 1'1 + connect \Y $add$build/ls180/gateware/ls180.v:7452$2306_Y + end + attribute \src "build/ls180/gateware/ls180.v:7455.60-7455.119" + cell $add $add$build/ls180/gateware/ls180.v:7455$2307 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 3 + connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_consume + connect \B 1'1 + connect \Y $add$build/ls180/gateware/ls180.v:7455$2307_Y + end + attribute \src "build/ls180/gateware/ls180.v:7459.59-7459.116" + cell $add $add$build/ls180/gateware/ls180.v:7459$2312 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 4 + connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_level + connect \B 1'1 + connect \Y $add$build/ls180/gateware/ls180.v:7459$2312_Y + end + attribute \src "build/ls180/gateware/ls180.v:7681.24-7681.48" + cell $add $add$build/ls180/gateware/ls180.v:7681$2361 + parameter \A_SIGNED 0 + parameter \A_WIDTH 16 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 16 + connect \A \main_clk_divider1 + connect \B 1'1 + connect \Y $add$build/ls180/gateware/ls180.v:7681$2361_Y + end + attribute \src "build/ls180/gateware/ls180.v:7717.32-7717.63" + cell $add $add$build/ls180/gateware/ls180.v:7717$2367 + parameter \A_SIGNED 0 + parameter \A_WIDTH 9 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 9 + connect \A \libresocsim_clocker_clks + connect \B 1'1 + connect \Y $add$build/ls180/gateware/ls180.v:7717$2367_Y + end + attribute \src "build/ls180/gateware/ls180.v:7740.46-7740.90" + cell $add $add$build/ls180/gateware/ls180.v:7740$2371 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 3 + connect \A \libresocsim_cmdr_cmdr_converter_demux + connect \B 1'1 + connect \Y $add$build/ls180/gateware/ls180.v:7740$2371_Y + end + attribute \src "build/ls180/gateware/ls180.v:7786.72-7786.116" + cell $add $add$build/ls180/gateware/ls180.v:7786$2377 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 4 + connect \A \libresocsim_cmdr_cmdr_converter_demux + connect \B 1'1 + connect \Y $add$build/ls180/gateware/ls180.v:7786$2377_Y + end + attribute \src "build/ls180/gateware/ls180.v:7821.47-7821.92" + cell $add $add$build/ls180/gateware/ls180.v:7821$2383 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 3 + connect \A \libresocsim_dataw_crcr_converter_demux + connect \B 1'1 + connect \Y $add$build/ls180/gateware/ls180.v:7821$2383_Y + end + attribute \src "build/ls180/gateware/ls180.v:7867.73-7867.118" + cell $add $add$build/ls180/gateware/ls180.v:7867$2389 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 4 + connect \A \libresocsim_dataw_crcr_converter_demux + connect \B 1'1 + connect \Y $add$build/ls180/gateware/ls180.v:7867$2389_Y + end + attribute \src "build/ls180/gateware/ls180.v:7900.48-7900.94" + cell $add $add$build/ls180/gateware/ls180.v:7900$2395 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \libresocsim_datar_datar_converter_demux + connect \B 1'1 + connect \Y $add$build/ls180/gateware/ls180.v:7900$2395_Y + end + attribute \src "build/ls180/gateware/ls180.v:7928.74-7928.120" + cell $add $add$build/ls180/gateware/ls180.v:7928$2401 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 2 + connect \A \libresocsim_datar_datar_converter_demux + connect \B 1'1 + connect \Y $add$build/ls180/gateware/ls180.v:7928$2401_Y + end + attribute \src "build/ls180/gateware/ls180.v:8040.46-8040.89" + cell $add $add$build/ls180/gateware/ls180.v:8040$2414 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 4 + connect \A \libresocsim_sdcore_crc16_checker_cnt + connect \B 1'1 + connect \Y $add$build/ls180/gateware/ls180.v:8040$2414_Y + end + attribute \src "build/ls180/gateware/ls180.v:8101.44-8101.87" + cell $add $add$build/ls180/gateware/ls180.v:8101$2418 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 5 + connect \A \libresocsim_sdblock2mem_fifo_produce + connect \B 1'1 + connect \Y $add$build/ls180/gateware/ls180.v:8101$2418_Y + end + attribute \src "build/ls180/gateware/ls180.v:8104.44-8104.87" + cell $add $add$build/ls180/gateware/ls180.v:8104$2419 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 5 + connect \A \libresocsim_sdblock2mem_fifo_consume + connect \B 1'1 + connect \Y $add$build/ls180/gateware/ls180.v:8104$2419_Y + end + attribute \src "build/ls180/gateware/ls180.v:8108.43-8108.84" + cell $add $add$build/ls180/gateware/ls180.v:8108$2424 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 6 + connect \A \libresocsim_sdblock2mem_fifo_level + connect \B 1'1 + connect \Y $add$build/ls180/gateware/ls180.v:8108$2424_Y + end + attribute \src "build/ls180/gateware/ls180.v:8123.48-8123.94" + cell $add $add$build/ls180/gateware/ls180.v:8123$2428 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 2 + connect \A \libresocsim_sdblock2mem_converter_demux + connect \B 1'1 + connect \Y $add$build/ls180/gateware/ls180.v:8123$2428_Y + end + attribute \src "build/ls180/gateware/ls180.v:8157.74-8157.120" + cell $add $add$build/ls180/gateware/ls180.v:8157$2434 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 3 + connect \A \libresocsim_sdblock2mem_converter_demux + connect \B 1'1 + connect \Y $add$build/ls180/gateware/ls180.v:8157$2434_Y + end + attribute \src "build/ls180/gateware/ls180.v:8183.46-8183.90" + cell $add $add$build/ls180/gateware/ls180.v:8183$2436 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 2 + connect \A \libresocsim_sdmem2block_converter_mux + connect \B 1'1 + connect \Y $add$build/ls180/gateware/ls180.v:8183$2436_Y + end + attribute \src "build/ls180/gateware/ls180.v:8187.44-8187.87" + cell $add $add$build/ls180/gateware/ls180.v:8187$2440 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 5 + connect \A \libresocsim_sdmem2block_fifo_produce + connect \B 1'1 + connect \Y $add$build/ls180/gateware/ls180.v:8187$2440_Y + end + attribute \src "build/ls180/gateware/ls180.v:8190.44-8190.87" + cell $add $add$build/ls180/gateware/ls180.v:8190$2441 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 5 + connect \A \libresocsim_sdmem2block_fifo_consume + connect \B 1'1 + connect \Y $add$build/ls180/gateware/ls180.v:8190$2441_Y + end + attribute \src "build/ls180/gateware/ls180.v:8194.43-8194.84" + cell $add $add$build/ls180/gateware/ls180.v:8194$2446 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 6 + connect \A \libresocsim_sdmem2block_fifo_level + connect \B 1'1 + connect \Y $add$build/ls180/gateware/ls180.v:8194$2446_Y + end + attribute \src "build/ls180/gateware/ls180.v:8201.31-8201.62" + cell $add $add$build/ls180/gateware/ls180.v:8201$2448 + parameter \A_SIGNED 0 + parameter \A_WIDTH 16 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 16 + connect \A \libresocsim_clk_divider1 + connect \B 1'1 + connect \Y $add$build/ls180/gateware/ls180.v:8201$2448_Y + end + attribute \src "build/ls180/gateware/ls180.v:2629.9-2629.80" + cell $and $and$build/ls180/gateware/ls180.v:2629$17 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_libresocsim_libresoc_ibus_stb + connect \B \main_libresocsim_libresoc_ibus_cyc + connect \Y $and$build/ls180/gateware/ls180.v:2629$17_Y + end + attribute \src "build/ls180/gateware/ls180.v:2647.9-2647.80" + cell $and $and$build/ls180/gateware/ls180.v:2647$24 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_libresocsim_libresoc_ibus_stb + connect \B \main_libresocsim_libresoc_ibus_cyc + connect \Y $and$build/ls180/gateware/ls180.v:2647$24_Y + end + attribute \src "build/ls180/gateware/ls180.v:2689.9-2689.80" + cell $and $and$build/ls180/gateware/ls180.v:2689$28 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_libresocsim_libresoc_dbus_stb + connect \B \main_libresocsim_libresoc_dbus_cyc + connect \Y $and$build/ls180/gateware/ls180.v:2689$28_Y + end + attribute \src "build/ls180/gateware/ls180.v:2707.9-2707.80" + cell $and $and$build/ls180/gateware/ls180.v:2707$35 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_libresocsim_libresoc_dbus_stb + connect \B \main_libresocsim_libresoc_dbus_cyc + connect \Y $and$build/ls180/gateware/ls180.v:2707$35_Y + end + attribute \src "build/ls180/gateware/ls180.v:2717.31-2717.90" + cell $and $and$build/ls180/gateware/ls180.v:2717$37 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_libresocsim_ram_bus_cyc + connect \B \main_libresocsim_ram_bus_stb + connect \Y $and$build/ls180/gateware/ls180.v:2717$37_Y + end + attribute \src "build/ls180/gateware/ls180.v:2717.30-2717.121" + cell $and $and$build/ls180/gateware/ls180.v:2717$38 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$build/ls180/gateware/ls180.v:2717$37_Y + connect \B \main_libresocsim_ram_bus_we + connect \Y $and$build/ls180/gateware/ls180.v:2717$38_Y + end + attribute \src "build/ls180/gateware/ls180.v:2717.29-2717.156" + cell $and $and$build/ls180/gateware/ls180.v:2717$39 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$build/ls180/gateware/ls180.v:2717$38_Y + connect \B \main_libresocsim_ram_bus_sel [0] + connect \Y $and$build/ls180/gateware/ls180.v:2717$39_Y + end + attribute \src "build/ls180/gateware/ls180.v:2718.31-2718.90" + cell $and $and$build/ls180/gateware/ls180.v:2718$40 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_libresocsim_ram_bus_cyc + connect \B \main_libresocsim_ram_bus_stb + connect \Y $and$build/ls180/gateware/ls180.v:2718$40_Y + end + attribute \src "build/ls180/gateware/ls180.v:2718.30-2718.121" + cell $and $and$build/ls180/gateware/ls180.v:2718$41 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$build/ls180/gateware/ls180.v:2718$40_Y + connect \B \main_libresocsim_ram_bus_we + connect \Y $and$build/ls180/gateware/ls180.v:2718$41_Y + end + attribute \src "build/ls180/gateware/ls180.v:2718.29-2718.156" + cell $and $and$build/ls180/gateware/ls180.v:2718$42 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$build/ls180/gateware/ls180.v:2718$41_Y + connect \B \main_libresocsim_ram_bus_sel [1] + connect \Y $and$build/ls180/gateware/ls180.v:2718$42_Y + end + attribute \src "build/ls180/gateware/ls180.v:2719.31-2719.90" + cell $and $and$build/ls180/gateware/ls180.v:2719$43 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_libresocsim_ram_bus_cyc + connect \B \main_libresocsim_ram_bus_stb + connect \Y $and$build/ls180/gateware/ls180.v:2719$43_Y + end + attribute \src "build/ls180/gateware/ls180.v:2719.30-2719.121" + cell $and $and$build/ls180/gateware/ls180.v:2719$44 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$build/ls180/gateware/ls180.v:2719$43_Y + connect \B \main_libresocsim_ram_bus_we + connect \Y $and$build/ls180/gateware/ls180.v:2719$44_Y + end + attribute \src "build/ls180/gateware/ls180.v:2719.29-2719.156" + cell $and $and$build/ls180/gateware/ls180.v:2719$45 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$build/ls180/gateware/ls180.v:2719$44_Y + connect \B \main_libresocsim_ram_bus_sel [2] + connect \Y $and$build/ls180/gateware/ls180.v:2719$45_Y + end + attribute \src "build/ls180/gateware/ls180.v:2720.31-2720.90" + cell $and $and$build/ls180/gateware/ls180.v:2720$46 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_libresocsim_ram_bus_cyc + connect \B \main_libresocsim_ram_bus_stb + connect \Y $and$build/ls180/gateware/ls180.v:2720$46_Y + end + attribute \src "build/ls180/gateware/ls180.v:2720.30-2720.121" + cell $and $and$build/ls180/gateware/ls180.v:2720$47 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$build/ls180/gateware/ls180.v:2720$46_Y + connect \B \main_libresocsim_ram_bus_we + connect \Y $and$build/ls180/gateware/ls180.v:2720$47_Y + end + attribute \src "build/ls180/gateware/ls180.v:2720.29-2720.156" + cell $and $and$build/ls180/gateware/ls180.v:2720$48 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$build/ls180/gateware/ls180.v:2720$47_Y + connect \B \main_libresocsim_ram_bus_sel [3] + connect \Y $and$build/ls180/gateware/ls180.v:2720$48_Y + end + attribute \src "build/ls180/gateware/ls180.v:2753.88-2753.124" + cell $and $and$build/ls180/gateware/ls180.v:2753$54 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A 1'0 + connect \B \main_libresocsim_uart_rxtx_we + connect \Y $and$build/ls180/gateware/ls180.v:2753$54_Y + end + attribute \src "build/ls180/gateware/ls180.v:2757.7-2757.102" + cell $and $and$build/ls180/gateware/ls180.v:2757$58 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_libresocsim_uart_eventmanager_pending_re + connect \B \main_libresocsim_uart_eventmanager_pending_r [0] + connect \Y $and$build/ls180/gateware/ls180.v:2757$58_Y + end + attribute \src "build/ls180/gateware/ls180.v:2768.7-2768.102" + cell $and $and$build/ls180/gateware/ls180.v:2768$61 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_libresocsim_uart_eventmanager_pending_re + connect \B \main_libresocsim_uart_eventmanager_pending_r [1] + connect \Y $and$build/ls180/gateware/ls180.v:2768$61_Y + end + attribute \src "build/ls180/gateware/ls180.v:2777.38-2777.133" + cell $and $and$build/ls180/gateware/ls180.v:2777$63 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_libresocsim_uart_eventmanager_pending_w [0] + connect \B \main_libresocsim_uart_eventmanager_storage [0] + connect \Y $and$build/ls180/gateware/ls180.v:2777$63_Y + end + attribute \src "build/ls180/gateware/ls180.v:2777.138-2777.233" + cell $and $and$build/ls180/gateware/ls180.v:2777$64 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_libresocsim_uart_eventmanager_pending_w [1] + connect \B \main_libresocsim_uart_eventmanager_storage [1] + connect \Y $and$build/ls180/gateware/ls180.v:2777$64_Y + end + attribute \src "build/ls180/gateware/ls180.v:2792.53-2792.181" + cell $and $and$build/ls180/gateware/ls180.v:2792$68 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_libresocsim_uart_tx_fifo_syncfifo_readable + connect \B $or$build/ls180/gateware/ls180.v:2792$67_Y + connect \Y $and$build/ls180/gateware/ls180.v:2792$68_Y + end + attribute \src "build/ls180/gateware/ls180.v:2803.51-2803.184" + cell $and $and$build/ls180/gateware/ls180.v:2803$73 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_libresocsim_uart_tx_fifo_syncfifo_we + connect \B $or$build/ls180/gateware/ls180.v:2803$72_Y + connect \Y $and$build/ls180/gateware/ls180.v:2803$73_Y + end + attribute \src "build/ls180/gateware/ls180.v:2804.49-2804.140" + cell $and $and$build/ls180/gateware/ls180.v:2804$74 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_libresocsim_uart_tx_fifo_syncfifo_readable + connect \B \main_libresocsim_uart_tx_fifo_syncfifo_re + connect \Y $and$build/ls180/gateware/ls180.v:2804$74_Y + end + attribute \src "build/ls180/gateware/ls180.v:2822.53-2822.181" + cell $and $and$build/ls180/gateware/ls180.v:2822$79 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_libresocsim_uart_rx_fifo_syncfifo_readable + connect \B $or$build/ls180/gateware/ls180.v:2822$78_Y + connect \Y $and$build/ls180/gateware/ls180.v:2822$79_Y + end + attribute \src "build/ls180/gateware/ls180.v:2833.51-2833.184" + cell $and $and$build/ls180/gateware/ls180.v:2833$84 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_libresocsim_uart_rx_fifo_syncfifo_we + connect \B $or$build/ls180/gateware/ls180.v:2833$83_Y + connect \Y $and$build/ls180/gateware/ls180.v:2833$84_Y + end + attribute \src "build/ls180/gateware/ls180.v:2834.49-2834.140" + cell $and $and$build/ls180/gateware/ls180.v:2834$85 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_libresocsim_uart_rx_fifo_syncfifo_readable + connect \B \main_libresocsim_uart_rx_fifo_syncfifo_re + connect \Y $and$build/ls180/gateware/ls180.v:2834$85_Y + end + attribute \src "build/ls180/gateware/ls180.v:2844.7-2844.101" + cell $and $and$build/ls180/gateware/ls180.v:2844$90 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_libresocsim_timer_eventmanager_pending_re + connect \B \main_libresocsim_timer_eventmanager_pending_r + connect \Y $and$build/ls180/gateware/ls180.v:2844$90_Y + end + attribute \src "build/ls180/gateware/ls180.v:2849.38-2849.129" + cell $and $and$build/ls180/gateware/ls180.v:2849$91 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_libresocsim_timer_eventmanager_pending_w + connect \B \main_libresocsim_timer_eventmanager_storage + connect \Y $and$build/ls180/gateware/ls180.v:2849$91_Y + end + attribute \src "build/ls180/gateware/ls180.v:2968.40-2968.99" + cell $and $and$build/ls180/gateware/ls180.v:2968$99 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_command_issue_re + connect \B \main_sdram_command_storage [4] + connect \Y $and$build/ls180/gateware/ls180.v:2968$99_Y + end + attribute \src "build/ls180/gateware/ls180.v:2969.40-2969.99" + cell $and $and$build/ls180/gateware/ls180.v:2969$100 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_command_issue_re + connect \B \main_sdram_command_storage [5] + connect \Y $and$build/ls180/gateware/ls180.v:2969$100_Y + end + attribute \src "build/ls180/gateware/ls180.v:3007.38-3007.103" + cell $and $and$build/ls180/gateware/ls180.v:3007$106 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_sequencer_done1 + connect \B $eq$build/ls180/gateware/ls180.v:3007$105_Y + connect \Y $and$build/ls180/gateware/ls180.v:3007$106_Y + end + attribute \src "build/ls180/gateware/ls180.v:3061.50-3061.119" + cell $and $and$build/ls180/gateware/ls180.v:3061$114 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine0_cmd_valid + connect \B \main_sdram_bankmachine0_cmd_ready + connect \Y $and$build/ls180/gateware/ls180.v:3061$114_Y + end + attribute \src "build/ls180/gateware/ls180.v:3061.49-3061.167" + cell $and $and$build/ls180/gateware/ls180.v:3061$115 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$build/ls180/gateware/ls180.v:3061$114_Y + connect \B \main_sdram_bankmachine0_cmd_payload_is_write + connect \Y $and$build/ls180/gateware/ls180.v:3061$115_Y + end + attribute \src "build/ls180/gateware/ls180.v:3062.49-3062.118" + cell $and $and$build/ls180/gateware/ls180.v:3062$116 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine0_cmd_valid + connect \B \main_sdram_bankmachine0_cmd_ready + connect \Y $and$build/ls180/gateware/ls180.v:3062$116_Y + end + attribute \src "build/ls180/gateware/ls180.v:3062.48-3062.154" + cell $and $and$build/ls180/gateware/ls180.v:3062$117 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$build/ls180/gateware/ls180.v:3062$116_Y + connect \B \main_sdram_bankmachine0_row_open + connect \Y $and$build/ls180/gateware/ls180.v:3062$117_Y + end + attribute \src "build/ls180/gateware/ls180.v:3063.50-3063.119" + cell $and $and$build/ls180/gateware/ls180.v:3063$118 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine0_cmd_valid + connect \B \main_sdram_bankmachine0_cmd_ready + connect \Y $and$build/ls180/gateware/ls180.v:3063$118_Y + end + attribute \src "build/ls180/gateware/ls180.v:3063.49-3063.155" + cell $and $and$build/ls180/gateware/ls180.v:3063$119 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$build/ls180/gateware/ls180.v:3063$118_Y + connect \B \main_sdram_bankmachine0_row_open + connect \Y $and$build/ls180/gateware/ls180.v:3063$119_Y + end + attribute \src "build/ls180/gateware/ls180.v:3066.7-3066.114" + cell $and $and$build/ls180/gateware/ls180.v:3066$121 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_source_valid + connect \B \main_sdram_bankmachine0_cmd_buffer_source_valid + connect \Y $and$build/ls180/gateware/ls180.v:3066$121_Y + end + attribute \src "build/ls180/gateware/ls180.v:3095.66-3095.246" + cell $and $and$build/ls180/gateware/ls180.v:3095$127 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_we + connect \B $or$build/ls180/gateware/ls180.v:3095$126_Y + connect \Y $and$build/ls180/gateware/ls180.v:3095$127_Y + end + attribute \src "build/ls180/gateware/ls180.v:3096.64-3096.187" + cell $and $and$build/ls180/gateware/ls180.v:3096$128 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable + connect \B \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_re + connect \Y $and$build/ls180/gateware/ls180.v:3096$128_Y + end + attribute \src "build/ls180/gateware/ls180.v:3120.9-3120.86" + cell $and $and$build/ls180/gateware/ls180.v:3120$134 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine0_twtpcon_ready + connect \B \main_sdram_bankmachine0_trascon_ready + connect \Y $and$build/ls180/gateware/ls180.v:3120$134_Y + end + attribute \src "build/ls180/gateware/ls180.v:3132.9-3132.86" + cell $and $and$build/ls180/gateware/ls180.v:3132$135 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine0_twtpcon_ready + connect \B \main_sdram_bankmachine0_trascon_ready + connect \Y $and$build/ls180/gateware/ls180.v:3132$135_Y + end + attribute \src "build/ls180/gateware/ls180.v:3182.13-3182.87" + cell $and $and$build/ls180/gateware/ls180.v:3182$137 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine0_cmd_ready + connect \B \main_sdram_bankmachine0_auto_precharge + connect \Y $and$build/ls180/gateware/ls180.v:3182$137_Y + end + attribute \src "build/ls180/gateware/ls180.v:3218.50-3218.119" + cell $and $and$build/ls180/gateware/ls180.v:3218$144 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine1_cmd_valid + connect \B \main_sdram_bankmachine1_cmd_ready + connect \Y $and$build/ls180/gateware/ls180.v:3218$144_Y + end + attribute \src "build/ls180/gateware/ls180.v:3218.49-3218.167" + cell $and $and$build/ls180/gateware/ls180.v:3218$145 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$build/ls180/gateware/ls180.v:3218$144_Y + connect \B \main_sdram_bankmachine1_cmd_payload_is_write + connect \Y $and$build/ls180/gateware/ls180.v:3218$145_Y + end + attribute \src "build/ls180/gateware/ls180.v:3219.49-3219.118" + cell $and $and$build/ls180/gateware/ls180.v:3219$146 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine1_cmd_valid + connect \B \main_sdram_bankmachine1_cmd_ready + connect \Y $and$build/ls180/gateware/ls180.v:3219$146_Y + end + attribute \src "build/ls180/gateware/ls180.v:3219.48-3219.154" + cell $and $and$build/ls180/gateware/ls180.v:3219$147 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$build/ls180/gateware/ls180.v:3219$146_Y + connect \B \main_sdram_bankmachine1_row_open + connect \Y $and$build/ls180/gateware/ls180.v:3219$147_Y + end + attribute \src "build/ls180/gateware/ls180.v:3220.50-3220.119" + cell $and $and$build/ls180/gateware/ls180.v:3220$148 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine1_cmd_valid + connect \B \main_sdram_bankmachine1_cmd_ready + connect \Y $and$build/ls180/gateware/ls180.v:3220$148_Y + end + attribute \src "build/ls180/gateware/ls180.v:3220.49-3220.155" + cell $and $and$build/ls180/gateware/ls180.v:3220$149 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$build/ls180/gateware/ls180.v:3220$148_Y + connect \B \main_sdram_bankmachine1_row_open + connect \Y $and$build/ls180/gateware/ls180.v:3220$149_Y + end + attribute \src "build/ls180/gateware/ls180.v:3223.7-3223.114" + cell $and $and$build/ls180/gateware/ls180.v:3223$151 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_source_valid + connect \B \main_sdram_bankmachine1_cmd_buffer_source_valid + connect \Y $and$build/ls180/gateware/ls180.v:3223$151_Y + end + attribute \src "build/ls180/gateware/ls180.v:3252.66-3252.246" + cell $and $and$build/ls180/gateware/ls180.v:3252$157 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_we + connect \B $or$build/ls180/gateware/ls180.v:3252$156_Y + connect \Y $and$build/ls180/gateware/ls180.v:3252$157_Y + end + attribute \src "build/ls180/gateware/ls180.v:3253.64-3253.187" + cell $and $and$build/ls180/gateware/ls180.v:3253$158 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable + connect \B \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_re + connect \Y $and$build/ls180/gateware/ls180.v:3253$158_Y + end + attribute \src "build/ls180/gateware/ls180.v:3277.9-3277.86" + cell $and $and$build/ls180/gateware/ls180.v:3277$164 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine1_twtpcon_ready + connect \B \main_sdram_bankmachine1_trascon_ready + connect \Y $and$build/ls180/gateware/ls180.v:3277$164_Y + end + attribute \src "build/ls180/gateware/ls180.v:3289.9-3289.86" + cell $and $and$build/ls180/gateware/ls180.v:3289$165 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine1_twtpcon_ready + connect \B \main_sdram_bankmachine1_trascon_ready + connect \Y $and$build/ls180/gateware/ls180.v:3289$165_Y + end + attribute \src "build/ls180/gateware/ls180.v:3339.13-3339.87" + cell $and $and$build/ls180/gateware/ls180.v:3339$167 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine1_cmd_ready + connect \B \main_sdram_bankmachine1_auto_precharge + connect \Y $and$build/ls180/gateware/ls180.v:3339$167_Y + end + attribute \src "build/ls180/gateware/ls180.v:3375.50-3375.119" + cell $and $and$build/ls180/gateware/ls180.v:3375$174 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine2_cmd_valid + connect \B \main_sdram_bankmachine2_cmd_ready + connect \Y $and$build/ls180/gateware/ls180.v:3375$174_Y + end + attribute \src "build/ls180/gateware/ls180.v:3375.49-3375.167" + cell $and $and$build/ls180/gateware/ls180.v:3375$175 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$build/ls180/gateware/ls180.v:3375$174_Y + connect \B \main_sdram_bankmachine2_cmd_payload_is_write + connect \Y $and$build/ls180/gateware/ls180.v:3375$175_Y + end + attribute \src "build/ls180/gateware/ls180.v:3376.49-3376.118" + cell $and $and$build/ls180/gateware/ls180.v:3376$176 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine2_cmd_valid + connect \B \main_sdram_bankmachine2_cmd_ready + connect \Y $and$build/ls180/gateware/ls180.v:3376$176_Y + end + attribute \src "build/ls180/gateware/ls180.v:3376.48-3376.154" + cell $and $and$build/ls180/gateware/ls180.v:3376$177 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$build/ls180/gateware/ls180.v:3376$176_Y + connect \B \main_sdram_bankmachine2_row_open + connect \Y $and$build/ls180/gateware/ls180.v:3376$177_Y + end + attribute \src "build/ls180/gateware/ls180.v:3377.50-3377.119" + cell $and $and$build/ls180/gateware/ls180.v:3377$178 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine2_cmd_valid + connect \B \main_sdram_bankmachine2_cmd_ready + connect \Y $and$build/ls180/gateware/ls180.v:3377$178_Y + end + attribute \src "build/ls180/gateware/ls180.v:3377.49-3377.155" + cell $and $and$build/ls180/gateware/ls180.v:3377$179 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$build/ls180/gateware/ls180.v:3377$178_Y + connect \B \main_sdram_bankmachine2_row_open + connect \Y $and$build/ls180/gateware/ls180.v:3377$179_Y + end + attribute \src "build/ls180/gateware/ls180.v:3380.7-3380.114" + cell $and $and$build/ls180/gateware/ls180.v:3380$181 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_source_valid + connect \B \main_sdram_bankmachine2_cmd_buffer_source_valid + connect \Y $and$build/ls180/gateware/ls180.v:3380$181_Y + end + attribute \src "build/ls180/gateware/ls180.v:3409.66-3409.246" + cell $and $and$build/ls180/gateware/ls180.v:3409$187 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_we + connect \B $or$build/ls180/gateware/ls180.v:3409$186_Y + connect \Y $and$build/ls180/gateware/ls180.v:3409$187_Y + end + attribute \src "build/ls180/gateware/ls180.v:3410.64-3410.187" + cell $and $and$build/ls180/gateware/ls180.v:3410$188 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable + connect \B \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_re + connect \Y $and$build/ls180/gateware/ls180.v:3410$188_Y + end + attribute \src "build/ls180/gateware/ls180.v:3434.9-3434.86" + cell $and $and$build/ls180/gateware/ls180.v:3434$194 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine2_twtpcon_ready + connect \B \main_sdram_bankmachine2_trascon_ready + connect \Y $and$build/ls180/gateware/ls180.v:3434$194_Y + end + attribute \src "build/ls180/gateware/ls180.v:3446.9-3446.86" + cell $and $and$build/ls180/gateware/ls180.v:3446$195 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine2_twtpcon_ready + connect \B \main_sdram_bankmachine2_trascon_ready + connect \Y $and$build/ls180/gateware/ls180.v:3446$195_Y + end + attribute \src "build/ls180/gateware/ls180.v:3496.13-3496.87" + cell $and $and$build/ls180/gateware/ls180.v:3496$197 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine2_cmd_ready + connect \B \main_sdram_bankmachine2_auto_precharge + connect \Y $and$build/ls180/gateware/ls180.v:3496$197_Y + end + attribute \src "build/ls180/gateware/ls180.v:3532.50-3532.119" + cell $and $and$build/ls180/gateware/ls180.v:3532$204 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine3_cmd_valid + connect \B \main_sdram_bankmachine3_cmd_ready + connect \Y $and$build/ls180/gateware/ls180.v:3532$204_Y + end + attribute \src "build/ls180/gateware/ls180.v:3532.49-3532.167" + cell $and $and$build/ls180/gateware/ls180.v:3532$205 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$build/ls180/gateware/ls180.v:3532$204_Y + connect \B \main_sdram_bankmachine3_cmd_payload_is_write + connect \Y $and$build/ls180/gateware/ls180.v:3532$205_Y + end + attribute \src "build/ls180/gateware/ls180.v:3533.49-3533.118" + cell $and $and$build/ls180/gateware/ls180.v:3533$206 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine3_cmd_valid + connect \B \main_sdram_bankmachine3_cmd_ready + connect \Y $and$build/ls180/gateware/ls180.v:3533$206_Y + end + attribute \src "build/ls180/gateware/ls180.v:3533.48-3533.154" + cell $and $and$build/ls180/gateware/ls180.v:3533$207 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$build/ls180/gateware/ls180.v:3533$206_Y + connect \B \main_sdram_bankmachine3_row_open + connect \Y $and$build/ls180/gateware/ls180.v:3533$207_Y + end + attribute \src "build/ls180/gateware/ls180.v:3534.50-3534.119" + cell $and $and$build/ls180/gateware/ls180.v:3534$208 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine3_cmd_valid + connect \B \main_sdram_bankmachine3_cmd_ready + connect \Y $and$build/ls180/gateware/ls180.v:3534$208_Y + end + attribute \src "build/ls180/gateware/ls180.v:3534.49-3534.155" + cell $and $and$build/ls180/gateware/ls180.v:3534$209 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$build/ls180/gateware/ls180.v:3534$208_Y + connect \B \main_sdram_bankmachine3_row_open + connect \Y $and$build/ls180/gateware/ls180.v:3534$209_Y + end + attribute \src "build/ls180/gateware/ls180.v:3537.7-3537.114" + cell $and $and$build/ls180/gateware/ls180.v:3537$211 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_source_valid + connect \B \main_sdram_bankmachine3_cmd_buffer_source_valid + connect \Y $and$build/ls180/gateware/ls180.v:3537$211_Y + end + attribute \src "build/ls180/gateware/ls180.v:3566.66-3566.246" + cell $and $and$build/ls180/gateware/ls180.v:3566$217 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_we + connect \B $or$build/ls180/gateware/ls180.v:3566$216_Y + connect \Y $and$build/ls180/gateware/ls180.v:3566$217_Y + end + attribute \src "build/ls180/gateware/ls180.v:3567.64-3567.187" + cell $and $and$build/ls180/gateware/ls180.v:3567$218 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable + connect \B \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_re + connect \Y $and$build/ls180/gateware/ls180.v:3567$218_Y + end + attribute \src "build/ls180/gateware/ls180.v:3591.9-3591.86" + cell $and $and$build/ls180/gateware/ls180.v:3591$224 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine3_twtpcon_ready + connect \B \main_sdram_bankmachine3_trascon_ready + connect \Y $and$build/ls180/gateware/ls180.v:3591$224_Y + end + attribute \src "build/ls180/gateware/ls180.v:3603.9-3603.86" + cell $and $and$build/ls180/gateware/ls180.v:3603$225 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine3_twtpcon_ready + connect \B \main_sdram_bankmachine3_trascon_ready + connect \Y $and$build/ls180/gateware/ls180.v:3603$225_Y + end + attribute \src "build/ls180/gateware/ls180.v:3653.13-3653.87" + cell $and $and$build/ls180/gateware/ls180.v:3653$227 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine3_cmd_ready + connect \B \main_sdram_bankmachine3_auto_precharge + connect \Y $and$build/ls180/gateware/ls180.v:3653$227_Y + end + attribute \src "build/ls180/gateware/ls180.v:3668.37-3668.102" + cell $and $and$build/ls180/gateware/ls180.v:3668$228 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_req_cmd_valid + connect \B \main_sdram_choose_req_cmd_ready + connect \Y $and$build/ls180/gateware/ls180.v:3668$228_Y + end + attribute \src "build/ls180/gateware/ls180.v:3668.108-3668.188" + cell $and $and$build/ls180/gateware/ls180.v:3668$230 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_req_cmd_payload_ras + connect \B $not$build/ls180/gateware/ls180.v:3668$229_Y + connect \Y $and$build/ls180/gateware/ls180.v:3668$230_Y + end + attribute \src "build/ls180/gateware/ls180.v:3668.107-3668.231" + cell $and $and$build/ls180/gateware/ls180.v:3668$232 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$build/ls180/gateware/ls180.v:3668$230_Y + connect \B $not$build/ls180/gateware/ls180.v:3668$231_Y + connect \Y $and$build/ls180/gateware/ls180.v:3668$232_Y + end + attribute \src "build/ls180/gateware/ls180.v:3668.36-3668.232" + cell $and $and$build/ls180/gateware/ls180.v:3668$233 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$build/ls180/gateware/ls180.v:3668$228_Y + connect \B $and$build/ls180/gateware/ls180.v:3668$232_Y + connect \Y $and$build/ls180/gateware/ls180.v:3668$233_Y + end + attribute \src "build/ls180/gateware/ls180.v:3669.37-3669.102" + cell $and $and$build/ls180/gateware/ls180.v:3669$234 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_req_cmd_valid + connect \B \main_sdram_choose_req_cmd_ready + connect \Y $and$build/ls180/gateware/ls180.v:3669$234_Y + end + attribute \src "build/ls180/gateware/ls180.v:3669.108-3669.188" + cell $and $and$build/ls180/gateware/ls180.v:3669$236 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_req_cmd_payload_ras + connect \B $not$build/ls180/gateware/ls180.v:3669$235_Y + connect \Y $and$build/ls180/gateware/ls180.v:3669$236_Y + end + attribute \src "build/ls180/gateware/ls180.v:3669.107-3669.231" + cell $and $and$build/ls180/gateware/ls180.v:3669$238 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$build/ls180/gateware/ls180.v:3669$236_Y + connect \B $not$build/ls180/gateware/ls180.v:3669$237_Y + connect \Y $and$build/ls180/gateware/ls180.v:3669$238_Y + end + attribute \src "build/ls180/gateware/ls180.v:3669.36-3669.232" + cell $and $and$build/ls180/gateware/ls180.v:3669$239 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$build/ls180/gateware/ls180.v:3669$234_Y + connect \B $and$build/ls180/gateware/ls180.v:3669$238_Y + connect \Y $and$build/ls180/gateware/ls180.v:3669$239_Y + end + attribute \src "build/ls180/gateware/ls180.v:3670.34-3670.85" + cell $and $and$build/ls180/gateware/ls180.v:3670$240 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_trrdcon_ready + connect \B \main_sdram_tfawcon_ready + connect \Y $and$build/ls180/gateware/ls180.v:3670$240_Y + end + attribute \src "build/ls180/gateware/ls180.v:3671.37-3671.102" + cell $and $and$build/ls180/gateware/ls180.v:3671$241 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_req_cmd_valid + connect \B \main_sdram_choose_req_cmd_ready + connect \Y $and$build/ls180/gateware/ls180.v:3671$241_Y + end + attribute \src "build/ls180/gateware/ls180.v:3671.36-3671.194" + cell $and $and$build/ls180/gateware/ls180.v:3671$243 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$build/ls180/gateware/ls180.v:3671$241_Y + connect \B $or$build/ls180/gateware/ls180.v:3671$242_Y + connect \Y $and$build/ls180/gateware/ls180.v:3671$243_Y + end + attribute \src "build/ls180/gateware/ls180.v:3673.37-3673.102" + cell $and $and$build/ls180/gateware/ls180.v:3673$244 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_req_cmd_valid + connect \B \main_sdram_choose_req_cmd_ready + connect \Y $and$build/ls180/gateware/ls180.v:3673$244_Y + end + attribute \src "build/ls180/gateware/ls180.v:3673.36-3673.148" + cell $and $and$build/ls180/gateware/ls180.v:3673$245 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$build/ls180/gateware/ls180.v:3673$244_Y + connect \B \main_sdram_choose_req_cmd_payload_is_write + connect \Y $and$build/ls180/gateware/ls180.v:3673$245_Y + end + attribute \src "build/ls180/gateware/ls180.v:3674.40-3674.119" + cell $and $and$build/ls180/gateware/ls180.v:3674$246 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine0_cmd_valid + connect \B \main_sdram_bankmachine0_cmd_payload_is_read + connect \Y $and$build/ls180/gateware/ls180.v:3674$246_Y + end + attribute \src "build/ls180/gateware/ls180.v:3674.124-3674.203" + cell $and $and$build/ls180/gateware/ls180.v:3674$247 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine1_cmd_valid + connect \B \main_sdram_bankmachine1_cmd_payload_is_read + connect \Y $and$build/ls180/gateware/ls180.v:3674$247_Y + end + attribute \src "build/ls180/gateware/ls180.v:3674.209-3674.288" + cell $and $and$build/ls180/gateware/ls180.v:3674$249 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine2_cmd_valid + connect \B \main_sdram_bankmachine2_cmd_payload_is_read + connect \Y $and$build/ls180/gateware/ls180.v:3674$249_Y + end + attribute \src "build/ls180/gateware/ls180.v:3674.294-3674.373" + cell $and $and$build/ls180/gateware/ls180.v:3674$251 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine3_cmd_valid + connect \B \main_sdram_bankmachine3_cmd_payload_is_read + connect \Y $and$build/ls180/gateware/ls180.v:3674$251_Y + end + attribute \src "build/ls180/gateware/ls180.v:3675.41-3675.121" + cell $and $and$build/ls180/gateware/ls180.v:3675$253 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine0_cmd_valid + connect \B \main_sdram_bankmachine0_cmd_payload_is_write + connect \Y $and$build/ls180/gateware/ls180.v:3675$253_Y + end + attribute \src "build/ls180/gateware/ls180.v:3675.126-3675.206" + cell $and $and$build/ls180/gateware/ls180.v:3675$254 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine1_cmd_valid + connect \B \main_sdram_bankmachine1_cmd_payload_is_write + connect \Y $and$build/ls180/gateware/ls180.v:3675$254_Y + end + attribute \src "build/ls180/gateware/ls180.v:3675.212-3675.292" + cell $and $and$build/ls180/gateware/ls180.v:3675$256 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine2_cmd_valid + connect \B \main_sdram_bankmachine2_cmd_payload_is_write + connect \Y $and$build/ls180/gateware/ls180.v:3675$256_Y + end + attribute \src "build/ls180/gateware/ls180.v:3675.298-3675.378" + cell $and $and$build/ls180/gateware/ls180.v:3675$258 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine3_cmd_valid + connect \B \main_sdram_bankmachine3_cmd_payload_is_write + connect \Y $and$build/ls180/gateware/ls180.v:3675$258_Y + end + attribute \src "build/ls180/gateware/ls180.v:3682.38-3682.111" + cell $and $and$build/ls180/gateware/ls180.v:3682$262 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine0_refresh_gnt + connect \B \main_sdram_bankmachine1_refresh_gnt + connect \Y $and$build/ls180/gateware/ls180.v:3682$262_Y + end + attribute \src "build/ls180/gateware/ls180.v:3682.37-3682.150" + cell $and $and$build/ls180/gateware/ls180.v:3682$263 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$build/ls180/gateware/ls180.v:3682$262_Y + connect \B \main_sdram_bankmachine2_refresh_gnt + connect \Y $and$build/ls180/gateware/ls180.v:3682$263_Y + end + attribute \src "build/ls180/gateware/ls180.v:3682.36-3682.189" + cell $and $and$build/ls180/gateware/ls180.v:3682$264 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$build/ls180/gateware/ls180.v:3682$263_Y + connect \B \main_sdram_bankmachine3_refresh_gnt + connect \Y $and$build/ls180/gateware/ls180.v:3682$264_Y + end + attribute \src "build/ls180/gateware/ls180.v:3688.77-3688.153" + cell $and $and$build/ls180/gateware/ls180.v:3688$267 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine0_cmd_payload_is_cmd + connect \B \main_sdram_choose_cmd_want_cmds + connect \Y $and$build/ls180/gateware/ls180.v:3688$267_Y + end + attribute \src "build/ls180/gateware/ls180.v:3688.162-3688.246" + cell $and $and$build/ls180/gateware/ls180.v:3688$269 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine0_cmd_payload_ras + connect \B $not$build/ls180/gateware/ls180.v:3688$268_Y + connect \Y $and$build/ls180/gateware/ls180.v:3688$269_Y + end + attribute \src "build/ls180/gateware/ls180.v:3688.161-3688.291" + cell $and $and$build/ls180/gateware/ls180.v:3688$271 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$build/ls180/gateware/ls180.v:3688$269_Y + connect \B $not$build/ls180/gateware/ls180.v:3688$270_Y + connect \Y $and$build/ls180/gateware/ls180.v:3688$271_Y + end + attribute \src "build/ls180/gateware/ls180.v:3688.76-3688.333" + cell $and $and$build/ls180/gateware/ls180.v:3688$274 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$build/ls180/gateware/ls180.v:3688$267_Y + connect \B $or$build/ls180/gateware/ls180.v:3688$273_Y + connect \Y $and$build/ls180/gateware/ls180.v:3688$274_Y + end + attribute \src "build/ls180/gateware/ls180.v:3688.338-3688.505" + cell $and $and$build/ls180/gateware/ls180.v:3688$277 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $eq$build/ls180/gateware/ls180.v:3688$275_Y + connect \B $eq$build/ls180/gateware/ls180.v:3688$276_Y + connect \Y $and$build/ls180/gateware/ls180.v:3688$277_Y + end + attribute \src "build/ls180/gateware/ls180.v:3688.38-3688.507" + cell $and $and$build/ls180/gateware/ls180.v:3688$279 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine0_cmd_valid + connect \B $or$build/ls180/gateware/ls180.v:3688$278_Y + connect \Y $and$build/ls180/gateware/ls180.v:3688$279_Y + end + attribute \src "build/ls180/gateware/ls180.v:3689.77-3689.153" + cell $and $and$build/ls180/gateware/ls180.v:3689$280 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine1_cmd_payload_is_cmd + connect \B \main_sdram_choose_cmd_want_cmds + connect \Y $and$build/ls180/gateware/ls180.v:3689$280_Y + end + attribute \src "build/ls180/gateware/ls180.v:3689.162-3689.246" + cell $and $and$build/ls180/gateware/ls180.v:3689$282 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine1_cmd_payload_ras + connect \B $not$build/ls180/gateware/ls180.v:3689$281_Y + connect \Y $and$build/ls180/gateware/ls180.v:3689$282_Y + end + attribute \src "build/ls180/gateware/ls180.v:3689.161-3689.291" + cell $and $and$build/ls180/gateware/ls180.v:3689$284 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$build/ls180/gateware/ls180.v:3689$282_Y + connect \B $not$build/ls180/gateware/ls180.v:3689$283_Y + connect \Y $and$build/ls180/gateware/ls180.v:3689$284_Y + end + attribute \src "build/ls180/gateware/ls180.v:3689.76-3689.333" + cell $and $and$build/ls180/gateware/ls180.v:3689$287 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$build/ls180/gateware/ls180.v:3689$280_Y + connect \B $or$build/ls180/gateware/ls180.v:3689$286_Y + connect \Y $and$build/ls180/gateware/ls180.v:3689$287_Y + end + attribute \src "build/ls180/gateware/ls180.v:3689.338-3689.505" + cell $and $and$build/ls180/gateware/ls180.v:3689$290 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $eq$build/ls180/gateware/ls180.v:3689$288_Y + connect \B $eq$build/ls180/gateware/ls180.v:3689$289_Y + connect \Y $and$build/ls180/gateware/ls180.v:3689$290_Y + end + attribute \src "build/ls180/gateware/ls180.v:3689.38-3689.507" + cell $and $and$build/ls180/gateware/ls180.v:3689$292 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine1_cmd_valid + connect \B $or$build/ls180/gateware/ls180.v:3689$291_Y + connect \Y $and$build/ls180/gateware/ls180.v:3689$292_Y + end + attribute \src "build/ls180/gateware/ls180.v:3690.77-3690.153" + cell $and $and$build/ls180/gateware/ls180.v:3690$293 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine2_cmd_payload_is_cmd + connect \B \main_sdram_choose_cmd_want_cmds + connect \Y $and$build/ls180/gateware/ls180.v:3690$293_Y + end + attribute \src "build/ls180/gateware/ls180.v:3690.162-3690.246" + cell $and $and$build/ls180/gateware/ls180.v:3690$295 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine2_cmd_payload_ras + connect \B $not$build/ls180/gateware/ls180.v:3690$294_Y + connect \Y $and$build/ls180/gateware/ls180.v:3690$295_Y + end + attribute \src "build/ls180/gateware/ls180.v:3690.161-3690.291" + cell $and $and$build/ls180/gateware/ls180.v:3690$297 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$build/ls180/gateware/ls180.v:3690$295_Y + connect \B $not$build/ls180/gateware/ls180.v:3690$296_Y + connect \Y $and$build/ls180/gateware/ls180.v:3690$297_Y + end + attribute \src "build/ls180/gateware/ls180.v:3690.76-3690.333" + cell $and $and$build/ls180/gateware/ls180.v:3690$300 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$build/ls180/gateware/ls180.v:3690$293_Y + connect \B $or$build/ls180/gateware/ls180.v:3690$299_Y + connect \Y $and$build/ls180/gateware/ls180.v:3690$300_Y + end + attribute \src "build/ls180/gateware/ls180.v:3690.338-3690.505" + cell $and $and$build/ls180/gateware/ls180.v:3690$303 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $eq$build/ls180/gateware/ls180.v:3690$301_Y + connect \B $eq$build/ls180/gateware/ls180.v:3690$302_Y + connect \Y $and$build/ls180/gateware/ls180.v:3690$303_Y + end + attribute \src "build/ls180/gateware/ls180.v:3690.38-3690.507" + cell $and $and$build/ls180/gateware/ls180.v:3690$305 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine2_cmd_valid + connect \B $or$build/ls180/gateware/ls180.v:3690$304_Y + connect \Y $and$build/ls180/gateware/ls180.v:3690$305_Y + end + attribute \src "build/ls180/gateware/ls180.v:3691.77-3691.153" + cell $and $and$build/ls180/gateware/ls180.v:3691$306 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine3_cmd_payload_is_cmd + connect \B \main_sdram_choose_cmd_want_cmds + connect \Y $and$build/ls180/gateware/ls180.v:3691$306_Y + end + attribute \src "build/ls180/gateware/ls180.v:3691.162-3691.246" + cell $and $and$build/ls180/gateware/ls180.v:3691$308 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 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\main_sdram_choose_req_cmd_valid + connect \B \main_sdram_choose_req_cmd_ready + connect \Y $and$build/ls180/gateware/ls180.v:3756$384_Y + end + attribute \src "build/ls180/gateware/ls180.v:3756.7-3756.114" + cell $and $and$build/ls180/gateware/ls180.v:3756$386 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$build/ls180/gateware/ls180.v:3756$384_Y + connect \B $eq$build/ls180/gateware/ls180.v:3756$385_Y + connect \Y $and$build/ls180/gateware/ls180.v:3756$386_Y + end + attribute \src "build/ls180/gateware/ls180.v:3762.8-3762.73" + cell $and $and$build/ls180/gateware/ls180.v:3762$388 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_cmd_cmd_valid + connect \B \main_sdram_choose_cmd_cmd_ready + connect \Y $and$build/ls180/gateware/ls180.v:3762$388_Y + end + attribute \src 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$and$build/ls180/gateware/ls180.v:3771$397_Y + end + attribute \src "build/ls180/gateware/ls180.v:3774.8-3774.73" + cell $and $and$build/ls180/gateware/ls180.v:3774$398 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_req_cmd_valid + connect \B \main_sdram_choose_req_cmd_ready + connect \Y $and$build/ls180/gateware/ls180.v:3774$398_Y + end + attribute \src "build/ls180/gateware/ls180.v:3774.7-3774.114" + cell $and $and$build/ls180/gateware/ls180.v:3774$400 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$build/ls180/gateware/ls180.v:3774$398_Y + connect \B $eq$build/ls180/gateware/ls180.v:3774$399_Y + connect \Y $and$build/ls180/gateware/ls180.v:3774$400_Y + end + attribute \src "build/ls180/gateware/ls180.v:3780.8-3780.73" + cell $and $and$build/ls180/gateware/ls180.v:3780$402 + parameter \A_SIGNED 0 + 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\Y $and$build/ls180/gateware/ls180.v:3783$405_Y + end + attribute \src "build/ls180/gateware/ls180.v:3783.7-3783.114" + cell $and $and$build/ls180/gateware/ls180.v:3783$407 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$build/ls180/gateware/ls180.v:3783$405_Y + connect \B $eq$build/ls180/gateware/ls180.v:3783$406_Y + connect \Y $and$build/ls180/gateware/ls180.v:3783$407_Y + end + attribute \src "build/ls180/gateware/ls180.v:3808.71-3808.151" + cell $and $and$build/ls180/gateware/ls180.v:3808$412 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_req_cmd_payload_ras + connect \B $not$build/ls180/gateware/ls180.v:3808$411_Y + connect \Y $and$build/ls180/gateware/ls180.v:3808$412_Y + end + attribute \src "build/ls180/gateware/ls180.v:3808.70-3808.194" + cell $and $and$build/ls180/gateware/ls180.v:3808$414 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$and$build/ls180/gateware/ls180.v:3869$456_Y + end + attribute \src "build/ls180/gateware/ls180.v:3869.40-3869.355" + cell $and $and$build/ls180/gateware/ls180.v:3869$457 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$build/ls180/gateware/ls180.v:3869$456_Y + connect \B \main_port_cmd_valid + connect \Y $and$build/ls180/gateware/ls180.v:3869$457_Y + end + attribute \src "build/ls180/gateware/ls180.v:3870.34-3870.106" + cell $and $and$build/ls180/gateware/ls180.v:3870$460 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $not$build/ls180/gateware/ls180.v:3870$458_Y + connect \B $not$build/ls180/gateware/ls180.v:3870$459_Y + connect \Y $and$build/ls180/gateware/ls180.v:3870$460_Y + end + attribute \src "build/ls180/gateware/ls180.v:3874.110-3874.179" + cell $and $and$build/ls180/gateware/ls180.v:3874$463 + parameter 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$eq$build/ls180/gateware/ls180.v:3874$468_Y + connect \Y $and$build/ls180/gateware/ls180.v:3874$469_Y + end + attribute \src "build/ls180/gateware/ls180.v:3874.41-3874.332" + cell $and $and$build/ls180/gateware/ls180.v:3874$472 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $eq$build/ls180/gateware/ls180.v:3874$461_Y + connect \B $not$build/ls180/gateware/ls180.v:3874$471_Y + connect \Y $and$build/ls180/gateware/ls180.v:3874$472_Y + end + attribute \src "build/ls180/gateware/ls180.v:3874.40-3874.355" + cell $and $and$build/ls180/gateware/ls180.v:3874$473 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$build/ls180/gateware/ls180.v:3874$472_Y + connect \B \main_port_cmd_valid + connect \Y $and$build/ls180/gateware/ls180.v:3874$473_Y + end + attribute \src "build/ls180/gateware/ls180.v:3875.34-3875.106" + cell $and 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\main_sdram_interface_bank1_lock + connect \B $eq$build/ls180/gateware/ls180.v:3879$481_Y + connect \Y $and$build/ls180/gateware/ls180.v:3879$482_Y + end + attribute \src "build/ls180/gateware/ls180.v:3879.260-3879.329" + cell $and $and$build/ls180/gateware/ls180.v:3879$485 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_interface_bank2_lock + connect \B $eq$build/ls180/gateware/ls180.v:3879$484_Y + connect \Y $and$build/ls180/gateware/ls180.v:3879$485_Y + end + attribute \src "build/ls180/gateware/ls180.v:3879.41-3879.332" + cell $and $and$build/ls180/gateware/ls180.v:3879$488 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $eq$build/ls180/gateware/ls180.v:3879$477_Y + connect \B $not$build/ls180/gateware/ls180.v:3879$487_Y + connect \Y $and$build/ls180/gateware/ls180.v:3879$488_Y + end + attribute \src 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\B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_interface_bank1_lock + connect \B $eq$build/ls180/gateware/ls180.v:3884$495_Y + connect \Y $and$build/ls180/gateware/ls180.v:3884$496_Y + end + attribute \src "build/ls180/gateware/ls180.v:3884.226-3884.295" + cell $and $and$build/ls180/gateware/ls180.v:3884$499 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_interface_bank2_lock + connect \B $eq$build/ls180/gateware/ls180.v:3884$498_Y + connect \Y $and$build/ls180/gateware/ls180.v:3884$499_Y + end + attribute \src "build/ls180/gateware/ls180.v:3884.301-3884.370" + cell $and $and$build/ls180/gateware/ls180.v:3884$502 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_interface_bank3_lock + connect \B $eq$build/ls180/gateware/ls180.v:3884$501_Y + connect \Y $and$build/ls180/gateware/ls180.v:3884$502_Y + end + attribute \src "build/ls180/gateware/ls180.v:3884.82-3884.373" + cell $and $and$build/ls180/gateware/ls180.v:3884$505 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $eq$build/ls180/gateware/ls180.v:3884$494_Y + connect \B $not$build/ls180/gateware/ls180.v:3884$504_Y + connect \Y $and$build/ls180/gateware/ls180.v:3884$505_Y + end + attribute \src "build/ls180/gateware/ls180.v:3884.43-3884.374" + cell $and $and$build/ls180/gateware/ls180.v:3884$506 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $eq$build/ls180/gateware/ls180.v:3884$493_Y + connect \B $and$build/ls180/gateware/ls180.v:3884$505_Y + connect \Y $and$build/ls180/gateware/ls180.v:3884$506_Y + end + attribute \src "build/ls180/gateware/ls180.v:3884.42-3884.410" + cell $and $and$build/ls180/gateware/ls180.v:3884$507 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$build/ls180/gateware/ls180.v:3884$506_Y + connect \B \main_sdram_interface_bank0_ready + connect \Y $and$build/ls180/gateware/ls180.v:3884$507_Y + end + attribute \src "build/ls180/gateware/ls180.v:3884.525-3884.594" + cell $and $and$build/ls180/gateware/ls180.v:3884$512 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_interface_bank0_lock + connect \B $eq$build/ls180/gateware/ls180.v:3884$511_Y + connect \Y $and$build/ls180/gateware/ls180.v:3884$512_Y + end + attribute \src "build/ls180/gateware/ls180.v:3884.600-3884.669" + cell $and $and$build/ls180/gateware/ls180.v:3884$515 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_interface_bank2_lock + connect \B $eq$build/ls180/gateware/ls180.v:3884$514_Y + connect \Y $and$build/ls180/gateware/ls180.v:3884$515_Y + end + attribute \src "build/ls180/gateware/ls180.v:3884.675-3884.744" + cell $and $and$build/ls180/gateware/ls180.v:3884$518 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_interface_bank3_lock + connect \B $eq$build/ls180/gateware/ls180.v:3884$517_Y + connect \Y $and$build/ls180/gateware/ls180.v:3884$518_Y + end + attribute \src "build/ls180/gateware/ls180.v:3884.456-3884.747" + cell $and $and$build/ls180/gateware/ls180.v:3884$521 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $eq$build/ls180/gateware/ls180.v:3884$510_Y + connect \B $not$build/ls180/gateware/ls180.v:3884$520_Y + connect \Y $and$build/ls180/gateware/ls180.v:3884$521_Y + end + attribute \src "build/ls180/gateware/ls180.v:3884.417-3884.748" + cell $and $and$build/ls180/gateware/ls180.v:3884$522 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $eq$build/ls180/gateware/ls180.v:3884$509_Y + connect \B $and$build/ls180/gateware/ls180.v:3884$521_Y + connect \Y $and$build/ls180/gateware/ls180.v:3884$522_Y + end + attribute \src "build/ls180/gateware/ls180.v:3884.416-3884.784" + cell $and $and$build/ls180/gateware/ls180.v:3884$523 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$build/ls180/gateware/ls180.v:3884$522_Y + connect \B \main_sdram_interface_bank1_ready + connect \Y $and$build/ls180/gateware/ls180.v:3884$523_Y + end + attribute \src "build/ls180/gateware/ls180.v:3884.899-3884.968" + cell $and $and$build/ls180/gateware/ls180.v:3884$528 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_interface_bank0_lock + connect \B $eq$build/ls180/gateware/ls180.v:3884$527_Y + connect \Y $and$build/ls180/gateware/ls180.v:3884$528_Y + end + attribute \src "build/ls180/gateware/ls180.v:3884.974-3884.1043" + cell $and $and$build/ls180/gateware/ls180.v:3884$531 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_interface_bank1_lock + connect \B $eq$build/ls180/gateware/ls180.v:3884$530_Y + connect \Y $and$build/ls180/gateware/ls180.v:3884$531_Y + end + attribute \src "build/ls180/gateware/ls180.v:3884.1049-3884.1118" + cell $and $and$build/ls180/gateware/ls180.v:3884$534 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_interface_bank3_lock + connect \B $eq$build/ls180/gateware/ls180.v:3884$533_Y + connect \Y $and$build/ls180/gateware/ls180.v:3884$534_Y + end + attribute \src "build/ls180/gateware/ls180.v:3884.830-3884.1121" + cell $and $and$build/ls180/gateware/ls180.v:3884$537 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $eq$build/ls180/gateware/ls180.v:3884$526_Y + connect \B $not$build/ls180/gateware/ls180.v:3884$536_Y + connect \Y $and$build/ls180/gateware/ls180.v:3884$537_Y + end + attribute \src "build/ls180/gateware/ls180.v:3884.791-3884.1122" + cell $and $and$build/ls180/gateware/ls180.v:3884$538 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $eq$build/ls180/gateware/ls180.v:3884$525_Y + connect \B $and$build/ls180/gateware/ls180.v:3884$537_Y + connect \Y $and$build/ls180/gateware/ls180.v:3884$538_Y + end + attribute \src "build/ls180/gateware/ls180.v:3884.790-3884.1158" + cell $and $and$build/ls180/gateware/ls180.v:3884$539 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$build/ls180/gateware/ls180.v:3884$538_Y + connect \B \main_sdram_interface_bank2_ready + connect \Y $and$build/ls180/gateware/ls180.v:3884$539_Y + end + attribute \src "build/ls180/gateware/ls180.v:3884.1273-3884.1342" + cell $and $and$build/ls180/gateware/ls180.v:3884$544 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_interface_bank0_lock + connect \B $eq$build/ls180/gateware/ls180.v:3884$543_Y + connect \Y $and$build/ls180/gateware/ls180.v:3884$544_Y + end + attribute \src "build/ls180/gateware/ls180.v:3884.1348-3884.1417" + cell $and $and$build/ls180/gateware/ls180.v:3884$547 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_interface_bank1_lock + connect \B $eq$build/ls180/gateware/ls180.v:3884$546_Y + connect \Y $and$build/ls180/gateware/ls180.v:3884$547_Y + end + attribute \src "build/ls180/gateware/ls180.v:3884.1423-3884.1492" + cell $and $and$build/ls180/gateware/ls180.v:3884$550 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_interface_bank2_lock + connect \B $eq$build/ls180/gateware/ls180.v:3884$549_Y + connect \Y $and$build/ls180/gateware/ls180.v:3884$550_Y + end + attribute \src "build/ls180/gateware/ls180.v:3884.1204-3884.1495" + cell $and $and$build/ls180/gateware/ls180.v:3884$553 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $eq$build/ls180/gateware/ls180.v:3884$542_Y + connect \B $not$build/ls180/gateware/ls180.v:3884$552_Y + connect \Y $and$build/ls180/gateware/ls180.v:3884$553_Y + end + attribute \src "build/ls180/gateware/ls180.v:3884.1165-3884.1496" + cell $and $and$build/ls180/gateware/ls180.v:3884$554 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $eq$build/ls180/gateware/ls180.v:3884$541_Y + connect \B $and$build/ls180/gateware/ls180.v:3884$553_Y + connect \Y $and$build/ls180/gateware/ls180.v:3884$554_Y + end + attribute \src "build/ls180/gateware/ls180.v:3884.1164-3884.1532" + cell $and $and$build/ls180/gateware/ls180.v:3884$555 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$build/ls180/gateware/ls180.v:3884$554_Y + connect \B \main_sdram_interface_bank3_ready + connect \Y $and$build/ls180/gateware/ls180.v:3884$555_Y + end + attribute \src "build/ls180/gateware/ls180.v:3942.9-3942.46" + cell $and $and$build/ls180/gateware/ls180.v:3942$561 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_wb_sdram_stb + connect \B \main_wb_sdram_cyc + connect \Y $and$build/ls180/gateware/ls180.v:3942$561_Y + end + attribute \src "build/ls180/gateware/ls180.v:3960.9-3960.46" + cell $and $and$build/ls180/gateware/ls180.v:3960$568 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_wb_sdram_stb + connect \B \main_wb_sdram_cyc + connect \Y $and$build/ls180/gateware/ls180.v:3960$568_Y + end + attribute \src "build/ls180/gateware/ls180.v:3973.32-3973.75" + cell $and $and$build/ls180/gateware/ls180.v:3973$572 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_litedram_wb_cyc + connect \B \main_litedram_wb_stb + connect \Y $and$build/ls180/gateware/ls180.v:3973$572_Y + end + attribute \src "build/ls180/gateware/ls180.v:3973.31-3973.99" + cell $and $and$build/ls180/gateware/ls180.v:3973$574 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$build/ls180/gateware/ls180.v:3973$572_Y + connect \B $not$build/ls180/gateware/ls180.v:3973$573_Y + connect \Y $and$build/ls180/gateware/ls180.v:3973$574_Y + end + attribute \src "build/ls180/gateware/ls180.v:3974.34-3974.102" + cell $and $and$build/ls180/gateware/ls180.v:3974$576 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$build/ls180/gateware/ls180.v:3974$575_Y + connect \B \main_port_cmd_payload_we + connect \Y $and$build/ls180/gateware/ls180.v:3974$576_Y + end + attribute \src "build/ls180/gateware/ls180.v:3974.33-3974.128" + cell $and $and$build/ls180/gateware/ls180.v:3974$578 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$build/ls180/gateware/ls180.v:3974$576_Y + connect \B $not$build/ls180/gateware/ls180.v:3974$577_Y + connect \Y $and$build/ls180/gateware/ls180.v:3974$578_Y + end + attribute \src "build/ls180/gateware/ls180.v:3975.33-3975.104" + cell $and $and$build/ls180/gateware/ls180.v:3975$581 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$build/ls180/gateware/ls180.v:3975$579_Y + connect \B $not$build/ls180/gateware/ls180.v:3975$580_Y + connect \Y $and$build/ls180/gateware/ls180.v:3975$581_Y + end + attribute \src "build/ls180/gateware/ls180.v:3976.49-3976.85" + cell $and $and$build/ls180/gateware/ls180.v:3976$582 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_litedram_wb_we + connect \B \main_ack_wdata + connect \Y $and$build/ls180/gateware/ls180.v:3976$582_Y + end + attribute \src "build/ls180/gateware/ls180.v:3976.90-3976.129" + cell $and $and$build/ls180/gateware/ls180.v:3976$584 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $not$build/ls180/gateware/ls180.v:3976$583_Y + connect \B \main_ack_rdata + connect \Y $and$build/ls180/gateware/ls180.v:3976$584_Y + end + attribute \src "build/ls180/gateware/ls180.v:3976.32-3976.131" + cell $and $and$build/ls180/gateware/ls180.v:3976$586 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_ack_cmd + connect \B $or$build/ls180/gateware/ls180.v:3976$585_Y + connect \Y $and$build/ls180/gateware/ls180.v:3976$586_Y + end + attribute \src "build/ls180/gateware/ls180.v:3977.25-3977.66" + cell $and $and$build/ls180/gateware/ls180.v:3977$587 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_port_cmd_valid + connect \B \main_port_cmd_ready + connect \Y $and$build/ls180/gateware/ls180.v:3977$587_Y + end + attribute \src "build/ls180/gateware/ls180.v:3978.27-3978.72" + cell $and $and$build/ls180/gateware/ls180.v:3978$589 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_port_wdata_valid + connect \B \main_port_wdata_ready + connect \Y $and$build/ls180/gateware/ls180.v:3978$589_Y + end + attribute \src "build/ls180/gateware/ls180.v:3979.26-3979.71" + cell $and $and$build/ls180/gateware/ls180.v:3979$591 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_port_rdata_valid + connect \B \main_port_rdata_ready + connect \Y $and$build/ls180/gateware/ls180.v:3979$591_Y + end + attribute \src "build/ls180/gateware/ls180.v:4094.34-4094.89" + cell $and $and$build/ls180/gateware/ls180.v:4094$623 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \libresocsim_clocker_clk1 + connect \B $not$build/ls180/gateware/ls180.v:4094$622_Y + connect \Y $and$build/ls180/gateware/ls180.v:4094$623_Y + end + attribute \src "build/ls180/gateware/ls180.v:4198.9-4198.70" + cell $and $and$build/ls180/gateware/ls180.v:4198$632 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \libresocsim_cmdw_sink_valid + connect \B \libresocsim_cmdw_pads_out_ready + connect \Y $and$build/ls180/gateware/ls180.v:4198$632_Y + end + attribute \src "build/ls180/gateware/ls180.v:4218.54-4218.149" + cell $and $and$build/ls180/gateware/ls180.v:4218$635 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \libresocsim_cmdr_cmdr_pads_in_valid + connect \B $or$build/ls180/gateware/ls180.v:4218$634_Y + connect \Y $and$build/ls180/gateware/ls180.v:4218$635_Y + end + attribute \src "build/ls180/gateware/ls180.v:4237.53-4237.140" + cell $and $and$build/ls180/gateware/ls180.v:4237$638 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \libresocsim_cmdr_cmdr_converter_sink_valid + connect \B \libresocsim_cmdr_cmdr_converter_sink_ready + connect \Y $and$build/ls180/gateware/ls180.v:4237$638_Y + end + attribute \src "build/ls180/gateware/ls180.v:4278.9-4278.70" + cell $and $and$build/ls180/gateware/ls180.v:4278$646 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \libresocsim_cmdr_source_valid + connect \B \libresocsim_cmdr_source_ready + connect \Y $and$build/ls180/gateware/ls180.v:4278$646_Y + end + attribute \src "build/ls180/gateware/ls180.v:4316.9-4316.70" + cell $and $and$build/ls180/gateware/ls180.v:4316$652 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \libresocsim_cmdr_source_valid + connect \B \libresocsim_cmdr_source_ready + connect \Y $and$build/ls180/gateware/ls180.v:4316$652_Y + end + attribute \src "build/ls180/gateware/ls180.v:4325.10-4325.71" + cell $and $and$build/ls180/gateware/ls180.v:4325$653 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \libresocsim_cmdr_sink_valid + connect \B \libresocsim_cmdr_pads_out_ready + connect \Y $and$build/ls180/gateware/ls180.v:4325$653_Y + end + attribute \src "build/ls180/gateware/ls180.v:4325.9-4325.96" + cell $and $and$build/ls180/gateware/ls180.v:4325$654 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$build/ls180/gateware/ls180.v:4325$653_Y + connect \B \libresocsim_cmdw_done + connect \Y $and$build/ls180/gateware/ls180.v:4325$654_Y + end + attribute \src "build/ls180/gateware/ls180.v:4345.55-4345.120" + cell $and $and$build/ls180/gateware/ls180.v:4345$656 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \libresocsim_dataw_crcr_pads_in_valid + connect \B \libresocsim_dataw_crcr_run + connect \Y $and$build/ls180/gateware/ls180.v:4345$656_Y + end + attribute \src "build/ls180/gateware/ls180.v:4364.54-4364.143" + cell $and $and$build/ls180/gateware/ls180.v:4364$659 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \libresocsim_dataw_crcr_converter_sink_valid + connect \B \libresocsim_dataw_crcr_converter_sink_ready + connect \Y $and$build/ls180/gateware/ls180.v:4364$659_Y + end + attribute \src "build/ls180/gateware/ls180.v:4461.9-4461.72" + cell $and $and$build/ls180/gateware/ls180.v:4461$669 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \libresocsim_dataw_sink_valid + connect \B \libresocsim_dataw_pads_out_ready + connect \Y $and$build/ls180/gateware/ls180.v:4461$669_Y + end + attribute \src "build/ls180/gateware/ls180.v:4479.56-4479.123" + cell $and $and$build/ls180/gateware/ls180.v:4479$671 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \libresocsim_datar_datar_pads_in_valid + connect \B \libresocsim_datar_datar_run + connect \Y $and$build/ls180/gateware/ls180.v:4479$671_Y + end + attribute \src "build/ls180/gateware/ls180.v:4498.55-4498.146" + cell $and $and$build/ls180/gateware/ls180.v:4498$674 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \libresocsim_datar_datar_converter_sink_valid + connect \B \libresocsim_datar_datar_converter_sink_ready + connect \Y $and$build/ls180/gateware/ls180.v:4498$674_Y + end + attribute \src "build/ls180/gateware/ls180.v:4580.9-4580.72" + cell $and $and$build/ls180/gateware/ls180.v:4580$689 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \libresocsim_datar_source_valid + connect \B \libresocsim_datar_source_ready + connect \Y $and$build/ls180/gateware/ls180.v:4580$689_Y + end + attribute \src "build/ls180/gateware/ls180.v:4587.9-4587.72" + cell $and $and$build/ls180/gateware/ls180.v:4587$690 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \libresocsim_datar_sink_valid + connect \B \libresocsim_datar_pads_out_ready + connect \Y $and$build/ls180/gateware/ls180.v:4587$690_Y + end + attribute \src "build/ls180/gateware/ls180.v:4668.55-4668.145" + cell $and $and$build/ls180/gateware/ls180.v:4668$813 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \libresocsim_sdcore_crc16_inserter_sink_last + connect \B \libresocsim_sdcore_crc16_inserter_sink_valid + connect \Y $and$build/ls180/gateware/ls180.v:4668$813_Y + end + attribute \src "build/ls180/gateware/ls180.v:4668.54-4668.193" + cell $and $and$build/ls180/gateware/ls180.v:4668$814 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$build/ls180/gateware/ls180.v:4668$813_Y + connect \B \libresocsim_sdcore_crc16_inserter_sink_ready + connect \Y $and$build/ls180/gateware/ls180.v:4668$814_Y + end + attribute \src "build/ls180/gateware/ls180.v:4669.57-4669.148" + cell $and $and$build/ls180/gateware/ls180.v:4669$815 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \libresocsim_sdcore_crc16_inserter_sink_valid + connect \B \libresocsim_sdcore_crc16_inserter_sink_ready + connect \Y $and$build/ls180/gateware/ls180.v:4669$815_Y + end + attribute \src "build/ls180/gateware/ls180.v:4671.55-4671.145" + cell $and $and$build/ls180/gateware/ls180.v:4671$816 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \libresocsim_sdcore_crc16_inserter_sink_last + connect \B \libresocsim_sdcore_crc16_inserter_sink_valid + connect \Y $and$build/ls180/gateware/ls180.v:4671$816_Y + end + attribute \src "build/ls180/gateware/ls180.v:4671.54-4671.193" + cell $and $and$build/ls180/gateware/ls180.v:4671$817 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$build/ls180/gateware/ls180.v:4671$816_Y + connect \B \libresocsim_sdcore_crc16_inserter_sink_ready + connect \Y $and$build/ls180/gateware/ls180.v:4671$817_Y + end + attribute \src "build/ls180/gateware/ls180.v:4672.57-4672.148" + cell $and $and$build/ls180/gateware/ls180.v:4672$818 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \libresocsim_sdcore_crc16_inserter_sink_valid + connect \B \libresocsim_sdcore_crc16_inserter_sink_ready + connect \Y $and$build/ls180/gateware/ls180.v:4672$818_Y + end + attribute \src "build/ls180/gateware/ls180.v:4674.55-4674.145" + cell $and $and$build/ls180/gateware/ls180.v:4674$819 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \libresocsim_sdcore_crc16_inserter_sink_last + connect \B \libresocsim_sdcore_crc16_inserter_sink_valid + connect \Y $and$build/ls180/gateware/ls180.v:4674$819_Y + end + attribute \src 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\libresocsim_sdcore_crc16_inserter_sink_ready + connect \Y $and$build/ls180/gateware/ls180.v:4678$824_Y + end + attribute \src "build/ls180/gateware/ls180.v:4791.10-4791.100" + cell $and $and$build/ls180/gateware/ls180.v:4791$873 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \libresocsim_sdcore_crc16_inserter_sink_valid + connect \B \libresocsim_sdcore_crc16_inserter_sink_last + connect \Y $and$build/ls180/gateware/ls180.v:4791$873_Y + end + attribute \src "build/ls180/gateware/ls180.v:4791.9-4791.148" + cell $and $and$build/ls180/gateware/ls180.v:4791$874 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$build/ls180/gateware/ls180.v:4791$873_Y + connect \B \libresocsim_sdcore_crc16_inserter_sink_ready + connect \Y $and$build/ls180/gateware/ls180.v:4791$874_Y + end + attribute \src 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connect \Y $and$build/ls180/gateware/ls180.v:4816$886_Y + end + attribute \src "build/ls180/gateware/ls180.v:4826.56-4826.145" + cell $and $and$build/ls180/gateware/ls180.v:4826$889 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \libresocsim_sdcore_crc16_checker_sink_valid + connect \B \libresocsim_sdcore_crc16_checker_sink_ready + connect \Y $and$build/ls180/gateware/ls180.v:4826$889_Y + end + attribute \src "build/ls180/gateware/ls180.v:4836.56-4836.145" + cell $and $and$build/ls180/gateware/ls180.v:4836$892 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \libresocsim_sdcore_crc16_checker_sink_valid + connect \B \libresocsim_sdcore_crc16_checker_sink_ready + connect \Y $and$build/ls180/gateware/ls180.v:4836$892_Y + end + attribute \src "build/ls180/gateware/ls180.v:4848.7-4848.98" + cell $and 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\A \libresocsim_sdblock2mem_converter_sink_valid + connect \B \libresocsim_sdblock2mem_converter_sink_ready + connect \Y $and$build/ls180/gateware/ls180.v:5141$978_Y + end + attribute \src "build/ls180/gateware/ls180.v:5168.9-5168.116" + cell $and $and$build/ls180/gateware/ls180.v:5168$982 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \libresocsim_sdblock2mem_wishbonedmawriter_sink_valid + connect \B \libresocsim_sdblock2mem_wishbonedmawriter_sink_ready + connect \Y $and$build/ls180/gateware/ls180.v:5168$982_Y + end + attribute \src "build/ls180/gateware/ls180.v:5241.9-5241.72" + cell $and $and$build/ls180/gateware/ls180.v:5241$988 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \libresocsim_interface1_bus_stb + connect \B \libresocsim_interface1_bus_ack + connect \Y $and$build/ls180/gateware/ls180.v:5241$988_Y + end + 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parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \libresocsim_sdmem2block_converter_last + connect \B \libresocsim_sdmem2block_converter_source_ready + connect \Y $and$build/ls180/gateware/ls180.v:5296$998_Y + end + attribute \src "build/ls180/gateware/ls180.v:5336.50-5336.180" + cell $and $and$build/ls180/gateware/ls180.v:5336$1003 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \libresocsim_sdmem2block_fifo_syncfifo_we + connect \B $or$build/ls180/gateware/ls180.v:5336$1002_Y + connect \Y $and$build/ls180/gateware/ls180.v:5336$1003_Y + end + attribute \src "build/ls180/gateware/ls180.v:5337.48-5337.137" + cell $and $and$build/ls180/gateware/ls180.v:5337$1004 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \libresocsim_sdmem2block_fifo_syncfifo_readable + connect \B \libresocsim_sdmem2block_fifo_syncfifo_re + connect \Y $and$build/ls180/gateware/ls180.v:5337$1004_Y + end + attribute \src "build/ls180/gateware/ls180.v:5428.9-5428.76" + cell $and $and$build/ls180/gateware/ls180.v:5428$1016 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_libresocsim_wishbone_cyc + connect \B \builder_libresocsim_wishbone_stb + connect \Y $and$build/ls180/gateware/ls180.v:5428$1016_Y + end + attribute \src "build/ls180/gateware/ls180.v:5431.44-5431.120" + cell $and $and$build/ls180/gateware/ls180.v:5431$1018 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_libresocsim_wishbone_we + connect \B $ne$build/ls180/gateware/ls180.v:5431$1017_Y + connect \Y $and$build/ls180/gateware/ls180.v:5431$1018_Y + end + attribute \src "build/ls180/gateware/ls180.v:5450.63-5450.107" + cell $and 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$eq$build/ls180/gateware/ls180.v:5452$1023_Y + connect \Y $and$build/ls180/gateware/ls180.v:5452$1024_Y + end + attribute \src "build/ls180/gateware/ls180.v:5453.42-5453.86" + cell $and $and$build/ls180/gateware/ls180.v:5453$1026 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_shared_ack + connect \B $eq$build/ls180/gateware/ls180.v:5453$1025_Y + connect \Y $and$build/ls180/gateware/ls180.v:5453$1026_Y + end + attribute \src "build/ls180/gateware/ls180.v:5454.63-5454.107" + cell $and $and$build/ls180/gateware/ls180.v:5454$1028 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_shared_err + connect \B $eq$build/ls180/gateware/ls180.v:5454$1027_Y + connect \Y $and$build/ls180/gateware/ls180.v:5454$1028_Y + end + attribute \src "build/ls180/gateware/ls180.v:5455.63-5455.107" + cell $and $and$build/ls180/gateware/ls180.v:5455$1030 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_shared_err + connect \B $eq$build/ls180/gateware/ls180.v:5455$1029_Y + connect \Y $and$build/ls180/gateware/ls180.v:5455$1030_Y + end + attribute \src "build/ls180/gateware/ls180.v:5456.42-5456.86" + cell $and $and$build/ls180/gateware/ls180.v:5456$1032 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_shared_err + connect \B $eq$build/ls180/gateware/ls180.v:5456$1031_Y + connect \Y $and$build/ls180/gateware/ls180.v:5456$1032_Y + end + attribute \src "build/ls180/gateware/ls180.v:5457.42-5457.86" + cell $and $and$build/ls180/gateware/ls180.v:5457$1034 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_shared_err + connect \B $eq$build/ls180/gateware/ls180.v:5457$1033_Y + connect \Y $and$build/ls180/gateware/ls180.v:5457$1034_Y + end + attribute \src "build/ls180/gateware/ls180.v:5502.40-5502.81" + cell $and $and$build/ls180/gateware/ls180.v:5502$1041 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_shared_cyc + connect \B \builder_slave_sel [0] + connect \Y $and$build/ls180/gateware/ls180.v:5502$1041_Y + end + attribute \src "build/ls180/gateware/ls180.v:5503.50-5503.91" + cell $and $and$build/ls180/gateware/ls180.v:5503$1042 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_shared_cyc + connect \B \builder_slave_sel [1] + connect \Y $and$build/ls180/gateware/ls180.v:5503$1042_Y + end + attribute \src "build/ls180/gateware/ls180.v:5504.50-5504.91" + cell $and $and$build/ls180/gateware/ls180.v:5504$1043 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_shared_cyc + connect \B \builder_slave_sel [2] + connect \Y $and$build/ls180/gateware/ls180.v:5504$1043_Y + end + attribute \src "build/ls180/gateware/ls180.v:5505.29-5505.70" + cell $and $and$build/ls180/gateware/ls180.v:5505$1044 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_shared_cyc + connect \B \builder_slave_sel [3] + connect \Y $and$build/ls180/gateware/ls180.v:5505$1044_Y + end + attribute \src "build/ls180/gateware/ls180.v:5506.44-5506.85" + cell $and $and$build/ls180/gateware/ls180.v:5506$1045 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_shared_cyc + connect \B \builder_slave_sel [4] + connect \Y $and$build/ls180/gateware/ls180.v:5506$1045_Y + end + attribute \src "build/ls180/gateware/ls180.v:5508.25-5508.64" + cell $and $and$build/ls180/gateware/ls180.v:5508$1050 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_shared_stb + connect \B \builder_shared_cyc + connect \Y $and$build/ls180/gateware/ls180.v:5508$1050_Y + end + attribute \src "build/ls180/gateware/ls180.v:5508.24-5508.89" + cell $and $and$build/ls180/gateware/ls180.v:5508$1052 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$build/ls180/gateware/ls180.v:5508$1050_Y + connect \B $not$build/ls180/gateware/ls180.v:5508$1051_Y + connect \Y $and$build/ls180/gateware/ls180.v:5508$1052_Y + end + attribute \src "build/ls180/gateware/ls180.v:5514.31-5514.92" + cell $and $and$build/ls180/gateware/ls180.v:5514$1058 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 32 + parameter \Y_WIDTH 32 + connect \A { \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] \builder_slave_sel_r [0] } + connect \B \main_libresocsim_ram_bus_dat_r + connect \Y $and$build/ls180/gateware/ls180.v:5514$1058_Y + end + attribute \src "build/ls180/gateware/ls180.v:5514.97-5514.168" + cell $and $and$build/ls180/gateware/ls180.v:5514$1059 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 32 + parameter \Y_WIDTH 32 + connect \A { \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] \builder_slave_sel_r [1] } + connect \B \main_libresocsim_libresoc_xics_icp_dat_r + connect \Y $and$build/ls180/gateware/ls180.v:5514$1059_Y + end + attribute \src "build/ls180/gateware/ls180.v:5514.174-5514.245" + cell $and $and$build/ls180/gateware/ls180.v:5514$1061 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 32 + parameter \Y_WIDTH 32 + connect \A { \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] \builder_slave_sel_r [2] } + connect \B \main_libresocsim_libresoc_xics_ics_dat_r + connect \Y $and$build/ls180/gateware/ls180.v:5514$1061_Y + end + attribute \src "build/ls180/gateware/ls180.v:5514.251-5514.301" + cell $and $and$build/ls180/gateware/ls180.v:5514$1063 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 32 + parameter \Y_WIDTH 32 + connect \A { \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] \builder_slave_sel_r [3] } + connect \B \main_wb_sdram_dat_r + connect \Y $and$build/ls180/gateware/ls180.v:5514$1063_Y + end + attribute \src "build/ls180/gateware/ls180.v:5514.307-5514.372" + cell $and $and$build/ls180/gateware/ls180.v:5514$1065 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 32 + parameter \Y_WIDTH 32 + connect \A { \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] \builder_slave_sel_r [4] } + connect \B \builder_libresocsim_wishbone_dat_r + connect \Y $and$build/ls180/gateware/ls180.v:5514$1065_Y + end + attribute \src "build/ls180/gateware/ls180.v:5524.39-5524.92" + cell $and $and$build/ls180/gateware/ls180.v:5524$1069 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank0_sel + connect \B \builder_interface0_bank_bus_we + connect \Y $and$build/ls180/gateware/ls180.v:5524$1069_Y + end + attribute \src "build/ls180/gateware/ls180.v:5524.38-5524.142" + cell $and $and$build/ls180/gateware/ls180.v:5524$1071 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$build/ls180/gateware/ls180.v:5524$1069_Y + connect \B $eq$build/ls180/gateware/ls180.v:5524$1070_Y + connect \Y $and$build/ls180/gateware/ls180.v:5524$1071_Y + end + attribute \src "build/ls180/gateware/ls180.v:5525.39-5525.95" + cell $and $and$build/ls180/gateware/ls180.v:5525$1073 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank0_sel + connect \B $not$build/ls180/gateware/ls180.v:5525$1072_Y + connect \Y $and$build/ls180/gateware/ls180.v:5525$1073_Y + end + attribute \src "build/ls180/gateware/ls180.v:5525.38-5525.145" + cell $and $and$build/ls180/gateware/ls180.v:5525$1075 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$build/ls180/gateware/ls180.v:5525$1073_Y + connect \B $eq$build/ls180/gateware/ls180.v:5525$1074_Y + connect \Y $and$build/ls180/gateware/ls180.v:5525$1075_Y + end + attribute \src "build/ls180/gateware/ls180.v:5527.41-5527.94" + cell $and $and$build/ls180/gateware/ls180.v:5527$1076 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank0_sel + connect \B \builder_interface0_bank_bus_we + connect \Y $and$build/ls180/gateware/ls180.v:5527$1076_Y + end + attribute \src "build/ls180/gateware/ls180.v:5527.40-5527.144" + cell $and $and$build/ls180/gateware/ls180.v:5527$1078 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$build/ls180/gateware/ls180.v:5527$1076_Y + connect \B $eq$build/ls180/gateware/ls180.v:5527$1077_Y + connect \Y $and$build/ls180/gateware/ls180.v:5527$1078_Y + end + attribute \src "build/ls180/gateware/ls180.v:5528.41-5528.97" + cell $and $and$build/ls180/gateware/ls180.v:5528$1080 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank0_sel + connect \B $not$build/ls180/gateware/ls180.v:5528$1079_Y + connect \Y $and$build/ls180/gateware/ls180.v:5528$1080_Y + end + attribute \src "build/ls180/gateware/ls180.v:5528.40-5528.147" + cell $and $and$build/ls180/gateware/ls180.v:5528$1082 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$build/ls180/gateware/ls180.v:5528$1080_Y + connect \B $eq$build/ls180/gateware/ls180.v:5528$1081_Y + connect \Y $and$build/ls180/gateware/ls180.v:5528$1082_Y + end + attribute \src "build/ls180/gateware/ls180.v:5530.41-5530.94" + cell $and $and$build/ls180/gateware/ls180.v:5530$1083 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank0_sel + connect \B \builder_interface0_bank_bus_we + connect \Y $and$build/ls180/gateware/ls180.v:5530$1083_Y + end + attribute \src "build/ls180/gateware/ls180.v:5530.40-5530.144" + cell $and $and$build/ls180/gateware/ls180.v:5530$1085 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$build/ls180/gateware/ls180.v:5530$1083_Y + connect \B $eq$build/ls180/gateware/ls180.v:5530$1084_Y + connect \Y $and$build/ls180/gateware/ls180.v:5530$1085_Y + end + attribute \src "build/ls180/gateware/ls180.v:5531.41-5531.97" + cell $and $and$build/ls180/gateware/ls180.v:5531$1087 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank0_sel + connect \B $not$build/ls180/gateware/ls180.v:5531$1086_Y + connect \Y $and$build/ls180/gateware/ls180.v:5531$1087_Y + end + attribute \src "build/ls180/gateware/ls180.v:5531.40-5531.147" + cell $and $and$build/ls180/gateware/ls180.v:5531$1089 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$build/ls180/gateware/ls180.v:5531$1087_Y + connect \B $eq$build/ls180/gateware/ls180.v:5531$1088_Y + connect \Y $and$build/ls180/gateware/ls180.v:5531$1089_Y + end + attribute \src "build/ls180/gateware/ls180.v:5533.41-5533.94" + cell $and $and$build/ls180/gateware/ls180.v:5533$1090 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank0_sel + connect \B \builder_interface0_bank_bus_we + connect \Y $and$build/ls180/gateware/ls180.v:5533$1090_Y + end + attribute \src "build/ls180/gateware/ls180.v:5533.40-5533.144" + cell $and $and$build/ls180/gateware/ls180.v:5533$1092 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$build/ls180/gateware/ls180.v:5533$1090_Y + connect \B $eq$build/ls180/gateware/ls180.v:5533$1091_Y + connect \Y $and$build/ls180/gateware/ls180.v:5533$1092_Y + end + attribute \src "build/ls180/gateware/ls180.v:5534.41-5534.97" + cell $and $and$build/ls180/gateware/ls180.v:5534$1094 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank0_sel + connect \B $not$build/ls180/gateware/ls180.v:5534$1093_Y + connect \Y $and$build/ls180/gateware/ls180.v:5534$1094_Y + end + attribute \src "build/ls180/gateware/ls180.v:5534.40-5534.147" + cell $and $and$build/ls180/gateware/ls180.v:5534$1096 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$build/ls180/gateware/ls180.v:5534$1094_Y + connect \B $eq$build/ls180/gateware/ls180.v:5534$1095_Y + connect \Y $and$build/ls180/gateware/ls180.v:5534$1096_Y + end + attribute \src "build/ls180/gateware/ls180.v:5536.41-5536.94" + cell $and $and$build/ls180/gateware/ls180.v:5536$1097 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank0_sel + connect \B \builder_interface0_bank_bus_we + connect \Y $and$build/ls180/gateware/ls180.v:5536$1097_Y + end + attribute \src "build/ls180/gateware/ls180.v:5536.40-5536.144" + cell $and $and$build/ls180/gateware/ls180.v:5536$1099 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$build/ls180/gateware/ls180.v:5536$1097_Y + connect \B $eq$build/ls180/gateware/ls180.v:5536$1098_Y + connect \Y $and$build/ls180/gateware/ls180.v:5536$1099_Y + end + attribute \src "build/ls180/gateware/ls180.v:5537.41-5537.97" + cell $and $and$build/ls180/gateware/ls180.v:5537$1101 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank0_sel + connect \B $not$build/ls180/gateware/ls180.v:5537$1100_Y + connect \Y $and$build/ls180/gateware/ls180.v:5537$1101_Y + end + attribute \src "build/ls180/gateware/ls180.v:5537.40-5537.147" + cell $and $and$build/ls180/gateware/ls180.v:5537$1103 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$build/ls180/gateware/ls180.v:5537$1101_Y + connect \B $eq$build/ls180/gateware/ls180.v:5537$1102_Y + connect \Y $and$build/ls180/gateware/ls180.v:5537$1103_Y + end + attribute \src "build/ls180/gateware/ls180.v:5539.44-5539.97" + cell $and $and$build/ls180/gateware/ls180.v:5539$1104 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank0_sel + connect \B \builder_interface0_bank_bus_we + connect \Y $and$build/ls180/gateware/ls180.v:5539$1104_Y + end + attribute \src "build/ls180/gateware/ls180.v:5539.43-5539.147" + cell $and $and$build/ls180/gateware/ls180.v:5539$1106 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$build/ls180/gateware/ls180.v:5539$1104_Y + connect \B $eq$build/ls180/gateware/ls180.v:5539$1105_Y + connect \Y $and$build/ls180/gateware/ls180.v:5539$1106_Y + end + attribute \src "build/ls180/gateware/ls180.v:5540.44-5540.100" + cell $and $and$build/ls180/gateware/ls180.v:5540$1108 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank0_sel + connect \B $not$build/ls180/gateware/ls180.v:5540$1107_Y + connect \Y $and$build/ls180/gateware/ls180.v:5540$1108_Y + end + attribute \src "build/ls180/gateware/ls180.v:5540.43-5540.150" + cell $and $and$build/ls180/gateware/ls180.v:5540$1110 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$build/ls180/gateware/ls180.v:5540$1108_Y + connect \B $eq$build/ls180/gateware/ls180.v:5540$1109_Y + connect \Y $and$build/ls180/gateware/ls180.v:5540$1110_Y + end + attribute \src "build/ls180/gateware/ls180.v:5542.44-5542.97" + cell $and $and$build/ls180/gateware/ls180.v:5542$1111 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank0_sel + connect \B \builder_interface0_bank_bus_we + connect \Y $and$build/ls180/gateware/ls180.v:5542$1111_Y + end + attribute \src "build/ls180/gateware/ls180.v:5542.43-5542.147" + cell $and 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\src "build/ls180/gateware/ls180.v:6071.40-6071.95" + cell $and $and$build/ls180/gateware/ls180.v:6071$1964 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank11_sel + connect \B \builder_interface11_bank_bus_we + connect \Y $and$build/ls180/gateware/ls180.v:6071$1964_Y + end + attribute \src "build/ls180/gateware/ls180.v:6071.39-6071.146" + cell $and $and$build/ls180/gateware/ls180.v:6071$1966 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$build/ls180/gateware/ls180.v:6071$1964_Y + connect \B $eq$build/ls180/gateware/ls180.v:6071$1965_Y + connect \Y $and$build/ls180/gateware/ls180.v:6071$1966_Y + end + attribute \src "build/ls180/gateware/ls180.v:6072.40-6072.98" + cell $and $and$build/ls180/gateware/ls180.v:6072$1968 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank11_sel + connect \B $not$build/ls180/gateware/ls180.v:6072$1967_Y + connect \Y $and$build/ls180/gateware/ls180.v:6072$1968_Y + end + attribute \src "build/ls180/gateware/ls180.v:6072.39-6072.149" + cell $and $and$build/ls180/gateware/ls180.v:6072$1970 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$build/ls180/gateware/ls180.v:6072$1968_Y + connect \B $eq$build/ls180/gateware/ls180.v:6072$1969_Y + connect \Y $and$build/ls180/gateware/ls180.v:6072$1970_Y + end + attribute \src "build/ls180/gateware/ls180.v:6074.41-6074.96" + cell $and $and$build/ls180/gateware/ls180.v:6074$1971 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank11_sel + connect \B \builder_interface11_bank_bus_we + connect \Y $and$build/ls180/gateware/ls180.v:6074$1971_Y + end + attribute \src "build/ls180/gateware/ls180.v:6074.40-6074.147" + cell $and $and$build/ls180/gateware/ls180.v:6074$1973 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$build/ls180/gateware/ls180.v:6074$1971_Y + connect \B $eq$build/ls180/gateware/ls180.v:6074$1972_Y + connect \Y $and$build/ls180/gateware/ls180.v:6074$1973_Y + end + attribute \src "build/ls180/gateware/ls180.v:6075.41-6075.99" + cell $and $and$build/ls180/gateware/ls180.v:6075$1975 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank11_sel + connect \B $not$build/ls180/gateware/ls180.v:6075$1974_Y + connect \Y $and$build/ls180/gateware/ls180.v:6075$1975_Y + end + attribute \src "build/ls180/gateware/ls180.v:6075.40-6075.150" + cell $and $and$build/ls180/gateware/ls180.v:6075$1977 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$build/ls180/gateware/ls180.v:6075$1975_Y + connect \B $eq$build/ls180/gateware/ls180.v:6075$1976_Y + connect \Y $and$build/ls180/gateware/ls180.v:6075$1977_Y + end + attribute \src "build/ls180/gateware/ls180.v:6077.57-6077.112" + cell $and $and$build/ls180/gateware/ls180.v:6077$1978 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank11_sel + connect \B \builder_interface11_bank_bus_we + connect \Y $and$build/ls180/gateware/ls180.v:6077$1978_Y + end + attribute \src "build/ls180/gateware/ls180.v:6077.56-6077.163" + cell $and $and$build/ls180/gateware/ls180.v:6077$1980 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$build/ls180/gateware/ls180.v:6077$1978_Y + connect \B $eq$build/ls180/gateware/ls180.v:6077$1979_Y + connect \Y $and$build/ls180/gateware/ls180.v:6077$1980_Y + end + attribute \src "build/ls180/gateware/ls180.v:6078.57-6078.115" + cell $and $and$build/ls180/gateware/ls180.v:6078$1982 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank11_sel + connect \B $not$build/ls180/gateware/ls180.v:6078$1981_Y + connect \Y $and$build/ls180/gateware/ls180.v:6078$1982_Y + end + attribute \src "build/ls180/gateware/ls180.v:6078.56-6078.166" + cell $and $and$build/ls180/gateware/ls180.v:6078$1984 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$build/ls180/gateware/ls180.v:6078$1982_Y + connect \B $eq$build/ls180/gateware/ls180.v:6078$1983_Y + connect \Y $and$build/ls180/gateware/ls180.v:6078$1984_Y + end + attribute \src "build/ls180/gateware/ls180.v:6080.58-6080.113" + cell $and $and$build/ls180/gateware/ls180.v:6080$1985 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank11_sel + connect \B \builder_interface11_bank_bus_we + connect \Y $and$build/ls180/gateware/ls180.v:6080$1985_Y + end + attribute \src "build/ls180/gateware/ls180.v:6080.57-6080.164" + cell $and $and$build/ls180/gateware/ls180.v:6080$1987 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$build/ls180/gateware/ls180.v:6080$1985_Y + connect \B $eq$build/ls180/gateware/ls180.v:6080$1986_Y + connect \Y $and$build/ls180/gateware/ls180.v:6080$1987_Y + end + attribute \src "build/ls180/gateware/ls180.v:6081.58-6081.116" + cell $and $and$build/ls180/gateware/ls180.v:6081$1989 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank11_sel + connect \B $not$build/ls180/gateware/ls180.v:6081$1988_Y + connect \Y $and$build/ls180/gateware/ls180.v:6081$1989_Y + end + attribute \src "build/ls180/gateware/ls180.v:6081.57-6081.167" + cell $and $and$build/ls180/gateware/ls180.v:6081$1991 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$build/ls180/gateware/ls180.v:6081$1989_Y + connect \B $eq$build/ls180/gateware/ls180.v:6081$1990_Y + connect \Y $and$build/ls180/gateware/ls180.v:6081$1991_Y + end + attribute \src "build/ls180/gateware/ls180.v:6083.44-6083.99" + cell $and $and$build/ls180/gateware/ls180.v:6083$1992 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank11_sel + connect \B \builder_interface11_bank_bus_we + connect \Y $and$build/ls180/gateware/ls180.v:6083$1992_Y + end + attribute \src "build/ls180/gateware/ls180.v:6083.43-6083.150" + cell $and $and$build/ls180/gateware/ls180.v:6083$1994 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$build/ls180/gateware/ls180.v:6083$1992_Y + connect \B $eq$build/ls180/gateware/ls180.v:6083$1993_Y + connect \Y $and$build/ls180/gateware/ls180.v:6083$1994_Y + end + attribute \src "build/ls180/gateware/ls180.v:6084.44-6084.102" + cell $and $and$build/ls180/gateware/ls180.v:6084$1996 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank11_sel + connect \B $not$build/ls180/gateware/ls180.v:6084$1995_Y + connect \Y $and$build/ls180/gateware/ls180.v:6084$1996_Y + end + attribute \src "build/ls180/gateware/ls180.v:6084.43-6084.153" + cell $and $and$build/ls180/gateware/ls180.v:6084$1998 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$build/ls180/gateware/ls180.v:6084$1996_Y + connect \B $eq$build/ls180/gateware/ls180.v:6084$1997_Y + connect \Y $and$build/ls180/gateware/ls180.v:6084$1998_Y + end + attribute \src "build/ls180/gateware/ls180.v:6086.41-6086.96" + cell $and $and$build/ls180/gateware/ls180.v:6086$1999 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank11_sel + connect \B \builder_interface11_bank_bus_we + connect \Y $and$build/ls180/gateware/ls180.v:6086$1999_Y + end + attribute \src "build/ls180/gateware/ls180.v:6086.40-6086.147" + cell $and $and$build/ls180/gateware/ls180.v:6086$2001 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$build/ls180/gateware/ls180.v:6086$1999_Y + connect \B $eq$build/ls180/gateware/ls180.v:6086$2000_Y + connect \Y $and$build/ls180/gateware/ls180.v:6086$2001_Y + end + attribute \src "build/ls180/gateware/ls180.v:6087.41-6087.99" + cell $and $and$build/ls180/gateware/ls180.v:6087$2003 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank11_sel + connect \B $not$build/ls180/gateware/ls180.v:6087$2002_Y + connect \Y $and$build/ls180/gateware/ls180.v:6087$2003_Y + end + attribute \src "build/ls180/gateware/ls180.v:6087.40-6087.150" + cell $and $and$build/ls180/gateware/ls180.v:6087$2005 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$build/ls180/gateware/ls180.v:6087$2003_Y + connect \B $eq$build/ls180/gateware/ls180.v:6087$2004_Y + connect \Y $and$build/ls180/gateware/ls180.v:6087$2005_Y + end + attribute \src "build/ls180/gateware/ls180.v:6089.40-6089.95" + cell $and $and$build/ls180/gateware/ls180.v:6089$2006 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank11_sel + connect \B \builder_interface11_bank_bus_we + connect \Y $and$build/ls180/gateware/ls180.v:6089$2006_Y + end + attribute \src "build/ls180/gateware/ls180.v:6089.39-6089.146" + cell $and $and$build/ls180/gateware/ls180.v:6089$2008 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$build/ls180/gateware/ls180.v:6089$2006_Y + connect \B $eq$build/ls180/gateware/ls180.v:6089$2007_Y + connect \Y $and$build/ls180/gateware/ls180.v:6089$2008_Y + end + attribute \src "build/ls180/gateware/ls180.v:6090.40-6090.98" + cell $and $and$build/ls180/gateware/ls180.v:6090$2010 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank11_sel + connect \B $not$build/ls180/gateware/ls180.v:6090$2009_Y + connect \Y $and$build/ls180/gateware/ls180.v:6090$2010_Y + end + attribute \src "build/ls180/gateware/ls180.v:6090.39-6090.149" + cell $and $and$build/ls180/gateware/ls180.v:6090$2012 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$build/ls180/gateware/ls180.v:6090$2010_Y + connect \B $eq$build/ls180/gateware/ls180.v:6090$2011_Y + connect \Y $and$build/ls180/gateware/ls180.v:6090$2012_Y + end + attribute \src "build/ls180/gateware/ls180.v:6102.46-6102.101" + cell $and $and$build/ls180/gateware/ls180.v:6102$2014 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank12_sel + connect \B \builder_interface12_bank_bus_we + connect \Y $and$build/ls180/gateware/ls180.v:6102$2014_Y + end + attribute \src "build/ls180/gateware/ls180.v:6102.45-6102.152" + cell $and $and$build/ls180/gateware/ls180.v:6102$2016 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$build/ls180/gateware/ls180.v:6102$2014_Y + connect \B $eq$build/ls180/gateware/ls180.v:6102$2015_Y + connect \Y $and$build/ls180/gateware/ls180.v:6102$2016_Y + end + attribute \src "build/ls180/gateware/ls180.v:6103.46-6103.104" + cell $and $and$build/ls180/gateware/ls180.v:6103$2018 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank12_sel + connect \B $not$build/ls180/gateware/ls180.v:6103$2017_Y + connect \Y $and$build/ls180/gateware/ls180.v:6103$2018_Y + end + attribute \src "build/ls180/gateware/ls180.v:6103.45-6103.155" + cell $and $and$build/ls180/gateware/ls180.v:6103$2020 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$build/ls180/gateware/ls180.v:6103$2018_Y + connect \B $eq$build/ls180/gateware/ls180.v:6103$2019_Y + connect \Y $and$build/ls180/gateware/ls180.v:6103$2020_Y + end + attribute \src "build/ls180/gateware/ls180.v:6105.46-6105.101" + cell $and $and$build/ls180/gateware/ls180.v:6105$2021 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank12_sel + connect \B \builder_interface12_bank_bus_we + connect \Y $and$build/ls180/gateware/ls180.v:6105$2021_Y + end + attribute \src "build/ls180/gateware/ls180.v:6105.45-6105.152" + cell $and $and$build/ls180/gateware/ls180.v:6105$2023 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$build/ls180/gateware/ls180.v:6105$2021_Y + connect \B $eq$build/ls180/gateware/ls180.v:6105$2022_Y + connect \Y $and$build/ls180/gateware/ls180.v:6105$2023_Y + end + attribute \src "build/ls180/gateware/ls180.v:6106.46-6106.104" + cell $and $and$build/ls180/gateware/ls180.v:6106$2025 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank12_sel + connect \B $not$build/ls180/gateware/ls180.v:6106$2024_Y + connect \Y $and$build/ls180/gateware/ls180.v:6106$2025_Y + end + attribute \src "build/ls180/gateware/ls180.v:6106.45-6106.155" + cell $and $and$build/ls180/gateware/ls180.v:6106$2027 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$build/ls180/gateware/ls180.v:6106$2025_Y + connect \B $eq$build/ls180/gateware/ls180.v:6106$2026_Y + connect \Y $and$build/ls180/gateware/ls180.v:6106$2027_Y + end + attribute \src "build/ls180/gateware/ls180.v:6108.46-6108.101" + cell $and $and$build/ls180/gateware/ls180.v:6108$2028 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank12_sel + connect \B \builder_interface12_bank_bus_we + connect \Y $and$build/ls180/gateware/ls180.v:6108$2028_Y + end + attribute \src "build/ls180/gateware/ls180.v:6108.45-6108.152" + cell $and $and$build/ls180/gateware/ls180.v:6108$2030 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$build/ls180/gateware/ls180.v:6108$2028_Y + connect \B $eq$build/ls180/gateware/ls180.v:6108$2029_Y + connect \Y $and$build/ls180/gateware/ls180.v:6108$2030_Y + end + attribute \src "build/ls180/gateware/ls180.v:6109.46-6109.104" + cell $and $and$build/ls180/gateware/ls180.v:6109$2032 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_csrbank12_sel + connect \B $not$build/ls180/gateware/ls180.v:6109$2031_Y + connect \Y $and$build/ls180/gateware/ls180.v:6109$2032_Y + end + attribute \src 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$and$build/ls180/gateware/ls180.v:6112$2041_Y + end + attribute \src "build/ls180/gateware/ls180.v:6487.109-6487.178" + cell $and $and$build/ls180/gateware/ls180.v:6487$2077 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_interface_bank1_lock + connect \B $eq$build/ls180/gateware/ls180.v:6487$2076_Y + connect \Y $and$build/ls180/gateware/ls180.v:6487$2077_Y + end + attribute \src "build/ls180/gateware/ls180.v:6487.184-6487.253" + cell $and $and$build/ls180/gateware/ls180.v:6487$2080 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_interface_bank2_lock + connect \B $eq$build/ls180/gateware/ls180.v:6487$2079_Y + connect \Y $and$build/ls180/gateware/ls180.v:6487$2080_Y + end + attribute \src "build/ls180/gateware/ls180.v:6487.259-6487.328" + cell $and $and$build/ls180/gateware/ls180.v:6487$2083 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_interface_bank3_lock + connect \B $eq$build/ls180/gateware/ls180.v:6487$2082_Y + connect \Y $and$build/ls180/gateware/ls180.v:6487$2083_Y + end + attribute \src "build/ls180/gateware/ls180.v:6487.40-6487.331" + cell $and $and$build/ls180/gateware/ls180.v:6487$2086 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $eq$build/ls180/gateware/ls180.v:6487$2075_Y + connect \B $not$build/ls180/gateware/ls180.v:6487$2085_Y + connect \Y $and$build/ls180/gateware/ls180.v:6487$2086_Y + end + attribute \src "build/ls180/gateware/ls180.v:6487.39-6487.354" + cell $and $and$build/ls180/gateware/ls180.v:6487$2087 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$build/ls180/gateware/ls180.v:6487$2086_Y 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$and$build/ls180/gateware/ls180.v:6559$2128_Y + end + attribute \src "build/ls180/gateware/ls180.v:6559.259-6559.328" + cell $and $and$build/ls180/gateware/ls180.v:6559$2131 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_interface_bank2_lock + connect \B $eq$build/ls180/gateware/ls180.v:6559$2130_Y + connect \Y $and$build/ls180/gateware/ls180.v:6559$2131_Y + end + attribute \src "build/ls180/gateware/ls180.v:6559.40-6559.331" + cell $and $and$build/ls180/gateware/ls180.v:6559$2134 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $eq$build/ls180/gateware/ls180.v:6559$2123_Y + connect \B $not$build/ls180/gateware/ls180.v:6559$2133_Y + connect \Y $and$build/ls180/gateware/ls180.v:6559$2134_Y + end + attribute \src "build/ls180/gateware/ls180.v:6559.39-6559.354" + cell $and $and$build/ls180/gateware/ls180.v:6559$2135 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+ end + attribute \src "build/ls180/gateware/ls180.v:6814.38-6814.117" + cell $and $and$build/ls180/gateware/ls180.v:6814$2180 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$build/ls180/gateware/ls180.v:6814$2179_Y + connect \B \main_sdram_cmd_payload_is_write + connect \Y $and$build/ls180/gateware/ls180.v:6814$2180_Y + end + attribute \src "build/ls180/gateware/ls180.v:7005.17-7005.69" + cell $and $and$build/ls180/gateware/ls180.v:7005$2186 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $not$build/ls180/gateware/ls180.v:7005$2185_Y + connect \B \libresocsim_sdpads_clk + connect \Y $and$build/ls180/gateware/ls180.v:7005$2186_Y + end + attribute \src "build/ls180/gateware/ls180.v:7084.8-7084.67" + cell $and $and$build/ls180/gateware/ls180.v:7084$2192 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_libresocsim_ram_bus_cyc + connect \B \main_libresocsim_ram_bus_stb + connect \Y $and$build/ls180/gateware/ls180.v:7084$2192_Y + end + attribute \src "build/ls180/gateware/ls180.v:7084.7-7084.102" + cell $and $and$build/ls180/gateware/ls180.v:7084$2194 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$build/ls180/gateware/ls180.v:7084$2192_Y + connect \B $not$build/ls180/gateware/ls180.v:7084$2193_Y + connect \Y $and$build/ls180/gateware/ls180.v:7084$2194_Y + end + attribute \src "build/ls180/gateware/ls180.v:7088.8-7088.65" + cell $and $and$build/ls180/gateware/ls180.v:7088$2196 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_libresocsim_sink_valid + connect \B $not$build/ls180/gateware/ls180.v:7088$2195_Y + connect \Y $and$build/ls180/gateware/ls180.v:7088$2196_Y + end + attribute \src "build/ls180/gateware/ls180.v:7088.7-7088.99" + cell $and $and$build/ls180/gateware/ls180.v:7088$2198 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$build/ls180/gateware/ls180.v:7088$2196_Y + connect \B $not$build/ls180/gateware/ls180.v:7088$2197_Y + connect \Y $and$build/ls180/gateware/ls180.v:7088$2198_Y + end + attribute \src "build/ls180/gateware/ls180.v:7094.8-7094.65" + cell $and $and$build/ls180/gateware/ls180.v:7094$2199 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_libresocsim_uart_clk_txen + connect \B \main_libresocsim_tx_busy + connect \Y $and$build/ls180/gateware/ls180.v:7094$2199_Y + end + attribute \src "build/ls180/gateware/ls180.v:7118.8-7118.54" + cell $and $and$build/ls180/gateware/ls180.v:7118$2206 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $not$build/ls180/gateware/ls180.v:7118$2205_Y + connect \B \main_libresocsim_rx_r + connect \Y $and$build/ls180/gateware/ls180.v:7118$2206_Y + end + attribute \src "build/ls180/gateware/ls180.v:7151.7-7151.81" + cell $and $and$build/ls180/gateware/ls180.v:7151$2212 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $not$build/ls180/gateware/ls180.v:7151$2211_Y + connect \B \main_libresocsim_uart_tx_old_trigger + connect \Y $and$build/ls180/gateware/ls180.v:7151$2212_Y + end + attribute \src "build/ls180/gateware/ls180.v:7158.7-7158.81" + cell $and $and$build/ls180/gateware/ls180.v:7158$2214 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $not$build/ls180/gateware/ls180.v:7158$2213_Y + connect \B \main_libresocsim_uart_rx_old_trigger + connect \Y $and$build/ls180/gateware/ls180.v:7158$2214_Y + end + attribute \src "build/ls180/gateware/ls180.v:7168.8-7168.99" + cell $and $and$build/ls180/gateware/ls180.v:7168$2215 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_libresocsim_uart_tx_fifo_syncfifo_we + connect \B \main_libresocsim_uart_tx_fifo_syncfifo_writable + connect \Y $and$build/ls180/gateware/ls180.v:7168$2215_Y + end + attribute \src "build/ls180/gateware/ls180.v:7168.7-7168.143" + cell $and $and$build/ls180/gateware/ls180.v:7168$2217 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$build/ls180/gateware/ls180.v:7168$2215_Y + connect \B $not$build/ls180/gateware/ls180.v:7168$2216_Y + connect \Y $and$build/ls180/gateware/ls180.v:7168$2217_Y + end + attribute \src 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\B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_libresocsim_uart_rx_fifo_syncfifo_we + connect \B \main_libresocsim_uart_rx_fifo_syncfifo_writable + connect \Y $and$build/ls180/gateware/ls180.v:7190$2226_Y + end + attribute \src "build/ls180/gateware/ls180.v:7190.7-7190.143" + cell $and $and$build/ls180/gateware/ls180.v:7190$2228 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$build/ls180/gateware/ls180.v:7190$2226_Y + connect \B $not$build/ls180/gateware/ls180.v:7190$2227_Y + connect \Y $and$build/ls180/gateware/ls180.v:7190$2228_Y + end + attribute \src "build/ls180/gateware/ls180.v:7196.8-7196.99" + cell $and $and$build/ls180/gateware/ls180.v:7196$2231 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_libresocsim_uart_rx_fifo_syncfifo_we + connect \B \main_libresocsim_uart_rx_fifo_syncfifo_writable + connect \Y $and$build/ls180/gateware/ls180.v:7196$2231_Y + end + attribute \src "build/ls180/gateware/ls180.v:7196.7-7196.143" + cell $and $and$build/ls180/gateware/ls180.v:7196$2233 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$build/ls180/gateware/ls180.v:7196$2231_Y + connect \B $not$build/ls180/gateware/ls180.v:7196$2232_Y + connect \Y $and$build/ls180/gateware/ls180.v:7196$2233_Y + end + attribute \src "build/ls180/gateware/ls180.v:7235.7-7235.87" + cell $and $and$build/ls180/gateware/ls180.v:7235$2240 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $not$build/ls180/gateware/ls180.v:7235$2239_Y + connect \B \main_libresocsim_timer_zero_old_trigger + connect \Y $and$build/ls180/gateware/ls180.v:7235$2240_Y + end + attribute \src "build/ls180/gateware/ls180.v:7243.7-7243.56" + cell $and $and$build/ls180/gateware/ls180.v:7243$2242 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_timer_wait + connect \B $not$build/ls180/gateware/ls180.v:7243$2241_Y + connect \Y $and$build/ls180/gateware/ls180.v:7243$2242_Y + end + attribute \src "build/ls180/gateware/ls180.v:7271.7-7271.75" + cell $and $and$build/ls180/gateware/ls180.v:7271$2249 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_sequencer_start1 + connect \B $eq$build/ls180/gateware/ls180.v:7271$2248_Y + connect \Y $and$build/ls180/gateware/ls180.v:7271$2249_Y + end + attribute \src "build/ls180/gateware/ls180.v:7313.8-7313.131" + cell $and $and$build/ls180/gateware/ls180.v:7313$2255 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_we + connect \B \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable + connect \Y $and$build/ls180/gateware/ls180.v:7313$2255_Y + end + attribute \src "build/ls180/gateware/ls180.v:7313.7-7313.190" + cell $and $and$build/ls180/gateware/ls180.v:7313$2257 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$build/ls180/gateware/ls180.v:7313$2255_Y + connect \B $not$build/ls180/gateware/ls180.v:7313$2256_Y + connect \Y $and$build/ls180/gateware/ls180.v:7313$2257_Y + end + attribute \src "build/ls180/gateware/ls180.v:7319.8-7319.131" + cell $and $and$build/ls180/gateware/ls180.v:7319$2260 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_we + connect \B \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable + connect \Y $and$build/ls180/gateware/ls180.v:7319$2260_Y + end + attribute \src "build/ls180/gateware/ls180.v:7319.7-7319.190" + cell $and $and$build/ls180/gateware/ls180.v:7319$2262 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$build/ls180/gateware/ls180.v:7319$2260_Y + connect \B $not$build/ls180/gateware/ls180.v:7319$2261_Y + connect \Y $and$build/ls180/gateware/ls180.v:7319$2262_Y + end + attribute \src "build/ls180/gateware/ls180.v:7359.8-7359.131" + cell $and $and$build/ls180/gateware/ls180.v:7359$2271 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_we + connect \B \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable + connect \Y $and$build/ls180/gateware/ls180.v:7359$2271_Y + end + attribute \src "build/ls180/gateware/ls180.v:7359.7-7359.190" + cell $and $and$build/ls180/gateware/ls180.v:7359$2273 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$build/ls180/gateware/ls180.v:7359$2271_Y + connect \B $not$build/ls180/gateware/ls180.v:7359$2272_Y + connect \Y $and$build/ls180/gateware/ls180.v:7359$2273_Y + end + attribute \src "build/ls180/gateware/ls180.v:7365.8-7365.131" + cell $and $and$build/ls180/gateware/ls180.v:7365$2276 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_we + connect \B \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable + connect \Y $and$build/ls180/gateware/ls180.v:7365$2276_Y + end + attribute \src "build/ls180/gateware/ls180.v:7365.7-7365.190" + cell $and $and$build/ls180/gateware/ls180.v:7365$2278 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$build/ls180/gateware/ls180.v:7365$2276_Y + connect \B $not$build/ls180/gateware/ls180.v:7365$2277_Y + connect \Y $and$build/ls180/gateware/ls180.v:7365$2278_Y + end + attribute \src "build/ls180/gateware/ls180.v:7405.8-7405.131" + cell $and $and$build/ls180/gateware/ls180.v:7405$2287 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_we + connect \B \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable + connect \Y $and$build/ls180/gateware/ls180.v:7405$2287_Y + end + attribute \src "build/ls180/gateware/ls180.v:7405.7-7405.190" + cell $and $and$build/ls180/gateware/ls180.v:7405$2289 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$build/ls180/gateware/ls180.v:7405$2287_Y + connect \B $not$build/ls180/gateware/ls180.v:7405$2288_Y + connect \Y $and$build/ls180/gateware/ls180.v:7405$2289_Y + end + attribute \src "build/ls180/gateware/ls180.v:7411.8-7411.131" + cell $and $and$build/ls180/gateware/ls180.v:7411$2292 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_we + connect \B \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable + connect \Y $and$build/ls180/gateware/ls180.v:7411$2292_Y + end + attribute \src "build/ls180/gateware/ls180.v:7411.7-7411.190" + cell $and $and$build/ls180/gateware/ls180.v:7411$2294 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$build/ls180/gateware/ls180.v:7411$2292_Y + connect \B $not$build/ls180/gateware/ls180.v:7411$2293_Y + connect \Y $and$build/ls180/gateware/ls180.v:7411$2294_Y + end + attribute \src "build/ls180/gateware/ls180.v:7451.8-7451.131" + cell $and $and$build/ls180/gateware/ls180.v:7451$2303 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_we + connect \B \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable + connect \Y $and$build/ls180/gateware/ls180.v:7451$2303_Y + end + attribute \src "build/ls180/gateware/ls180.v:7451.7-7451.190" + cell $and $and$build/ls180/gateware/ls180.v:7451$2305 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$build/ls180/gateware/ls180.v:7451$2303_Y + connect \B $not$build/ls180/gateware/ls180.v:7451$2304_Y + connect \Y $and$build/ls180/gateware/ls180.v:7451$2305_Y + end + attribute \src "build/ls180/gateware/ls180.v:7457.8-7457.131" + cell $and $and$build/ls180/gateware/ls180.v:7457$2308 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_we + connect \B \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable + connect \Y $and$build/ls180/gateware/ls180.v:7457$2308_Y + end + attribute \src "build/ls180/gateware/ls180.v:7457.7-7457.190" + cell $and $and$build/ls180/gateware/ls180.v:7457$2310 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$build/ls180/gateware/ls180.v:7457$2308_Y + connect \B $not$build/ls180/gateware/ls180.v:7457$2309_Y + connect \Y $and$build/ls180/gateware/ls180.v:7457$2310_Y + end + attribute \src "build/ls180/gateware/ls180.v:7654.48-7654.124" + cell $and $and$build/ls180/gateware/ls180.v:7654$2335 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $eq$build/ls180/gateware/ls180.v:7654$2334_Y + connect \B \main_sdram_interface_bank0_wdata_ready + connect \Y $and$build/ls180/gateware/ls180.v:7654$2335_Y + end + attribute \src "build/ls180/gateware/ls180.v:7654.130-7654.206" + cell $and $and$build/ls180/gateware/ls180.v:7654$2338 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $eq$build/ls180/gateware/ls180.v:7654$2337_Y + connect \B \main_sdram_interface_bank1_wdata_ready + connect \Y $and$build/ls180/gateware/ls180.v:7654$2338_Y + end + attribute \src "build/ls180/gateware/ls180.v:7654.212-7654.288" + cell $and $and$build/ls180/gateware/ls180.v:7654$2341 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $eq$build/ls180/gateware/ls180.v:7654$2340_Y + connect \B \main_sdram_interface_bank2_wdata_ready + connect \Y $and$build/ls180/gateware/ls180.v:7654$2341_Y + end + attribute \src "build/ls180/gateware/ls180.v:7654.294-7654.370" + cell $and $and$build/ls180/gateware/ls180.v:7654$2344 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $eq$build/ls180/gateware/ls180.v:7654$2343_Y + connect \B \main_sdram_interface_bank3_wdata_ready + connect \Y $and$build/ls180/gateware/ls180.v:7654$2344_Y + end + attribute \src "build/ls180/gateware/ls180.v:7655.49-7655.125" + cell $and $and$build/ls180/gateware/ls180.v:7655$2347 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $eq$build/ls180/gateware/ls180.v:7655$2346_Y + connect \B \main_sdram_interface_bank0_rdata_valid + connect \Y $and$build/ls180/gateware/ls180.v:7655$2347_Y + end + attribute \src "build/ls180/gateware/ls180.v:7655.131-7655.207" + cell $and $and$build/ls180/gateware/ls180.v:7655$2350 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $eq$build/ls180/gateware/ls180.v:7655$2349_Y + connect \B \main_sdram_interface_bank1_rdata_valid + connect \Y $and$build/ls180/gateware/ls180.v:7655$2350_Y + end + attribute \src "build/ls180/gateware/ls180.v:7655.213-7655.289" + cell $and $and$build/ls180/gateware/ls180.v:7655$2353 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $eq$build/ls180/gateware/ls180.v:7655$2352_Y + connect \B \main_sdram_interface_bank2_rdata_valid + connect \Y $and$build/ls180/gateware/ls180.v:7655$2353_Y + end + attribute \src "build/ls180/gateware/ls180.v:7655.295-7655.371" + cell $and $and$build/ls180/gateware/ls180.v:7655$2356 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $eq$build/ls180/gateware/ls180.v:7655$2355_Y + connect \B \main_sdram_interface_bank3_rdata_valid + connect \Y $and$build/ls180/gateware/ls180.v:7655$2356_Y + end + attribute \src "build/ls180/gateware/ls180.v:7674.8-7674.49" + cell $and $and$build/ls180/gateware/ls180.v:7674$2359 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_port_cmd_valid + connect \B \main_port_cmd_ready + connect \Y $and$build/ls180/gateware/ls180.v:7674$2359_Y + end + attribute \src "build/ls180/gateware/ls180.v:7677.8-7677.53" + cell $and $and$build/ls180/gateware/ls180.v:7677$2360 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_port_wdata_valid + connect \B \main_port_wdata_ready + connect \Y $and$build/ls180/gateware/ls180.v:7677$2360_Y + end + attribute \src "build/ls180/gateware/ls180.v:7743.7-7743.98" + cell $and $and$build/ls180/gateware/ls180.v:7743$2372 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \libresocsim_cmdr_cmdr_converter_source_valid + connect \B \libresocsim_cmdr_cmdr_converter_source_ready + connect \Y $and$build/ls180/gateware/ls180.v:7743$2372_Y + end + attribute \src "build/ls180/gateware/ls180.v:7744.8-7744.95" + cell $and $and$build/ls180/gateware/ls180.v:7744$2373 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \libresocsim_cmdr_cmdr_converter_sink_valid + connect \B \libresocsim_cmdr_cmdr_converter_sink_ready + connect \Y $and$build/ls180/gateware/ls180.v:7744$2373_Y + end + attribute \src "build/ls180/gateware/ls180.v:7752.8-7752.95" + cell $and $and$build/ls180/gateware/ls180.v:7752$2374 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \libresocsim_cmdr_cmdr_converter_sink_valid + connect \B \libresocsim_cmdr_cmdr_converter_sink_ready + connect \Y $and$build/ls180/gateware/ls180.v:7752$2374_Y + end + attribute \src "build/ls180/gateware/ls180.v:7824.7-7824.100" + cell $and $and$build/ls180/gateware/ls180.v:7824$2384 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \libresocsim_dataw_crcr_converter_source_valid + connect \B \libresocsim_dataw_crcr_converter_source_ready + connect \Y $and$build/ls180/gateware/ls180.v:7824$2384_Y + end + attribute \src "build/ls180/gateware/ls180.v:7825.8-7825.97" + cell $and $and$build/ls180/gateware/ls180.v:7825$2385 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \libresocsim_dataw_crcr_converter_sink_valid + connect \B \libresocsim_dataw_crcr_converter_sink_ready + connect \Y $and$build/ls180/gateware/ls180.v:7825$2385_Y + end + attribute \src "build/ls180/gateware/ls180.v:7833.8-7833.97" + cell $and $and$build/ls180/gateware/ls180.v:7833$2386 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \libresocsim_dataw_crcr_converter_sink_valid + connect \B \libresocsim_dataw_crcr_converter_sink_ready + connect \Y $and$build/ls180/gateware/ls180.v:7833$2386_Y + end + attribute \src "build/ls180/gateware/ls180.v:7903.7-7903.102" + cell $and $and$build/ls180/gateware/ls180.v:7903$2396 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \libresocsim_datar_datar_converter_source_valid + connect \B \libresocsim_datar_datar_converter_source_ready + connect \Y $and$build/ls180/gateware/ls180.v:7903$2396_Y + end + attribute \src "build/ls180/gateware/ls180.v:7904.8-7904.99" + cell $and $and$build/ls180/gateware/ls180.v:7904$2397 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \libresocsim_datar_datar_converter_sink_valid + connect \B \libresocsim_datar_datar_converter_sink_ready + connect \Y $and$build/ls180/gateware/ls180.v:7904$2397_Y + end + attribute \src "build/ls180/gateware/ls180.v:7912.8-7912.99" + cell $and $and$build/ls180/gateware/ls180.v:7912$2398 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \libresocsim_datar_datar_converter_sink_valid + connect \B \libresocsim_datar_datar_converter_sink_ready + connect \Y $and$build/ls180/gateware/ls180.v:7912$2398_Y + end + attribute \src "build/ls180/gateware/ls180.v:8003.7-8003.96" + cell $and $and$build/ls180/gateware/ls180.v:8003$2404 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \libresocsim_sdcore_crc16_checker_sink_ready + connect \B \libresocsim_sdcore_crc16_checker_sink_valid + connect \Y $and$build/ls180/gateware/ls180.v:8003$2404_Y + end + attribute \src "build/ls180/gateware/ls180.v:8006.7-8006.96" + cell $and $and$build/ls180/gateware/ls180.v:8006$2405 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \libresocsim_sdcore_crc16_checker_sink_ready + connect \B \libresocsim_sdcore_crc16_checker_sink_valid + connect \Y $and$build/ls180/gateware/ls180.v:8006$2405_Y + end + attribute \src "build/ls180/gateware/ls180.v:8009.7-8009.96" + cell $and $and$build/ls180/gateware/ls180.v:8009$2406 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \libresocsim_sdcore_crc16_checker_sink_ready + connect \B \libresocsim_sdcore_crc16_checker_sink_valid + connect \Y $and$build/ls180/gateware/ls180.v:8009$2406_Y + end + attribute \src "build/ls180/gateware/ls180.v:8012.7-8012.96" + cell $and $and$build/ls180/gateware/ls180.v:8012$2407 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \libresocsim_sdcore_crc16_checker_sink_ready + connect \B \libresocsim_sdcore_crc16_checker_sink_valid + connect \Y $and$build/ls180/gateware/ls180.v:8012$2407_Y + end + attribute \src "build/ls180/gateware/ls180.v:8015.7-8015.96" + cell $and $and$build/ls180/gateware/ls180.v:8015$2408 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \libresocsim_sdcore_crc16_checker_sink_valid + connect \B \libresocsim_sdcore_crc16_checker_sink_ready + connect \Y $and$build/ls180/gateware/ls180.v:8015$2408_Y + end + attribute \src "build/ls180/gateware/ls180.v:8020.7-8020.96" + cell $and $and$build/ls180/gateware/ls180.v:8020$2409 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \libresocsim_sdcore_crc16_checker_sink_valid + connect \B \libresocsim_sdcore_crc16_checker_sink_ready + connect \Y $and$build/ls180/gateware/ls180.v:8020$2409_Y + end + attribute \src "build/ls180/gateware/ls180.v:8025.7-8025.96" + cell $and $and$build/ls180/gateware/ls180.v:8025$2410 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \libresocsim_sdcore_crc16_checker_sink_valid + connect \B \libresocsim_sdcore_crc16_checker_sink_ready + connect \Y $and$build/ls180/gateware/ls180.v:8025$2410_Y + end + attribute \src "build/ls180/gateware/ls180.v:8030.7-8030.96" + cell $and $and$build/ls180/gateware/ls180.v:8030$2411 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \libresocsim_sdcore_crc16_checker_sink_valid + connect \B \libresocsim_sdcore_crc16_checker_sink_ready + connect \Y $and$build/ls180/gateware/ls180.v:8030$2411_Y + end + attribute \src "build/ls180/gateware/ls180.v:8035.7-8035.96" + cell $and $and$build/ls180/gateware/ls180.v:8035$2412 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \libresocsim_sdcore_crc16_checker_sink_valid + connect \B \libresocsim_sdcore_crc16_checker_sink_ready + connect \Y $and$build/ls180/gateware/ls180.v:8035$2412_Y + end + attribute \src "build/ls180/gateware/ls180.v:8100.8-8100.97" + cell $and $and$build/ls180/gateware/ls180.v:8100$2415 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \libresocsim_sdblock2mem_fifo_syncfifo_we + connect \B \libresocsim_sdblock2mem_fifo_syncfifo_writable + connect \Y $and$build/ls180/gateware/ls180.v:8100$2415_Y + end + attribute \src "build/ls180/gateware/ls180.v:8100.7-8100.140" + cell $and $and$build/ls180/gateware/ls180.v:8100$2417 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$build/ls180/gateware/ls180.v:8100$2415_Y + connect \B $not$build/ls180/gateware/ls180.v:8100$2416_Y + connect \Y $and$build/ls180/gateware/ls180.v:8100$2417_Y + end + attribute \src "build/ls180/gateware/ls180.v:8106.8-8106.97" + cell $and $and$build/ls180/gateware/ls180.v:8106$2420 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \libresocsim_sdblock2mem_fifo_syncfifo_we + connect \B \libresocsim_sdblock2mem_fifo_syncfifo_writable + connect \Y $and$build/ls180/gateware/ls180.v:8106$2420_Y + end + attribute \src "build/ls180/gateware/ls180.v:8106.7-8106.140" + cell $and $and$build/ls180/gateware/ls180.v:8106$2422 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$build/ls180/gateware/ls180.v:8106$2420_Y + connect \B $not$build/ls180/gateware/ls180.v:8106$2421_Y + connect \Y $and$build/ls180/gateware/ls180.v:8106$2422_Y + end + attribute \src "build/ls180/gateware/ls180.v:8126.7-8126.102" + cell $and $and$build/ls180/gateware/ls180.v:8126$2429 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \libresocsim_sdblock2mem_converter_source_valid + connect \B \libresocsim_sdblock2mem_converter_source_ready + connect \Y $and$build/ls180/gateware/ls180.v:8126$2429_Y + end + attribute \src "build/ls180/gateware/ls180.v:8127.8-8127.99" + cell $and $and$build/ls180/gateware/ls180.v:8127$2430 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \libresocsim_sdblock2mem_converter_sink_valid + connect \B \libresocsim_sdblock2mem_converter_sink_ready + connect \Y $and$build/ls180/gateware/ls180.v:8127$2430_Y + end + attribute \src "build/ls180/gateware/ls180.v:8135.8-8135.99" + cell $and $and$build/ls180/gateware/ls180.v:8135$2431 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \libresocsim_sdblock2mem_converter_sink_valid + connect \B \libresocsim_sdblock2mem_converter_sink_ready + connect \Y $and$build/ls180/gateware/ls180.v:8135$2431_Y + end + attribute \src "build/ls180/gateware/ls180.v:8179.7-8179.102" + cell $and $and$build/ls180/gateware/ls180.v:8179$2435 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \libresocsim_sdmem2block_converter_source_valid + connect \B \libresocsim_sdmem2block_converter_source_ready + connect \Y $and$build/ls180/gateware/ls180.v:8179$2435_Y + end + attribute \src "build/ls180/gateware/ls180.v:8186.8-8186.97" + cell $and $and$build/ls180/gateware/ls180.v:8186$2437 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \libresocsim_sdmem2block_fifo_syncfifo_we + connect \B \libresocsim_sdmem2block_fifo_syncfifo_writable + connect \Y $and$build/ls180/gateware/ls180.v:8186$2437_Y + end + attribute \src "build/ls180/gateware/ls180.v:8186.7-8186.140" + cell $and $and$build/ls180/gateware/ls180.v:8186$2439 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$build/ls180/gateware/ls180.v:8186$2437_Y + connect \B $not$build/ls180/gateware/ls180.v:8186$2438_Y + connect \Y $and$build/ls180/gateware/ls180.v:8186$2439_Y + end + attribute \src "build/ls180/gateware/ls180.v:8192.8-8192.97" + cell $and $and$build/ls180/gateware/ls180.v:8192$2442 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \libresocsim_sdmem2block_fifo_syncfifo_we + connect \B \libresocsim_sdmem2block_fifo_syncfifo_writable + connect \Y $and$build/ls180/gateware/ls180.v:8192$2442_Y + end + attribute \src "build/ls180/gateware/ls180.v:8192.7-8192.140" + cell $and $and$build/ls180/gateware/ls180.v:8192$2444 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$build/ls180/gateware/ls180.v:8192$2442_Y + connect \B $not$build/ls180/gateware/ls180.v:8192$2443_Y + connect \Y $and$build/ls180/gateware/ls180.v:8192$2444_Y + end + attribute \src "build/ls180/gateware/ls180.v:2630.42-2630.101" + cell $eq $eq$build/ls180/gateware/ls180.v:2630$18 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_libresocsim_interface0_converted_interface_sel + connect \B 1'0 + connect \Y $eq$build/ls180/gateware/ls180.v:2630$18_Y + end + attribute \src "build/ls180/gateware/ls180.v:2637.11-2637.54" + cell $eq $eq$build/ls180/gateware/ls180.v:2637$23 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_libresocsim_converter0_counter + connect \B 1'1 + connect \Y $eq$build/ls180/gateware/ls180.v:2637$23_Y + end + attribute \src "build/ls180/gateware/ls180.v:2690.42-2690.101" + cell $eq $eq$build/ls180/gateware/ls180.v:2690$29 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_libresocsim_interface1_converted_interface_sel + connect \B 1'0 + connect \Y $eq$build/ls180/gateware/ls180.v:2690$29_Y + end + attribute \src "build/ls180/gateware/ls180.v:2697.11-2697.54" + cell $eq $eq$build/ls180/gateware/ls180.v:2697$34 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_libresocsim_converter1_counter + connect \B 1'1 + connect \Y $eq$build/ls180/gateware/ls180.v:2697$34_Y + end + attribute \src "build/ls180/gateware/ls180.v:3003.34-3003.65" + cell $eq $eq$build/ls180/gateware/ls180.v:3003$102 + parameter \A_SIGNED 0 + parameter \A_WIDTH 10 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_timer_count1 + connect \B 1'0 + connect \Y $eq$build/ls180/gateware/ls180.v:3003$102_Y + end + attribute \src "build/ls180/gateware/ls180.v:3007.68-3007.102" + cell $eq $eq$build/ls180/gateware/ls180.v:3007$105 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_sequencer_count + connect \B 1'0 + connect \Y $eq$build/ls180/gateware/ls180.v:3007$105_Y + end + attribute \src "build/ls180/gateware/ls180.v:3051.43-3051.134" + cell $eq $eq$build/ls180/gateware/ls180.v:3051$110 + parameter \A_SIGNED 0 + parameter \A_WIDTH 13 + parameter \B_SIGNED 0 + parameter \B_WIDTH 13 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine0_row + connect \B \main_sdram_bankmachine0_cmd_buffer_source_payload_addr [21:9] + connect \Y $eq$build/ls180/gateware/ls180.v:3051$110_Y + end + attribute \src "build/ls180/gateware/ls180.v:3068.47-3068.88" + cell $eq $eq$build/ls180/gateware/ls180.v:3068$123 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine0_row_close + connect \B 1'0 + connect \Y $eq$build/ls180/gateware/ls180.v:3068$123_Y + end + attribute \src "build/ls180/gateware/ls180.v:3208.43-3208.134" + cell $eq $eq$build/ls180/gateware/ls180.v:3208$140 + parameter \A_SIGNED 0 + parameter \A_WIDTH 13 + parameter \B_SIGNED 0 + parameter \B_WIDTH 13 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine1_row + connect \B \main_sdram_bankmachine1_cmd_buffer_source_payload_addr [21:9] + connect \Y $eq$build/ls180/gateware/ls180.v:3208$140_Y + end + attribute \src "build/ls180/gateware/ls180.v:3225.47-3225.88" + cell $eq $eq$build/ls180/gateware/ls180.v:3225$153 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine1_row_close + connect \B 1'0 + connect \Y $eq$build/ls180/gateware/ls180.v:3225$153_Y + end + attribute \src "build/ls180/gateware/ls180.v:3365.43-3365.134" + cell $eq $eq$build/ls180/gateware/ls180.v:3365$170 + parameter \A_SIGNED 0 + parameter \A_WIDTH 13 + parameter \B_SIGNED 0 + parameter \B_WIDTH 13 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine2_row + connect \B \main_sdram_bankmachine2_cmd_buffer_source_payload_addr [21:9] + connect \Y $eq$build/ls180/gateware/ls180.v:3365$170_Y + end + attribute \src "build/ls180/gateware/ls180.v:3382.47-3382.88" + cell $eq $eq$build/ls180/gateware/ls180.v:3382$183 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine2_row_close + connect \B 1'0 + connect \Y $eq$build/ls180/gateware/ls180.v:3382$183_Y + end + attribute \src "build/ls180/gateware/ls180.v:3522.43-3522.134" + cell $eq $eq$build/ls180/gateware/ls180.v:3522$200 + parameter \A_SIGNED 0 + parameter \A_WIDTH 13 + parameter \B_SIGNED 0 + parameter \B_WIDTH 13 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine3_row + connect \B \main_sdram_bankmachine3_cmd_buffer_source_payload_addr [21:9] + connect \Y $eq$build/ls180/gateware/ls180.v:3522$200_Y + end + attribute \src "build/ls180/gateware/ls180.v:3539.47-3539.88" + cell $eq $eq$build/ls180/gateware/ls180.v:3539$213 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine3_row_close + connect \B 1'0 + connect \Y $eq$build/ls180/gateware/ls180.v:3539$213_Y + end + attribute \src "build/ls180/gateware/ls180.v:3676.32-3676.56" + cell $eq $eq$build/ls180/gateware/ls180.v:3676$260 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_time0 + connect \B 1'0 + connect \Y $eq$build/ls180/gateware/ls180.v:3676$260_Y + end + attribute \src "build/ls180/gateware/ls180.v:3677.32-3677.56" + cell $eq $eq$build/ls180/gateware/ls180.v:3677$261 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_time1 + connect \B 1'0 + connect \Y $eq$build/ls180/gateware/ls180.v:3677$261_Y + end + attribute \src "build/ls180/gateware/ls180.v:3688.339-3688.418" + cell $eq $eq$build/ls180/gateware/ls180.v:3688$275 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine0_cmd_payload_is_read + connect \B \main_sdram_choose_cmd_want_reads + connect \Y $eq$build/ls180/gateware/ls180.v:3688$275_Y + end + attribute \src "build/ls180/gateware/ls180.v:3688.423-3688.504" + cell $eq $eq$build/ls180/gateware/ls180.v:3688$276 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine0_cmd_payload_is_write + connect \B \main_sdram_choose_cmd_want_writes + connect \Y $eq$build/ls180/gateware/ls180.v:3688$276_Y + end + attribute \src "build/ls180/gateware/ls180.v:3689.339-3689.418" + cell $eq $eq$build/ls180/gateware/ls180.v:3689$288 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine1_cmd_payload_is_read + connect \B \main_sdram_choose_cmd_want_reads + connect \Y $eq$build/ls180/gateware/ls180.v:3689$288_Y + end + attribute \src "build/ls180/gateware/ls180.v:3689.423-3689.504" + cell $eq $eq$build/ls180/gateware/ls180.v:3689$289 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine1_cmd_payload_is_write + connect \B \main_sdram_choose_cmd_want_writes + connect \Y $eq$build/ls180/gateware/ls180.v:3689$289_Y + end + attribute \src "build/ls180/gateware/ls180.v:3690.339-3690.418" + cell $eq $eq$build/ls180/gateware/ls180.v:3690$301 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine2_cmd_payload_is_read + connect \B \main_sdram_choose_cmd_want_reads + connect \Y $eq$build/ls180/gateware/ls180.v:3690$301_Y + end + attribute \src "build/ls180/gateware/ls180.v:3690.423-3690.504" + cell $eq $eq$build/ls180/gateware/ls180.v:3690$302 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine2_cmd_payload_is_write + connect \B \main_sdram_choose_cmd_want_writes + connect \Y $eq$build/ls180/gateware/ls180.v:3690$302_Y + end + attribute \src "build/ls180/gateware/ls180.v:3691.339-3691.418" + cell $eq $eq$build/ls180/gateware/ls180.v:3691$314 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine3_cmd_payload_is_read + connect \B \main_sdram_choose_cmd_want_reads + connect \Y $eq$build/ls180/gateware/ls180.v:3691$314_Y + end + attribute \src "build/ls180/gateware/ls180.v:3691.423-3691.504" + cell $eq $eq$build/ls180/gateware/ls180.v:3691$315 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine3_cmd_payload_is_write + connect \B \main_sdram_choose_cmd_want_writes + connect \Y $eq$build/ls180/gateware/ls180.v:3691$315_Y + end + attribute \src "build/ls180/gateware/ls180.v:3721.339-3721.418" + cell $eq $eq$build/ls180/gateware/ls180.v:3721$333 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine0_cmd_payload_is_read + connect \B \main_sdram_choose_req_want_reads + connect \Y $eq$build/ls180/gateware/ls180.v:3721$333_Y + end + attribute \src "build/ls180/gateware/ls180.v:3721.423-3721.504" + cell $eq $eq$build/ls180/gateware/ls180.v:3721$334 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine0_cmd_payload_is_write + connect \B \main_sdram_choose_req_want_writes + connect \Y $eq$build/ls180/gateware/ls180.v:3721$334_Y + end + attribute \src "build/ls180/gateware/ls180.v:3722.339-3722.418" + cell $eq $eq$build/ls180/gateware/ls180.v:3722$346 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine1_cmd_payload_is_read + connect \B \main_sdram_choose_req_want_reads + connect \Y $eq$build/ls180/gateware/ls180.v:3722$346_Y + end + attribute \src "build/ls180/gateware/ls180.v:3722.423-3722.504" + cell $eq $eq$build/ls180/gateware/ls180.v:3722$347 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine1_cmd_payload_is_write + connect \B \main_sdram_choose_req_want_writes + connect \Y $eq$build/ls180/gateware/ls180.v:3722$347_Y + end + attribute \src "build/ls180/gateware/ls180.v:3723.339-3723.418" + cell $eq $eq$build/ls180/gateware/ls180.v:3723$359 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine2_cmd_payload_is_read + connect \B \main_sdram_choose_req_want_reads + connect \Y $eq$build/ls180/gateware/ls180.v:3723$359_Y + end + attribute \src "build/ls180/gateware/ls180.v:3723.423-3723.504" + cell $eq $eq$build/ls180/gateware/ls180.v:3723$360 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine2_cmd_payload_is_write + connect \B \main_sdram_choose_req_want_writes + connect \Y $eq$build/ls180/gateware/ls180.v:3723$360_Y + end + attribute \src "build/ls180/gateware/ls180.v:3724.339-3724.418" + cell $eq $eq$build/ls180/gateware/ls180.v:3724$372 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine3_cmd_payload_is_read + connect \B \main_sdram_choose_req_want_reads + connect \Y $eq$build/ls180/gateware/ls180.v:3724$372_Y + end + attribute \src "build/ls180/gateware/ls180.v:3724.423-3724.504" + cell $eq $eq$build/ls180/gateware/ls180.v:3724$373 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine3_cmd_payload_is_write + connect \B \main_sdram_choose_req_want_writes + connect \Y $eq$build/ls180/gateware/ls180.v:3724$373_Y + end + attribute \src "build/ls180/gateware/ls180.v:3753.78-3753.113" + cell $eq $eq$build/ls180/gateware/ls180.v:3753$382 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_cmd_grant + connect \B 1'0 + connect \Y $eq$build/ls180/gateware/ls180.v:3753$382_Y + end + attribute \src "build/ls180/gateware/ls180.v:3756.78-3756.113" + cell $eq $eq$build/ls180/gateware/ls180.v:3756$385 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_req_grant + connect \B 1'0 + connect \Y $eq$build/ls180/gateware/ls180.v:3756$385_Y + end + attribute \src "build/ls180/gateware/ls180.v:3762.78-3762.113" + cell $eq $eq$build/ls180/gateware/ls180.v:3762$389 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_cmd_grant + connect \B 1'1 + connect \Y $eq$build/ls180/gateware/ls180.v:3762$389_Y + end + attribute \src "build/ls180/gateware/ls180.v:3765.78-3765.113" + cell $eq $eq$build/ls180/gateware/ls180.v:3765$392 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_req_grant + connect \B 1'1 + connect \Y $eq$build/ls180/gateware/ls180.v:3765$392_Y + end + attribute \src "build/ls180/gateware/ls180.v:3771.78-3771.113" + cell $eq $eq$build/ls180/gateware/ls180.v:3771$396 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_cmd_grant + connect \B 2'10 + connect \Y $eq$build/ls180/gateware/ls180.v:3771$396_Y + end + attribute \src "build/ls180/gateware/ls180.v:3774.78-3774.113" + cell $eq $eq$build/ls180/gateware/ls180.v:3774$399 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_req_grant + connect \B 2'10 + connect \Y $eq$build/ls180/gateware/ls180.v:3774$399_Y + end + attribute \src "build/ls180/gateware/ls180.v:3780.78-3780.113" + cell $eq $eq$build/ls180/gateware/ls180.v:3780$403 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_cmd_grant + connect \B 2'11 + connect \Y $eq$build/ls180/gateware/ls180.v:3780$403_Y + end + attribute \src "build/ls180/gateware/ls180.v:3783.78-3783.113" + cell $eq $eq$build/ls180/gateware/ls180.v:3783$406 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_req_grant + connect \B 2'11 + connect \Y $eq$build/ls180/gateware/ls180.v:3783$406_Y + end + attribute \src "build/ls180/gateware/ls180.v:3864.42-3864.82" + cell $eq $eq$build/ls180/gateware/ls180.v:3864$429 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_port_cmd_payload_addr [10:9] + connect \B 1'0 + connect \Y $eq$build/ls180/gateware/ls180.v:3864$429_Y + end + attribute \src "build/ls180/gateware/ls180.v:3864.145-3864.178" + cell $eq $eq$build/ls180/gateware/ls180.v:3864$430 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin1_grant + connect \B 1'0 + connect \Y $eq$build/ls180/gateware/ls180.v:3864$430_Y + end + attribute \src "build/ls180/gateware/ls180.v:3864.220-3864.253" + cell $eq $eq$build/ls180/gateware/ls180.v:3864$433 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin2_grant + connect \B 1'0 + connect \Y $eq$build/ls180/gateware/ls180.v:3864$433_Y + end + attribute \src "build/ls180/gateware/ls180.v:3864.295-3864.328" + cell $eq $eq$build/ls180/gateware/ls180.v:3864$436 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin3_grant + connect \B 1'0 + connect \Y $eq$build/ls180/gateware/ls180.v:3864$436_Y + end + attribute \src "build/ls180/gateware/ls180.v:3869.42-3869.82" + cell $eq $eq$build/ls180/gateware/ls180.v:3869$445 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_port_cmd_payload_addr [10:9] + connect \B 1'1 + connect \Y $eq$build/ls180/gateware/ls180.v:3869$445_Y + end + attribute \src "build/ls180/gateware/ls180.v:3869.145-3869.178" + cell $eq $eq$build/ls180/gateware/ls180.v:3869$446 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin0_grant + connect \B 1'0 + connect \Y $eq$build/ls180/gateware/ls180.v:3869$446_Y + end + attribute \src "build/ls180/gateware/ls180.v:3869.220-3869.253" + cell $eq $eq$build/ls180/gateware/ls180.v:3869$449 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin2_grant + connect \B 1'0 + connect \Y $eq$build/ls180/gateware/ls180.v:3869$449_Y + end + attribute \src "build/ls180/gateware/ls180.v:3869.295-3869.328" + cell $eq $eq$build/ls180/gateware/ls180.v:3869$452 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin3_grant + connect \B 1'0 + connect \Y $eq$build/ls180/gateware/ls180.v:3869$452_Y + end + attribute \src "build/ls180/gateware/ls180.v:3874.42-3874.82" + cell $eq $eq$build/ls180/gateware/ls180.v:3874$461 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \main_port_cmd_payload_addr [10:9] + connect \B 2'10 + connect \Y $eq$build/ls180/gateware/ls180.v:3874$461_Y + end + attribute \src "build/ls180/gateware/ls180.v:3874.145-3874.178" + cell $eq $eq$build/ls180/gateware/ls180.v:3874$462 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin0_grant + connect \B 1'0 + connect \Y $eq$build/ls180/gateware/ls180.v:3874$462_Y + end + attribute \src "build/ls180/gateware/ls180.v:3874.220-3874.253" + cell $eq $eq$build/ls180/gateware/ls180.v:3874$465 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin1_grant + connect \B 1'0 + connect \Y $eq$build/ls180/gateware/ls180.v:3874$465_Y + end + attribute \src "build/ls180/gateware/ls180.v:3874.295-3874.328" + cell $eq $eq$build/ls180/gateware/ls180.v:3874$468 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin3_grant + connect \B 1'0 + connect \Y $eq$build/ls180/gateware/ls180.v:3874$468_Y + end + attribute \src "build/ls180/gateware/ls180.v:3879.42-3879.82" + cell $eq $eq$build/ls180/gateware/ls180.v:3879$477 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \main_port_cmd_payload_addr [10:9] + connect \B 2'11 + connect \Y $eq$build/ls180/gateware/ls180.v:3879$477_Y + end + attribute \src "build/ls180/gateware/ls180.v:3879.145-3879.178" + cell $eq $eq$build/ls180/gateware/ls180.v:3879$478 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin0_grant + connect \B 1'0 + connect \Y $eq$build/ls180/gateware/ls180.v:3879$478_Y + end + attribute \src "build/ls180/gateware/ls180.v:3879.220-3879.253" + cell $eq $eq$build/ls180/gateware/ls180.v:3879$481 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin1_grant + connect \B 1'0 + connect \Y $eq$build/ls180/gateware/ls180.v:3879$481_Y + end + attribute \src "build/ls180/gateware/ls180.v:3879.295-3879.328" + cell $eq $eq$build/ls180/gateware/ls180.v:3879$484 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin2_grant + connect \B 1'0 + connect \Y $eq$build/ls180/gateware/ls180.v:3879$484_Y + end + attribute \src "build/ls180/gateware/ls180.v:3884.44-3884.77" + cell $eq $eq$build/ls180/gateware/ls180.v:3884$493 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin0_grant + connect \B 1'0 + connect \Y $eq$build/ls180/gateware/ls180.v:3884$493_Y + end + attribute \src "build/ls180/gateware/ls180.v:3884.83-3884.123" + cell $eq $eq$build/ls180/gateware/ls180.v:3884$494 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_port_cmd_payload_addr [10:9] + connect \B 1'0 + connect \Y $eq$build/ls180/gateware/ls180.v:3884$494_Y + end + attribute \src "build/ls180/gateware/ls180.v:3884.186-3884.219" + cell $eq $eq$build/ls180/gateware/ls180.v:3884$495 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin1_grant + connect \B 1'0 + connect \Y $eq$build/ls180/gateware/ls180.v:3884$495_Y + end + attribute \src "build/ls180/gateware/ls180.v:3884.261-3884.294" + cell $eq $eq$build/ls180/gateware/ls180.v:3884$498 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin2_grant + connect \B 1'0 + connect \Y $eq$build/ls180/gateware/ls180.v:3884$498_Y + end + attribute \src "build/ls180/gateware/ls180.v:3884.336-3884.369" + cell $eq $eq$build/ls180/gateware/ls180.v:3884$501 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin3_grant + connect \B 1'0 + connect \Y $eq$build/ls180/gateware/ls180.v:3884$501_Y + end + attribute \src "build/ls180/gateware/ls180.v:3884.418-3884.451" + cell $eq $eq$build/ls180/gateware/ls180.v:3884$509 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin1_grant + connect \B 1'0 + connect \Y $eq$build/ls180/gateware/ls180.v:3884$509_Y + end + attribute \src "build/ls180/gateware/ls180.v:3884.457-3884.497" + cell $eq $eq$build/ls180/gateware/ls180.v:3884$510 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_port_cmd_payload_addr [10:9] + connect \B 1'1 + connect \Y $eq$build/ls180/gateware/ls180.v:3884$510_Y + end + attribute \src "build/ls180/gateware/ls180.v:3884.560-3884.593" + cell $eq $eq$build/ls180/gateware/ls180.v:3884$511 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin0_grant + connect \B 1'0 + connect \Y $eq$build/ls180/gateware/ls180.v:3884$511_Y + end + attribute \src "build/ls180/gateware/ls180.v:3884.635-3884.668" + cell $eq $eq$build/ls180/gateware/ls180.v:3884$514 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin2_grant + connect \B 1'0 + connect \Y $eq$build/ls180/gateware/ls180.v:3884$514_Y + end + attribute \src "build/ls180/gateware/ls180.v:3884.710-3884.743" + cell $eq $eq$build/ls180/gateware/ls180.v:3884$517 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin3_grant + connect \B 1'0 + connect \Y $eq$build/ls180/gateware/ls180.v:3884$517_Y + end + attribute \src "build/ls180/gateware/ls180.v:3884.792-3884.825" + cell $eq $eq$build/ls180/gateware/ls180.v:3884$525 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin2_grant + connect \B 1'0 + connect \Y $eq$build/ls180/gateware/ls180.v:3884$525_Y + end + attribute \src "build/ls180/gateware/ls180.v:3884.831-3884.871" + cell $eq $eq$build/ls180/gateware/ls180.v:3884$526 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \main_port_cmd_payload_addr [10:9] + connect \B 2'10 + connect \Y $eq$build/ls180/gateware/ls180.v:3884$526_Y + end + attribute \src "build/ls180/gateware/ls180.v:3884.934-3884.967" + cell $eq $eq$build/ls180/gateware/ls180.v:3884$527 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin0_grant + connect \B 1'0 + connect \Y $eq$build/ls180/gateware/ls180.v:3884$527_Y + end + attribute \src "build/ls180/gateware/ls180.v:3884.1009-3884.1042" + cell $eq $eq$build/ls180/gateware/ls180.v:3884$530 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin1_grant + connect \B 1'0 + connect \Y $eq$build/ls180/gateware/ls180.v:3884$530_Y + end + attribute \src "build/ls180/gateware/ls180.v:3884.1084-3884.1117" + cell $eq $eq$build/ls180/gateware/ls180.v:3884$533 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin3_grant + connect \B 1'0 + connect \Y $eq$build/ls180/gateware/ls180.v:3884$533_Y + end + attribute \src "build/ls180/gateware/ls180.v:3884.1166-3884.1199" + cell $eq $eq$build/ls180/gateware/ls180.v:3884$541 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin3_grant + connect \B 1'0 + connect \Y $eq$build/ls180/gateware/ls180.v:3884$541_Y + end + attribute \src "build/ls180/gateware/ls180.v:3884.1205-3884.1245" + cell $eq $eq$build/ls180/gateware/ls180.v:3884$542 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \main_port_cmd_payload_addr [10:9] + connect \B 2'11 + connect \Y $eq$build/ls180/gateware/ls180.v:3884$542_Y + end + attribute \src "build/ls180/gateware/ls180.v:3884.1308-3884.1341" + cell $eq $eq$build/ls180/gateware/ls180.v:3884$543 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin0_grant + connect \B 1'0 + connect \Y $eq$build/ls180/gateware/ls180.v:3884$543_Y + end + attribute \src "build/ls180/gateware/ls180.v:3884.1383-3884.1416" + cell $eq $eq$build/ls180/gateware/ls180.v:3884$546 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin1_grant + connect \B 1'0 + connect \Y $eq$build/ls180/gateware/ls180.v:3884$546_Y + end + attribute \src "build/ls180/gateware/ls180.v:3884.1458-3884.1491" + cell $eq $eq$build/ls180/gateware/ls180.v:3884$549 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin2_grant + connect \B 1'0 + connect \Y $eq$build/ls180/gateware/ls180.v:3884$549_Y + end + attribute \src "build/ls180/gateware/ls180.v:3943.29-3943.57" + cell $eq $eq$build/ls180/gateware/ls180.v:3943$562 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_litedram_wb_sel + connect \B 1'0 + connect \Y $eq$build/ls180/gateware/ls180.v:3943$562_Y + end + attribute \src "build/ls180/gateware/ls180.v:3950.11-3950.41" + cell $eq $eq$build/ls180/gateware/ls180.v:3950$567 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_converter_counter + connect \B 1'1 + connect \Y $eq$build/ls180/gateware/ls180.v:3950$567_Y + end + attribute \src "build/ls180/gateware/ls180.v:3987.25-3987.78" + cell $eq $eq$build/ls180/gateware/ls180.v:3987$593 + parameter \A_SIGNED 0 + parameter \A_WIDTH 16 + parameter \B_SIGNED 0 + parameter \B_WIDTH 16 + parameter \Y_WIDTH 1 + connect \A \main_clk_divider1 + connect \B $sub$build/ls180/gateware/ls180.v:3987$592_Y + connect \Y $eq$build/ls180/gateware/ls180.v:3987$593_Y + end + attribute \src "build/ls180/gateware/ls180.v:3988.25-3988.72" + cell $eq $eq$build/ls180/gateware/ls180.v:3988$595 + parameter \A_SIGNED 0 + parameter \A_WIDTH 16 + parameter \B_SIGNED 0 + parameter \B_WIDTH 16 + parameter \Y_WIDTH 1 + connect \A \main_clk_divider1 + connect \B $sub$build/ls180/gateware/ls180.v:3988$594_Y + connect \Y $eq$build/ls180/gateware/ls180.v:3988$595_Y + end + attribute \src "build/ls180/gateware/ls180.v:4015.10-4015.45" + cell $eq $eq$build/ls180/gateware/ls180.v:4015$599 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \main_count + connect \B $sub$build/ls180/gateware/ls180.v:4015$598_Y + connect \Y $eq$build/ls180/gateware/ls180.v:4015$599_Y + end + attribute \src "build/ls180/gateware/ls180.v:4115.10-4115.41" + cell $eq $eq$build/ls180/gateware/ls180.v:4115$626 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \libresocsim_init_count + connect \B 7'1001111 + connect \Y $eq$build/ls180/gateware/ls180.v:4115$626_Y + end + attribute \src "build/ls180/gateware/ls180.v:4172.10-4172.40" + cell $eq $eq$build/ls180/gateware/ls180.v:4172$629 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \libresocsim_cmdw_count + connect \B 3'111 + connect \Y $eq$build/ls180/gateware/ls180.v:4172$629_Y + end + attribute \src "build/ls180/gateware/ls180.v:4189.10-4189.40" + cell $eq $eq$build/ls180/gateware/ls180.v:4189$631 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \libresocsim_cmdw_count + connect \B 3'111 + connect \Y $eq$build/ls180/gateware/ls180.v:4189$631_Y + end + attribute \src "build/ls180/gateware/ls180.v:4217.39-4217.90" + cell $eq $eq$build/ls180/gateware/ls180.v:4217$633 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \libresocsim_cmdr_cmdr_pads_in_payload_cmd_i + connect \B 1'0 + connect \Y $eq$build/ls180/gateware/ls180.v:4217$633_Y + end + attribute \src "build/ls180/gateware/ls180.v:4267.9-4267.41" + cell $eq $eq$build/ls180/gateware/ls180.v:4267$643 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \libresocsim_cmdr_timeout + connect \B 1'0 + connect \Y $eq$build/ls180/gateware/ls180.v:4267$643_Y + end + attribute \src "build/ls180/gateware/ls180.v:4276.37-4276.108" + cell $eq $eq$build/ls180/gateware/ls180.v:4276$645 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \libresocsim_cmdr_count + connect \B $sub$build/ls180/gateware/ls180.v:4276$644_Y + connect \Y $eq$build/ls180/gateware/ls180.v:4276$645_Y + end + attribute \src "build/ls180/gateware/ls180.v:4295.9-4295.41" + cell $eq $eq$build/ls180/gateware/ls180.v:4295$649 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \libresocsim_cmdr_timeout + connect \B 1'0 + connect \Y $eq$build/ls180/gateware/ls180.v:4295$649_Y + end + attribute \src "build/ls180/gateware/ls180.v:4307.10-4307.40" + cell $eq $eq$build/ls180/gateware/ls180.v:4307$651 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \libresocsim_cmdr_count + connect \B 3'111 + connect \Y $eq$build/ls180/gateware/ls180.v:4307$651_Y + end + attribute \src "build/ls180/gateware/ls180.v:4344.40-4344.96" + cell $eq $eq$build/ls180/gateware/ls180.v:4344$655 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \libresocsim_dataw_crcr_pads_in_payload_data_i [0] + connect \B 1'0 + connect \Y $eq$build/ls180/gateware/ls180.v:4344$655_Y + end + attribute \src "build/ls180/gateware/ls180.v:4381.33-4381.91" + cell $eq $eq$build/ls180/gateware/ls180.v:4381$664 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \libresocsim_dataw_crcr_source_source_payload_data0 + connect \B 3'101 + connect \Y $eq$build/ls180/gateware/ls180.v:4381$664_Y + end + attribute \src "build/ls180/gateware/ls180.v:4429.10-4429.41" + cell $eq $eq$build/ls180/gateware/ls180.v:4429$668 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \libresocsim_dataw_count + connect \B 1'1 + connect \Y $eq$build/ls180/gateware/ls180.v:4429$668_Y + end + attribute \src "build/ls180/gateware/ls180.v:4478.41-4478.100" + cell $eq $eq$build/ls180/gateware/ls180.v:4478$670 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \libresocsim_datar_datar_pads_in_payload_data_i + connect \B 1'0 + connect \Y $eq$build/ls180/gateware/ls180.v:4478$670_Y + end + attribute \src "build/ls180/gateware/ls180.v:4529.9-4529.42" + cell $eq $eq$build/ls180/gateware/ls180.v:4529$680 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \libresocsim_datar_timeout + connect \B 1'0 + connect \Y $eq$build/ls180/gateware/ls180.v:4529$680_Y + end + attribute \src "build/ls180/gateware/ls180.v:4538.38-4538.126" + cell $eq $eq$build/ls180/gateware/ls180.v:4538$683 + parameter \A_SIGNED 0 + parameter \A_WIDTH 10 + parameter \B_SIGNED 0 + parameter \B_WIDTH 10 + parameter \Y_WIDTH 1 + connect \A \libresocsim_datar_count + connect \B $sub$build/ls180/gateware/ls180.v:4538$682_Y + connect \Y $eq$build/ls180/gateware/ls180.v:4538$683_Y + end + attribute \src "build/ls180/gateware/ls180.v:4561.9-4561.42" + cell $eq $eq$build/ls180/gateware/ls180.v:4561$686 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \libresocsim_datar_timeout + connect \B 1'0 + connect \Y $eq$build/ls180/gateware/ls180.v:4561$686_Y + end + attribute \src "build/ls180/gateware/ls180.v:4571.10-4571.42" + cell $eq $eq$build/ls180/gateware/ls180.v:4571$688 + parameter \A_SIGNED 0 + parameter \A_WIDTH 10 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \libresocsim_datar_count + connect \B 6'100111 + connect \Y $eq$build/ls180/gateware/ls180.v:4571$688_Y + end + attribute \src "build/ls180/gateware/ls180.v:4740.9-4740.54" + cell $eq $eq$build/ls180/gateware/ls180.v:4740$870 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \libresocsim_sdcore_crc16_inserter_cnt + connect \B 3'111 + connect \Y $eq$build/ls180/gateware/ls180.v:4740$870_Y + end + attribute \src "build/ls180/gateware/ls180.v:4770.10-4770.55" + cell $eq $eq$build/ls180/gateware/ls180.v:4770$871 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \libresocsim_sdcore_crc16_inserter_cnt + connect \B 3'111 + connect \Y $eq$build/ls180/gateware/ls180.v:4770$871_Y + end + attribute \src "build/ls180/gateware/ls180.v:4801.10-4801.92" + cell $eq $eq$build/ls180/gateware/ls180.v:4801$876 + parameter \A_SIGNED 0 + parameter \A_WIDTH 16 + parameter \B_SIGNED 0 + parameter \B_WIDTH 16 + parameter \Y_WIDTH 1 + connect \A \libresocsim_sdcore_crc16_checker_fifo0 + connect \B \libresocsim_sdcore_crc16_checker_crctmp0 + connect \Y $eq$build/ls180/gateware/ls180.v:4801$876_Y + end + attribute \src "build/ls180/gateware/ls180.v:4801.97-4801.179" + cell $eq $eq$build/ls180/gateware/ls180.v:4801$877 + parameter \A_SIGNED 0 + parameter \A_WIDTH 16 + parameter \B_SIGNED 0 + parameter \B_WIDTH 16 + parameter \Y_WIDTH 1 + connect \A \libresocsim_sdcore_crc16_checker_fifo1 + connect \B \libresocsim_sdcore_crc16_checker_crctmp1 + connect \Y $eq$build/ls180/gateware/ls180.v:4801$877_Y + end + attribute \src "build/ls180/gateware/ls180.v:4801.185-4801.267" + cell $eq $eq$build/ls180/gateware/ls180.v:4801$879 + parameter \A_SIGNED 0 + parameter \A_WIDTH 16 + parameter \B_SIGNED 0 + parameter \B_WIDTH 16 + parameter \Y_WIDTH 1 + connect \A \libresocsim_sdcore_crc16_checker_fifo2 + connect \B \libresocsim_sdcore_crc16_checker_crctmp2 + connect \Y $eq$build/ls180/gateware/ls180.v:4801$879_Y + end + attribute \src "build/ls180/gateware/ls180.v:4801.273-4801.355" + cell $eq $eq$build/ls180/gateware/ls180.v:4801$881 + parameter \A_SIGNED 0 + parameter \A_WIDTH 16 + parameter \B_SIGNED 0 + parameter \B_WIDTH 16 + parameter \Y_WIDTH 1 + connect \A \libresocsim_sdcore_crc16_checker_fifo3 + connect \B \libresocsim_sdcore_crc16_checker_crctmp3 + connect \Y $eq$build/ls180/gateware/ls180.v:4801$881_Y + end + attribute \src "build/ls180/gateware/ls180.v:4809.7-4809.51" + cell $eq $eq$build/ls180/gateware/ls180.v:4809$885 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \libresocsim_sdcore_crc16_checker_cnt + connect \B 3'111 + connect \Y $eq$build/ls180/gateware/ls180.v:4809$885_Y + end + attribute \src "build/ls180/gateware/ls180.v:4819.7-4819.51" + cell $eq $eq$build/ls180/gateware/ls180.v:4819$888 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \libresocsim_sdcore_crc16_checker_cnt + connect \B 3'111 + connect \Y $eq$build/ls180/gateware/ls180.v:4819$888_Y + end + attribute \src "build/ls180/gateware/ls180.v:4829.7-4829.51" + cell $eq $eq$build/ls180/gateware/ls180.v:4829$891 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \libresocsim_sdcore_crc16_checker_cnt + connect \B 3'111 + connect \Y $eq$build/ls180/gateware/ls180.v:4829$891_Y + end + attribute \src "build/ls180/gateware/ls180.v:4839.7-4839.51" + cell $eq $eq$build/ls180/gateware/ls180.v:4839$894 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \libresocsim_sdcore_crc16_checker_cnt + connect \B 3'111 + connect \Y $eq$build/ls180/gateware/ls180.v:4839$894_Y + end + attribute \src "build/ls180/gateware/ls180.v:4963.37-4963.72" + cell $eq $eq$build/ls180/gateware/ls180.v:4963$945 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \libresocsim_sdcore_cmd_type + connect \B 1'0 + connect \Y $eq$build/ls180/gateware/ls180.v:4963$945_Y + end + attribute \src "build/ls180/gateware/ls180.v:4969.10-4969.46" + cell $eq $eq$build/ls180/gateware/ls180.v:4969$948 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \libresocsim_sdcore_cmd_count + connect \B 3'101 + connect \Y $eq$build/ls180/gateware/ls180.v:4969$948_Y + end + attribute \src "build/ls180/gateware/ls180.v:4970.11-4970.46" + cell $eq $eq$build/ls180/gateware/ls180.v:4970$949 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \libresocsim_sdcore_cmd_type + connect \B 1'0 + connect \Y $eq$build/ls180/gateware/ls180.v:4970$949_Y + end + attribute \src "build/ls180/gateware/ls180.v:4982.35-4982.71" + cell $eq $eq$build/ls180/gateware/ls180.v:4982$950 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \libresocsim_sdcore_data_type + connect \B 1'0 + connect \Y $eq$build/ls180/gateware/ls180.v:4982$950_Y + end + attribute \src "build/ls180/gateware/ls180.v:4983.9-4983.44" + cell $eq $eq$build/ls180/gateware/ls180.v:4983$951 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \libresocsim_sdcore_cmd_type + connect \B 2'10 + connect \Y $eq$build/ls180/gateware/ls180.v:4983$951_Y + end + attribute \src "build/ls180/gateware/ls180.v:4990.10-4990.56" + cell $eq $eq$build/ls180/gateware/ls180.v:4990$952 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \libresocsim_cmdr_source_payload_status + connect \B 1'1 + connect \Y $eq$build/ls180/gateware/ls180.v:4990$952_Y + end + attribute \src "build/ls180/gateware/ls180.v:4996.12-4996.48" + cell $eq $eq$build/ls180/gateware/ls180.v:4996$953 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \libresocsim_sdcore_data_type + connect \B 2'10 + connect \Y $eq$build/ls180/gateware/ls180.v:4996$953_Y + end + attribute \src "build/ls180/gateware/ls180.v:4999.13-4999.49" + cell $eq $eq$build/ls180/gateware/ls180.v:4999$954 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \libresocsim_sdcore_data_type + connect \B 1'1 + connect \Y $eq$build/ls180/gateware/ls180.v:4999$954_Y + end + attribute \src "build/ls180/gateware/ls180.v:5021.10-5021.90" + cell $eq $eq$build/ls180/gateware/ls180.v:5021$959 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 32 + parameter \Y_WIDTH 1 + connect \A \libresocsim_sdcore_data_count + connect \B $sub$build/ls180/gateware/ls180.v:5021$958_Y + connect \Y $eq$build/ls180/gateware/ls180.v:5021$959_Y + end + attribute \src "build/ls180/gateware/ls180.v:5036.36-5036.116" + cell $eq $eq$build/ls180/gateware/ls180.v:5036$962 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 32 + parameter \Y_WIDTH 1 + connect \A \libresocsim_sdcore_data_count + connect \B $sub$build/ls180/gateware/ls180.v:5036$961_Y + connect \Y $eq$build/ls180/gateware/ls180.v:5036$962_Y + end + attribute \src "build/ls180/gateware/ls180.v:5038.10-5038.57" + cell $eq $eq$build/ls180/gateware/ls180.v:5038$963 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \libresocsim_datar_source_payload_status + connect \B 1'0 + connect \Y $eq$build/ls180/gateware/ls180.v:5038$963_Y + end + attribute \src "build/ls180/gateware/ls180.v:5047.12-5047.92" + cell $eq $eq$build/ls180/gateware/ls180.v:5047$967 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 32 + parameter \Y_WIDTH 1 + connect \A \libresocsim_sdcore_data_count + connect \B $sub$build/ls180/gateware/ls180.v:5047$966_Y + connect \Y $eq$build/ls180/gateware/ls180.v:5047$967_Y + end + attribute \src "build/ls180/gateware/ls180.v:5054.11-5054.58" + cell $eq $eq$build/ls180/gateware/ls180.v:5054$968 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \libresocsim_datar_source_payload_status + connect \B 1'1 + connect \Y $eq$build/ls180/gateware/ls180.v:5054$968_Y + end + attribute \src "build/ls180/gateware/ls180.v:5171.10-5171.119" + cell $eq $eq$build/ls180/gateware/ls180.v:5171$985 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 32 + parameter \Y_WIDTH 1 + connect \A \libresocsim_sdblock2mem_wishbonedmawriter_offset + connect \B $sub$build/ls180/gateware/ls180.v:5171$984_Y + connect \Y $eq$build/ls180/gateware/ls180.v:5171$985_Y + end + attribute \src "build/ls180/gateware/ls180.v:5261.46-5261.127" + cell $eq $eq$build/ls180/gateware/ls180.v:5261$991 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 32 + parameter \Y_WIDTH 1 + connect \A \libresocsim_sdmem2block_dma_offset + connect \B $sub$build/ls180/gateware/ls180.v:5261$990_Y + connect \Y $eq$build/ls180/gateware/ls180.v:5261$991_Y + end + attribute \src "build/ls180/gateware/ls180.v:5291.51-5291.96" + cell $eq $eq$build/ls180/gateware/ls180.v:5291$994 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \libresocsim_sdmem2block_converter_mux + connect \B 1'0 + connect \Y $eq$build/ls180/gateware/ls180.v:5291$994_Y + end + attribute \src "build/ls180/gateware/ls180.v:5292.50-5292.95" + cell $eq $eq$build/ls180/gateware/ls180.v:5292$995 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \libresocsim_sdmem2block_converter_mux + connect \B 2'11 + connect \Y $eq$build/ls180/gateware/ls180.v:5292$995_Y + end + attribute \src "build/ls180/gateware/ls180.v:5349.32-5349.99" + cell $eq $eq$build/ls180/gateware/ls180.v:5349$1008 + parameter \A_SIGNED 0 + parameter \A_WIDTH 16 + parameter \B_SIGNED 0 + parameter \B_WIDTH 16 + parameter \Y_WIDTH 1 + connect \A \libresocsim_clk_divider1 + connect \B $sub$build/ls180/gateware/ls180.v:5349$1007_Y + connect \Y $eq$build/ls180/gateware/ls180.v:5349$1008_Y + end + attribute \src "build/ls180/gateware/ls180.v:5350.32-5350.93" + cell $eq $eq$build/ls180/gateware/ls180.v:5350$1010 + parameter \A_SIGNED 0 + parameter \A_WIDTH 16 + parameter \B_SIGNED 0 + parameter \B_WIDTH 16 + parameter \Y_WIDTH 1 + connect \A \libresocsim_clk_divider1 + connect \B $sub$build/ls180/gateware/ls180.v:5350$1009_Y + connect \Y $eq$build/ls180/gateware/ls180.v:5350$1010_Y + end + attribute \src "build/ls180/gateware/ls180.v:5378.10-5378.59" + cell $eq $eq$build/ls180/gateware/ls180.v:5378$1014 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \libresocsim_count + connect \B $sub$build/ls180/gateware/ls180.v:5378$1013_Y + connect \Y $eq$build/ls180/gateware/ls180.v:5378$1014_Y + end + attribute \src "build/ls180/gateware/ls180.v:5450.85-5450.106" + cell $eq $eq$build/ls180/gateware/ls180.v:5450$1019 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_grant + connect \B 1'0 + connect \Y $eq$build/ls180/gateware/ls180.v:5450$1019_Y + end + attribute \src "build/ls180/gateware/ls180.v:5451.85-5451.106" + cell $eq $eq$build/ls180/gateware/ls180.v:5451$1021 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_grant + connect \B 1'1 + connect \Y $eq$build/ls180/gateware/ls180.v:5451$1021_Y + end + attribute \src "build/ls180/gateware/ls180.v:5452.64-5452.85" + cell $eq $eq$build/ls180/gateware/ls180.v:5452$1023 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_grant + connect \B 2'10 + connect \Y $eq$build/ls180/gateware/ls180.v:5452$1023_Y + end + attribute \src "build/ls180/gateware/ls180.v:5453.64-5453.85" + cell $eq $eq$build/ls180/gateware/ls180.v:5453$1025 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_grant + connect \B 2'11 + connect \Y $eq$build/ls180/gateware/ls180.v:5453$1025_Y + end + attribute \src "build/ls180/gateware/ls180.v:5454.85-5454.106" + cell $eq $eq$build/ls180/gateware/ls180.v:5454$1027 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_grant + connect \B 1'0 + connect \Y $eq$build/ls180/gateware/ls180.v:5454$1027_Y + end + attribute \src "build/ls180/gateware/ls180.v:5455.85-5455.106" + cell $eq $eq$build/ls180/gateware/ls180.v:5455$1029 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_grant + connect \B 1'1 + connect \Y $eq$build/ls180/gateware/ls180.v:5455$1029_Y + end + attribute \src "build/ls180/gateware/ls180.v:5456.64-5456.85" + cell $eq $eq$build/ls180/gateware/ls180.v:5456$1031 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_grant + connect \B 2'10 + connect \Y $eq$build/ls180/gateware/ls180.v:5456$1031_Y + end + attribute \src "build/ls180/gateware/ls180.v:5457.64-5457.85" + cell $eq $eq$build/ls180/gateware/ls180.v:5457$1033 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_grant + connect \B 2'11 + connect \Y $eq$build/ls180/gateware/ls180.v:5457$1033_Y + end + attribute \src "build/ls180/gateware/ls180.v:5461.27-5461.64" + cell $eq $eq$build/ls180/gateware/ls180.v:5461$1036 + parameter \A_SIGNED 0 + parameter \A_WIDTH 14 + parameter \B_SIGNED 0 + parameter \B_WIDTH 14 + parameter \Y_WIDTH 1 + connect \A \builder_shared_adr [29:16] + connect \B 14'10010000000000 + connect \Y $eq$build/ls180/gateware/ls180.v:5461$1036_Y + end + attribute \src "build/ls180/gateware/ls180.v:5462.27-5462.68" + cell $eq $eq$build/ls180/gateware/ls180.v:5462$1037 + parameter \A_SIGNED 0 + parameter \A_WIDTH 27 + parameter \B_SIGNED 0 + parameter \B_WIDTH 27 + parameter \Y_WIDTH 1 + connect \A \builder_shared_adr [29:3] + connect \B 27'110000000000000100000000000 + connect \Y $eq$build/ls180/gateware/ls180.v:5462$1037_Y + end + attribute \src "build/ls180/gateware/ls180.v:5463.27-5463.66" + cell $eq $eq$build/ls180/gateware/ls180.v:5463$1038 + parameter \A_SIGNED 0 + parameter \A_WIDTH 20 + parameter \B_SIGNED 0 + parameter \B_WIDTH 20 + parameter \Y_WIDTH 1 + connect \A \builder_shared_adr [29:10] + connect \B 20'11000000000000010001 + connect \Y $eq$build/ls180/gateware/ls180.v:5463$1038_Y + end + attribute \src "build/ls180/gateware/ls180.v:5464.27-5464.60" + cell $eq $eq$build/ls180/gateware/ls180.v:5464$1039 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_shared_adr [29:23] + connect \B 1'0 + connect \Y $eq$build/ls180/gateware/ls180.v:5464$1039_Y + end + attribute \src "build/ls180/gateware/ls180.v:5465.27-5465.65" + cell $eq $eq$build/ls180/gateware/ls180.v:5465$1040 + parameter \A_SIGNED 0 + parameter \A_WIDTH 16 + parameter \B_SIGNED 0 + parameter \B_WIDTH 16 + parameter \Y_WIDTH 1 + connect \A \builder_shared_adr [29:14] + connect \B 16'1100000000000000 + connect \Y $eq$build/ls180/gateware/ls180.v:5465$1040_Y + end + attribute \src "build/ls180/gateware/ls180.v:5521.24-5521.45" + cell $eq $eq$build/ls180/gateware/ls180.v:5521$1067 + parameter \A_SIGNED 0 + parameter \A_WIDTH 20 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_count + connect \B 1'0 + connect \Y $eq$build/ls180/gateware/ls180.v:5521$1067_Y + end + attribute \src "build/ls180/gateware/ls180.v:5522.32-5522.77" + cell $eq $eq$build/ls180/gateware/ls180.v:5522$1068 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface0_bank_bus_adr [13:9] + connect \B 1'0 + connect \Y $eq$build/ls180/gateware/ls180.v:5522$1068_Y + end + attribute \src "build/ls180/gateware/ls180.v:5524.97-5524.141" + cell $eq $eq$build/ls180/gateware/ls180.v:5524$1070 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface0_bank_bus_adr [3:0] + connect \B 1'0 + connect \Y $eq$build/ls180/gateware/ls180.v:5524$1070_Y + end + attribute \src "build/ls180/gateware/ls180.v:5525.100-5525.144" + cell $eq $eq$build/ls180/gateware/ls180.v:5525$1074 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface0_bank_bus_adr [3:0] + connect \B 1'0 + connect \Y $eq$build/ls180/gateware/ls180.v:5525$1074_Y + end + attribute \src "build/ls180/gateware/ls180.v:5527.99-5527.143" + cell $eq $eq$build/ls180/gateware/ls180.v:5527$1077 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface0_bank_bus_adr [3:0] + connect \B 1'1 + connect \Y $eq$build/ls180/gateware/ls180.v:5527$1077_Y + end + attribute \src "build/ls180/gateware/ls180.v:5528.102-5528.146" + cell $eq $eq$build/ls180/gateware/ls180.v:5528$1081 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface0_bank_bus_adr [3:0] + connect \B 1'1 + connect \Y $eq$build/ls180/gateware/ls180.v:5528$1081_Y + end + attribute \src "build/ls180/gateware/ls180.v:5530.99-5530.143" + cell $eq $eq$build/ls180/gateware/ls180.v:5530$1084 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface0_bank_bus_adr [3:0] + connect \B 2'10 + connect \Y $eq$build/ls180/gateware/ls180.v:5530$1084_Y + end + attribute \src "build/ls180/gateware/ls180.v:5531.102-5531.146" + cell $eq $eq$build/ls180/gateware/ls180.v:5531$1088 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface0_bank_bus_adr [3:0] + connect \B 2'10 + connect \Y $eq$build/ls180/gateware/ls180.v:5531$1088_Y + end + attribute \src "build/ls180/gateware/ls180.v:5533.99-5533.143" + cell $eq $eq$build/ls180/gateware/ls180.v:5533$1091 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface0_bank_bus_adr [3:0] + connect \B 2'11 + connect \Y $eq$build/ls180/gateware/ls180.v:5533$1091_Y + end + attribute \src "build/ls180/gateware/ls180.v:5534.102-5534.146" + cell $eq $eq$build/ls180/gateware/ls180.v:5534$1095 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface0_bank_bus_adr [3:0] + connect \B 2'11 + connect \Y $eq$build/ls180/gateware/ls180.v:5534$1095_Y + end + attribute \src "build/ls180/gateware/ls180.v:5536.99-5536.143" + cell $eq $eq$build/ls180/gateware/ls180.v:5536$1098 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface0_bank_bus_adr [3:0] + connect \B 3'100 + connect \Y $eq$build/ls180/gateware/ls180.v:5536$1098_Y + end + attribute \src "build/ls180/gateware/ls180.v:5537.102-5537.146" + cell $eq $eq$build/ls180/gateware/ls180.v:5537$1102 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface0_bank_bus_adr [3:0] + connect \B 3'100 + connect \Y $eq$build/ls180/gateware/ls180.v:5537$1102_Y + end + attribute \src "build/ls180/gateware/ls180.v:5539.102-5539.146" + cell $eq $eq$build/ls180/gateware/ls180.v:5539$1105 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface0_bank_bus_adr [3:0] + connect \B 3'101 + connect \Y $eq$build/ls180/gateware/ls180.v:5539$1105_Y + end + attribute \src "build/ls180/gateware/ls180.v:5540.105-5540.149" + cell $eq $eq$build/ls180/gateware/ls180.v:5540$1109 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface0_bank_bus_adr [3:0] + connect \B 3'101 + connect \Y $eq$build/ls180/gateware/ls180.v:5540$1109_Y + end + attribute \src "build/ls180/gateware/ls180.v:5542.102-5542.146" + cell $eq $eq$build/ls180/gateware/ls180.v:5542$1112 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface0_bank_bus_adr [3:0] + connect \B 3'110 + connect \Y $eq$build/ls180/gateware/ls180.v:5542$1112_Y + end + attribute \src "build/ls180/gateware/ls180.v:5543.105-5543.149" + cell $eq $eq$build/ls180/gateware/ls180.v:5543$1116 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface0_bank_bus_adr [3:0] + connect \B 3'110 + connect \Y $eq$build/ls180/gateware/ls180.v:5543$1116_Y + end + attribute \src "build/ls180/gateware/ls180.v:5545.102-5545.146" + cell $eq $eq$build/ls180/gateware/ls180.v:5545$1119 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface0_bank_bus_adr [3:0] + connect \B 3'111 + connect \Y $eq$build/ls180/gateware/ls180.v:5545$1119_Y + end + attribute \src "build/ls180/gateware/ls180.v:5546.105-5546.149" + cell $eq $eq$build/ls180/gateware/ls180.v:5546$1123 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface0_bank_bus_adr [3:0] + connect \B 3'111 + connect \Y $eq$build/ls180/gateware/ls180.v:5546$1123_Y + end + attribute \src "build/ls180/gateware/ls180.v:5548.102-5548.146" + cell $eq $eq$build/ls180/gateware/ls180.v:5548$1126 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface0_bank_bus_adr [3:0] + connect \B 4'1000 + connect \Y $eq$build/ls180/gateware/ls180.v:5548$1126_Y + end + attribute \src "build/ls180/gateware/ls180.v:5549.105-5549.149" + cell $eq $eq$build/ls180/gateware/ls180.v:5549$1130 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface0_bank_bus_adr [3:0] + connect \B 4'1000 + connect \Y $eq$build/ls180/gateware/ls180.v:5549$1130_Y + end + attribute \src "build/ls180/gateware/ls180.v:5560.32-5560.77" + cell $eq $eq$build/ls180/gateware/ls180.v:5560$1132 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface1_bank_bus_adr [13:9] + connect \B 3'110 + connect \Y $eq$build/ls180/gateware/ls180.v:5560$1132_Y + end + attribute \src "build/ls180/gateware/ls180.v:5562.93-5562.135" + cell $eq $eq$build/ls180/gateware/ls180.v:5562$1134 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface1_bank_bus_adr [0] + connect \B 1'0 + connect \Y $eq$build/ls180/gateware/ls180.v:5562$1134_Y + end + attribute \src "build/ls180/gateware/ls180.v:5563.96-5563.138" + cell $eq $eq$build/ls180/gateware/ls180.v:5563$1138 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface1_bank_bus_adr [0] + connect \B 1'0 + connect \Y $eq$build/ls180/gateware/ls180.v:5563$1138_Y + end + attribute \src "build/ls180/gateware/ls180.v:5566.32-5566.77" + cell $eq $eq$build/ls180/gateware/ls180.v:5566$1140 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface2_bank_bus_adr [13:9] + connect \B 3'111 + connect \Y $eq$build/ls180/gateware/ls180.v:5566$1140_Y + end + attribute \src "build/ls180/gateware/ls180.v:5568.93-5568.135" + cell $eq $eq$build/ls180/gateware/ls180.v:5568$1142 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface2_bank_bus_adr [0] + connect \B 1'0 + connect \Y $eq$build/ls180/gateware/ls180.v:5568$1142_Y + end + attribute \src "build/ls180/gateware/ls180.v:5569.96-5569.138" + cell $eq $eq$build/ls180/gateware/ls180.v:5569$1146 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface2_bank_bus_adr [0] + connect \B 1'0 + connect \Y $eq$build/ls180/gateware/ls180.v:5569$1146_Y + end + attribute \src "build/ls180/gateware/ls180.v:5572.32-5572.78" + cell $eq $eq$build/ls180/gateware/ls180.v:5572$1148 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface3_bank_bus_adr [13:9] + connect \B 4'1011 + connect \Y $eq$build/ls180/gateware/ls180.v:5572$1148_Y + end + attribute \src "build/ls180/gateware/ls180.v:5574.100-5574.144" + cell $eq $eq$build/ls180/gateware/ls180.v:5574$1150 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface3_bank_bus_adr [3:0] + connect \B 1'0 + connect \Y $eq$build/ls180/gateware/ls180.v:5574$1150_Y + end + attribute \src "build/ls180/gateware/ls180.v:5575.103-5575.147" + cell $eq $eq$build/ls180/gateware/ls180.v:5575$1154 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface3_bank_bus_adr [3:0] + connect \B 1'0 + connect \Y $eq$build/ls180/gateware/ls180.v:5575$1154_Y + end + attribute \src "build/ls180/gateware/ls180.v:5577.100-5577.144" + cell $eq $eq$build/ls180/gateware/ls180.v:5577$1157 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface3_bank_bus_adr [3:0] + connect \B 1'1 + connect \Y $eq$build/ls180/gateware/ls180.v:5577$1157_Y + end + attribute \src "build/ls180/gateware/ls180.v:5578.103-5578.147" + cell $eq $eq$build/ls180/gateware/ls180.v:5578$1161 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface3_bank_bus_adr [3:0] + connect \B 1'1 + connect \Y $eq$build/ls180/gateware/ls180.v:5578$1161_Y + end + attribute \src "build/ls180/gateware/ls180.v:5580.100-5580.144" + cell $eq $eq$build/ls180/gateware/ls180.v:5580$1164 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface3_bank_bus_adr [3:0] + connect \B 2'10 + connect \Y $eq$build/ls180/gateware/ls180.v:5580$1164_Y + end + attribute \src "build/ls180/gateware/ls180.v:5581.103-5581.147" + cell $eq $eq$build/ls180/gateware/ls180.v:5581$1168 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface3_bank_bus_adr [3:0] + connect \B 2'10 + connect \Y $eq$build/ls180/gateware/ls180.v:5581$1168_Y + end + attribute \src "build/ls180/gateware/ls180.v:5583.100-5583.144" + cell $eq $eq$build/ls180/gateware/ls180.v:5583$1171 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface3_bank_bus_adr [3:0] + connect \B 2'11 + connect \Y $eq$build/ls180/gateware/ls180.v:5583$1171_Y + end + attribute \src "build/ls180/gateware/ls180.v:5584.103-5584.147" + cell $eq $eq$build/ls180/gateware/ls180.v:5584$1175 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface3_bank_bus_adr [3:0] + connect \B 2'11 + connect \Y $eq$build/ls180/gateware/ls180.v:5584$1175_Y + end + attribute \src "build/ls180/gateware/ls180.v:5586.100-5586.144" + cell $eq $eq$build/ls180/gateware/ls180.v:5586$1178 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface3_bank_bus_adr [3:0] + connect \B 3'100 + connect \Y $eq$build/ls180/gateware/ls180.v:5586$1178_Y + end + attribute \src "build/ls180/gateware/ls180.v:5587.103-5587.147" + cell $eq $eq$build/ls180/gateware/ls180.v:5587$1182 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface3_bank_bus_adr [3:0] + connect \B 3'100 + connect \Y $eq$build/ls180/gateware/ls180.v:5587$1182_Y + end + attribute \src "build/ls180/gateware/ls180.v:5589.100-5589.144" + cell $eq $eq$build/ls180/gateware/ls180.v:5589$1185 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface3_bank_bus_adr [3:0] + connect \B 3'101 + connect \Y $eq$build/ls180/gateware/ls180.v:5589$1185_Y + end + attribute \src "build/ls180/gateware/ls180.v:5590.103-5590.147" + cell $eq $eq$build/ls180/gateware/ls180.v:5590$1189 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface3_bank_bus_adr [3:0] + connect \B 3'101 + connect \Y $eq$build/ls180/gateware/ls180.v:5590$1189_Y + end + attribute \src "build/ls180/gateware/ls180.v:5592.100-5592.144" + cell $eq $eq$build/ls180/gateware/ls180.v:5592$1192 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface3_bank_bus_adr [3:0] + connect \B 3'110 + connect \Y $eq$build/ls180/gateware/ls180.v:5592$1192_Y + end + attribute \src "build/ls180/gateware/ls180.v:5593.103-5593.147" + cell $eq $eq$build/ls180/gateware/ls180.v:5593$1196 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface3_bank_bus_adr [3:0] + connect \B 3'110 + connect \Y $eq$build/ls180/gateware/ls180.v:5593$1196_Y + end + attribute \src "build/ls180/gateware/ls180.v:5595.100-5595.144" + cell $eq $eq$build/ls180/gateware/ls180.v:5595$1199 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface3_bank_bus_adr [3:0] + connect \B 3'111 + connect \Y $eq$build/ls180/gateware/ls180.v:5595$1199_Y + end + attribute \src "build/ls180/gateware/ls180.v:5596.103-5596.147" + cell $eq $eq$build/ls180/gateware/ls180.v:5596$1203 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface3_bank_bus_adr [3:0] + connect \B 3'111 + connect \Y $eq$build/ls180/gateware/ls180.v:5596$1203_Y + end + attribute \src "build/ls180/gateware/ls180.v:5598.102-5598.146" + cell $eq $eq$build/ls180/gateware/ls180.v:5598$1206 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface3_bank_bus_adr [3:0] + connect \B 4'1000 + connect \Y $eq$build/ls180/gateware/ls180.v:5598$1206_Y + end + attribute \src "build/ls180/gateware/ls180.v:5599.105-5599.149" + cell $eq $eq$build/ls180/gateware/ls180.v:5599$1210 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface3_bank_bus_adr [3:0] + connect \B 4'1000 + connect \Y $eq$build/ls180/gateware/ls180.v:5599$1210_Y + end + attribute \src "build/ls180/gateware/ls180.v:5601.102-5601.146" + cell $eq $eq$build/ls180/gateware/ls180.v:5601$1213 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface3_bank_bus_adr [3:0] + connect \B 4'1001 + connect \Y $eq$build/ls180/gateware/ls180.v:5601$1213_Y + end + attribute \src "build/ls180/gateware/ls180.v:5602.105-5602.149" + cell $eq $eq$build/ls180/gateware/ls180.v:5602$1217 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface3_bank_bus_adr [3:0] + connect \B 4'1001 + connect \Y $eq$build/ls180/gateware/ls180.v:5602$1217_Y + end + attribute \src "build/ls180/gateware/ls180.v:5604.102-5604.147" + cell $eq $eq$build/ls180/gateware/ls180.v:5604$1220 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface3_bank_bus_adr [3:0] + connect \B 4'1010 + connect \Y $eq$build/ls180/gateware/ls180.v:5604$1220_Y + end + attribute \src "build/ls180/gateware/ls180.v:5605.105-5605.150" + cell $eq $eq$build/ls180/gateware/ls180.v:5605$1224 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface3_bank_bus_adr [3:0] + connect \B 4'1010 + connect \Y $eq$build/ls180/gateware/ls180.v:5605$1224_Y + end + attribute \src "build/ls180/gateware/ls180.v:5607.102-5607.147" + cell $eq $eq$build/ls180/gateware/ls180.v:5607$1227 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface3_bank_bus_adr [3:0] + connect \B 4'1011 + connect \Y $eq$build/ls180/gateware/ls180.v:5607$1227_Y + end + attribute \src "build/ls180/gateware/ls180.v:5608.105-5608.150" + cell $eq $eq$build/ls180/gateware/ls180.v:5608$1231 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface3_bank_bus_adr [3:0] + connect \B 4'1011 + connect \Y $eq$build/ls180/gateware/ls180.v:5608$1231_Y + end + attribute \src "build/ls180/gateware/ls180.v:5610.102-5610.147" + cell $eq $eq$build/ls180/gateware/ls180.v:5610$1234 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface3_bank_bus_adr [3:0] + connect \B 4'1100 + connect \Y $eq$build/ls180/gateware/ls180.v:5610$1234_Y + end + attribute \src "build/ls180/gateware/ls180.v:5611.105-5611.150" + cell $eq $eq$build/ls180/gateware/ls180.v:5611$1238 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface3_bank_bus_adr [3:0] + connect \B 4'1100 + connect \Y $eq$build/ls180/gateware/ls180.v:5611$1238_Y + end + attribute \src "build/ls180/gateware/ls180.v:5613.99-5613.144" + cell $eq $eq$build/ls180/gateware/ls180.v:5613$1241 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface3_bank_bus_adr [3:0] + connect \B 4'1101 + connect \Y $eq$build/ls180/gateware/ls180.v:5613$1241_Y + end + attribute \src "build/ls180/gateware/ls180.v:5614.102-5614.147" + cell $eq $eq$build/ls180/gateware/ls180.v:5614$1245 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface3_bank_bus_adr [3:0] + connect \B 4'1101 + connect \Y $eq$build/ls180/gateware/ls180.v:5614$1245_Y + end + attribute \src "build/ls180/gateware/ls180.v:5616.100-5616.145" + cell $eq $eq$build/ls180/gateware/ls180.v:5616$1248 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface3_bank_bus_adr [3:0] + connect \B 4'1110 + connect \Y $eq$build/ls180/gateware/ls180.v:5616$1248_Y + end + attribute \src "build/ls180/gateware/ls180.v:5617.103-5617.148" + cell $eq $eq$build/ls180/gateware/ls180.v:5617$1252 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface3_bank_bus_adr [3:0] + connect \B 4'1110 + connect \Y $eq$build/ls180/gateware/ls180.v:5617$1252_Y + end + attribute \src "build/ls180/gateware/ls180.v:5634.32-5634.78" + cell $eq $eq$build/ls180/gateware/ls180.v:5634$1254 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface4_bank_bus_adr [13:9] + connect \B 4'1010 + connect \Y $eq$build/ls180/gateware/ls180.v:5634$1254_Y + end + attribute \src "build/ls180/gateware/ls180.v:5636.104-5636.148" + cell $eq $eq$build/ls180/gateware/ls180.v:5636$1256 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface4_bank_bus_adr [5:0] + connect \B 1'0 + connect \Y $eq$build/ls180/gateware/ls180.v:5636$1256_Y + end + attribute \src "build/ls180/gateware/ls180.v:5637.107-5637.151" + cell $eq $eq$build/ls180/gateware/ls180.v:5637$1260 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface4_bank_bus_adr [5:0] + connect \B 1'0 + connect \Y $eq$build/ls180/gateware/ls180.v:5637$1260_Y + end + attribute \src "build/ls180/gateware/ls180.v:5639.104-5639.148" + cell $eq $eq$build/ls180/gateware/ls180.v:5639$1263 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface4_bank_bus_adr [5:0] + connect \B 1'1 + connect \Y $eq$build/ls180/gateware/ls180.v:5639$1263_Y + end + attribute \src "build/ls180/gateware/ls180.v:5640.107-5640.151" + cell $eq $eq$build/ls180/gateware/ls180.v:5640$1267 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface4_bank_bus_adr [5:0] + connect \B 1'1 + connect \Y $eq$build/ls180/gateware/ls180.v:5640$1267_Y + end + attribute \src "build/ls180/gateware/ls180.v:5642.104-5642.148" + cell $eq $eq$build/ls180/gateware/ls180.v:5642$1270 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface4_bank_bus_adr [5:0] + connect \B 2'10 + connect \Y $eq$build/ls180/gateware/ls180.v:5642$1270_Y + end + attribute \src "build/ls180/gateware/ls180.v:5643.107-5643.151" + cell $eq $eq$build/ls180/gateware/ls180.v:5643$1274 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface4_bank_bus_adr [5:0] + connect \B 2'10 + connect \Y $eq$build/ls180/gateware/ls180.v:5643$1274_Y + end + attribute \src "build/ls180/gateware/ls180.v:5645.104-5645.148" + cell $eq $eq$build/ls180/gateware/ls180.v:5645$1277 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface4_bank_bus_adr [5:0] + connect \B 2'11 + connect \Y $eq$build/ls180/gateware/ls180.v:5645$1277_Y + end + attribute \src "build/ls180/gateware/ls180.v:5646.107-5646.151" + cell $eq $eq$build/ls180/gateware/ls180.v:5646$1281 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface4_bank_bus_adr [5:0] + connect \B 2'11 + connect \Y $eq$build/ls180/gateware/ls180.v:5646$1281_Y + end + attribute \src "build/ls180/gateware/ls180.v:5648.103-5648.147" + cell $eq $eq$build/ls180/gateware/ls180.v:5648$1284 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface4_bank_bus_adr [5:0] + connect \B 3'100 + connect \Y $eq$build/ls180/gateware/ls180.v:5648$1284_Y + end + attribute \src "build/ls180/gateware/ls180.v:5649.106-5649.150" + cell $eq $eq$build/ls180/gateware/ls180.v:5649$1288 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface4_bank_bus_adr [5:0] + connect \B 3'100 + connect \Y $eq$build/ls180/gateware/ls180.v:5649$1288_Y + end + attribute \src "build/ls180/gateware/ls180.v:5651.103-5651.147" + cell $eq $eq$build/ls180/gateware/ls180.v:5651$1291 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface4_bank_bus_adr [5:0] + connect \B 3'101 + connect \Y $eq$build/ls180/gateware/ls180.v:5651$1291_Y + end + attribute \src "build/ls180/gateware/ls180.v:5652.106-5652.150" + cell $eq $eq$build/ls180/gateware/ls180.v:5652$1295 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface4_bank_bus_adr [5:0] + connect \B 3'101 + connect \Y $eq$build/ls180/gateware/ls180.v:5652$1295_Y + end + attribute \src "build/ls180/gateware/ls180.v:5654.103-5654.147" + cell $eq $eq$build/ls180/gateware/ls180.v:5654$1298 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface4_bank_bus_adr [5:0] + connect \B 3'110 + connect \Y $eq$build/ls180/gateware/ls180.v:5654$1298_Y + end + attribute \src "build/ls180/gateware/ls180.v:5655.106-5655.150" + cell $eq $eq$build/ls180/gateware/ls180.v:5655$1302 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface4_bank_bus_adr [5:0] + connect \B 3'110 + connect \Y $eq$build/ls180/gateware/ls180.v:5655$1302_Y + end + attribute \src "build/ls180/gateware/ls180.v:5657.103-5657.147" + cell $eq $eq$build/ls180/gateware/ls180.v:5657$1305 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface4_bank_bus_adr [5:0] + connect \B 3'111 + connect \Y $eq$build/ls180/gateware/ls180.v:5657$1305_Y + end + attribute \src "build/ls180/gateware/ls180.v:5658.106-5658.150" + cell $eq $eq$build/ls180/gateware/ls180.v:5658$1309 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface4_bank_bus_adr [5:0] + connect \B 3'111 + connect \Y $eq$build/ls180/gateware/ls180.v:5658$1309_Y + end + attribute \src "build/ls180/gateware/ls180.v:5660.101-5660.145" + cell $eq $eq$build/ls180/gateware/ls180.v:5660$1312 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface4_bank_bus_adr [5:0] + connect \B 4'1000 + connect \Y $eq$build/ls180/gateware/ls180.v:5660$1312_Y + end + attribute \src "build/ls180/gateware/ls180.v:5661.104-5661.148" + cell $eq $eq$build/ls180/gateware/ls180.v:5661$1316 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface4_bank_bus_adr [5:0] + connect \B 4'1000 + connect \Y $eq$build/ls180/gateware/ls180.v:5661$1316_Y + end + attribute \src "build/ls180/gateware/ls180.v:5663.105-5663.149" + cell $eq $eq$build/ls180/gateware/ls180.v:5663$1319 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface4_bank_bus_adr [5:0] + connect \B 4'1001 + connect \Y $eq$build/ls180/gateware/ls180.v:5663$1319_Y + end + attribute \src "build/ls180/gateware/ls180.v:5664.108-5664.152" + cell $eq $eq$build/ls180/gateware/ls180.v:5664$1323 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface4_bank_bus_adr [5:0] + connect \B 4'1001 + connect \Y $eq$build/ls180/gateware/ls180.v:5664$1323_Y + end + attribute \src "build/ls180/gateware/ls180.v:5666.105-5666.150" + cell $eq $eq$build/ls180/gateware/ls180.v:5666$1326 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface4_bank_bus_adr [5:0] + connect \B 4'1010 + connect \Y $eq$build/ls180/gateware/ls180.v:5666$1326_Y + end + attribute \src "build/ls180/gateware/ls180.v:5667.108-5667.153" + cell $eq $eq$build/ls180/gateware/ls180.v:5667$1330 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface4_bank_bus_adr [5:0] + connect \B 4'1010 + connect \Y $eq$build/ls180/gateware/ls180.v:5667$1330_Y + end + attribute \src "build/ls180/gateware/ls180.v:5669.105-5669.150" + cell $eq $eq$build/ls180/gateware/ls180.v:5669$1333 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface4_bank_bus_adr [5:0] + connect \B 4'1011 + connect \Y $eq$build/ls180/gateware/ls180.v:5669$1333_Y + end + attribute \src "build/ls180/gateware/ls180.v:5670.108-5670.153" + cell $eq $eq$build/ls180/gateware/ls180.v:5670$1337 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface4_bank_bus_adr [5:0] + connect \B 4'1011 + connect \Y $eq$build/ls180/gateware/ls180.v:5670$1337_Y + end + attribute \src "build/ls180/gateware/ls180.v:5672.105-5672.150" + cell $eq $eq$build/ls180/gateware/ls180.v:5672$1340 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface4_bank_bus_adr [5:0] + connect \B 4'1100 + connect \Y $eq$build/ls180/gateware/ls180.v:5672$1340_Y + end + attribute \src "build/ls180/gateware/ls180.v:5673.108-5673.153" + cell $eq $eq$build/ls180/gateware/ls180.v:5673$1344 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface4_bank_bus_adr [5:0] + connect \B 4'1100 + connect \Y $eq$build/ls180/gateware/ls180.v:5673$1344_Y + end + attribute \src "build/ls180/gateware/ls180.v:5675.105-5675.150" + cell $eq $eq$build/ls180/gateware/ls180.v:5675$1347 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface4_bank_bus_adr [5:0] + connect \B 4'1101 + connect \Y $eq$build/ls180/gateware/ls180.v:5675$1347_Y + end + attribute \src "build/ls180/gateware/ls180.v:5676.108-5676.153" + cell $eq $eq$build/ls180/gateware/ls180.v:5676$1351 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface4_bank_bus_adr [5:0] + connect \B 4'1101 + connect \Y $eq$build/ls180/gateware/ls180.v:5676$1351_Y + end + attribute \src "build/ls180/gateware/ls180.v:5678.105-5678.150" + cell $eq $eq$build/ls180/gateware/ls180.v:5678$1354 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface4_bank_bus_adr [5:0] + connect \B 4'1110 + connect \Y $eq$build/ls180/gateware/ls180.v:5678$1354_Y + end + attribute \src "build/ls180/gateware/ls180.v:5679.108-5679.153" + cell $eq $eq$build/ls180/gateware/ls180.v:5679$1358 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface4_bank_bus_adr [5:0] + connect \B 4'1110 + connect \Y $eq$build/ls180/gateware/ls180.v:5679$1358_Y + end + attribute \src "build/ls180/gateware/ls180.v:5681.104-5681.149" + cell $eq $eq$build/ls180/gateware/ls180.v:5681$1361 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface4_bank_bus_adr [5:0] + connect \B 4'1111 + connect \Y $eq$build/ls180/gateware/ls180.v:5681$1361_Y + end + attribute \src "build/ls180/gateware/ls180.v:5682.107-5682.152" + cell $eq $eq$build/ls180/gateware/ls180.v:5682$1365 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface4_bank_bus_adr [5:0] + connect \B 4'1111 + connect \Y $eq$build/ls180/gateware/ls180.v:5682$1365_Y + end + attribute \src "build/ls180/gateware/ls180.v:5684.104-5684.149" + cell $eq $eq$build/ls180/gateware/ls180.v:5684$1368 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \builder_interface4_bank_bus_adr [5:0] + connect \B 5'10000 + connect \Y $eq$build/ls180/gateware/ls180.v:5684$1368_Y + end + attribute \src "build/ls180/gateware/ls180.v:5685.107-5685.152" + cell $eq $eq$build/ls180/gateware/ls180.v:5685$1372 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \builder_interface4_bank_bus_adr [5:0] + connect \B 5'10000 + connect \Y $eq$build/ls180/gateware/ls180.v:5685$1372_Y + end + attribute \src "build/ls180/gateware/ls180.v:5687.104-5687.149" + cell $eq $eq$build/ls180/gateware/ls180.v:5687$1375 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \builder_interface4_bank_bus_adr [5:0] + connect \B 5'10001 + connect \Y $eq$build/ls180/gateware/ls180.v:5687$1375_Y + end + attribute \src "build/ls180/gateware/ls180.v:5688.107-5688.152" + cell $eq $eq$build/ls180/gateware/ls180.v:5688$1379 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \builder_interface4_bank_bus_adr [5:0] + connect \B 5'10001 + connect \Y $eq$build/ls180/gateware/ls180.v:5688$1379_Y + end + attribute \src "build/ls180/gateware/ls180.v:5690.104-5690.149" + cell $eq $eq$build/ls180/gateware/ls180.v:5690$1382 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \builder_interface4_bank_bus_adr [5:0] + connect \B 5'10010 + connect \Y $eq$build/ls180/gateware/ls180.v:5690$1382_Y + end + attribute \src "build/ls180/gateware/ls180.v:5691.107-5691.152" + cell $eq $eq$build/ls180/gateware/ls180.v:5691$1386 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \builder_interface4_bank_bus_adr [5:0] + connect \B 5'10010 + connect \Y $eq$build/ls180/gateware/ls180.v:5691$1386_Y + end + attribute \src "build/ls180/gateware/ls180.v:5693.104-5693.149" + cell $eq $eq$build/ls180/gateware/ls180.v:5693$1389 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \builder_interface4_bank_bus_adr [5:0] + connect \B 5'10011 + connect \Y $eq$build/ls180/gateware/ls180.v:5693$1389_Y + end + attribute \src "build/ls180/gateware/ls180.v:5694.107-5694.152" + cell $eq $eq$build/ls180/gateware/ls180.v:5694$1393 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \builder_interface4_bank_bus_adr [5:0] + connect \B 5'10011 + connect \Y $eq$build/ls180/gateware/ls180.v:5694$1393_Y + end + attribute \src "build/ls180/gateware/ls180.v:5696.104-5696.149" + cell $eq $eq$build/ls180/gateware/ls180.v:5696$1396 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \builder_interface4_bank_bus_adr [5:0] + connect \B 5'10100 + connect \Y $eq$build/ls180/gateware/ls180.v:5696$1396_Y + end + attribute \src "build/ls180/gateware/ls180.v:5697.107-5697.152" + cell $eq $eq$build/ls180/gateware/ls180.v:5697$1400 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \builder_interface4_bank_bus_adr [5:0] + connect \B 5'10100 + connect \Y $eq$build/ls180/gateware/ls180.v:5697$1400_Y + end + attribute \src "build/ls180/gateware/ls180.v:5699.104-5699.149" + cell $eq $eq$build/ls180/gateware/ls180.v:5699$1403 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \builder_interface4_bank_bus_adr [5:0] + connect \B 5'10101 + connect \Y $eq$build/ls180/gateware/ls180.v:5699$1403_Y + end + attribute \src "build/ls180/gateware/ls180.v:5700.107-5700.152" + cell $eq $eq$build/ls180/gateware/ls180.v:5700$1407 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \builder_interface4_bank_bus_adr [5:0] + connect \B 5'10101 + connect \Y $eq$build/ls180/gateware/ls180.v:5700$1407_Y + end + attribute \src "build/ls180/gateware/ls180.v:5702.104-5702.149" + cell $eq $eq$build/ls180/gateware/ls180.v:5702$1410 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \builder_interface4_bank_bus_adr [5:0] + connect \B 5'10110 + connect \Y $eq$build/ls180/gateware/ls180.v:5702$1410_Y + end + attribute \src "build/ls180/gateware/ls180.v:5703.107-5703.152" + cell $eq $eq$build/ls180/gateware/ls180.v:5703$1414 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \builder_interface4_bank_bus_adr [5:0] + connect \B 5'10110 + connect \Y $eq$build/ls180/gateware/ls180.v:5703$1414_Y + end + attribute \src "build/ls180/gateware/ls180.v:5705.104-5705.149" + cell $eq $eq$build/ls180/gateware/ls180.v:5705$1417 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \builder_interface4_bank_bus_adr [5:0] + connect \B 5'10111 + connect \Y $eq$build/ls180/gateware/ls180.v:5705$1417_Y + end + attribute \src "build/ls180/gateware/ls180.v:5706.107-5706.152" + cell $eq $eq$build/ls180/gateware/ls180.v:5706$1421 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \builder_interface4_bank_bus_adr [5:0] + connect \B 5'10111 + connect \Y $eq$build/ls180/gateware/ls180.v:5706$1421_Y + end + attribute \src "build/ls180/gateware/ls180.v:5708.104-5708.149" + cell $eq $eq$build/ls180/gateware/ls180.v:5708$1424 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \builder_interface4_bank_bus_adr [5:0] + connect \B 5'11000 + connect \Y $eq$build/ls180/gateware/ls180.v:5708$1424_Y + end + attribute \src "build/ls180/gateware/ls180.v:5709.107-5709.152" + cell $eq $eq$build/ls180/gateware/ls180.v:5709$1428 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \builder_interface4_bank_bus_adr [5:0] + connect \B 5'11000 + connect \Y $eq$build/ls180/gateware/ls180.v:5709$1428_Y + end + attribute \src "build/ls180/gateware/ls180.v:5711.100-5711.145" + cell $eq $eq$build/ls180/gateware/ls180.v:5711$1431 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \builder_interface4_bank_bus_adr [5:0] + connect \B 5'11001 + connect \Y $eq$build/ls180/gateware/ls180.v:5711$1431_Y + end + attribute \src "build/ls180/gateware/ls180.v:5712.103-5712.148" + cell $eq $eq$build/ls180/gateware/ls180.v:5712$1435 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \builder_interface4_bank_bus_adr [5:0] + connect \B 5'11001 + connect \Y $eq$build/ls180/gateware/ls180.v:5712$1435_Y + end + attribute \src "build/ls180/gateware/ls180.v:5714.101-5714.146" + cell $eq $eq$build/ls180/gateware/ls180.v:5714$1438 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \builder_interface4_bank_bus_adr [5:0] + connect \B 5'11010 + connect \Y $eq$build/ls180/gateware/ls180.v:5714$1438_Y + end + attribute \src "build/ls180/gateware/ls180.v:5715.104-5715.149" + cell $eq $eq$build/ls180/gateware/ls180.v:5715$1442 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \builder_interface4_bank_bus_adr [5:0] + connect \B 5'11010 + connect \Y $eq$build/ls180/gateware/ls180.v:5715$1442_Y + end + attribute \src "build/ls180/gateware/ls180.v:5717.104-5717.149" + cell $eq $eq$build/ls180/gateware/ls180.v:5717$1445 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \builder_interface4_bank_bus_adr [5:0] + connect \B 5'11011 + connect \Y $eq$build/ls180/gateware/ls180.v:5717$1445_Y + end + attribute \src "build/ls180/gateware/ls180.v:5718.107-5718.152" + cell $eq $eq$build/ls180/gateware/ls180.v:5718$1449 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \builder_interface4_bank_bus_adr [5:0] + connect \B 5'11011 + connect \Y $eq$build/ls180/gateware/ls180.v:5718$1449_Y + end + attribute \src "build/ls180/gateware/ls180.v:5720.104-5720.149" + cell $eq $eq$build/ls180/gateware/ls180.v:5720$1452 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \builder_interface4_bank_bus_adr [5:0] + connect \B 5'11100 + connect \Y $eq$build/ls180/gateware/ls180.v:5720$1452_Y + end + attribute \src "build/ls180/gateware/ls180.v:5721.107-5721.152" + cell $eq $eq$build/ls180/gateware/ls180.v:5721$1456 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \builder_interface4_bank_bus_adr [5:0] + connect \B 5'11100 + connect \Y $eq$build/ls180/gateware/ls180.v:5721$1456_Y + end + attribute \src "build/ls180/gateware/ls180.v:5723.103-5723.148" + cell $eq $eq$build/ls180/gateware/ls180.v:5723$1459 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \builder_interface4_bank_bus_adr [5:0] + connect \B 5'11101 + connect \Y $eq$build/ls180/gateware/ls180.v:5723$1459_Y + end + attribute \src "build/ls180/gateware/ls180.v:5724.106-5724.151" + cell $eq $eq$build/ls180/gateware/ls180.v:5724$1463 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \builder_interface4_bank_bus_adr [5:0] + connect \B 5'11101 + connect \Y $eq$build/ls180/gateware/ls180.v:5724$1463_Y + end + attribute \src "build/ls180/gateware/ls180.v:5726.103-5726.148" + cell $eq $eq$build/ls180/gateware/ls180.v:5726$1466 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \builder_interface4_bank_bus_adr [5:0] + connect \B 5'11110 + connect \Y $eq$build/ls180/gateware/ls180.v:5726$1466_Y + end + attribute \src "build/ls180/gateware/ls180.v:5727.106-5727.151" + cell $eq $eq$build/ls180/gateware/ls180.v:5727$1470 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \builder_interface4_bank_bus_adr [5:0] + connect \B 5'11110 + connect \Y $eq$build/ls180/gateware/ls180.v:5727$1470_Y + end + attribute \src "build/ls180/gateware/ls180.v:5729.103-5729.148" + cell $eq $eq$build/ls180/gateware/ls180.v:5729$1473 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \builder_interface4_bank_bus_adr [5:0] + connect \B 5'11111 + connect \Y $eq$build/ls180/gateware/ls180.v:5729$1473_Y + end + attribute \src "build/ls180/gateware/ls180.v:5730.106-5730.151" + cell $eq $eq$build/ls180/gateware/ls180.v:5730$1477 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \builder_interface4_bank_bus_adr [5:0] + connect \B 5'11111 + connect \Y $eq$build/ls180/gateware/ls180.v:5730$1477_Y + end + attribute \src "build/ls180/gateware/ls180.v:5732.103-5732.148" + cell $eq $eq$build/ls180/gateware/ls180.v:5732$1480 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \builder_interface4_bank_bus_adr [5:0] + connect \B 6'100000 + connect \Y $eq$build/ls180/gateware/ls180.v:5732$1480_Y + end + attribute \src "build/ls180/gateware/ls180.v:5733.106-5733.151" + cell $eq $eq$build/ls180/gateware/ls180.v:5733$1484 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \builder_interface4_bank_bus_adr [5:0] + connect \B 6'100000 + connect \Y $eq$build/ls180/gateware/ls180.v:5733$1484_Y + end + attribute \src "build/ls180/gateware/ls180.v:5769.32-5769.78" + cell $eq $eq$build/ls180/gateware/ls180.v:5769$1486 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_adr [13:9] + connect \B 4'1100 + connect \Y $eq$build/ls180/gateware/ls180.v:5769$1486_Y + end + attribute \src "build/ls180/gateware/ls180.v:5771.100-5771.144" + cell $eq $eq$build/ls180/gateware/ls180.v:5771$1488 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_adr [4:0] + connect \B 1'0 + connect \Y $eq$build/ls180/gateware/ls180.v:5771$1488_Y + end + attribute \src "build/ls180/gateware/ls180.v:5772.103-5772.147" + cell $eq $eq$build/ls180/gateware/ls180.v:5772$1492 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_adr [4:0] + connect \B 1'0 + connect \Y $eq$build/ls180/gateware/ls180.v:5772$1492_Y + end + attribute \src "build/ls180/gateware/ls180.v:5774.100-5774.144" + cell $eq $eq$build/ls180/gateware/ls180.v:5774$1495 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_adr [4:0] + connect \B 1'1 + connect \Y $eq$build/ls180/gateware/ls180.v:5774$1495_Y + end + attribute \src "build/ls180/gateware/ls180.v:5775.103-5775.147" + cell $eq $eq$build/ls180/gateware/ls180.v:5775$1499 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_adr [4:0] + connect \B 1'1 + connect \Y $eq$build/ls180/gateware/ls180.v:5775$1499_Y + end + attribute \src "build/ls180/gateware/ls180.v:5777.100-5777.144" + cell $eq $eq$build/ls180/gateware/ls180.v:5777$1502 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_adr [4:0] + connect \B 2'10 + connect \Y $eq$build/ls180/gateware/ls180.v:5777$1502_Y + end + attribute \src "build/ls180/gateware/ls180.v:5778.103-5778.147" + cell $eq $eq$build/ls180/gateware/ls180.v:5778$1506 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_adr [4:0] + connect \B 2'10 + connect \Y $eq$build/ls180/gateware/ls180.v:5778$1506_Y + end + attribute \src "build/ls180/gateware/ls180.v:5780.100-5780.144" + cell $eq $eq$build/ls180/gateware/ls180.v:5780$1509 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_adr [4:0] + connect \B 2'11 + connect \Y $eq$build/ls180/gateware/ls180.v:5780$1509_Y + end + attribute \src "build/ls180/gateware/ls180.v:5781.103-5781.147" + cell $eq $eq$build/ls180/gateware/ls180.v:5781$1513 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_adr [4:0] + connect \B 2'11 + connect \Y $eq$build/ls180/gateware/ls180.v:5781$1513_Y + end + attribute \src "build/ls180/gateware/ls180.v:5783.100-5783.144" + cell $eq $eq$build/ls180/gateware/ls180.v:5783$1516 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_adr [4:0] + connect \B 3'100 + connect \Y $eq$build/ls180/gateware/ls180.v:5783$1516_Y + end + attribute \src "build/ls180/gateware/ls180.v:5784.103-5784.147" + cell $eq $eq$build/ls180/gateware/ls180.v:5784$1520 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_adr [4:0] + connect \B 3'100 + connect \Y $eq$build/ls180/gateware/ls180.v:5784$1520_Y + end + attribute \src "build/ls180/gateware/ls180.v:5786.100-5786.144" + cell $eq $eq$build/ls180/gateware/ls180.v:5786$1523 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_adr [4:0] + connect \B 3'101 + connect \Y $eq$build/ls180/gateware/ls180.v:5786$1523_Y + end + attribute \src "build/ls180/gateware/ls180.v:5787.103-5787.147" + cell $eq $eq$build/ls180/gateware/ls180.v:5787$1527 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_adr [4:0] + connect \B 3'101 + connect \Y $eq$build/ls180/gateware/ls180.v:5787$1527_Y + end + attribute \src "build/ls180/gateware/ls180.v:5789.100-5789.144" + cell $eq $eq$build/ls180/gateware/ls180.v:5789$1530 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_adr [4:0] + connect \B 3'110 + connect \Y $eq$build/ls180/gateware/ls180.v:5789$1530_Y + end + attribute \src "build/ls180/gateware/ls180.v:5790.103-5790.147" + cell $eq $eq$build/ls180/gateware/ls180.v:5790$1534 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_adr [4:0] + connect \B 3'110 + connect \Y $eq$build/ls180/gateware/ls180.v:5790$1534_Y + end + attribute \src "build/ls180/gateware/ls180.v:5792.100-5792.144" + cell $eq $eq$build/ls180/gateware/ls180.v:5792$1537 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_adr [4:0] + connect \B 3'111 + connect \Y $eq$build/ls180/gateware/ls180.v:5792$1537_Y + end + attribute \src "build/ls180/gateware/ls180.v:5793.103-5793.147" + cell $eq $eq$build/ls180/gateware/ls180.v:5793$1541 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_adr [4:0] + connect \B 3'111 + connect \Y $eq$build/ls180/gateware/ls180.v:5793$1541_Y + end + attribute \src "build/ls180/gateware/ls180.v:5795.102-5795.146" + cell $eq $eq$build/ls180/gateware/ls180.v:5795$1544 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_adr [4:0] + connect \B 4'1000 + connect \Y $eq$build/ls180/gateware/ls180.v:5795$1544_Y + end + attribute \src "build/ls180/gateware/ls180.v:5796.105-5796.149" + cell $eq $eq$build/ls180/gateware/ls180.v:5796$1548 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_adr [4:0] + connect \B 4'1000 + connect \Y $eq$build/ls180/gateware/ls180.v:5796$1548_Y + end + attribute \src "build/ls180/gateware/ls180.v:5798.102-5798.146" + cell $eq $eq$build/ls180/gateware/ls180.v:5798$1551 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_adr [4:0] + connect \B 4'1001 + connect \Y $eq$build/ls180/gateware/ls180.v:5798$1551_Y + end + attribute \src "build/ls180/gateware/ls180.v:5799.105-5799.149" + cell $eq $eq$build/ls180/gateware/ls180.v:5799$1555 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_adr [4:0] + connect \B 4'1001 + connect \Y $eq$build/ls180/gateware/ls180.v:5799$1555_Y + end + attribute \src "build/ls180/gateware/ls180.v:5801.102-5801.147" + cell $eq $eq$build/ls180/gateware/ls180.v:5801$1558 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_adr [4:0] + connect \B 4'1010 + connect \Y $eq$build/ls180/gateware/ls180.v:5801$1558_Y + end + attribute \src "build/ls180/gateware/ls180.v:5802.105-5802.150" + cell $eq $eq$build/ls180/gateware/ls180.v:5802$1562 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_adr [4:0] + connect \B 4'1010 + connect \Y $eq$build/ls180/gateware/ls180.v:5802$1562_Y + end + attribute \src "build/ls180/gateware/ls180.v:5804.102-5804.147" + cell $eq $eq$build/ls180/gateware/ls180.v:5804$1565 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_adr [4:0] + connect \B 4'1011 + connect \Y $eq$build/ls180/gateware/ls180.v:5804$1565_Y + end + attribute \src "build/ls180/gateware/ls180.v:5805.105-5805.150" + cell $eq $eq$build/ls180/gateware/ls180.v:5805$1569 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_adr [4:0] + connect \B 4'1011 + connect \Y $eq$build/ls180/gateware/ls180.v:5805$1569_Y + end + attribute \src "build/ls180/gateware/ls180.v:5807.102-5807.147" + cell $eq $eq$build/ls180/gateware/ls180.v:5807$1572 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_adr [4:0] + connect \B 4'1100 + connect \Y $eq$build/ls180/gateware/ls180.v:5807$1572_Y + end + attribute \src "build/ls180/gateware/ls180.v:5808.105-5808.150" + cell $eq $eq$build/ls180/gateware/ls180.v:5808$1576 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_adr [4:0] + connect \B 4'1100 + connect \Y $eq$build/ls180/gateware/ls180.v:5808$1576_Y + end + attribute \src "build/ls180/gateware/ls180.v:5810.99-5810.144" + cell $eq $eq$build/ls180/gateware/ls180.v:5810$1579 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_adr [4:0] + connect \B 4'1101 + connect \Y $eq$build/ls180/gateware/ls180.v:5810$1579_Y + end + attribute \src "build/ls180/gateware/ls180.v:5811.102-5811.147" + cell $eq $eq$build/ls180/gateware/ls180.v:5811$1583 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_adr [4:0] + connect \B 4'1101 + connect \Y $eq$build/ls180/gateware/ls180.v:5811$1583_Y + end + attribute \src "build/ls180/gateware/ls180.v:5813.100-5813.145" + cell $eq $eq$build/ls180/gateware/ls180.v:5813$1586 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_adr [4:0] + connect \B 4'1110 + connect \Y $eq$build/ls180/gateware/ls180.v:5813$1586_Y + end + attribute \src "build/ls180/gateware/ls180.v:5814.103-5814.148" + cell $eq $eq$build/ls180/gateware/ls180.v:5814$1590 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_adr [4:0] + connect \B 4'1110 + connect \Y $eq$build/ls180/gateware/ls180.v:5814$1590_Y + end + attribute \src "build/ls180/gateware/ls180.v:5816.102-5816.147" + cell $eq $eq$build/ls180/gateware/ls180.v:5816$1593 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_adr [4:0] + connect \B 4'1111 + connect \Y $eq$build/ls180/gateware/ls180.v:5816$1593_Y + end + attribute \src "build/ls180/gateware/ls180.v:5817.105-5817.150" + cell $eq $eq$build/ls180/gateware/ls180.v:5817$1597 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_adr [4:0] + connect \B 4'1111 + connect \Y $eq$build/ls180/gateware/ls180.v:5817$1597_Y + end + attribute \src "build/ls180/gateware/ls180.v:5819.102-5819.147" + cell $eq $eq$build/ls180/gateware/ls180.v:5819$1600 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_adr [4:0] + connect \B 5'10000 + connect \Y $eq$build/ls180/gateware/ls180.v:5819$1600_Y + end + attribute \src "build/ls180/gateware/ls180.v:5820.105-5820.150" + cell $eq $eq$build/ls180/gateware/ls180.v:5820$1604 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_adr [4:0] + connect \B 5'10000 + connect \Y $eq$build/ls180/gateware/ls180.v:5820$1604_Y + end + attribute \src "build/ls180/gateware/ls180.v:5822.102-5822.147" + cell $eq $eq$build/ls180/gateware/ls180.v:5822$1607 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_adr [4:0] + connect \B 5'10001 + connect \Y $eq$build/ls180/gateware/ls180.v:5822$1607_Y + end + attribute \src "build/ls180/gateware/ls180.v:5823.105-5823.150" + cell $eq $eq$build/ls180/gateware/ls180.v:5823$1611 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_adr [4:0] + connect \B 5'10001 + connect \Y $eq$build/ls180/gateware/ls180.v:5823$1611_Y + end + attribute \src "build/ls180/gateware/ls180.v:5825.102-5825.147" + cell $eq $eq$build/ls180/gateware/ls180.v:5825$1614 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_adr [4:0] + connect \B 5'10010 + connect \Y $eq$build/ls180/gateware/ls180.v:5825$1614_Y + end + attribute \src "build/ls180/gateware/ls180.v:5826.105-5826.150" + cell $eq $eq$build/ls180/gateware/ls180.v:5826$1618 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_adr [4:0] + connect \B 5'10010 + connect \Y $eq$build/ls180/gateware/ls180.v:5826$1618_Y + end + attribute \src "build/ls180/gateware/ls180.v:5848.32-5848.77" + cell $eq $eq$build/ls180/gateware/ls180.v:5848$1620 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [13:9] + connect \B 4'1001 + connect \Y $eq$build/ls180/gateware/ls180.v:5848$1620_Y + end + attribute \src "build/ls180/gateware/ls180.v:5850.102-5850.146" + cell $eq $eq$build/ls180/gateware/ls180.v:5850$1622 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [1:0] + connect \B 1'0 + connect \Y $eq$build/ls180/gateware/ls180.v:5850$1622_Y + end + attribute \src "build/ls180/gateware/ls180.v:5851.105-5851.149" + cell $eq $eq$build/ls180/gateware/ls180.v:5851$1626 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [1:0] + connect \B 1'0 + connect \Y $eq$build/ls180/gateware/ls180.v:5851$1626_Y + end + attribute \src "build/ls180/gateware/ls180.v:5853.107-5853.151" + cell $eq $eq$build/ls180/gateware/ls180.v:5853$1629 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [1:0] + connect \B 1'1 + connect \Y $eq$build/ls180/gateware/ls180.v:5853$1629_Y + end + attribute \src "build/ls180/gateware/ls180.v:5854.110-5854.154" + cell $eq $eq$build/ls180/gateware/ls180.v:5854$1633 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [1:0] + connect \B 1'1 + connect \Y $eq$build/ls180/gateware/ls180.v:5854$1633_Y + end + attribute \src "build/ls180/gateware/ls180.v:5856.107-5856.151" + cell $eq $eq$build/ls180/gateware/ls180.v:5856$1636 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [1:0] + connect \B 2'10 + connect \Y $eq$build/ls180/gateware/ls180.v:5856$1636_Y + end + attribute \src "build/ls180/gateware/ls180.v:5857.110-5857.154" + cell $eq $eq$build/ls180/gateware/ls180.v:5857$1640 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [1:0] + connect \B 2'10 + connect \Y $eq$build/ls180/gateware/ls180.v:5857$1640_Y + end + attribute \src "build/ls180/gateware/ls180.v:5859.101-5859.145" + cell $eq $eq$build/ls180/gateware/ls180.v:5859$1643 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [1:0] + connect \B 2'11 + connect \Y $eq$build/ls180/gateware/ls180.v:5859$1643_Y + end + attribute \src "build/ls180/gateware/ls180.v:5860.104-5860.148" + cell $eq $eq$build/ls180/gateware/ls180.v:5860$1647 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_adr [1:0] + connect \B 2'11 + connect \Y $eq$build/ls180/gateware/ls180.v:5860$1647_Y + end + attribute \src "build/ls180/gateware/ls180.v:5865.32-5865.77" + cell $eq $eq$build/ls180/gateware/ls180.v:5865$1649 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface7_bank_bus_adr [13:9] + connect \B 3'101 + connect \Y $eq$build/ls180/gateware/ls180.v:5865$1649_Y + end + attribute \src "build/ls180/gateware/ls180.v:5867.104-5867.148" + cell $eq $eq$build/ls180/gateware/ls180.v:5867$1651 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface7_bank_bus_adr [3:0] + connect \B 1'0 + connect \Y $eq$build/ls180/gateware/ls180.v:5867$1651_Y + end + attribute \src "build/ls180/gateware/ls180.v:5868.107-5868.151" + cell $eq $eq$build/ls180/gateware/ls180.v:5868$1655 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface7_bank_bus_adr [3:0] + connect \B 1'0 + connect \Y $eq$build/ls180/gateware/ls180.v:5868$1655_Y + end + attribute \src "build/ls180/gateware/ls180.v:5870.108-5870.152" + cell $eq $eq$build/ls180/gateware/ls180.v:5870$1658 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface7_bank_bus_adr [3:0] + connect \B 1'1 + connect \Y $eq$build/ls180/gateware/ls180.v:5870$1658_Y + end + attribute \src "build/ls180/gateware/ls180.v:5871.111-5871.155" + cell $eq $eq$build/ls180/gateware/ls180.v:5871$1662 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface7_bank_bus_adr [3:0] + connect \B 1'1 + connect \Y $eq$build/ls180/gateware/ls180.v:5871$1662_Y + end + attribute \src "build/ls180/gateware/ls180.v:5873.98-5873.142" + cell $eq $eq$build/ls180/gateware/ls180.v:5873$1665 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface7_bank_bus_adr [3:0] + connect \B 2'10 + connect \Y $eq$build/ls180/gateware/ls180.v:5873$1665_Y + end + attribute \src "build/ls180/gateware/ls180.v:5874.101-5874.145" + cell $eq $eq$build/ls180/gateware/ls180.v:5874$1669 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface7_bank_bus_adr [3:0] + connect \B 2'10 + connect \Y $eq$build/ls180/gateware/ls180.v:5874$1669_Y + end + attribute \src "build/ls180/gateware/ls180.v:5876.108-5876.152" + cell $eq $eq$build/ls180/gateware/ls180.v:5876$1672 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface7_bank_bus_adr [3:0] + connect \B 2'11 + connect \Y $eq$build/ls180/gateware/ls180.v:5876$1672_Y + end + attribute \src "build/ls180/gateware/ls180.v:5877.111-5877.155" + cell $eq $eq$build/ls180/gateware/ls180.v:5877$1676 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface7_bank_bus_adr [3:0] + connect \B 2'11 + connect \Y $eq$build/ls180/gateware/ls180.v:5877$1676_Y + end + attribute \src "build/ls180/gateware/ls180.v:5879.108-5879.152" + cell $eq $eq$build/ls180/gateware/ls180.v:5879$1679 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface7_bank_bus_adr [3:0] + connect \B 3'100 + connect \Y $eq$build/ls180/gateware/ls180.v:5879$1679_Y + end + attribute \src "build/ls180/gateware/ls180.v:5880.111-5880.155" + cell $eq $eq$build/ls180/gateware/ls180.v:5880$1683 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface7_bank_bus_adr [3:0] + connect \B 3'100 + connect \Y $eq$build/ls180/gateware/ls180.v:5880$1683_Y + end + attribute \src "build/ls180/gateware/ls180.v:5882.109-5882.153" + cell $eq $eq$build/ls180/gateware/ls180.v:5882$1686 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface7_bank_bus_adr [3:0] + connect \B 3'101 + connect \Y $eq$build/ls180/gateware/ls180.v:5882$1686_Y + end + attribute \src "build/ls180/gateware/ls180.v:5883.112-5883.156" + cell $eq $eq$build/ls180/gateware/ls180.v:5883$1690 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface7_bank_bus_adr [3:0] + connect \B 3'101 + connect \Y $eq$build/ls180/gateware/ls180.v:5883$1690_Y + end + attribute \src "build/ls180/gateware/ls180.v:5885.107-5885.151" + cell $eq $eq$build/ls180/gateware/ls180.v:5885$1693 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface7_bank_bus_adr [3:0] + connect \B 3'110 + connect \Y $eq$build/ls180/gateware/ls180.v:5885$1693_Y + end + attribute \src "build/ls180/gateware/ls180.v:5886.110-5886.154" + cell $eq $eq$build/ls180/gateware/ls180.v:5886$1697 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface7_bank_bus_adr [3:0] + connect \B 3'110 + connect \Y $eq$build/ls180/gateware/ls180.v:5886$1697_Y + end + attribute \src "build/ls180/gateware/ls180.v:5888.107-5888.151" + cell $eq $eq$build/ls180/gateware/ls180.v:5888$1700 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface7_bank_bus_adr [3:0] + connect \B 3'111 + connect \Y $eq$build/ls180/gateware/ls180.v:5888$1700_Y + end + attribute \src "build/ls180/gateware/ls180.v:5889.110-5889.154" + cell $eq $eq$build/ls180/gateware/ls180.v:5889$1704 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface7_bank_bus_adr [3:0] + connect \B 3'111 + connect \Y $eq$build/ls180/gateware/ls180.v:5889$1704_Y + end + attribute \src "build/ls180/gateware/ls180.v:5891.107-5891.151" + cell $eq $eq$build/ls180/gateware/ls180.v:5891$1707 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface7_bank_bus_adr [3:0] + connect \B 4'1000 + connect \Y $eq$build/ls180/gateware/ls180.v:5891$1707_Y + end + attribute \src "build/ls180/gateware/ls180.v:5892.110-5892.154" + cell $eq $eq$build/ls180/gateware/ls180.v:5892$1711 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface7_bank_bus_adr [3:0] + connect \B 4'1000 + connect \Y $eq$build/ls180/gateware/ls180.v:5892$1711_Y + end + attribute \src "build/ls180/gateware/ls180.v:5894.107-5894.151" + cell $eq $eq$build/ls180/gateware/ls180.v:5894$1714 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface7_bank_bus_adr [3:0] + connect \B 4'1001 + connect \Y $eq$build/ls180/gateware/ls180.v:5894$1714_Y + end + attribute \src "build/ls180/gateware/ls180.v:5895.110-5895.154" + cell $eq $eq$build/ls180/gateware/ls180.v:5895$1718 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface7_bank_bus_adr [3:0] + connect \B 4'1001 + connect \Y $eq$build/ls180/gateware/ls180.v:5895$1718_Y + end + attribute \src "build/ls180/gateware/ls180.v:5910.32-5910.77" + cell $eq $eq$build/ls180/gateware/ls180.v:5910$1720 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface8_bank_bus_adr [13:9] + connect \B 4'1000 + connect \Y $eq$build/ls180/gateware/ls180.v:5910$1720_Y + end + attribute \src "build/ls180/gateware/ls180.v:5912.99-5912.143" + cell $eq $eq$build/ls180/gateware/ls180.v:5912$1722 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface8_bank_bus_adr [2:0] + connect \B 1'0 + connect \Y $eq$build/ls180/gateware/ls180.v:5912$1722_Y + end + attribute \src "build/ls180/gateware/ls180.v:5913.102-5913.146" + cell $eq $eq$build/ls180/gateware/ls180.v:5913$1726 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface8_bank_bus_adr [2:0] + connect \B 1'0 + connect \Y $eq$build/ls180/gateware/ls180.v:5913$1726_Y + end + attribute \src "build/ls180/gateware/ls180.v:5915.99-5915.143" + cell $eq $eq$build/ls180/gateware/ls180.v:5915$1729 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface8_bank_bus_adr [2:0] + connect \B 1'1 + connect \Y $eq$build/ls180/gateware/ls180.v:5915$1729_Y + end + attribute \src "build/ls180/gateware/ls180.v:5916.102-5916.146" + cell $eq $eq$build/ls180/gateware/ls180.v:5916$1733 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface8_bank_bus_adr [2:0] + connect \B 1'1 + connect \Y $eq$build/ls180/gateware/ls180.v:5916$1733_Y + end + attribute \src "build/ls180/gateware/ls180.v:5918.97-5918.141" + cell $eq $eq$build/ls180/gateware/ls180.v:5918$1736 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface8_bank_bus_adr [2:0] + connect \B 2'10 + connect \Y $eq$build/ls180/gateware/ls180.v:5918$1736_Y + end + attribute \src "build/ls180/gateware/ls180.v:5919.100-5919.144" + cell $eq $eq$build/ls180/gateware/ls180.v:5919$1740 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface8_bank_bus_adr [2:0] + connect \B 2'10 + connect \Y $eq$build/ls180/gateware/ls180.v:5919$1740_Y + end + attribute \src "build/ls180/gateware/ls180.v:5921.96-5921.140" + cell $eq $eq$build/ls180/gateware/ls180.v:5921$1743 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface8_bank_bus_adr [2:0] + connect \B 2'11 + connect \Y $eq$build/ls180/gateware/ls180.v:5921$1743_Y + end + attribute \src "build/ls180/gateware/ls180.v:5922.99-5922.143" + cell $eq $eq$build/ls180/gateware/ls180.v:5922$1747 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface8_bank_bus_adr [2:0] + connect \B 2'11 + connect \Y $eq$build/ls180/gateware/ls180.v:5922$1747_Y + end + attribute \src "build/ls180/gateware/ls180.v:5924.95-5924.139" + cell $eq $eq$build/ls180/gateware/ls180.v:5924$1750 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface8_bank_bus_adr [2:0] + connect \B 3'100 + connect \Y $eq$build/ls180/gateware/ls180.v:5924$1750_Y + end + attribute \src "build/ls180/gateware/ls180.v:5925.98-5925.142" + cell $eq $eq$build/ls180/gateware/ls180.v:5925$1754 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface8_bank_bus_adr [2:0] + connect \B 3'100 + connect \Y $eq$build/ls180/gateware/ls180.v:5925$1754_Y + end + attribute \src "build/ls180/gateware/ls180.v:5927.94-5927.138" + cell $eq $eq$build/ls180/gateware/ls180.v:5927$1757 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface8_bank_bus_adr [2:0] + connect \B 3'101 + connect \Y $eq$build/ls180/gateware/ls180.v:5927$1757_Y + end + attribute \src "build/ls180/gateware/ls180.v:5928.97-5928.141" + cell $eq $eq$build/ls180/gateware/ls180.v:5928$1761 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface8_bank_bus_adr [2:0] + connect \B 3'101 + connect \Y $eq$build/ls180/gateware/ls180.v:5928$1761_Y + end + attribute \src "build/ls180/gateware/ls180.v:5930.100-5930.144" + cell $eq $eq$build/ls180/gateware/ls180.v:5930$1764 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface8_bank_bus_adr [2:0] + connect \B 3'110 + connect \Y $eq$build/ls180/gateware/ls180.v:5930$1764_Y + end + attribute \src "build/ls180/gateware/ls180.v:5931.103-5931.147" + cell $eq $eq$build/ls180/gateware/ls180.v:5931$1768 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface8_bank_bus_adr [2:0] + connect \B 3'110 + connect \Y $eq$build/ls180/gateware/ls180.v:5931$1768_Y + end + attribute \src "build/ls180/gateware/ls180.v:5950.32-5950.78" + cell $eq $eq$build/ls180/gateware/ls180.v:5950$1771 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface9_bank_bus_adr [13:9] + connect \B 4'1101 + connect \Y $eq$build/ls180/gateware/ls180.v:5950$1771_Y + end + attribute \src "build/ls180/gateware/ls180.v:5952.99-5952.143" + cell $eq $eq$build/ls180/gateware/ls180.v:5952$1773 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface9_bank_bus_adr [3:0] + connect \B 1'0 + connect \Y $eq$build/ls180/gateware/ls180.v:5952$1773_Y + end + attribute \src "build/ls180/gateware/ls180.v:5953.102-5953.146" + cell $eq $eq$build/ls180/gateware/ls180.v:5953$1777 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface9_bank_bus_adr [3:0] + connect \B 1'0 + connect \Y $eq$build/ls180/gateware/ls180.v:5953$1777_Y + end + attribute \src "build/ls180/gateware/ls180.v:5955.99-5955.143" + cell $eq $eq$build/ls180/gateware/ls180.v:5955$1780 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface9_bank_bus_adr [3:0] + connect \B 1'1 + connect \Y $eq$build/ls180/gateware/ls180.v:5955$1780_Y + end + attribute \src "build/ls180/gateware/ls180.v:5956.102-5956.146" + cell $eq $eq$build/ls180/gateware/ls180.v:5956$1784 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface9_bank_bus_adr [3:0] + connect \B 1'1 + connect \Y $eq$build/ls180/gateware/ls180.v:5956$1784_Y + end + attribute \src "build/ls180/gateware/ls180.v:5958.97-5958.141" + cell $eq $eq$build/ls180/gateware/ls180.v:5958$1787 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface9_bank_bus_adr [3:0] + connect \B 2'10 + connect \Y $eq$build/ls180/gateware/ls180.v:5958$1787_Y + end + attribute \src "build/ls180/gateware/ls180.v:5959.100-5959.144" + cell $eq $eq$build/ls180/gateware/ls180.v:5959$1791 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface9_bank_bus_adr [3:0] + connect \B 2'10 + connect \Y $eq$build/ls180/gateware/ls180.v:5959$1791_Y + end + attribute \src "build/ls180/gateware/ls180.v:5961.96-5961.140" + cell $eq $eq$build/ls180/gateware/ls180.v:5961$1794 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface9_bank_bus_adr [3:0] + connect \B 2'11 + connect \Y $eq$build/ls180/gateware/ls180.v:5961$1794_Y + end + attribute \src "build/ls180/gateware/ls180.v:5962.99-5962.143" + cell $eq $eq$build/ls180/gateware/ls180.v:5962$1798 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface9_bank_bus_adr [3:0] + connect \B 2'11 + connect \Y $eq$build/ls180/gateware/ls180.v:5962$1798_Y + end + attribute \src "build/ls180/gateware/ls180.v:5964.95-5964.139" + cell $eq $eq$build/ls180/gateware/ls180.v:5964$1801 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface9_bank_bus_adr [3:0] + connect \B 3'100 + connect \Y $eq$build/ls180/gateware/ls180.v:5964$1801_Y + end + attribute \src "build/ls180/gateware/ls180.v:5965.98-5965.142" + cell $eq $eq$build/ls180/gateware/ls180.v:5965$1805 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface9_bank_bus_adr [3:0] + connect \B 3'100 + connect \Y $eq$build/ls180/gateware/ls180.v:5965$1805_Y + end + attribute \src "build/ls180/gateware/ls180.v:5967.94-5967.138" + cell $eq $eq$build/ls180/gateware/ls180.v:5967$1808 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface9_bank_bus_adr [3:0] + connect \B 3'101 + connect \Y $eq$build/ls180/gateware/ls180.v:5967$1808_Y + end + attribute \src "build/ls180/gateware/ls180.v:5968.97-5968.141" + cell $eq $eq$build/ls180/gateware/ls180.v:5968$1812 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface9_bank_bus_adr [3:0] + connect \B 3'101 + connect \Y $eq$build/ls180/gateware/ls180.v:5968$1812_Y + end + attribute \src "build/ls180/gateware/ls180.v:5970.100-5970.144" + cell $eq $eq$build/ls180/gateware/ls180.v:5970$1815 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface9_bank_bus_adr [3:0] + connect \B 3'110 + connect \Y $eq$build/ls180/gateware/ls180.v:5970$1815_Y + end + attribute \src "build/ls180/gateware/ls180.v:5971.103-5971.147" + cell $eq $eq$build/ls180/gateware/ls180.v:5971$1819 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface9_bank_bus_adr [3:0] + connect \B 3'110 + connect \Y $eq$build/ls180/gateware/ls180.v:5971$1819_Y + end + attribute \src "build/ls180/gateware/ls180.v:5973.103-5973.147" + cell $eq $eq$build/ls180/gateware/ls180.v:5973$1822 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface9_bank_bus_adr [3:0] + connect \B 3'111 + connect \Y $eq$build/ls180/gateware/ls180.v:5973$1822_Y + end + attribute \src "build/ls180/gateware/ls180.v:5974.106-5974.150" + cell $eq $eq$build/ls180/gateware/ls180.v:5974$1826 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface9_bank_bus_adr [3:0] + connect \B 3'111 + connect \Y $eq$build/ls180/gateware/ls180.v:5974$1826_Y + end + attribute \src "build/ls180/gateware/ls180.v:5976.103-5976.147" + cell $eq $eq$build/ls180/gateware/ls180.v:5976$1829 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface9_bank_bus_adr [3:0] + connect \B 4'1000 + connect \Y $eq$build/ls180/gateware/ls180.v:5976$1829_Y + end + attribute \src "build/ls180/gateware/ls180.v:5977.106-5977.150" + cell $eq $eq$build/ls180/gateware/ls180.v:5977$1833 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface9_bank_bus_adr [3:0] + connect \B 4'1000 + connect \Y $eq$build/ls180/gateware/ls180.v:5977$1833_Y + end + attribute \src "build/ls180/gateware/ls180.v:5998.33-5998.79" + cell $eq $eq$build/ls180/gateware/ls180.v:5998$1836 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface10_bank_bus_adr [13:9] + connect \B 2'11 + connect \Y $eq$build/ls180/gateware/ls180.v:5998$1836_Y + end + attribute \src "build/ls180/gateware/ls180.v:6000.99-6000.144" + cell $eq $eq$build/ls180/gateware/ls180.v:6000$1838 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface10_bank_bus_adr [4:0] + connect \B 1'0 + connect \Y $eq$build/ls180/gateware/ls180.v:6000$1838_Y + end + attribute \src "build/ls180/gateware/ls180.v:6001.102-6001.147" + cell $eq $eq$build/ls180/gateware/ls180.v:6001$1842 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface10_bank_bus_adr [4:0] + connect \B 1'0 + connect \Y $eq$build/ls180/gateware/ls180.v:6001$1842_Y + end + attribute \src "build/ls180/gateware/ls180.v:6003.99-6003.144" + cell $eq $eq$build/ls180/gateware/ls180.v:6003$1845 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface10_bank_bus_adr [4:0] + connect \B 1'1 + connect \Y $eq$build/ls180/gateware/ls180.v:6003$1845_Y + end + attribute \src "build/ls180/gateware/ls180.v:6004.102-6004.147" + cell $eq $eq$build/ls180/gateware/ls180.v:6004$1849 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface10_bank_bus_adr [4:0] + connect \B 1'1 + connect \Y $eq$build/ls180/gateware/ls180.v:6004$1849_Y + end + attribute \src "build/ls180/gateware/ls180.v:6006.99-6006.144" + cell $eq $eq$build/ls180/gateware/ls180.v:6006$1852 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface10_bank_bus_adr [4:0] + connect \B 2'10 + connect \Y $eq$build/ls180/gateware/ls180.v:6006$1852_Y + end + attribute \src "build/ls180/gateware/ls180.v:6007.102-6007.147" + cell $eq $eq$build/ls180/gateware/ls180.v:6007$1856 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface10_bank_bus_adr [4:0] + connect \B 2'10 + connect \Y $eq$build/ls180/gateware/ls180.v:6007$1856_Y + end + attribute \src "build/ls180/gateware/ls180.v:6009.99-6009.144" + cell $eq $eq$build/ls180/gateware/ls180.v:6009$1859 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface10_bank_bus_adr [4:0] + connect \B 2'11 + connect \Y $eq$build/ls180/gateware/ls180.v:6009$1859_Y + end + attribute \src "build/ls180/gateware/ls180.v:6010.102-6010.147" + cell $eq $eq$build/ls180/gateware/ls180.v:6010$1863 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface10_bank_bus_adr [4:0] + connect \B 2'11 + connect \Y $eq$build/ls180/gateware/ls180.v:6010$1863_Y + end + attribute \src "build/ls180/gateware/ls180.v:6012.101-6012.146" + cell $eq $eq$build/ls180/gateware/ls180.v:6012$1866 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface10_bank_bus_adr [4:0] + connect \B 3'100 + connect \Y $eq$build/ls180/gateware/ls180.v:6012$1866_Y + end + attribute \src "build/ls180/gateware/ls180.v:6013.104-6013.149" + cell $eq $eq$build/ls180/gateware/ls180.v:6013$1870 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface10_bank_bus_adr [4:0] + connect \B 3'100 + connect \Y $eq$build/ls180/gateware/ls180.v:6013$1870_Y + end + attribute \src "build/ls180/gateware/ls180.v:6015.101-6015.146" + cell $eq $eq$build/ls180/gateware/ls180.v:6015$1873 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface10_bank_bus_adr [4:0] + connect \B 3'101 + connect \Y $eq$build/ls180/gateware/ls180.v:6015$1873_Y + end + attribute \src "build/ls180/gateware/ls180.v:6016.104-6016.149" + cell $eq $eq$build/ls180/gateware/ls180.v:6016$1877 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface10_bank_bus_adr [4:0] + connect \B 3'101 + connect \Y $eq$build/ls180/gateware/ls180.v:6016$1877_Y + end + attribute \src "build/ls180/gateware/ls180.v:6018.101-6018.146" + cell $eq $eq$build/ls180/gateware/ls180.v:6018$1880 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface10_bank_bus_adr [4:0] + connect \B 3'110 + connect \Y $eq$build/ls180/gateware/ls180.v:6018$1880_Y + end + attribute \src "build/ls180/gateware/ls180.v:6019.104-6019.149" + cell $eq $eq$build/ls180/gateware/ls180.v:6019$1884 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface10_bank_bus_adr [4:0] + connect \B 3'110 + connect \Y $eq$build/ls180/gateware/ls180.v:6019$1884_Y + end + attribute \src "build/ls180/gateware/ls180.v:6021.101-6021.146" + cell $eq $eq$build/ls180/gateware/ls180.v:6021$1887 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface10_bank_bus_adr [4:0] + connect \B 3'111 + connect \Y $eq$build/ls180/gateware/ls180.v:6021$1887_Y + end + attribute \src "build/ls180/gateware/ls180.v:6022.104-6022.149" + cell $eq $eq$build/ls180/gateware/ls180.v:6022$1891 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface10_bank_bus_adr [4:0] + connect \B 3'111 + connect \Y $eq$build/ls180/gateware/ls180.v:6022$1891_Y + end + attribute \src "build/ls180/gateware/ls180.v:6024.97-6024.142" + cell $eq $eq$build/ls180/gateware/ls180.v:6024$1894 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface10_bank_bus_adr [4:0] + connect \B 4'1000 + connect \Y $eq$build/ls180/gateware/ls180.v:6024$1894_Y + end + attribute \src "build/ls180/gateware/ls180.v:6025.100-6025.145" + cell $eq $eq$build/ls180/gateware/ls180.v:6025$1898 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface10_bank_bus_adr [4:0] + connect \B 4'1000 + connect \Y $eq$build/ls180/gateware/ls180.v:6025$1898_Y + end + attribute \src "build/ls180/gateware/ls180.v:6027.107-6027.152" + cell $eq $eq$build/ls180/gateware/ls180.v:6027$1901 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface10_bank_bus_adr [4:0] + connect \B 4'1001 + connect \Y $eq$build/ls180/gateware/ls180.v:6027$1901_Y + end + attribute \src "build/ls180/gateware/ls180.v:6028.110-6028.155" + cell $eq $eq$build/ls180/gateware/ls180.v:6028$1905 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface10_bank_bus_adr [4:0] + connect \B 4'1001 + connect \Y $eq$build/ls180/gateware/ls180.v:6028$1905_Y + end + attribute \src "build/ls180/gateware/ls180.v:6030.100-6030.146" + cell $eq $eq$build/ls180/gateware/ls180.v:6030$1908 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface10_bank_bus_adr [4:0] + connect \B 4'1010 + connect \Y $eq$build/ls180/gateware/ls180.v:6030$1908_Y + end + attribute \src "build/ls180/gateware/ls180.v:6031.103-6031.149" + cell $eq $eq$build/ls180/gateware/ls180.v:6031$1912 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface10_bank_bus_adr [4:0] + connect \B 4'1010 + connect \Y $eq$build/ls180/gateware/ls180.v:6031$1912_Y + end + attribute \src "build/ls180/gateware/ls180.v:6033.100-6033.146" + cell $eq $eq$build/ls180/gateware/ls180.v:6033$1915 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface10_bank_bus_adr [4:0] + connect \B 4'1011 + connect \Y $eq$build/ls180/gateware/ls180.v:6033$1915_Y + end + attribute \src "build/ls180/gateware/ls180.v:6034.103-6034.149" + cell $eq $eq$build/ls180/gateware/ls180.v:6034$1919 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface10_bank_bus_adr [4:0] + connect \B 4'1011 + connect \Y $eq$build/ls180/gateware/ls180.v:6034$1919_Y + end + attribute \src "build/ls180/gateware/ls180.v:6036.100-6036.146" + cell $eq $eq$build/ls180/gateware/ls180.v:6036$1922 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface10_bank_bus_adr [4:0] + connect \B 4'1100 + connect \Y $eq$build/ls180/gateware/ls180.v:6036$1922_Y + end + attribute \src "build/ls180/gateware/ls180.v:6037.103-6037.149" + cell $eq $eq$build/ls180/gateware/ls180.v:6037$1926 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface10_bank_bus_adr [4:0] + connect \B 4'1100 + connect \Y $eq$build/ls180/gateware/ls180.v:6037$1926_Y + end + attribute \src "build/ls180/gateware/ls180.v:6039.100-6039.146" + cell $eq $eq$build/ls180/gateware/ls180.v:6039$1929 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface10_bank_bus_adr [4:0] + connect \B 4'1101 + connect \Y $eq$build/ls180/gateware/ls180.v:6039$1929_Y + end + attribute \src "build/ls180/gateware/ls180.v:6040.103-6040.149" + cell $eq $eq$build/ls180/gateware/ls180.v:6040$1933 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface10_bank_bus_adr [4:0] + connect \B 4'1101 + connect \Y $eq$build/ls180/gateware/ls180.v:6040$1933_Y + end + attribute \src "build/ls180/gateware/ls180.v:6042.118-6042.164" + cell $eq $eq$build/ls180/gateware/ls180.v:6042$1936 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface10_bank_bus_adr [4:0] + connect \B 4'1110 + connect \Y $eq$build/ls180/gateware/ls180.v:6042$1936_Y + end + attribute \src "build/ls180/gateware/ls180.v:6043.121-6043.167" + cell $eq $eq$build/ls180/gateware/ls180.v:6043$1940 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface10_bank_bus_adr [4:0] + connect \B 4'1110 + connect \Y $eq$build/ls180/gateware/ls180.v:6043$1940_Y + end + attribute \src "build/ls180/gateware/ls180.v:6045.119-6045.165" + cell $eq $eq$build/ls180/gateware/ls180.v:6045$1943 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface10_bank_bus_adr [4:0] + connect \B 4'1111 + connect \Y $eq$build/ls180/gateware/ls180.v:6045$1943_Y + end + attribute \src "build/ls180/gateware/ls180.v:6046.122-6046.168" + cell $eq $eq$build/ls180/gateware/ls180.v:6046$1947 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \builder_interface10_bank_bus_adr [4:0] + connect \B 4'1111 + connect \Y $eq$build/ls180/gateware/ls180.v:6046$1947_Y + end + attribute \src "build/ls180/gateware/ls180.v:6048.104-6048.150" + cell $eq $eq$build/ls180/gateware/ls180.v:6048$1950 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \builder_interface10_bank_bus_adr [4:0] + connect \B 5'10000 + connect \Y $eq$build/ls180/gateware/ls180.v:6048$1950_Y + end + attribute \src "build/ls180/gateware/ls180.v:6049.107-6049.153" + cell $eq $eq$build/ls180/gateware/ls180.v:6049$1954 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \builder_interface10_bank_bus_adr [4:0] + connect \B 5'10000 + connect \Y $eq$build/ls180/gateware/ls180.v:6049$1954_Y + end + attribute \src "build/ls180/gateware/ls180.v:6066.33-6066.79" + cell $eq $eq$build/ls180/gateware/ls180.v:6066$1956 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface11_bank_bus_adr [13:9] + connect \B 3'100 + connect \Y $eq$build/ls180/gateware/ls180.v:6066$1956_Y + end + attribute \src "build/ls180/gateware/ls180.v:6068.102-6068.147" + cell $eq $eq$build/ls180/gateware/ls180.v:6068$1958 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface11_bank_bus_adr [2:0] + connect \B 1'0 + connect \Y $eq$build/ls180/gateware/ls180.v:6068$1958_Y + end + attribute \src "build/ls180/gateware/ls180.v:6069.105-6069.150" + cell $eq $eq$build/ls180/gateware/ls180.v:6069$1962 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface11_bank_bus_adr [2:0] + connect \B 1'0 + connect \Y $eq$build/ls180/gateware/ls180.v:6069$1962_Y + end + attribute \src "build/ls180/gateware/ls180.v:6071.100-6071.145" + cell $eq $eq$build/ls180/gateware/ls180.v:6071$1965 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface11_bank_bus_adr [2:0] + connect \B 1'1 + connect \Y $eq$build/ls180/gateware/ls180.v:6071$1965_Y + end + attribute \src "build/ls180/gateware/ls180.v:6072.103-6072.148" + cell $eq $eq$build/ls180/gateware/ls180.v:6072$1969 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface11_bank_bus_adr [2:0] + connect \B 1'1 + connect \Y $eq$build/ls180/gateware/ls180.v:6072$1969_Y + end + attribute \src "build/ls180/gateware/ls180.v:6074.101-6074.146" + cell $eq $eq$build/ls180/gateware/ls180.v:6074$1972 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface11_bank_bus_adr [2:0] + connect \B 2'10 + connect \Y $eq$build/ls180/gateware/ls180.v:6074$1972_Y + end + attribute \src "build/ls180/gateware/ls180.v:6075.104-6075.149" + cell $eq $eq$build/ls180/gateware/ls180.v:6075$1976 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface11_bank_bus_adr [2:0] + connect \B 2'10 + connect \Y $eq$build/ls180/gateware/ls180.v:6075$1976_Y + end + attribute \src "build/ls180/gateware/ls180.v:6077.117-6077.162" + cell $eq $eq$build/ls180/gateware/ls180.v:6077$1979 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface11_bank_bus_adr [2:0] + connect \B 2'11 + connect \Y $eq$build/ls180/gateware/ls180.v:6077$1979_Y + end + attribute \src "build/ls180/gateware/ls180.v:6078.120-6078.165" + cell $eq $eq$build/ls180/gateware/ls180.v:6078$1983 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface11_bank_bus_adr [2:0] + connect \B 2'11 + connect \Y $eq$build/ls180/gateware/ls180.v:6078$1983_Y + end + attribute \src "build/ls180/gateware/ls180.v:6080.118-6080.163" + cell $eq $eq$build/ls180/gateware/ls180.v:6080$1986 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface11_bank_bus_adr [2:0] + connect \B 3'100 + connect \Y $eq$build/ls180/gateware/ls180.v:6080$1986_Y + end + attribute \src "build/ls180/gateware/ls180.v:6081.121-6081.166" + cell $eq $eq$build/ls180/gateware/ls180.v:6081$1990 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface11_bank_bus_adr [2:0] + connect \B 3'100 + connect \Y $eq$build/ls180/gateware/ls180.v:6081$1990_Y + end + attribute \src "build/ls180/gateware/ls180.v:6083.104-6083.149" + cell $eq $eq$build/ls180/gateware/ls180.v:6083$1993 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface11_bank_bus_adr [2:0] + connect \B 3'101 + connect \Y $eq$build/ls180/gateware/ls180.v:6083$1993_Y + end + attribute \src "build/ls180/gateware/ls180.v:6084.107-6084.152" + cell $eq $eq$build/ls180/gateware/ls180.v:6084$1997 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface11_bank_bus_adr [2:0] + connect \B 3'101 + connect \Y $eq$build/ls180/gateware/ls180.v:6084$1997_Y + end + attribute \src "build/ls180/gateware/ls180.v:6086.101-6086.146" + cell $eq $eq$build/ls180/gateware/ls180.v:6086$2000 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface11_bank_bus_adr [2:0] + connect \B 3'110 + connect \Y $eq$build/ls180/gateware/ls180.v:6086$2000_Y + end + attribute \src "build/ls180/gateware/ls180.v:6087.104-6087.149" + cell $eq $eq$build/ls180/gateware/ls180.v:6087$2004 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface11_bank_bus_adr [2:0] + connect \B 3'110 + connect \Y $eq$build/ls180/gateware/ls180.v:6087$2004_Y + end + attribute \src "build/ls180/gateware/ls180.v:6089.100-6089.145" + cell $eq $eq$build/ls180/gateware/ls180.v:6089$2007 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface11_bank_bus_adr [2:0] + connect \B 3'111 + connect \Y $eq$build/ls180/gateware/ls180.v:6089$2007_Y + end + attribute \src "build/ls180/gateware/ls180.v:6090.103-6090.148" + cell $eq $eq$build/ls180/gateware/ls180.v:6090$2011 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \builder_interface11_bank_bus_adr [2:0] + connect \B 3'111 + connect \Y $eq$build/ls180/gateware/ls180.v:6090$2011_Y + end + attribute \src "build/ls180/gateware/ls180.v:6100.33-6100.79" + cell $eq $eq$build/ls180/gateware/ls180.v:6100$2013 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface12_bank_bus_adr [13:9] + connect \B 2'10 + connect \Y $eq$build/ls180/gateware/ls180.v:6100$2013_Y + end + attribute \src "build/ls180/gateware/ls180.v:6102.106-6102.151" + cell $eq $eq$build/ls180/gateware/ls180.v:6102$2015 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface12_bank_bus_adr [1:0] + connect \B 1'0 + connect \Y $eq$build/ls180/gateware/ls180.v:6102$2015_Y + end + attribute \src "build/ls180/gateware/ls180.v:6103.109-6103.154" + cell $eq $eq$build/ls180/gateware/ls180.v:6103$2019 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface12_bank_bus_adr [1:0] + connect \B 1'0 + connect \Y $eq$build/ls180/gateware/ls180.v:6103$2019_Y + end + attribute \src "build/ls180/gateware/ls180.v:6105.106-6105.151" + cell $eq $eq$build/ls180/gateware/ls180.v:6105$2022 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface12_bank_bus_adr [1:0] + connect \B 1'1 + connect \Y $eq$build/ls180/gateware/ls180.v:6105$2022_Y + end + attribute \src "build/ls180/gateware/ls180.v:6106.109-6106.154" + cell $eq $eq$build/ls180/gateware/ls180.v:6106$2026 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface12_bank_bus_adr [1:0] + connect \B 1'1 + connect \Y $eq$build/ls180/gateware/ls180.v:6106$2026_Y + end + attribute \src "build/ls180/gateware/ls180.v:6108.106-6108.151" + cell $eq $eq$build/ls180/gateware/ls180.v:6108$2029 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface12_bank_bus_adr [1:0] + connect \B 2'10 + connect \Y $eq$build/ls180/gateware/ls180.v:6108$2029_Y + end + attribute \src "build/ls180/gateware/ls180.v:6109.109-6109.154" + cell $eq $eq$build/ls180/gateware/ls180.v:6109$2033 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface12_bank_bus_adr [1:0] + connect \B 2'10 + connect \Y $eq$build/ls180/gateware/ls180.v:6109$2033_Y + end + attribute \src "build/ls180/gateware/ls180.v:6111.106-6111.151" + cell $eq $eq$build/ls180/gateware/ls180.v:6111$2036 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface12_bank_bus_adr [1:0] + connect \B 2'11 + connect \Y $eq$build/ls180/gateware/ls180.v:6111$2036_Y + end + attribute \src "build/ls180/gateware/ls180.v:6112.109-6112.154" + cell $eq $eq$build/ls180/gateware/ls180.v:6112$2040 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \builder_interface12_bank_bus_adr [1:0] + connect \B 2'11 + connect \Y $eq$build/ls180/gateware/ls180.v:6112$2040_Y + end + attribute \src "build/ls180/gateware/ls180.v:6487.41-6487.81" + cell $eq $eq$build/ls180/gateware/ls180.v:6487$2075 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_port_cmd_payload_addr [10:9] + connect \B 1'0 + connect \Y $eq$build/ls180/gateware/ls180.v:6487$2075_Y + end + attribute \src "build/ls180/gateware/ls180.v:6487.144-6487.177" + cell $eq $eq$build/ls180/gateware/ls180.v:6487$2076 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin1_grant + connect \B 1'0 + connect \Y $eq$build/ls180/gateware/ls180.v:6487$2076_Y + end + attribute \src "build/ls180/gateware/ls180.v:6487.219-6487.252" + cell $eq $eq$build/ls180/gateware/ls180.v:6487$2079 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin2_grant + connect \B 1'0 + connect \Y $eq$build/ls180/gateware/ls180.v:6487$2079_Y + end + attribute \src "build/ls180/gateware/ls180.v:6487.294-6487.327" + cell $eq $eq$build/ls180/gateware/ls180.v:6487$2082 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin3_grant + connect \B 1'0 + connect \Y $eq$build/ls180/gateware/ls180.v:6487$2082_Y + end + attribute \src "build/ls180/gateware/ls180.v:6511.41-6511.81" + cell $eq $eq$build/ls180/gateware/ls180.v:6511$2091 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_port_cmd_payload_addr [10:9] + connect \B 1'1 + connect \Y $eq$build/ls180/gateware/ls180.v:6511$2091_Y + end + attribute \src "build/ls180/gateware/ls180.v:6511.144-6511.177" + cell $eq $eq$build/ls180/gateware/ls180.v:6511$2092 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin0_grant + connect \B 1'0 + connect \Y $eq$build/ls180/gateware/ls180.v:6511$2092_Y + end + attribute \src "build/ls180/gateware/ls180.v:6511.219-6511.252" + cell $eq $eq$build/ls180/gateware/ls180.v:6511$2095 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin2_grant + connect \B 1'0 + connect \Y $eq$build/ls180/gateware/ls180.v:6511$2095_Y + end + attribute \src "build/ls180/gateware/ls180.v:6511.294-6511.327" + cell $eq $eq$build/ls180/gateware/ls180.v:6511$2098 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin3_grant + connect \B 1'0 + connect \Y $eq$build/ls180/gateware/ls180.v:6511$2098_Y + end + attribute \src "build/ls180/gateware/ls180.v:6535.41-6535.81" + cell $eq $eq$build/ls180/gateware/ls180.v:6535$2107 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \main_port_cmd_payload_addr [10:9] + connect \B 2'10 + connect \Y $eq$build/ls180/gateware/ls180.v:6535$2107_Y + end + attribute \src "build/ls180/gateware/ls180.v:6535.144-6535.177" + cell $eq $eq$build/ls180/gateware/ls180.v:6535$2108 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin0_grant + connect \B 1'0 + connect \Y $eq$build/ls180/gateware/ls180.v:6535$2108_Y + end + attribute \src "build/ls180/gateware/ls180.v:6535.219-6535.252" + cell $eq $eq$build/ls180/gateware/ls180.v:6535$2111 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin1_grant + connect \B 1'0 + connect \Y $eq$build/ls180/gateware/ls180.v:6535$2111_Y + end + attribute \src "build/ls180/gateware/ls180.v:6535.294-6535.327" + cell $eq $eq$build/ls180/gateware/ls180.v:6535$2114 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin3_grant + connect \B 1'0 + connect \Y $eq$build/ls180/gateware/ls180.v:6535$2114_Y + end + attribute \src "build/ls180/gateware/ls180.v:6559.41-6559.81" + cell $eq $eq$build/ls180/gateware/ls180.v:6559$2123 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \main_port_cmd_payload_addr [10:9] + connect \B 2'11 + connect \Y $eq$build/ls180/gateware/ls180.v:6559$2123_Y + end + attribute \src "build/ls180/gateware/ls180.v:6559.144-6559.177" + cell $eq $eq$build/ls180/gateware/ls180.v:6559$2124 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin0_grant + connect \B 1'0 + connect \Y $eq$build/ls180/gateware/ls180.v:6559$2124_Y + end + attribute \src "build/ls180/gateware/ls180.v:6559.219-6559.252" + cell $eq $eq$build/ls180/gateware/ls180.v:6559$2127 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin1_grant + connect \B 1'0 + connect \Y $eq$build/ls180/gateware/ls180.v:6559$2127_Y + end + attribute \src "build/ls180/gateware/ls180.v:6559.294-6559.327" + cell $eq $eq$build/ls180/gateware/ls180.v:6559$2130 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin2_grant + connect \B 1'0 + connect \Y $eq$build/ls180/gateware/ls180.v:6559$2130_Y + end + attribute \src "build/ls180/gateware/ls180.v:7096.9-7096.45" + cell $eq $eq$build/ls180/gateware/ls180.v:7096$2201 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \main_libresocsim_tx_bitcount + connect \B 4'1000 + connect \Y $eq$build/ls180/gateware/ls180.v:7096$2201_Y + end + attribute \src "build/ls180/gateware/ls180.v:7099.10-7099.46" + cell $eq $eq$build/ls180/gateware/ls180.v:7099$2202 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \main_libresocsim_tx_bitcount + connect \B 4'1001 + connect \Y $eq$build/ls180/gateware/ls180.v:7099$2202_Y + end + attribute \src "build/ls180/gateware/ls180.v:7125.9-7125.45" + cell $eq $eq$build/ls180/gateware/ls180.v:7125$2208 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_libresocsim_rx_bitcount + connect \B 1'0 + connect \Y $eq$build/ls180/gateware/ls180.v:7125$2208_Y + end + attribute \src "build/ls180/gateware/ls180.v:7130.10-7130.46" + cell $eq $eq$build/ls180/gateware/ls180.v:7130$2209 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \main_libresocsim_rx_bitcount + connect \B 4'1001 + connect \Y $eq$build/ls180/gateware/ls180.v:7130$2209_Y + end + attribute \src "build/ls180/gateware/ls180.v:7220.8-7220.44" + cell $eq $eq$build/ls180/gateware/ls180.v:7220$2237 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_libresocsim_timer_value + connect \B 1'0 + connect \Y $eq$build/ls180/gateware/ls180.v:7220$2237_Y + end + attribute \src "build/ls180/gateware/ls180.v:7251.8-7251.42" + cell $eq $eq$build/ls180/gateware/ls180.v:7251$2245 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_postponer_count + connect \B 1'0 + connect \Y $eq$build/ls180/gateware/ls180.v:7251$2245_Y + end + attribute \src "build/ls180/gateware/ls180.v:7271.38-7271.74" + cell $eq $eq$build/ls180/gateware/ls180.v:7271$2248 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_sequencer_counter + connect \B 1'0 + connect \Y $eq$build/ls180/gateware/ls180.v:7271$2248_Y + end + attribute \src "build/ls180/gateware/ls180.v:7278.7-7278.43" + cell $eq $eq$build/ls180/gateware/ls180.v:7278$2250 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \main_sdram_sequencer_counter + connect \B 2'10 + connect \Y $eq$build/ls180/gateware/ls180.v:7278$2250_Y + end + attribute \src "build/ls180/gateware/ls180.v:7285.7-7285.43" + cell $eq $eq$build/ls180/gateware/ls180.v:7285$2251 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \main_sdram_sequencer_counter + connect \B 4'1000 + connect \Y $eq$build/ls180/gateware/ls180.v:7285$2251_Y + end + attribute \src "build/ls180/gateware/ls180.v:7293.7-7293.43" + cell $eq $eq$build/ls180/gateware/ls180.v:7293$2252 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \main_sdram_sequencer_counter + connect \B 4'1000 + connect \Y $eq$build/ls180/gateware/ls180.v:7293$2252_Y + end + attribute \src "build/ls180/gateware/ls180.v:7345.9-7345.54" + cell $eq $eq$build/ls180/gateware/ls180.v:7345$2270 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine0_twtpcon_count + connect \B 1'1 + connect \Y $eq$build/ls180/gateware/ls180.v:7345$2270_Y + end + attribute \src "build/ls180/gateware/ls180.v:7391.9-7391.54" + cell $eq $eq$build/ls180/gateware/ls180.v:7391$2286 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine1_twtpcon_count + connect \B 1'1 + connect \Y $eq$build/ls180/gateware/ls180.v:7391$2286_Y + end + attribute \src "build/ls180/gateware/ls180.v:7437.9-7437.54" + cell $eq $eq$build/ls180/gateware/ls180.v:7437$2302 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine2_twtpcon_count + connect \B 1'1 + connect \Y $eq$build/ls180/gateware/ls180.v:7437$2302_Y + end + attribute \src "build/ls180/gateware/ls180.v:7483.9-7483.54" + cell $eq $eq$build/ls180/gateware/ls180.v:7483$2318 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine3_twtpcon_count + connect \B 1'1 + connect \Y $eq$build/ls180/gateware/ls180.v:7483$2318_Y + end + attribute \src "build/ls180/gateware/ls180.v:7633.9-7633.41" + cell $eq $eq$build/ls180/gateware/ls180.v:7633$2330 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_tccdcon_count + connect \B 1'1 + connect \Y $eq$build/ls180/gateware/ls180.v:7633$2330_Y + end + attribute \src "build/ls180/gateware/ls180.v:7648.9-7648.41" + cell $eq $eq$build/ls180/gateware/ls180.v:7648$2333 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_twtrcon_count + connect \B 1'1 + connect \Y $eq$build/ls180/gateware/ls180.v:7648$2333_Y + end + attribute \src "build/ls180/gateware/ls180.v:7654.49-7654.82" + cell $eq $eq$build/ls180/gateware/ls180.v:7654$2334 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin0_grant + connect \B 1'0 + connect \Y $eq$build/ls180/gateware/ls180.v:7654$2334_Y + end + attribute \src "build/ls180/gateware/ls180.v:7654.131-7654.164" + cell $eq $eq$build/ls180/gateware/ls180.v:7654$2337 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin1_grant + connect \B 1'0 + connect \Y $eq$build/ls180/gateware/ls180.v:7654$2337_Y + end + attribute \src "build/ls180/gateware/ls180.v:7654.213-7654.246" + cell $eq $eq$build/ls180/gateware/ls180.v:7654$2340 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin2_grant + connect \B 1'0 + connect \Y $eq$build/ls180/gateware/ls180.v:7654$2340_Y + end + attribute \src "build/ls180/gateware/ls180.v:7654.295-7654.328" + cell $eq $eq$build/ls180/gateware/ls180.v:7654$2343 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin3_grant + connect \B 1'0 + connect \Y $eq$build/ls180/gateware/ls180.v:7654$2343_Y + end + attribute \src "build/ls180/gateware/ls180.v:7655.50-7655.83" + cell $eq $eq$build/ls180/gateware/ls180.v:7655$2346 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin0_grant + connect \B 1'0 + connect \Y $eq$build/ls180/gateware/ls180.v:7655$2346_Y + end + attribute \src "build/ls180/gateware/ls180.v:7655.132-7655.165" + cell $eq $eq$build/ls180/gateware/ls180.v:7655$2349 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin1_grant + connect \B 1'0 + connect \Y $eq$build/ls180/gateware/ls180.v:7655$2349_Y + end + attribute \src "build/ls180/gateware/ls180.v:7655.214-7655.247" + cell $eq $eq$build/ls180/gateware/ls180.v:7655$2352 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin2_grant + connect \B 1'0 + connect \Y $eq$build/ls180/gateware/ls180.v:7655$2352_Y + end + attribute \src "build/ls180/gateware/ls180.v:7655.296-7655.329" + cell $eq $eq$build/ls180/gateware/ls180.v:7655$2355 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_roundrobin3_grant + connect \B 1'0 + connect \Y $eq$build/ls180/gateware/ls180.v:7655$2355_Y + end + attribute \src "build/ls180/gateware/ls180.v:7736.9-7736.54" + cell $eq $eq$build/ls180/gateware/ls180.v:7736$2369 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \libresocsim_cmdr_cmdr_converter_demux + connect \B 3'111 + connect \Y $eq$build/ls180/gateware/ls180.v:7736$2369_Y + end + attribute \src "build/ls180/gateware/ls180.v:7817.9-7817.55" + cell $eq $eq$build/ls180/gateware/ls180.v:7817$2381 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \libresocsim_dataw_crcr_converter_demux + connect \B 3'111 + connect \Y $eq$build/ls180/gateware/ls180.v:7817$2381_Y + end + attribute \src "build/ls180/gateware/ls180.v:7896.9-7896.56" + cell $eq $eq$build/ls180/gateware/ls180.v:7896$2393 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \libresocsim_datar_datar_converter_demux + connect \B 1'1 + connect \Y $eq$build/ls180/gateware/ls180.v:7896$2393_Y + end + attribute \src "build/ls180/gateware/ls180.v:8119.9-8119.56" + cell $eq $eq$build/ls180/gateware/ls180.v:8119$2426 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \libresocsim_sdblock2mem_converter_demux + connect \B 2'11 + connect \Y $eq$build/ls180/gateware/ls180.v:8119$2426_Y + end + attribute \src "build/ls180/gateware/ls180.v:4848.54-4848.97" + cell $gt $gt$build/ls180/gateware/ls180.v:4848$896 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \libresocsim_sdcore_crc16_checker_cnt + connect \B 3'111 + connect \Y $gt$build/ls180/gateware/ls180.v:4848$896_Y + end + attribute \src "build/ls180/gateware/ls180.v:4854.7-4854.50" + cell $lt $lt$build/ls180/gateware/ls180.v:4854$899 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \libresocsim_sdcore_crc16_checker_cnt + connect \B 4'1000 + connect \Y $lt$build/ls180/gateware/ls180.v:4854$899_Y + end + attribute \src "build/ls180/gateware/ls180.v:9379.33-9379.36" + cell $memrd $memrd$\mem$build/ls180/gateware/ls180.v:9379$2472 + parameter \ABITS 16 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\mem" + parameter \TRANSPARENT 0 + parameter \WIDTH 32 + connect \ADDR \memadr + connect \CLK 1'x + connect \DATA $memrd$\mem$build/ls180/gateware/ls180.v:9379$2472_DATA + connect \EN 1'x + end + attribute \src "build/ls180/gateware/ls180.v:9391.12-9391.19" + cell $memrd $memrd$\storage$build/ls180/gateware/ls180.v:9391$2477 + parameter \ABITS 4 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\storage" + parameter \TRANSPARENT 0 + parameter \WIDTH 10 + connect \ADDR \main_libresocsim_uart_tx_fifo_wrport_adr + connect \CLK 1'x + connect \DATA $memrd$\storage$build/ls180/gateware/ls180.v:9391$2477_DATA + connect \EN 1'x + end + attribute \src "build/ls180/gateware/ls180.v:9396.15-9396.22" + cell $memrd $memrd$\storage$build/ls180/gateware/ls180.v:9396$2479 + parameter \ABITS 4 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\storage" + parameter \TRANSPARENT 0 + parameter \WIDTH 10 + connect \ADDR \main_libresocsim_uart_tx_fifo_rdport_adr + connect \CLK 1'x + connect \DATA $memrd$\storage$build/ls180/gateware/ls180.v:9396$2479_DATA + connect \EN 1'x + end + attribute \src "build/ls180/gateware/ls180.v:9408.14-9408.23" + cell $memrd $memrd$\storage_1$build/ls180/gateware/ls180.v:9408$2484 + parameter \ABITS 4 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\storage_1" + parameter \TRANSPARENT 0 + parameter \WIDTH 10 + connect \ADDR \main_libresocsim_uart_rx_fifo_wrport_adr + connect \CLK 1'x + connect \DATA $memrd$\storage_1$build/ls180/gateware/ls180.v:9408$2484_DATA + connect \EN 1'x + end + attribute \src "build/ls180/gateware/ls180.v:9413.15-9413.24" + cell $memrd $memrd$\storage_1$build/ls180/gateware/ls180.v:9413$2486 + parameter \ABITS 4 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\storage_1" + parameter \TRANSPARENT 0 + parameter \WIDTH 10 + connect \ADDR \main_libresocsim_uart_rx_fifo_rdport_adr + connect \CLK 1'x + connect \DATA $memrd$\storage_1$build/ls180/gateware/ls180.v:9413$2486_DATA + connect \EN 1'x + end + attribute \src "build/ls180/gateware/ls180.v:9424.14-9424.23" + cell $memrd $memrd$\storage_2$build/ls180/gateware/ls180.v:9424$2491 + parameter \ABITS 3 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\storage_2" + parameter \TRANSPARENT 0 + parameter \WIDTH 25 + connect \ADDR \main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr + connect \CLK 1'x + connect \DATA $memrd$\storage_2$build/ls180/gateware/ls180.v:9424$2491_DATA + connect \EN 1'x + end + attribute \src "build/ls180/gateware/ls180.v:9431.68-9431.77" + cell $memrd $memrd$\storage_2$build/ls180/gateware/ls180.v:9431$2493 + parameter \ABITS 3 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\storage_2" + parameter \TRANSPARENT 0 + parameter \WIDTH 25 + connect \ADDR \main_sdram_bankmachine0_cmd_buffer_lookahead_rdport_adr + connect \CLK 1'x + connect \DATA $memrd$\storage_2$build/ls180/gateware/ls180.v:9431$2493_DATA + connect \EN 1'x + end + attribute \src "build/ls180/gateware/ls180.v:9438.14-9438.23" + cell $memrd $memrd$\storage_3$build/ls180/gateware/ls180.v:9438$2498 + parameter \ABITS 3 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\storage_3" + parameter \TRANSPARENT 0 + parameter \WIDTH 25 + connect \ADDR \main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr + connect \CLK 1'x + connect \DATA $memrd$\storage_3$build/ls180/gateware/ls180.v:9438$2498_DATA + connect \EN 1'x + end + attribute \src "build/ls180/gateware/ls180.v:9445.68-9445.77" + cell $memrd $memrd$\storage_3$build/ls180/gateware/ls180.v:9445$2500 + parameter \ABITS 3 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\storage_3" + parameter \TRANSPARENT 0 + parameter \WIDTH 25 + connect \ADDR \main_sdram_bankmachine1_cmd_buffer_lookahead_rdport_adr + connect \CLK 1'x + connect \DATA $memrd$\storage_3$build/ls180/gateware/ls180.v:9445$2500_DATA + connect \EN 1'x + end + attribute \src "build/ls180/gateware/ls180.v:9452.14-9452.23" + cell $memrd $memrd$\storage_4$build/ls180/gateware/ls180.v:9452$2505 + parameter \ABITS 3 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\storage_4" + parameter \TRANSPARENT 0 + parameter \WIDTH 25 + connect \ADDR \main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr + connect \CLK 1'x + connect \DATA $memrd$\storage_4$build/ls180/gateware/ls180.v:9452$2505_DATA + connect \EN 1'x + end + attribute \src "build/ls180/gateware/ls180.v:9459.68-9459.77" + cell $memrd $memrd$\storage_4$build/ls180/gateware/ls180.v:9459$2507 + parameter \ABITS 3 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\storage_4" + parameter \TRANSPARENT 0 + parameter \WIDTH 25 + connect \ADDR \main_sdram_bankmachine2_cmd_buffer_lookahead_rdport_adr + connect \CLK 1'x + connect \DATA $memrd$\storage_4$build/ls180/gateware/ls180.v:9459$2507_DATA + connect \EN 1'x + end + attribute \src "build/ls180/gateware/ls180.v:9466.14-9466.23" + cell $memrd $memrd$\storage_5$build/ls180/gateware/ls180.v:9466$2512 + parameter \ABITS 3 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\storage_5" + parameter \TRANSPARENT 0 + parameter \WIDTH 25 + connect \ADDR \main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr + connect \CLK 1'x + connect \DATA $memrd$\storage_5$build/ls180/gateware/ls180.v:9466$2512_DATA + connect \EN 1'x + end + attribute \src "build/ls180/gateware/ls180.v:9473.68-9473.77" + cell $memrd $memrd$\storage_5$build/ls180/gateware/ls180.v:9473$2514 + parameter \ABITS 3 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\storage_5" + parameter \TRANSPARENT 0 + parameter \WIDTH 25 + connect \ADDR \main_sdram_bankmachine3_cmd_buffer_lookahead_rdport_adr + connect \CLK 1'x + connect \DATA $memrd$\storage_5$build/ls180/gateware/ls180.v:9473$2514_DATA + connect \EN 1'x + end + attribute \src "build/ls180/gateware/ls180.v:9480.14-9480.23" + cell $memrd $memrd$\storage_6$build/ls180/gateware/ls180.v:9480$2519 + parameter \ABITS 5 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\storage_6" + parameter \TRANSPARENT 0 + parameter \WIDTH 10 + connect \ADDR \libresocsim_sdblock2mem_fifo_wrport_adr + connect \CLK 1'x + connect \DATA $memrd$\storage_6$build/ls180/gateware/ls180.v:9480$2519_DATA + connect \EN 1'x + end + attribute \src "build/ls180/gateware/ls180.v:9487.52-9487.61" + cell $memrd $memrd$\storage_6$build/ls180/gateware/ls180.v:9487$2521 + parameter \ABITS 5 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\storage_6" + parameter \TRANSPARENT 0 + parameter \WIDTH 10 + connect \ADDR \libresocsim_sdblock2mem_fifo_rdport_adr + connect \CLK 1'x + connect \DATA $memrd$\storage_6$build/ls180/gateware/ls180.v:9487$2521_DATA + connect \EN 1'x + end + attribute \src "build/ls180/gateware/ls180.v:9494.14-9494.23" + cell $memrd $memrd$\storage_7$build/ls180/gateware/ls180.v:9494$2526 + parameter \ABITS 5 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\storage_7" + parameter \TRANSPARENT 0 + parameter \WIDTH 10 + connect \ADDR \libresocsim_sdmem2block_fifo_wrport_adr + connect \CLK 1'x + connect \DATA $memrd$\storage_7$build/ls180/gateware/ls180.v:9494$2526_DATA + connect \EN 1'x + end + attribute \src "build/ls180/gateware/ls180.v:9501.52-9501.61" + cell $memrd $memrd$\storage_7$build/ls180/gateware/ls180.v:9501$2528 + parameter \ABITS 5 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\storage_7" + parameter \TRANSPARENT 0 + parameter \WIDTH 10 + connect \ADDR \libresocsim_sdmem2block_fifo_rdport_adr + connect \CLK 1'x + connect \DATA $memrd$\storage_7$build/ls180/gateware/ls180.v:9501$2528_DATA + connect \EN 1'x + end + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + cell $memwr $memwr$\mem$build/ls180/gateware/ls180.v:0$2551 + parameter \ABITS 16 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\mem" + parameter \PRIORITY 2551 + parameter \WIDTH 32 + connect \ADDR $memwr$\mem$build/ls180/gateware/ls180.v:9369$1_ADDR + connect \CLK 1'x + connect \DATA $memwr$\mem$build/ls180/gateware/ls180.v:9369$1_DATA + connect \EN $memwr$\mem$build/ls180/gateware/ls180.v:9369$1_EN + end + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + cell $memwr $memwr$\mem$build/ls180/gateware/ls180.v:0$2552 + parameter \ABITS 16 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\mem" + parameter \PRIORITY 2552 + parameter \WIDTH 32 + connect \ADDR $memwr$\mem$build/ls180/gateware/ls180.v:9371$2_ADDR + connect \CLK 1'x + connect \DATA $memwr$\mem$build/ls180/gateware/ls180.v:9371$2_DATA + connect \EN $memwr$\mem$build/ls180/gateware/ls180.v:9371$2_EN + end + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + cell $memwr $memwr$\mem$build/ls180/gateware/ls180.v:0$2553 + parameter \ABITS 16 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\mem" + parameter \PRIORITY 2553 + parameter \WIDTH 32 + connect \ADDR $memwr$\mem$build/ls180/gateware/ls180.v:9373$3_ADDR + connect \CLK 1'x + connect \DATA $memwr$\mem$build/ls180/gateware/ls180.v:9373$3_DATA + connect \EN $memwr$\mem$build/ls180/gateware/ls180.v:9373$3_EN + end + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + cell $memwr $memwr$\mem$build/ls180/gateware/ls180.v:0$2554 + parameter \ABITS 16 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\mem" + parameter \PRIORITY 2554 + parameter \WIDTH 32 + connect \ADDR $memwr$\mem$build/ls180/gateware/ls180.v:9375$4_ADDR + connect \CLK 1'x + connect \DATA $memwr$\mem$build/ls180/gateware/ls180.v:9375$4_DATA + connect \EN $memwr$\mem$build/ls180/gateware/ls180.v:9375$4_EN + end + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + cell $memwr $memwr$\storage$build/ls180/gateware/ls180.v:0$2555 + parameter \ABITS 4 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\storage" + parameter \PRIORITY 2555 + parameter \WIDTH 10 + connect \ADDR $memwr$\storage$build/ls180/gateware/ls180.v:9390$5_ADDR + connect \CLK 1'x + connect \DATA $memwr$\storage$build/ls180/gateware/ls180.v:9390$5_DATA + connect \EN $memwr$\storage$build/ls180/gateware/ls180.v:9390$5_EN + end + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + cell $memwr $memwr$\storage_1$build/ls180/gateware/ls180.v:0$2556 + parameter \ABITS 4 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\storage_1" + parameter \PRIORITY 2556 + parameter \WIDTH 10 + connect \ADDR $memwr$\storage_1$build/ls180/gateware/ls180.v:9407$6_ADDR + connect \CLK 1'x + connect \DATA $memwr$\storage_1$build/ls180/gateware/ls180.v:9407$6_DATA + connect \EN $memwr$\storage_1$build/ls180/gateware/ls180.v:9407$6_EN + end + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + cell $memwr $memwr$\storage_2$build/ls180/gateware/ls180.v:0$2557 + parameter \ABITS 3 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\storage_2" + parameter \PRIORITY 2557 + parameter \WIDTH 25 + connect \ADDR $memwr$\storage_2$build/ls180/gateware/ls180.v:9423$7_ADDR + connect \CLK 1'x + connect \DATA $memwr$\storage_2$build/ls180/gateware/ls180.v:9423$7_DATA + connect \EN $memwr$\storage_2$build/ls180/gateware/ls180.v:9423$7_EN + end + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + cell $memwr $memwr$\storage_3$build/ls180/gateware/ls180.v:0$2558 + parameter \ABITS 3 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\storage_3" + parameter \PRIORITY 2558 + parameter \WIDTH 25 + connect \ADDR $memwr$\storage_3$build/ls180/gateware/ls180.v:9437$8_ADDR + connect \CLK 1'x + connect \DATA $memwr$\storage_3$build/ls180/gateware/ls180.v:9437$8_DATA + connect \EN $memwr$\storage_3$build/ls180/gateware/ls180.v:9437$8_EN + end + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + cell $memwr $memwr$\storage_4$build/ls180/gateware/ls180.v:0$2559 + parameter \ABITS 3 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\storage_4" + parameter \PRIORITY 2559 + parameter \WIDTH 25 + connect \ADDR $memwr$\storage_4$build/ls180/gateware/ls180.v:9451$9_ADDR + connect \CLK 1'x + connect \DATA $memwr$\storage_4$build/ls180/gateware/ls180.v:9451$9_DATA + connect \EN $memwr$\storage_4$build/ls180/gateware/ls180.v:9451$9_EN + end + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + cell $memwr $memwr$\storage_5$build/ls180/gateware/ls180.v:0$2560 + parameter \ABITS 3 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\storage_5" + parameter \PRIORITY 2560 + parameter \WIDTH 25 + connect \ADDR $memwr$\storage_5$build/ls180/gateware/ls180.v:9465$10_ADDR + connect \CLK 1'x + connect \DATA $memwr$\storage_5$build/ls180/gateware/ls180.v:9465$10_DATA + connect \EN $memwr$\storage_5$build/ls180/gateware/ls180.v:9465$10_EN + end + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + cell $memwr $memwr$\storage_6$build/ls180/gateware/ls180.v:0$2561 + parameter \ABITS 5 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\storage_6" + parameter \PRIORITY 2561 + parameter \WIDTH 10 + connect \ADDR $memwr$\storage_6$build/ls180/gateware/ls180.v:9479$11_ADDR + connect \CLK 1'x + connect \DATA $memwr$\storage_6$build/ls180/gateware/ls180.v:9479$11_DATA + connect \EN $memwr$\storage_6$build/ls180/gateware/ls180.v:9479$11_EN + end + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + cell $memwr $memwr$\storage_7$build/ls180/gateware/ls180.v:0$2562 + parameter \ABITS 5 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\storage_7" + parameter \PRIORITY 2562 + parameter \WIDTH 10 + connect \ADDR $memwr$\storage_7$build/ls180/gateware/ls180.v:9493$12_ADDR + connect \CLK 1'x + connect \DATA $memwr$\storage_7$build/ls180/gateware/ls180.v:9493$12_DATA + connect \EN $memwr$\storage_7$build/ls180/gateware/ls180.v:9493$12_EN + end + attribute \src "build/ls180/gateware/ls180.v:2808.59-2808.104" + cell $ne $ne$build/ls180/gateware/ls180.v:2808$75 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \main_libresocsim_uart_tx_fifo_level0 + connect \B 5'10000 + connect \Y $ne$build/ls180/gateware/ls180.v:2808$75_Y + end + attribute \src "build/ls180/gateware/ls180.v:2809.59-2809.103" + cell $ne $ne$build/ls180/gateware/ls180.v:2809$76 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_libresocsim_uart_tx_fifo_level0 + connect \B 1'0 + connect \Y $ne$build/ls180/gateware/ls180.v:2809$76_Y + end + attribute \src "build/ls180/gateware/ls180.v:2838.59-2838.104" + cell $ne $ne$build/ls180/gateware/ls180.v:2838$86 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \main_libresocsim_uart_rx_fifo_level0 + connect \B 5'10000 + connect \Y $ne$build/ls180/gateware/ls180.v:2838$86_Y + end + attribute \src "build/ls180/gateware/ls180.v:2839.59-2839.103" + cell $ne $ne$build/ls180/gateware/ls180.v:2839$87 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_libresocsim_uart_rx_fifo_level0 + connect \B 1'0 + connect \Y $ne$build/ls180/gateware/ls180.v:2839$87_Y + end + attribute \src "build/ls180/gateware/ls180.v:2840.47-2840.83" + cell $ne $ne$build/ls180/gateware/ls180.v:2840$88 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_libresocsim_timer_value + connect \B 1'0 + connect \Y $ne$build/ls180/gateware/ls180.v:2840$88_Y + end + attribute \src "build/ls180/gateware/ls180.v:3006.70-3006.104" + cell $ne $ne$build/ls180/gateware/ls180.v:3006$103 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_sequencer_count + connect \B 1'0 + connect \Y $ne$build/ls180/gateware/ls180.v:3006$103_Y + end + attribute \src "build/ls180/gateware/ls180.v:3067.8-3067.142" + cell $ne $ne$build/ls180/gateware/ls180.v:3067$122 + parameter \A_SIGNED 0 + parameter \A_WIDTH 13 + parameter \B_SIGNED 0 + parameter \B_WIDTH 13 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_source_payload_addr [21:9] + connect \B \main_sdram_bankmachine0_cmd_buffer_source_payload_addr [21:9] + connect \Y $ne$build/ls180/gateware/ls180.v:3067$122_Y + end + attribute \src "build/ls180/gateware/ls180.v:3099.75-3099.133" + cell $ne $ne$build/ls180/gateware/ls180.v:3099$129 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_level + connect \B 4'1000 + connect \Y $ne$build/ls180/gateware/ls180.v:3099$129_Y + end + attribute \src "build/ls180/gateware/ls180.v:3100.75-3100.133" + cell $ne $ne$build/ls180/gateware/ls180.v:3100$130 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_level + connect \B 1'0 + connect \Y $ne$build/ls180/gateware/ls180.v:3100$130_Y + end + attribute \src "build/ls180/gateware/ls180.v:3224.8-3224.142" + cell $ne $ne$build/ls180/gateware/ls180.v:3224$152 + parameter \A_SIGNED 0 + parameter \A_WIDTH 13 + parameter \B_SIGNED 0 + parameter \B_WIDTH 13 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_source_payload_addr [21:9] + connect \B \main_sdram_bankmachine1_cmd_buffer_source_payload_addr [21:9] + connect \Y $ne$build/ls180/gateware/ls180.v:3224$152_Y + end + attribute \src "build/ls180/gateware/ls180.v:3256.75-3256.133" + cell $ne $ne$build/ls180/gateware/ls180.v:3256$159 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_level + connect \B 4'1000 + connect \Y $ne$build/ls180/gateware/ls180.v:3256$159_Y + end + attribute \src "build/ls180/gateware/ls180.v:3257.75-3257.133" + cell $ne $ne$build/ls180/gateware/ls180.v:3257$160 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_level + connect \B 1'0 + connect \Y $ne$build/ls180/gateware/ls180.v:3257$160_Y + end + attribute \src "build/ls180/gateware/ls180.v:3381.8-3381.142" + cell $ne $ne$build/ls180/gateware/ls180.v:3381$182 + parameter \A_SIGNED 0 + parameter \A_WIDTH 13 + parameter \B_SIGNED 0 + parameter \B_WIDTH 13 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_source_payload_addr [21:9] + connect \B \main_sdram_bankmachine2_cmd_buffer_source_payload_addr [21:9] + connect \Y $ne$build/ls180/gateware/ls180.v:3381$182_Y + end + attribute \src "build/ls180/gateware/ls180.v:3413.75-3413.133" + cell $ne $ne$build/ls180/gateware/ls180.v:3413$189 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_level + connect \B 4'1000 + connect \Y $ne$build/ls180/gateware/ls180.v:3413$189_Y + end + attribute \src "build/ls180/gateware/ls180.v:3414.75-3414.133" + cell $ne $ne$build/ls180/gateware/ls180.v:3414$190 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_level + connect \B 1'0 + connect \Y $ne$build/ls180/gateware/ls180.v:3414$190_Y + end + attribute \src "build/ls180/gateware/ls180.v:3538.8-3538.142" + cell $ne $ne$build/ls180/gateware/ls180.v:3538$212 + parameter \A_SIGNED 0 + parameter \A_WIDTH 13 + parameter \B_SIGNED 0 + parameter \B_WIDTH 13 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_source_payload_addr [21:9] + connect \B \main_sdram_bankmachine3_cmd_buffer_source_payload_addr [21:9] + connect \Y $ne$build/ls180/gateware/ls180.v:3538$212_Y + end + attribute \src "build/ls180/gateware/ls180.v:3570.75-3570.133" + cell $ne $ne$build/ls180/gateware/ls180.v:3570$219 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_level + connect \B 4'1000 + connect \Y $ne$build/ls180/gateware/ls180.v:3570$219_Y + end + attribute \src "build/ls180/gateware/ls180.v:3571.75-3571.133" + cell $ne $ne$build/ls180/gateware/ls180.v:3571$220 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_level + connect \B 1'0 + connect \Y $ne$build/ls180/gateware/ls180.v:3571$220_Y + end + attribute \src "build/ls180/gateware/ls180.v:4380.33-4380.91" + cell $ne $ne$build/ls180/gateware/ls180.v:4380$663 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \libresocsim_dataw_crcr_source_source_payload_data0 + connect \B 3'101 + connect \Y $ne$build/ls180/gateware/ls180.v:4380$663_Y + end + attribute \src "build/ls180/gateware/ls180.v:5027.10-5027.57" + cell $ne $ne$build/ls180/gateware/ls180.v:5027$960 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \libresocsim_datar_source_payload_status + connect \B 2'10 + connect \Y $ne$build/ls180/gateware/ls180.v:5027$960_Y + end + attribute \src "build/ls180/gateware/ls180.v:5132.58-5132.101" + cell $ne $ne$build/ls180/gateware/ls180.v:5132$974 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \libresocsim_sdblock2mem_fifo_level + connect \B 6'100000 + connect \Y $ne$build/ls180/gateware/ls180.v:5132$974_Y + end + attribute \src "build/ls180/gateware/ls180.v:5133.58-5133.100" + cell $ne $ne$build/ls180/gateware/ls180.v:5133$975 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \libresocsim_sdblock2mem_fifo_level + connect \B 1'0 + connect \Y $ne$build/ls180/gateware/ls180.v:5133$975_Y + end + attribute \src "build/ls180/gateware/ls180.v:5340.58-5340.101" + cell $ne $ne$build/ls180/gateware/ls180.v:5340$1005 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \libresocsim_sdmem2block_fifo_level + connect \B 6'100000 + connect \Y $ne$build/ls180/gateware/ls180.v:5340$1005_Y + end + attribute \src "build/ls180/gateware/ls180.v:5341.58-5341.100" + cell $ne $ne$build/ls180/gateware/ls180.v:5341$1006 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \libresocsim_sdmem2block_fifo_level + connect \B 1'0 + connect \Y $ne$build/ls180/gateware/ls180.v:5341$1006_Y + end + attribute \src "build/ls180/gateware/ls180.v:5431.79-5431.119" + cell $ne $ne$build/ls180/gateware/ls180.v:5431$1017 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_libresocsim_wishbone_sel + connect \B 1'0 + connect \Y $ne$build/ls180/gateware/ls180.v:5431$1017_Y + end + attribute \src "build/ls180/gateware/ls180.v:7078.7-7078.66" + cell $ne $ne$build/ls180/gateware/ls180.v:7078$2190 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 32 + parameter \Y_WIDTH 1 + connect \A \main_libresocsim_soccontroller_bus_errors + connect \B 32'11111111111111111111111111111111 + connect \Y $ne$build/ls180/gateware/ls180.v:7078$2190_Y + end + attribute \src "build/ls180/gateware/ls180.v:7260.9-7260.43" + cell $ne $ne$build/ls180/gateware/ls180.v:7260$2246 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_sequencer_count + connect \B 1'0 + connect \Y $ne$build/ls180/gateware/ls180.v:7260$2246_Y + end + attribute \src "build/ls180/gateware/ls180.v:7296.8-7296.44" + cell $ne $ne$build/ls180/gateware/ls180.v:7296$2253 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_sequencer_counter + connect \B 1'0 + connect \Y $ne$build/ls180/gateware/ls180.v:7296$2253_Y + end + attribute \src "build/ls180/gateware/ls180.v:8039.9-8039.54" + cell $ne $ne$build/ls180/gateware/ls180.v:8039$2413 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \libresocsim_sdcore_crc16_checker_cnt + connect \B 4'1010 + connect \Y $ne$build/ls180/gateware/ls180.v:8039$2413_Y + end + attribute \src "build/ls180/gateware/ls180.v:2593.45-2593.80" + cell $not $not$build/ls180/gateware/ls180.v:2593$14 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_libresocsim_libresoc_ibus_cyc + connect \Y $not$build/ls180/gateware/ls180.v:2593$14_Y + end + attribute \src "build/ls180/gateware/ls180.v:2632.61-2632.94" + cell $not $not$build/ls180/gateware/ls180.v:2632$19 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_libresocsim_converter0_skip + connect \Y $not$build/ls180/gateware/ls180.v:2632$19_Y + end + attribute \src "build/ls180/gateware/ls180.v:2633.61-2633.94" + cell $not $not$build/ls180/gateware/ls180.v:2633$20 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_libresocsim_converter0_skip + connect \Y $not$build/ls180/gateware/ls180.v:2633$20_Y + end + attribute \src "build/ls180/gateware/ls180.v:2653.45-2653.80" + cell $not $not$build/ls180/gateware/ls180.v:2653$25 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_libresocsim_libresoc_dbus_cyc + connect \Y $not$build/ls180/gateware/ls180.v:2653$25_Y + end + attribute \src "build/ls180/gateware/ls180.v:2692.61-2692.94" + cell $not $not$build/ls180/gateware/ls180.v:2692$30 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_libresocsim_converter1_skip + connect \Y $not$build/ls180/gateware/ls180.v:2692$30_Y + end + attribute \src "build/ls180/gateware/ls180.v:2693.61-2693.94" + cell $not $not$build/ls180/gateware/ls180.v:2693$31 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_libresocsim_converter1_skip + connect \Y $not$build/ls180/gateware/ls180.v:2693$31_Y + end + attribute \src "build/ls180/gateware/ls180.v:2737.47-2737.88" + cell $not $not$build/ls180/gateware/ls180.v:2737$49 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_libresocsim_uart_tx_fifo_sink_ready + connect \Y $not$build/ls180/gateware/ls180.v:2737$49_Y + end + attribute \src "build/ls180/gateware/ls180.v:2738.48-2738.91" + cell $not $not$build/ls180/gateware/ls180.v:2738$50 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_libresocsim_uart_tx_fifo_source_valid + connect \Y $not$build/ls180/gateware/ls180.v:2738$50_Y + end + attribute \src "build/ls180/gateware/ls180.v:2744.44-2744.85" + cell $not $not$build/ls180/gateware/ls180.v:2744$51 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_libresocsim_uart_tx_fifo_sink_ready + connect \Y $not$build/ls180/gateware/ls180.v:2744$51_Y + end + attribute \src "build/ls180/gateware/ls180.v:2750.48-2750.91" + cell $not $not$build/ls180/gateware/ls180.v:2750$52 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_libresocsim_uart_rx_fifo_source_valid + connect \Y $not$build/ls180/gateware/ls180.v:2750$52_Y + end + attribute \src "build/ls180/gateware/ls180.v:2751.47-2751.88" + cell $not $not$build/ls180/gateware/ls180.v:2751$53 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_libresocsim_uart_rx_fifo_sink_ready + connect \Y $not$build/ls180/gateware/ls180.v:2751$53_Y + end + attribute \src "build/ls180/gateware/ls180.v:2754.44-2754.87" + cell $not $not$build/ls180/gateware/ls180.v:2754$56 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_libresocsim_uart_rx_fifo_source_valid + connect \Y $not$build/ls180/gateware/ls180.v:2754$56_Y + end + attribute \src "build/ls180/gateware/ls180.v:2792.105-2792.144" + cell $not $not$build/ls180/gateware/ls180.v:2792$66 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_libresocsim_uart_tx_fifo_readable + connect \Y $not$build/ls180/gateware/ls180.v:2792$66_Y + end + attribute \src "build/ls180/gateware/ls180.v:2822.105-2822.144" + cell $not $not$build/ls180/gateware/ls180.v:2822$77 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_libresocsim_uart_rx_fifo_readable + connect \Y $not$build/ls180/gateware/ls180.v:2822$77_Y + end + attribute \src "build/ls180/gateware/ls180.v:2955.34-2955.64" + cell $not $not$build/ls180/gateware/ls180.v:2955$95 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_command_storage [0] + connect \Y $not$build/ls180/gateware/ls180.v:2955$95_Y + end + attribute \src "build/ls180/gateware/ls180.v:2956.31-2956.61" + cell $not $not$build/ls180/gateware/ls180.v:2956$96 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_command_storage [1] + connect \Y $not$build/ls180/gateware/ls180.v:2956$96_Y + end + attribute \src "build/ls180/gateware/ls180.v:2957.32-2957.62" + cell $not $not$build/ls180/gateware/ls180.v:2957$97 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_command_storage [2] + connect \Y $not$build/ls180/gateware/ls180.v:2957$97_Y + end + attribute \src "build/ls180/gateware/ls180.v:2958.32-2958.62" + cell $not $not$build/ls180/gateware/ls180.v:2958$98 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_command_storage [3] + connect \Y $not$build/ls180/gateware/ls180.v:2958$98_Y + end + attribute \src "build/ls180/gateware/ls180.v:3000.33-3000.56" + cell $not $not$build/ls180/gateware/ls180.v:3000$101 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_timer_done0 + connect \Y $not$build/ls180/gateware/ls180.v:3000$101_Y + end + attribute \src "build/ls180/gateware/ls180.v:3101.58-3101.106" + cell $not $not$build/ls180/gateware/ls180.v:3101$131 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine0_cmd_buffer_source_valid + connect \Y $not$build/ls180/gateware/ls180.v:3101$131_Y + end + attribute \src "build/ls180/gateware/ls180.v:3155.9-3155.45" + cell $not $not$build/ls180/gateware/ls180.v:3155$136 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine0_refresh_req + connect \Y $not$build/ls180/gateware/ls180.v:3155$136_Y + end + attribute \src "build/ls180/gateware/ls180.v:3258.58-3258.106" + cell $not $not$build/ls180/gateware/ls180.v:3258$161 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine1_cmd_buffer_source_valid + connect \Y $not$build/ls180/gateware/ls180.v:3258$161_Y + end + attribute \src "build/ls180/gateware/ls180.v:3312.9-3312.45" + cell $not $not$build/ls180/gateware/ls180.v:3312$166 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine1_refresh_req + connect \Y $not$build/ls180/gateware/ls180.v:3312$166_Y + end + attribute \src "build/ls180/gateware/ls180.v:3415.58-3415.106" + cell $not $not$build/ls180/gateware/ls180.v:3415$191 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine2_cmd_buffer_source_valid + connect \Y $not$build/ls180/gateware/ls180.v:3415$191_Y + end + attribute \src "build/ls180/gateware/ls180.v:3469.9-3469.45" + cell $not $not$build/ls180/gateware/ls180.v:3469$196 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine2_refresh_req + connect \Y $not$build/ls180/gateware/ls180.v:3469$196_Y + end + attribute \src "build/ls180/gateware/ls180.v:3572.58-3572.106" + cell $not $not$build/ls180/gateware/ls180.v:3572$221 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine3_cmd_buffer_source_valid + connect \Y $not$build/ls180/gateware/ls180.v:3572$221_Y + end + attribute \src "build/ls180/gateware/ls180.v:3626.9-3626.45" + cell $not $not$build/ls180/gateware/ls180.v:3626$226 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine3_refresh_req + connect \Y $not$build/ls180/gateware/ls180.v:3626$226_Y + end + attribute \src "build/ls180/gateware/ls180.v:3668.149-3668.187" + cell $not $not$build/ls180/gateware/ls180.v:3668$229 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_req_cmd_payload_cas + connect \Y $not$build/ls180/gateware/ls180.v:3668$229_Y + end + attribute \src "build/ls180/gateware/ls180.v:3668.193-3668.230" + cell $not $not$build/ls180/gateware/ls180.v:3668$231 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_req_cmd_payload_we + connect \Y $not$build/ls180/gateware/ls180.v:3668$231_Y + end + attribute \src "build/ls180/gateware/ls180.v:3669.149-3669.187" + cell $not $not$build/ls180/gateware/ls180.v:3669$235 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_req_cmd_payload_cas + connect \Y $not$build/ls180/gateware/ls180.v:3669$235_Y + end + attribute \src "build/ls180/gateware/ls180.v:3669.193-3669.230" + cell $not $not$build/ls180/gateware/ls180.v:3669$237 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_req_cmd_payload_we + connect \Y $not$build/ls180/gateware/ls180.v:3669$237_Y + end + attribute \src "build/ls180/gateware/ls180.v:3685.43-3685.73" + cell $not $not$build/ls180/gateware/ls180.v:3685$265 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 2 + connect \A \main_sdram_interface_wdata_we + connect \Y $not$build/ls180/gateware/ls180.v:3685$265_Y + end + attribute \src "build/ls180/gateware/ls180.v:3688.205-3688.245" + cell $not $not$build/ls180/gateware/ls180.v:3688$268 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine0_cmd_payload_cas + connect \Y $not$build/ls180/gateware/ls180.v:3688$268_Y + end + attribute \src "build/ls180/gateware/ls180.v:3688.251-3688.290" + cell $not $not$build/ls180/gateware/ls180.v:3688$270 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine0_cmd_payload_we + connect \Y $not$build/ls180/gateware/ls180.v:3688$270_Y + end + attribute \src "build/ls180/gateware/ls180.v:3688.159-3688.292" + cell $not $not$build/ls180/gateware/ls180.v:3688$272 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$build/ls180/gateware/ls180.v:3688$271_Y + connect \Y $not$build/ls180/gateware/ls180.v:3688$272_Y + end + attribute \src "build/ls180/gateware/ls180.v:3689.205-3689.245" + cell $not $not$build/ls180/gateware/ls180.v:3689$281 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine1_cmd_payload_cas + connect \Y $not$build/ls180/gateware/ls180.v:3689$281_Y + end + attribute \src "build/ls180/gateware/ls180.v:3689.251-3689.290" + cell $not $not$build/ls180/gateware/ls180.v:3689$283 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine1_cmd_payload_we + connect \Y $not$build/ls180/gateware/ls180.v:3689$283_Y + end + attribute \src "build/ls180/gateware/ls180.v:3689.159-3689.292" + cell $not $not$build/ls180/gateware/ls180.v:3689$285 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$build/ls180/gateware/ls180.v:3689$284_Y + connect \Y $not$build/ls180/gateware/ls180.v:3689$285_Y + end + attribute \src "build/ls180/gateware/ls180.v:3690.205-3690.245" + cell $not $not$build/ls180/gateware/ls180.v:3690$294 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine2_cmd_payload_cas + connect \Y $not$build/ls180/gateware/ls180.v:3690$294_Y + end + attribute \src "build/ls180/gateware/ls180.v:3690.251-3690.290" + cell $not $not$build/ls180/gateware/ls180.v:3690$296 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine2_cmd_payload_we + connect \Y $not$build/ls180/gateware/ls180.v:3690$296_Y + end + attribute \src "build/ls180/gateware/ls180.v:3690.159-3690.292" + cell $not $not$build/ls180/gateware/ls180.v:3690$298 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$build/ls180/gateware/ls180.v:3690$297_Y + connect \Y $not$build/ls180/gateware/ls180.v:3690$298_Y + end + attribute \src "build/ls180/gateware/ls180.v:3691.205-3691.245" + cell $not $not$build/ls180/gateware/ls180.v:3691$307 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine3_cmd_payload_cas + connect \Y $not$build/ls180/gateware/ls180.v:3691$307_Y + end + attribute \src "build/ls180/gateware/ls180.v:3691.251-3691.290" + cell $not $not$build/ls180/gateware/ls180.v:3691$309 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine3_cmd_payload_we + connect \Y $not$build/ls180/gateware/ls180.v:3691$309_Y + end + attribute \src "build/ls180/gateware/ls180.v:3691.159-3691.292" + cell $not $not$build/ls180/gateware/ls180.v:3691$311 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$build/ls180/gateware/ls180.v:3691$310_Y + connect \Y $not$build/ls180/gateware/ls180.v:3691$311_Y + end + attribute \src "build/ls180/gateware/ls180.v:3718.71-3718.103" + cell $not $not$build/ls180/gateware/ls180.v:3718$322 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_cmd_cmd_valid + connect \Y $not$build/ls180/gateware/ls180.v:3718$322_Y + end + attribute \src "build/ls180/gateware/ls180.v:3721.205-3721.245" + cell $not $not$build/ls180/gateware/ls180.v:3721$326 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine0_cmd_payload_cas + connect \Y $not$build/ls180/gateware/ls180.v:3721$326_Y + end + attribute \src "build/ls180/gateware/ls180.v:3721.251-3721.290" + cell $not $not$build/ls180/gateware/ls180.v:3721$328 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine0_cmd_payload_we + connect \Y $not$build/ls180/gateware/ls180.v:3721$328_Y + end + attribute \src "build/ls180/gateware/ls180.v:3721.159-3721.292" + cell $not $not$build/ls180/gateware/ls180.v:3721$330 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$build/ls180/gateware/ls180.v:3721$329_Y + connect \Y $not$build/ls180/gateware/ls180.v:3721$330_Y + end + attribute \src "build/ls180/gateware/ls180.v:3722.205-3722.245" + cell $not $not$build/ls180/gateware/ls180.v:3722$339 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine1_cmd_payload_cas + connect \Y $not$build/ls180/gateware/ls180.v:3722$339_Y + end + attribute \src "build/ls180/gateware/ls180.v:3722.251-3722.290" + cell $not $not$build/ls180/gateware/ls180.v:3722$341 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine1_cmd_payload_we + connect \Y $not$build/ls180/gateware/ls180.v:3722$341_Y + end + attribute \src "build/ls180/gateware/ls180.v:3722.159-3722.292" + cell $not $not$build/ls180/gateware/ls180.v:3722$343 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$build/ls180/gateware/ls180.v:3722$342_Y + connect \Y $not$build/ls180/gateware/ls180.v:3722$343_Y + end + attribute \src "build/ls180/gateware/ls180.v:3723.205-3723.245" + cell $not $not$build/ls180/gateware/ls180.v:3723$352 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine2_cmd_payload_cas + connect \Y $not$build/ls180/gateware/ls180.v:3723$352_Y + end + attribute \src "build/ls180/gateware/ls180.v:3723.251-3723.290" + cell $not $not$build/ls180/gateware/ls180.v:3723$354 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine2_cmd_payload_we + connect \Y $not$build/ls180/gateware/ls180.v:3723$354_Y + end + attribute \src "build/ls180/gateware/ls180.v:3723.159-3723.292" + cell $not $not$build/ls180/gateware/ls180.v:3723$356 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$build/ls180/gateware/ls180.v:3723$355_Y + connect \Y $not$build/ls180/gateware/ls180.v:3723$356_Y + end + attribute \src "build/ls180/gateware/ls180.v:3724.205-3724.245" + cell $not $not$build/ls180/gateware/ls180.v:3724$365 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine3_cmd_payload_cas + connect \Y $not$build/ls180/gateware/ls180.v:3724$365_Y + end + attribute \src "build/ls180/gateware/ls180.v:3724.251-3724.290" + cell $not $not$build/ls180/gateware/ls180.v:3724$367 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine3_cmd_payload_we + connect \Y $not$build/ls180/gateware/ls180.v:3724$367_Y + end + attribute \src "build/ls180/gateware/ls180.v:3724.159-3724.292" + cell $not $not$build/ls180/gateware/ls180.v:3724$369 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$build/ls180/gateware/ls180.v:3724$368_Y + connect \Y $not$build/ls180/gateware/ls180.v:3724$369_Y + end + attribute \src "build/ls180/gateware/ls180.v:3787.71-3787.103" + cell $not $not$build/ls180/gateware/ls180.v:3787$408 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_req_cmd_valid + connect \Y $not$build/ls180/gateware/ls180.v:3787$408_Y + end + attribute \src "build/ls180/gateware/ls180.v:3808.112-3808.150" + cell $not $not$build/ls180/gateware/ls180.v:3808$411 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_req_cmd_payload_cas + connect \Y $not$build/ls180/gateware/ls180.v:3808$411_Y + end + attribute \src "build/ls180/gateware/ls180.v:3808.156-3808.193" + cell $not $not$build/ls180/gateware/ls180.v:3808$413 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_req_cmd_payload_we + connect \Y $not$build/ls180/gateware/ls180.v:3808$413_Y + end + attribute \src "build/ls180/gateware/ls180.v:3808.68-3808.195" + cell $not $not$build/ls180/gateware/ls180.v:3808$415 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$build/ls180/gateware/ls180.v:3808$414_Y + connect \Y $not$build/ls180/gateware/ls180.v:3808$415_Y + end + attribute \src "build/ls180/gateware/ls180.v:3816.11-3816.38" + cell $not $not$build/ls180/gateware/ls180.v:3816$418 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_write_available + connect \Y $not$build/ls180/gateware/ls180.v:3816$418_Y + end + attribute \src "build/ls180/gateware/ls180.v:3846.112-3846.150" + cell $not $not$build/ls180/gateware/ls180.v:3846$420 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_req_cmd_payload_cas + connect \Y $not$build/ls180/gateware/ls180.v:3846$420_Y + end + attribute \src "build/ls180/gateware/ls180.v:3846.156-3846.193" + cell $not $not$build/ls180/gateware/ls180.v:3846$422 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_req_cmd_payload_we + connect \Y $not$build/ls180/gateware/ls180.v:3846$422_Y + end + attribute \src "build/ls180/gateware/ls180.v:3846.68-3846.195" + cell $not $not$build/ls180/gateware/ls180.v:3846$424 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$build/ls180/gateware/ls180.v:3846$423_Y + connect \Y $not$build/ls180/gateware/ls180.v:3846$424_Y + end + attribute \src "build/ls180/gateware/ls180.v:3854.11-3854.37" + cell $not $not$build/ls180/gateware/ls180.v:3854$427 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_read_available + connect \Y $not$build/ls180/gateware/ls180.v:3854$427_Y + end + attribute \src "build/ls180/gateware/ls180.v:3864.87-3864.331" + cell $not $not$build/ls180/gateware/ls180.v:3864$439 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$build/ls180/gateware/ls180.v:3864$438_Y + connect \Y $not$build/ls180/gateware/ls180.v:3864$439_Y + end + attribute \src "build/ls180/gateware/ls180.v:3865.35-3865.68" + cell $not $not$build/ls180/gateware/ls180.v:3865$442 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_interface_bank0_valid + connect \Y $not$build/ls180/gateware/ls180.v:3865$442_Y + end + attribute \src "build/ls180/gateware/ls180.v:3865.73-3865.105" + cell $not $not$build/ls180/gateware/ls180.v:3865$443 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_interface_bank0_lock + connect \Y $not$build/ls180/gateware/ls180.v:3865$443_Y + end + attribute \src "build/ls180/gateware/ls180.v:3869.87-3869.331" + cell $not $not$build/ls180/gateware/ls180.v:3869$455 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$build/ls180/gateware/ls180.v:3869$454_Y + connect \Y $not$build/ls180/gateware/ls180.v:3869$455_Y + end + attribute \src "build/ls180/gateware/ls180.v:3870.35-3870.68" + cell $not $not$build/ls180/gateware/ls180.v:3870$458 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_interface_bank1_valid + connect \Y $not$build/ls180/gateware/ls180.v:3870$458_Y + end + attribute \src "build/ls180/gateware/ls180.v:3870.73-3870.105" + cell $not $not$build/ls180/gateware/ls180.v:3870$459 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_interface_bank1_lock + connect \Y $not$build/ls180/gateware/ls180.v:3870$459_Y + end + attribute \src "build/ls180/gateware/ls180.v:3874.87-3874.331" + cell $not $not$build/ls180/gateware/ls180.v:3874$471 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$build/ls180/gateware/ls180.v:3874$470_Y + connect \Y $not$build/ls180/gateware/ls180.v:3874$471_Y + end + attribute \src "build/ls180/gateware/ls180.v:3875.35-3875.68" + cell $not $not$build/ls180/gateware/ls180.v:3875$474 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_interface_bank2_valid + connect \Y $not$build/ls180/gateware/ls180.v:3875$474_Y + end + attribute \src "build/ls180/gateware/ls180.v:3875.73-3875.105" + cell $not $not$build/ls180/gateware/ls180.v:3875$475 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_interface_bank2_lock + connect \Y $not$build/ls180/gateware/ls180.v:3875$475_Y + end + attribute \src "build/ls180/gateware/ls180.v:3879.87-3879.331" + cell $not $not$build/ls180/gateware/ls180.v:3879$487 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$build/ls180/gateware/ls180.v:3879$486_Y + connect \Y $not$build/ls180/gateware/ls180.v:3879$487_Y + end + attribute \src "build/ls180/gateware/ls180.v:3880.35-3880.68" + cell $not $not$build/ls180/gateware/ls180.v:3880$490 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_interface_bank3_valid + connect \Y $not$build/ls180/gateware/ls180.v:3880$490_Y + end + attribute \src "build/ls180/gateware/ls180.v:3880.73-3880.105" + cell $not $not$build/ls180/gateware/ls180.v:3880$491 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_interface_bank3_lock + connect \Y $not$build/ls180/gateware/ls180.v:3880$491_Y + end + attribute \src "build/ls180/gateware/ls180.v:3884.128-3884.372" + cell $not $not$build/ls180/gateware/ls180.v:3884$504 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$build/ls180/gateware/ls180.v:3884$503_Y + connect \Y $not$build/ls180/gateware/ls180.v:3884$504_Y + end + attribute \src "build/ls180/gateware/ls180.v:3884.502-3884.746" + cell $not $not$build/ls180/gateware/ls180.v:3884$520 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$build/ls180/gateware/ls180.v:3884$519_Y + connect \Y $not$build/ls180/gateware/ls180.v:3884$520_Y + end + attribute \src "build/ls180/gateware/ls180.v:3884.876-3884.1120" + cell $not $not$build/ls180/gateware/ls180.v:3884$536 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$build/ls180/gateware/ls180.v:3884$535_Y + connect \Y $not$build/ls180/gateware/ls180.v:3884$536_Y + end + attribute \src "build/ls180/gateware/ls180.v:3884.1250-3884.1494" + cell $not $not$build/ls180/gateware/ls180.v:3884$552 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$build/ls180/gateware/ls180.v:3884$551_Y + connect \Y $not$build/ls180/gateware/ls180.v:3884$552_Y + end + attribute \src "build/ls180/gateware/ls180.v:3906.32-3906.50" + cell $not $not$build/ls180/gateware/ls180.v:3906$558 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_wb_sdram_cyc + connect \Y $not$build/ls180/gateware/ls180.v:3906$558_Y + end + attribute \src "build/ls180/gateware/ls180.v:3945.30-3945.50" + cell $not $not$build/ls180/gateware/ls180.v:3945$563 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_converter_skip + connect \Y $not$build/ls180/gateware/ls180.v:3945$563_Y + end + attribute \src "build/ls180/gateware/ls180.v:3946.30-3946.50" + cell $not $not$build/ls180/gateware/ls180.v:3946$564 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_converter_skip + connect \Y $not$build/ls180/gateware/ls180.v:3946$564_Y + end + attribute \src "build/ls180/gateware/ls180.v:3971.27-3971.48" + cell $not $not$build/ls180/gateware/ls180.v:3971$570 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_litedram_wb_cyc + connect \Y $not$build/ls180/gateware/ls180.v:3971$570_Y + end + attribute \src "build/ls180/gateware/ls180.v:3972.30-3972.50" + cell $not $not$build/ls180/gateware/ls180.v:3972$571 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_litedram_wb_we + connect \Y $not$build/ls180/gateware/ls180.v:3972$571_Y + end + attribute \src "build/ls180/gateware/ls180.v:3973.80-3973.98" + cell $not $not$build/ls180/gateware/ls180.v:3973$573 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_cmd_consumed + connect \Y $not$build/ls180/gateware/ls180.v:3973$573_Y + end + attribute \src "build/ls180/gateware/ls180.v:3974.107-3974.127" + cell $not $not$build/ls180/gateware/ls180.v:3974$577 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_wdata_consumed + connect \Y $not$build/ls180/gateware/ls180.v:3974$577_Y + end + attribute \src "build/ls180/gateware/ls180.v:3975.78-3975.103" + cell $not $not$build/ls180/gateware/ls180.v:3975$580 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_port_cmd_payload_we + connect \Y $not$build/ls180/gateware/ls180.v:3975$580_Y + end + attribute \src "build/ls180/gateware/ls180.v:3976.91-3976.111" + cell $not $not$build/ls180/gateware/ls180.v:3976$583 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_litedram_wb_we + connect \Y $not$build/ls180/gateware/ls180.v:3976$583_Y + end + attribute \src "build/ls180/gateware/ls180.v:4094.62-4094.88" + cell $not $not$build/ls180/gateware/ls180.v:4094$622 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \libresocsim_clocker_clk_d + connect \Y $not$build/ls180/gateware/ls180.v:4094$622_Y + end + attribute \src "build/ls180/gateware/ls180.v:4235.55-4235.98" + cell $not $not$build/ls180/gateware/ls180.v:4235$636 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \libresocsim_cmdr_cmdr_converter_strobe_all + connect \Y $not$build/ls180/gateware/ls180.v:4235$636_Y + end + attribute \src "build/ls180/gateware/ls180.v:4238.49-4238.88" + cell $not $not$build/ls180/gateware/ls180.v:4238$639 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \libresocsim_cmdr_cmdr_buf_source_valid + connect \Y $not$build/ls180/gateware/ls180.v:4238$639_Y + end + attribute \src "build/ls180/gateware/ls180.v:4362.56-4362.100" + cell $not $not$build/ls180/gateware/ls180.v:4362$657 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \libresocsim_dataw_crcr_converter_strobe_all + connect \Y $not$build/ls180/gateware/ls180.v:4362$657_Y + end + attribute \src "build/ls180/gateware/ls180.v:4365.50-4365.90" + cell $not $not$build/ls180/gateware/ls180.v:4365$660 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \libresocsim_dataw_crcr_buf_source_valid + connect \Y $not$build/ls180/gateware/ls180.v:4365$660_Y + end + attribute \src "build/ls180/gateware/ls180.v:4415.31-4415.60" + cell $not $not$build/ls180/gateware/ls180.v:4415$666 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \libresocsim_dataw_sink_valid + connect \Y $not$build/ls180/gateware/ls180.v:4415$666_Y + end + attribute \src "build/ls180/gateware/ls180.v:4496.57-4496.102" + cell $not $not$build/ls180/gateware/ls180.v:4496$672 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \libresocsim_datar_datar_converter_strobe_all + connect \Y $not$build/ls180/gateware/ls180.v:4496$672_Y + end + attribute \src "build/ls180/gateware/ls180.v:4499.51-4499.92" + cell $not $not$build/ls180/gateware/ls180.v:4499$675 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \libresocsim_datar_datar_buf_source_valid + connect \Y $not$build/ls180/gateware/ls180.v:4499$675_Y + end + attribute \src "build/ls180/gateware/ls180.v:4615.49-4615.88" + cell $not $not$build/ls180/gateware/ls180.v:4615$691 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \libresocsim_sdcore_crc16_checker_valid + connect \Y $not$build/ls180/gateware/ls180.v:4615$691_Y + end + attribute \src "build/ls180/gateware/ls180.v:5139.57-5139.102" + cell $not $not$build/ls180/gateware/ls180.v:5139$976 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \libresocsim_sdblock2mem_converter_strobe_all + connect \Y $not$build/ls180/gateware/ls180.v:5139$976_Y + end + attribute \src "build/ls180/gateware/ls180.v:5151.59-5151.116" + cell $not $not$build/ls180/gateware/ls180.v:5151$979 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \libresocsim_sdblock2mem_wishbonedmawriter_enable_storage + connect \Y $not$build/ls180/gateware/ls180.v:5151$979_Y + end + attribute \src "build/ls180/gateware/ls180.v:5210.45-5210.88" + cell $not $not$build/ls180/gateware/ls180.v:5210$986 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \libresocsim_sdmem2block_dma_enable_storage + connect \Y $not$build/ls180/gateware/ls180.v:5210$986_Y + end + attribute \src "build/ls180/gateware/ls180.v:5508.69-5508.88" + cell $not $not$build/ls180/gateware/ls180.v:5508$1051 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_shared_ack + connect \Y $not$build/ls180/gateware/ls180.v:5508$1051_Y + end + attribute \src "build/ls180/gateware/ls180.v:5525.63-5525.94" + cell $not $not$build/ls180/gateware/ls180.v:5525$1072 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface0_bank_bus_we + connect \Y $not$build/ls180/gateware/ls180.v:5525$1072_Y + end + attribute \src "build/ls180/gateware/ls180.v:5528.65-5528.96" + cell $not $not$build/ls180/gateware/ls180.v:5528$1079 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface0_bank_bus_we + connect \Y $not$build/ls180/gateware/ls180.v:5528$1079_Y + end + attribute \src "build/ls180/gateware/ls180.v:5531.65-5531.96" + cell $not $not$build/ls180/gateware/ls180.v:5531$1086 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface0_bank_bus_we + connect \Y $not$build/ls180/gateware/ls180.v:5531$1086_Y + end + attribute \src "build/ls180/gateware/ls180.v:5534.65-5534.96" + cell $not $not$build/ls180/gateware/ls180.v:5534$1093 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface0_bank_bus_we + connect \Y $not$build/ls180/gateware/ls180.v:5534$1093_Y + end + attribute \src "build/ls180/gateware/ls180.v:5537.65-5537.96" + cell $not $not$build/ls180/gateware/ls180.v:5537$1100 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface0_bank_bus_we + connect \Y $not$build/ls180/gateware/ls180.v:5537$1100_Y + end + attribute \src "build/ls180/gateware/ls180.v:5540.68-5540.99" + cell $not $not$build/ls180/gateware/ls180.v:5540$1107 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface0_bank_bus_we + connect \Y $not$build/ls180/gateware/ls180.v:5540$1107_Y + end + attribute \src "build/ls180/gateware/ls180.v:5543.68-5543.99" + cell $not $not$build/ls180/gateware/ls180.v:5543$1114 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface0_bank_bus_we + connect \Y $not$build/ls180/gateware/ls180.v:5543$1114_Y + end + attribute \src "build/ls180/gateware/ls180.v:5546.68-5546.99" + cell $not $not$build/ls180/gateware/ls180.v:5546$1121 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface0_bank_bus_we + connect \Y $not$build/ls180/gateware/ls180.v:5546$1121_Y + end + attribute \src "build/ls180/gateware/ls180.v:5549.68-5549.99" + cell $not $not$build/ls180/gateware/ls180.v:5549$1128 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface0_bank_bus_we + connect \Y $not$build/ls180/gateware/ls180.v:5549$1128_Y + end + attribute \src "build/ls180/gateware/ls180.v:5563.59-5563.90" + cell $not $not$build/ls180/gateware/ls180.v:5563$1136 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface1_bank_bus_we + connect \Y $not$build/ls180/gateware/ls180.v:5563$1136_Y + end + attribute \src "build/ls180/gateware/ls180.v:5569.59-5569.90" + cell $not $not$build/ls180/gateware/ls180.v:5569$1144 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface2_bank_bus_we + connect \Y $not$build/ls180/gateware/ls180.v:5569$1144_Y + end + attribute \src "build/ls180/gateware/ls180.v:5575.66-5575.97" + cell $not $not$build/ls180/gateware/ls180.v:5575$1152 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface3_bank_bus_we + connect \Y $not$build/ls180/gateware/ls180.v:5575$1152_Y + end + attribute \src "build/ls180/gateware/ls180.v:5578.66-5578.97" + cell $not $not$build/ls180/gateware/ls180.v:5578$1159 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface3_bank_bus_we + connect \Y $not$build/ls180/gateware/ls180.v:5578$1159_Y + end + attribute \src "build/ls180/gateware/ls180.v:5581.66-5581.97" + cell $not $not$build/ls180/gateware/ls180.v:5581$1166 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface3_bank_bus_we + connect \Y $not$build/ls180/gateware/ls180.v:5581$1166_Y + end + attribute \src "build/ls180/gateware/ls180.v:5584.66-5584.97" + cell $not $not$build/ls180/gateware/ls180.v:5584$1173 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface3_bank_bus_we + connect \Y $not$build/ls180/gateware/ls180.v:5584$1173_Y + end + attribute \src "build/ls180/gateware/ls180.v:5587.66-5587.97" + cell $not $not$build/ls180/gateware/ls180.v:5587$1180 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface3_bank_bus_we + connect \Y $not$build/ls180/gateware/ls180.v:5587$1180_Y + end + attribute \src "build/ls180/gateware/ls180.v:5590.66-5590.97" + cell $not $not$build/ls180/gateware/ls180.v:5590$1187 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface3_bank_bus_we + connect \Y $not$build/ls180/gateware/ls180.v:5590$1187_Y + end + attribute \src "build/ls180/gateware/ls180.v:5593.66-5593.97" + cell $not $not$build/ls180/gateware/ls180.v:5593$1194 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface3_bank_bus_we + connect \Y $not$build/ls180/gateware/ls180.v:5593$1194_Y + end + attribute \src "build/ls180/gateware/ls180.v:5596.66-5596.97" + cell $not $not$build/ls180/gateware/ls180.v:5596$1201 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface3_bank_bus_we + connect \Y $not$build/ls180/gateware/ls180.v:5596$1201_Y + end + attribute \src "build/ls180/gateware/ls180.v:5599.68-5599.99" + cell $not $not$build/ls180/gateware/ls180.v:5599$1208 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface3_bank_bus_we + connect \Y $not$build/ls180/gateware/ls180.v:5599$1208_Y + end + attribute \src "build/ls180/gateware/ls180.v:5602.68-5602.99" + cell $not $not$build/ls180/gateware/ls180.v:5602$1215 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface3_bank_bus_we + connect \Y $not$build/ls180/gateware/ls180.v:5602$1215_Y + end + attribute \src "build/ls180/gateware/ls180.v:5605.68-5605.99" + cell $not $not$build/ls180/gateware/ls180.v:5605$1222 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface3_bank_bus_we + connect \Y $not$build/ls180/gateware/ls180.v:5605$1222_Y + end + attribute \src "build/ls180/gateware/ls180.v:5608.68-5608.99" + cell $not $not$build/ls180/gateware/ls180.v:5608$1229 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface3_bank_bus_we + connect \Y $not$build/ls180/gateware/ls180.v:5608$1229_Y + end + attribute \src "build/ls180/gateware/ls180.v:5611.68-5611.99" + cell $not $not$build/ls180/gateware/ls180.v:5611$1236 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface3_bank_bus_we + connect \Y $not$build/ls180/gateware/ls180.v:5611$1236_Y + end + attribute \src "build/ls180/gateware/ls180.v:5614.65-5614.96" + cell $not $not$build/ls180/gateware/ls180.v:5614$1243 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface3_bank_bus_we + connect \Y $not$build/ls180/gateware/ls180.v:5614$1243_Y + end + attribute \src "build/ls180/gateware/ls180.v:5617.66-5617.97" + cell $not $not$build/ls180/gateware/ls180.v:5617$1250 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface3_bank_bus_we + connect \Y $not$build/ls180/gateware/ls180.v:5617$1250_Y + end + attribute \src "build/ls180/gateware/ls180.v:5637.70-5637.101" + cell $not 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parameter \Y_WIDTH 1 + connect \A \builder_interface4_bank_bus_we + connect \Y $not$build/ls180/gateware/ls180.v:5646$1279_Y + end + attribute \src "build/ls180/gateware/ls180.v:5649.69-5649.100" + cell $not $not$build/ls180/gateware/ls180.v:5649$1286 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface4_bank_bus_we + connect \Y $not$build/ls180/gateware/ls180.v:5649$1286_Y + end + attribute \src "build/ls180/gateware/ls180.v:5652.69-5652.100" + cell $not $not$build/ls180/gateware/ls180.v:5652$1293 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface4_bank_bus_we + connect \Y $not$build/ls180/gateware/ls180.v:5652$1293_Y + end + attribute \src "build/ls180/gateware/ls180.v:5655.69-5655.100" + cell $not $not$build/ls180/gateware/ls180.v:5655$1300 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface4_bank_bus_we + connect \Y $not$build/ls180/gateware/ls180.v:5655$1300_Y + end + attribute \src "build/ls180/gateware/ls180.v:5658.69-5658.100" + cell $not $not$build/ls180/gateware/ls180.v:5658$1307 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface4_bank_bus_we + connect \Y $not$build/ls180/gateware/ls180.v:5658$1307_Y + end + attribute \src "build/ls180/gateware/ls180.v:5661.67-5661.98" + cell $not $not$build/ls180/gateware/ls180.v:5661$1314 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface4_bank_bus_we + connect \Y $not$build/ls180/gateware/ls180.v:5661$1314_Y + end + attribute \src "build/ls180/gateware/ls180.v:5664.71-5664.102" + cell $not $not$build/ls180/gateware/ls180.v:5664$1321 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface4_bank_bus_we + connect \Y $not$build/ls180/gateware/ls180.v:5664$1321_Y + end + attribute \src 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parameter \Y_WIDTH 1 + connect \A \builder_interface4_bank_bus_we + connect \Y $not$build/ls180/gateware/ls180.v:5685$1370_Y + end + attribute \src "build/ls180/gateware/ls180.v:5688.70-5688.101" + cell $not $not$build/ls180/gateware/ls180.v:5688$1377 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface4_bank_bus_we + connect \Y $not$build/ls180/gateware/ls180.v:5688$1377_Y + end + attribute \src "build/ls180/gateware/ls180.v:5691.70-5691.101" + cell $not $not$build/ls180/gateware/ls180.v:5691$1384 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface4_bank_bus_we + connect \Y $not$build/ls180/gateware/ls180.v:5691$1384_Y + end + attribute \src "build/ls180/gateware/ls180.v:5694.70-5694.101" + cell $not $not$build/ls180/gateware/ls180.v:5694$1391 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface4_bank_bus_we + connect \Y $not$build/ls180/gateware/ls180.v:5694$1391_Y + end + attribute \src "build/ls180/gateware/ls180.v:5697.70-5697.101" + cell $not $not$build/ls180/gateware/ls180.v:5697$1398 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface4_bank_bus_we + connect \Y $not$build/ls180/gateware/ls180.v:5697$1398_Y + end + attribute \src "build/ls180/gateware/ls180.v:5700.70-5700.101" + cell $not $not$build/ls180/gateware/ls180.v:5700$1405 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface4_bank_bus_we + connect \Y $not$build/ls180/gateware/ls180.v:5700$1405_Y + end + attribute \src "build/ls180/gateware/ls180.v:5703.70-5703.101" + cell $not $not$build/ls180/gateware/ls180.v:5703$1412 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface4_bank_bus_we + connect \Y $not$build/ls180/gateware/ls180.v:5703$1412_Y + end + attribute \src "build/ls180/gateware/ls180.v:5706.70-5706.101" + cell $not $not$build/ls180/gateware/ls180.v:5706$1419 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface4_bank_bus_we + connect \Y $not$build/ls180/gateware/ls180.v:5706$1419_Y + end + attribute \src "build/ls180/gateware/ls180.v:5709.70-5709.101" + cell $not $not$build/ls180/gateware/ls180.v:5709$1426 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface4_bank_bus_we + connect \Y $not$build/ls180/gateware/ls180.v:5709$1426_Y + end + attribute \src "build/ls180/gateware/ls180.v:5712.66-5712.97" + cell $not $not$build/ls180/gateware/ls180.v:5712$1433 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface4_bank_bus_we + connect \Y $not$build/ls180/gateware/ls180.v:5712$1433_Y + end + attribute \src "build/ls180/gateware/ls180.v:5715.67-5715.98" + cell $not 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parameter \Y_WIDTH 1 + connect \A \builder_interface4_bank_bus_we + connect \Y $not$build/ls180/gateware/ls180.v:5724$1461_Y + end + attribute \src "build/ls180/gateware/ls180.v:5727.69-5727.100" + cell $not $not$build/ls180/gateware/ls180.v:5727$1468 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface4_bank_bus_we + connect \Y $not$build/ls180/gateware/ls180.v:5727$1468_Y + end + attribute \src "build/ls180/gateware/ls180.v:5730.69-5730.100" + cell $not $not$build/ls180/gateware/ls180.v:5730$1475 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface4_bank_bus_we + connect \Y $not$build/ls180/gateware/ls180.v:5730$1475_Y + end + attribute \src "build/ls180/gateware/ls180.v:5733.69-5733.100" + cell $not $not$build/ls180/gateware/ls180.v:5733$1482 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface4_bank_bus_we + connect \Y $not$build/ls180/gateware/ls180.v:5733$1482_Y + end + attribute \src "build/ls180/gateware/ls180.v:5772.66-5772.97" + cell $not $not$build/ls180/gateware/ls180.v:5772$1490 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_we + connect \Y $not$build/ls180/gateware/ls180.v:5772$1490_Y + end + attribute \src "build/ls180/gateware/ls180.v:5775.66-5775.97" + cell $not $not$build/ls180/gateware/ls180.v:5775$1497 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_we + connect \Y $not$build/ls180/gateware/ls180.v:5775$1497_Y + end + attribute \src "build/ls180/gateware/ls180.v:5778.66-5778.97" + cell $not $not$build/ls180/gateware/ls180.v:5778$1504 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_we + connect \Y $not$build/ls180/gateware/ls180.v:5778$1504_Y + end + attribute \src "build/ls180/gateware/ls180.v:5781.66-5781.97" + cell $not $not$build/ls180/gateware/ls180.v:5781$1511 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_we + connect \Y $not$build/ls180/gateware/ls180.v:5781$1511_Y + end + attribute \src "build/ls180/gateware/ls180.v:5784.66-5784.97" + cell $not $not$build/ls180/gateware/ls180.v:5784$1518 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_we + connect \Y $not$build/ls180/gateware/ls180.v:5784$1518_Y + end + attribute \src "build/ls180/gateware/ls180.v:5787.66-5787.97" + cell $not $not$build/ls180/gateware/ls180.v:5787$1525 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_we + connect \Y $not$build/ls180/gateware/ls180.v:5787$1525_Y + end + attribute \src "build/ls180/gateware/ls180.v:5790.66-5790.97" + cell $not $not$build/ls180/gateware/ls180.v:5790$1532 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_we + connect \Y $not$build/ls180/gateware/ls180.v:5790$1532_Y + end + attribute \src "build/ls180/gateware/ls180.v:5793.66-5793.97" + cell $not $not$build/ls180/gateware/ls180.v:5793$1539 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_we + connect \Y $not$build/ls180/gateware/ls180.v:5793$1539_Y + end + attribute \src "build/ls180/gateware/ls180.v:5796.68-5796.99" + cell $not $not$build/ls180/gateware/ls180.v:5796$1546 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_we + connect \Y $not$build/ls180/gateware/ls180.v:5796$1546_Y + end + attribute \src "build/ls180/gateware/ls180.v:5799.68-5799.99" + cell $not $not$build/ls180/gateware/ls180.v:5799$1553 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_we + connect \Y $not$build/ls180/gateware/ls180.v:5799$1553_Y + end + attribute \src "build/ls180/gateware/ls180.v:5802.68-5802.99" + cell $not $not$build/ls180/gateware/ls180.v:5802$1560 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_we + connect \Y $not$build/ls180/gateware/ls180.v:5802$1560_Y + end + attribute \src "build/ls180/gateware/ls180.v:5805.68-5805.99" + cell $not $not$build/ls180/gateware/ls180.v:5805$1567 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_we + connect \Y $not$build/ls180/gateware/ls180.v:5805$1567_Y + end + attribute \src "build/ls180/gateware/ls180.v:5808.68-5808.99" + cell $not $not$build/ls180/gateware/ls180.v:5808$1574 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_we + connect \Y $not$build/ls180/gateware/ls180.v:5808$1574_Y + end + attribute \src "build/ls180/gateware/ls180.v:5811.65-5811.96" + cell $not $not$build/ls180/gateware/ls180.v:5811$1581 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_we + connect \Y $not$build/ls180/gateware/ls180.v:5811$1581_Y + end + attribute \src "build/ls180/gateware/ls180.v:5814.66-5814.97" + cell $not $not$build/ls180/gateware/ls180.v:5814$1588 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_we + connect \Y $not$build/ls180/gateware/ls180.v:5814$1588_Y + end + attribute \src "build/ls180/gateware/ls180.v:5817.68-5817.99" + cell $not $not$build/ls180/gateware/ls180.v:5817$1595 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_we + connect \Y $not$build/ls180/gateware/ls180.v:5817$1595_Y + end + attribute \src "build/ls180/gateware/ls180.v:5820.68-5820.99" + cell $not $not$build/ls180/gateware/ls180.v:5820$1602 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_we + connect \Y $not$build/ls180/gateware/ls180.v:5820$1602_Y + end + attribute \src "build/ls180/gateware/ls180.v:5823.68-5823.99" + cell $not $not$build/ls180/gateware/ls180.v:5823$1609 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_we + connect \Y $not$build/ls180/gateware/ls180.v:5823$1609_Y + end + attribute \src "build/ls180/gateware/ls180.v:5826.68-5826.99" + cell $not $not$build/ls180/gateware/ls180.v:5826$1616 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface5_bank_bus_we + connect \Y $not$build/ls180/gateware/ls180.v:5826$1616_Y + end + attribute \src "build/ls180/gateware/ls180.v:5851.68-5851.99" + cell $not $not$build/ls180/gateware/ls180.v:5851$1624 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_we + connect \Y $not$build/ls180/gateware/ls180.v:5851$1624_Y + end + attribute \src "build/ls180/gateware/ls180.v:5854.73-5854.104" + cell $not $not$build/ls180/gateware/ls180.v:5854$1631 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_we + connect \Y $not$build/ls180/gateware/ls180.v:5854$1631_Y + end + attribute \src "build/ls180/gateware/ls180.v:5857.73-5857.104" + cell $not $not$build/ls180/gateware/ls180.v:5857$1638 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_we + connect \Y $not$build/ls180/gateware/ls180.v:5857$1638_Y + end + attribute \src "build/ls180/gateware/ls180.v:5860.67-5860.98" + cell $not $not$build/ls180/gateware/ls180.v:5860$1645 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface6_bank_bus_we + connect \Y $not$build/ls180/gateware/ls180.v:5860$1645_Y + end + attribute \src "build/ls180/gateware/ls180.v:5868.70-5868.101" + cell $not $not$build/ls180/gateware/ls180.v:5868$1653 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface7_bank_bus_we + connect \Y $not$build/ls180/gateware/ls180.v:5868$1653_Y + end + attribute \src "build/ls180/gateware/ls180.v:5871.74-5871.105" + cell $not $not$build/ls180/gateware/ls180.v:5871$1660 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface7_bank_bus_we + connect \Y $not$build/ls180/gateware/ls180.v:5871$1660_Y + end + attribute \src "build/ls180/gateware/ls180.v:5874.64-5874.95" + cell $not $not$build/ls180/gateware/ls180.v:5874$1667 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface7_bank_bus_we + connect \Y $not$build/ls180/gateware/ls180.v:5874$1667_Y + end + attribute \src "build/ls180/gateware/ls180.v:5877.74-5877.105" + cell $not $not$build/ls180/gateware/ls180.v:5877$1674 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface7_bank_bus_we + connect \Y $not$build/ls180/gateware/ls180.v:5877$1674_Y + end + attribute \src "build/ls180/gateware/ls180.v:5880.74-5880.105" + cell $not $not$build/ls180/gateware/ls180.v:5880$1681 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface7_bank_bus_we + connect \Y $not$build/ls180/gateware/ls180.v:5880$1681_Y + end + attribute \src "build/ls180/gateware/ls180.v:5883.75-5883.106" + cell $not $not$build/ls180/gateware/ls180.v:5883$1688 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface7_bank_bus_we + connect \Y $not$build/ls180/gateware/ls180.v:5883$1688_Y + end + attribute \src "build/ls180/gateware/ls180.v:5886.73-5886.104" + cell $not $not$build/ls180/gateware/ls180.v:5886$1695 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface7_bank_bus_we + connect \Y $not$build/ls180/gateware/ls180.v:5886$1695_Y + end + attribute \src "build/ls180/gateware/ls180.v:5889.73-5889.104" + cell $not $not$build/ls180/gateware/ls180.v:5889$1702 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface7_bank_bus_we + connect \Y $not$build/ls180/gateware/ls180.v:5889$1702_Y + end + attribute \src "build/ls180/gateware/ls180.v:5892.73-5892.104" + cell $not $not$build/ls180/gateware/ls180.v:5892$1709 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface7_bank_bus_we + connect \Y $not$build/ls180/gateware/ls180.v:5892$1709_Y + end + attribute \src "build/ls180/gateware/ls180.v:5895.73-5895.104" + cell $not $not$build/ls180/gateware/ls180.v:5895$1716 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface7_bank_bus_we + connect \Y $not$build/ls180/gateware/ls180.v:5895$1716_Y + end + attribute \src "build/ls180/gateware/ls180.v:5913.65-5913.96" + cell $not $not$build/ls180/gateware/ls180.v:5913$1724 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface8_bank_bus_we + connect \Y $not$build/ls180/gateware/ls180.v:5913$1724_Y + end + attribute \src "build/ls180/gateware/ls180.v:5916.65-5916.96" + cell $not $not$build/ls180/gateware/ls180.v:5916$1731 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface8_bank_bus_we + connect \Y $not$build/ls180/gateware/ls180.v:5916$1731_Y + end + attribute \src "build/ls180/gateware/ls180.v:5919.63-5919.94" + cell $not $not$build/ls180/gateware/ls180.v:5919$1738 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface8_bank_bus_we + connect \Y $not$build/ls180/gateware/ls180.v:5919$1738_Y + end + attribute \src "build/ls180/gateware/ls180.v:5922.62-5922.93" + cell $not $not$build/ls180/gateware/ls180.v:5922$1745 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface8_bank_bus_we + connect \Y $not$build/ls180/gateware/ls180.v:5922$1745_Y + end + attribute \src "build/ls180/gateware/ls180.v:5925.61-5925.92" + cell $not $not$build/ls180/gateware/ls180.v:5925$1752 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface8_bank_bus_we + connect \Y $not$build/ls180/gateware/ls180.v:5925$1752_Y + end + attribute \src "build/ls180/gateware/ls180.v:5928.60-5928.91" + cell $not $not$build/ls180/gateware/ls180.v:5928$1759 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface8_bank_bus_we + connect \Y $not$build/ls180/gateware/ls180.v:5928$1759_Y + end + attribute \src "build/ls180/gateware/ls180.v:5931.66-5931.97" + cell $not $not$build/ls180/gateware/ls180.v:5931$1766 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface8_bank_bus_we + connect \Y $not$build/ls180/gateware/ls180.v:5931$1766_Y + end + attribute \src "build/ls180/gateware/ls180.v:5953.65-5953.96" + cell $not $not$build/ls180/gateware/ls180.v:5953$1775 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface9_bank_bus_we + connect \Y $not$build/ls180/gateware/ls180.v:5953$1775_Y + end + attribute \src "build/ls180/gateware/ls180.v:5956.65-5956.96" + cell $not $not$build/ls180/gateware/ls180.v:5956$1782 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface9_bank_bus_we + connect \Y $not$build/ls180/gateware/ls180.v:5956$1782_Y + end + attribute \src "build/ls180/gateware/ls180.v:5959.63-5959.94" + cell $not $not$build/ls180/gateware/ls180.v:5959$1789 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface9_bank_bus_we + connect \Y $not$build/ls180/gateware/ls180.v:5959$1789_Y + end + attribute \src "build/ls180/gateware/ls180.v:5962.62-5962.93" + cell $not $not$build/ls180/gateware/ls180.v:5962$1796 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface9_bank_bus_we + connect \Y $not$build/ls180/gateware/ls180.v:5962$1796_Y + end + attribute \src "build/ls180/gateware/ls180.v:5965.61-5965.92" + cell $not $not$build/ls180/gateware/ls180.v:5965$1803 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface9_bank_bus_we + connect \Y $not$build/ls180/gateware/ls180.v:5965$1803_Y + end + attribute \src "build/ls180/gateware/ls180.v:5968.60-5968.91" + cell $not $not$build/ls180/gateware/ls180.v:5968$1810 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface9_bank_bus_we + connect \Y $not$build/ls180/gateware/ls180.v:5968$1810_Y + end + attribute \src "build/ls180/gateware/ls180.v:5971.66-5971.97" + cell $not $not$build/ls180/gateware/ls180.v:5971$1817 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface9_bank_bus_we + connect \Y $not$build/ls180/gateware/ls180.v:5971$1817_Y + end + attribute \src "build/ls180/gateware/ls180.v:5974.69-5974.100" + cell $not $not$build/ls180/gateware/ls180.v:5974$1824 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface9_bank_bus_we + connect \Y $not$build/ls180/gateware/ls180.v:5974$1824_Y + end + attribute \src "build/ls180/gateware/ls180.v:5977.69-5977.100" + cell $not $not$build/ls180/gateware/ls180.v:5977$1831 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface9_bank_bus_we + connect \Y $not$build/ls180/gateware/ls180.v:5977$1831_Y + end + attribute \src "build/ls180/gateware/ls180.v:6001.64-6001.96" + cell $not $not$build/ls180/gateware/ls180.v:6001$1840 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface10_bank_bus_we + connect \Y $not$build/ls180/gateware/ls180.v:6001$1840_Y + end + attribute \src "build/ls180/gateware/ls180.v:6004.64-6004.96" + cell $not $not$build/ls180/gateware/ls180.v:6004$1847 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface10_bank_bus_we + connect \Y $not$build/ls180/gateware/ls180.v:6004$1847_Y + end + attribute \src "build/ls180/gateware/ls180.v:6007.64-6007.96" + cell $not $not$build/ls180/gateware/ls180.v:6007$1854 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface10_bank_bus_we + connect \Y $not$build/ls180/gateware/ls180.v:6007$1854_Y + end + attribute \src "build/ls180/gateware/ls180.v:6010.64-6010.96" + cell $not $not$build/ls180/gateware/ls180.v:6010$1861 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface10_bank_bus_we + connect \Y $not$build/ls180/gateware/ls180.v:6010$1861_Y + end + attribute \src "build/ls180/gateware/ls180.v:6013.66-6013.98" + cell $not $not$build/ls180/gateware/ls180.v:6013$1868 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface10_bank_bus_we + connect \Y $not$build/ls180/gateware/ls180.v:6013$1868_Y + end + attribute \src "build/ls180/gateware/ls180.v:6016.66-6016.98" + cell $not $not$build/ls180/gateware/ls180.v:6016$1875 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface10_bank_bus_we + connect \Y $not$build/ls180/gateware/ls180.v:6016$1875_Y + end + attribute \src "build/ls180/gateware/ls180.v:6019.66-6019.98" + cell $not $not$build/ls180/gateware/ls180.v:6019$1882 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface10_bank_bus_we + connect \Y $not$build/ls180/gateware/ls180.v:6019$1882_Y + end + attribute \src "build/ls180/gateware/ls180.v:6022.66-6022.98" + cell $not $not$build/ls180/gateware/ls180.v:6022$1889 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface10_bank_bus_we + connect \Y $not$build/ls180/gateware/ls180.v:6022$1889_Y + end + attribute \src "build/ls180/gateware/ls180.v:6025.62-6025.94" + cell $not $not$build/ls180/gateware/ls180.v:6025$1896 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface10_bank_bus_we + connect \Y $not$build/ls180/gateware/ls180.v:6025$1896_Y + end + attribute \src "build/ls180/gateware/ls180.v:6028.72-6028.104" + cell $not $not$build/ls180/gateware/ls180.v:6028$1903 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface10_bank_bus_we + connect \Y $not$build/ls180/gateware/ls180.v:6028$1903_Y + end + attribute \src "build/ls180/gateware/ls180.v:6031.65-6031.97" + cell $not $not$build/ls180/gateware/ls180.v:6031$1910 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface10_bank_bus_we + connect \Y $not$build/ls180/gateware/ls180.v:6031$1910_Y + end + attribute \src "build/ls180/gateware/ls180.v:6034.65-6034.97" + cell $not $not$build/ls180/gateware/ls180.v:6034$1917 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface10_bank_bus_we + connect \Y $not$build/ls180/gateware/ls180.v:6034$1917_Y + end + attribute \src "build/ls180/gateware/ls180.v:6037.65-6037.97" + cell $not $not$build/ls180/gateware/ls180.v:6037$1924 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface10_bank_bus_we + connect \Y $not$build/ls180/gateware/ls180.v:6037$1924_Y + end + attribute \src "build/ls180/gateware/ls180.v:6040.65-6040.97" + cell $not $not$build/ls180/gateware/ls180.v:6040$1931 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface10_bank_bus_we + connect \Y $not$build/ls180/gateware/ls180.v:6040$1931_Y + end + attribute \src "build/ls180/gateware/ls180.v:6043.83-6043.115" + cell $not $not$build/ls180/gateware/ls180.v:6043$1938 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface10_bank_bus_we + connect \Y $not$build/ls180/gateware/ls180.v:6043$1938_Y + end + attribute \src "build/ls180/gateware/ls180.v:6046.84-6046.116" + cell $not $not$build/ls180/gateware/ls180.v:6046$1945 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface10_bank_bus_we + connect \Y $not$build/ls180/gateware/ls180.v:6046$1945_Y + end + attribute \src "build/ls180/gateware/ls180.v:6049.69-6049.101" + cell $not $not$build/ls180/gateware/ls180.v:6049$1952 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface10_bank_bus_we + connect \Y $not$build/ls180/gateware/ls180.v:6049$1952_Y + end + attribute \src "build/ls180/gateware/ls180.v:6069.67-6069.99" + cell $not $not$build/ls180/gateware/ls180.v:6069$1960 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface11_bank_bus_we + connect \Y $not$build/ls180/gateware/ls180.v:6069$1960_Y + end + attribute \src "build/ls180/gateware/ls180.v:6072.65-6072.97" + cell $not $not$build/ls180/gateware/ls180.v:6072$1967 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface11_bank_bus_we + connect \Y $not$build/ls180/gateware/ls180.v:6072$1967_Y + end + attribute \src "build/ls180/gateware/ls180.v:6075.66-6075.98" + cell $not $not$build/ls180/gateware/ls180.v:6075$1974 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface11_bank_bus_we + connect \Y $not$build/ls180/gateware/ls180.v:6075$1974_Y + end + attribute \src "build/ls180/gateware/ls180.v:6078.82-6078.114" + cell $not $not$build/ls180/gateware/ls180.v:6078$1981 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface11_bank_bus_we + connect \Y $not$build/ls180/gateware/ls180.v:6078$1981_Y + end + attribute \src "build/ls180/gateware/ls180.v:6081.83-6081.115" + cell $not $not$build/ls180/gateware/ls180.v:6081$1988 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface11_bank_bus_we + connect \Y $not$build/ls180/gateware/ls180.v:6081$1988_Y + end + attribute \src "build/ls180/gateware/ls180.v:6084.69-6084.101" + cell $not $not$build/ls180/gateware/ls180.v:6084$1995 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface11_bank_bus_we + connect \Y $not$build/ls180/gateware/ls180.v:6084$1995_Y + end + attribute \src "build/ls180/gateware/ls180.v:6087.66-6087.98" + cell $not $not$build/ls180/gateware/ls180.v:6087$2002 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface11_bank_bus_we + connect \Y $not$build/ls180/gateware/ls180.v:6087$2002_Y + end + attribute \src "build/ls180/gateware/ls180.v:6090.65-6090.97" + cell $not $not$build/ls180/gateware/ls180.v:6090$2009 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface11_bank_bus_we + connect \Y $not$build/ls180/gateware/ls180.v:6090$2009_Y + end + attribute \src "build/ls180/gateware/ls180.v:6103.71-6103.103" + cell $not $not$build/ls180/gateware/ls180.v:6103$2017 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface12_bank_bus_we + connect \Y $not$build/ls180/gateware/ls180.v:6103$2017_Y + end + attribute \src "build/ls180/gateware/ls180.v:6106.71-6106.103" + cell $not $not$build/ls180/gateware/ls180.v:6106$2024 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface12_bank_bus_we + connect \Y $not$build/ls180/gateware/ls180.v:6106$2024_Y + end + attribute \src "build/ls180/gateware/ls180.v:6109.71-6109.103" + cell $not $not$build/ls180/gateware/ls180.v:6109$2031 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface12_bank_bus_we + connect \Y $not$build/ls180/gateware/ls180.v:6109$2031_Y + end + attribute \src "build/ls180/gateware/ls180.v:6112.71-6112.103" + cell $not $not$build/ls180/gateware/ls180.v:6112$2038 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_interface12_bank_bus_we + connect \Y $not$build/ls180/gateware/ls180.v:6112$2038_Y + end + attribute \src "build/ls180/gateware/ls180.v:6487.86-6487.330" + cell $not $not$build/ls180/gateware/ls180.v:6487$2085 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$build/ls180/gateware/ls180.v:6487$2084_Y + connect \Y $not$build/ls180/gateware/ls180.v:6487$2085_Y + end + attribute \src "build/ls180/gateware/ls180.v:6511.86-6511.330" + cell $not $not$build/ls180/gateware/ls180.v:6511$2101 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$build/ls180/gateware/ls180.v:6511$2100_Y + connect \Y $not$build/ls180/gateware/ls180.v:6511$2101_Y + end + attribute \src "build/ls180/gateware/ls180.v:6535.86-6535.330" + cell $not $not$build/ls180/gateware/ls180.v:6535$2117 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$build/ls180/gateware/ls180.v:6535$2116_Y + connect \Y $not$build/ls180/gateware/ls180.v:6535$2117_Y + end + attribute \src "build/ls180/gateware/ls180.v:6559.86-6559.330" + cell $not $not$build/ls180/gateware/ls180.v:6559$2133 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$build/ls180/gateware/ls180.v:6559$2132_Y + connect \Y $not$build/ls180/gateware/ls180.v:6559$2133_Y + end + attribute \src "build/ls180/gateware/ls180.v:7005.18-7005.43" + cell $not $not$build/ls180/gateware/ls180.v:7005$2185 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \libresocsim_clocker_clk0 + connect \Y $not$build/ls180/gateware/ls180.v:7005$2185_Y + end + attribute \src "build/ls180/gateware/ls180.v:7084.72-7084.101" + cell $not $not$build/ls180/gateware/ls180.v:7084$2193 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_libresocsim_ram_bus_ack + connect \Y $not$build/ls180/gateware/ls180.v:7084$2193_Y + end + attribute \src "build/ls180/gateware/ls180.v:7088.39-7088.64" + cell $not $not$build/ls180/gateware/ls180.v:7088$2195 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_libresocsim_tx_busy + connect \Y $not$build/ls180/gateware/ls180.v:7088$2195_Y + end + attribute \src "build/ls180/gateware/ls180.v:7088.70-7088.98" + cell $not $not$build/ls180/gateware/ls180.v:7088$2197 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_libresocsim_sink_ready + connect \Y $not$build/ls180/gateware/ls180.v:7088$2197_Y + end + attribute \src "build/ls180/gateware/ls180.v:7117.7-7117.32" + cell $not $not$build/ls180/gateware/ls180.v:7117$2204 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_libresocsim_rx_busy + connect \Y $not$build/ls180/gateware/ls180.v:7117$2204_Y + end + attribute \src "build/ls180/gateware/ls180.v:7118.9-7118.29" + cell $not $not$build/ls180/gateware/ls180.v:7118$2205 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_libresocsim_rx + connect \Y $not$build/ls180/gateware/ls180.v:7118$2205_Y + end + attribute \src "build/ls180/gateware/ls180.v:7151.8-7151.41" + cell $not $not$build/ls180/gateware/ls180.v:7151$2211 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_libresocsim_uart_tx_trigger + connect \Y $not$build/ls180/gateware/ls180.v:7151$2211_Y + end + attribute \src "build/ls180/gateware/ls180.v:7158.8-7158.41" + cell $not $not$build/ls180/gateware/ls180.v:7158$2213 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_libresocsim_uart_rx_trigger + connect \Y $not$build/ls180/gateware/ls180.v:7158$2213_Y + end + attribute \src "build/ls180/gateware/ls180.v:7168.104-7168.142" + cell $not $not$build/ls180/gateware/ls180.v:7168$2216 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_libresocsim_uart_tx_fifo_replace + connect \Y $not$build/ls180/gateware/ls180.v:7168$2216_Y + end + attribute \src "build/ls180/gateware/ls180.v:7174.104-7174.142" + cell $not $not$build/ls180/gateware/ls180.v:7174$2221 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_libresocsim_uart_tx_fifo_replace + connect \Y $not$build/ls180/gateware/ls180.v:7174$2221_Y + end + attribute \src "build/ls180/gateware/ls180.v:7175.8-7175.46" + cell $not $not$build/ls180/gateware/ls180.v:7175$2223 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_libresocsim_uart_tx_fifo_do_read + connect \Y $not$build/ls180/gateware/ls180.v:7175$2223_Y + end + attribute \src "build/ls180/gateware/ls180.v:7190.104-7190.142" + cell $not $not$build/ls180/gateware/ls180.v:7190$2227 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_libresocsim_uart_rx_fifo_replace + connect \Y $not$build/ls180/gateware/ls180.v:7190$2227_Y + end + attribute \src "build/ls180/gateware/ls180.v:7196.104-7196.142" + cell $not $not$build/ls180/gateware/ls180.v:7196$2232 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_libresocsim_uart_rx_fifo_replace + connect \Y $not$build/ls180/gateware/ls180.v:7196$2232_Y + end + attribute \src "build/ls180/gateware/ls180.v:7197.8-7197.46" + cell $not $not$build/ls180/gateware/ls180.v:7197$2234 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_libresocsim_uart_rx_fifo_do_read + connect \Y $not$build/ls180/gateware/ls180.v:7197$2234_Y + end + attribute \src "build/ls180/gateware/ls180.v:7235.8-7235.44" + cell $not $not$build/ls180/gateware/ls180.v:7235$2239 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_libresocsim_timer_zero_trigger + connect \Y $not$build/ls180/gateware/ls180.v:7235$2239_Y + end + attribute \src "build/ls180/gateware/ls180.v:7243.32-7243.55" + cell $not $not$build/ls180/gateware/ls180.v:7243$2241 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_timer_done0 + connect \Y $not$build/ls180/gateware/ls180.v:7243$2241_Y + end + attribute \src "build/ls180/gateware/ls180.v:7313.136-7313.189" + cell $not $not$build/ls180/gateware/ls180.v:7313$2256 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_replace + connect \Y $not$build/ls180/gateware/ls180.v:7313$2256_Y + end + attribute \src "build/ls180/gateware/ls180.v:7319.136-7319.189" + cell $not $not$build/ls180/gateware/ls180.v:7319$2261 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_replace + connect \Y $not$build/ls180/gateware/ls180.v:7319$2261_Y + end + attribute \src "build/ls180/gateware/ls180.v:7320.8-7320.61" + cell $not $not$build/ls180/gateware/ls180.v:7320$2263 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_do_read + connect \Y $not$build/ls180/gateware/ls180.v:7320$2263_Y + end + attribute \src "build/ls180/gateware/ls180.v:7328.8-7328.56" + cell $not $not$build/ls180/gateware/ls180.v:7328$2266 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine0_cmd_buffer_source_valid + connect \Y $not$build/ls180/gateware/ls180.v:7328$2266_Y + end + attribute \src "build/ls180/gateware/ls180.v:7343.8-7343.46" + cell $not $not$build/ls180/gateware/ls180.v:7343$2268 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine0_twtpcon_ready + connect \Y $not$build/ls180/gateware/ls180.v:7343$2268_Y + end + attribute \src "build/ls180/gateware/ls180.v:7359.136-7359.189" + cell $not $not$build/ls180/gateware/ls180.v:7359$2272 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_replace + connect \Y $not$build/ls180/gateware/ls180.v:7359$2272_Y + end + attribute \src "build/ls180/gateware/ls180.v:7365.136-7365.189" + cell $not $not$build/ls180/gateware/ls180.v:7365$2277 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_replace + connect \Y $not$build/ls180/gateware/ls180.v:7365$2277_Y + end + attribute \src "build/ls180/gateware/ls180.v:7366.8-7366.61" + cell $not $not$build/ls180/gateware/ls180.v:7366$2279 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_do_read + connect \Y $not$build/ls180/gateware/ls180.v:7366$2279_Y + end + attribute \src "build/ls180/gateware/ls180.v:7374.8-7374.56" + cell $not $not$build/ls180/gateware/ls180.v:7374$2282 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine1_cmd_buffer_source_valid + connect \Y $not$build/ls180/gateware/ls180.v:7374$2282_Y + end + attribute \src "build/ls180/gateware/ls180.v:7389.8-7389.46" + cell $not $not$build/ls180/gateware/ls180.v:7389$2284 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine1_twtpcon_ready + connect \Y $not$build/ls180/gateware/ls180.v:7389$2284_Y + end + attribute \src "build/ls180/gateware/ls180.v:7405.136-7405.189" + cell $not $not$build/ls180/gateware/ls180.v:7405$2288 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_replace + connect \Y $not$build/ls180/gateware/ls180.v:7405$2288_Y + end + attribute \src "build/ls180/gateware/ls180.v:7411.136-7411.189" + cell $not $not$build/ls180/gateware/ls180.v:7411$2293 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_replace + connect \Y $not$build/ls180/gateware/ls180.v:7411$2293_Y + end + attribute \src "build/ls180/gateware/ls180.v:7412.8-7412.61" + cell $not $not$build/ls180/gateware/ls180.v:7412$2295 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_do_read + connect \Y $not$build/ls180/gateware/ls180.v:7412$2295_Y + end + attribute \src "build/ls180/gateware/ls180.v:7420.8-7420.56" + cell $not $not$build/ls180/gateware/ls180.v:7420$2298 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine2_cmd_buffer_source_valid + connect \Y $not$build/ls180/gateware/ls180.v:7420$2298_Y + end + attribute \src "build/ls180/gateware/ls180.v:7435.8-7435.46" + cell $not $not$build/ls180/gateware/ls180.v:7435$2300 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine2_twtpcon_ready + connect \Y $not$build/ls180/gateware/ls180.v:7435$2300_Y + end + attribute \src "build/ls180/gateware/ls180.v:7451.136-7451.189" + cell $not $not$build/ls180/gateware/ls180.v:7451$2304 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_replace + connect \Y $not$build/ls180/gateware/ls180.v:7451$2304_Y + end + attribute \src "build/ls180/gateware/ls180.v:7457.136-7457.189" + cell $not $not$build/ls180/gateware/ls180.v:7457$2309 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_replace + connect \Y $not$build/ls180/gateware/ls180.v:7457$2309_Y + end + attribute \src "build/ls180/gateware/ls180.v:7458.8-7458.61" + cell $not $not$build/ls180/gateware/ls180.v:7458$2311 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_do_read + connect \Y $not$build/ls180/gateware/ls180.v:7458$2311_Y + end + attribute \src "build/ls180/gateware/ls180.v:7466.8-7466.56" + cell $not $not$build/ls180/gateware/ls180.v:7466$2314 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine3_cmd_buffer_source_valid + connect \Y $not$build/ls180/gateware/ls180.v:7466$2314_Y + end + attribute \src "build/ls180/gateware/ls180.v:7481.8-7481.46" + cell $not $not$build/ls180/gateware/ls180.v:7481$2316 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine3_twtpcon_ready + connect \Y $not$build/ls180/gateware/ls180.v:7481$2316_Y + end + attribute \src "build/ls180/gateware/ls180.v:7489.7-7489.22" + cell $not $not$build/ls180/gateware/ls180.v:7489$2319 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_en0 + connect \Y $not$build/ls180/gateware/ls180.v:7489$2319_Y + end + attribute \src "build/ls180/gateware/ls180.v:7492.8-7492.29" + cell $not $not$build/ls180/gateware/ls180.v:7492$2320 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_max_time0 + connect \Y $not$build/ls180/gateware/ls180.v:7492$2320_Y + end + attribute \src "build/ls180/gateware/ls180.v:7496.7-7496.22" + cell $not $not$build/ls180/gateware/ls180.v:7496$2322 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_en1 + connect \Y $not$build/ls180/gateware/ls180.v:7496$2322_Y + end + attribute \src "build/ls180/gateware/ls180.v:7499.8-7499.29" + cell $not $not$build/ls180/gateware/ls180.v:7499$2323 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_max_time1 + connect \Y $not$build/ls180/gateware/ls180.v:7499$2323_Y + end + attribute \src "build/ls180/gateware/ls180.v:7618.30-7618.60" + cell $not $not$build/ls180/gateware/ls180.v:7618$2325 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_sync_rhs_array_muxed2 + connect \Y $not$build/ls180/gateware/ls180.v:7618$2325_Y + end + attribute \src "build/ls180/gateware/ls180.v:7619.30-7619.60" + cell $not $not$build/ls180/gateware/ls180.v:7619$2326 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_sync_rhs_array_muxed3 + connect \Y $not$build/ls180/gateware/ls180.v:7619$2326_Y + end + attribute \src "build/ls180/gateware/ls180.v:7620.29-7620.59" + cell $not $not$build/ls180/gateware/ls180.v:7620$2327 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_sync_rhs_array_muxed4 + connect \Y $not$build/ls180/gateware/ls180.v:7620$2327_Y + end + attribute \src "build/ls180/gateware/ls180.v:7631.8-7631.33" + cell $not $not$build/ls180/gateware/ls180.v:7631$2328 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_tccdcon_ready + connect \Y $not$build/ls180/gateware/ls180.v:7631$2328_Y + end + attribute \src "build/ls180/gateware/ls180.v:7646.8-7646.33" + cell $not $not$build/ls180/gateware/ls180.v:7646$2331 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_twtrcon_ready + connect \Y $not$build/ls180/gateware/ls180.v:7646$2331_Y + end + attribute \src "build/ls180/gateware/ls180.v:7690.23-7690.31" + cell $not $not$build/ls180/gateware/ls180.v:7690$2362 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_cs + connect \Y $not$build/ls180/gateware/ls180.v:7690$2362_Y + end + attribute \src "build/ls180/gateware/ls180.v:7690.36-7690.51" + cell $not $not$build/ls180/gateware/ls180.v:7690$2363 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_cs_enable + connect \Y $not$build/ls180/gateware/ls180.v:7690$2363_Y + end + attribute \src "build/ls180/gateware/ls180.v:7716.7-7716.32" + cell $not $not$build/ls180/gateware/ls180.v:7716$2366 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \libresocsim_clocker_stop + connect \Y $not$build/ls180/gateware/ls180.v:7716$2366_Y + end + attribute \src "build/ls180/gateware/ls180.v:7788.8-7788.47" + cell $not $not$build/ls180/gateware/ls180.v:7788$2378 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \libresocsim_cmdr_cmdr_buf_source_valid + connect \Y $not$build/ls180/gateware/ls180.v:7788$2378_Y + end + attribute \src "build/ls180/gateware/ls180.v:7869.8-7869.48" + cell $not $not$build/ls180/gateware/ls180.v:7869$2390 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \libresocsim_dataw_crcr_buf_source_valid + connect \Y $not$build/ls180/gateware/ls180.v:7869$2390_Y + end + attribute \src "build/ls180/gateware/ls180.v:7930.8-7930.49" + cell $not $not$build/ls180/gateware/ls180.v:7930$2402 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \libresocsim_datar_datar_buf_source_valid + connect \Y $not$build/ls180/gateware/ls180.v:7930$2402_Y + end + attribute \src "build/ls180/gateware/ls180.v:8100.102-8100.139" + cell $not $not$build/ls180/gateware/ls180.v:8100$2416 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \libresocsim_sdblock2mem_fifo_replace + connect \Y $not$build/ls180/gateware/ls180.v:8100$2416_Y + end + attribute \src "build/ls180/gateware/ls180.v:8106.102-8106.139" + cell $not $not$build/ls180/gateware/ls180.v:8106$2421 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \libresocsim_sdblock2mem_fifo_replace + connect \Y $not$build/ls180/gateware/ls180.v:8106$2421_Y + end + attribute \src "build/ls180/gateware/ls180.v:8107.8-8107.45" + cell $not $not$build/ls180/gateware/ls180.v:8107$2423 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \libresocsim_sdblock2mem_fifo_do_read + connect \Y $not$build/ls180/gateware/ls180.v:8107$2423_Y + end + attribute \src "build/ls180/gateware/ls180.v:8186.102-8186.139" + cell $not $not$build/ls180/gateware/ls180.v:8186$2438 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \libresocsim_sdmem2block_fifo_replace + connect \Y $not$build/ls180/gateware/ls180.v:8186$2438_Y + end + attribute \src "build/ls180/gateware/ls180.v:8192.102-8192.139" + cell $not $not$build/ls180/gateware/ls180.v:8192$2443 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \libresocsim_sdmem2block_fifo_replace + connect \Y $not$build/ls180/gateware/ls180.v:8192$2443_Y + end + attribute \src "build/ls180/gateware/ls180.v:8193.8-8193.45" + cell $not $not$build/ls180/gateware/ls180.v:8193$2445 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \libresocsim_sdmem2block_fifo_do_read + connect \Y $not$build/ls180/gateware/ls180.v:8193$2445_Y + end + attribute \src "build/ls180/gateware/ls180.v:8210.22-8210.37" + cell $not $not$build/ls180/gateware/ls180.v:8210$2449 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \libresocsim_cs + connect \Y $not$build/ls180/gateware/ls180.v:8210$2449_Y + end + attribute \src "build/ls180/gateware/ls180.v:8210.42-8210.64" + cell $not $not$build/ls180/gateware/ls180.v:8210$2450 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \libresocsim_cs_enable + connect \Y $not$build/ls180/gateware/ls180.v:8210$2450_Y + end + attribute \src "build/ls180/gateware/ls180.v:8248.9-8248.28" + cell $not $not$build/ls180/gateware/ls180.v:8248$2453 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_request [0] + connect \Y $not$build/ls180/gateware/ls180.v:8248$2453_Y + end + attribute \src "build/ls180/gateware/ls180.v:8263.9-8263.28" + cell $not $not$build/ls180/gateware/ls180.v:8263$2454 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_request [1] + connect \Y $not$build/ls180/gateware/ls180.v:8263$2454_Y + end + attribute \src "build/ls180/gateware/ls180.v:8278.9-8278.28" + cell $not $not$build/ls180/gateware/ls180.v:8278$2455 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_request [2] + connect \Y $not$build/ls180/gateware/ls180.v:8278$2455_Y + end + attribute \src "build/ls180/gateware/ls180.v:8293.9-8293.28" + cell $not $not$build/ls180/gateware/ls180.v:8293$2456 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_request [3] + connect \Y $not$build/ls180/gateware/ls180.v:8293$2456_Y + end + attribute \src "build/ls180/gateware/ls180.v:8310.8-8310.21" + cell $not $not$build/ls180/gateware/ls180.v:8310$2457 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_done + connect \Y $not$build/ls180/gateware/ls180.v:8310$2457_Y + end + attribute \src "build/ls180/gateware/ls180.v:2634.10-2634.96" + cell $or $or$build/ls180/gateware/ls180.v:2634$21 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_libresocsim_interface0_converted_interface_ack + connect \B \main_libresocsim_converter0_skip + connect \Y $or$build/ls180/gateware/ls180.v:2634$21_Y + end + attribute \src "build/ls180/gateware/ls180.v:2694.10-2694.96" + cell $or $or$build/ls180/gateware/ls180.v:2694$32 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_libresocsim_interface1_converted_interface_ack + connect \B \main_libresocsim_converter1_skip + connect \Y $or$build/ls180/gateware/ls180.v:2694$32_Y + end + attribute \src "build/ls180/gateware/ls180.v:2753.54-2753.125" + cell $or $or$build/ls180/gateware/ls180.v:2753$55 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_libresocsim_uart_rx_clear + connect \B $and$build/ls180/gateware/ls180.v:2753$54_Y + connect \Y $or$build/ls180/gateware/ls180.v:2753$55_Y + end + attribute \src "build/ls180/gateware/ls180.v:2777.37-2777.234" + cell $or $or$build/ls180/gateware/ls180.v:2777$65 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$build/ls180/gateware/ls180.v:2777$63_Y + connect \B $and$build/ls180/gateware/ls180.v:2777$64_Y + connect \Y $or$build/ls180/gateware/ls180.v:2777$65_Y + end + attribute \src "build/ls180/gateware/ls180.v:2792.104-2792.180" + cell $or $or$build/ls180/gateware/ls180.v:2792$67 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $not$build/ls180/gateware/ls180.v:2792$66_Y + connect \B \main_libresocsim_uart_tx_fifo_re + connect \Y $or$build/ls180/gateware/ls180.v:2792$67_Y + end + attribute \src "build/ls180/gateware/ls180.v:2803.96-2803.183" + cell $or $or$build/ls180/gateware/ls180.v:2803$72 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_libresocsim_uart_tx_fifo_syncfifo_writable + connect \B \main_libresocsim_uart_tx_fifo_replace + connect \Y $or$build/ls180/gateware/ls180.v:2803$72_Y + end + attribute \src "build/ls180/gateware/ls180.v:2822.104-2822.180" + cell $or $or$build/ls180/gateware/ls180.v:2822$78 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $not$build/ls180/gateware/ls180.v:2822$77_Y + connect \B \main_libresocsim_uart_rx_fifo_re + connect \Y $or$build/ls180/gateware/ls180.v:2822$78_Y + end + attribute \src "build/ls180/gateware/ls180.v:2833.96-2833.183" + cell $or $or$build/ls180/gateware/ls180.v:2833$83 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_libresocsim_uart_rx_fifo_syncfifo_writable + connect \B \main_libresocsim_uart_rx_fifo_replace + connect \Y $or$build/ls180/gateware/ls180.v:2833$83_Y + end + attribute \src "build/ls180/gateware/ls180.v:3006.39-3006.105" + cell $or $or$build/ls180/gateware/ls180.v:3006$104 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_sequencer_start0 + connect \B $ne$build/ls180/gateware/ls180.v:3006$103_Y + connect \Y $or$build/ls180/gateware/ls180.v:3006$104_Y + end + attribute \src "build/ls180/gateware/ls180.v:3049.59-3049.140" + cell $or $or$build/ls180/gateware/ls180.v:3049$108 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine0_req_wdata_ready + connect \B \main_sdram_bankmachine0_req_rdata_valid + connect \Y $or$build/ls180/gateware/ls180.v:3049$108_Y + end + attribute \src "build/ls180/gateware/ls180.v:3050.44-3050.151" + cell $or $or$build/ls180/gateware/ls180.v:3050$109 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_source_valid + connect \B \main_sdram_bankmachine0_cmd_buffer_source_valid + connect \Y $or$build/ls180/gateware/ls180.v:3050$109_Y + end + attribute \src "build/ls180/gateware/ls180.v:3058.45-3058.170" + cell $or $or$build/ls180/gateware/ls180.v:3058$113 + parameter \A_SIGNED 0 + parameter \A_WIDTH 13 + parameter \B_SIGNED 0 + parameter \B_WIDTH 13 + parameter \Y_WIDTH 13 + connect \A $sshl$build/ls180/gateware/ls180.v:3058$112_Y + connect \B { 4'0000 \main_sdram_bankmachine0_cmd_buffer_source_payload_addr [8:0] } + connect \Y $or$build/ls180/gateware/ls180.v:3058$113_Y + end + attribute \src "build/ls180/gateware/ls180.v:3095.127-3095.245" + cell $or $or$build/ls180/gateware/ls180.v:3095$126 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable + connect \B \main_sdram_bankmachine0_cmd_buffer_lookahead_replace + connect \Y $or$build/ls180/gateware/ls180.v:3095$126_Y + end + attribute \src "build/ls180/gateware/ls180.v:3101.57-3101.157" + cell $or $or$build/ls180/gateware/ls180.v:3101$132 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $not$build/ls180/gateware/ls180.v:3101$131_Y + connect \B \main_sdram_bankmachine0_cmd_buffer_source_ready + connect \Y $or$build/ls180/gateware/ls180.v:3101$132_Y + end + attribute \src "build/ls180/gateware/ls180.v:3206.59-3206.140" + cell $or $or$build/ls180/gateware/ls180.v:3206$138 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine1_req_wdata_ready + connect \B \main_sdram_bankmachine1_req_rdata_valid + connect \Y $or$build/ls180/gateware/ls180.v:3206$138_Y + end + attribute \src "build/ls180/gateware/ls180.v:3207.44-3207.151" + cell $or $or$build/ls180/gateware/ls180.v:3207$139 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_source_valid + connect \B \main_sdram_bankmachine1_cmd_buffer_source_valid + connect \Y $or$build/ls180/gateware/ls180.v:3207$139_Y + end + attribute \src "build/ls180/gateware/ls180.v:3215.45-3215.170" + cell $or $or$build/ls180/gateware/ls180.v:3215$143 + parameter \A_SIGNED 0 + parameter \A_WIDTH 13 + parameter \B_SIGNED 0 + parameter \B_WIDTH 13 + parameter \Y_WIDTH 13 + connect \A $sshl$build/ls180/gateware/ls180.v:3215$142_Y + connect \B { 4'0000 \main_sdram_bankmachine1_cmd_buffer_source_payload_addr [8:0] } + connect \Y $or$build/ls180/gateware/ls180.v:3215$143_Y + end + attribute \src "build/ls180/gateware/ls180.v:3252.127-3252.245" + cell $or $or$build/ls180/gateware/ls180.v:3252$156 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable + connect \B \main_sdram_bankmachine1_cmd_buffer_lookahead_replace + connect \Y $or$build/ls180/gateware/ls180.v:3252$156_Y + end + attribute \src "build/ls180/gateware/ls180.v:3258.57-3258.157" + cell $or $or$build/ls180/gateware/ls180.v:3258$162 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $not$build/ls180/gateware/ls180.v:3258$161_Y + connect \B \main_sdram_bankmachine1_cmd_buffer_source_ready + connect \Y $or$build/ls180/gateware/ls180.v:3258$162_Y + end + attribute \src "build/ls180/gateware/ls180.v:3363.59-3363.140" + cell $or $or$build/ls180/gateware/ls180.v:3363$168 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine2_req_wdata_ready + connect \B \main_sdram_bankmachine2_req_rdata_valid + connect \Y $or$build/ls180/gateware/ls180.v:3363$168_Y + end + attribute \src "build/ls180/gateware/ls180.v:3364.44-3364.151" + cell $or $or$build/ls180/gateware/ls180.v:3364$169 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_source_valid + connect \B \main_sdram_bankmachine2_cmd_buffer_source_valid + connect \Y $or$build/ls180/gateware/ls180.v:3364$169_Y + end + attribute \src "build/ls180/gateware/ls180.v:3372.45-3372.170" + cell $or $or$build/ls180/gateware/ls180.v:3372$173 + parameter \A_SIGNED 0 + parameter \A_WIDTH 13 + parameter \B_SIGNED 0 + parameter \B_WIDTH 13 + parameter \Y_WIDTH 13 + connect \A $sshl$build/ls180/gateware/ls180.v:3372$172_Y + connect \B { 4'0000 \main_sdram_bankmachine2_cmd_buffer_source_payload_addr [8:0] } + connect \Y $or$build/ls180/gateware/ls180.v:3372$173_Y + end + attribute \src "build/ls180/gateware/ls180.v:3409.127-3409.245" + cell $or $or$build/ls180/gateware/ls180.v:3409$186 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable + connect \B \main_sdram_bankmachine2_cmd_buffer_lookahead_replace + connect \Y $or$build/ls180/gateware/ls180.v:3409$186_Y + end + attribute \src "build/ls180/gateware/ls180.v:3415.57-3415.157" + cell $or $or$build/ls180/gateware/ls180.v:3415$192 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $not$build/ls180/gateware/ls180.v:3415$191_Y + connect \B \main_sdram_bankmachine2_cmd_buffer_source_ready + connect \Y $or$build/ls180/gateware/ls180.v:3415$192_Y + end + attribute \src "build/ls180/gateware/ls180.v:3520.59-3520.140" + cell $or $or$build/ls180/gateware/ls180.v:3520$198 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine3_req_wdata_ready + connect \B \main_sdram_bankmachine3_req_rdata_valid + connect \Y $or$build/ls180/gateware/ls180.v:3520$198_Y + end + attribute \src "build/ls180/gateware/ls180.v:3521.44-3521.151" + cell $or $or$build/ls180/gateware/ls180.v:3521$199 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_source_valid + connect \B \main_sdram_bankmachine3_cmd_buffer_source_valid + connect \Y $or$build/ls180/gateware/ls180.v:3521$199_Y + end + attribute \src "build/ls180/gateware/ls180.v:3529.45-3529.170" + cell $or $or$build/ls180/gateware/ls180.v:3529$203 + parameter \A_SIGNED 0 + parameter \A_WIDTH 13 + parameter \B_SIGNED 0 + parameter \B_WIDTH 13 + parameter \Y_WIDTH 13 + connect \A $sshl$build/ls180/gateware/ls180.v:3529$202_Y + connect \B { 4'0000 \main_sdram_bankmachine3_cmd_buffer_source_payload_addr [8:0] } + connect \Y $or$build/ls180/gateware/ls180.v:3529$203_Y + end + attribute \src "build/ls180/gateware/ls180.v:3566.127-3566.245" + cell $or $or$build/ls180/gateware/ls180.v:3566$216 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable + connect \B \main_sdram_bankmachine3_cmd_buffer_lookahead_replace + connect \Y $or$build/ls180/gateware/ls180.v:3566$216_Y + end + attribute \src "build/ls180/gateware/ls180.v:3572.57-3572.157" + cell $or $or$build/ls180/gateware/ls180.v:3572$222 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $not$build/ls180/gateware/ls180.v:3572$221_Y + connect \B \main_sdram_bankmachine3_cmd_buffer_source_ready + connect \Y $or$build/ls180/gateware/ls180.v:3572$222_Y + end + attribute \src "build/ls180/gateware/ls180.v:3671.107-3671.193" + cell $or $or$build/ls180/gateware/ls180.v:3671$242 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_req_cmd_payload_is_write + connect \B \main_sdram_choose_req_cmd_payload_is_read + connect \Y $or$build/ls180/gateware/ls180.v:3671$242_Y + end + attribute \src "build/ls180/gateware/ls180.v:3674.39-3674.204" + cell $or $or$build/ls180/gateware/ls180.v:3674$248 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$build/ls180/gateware/ls180.v:3674$246_Y + connect \B $and$build/ls180/gateware/ls180.v:3674$247_Y + connect \Y $or$build/ls180/gateware/ls180.v:3674$248_Y + end + attribute \src "build/ls180/gateware/ls180.v:3674.38-3674.289" + cell $or $or$build/ls180/gateware/ls180.v:3674$250 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$build/ls180/gateware/ls180.v:3674$248_Y + connect \B $and$build/ls180/gateware/ls180.v:3674$249_Y + connect \Y $or$build/ls180/gateware/ls180.v:3674$250_Y + end + attribute \src "build/ls180/gateware/ls180.v:3674.37-3674.374" + cell $or $or$build/ls180/gateware/ls180.v:3674$252 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$build/ls180/gateware/ls180.v:3674$250_Y + connect \B $and$build/ls180/gateware/ls180.v:3674$251_Y + connect \Y $or$build/ls180/gateware/ls180.v:3674$252_Y + end + attribute \src "build/ls180/gateware/ls180.v:3675.40-3675.207" + cell $or $or$build/ls180/gateware/ls180.v:3675$255 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$build/ls180/gateware/ls180.v:3675$253_Y + connect \B $and$build/ls180/gateware/ls180.v:3675$254_Y + connect \Y $or$build/ls180/gateware/ls180.v:3675$255_Y + end + attribute \src "build/ls180/gateware/ls180.v:3675.39-3675.293" + cell $or $or$build/ls180/gateware/ls180.v:3675$257 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$build/ls180/gateware/ls180.v:3675$255_Y + connect \B $and$build/ls180/gateware/ls180.v:3675$256_Y + connect \Y $or$build/ls180/gateware/ls180.v:3675$257_Y + end + attribute \src "build/ls180/gateware/ls180.v:3675.38-3675.379" + cell $or $or$build/ls180/gateware/ls180.v:3675$259 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$build/ls180/gateware/ls180.v:3675$257_Y + connect \B $and$build/ls180/gateware/ls180.v:3675$258_Y + connect \Y $or$build/ls180/gateware/ls180.v:3675$259_Y + end + attribute \src "build/ls180/gateware/ls180.v:3688.158-3688.332" + cell $or $or$build/ls180/gateware/ls180.v:3688$273 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $not$build/ls180/gateware/ls180.v:3688$272_Y + connect \B \main_sdram_choose_cmd_want_activates + connect \Y $or$build/ls180/gateware/ls180.v:3688$273_Y + end + attribute \src "build/ls180/gateware/ls180.v:3688.75-3688.506" + cell $or $or$build/ls180/gateware/ls180.v:3688$278 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$build/ls180/gateware/ls180.v:3688$274_Y + connect \B $and$build/ls180/gateware/ls180.v:3688$277_Y + connect \Y $or$build/ls180/gateware/ls180.v:3688$278_Y + end + attribute \src "build/ls180/gateware/ls180.v:3689.158-3689.332" + cell $or $or$build/ls180/gateware/ls180.v:3689$286 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $not$build/ls180/gateware/ls180.v:3689$285_Y + connect \B \main_sdram_choose_cmd_want_activates + connect \Y $or$build/ls180/gateware/ls180.v:3689$286_Y + end + attribute \src "build/ls180/gateware/ls180.v:3689.75-3689.506" + cell $or $or$build/ls180/gateware/ls180.v:3689$291 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$build/ls180/gateware/ls180.v:3689$287_Y + connect \B $and$build/ls180/gateware/ls180.v:3689$290_Y + connect \Y $or$build/ls180/gateware/ls180.v:3689$291_Y + end + attribute \src "build/ls180/gateware/ls180.v:3690.158-3690.332" + cell $or $or$build/ls180/gateware/ls180.v:3690$299 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $not$build/ls180/gateware/ls180.v:3690$298_Y + connect \B \main_sdram_choose_cmd_want_activates + connect \Y $or$build/ls180/gateware/ls180.v:3690$299_Y + end + attribute \src "build/ls180/gateware/ls180.v:3690.75-3690.506" + cell $or $or$build/ls180/gateware/ls180.v:3690$304 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$build/ls180/gateware/ls180.v:3690$300_Y + connect \B $and$build/ls180/gateware/ls180.v:3690$303_Y + connect \Y $or$build/ls180/gateware/ls180.v:3690$304_Y + end + attribute \src "build/ls180/gateware/ls180.v:3691.158-3691.332" + cell $or $or$build/ls180/gateware/ls180.v:3691$312 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $not$build/ls180/gateware/ls180.v:3691$311_Y + connect \B \main_sdram_choose_cmd_want_activates + connect \Y $or$build/ls180/gateware/ls180.v:3691$312_Y + end + attribute \src "build/ls180/gateware/ls180.v:3691.75-3691.506" + cell $or $or$build/ls180/gateware/ls180.v:3691$317 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$build/ls180/gateware/ls180.v:3691$313_Y + connect \B $and$build/ls180/gateware/ls180.v:3691$316_Y + connect \Y $or$build/ls180/gateware/ls180.v:3691$317_Y + end + attribute \src "build/ls180/gateware/ls180.v:3718.36-3718.104" + cell $or $or$build/ls180/gateware/ls180.v:3718$323 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_cmd_cmd_ready + connect \B $not$build/ls180/gateware/ls180.v:3718$322_Y + connect \Y $or$build/ls180/gateware/ls180.v:3718$323_Y + end + attribute \src "build/ls180/gateware/ls180.v:3721.158-3721.332" + cell $or $or$build/ls180/gateware/ls180.v:3721$331 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $not$build/ls180/gateware/ls180.v:3721$330_Y + connect \B \main_sdram_choose_req_want_activates + connect \Y $or$build/ls180/gateware/ls180.v:3721$331_Y + end + attribute \src "build/ls180/gateware/ls180.v:3721.75-3721.506" + cell $or $or$build/ls180/gateware/ls180.v:3721$336 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$build/ls180/gateware/ls180.v:3721$332_Y + connect \B $and$build/ls180/gateware/ls180.v:3721$335_Y + connect \Y $or$build/ls180/gateware/ls180.v:3721$336_Y + end + attribute \src "build/ls180/gateware/ls180.v:3722.158-3722.332" + cell $or $or$build/ls180/gateware/ls180.v:3722$344 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $not$build/ls180/gateware/ls180.v:3722$343_Y + connect \B \main_sdram_choose_req_want_activates + connect \Y $or$build/ls180/gateware/ls180.v:3722$344_Y + end + attribute \src "build/ls180/gateware/ls180.v:3722.75-3722.506" + cell $or $or$build/ls180/gateware/ls180.v:3722$349 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$build/ls180/gateware/ls180.v:3722$345_Y + connect \B $and$build/ls180/gateware/ls180.v:3722$348_Y + connect \Y $or$build/ls180/gateware/ls180.v:3722$349_Y + end + attribute \src "build/ls180/gateware/ls180.v:3723.158-3723.332" + cell $or $or$build/ls180/gateware/ls180.v:3723$357 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $not$build/ls180/gateware/ls180.v:3723$356_Y + connect \B \main_sdram_choose_req_want_activates + connect \Y $or$build/ls180/gateware/ls180.v:3723$357_Y + end + attribute \src "build/ls180/gateware/ls180.v:3723.75-3723.506" + cell $or $or$build/ls180/gateware/ls180.v:3723$362 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$build/ls180/gateware/ls180.v:3723$358_Y + connect \B $and$build/ls180/gateware/ls180.v:3723$361_Y + connect \Y $or$build/ls180/gateware/ls180.v:3723$362_Y + end + attribute \src "build/ls180/gateware/ls180.v:3724.158-3724.332" + cell $or $or$build/ls180/gateware/ls180.v:3724$370 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $not$build/ls180/gateware/ls180.v:3724$369_Y + connect \B \main_sdram_choose_req_want_activates + connect \Y $or$build/ls180/gateware/ls180.v:3724$370_Y + end + attribute \src "build/ls180/gateware/ls180.v:3724.75-3724.506" + cell $or $or$build/ls180/gateware/ls180.v:3724$375 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$build/ls180/gateware/ls180.v:3724$371_Y + connect \B $and$build/ls180/gateware/ls180.v:3724$374_Y + connect \Y $or$build/ls180/gateware/ls180.v:3724$375_Y + end + attribute \src "build/ls180/gateware/ls180.v:3787.36-3787.104" + cell $or $or$build/ls180/gateware/ls180.v:3787$409 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_choose_req_cmd_ready + connect \B $not$build/ls180/gateware/ls180.v:3787$408_Y + connect \Y $or$build/ls180/gateware/ls180.v:3787$409_Y + end + attribute \src "build/ls180/gateware/ls180.v:3808.67-3808.221" + cell $or $or$build/ls180/gateware/ls180.v:3808$416 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $not$build/ls180/gateware/ls180.v:3808$415_Y + connect \B \main_sdram_ras_allowed + connect \Y $or$build/ls180/gateware/ls180.v:3808$416_Y + end + attribute \src "build/ls180/gateware/ls180.v:3816.10-3816.62" + cell $or $or$build/ls180/gateware/ls180.v:3816$419 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $not$build/ls180/gateware/ls180.v:3816$418_Y + connect \B \main_sdram_max_time1 + connect \Y $or$build/ls180/gateware/ls180.v:3816$419_Y + end + attribute \src "build/ls180/gateware/ls180.v:3846.67-3846.221" + cell $or $or$build/ls180/gateware/ls180.v:3846$425 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $not$build/ls180/gateware/ls180.v:3846$424_Y + connect \B \main_sdram_ras_allowed + connect \Y $or$build/ls180/gateware/ls180.v:3846$425_Y + end + attribute \src "build/ls180/gateware/ls180.v:3854.10-3854.61" + cell $or $or$build/ls180/gateware/ls180.v:3854$428 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $not$build/ls180/gateware/ls180.v:3854$427_Y + connect \B \main_sdram_max_time0 + connect \Y $or$build/ls180/gateware/ls180.v:3854$428_Y + end + attribute \src "build/ls180/gateware/ls180.v:3864.91-3864.180" + cell $or $or$build/ls180/gateware/ls180.v:3864$432 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_locked0 + connect \B $and$build/ls180/gateware/ls180.v:3864$431_Y + connect \Y $or$build/ls180/gateware/ls180.v:3864$432_Y + end + attribute \src "build/ls180/gateware/ls180.v:3864.90-3864.255" + cell $or $or$build/ls180/gateware/ls180.v:3864$435 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$build/ls180/gateware/ls180.v:3864$432_Y + connect \B $and$build/ls180/gateware/ls180.v:3864$434_Y + connect \Y $or$build/ls180/gateware/ls180.v:3864$435_Y + end + attribute \src "build/ls180/gateware/ls180.v:3864.89-3864.330" + cell $or $or$build/ls180/gateware/ls180.v:3864$438 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$build/ls180/gateware/ls180.v:3864$435_Y + connect \B $and$build/ls180/gateware/ls180.v:3864$437_Y + connect \Y $or$build/ls180/gateware/ls180.v:3864$438_Y + end + attribute \src "build/ls180/gateware/ls180.v:3869.91-3869.180" + cell $or $or$build/ls180/gateware/ls180.v:3869$448 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_locked1 + connect \B $and$build/ls180/gateware/ls180.v:3869$447_Y + connect \Y $or$build/ls180/gateware/ls180.v:3869$448_Y + end + attribute \src "build/ls180/gateware/ls180.v:3869.90-3869.255" + cell $or $or$build/ls180/gateware/ls180.v:3869$451 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$build/ls180/gateware/ls180.v:3869$448_Y + connect \B $and$build/ls180/gateware/ls180.v:3869$450_Y + connect \Y $or$build/ls180/gateware/ls180.v:3869$451_Y + end + attribute \src "build/ls180/gateware/ls180.v:3869.89-3869.330" + cell $or $or$build/ls180/gateware/ls180.v:3869$454 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$build/ls180/gateware/ls180.v:3869$451_Y + connect \B $and$build/ls180/gateware/ls180.v:3869$453_Y + connect \Y $or$build/ls180/gateware/ls180.v:3869$454_Y + end + attribute \src "build/ls180/gateware/ls180.v:3874.91-3874.180" + cell $or $or$build/ls180/gateware/ls180.v:3874$464 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_locked2 + connect \B $and$build/ls180/gateware/ls180.v:3874$463_Y + connect \Y $or$build/ls180/gateware/ls180.v:3874$464_Y + end + attribute \src "build/ls180/gateware/ls180.v:3874.90-3874.255" + cell $or $or$build/ls180/gateware/ls180.v:3874$467 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$build/ls180/gateware/ls180.v:3874$464_Y + connect \B $and$build/ls180/gateware/ls180.v:3874$466_Y + connect \Y $or$build/ls180/gateware/ls180.v:3874$467_Y + end + attribute \src "build/ls180/gateware/ls180.v:3874.89-3874.330" + cell $or $or$build/ls180/gateware/ls180.v:3874$470 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$build/ls180/gateware/ls180.v:3874$467_Y + connect \B $and$build/ls180/gateware/ls180.v:3874$469_Y + connect \Y $or$build/ls180/gateware/ls180.v:3874$470_Y + end + attribute \src "build/ls180/gateware/ls180.v:3879.91-3879.180" + cell $or $or$build/ls180/gateware/ls180.v:3879$480 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_locked3 + connect \B $and$build/ls180/gateware/ls180.v:3879$479_Y + connect \Y $or$build/ls180/gateware/ls180.v:3879$480_Y + end + attribute \src "build/ls180/gateware/ls180.v:3879.90-3879.255" + cell $or $or$build/ls180/gateware/ls180.v:3879$483 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$build/ls180/gateware/ls180.v:3879$480_Y + connect \B $and$build/ls180/gateware/ls180.v:3879$482_Y + connect \Y $or$build/ls180/gateware/ls180.v:3879$483_Y + end + attribute \src "build/ls180/gateware/ls180.v:3879.89-3879.330" + cell $or $or$build/ls180/gateware/ls180.v:3879$486 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$build/ls180/gateware/ls180.v:3879$483_Y + connect \B $and$build/ls180/gateware/ls180.v:3879$485_Y + connect \Y $or$build/ls180/gateware/ls180.v:3879$486_Y + end + attribute \src "build/ls180/gateware/ls180.v:3884.132-3884.221" + cell $or $or$build/ls180/gateware/ls180.v:3884$497 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_locked0 + connect \B $and$build/ls180/gateware/ls180.v:3884$496_Y + connect \Y $or$build/ls180/gateware/ls180.v:3884$497_Y + end + attribute \src "build/ls180/gateware/ls180.v:3884.131-3884.296" + cell $or $or$build/ls180/gateware/ls180.v:3884$500 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$build/ls180/gateware/ls180.v:3884$497_Y + connect \B $and$build/ls180/gateware/ls180.v:3884$499_Y + connect \Y $or$build/ls180/gateware/ls180.v:3884$500_Y + end + attribute \src "build/ls180/gateware/ls180.v:3884.130-3884.371" + cell $or $or$build/ls180/gateware/ls180.v:3884$503 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$build/ls180/gateware/ls180.v:3884$500_Y + connect \B $and$build/ls180/gateware/ls180.v:3884$502_Y + connect \Y $or$build/ls180/gateware/ls180.v:3884$503_Y + end + attribute \src "build/ls180/gateware/ls180.v:3884.34-3884.411" + cell $or $or$build/ls180/gateware/ls180.v:3884$508 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A 1'0 + connect \B $and$build/ls180/gateware/ls180.v:3884$507_Y + connect \Y $or$build/ls180/gateware/ls180.v:3884$508_Y + end + attribute \src "build/ls180/gateware/ls180.v:3884.506-3884.595" + cell $or $or$build/ls180/gateware/ls180.v:3884$513 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_locked1 + connect \B $and$build/ls180/gateware/ls180.v:3884$512_Y + connect \Y $or$build/ls180/gateware/ls180.v:3884$513_Y + end + attribute \src "build/ls180/gateware/ls180.v:3884.505-3884.670" + cell $or $or$build/ls180/gateware/ls180.v:3884$516 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$build/ls180/gateware/ls180.v:3884$513_Y + connect \B $and$build/ls180/gateware/ls180.v:3884$515_Y + connect \Y $or$build/ls180/gateware/ls180.v:3884$516_Y + end + attribute \src "build/ls180/gateware/ls180.v:3884.504-3884.745" + cell $or $or$build/ls180/gateware/ls180.v:3884$519 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$build/ls180/gateware/ls180.v:3884$516_Y + connect \B $and$build/ls180/gateware/ls180.v:3884$518_Y + connect \Y $or$build/ls180/gateware/ls180.v:3884$519_Y + end + attribute \src "build/ls180/gateware/ls180.v:3884.33-3884.785" + cell $or $or$build/ls180/gateware/ls180.v:3884$524 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$build/ls180/gateware/ls180.v:3884$508_Y + connect \B $and$build/ls180/gateware/ls180.v:3884$523_Y + connect \Y $or$build/ls180/gateware/ls180.v:3884$524_Y + end + attribute \src "build/ls180/gateware/ls180.v:3884.880-3884.969" + cell $or $or$build/ls180/gateware/ls180.v:3884$529 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_locked2 + connect \B $and$build/ls180/gateware/ls180.v:3884$528_Y + connect \Y $or$build/ls180/gateware/ls180.v:3884$529_Y + end + attribute \src "build/ls180/gateware/ls180.v:3884.879-3884.1044" + cell $or $or$build/ls180/gateware/ls180.v:3884$532 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$build/ls180/gateware/ls180.v:3884$529_Y + connect \B $and$build/ls180/gateware/ls180.v:3884$531_Y + connect \Y $or$build/ls180/gateware/ls180.v:3884$532_Y + end + attribute \src "build/ls180/gateware/ls180.v:3884.878-3884.1119" + cell $or $or$build/ls180/gateware/ls180.v:3884$535 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$build/ls180/gateware/ls180.v:3884$532_Y + connect \B $and$build/ls180/gateware/ls180.v:3884$534_Y + connect \Y $or$build/ls180/gateware/ls180.v:3884$535_Y + end + attribute \src "build/ls180/gateware/ls180.v:3884.32-3884.1159" + cell $or $or$build/ls180/gateware/ls180.v:3884$540 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$build/ls180/gateware/ls180.v:3884$524_Y + connect \B $and$build/ls180/gateware/ls180.v:3884$539_Y + connect \Y $or$build/ls180/gateware/ls180.v:3884$540_Y + end + attribute \src "build/ls180/gateware/ls180.v:3884.1254-3884.1343" + cell $or $or$build/ls180/gateware/ls180.v:3884$545 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_locked3 + connect \B $and$build/ls180/gateware/ls180.v:3884$544_Y + connect \Y $or$build/ls180/gateware/ls180.v:3884$545_Y + end + attribute \src "build/ls180/gateware/ls180.v:3884.1253-3884.1418" + cell $or $or$build/ls180/gateware/ls180.v:3884$548 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$build/ls180/gateware/ls180.v:3884$545_Y + connect \B $and$build/ls180/gateware/ls180.v:3884$547_Y + connect \Y $or$build/ls180/gateware/ls180.v:3884$548_Y + end + attribute \src "build/ls180/gateware/ls180.v:3884.1252-3884.1493" + cell $or $or$build/ls180/gateware/ls180.v:3884$551 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$build/ls180/gateware/ls180.v:3884$548_Y + connect \B $and$build/ls180/gateware/ls180.v:3884$550_Y + connect \Y $or$build/ls180/gateware/ls180.v:3884$551_Y + end + attribute \src "build/ls180/gateware/ls180.v:3884.31-3884.1533" + cell $or $or$build/ls180/gateware/ls180.v:3884$556 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$build/ls180/gateware/ls180.v:3884$540_Y + connect \B $and$build/ls180/gateware/ls180.v:3884$555_Y + connect \Y $or$build/ls180/gateware/ls180.v:3884$556_Y + end + attribute \src "build/ls180/gateware/ls180.v:3947.10-3947.52" + cell $or $or$build/ls180/gateware/ls180.v:3947$565 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_litedram_wb_ack + connect \B \main_converter_skip + connect \Y $or$build/ls180/gateware/ls180.v:3947$565_Y + end + attribute \src "build/ls180/gateware/ls180.v:3974.35-3974.74" + cell $or $or$build/ls180/gateware/ls180.v:3974$575 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_port_cmd_valid + connect \B \main_cmd_consumed + connect \Y $or$build/ls180/gateware/ls180.v:3974$575_Y + end + attribute \src "build/ls180/gateware/ls180.v:3975.34-3975.73" + cell $or $or$build/ls180/gateware/ls180.v:3975$579 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_port_cmd_valid + connect \B \main_cmd_consumed + connect \Y $or$build/ls180/gateware/ls180.v:3975$579_Y + end + attribute \src "build/ls180/gateware/ls180.v:3976.48-3976.130" + cell $or $or$build/ls180/gateware/ls180.v:3976$585 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$build/ls180/gateware/ls180.v:3976$582_Y + connect \B $and$build/ls180/gateware/ls180.v:3976$584_Y + connect \Y $or$build/ls180/gateware/ls180.v:3976$585_Y + end + attribute \src "build/ls180/gateware/ls180.v:3977.24-3977.87" + cell $or $or$build/ls180/gateware/ls180.v:3977$588 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$build/ls180/gateware/ls180.v:3977$587_Y + connect \B \main_cmd_consumed + connect \Y $or$build/ls180/gateware/ls180.v:3977$588_Y + end + attribute \src "build/ls180/gateware/ls180.v:3978.26-3978.95" + cell $or $or$build/ls180/gateware/ls180.v:3978$590 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $and$build/ls180/gateware/ls180.v:3978$589_Y + connect \B \main_wdata_consumed + connect \Y $or$build/ls180/gateware/ls180.v:3978$590_Y + end + attribute \src "build/ls180/gateware/ls180.v:4039.37-4039.114" + cell $or $or$build/ls180/gateware/ls180.v:4039$600 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \libresocsim_init_pads_out_payload_clk + connect \B \libresocsim_cmdw_pads_out_payload_clk + connect \Y $or$build/ls180/gateware/ls180.v:4039$600_Y + end + attribute \src "build/ls180/gateware/ls180.v:4039.36-4039.155" + cell $or $or$build/ls180/gateware/ls180.v:4039$601 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$build/ls180/gateware/ls180.v:4039$600_Y + connect \B \libresocsim_cmdr_pads_out_payload_clk + connect \Y $or$build/ls180/gateware/ls180.v:4039$601_Y + end + attribute \src "build/ls180/gateware/ls180.v:4039.35-4039.197" + cell $or $or$build/ls180/gateware/ls180.v:4039$602 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$build/ls180/gateware/ls180.v:4039$601_Y + connect \B \libresocsim_dataw_pads_out_payload_clk + connect \Y $or$build/ls180/gateware/ls180.v:4039$602_Y + end + attribute \src "build/ls180/gateware/ls180.v:4039.34-4039.239" + cell $or $or$build/ls180/gateware/ls180.v:4039$603 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$build/ls180/gateware/ls180.v:4039$602_Y + connect \B \libresocsim_datar_pads_out_payload_clk + connect \Y $or$build/ls180/gateware/ls180.v:4039$603_Y + end + attribute \src "build/ls180/gateware/ls180.v:4040.40-4040.123" + cell $or $or$build/ls180/gateware/ls180.v:4040$604 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \libresocsim_init_pads_out_payload_cmd_oe + connect \B \libresocsim_cmdw_pads_out_payload_cmd_oe + connect \Y $or$build/ls180/gateware/ls180.v:4040$604_Y + end + attribute \src "build/ls180/gateware/ls180.v:4040.39-4040.167" + cell $or $or$build/ls180/gateware/ls180.v:4040$605 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$build/ls180/gateware/ls180.v:4040$604_Y + connect \B \libresocsim_cmdr_pads_out_payload_cmd_oe + connect \Y $or$build/ls180/gateware/ls180.v:4040$605_Y + end + attribute \src "build/ls180/gateware/ls180.v:4040.38-4040.212" + cell $or $or$build/ls180/gateware/ls180.v:4040$606 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$build/ls180/gateware/ls180.v:4040$605_Y + connect \B \libresocsim_dataw_pads_out_payload_cmd_oe + connect \Y $or$build/ls180/gateware/ls180.v:4040$606_Y + end + attribute \src "build/ls180/gateware/ls180.v:4040.37-4040.257" + cell $or $or$build/ls180/gateware/ls180.v:4040$607 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$build/ls180/gateware/ls180.v:4040$606_Y + connect \B \libresocsim_datar_pads_out_payload_cmd_oe + connect \Y $or$build/ls180/gateware/ls180.v:4040$607_Y + end + attribute \src "build/ls180/gateware/ls180.v:4041.39-4041.120" + cell $or $or$build/ls180/gateware/ls180.v:4041$608 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \libresocsim_init_pads_out_payload_cmd_o + connect \B \libresocsim_cmdw_pads_out_payload_cmd_o + connect \Y $or$build/ls180/gateware/ls180.v:4041$608_Y + end + attribute \src "build/ls180/gateware/ls180.v:4041.38-4041.163" + cell $or $or$build/ls180/gateware/ls180.v:4041$609 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$build/ls180/gateware/ls180.v:4041$608_Y + connect \B \libresocsim_cmdr_pads_out_payload_cmd_o + connect \Y $or$build/ls180/gateware/ls180.v:4041$609_Y + end + attribute \src "build/ls180/gateware/ls180.v:4041.37-4041.207" + cell $or $or$build/ls180/gateware/ls180.v:4041$610 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$build/ls180/gateware/ls180.v:4041$609_Y + connect \B \libresocsim_dataw_pads_out_payload_cmd_o + connect \Y $or$build/ls180/gateware/ls180.v:4041$610_Y + end + attribute \src "build/ls180/gateware/ls180.v:4041.36-4041.251" + cell $or $or$build/ls180/gateware/ls180.v:4041$611 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$build/ls180/gateware/ls180.v:4041$610_Y + connect \B \libresocsim_datar_pads_out_payload_cmd_o + connect \Y $or$build/ls180/gateware/ls180.v:4041$611_Y + end + attribute \src "build/ls180/gateware/ls180.v:4042.41-4042.126" + cell $or $or$build/ls180/gateware/ls180.v:4042$612 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \libresocsim_init_pads_out_payload_data_oe + connect \B \libresocsim_cmdw_pads_out_payload_data_oe + connect \Y $or$build/ls180/gateware/ls180.v:4042$612_Y + end + attribute \src "build/ls180/gateware/ls180.v:4042.40-4042.171" + cell $or $or$build/ls180/gateware/ls180.v:4042$613 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$build/ls180/gateware/ls180.v:4042$612_Y + connect \B \libresocsim_cmdr_pads_out_payload_data_oe + connect \Y $or$build/ls180/gateware/ls180.v:4042$613_Y + end + attribute \src "build/ls180/gateware/ls180.v:4042.39-4042.217" + cell $or $or$build/ls180/gateware/ls180.v:4042$614 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$build/ls180/gateware/ls180.v:4042$613_Y + connect \B \libresocsim_dataw_pads_out_payload_data_oe + connect \Y $or$build/ls180/gateware/ls180.v:4042$614_Y + end + attribute \src "build/ls180/gateware/ls180.v:4042.38-4042.263" + cell $or $or$build/ls180/gateware/ls180.v:4042$615 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$build/ls180/gateware/ls180.v:4042$614_Y + connect \B \libresocsim_datar_pads_out_payload_data_oe + connect \Y $or$build/ls180/gateware/ls180.v:4042$615_Y + end + attribute \src "build/ls180/gateware/ls180.v:4043.40-4043.123" + cell $or $or$build/ls180/gateware/ls180.v:4043$616 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \libresocsim_init_pads_out_payload_data_o + connect \B \libresocsim_cmdw_pads_out_payload_data_o + connect \Y $or$build/ls180/gateware/ls180.v:4043$616_Y + end + attribute \src "build/ls180/gateware/ls180.v:4043.39-4043.167" + cell $or $or$build/ls180/gateware/ls180.v:4043$617 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A $or$build/ls180/gateware/ls180.v:4043$616_Y + connect \B \libresocsim_cmdr_pads_out_payload_data_o + connect \Y $or$build/ls180/gateware/ls180.v:4043$617_Y + end + attribute \src "build/ls180/gateware/ls180.v:4043.38-4043.212" + cell $or $or$build/ls180/gateware/ls180.v:4043$618 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A $or$build/ls180/gateware/ls180.v:4043$617_Y + connect \B \libresocsim_dataw_pads_out_payload_data_o + connect \Y $or$build/ls180/gateware/ls180.v:4043$618_Y + end + attribute \src "build/ls180/gateware/ls180.v:4043.37-4043.257" + cell $or $or$build/ls180/gateware/ls180.v:4043$619 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A $or$build/ls180/gateware/ls180.v:4043$618_Y + connect \B \libresocsim_datar_pads_out_payload_data_o + connect \Y $or$build/ls180/gateware/ls180.v:4043$619_Y + end + attribute \src "build/ls180/gateware/ls180.v:4064.36-4064.83" + cell $or $or$build/ls180/gateware/ls180.v:4064$620 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \libresocsim_dataw_stop + connect \B \libresocsim_datar_stop + connect \Y $or$build/ls180/gateware/ls180.v:4064$620_Y + end + attribute \src "build/ls180/gateware/ls180.v:4218.93-4218.148" + cell $or $or$build/ls180/gateware/ls180.v:4218$634 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \libresocsim_cmdr_cmdr_start + connect \B \libresocsim_cmdr_cmdr_run + connect \Y $or$build/ls180/gateware/ls180.v:4218$634_Y + end + attribute \src "build/ls180/gateware/ls180.v:4235.54-4235.146" + cell $or $or$build/ls180/gateware/ls180.v:4235$637 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $not$build/ls180/gateware/ls180.v:4235$636_Y + connect \B \libresocsim_cmdr_cmdr_converter_source_ready + connect \Y $or$build/ls180/gateware/ls180.v:4235$637_Y + end + attribute \src "build/ls180/gateware/ls180.v:4238.48-4238.130" + cell $or $or$build/ls180/gateware/ls180.v:4238$640 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $not$build/ls180/gateware/ls180.v:4238$639_Y + connect \B \libresocsim_cmdr_cmdr_buf_source_ready + connect \Y $or$build/ls180/gateware/ls180.v:4238$640_Y + end + attribute \src "build/ls180/gateware/ls180.v:4362.55-4362.149" + cell $or $or$build/ls180/gateware/ls180.v:4362$658 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $not$build/ls180/gateware/ls180.v:4362$657_Y + connect \B \libresocsim_dataw_crcr_converter_source_ready + connect \Y $or$build/ls180/gateware/ls180.v:4362$658_Y + end + attribute \src "build/ls180/gateware/ls180.v:4365.49-4365.133" + cell $or $or$build/ls180/gateware/ls180.v:4365$661 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $not$build/ls180/gateware/ls180.v:4365$660_Y + connect \B \libresocsim_dataw_crcr_buf_source_ready + connect \Y $or$build/ls180/gateware/ls180.v:4365$661_Y + end + attribute \src "build/ls180/gateware/ls180.v:4496.56-4496.152" + cell $or $or$build/ls180/gateware/ls180.v:4496$673 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $not$build/ls180/gateware/ls180.v:4496$672_Y + connect \B \libresocsim_datar_datar_converter_source_ready + connect \Y $or$build/ls180/gateware/ls180.v:4496$673_Y + end + attribute \src "build/ls180/gateware/ls180.v:4499.50-4499.136" + cell $or $or$build/ls180/gateware/ls180.v:4499$676 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $not$build/ls180/gateware/ls180.v:4499$675_Y + connect \B \libresocsim_datar_datar_buf_source_ready + connect \Y $or$build/ls180/gateware/ls180.v:4499$676_Y + end + attribute \src "build/ls180/gateware/ls180.v:5128.94-5128.179" + cell $or $or$build/ls180/gateware/ls180.v:5128$971 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \libresocsim_sdblock2mem_fifo_syncfifo_writable + connect \B \libresocsim_sdblock2mem_fifo_replace + connect \Y $or$build/ls180/gateware/ls180.v:5128$971_Y + end + attribute \src "build/ls180/gateware/ls180.v:5139.56-5139.152" + cell $or $or$build/ls180/gateware/ls180.v:5139$977 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $not$build/ls180/gateware/ls180.v:5139$976_Y + connect \B \libresocsim_sdblock2mem_converter_source_ready + connect \Y $or$build/ls180/gateware/ls180.v:5139$977_Y + end + attribute \src "build/ls180/gateware/ls180.v:5336.94-5336.179" + cell $or $or$build/ls180/gateware/ls180.v:5336$1002 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \libresocsim_sdmem2block_fifo_syncfifo_writable + connect \B \libresocsim_sdmem2block_fifo_replace + connect \Y $or$build/ls180/gateware/ls180.v:5336$1002_Y + end + attribute \src "build/ls180/gateware/ls180.v:5507.33-5507.102" + cell $or $or$build/ls180/gateware/ls180.v:5507$1046 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_libresocsim_ram_bus_err + connect \B \main_libresocsim_libresoc_xics_icp_err + connect \Y $or$build/ls180/gateware/ls180.v:5507$1046_Y + end + attribute \src "build/ls180/gateware/ls180.v:5507.32-5507.144" + cell $or $or$build/ls180/gateware/ls180.v:5507$1047 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$build/ls180/gateware/ls180.v:5507$1046_Y + connect \B \main_libresocsim_libresoc_xics_ics_err + connect \Y $or$build/ls180/gateware/ls180.v:5507$1047_Y + end + attribute \src "build/ls180/gateware/ls180.v:5507.31-5507.165" + cell $or $or$build/ls180/gateware/ls180.v:5507$1048 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$build/ls180/gateware/ls180.v:5507$1047_Y + connect \B \main_wb_sdram_err + connect \Y $or$build/ls180/gateware/ls180.v:5507$1048_Y + end + attribute \src "build/ls180/gateware/ls180.v:5507.30-5507.201" + cell $or $or$build/ls180/gateware/ls180.v:5507$1049 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$build/ls180/gateware/ls180.v:5507$1048_Y + connect \B \builder_libresocsim_wishbone_err + connect \Y $or$build/ls180/gateware/ls180.v:5507$1049_Y + end + attribute \src "build/ls180/gateware/ls180.v:5513.28-5513.97" + cell $or $or$build/ls180/gateware/ls180.v:5513$1054 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_libresocsim_ram_bus_ack + connect \B \main_libresocsim_libresoc_xics_icp_ack + connect \Y $or$build/ls180/gateware/ls180.v:5513$1054_Y + end + attribute \src "build/ls180/gateware/ls180.v:5513.27-5513.139" + cell $or $or$build/ls180/gateware/ls180.v:5513$1055 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$build/ls180/gateware/ls180.v:5513$1054_Y + connect \B \main_libresocsim_libresoc_xics_ics_ack + connect \Y $or$build/ls180/gateware/ls180.v:5513$1055_Y + end + attribute \src "build/ls180/gateware/ls180.v:5513.26-5513.160" + cell $or $or$build/ls180/gateware/ls180.v:5513$1056 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$build/ls180/gateware/ls180.v:5513$1055_Y + connect \B \main_wb_sdram_ack + connect \Y $or$build/ls180/gateware/ls180.v:5513$1056_Y + end + attribute \src "build/ls180/gateware/ls180.v:5513.25-5513.196" + cell $or $or$build/ls180/gateware/ls180.v:5513$1057 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$build/ls180/gateware/ls180.v:5513$1056_Y + connect \B \builder_libresocsim_wishbone_ack + connect \Y $or$build/ls180/gateware/ls180.v:5513$1057_Y + end + attribute \src "build/ls180/gateware/ls180.v:5514.30-5514.169" + cell $or $or$build/ls180/gateware/ls180.v:5514$1060 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 32 + parameter \Y_WIDTH 32 + connect \A $and$build/ls180/gateware/ls180.v:5514$1058_Y + connect \B $and$build/ls180/gateware/ls180.v:5514$1059_Y + connect \Y $or$build/ls180/gateware/ls180.v:5514$1060_Y + end + attribute \src "build/ls180/gateware/ls180.v:5514.29-5514.246" + cell $or $or$build/ls180/gateware/ls180.v:5514$1062 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 32 + parameter \Y_WIDTH 32 + connect \A $or$build/ls180/gateware/ls180.v:5514$1060_Y + connect \B $and$build/ls180/gateware/ls180.v:5514$1061_Y + connect \Y $or$build/ls180/gateware/ls180.v:5514$1062_Y + end + attribute \src "build/ls180/gateware/ls180.v:5514.28-5514.302" + cell $or $or$build/ls180/gateware/ls180.v:5514$1064 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 32 + parameter \Y_WIDTH 32 + connect \A $or$build/ls180/gateware/ls180.v:5514$1062_Y + connect \B $and$build/ls180/gateware/ls180.v:5514$1063_Y + connect \Y $or$build/ls180/gateware/ls180.v:5514$1064_Y + end + attribute \src "build/ls180/gateware/ls180.v:5514.27-5514.373" + cell $or $or$build/ls180/gateware/ls180.v:5514$1066 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 32 + parameter \Y_WIDTH 32 + connect \A $or$build/ls180/gateware/ls180.v:5514$1064_Y + connect \B $and$build/ls180/gateware/ls180.v:5514$1065_Y + connect \Y $or$build/ls180/gateware/ls180.v:5514$1066_Y + end + attribute \src "build/ls180/gateware/ls180.v:6160.53-6160.122" + cell $or $or$build/ls180/gateware/ls180.v:6160$2042 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 8 + connect \A \builder_interface0_bank_bus_dat_r + connect \B \builder_interface1_bank_bus_dat_r + connect \Y $or$build/ls180/gateware/ls180.v:6160$2042_Y + end + attribute \src "build/ls180/gateware/ls180.v:6160.52-6160.159" + cell $or $or$build/ls180/gateware/ls180.v:6160$2043 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 8 + connect \A $or$build/ls180/gateware/ls180.v:6160$2042_Y + connect \B \builder_interface2_bank_bus_dat_r + connect \Y $or$build/ls180/gateware/ls180.v:6160$2043_Y + end + attribute \src "build/ls180/gateware/ls180.v:6160.51-6160.196" + cell $or $or$build/ls180/gateware/ls180.v:6160$2044 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 8 + connect \A $or$build/ls180/gateware/ls180.v:6160$2043_Y + connect \B \builder_interface3_bank_bus_dat_r + connect \Y $or$build/ls180/gateware/ls180.v:6160$2044_Y + end + attribute \src "build/ls180/gateware/ls180.v:6160.50-6160.233" + cell $or $or$build/ls180/gateware/ls180.v:6160$2045 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 8 + connect \A $or$build/ls180/gateware/ls180.v:6160$2044_Y + connect \B \builder_interface4_bank_bus_dat_r + connect \Y $or$build/ls180/gateware/ls180.v:6160$2045_Y + end + attribute \src "build/ls180/gateware/ls180.v:6160.49-6160.270" + cell $or $or$build/ls180/gateware/ls180.v:6160$2046 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 8 + connect \A $or$build/ls180/gateware/ls180.v:6160$2045_Y + connect \B \builder_interface5_bank_bus_dat_r + connect \Y $or$build/ls180/gateware/ls180.v:6160$2046_Y + end + attribute \src "build/ls180/gateware/ls180.v:6160.48-6160.307" + cell $or $or$build/ls180/gateware/ls180.v:6160$2047 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 8 + connect \A $or$build/ls180/gateware/ls180.v:6160$2046_Y + connect \B \builder_interface6_bank_bus_dat_r + connect \Y $or$build/ls180/gateware/ls180.v:6160$2047_Y + end + attribute \src "build/ls180/gateware/ls180.v:6160.47-6160.344" + cell $or $or$build/ls180/gateware/ls180.v:6160$2048 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 8 + connect \A $or$build/ls180/gateware/ls180.v:6160$2047_Y + connect \B \builder_interface7_bank_bus_dat_r + connect \Y $or$build/ls180/gateware/ls180.v:6160$2048_Y + end + attribute \src "build/ls180/gateware/ls180.v:6160.46-6160.381" + cell $or $or$build/ls180/gateware/ls180.v:6160$2049 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 8 + connect \A $or$build/ls180/gateware/ls180.v:6160$2048_Y + connect \B \builder_interface8_bank_bus_dat_r + connect \Y $or$build/ls180/gateware/ls180.v:6160$2049_Y + end + attribute \src "build/ls180/gateware/ls180.v:6160.45-6160.418" + cell $or $or$build/ls180/gateware/ls180.v:6160$2050 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 8 + connect \A $or$build/ls180/gateware/ls180.v:6160$2049_Y + connect \B \builder_interface9_bank_bus_dat_r + connect \Y $or$build/ls180/gateware/ls180.v:6160$2050_Y + end + attribute \src "build/ls180/gateware/ls180.v:6160.44-6160.456" + cell $or $or$build/ls180/gateware/ls180.v:6160$2051 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 8 + connect \A $or$build/ls180/gateware/ls180.v:6160$2050_Y + connect \B \builder_interface10_bank_bus_dat_r + connect \Y $or$build/ls180/gateware/ls180.v:6160$2051_Y + end + attribute \src "build/ls180/gateware/ls180.v:6160.43-6160.494" + cell $or $or$build/ls180/gateware/ls180.v:6160$2052 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 8 + connect \A $or$build/ls180/gateware/ls180.v:6160$2051_Y + connect \B \builder_interface11_bank_bus_dat_r + connect \Y $or$build/ls180/gateware/ls180.v:6160$2052_Y + end + attribute \src "build/ls180/gateware/ls180.v:6160.42-6160.532" + cell $or $or$build/ls180/gateware/ls180.v:6160$2053 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 8 + connect \A $or$build/ls180/gateware/ls180.v:6160$2052_Y + connect \B \builder_interface12_bank_bus_dat_r + connect \Y $or$build/ls180/gateware/ls180.v:6160$2053_Y + end + attribute \src "build/ls180/gateware/ls180.v:6487.90-6487.179" + cell $or $or$build/ls180/gateware/ls180.v:6487$2078 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_locked0 + connect \B $and$build/ls180/gateware/ls180.v:6487$2077_Y + connect \Y $or$build/ls180/gateware/ls180.v:6487$2078_Y + end + attribute \src "build/ls180/gateware/ls180.v:6487.89-6487.254" + cell $or $or$build/ls180/gateware/ls180.v:6487$2081 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$build/ls180/gateware/ls180.v:6487$2078_Y + connect \B $and$build/ls180/gateware/ls180.v:6487$2080_Y + connect \Y $or$build/ls180/gateware/ls180.v:6487$2081_Y + end + attribute \src "build/ls180/gateware/ls180.v:6487.88-6487.329" + cell $or $or$build/ls180/gateware/ls180.v:6487$2084 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$build/ls180/gateware/ls180.v:6487$2081_Y + connect \B $and$build/ls180/gateware/ls180.v:6487$2083_Y + connect \Y $or$build/ls180/gateware/ls180.v:6487$2084_Y + end + attribute \src "build/ls180/gateware/ls180.v:6511.90-6511.179" + cell $or $or$build/ls180/gateware/ls180.v:6511$2094 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_locked1 + connect \B $and$build/ls180/gateware/ls180.v:6511$2093_Y + connect \Y $or$build/ls180/gateware/ls180.v:6511$2094_Y + end + attribute \src "build/ls180/gateware/ls180.v:6511.89-6511.254" + cell $or $or$build/ls180/gateware/ls180.v:6511$2097 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$build/ls180/gateware/ls180.v:6511$2094_Y + connect \B $and$build/ls180/gateware/ls180.v:6511$2096_Y + connect \Y $or$build/ls180/gateware/ls180.v:6511$2097_Y + end + attribute \src "build/ls180/gateware/ls180.v:6511.88-6511.329" + cell $or $or$build/ls180/gateware/ls180.v:6511$2100 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$build/ls180/gateware/ls180.v:6511$2097_Y + connect \B $and$build/ls180/gateware/ls180.v:6511$2099_Y + connect \Y $or$build/ls180/gateware/ls180.v:6511$2100_Y + end + attribute \src "build/ls180/gateware/ls180.v:6535.90-6535.179" + cell $or $or$build/ls180/gateware/ls180.v:6535$2110 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_locked2 + connect \B $and$build/ls180/gateware/ls180.v:6535$2109_Y + connect \Y $or$build/ls180/gateware/ls180.v:6535$2110_Y + end + attribute \src "build/ls180/gateware/ls180.v:6535.89-6535.254" + cell $or $or$build/ls180/gateware/ls180.v:6535$2113 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$build/ls180/gateware/ls180.v:6535$2110_Y + connect \B $and$build/ls180/gateware/ls180.v:6535$2112_Y + connect \Y $or$build/ls180/gateware/ls180.v:6535$2113_Y + end + attribute \src "build/ls180/gateware/ls180.v:6535.88-6535.329" + cell $or $or$build/ls180/gateware/ls180.v:6535$2116 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$build/ls180/gateware/ls180.v:6535$2113_Y + connect \B $and$build/ls180/gateware/ls180.v:6535$2115_Y + connect \Y $or$build/ls180/gateware/ls180.v:6535$2116_Y + end + attribute \src "build/ls180/gateware/ls180.v:6559.90-6559.179" + cell $or $or$build/ls180/gateware/ls180.v:6559$2126 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \builder_locked3 + connect \B $and$build/ls180/gateware/ls180.v:6559$2125_Y + connect \Y $or$build/ls180/gateware/ls180.v:6559$2126_Y + end + attribute \src "build/ls180/gateware/ls180.v:6559.89-6559.254" + cell $or $or$build/ls180/gateware/ls180.v:6559$2129 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$build/ls180/gateware/ls180.v:6559$2126_Y + connect \B $and$build/ls180/gateware/ls180.v:6559$2128_Y + connect \Y $or$build/ls180/gateware/ls180.v:6559$2129_Y + end + attribute \src "build/ls180/gateware/ls180.v:6559.88-6559.329" + cell $or $or$build/ls180/gateware/ls180.v:6559$2132 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$build/ls180/gateware/ls180.v:6559$2129_Y + connect \B $and$build/ls180/gateware/ls180.v:6559$2131_Y + connect \Y $or$build/ls180/gateware/ls180.v:6559$2132_Y + end + attribute \src "build/ls180/gateware/ls180.v:7056.7-7056.93" + cell $or $or$build/ls180/gateware/ls180.v:7056$2188 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_libresocsim_interface0_converted_interface_ack + connect \B \main_libresocsim_converter0_skip + connect \Y $or$build/ls180/gateware/ls180.v:7056$2188_Y + end + attribute \src "build/ls180/gateware/ls180.v:7067.7-7067.93" + cell $or $or$build/ls180/gateware/ls180.v:7067$2189 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_libresocsim_interface1_converted_interface_ack + connect \B \main_libresocsim_converter1_skip + connect \Y $or$build/ls180/gateware/ls180.v:7067$2189_Y + end + attribute \src "build/ls180/gateware/ls180.v:7328.7-7328.107" + cell $or $or$build/ls180/gateware/ls180.v:7328$2267 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $not$build/ls180/gateware/ls180.v:7328$2266_Y + connect \B \main_sdram_bankmachine0_cmd_buffer_source_ready + connect \Y $or$build/ls180/gateware/ls180.v:7328$2267_Y + end + attribute \src "build/ls180/gateware/ls180.v:7374.7-7374.107" + cell $or $or$build/ls180/gateware/ls180.v:7374$2283 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $not$build/ls180/gateware/ls180.v:7374$2282_Y + connect \B \main_sdram_bankmachine1_cmd_buffer_source_ready + connect \Y $or$build/ls180/gateware/ls180.v:7374$2283_Y + end + attribute \src "build/ls180/gateware/ls180.v:7420.7-7420.107" + cell $or $or$build/ls180/gateware/ls180.v:7420$2299 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $not$build/ls180/gateware/ls180.v:7420$2298_Y + connect \B \main_sdram_bankmachine2_cmd_buffer_source_ready + connect \Y $or$build/ls180/gateware/ls180.v:7420$2299_Y + end + attribute \src "build/ls180/gateware/ls180.v:7466.7-7466.107" + cell $or $or$build/ls180/gateware/ls180.v:7466$2315 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $not$build/ls180/gateware/ls180.v:7466$2314_Y + connect \B \main_sdram_bankmachine3_cmd_buffer_source_ready + connect \Y $or$build/ls180/gateware/ls180.v:7466$2315_Y + end + attribute \src "build/ls180/gateware/ls180.v:7654.40-7654.125" + cell $or $or$build/ls180/gateware/ls180.v:7654$2336 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A 1'0 + connect \B $and$build/ls180/gateware/ls180.v:7654$2335_Y + connect \Y $or$build/ls180/gateware/ls180.v:7654$2336_Y + end + attribute \src "build/ls180/gateware/ls180.v:7654.39-7654.207" + cell $or $or$build/ls180/gateware/ls180.v:7654$2339 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$build/ls180/gateware/ls180.v:7654$2336_Y + connect \B $and$build/ls180/gateware/ls180.v:7654$2338_Y + connect \Y $or$build/ls180/gateware/ls180.v:7654$2339_Y + end + attribute \src "build/ls180/gateware/ls180.v:7654.38-7654.289" + cell $or $or$build/ls180/gateware/ls180.v:7654$2342 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$build/ls180/gateware/ls180.v:7654$2339_Y + connect \B $and$build/ls180/gateware/ls180.v:7654$2341_Y + connect \Y $or$build/ls180/gateware/ls180.v:7654$2342_Y + end + attribute \src "build/ls180/gateware/ls180.v:7654.37-7654.371" + cell $or $or$build/ls180/gateware/ls180.v:7654$2345 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$build/ls180/gateware/ls180.v:7654$2342_Y + connect \B $and$build/ls180/gateware/ls180.v:7654$2344_Y + connect \Y $or$build/ls180/gateware/ls180.v:7654$2345_Y + end + attribute \src "build/ls180/gateware/ls180.v:7655.41-7655.126" + cell $or $or$build/ls180/gateware/ls180.v:7655$2348 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A 1'0 + connect \B $and$build/ls180/gateware/ls180.v:7655$2347_Y + connect \Y $or$build/ls180/gateware/ls180.v:7655$2348_Y + end + attribute \src "build/ls180/gateware/ls180.v:7655.40-7655.208" + cell $or $or$build/ls180/gateware/ls180.v:7655$2351 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$build/ls180/gateware/ls180.v:7655$2348_Y + connect \B $and$build/ls180/gateware/ls180.v:7655$2350_Y + connect \Y $or$build/ls180/gateware/ls180.v:7655$2351_Y + end + attribute \src "build/ls180/gateware/ls180.v:7655.39-7655.290" + cell $or $or$build/ls180/gateware/ls180.v:7655$2354 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$build/ls180/gateware/ls180.v:7655$2351_Y + connect \B $and$build/ls180/gateware/ls180.v:7655$2353_Y + connect \Y $or$build/ls180/gateware/ls180.v:7655$2354_Y + end + attribute \src "build/ls180/gateware/ls180.v:7655.38-7655.372" + cell $or $or$build/ls180/gateware/ls180.v:7655$2357 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $or$build/ls180/gateware/ls180.v:7655$2354_Y + connect \B $and$build/ls180/gateware/ls180.v:7655$2356_Y + connect \Y $or$build/ls180/gateware/ls180.v:7655$2357_Y + end + attribute \src "build/ls180/gateware/ls180.v:7659.7-7659.49" + cell $or $or$build/ls180/gateware/ls180.v:7659$2358 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_litedram_wb_ack + connect \B \main_converter_skip + connect \Y $or$build/ls180/gateware/ls180.v:7659$2358_Y + end + attribute \src "build/ls180/gateware/ls180.v:7690.22-7690.52" + cell $or $or$build/ls180/gateware/ls180.v:7690$2364 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $not$build/ls180/gateware/ls180.v:7690$2362_Y + connect \B $not$build/ls180/gateware/ls180.v:7690$2363_Y + connect \Y $or$build/ls180/gateware/ls180.v:7690$2364_Y + end + attribute \src "build/ls180/gateware/ls180.v:7730.33-7730.88" + cell $or $or$build/ls180/gateware/ls180.v:7730$2368 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \libresocsim_cmdr_cmdr_start + connect \B \libresocsim_cmdr_cmdr_run + connect \Y $or$build/ls180/gateware/ls180.v:7730$2368_Y + end + attribute \src "build/ls180/gateware/ls180.v:7736.8-7736.99" + cell $or $or$build/ls180/gateware/ls180.v:7736$2370 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $eq$build/ls180/gateware/ls180.v:7736$2369_Y + connect \B \libresocsim_cmdr_cmdr_converter_sink_last + connect \Y $or$build/ls180/gateware/ls180.v:7736$2370_Y + end + attribute \src "build/ls180/gateware/ls180.v:7753.53-7753.142" + cell $or $or$build/ls180/gateware/ls180.v:7753$2375 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \libresocsim_cmdr_cmdr_converter_sink_first + connect \B \libresocsim_cmdr_cmdr_converter_source_first + connect \Y $or$build/ls180/gateware/ls180.v:7753$2375_Y + end + attribute \src "build/ls180/gateware/ls180.v:7754.52-7754.139" + cell $or $or$build/ls180/gateware/ls180.v:7754$2376 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \libresocsim_cmdr_cmdr_converter_sink_last + connect \B \libresocsim_cmdr_cmdr_converter_source_last + connect \Y $or$build/ls180/gateware/ls180.v:7754$2376_Y + end + attribute \src "build/ls180/gateware/ls180.v:7788.7-7788.89" + cell $or $or$build/ls180/gateware/ls180.v:7788$2379 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $not$build/ls180/gateware/ls180.v:7788$2378_Y + connect \B \libresocsim_cmdr_cmdr_buf_source_ready + connect \Y $or$build/ls180/gateware/ls180.v:7788$2379_Y + end + attribute \src "build/ls180/gateware/ls180.v:7811.34-7811.91" + cell $or $or$build/ls180/gateware/ls180.v:7811$2380 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \libresocsim_dataw_crcr_start + connect \B \libresocsim_dataw_crcr_run + connect \Y $or$build/ls180/gateware/ls180.v:7811$2380_Y + end + attribute \src "build/ls180/gateware/ls180.v:7817.8-7817.101" + cell $or $or$build/ls180/gateware/ls180.v:7817$2382 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $eq$build/ls180/gateware/ls180.v:7817$2381_Y + connect \B \libresocsim_dataw_crcr_converter_sink_last + connect \Y $or$build/ls180/gateware/ls180.v:7817$2382_Y + end + attribute \src "build/ls180/gateware/ls180.v:7834.54-7834.145" + cell $or $or$build/ls180/gateware/ls180.v:7834$2387 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \libresocsim_dataw_crcr_converter_sink_first + connect \B \libresocsim_dataw_crcr_converter_source_first + connect \Y $or$build/ls180/gateware/ls180.v:7834$2387_Y + end + attribute \src "build/ls180/gateware/ls180.v:7835.53-7835.142" + cell $or $or$build/ls180/gateware/ls180.v:7835$2388 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \libresocsim_dataw_crcr_converter_sink_last + connect \B \libresocsim_dataw_crcr_converter_source_last + connect \Y $or$build/ls180/gateware/ls180.v:7835$2388_Y + end + attribute \src "build/ls180/gateware/ls180.v:7869.7-7869.91" + cell $or $or$build/ls180/gateware/ls180.v:7869$2391 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $not$build/ls180/gateware/ls180.v:7869$2390_Y + connect \B \libresocsim_dataw_crcr_buf_source_ready + connect \Y $or$build/ls180/gateware/ls180.v:7869$2391_Y + end + attribute \src "build/ls180/gateware/ls180.v:7890.35-7890.94" + cell $or $or$build/ls180/gateware/ls180.v:7890$2392 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \libresocsim_datar_datar_start + connect \B \libresocsim_datar_datar_run + connect \Y $or$build/ls180/gateware/ls180.v:7890$2392_Y + end + attribute \src "build/ls180/gateware/ls180.v:7896.8-7896.103" + cell $or $or$build/ls180/gateware/ls180.v:7896$2394 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $eq$build/ls180/gateware/ls180.v:7896$2393_Y + connect \B \libresocsim_datar_datar_converter_sink_last + connect \Y $or$build/ls180/gateware/ls180.v:7896$2394_Y + end + attribute \src "build/ls180/gateware/ls180.v:7913.55-7913.148" + cell $or $or$build/ls180/gateware/ls180.v:7913$2399 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \libresocsim_datar_datar_converter_sink_first + connect \B \libresocsim_datar_datar_converter_source_first + connect \Y $or$build/ls180/gateware/ls180.v:7913$2399_Y + end + attribute \src "build/ls180/gateware/ls180.v:7914.54-7914.145" + cell $or $or$build/ls180/gateware/ls180.v:7914$2400 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \libresocsim_datar_datar_converter_sink_last + connect \B \libresocsim_datar_datar_converter_source_last + connect \Y $or$build/ls180/gateware/ls180.v:7914$2400_Y + end + attribute \src "build/ls180/gateware/ls180.v:7930.7-7930.93" + cell $or $or$build/ls180/gateware/ls180.v:7930$2403 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $not$build/ls180/gateware/ls180.v:7930$2402_Y + connect \B \libresocsim_datar_datar_buf_source_ready + connect \Y $or$build/ls180/gateware/ls180.v:7930$2403_Y + end + attribute \src "build/ls180/gateware/ls180.v:8119.8-8119.103" + cell $or $or$build/ls180/gateware/ls180.v:8119$2427 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $eq$build/ls180/gateware/ls180.v:8119$2426_Y + connect \B \libresocsim_sdblock2mem_converter_sink_last + connect \Y $or$build/ls180/gateware/ls180.v:8119$2427_Y + end + attribute \src "build/ls180/gateware/ls180.v:8136.55-8136.148" + cell $or $or$build/ls180/gateware/ls180.v:8136$2432 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \libresocsim_sdblock2mem_converter_sink_first + connect \B \libresocsim_sdblock2mem_converter_source_first + connect \Y $or$build/ls180/gateware/ls180.v:8136$2432_Y + end + attribute \src "build/ls180/gateware/ls180.v:8137.54-8137.145" + cell $or $or$build/ls180/gateware/ls180.v:8137$2433 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \libresocsim_sdblock2mem_converter_sink_last + connect \B \libresocsim_sdblock2mem_converter_source_last + connect \Y $or$build/ls180/gateware/ls180.v:8137$2433_Y + end + attribute \src "build/ls180/gateware/ls180.v:8210.21-8210.65" + cell $or $or$build/ls180/gateware/ls180.v:8210$2451 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A $not$build/ls180/gateware/ls180.v:8210$2449_Y + connect \B $not$build/ls180/gateware/ls180.v:8210$2450_Y + connect \Y $or$build/ls180/gateware/ls180.v:8210$2451_Y + end + attribute \src "build/ls180/gateware/ls180.v:9525.8-9525.49" + cell $or $or$build/ls180/gateware/ls180.v:9525$2529 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \sys_rst + connect \B \main_libresocsim_libresoc_reset + connect \Y $or$build/ls180/gateware/ls180.v:9525$2529_Y + end + attribute \src "build/ls180/gateware/ls180.v:3058.46-3058.94" + cell $sshl $sshl$build/ls180/gateware/ls180.v:3058$112 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 13 + connect \A \main_sdram_bankmachine0_auto_precharge + connect \B 4'1010 + connect \Y $sshl$build/ls180/gateware/ls180.v:3058$112_Y + end + attribute \src "build/ls180/gateware/ls180.v:3215.46-3215.94" + cell $sshl $sshl$build/ls180/gateware/ls180.v:3215$142 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 13 + connect \A \main_sdram_bankmachine1_auto_precharge + connect \B 4'1010 + connect \Y $sshl$build/ls180/gateware/ls180.v:3215$142_Y + end + attribute \src "build/ls180/gateware/ls180.v:3372.46-3372.94" + cell $sshl $sshl$build/ls180/gateware/ls180.v:3372$172 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 13 + connect \A \main_sdram_bankmachine2_auto_precharge + connect \B 4'1010 + connect \Y $sshl$build/ls180/gateware/ls180.v:3372$172_Y + end + attribute \src "build/ls180/gateware/ls180.v:3529.46-3529.94" + cell $sshl $sshl$build/ls180/gateware/ls180.v:3529$202 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 13 + connect \A \main_sdram_bankmachine3_auto_precharge + connect \B 4'1010 + connect \Y $sshl$build/ls180/gateware/ls180.v:3529$202_Y + end + attribute \src "build/ls180/gateware/ls180.v:2797.48-2797.92" + cell $sub $sub$build/ls180/gateware/ls180.v:2797$71 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 4 + connect \A \main_libresocsim_uart_tx_fifo_produce + connect \B 1'1 + connect \Y $sub$build/ls180/gateware/ls180.v:2797$71_Y + end + attribute \src "build/ls180/gateware/ls180.v:2827.48-2827.92" + cell $sub $sub$build/ls180/gateware/ls180.v:2827$82 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 4 + connect \A \main_libresocsim_uart_rx_fifo_produce + connect \B 1'1 + connect \Y $sub$build/ls180/gateware/ls180.v:2827$82_Y + end + attribute \src "build/ls180/gateware/ls180.v:3089.63-3089.122" + cell $sub $sub$build/ls180/gateware/ls180.v:3089$125 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 3 + connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_produce + connect \B 1'1 + connect \Y $sub$build/ls180/gateware/ls180.v:3089$125_Y + end + attribute \src "build/ls180/gateware/ls180.v:3246.63-3246.122" + cell $sub $sub$build/ls180/gateware/ls180.v:3246$155 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 3 + connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_produce + connect \B 1'1 + connect \Y $sub$build/ls180/gateware/ls180.v:3246$155_Y + end + attribute \src "build/ls180/gateware/ls180.v:3403.63-3403.122" + cell $sub $sub$build/ls180/gateware/ls180.v:3403$185 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 3 + connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_produce + connect \B 1'1 + connect \Y $sub$build/ls180/gateware/ls180.v:3403$185_Y + end + attribute \src "build/ls180/gateware/ls180.v:3560.63-3560.122" + cell $sub $sub$build/ls180/gateware/ls180.v:3560$215 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 3 + connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_produce + connect \B 1'1 + connect \Y $sub$build/ls180/gateware/ls180.v:3560$215_Y + end + attribute \src "build/ls180/gateware/ls180.v:3966.38-3966.65" + cell $sub $sub$build/ls180/gateware/ls180.v:3966$569 + parameter \A_SIGNED 0 + parameter \A_WIDTH 30 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 30 + connect \A \main_litedram_wb_adr + connect \B 1'0 + connect \Y $sub$build/ls180/gateware/ls180.v:3966$569_Y + end + attribute \src "build/ls180/gateware/ls180.v:3987.47-3987.77" + cell $sub $sub$build/ls180/gateware/ls180.v:3987$592 + parameter \A_SIGNED 0 + parameter \A_WIDTH 15 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 16 + connect \A \main_clk_divider0 [15:1] + connect \B 1'1 + connect \Y $sub$build/ls180/gateware/ls180.v:3987$592_Y + end + attribute \src "build/ls180/gateware/ls180.v:3988.47-3988.71" + cell $sub $sub$build/ls180/gateware/ls180.v:3988$594 + parameter \A_SIGNED 0 + parameter \A_WIDTH 16 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 16 + connect \A \main_clk_divider0 + connect \B 1'1 + connect \Y $sub$build/ls180/gateware/ls180.v:3988$594_Y + end + attribute \src "build/ls180/gateware/ls180.v:4015.25-4015.44" + cell $sub $sub$build/ls180/gateware/ls180.v:4015$598 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 8 + connect \A \main_length0 + connect \B 1'1 + connect \Y $sub$build/ls180/gateware/ls180.v:4015$598_Y + end + attribute \src "build/ls180/gateware/ls180.v:4265.61-4265.92" + cell $sub $sub$build/ls180/gateware/ls180.v:4265$642 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 32 + connect \A \libresocsim_cmdr_timeout + connect \B 1'1 + connect \Y $sub$build/ls180/gateware/ls180.v:4265$642_Y + end + attribute \src "build/ls180/gateware/ls180.v:4276.64-4276.107" + cell $sub $sub$build/ls180/gateware/ls180.v:4276$644 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 8 + connect \A \libresocsim_cmdr_sink_payload_length + connect \B 1'1 + connect \Y $sub$build/ls180/gateware/ls180.v:4276$644_Y + end + attribute \src "build/ls180/gateware/ls180.v:4293.61-4293.92" + cell $sub $sub$build/ls180/gateware/ls180.v:4293$648 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 32 + connect \A \libresocsim_cmdr_timeout + connect \B 1'1 + connect \Y $sub$build/ls180/gateware/ls180.v:4293$648_Y + end + attribute \src "build/ls180/gateware/ls180.v:4522.63-4522.95" + cell $sub $sub$build/ls180/gateware/ls180.v:4522$678 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 32 + connect \A \libresocsim_datar_timeout + connect \B 1'1 + connect \Y $sub$build/ls180/gateware/ls180.v:4522$678_Y + end + attribute \src "build/ls180/gateware/ls180.v:4527.63-4527.95" + cell $sub $sub$build/ls180/gateware/ls180.v:4527$679 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 32 + connect \A \libresocsim_datar_timeout + connect \B 1'1 + connect \Y $sub$build/ls180/gateware/ls180.v:4527$679_Y + end + attribute \src "build/ls180/gateware/ls180.v:4538.66-4538.125" + cell $sub $sub$build/ls180/gateware/ls180.v:4538$682 + parameter \A_SIGNED 0 + parameter \A_WIDTH 10 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 10 + connect \A $add$build/ls180/gateware/ls180.v:4538$681_Y + connect \B 1'1 + connect \Y $sub$build/ls180/gateware/ls180.v:4538$682_Y + end + attribute \src "build/ls180/gateware/ls180.v:4559.63-4559.95" + cell $sub $sub$build/ls180/gateware/ls180.v:4559$685 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 32 + connect \A \libresocsim_datar_timeout + connect \B 1'1 + connect \Y $sub$build/ls180/gateware/ls180.v:4559$685_Y + end + attribute \src "build/ls180/gateware/ls180.v:5021.44-5021.89" + cell $sub $sub$build/ls180/gateware/ls180.v:5021$958 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 32 + connect \A \libresocsim_sdcore_block_count_storage + connect \B 1'1 + connect \Y $sub$build/ls180/gateware/ls180.v:5021$958_Y + end + attribute \src "build/ls180/gateware/ls180.v:5036.70-5036.115" + cell $sub $sub$build/ls180/gateware/ls180.v:5036$961 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 32 + connect \A \libresocsim_sdcore_block_count_storage + connect \B 1'1 + connect \Y $sub$build/ls180/gateware/ls180.v:5036$961_Y + end + attribute \src "build/ls180/gateware/ls180.v:5047.46-5047.91" + cell $sub $sub$build/ls180/gateware/ls180.v:5047$966 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 32 + connect \A \libresocsim_sdcore_block_count_storage + connect \B 1'1 + connect \Y $sub$build/ls180/gateware/ls180.v:5047$966_Y + end + attribute \src "build/ls180/gateware/ls180.v:5122.47-5122.90" + cell $sub $sub$build/ls180/gateware/ls180.v:5122$970 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 5 + connect \A \libresocsim_sdblock2mem_fifo_produce + connect \B 1'1 + connect \Y $sub$build/ls180/gateware/ls180.v:5122$970_Y + end + attribute \src "build/ls180/gateware/ls180.v:5171.63-5171.118" + cell $sub $sub$build/ls180/gateware/ls180.v:5171$984 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 32 + connect \A \libresocsim_sdblock2mem_wishbonedmawriter_length + connect \B 1'1 + connect \Y $sub$build/ls180/gateware/ls180.v:5171$984_Y + end + attribute \src "build/ls180/gateware/ls180.v:5261.85-5261.126" + cell $sub $sub$build/ls180/gateware/ls180.v:5261$990 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 32 + connect \A \libresocsim_sdmem2block_dma_length + connect \B 1'1 + connect \Y $sub$build/ls180/gateware/ls180.v:5261$990_Y + end + attribute \src "build/ls180/gateware/ls180.v:5330.47-5330.90" + cell $sub $sub$build/ls180/gateware/ls180.v:5330$1001 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 5 + connect \A \libresocsim_sdmem2block_fifo_produce + connect \B 1'1 + connect \Y $sub$build/ls180/gateware/ls180.v:5330$1001_Y + end + attribute \src "build/ls180/gateware/ls180.v:5349.61-5349.98" + cell $sub $sub$build/ls180/gateware/ls180.v:5349$1007 + parameter \A_SIGNED 0 + parameter \A_WIDTH 15 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 16 + connect \A \libresocsim_clk_divider0 [15:1] + connect \B 1'1 + connect \Y $sub$build/ls180/gateware/ls180.v:5349$1007_Y + end + attribute \src "build/ls180/gateware/ls180.v:5350.61-5350.92" + cell $sub $sub$build/ls180/gateware/ls180.v:5350$1009 + parameter \A_SIGNED 0 + parameter \A_WIDTH 16 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 16 + connect \A \libresocsim_clk_divider0 + connect \B 1'1 + connect \Y $sub$build/ls180/gateware/ls180.v:5350$1009_Y + end + attribute \src "build/ls180/gateware/ls180.v:5378.32-5378.58" + cell $sub $sub$build/ls180/gateware/ls180.v:5378$1013 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 8 + connect \A \libresocsim_length0 + connect \B 1'1 + connect \Y $sub$build/ls180/gateware/ls180.v:5378$1013_Y + end + attribute \src "build/ls180/gateware/ls180.v:7180.45-7180.88" + cell $sub $sub$build/ls180/gateware/ls180.v:7180$2225 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 5 + connect \A \main_libresocsim_uart_tx_fifo_level0 + connect \B 1'1 + connect \Y $sub$build/ls180/gateware/ls180.v:7180$2225_Y + end + attribute \src "build/ls180/gateware/ls180.v:7202.45-7202.88" + cell $sub $sub$build/ls180/gateware/ls180.v:7202$2236 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 5 + connect \A \main_libresocsim_uart_rx_fifo_level0 + connect \B 1'1 + connect \Y $sub$build/ls180/gateware/ls180.v:7202$2236_Y + end + attribute \src "build/ls180/gateware/ls180.v:7223.37-7223.72" + cell $sub $sub$build/ls180/gateware/ls180.v:7223$2238 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 32 + connect \A \main_libresocsim_timer_value + connect \B 1'1 + connect \Y $sub$build/ls180/gateware/ls180.v:7223$2238_Y + end + attribute \src "build/ls180/gateware/ls180.v:7244.31-7244.61" + cell $sub $sub$build/ls180/gateware/ls180.v:7244$2243 + parameter \A_SIGNED 0 + parameter \A_WIDTH 10 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 10 + connect \A \main_sdram_timer_count1 + connect \B 1'1 + connect \Y $sub$build/ls180/gateware/ls180.v:7244$2243_Y + end + attribute \src "build/ls180/gateware/ls180.v:7250.34-7250.67" + cell $sub $sub$build/ls180/gateware/ls180.v:7250$2244 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_postponer_count + connect \B 1'1 + connect \Y $sub$build/ls180/gateware/ls180.v:7250$2244_Y + end + attribute \src "build/ls180/gateware/ls180.v:7261.36-7261.69" + cell $sub $sub$build/ls180/gateware/ls180.v:7261$2247 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_sequencer_count + connect \B 1'1 + connect \Y $sub$build/ls180/gateware/ls180.v:7261$2247_Y + end + attribute \src "build/ls180/gateware/ls180.v:7325.59-7325.116" + cell $sub $sub$build/ls180/gateware/ls180.v:7325$2265 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 4 + connect \A \main_sdram_bankmachine0_cmd_buffer_lookahead_level + connect \B 1'1 + connect \Y $sub$build/ls180/gateware/ls180.v:7325$2265_Y + end + attribute \src "build/ls180/gateware/ls180.v:7344.46-7344.90" + cell $sub $sub$build/ls180/gateware/ls180.v:7344$2269 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 3 + connect \A \main_sdram_bankmachine0_twtpcon_count + connect \B 1'1 + connect \Y $sub$build/ls180/gateware/ls180.v:7344$2269_Y + end + attribute \src "build/ls180/gateware/ls180.v:7371.59-7371.116" + cell $sub $sub$build/ls180/gateware/ls180.v:7371$2281 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 4 + connect \A \main_sdram_bankmachine1_cmd_buffer_lookahead_level + connect \B 1'1 + connect \Y $sub$build/ls180/gateware/ls180.v:7371$2281_Y + end + attribute \src "build/ls180/gateware/ls180.v:7390.46-7390.90" + cell $sub $sub$build/ls180/gateware/ls180.v:7390$2285 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 3 + connect \A \main_sdram_bankmachine1_twtpcon_count + connect \B 1'1 + connect \Y $sub$build/ls180/gateware/ls180.v:7390$2285_Y + end + attribute \src "build/ls180/gateware/ls180.v:7417.59-7417.116" + cell $sub $sub$build/ls180/gateware/ls180.v:7417$2297 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 4 + connect \A \main_sdram_bankmachine2_cmd_buffer_lookahead_level + connect \B 1'1 + connect \Y $sub$build/ls180/gateware/ls180.v:7417$2297_Y + end + attribute \src "build/ls180/gateware/ls180.v:7436.46-7436.90" + cell $sub $sub$build/ls180/gateware/ls180.v:7436$2301 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 3 + connect \A \main_sdram_bankmachine2_twtpcon_count + connect \B 1'1 + connect \Y $sub$build/ls180/gateware/ls180.v:7436$2301_Y + end + attribute \src "build/ls180/gateware/ls180.v:7463.59-7463.116" + cell $sub $sub$build/ls180/gateware/ls180.v:7463$2313 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 4 + connect \A \main_sdram_bankmachine3_cmd_buffer_lookahead_level + connect \B 1'1 + connect \Y $sub$build/ls180/gateware/ls180.v:7463$2313_Y + end + attribute \src "build/ls180/gateware/ls180.v:7482.46-7482.90" + cell $sub $sub$build/ls180/gateware/ls180.v:7482$2317 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 3 + connect \A \main_sdram_bankmachine3_twtpcon_count + connect \B 1'1 + connect \Y $sub$build/ls180/gateware/ls180.v:7482$2317_Y + end + attribute \src "build/ls180/gateware/ls180.v:7493.25-7493.48" + cell $sub $sub$build/ls180/gateware/ls180.v:7493$2321 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 5 + connect \A \main_sdram_time0 + connect \B 1'1 + connect \Y $sub$build/ls180/gateware/ls180.v:7493$2321_Y + end + attribute \src "build/ls180/gateware/ls180.v:7500.25-7500.48" + cell $sub $sub$build/ls180/gateware/ls180.v:7500$2324 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 4 + connect \A \main_sdram_time1 + connect \B 1'1 + connect \Y $sub$build/ls180/gateware/ls180.v:7500$2324_Y + end + attribute \src "build/ls180/gateware/ls180.v:7632.33-7632.64" + cell $sub $sub$build/ls180/gateware/ls180.v:7632$2329 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \main_sdram_tccdcon_count + connect \B 1'1 + connect \Y $sub$build/ls180/gateware/ls180.v:7632$2329_Y + end + attribute \src "build/ls180/gateware/ls180.v:7647.33-7647.64" + cell $sub $sub$build/ls180/gateware/ls180.v:7647$2332 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 3 + connect \A \main_sdram_twtrcon_count + connect \B 1'1 + connect \Y $sub$build/ls180/gateware/ls180.v:7647$2332_Y + end + attribute \src "build/ls180/gateware/ls180.v:7699.22-7699.42" + cell $sub $sub$build/ls180/gateware/ls180.v:7699$2365 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 3 + connect \A \main_mosi_sel + connect \B 1'1 + connect \Y $sub$build/ls180/gateware/ls180.v:7699$2365_Y + end + attribute \src "build/ls180/gateware/ls180.v:8112.43-8112.84" + cell $sub $sub$build/ls180/gateware/ls180.v:8112$2425 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 6 + connect \A \libresocsim_sdblock2mem_fifo_level + connect \B 1'1 + connect \Y $sub$build/ls180/gateware/ls180.v:8112$2425_Y + end + attribute \src "build/ls180/gateware/ls180.v:8198.43-8198.84" + cell $sub $sub$build/ls180/gateware/ls180.v:8198$2447 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 6 + connect \A \libresocsim_sdmem2block_fifo_level + connect \B 1'1 + connect \Y $sub$build/ls180/gateware/ls180.v:8198$2447_Y + end + attribute \src "build/ls180/gateware/ls180.v:8219.29-8219.56" + cell $sub $sub$build/ls180/gateware/ls180.v:8219$2452 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 3 + connect \A \libresocsim_mosi_sel + connect \B 1'1 + connect \Y $sub$build/ls180/gateware/ls180.v:8219$2452_Y + end + attribute \src "build/ls180/gateware/ls180.v:8311.22-8311.42" + cell $sub $sub$build/ls180/gateware/ls180.v:8311$2458 + parameter \A_SIGNED 0 + parameter \A_WIDTH 20 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 20 + connect \A \builder_count + connect \B 1'1 + connect \Y $sub$build/ls180/gateware/ls180.v:8311$2458_Y + end + attribute \src "build/ls180/gateware/ls180.v:9564.22-9564.92" + cell $mux $ternary$build/ls180/gateware/ls180.v:9564$2530 + parameter \WIDTH 1 + connect \A 1'z + connect \B \builder_inferedsdrtristate0__o + connect \S \builder_inferedsdrtristate0_oe + connect \Y $ternary$build/ls180/gateware/ls180.v:9564$2530_Y + end + attribute \src "build/ls180/gateware/ls180.v:9567.22-9567.92" + cell $mux $ternary$build/ls180/gateware/ls180.v:9567$2531 + parameter \WIDTH 1 + connect \A 1'z + connect \B \builder_inferedsdrtristate1__o + connect \S \builder_inferedsdrtristate1_oe + connect \Y $ternary$build/ls180/gateware/ls180.v:9567$2531_Y + end + attribute \src "build/ls180/gateware/ls180.v:9570.22-9570.92" + cell $mux $ternary$build/ls180/gateware/ls180.v:9570$2532 + parameter \WIDTH 1 + connect \A 1'z + connect \B \builder_inferedsdrtristate2__o + connect \S \builder_inferedsdrtristate2_oe + connect \Y $ternary$build/ls180/gateware/ls180.v:9570$2532_Y + end + attribute \src "build/ls180/gateware/ls180.v:9573.22-9573.92" + cell $mux $ternary$build/ls180/gateware/ls180.v:9573$2533 + parameter \WIDTH 1 + connect \A 1'z + connect \B \builder_inferedsdrtristate3__o + connect \S \builder_inferedsdrtristate3_oe + connect \Y $ternary$build/ls180/gateware/ls180.v:9573$2533_Y + end + attribute \src "build/ls180/gateware/ls180.v:9576.22-9576.92" + cell $mux $ternary$build/ls180/gateware/ls180.v:9576$2534 + parameter \WIDTH 1 + connect \A 1'z + connect \B \builder_inferedsdrtristate4__o + connect \S \builder_inferedsdrtristate4_oe + connect \Y $ternary$build/ls180/gateware/ls180.v:9576$2534_Y + end + attribute \src "build/ls180/gateware/ls180.v:9579.22-9579.92" + cell $mux $ternary$build/ls180/gateware/ls180.v:9579$2535 + parameter \WIDTH 1 + connect \A 1'z + connect \B \builder_inferedsdrtristate5__o + connect \S \builder_inferedsdrtristate5_oe + connect \Y $ternary$build/ls180/gateware/ls180.v:9579$2535_Y + end + attribute \src "build/ls180/gateware/ls180.v:9582.22-9582.92" + cell $mux $ternary$build/ls180/gateware/ls180.v:9582$2536 + parameter \WIDTH 1 + connect \A 1'z + connect \B \builder_inferedsdrtristate6__o + connect \S \builder_inferedsdrtristate6_oe + connect \Y $ternary$build/ls180/gateware/ls180.v:9582$2536_Y + end + attribute \src "build/ls180/gateware/ls180.v:9585.22-9585.92" + cell $mux $ternary$build/ls180/gateware/ls180.v:9585$2537 + parameter \WIDTH 1 + connect \A 1'z + connect \B \builder_inferedsdrtristate7__o + connect \S \builder_inferedsdrtristate7_oe + connect \Y $ternary$build/ls180/gateware/ls180.v:9585$2537_Y + end + attribute \src "build/ls180/gateware/ls180.v:9588.22-9588.92" + cell $mux $ternary$build/ls180/gateware/ls180.v:9588$2538 + parameter \WIDTH 1 + connect \A 1'z + connect \B \builder_inferedsdrtristate8__o + connect \S \builder_inferedsdrtristate8_oe + connect \Y $ternary$build/ls180/gateware/ls180.v:9588$2538_Y + end + attribute \src "build/ls180/gateware/ls180.v:9591.22-9591.92" + cell $mux $ternary$build/ls180/gateware/ls180.v:9591$2539 + parameter \WIDTH 1 + connect \A 1'z + connect \B \builder_inferedsdrtristate9__o + connect \S \builder_inferedsdrtristate9_oe + connect \Y $ternary$build/ls180/gateware/ls180.v:9591$2539_Y + end + attribute \src "build/ls180/gateware/ls180.v:9594.23-9594.95" + cell $mux $ternary$build/ls180/gateware/ls180.v:9594$2540 + parameter \WIDTH 1 + connect \A 1'z + connect \B \builder_inferedsdrtristate10__o + connect \S \builder_inferedsdrtristate10_oe + connect \Y $ternary$build/ls180/gateware/ls180.v:9594$2540_Y + end + attribute \src "build/ls180/gateware/ls180.v:9597.23-9597.95" + cell $mux $ternary$build/ls180/gateware/ls180.v:9597$2541 + parameter \WIDTH 1 + connect \A 1'z + connect \B \builder_inferedsdrtristate11__o + connect \S \builder_inferedsdrtristate11_oe + connect \Y $ternary$build/ls180/gateware/ls180.v:9597$2541_Y + end + attribute \src "build/ls180/gateware/ls180.v:9600.23-9600.95" + cell $mux $ternary$build/ls180/gateware/ls180.v:9600$2542 + parameter \WIDTH 1 + connect \A 1'z + connect \B \builder_inferedsdrtristate12__o + connect \S \builder_inferedsdrtristate12_oe + connect \Y $ternary$build/ls180/gateware/ls180.v:9600$2542_Y + end + attribute \src "build/ls180/gateware/ls180.v:9603.23-9603.95" + cell $mux $ternary$build/ls180/gateware/ls180.v:9603$2543 + parameter \WIDTH 1 + connect \A 1'z + connect \B \builder_inferedsdrtristate13__o + connect \S \builder_inferedsdrtristate13_oe + connect \Y $ternary$build/ls180/gateware/ls180.v:9603$2543_Y + end + attribute \src "build/ls180/gateware/ls180.v:9606.23-9606.95" + cell $mux $ternary$build/ls180/gateware/ls180.v:9606$2544 + parameter \WIDTH 1 + connect \A 1'z + connect \B \builder_inferedsdrtristate14__o + connect \S \builder_inferedsdrtristate14_oe + connect \Y $ternary$build/ls180/gateware/ls180.v:9606$2544_Y + end + attribute \src "build/ls180/gateware/ls180.v:9609.23-9609.95" + cell $mux $ternary$build/ls180/gateware/ls180.v:9609$2545 + parameter \WIDTH 1 + connect \A 1'z + connect \B \builder_inferedsdrtristate15__o + connect \S \builder_inferedsdrtristate15_oe + connect \Y $ternary$build/ls180/gateware/ls180.v:9609$2545_Y + end + attribute \src "build/ls180/gateware/ls180.v:9612.21-9612.93" + cell $mux $ternary$build/ls180/gateware/ls180.v:9612$2546 + parameter \WIDTH 1 + connect \A 1'z + connect \B \builder_inferedsdrtristate16__o + connect \S \builder_inferedsdrtristate16_oe + connect \Y $ternary$build/ls180/gateware/ls180.v:9612$2546_Y + end + attribute \src "build/ls180/gateware/ls180.v:9615.25-9615.97" + cell $mux $ternary$build/ls180/gateware/ls180.v:9615$2547 + parameter \WIDTH 1 + connect \A 1'z + connect \B \builder_inferedsdrtristate17__o + connect \S \builder_inferedsdrtristate17_oe + connect \Y $ternary$build/ls180/gateware/ls180.v:9615$2547_Y + end + attribute \src "build/ls180/gateware/ls180.v:9618.25-9618.97" + cell $mux $ternary$build/ls180/gateware/ls180.v:9618$2548 + parameter \WIDTH 1 + connect \A 1'z + connect \B \builder_inferedsdrtristate18__o + connect \S \builder_inferedsdrtristate18_oe + connect \Y $ternary$build/ls180/gateware/ls180.v:9618$2548_Y + end + attribute \src "build/ls180/gateware/ls180.v:9621.25-9621.97" + cell $mux $ternary$build/ls180/gateware/ls180.v:9621$2549 + parameter \WIDTH 1 + connect \A 1'z + connect \B \builder_inferedsdrtristate19__o + connect \S \builder_inferedsdrtristate19_oe + connect \Y $ternary$build/ls180/gateware/ls180.v:9621$2549_Y + end + attribute \src "build/ls180/gateware/ls180.v:9624.25-9624.97" + cell $mux $ternary$build/ls180/gateware/ls180.v:9624$2550 + parameter \WIDTH 1 + connect \A 1'z + connect \B \builder_inferedsdrtristate20__o + connect \S \builder_inferedsdrtristate20_oe + connect \Y $ternary$build/ls180/gateware/ls180.v:9624$2550_Y + end + attribute \src "build/ls180/gateware/ls180.v:4619.416-4619.502" + cell $xor $xor$build/ls180/gateware/ls180.v:4619$692 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \libresocsim_sdcore_crc7_inserter_val [39] + connect \B \libresocsim_sdcore_crc7_inserter_crcreg0 [6] + connect \Y $xor$build/ls180/gateware/ls180.v:4619$692_Y + end + attribute \src "build/ls180/gateware/ls180.v:4619.235-4619.321" + cell $xor $xor$build/ls180/gateware/ls180.v:4619$693 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \libresocsim_sdcore_crc7_inserter_val [39] + connect \B \libresocsim_sdcore_crc7_inserter_crcreg0 [6] + connect \Y $xor$build/ls180/gateware/ls180.v:4619$693_Y + end + attribute \src "build/ls180/gateware/ls180.v:4619.188-4619.322" + cell $xor $xor$build/ls180/gateware/ls180.v:4619$694 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \libresocsim_sdcore_crc7_inserter_crcreg0 [2] + connect \B $xor$build/ls180/gateware/ls180.v:4619$693_Y + connect \Y $xor$build/ls180/gateware/ls180.v:4619$694_Y + end + attribute \src "build/ls180/gateware/ls180.v:4620.416-4620.502" + cell $xor $xor$build/ls180/gateware/ls180.v:4620$695 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \libresocsim_sdcore_crc7_inserter_val [38] + connect \B \libresocsim_sdcore_crc7_inserter_crcreg1 [6] + connect \Y $xor$build/ls180/gateware/ls180.v:4620$695_Y + end + attribute \src "build/ls180/gateware/ls180.v:4620.235-4620.321" + cell $xor $xor$build/ls180/gateware/ls180.v:4620$696 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \libresocsim_sdcore_crc7_inserter_val [38] + connect \B \libresocsim_sdcore_crc7_inserter_crcreg1 [6] + connect \Y $xor$build/ls180/gateware/ls180.v:4620$696_Y + end + attribute \src "build/ls180/gateware/ls180.v:4620.188-4620.322" + cell $xor $xor$build/ls180/gateware/ls180.v:4620$697 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \libresocsim_sdcore_crc7_inserter_crcreg1 [2] + connect \B $xor$build/ls180/gateware/ls180.v:4620$696_Y + connect \Y $xor$build/ls180/gateware/ls180.v:4620$697_Y + end + attribute \src "build/ls180/gateware/ls180.v:4621.416-4621.502" + cell $xor $xor$build/ls180/gateware/ls180.v:4621$698 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \libresocsim_sdcore_crc7_inserter_val [37] + connect \B \libresocsim_sdcore_crc7_inserter_crcreg2 [6] + connect \Y $xor$build/ls180/gateware/ls180.v:4621$698_Y + end + attribute \src "build/ls180/gateware/ls180.v:4621.235-4621.321" + cell $xor $xor$build/ls180/gateware/ls180.v:4621$699 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \libresocsim_sdcore_crc7_inserter_val [37] + connect \B \libresocsim_sdcore_crc7_inserter_crcreg2 [6] + connect \Y $xor$build/ls180/gateware/ls180.v:4621$699_Y + end + attribute \src "build/ls180/gateware/ls180.v:4621.188-4621.322" + cell $xor $xor$build/ls180/gateware/ls180.v:4621$700 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \libresocsim_sdcore_crc7_inserter_crcreg2 [2] + connect \B $xor$build/ls180/gateware/ls180.v:4621$699_Y + connect \Y $xor$build/ls180/gateware/ls180.v:4621$700_Y + end + attribute \src "build/ls180/gateware/ls180.v:4622.416-4622.502" + cell $xor $xor$build/ls180/gateware/ls180.v:4622$701 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \libresocsim_sdcore_crc7_inserter_val [36] + connect \B \libresocsim_sdcore_crc7_inserter_crcreg3 [6] + connect \Y $xor$build/ls180/gateware/ls180.v:4622$701_Y + end + attribute \src "build/ls180/gateware/ls180.v:4622.235-4622.321" + cell $xor $xor$build/ls180/gateware/ls180.v:4622$702 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \libresocsim_sdcore_crc7_inserter_val [36] + connect \B \libresocsim_sdcore_crc7_inserter_crcreg3 [6] + connect \Y $xor$build/ls180/gateware/ls180.v:4622$702_Y + end + attribute \src "build/ls180/gateware/ls180.v:4622.188-4622.322" + cell $xor $xor$build/ls180/gateware/ls180.v:4622$703 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \libresocsim_sdcore_crc7_inserter_crcreg3 [2] + connect \B $xor$build/ls180/gateware/ls180.v:4622$702_Y + connect \Y $xor$build/ls180/gateware/ls180.v:4622$703_Y + end + attribute \src "build/ls180/gateware/ls180.v:4623.416-4623.502" + cell $xor $xor$build/ls180/gateware/ls180.v:4623$704 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \libresocsim_sdcore_crc7_inserter_val [35] + connect \B \libresocsim_sdcore_crc7_inserter_crcreg4 [6] + connect \Y $xor$build/ls180/gateware/ls180.v:4623$704_Y + end + attribute \src "build/ls180/gateware/ls180.v:4623.235-4623.321" + cell $xor $xor$build/ls180/gateware/ls180.v:4623$705 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \libresocsim_sdcore_crc7_inserter_val [35] + connect \B \libresocsim_sdcore_crc7_inserter_crcreg4 [6] + connect \Y $xor$build/ls180/gateware/ls180.v:4623$705_Y + end + attribute \src "build/ls180/gateware/ls180.v:4623.188-4623.322" + cell $xor $xor$build/ls180/gateware/ls180.v:4623$706 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \libresocsim_sdcore_crc7_inserter_crcreg4 [2] + connect \B $xor$build/ls180/gateware/ls180.v:4623$705_Y + connect \Y $xor$build/ls180/gateware/ls180.v:4623$706_Y + end + attribute \src "build/ls180/gateware/ls180.v:4624.416-4624.502" + cell $xor $xor$build/ls180/gateware/ls180.v:4624$707 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \libresocsim_sdcore_crc7_inserter_val [34] + connect \B \libresocsim_sdcore_crc7_inserter_crcreg5 [6] + connect \Y $xor$build/ls180/gateware/ls180.v:4624$707_Y + end + attribute \src "build/ls180/gateware/ls180.v:4624.235-4624.321" + cell $xor $xor$build/ls180/gateware/ls180.v:4624$708 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \libresocsim_sdcore_crc7_inserter_val [34] + connect \B \libresocsim_sdcore_crc7_inserter_crcreg5 [6] + connect \Y $xor$build/ls180/gateware/ls180.v:4624$708_Y + end + attribute \src "build/ls180/gateware/ls180.v:4624.188-4624.322" + cell $xor $xor$build/ls180/gateware/ls180.v:4624$709 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \libresocsim_sdcore_crc7_inserter_crcreg5 [2] + connect \B $xor$build/ls180/gateware/ls180.v:4624$708_Y + connect \Y $xor$build/ls180/gateware/ls180.v:4624$709_Y + end + attribute \src "build/ls180/gateware/ls180.v:4625.416-4625.502" + cell $xor $xor$build/ls180/gateware/ls180.v:4625$710 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \libresocsim_sdcore_crc7_inserter_val [33] + connect \B \libresocsim_sdcore_crc7_inserter_crcreg6 [6] + connect \Y $xor$build/ls180/gateware/ls180.v:4625$710_Y + end + attribute \src "build/ls180/gateware/ls180.v:4625.235-4625.321" + cell $xor $xor$build/ls180/gateware/ls180.v:4625$711 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \libresocsim_sdcore_crc7_inserter_val [33] + connect \B \libresocsim_sdcore_crc7_inserter_crcreg6 [6] + connect \Y $xor$build/ls180/gateware/ls180.v:4625$711_Y + end + attribute \src "build/ls180/gateware/ls180.v:4625.188-4625.322" + cell $xor $xor$build/ls180/gateware/ls180.v:4625$712 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \libresocsim_sdcore_crc7_inserter_crcreg6 [2] + connect \B $xor$build/ls180/gateware/ls180.v:4625$711_Y + connect \Y $xor$build/ls180/gateware/ls180.v:4625$712_Y + end + attribute \src "build/ls180/gateware/ls180.v:4626.416-4626.502" + cell $xor $xor$build/ls180/gateware/ls180.v:4626$713 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \libresocsim_sdcore_crc7_inserter_val [32] + connect \B \libresocsim_sdcore_crc7_inserter_crcreg7 [6] + connect \Y $xor$build/ls180/gateware/ls180.v:4626$713_Y + end + attribute \src "build/ls180/gateware/ls180.v:4626.235-4626.321" + cell $xor $xor$build/ls180/gateware/ls180.v:4626$714 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \libresocsim_sdcore_crc7_inserter_val [32] + connect \B \libresocsim_sdcore_crc7_inserter_crcreg7 [6] + connect \Y $xor$build/ls180/gateware/ls180.v:4626$714_Y + end + attribute \src "build/ls180/gateware/ls180.v:4626.188-4626.322" + cell $xor $xor$build/ls180/gateware/ls180.v:4626$715 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \libresocsim_sdcore_crc7_inserter_crcreg7 [2] + connect \B $xor$build/ls180/gateware/ls180.v:4626$714_Y + connect \Y $xor$build/ls180/gateware/ls180.v:4626$715_Y + end + attribute \src "build/ls180/gateware/ls180.v:4627.416-4627.502" + cell $xor $xor$build/ls180/gateware/ls180.v:4627$716 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \libresocsim_sdcore_crc7_inserter_val [31] + connect \B \libresocsim_sdcore_crc7_inserter_crcreg8 [6] + connect \Y $xor$build/ls180/gateware/ls180.v:4627$716_Y + end + attribute \src "build/ls180/gateware/ls180.v:4627.235-4627.321" + cell $xor $xor$build/ls180/gateware/ls180.v:4627$717 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \libresocsim_sdcore_crc7_inserter_val [31] + connect \B \libresocsim_sdcore_crc7_inserter_crcreg8 [6] + connect \Y $xor$build/ls180/gateware/ls180.v:4627$717_Y + end + attribute \src "build/ls180/gateware/ls180.v:4627.188-4627.322" + cell $xor $xor$build/ls180/gateware/ls180.v:4627$718 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \libresocsim_sdcore_crc7_inserter_crcreg8 [2] + connect \B $xor$build/ls180/gateware/ls180.v:4627$717_Y + connect \Y $xor$build/ls180/gateware/ls180.v:4627$718_Y + end + attribute \src "build/ls180/gateware/ls180.v:4628.417-4628.503" + cell $xor $xor$build/ls180/gateware/ls180.v:4628$719 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \libresocsim_sdcore_crc7_inserter_val [30] + connect \B \libresocsim_sdcore_crc7_inserter_crcreg9 [6] + connect \Y $xor$build/ls180/gateware/ls180.v:4628$719_Y + end + attribute \src "build/ls180/gateware/ls180.v:4628.236-4628.322" + cell $xor $xor$build/ls180/gateware/ls180.v:4628$720 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \libresocsim_sdcore_crc7_inserter_val [30] + connect \B \libresocsim_sdcore_crc7_inserter_crcreg9 [6] + connect \Y $xor$build/ls180/gateware/ls180.v:4628$720_Y + end + attribute \src "build/ls180/gateware/ls180.v:4628.189-4628.323" + cell $xor $xor$build/ls180/gateware/ls180.v:4628$721 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \libresocsim_sdcore_crc7_inserter_crcreg9 [2] + connect \B $xor$build/ls180/gateware/ls180.v:4628$720_Y + connect \Y $xor$build/ls180/gateware/ls180.v:4628$721_Y + end + attribute \src "build/ls180/gateware/ls180.v:4629.424-4629.511" + cell $xor $xor$build/ls180/gateware/ls180.v:4629$722 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \libresocsim_sdcore_crc7_inserter_val [29] + connect \B \libresocsim_sdcore_crc7_inserter_crcreg10 [6] + connect \Y $xor$build/ls180/gateware/ls180.v:4629$722_Y + end + attribute \src "build/ls180/gateware/ls180.v:4629.240-4629.327" + cell $xor $xor$build/ls180/gateware/ls180.v:4629$723 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \libresocsim_sdcore_crc7_inserter_val [29] + connect \B \libresocsim_sdcore_crc7_inserter_crcreg10 [6] + connect \Y $xor$build/ls180/gateware/ls180.v:4629$723_Y + end + attribute \src "build/ls180/gateware/ls180.v:4629.192-4629.328" + cell $xor $xor$build/ls180/gateware/ls180.v:4629$724 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \libresocsim_sdcore_crc7_inserter_crcreg10 [2] + connect \B $xor$build/ls180/gateware/ls180.v:4629$723_Y + connect \Y $xor$build/ls180/gateware/ls180.v:4629$724_Y + end + attribute \src "build/ls180/gateware/ls180.v:4630.424-4630.511" + cell $xor $xor$build/ls180/gateware/ls180.v:4630$725 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \libresocsim_sdcore_crc7_inserter_val [28] + connect \B \libresocsim_sdcore_crc7_inserter_crcreg11 [6] + connect \Y $xor$build/ls180/gateware/ls180.v:4630$725_Y + end + attribute \src "build/ls180/gateware/ls180.v:4630.240-4630.327" + cell $xor $xor$build/ls180/gateware/ls180.v:4630$726 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \libresocsim_sdcore_crc7_inserter_val [28] + connect \B \libresocsim_sdcore_crc7_inserter_crcreg11 [6] + connect \Y $xor$build/ls180/gateware/ls180.v:4630$726_Y + end + attribute \src "build/ls180/gateware/ls180.v:4630.192-4630.328" + cell $xor $xor$build/ls180/gateware/ls180.v:4630$727 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \libresocsim_sdcore_crc7_inserter_crcreg11 [2] + connect \B $xor$build/ls180/gateware/ls180.v:4630$726_Y + connect \Y $xor$build/ls180/gateware/ls180.v:4630$727_Y + end + attribute \src "build/ls180/gateware/ls180.v:4631.424-4631.511" + cell $xor $xor$build/ls180/gateware/ls180.v:4631$728 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \libresocsim_sdcore_crc7_inserter_val [27] + connect \B \libresocsim_sdcore_crc7_inserter_crcreg12 [6] + connect \Y $xor$build/ls180/gateware/ls180.v:4631$728_Y + end + attribute \src "build/ls180/gateware/ls180.v:4631.240-4631.327" + cell $xor $xor$build/ls180/gateware/ls180.v:4631$729 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \libresocsim_sdcore_crc7_inserter_val [27] + connect \B \libresocsim_sdcore_crc7_inserter_crcreg12 [6] + connect \Y $xor$build/ls180/gateware/ls180.v:4631$729_Y + end + attribute \src "build/ls180/gateware/ls180.v:4631.192-4631.328" + cell $xor $xor$build/ls180/gateware/ls180.v:4631$730 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \libresocsim_sdcore_crc7_inserter_crcreg12 [2] + connect \B $xor$build/ls180/gateware/ls180.v:4631$729_Y + connect \Y $xor$build/ls180/gateware/ls180.v:4631$730_Y + end + attribute \src "build/ls180/gateware/ls180.v:4632.424-4632.511" + cell $xor $xor$build/ls180/gateware/ls180.v:4632$731 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \libresocsim_sdcore_crc7_inserter_val [26] + connect \B \libresocsim_sdcore_crc7_inserter_crcreg13 [6] + connect \Y $xor$build/ls180/gateware/ls180.v:4632$731_Y + end + attribute \src "build/ls180/gateware/ls180.v:4632.240-4632.327" + cell $xor $xor$build/ls180/gateware/ls180.v:4632$732 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \libresocsim_sdcore_crc7_inserter_val [26] + connect \B \libresocsim_sdcore_crc7_inserter_crcreg13 [6] + connect \Y $xor$build/ls180/gateware/ls180.v:4632$732_Y + end + attribute \src "build/ls180/gateware/ls180.v:4632.192-4632.328" + cell $xor $xor$build/ls180/gateware/ls180.v:4632$733 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \libresocsim_sdcore_crc7_inserter_crcreg13 [2] + connect \B $xor$build/ls180/gateware/ls180.v:4632$732_Y + connect \Y $xor$build/ls180/gateware/ls180.v:4632$733_Y + end + attribute \src "build/ls180/gateware/ls180.v:4633.424-4633.511" + cell $xor $xor$build/ls180/gateware/ls180.v:4633$734 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \libresocsim_sdcore_crc7_inserter_val [25] + connect \B \libresocsim_sdcore_crc7_inserter_crcreg14 [6] + connect \Y $xor$build/ls180/gateware/ls180.v:4633$734_Y + end + attribute \src "build/ls180/gateware/ls180.v:4633.240-4633.327" + cell $xor $xor$build/ls180/gateware/ls180.v:4633$735 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \libresocsim_sdcore_crc7_inserter_val [25] + connect \B \libresocsim_sdcore_crc7_inserter_crcreg14 [6] + connect \Y $xor$build/ls180/gateware/ls180.v:4633$735_Y + end + attribute \src "build/ls180/gateware/ls180.v:4633.192-4633.328" + cell $xor $xor$build/ls180/gateware/ls180.v:4633$736 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \libresocsim_sdcore_crc7_inserter_crcreg14 [2] + connect \B $xor$build/ls180/gateware/ls180.v:4633$735_Y + connect \Y $xor$build/ls180/gateware/ls180.v:4633$736_Y + end + attribute \src "build/ls180/gateware/ls180.v:4634.424-4634.511" + cell $xor $xor$build/ls180/gateware/ls180.v:4634$737 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \libresocsim_sdcore_crc7_inserter_val [24] + connect \B \libresocsim_sdcore_crc7_inserter_crcreg15 [6] + connect \Y $xor$build/ls180/gateware/ls180.v:4634$737_Y + end + attribute \src "build/ls180/gateware/ls180.v:4634.240-4634.327" + cell $xor $xor$build/ls180/gateware/ls180.v:4634$738 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \libresocsim_sdcore_crc7_inserter_val [24] + connect \B \libresocsim_sdcore_crc7_inserter_crcreg15 [6] + connect \Y $xor$build/ls180/gateware/ls180.v:4634$738_Y + end + attribute \src "build/ls180/gateware/ls180.v:4634.192-4634.328" + cell $xor $xor$build/ls180/gateware/ls180.v:4634$739 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \libresocsim_sdcore_crc7_inserter_crcreg15 [2] + connect \B $xor$build/ls180/gateware/ls180.v:4634$738_Y + connect \Y $xor$build/ls180/gateware/ls180.v:4634$739_Y + end + attribute \src "build/ls180/gateware/ls180.v:4635.424-4635.511" + cell $xor $xor$build/ls180/gateware/ls180.v:4635$740 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \libresocsim_sdcore_crc7_inserter_val [23] + connect \B \libresocsim_sdcore_crc7_inserter_crcreg16 [6] + connect \Y $xor$build/ls180/gateware/ls180.v:4635$740_Y + end + attribute \src "build/ls180/gateware/ls180.v:4635.240-4635.327" + cell $xor $xor$build/ls180/gateware/ls180.v:4635$741 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \libresocsim_sdcore_crc7_inserter_val [23] + connect \B \libresocsim_sdcore_crc7_inserter_crcreg16 [6] + connect \Y $xor$build/ls180/gateware/ls180.v:4635$741_Y + end + attribute \src "build/ls180/gateware/ls180.v:4635.192-4635.328" + cell $xor $xor$build/ls180/gateware/ls180.v:4635$742 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \libresocsim_sdcore_crc7_inserter_crcreg16 [2] + connect \B $xor$build/ls180/gateware/ls180.v:4635$741_Y + connect \Y $xor$build/ls180/gateware/ls180.v:4635$742_Y + end + attribute \src "build/ls180/gateware/ls180.v:4636.424-4636.511" + cell $xor $xor$build/ls180/gateware/ls180.v:4636$743 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \libresocsim_sdcore_crc7_inserter_val [22] + connect \B \libresocsim_sdcore_crc7_inserter_crcreg17 [6] + connect \Y $xor$build/ls180/gateware/ls180.v:4636$743_Y + end + attribute \src "build/ls180/gateware/ls180.v:4636.240-4636.327" + cell $xor $xor$build/ls180/gateware/ls180.v:4636$744 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \libresocsim_sdcore_crc7_inserter_val [22] + connect \B \libresocsim_sdcore_crc7_inserter_crcreg17 [6] + connect \Y $xor$build/ls180/gateware/ls180.v:4636$744_Y + end + attribute \src "build/ls180/gateware/ls180.v:4636.192-4636.328" + cell $xor $xor$build/ls180/gateware/ls180.v:4636$745 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \libresocsim_sdcore_crc7_inserter_crcreg17 [2] + connect \B $xor$build/ls180/gateware/ls180.v:4636$744_Y + connect \Y $xor$build/ls180/gateware/ls180.v:4636$745_Y + end + attribute \src "build/ls180/gateware/ls180.v:4637.424-4637.511" + cell $xor $xor$build/ls180/gateware/ls180.v:4637$746 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \libresocsim_sdcore_crc7_inserter_val [21] + connect \B \libresocsim_sdcore_crc7_inserter_crcreg18 [6] + connect \Y $xor$build/ls180/gateware/ls180.v:4637$746_Y + end + attribute \src "build/ls180/gateware/ls180.v:4637.240-4637.327" + cell $xor $xor$build/ls180/gateware/ls180.v:4637$747 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \libresocsim_sdcore_crc7_inserter_val [21] + connect \B \libresocsim_sdcore_crc7_inserter_crcreg18 [6] + connect \Y $xor$build/ls180/gateware/ls180.v:4637$747_Y + end + attribute \src "build/ls180/gateware/ls180.v:4637.192-4637.328" + cell $xor $xor$build/ls180/gateware/ls180.v:4637$748 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \libresocsim_sdcore_crc7_inserter_crcreg18 [2] + connect \B $xor$build/ls180/gateware/ls180.v:4637$747_Y + connect \Y $xor$build/ls180/gateware/ls180.v:4637$748_Y + end + attribute \src "build/ls180/gateware/ls180.v:4638.424-4638.511" + cell $xor $xor$build/ls180/gateware/ls180.v:4638$749 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \libresocsim_sdcore_crc7_inserter_val [20] + connect \B \libresocsim_sdcore_crc7_inserter_crcreg19 [6] + connect \Y $xor$build/ls180/gateware/ls180.v:4638$749_Y + end + attribute \src "build/ls180/gateware/ls180.v:4638.240-4638.327" + cell $xor $xor$build/ls180/gateware/ls180.v:4638$750 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \libresocsim_sdcore_crc7_inserter_val [20] + connect \B \libresocsim_sdcore_crc7_inserter_crcreg19 [6] + connect \Y $xor$build/ls180/gateware/ls180.v:4638$750_Y + end + attribute \src "build/ls180/gateware/ls180.v:4638.192-4638.328" + cell $xor $xor$build/ls180/gateware/ls180.v:4638$751 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \libresocsim_sdcore_crc7_inserter_crcreg19 [2] + connect \B $xor$build/ls180/gateware/ls180.v:4638$750_Y + connect \Y $xor$build/ls180/gateware/ls180.v:4638$751_Y + end + attribute \src "build/ls180/gateware/ls180.v:4639.424-4639.511" + cell $xor $xor$build/ls180/gateware/ls180.v:4639$752 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \libresocsim_sdcore_crc7_inserter_val [19] + connect \B \libresocsim_sdcore_crc7_inserter_crcreg20 [6] + connect \Y $xor$build/ls180/gateware/ls180.v:4639$752_Y + end + attribute \src "build/ls180/gateware/ls180.v:4639.240-4639.327" + cell $xor $xor$build/ls180/gateware/ls180.v:4639$753 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \libresocsim_sdcore_crc7_inserter_val [19] + connect \B \libresocsim_sdcore_crc7_inserter_crcreg20 [6] + connect \Y $xor$build/ls180/gateware/ls180.v:4639$753_Y + end + attribute \src "build/ls180/gateware/ls180.v:4639.192-4639.328" + cell $xor $xor$build/ls180/gateware/ls180.v:4639$754 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \libresocsim_sdcore_crc7_inserter_crcreg20 [2] + connect \B $xor$build/ls180/gateware/ls180.v:4639$753_Y + connect \Y $xor$build/ls180/gateware/ls180.v:4639$754_Y + end + attribute \src "build/ls180/gateware/ls180.v:4640.424-4640.511" + cell $xor $xor$build/ls180/gateware/ls180.v:4640$755 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \libresocsim_sdcore_crc7_inserter_val [18] + connect \B \libresocsim_sdcore_crc7_inserter_crcreg21 [6] + connect \Y $xor$build/ls180/gateware/ls180.v:4640$755_Y + end + attribute \src "build/ls180/gateware/ls180.v:4640.240-4640.327" + cell $xor $xor$build/ls180/gateware/ls180.v:4640$756 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \libresocsim_sdcore_crc7_inserter_val [18] + connect \B \libresocsim_sdcore_crc7_inserter_crcreg21 [6] + connect \Y $xor$build/ls180/gateware/ls180.v:4640$756_Y + end + attribute \src "build/ls180/gateware/ls180.v:4640.192-4640.328" + cell $xor $xor$build/ls180/gateware/ls180.v:4640$757 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \libresocsim_sdcore_crc7_inserter_crcreg21 [2] + connect \B $xor$build/ls180/gateware/ls180.v:4640$756_Y + connect \Y $xor$build/ls180/gateware/ls180.v:4640$757_Y + end + attribute \src "build/ls180/gateware/ls180.v:4641.424-4641.511" + cell $xor $xor$build/ls180/gateware/ls180.v:4641$758 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \libresocsim_sdcore_crc7_inserter_val [17] + connect \B \libresocsim_sdcore_crc7_inserter_crcreg22 [6] + connect \Y $xor$build/ls180/gateware/ls180.v:4641$758_Y + end + attribute \src "build/ls180/gateware/ls180.v:4641.240-4641.327" + cell $xor $xor$build/ls180/gateware/ls180.v:4641$759 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \libresocsim_sdcore_crc7_inserter_val [17] + connect \B \libresocsim_sdcore_crc7_inserter_crcreg22 [6] + connect \Y $xor$build/ls180/gateware/ls180.v:4641$759_Y + end + attribute \src "build/ls180/gateware/ls180.v:4641.192-4641.328" + cell $xor $xor$build/ls180/gateware/ls180.v:4641$760 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \libresocsim_sdcore_crc7_inserter_crcreg22 [2] + connect \B $xor$build/ls180/gateware/ls180.v:4641$759_Y + connect \Y $xor$build/ls180/gateware/ls180.v:4641$760_Y + end + attribute \src "build/ls180/gateware/ls180.v:4642.424-4642.511" + cell $xor $xor$build/ls180/gateware/ls180.v:4642$761 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \libresocsim_sdcore_crc7_inserter_val [16] + connect \B \libresocsim_sdcore_crc7_inserter_crcreg23 [6] + connect \Y $xor$build/ls180/gateware/ls180.v:4642$761_Y + end + attribute \src "build/ls180/gateware/ls180.v:4642.240-4642.327" + cell $xor $xor$build/ls180/gateware/ls180.v:4642$762 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \libresocsim_sdcore_crc7_inserter_val [16] + connect \B \libresocsim_sdcore_crc7_inserter_crcreg23 [6] + connect \Y $xor$build/ls180/gateware/ls180.v:4642$762_Y + end + attribute \src "build/ls180/gateware/ls180.v:4642.192-4642.328" + cell $xor $xor$build/ls180/gateware/ls180.v:4642$763 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \libresocsim_sdcore_crc7_inserter_crcreg23 [2] + connect \B $xor$build/ls180/gateware/ls180.v:4642$762_Y + connect \Y $xor$build/ls180/gateware/ls180.v:4642$763_Y + end + attribute \src "build/ls180/gateware/ls180.v:4643.424-4643.511" + cell $xor $xor$build/ls180/gateware/ls180.v:4643$764 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \libresocsim_sdcore_crc7_inserter_val [15] + connect \B \libresocsim_sdcore_crc7_inserter_crcreg24 [6] + connect \Y $xor$build/ls180/gateware/ls180.v:4643$764_Y + end + attribute \src "build/ls180/gateware/ls180.v:4643.240-4643.327" + cell $xor $xor$build/ls180/gateware/ls180.v:4643$765 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \libresocsim_sdcore_crc7_inserter_val [15] + connect \B \libresocsim_sdcore_crc7_inserter_crcreg24 [6] + connect \Y $xor$build/ls180/gateware/ls180.v:4643$765_Y + end + attribute \src "build/ls180/gateware/ls180.v:4643.192-4643.328" + cell $xor $xor$build/ls180/gateware/ls180.v:4643$766 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \libresocsim_sdcore_crc7_inserter_crcreg24 [2] + connect \B $xor$build/ls180/gateware/ls180.v:4643$765_Y + connect \Y $xor$build/ls180/gateware/ls180.v:4643$766_Y + end + attribute \src "build/ls180/gateware/ls180.v:4644.424-4644.511" + cell $xor $xor$build/ls180/gateware/ls180.v:4644$767 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \libresocsim_sdcore_crc7_inserter_val [14] + connect \B \libresocsim_sdcore_crc7_inserter_crcreg25 [6] + connect \Y $xor$build/ls180/gateware/ls180.v:4644$767_Y + end + attribute \src "build/ls180/gateware/ls180.v:4644.240-4644.327" + cell $xor $xor$build/ls180/gateware/ls180.v:4644$768 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \libresocsim_sdcore_crc7_inserter_val [14] + connect \B \libresocsim_sdcore_crc7_inserter_crcreg25 [6] + connect \Y $xor$build/ls180/gateware/ls180.v:4644$768_Y + end + attribute \src "build/ls180/gateware/ls180.v:4644.192-4644.328" + cell $xor $xor$build/ls180/gateware/ls180.v:4644$769 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \libresocsim_sdcore_crc7_inserter_crcreg25 [2] + connect \B $xor$build/ls180/gateware/ls180.v:4644$768_Y + connect \Y $xor$build/ls180/gateware/ls180.v:4644$769_Y + end + attribute \src "build/ls180/gateware/ls180.v:4645.424-4645.511" + cell $xor $xor$build/ls180/gateware/ls180.v:4645$770 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \libresocsim_sdcore_crc7_inserter_val [13] + connect \B \libresocsim_sdcore_crc7_inserter_crcreg26 [6] + connect \Y $xor$build/ls180/gateware/ls180.v:4645$770_Y + end + attribute \src "build/ls180/gateware/ls180.v:4645.240-4645.327" + cell $xor $xor$build/ls180/gateware/ls180.v:4645$771 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \libresocsim_sdcore_crc7_inserter_val [13] + connect \B \libresocsim_sdcore_crc7_inserter_crcreg26 [6] + connect \Y $xor$build/ls180/gateware/ls180.v:4645$771_Y + end + attribute \src "build/ls180/gateware/ls180.v:4645.192-4645.328" + cell $xor $xor$build/ls180/gateware/ls180.v:4645$772 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \libresocsim_sdcore_crc7_inserter_crcreg26 [2] + connect \B $xor$build/ls180/gateware/ls180.v:4645$771_Y + connect \Y $xor$build/ls180/gateware/ls180.v:4645$772_Y + end + attribute \src "build/ls180/gateware/ls180.v:4646.424-4646.511" + cell $xor $xor$build/ls180/gateware/ls180.v:4646$773 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \libresocsim_sdcore_crc7_inserter_val [12] + connect \B \libresocsim_sdcore_crc7_inserter_crcreg27 [6] + connect \Y $xor$build/ls180/gateware/ls180.v:4646$773_Y + end + attribute \src "build/ls180/gateware/ls180.v:4646.240-4646.327" + cell $xor $xor$build/ls180/gateware/ls180.v:4646$774 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \libresocsim_sdcore_crc7_inserter_val [12] + connect \B \libresocsim_sdcore_crc7_inserter_crcreg27 [6] + connect \Y $xor$build/ls180/gateware/ls180.v:4646$774_Y + end + attribute \src "build/ls180/gateware/ls180.v:4646.192-4646.328" + cell $xor $xor$build/ls180/gateware/ls180.v:4646$775 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \libresocsim_sdcore_crc7_inserter_crcreg27 [2] + connect \B $xor$build/ls180/gateware/ls180.v:4646$774_Y + connect \Y $xor$build/ls180/gateware/ls180.v:4646$775_Y + end + attribute \src "build/ls180/gateware/ls180.v:4647.424-4647.511" + cell $xor $xor$build/ls180/gateware/ls180.v:4647$776 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \libresocsim_sdcore_crc7_inserter_val [11] + connect \B \libresocsim_sdcore_crc7_inserter_crcreg28 [6] + connect \Y $xor$build/ls180/gateware/ls180.v:4647$776_Y + end + attribute \src "build/ls180/gateware/ls180.v:4647.240-4647.327" + cell $xor $xor$build/ls180/gateware/ls180.v:4647$777 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \libresocsim_sdcore_crc7_inserter_val [11] + connect \B \libresocsim_sdcore_crc7_inserter_crcreg28 [6] + connect \Y $xor$build/ls180/gateware/ls180.v:4647$777_Y + end + attribute \src "build/ls180/gateware/ls180.v:4647.192-4647.328" + cell $xor $xor$build/ls180/gateware/ls180.v:4647$778 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \libresocsim_sdcore_crc7_inserter_crcreg28 [2] + connect \B $xor$build/ls180/gateware/ls180.v:4647$777_Y + connect \Y $xor$build/ls180/gateware/ls180.v:4647$778_Y + end + attribute \src "build/ls180/gateware/ls180.v:4648.424-4648.511" + cell $xor $xor$build/ls180/gateware/ls180.v:4648$779 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \libresocsim_sdcore_crc7_inserter_val [10] + connect \B \libresocsim_sdcore_crc7_inserter_crcreg29 [6] + connect \Y $xor$build/ls180/gateware/ls180.v:4648$779_Y + end + attribute \src "build/ls180/gateware/ls180.v:4648.240-4648.327" + cell $xor $xor$build/ls180/gateware/ls180.v:4648$780 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \libresocsim_sdcore_crc7_inserter_val [10] + connect \B \libresocsim_sdcore_crc7_inserter_crcreg29 [6] + connect \Y $xor$build/ls180/gateware/ls180.v:4648$780_Y + end + attribute \src "build/ls180/gateware/ls180.v:4648.192-4648.328" + cell $xor $xor$build/ls180/gateware/ls180.v:4648$781 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \libresocsim_sdcore_crc7_inserter_crcreg29 [2] + connect \B $xor$build/ls180/gateware/ls180.v:4648$780_Y + connect \Y $xor$build/ls180/gateware/ls180.v:4648$781_Y + end + attribute \src "build/ls180/gateware/ls180.v:4649.423-4649.509" + cell $xor $xor$build/ls180/gateware/ls180.v:4649$782 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \libresocsim_sdcore_crc7_inserter_val [9] + connect \B \libresocsim_sdcore_crc7_inserter_crcreg30 [6] + connect \Y $xor$build/ls180/gateware/ls180.v:4649$782_Y + end + attribute \src "build/ls180/gateware/ls180.v:4649.240-4649.326" + cell $xor $xor$build/ls180/gateware/ls180.v:4649$783 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \libresocsim_sdcore_crc7_inserter_val [9] + connect \B \libresocsim_sdcore_crc7_inserter_crcreg30 [6] + connect \Y $xor$build/ls180/gateware/ls180.v:4649$783_Y + end + attribute \src "build/ls180/gateware/ls180.v:4649.192-4649.327" + cell $xor $xor$build/ls180/gateware/ls180.v:4649$784 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \libresocsim_sdcore_crc7_inserter_crcreg30 [2] + connect \B $xor$build/ls180/gateware/ls180.v:4649$783_Y + connect \Y $xor$build/ls180/gateware/ls180.v:4649$784_Y + end + attribute \src "build/ls180/gateware/ls180.v:4650.423-4650.509" + cell $xor $xor$build/ls180/gateware/ls180.v:4650$785 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \libresocsim_sdcore_crc7_inserter_val [8] + connect \B \libresocsim_sdcore_crc7_inserter_crcreg31 [6] + connect \Y $xor$build/ls180/gateware/ls180.v:4650$785_Y + end + attribute \src "build/ls180/gateware/ls180.v:4650.240-4650.326" + cell $xor $xor$build/ls180/gateware/ls180.v:4650$786 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \libresocsim_sdcore_crc7_inserter_val [8] + connect \B \libresocsim_sdcore_crc7_inserter_crcreg31 [6] + connect \Y $xor$build/ls180/gateware/ls180.v:4650$786_Y + end + attribute \src "build/ls180/gateware/ls180.v:4650.192-4650.327" + cell $xor $xor$build/ls180/gateware/ls180.v:4650$787 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \libresocsim_sdcore_crc7_inserter_crcreg31 [2] + connect \B $xor$build/ls180/gateware/ls180.v:4650$786_Y + connect \Y $xor$build/ls180/gateware/ls180.v:4650$787_Y + end + attribute \src "build/ls180/gateware/ls180.v:4651.423-4651.509" + cell $xor $xor$build/ls180/gateware/ls180.v:4651$788 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \libresocsim_sdcore_crc7_inserter_val [7] + connect \B \libresocsim_sdcore_crc7_inserter_crcreg32 [6] + connect \Y $xor$build/ls180/gateware/ls180.v:4651$788_Y + end + attribute \src "build/ls180/gateware/ls180.v:4651.240-4651.326" + cell $xor $xor$build/ls180/gateware/ls180.v:4651$789 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \libresocsim_sdcore_crc7_inserter_val [7] + connect \B \libresocsim_sdcore_crc7_inserter_crcreg32 [6] + connect \Y $xor$build/ls180/gateware/ls180.v:4651$789_Y + end + attribute \src "build/ls180/gateware/ls180.v:4651.192-4651.327" + cell $xor $xor$build/ls180/gateware/ls180.v:4651$790 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \libresocsim_sdcore_crc7_inserter_crcreg32 [2] + connect \B $xor$build/ls180/gateware/ls180.v:4651$789_Y + connect \Y $xor$build/ls180/gateware/ls180.v:4651$790_Y + end + attribute \src "build/ls180/gateware/ls180.v:4652.423-4652.509" + cell $xor $xor$build/ls180/gateware/ls180.v:4652$791 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \libresocsim_sdcore_crc7_inserter_val [6] + connect \B \libresocsim_sdcore_crc7_inserter_crcreg33 [6] + connect \Y $xor$build/ls180/gateware/ls180.v:4652$791_Y + end + attribute \src "build/ls180/gateware/ls180.v:4652.240-4652.326" + cell $xor $xor$build/ls180/gateware/ls180.v:4652$792 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \libresocsim_sdcore_crc7_inserter_val [6] + connect \B \libresocsim_sdcore_crc7_inserter_crcreg33 [6] + connect \Y $xor$build/ls180/gateware/ls180.v:4652$792_Y + end + attribute \src "build/ls180/gateware/ls180.v:4652.192-4652.327" + cell $xor $xor$build/ls180/gateware/ls180.v:4652$793 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \libresocsim_sdcore_crc7_inserter_crcreg33 [2] + connect \B $xor$build/ls180/gateware/ls180.v:4652$792_Y + connect \Y $xor$build/ls180/gateware/ls180.v:4652$793_Y + end + attribute \src "build/ls180/gateware/ls180.v:4653.423-4653.509" + cell $xor $xor$build/ls180/gateware/ls180.v:4653$794 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \libresocsim_sdcore_crc7_inserter_val [5] + connect \B \libresocsim_sdcore_crc7_inserter_crcreg34 [6] + connect \Y $xor$build/ls180/gateware/ls180.v:4653$794_Y + end + attribute \src "build/ls180/gateware/ls180.v:4653.240-4653.326" + cell $xor $xor$build/ls180/gateware/ls180.v:4653$795 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \libresocsim_sdcore_crc7_inserter_val [5] + connect \B \libresocsim_sdcore_crc7_inserter_crcreg34 [6] + connect \Y $xor$build/ls180/gateware/ls180.v:4653$795_Y + end + attribute \src "build/ls180/gateware/ls180.v:4653.192-4653.327" + cell $xor $xor$build/ls180/gateware/ls180.v:4653$796 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \libresocsim_sdcore_crc7_inserter_crcreg34 [2] + connect \B $xor$build/ls180/gateware/ls180.v:4653$795_Y + connect \Y $xor$build/ls180/gateware/ls180.v:4653$796_Y + end + attribute \src "build/ls180/gateware/ls180.v:4654.423-4654.509" + cell $xor $xor$build/ls180/gateware/ls180.v:4654$797 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \libresocsim_sdcore_crc7_inserter_val [4] + connect \B \libresocsim_sdcore_crc7_inserter_crcreg35 [6] + connect \Y $xor$build/ls180/gateware/ls180.v:4654$797_Y + end + attribute \src "build/ls180/gateware/ls180.v:4654.240-4654.326" + cell $xor $xor$build/ls180/gateware/ls180.v:4654$798 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \libresocsim_sdcore_crc7_inserter_val [4] + connect \B \libresocsim_sdcore_crc7_inserter_crcreg35 [6] + connect \Y $xor$build/ls180/gateware/ls180.v:4654$798_Y + end + attribute \src "build/ls180/gateware/ls180.v:4654.192-4654.327" + cell $xor $xor$build/ls180/gateware/ls180.v:4654$799 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \libresocsim_sdcore_crc7_inserter_crcreg35 [2] + connect \B $xor$build/ls180/gateware/ls180.v:4654$798_Y + connect \Y $xor$build/ls180/gateware/ls180.v:4654$799_Y + end + attribute \src "build/ls180/gateware/ls180.v:4655.423-4655.509" + cell $xor $xor$build/ls180/gateware/ls180.v:4655$800 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \libresocsim_sdcore_crc7_inserter_val [3] + connect \B \libresocsim_sdcore_crc7_inserter_crcreg36 [6] + connect \Y $xor$build/ls180/gateware/ls180.v:4655$800_Y + end + attribute \src "build/ls180/gateware/ls180.v:4655.240-4655.326" + cell $xor $xor$build/ls180/gateware/ls180.v:4655$801 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \libresocsim_sdcore_crc7_inserter_val [3] + connect \B \libresocsim_sdcore_crc7_inserter_crcreg36 [6] + connect \Y $xor$build/ls180/gateware/ls180.v:4655$801_Y + end + attribute \src "build/ls180/gateware/ls180.v:4655.192-4655.327" + cell $xor $xor$build/ls180/gateware/ls180.v:4655$802 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \libresocsim_sdcore_crc7_inserter_crcreg36 [2] + connect \B $xor$build/ls180/gateware/ls180.v:4655$801_Y + connect \Y $xor$build/ls180/gateware/ls180.v:4655$802_Y + end + attribute \src "build/ls180/gateware/ls180.v:4656.423-4656.509" + cell $xor $xor$build/ls180/gateware/ls180.v:4656$803 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \libresocsim_sdcore_crc7_inserter_val [2] + connect \B \libresocsim_sdcore_crc7_inserter_crcreg37 [6] + connect \Y $xor$build/ls180/gateware/ls180.v:4656$803_Y + end + attribute \src "build/ls180/gateware/ls180.v:4656.240-4656.326" + cell $xor $xor$build/ls180/gateware/ls180.v:4656$804 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \libresocsim_sdcore_crc7_inserter_val [2] + connect \B \libresocsim_sdcore_crc7_inserter_crcreg37 [6] + connect \Y $xor$build/ls180/gateware/ls180.v:4656$804_Y + end + attribute \src "build/ls180/gateware/ls180.v:4656.192-4656.327" + cell $xor $xor$build/ls180/gateware/ls180.v:4656$805 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \libresocsim_sdcore_crc7_inserter_crcreg37 [2] + connect \B $xor$build/ls180/gateware/ls180.v:4656$804_Y + connect \Y $xor$build/ls180/gateware/ls180.v:4656$805_Y + end + attribute \src "build/ls180/gateware/ls180.v:4657.423-4657.509" + cell $xor $xor$build/ls180/gateware/ls180.v:4657$806 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \libresocsim_sdcore_crc7_inserter_val [1] + connect \B \libresocsim_sdcore_crc7_inserter_crcreg38 [6] + connect \Y $xor$build/ls180/gateware/ls180.v:4657$806_Y + end + attribute \src "build/ls180/gateware/ls180.v:4657.240-4657.326" + cell $xor $xor$build/ls180/gateware/ls180.v:4657$807 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \libresocsim_sdcore_crc7_inserter_val [1] + connect \B \libresocsim_sdcore_crc7_inserter_crcreg38 [6] + connect \Y $xor$build/ls180/gateware/ls180.v:4657$807_Y + end + attribute \src "build/ls180/gateware/ls180.v:4657.192-4657.327" + cell $xor $xor$build/ls180/gateware/ls180.v:4657$808 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \libresocsim_sdcore_crc7_inserter_crcreg38 [2] + connect \B $xor$build/ls180/gateware/ls180.v:4657$807_Y + connect \Y $xor$build/ls180/gateware/ls180.v:4657$808_Y + end + attribute \src "build/ls180/gateware/ls180.v:4658.423-4658.509" + cell $xor $xor$build/ls180/gateware/ls180.v:4658$809 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \libresocsim_sdcore_crc7_inserter_val [0] + connect \B \libresocsim_sdcore_crc7_inserter_crcreg39 [6] + connect \Y $xor$build/ls180/gateware/ls180.v:4658$809_Y + end + attribute \src "build/ls180/gateware/ls180.v:4658.240-4658.326" + cell $xor $xor$build/ls180/gateware/ls180.v:4658$810 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \libresocsim_sdcore_crc7_inserter_val [0] + connect \B \libresocsim_sdcore_crc7_inserter_crcreg39 [6] + connect \Y $xor$build/ls180/gateware/ls180.v:4658$810_Y + end + attribute \src "build/ls180/gateware/ls180.v:4658.192-4658.327" + cell $xor $xor$build/ls180/gateware/ls180.v:4658$811 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \libresocsim_sdcore_crc7_inserter_crcreg39 [2] + connect \B $xor$build/ls180/gateware/ls180.v:4658$810_Y + connect \Y $xor$build/ls180/gateware/ls180.v:4658$811_Y + end + attribute \src "build/ls180/gateware/ls180.v:4679.1039-4679.1137" + cell $xor $xor$build/ls180/gateware/ls180.v:4679$825 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \libresocsim_sdcore_crc16_inserter_crc0_val [1] + connect \B \libresocsim_sdcore_crc16_inserter_crc0_crcreg0 [15] + connect \Y $xor$build/ls180/gateware/ls180.v:4679$825_Y + end + attribute \src "build/ls180/gateware/ls180.v:4679.732-4679.830" + cell $xor $xor$build/ls180/gateware/ls180.v:4679$826 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \libresocsim_sdcore_crc16_inserter_crc0_val [1] + connect \B \libresocsim_sdcore_crc16_inserter_crc0_crcreg0 [15] + connect \Y $xor$build/ls180/gateware/ls180.v:4679$826_Y + end + attribute \src "build/ls180/gateware/ls180.v:4679.679-4679.831" + cell $xor $xor$build/ls180/gateware/ls180.v:4679$827 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \libresocsim_sdcore_crc16_inserter_crc0_crcreg0 [4] + connect \B $xor$build/ls180/gateware/ls180.v:4679$826_Y + connect \Y $xor$build/ls180/gateware/ls180.v:4679$827_Y + end + attribute \src "build/ls180/gateware/ls180.v:4679.269-4679.367" + cell $xor $xor$build/ls180/gateware/ls180.v:4679$828 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \libresocsim_sdcore_crc16_inserter_crc0_val [1] + connect \B \libresocsim_sdcore_crc16_inserter_crc0_crcreg0 [15] + connect \Y $xor$build/ls180/gateware/ls180.v:4679$828_Y + end + attribute \src "build/ls180/gateware/ls180.v:4679.215-4679.368" + cell $xor $xor$build/ls180/gateware/ls180.v:4679$829 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \libresocsim_sdcore_crc16_inserter_crc0_crcreg0 [11] + connect \B $xor$build/ls180/gateware/ls180.v:4679$828_Y + connect \Y $xor$build/ls180/gateware/ls180.v:4679$829_Y + end + attribute \src "build/ls180/gateware/ls180.v:4680.1039-4680.1137" + cell $xor $xor$build/ls180/gateware/ls180.v:4680$830 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \libresocsim_sdcore_crc16_inserter_crc0_val [0] + connect \B \libresocsim_sdcore_crc16_inserter_crc0_crcreg1 [15] + connect \Y $xor$build/ls180/gateware/ls180.v:4680$830_Y + end + attribute \src "build/ls180/gateware/ls180.v:4680.732-4680.830" + cell $xor $xor$build/ls180/gateware/ls180.v:4680$831 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \libresocsim_sdcore_crc16_inserter_crc0_val [0] + connect \B \libresocsim_sdcore_crc16_inserter_crc0_crcreg1 [15] + connect \Y $xor$build/ls180/gateware/ls180.v:4680$831_Y + end + attribute \src "build/ls180/gateware/ls180.v:4680.679-4680.831" + cell $xor $xor$build/ls180/gateware/ls180.v:4680$832 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \libresocsim_sdcore_crc16_inserter_crc0_crcreg1 [4] + connect \B $xor$build/ls180/gateware/ls180.v:4680$831_Y + connect \Y $xor$build/ls180/gateware/ls180.v:4680$832_Y + end + attribute \src "build/ls180/gateware/ls180.v:4680.269-4680.367" + cell $xor $xor$build/ls180/gateware/ls180.v:4680$833 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \libresocsim_sdcore_crc16_inserter_crc0_val [0] + connect \B \libresocsim_sdcore_crc16_inserter_crc0_crcreg1 [15] + connect \Y $xor$build/ls180/gateware/ls180.v:4680$833_Y + end + attribute \src "build/ls180/gateware/ls180.v:4680.215-4680.368" + cell $xor $xor$build/ls180/gateware/ls180.v:4680$834 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \libresocsim_sdcore_crc16_inserter_crc0_crcreg1 [11] + connect \B $xor$build/ls180/gateware/ls180.v:4680$833_Y + connect \Y $xor$build/ls180/gateware/ls180.v:4680$834_Y + end + attribute \src "build/ls180/gateware/ls180.v:4689.1039-4689.1137" + cell $xor $xor$build/ls180/gateware/ls180.v:4689$836 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \libresocsim_sdcore_crc16_inserter_crc1_val [1] + connect \B \libresocsim_sdcore_crc16_inserter_crc1_crcreg0 [15] + connect \Y $xor$build/ls180/gateware/ls180.v:4689$836_Y + end + attribute \src "build/ls180/gateware/ls180.v:4689.732-4689.830" + cell $xor $xor$build/ls180/gateware/ls180.v:4689$837 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \libresocsim_sdcore_crc16_inserter_crc1_val [1] + connect \B \libresocsim_sdcore_crc16_inserter_crc1_crcreg0 [15] + connect \Y $xor$build/ls180/gateware/ls180.v:4689$837_Y + end + attribute \src "build/ls180/gateware/ls180.v:4689.679-4689.831" + cell $xor $xor$build/ls180/gateware/ls180.v:4689$838 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \libresocsim_sdcore_crc16_inserter_crc1_crcreg0 [4] + connect \B $xor$build/ls180/gateware/ls180.v:4689$837_Y + connect \Y $xor$build/ls180/gateware/ls180.v:4689$838_Y + end + attribute \src "build/ls180/gateware/ls180.v:4689.269-4689.367" + cell $xor $xor$build/ls180/gateware/ls180.v:4689$839 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \libresocsim_sdcore_crc16_inserter_crc1_val [1] + connect \B \libresocsim_sdcore_crc16_inserter_crc1_crcreg0 [15] + connect \Y $xor$build/ls180/gateware/ls180.v:4689$839_Y + end + attribute \src "build/ls180/gateware/ls180.v:4689.215-4689.368" + cell $xor $xor$build/ls180/gateware/ls180.v:4689$840 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \libresocsim_sdcore_crc16_inserter_crc1_crcreg0 [11] + connect \B $xor$build/ls180/gateware/ls180.v:4689$839_Y + connect \Y $xor$build/ls180/gateware/ls180.v:4689$840_Y + end + attribute \src "build/ls180/gateware/ls180.v:4690.1039-4690.1137" + cell $xor $xor$build/ls180/gateware/ls180.v:4690$841 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \libresocsim_sdcore_crc16_inserter_crc1_val [0] + connect \B \libresocsim_sdcore_crc16_inserter_crc1_crcreg1 [15] + connect \Y $xor$build/ls180/gateware/ls180.v:4690$841_Y + end + attribute \src "build/ls180/gateware/ls180.v:4690.732-4690.830" + cell $xor $xor$build/ls180/gateware/ls180.v:4690$842 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \libresocsim_sdcore_crc16_inserter_crc1_val [0] + connect \B \libresocsim_sdcore_crc16_inserter_crc1_crcreg1 [15] + connect \Y $xor$build/ls180/gateware/ls180.v:4690$842_Y + end + attribute \src "build/ls180/gateware/ls180.v:4690.679-4690.831" + cell $xor $xor$build/ls180/gateware/ls180.v:4690$843 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \libresocsim_sdcore_crc16_inserter_crc1_crcreg1 [4] + connect \B $xor$build/ls180/gateware/ls180.v:4690$842_Y + connect \Y $xor$build/ls180/gateware/ls180.v:4690$843_Y + end + attribute \src "build/ls180/gateware/ls180.v:4690.269-4690.367" + cell $xor $xor$build/ls180/gateware/ls180.v:4690$844 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \libresocsim_sdcore_crc16_inserter_crc1_val [0] + connect \B \libresocsim_sdcore_crc16_inserter_crc1_crcreg1 [15] + connect \Y $xor$build/ls180/gateware/ls180.v:4690$844_Y + end + attribute \src "build/ls180/gateware/ls180.v:4690.215-4690.368" + cell $xor $xor$build/ls180/gateware/ls180.v:4690$845 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \libresocsim_sdcore_crc16_inserter_crc1_crcreg1 [11] + connect \B $xor$build/ls180/gateware/ls180.v:4690$844_Y + connect \Y $xor$build/ls180/gateware/ls180.v:4690$845_Y + end + attribute \src "build/ls180/gateware/ls180.v:4699.1039-4699.1137" + cell $xor $xor$build/ls180/gateware/ls180.v:4699$847 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \libresocsim_sdcore_crc16_inserter_crc2_val [1] + connect \B \libresocsim_sdcore_crc16_inserter_crc2_crcreg0 [15] + connect \Y $xor$build/ls180/gateware/ls180.v:4699$847_Y + end + attribute \src "build/ls180/gateware/ls180.v:4699.732-4699.830" + cell $xor $xor$build/ls180/gateware/ls180.v:4699$848 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \libresocsim_sdcore_crc16_inserter_crc2_val [1] + connect \B \libresocsim_sdcore_crc16_inserter_crc2_crcreg0 [15] + connect \Y $xor$build/ls180/gateware/ls180.v:4699$848_Y + end + attribute \src "build/ls180/gateware/ls180.v:4699.679-4699.831" + cell $xor $xor$build/ls180/gateware/ls180.v:4699$849 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \libresocsim_sdcore_crc16_inserter_crc2_crcreg0 [4] + connect \B $xor$build/ls180/gateware/ls180.v:4699$848_Y + connect \Y $xor$build/ls180/gateware/ls180.v:4699$849_Y + end + attribute \src "build/ls180/gateware/ls180.v:4699.269-4699.367" + cell $xor $xor$build/ls180/gateware/ls180.v:4699$850 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \libresocsim_sdcore_crc16_inserter_crc2_val [1] + connect \B \libresocsim_sdcore_crc16_inserter_crc2_crcreg0 [15] + connect \Y $xor$build/ls180/gateware/ls180.v:4699$850_Y + end + attribute \src "build/ls180/gateware/ls180.v:4699.215-4699.368" + cell $xor $xor$build/ls180/gateware/ls180.v:4699$851 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \libresocsim_sdcore_crc16_inserter_crc2_crcreg0 [11] + connect \B $xor$build/ls180/gateware/ls180.v:4699$850_Y + connect \Y $xor$build/ls180/gateware/ls180.v:4699$851_Y + end + attribute \src "build/ls180/gateware/ls180.v:4700.1039-4700.1137" + cell $xor $xor$build/ls180/gateware/ls180.v:4700$852 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \libresocsim_sdcore_crc16_inserter_crc2_val [0] + connect \B \libresocsim_sdcore_crc16_inserter_crc2_crcreg1 [15] + connect \Y $xor$build/ls180/gateware/ls180.v:4700$852_Y + end + attribute \src "build/ls180/gateware/ls180.v:4700.732-4700.830" + cell $xor $xor$build/ls180/gateware/ls180.v:4700$853 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \libresocsim_sdcore_crc16_inserter_crc2_val [0] + connect \B \libresocsim_sdcore_crc16_inserter_crc2_crcreg1 [15] + connect \Y $xor$build/ls180/gateware/ls180.v:4700$853_Y + end + attribute \src "build/ls180/gateware/ls180.v:4700.679-4700.831" + cell $xor $xor$build/ls180/gateware/ls180.v:4700$854 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \libresocsim_sdcore_crc16_inserter_crc2_crcreg1 [4] + connect \B $xor$build/ls180/gateware/ls180.v:4700$853_Y + connect \Y $xor$build/ls180/gateware/ls180.v:4700$854_Y + end + attribute \src "build/ls180/gateware/ls180.v:4700.269-4700.367" + cell $xor $xor$build/ls180/gateware/ls180.v:4700$855 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \libresocsim_sdcore_crc16_inserter_crc2_val [0] + connect \B \libresocsim_sdcore_crc16_inserter_crc2_crcreg1 [15] + connect \Y $xor$build/ls180/gateware/ls180.v:4700$855_Y + end + attribute \src "build/ls180/gateware/ls180.v:4700.215-4700.368" + cell $xor $xor$build/ls180/gateware/ls180.v:4700$856 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \libresocsim_sdcore_crc16_inserter_crc2_crcreg1 [11] + connect \B $xor$build/ls180/gateware/ls180.v:4700$855_Y + connect \Y $xor$build/ls180/gateware/ls180.v:4700$856_Y + end + attribute \src "build/ls180/gateware/ls180.v:4709.1039-4709.1137" + cell $xor $xor$build/ls180/gateware/ls180.v:4709$858 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \libresocsim_sdcore_crc16_inserter_crc3_val [1] + connect \B \libresocsim_sdcore_crc16_inserter_crc3_crcreg0 [15] + connect \Y $xor$build/ls180/gateware/ls180.v:4709$858_Y + end + attribute \src "build/ls180/gateware/ls180.v:4709.732-4709.830" + cell $xor $xor$build/ls180/gateware/ls180.v:4709$859 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \libresocsim_sdcore_crc16_inserter_crc3_val [1] + connect \B \libresocsim_sdcore_crc16_inserter_crc3_crcreg0 [15] + connect \Y $xor$build/ls180/gateware/ls180.v:4709$859_Y + end + attribute \src "build/ls180/gateware/ls180.v:4709.679-4709.831" + cell $xor $xor$build/ls180/gateware/ls180.v:4709$860 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \libresocsim_sdcore_crc16_inserter_crc3_crcreg0 [4] + connect \B $xor$build/ls180/gateware/ls180.v:4709$859_Y + connect \Y $xor$build/ls180/gateware/ls180.v:4709$860_Y + end + attribute \src "build/ls180/gateware/ls180.v:4709.269-4709.367" + cell $xor $xor$build/ls180/gateware/ls180.v:4709$861 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \libresocsim_sdcore_crc16_inserter_crc3_val [1] + connect \B \libresocsim_sdcore_crc16_inserter_crc3_crcreg0 [15] + connect \Y $xor$build/ls180/gateware/ls180.v:4709$861_Y + end + attribute \src "build/ls180/gateware/ls180.v:4709.215-4709.368" + cell $xor $xor$build/ls180/gateware/ls180.v:4709$862 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \libresocsim_sdcore_crc16_inserter_crc3_crcreg0 [11] + connect \B $xor$build/ls180/gateware/ls180.v:4709$861_Y + connect \Y $xor$build/ls180/gateware/ls180.v:4709$862_Y + end + attribute \src "build/ls180/gateware/ls180.v:4710.1039-4710.1137" + cell $xor $xor$build/ls180/gateware/ls180.v:4710$863 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \libresocsim_sdcore_crc16_inserter_crc3_val [0] + connect \B \libresocsim_sdcore_crc16_inserter_crc3_crcreg1 [15] + connect \Y $xor$build/ls180/gateware/ls180.v:4710$863_Y + end + attribute \src "build/ls180/gateware/ls180.v:4710.732-4710.830" + cell $xor $xor$build/ls180/gateware/ls180.v:4710$864 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \libresocsim_sdcore_crc16_inserter_crc3_val [0] + connect \B \libresocsim_sdcore_crc16_inserter_crc3_crcreg1 [15] + connect \Y $xor$build/ls180/gateware/ls180.v:4710$864_Y + end + attribute \src "build/ls180/gateware/ls180.v:4710.679-4710.831" + cell $xor $xor$build/ls180/gateware/ls180.v:4710$865 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \libresocsim_sdcore_crc16_inserter_crc3_crcreg1 [4] + connect \B $xor$build/ls180/gateware/ls180.v:4710$864_Y + connect \Y $xor$build/ls180/gateware/ls180.v:4710$865_Y + end + attribute \src "build/ls180/gateware/ls180.v:4710.269-4710.367" + cell $xor $xor$build/ls180/gateware/ls180.v:4710$866 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \libresocsim_sdcore_crc16_inserter_crc3_val [0] + connect \B \libresocsim_sdcore_crc16_inserter_crc3_crcreg1 [15] + connect \Y $xor$build/ls180/gateware/ls180.v:4710$866_Y + end + attribute \src "build/ls180/gateware/ls180.v:4710.215-4710.368" + cell $xor $xor$build/ls180/gateware/ls180.v:4710$867 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \libresocsim_sdcore_crc16_inserter_crc3_crcreg1 [11] + connect \B $xor$build/ls180/gateware/ls180.v:4710$866_Y + connect \Y $xor$build/ls180/gateware/ls180.v:4710$867_Y + end + attribute \src "build/ls180/gateware/ls180.v:4861.1019-4861.1115" + cell $xor $xor$build/ls180/gateware/ls180.v:4861$900 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \libresocsim_sdcore_crc16_checker_crc0_val [1] + connect \B \libresocsim_sdcore_crc16_checker_crc0_crcreg0 [15] + connect \Y $xor$build/ls180/gateware/ls180.v:4861$900_Y + end + attribute \src "build/ls180/gateware/ls180.v:4861.718-4861.814" + cell $xor $xor$build/ls180/gateware/ls180.v:4861$901 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \libresocsim_sdcore_crc16_checker_crc0_val [1] + connect \B \libresocsim_sdcore_crc16_checker_crc0_crcreg0 [15] + connect \Y $xor$build/ls180/gateware/ls180.v:4861$901_Y + end + attribute \src "build/ls180/gateware/ls180.v:4861.666-4861.815" + cell $xor $xor$build/ls180/gateware/ls180.v:4861$902 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \libresocsim_sdcore_crc16_checker_crc0_crcreg0 [4] + connect \B $xor$build/ls180/gateware/ls180.v:4861$901_Y + connect \Y $xor$build/ls180/gateware/ls180.v:4861$902_Y + end + attribute \src "build/ls180/gateware/ls180.v:4861.264-4861.360" + cell $xor $xor$build/ls180/gateware/ls180.v:4861$903 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \libresocsim_sdcore_crc16_checker_crc0_val [1] + connect \B \libresocsim_sdcore_crc16_checker_crc0_crcreg0 [15] + connect \Y $xor$build/ls180/gateware/ls180.v:4861$903_Y + end + attribute \src "build/ls180/gateware/ls180.v:4861.211-4861.361" + cell $xor $xor$build/ls180/gateware/ls180.v:4861$904 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \libresocsim_sdcore_crc16_checker_crc0_crcreg0 [11] + connect \B $xor$build/ls180/gateware/ls180.v:4861$903_Y + connect \Y $xor$build/ls180/gateware/ls180.v:4861$904_Y + end + attribute \src "build/ls180/gateware/ls180.v:4862.1019-4862.1115" + cell $xor $xor$build/ls180/gateware/ls180.v:4862$905 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \libresocsim_sdcore_crc16_checker_crc0_val [0] + connect \B \libresocsim_sdcore_crc16_checker_crc0_crcreg1 [15] + connect \Y $xor$build/ls180/gateware/ls180.v:4862$905_Y + end + attribute \src "build/ls180/gateware/ls180.v:4862.718-4862.814" + cell $xor $xor$build/ls180/gateware/ls180.v:4862$906 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \libresocsim_sdcore_crc16_checker_crc0_val [0] + connect \B \libresocsim_sdcore_crc16_checker_crc0_crcreg1 [15] + connect \Y $xor$build/ls180/gateware/ls180.v:4862$906_Y + end + attribute \src "build/ls180/gateware/ls180.v:4862.666-4862.815" + cell $xor $xor$build/ls180/gateware/ls180.v:4862$907 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \libresocsim_sdcore_crc16_checker_crc0_crcreg1 [4] + connect \B $xor$build/ls180/gateware/ls180.v:4862$906_Y + connect \Y $xor$build/ls180/gateware/ls180.v:4862$907_Y + end + attribute \src "build/ls180/gateware/ls180.v:4862.264-4862.360" + cell $xor $xor$build/ls180/gateware/ls180.v:4862$908 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \libresocsim_sdcore_crc16_checker_crc0_val [0] + connect \B \libresocsim_sdcore_crc16_checker_crc0_crcreg1 [15] + connect \Y $xor$build/ls180/gateware/ls180.v:4862$908_Y + end + attribute \src "build/ls180/gateware/ls180.v:4862.211-4862.361" + cell $xor $xor$build/ls180/gateware/ls180.v:4862$909 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \libresocsim_sdcore_crc16_checker_crc0_crcreg1 [11] + connect \B $xor$build/ls180/gateware/ls180.v:4862$908_Y + connect \Y $xor$build/ls180/gateware/ls180.v:4862$909_Y + end + attribute \src "build/ls180/gateware/ls180.v:4871.1019-4871.1115" + cell $xor $xor$build/ls180/gateware/ls180.v:4871$911 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \libresocsim_sdcore_crc16_checker_crc1_val [1] + connect \B \libresocsim_sdcore_crc16_checker_crc1_crcreg0 [15] + connect \Y $xor$build/ls180/gateware/ls180.v:4871$911_Y + end + attribute \src "build/ls180/gateware/ls180.v:4871.718-4871.814" + cell $xor $xor$build/ls180/gateware/ls180.v:4871$912 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \libresocsim_sdcore_crc16_checker_crc1_val [1] + connect \B \libresocsim_sdcore_crc16_checker_crc1_crcreg0 [15] + connect \Y $xor$build/ls180/gateware/ls180.v:4871$912_Y + end + attribute \src "build/ls180/gateware/ls180.v:4871.666-4871.815" + cell $xor $xor$build/ls180/gateware/ls180.v:4871$913 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \libresocsim_sdcore_crc16_checker_crc1_crcreg0 [4] + connect \B $xor$build/ls180/gateware/ls180.v:4871$912_Y + connect \Y $xor$build/ls180/gateware/ls180.v:4871$913_Y + end + attribute \src "build/ls180/gateware/ls180.v:4871.264-4871.360" + cell $xor $xor$build/ls180/gateware/ls180.v:4871$914 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \libresocsim_sdcore_crc16_checker_crc1_val [1] + connect \B \libresocsim_sdcore_crc16_checker_crc1_crcreg0 [15] + connect \Y $xor$build/ls180/gateware/ls180.v:4871$914_Y + end + attribute \src "build/ls180/gateware/ls180.v:4871.211-4871.361" + cell $xor $xor$build/ls180/gateware/ls180.v:4871$915 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \libresocsim_sdcore_crc16_checker_crc1_crcreg0 [11] + connect \B $xor$build/ls180/gateware/ls180.v:4871$914_Y + connect \Y $xor$build/ls180/gateware/ls180.v:4871$915_Y + end + attribute \src "build/ls180/gateware/ls180.v:4872.1019-4872.1115" + cell $xor $xor$build/ls180/gateware/ls180.v:4872$916 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \libresocsim_sdcore_crc16_checker_crc1_val [0] + connect \B \libresocsim_sdcore_crc16_checker_crc1_crcreg1 [15] + connect \Y $xor$build/ls180/gateware/ls180.v:4872$916_Y + end + attribute \src "build/ls180/gateware/ls180.v:4872.718-4872.814" + cell $xor $xor$build/ls180/gateware/ls180.v:4872$917 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \libresocsim_sdcore_crc16_checker_crc1_val [0] + connect \B \libresocsim_sdcore_crc16_checker_crc1_crcreg1 [15] + connect \Y $xor$build/ls180/gateware/ls180.v:4872$917_Y + end + attribute \src "build/ls180/gateware/ls180.v:4872.666-4872.815" + cell $xor $xor$build/ls180/gateware/ls180.v:4872$918 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \libresocsim_sdcore_crc16_checker_crc1_crcreg1 [4] + connect \B $xor$build/ls180/gateware/ls180.v:4872$917_Y + connect \Y $xor$build/ls180/gateware/ls180.v:4872$918_Y + end + attribute \src "build/ls180/gateware/ls180.v:4872.264-4872.360" + cell $xor $xor$build/ls180/gateware/ls180.v:4872$919 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \libresocsim_sdcore_crc16_checker_crc1_val [0] + connect \B \libresocsim_sdcore_crc16_checker_crc1_crcreg1 [15] + connect \Y $xor$build/ls180/gateware/ls180.v:4872$919_Y + end + attribute \src "build/ls180/gateware/ls180.v:4872.211-4872.361" + cell $xor $xor$build/ls180/gateware/ls180.v:4872$920 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \libresocsim_sdcore_crc16_checker_crc1_crcreg1 [11] + connect \B $xor$build/ls180/gateware/ls180.v:4872$919_Y + connect \Y $xor$build/ls180/gateware/ls180.v:4872$920_Y + end + attribute \src "build/ls180/gateware/ls180.v:4881.1019-4881.1115" + cell $xor $xor$build/ls180/gateware/ls180.v:4881$922 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \libresocsim_sdcore_crc16_checker_crc2_val [1] + connect \B \libresocsim_sdcore_crc16_checker_crc2_crcreg0 [15] + connect \Y $xor$build/ls180/gateware/ls180.v:4881$922_Y + end + attribute \src "build/ls180/gateware/ls180.v:4881.718-4881.814" + cell $xor $xor$build/ls180/gateware/ls180.v:4881$923 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \libresocsim_sdcore_crc16_checker_crc2_val [1] + connect \B \libresocsim_sdcore_crc16_checker_crc2_crcreg0 [15] + connect \Y $xor$build/ls180/gateware/ls180.v:4881$923_Y + end + attribute \src "build/ls180/gateware/ls180.v:4881.666-4881.815" + cell $xor $xor$build/ls180/gateware/ls180.v:4881$924 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \libresocsim_sdcore_crc16_checker_crc2_crcreg0 [4] + connect \B $xor$build/ls180/gateware/ls180.v:4881$923_Y + connect \Y $xor$build/ls180/gateware/ls180.v:4881$924_Y + end + attribute \src "build/ls180/gateware/ls180.v:4881.264-4881.360" + cell $xor $xor$build/ls180/gateware/ls180.v:4881$925 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \libresocsim_sdcore_crc16_checker_crc2_val [1] + connect \B \libresocsim_sdcore_crc16_checker_crc2_crcreg0 [15] + connect \Y $xor$build/ls180/gateware/ls180.v:4881$925_Y + end + attribute \src "build/ls180/gateware/ls180.v:4881.211-4881.361" + cell $xor $xor$build/ls180/gateware/ls180.v:4881$926 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \libresocsim_sdcore_crc16_checker_crc2_crcreg0 [11] + connect \B $xor$build/ls180/gateware/ls180.v:4881$925_Y + connect \Y $xor$build/ls180/gateware/ls180.v:4881$926_Y + end + attribute \src "build/ls180/gateware/ls180.v:4882.1019-4882.1115" + cell $xor $xor$build/ls180/gateware/ls180.v:4882$927 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \libresocsim_sdcore_crc16_checker_crc2_val [0] + connect \B \libresocsim_sdcore_crc16_checker_crc2_crcreg1 [15] + connect \Y $xor$build/ls180/gateware/ls180.v:4882$927_Y + end + attribute \src "build/ls180/gateware/ls180.v:4882.718-4882.814" + cell $xor $xor$build/ls180/gateware/ls180.v:4882$928 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \libresocsim_sdcore_crc16_checker_crc2_val [0] + connect \B \libresocsim_sdcore_crc16_checker_crc2_crcreg1 [15] + connect \Y $xor$build/ls180/gateware/ls180.v:4882$928_Y + end + attribute \src "build/ls180/gateware/ls180.v:4882.666-4882.815" + cell $xor $xor$build/ls180/gateware/ls180.v:4882$929 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \libresocsim_sdcore_crc16_checker_crc2_crcreg1 [4] + connect \B $xor$build/ls180/gateware/ls180.v:4882$928_Y + connect \Y $xor$build/ls180/gateware/ls180.v:4882$929_Y + end + attribute \src "build/ls180/gateware/ls180.v:4882.264-4882.360" + cell $xor $xor$build/ls180/gateware/ls180.v:4882$930 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \libresocsim_sdcore_crc16_checker_crc2_val [0] + connect \B \libresocsim_sdcore_crc16_checker_crc2_crcreg1 [15] + connect \Y $xor$build/ls180/gateware/ls180.v:4882$930_Y + end + attribute \src "build/ls180/gateware/ls180.v:4882.211-4882.361" + cell $xor $xor$build/ls180/gateware/ls180.v:4882$931 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \libresocsim_sdcore_crc16_checker_crc2_crcreg1 [11] + connect \B $xor$build/ls180/gateware/ls180.v:4882$930_Y + connect \Y $xor$build/ls180/gateware/ls180.v:4882$931_Y + end + attribute \src "build/ls180/gateware/ls180.v:4891.1019-4891.1115" + cell $xor $xor$build/ls180/gateware/ls180.v:4891$933 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \libresocsim_sdcore_crc16_checker_crc3_val [1] + connect \B \libresocsim_sdcore_crc16_checker_crc3_crcreg0 [15] + connect \Y $xor$build/ls180/gateware/ls180.v:4891$933_Y + end + attribute \src "build/ls180/gateware/ls180.v:4891.718-4891.814" + cell $xor $xor$build/ls180/gateware/ls180.v:4891$934 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \libresocsim_sdcore_crc16_checker_crc3_val [1] + connect \B \libresocsim_sdcore_crc16_checker_crc3_crcreg0 [15] + connect \Y $xor$build/ls180/gateware/ls180.v:4891$934_Y + end + attribute \src "build/ls180/gateware/ls180.v:4891.666-4891.815" + cell $xor $xor$build/ls180/gateware/ls180.v:4891$935 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \libresocsim_sdcore_crc16_checker_crc3_crcreg0 [4] + connect \B $xor$build/ls180/gateware/ls180.v:4891$934_Y + connect \Y $xor$build/ls180/gateware/ls180.v:4891$935_Y + end + attribute \src "build/ls180/gateware/ls180.v:4891.264-4891.360" + cell $xor $xor$build/ls180/gateware/ls180.v:4891$936 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \libresocsim_sdcore_crc16_checker_crc3_val [1] + connect \B \libresocsim_sdcore_crc16_checker_crc3_crcreg0 [15] + connect \Y $xor$build/ls180/gateware/ls180.v:4891$936_Y + end + attribute \src "build/ls180/gateware/ls180.v:4891.211-4891.361" + cell $xor $xor$build/ls180/gateware/ls180.v:4891$937 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \libresocsim_sdcore_crc16_checker_crc3_crcreg0 [11] + connect \B $xor$build/ls180/gateware/ls180.v:4891$936_Y + connect \Y $xor$build/ls180/gateware/ls180.v:4891$937_Y + end + attribute \src "build/ls180/gateware/ls180.v:4892.1019-4892.1115" + cell $xor $xor$build/ls180/gateware/ls180.v:4892$938 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \libresocsim_sdcore_crc16_checker_crc3_val [0] + connect \B \libresocsim_sdcore_crc16_checker_crc3_crcreg1 [15] + connect \Y $xor$build/ls180/gateware/ls180.v:4892$938_Y + end + attribute \src "build/ls180/gateware/ls180.v:4892.718-4892.814" + cell $xor $xor$build/ls180/gateware/ls180.v:4892$939 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \libresocsim_sdcore_crc16_checker_crc3_val [0] + connect \B \libresocsim_sdcore_crc16_checker_crc3_crcreg1 [15] + connect \Y $xor$build/ls180/gateware/ls180.v:4892$939_Y + end + attribute \src "build/ls180/gateware/ls180.v:4892.666-4892.815" + cell $xor $xor$build/ls180/gateware/ls180.v:4892$940 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \libresocsim_sdcore_crc16_checker_crc3_crcreg1 [4] + connect \B $xor$build/ls180/gateware/ls180.v:4892$939_Y + connect \Y $xor$build/ls180/gateware/ls180.v:4892$940_Y + end + attribute \src "build/ls180/gateware/ls180.v:4892.264-4892.360" + cell $xor $xor$build/ls180/gateware/ls180.v:4892$941 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \libresocsim_sdcore_crc16_checker_crc3_val [0] + connect \B \libresocsim_sdcore_crc16_checker_crc3_crcreg1 [15] + connect \Y $xor$build/ls180/gateware/ls180.v:4892$941_Y + end + attribute \src "build/ls180/gateware/ls180.v:4892.211-4892.361" + cell $xor $xor$build/ls180/gateware/ls180.v:4892$942 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \libresocsim_sdcore_crc16_checker_crc3_crcreg1 [11] + connect \B $xor$build/ls180/gateware/ls180.v:4892$941_Y + connect \Y $xor$build/ls180/gateware/ls180.v:4892$942_Y + end + attribute \module_not_derived 1 + attribute \src "build/ls180/gateware/ls180.v:9503.13-9562.2" + cell \test_issuer \test_issuer + connect \busy_o \main_libresocsim_libresoc0 + connect \clk \sys_clk_1 + connect \core_bigendian_i 1'0 + connect \dbus__ack \main_libresocsim_libresoc_dbus_ack + connect \dbus__adr \main_libresocsim_libresoc_dbus_adr + connect \dbus__bte \main_libresocsim_libresoc_dbus_bte + connect \dbus__cti \main_libresocsim_libresoc_dbus_cti + connect \dbus__cyc \main_libresocsim_libresoc_dbus_cyc + connect \dbus__dat_r \main_libresocsim_libresoc_dbus_dat_r + connect \dbus__dat_w \main_libresocsim_libresoc_dbus_dat_w + connect \dbus__err \main_libresocsim_libresoc_dbus_err + connect \dbus__sel \main_libresocsim_libresoc_dbus_sel + connect \dbus__stb \main_libresocsim_libresoc_dbus_stb + connect \dbus__we \main_libresocsim_libresoc_dbus_we + connect \dmi_ack_o \main_libresocsim_libresoc_dmi_ack + connect \dmi_addr_i \main_libresocsim_libresoc_dmi_addr + connect \dmi_din \main_libresocsim_libresoc_dmi_din + connect \dmi_dout \main_libresocsim_libresoc_dmi_dout + connect \dmi_req_i \main_libresocsim_libresoc_dmi_req + connect \dmi_we_i \main_libresocsim_libresoc_dmi_wr + connect \ibus__ack \main_libresocsim_libresoc_ibus_ack + connect \ibus__adr \main_libresocsim_libresoc_ibus_adr + connect \ibus__bte \main_libresocsim_libresoc_ibus_bte + connect \ibus__cti \main_libresocsim_libresoc_ibus_cti + connect \ibus__cyc \main_libresocsim_libresoc_ibus_cyc + connect \ibus__dat_r \main_libresocsim_libresoc_ibus_dat_r + connect \ibus__dat_w \main_libresocsim_libresoc_ibus_dat_w + connect \ibus__err \main_libresocsim_libresoc_ibus_err + connect \ibus__sel \main_libresocsim_libresoc_ibus_sel + connect \ibus__stb \main_libresocsim_libresoc_ibus_stb + connect \ibus__we \main_libresocsim_libresoc_ibus_we + connect \icp_wb__ack \main_libresocsim_libresoc_xics_icp_ack + connect \icp_wb__adr \main_libresocsim_libresoc_xics_icp_adr + connect \icp_wb__bte \main_libresocsim_libresoc_xics_icp_bte + connect \icp_wb__cti \main_libresocsim_libresoc_xics_icp_cti + connect \icp_wb__cyc \main_libresocsim_libresoc_xics_icp_cyc + connect \icp_wb__dat_r \main_libresocsim_libresoc_xics_icp_dat_r + connect \icp_wb__dat_w \main_libresocsim_libresoc_xics_icp_dat_w + connect \icp_wb__err \main_libresocsim_libresoc_xics_icp_err + connect \icp_wb__sel \main_libresocsim_libresoc_xics_icp_sel + connect \icp_wb__stb \main_libresocsim_libresoc_xics_icp_stb + connect \icp_wb__we \main_libresocsim_libresoc_xics_icp_we + connect \ics_wb__ack \main_libresocsim_libresoc_xics_ics_ack + connect \ics_wb__adr \main_libresocsim_libresoc_xics_ics_adr + connect \ics_wb__bte \main_libresocsim_libresoc_xics_ics_bte + connect \ics_wb__cti \main_libresocsim_libresoc_xics_ics_cti + connect \ics_wb__cyc \main_libresocsim_libresoc_xics_ics_cyc + connect \ics_wb__dat_r \main_libresocsim_libresoc_xics_ics_dat_r + connect \ics_wb__dat_w \main_libresocsim_libresoc_xics_ics_dat_w + connect \ics_wb__err \main_libresocsim_libresoc_xics_ics_err + connect \ics_wb__sel \main_libresocsim_libresoc_xics_ics_sel + connect \ics_wb__stb \main_libresocsim_libresoc_xics_ics_stb + connect \ics_wb__we \main_libresocsim_libresoc_xics_ics_we + connect \int_level_i \main_libresocsim_libresoc_interrupt + connect \memerr_o \main_libresocsim_libresoc1 + connect \pc_i 1'0 + connect \pc_i_ok 1'0 + connect \rst $or$build/ls180/gateware/ls180.v:9525$2529_Y + end + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + process $proc$build/ls180/gateware/ls180.v:0$3484 + sync always + sync init + end + attribute \src "build/ls180/gateware/ls180.v:100.5-100.63" + process $proc$build/ls180/gateware/ls180.v:100$2586 + assign { } { } + assign $1\main_libresocsim_interface0_converted_interface_cyc[0:0] 1'0 + sync always + sync init + update \main_libresocsim_interface0_converted_interface_cyc $1\main_libresocsim_interface0_converted_interface_cyc[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:1000.5-1000.38" + process $proc$build/ls180/gateware/ls180.v:1000$2976 + assign { } { } + assign $1\libresocsim_cmdr_sink_last[0:0] 1'0 + sync always + sync init + update \libresocsim_cmdr_sink_last $1\libresocsim_cmdr_sink_last[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:1001.11-1001.54" + process $proc$build/ls180/gateware/ls180.v:1001$2977 + assign { } { } + assign $1\libresocsim_cmdr_sink_payload_length[7:0] 8'00000000 + sync always + sync init + update \libresocsim_cmdr_sink_payload_length $1\libresocsim_cmdr_sink_payload_length[7:0] + end + attribute \src "build/ls180/gateware/ls180.v:1002.5-1002.41" + process $proc$build/ls180/gateware/ls180.v:1002$2978 + assign { } { } + assign $1\libresocsim_cmdr_source_valid[0:0] 1'0 + sync always + sync init + update \libresocsim_cmdr_source_valid $1\libresocsim_cmdr_source_valid[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:1003.5-1003.41" + process $proc$build/ls180/gateware/ls180.v:1003$2979 + assign { } { } + assign $1\libresocsim_cmdr_source_ready[0:0] 1'0 + sync always + sync init + update \libresocsim_cmdr_source_ready $1\libresocsim_cmdr_source_ready[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:1004.5-1004.40" + process $proc$build/ls180/gateware/ls180.v:1004$2980 + assign { } { } + assign $1\libresocsim_cmdr_source_last[0:0] 1'0 + sync always + sync init + update \libresocsim_cmdr_source_last $1\libresocsim_cmdr_source_last[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:1005.11-1005.54" + process $proc$build/ls180/gateware/ls180.v:1005$2981 + assign { } { } + assign $1\libresocsim_cmdr_source_payload_data[7:0] 8'00000000 + sync always + sync init + update \libresocsim_cmdr_source_payload_data $1\libresocsim_cmdr_source_payload_data[7:0] + end + attribute \src "build/ls180/gateware/ls180.v:1006.11-1006.56" + process $proc$build/ls180/gateware/ls180.v:1006$2982 + assign { } { } + assign $1\libresocsim_cmdr_source_payload_status[2:0] 3'000 + sync always + sync init + update \libresocsim_cmdr_source_payload_status $1\libresocsim_cmdr_source_payload_status[2:0] + end + attribute \src "build/ls180/gateware/ls180.v:1007.12-1007.49" + process $proc$build/ls180/gateware/ls180.v:1007$2983 + assign { } { } + assign $1\libresocsim_cmdr_timeout[31:0] 500000 + sync always + sync init + update \libresocsim_cmdr_timeout $1\libresocsim_cmdr_timeout[31:0] + end + attribute \src "build/ls180/gateware/ls180.v:1008.11-1008.40" + process $proc$build/ls180/gateware/ls180.v:1008$2984 + assign { } { } + assign $1\libresocsim_cmdr_count[7:0] 8'00000000 + sync always + sync init + update \libresocsim_cmdr_count $1\libresocsim_cmdr_count[7:0] + end + attribute \src "build/ls180/gateware/ls180.v:101.5-101.63" + process $proc$build/ls180/gateware/ls180.v:101$2587 + assign { } { } + assign $1\main_libresocsim_interface0_converted_interface_stb[0:0] 1'0 + sync always + sync init + update \main_libresocsim_interface0_converted_interface_stb $1\main_libresocsim_interface0_converted_interface_stb[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:1010.5-1010.47" + process $proc$build/ls180/gateware/ls180.v:1010$2985 + assign { } { } + assign $0\libresocsim_cmdr_cmdr_pads_in_ready[0:0] 1'0 + sync always + update \libresocsim_cmdr_cmdr_pads_in_ready $0\libresocsim_cmdr_cmdr_pads_in_ready[0:0] + sync init + end + attribute \src "build/ls180/gateware/ls180.v:1021.5-1021.54" + process $proc$build/ls180/gateware/ls180.v:1021$2986 + assign { } { } + assign $1\libresocsim_cmdr_cmdr_source_source_ready0[0:0] 1'0 + sync always + sync init + update \libresocsim_cmdr_cmdr_source_source_ready0 $1\libresocsim_cmdr_cmdr_source_source_ready0[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:1026.5-1026.37" + process $proc$build/ls180/gateware/ls180.v:1026$2987 + assign { } { } + assign $1\libresocsim_cmdr_cmdr_run[0:0] 1'0 + sync always + sync init + update \libresocsim_cmdr_cmdr_run $1\libresocsim_cmdr_cmdr_run[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:1029.5-1029.54" + process $proc$build/ls180/gateware/ls180.v:1029$2988 + assign { } { } + assign $0\libresocsim_cmdr_cmdr_converter_sink_first[0:0] 1'0 + sync always + update \libresocsim_cmdr_cmdr_converter_sink_first $0\libresocsim_cmdr_cmdr_converter_sink_first[0:0] + sync init + end + attribute \src "build/ls180/gateware/ls180.v:103.5-103.62" + process $proc$build/ls180/gateware/ls180.v:103$2588 + assign { } { } + assign $1\main_libresocsim_interface0_converted_interface_we[0:0] 1'0 + sync always + sync init + update \main_libresocsim_interface0_converted_interface_we $1\main_libresocsim_interface0_converted_interface_we[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:1030.5-1030.53" + process $proc$build/ls180/gateware/ls180.v:1030$2989 + assign { } { } + assign $0\libresocsim_cmdr_cmdr_converter_sink_last[0:0] 1'0 + sync always + update \libresocsim_cmdr_cmdr_converter_sink_last $0\libresocsim_cmdr_cmdr_converter_sink_last[0:0] + sync init + end + attribute \src "build/ls180/gateware/ls180.v:1034.5-1034.56" + process $proc$build/ls180/gateware/ls180.v:1034$2990 + assign { } { } + assign $1\libresocsim_cmdr_cmdr_converter_source_first[0:0] 1'0 + sync always + sync init + update \libresocsim_cmdr_cmdr_converter_source_first $1\libresocsim_cmdr_cmdr_converter_source_first[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:1035.5-1035.55" + process $proc$build/ls180/gateware/ls180.v:1035$2991 + assign { } { } + assign $1\libresocsim_cmdr_cmdr_converter_source_last[0:0] 1'0 + sync always + sync init + update \libresocsim_cmdr_cmdr_converter_source_last $1\libresocsim_cmdr_cmdr_converter_source_last[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:1036.11-1036.69" + process $proc$build/ls180/gateware/ls180.v:1036$2992 + assign { } { } + assign $1\libresocsim_cmdr_cmdr_converter_source_payload_data[7:0] 8'00000000 + sync always + sync init + update \libresocsim_cmdr_cmdr_converter_source_payload_data $1\libresocsim_cmdr_cmdr_converter_source_payload_data[7:0] + end + attribute \src "build/ls180/gateware/ls180.v:1037.11-1037.82" + process $proc$build/ls180/gateware/ls180.v:1037$2993 + assign { } { } + assign $1\libresocsim_cmdr_cmdr_converter_source_payload_valid_token_count[3:0] 4'0000 + sync always + sync init + update \libresocsim_cmdr_cmdr_converter_source_payload_valid_token_count $1\libresocsim_cmdr_cmdr_converter_source_payload_valid_token_count[3:0] + end + attribute \src "build/ls180/gateware/ls180.v:1038.11-1038.55" + process $proc$build/ls180/gateware/ls180.v:1038$2994 + assign { } { } + assign $1\libresocsim_cmdr_cmdr_converter_demux[2:0] 3'000 + sync always + sync init + update \libresocsim_cmdr_cmdr_converter_demux $1\libresocsim_cmdr_cmdr_converter_demux[2:0] + end + attribute \src "build/ls180/gateware/ls180.v:104.11-104.69" + process $proc$build/ls180/gateware/ls180.v:104$2589 + assign { } { } + assign $0\main_libresocsim_interface0_converted_interface_cti[2:0] 3'000 + sync always + update \main_libresocsim_interface0_converted_interface_cti $0\main_libresocsim_interface0_converted_interface_cti[2:0] + sync init + end + attribute \src "build/ls180/gateware/ls180.v:1040.5-1040.54" + process $proc$build/ls180/gateware/ls180.v:1040$2995 + assign { } { } + assign $1\libresocsim_cmdr_cmdr_converter_strobe_all[0:0] 1'0 + sync always + sync init + update \libresocsim_cmdr_cmdr_converter_strobe_all $1\libresocsim_cmdr_cmdr_converter_strobe_all[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:105.11-105.69" + process $proc$build/ls180/gateware/ls180.v:105$2590 + assign { } { } + assign $0\main_libresocsim_interface0_converted_interface_bte[1:0] 2'00 + sync always + update \main_libresocsim_interface0_converted_interface_bte $0\main_libresocsim_interface0_converted_interface_bte[1:0] + sync init + end + attribute \src "build/ls180/gateware/ls180.v:1051.5-1051.50" + process $proc$build/ls180/gateware/ls180.v:1051$2996 + assign { } { } + assign $1\libresocsim_cmdr_cmdr_buf_source_valid[0:0] 1'0 + sync always + sync init + update \libresocsim_cmdr_cmdr_buf_source_valid $1\libresocsim_cmdr_cmdr_buf_source_valid[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:1053.5-1053.50" + process $proc$build/ls180/gateware/ls180.v:1053$2997 + assign { } { } + assign $1\libresocsim_cmdr_cmdr_buf_source_first[0:0] 1'0 + sync always + sync init + update \libresocsim_cmdr_cmdr_buf_source_first $1\libresocsim_cmdr_cmdr_buf_source_first[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:1054.5-1054.49" + process $proc$build/ls180/gateware/ls180.v:1054$2998 + assign { } { } + assign $1\libresocsim_cmdr_cmdr_buf_source_last[0:0] 1'0 + sync always + sync init + update \libresocsim_cmdr_cmdr_buf_source_last $1\libresocsim_cmdr_cmdr_buf_source_last[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:1055.11-1055.63" + process $proc$build/ls180/gateware/ls180.v:1055$2999 + assign { } { } + assign $1\libresocsim_cmdr_cmdr_buf_source_payload_data[7:0] 8'00000000 + sync always + sync init + update \libresocsim_cmdr_cmdr_buf_source_payload_data $1\libresocsim_cmdr_cmdr_buf_source_payload_data[7:0] + end + attribute \src "build/ls180/gateware/ls180.v:1056.5-1056.39" + process $proc$build/ls180/gateware/ls180.v:1056$3000 + assign { } { } + assign $1\libresocsim_cmdr_cmdr_reset[0:0] 1'0 + sync always + sync init + update \libresocsim_cmdr_cmdr_reset $1\libresocsim_cmdr_cmdr_reset[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:1061.5-1061.50" + process $proc$build/ls180/gateware/ls180.v:1061$3001 + assign { } { } + assign $1\libresocsim_dataw_pads_out_payload_clk[0:0] 1'0 + sync always + sync init + update \libresocsim_dataw_pads_out_payload_clk $1\libresocsim_dataw_pads_out_payload_clk[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:1062.5-1062.52" + process $proc$build/ls180/gateware/ls180.v:1062$3002 + assign { } { } + assign $0\libresocsim_dataw_pads_out_payload_cmd_o[0:0] 1'0 + sync always + update \libresocsim_dataw_pads_out_payload_cmd_o $0\libresocsim_dataw_pads_out_payload_cmd_o[0:0] + sync init + end + attribute \src "build/ls180/gateware/ls180.v:1063.5-1063.53" + process $proc$build/ls180/gateware/ls180.v:1063$3003 + assign { } { } + assign $0\libresocsim_dataw_pads_out_payload_cmd_oe[0:0] 1'0 + sync always + update \libresocsim_dataw_pads_out_payload_cmd_oe $0\libresocsim_dataw_pads_out_payload_cmd_oe[0:0] + sync init + end + attribute \src "build/ls180/gateware/ls180.v:1064.11-1064.59" + process $proc$build/ls180/gateware/ls180.v:1064$3004 + assign { } { } + assign $1\libresocsim_dataw_pads_out_payload_data_o[3:0] 4'0000 + sync always + sync init + update \libresocsim_dataw_pads_out_payload_data_o $1\libresocsim_dataw_pads_out_payload_data_o[3:0] + end + attribute \src "build/ls180/gateware/ls180.v:1065.5-1065.54" + process $proc$build/ls180/gateware/ls180.v:1065$3005 + assign { } { } + assign $1\libresocsim_dataw_pads_out_payload_data_oe[0:0] 1'0 + sync always + sync init + update \libresocsim_dataw_pads_out_payload_data_oe $1\libresocsim_dataw_pads_out_payload_data_oe[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:1066.5-1066.40" + process $proc$build/ls180/gateware/ls180.v:1066$3006 + assign { } { } + assign $1\libresocsim_dataw_sink_valid[0:0] 1'0 + sync always + sync init + update \libresocsim_dataw_sink_valid $1\libresocsim_dataw_sink_valid[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:1067.5-1067.40" + process $proc$build/ls180/gateware/ls180.v:1067$3007 + assign { } { } + assign $1\libresocsim_dataw_sink_ready[0:0] 1'0 + sync always + sync init + update \libresocsim_dataw_sink_ready $1\libresocsim_dataw_sink_ready[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:1068.5-1068.40" + process $proc$build/ls180/gateware/ls180.v:1068$3008 + assign { } { } + assign $1\libresocsim_dataw_sink_first[0:0] 1'0 + sync always + sync init + update \libresocsim_dataw_sink_first $1\libresocsim_dataw_sink_first[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:1069.5-1069.39" + process $proc$build/ls180/gateware/ls180.v:1069$3009 + assign { } { } + assign $1\libresocsim_dataw_sink_last[0:0] 1'0 + sync always + sync init + update \libresocsim_dataw_sink_last $1\libresocsim_dataw_sink_last[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:107.5-107.44" + process $proc$build/ls180/gateware/ls180.v:107$2591 + assign { } { } + assign $1\main_libresocsim_converter0_skip[0:0] 1'0 + sync always + sync init + update \main_libresocsim_converter0_skip $1\main_libresocsim_converter0_skip[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:1070.11-1070.53" + process $proc$build/ls180/gateware/ls180.v:1070$3010 + assign { } { } + assign $1\libresocsim_dataw_sink_payload_data[7:0] 8'00000000 + sync always + sync init + update \libresocsim_dataw_sink_payload_data $1\libresocsim_dataw_sink_payload_data[7:0] + end + attribute \src "build/ls180/gateware/ls180.v:1071.5-1071.34" + process $proc$build/ls180/gateware/ls180.v:1071$3011 + assign { } { } + assign $1\libresocsim_dataw_stop[0:0] 1'0 + sync always + sync init + update \libresocsim_dataw_stop $1\libresocsim_dataw_stop[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:1072.11-1072.41" + process $proc$build/ls180/gateware/ls180.v:1072$3012 + assign { } { } + assign $1\libresocsim_dataw_count[7:0] 8'00000000 + sync always + sync init + update \libresocsim_dataw_count $1\libresocsim_dataw_count[7:0] + end + attribute \src "build/ls180/gateware/ls180.v:1073.5-1073.51" + process $proc$build/ls180/gateware/ls180.v:1073$3013 + assign { } { } + assign $0\libresocsim_dataw_pads_in_pads_in_valid[0:0] 1'0 + sync always + update \libresocsim_dataw_pads_in_pads_in_valid $0\libresocsim_dataw_pads_in_pads_in_valid[0:0] + sync init + end + attribute \src "build/ls180/gateware/ls180.v:1075.5-1075.51" + process $proc$build/ls180/gateware/ls180.v:1075$3014 + assign { } { } + assign $0\libresocsim_dataw_pads_in_pads_in_first[0:0] 1'0 + sync always + update \libresocsim_dataw_pads_in_pads_in_first $0\libresocsim_dataw_pads_in_pads_in_first[0:0] + sync init + end + attribute \src "build/ls180/gateware/ls180.v:1076.5-1076.50" + process $proc$build/ls180/gateware/ls180.v:1076$3015 + assign { } { } + assign $0\libresocsim_dataw_pads_in_pads_in_last[0:0] 1'0 + sync always + update \libresocsim_dataw_pads_in_pads_in_last $0\libresocsim_dataw_pads_in_pads_in_last[0:0] + sync init + end + attribute \src "build/ls180/gateware/ls180.v:1077.5-1077.57" + process $proc$build/ls180/gateware/ls180.v:1077$3016 + assign { } { } + assign $0\libresocsim_dataw_pads_in_pads_in_payload_clk[0:0] 1'0 + sync always + update \libresocsim_dataw_pads_in_pads_in_payload_clk $0\libresocsim_dataw_pads_in_pads_in_payload_clk[0:0] + sync init + end + attribute \src "build/ls180/gateware/ls180.v:1078.5-1078.59" + process $proc$build/ls180/gateware/ls180.v:1078$3017 + assign { } { } + assign $0\libresocsim_dataw_pads_in_pads_in_payload_cmd_i[0:0] 1'0 + sync always + update \libresocsim_dataw_pads_in_pads_in_payload_cmd_i $0\libresocsim_dataw_pads_in_pads_in_payload_cmd_i[0:0] + sync init + end + attribute \src "build/ls180/gateware/ls180.v:1079.5-1079.59" + process $proc$build/ls180/gateware/ls180.v:1079$3018 + assign { } { } + assign $0\libresocsim_dataw_pads_in_pads_in_payload_cmd_o[0:0] 1'0 + sync always + update \libresocsim_dataw_pads_in_pads_in_payload_cmd_o $0\libresocsim_dataw_pads_in_pads_in_payload_cmd_o[0:0] + sync init + end + attribute \src "build/ls180/gateware/ls180.v:108.5-108.47" + process $proc$build/ls180/gateware/ls180.v:108$2592 + assign { } { } + assign $1\main_libresocsim_converter0_counter[0:0] 1'0 + sync always + sync init + update \main_libresocsim_converter0_counter $1\main_libresocsim_converter0_counter[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:1080.5-1080.60" + process $proc$build/ls180/gateware/ls180.v:1080$3019 + assign { } { } + assign $0\libresocsim_dataw_pads_in_pads_in_payload_cmd_oe[0:0] 1'0 + sync always + update \libresocsim_dataw_pads_in_pads_in_payload_cmd_oe $0\libresocsim_dataw_pads_in_pads_in_payload_cmd_oe[0:0] + sync init + end + attribute \src "build/ls180/gateware/ls180.v:1081.11-1081.66" + process $proc$build/ls180/gateware/ls180.v:1081$3020 + assign { } { } + assign $0\libresocsim_dataw_pads_in_pads_in_payload_data_i[3:0] 4'0000 + sync always + update \libresocsim_dataw_pads_in_pads_in_payload_data_i $0\libresocsim_dataw_pads_in_pads_in_payload_data_i[3:0] + sync init + end + attribute \src "build/ls180/gateware/ls180.v:1082.11-1082.66" + process $proc$build/ls180/gateware/ls180.v:1082$3021 + assign { } { } + assign $0\libresocsim_dataw_pads_in_pads_in_payload_data_o[3:0] 4'0000 + sync always + update \libresocsim_dataw_pads_in_pads_in_payload_data_o $0\libresocsim_dataw_pads_in_pads_in_payload_data_o[3:0] + sync init + end + attribute \src "build/ls180/gateware/ls180.v:1083.5-1083.61" + process $proc$build/ls180/gateware/ls180.v:1083$3022 + assign { } { } + assign $0\libresocsim_dataw_pads_in_pads_in_payload_data_oe[0:0] 1'0 + sync always + update \libresocsim_dataw_pads_in_pads_in_payload_data_oe $0\libresocsim_dataw_pads_in_pads_in_payload_data_oe[0:0] + sync init + end + attribute \src "build/ls180/gateware/ls180.v:1084.5-1084.35" + process $proc$build/ls180/gateware/ls180.v:1084$3023 + assign { } { } + assign $1\libresocsim_dataw_start[0:0] 1'0 + sync always + sync init + update \libresocsim_dataw_start $1\libresocsim_dataw_start[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:1085.5-1085.35" + process $proc$build/ls180/gateware/ls180.v:1085$3024 + assign { } { } + assign $1\libresocsim_dataw_valid[0:0] 1'0 + sync always + sync init + update \libresocsim_dataw_valid $1\libresocsim_dataw_valid[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:1086.5-1086.35" + process $proc$build/ls180/gateware/ls180.v:1086$3025 + assign { } { } + assign $1\libresocsim_dataw_error[0:0] 1'0 + sync always + sync init + update \libresocsim_dataw_error $1\libresocsim_dataw_error[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:1088.5-1088.48" + process $proc$build/ls180/gateware/ls180.v:1088$3026 + assign { } { } + assign $0\libresocsim_dataw_crcr_pads_in_ready[0:0] 1'0 + sync always + update \libresocsim_dataw_crcr_pads_in_ready $0\libresocsim_dataw_crcr_pads_in_ready[0:0] + sync init + end + attribute \src "build/ls180/gateware/ls180.v:1099.5-1099.55" + process $proc$build/ls180/gateware/ls180.v:1099$3027 + assign { } { } + assign $1\libresocsim_dataw_crcr_source_source_ready0[0:0] 1'0 + sync always + sync init + update \libresocsim_dataw_crcr_source_source_ready0 $1\libresocsim_dataw_crcr_source_source_ready0[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:110.12-110.53" + process $proc$build/ls180/gateware/ls180.v:110$2593 + assign { } { } + assign $1\main_libresocsim_converter0_dat_r[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \main_libresocsim_converter0_dat_r $1\main_libresocsim_converter0_dat_r[63:0] + end + attribute \src "build/ls180/gateware/ls180.v:1104.5-1104.38" + process $proc$build/ls180/gateware/ls180.v:1104$3028 + assign { } { } + assign $1\libresocsim_dataw_crcr_run[0:0] 1'0 + sync always + sync init + update \libresocsim_dataw_crcr_run $1\libresocsim_dataw_crcr_run[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:1107.5-1107.55" + process $proc$build/ls180/gateware/ls180.v:1107$3029 + assign { } { } + assign $0\libresocsim_dataw_crcr_converter_sink_first[0:0] 1'0 + sync always + update \libresocsim_dataw_crcr_converter_sink_first $0\libresocsim_dataw_crcr_converter_sink_first[0:0] + sync init + end + attribute \src "build/ls180/gateware/ls180.v:1108.5-1108.54" + process $proc$build/ls180/gateware/ls180.v:1108$3030 + assign { } { } + assign $0\libresocsim_dataw_crcr_converter_sink_last[0:0] 1'0 + sync always + update \libresocsim_dataw_crcr_converter_sink_last $0\libresocsim_dataw_crcr_converter_sink_last[0:0] + sync init + end + attribute \src "build/ls180/gateware/ls180.v:111.12-111.71" + process $proc$build/ls180/gateware/ls180.v:111$2594 + assign { } { } + assign $1\main_libresocsim_interface1_converted_interface_adr[29:0] 30'000000000000000000000000000000 + sync always + sync init + update \main_libresocsim_interface1_converted_interface_adr $1\main_libresocsim_interface1_converted_interface_adr[29:0] + end + attribute \src "build/ls180/gateware/ls180.v:1112.5-1112.57" + process $proc$build/ls180/gateware/ls180.v:1112$3031 + assign { } { } + assign $1\libresocsim_dataw_crcr_converter_source_first[0:0] 1'0 + sync always + sync init + update \libresocsim_dataw_crcr_converter_source_first $1\libresocsim_dataw_crcr_converter_source_first[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:1113.5-1113.56" + process $proc$build/ls180/gateware/ls180.v:1113$3032 + assign { } { } + assign $1\libresocsim_dataw_crcr_converter_source_last[0:0] 1'0 + sync always + sync init + update \libresocsim_dataw_crcr_converter_source_last $1\libresocsim_dataw_crcr_converter_source_last[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:1114.11-1114.70" + process $proc$build/ls180/gateware/ls180.v:1114$3033 + assign { } { } + assign $1\libresocsim_dataw_crcr_converter_source_payload_data[7:0] 8'00000000 + sync always + sync init + update \libresocsim_dataw_crcr_converter_source_payload_data $1\libresocsim_dataw_crcr_converter_source_payload_data[7:0] + end + attribute \src "build/ls180/gateware/ls180.v:1115.11-1115.83" + process $proc$build/ls180/gateware/ls180.v:1115$3034 + assign { } { } + assign $1\libresocsim_dataw_crcr_converter_source_payload_valid_token_count[3:0] 4'0000 + sync always + sync init + update \libresocsim_dataw_crcr_converter_source_payload_valid_token_count $1\libresocsim_dataw_crcr_converter_source_payload_valid_token_count[3:0] + end + attribute \src "build/ls180/gateware/ls180.v:1116.11-1116.56" + process $proc$build/ls180/gateware/ls180.v:1116$3035 + assign { } { } + assign $1\libresocsim_dataw_crcr_converter_demux[2:0] 3'000 + sync always + sync init + update \libresocsim_dataw_crcr_converter_demux $1\libresocsim_dataw_crcr_converter_demux[2:0] + end + attribute \src "build/ls180/gateware/ls180.v:1118.5-1118.55" + process $proc$build/ls180/gateware/ls180.v:1118$3036 + assign { } { } + assign $1\libresocsim_dataw_crcr_converter_strobe_all[0:0] 1'0 + sync always + sync init + update \libresocsim_dataw_crcr_converter_strobe_all $1\libresocsim_dataw_crcr_converter_strobe_all[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:112.12-112.73" + process $proc$build/ls180/gateware/ls180.v:112$2595 + assign { } { } + assign $1\main_libresocsim_interface1_converted_interface_dat_w[31:0] 0 + sync always + sync init + update \main_libresocsim_interface1_converted_interface_dat_w $1\main_libresocsim_interface1_converted_interface_dat_w[31:0] + end + attribute \src "build/ls180/gateware/ls180.v:1129.5-1129.51" + process $proc$build/ls180/gateware/ls180.v:1129$3037 + assign { } { } + assign $1\libresocsim_dataw_crcr_buf_source_valid[0:0] 1'0 + sync always + sync init + update \libresocsim_dataw_crcr_buf_source_valid $1\libresocsim_dataw_crcr_buf_source_valid[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:1131.5-1131.51" + process $proc$build/ls180/gateware/ls180.v:1131$3038 + assign { } { } + assign $1\libresocsim_dataw_crcr_buf_source_first[0:0] 1'0 + sync always + sync init + update \libresocsim_dataw_crcr_buf_source_first $1\libresocsim_dataw_crcr_buf_source_first[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:1132.5-1132.50" + process $proc$build/ls180/gateware/ls180.v:1132$3039 + assign { } { } + assign $1\libresocsim_dataw_crcr_buf_source_last[0:0] 1'0 + sync always + sync init + update \libresocsim_dataw_crcr_buf_source_last $1\libresocsim_dataw_crcr_buf_source_last[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:1133.11-1133.64" + process $proc$build/ls180/gateware/ls180.v:1133$3040 + assign { } { } + assign $1\libresocsim_dataw_crcr_buf_source_payload_data[7:0] 8'00000000 + sync always + sync init + update \libresocsim_dataw_crcr_buf_source_payload_data $1\libresocsim_dataw_crcr_buf_source_payload_data[7:0] + end + attribute \src "build/ls180/gateware/ls180.v:1134.5-1134.40" + process $proc$build/ls180/gateware/ls180.v:1134$3041 + assign { } { } + assign $1\libresocsim_dataw_crcr_reset[0:0] 1'0 + sync always + sync init + update \libresocsim_dataw_crcr_reset $1\libresocsim_dataw_crcr_reset[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:1137.5-1137.51" + process $proc$build/ls180/gateware/ls180.v:1137$3042 + assign { } { } + assign $0\libresocsim_datar_pads_in_pads_in_first[0:0] 1'0 + sync always + update \libresocsim_datar_pads_in_pads_in_first $0\libresocsim_datar_pads_in_pads_in_first[0:0] + sync init + end + attribute \src "build/ls180/gateware/ls180.v:1138.5-1138.50" + process $proc$build/ls180/gateware/ls180.v:1138$3043 + assign { } { } + assign $0\libresocsim_datar_pads_in_pads_in_last[0:0] 1'0 + sync always + update \libresocsim_datar_pads_in_pads_in_last $0\libresocsim_datar_pads_in_pads_in_last[0:0] + sync init + end + attribute \src "build/ls180/gateware/ls180.v:1139.5-1139.57" + process $proc$build/ls180/gateware/ls180.v:1139$3044 + assign { } { } + assign $0\libresocsim_datar_pads_in_pads_in_payload_clk[0:0] 1'0 + sync always + update \libresocsim_datar_pads_in_pads_in_payload_clk $0\libresocsim_datar_pads_in_pads_in_payload_clk[0:0] + sync init + end + attribute \src "build/ls180/gateware/ls180.v:114.11-114.69" + process $proc$build/ls180/gateware/ls180.v:114$2596 + assign { } { } + assign $1\main_libresocsim_interface1_converted_interface_sel[3:0] 4'0000 + sync always + sync init + update \main_libresocsim_interface1_converted_interface_sel $1\main_libresocsim_interface1_converted_interface_sel[3:0] + end + attribute \src "build/ls180/gateware/ls180.v:1141.5-1141.59" + process $proc$build/ls180/gateware/ls180.v:1141$3045 + assign { } { } + assign $0\libresocsim_datar_pads_in_pads_in_payload_cmd_o[0:0] 1'0 + sync always + update \libresocsim_datar_pads_in_pads_in_payload_cmd_o $0\libresocsim_datar_pads_in_pads_in_payload_cmd_o[0:0] + sync init + end + attribute \src "build/ls180/gateware/ls180.v:1142.5-1142.60" + process $proc$build/ls180/gateware/ls180.v:1142$3046 + assign { } { } + assign $0\libresocsim_datar_pads_in_pads_in_payload_cmd_oe[0:0] 1'0 + sync always + update \libresocsim_datar_pads_in_pads_in_payload_cmd_oe $0\libresocsim_datar_pads_in_pads_in_payload_cmd_oe[0:0] + sync init + end + attribute \src "build/ls180/gateware/ls180.v:1144.11-1144.66" + process $proc$build/ls180/gateware/ls180.v:1144$3047 + assign { } { } + assign $0\libresocsim_datar_pads_in_pads_in_payload_data_o[3:0] 4'0000 + sync always + update \libresocsim_datar_pads_in_pads_in_payload_data_o $0\libresocsim_datar_pads_in_pads_in_payload_data_o[3:0] + sync init + end + attribute \src "build/ls180/gateware/ls180.v:1145.5-1145.61" + process $proc$build/ls180/gateware/ls180.v:1145$3048 + assign { } { } + assign $0\libresocsim_datar_pads_in_pads_in_payload_data_oe[0:0] 1'0 + sync always + update \libresocsim_datar_pads_in_pads_in_payload_data_oe $0\libresocsim_datar_pads_in_pads_in_payload_data_oe[0:0] + sync init + end + attribute \src "build/ls180/gateware/ls180.v:1147.5-1147.50" + process $proc$build/ls180/gateware/ls180.v:1147$3049 + assign { } { } + assign $1\libresocsim_datar_pads_out_payload_clk[0:0] 1'0 + sync always + sync init + update \libresocsim_datar_pads_out_payload_clk $1\libresocsim_datar_pads_out_payload_clk[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:1148.5-1148.52" + process $proc$build/ls180/gateware/ls180.v:1148$3050 + assign { } { } + assign $0\libresocsim_datar_pads_out_payload_cmd_o[0:0] 1'0 + sync always + update \libresocsim_datar_pads_out_payload_cmd_o $0\libresocsim_datar_pads_out_payload_cmd_o[0:0] + sync init + end + attribute \src "build/ls180/gateware/ls180.v:1149.5-1149.53" + process $proc$build/ls180/gateware/ls180.v:1149$3051 + assign { } { } + assign $0\libresocsim_datar_pads_out_payload_cmd_oe[0:0] 1'0 + sync always + update \libresocsim_datar_pads_out_payload_cmd_oe $0\libresocsim_datar_pads_out_payload_cmd_oe[0:0] + sync init + end + attribute \src "build/ls180/gateware/ls180.v:115.5-115.63" + process $proc$build/ls180/gateware/ls180.v:115$2597 + assign { } { } + assign $1\main_libresocsim_interface1_converted_interface_cyc[0:0] 1'0 + sync always + sync init + update \main_libresocsim_interface1_converted_interface_cyc $1\main_libresocsim_interface1_converted_interface_cyc[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:1150.11-1150.59" + process $proc$build/ls180/gateware/ls180.v:1150$3052 + assign { } { } + assign $0\libresocsim_datar_pads_out_payload_data_o[3:0] 4'0000 + sync always + update \libresocsim_datar_pads_out_payload_data_o $0\libresocsim_datar_pads_out_payload_data_o[3:0] + sync init + end + attribute \src "build/ls180/gateware/ls180.v:1151.5-1151.54" + process $proc$build/ls180/gateware/ls180.v:1151$3053 + assign { } { } + assign $0\libresocsim_datar_pads_out_payload_data_oe[0:0] 1'0 + sync always + update \libresocsim_datar_pads_out_payload_data_oe $0\libresocsim_datar_pads_out_payload_data_oe[0:0] + sync init + end + attribute \src "build/ls180/gateware/ls180.v:1152.5-1152.40" + process $proc$build/ls180/gateware/ls180.v:1152$3054 + assign { } { } + assign $1\libresocsim_datar_sink_valid[0:0] 1'0 + sync always + sync init + update \libresocsim_datar_sink_valid $1\libresocsim_datar_sink_valid[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:1153.5-1153.40" + process $proc$build/ls180/gateware/ls180.v:1153$3055 + assign { } { } + assign $1\libresocsim_datar_sink_ready[0:0] 1'0 + sync always + sync init + update \libresocsim_datar_sink_ready $1\libresocsim_datar_sink_ready[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:1154.5-1154.39" + process $proc$build/ls180/gateware/ls180.v:1154$3056 + assign { } { } + assign $1\libresocsim_datar_sink_last[0:0] 1'0 + sync always + sync init + update \libresocsim_datar_sink_last $1\libresocsim_datar_sink_last[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:1155.11-1155.62" + process $proc$build/ls180/gateware/ls180.v:1155$3057 + assign { } { } + assign $1\libresocsim_datar_sink_payload_block_length[9:0] 10'0000000000 + sync always + sync init + update \libresocsim_datar_sink_payload_block_length $1\libresocsim_datar_sink_payload_block_length[9:0] + end + attribute \src "build/ls180/gateware/ls180.v:1156.5-1156.42" + process $proc$build/ls180/gateware/ls180.v:1156$3058 + assign { } { } + assign $1\libresocsim_datar_source_valid[0:0] 1'0 + sync always + sync init + update \libresocsim_datar_source_valid $1\libresocsim_datar_source_valid[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:1157.5-1157.42" + process $proc$build/ls180/gateware/ls180.v:1157$3059 + assign { } { } + assign $1\libresocsim_datar_source_ready[0:0] 1'0 + sync always + sync init + update \libresocsim_datar_source_ready $1\libresocsim_datar_source_ready[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:1158.5-1158.42" + process $proc$build/ls180/gateware/ls180.v:1158$3060 + assign { } { } + assign $0\libresocsim_datar_source_first[0:0] 1'0 + sync always + update \libresocsim_datar_source_first $0\libresocsim_datar_source_first[0:0] + sync init + end + attribute \src "build/ls180/gateware/ls180.v:1159.5-1159.41" + process $proc$build/ls180/gateware/ls180.v:1159$3061 + assign { } { } + assign $1\libresocsim_datar_source_last[0:0] 1'0 + sync always + sync init + update \libresocsim_datar_source_last $1\libresocsim_datar_source_last[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:116.5-116.63" + process $proc$build/ls180/gateware/ls180.v:116$2598 + assign { } { } + assign $1\main_libresocsim_interface1_converted_interface_stb[0:0] 1'0 + sync always + sync init + update \main_libresocsim_interface1_converted_interface_stb $1\main_libresocsim_interface1_converted_interface_stb[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:1160.11-1160.55" + process $proc$build/ls180/gateware/ls180.v:1160$3062 + assign { } { } + assign $1\libresocsim_datar_source_payload_data[7:0] 8'00000000 + sync always + sync init + update \libresocsim_datar_source_payload_data $1\libresocsim_datar_source_payload_data[7:0] + end + attribute \src "build/ls180/gateware/ls180.v:1161.11-1161.57" + process $proc$build/ls180/gateware/ls180.v:1161$3063 + assign { } { } + assign $1\libresocsim_datar_source_payload_status[2:0] 3'000 + sync always + sync init + update \libresocsim_datar_source_payload_status $1\libresocsim_datar_source_payload_status[2:0] + end + attribute \src "build/ls180/gateware/ls180.v:1162.5-1162.34" + process $proc$build/ls180/gateware/ls180.v:1162$3064 + assign { } { } + assign $1\libresocsim_datar_stop[0:0] 1'0 + sync always + sync init + update \libresocsim_datar_stop $1\libresocsim_datar_stop[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:1163.12-1163.50" + process $proc$build/ls180/gateware/ls180.v:1163$3065 + assign { } { } + assign $1\libresocsim_datar_timeout[31:0] 500000 + sync always + sync init + update \libresocsim_datar_timeout $1\libresocsim_datar_timeout[31:0] + end + attribute \src "build/ls180/gateware/ls180.v:1164.11-1164.42" + process $proc$build/ls180/gateware/ls180.v:1164$3066 + assign { } { } + assign $1\libresocsim_datar_count[9:0] 10'0000000000 + sync always + sync init + update \libresocsim_datar_count $1\libresocsim_datar_count[9:0] + end + attribute \src "build/ls180/gateware/ls180.v:1166.5-1166.49" + process $proc$build/ls180/gateware/ls180.v:1166$3067 + assign { } { } + assign $0\libresocsim_datar_datar_pads_in_ready[0:0] 1'0 + sync always + update \libresocsim_datar_datar_pads_in_ready $0\libresocsim_datar_datar_pads_in_ready[0:0] + sync init + end + attribute \src "build/ls180/gateware/ls180.v:1177.5-1177.56" + process $proc$build/ls180/gateware/ls180.v:1177$3068 + assign { } { } + assign $1\libresocsim_datar_datar_source_source_ready0[0:0] 1'0 + sync always + sync init + update \libresocsim_datar_datar_source_source_ready0 $1\libresocsim_datar_datar_source_source_ready0[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:118.5-118.62" + process $proc$build/ls180/gateware/ls180.v:118$2599 + assign { } { } + assign $1\main_libresocsim_interface1_converted_interface_we[0:0] 1'0 + sync always + sync init + update \main_libresocsim_interface1_converted_interface_we $1\main_libresocsim_interface1_converted_interface_we[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:1182.5-1182.39" + process $proc$build/ls180/gateware/ls180.v:1182$3069 + assign { } { } + assign $1\libresocsim_datar_datar_run[0:0] 1'0 + sync always + sync init + update \libresocsim_datar_datar_run $1\libresocsim_datar_datar_run[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:1185.5-1185.56" + process $proc$build/ls180/gateware/ls180.v:1185$3070 + assign { } { } + assign $0\libresocsim_datar_datar_converter_sink_first[0:0] 1'0 + sync always + update \libresocsim_datar_datar_converter_sink_first $0\libresocsim_datar_datar_converter_sink_first[0:0] + sync init + end + attribute \src "build/ls180/gateware/ls180.v:1186.5-1186.55" + process $proc$build/ls180/gateware/ls180.v:1186$3071 + assign { } { } + assign $0\libresocsim_datar_datar_converter_sink_last[0:0] 1'0 + sync always + update \libresocsim_datar_datar_converter_sink_last $0\libresocsim_datar_datar_converter_sink_last[0:0] + sync init + end + attribute \src "build/ls180/gateware/ls180.v:119.11-119.69" + process $proc$build/ls180/gateware/ls180.v:119$2600 + assign { } { } + assign $0\main_libresocsim_interface1_converted_interface_cti[2:0] 3'000 + sync always + update \main_libresocsim_interface1_converted_interface_cti $0\main_libresocsim_interface1_converted_interface_cti[2:0] + sync init + end + attribute \src "build/ls180/gateware/ls180.v:1190.5-1190.58" + process $proc$build/ls180/gateware/ls180.v:1190$3072 + assign { } { } + assign $1\libresocsim_datar_datar_converter_source_first[0:0] 1'0 + sync always + sync init + update \libresocsim_datar_datar_converter_source_first $1\libresocsim_datar_datar_converter_source_first[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:1191.5-1191.57" + process $proc$build/ls180/gateware/ls180.v:1191$3073 + assign { } { } + assign $1\libresocsim_datar_datar_converter_source_last[0:0] 1'0 + sync always + sync init + update \libresocsim_datar_datar_converter_source_last $1\libresocsim_datar_datar_converter_source_last[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:1192.11-1192.71" + process $proc$build/ls180/gateware/ls180.v:1192$3074 + assign { } { } + assign $1\libresocsim_datar_datar_converter_source_payload_data[7:0] 8'00000000 + sync always + sync init + update \libresocsim_datar_datar_converter_source_payload_data $1\libresocsim_datar_datar_converter_source_payload_data[7:0] + end + attribute \src "build/ls180/gateware/ls180.v:1193.11-1193.84" + process $proc$build/ls180/gateware/ls180.v:1193$3075 + assign { } { } + assign $1\libresocsim_datar_datar_converter_source_payload_valid_token_count[1:0] 2'00 + sync always + sync init + update \libresocsim_datar_datar_converter_source_payload_valid_token_count $1\libresocsim_datar_datar_converter_source_payload_valid_token_count[1:0] + end + attribute \src "build/ls180/gateware/ls180.v:1194.5-1194.51" + process $proc$build/ls180/gateware/ls180.v:1194$3076 + assign { } { } + assign $1\libresocsim_datar_datar_converter_demux[0:0] 1'0 + sync always + sync init + update \libresocsim_datar_datar_converter_demux $1\libresocsim_datar_datar_converter_demux[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:1196.5-1196.56" + process $proc$build/ls180/gateware/ls180.v:1196$3077 + assign { } { } + assign $1\libresocsim_datar_datar_converter_strobe_all[0:0] 1'0 + sync always + sync init + update \libresocsim_datar_datar_converter_strobe_all $1\libresocsim_datar_datar_converter_strobe_all[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:120.11-120.69" + process $proc$build/ls180/gateware/ls180.v:120$2601 + assign { } { } + assign $0\main_libresocsim_interface1_converted_interface_bte[1:0] 2'00 + sync always + update \main_libresocsim_interface1_converted_interface_bte $0\main_libresocsim_interface1_converted_interface_bte[1:0] + sync init + end + attribute \src "build/ls180/gateware/ls180.v:1207.5-1207.52" + process $proc$build/ls180/gateware/ls180.v:1207$3078 + assign { } { } + assign $1\libresocsim_datar_datar_buf_source_valid[0:0] 1'0 + sync always + sync init + update \libresocsim_datar_datar_buf_source_valid $1\libresocsim_datar_datar_buf_source_valid[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:1209.5-1209.52" + process $proc$build/ls180/gateware/ls180.v:1209$3079 + assign { } { } + assign $1\libresocsim_datar_datar_buf_source_first[0:0] 1'0 + sync always + sync init + update \libresocsim_datar_datar_buf_source_first $1\libresocsim_datar_datar_buf_source_first[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:1210.5-1210.51" + process $proc$build/ls180/gateware/ls180.v:1210$3080 + assign { } { } + assign $1\libresocsim_datar_datar_buf_source_last[0:0] 1'0 + sync always + sync init + update \libresocsim_datar_datar_buf_source_last $1\libresocsim_datar_datar_buf_source_last[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:1211.11-1211.65" + process $proc$build/ls180/gateware/ls180.v:1211$3081 + assign { } { } + assign $1\libresocsim_datar_datar_buf_source_payload_data[7:0] 8'00000000 + sync always + sync init + update \libresocsim_datar_datar_buf_source_payload_data $1\libresocsim_datar_datar_buf_source_payload_data[7:0] + end + attribute \src "build/ls180/gateware/ls180.v:1212.5-1212.41" + process $proc$build/ls180/gateware/ls180.v:1212$3082 + assign { } { } + assign $1\libresocsim_datar_datar_reset[0:0] 1'0 + sync always + sync init + update \libresocsim_datar_datar_reset $1\libresocsim_datar_datar_reset[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:1214.5-1214.36" + process $proc$build/ls180/gateware/ls180.v:1214$3083 + assign { } { } + assign $1\libresocsim_sdpads_cmd_i[0:0] 1'0 + sync always + sync init + update \libresocsim_sdpads_cmd_i $1\libresocsim_sdpads_cmd_i[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:1217.11-1217.43" + process $proc$build/ls180/gateware/ls180.v:1217$3084 + assign { } { } + assign $1\libresocsim_sdpads_data_i[3:0] 4'0000 + sync always + sync init + update \libresocsim_sdpads_data_i $1\libresocsim_sdpads_data_i[3:0] + end + attribute \src "build/ls180/gateware/ls180.v:122.5-122.44" + process $proc$build/ls180/gateware/ls180.v:122$2602 + assign { } { } + assign $1\main_libresocsim_converter1_skip[0:0] 1'0 + sync always + sync init + update \main_libresocsim_converter1_skip $1\main_libresocsim_converter1_skip[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:123.5-123.47" + process $proc$build/ls180/gateware/ls180.v:123$2603 + assign { } { } + assign $1\main_libresocsim_converter1_counter[0:0] 1'0 + sync always + sync init + update \main_libresocsim_converter1_counter $1\main_libresocsim_converter1_counter[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:1230.12-1230.59" + process $proc$build/ls180/gateware/ls180.v:1230$3085 + assign { } { } + assign $1\libresocsim_sdcore_cmd_argument_storage[31:0] 0 + sync always + sync init + update \libresocsim_sdcore_cmd_argument_storage $1\libresocsim_sdcore_cmd_argument_storage[31:0] + end + attribute \src "build/ls180/gateware/ls180.v:1231.5-1231.46" + process $proc$build/ls180/gateware/ls180.v:1231$3086 + assign { } { } + assign $1\libresocsim_sdcore_cmd_argument_re[0:0] 1'0 + sync always + sync init + update \libresocsim_sdcore_cmd_argument_re $1\libresocsim_sdcore_cmd_argument_re[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:1232.12-1232.58" + process $proc$build/ls180/gateware/ls180.v:1232$3087 + assign { } { } + assign $1\libresocsim_sdcore_cmd_command_storage[31:0] 0 + sync always + sync init + update \libresocsim_sdcore_cmd_command_storage $1\libresocsim_sdcore_cmd_command_storage[31:0] + end + attribute \src "build/ls180/gateware/ls180.v:1233.5-1233.45" + process $proc$build/ls180/gateware/ls180.v:1233$3088 + assign { } { } + assign $1\libresocsim_sdcore_cmd_command_re[0:0] 1'0 + sync always + sync init + update \libresocsim_sdcore_cmd_command_re $1\libresocsim_sdcore_cmd_command_re[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:1237.5-1237.41" + process $proc$build/ls180/gateware/ls180.v:1237$3089 + assign { } { } + assign $0\libresocsim_sdcore_cmd_send_w[0:0] 1'0 + sync always + update \libresocsim_sdcore_cmd_send_w $0\libresocsim_sdcore_cmd_send_w[0:0] + sync init + end + attribute \src "build/ls180/gateware/ls180.v:1238.13-1238.60" + process $proc$build/ls180/gateware/ls180.v:1238$3090 + assign { } { } + assign $1\libresocsim_sdcore_cmd_response_status[127:0] 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \libresocsim_sdcore_cmd_response_status $1\libresocsim_sdcore_cmd_response_status[127:0] + end + attribute \src "build/ls180/gateware/ls180.v:1244.11-1244.58" + process $proc$build/ls180/gateware/ls180.v:1244$3091 + assign { } { } + assign $1\libresocsim_sdcore_block_length_storage[9:0] 10'0000000000 + sync always + sync init + update \libresocsim_sdcore_block_length_storage $1\libresocsim_sdcore_block_length_storage[9:0] + end + attribute \src "build/ls180/gateware/ls180.v:1245.5-1245.46" + process $proc$build/ls180/gateware/ls180.v:1245$3092 + assign { } { } + assign $1\libresocsim_sdcore_block_length_re[0:0] 1'0 + sync always + sync init + update \libresocsim_sdcore_block_length_re $1\libresocsim_sdcore_block_length_re[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:1246.12-1246.58" + process $proc$build/ls180/gateware/ls180.v:1246$3093 + assign { } { } + assign $1\libresocsim_sdcore_block_count_storage[31:0] 0 + sync always + sync init + update \libresocsim_sdcore_block_count_storage $1\libresocsim_sdcore_block_count_storage[31:0] + end + attribute \src "build/ls180/gateware/ls180.v:1247.5-1247.45" + process $proc$build/ls180/gateware/ls180.v:1247$3094 + assign { } { } + assign $1\libresocsim_sdcore_block_count_re[0:0] 1'0 + sync always + sync init + update \libresocsim_sdcore_block_count_re $1\libresocsim_sdcore_block_count_re[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:1248.11-1248.58" + process $proc$build/ls180/gateware/ls180.v:1248$3095 + assign { } { } + assign $1\libresocsim_sdcore_crc7_inserter_crcreg0[6:0] 7'0000000 + sync always + sync init + update \libresocsim_sdcore_crc7_inserter_crcreg0 $1\libresocsim_sdcore_crc7_inserter_crcreg0[6:0] + end + attribute \src "build/ls180/gateware/ls180.v:125.12-125.53" + process $proc$build/ls180/gateware/ls180.v:125$2604 + assign { } { } + assign $1\main_libresocsim_converter1_dat_r[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \main_libresocsim_converter1_dat_r $1\main_libresocsim_converter1_dat_r[63:0] + end + attribute \src "build/ls180/gateware/ls180.v:1290.11-1290.54" + process $proc$build/ls180/gateware/ls180.v:1290$3096 + assign { } { } + assign $1\libresocsim_sdcore_crc7_inserter_crc[6:0] 7'0000000 + sync always + sync init + update \libresocsim_sdcore_crc7_inserter_crc $1\libresocsim_sdcore_crc7_inserter_crc[6:0] + end + attribute \src "build/ls180/gateware/ls180.v:1294.5-1294.56" + process $proc$build/ls180/gateware/ls180.v:1294$3097 + assign { } { } + assign $1\libresocsim_sdcore_crc16_inserter_sink_ready[0:0] 1'0 + sync always + sync init + update \libresocsim_sdcore_crc16_inserter_sink_ready $1\libresocsim_sdcore_crc16_inserter_sink_ready[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:1298.5-1298.58" + process $proc$build/ls180/gateware/ls180.v:1298$3098 + assign { } { } + assign $1\libresocsim_sdcore_crc16_inserter_source_valid[0:0] 1'0 + sync always + sync init + update \libresocsim_sdcore_crc16_inserter_source_valid $1\libresocsim_sdcore_crc16_inserter_source_valid[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:1299.5-1299.58" + process $proc$build/ls180/gateware/ls180.v:1299$3099 + assign { } { } + assign $1\libresocsim_sdcore_crc16_inserter_source_ready[0:0] 1'0 + sync always + sync init + update \libresocsim_sdcore_crc16_inserter_source_ready $1\libresocsim_sdcore_crc16_inserter_source_ready[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:1300.5-1300.58" + process $proc$build/ls180/gateware/ls180.v:1300$3100 + assign { } { } + assign $0\libresocsim_sdcore_crc16_inserter_source_first[0:0] 1'0 + sync always + update \libresocsim_sdcore_crc16_inserter_source_first $0\libresocsim_sdcore_crc16_inserter_source_first[0:0] + sync init + end + attribute \src "build/ls180/gateware/ls180.v:1301.5-1301.57" + process $proc$build/ls180/gateware/ls180.v:1301$3101 + assign { } { } + assign $1\libresocsim_sdcore_crc16_inserter_source_last[0:0] 1'0 + sync always + sync init + update \libresocsim_sdcore_crc16_inserter_source_last $1\libresocsim_sdcore_crc16_inserter_source_last[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:1302.11-1302.71" + process $proc$build/ls180/gateware/ls180.v:1302$3102 + assign { } { } + assign $1\libresocsim_sdcore_crc16_inserter_source_payload_data[7:0] 8'00000000 + sync always + sync init + update \libresocsim_sdcore_crc16_inserter_source_payload_data $1\libresocsim_sdcore_crc16_inserter_source_payload_data[7:0] + end + attribute \src "build/ls180/gateware/ls180.v:1303.11-1303.55" + process $proc$build/ls180/gateware/ls180.v:1303$3103 + assign { } { } + assign $1\libresocsim_sdcore_crc16_inserter_cnt[2:0] 3'000 + sync always + sync init + update \libresocsim_sdcore_crc16_inserter_cnt $1\libresocsim_sdcore_crc16_inserter_cnt[2:0] + end + attribute \src "build/ls180/gateware/ls180.v:1304.12-1304.66" + process $proc$build/ls180/gateware/ls180.v:1304$3104 + assign { } { } + assign $1\libresocsim_sdcore_crc16_inserter_crc0_crcreg0[15:0] 16'0000000000000000 + sync always + sync init + update \libresocsim_sdcore_crc16_inserter_crc0_crcreg0 $1\libresocsim_sdcore_crc16_inserter_crc0_crcreg0[15:0] + end + attribute \src "build/ls180/gateware/ls180.v:1308.12-1308.62" + process $proc$build/ls180/gateware/ls180.v:1308$3105 + assign { } { } + assign $1\libresocsim_sdcore_crc16_inserter_crc0_crc[15:0] 16'0000000000000000 + sync always + sync init + update \libresocsim_sdcore_crc16_inserter_crc0_crc $1\libresocsim_sdcore_crc16_inserter_crc0_crc[15:0] + end + attribute \src "build/ls180/gateware/ls180.v:1311.12-1311.66" + process $proc$build/ls180/gateware/ls180.v:1311$3106 + assign { } { } + assign $1\libresocsim_sdcore_crc16_inserter_crc1_crcreg0[15:0] 16'0000000000000000 + sync always + sync init + update \libresocsim_sdcore_crc16_inserter_crc1_crcreg0 $1\libresocsim_sdcore_crc16_inserter_crc1_crcreg0[15:0] + end + attribute \src "build/ls180/gateware/ls180.v:1315.12-1315.62" + process $proc$build/ls180/gateware/ls180.v:1315$3107 + assign { } { } + assign $1\libresocsim_sdcore_crc16_inserter_crc1_crc[15:0] 16'0000000000000000 + sync always + sync init + update \libresocsim_sdcore_crc16_inserter_crc1_crc $1\libresocsim_sdcore_crc16_inserter_crc1_crc[15:0] + end + attribute \src "build/ls180/gateware/ls180.v:1318.12-1318.66" + process $proc$build/ls180/gateware/ls180.v:1318$3108 + assign { } { } + assign $1\libresocsim_sdcore_crc16_inserter_crc2_crcreg0[15:0] 16'0000000000000000 + sync always + sync init + update \libresocsim_sdcore_crc16_inserter_crc2_crcreg0 $1\libresocsim_sdcore_crc16_inserter_crc2_crcreg0[15:0] + end + attribute \src "build/ls180/gateware/ls180.v:132.5-132.40" + process $proc$build/ls180/gateware/ls180.v:132$2605 + assign { } { } + assign $1\main_libresocsim_ram_bus_ack[0:0] 1'0 + sync always + sync init + update \main_libresocsim_ram_bus_ack $1\main_libresocsim_ram_bus_ack[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:1322.12-1322.62" + process $proc$build/ls180/gateware/ls180.v:1322$3109 + assign { } { } + assign $1\libresocsim_sdcore_crc16_inserter_crc2_crc[15:0] 16'0000000000000000 + sync always + sync init + update \libresocsim_sdcore_crc16_inserter_crc2_crc $1\libresocsim_sdcore_crc16_inserter_crc2_crc[15:0] + end + attribute \src "build/ls180/gateware/ls180.v:1325.12-1325.66" + process $proc$build/ls180/gateware/ls180.v:1325$3110 + assign { } { } + assign $1\libresocsim_sdcore_crc16_inserter_crc3_crcreg0[15:0] 16'0000000000000000 + sync always + sync init + update \libresocsim_sdcore_crc16_inserter_crc3_crcreg0 $1\libresocsim_sdcore_crc16_inserter_crc3_crcreg0[15:0] + end + attribute \src "build/ls180/gateware/ls180.v:1329.12-1329.62" + process $proc$build/ls180/gateware/ls180.v:1329$3111 + assign { } { } + assign $1\libresocsim_sdcore_crc16_inserter_crc3_crc[15:0] 16'0000000000000000 + sync always + sync init + update \libresocsim_sdcore_crc16_inserter_crc3_crc $1\libresocsim_sdcore_crc16_inserter_crc3_crc[15:0] + end + attribute \src "build/ls180/gateware/ls180.v:1332.12-1332.61" + process $proc$build/ls180/gateware/ls180.v:1332$3112 + assign { } { } + assign $1\libresocsim_sdcore_crc16_inserter_crctmp0[15:0] 16'0000000000000000 + sync always + sync init + update \libresocsim_sdcore_crc16_inserter_crctmp0 $1\libresocsim_sdcore_crc16_inserter_crctmp0[15:0] + end + attribute \src "build/ls180/gateware/ls180.v:1333.12-1333.61" + process $proc$build/ls180/gateware/ls180.v:1333$3113 + assign { } { } + assign $1\libresocsim_sdcore_crc16_inserter_crctmp1[15:0] 16'0000000000000000 + sync always + sync init + update \libresocsim_sdcore_crc16_inserter_crctmp1 $1\libresocsim_sdcore_crc16_inserter_crctmp1[15:0] + end + attribute \src "build/ls180/gateware/ls180.v:1334.12-1334.61" + process $proc$build/ls180/gateware/ls180.v:1334$3114 + assign { } { } + assign $1\libresocsim_sdcore_crc16_inserter_crctmp2[15:0] 16'0000000000000000 + sync always + sync init + update \libresocsim_sdcore_crc16_inserter_crctmp2 $1\libresocsim_sdcore_crc16_inserter_crctmp2[15:0] + end + attribute \src "build/ls180/gateware/ls180.v:1335.12-1335.61" + process $proc$build/ls180/gateware/ls180.v:1335$3115 + assign { } { } + assign $1\libresocsim_sdcore_crc16_inserter_crctmp3[15:0] 16'0000000000000000 + sync always + sync init + update \libresocsim_sdcore_crc16_inserter_crctmp3 $1\libresocsim_sdcore_crc16_inserter_crctmp3[15:0] + end + attribute \src "build/ls180/gateware/ls180.v:1336.5-1336.55" + process $proc$build/ls180/gateware/ls180.v:1336$3116 + assign { } { } + assign $1\libresocsim_sdcore_crc16_checker_sink_valid[0:0] 1'0 + sync always + sync init + update \libresocsim_sdcore_crc16_checker_sink_valid $1\libresocsim_sdcore_crc16_checker_sink_valid[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:1337.5-1337.55" + process $proc$build/ls180/gateware/ls180.v:1337$3117 + assign { } { } + assign $1\libresocsim_sdcore_crc16_checker_sink_ready[0:0] 1'0 + sync always + sync init + update \libresocsim_sdcore_crc16_checker_sink_ready $1\libresocsim_sdcore_crc16_checker_sink_ready[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:1338.5-1338.55" + process $proc$build/ls180/gateware/ls180.v:1338$3118 + assign { } { } + assign $1\libresocsim_sdcore_crc16_checker_sink_first[0:0] 1'0 + sync always + sync init + update \libresocsim_sdcore_crc16_checker_sink_first $1\libresocsim_sdcore_crc16_checker_sink_first[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:1339.5-1339.54" + process $proc$build/ls180/gateware/ls180.v:1339$3119 + assign { } { } + assign $1\libresocsim_sdcore_crc16_checker_sink_last[0:0] 1'0 + sync always + sync init + update \libresocsim_sdcore_crc16_checker_sink_last $1\libresocsim_sdcore_crc16_checker_sink_last[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:1340.11-1340.68" + process $proc$build/ls180/gateware/ls180.v:1340$3120 + assign { } { } + assign $1\libresocsim_sdcore_crc16_checker_sink_payload_data[7:0] 8'00000000 + sync always + sync init + update \libresocsim_sdcore_crc16_checker_sink_payload_data $1\libresocsim_sdcore_crc16_checker_sink_payload_data[7:0] + end + attribute \src "build/ls180/gateware/ls180.v:1341.5-1341.57" + process $proc$build/ls180/gateware/ls180.v:1341$3121 + assign { } { } + assign $1\libresocsim_sdcore_crc16_checker_source_valid[0:0] 1'0 + sync always + sync init + update \libresocsim_sdcore_crc16_checker_source_valid $1\libresocsim_sdcore_crc16_checker_source_valid[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:1343.5-1343.57" + process $proc$build/ls180/gateware/ls180.v:1343$3122 + assign { } { } + assign $0\libresocsim_sdcore_crc16_checker_source_first[0:0] 1'0 + sync always + update \libresocsim_sdcore_crc16_checker_source_first $0\libresocsim_sdcore_crc16_checker_source_first[0:0] + sync init + end + attribute \src "build/ls180/gateware/ls180.v:1346.11-1346.54" + process $proc$build/ls180/gateware/ls180.v:1346$3123 + assign { } { } + assign $1\libresocsim_sdcore_crc16_checker_val[7:0] 8'00000000 + sync always + sync init + update \libresocsim_sdcore_crc16_checker_val $1\libresocsim_sdcore_crc16_checker_val[7:0] + end + attribute \src "build/ls180/gateware/ls180.v:1347.11-1347.54" + process $proc$build/ls180/gateware/ls180.v:1347$3124 + assign { } { } + assign $1\libresocsim_sdcore_crc16_checker_cnt[3:0] 4'0000 + sync always + sync init + update \libresocsim_sdcore_crc16_checker_cnt $1\libresocsim_sdcore_crc16_checker_cnt[3:0] + end + attribute \src "build/ls180/gateware/ls180.v:1348.12-1348.65" + process $proc$build/ls180/gateware/ls180.v:1348$3125 + assign { } { } + assign $1\libresocsim_sdcore_crc16_checker_crc0_crcreg0[15:0] 16'0000000000000000 + sync always + sync init + update \libresocsim_sdcore_crc16_checker_crc0_crcreg0 $1\libresocsim_sdcore_crc16_checker_crc0_crcreg0[15:0] + end + attribute \src "build/ls180/gateware/ls180.v:1352.12-1352.61" + process $proc$build/ls180/gateware/ls180.v:1352$3126 + assign { } { } + assign $1\libresocsim_sdcore_crc16_checker_crc0_crc[15:0] 16'0000000000000000 + sync always + sync init + update \libresocsim_sdcore_crc16_checker_crc0_crc $1\libresocsim_sdcore_crc16_checker_crc0_crc[15:0] + end + attribute \src "build/ls180/gateware/ls180.v:1353.5-1353.53" + process $proc$build/ls180/gateware/ls180.v:1353$3127 + assign { } { } + assign $1\libresocsim_sdcore_crc16_checker_crc0_clr[0:0] 1'0 + sync always + sync init + update \libresocsim_sdcore_crc16_checker_crc0_clr $1\libresocsim_sdcore_crc16_checker_crc0_clr[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:1355.12-1355.65" + process $proc$build/ls180/gateware/ls180.v:1355$3128 + assign { } { } + assign $1\libresocsim_sdcore_crc16_checker_crc1_crcreg0[15:0] 16'0000000000000000 + sync always + sync init + update \libresocsim_sdcore_crc16_checker_crc1_crcreg0 $1\libresocsim_sdcore_crc16_checker_crc1_crcreg0[15:0] + end + attribute \src "build/ls180/gateware/ls180.v:1359.12-1359.61" + process $proc$build/ls180/gateware/ls180.v:1359$3129 + assign { } { } + assign $1\libresocsim_sdcore_crc16_checker_crc1_crc[15:0] 16'0000000000000000 + sync always + sync init + update \libresocsim_sdcore_crc16_checker_crc1_crc $1\libresocsim_sdcore_crc16_checker_crc1_crc[15:0] + end + attribute \src "build/ls180/gateware/ls180.v:136.5-136.40" + process $proc$build/ls180/gateware/ls180.v:136$2606 + assign { } { } + assign $0\main_libresocsim_ram_bus_err[0:0] 1'0 + sync always + update \main_libresocsim_ram_bus_err $0\main_libresocsim_ram_bus_err[0:0] + sync init + end + attribute \src "build/ls180/gateware/ls180.v:1360.5-1360.53" + process $proc$build/ls180/gateware/ls180.v:1360$3130 + assign { } { } + assign $1\libresocsim_sdcore_crc16_checker_crc1_clr[0:0] 1'0 + sync always + sync init + update \libresocsim_sdcore_crc16_checker_crc1_clr $1\libresocsim_sdcore_crc16_checker_crc1_clr[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:1362.12-1362.65" + process $proc$build/ls180/gateware/ls180.v:1362$3131 + assign { } { } + assign $1\libresocsim_sdcore_crc16_checker_crc2_crcreg0[15:0] 16'0000000000000000 + sync always + sync init + update \libresocsim_sdcore_crc16_checker_crc2_crcreg0 $1\libresocsim_sdcore_crc16_checker_crc2_crcreg0[15:0] + end + attribute \src "build/ls180/gateware/ls180.v:1366.12-1366.61" + process $proc$build/ls180/gateware/ls180.v:1366$3132 + assign { } { } + assign $1\libresocsim_sdcore_crc16_checker_crc2_crc[15:0] 16'0000000000000000 + sync always + sync init + update \libresocsim_sdcore_crc16_checker_crc2_crc $1\libresocsim_sdcore_crc16_checker_crc2_crc[15:0] + end + attribute \src "build/ls180/gateware/ls180.v:1367.5-1367.53" + process $proc$build/ls180/gateware/ls180.v:1367$3133 + assign { } { } + assign $1\libresocsim_sdcore_crc16_checker_crc2_clr[0:0] 1'0 + sync always + sync init + update \libresocsim_sdcore_crc16_checker_crc2_clr $1\libresocsim_sdcore_crc16_checker_crc2_clr[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:1369.12-1369.65" + process $proc$build/ls180/gateware/ls180.v:1369$3134 + assign { } { } + assign $1\libresocsim_sdcore_crc16_checker_crc3_crcreg0[15:0] 16'0000000000000000 + sync always + sync init + update \libresocsim_sdcore_crc16_checker_crc3_crcreg0 $1\libresocsim_sdcore_crc16_checker_crc3_crcreg0[15:0] + end + attribute \src "build/ls180/gateware/ls180.v:1373.12-1373.61" + process $proc$build/ls180/gateware/ls180.v:1373$3135 + assign { } { } + assign $1\libresocsim_sdcore_crc16_checker_crc3_crc[15:0] 16'0000000000000000 + sync always + sync init + update \libresocsim_sdcore_crc16_checker_crc3_crc $1\libresocsim_sdcore_crc16_checker_crc3_crc[15:0] + end + attribute \src "build/ls180/gateware/ls180.v:1374.5-1374.53" + process $proc$build/ls180/gateware/ls180.v:1374$3136 + assign { } { } + assign $1\libresocsim_sdcore_crc16_checker_crc3_clr[0:0] 1'0 + sync always + sync init + update \libresocsim_sdcore_crc16_checker_crc3_clr $1\libresocsim_sdcore_crc16_checker_crc3_clr[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:1376.12-1376.60" + process $proc$build/ls180/gateware/ls180.v:1376$3137 + assign { } { } + assign $1\libresocsim_sdcore_crc16_checker_crctmp0[15:0] 16'0000000000000000 + sync always + sync init + update \libresocsim_sdcore_crc16_checker_crctmp0 $1\libresocsim_sdcore_crc16_checker_crctmp0[15:0] + end + attribute \src "build/ls180/gateware/ls180.v:1377.12-1377.60" + process $proc$build/ls180/gateware/ls180.v:1377$3138 + assign { } { } + assign $1\libresocsim_sdcore_crc16_checker_crctmp1[15:0] 16'0000000000000000 + sync always + sync init + update \libresocsim_sdcore_crc16_checker_crctmp1 $1\libresocsim_sdcore_crc16_checker_crctmp1[15:0] + end + attribute \src "build/ls180/gateware/ls180.v:1378.12-1378.60" + process $proc$build/ls180/gateware/ls180.v:1378$3139 + assign { } { } + assign $1\libresocsim_sdcore_crc16_checker_crctmp2[15:0] 16'0000000000000000 + sync always + sync init + update \libresocsim_sdcore_crc16_checker_crctmp2 $1\libresocsim_sdcore_crc16_checker_crctmp2[15:0] + end + attribute \src "build/ls180/gateware/ls180.v:1379.12-1379.60" + process $proc$build/ls180/gateware/ls180.v:1379$3140 + assign { } { } + assign $1\libresocsim_sdcore_crc16_checker_crctmp3[15:0] 16'0000000000000000 + sync always + sync init + update \libresocsim_sdcore_crc16_checker_crctmp3 $1\libresocsim_sdcore_crc16_checker_crctmp3[15:0] + end + attribute \src "build/ls180/gateware/ls180.v:1380.5-1380.50" + process $proc$build/ls180/gateware/ls180.v:1380$3141 + assign { } { } + assign $1\libresocsim_sdcore_crc16_checker_valid[0:0] 1'0 + sync always + sync init + update \libresocsim_sdcore_crc16_checker_valid $1\libresocsim_sdcore_crc16_checker_valid[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:1381.12-1381.58" + process $proc$build/ls180/gateware/ls180.v:1381$3142 + assign { } { } + assign $1\libresocsim_sdcore_crc16_checker_fifo0[15:0] 16'0000000000000000 + sync always + sync init + update \libresocsim_sdcore_crc16_checker_fifo0 $1\libresocsim_sdcore_crc16_checker_fifo0[15:0] + end + attribute \src "build/ls180/gateware/ls180.v:1382.12-1382.58" + process $proc$build/ls180/gateware/ls180.v:1382$3143 + assign { } { } + assign $1\libresocsim_sdcore_crc16_checker_fifo1[15:0] 16'0000000000000000 + sync always + sync init + update \libresocsim_sdcore_crc16_checker_fifo1 $1\libresocsim_sdcore_crc16_checker_fifo1[15:0] + end + attribute \src "build/ls180/gateware/ls180.v:1383.12-1383.58" + process $proc$build/ls180/gateware/ls180.v:1383$3144 + assign { } { } + assign $1\libresocsim_sdcore_crc16_checker_fifo2[15:0] 16'0000000000000000 + sync always + sync init + update \libresocsim_sdcore_crc16_checker_fifo2 $1\libresocsim_sdcore_crc16_checker_fifo2[15:0] + end + attribute \src "build/ls180/gateware/ls180.v:1384.12-1384.58" + process $proc$build/ls180/gateware/ls180.v:1384$3145 + assign { } { } + assign $1\libresocsim_sdcore_crc16_checker_fifo3[15:0] 16'0000000000000000 + sync always + sync init + update \libresocsim_sdcore_crc16_checker_fifo3 $1\libresocsim_sdcore_crc16_checker_fifo3[15:0] + end + attribute \src "build/ls180/gateware/ls180.v:1386.11-1386.46" + process $proc$build/ls180/gateware/ls180.v:1386$3146 + assign { } { } + assign $1\libresocsim_sdcore_cmd_count[2:0] 3'000 + sync always + sync init + update \libresocsim_sdcore_cmd_count $1\libresocsim_sdcore_cmd_count[2:0] + end + attribute \src "build/ls180/gateware/ls180.v:1387.5-1387.39" + process $proc$build/ls180/gateware/ls180.v:1387$3147 + assign { } { } + assign $1\libresocsim_sdcore_cmd_done[0:0] 1'0 + sync always + sync init + update \libresocsim_sdcore_cmd_done $1\libresocsim_sdcore_cmd_done[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:1388.5-1388.40" + process $proc$build/ls180/gateware/ls180.v:1388$3148 + assign { } { } + assign $1\libresocsim_sdcore_cmd_error[0:0] 1'0 + sync always + sync init + update \libresocsim_sdcore_cmd_error $1\libresocsim_sdcore_cmd_error[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:1389.5-1389.42" + process $proc$build/ls180/gateware/ls180.v:1389$3149 + assign { } { } + assign $1\libresocsim_sdcore_cmd_timeout[0:0] 1'0 + sync always + sync init + update \libresocsim_sdcore_cmd_timeout $1\libresocsim_sdcore_cmd_timeout[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:139.11-139.37" + process $proc$build/ls180/gateware/ls180.v:139$2607 + assign { } { } + assign $1\main_libresocsim_we[3:0] 4'0000 + sync always + sync init + update \main_libresocsim_we $1\main_libresocsim_we[3:0] + end + attribute \src "build/ls180/gateware/ls180.v:1391.12-1391.49" + process $proc$build/ls180/gateware/ls180.v:1391$3150 + assign { } { } + assign $1\libresocsim_sdcore_data_count[31:0] 0 + sync always + sync init + update \libresocsim_sdcore_data_count $1\libresocsim_sdcore_data_count[31:0] + end + attribute \src "build/ls180/gateware/ls180.v:1392.5-1392.40" + process $proc$build/ls180/gateware/ls180.v:1392$3151 + assign { } { } + assign $1\libresocsim_sdcore_data_done[0:0] 1'0 + sync always + sync init + update \libresocsim_sdcore_data_done $1\libresocsim_sdcore_data_done[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:1393.5-1393.41" + process $proc$build/ls180/gateware/ls180.v:1393$3152 + assign { } { } + assign $1\libresocsim_sdcore_data_error[0:0] 1'0 + sync always + sync init + update \libresocsim_sdcore_data_error $1\libresocsim_sdcore_data_error[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:1394.5-1394.43" + process $proc$build/ls180/gateware/ls180.v:1394$3153 + assign { } { } + assign $1\libresocsim_sdcore_data_timeout[0:0] 1'0 + sync always + sync init + update \libresocsim_sdcore_data_timeout $1\libresocsim_sdcore_data_timeout[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:1403.11-1403.48" + process $proc$build/ls180/gateware/ls180.v:1403$3154 + assign { } { } + assign $0\libresocsim_interface0_bus_cti[2:0] 3'000 + sync always + update \libresocsim_interface0_bus_cti $0\libresocsim_interface0_bus_cti[2:0] + sync init + end + attribute \src "build/ls180/gateware/ls180.v:1404.11-1404.48" + process $proc$build/ls180/gateware/ls180.v:1404$3155 + assign { } { } + assign $0\libresocsim_interface0_bus_bte[1:0] 2'00 + sync always + update \libresocsim_interface0_bus_bte $0\libresocsim_interface0_bus_bte[1:0] + sync init + end + attribute \src "build/ls180/gateware/ls180.v:141.12-141.50" + process $proc$build/ls180/gateware/ls180.v:141$2608 + assign { } { } + assign $1\main_libresocsim_storage[31:0] 9895604 + sync always + sync init + update \main_libresocsim_storage $1\main_libresocsim_storage[31:0] + end + attribute \src "build/ls180/gateware/ls180.v:142.5-142.31" + process $proc$build/ls180/gateware/ls180.v:142$2609 + assign { } { } + assign $1\main_libresocsim_re[0:0] 1'0 + sync always + sync init + update \main_libresocsim_re $1\main_libresocsim_re[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:1427.11-1427.52" + process $proc$build/ls180/gateware/ls180.v:1427$3156 + assign { } { } + assign $1\libresocsim_sdblock2mem_fifo_level[5:0] 6'000000 + sync always + sync init + update \libresocsim_sdblock2mem_fifo_level $1\libresocsim_sdblock2mem_fifo_level[5:0] + end + attribute \src "build/ls180/gateware/ls180.v:1428.5-1428.48" + process $proc$build/ls180/gateware/ls180.v:1428$3157 + assign { } { } + assign $0\libresocsim_sdblock2mem_fifo_replace[0:0] 1'0 + sync always + update \libresocsim_sdblock2mem_fifo_replace $0\libresocsim_sdblock2mem_fifo_replace[0:0] + sync init + end + attribute \src "build/ls180/gateware/ls180.v:1429.11-1429.54" + process $proc$build/ls180/gateware/ls180.v:1429$3158 + assign { } { } + assign $1\libresocsim_sdblock2mem_fifo_produce[4:0] 5'00000 + sync always + sync init + update \libresocsim_sdblock2mem_fifo_produce $1\libresocsim_sdblock2mem_fifo_produce[4:0] + end + attribute \src "build/ls180/gateware/ls180.v:1430.11-1430.54" + process $proc$build/ls180/gateware/ls180.v:1430$3159 + assign { } { } + assign $1\libresocsim_sdblock2mem_fifo_consume[4:0] 5'00000 + sync always + sync init + update \libresocsim_sdblock2mem_fifo_consume $1\libresocsim_sdblock2mem_fifo_consume[4:0] + end + attribute \src "build/ls180/gateware/ls180.v:1431.11-1431.57" + process $proc$build/ls180/gateware/ls180.v:1431$3160 + assign { } { } + assign $1\libresocsim_sdblock2mem_fifo_wrport_adr[4:0] 5'00000 + sync always + sync init + update \libresocsim_sdblock2mem_fifo_wrport_adr $1\libresocsim_sdblock2mem_fifo_wrport_adr[4:0] + end + attribute \src "build/ls180/gateware/ls180.v:144.5-144.39" + process $proc$build/ls180/gateware/ls180.v:144$2610 + assign { } { } + assign $1\main_libresocsim_sink_ready[0:0] 1'0 + sync always + sync init + update \main_libresocsim_sink_ready $1\main_libresocsim_sink_ready[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:1451.5-1451.58" + process $proc$build/ls180/gateware/ls180.v:1451$3161 + assign { } { } + assign $1\libresocsim_sdblock2mem_converter_source_first[0:0] 1'0 + sync always + sync init + update \libresocsim_sdblock2mem_converter_source_first $1\libresocsim_sdblock2mem_converter_source_first[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:1452.5-1452.57" + process $proc$build/ls180/gateware/ls180.v:1452$3162 + assign { } { } + assign $1\libresocsim_sdblock2mem_converter_source_last[0:0] 1'0 + sync always + sync init + update \libresocsim_sdblock2mem_converter_source_last $1\libresocsim_sdblock2mem_converter_source_last[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:1453.12-1453.73" + process $proc$build/ls180/gateware/ls180.v:1453$3163 + assign { } { } + assign $1\libresocsim_sdblock2mem_converter_source_payload_data[31:0] 0 + sync always + sync init + update \libresocsim_sdblock2mem_converter_source_payload_data $1\libresocsim_sdblock2mem_converter_source_payload_data[31:0] + end + attribute \src "build/ls180/gateware/ls180.v:1454.11-1454.84" + process $proc$build/ls180/gateware/ls180.v:1454$3164 + assign { } { } + assign $1\libresocsim_sdblock2mem_converter_source_payload_valid_token_count[2:0] 3'000 + sync always + sync init + update \libresocsim_sdblock2mem_converter_source_payload_valid_token_count $1\libresocsim_sdblock2mem_converter_source_payload_valid_token_count[2:0] + end + attribute \src "build/ls180/gateware/ls180.v:1455.11-1455.57" + process $proc$build/ls180/gateware/ls180.v:1455$3165 + assign { } { } + assign $1\libresocsim_sdblock2mem_converter_demux[1:0] 2'00 + sync always + sync init + update \libresocsim_sdblock2mem_converter_demux $1\libresocsim_sdblock2mem_converter_demux[1:0] + end + attribute \src "build/ls180/gateware/ls180.v:1457.5-1457.56" + process $proc$build/ls180/gateware/ls180.v:1457$3166 + assign { } { } + assign $1\libresocsim_sdblock2mem_converter_strobe_all[0:0] 1'0 + sync always + sync init + update \libresocsim_sdblock2mem_converter_strobe_all $1\libresocsim_sdblock2mem_converter_strobe_all[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:1463.5-1463.52" + process $proc$build/ls180/gateware/ls180.v:1463$3167 + assign { } { } + assign $1\libresocsim_sdblock2mem_sink_sink_valid1[0:0] 1'0 + sync always + sync init + update \libresocsim_sdblock2mem_sink_sink_valid1 $1\libresocsim_sdblock2mem_sink_sink_valid1[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:1465.12-1465.69" + process $proc$build/ls180/gateware/ls180.v:1465$3168 + assign { } { } + assign $1\libresocsim_sdblock2mem_sink_sink_payload_address[31:0] 0 + sync always + sync init + update \libresocsim_sdblock2mem_sink_sink_payload_address $1\libresocsim_sdblock2mem_sink_sink_payload_address[31:0] + end + attribute \src "build/ls180/gateware/ls180.v:1466.12-1466.67" + process $proc$build/ls180/gateware/ls180.v:1466$3169 + assign { } { } + assign $1\libresocsim_sdblock2mem_sink_sink_payload_data1[31:0] 0 + sync always + sync init + update \libresocsim_sdblock2mem_sink_sink_payload_data1 $1\libresocsim_sdblock2mem_sink_sink_payload_data1[31:0] + end + attribute \src "build/ls180/gateware/ls180.v:1468.5-1468.64" + process $proc$build/ls180/gateware/ls180.v:1468$3170 + assign { } { } + assign $1\libresocsim_sdblock2mem_wishbonedmawriter_sink_ready[0:0] 1'0 + sync always + sync init + update \libresocsim_sdblock2mem_wishbonedmawriter_sink_ready $1\libresocsim_sdblock2mem_wishbonedmawriter_sink_ready[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:1472.12-1472.74" + process $proc$build/ls180/gateware/ls180.v:1472$3171 + assign { } { } + assign $1\libresocsim_sdblock2mem_wishbonedmawriter_base_storage[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \libresocsim_sdblock2mem_wishbonedmawriter_base_storage $1\libresocsim_sdblock2mem_wishbonedmawriter_base_storage[63:0] + end + attribute \src "build/ls180/gateware/ls180.v:1473.5-1473.61" + process $proc$build/ls180/gateware/ls180.v:1473$3172 + assign { } { } + assign $1\libresocsim_sdblock2mem_wishbonedmawriter_base_re[0:0] 1'0 + sync always + sync init + update \libresocsim_sdblock2mem_wishbonedmawriter_base_re $1\libresocsim_sdblock2mem_wishbonedmawriter_base_re[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:1474.12-1474.76" + process $proc$build/ls180/gateware/ls180.v:1474$3173 + assign { } { } + assign $1\libresocsim_sdblock2mem_wishbonedmawriter_length_storage[31:0] 0 + sync always + sync init + update \libresocsim_sdblock2mem_wishbonedmawriter_length_storage $1\libresocsim_sdblock2mem_wishbonedmawriter_length_storage[31:0] + end + attribute \src "build/ls180/gateware/ls180.v:1475.5-1475.63" + process $proc$build/ls180/gateware/ls180.v:1475$3174 + assign { } { } + assign $1\libresocsim_sdblock2mem_wishbonedmawriter_length_re[0:0] 1'0 + sync always + sync init + update \libresocsim_sdblock2mem_wishbonedmawriter_length_re $1\libresocsim_sdblock2mem_wishbonedmawriter_length_re[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:1476.5-1476.68" + process $proc$build/ls180/gateware/ls180.v:1476$3175 + assign { } { } + assign $1\libresocsim_sdblock2mem_wishbonedmawriter_enable_storage[0:0] 1'0 + sync always + sync init + update \libresocsim_sdblock2mem_wishbonedmawriter_enable_storage $1\libresocsim_sdblock2mem_wishbonedmawriter_enable_storage[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:1477.5-1477.63" + process $proc$build/ls180/gateware/ls180.v:1477$3176 + assign { } { } + assign $1\libresocsim_sdblock2mem_wishbonedmawriter_enable_re[0:0] 1'0 + sync always + sync init + update \libresocsim_sdblock2mem_wishbonedmawriter_enable_re $1\libresocsim_sdblock2mem_wishbonedmawriter_enable_re[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:1478.5-1478.60" + process $proc$build/ls180/gateware/ls180.v:1478$3177 + assign { } { } + assign $1\libresocsim_sdblock2mem_wishbonedmawriter_status[0:0] 1'0 + sync always + sync init + update \libresocsim_sdblock2mem_wishbonedmawriter_status $1\libresocsim_sdblock2mem_wishbonedmawriter_status[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:148.5-148.42" + process $proc$build/ls180/gateware/ls180.v:148$2611 + assign { } { } + assign $1\main_libresocsim_uart_clk_txen[0:0] 1'0 + sync always + sync init + update \main_libresocsim_uart_clk_txen $1\main_libresocsim_uart_clk_txen[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:1480.5-1480.66" + process $proc$build/ls180/gateware/ls180.v:1480$3178 + assign { } { } + assign $1\libresocsim_sdblock2mem_wishbonedmawriter_loop_storage[0:0] 1'0 + sync always + sync init + update \libresocsim_sdblock2mem_wishbonedmawriter_loop_storage $1\libresocsim_sdblock2mem_wishbonedmawriter_loop_storage[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:1481.5-1481.61" + process $proc$build/ls180/gateware/ls180.v:1481$3179 + assign { } { } + assign $1\libresocsim_sdblock2mem_wishbonedmawriter_loop_re[0:0] 1'0 + sync always + sync init + update \libresocsim_sdblock2mem_wishbonedmawriter_loop_re $1\libresocsim_sdblock2mem_wishbonedmawriter_loop_re[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:1483.12-1483.68" + process $proc$build/ls180/gateware/ls180.v:1483$3180 + assign { } { } + assign $1\libresocsim_sdblock2mem_wishbonedmawriter_offset[31:0] 0 + sync always + sync init + update \libresocsim_sdblock2mem_wishbonedmawriter_offset $1\libresocsim_sdblock2mem_wishbonedmawriter_offset[31:0] + end + attribute \src "build/ls180/gateware/ls180.v:1486.12-1486.50" + process $proc$build/ls180/gateware/ls180.v:1486$3181 + assign { } { } + assign $1\libresocsim_interface1_bus_adr[31:0] 0 + sync always + sync init + update \libresocsim_interface1_bus_adr $1\libresocsim_interface1_bus_adr[31:0] + end + attribute \src "build/ls180/gateware/ls180.v:1487.12-1487.52" + process $proc$build/ls180/gateware/ls180.v:1487$3182 + assign { } { } + assign $0\libresocsim_interface1_bus_dat_w[31:0] 0 + sync always + update \libresocsim_interface1_bus_dat_w $0\libresocsim_interface1_bus_dat_w[31:0] + sync init + end + attribute \src "build/ls180/gateware/ls180.v:1489.11-1489.48" + process $proc$build/ls180/gateware/ls180.v:1489$3183 + assign { } { } + assign $1\libresocsim_interface1_bus_sel[3:0] 4'0000 + sync always + sync init + update \libresocsim_interface1_bus_sel $1\libresocsim_interface1_bus_sel[3:0] + end + attribute \src "build/ls180/gateware/ls180.v:149.12-149.57" + process $proc$build/ls180/gateware/ls180.v:149$2612 + assign { } { } + assign $1\main_libresocsim_phase_accumulator_tx[31:0] 0 + sync always + sync init + update \main_libresocsim_phase_accumulator_tx $1\main_libresocsim_phase_accumulator_tx[31:0] + end + attribute \src "build/ls180/gateware/ls180.v:1490.5-1490.42" + process $proc$build/ls180/gateware/ls180.v:1490$3184 + assign { } { } + assign $1\libresocsim_interface1_bus_cyc[0:0] 1'0 + sync always + sync init + update \libresocsim_interface1_bus_cyc $1\libresocsim_interface1_bus_cyc[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:1491.5-1491.42" + process $proc$build/ls180/gateware/ls180.v:1491$3185 + assign { } { } + assign $1\libresocsim_interface1_bus_stb[0:0] 1'0 + sync always + sync init + update \libresocsim_interface1_bus_stb $1\libresocsim_interface1_bus_stb[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:1493.5-1493.41" + process $proc$build/ls180/gateware/ls180.v:1493$3186 + assign { } { } + assign $1\libresocsim_interface1_bus_we[0:0] 1'0 + sync always + sync init + update \libresocsim_interface1_bus_we $1\libresocsim_interface1_bus_we[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:1494.11-1494.48" + process $proc$build/ls180/gateware/ls180.v:1494$3187 + assign { } { } + assign $0\libresocsim_interface1_bus_cti[2:0] 3'000 + sync always + update \libresocsim_interface1_bus_cti $0\libresocsim_interface1_bus_cti[2:0] + sync init + end + attribute \src "build/ls180/gateware/ls180.v:1495.11-1495.48" + process $proc$build/ls180/gateware/ls180.v:1495$3188 + assign { } { } + assign $0\libresocsim_interface1_bus_bte[1:0] 2'00 + sync always + update \libresocsim_interface1_bus_bte $0\libresocsim_interface1_bus_bte[1:0] + sync init + end + attribute \src "build/ls180/gateware/ls180.v:150.11-150.41" + process $proc$build/ls180/gateware/ls180.v:150$2613 + assign { } { } + assign $1\main_libresocsim_tx_reg[7:0] 8'00000000 + sync always + sync init + update \main_libresocsim_tx_reg $1\main_libresocsim_tx_reg[7:0] + end + attribute \src "build/ls180/gateware/ls180.v:1502.5-1502.50" + process $proc$build/ls180/gateware/ls180.v:1502$3189 + assign { } { } + assign $1\libresocsim_sdmem2block_dma_sink_valid[0:0] 1'0 + sync always + sync init + update \libresocsim_sdmem2block_dma_sink_valid $1\libresocsim_sdmem2block_dma_sink_valid[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:1503.5-1503.50" + process $proc$build/ls180/gateware/ls180.v:1503$3190 + assign { } { } + assign $1\libresocsim_sdmem2block_dma_sink_ready[0:0] 1'0 + sync always + sync init + update \libresocsim_sdmem2block_dma_sink_ready $1\libresocsim_sdmem2block_dma_sink_ready[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:1504.5-1504.49" + process $proc$build/ls180/gateware/ls180.v:1504$3191 + assign { } { } + assign $1\libresocsim_sdmem2block_dma_sink_last[0:0] 1'0 + sync always + sync init + update \libresocsim_sdmem2block_dma_sink_last $1\libresocsim_sdmem2block_dma_sink_last[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:1505.12-1505.68" + process $proc$build/ls180/gateware/ls180.v:1505$3192 + assign { } { } + assign $1\libresocsim_sdmem2block_dma_sink_payload_address[31:0] 0 + sync always + sync init + update \libresocsim_sdmem2block_dma_sink_payload_address $1\libresocsim_sdmem2block_dma_sink_payload_address[31:0] + end + attribute \src "build/ls180/gateware/ls180.v:1506.5-1506.52" + process $proc$build/ls180/gateware/ls180.v:1506$3193 + assign { } { } + assign $1\libresocsim_sdmem2block_dma_source_valid[0:0] 1'0 + sync always + sync init + update \libresocsim_sdmem2block_dma_source_valid $1\libresocsim_sdmem2block_dma_source_valid[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:1508.5-1508.52" + process $proc$build/ls180/gateware/ls180.v:1508$3194 + assign { } { } + assign $0\libresocsim_sdmem2block_dma_source_first[0:0] 1'0 + sync always + update \libresocsim_sdmem2block_dma_source_first $0\libresocsim_sdmem2block_dma_source_first[0:0] + sync init + end + attribute \src "build/ls180/gateware/ls180.v:1509.5-1509.51" + process $proc$build/ls180/gateware/ls180.v:1509$3195 + assign { } { } + assign $1\libresocsim_sdmem2block_dma_source_last[0:0] 1'0 + sync always + sync init + update \libresocsim_sdmem2block_dma_source_last $1\libresocsim_sdmem2block_dma_source_last[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:151.11-151.46" + process $proc$build/ls180/gateware/ls180.v:151$2614 + assign { } { } + assign $1\main_libresocsim_tx_bitcount[3:0] 4'0000 + sync always + sync init + update \main_libresocsim_tx_bitcount $1\main_libresocsim_tx_bitcount[3:0] + end + attribute \src "build/ls180/gateware/ls180.v:1510.12-1510.67" + process $proc$build/ls180/gateware/ls180.v:1510$3196 + assign { } { } + assign $1\libresocsim_sdmem2block_dma_source_payload_data[31:0] 0 + sync always + sync init + update \libresocsim_sdmem2block_dma_source_payload_data $1\libresocsim_sdmem2block_dma_source_payload_data[31:0] + end + attribute \src "build/ls180/gateware/ls180.v:1511.12-1511.52" + process $proc$build/ls180/gateware/ls180.v:1511$3197 + assign { } { } + assign $1\libresocsim_sdmem2block_dma_data[31:0] 0 + sync always + sync init + update \libresocsim_sdmem2block_dma_data $1\libresocsim_sdmem2block_dma_data[31:0] + end + attribute \src "build/ls180/gateware/ls180.v:1512.12-1512.60" + process $proc$build/ls180/gateware/ls180.v:1512$3198 + assign { } { } + assign $1\libresocsim_sdmem2block_dma_base_storage[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \libresocsim_sdmem2block_dma_base_storage $1\libresocsim_sdmem2block_dma_base_storage[63:0] + end + attribute \src "build/ls180/gateware/ls180.v:1513.5-1513.47" + process $proc$build/ls180/gateware/ls180.v:1513$3199 + assign { } { } + assign $1\libresocsim_sdmem2block_dma_base_re[0:0] 1'0 + sync always + sync init + update \libresocsim_sdmem2block_dma_base_re $1\libresocsim_sdmem2block_dma_base_re[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:1514.12-1514.62" + process $proc$build/ls180/gateware/ls180.v:1514$3200 + assign { } { } + assign $1\libresocsim_sdmem2block_dma_length_storage[31:0] 0 + sync always + sync init + update \libresocsim_sdmem2block_dma_length_storage $1\libresocsim_sdmem2block_dma_length_storage[31:0] + end + attribute \src "build/ls180/gateware/ls180.v:1515.5-1515.49" + process $proc$build/ls180/gateware/ls180.v:1515$3201 + assign { } { } + assign $1\libresocsim_sdmem2block_dma_length_re[0:0] 1'0 + sync always + sync init + update \libresocsim_sdmem2block_dma_length_re $1\libresocsim_sdmem2block_dma_length_re[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:1516.5-1516.54" + process $proc$build/ls180/gateware/ls180.v:1516$3202 + assign { } { } + assign $1\libresocsim_sdmem2block_dma_enable_storage[0:0] 1'0 + sync always + sync init + update \libresocsim_sdmem2block_dma_enable_storage $1\libresocsim_sdmem2block_dma_enable_storage[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:1517.5-1517.49" + process $proc$build/ls180/gateware/ls180.v:1517$3203 + assign { } { } + assign $1\libresocsim_sdmem2block_dma_enable_re[0:0] 1'0 + sync always + sync init + update \libresocsim_sdmem2block_dma_enable_re $1\libresocsim_sdmem2block_dma_enable_re[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:1518.5-1518.51" + process $proc$build/ls180/gateware/ls180.v:1518$3204 + assign { } { } + assign $1\libresocsim_sdmem2block_dma_done_status[0:0] 1'0 + sync always + sync init + update \libresocsim_sdmem2block_dma_done_status $1\libresocsim_sdmem2block_dma_done_status[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:152.5-152.36" + process $proc$build/ls180/gateware/ls180.v:152$2615 + assign { } { } + assign $1\main_libresocsim_tx_busy[0:0] 1'0 + sync always + sync init + update \main_libresocsim_tx_busy $1\main_libresocsim_tx_busy[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:1520.5-1520.52" + process $proc$build/ls180/gateware/ls180.v:1520$3205 + assign { } { } + assign $1\libresocsim_sdmem2block_dma_loop_storage[0:0] 1'0 + sync always + sync init + update \libresocsim_sdmem2block_dma_loop_storage $1\libresocsim_sdmem2block_dma_loop_storage[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:1521.5-1521.47" + process $proc$build/ls180/gateware/ls180.v:1521$3206 + assign { } { } + assign $1\libresocsim_sdmem2block_dma_loop_re[0:0] 1'0 + sync always + sync init + update \libresocsim_sdmem2block_dma_loop_re $1\libresocsim_sdmem2block_dma_loop_re[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:1525.12-1525.54" + process $proc$build/ls180/gateware/ls180.v:1525$3207 + assign { } { } + assign $1\libresocsim_sdmem2block_dma_offset[31:0] 0 + sync always + sync init + update \libresocsim_sdmem2block_dma_offset $1\libresocsim_sdmem2block_dma_offset[31:0] + end + attribute \src "build/ls180/gateware/ls180.v:153.5-153.41" + process $proc$build/ls180/gateware/ls180.v:153$2616 + assign { } { } + assign $1\main_libresocsim_source_valid[0:0] 1'0 + sync always + sync init + update \main_libresocsim_source_valid $1\main_libresocsim_source_valid[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:1537.11-1537.71" + process $proc$build/ls180/gateware/ls180.v:1537$3208 + assign { } { } + assign $1\libresocsim_sdmem2block_converter_source_payload_data[7:0] 8'00000000 + sync always + sync init + update \libresocsim_sdmem2block_converter_source_payload_data $1\libresocsim_sdmem2block_converter_source_payload_data[7:0] + end + attribute \src "build/ls180/gateware/ls180.v:1539.11-1539.55" + process $proc$build/ls180/gateware/ls180.v:1539$3209 + assign { } { } + assign $1\libresocsim_sdmem2block_converter_mux[1:0] 2'00 + sync always + sync init + update \libresocsim_sdmem2block_converter_mux $1\libresocsim_sdmem2block_converter_mux[1:0] + end + attribute \src "build/ls180/gateware/ls180.v:155.5-155.41" + process $proc$build/ls180/gateware/ls180.v:155$2617 + assign { } { } + assign $0\main_libresocsim_source_first[0:0] 1'0 + sync always + update \main_libresocsim_source_first $0\main_libresocsim_source_first[0:0] + sync init + end + attribute \src "build/ls180/gateware/ls180.v:156.5-156.40" + process $proc$build/ls180/gateware/ls180.v:156$2618 + assign { } { } + assign $0\main_libresocsim_source_last[0:0] 1'0 + sync always + update \main_libresocsim_source_last $0\main_libresocsim_source_last[0:0] + sync init + end + attribute \src "build/ls180/gateware/ls180.v:1563.11-1563.52" + process $proc$build/ls180/gateware/ls180.v:1563$3210 + assign { } { } + assign $1\libresocsim_sdmem2block_fifo_level[5:0] 6'000000 + sync always + sync init + update \libresocsim_sdmem2block_fifo_level $1\libresocsim_sdmem2block_fifo_level[5:0] + end + attribute \src "build/ls180/gateware/ls180.v:1564.5-1564.48" + process $proc$build/ls180/gateware/ls180.v:1564$3211 + assign { } { } + assign $0\libresocsim_sdmem2block_fifo_replace[0:0] 1'0 + sync always + update \libresocsim_sdmem2block_fifo_replace $0\libresocsim_sdmem2block_fifo_replace[0:0] + sync init + end + attribute \src "build/ls180/gateware/ls180.v:1565.11-1565.54" + process $proc$build/ls180/gateware/ls180.v:1565$3212 + assign { } { } + assign $1\libresocsim_sdmem2block_fifo_produce[4:0] 5'00000 + sync always + sync init + update \libresocsim_sdmem2block_fifo_produce $1\libresocsim_sdmem2block_fifo_produce[4:0] + end + attribute \src "build/ls180/gateware/ls180.v:1566.11-1566.54" + process $proc$build/ls180/gateware/ls180.v:1566$3213 + assign { } { } + assign $1\libresocsim_sdmem2block_fifo_consume[4:0] 5'00000 + sync always + sync init + update \libresocsim_sdmem2block_fifo_consume $1\libresocsim_sdmem2block_fifo_consume[4:0] + end + attribute \src "build/ls180/gateware/ls180.v:1567.11-1567.57" + process $proc$build/ls180/gateware/ls180.v:1567$3214 + assign { } { } + assign $1\libresocsim_sdmem2block_fifo_wrport_adr[4:0] 5'00000 + sync always + sync init + update \libresocsim_sdmem2block_fifo_wrport_adr $1\libresocsim_sdmem2block_fifo_wrport_adr[4:0] + end + attribute \src "build/ls180/gateware/ls180.v:157.11-157.54" + process $proc$build/ls180/gateware/ls180.v:157$2619 + assign { } { } + assign $1\main_libresocsim_source_payload_data[7:0] 8'00000000 + sync always + sync init + update \main_libresocsim_source_payload_data $1\main_libresocsim_source_payload_data[7:0] + end + attribute \src "build/ls180/gateware/ls180.v:158.5-158.42" + process $proc$build/ls180/gateware/ls180.v:158$2620 + assign { } { } + assign $1\main_libresocsim_uart_clk_rxen[0:0] 1'0 + sync always + sync init + update \main_libresocsim_uart_clk_rxen $1\main_libresocsim_uart_clk_rxen[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:1582.5-1582.29" + process $proc$build/ls180/gateware/ls180.v:1582$3215 + assign { } { } + assign $1\libresocsim_done0[0:0] 1'0 + sync always + sync init + update \libresocsim_done0 $1\libresocsim_done0[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:1583.5-1583.27" + process $proc$build/ls180/gateware/ls180.v:1583$3216 + assign { } { } + assign $1\libresocsim_irq[0:0] 1'0 + sync always + sync init + update \libresocsim_irq $1\libresocsim_irq[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:1585.11-1585.34" + process $proc$build/ls180/gateware/ls180.v:1585$3217 + assign { } { } + assign $1\libresocsim_miso[7:0] 8'00000000 + sync always + sync init + update \libresocsim_miso $1\libresocsim_miso[7:0] + end + attribute \src "build/ls180/gateware/ls180.v:1589.5-1589.30" + process $proc$build/ls180/gateware/ls180.v:1589$3218 + assign { } { } + assign $1\libresocsim_start1[0:0] 1'0 + sync always + sync init + update \libresocsim_start1 $1\libresocsim_start1[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:159.12-159.57" + process $proc$build/ls180/gateware/ls180.v:159$2621 + assign { } { } + assign $1\main_libresocsim_phase_accumulator_rx[31:0] 0 + sync always + sync init + update \main_libresocsim_phase_accumulator_rx $1\main_libresocsim_phase_accumulator_rx[31:0] + end + attribute \src "build/ls180/gateware/ls180.v:1591.12-1591.47" + process $proc$build/ls180/gateware/ls180.v:1591$3219 + assign { } { } + assign $1\libresocsim_control_storage[15:0] 16'0000000000000000 + sync always + sync init + update \libresocsim_control_storage $1\libresocsim_control_storage[15:0] + end + attribute \src "build/ls180/gateware/ls180.v:1592.5-1592.34" + process $proc$build/ls180/gateware/ls180.v:1592$3220 + assign { } { } + assign $1\libresocsim_control_re[0:0] 1'0 + sync always + sync init + update \libresocsim_control_re $1\libresocsim_control_re[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:1596.11-1596.42" + process $proc$build/ls180/gateware/ls180.v:1596$3221 + assign { } { } + assign $1\libresocsim_mosi_storage[7:0] 8'00000000 + sync always + sync init + update \libresocsim_mosi_storage $1\libresocsim_mosi_storage[7:0] + end + attribute \src "build/ls180/gateware/ls180.v:1597.5-1597.31" + process $proc$build/ls180/gateware/ls180.v:1597$3222 + assign { } { } + assign $1\libresocsim_mosi_re[0:0] 1'0 + sync always + sync init + update \libresocsim_mosi_re $1\libresocsim_mosi_re[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:1601.5-1601.34" + process $proc$build/ls180/gateware/ls180.v:1601$3223 + assign { } { } + assign $1\libresocsim_cs_storage[0:0] 1'1 + sync always + sync init + update \libresocsim_cs_storage $1\libresocsim_cs_storage[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:1602.5-1602.29" + process $proc$build/ls180/gateware/ls180.v:1602$3224 + assign { } { } + assign $1\libresocsim_cs_re[0:0] 1'0 + sync always + sync init + update \libresocsim_cs_re $1\libresocsim_cs_re[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:1603.5-1603.40" + process $proc$build/ls180/gateware/ls180.v:1603$3225 + assign { } { } + assign $1\libresocsim_loopback_storage[0:0] 1'0 + sync always + sync init + update \libresocsim_loopback_storage $1\libresocsim_loopback_storage[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:1604.5-1604.35" + process $proc$build/ls180/gateware/ls180.v:1604$3226 + assign { } { } + assign $1\libresocsim_loopback_re[0:0] 1'0 + sync always + sync init + update \libresocsim_loopback_re $1\libresocsim_loopback_re[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:1605.5-1605.34" + process $proc$build/ls180/gateware/ls180.v:1605$3227 + assign { } { } + assign $1\libresocsim_clk_enable[0:0] 1'0 + sync always + sync init + update \libresocsim_clk_enable $1\libresocsim_clk_enable[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:1606.5-1606.33" + process $proc$build/ls180/gateware/ls180.v:1606$3228 + assign { } { } + assign $1\libresocsim_cs_enable[0:0] 1'0 + sync always + sync init + update \libresocsim_cs_enable $1\libresocsim_cs_enable[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:1607.11-1607.35" + process $proc$build/ls180/gateware/ls180.v:1607$3229 + assign { } { } + assign $1\libresocsim_count[2:0] 3'000 + sync always + sync init + update \libresocsim_count $1\libresocsim_count[2:0] + end + attribute \src "build/ls180/gateware/ls180.v:1608.5-1608.34" + process $proc$build/ls180/gateware/ls180.v:1608$3230 + assign { } { } + assign $1\libresocsim_mosi_latch[0:0] 1'0 + sync always + sync init + update \libresocsim_mosi_latch $1\libresocsim_mosi_latch[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:1609.5-1609.34" + process $proc$build/ls180/gateware/ls180.v:1609$3231 + assign { } { } + assign $1\libresocsim_miso_latch[0:0] 1'0 + sync always + sync init + update \libresocsim_miso_latch $1\libresocsim_miso_latch[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:161.5-161.33" + process $proc$build/ls180/gateware/ls180.v:161$2622 + assign { } { } + assign $1\main_libresocsim_rx_r[0:0] 1'0 + sync always + sync init + update \main_libresocsim_rx_r $1\main_libresocsim_rx_r[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:1610.12-1610.44" + process $proc$build/ls180/gateware/ls180.v:1610$3232 + assign { } { } + assign $1\libresocsim_clk_divider1[15:0] 16'0000000000000000 + sync always + sync init + update \libresocsim_clk_divider1 $1\libresocsim_clk_divider1[15:0] + end + attribute \src "build/ls180/gateware/ls180.v:1613.11-1613.39" + process $proc$build/ls180/gateware/ls180.v:1613$3233 + assign { } { } + assign $1\libresocsim_mosi_data[7:0] 8'00000000 + sync always + sync init + update \libresocsim_mosi_data $1\libresocsim_mosi_data[7:0] + end + attribute \src "build/ls180/gateware/ls180.v:1614.11-1614.38" + process $proc$build/ls180/gateware/ls180.v:1614$3234 + assign { } { } + assign $1\libresocsim_mosi_sel[2:0] 3'000 + sync always + sync init + update \libresocsim_mosi_sel $1\libresocsim_mosi_sel[2:0] + end + attribute \src "build/ls180/gateware/ls180.v:1615.11-1615.39" + process $proc$build/ls180/gateware/ls180.v:1615$3235 + assign { } { } + assign $1\libresocsim_miso_data[7:0] 8'00000000 + sync always + sync init + update \libresocsim_miso_data $1\libresocsim_miso_data[7:0] + end + attribute \src "build/ls180/gateware/ls180.v:1616.12-1616.41" + process $proc$build/ls180/gateware/ls180.v:1616$3236 + assign { } { } + assign $1\libresocsim_storage[15:0] 16'0000000001111101 + sync always + sync init + update \libresocsim_storage $1\libresocsim_storage[15:0] + end + attribute \src "build/ls180/gateware/ls180.v:1617.5-1617.26" + process $proc$build/ls180/gateware/ls180.v:1617$3237 + assign { } { } + assign $1\libresocsim_re[0:0] 1'0 + sync always + sync init + update \libresocsim_re $1\libresocsim_re[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:1618.5-1618.36" + process $proc$build/ls180/gateware/ls180.v:1618$3238 + assign { } { } + assign $1\builder_converter0_state[0:0] 1'0 + sync always + sync init + update \builder_converter0_state $1\builder_converter0_state[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:1619.5-1619.41" + process $proc$build/ls180/gateware/ls180.v:1619$3239 + assign { } { } + assign $1\builder_converter0_next_state[0:0] 1'0 + sync always + sync init + update \builder_converter0_next_state $1\builder_converter0_next_state[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:162.11-162.41" + process $proc$build/ls180/gateware/ls180.v:162$2623 + assign { } { } + assign $1\main_libresocsim_rx_reg[7:0] 8'00000000 + sync always + sync init + update \main_libresocsim_rx_reg $1\main_libresocsim_rx_reg[7:0] + end + attribute \src "build/ls180/gateware/ls180.v:1620.5-1620.69" + process $proc$build/ls180/gateware/ls180.v:1620$3240 + assign { } { } + assign $1\main_libresocsim_converter0_counter_converter0_next_value[0:0] 1'0 + sync always + sync init + update \main_libresocsim_converter0_counter_converter0_next_value $1\main_libresocsim_converter0_counter_converter0_next_value[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:1621.5-1621.72" + process $proc$build/ls180/gateware/ls180.v:1621$3241 + assign { } { } + assign $1\main_libresocsim_converter0_counter_converter0_next_value_ce[0:0] 1'0 + sync always + sync init + update \main_libresocsim_converter0_counter_converter0_next_value_ce $1\main_libresocsim_converter0_counter_converter0_next_value_ce[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:1622.5-1622.36" + process $proc$build/ls180/gateware/ls180.v:1622$3242 + assign { } { } + assign $1\builder_converter1_state[0:0] 1'0 + sync always + sync init + update \builder_converter1_state $1\builder_converter1_state[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:1623.5-1623.41" + process $proc$build/ls180/gateware/ls180.v:1623$3243 + assign { } { } + assign $1\builder_converter1_next_state[0:0] 1'0 + sync always + sync init + update \builder_converter1_next_state $1\builder_converter1_next_state[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:1624.5-1624.69" + process $proc$build/ls180/gateware/ls180.v:1624$3244 + assign { } { } + assign $1\main_libresocsim_converter1_counter_converter1_next_value[0:0] 1'0 + sync always + sync init + update \main_libresocsim_converter1_counter_converter1_next_value $1\main_libresocsim_converter1_counter_converter1_next_value[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:1625.5-1625.72" + process $proc$build/ls180/gateware/ls180.v:1625$3245 + assign { } { } + assign $1\main_libresocsim_converter1_counter_converter1_next_value_ce[0:0] 1'0 + sync always + sync init + update \main_libresocsim_converter1_counter_converter1_next_value_ce $1\main_libresocsim_converter1_counter_converter1_next_value_ce[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:1626.11-1626.41" + process $proc$build/ls180/gateware/ls180.v:1626$3246 + assign { } { } + assign $1\builder_refresher_state[1:0] 2'00 + sync always + sync init + update \builder_refresher_state $1\builder_refresher_state[1:0] + end + attribute \src "build/ls180/gateware/ls180.v:1627.11-1627.46" + process $proc$build/ls180/gateware/ls180.v:1627$3247 + assign { } { } + assign $1\builder_refresher_next_state[1:0] 2'00 + sync always + sync init + update \builder_refresher_next_state $1\builder_refresher_next_state[1:0] + end + attribute \src "build/ls180/gateware/ls180.v:1628.11-1628.44" + process $proc$build/ls180/gateware/ls180.v:1628$3248 + assign { } { } + assign $1\builder_bankmachine0_state[2:0] 3'000 + sync always + sync init + update \builder_bankmachine0_state $1\builder_bankmachine0_state[2:0] + end + attribute \src "build/ls180/gateware/ls180.v:1629.11-1629.49" + process $proc$build/ls180/gateware/ls180.v:1629$3249 + assign { } { } + assign $1\builder_bankmachine0_next_state[2:0] 3'000 + sync always + sync init + update \builder_bankmachine0_next_state $1\builder_bankmachine0_next_state[2:0] + end + attribute \src "build/ls180/gateware/ls180.v:163.11-163.46" + process $proc$build/ls180/gateware/ls180.v:163$2624 + assign { } { } + assign $1\main_libresocsim_rx_bitcount[3:0] 4'0000 + sync always + sync init + update \main_libresocsim_rx_bitcount $1\main_libresocsim_rx_bitcount[3:0] + end + attribute \src "build/ls180/gateware/ls180.v:1630.11-1630.44" + process $proc$build/ls180/gateware/ls180.v:1630$3250 + assign { } { } + assign $1\builder_bankmachine1_state[2:0] 3'000 + sync always + sync init + update \builder_bankmachine1_state $1\builder_bankmachine1_state[2:0] + end + attribute \src "build/ls180/gateware/ls180.v:1631.11-1631.49" + process $proc$build/ls180/gateware/ls180.v:1631$3251 + assign { } { } + assign $1\builder_bankmachine1_next_state[2:0] 3'000 + sync always + sync init + update \builder_bankmachine1_next_state $1\builder_bankmachine1_next_state[2:0] + end + attribute \src "build/ls180/gateware/ls180.v:1632.11-1632.44" + process $proc$build/ls180/gateware/ls180.v:1632$3252 + assign { } { } + assign $1\builder_bankmachine2_state[2:0] 3'000 + sync always + sync init + update \builder_bankmachine2_state $1\builder_bankmachine2_state[2:0] + end + attribute \src "build/ls180/gateware/ls180.v:1633.11-1633.49" + process $proc$build/ls180/gateware/ls180.v:1633$3253 + assign { } { } + assign $1\builder_bankmachine2_next_state[2:0] 3'000 + sync always + sync init + update \builder_bankmachine2_next_state $1\builder_bankmachine2_next_state[2:0] + end + attribute \src "build/ls180/gateware/ls180.v:1634.11-1634.44" + process $proc$build/ls180/gateware/ls180.v:1634$3254 + assign { } { } + assign $1\builder_bankmachine3_state[2:0] 3'000 + sync always + sync init + update \builder_bankmachine3_state $1\builder_bankmachine3_state[2:0] + end + attribute \src "build/ls180/gateware/ls180.v:1635.11-1635.49" + process $proc$build/ls180/gateware/ls180.v:1635$3255 + assign { } { } + assign $1\builder_bankmachine3_next_state[2:0] 3'000 + sync always + sync init + update \builder_bankmachine3_next_state $1\builder_bankmachine3_next_state[2:0] + end + attribute \src "build/ls180/gateware/ls180.v:1636.11-1636.43" + process $proc$build/ls180/gateware/ls180.v:1636$3256 + assign { } { } + assign $1\builder_multiplexer_state[2:0] 3'000 + sync always + sync init + update \builder_multiplexer_state $1\builder_multiplexer_state[2:0] + end + attribute \src "build/ls180/gateware/ls180.v:1637.11-1637.48" + process $proc$build/ls180/gateware/ls180.v:1637$3257 + assign { } { } + assign $1\builder_multiplexer_next_state[2:0] 3'000 + sync always + sync init + update \builder_multiplexer_next_state $1\builder_multiplexer_next_state[2:0] + end + attribute \src "build/ls180/gateware/ls180.v:164.5-164.36" + process $proc$build/ls180/gateware/ls180.v:164$2625 + assign { } { } + assign $1\main_libresocsim_rx_busy[0:0] 1'0 + sync always + sync init + update \main_libresocsim_rx_busy $1\main_libresocsim_rx_busy[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:1650.5-1650.27" + process $proc$build/ls180/gateware/ls180.v:1650$3258 + assign { } { } + assign $0\builder_locked0[0:0] 1'0 + sync always + update \builder_locked0 $0\builder_locked0[0:0] + sync init + end + attribute \src "build/ls180/gateware/ls180.v:1651.5-1651.27" + process $proc$build/ls180/gateware/ls180.v:1651$3259 + assign { } { } + assign $0\builder_locked1[0:0] 1'0 + sync always + update \builder_locked1 $0\builder_locked1[0:0] + sync init + end + attribute \src "build/ls180/gateware/ls180.v:1652.5-1652.27" + process $proc$build/ls180/gateware/ls180.v:1652$3260 + assign { } { } + assign $0\builder_locked2[0:0] 1'0 + sync always + update \builder_locked2 $0\builder_locked2[0:0] + sync init + end + attribute \src "build/ls180/gateware/ls180.v:1653.5-1653.27" + process $proc$build/ls180/gateware/ls180.v:1653$3261 + assign { } { } + assign $0\builder_locked3[0:0] 1'0 + sync always + update \builder_locked3 $0\builder_locked3[0:0] + sync init + end + attribute \src "build/ls180/gateware/ls180.v:1654.5-1654.42" + process $proc$build/ls180/gateware/ls180.v:1654$3262 + assign { } { } + assign $1\builder_new_master_wdata_ready[0:0] 1'0 + sync always + sync init + update \builder_new_master_wdata_ready $1\builder_new_master_wdata_ready[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:1655.5-1655.43" + process $proc$build/ls180/gateware/ls180.v:1655$3263 + assign { } { } + assign $1\builder_new_master_rdata_valid0[0:0] 1'0 + sync always + sync init + update \builder_new_master_rdata_valid0 $1\builder_new_master_rdata_valid0[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:1656.5-1656.43" + process $proc$build/ls180/gateware/ls180.v:1656$3264 + assign { } { } + assign $1\builder_new_master_rdata_valid1[0:0] 1'0 + sync always + sync init + update \builder_new_master_rdata_valid1 $1\builder_new_master_rdata_valid1[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:1657.5-1657.43" + process $proc$build/ls180/gateware/ls180.v:1657$3265 + assign { } { } + assign $1\builder_new_master_rdata_valid2[0:0] 1'0 + sync always + sync init + update \builder_new_master_rdata_valid2 $1\builder_new_master_rdata_valid2[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:1658.5-1658.43" + process $proc$build/ls180/gateware/ls180.v:1658$3266 + assign { } { } + assign $1\builder_new_master_rdata_valid3[0:0] 1'0 + sync always + sync init + update \builder_new_master_rdata_valid3 $1\builder_new_master_rdata_valid3[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:1659.5-1659.35" + process $proc$build/ls180/gateware/ls180.v:1659$3267 + assign { } { } + assign $1\builder_converter_state[0:0] 1'0 + sync always + sync init + update \builder_converter_state $1\builder_converter_state[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:1660.5-1660.40" + process $proc$build/ls180/gateware/ls180.v:1660$3268 + assign { } { } + assign $1\builder_converter_next_state[0:0] 1'0 + sync always + sync init + update \builder_converter_next_state $1\builder_converter_next_state[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:1661.5-1661.55" + process $proc$build/ls180/gateware/ls180.v:1661$3269 + assign { } { } + assign $1\main_converter_counter_converter_next_value[0:0] 1'0 + sync always + sync init + update \main_converter_counter_converter_next_value $1\main_converter_counter_converter_next_value[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:1662.5-1662.58" + process $proc$build/ls180/gateware/ls180.v:1662$3270 + assign { } { } + assign $1\main_converter_counter_converter_next_value_ce[0:0] 1'0 + sync always + sync init + update \main_converter_counter_converter_next_value_ce $1\main_converter_counter_converter_next_value_ce[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:1663.11-1663.42" + process $proc$build/ls180/gateware/ls180.v:1663$3271 + assign { } { } + assign $1\builder_spimaster0_state[1:0] 2'00 + sync always + sync init + update \builder_spimaster0_state $1\builder_spimaster0_state[1:0] + end + attribute \src "build/ls180/gateware/ls180.v:1664.11-1664.47" + process $proc$build/ls180/gateware/ls180.v:1664$3272 + assign { } { } + assign $1\builder_spimaster0_next_state[1:0] 2'00 + sync always + sync init + update \builder_spimaster0_next_state $1\builder_spimaster0_next_state[1:0] + end + attribute \src "build/ls180/gateware/ls180.v:1665.11-1665.50" + process $proc$build/ls180/gateware/ls180.v:1665$3273 + assign { } { } + assign $1\main_count_spimaster0_next_value[2:0] 3'000 + sync always + sync init + update \main_count_spimaster0_next_value $1\main_count_spimaster0_next_value[2:0] + end + attribute \src "build/ls180/gateware/ls180.v:1666.5-1666.47" + process $proc$build/ls180/gateware/ls180.v:1666$3274 + assign { } { } + assign $1\main_count_spimaster0_next_value_ce[0:0] 1'0 + sync always + sync init + update \main_count_spimaster0_next_value_ce $1\main_count_spimaster0_next_value_ce[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:1667.5-1667.41" + process $proc$build/ls180/gateware/ls180.v:1667$3275 + assign { } { } + assign $1\builder_sdphy_sdphyinit_state[0:0] 1'0 + sync always + sync init + update \builder_sdphy_sdphyinit_state $1\builder_sdphy_sdphyinit_state[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:1668.5-1668.46" + process $proc$build/ls180/gateware/ls180.v:1668$3276 + assign { } { } + assign $1\builder_sdphy_sdphyinit_next_state[0:0] 1'0 + sync always + sync init + update \builder_sdphy_sdphyinit_next_state $1\builder_sdphy_sdphyinit_next_state[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:1669.11-1669.67" + process $proc$build/ls180/gateware/ls180.v:1669$3277 + assign { } { } + assign $1\libresocsim_init_count_sdphy_sdphyinit_next_value[7:0] 8'00000000 + sync always + sync init + update \libresocsim_init_count_sdphy_sdphyinit_next_value $1\libresocsim_init_count_sdphy_sdphyinit_next_value[7:0] + end + attribute \src "build/ls180/gateware/ls180.v:1670.5-1670.64" + process $proc$build/ls180/gateware/ls180.v:1670$3278 + assign { } { } + assign $1\libresocsim_init_count_sdphy_sdphyinit_next_value_ce[0:0] 1'0 + sync always + sync init + update \libresocsim_init_count_sdphy_sdphyinit_next_value_ce $1\libresocsim_init_count_sdphy_sdphyinit_next_value_ce[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:1671.11-1671.47" + process $proc$build/ls180/gateware/ls180.v:1671$3279 + assign { } { } + assign $1\builder_sdphy_sdphycmdw_state[1:0] 2'00 + sync always + sync init + update \builder_sdphy_sdphycmdw_state $1\builder_sdphy_sdphycmdw_state[1:0] + end + attribute \src "build/ls180/gateware/ls180.v:1672.11-1672.52" + process $proc$build/ls180/gateware/ls180.v:1672$3280 + assign { } { } + assign $1\builder_sdphy_sdphycmdw_next_state[1:0] 2'00 + sync always + sync init + update \builder_sdphy_sdphycmdw_next_state $1\builder_sdphy_sdphycmdw_next_state[1:0] + end + attribute \src "build/ls180/gateware/ls180.v:1673.11-1673.67" + process $proc$build/ls180/gateware/ls180.v:1673$3281 + assign { } { } + assign $1\libresocsim_cmdw_count_sdphy_sdphycmdw_next_value[7:0] 8'00000000 + sync always + sync init + update \libresocsim_cmdw_count_sdphy_sdphycmdw_next_value $1\libresocsim_cmdw_count_sdphy_sdphycmdw_next_value[7:0] + end + attribute \src "build/ls180/gateware/ls180.v:1674.5-1674.64" + process $proc$build/ls180/gateware/ls180.v:1674$3282 + assign { } { } + assign $1\libresocsim_cmdw_count_sdphy_sdphycmdw_next_value_ce[0:0] 1'0 + sync always + sync init + update \libresocsim_cmdw_count_sdphy_sdphycmdw_next_value_ce $1\libresocsim_cmdw_count_sdphy_sdphycmdw_next_value_ce[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:1675.11-1675.47" + process $proc$build/ls180/gateware/ls180.v:1675$3283 + assign { } { } + assign $1\builder_sdphy_sdphycmdr_state[2:0] 3'000 + sync always + sync init + update \builder_sdphy_sdphycmdr_state $1\builder_sdphy_sdphycmdr_state[2:0] + end + attribute \src "build/ls180/gateware/ls180.v:1676.11-1676.52" + process $proc$build/ls180/gateware/ls180.v:1676$3284 + assign { } { } + assign $1\builder_sdphy_sdphycmdr_next_state[2:0] 3'000 + sync always + sync init + update \builder_sdphy_sdphycmdr_next_state $1\builder_sdphy_sdphycmdr_next_state[2:0] + end + attribute \src "build/ls180/gateware/ls180.v:1677.11-1677.68" + process $proc$build/ls180/gateware/ls180.v:1677$3285 + assign { } { } + assign $1\libresocsim_cmdr_count_sdphy_sdphycmdr_next_value0[7:0] 8'00000000 + sync always + sync init + update \libresocsim_cmdr_count_sdphy_sdphycmdr_next_value0 $1\libresocsim_cmdr_count_sdphy_sdphycmdr_next_value0[7:0] + end + attribute \src "build/ls180/gateware/ls180.v:1678.5-1678.65" + process $proc$build/ls180/gateware/ls180.v:1678$3286 + assign { } { } + assign $1\libresocsim_cmdr_count_sdphy_sdphycmdr_next_value_ce0[0:0] 1'0 + sync always + sync init + update \libresocsim_cmdr_count_sdphy_sdphycmdr_next_value_ce0 $1\libresocsim_cmdr_count_sdphy_sdphycmdr_next_value_ce0[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:1679.12-1679.72" + process $proc$build/ls180/gateware/ls180.v:1679$3287 + assign { } { } + assign $1\libresocsim_cmdr_timeout_sdphy_sdphycmdr_next_value1[31:0] 0 + sync always + sync init + update \libresocsim_cmdr_timeout_sdphy_sdphycmdr_next_value1 $1\libresocsim_cmdr_timeout_sdphy_sdphycmdr_next_value1[31:0] + end + attribute \src "build/ls180/gateware/ls180.v:1680.5-1680.67" + process $proc$build/ls180/gateware/ls180.v:1680$3288 + assign { } { } + assign $1\libresocsim_cmdr_timeout_sdphy_sdphycmdr_next_value_ce1[0:0] 1'0 + sync always + sync init + update \libresocsim_cmdr_timeout_sdphy_sdphycmdr_next_value_ce1 $1\libresocsim_cmdr_timeout_sdphy_sdphycmdr_next_value_ce1[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:1681.5-1681.67" + process $proc$build/ls180/gateware/ls180.v:1681$3289 + assign { } { } + assign $1\libresocsim_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value2[0:0] 1'0 + sync always + sync init + update \libresocsim_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value2 $1\libresocsim_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value2[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:1682.5-1682.70" + process $proc$build/ls180/gateware/ls180.v:1682$3290 + assign { } { } + assign $1\libresocsim_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value_ce2[0:0] 1'0 + sync always + sync init + update \libresocsim_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value_ce2 $1\libresocsim_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value_ce2[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:1683.5-1683.41" + process $proc$build/ls180/gateware/ls180.v:1683$3291 + assign { } { } + assign $1\builder_sdphy_sdphycrcr_state[0:0] 1'0 + sync always + sync init + update \builder_sdphy_sdphycrcr_state $1\builder_sdphy_sdphycrcr_state[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:1684.5-1684.46" + process $proc$build/ls180/gateware/ls180.v:1684$3292 + assign { } { } + assign $1\builder_sdphy_sdphycrcr_next_state[0:0] 1'0 + sync always + sync init + update \builder_sdphy_sdphycrcr_next_state $1\builder_sdphy_sdphycrcr_next_state[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:1685.5-1685.67" + process $proc$build/ls180/gateware/ls180.v:1685$3293 + assign { } { } + assign $1\libresocsim_dataw_crcr_reset_sdphy_sdphycrcr_next_value[0:0] 1'0 + sync always + sync init + update \libresocsim_dataw_crcr_reset_sdphy_sdphycrcr_next_value $1\libresocsim_dataw_crcr_reset_sdphy_sdphycrcr_next_value[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:1686.5-1686.70" + process $proc$build/ls180/gateware/ls180.v:1686$3294 + assign { } { } + assign $1\libresocsim_dataw_crcr_reset_sdphy_sdphycrcr_next_value_ce[0:0] 1'0 + sync always + sync init + update \libresocsim_dataw_crcr_reset_sdphy_sdphycrcr_next_value_ce $1\libresocsim_dataw_crcr_reset_sdphy_sdphycrcr_next_value_ce[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:1687.11-1687.41" + process $proc$build/ls180/gateware/ls180.v:1687$3295 + assign { } { } + assign $1\builder_sdphy_fsm_state[2:0] 3'000 + sync always + sync init + update \builder_sdphy_fsm_state $1\builder_sdphy_fsm_state[2:0] + end + attribute \src "build/ls180/gateware/ls180.v:1688.11-1688.46" + process $proc$build/ls180/gateware/ls180.v:1688$3296 + assign { } { } + assign $1\builder_sdphy_fsm_next_state[2:0] 3'000 + sync always + sync init + update \builder_sdphy_fsm_next_state $1\builder_sdphy_fsm_next_state[2:0] + end + attribute \src "build/ls180/gateware/ls180.v:1689.11-1689.62" + process $proc$build/ls180/gateware/ls180.v:1689$3297 + assign { } { } + assign $1\libresocsim_dataw_count_sdphy_fsm_next_value[7:0] 8'00000000 + sync always + sync init + update \libresocsim_dataw_count_sdphy_fsm_next_value $1\libresocsim_dataw_count_sdphy_fsm_next_value[7:0] + end + attribute \src "build/ls180/gateware/ls180.v:1690.5-1690.59" + process $proc$build/ls180/gateware/ls180.v:1690$3298 + assign { } { } + assign $1\libresocsim_dataw_count_sdphy_fsm_next_value_ce[0:0] 1'0 + sync always + sync init + update \libresocsim_dataw_count_sdphy_fsm_next_value_ce $1\libresocsim_dataw_count_sdphy_fsm_next_value_ce[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:1691.11-1691.48" + process $proc$build/ls180/gateware/ls180.v:1691$3299 + assign { } { } + assign $1\builder_sdphy_sdphydatar_state[2:0] 3'000 + sync always + sync init + update \builder_sdphy_sdphydatar_state $1\builder_sdphy_sdphydatar_state[2:0] + end + attribute \src "build/ls180/gateware/ls180.v:1692.11-1692.53" + process $proc$build/ls180/gateware/ls180.v:1692$3300 + assign { } { } + assign $1\builder_sdphy_sdphydatar_next_state[2:0] 3'000 + sync always + sync init + update \builder_sdphy_sdphydatar_next_state $1\builder_sdphy_sdphydatar_next_state[2:0] + end + attribute \src "build/ls180/gateware/ls180.v:1693.11-1693.71" + process $proc$build/ls180/gateware/ls180.v:1693$3301 + assign { } { } + assign $1\libresocsim_datar_count_sdphy_sdphydatar_next_value0[9:0] 10'0000000000 + sync always + sync init + update \libresocsim_datar_count_sdphy_sdphydatar_next_value0 $1\libresocsim_datar_count_sdphy_sdphydatar_next_value0[9:0] + end + attribute \src "build/ls180/gateware/ls180.v:1694.5-1694.67" + process $proc$build/ls180/gateware/ls180.v:1694$3302 + assign { } { } + assign $1\libresocsim_datar_count_sdphy_sdphydatar_next_value_ce0[0:0] 1'0 + sync always + sync init + update \libresocsim_datar_count_sdphy_sdphydatar_next_value_ce0 $1\libresocsim_datar_count_sdphy_sdphydatar_next_value_ce0[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:1695.12-1695.74" + process $proc$build/ls180/gateware/ls180.v:1695$3303 + assign { } { } + assign $1\libresocsim_datar_timeout_sdphy_sdphydatar_next_value1[31:0] 0 + sync always + sync init + update \libresocsim_datar_timeout_sdphy_sdphydatar_next_value1 $1\libresocsim_datar_timeout_sdphy_sdphydatar_next_value1[31:0] + end + attribute \src "build/ls180/gateware/ls180.v:1696.5-1696.69" + process $proc$build/ls180/gateware/ls180.v:1696$3304 + assign { } { } + assign $1\libresocsim_datar_timeout_sdphy_sdphydatar_next_value_ce1[0:0] 1'0 + sync always + sync init + update \libresocsim_datar_timeout_sdphy_sdphydatar_next_value_ce1 $1\libresocsim_datar_timeout_sdphy_sdphydatar_next_value_ce1[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:1697.5-1697.70" + process $proc$build/ls180/gateware/ls180.v:1697$3305 + assign { } { } + assign $1\libresocsim_datar_datar_reset_sdphy_sdphydatar_next_value2[0:0] 1'0 + sync always + sync init + update \libresocsim_datar_datar_reset_sdphy_sdphydatar_next_value2 $1\libresocsim_datar_datar_reset_sdphy_sdphydatar_next_value2[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:1698.5-1698.73" + process $proc$build/ls180/gateware/ls180.v:1698$3306 + assign { } { } + assign $1\libresocsim_datar_datar_reset_sdphy_sdphydatar_next_value_ce2[0:0] 1'0 + sync always + sync init + update \libresocsim_datar_datar_reset_sdphy_sdphydatar_next_value_ce2 $1\libresocsim_datar_datar_reset_sdphy_sdphydatar_next_value_ce2[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:1699.5-1699.52" + process $proc$build/ls180/gateware/ls180.v:1699$3307 + assign { } { } + assign $1\builder_sdcore_crcupstreaminserter_state[0:0] 1'0 + sync always + sync init + update \builder_sdcore_crcupstreaminserter_state $1\builder_sdcore_crcupstreaminserter_state[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:1700.5-1700.57" + process $proc$build/ls180/gateware/ls180.v:1700$3308 + assign { } { } + assign $1\builder_sdcore_crcupstreaminserter_next_state[0:0] 1'0 + sync always + sync init + update \builder_sdcore_crcupstreaminserter_next_state $1\builder_sdcore_crcupstreaminserter_next_state[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:1701.12-1701.100" + process $proc$build/ls180/gateware/ls180.v:1701$3309 + assign { } { } + assign $1\libresocsim_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value0[15:0] 16'0000000000000000 + sync always + sync init + update \libresocsim_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value0 $1\libresocsim_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value0[15:0] + end + attribute \src "build/ls180/gateware/ls180.v:1702.5-1702.95" + process $proc$build/ls180/gateware/ls180.v:1702$3310 + assign { } { } + assign $1\libresocsim_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value_ce0[0:0] 1'0 + sync always + sync init + update \libresocsim_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value_ce0 $1\libresocsim_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value_ce0[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:1703.12-1703.100" + process $proc$build/ls180/gateware/ls180.v:1703$3311 + assign { } { } + assign $1\libresocsim_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value1[15:0] 16'0000000000000000 + sync always + sync init + update \libresocsim_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value1 $1\libresocsim_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value1[15:0] + end + attribute \src "build/ls180/gateware/ls180.v:1704.5-1704.95" + process $proc$build/ls180/gateware/ls180.v:1704$3312 + assign { } { } + assign $1\libresocsim_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value_ce1[0:0] 1'0 + sync always + sync init + update \libresocsim_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value_ce1 $1\libresocsim_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value_ce1[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:1705.12-1705.100" + process $proc$build/ls180/gateware/ls180.v:1705$3313 + assign { } { } + assign $1\libresocsim_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value2[15:0] 16'0000000000000000 + sync always + sync init + update \libresocsim_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value2 $1\libresocsim_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value2[15:0] + end + attribute \src "build/ls180/gateware/ls180.v:1706.5-1706.95" + process $proc$build/ls180/gateware/ls180.v:1706$3314 + assign { } { } + assign $1\libresocsim_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value_ce2[0:0] 1'0 + sync always + sync init + update \libresocsim_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value_ce2 $1\libresocsim_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value_ce2[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:1707.12-1707.100" + process $proc$build/ls180/gateware/ls180.v:1707$3315 + assign { } { } + assign $1\libresocsim_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value3[15:0] 16'0000000000000000 + sync always + sync init + update \libresocsim_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value3 $1\libresocsim_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value3[15:0] + end + attribute \src "build/ls180/gateware/ls180.v:1708.5-1708.95" + process $proc$build/ls180/gateware/ls180.v:1708$3316 + assign { } { } + assign $1\libresocsim_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value_ce3[0:0] 1'0 + sync always + sync init + update \libresocsim_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value_ce3 $1\libresocsim_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value_ce3[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:1709.11-1709.94" + process $proc$build/ls180/gateware/ls180.v:1709$3317 + assign { } { } + assign $1\libresocsim_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value4[2:0] 3'000 + sync always + sync init + update \libresocsim_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value4 $1\libresocsim_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value4[2:0] + end + attribute \src "build/ls180/gateware/ls180.v:1710.5-1710.91" + process $proc$build/ls180/gateware/ls180.v:1710$3318 + assign { } { } + assign $1\libresocsim_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value_ce4[0:0] 1'0 + sync always + sync init + update \libresocsim_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value_ce4 $1\libresocsim_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value_ce4[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:1711.11-1711.42" + process $proc$build/ls180/gateware/ls180.v:1711$3319 + assign { } { } + assign $1\builder_sdcore_fsm_state[2:0] 3'000 + sync always + sync init + update \builder_sdcore_fsm_state $1\builder_sdcore_fsm_state[2:0] + end + attribute \src "build/ls180/gateware/ls180.v:1712.11-1712.47" + process $proc$build/ls180/gateware/ls180.v:1712$3320 + assign { } { } + assign $1\builder_sdcore_fsm_next_state[2:0] 3'000 + sync always + sync init + update \builder_sdcore_fsm_next_state $1\builder_sdcore_fsm_next_state[2:0] + end + attribute \src "build/ls180/gateware/ls180.v:1713.5-1713.62" + process $proc$build/ls180/gateware/ls180.v:1713$3321 + assign { } { } + assign $1\libresocsim_sdcore_cmd_done_sdcore_fsm_next_value0[0:0] 1'0 + sync always + sync init + update \libresocsim_sdcore_cmd_done_sdcore_fsm_next_value0 $1\libresocsim_sdcore_cmd_done_sdcore_fsm_next_value0[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:1714.5-1714.65" + process $proc$build/ls180/gateware/ls180.v:1714$3322 + assign { } { } + assign $1\libresocsim_sdcore_cmd_done_sdcore_fsm_next_value_ce0[0:0] 1'0 + sync always + sync init + update \libresocsim_sdcore_cmd_done_sdcore_fsm_next_value_ce0 $1\libresocsim_sdcore_cmd_done_sdcore_fsm_next_value_ce0[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:1715.5-1715.63" + process $proc$build/ls180/gateware/ls180.v:1715$3323 + assign { } { } + assign $1\libresocsim_sdcore_data_done_sdcore_fsm_next_value1[0:0] 1'0 + sync always + sync init + update \libresocsim_sdcore_data_done_sdcore_fsm_next_value1 $1\libresocsim_sdcore_data_done_sdcore_fsm_next_value1[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:1716.5-1716.66" + process $proc$build/ls180/gateware/ls180.v:1716$3324 + assign { } { } + assign $1\libresocsim_sdcore_data_done_sdcore_fsm_next_value_ce1[0:0] 1'0 + sync always + sync init + update \libresocsim_sdcore_data_done_sdcore_fsm_next_value_ce1 $1\libresocsim_sdcore_data_done_sdcore_fsm_next_value_ce1[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:1717.11-1717.69" + process $proc$build/ls180/gateware/ls180.v:1717$3325 + assign { } { } + assign $1\libresocsim_sdcore_cmd_count_sdcore_fsm_next_value2[2:0] 3'000 + sync always + sync init + update \libresocsim_sdcore_cmd_count_sdcore_fsm_next_value2 $1\libresocsim_sdcore_cmd_count_sdcore_fsm_next_value2[2:0] + end + attribute \src "build/ls180/gateware/ls180.v:1718.5-1718.66" + process $proc$build/ls180/gateware/ls180.v:1718$3326 + assign { } { } + assign $1\libresocsim_sdcore_cmd_count_sdcore_fsm_next_value_ce2[0:0] 1'0 + sync always + sync init + update \libresocsim_sdcore_cmd_count_sdcore_fsm_next_value_ce2 $1\libresocsim_sdcore_cmd_count_sdcore_fsm_next_value_ce2[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:1719.12-1719.72" + process $proc$build/ls180/gateware/ls180.v:1719$3327 + assign { } { } + assign $1\libresocsim_sdcore_data_count_sdcore_fsm_next_value3[31:0] 0 + sync always + sync init + update \libresocsim_sdcore_data_count_sdcore_fsm_next_value3 $1\libresocsim_sdcore_data_count_sdcore_fsm_next_value3[31:0] + end + attribute \src "build/ls180/gateware/ls180.v:1720.5-1720.67" + process $proc$build/ls180/gateware/ls180.v:1720$3328 + assign { } { } + assign $1\libresocsim_sdcore_data_count_sdcore_fsm_next_value_ce3[0:0] 1'0 + sync always + sync init + update \libresocsim_sdcore_data_count_sdcore_fsm_next_value_ce3 $1\libresocsim_sdcore_data_count_sdcore_fsm_next_value_ce3[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:1721.5-1721.63" + process $proc$build/ls180/gateware/ls180.v:1721$3329 + assign { } { } + assign $1\libresocsim_sdcore_cmd_error_sdcore_fsm_next_value4[0:0] 1'0 + sync always + sync init + update \libresocsim_sdcore_cmd_error_sdcore_fsm_next_value4 $1\libresocsim_sdcore_cmd_error_sdcore_fsm_next_value4[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:1722.5-1722.66" + process $proc$build/ls180/gateware/ls180.v:1722$3330 + assign { } { } + assign $1\libresocsim_sdcore_cmd_error_sdcore_fsm_next_value_ce4[0:0] 1'0 + sync always + sync init + update \libresocsim_sdcore_cmd_error_sdcore_fsm_next_value_ce4 $1\libresocsim_sdcore_cmd_error_sdcore_fsm_next_value_ce4[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:1723.5-1723.65" + process $proc$build/ls180/gateware/ls180.v:1723$3331 + assign { } { } + assign $1\libresocsim_sdcore_cmd_timeout_sdcore_fsm_next_value5[0:0] 1'0 + sync always + sync init + update \libresocsim_sdcore_cmd_timeout_sdcore_fsm_next_value5 $1\libresocsim_sdcore_cmd_timeout_sdcore_fsm_next_value5[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:1724.5-1724.68" + process $proc$build/ls180/gateware/ls180.v:1724$3332 + assign { } { } + assign $1\libresocsim_sdcore_cmd_timeout_sdcore_fsm_next_value_ce5[0:0] 1'0 + sync always + sync init + update \libresocsim_sdcore_cmd_timeout_sdcore_fsm_next_value_ce5 $1\libresocsim_sdcore_cmd_timeout_sdcore_fsm_next_value_ce5[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:1725.5-1725.64" + process $proc$build/ls180/gateware/ls180.v:1725$3333 + assign { } { } + assign $1\libresocsim_sdcore_data_error_sdcore_fsm_next_value6[0:0] 1'0 + sync always + sync init + update \libresocsim_sdcore_data_error_sdcore_fsm_next_value6 $1\libresocsim_sdcore_data_error_sdcore_fsm_next_value6[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:1726.5-1726.67" + process $proc$build/ls180/gateware/ls180.v:1726$3334 + assign { } { } + assign $1\libresocsim_sdcore_data_error_sdcore_fsm_next_value_ce6[0:0] 1'0 + sync always + sync init + update \libresocsim_sdcore_data_error_sdcore_fsm_next_value_ce6 $1\libresocsim_sdcore_data_error_sdcore_fsm_next_value_ce6[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:1727.5-1727.66" + process $proc$build/ls180/gateware/ls180.v:1727$3335 + assign { } { } + assign $1\libresocsim_sdcore_data_timeout_sdcore_fsm_next_value7[0:0] 1'0 + sync always + sync init + update \libresocsim_sdcore_data_timeout_sdcore_fsm_next_value7 $1\libresocsim_sdcore_data_timeout_sdcore_fsm_next_value7[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:1728.5-1728.69" + process $proc$build/ls180/gateware/ls180.v:1728$3336 + assign { } { } + assign $1\libresocsim_sdcore_data_timeout_sdcore_fsm_next_value_ce7[0:0] 1'0 + sync always + sync init + update \libresocsim_sdcore_data_timeout_sdcore_fsm_next_value_ce7 $1\libresocsim_sdcore_data_timeout_sdcore_fsm_next_value_ce7[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:1729.13-1729.83" + process $proc$build/ls180/gateware/ls180.v:1729$3337 + assign { } { } + assign $1\libresocsim_sdcore_cmd_response_status_sdcore_fsm_next_value8[127:0] 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \libresocsim_sdcore_cmd_response_status_sdcore_fsm_next_value8 $1\libresocsim_sdcore_cmd_response_status_sdcore_fsm_next_value8[127:0] + end + attribute \src "build/ls180/gateware/ls180.v:1730.5-1730.76" + process $proc$build/ls180/gateware/ls180.v:1730$3338 + assign { } { } + assign $1\libresocsim_sdcore_cmd_response_status_sdcore_fsm_next_value_ce8[0:0] 1'0 + sync always + sync init + update \libresocsim_sdcore_cmd_response_status_sdcore_fsm_next_value_ce8 $1\libresocsim_sdcore_cmd_response_status_sdcore_fsm_next_value_ce8[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:1731.11-1731.46" + process $proc$build/ls180/gateware/ls180.v:1731$3339 + assign { } { } + assign $1\builder_sdblock2memdma_state[1:0] 2'00 + sync always + sync init + update \builder_sdblock2memdma_state $1\builder_sdblock2memdma_state[1:0] + end + attribute \src "build/ls180/gateware/ls180.v:1732.11-1732.51" + process $proc$build/ls180/gateware/ls180.v:1732$3340 + assign { } { } + assign $1\builder_sdblock2memdma_next_state[1:0] 2'00 + sync always + sync init + update \builder_sdblock2memdma_next_state $1\builder_sdblock2memdma_next_state[1:0] + end + attribute \src "build/ls180/gateware/ls180.v:1733.12-1733.94" + process $proc$build/ls180/gateware/ls180.v:1733$3341 + assign { } { } + assign $1\libresocsim_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value[31:0] 0 + sync always + sync init + update \libresocsim_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value $1\libresocsim_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value[31:0] + end + attribute \src "build/ls180/gateware/ls180.v:1734.5-1734.89" + process $proc$build/ls180/gateware/ls180.v:1734$3342 + assign { } { } + assign $1\libresocsim_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value_ce[0:0] 1'0 + sync always + sync init + update \libresocsim_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value_ce $1\libresocsim_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value_ce[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:1735.5-1735.44" + process $proc$build/ls180/gateware/ls180.v:1735$3343 + assign { } { } + assign $1\builder_sdmem2blockdma_fsm_state[0:0] 1'0 + sync always + sync init + update \builder_sdmem2blockdma_fsm_state $1\builder_sdmem2blockdma_fsm_state[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:1736.5-1736.49" + process $proc$build/ls180/gateware/ls180.v:1736$3344 + assign { } { } + assign $1\builder_sdmem2blockdma_fsm_next_state[0:0] 1'0 + sync always + sync init + update \builder_sdmem2blockdma_fsm_next_state $1\builder_sdmem2blockdma_fsm_next_state[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:1737.12-1737.82" + process $proc$build/ls180/gateware/ls180.v:1737$3345 + assign { } { } + assign $1\libresocsim_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value[31:0] 0 + sync always + sync init + update \libresocsim_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value $1\libresocsim_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value[31:0] + end + attribute \src "build/ls180/gateware/ls180.v:1738.5-1738.77" + process $proc$build/ls180/gateware/ls180.v:1738$3346 + assign { } { } + assign $1\libresocsim_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value_ce[0:0] 1'0 + sync always + sync init + update \libresocsim_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value_ce $1\libresocsim_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value_ce[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:1739.11-1739.60" + process $proc$build/ls180/gateware/ls180.v:1739$3347 + assign { } { } + assign $1\builder_sdmem2blockdma_resetinserter_state[1:0] 2'00 + sync always + sync init + update \builder_sdmem2blockdma_resetinserter_state $1\builder_sdmem2blockdma_resetinserter_state[1:0] + end + attribute \src "build/ls180/gateware/ls180.v:1740.11-1740.65" + process $proc$build/ls180/gateware/ls180.v:1740$3348 + assign { } { } + assign $1\builder_sdmem2blockdma_resetinserter_next_state[1:0] 2'00 + sync always + sync init + update \builder_sdmem2blockdma_resetinserter_next_state $1\builder_sdmem2blockdma_resetinserter_next_state[1:0] + end + attribute \src "build/ls180/gateware/ls180.v:1741.12-1741.94" + process $proc$build/ls180/gateware/ls180.v:1741$3349 + assign { } { } + assign $1\libresocsim_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value[31:0] 0 + sync always + sync init + update \libresocsim_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value $1\libresocsim_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value[31:0] + end + attribute \src "build/ls180/gateware/ls180.v:1742.5-1742.89" + process $proc$build/ls180/gateware/ls180.v:1742$3350 + assign { } { } + assign $1\libresocsim_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value_ce[0:0] 1'0 + sync always + sync init + update \libresocsim_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value_ce $1\libresocsim_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value_ce[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:1743.11-1743.42" + process $proc$build/ls180/gateware/ls180.v:1743$3351 + assign { } { } + assign $1\builder_spimaster1_state[1:0] 2'00 + sync always + sync init + update \builder_spimaster1_state $1\builder_spimaster1_state[1:0] + end + attribute \src "build/ls180/gateware/ls180.v:1744.11-1744.47" + process $proc$build/ls180/gateware/ls180.v:1744$3352 + assign { } { } + assign $1\builder_spimaster1_next_state[1:0] 2'00 + sync always + sync init + update \builder_spimaster1_next_state $1\builder_spimaster1_next_state[1:0] + end + attribute \src "build/ls180/gateware/ls180.v:1745.11-1745.57" + process $proc$build/ls180/gateware/ls180.v:1745$3353 + assign { } { } + assign $1\libresocsim_count_spimaster1_next_value[2:0] 3'000 + sync always + sync init + update \libresocsim_count_spimaster1_next_value $1\libresocsim_count_spimaster1_next_value[2:0] + end + attribute \src "build/ls180/gateware/ls180.v:1746.5-1746.54" + process $proc$build/ls180/gateware/ls180.v:1746$3354 + assign { } { } + assign $1\libresocsim_count_spimaster1_next_value_ce[0:0] 1'0 + sync always + sync init + update \libresocsim_count_spimaster1_next_value_ce $1\libresocsim_count_spimaster1_next_value_ce[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:1747.12-1747.43" + process $proc$build/ls180/gateware/ls180.v:1747$3355 + assign { } { } + assign $1\builder_libresocsim_adr[13:0] 14'00000000000000 + sync always + sync init + update \builder_libresocsim_adr $1\builder_libresocsim_adr[13:0] + end + attribute \src "build/ls180/gateware/ls180.v:1748.5-1748.34" + process $proc$build/ls180/gateware/ls180.v:1748$3356 + assign { } { } + assign $1\builder_libresocsim_we[0:0] 1'0 + sync always + sync init + update \builder_libresocsim_we $1\builder_libresocsim_we[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:1749.11-1749.43" + process $proc$build/ls180/gateware/ls180.v:1749$3357 + assign { } { } + assign $1\builder_libresocsim_dat_w[7:0] 8'00000000 + sync always + sync init + update \builder_libresocsim_dat_w $1\builder_libresocsim_dat_w[7:0] + end + attribute \src "build/ls180/gateware/ls180.v:175.5-175.44" + process $proc$build/ls180/gateware/ls180.v:175$2626 + assign { } { } + assign $1\main_libresocsim_uart_tx_pending[0:0] 1'0 + sync always + sync init + update \main_libresocsim_uart_tx_pending $1\main_libresocsim_uart_tx_pending[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:1753.12-1753.54" + process $proc$build/ls180/gateware/ls180.v:1753$3358 + assign { } { } + assign $1\builder_libresocsim_wishbone_dat_r[31:0] 0 + sync always + sync init + update \builder_libresocsim_wishbone_dat_r $1\builder_libresocsim_wishbone_dat_r[31:0] + end + attribute \src "build/ls180/gateware/ls180.v:1757.5-1757.44" + process $proc$build/ls180/gateware/ls180.v:1757$3359 + assign { } { } + assign $1\builder_libresocsim_wishbone_ack[0:0] 1'0 + sync always + sync init + update \builder_libresocsim_wishbone_ack $1\builder_libresocsim_wishbone_ack[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:1761.5-1761.44" + process $proc$build/ls180/gateware/ls180.v:1761$3360 + assign { } { } + assign $0\builder_libresocsim_wishbone_err[0:0] 1'0 + sync always + update \builder_libresocsim_wishbone_err $0\builder_libresocsim_wishbone_err[0:0] + sync init + end + attribute \src "build/ls180/gateware/ls180.v:1764.12-1764.40" + process $proc$build/ls180/gateware/ls180.v:1764$3361 + assign { } { } + assign $1\builder_shared_dat_r[31:0] 0 + sync always + sync init + update \builder_shared_dat_r $1\builder_shared_dat_r[31:0] + end + attribute \src "build/ls180/gateware/ls180.v:1768.5-1768.30" + process $proc$build/ls180/gateware/ls180.v:1768$3362 + assign { } { } + assign $1\builder_shared_ack[0:0] 1'0 + sync always + sync init + update \builder_shared_ack $1\builder_shared_ack[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:177.5-177.42" + process $proc$build/ls180/gateware/ls180.v:177$2627 + assign { } { } + assign $1\main_libresocsim_uart_tx_clear[0:0] 1'0 + sync always + sync init + update \main_libresocsim_uart_tx_clear $1\main_libresocsim_uart_tx_clear[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:1774.11-1774.31" + process $proc$build/ls180/gateware/ls180.v:1774$3363 + assign { } { } + assign $1\builder_grant[1:0] 2'00 + sync always + sync init + update \builder_grant $1\builder_grant[1:0] + end + attribute \src "build/ls180/gateware/ls180.v:1775.11-1775.35" + process $proc$build/ls180/gateware/ls180.v:1775$3364 + assign { } { } + assign $1\builder_slave_sel[4:0] 5'00000 + sync always + sync init + update \builder_slave_sel $1\builder_slave_sel[4:0] + end + attribute \src "build/ls180/gateware/ls180.v:1776.11-1776.37" + process $proc$build/ls180/gateware/ls180.v:1776$3365 + assign { } { } + assign $1\builder_slave_sel_r[4:0] 5'00000 + sync always + sync init + update \builder_slave_sel_r $1\builder_slave_sel_r[4:0] + end + attribute \src "build/ls180/gateware/ls180.v:1777.5-1777.25" + process $proc$build/ls180/gateware/ls180.v:1777$3366 + assign { } { } + assign $1\builder_error[0:0] 1'0 + sync always + sync init + update \builder_error $1\builder_error[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:178.5-178.48" + process $proc$build/ls180/gateware/ls180.v:178$2628 + assign { } { } + assign $1\main_libresocsim_uart_tx_old_trigger[0:0] 1'0 + sync always + sync init + update \main_libresocsim_uart_tx_old_trigger $1\main_libresocsim_uart_tx_old_trigger[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:1780.12-1780.39" + process $proc$build/ls180/gateware/ls180.v:1780$3367 + assign { } { } + assign $1\builder_count[19:0] 20'11110100001001000000 + sync always + sync init + update \builder_count $1\builder_count[19:0] + end + attribute \src "build/ls180/gateware/ls180.v:1784.11-1784.51" + process $proc$build/ls180/gateware/ls180.v:1784$3368 + assign { } { } + assign $1\builder_interface0_bank_bus_dat_r[7:0] 8'00000000 + sync always + sync init + update \builder_interface0_bank_bus_dat_r $1\builder_interface0_bank_bus_dat_r[7:0] + end + attribute \src "build/ls180/gateware/ls180.v:180.5-180.44" + process $proc$build/ls180/gateware/ls180.v:180$2629 + assign { } { } + assign $1\main_libresocsim_uart_rx_pending[0:0] 1'0 + sync always + sync init + update \main_libresocsim_uart_rx_pending $1\main_libresocsim_uart_rx_pending[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:182.5-182.42" + process $proc$build/ls180/gateware/ls180.v:182$2630 + assign { } { } + assign $1\main_libresocsim_uart_rx_clear[0:0] 1'0 + sync always + sync init + update \main_libresocsim_uart_rx_clear $1\main_libresocsim_uart_rx_clear[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:1825.11-1825.51" + process $proc$build/ls180/gateware/ls180.v:1825$3369 + assign { } { } + assign $1\builder_interface1_bank_bus_dat_r[7:0] 8'00000000 + sync always + sync init + update \builder_interface1_bank_bus_dat_r $1\builder_interface1_bank_bus_dat_r[7:0] + end + attribute \src "build/ls180/gateware/ls180.v:183.5-183.48" + process $proc$build/ls180/gateware/ls180.v:183$2631 + assign { } { } + assign $1\main_libresocsim_uart_rx_old_trigger[0:0] 1'0 + sync always + sync init + update \main_libresocsim_uart_rx_old_trigger $1\main_libresocsim_uart_rx_old_trigger[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:1834.11-1834.51" + process $proc$build/ls180/gateware/ls180.v:1834$3370 + assign { } { } + assign $1\builder_interface2_bank_bus_dat_r[7:0] 8'00000000 + sync always + sync init + update \builder_interface2_bank_bus_dat_r $1\builder_interface2_bank_bus_dat_r[7:0] + end + attribute \src "build/ls180/gateware/ls180.v:1843.11-1843.51" + process $proc$build/ls180/gateware/ls180.v:1843$3371 + assign { } { } + assign $1\builder_interface3_bank_bus_dat_r[7:0] 8'00000000 + sync always + sync init + update \builder_interface3_bank_bus_dat_r $1\builder_interface3_bank_bus_dat_r[7:0] + end + attribute \src "build/ls180/gateware/ls180.v:187.11-187.61" + process $proc$build/ls180/gateware/ls180.v:187$2632 + assign { } { } + assign $1\main_libresocsim_uart_eventmanager_status_w[1:0] 2'00 + sync always + sync init + update \main_libresocsim_uart_eventmanager_status_w $1\main_libresocsim_uart_eventmanager_status_w[1:0] + end + attribute \src "build/ls180/gateware/ls180.v:1908.11-1908.51" + process $proc$build/ls180/gateware/ls180.v:1908$3372 + assign { } { } + assign $1\builder_interface4_bank_bus_dat_r[7:0] 8'00000000 + sync always + sync init + update \builder_interface4_bank_bus_dat_r $1\builder_interface4_bank_bus_dat_r[7:0] + end + attribute \src "build/ls180/gateware/ls180.v:191.11-191.62" + process $proc$build/ls180/gateware/ls180.v:191$2633 + assign { } { } + assign $1\main_libresocsim_uart_eventmanager_pending_w[1:0] 2'00 + sync always + sync init + update \main_libresocsim_uart_eventmanager_pending_w $1\main_libresocsim_uart_eventmanager_pending_w[1:0] + end + attribute \src "build/ls180/gateware/ls180.v:192.11-192.60" + process $proc$build/ls180/gateware/ls180.v:192$2634 + assign { } { } + assign $1\main_libresocsim_uart_eventmanager_storage[1:0] 2'00 + sync always + sync init + update \main_libresocsim_uart_eventmanager_storage $1\main_libresocsim_uart_eventmanager_storage[1:0] + end + attribute \src "build/ls180/gateware/ls180.v:193.5-193.49" + process $proc$build/ls180/gateware/ls180.v:193$2635 + assign { } { } + assign $1\main_libresocsim_uart_eventmanager_re[0:0] 1'0 + sync always + sync init + update \main_libresocsim_uart_eventmanager_re $1\main_libresocsim_uart_eventmanager_re[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:2041.11-2041.51" + process $proc$build/ls180/gateware/ls180.v:2041$3373 + assign { } { } + assign $1\builder_interface5_bank_bus_dat_r[7:0] 8'00000000 + sync always + sync init + update \builder_interface5_bank_bus_dat_r $1\builder_interface5_bank_bus_dat_r[7:0] + end + attribute \src "build/ls180/gateware/ls180.v:210.5-210.52" + process $proc$build/ls180/gateware/ls180.v:210$2636 + assign { } { } + assign $0\main_libresocsim_uart_tx_fifo_sink_first[0:0] 1'0 + sync always + update \main_libresocsim_uart_tx_fifo_sink_first $0\main_libresocsim_uart_tx_fifo_sink_first[0:0] + sync init + end + attribute \src "build/ls180/gateware/ls180.v:211.5-211.51" + process $proc$build/ls180/gateware/ls180.v:211$2637 + assign { } { } + assign $0\main_libresocsim_uart_tx_fifo_sink_last[0:0] 1'0 + sync always + update \main_libresocsim_uart_tx_fifo_sink_last $0\main_libresocsim_uart_tx_fifo_sink_last[0:0] + sync init + end + attribute \src "build/ls180/gateware/ls180.v:2122.11-2122.51" + process $proc$build/ls180/gateware/ls180.v:2122$3374 + assign { } { } + assign $1\builder_interface6_bank_bus_dat_r[7:0] 8'00000000 + sync always + sync init + update \builder_interface6_bank_bus_dat_r $1\builder_interface6_bank_bus_dat_r[7:0] + end + attribute \src "build/ls180/gateware/ls180.v:2139.11-2139.51" + process $proc$build/ls180/gateware/ls180.v:2139$3375 + assign { } { } + assign $1\builder_interface7_bank_bus_dat_r[7:0] 8'00000000 + sync always + sync init + update \builder_interface7_bank_bus_dat_r $1\builder_interface7_bank_bus_dat_r[7:0] + end + attribute \src "build/ls180/gateware/ls180.v:2180.11-2180.51" + process $proc$build/ls180/gateware/ls180.v:2180$3376 + assign { } { } + assign $1\builder_interface8_bank_bus_dat_r[7:0] 8'00000000 + sync always + sync init + update \builder_interface8_bank_bus_dat_r $1\builder_interface8_bank_bus_dat_r[7:0] + end + attribute \src "build/ls180/gateware/ls180.v:219.5-219.50" + process $proc$build/ls180/gateware/ls180.v:219$2638 + assign { } { } + assign $1\main_libresocsim_uart_tx_fifo_readable[0:0] 1'0 + sync always + sync init + update \main_libresocsim_uart_tx_fifo_readable $1\main_libresocsim_uart_tx_fifo_readable[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:2213.11-2213.51" + process $proc$build/ls180/gateware/ls180.v:2213$3377 + assign { } { } + assign $1\builder_interface9_bank_bus_dat_r[7:0] 8'00000000 + sync always + sync init + update \builder_interface9_bank_bus_dat_r $1\builder_interface9_bank_bus_dat_r[7:0] + end + attribute \src "build/ls180/gateware/ls180.v:2254.11-2254.52" + process $proc$build/ls180/gateware/ls180.v:2254$3378 + assign { } { } + assign $1\builder_interface10_bank_bus_dat_r[7:0] 8'00000000 + sync always + sync init + update \builder_interface10_bank_bus_dat_r $1\builder_interface10_bank_bus_dat_r[7:0] + end + attribute \src "build/ls180/gateware/ls180.v:226.11-226.54" + process $proc$build/ls180/gateware/ls180.v:226$2639 + assign { } { } + assign $1\main_libresocsim_uart_tx_fifo_level0[4:0] 5'00000 + sync always + sync init + update \main_libresocsim_uart_tx_fifo_level0 $1\main_libresocsim_uart_tx_fifo_level0[4:0] + end + attribute \src "build/ls180/gateware/ls180.v:227.5-227.49" + process $proc$build/ls180/gateware/ls180.v:227$2640 + assign { } { } + assign $0\main_libresocsim_uart_tx_fifo_replace[0:0] 1'0 + sync always + update \main_libresocsim_uart_tx_fifo_replace $0\main_libresocsim_uart_tx_fifo_replace[0:0] + sync init + end + attribute \src "build/ls180/gateware/ls180.v:228.11-228.55" + process $proc$build/ls180/gateware/ls180.v:228$2641 + assign { } { } + assign $1\main_libresocsim_uart_tx_fifo_produce[3:0] 4'0000 + sync always + sync init + update \main_libresocsim_uart_tx_fifo_produce $1\main_libresocsim_uart_tx_fifo_produce[3:0] + end + attribute \src "build/ls180/gateware/ls180.v:229.11-229.55" + process $proc$build/ls180/gateware/ls180.v:229$2642 + assign { } { } + assign $1\main_libresocsim_uart_tx_fifo_consume[3:0] 4'0000 + sync always + sync init + update \main_libresocsim_uart_tx_fifo_consume $1\main_libresocsim_uart_tx_fifo_consume[3:0] + end + attribute \src "build/ls180/gateware/ls180.v:230.11-230.58" + process $proc$build/ls180/gateware/ls180.v:230$2643 + assign { } { } + assign $1\main_libresocsim_uart_tx_fifo_wrport_adr[3:0] 4'0000 + sync always + sync init + update \main_libresocsim_uart_tx_fifo_wrport_adr $1\main_libresocsim_uart_tx_fifo_wrport_adr[3:0] + end + attribute \src "build/ls180/gateware/ls180.v:2319.11-2319.52" + process $proc$build/ls180/gateware/ls180.v:2319$3379 + assign { } { } + assign $1\builder_interface11_bank_bus_dat_r[7:0] 8'00000000 + sync always + sync init + update \builder_interface11_bank_bus_dat_r $1\builder_interface11_bank_bus_dat_r[7:0] + end + attribute \src "build/ls180/gateware/ls180.v:2344.11-2344.52" + process $proc$build/ls180/gateware/ls180.v:2344$3380 + assign { } { } + assign $1\builder_interface12_bank_bus_dat_r[7:0] 8'00000000 + sync always + sync init + update \builder_interface12_bank_bus_dat_r $1\builder_interface12_bank_bus_dat_r[7:0] + end + attribute \src "build/ls180/gateware/ls180.v:2366.11-2366.31" + process $proc$build/ls180/gateware/ls180.v:2366$3381 + assign { } { } + assign $1\builder_state[1:0] 2'00 + sync always + sync init + update \builder_state $1\builder_state[1:0] + end + attribute \src "build/ls180/gateware/ls180.v:2367.11-2367.36" + process $proc$build/ls180/gateware/ls180.v:2367$3382 + assign { } { } + assign $1\builder_next_state[1:0] 2'00 + sync always + sync init + update \builder_next_state $1\builder_next_state[1:0] + end + attribute \src "build/ls180/gateware/ls180.v:2368.11-2368.55" + process $proc$build/ls180/gateware/ls180.v:2368$3383 + assign { } { } + assign $1\builder_libresocsim_dat_w_next_value0[7:0] 8'00000000 + sync always + sync init + update \builder_libresocsim_dat_w_next_value0 $1\builder_libresocsim_dat_w_next_value0[7:0] + end + attribute \src "build/ls180/gateware/ls180.v:2369.5-2369.52" + process $proc$build/ls180/gateware/ls180.v:2369$3384 + assign { } { } + assign $1\builder_libresocsim_dat_w_next_value_ce0[0:0] 1'0 + sync always + sync init + update \builder_libresocsim_dat_w_next_value_ce0 $1\builder_libresocsim_dat_w_next_value_ce0[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:2370.12-2370.55" + process $proc$build/ls180/gateware/ls180.v:2370$3385 + assign { } { } + assign $1\builder_libresocsim_adr_next_value1[13:0] 14'00000000000000 + sync always + sync init + update \builder_libresocsim_adr_next_value1 $1\builder_libresocsim_adr_next_value1[13:0] + end + attribute \src "build/ls180/gateware/ls180.v:2371.5-2371.50" + process $proc$build/ls180/gateware/ls180.v:2371$3386 + assign { } { } + assign $1\builder_libresocsim_adr_next_value_ce1[0:0] 1'0 + sync always + sync init + update \builder_libresocsim_adr_next_value_ce1 $1\builder_libresocsim_adr_next_value_ce1[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:2372.5-2372.46" + process $proc$build/ls180/gateware/ls180.v:2372$3387 + assign { } { } + assign $1\builder_libresocsim_we_next_value2[0:0] 1'0 + sync always + sync init + update \builder_libresocsim_we_next_value2 $1\builder_libresocsim_we_next_value2[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:2373.5-2373.49" + process $proc$build/ls180/gateware/ls180.v:2373$3388 + assign { } { } + assign $1\builder_libresocsim_we_next_value_ce2[0:0] 1'0 + sync always + sync init + update \builder_libresocsim_we_next_value_ce2 $1\builder_libresocsim_we_next_value_ce2[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:2374.5-2374.41" + process $proc$build/ls180/gateware/ls180.v:2374$3389 + assign { } { } + assign $1\builder_comb_rhs_array_muxed0[0:0] 1'0 + sync always + sync init + update \builder_comb_rhs_array_muxed0 $1\builder_comb_rhs_array_muxed0[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:2375.12-2375.49" + process $proc$build/ls180/gateware/ls180.v:2375$3390 + assign { } { } + assign $1\builder_comb_rhs_array_muxed1[12:0] 13'0000000000000 + sync always + sync init + update \builder_comb_rhs_array_muxed1 $1\builder_comb_rhs_array_muxed1[12:0] + end + attribute \src "build/ls180/gateware/ls180.v:2376.11-2376.47" + process $proc$build/ls180/gateware/ls180.v:2376$3391 + assign { } { } + assign $1\builder_comb_rhs_array_muxed2[1:0] 2'00 + sync always + sync init + update \builder_comb_rhs_array_muxed2 $1\builder_comb_rhs_array_muxed2[1:0] + end + attribute \src "build/ls180/gateware/ls180.v:2377.5-2377.41" + process $proc$build/ls180/gateware/ls180.v:2377$3392 + assign { } { } + assign $1\builder_comb_rhs_array_muxed3[0:0] 1'0 + sync always + sync init + update \builder_comb_rhs_array_muxed3 $1\builder_comb_rhs_array_muxed3[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:2378.5-2378.41" + process $proc$build/ls180/gateware/ls180.v:2378$3393 + assign { } { } + assign $1\builder_comb_rhs_array_muxed4[0:0] 1'0 + sync always + sync init + update \builder_comb_rhs_array_muxed4 $1\builder_comb_rhs_array_muxed4[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:2379.5-2379.41" + process $proc$build/ls180/gateware/ls180.v:2379$3394 + assign { } { } + assign $1\builder_comb_rhs_array_muxed5[0:0] 1'0 + sync always + sync init + update \builder_comb_rhs_array_muxed5 $1\builder_comb_rhs_array_muxed5[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:2380.5-2380.39" + process $proc$build/ls180/gateware/ls180.v:2380$3395 + assign { } { } + assign $1\builder_comb_t_array_muxed0[0:0] 1'0 + sync always + sync init + update \builder_comb_t_array_muxed0 $1\builder_comb_t_array_muxed0[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:2381.5-2381.39" + process $proc$build/ls180/gateware/ls180.v:2381$3396 + assign { } { } + assign $1\builder_comb_t_array_muxed1[0:0] 1'0 + sync always + sync init + update \builder_comb_t_array_muxed1 $1\builder_comb_t_array_muxed1[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:2382.5-2382.39" + process $proc$build/ls180/gateware/ls180.v:2382$3397 + assign { } { } + assign $1\builder_comb_t_array_muxed2[0:0] 1'0 + sync always + sync init + update \builder_comb_t_array_muxed2 $1\builder_comb_t_array_muxed2[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:2383.5-2383.41" + process $proc$build/ls180/gateware/ls180.v:2383$3398 + assign { } { } + assign $1\builder_comb_rhs_array_muxed6[0:0] 1'0 + sync always + sync init + update \builder_comb_rhs_array_muxed6 $1\builder_comb_rhs_array_muxed6[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:2384.12-2384.49" + process $proc$build/ls180/gateware/ls180.v:2384$3399 + assign { } { } + assign $1\builder_comb_rhs_array_muxed7[12:0] 13'0000000000000 + sync always + sync init + update \builder_comb_rhs_array_muxed7 $1\builder_comb_rhs_array_muxed7[12:0] + end + attribute \src "build/ls180/gateware/ls180.v:2385.11-2385.47" + process $proc$build/ls180/gateware/ls180.v:2385$3400 + assign { } { } + assign $1\builder_comb_rhs_array_muxed8[1:0] 2'00 + sync always + sync init + update \builder_comb_rhs_array_muxed8 $1\builder_comb_rhs_array_muxed8[1:0] + end + attribute \src "build/ls180/gateware/ls180.v:2386.5-2386.41" + process $proc$build/ls180/gateware/ls180.v:2386$3401 + assign { } { } + assign $1\builder_comb_rhs_array_muxed9[0:0] 1'0 + sync always + sync init + update \builder_comb_rhs_array_muxed9 $1\builder_comb_rhs_array_muxed9[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:2387.5-2387.42" + process $proc$build/ls180/gateware/ls180.v:2387$3402 + assign { } { } + assign $1\builder_comb_rhs_array_muxed10[0:0] 1'0 + sync always + sync init + update \builder_comb_rhs_array_muxed10 $1\builder_comb_rhs_array_muxed10[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:2388.5-2388.42" + process $proc$build/ls180/gateware/ls180.v:2388$3403 + assign { } { } + assign $1\builder_comb_rhs_array_muxed11[0:0] 1'0 + sync always + sync init + update \builder_comb_rhs_array_muxed11 $1\builder_comb_rhs_array_muxed11[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:2389.5-2389.39" + process $proc$build/ls180/gateware/ls180.v:2389$3404 + assign { } { } + assign $1\builder_comb_t_array_muxed3[0:0] 1'0 + sync always + sync init + update \builder_comb_t_array_muxed3 $1\builder_comb_t_array_muxed3[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:2390.5-2390.39" + process $proc$build/ls180/gateware/ls180.v:2390$3405 + assign { } { } + assign $1\builder_comb_t_array_muxed4[0:0] 1'0 + sync always + sync init + update \builder_comb_t_array_muxed4 $1\builder_comb_t_array_muxed4[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:2391.5-2391.39" + process $proc$build/ls180/gateware/ls180.v:2391$3406 + assign { } { } + assign $1\builder_comb_t_array_muxed5[0:0] 1'0 + sync always + sync init + update \builder_comb_t_array_muxed5 $1\builder_comb_t_array_muxed5[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:2392.12-2392.50" + process $proc$build/ls180/gateware/ls180.v:2392$3407 + assign { } { } + assign $1\builder_comb_rhs_array_muxed12[21:0] 22'0000000000000000000000 + sync always + sync init + update \builder_comb_rhs_array_muxed12 $1\builder_comb_rhs_array_muxed12[21:0] + end + attribute \src "build/ls180/gateware/ls180.v:2393.5-2393.42" + process $proc$build/ls180/gateware/ls180.v:2393$3408 + assign { } { } + assign $1\builder_comb_rhs_array_muxed13[0:0] 1'0 + sync always + sync init + update \builder_comb_rhs_array_muxed13 $1\builder_comb_rhs_array_muxed13[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:2394.5-2394.42" + process $proc$build/ls180/gateware/ls180.v:2394$3409 + assign { } { } + assign $1\builder_comb_rhs_array_muxed14[0:0] 1'0 + sync always + sync init + update \builder_comb_rhs_array_muxed14 $1\builder_comb_rhs_array_muxed14[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:2395.12-2395.50" + process $proc$build/ls180/gateware/ls180.v:2395$3410 + assign { } { } + assign $1\builder_comb_rhs_array_muxed15[21:0] 22'0000000000000000000000 + sync always + sync init + update \builder_comb_rhs_array_muxed15 $1\builder_comb_rhs_array_muxed15[21:0] + end + attribute \src "build/ls180/gateware/ls180.v:2396.5-2396.42" + process $proc$build/ls180/gateware/ls180.v:2396$3411 + assign { } { } + assign $1\builder_comb_rhs_array_muxed16[0:0] 1'0 + sync always + sync init + update \builder_comb_rhs_array_muxed16 $1\builder_comb_rhs_array_muxed16[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:2397.5-2397.42" + process $proc$build/ls180/gateware/ls180.v:2397$3412 + assign { } { } + assign $1\builder_comb_rhs_array_muxed17[0:0] 1'0 + sync always + sync init + update \builder_comb_rhs_array_muxed17 $1\builder_comb_rhs_array_muxed17[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:2398.12-2398.50" + process $proc$build/ls180/gateware/ls180.v:2398$3413 + assign { } { } + assign $1\builder_comb_rhs_array_muxed18[21:0] 22'0000000000000000000000 + sync always + sync init + update \builder_comb_rhs_array_muxed18 $1\builder_comb_rhs_array_muxed18[21:0] + end + attribute \src "build/ls180/gateware/ls180.v:2399.5-2399.42" + process $proc$build/ls180/gateware/ls180.v:2399$3414 + assign { } { } + assign $1\builder_comb_rhs_array_muxed19[0:0] 1'0 + sync always + sync init + update \builder_comb_rhs_array_muxed19 $1\builder_comb_rhs_array_muxed19[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:2400.5-2400.42" + process $proc$build/ls180/gateware/ls180.v:2400$3415 + assign { } { } + assign $1\builder_comb_rhs_array_muxed20[0:0] 1'0 + sync always + sync init + update \builder_comb_rhs_array_muxed20 $1\builder_comb_rhs_array_muxed20[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:2401.12-2401.50" + process $proc$build/ls180/gateware/ls180.v:2401$3416 + assign { } { } + assign $1\builder_comb_rhs_array_muxed21[21:0] 22'0000000000000000000000 + sync always + sync init + update \builder_comb_rhs_array_muxed21 $1\builder_comb_rhs_array_muxed21[21:0] + end + attribute \src "build/ls180/gateware/ls180.v:2402.5-2402.42" + process $proc$build/ls180/gateware/ls180.v:2402$3417 + assign { } { } + assign $1\builder_comb_rhs_array_muxed22[0:0] 1'0 + sync always + sync init + update \builder_comb_rhs_array_muxed22 $1\builder_comb_rhs_array_muxed22[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:2403.5-2403.42" + process $proc$build/ls180/gateware/ls180.v:2403$3418 + assign { } { } + assign $1\builder_comb_rhs_array_muxed23[0:0] 1'0 + sync always + sync init + update \builder_comb_rhs_array_muxed23 $1\builder_comb_rhs_array_muxed23[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:2404.12-2404.50" + process $proc$build/ls180/gateware/ls180.v:2404$3419 + assign { } { } + assign $1\builder_comb_rhs_array_muxed24[31:0] 0 + sync always + sync init + update \builder_comb_rhs_array_muxed24 $1\builder_comb_rhs_array_muxed24[31:0] + end + attribute \src "build/ls180/gateware/ls180.v:2405.12-2405.50" + process $proc$build/ls180/gateware/ls180.v:2405$3420 + assign { } { } + assign $1\builder_comb_rhs_array_muxed25[31:0] 0 + sync always + sync init + update \builder_comb_rhs_array_muxed25 $1\builder_comb_rhs_array_muxed25[31:0] + end + attribute \src "build/ls180/gateware/ls180.v:2406.11-2406.48" + process $proc$build/ls180/gateware/ls180.v:2406$3421 + assign { } { } + assign $1\builder_comb_rhs_array_muxed26[3:0] 4'0000 + sync always + sync init + update \builder_comb_rhs_array_muxed26 $1\builder_comb_rhs_array_muxed26[3:0] + end + attribute \src "build/ls180/gateware/ls180.v:2407.5-2407.42" + process $proc$build/ls180/gateware/ls180.v:2407$3422 + assign { } { } + assign $1\builder_comb_rhs_array_muxed27[0:0] 1'0 + sync always + sync init + update \builder_comb_rhs_array_muxed27 $1\builder_comb_rhs_array_muxed27[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:2408.5-2408.42" + process $proc$build/ls180/gateware/ls180.v:2408$3423 + assign { } { } + assign $1\builder_comb_rhs_array_muxed28[0:0] 1'0 + sync always + sync init + update \builder_comb_rhs_array_muxed28 $1\builder_comb_rhs_array_muxed28[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:2409.5-2409.42" + process $proc$build/ls180/gateware/ls180.v:2409$3424 + assign { } { } + assign $1\builder_comb_rhs_array_muxed29[0:0] 1'0 + sync always + sync init + update \builder_comb_rhs_array_muxed29 $1\builder_comb_rhs_array_muxed29[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:2410.11-2410.48" + process $proc$build/ls180/gateware/ls180.v:2410$3425 + assign { } { } + assign $1\builder_comb_rhs_array_muxed30[2:0] 3'000 + sync always + sync init + update \builder_comb_rhs_array_muxed30 $1\builder_comb_rhs_array_muxed30[2:0] + end + attribute \src "build/ls180/gateware/ls180.v:2411.11-2411.48" + process $proc$build/ls180/gateware/ls180.v:2411$3426 + assign { } { } + assign $1\builder_comb_rhs_array_muxed31[1:0] 2'00 + sync always + sync init + update \builder_comb_rhs_array_muxed31 $1\builder_comb_rhs_array_muxed31[1:0] + end + attribute \src "build/ls180/gateware/ls180.v:2412.11-2412.47" + process $proc$build/ls180/gateware/ls180.v:2412$3427 + assign { } { } + assign $1\builder_sync_rhs_array_muxed0[1:0] 2'00 + sync always + sync init + update \builder_sync_rhs_array_muxed0 $1\builder_sync_rhs_array_muxed0[1:0] + end + attribute \src "build/ls180/gateware/ls180.v:2413.12-2413.49" + process $proc$build/ls180/gateware/ls180.v:2413$3428 + assign { } { } + assign $1\builder_sync_rhs_array_muxed1[12:0] 13'0000000000000 + sync always + sync init + update \builder_sync_rhs_array_muxed1 $1\builder_sync_rhs_array_muxed1[12:0] + end + attribute \src "build/ls180/gateware/ls180.v:2414.5-2414.41" + process $proc$build/ls180/gateware/ls180.v:2414$3429 + assign { } { } + assign $1\builder_sync_rhs_array_muxed2[0:0] 1'0 + sync always + sync init + update \builder_sync_rhs_array_muxed2 $1\builder_sync_rhs_array_muxed2[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:2415.5-2415.41" + process $proc$build/ls180/gateware/ls180.v:2415$3430 + assign { } { } + assign $1\builder_sync_rhs_array_muxed3[0:0] 1'0 + sync always + sync init + update \builder_sync_rhs_array_muxed3 $1\builder_sync_rhs_array_muxed3[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:2416.5-2416.41" + process $proc$build/ls180/gateware/ls180.v:2416$3431 + assign { } { } + assign $1\builder_sync_rhs_array_muxed4[0:0] 1'0 + sync always + sync init + update \builder_sync_rhs_array_muxed4 $1\builder_sync_rhs_array_muxed4[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:2417.5-2417.41" + process $proc$build/ls180/gateware/ls180.v:2417$3432 + assign { } { } + assign $1\builder_sync_rhs_array_muxed5[0:0] 1'0 + sync always + sync init + update \builder_sync_rhs_array_muxed5 $1\builder_sync_rhs_array_muxed5[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:2418.5-2418.41" + process $proc$build/ls180/gateware/ls180.v:2418$3433 + assign { } { } + assign $1\builder_sync_rhs_array_muxed6[0:0] 1'0 + sync always + sync init + update \builder_sync_rhs_array_muxed6 $1\builder_sync_rhs_array_muxed6[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:2419.5-2419.39" + process $proc$build/ls180/gateware/ls180.v:2419$3434 + assign { } { } + assign $1\builder_sync_f_array_muxed0[0:0] 1'0 + sync always + sync init + update \builder_sync_f_array_muxed0 $1\builder_sync_f_array_muxed0[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:2420.5-2420.39" + process $proc$build/ls180/gateware/ls180.v:2420$3435 + assign { } { } + assign $1\builder_sync_f_array_muxed1[0:0] 1'0 + sync always + sync init + update \builder_sync_f_array_muxed1 $1\builder_sync_f_array_muxed1[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:2421.32-2421.66" + process $proc$build/ls180/gateware/ls180.v:2421$3436 + assign { } { } + assign $1\builder_multiregimpl0_regs0[0:0] 1'0 + sync always + sync init + update \builder_multiregimpl0_regs0 $1\builder_multiregimpl0_regs0[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:2422.32-2422.66" + process $proc$build/ls180/gateware/ls180.v:2422$3437 + assign { } { } + assign $1\builder_multiregimpl0_regs1[0:0] 1'0 + sync always + sync init + update \builder_multiregimpl0_regs1 $1\builder_multiregimpl0_regs1[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:2443.5-2443.42" + process $proc$build/ls180/gateware/ls180.v:2443$3438 + assign { } { } + assign $1\builder_inferedsdrtristate0__o[0:0] 1'0 + sync always + sync init + update \builder_inferedsdrtristate0__o $1\builder_inferedsdrtristate0__o[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:2444.5-2444.42" + process $proc$build/ls180/gateware/ls180.v:2444$3439 + assign { } { } + assign $1\builder_inferedsdrtristate0_oe[0:0] 1'0 + sync always + sync init + update \builder_inferedsdrtristate0_oe $1\builder_inferedsdrtristate0_oe[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:2447.5-2447.42" + process $proc$build/ls180/gateware/ls180.v:2447$3440 + assign { } { } + assign $1\builder_inferedsdrtristate1__o[0:0] 1'0 + sync always + sync init + update \builder_inferedsdrtristate1__o $1\builder_inferedsdrtristate1__o[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:2448.5-2448.42" + process $proc$build/ls180/gateware/ls180.v:2448$3441 + assign { } { } + assign $1\builder_inferedsdrtristate1_oe[0:0] 1'0 + sync always + sync init + update \builder_inferedsdrtristate1_oe $1\builder_inferedsdrtristate1_oe[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:2451.5-2451.42" + process $proc$build/ls180/gateware/ls180.v:2451$3442 + assign { } { } + assign $1\builder_inferedsdrtristate2__o[0:0] 1'0 + sync always + sync init + update \builder_inferedsdrtristate2__o $1\builder_inferedsdrtristate2__o[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:2452.5-2452.42" + process $proc$build/ls180/gateware/ls180.v:2452$3443 + assign { } { } + assign $1\builder_inferedsdrtristate2_oe[0:0] 1'0 + sync always + sync init + update \builder_inferedsdrtristate2_oe $1\builder_inferedsdrtristate2_oe[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:2455.5-2455.42" + process $proc$build/ls180/gateware/ls180.v:2455$3444 + assign { } { } + assign $1\builder_inferedsdrtristate3__o[0:0] 1'0 + sync always + sync init + update \builder_inferedsdrtristate3__o $1\builder_inferedsdrtristate3__o[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:2456.5-2456.42" + process $proc$build/ls180/gateware/ls180.v:2456$3445 + assign { } { } + assign $1\builder_inferedsdrtristate3_oe[0:0] 1'0 + sync always + sync init + update \builder_inferedsdrtristate3_oe $1\builder_inferedsdrtristate3_oe[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:2459.5-2459.42" + process $proc$build/ls180/gateware/ls180.v:2459$3446 + assign { } { } + assign $1\builder_inferedsdrtristate4__o[0:0] 1'0 + sync always + sync init + update \builder_inferedsdrtristate4__o $1\builder_inferedsdrtristate4__o[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:2460.5-2460.42" + process $proc$build/ls180/gateware/ls180.v:2460$3447 + assign { } { } + assign $1\builder_inferedsdrtristate4_oe[0:0] 1'0 + sync always + sync init + update \builder_inferedsdrtristate4_oe $1\builder_inferedsdrtristate4_oe[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:2463.5-2463.42" + process $proc$build/ls180/gateware/ls180.v:2463$3448 + assign { } { } + assign $1\builder_inferedsdrtristate5__o[0:0] 1'0 + sync always + sync init + update \builder_inferedsdrtristate5__o $1\builder_inferedsdrtristate5__o[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:2464.5-2464.42" + process $proc$build/ls180/gateware/ls180.v:2464$3449 + assign { } { } + assign $1\builder_inferedsdrtristate5_oe[0:0] 1'0 + sync always + sync init + update \builder_inferedsdrtristate5_oe $1\builder_inferedsdrtristate5_oe[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:2467.5-2467.42" + process $proc$build/ls180/gateware/ls180.v:2467$3450 + assign { } { } + assign $1\builder_inferedsdrtristate6__o[0:0] 1'0 + sync always + sync init + update \builder_inferedsdrtristate6__o $1\builder_inferedsdrtristate6__o[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:2468.5-2468.42" + process $proc$build/ls180/gateware/ls180.v:2468$3451 + assign { } { } + assign $1\builder_inferedsdrtristate6_oe[0:0] 1'0 + sync always + sync init + update \builder_inferedsdrtristate6_oe $1\builder_inferedsdrtristate6_oe[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:2471.5-2471.42" + process $proc$build/ls180/gateware/ls180.v:2471$3452 + assign { } { } + assign $1\builder_inferedsdrtristate7__o[0:0] 1'0 + sync always + sync init + update \builder_inferedsdrtristate7__o $1\builder_inferedsdrtristate7__o[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:2472.5-2472.42" + process $proc$build/ls180/gateware/ls180.v:2472$3453 + assign { } { } + assign $1\builder_inferedsdrtristate7_oe[0:0] 1'0 + sync always + sync init + update \builder_inferedsdrtristate7_oe $1\builder_inferedsdrtristate7_oe[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:2475.5-2475.42" + process $proc$build/ls180/gateware/ls180.v:2475$3454 + assign { } { } + assign $1\builder_inferedsdrtristate8__o[0:0] 1'0 + sync always + sync init + update \builder_inferedsdrtristate8__o $1\builder_inferedsdrtristate8__o[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:2476.5-2476.42" + process $proc$build/ls180/gateware/ls180.v:2476$3455 + assign { } { } + assign $1\builder_inferedsdrtristate8_oe[0:0] 1'0 + sync always + sync init + update \builder_inferedsdrtristate8_oe $1\builder_inferedsdrtristate8_oe[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:2479.5-2479.42" + process $proc$build/ls180/gateware/ls180.v:2479$3456 + assign { } { } + assign $1\builder_inferedsdrtristate9__o[0:0] 1'0 + sync always + sync init + update \builder_inferedsdrtristate9__o $1\builder_inferedsdrtristate9__o[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:2480.5-2480.42" + process $proc$build/ls180/gateware/ls180.v:2480$3457 + assign { } { } + assign $1\builder_inferedsdrtristate9_oe[0:0] 1'0 + sync always + sync init + update \builder_inferedsdrtristate9_oe $1\builder_inferedsdrtristate9_oe[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:2483.5-2483.43" + process $proc$build/ls180/gateware/ls180.v:2483$3458 + assign { } { } + assign $1\builder_inferedsdrtristate10__o[0:0] 1'0 + sync always + sync init + update \builder_inferedsdrtristate10__o $1\builder_inferedsdrtristate10__o[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:2484.5-2484.43" + process $proc$build/ls180/gateware/ls180.v:2484$3459 + assign { } { } + assign $1\builder_inferedsdrtristate10_oe[0:0] 1'0 + sync always + sync init + update \builder_inferedsdrtristate10_oe $1\builder_inferedsdrtristate10_oe[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:2487.5-2487.43" + process $proc$build/ls180/gateware/ls180.v:2487$3460 + assign { } { } + assign $1\builder_inferedsdrtristate11__o[0:0] 1'0 + sync always + sync init + update \builder_inferedsdrtristate11__o $1\builder_inferedsdrtristate11__o[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:2488.5-2488.43" + process $proc$build/ls180/gateware/ls180.v:2488$3461 + assign { } { } + assign $1\builder_inferedsdrtristate11_oe[0:0] 1'0 + sync always + sync init + update \builder_inferedsdrtristate11_oe $1\builder_inferedsdrtristate11_oe[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:2491.5-2491.43" + process $proc$build/ls180/gateware/ls180.v:2491$3462 + assign { } { } + assign $1\builder_inferedsdrtristate12__o[0:0] 1'0 + sync always + sync init + update \builder_inferedsdrtristate12__o $1\builder_inferedsdrtristate12__o[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:2492.5-2492.43" + process $proc$build/ls180/gateware/ls180.v:2492$3463 + assign { } { } + assign $1\builder_inferedsdrtristate12_oe[0:0] 1'0 + sync always + sync init + update \builder_inferedsdrtristate12_oe $1\builder_inferedsdrtristate12_oe[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:2495.5-2495.43" + process $proc$build/ls180/gateware/ls180.v:2495$3464 + assign { } { } + assign $1\builder_inferedsdrtristate13__o[0:0] 1'0 + sync always + sync init + update \builder_inferedsdrtristate13__o $1\builder_inferedsdrtristate13__o[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:2496.5-2496.43" + process $proc$build/ls180/gateware/ls180.v:2496$3465 + assign { } { } + assign $1\builder_inferedsdrtristate13_oe[0:0] 1'0 + sync always + sync init + update \builder_inferedsdrtristate13_oe $1\builder_inferedsdrtristate13_oe[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:2499.5-2499.43" + process $proc$build/ls180/gateware/ls180.v:2499$3466 + assign { } { } + assign $1\builder_inferedsdrtristate14__o[0:0] 1'0 + sync always + sync init + update \builder_inferedsdrtristate14__o $1\builder_inferedsdrtristate14__o[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:2500.5-2500.43" + process $proc$build/ls180/gateware/ls180.v:2500$3467 + assign { } { } + assign $1\builder_inferedsdrtristate14_oe[0:0] 1'0 + sync always + sync init + update \builder_inferedsdrtristate14_oe $1\builder_inferedsdrtristate14_oe[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:2503.5-2503.43" + process $proc$build/ls180/gateware/ls180.v:2503$3468 + assign { } { } + assign $1\builder_inferedsdrtristate15__o[0:0] 1'0 + sync always + sync init + update \builder_inferedsdrtristate15__o $1\builder_inferedsdrtristate15__o[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:2504.5-2504.43" + process $proc$build/ls180/gateware/ls180.v:2504$3469 + assign { } { } + assign $1\builder_inferedsdrtristate15_oe[0:0] 1'0 + sync always + sync init + update \builder_inferedsdrtristate15_oe $1\builder_inferedsdrtristate15_oe[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:2507.38-2507.72" + process $proc$build/ls180/gateware/ls180.v:2507$3470 + assign { } { } + assign $1\builder_multiregimpl1_regs0[7:0] 8'00000000 + sync always + sync init + update \builder_multiregimpl1_regs0 $1\builder_multiregimpl1_regs0[7:0] + end + attribute \src "build/ls180/gateware/ls180.v:2508.38-2508.72" + process $proc$build/ls180/gateware/ls180.v:2508$3471 + assign { } { } + assign $1\builder_multiregimpl1_regs1[7:0] 8'00000000 + sync always + sync init + update \builder_multiregimpl1_regs1 $1\builder_multiregimpl1_regs1[7:0] + end + attribute \src "build/ls180/gateware/ls180.v:2509.38-2509.72" + process $proc$build/ls180/gateware/ls180.v:2509$3472 + assign { } { } + assign $1\builder_multiregimpl2_regs0[7:0] 8'00000000 + sync always + sync init + update \builder_multiregimpl2_regs0 $1\builder_multiregimpl2_regs0[7:0] + end + attribute \src "build/ls180/gateware/ls180.v:2510.38-2510.72" + process $proc$build/ls180/gateware/ls180.v:2510$3473 + assign { } { } + assign $1\builder_multiregimpl2_regs1[7:0] 8'00000000 + sync always + sync init + update \builder_multiregimpl2_regs1 $1\builder_multiregimpl2_regs1[7:0] + end + attribute \src "build/ls180/gateware/ls180.v:2512.5-2512.43" + process $proc$build/ls180/gateware/ls180.v:2512$3474 + assign { } { } + assign $1\builder_inferedsdrtristate16__o[0:0] 1'0 + sync always + sync init + update \builder_inferedsdrtristate16__o $1\builder_inferedsdrtristate16__o[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:2513.5-2513.43" + process $proc$build/ls180/gateware/ls180.v:2513$3475 + assign { } { } + assign $1\builder_inferedsdrtristate16_oe[0:0] 1'0 + sync always + sync init + update \builder_inferedsdrtristate16_oe $1\builder_inferedsdrtristate16_oe[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:2516.5-2516.43" + process $proc$build/ls180/gateware/ls180.v:2516$3476 + assign { } { } + assign $1\builder_inferedsdrtristate17__o[0:0] 1'0 + sync always + sync init + update \builder_inferedsdrtristate17__o $1\builder_inferedsdrtristate17__o[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:2517.5-2517.43" + process $proc$build/ls180/gateware/ls180.v:2517$3477 + assign { } { } + assign $1\builder_inferedsdrtristate17_oe[0:0] 1'0 + sync always + sync init + update \builder_inferedsdrtristate17_oe $1\builder_inferedsdrtristate17_oe[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:2520.5-2520.43" + process $proc$build/ls180/gateware/ls180.v:2520$3478 + assign { } { } + assign $1\builder_inferedsdrtristate18__o[0:0] 1'0 + sync always + sync init + update \builder_inferedsdrtristate18__o $1\builder_inferedsdrtristate18__o[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:2521.5-2521.43" + process $proc$build/ls180/gateware/ls180.v:2521$3479 + assign { } { } + assign $1\builder_inferedsdrtristate18_oe[0:0] 1'0 + sync always + sync init + update \builder_inferedsdrtristate18_oe $1\builder_inferedsdrtristate18_oe[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:2524.5-2524.43" + process $proc$build/ls180/gateware/ls180.v:2524$3480 + assign { } { } + assign $1\builder_inferedsdrtristate19__o[0:0] 1'0 + sync always + sync init + update \builder_inferedsdrtristate19__o $1\builder_inferedsdrtristate19__o[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:2525.5-2525.43" + process $proc$build/ls180/gateware/ls180.v:2525$3481 + assign { } { } + assign $1\builder_inferedsdrtristate19_oe[0:0] 1'0 + sync always + sync init + update \builder_inferedsdrtristate19_oe $1\builder_inferedsdrtristate19_oe[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:2528.5-2528.43" + process $proc$build/ls180/gateware/ls180.v:2528$3482 + assign { } { } + assign $1\builder_inferedsdrtristate20__o[0:0] 1'0 + sync always + sync init + update \builder_inferedsdrtristate20__o $1\builder_inferedsdrtristate20__o[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:2529.5-2529.43" + process $proc$build/ls180/gateware/ls180.v:2529$3483 + assign { } { } + assign $1\builder_inferedsdrtristate20_oe[0:0] 1'0 + sync always + sync init + update \builder_inferedsdrtristate20_oe $1\builder_inferedsdrtristate20_oe[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:256.5-256.50" + process $proc$build/ls180/gateware/ls180.v:256$2644 + assign { } { } + assign $1\main_libresocsim_uart_rx_fifo_readable[0:0] 1'0 + sync always + sync init + update \main_libresocsim_uart_rx_fifo_readable $1\main_libresocsim_uart_rx_fifo_readable[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:2587.1-2592.4" + process $proc$build/ls180/gateware/ls180.v:2587$13 + assign { } { } + assign $0\main_libresocsim_libresoc_interrupt[15:0] [11:2] 10'0000000000 + assign $0\main_libresocsim_libresoc_interrupt[15:0] [15:12] { 1'0 \eint } + assign $0\main_libresocsim_libresoc_interrupt[15:0] [1] \main_libresocsim_timer_irq + assign $0\main_libresocsim_libresoc_interrupt[15:0] [0] \main_libresocsim_uart_irq + sync always + update \main_libresocsim_libresoc_interrupt $0\main_libresocsim_libresoc_interrupt[15:0] + end + attribute \src "build/ls180/gateware/ls180.v:2594.1-2604.4" + process $proc$build/ls180/gateware/ls180.v:2594$15 + assign { } { } + assign $0\main_libresocsim_interface0_converted_interface_dat_w[31:0] 0 + attribute \src "build/ls180/gateware/ls180.v:2596.2-2603.9" + switch \main_libresocsim_converter0_counter + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case 1'0 + assign $0\main_libresocsim_interface0_converted_interface_dat_w[31:0] \main_libresocsim_libresoc_ibus_dat_w [31:0] + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case 1'1 + assign $0\main_libresocsim_interface0_converted_interface_dat_w[31:0] \main_libresocsim_libresoc_ibus_dat_w [63:32] + case + end + sync always + update \main_libresocsim_interface0_converted_interface_dat_w $0\main_libresocsim_interface0_converted_interface_dat_w[31:0] + end + attribute \src "build/ls180/gateware/ls180.v:2606.1-2652.4" + process $proc$build/ls180/gateware/ls180.v:2606$16 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\main_libresocsim_converter0_skip[0:0] 1'0 + assign $0\main_libresocsim_libresoc_ibus_ack[0:0] 1'0 + assign { } { } + assign $0\main_libresocsim_converter0_counter_converter0_next_value[0:0] 1'0 + assign $0\main_libresocsim_converter0_counter_converter0_next_value_ce[0:0] 1'0 + assign $0\main_libresocsim_interface0_converted_interface_adr[29:0] 30'000000000000000000000000000000 + assign $0\main_libresocsim_interface0_converted_interface_sel[3:0] 4'0000 + assign $0\main_libresocsim_interface0_converted_interface_cyc[0:0] 1'0 + assign $0\main_libresocsim_interface0_converted_interface_stb[0:0] 1'0 + assign $0\main_libresocsim_interface0_converted_interface_we[0:0] 1'0 + assign $0\builder_converter0_next_state[0:0] \builder_converter0_state + attribute \src "build/ls180/gateware/ls180.v:2618.2-2651.9" + switch \builder_converter0_state + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case 1'1 + assign $0\main_libresocsim_interface0_converted_interface_adr[29:0] { \main_libresocsim_libresoc_ibus_adr \main_libresocsim_converter0_counter } + attribute \src "build/ls180/gateware/ls180.v:2621.4-2628.11" + switch \main_libresocsim_converter0_counter + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case 1'0 + assign $0\main_libresocsim_interface0_converted_interface_sel[3:0] \main_libresocsim_libresoc_ibus_sel [3:0] + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case 1'1 + assign $0\main_libresocsim_interface0_converted_interface_sel[3:0] \main_libresocsim_libresoc_ibus_sel [7:4] + case + end + attribute \src "build/ls180/gateware/ls180.v:2629.4-2642.7" + switch $and$build/ls180/gateware/ls180.v:2629$17_Y + attribute \src "build/ls180/gateware/ls180.v:2629.8-2629.81" + case 1'1 + assign $0\main_libresocsim_converter0_skip[0:0] $eq$build/ls180/gateware/ls180.v:2630$18_Y + assign $0\main_libresocsim_interface0_converted_interface_we[0:0] \main_libresocsim_libresoc_ibus_we + assign $0\main_libresocsim_interface0_converted_interface_cyc[0:0] $not$build/ls180/gateware/ls180.v:2632$19_Y + assign $0\main_libresocsim_interface0_converted_interface_stb[0:0] $not$build/ls180/gateware/ls180.v:2633$20_Y + attribute \src "build/ls180/gateware/ls180.v:2634.5-2641.8" + switch $or$build/ls180/gateware/ls180.v:2634$21_Y + attribute \src "build/ls180/gateware/ls180.v:2634.9-2634.97" + case 1'1 + assign $0\main_libresocsim_converter0_counter_converter0_next_value[0:0] $add$build/ls180/gateware/ls180.v:2635$22_Y + assign $0\main_libresocsim_converter0_counter_converter0_next_value_ce[0:0] 1'1 + attribute \src "build/ls180/gateware/ls180.v:2637.6-2640.9" + switch $eq$build/ls180/gateware/ls180.v:2637$23_Y + attribute \src "build/ls180/gateware/ls180.v:2637.10-2637.55" + case 1'1 + assign $0\main_libresocsim_libresoc_ibus_ack[0:0] 1'1 + assign $0\builder_converter0_next_state[0:0] 1'0 + case + end + case + end + case + end + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case + assign $0\main_libresocsim_converter0_counter_converter0_next_value[0:0] 1'0 + assign $0\main_libresocsim_converter0_counter_converter0_next_value_ce[0:0] 1'1 + attribute \src "build/ls180/gateware/ls180.v:2647.4-2649.7" + switch $and$build/ls180/gateware/ls180.v:2647$24_Y + attribute \src "build/ls180/gateware/ls180.v:2647.8-2647.81" + case 1'1 + assign $0\builder_converter0_next_state[0:0] 1'1 + case + end + end + sync always + update \main_libresocsim_libresoc_ibus_ack $0\main_libresocsim_libresoc_ibus_ack[0:0] + update \main_libresocsim_interface0_converted_interface_adr $0\main_libresocsim_interface0_converted_interface_adr[29:0] + update \main_libresocsim_interface0_converted_interface_sel $0\main_libresocsim_interface0_converted_interface_sel[3:0] + update \main_libresocsim_interface0_converted_interface_cyc $0\main_libresocsim_interface0_converted_interface_cyc[0:0] + update \main_libresocsim_interface0_converted_interface_stb $0\main_libresocsim_interface0_converted_interface_stb[0:0] + update \main_libresocsim_interface0_converted_interface_we $0\main_libresocsim_interface0_converted_interface_we[0:0] + update \main_libresocsim_converter0_skip $0\main_libresocsim_converter0_skip[0:0] + update \builder_converter0_next_state $0\builder_converter0_next_state[0:0] + update \main_libresocsim_converter0_counter_converter0_next_value $0\main_libresocsim_converter0_counter_converter0_next_value[0:0] + update \main_libresocsim_converter0_counter_converter0_next_value_ce $0\main_libresocsim_converter0_counter_converter0_next_value_ce[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:263.11-263.54" + process $proc$build/ls180/gateware/ls180.v:263$2645 + assign { } { } + assign $1\main_libresocsim_uart_rx_fifo_level0[4:0] 5'00000 + sync always + sync init + update \main_libresocsim_uart_rx_fifo_level0 $1\main_libresocsim_uart_rx_fifo_level0[4:0] + end + attribute \src "build/ls180/gateware/ls180.v:264.5-264.49" + process $proc$build/ls180/gateware/ls180.v:264$2646 + assign { } { } + assign $0\main_libresocsim_uart_rx_fifo_replace[0:0] 1'0 + sync always + update \main_libresocsim_uart_rx_fifo_replace $0\main_libresocsim_uart_rx_fifo_replace[0:0] + sync init + end + attribute \src "build/ls180/gateware/ls180.v:265.11-265.55" + process $proc$build/ls180/gateware/ls180.v:265$2647 + assign { } { } + assign $1\main_libresocsim_uart_rx_fifo_produce[3:0] 4'0000 + sync always + sync init + update \main_libresocsim_uart_rx_fifo_produce $1\main_libresocsim_uart_rx_fifo_produce[3:0] + end + attribute \src "build/ls180/gateware/ls180.v:2654.1-2664.4" + process $proc$build/ls180/gateware/ls180.v:2654$26 + assign { } { } + assign $0\main_libresocsim_interface1_converted_interface_dat_w[31:0] 0 + attribute \src "build/ls180/gateware/ls180.v:2656.2-2663.9" + switch \main_libresocsim_converter1_counter + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case 1'0 + assign $0\main_libresocsim_interface1_converted_interface_dat_w[31:0] \main_libresocsim_libresoc_dbus_dat_w [31:0] + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case 1'1 + assign $0\main_libresocsim_interface1_converted_interface_dat_w[31:0] \main_libresocsim_libresoc_dbus_dat_w [63:32] + case + end + sync always + update \main_libresocsim_interface1_converted_interface_dat_w $0\main_libresocsim_interface1_converted_interface_dat_w[31:0] + end + attribute \src "build/ls180/gateware/ls180.v:266.11-266.55" + process $proc$build/ls180/gateware/ls180.v:266$2648 + assign { } { } + assign $1\main_libresocsim_uart_rx_fifo_consume[3:0] 4'0000 + sync always + sync init + update \main_libresocsim_uart_rx_fifo_consume $1\main_libresocsim_uart_rx_fifo_consume[3:0] + end + attribute \src "build/ls180/gateware/ls180.v:2666.1-2712.4" + process $proc$build/ls180/gateware/ls180.v:2666$27 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\main_libresocsim_interface1_converted_interface_adr[29:0] 30'000000000000000000000000000000 + assign { } { } + assign $0\main_libresocsim_converter1_counter_converter1_next_value[0:0] 1'0 + assign $0\main_libresocsim_converter1_counter_converter1_next_value_ce[0:0] 1'0 + assign $0\main_libresocsim_interface1_converted_interface_sel[3:0] 4'0000 + assign $0\main_libresocsim_interface1_converted_interface_cyc[0:0] 1'0 + assign $0\main_libresocsim_interface1_converted_interface_stb[0:0] 1'0 + assign $0\main_libresocsim_libresoc_dbus_ack[0:0] 1'0 + assign $0\main_libresocsim_interface1_converted_interface_we[0:0] 1'0 + assign $0\main_libresocsim_converter1_skip[0:0] 1'0 + assign $0\builder_converter1_next_state[0:0] \builder_converter1_state + attribute \src "build/ls180/gateware/ls180.v:2678.2-2711.9" + switch \builder_converter1_state + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case 1'1 + assign $0\main_libresocsim_interface1_converted_interface_adr[29:0] { \main_libresocsim_libresoc_dbus_adr \main_libresocsim_converter1_counter } + attribute \src "build/ls180/gateware/ls180.v:2681.4-2688.11" + switch \main_libresocsim_converter1_counter + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case 1'0 + assign $0\main_libresocsim_interface1_converted_interface_sel[3:0] \main_libresocsim_libresoc_dbus_sel [3:0] + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case 1'1 + assign $0\main_libresocsim_interface1_converted_interface_sel[3:0] \main_libresocsim_libresoc_dbus_sel [7:4] + case + end + attribute \src "build/ls180/gateware/ls180.v:2689.4-2702.7" + switch $and$build/ls180/gateware/ls180.v:2689$28_Y + attribute \src "build/ls180/gateware/ls180.v:2689.8-2689.81" + case 1'1 + assign $0\main_libresocsim_converter1_skip[0:0] $eq$build/ls180/gateware/ls180.v:2690$29_Y + assign $0\main_libresocsim_interface1_converted_interface_we[0:0] \main_libresocsim_libresoc_dbus_we + assign $0\main_libresocsim_interface1_converted_interface_cyc[0:0] $not$build/ls180/gateware/ls180.v:2692$30_Y + assign $0\main_libresocsim_interface1_converted_interface_stb[0:0] $not$build/ls180/gateware/ls180.v:2693$31_Y + attribute \src "build/ls180/gateware/ls180.v:2694.5-2701.8" + switch $or$build/ls180/gateware/ls180.v:2694$32_Y + attribute \src "build/ls180/gateware/ls180.v:2694.9-2694.97" + case 1'1 + assign $0\main_libresocsim_converter1_counter_converter1_next_value[0:0] $add$build/ls180/gateware/ls180.v:2695$33_Y + assign $0\main_libresocsim_converter1_counter_converter1_next_value_ce[0:0] 1'1 + attribute \src "build/ls180/gateware/ls180.v:2697.6-2700.9" + switch $eq$build/ls180/gateware/ls180.v:2697$34_Y + attribute \src "build/ls180/gateware/ls180.v:2697.10-2697.55" + case 1'1 + assign $0\main_libresocsim_libresoc_dbus_ack[0:0] 1'1 + assign $0\builder_converter1_next_state[0:0] 1'0 + case + end + case + end + case + end + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case + assign $0\main_libresocsim_converter1_counter_converter1_next_value[0:0] 1'0 + assign $0\main_libresocsim_converter1_counter_converter1_next_value_ce[0:0] 1'1 + attribute \src "build/ls180/gateware/ls180.v:2707.4-2709.7" + switch $and$build/ls180/gateware/ls180.v:2707$35_Y + attribute \src "build/ls180/gateware/ls180.v:2707.8-2707.81" + case 1'1 + assign $0\builder_converter1_next_state[0:0] 1'1 + case + end + end + sync always + update \main_libresocsim_libresoc_dbus_ack $0\main_libresocsim_libresoc_dbus_ack[0:0] + update \main_libresocsim_interface1_converted_interface_adr $0\main_libresocsim_interface1_converted_interface_adr[29:0] + update \main_libresocsim_interface1_converted_interface_sel $0\main_libresocsim_interface1_converted_interface_sel[3:0] + update \main_libresocsim_interface1_converted_interface_cyc $0\main_libresocsim_interface1_converted_interface_cyc[0:0] + update \main_libresocsim_interface1_converted_interface_stb $0\main_libresocsim_interface1_converted_interface_stb[0:0] + update \main_libresocsim_interface1_converted_interface_we $0\main_libresocsim_interface1_converted_interface_we[0:0] + update \main_libresocsim_converter1_skip $0\main_libresocsim_converter1_skip[0:0] + update \builder_converter1_next_state $0\builder_converter1_next_state[0:0] + update \main_libresocsim_converter1_counter_converter1_next_value $0\main_libresocsim_converter1_counter_converter1_next_value[0:0] + update \main_libresocsim_converter1_counter_converter1_next_value_ce $0\main_libresocsim_converter1_counter_converter1_next_value_ce[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:267.11-267.58" + process $proc$build/ls180/gateware/ls180.v:267$2649 + assign { } { } + assign $1\main_libresocsim_uart_rx_fifo_wrport_adr[3:0] 4'0000 + sync always + sync init + update \main_libresocsim_uart_rx_fifo_wrport_adr $1\main_libresocsim_uart_rx_fifo_wrport_adr[3:0] + end + attribute \src "build/ls180/gateware/ls180.v:2715.1-2721.4" + process $proc$build/ls180/gateware/ls180.v:2715$36 + assign { } { } + assign { } { } + assign $0\main_libresocsim_we[3:0] [0] $and$build/ls180/gateware/ls180.v:2717$39_Y + assign $0\main_libresocsim_we[3:0] [1] $and$build/ls180/gateware/ls180.v:2718$42_Y + assign $0\main_libresocsim_we[3:0] [2] $and$build/ls180/gateware/ls180.v:2719$45_Y + assign $0\main_libresocsim_we[3:0] [3] $and$build/ls180/gateware/ls180.v:2720$48_Y + sync always + update \main_libresocsim_we $0\main_libresocsim_we[3:0] + end + attribute \src "build/ls180/gateware/ls180.v:2755.1-2760.4" + process $proc$build/ls180/gateware/ls180.v:2755$57 + assign { } { } + assign $0\main_libresocsim_uart_tx_clear[0:0] 1'0 + attribute \src "build/ls180/gateware/ls180.v:2757.2-2759.5" + switch $and$build/ls180/gateware/ls180.v:2757$58_Y + attribute \src "build/ls180/gateware/ls180.v:2757.6-2757.103" + case 1'1 + assign $0\main_libresocsim_uart_tx_clear[0:0] 1'1 + case + end + sync always + update \main_libresocsim_uart_tx_clear $0\main_libresocsim_uart_tx_clear[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:2761.1-2765.4" + process $proc$build/ls180/gateware/ls180.v:2761$59 + assign { } { } + assign { } { } + assign $0\main_libresocsim_uart_eventmanager_status_w[1:0] [0] \main_libresocsim_uart_tx_status + assign $0\main_libresocsim_uart_eventmanager_status_w[1:0] [1] \main_libresocsim_uart_rx_status + sync always + update \main_libresocsim_uart_eventmanager_status_w $0\main_libresocsim_uart_eventmanager_status_w[1:0] + end + attribute \src "build/ls180/gateware/ls180.v:2766.1-2771.4" + process $proc$build/ls180/gateware/ls180.v:2766$60 + assign { } { } + assign $0\main_libresocsim_uart_rx_clear[0:0] 1'0 + attribute \src "build/ls180/gateware/ls180.v:2768.2-2770.5" + switch $and$build/ls180/gateware/ls180.v:2768$61_Y + attribute \src "build/ls180/gateware/ls180.v:2768.6-2768.103" + case 1'1 + assign $0\main_libresocsim_uart_rx_clear[0:0] 1'1 + case + end + sync always + update \main_libresocsim_uart_rx_clear $0\main_libresocsim_uart_rx_clear[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:2772.1-2776.4" + process $proc$build/ls180/gateware/ls180.v:2772$62 + assign { } { } + assign { } { } + assign $0\main_libresocsim_uart_eventmanager_pending_w[1:0] [0] \main_libresocsim_uart_tx_pending + assign $0\main_libresocsim_uart_eventmanager_pending_w[1:0] [1] \main_libresocsim_uart_rx_pending + sync always + update \main_libresocsim_uart_eventmanager_pending_w $0\main_libresocsim_uart_eventmanager_pending_w[1:0] + end + attribute \src "build/ls180/gateware/ls180.v:2794.1-2801.4" + process $proc$build/ls180/gateware/ls180.v:2794$70 + assign { } { } + assign $0\main_libresocsim_uart_tx_fifo_wrport_adr[3:0] 4'0000 + attribute \src "build/ls180/gateware/ls180.v:2796.2-2800.5" + switch \main_libresocsim_uart_tx_fifo_replace + attribute \src "build/ls180/gateware/ls180.v:2796.6-2796.43" + case 1'1 + assign $0\main_libresocsim_uart_tx_fifo_wrport_adr[3:0] $sub$build/ls180/gateware/ls180.v:2797$71_Y + attribute \src "build/ls180/gateware/ls180.v:2798.6-2798.10" + case + assign $0\main_libresocsim_uart_tx_fifo_wrport_adr[3:0] \main_libresocsim_uart_tx_fifo_produce + end + sync always + update \main_libresocsim_uart_tx_fifo_wrport_adr $0\main_libresocsim_uart_tx_fifo_wrport_adr[3:0] + end + attribute \src "build/ls180/gateware/ls180.v:282.5-282.39" + process $proc$build/ls180/gateware/ls180.v:282$2650 + assign { } { } + assign $0\main_libresocsim_uart_reset[0:0] 1'0 + sync always + update \main_libresocsim_uart_reset $0\main_libresocsim_uart_reset[0:0] + sync init + end + attribute \src "build/ls180/gateware/ls180.v:2824.1-2831.4" + process $proc$build/ls180/gateware/ls180.v:2824$81 + assign { } { } + assign $0\main_libresocsim_uart_rx_fifo_wrport_adr[3:0] 4'0000 + attribute \src "build/ls180/gateware/ls180.v:2826.2-2830.5" + switch \main_libresocsim_uart_rx_fifo_replace + attribute \src "build/ls180/gateware/ls180.v:2826.6-2826.43" + case 1'1 + assign $0\main_libresocsim_uart_rx_fifo_wrport_adr[3:0] $sub$build/ls180/gateware/ls180.v:2827$82_Y + attribute \src "build/ls180/gateware/ls180.v:2828.6-2828.10" + case + assign $0\main_libresocsim_uart_rx_fifo_wrport_adr[3:0] \main_libresocsim_uart_rx_fifo_produce + end + sync always + update \main_libresocsim_uart_rx_fifo_wrport_adr $0\main_libresocsim_uart_rx_fifo_wrport_adr[3:0] + end + attribute \src "build/ls180/gateware/ls180.v:283.12-283.55" + process $proc$build/ls180/gateware/ls180.v:283$2651 + assign { } { } + assign $1\main_libresocsim_timer_load_storage[31:0] 0 + sync always + sync init + update \main_libresocsim_timer_load_storage $1\main_libresocsim_timer_load_storage[31:0] + end + attribute \src "build/ls180/gateware/ls180.v:284.5-284.42" + process $proc$build/ls180/gateware/ls180.v:284$2652 + assign { } { } + assign $1\main_libresocsim_timer_load_re[0:0] 1'0 + sync always + sync init + update \main_libresocsim_timer_load_re $1\main_libresocsim_timer_load_re[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:2842.1-2847.4" + process $proc$build/ls180/gateware/ls180.v:2842$89 + assign { } { } + assign $0\main_libresocsim_timer_zero_clear[0:0] 1'0 + attribute \src "build/ls180/gateware/ls180.v:2844.2-2846.5" + switch $and$build/ls180/gateware/ls180.v:2844$90_Y + attribute \src "build/ls180/gateware/ls180.v:2844.6-2844.102" + case 1'1 + assign $0\main_libresocsim_timer_zero_clear[0:0] 1'1 + case + end + sync always + update \main_libresocsim_timer_zero_clear $0\main_libresocsim_timer_zero_clear[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:285.12-285.57" + process $proc$build/ls180/gateware/ls180.v:285$2653 + assign { } { } + assign $1\main_libresocsim_timer_reload_storage[31:0] 0 + sync always + sync init + update \main_libresocsim_timer_reload_storage $1\main_libresocsim_timer_reload_storage[31:0] + end + attribute \src "build/ls180/gateware/ls180.v:2854.1-2858.4" + process $proc$build/ls180/gateware/ls180.v:2854$92 + assign { } { } + assign { } { } + assign $0\sdram_dm[1:0] [0] 1'0 + assign $0\sdram_dm[1:0] [1] 1'0 + sync always + update \sdram_dm $0\sdram_dm[1:0] + end + attribute \src "build/ls180/gateware/ls180.v:286.5-286.44" + process $proc$build/ls180/gateware/ls180.v:286$2654 + assign { } { } + assign $1\main_libresocsim_timer_reload_re[0:0] 1'0 + sync always + sync init + update \main_libresocsim_timer_reload_re $1\main_libresocsim_timer_reload_re[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:287.5-287.45" + process $proc$build/ls180/gateware/ls180.v:287$2655 + assign { } { } + assign $1\main_libresocsim_timer_en_storage[0:0] 1'0 + sync always + sync init + update \main_libresocsim_timer_en_storage $1\main_libresocsim_timer_en_storage[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:288.5-288.40" + process $proc$build/ls180/gateware/ls180.v:288$2656 + assign { } { } + assign $1\main_libresocsim_timer_en_re[0:0] 1'0 + sync always + sync init + update \main_libresocsim_timer_en_re $1\main_libresocsim_timer_en_re[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:289.5-289.55" + process $proc$build/ls180/gateware/ls180.v:289$2657 + assign { } { } + assign $1\main_libresocsim_timer_update_value_storage[0:0] 1'0 + sync always + sync init + update \main_libresocsim_timer_update_value_storage $1\main_libresocsim_timer_update_value_storage[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:2891.1-2945.4" + process $proc$build/ls180/gateware/ls180.v:2891$93 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\main_sdram_master_p0_cs_n[0:0] 1'1 + assign $0\main_sdram_master_p0_ras_n[0:0] 1'1 + assign $0\main_sdram_master_p0_we_n[0:0] 1'1 + assign $0\main_sdram_master_p0_cke[0:0] 1'0 + assign $0\main_sdram_master_p0_odt[0:0] 1'0 + assign $0\main_sdram_master_p0_reset_n[0:0] 1'0 + assign $0\main_sdram_master_p0_act_n[0:0] 1'1 + assign $0\main_sdram_inti_p0_rddata[15:0] 16'0000000000000000 + assign $0\main_sdram_master_p0_wrdata[15:0] 16'0000000000000000 + assign $0\main_sdram_inti_p0_rddata_valid[0:0] 1'0 + assign $0\main_sdram_master_p0_wrdata_en[0:0] 1'0 + assign $0\main_sdram_master_p0_wrdata_mask[1:0] 2'00 + assign $0\main_sdram_master_p0_rddata_en[0:0] 1'0 + assign $0\main_sdram_slave_p0_rddata[15:0] 16'0000000000000000 + assign $0\main_sdram_slave_p0_rddata_valid[0:0] 1'0 + assign $0\main_sdram_master_p0_address[12:0] 13'0000000000000 + assign $0\main_sdram_master_p0_bank[1:0] 2'00 + assign $0\main_sdram_master_p0_cas_n[0:0] 1'1 + attribute \src "build/ls180/gateware/ls180.v:2910.2-2944.5" + switch \main_sdram_sel + attribute \src "build/ls180/gateware/ls180.v:2910.6-2910.20" + case 1'1 + assign $0\main_sdram_master_p0_address[12:0] \main_sdram_slave_p0_address + assign $0\main_sdram_master_p0_bank[1:0] \main_sdram_slave_p0_bank + assign $0\main_sdram_master_p0_cas_n[0:0] \main_sdram_slave_p0_cas_n + assign $0\main_sdram_master_p0_cs_n[0:0] \main_sdram_slave_p0_cs_n + assign $0\main_sdram_master_p0_ras_n[0:0] \main_sdram_slave_p0_ras_n + assign $0\main_sdram_master_p0_we_n[0:0] \main_sdram_slave_p0_we_n + assign $0\main_sdram_master_p0_cke[0:0] \main_sdram_slave_p0_cke + assign $0\main_sdram_master_p0_odt[0:0] \main_sdram_slave_p0_odt + assign $0\main_sdram_master_p0_reset_n[0:0] \main_sdram_slave_p0_reset_n + assign $0\main_sdram_master_p0_act_n[0:0] \main_sdram_slave_p0_act_n + assign $0\main_sdram_master_p0_wrdata[15:0] \main_sdram_slave_p0_wrdata + assign $0\main_sdram_master_p0_wrdata_en[0:0] \main_sdram_slave_p0_wrdata_en + assign $0\main_sdram_master_p0_wrdata_mask[1:0] \main_sdram_slave_p0_wrdata_mask + assign $0\main_sdram_master_p0_rddata_en[0:0] \main_sdram_slave_p0_rddata_en + assign $0\main_sdram_slave_p0_rddata[15:0] \main_sdram_master_p0_rddata + assign $0\main_sdram_slave_p0_rddata_valid[0:0] \main_sdram_master_p0_rddata_valid + attribute \src "build/ls180/gateware/ls180.v:2927.6-2927.10" + case + assign $0\main_sdram_master_p0_address[12:0] \main_sdram_inti_p0_address + assign $0\main_sdram_master_p0_bank[1:0] \main_sdram_inti_p0_bank + assign $0\main_sdram_master_p0_cas_n[0:0] \main_sdram_inti_p0_cas_n + assign $0\main_sdram_master_p0_cs_n[0:0] \main_sdram_inti_p0_cs_n + assign $0\main_sdram_master_p0_ras_n[0:0] \main_sdram_inti_p0_ras_n + assign $0\main_sdram_master_p0_we_n[0:0] \main_sdram_inti_p0_we_n + assign $0\main_sdram_master_p0_cke[0:0] \main_sdram_inti_p0_cke + assign $0\main_sdram_master_p0_odt[0:0] \main_sdram_inti_p0_odt + assign $0\main_sdram_master_p0_reset_n[0:0] \main_sdram_inti_p0_reset_n + assign $0\main_sdram_master_p0_act_n[0:0] \main_sdram_inti_p0_act_n + assign $0\main_sdram_master_p0_wrdata[15:0] \main_sdram_inti_p0_wrdata + assign $0\main_sdram_master_p0_wrdata_en[0:0] \main_sdram_inti_p0_wrdata_en + assign $0\main_sdram_master_p0_wrdata_mask[1:0] \main_sdram_inti_p0_wrdata_mask + assign $0\main_sdram_master_p0_rddata_en[0:0] \main_sdram_inti_p0_rddata_en + assign $0\main_sdram_inti_p0_rddata[15:0] \main_sdram_master_p0_rddata + assign $0\main_sdram_inti_p0_rddata_valid[0:0] \main_sdram_master_p0_rddata_valid + end + sync always + update \main_sdram_inti_p0_rddata $0\main_sdram_inti_p0_rddata[15:0] + update \main_sdram_inti_p0_rddata_valid $0\main_sdram_inti_p0_rddata_valid[0:0] + update \main_sdram_slave_p0_rddata $0\main_sdram_slave_p0_rddata[15:0] + update \main_sdram_slave_p0_rddata_valid $0\main_sdram_slave_p0_rddata_valid[0:0] + update \main_sdram_master_p0_address $0\main_sdram_master_p0_address[12:0] + update \main_sdram_master_p0_bank $0\main_sdram_master_p0_bank[1:0] + update \main_sdram_master_p0_cas_n $0\main_sdram_master_p0_cas_n[0:0] + update \main_sdram_master_p0_cs_n $0\main_sdram_master_p0_cs_n[0:0] + update \main_sdram_master_p0_ras_n $0\main_sdram_master_p0_ras_n[0:0] + update \main_sdram_master_p0_we_n $0\main_sdram_master_p0_we_n[0:0] + update \main_sdram_master_p0_cke $0\main_sdram_master_p0_cke[0:0] + update \main_sdram_master_p0_odt $0\main_sdram_master_p0_odt[0:0] + update \main_sdram_master_p0_reset_n $0\main_sdram_master_p0_reset_n[0:0] + update \main_sdram_master_p0_act_n $0\main_sdram_master_p0_act_n[0:0] + update \main_sdram_master_p0_wrdata $0\main_sdram_master_p0_wrdata[15:0] + update \main_sdram_master_p0_wrdata_en $0\main_sdram_master_p0_wrdata_en[0:0] + update \main_sdram_master_p0_wrdata_mask $0\main_sdram_master_p0_wrdata_mask[1:0] + update \main_sdram_master_p0_rddata_en $0\main_sdram_master_p0_rddata_en[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:290.5-290.50" + process $proc$build/ls180/gateware/ls180.v:290$2658 + assign { } { } + assign $1\main_libresocsim_timer_update_value_re[0:0] 1'0 + sync always + sync init + update \main_libresocsim_timer_update_value_re $1\main_libresocsim_timer_update_value_re[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:291.12-291.55" + process $proc$build/ls180/gateware/ls180.v:291$2659 + assign { } { } + assign $1\main_libresocsim_timer_value_status[31:0] 0 + sync always + sync init + update \main_libresocsim_timer_value_status $1\main_libresocsim_timer_value_status[31:0] + end + attribute \src "build/ls180/gateware/ls180.v:2949.1-2965.4" + process $proc$build/ls180/gateware/ls180.v:2949$94 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\main_sdram_inti_p0_ras_n[0:0] 1'1 + assign $0\main_sdram_inti_p0_we_n[0:0] 1'1 + assign $0\main_sdram_inti_p0_cas_n[0:0] 1'1 + assign $0\main_sdram_inti_p0_cs_n[0:0] 1'1 + attribute \src "build/ls180/gateware/ls180.v:2954.2-2964.5" + switch \main_sdram_command_issue_re + attribute \src "build/ls180/gateware/ls180.v:2954.6-2954.33" + case 1'1 + assign $0\main_sdram_inti_p0_cs_n[0:0] $not$build/ls180/gateware/ls180.v:2955$95_Y + assign $0\main_sdram_inti_p0_we_n[0:0] $not$build/ls180/gateware/ls180.v:2956$96_Y + assign $0\main_sdram_inti_p0_cas_n[0:0] $not$build/ls180/gateware/ls180.v:2957$97_Y + assign $0\main_sdram_inti_p0_ras_n[0:0] $not$build/ls180/gateware/ls180.v:2958$98_Y + attribute \src "build/ls180/gateware/ls180.v:2959.6-2959.10" + case + assign $0\main_sdram_inti_p0_cs_n[0:0] 1'1 + assign $0\main_sdram_inti_p0_we_n[0:0] 1'1 + assign $0\main_sdram_inti_p0_cas_n[0:0] 1'1 + assign $0\main_sdram_inti_p0_ras_n[0:0] 1'1 + end + sync always + update \main_sdram_inti_p0_cas_n $0\main_sdram_inti_p0_cas_n[0:0] + update \main_sdram_inti_p0_cs_n $0\main_sdram_inti_p0_cs_n[0:0] + update \main_sdram_inti_p0_ras_n $0\main_sdram_inti_p0_ras_n[0:0] + update \main_sdram_inti_p0_we_n $0\main_sdram_inti_p0_we_n[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:295.5-295.47" + process $proc$build/ls180/gateware/ls180.v:295$2660 + assign { } { } + assign $1\main_libresocsim_timer_zero_pending[0:0] 1'0 + sync always + sync init + update \main_libresocsim_timer_zero_pending $1\main_libresocsim_timer_zero_pending[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:297.5-297.45" + process $proc$build/ls180/gateware/ls180.v:297$2661 + assign { } { } + assign $1\main_libresocsim_timer_zero_clear[0:0] 1'0 + sync always + sync init + update \main_libresocsim_timer_zero_clear $1\main_libresocsim_timer_zero_clear[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:298.5-298.51" + process $proc$build/ls180/gateware/ls180.v:298$2662 + assign { } { } + assign $1\main_libresocsim_timer_zero_old_trigger[0:0] 1'0 + sync always + sync init + update \main_libresocsim_timer_zero_old_trigger $1\main_libresocsim_timer_zero_old_trigger[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:3008.1-3038.4" + process $proc$build/ls180/gateware/ls180.v:3008$107 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\main_sdram_cmd_last[0:0] 1'0 + assign $0\main_sdram_sequencer_start0[0:0] 1'0 + assign { } { } + assign $0\main_sdram_cmd_valid[0:0] 1'0 + assign $0\builder_refresher_next_state[1:0] \builder_refresher_state + attribute \src "build/ls180/gateware/ls180.v:3014.2-3037.9" + switch \builder_refresher_state + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case 2'01 + assign $0\main_sdram_cmd_valid[0:0] 1'1 + attribute \src "build/ls180/gateware/ls180.v:3017.4-3020.7" + switch \main_sdram_cmd_ready + attribute \src "build/ls180/gateware/ls180.v:3017.8-3017.28" + case 1'1 + assign $0\main_sdram_sequencer_start0[0:0] 1'1 + assign $0\builder_refresher_next_state[1:0] 2'10 + case + end + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case 2'10 + assign $0\main_sdram_cmd_valid[0:0] 1'1 + attribute \src "build/ls180/gateware/ls180.v:3024.4-3028.7" + switch \main_sdram_sequencer_done0 + attribute \src "build/ls180/gateware/ls180.v:3024.8-3024.34" + case 1'1 + assign $0\main_sdram_cmd_valid[0:0] 1'0 + assign $0\main_sdram_cmd_last[0:0] 1'1 + assign $0\builder_refresher_next_state[1:0] 2'00 + case + end + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case + attribute \src "build/ls180/gateware/ls180.v:3031.4-3035.7" + switch 1'1 + attribute \src "build/ls180/gateware/ls180.v:3031.8-3031.12" + case 1'1 + attribute \src "build/ls180/gateware/ls180.v:3032.5-3034.8" + switch \main_sdram_wants_refresh + attribute \src "build/ls180/gateware/ls180.v:3032.9-3032.33" + case 1'1 + assign $0\builder_refresher_next_state[1:0] 2'01 + case + end + case + end + end + sync always + update \main_sdram_cmd_valid $0\main_sdram_cmd_valid[0:0] + update \main_sdram_cmd_last $0\main_sdram_cmd_last[0:0] + update \main_sdram_sequencer_start0 $0\main_sdram_sequencer_start0[0:0] + update \builder_refresher_next_state $0\builder_refresher_next_state[1:0] + end + attribute \src "build/ls180/gateware/ls180.v:3053.1-3060.4" + process $proc$build/ls180/gateware/ls180.v:3053$111 + assign { } { } + assign $0\main_sdram_bankmachine0_cmd_payload_a[12:0] 13'0000000000000 + attribute \src "build/ls180/gateware/ls180.v:3055.2-3059.5" + switch \main_sdram_bankmachine0_row_col_n_addr_sel + attribute \src "build/ls180/gateware/ls180.v:3055.6-3055.48" + case 1'1 + assign $0\main_sdram_bankmachine0_cmd_payload_a[12:0] \main_sdram_bankmachine0_cmd_buffer_source_payload_addr [21:9] + attribute \src "build/ls180/gateware/ls180.v:3057.6-3057.10" + case + assign $0\main_sdram_bankmachine0_cmd_payload_a[12:0] $or$build/ls180/gateware/ls180.v:3058$113_Y + end + sync always + update \main_sdram_bankmachine0_cmd_payload_a $0\main_sdram_bankmachine0_cmd_payload_a[12:0] + end + attribute \src "build/ls180/gateware/ls180.v:3064.1-3071.4" + process $proc$build/ls180/gateware/ls180.v:3064$120 + assign { } { } + assign $0\main_sdram_bankmachine0_auto_precharge[0:0] 1'0 + attribute \src "build/ls180/gateware/ls180.v:3066.2-3070.5" + switch $and$build/ls180/gateware/ls180.v:3066$121_Y + attribute \src "build/ls180/gateware/ls180.v:3066.6-3066.115" + case 1'1 + attribute \src "build/ls180/gateware/ls180.v:3067.3-3069.6" + switch $ne$build/ls180/gateware/ls180.v:3067$122_Y + attribute \src "build/ls180/gateware/ls180.v:3067.7-3067.143" + case 1'1 + assign $0\main_sdram_bankmachine0_auto_precharge[0:0] $eq$build/ls180/gateware/ls180.v:3068$123_Y + case + end + case + end + sync always + update \main_sdram_bankmachine0_auto_precharge $0\main_sdram_bankmachine0_auto_precharge[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:307.5-307.55" + process $proc$build/ls180/gateware/ls180.v:307$2663 + assign { } { } + assign $1\main_libresocsim_timer_eventmanager_storage[0:0] 1'0 + sync always + sync init + update \main_libresocsim_timer_eventmanager_storage $1\main_libresocsim_timer_eventmanager_storage[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:308.5-308.50" + process $proc$build/ls180/gateware/ls180.v:308$2664 + assign { } { } + assign $1\main_libresocsim_timer_eventmanager_re[0:0] 1'0 + sync always + sync init + update \main_libresocsim_timer_eventmanager_re $1\main_libresocsim_timer_eventmanager_re[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:3086.1-3093.4" + process $proc$build/ls180/gateware/ls180.v:3086$124 + assign { } { } + assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr[2:0] 3'000 + attribute \src "build/ls180/gateware/ls180.v:3088.2-3092.5" + switch \main_sdram_bankmachine0_cmd_buffer_lookahead_replace + attribute \src "build/ls180/gateware/ls180.v:3088.6-3088.58" + case 1'1 + assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr[2:0] $sub$build/ls180/gateware/ls180.v:3089$125_Y + attribute \src "build/ls180/gateware/ls180.v:3090.6-3090.10" + case + assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr[2:0] \main_sdram_bankmachine0_cmd_buffer_lookahead_produce + end + sync always + update \main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr $0\main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr[2:0] + end + attribute \src "build/ls180/gateware/ls180.v:309.12-309.48" + process $proc$build/ls180/gateware/ls180.v:309$2665 + assign { } { } + assign $1\main_libresocsim_timer_value[31:0] 0 + sync always + sync init + update \main_libresocsim_timer_value $1\main_libresocsim_timer_value[31:0] + end + attribute \src "build/ls180/gateware/ls180.v:3102.1-3195.4" + process $proc$build/ls180/gateware/ls180.v:3102$133 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\main_sdram_bankmachine0_row_close[0:0] 1'0 + assign $0\main_sdram_bankmachine0_cmd_payload_cas[0:0] 1'0 + assign $0\main_sdram_bankmachine0_cmd_payload_ras[0:0] 1'0 + assign $0\main_sdram_bankmachine0_cmd_payload_we[0:0] 1'0 + assign $0\main_sdram_bankmachine0_row_col_n_addr_sel[0:0] 1'0 + assign $0\main_sdram_bankmachine0_cmd_payload_is_cmd[0:0] 1'0 + assign $0\main_sdram_bankmachine0_cmd_payload_is_read[0:0] 1'0 + assign $0\main_sdram_bankmachine0_cmd_payload_is_write[0:0] 1'0 + assign $0\main_sdram_bankmachine0_req_wdata_ready[0:0] 1'0 + assign $0\main_sdram_bankmachine0_req_rdata_valid[0:0] 1'0 + assign { } { } + assign $0\main_sdram_bankmachine0_refresh_gnt[0:0] 1'0 + assign $0\main_sdram_bankmachine0_cmd_valid[0:0] 1'0 + assign $0\main_sdram_bankmachine0_row_open[0:0] 1'0 + assign $0\builder_bankmachine0_next_state[2:0] \builder_bankmachine0_state + attribute \src "build/ls180/gateware/ls180.v:3118.2-3194.9" + switch \builder_bankmachine0_state + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case 3'001 + assign $0\main_sdram_bankmachine0_row_close[0:0] 1'1 + attribute \src "build/ls180/gateware/ls180.v:3120.4-3128.7" + switch $and$build/ls180/gateware/ls180.v:3120$134_Y + attribute \src "build/ls180/gateware/ls180.v:3120.8-3120.87" + case 1'1 + assign $0\main_sdram_bankmachine0_cmd_valid[0:0] 1'1 + assign $0\main_sdram_bankmachine0_cmd_payload_ras[0:0] 1'1 + assign $0\main_sdram_bankmachine0_cmd_payload_we[0:0] 1'1 + assign $0\main_sdram_bankmachine0_cmd_payload_is_cmd[0:0] 1'1 + attribute \src "build/ls180/gateware/ls180.v:3122.5-3124.8" + switch \main_sdram_bankmachine0_cmd_ready + attribute \src "build/ls180/gateware/ls180.v:3122.9-3122.42" + case 1'1 + assign $0\builder_bankmachine0_next_state[2:0] 3'101 + case + end + case + end + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case 3'010 + assign $0\main_sdram_bankmachine0_row_close[0:0] 1'1 + attribute \src "build/ls180/gateware/ls180.v:3132.4-3134.7" + switch $and$build/ls180/gateware/ls180.v:3132$135_Y + attribute \src "build/ls180/gateware/ls180.v:3132.8-3132.87" + case 1'1 + assign $0\builder_bankmachine0_next_state[2:0] 3'101 + case + end + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case 3'011 + attribute \src "build/ls180/gateware/ls180.v:3138.4-3147.7" + switch \main_sdram_bankmachine0_trccon_ready + attribute \src "build/ls180/gateware/ls180.v:3138.8-3138.44" + case 1'1 + assign $0\main_sdram_bankmachine0_row_col_n_addr_sel[0:0] 1'1 + assign $0\main_sdram_bankmachine0_row_open[0:0] 1'1 + assign $0\main_sdram_bankmachine0_cmd_valid[0:0] 1'1 + assign $0\main_sdram_bankmachine0_cmd_payload_is_cmd[0:0] 1'1 + assign $0\main_sdram_bankmachine0_cmd_payload_ras[0:0] 1'1 + attribute \src "build/ls180/gateware/ls180.v:3143.5-3145.8" + switch \main_sdram_bankmachine0_cmd_ready + attribute \src "build/ls180/gateware/ls180.v:3143.9-3143.42" + case 1'1 + assign $0\builder_bankmachine0_next_state[2:0] 3'110 + case + end + case + end + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case 3'100 + assign $0\main_sdram_bankmachine0_row_close[0:0] 1'1 + assign $0\main_sdram_bankmachine0_cmd_payload_is_cmd[0:0] 1'1 + attribute \src "build/ls180/gateware/ls180.v:3150.4-3152.7" + switch \main_sdram_bankmachine0_twtpcon_ready + attribute \src "build/ls180/gateware/ls180.v:3150.8-3150.45" + case 1'1 + assign $0\main_sdram_bankmachine0_refresh_gnt[0:0] 1'1 + case + end + attribute \src "build/ls180/gateware/ls180.v:3155.4-3157.7" + switch $not$build/ls180/gateware/ls180.v:3155$136_Y + attribute \src "build/ls180/gateware/ls180.v:3155.8-3155.46" + case 1'1 + assign $0\builder_bankmachine0_next_state[2:0] 3'000 + case + end + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case 3'101 + assign $0\builder_bankmachine0_next_state[2:0] 3'011 + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case 3'110 + assign $0\builder_bankmachine0_next_state[2:0] 3'000 + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case + attribute \src "build/ls180/gateware/ls180.v:3166.4-3192.7" + switch \main_sdram_bankmachine0_refresh_req + attribute \src "build/ls180/gateware/ls180.v:3166.8-3166.43" + case 1'1 + assign $0\builder_bankmachine0_next_state[2:0] 3'100 + attribute \src "build/ls180/gateware/ls180.v:3168.8-3168.12" + case + attribute \src "build/ls180/gateware/ls180.v:3169.5-3191.8" + switch \main_sdram_bankmachine0_cmd_buffer_source_valid + attribute \src "build/ls180/gateware/ls180.v:3169.9-3169.56" + case 1'1 + attribute \src "build/ls180/gateware/ls180.v:3170.6-3190.9" + switch \main_sdram_bankmachine0_row_opened + attribute \src "build/ls180/gateware/ls180.v:3170.10-3170.44" + case 1'1 + attribute \src "build/ls180/gateware/ls180.v:3171.7-3187.10" + switch \main_sdram_bankmachine0_row_hit + attribute \src "build/ls180/gateware/ls180.v:3171.11-3171.42" + case 1'1 + assign $0\main_sdram_bankmachine0_cmd_valid[0:0] 1'1 + assign $0\main_sdram_bankmachine0_cmd_payload_cas[0:0] 1'1 + attribute \src "build/ls180/gateware/ls180.v:3173.8-3180.11" + switch \main_sdram_bankmachine0_cmd_buffer_source_payload_we + attribute \src "build/ls180/gateware/ls180.v:3173.12-3173.64" + case 1'1 + assign $0\main_sdram_bankmachine0_req_wdata_ready[0:0] \main_sdram_bankmachine0_cmd_ready + assign $0\main_sdram_bankmachine0_cmd_payload_is_write[0:0] 1'1 + assign $0\main_sdram_bankmachine0_cmd_payload_we[0:0] 1'1 + attribute \src "build/ls180/gateware/ls180.v:3177.12-3177.16" + case + assign $0\main_sdram_bankmachine0_req_rdata_valid[0:0] \main_sdram_bankmachine0_cmd_ready + assign $0\main_sdram_bankmachine0_cmd_payload_is_read[0:0] 1'1 + end + attribute \src "build/ls180/gateware/ls180.v:3182.8-3184.11" + switch $and$build/ls180/gateware/ls180.v:3182$137_Y + attribute \src "build/ls180/gateware/ls180.v:3182.12-3182.88" + case 1'1 + assign $0\builder_bankmachine0_next_state[2:0] 3'010 + case + end + attribute \src "build/ls180/gateware/ls180.v:3185.11-3185.15" + case + assign $0\builder_bankmachine0_next_state[2:0] 3'001 + end + attribute \src "build/ls180/gateware/ls180.v:3188.10-3188.14" + case + assign $0\builder_bankmachine0_next_state[2:0] 3'011 + end + case + end + end + end + sync always + update \main_sdram_bankmachine0_req_wdata_ready $0\main_sdram_bankmachine0_req_wdata_ready[0:0] + update \main_sdram_bankmachine0_req_rdata_valid $0\main_sdram_bankmachine0_req_rdata_valid[0:0] + update \main_sdram_bankmachine0_refresh_gnt $0\main_sdram_bankmachine0_refresh_gnt[0:0] + update \main_sdram_bankmachine0_cmd_valid $0\main_sdram_bankmachine0_cmd_valid[0:0] + update \main_sdram_bankmachine0_cmd_payload_cas $0\main_sdram_bankmachine0_cmd_payload_cas[0:0] + update \main_sdram_bankmachine0_cmd_payload_ras $0\main_sdram_bankmachine0_cmd_payload_ras[0:0] + update \main_sdram_bankmachine0_cmd_payload_we $0\main_sdram_bankmachine0_cmd_payload_we[0:0] + update \main_sdram_bankmachine0_cmd_payload_is_cmd $0\main_sdram_bankmachine0_cmd_payload_is_cmd[0:0] + update \main_sdram_bankmachine0_cmd_payload_is_read $0\main_sdram_bankmachine0_cmd_payload_is_read[0:0] + update \main_sdram_bankmachine0_cmd_payload_is_write $0\main_sdram_bankmachine0_cmd_payload_is_write[0:0] + update \main_sdram_bankmachine0_row_open $0\main_sdram_bankmachine0_row_open[0:0] + update \main_sdram_bankmachine0_row_close $0\main_sdram_bankmachine0_row_close[0:0] + update \main_sdram_bankmachine0_row_col_n_addr_sel $0\main_sdram_bankmachine0_row_col_n_addr_sel[0:0] + update \builder_bankmachine0_next_state $0\builder_bankmachine0_next_state[2:0] + end + attribute \src "build/ls180/gateware/ls180.v:313.5-313.24" + process $proc$build/ls180/gateware/ls180.v:313$2666 + assign { } { } + assign $1\main_int_rst[0:0] 1'1 + sync always + sync init + update \main_int_rst $1\main_int_rst[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:3210.1-3217.4" + process $proc$build/ls180/gateware/ls180.v:3210$141 + assign { } { } + assign $0\main_sdram_bankmachine1_cmd_payload_a[12:0] 13'0000000000000 + attribute \src "build/ls180/gateware/ls180.v:3212.2-3216.5" + switch \main_sdram_bankmachine1_row_col_n_addr_sel + attribute \src "build/ls180/gateware/ls180.v:3212.6-3212.48" + case 1'1 + assign $0\main_sdram_bankmachine1_cmd_payload_a[12:0] \main_sdram_bankmachine1_cmd_buffer_source_payload_addr [21:9] + attribute \src "build/ls180/gateware/ls180.v:3214.6-3214.10" + case + assign $0\main_sdram_bankmachine1_cmd_payload_a[12:0] $or$build/ls180/gateware/ls180.v:3215$143_Y + end + sync always + update \main_sdram_bankmachine1_cmd_payload_a $0\main_sdram_bankmachine1_cmd_payload_a[12:0] + end + attribute \src "build/ls180/gateware/ls180.v:3221.1-3228.4" + process $proc$build/ls180/gateware/ls180.v:3221$150 + assign { } { } + assign $0\main_sdram_bankmachine1_auto_precharge[0:0] 1'0 + attribute \src "build/ls180/gateware/ls180.v:3223.2-3227.5" + switch $and$build/ls180/gateware/ls180.v:3223$151_Y + attribute \src "build/ls180/gateware/ls180.v:3223.6-3223.115" + case 1'1 + attribute \src "build/ls180/gateware/ls180.v:3224.3-3226.6" + switch $ne$build/ls180/gateware/ls180.v:3224$152_Y + attribute \src "build/ls180/gateware/ls180.v:3224.7-3224.143" + case 1'1 + assign $0\main_sdram_bankmachine1_auto_precharge[0:0] $eq$build/ls180/gateware/ls180.v:3225$153_Y + case + end + case + end + sync always + update \main_sdram_bankmachine1_auto_precharge $0\main_sdram_bankmachine1_auto_precharge[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:3243.1-3250.4" + process $proc$build/ls180/gateware/ls180.v:3243$154 + assign { } { } + assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr[2:0] 3'000 + attribute \src "build/ls180/gateware/ls180.v:3245.2-3249.5" + switch \main_sdram_bankmachine1_cmd_buffer_lookahead_replace + attribute \src "build/ls180/gateware/ls180.v:3245.6-3245.58" + case 1'1 + assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr[2:0] $sub$build/ls180/gateware/ls180.v:3246$155_Y + attribute \src "build/ls180/gateware/ls180.v:3247.6-3247.10" + case + assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr[2:0] \main_sdram_bankmachine1_cmd_buffer_lookahead_produce + end + sync always + update \main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr $0\main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr[2:0] + end + attribute \src "build/ls180/gateware/ls180.v:3259.1-3352.4" + process $proc$build/ls180/gateware/ls180.v:3259$163 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\main_sdram_bankmachine1_row_open[0:0] 1'0 + assign $0\main_sdram_bankmachine1_row_close[0:0] 1'0 + assign $0\main_sdram_bankmachine1_cmd_payload_cas[0:0] 1'0 + assign $0\main_sdram_bankmachine1_cmd_payload_ras[0:0] 1'0 + assign { } { } + assign $0\main_sdram_bankmachine1_cmd_payload_we[0:0] 1'0 + assign $0\main_sdram_bankmachine1_row_col_n_addr_sel[0:0] 1'0 + assign $0\main_sdram_bankmachine1_cmd_payload_is_cmd[0:0] 1'0 + assign $0\main_sdram_bankmachine1_cmd_payload_is_read[0:0] 1'0 + assign $0\main_sdram_bankmachine1_cmd_payload_is_write[0:0] 1'0 + assign $0\main_sdram_bankmachine1_req_wdata_ready[0:0] 1'0 + assign $0\main_sdram_bankmachine1_req_rdata_valid[0:0] 1'0 + assign $0\main_sdram_bankmachine1_refresh_gnt[0:0] 1'0 + assign $0\main_sdram_bankmachine1_cmd_valid[0:0] 1'0 + assign $0\builder_bankmachine1_next_state[2:0] \builder_bankmachine1_state + attribute \src "build/ls180/gateware/ls180.v:3275.2-3351.9" + switch \builder_bankmachine1_state + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case 3'001 + assign $0\main_sdram_bankmachine1_row_close[0:0] 1'1 + attribute \src "build/ls180/gateware/ls180.v:3277.4-3285.7" + switch $and$build/ls180/gateware/ls180.v:3277$164_Y + attribute \src "build/ls180/gateware/ls180.v:3277.8-3277.87" + case 1'1 + assign $0\main_sdram_bankmachine1_cmd_valid[0:0] 1'1 + assign $0\main_sdram_bankmachine1_cmd_payload_ras[0:0] 1'1 + assign $0\main_sdram_bankmachine1_cmd_payload_we[0:0] 1'1 + assign $0\main_sdram_bankmachine1_cmd_payload_is_cmd[0:0] 1'1 + attribute \src "build/ls180/gateware/ls180.v:3279.5-3281.8" + switch \main_sdram_bankmachine1_cmd_ready + attribute \src "build/ls180/gateware/ls180.v:3279.9-3279.42" + case 1'1 + assign $0\builder_bankmachine1_next_state[2:0] 3'101 + case + end + case + end + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case 3'010 + assign $0\main_sdram_bankmachine1_row_close[0:0] 1'1 + attribute \src "build/ls180/gateware/ls180.v:3289.4-3291.7" + switch $and$build/ls180/gateware/ls180.v:3289$165_Y + attribute \src "build/ls180/gateware/ls180.v:3289.8-3289.87" + case 1'1 + assign $0\builder_bankmachine1_next_state[2:0] 3'101 + case + end + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case 3'011 + attribute \src "build/ls180/gateware/ls180.v:3295.4-3304.7" + switch \main_sdram_bankmachine1_trccon_ready + attribute \src "build/ls180/gateware/ls180.v:3295.8-3295.44" + case 1'1 + assign $0\main_sdram_bankmachine1_row_col_n_addr_sel[0:0] 1'1 + assign $0\main_sdram_bankmachine1_row_open[0:0] 1'1 + assign $0\main_sdram_bankmachine1_cmd_valid[0:0] 1'1 + assign $0\main_sdram_bankmachine1_cmd_payload_is_cmd[0:0] 1'1 + assign $0\main_sdram_bankmachine1_cmd_payload_ras[0:0] 1'1 + attribute \src "build/ls180/gateware/ls180.v:3300.5-3302.8" + switch \main_sdram_bankmachine1_cmd_ready + attribute \src "build/ls180/gateware/ls180.v:3300.9-3300.42" + case 1'1 + assign $0\builder_bankmachine1_next_state[2:0] 3'110 + case + end + case + end + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case 3'100 + assign $0\main_sdram_bankmachine1_row_close[0:0] 1'1 + assign $0\main_sdram_bankmachine1_cmd_payload_is_cmd[0:0] 1'1 + attribute \src "build/ls180/gateware/ls180.v:3307.4-3309.7" + switch \main_sdram_bankmachine1_twtpcon_ready + attribute \src "build/ls180/gateware/ls180.v:3307.8-3307.45" + case 1'1 + assign $0\main_sdram_bankmachine1_refresh_gnt[0:0] 1'1 + case + end + attribute \src "build/ls180/gateware/ls180.v:3312.4-3314.7" + switch $not$build/ls180/gateware/ls180.v:3312$166_Y + attribute \src "build/ls180/gateware/ls180.v:3312.8-3312.46" + case 1'1 + assign $0\builder_bankmachine1_next_state[2:0] 3'000 + case + end + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case 3'101 + assign $0\builder_bankmachine1_next_state[2:0] 3'011 + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case 3'110 + assign $0\builder_bankmachine1_next_state[2:0] 3'000 + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case + attribute \src "build/ls180/gateware/ls180.v:3323.4-3349.7" + switch \main_sdram_bankmachine1_refresh_req + attribute \src "build/ls180/gateware/ls180.v:3323.8-3323.43" + case 1'1 + assign $0\builder_bankmachine1_next_state[2:0] 3'100 + attribute \src "build/ls180/gateware/ls180.v:3325.8-3325.12" + case + attribute \src "build/ls180/gateware/ls180.v:3326.5-3348.8" + switch \main_sdram_bankmachine1_cmd_buffer_source_valid + attribute \src "build/ls180/gateware/ls180.v:3326.9-3326.56" + case 1'1 + attribute \src "build/ls180/gateware/ls180.v:3327.6-3347.9" + switch \main_sdram_bankmachine1_row_opened + attribute \src "build/ls180/gateware/ls180.v:3327.10-3327.44" + case 1'1 + attribute \src "build/ls180/gateware/ls180.v:3328.7-3344.10" + switch \main_sdram_bankmachine1_row_hit + attribute \src "build/ls180/gateware/ls180.v:3328.11-3328.42" + case 1'1 + assign $0\main_sdram_bankmachine1_cmd_valid[0:0] 1'1 + assign $0\main_sdram_bankmachine1_cmd_payload_cas[0:0] 1'1 + attribute \src "build/ls180/gateware/ls180.v:3330.8-3337.11" + switch \main_sdram_bankmachine1_cmd_buffer_source_payload_we + attribute \src "build/ls180/gateware/ls180.v:3330.12-3330.64" + case 1'1 + assign $0\main_sdram_bankmachine1_req_wdata_ready[0:0] \main_sdram_bankmachine1_cmd_ready + assign $0\main_sdram_bankmachine1_cmd_payload_is_write[0:0] 1'1 + assign $0\main_sdram_bankmachine1_cmd_payload_we[0:0] 1'1 + attribute \src "build/ls180/gateware/ls180.v:3334.12-3334.16" + case + assign $0\main_sdram_bankmachine1_req_rdata_valid[0:0] \main_sdram_bankmachine1_cmd_ready + assign $0\main_sdram_bankmachine1_cmd_payload_is_read[0:0] 1'1 + end + attribute \src "build/ls180/gateware/ls180.v:3339.8-3341.11" + switch $and$build/ls180/gateware/ls180.v:3339$167_Y + attribute \src "build/ls180/gateware/ls180.v:3339.12-3339.88" + case 1'1 + assign $0\builder_bankmachine1_next_state[2:0] 3'010 + case + end + attribute \src "build/ls180/gateware/ls180.v:3342.11-3342.15" + case + assign $0\builder_bankmachine1_next_state[2:0] 3'001 + end + attribute \src "build/ls180/gateware/ls180.v:3345.10-3345.14" + case + assign $0\builder_bankmachine1_next_state[2:0] 3'011 + end + case + end + end + end + sync always + update \main_sdram_bankmachine1_req_wdata_ready $0\main_sdram_bankmachine1_req_wdata_ready[0:0] + update \main_sdram_bankmachine1_req_rdata_valid $0\main_sdram_bankmachine1_req_rdata_valid[0:0] + update \main_sdram_bankmachine1_refresh_gnt $0\main_sdram_bankmachine1_refresh_gnt[0:0] + update \main_sdram_bankmachine1_cmd_valid $0\main_sdram_bankmachine1_cmd_valid[0:0] + update \main_sdram_bankmachine1_cmd_payload_cas $0\main_sdram_bankmachine1_cmd_payload_cas[0:0] + update \main_sdram_bankmachine1_cmd_payload_ras $0\main_sdram_bankmachine1_cmd_payload_ras[0:0] + update \main_sdram_bankmachine1_cmd_payload_we $0\main_sdram_bankmachine1_cmd_payload_we[0:0] + update \main_sdram_bankmachine1_cmd_payload_is_cmd $0\main_sdram_bankmachine1_cmd_payload_is_cmd[0:0] + update \main_sdram_bankmachine1_cmd_payload_is_read $0\main_sdram_bankmachine1_cmd_payload_is_read[0:0] + update \main_sdram_bankmachine1_cmd_payload_is_write $0\main_sdram_bankmachine1_cmd_payload_is_write[0:0] + update \main_sdram_bankmachine1_row_open $0\main_sdram_bankmachine1_row_open[0:0] + update \main_sdram_bankmachine1_row_close $0\main_sdram_bankmachine1_row_close[0:0] + update \main_sdram_bankmachine1_row_col_n_addr_sel $0\main_sdram_bankmachine1_row_col_n_addr_sel[0:0] + update \builder_bankmachine1_next_state $0\builder_bankmachine1_next_state[2:0] + end + attribute \src "build/ls180/gateware/ls180.v:328.12-328.38" + process $proc$build/ls180/gateware/ls180.v:328$2667 + assign { } { } + assign $1\main_dfi_p0_rddata[15:0] 16'0000000000000000 + sync always + sync init + update \main_dfi_p0_rddata $1\main_dfi_p0_rddata[15:0] + end + attribute \src "build/ls180/gateware/ls180.v:329.5-329.36" + process $proc$build/ls180/gateware/ls180.v:329$2668 + assign { } { } + assign $1\main_dfi_p0_rddata_valid[0:0] 1'0 + sync always + sync init + update \main_dfi_p0_rddata_valid $1\main_dfi_p0_rddata_valid[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:33.5-33.56" + process $proc$build/ls180/gateware/ls180.v:33$2563 + assign { } { } + assign $1\main_libresocsim_soccontroller_reset_storage[0:0] 1'0 + sync always + sync init + update \main_libresocsim_soccontroller_reset_storage $1\main_libresocsim_soccontroller_reset_storage[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:330.11-330.32" + process $proc$build/ls180/gateware/ls180.v:330$2669 + assign { } { } + assign $1\main_rddata_en[2:0] 3'000 + sync always + sync init + update \main_rddata_en $1\main_rddata_en[2:0] + end + attribute \src "build/ls180/gateware/ls180.v:333.5-333.36" + process $proc$build/ls180/gateware/ls180.v:333$2670 + assign { } { } + assign $1\main_sdram_inti_p0_cas_n[0:0] 1'1 + sync always + sync init + update \main_sdram_inti_p0_cas_n $1\main_sdram_inti_p0_cas_n[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:334.5-334.35" + process $proc$build/ls180/gateware/ls180.v:334$2671 + assign { } { } + assign $1\main_sdram_inti_p0_cs_n[0:0] 1'1 + sync always + sync init + update \main_sdram_inti_p0_cs_n $1\main_sdram_inti_p0_cs_n[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:335.5-335.36" + process $proc$build/ls180/gateware/ls180.v:335$2672 + assign { } { } + assign $1\main_sdram_inti_p0_ras_n[0:0] 1'1 + sync always + sync init + update \main_sdram_inti_p0_ras_n $1\main_sdram_inti_p0_ras_n[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:336.5-336.35" + process $proc$build/ls180/gateware/ls180.v:336$2673 + assign { } { } + assign $1\main_sdram_inti_p0_we_n[0:0] 1'1 + sync always + sync init + update \main_sdram_inti_p0_we_n $1\main_sdram_inti_p0_we_n[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:3367.1-3374.4" + process $proc$build/ls180/gateware/ls180.v:3367$171 + assign { } { } + assign $0\main_sdram_bankmachine2_cmd_payload_a[12:0] 13'0000000000000 + attribute \src "build/ls180/gateware/ls180.v:3369.2-3373.5" + switch \main_sdram_bankmachine2_row_col_n_addr_sel + attribute \src "build/ls180/gateware/ls180.v:3369.6-3369.48" + case 1'1 + assign $0\main_sdram_bankmachine2_cmd_payload_a[12:0] \main_sdram_bankmachine2_cmd_buffer_source_payload_addr [21:9] + attribute \src "build/ls180/gateware/ls180.v:3371.6-3371.10" + case + assign $0\main_sdram_bankmachine2_cmd_payload_a[12:0] $or$build/ls180/gateware/ls180.v:3372$173_Y + end + sync always + update \main_sdram_bankmachine2_cmd_payload_a $0\main_sdram_bankmachine2_cmd_payload_a[12:0] + end + attribute \src "build/ls180/gateware/ls180.v:3378.1-3385.4" + process $proc$build/ls180/gateware/ls180.v:3378$180 + assign { } { } + assign $0\main_sdram_bankmachine2_auto_precharge[0:0] 1'0 + attribute \src "build/ls180/gateware/ls180.v:3380.2-3384.5" + switch $and$build/ls180/gateware/ls180.v:3380$181_Y + attribute \src "build/ls180/gateware/ls180.v:3380.6-3380.115" + case 1'1 + attribute \src "build/ls180/gateware/ls180.v:3381.3-3383.6" + switch $ne$build/ls180/gateware/ls180.v:3381$182_Y + attribute \src "build/ls180/gateware/ls180.v:3381.7-3381.143" + case 1'1 + assign $0\main_sdram_bankmachine2_auto_precharge[0:0] $eq$build/ls180/gateware/ls180.v:3382$183_Y + case + end + case + end + sync always + update \main_sdram_bankmachine2_auto_precharge $0\main_sdram_bankmachine2_auto_precharge[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:34.5-34.51" + process $proc$build/ls180/gateware/ls180.v:34$2564 + assign { } { } + assign $1\main_libresocsim_soccontroller_reset_re[0:0] 1'0 + sync always + sync init + update \main_libresocsim_soccontroller_reset_re $1\main_libresocsim_soccontroller_reset_re[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:340.5-340.36" + process $proc$build/ls180/gateware/ls180.v:340$2674 + assign { } { } + assign $0\main_sdram_inti_p0_act_n[0:0] 1'1 + sync always + update \main_sdram_inti_p0_act_n $0\main_sdram_inti_p0_act_n[0:0] + sync init + end + attribute \src "build/ls180/gateware/ls180.v:3400.1-3407.4" + process $proc$build/ls180/gateware/ls180.v:3400$184 + assign { } { } + assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr[2:0] 3'000 + attribute \src "build/ls180/gateware/ls180.v:3402.2-3406.5" + switch \main_sdram_bankmachine2_cmd_buffer_lookahead_replace + attribute \src "build/ls180/gateware/ls180.v:3402.6-3402.58" + case 1'1 + assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr[2:0] $sub$build/ls180/gateware/ls180.v:3403$185_Y + attribute \src "build/ls180/gateware/ls180.v:3404.6-3404.10" + case + assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr[2:0] \main_sdram_bankmachine2_cmd_buffer_lookahead_produce + end + sync always + update \main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr $0\main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr[2:0] + end + attribute \src "build/ls180/gateware/ls180.v:3416.1-3509.4" + process $proc$build/ls180/gateware/ls180.v:3416$193 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\main_sdram_bankmachine2_row_col_n_addr_sel[0:0] 1'0 + assign $0\main_sdram_bankmachine2_req_rdata_valid[0:0] 1'0 + assign $0\main_sdram_bankmachine2_refresh_gnt[0:0] 1'0 + assign $0\main_sdram_bankmachine2_cmd_valid[0:0] 1'0 + assign { } { } + assign $0\main_sdram_bankmachine2_row_open[0:0] 1'0 + assign $0\main_sdram_bankmachine2_row_close[0:0] 1'0 + assign $0\main_sdram_bankmachine2_cmd_payload_cas[0:0] 1'0 + assign $0\main_sdram_bankmachine2_cmd_payload_ras[0:0] 1'0 + assign $0\main_sdram_bankmachine2_cmd_payload_we[0:0] 1'0 + assign $0\main_sdram_bankmachine2_cmd_payload_is_cmd[0:0] 1'0 + assign $0\main_sdram_bankmachine2_cmd_payload_is_read[0:0] 1'0 + assign $0\main_sdram_bankmachine2_cmd_payload_is_write[0:0] 1'0 + assign $0\main_sdram_bankmachine2_req_wdata_ready[0:0] 1'0 + assign $0\builder_bankmachine2_next_state[2:0] \builder_bankmachine2_state + attribute \src "build/ls180/gateware/ls180.v:3432.2-3508.9" + switch \builder_bankmachine2_state + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case 3'001 + assign $0\main_sdram_bankmachine2_row_close[0:0] 1'1 + attribute \src "build/ls180/gateware/ls180.v:3434.4-3442.7" + switch $and$build/ls180/gateware/ls180.v:3434$194_Y + attribute \src "build/ls180/gateware/ls180.v:3434.8-3434.87" + case 1'1 + assign $0\main_sdram_bankmachine2_cmd_valid[0:0] 1'1 + assign $0\main_sdram_bankmachine2_cmd_payload_ras[0:0] 1'1 + assign $0\main_sdram_bankmachine2_cmd_payload_we[0:0] 1'1 + assign $0\main_sdram_bankmachine2_cmd_payload_is_cmd[0:0] 1'1 + attribute \src "build/ls180/gateware/ls180.v:3436.5-3438.8" + switch \main_sdram_bankmachine2_cmd_ready + attribute \src "build/ls180/gateware/ls180.v:3436.9-3436.42" + case 1'1 + assign $0\builder_bankmachine2_next_state[2:0] 3'101 + case + end + case + end + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case 3'010 + assign $0\main_sdram_bankmachine2_row_close[0:0] 1'1 + attribute \src "build/ls180/gateware/ls180.v:3446.4-3448.7" + switch $and$build/ls180/gateware/ls180.v:3446$195_Y + attribute \src "build/ls180/gateware/ls180.v:3446.8-3446.87" + case 1'1 + assign $0\builder_bankmachine2_next_state[2:0] 3'101 + case + end + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case 3'011 + attribute \src "build/ls180/gateware/ls180.v:3452.4-3461.7" + switch \main_sdram_bankmachine2_trccon_ready + attribute \src "build/ls180/gateware/ls180.v:3452.8-3452.44" + case 1'1 + assign $0\main_sdram_bankmachine2_row_col_n_addr_sel[0:0] 1'1 + assign $0\main_sdram_bankmachine2_row_open[0:0] 1'1 + assign $0\main_sdram_bankmachine2_cmd_valid[0:0] 1'1 + assign $0\main_sdram_bankmachine2_cmd_payload_is_cmd[0:0] 1'1 + assign $0\main_sdram_bankmachine2_cmd_payload_ras[0:0] 1'1 + attribute \src "build/ls180/gateware/ls180.v:3457.5-3459.8" + switch \main_sdram_bankmachine2_cmd_ready + attribute \src "build/ls180/gateware/ls180.v:3457.9-3457.42" + case 1'1 + assign $0\builder_bankmachine2_next_state[2:0] 3'110 + case + end + case + end + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case 3'100 + assign $0\main_sdram_bankmachine2_row_close[0:0] 1'1 + assign $0\main_sdram_bankmachine2_cmd_payload_is_cmd[0:0] 1'1 + attribute \src "build/ls180/gateware/ls180.v:3464.4-3466.7" + switch \main_sdram_bankmachine2_twtpcon_ready + attribute \src "build/ls180/gateware/ls180.v:3464.8-3464.45" + case 1'1 + assign $0\main_sdram_bankmachine2_refresh_gnt[0:0] 1'1 + case + end + attribute \src "build/ls180/gateware/ls180.v:3469.4-3471.7" + switch $not$build/ls180/gateware/ls180.v:3469$196_Y + attribute \src "build/ls180/gateware/ls180.v:3469.8-3469.46" + case 1'1 + assign $0\builder_bankmachine2_next_state[2:0] 3'000 + case + end + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case 3'101 + assign $0\builder_bankmachine2_next_state[2:0] 3'011 + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case 3'110 + assign $0\builder_bankmachine2_next_state[2:0] 3'000 + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case + attribute \src "build/ls180/gateware/ls180.v:3480.4-3506.7" + switch \main_sdram_bankmachine2_refresh_req + attribute \src "build/ls180/gateware/ls180.v:3480.8-3480.43" + case 1'1 + assign $0\builder_bankmachine2_next_state[2:0] 3'100 + attribute \src "build/ls180/gateware/ls180.v:3482.8-3482.12" + case + attribute \src "build/ls180/gateware/ls180.v:3483.5-3505.8" + switch \main_sdram_bankmachine2_cmd_buffer_source_valid + attribute \src "build/ls180/gateware/ls180.v:3483.9-3483.56" + case 1'1 + attribute \src "build/ls180/gateware/ls180.v:3484.6-3504.9" + switch \main_sdram_bankmachine2_row_opened + attribute \src "build/ls180/gateware/ls180.v:3484.10-3484.44" + case 1'1 + attribute \src "build/ls180/gateware/ls180.v:3485.7-3501.10" + switch \main_sdram_bankmachine2_row_hit + attribute \src "build/ls180/gateware/ls180.v:3485.11-3485.42" + case 1'1 + assign $0\main_sdram_bankmachine2_cmd_valid[0:0] 1'1 + assign $0\main_sdram_bankmachine2_cmd_payload_cas[0:0] 1'1 + attribute \src "build/ls180/gateware/ls180.v:3487.8-3494.11" + switch \main_sdram_bankmachine2_cmd_buffer_source_payload_we + attribute \src "build/ls180/gateware/ls180.v:3487.12-3487.64" + case 1'1 + assign $0\main_sdram_bankmachine2_req_wdata_ready[0:0] \main_sdram_bankmachine2_cmd_ready + assign $0\main_sdram_bankmachine2_cmd_payload_is_write[0:0] 1'1 + assign $0\main_sdram_bankmachine2_cmd_payload_we[0:0] 1'1 + attribute \src "build/ls180/gateware/ls180.v:3491.12-3491.16" + case + assign $0\main_sdram_bankmachine2_req_rdata_valid[0:0] \main_sdram_bankmachine2_cmd_ready + assign $0\main_sdram_bankmachine2_cmd_payload_is_read[0:0] 1'1 + end + attribute \src "build/ls180/gateware/ls180.v:3496.8-3498.11" + switch $and$build/ls180/gateware/ls180.v:3496$197_Y + attribute \src "build/ls180/gateware/ls180.v:3496.12-3496.88" + case 1'1 + assign $0\builder_bankmachine2_next_state[2:0] 3'010 + case + end + attribute \src "build/ls180/gateware/ls180.v:3499.11-3499.15" + case + assign $0\builder_bankmachine2_next_state[2:0] 3'001 + end + attribute \src "build/ls180/gateware/ls180.v:3502.10-3502.14" + case + assign $0\builder_bankmachine2_next_state[2:0] 3'011 + end + case + end + end + end + sync always + update \main_sdram_bankmachine2_req_wdata_ready $0\main_sdram_bankmachine2_req_wdata_ready[0:0] + update \main_sdram_bankmachine2_req_rdata_valid $0\main_sdram_bankmachine2_req_rdata_valid[0:0] + update \main_sdram_bankmachine2_refresh_gnt $0\main_sdram_bankmachine2_refresh_gnt[0:0] + update \main_sdram_bankmachine2_cmd_valid $0\main_sdram_bankmachine2_cmd_valid[0:0] + update \main_sdram_bankmachine2_cmd_payload_cas $0\main_sdram_bankmachine2_cmd_payload_cas[0:0] + update \main_sdram_bankmachine2_cmd_payload_ras $0\main_sdram_bankmachine2_cmd_payload_ras[0:0] + update \main_sdram_bankmachine2_cmd_payload_we $0\main_sdram_bankmachine2_cmd_payload_we[0:0] + update \main_sdram_bankmachine2_cmd_payload_is_cmd $0\main_sdram_bankmachine2_cmd_payload_is_cmd[0:0] + update \main_sdram_bankmachine2_cmd_payload_is_read $0\main_sdram_bankmachine2_cmd_payload_is_read[0:0] + update \main_sdram_bankmachine2_cmd_payload_is_write $0\main_sdram_bankmachine2_cmd_payload_is_write[0:0] + update \main_sdram_bankmachine2_row_open $0\main_sdram_bankmachine2_row_open[0:0] + update \main_sdram_bankmachine2_row_close $0\main_sdram_bankmachine2_row_close[0:0] + update \main_sdram_bankmachine2_row_col_n_addr_sel $0\main_sdram_bankmachine2_row_col_n_addr_sel[0:0] + update \builder_bankmachine2_next_state $0\builder_bankmachine2_next_state[2:0] + end + attribute \src "build/ls180/gateware/ls180.v:345.12-345.45" + process $proc$build/ls180/gateware/ls180.v:345$2675 + assign { } { } + assign $1\main_sdram_inti_p0_rddata[15:0] 16'0000000000000000 + sync always + sync init + update \main_sdram_inti_p0_rddata $1\main_sdram_inti_p0_rddata[15:0] + end + attribute \src "build/ls180/gateware/ls180.v:346.5-346.43" + process $proc$build/ls180/gateware/ls180.v:346$2676 + assign { } { } + assign $1\main_sdram_inti_p0_rddata_valid[0:0] 1'0 + sync always + sync init + update \main_sdram_inti_p0_rddata_valid $1\main_sdram_inti_p0_rddata_valid[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:35.12-35.74" + process $proc$build/ls180/gateware/ls180.v:35$2565 + assign { } { } + assign $1\main_libresocsim_soccontroller_scratch_storage[31:0] 305419896 + sync always + sync init + update \main_libresocsim_soccontroller_scratch_storage $1\main_libresocsim_soccontroller_scratch_storage[31:0] + end + attribute \src "build/ls180/gateware/ls180.v:3524.1-3531.4" + process $proc$build/ls180/gateware/ls180.v:3524$201 + assign { } { } + assign $0\main_sdram_bankmachine3_cmd_payload_a[12:0] 13'0000000000000 + attribute \src "build/ls180/gateware/ls180.v:3526.2-3530.5" + switch \main_sdram_bankmachine3_row_col_n_addr_sel + attribute \src "build/ls180/gateware/ls180.v:3526.6-3526.48" + case 1'1 + assign $0\main_sdram_bankmachine3_cmd_payload_a[12:0] \main_sdram_bankmachine3_cmd_buffer_source_payload_addr [21:9] + attribute \src "build/ls180/gateware/ls180.v:3528.6-3528.10" + case + assign $0\main_sdram_bankmachine3_cmd_payload_a[12:0] $or$build/ls180/gateware/ls180.v:3529$203_Y + end + sync always + update \main_sdram_bankmachine3_cmd_payload_a $0\main_sdram_bankmachine3_cmd_payload_a[12:0] + end + attribute \src "build/ls180/gateware/ls180.v:3535.1-3542.4" + process $proc$build/ls180/gateware/ls180.v:3535$210 + assign { } { } + assign $0\main_sdram_bankmachine3_auto_precharge[0:0] 1'0 + attribute \src "build/ls180/gateware/ls180.v:3537.2-3541.5" + switch $and$build/ls180/gateware/ls180.v:3537$211_Y + attribute \src "build/ls180/gateware/ls180.v:3537.6-3537.115" + case 1'1 + attribute \src "build/ls180/gateware/ls180.v:3538.3-3540.6" + switch $ne$build/ls180/gateware/ls180.v:3538$212_Y + attribute \src "build/ls180/gateware/ls180.v:3538.7-3538.143" + case 1'1 + assign $0\main_sdram_bankmachine3_auto_precharge[0:0] $eq$build/ls180/gateware/ls180.v:3539$213_Y + case + end + case + end + sync always + update \main_sdram_bankmachine3_auto_precharge $0\main_sdram_bankmachine3_auto_precharge[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:3557.1-3564.4" + process $proc$build/ls180/gateware/ls180.v:3557$214 + assign { } { } + assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr[2:0] 3'000 + attribute \src "build/ls180/gateware/ls180.v:3559.2-3563.5" + switch \main_sdram_bankmachine3_cmd_buffer_lookahead_replace + attribute \src "build/ls180/gateware/ls180.v:3559.6-3559.58" + case 1'1 + assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr[2:0] $sub$build/ls180/gateware/ls180.v:3560$215_Y + attribute \src "build/ls180/gateware/ls180.v:3561.6-3561.10" + case + assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr[2:0] \main_sdram_bankmachine3_cmd_buffer_lookahead_produce + end + sync always + update \main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr $0\main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr[2:0] + end + attribute \src "build/ls180/gateware/ls180.v:3573.1-3666.4" + process $proc$build/ls180/gateware/ls180.v:3573$223 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\main_sdram_bankmachine3_cmd_payload_is_cmd[0:0] 1'0 + assign $0\main_sdram_bankmachine3_cmd_payload_is_read[0:0] 1'0 + assign $0\main_sdram_bankmachine3_cmd_payload_is_write[0:0] 1'0 + assign { } { } + assign $0\main_sdram_bankmachine3_req_wdata_ready[0:0] 1'0 + assign $0\main_sdram_bankmachine3_req_rdata_valid[0:0] 1'0 + assign $0\main_sdram_bankmachine3_refresh_gnt[0:0] 1'0 + assign $0\main_sdram_bankmachine3_cmd_valid[0:0] 1'0 + assign $0\main_sdram_bankmachine3_row_col_n_addr_sel[0:0] 1'0 + assign $0\main_sdram_bankmachine3_row_open[0:0] 1'0 + assign $0\main_sdram_bankmachine3_row_close[0:0] 1'0 + assign $0\main_sdram_bankmachine3_cmd_payload_cas[0:0] 1'0 + assign $0\main_sdram_bankmachine3_cmd_payload_ras[0:0] 1'0 + assign $0\main_sdram_bankmachine3_cmd_payload_we[0:0] 1'0 + assign $0\builder_bankmachine3_next_state[2:0] \builder_bankmachine3_state + attribute \src "build/ls180/gateware/ls180.v:3589.2-3665.9" + switch \builder_bankmachine3_state + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case 3'001 + assign $0\main_sdram_bankmachine3_row_close[0:0] 1'1 + attribute \src "build/ls180/gateware/ls180.v:3591.4-3599.7" + switch $and$build/ls180/gateware/ls180.v:3591$224_Y + attribute \src "build/ls180/gateware/ls180.v:3591.8-3591.87" + case 1'1 + assign $0\main_sdram_bankmachine3_cmd_valid[0:0] 1'1 + assign $0\main_sdram_bankmachine3_cmd_payload_ras[0:0] 1'1 + assign $0\main_sdram_bankmachine3_cmd_payload_we[0:0] 1'1 + assign $0\main_sdram_bankmachine3_cmd_payload_is_cmd[0:0] 1'1 + attribute \src "build/ls180/gateware/ls180.v:3593.5-3595.8" + switch \main_sdram_bankmachine3_cmd_ready + attribute \src "build/ls180/gateware/ls180.v:3593.9-3593.42" + case 1'1 + assign $0\builder_bankmachine3_next_state[2:0] 3'101 + case + end + case + end + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case 3'010 + assign $0\main_sdram_bankmachine3_row_close[0:0] 1'1 + attribute \src "build/ls180/gateware/ls180.v:3603.4-3605.7" + switch $and$build/ls180/gateware/ls180.v:3603$225_Y + attribute \src "build/ls180/gateware/ls180.v:3603.8-3603.87" + case 1'1 + assign $0\builder_bankmachine3_next_state[2:0] 3'101 + case + end + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case 3'011 + attribute \src "build/ls180/gateware/ls180.v:3609.4-3618.7" + switch \main_sdram_bankmachine3_trccon_ready + attribute \src "build/ls180/gateware/ls180.v:3609.8-3609.44" + case 1'1 + assign $0\main_sdram_bankmachine3_row_col_n_addr_sel[0:0] 1'1 + assign $0\main_sdram_bankmachine3_row_open[0:0] 1'1 + assign $0\main_sdram_bankmachine3_cmd_valid[0:0] 1'1 + assign $0\main_sdram_bankmachine3_cmd_payload_is_cmd[0:0] 1'1 + assign $0\main_sdram_bankmachine3_cmd_payload_ras[0:0] 1'1 + attribute \src "build/ls180/gateware/ls180.v:3614.5-3616.8" + switch \main_sdram_bankmachine3_cmd_ready + attribute \src "build/ls180/gateware/ls180.v:3614.9-3614.42" + case 1'1 + assign $0\builder_bankmachine3_next_state[2:0] 3'110 + case + end + case + end + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case 3'100 + assign $0\main_sdram_bankmachine3_row_close[0:0] 1'1 + assign $0\main_sdram_bankmachine3_cmd_payload_is_cmd[0:0] 1'1 + attribute \src "build/ls180/gateware/ls180.v:3621.4-3623.7" + switch \main_sdram_bankmachine3_twtpcon_ready + attribute \src "build/ls180/gateware/ls180.v:3621.8-3621.45" + case 1'1 + assign $0\main_sdram_bankmachine3_refresh_gnt[0:0] 1'1 + case + end + attribute \src "build/ls180/gateware/ls180.v:3626.4-3628.7" + switch $not$build/ls180/gateware/ls180.v:3626$226_Y + attribute \src "build/ls180/gateware/ls180.v:3626.8-3626.46" + case 1'1 + assign $0\builder_bankmachine3_next_state[2:0] 3'000 + case + end + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case 3'101 + assign $0\builder_bankmachine3_next_state[2:0] 3'011 + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case 3'110 + assign $0\builder_bankmachine3_next_state[2:0] 3'000 + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case + attribute \src "build/ls180/gateware/ls180.v:3637.4-3663.7" + switch \main_sdram_bankmachine3_refresh_req + attribute \src "build/ls180/gateware/ls180.v:3637.8-3637.43" + case 1'1 + assign $0\builder_bankmachine3_next_state[2:0] 3'100 + attribute \src "build/ls180/gateware/ls180.v:3639.8-3639.12" + case + attribute \src "build/ls180/gateware/ls180.v:3640.5-3662.8" + switch \main_sdram_bankmachine3_cmd_buffer_source_valid + attribute \src "build/ls180/gateware/ls180.v:3640.9-3640.56" + case 1'1 + attribute \src "build/ls180/gateware/ls180.v:3641.6-3661.9" + switch \main_sdram_bankmachine3_row_opened + attribute \src "build/ls180/gateware/ls180.v:3641.10-3641.44" + case 1'1 + attribute \src "build/ls180/gateware/ls180.v:3642.7-3658.10" + switch \main_sdram_bankmachine3_row_hit + attribute \src "build/ls180/gateware/ls180.v:3642.11-3642.42" + case 1'1 + assign $0\main_sdram_bankmachine3_cmd_valid[0:0] 1'1 + assign $0\main_sdram_bankmachine3_cmd_payload_cas[0:0] 1'1 + attribute \src "build/ls180/gateware/ls180.v:3644.8-3651.11" + switch \main_sdram_bankmachine3_cmd_buffer_source_payload_we + attribute \src "build/ls180/gateware/ls180.v:3644.12-3644.64" + case 1'1 + assign $0\main_sdram_bankmachine3_req_wdata_ready[0:0] \main_sdram_bankmachine3_cmd_ready + assign $0\main_sdram_bankmachine3_cmd_payload_is_write[0:0] 1'1 + assign $0\main_sdram_bankmachine3_cmd_payload_we[0:0] 1'1 + attribute \src "build/ls180/gateware/ls180.v:3648.12-3648.16" + case + assign $0\main_sdram_bankmachine3_req_rdata_valid[0:0] \main_sdram_bankmachine3_cmd_ready + assign $0\main_sdram_bankmachine3_cmd_payload_is_read[0:0] 1'1 + end + attribute \src "build/ls180/gateware/ls180.v:3653.8-3655.11" + switch $and$build/ls180/gateware/ls180.v:3653$227_Y + attribute \src "build/ls180/gateware/ls180.v:3653.12-3653.88" + case 1'1 + assign $0\builder_bankmachine3_next_state[2:0] 3'010 + case + end + attribute \src "build/ls180/gateware/ls180.v:3656.11-3656.15" + case + assign $0\builder_bankmachine3_next_state[2:0] 3'001 + end + attribute \src "build/ls180/gateware/ls180.v:3659.10-3659.14" + case + assign $0\builder_bankmachine3_next_state[2:0] 3'011 + end + case + end + end + end + sync always + update \main_sdram_bankmachine3_req_wdata_ready $0\main_sdram_bankmachine3_req_wdata_ready[0:0] + update \main_sdram_bankmachine3_req_rdata_valid $0\main_sdram_bankmachine3_req_rdata_valid[0:0] + update \main_sdram_bankmachine3_refresh_gnt $0\main_sdram_bankmachine3_refresh_gnt[0:0] + update \main_sdram_bankmachine3_cmd_valid $0\main_sdram_bankmachine3_cmd_valid[0:0] + update \main_sdram_bankmachine3_cmd_payload_cas $0\main_sdram_bankmachine3_cmd_payload_cas[0:0] + update \main_sdram_bankmachine3_cmd_payload_ras $0\main_sdram_bankmachine3_cmd_payload_ras[0:0] + update \main_sdram_bankmachine3_cmd_payload_we $0\main_sdram_bankmachine3_cmd_payload_we[0:0] + update \main_sdram_bankmachine3_cmd_payload_is_cmd $0\main_sdram_bankmachine3_cmd_payload_is_cmd[0:0] + update \main_sdram_bankmachine3_cmd_payload_is_read $0\main_sdram_bankmachine3_cmd_payload_is_read[0:0] + update \main_sdram_bankmachine3_cmd_payload_is_write $0\main_sdram_bankmachine3_cmd_payload_is_write[0:0] + update \main_sdram_bankmachine3_row_open $0\main_sdram_bankmachine3_row_open[0:0] + update \main_sdram_bankmachine3_row_close $0\main_sdram_bankmachine3_row_close[0:0] + update \main_sdram_bankmachine3_row_col_n_addr_sel $0\main_sdram_bankmachine3_row_col_n_addr_sel[0:0] + update \builder_bankmachine3_next_state $0\builder_bankmachine3_next_state[2:0] + end + attribute \src "build/ls180/gateware/ls180.v:36.5-36.53" + process $proc$build/ls180/gateware/ls180.v:36$2566 + assign { } { } + assign $1\main_libresocsim_soccontroller_scratch_re[0:0] 1'0 + sync always + sync init + update \main_libresocsim_soccontroller_scratch_re $1\main_libresocsim_soccontroller_scratch_re[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:361.12-361.46" + process $proc$build/ls180/gateware/ls180.v:361$2677 + assign { } { } + assign $1\main_sdram_slave_p0_rddata[15:0] 16'0000000000000000 + sync always + sync init + update \main_sdram_slave_p0_rddata $1\main_sdram_slave_p0_rddata[15:0] + end + attribute \src "build/ls180/gateware/ls180.v:362.5-362.44" + process $proc$build/ls180/gateware/ls180.v:362$2678 + assign { } { } + assign $1\main_sdram_slave_p0_rddata_valid[0:0] 1'0 + sync always + sync init + update \main_sdram_slave_p0_rddata_valid $1\main_sdram_slave_p0_rddata_valid[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:363.12-363.48" + process $proc$build/ls180/gateware/ls180.v:363$2679 + assign { } { } + assign $1\main_sdram_master_p0_address[12:0] 13'0000000000000 + sync always + sync init + update \main_sdram_master_p0_address $1\main_sdram_master_p0_address[12:0] + end + attribute \src "build/ls180/gateware/ls180.v:364.11-364.43" + process $proc$build/ls180/gateware/ls180.v:364$2680 + assign { } { } + assign $1\main_sdram_master_p0_bank[1:0] 2'00 + sync always + sync init + update \main_sdram_master_p0_bank $1\main_sdram_master_p0_bank[1:0] + end + attribute \src "build/ls180/gateware/ls180.v:365.5-365.38" + process $proc$build/ls180/gateware/ls180.v:365$2681 + assign { } { } + assign $1\main_sdram_master_p0_cas_n[0:0] 1'1 + sync always + sync init + update \main_sdram_master_p0_cas_n $1\main_sdram_master_p0_cas_n[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:366.5-366.37" + process $proc$build/ls180/gateware/ls180.v:366$2682 + assign { } { } + assign $1\main_sdram_master_p0_cs_n[0:0] 1'1 + sync always + sync init + update \main_sdram_master_p0_cs_n $1\main_sdram_master_p0_cs_n[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:367.5-367.38" + process $proc$build/ls180/gateware/ls180.v:367$2683 + assign { } { } + assign $1\main_sdram_master_p0_ras_n[0:0] 1'1 + sync always + sync init + update \main_sdram_master_p0_ras_n $1\main_sdram_master_p0_ras_n[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:368.5-368.37" + process $proc$build/ls180/gateware/ls180.v:368$2684 + assign { } { } + assign $1\main_sdram_master_p0_we_n[0:0] 1'1 + sync always + sync init + update \main_sdram_master_p0_we_n $1\main_sdram_master_p0_we_n[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:3686.1-3692.4" + process $proc$build/ls180/gateware/ls180.v:3686$266 + assign { } { } + assign { } { } + assign $0\main_sdram_choose_cmd_valids[3:0] [0] $and$build/ls180/gateware/ls180.v:3688$279_Y + assign $0\main_sdram_choose_cmd_valids[3:0] [1] $and$build/ls180/gateware/ls180.v:3689$292_Y + assign $0\main_sdram_choose_cmd_valids[3:0] [2] $and$build/ls180/gateware/ls180.v:3690$305_Y + assign $0\main_sdram_choose_cmd_valids[3:0] [3] $and$build/ls180/gateware/ls180.v:3691$318_Y + sync always + update \main_sdram_choose_cmd_valids $0\main_sdram_choose_cmd_valids[3:0] + end + attribute \src "build/ls180/gateware/ls180.v:369.5-369.36" + process $proc$build/ls180/gateware/ls180.v:369$2685 + assign { } { } + assign $1\main_sdram_master_p0_cke[0:0] 1'0 + sync always + sync init + update \main_sdram_master_p0_cke $1\main_sdram_master_p0_cke[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:370.5-370.36" + process $proc$build/ls180/gateware/ls180.v:370$2686 + assign { } { } + assign $1\main_sdram_master_p0_odt[0:0] 1'0 + sync always + sync init + update \main_sdram_master_p0_odt $1\main_sdram_master_p0_odt[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:3700.1-3705.4" + process $proc$build/ls180/gateware/ls180.v:3700$319 + assign { } { } + assign $0\main_sdram_choose_cmd_cmd_payload_cas[0:0] 1'0 + attribute \src "build/ls180/gateware/ls180.v:3702.2-3704.5" + switch \main_sdram_choose_cmd_cmd_valid + attribute \src "build/ls180/gateware/ls180.v:3702.6-3702.37" + case 1'1 + assign $0\main_sdram_choose_cmd_cmd_payload_cas[0:0] \builder_comb_t_array_muxed0 + case + end + sync always + update \main_sdram_choose_cmd_cmd_payload_cas $0\main_sdram_choose_cmd_cmd_payload_cas[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:3706.1-3711.4" + process $proc$build/ls180/gateware/ls180.v:3706$320 + assign { } { } + assign $0\main_sdram_choose_cmd_cmd_payload_ras[0:0] 1'0 + attribute \src "build/ls180/gateware/ls180.v:3708.2-3710.5" + switch \main_sdram_choose_cmd_cmd_valid + attribute \src "build/ls180/gateware/ls180.v:3708.6-3708.37" + case 1'1 + assign $0\main_sdram_choose_cmd_cmd_payload_ras[0:0] \builder_comb_t_array_muxed1 + case + end + sync always + update \main_sdram_choose_cmd_cmd_payload_ras $0\main_sdram_choose_cmd_cmd_payload_ras[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:371.5-371.40" + process $proc$build/ls180/gateware/ls180.v:371$2687 + assign { } { } + assign $1\main_sdram_master_p0_reset_n[0:0] 1'0 + sync always + sync init + update \main_sdram_master_p0_reset_n $1\main_sdram_master_p0_reset_n[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:3712.1-3717.4" + process $proc$build/ls180/gateware/ls180.v:3712$321 + assign { } { } + assign $0\main_sdram_choose_cmd_cmd_payload_we[0:0] 1'0 + attribute \src "build/ls180/gateware/ls180.v:3714.2-3716.5" + switch \main_sdram_choose_cmd_cmd_valid + attribute \src "build/ls180/gateware/ls180.v:3714.6-3714.37" + case 1'1 + assign $0\main_sdram_choose_cmd_cmd_payload_we[0:0] \builder_comb_t_array_muxed2 + case + end + sync always + update \main_sdram_choose_cmd_cmd_payload_we $0\main_sdram_choose_cmd_cmd_payload_we[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:3719.1-3725.4" + process $proc$build/ls180/gateware/ls180.v:3719$324 + assign { } { } + assign { } { } + assign $0\main_sdram_choose_req_valids[3:0] [0] $and$build/ls180/gateware/ls180.v:3721$337_Y + assign $0\main_sdram_choose_req_valids[3:0] [1] $and$build/ls180/gateware/ls180.v:3722$350_Y + assign $0\main_sdram_choose_req_valids[3:0] [2] $and$build/ls180/gateware/ls180.v:3723$363_Y + assign $0\main_sdram_choose_req_valids[3:0] [3] $and$build/ls180/gateware/ls180.v:3724$376_Y + sync always + update \main_sdram_choose_req_valids $0\main_sdram_choose_req_valids[3:0] + end + attribute \src "build/ls180/gateware/ls180.v:372.5-372.38" + process $proc$build/ls180/gateware/ls180.v:372$2688 + assign { } { } + assign $1\main_sdram_master_p0_act_n[0:0] 1'1 + sync always + sync init + update \main_sdram_master_p0_act_n $1\main_sdram_master_p0_act_n[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:373.12-373.47" + process $proc$build/ls180/gateware/ls180.v:373$2689 + assign { } { } + assign $1\main_sdram_master_p0_wrdata[15:0] 16'0000000000000000 + sync always + sync init + update \main_sdram_master_p0_wrdata $1\main_sdram_master_p0_wrdata[15:0] + end + attribute \src "build/ls180/gateware/ls180.v:3733.1-3738.4" + process $proc$build/ls180/gateware/ls180.v:3733$377 + assign { } { } + assign $0\main_sdram_choose_req_cmd_payload_cas[0:0] 1'0 + attribute \src "build/ls180/gateware/ls180.v:3735.2-3737.5" + switch \main_sdram_choose_req_cmd_valid + attribute \src "build/ls180/gateware/ls180.v:3735.6-3735.37" + case 1'1 + assign $0\main_sdram_choose_req_cmd_payload_cas[0:0] \builder_comb_t_array_muxed3 + case + end + sync always + update \main_sdram_choose_req_cmd_payload_cas $0\main_sdram_choose_req_cmd_payload_cas[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:3739.1-3744.4" + process $proc$build/ls180/gateware/ls180.v:3739$378 + assign { } { } + assign $0\main_sdram_choose_req_cmd_payload_ras[0:0] 1'0 + attribute \src "build/ls180/gateware/ls180.v:3741.2-3743.5" + switch \main_sdram_choose_req_cmd_valid + attribute \src "build/ls180/gateware/ls180.v:3741.6-3741.37" + case 1'1 + assign $0\main_sdram_choose_req_cmd_payload_ras[0:0] \builder_comb_t_array_muxed4 + case + end + sync always + update \main_sdram_choose_req_cmd_payload_ras $0\main_sdram_choose_req_cmd_payload_ras[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:374.5-374.42" + process $proc$build/ls180/gateware/ls180.v:374$2690 + assign { } { } + assign $1\main_sdram_master_p0_wrdata_en[0:0] 1'0 + sync always + sync init + update \main_sdram_master_p0_wrdata_en $1\main_sdram_master_p0_wrdata_en[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:3745.1-3750.4" + process $proc$build/ls180/gateware/ls180.v:3745$379 + assign { } { } + assign $0\main_sdram_choose_req_cmd_payload_we[0:0] 1'0 + attribute \src "build/ls180/gateware/ls180.v:3747.2-3749.5" + switch \main_sdram_choose_req_cmd_valid + attribute \src "build/ls180/gateware/ls180.v:3747.6-3747.37" + case 1'1 + assign $0\main_sdram_choose_req_cmd_payload_we[0:0] \builder_comb_t_array_muxed5 + case + end + sync always + update \main_sdram_choose_req_cmd_payload_we $0\main_sdram_choose_req_cmd_payload_we[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:375.11-375.50" + process $proc$build/ls180/gateware/ls180.v:375$2691 + assign { } { } + assign $1\main_sdram_master_p0_wrdata_mask[1:0] 2'00 + sync always + sync init + update \main_sdram_master_p0_wrdata_mask $1\main_sdram_master_p0_wrdata_mask[1:0] + end + attribute \src "build/ls180/gateware/ls180.v:3751.1-3759.4" + process $proc$build/ls180/gateware/ls180.v:3751$380 + assign { } { } + assign $0\main_sdram_bankmachine0_cmd_ready[0:0] 1'0 + attribute \src "build/ls180/gateware/ls180.v:3753.2-3755.5" + switch $and$build/ls180/gateware/ls180.v:3753$383_Y + attribute \src "build/ls180/gateware/ls180.v:3753.6-3753.115" + case 1'1 + assign $0\main_sdram_bankmachine0_cmd_ready[0:0] 1'1 + case + end + attribute \src "build/ls180/gateware/ls180.v:3756.2-3758.5" + switch $and$build/ls180/gateware/ls180.v:3756$386_Y + attribute \src "build/ls180/gateware/ls180.v:3756.6-3756.115" + case 1'1 + assign $0\main_sdram_bankmachine0_cmd_ready[0:0] 1'1 + case + end + sync always + update \main_sdram_bankmachine0_cmd_ready $0\main_sdram_bankmachine0_cmd_ready[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:376.5-376.42" + process $proc$build/ls180/gateware/ls180.v:376$2692 + assign { } { } + assign $1\main_sdram_master_p0_rddata_en[0:0] 1'0 + sync always + sync init + update \main_sdram_master_p0_rddata_en $1\main_sdram_master_p0_rddata_en[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:3760.1-3768.4" + process $proc$build/ls180/gateware/ls180.v:3760$387 + assign { } { } + assign $0\main_sdram_bankmachine1_cmd_ready[0:0] 1'0 + attribute \src "build/ls180/gateware/ls180.v:3762.2-3764.5" + switch $and$build/ls180/gateware/ls180.v:3762$390_Y + attribute \src "build/ls180/gateware/ls180.v:3762.6-3762.115" + case 1'1 + assign $0\main_sdram_bankmachine1_cmd_ready[0:0] 1'1 + case + end + attribute \src "build/ls180/gateware/ls180.v:3765.2-3767.5" + switch $and$build/ls180/gateware/ls180.v:3765$393_Y + attribute \src "build/ls180/gateware/ls180.v:3765.6-3765.115" + case 1'1 + assign $0\main_sdram_bankmachine1_cmd_ready[0:0] 1'1 + case + end + sync always + update \main_sdram_bankmachine1_cmd_ready $0\main_sdram_bankmachine1_cmd_ready[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:3769.1-3777.4" + process $proc$build/ls180/gateware/ls180.v:3769$394 + assign { } { } + assign $0\main_sdram_bankmachine2_cmd_ready[0:0] 1'0 + attribute \src "build/ls180/gateware/ls180.v:3771.2-3773.5" + switch $and$build/ls180/gateware/ls180.v:3771$397_Y + attribute \src "build/ls180/gateware/ls180.v:3771.6-3771.115" + case 1'1 + assign $0\main_sdram_bankmachine2_cmd_ready[0:0] 1'1 + case + end + attribute \src "build/ls180/gateware/ls180.v:3774.2-3776.5" + switch $and$build/ls180/gateware/ls180.v:3774$400_Y + attribute \src "build/ls180/gateware/ls180.v:3774.6-3774.115" + case 1'1 + assign $0\main_sdram_bankmachine2_cmd_ready[0:0] 1'1 + case + end + sync always + update \main_sdram_bankmachine2_cmd_ready $0\main_sdram_bankmachine2_cmd_ready[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:3778.1-3786.4" + process $proc$build/ls180/gateware/ls180.v:3778$401 + assign { } { } + assign $0\main_sdram_bankmachine3_cmd_ready[0:0] 1'0 + attribute \src "build/ls180/gateware/ls180.v:3780.2-3782.5" + switch $and$build/ls180/gateware/ls180.v:3780$404_Y + attribute \src "build/ls180/gateware/ls180.v:3780.6-3780.115" + case 1'1 + assign $0\main_sdram_bankmachine3_cmd_ready[0:0] 1'1 + case + end + attribute \src "build/ls180/gateware/ls180.v:3783.2-3785.5" + switch $and$build/ls180/gateware/ls180.v:3783$407_Y + attribute \src "build/ls180/gateware/ls180.v:3783.6-3783.115" + case 1'1 + assign $0\main_sdram_bankmachine3_cmd_ready[0:0] 1'1 + case + end + sync always + update \main_sdram_bankmachine3_cmd_ready $0\main_sdram_bankmachine3_cmd_ready[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:3791.1-3863.4" + process $proc$build/ls180/gateware/ls180.v:3791$410 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\main_sdram_en1[0:0] 1'0 + assign $0\main_sdram_choose_req_want_reads[0:0] 1'0 + assign $0\main_sdram_choose_req_want_writes[0:0] 1'0 + assign $0\main_sdram_cmd_ready[0:0] 1'0 + assign { } { } + assign $0\main_sdram_choose_req_cmd_ready[0:0] 1'0 + assign $0\main_sdram_steerer_sel[1:0] 2'00 + assign $0\main_sdram_en0[0:0] 1'0 + assign $0\main_sdram_choose_req_want_activates[0:0] \main_sdram_ras_allowed + assign $0\builder_multiplexer_next_state[2:0] \builder_multiplexer_state + attribute \src "build/ls180/gateware/ls180.v:3803.2-3862.9" + switch \builder_multiplexer_state + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case 3'001 + assign $0\main_sdram_en1[0:0] 1'1 + assign $0\main_sdram_choose_req_want_writes[0:0] 1'1 + assign $0\main_sdram_steerer_sel[1:0] 2'10 + attribute \src "build/ls180/gateware/ls180.v:3807.4-3813.7" + switch 1'1 + attribute \src "build/ls180/gateware/ls180.v:3807.8-3807.12" + case 1'1 + assign $0\main_sdram_choose_req_cmd_ready[0:0] $and$build/ls180/gateware/ls180.v:3808$417_Y + case + end + attribute \src "build/ls180/gateware/ls180.v:3815.4-3819.7" + switch \main_sdram_read_available + attribute \src "build/ls180/gateware/ls180.v:3815.8-3815.33" + case 1'1 + attribute \src "build/ls180/gateware/ls180.v:3816.5-3818.8" + switch $or$build/ls180/gateware/ls180.v:3816$419_Y + attribute \src "build/ls180/gateware/ls180.v:3816.9-3816.63" + case 1'1 + assign $0\builder_multiplexer_next_state[2:0] 3'011 + case + end + case + end + attribute \src "build/ls180/gateware/ls180.v:3820.4-3822.7" + switch \main_sdram_go_to_refresh + attribute \src "build/ls180/gateware/ls180.v:3820.8-3820.32" + case 1'1 + assign $0\builder_multiplexer_next_state[2:0] 3'010 + case + end + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case 3'010 + assign $0\main_sdram_steerer_sel[1:0] 2'11 + assign $0\main_sdram_cmd_ready[0:0] 1'1 + attribute \src "build/ls180/gateware/ls180.v:3827.4-3829.7" + switch \main_sdram_cmd_last + attribute \src "build/ls180/gateware/ls180.v:3827.8-3827.27" + case 1'1 + assign $0\builder_multiplexer_next_state[2:0] 3'000 + case + end + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case 3'011 + attribute \src "build/ls180/gateware/ls180.v:3832.4-3834.7" + switch \main_sdram_twtrcon_ready + attribute \src "build/ls180/gateware/ls180.v:3832.8-3832.32" + case 1'1 + assign $0\builder_multiplexer_next_state[2:0] 3'000 + case + end + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case 3'100 + assign $0\builder_multiplexer_next_state[2:0] 3'101 + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case 3'101 + assign $0\builder_multiplexer_next_state[2:0] 3'001 + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case + assign $0\main_sdram_en0[0:0] 1'1 + assign $0\main_sdram_choose_req_want_reads[0:0] 1'1 + assign $0\main_sdram_steerer_sel[1:0] 2'10 + attribute \src "build/ls180/gateware/ls180.v:3845.4-3851.7" + switch 1'1 + attribute \src "build/ls180/gateware/ls180.v:3845.8-3845.12" + case 1'1 + assign $0\main_sdram_choose_req_cmd_ready[0:0] $and$build/ls180/gateware/ls180.v:3846$426_Y + case + end + attribute \src "build/ls180/gateware/ls180.v:3853.4-3857.7" + switch \main_sdram_write_available + attribute \src "build/ls180/gateware/ls180.v:3853.8-3853.34" + case 1'1 + attribute \src "build/ls180/gateware/ls180.v:3854.5-3856.8" + switch $or$build/ls180/gateware/ls180.v:3854$428_Y + attribute \src "build/ls180/gateware/ls180.v:3854.9-3854.62" + case 1'1 + assign $0\builder_multiplexer_next_state[2:0] 3'100 + case + end + case + end + attribute \src "build/ls180/gateware/ls180.v:3858.4-3860.7" + switch \main_sdram_go_to_refresh + attribute \src "build/ls180/gateware/ls180.v:3858.8-3858.32" + case 1'1 + assign $0\builder_multiplexer_next_state[2:0] 3'010 + case + end + end + sync always + update \main_sdram_cmd_ready $0\main_sdram_cmd_ready[0:0] + update \main_sdram_choose_req_want_reads $0\main_sdram_choose_req_want_reads[0:0] + update \main_sdram_choose_req_want_writes $0\main_sdram_choose_req_want_writes[0:0] + update \main_sdram_choose_req_want_activates $0\main_sdram_choose_req_want_activates[0:0] + update \main_sdram_choose_req_cmd_ready $0\main_sdram_choose_req_cmd_ready[0:0] + update \main_sdram_steerer_sel $0\main_sdram_steerer_sel[1:0] + update \main_sdram_en0 $0\main_sdram_en0[0:0] + update \main_sdram_en1 $0\main_sdram_en1[0:0] + update \builder_multiplexer_next_state $0\builder_multiplexer_next_state[2:0] + end + attribute \src "build/ls180/gateware/ls180.v:383.11-383.36" + process $proc$build/ls180/gateware/ls180.v:383$2693 + assign { } { } + assign $1\main_sdram_storage[3:0] 4'0001 + sync always + sync init + update \main_sdram_storage $1\main_sdram_storage[3:0] + end + attribute \src "build/ls180/gateware/ls180.v:384.5-384.25" + process $proc$build/ls180/gateware/ls180.v:384$2694 + assign { } { } + assign $1\main_sdram_re[0:0] 1'0 + sync always + sync init + update \main_sdram_re $1\main_sdram_re[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:385.11-385.44" + process $proc$build/ls180/gateware/ls180.v:385$2695 + assign { } { } + assign $1\main_sdram_command_storage[5:0] 6'000000 + sync always + sync init + update \main_sdram_command_storage $1\main_sdram_command_storage[5:0] + end + attribute \src "build/ls180/gateware/ls180.v:386.5-386.33" + process $proc$build/ls180/gateware/ls180.v:386$2696 + assign { } { } + assign $1\main_sdram_command_re[0:0] 1'0 + sync always + sync init + update \main_sdram_command_re $1\main_sdram_command_re[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:3887.1-3900.4" + process $proc$build/ls180/gateware/ls180.v:3887$557 + assign { } { } + assign { } { } + assign $0\main_sdram_interface_wdata[15:0] 16'0000000000000000 + assign $0\main_sdram_interface_wdata_we[1:0] 2'00 + attribute \src "build/ls180/gateware/ls180.v:3890.2-3899.9" + switch \builder_new_master_wdata_ready + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case 1'1 + assign $0\main_sdram_interface_wdata[15:0] \main_port_wdata_payload_data + assign $0\main_sdram_interface_wdata_we[1:0] \main_port_wdata_payload_we + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case + assign $0\main_sdram_interface_wdata[15:0] 16'0000000000000000 + assign $0\main_sdram_interface_wdata_we[1:0] 2'00 + end + sync always + update \main_sdram_interface_wdata $0\main_sdram_interface_wdata[15:0] + update \main_sdram_interface_wdata_we $0\main_sdram_interface_wdata_we[1:0] + end + attribute \src "build/ls180/gateware/ls180.v:390.5-390.38" + process $proc$build/ls180/gateware/ls180.v:390$2697 + assign { } { } + assign $0\main_sdram_command_issue_w[0:0] 1'0 + sync always + update \main_sdram_command_issue_w $0\main_sdram_command_issue_w[0:0] + sync init + end + attribute \src "build/ls180/gateware/ls180.v:3907.1-3917.4" + process $proc$build/ls180/gateware/ls180.v:3907$559 + assign { } { } + assign $0\main_litedram_wb_dat_w[15:0] 16'0000000000000000 + attribute \src "build/ls180/gateware/ls180.v:3909.2-3916.9" + switch \main_converter_counter + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case 1'0 + assign $0\main_litedram_wb_dat_w[15:0] \main_wb_sdram_dat_w [15:0] + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case 1'1 + assign $0\main_litedram_wb_dat_w[15:0] \main_wb_sdram_dat_w [31:16] + case + end + sync always + update \main_litedram_wb_dat_w $0\main_litedram_wb_dat_w[15:0] + end + attribute \src "build/ls180/gateware/ls180.v:391.12-391.46" + process $proc$build/ls180/gateware/ls180.v:391$2698 + assign { } { } + assign $1\main_sdram_address_storage[12:0] 13'0000000000000 + sync always + sync init + update \main_sdram_address_storage $1\main_sdram_address_storage[12:0] + end + attribute \src "build/ls180/gateware/ls180.v:3919.1-3965.4" + process $proc$build/ls180/gateware/ls180.v:3919$560 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\main_litedram_wb_adr[29:0] 30'000000000000000000000000000000 + assign $0\main_wb_sdram_ack[0:0] 1'0 + assign $0\main_litedram_wb_sel[1:0] 2'00 + assign { } { } + assign $0\main_litedram_wb_cyc[0:0] 1'0 + assign $0\main_converter_counter_converter_next_value[0:0] 1'0 + assign $0\main_litedram_wb_stb[0:0] 1'0 + assign $0\main_converter_counter_converter_next_value_ce[0:0] 1'0 + assign $0\main_litedram_wb_we[0:0] 1'0 + assign $0\main_converter_skip[0:0] 1'0 + assign $0\builder_converter_next_state[0:0] \builder_converter_state + attribute \src "build/ls180/gateware/ls180.v:3931.2-3964.9" + switch \builder_converter_state + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case 1'1 + assign $0\main_litedram_wb_adr[29:0] { \main_wb_sdram_adr [28:0] \main_converter_counter } + attribute \src "build/ls180/gateware/ls180.v:3934.4-3941.11" + switch \main_converter_counter + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case 1'0 + assign $0\main_litedram_wb_sel[1:0] \main_wb_sdram_sel [1:0] + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case 1'1 + assign $0\main_litedram_wb_sel[1:0] \main_wb_sdram_sel [3:2] + case + end + attribute \src "build/ls180/gateware/ls180.v:3942.4-3955.7" + switch $and$build/ls180/gateware/ls180.v:3942$561_Y + attribute \src "build/ls180/gateware/ls180.v:3942.8-3942.47" + case 1'1 + assign $0\main_converter_skip[0:0] $eq$build/ls180/gateware/ls180.v:3943$562_Y + assign $0\main_litedram_wb_we[0:0] \main_wb_sdram_we + assign $0\main_litedram_wb_cyc[0:0] $not$build/ls180/gateware/ls180.v:3945$563_Y + assign $0\main_litedram_wb_stb[0:0] $not$build/ls180/gateware/ls180.v:3946$564_Y + attribute \src "build/ls180/gateware/ls180.v:3947.5-3954.8" + switch $or$build/ls180/gateware/ls180.v:3947$565_Y + attribute \src "build/ls180/gateware/ls180.v:3947.9-3947.53" + case 1'1 + assign $0\main_converter_counter_converter_next_value[0:0] $add$build/ls180/gateware/ls180.v:3948$566_Y + assign $0\main_converter_counter_converter_next_value_ce[0:0] 1'1 + attribute \src "build/ls180/gateware/ls180.v:3950.6-3953.9" + switch $eq$build/ls180/gateware/ls180.v:3950$567_Y + attribute \src "build/ls180/gateware/ls180.v:3950.10-3950.42" + case 1'1 + assign $0\main_wb_sdram_ack[0:0] 1'1 + assign $0\builder_converter_next_state[0:0] 1'0 + case + end + case + end + case + end + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case + assign $0\main_converter_counter_converter_next_value[0:0] 1'0 + assign $0\main_converter_counter_converter_next_value_ce[0:0] 1'1 + attribute \src "build/ls180/gateware/ls180.v:3960.4-3962.7" + switch $and$build/ls180/gateware/ls180.v:3960$568_Y + attribute \src "build/ls180/gateware/ls180.v:3960.8-3960.47" + case 1'1 + assign $0\builder_converter_next_state[0:0] 1'1 + case + end + end + sync always + update \main_wb_sdram_ack $0\main_wb_sdram_ack[0:0] + update \main_litedram_wb_adr $0\main_litedram_wb_adr[29:0] + update \main_litedram_wb_sel $0\main_litedram_wb_sel[1:0] + update \main_litedram_wb_cyc $0\main_litedram_wb_cyc[0:0] + update \main_litedram_wb_stb $0\main_litedram_wb_stb[0:0] + update \main_litedram_wb_we $0\main_litedram_wb_we[0:0] + update \main_converter_skip $0\main_converter_skip[0:0] + update \builder_converter_next_state $0\builder_converter_next_state[0:0] + update \main_converter_counter_converter_next_value $0\main_converter_counter_converter_next_value[0:0] + update \main_converter_counter_converter_next_value_ce $0\main_converter_counter_converter_next_value_ce[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:392.5-392.33" + process $proc$build/ls180/gateware/ls180.v:392$2699 + assign { } { } + assign $1\main_sdram_address_re[0:0] 1'0 + sync always + sync init + update \main_sdram_address_re $1\main_sdram_address_re[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:393.11-393.45" + process $proc$build/ls180/gateware/ls180.v:393$2700 + assign { } { } + assign $1\main_sdram_baddress_storage[1:0] 2'00 + sync always + sync init + update \main_sdram_baddress_storage $1\main_sdram_baddress_storage[1:0] + end + attribute \src "build/ls180/gateware/ls180.v:394.5-394.34" + process $proc$build/ls180/gateware/ls180.v:394$2701 + assign { } { } + assign $1\main_sdram_baddress_re[0:0] 1'0 + sync always + sync init + update \main_sdram_baddress_re $1\main_sdram_baddress_re[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:395.12-395.45" + process $proc$build/ls180/gateware/ls180.v:395$2702 + assign { } { } + assign $1\main_sdram_wrdata_storage[15:0] 16'0000000000000000 + sync always + sync init + update \main_sdram_wrdata_storage $1\main_sdram_wrdata_storage[15:0] + end + attribute \src "build/ls180/gateware/ls180.v:396.5-396.32" + process $proc$build/ls180/gateware/ls180.v:396$2703 + assign { } { } + assign $1\main_sdram_wrdata_re[0:0] 1'0 + sync always + sync init + update \main_sdram_wrdata_re $1\main_sdram_wrdata_re[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:397.12-397.37" + process $proc$build/ls180/gateware/ls180.v:397$2704 + assign { } { } + assign $1\main_sdram_status[15:0] 16'0000000000000000 + sync always + sync init + update \main_sdram_status $1\main_sdram_status[15:0] + end + attribute \src "build/ls180/gateware/ls180.v:3989.1-4037.4" + process $proc$build/ls180/gateware/ls180.v:3989$596 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\main_miso_latch[0:0] 1'0 + assign { } { } + assign $0\main_count_spimaster0_next_value[2:0] 3'000 + assign $0\main_count_spimaster0_next_value_ce[0:0] 1'0 + assign $0\main_clk_enable[0:0] 1'0 + assign $0\main_cs_enable[0:0] 1'0 + assign $0\main_mosi_latch[0:0] 1'0 + assign $0\main_done0[0:0] 1'0 + assign $0\main_irq[0:0] 1'0 + assign $0\builder_spimaster0_next_state[1:0] \builder_spimaster0_state + attribute \src "build/ls180/gateware/ls180.v:4000.2-4036.9" + switch \builder_spimaster0_state + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case 2'01 + assign $0\main_count_spimaster0_next_value[2:0] 3'000 + assign $0\main_count_spimaster0_next_value_ce[0:0] 1'1 + attribute \src "build/ls180/gateware/ls180.v:4004.4-4007.7" + switch \main_clk_fall + attribute \src "build/ls180/gateware/ls180.v:4004.8-4004.21" + case 1'1 + assign $0\main_cs_enable[0:0] 1'1 + assign $0\builder_spimaster0_next_state[1:0] 2'10 + case + end + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case 2'10 + assign $0\main_clk_enable[0:0] 1'1 + assign $0\main_cs_enable[0:0] 1'1 + attribute \src "build/ls180/gateware/ls180.v:4012.4-4018.7" + switch \main_clk_fall + attribute \src "build/ls180/gateware/ls180.v:4012.8-4012.21" + case 1'1 + assign $0\main_count_spimaster0_next_value[2:0] $add$build/ls180/gateware/ls180.v:4013$597_Y + assign $0\main_count_spimaster0_next_value_ce[0:0] 1'1 + attribute \src "build/ls180/gateware/ls180.v:4015.5-4017.8" + switch $eq$build/ls180/gateware/ls180.v:4015$599_Y + attribute \src "build/ls180/gateware/ls180.v:4015.9-4015.46" + case 1'1 + assign $0\builder_spimaster0_next_state[1:0] 2'11 + case + end + case + end + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case 2'11 + assign $0\main_cs_enable[0:0] 1'1 + attribute \src "build/ls180/gateware/ls180.v:4022.4-4026.7" + switch \main_clk_rise + attribute \src "build/ls180/gateware/ls180.v:4022.8-4022.21" + case 1'1 + assign $0\main_miso_latch[0:0] 1'1 + assign $0\main_irq[0:0] 1'1 + assign $0\builder_spimaster0_next_state[1:0] 2'00 + case + end + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case + assign $0\main_done0[0:0] 1'1 + attribute \src "build/ls180/gateware/ls180.v:4030.4-4034.7" + switch \main_start0 + attribute \src "build/ls180/gateware/ls180.v:4030.8-4030.19" + case 1'1 + assign $0\main_done0[0:0] 1'0 + assign $0\main_mosi_latch[0:0] 1'1 + assign $0\builder_spimaster0_next_state[1:0] 2'01 + case + end + end + sync always + update \main_done0 $0\main_done0[0:0] + update \main_irq $0\main_irq[0:0] + update \main_clk_enable $0\main_clk_enable[0:0] + update \main_cs_enable $0\main_cs_enable[0:0] + update \main_mosi_latch $0\main_mosi_latch[0:0] + update \main_miso_latch $0\main_miso_latch[0:0] + update \builder_spimaster0_next_state $0\builder_spimaster0_next_state[1:0] + update \main_count_spimaster0_next_value $0\main_count_spimaster0_next_value[2:0] + update \main_count_spimaster0_next_value_ce $0\main_count_spimaster0_next_value_ce[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:4065.1-4093.4" + process $proc$build/ls180/gateware/ls180.v:4065$621 + assign { } { } + assign $0\libresocsim_clocker_clk1[0:0] 1'0 + attribute \src "build/ls180/gateware/ls180.v:4067.2-4092.9" + switch \libresocsim_clocker_storage + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case 9'000000100 + assign $0\libresocsim_clocker_clk1[0:0] \libresocsim_clocker_clks [1] + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case 9'000001000 + assign $0\libresocsim_clocker_clk1[0:0] \libresocsim_clocker_clks [2] + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case 9'000010000 + assign $0\libresocsim_clocker_clk1[0:0] \libresocsim_clocker_clks [3] + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case 9'000100000 + assign $0\libresocsim_clocker_clk1[0:0] \libresocsim_clocker_clks [4] + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case 9'001000000 + assign $0\libresocsim_clocker_clk1[0:0] \libresocsim_clocker_clks [5] + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case 9'010000000 + assign $0\libresocsim_clocker_clk1[0:0] \libresocsim_clocker_clks [6] + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case 9'100000000 + assign $0\libresocsim_clocker_clk1[0:0] \libresocsim_clocker_clks [7] + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case + assign $0\libresocsim_clocker_clk1[0:0] \libresocsim_clocker_clks [0] + end + sync always + update \libresocsim_clocker_clk1 $0\libresocsim_clocker_clk1[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:4095.1-4128.4" + process $proc$build/ls180/gateware/ls180.v:4095$624 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\libresocsim_init_count_sdphy_sdphyinit_next_value[7:0] 8'00000000 + assign $0\libresocsim_init_pads_out_payload_data_oe[0:0] 1'0 + assign $0\libresocsim_init_count_sdphy_sdphyinit_next_value_ce[0:0] 1'0 + assign $0\libresocsim_init_pads_out_payload_data_o[3:0] 4'0000 + assign $0\libresocsim_init_pads_out_payload_clk[0:0] 1'0 + assign $0\libresocsim_init_pads_out_payload_cmd_o[0:0] 1'0 + assign $0\libresocsim_init_pads_out_payload_cmd_oe[0:0] 1'0 + assign { } { } + assign $0\builder_sdphy_sdphyinit_next_state[0:0] \builder_sdphy_sdphyinit_state + attribute \src "build/ls180/gateware/ls180.v:4105.2-4127.9" + switch \builder_sdphy_sdphyinit_state + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case 1'1 + assign $0\libresocsim_init_pads_out_payload_clk[0:0] 1'1 + assign $0\libresocsim_init_pads_out_payload_cmd_oe[0:0] 1'1 + assign $0\libresocsim_init_pads_out_payload_cmd_o[0:0] 1'1 + assign $0\libresocsim_init_pads_out_payload_data_oe[0:0] 1'1 + assign $0\libresocsim_init_pads_out_payload_data_o[3:0] 4'1111 + attribute \src "build/ls180/gateware/ls180.v:4112.4-4118.7" + switch \libresocsim_init_pads_out_ready + attribute \src "build/ls180/gateware/ls180.v:4112.8-4112.39" + case 1'1 + assign $0\libresocsim_init_count_sdphy_sdphyinit_next_value[7:0] $add$build/ls180/gateware/ls180.v:4113$625_Y + assign $0\libresocsim_init_count_sdphy_sdphyinit_next_value_ce[0:0] 1'1 + attribute \src "build/ls180/gateware/ls180.v:4115.5-4117.8" + switch $eq$build/ls180/gateware/ls180.v:4115$626_Y + attribute \src "build/ls180/gateware/ls180.v:4115.9-4115.42" + case 1'1 + assign $0\builder_sdphy_sdphyinit_next_state[0:0] 1'0 + case + end + case + end + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case + assign $0\libresocsim_init_count_sdphy_sdphyinit_next_value[7:0] 8'00000000 + assign $0\libresocsim_init_count_sdphy_sdphyinit_next_value_ce[0:0] 1'1 + attribute \src "build/ls180/gateware/ls180.v:4123.4-4125.7" + switch \libresocsim_init_initialize_re + attribute \src "build/ls180/gateware/ls180.v:4123.8-4123.38" + case 1'1 + assign $0\builder_sdphy_sdphyinit_next_state[0:0] 1'1 + case + end + end + sync always + update \libresocsim_init_pads_out_payload_clk $0\libresocsim_init_pads_out_payload_clk[0:0] + update \libresocsim_init_pads_out_payload_cmd_o $0\libresocsim_init_pads_out_payload_cmd_o[0:0] + update \libresocsim_init_pads_out_payload_cmd_oe $0\libresocsim_init_pads_out_payload_cmd_oe[0:0] + update \libresocsim_init_pads_out_payload_data_o $0\libresocsim_init_pads_out_payload_data_o[3:0] + update \libresocsim_init_pads_out_payload_data_oe $0\libresocsim_init_pads_out_payload_data_oe[0:0] + update \builder_sdphy_sdphyinit_next_state $0\builder_sdphy_sdphyinit_next_state[0:0] + update \libresocsim_init_count_sdphy_sdphyinit_next_value $0\libresocsim_init_count_sdphy_sdphyinit_next_value[7:0] + update \libresocsim_init_count_sdphy_sdphyinit_next_value_ce $0\libresocsim_init_count_sdphy_sdphyinit_next_value_ce[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:41.12-41.61" + process $proc$build/ls180/gateware/ls180.v:41$2567 + assign { } { } + assign $1\main_libresocsim_soccontroller_bus_errors[31:0] 0 + sync always + sync init + update \main_libresocsim_soccontroller_bus_errors $1\main_libresocsim_soccontroller_bus_errors[31:0] + end + attribute \src "build/ls180/gateware/ls180.v:4129.1-4205.4" + process $proc$build/ls180/gateware/ls180.v:4129$627 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\libresocsim_cmdw_done[0:0] 1'0 + assign $0\libresocsim_cmdw_pads_out_payload_clk[0:0] 1'0 + assign $0\libresocsim_cmdw_pads_out_payload_cmd_o[0:0] 1'0 + assign { } { } + assign $0\libresocsim_cmdw_pads_out_payload_cmd_oe[0:0] 1'0 + assign $0\libresocsim_cmdw_count_sdphy_sdphycmdw_next_value[7:0] 8'00000000 + assign $0\libresocsim_cmdw_count_sdphy_sdphycmdw_next_value_ce[0:0] 1'0 + assign $0\libresocsim_cmdw_sink_ready[0:0] 1'0 + assign $0\builder_sdphy_sdphycmdw_next_state[1:0] \builder_sdphy_sdphycmdw_state + attribute \src "build/ls180/gateware/ls180.v:4139.2-4204.9" + switch \builder_sdphy_sdphycmdw_state + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case 2'01 + assign $0\libresocsim_cmdw_pads_out_payload_clk[0:0] 1'1 + assign $0\libresocsim_cmdw_pads_out_payload_cmd_oe[0:0] 1'1 + attribute \src "build/ls180/gateware/ls180.v:4143.4-4168.11" + switch \libresocsim_cmdw_count + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case 8'00000000 + assign $0\libresocsim_cmdw_pads_out_payload_cmd_o[0:0] \libresocsim_cmdw_sink_payload_data [7] + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case 8'00000001 + assign $0\libresocsim_cmdw_pads_out_payload_cmd_o[0:0] \libresocsim_cmdw_sink_payload_data [6] + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case 8'00000010 + assign $0\libresocsim_cmdw_pads_out_payload_cmd_o[0:0] \libresocsim_cmdw_sink_payload_data [5] + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case 8'00000011 + assign $0\libresocsim_cmdw_pads_out_payload_cmd_o[0:0] \libresocsim_cmdw_sink_payload_data [4] + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case 8'00000100 + assign $0\libresocsim_cmdw_pads_out_payload_cmd_o[0:0] \libresocsim_cmdw_sink_payload_data [3] + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case 8'00000101 + assign $0\libresocsim_cmdw_pads_out_payload_cmd_o[0:0] \libresocsim_cmdw_sink_payload_data [2] + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case 8'00000110 + assign $0\libresocsim_cmdw_pads_out_payload_cmd_o[0:0] \libresocsim_cmdw_sink_payload_data [1] + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case 8'00000111 + assign $0\libresocsim_cmdw_pads_out_payload_cmd_o[0:0] \libresocsim_cmdw_sink_payload_data [0] + case + end + attribute \src "build/ls180/gateware/ls180.v:4169.4-4180.7" + switch \libresocsim_cmdw_pads_out_ready + attribute \src "build/ls180/gateware/ls180.v:4169.8-4169.39" + case 1'1 + assign $0\libresocsim_cmdw_count_sdphy_sdphycmdw_next_value[7:0] $add$build/ls180/gateware/ls180.v:4170$628_Y + assign $0\libresocsim_cmdw_count_sdphy_sdphycmdw_next_value_ce[0:0] 1'1 + attribute \src "build/ls180/gateware/ls180.v:4172.5-4179.8" + switch $eq$build/ls180/gateware/ls180.v:4172$629_Y + attribute \src "build/ls180/gateware/ls180.v:4172.9-4172.41" + case 1'1 + attribute \src "build/ls180/gateware/ls180.v:4173.6-4178.9" + switch \libresocsim_cmdw_sink_last + attribute \src "build/ls180/gateware/ls180.v:4173.10-4173.36" + case 1'1 + assign $0\builder_sdphy_sdphycmdw_next_state[1:0] 2'10 + attribute \src "build/ls180/gateware/ls180.v:4175.10-4175.14" + case + assign $0\libresocsim_cmdw_sink_ready[0:0] 1'1 + assign $0\builder_sdphy_sdphycmdw_next_state[1:0] 2'00 + end + case + end + case + end + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case 2'10 + assign $0\libresocsim_cmdw_pads_out_payload_clk[0:0] 1'1 + assign $0\libresocsim_cmdw_pads_out_payload_cmd_oe[0:0] 1'1 + assign $0\libresocsim_cmdw_pads_out_payload_cmd_o[0:0] 1'1 + attribute \src "build/ls180/gateware/ls180.v:4186.4-4193.7" + switch \libresocsim_cmdw_pads_out_ready + attribute \src "build/ls180/gateware/ls180.v:4186.8-4186.39" + case 1'1 + assign $0\libresocsim_cmdw_count_sdphy_sdphycmdw_next_value[7:0] $add$build/ls180/gateware/ls180.v:4187$630_Y + assign $0\libresocsim_cmdw_count_sdphy_sdphycmdw_next_value_ce[0:0] 1'1 + attribute \src "build/ls180/gateware/ls180.v:4189.5-4192.8" + switch $eq$build/ls180/gateware/ls180.v:4189$631_Y + attribute \src "build/ls180/gateware/ls180.v:4189.9-4189.41" + case 1'1 + assign $0\libresocsim_cmdw_sink_ready[0:0] 1'1 + assign $0\builder_sdphy_sdphycmdw_next_state[1:0] 2'00 + case + end + case + end + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case + assign $0\libresocsim_cmdw_count_sdphy_sdphycmdw_next_value[7:0] 8'00000000 + assign $0\libresocsim_cmdw_count_sdphy_sdphycmdw_next_value_ce[0:0] 1'1 + attribute \src "build/ls180/gateware/ls180.v:4198.4-4202.7" + switch $and$build/ls180/gateware/ls180.v:4198$632_Y + attribute \src "build/ls180/gateware/ls180.v:4198.8-4198.71" + case 1'1 + assign $0\builder_sdphy_sdphycmdw_next_state[1:0] 2'01 + attribute \src "build/ls180/gateware/ls180.v:4200.8-4200.12" + case + assign $0\libresocsim_cmdw_done[0:0] 1'1 + end + end + sync always + update \libresocsim_cmdw_pads_out_payload_clk $0\libresocsim_cmdw_pads_out_payload_clk[0:0] + update \libresocsim_cmdw_pads_out_payload_cmd_o $0\libresocsim_cmdw_pads_out_payload_cmd_o[0:0] + update \libresocsim_cmdw_pads_out_payload_cmd_oe $0\libresocsim_cmdw_pads_out_payload_cmd_oe[0:0] + update \libresocsim_cmdw_sink_ready $0\libresocsim_cmdw_sink_ready[0:0] + update \libresocsim_cmdw_done $0\libresocsim_cmdw_done[0:0] + update \builder_sdphy_sdphycmdw_next_state $0\builder_sdphy_sdphycmdw_next_state[1:0] + update \libresocsim_cmdw_count_sdphy_sdphycmdw_next_value $0\libresocsim_cmdw_count_sdphy_sdphycmdw_next_value[7:0] + update \libresocsim_cmdw_count_sdphy_sdphycmdw_next_value_ce $0\libresocsim_cmdw_count_sdphy_sdphycmdw_next_value_ce[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:4239.1-4332.4" + process $proc$build/ls180/gateware/ls180.v:4239$641 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\libresocsim_cmdr_source_last[0:0] 1'0 + assign $0\libresocsim_cmdr_source_payload_data[7:0] 8'00000000 + assign $0\libresocsim_cmdr_source_payload_status[2:0] 3'000 + assign { } { } + assign $0\libresocsim_cmdr_count_sdphy_sdphycmdr_next_value0[7:0] 8'00000000 + assign $0\libresocsim_cmdr_count_sdphy_sdphycmdr_next_value_ce0[0:0] 1'0 + assign $0\libresocsim_cmdr_timeout_sdphy_sdphycmdr_next_value1[31:0] 0 + assign $0\libresocsim_cmdr_timeout_sdphy_sdphycmdr_next_value_ce1[0:0] 1'0 + assign $0\libresocsim_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value2[0:0] 1'0 + assign $0\libresocsim_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value_ce2[0:0] 1'0 + assign $0\libresocsim_cmdr_pads_out_payload_clk[0:0] 1'0 + assign $0\libresocsim_cmdr_cmdr_source_source_ready0[0:0] 1'0 + assign $0\libresocsim_cmdr_pads_out_payload_cmd_o[0:0] 1'0 + assign $0\libresocsim_cmdr_pads_out_payload_cmd_oe[0:0] 1'0 + assign $0\libresocsim_cmdr_sink_ready[0:0] 1'0 + assign $0\libresocsim_cmdr_source_valid[0:0] 1'0 + assign $0\builder_sdphy_sdphycmdr_next_state[2:0] \builder_sdphy_sdphycmdr_state + attribute \src "build/ls180/gateware/ls180.v:4257.2-4331.9" + switch \builder_sdphy_sdphycmdr_state + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case 3'001 + assign $0\libresocsim_cmdr_pads_out_payload_clk[0:0] 1'1 + assign $0\libresocsim_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value2[0:0] 1'0 + assign $0\libresocsim_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value_ce2[0:0] 1'1 + assign $0\libresocsim_cmdr_timeout_sdphy_sdphycmdr_next_value1[31:0] $sub$build/ls180/gateware/ls180.v:4265$642_Y + assign $0\libresocsim_cmdr_timeout_sdphy_sdphycmdr_next_value_ce1[0:0] 1'1 + attribute \src "build/ls180/gateware/ls180.v:4262.4-4264.7" + switch \libresocsim_cmdr_cmdr_source_source_valid0 + attribute \src "build/ls180/gateware/ls180.v:4262.8-4262.50" + case 1'1 + assign $0\builder_sdphy_sdphycmdr_next_state[2:0] 3'010 + case + end + attribute \src "build/ls180/gateware/ls180.v:4267.4-4270.7" + switch $eq$build/ls180/gateware/ls180.v:4267$643_Y + attribute \src "build/ls180/gateware/ls180.v:4267.8-4267.42" + case 1'1 + assign $0\libresocsim_cmdr_sink_ready[0:0] 1'1 + assign $0\builder_sdphy_sdphycmdr_next_state[2:0] 3'100 + case + end + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case 3'010 + assign $0\libresocsim_cmdr_pads_out_payload_clk[0:0] 1'1 + assign $0\libresocsim_cmdr_source_valid[0:0] \libresocsim_cmdr_cmdr_source_source_valid0 + assign $0\libresocsim_cmdr_source_payload_status[2:0] 3'000 + assign $0\libresocsim_cmdr_source_last[0:0] $eq$build/ls180/gateware/ls180.v:4276$645_Y + assign $0\libresocsim_cmdr_source_payload_data[7:0] \libresocsim_cmdr_cmdr_source_source_payload_data0 + assign $0\libresocsim_cmdr_timeout_sdphy_sdphycmdr_next_value1[31:0] $sub$build/ls180/gateware/ls180.v:4293$648_Y + assign $0\libresocsim_cmdr_timeout_sdphy_sdphycmdr_next_value_ce1[0:0] 1'1 + attribute \src "build/ls180/gateware/ls180.v:4278.4-4292.7" + switch $and$build/ls180/gateware/ls180.v:4278$646_Y + attribute \src "build/ls180/gateware/ls180.v:4278.8-4278.71" + case 1'1 + assign $0\libresocsim_cmdr_cmdr_source_source_ready0[0:0] 1'1 + assign $0\libresocsim_cmdr_count_sdphy_sdphycmdr_next_value0[7:0] $add$build/ls180/gateware/ls180.v:4280$647_Y + assign $0\libresocsim_cmdr_count_sdphy_sdphycmdr_next_value_ce0[0:0] 1'1 + attribute \src "build/ls180/gateware/ls180.v:4282.5-4291.8" + switch \libresocsim_cmdr_source_last + attribute \src "build/ls180/gateware/ls180.v:4282.9-4282.37" + case 1'1 + assign $0\libresocsim_cmdr_sink_ready[0:0] 1'1 + attribute \src "build/ls180/gateware/ls180.v:4284.6-4290.9" + switch \libresocsim_cmdr_sink_last + attribute \src "build/ls180/gateware/ls180.v:4284.10-4284.36" + case 1'1 + assign $0\libresocsim_cmdr_count_sdphy_sdphycmdr_next_value0[7:0] 8'00000000 + assign $0\libresocsim_cmdr_count_sdphy_sdphycmdr_next_value_ce0[0:0] 1'1 + assign $0\builder_sdphy_sdphycmdr_next_state[2:0] 3'011 + attribute \src "build/ls180/gateware/ls180.v:4288.10-4288.14" + case + assign $0\builder_sdphy_sdphycmdr_next_state[2:0] 3'000 + end + case + end + case + end + attribute \src "build/ls180/gateware/ls180.v:4295.4-4298.7" + switch $eq$build/ls180/gateware/ls180.v:4295$649_Y + attribute \src "build/ls180/gateware/ls180.v:4295.8-4295.42" + case 1'1 + assign $0\libresocsim_cmdr_sink_ready[0:0] 1'1 + assign $0\builder_sdphy_sdphycmdr_next_state[2:0] 3'100 + case + end + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case 3'011 + assign $0\libresocsim_cmdr_pads_out_payload_clk[0:0] 1'1 + assign $0\libresocsim_cmdr_pads_out_payload_cmd_oe[0:0] 1'1 + assign $0\libresocsim_cmdr_pads_out_payload_cmd_o[0:0] 1'1 + attribute \src "build/ls180/gateware/ls180.v:4304.4-4310.7" + switch \libresocsim_cmdr_pads_out_ready + attribute \src "build/ls180/gateware/ls180.v:4304.8-4304.39" + case 1'1 + assign $0\libresocsim_cmdr_count_sdphy_sdphycmdr_next_value0[7:0] $add$build/ls180/gateware/ls180.v:4305$650_Y + assign $0\libresocsim_cmdr_count_sdphy_sdphycmdr_next_value_ce0[0:0] 1'1 + attribute \src "build/ls180/gateware/ls180.v:4307.5-4309.8" + switch $eq$build/ls180/gateware/ls180.v:4307$651_Y + attribute \src "build/ls180/gateware/ls180.v:4307.9-4307.41" + case 1'1 + assign $0\builder_sdphy_sdphycmdr_next_state[2:0] 3'000 + case + end + case + end + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case 3'100 + assign $0\libresocsim_cmdr_source_valid[0:0] 1'1 + assign $0\libresocsim_cmdr_source_payload_status[2:0] 3'001 + assign $0\libresocsim_cmdr_source_last[0:0] 1'1 + attribute \src "build/ls180/gateware/ls180.v:4316.4-4318.7" + switch $and$build/ls180/gateware/ls180.v:4316$652_Y + attribute \src "build/ls180/gateware/ls180.v:4316.8-4316.71" + case 1'1 + assign $0\builder_sdphy_sdphycmdr_next_state[2:0] 3'000 + case + end + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case + assign $0\libresocsim_cmdr_count_sdphy_sdphycmdr_next_value0[7:0] 8'00000000 + assign $0\libresocsim_cmdr_count_sdphy_sdphycmdr_next_value_ce0[0:0] 1'1 + assign $0\libresocsim_cmdr_timeout_sdphy_sdphycmdr_next_value1[31:0] 500000 + assign $0\libresocsim_cmdr_timeout_sdphy_sdphycmdr_next_value_ce1[0:0] 1'1 + attribute \src "build/ls180/gateware/ls180.v:4325.4-4329.7" + switch $and$build/ls180/gateware/ls180.v:4325$654_Y + attribute \src "build/ls180/gateware/ls180.v:4325.8-4325.97" + case 1'1 + assign $0\libresocsim_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value2[0:0] 1'1 + assign $0\libresocsim_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value_ce2[0:0] 1'1 + assign $0\builder_sdphy_sdphycmdr_next_state[2:0] 3'001 + case + end + end + sync always + update \libresocsim_cmdr_pads_out_payload_clk $0\libresocsim_cmdr_pads_out_payload_clk[0:0] + update \libresocsim_cmdr_pads_out_payload_cmd_o $0\libresocsim_cmdr_pads_out_payload_cmd_o[0:0] + update \libresocsim_cmdr_pads_out_payload_cmd_oe $0\libresocsim_cmdr_pads_out_payload_cmd_oe[0:0] + update \libresocsim_cmdr_sink_ready $0\libresocsim_cmdr_sink_ready[0:0] + update \libresocsim_cmdr_source_valid $0\libresocsim_cmdr_source_valid[0:0] + update \libresocsim_cmdr_source_last $0\libresocsim_cmdr_source_last[0:0] + update \libresocsim_cmdr_source_payload_data $0\libresocsim_cmdr_source_payload_data[7:0] + update \libresocsim_cmdr_source_payload_status $0\libresocsim_cmdr_source_payload_status[2:0] + update \libresocsim_cmdr_cmdr_source_source_ready0 $0\libresocsim_cmdr_cmdr_source_source_ready0[0:0] + update \builder_sdphy_sdphycmdr_next_state $0\builder_sdphy_sdphycmdr_next_state[2:0] + update \libresocsim_cmdr_count_sdphy_sdphycmdr_next_value0 $0\libresocsim_cmdr_count_sdphy_sdphycmdr_next_value0[7:0] + update \libresocsim_cmdr_count_sdphy_sdphycmdr_next_value_ce0 $0\libresocsim_cmdr_count_sdphy_sdphycmdr_next_value_ce0[0:0] + update \libresocsim_cmdr_timeout_sdphy_sdphycmdr_next_value1 $0\libresocsim_cmdr_timeout_sdphy_sdphycmdr_next_value1[31:0] + update \libresocsim_cmdr_timeout_sdphy_sdphycmdr_next_value_ce1 $0\libresocsim_cmdr_timeout_sdphy_sdphycmdr_next_value_ce1[0:0] + update \libresocsim_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value2 $0\libresocsim_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value2[0:0] + update \libresocsim_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value_ce2 $0\libresocsim_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value_ce2[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:427.12-427.46" + process $proc$build/ls180/gateware/ls180.v:427$2705 + assign { } { } + assign $1\main_sdram_interface_wdata[15:0] 16'0000000000000000 + sync always + sync init + update \main_sdram_interface_wdata $1\main_sdram_interface_wdata[15:0] + end + attribute \src "build/ls180/gateware/ls180.v:428.11-428.47" + process $proc$build/ls180/gateware/ls180.v:428$2706 + assign { } { } + assign $1\main_sdram_interface_wdata_we[1:0] 2'00 + sync always + sync init + update \main_sdram_interface_wdata_we $1\main_sdram_interface_wdata_we[1:0] + end + attribute \src "build/ls180/gateware/ls180.v:43.12-43.55" + process $proc$build/ls180/gateware/ls180.v:43$2568 + assign { } { } + assign $1\main_libresocsim_libresoc_interrupt[15:0] 16'0000000000000000 + sync always + sync init + update \main_libresocsim_libresoc_interrupt $1\main_libresocsim_libresoc_interrupt[15:0] + end + attribute \src "build/ls180/gateware/ls180.v:430.12-430.45" + process $proc$build/ls180/gateware/ls180.v:430$2707 + assign { } { } + assign $1\main_sdram_dfi_p0_address[12:0] 13'0000000000000 + sync always + sync init + update \main_sdram_dfi_p0_address $1\main_sdram_dfi_p0_address[12:0] + end + attribute \src "build/ls180/gateware/ls180.v:431.11-431.40" + process $proc$build/ls180/gateware/ls180.v:431$2708 + assign { } { } + assign $1\main_sdram_dfi_p0_bank[1:0] 2'00 + sync always + sync init + update \main_sdram_dfi_p0_bank $1\main_sdram_dfi_p0_bank[1:0] + end + attribute \src "build/ls180/gateware/ls180.v:432.5-432.35" + process $proc$build/ls180/gateware/ls180.v:432$2709 + assign { } { } + assign $1\main_sdram_dfi_p0_cas_n[0:0] 1'1 + sync always + sync init + update \main_sdram_dfi_p0_cas_n $1\main_sdram_dfi_p0_cas_n[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:433.5-433.34" + process $proc$build/ls180/gateware/ls180.v:433$2710 + assign { } { } + assign $1\main_sdram_dfi_p0_cs_n[0:0] 1'1 + sync always + sync init + update \main_sdram_dfi_p0_cs_n $1\main_sdram_dfi_p0_cs_n[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:434.5-434.35" + process $proc$build/ls180/gateware/ls180.v:434$2711 + assign { } { } + assign $1\main_sdram_dfi_p0_ras_n[0:0] 1'1 + sync always + sync init + update \main_sdram_dfi_p0_ras_n $1\main_sdram_dfi_p0_ras_n[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:435.5-435.34" + process $proc$build/ls180/gateware/ls180.v:435$2712 + assign { } { } + assign $1\main_sdram_dfi_p0_we_n[0:0] 1'1 + sync always + sync init + update \main_sdram_dfi_p0_we_n $1\main_sdram_dfi_p0_we_n[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:4366.1-4393.4" + process $proc$build/ls180/gateware/ls180.v:4366$662 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\libresocsim_dataw_crcr_source_source_ready0[0:0] 1'0 + assign $0\libresocsim_dataw_valid[0:0] 1'0 + assign $0\libresocsim_dataw_error[0:0] 1'0 + assign { } { } + assign $0\libresocsim_dataw_crcr_reset_sdphy_sdphycrcr_next_value[0:0] 1'0 + assign $0\libresocsim_dataw_crcr_reset_sdphy_sdphycrcr_next_value_ce[0:0] 1'0 + assign $0\builder_sdphy_sdphycrcr_next_state[0:0] \builder_sdphy_sdphycrcr_state + attribute \src "build/ls180/gateware/ls180.v:4374.2-4392.9" + switch \builder_sdphy_sdphycrcr_state + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case 1'1 + assign $0\libresocsim_dataw_crcr_reset_sdphy_sdphycrcr_next_value[0:0] 1'0 + assign $0\libresocsim_dataw_crcr_reset_sdphy_sdphycrcr_next_value_ce[0:0] 1'1 + assign $0\libresocsim_dataw_crcr_source_source_ready0[0:0] 1'1 + attribute \src "build/ls180/gateware/ls180.v:4379.4-4383.7" + switch \libresocsim_dataw_crcr_source_source_valid0 + attribute \src "build/ls180/gateware/ls180.v:4379.8-4379.51" + case 1'1 + assign $0\libresocsim_dataw_valid[0:0] $ne$build/ls180/gateware/ls180.v:4380$663_Y + assign $0\libresocsim_dataw_error[0:0] $eq$build/ls180/gateware/ls180.v:4381$664_Y + assign $0\builder_sdphy_sdphycrcr_next_state[0:0] 1'0 + case + end + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case + attribute \src "build/ls180/gateware/ls180.v:4386.4-4390.7" + switch \libresocsim_dataw_start + attribute \src "build/ls180/gateware/ls180.v:4386.8-4386.31" + case 1'1 + assign $0\libresocsim_dataw_crcr_reset_sdphy_sdphycrcr_next_value[0:0] 1'1 + assign $0\libresocsim_dataw_crcr_reset_sdphy_sdphycrcr_next_value_ce[0:0] 1'1 + assign $0\builder_sdphy_sdphycrcr_next_state[0:0] 1'1 + case + end + end + sync always + update \libresocsim_dataw_valid $0\libresocsim_dataw_valid[0:0] + update \libresocsim_dataw_error $0\libresocsim_dataw_error[0:0] + update \libresocsim_dataw_crcr_source_source_ready0 $0\libresocsim_dataw_crcr_source_source_ready0[0:0] + update \builder_sdphy_sdphycrcr_next_state $0\builder_sdphy_sdphycrcr_next_state[0:0] + update \libresocsim_dataw_crcr_reset_sdphy_sdphycrcr_next_value $0\libresocsim_dataw_crcr_reset_sdphy_sdphycrcr_next_value[0:0] + update \libresocsim_dataw_crcr_reset_sdphy_sdphycrcr_next_value_ce $0\libresocsim_dataw_crcr_reset_sdphy_sdphycrcr_next_value_ce[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:439.5-439.35" + process $proc$build/ls180/gateware/ls180.v:439$2713 + assign { } { } + assign $0\main_sdram_dfi_p0_act_n[0:0] 1'1 + sync always + update \main_sdram_dfi_p0_act_n $0\main_sdram_dfi_p0_act_n[0:0] + sync init + end + attribute \src "build/ls180/gateware/ls180.v:4394.1-4466.4" + process $proc$build/ls180/gateware/ls180.v:4394$665 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\libresocsim_dataw_count_sdphy_fsm_next_value_ce[0:0] 1'0 + assign $0\libresocsim_dataw_pads_out_payload_data_o[3:0] 4'0000 + assign $0\libresocsim_dataw_pads_out_payload_data_oe[0:0] 1'0 + assign $0\libresocsim_dataw_sink_ready[0:0] 1'0 + assign $0\libresocsim_dataw_start[0:0] 1'0 + assign $0\libresocsim_dataw_stop[0:0] 1'0 + assign $0\libresocsim_dataw_pads_out_payload_clk[0:0] 1'0 + assign { } { } + assign $0\libresocsim_dataw_count_sdphy_fsm_next_value[7:0] 8'00000000 + assign $0\builder_sdphy_fsm_next_state[2:0] \builder_sdphy_fsm_state + attribute \src "build/ls180/gateware/ls180.v:4405.2-4465.9" + switch \builder_sdphy_fsm_state + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case 3'001 + assign $0\libresocsim_dataw_pads_out_payload_clk[0:0] 1'1 + assign $0\libresocsim_dataw_pads_out_payload_data_oe[0:0] 1'1 + assign $0\libresocsim_dataw_pads_out_payload_data_o[3:0] 4'0000 + attribute \src "build/ls180/gateware/ls180.v:4410.4-4412.7" + switch \libresocsim_dataw_pads_out_ready + attribute \src "build/ls180/gateware/ls180.v:4410.8-4410.40" + case 1'1 + assign $0\builder_sdphy_fsm_next_state[2:0] 3'010 + case + end + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case 3'010 + assign $0\libresocsim_dataw_stop[0:0] $not$build/ls180/gateware/ls180.v:4415$666_Y + assign $0\libresocsim_dataw_pads_out_payload_clk[0:0] 1'1 + assign $0\libresocsim_dataw_pads_out_payload_data_oe[0:0] 1'1 + attribute \src "build/ls180/gateware/ls180.v:4418.4-4425.11" + switch \libresocsim_dataw_count + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case 8'00000000 + assign $0\libresocsim_dataw_pads_out_payload_data_o[3:0] \libresocsim_dataw_sink_payload_data [7:4] + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case 8'00000001 + assign $0\libresocsim_dataw_pads_out_payload_data_o[3:0] \libresocsim_dataw_sink_payload_data [3:0] + case + end + attribute \src "build/ls180/gateware/ls180.v:4426.4-4438.7" + switch \libresocsim_dataw_pads_out_ready + attribute \src "build/ls180/gateware/ls180.v:4426.8-4426.40" + case 1'1 + assign $0\libresocsim_dataw_count_sdphy_fsm_next_value[7:0] $add$build/ls180/gateware/ls180.v:4427$667_Y + assign $0\libresocsim_dataw_count_sdphy_fsm_next_value_ce[0:0] 1'1 + attribute \src "build/ls180/gateware/ls180.v:4429.5-4437.8" + switch $eq$build/ls180/gateware/ls180.v:4429$668_Y + attribute \src "build/ls180/gateware/ls180.v:4429.9-4429.42" + case 1'1 + assign $0\libresocsim_dataw_count_sdphy_fsm_next_value[7:0] 8'00000000 + assign $0\libresocsim_dataw_count_sdphy_fsm_next_value_ce[0:0] 1'1 + attribute \src "build/ls180/gateware/ls180.v:4432.6-4436.9" + switch \libresocsim_dataw_sink_last + attribute \src "build/ls180/gateware/ls180.v:4432.10-4432.37" + case 1'1 + assign $0\builder_sdphy_fsm_next_state[2:0] 3'011 + attribute \src "build/ls180/gateware/ls180.v:4434.10-4434.14" + case + assign $0\libresocsim_dataw_sink_ready[0:0] 1'1 + end + case + end + case + end + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case 3'011 + assign $0\libresocsim_dataw_pads_out_payload_clk[0:0] 1'1 + assign $0\libresocsim_dataw_pads_out_payload_data_oe[0:0] 1'1 + assign $0\libresocsim_dataw_pads_out_payload_data_o[3:0] 4'1111 + attribute \src "build/ls180/gateware/ls180.v:4444.4-4447.7" + switch \libresocsim_dataw_pads_out_ready + attribute \src "build/ls180/gateware/ls180.v:4444.8-4444.40" + case 1'1 + assign $0\libresocsim_dataw_start[0:0] 1'1 + assign $0\builder_sdphy_fsm_next_state[2:0] 3'100 + case + end + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case 3'100 + assign $0\libresocsim_dataw_pads_out_payload_clk[0:0] 1'1 + attribute \src "build/ls180/gateware/ls180.v:4451.4-4456.7" + switch \libresocsim_dataw_pads_out_ready + attribute \src "build/ls180/gateware/ls180.v:4451.8-4451.40" + case 1'1 + attribute \src "build/ls180/gateware/ls180.v:4452.5-4455.8" + switch \libresocsim_dataw_pads_in_payload_data_i [0] + attribute \src "build/ls180/gateware/ls180.v:4452.9-4452.52" + case 1'1 + assign $0\libresocsim_dataw_sink_ready[0:0] 1'1 + assign $0\builder_sdphy_fsm_next_state[2:0] 3'000 + case + end + case + end + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case + assign $0\libresocsim_dataw_count_sdphy_fsm_next_value[7:0] 8'00000000 + assign $0\libresocsim_dataw_count_sdphy_fsm_next_value_ce[0:0] 1'1 + attribute \src "build/ls180/gateware/ls180.v:4461.4-4463.7" + switch $and$build/ls180/gateware/ls180.v:4461$669_Y + attribute \src "build/ls180/gateware/ls180.v:4461.8-4461.73" + case 1'1 + assign $0\builder_sdphy_fsm_next_state[2:0] 3'001 + case + end + end + sync always + update \libresocsim_dataw_pads_out_payload_clk $0\libresocsim_dataw_pads_out_payload_clk[0:0] + update \libresocsim_dataw_pads_out_payload_data_o $0\libresocsim_dataw_pads_out_payload_data_o[3:0] + update \libresocsim_dataw_pads_out_payload_data_oe $0\libresocsim_dataw_pads_out_payload_data_oe[0:0] + update \libresocsim_dataw_sink_ready $0\libresocsim_dataw_sink_ready[0:0] + update \libresocsim_dataw_stop $0\libresocsim_dataw_stop[0:0] + update \libresocsim_dataw_start $0\libresocsim_dataw_start[0:0] + update \builder_sdphy_fsm_next_state $0\builder_sdphy_fsm_next_state[2:0] + update \libresocsim_dataw_count_sdphy_fsm_next_value $0\libresocsim_dataw_count_sdphy_fsm_next_value[7:0] + update \libresocsim_dataw_count_sdphy_fsm_next_value_ce $0\libresocsim_dataw_count_sdphy_fsm_next_value_ce[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:441.5-441.39" + process $proc$build/ls180/gateware/ls180.v:441$2714 + assign { } { } + assign $1\main_sdram_dfi_p0_wrdata_en[0:0] 1'0 + sync always + sync init + update \main_sdram_dfi_p0_wrdata_en $1\main_sdram_dfi_p0_wrdata_en[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:443.5-443.39" + process $proc$build/ls180/gateware/ls180.v:443$2715 + assign { } { } + assign $1\main_sdram_dfi_p0_rddata_en[0:0] 1'0 + sync always + sync init + update \main_sdram_dfi_p0_rddata_en $1\main_sdram_dfi_p0_rddata_en[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:446.5-446.32" + process $proc$build/ls180/gateware/ls180.v:446$2716 + assign { } { } + assign $1\main_sdram_cmd_valid[0:0] 1'0 + sync always + sync init + update \main_sdram_cmd_valid $1\main_sdram_cmd_valid[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:447.5-447.32" + process $proc$build/ls180/gateware/ls180.v:447$2717 + assign { } { } + assign $1\main_sdram_cmd_ready[0:0] 1'0 + sync always + sync init + update \main_sdram_cmd_ready $1\main_sdram_cmd_ready[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:448.5-448.31" + process $proc$build/ls180/gateware/ls180.v:448$2718 + assign { } { } + assign $1\main_sdram_cmd_last[0:0] 1'0 + sync always + sync init + update \main_sdram_cmd_last $1\main_sdram_cmd_last[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:449.12-449.44" + process $proc$build/ls180/gateware/ls180.v:449$2719 + assign { } { } + assign $1\main_sdram_cmd_payload_a[12:0] 13'0000000000000 + sync always + sync init + update \main_sdram_cmd_payload_a $1\main_sdram_cmd_payload_a[12:0] + end + attribute \src "build/ls180/gateware/ls180.v:450.11-450.43" + process $proc$build/ls180/gateware/ls180.v:450$2720 + assign { } { } + assign $1\main_sdram_cmd_payload_ba[1:0] 2'00 + sync always + sync init + update \main_sdram_cmd_payload_ba $1\main_sdram_cmd_payload_ba[1:0] + end + attribute \src "build/ls180/gateware/ls180.v:4500.1-4601.4" + process $proc$build/ls180/gateware/ls180.v:4500$677 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\libresocsim_datar_count_sdphy_sdphydatar_next_value_ce0[0:0] 1'0 + assign $0\libresocsim_datar_stop[0:0] 1'0 + assign $0\libresocsim_datar_timeout_sdphy_sdphydatar_next_value1[31:0] 0 + assign $0\libresocsim_datar_timeout_sdphy_sdphydatar_next_value_ce1[0:0] 1'0 + assign $0\libresocsim_datar_sink_ready[0:0] 1'0 + assign $0\libresocsim_datar_source_payload_status[2:0] 3'000 + assign $0\libresocsim_datar_datar_reset_sdphy_sdphydatar_next_value2[0:0] 1'0 + assign $0\libresocsim_datar_datar_reset_sdphy_sdphydatar_next_value_ce2[0:0] 1'0 + assign $0\libresocsim_datar_source_payload_data[7:0] 8'00000000 + assign $0\libresocsim_datar_source_valid[0:0] 1'0 + assign $0\libresocsim_datar_source_last[0:0] 1'0 + assign $0\libresocsim_datar_pads_out_payload_clk[0:0] 1'0 + assign $0\libresocsim_datar_datar_source_source_ready0[0:0] 1'0 + assign { } { } + assign $0\libresocsim_datar_count_sdphy_sdphydatar_next_value0[9:0] 10'0000000000 + assign $0\builder_sdphy_sdphydatar_next_state[2:0] \builder_sdphy_sdphydatar_state + attribute \src "build/ls180/gateware/ls180.v:4517.2-4600.9" + switch \builder_sdphy_sdphydatar_state + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case 3'001 + assign $0\libresocsim_datar_pads_out_payload_clk[0:0] 1'1 + assign $0\libresocsim_datar_datar_reset_sdphy_sdphydatar_next_value2[0:0] 1'0 + assign $0\libresocsim_datar_datar_reset_sdphy_sdphydatar_next_value_ce2[0:0] 1'1 + assign { } { } + assign { } { } + assign $0\libresocsim_datar_timeout_sdphy_sdphydatar_next_value1[31:0] $sub$build/ls180/gateware/ls180.v:4527$679_Y + assign $0\libresocsim_datar_timeout_sdphy_sdphydatar_next_value_ce1[0:0] 1'1 + attribute \src "build/ls180/gateware/ls180.v:4524.4-4526.7" + switch \libresocsim_datar_datar_source_source_valid0 + attribute \src "build/ls180/gateware/ls180.v:4524.8-4524.52" + case 1'1 + assign $0\builder_sdphy_sdphydatar_next_state[2:0] 3'010 + case + end + attribute \src "build/ls180/gateware/ls180.v:4529.4-4532.7" + switch $eq$build/ls180/gateware/ls180.v:4529$680_Y + attribute \src "build/ls180/gateware/ls180.v:4529.8-4529.43" + case 1'1 + assign $0\libresocsim_datar_sink_ready[0:0] 1'1 + assign $0\builder_sdphy_sdphydatar_next_state[2:0] 3'100 + case + end + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case 3'010 + assign $0\libresocsim_datar_pads_out_payload_clk[0:0] 1'1 + assign $0\libresocsim_datar_source_valid[0:0] \libresocsim_datar_datar_source_source_valid0 + assign $0\libresocsim_datar_source_payload_status[2:0] 3'000 + assign $0\libresocsim_datar_source_last[0:0] $eq$build/ls180/gateware/ls180.v:4538$683_Y + assign $0\libresocsim_datar_source_payload_data[7:0] \libresocsim_datar_datar_source_source_payload_data0 + assign $0\libresocsim_datar_timeout_sdphy_sdphydatar_next_value1[31:0] $sub$build/ls180/gateware/ls180.v:4559$685_Y + assign $0\libresocsim_datar_timeout_sdphy_sdphydatar_next_value_ce1[0:0] 1'1 + attribute \src "build/ls180/gateware/ls180.v:4540.4-4558.7" + switch \libresocsim_datar_source_valid + attribute \src "build/ls180/gateware/ls180.v:4540.8-4540.38" + case 1'1 + attribute \src "build/ls180/gateware/ls180.v:4541.5-4557.8" + switch \libresocsim_datar_source_ready + attribute \src "build/ls180/gateware/ls180.v:4541.9-4541.39" + case 1'1 + assign $0\libresocsim_datar_datar_source_source_ready0[0:0] 1'1 + assign $0\libresocsim_datar_count_sdphy_sdphydatar_next_value0[9:0] $add$build/ls180/gateware/ls180.v:4543$684_Y + assign $0\libresocsim_datar_count_sdphy_sdphydatar_next_value_ce0[0:0] 1'1 + attribute \src "build/ls180/gateware/ls180.v:4545.6-4554.9" + switch \libresocsim_datar_source_last + attribute \src "build/ls180/gateware/ls180.v:4545.10-4545.39" + case 1'1 + assign $0\libresocsim_datar_sink_ready[0:0] 1'1 + attribute \src "build/ls180/gateware/ls180.v:4547.7-4553.10" + switch \libresocsim_datar_sink_last + attribute \src "build/ls180/gateware/ls180.v:4547.11-4547.38" + case 1'1 + assign $0\libresocsim_datar_count_sdphy_sdphydatar_next_value0[9:0] 10'0000000000 + assign $0\libresocsim_datar_count_sdphy_sdphydatar_next_value_ce0[0:0] 1'1 + assign $0\builder_sdphy_sdphydatar_next_state[2:0] 3'011 + attribute \src "build/ls180/gateware/ls180.v:4551.11-4551.15" + case + assign $0\builder_sdphy_sdphydatar_next_state[2:0] 3'000 + end + case + end + attribute \src "build/ls180/gateware/ls180.v:4555.9-4555.13" + case + assign $0\libresocsim_datar_stop[0:0] 1'1 + end + case + end + attribute \src "build/ls180/gateware/ls180.v:4561.4-4564.7" + switch $eq$build/ls180/gateware/ls180.v:4561$686_Y + attribute \src "build/ls180/gateware/ls180.v:4561.8-4561.43" + case 1'1 + assign $0\libresocsim_datar_sink_ready[0:0] 1'1 + assign $0\builder_sdphy_sdphydatar_next_state[2:0] 3'100 + case + end + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case 3'011 + assign $0\libresocsim_datar_pads_out_payload_clk[0:0] 1'1 + attribute \src "build/ls180/gateware/ls180.v:4568.4-4574.7" + switch \libresocsim_datar_pads_out_ready + attribute \src "build/ls180/gateware/ls180.v:4568.8-4568.40" + case 1'1 + assign $0\libresocsim_datar_count_sdphy_sdphydatar_next_value0[9:0] $add$build/ls180/gateware/ls180.v:4569$687_Y + assign $0\libresocsim_datar_count_sdphy_sdphydatar_next_value_ce0[0:0] 1'1 + attribute \src "build/ls180/gateware/ls180.v:4571.5-4573.8" + switch $eq$build/ls180/gateware/ls180.v:4571$688_Y + attribute \src "build/ls180/gateware/ls180.v:4571.9-4571.43" + case 1'1 + assign $0\builder_sdphy_sdphydatar_next_state[2:0] 3'000 + case + end + case + end + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case 3'100 + assign $0\libresocsim_datar_source_valid[0:0] 1'1 + assign $0\libresocsim_datar_source_payload_status[2:0] 3'001 + assign $0\libresocsim_datar_source_last[0:0] 1'1 + attribute \src "build/ls180/gateware/ls180.v:4580.4-4582.7" + switch $and$build/ls180/gateware/ls180.v:4580$689_Y + attribute \src "build/ls180/gateware/ls180.v:4580.8-4580.73" + case 1'1 + assign $0\builder_sdphy_sdphydatar_next_state[2:0] 3'000 + case + end + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case + assign $0\libresocsim_datar_count_sdphy_sdphydatar_next_value0[9:0] 10'0000000000 + assign $0\libresocsim_datar_count_sdphy_sdphydatar_next_value_ce0[0:0] 1'1 + attribute \src "build/ls180/gateware/ls180.v:4587.4-4598.7" + switch $and$build/ls180/gateware/ls180.v:4587$690_Y + attribute \src "build/ls180/gateware/ls180.v:4587.8-4587.73" + case 1'1 + assign $0\libresocsim_datar_pads_out_payload_clk[0:0] 1'1 + attribute \src "build/ls180/gateware/ls180.v:4589.5-4597.8" + switch \libresocsim_datar_pads_out_ready + attribute \src "build/ls180/gateware/ls180.v:4589.9-4589.41" + case 1'1 + assign $0\libresocsim_datar_timeout_sdphy_sdphydatar_next_value1[31:0] 500000 + assign $0\libresocsim_datar_timeout_sdphy_sdphydatar_next_value_ce1[0:0] 1'1 + assign $0\libresocsim_datar_count_sdphy_sdphydatar_next_value0[9:0] 10'0000000000 + assign $0\libresocsim_datar_count_sdphy_sdphydatar_next_value_ce0[0:0] 1'1 + assign $0\libresocsim_datar_datar_reset_sdphy_sdphydatar_next_value2[0:0] 1'1 + assign $0\libresocsim_datar_datar_reset_sdphy_sdphydatar_next_value_ce2[0:0] 1'1 + assign $0\builder_sdphy_sdphydatar_next_state[2:0] 3'001 + case + end + case + end + end + sync always + update \libresocsim_datar_pads_out_payload_clk $0\libresocsim_datar_pads_out_payload_clk[0:0] + update \libresocsim_datar_sink_ready $0\libresocsim_datar_sink_ready[0:0] + update \libresocsim_datar_source_valid $0\libresocsim_datar_source_valid[0:0] + update \libresocsim_datar_source_last $0\libresocsim_datar_source_last[0:0] + update \libresocsim_datar_source_payload_data $0\libresocsim_datar_source_payload_data[7:0] + update \libresocsim_datar_source_payload_status $0\libresocsim_datar_source_payload_status[2:0] + update \libresocsim_datar_stop $0\libresocsim_datar_stop[0:0] + update \libresocsim_datar_datar_source_source_ready0 $0\libresocsim_datar_datar_source_source_ready0[0:0] + update \builder_sdphy_sdphydatar_next_state $0\builder_sdphy_sdphydatar_next_state[2:0] + update \libresocsim_datar_count_sdphy_sdphydatar_next_value0 $0\libresocsim_datar_count_sdphy_sdphydatar_next_value0[9:0] + update \libresocsim_datar_count_sdphy_sdphydatar_next_value_ce0 $0\libresocsim_datar_count_sdphy_sdphydatar_next_value_ce0[0:0] + update \libresocsim_datar_timeout_sdphy_sdphydatar_next_value1 $0\libresocsim_datar_timeout_sdphy_sdphydatar_next_value1[31:0] + update \libresocsim_datar_timeout_sdphy_sdphydatar_next_value_ce1 $0\libresocsim_datar_timeout_sdphy_sdphydatar_next_value_ce1[0:0] + update \libresocsim_datar_datar_reset_sdphy_sdphydatar_next_value2 $0\libresocsim_datar_datar_reset_sdphy_sdphydatar_next_value2[0:0] + update \libresocsim_datar_datar_reset_sdphy_sdphydatar_next_value_ce2 $0\libresocsim_datar_datar_reset_sdphy_sdphydatar_next_value_ce2[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:451.5-451.38" + process $proc$build/ls180/gateware/ls180.v:451$2721 + assign { } { } + assign $1\main_sdram_cmd_payload_cas[0:0] 1'0 + sync always + sync init + update \main_sdram_cmd_payload_cas $1\main_sdram_cmd_payload_cas[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:452.5-452.38" + process $proc$build/ls180/gateware/ls180.v:452$2722 + assign { } { } + assign $1\main_sdram_cmd_payload_ras[0:0] 1'0 + sync always + sync init + update \main_sdram_cmd_payload_ras $1\main_sdram_cmd_payload_ras[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:453.5-453.37" + process $proc$build/ls180/gateware/ls180.v:453$2723 + assign { } { } + assign $1\main_sdram_cmd_payload_we[0:0] 1'0 + sync always + sync init + update \main_sdram_cmd_payload_we $1\main_sdram_cmd_payload_we[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:454.5-454.42" + process $proc$build/ls180/gateware/ls180.v:454$2724 + assign { } { } + assign $0\main_sdram_cmd_payload_is_read[0:0] 1'0 + sync always + update \main_sdram_cmd_payload_is_read $0\main_sdram_cmd_payload_is_read[0:0] + sync init + end + attribute \src "build/ls180/gateware/ls180.v:455.5-455.43" + process $proc$build/ls180/gateware/ls180.v:455$2725 + assign { } { } + assign $0\main_sdram_cmd_payload_is_write[0:0] 1'0 + sync always + update \main_sdram_cmd_payload_is_write $0\main_sdram_cmd_payload_is_write[0:0] + sync init + end + attribute \src "build/ls180/gateware/ls180.v:461.11-461.44" + process $proc$build/ls180/gateware/ls180.v:461$2726 + assign { } { } + assign $1\main_sdram_timer_count1[9:0] 10'1100001101 + sync always + sync init + update \main_sdram_timer_count1 $1\main_sdram_timer_count1[9:0] + end + attribute \src "build/ls180/gateware/ls180.v:463.5-463.38" + process $proc$build/ls180/gateware/ls180.v:463$2727 + assign { } { } + assign $1\main_sdram_postponer_req_o[0:0] 1'0 + sync always + sync init + update \main_sdram_postponer_req_o $1\main_sdram_postponer_req_o[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:464.5-464.38" + process $proc$build/ls180/gateware/ls180.v:464$2728 + assign { } { } + assign $1\main_sdram_postponer_count[0:0] 1'0 + sync always + sync init + update \main_sdram_postponer_count $1\main_sdram_postponer_count[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:465.5-465.39" + process $proc$build/ls180/gateware/ls180.v:465$2729 + assign { } { } + assign $1\main_sdram_sequencer_start0[0:0] 1'0 + sync always + sync init + update \main_sdram_sequencer_start0 $1\main_sdram_sequencer_start0[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:4659.1-4666.4" + process $proc$build/ls180/gateware/ls180.v:4659$812 + assign { } { } + assign $0\libresocsim_sdcore_crc7_inserter_crc[6:0] 7'0000000 + attribute \src "build/ls180/gateware/ls180.v:4661.2-4665.5" + switch \libresocsim_sdcore_crc7_inserter_enable + attribute \src "build/ls180/gateware/ls180.v:4661.6-4661.45" + case 1'1 + assign $0\libresocsim_sdcore_crc7_inserter_crc[6:0] \libresocsim_sdcore_crc7_inserter_crcreg40 + attribute \src "build/ls180/gateware/ls180.v:4663.6-4663.10" + case + assign $0\libresocsim_sdcore_crc7_inserter_crc[6:0] \libresocsim_sdcore_crc7_inserter_crcreg0 + end + sync always + update \libresocsim_sdcore_crc7_inserter_crc $0\libresocsim_sdcore_crc7_inserter_crc[6:0] + end + attribute \src "build/ls180/gateware/ls180.v:468.5-468.38" + process $proc$build/ls180/gateware/ls180.v:468$2730 + assign { } { } + assign $1\main_sdram_sequencer_done1[0:0] 1'0 + sync always + sync init + update \main_sdram_sequencer_done1 $1\main_sdram_sequencer_done1[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:4681.1-4688.4" + process $proc$build/ls180/gateware/ls180.v:4681$835 + assign { } { } + assign $0\libresocsim_sdcore_crc16_inserter_crc0_crc[15:0] 16'0000000000000000 + attribute \src "build/ls180/gateware/ls180.v:4683.2-4687.5" + switch \libresocsim_sdcore_crc16_inserter_crc0_enable + attribute \src "build/ls180/gateware/ls180.v:4683.6-4683.51" + case 1'1 + assign $0\libresocsim_sdcore_crc16_inserter_crc0_crc[15:0] \libresocsim_sdcore_crc16_inserter_crc0_crcreg2 + attribute \src "build/ls180/gateware/ls180.v:4685.6-4685.10" + case + assign $0\libresocsim_sdcore_crc16_inserter_crc0_crc[15:0] \libresocsim_sdcore_crc16_inserter_crc0_crcreg0 + end + sync always + update \libresocsim_sdcore_crc16_inserter_crc0_crc $0\libresocsim_sdcore_crc16_inserter_crc0_crc[15:0] + end + attribute \src "build/ls180/gateware/ls180.v:469.11-469.46" + process $proc$build/ls180/gateware/ls180.v:469$2731 + assign { } { } + assign $1\main_sdram_sequencer_counter[3:0] 4'0000 + sync always + sync init + update \main_sdram_sequencer_counter $1\main_sdram_sequencer_counter[3:0] + end + attribute \src "build/ls180/gateware/ls180.v:4691.1-4698.4" + process $proc$build/ls180/gateware/ls180.v:4691$846 + assign { } { } + assign $0\libresocsim_sdcore_crc16_inserter_crc1_crc[15:0] 16'0000000000000000 + attribute \src "build/ls180/gateware/ls180.v:4693.2-4697.5" + switch \libresocsim_sdcore_crc16_inserter_crc1_enable + attribute \src "build/ls180/gateware/ls180.v:4693.6-4693.51" + case 1'1 + assign $0\libresocsim_sdcore_crc16_inserter_crc1_crc[15:0] \libresocsim_sdcore_crc16_inserter_crc1_crcreg2 + attribute \src "build/ls180/gateware/ls180.v:4695.6-4695.10" + case + assign $0\libresocsim_sdcore_crc16_inserter_crc1_crc[15:0] \libresocsim_sdcore_crc16_inserter_crc1_crcreg0 + end + sync always + update \libresocsim_sdcore_crc16_inserter_crc1_crc $0\libresocsim_sdcore_crc16_inserter_crc1_crc[15:0] + end + attribute \src "build/ls180/gateware/ls180.v:470.5-470.38" + process $proc$build/ls180/gateware/ls180.v:470$2732 + assign { } { } + assign $1\main_sdram_sequencer_count[0:0] 1'0 + sync always + sync init + update \main_sdram_sequencer_count $1\main_sdram_sequencer_count[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:4701.1-4708.4" + process $proc$build/ls180/gateware/ls180.v:4701$857 + assign { } { } + assign $0\libresocsim_sdcore_crc16_inserter_crc2_crc[15:0] 16'0000000000000000 + attribute \src "build/ls180/gateware/ls180.v:4703.2-4707.5" + switch \libresocsim_sdcore_crc16_inserter_crc2_enable + attribute \src "build/ls180/gateware/ls180.v:4703.6-4703.51" + case 1'1 + assign $0\libresocsim_sdcore_crc16_inserter_crc2_crc[15:0] \libresocsim_sdcore_crc16_inserter_crc2_crcreg2 + attribute \src "build/ls180/gateware/ls180.v:4705.6-4705.10" + case + assign $0\libresocsim_sdcore_crc16_inserter_crc2_crc[15:0] \libresocsim_sdcore_crc16_inserter_crc2_crcreg0 + end + sync always + update \libresocsim_sdcore_crc16_inserter_crc2_crc $0\libresocsim_sdcore_crc16_inserter_crc2_crc[15:0] + end + attribute \src "build/ls180/gateware/ls180.v:4711.1-4718.4" + process $proc$build/ls180/gateware/ls180.v:4711$868 + assign { } { } + assign $0\libresocsim_sdcore_crc16_inserter_crc3_crc[15:0] 16'0000000000000000 + attribute \src "build/ls180/gateware/ls180.v:4713.2-4717.5" + switch \libresocsim_sdcore_crc16_inserter_crc3_enable + attribute \src "build/ls180/gateware/ls180.v:4713.6-4713.51" + case 1'1 + assign $0\libresocsim_sdcore_crc16_inserter_crc3_crc[15:0] \libresocsim_sdcore_crc16_inserter_crc3_crcreg2 + attribute \src "build/ls180/gateware/ls180.v:4715.6-4715.10" + case + assign $0\libresocsim_sdcore_crc16_inserter_crc3_crc[15:0] \libresocsim_sdcore_crc16_inserter_crc3_crcreg0 + end + sync always + update \libresocsim_sdcore_crc16_inserter_crc3_crc $0\libresocsim_sdcore_crc16_inserter_crc3_crc[15:0] + end + attribute \src "build/ls180/gateware/ls180.v:4719.1-4798.4" + process $proc$build/ls180/gateware/ls180.v:4719$869 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\libresocsim_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value2[15:0] 16'0000000000000000 + assign $0\libresocsim_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value_ce2[0:0] 1'0 + assign $0\libresocsim_sdcore_crc16_inserter_source_valid[0:0] 1'0 + assign $0\libresocsim_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value3[15:0] 16'0000000000000000 + assign $0\libresocsim_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value_ce3[0:0] 1'0 + assign $0\libresocsim_sdcore_crc16_inserter_source_last[0:0] 1'0 + assign $0\libresocsim_sdcore_crc16_inserter_source_payload_data[7:0] 8'00000000 + assign $0\libresocsim_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value4[2:0] 3'000 + assign $0\libresocsim_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value_ce4[0:0] 1'0 + assign { } { } + assign $0\libresocsim_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value1[15:0] 16'0000000000000000 + assign $0\libresocsim_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value0[15:0] 16'0000000000000000 + assign $0\libresocsim_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value_ce0[0:0] 1'0 + assign $0\libresocsim_sdcore_crc16_inserter_sink_ready[0:0] 1'0 + assign $0\libresocsim_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value_ce1[0:0] 1'0 + assign $0\builder_sdcore_crcupstreaminserter_next_state[0:0] \builder_sdcore_crcupstreaminserter_state + attribute \src "build/ls180/gateware/ls180.v:4736.2-4797.9" + switch \builder_sdcore_crcupstreaminserter_state + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case 1'1 + assign $0\libresocsim_sdcore_crc16_inserter_sink_ready[0:0] 1'0 + assign $0\libresocsim_sdcore_crc16_inserter_source_valid[0:0] 1'1 + attribute \src "build/ls180/gateware/ls180.v:4740.4-4742.7" + switch $eq$build/ls180/gateware/ls180.v:4740$870_Y + attribute \src "build/ls180/gateware/ls180.v:4740.8-4740.55" + case 1'1 + assign $0\libresocsim_sdcore_crc16_inserter_source_last[0:0] 1'1 + case + end + attribute \src "build/ls180/gateware/ls180.v:4743.4-4768.11" + switch \libresocsim_sdcore_crc16_inserter_cnt + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case 3'000 + assign $0\libresocsim_sdcore_crc16_inserter_source_payload_data[7:0] { \libresocsim_sdcore_crc16_inserter_crctmp3 [15] \libresocsim_sdcore_crc16_inserter_crctmp2 [15] \libresocsim_sdcore_crc16_inserter_crctmp1 [15] \libresocsim_sdcore_crc16_inserter_crctmp0 [15] \libresocsim_sdcore_crc16_inserter_crctmp3 [14] \libresocsim_sdcore_crc16_inserter_crctmp2 [14] \libresocsim_sdcore_crc16_inserter_crctmp1 [14] \libresocsim_sdcore_crc16_inserter_crctmp0 [14] } + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case 3'001 + assign $0\libresocsim_sdcore_crc16_inserter_source_payload_data[7:0] { \libresocsim_sdcore_crc16_inserter_crctmp3 [13] \libresocsim_sdcore_crc16_inserter_crctmp2 [13] \libresocsim_sdcore_crc16_inserter_crctmp1 [13] \libresocsim_sdcore_crc16_inserter_crctmp0 [13] \libresocsim_sdcore_crc16_inserter_crctmp3 [12] \libresocsim_sdcore_crc16_inserter_crctmp2 [12] \libresocsim_sdcore_crc16_inserter_crctmp1 [12] \libresocsim_sdcore_crc16_inserter_crctmp0 [12] } + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case 3'010 + assign $0\libresocsim_sdcore_crc16_inserter_source_payload_data[7:0] { \libresocsim_sdcore_crc16_inserter_crctmp3 [11] \libresocsim_sdcore_crc16_inserter_crctmp2 [11] \libresocsim_sdcore_crc16_inserter_crctmp1 [11] \libresocsim_sdcore_crc16_inserter_crctmp0 [11] \libresocsim_sdcore_crc16_inserter_crctmp3 [10] \libresocsim_sdcore_crc16_inserter_crctmp2 [10] \libresocsim_sdcore_crc16_inserter_crctmp1 [10] \libresocsim_sdcore_crc16_inserter_crctmp0 [10] } + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case 3'011 + assign $0\libresocsim_sdcore_crc16_inserter_source_payload_data[7:0] { \libresocsim_sdcore_crc16_inserter_crctmp3 [9] \libresocsim_sdcore_crc16_inserter_crctmp2 [9] \libresocsim_sdcore_crc16_inserter_crctmp1 [9] \libresocsim_sdcore_crc16_inserter_crctmp0 [9] \libresocsim_sdcore_crc16_inserter_crctmp3 [8] \libresocsim_sdcore_crc16_inserter_crctmp2 [8] \libresocsim_sdcore_crc16_inserter_crctmp1 [8] \libresocsim_sdcore_crc16_inserter_crctmp0 [8] } + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case 3'100 + assign $0\libresocsim_sdcore_crc16_inserter_source_payload_data[7:0] { \libresocsim_sdcore_crc16_inserter_crctmp3 [7] \libresocsim_sdcore_crc16_inserter_crctmp2 [7] \libresocsim_sdcore_crc16_inserter_crctmp1 [7] \libresocsim_sdcore_crc16_inserter_crctmp0 [7] \libresocsim_sdcore_crc16_inserter_crctmp3 [6] \libresocsim_sdcore_crc16_inserter_crctmp2 [6] \libresocsim_sdcore_crc16_inserter_crctmp1 [6] \libresocsim_sdcore_crc16_inserter_crctmp0 [6] } + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case 3'101 + assign $0\libresocsim_sdcore_crc16_inserter_source_payload_data[7:0] { \libresocsim_sdcore_crc16_inserter_crctmp3 [5] \libresocsim_sdcore_crc16_inserter_crctmp2 [5] \libresocsim_sdcore_crc16_inserter_crctmp1 [5] \libresocsim_sdcore_crc16_inserter_crctmp0 [5] \libresocsim_sdcore_crc16_inserter_crctmp3 [4] \libresocsim_sdcore_crc16_inserter_crctmp2 [4] \libresocsim_sdcore_crc16_inserter_crctmp1 [4] \libresocsim_sdcore_crc16_inserter_crctmp0 [4] } + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case 3'110 + assign $0\libresocsim_sdcore_crc16_inserter_source_payload_data[7:0] { \libresocsim_sdcore_crc16_inserter_crctmp3 [3] \libresocsim_sdcore_crc16_inserter_crctmp2 [3] \libresocsim_sdcore_crc16_inserter_crctmp1 [3] \libresocsim_sdcore_crc16_inserter_crctmp0 [3] \libresocsim_sdcore_crc16_inserter_crctmp3 [2] \libresocsim_sdcore_crc16_inserter_crctmp2 [2] \libresocsim_sdcore_crc16_inserter_crctmp1 [2] \libresocsim_sdcore_crc16_inserter_crctmp0 [2] } + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case 3'111 + assign $0\libresocsim_sdcore_crc16_inserter_source_payload_data[7:0] { \libresocsim_sdcore_crc16_inserter_crctmp3 [1] \libresocsim_sdcore_crc16_inserter_crctmp2 [1] \libresocsim_sdcore_crc16_inserter_crctmp1 [1] \libresocsim_sdcore_crc16_inserter_crctmp0 [1] \libresocsim_sdcore_crc16_inserter_crctmp3 [0] \libresocsim_sdcore_crc16_inserter_crctmp2 [0] \libresocsim_sdcore_crc16_inserter_crctmp1 [0] \libresocsim_sdcore_crc16_inserter_crctmp0 [0] } + case + end + attribute \src "build/ls180/gateware/ls180.v:4769.4-4776.7" + switch \libresocsim_sdcore_crc16_inserter_source_ready + attribute \src "build/ls180/gateware/ls180.v:4769.8-4769.54" + case 1'1 + attribute \src "build/ls180/gateware/ls180.v:4770.5-4775.8" + switch $eq$build/ls180/gateware/ls180.v:4770$871_Y + attribute \src "build/ls180/gateware/ls180.v:4770.9-4770.56" + case 1'1 + assign $0\builder_sdcore_crcupstreaminserter_next_state[0:0] 1'0 + attribute \src "build/ls180/gateware/ls180.v:4772.9-4772.13" + case + assign $0\libresocsim_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value4[2:0] $add$build/ls180/gateware/ls180.v:4773$872_Y + assign $0\libresocsim_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value_ce4[0:0] 1'1 + end + case + end + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case + assign $0\libresocsim_sdcore_crc16_inserter_source_payload_data[7:0] \libresocsim_sdcore_crc16_inserter_sink_payload_data + assign $0\libresocsim_sdcore_crc16_inserter_source_valid[0:0] \libresocsim_sdcore_crc16_inserter_sink_valid + assign $0\libresocsim_sdcore_crc16_inserter_sink_ready[0:0] \libresocsim_sdcore_crc16_inserter_source_ready + assign $0\libresocsim_sdcore_crc16_inserter_source_last[0:0] 1'0 + assign $0\libresocsim_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value0[15:0] \libresocsim_sdcore_crc16_inserter_crc0_crc + assign $0\libresocsim_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value_ce0[0:0] 1'1 + assign $0\libresocsim_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value1[15:0] \libresocsim_sdcore_crc16_inserter_crc1_crc + assign $0\libresocsim_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value_ce1[0:0] 1'1 + assign $0\libresocsim_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value2[15:0] \libresocsim_sdcore_crc16_inserter_crc2_crc + assign $0\libresocsim_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value_ce2[0:0] 1'1 + assign $0\libresocsim_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value3[15:0] \libresocsim_sdcore_crc16_inserter_crc3_crc + assign $0\libresocsim_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value_ce3[0:0] 1'1 + attribute \src "build/ls180/gateware/ls180.v:4791.4-4795.7" + switch $and$build/ls180/gateware/ls180.v:4791$874_Y + attribute \src "build/ls180/gateware/ls180.v:4791.8-4791.149" + case 1'1 + assign $0\builder_sdcore_crcupstreaminserter_next_state[0:0] 1'1 + assign $0\libresocsim_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value4[2:0] 3'000 + assign $0\libresocsim_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value_ce4[0:0] 1'1 + case + end + end + sync always + update \libresocsim_sdcore_crc16_inserter_sink_ready $0\libresocsim_sdcore_crc16_inserter_sink_ready[0:0] + update \libresocsim_sdcore_crc16_inserter_source_valid $0\libresocsim_sdcore_crc16_inserter_source_valid[0:0] + update \libresocsim_sdcore_crc16_inserter_source_last $0\libresocsim_sdcore_crc16_inserter_source_last[0:0] + update \libresocsim_sdcore_crc16_inserter_source_payload_data $0\libresocsim_sdcore_crc16_inserter_source_payload_data[7:0] + update \builder_sdcore_crcupstreaminserter_next_state $0\builder_sdcore_crcupstreaminserter_next_state[0:0] + update \libresocsim_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value0 $0\libresocsim_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value0[15:0] + update \libresocsim_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value_ce0 $0\libresocsim_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value_ce0[0:0] + update \libresocsim_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value1 $0\libresocsim_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value1[15:0] + update \libresocsim_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value_ce1 $0\libresocsim_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value_ce1[0:0] + update \libresocsim_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value2 $0\libresocsim_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value2[15:0] + update \libresocsim_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value_ce2 $0\libresocsim_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value_ce2[0:0] + update \libresocsim_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value3 $0\libresocsim_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value3[15:0] + update \libresocsim_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value_ce3 $0\libresocsim_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value_ce3[0:0] + update \libresocsim_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value4 $0\libresocsim_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value4[2:0] + update \libresocsim_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value_ce4 $0\libresocsim_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value_ce4[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:476.5-476.51" + process $proc$build/ls180/gateware/ls180.v:476$2733 + assign { } { } + assign $1\main_sdram_bankmachine0_req_wdata_ready[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine0_req_wdata_ready $1\main_sdram_bankmachine0_req_wdata_ready[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:477.5-477.51" + process $proc$build/ls180/gateware/ls180.v:477$2734 + assign { } { } + assign $1\main_sdram_bankmachine0_req_rdata_valid[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine0_req_rdata_valid $1\main_sdram_bankmachine0_req_rdata_valid[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:479.5-479.47" + process $proc$build/ls180/gateware/ls180.v:479$2735 + assign { } { } + assign $1\main_sdram_bankmachine0_refresh_gnt[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine0_refresh_gnt $1\main_sdram_bankmachine0_refresh_gnt[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:4799.1-4804.4" + process $proc$build/ls180/gateware/ls180.v:4799$875 + assign { } { } + assign $0\libresocsim_sdcore_crc16_checker_valid[0:0] 1'0 + attribute \src "build/ls180/gateware/ls180.v:4801.2-4803.5" + switch $and$build/ls180/gateware/ls180.v:4801$882_Y + attribute \src "build/ls180/gateware/ls180.v:4801.6-4801.357" + case 1'1 + assign $0\libresocsim_sdcore_crc16_checker_valid[0:0] 1'1 + case + end + sync always + update \libresocsim_sdcore_crc16_checker_valid $0\libresocsim_sdcore_crc16_checker_valid[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:480.5-480.45" + process $proc$build/ls180/gateware/ls180.v:480$2736 + assign { } { } + assign $1\main_sdram_bankmachine0_cmd_valid[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine0_cmd_valid $1\main_sdram_bankmachine0_cmd_valid[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:4807.1-4814.4" + process $proc$build/ls180/gateware/ls180.v:4807$884 + assign { } { } + assign $0\libresocsim_sdcore_crc16_checker_crc0_clr[0:0] 1'0 + attribute \src "build/ls180/gateware/ls180.v:4809.2-4813.5" + switch $eq$build/ls180/gateware/ls180.v:4809$885_Y + attribute \src "build/ls180/gateware/ls180.v:4809.6-4809.52" + case 1'1 + assign $0\libresocsim_sdcore_crc16_checker_crc0_clr[0:0] 1'1 + attribute \src "build/ls180/gateware/ls180.v:4811.6-4811.10" + case + assign $0\libresocsim_sdcore_crc16_checker_crc0_clr[0:0] 1'0 + end + sync always + update \libresocsim_sdcore_crc16_checker_crc0_clr $0\libresocsim_sdcore_crc16_checker_crc0_clr[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:481.5-481.45" + process $proc$build/ls180/gateware/ls180.v:481$2737 + assign { } { } + assign $1\main_sdram_bankmachine0_cmd_ready[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine0_cmd_ready $1\main_sdram_bankmachine0_cmd_ready[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:4817.1-4824.4" + process $proc$build/ls180/gateware/ls180.v:4817$887 + assign { } { } + assign $0\libresocsim_sdcore_crc16_checker_crc1_clr[0:0] 1'0 + attribute \src "build/ls180/gateware/ls180.v:4819.2-4823.5" + switch $eq$build/ls180/gateware/ls180.v:4819$888_Y + attribute \src "build/ls180/gateware/ls180.v:4819.6-4819.52" + case 1'1 + assign $0\libresocsim_sdcore_crc16_checker_crc1_clr[0:0] 1'1 + attribute \src "build/ls180/gateware/ls180.v:4821.6-4821.10" + case + assign $0\libresocsim_sdcore_crc16_checker_crc1_clr[0:0] 1'0 + end + sync always + update \libresocsim_sdcore_crc16_checker_crc1_clr $0\libresocsim_sdcore_crc16_checker_crc1_clr[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:482.12-482.57" + process $proc$build/ls180/gateware/ls180.v:482$2738 + assign { } { } + assign $1\main_sdram_bankmachine0_cmd_payload_a[12:0] 13'0000000000000 + sync always + sync init + update \main_sdram_bankmachine0_cmd_payload_a $1\main_sdram_bankmachine0_cmd_payload_a[12:0] + end + attribute \src "build/ls180/gateware/ls180.v:4827.1-4834.4" + process $proc$build/ls180/gateware/ls180.v:4827$890 + assign { } { } + assign $0\libresocsim_sdcore_crc16_checker_crc2_clr[0:0] 1'0 + attribute \src "build/ls180/gateware/ls180.v:4829.2-4833.5" + switch $eq$build/ls180/gateware/ls180.v:4829$891_Y + attribute \src "build/ls180/gateware/ls180.v:4829.6-4829.52" + case 1'1 + assign $0\libresocsim_sdcore_crc16_checker_crc2_clr[0:0] 1'1 + attribute \src "build/ls180/gateware/ls180.v:4831.6-4831.10" + case + assign $0\libresocsim_sdcore_crc16_checker_crc2_clr[0:0] 1'0 + end + sync always + update \libresocsim_sdcore_crc16_checker_crc2_clr $0\libresocsim_sdcore_crc16_checker_crc2_clr[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:4837.1-4844.4" + process $proc$build/ls180/gateware/ls180.v:4837$893 + assign { } { } + assign $0\libresocsim_sdcore_crc16_checker_crc3_clr[0:0] 1'0 + attribute \src "build/ls180/gateware/ls180.v:4839.2-4843.5" + switch $eq$build/ls180/gateware/ls180.v:4839$894_Y + attribute \src "build/ls180/gateware/ls180.v:4839.6-4839.52" + case 1'1 + assign $0\libresocsim_sdcore_crc16_checker_crc3_clr[0:0] 1'1 + attribute \src "build/ls180/gateware/ls180.v:4841.6-4841.10" + case + assign $0\libresocsim_sdcore_crc16_checker_crc3_clr[0:0] 1'0 + end + sync always + update \libresocsim_sdcore_crc16_checker_crc3_clr $0\libresocsim_sdcore_crc16_checker_crc3_clr[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:484.5-484.51" + process $proc$build/ls180/gateware/ls180.v:484$2739 + assign { } { } + assign $1\main_sdram_bankmachine0_cmd_payload_cas[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine0_cmd_payload_cas $1\main_sdram_bankmachine0_cmd_payload_cas[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:4846.1-4851.4" + process $proc$build/ls180/gateware/ls180.v:4846$895 + assign { } { } + assign $0\libresocsim_sdcore_crc16_checker_source_valid[0:0] 1'0 + attribute \src "build/ls180/gateware/ls180.v:4848.2-4850.5" + switch $and$build/ls180/gateware/ls180.v:4848$897_Y + attribute \src "build/ls180/gateware/ls180.v:4848.6-4848.99" + case 1'1 + assign $0\libresocsim_sdcore_crc16_checker_source_valid[0:0] 1'1 + case + end + sync always + update \libresocsim_sdcore_crc16_checker_source_valid $0\libresocsim_sdcore_crc16_checker_source_valid[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:485.5-485.51" + process $proc$build/ls180/gateware/ls180.v:485$2740 + assign { } { } + assign $1\main_sdram_bankmachine0_cmd_payload_ras[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine0_cmd_payload_ras $1\main_sdram_bankmachine0_cmd_payload_ras[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:4852.1-4859.4" + process $proc$build/ls180/gateware/ls180.v:4852$898 + assign { } { } + assign $0\libresocsim_sdcore_crc16_checker_sink_ready[0:0] 1'0 + attribute \src "build/ls180/gateware/ls180.v:4854.2-4858.5" + switch $lt$build/ls180/gateware/ls180.v:4854$899_Y + attribute \src "build/ls180/gateware/ls180.v:4854.6-4854.51" + case 1'1 + assign $0\libresocsim_sdcore_crc16_checker_sink_ready[0:0] 1'1 + attribute \src "build/ls180/gateware/ls180.v:4856.6-4856.10" + case + assign $0\libresocsim_sdcore_crc16_checker_sink_ready[0:0] \libresocsim_sdcore_crc16_checker_source_ready + end + sync always + update \libresocsim_sdcore_crc16_checker_sink_ready $0\libresocsim_sdcore_crc16_checker_sink_ready[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:486.5-486.50" + process $proc$build/ls180/gateware/ls180.v:486$2741 + assign { } { } + assign $1\main_sdram_bankmachine0_cmd_payload_we[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine0_cmd_payload_we $1\main_sdram_bankmachine0_cmd_payload_we[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:4863.1-4870.4" + process $proc$build/ls180/gateware/ls180.v:4863$910 + assign { } { } + assign $0\libresocsim_sdcore_crc16_checker_crc0_crc[15:0] 16'0000000000000000 + attribute \src "build/ls180/gateware/ls180.v:4865.2-4869.5" + switch \libresocsim_sdcore_crc16_checker_crc0_enable + attribute \src "build/ls180/gateware/ls180.v:4865.6-4865.50" + case 1'1 + assign $0\libresocsim_sdcore_crc16_checker_crc0_crc[15:0] \libresocsim_sdcore_crc16_checker_crc0_crcreg2 + attribute \src "build/ls180/gateware/ls180.v:4867.6-4867.10" + case + assign $0\libresocsim_sdcore_crc16_checker_crc0_crc[15:0] \libresocsim_sdcore_crc16_checker_crc0_crcreg0 + end + sync always + update \libresocsim_sdcore_crc16_checker_crc0_crc $0\libresocsim_sdcore_crc16_checker_crc0_crc[15:0] + end + attribute \src "build/ls180/gateware/ls180.v:487.5-487.54" + process $proc$build/ls180/gateware/ls180.v:487$2742 + assign { } { } + assign $1\main_sdram_bankmachine0_cmd_payload_is_cmd[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine0_cmd_payload_is_cmd $1\main_sdram_bankmachine0_cmd_payload_is_cmd[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:4873.1-4880.4" + process $proc$build/ls180/gateware/ls180.v:4873$921 + assign { } { } + assign $0\libresocsim_sdcore_crc16_checker_crc1_crc[15:0] 16'0000000000000000 + attribute \src "build/ls180/gateware/ls180.v:4875.2-4879.5" + switch \libresocsim_sdcore_crc16_checker_crc1_enable + attribute \src "build/ls180/gateware/ls180.v:4875.6-4875.50" + case 1'1 + assign $0\libresocsim_sdcore_crc16_checker_crc1_crc[15:0] \libresocsim_sdcore_crc16_checker_crc1_crcreg2 + attribute \src "build/ls180/gateware/ls180.v:4877.6-4877.10" + case + assign $0\libresocsim_sdcore_crc16_checker_crc1_crc[15:0] \libresocsim_sdcore_crc16_checker_crc1_crcreg0 + end + sync always + update \libresocsim_sdcore_crc16_checker_crc1_crc $0\libresocsim_sdcore_crc16_checker_crc1_crc[15:0] + end + attribute \src "build/ls180/gateware/ls180.v:488.5-488.55" + process $proc$build/ls180/gateware/ls180.v:488$2743 + assign { } { } + assign $1\main_sdram_bankmachine0_cmd_payload_is_read[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine0_cmd_payload_is_read $1\main_sdram_bankmachine0_cmd_payload_is_read[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:4883.1-4890.4" + process $proc$build/ls180/gateware/ls180.v:4883$932 + assign { } { } + assign $0\libresocsim_sdcore_crc16_checker_crc2_crc[15:0] 16'0000000000000000 + attribute \src "build/ls180/gateware/ls180.v:4885.2-4889.5" + switch \libresocsim_sdcore_crc16_checker_crc2_enable + attribute \src "build/ls180/gateware/ls180.v:4885.6-4885.50" + case 1'1 + assign $0\libresocsim_sdcore_crc16_checker_crc2_crc[15:0] \libresocsim_sdcore_crc16_checker_crc2_crcreg2 + attribute \src "build/ls180/gateware/ls180.v:4887.6-4887.10" + case + assign $0\libresocsim_sdcore_crc16_checker_crc2_crc[15:0] \libresocsim_sdcore_crc16_checker_crc2_crcreg0 + end + sync always + update \libresocsim_sdcore_crc16_checker_crc2_crc $0\libresocsim_sdcore_crc16_checker_crc2_crc[15:0] + end + attribute \src "build/ls180/gateware/ls180.v:489.5-489.56" + process $proc$build/ls180/gateware/ls180.v:489$2744 + assign { } { } + assign $1\main_sdram_bankmachine0_cmd_payload_is_write[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine0_cmd_payload_is_write $1\main_sdram_bankmachine0_cmd_payload_is_write[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:4893.1-4900.4" + process $proc$build/ls180/gateware/ls180.v:4893$943 + assign { } { } + assign $0\libresocsim_sdcore_crc16_checker_crc3_crc[15:0] 16'0000000000000000 + attribute \src "build/ls180/gateware/ls180.v:4895.2-4899.5" + switch \libresocsim_sdcore_crc16_checker_crc3_enable + attribute \src "build/ls180/gateware/ls180.v:4895.6-4895.50" + case 1'1 + assign $0\libresocsim_sdcore_crc16_checker_crc3_crc[15:0] \libresocsim_sdcore_crc16_checker_crc3_crcreg2 + attribute \src "build/ls180/gateware/ls180.v:4897.6-4897.10" + case + assign $0\libresocsim_sdcore_crc16_checker_crc3_crc[15:0] \libresocsim_sdcore_crc16_checker_crc3_crcreg0 + end + sync always + update \libresocsim_sdcore_crc16_checker_crc3_crc $0\libresocsim_sdcore_crc16_checker_crc3_crc[15:0] + end + attribute \src "build/ls180/gateware/ls180.v:490.5-490.50" + process $proc$build/ls180/gateware/ls180.v:490$2745 + assign { } { } + assign $1\main_sdram_bankmachine0_auto_precharge[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine0_auto_precharge $1\main_sdram_bankmachine0_auto_precharge[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:4901.1-5091.4" + process $proc$build/ls180/gateware/ls180.v:4901$944 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\libresocsim_sdcore_crc16_inserter_source_ready[0:0] 1'0 + assign { } { } + assign $0\libresocsim_sdcore_cmd_done_sdcore_fsm_next_value0[0:0] 1'0 + assign $0\libresocsim_dataw_sink_valid[0:0] 1'0 + assign $0\libresocsim_sdcore_cmd_done_sdcore_fsm_next_value_ce0[0:0] 1'0 + assign $0\libresocsim_datar_sink_valid[0:0] 1'0 + assign $0\libresocsim_dataw_sink_first[0:0] 1'0 + assign $0\libresocsim_sdcore_data_done_sdcore_fsm_next_value1[0:0] 1'0 + assign $0\libresocsim_dataw_sink_last[0:0] 1'0 + assign $0\libresocsim_sdcore_data_done_sdcore_fsm_next_value_ce1[0:0] 1'0 + assign $0\libresocsim_dataw_sink_payload_data[7:0] 8'00000000 + assign $0\libresocsim_datar_sink_payload_block_length[9:0] 10'0000000000 + assign $0\libresocsim_cmdr_sink_valid[0:0] 1'0 + assign $0\libresocsim_sdcore_cmd_count_sdcore_fsm_next_value2[2:0] 3'000 + assign $0\libresocsim_datar_source_ready[0:0] 1'0 + assign $0\libresocsim_sdcore_cmd_count_sdcore_fsm_next_value_ce2[0:0] 1'0 + assign $0\libresocsim_datar_sink_last[0:0] 1'0 + assign $0\libresocsim_cmdr_sink_last[0:0] 1'0 + assign $0\libresocsim_sdcore_data_count_sdcore_fsm_next_value3[31:0] 0 + assign $0\libresocsim_cmdr_sink_payload_length[7:0] 8'00000000 + assign $0\libresocsim_sdcore_data_count_sdcore_fsm_next_value_ce3[0:0] 1'0 + assign $0\libresocsim_cmdr_source_ready[0:0] 1'0 + assign $0\libresocsim_sdcore_cmd_error_sdcore_fsm_next_value4[0:0] 1'0 + assign $0\libresocsim_sdcore_cmd_error_sdcore_fsm_next_value_ce4[0:0] 1'0 + assign $0\libresocsim_sdcore_cmd_timeout_sdcore_fsm_next_value5[0:0] 1'0 + assign $0\libresocsim_sdcore_cmd_timeout_sdcore_fsm_next_value_ce5[0:0] 1'0 + assign $0\libresocsim_sdcore_data_error_sdcore_fsm_next_value6[0:0] 1'0 + assign $0\libresocsim_sdcore_data_error_sdcore_fsm_next_value_ce6[0:0] 1'0 + assign $0\libresocsim_sdcore_data_timeout_sdcore_fsm_next_value7[0:0] 1'0 + assign $0\libresocsim_cmdw_sink_valid[0:0] 1'0 + assign $0\libresocsim_sdcore_data_timeout_sdcore_fsm_next_value_ce7[0:0] 1'0 + assign $0\libresocsim_cmdw_sink_last[0:0] 1'0 + assign $0\libresocsim_cmdw_sink_payload_data[7:0] 8'00000000 + assign $0\libresocsim_sdcore_crc16_checker_sink_valid[0:0] 1'0 + assign $0\libresocsim_sdcore_crc16_checker_sink_first[0:0] 1'0 + assign $0\libresocsim_sdcore_crc16_checker_sink_last[0:0] 1'0 + assign $0\libresocsim_sdcore_cmd_response_status_sdcore_fsm_next_value8[127:0] 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign $0\libresocsim_sdcore_crc16_checker_sink_payload_data[7:0] 8'00000000 + assign $0\libresocsim_sdcore_cmd_response_status_sdcore_fsm_next_value_ce8[0:0] 1'0 + assign $0\builder_sdcore_fsm_next_state[2:0] \builder_sdcore_fsm_state + attribute \src "build/ls180/gateware/ls180.v:4942.2-5090.9" + switch \builder_sdcore_fsm_state + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case 3'001 + assign $0\libresocsim_cmdw_sink_valid[0:0] 1'1 + attribute \src "build/ls180/gateware/ls180.v:4945.4-4965.11" + switch \libresocsim_sdcore_cmd_count + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case 3'000 + assign $0\libresocsim_cmdw_sink_payload_data[7:0] { 2'01 \libresocsim_sdcore_cmd_command_storage [13:8] } + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case 3'001 + assign $0\libresocsim_cmdw_sink_payload_data[7:0] \libresocsim_sdcore_cmd_argument_storage [31:24] + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case 3'010 + assign $0\libresocsim_cmdw_sink_payload_data[7:0] \libresocsim_sdcore_cmd_argument_storage [23:16] + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case 3'011 + assign $0\libresocsim_cmdw_sink_payload_data[7:0] \libresocsim_sdcore_cmd_argument_storage [15:8] + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case 3'100 + assign $0\libresocsim_cmdw_sink_payload_data[7:0] \libresocsim_sdcore_cmd_argument_storage [7:0] + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case 3'101 + assign $0\libresocsim_cmdw_sink_payload_data[7:0] { \libresocsim_sdcore_crc7_inserter_crc 1'1 } + assign $0\libresocsim_cmdw_sink_last[0:0] $eq$build/ls180/gateware/ls180.v:4963$945_Y + case + end + attribute \src "build/ls180/gateware/ls180.v:4966.4-4978.7" + switch $and$build/ls180/gateware/ls180.v:4966$946_Y + attribute \src "build/ls180/gateware/ls180.v:4966.8-4966.67" + case 1'1 + assign $0\libresocsim_sdcore_cmd_count_sdcore_fsm_next_value2[2:0] $add$build/ls180/gateware/ls180.v:4967$947_Y + assign $0\libresocsim_sdcore_cmd_count_sdcore_fsm_next_value_ce2[0:0] 1'1 + attribute \src "build/ls180/gateware/ls180.v:4969.5-4977.8" + switch $eq$build/ls180/gateware/ls180.v:4969$948_Y + attribute \src "build/ls180/gateware/ls180.v:4969.9-4969.47" + case 1'1 + attribute \src "build/ls180/gateware/ls180.v:4970.6-4976.9" + switch $eq$build/ls180/gateware/ls180.v:4970$949_Y + attribute \src "build/ls180/gateware/ls180.v:4970.10-4970.47" + case 1'1 + assign $0\libresocsim_sdcore_cmd_done_sdcore_fsm_next_value0[0:0] 1'1 + assign $0\libresocsim_sdcore_cmd_done_sdcore_fsm_next_value_ce0[0:0] 1'1 + assign $0\builder_sdcore_fsm_next_state[2:0] 3'000 + attribute \src "build/ls180/gateware/ls180.v:4974.10-4974.14" + case + assign $0\builder_sdcore_fsm_next_state[2:0] 3'010 + end + case + end + case + end + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case 3'010 + assign $0\libresocsim_cmdr_sink_valid[0:0] 1'1 + assign $0\libresocsim_cmdr_sink_last[0:0] $eq$build/ls180/gateware/ls180.v:4982$950_Y + assign $0\libresocsim_cmdr_source_ready[0:0] 1'1 + attribute \src "build/ls180/gateware/ls180.v:4983.4-4987.7" + switch $eq$build/ls180/gateware/ls180.v:4983$951_Y + attribute \src "build/ls180/gateware/ls180.v:4983.8-4983.45" + case 1'1 + assign $0\libresocsim_cmdr_sink_payload_length[7:0] 8'00010001 + attribute \src "build/ls180/gateware/ls180.v:4985.8-4985.12" + case + assign $0\libresocsim_cmdr_sink_payload_length[7:0] 8'00000110 + end + attribute \src "build/ls180/gateware/ls180.v:4989.4-5010.7" + switch \libresocsim_cmdr_source_valid + attribute \src "build/ls180/gateware/ls180.v:4989.8-4989.37" + case 1'1 + attribute \src "build/ls180/gateware/ls180.v:4990.5-5009.8" + switch $eq$build/ls180/gateware/ls180.v:4990$952_Y + attribute \src "build/ls180/gateware/ls180.v:4990.9-4990.57" + case 1'1 + assign $0\libresocsim_sdcore_cmd_timeout_sdcore_fsm_next_value5[0:0] 1'1 + assign $0\libresocsim_sdcore_cmd_timeout_sdcore_fsm_next_value_ce5[0:0] 1'1 + assign $0\builder_sdcore_fsm_next_state[2:0] 3'000 + attribute \src "build/ls180/gateware/ls180.v:4994.9-4994.13" + case + attribute \src "build/ls180/gateware/ls180.v:4995.6-5008.9" + switch \libresocsim_cmdr_source_last + attribute \src "build/ls180/gateware/ls180.v:4995.10-4995.38" + case 1'1 + attribute \src "build/ls180/gateware/ls180.v:4996.7-5004.10" + switch $eq$build/ls180/gateware/ls180.v:4996$953_Y + attribute \src "build/ls180/gateware/ls180.v:4996.11-4996.49" + case 1'1 + assign $0\builder_sdcore_fsm_next_state[2:0] 3'011 + attribute \src "build/ls180/gateware/ls180.v:4998.11-4998.15" + case + attribute \src "build/ls180/gateware/ls180.v:4999.8-5003.11" + switch $eq$build/ls180/gateware/ls180.v:4999$954_Y + attribute \src "build/ls180/gateware/ls180.v:4999.12-4999.50" + case 1'1 + assign $0\builder_sdcore_fsm_next_state[2:0] 3'100 + attribute \src "build/ls180/gateware/ls180.v:5001.12-5001.16" + case + assign $0\builder_sdcore_fsm_next_state[2:0] 3'000 + end + end + attribute \src "build/ls180/gateware/ls180.v:5005.10-5005.14" + case + assign $0\libresocsim_sdcore_cmd_response_status_sdcore_fsm_next_value8[127:0] { \libresocsim_sdcore_cmd_response_status [119:0] \libresocsim_cmdr_source_payload_data } + assign $0\libresocsim_sdcore_cmd_response_status_sdcore_fsm_next_value_ce8[0:0] 1'1 + end + end + case + end + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case 3'011 + assign $0\libresocsim_dataw_sink_valid[0:0] \libresocsim_sdcore_crc16_inserter_source_valid + assign $0\libresocsim_sdcore_crc16_inserter_source_ready[0:0] \libresocsim_dataw_sink_ready + assign $0\libresocsim_dataw_sink_first[0:0] \libresocsim_sdcore_crc16_inserter_source_first + assign $0\libresocsim_dataw_sink_last[0:0] \libresocsim_sdcore_crc16_inserter_source_last + assign $0\libresocsim_dataw_sink_payload_data[7:0] \libresocsim_sdcore_crc16_inserter_source_payload_data + assign $0\libresocsim_datar_source_ready[0:0] 1'1 + attribute \src "build/ls180/gateware/ls180.v:5018.4-5024.7" + switch $and$build/ls180/gateware/ls180.v:5018$956_Y + attribute \src "build/ls180/gateware/ls180.v:5018.8-5018.101" + case 1'1 + assign $0\libresocsim_sdcore_data_count_sdcore_fsm_next_value3[31:0] $add$build/ls180/gateware/ls180.v:5019$957_Y + assign $0\libresocsim_sdcore_data_count_sdcore_fsm_next_value_ce3[0:0] 1'1 + attribute \src "build/ls180/gateware/ls180.v:5021.5-5023.8" + switch $eq$build/ls180/gateware/ls180.v:5021$959_Y + attribute \src "build/ls180/gateware/ls180.v:5021.9-5021.91" + case 1'1 + assign $0\builder_sdcore_fsm_next_state[2:0] 3'000 + case + end + case + end + attribute \src "build/ls180/gateware/ls180.v:5026.4-5031.7" + switch \libresocsim_datar_source_valid + attribute \src "build/ls180/gateware/ls180.v:5026.8-5026.38" + case 1'1 + attribute \src "build/ls180/gateware/ls180.v:5027.5-5030.8" + switch $ne$build/ls180/gateware/ls180.v:5027$960_Y + attribute \src "build/ls180/gateware/ls180.v:5027.9-5027.58" + case 1'1 + assign $0\libresocsim_sdcore_data_error_sdcore_fsm_next_value6[0:0] 1'1 + assign $0\libresocsim_sdcore_data_error_sdcore_fsm_next_value_ce6[0:0] 1'1 + case + end + case + end + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case 3'100 + assign $0\libresocsim_datar_sink_valid[0:0] 1'1 + assign $0\libresocsim_datar_sink_payload_block_length[9:0] \libresocsim_sdcore_block_length_storage + assign $0\libresocsim_datar_sink_last[0:0] $eq$build/ls180/gateware/ls180.v:5036$962_Y + attribute \src "build/ls180/gateware/ls180.v:5037.4-5063.7" + switch \libresocsim_datar_source_valid + attribute \src "build/ls180/gateware/ls180.v:5037.8-5037.38" + case 1'1 + attribute \src "build/ls180/gateware/ls180.v:5038.5-5062.8" + switch $eq$build/ls180/gateware/ls180.v:5038$963_Y + attribute \src "build/ls180/gateware/ls180.v:5038.9-5038.58" + case 1'1 + assign $0\libresocsim_sdcore_crc16_checker_sink_valid[0:0] \libresocsim_datar_source_valid + assign $0\libresocsim_datar_source_ready[0:0] \libresocsim_sdcore_crc16_checker_sink_ready + assign $0\libresocsim_sdcore_crc16_checker_sink_first[0:0] \libresocsim_datar_source_first + assign $0\libresocsim_sdcore_crc16_checker_sink_last[0:0] \libresocsim_datar_source_last + assign $0\libresocsim_sdcore_crc16_checker_sink_payload_data[7:0] \libresocsim_datar_source_payload_data + attribute \src "build/ls180/gateware/ls180.v:5044.6-5052.9" + switch $and$build/ls180/gateware/ls180.v:5044$964_Y + attribute \src "build/ls180/gateware/ls180.v:5044.10-5044.74" + case 1'1 + assign $0\libresocsim_sdcore_data_count_sdcore_fsm_next_value3[31:0] $add$build/ls180/gateware/ls180.v:5045$965_Y + assign $0\libresocsim_sdcore_data_count_sdcore_fsm_next_value_ce3[0:0] 1'1 + attribute \src "build/ls180/gateware/ls180.v:5047.7-5051.10" + switch $eq$build/ls180/gateware/ls180.v:5047$967_Y + attribute \src "build/ls180/gateware/ls180.v:5047.11-5047.93" + case 1'1 + assign $0\builder_sdcore_fsm_next_state[2:0] 3'000 + attribute \src "build/ls180/gateware/ls180.v:5049.11-5049.15" + case + assign $0\builder_sdcore_fsm_next_state[2:0] 3'100 + end + case + end + attribute \src "build/ls180/gateware/ls180.v:5053.9-5053.13" + case + attribute \src "build/ls180/gateware/ls180.v:5054.6-5061.9" + switch $eq$build/ls180/gateware/ls180.v:5054$968_Y + attribute \src "build/ls180/gateware/ls180.v:5054.10-5054.59" + case 1'1 + assign $0\libresocsim_sdcore_data_timeout_sdcore_fsm_next_value7[0:0] 1'1 + assign $0\libresocsim_sdcore_data_timeout_sdcore_fsm_next_value_ce7[0:0] 1'1 + assign $0\libresocsim_sdcore_data_count_sdcore_fsm_next_value3[31:0] 0 + assign $0\libresocsim_sdcore_data_count_sdcore_fsm_next_value_ce3[0:0] 1'1 + assign $0\libresocsim_datar_source_ready[0:0] 1'1 + assign $0\builder_sdcore_fsm_next_state[2:0] 3'000 + case + end + end + case + end + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case + assign $0\libresocsim_sdcore_cmd_done_sdcore_fsm_next_value0[0:0] 1'1 + assign $0\libresocsim_sdcore_cmd_done_sdcore_fsm_next_value_ce0[0:0] 1'1 + assign $0\libresocsim_sdcore_data_done_sdcore_fsm_next_value1[0:0] 1'1 + assign $0\libresocsim_sdcore_data_done_sdcore_fsm_next_value_ce1[0:0] 1'1 + assign $0\libresocsim_sdcore_cmd_count_sdcore_fsm_next_value2[2:0] 3'000 + assign $0\libresocsim_sdcore_cmd_count_sdcore_fsm_next_value_ce2[0:0] 1'1 + assign $0\libresocsim_sdcore_data_count_sdcore_fsm_next_value3[31:0] 0 + assign $0\libresocsim_sdcore_data_count_sdcore_fsm_next_value_ce3[0:0] 1'1 + attribute \src "build/ls180/gateware/ls180.v:5074.4-5088.7" + switch \libresocsim_sdcore_cmd_send_re + attribute \src "build/ls180/gateware/ls180.v:5074.8-5074.38" + case 1'1 + assign $0\libresocsim_sdcore_cmd_done_sdcore_fsm_next_value0[0:0] 1'0 + assign $0\libresocsim_sdcore_cmd_done_sdcore_fsm_next_value_ce0[0:0] 1'1 + assign $0\libresocsim_sdcore_cmd_error_sdcore_fsm_next_value4[0:0] 1'0 + assign $0\libresocsim_sdcore_cmd_error_sdcore_fsm_next_value_ce4[0:0] 1'1 + assign $0\libresocsim_sdcore_cmd_timeout_sdcore_fsm_next_value5[0:0] 1'0 + assign $0\libresocsim_sdcore_cmd_timeout_sdcore_fsm_next_value_ce5[0:0] 1'1 + assign $0\libresocsim_sdcore_data_done_sdcore_fsm_next_value1[0:0] 1'0 + assign $0\libresocsim_sdcore_data_done_sdcore_fsm_next_value_ce1[0:0] 1'1 + assign $0\libresocsim_sdcore_data_error_sdcore_fsm_next_value6[0:0] 1'0 + assign $0\libresocsim_sdcore_data_error_sdcore_fsm_next_value_ce6[0:0] 1'1 + assign $0\libresocsim_sdcore_data_timeout_sdcore_fsm_next_value7[0:0] 1'0 + assign $0\libresocsim_sdcore_data_timeout_sdcore_fsm_next_value_ce7[0:0] 1'1 + assign $0\builder_sdcore_fsm_next_state[2:0] 3'001 + case + end + end + sync always + update \libresocsim_cmdw_sink_valid $0\libresocsim_cmdw_sink_valid[0:0] + update \libresocsim_cmdw_sink_last $0\libresocsim_cmdw_sink_last[0:0] + update \libresocsim_cmdw_sink_payload_data $0\libresocsim_cmdw_sink_payload_data[7:0] + update \libresocsim_cmdr_sink_valid $0\libresocsim_cmdr_sink_valid[0:0] + update \libresocsim_cmdr_sink_last $0\libresocsim_cmdr_sink_last[0:0] + update \libresocsim_cmdr_sink_payload_length $0\libresocsim_cmdr_sink_payload_length[7:0] + update \libresocsim_cmdr_source_ready $0\libresocsim_cmdr_source_ready[0:0] + update \libresocsim_dataw_sink_valid $0\libresocsim_dataw_sink_valid[0:0] + update \libresocsim_dataw_sink_first $0\libresocsim_dataw_sink_first[0:0] + update \libresocsim_dataw_sink_last $0\libresocsim_dataw_sink_last[0:0] + update \libresocsim_dataw_sink_payload_data $0\libresocsim_dataw_sink_payload_data[7:0] + update \libresocsim_datar_sink_valid $0\libresocsim_datar_sink_valid[0:0] + update \libresocsim_datar_sink_last $0\libresocsim_datar_sink_last[0:0] + update \libresocsim_datar_sink_payload_block_length $0\libresocsim_datar_sink_payload_block_length[9:0] + update \libresocsim_datar_source_ready $0\libresocsim_datar_source_ready[0:0] + update \libresocsim_sdcore_crc16_inserter_source_ready $0\libresocsim_sdcore_crc16_inserter_source_ready[0:0] + update \libresocsim_sdcore_crc16_checker_sink_valid $0\libresocsim_sdcore_crc16_checker_sink_valid[0:0] + update \libresocsim_sdcore_crc16_checker_sink_first $0\libresocsim_sdcore_crc16_checker_sink_first[0:0] + update \libresocsim_sdcore_crc16_checker_sink_last $0\libresocsim_sdcore_crc16_checker_sink_last[0:0] + update \libresocsim_sdcore_crc16_checker_sink_payload_data $0\libresocsim_sdcore_crc16_checker_sink_payload_data[7:0] + update \builder_sdcore_fsm_next_state $0\builder_sdcore_fsm_next_state[2:0] + update \libresocsim_sdcore_cmd_done_sdcore_fsm_next_value0 $0\libresocsim_sdcore_cmd_done_sdcore_fsm_next_value0[0:0] + update \libresocsim_sdcore_cmd_done_sdcore_fsm_next_value_ce0 $0\libresocsim_sdcore_cmd_done_sdcore_fsm_next_value_ce0[0:0] + update \libresocsim_sdcore_data_done_sdcore_fsm_next_value1 $0\libresocsim_sdcore_data_done_sdcore_fsm_next_value1[0:0] + update \libresocsim_sdcore_data_done_sdcore_fsm_next_value_ce1 $0\libresocsim_sdcore_data_done_sdcore_fsm_next_value_ce1[0:0] + update \libresocsim_sdcore_cmd_count_sdcore_fsm_next_value2 $0\libresocsim_sdcore_cmd_count_sdcore_fsm_next_value2[2:0] + update \libresocsim_sdcore_cmd_count_sdcore_fsm_next_value_ce2 $0\libresocsim_sdcore_cmd_count_sdcore_fsm_next_value_ce2[0:0] + update \libresocsim_sdcore_data_count_sdcore_fsm_next_value3 $0\libresocsim_sdcore_data_count_sdcore_fsm_next_value3[31:0] + update \libresocsim_sdcore_data_count_sdcore_fsm_next_value_ce3 $0\libresocsim_sdcore_data_count_sdcore_fsm_next_value_ce3[0:0] + update \libresocsim_sdcore_cmd_error_sdcore_fsm_next_value4 $0\libresocsim_sdcore_cmd_error_sdcore_fsm_next_value4[0:0] + update \libresocsim_sdcore_cmd_error_sdcore_fsm_next_value_ce4 $0\libresocsim_sdcore_cmd_error_sdcore_fsm_next_value_ce4[0:0] + update \libresocsim_sdcore_cmd_timeout_sdcore_fsm_next_value5 $0\libresocsim_sdcore_cmd_timeout_sdcore_fsm_next_value5[0:0] + update \libresocsim_sdcore_cmd_timeout_sdcore_fsm_next_value_ce5 $0\libresocsim_sdcore_cmd_timeout_sdcore_fsm_next_value_ce5[0:0] + update \libresocsim_sdcore_data_error_sdcore_fsm_next_value6 $0\libresocsim_sdcore_data_error_sdcore_fsm_next_value6[0:0] + update \libresocsim_sdcore_data_error_sdcore_fsm_next_value_ce6 $0\libresocsim_sdcore_data_error_sdcore_fsm_next_value_ce6[0:0] + update \libresocsim_sdcore_data_timeout_sdcore_fsm_next_value7 $0\libresocsim_sdcore_data_timeout_sdcore_fsm_next_value7[0:0] + update \libresocsim_sdcore_data_timeout_sdcore_fsm_next_value_ce7 $0\libresocsim_sdcore_data_timeout_sdcore_fsm_next_value_ce7[0:0] + update \libresocsim_sdcore_cmd_response_status_sdcore_fsm_next_value8 $0\libresocsim_sdcore_cmd_response_status_sdcore_fsm_next_value8[127:0] + update \libresocsim_sdcore_cmd_response_status_sdcore_fsm_next_value_ce8 $0\libresocsim_sdcore_cmd_response_status_sdcore_fsm_next_value_ce8[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:493.5-493.67" + process $proc$build/ls180/gateware/ls180.v:493$2746 + assign { } { } + assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_sink_first[0:0] 1'0 + sync always + update \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_first $0\main_sdram_bankmachine0_cmd_buffer_lookahead_sink_first[0:0] + sync init + end + attribute \src "build/ls180/gateware/ls180.v:494.5-494.66" + process $proc$build/ls180/gateware/ls180.v:494$2747 + assign { } { } + assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_sink_last[0:0] 1'0 + sync always + update \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_last $0\main_sdram_bankmachine0_cmd_buffer_lookahead_sink_last[0:0] + sync init + end + attribute \src "build/ls180/gateware/ls180.v:50.5-50.46" + process $proc$build/ls180/gateware/ls180.v:50$2569 + assign { } { } + assign $1\main_libresocsim_libresoc_dbus_ack[0:0] 1'0 + sync always + sync init + update \main_libresocsim_libresoc_dbus_ack $1\main_libresocsim_libresoc_dbus_ack[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:509.11-509.68" + process $proc$build/ls180/gateware/ls180.v:509$2748 + assign { } { } + assign $1\main_sdram_bankmachine0_cmd_buffer_lookahead_level[3:0] 4'0000 + sync always + sync init + update \main_sdram_bankmachine0_cmd_buffer_lookahead_level $1\main_sdram_bankmachine0_cmd_buffer_lookahead_level[3:0] + end + attribute \src "build/ls180/gateware/ls180.v:510.5-510.64" + process $proc$build/ls180/gateware/ls180.v:510$2749 + assign { } { } + assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_replace[0:0] 1'0 + sync always + update \main_sdram_bankmachine0_cmd_buffer_lookahead_replace $0\main_sdram_bankmachine0_cmd_buffer_lookahead_replace[0:0] + sync init + end + attribute \src "build/ls180/gateware/ls180.v:511.11-511.70" + process $proc$build/ls180/gateware/ls180.v:511$2750 + assign { } { } + assign $1\main_sdram_bankmachine0_cmd_buffer_lookahead_produce[2:0] 3'000 + sync always + sync init + update \main_sdram_bankmachine0_cmd_buffer_lookahead_produce $1\main_sdram_bankmachine0_cmd_buffer_lookahead_produce[2:0] + end + attribute \src "build/ls180/gateware/ls180.v:5119.1-5126.4" + process $proc$build/ls180/gateware/ls180.v:5119$969 + assign { } { } + assign $0\libresocsim_sdblock2mem_fifo_wrport_adr[4:0] 5'00000 + attribute \src "build/ls180/gateware/ls180.v:5121.2-5125.5" + switch \libresocsim_sdblock2mem_fifo_replace + attribute \src "build/ls180/gateware/ls180.v:5121.6-5121.42" + case 1'1 + assign $0\libresocsim_sdblock2mem_fifo_wrport_adr[4:0] $sub$build/ls180/gateware/ls180.v:5122$970_Y + attribute \src "build/ls180/gateware/ls180.v:5123.6-5123.10" + case + assign $0\libresocsim_sdblock2mem_fifo_wrport_adr[4:0] \libresocsim_sdblock2mem_fifo_produce + end + sync always + update \libresocsim_sdblock2mem_fifo_wrport_adr $0\libresocsim_sdblock2mem_fifo_wrport_adr[4:0] + end + attribute \src "build/ls180/gateware/ls180.v:512.11-512.70" + process $proc$build/ls180/gateware/ls180.v:512$2751 + assign { } { } + assign $1\main_sdram_bankmachine0_cmd_buffer_lookahead_consume[2:0] 3'000 + sync always + sync init + update \main_sdram_bankmachine0_cmd_buffer_lookahead_consume $1\main_sdram_bankmachine0_cmd_buffer_lookahead_consume[2:0] + end + attribute \src "build/ls180/gateware/ls180.v:513.11-513.73" + process $proc$build/ls180/gateware/ls180.v:513$2752 + assign { } { } + assign $1\main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr[2:0] 3'000 + sync always + sync init + update \main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr $1\main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr[2:0] + end + attribute \src "build/ls180/gateware/ls180.v:5152.1-5191.4" + process $proc$build/ls180/gateware/ls180.v:5152$980 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\libresocsim_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value[31:0] 0 + assign $0\libresocsim_sdblock2mem_sink_sink_valid1[0:0] 1'0 + assign $0\libresocsim_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value_ce[0:0] 1'0 + assign $0\libresocsim_sdblock2mem_sink_sink_payload_address[31:0] 0 + assign $0\libresocsim_sdblock2mem_sink_sink_payload_data1[31:0] 0 + assign $0\libresocsim_sdblock2mem_wishbonedmawriter_status[0:0] 1'0 + assign $0\libresocsim_sdblock2mem_wishbonedmawriter_sink_ready[0:0] 1'0 + assign $0\builder_sdblock2memdma_next_state[1:0] \builder_sdblock2memdma_state + attribute \src "build/ls180/gateware/ls180.v:5162.2-5190.9" + switch \builder_sdblock2memdma_state + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case 2'01 + assign $0\libresocsim_sdblock2mem_sink_sink_valid1[0:0] \libresocsim_sdblock2mem_wishbonedmawriter_sink_valid + assign $0\libresocsim_sdblock2mem_sink_sink_payload_data1[31:0] \libresocsim_sdblock2mem_wishbonedmawriter_sink_payload_data + assign $0\libresocsim_sdblock2mem_sink_sink_payload_address[31:0] $add$build/ls180/gateware/ls180.v:5166$981_Y + assign $0\libresocsim_sdblock2mem_wishbonedmawriter_sink_ready[0:0] \libresocsim_sdblock2mem_sink_sink_ready1 + attribute \src "build/ls180/gateware/ls180.v:5168.4-5179.7" + switch $and$build/ls180/gateware/ls180.v:5168$982_Y + attribute \src "build/ls180/gateware/ls180.v:5168.8-5168.117" + case 1'1 + assign $0\libresocsim_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value[31:0] $add$build/ls180/gateware/ls180.v:5169$983_Y + assign $0\libresocsim_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value_ce[0:0] 1'1 + attribute \src "build/ls180/gateware/ls180.v:5171.5-5178.8" + switch $eq$build/ls180/gateware/ls180.v:5171$985_Y + attribute \src "build/ls180/gateware/ls180.v:5171.9-5171.120" + case 1'1 + attribute \src "build/ls180/gateware/ls180.v:5172.6-5177.9" + switch \libresocsim_sdblock2mem_wishbonedmawriter_loop_storage + attribute \src "build/ls180/gateware/ls180.v:5172.10-5172.64" + case 1'1 + assign $0\libresocsim_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value[31:0] 0 + assign $0\libresocsim_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value_ce[0:0] 1'1 + attribute \src "build/ls180/gateware/ls180.v:5175.10-5175.14" + case + assign $0\builder_sdblock2memdma_next_state[1:0] 2'10 + end + case + end + case + end + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case 2'10 + assign $0\libresocsim_sdblock2mem_wishbonedmawriter_status[0:0] 1'1 + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case + assign $0\libresocsim_sdblock2mem_wishbonedmawriter_sink_ready[0:0] 1'1 + assign $0\libresocsim_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value[31:0] 0 + assign $0\libresocsim_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value_ce[0:0] 1'1 + assign $0\builder_sdblock2memdma_next_state[1:0] 2'01 + end + sync always + update \libresocsim_sdblock2mem_sink_sink_valid1 $0\libresocsim_sdblock2mem_sink_sink_valid1[0:0] + update \libresocsim_sdblock2mem_sink_sink_payload_address $0\libresocsim_sdblock2mem_sink_sink_payload_address[31:0] + update \libresocsim_sdblock2mem_sink_sink_payload_data1 $0\libresocsim_sdblock2mem_sink_sink_payload_data1[31:0] + update \libresocsim_sdblock2mem_wishbonedmawriter_sink_ready $0\libresocsim_sdblock2mem_wishbonedmawriter_sink_ready[0:0] + update \libresocsim_sdblock2mem_wishbonedmawriter_status $0\libresocsim_sdblock2mem_wishbonedmawriter_status[0:0] + update \builder_sdblock2memdma_next_state $0\builder_sdblock2memdma_next_state[1:0] + update \libresocsim_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value $0\libresocsim_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value[31:0] + update \libresocsim_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value_ce $0\libresocsim_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value_ce[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:5211.1-5248.4" + process $proc$build/ls180/gateware/ls180.v:5211$987 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\libresocsim_sdmem2block_dma_source_last[0:0] 1'0 + assign $0\libresocsim_sdmem2block_dma_source_payload_data[31:0] 0 + assign $0\libresocsim_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value_ce[0:0] 1'0 + assign $0\libresocsim_sdmem2block_dma_source_valid[0:0] 1'0 + assign $0\libresocsim_interface1_bus_adr[31:0] 0 + assign $0\libresocsim_sdmem2block_dma_sink_ready[0:0] 1'0 + assign $0\libresocsim_interface1_bus_sel[3:0] 4'0000 + assign $0\libresocsim_interface1_bus_cyc[0:0] 1'0 + assign { } { } + assign $0\libresocsim_interface1_bus_stb[0:0] 1'0 + assign $0\libresocsim_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value[31:0] 0 + assign $0\libresocsim_interface1_bus_we[0:0] 1'0 + assign $0\builder_sdmem2blockdma_fsm_next_state[0:0] \builder_sdmem2blockdma_fsm_state + attribute \src "build/ls180/gateware/ls180.v:5225.2-5247.9" + switch \builder_sdmem2blockdma_fsm_state + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case 1'1 + assign $0\libresocsim_sdmem2block_dma_source_valid[0:0] 1'1 + assign $0\libresocsim_sdmem2block_dma_source_last[0:0] \libresocsim_sdmem2block_dma_sink_last + assign $0\libresocsim_sdmem2block_dma_source_payload_data[31:0] \libresocsim_sdmem2block_dma_data + attribute \src "build/ls180/gateware/ls180.v:5230.4-5233.7" + switch \libresocsim_sdmem2block_dma_source_ready + attribute \src "build/ls180/gateware/ls180.v:5230.8-5230.48" + case 1'1 + assign $0\libresocsim_sdmem2block_dma_sink_ready[0:0] 1'1 + assign $0\builder_sdmem2blockdma_fsm_next_state[0:0] 1'0 + case + end + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case + assign $0\libresocsim_interface1_bus_stb[0:0] \libresocsim_sdmem2block_dma_sink_valid + assign $0\libresocsim_interface1_bus_cyc[0:0] \libresocsim_sdmem2block_dma_sink_valid + assign $0\libresocsim_interface1_bus_we[0:0] 1'0 + assign $0\libresocsim_interface1_bus_sel[3:0] 4'1111 + assign $0\libresocsim_interface1_bus_adr[31:0] \libresocsim_sdmem2block_dma_sink_payload_address + attribute \src "build/ls180/gateware/ls180.v:5241.4-5245.7" + switch $and$build/ls180/gateware/ls180.v:5241$988_Y + attribute \src "build/ls180/gateware/ls180.v:5241.8-5241.73" + case 1'1 + assign $0\libresocsim_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value[31:0] { \libresocsim_interface1_bus_dat_r [7:0] \libresocsim_interface1_bus_dat_r [15:8] \libresocsim_interface1_bus_dat_r [23:16] \libresocsim_interface1_bus_dat_r [31:24] } + assign $0\libresocsim_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value_ce[0:0] 1'1 + assign $0\builder_sdmem2blockdma_fsm_next_state[0:0] 1'1 + case + end + end + sync always + update \libresocsim_interface1_bus_adr $0\libresocsim_interface1_bus_adr[31:0] + update \libresocsim_interface1_bus_sel $0\libresocsim_interface1_bus_sel[3:0] + update \libresocsim_interface1_bus_cyc $0\libresocsim_interface1_bus_cyc[0:0] + update \libresocsim_interface1_bus_stb $0\libresocsim_interface1_bus_stb[0:0] + update \libresocsim_interface1_bus_we $0\libresocsim_interface1_bus_we[0:0] + update \libresocsim_sdmem2block_dma_sink_ready $0\libresocsim_sdmem2block_dma_sink_ready[0:0] + update \libresocsim_sdmem2block_dma_source_valid $0\libresocsim_sdmem2block_dma_source_valid[0:0] + update \libresocsim_sdmem2block_dma_source_last $0\libresocsim_sdmem2block_dma_source_last[0:0] + update \libresocsim_sdmem2block_dma_source_payload_data $0\libresocsim_sdmem2block_dma_source_payload_data[31:0] + update \builder_sdmem2blockdma_fsm_next_state $0\builder_sdmem2blockdma_fsm_next_state[0:0] + update \libresocsim_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value $0\libresocsim_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value[31:0] + update \libresocsim_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value_ce $0\libresocsim_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value_ce[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:5249.1-5285.4" + process $proc$build/ls180/gateware/ls180.v:5249$989 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\libresocsim_sdmem2block_dma_done_status[0:0] 1'0 + assign $0\libresocsim_sdmem2block_dma_sink_valid[0:0] 1'0 + assign $0\libresocsim_sdmem2block_dma_sink_last[0:0] 1'0 + assign $0\libresocsim_sdmem2block_dma_sink_payload_address[31:0] 0 + assign { } { } + assign $0\libresocsim_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value[31:0] 0 + assign $0\libresocsim_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value_ce[0:0] 1'0 + assign $0\builder_sdmem2blockdma_resetinserter_next_state[1:0] \builder_sdmem2blockdma_resetinserter_state + attribute \src "build/ls180/gateware/ls180.v:5258.2-5284.9" + switch \builder_sdmem2blockdma_resetinserter_state + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case 2'01 + assign $0\libresocsim_sdmem2block_dma_sink_valid[0:0] 1'1 + assign $0\libresocsim_sdmem2block_dma_sink_last[0:0] $eq$build/ls180/gateware/ls180.v:5261$991_Y + assign $0\libresocsim_sdmem2block_dma_sink_payload_address[31:0] $add$build/ls180/gateware/ls180.v:5262$992_Y + attribute \src "build/ls180/gateware/ls180.v:5263.4-5274.7" + switch \libresocsim_sdmem2block_dma_sink_ready + attribute \src "build/ls180/gateware/ls180.v:5263.8-5263.46" + case 1'1 + assign $0\libresocsim_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value[31:0] $add$build/ls180/gateware/ls180.v:5264$993_Y + assign $0\libresocsim_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value_ce[0:0] 1'1 + attribute \src "build/ls180/gateware/ls180.v:5266.5-5273.8" + switch \libresocsim_sdmem2block_dma_sink_last + attribute \src "build/ls180/gateware/ls180.v:5266.9-5266.46" + case 1'1 + attribute \src "build/ls180/gateware/ls180.v:5267.6-5272.9" + switch \libresocsim_sdmem2block_dma_loop_storage + attribute \src "build/ls180/gateware/ls180.v:5267.10-5267.50" + case 1'1 + assign $0\libresocsim_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value[31:0] 0 + assign $0\libresocsim_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value_ce[0:0] 1'1 + attribute \src "build/ls180/gateware/ls180.v:5270.10-5270.14" + case + assign $0\builder_sdmem2blockdma_resetinserter_next_state[1:0] 2'10 + end + case + end + case + end + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case 2'10 + assign $0\libresocsim_sdmem2block_dma_done_status[0:0] 1'1 + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case + assign $0\libresocsim_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value[31:0] 0 + assign $0\libresocsim_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value_ce[0:0] 1'1 + assign $0\builder_sdmem2blockdma_resetinserter_next_state[1:0] 2'01 + end + sync always + update \libresocsim_sdmem2block_dma_sink_valid $0\libresocsim_sdmem2block_dma_sink_valid[0:0] + update \libresocsim_sdmem2block_dma_sink_last $0\libresocsim_sdmem2block_dma_sink_last[0:0] + update \libresocsim_sdmem2block_dma_sink_payload_address $0\libresocsim_sdmem2block_dma_sink_payload_address[31:0] + update \libresocsim_sdmem2block_dma_done_status $0\libresocsim_sdmem2block_dma_done_status[0:0] + update \builder_sdmem2blockdma_resetinserter_next_state $0\builder_sdmem2blockdma_resetinserter_next_state[1:0] + update \libresocsim_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value $0\libresocsim_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value[31:0] + update \libresocsim_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value_ce $0\libresocsim_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value_ce[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:5297.1-5313.4" + process $proc$build/ls180/gateware/ls180.v:5297$999 + assign { } { } + assign $0\libresocsim_sdmem2block_converter_source_payload_data[7:0] 8'00000000 + attribute \src "build/ls180/gateware/ls180.v:5299.2-5312.9" + switch \libresocsim_sdmem2block_converter_mux + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case 2'00 + assign $0\libresocsim_sdmem2block_converter_source_payload_data[7:0] \libresocsim_sdmem2block_converter_sink_payload_data [31:24] + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case 2'01 + assign $0\libresocsim_sdmem2block_converter_source_payload_data[7:0] \libresocsim_sdmem2block_converter_sink_payload_data [23:16] + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case 2'10 + assign $0\libresocsim_sdmem2block_converter_source_payload_data[7:0] \libresocsim_sdmem2block_converter_sink_payload_data [15:8] + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case + assign $0\libresocsim_sdmem2block_converter_source_payload_data[7:0] \libresocsim_sdmem2block_converter_sink_payload_data [7:0] + end + sync always + update \libresocsim_sdmem2block_converter_source_payload_data $0\libresocsim_sdmem2block_converter_source_payload_data[7:0] + end + attribute \src "build/ls180/gateware/ls180.v:5327.1-5334.4" + process $proc$build/ls180/gateware/ls180.v:5327$1000 + assign { } { } + assign $0\libresocsim_sdmem2block_fifo_wrport_adr[4:0] 5'00000 + attribute \src "build/ls180/gateware/ls180.v:5329.2-5333.5" + switch \libresocsim_sdmem2block_fifo_replace + attribute \src "build/ls180/gateware/ls180.v:5329.6-5329.42" + case 1'1 + assign $0\libresocsim_sdmem2block_fifo_wrport_adr[4:0] $sub$build/ls180/gateware/ls180.v:5330$1001_Y + attribute \src "build/ls180/gateware/ls180.v:5331.6-5331.10" + case + assign $0\libresocsim_sdmem2block_fifo_wrport_adr[4:0] \libresocsim_sdmem2block_fifo_produce + end + sync always + update \libresocsim_sdmem2block_fifo_wrport_adr $0\libresocsim_sdmem2block_fifo_wrport_adr[4:0] + end + attribute \src "build/ls180/gateware/ls180.v:534.5-534.59" + process $proc$build/ls180/gateware/ls180.v:534$2753 + assign { } { } + assign $1\main_sdram_bankmachine0_cmd_buffer_source_valid[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine0_cmd_buffer_source_valid $1\main_sdram_bankmachine0_cmd_buffer_source_valid[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:5352.1-5400.4" + process $proc$build/ls180/gateware/ls180.v:5352$1011 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\libresocsim_cs_enable[0:0] 1'0 + assign { } { } + assign $0\libresocsim_count_spimaster1_next_value[2:0] 3'000 + assign $0\libresocsim_mosi_latch[0:0] 1'0 + assign $0\libresocsim_count_spimaster1_next_value_ce[0:0] 1'0 + assign $0\libresocsim_done0[0:0] 1'0 + assign $0\libresocsim_miso_latch[0:0] 1'0 + assign $0\libresocsim_irq[0:0] 1'0 + assign $0\libresocsim_clk_enable[0:0] 1'0 + assign $0\builder_spimaster1_next_state[1:0] \builder_spimaster1_state + attribute \src "build/ls180/gateware/ls180.v:5363.2-5399.9" + switch \builder_spimaster1_state + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case 2'01 + assign $0\libresocsim_count_spimaster1_next_value[2:0] 3'000 + assign $0\libresocsim_count_spimaster1_next_value_ce[0:0] 1'1 + attribute \src "build/ls180/gateware/ls180.v:5367.4-5370.7" + switch \libresocsim_clk_fall + attribute \src "build/ls180/gateware/ls180.v:5367.8-5367.28" + case 1'1 + assign $0\libresocsim_cs_enable[0:0] 1'1 + assign $0\builder_spimaster1_next_state[1:0] 2'10 + case + end + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case 2'10 + assign $0\libresocsim_clk_enable[0:0] 1'1 + assign $0\libresocsim_cs_enable[0:0] 1'1 + attribute \src "build/ls180/gateware/ls180.v:5375.4-5381.7" + switch \libresocsim_clk_fall + attribute \src "build/ls180/gateware/ls180.v:5375.8-5375.28" + case 1'1 + assign $0\libresocsim_count_spimaster1_next_value[2:0] $add$build/ls180/gateware/ls180.v:5376$1012_Y + assign $0\libresocsim_count_spimaster1_next_value_ce[0:0] 1'1 + attribute \src "build/ls180/gateware/ls180.v:5378.5-5380.8" + switch $eq$build/ls180/gateware/ls180.v:5378$1014_Y + attribute \src "build/ls180/gateware/ls180.v:5378.9-5378.60" + case 1'1 + assign $0\builder_spimaster1_next_state[1:0] 2'11 + case + end + case + end + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case 2'11 + assign $0\libresocsim_cs_enable[0:0] 1'1 + attribute \src "build/ls180/gateware/ls180.v:5385.4-5389.7" + switch \libresocsim_clk_rise + attribute \src "build/ls180/gateware/ls180.v:5385.8-5385.28" + case 1'1 + assign $0\libresocsim_miso_latch[0:0] 1'1 + assign $0\libresocsim_irq[0:0] 1'1 + assign $0\builder_spimaster1_next_state[1:0] 2'00 + case + end + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case + assign $0\libresocsim_done0[0:0] 1'1 + attribute \src "build/ls180/gateware/ls180.v:5393.4-5397.7" + switch \libresocsim_start0 + attribute \src "build/ls180/gateware/ls180.v:5393.8-5393.26" + case 1'1 + assign $0\libresocsim_done0[0:0] 1'0 + assign $0\libresocsim_mosi_latch[0:0] 1'1 + assign $0\builder_spimaster1_next_state[1:0] 2'01 + case + end + end + sync always + update \libresocsim_done0 $0\libresocsim_done0[0:0] + update \libresocsim_irq $0\libresocsim_irq[0:0] + update \libresocsim_clk_enable $0\libresocsim_clk_enable[0:0] + update \libresocsim_cs_enable $0\libresocsim_cs_enable[0:0] + update \libresocsim_mosi_latch $0\libresocsim_mosi_latch[0:0] + update \libresocsim_miso_latch $0\libresocsim_miso_latch[0:0] + update \builder_spimaster1_next_state $0\builder_spimaster1_next_state[1:0] + update \libresocsim_count_spimaster1_next_value $0\libresocsim_count_spimaster1_next_value[2:0] + update \libresocsim_count_spimaster1_next_value_ce $0\libresocsim_count_spimaster1_next_value_ce[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:536.5-536.59" + process $proc$build/ls180/gateware/ls180.v:536$2754 + assign { } { } + assign $1\main_sdram_bankmachine0_cmd_buffer_source_first[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine0_cmd_buffer_source_first $1\main_sdram_bankmachine0_cmd_buffer_source_first[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:537.5-537.58" + process $proc$build/ls180/gateware/ls180.v:537$2755 + assign { } { } + assign $1\main_sdram_bankmachine0_cmd_buffer_source_last[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine0_cmd_buffer_source_last $1\main_sdram_bankmachine0_cmd_buffer_source_last[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:538.5-538.64" + process $proc$build/ls180/gateware/ls180.v:538$2756 + assign { } { } + assign $1\main_sdram_bankmachine0_cmd_buffer_source_payload_we[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine0_cmd_buffer_source_payload_we $1\main_sdram_bankmachine0_cmd_buffer_source_payload_we[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:539.12-539.74" + process $proc$build/ls180/gateware/ls180.v:539$2757 + assign { } { } + assign $1\main_sdram_bankmachine0_cmd_buffer_source_payload_addr[21:0] 22'0000000000000000000000 + sync always + sync init + update \main_sdram_bankmachine0_cmd_buffer_source_payload_addr $1\main_sdram_bankmachine0_cmd_buffer_source_payload_addr[21:0] + end + attribute \src "build/ls180/gateware/ls180.v:54.5-54.46" + process $proc$build/ls180/gateware/ls180.v:54$2570 + assign { } { } + assign $0\main_libresocsim_libresoc_dbus_err[0:0] 1'0 + sync always + update \main_libresocsim_libresoc_dbus_err $0\main_libresocsim_libresoc_dbus_err[0:0] + sync init + end + attribute \src "build/ls180/gateware/ls180.v:540.12-540.47" + process $proc$build/ls180/gateware/ls180.v:540$2758 + assign { } { } + assign $1\main_sdram_bankmachine0_row[12:0] 13'0000000000000 + sync always + sync init + update \main_sdram_bankmachine0_row $1\main_sdram_bankmachine0_row[12:0] + end + attribute \src "build/ls180/gateware/ls180.v:5401.1-5437.4" + process $proc$build/ls180/gateware/ls180.v:5401$1015 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\builder_libresocsim_adr_next_value1[13:0] 14'00000000000000 + assign $0\builder_libresocsim_adr_next_value_ce1[0:0] 1'0 + assign $0\builder_libresocsim_wishbone_dat_r[31:0] 0 + assign $0\builder_libresocsim_we_next_value2[0:0] 1'0 + assign $0\builder_libresocsim_we_next_value_ce2[0:0] 1'0 + assign $0\builder_libresocsim_wishbone_ack[0:0] 1'0 + assign { } { } + assign $0\builder_libresocsim_dat_w_next_value0[7:0] 8'00000000 + assign $0\builder_libresocsim_dat_w_next_value_ce0[0:0] 1'0 + assign $0\builder_next_state[1:0] \builder_state + attribute \src "build/ls180/gateware/ls180.v:5412.2-5436.9" + switch \builder_state + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case 2'01 + assign $0\builder_libresocsim_adr_next_value1[13:0] 14'00000000000000 + assign $0\builder_libresocsim_adr_next_value_ce1[0:0] 1'1 + assign $0\builder_libresocsim_we_next_value2[0:0] 1'0 + assign $0\builder_libresocsim_we_next_value_ce2[0:0] 1'1 + assign $0\builder_next_state[1:0] 2'10 + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case 2'10 + assign $0\builder_libresocsim_wishbone_ack[0:0] 1'1 + assign $0\builder_libresocsim_wishbone_dat_r[31:0] { 24'000000000000000000000000 \builder_libresocsim_dat_r } + assign $0\builder_next_state[1:0] 2'00 + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case + assign $0\builder_libresocsim_dat_w_next_value0[7:0] \builder_libresocsim_wishbone_dat_w [7:0] + assign $0\builder_libresocsim_dat_w_next_value_ce0[0:0] 1'1 + attribute \src "build/ls180/gateware/ls180.v:5428.4-5434.7" + switch $and$build/ls180/gateware/ls180.v:5428$1016_Y + attribute \src "build/ls180/gateware/ls180.v:5428.8-5428.77" + case 1'1 + assign $0\builder_libresocsim_adr_next_value1[13:0] \builder_libresocsim_wishbone_adr [13:0] + assign $0\builder_libresocsim_adr_next_value_ce1[0:0] 1'1 + assign $0\builder_libresocsim_we_next_value2[0:0] $and$build/ls180/gateware/ls180.v:5431$1018_Y + assign $0\builder_libresocsim_we_next_value_ce2[0:0] 1'1 + assign $0\builder_next_state[1:0] 2'01 + case + end + end + sync always + update \builder_libresocsim_wishbone_dat_r $0\builder_libresocsim_wishbone_dat_r[31:0] + update \builder_libresocsim_wishbone_ack $0\builder_libresocsim_wishbone_ack[0:0] + update \builder_next_state $0\builder_next_state[1:0] + update \builder_libresocsim_dat_w_next_value0 $0\builder_libresocsim_dat_w_next_value0[7:0] + update \builder_libresocsim_dat_w_next_value_ce0 $0\builder_libresocsim_dat_w_next_value_ce0[0:0] + update \builder_libresocsim_adr_next_value1 $0\builder_libresocsim_adr_next_value1[13:0] + update \builder_libresocsim_adr_next_value_ce1 $0\builder_libresocsim_adr_next_value_ce1[0:0] + update \builder_libresocsim_we_next_value2 $0\builder_libresocsim_we_next_value2[0:0] + update \builder_libresocsim_we_next_value_ce2 $0\builder_libresocsim_we_next_value_ce2[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:541.5-541.46" + process $proc$build/ls180/gateware/ls180.v:541$2759 + assign { } { } + assign $1\main_sdram_bankmachine0_row_opened[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine0_row_opened $1\main_sdram_bankmachine0_row_opened[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:543.5-543.44" + process $proc$build/ls180/gateware/ls180.v:543$2760 + assign { } { } + assign $1\main_sdram_bankmachine0_row_open[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine0_row_open $1\main_sdram_bankmachine0_row_open[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:544.5-544.45" + process $proc$build/ls180/gateware/ls180.v:544$2761 + assign { } { } + assign $1\main_sdram_bankmachine0_row_close[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine0_row_close $1\main_sdram_bankmachine0_row_close[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:545.5-545.54" + process $proc$build/ls180/gateware/ls180.v:545$2762 + assign { } { } + assign $1\main_sdram_bankmachine0_row_col_n_addr_sel[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine0_row_col_n_addr_sel $1\main_sdram_bankmachine0_row_col_n_addr_sel[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:5459.1-5466.4" + process $proc$build/ls180/gateware/ls180.v:5459$1035 + assign { } { } + assign { } { } + assign $0\builder_slave_sel[4:0] [0] $eq$build/ls180/gateware/ls180.v:5461$1036_Y + assign $0\builder_slave_sel[4:0] [1] $eq$build/ls180/gateware/ls180.v:5462$1037_Y + assign $0\builder_slave_sel[4:0] [2] $eq$build/ls180/gateware/ls180.v:5463$1038_Y + assign $0\builder_slave_sel[4:0] [3] $eq$build/ls180/gateware/ls180.v:5464$1039_Y + assign $0\builder_slave_sel[4:0] [4] $eq$build/ls180/gateware/ls180.v:5465$1040_Y + sync always + update \builder_slave_sel $0\builder_slave_sel[4:0] + end + attribute \src "build/ls180/gateware/ls180.v:547.32-547.76" + process $proc$build/ls180/gateware/ls180.v:547$2763 + assign { } { } + assign $1\main_sdram_bankmachine0_twtpcon_ready[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine0_twtpcon_ready $1\main_sdram_bankmachine0_twtpcon_ready[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:548.11-548.55" + process $proc$build/ls180/gateware/ls180.v:548$2764 + assign { } { } + assign $1\main_sdram_bankmachine0_twtpcon_count[2:0] 3'000 + sync always + sync init + update \main_sdram_bankmachine0_twtpcon_count $1\main_sdram_bankmachine0_twtpcon_count[2:0] + end + attribute \src "build/ls180/gateware/ls180.v:550.32-550.75" + process $proc$build/ls180/gateware/ls180.v:550$2765 + assign { } { } + assign $0\main_sdram_bankmachine0_trccon_ready[0:0] 1'1 + sync always + update \main_sdram_bankmachine0_trccon_ready $0\main_sdram_bankmachine0_trccon_ready[0:0] + sync init + end + attribute \src "build/ls180/gateware/ls180.v:5509.1-5520.4" + process $proc$build/ls180/gateware/ls180.v:5509$1053 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\builder_error[0:0] 1'0 + assign { } { } + assign $0\builder_shared_ack[0:0] $or$build/ls180/gateware/ls180.v:5513$1057_Y + assign $0\builder_shared_dat_r[31:0] $or$build/ls180/gateware/ls180.v:5514$1066_Y + attribute \src "build/ls180/gateware/ls180.v:5515.2-5519.5" + switch \builder_done + attribute \src "build/ls180/gateware/ls180.v:5515.6-5515.18" + case 1'1 + assign $0\builder_shared_dat_r[31:0] 32'11111111111111111111111111111111 + assign $0\builder_shared_ack[0:0] 1'1 + assign $0\builder_error[0:0] 1'1 + case + end + sync always + update \builder_shared_dat_r $0\builder_shared_dat_r[31:0] + update \builder_shared_ack $0\builder_shared_ack[0:0] + update \builder_error $0\builder_error[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:552.32-552.76" + process $proc$build/ls180/gateware/ls180.v:552$2766 + assign { } { } + assign $0\main_sdram_bankmachine0_trascon_ready[0:0] 1'1 + sync always + update \main_sdram_bankmachine0_trascon_ready $0\main_sdram_bankmachine0_trascon_ready[0:0] + sync init + end + attribute \src "build/ls180/gateware/ls180.v:558.5-558.51" + process $proc$build/ls180/gateware/ls180.v:558$2767 + assign { } { } + assign $1\main_sdram_bankmachine1_req_wdata_ready[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine1_req_wdata_ready $1\main_sdram_bankmachine1_req_wdata_ready[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:559.5-559.51" + process $proc$build/ls180/gateware/ls180.v:559$2768 + assign { } { } + assign $1\main_sdram_bankmachine1_req_rdata_valid[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine1_req_rdata_valid $1\main_sdram_bankmachine1_req_rdata_valid[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:561.5-561.47" + process $proc$build/ls180/gateware/ls180.v:561$2769 + assign { } { } + assign $1\main_sdram_bankmachine1_refresh_gnt[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine1_refresh_gnt $1\main_sdram_bankmachine1_refresh_gnt[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:562.5-562.45" + process $proc$build/ls180/gateware/ls180.v:562$2770 + assign { } { } + assign $1\main_sdram_bankmachine1_cmd_valid[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine1_cmd_valid $1\main_sdram_bankmachine1_cmd_valid[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:563.5-563.45" + process $proc$build/ls180/gateware/ls180.v:563$2771 + assign { } { } + assign $1\main_sdram_bankmachine1_cmd_ready[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine1_cmd_ready $1\main_sdram_bankmachine1_cmd_ready[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:564.12-564.57" + process $proc$build/ls180/gateware/ls180.v:564$2772 + assign { } { } + assign $1\main_sdram_bankmachine1_cmd_payload_a[12:0] 13'0000000000000 + sync always + sync init + update \main_sdram_bankmachine1_cmd_payload_a $1\main_sdram_bankmachine1_cmd_payload_a[12:0] + end + attribute \src "build/ls180/gateware/ls180.v:566.5-566.51" + process $proc$build/ls180/gateware/ls180.v:566$2773 + assign { } { } + assign $1\main_sdram_bankmachine1_cmd_payload_cas[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine1_cmd_payload_cas $1\main_sdram_bankmachine1_cmd_payload_cas[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:567.5-567.51" + process $proc$build/ls180/gateware/ls180.v:567$2774 + assign { } { } + assign $1\main_sdram_bankmachine1_cmd_payload_ras[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine1_cmd_payload_ras $1\main_sdram_bankmachine1_cmd_payload_ras[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:568.5-568.50" + process $proc$build/ls180/gateware/ls180.v:568$2775 + assign { } { } + assign $1\main_sdram_bankmachine1_cmd_payload_we[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine1_cmd_payload_we $1\main_sdram_bankmachine1_cmd_payload_we[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:569.5-569.54" + process $proc$build/ls180/gateware/ls180.v:569$2776 + assign { } { } + assign $1\main_sdram_bankmachine1_cmd_payload_is_cmd[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine1_cmd_payload_is_cmd $1\main_sdram_bankmachine1_cmd_payload_is_cmd[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:570.5-570.55" + process $proc$build/ls180/gateware/ls180.v:570$2777 + assign { } { } + assign $1\main_sdram_bankmachine1_cmd_payload_is_read[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine1_cmd_payload_is_read $1\main_sdram_bankmachine1_cmd_payload_is_read[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:571.5-571.56" + process $proc$build/ls180/gateware/ls180.v:571$2778 + assign { } { } + assign $1\main_sdram_bankmachine1_cmd_payload_is_write[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine1_cmd_payload_is_write $1\main_sdram_bankmachine1_cmd_payload_is_write[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:572.5-572.50" + process $proc$build/ls180/gateware/ls180.v:572$2779 + assign { } { } + assign $1\main_sdram_bankmachine1_auto_precharge[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine1_auto_precharge $1\main_sdram_bankmachine1_auto_precharge[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:575.5-575.67" + process $proc$build/ls180/gateware/ls180.v:575$2780 + assign { } { } + assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_sink_first[0:0] 1'0 + sync always + update \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_first $0\main_sdram_bankmachine1_cmd_buffer_lookahead_sink_first[0:0] + sync init + end + attribute \src "build/ls180/gateware/ls180.v:576.5-576.66" + process $proc$build/ls180/gateware/ls180.v:576$2781 + assign { } { } + assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_sink_last[0:0] 1'0 + sync always + update \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_last $0\main_sdram_bankmachine1_cmd_buffer_lookahead_sink_last[0:0] + sync init + end + attribute \src "build/ls180/gateware/ls180.v:591.11-591.68" + process $proc$build/ls180/gateware/ls180.v:591$2782 + assign { } { } + assign $1\main_sdram_bankmachine1_cmd_buffer_lookahead_level[3:0] 4'0000 + sync always + sync init + update \main_sdram_bankmachine1_cmd_buffer_lookahead_level $1\main_sdram_bankmachine1_cmd_buffer_lookahead_level[3:0] + end + attribute \src "build/ls180/gateware/ls180.v:592.5-592.64" + process $proc$build/ls180/gateware/ls180.v:592$2783 + assign { } { } + assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_replace[0:0] 1'0 + sync always + update \main_sdram_bankmachine1_cmd_buffer_lookahead_replace $0\main_sdram_bankmachine1_cmd_buffer_lookahead_replace[0:0] + sync init + end + attribute \src "build/ls180/gateware/ls180.v:593.11-593.70" + process $proc$build/ls180/gateware/ls180.v:593$2784 + assign { } { } + assign $1\main_sdram_bankmachine1_cmd_buffer_lookahead_produce[2:0] 3'000 + sync always + sync init + update \main_sdram_bankmachine1_cmd_buffer_lookahead_produce $1\main_sdram_bankmachine1_cmd_buffer_lookahead_produce[2:0] + end + attribute \src "build/ls180/gateware/ls180.v:5932.1-5937.4" + process $proc$build/ls180/gateware/ls180.v:5932$1770 + assign { } { } + assign $0\main_start1[0:0] 1'0 + attribute \src "build/ls180/gateware/ls180.v:5934.2-5936.5" + switch \main_control_re + attribute \src "build/ls180/gateware/ls180.v:5934.6-5934.21" + case 1'1 + assign $0\main_start1[0:0] \main_control_storage [0] + case + end + sync always + update \main_start1 $0\main_start1[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:594.11-594.70" + process $proc$build/ls180/gateware/ls180.v:594$2785 + assign { } { } + assign $1\main_sdram_bankmachine1_cmd_buffer_lookahead_consume[2:0] 3'000 + sync always + sync init + update \main_sdram_bankmachine1_cmd_buffer_lookahead_consume $1\main_sdram_bankmachine1_cmd_buffer_lookahead_consume[2:0] + end + attribute \src "build/ls180/gateware/ls180.v:595.11-595.73" + process $proc$build/ls180/gateware/ls180.v:595$2786 + assign { } { } + assign $1\main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr[2:0] 3'000 + sync always + sync init + update \main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr $1\main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr[2:0] + end + attribute \src "build/ls180/gateware/ls180.v:5978.1-5983.4" + process $proc$build/ls180/gateware/ls180.v:5978$1835 + assign { } { } + assign $0\libresocsim_start1[0:0] 1'0 + attribute \src "build/ls180/gateware/ls180.v:5980.2-5982.5" + switch \libresocsim_control_re + attribute \src "build/ls180/gateware/ls180.v:5980.6-5980.28" + case 1'1 + assign $0\libresocsim_start1[0:0] \libresocsim_control_storage [0] + case + end + sync always + update \libresocsim_start1 $0\libresocsim_start1[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:61.5-61.46" + process $proc$build/ls180/gateware/ls180.v:61$2571 + assign { } { } + assign $1\main_libresocsim_libresoc_ibus_ack[0:0] 1'0 + sync always + sync init + update \main_libresocsim_libresoc_ibus_ack $1\main_libresocsim_libresoc_ibus_ack[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:616.5-616.59" + process $proc$build/ls180/gateware/ls180.v:616$2787 + assign { } { } + assign $1\main_sdram_bankmachine1_cmd_buffer_source_valid[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine1_cmd_buffer_source_valid $1\main_sdram_bankmachine1_cmd_buffer_source_valid[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:6161.1-6177.4" + process $proc$build/ls180/gateware/ls180.v:6161$2054 + assign { } { } + assign $0\builder_comb_rhs_array_muxed0[0:0] 1'0 + attribute \src "build/ls180/gateware/ls180.v:6163.2-6176.9" + switch \main_sdram_choose_cmd_grant + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case 2'00 + assign $0\builder_comb_rhs_array_muxed0[0:0] \main_sdram_choose_cmd_valids [0] + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case 2'01 + assign $0\builder_comb_rhs_array_muxed0[0:0] \main_sdram_choose_cmd_valids [1] + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case 2'10 + assign $0\builder_comb_rhs_array_muxed0[0:0] \main_sdram_choose_cmd_valids [2] + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case + assign $0\builder_comb_rhs_array_muxed0[0:0] \main_sdram_choose_cmd_valids [3] + end + sync always + update \builder_comb_rhs_array_muxed0 $0\builder_comb_rhs_array_muxed0[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:6178.1-6194.4" + process $proc$build/ls180/gateware/ls180.v:6178$2055 + assign { } { } + assign $0\builder_comb_rhs_array_muxed1[12:0] 13'0000000000000 + attribute \src "build/ls180/gateware/ls180.v:6180.2-6193.9" + switch \main_sdram_choose_cmd_grant + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case 2'00 + assign $0\builder_comb_rhs_array_muxed1[12:0] \main_sdram_bankmachine0_cmd_payload_a + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case 2'01 + assign $0\builder_comb_rhs_array_muxed1[12:0] \main_sdram_bankmachine1_cmd_payload_a + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case 2'10 + assign $0\builder_comb_rhs_array_muxed1[12:0] \main_sdram_bankmachine2_cmd_payload_a + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case + assign $0\builder_comb_rhs_array_muxed1[12:0] \main_sdram_bankmachine3_cmd_payload_a + end + sync always + update \builder_comb_rhs_array_muxed1 $0\builder_comb_rhs_array_muxed1[12:0] + end + attribute \src "build/ls180/gateware/ls180.v:618.5-618.59" + process $proc$build/ls180/gateware/ls180.v:618$2788 + assign { } { } + assign $1\main_sdram_bankmachine1_cmd_buffer_source_first[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine1_cmd_buffer_source_first $1\main_sdram_bankmachine1_cmd_buffer_source_first[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:619.5-619.58" + process $proc$build/ls180/gateware/ls180.v:619$2789 + assign { } { } + assign $1\main_sdram_bankmachine1_cmd_buffer_source_last[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine1_cmd_buffer_source_last $1\main_sdram_bankmachine1_cmd_buffer_source_last[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:6195.1-6211.4" + process $proc$build/ls180/gateware/ls180.v:6195$2056 + assign { } { } + assign $0\builder_comb_rhs_array_muxed2[1:0] 2'00 + attribute \src "build/ls180/gateware/ls180.v:6197.2-6210.9" + switch \main_sdram_choose_cmd_grant + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case 2'00 + assign $0\builder_comb_rhs_array_muxed2[1:0] \main_sdram_bankmachine0_cmd_payload_ba + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case 2'01 + assign $0\builder_comb_rhs_array_muxed2[1:0] \main_sdram_bankmachine1_cmd_payload_ba + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case 2'10 + assign $0\builder_comb_rhs_array_muxed2[1:0] \main_sdram_bankmachine2_cmd_payload_ba + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case + assign $0\builder_comb_rhs_array_muxed2[1:0] \main_sdram_bankmachine3_cmd_payload_ba + end + sync always + update \builder_comb_rhs_array_muxed2 $0\builder_comb_rhs_array_muxed2[1:0] + end + attribute \src "build/ls180/gateware/ls180.v:620.5-620.64" + process $proc$build/ls180/gateware/ls180.v:620$2790 + assign { } { } + assign $1\main_sdram_bankmachine1_cmd_buffer_source_payload_we[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine1_cmd_buffer_source_payload_we $1\main_sdram_bankmachine1_cmd_buffer_source_payload_we[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:621.12-621.74" + process $proc$build/ls180/gateware/ls180.v:621$2791 + assign { } { } + assign $1\main_sdram_bankmachine1_cmd_buffer_source_payload_addr[21:0] 22'0000000000000000000000 + sync always + sync init + update \main_sdram_bankmachine1_cmd_buffer_source_payload_addr $1\main_sdram_bankmachine1_cmd_buffer_source_payload_addr[21:0] + end + attribute \src "build/ls180/gateware/ls180.v:6212.1-6228.4" + process $proc$build/ls180/gateware/ls180.v:6212$2057 + assign { } { } + assign $0\builder_comb_rhs_array_muxed3[0:0] 1'0 + attribute \src "build/ls180/gateware/ls180.v:6214.2-6227.9" + switch \main_sdram_choose_cmd_grant + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case 2'00 + assign $0\builder_comb_rhs_array_muxed3[0:0] \main_sdram_bankmachine0_cmd_payload_is_read + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case 2'01 + assign $0\builder_comb_rhs_array_muxed3[0:0] \main_sdram_bankmachine1_cmd_payload_is_read + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case 2'10 + assign $0\builder_comb_rhs_array_muxed3[0:0] \main_sdram_bankmachine2_cmd_payload_is_read + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case + assign $0\builder_comb_rhs_array_muxed3[0:0] \main_sdram_bankmachine3_cmd_payload_is_read + end + sync always + update \builder_comb_rhs_array_muxed3 $0\builder_comb_rhs_array_muxed3[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:622.12-622.47" + process $proc$build/ls180/gateware/ls180.v:622$2792 + assign { } { } + assign $1\main_sdram_bankmachine1_row[12:0] 13'0000000000000 + sync always + sync init + update \main_sdram_bankmachine1_row $1\main_sdram_bankmachine1_row[12:0] + end + attribute \src "build/ls180/gateware/ls180.v:6229.1-6245.4" + process $proc$build/ls180/gateware/ls180.v:6229$2058 + assign { } { } + assign $0\builder_comb_rhs_array_muxed4[0:0] 1'0 + attribute \src "build/ls180/gateware/ls180.v:6231.2-6244.9" + switch \main_sdram_choose_cmd_grant + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case 2'00 + assign $0\builder_comb_rhs_array_muxed4[0:0] \main_sdram_bankmachine0_cmd_payload_is_write + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case 2'01 + assign $0\builder_comb_rhs_array_muxed4[0:0] \main_sdram_bankmachine1_cmd_payload_is_write + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case 2'10 + assign $0\builder_comb_rhs_array_muxed4[0:0] \main_sdram_bankmachine2_cmd_payload_is_write + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case + assign $0\builder_comb_rhs_array_muxed4[0:0] \main_sdram_bankmachine3_cmd_payload_is_write + end + sync always + update \builder_comb_rhs_array_muxed4 $0\builder_comb_rhs_array_muxed4[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:623.5-623.46" + process $proc$build/ls180/gateware/ls180.v:623$2793 + assign { } { } + assign $1\main_sdram_bankmachine1_row_opened[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine1_row_opened $1\main_sdram_bankmachine1_row_opened[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:6246.1-6262.4" + process $proc$build/ls180/gateware/ls180.v:6246$2059 + assign { } { } + assign $0\builder_comb_rhs_array_muxed5[0:0] 1'0 + attribute \src "build/ls180/gateware/ls180.v:6248.2-6261.9" + switch \main_sdram_choose_cmd_grant + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case 2'00 + assign $0\builder_comb_rhs_array_muxed5[0:0] \main_sdram_bankmachine0_cmd_payload_is_cmd + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case 2'01 + assign $0\builder_comb_rhs_array_muxed5[0:0] \main_sdram_bankmachine1_cmd_payload_is_cmd + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case 2'10 + assign $0\builder_comb_rhs_array_muxed5[0:0] \main_sdram_bankmachine2_cmd_payload_is_cmd + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case + assign $0\builder_comb_rhs_array_muxed5[0:0] \main_sdram_bankmachine3_cmd_payload_is_cmd + end + sync always + update \builder_comb_rhs_array_muxed5 $0\builder_comb_rhs_array_muxed5[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:625.5-625.44" + process $proc$build/ls180/gateware/ls180.v:625$2794 + assign { } { } + assign $1\main_sdram_bankmachine1_row_open[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine1_row_open $1\main_sdram_bankmachine1_row_open[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:626.5-626.45" + process $proc$build/ls180/gateware/ls180.v:626$2795 + assign { } { } + assign $1\main_sdram_bankmachine1_row_close[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine1_row_close $1\main_sdram_bankmachine1_row_close[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:6263.1-6279.4" + process $proc$build/ls180/gateware/ls180.v:6263$2060 + assign { } { } + assign $0\builder_comb_t_array_muxed0[0:0] 1'0 + attribute \src "build/ls180/gateware/ls180.v:6265.2-6278.9" + switch \main_sdram_choose_cmd_grant + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case 2'00 + assign $0\builder_comb_t_array_muxed0[0:0] \main_sdram_bankmachine0_cmd_payload_cas + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case 2'01 + assign $0\builder_comb_t_array_muxed0[0:0] \main_sdram_bankmachine1_cmd_payload_cas + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case 2'10 + assign $0\builder_comb_t_array_muxed0[0:0] \main_sdram_bankmachine2_cmd_payload_cas + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case + assign $0\builder_comb_t_array_muxed0[0:0] \main_sdram_bankmachine3_cmd_payload_cas + end + sync always + update \builder_comb_t_array_muxed0 $0\builder_comb_t_array_muxed0[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:627.5-627.54" + process $proc$build/ls180/gateware/ls180.v:627$2796 + assign { } { } + assign $1\main_sdram_bankmachine1_row_col_n_addr_sel[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine1_row_col_n_addr_sel $1\main_sdram_bankmachine1_row_col_n_addr_sel[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:6280.1-6296.4" + process $proc$build/ls180/gateware/ls180.v:6280$2061 + assign { } { } + assign $0\builder_comb_t_array_muxed1[0:0] 1'0 + attribute \src "build/ls180/gateware/ls180.v:6282.2-6295.9" + switch \main_sdram_choose_cmd_grant + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case 2'00 + assign $0\builder_comb_t_array_muxed1[0:0] \main_sdram_bankmachine0_cmd_payload_ras + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case 2'01 + assign $0\builder_comb_t_array_muxed1[0:0] \main_sdram_bankmachine1_cmd_payload_ras + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case 2'10 + assign $0\builder_comb_t_array_muxed1[0:0] \main_sdram_bankmachine2_cmd_payload_ras + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case + assign $0\builder_comb_t_array_muxed1[0:0] \main_sdram_bankmachine3_cmd_payload_ras + end + sync always + update \builder_comb_t_array_muxed1 $0\builder_comb_t_array_muxed1[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:629.32-629.76" + process $proc$build/ls180/gateware/ls180.v:629$2797 + assign { } { } + assign $1\main_sdram_bankmachine1_twtpcon_ready[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine1_twtpcon_ready $1\main_sdram_bankmachine1_twtpcon_ready[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:6297.1-6313.4" + process $proc$build/ls180/gateware/ls180.v:6297$2062 + assign { } { } + assign $0\builder_comb_t_array_muxed2[0:0] 1'0 + attribute \src "build/ls180/gateware/ls180.v:6299.2-6312.9" + switch \main_sdram_choose_cmd_grant + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case 2'00 + assign $0\builder_comb_t_array_muxed2[0:0] \main_sdram_bankmachine0_cmd_payload_we + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case 2'01 + assign $0\builder_comb_t_array_muxed2[0:0] \main_sdram_bankmachine1_cmd_payload_we + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case 2'10 + assign $0\builder_comb_t_array_muxed2[0:0] \main_sdram_bankmachine2_cmd_payload_we + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case + assign $0\builder_comb_t_array_muxed2[0:0] \main_sdram_bankmachine3_cmd_payload_we + end + sync always + update \builder_comb_t_array_muxed2 $0\builder_comb_t_array_muxed2[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:630.11-630.55" + process $proc$build/ls180/gateware/ls180.v:630$2798 + assign { } { } + assign $1\main_sdram_bankmachine1_twtpcon_count[2:0] 3'000 + sync always + sync init + update \main_sdram_bankmachine1_twtpcon_count $1\main_sdram_bankmachine1_twtpcon_count[2:0] + end + attribute \src "build/ls180/gateware/ls180.v:6314.1-6330.4" + process $proc$build/ls180/gateware/ls180.v:6314$2063 + assign { } { } + assign $0\builder_comb_rhs_array_muxed6[0:0] 1'0 + attribute \src "build/ls180/gateware/ls180.v:6316.2-6329.9" + switch \main_sdram_choose_req_grant + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case 2'00 + assign $0\builder_comb_rhs_array_muxed6[0:0] \main_sdram_choose_req_valids [0] + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case 2'01 + assign $0\builder_comb_rhs_array_muxed6[0:0] \main_sdram_choose_req_valids [1] + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case 2'10 + assign $0\builder_comb_rhs_array_muxed6[0:0] \main_sdram_choose_req_valids [2] + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case + assign $0\builder_comb_rhs_array_muxed6[0:0] \main_sdram_choose_req_valids [3] + end + sync always + update \builder_comb_rhs_array_muxed6 $0\builder_comb_rhs_array_muxed6[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:632.32-632.75" + process $proc$build/ls180/gateware/ls180.v:632$2799 + assign { } { } + assign $0\main_sdram_bankmachine1_trccon_ready[0:0] 1'1 + sync always + update \main_sdram_bankmachine1_trccon_ready $0\main_sdram_bankmachine1_trccon_ready[0:0] + sync init + end + attribute \src "build/ls180/gateware/ls180.v:6331.1-6347.4" + process $proc$build/ls180/gateware/ls180.v:6331$2064 + assign { } { } + assign $0\builder_comb_rhs_array_muxed7[12:0] 13'0000000000000 + attribute \src "build/ls180/gateware/ls180.v:6333.2-6346.9" + switch \main_sdram_choose_req_grant + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case 2'00 + assign $0\builder_comb_rhs_array_muxed7[12:0] \main_sdram_bankmachine0_cmd_payload_a + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case 2'01 + assign $0\builder_comb_rhs_array_muxed7[12:0] \main_sdram_bankmachine1_cmd_payload_a + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case 2'10 + assign $0\builder_comb_rhs_array_muxed7[12:0] \main_sdram_bankmachine2_cmd_payload_a + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case + assign $0\builder_comb_rhs_array_muxed7[12:0] \main_sdram_bankmachine3_cmd_payload_a + end + sync always + update \builder_comb_rhs_array_muxed7 $0\builder_comb_rhs_array_muxed7[12:0] + end + attribute \src "build/ls180/gateware/ls180.v:634.32-634.76" + process $proc$build/ls180/gateware/ls180.v:634$2800 + assign { } { } + assign $0\main_sdram_bankmachine1_trascon_ready[0:0] 1'1 + sync always + update \main_sdram_bankmachine1_trascon_ready $0\main_sdram_bankmachine1_trascon_ready[0:0] + sync init + end + attribute \src "build/ls180/gateware/ls180.v:6348.1-6364.4" + process $proc$build/ls180/gateware/ls180.v:6348$2065 + assign { } { } + assign $0\builder_comb_rhs_array_muxed8[1:0] 2'00 + attribute \src "build/ls180/gateware/ls180.v:6350.2-6363.9" + switch \main_sdram_choose_req_grant + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case 2'00 + assign $0\builder_comb_rhs_array_muxed8[1:0] \main_sdram_bankmachine0_cmd_payload_ba + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case 2'01 + assign $0\builder_comb_rhs_array_muxed8[1:0] \main_sdram_bankmachine1_cmd_payload_ba + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case 2'10 + assign $0\builder_comb_rhs_array_muxed8[1:0] \main_sdram_bankmachine2_cmd_payload_ba + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case + assign $0\builder_comb_rhs_array_muxed8[1:0] \main_sdram_bankmachine3_cmd_payload_ba + end + sync always + update \builder_comb_rhs_array_muxed8 $0\builder_comb_rhs_array_muxed8[1:0] + end + attribute \src "build/ls180/gateware/ls180.v:6365.1-6381.4" + process $proc$build/ls180/gateware/ls180.v:6365$2066 + assign { } { } + assign $0\builder_comb_rhs_array_muxed9[0:0] 1'0 + attribute \src "build/ls180/gateware/ls180.v:6367.2-6380.9" + switch \main_sdram_choose_req_grant + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case 2'00 + assign $0\builder_comb_rhs_array_muxed9[0:0] \main_sdram_bankmachine0_cmd_payload_is_read + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case 2'01 + assign $0\builder_comb_rhs_array_muxed9[0:0] \main_sdram_bankmachine1_cmd_payload_is_read + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case 2'10 + assign $0\builder_comb_rhs_array_muxed9[0:0] \main_sdram_bankmachine2_cmd_payload_is_read + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case + assign $0\builder_comb_rhs_array_muxed9[0:0] \main_sdram_bankmachine3_cmd_payload_is_read + end + sync always + update \builder_comb_rhs_array_muxed9 $0\builder_comb_rhs_array_muxed9[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:6382.1-6398.4" + process $proc$build/ls180/gateware/ls180.v:6382$2067 + assign { } { } + assign $0\builder_comb_rhs_array_muxed10[0:0] 1'0 + attribute \src "build/ls180/gateware/ls180.v:6384.2-6397.9" + switch \main_sdram_choose_req_grant + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case 2'00 + assign $0\builder_comb_rhs_array_muxed10[0:0] \main_sdram_bankmachine0_cmd_payload_is_write + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case 2'01 + assign $0\builder_comb_rhs_array_muxed10[0:0] \main_sdram_bankmachine1_cmd_payload_is_write + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case 2'10 + assign $0\builder_comb_rhs_array_muxed10[0:0] \main_sdram_bankmachine2_cmd_payload_is_write + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case + assign $0\builder_comb_rhs_array_muxed10[0:0] \main_sdram_bankmachine3_cmd_payload_is_write + end + sync always + update \builder_comb_rhs_array_muxed10 $0\builder_comb_rhs_array_muxed10[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:6399.1-6415.4" + process $proc$build/ls180/gateware/ls180.v:6399$2068 + assign { } { } + assign $0\builder_comb_rhs_array_muxed11[0:0] 1'0 + attribute \src "build/ls180/gateware/ls180.v:6401.2-6414.9" + switch \main_sdram_choose_req_grant + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case 2'00 + assign $0\builder_comb_rhs_array_muxed11[0:0] \main_sdram_bankmachine0_cmd_payload_is_cmd + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case 2'01 + assign $0\builder_comb_rhs_array_muxed11[0:0] \main_sdram_bankmachine1_cmd_payload_is_cmd + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case 2'10 + assign $0\builder_comb_rhs_array_muxed11[0:0] \main_sdram_bankmachine2_cmd_payload_is_cmd + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case + assign $0\builder_comb_rhs_array_muxed11[0:0] \main_sdram_bankmachine3_cmd_payload_is_cmd + end + sync always + update \builder_comb_rhs_array_muxed11 $0\builder_comb_rhs_array_muxed11[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:640.5-640.51" + process $proc$build/ls180/gateware/ls180.v:640$2801 + assign { } { } + assign $1\main_sdram_bankmachine2_req_wdata_ready[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine2_req_wdata_ready $1\main_sdram_bankmachine2_req_wdata_ready[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:641.5-641.51" + process $proc$build/ls180/gateware/ls180.v:641$2802 + assign { } { } + assign $1\main_sdram_bankmachine2_req_rdata_valid[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine2_req_rdata_valid $1\main_sdram_bankmachine2_req_rdata_valid[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:6416.1-6432.4" + process $proc$build/ls180/gateware/ls180.v:6416$2069 + assign { } { } + assign $0\builder_comb_t_array_muxed3[0:0] 1'0 + attribute \src "build/ls180/gateware/ls180.v:6418.2-6431.9" + switch \main_sdram_choose_req_grant + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case 2'00 + assign $0\builder_comb_t_array_muxed3[0:0] \main_sdram_bankmachine0_cmd_payload_cas + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case 2'01 + assign $0\builder_comb_t_array_muxed3[0:0] \main_sdram_bankmachine1_cmd_payload_cas + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case 2'10 + assign $0\builder_comb_t_array_muxed3[0:0] \main_sdram_bankmachine2_cmd_payload_cas + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case + assign $0\builder_comb_t_array_muxed3[0:0] \main_sdram_bankmachine3_cmd_payload_cas + end + sync always + update \builder_comb_t_array_muxed3 $0\builder_comb_t_array_muxed3[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:643.5-643.47" + process $proc$build/ls180/gateware/ls180.v:643$2803 + assign { } { } + assign $1\main_sdram_bankmachine2_refresh_gnt[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine2_refresh_gnt $1\main_sdram_bankmachine2_refresh_gnt[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:6433.1-6449.4" + process $proc$build/ls180/gateware/ls180.v:6433$2070 + assign { } { } + assign $0\builder_comb_t_array_muxed4[0:0] 1'0 + attribute \src "build/ls180/gateware/ls180.v:6435.2-6448.9" + switch \main_sdram_choose_req_grant + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case 2'00 + assign $0\builder_comb_t_array_muxed4[0:0] \main_sdram_bankmachine0_cmd_payload_ras + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case 2'01 + assign $0\builder_comb_t_array_muxed4[0:0] \main_sdram_bankmachine1_cmd_payload_ras + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case 2'10 + assign $0\builder_comb_t_array_muxed4[0:0] \main_sdram_bankmachine2_cmd_payload_ras + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case + assign $0\builder_comb_t_array_muxed4[0:0] \main_sdram_bankmachine3_cmd_payload_ras + end + sync always + update \builder_comb_t_array_muxed4 $0\builder_comb_t_array_muxed4[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:644.5-644.45" + process $proc$build/ls180/gateware/ls180.v:644$2804 + assign { } { } + assign $1\main_sdram_bankmachine2_cmd_valid[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine2_cmd_valid $1\main_sdram_bankmachine2_cmd_valid[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:645.5-645.45" + process $proc$build/ls180/gateware/ls180.v:645$2805 + assign { } { } + assign $1\main_sdram_bankmachine2_cmd_ready[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine2_cmd_ready $1\main_sdram_bankmachine2_cmd_ready[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:6450.1-6466.4" + process $proc$build/ls180/gateware/ls180.v:6450$2071 + assign { } { } + assign $0\builder_comb_t_array_muxed5[0:0] 1'0 + attribute \src "build/ls180/gateware/ls180.v:6452.2-6465.9" + switch \main_sdram_choose_req_grant + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case 2'00 + assign $0\builder_comb_t_array_muxed5[0:0] \main_sdram_bankmachine0_cmd_payload_we + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case 2'01 + assign $0\builder_comb_t_array_muxed5[0:0] \main_sdram_bankmachine1_cmd_payload_we + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case 2'10 + assign $0\builder_comb_t_array_muxed5[0:0] \main_sdram_bankmachine2_cmd_payload_we + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case + assign $0\builder_comb_t_array_muxed5[0:0] \main_sdram_bankmachine3_cmd_payload_we + end + sync always + update \builder_comb_t_array_muxed5 $0\builder_comb_t_array_muxed5[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:646.12-646.57" + process $proc$build/ls180/gateware/ls180.v:646$2806 + assign { } { } + assign $1\main_sdram_bankmachine2_cmd_payload_a[12:0] 13'0000000000000 + sync always + sync init + update \main_sdram_bankmachine2_cmd_payload_a $1\main_sdram_bankmachine2_cmd_payload_a[12:0] + end + attribute \src "build/ls180/gateware/ls180.v:6467.1-6474.4" + process $proc$build/ls180/gateware/ls180.v:6467$2072 + assign { } { } + assign $0\builder_comb_rhs_array_muxed12[21:0] 22'0000000000000000000000 + attribute \src "build/ls180/gateware/ls180.v:6469.2-6473.9" + switch \builder_roundrobin0_grant + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case + assign $0\builder_comb_rhs_array_muxed12[21:0] { \main_port_cmd_payload_addr [23:11] \main_port_cmd_payload_addr [8:0] } + end + sync always + update \builder_comb_rhs_array_muxed12 $0\builder_comb_rhs_array_muxed12[21:0] + end + attribute \src "build/ls180/gateware/ls180.v:6475.1-6482.4" + process $proc$build/ls180/gateware/ls180.v:6475$2073 + assign { } { } + assign $0\builder_comb_rhs_array_muxed13[0:0] 1'0 + attribute \src "build/ls180/gateware/ls180.v:6477.2-6481.9" + switch \builder_roundrobin0_grant + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case + assign $0\builder_comb_rhs_array_muxed13[0:0] \main_port_cmd_payload_we + end + sync always + update \builder_comb_rhs_array_muxed13 $0\builder_comb_rhs_array_muxed13[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:648.5-648.51" + process $proc$build/ls180/gateware/ls180.v:648$2807 + assign { } { } + assign $1\main_sdram_bankmachine2_cmd_payload_cas[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine2_cmd_payload_cas $1\main_sdram_bankmachine2_cmd_payload_cas[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:6483.1-6490.4" + process $proc$build/ls180/gateware/ls180.v:6483$2074 + assign { } { } + assign $0\builder_comb_rhs_array_muxed14[0:0] 1'0 + attribute \src "build/ls180/gateware/ls180.v:6485.2-6489.9" + switch \builder_roundrobin0_grant + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case + assign $0\builder_comb_rhs_array_muxed14[0:0] $and$build/ls180/gateware/ls180.v:6487$2087_Y + end + sync always + update \builder_comb_rhs_array_muxed14 $0\builder_comb_rhs_array_muxed14[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:649.5-649.51" + process $proc$build/ls180/gateware/ls180.v:649$2808 + assign { } { } + assign $1\main_sdram_bankmachine2_cmd_payload_ras[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine2_cmd_payload_ras $1\main_sdram_bankmachine2_cmd_payload_ras[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:6491.1-6498.4" + process $proc$build/ls180/gateware/ls180.v:6491$2088 + assign { } { } + assign $0\builder_comb_rhs_array_muxed15[21:0] 22'0000000000000000000000 + attribute \src "build/ls180/gateware/ls180.v:6493.2-6497.9" + switch \builder_roundrobin1_grant + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case + assign $0\builder_comb_rhs_array_muxed15[21:0] { \main_port_cmd_payload_addr [23:11] \main_port_cmd_payload_addr [8:0] } + end + sync always + update \builder_comb_rhs_array_muxed15 $0\builder_comb_rhs_array_muxed15[21:0] + end + attribute \src "build/ls180/gateware/ls180.v:6499.1-6506.4" + process $proc$build/ls180/gateware/ls180.v:6499$2089 + assign { } { } + assign $0\builder_comb_rhs_array_muxed16[0:0] 1'0 + attribute \src "build/ls180/gateware/ls180.v:6501.2-6505.9" + switch \builder_roundrobin1_grant + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case + assign $0\builder_comb_rhs_array_muxed16[0:0] \main_port_cmd_payload_we + end + sync always + update \builder_comb_rhs_array_muxed16 $0\builder_comb_rhs_array_muxed16[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:65.5-65.46" + process $proc$build/ls180/gateware/ls180.v:65$2572 + assign { } { } + assign $0\main_libresocsim_libresoc_ibus_err[0:0] 1'0 + sync always + update \main_libresocsim_libresoc_ibus_err $0\main_libresocsim_libresoc_ibus_err[0:0] + sync init + end + attribute \src "build/ls180/gateware/ls180.v:650.5-650.50" + process $proc$build/ls180/gateware/ls180.v:650$2809 + assign { } { } + assign $1\main_sdram_bankmachine2_cmd_payload_we[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine2_cmd_payload_we $1\main_sdram_bankmachine2_cmd_payload_we[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:6507.1-6514.4" + process $proc$build/ls180/gateware/ls180.v:6507$2090 + assign { } { } + assign $0\builder_comb_rhs_array_muxed17[0:0] 1'0 + attribute \src "build/ls180/gateware/ls180.v:6509.2-6513.9" + switch \builder_roundrobin1_grant + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case + assign $0\builder_comb_rhs_array_muxed17[0:0] $and$build/ls180/gateware/ls180.v:6511$2103_Y + end + sync always + update \builder_comb_rhs_array_muxed17 $0\builder_comb_rhs_array_muxed17[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:651.5-651.54" + process $proc$build/ls180/gateware/ls180.v:651$2810 + assign { } { } + assign $1\main_sdram_bankmachine2_cmd_payload_is_cmd[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine2_cmd_payload_is_cmd $1\main_sdram_bankmachine2_cmd_payload_is_cmd[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:6515.1-6522.4" + process $proc$build/ls180/gateware/ls180.v:6515$2104 + assign { } { } + assign $0\builder_comb_rhs_array_muxed18[21:0] 22'0000000000000000000000 + attribute \src "build/ls180/gateware/ls180.v:6517.2-6521.9" + switch \builder_roundrobin2_grant + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case + assign $0\builder_comb_rhs_array_muxed18[21:0] { \main_port_cmd_payload_addr [23:11] \main_port_cmd_payload_addr [8:0] } + end + sync always + update \builder_comb_rhs_array_muxed18 $0\builder_comb_rhs_array_muxed18[21:0] + end + attribute \src "build/ls180/gateware/ls180.v:652.5-652.55" + process $proc$build/ls180/gateware/ls180.v:652$2811 + assign { } { } + assign $1\main_sdram_bankmachine2_cmd_payload_is_read[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine2_cmd_payload_is_read $1\main_sdram_bankmachine2_cmd_payload_is_read[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:6523.1-6530.4" + process $proc$build/ls180/gateware/ls180.v:6523$2105 + assign { } { } + assign $0\builder_comb_rhs_array_muxed19[0:0] 1'0 + attribute \src "build/ls180/gateware/ls180.v:6525.2-6529.9" + switch \builder_roundrobin2_grant + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case + assign $0\builder_comb_rhs_array_muxed19[0:0] \main_port_cmd_payload_we + end + sync always + update \builder_comb_rhs_array_muxed19 $0\builder_comb_rhs_array_muxed19[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:653.5-653.56" + process $proc$build/ls180/gateware/ls180.v:653$2812 + assign { } { } + assign $1\main_sdram_bankmachine2_cmd_payload_is_write[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine2_cmd_payload_is_write $1\main_sdram_bankmachine2_cmd_payload_is_write[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:6531.1-6538.4" + process $proc$build/ls180/gateware/ls180.v:6531$2106 + assign { } { } + assign $0\builder_comb_rhs_array_muxed20[0:0] 1'0 + attribute \src "build/ls180/gateware/ls180.v:6533.2-6537.9" + switch \builder_roundrobin2_grant + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case + assign $0\builder_comb_rhs_array_muxed20[0:0] $and$build/ls180/gateware/ls180.v:6535$2119_Y + end + sync always + update \builder_comb_rhs_array_muxed20 $0\builder_comb_rhs_array_muxed20[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:6539.1-6546.4" + process $proc$build/ls180/gateware/ls180.v:6539$2120 + assign { } { } + assign $0\builder_comb_rhs_array_muxed21[21:0] 22'0000000000000000000000 + attribute \src "build/ls180/gateware/ls180.v:6541.2-6545.9" + switch \builder_roundrobin3_grant + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case + assign $0\builder_comb_rhs_array_muxed21[21:0] { \main_port_cmd_payload_addr [23:11] \main_port_cmd_payload_addr [8:0] } + end + sync always + update \builder_comb_rhs_array_muxed21 $0\builder_comb_rhs_array_muxed21[21:0] + end + attribute \src "build/ls180/gateware/ls180.v:654.5-654.50" + process $proc$build/ls180/gateware/ls180.v:654$2813 + assign { } { } + assign $1\main_sdram_bankmachine2_auto_precharge[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine2_auto_precharge $1\main_sdram_bankmachine2_auto_precharge[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:6547.1-6554.4" + process $proc$build/ls180/gateware/ls180.v:6547$2121 + assign { } { } + assign $0\builder_comb_rhs_array_muxed22[0:0] 1'0 + attribute \src "build/ls180/gateware/ls180.v:6549.2-6553.9" + switch \builder_roundrobin3_grant + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case + assign $0\builder_comb_rhs_array_muxed22[0:0] \main_port_cmd_payload_we + end + sync always + update \builder_comb_rhs_array_muxed22 $0\builder_comb_rhs_array_muxed22[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:6555.1-6562.4" + process $proc$build/ls180/gateware/ls180.v:6555$2122 + assign { } { } + assign $0\builder_comb_rhs_array_muxed23[0:0] 1'0 + attribute \src "build/ls180/gateware/ls180.v:6557.2-6561.9" + switch \builder_roundrobin3_grant + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case + assign $0\builder_comb_rhs_array_muxed23[0:0] $and$build/ls180/gateware/ls180.v:6559$2135_Y + end + sync always + update \builder_comb_rhs_array_muxed23 $0\builder_comb_rhs_array_muxed23[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:6563.1-6579.4" + process $proc$build/ls180/gateware/ls180.v:6563$2136 + assign { } { } + assign $0\builder_comb_rhs_array_muxed24[31:0] 0 + attribute \src "build/ls180/gateware/ls180.v:6565.2-6578.9" + switch \builder_grant + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case 2'00 + assign $0\builder_comb_rhs_array_muxed24[31:0] { 2'00 \main_libresocsim_interface0_converted_interface_adr } + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case 2'01 + assign $0\builder_comb_rhs_array_muxed24[31:0] { 2'00 \main_libresocsim_interface1_converted_interface_adr } + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case 2'10 + assign $0\builder_comb_rhs_array_muxed24[31:0] \libresocsim_interface0_bus_adr + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case + assign $0\builder_comb_rhs_array_muxed24[31:0] \libresocsim_interface1_bus_adr + end + sync always + update \builder_comb_rhs_array_muxed24 $0\builder_comb_rhs_array_muxed24[31:0] + end + attribute \src "build/ls180/gateware/ls180.v:657.5-657.67" + process $proc$build/ls180/gateware/ls180.v:657$2814 + assign { } { } + assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_sink_first[0:0] 1'0 + sync always + update \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_first $0\main_sdram_bankmachine2_cmd_buffer_lookahead_sink_first[0:0] + sync init + end + attribute \src "build/ls180/gateware/ls180.v:658.5-658.66" + process $proc$build/ls180/gateware/ls180.v:658$2815 + assign { } { } + assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_sink_last[0:0] 1'0 + sync always + update \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_last $0\main_sdram_bankmachine2_cmd_buffer_lookahead_sink_last[0:0] + sync init + end + attribute \src "build/ls180/gateware/ls180.v:6580.1-6596.4" + process $proc$build/ls180/gateware/ls180.v:6580$2137 + assign { } { } + assign $0\builder_comb_rhs_array_muxed25[31:0] 0 + attribute \src "build/ls180/gateware/ls180.v:6582.2-6595.9" + switch \builder_grant + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case 2'00 + assign $0\builder_comb_rhs_array_muxed25[31:0] \main_libresocsim_interface0_converted_interface_dat_w + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case 2'01 + assign $0\builder_comb_rhs_array_muxed25[31:0] \main_libresocsim_interface1_converted_interface_dat_w + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case 2'10 + assign $0\builder_comb_rhs_array_muxed25[31:0] \libresocsim_interface0_bus_dat_w + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case + assign $0\builder_comb_rhs_array_muxed25[31:0] \libresocsim_interface1_bus_dat_w + end + sync always + update \builder_comb_rhs_array_muxed25 $0\builder_comb_rhs_array_muxed25[31:0] + end + attribute \src "build/ls180/gateware/ls180.v:6597.1-6613.4" + process $proc$build/ls180/gateware/ls180.v:6597$2138 + assign { } { } + assign $0\builder_comb_rhs_array_muxed26[3:0] 4'0000 + attribute \src "build/ls180/gateware/ls180.v:6599.2-6612.9" + switch \builder_grant + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case 2'00 + assign $0\builder_comb_rhs_array_muxed26[3:0] \main_libresocsim_interface0_converted_interface_sel + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case 2'01 + assign $0\builder_comb_rhs_array_muxed26[3:0] \main_libresocsim_interface1_converted_interface_sel + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case 2'10 + assign $0\builder_comb_rhs_array_muxed26[3:0] \libresocsim_interface0_bus_sel + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case + assign $0\builder_comb_rhs_array_muxed26[3:0] \libresocsim_interface1_bus_sel + end + sync always + update \builder_comb_rhs_array_muxed26 $0\builder_comb_rhs_array_muxed26[3:0] + end + attribute \src "build/ls180/gateware/ls180.v:6614.1-6630.4" + process $proc$build/ls180/gateware/ls180.v:6614$2139 + assign { } { } + assign $0\builder_comb_rhs_array_muxed27[0:0] 1'0 + attribute \src "build/ls180/gateware/ls180.v:6616.2-6629.9" + switch \builder_grant + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case 2'00 + assign $0\builder_comb_rhs_array_muxed27[0:0] \main_libresocsim_interface0_converted_interface_cyc + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case 2'01 + assign $0\builder_comb_rhs_array_muxed27[0:0] \main_libresocsim_interface1_converted_interface_cyc + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case 2'10 + assign $0\builder_comb_rhs_array_muxed27[0:0] \libresocsim_interface0_bus_cyc + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case + assign $0\builder_comb_rhs_array_muxed27[0:0] \libresocsim_interface1_bus_cyc + end + sync always + update \builder_comb_rhs_array_muxed27 $0\builder_comb_rhs_array_muxed27[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:6631.1-6647.4" + process $proc$build/ls180/gateware/ls180.v:6631$2140 + assign { } { } + assign $0\builder_comb_rhs_array_muxed28[0:0] 1'0 + attribute \src "build/ls180/gateware/ls180.v:6633.2-6646.9" + switch \builder_grant + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case 2'00 + assign $0\builder_comb_rhs_array_muxed28[0:0] \main_libresocsim_interface0_converted_interface_stb + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case 2'01 + assign $0\builder_comb_rhs_array_muxed28[0:0] \main_libresocsim_interface1_converted_interface_stb + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case 2'10 + assign $0\builder_comb_rhs_array_muxed28[0:0] \libresocsim_interface0_bus_stb + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case + assign $0\builder_comb_rhs_array_muxed28[0:0] \libresocsim_interface1_bus_stb + end + sync always + update \builder_comb_rhs_array_muxed28 $0\builder_comb_rhs_array_muxed28[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:6648.1-6664.4" + process $proc$build/ls180/gateware/ls180.v:6648$2141 + assign { } { } + assign $0\builder_comb_rhs_array_muxed29[0:0] 1'0 + attribute \src "build/ls180/gateware/ls180.v:6650.2-6663.9" + switch \builder_grant + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case 2'00 + assign $0\builder_comb_rhs_array_muxed29[0:0] \main_libresocsim_interface0_converted_interface_we + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case 2'01 + assign $0\builder_comb_rhs_array_muxed29[0:0] \main_libresocsim_interface1_converted_interface_we + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case 2'10 + assign $0\builder_comb_rhs_array_muxed29[0:0] \libresocsim_interface0_bus_we + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case + assign $0\builder_comb_rhs_array_muxed29[0:0] \libresocsim_interface1_bus_we + end + sync always + update \builder_comb_rhs_array_muxed29 $0\builder_comb_rhs_array_muxed29[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:6665.1-6681.4" + process $proc$build/ls180/gateware/ls180.v:6665$2142 + assign { } { } + assign $0\builder_comb_rhs_array_muxed30[2:0] 3'000 + attribute \src "build/ls180/gateware/ls180.v:6667.2-6680.9" + switch \builder_grant + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case 2'00 + assign $0\builder_comb_rhs_array_muxed30[2:0] \main_libresocsim_interface0_converted_interface_cti + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case 2'01 + assign $0\builder_comb_rhs_array_muxed30[2:0] \main_libresocsim_interface1_converted_interface_cti + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case 2'10 + assign $0\builder_comb_rhs_array_muxed30[2:0] \libresocsim_interface0_bus_cti + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case + assign $0\builder_comb_rhs_array_muxed30[2:0] \libresocsim_interface1_bus_cti + end + sync always + update \builder_comb_rhs_array_muxed30 $0\builder_comb_rhs_array_muxed30[2:0] + end + attribute \src "build/ls180/gateware/ls180.v:6682.1-6698.4" + process $proc$build/ls180/gateware/ls180.v:6682$2143 + assign { } { } + assign $0\builder_comb_rhs_array_muxed31[1:0] 2'00 + attribute \src "build/ls180/gateware/ls180.v:6684.2-6697.9" + switch \builder_grant + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case 2'00 + assign $0\builder_comb_rhs_array_muxed31[1:0] \main_libresocsim_interface0_converted_interface_bte + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case 2'01 + assign $0\builder_comb_rhs_array_muxed31[1:0] \main_libresocsim_interface1_converted_interface_bte + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case 2'10 + assign $0\builder_comb_rhs_array_muxed31[1:0] \libresocsim_interface0_bus_bte + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case + assign $0\builder_comb_rhs_array_muxed31[1:0] \libresocsim_interface1_bus_bte + end + sync always + update \builder_comb_rhs_array_muxed31 $0\builder_comb_rhs_array_muxed31[1:0] + end + attribute \src "build/ls180/gateware/ls180.v:6699.1-6715.4" + process $proc$build/ls180/gateware/ls180.v:6699$2144 + assign { } { } + assign $0\builder_sync_rhs_array_muxed0[1:0] 2'00 + attribute \src "build/ls180/gateware/ls180.v:6701.2-6714.9" + switch \main_sdram_steerer_sel + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case 2'00 + assign $0\builder_sync_rhs_array_muxed0[1:0] \main_sdram_nop_ba + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case 2'01 + assign $0\builder_sync_rhs_array_muxed0[1:0] \main_sdram_choose_req_cmd_payload_ba + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case 2'10 + assign $0\builder_sync_rhs_array_muxed0[1:0] \main_sdram_choose_req_cmd_payload_ba + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case + assign $0\builder_sync_rhs_array_muxed0[1:0] \main_sdram_cmd_payload_ba + end + sync always + update \builder_sync_rhs_array_muxed0 $0\builder_sync_rhs_array_muxed0[1:0] + end + attribute \src "build/ls180/gateware/ls180.v:6716.1-6732.4" + process $proc$build/ls180/gateware/ls180.v:6716$2145 + assign { } { } + assign $0\builder_sync_rhs_array_muxed1[12:0] 13'0000000000000 + attribute \src "build/ls180/gateware/ls180.v:6718.2-6731.9" + switch \main_sdram_steerer_sel + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case 2'00 + assign $0\builder_sync_rhs_array_muxed1[12:0] \main_sdram_nop_a + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case 2'01 + assign $0\builder_sync_rhs_array_muxed1[12:0] \main_sdram_choose_req_cmd_payload_a + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case 2'10 + assign $0\builder_sync_rhs_array_muxed1[12:0] \main_sdram_choose_req_cmd_payload_a + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case + assign $0\builder_sync_rhs_array_muxed1[12:0] \main_sdram_cmd_payload_a + end + sync always + update \builder_sync_rhs_array_muxed1 $0\builder_sync_rhs_array_muxed1[12:0] + end + attribute \src "build/ls180/gateware/ls180.v:673.11-673.68" + process $proc$build/ls180/gateware/ls180.v:673$2816 + assign { } { } + assign $1\main_sdram_bankmachine2_cmd_buffer_lookahead_level[3:0] 4'0000 + sync always + sync init + update \main_sdram_bankmachine2_cmd_buffer_lookahead_level $1\main_sdram_bankmachine2_cmd_buffer_lookahead_level[3:0] + end + attribute \src "build/ls180/gateware/ls180.v:6733.1-6749.4" + process $proc$build/ls180/gateware/ls180.v:6733$2146 + assign { } { } + assign $0\builder_sync_rhs_array_muxed2[0:0] 1'0 + attribute \src "build/ls180/gateware/ls180.v:6735.2-6748.9" + switch \main_sdram_steerer_sel + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case 2'00 + assign $0\builder_sync_rhs_array_muxed2[0:0] 1'0 + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case 2'01 + assign $0\builder_sync_rhs_array_muxed2[0:0] $and$build/ls180/gateware/ls180.v:6740$2148_Y + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case 2'10 + assign $0\builder_sync_rhs_array_muxed2[0:0] $and$build/ls180/gateware/ls180.v:6743$2150_Y + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case + assign $0\builder_sync_rhs_array_muxed2[0:0] $and$build/ls180/gateware/ls180.v:6746$2152_Y + end + sync always + update \builder_sync_rhs_array_muxed2 $0\builder_sync_rhs_array_muxed2[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:674.5-674.64" + process $proc$build/ls180/gateware/ls180.v:674$2817 + assign { } { } + assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_replace[0:0] 1'0 + sync always + update \main_sdram_bankmachine2_cmd_buffer_lookahead_replace $0\main_sdram_bankmachine2_cmd_buffer_lookahead_replace[0:0] + sync init + end + attribute \src "build/ls180/gateware/ls180.v:675.11-675.70" + process $proc$build/ls180/gateware/ls180.v:675$2818 + assign { } { } + assign $1\main_sdram_bankmachine2_cmd_buffer_lookahead_produce[2:0] 3'000 + sync always + sync init + update \main_sdram_bankmachine2_cmd_buffer_lookahead_produce $1\main_sdram_bankmachine2_cmd_buffer_lookahead_produce[2:0] + end + attribute \src "build/ls180/gateware/ls180.v:6750.1-6766.4" + process $proc$build/ls180/gateware/ls180.v:6750$2153 + assign { } { } + assign $0\builder_sync_rhs_array_muxed3[0:0] 1'0 + attribute \src "build/ls180/gateware/ls180.v:6752.2-6765.9" + switch \main_sdram_steerer_sel + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case 2'00 + assign $0\builder_sync_rhs_array_muxed3[0:0] 1'0 + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case 2'01 + assign $0\builder_sync_rhs_array_muxed3[0:0] $and$build/ls180/gateware/ls180.v:6757$2155_Y + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case 2'10 + assign $0\builder_sync_rhs_array_muxed3[0:0] $and$build/ls180/gateware/ls180.v:6760$2157_Y + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case + assign $0\builder_sync_rhs_array_muxed3[0:0] $and$build/ls180/gateware/ls180.v:6763$2159_Y + end + sync always + update \builder_sync_rhs_array_muxed3 $0\builder_sync_rhs_array_muxed3[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:676.11-676.70" + process $proc$build/ls180/gateware/ls180.v:676$2819 + assign { } { } + assign $1\main_sdram_bankmachine2_cmd_buffer_lookahead_consume[2:0] 3'000 + sync always + sync init + update \main_sdram_bankmachine2_cmd_buffer_lookahead_consume $1\main_sdram_bankmachine2_cmd_buffer_lookahead_consume[2:0] + end + attribute \src "build/ls180/gateware/ls180.v:6767.1-6783.4" + process $proc$build/ls180/gateware/ls180.v:6767$2160 + assign { } { } + assign $0\builder_sync_rhs_array_muxed4[0:0] 1'0 + attribute \src "build/ls180/gateware/ls180.v:6769.2-6782.9" + switch \main_sdram_steerer_sel + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case 2'00 + assign $0\builder_sync_rhs_array_muxed4[0:0] 1'0 + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case 2'01 + assign $0\builder_sync_rhs_array_muxed4[0:0] $and$build/ls180/gateware/ls180.v:6774$2162_Y + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case 2'10 + assign $0\builder_sync_rhs_array_muxed4[0:0] $and$build/ls180/gateware/ls180.v:6777$2164_Y + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case + assign $0\builder_sync_rhs_array_muxed4[0:0] $and$build/ls180/gateware/ls180.v:6780$2166_Y + end + sync always + update \builder_sync_rhs_array_muxed4 $0\builder_sync_rhs_array_muxed4[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:677.11-677.73" + process $proc$build/ls180/gateware/ls180.v:677$2820 + assign { } { } + assign $1\main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr[2:0] 3'000 + sync always + sync init + update \main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr $1\main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr[2:0] + end + attribute \src "build/ls180/gateware/ls180.v:6784.1-6800.4" + process $proc$build/ls180/gateware/ls180.v:6784$2167 + assign { } { } + assign $0\builder_sync_rhs_array_muxed5[0:0] 1'0 + attribute \src "build/ls180/gateware/ls180.v:6786.2-6799.9" + switch \main_sdram_steerer_sel + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case 2'00 + assign $0\builder_sync_rhs_array_muxed5[0:0] 1'0 + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case 2'01 + assign $0\builder_sync_rhs_array_muxed5[0:0] $and$build/ls180/gateware/ls180.v:6791$2169_Y + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case 2'10 + assign $0\builder_sync_rhs_array_muxed5[0:0] $and$build/ls180/gateware/ls180.v:6794$2171_Y + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case + assign $0\builder_sync_rhs_array_muxed5[0:0] $and$build/ls180/gateware/ls180.v:6797$2173_Y + end + sync always + update \builder_sync_rhs_array_muxed5 $0\builder_sync_rhs_array_muxed5[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:68.12-68.60" + process $proc$build/ls180/gateware/ls180.v:68$2573 + assign { } { } + assign $0\main_libresocsim_libresoc_xics_icp_dat_r[31:0] 0 + sync always + update \main_libresocsim_libresoc_xics_icp_dat_r $0\main_libresocsim_libresoc_xics_icp_dat_r[31:0] + sync init + end + attribute \src "build/ls180/gateware/ls180.v:6801.1-6817.4" + process $proc$build/ls180/gateware/ls180.v:6801$2174 + assign { } { } + assign $0\builder_sync_rhs_array_muxed6[0:0] 1'0 + attribute \src "build/ls180/gateware/ls180.v:6803.2-6816.9" + switch \main_sdram_steerer_sel + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case 2'00 + assign $0\builder_sync_rhs_array_muxed6[0:0] 1'0 + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case 2'01 + assign $0\builder_sync_rhs_array_muxed6[0:0] $and$build/ls180/gateware/ls180.v:6808$2176_Y + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case 2'10 + assign $0\builder_sync_rhs_array_muxed6[0:0] $and$build/ls180/gateware/ls180.v:6811$2178_Y + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case + assign $0\builder_sync_rhs_array_muxed6[0:0] $and$build/ls180/gateware/ls180.v:6814$2180_Y + end + sync always + update \builder_sync_rhs_array_muxed6 $0\builder_sync_rhs_array_muxed6[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:6818.1-6846.4" + process $proc$build/ls180/gateware/ls180.v:6818$2181 + assign { } { } + assign $0\builder_sync_f_array_muxed0[0:0] 1'0 + attribute \src "build/ls180/gateware/ls180.v:6820.2-6845.9" + switch \main_mosi_sel + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case 3'000 + assign $0\builder_sync_f_array_muxed0[0:0] \main_mosi_data [0] + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case 3'001 + assign $0\builder_sync_f_array_muxed0[0:0] \main_mosi_data [1] + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case 3'010 + assign $0\builder_sync_f_array_muxed0[0:0] \main_mosi_data [2] + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case 3'011 + assign $0\builder_sync_f_array_muxed0[0:0] \main_mosi_data [3] + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case 3'100 + assign $0\builder_sync_f_array_muxed0[0:0] \main_mosi_data [4] + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case 3'101 + assign $0\builder_sync_f_array_muxed0[0:0] \main_mosi_data [5] + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case 3'110 + assign $0\builder_sync_f_array_muxed0[0:0] \main_mosi_data [6] + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case + assign $0\builder_sync_f_array_muxed0[0:0] \main_mosi_data [7] + end + sync always + update \builder_sync_f_array_muxed0 $0\builder_sync_f_array_muxed0[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:6847.1-6875.4" + process $proc$build/ls180/gateware/ls180.v:6847$2182 + assign { } { } + assign $0\builder_sync_f_array_muxed1[0:0] 1'0 + attribute \src "build/ls180/gateware/ls180.v:6849.2-6874.9" + switch \libresocsim_mosi_sel + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case 3'000 + assign $0\builder_sync_f_array_muxed1[0:0] \libresocsim_mosi_data [0] + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case 3'001 + assign $0\builder_sync_f_array_muxed1[0:0] \libresocsim_mosi_data [1] + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case 3'010 + assign $0\builder_sync_f_array_muxed1[0:0] \libresocsim_mosi_data [2] + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case 3'011 + assign $0\builder_sync_f_array_muxed1[0:0] \libresocsim_mosi_data [3] + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case 3'100 + assign $0\builder_sync_f_array_muxed1[0:0] \libresocsim_mosi_data [4] + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case 3'101 + assign $0\builder_sync_f_array_muxed1[0:0] \libresocsim_mosi_data [5] + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case 3'110 + assign $0\builder_sync_f_array_muxed1[0:0] \libresocsim_mosi_data [6] + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case + assign $0\builder_sync_f_array_muxed1[0:0] \libresocsim_mosi_data [7] + end + sync always + update \builder_sync_f_array_muxed1 $0\builder_sync_f_array_muxed1[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:6964.1-6966.4" + process $proc$build/ls180/gateware/ls180.v:6964$2183 + assign { } { } + assign $0\main_int_rst[0:0] 1'0 + sync posedge \por_clk + update \main_int_rst $0\main_int_rst[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:6968.1-7053.4" + process $proc$build/ls180/gateware/ls180.v:6968$2184 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\sdram_a[12:0] [0] \main_dfi_p0_address [0] + assign $0\sdram_a[12:0] [1] \main_dfi_p0_address [1] + assign $0\sdram_a[12:0] [2] \main_dfi_p0_address [2] + assign $0\sdram_a[12:0] [3] \main_dfi_p0_address [3] + assign $0\sdram_a[12:0] [4] \main_dfi_p0_address [4] + assign $0\sdram_a[12:0] [5] \main_dfi_p0_address [5] + assign $0\sdram_a[12:0] [6] \main_dfi_p0_address [6] + assign $0\sdram_a[12:0] [7] \main_dfi_p0_address [7] + assign $0\sdram_a[12:0] [8] \main_dfi_p0_address [8] + assign $0\sdram_a[12:0] [9] \main_dfi_p0_address [9] + assign $0\sdram_a[12:0] [10] \main_dfi_p0_address [10] + assign $0\sdram_a[12:0] [11] \main_dfi_p0_address [11] + assign $0\sdram_a[12:0] [12] \main_dfi_p0_address [12] + assign $0\sdram_ba[1:0] [0] \main_dfi_p0_bank [0] + assign $0\sdram_ba[1:0] [1] \main_dfi_p0_bank [1] + assign $0\sdram_cas_n[0:0] \main_dfi_p0_cas_n + assign $0\sdram_ras_n[0:0] \main_dfi_p0_ras_n + assign $0\sdram_we_n[0:0] \main_dfi_p0_we_n + assign $0\sdram_cke[0:0] \main_dfi_p0_cke + assign $0\sdram_cs_n[0:0] \main_dfi_p0_cs_n + assign $0\builder_inferedsdrtristate0_oe[0:0] \main_dfi_p0_wrdata_en + assign $0\builder_inferedsdrtristate1_oe[0:0] \main_dfi_p0_wrdata_en + assign $0\builder_inferedsdrtristate2_oe[0:0] \main_dfi_p0_wrdata_en + assign $0\builder_inferedsdrtristate3_oe[0:0] \main_dfi_p0_wrdata_en + assign $0\builder_inferedsdrtristate4_oe[0:0] \main_dfi_p0_wrdata_en + assign $0\builder_inferedsdrtristate5_oe[0:0] \main_dfi_p0_wrdata_en + assign $0\builder_inferedsdrtristate6_oe[0:0] \main_dfi_p0_wrdata_en + assign $0\builder_inferedsdrtristate7_oe[0:0] \main_dfi_p0_wrdata_en + assign $0\builder_inferedsdrtristate8_oe[0:0] \main_dfi_p0_wrdata_en + assign $0\builder_inferedsdrtristate9_oe[0:0] \main_dfi_p0_wrdata_en + assign $0\builder_inferedsdrtristate10_oe[0:0] \main_dfi_p0_wrdata_en + assign $0\builder_inferedsdrtristate11_oe[0:0] \main_dfi_p0_wrdata_en + assign $0\builder_inferedsdrtristate12_oe[0:0] \main_dfi_p0_wrdata_en + assign $0\builder_inferedsdrtristate13_oe[0:0] \main_dfi_p0_wrdata_en + assign $0\builder_inferedsdrtristate14_oe[0:0] \main_dfi_p0_wrdata_en + assign $0\builder_inferedsdrtristate15_oe[0:0] \main_dfi_p0_wrdata_en + assign $0\sdcard_clk[0:0] $and$build/ls180/gateware/ls180.v:7005$2186_Y + assign $0\builder_inferedsdrtristate16_oe[0:0] \libresocsim_sdpads_cmd_oe + assign $0\builder_inferedsdrtristate17_oe[0:0] \libresocsim_sdpads_data_oe + assign $0\builder_inferedsdrtristate18_oe[0:0] \libresocsim_sdpads_data_oe + assign $0\builder_inferedsdrtristate19_oe[0:0] \libresocsim_sdpads_data_oe + assign $0\builder_inferedsdrtristate20_oe[0:0] \libresocsim_sdpads_data_oe + assign $0\builder_inferedsdrtristate0__o[0:0] \main_dfi_p0_wrdata [0] + assign $0\main_dfi_p0_rddata[15:0] [0] \builder_inferedsdrtristate0__i + assign $0\builder_inferedsdrtristate1__o[0:0] \main_dfi_p0_wrdata [1] + assign $0\main_dfi_p0_rddata[15:0] [1] \builder_inferedsdrtristate1__i + assign $0\builder_inferedsdrtristate2__o[0:0] \main_dfi_p0_wrdata [2] + assign $0\main_dfi_p0_rddata[15:0] [2] \builder_inferedsdrtristate2__i + assign $0\builder_inferedsdrtristate3__o[0:0] \main_dfi_p0_wrdata [3] + assign $0\main_dfi_p0_rddata[15:0] [3] \builder_inferedsdrtristate3__i + assign $0\builder_inferedsdrtristate4__o[0:0] \main_dfi_p0_wrdata [4] + assign $0\main_dfi_p0_rddata[15:0] [4] \builder_inferedsdrtristate4__i + assign $0\builder_inferedsdrtristate5__o[0:0] \main_dfi_p0_wrdata [5] + assign $0\main_dfi_p0_rddata[15:0] [5] \builder_inferedsdrtristate5__i + assign $0\builder_inferedsdrtristate6__o[0:0] \main_dfi_p0_wrdata [6] + assign $0\main_dfi_p0_rddata[15:0] [6] \builder_inferedsdrtristate6__i + assign $0\builder_inferedsdrtristate7__o[0:0] \main_dfi_p0_wrdata [7] + assign $0\main_dfi_p0_rddata[15:0] [7] \builder_inferedsdrtristate7__i + assign $0\builder_inferedsdrtristate8__o[0:0] \main_dfi_p0_wrdata [8] + assign $0\main_dfi_p0_rddata[15:0] [8] \builder_inferedsdrtristate8__i + assign $0\builder_inferedsdrtristate9__o[0:0] \main_dfi_p0_wrdata [9] + assign $0\main_dfi_p0_rddata[15:0] [9] \builder_inferedsdrtristate9__i + assign $0\builder_inferedsdrtristate10__o[0:0] \main_dfi_p0_wrdata [10] + assign $0\main_dfi_p0_rddata[15:0] [10] \builder_inferedsdrtristate10__i + assign $0\builder_inferedsdrtristate11__o[0:0] \main_dfi_p0_wrdata [11] + assign $0\main_dfi_p0_rddata[15:0] [11] \builder_inferedsdrtristate11__i + assign $0\builder_inferedsdrtristate12__o[0:0] \main_dfi_p0_wrdata [12] + assign $0\main_dfi_p0_rddata[15:0] [12] \builder_inferedsdrtristate12__i + assign $0\builder_inferedsdrtristate13__o[0:0] \main_dfi_p0_wrdata [13] + assign $0\main_dfi_p0_rddata[15:0] [13] \builder_inferedsdrtristate13__i + assign $0\builder_inferedsdrtristate14__o[0:0] \main_dfi_p0_wrdata [14] + assign $0\main_dfi_p0_rddata[15:0] [14] \builder_inferedsdrtristate14__i + assign $0\builder_inferedsdrtristate15__o[0:0] \main_dfi_p0_wrdata [15] + assign $0\main_dfi_p0_rddata[15:0] [15] \builder_inferedsdrtristate15__i + assign $0\builder_inferedsdrtristate16__o[0:0] \libresocsim_sdpads_cmd_o + assign $0\libresocsim_sdpads_cmd_i[0:0] \builder_inferedsdrtristate16__i + assign $0\builder_inferedsdrtristate17__o[0:0] \libresocsim_sdpads_data_o [0] + assign $0\libresocsim_sdpads_data_i[3:0] [0] \builder_inferedsdrtristate17__i + assign $0\builder_inferedsdrtristate18__o[0:0] \libresocsim_sdpads_data_o [1] + assign $0\libresocsim_sdpads_data_i[3:0] [1] \builder_inferedsdrtristate18__i + assign $0\builder_inferedsdrtristate19__o[0:0] \libresocsim_sdpads_data_o [2] + assign $0\libresocsim_sdpads_data_i[3:0] [2] \builder_inferedsdrtristate19__i + assign $0\builder_inferedsdrtristate20__o[0:0] \libresocsim_sdpads_data_o [3] + assign $0\libresocsim_sdpads_data_i[3:0] [3] \builder_inferedsdrtristate20__i + sync posedge \sdrio_clk + update \sdram_a $0\sdram_a[12:0] + update \sdram_we_n $0\sdram_we_n[0:0] + update \sdram_ras_n $0\sdram_ras_n[0:0] + update \sdram_cas_n $0\sdram_cas_n[0:0] + update \sdram_cs_n $0\sdram_cs_n[0:0] + update \sdram_cke $0\sdram_cke[0:0] + update \sdram_ba $0\sdram_ba[1:0] + update \sdcard_clk $0\sdcard_clk[0:0] + update \main_dfi_p0_rddata $0\main_dfi_p0_rddata[15:0] + update \libresocsim_sdpads_cmd_i $0\libresocsim_sdpads_cmd_i[0:0] + update \libresocsim_sdpads_data_i $0\libresocsim_sdpads_data_i[3:0] + update \builder_inferedsdrtristate0__o $0\builder_inferedsdrtristate0__o[0:0] + update \builder_inferedsdrtristate0_oe $0\builder_inferedsdrtristate0_oe[0:0] + update \builder_inferedsdrtristate1__o $0\builder_inferedsdrtristate1__o[0:0] + update \builder_inferedsdrtristate1_oe $0\builder_inferedsdrtristate1_oe[0:0] + update \builder_inferedsdrtristate2__o $0\builder_inferedsdrtristate2__o[0:0] + update \builder_inferedsdrtristate2_oe $0\builder_inferedsdrtristate2_oe[0:0] + update \builder_inferedsdrtristate3__o $0\builder_inferedsdrtristate3__o[0:0] + update \builder_inferedsdrtristate3_oe $0\builder_inferedsdrtristate3_oe[0:0] + update \builder_inferedsdrtristate4__o $0\builder_inferedsdrtristate4__o[0:0] + update \builder_inferedsdrtristate4_oe $0\builder_inferedsdrtristate4_oe[0:0] + update \builder_inferedsdrtristate5__o $0\builder_inferedsdrtristate5__o[0:0] + update \builder_inferedsdrtristate5_oe $0\builder_inferedsdrtristate5_oe[0:0] + update \builder_inferedsdrtristate6__o $0\builder_inferedsdrtristate6__o[0:0] + update \builder_inferedsdrtristate6_oe $0\builder_inferedsdrtristate6_oe[0:0] + update \builder_inferedsdrtristate7__o $0\builder_inferedsdrtristate7__o[0:0] + update \builder_inferedsdrtristate7_oe $0\builder_inferedsdrtristate7_oe[0:0] + update \builder_inferedsdrtristate8__o $0\builder_inferedsdrtristate8__o[0:0] + update \builder_inferedsdrtristate8_oe $0\builder_inferedsdrtristate8_oe[0:0] + update \builder_inferedsdrtristate9__o $0\builder_inferedsdrtristate9__o[0:0] + update \builder_inferedsdrtristate9_oe $0\builder_inferedsdrtristate9_oe[0:0] + update \builder_inferedsdrtristate10__o $0\builder_inferedsdrtristate10__o[0:0] + update \builder_inferedsdrtristate10_oe $0\builder_inferedsdrtristate10_oe[0:0] + update \builder_inferedsdrtristate11__o $0\builder_inferedsdrtristate11__o[0:0] + update \builder_inferedsdrtristate11_oe $0\builder_inferedsdrtristate11_oe[0:0] + update \builder_inferedsdrtristate12__o $0\builder_inferedsdrtristate12__o[0:0] + update \builder_inferedsdrtristate12_oe $0\builder_inferedsdrtristate12_oe[0:0] + update \builder_inferedsdrtristate13__o $0\builder_inferedsdrtristate13__o[0:0] + update \builder_inferedsdrtristate13_oe $0\builder_inferedsdrtristate13_oe[0:0] + update \builder_inferedsdrtristate14__o $0\builder_inferedsdrtristate14__o[0:0] + update \builder_inferedsdrtristate14_oe $0\builder_inferedsdrtristate14_oe[0:0] + update \builder_inferedsdrtristate15__o $0\builder_inferedsdrtristate15__o[0:0] + update \builder_inferedsdrtristate15_oe $0\builder_inferedsdrtristate15_oe[0:0] + update \builder_inferedsdrtristate16__o $0\builder_inferedsdrtristate16__o[0:0] + update \builder_inferedsdrtristate16_oe $0\builder_inferedsdrtristate16_oe[0:0] + update \builder_inferedsdrtristate17__o $0\builder_inferedsdrtristate17__o[0:0] + update \builder_inferedsdrtristate17_oe $0\builder_inferedsdrtristate17_oe[0:0] + update \builder_inferedsdrtristate18__o $0\builder_inferedsdrtristate18__o[0:0] + update \builder_inferedsdrtristate18_oe $0\builder_inferedsdrtristate18_oe[0:0] + update \builder_inferedsdrtristate19__o $0\builder_inferedsdrtristate19__o[0:0] + update \builder_inferedsdrtristate19_oe $0\builder_inferedsdrtristate19_oe[0:0] + update \builder_inferedsdrtristate20__o $0\builder_inferedsdrtristate20__o[0:0] + update \builder_inferedsdrtristate20_oe $0\builder_inferedsdrtristate20_oe[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:698.5-698.59" + process $proc$build/ls180/gateware/ls180.v:698$2821 + assign { } { } + assign $1\main_sdram_bankmachine2_cmd_buffer_source_valid[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine2_cmd_buffer_source_valid $1\main_sdram_bankmachine2_cmd_buffer_source_valid[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:700.5-700.59" + process $proc$build/ls180/gateware/ls180.v:700$2822 + assign { } { } + assign $1\main_sdram_bankmachine2_cmd_buffer_source_first[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine2_cmd_buffer_source_first $1\main_sdram_bankmachine2_cmd_buffer_source_first[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:701.5-701.58" + process $proc$build/ls180/gateware/ls180.v:701$2823 + assign { } { } + assign $1\main_sdram_bankmachine2_cmd_buffer_source_last[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine2_cmd_buffer_source_last $1\main_sdram_bankmachine2_cmd_buffer_source_last[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:702.5-702.64" + process $proc$build/ls180/gateware/ls180.v:702$2824 + assign { } { } + assign $1\main_sdram_bankmachine2_cmd_buffer_source_payload_we[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine2_cmd_buffer_source_payload_we $1\main_sdram_bankmachine2_cmd_buffer_source_payload_we[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:703.12-703.74" + process $proc$build/ls180/gateware/ls180.v:703$2825 + assign { } { } + assign $1\main_sdram_bankmachine2_cmd_buffer_source_payload_addr[21:0] 22'0000000000000000000000 + sync always + sync init + update \main_sdram_bankmachine2_cmd_buffer_source_payload_addr $1\main_sdram_bankmachine2_cmd_buffer_source_payload_addr[21:0] + end + attribute \src "build/ls180/gateware/ls180.v:704.12-704.47" + process $proc$build/ls180/gateware/ls180.v:704$2826 + assign { } { } + assign $1\main_sdram_bankmachine2_row[12:0] 13'0000000000000 + sync always + sync init + update \main_sdram_bankmachine2_row $1\main_sdram_bankmachine2_row[12:0] + end + attribute \src "build/ls180/gateware/ls180.v:705.5-705.46" + process $proc$build/ls180/gateware/ls180.v:705$2827 + assign { } { } + assign $1\main_sdram_bankmachine2_row_opened[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine2_row_opened $1\main_sdram_bankmachine2_row_opened[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:7055.1-9363.4" + process $proc$build/ls180/gateware/ls180.v:7055$2187 + assign $0\serial_tx[0:0] \serial_tx + assign $0\spi_master_clk[0:0] \spi_master_clk + assign $0\spi_master_mosi[0:0] \spi_master_mosi + assign { } { } + assign $0\spisdcard_clk[0:0] \spisdcard_clk + assign $0\spisdcard_mosi[0:0] \spisdcard_mosi + assign { } { } + assign $0\main_libresocsim_soccontroller_reset_storage[0:0] \main_libresocsim_soccontroller_reset_storage + assign { } { } + assign $0\main_libresocsim_soccontroller_scratch_storage[31:0] \main_libresocsim_soccontroller_scratch_storage + assign { } { } + assign $0\main_libresocsim_soccontroller_bus_errors[31:0] \main_libresocsim_soccontroller_bus_errors + assign $0\main_libresocsim_converter0_counter[0:0] \main_libresocsim_converter0_counter + assign $0\main_libresocsim_converter0_dat_r[63:0] \main_libresocsim_converter0_dat_r + assign $0\main_libresocsim_converter1_counter[0:0] \main_libresocsim_converter1_counter + assign $0\main_libresocsim_converter1_dat_r[63:0] \main_libresocsim_converter1_dat_r + assign { } { } + assign $0\main_libresocsim_storage[31:0] \main_libresocsim_storage + assign { } { } + assign { } { } + assign $0\main_libresocsim_uart_clk_txen[0:0] \main_libresocsim_uart_clk_txen + assign $0\main_libresocsim_phase_accumulator_tx[31:0] \main_libresocsim_phase_accumulator_tx + assign $0\main_libresocsim_tx_reg[7:0] \main_libresocsim_tx_reg + assign $0\main_libresocsim_tx_bitcount[3:0] \main_libresocsim_tx_bitcount + assign $0\main_libresocsim_tx_busy[0:0] \main_libresocsim_tx_busy + assign { } { } + assign $0\main_libresocsim_source_payload_data[7:0] \main_libresocsim_source_payload_data + assign $0\main_libresocsim_uart_clk_rxen[0:0] \main_libresocsim_uart_clk_rxen + assign $0\main_libresocsim_phase_accumulator_rx[31:0] \main_libresocsim_phase_accumulator_rx + assign { } { } + assign $0\main_libresocsim_rx_reg[7:0] \main_libresocsim_rx_reg + assign $0\main_libresocsim_rx_bitcount[3:0] \main_libresocsim_rx_bitcount + assign $0\main_libresocsim_rx_busy[0:0] \main_libresocsim_rx_busy + assign $0\main_libresocsim_uart_tx_pending[0:0] \main_libresocsim_uart_tx_pending + assign { } { } + assign $0\main_libresocsim_uart_rx_pending[0:0] \main_libresocsim_uart_rx_pending + assign { } { } + assign $0\main_libresocsim_uart_eventmanager_storage[1:0] \main_libresocsim_uart_eventmanager_storage + assign { } { } + assign $0\main_libresocsim_uart_tx_fifo_readable[0:0] \main_libresocsim_uart_tx_fifo_readable + assign $0\main_libresocsim_uart_tx_fifo_level0[4:0] \main_libresocsim_uart_tx_fifo_level0 + assign $0\main_libresocsim_uart_tx_fifo_produce[3:0] \main_libresocsim_uart_tx_fifo_produce + assign $0\main_libresocsim_uart_tx_fifo_consume[3:0] \main_libresocsim_uart_tx_fifo_consume + assign $0\main_libresocsim_uart_rx_fifo_readable[0:0] \main_libresocsim_uart_rx_fifo_readable + assign $0\main_libresocsim_uart_rx_fifo_level0[4:0] \main_libresocsim_uart_rx_fifo_level0 + assign $0\main_libresocsim_uart_rx_fifo_produce[3:0] \main_libresocsim_uart_rx_fifo_produce + assign $0\main_libresocsim_uart_rx_fifo_consume[3:0] \main_libresocsim_uart_rx_fifo_consume + assign $0\main_libresocsim_timer_load_storage[31:0] \main_libresocsim_timer_load_storage + assign { } { } + assign $0\main_libresocsim_timer_reload_storage[31:0] \main_libresocsim_timer_reload_storage + assign { } { } + assign $0\main_libresocsim_timer_en_storage[0:0] \main_libresocsim_timer_en_storage + assign { } { } + assign $0\main_libresocsim_timer_update_value_storage[0:0] \main_libresocsim_timer_update_value_storage + assign { } { } + assign $0\main_libresocsim_timer_value_status[31:0] \main_libresocsim_timer_value_status + assign $0\main_libresocsim_timer_zero_pending[0:0] \main_libresocsim_timer_zero_pending + assign { } { } + assign $0\main_libresocsim_timer_eventmanager_storage[0:0] \main_libresocsim_timer_eventmanager_storage + assign { } { } + assign $0\main_libresocsim_timer_value[31:0] \main_libresocsim_timer_value + assign { } { } + assign { } { } + assign $0\main_sdram_storage[3:0] \main_sdram_storage + assign { } { } + assign $0\main_sdram_command_storage[5:0] \main_sdram_command_storage + assign { } { } + assign $0\main_sdram_address_storage[12:0] \main_sdram_address_storage + assign { } { } + assign $0\main_sdram_baddress_storage[1:0] \main_sdram_baddress_storage + assign { } { } + assign $0\main_sdram_wrdata_storage[15:0] \main_sdram_wrdata_storage + assign { } { } + assign $0\main_sdram_status[15:0] \main_sdram_status + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\main_sdram_timer_count1[9:0] \main_sdram_timer_count1 + assign { } { } + assign $0\main_sdram_postponer_count[0:0] \main_sdram_postponer_count + assign { } { } + assign $0\main_sdram_sequencer_counter[3:0] \main_sdram_sequencer_counter + assign $0\main_sdram_sequencer_count[0:0] \main_sdram_sequencer_count + assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_level[3:0] \main_sdram_bankmachine0_cmd_buffer_lookahead_level + assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_produce[2:0] \main_sdram_bankmachine0_cmd_buffer_lookahead_produce + assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_consume[2:0] \main_sdram_bankmachine0_cmd_buffer_lookahead_consume + assign $0\main_sdram_bankmachine0_cmd_buffer_source_valid[0:0] \main_sdram_bankmachine0_cmd_buffer_source_valid + assign $0\main_sdram_bankmachine0_cmd_buffer_source_first[0:0] \main_sdram_bankmachine0_cmd_buffer_source_first + assign $0\main_sdram_bankmachine0_cmd_buffer_source_last[0:0] \main_sdram_bankmachine0_cmd_buffer_source_last + assign $0\main_sdram_bankmachine0_cmd_buffer_source_payload_we[0:0] \main_sdram_bankmachine0_cmd_buffer_source_payload_we + assign $0\main_sdram_bankmachine0_cmd_buffer_source_payload_addr[21:0] \main_sdram_bankmachine0_cmd_buffer_source_payload_addr + assign $0\main_sdram_bankmachine0_row[12:0] \main_sdram_bankmachine0_row + assign $0\main_sdram_bankmachine0_row_opened[0:0] \main_sdram_bankmachine0_row_opened + assign $0\main_sdram_bankmachine0_twtpcon_ready[0:0] \main_sdram_bankmachine0_twtpcon_ready + assign $0\main_sdram_bankmachine0_twtpcon_count[2:0] \main_sdram_bankmachine0_twtpcon_count + assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_level[3:0] \main_sdram_bankmachine1_cmd_buffer_lookahead_level + assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_produce[2:0] \main_sdram_bankmachine1_cmd_buffer_lookahead_produce + assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_consume[2:0] \main_sdram_bankmachine1_cmd_buffer_lookahead_consume + assign $0\main_sdram_bankmachine1_cmd_buffer_source_valid[0:0] \main_sdram_bankmachine1_cmd_buffer_source_valid + assign $0\main_sdram_bankmachine1_cmd_buffer_source_first[0:0] \main_sdram_bankmachine1_cmd_buffer_source_first + assign $0\main_sdram_bankmachine1_cmd_buffer_source_last[0:0] \main_sdram_bankmachine1_cmd_buffer_source_last + assign $0\main_sdram_bankmachine1_cmd_buffer_source_payload_we[0:0] \main_sdram_bankmachine1_cmd_buffer_source_payload_we + assign $0\main_sdram_bankmachine1_cmd_buffer_source_payload_addr[21:0] \main_sdram_bankmachine1_cmd_buffer_source_payload_addr + assign $0\main_sdram_bankmachine1_row[12:0] \main_sdram_bankmachine1_row + assign $0\main_sdram_bankmachine1_row_opened[0:0] \main_sdram_bankmachine1_row_opened + assign $0\main_sdram_bankmachine1_twtpcon_ready[0:0] \main_sdram_bankmachine1_twtpcon_ready + assign $0\main_sdram_bankmachine1_twtpcon_count[2:0] \main_sdram_bankmachine1_twtpcon_count + assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_level[3:0] \main_sdram_bankmachine2_cmd_buffer_lookahead_level + assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_produce[2:0] \main_sdram_bankmachine2_cmd_buffer_lookahead_produce + assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_consume[2:0] \main_sdram_bankmachine2_cmd_buffer_lookahead_consume + assign $0\main_sdram_bankmachine2_cmd_buffer_source_valid[0:0] \main_sdram_bankmachine2_cmd_buffer_source_valid + assign $0\main_sdram_bankmachine2_cmd_buffer_source_first[0:0] \main_sdram_bankmachine2_cmd_buffer_source_first + assign $0\main_sdram_bankmachine2_cmd_buffer_source_last[0:0] \main_sdram_bankmachine2_cmd_buffer_source_last + assign $0\main_sdram_bankmachine2_cmd_buffer_source_payload_we[0:0] \main_sdram_bankmachine2_cmd_buffer_source_payload_we + assign $0\main_sdram_bankmachine2_cmd_buffer_source_payload_addr[21:0] \main_sdram_bankmachine2_cmd_buffer_source_payload_addr + assign $0\main_sdram_bankmachine2_row[12:0] \main_sdram_bankmachine2_row + assign $0\main_sdram_bankmachine2_row_opened[0:0] \main_sdram_bankmachine2_row_opened + assign $0\main_sdram_bankmachine2_twtpcon_ready[0:0] \main_sdram_bankmachine2_twtpcon_ready + assign $0\main_sdram_bankmachine2_twtpcon_count[2:0] \main_sdram_bankmachine2_twtpcon_count + assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_level[3:0] \main_sdram_bankmachine3_cmd_buffer_lookahead_level + assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_produce[2:0] \main_sdram_bankmachine3_cmd_buffer_lookahead_produce + assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_consume[2:0] \main_sdram_bankmachine3_cmd_buffer_lookahead_consume + assign $0\main_sdram_bankmachine3_cmd_buffer_source_valid[0:0] \main_sdram_bankmachine3_cmd_buffer_source_valid + assign $0\main_sdram_bankmachine3_cmd_buffer_source_first[0:0] \main_sdram_bankmachine3_cmd_buffer_source_first + assign $0\main_sdram_bankmachine3_cmd_buffer_source_last[0:0] \main_sdram_bankmachine3_cmd_buffer_source_last + assign $0\main_sdram_bankmachine3_cmd_buffer_source_payload_we[0:0] \main_sdram_bankmachine3_cmd_buffer_source_payload_we + assign $0\main_sdram_bankmachine3_cmd_buffer_source_payload_addr[21:0] \main_sdram_bankmachine3_cmd_buffer_source_payload_addr + assign $0\main_sdram_bankmachine3_row[12:0] \main_sdram_bankmachine3_row + assign $0\main_sdram_bankmachine3_row_opened[0:0] \main_sdram_bankmachine3_row_opened + assign $0\main_sdram_bankmachine3_twtpcon_ready[0:0] \main_sdram_bankmachine3_twtpcon_ready + assign $0\main_sdram_bankmachine3_twtpcon_count[2:0] \main_sdram_bankmachine3_twtpcon_count + assign $0\main_sdram_choose_cmd_grant[1:0] \main_sdram_choose_cmd_grant + assign $0\main_sdram_choose_req_grant[1:0] \main_sdram_choose_req_grant + assign $0\main_sdram_tccdcon_ready[0:0] \main_sdram_tccdcon_ready + assign $0\main_sdram_tccdcon_count[0:0] \main_sdram_tccdcon_count + assign $0\main_sdram_twtrcon_ready[0:0] \main_sdram_twtrcon_ready + assign $0\main_sdram_twtrcon_count[2:0] \main_sdram_twtrcon_count + assign $0\main_sdram_time0[4:0] \main_sdram_time0 + assign $0\main_sdram_time1[3:0] \main_sdram_time1 + assign $0\main_converter_counter[0:0] \main_converter_counter + assign $0\main_converter_dat_r[31:0] \main_converter_dat_r + assign $0\main_cmd_consumed[0:0] \main_cmd_consumed + assign $0\main_wdata_consumed[0:0] \main_wdata_consumed + assign $0\main_miso[7:0] \main_miso + assign $0\main_control_storage[15:0] \main_control_storage + assign { } { } + assign $0\main_mosi_storage[7:0] \main_mosi_storage + assign { } { } + assign $0\main_cs_storage[0:0] \main_cs_storage + assign { } { } + assign $0\main_loopback_storage[0:0] \main_loopback_storage + assign { } { } + assign $0\main_count[2:0] \main_count + assign { } { } + assign $0\main_mosi_data[7:0] \main_mosi_data + assign $0\main_mosi_sel[2:0] \main_mosi_sel + assign $0\main_miso_data[7:0] \main_miso_data + assign $0\libresocsim_clocker_storage[8:0] \libresocsim_clocker_storage + assign { } { } + assign { } { } + assign $0\libresocsim_clocker_clks[8:0] \libresocsim_clocker_clks + assign { } { } + assign $0\libresocsim_init_count[7:0] \libresocsim_init_count + assign $0\libresocsim_cmdw_count[7:0] \libresocsim_cmdw_count + assign $0\libresocsim_cmdr_timeout[31:0] \libresocsim_cmdr_timeout + assign $0\libresocsim_cmdr_count[7:0] \libresocsim_cmdr_count + assign $0\libresocsim_cmdr_cmdr_run[0:0] \libresocsim_cmdr_cmdr_run + assign $0\libresocsim_cmdr_cmdr_converter_source_first[0:0] \libresocsim_cmdr_cmdr_converter_source_first + assign $0\libresocsim_cmdr_cmdr_converter_source_last[0:0] \libresocsim_cmdr_cmdr_converter_source_last + assign $0\libresocsim_cmdr_cmdr_converter_source_payload_data[7:0] \libresocsim_cmdr_cmdr_converter_source_payload_data + assign $0\libresocsim_cmdr_cmdr_converter_source_payload_valid_token_count[3:0] \libresocsim_cmdr_cmdr_converter_source_payload_valid_token_count + assign $0\libresocsim_cmdr_cmdr_converter_demux[2:0] \libresocsim_cmdr_cmdr_converter_demux + assign $0\libresocsim_cmdr_cmdr_converter_strobe_all[0:0] \libresocsim_cmdr_cmdr_converter_strobe_all + assign $0\libresocsim_cmdr_cmdr_buf_source_valid[0:0] \libresocsim_cmdr_cmdr_buf_source_valid + assign $0\libresocsim_cmdr_cmdr_buf_source_first[0:0] \libresocsim_cmdr_cmdr_buf_source_first + assign $0\libresocsim_cmdr_cmdr_buf_source_last[0:0] \libresocsim_cmdr_cmdr_buf_source_last + assign $0\libresocsim_cmdr_cmdr_buf_source_payload_data[7:0] \libresocsim_cmdr_cmdr_buf_source_payload_data + assign $0\libresocsim_cmdr_cmdr_reset[0:0] \libresocsim_cmdr_cmdr_reset + assign $0\libresocsim_dataw_count[7:0] \libresocsim_dataw_count + assign $0\libresocsim_dataw_crcr_run[0:0] \libresocsim_dataw_crcr_run + assign $0\libresocsim_dataw_crcr_converter_source_first[0:0] \libresocsim_dataw_crcr_converter_source_first + assign $0\libresocsim_dataw_crcr_converter_source_last[0:0] \libresocsim_dataw_crcr_converter_source_last + assign $0\libresocsim_dataw_crcr_converter_source_payload_data[7:0] \libresocsim_dataw_crcr_converter_source_payload_data + assign $0\libresocsim_dataw_crcr_converter_source_payload_valid_token_count[3:0] \libresocsim_dataw_crcr_converter_source_payload_valid_token_count + assign $0\libresocsim_dataw_crcr_converter_demux[2:0] \libresocsim_dataw_crcr_converter_demux + assign $0\libresocsim_dataw_crcr_converter_strobe_all[0:0] \libresocsim_dataw_crcr_converter_strobe_all + assign $0\libresocsim_dataw_crcr_buf_source_valid[0:0] \libresocsim_dataw_crcr_buf_source_valid + assign $0\libresocsim_dataw_crcr_buf_source_first[0:0] \libresocsim_dataw_crcr_buf_source_first + assign $0\libresocsim_dataw_crcr_buf_source_last[0:0] \libresocsim_dataw_crcr_buf_source_last + assign $0\libresocsim_dataw_crcr_buf_source_payload_data[7:0] \libresocsim_dataw_crcr_buf_source_payload_data + assign $0\libresocsim_dataw_crcr_reset[0:0] \libresocsim_dataw_crcr_reset + assign $0\libresocsim_datar_timeout[31:0] \libresocsim_datar_timeout + assign $0\libresocsim_datar_count[9:0] \libresocsim_datar_count + assign $0\libresocsim_datar_datar_run[0:0] \libresocsim_datar_datar_run + assign $0\libresocsim_datar_datar_converter_source_first[0:0] \libresocsim_datar_datar_converter_source_first + assign $0\libresocsim_datar_datar_converter_source_last[0:0] \libresocsim_datar_datar_converter_source_last + assign $0\libresocsim_datar_datar_converter_source_payload_data[7:0] \libresocsim_datar_datar_converter_source_payload_data + assign $0\libresocsim_datar_datar_converter_source_payload_valid_token_count[1:0] \libresocsim_datar_datar_converter_source_payload_valid_token_count + assign $0\libresocsim_datar_datar_converter_demux[0:0] \libresocsim_datar_datar_converter_demux + assign $0\libresocsim_datar_datar_converter_strobe_all[0:0] \libresocsim_datar_datar_converter_strobe_all + assign $0\libresocsim_datar_datar_buf_source_valid[0:0] \libresocsim_datar_datar_buf_source_valid + assign $0\libresocsim_datar_datar_buf_source_first[0:0] \libresocsim_datar_datar_buf_source_first + assign $0\libresocsim_datar_datar_buf_source_last[0:0] \libresocsim_datar_datar_buf_source_last + assign $0\libresocsim_datar_datar_buf_source_payload_data[7:0] \libresocsim_datar_datar_buf_source_payload_data + assign $0\libresocsim_datar_datar_reset[0:0] \libresocsim_datar_datar_reset + assign $0\libresocsim_sdcore_cmd_argument_storage[31:0] \libresocsim_sdcore_cmd_argument_storage + assign { } { } + assign $0\libresocsim_sdcore_cmd_command_storage[31:0] \libresocsim_sdcore_cmd_command_storage + assign { } { } + assign $0\libresocsim_sdcore_cmd_response_status[127:0] \libresocsim_sdcore_cmd_response_status + assign $0\libresocsim_sdcore_block_length_storage[9:0] \libresocsim_sdcore_block_length_storage + assign { } { } + assign $0\libresocsim_sdcore_block_count_storage[31:0] \libresocsim_sdcore_block_count_storage + assign { } { } + assign $0\libresocsim_sdcore_crc7_inserter_crcreg0[6:0] \libresocsim_sdcore_crc7_inserter_crcreg0 + assign $0\libresocsim_sdcore_crc16_inserter_cnt[2:0] \libresocsim_sdcore_crc16_inserter_cnt + assign $0\libresocsim_sdcore_crc16_inserter_crc0_crcreg0[15:0] \libresocsim_sdcore_crc16_inserter_crc0_crcreg0 + assign $0\libresocsim_sdcore_crc16_inserter_crc1_crcreg0[15:0] \libresocsim_sdcore_crc16_inserter_crc1_crcreg0 + assign $0\libresocsim_sdcore_crc16_inserter_crc2_crcreg0[15:0] \libresocsim_sdcore_crc16_inserter_crc2_crcreg0 + assign $0\libresocsim_sdcore_crc16_inserter_crc3_crcreg0[15:0] \libresocsim_sdcore_crc16_inserter_crc3_crcreg0 + assign $0\libresocsim_sdcore_crc16_inserter_crctmp0[15:0] \libresocsim_sdcore_crc16_inserter_crctmp0 + assign $0\libresocsim_sdcore_crc16_inserter_crctmp1[15:0] \libresocsim_sdcore_crc16_inserter_crctmp1 + assign $0\libresocsim_sdcore_crc16_inserter_crctmp2[15:0] \libresocsim_sdcore_crc16_inserter_crctmp2 + assign $0\libresocsim_sdcore_crc16_inserter_crctmp3[15:0] \libresocsim_sdcore_crc16_inserter_crctmp3 + assign $0\libresocsim_sdcore_crc16_checker_val[7:0] \libresocsim_sdcore_crc16_checker_val + assign $0\libresocsim_sdcore_crc16_checker_cnt[3:0] \libresocsim_sdcore_crc16_checker_cnt + assign $0\libresocsim_sdcore_crc16_checker_crc0_crcreg0[15:0] \libresocsim_sdcore_crc16_checker_crc0_crcreg0 + assign $0\libresocsim_sdcore_crc16_checker_crc1_crcreg0[15:0] \libresocsim_sdcore_crc16_checker_crc1_crcreg0 + assign $0\libresocsim_sdcore_crc16_checker_crc2_crcreg0[15:0] \libresocsim_sdcore_crc16_checker_crc2_crcreg0 + assign $0\libresocsim_sdcore_crc16_checker_crc3_crcreg0[15:0] \libresocsim_sdcore_crc16_checker_crc3_crcreg0 + assign $0\libresocsim_sdcore_crc16_checker_crctmp0[15:0] \libresocsim_sdcore_crc16_checker_crctmp0 + assign $0\libresocsim_sdcore_crc16_checker_crctmp1[15:0] \libresocsim_sdcore_crc16_checker_crctmp1 + assign $0\libresocsim_sdcore_crc16_checker_crctmp2[15:0] \libresocsim_sdcore_crc16_checker_crctmp2 + assign $0\libresocsim_sdcore_crc16_checker_crctmp3[15:0] \libresocsim_sdcore_crc16_checker_crctmp3 + assign $0\libresocsim_sdcore_crc16_checker_fifo0[15:0] \libresocsim_sdcore_crc16_checker_fifo0 + assign $0\libresocsim_sdcore_crc16_checker_fifo1[15:0] \libresocsim_sdcore_crc16_checker_fifo1 + assign $0\libresocsim_sdcore_crc16_checker_fifo2[15:0] \libresocsim_sdcore_crc16_checker_fifo2 + assign $0\libresocsim_sdcore_crc16_checker_fifo3[15:0] \libresocsim_sdcore_crc16_checker_fifo3 + assign $0\libresocsim_sdcore_cmd_count[2:0] \libresocsim_sdcore_cmd_count + assign $0\libresocsim_sdcore_cmd_done[0:0] \libresocsim_sdcore_cmd_done + assign $0\libresocsim_sdcore_cmd_error[0:0] \libresocsim_sdcore_cmd_error + assign $0\libresocsim_sdcore_cmd_timeout[0:0] \libresocsim_sdcore_cmd_timeout + assign $0\libresocsim_sdcore_data_count[31:0] \libresocsim_sdcore_data_count + assign $0\libresocsim_sdcore_data_done[0:0] \libresocsim_sdcore_data_done + assign $0\libresocsim_sdcore_data_error[0:0] \libresocsim_sdcore_data_error + assign $0\libresocsim_sdcore_data_timeout[0:0] \libresocsim_sdcore_data_timeout + assign $0\libresocsim_sdblock2mem_fifo_level[5:0] \libresocsim_sdblock2mem_fifo_level + assign $0\libresocsim_sdblock2mem_fifo_produce[4:0] \libresocsim_sdblock2mem_fifo_produce + assign $0\libresocsim_sdblock2mem_fifo_consume[4:0] \libresocsim_sdblock2mem_fifo_consume + assign $0\libresocsim_sdblock2mem_converter_source_first[0:0] \libresocsim_sdblock2mem_converter_source_first + assign $0\libresocsim_sdblock2mem_converter_source_last[0:0] \libresocsim_sdblock2mem_converter_source_last + assign $0\libresocsim_sdblock2mem_converter_source_payload_data[31:0] \libresocsim_sdblock2mem_converter_source_payload_data + assign $0\libresocsim_sdblock2mem_converter_source_payload_valid_token_count[2:0] \libresocsim_sdblock2mem_converter_source_payload_valid_token_count + assign $0\libresocsim_sdblock2mem_converter_demux[1:0] \libresocsim_sdblock2mem_converter_demux + assign $0\libresocsim_sdblock2mem_converter_strobe_all[0:0] \libresocsim_sdblock2mem_converter_strobe_all + assign $0\libresocsim_sdblock2mem_wishbonedmawriter_base_storage[63:0] \libresocsim_sdblock2mem_wishbonedmawriter_base_storage + assign { } { } + assign $0\libresocsim_sdblock2mem_wishbonedmawriter_length_storage[31:0] \libresocsim_sdblock2mem_wishbonedmawriter_length_storage + assign { } { } + assign $0\libresocsim_sdblock2mem_wishbonedmawriter_enable_storage[0:0] \libresocsim_sdblock2mem_wishbonedmawriter_enable_storage + assign { } { } + assign $0\libresocsim_sdblock2mem_wishbonedmawriter_loop_storage[0:0] \libresocsim_sdblock2mem_wishbonedmawriter_loop_storage + assign { } { } + assign $0\libresocsim_sdblock2mem_wishbonedmawriter_offset[31:0] \libresocsim_sdblock2mem_wishbonedmawriter_offset + assign $0\libresocsim_sdmem2block_dma_data[31:0] \libresocsim_sdmem2block_dma_data + assign $0\libresocsim_sdmem2block_dma_base_storage[63:0] \libresocsim_sdmem2block_dma_base_storage + assign { } { } + assign $0\libresocsim_sdmem2block_dma_length_storage[31:0] \libresocsim_sdmem2block_dma_length_storage + assign { } { } + assign $0\libresocsim_sdmem2block_dma_enable_storage[0:0] \libresocsim_sdmem2block_dma_enable_storage + assign { } { } + assign $0\libresocsim_sdmem2block_dma_loop_storage[0:0] \libresocsim_sdmem2block_dma_loop_storage + assign { } { } + assign $0\libresocsim_sdmem2block_dma_offset[31:0] \libresocsim_sdmem2block_dma_offset + assign $0\libresocsim_sdmem2block_converter_mux[1:0] \libresocsim_sdmem2block_converter_mux + assign $0\libresocsim_sdmem2block_fifo_level[5:0] \libresocsim_sdmem2block_fifo_level + assign $0\libresocsim_sdmem2block_fifo_produce[4:0] \libresocsim_sdmem2block_fifo_produce + assign $0\libresocsim_sdmem2block_fifo_consume[4:0] \libresocsim_sdmem2block_fifo_consume + assign $0\libresocsim_miso[7:0] \libresocsim_miso + assign $0\libresocsim_control_storage[15:0] \libresocsim_control_storage + assign { } { } + assign $0\libresocsim_mosi_storage[7:0] \libresocsim_mosi_storage + assign { } { } + assign $0\libresocsim_cs_storage[0:0] \libresocsim_cs_storage + assign { } { } + assign $0\libresocsim_loopback_storage[0:0] \libresocsim_loopback_storage + assign { } { } + assign $0\libresocsim_count[2:0] \libresocsim_count + assign { } { } + assign $0\libresocsim_mosi_data[7:0] \libresocsim_mosi_data + assign $0\libresocsim_mosi_sel[2:0] \libresocsim_mosi_sel + assign $0\libresocsim_miso_data[7:0] \libresocsim_miso_data + assign $0\libresocsim_storage[15:0] \libresocsim_storage + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\builder_libresocsim_adr[13:0] \builder_libresocsim_adr + assign $0\builder_libresocsim_we[0:0] \builder_libresocsim_we + assign $0\builder_libresocsim_dat_w[7:0] \builder_libresocsim_dat_w + assign $0\builder_grant[1:0] \builder_grant + assign { } { } + assign $0\builder_count[19:0] \builder_count + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\builder_converter0_state[0:0] \builder_converter0_next_state + assign $0\builder_converter1_state[0:0] \builder_converter1_next_state + assign $0\main_libresocsim_ram_bus_ack[0:0] 1'0 + assign $0\main_libresocsim_sink_ready[0:0] 1'0 + assign $0\main_libresocsim_source_valid[0:0] 1'0 + assign $0\main_libresocsim_rx_r[0:0] \main_libresocsim_rx + assign $0\main_libresocsim_uart_tx_old_trigger[0:0] \main_libresocsim_uart_tx_trigger + assign $0\main_libresocsim_uart_rx_old_trigger[0:0] \main_libresocsim_uart_rx_trigger + assign $0\main_libresocsim_timer_zero_old_trigger[0:0] \main_libresocsim_timer_zero_trigger + assign $0\main_rddata_en[2:0] { \main_rddata_en [1:0] \main_dfi_p0_rddata_en } + assign $0\main_dfi_p0_rddata_valid[0:0] \main_rddata_en [2] + assign $0\main_sdram_postponer_req_o[0:0] 1'0 + assign $0\main_sdram_cmd_payload_a[12:0] 13'0000000000000 + assign $0\main_sdram_cmd_payload_ba[1:0] 2'00 + assign $0\main_sdram_cmd_payload_cas[0:0] 1'0 + assign $0\main_sdram_cmd_payload_ras[0:0] 1'0 + assign $0\main_sdram_cmd_payload_we[0:0] 1'0 + assign $0\main_sdram_sequencer_done1[0:0] 1'0 + assign $0\builder_refresher_state[1:0] \builder_refresher_next_state + assign $0\builder_bankmachine0_state[2:0] \builder_bankmachine0_next_state + assign $0\builder_bankmachine1_state[2:0] \builder_bankmachine1_next_state + assign $0\builder_bankmachine2_state[2:0] \builder_bankmachine2_next_state + assign $0\builder_bankmachine3_state[2:0] \builder_bankmachine3_next_state + assign $0\main_sdram_dfi_p0_cs_n[0:0] 1'0 + assign $0\main_sdram_dfi_p0_bank[1:0] \builder_sync_rhs_array_muxed0 + assign $0\main_sdram_dfi_p0_address[12:0] \builder_sync_rhs_array_muxed1 + assign $0\main_sdram_dfi_p0_cas_n[0:0] $not$build/ls180/gateware/ls180.v:7618$2325_Y + assign $0\main_sdram_dfi_p0_ras_n[0:0] $not$build/ls180/gateware/ls180.v:7619$2326_Y + assign $0\main_sdram_dfi_p0_we_n[0:0] $not$build/ls180/gateware/ls180.v:7620$2327_Y + assign $0\main_sdram_dfi_p0_rddata_en[0:0] \builder_sync_rhs_array_muxed5 + assign $0\main_sdram_dfi_p0_wrdata_en[0:0] \builder_sync_rhs_array_muxed6 + assign $0\builder_multiplexer_state[2:0] \builder_multiplexer_next_state + assign $0\builder_new_master_wdata_ready[0:0] $or$build/ls180/gateware/ls180.v:7654$2345_Y + assign $0\builder_new_master_rdata_valid0[0:0] $or$build/ls180/gateware/ls180.v:7655$2357_Y + assign $0\builder_new_master_rdata_valid1[0:0] \builder_new_master_rdata_valid0 + assign $0\builder_new_master_rdata_valid2[0:0] \builder_new_master_rdata_valid1 + assign $0\builder_new_master_rdata_valid3[0:0] \builder_new_master_rdata_valid2 + assign $0\builder_converter_state[0:0] \builder_converter_next_state + assign $0\main_clk_divider1[15:0] $add$build/ls180/gateware/ls180.v:7681$2361_Y + assign $0\spi_master_cs_n[0:0] $or$build/ls180/gateware/ls180.v:7690$2364_Y + assign $0\builder_spimaster0_state[1:0] \builder_spimaster0_next_state + assign $0\libresocsim_clocker_clk_d[0:0] \libresocsim_clocker_clk1 + assign $0\libresocsim_clocker_clk0[0:0] \libresocsim_clocker_clk1 + assign $0\builder_sdphy_sdphyinit_state[0:0] \builder_sdphy_sdphyinit_next_state + assign $0\builder_sdphy_sdphycmdw_state[1:0] \builder_sdphy_sdphycmdw_next_state + assign $0\builder_sdphy_sdphycmdr_state[2:0] \builder_sdphy_sdphycmdr_next_state + assign $0\builder_sdphy_sdphycrcr_state[0:0] \builder_sdphy_sdphycrcr_next_state + assign $0\builder_sdphy_fsm_state[2:0] \builder_sdphy_fsm_next_state + assign $0\builder_sdphy_sdphydatar_state[2:0] \builder_sdphy_sdphydatar_next_state + assign $0\builder_sdcore_crcupstreaminserter_state[0:0] \builder_sdcore_crcupstreaminserter_next_state + assign $0\builder_sdcore_fsm_state[2:0] \builder_sdcore_fsm_next_state + assign $0\builder_sdblock2memdma_state[1:0] \builder_sdblock2memdma_next_state + assign $0\builder_sdmem2blockdma_fsm_state[0:0] \builder_sdmem2blockdma_fsm_next_state + assign $0\builder_sdmem2blockdma_resetinserter_state[1:0] \builder_sdmem2blockdma_resetinserter_next_state + assign $0\libresocsim_clk_divider1[15:0] $add$build/ls180/gateware/ls180.v:8201$2448_Y + assign $0\spisdcard_cs_n[0:0] $or$build/ls180/gateware/ls180.v:8210$2451_Y + assign $0\builder_spimaster1_state[1:0] \builder_spimaster1_next_state + assign $0\builder_state[1:0] \builder_next_state + assign $0\builder_slave_sel_r[4:0] \builder_slave_sel + assign $0\builder_interface0_bank_bus_dat_r[7:0] 8'00000000 + assign $0\main_libresocsim_soccontroller_reset_re[0:0] \builder_csrbank0_reset0_re + assign $0\main_libresocsim_soccontroller_scratch_re[0:0] \builder_csrbank0_scratch0_re + assign $0\builder_interface1_bank_bus_dat_r[7:0] 8'00000000 + assign $0\builder_interface2_bank_bus_dat_r[7:0] 8'00000000 + assign $0\builder_interface3_bank_bus_dat_r[7:0] 8'00000000 + assign $0\libresocsim_sdblock2mem_wishbonedmawriter_base_re[0:0] \builder_csrbank3_dma_base0_re + assign $0\libresocsim_sdblock2mem_wishbonedmawriter_length_re[0:0] \builder_csrbank3_dma_length0_re + assign $0\libresocsim_sdblock2mem_wishbonedmawriter_enable_re[0:0] \builder_csrbank3_dma_enable0_re + assign $0\libresocsim_sdblock2mem_wishbonedmawriter_loop_re[0:0] \builder_csrbank3_dma_loop0_re + assign $0\builder_interface4_bank_bus_dat_r[7:0] 8'00000000 + assign $0\libresocsim_sdcore_cmd_argument_re[0:0] \builder_csrbank4_cmd_argument0_re + assign $0\libresocsim_sdcore_cmd_command_re[0:0] \builder_csrbank4_cmd_command0_re + assign $0\libresocsim_sdcore_block_length_re[0:0] \builder_csrbank4_block_length0_re + assign $0\libresocsim_sdcore_block_count_re[0:0] \builder_csrbank4_block_count0_re + assign $0\builder_interface5_bank_bus_dat_r[7:0] 8'00000000 + assign $0\libresocsim_sdmem2block_dma_base_re[0:0] \builder_csrbank5_dma_base0_re + assign $0\libresocsim_sdmem2block_dma_length_re[0:0] \builder_csrbank5_dma_length0_re + assign $0\libresocsim_sdmem2block_dma_enable_re[0:0] \builder_csrbank5_dma_enable0_re + assign $0\libresocsim_sdmem2block_dma_loop_re[0:0] \builder_csrbank5_dma_loop0_re + assign $0\builder_interface6_bank_bus_dat_r[7:0] 8'00000000 + assign $0\libresocsim_clocker_re[0:0] \builder_csrbank6_clocker_divider0_re + assign $0\builder_interface7_bank_bus_dat_r[7:0] 8'00000000 + assign $0\main_sdram_re[0:0] \builder_csrbank7_dfii_control0_re + assign $0\main_sdram_command_re[0:0] \builder_csrbank7_dfii_pi0_command0_re + assign $0\main_sdram_address_re[0:0] \builder_csrbank7_dfii_pi0_address0_re + assign $0\main_sdram_baddress_re[0:0] \builder_csrbank7_dfii_pi0_baddress0_re + assign $0\main_sdram_wrdata_re[0:0] \builder_csrbank7_dfii_pi0_wrdata0_re + assign $0\builder_interface8_bank_bus_dat_r[7:0] 8'00000000 + assign $0\main_control_re[0:0] \builder_csrbank8_control0_re + assign $0\main_mosi_re[0:0] \builder_csrbank8_mosi0_re + assign $0\main_cs_re[0:0] \builder_csrbank8_cs0_re + assign $0\main_loopback_re[0:0] \builder_csrbank8_loopback0_re + assign $0\builder_interface9_bank_bus_dat_r[7:0] 8'00000000 + assign $0\libresocsim_control_re[0:0] \builder_csrbank9_control0_re + assign $0\libresocsim_mosi_re[0:0] \builder_csrbank9_mosi0_re + assign $0\libresocsim_cs_re[0:0] \builder_csrbank9_cs0_re + assign $0\libresocsim_loopback_re[0:0] \builder_csrbank9_loopback0_re + assign $0\libresocsim_re[0:0] \builder_csrbank9_clk_divider0_re + assign $0\builder_interface10_bank_bus_dat_r[7:0] 8'00000000 + assign $0\main_libresocsim_timer_load_re[0:0] \builder_csrbank10_load0_re + assign $0\main_libresocsim_timer_reload_re[0:0] \builder_csrbank10_reload0_re + assign $0\main_libresocsim_timer_en_re[0:0] \builder_csrbank10_en0_re + assign $0\main_libresocsim_timer_update_value_re[0:0] \builder_csrbank10_update_value0_re + assign $0\main_libresocsim_timer_eventmanager_re[0:0] \builder_csrbank10_ev_enable0_re + assign $0\builder_interface11_bank_bus_dat_r[7:0] 8'00000000 + assign $0\main_libresocsim_uart_eventmanager_re[0:0] \builder_csrbank11_ev_enable0_re + assign $0\builder_interface12_bank_bus_dat_r[7:0] 8'00000000 + assign $0\main_libresocsim_re[0:0] \builder_csrbank12_tuning_word0_re + assign $0\builder_multiregimpl0_regs0[0:0] \serial_rx + assign $0\builder_multiregimpl0_regs1[0:0] \builder_multiregimpl0_regs0 + assign $0\builder_multiregimpl1_regs0[7:0] \gpio_in + assign $0\builder_multiregimpl1_regs1[7:0] \builder_multiregimpl1_regs0 + assign $0\builder_multiregimpl2_regs0[7:0] \gpio_out + assign $0\builder_multiregimpl2_regs1[7:0] \builder_multiregimpl2_regs0 + attribute \src "build/ls180/gateware/ls180.v:7056.2-7058.5" + switch $or$build/ls180/gateware/ls180.v:7056$2188_Y + attribute \src "build/ls180/gateware/ls180.v:7056.6-7056.94" + case 1'1 + assign $0\main_libresocsim_converter0_dat_r[63:0] \main_libresocsim_libresoc_ibus_dat_r + case + end + attribute \src "build/ls180/gateware/ls180.v:7060.2-7062.5" + switch \main_libresocsim_converter0_counter_converter0_next_value_ce + attribute \src "build/ls180/gateware/ls180.v:7060.6-7060.66" + case 1'1 + assign $0\main_libresocsim_converter0_counter[0:0] \main_libresocsim_converter0_counter_converter0_next_value + case + end + attribute \src "build/ls180/gateware/ls180.v:7063.2-7066.5" + switch \main_libresocsim_converter0_reset + attribute \src "build/ls180/gateware/ls180.v:7063.6-7063.39" + case 1'1 + assign $0\main_libresocsim_converter0_counter[0:0] 1'0 + assign $0\builder_converter0_state[0:0] 1'0 + case + end + attribute \src "build/ls180/gateware/ls180.v:7067.2-7069.5" + switch $or$build/ls180/gateware/ls180.v:7067$2189_Y + attribute \src "build/ls180/gateware/ls180.v:7067.6-7067.94" + case 1'1 + assign $0\main_libresocsim_converter1_dat_r[63:0] \main_libresocsim_libresoc_dbus_dat_r + case + end + attribute \src "build/ls180/gateware/ls180.v:7071.2-7073.5" + switch \main_libresocsim_converter1_counter_converter1_next_value_ce + attribute \src "build/ls180/gateware/ls180.v:7071.6-7071.66" + case 1'1 + assign $0\main_libresocsim_converter1_counter[0:0] \main_libresocsim_converter1_counter_converter1_next_value + case + end + attribute \src "build/ls180/gateware/ls180.v:7074.2-7077.5" + switch \main_libresocsim_converter1_reset + attribute \src "build/ls180/gateware/ls180.v:7074.6-7074.39" + case 1'1 + assign $0\main_libresocsim_converter1_counter[0:0] 1'0 + assign $0\builder_converter1_state[0:0] 1'0 + case + end + attribute \src "build/ls180/gateware/ls180.v:7078.2-7082.5" + switch $ne$build/ls180/gateware/ls180.v:7078$2190_Y + attribute \src "build/ls180/gateware/ls180.v:7078.6-7078.67" + case 1'1 + attribute \src "build/ls180/gateware/ls180.v:7079.3-7081.6" + switch \main_libresocsim_soccontroller_bus_error + attribute \src "build/ls180/gateware/ls180.v:7079.7-7079.47" + case 1'1 + assign $0\main_libresocsim_soccontroller_bus_errors[31:0] $add$build/ls180/gateware/ls180.v:7080$2191_Y + case + end + case + end + attribute \src "build/ls180/gateware/ls180.v:7084.2-7086.5" + switch $and$build/ls180/gateware/ls180.v:7084$2194_Y + attribute \src "build/ls180/gateware/ls180.v:7084.6-7084.103" + case 1'1 + assign $0\main_libresocsim_ram_bus_ack[0:0] 1'1 + case + end + attribute \src "build/ls180/gateware/ls180.v:7088.2-7109.5" + switch $and$build/ls180/gateware/ls180.v:7088$2198_Y + attribute \src "build/ls180/gateware/ls180.v:7088.6-7088.100" + case 1'1 + assign $0\main_libresocsim_tx_reg[7:0] \main_libresocsim_sink_payload_data + assign $0\main_libresocsim_tx_bitcount[3:0] 4'0000 + assign $0\main_libresocsim_tx_busy[0:0] 1'1 + assign $0\serial_tx[0:0] 1'0 + attribute \src "build/ls180/gateware/ls180.v:7093.6-7093.10" + case + attribute \src "build/ls180/gateware/ls180.v:7094.3-7108.6" + switch $and$build/ls180/gateware/ls180.v:7094$2199_Y + attribute \src "build/ls180/gateware/ls180.v:7094.7-7094.66" + case 1'1 + assign $0\main_libresocsim_tx_bitcount[3:0] $add$build/ls180/gateware/ls180.v:7095$2200_Y + attribute \src "build/ls180/gateware/ls180.v:7096.4-7107.7" + switch $eq$build/ls180/gateware/ls180.v:7096$2201_Y + attribute \src "build/ls180/gateware/ls180.v:7096.8-7096.46" + case 1'1 + assign $0\serial_tx[0:0] 1'1 + attribute \src "build/ls180/gateware/ls180.v:7098.8-7098.12" + case + attribute \src "build/ls180/gateware/ls180.v:7099.5-7106.8" + switch $eq$build/ls180/gateware/ls180.v:7099$2202_Y + attribute \src "build/ls180/gateware/ls180.v:7099.9-7099.47" + case 1'1 + assign $0\serial_tx[0:0] 1'1 + assign $0\main_libresocsim_tx_busy[0:0] 1'0 + assign $0\main_libresocsim_sink_ready[0:0] 1'1 + attribute \src "build/ls180/gateware/ls180.v:7103.9-7103.13" + case + assign $0\serial_tx[0:0] \main_libresocsim_tx_reg [0] + assign $0\main_libresocsim_tx_reg[7:0] { 1'0 \main_libresocsim_tx_reg [7:1] } + end + end + case + end + end + attribute \src "build/ls180/gateware/ls180.v:7110.2-7114.5" + switch \main_libresocsim_tx_busy + attribute \src "build/ls180/gateware/ls180.v:7110.6-7110.30" + case 1'1 + assign { $0\main_libresocsim_uart_clk_txen[0:0] $0\main_libresocsim_phase_accumulator_tx[31:0] } $add$build/ls180/gateware/ls180.v:7111$2203_Y + attribute \src "build/ls180/gateware/ls180.v:7112.6-7112.10" + case + assign { $0\main_libresocsim_uart_clk_txen[0:0] $0\main_libresocsim_phase_accumulator_tx[31:0] } { 1'0 \main_libresocsim_storage } + end + attribute \src "build/ls180/gateware/ls180.v:7117.2-7141.5" + switch $not$build/ls180/gateware/ls180.v:7117$2204_Y + attribute \src "build/ls180/gateware/ls180.v:7117.6-7117.33" + case 1'1 + attribute \src "build/ls180/gateware/ls180.v:7118.3-7121.6" + switch $and$build/ls180/gateware/ls180.v:7118$2206_Y + attribute \src "build/ls180/gateware/ls180.v:7118.7-7118.55" + case 1'1 + assign $0\main_libresocsim_rx_busy[0:0] 1'1 + assign $0\main_libresocsim_rx_bitcount[3:0] 4'0000 + case + end + attribute \src "build/ls180/gateware/ls180.v:7122.6-7122.10" + case + attribute \src "build/ls180/gateware/ls180.v:7123.3-7140.6" + switch \main_libresocsim_uart_clk_rxen + attribute \src "build/ls180/gateware/ls180.v:7123.7-7123.37" + case 1'1 + assign $0\main_libresocsim_rx_bitcount[3:0] $add$build/ls180/gateware/ls180.v:7124$2207_Y + attribute \src "build/ls180/gateware/ls180.v:7125.4-7139.7" + switch $eq$build/ls180/gateware/ls180.v:7125$2208_Y + attribute \src "build/ls180/gateware/ls180.v:7125.8-7125.46" + case 1'1 + attribute \src "build/ls180/gateware/ls180.v:7126.5-7128.8" + switch \main_libresocsim_rx + attribute \src "build/ls180/gateware/ls180.v:7126.9-7126.28" + case 1'1 + assign $0\main_libresocsim_rx_busy[0:0] 1'0 + case + end + attribute \src "build/ls180/gateware/ls180.v:7129.8-7129.12" + case + attribute \src "build/ls180/gateware/ls180.v:7130.5-7138.8" + switch $eq$build/ls180/gateware/ls180.v:7130$2209_Y + attribute \src "build/ls180/gateware/ls180.v:7130.9-7130.47" + case 1'1 + assign $0\main_libresocsim_rx_busy[0:0] 1'0 + attribute \src "build/ls180/gateware/ls180.v:7132.6-7135.9" + switch \main_libresocsim_rx + attribute \src "build/ls180/gateware/ls180.v:7132.10-7132.29" + case 1'1 + assign $0\main_libresocsim_source_payload_data[7:0] \main_libresocsim_rx_reg + assign $0\main_libresocsim_source_valid[0:0] 1'1 + case + end + attribute \src "build/ls180/gateware/ls180.v:7136.9-7136.13" + case + assign $0\main_libresocsim_rx_reg[7:0] { \main_libresocsim_rx \main_libresocsim_rx_reg [7:1] } + end + end + case + end + end + attribute \src "build/ls180/gateware/ls180.v:7142.2-7146.5" + switch \main_libresocsim_rx_busy + attribute \src "build/ls180/gateware/ls180.v:7142.6-7142.30" + case 1'1 + assign { $0\main_libresocsim_uart_clk_rxen[0:0] $0\main_libresocsim_phase_accumulator_rx[31:0] } $add$build/ls180/gateware/ls180.v:7143$2210_Y + attribute \src "build/ls180/gateware/ls180.v:7144.6-7144.10" + case + assign { $0\main_libresocsim_uart_clk_rxen[0:0] $0\main_libresocsim_phase_accumulator_rx[31:0] } 33'010000000000000000000000000000000 + end + attribute \src "build/ls180/gateware/ls180.v:7147.2-7149.5" + switch \main_libresocsim_uart_tx_clear + attribute \src "build/ls180/gateware/ls180.v:7147.6-7147.36" + case 1'1 + assign $0\main_libresocsim_uart_tx_pending[0:0] 1'0 + case + end + attribute \src "build/ls180/gateware/ls180.v:7151.2-7153.5" + switch $and$build/ls180/gateware/ls180.v:7151$2212_Y + attribute \src "build/ls180/gateware/ls180.v:7151.6-7151.82" + case 1'1 + assign $0\main_libresocsim_uart_tx_pending[0:0] 1'1 + case + end + attribute \src "build/ls180/gateware/ls180.v:7154.2-7156.5" + switch \main_libresocsim_uart_rx_clear + attribute \src "build/ls180/gateware/ls180.v:7154.6-7154.36" + case 1'1 + assign $0\main_libresocsim_uart_rx_pending[0:0] 1'0 + case + end + attribute \src "build/ls180/gateware/ls180.v:7158.2-7160.5" + switch $and$build/ls180/gateware/ls180.v:7158$2214_Y + attribute \src "build/ls180/gateware/ls180.v:7158.6-7158.82" + case 1'1 + assign $0\main_libresocsim_uart_rx_pending[0:0] 1'1 + case + end + attribute \src "build/ls180/gateware/ls180.v:7161.2-7167.5" + switch \main_libresocsim_uart_tx_fifo_syncfifo_re + attribute \src "build/ls180/gateware/ls180.v:7161.6-7161.47" + case 1'1 + assign $0\main_libresocsim_uart_tx_fifo_readable[0:0] 1'1 + attribute \src "build/ls180/gateware/ls180.v:7163.6-7163.10" + case + attribute \src "build/ls180/gateware/ls180.v:7164.3-7166.6" + switch \main_libresocsim_uart_tx_fifo_re + attribute \src "build/ls180/gateware/ls180.v:7164.7-7164.39" + case 1'1 + assign $0\main_libresocsim_uart_tx_fifo_readable[0:0] 1'0 + case + end + end + attribute \src "build/ls180/gateware/ls180.v:7168.2-7170.5" + switch $and$build/ls180/gateware/ls180.v:7168$2217_Y + attribute \src "build/ls180/gateware/ls180.v:7168.6-7168.144" + case 1'1 + assign $0\main_libresocsim_uart_tx_fifo_produce[3:0] $add$build/ls180/gateware/ls180.v:7169$2218_Y + case + end + attribute \src "build/ls180/gateware/ls180.v:7171.2-7173.5" + switch \main_libresocsim_uart_tx_fifo_do_read + attribute \src "build/ls180/gateware/ls180.v:7171.6-7171.43" + case 1'1 + assign $0\main_libresocsim_uart_tx_fifo_consume[3:0] $add$build/ls180/gateware/ls180.v:7172$2219_Y + case + end + attribute \src "build/ls180/gateware/ls180.v:7174.2-7182.5" + switch $and$build/ls180/gateware/ls180.v:7174$2222_Y + attribute \src "build/ls180/gateware/ls180.v:7174.6-7174.144" + case 1'1 + attribute \src "build/ls180/gateware/ls180.v:7175.3-7177.6" + switch $not$build/ls180/gateware/ls180.v:7175$2223_Y + attribute \src "build/ls180/gateware/ls180.v:7175.7-7175.47" + case 1'1 + assign $0\main_libresocsim_uart_tx_fifo_level0[4:0] $add$build/ls180/gateware/ls180.v:7176$2224_Y + case + end + attribute \src "build/ls180/gateware/ls180.v:7178.6-7178.10" + case + attribute \src "build/ls180/gateware/ls180.v:7179.3-7181.6" + switch \main_libresocsim_uart_tx_fifo_do_read + attribute \src "build/ls180/gateware/ls180.v:7179.7-7179.44" + case 1'1 + assign $0\main_libresocsim_uart_tx_fifo_level0[4:0] $sub$build/ls180/gateware/ls180.v:7180$2225_Y + case + end + end + attribute \src "build/ls180/gateware/ls180.v:7183.2-7189.5" + switch \main_libresocsim_uart_rx_fifo_syncfifo_re + attribute \src "build/ls180/gateware/ls180.v:7183.6-7183.47" + case 1'1 + assign $0\main_libresocsim_uart_rx_fifo_readable[0:0] 1'1 + attribute \src "build/ls180/gateware/ls180.v:7185.6-7185.10" + case + attribute \src "build/ls180/gateware/ls180.v:7186.3-7188.6" + switch \main_libresocsim_uart_rx_fifo_re + attribute \src "build/ls180/gateware/ls180.v:7186.7-7186.39" + case 1'1 + assign $0\main_libresocsim_uart_rx_fifo_readable[0:0] 1'0 + case + end + end + attribute \src "build/ls180/gateware/ls180.v:7190.2-7192.5" + switch $and$build/ls180/gateware/ls180.v:7190$2228_Y + attribute \src "build/ls180/gateware/ls180.v:7190.6-7190.144" + case 1'1 + assign $0\main_libresocsim_uart_rx_fifo_produce[3:0] $add$build/ls180/gateware/ls180.v:7191$2229_Y + case + end + attribute \src "build/ls180/gateware/ls180.v:7193.2-7195.5" + switch \main_libresocsim_uart_rx_fifo_do_read + attribute \src "build/ls180/gateware/ls180.v:7193.6-7193.43" + case 1'1 + assign $0\main_libresocsim_uart_rx_fifo_consume[3:0] $add$build/ls180/gateware/ls180.v:7194$2230_Y + case + end + attribute \src "build/ls180/gateware/ls180.v:7196.2-7204.5" + switch $and$build/ls180/gateware/ls180.v:7196$2233_Y + attribute \src "build/ls180/gateware/ls180.v:7196.6-7196.144" + case 1'1 + attribute \src "build/ls180/gateware/ls180.v:7197.3-7199.6" + switch $not$build/ls180/gateware/ls180.v:7197$2234_Y + attribute \src "build/ls180/gateware/ls180.v:7197.7-7197.47" + case 1'1 + assign $0\main_libresocsim_uart_rx_fifo_level0[4:0] $add$build/ls180/gateware/ls180.v:7198$2235_Y + case + end + attribute \src "build/ls180/gateware/ls180.v:7200.6-7200.10" + case + attribute \src "build/ls180/gateware/ls180.v:7201.3-7203.6" + switch \main_libresocsim_uart_rx_fifo_do_read + attribute \src "build/ls180/gateware/ls180.v:7201.7-7201.44" + case 1'1 + assign $0\main_libresocsim_uart_rx_fifo_level0[4:0] $sub$build/ls180/gateware/ls180.v:7202$2236_Y + case + end + end + attribute \src "build/ls180/gateware/ls180.v:7205.2-7218.5" + switch \main_libresocsim_uart_reset + attribute \src "build/ls180/gateware/ls180.v:7205.6-7205.33" + case 1'1 + assign $0\main_libresocsim_uart_tx_pending[0:0] 1'0 + assign $0\main_libresocsim_uart_tx_old_trigger[0:0] 1'0 + assign $0\main_libresocsim_uart_rx_pending[0:0] 1'0 + assign $0\main_libresocsim_uart_rx_old_trigger[0:0] 1'0 + assign $0\main_libresocsim_uart_tx_fifo_readable[0:0] 1'0 + assign $0\main_libresocsim_uart_tx_fifo_level0[4:0] 5'00000 + assign $0\main_libresocsim_uart_tx_fifo_produce[3:0] 4'0000 + assign $0\main_libresocsim_uart_tx_fifo_consume[3:0] 4'0000 + assign $0\main_libresocsim_uart_rx_fifo_readable[0:0] 1'0 + assign $0\main_libresocsim_uart_rx_fifo_level0[4:0] 5'00000 + assign $0\main_libresocsim_uart_rx_fifo_produce[3:0] 4'0000 + assign $0\main_libresocsim_uart_rx_fifo_consume[3:0] 4'0000 + case + end + attribute \src "build/ls180/gateware/ls180.v:7219.2-7227.5" + switch \main_libresocsim_timer_en_storage + attribute \src "build/ls180/gateware/ls180.v:7219.6-7219.39" + case 1'1 + attribute \src "build/ls180/gateware/ls180.v:7220.3-7224.6" + switch $eq$build/ls180/gateware/ls180.v:7220$2237_Y + attribute \src "build/ls180/gateware/ls180.v:7220.7-7220.45" + case 1'1 + assign $0\main_libresocsim_timer_value[31:0] \main_libresocsim_timer_reload_storage + attribute \src "build/ls180/gateware/ls180.v:7222.7-7222.11" + case + assign $0\main_libresocsim_timer_value[31:0] $sub$build/ls180/gateware/ls180.v:7223$2238_Y + end + attribute \src "build/ls180/gateware/ls180.v:7225.6-7225.10" + case + assign $0\main_libresocsim_timer_value[31:0] \main_libresocsim_timer_load_storage + end + attribute \src "build/ls180/gateware/ls180.v:7228.2-7230.5" + switch \main_libresocsim_timer_update_value_re + attribute \src "build/ls180/gateware/ls180.v:7228.6-7228.44" + case 1'1 + assign $0\main_libresocsim_timer_value_status[31:0] \main_libresocsim_timer_value + case + end + attribute \src "build/ls180/gateware/ls180.v:7231.2-7233.5" + switch \main_libresocsim_timer_zero_clear + attribute \src "build/ls180/gateware/ls180.v:7231.6-7231.39" + case 1'1 + assign $0\main_libresocsim_timer_zero_pending[0:0] 1'0 + case + end + attribute \src "build/ls180/gateware/ls180.v:7235.2-7237.5" + switch $and$build/ls180/gateware/ls180.v:7235$2240_Y + attribute \src "build/ls180/gateware/ls180.v:7235.6-7235.88" + case 1'1 + assign $0\main_libresocsim_timer_zero_pending[0:0] 1'1 + case + end + attribute \src "build/ls180/gateware/ls180.v:7240.2-7242.5" + switch \main_sdram_inti_p0_rddata_valid + attribute \src "build/ls180/gateware/ls180.v:7240.6-7240.37" + case 1'1 + assign $0\main_sdram_status[15:0] \main_sdram_inti_p0_rddata + case + end + attribute \src "build/ls180/gateware/ls180.v:7243.2-7247.5" + switch $and$build/ls180/gateware/ls180.v:7243$2242_Y + attribute \src "build/ls180/gateware/ls180.v:7243.6-7243.57" + case 1'1 + assign $0\main_sdram_timer_count1[9:0] $sub$build/ls180/gateware/ls180.v:7244$2243_Y + attribute \src "build/ls180/gateware/ls180.v:7245.6-7245.10" + case + assign $0\main_sdram_timer_count1[9:0] 10'1100001101 + end + attribute \src "build/ls180/gateware/ls180.v:7249.2-7255.5" + switch \main_sdram_postponer_req_i + attribute \src "build/ls180/gateware/ls180.v:7249.6-7249.32" + case 1'1 + assign $0\main_sdram_postponer_count[0:0] $sub$build/ls180/gateware/ls180.v:7250$2244_Y + attribute \src "build/ls180/gateware/ls180.v:7251.3-7254.6" + switch $eq$build/ls180/gateware/ls180.v:7251$2245_Y + attribute \src "build/ls180/gateware/ls180.v:7251.7-7251.43" + case 1'1 + assign $0\main_sdram_postponer_count[0:0] 1'0 + assign $0\main_sdram_postponer_req_o[0:0] 1'1 + case + end + case + end + attribute \src "build/ls180/gateware/ls180.v:7256.2-7264.5" + switch \main_sdram_sequencer_start0 + attribute \src "build/ls180/gateware/ls180.v:7256.6-7256.33" + case 1'1 + assign $0\main_sdram_sequencer_count[0:0] 1'0 + attribute \src "build/ls180/gateware/ls180.v:7258.6-7258.10" + case + attribute \src "build/ls180/gateware/ls180.v:7259.3-7263.6" + switch \main_sdram_sequencer_done1 + attribute \src "build/ls180/gateware/ls180.v:7259.7-7259.33" + case 1'1 + attribute \src "build/ls180/gateware/ls180.v:7260.4-7262.7" + switch $ne$build/ls180/gateware/ls180.v:7260$2246_Y + attribute \src "build/ls180/gateware/ls180.v:7260.8-7260.44" + case 1'1 + assign $0\main_sdram_sequencer_count[0:0] $sub$build/ls180/gateware/ls180.v:7261$2247_Y + case + end + case + end + end + attribute \src "build/ls180/gateware/ls180.v:7271.2-7277.5" + switch $and$build/ls180/gateware/ls180.v:7271$2249_Y + attribute \src "build/ls180/gateware/ls180.v:7271.6-7271.76" + case 1'1 + assign $0\main_sdram_cmd_payload_a[12:0] 13'0010000000000 + assign $0\main_sdram_cmd_payload_ba[1:0] 2'00 + assign $0\main_sdram_cmd_payload_cas[0:0] 1'0 + assign $0\main_sdram_cmd_payload_ras[0:0] 1'1 + assign $0\main_sdram_cmd_payload_we[0:0] 1'1 + case + end + attribute \src "build/ls180/gateware/ls180.v:7278.2-7284.5" + switch $eq$build/ls180/gateware/ls180.v:7278$2250_Y + attribute \src "build/ls180/gateware/ls180.v:7278.6-7278.44" + case 1'1 + assign $0\main_sdram_cmd_payload_a[12:0] 13'0000000000000 + assign $0\main_sdram_cmd_payload_ba[1:0] 2'00 + assign $0\main_sdram_cmd_payload_cas[0:0] 1'1 + assign $0\main_sdram_cmd_payload_ras[0:0] 1'1 + assign $0\main_sdram_cmd_payload_we[0:0] 1'0 + case + end + attribute \src "build/ls180/gateware/ls180.v:7285.2-7292.5" + switch $eq$build/ls180/gateware/ls180.v:7285$2251_Y + attribute \src "build/ls180/gateware/ls180.v:7285.6-7285.44" + case 1'1 + assign $0\main_sdram_cmd_payload_a[12:0] 13'0000000000000 + assign $0\main_sdram_cmd_payload_ba[1:0] 2'00 + assign $0\main_sdram_cmd_payload_cas[0:0] 1'0 + assign $0\main_sdram_cmd_payload_ras[0:0] 1'0 + assign $0\main_sdram_cmd_payload_we[0:0] 1'0 + assign $0\main_sdram_sequencer_done1[0:0] 1'1 + case + end + attribute \src "build/ls180/gateware/ls180.v:7293.2-7303.5" + switch $eq$build/ls180/gateware/ls180.v:7293$2252_Y + attribute \src "build/ls180/gateware/ls180.v:7293.6-7293.44" + case 1'1 + assign $0\main_sdram_sequencer_counter[3:0] 4'0000 + attribute \src "build/ls180/gateware/ls180.v:7295.6-7295.10" + case + attribute \src "build/ls180/gateware/ls180.v:7296.3-7302.6" + switch $ne$build/ls180/gateware/ls180.v:7296$2253_Y + attribute \src "build/ls180/gateware/ls180.v:7296.7-7296.45" + case 1'1 + assign $0\main_sdram_sequencer_counter[3:0] $add$build/ls180/gateware/ls180.v:7297$2254_Y + attribute \src "build/ls180/gateware/ls180.v:7298.7-7298.11" + case + attribute \src "build/ls180/gateware/ls180.v:7299.4-7301.7" + switch \main_sdram_sequencer_start1 + attribute \src "build/ls180/gateware/ls180.v:7299.8-7299.35" + case 1'1 + assign $0\main_sdram_sequencer_counter[3:0] 4'0001 + case + end + end + end + attribute \src "build/ls180/gateware/ls180.v:7305.2-7312.5" + switch \main_sdram_bankmachine0_row_close + attribute \src "build/ls180/gateware/ls180.v:7305.6-7305.39" + case 1'1 + assign $0\main_sdram_bankmachine0_row_opened[0:0] 1'0 + attribute \src "build/ls180/gateware/ls180.v:7307.6-7307.10" + case + attribute \src "build/ls180/gateware/ls180.v:7308.3-7311.6" + switch \main_sdram_bankmachine0_row_open + attribute \src "build/ls180/gateware/ls180.v:7308.7-7308.39" + case 1'1 + assign $0\main_sdram_bankmachine0_row_opened[0:0] 1'1 + assign $0\main_sdram_bankmachine0_row[12:0] \main_sdram_bankmachine0_cmd_buffer_source_payload_addr [21:9] + case + end + end + attribute \src "build/ls180/gateware/ls180.v:7313.2-7315.5" + switch $and$build/ls180/gateware/ls180.v:7313$2257_Y + attribute \src "build/ls180/gateware/ls180.v:7313.6-7313.191" + case 1'1 + assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_produce[2:0] $add$build/ls180/gateware/ls180.v:7314$2258_Y + case + end + attribute \src "build/ls180/gateware/ls180.v:7316.2-7318.5" + switch \main_sdram_bankmachine0_cmd_buffer_lookahead_do_read + attribute \src "build/ls180/gateware/ls180.v:7316.6-7316.58" + case 1'1 + assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_consume[2:0] $add$build/ls180/gateware/ls180.v:7317$2259_Y + case + end + attribute \src "build/ls180/gateware/ls180.v:7319.2-7327.5" + switch $and$build/ls180/gateware/ls180.v:7319$2262_Y + attribute \src "build/ls180/gateware/ls180.v:7319.6-7319.191" + case 1'1 + attribute \src "build/ls180/gateware/ls180.v:7320.3-7322.6" + switch $not$build/ls180/gateware/ls180.v:7320$2263_Y + attribute \src "build/ls180/gateware/ls180.v:7320.7-7320.62" + case 1'1 + assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_level[3:0] $add$build/ls180/gateware/ls180.v:7321$2264_Y + case + end + attribute \src "build/ls180/gateware/ls180.v:7323.6-7323.10" + case + attribute \src "build/ls180/gateware/ls180.v:7324.3-7326.6" + switch \main_sdram_bankmachine0_cmd_buffer_lookahead_do_read + attribute \src "build/ls180/gateware/ls180.v:7324.7-7324.59" + case 1'1 + assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_level[3:0] $sub$build/ls180/gateware/ls180.v:7325$2265_Y + case + end + end + attribute \src "build/ls180/gateware/ls180.v:7328.2-7334.5" + switch $or$build/ls180/gateware/ls180.v:7328$2267_Y + attribute \src "build/ls180/gateware/ls180.v:7328.6-7328.108" + case 1'1 + assign $0\main_sdram_bankmachine0_cmd_buffer_source_valid[0:0] \main_sdram_bankmachine0_cmd_buffer_sink_valid + assign $0\main_sdram_bankmachine0_cmd_buffer_source_first[0:0] \main_sdram_bankmachine0_cmd_buffer_sink_first + assign $0\main_sdram_bankmachine0_cmd_buffer_source_last[0:0] \main_sdram_bankmachine0_cmd_buffer_sink_last + assign $0\main_sdram_bankmachine0_cmd_buffer_source_payload_we[0:0] \main_sdram_bankmachine0_cmd_buffer_sink_payload_we + assign $0\main_sdram_bankmachine0_cmd_buffer_source_payload_addr[21:0] \main_sdram_bankmachine0_cmd_buffer_sink_payload_addr + case + end + attribute \src "build/ls180/gateware/ls180.v:7335.2-7349.5" + switch \main_sdram_bankmachine0_twtpcon_valid + attribute \src "build/ls180/gateware/ls180.v:7335.6-7335.43" + case 1'1 + assign $0\main_sdram_bankmachine0_twtpcon_count[2:0] 3'100 + attribute \src "build/ls180/gateware/ls180.v:7337.3-7341.6" + switch 1'0 + attribute \src "build/ls180/gateware/ls180.v:7339.7-7339.11" + case + assign $0\main_sdram_bankmachine0_twtpcon_ready[0:0] 1'0 + end + attribute \src "build/ls180/gateware/ls180.v:7342.6-7342.10" + case + attribute \src "build/ls180/gateware/ls180.v:7343.3-7348.6" + switch $not$build/ls180/gateware/ls180.v:7343$2268_Y + attribute \src "build/ls180/gateware/ls180.v:7343.7-7343.47" + case 1'1 + assign $0\main_sdram_bankmachine0_twtpcon_count[2:0] $sub$build/ls180/gateware/ls180.v:7344$2269_Y + attribute \src "build/ls180/gateware/ls180.v:7345.4-7347.7" + switch $eq$build/ls180/gateware/ls180.v:7345$2270_Y + attribute \src "build/ls180/gateware/ls180.v:7345.8-7345.55" + case 1'1 + assign $0\main_sdram_bankmachine0_twtpcon_ready[0:0] 1'1 + case + end + case + end + end + attribute \src "build/ls180/gateware/ls180.v:7351.2-7358.5" + switch \main_sdram_bankmachine1_row_close + attribute \src "build/ls180/gateware/ls180.v:7351.6-7351.39" + case 1'1 + assign $0\main_sdram_bankmachine1_row_opened[0:0] 1'0 + attribute \src "build/ls180/gateware/ls180.v:7353.6-7353.10" + case + attribute \src "build/ls180/gateware/ls180.v:7354.3-7357.6" + switch \main_sdram_bankmachine1_row_open + attribute \src "build/ls180/gateware/ls180.v:7354.7-7354.39" + case 1'1 + assign $0\main_sdram_bankmachine1_row_opened[0:0] 1'1 + assign $0\main_sdram_bankmachine1_row[12:0] \main_sdram_bankmachine1_cmd_buffer_source_payload_addr [21:9] + case + end + end + attribute \src "build/ls180/gateware/ls180.v:7359.2-7361.5" + switch $and$build/ls180/gateware/ls180.v:7359$2273_Y + attribute \src "build/ls180/gateware/ls180.v:7359.6-7359.191" + case 1'1 + assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_produce[2:0] $add$build/ls180/gateware/ls180.v:7360$2274_Y + case + end + attribute \src "build/ls180/gateware/ls180.v:7362.2-7364.5" + switch \main_sdram_bankmachine1_cmd_buffer_lookahead_do_read + attribute \src "build/ls180/gateware/ls180.v:7362.6-7362.58" + case 1'1 + assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_consume[2:0] $add$build/ls180/gateware/ls180.v:7363$2275_Y + case + end + attribute \src "build/ls180/gateware/ls180.v:7365.2-7373.5" + switch $and$build/ls180/gateware/ls180.v:7365$2278_Y + attribute \src "build/ls180/gateware/ls180.v:7365.6-7365.191" + case 1'1 + attribute \src "build/ls180/gateware/ls180.v:7366.3-7368.6" + switch $not$build/ls180/gateware/ls180.v:7366$2279_Y + attribute \src "build/ls180/gateware/ls180.v:7366.7-7366.62" + case 1'1 + assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_level[3:0] $add$build/ls180/gateware/ls180.v:7367$2280_Y + case + end + attribute \src "build/ls180/gateware/ls180.v:7369.6-7369.10" + case + attribute \src "build/ls180/gateware/ls180.v:7370.3-7372.6" + switch \main_sdram_bankmachine1_cmd_buffer_lookahead_do_read + attribute \src "build/ls180/gateware/ls180.v:7370.7-7370.59" + case 1'1 + assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_level[3:0] $sub$build/ls180/gateware/ls180.v:7371$2281_Y + case + end + end + attribute \src "build/ls180/gateware/ls180.v:7374.2-7380.5" + switch $or$build/ls180/gateware/ls180.v:7374$2283_Y + attribute \src "build/ls180/gateware/ls180.v:7374.6-7374.108" + case 1'1 + assign $0\main_sdram_bankmachine1_cmd_buffer_source_valid[0:0] \main_sdram_bankmachine1_cmd_buffer_sink_valid + assign $0\main_sdram_bankmachine1_cmd_buffer_source_first[0:0] \main_sdram_bankmachine1_cmd_buffer_sink_first + assign $0\main_sdram_bankmachine1_cmd_buffer_source_last[0:0] \main_sdram_bankmachine1_cmd_buffer_sink_last + assign $0\main_sdram_bankmachine1_cmd_buffer_source_payload_we[0:0] \main_sdram_bankmachine1_cmd_buffer_sink_payload_we + assign $0\main_sdram_bankmachine1_cmd_buffer_source_payload_addr[21:0] \main_sdram_bankmachine1_cmd_buffer_sink_payload_addr + case + end + attribute \src "build/ls180/gateware/ls180.v:7381.2-7395.5" + switch \main_sdram_bankmachine1_twtpcon_valid + attribute \src "build/ls180/gateware/ls180.v:7381.6-7381.43" + case 1'1 + assign $0\main_sdram_bankmachine1_twtpcon_count[2:0] 3'100 + attribute \src "build/ls180/gateware/ls180.v:7383.3-7387.6" + switch 1'0 + attribute \src "build/ls180/gateware/ls180.v:7385.7-7385.11" + case + assign $0\main_sdram_bankmachine1_twtpcon_ready[0:0] 1'0 + end + attribute \src "build/ls180/gateware/ls180.v:7388.6-7388.10" + case + attribute \src "build/ls180/gateware/ls180.v:7389.3-7394.6" + switch $not$build/ls180/gateware/ls180.v:7389$2284_Y + attribute \src "build/ls180/gateware/ls180.v:7389.7-7389.47" + case 1'1 + assign $0\main_sdram_bankmachine1_twtpcon_count[2:0] $sub$build/ls180/gateware/ls180.v:7390$2285_Y + attribute \src "build/ls180/gateware/ls180.v:7391.4-7393.7" + switch $eq$build/ls180/gateware/ls180.v:7391$2286_Y + attribute \src "build/ls180/gateware/ls180.v:7391.8-7391.55" + case 1'1 + assign $0\main_sdram_bankmachine1_twtpcon_ready[0:0] 1'1 + case + end + case + end + end + attribute \src "build/ls180/gateware/ls180.v:7397.2-7404.5" + switch \main_sdram_bankmachine2_row_close + attribute \src "build/ls180/gateware/ls180.v:7397.6-7397.39" + case 1'1 + assign $0\main_sdram_bankmachine2_row_opened[0:0] 1'0 + attribute \src "build/ls180/gateware/ls180.v:7399.6-7399.10" + case + attribute \src "build/ls180/gateware/ls180.v:7400.3-7403.6" + switch \main_sdram_bankmachine2_row_open + attribute \src "build/ls180/gateware/ls180.v:7400.7-7400.39" + case 1'1 + assign $0\main_sdram_bankmachine2_row_opened[0:0] 1'1 + assign $0\main_sdram_bankmachine2_row[12:0] \main_sdram_bankmachine2_cmd_buffer_source_payload_addr [21:9] + case + end + end + attribute \src "build/ls180/gateware/ls180.v:7405.2-7407.5" + switch $and$build/ls180/gateware/ls180.v:7405$2289_Y + attribute \src "build/ls180/gateware/ls180.v:7405.6-7405.191" + case 1'1 + assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_produce[2:0] $add$build/ls180/gateware/ls180.v:7406$2290_Y + case + end + attribute \src "build/ls180/gateware/ls180.v:7408.2-7410.5" + switch \main_sdram_bankmachine2_cmd_buffer_lookahead_do_read + attribute \src "build/ls180/gateware/ls180.v:7408.6-7408.58" + case 1'1 + assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_consume[2:0] $add$build/ls180/gateware/ls180.v:7409$2291_Y + case + end + attribute \src "build/ls180/gateware/ls180.v:7411.2-7419.5" + switch $and$build/ls180/gateware/ls180.v:7411$2294_Y + attribute \src "build/ls180/gateware/ls180.v:7411.6-7411.191" + case 1'1 + attribute \src "build/ls180/gateware/ls180.v:7412.3-7414.6" + switch $not$build/ls180/gateware/ls180.v:7412$2295_Y + attribute \src "build/ls180/gateware/ls180.v:7412.7-7412.62" + case 1'1 + assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_level[3:0] $add$build/ls180/gateware/ls180.v:7413$2296_Y + case + end + attribute \src "build/ls180/gateware/ls180.v:7415.6-7415.10" + case + attribute \src "build/ls180/gateware/ls180.v:7416.3-7418.6" + switch \main_sdram_bankmachine2_cmd_buffer_lookahead_do_read + attribute \src "build/ls180/gateware/ls180.v:7416.7-7416.59" + case 1'1 + assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_level[3:0] $sub$build/ls180/gateware/ls180.v:7417$2297_Y + case + end + end + attribute \src "build/ls180/gateware/ls180.v:7420.2-7426.5" + switch $or$build/ls180/gateware/ls180.v:7420$2299_Y + attribute \src "build/ls180/gateware/ls180.v:7420.6-7420.108" + case 1'1 + assign $0\main_sdram_bankmachine2_cmd_buffer_source_valid[0:0] \main_sdram_bankmachine2_cmd_buffer_sink_valid + assign $0\main_sdram_bankmachine2_cmd_buffer_source_first[0:0] \main_sdram_bankmachine2_cmd_buffer_sink_first + assign $0\main_sdram_bankmachine2_cmd_buffer_source_last[0:0] \main_sdram_bankmachine2_cmd_buffer_sink_last + assign $0\main_sdram_bankmachine2_cmd_buffer_source_payload_we[0:0] \main_sdram_bankmachine2_cmd_buffer_sink_payload_we + assign $0\main_sdram_bankmachine2_cmd_buffer_source_payload_addr[21:0] \main_sdram_bankmachine2_cmd_buffer_sink_payload_addr + case + end + attribute \src "build/ls180/gateware/ls180.v:7427.2-7441.5" + switch \main_sdram_bankmachine2_twtpcon_valid + attribute \src "build/ls180/gateware/ls180.v:7427.6-7427.43" + case 1'1 + assign $0\main_sdram_bankmachine2_twtpcon_count[2:0] 3'100 + attribute \src "build/ls180/gateware/ls180.v:7429.3-7433.6" + switch 1'0 + attribute \src "build/ls180/gateware/ls180.v:7431.7-7431.11" + case + assign $0\main_sdram_bankmachine2_twtpcon_ready[0:0] 1'0 + end + attribute \src "build/ls180/gateware/ls180.v:7434.6-7434.10" + case + attribute \src "build/ls180/gateware/ls180.v:7435.3-7440.6" + switch $not$build/ls180/gateware/ls180.v:7435$2300_Y + attribute \src "build/ls180/gateware/ls180.v:7435.7-7435.47" + case 1'1 + assign $0\main_sdram_bankmachine2_twtpcon_count[2:0] $sub$build/ls180/gateware/ls180.v:7436$2301_Y + attribute \src "build/ls180/gateware/ls180.v:7437.4-7439.7" + switch $eq$build/ls180/gateware/ls180.v:7437$2302_Y + attribute \src "build/ls180/gateware/ls180.v:7437.8-7437.55" + case 1'1 + assign $0\main_sdram_bankmachine2_twtpcon_ready[0:0] 1'1 + case + end + case + end + end + attribute \src "build/ls180/gateware/ls180.v:7443.2-7450.5" + switch \main_sdram_bankmachine3_row_close + attribute \src "build/ls180/gateware/ls180.v:7443.6-7443.39" + case 1'1 + assign $0\main_sdram_bankmachine3_row_opened[0:0] 1'0 + attribute \src "build/ls180/gateware/ls180.v:7445.6-7445.10" + case + attribute \src "build/ls180/gateware/ls180.v:7446.3-7449.6" + switch \main_sdram_bankmachine3_row_open + attribute \src "build/ls180/gateware/ls180.v:7446.7-7446.39" + case 1'1 + assign $0\main_sdram_bankmachine3_row_opened[0:0] 1'1 + assign $0\main_sdram_bankmachine3_row[12:0] \main_sdram_bankmachine3_cmd_buffer_source_payload_addr [21:9] + case + end + end + attribute \src "build/ls180/gateware/ls180.v:7451.2-7453.5" + switch $and$build/ls180/gateware/ls180.v:7451$2305_Y + attribute \src "build/ls180/gateware/ls180.v:7451.6-7451.191" + case 1'1 + assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_produce[2:0] $add$build/ls180/gateware/ls180.v:7452$2306_Y + case + end + attribute \src "build/ls180/gateware/ls180.v:7454.2-7456.5" + switch \main_sdram_bankmachine3_cmd_buffer_lookahead_do_read + attribute \src "build/ls180/gateware/ls180.v:7454.6-7454.58" + case 1'1 + assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_consume[2:0] $add$build/ls180/gateware/ls180.v:7455$2307_Y + case + end + attribute \src "build/ls180/gateware/ls180.v:7457.2-7465.5" + switch $and$build/ls180/gateware/ls180.v:7457$2310_Y + attribute \src "build/ls180/gateware/ls180.v:7457.6-7457.191" + case 1'1 + attribute \src "build/ls180/gateware/ls180.v:7458.3-7460.6" + switch $not$build/ls180/gateware/ls180.v:7458$2311_Y + attribute \src "build/ls180/gateware/ls180.v:7458.7-7458.62" + case 1'1 + assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_level[3:0] $add$build/ls180/gateware/ls180.v:7459$2312_Y + case + end + attribute \src "build/ls180/gateware/ls180.v:7461.6-7461.10" + case + attribute \src "build/ls180/gateware/ls180.v:7462.3-7464.6" + switch \main_sdram_bankmachine3_cmd_buffer_lookahead_do_read + attribute \src "build/ls180/gateware/ls180.v:7462.7-7462.59" + case 1'1 + assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_level[3:0] $sub$build/ls180/gateware/ls180.v:7463$2313_Y + case + end + end + attribute \src "build/ls180/gateware/ls180.v:7466.2-7472.5" + switch $or$build/ls180/gateware/ls180.v:7466$2315_Y + attribute \src "build/ls180/gateware/ls180.v:7466.6-7466.108" + case 1'1 + assign $0\main_sdram_bankmachine3_cmd_buffer_source_valid[0:0] \main_sdram_bankmachine3_cmd_buffer_sink_valid + assign $0\main_sdram_bankmachine3_cmd_buffer_source_first[0:0] \main_sdram_bankmachine3_cmd_buffer_sink_first + assign $0\main_sdram_bankmachine3_cmd_buffer_source_last[0:0] \main_sdram_bankmachine3_cmd_buffer_sink_last + assign $0\main_sdram_bankmachine3_cmd_buffer_source_payload_we[0:0] \main_sdram_bankmachine3_cmd_buffer_sink_payload_we + assign $0\main_sdram_bankmachine3_cmd_buffer_source_payload_addr[21:0] \main_sdram_bankmachine3_cmd_buffer_sink_payload_addr + case + end + attribute \src "build/ls180/gateware/ls180.v:7473.2-7487.5" + switch \main_sdram_bankmachine3_twtpcon_valid + attribute \src "build/ls180/gateware/ls180.v:7473.6-7473.43" + case 1'1 + assign $0\main_sdram_bankmachine3_twtpcon_count[2:0] 3'100 + attribute \src "build/ls180/gateware/ls180.v:7475.3-7479.6" + switch 1'0 + attribute \src "build/ls180/gateware/ls180.v:7477.7-7477.11" + case + assign $0\main_sdram_bankmachine3_twtpcon_ready[0:0] 1'0 + end + attribute \src "build/ls180/gateware/ls180.v:7480.6-7480.10" + case + attribute \src "build/ls180/gateware/ls180.v:7481.3-7486.6" + switch $not$build/ls180/gateware/ls180.v:7481$2316_Y + attribute \src "build/ls180/gateware/ls180.v:7481.7-7481.47" + case 1'1 + assign $0\main_sdram_bankmachine3_twtpcon_count[2:0] $sub$build/ls180/gateware/ls180.v:7482$2317_Y + attribute \src "build/ls180/gateware/ls180.v:7483.4-7485.7" + switch $eq$build/ls180/gateware/ls180.v:7483$2318_Y + attribute \src "build/ls180/gateware/ls180.v:7483.8-7483.55" + case 1'1 + assign $0\main_sdram_bankmachine3_twtpcon_ready[0:0] 1'1 + case + end + case + end + end + attribute \src "build/ls180/gateware/ls180.v:7489.2-7495.5" + switch $not$build/ls180/gateware/ls180.v:7489$2319_Y + attribute \src "build/ls180/gateware/ls180.v:7489.6-7489.23" + case 1'1 + assign $0\main_sdram_time0[4:0] 5'11111 + attribute \src "build/ls180/gateware/ls180.v:7491.6-7491.10" + case + attribute \src "build/ls180/gateware/ls180.v:7492.3-7494.6" + switch $not$build/ls180/gateware/ls180.v:7492$2320_Y + attribute \src "build/ls180/gateware/ls180.v:7492.7-7492.30" + case 1'1 + assign $0\main_sdram_time0[4:0] $sub$build/ls180/gateware/ls180.v:7493$2321_Y + case + end + end + attribute \src "build/ls180/gateware/ls180.v:7496.2-7502.5" + switch $not$build/ls180/gateware/ls180.v:7496$2322_Y + attribute \src "build/ls180/gateware/ls180.v:7496.6-7496.23" + case 1'1 + assign $0\main_sdram_time1[3:0] 4'1111 + attribute \src "build/ls180/gateware/ls180.v:7498.6-7498.10" + case + attribute \src "build/ls180/gateware/ls180.v:7499.3-7501.6" + switch $not$build/ls180/gateware/ls180.v:7499$2323_Y + attribute \src "build/ls180/gateware/ls180.v:7499.7-7499.30" + case 1'1 + assign $0\main_sdram_time1[3:0] $sub$build/ls180/gateware/ls180.v:7500$2324_Y + case + end + end + attribute \src "build/ls180/gateware/ls180.v:7503.2-7558.5" + switch \main_sdram_choose_cmd_ce + attribute \src "build/ls180/gateware/ls180.v:7503.6-7503.30" + case 1'1 + attribute \src "build/ls180/gateware/ls180.v:7504.3-7557.10" + switch \main_sdram_choose_cmd_grant + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case 2'00 + attribute \src "build/ls180/gateware/ls180.v:7506.5-7516.8" + switch \main_sdram_choose_cmd_request [1] + attribute \src "build/ls180/gateware/ls180.v:7506.9-7506.41" + case 1'1 + assign $0\main_sdram_choose_cmd_grant[1:0] 2'01 + attribute \src "build/ls180/gateware/ls180.v:7508.9-7508.13" + case + attribute \src "build/ls180/gateware/ls180.v:7509.6-7515.9" + switch \main_sdram_choose_cmd_request [2] + attribute \src "build/ls180/gateware/ls180.v:7509.10-7509.42" + case 1'1 + assign $0\main_sdram_choose_cmd_grant[1:0] 2'10 + attribute \src "build/ls180/gateware/ls180.v:7511.10-7511.14" + case + attribute \src "build/ls180/gateware/ls180.v:7512.7-7514.10" + switch \main_sdram_choose_cmd_request [3] + attribute \src "build/ls180/gateware/ls180.v:7512.11-7512.43" + case 1'1 + assign $0\main_sdram_choose_cmd_grant[1:0] 2'11 + case + end + end + end + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case 2'01 + attribute \src "build/ls180/gateware/ls180.v:7519.5-7529.8" + switch \main_sdram_choose_cmd_request [2] + attribute \src "build/ls180/gateware/ls180.v:7519.9-7519.41" + case 1'1 + assign $0\main_sdram_choose_cmd_grant[1:0] 2'10 + attribute \src "build/ls180/gateware/ls180.v:7521.9-7521.13" + case + attribute \src "build/ls180/gateware/ls180.v:7522.6-7528.9" + switch \main_sdram_choose_cmd_request [3] + attribute \src "build/ls180/gateware/ls180.v:7522.10-7522.42" + case 1'1 + assign $0\main_sdram_choose_cmd_grant[1:0] 2'11 + attribute \src "build/ls180/gateware/ls180.v:7524.10-7524.14" + case + attribute \src "build/ls180/gateware/ls180.v:7525.7-7527.10" + switch \main_sdram_choose_cmd_request [0] + attribute \src "build/ls180/gateware/ls180.v:7525.11-7525.43" + case 1'1 + assign $0\main_sdram_choose_cmd_grant[1:0] 2'00 + case + end + end + end + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case 2'10 + attribute \src "build/ls180/gateware/ls180.v:7532.5-7542.8" + switch \main_sdram_choose_cmd_request [3] + attribute \src "build/ls180/gateware/ls180.v:7532.9-7532.41" + case 1'1 + assign $0\main_sdram_choose_cmd_grant[1:0] 2'11 + attribute \src "build/ls180/gateware/ls180.v:7534.9-7534.13" + case + attribute \src "build/ls180/gateware/ls180.v:7535.6-7541.9" + switch \main_sdram_choose_cmd_request [0] + attribute \src "build/ls180/gateware/ls180.v:7535.10-7535.42" + case 1'1 + assign $0\main_sdram_choose_cmd_grant[1:0] 2'00 + attribute \src "build/ls180/gateware/ls180.v:7537.10-7537.14" + case + attribute \src "build/ls180/gateware/ls180.v:7538.7-7540.10" + switch \main_sdram_choose_cmd_request [1] + attribute \src "build/ls180/gateware/ls180.v:7538.11-7538.43" + case 1'1 + assign $0\main_sdram_choose_cmd_grant[1:0] 2'01 + case + end + end + end + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case 2'11 + attribute \src "build/ls180/gateware/ls180.v:7545.5-7555.8" + switch \main_sdram_choose_cmd_request [0] + attribute \src "build/ls180/gateware/ls180.v:7545.9-7545.41" + case 1'1 + assign $0\main_sdram_choose_cmd_grant[1:0] 2'00 + attribute \src "build/ls180/gateware/ls180.v:7547.9-7547.13" + case + attribute \src "build/ls180/gateware/ls180.v:7548.6-7554.9" + switch \main_sdram_choose_cmd_request [1] + attribute \src "build/ls180/gateware/ls180.v:7548.10-7548.42" + case 1'1 + assign $0\main_sdram_choose_cmd_grant[1:0] 2'01 + attribute \src "build/ls180/gateware/ls180.v:7550.10-7550.14" + case + attribute \src "build/ls180/gateware/ls180.v:7551.7-7553.10" + switch \main_sdram_choose_cmd_request [2] + attribute \src "build/ls180/gateware/ls180.v:7551.11-7551.43" + case 1'1 + assign $0\main_sdram_choose_cmd_grant[1:0] 2'10 + case + end + end + end + case + end + case + end + attribute \src "build/ls180/gateware/ls180.v:7559.2-7614.5" + switch \main_sdram_choose_req_ce + attribute \src "build/ls180/gateware/ls180.v:7559.6-7559.30" + case 1'1 + attribute \src "build/ls180/gateware/ls180.v:7560.3-7613.10" + switch \main_sdram_choose_req_grant + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case 2'00 + attribute \src "build/ls180/gateware/ls180.v:7562.5-7572.8" + switch \main_sdram_choose_req_request [1] + attribute \src "build/ls180/gateware/ls180.v:7562.9-7562.41" + case 1'1 + assign $0\main_sdram_choose_req_grant[1:0] 2'01 + attribute \src "build/ls180/gateware/ls180.v:7564.9-7564.13" + case + attribute \src "build/ls180/gateware/ls180.v:7565.6-7571.9" + switch \main_sdram_choose_req_request [2] + attribute \src "build/ls180/gateware/ls180.v:7565.10-7565.42" + case 1'1 + assign $0\main_sdram_choose_req_grant[1:0] 2'10 + attribute \src "build/ls180/gateware/ls180.v:7567.10-7567.14" + case + attribute \src "build/ls180/gateware/ls180.v:7568.7-7570.10" + switch \main_sdram_choose_req_request [3] + attribute \src "build/ls180/gateware/ls180.v:7568.11-7568.43" + case 1'1 + assign $0\main_sdram_choose_req_grant[1:0] 2'11 + case + end + end + end + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case 2'01 + attribute \src "build/ls180/gateware/ls180.v:7575.5-7585.8" + switch \main_sdram_choose_req_request [2] + attribute \src "build/ls180/gateware/ls180.v:7575.9-7575.41" + case 1'1 + assign $0\main_sdram_choose_req_grant[1:0] 2'10 + attribute \src "build/ls180/gateware/ls180.v:7577.9-7577.13" + case + attribute \src "build/ls180/gateware/ls180.v:7578.6-7584.9" + switch \main_sdram_choose_req_request [3] + attribute \src "build/ls180/gateware/ls180.v:7578.10-7578.42" + case 1'1 + assign $0\main_sdram_choose_req_grant[1:0] 2'11 + attribute \src "build/ls180/gateware/ls180.v:7580.10-7580.14" + case + attribute \src "build/ls180/gateware/ls180.v:7581.7-7583.10" + switch \main_sdram_choose_req_request [0] + attribute \src "build/ls180/gateware/ls180.v:7581.11-7581.43" + case 1'1 + assign $0\main_sdram_choose_req_grant[1:0] 2'00 + case + end + end + end + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case 2'10 + attribute \src "build/ls180/gateware/ls180.v:7588.5-7598.8" + switch \main_sdram_choose_req_request [3] + attribute \src "build/ls180/gateware/ls180.v:7588.9-7588.41" + case 1'1 + assign $0\main_sdram_choose_req_grant[1:0] 2'11 + attribute \src "build/ls180/gateware/ls180.v:7590.9-7590.13" + case + attribute \src "build/ls180/gateware/ls180.v:7591.6-7597.9" + switch \main_sdram_choose_req_request [0] + attribute \src "build/ls180/gateware/ls180.v:7591.10-7591.42" + case 1'1 + assign $0\main_sdram_choose_req_grant[1:0] 2'00 + attribute \src "build/ls180/gateware/ls180.v:7593.10-7593.14" + case + attribute \src "build/ls180/gateware/ls180.v:7594.7-7596.10" + switch \main_sdram_choose_req_request [1] + attribute \src "build/ls180/gateware/ls180.v:7594.11-7594.43" + case 1'1 + assign $0\main_sdram_choose_req_grant[1:0] 2'01 + case + end + end + end + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case 2'11 + attribute \src "build/ls180/gateware/ls180.v:7601.5-7611.8" + switch \main_sdram_choose_req_request [0] + attribute \src "build/ls180/gateware/ls180.v:7601.9-7601.41" + case 1'1 + assign $0\main_sdram_choose_req_grant[1:0] 2'00 + attribute \src "build/ls180/gateware/ls180.v:7603.9-7603.13" + case + attribute \src "build/ls180/gateware/ls180.v:7604.6-7610.9" + switch \main_sdram_choose_req_request [1] + attribute \src "build/ls180/gateware/ls180.v:7604.10-7604.42" + case 1'1 + assign $0\main_sdram_choose_req_grant[1:0] 2'01 + attribute \src "build/ls180/gateware/ls180.v:7606.10-7606.14" + case + attribute \src "build/ls180/gateware/ls180.v:7607.7-7609.10" + switch \main_sdram_choose_req_request [2] + attribute \src "build/ls180/gateware/ls180.v:7607.11-7607.43" + case 1'1 + assign $0\main_sdram_choose_req_grant[1:0] 2'10 + case + end + end + end + case + end + case + end + attribute \src "build/ls180/gateware/ls180.v:7623.2-7637.5" + switch \main_sdram_tccdcon_valid + attribute \src "build/ls180/gateware/ls180.v:7623.6-7623.30" + case 1'1 + assign $0\main_sdram_tccdcon_count[0:0] 1'0 + attribute \src "build/ls180/gateware/ls180.v:7625.3-7629.6" + switch 1'1 + attribute \src "build/ls180/gateware/ls180.v:7625.7-7625.11" + case 1'1 + assign $0\main_sdram_tccdcon_ready[0:0] 1'1 + case + end + attribute \src "build/ls180/gateware/ls180.v:7630.6-7630.10" + case + attribute \src "build/ls180/gateware/ls180.v:7631.3-7636.6" + switch $not$build/ls180/gateware/ls180.v:7631$2328_Y + attribute \src "build/ls180/gateware/ls180.v:7631.7-7631.34" + case 1'1 + assign $0\main_sdram_tccdcon_count[0:0] $sub$build/ls180/gateware/ls180.v:7632$2329_Y + attribute \src "build/ls180/gateware/ls180.v:7633.4-7635.7" + switch $eq$build/ls180/gateware/ls180.v:7633$2330_Y + attribute \src "build/ls180/gateware/ls180.v:7633.8-7633.42" + case 1'1 + assign $0\main_sdram_tccdcon_ready[0:0] 1'1 + case + end + case + end + end + attribute \src "build/ls180/gateware/ls180.v:7638.2-7652.5" + switch \main_sdram_twtrcon_valid + attribute \src "build/ls180/gateware/ls180.v:7638.6-7638.30" + case 1'1 + assign $0\main_sdram_twtrcon_count[2:0] 3'100 + attribute \src "build/ls180/gateware/ls180.v:7640.3-7644.6" + switch 1'0 + attribute \src "build/ls180/gateware/ls180.v:7642.7-7642.11" + case + assign $0\main_sdram_twtrcon_ready[0:0] 1'0 + end + attribute \src "build/ls180/gateware/ls180.v:7645.6-7645.10" + case + attribute \src "build/ls180/gateware/ls180.v:7646.3-7651.6" + switch $not$build/ls180/gateware/ls180.v:7646$2331_Y + attribute \src "build/ls180/gateware/ls180.v:7646.7-7646.34" + case 1'1 + assign $0\main_sdram_twtrcon_count[2:0] $sub$build/ls180/gateware/ls180.v:7647$2332_Y + attribute \src "build/ls180/gateware/ls180.v:7648.4-7650.7" + switch $eq$build/ls180/gateware/ls180.v:7648$2333_Y + attribute \src "build/ls180/gateware/ls180.v:7648.8-7648.42" + case 1'1 + assign $0\main_sdram_twtrcon_ready[0:0] 1'1 + case + end + case + end + end + attribute \src "build/ls180/gateware/ls180.v:7659.2-7661.5" + switch $or$build/ls180/gateware/ls180.v:7659$2358_Y + attribute \src "build/ls180/gateware/ls180.v:7659.6-7659.50" + case 1'1 + assign $0\main_converter_dat_r[31:0] \main_wb_sdram_dat_r + case + end + attribute \src "build/ls180/gateware/ls180.v:7663.2-7665.5" + switch \main_converter_counter_converter_next_value_ce + attribute \src "build/ls180/gateware/ls180.v:7663.6-7663.52" + case 1'1 + assign $0\main_converter_counter[0:0] \main_converter_counter_converter_next_value + case + end + attribute \src "build/ls180/gateware/ls180.v:7666.2-7669.5" + switch \main_converter_reset + attribute \src "build/ls180/gateware/ls180.v:7666.6-7666.26" + case 1'1 + assign $0\main_converter_counter[0:0] 1'0 + assign $0\builder_converter_state[0:0] 1'0 + case + end + attribute \src "build/ls180/gateware/ls180.v:7670.2-7680.5" + switch \main_litedram_wb_ack + attribute \src "build/ls180/gateware/ls180.v:7670.6-7670.26" + case 1'1 + assign $0\main_cmd_consumed[0:0] 1'0 + assign $0\main_wdata_consumed[0:0] 1'0 + attribute \src "build/ls180/gateware/ls180.v:7673.6-7673.10" + case + attribute \src "build/ls180/gateware/ls180.v:7674.3-7676.6" + switch $and$build/ls180/gateware/ls180.v:7674$2359_Y + attribute \src "build/ls180/gateware/ls180.v:7674.7-7674.50" + case 1'1 + assign $0\main_cmd_consumed[0:0] 1'1 + case + end + attribute \src "build/ls180/gateware/ls180.v:7677.3-7679.6" + switch $and$build/ls180/gateware/ls180.v:7677$2360_Y + attribute \src "build/ls180/gateware/ls180.v:7677.7-7677.54" + case 1'1 + assign $0\main_wdata_consumed[0:0] 1'1 + case + end + end + attribute \src "build/ls180/gateware/ls180.v:7682.2-7689.5" + switch \main_clk_rise + attribute \src "build/ls180/gateware/ls180.v:7682.6-7682.19" + case 1'1 + assign $0\spi_master_clk[0:0] \main_clk_enable + attribute \src "build/ls180/gateware/ls180.v:7684.6-7684.10" + case + attribute \src "build/ls180/gateware/ls180.v:7685.3-7688.6" + switch \main_clk_fall + attribute \src "build/ls180/gateware/ls180.v:7685.7-7685.20" + case 1'1 + assign $0\main_clk_divider1[15:0] 16'0000000000000000 + assign $0\spi_master_clk[0:0] 1'0 + case + end + end + attribute \src "build/ls180/gateware/ls180.v:7691.2-7701.5" + switch \main_mosi_latch + attribute \src "build/ls180/gateware/ls180.v:7691.6-7691.21" + case 1'1 + assign $0\main_mosi_data[7:0] \main_mosi + assign $0\main_mosi_sel[2:0] 3'111 + attribute \src "build/ls180/gateware/ls180.v:7694.6-7694.10" + case + attribute \src "build/ls180/gateware/ls180.v:7695.3-7700.6" + switch \main_clk_fall + attribute \src "build/ls180/gateware/ls180.v:7695.7-7695.20" + case 1'1 + assign $0\main_mosi_sel[2:0] $sub$build/ls180/gateware/ls180.v:7699$2365_Y + attribute \src "build/ls180/gateware/ls180.v:7696.4-7698.7" + switch \main_cs_enable + attribute \src "build/ls180/gateware/ls180.v:7696.8-7696.22" + case 1'1 + assign $0\spi_master_mosi[0:0] \builder_sync_f_array_muxed0 + case + end + case + end + end + attribute \src "build/ls180/gateware/ls180.v:7702.2-7708.5" + switch \main_clk_rise + attribute \src "build/ls180/gateware/ls180.v:7702.6-7702.19" + case 1'1 + attribute \src "build/ls180/gateware/ls180.v:7703.3-7707.6" + switch \main_loopback + attribute \src "build/ls180/gateware/ls180.v:7703.7-7703.20" + case 1'1 + assign $0\main_miso_data[7:0] { \main_miso_data [6:0] \spi_master_mosi } + attribute \src "build/ls180/gateware/ls180.v:7705.7-7705.11" + case + assign $0\main_miso_data[7:0] { \main_miso_data [6:0] \spi_master_miso } + end + case + end + attribute \src "build/ls180/gateware/ls180.v:7709.2-7711.5" + switch \main_miso_latch + attribute \src "build/ls180/gateware/ls180.v:7709.6-7709.21" + case 1'1 + assign $0\main_miso[7:0] \main_miso_data + case + end + attribute \src "build/ls180/gateware/ls180.v:7713.2-7715.5" + switch \main_count_spimaster0_next_value_ce + attribute \src "build/ls180/gateware/ls180.v:7713.6-7713.41" + case 1'1 + assign $0\main_count[2:0] \main_count_spimaster0_next_value + case + end + attribute \src "build/ls180/gateware/ls180.v:7716.2-7718.5" + switch $not$build/ls180/gateware/ls180.v:7716$2366_Y + attribute \src "build/ls180/gateware/ls180.v:7716.6-7716.33" + case 1'1 + assign $0\libresocsim_clocker_clks[8:0] $add$build/ls180/gateware/ls180.v:7717$2367_Y + case + end + attribute \src "build/ls180/gateware/ls180.v:7722.2-7724.5" + switch \libresocsim_init_count_sdphy_sdphyinit_next_value_ce + attribute \src "build/ls180/gateware/ls180.v:7722.6-7722.58" + case 1'1 + assign $0\libresocsim_init_count[7:0] \libresocsim_init_count_sdphy_sdphyinit_next_value + case + end + attribute \src "build/ls180/gateware/ls180.v:7726.2-7728.5" + switch \libresocsim_cmdw_count_sdphy_sdphycmdw_next_value_ce + attribute \src "build/ls180/gateware/ls180.v:7726.6-7726.58" + case 1'1 + assign $0\libresocsim_cmdw_count[7:0] \libresocsim_cmdw_count_sdphy_sdphycmdw_next_value + case + end + attribute \src "build/ls180/gateware/ls180.v:7729.2-7731.5" + switch \libresocsim_cmdr_cmdr_pads_in_valid + attribute \src "build/ls180/gateware/ls180.v:7729.6-7729.41" + case 1'1 + assign $0\libresocsim_cmdr_cmdr_run[0:0] $or$build/ls180/gateware/ls180.v:7730$2368_Y + case + end + attribute \src "build/ls180/gateware/ls180.v:7732.2-7734.5" + switch \libresocsim_cmdr_cmdr_converter_source_ready + attribute \src "build/ls180/gateware/ls180.v:7732.6-7732.50" + case 1'1 + assign $0\libresocsim_cmdr_cmdr_converter_strobe_all[0:0] 1'0 + case + end + attribute \src "build/ls180/gateware/ls180.v:7735.2-7742.5" + switch \libresocsim_cmdr_cmdr_converter_load_part + attribute \src "build/ls180/gateware/ls180.v:7735.6-7735.47" + case 1'1 + attribute \src "build/ls180/gateware/ls180.v:7736.3-7741.6" + switch $or$build/ls180/gateware/ls180.v:7736$2370_Y + attribute \src "build/ls180/gateware/ls180.v:7736.7-7736.100" + case 1'1 + assign $0\libresocsim_cmdr_cmdr_converter_demux[2:0] 3'000 + assign $0\libresocsim_cmdr_cmdr_converter_strobe_all[0:0] 1'1 + attribute \src "build/ls180/gateware/ls180.v:7739.7-7739.11" + case + assign $0\libresocsim_cmdr_cmdr_converter_demux[2:0] $add$build/ls180/gateware/ls180.v:7740$2371_Y + end + case + end + attribute \src "build/ls180/gateware/ls180.v:7743.2-7756.5" + switch $and$build/ls180/gateware/ls180.v:7743$2372_Y + attribute \src "build/ls180/gateware/ls180.v:7743.6-7743.99" + case 1'1 + attribute \src "build/ls180/gateware/ls180.v:7744.3-7750.6" + switch $and$build/ls180/gateware/ls180.v:7744$2373_Y + attribute \src "build/ls180/gateware/ls180.v:7744.7-7744.96" + case 1'1 + assign $0\libresocsim_cmdr_cmdr_converter_source_first[0:0] \libresocsim_cmdr_cmdr_converter_sink_first + assign $0\libresocsim_cmdr_cmdr_converter_source_last[0:0] \libresocsim_cmdr_cmdr_converter_sink_last + attribute \src "build/ls180/gateware/ls180.v:7747.7-7747.11" + case + assign $0\libresocsim_cmdr_cmdr_converter_source_first[0:0] 1'0 + assign $0\libresocsim_cmdr_cmdr_converter_source_last[0:0] 1'0 + end + attribute \src "build/ls180/gateware/ls180.v:7751.6-7751.10" + case + attribute \src "build/ls180/gateware/ls180.v:7752.3-7755.6" + switch $and$build/ls180/gateware/ls180.v:7752$2374_Y + attribute \src "build/ls180/gateware/ls180.v:7752.7-7752.96" + case 1'1 + assign $0\libresocsim_cmdr_cmdr_converter_source_first[0:0] $or$build/ls180/gateware/ls180.v:7753$2375_Y + assign $0\libresocsim_cmdr_cmdr_converter_source_last[0:0] $or$build/ls180/gateware/ls180.v:7754$2376_Y + case + end + end + attribute \src "build/ls180/gateware/ls180.v:7757.2-7784.5" + switch \libresocsim_cmdr_cmdr_converter_load_part + attribute \src "build/ls180/gateware/ls180.v:7757.6-7757.47" + case 1'1 + attribute \src "build/ls180/gateware/ls180.v:7758.3-7783.10" + switch \libresocsim_cmdr_cmdr_converter_demux + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case 3'000 + assign $0\libresocsim_cmdr_cmdr_converter_source_payload_data[7:0] [7] \libresocsim_cmdr_cmdr_converter_sink_payload_data + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case 3'001 + assign $0\libresocsim_cmdr_cmdr_converter_source_payload_data[7:0] [6] \libresocsim_cmdr_cmdr_converter_sink_payload_data + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case 3'010 + assign $0\libresocsim_cmdr_cmdr_converter_source_payload_data[7:0] [5] \libresocsim_cmdr_cmdr_converter_sink_payload_data + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case 3'011 + assign $0\libresocsim_cmdr_cmdr_converter_source_payload_data[7:0] [4] \libresocsim_cmdr_cmdr_converter_sink_payload_data + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case 3'100 + assign $0\libresocsim_cmdr_cmdr_converter_source_payload_data[7:0] [3] \libresocsim_cmdr_cmdr_converter_sink_payload_data + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case 3'101 + assign $0\libresocsim_cmdr_cmdr_converter_source_payload_data[7:0] [2] \libresocsim_cmdr_cmdr_converter_sink_payload_data + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case 3'110 + assign $0\libresocsim_cmdr_cmdr_converter_source_payload_data[7:0] [1] \libresocsim_cmdr_cmdr_converter_sink_payload_data + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case 3'111 + assign $0\libresocsim_cmdr_cmdr_converter_source_payload_data[7:0] [0] \libresocsim_cmdr_cmdr_converter_sink_payload_data + case + end + case + end + attribute \src "build/ls180/gateware/ls180.v:7785.2-7787.5" + switch \libresocsim_cmdr_cmdr_converter_load_part + attribute \src "build/ls180/gateware/ls180.v:7785.6-7785.47" + case 1'1 + assign $0\libresocsim_cmdr_cmdr_converter_source_payload_valid_token_count[3:0] $add$build/ls180/gateware/ls180.v:7786$2377_Y + case + end + attribute \src "build/ls180/gateware/ls180.v:7788.2-7793.5" + switch $or$build/ls180/gateware/ls180.v:7788$2379_Y + attribute \src "build/ls180/gateware/ls180.v:7788.6-7788.90" + case 1'1 + assign $0\libresocsim_cmdr_cmdr_buf_source_valid[0:0] \libresocsim_cmdr_cmdr_buf_sink_valid + assign $0\libresocsim_cmdr_cmdr_buf_source_first[0:0] \libresocsim_cmdr_cmdr_buf_sink_first + assign $0\libresocsim_cmdr_cmdr_buf_source_last[0:0] \libresocsim_cmdr_cmdr_buf_sink_last + assign $0\libresocsim_cmdr_cmdr_buf_source_payload_data[7:0] \libresocsim_cmdr_cmdr_buf_sink_payload_data + case + end + attribute \src "build/ls180/gateware/ls180.v:7794.2-7799.5" + switch \libresocsim_cmdr_cmdr_reset + attribute \src "build/ls180/gateware/ls180.v:7794.6-7794.33" + case 1'1 + assign $0\libresocsim_cmdr_cmdr_run[0:0] 1'0 + assign $0\libresocsim_cmdr_cmdr_converter_demux[2:0] 3'000 + assign $0\libresocsim_cmdr_cmdr_converter_strobe_all[0:0] 1'0 + assign $0\libresocsim_cmdr_cmdr_buf_source_valid[0:0] 1'0 + case + end + attribute \src "build/ls180/gateware/ls180.v:7801.2-7803.5" + switch \libresocsim_cmdr_count_sdphy_sdphycmdr_next_value_ce0 + attribute \src "build/ls180/gateware/ls180.v:7801.6-7801.59" + case 1'1 + assign $0\libresocsim_cmdr_count[7:0] \libresocsim_cmdr_count_sdphy_sdphycmdr_next_value0 + case + end + attribute \src "build/ls180/gateware/ls180.v:7804.2-7806.5" + switch \libresocsim_cmdr_timeout_sdphy_sdphycmdr_next_value_ce1 + attribute \src "build/ls180/gateware/ls180.v:7804.6-7804.61" + case 1'1 + assign $0\libresocsim_cmdr_timeout[31:0] \libresocsim_cmdr_timeout_sdphy_sdphycmdr_next_value1 + case + end + attribute \src "build/ls180/gateware/ls180.v:7807.2-7809.5" + switch \libresocsim_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value_ce2 + attribute \src "build/ls180/gateware/ls180.v:7807.6-7807.64" + case 1'1 + assign $0\libresocsim_cmdr_cmdr_reset[0:0] \libresocsim_cmdr_cmdr_reset_sdphy_sdphycmdr_next_value2 + case + end + attribute \src "build/ls180/gateware/ls180.v:7810.2-7812.5" + switch \libresocsim_dataw_crcr_pads_in_valid + attribute \src "build/ls180/gateware/ls180.v:7810.6-7810.42" + case 1'1 + assign $0\libresocsim_dataw_crcr_run[0:0] $or$build/ls180/gateware/ls180.v:7811$2380_Y + case + end + attribute \src "build/ls180/gateware/ls180.v:7813.2-7815.5" + switch \libresocsim_dataw_crcr_converter_source_ready + attribute \src "build/ls180/gateware/ls180.v:7813.6-7813.51" + case 1'1 + assign $0\libresocsim_dataw_crcr_converter_strobe_all[0:0] 1'0 + case + end + attribute \src "build/ls180/gateware/ls180.v:7816.2-7823.5" + switch \libresocsim_dataw_crcr_converter_load_part + attribute \src "build/ls180/gateware/ls180.v:7816.6-7816.48" + case 1'1 + attribute \src "build/ls180/gateware/ls180.v:7817.3-7822.6" + switch $or$build/ls180/gateware/ls180.v:7817$2382_Y + attribute \src "build/ls180/gateware/ls180.v:7817.7-7817.102" + case 1'1 + assign $0\libresocsim_dataw_crcr_converter_demux[2:0] 3'000 + assign $0\libresocsim_dataw_crcr_converter_strobe_all[0:0] 1'1 + attribute \src "build/ls180/gateware/ls180.v:7820.7-7820.11" + case + assign $0\libresocsim_dataw_crcr_converter_demux[2:0] $add$build/ls180/gateware/ls180.v:7821$2383_Y + end + case + end + attribute \src "build/ls180/gateware/ls180.v:7824.2-7837.5" + switch $and$build/ls180/gateware/ls180.v:7824$2384_Y + attribute \src "build/ls180/gateware/ls180.v:7824.6-7824.101" + case 1'1 + attribute \src "build/ls180/gateware/ls180.v:7825.3-7831.6" + switch $and$build/ls180/gateware/ls180.v:7825$2385_Y + attribute \src "build/ls180/gateware/ls180.v:7825.7-7825.98" + case 1'1 + assign $0\libresocsim_dataw_crcr_converter_source_first[0:0] \libresocsim_dataw_crcr_converter_sink_first + assign $0\libresocsim_dataw_crcr_converter_source_last[0:0] \libresocsim_dataw_crcr_converter_sink_last + attribute \src "build/ls180/gateware/ls180.v:7828.7-7828.11" + case + assign $0\libresocsim_dataw_crcr_converter_source_first[0:0] 1'0 + assign $0\libresocsim_dataw_crcr_converter_source_last[0:0] 1'0 + end + attribute \src "build/ls180/gateware/ls180.v:7832.6-7832.10" + case + attribute \src "build/ls180/gateware/ls180.v:7833.3-7836.6" + switch $and$build/ls180/gateware/ls180.v:7833$2386_Y + attribute \src "build/ls180/gateware/ls180.v:7833.7-7833.98" + case 1'1 + assign $0\libresocsim_dataw_crcr_converter_source_first[0:0] $or$build/ls180/gateware/ls180.v:7834$2387_Y + assign $0\libresocsim_dataw_crcr_converter_source_last[0:0] $or$build/ls180/gateware/ls180.v:7835$2388_Y + case + end + end + attribute \src "build/ls180/gateware/ls180.v:7838.2-7865.5" + switch \libresocsim_dataw_crcr_converter_load_part + attribute \src "build/ls180/gateware/ls180.v:7838.6-7838.48" + case 1'1 + attribute \src "build/ls180/gateware/ls180.v:7839.3-7864.10" + switch \libresocsim_dataw_crcr_converter_demux + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case 3'000 + assign $0\libresocsim_dataw_crcr_converter_source_payload_data[7:0] [7] \libresocsim_dataw_crcr_converter_sink_payload_data + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case 3'001 + assign $0\libresocsim_dataw_crcr_converter_source_payload_data[7:0] [6] \libresocsim_dataw_crcr_converter_sink_payload_data + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case 3'010 + assign $0\libresocsim_dataw_crcr_converter_source_payload_data[7:0] [5] \libresocsim_dataw_crcr_converter_sink_payload_data + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case 3'011 + assign $0\libresocsim_dataw_crcr_converter_source_payload_data[7:0] [4] \libresocsim_dataw_crcr_converter_sink_payload_data + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case 3'100 + assign $0\libresocsim_dataw_crcr_converter_source_payload_data[7:0] [3] \libresocsim_dataw_crcr_converter_sink_payload_data + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case 3'101 + assign $0\libresocsim_dataw_crcr_converter_source_payload_data[7:0] [2] \libresocsim_dataw_crcr_converter_sink_payload_data + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case 3'110 + assign $0\libresocsim_dataw_crcr_converter_source_payload_data[7:0] [1] \libresocsim_dataw_crcr_converter_sink_payload_data + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case 3'111 + assign $0\libresocsim_dataw_crcr_converter_source_payload_data[7:0] [0] \libresocsim_dataw_crcr_converter_sink_payload_data + case + end + case + end + attribute \src "build/ls180/gateware/ls180.v:7866.2-7868.5" + switch \libresocsim_dataw_crcr_converter_load_part + attribute \src "build/ls180/gateware/ls180.v:7866.6-7866.48" + case 1'1 + assign $0\libresocsim_dataw_crcr_converter_source_payload_valid_token_count[3:0] $add$build/ls180/gateware/ls180.v:7867$2389_Y + case + end + attribute \src "build/ls180/gateware/ls180.v:7869.2-7874.5" + switch $or$build/ls180/gateware/ls180.v:7869$2391_Y + attribute \src "build/ls180/gateware/ls180.v:7869.6-7869.92" + case 1'1 + assign $0\libresocsim_dataw_crcr_buf_source_valid[0:0] \libresocsim_dataw_crcr_buf_sink_valid + assign $0\libresocsim_dataw_crcr_buf_source_first[0:0] \libresocsim_dataw_crcr_buf_sink_first + assign $0\libresocsim_dataw_crcr_buf_source_last[0:0] \libresocsim_dataw_crcr_buf_sink_last + assign $0\libresocsim_dataw_crcr_buf_source_payload_data[7:0] \libresocsim_dataw_crcr_buf_sink_payload_data + case + end + attribute \src "build/ls180/gateware/ls180.v:7875.2-7880.5" + switch \libresocsim_dataw_crcr_reset + attribute \src "build/ls180/gateware/ls180.v:7875.6-7875.34" + case 1'1 + assign $0\libresocsim_dataw_crcr_run[0:0] 1'0 + assign $0\libresocsim_dataw_crcr_converter_demux[2:0] 3'000 + assign $0\libresocsim_dataw_crcr_converter_strobe_all[0:0] 1'0 + assign $0\libresocsim_dataw_crcr_buf_source_valid[0:0] 1'0 + case + end + attribute \src "build/ls180/gateware/ls180.v:7882.2-7884.5" + switch \libresocsim_dataw_crcr_reset_sdphy_sdphycrcr_next_value_ce + attribute \src "build/ls180/gateware/ls180.v:7882.6-7882.64" + case 1'1 + assign $0\libresocsim_dataw_crcr_reset[0:0] \libresocsim_dataw_crcr_reset_sdphy_sdphycrcr_next_value + case + end + attribute \src "build/ls180/gateware/ls180.v:7886.2-7888.5" + switch \libresocsim_dataw_count_sdphy_fsm_next_value_ce + attribute \src "build/ls180/gateware/ls180.v:7886.6-7886.53" + case 1'1 + assign $0\libresocsim_dataw_count[7:0] \libresocsim_dataw_count_sdphy_fsm_next_value + case + end + attribute \src "build/ls180/gateware/ls180.v:7889.2-7891.5" + switch \libresocsim_datar_datar_pads_in_valid + attribute \src "build/ls180/gateware/ls180.v:7889.6-7889.43" + case 1'1 + assign $0\libresocsim_datar_datar_run[0:0] $or$build/ls180/gateware/ls180.v:7890$2392_Y + case + end + attribute \src "build/ls180/gateware/ls180.v:7892.2-7894.5" + switch \libresocsim_datar_datar_converter_source_ready + attribute \src "build/ls180/gateware/ls180.v:7892.6-7892.52" + case 1'1 + assign $0\libresocsim_datar_datar_converter_strobe_all[0:0] 1'0 + case + end + attribute \src "build/ls180/gateware/ls180.v:7895.2-7902.5" + switch \libresocsim_datar_datar_converter_load_part + attribute \src "build/ls180/gateware/ls180.v:7895.6-7895.49" + case 1'1 + attribute \src "build/ls180/gateware/ls180.v:7896.3-7901.6" + switch $or$build/ls180/gateware/ls180.v:7896$2394_Y + attribute \src "build/ls180/gateware/ls180.v:7896.7-7896.104" + case 1'1 + assign $0\libresocsim_datar_datar_converter_demux[0:0] 1'0 + assign $0\libresocsim_datar_datar_converter_strobe_all[0:0] 1'1 + attribute \src "build/ls180/gateware/ls180.v:7899.7-7899.11" + case + assign $0\libresocsim_datar_datar_converter_demux[0:0] $add$build/ls180/gateware/ls180.v:7900$2395_Y + end + case + end + attribute \src "build/ls180/gateware/ls180.v:7903.2-7916.5" + switch $and$build/ls180/gateware/ls180.v:7903$2396_Y + attribute \src "build/ls180/gateware/ls180.v:7903.6-7903.103" + case 1'1 + attribute \src "build/ls180/gateware/ls180.v:7904.3-7910.6" + switch $and$build/ls180/gateware/ls180.v:7904$2397_Y + attribute \src "build/ls180/gateware/ls180.v:7904.7-7904.100" + case 1'1 + assign $0\libresocsim_datar_datar_converter_source_first[0:0] \libresocsim_datar_datar_converter_sink_first + assign $0\libresocsim_datar_datar_converter_source_last[0:0] \libresocsim_datar_datar_converter_sink_last + attribute \src "build/ls180/gateware/ls180.v:7907.7-7907.11" + case + assign $0\libresocsim_datar_datar_converter_source_first[0:0] 1'0 + assign $0\libresocsim_datar_datar_converter_source_last[0:0] 1'0 + end + attribute \src "build/ls180/gateware/ls180.v:7911.6-7911.10" + case + attribute \src "build/ls180/gateware/ls180.v:7912.3-7915.6" + switch $and$build/ls180/gateware/ls180.v:7912$2398_Y + attribute \src "build/ls180/gateware/ls180.v:7912.7-7912.100" + case 1'1 + assign $0\libresocsim_datar_datar_converter_source_first[0:0] $or$build/ls180/gateware/ls180.v:7913$2399_Y + assign $0\libresocsim_datar_datar_converter_source_last[0:0] $or$build/ls180/gateware/ls180.v:7914$2400_Y + case + end + end + attribute \src "build/ls180/gateware/ls180.v:7917.2-7926.5" + switch \libresocsim_datar_datar_converter_load_part + attribute \src "build/ls180/gateware/ls180.v:7917.6-7917.49" + case 1'1 + attribute \src "build/ls180/gateware/ls180.v:7918.3-7925.10" + switch \libresocsim_datar_datar_converter_demux + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case 1'0 + assign $0\libresocsim_datar_datar_converter_source_payload_data[7:0] [7:4] \libresocsim_datar_datar_converter_sink_payload_data + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case 1'1 + assign $0\libresocsim_datar_datar_converter_source_payload_data[7:0] [3:0] \libresocsim_datar_datar_converter_sink_payload_data + case + end + case + end + attribute \src "build/ls180/gateware/ls180.v:7927.2-7929.5" + switch \libresocsim_datar_datar_converter_load_part + attribute \src "build/ls180/gateware/ls180.v:7927.6-7927.49" + case 1'1 + assign $0\libresocsim_datar_datar_converter_source_payload_valid_token_count[1:0] $add$build/ls180/gateware/ls180.v:7928$2401_Y + case + end + attribute \src "build/ls180/gateware/ls180.v:7930.2-7935.5" + switch $or$build/ls180/gateware/ls180.v:7930$2403_Y + attribute \src "build/ls180/gateware/ls180.v:7930.6-7930.94" + case 1'1 + assign $0\libresocsim_datar_datar_buf_source_valid[0:0] \libresocsim_datar_datar_buf_sink_valid + assign $0\libresocsim_datar_datar_buf_source_first[0:0] \libresocsim_datar_datar_buf_sink_first + assign $0\libresocsim_datar_datar_buf_source_last[0:0] \libresocsim_datar_datar_buf_sink_last + assign $0\libresocsim_datar_datar_buf_source_payload_data[7:0] \libresocsim_datar_datar_buf_sink_payload_data + case + end + attribute \src "build/ls180/gateware/ls180.v:7936.2-7941.5" + switch \libresocsim_datar_datar_reset + attribute \src "build/ls180/gateware/ls180.v:7936.6-7936.35" + case 1'1 + assign $0\libresocsim_datar_datar_run[0:0] 1'0 + assign $0\libresocsim_datar_datar_converter_demux[0:0] 1'0 + assign $0\libresocsim_datar_datar_converter_strobe_all[0:0] 1'0 + assign $0\libresocsim_datar_datar_buf_source_valid[0:0] 1'0 + case + end + attribute \src "build/ls180/gateware/ls180.v:7943.2-7945.5" + switch \libresocsim_datar_count_sdphy_sdphydatar_next_value_ce0 + attribute \src "build/ls180/gateware/ls180.v:7943.6-7943.61" + case 1'1 + assign $0\libresocsim_datar_count[9:0] \libresocsim_datar_count_sdphy_sdphydatar_next_value0 + case + end + attribute \src "build/ls180/gateware/ls180.v:7946.2-7948.5" + switch \libresocsim_datar_timeout_sdphy_sdphydatar_next_value_ce1 + attribute \src "build/ls180/gateware/ls180.v:7946.6-7946.63" + case 1'1 + assign $0\libresocsim_datar_timeout[31:0] \libresocsim_datar_timeout_sdphy_sdphydatar_next_value1 + case + end + attribute \src "build/ls180/gateware/ls180.v:7949.2-7951.5" + switch \libresocsim_datar_datar_reset_sdphy_sdphydatar_next_value_ce2 + attribute \src "build/ls180/gateware/ls180.v:7949.6-7949.67" + case 1'1 + assign $0\libresocsim_datar_datar_reset[0:0] \libresocsim_datar_datar_reset_sdphy_sdphydatar_next_value2 + case + end + attribute \src "build/ls180/gateware/ls180.v:7952.2-7958.5" + switch \libresocsim_sdcore_crc7_inserter_clr + attribute \src "build/ls180/gateware/ls180.v:7952.6-7952.42" + case 1'1 + assign $0\libresocsim_sdcore_crc7_inserter_crcreg0[6:0] 7'0000000 + attribute \src "build/ls180/gateware/ls180.v:7954.6-7954.10" + case + attribute \src "build/ls180/gateware/ls180.v:7955.3-7957.6" + switch \libresocsim_sdcore_crc7_inserter_enable + attribute \src "build/ls180/gateware/ls180.v:7955.7-7955.46" + case 1'1 + assign $0\libresocsim_sdcore_crc7_inserter_crcreg0[6:0] \libresocsim_sdcore_crc7_inserter_crcreg40 + case + end + end + attribute \src "build/ls180/gateware/ls180.v:7959.2-7965.5" + switch \libresocsim_sdcore_crc16_inserter_crc0_clr + attribute \src "build/ls180/gateware/ls180.v:7959.6-7959.48" + case 1'1 + assign $0\libresocsim_sdcore_crc16_inserter_crc0_crcreg0[15:0] 16'0000000000000000 + attribute \src "build/ls180/gateware/ls180.v:7961.6-7961.10" + case + attribute \src "build/ls180/gateware/ls180.v:7962.3-7964.6" + switch \libresocsim_sdcore_crc16_inserter_crc0_enable + attribute \src "build/ls180/gateware/ls180.v:7962.7-7962.52" + case 1'1 + assign $0\libresocsim_sdcore_crc16_inserter_crc0_crcreg0[15:0] \libresocsim_sdcore_crc16_inserter_crc0_crcreg2 + case + end + end + attribute \src "build/ls180/gateware/ls180.v:7966.2-7972.5" + switch \libresocsim_sdcore_crc16_inserter_crc1_clr + attribute \src "build/ls180/gateware/ls180.v:7966.6-7966.48" + case 1'1 + assign $0\libresocsim_sdcore_crc16_inserter_crc1_crcreg0[15:0] 16'0000000000000000 + attribute \src "build/ls180/gateware/ls180.v:7968.6-7968.10" + case + attribute \src "build/ls180/gateware/ls180.v:7969.3-7971.6" + switch \libresocsim_sdcore_crc16_inserter_crc1_enable + attribute \src "build/ls180/gateware/ls180.v:7969.7-7969.52" + case 1'1 + assign $0\libresocsim_sdcore_crc16_inserter_crc1_crcreg0[15:0] \libresocsim_sdcore_crc16_inserter_crc1_crcreg2 + case + end + end + attribute \src "build/ls180/gateware/ls180.v:7973.2-7979.5" + switch \libresocsim_sdcore_crc16_inserter_crc2_clr + attribute \src "build/ls180/gateware/ls180.v:7973.6-7973.48" + case 1'1 + assign $0\libresocsim_sdcore_crc16_inserter_crc2_crcreg0[15:0] 16'0000000000000000 + attribute \src "build/ls180/gateware/ls180.v:7975.6-7975.10" + case + attribute \src "build/ls180/gateware/ls180.v:7976.3-7978.6" + switch \libresocsim_sdcore_crc16_inserter_crc2_enable + attribute \src "build/ls180/gateware/ls180.v:7976.7-7976.52" + case 1'1 + assign $0\libresocsim_sdcore_crc16_inserter_crc2_crcreg0[15:0] \libresocsim_sdcore_crc16_inserter_crc2_crcreg2 + case + end + end + attribute \src "build/ls180/gateware/ls180.v:7980.2-7986.5" + switch \libresocsim_sdcore_crc16_inserter_crc3_clr + attribute \src "build/ls180/gateware/ls180.v:7980.6-7980.48" + case 1'1 + assign $0\libresocsim_sdcore_crc16_inserter_crc3_crcreg0[15:0] 16'0000000000000000 + attribute \src "build/ls180/gateware/ls180.v:7982.6-7982.10" + case + attribute \src "build/ls180/gateware/ls180.v:7983.3-7985.6" + switch \libresocsim_sdcore_crc16_inserter_crc3_enable + attribute \src "build/ls180/gateware/ls180.v:7983.7-7983.52" + case 1'1 + assign $0\libresocsim_sdcore_crc16_inserter_crc3_crcreg0[15:0] \libresocsim_sdcore_crc16_inserter_crc3_crcreg2 + case + end + end + attribute \src "build/ls180/gateware/ls180.v:7988.2-7990.5" + switch \libresocsim_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value_ce0 + attribute \src "build/ls180/gateware/ls180.v:7988.6-7988.89" + case 1'1 + assign $0\libresocsim_sdcore_crc16_inserter_crctmp0[15:0] \libresocsim_sdcore_crc16_inserter_crctmp0_sdcore_crcupstreaminserter_next_value0 + case + end + attribute \src "build/ls180/gateware/ls180.v:7991.2-7993.5" + switch \libresocsim_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value_ce1 + attribute \src "build/ls180/gateware/ls180.v:7991.6-7991.89" + case 1'1 + assign $0\libresocsim_sdcore_crc16_inserter_crctmp1[15:0] \libresocsim_sdcore_crc16_inserter_crctmp1_sdcore_crcupstreaminserter_next_value1 + case + end + attribute \src "build/ls180/gateware/ls180.v:7994.2-7996.5" + switch \libresocsim_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value_ce2 + attribute \src "build/ls180/gateware/ls180.v:7994.6-7994.89" + case 1'1 + assign $0\libresocsim_sdcore_crc16_inserter_crctmp2[15:0] \libresocsim_sdcore_crc16_inserter_crctmp2_sdcore_crcupstreaminserter_next_value2 + case + end + attribute \src "build/ls180/gateware/ls180.v:7997.2-7999.5" + switch \libresocsim_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value_ce3 + attribute \src "build/ls180/gateware/ls180.v:7997.6-7997.89" + case 1'1 + assign $0\libresocsim_sdcore_crc16_inserter_crctmp3[15:0] \libresocsim_sdcore_crc16_inserter_crctmp3_sdcore_crcupstreaminserter_next_value3 + case + end + attribute \src "build/ls180/gateware/ls180.v:8000.2-8002.5" + switch \libresocsim_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value_ce4 + attribute \src "build/ls180/gateware/ls180.v:8000.6-8000.85" + case 1'1 + assign $0\libresocsim_sdcore_crc16_inserter_cnt[2:0] \libresocsim_sdcore_crc16_inserter_cnt_sdcore_crcupstreaminserter_next_value4 + case + end + attribute \src "build/ls180/gateware/ls180.v:8003.2-8005.5" + switch $and$build/ls180/gateware/ls180.v:8003$2404_Y + attribute \src "build/ls180/gateware/ls180.v:8003.6-8003.97" + case 1'1 + assign $0\libresocsim_sdcore_crc16_checker_crctmp0[15:0] \libresocsim_sdcore_crc16_checker_crc0_crc + case + end + attribute \src "build/ls180/gateware/ls180.v:8006.2-8008.5" + switch $and$build/ls180/gateware/ls180.v:8006$2405_Y + attribute \src "build/ls180/gateware/ls180.v:8006.6-8006.97" + case 1'1 + assign $0\libresocsim_sdcore_crc16_checker_crctmp1[15:0] \libresocsim_sdcore_crc16_checker_crc1_crc + case + end + attribute \src "build/ls180/gateware/ls180.v:8009.2-8011.5" + switch $and$build/ls180/gateware/ls180.v:8009$2406_Y + attribute \src "build/ls180/gateware/ls180.v:8009.6-8009.97" + case 1'1 + assign $0\libresocsim_sdcore_crc16_checker_crctmp2[15:0] \libresocsim_sdcore_crc16_checker_crc2_crc + case + end + attribute \src "build/ls180/gateware/ls180.v:8012.2-8014.5" + switch $and$build/ls180/gateware/ls180.v:8012$2407_Y + attribute \src "build/ls180/gateware/ls180.v:8012.6-8012.97" + case 1'1 + assign $0\libresocsim_sdcore_crc16_checker_crctmp3[15:0] \libresocsim_sdcore_crc16_checker_crc3_crc + case + end + attribute \src "build/ls180/gateware/ls180.v:8015.2-8019.5" + switch $and$build/ls180/gateware/ls180.v:8015$2408_Y + attribute \src "build/ls180/gateware/ls180.v:8015.6-8015.97" + case 1'1 + assign $0\libresocsim_sdcore_crc16_checker_fifo0[15:0] { \libresocsim_sdcore_crc16_checker_fifo0 [13:0] \libresocsim_sdcore_crc16_checker_sink_payload_data [7] \libresocsim_sdcore_crc16_checker_sink_payload_data [3] } + assign $0\libresocsim_sdcore_crc16_checker_val[7:0] [7] \libresocsim_sdcore_crc16_checker_fifo0 [13] + assign $0\libresocsim_sdcore_crc16_checker_val[7:0] [3] \libresocsim_sdcore_crc16_checker_fifo0 [12] + case + end + attribute \src "build/ls180/gateware/ls180.v:8020.2-8024.5" + switch $and$build/ls180/gateware/ls180.v:8020$2409_Y + attribute \src "build/ls180/gateware/ls180.v:8020.6-8020.97" + case 1'1 + assign $0\libresocsim_sdcore_crc16_checker_fifo1[15:0] { \libresocsim_sdcore_crc16_checker_fifo1 [13:0] \libresocsim_sdcore_crc16_checker_sink_payload_data [6] \libresocsim_sdcore_crc16_checker_sink_payload_data [2] } + assign $0\libresocsim_sdcore_crc16_checker_val[7:0] [6] \libresocsim_sdcore_crc16_checker_fifo1 [13] + assign $0\libresocsim_sdcore_crc16_checker_val[7:0] [2] \libresocsim_sdcore_crc16_checker_fifo1 [12] + case + end + attribute \src "build/ls180/gateware/ls180.v:8025.2-8029.5" + switch $and$build/ls180/gateware/ls180.v:8025$2410_Y + attribute \src "build/ls180/gateware/ls180.v:8025.6-8025.97" + case 1'1 + assign $0\libresocsim_sdcore_crc16_checker_fifo2[15:0] { \libresocsim_sdcore_crc16_checker_fifo2 [13:0] \libresocsim_sdcore_crc16_checker_sink_payload_data [5] \libresocsim_sdcore_crc16_checker_sink_payload_data [1] } + assign $0\libresocsim_sdcore_crc16_checker_val[7:0] [5] \libresocsim_sdcore_crc16_checker_fifo2 [13] + assign $0\libresocsim_sdcore_crc16_checker_val[7:0] [1] \libresocsim_sdcore_crc16_checker_fifo2 [12] + case + end + attribute \src "build/ls180/gateware/ls180.v:8030.2-8034.5" + switch $and$build/ls180/gateware/ls180.v:8030$2411_Y + attribute \src "build/ls180/gateware/ls180.v:8030.6-8030.97" + case 1'1 + assign $0\libresocsim_sdcore_crc16_checker_fifo3[15:0] { \libresocsim_sdcore_crc16_checker_fifo3 [13:0] \libresocsim_sdcore_crc16_checker_sink_payload_data [4] \libresocsim_sdcore_crc16_checker_sink_payload_data [0] } + assign $0\libresocsim_sdcore_crc16_checker_val[7:0] [4] \libresocsim_sdcore_crc16_checker_fifo3 [13] + assign $0\libresocsim_sdcore_crc16_checker_val[7:0] [0] \libresocsim_sdcore_crc16_checker_fifo3 [12] + case + end + attribute \src "build/ls180/gateware/ls180.v:8035.2-8043.5" + switch $and$build/ls180/gateware/ls180.v:8035$2412_Y + attribute \src "build/ls180/gateware/ls180.v:8035.6-8035.97" + case 1'1 + attribute \src "build/ls180/gateware/ls180.v:8036.3-8042.6" + switch \libresocsim_sdcore_crc16_checker_sink_last + attribute \src "build/ls180/gateware/ls180.v:8036.7-8036.49" + case 1'1 + assign $0\libresocsim_sdcore_crc16_checker_cnt[3:0] 4'0000 + attribute \src "build/ls180/gateware/ls180.v:8038.7-8038.11" + case + attribute \src "build/ls180/gateware/ls180.v:8039.4-8041.7" + switch $ne$build/ls180/gateware/ls180.v:8039$2413_Y + attribute \src "build/ls180/gateware/ls180.v:8039.8-8039.55" + case 1'1 + assign $0\libresocsim_sdcore_crc16_checker_cnt[3:0] $add$build/ls180/gateware/ls180.v:8040$2414_Y + case + end + end + case + end + attribute \src "build/ls180/gateware/ls180.v:8044.2-8050.5" + switch \libresocsim_sdcore_crc16_checker_crc0_clr + attribute \src "build/ls180/gateware/ls180.v:8044.6-8044.47" + case 1'1 + assign $0\libresocsim_sdcore_crc16_checker_crc0_crcreg0[15:0] 16'0000000000000000 + attribute \src "build/ls180/gateware/ls180.v:8046.6-8046.10" + case + attribute \src "build/ls180/gateware/ls180.v:8047.3-8049.6" + switch \libresocsim_sdcore_crc16_checker_crc0_enable + attribute \src "build/ls180/gateware/ls180.v:8047.7-8047.51" + case 1'1 + assign $0\libresocsim_sdcore_crc16_checker_crc0_crcreg0[15:0] \libresocsim_sdcore_crc16_checker_crc0_crcreg2 + case + end + end + attribute \src "build/ls180/gateware/ls180.v:8051.2-8057.5" + switch \libresocsim_sdcore_crc16_checker_crc1_clr + attribute \src "build/ls180/gateware/ls180.v:8051.6-8051.47" + case 1'1 + assign $0\libresocsim_sdcore_crc16_checker_crc1_crcreg0[15:0] 16'0000000000000000 + attribute \src "build/ls180/gateware/ls180.v:8053.6-8053.10" + case + attribute \src "build/ls180/gateware/ls180.v:8054.3-8056.6" + switch \libresocsim_sdcore_crc16_checker_crc1_enable + attribute \src "build/ls180/gateware/ls180.v:8054.7-8054.51" + case 1'1 + assign $0\libresocsim_sdcore_crc16_checker_crc1_crcreg0[15:0] \libresocsim_sdcore_crc16_checker_crc1_crcreg2 + case + end + end + attribute \src "build/ls180/gateware/ls180.v:8058.2-8064.5" + switch \libresocsim_sdcore_crc16_checker_crc2_clr + attribute \src "build/ls180/gateware/ls180.v:8058.6-8058.47" + case 1'1 + assign $0\libresocsim_sdcore_crc16_checker_crc2_crcreg0[15:0] 16'0000000000000000 + attribute \src "build/ls180/gateware/ls180.v:8060.6-8060.10" + case + attribute \src "build/ls180/gateware/ls180.v:8061.3-8063.6" + switch \libresocsim_sdcore_crc16_checker_crc2_enable + attribute \src "build/ls180/gateware/ls180.v:8061.7-8061.51" + case 1'1 + assign $0\libresocsim_sdcore_crc16_checker_crc2_crcreg0[15:0] \libresocsim_sdcore_crc16_checker_crc2_crcreg2 + case + end + end + attribute \src "build/ls180/gateware/ls180.v:8065.2-8071.5" + switch \libresocsim_sdcore_crc16_checker_crc3_clr + attribute \src "build/ls180/gateware/ls180.v:8065.6-8065.47" + case 1'1 + assign $0\libresocsim_sdcore_crc16_checker_crc3_crcreg0[15:0] 16'0000000000000000 + attribute \src "build/ls180/gateware/ls180.v:8067.6-8067.10" + case + attribute \src "build/ls180/gateware/ls180.v:8068.3-8070.6" + switch \libresocsim_sdcore_crc16_checker_crc3_enable + attribute \src "build/ls180/gateware/ls180.v:8068.7-8068.51" + case 1'1 + assign $0\libresocsim_sdcore_crc16_checker_crc3_crcreg0[15:0] \libresocsim_sdcore_crc16_checker_crc3_crcreg2 + case + end + end + attribute \src "build/ls180/gateware/ls180.v:8073.2-8075.5" + switch \libresocsim_sdcore_cmd_done_sdcore_fsm_next_value_ce0 + attribute \src "build/ls180/gateware/ls180.v:8073.6-8073.59" + case 1'1 + assign $0\libresocsim_sdcore_cmd_done[0:0] \libresocsim_sdcore_cmd_done_sdcore_fsm_next_value0 + case + end + attribute \src "build/ls180/gateware/ls180.v:8076.2-8078.5" + switch \libresocsim_sdcore_data_done_sdcore_fsm_next_value_ce1 + attribute \src "build/ls180/gateware/ls180.v:8076.6-8076.60" + case 1'1 + assign $0\libresocsim_sdcore_data_done[0:0] \libresocsim_sdcore_data_done_sdcore_fsm_next_value1 + case + end + attribute \src "build/ls180/gateware/ls180.v:8079.2-8081.5" + switch \libresocsim_sdcore_cmd_count_sdcore_fsm_next_value_ce2 + attribute \src "build/ls180/gateware/ls180.v:8079.6-8079.60" + case 1'1 + assign $0\libresocsim_sdcore_cmd_count[2:0] \libresocsim_sdcore_cmd_count_sdcore_fsm_next_value2 + case + end + attribute \src "build/ls180/gateware/ls180.v:8082.2-8084.5" + switch \libresocsim_sdcore_data_count_sdcore_fsm_next_value_ce3 + attribute \src "build/ls180/gateware/ls180.v:8082.6-8082.61" + case 1'1 + assign $0\libresocsim_sdcore_data_count[31:0] \libresocsim_sdcore_data_count_sdcore_fsm_next_value3 + case + end + attribute \src "build/ls180/gateware/ls180.v:8085.2-8087.5" + switch \libresocsim_sdcore_cmd_error_sdcore_fsm_next_value_ce4 + attribute \src "build/ls180/gateware/ls180.v:8085.6-8085.60" + case 1'1 + assign $0\libresocsim_sdcore_cmd_error[0:0] \libresocsim_sdcore_cmd_error_sdcore_fsm_next_value4 + case + end + attribute \src "build/ls180/gateware/ls180.v:8088.2-8090.5" + switch \libresocsim_sdcore_cmd_timeout_sdcore_fsm_next_value_ce5 + attribute \src "build/ls180/gateware/ls180.v:8088.6-8088.62" + case 1'1 + assign $0\libresocsim_sdcore_cmd_timeout[0:0] \libresocsim_sdcore_cmd_timeout_sdcore_fsm_next_value5 + case + end + attribute \src "build/ls180/gateware/ls180.v:8091.2-8093.5" + switch \libresocsim_sdcore_data_error_sdcore_fsm_next_value_ce6 + attribute \src "build/ls180/gateware/ls180.v:8091.6-8091.61" + case 1'1 + assign $0\libresocsim_sdcore_data_error[0:0] \libresocsim_sdcore_data_error_sdcore_fsm_next_value6 + case + end + attribute \src "build/ls180/gateware/ls180.v:8094.2-8096.5" + switch \libresocsim_sdcore_data_timeout_sdcore_fsm_next_value_ce7 + attribute \src "build/ls180/gateware/ls180.v:8094.6-8094.63" + case 1'1 + assign $0\libresocsim_sdcore_data_timeout[0:0] \libresocsim_sdcore_data_timeout_sdcore_fsm_next_value7 + case + end + attribute \src "build/ls180/gateware/ls180.v:8097.2-8099.5" + switch \libresocsim_sdcore_cmd_response_status_sdcore_fsm_next_value_ce8 + attribute \src "build/ls180/gateware/ls180.v:8097.6-8097.70" + case 1'1 + assign $0\libresocsim_sdcore_cmd_response_status[127:0] \libresocsim_sdcore_cmd_response_status_sdcore_fsm_next_value8 + case + end + attribute \src "build/ls180/gateware/ls180.v:8100.2-8102.5" + switch $and$build/ls180/gateware/ls180.v:8100$2417_Y + attribute \src "build/ls180/gateware/ls180.v:8100.6-8100.141" + case 1'1 + assign $0\libresocsim_sdblock2mem_fifo_produce[4:0] $add$build/ls180/gateware/ls180.v:8101$2418_Y + case + end + attribute \src "build/ls180/gateware/ls180.v:8103.2-8105.5" + switch \libresocsim_sdblock2mem_fifo_do_read + attribute \src "build/ls180/gateware/ls180.v:8103.6-8103.42" + case 1'1 + assign $0\libresocsim_sdblock2mem_fifo_consume[4:0] $add$build/ls180/gateware/ls180.v:8104$2419_Y + case + end + attribute \src "build/ls180/gateware/ls180.v:8106.2-8114.5" + switch $and$build/ls180/gateware/ls180.v:8106$2422_Y + attribute \src "build/ls180/gateware/ls180.v:8106.6-8106.141" + case 1'1 + attribute \src "build/ls180/gateware/ls180.v:8107.3-8109.6" + switch $not$build/ls180/gateware/ls180.v:8107$2423_Y + attribute \src "build/ls180/gateware/ls180.v:8107.7-8107.46" + case 1'1 + assign $0\libresocsim_sdblock2mem_fifo_level[5:0] $add$build/ls180/gateware/ls180.v:8108$2424_Y + case + end + attribute \src "build/ls180/gateware/ls180.v:8110.6-8110.10" + case + attribute \src "build/ls180/gateware/ls180.v:8111.3-8113.6" + switch \libresocsim_sdblock2mem_fifo_do_read + attribute \src "build/ls180/gateware/ls180.v:8111.7-8111.43" + case 1'1 + assign $0\libresocsim_sdblock2mem_fifo_level[5:0] $sub$build/ls180/gateware/ls180.v:8112$2425_Y + case + end + end + attribute \src "build/ls180/gateware/ls180.v:8115.2-8117.5" + switch \libresocsim_sdblock2mem_converter_source_ready + attribute \src "build/ls180/gateware/ls180.v:8115.6-8115.52" + case 1'1 + assign $0\libresocsim_sdblock2mem_converter_strobe_all[0:0] 1'0 + case + end + attribute \src "build/ls180/gateware/ls180.v:8118.2-8125.5" + switch \libresocsim_sdblock2mem_converter_load_part + attribute \src "build/ls180/gateware/ls180.v:8118.6-8118.49" + case 1'1 + attribute \src "build/ls180/gateware/ls180.v:8119.3-8124.6" + switch $or$build/ls180/gateware/ls180.v:8119$2427_Y + attribute \src "build/ls180/gateware/ls180.v:8119.7-8119.104" + case 1'1 + assign $0\libresocsim_sdblock2mem_converter_demux[1:0] 2'00 + assign $0\libresocsim_sdblock2mem_converter_strobe_all[0:0] 1'1 + attribute \src "build/ls180/gateware/ls180.v:8122.7-8122.11" + case + assign $0\libresocsim_sdblock2mem_converter_demux[1:0] $add$build/ls180/gateware/ls180.v:8123$2428_Y + end + case + end + attribute \src "build/ls180/gateware/ls180.v:8126.2-8139.5" + switch $and$build/ls180/gateware/ls180.v:8126$2429_Y + attribute \src "build/ls180/gateware/ls180.v:8126.6-8126.103" + case 1'1 + attribute \src "build/ls180/gateware/ls180.v:8127.3-8133.6" + switch $and$build/ls180/gateware/ls180.v:8127$2430_Y + attribute \src "build/ls180/gateware/ls180.v:8127.7-8127.100" + case 1'1 + assign $0\libresocsim_sdblock2mem_converter_source_first[0:0] \libresocsim_sdblock2mem_converter_sink_first + assign $0\libresocsim_sdblock2mem_converter_source_last[0:0] \libresocsim_sdblock2mem_converter_sink_last + attribute \src "build/ls180/gateware/ls180.v:8130.7-8130.11" + case + assign $0\libresocsim_sdblock2mem_converter_source_first[0:0] 1'0 + assign $0\libresocsim_sdblock2mem_converter_source_last[0:0] 1'0 + end + attribute \src "build/ls180/gateware/ls180.v:8134.6-8134.10" + case + attribute \src "build/ls180/gateware/ls180.v:8135.3-8138.6" + switch $and$build/ls180/gateware/ls180.v:8135$2431_Y + attribute \src "build/ls180/gateware/ls180.v:8135.7-8135.100" + case 1'1 + assign $0\libresocsim_sdblock2mem_converter_source_first[0:0] $or$build/ls180/gateware/ls180.v:8136$2432_Y + assign $0\libresocsim_sdblock2mem_converter_source_last[0:0] $or$build/ls180/gateware/ls180.v:8137$2433_Y + case + end + end + attribute \src "build/ls180/gateware/ls180.v:8140.2-8155.5" + switch \libresocsim_sdblock2mem_converter_load_part + attribute \src "build/ls180/gateware/ls180.v:8140.6-8140.49" + case 1'1 + attribute \src "build/ls180/gateware/ls180.v:8141.3-8154.10" + switch \libresocsim_sdblock2mem_converter_demux + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case 2'00 + assign $0\libresocsim_sdblock2mem_converter_source_payload_data[31:0] [31:24] \libresocsim_sdblock2mem_converter_sink_payload_data + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case 2'01 + assign $0\libresocsim_sdblock2mem_converter_source_payload_data[31:0] [23:16] \libresocsim_sdblock2mem_converter_sink_payload_data + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case 2'10 + assign $0\libresocsim_sdblock2mem_converter_source_payload_data[31:0] [15:8] \libresocsim_sdblock2mem_converter_sink_payload_data + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case 2'11 + assign $0\libresocsim_sdblock2mem_converter_source_payload_data[31:0] [7:0] \libresocsim_sdblock2mem_converter_sink_payload_data + case + end + case + end + attribute \src "build/ls180/gateware/ls180.v:8156.2-8158.5" + switch \libresocsim_sdblock2mem_converter_load_part + attribute \src "build/ls180/gateware/ls180.v:8156.6-8156.49" + case 1'1 + assign $0\libresocsim_sdblock2mem_converter_source_payload_valid_token_count[2:0] $add$build/ls180/gateware/ls180.v:8157$2434_Y + case + end + attribute \src "build/ls180/gateware/ls180.v:8160.2-8162.5" + switch \libresocsim_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value_ce + attribute \src "build/ls180/gateware/ls180.v:8160.6-8160.83" + case 1'1 + assign $0\libresocsim_sdblock2mem_wishbonedmawriter_offset[31:0] \libresocsim_sdblock2mem_wishbonedmawriter_offset_sdblock2memdma_next_value + case + end + attribute \src "build/ls180/gateware/ls180.v:8163.2-8166.5" + switch \libresocsim_sdblock2mem_wishbonedmawriter_reset + attribute \src "build/ls180/gateware/ls180.v:8163.6-8163.53" + case 1'1 + assign $0\libresocsim_sdblock2mem_wishbonedmawriter_offset[31:0] 0 + assign $0\builder_sdblock2memdma_state[1:0] 2'00 + case + end + attribute \src "build/ls180/gateware/ls180.v:8168.2-8170.5" + switch \libresocsim_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value_ce + attribute \src "build/ls180/gateware/ls180.v:8168.6-8168.71" + case 1'1 + assign $0\libresocsim_sdmem2block_dma_data[31:0] \libresocsim_sdmem2block_dma_data_sdmem2blockdma_fsm_next_value + case + end + attribute \src "build/ls180/gateware/ls180.v:8172.2-8174.5" + switch \libresocsim_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value_ce + attribute \src "build/ls180/gateware/ls180.v:8172.6-8172.83" + case 1'1 + assign $0\libresocsim_sdmem2block_dma_offset[31:0] \libresocsim_sdmem2block_dma_offset_sdmem2blockdma_resetinserter_next_value + case + end + attribute \src "build/ls180/gateware/ls180.v:8175.2-8178.5" + switch \libresocsim_sdmem2block_dma_reset + attribute \src "build/ls180/gateware/ls180.v:8175.6-8175.39" + case 1'1 + assign $0\libresocsim_sdmem2block_dma_offset[31:0] 0 + assign $0\builder_sdmem2blockdma_resetinserter_state[1:0] 2'00 + case + end + attribute \src "build/ls180/gateware/ls180.v:8179.2-8185.5" + switch $and$build/ls180/gateware/ls180.v:8179$2435_Y + attribute \src "build/ls180/gateware/ls180.v:8179.6-8179.103" + case 1'1 + attribute \src "build/ls180/gateware/ls180.v:8180.3-8184.6" + switch \libresocsim_sdmem2block_converter_last + attribute \src "build/ls180/gateware/ls180.v:8180.7-8180.45" + case 1'1 + assign $0\libresocsim_sdmem2block_converter_mux[1:0] 2'00 + attribute \src "build/ls180/gateware/ls180.v:8182.7-8182.11" + case + assign $0\libresocsim_sdmem2block_converter_mux[1:0] $add$build/ls180/gateware/ls180.v:8183$2436_Y + end + case + end + attribute \src "build/ls180/gateware/ls180.v:8186.2-8188.5" + switch $and$build/ls180/gateware/ls180.v:8186$2439_Y + attribute \src "build/ls180/gateware/ls180.v:8186.6-8186.141" + case 1'1 + assign $0\libresocsim_sdmem2block_fifo_produce[4:0] $add$build/ls180/gateware/ls180.v:8187$2440_Y + case + end + attribute \src "build/ls180/gateware/ls180.v:8189.2-8191.5" + switch \libresocsim_sdmem2block_fifo_do_read + attribute \src "build/ls180/gateware/ls180.v:8189.6-8189.42" + case 1'1 + assign $0\libresocsim_sdmem2block_fifo_consume[4:0] $add$build/ls180/gateware/ls180.v:8190$2441_Y + case + end + attribute \src "build/ls180/gateware/ls180.v:8192.2-8200.5" + switch $and$build/ls180/gateware/ls180.v:8192$2444_Y + attribute \src "build/ls180/gateware/ls180.v:8192.6-8192.141" + case 1'1 + attribute \src "build/ls180/gateware/ls180.v:8193.3-8195.6" + switch $not$build/ls180/gateware/ls180.v:8193$2445_Y + attribute \src "build/ls180/gateware/ls180.v:8193.7-8193.46" + case 1'1 + assign $0\libresocsim_sdmem2block_fifo_level[5:0] $add$build/ls180/gateware/ls180.v:8194$2446_Y + case + end + attribute \src "build/ls180/gateware/ls180.v:8196.6-8196.10" + case + attribute \src "build/ls180/gateware/ls180.v:8197.3-8199.6" + switch \libresocsim_sdmem2block_fifo_do_read + attribute \src "build/ls180/gateware/ls180.v:8197.7-8197.43" + case 1'1 + assign $0\libresocsim_sdmem2block_fifo_level[5:0] $sub$build/ls180/gateware/ls180.v:8198$2447_Y + case + end + end + attribute \src "build/ls180/gateware/ls180.v:8202.2-8209.5" + switch \libresocsim_clk_rise + attribute \src "build/ls180/gateware/ls180.v:8202.6-8202.26" + case 1'1 + assign $0\spisdcard_clk[0:0] \libresocsim_clk_enable + attribute \src "build/ls180/gateware/ls180.v:8204.6-8204.10" + case + attribute \src "build/ls180/gateware/ls180.v:8205.3-8208.6" + switch \libresocsim_clk_fall + attribute \src "build/ls180/gateware/ls180.v:8205.7-8205.27" + case 1'1 + assign $0\libresocsim_clk_divider1[15:0] 16'0000000000000000 + assign $0\spisdcard_clk[0:0] 1'0 + case + end + end + attribute \src "build/ls180/gateware/ls180.v:8211.2-8221.5" + switch \libresocsim_mosi_latch + attribute \src "build/ls180/gateware/ls180.v:8211.6-8211.28" + case 1'1 + assign $0\libresocsim_mosi_data[7:0] \libresocsim_mosi + assign $0\libresocsim_mosi_sel[2:0] 3'111 + attribute \src "build/ls180/gateware/ls180.v:8214.6-8214.10" + case + attribute \src "build/ls180/gateware/ls180.v:8215.3-8220.6" + switch \libresocsim_clk_fall + attribute \src "build/ls180/gateware/ls180.v:8215.7-8215.27" + case 1'1 + assign $0\libresocsim_mosi_sel[2:0] $sub$build/ls180/gateware/ls180.v:8219$2452_Y + attribute \src "build/ls180/gateware/ls180.v:8216.4-8218.7" + switch \libresocsim_cs_enable + attribute \src "build/ls180/gateware/ls180.v:8216.8-8216.29" + case 1'1 + assign $0\spisdcard_mosi[0:0] \builder_sync_f_array_muxed1 + case + end + case + end + end + attribute \src "build/ls180/gateware/ls180.v:8222.2-8228.5" + switch \libresocsim_clk_rise + attribute \src "build/ls180/gateware/ls180.v:8222.6-8222.26" + case 1'1 + attribute \src "build/ls180/gateware/ls180.v:8223.3-8227.6" + switch \libresocsim_loopback + attribute \src "build/ls180/gateware/ls180.v:8223.7-8223.27" + case 1'1 + assign $0\libresocsim_miso_data[7:0] { \libresocsim_miso_data [6:0] \spisdcard_mosi } + attribute \src "build/ls180/gateware/ls180.v:8225.7-8225.11" + case + assign $0\libresocsim_miso_data[7:0] { \libresocsim_miso_data [6:0] \spisdcard_miso } + end + case + end + attribute \src "build/ls180/gateware/ls180.v:8229.2-8231.5" + switch \libresocsim_miso_latch + attribute \src "build/ls180/gateware/ls180.v:8229.6-8229.28" + case 1'1 + assign $0\libresocsim_miso[7:0] \libresocsim_miso_data + case + end + attribute \src "build/ls180/gateware/ls180.v:8233.2-8235.5" + switch \libresocsim_count_spimaster1_next_value_ce + attribute \src "build/ls180/gateware/ls180.v:8233.6-8233.48" + case 1'1 + assign $0\libresocsim_count[2:0] \libresocsim_count_spimaster1_next_value + case + end + attribute \src "build/ls180/gateware/ls180.v:8237.2-8239.5" + switch \builder_libresocsim_dat_w_next_value_ce0 + attribute \src "build/ls180/gateware/ls180.v:8237.6-8237.46" + case 1'1 + assign $0\builder_libresocsim_dat_w[7:0] \builder_libresocsim_dat_w_next_value0 + case + end + attribute \src "build/ls180/gateware/ls180.v:8240.2-8242.5" + switch \builder_libresocsim_adr_next_value_ce1 + attribute \src "build/ls180/gateware/ls180.v:8240.6-8240.44" + case 1'1 + assign $0\builder_libresocsim_adr[13:0] \builder_libresocsim_adr_next_value1 + case + end + attribute \src "build/ls180/gateware/ls180.v:8243.2-8245.5" + switch \builder_libresocsim_we_next_value_ce2 + attribute \src "build/ls180/gateware/ls180.v:8243.6-8243.43" + case 1'1 + assign $0\builder_libresocsim_we[0:0] \builder_libresocsim_we_next_value2 + case + end + attribute \src "build/ls180/gateware/ls180.v:8246.2-8307.9" + switch \builder_grant + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case 2'00 + attribute \src "build/ls180/gateware/ls180.v:8248.4-8260.7" + switch $not$build/ls180/gateware/ls180.v:8248$2453_Y + attribute \src "build/ls180/gateware/ls180.v:8248.8-8248.29" + case 1'1 + attribute \src "build/ls180/gateware/ls180.v:8249.5-8259.8" + switch \builder_request [1] + attribute \src "build/ls180/gateware/ls180.v:8249.9-8249.27" + case 1'1 + assign $0\builder_grant[1:0] 2'01 + attribute \src "build/ls180/gateware/ls180.v:8251.9-8251.13" + case + attribute \src "build/ls180/gateware/ls180.v:8252.6-8258.9" + switch \builder_request [2] + attribute \src "build/ls180/gateware/ls180.v:8252.10-8252.28" + case 1'1 + assign $0\builder_grant[1:0] 2'10 + attribute \src "build/ls180/gateware/ls180.v:8254.10-8254.14" + case + attribute \src "build/ls180/gateware/ls180.v:8255.7-8257.10" + switch \builder_request [3] + attribute \src "build/ls180/gateware/ls180.v:8255.11-8255.29" + case 1'1 + assign $0\builder_grant[1:0] 2'11 + case + end + end + end + case + end + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case 2'01 + attribute \src "build/ls180/gateware/ls180.v:8263.4-8275.7" + switch $not$build/ls180/gateware/ls180.v:8263$2454_Y + attribute \src "build/ls180/gateware/ls180.v:8263.8-8263.29" + case 1'1 + attribute \src "build/ls180/gateware/ls180.v:8264.5-8274.8" + switch \builder_request [2] + attribute \src "build/ls180/gateware/ls180.v:8264.9-8264.27" + case 1'1 + assign $0\builder_grant[1:0] 2'10 + attribute \src "build/ls180/gateware/ls180.v:8266.9-8266.13" + case + attribute \src "build/ls180/gateware/ls180.v:8267.6-8273.9" + switch \builder_request [3] + attribute \src "build/ls180/gateware/ls180.v:8267.10-8267.28" + case 1'1 + assign $0\builder_grant[1:0] 2'11 + attribute \src "build/ls180/gateware/ls180.v:8269.10-8269.14" + case + attribute \src "build/ls180/gateware/ls180.v:8270.7-8272.10" + switch \builder_request [0] + attribute \src "build/ls180/gateware/ls180.v:8270.11-8270.29" + case 1'1 + assign $0\builder_grant[1:0] 2'00 + case + end + end + end + case + end + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case 2'10 + attribute \src "build/ls180/gateware/ls180.v:8278.4-8290.7" + switch $not$build/ls180/gateware/ls180.v:8278$2455_Y + attribute \src "build/ls180/gateware/ls180.v:8278.8-8278.29" + case 1'1 + attribute \src "build/ls180/gateware/ls180.v:8279.5-8289.8" + switch \builder_request [3] + attribute \src "build/ls180/gateware/ls180.v:8279.9-8279.27" + case 1'1 + assign $0\builder_grant[1:0] 2'11 + attribute \src "build/ls180/gateware/ls180.v:8281.9-8281.13" + case + attribute \src "build/ls180/gateware/ls180.v:8282.6-8288.9" + switch \builder_request [0] + attribute \src "build/ls180/gateware/ls180.v:8282.10-8282.28" + case 1'1 + assign $0\builder_grant[1:0] 2'00 + attribute \src "build/ls180/gateware/ls180.v:8284.10-8284.14" + case + attribute \src "build/ls180/gateware/ls180.v:8285.7-8287.10" + switch \builder_request [1] + attribute \src "build/ls180/gateware/ls180.v:8285.11-8285.29" + case 1'1 + assign $0\builder_grant[1:0] 2'01 + case + end + end + end + case + end + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case 2'11 + attribute \src "build/ls180/gateware/ls180.v:8293.4-8305.7" + switch $not$build/ls180/gateware/ls180.v:8293$2456_Y + attribute \src "build/ls180/gateware/ls180.v:8293.8-8293.29" + case 1'1 + attribute \src "build/ls180/gateware/ls180.v:8294.5-8304.8" + switch \builder_request [0] + attribute \src "build/ls180/gateware/ls180.v:8294.9-8294.27" + case 1'1 + assign $0\builder_grant[1:0] 2'00 + attribute \src "build/ls180/gateware/ls180.v:8296.9-8296.13" + case + attribute \src "build/ls180/gateware/ls180.v:8297.6-8303.9" + switch \builder_request [1] + attribute \src "build/ls180/gateware/ls180.v:8297.10-8297.28" + case 1'1 + assign $0\builder_grant[1:0] 2'01 + attribute \src "build/ls180/gateware/ls180.v:8299.10-8299.14" + case + attribute \src "build/ls180/gateware/ls180.v:8300.7-8302.10" + switch \builder_request [2] + attribute \src "build/ls180/gateware/ls180.v:8300.11-8300.29" + case 1'1 + assign $0\builder_grant[1:0] 2'10 + case + end + end + end + case + end + case + end + attribute \src "build/ls180/gateware/ls180.v:8309.2-8315.5" + switch \builder_wait + attribute \src "build/ls180/gateware/ls180.v:8309.6-8309.18" + case 1'1 + attribute \src "build/ls180/gateware/ls180.v:8310.3-8312.6" + switch $not$build/ls180/gateware/ls180.v:8310$2457_Y + attribute \src "build/ls180/gateware/ls180.v:8310.7-8310.22" + case 1'1 + assign $0\builder_count[19:0] $sub$build/ls180/gateware/ls180.v:8311$2458_Y + case + end + attribute \src "build/ls180/gateware/ls180.v:8313.6-8313.10" + case + assign $0\builder_count[19:0] 20'11110100001001000000 + end + attribute \src "build/ls180/gateware/ls180.v:8317.2-8347.5" + switch \builder_csrbank0_sel + attribute \src "build/ls180/gateware/ls180.v:8317.6-8317.26" + case 1'1 + attribute \src "build/ls180/gateware/ls180.v:8318.3-8346.10" + switch \builder_interface0_bank_bus_adr [3:0] + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case 4'0000 + assign $0\builder_interface0_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank0_reset0_w } + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case 4'0001 + assign $0\builder_interface0_bank_bus_dat_r[7:0] \builder_csrbank0_scratch3_w + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case 4'0010 + assign $0\builder_interface0_bank_bus_dat_r[7:0] \builder_csrbank0_scratch2_w + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case 4'0011 + assign $0\builder_interface0_bank_bus_dat_r[7:0] \builder_csrbank0_scratch1_w + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case 4'0100 + assign $0\builder_interface0_bank_bus_dat_r[7:0] \builder_csrbank0_scratch0_w + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case 4'0101 + assign $0\builder_interface0_bank_bus_dat_r[7:0] \builder_csrbank0_bus_errors3_w + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case 4'0110 + assign $0\builder_interface0_bank_bus_dat_r[7:0] \builder_csrbank0_bus_errors2_w + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case 4'0111 + assign $0\builder_interface0_bank_bus_dat_r[7:0] \builder_csrbank0_bus_errors1_w + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case 4'1000 + assign $0\builder_interface0_bank_bus_dat_r[7:0] \builder_csrbank0_bus_errors0_w + case + end + case + end + attribute \src "build/ls180/gateware/ls180.v:8348.2-8350.5" + switch \builder_csrbank0_reset0_re + attribute \src "build/ls180/gateware/ls180.v:8348.6-8348.32" + case 1'1 + assign $0\main_libresocsim_soccontroller_reset_storage[0:0] \builder_csrbank0_reset0_r + case + end + attribute \src "build/ls180/gateware/ls180.v:8352.2-8354.5" + switch \builder_csrbank0_scratch3_re + attribute \src "build/ls180/gateware/ls180.v:8352.6-8352.34" + case 1'1 + assign $0\main_libresocsim_soccontroller_scratch_storage[31:0] [31:24] \builder_csrbank0_scratch3_r + case + end + attribute \src "build/ls180/gateware/ls180.v:8355.2-8357.5" + switch \builder_csrbank0_scratch2_re + attribute \src "build/ls180/gateware/ls180.v:8355.6-8355.34" + case 1'1 + assign $0\main_libresocsim_soccontroller_scratch_storage[31:0] [23:16] \builder_csrbank0_scratch2_r + case + end + attribute \src "build/ls180/gateware/ls180.v:8358.2-8360.5" + switch \builder_csrbank0_scratch1_re + attribute \src "build/ls180/gateware/ls180.v:8358.6-8358.34" + case 1'1 + assign $0\main_libresocsim_soccontroller_scratch_storage[31:0] [15:8] \builder_csrbank0_scratch1_r + case + end + attribute \src "build/ls180/gateware/ls180.v:8361.2-8363.5" + switch \builder_csrbank0_scratch0_re + attribute \src "build/ls180/gateware/ls180.v:8361.6-8361.34" + case 1'1 + assign $0\main_libresocsim_soccontroller_scratch_storage[31:0] [7:0] \builder_csrbank0_scratch0_r + case + end + attribute \src "build/ls180/gateware/ls180.v:8366.2-8372.5" + switch \builder_csrbank1_sel + attribute \src "build/ls180/gateware/ls180.v:8366.6-8366.26" + case 1'1 + attribute \src "build/ls180/gateware/ls180.v:8367.3-8371.10" + switch \builder_interface1_bank_bus_adr [0] + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case 1'0 + assign $0\builder_interface1_bank_bus_dat_r[7:0] \builder_csrbank1_in_w + case + end + case + end + attribute \src "build/ls180/gateware/ls180.v:8374.2-8380.5" + switch \builder_csrbank2_sel + attribute \src "build/ls180/gateware/ls180.v:8374.6-8374.26" + case 1'1 + attribute \src "build/ls180/gateware/ls180.v:8375.3-8379.10" + switch \builder_interface2_bank_bus_adr [0] + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case 1'0 + assign $0\builder_interface2_bank_bus_dat_r[7:0] \builder_csrbank2_in_w + case + end + case + end + attribute \src "build/ls180/gateware/ls180.v:8382.2-8430.5" + switch \builder_csrbank3_sel + attribute \src "build/ls180/gateware/ls180.v:8382.6-8382.26" + case 1'1 + attribute \src "build/ls180/gateware/ls180.v:8383.3-8429.10" + switch \builder_interface3_bank_bus_adr [3:0] + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case 4'0000 + assign $0\builder_interface3_bank_bus_dat_r[7:0] \builder_csrbank3_dma_base7_w + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case 4'0001 + assign $0\builder_interface3_bank_bus_dat_r[7:0] \builder_csrbank3_dma_base6_w + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case 4'0010 + assign $0\builder_interface3_bank_bus_dat_r[7:0] \builder_csrbank3_dma_base5_w + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case 4'0011 + assign $0\builder_interface3_bank_bus_dat_r[7:0] \builder_csrbank3_dma_base4_w + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case 4'0100 + assign $0\builder_interface3_bank_bus_dat_r[7:0] \builder_csrbank3_dma_base3_w + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case 4'0101 + assign $0\builder_interface3_bank_bus_dat_r[7:0] \builder_csrbank3_dma_base2_w + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case 4'0110 + assign $0\builder_interface3_bank_bus_dat_r[7:0] \builder_csrbank3_dma_base1_w + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case 4'0111 + assign $0\builder_interface3_bank_bus_dat_r[7:0] \builder_csrbank3_dma_base0_w + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case 4'1000 + assign $0\builder_interface3_bank_bus_dat_r[7:0] \builder_csrbank3_dma_length3_w + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case 4'1001 + assign $0\builder_interface3_bank_bus_dat_r[7:0] \builder_csrbank3_dma_length2_w + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case 4'1010 + assign $0\builder_interface3_bank_bus_dat_r[7:0] \builder_csrbank3_dma_length1_w + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case 4'1011 + assign $0\builder_interface3_bank_bus_dat_r[7:0] \builder_csrbank3_dma_length0_w + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case 4'1100 + assign $0\builder_interface3_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank3_dma_enable0_w } + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case 4'1101 + assign $0\builder_interface3_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank3_dma_done_w } + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case 4'1110 + assign $0\builder_interface3_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank3_dma_loop0_w } + case + end + case + end + attribute \src "build/ls180/gateware/ls180.v:8431.2-8433.5" + switch \builder_csrbank3_dma_base7_re + attribute \src "build/ls180/gateware/ls180.v:8431.6-8431.35" + case 1'1 + assign $0\libresocsim_sdblock2mem_wishbonedmawriter_base_storage[63:0] [63:56] \builder_csrbank3_dma_base7_r + case + end + attribute \src "build/ls180/gateware/ls180.v:8434.2-8436.5" + switch \builder_csrbank3_dma_base6_re + attribute \src "build/ls180/gateware/ls180.v:8434.6-8434.35" + case 1'1 + assign $0\libresocsim_sdblock2mem_wishbonedmawriter_base_storage[63:0] [55:48] \builder_csrbank3_dma_base6_r + case + end + attribute \src "build/ls180/gateware/ls180.v:8437.2-8439.5" + switch \builder_csrbank3_dma_base5_re + attribute \src "build/ls180/gateware/ls180.v:8437.6-8437.35" + case 1'1 + assign $0\libresocsim_sdblock2mem_wishbonedmawriter_base_storage[63:0] [47:40] \builder_csrbank3_dma_base5_r + case + end + attribute \src "build/ls180/gateware/ls180.v:8440.2-8442.5" + switch \builder_csrbank3_dma_base4_re + attribute \src "build/ls180/gateware/ls180.v:8440.6-8440.35" + case 1'1 + assign $0\libresocsim_sdblock2mem_wishbonedmawriter_base_storage[63:0] [39:32] \builder_csrbank3_dma_base4_r + case + end + attribute \src "build/ls180/gateware/ls180.v:8443.2-8445.5" + switch \builder_csrbank3_dma_base3_re + attribute \src "build/ls180/gateware/ls180.v:8443.6-8443.35" + case 1'1 + assign $0\libresocsim_sdblock2mem_wishbonedmawriter_base_storage[63:0] [31:24] \builder_csrbank3_dma_base3_r + case + end + attribute \src "build/ls180/gateware/ls180.v:8446.2-8448.5" + switch \builder_csrbank3_dma_base2_re + attribute \src "build/ls180/gateware/ls180.v:8446.6-8446.35" + case 1'1 + assign $0\libresocsim_sdblock2mem_wishbonedmawriter_base_storage[63:0] [23:16] \builder_csrbank3_dma_base2_r + case + end + attribute \src "build/ls180/gateware/ls180.v:8449.2-8451.5" + switch \builder_csrbank3_dma_base1_re + attribute \src "build/ls180/gateware/ls180.v:8449.6-8449.35" + case 1'1 + assign $0\libresocsim_sdblock2mem_wishbonedmawriter_base_storage[63:0] [15:8] \builder_csrbank3_dma_base1_r + case + end + attribute \src "build/ls180/gateware/ls180.v:8452.2-8454.5" + switch \builder_csrbank3_dma_base0_re + attribute \src "build/ls180/gateware/ls180.v:8452.6-8452.35" + case 1'1 + assign $0\libresocsim_sdblock2mem_wishbonedmawriter_base_storage[63:0] [7:0] \builder_csrbank3_dma_base0_r + case + end + attribute \src "build/ls180/gateware/ls180.v:8456.2-8458.5" + switch \builder_csrbank3_dma_length3_re + attribute \src "build/ls180/gateware/ls180.v:8456.6-8456.37" + case 1'1 + assign $0\libresocsim_sdblock2mem_wishbonedmawriter_length_storage[31:0] [31:24] \builder_csrbank3_dma_length3_r + case + end + attribute \src "build/ls180/gateware/ls180.v:8459.2-8461.5" + switch \builder_csrbank3_dma_length2_re + attribute \src "build/ls180/gateware/ls180.v:8459.6-8459.37" + case 1'1 + assign $0\libresocsim_sdblock2mem_wishbonedmawriter_length_storage[31:0] [23:16] \builder_csrbank3_dma_length2_r + case + end + attribute \src "build/ls180/gateware/ls180.v:8462.2-8464.5" + switch \builder_csrbank3_dma_length1_re + attribute \src "build/ls180/gateware/ls180.v:8462.6-8462.37" + case 1'1 + assign $0\libresocsim_sdblock2mem_wishbonedmawriter_length_storage[31:0] [15:8] \builder_csrbank3_dma_length1_r + case + end + attribute \src "build/ls180/gateware/ls180.v:8465.2-8467.5" + switch \builder_csrbank3_dma_length0_re + attribute \src "build/ls180/gateware/ls180.v:8465.6-8465.37" + case 1'1 + assign $0\libresocsim_sdblock2mem_wishbonedmawriter_length_storage[31:0] [7:0] \builder_csrbank3_dma_length0_r + case + end + attribute \src "build/ls180/gateware/ls180.v:8469.2-8471.5" + switch \builder_csrbank3_dma_enable0_re + attribute \src "build/ls180/gateware/ls180.v:8469.6-8469.37" + case 1'1 + assign $0\libresocsim_sdblock2mem_wishbonedmawriter_enable_storage[0:0] \builder_csrbank3_dma_enable0_r + case + end + attribute \src "build/ls180/gateware/ls180.v:8473.2-8475.5" + switch \builder_csrbank3_dma_loop0_re + attribute \src "build/ls180/gateware/ls180.v:8473.6-8473.35" + case 1'1 + assign $0\libresocsim_sdblock2mem_wishbonedmawriter_loop_storage[0:0] \builder_csrbank3_dma_loop0_r + case + end + attribute \src "build/ls180/gateware/ls180.v:8478.2-8580.5" + switch \builder_csrbank4_sel + attribute \src "build/ls180/gateware/ls180.v:8478.6-8478.26" + case 1'1 + attribute \src "build/ls180/gateware/ls180.v:8479.3-8579.10" + switch \builder_interface4_bank_bus_adr [5:0] + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case 6'000000 + assign $0\builder_interface4_bank_bus_dat_r[7:0] \builder_csrbank4_cmd_argument3_w + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case 6'000001 + assign $0\builder_interface4_bank_bus_dat_r[7:0] \builder_csrbank4_cmd_argument2_w + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case 6'000010 + assign $0\builder_interface4_bank_bus_dat_r[7:0] \builder_csrbank4_cmd_argument1_w + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case 6'000011 + assign $0\builder_interface4_bank_bus_dat_r[7:0] \builder_csrbank4_cmd_argument0_w + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case 6'000100 + assign $0\builder_interface4_bank_bus_dat_r[7:0] \builder_csrbank4_cmd_command3_w + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case 6'000101 + assign $0\builder_interface4_bank_bus_dat_r[7:0] \builder_csrbank4_cmd_command2_w + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case 6'000110 + assign $0\builder_interface4_bank_bus_dat_r[7:0] \builder_csrbank4_cmd_command1_w + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case 6'000111 + assign $0\builder_interface4_bank_bus_dat_r[7:0] \builder_csrbank4_cmd_command0_w + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case 6'001000 + assign $0\builder_interface4_bank_bus_dat_r[7:0] { 7'0000000 \libresocsim_sdcore_cmd_send_w } + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case 6'001001 + assign $0\builder_interface4_bank_bus_dat_r[7:0] \builder_csrbank4_cmd_response15_w + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case 6'001010 + assign $0\builder_interface4_bank_bus_dat_r[7:0] \builder_csrbank4_cmd_response14_w + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case 6'001011 + assign $0\builder_interface4_bank_bus_dat_r[7:0] \builder_csrbank4_cmd_response13_w + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case 6'001100 + assign $0\builder_interface4_bank_bus_dat_r[7:0] \builder_csrbank4_cmd_response12_w + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case 6'001101 + assign $0\builder_interface4_bank_bus_dat_r[7:0] \builder_csrbank4_cmd_response11_w + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case 6'001110 + assign $0\builder_interface4_bank_bus_dat_r[7:0] \builder_csrbank4_cmd_response10_w + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case 6'001111 + assign $0\builder_interface4_bank_bus_dat_r[7:0] \builder_csrbank4_cmd_response9_w + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case 6'010000 + assign $0\builder_interface4_bank_bus_dat_r[7:0] \builder_csrbank4_cmd_response8_w + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case 6'010001 + assign $0\builder_interface4_bank_bus_dat_r[7:0] \builder_csrbank4_cmd_response7_w + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case 6'010010 + assign $0\builder_interface4_bank_bus_dat_r[7:0] \builder_csrbank4_cmd_response6_w + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case 6'010011 + assign $0\builder_interface4_bank_bus_dat_r[7:0] \builder_csrbank4_cmd_response5_w + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case 6'010100 + assign $0\builder_interface4_bank_bus_dat_r[7:0] \builder_csrbank4_cmd_response4_w + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case 6'010101 + assign $0\builder_interface4_bank_bus_dat_r[7:0] \builder_csrbank4_cmd_response3_w + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case 6'010110 + assign $0\builder_interface4_bank_bus_dat_r[7:0] \builder_csrbank4_cmd_response2_w + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case 6'010111 + assign $0\builder_interface4_bank_bus_dat_r[7:0] \builder_csrbank4_cmd_response1_w + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case 6'011000 + assign $0\builder_interface4_bank_bus_dat_r[7:0] \builder_csrbank4_cmd_response0_w + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case 6'011001 + assign $0\builder_interface4_bank_bus_dat_r[7:0] { 4'0000 \builder_csrbank4_cmd_event_w } + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case 6'011010 + assign $0\builder_interface4_bank_bus_dat_r[7:0] { 4'0000 \builder_csrbank4_data_event_w } + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case 6'011011 + assign $0\builder_interface4_bank_bus_dat_r[7:0] { 6'000000 \builder_csrbank4_block_length1_w } + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case 6'011100 + assign $0\builder_interface4_bank_bus_dat_r[7:0] \builder_csrbank4_block_length0_w + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case 6'011101 + assign $0\builder_interface4_bank_bus_dat_r[7:0] \builder_csrbank4_block_count3_w + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case 6'011110 + assign $0\builder_interface4_bank_bus_dat_r[7:0] \builder_csrbank4_block_count2_w + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case 6'011111 + assign $0\builder_interface4_bank_bus_dat_r[7:0] \builder_csrbank4_block_count1_w + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case 6'100000 + assign $0\builder_interface4_bank_bus_dat_r[7:0] \builder_csrbank4_block_count0_w + case + end + case + end + attribute \src "build/ls180/gateware/ls180.v:8581.2-8583.5" + switch \builder_csrbank4_cmd_argument3_re + attribute \src "build/ls180/gateware/ls180.v:8581.6-8581.39" + case 1'1 + assign $0\libresocsim_sdcore_cmd_argument_storage[31:0] [31:24] \builder_csrbank4_cmd_argument3_r + case + end + attribute \src "build/ls180/gateware/ls180.v:8584.2-8586.5" + switch \builder_csrbank4_cmd_argument2_re + attribute \src "build/ls180/gateware/ls180.v:8584.6-8584.39" + case 1'1 + assign $0\libresocsim_sdcore_cmd_argument_storage[31:0] [23:16] \builder_csrbank4_cmd_argument2_r + case + end + attribute \src "build/ls180/gateware/ls180.v:8587.2-8589.5" + switch \builder_csrbank4_cmd_argument1_re + attribute \src "build/ls180/gateware/ls180.v:8587.6-8587.39" + case 1'1 + assign $0\libresocsim_sdcore_cmd_argument_storage[31:0] [15:8] \builder_csrbank4_cmd_argument1_r + case + end + attribute \src "build/ls180/gateware/ls180.v:8590.2-8592.5" + switch \builder_csrbank4_cmd_argument0_re + attribute \src "build/ls180/gateware/ls180.v:8590.6-8590.39" + case 1'1 + assign $0\libresocsim_sdcore_cmd_argument_storage[31:0] [7:0] \builder_csrbank4_cmd_argument0_r + case + end + attribute \src "build/ls180/gateware/ls180.v:8594.2-8596.5" + switch \builder_csrbank4_cmd_command3_re + attribute \src "build/ls180/gateware/ls180.v:8594.6-8594.38" + case 1'1 + assign $0\libresocsim_sdcore_cmd_command_storage[31:0] [31:24] \builder_csrbank4_cmd_command3_r + case + end + attribute \src "build/ls180/gateware/ls180.v:8597.2-8599.5" + switch \builder_csrbank4_cmd_command2_re + attribute \src "build/ls180/gateware/ls180.v:8597.6-8597.38" + case 1'1 + assign $0\libresocsim_sdcore_cmd_command_storage[31:0] [23:16] \builder_csrbank4_cmd_command2_r + case + end + attribute \src "build/ls180/gateware/ls180.v:8600.2-8602.5" + switch \builder_csrbank4_cmd_command1_re + attribute \src "build/ls180/gateware/ls180.v:8600.6-8600.38" + case 1'1 + assign $0\libresocsim_sdcore_cmd_command_storage[31:0] [15:8] \builder_csrbank4_cmd_command1_r + case + end + attribute \src "build/ls180/gateware/ls180.v:8603.2-8605.5" + switch \builder_csrbank4_cmd_command0_re + attribute \src "build/ls180/gateware/ls180.v:8603.6-8603.38" + case 1'1 + assign $0\libresocsim_sdcore_cmd_command_storage[31:0] [7:0] \builder_csrbank4_cmd_command0_r + case + end + attribute \src "build/ls180/gateware/ls180.v:8607.2-8609.5" + switch \builder_csrbank4_block_length1_re + attribute \src "build/ls180/gateware/ls180.v:8607.6-8607.39" + case 1'1 + assign $0\libresocsim_sdcore_block_length_storage[9:0] [9:8] \builder_csrbank4_block_length1_r + case + end + attribute \src "build/ls180/gateware/ls180.v:8610.2-8612.5" + switch \builder_csrbank4_block_length0_re + attribute \src "build/ls180/gateware/ls180.v:8610.6-8610.39" + case 1'1 + assign $0\libresocsim_sdcore_block_length_storage[9:0] [7:0] \builder_csrbank4_block_length0_r + case + end + attribute \src "build/ls180/gateware/ls180.v:8614.2-8616.5" + switch \builder_csrbank4_block_count3_re + attribute \src "build/ls180/gateware/ls180.v:8614.6-8614.38" + case 1'1 + assign $0\libresocsim_sdcore_block_count_storage[31:0] [31:24] \builder_csrbank4_block_count3_r + case + end + attribute \src "build/ls180/gateware/ls180.v:8617.2-8619.5" + switch \builder_csrbank4_block_count2_re + attribute \src "build/ls180/gateware/ls180.v:8617.6-8617.38" + case 1'1 + assign $0\libresocsim_sdcore_block_count_storage[31:0] [23:16] \builder_csrbank4_block_count2_r + case + end + attribute \src "build/ls180/gateware/ls180.v:8620.2-8622.5" + switch \builder_csrbank4_block_count1_re + attribute \src "build/ls180/gateware/ls180.v:8620.6-8620.38" + case 1'1 + assign $0\libresocsim_sdcore_block_count_storage[31:0] [15:8] \builder_csrbank4_block_count1_r + case + end + attribute \src "build/ls180/gateware/ls180.v:8623.2-8625.5" + switch \builder_csrbank4_block_count0_re + attribute \src "build/ls180/gateware/ls180.v:8623.6-8623.38" + case 1'1 + assign $0\libresocsim_sdcore_block_count_storage[31:0] [7:0] \builder_csrbank4_block_count0_r + case + end + attribute \src "build/ls180/gateware/ls180.v:8628.2-8688.5" + switch \builder_csrbank5_sel + attribute \src "build/ls180/gateware/ls180.v:8628.6-8628.26" + case 1'1 + attribute \src "build/ls180/gateware/ls180.v:8629.3-8687.10" + switch \builder_interface5_bank_bus_adr [4:0] + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case 5'00000 + assign $0\builder_interface5_bank_bus_dat_r[7:0] \builder_csrbank5_dma_base7_w + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case 5'00001 + assign $0\builder_interface5_bank_bus_dat_r[7:0] \builder_csrbank5_dma_base6_w + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case 5'00010 + assign $0\builder_interface5_bank_bus_dat_r[7:0] \builder_csrbank5_dma_base5_w + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case 5'00011 + assign $0\builder_interface5_bank_bus_dat_r[7:0] \builder_csrbank5_dma_base4_w + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case 5'00100 + assign $0\builder_interface5_bank_bus_dat_r[7:0] \builder_csrbank5_dma_base3_w + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case 5'00101 + assign $0\builder_interface5_bank_bus_dat_r[7:0] \builder_csrbank5_dma_base2_w + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case 5'00110 + assign $0\builder_interface5_bank_bus_dat_r[7:0] \builder_csrbank5_dma_base1_w + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case 5'00111 + assign $0\builder_interface5_bank_bus_dat_r[7:0] \builder_csrbank5_dma_base0_w + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case 5'01000 + assign $0\builder_interface5_bank_bus_dat_r[7:0] \builder_csrbank5_dma_length3_w + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case 5'01001 + assign $0\builder_interface5_bank_bus_dat_r[7:0] \builder_csrbank5_dma_length2_w + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case 5'01010 + assign $0\builder_interface5_bank_bus_dat_r[7:0] \builder_csrbank5_dma_length1_w + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case 5'01011 + assign $0\builder_interface5_bank_bus_dat_r[7:0] \builder_csrbank5_dma_length0_w + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case 5'01100 + assign $0\builder_interface5_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank5_dma_enable0_w } + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case 5'01101 + assign $0\builder_interface5_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank5_dma_done_w } + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case 5'01110 + assign $0\builder_interface5_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank5_dma_loop0_w } + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case 5'01111 + assign $0\builder_interface5_bank_bus_dat_r[7:0] \builder_csrbank5_dma_offset3_w + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case 5'10000 + assign $0\builder_interface5_bank_bus_dat_r[7:0] \builder_csrbank5_dma_offset2_w + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case 5'10001 + assign $0\builder_interface5_bank_bus_dat_r[7:0] \builder_csrbank5_dma_offset1_w + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case 5'10010 + assign $0\builder_interface5_bank_bus_dat_r[7:0] \builder_csrbank5_dma_offset0_w + case + end + case + end + attribute \src "build/ls180/gateware/ls180.v:8689.2-8691.5" + switch \builder_csrbank5_dma_base7_re + attribute \src "build/ls180/gateware/ls180.v:8689.6-8689.35" + case 1'1 + assign $0\libresocsim_sdmem2block_dma_base_storage[63:0] [63:56] \builder_csrbank5_dma_base7_r + case + end + attribute \src "build/ls180/gateware/ls180.v:8692.2-8694.5" + switch \builder_csrbank5_dma_base6_re + attribute \src "build/ls180/gateware/ls180.v:8692.6-8692.35" + case 1'1 + assign $0\libresocsim_sdmem2block_dma_base_storage[63:0] [55:48] \builder_csrbank5_dma_base6_r + case + end + attribute \src "build/ls180/gateware/ls180.v:8695.2-8697.5" + switch \builder_csrbank5_dma_base5_re + attribute \src "build/ls180/gateware/ls180.v:8695.6-8695.35" + case 1'1 + assign $0\libresocsim_sdmem2block_dma_base_storage[63:0] [47:40] \builder_csrbank5_dma_base5_r + case + end + attribute \src "build/ls180/gateware/ls180.v:8698.2-8700.5" + switch \builder_csrbank5_dma_base4_re + attribute \src "build/ls180/gateware/ls180.v:8698.6-8698.35" + case 1'1 + assign $0\libresocsim_sdmem2block_dma_base_storage[63:0] [39:32] \builder_csrbank5_dma_base4_r + case + end + attribute \src "build/ls180/gateware/ls180.v:8701.2-8703.5" + switch \builder_csrbank5_dma_base3_re + attribute \src "build/ls180/gateware/ls180.v:8701.6-8701.35" + case 1'1 + assign $0\libresocsim_sdmem2block_dma_base_storage[63:0] [31:24] \builder_csrbank5_dma_base3_r + case + end + attribute \src "build/ls180/gateware/ls180.v:8704.2-8706.5" + switch \builder_csrbank5_dma_base2_re + attribute \src "build/ls180/gateware/ls180.v:8704.6-8704.35" + case 1'1 + assign $0\libresocsim_sdmem2block_dma_base_storage[63:0] [23:16] \builder_csrbank5_dma_base2_r + case + end + attribute \src "build/ls180/gateware/ls180.v:8707.2-8709.5" + switch \builder_csrbank5_dma_base1_re + attribute \src "build/ls180/gateware/ls180.v:8707.6-8707.35" + case 1'1 + assign $0\libresocsim_sdmem2block_dma_base_storage[63:0] [15:8] \builder_csrbank5_dma_base1_r + case + end + attribute \src "build/ls180/gateware/ls180.v:8710.2-8712.5" + switch \builder_csrbank5_dma_base0_re + attribute \src "build/ls180/gateware/ls180.v:8710.6-8710.35" + case 1'1 + assign $0\libresocsim_sdmem2block_dma_base_storage[63:0] [7:0] \builder_csrbank5_dma_base0_r + case + end + attribute \src "build/ls180/gateware/ls180.v:8714.2-8716.5" + switch \builder_csrbank5_dma_length3_re + attribute \src "build/ls180/gateware/ls180.v:8714.6-8714.37" + case 1'1 + assign $0\libresocsim_sdmem2block_dma_length_storage[31:0] [31:24] \builder_csrbank5_dma_length3_r + case + end + attribute \src "build/ls180/gateware/ls180.v:8717.2-8719.5" + switch \builder_csrbank5_dma_length2_re + attribute \src "build/ls180/gateware/ls180.v:8717.6-8717.37" + case 1'1 + assign $0\libresocsim_sdmem2block_dma_length_storage[31:0] [23:16] \builder_csrbank5_dma_length2_r + case + end + attribute \src "build/ls180/gateware/ls180.v:8720.2-8722.5" + switch \builder_csrbank5_dma_length1_re + attribute \src "build/ls180/gateware/ls180.v:8720.6-8720.37" + case 1'1 + assign $0\libresocsim_sdmem2block_dma_length_storage[31:0] [15:8] \builder_csrbank5_dma_length1_r + case + end + attribute \src "build/ls180/gateware/ls180.v:8723.2-8725.5" + switch \builder_csrbank5_dma_length0_re + attribute \src "build/ls180/gateware/ls180.v:8723.6-8723.37" + case 1'1 + assign $0\libresocsim_sdmem2block_dma_length_storage[31:0] [7:0] \builder_csrbank5_dma_length0_r + case + end + attribute \src "build/ls180/gateware/ls180.v:8727.2-8729.5" + switch \builder_csrbank5_dma_enable0_re + attribute \src "build/ls180/gateware/ls180.v:8727.6-8727.37" + case 1'1 + assign $0\libresocsim_sdmem2block_dma_enable_storage[0:0] \builder_csrbank5_dma_enable0_r + case + end + attribute \src "build/ls180/gateware/ls180.v:8731.2-8733.5" + switch \builder_csrbank5_dma_loop0_re + attribute \src "build/ls180/gateware/ls180.v:8731.6-8731.35" + case 1'1 + assign $0\libresocsim_sdmem2block_dma_loop_storage[0:0] \builder_csrbank5_dma_loop0_r + case + end + attribute \src "build/ls180/gateware/ls180.v:8736.2-8751.5" + switch \builder_csrbank6_sel + attribute \src "build/ls180/gateware/ls180.v:8736.6-8736.26" + case 1'1 + attribute \src "build/ls180/gateware/ls180.v:8737.3-8750.10" + switch \builder_interface6_bank_bus_adr [1:0] + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case 2'00 + assign $0\builder_interface6_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank6_card_detect_w } + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case 2'01 + assign $0\builder_interface6_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank6_clocker_divider1_w } + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case 2'10 + assign $0\builder_interface6_bank_bus_dat_r[7:0] \builder_csrbank6_clocker_divider0_w + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case 2'11 + assign $0\builder_interface6_bank_bus_dat_r[7:0] { 7'0000000 \libresocsim_init_initialize_w } + case + end + case + end + attribute \src "build/ls180/gateware/ls180.v:8752.2-8754.5" + switch \builder_csrbank6_clocker_divider1_re + attribute \src "build/ls180/gateware/ls180.v:8752.6-8752.42" + case 1'1 + assign $0\libresocsim_clocker_storage[8:0] [8] \builder_csrbank6_clocker_divider1_r + case + end + attribute \src "build/ls180/gateware/ls180.v:8755.2-8757.5" + switch \builder_csrbank6_clocker_divider0_re + attribute \src "build/ls180/gateware/ls180.v:8755.6-8755.42" + case 1'1 + assign $0\libresocsim_clocker_storage[8:0] [7:0] \builder_csrbank6_clocker_divider0_r + case + end + attribute \src "build/ls180/gateware/ls180.v:8760.2-8793.5" + switch \builder_csrbank7_sel + attribute \src "build/ls180/gateware/ls180.v:8760.6-8760.26" + case 1'1 + attribute \src "build/ls180/gateware/ls180.v:8761.3-8792.10" + switch \builder_interface7_bank_bus_adr [3:0] + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case 4'0000 + assign $0\builder_interface7_bank_bus_dat_r[7:0] { 4'0000 \builder_csrbank7_dfii_control0_w } + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case 4'0001 + assign $0\builder_interface7_bank_bus_dat_r[7:0] { 2'00 \builder_csrbank7_dfii_pi0_command0_w } + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case 4'0010 + assign $0\builder_interface7_bank_bus_dat_r[7:0] { 7'0000000 \main_sdram_command_issue_w } + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case 4'0011 + assign $0\builder_interface7_bank_bus_dat_r[7:0] { 3'000 \builder_csrbank7_dfii_pi0_address1_w } + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case 4'0100 + assign $0\builder_interface7_bank_bus_dat_r[7:0] \builder_csrbank7_dfii_pi0_address0_w + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case 4'0101 + assign $0\builder_interface7_bank_bus_dat_r[7:0] { 6'000000 \builder_csrbank7_dfii_pi0_baddress0_w } + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case 4'0110 + assign $0\builder_interface7_bank_bus_dat_r[7:0] \builder_csrbank7_dfii_pi0_wrdata1_w + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case 4'0111 + assign $0\builder_interface7_bank_bus_dat_r[7:0] \builder_csrbank7_dfii_pi0_wrdata0_w + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case 4'1000 + assign $0\builder_interface7_bank_bus_dat_r[7:0] \builder_csrbank7_dfii_pi0_rddata1_w + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case 4'1001 + assign $0\builder_interface7_bank_bus_dat_r[7:0] \builder_csrbank7_dfii_pi0_rddata0_w + case + end + case + end + attribute \src "build/ls180/gateware/ls180.v:8794.2-8796.5" + switch \builder_csrbank7_dfii_control0_re + attribute \src "build/ls180/gateware/ls180.v:8794.6-8794.39" + case 1'1 + assign $0\main_sdram_storage[3:0] \builder_csrbank7_dfii_control0_r + case + end + attribute \src "build/ls180/gateware/ls180.v:8798.2-8800.5" + switch \builder_csrbank7_dfii_pi0_command0_re + attribute \src "build/ls180/gateware/ls180.v:8798.6-8798.43" + case 1'1 + assign $0\main_sdram_command_storage[5:0] \builder_csrbank7_dfii_pi0_command0_r + case + end + attribute \src "build/ls180/gateware/ls180.v:8802.2-8804.5" + switch \builder_csrbank7_dfii_pi0_address1_re + attribute \src "build/ls180/gateware/ls180.v:8802.6-8802.43" + case 1'1 + assign $0\main_sdram_address_storage[12:0] [12:8] \builder_csrbank7_dfii_pi0_address1_r + case + end + attribute \src "build/ls180/gateware/ls180.v:8805.2-8807.5" + switch \builder_csrbank7_dfii_pi0_address0_re + attribute \src "build/ls180/gateware/ls180.v:8805.6-8805.43" + case 1'1 + assign $0\main_sdram_address_storage[12:0] [7:0] \builder_csrbank7_dfii_pi0_address0_r + case + end + attribute \src "build/ls180/gateware/ls180.v:8809.2-8811.5" + switch \builder_csrbank7_dfii_pi0_baddress0_re + attribute \src "build/ls180/gateware/ls180.v:8809.6-8809.44" + case 1'1 + assign $0\main_sdram_baddress_storage[1:0] \builder_csrbank7_dfii_pi0_baddress0_r + case + end + attribute \src "build/ls180/gateware/ls180.v:8813.2-8815.5" + switch \builder_csrbank7_dfii_pi0_wrdata1_re + attribute \src "build/ls180/gateware/ls180.v:8813.6-8813.42" + case 1'1 + assign $0\main_sdram_wrdata_storage[15:0] [15:8] \builder_csrbank7_dfii_pi0_wrdata1_r + case + end + attribute \src "build/ls180/gateware/ls180.v:8816.2-8818.5" + switch \builder_csrbank7_dfii_pi0_wrdata0_re + attribute \src "build/ls180/gateware/ls180.v:8816.6-8816.42" + case 1'1 + assign $0\main_sdram_wrdata_storage[15:0] [7:0] \builder_csrbank7_dfii_pi0_wrdata0_r + case + end + attribute \src "build/ls180/gateware/ls180.v:8821.2-8845.5" + switch \builder_csrbank8_sel + attribute \src "build/ls180/gateware/ls180.v:8821.6-8821.26" + case 1'1 + attribute \src "build/ls180/gateware/ls180.v:8822.3-8844.10" + switch \builder_interface8_bank_bus_adr [2:0] + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case 3'000 + assign $0\builder_interface8_bank_bus_dat_r[7:0] \builder_csrbank8_control1_w + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case 3'001 + assign $0\builder_interface8_bank_bus_dat_r[7:0] \builder_csrbank8_control0_w + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case 3'010 + assign $0\builder_interface8_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank8_status_w } + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case 3'011 + assign $0\builder_interface8_bank_bus_dat_r[7:0] \builder_csrbank8_mosi0_w + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case 3'100 + assign $0\builder_interface8_bank_bus_dat_r[7:0] \builder_csrbank8_miso_w + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case 3'101 + assign $0\builder_interface8_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank8_cs0_w } + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case 3'110 + assign $0\builder_interface8_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank8_loopback0_w } + case + end + case + end + attribute \src "build/ls180/gateware/ls180.v:8846.2-8848.5" + switch \builder_csrbank8_control1_re + attribute \src "build/ls180/gateware/ls180.v:8846.6-8846.34" + case 1'1 + assign $0\main_control_storage[15:0] [15:8] \builder_csrbank8_control1_r + case + end + attribute \src "build/ls180/gateware/ls180.v:8849.2-8851.5" + switch \builder_csrbank8_control0_re + attribute \src "build/ls180/gateware/ls180.v:8849.6-8849.34" + case 1'1 + assign $0\main_control_storage[15:0] [7:0] \builder_csrbank8_control0_r + case + end + attribute \src "build/ls180/gateware/ls180.v:8853.2-8855.5" + switch \builder_csrbank8_mosi0_re + attribute \src "build/ls180/gateware/ls180.v:8853.6-8853.31" + case 1'1 + assign $0\main_mosi_storage[7:0] \builder_csrbank8_mosi0_r + case + end + attribute \src "build/ls180/gateware/ls180.v:8857.2-8859.5" + switch \builder_csrbank8_cs0_re + attribute \src "build/ls180/gateware/ls180.v:8857.6-8857.29" + case 1'1 + assign $0\main_cs_storage[0:0] \builder_csrbank8_cs0_r + case + end + attribute \src "build/ls180/gateware/ls180.v:8861.2-8863.5" + switch \builder_csrbank8_loopback0_re + attribute \src "build/ls180/gateware/ls180.v:8861.6-8861.35" + case 1'1 + assign $0\main_loopback_storage[0:0] \builder_csrbank8_loopback0_r + case + end + attribute \src "build/ls180/gateware/ls180.v:8866.2-8896.5" + switch \builder_csrbank9_sel + attribute \src "build/ls180/gateware/ls180.v:8866.6-8866.26" + case 1'1 + attribute \src "build/ls180/gateware/ls180.v:8867.3-8895.10" + switch \builder_interface9_bank_bus_adr [3:0] + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case 4'0000 + assign $0\builder_interface9_bank_bus_dat_r[7:0] \builder_csrbank9_control1_w + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case 4'0001 + assign $0\builder_interface9_bank_bus_dat_r[7:0] \builder_csrbank9_control0_w + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case 4'0010 + assign $0\builder_interface9_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank9_status_w } + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case 4'0011 + assign $0\builder_interface9_bank_bus_dat_r[7:0] \builder_csrbank9_mosi0_w + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case 4'0100 + assign $0\builder_interface9_bank_bus_dat_r[7:0] \builder_csrbank9_miso_w + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case 4'0101 + assign $0\builder_interface9_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank9_cs0_w } + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case 4'0110 + assign $0\builder_interface9_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank9_loopback0_w } + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case 4'0111 + assign $0\builder_interface9_bank_bus_dat_r[7:0] \builder_csrbank9_clk_divider1_w + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case 4'1000 + assign $0\builder_interface9_bank_bus_dat_r[7:0] \builder_csrbank9_clk_divider0_w + case + end + case + end + attribute \src "build/ls180/gateware/ls180.v:8897.2-8899.5" + switch \builder_csrbank9_control1_re + attribute \src "build/ls180/gateware/ls180.v:8897.6-8897.34" + case 1'1 + assign $0\libresocsim_control_storage[15:0] [15:8] \builder_csrbank9_control1_r + case + end + attribute \src "build/ls180/gateware/ls180.v:8900.2-8902.5" + switch \builder_csrbank9_control0_re + attribute \src "build/ls180/gateware/ls180.v:8900.6-8900.34" + case 1'1 + assign $0\libresocsim_control_storage[15:0] [7:0] \builder_csrbank9_control0_r + case + end + attribute \src "build/ls180/gateware/ls180.v:8904.2-8906.5" + switch \builder_csrbank9_mosi0_re + attribute \src "build/ls180/gateware/ls180.v:8904.6-8904.31" + case 1'1 + assign $0\libresocsim_mosi_storage[7:0] \builder_csrbank9_mosi0_r + case + end + attribute \src "build/ls180/gateware/ls180.v:8908.2-8910.5" + switch \builder_csrbank9_cs0_re + attribute \src "build/ls180/gateware/ls180.v:8908.6-8908.29" + case 1'1 + assign $0\libresocsim_cs_storage[0:0] \builder_csrbank9_cs0_r + case + end + attribute \src "build/ls180/gateware/ls180.v:8912.2-8914.5" + switch \builder_csrbank9_loopback0_re + attribute \src "build/ls180/gateware/ls180.v:8912.6-8912.35" + case 1'1 + assign $0\libresocsim_loopback_storage[0:0] \builder_csrbank9_loopback0_r + case + end + attribute \src "build/ls180/gateware/ls180.v:8916.2-8918.5" + switch \builder_csrbank9_clk_divider1_re + attribute \src "build/ls180/gateware/ls180.v:8916.6-8916.38" + case 1'1 + assign $0\libresocsim_storage[15:0] [15:8] \builder_csrbank9_clk_divider1_r + case + end + attribute \src "build/ls180/gateware/ls180.v:8919.2-8921.5" + switch \builder_csrbank9_clk_divider0_re + attribute \src "build/ls180/gateware/ls180.v:8919.6-8919.38" + case 1'1 + assign $0\libresocsim_storage[15:0] [7:0] \builder_csrbank9_clk_divider0_r + case + end + attribute \src "build/ls180/gateware/ls180.v:8924.2-8978.5" + switch \builder_csrbank10_sel + attribute \src "build/ls180/gateware/ls180.v:8924.6-8924.27" + case 1'1 + attribute \src "build/ls180/gateware/ls180.v:8925.3-8977.10" + switch \builder_interface10_bank_bus_adr [4:0] + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case 5'00000 + assign $0\builder_interface10_bank_bus_dat_r[7:0] \builder_csrbank10_load3_w + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case 5'00001 + assign $0\builder_interface10_bank_bus_dat_r[7:0] \builder_csrbank10_load2_w + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case 5'00010 + assign $0\builder_interface10_bank_bus_dat_r[7:0] \builder_csrbank10_load1_w + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case 5'00011 + assign $0\builder_interface10_bank_bus_dat_r[7:0] \builder_csrbank10_load0_w + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case 5'00100 + assign $0\builder_interface10_bank_bus_dat_r[7:0] \builder_csrbank10_reload3_w + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case 5'00101 + assign $0\builder_interface10_bank_bus_dat_r[7:0] \builder_csrbank10_reload2_w + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case 5'00110 + assign $0\builder_interface10_bank_bus_dat_r[7:0] \builder_csrbank10_reload1_w + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case 5'00111 + assign $0\builder_interface10_bank_bus_dat_r[7:0] \builder_csrbank10_reload0_w + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case 5'01000 + assign $0\builder_interface10_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank10_en0_w } + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case 5'01001 + assign $0\builder_interface10_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank10_update_value0_w } + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case 5'01010 + assign $0\builder_interface10_bank_bus_dat_r[7:0] \builder_csrbank10_value3_w + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case 5'01011 + assign $0\builder_interface10_bank_bus_dat_r[7:0] \builder_csrbank10_value2_w + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case 5'01100 + assign $0\builder_interface10_bank_bus_dat_r[7:0] \builder_csrbank10_value1_w + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case 5'01101 + assign $0\builder_interface10_bank_bus_dat_r[7:0] \builder_csrbank10_value0_w + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case 5'01110 + assign $0\builder_interface10_bank_bus_dat_r[7:0] { 7'0000000 \main_libresocsim_timer_eventmanager_status_w } + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case 5'01111 + assign $0\builder_interface10_bank_bus_dat_r[7:0] { 7'0000000 \main_libresocsim_timer_eventmanager_pending_w } + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case 5'10000 + assign $0\builder_interface10_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank10_ev_enable0_w } + case + end + case + end + attribute \src "build/ls180/gateware/ls180.v:8979.2-8981.5" + switch \builder_csrbank10_load3_re + attribute \src "build/ls180/gateware/ls180.v:8979.6-8979.32" + case 1'1 + assign $0\main_libresocsim_timer_load_storage[31:0] [31:24] \builder_csrbank10_load3_r + case + end + attribute \src "build/ls180/gateware/ls180.v:8982.2-8984.5" + switch \builder_csrbank10_load2_re + attribute \src "build/ls180/gateware/ls180.v:8982.6-8982.32" + case 1'1 + assign $0\main_libresocsim_timer_load_storage[31:0] [23:16] \builder_csrbank10_load2_r + case + end + attribute \src "build/ls180/gateware/ls180.v:8985.2-8987.5" + switch \builder_csrbank10_load1_re + attribute \src "build/ls180/gateware/ls180.v:8985.6-8985.32" + case 1'1 + assign $0\main_libresocsim_timer_load_storage[31:0] [15:8] \builder_csrbank10_load1_r + case + end + attribute \src "build/ls180/gateware/ls180.v:8988.2-8990.5" + switch \builder_csrbank10_load0_re + attribute \src "build/ls180/gateware/ls180.v:8988.6-8988.32" + case 1'1 + assign $0\main_libresocsim_timer_load_storage[31:0] [7:0] \builder_csrbank10_load0_r + case + end + attribute \src "build/ls180/gateware/ls180.v:8992.2-8994.5" + switch \builder_csrbank10_reload3_re + attribute \src "build/ls180/gateware/ls180.v:8992.6-8992.34" + case 1'1 + assign $0\main_libresocsim_timer_reload_storage[31:0] [31:24] \builder_csrbank10_reload3_r + case + end + attribute \src "build/ls180/gateware/ls180.v:8995.2-8997.5" + switch \builder_csrbank10_reload2_re + attribute \src "build/ls180/gateware/ls180.v:8995.6-8995.34" + case 1'1 + assign $0\main_libresocsim_timer_reload_storage[31:0] [23:16] \builder_csrbank10_reload2_r + case + end + attribute \src "build/ls180/gateware/ls180.v:8998.2-9000.5" + switch \builder_csrbank10_reload1_re + attribute \src "build/ls180/gateware/ls180.v:8998.6-8998.34" + case 1'1 + assign $0\main_libresocsim_timer_reload_storage[31:0] [15:8] \builder_csrbank10_reload1_r + case + end + attribute \src "build/ls180/gateware/ls180.v:9001.2-9003.5" + switch \builder_csrbank10_reload0_re + attribute \src "build/ls180/gateware/ls180.v:9001.6-9001.34" + case 1'1 + assign $0\main_libresocsim_timer_reload_storage[31:0] [7:0] \builder_csrbank10_reload0_r + case + end + attribute \src "build/ls180/gateware/ls180.v:9005.2-9007.5" + switch \builder_csrbank10_en0_re + attribute \src "build/ls180/gateware/ls180.v:9005.6-9005.30" + case 1'1 + assign $0\main_libresocsim_timer_en_storage[0:0] \builder_csrbank10_en0_r + case + end + attribute \src "build/ls180/gateware/ls180.v:9009.2-9011.5" + switch \builder_csrbank10_update_value0_re + attribute \src "build/ls180/gateware/ls180.v:9009.6-9009.40" + case 1'1 + assign $0\main_libresocsim_timer_update_value_storage[0:0] \builder_csrbank10_update_value0_r + case + end + attribute \src "build/ls180/gateware/ls180.v:9013.2-9015.5" + switch \builder_csrbank10_ev_enable0_re + attribute \src "build/ls180/gateware/ls180.v:9013.6-9013.37" + case 1'1 + assign $0\main_libresocsim_timer_eventmanager_storage[0:0] \builder_csrbank10_ev_enable0_r + case + end + attribute \src "build/ls180/gateware/ls180.v:9018.2-9045.5" + switch \builder_csrbank11_sel + attribute \src "build/ls180/gateware/ls180.v:9018.6-9018.27" + case 1'1 + attribute \src "build/ls180/gateware/ls180.v:9019.3-9044.10" + switch \builder_interface11_bank_bus_adr [2:0] + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case 3'000 + assign $0\builder_interface11_bank_bus_dat_r[7:0] \main_libresocsim_uart_rxtx_w + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case 3'001 + assign $0\builder_interface11_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank11_txfull_w } + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case 3'010 + assign $0\builder_interface11_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank11_rxempty_w } + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case 3'011 + assign $0\builder_interface11_bank_bus_dat_r[7:0] { 6'000000 \main_libresocsim_uart_eventmanager_status_w } + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case 3'100 + assign $0\builder_interface11_bank_bus_dat_r[7:0] { 6'000000 \main_libresocsim_uart_eventmanager_pending_w } + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case 3'101 + assign $0\builder_interface11_bank_bus_dat_r[7:0] { 6'000000 \builder_csrbank11_ev_enable0_w } + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case 3'110 + assign $0\builder_interface11_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank11_txempty_w } + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case 3'111 + assign $0\builder_interface11_bank_bus_dat_r[7:0] { 7'0000000 \builder_csrbank11_rxfull_w } + case + end + case + end + attribute \src "build/ls180/gateware/ls180.v:9046.2-9048.5" + switch \builder_csrbank11_ev_enable0_re + attribute \src "build/ls180/gateware/ls180.v:9046.6-9046.37" + case 1'1 + assign $0\main_libresocsim_uart_eventmanager_storage[1:0] \builder_csrbank11_ev_enable0_r + case + end + attribute \src "build/ls180/gateware/ls180.v:9051.2-9066.5" + switch \builder_csrbank12_sel + attribute \src "build/ls180/gateware/ls180.v:9051.6-9051.27" + case 1'1 + attribute \src "build/ls180/gateware/ls180.v:9052.3-9065.10" + switch \builder_interface12_bank_bus_adr [1:0] + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case 2'00 + assign $0\builder_interface12_bank_bus_dat_r[7:0] \builder_csrbank12_tuning_word3_w + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case 2'01 + assign $0\builder_interface12_bank_bus_dat_r[7:0] \builder_csrbank12_tuning_word2_w + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case 2'10 + assign $0\builder_interface12_bank_bus_dat_r[7:0] \builder_csrbank12_tuning_word1_w + attribute \src "build/ls180/gateware/ls180.v:0.0-0.0" + case 2'11 + assign $0\builder_interface12_bank_bus_dat_r[7:0] \builder_csrbank12_tuning_word0_w + case + end + case + end + attribute \src "build/ls180/gateware/ls180.v:9067.2-9069.5" + switch \builder_csrbank12_tuning_word3_re + attribute \src "build/ls180/gateware/ls180.v:9067.6-9067.39" + case 1'1 + assign $0\main_libresocsim_storage[31:0] [31:24] \builder_csrbank12_tuning_word3_r + case + end + attribute \src "build/ls180/gateware/ls180.v:9070.2-9072.5" + switch \builder_csrbank12_tuning_word2_re + attribute \src "build/ls180/gateware/ls180.v:9070.6-9070.39" + case 1'1 + assign $0\main_libresocsim_storage[31:0] [23:16] \builder_csrbank12_tuning_word2_r + case + end + attribute \src "build/ls180/gateware/ls180.v:9073.2-9075.5" + switch \builder_csrbank12_tuning_word1_re + attribute \src "build/ls180/gateware/ls180.v:9073.6-9073.39" + case 1'1 + assign $0\main_libresocsim_storage[31:0] [15:8] \builder_csrbank12_tuning_word1_r + case + end + attribute \src "build/ls180/gateware/ls180.v:9076.2-9078.5" + switch \builder_csrbank12_tuning_word0_re + attribute \src "build/ls180/gateware/ls180.v:9076.6-9076.39" + case 1'1 + assign $0\main_libresocsim_storage[31:0] [7:0] \builder_csrbank12_tuning_word0_r + case + end + attribute \src "build/ls180/gateware/ls180.v:9080.2-9356.5" + switch \sys_rst + attribute \src "build/ls180/gateware/ls180.v:9080.6-9080.13" + case 1'1 + assign $0\main_libresocsim_soccontroller_reset_storage[0:0] 1'0 + assign $0\main_libresocsim_soccontroller_reset_re[0:0] 1'0 + assign $0\main_libresocsim_soccontroller_scratch_storage[31:0] 305419896 + assign $0\main_libresocsim_soccontroller_scratch_re[0:0] 1'0 + assign $0\main_libresocsim_soccontroller_bus_errors[31:0] 0 + assign $0\main_libresocsim_converter0_counter[0:0] 1'0 + assign $0\main_libresocsim_converter1_counter[0:0] 1'0 + assign $0\main_libresocsim_ram_bus_ack[0:0] 1'0 + assign $0\serial_tx[0:0] 1'1 + assign $0\main_libresocsim_storage[31:0] 9895604 + assign $0\main_libresocsim_re[0:0] 1'0 + assign $0\main_libresocsim_sink_ready[0:0] 1'0 + assign $0\main_libresocsim_uart_clk_txen[0:0] 1'0 + assign $0\main_libresocsim_tx_busy[0:0] 1'0 + assign $0\main_libresocsim_source_valid[0:0] 1'0 + assign $0\main_libresocsim_uart_clk_rxen[0:0] 1'0 + assign $0\main_libresocsim_rx_r[0:0] 1'0 + assign $0\main_libresocsim_rx_busy[0:0] 1'0 + assign $0\main_libresocsim_uart_tx_pending[0:0] 1'0 + assign $0\main_libresocsim_uart_tx_old_trigger[0:0] 1'0 + assign $0\main_libresocsim_uart_rx_pending[0:0] 1'0 + assign $0\main_libresocsim_uart_rx_old_trigger[0:0] 1'0 + assign $0\main_libresocsim_uart_eventmanager_storage[1:0] 2'00 + assign $0\main_libresocsim_uart_eventmanager_re[0:0] 1'0 + assign $0\main_libresocsim_uart_tx_fifo_readable[0:0] 1'0 + assign $0\main_libresocsim_uart_tx_fifo_level0[4:0] 5'00000 + assign $0\main_libresocsim_uart_tx_fifo_produce[3:0] 4'0000 + assign $0\main_libresocsim_uart_tx_fifo_consume[3:0] 4'0000 + assign $0\main_libresocsim_uart_rx_fifo_readable[0:0] 1'0 + assign $0\main_libresocsim_uart_rx_fifo_level0[4:0] 5'00000 + assign $0\main_libresocsim_uart_rx_fifo_produce[3:0] 4'0000 + assign $0\main_libresocsim_uart_rx_fifo_consume[3:0] 4'0000 + assign $0\main_libresocsim_timer_load_storage[31:0] 0 + assign $0\main_libresocsim_timer_load_re[0:0] 1'0 + assign $0\main_libresocsim_timer_reload_storage[31:0] 0 + assign $0\main_libresocsim_timer_reload_re[0:0] 1'0 + assign $0\main_libresocsim_timer_en_storage[0:0] 1'0 + assign $0\main_libresocsim_timer_en_re[0:0] 1'0 + assign $0\main_libresocsim_timer_update_value_storage[0:0] 1'0 + assign $0\main_libresocsim_timer_update_value_re[0:0] 1'0 + assign $0\main_libresocsim_timer_value_status[31:0] 0 + assign $0\main_libresocsim_timer_zero_pending[0:0] 1'0 + assign $0\main_libresocsim_timer_zero_old_trigger[0:0] 1'0 + assign $0\main_libresocsim_timer_eventmanager_storage[0:0] 1'0 + assign $0\main_libresocsim_timer_eventmanager_re[0:0] 1'0 + assign $0\main_libresocsim_timer_value[31:0] 0 + assign $0\main_dfi_p0_rddata_valid[0:0] 1'0 + assign $0\main_rddata_en[2:0] 3'000 + assign $0\main_sdram_storage[3:0] 4'0001 + assign $0\main_sdram_re[0:0] 1'0 + assign $0\main_sdram_command_storage[5:0] 6'000000 + assign $0\main_sdram_command_re[0:0] 1'0 + assign $0\main_sdram_address_re[0:0] 1'0 + assign $0\main_sdram_baddress_re[0:0] 1'0 + assign $0\main_sdram_wrdata_re[0:0] 1'0 + assign $0\main_sdram_status[15:0] 16'0000000000000000 + assign $0\main_sdram_dfi_p0_address[12:0] 13'0000000000000 + assign $0\main_sdram_dfi_p0_bank[1:0] 2'00 + assign $0\main_sdram_dfi_p0_cas_n[0:0] 1'1 + assign $0\main_sdram_dfi_p0_cs_n[0:0] 1'1 + assign $0\main_sdram_dfi_p0_ras_n[0:0] 1'1 + assign $0\main_sdram_dfi_p0_we_n[0:0] 1'1 + assign $0\main_sdram_dfi_p0_wrdata_en[0:0] 1'0 + assign $0\main_sdram_dfi_p0_rddata_en[0:0] 1'0 + assign $0\main_sdram_timer_count1[9:0] 10'1100001101 + assign $0\main_sdram_postponer_req_o[0:0] 1'0 + assign $0\main_sdram_postponer_count[0:0] 1'0 + assign $0\main_sdram_sequencer_done1[0:0] 1'0 + assign $0\main_sdram_sequencer_counter[3:0] 4'0000 + assign $0\main_sdram_sequencer_count[0:0] 1'0 + assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_level[3:0] 4'0000 + assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_produce[2:0] 3'000 + assign $0\main_sdram_bankmachine0_cmd_buffer_lookahead_consume[2:0] 3'000 + assign $0\main_sdram_bankmachine0_cmd_buffer_source_valid[0:0] 1'0 + assign $0\main_sdram_bankmachine0_row[12:0] 13'0000000000000 + assign $0\main_sdram_bankmachine0_row_opened[0:0] 1'0 + assign $0\main_sdram_bankmachine0_twtpcon_ready[0:0] 1'0 + assign $0\main_sdram_bankmachine0_twtpcon_count[2:0] 3'000 + assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_level[3:0] 4'0000 + assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_produce[2:0] 3'000 + assign $0\main_sdram_bankmachine1_cmd_buffer_lookahead_consume[2:0] 3'000 + assign $0\main_sdram_bankmachine1_cmd_buffer_source_valid[0:0] 1'0 + assign $0\main_sdram_bankmachine1_row[12:0] 13'0000000000000 + assign $0\main_sdram_bankmachine1_row_opened[0:0] 1'0 + assign $0\main_sdram_bankmachine1_twtpcon_ready[0:0] 1'0 + assign $0\main_sdram_bankmachine1_twtpcon_count[2:0] 3'000 + assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_level[3:0] 4'0000 + assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_produce[2:0] 3'000 + assign $0\main_sdram_bankmachine2_cmd_buffer_lookahead_consume[2:0] 3'000 + assign $0\main_sdram_bankmachine2_cmd_buffer_source_valid[0:0] 1'0 + assign $0\main_sdram_bankmachine2_row[12:0] 13'0000000000000 + assign $0\main_sdram_bankmachine2_row_opened[0:0] 1'0 + assign $0\main_sdram_bankmachine2_twtpcon_ready[0:0] 1'0 + assign $0\main_sdram_bankmachine2_twtpcon_count[2:0] 3'000 + assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_level[3:0] 4'0000 + assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_produce[2:0] 3'000 + assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_consume[2:0] 3'000 + assign $0\main_sdram_bankmachine3_cmd_buffer_source_valid[0:0] 1'0 + assign $0\main_sdram_bankmachine3_row[12:0] 13'0000000000000 + assign $0\main_sdram_bankmachine3_row_opened[0:0] 1'0 + assign $0\main_sdram_bankmachine3_twtpcon_ready[0:0] 1'0 + assign $0\main_sdram_bankmachine3_twtpcon_count[2:0] 3'000 + assign $0\main_sdram_choose_cmd_grant[1:0] 2'00 + assign $0\main_sdram_choose_req_grant[1:0] 2'00 + assign $0\main_sdram_tccdcon_ready[0:0] 1'0 + assign $0\main_sdram_tccdcon_count[0:0] 1'0 + assign $0\main_sdram_twtrcon_ready[0:0] 1'0 + assign $0\main_sdram_twtrcon_count[2:0] 3'000 + assign $0\main_sdram_time0[4:0] 5'00000 + assign $0\main_sdram_time1[3:0] 4'0000 + assign $0\main_converter_counter[0:0] 1'0 + assign $0\main_cmd_consumed[0:0] 1'0 + assign $0\main_wdata_consumed[0:0] 1'0 + assign $0\spi_master_clk[0:0] 1'0 + assign $0\spi_master_mosi[0:0] 1'0 + assign $0\spi_master_cs_n[0:0] 1'0 + assign $0\main_miso[7:0] 8'00000000 + assign $0\main_control_storage[15:0] 16'0000000000000000 + assign $0\main_control_re[0:0] 1'0 + assign $0\main_mosi_re[0:0] 1'0 + assign $0\main_cs_storage[0:0] 1'1 + assign $0\main_cs_re[0:0] 1'0 + assign $0\main_loopback_storage[0:0] 1'0 + assign $0\main_loopback_re[0:0] 1'0 + assign $0\main_count[2:0] 3'000 + assign $0\main_clk_divider1[15:0] 16'0000000000000000 + assign $0\main_mosi_data[7:0] 8'00000000 + assign $0\main_mosi_sel[2:0] 3'000 + assign $0\main_miso_data[7:0] 8'00000000 + assign $0\libresocsim_clocker_storage[8:0] 9'100000000 + assign $0\libresocsim_clocker_re[0:0] 1'0 + assign $0\libresocsim_clocker_clk0[0:0] 1'0 + assign $0\libresocsim_clocker_clks[8:0] 9'000000000 + assign $0\libresocsim_clocker_clk_d[0:0] 1'0 + assign $0\libresocsim_init_count[7:0] 8'00000000 + assign $0\libresocsim_cmdw_count[7:0] 8'00000000 + assign $0\libresocsim_cmdr_timeout[31:0] 500000 + assign $0\libresocsim_cmdr_count[7:0] 8'00000000 + assign $0\libresocsim_cmdr_cmdr_run[0:0] 1'0 + assign $0\libresocsim_cmdr_cmdr_converter_demux[2:0] 3'000 + assign $0\libresocsim_cmdr_cmdr_converter_strobe_all[0:0] 1'0 + assign $0\libresocsim_cmdr_cmdr_buf_source_valid[0:0] 1'0 + assign $0\libresocsim_cmdr_cmdr_reset[0:0] 1'0 + assign $0\libresocsim_dataw_count[7:0] 8'00000000 + assign $0\libresocsim_dataw_crcr_run[0:0] 1'0 + assign $0\libresocsim_dataw_crcr_converter_demux[2:0] 3'000 + assign $0\libresocsim_dataw_crcr_converter_strobe_all[0:0] 1'0 + assign $0\libresocsim_dataw_crcr_buf_source_valid[0:0] 1'0 + assign $0\libresocsim_dataw_crcr_reset[0:0] 1'0 + assign $0\libresocsim_datar_timeout[31:0] 500000 + assign $0\libresocsim_datar_count[9:0] 10'0000000000 + assign $0\libresocsim_datar_datar_run[0:0] 1'0 + assign $0\libresocsim_datar_datar_converter_demux[0:0] 1'0 + assign $0\libresocsim_datar_datar_converter_strobe_all[0:0] 1'0 + assign $0\libresocsim_datar_datar_buf_source_valid[0:0] 1'0 + assign $0\libresocsim_datar_datar_reset[0:0] 1'0 + assign $0\libresocsim_sdcore_cmd_argument_storage[31:0] 0 + assign $0\libresocsim_sdcore_cmd_argument_re[0:0] 1'0 + assign $0\libresocsim_sdcore_cmd_command_storage[31:0] 0 + assign $0\libresocsim_sdcore_cmd_command_re[0:0] 1'0 + assign $0\libresocsim_sdcore_cmd_response_status[127:0] 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + assign $0\libresocsim_sdcore_block_length_storage[9:0] 10'0000000000 + assign $0\libresocsim_sdcore_block_length_re[0:0] 1'0 + assign $0\libresocsim_sdcore_block_count_storage[31:0] 0 + assign $0\libresocsim_sdcore_block_count_re[0:0] 1'0 + assign $0\libresocsim_sdcore_crc7_inserter_crcreg0[6:0] 7'0000000 + assign $0\libresocsim_sdcore_crc16_inserter_cnt[2:0] 3'000 + assign $0\libresocsim_sdcore_crc16_inserter_crc0_crcreg0[15:0] 16'0000000000000000 + assign $0\libresocsim_sdcore_crc16_inserter_crc1_crcreg0[15:0] 16'0000000000000000 + assign $0\libresocsim_sdcore_crc16_inserter_crc2_crcreg0[15:0] 16'0000000000000000 + assign $0\libresocsim_sdcore_crc16_inserter_crc3_crcreg0[15:0] 16'0000000000000000 + assign $0\libresocsim_sdcore_crc16_inserter_crctmp0[15:0] 16'0000000000000000 + assign $0\libresocsim_sdcore_crc16_inserter_crctmp1[15:0] 16'0000000000000000 + assign $0\libresocsim_sdcore_crc16_inserter_crctmp2[15:0] 16'0000000000000000 + assign $0\libresocsim_sdcore_crc16_inserter_crctmp3[15:0] 16'0000000000000000 + assign $0\libresocsim_sdcore_crc16_checker_val[7:0] 8'00000000 + assign $0\libresocsim_sdcore_crc16_checker_cnt[3:0] 4'0000 + assign $0\libresocsim_sdcore_crc16_checker_crc0_crcreg0[15:0] 16'0000000000000000 + assign $0\libresocsim_sdcore_crc16_checker_crc1_crcreg0[15:0] 16'0000000000000000 + assign $0\libresocsim_sdcore_crc16_checker_crc2_crcreg0[15:0] 16'0000000000000000 + assign $0\libresocsim_sdcore_crc16_checker_crc3_crcreg0[15:0] 16'0000000000000000 + assign $0\libresocsim_sdcore_crc16_checker_crctmp0[15:0] 16'0000000000000000 + assign $0\libresocsim_sdcore_crc16_checker_crctmp1[15:0] 16'0000000000000000 + assign $0\libresocsim_sdcore_crc16_checker_crctmp2[15:0] 16'0000000000000000 + assign $0\libresocsim_sdcore_crc16_checker_crctmp3[15:0] 16'0000000000000000 + assign $0\libresocsim_sdcore_crc16_checker_fifo0[15:0] 16'0000000000000000 + assign $0\libresocsim_sdcore_crc16_checker_fifo1[15:0] 16'0000000000000000 + assign $0\libresocsim_sdcore_crc16_checker_fifo2[15:0] 16'0000000000000000 + assign $0\libresocsim_sdcore_crc16_checker_fifo3[15:0] 16'0000000000000000 + assign $0\libresocsim_sdcore_cmd_count[2:0] 3'000 + assign $0\libresocsim_sdcore_cmd_done[0:0] 1'0 + assign $0\libresocsim_sdcore_cmd_error[0:0] 1'0 + assign $0\libresocsim_sdcore_cmd_timeout[0:0] 1'0 + assign $0\libresocsim_sdcore_data_count[31:0] 0 + assign $0\libresocsim_sdcore_data_done[0:0] 1'0 + assign $0\libresocsim_sdcore_data_error[0:0] 1'0 + assign $0\libresocsim_sdcore_data_timeout[0:0] 1'0 + assign $0\libresocsim_sdblock2mem_fifo_level[5:0] 6'000000 + assign $0\libresocsim_sdblock2mem_fifo_produce[4:0] 5'00000 + assign $0\libresocsim_sdblock2mem_fifo_consume[4:0] 5'00000 + assign $0\libresocsim_sdblock2mem_converter_demux[1:0] 2'00 + assign $0\libresocsim_sdblock2mem_converter_strobe_all[0:0] 1'0 + assign $0\libresocsim_sdblock2mem_wishbonedmawriter_base_storage[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0\libresocsim_sdblock2mem_wishbonedmawriter_base_re[0:0] 1'0 + assign $0\libresocsim_sdblock2mem_wishbonedmawriter_length_storage[31:0] 0 + assign $0\libresocsim_sdblock2mem_wishbonedmawriter_length_re[0:0] 1'0 + assign $0\libresocsim_sdblock2mem_wishbonedmawriter_enable_storage[0:0] 1'0 + assign $0\libresocsim_sdblock2mem_wishbonedmawriter_enable_re[0:0] 1'0 + assign $0\libresocsim_sdblock2mem_wishbonedmawriter_loop_storage[0:0] 1'0 + assign $0\libresocsim_sdblock2mem_wishbonedmawriter_loop_re[0:0] 1'0 + assign $0\libresocsim_sdblock2mem_wishbonedmawriter_offset[31:0] 0 + assign $0\libresocsim_sdmem2block_dma_data[31:0] 0 + assign $0\libresocsim_sdmem2block_dma_base_storage[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0\libresocsim_sdmem2block_dma_base_re[0:0] 1'0 + assign $0\libresocsim_sdmem2block_dma_length_storage[31:0] 0 + assign $0\libresocsim_sdmem2block_dma_length_re[0:0] 1'0 + assign $0\libresocsim_sdmem2block_dma_enable_storage[0:0] 1'0 + assign $0\libresocsim_sdmem2block_dma_enable_re[0:0] 1'0 + assign $0\libresocsim_sdmem2block_dma_loop_storage[0:0] 1'0 + assign $0\libresocsim_sdmem2block_dma_loop_re[0:0] 1'0 + assign $0\libresocsim_sdmem2block_dma_offset[31:0] 0 + assign $0\libresocsim_sdmem2block_converter_mux[1:0] 2'00 + assign $0\libresocsim_sdmem2block_fifo_level[5:0] 6'000000 + assign $0\libresocsim_sdmem2block_fifo_produce[4:0] 5'00000 + assign $0\libresocsim_sdmem2block_fifo_consume[4:0] 5'00000 + assign $0\spisdcard_clk[0:0] 1'0 + assign $0\spisdcard_mosi[0:0] 1'0 + assign $0\spisdcard_cs_n[0:0] 1'0 + assign $0\libresocsim_miso[7:0] 8'00000000 + assign $0\libresocsim_control_storage[15:0] 16'0000000000000000 + assign $0\libresocsim_control_re[0:0] 1'0 + assign $0\libresocsim_mosi_re[0:0] 1'0 + assign $0\libresocsim_cs_storage[0:0] 1'1 + assign $0\libresocsim_cs_re[0:0] 1'0 + assign $0\libresocsim_loopback_storage[0:0] 1'0 + assign $0\libresocsim_loopback_re[0:0] 1'0 + assign $0\libresocsim_count[2:0] 3'000 + assign $0\libresocsim_clk_divider1[15:0] 16'0000000000000000 + assign $0\libresocsim_mosi_data[7:0] 8'00000000 + assign $0\libresocsim_mosi_sel[2:0] 3'000 + assign $0\libresocsim_miso_data[7:0] 8'00000000 + assign $0\libresocsim_storage[15:0] 16'0000000001111101 + assign $0\libresocsim_re[0:0] 1'0 + assign $0\builder_converter0_state[0:0] 1'0 + assign $0\builder_converter1_state[0:0] 1'0 + assign $0\builder_refresher_state[1:0] 2'00 + assign $0\builder_bankmachine0_state[2:0] 3'000 + assign $0\builder_bankmachine1_state[2:0] 3'000 + assign $0\builder_bankmachine2_state[2:0] 3'000 + assign $0\builder_bankmachine3_state[2:0] 3'000 + assign $0\builder_multiplexer_state[2:0] 3'000 + assign $0\builder_new_master_wdata_ready[0:0] 1'0 + assign $0\builder_new_master_rdata_valid0[0:0] 1'0 + assign $0\builder_new_master_rdata_valid1[0:0] 1'0 + assign $0\builder_new_master_rdata_valid2[0:0] 1'0 + assign $0\builder_new_master_rdata_valid3[0:0] 1'0 + assign $0\builder_converter_state[0:0] 1'0 + assign $0\builder_spimaster0_state[1:0] 2'00 + assign $0\builder_sdphy_sdphyinit_state[0:0] 1'0 + assign $0\builder_sdphy_sdphycmdw_state[1:0] 2'00 + assign $0\builder_sdphy_sdphycmdr_state[2:0] 3'000 + assign $0\builder_sdphy_sdphycrcr_state[0:0] 1'0 + assign $0\builder_sdphy_fsm_state[2:0] 3'000 + assign $0\builder_sdphy_sdphydatar_state[2:0] 3'000 + assign $0\builder_sdcore_crcupstreaminserter_state[0:0] 1'0 + assign $0\builder_sdcore_fsm_state[2:0] 3'000 + assign $0\builder_sdblock2memdma_state[1:0] 2'00 + assign $0\builder_sdmem2blockdma_fsm_state[0:0] 1'0 + assign $0\builder_sdmem2blockdma_resetinserter_state[1:0] 2'00 + assign $0\builder_spimaster1_state[1:0] 2'00 + assign $0\builder_libresocsim_we[0:0] 1'0 + assign $0\builder_grant[1:0] 2'00 + assign $0\builder_slave_sel_r[4:0] 5'00000 + assign $0\builder_count[19:0] 20'11110100001001000000 + assign $0\builder_state[1:0] 2'00 + case + end + sync posedge \sys_clk_1 + update \serial_tx $0\serial_tx[0:0] + update \spi_master_clk $0\spi_master_clk[0:0] + update \spi_master_mosi $0\spi_master_mosi[0:0] + update \spi_master_cs_n $0\spi_master_cs_n[0:0] + update \spisdcard_clk $0\spisdcard_clk[0:0] + update \spisdcard_mosi $0\spisdcard_mosi[0:0] + update \spisdcard_cs_n $0\spisdcard_cs_n[0:0] + update \main_libresocsim_soccontroller_reset_storage $0\main_libresocsim_soccontroller_reset_storage[0:0] + update \main_libresocsim_soccontroller_reset_re $0\main_libresocsim_soccontroller_reset_re[0:0] + update \main_libresocsim_soccontroller_scratch_storage $0\main_libresocsim_soccontroller_scratch_storage[31:0] + update \main_libresocsim_soccontroller_scratch_re $0\main_libresocsim_soccontroller_scratch_re[0:0] + update \main_libresocsim_soccontroller_bus_errors $0\main_libresocsim_soccontroller_bus_errors[31:0] + update \main_libresocsim_converter0_counter $0\main_libresocsim_converter0_counter[0:0] + update \main_libresocsim_converter0_dat_r $0\main_libresocsim_converter0_dat_r[63:0] + update \main_libresocsim_converter1_counter $0\main_libresocsim_converter1_counter[0:0] + update \main_libresocsim_converter1_dat_r $0\main_libresocsim_converter1_dat_r[63:0] + update \main_libresocsim_ram_bus_ack $0\main_libresocsim_ram_bus_ack[0:0] + update \main_libresocsim_storage $0\main_libresocsim_storage[31:0] + update \main_libresocsim_re $0\main_libresocsim_re[0:0] + update \main_libresocsim_sink_ready $0\main_libresocsim_sink_ready[0:0] + update \main_libresocsim_uart_clk_txen $0\main_libresocsim_uart_clk_txen[0:0] + update \main_libresocsim_phase_accumulator_tx $0\main_libresocsim_phase_accumulator_tx[31:0] + update \main_libresocsim_tx_reg $0\main_libresocsim_tx_reg[7:0] + update \main_libresocsim_tx_bitcount $0\main_libresocsim_tx_bitcount[3:0] + update \main_libresocsim_tx_busy $0\main_libresocsim_tx_busy[0:0] + update \main_libresocsim_source_valid $0\main_libresocsim_source_valid[0:0] + update \main_libresocsim_source_payload_data $0\main_libresocsim_source_payload_data[7:0] + update \main_libresocsim_uart_clk_rxen $0\main_libresocsim_uart_clk_rxen[0:0] + update \main_libresocsim_phase_accumulator_rx $0\main_libresocsim_phase_accumulator_rx[31:0] + update \main_libresocsim_rx_r $0\main_libresocsim_rx_r[0:0] + update \main_libresocsim_rx_reg $0\main_libresocsim_rx_reg[7:0] + update \main_libresocsim_rx_bitcount $0\main_libresocsim_rx_bitcount[3:0] + update \main_libresocsim_rx_busy $0\main_libresocsim_rx_busy[0:0] + update \main_libresocsim_uart_tx_pending $0\main_libresocsim_uart_tx_pending[0:0] + update \main_libresocsim_uart_tx_old_trigger $0\main_libresocsim_uart_tx_old_trigger[0:0] + update \main_libresocsim_uart_rx_pending $0\main_libresocsim_uart_rx_pending[0:0] + update \main_libresocsim_uart_rx_old_trigger $0\main_libresocsim_uart_rx_old_trigger[0:0] + update \main_libresocsim_uart_eventmanager_storage $0\main_libresocsim_uart_eventmanager_storage[1:0] + update \main_libresocsim_uart_eventmanager_re $0\main_libresocsim_uart_eventmanager_re[0:0] + update \main_libresocsim_uart_tx_fifo_readable $0\main_libresocsim_uart_tx_fifo_readable[0:0] + update \main_libresocsim_uart_tx_fifo_level0 $0\main_libresocsim_uart_tx_fifo_level0[4:0] + update \main_libresocsim_uart_tx_fifo_produce $0\main_libresocsim_uart_tx_fifo_produce[3:0] + update \main_libresocsim_uart_tx_fifo_consume $0\main_libresocsim_uart_tx_fifo_consume[3:0] + update \main_libresocsim_uart_rx_fifo_readable $0\main_libresocsim_uart_rx_fifo_readable[0:0] + update \main_libresocsim_uart_rx_fifo_level0 $0\main_libresocsim_uart_rx_fifo_level0[4:0] + update \main_libresocsim_uart_rx_fifo_produce $0\main_libresocsim_uart_rx_fifo_produce[3:0] + update \main_libresocsim_uart_rx_fifo_consume $0\main_libresocsim_uart_rx_fifo_consume[3:0] + update \main_libresocsim_timer_load_storage $0\main_libresocsim_timer_load_storage[31:0] + update \main_libresocsim_timer_load_re $0\main_libresocsim_timer_load_re[0:0] + update \main_libresocsim_timer_reload_storage $0\main_libresocsim_timer_reload_storage[31:0] + update \main_libresocsim_timer_reload_re $0\main_libresocsim_timer_reload_re[0:0] + update \main_libresocsim_timer_en_storage $0\main_libresocsim_timer_en_storage[0:0] + update \main_libresocsim_timer_en_re $0\main_libresocsim_timer_en_re[0:0] + update \main_libresocsim_timer_update_value_storage $0\main_libresocsim_timer_update_value_storage[0:0] + update \main_libresocsim_timer_update_value_re $0\main_libresocsim_timer_update_value_re[0:0] + update \main_libresocsim_timer_value_status $0\main_libresocsim_timer_value_status[31:0] + update \main_libresocsim_timer_zero_pending $0\main_libresocsim_timer_zero_pending[0:0] + update \main_libresocsim_timer_zero_old_trigger $0\main_libresocsim_timer_zero_old_trigger[0:0] + update \main_libresocsim_timer_eventmanager_storage $0\main_libresocsim_timer_eventmanager_storage[0:0] + update \main_libresocsim_timer_eventmanager_re $0\main_libresocsim_timer_eventmanager_re[0:0] + update \main_libresocsim_timer_value $0\main_libresocsim_timer_value[31:0] + update \main_dfi_p0_rddata_valid $0\main_dfi_p0_rddata_valid[0:0] + update \main_rddata_en $0\main_rddata_en[2:0] + update \main_sdram_storage $0\main_sdram_storage[3:0] + update \main_sdram_re $0\main_sdram_re[0:0] + update \main_sdram_command_storage $0\main_sdram_command_storage[5:0] + update \main_sdram_command_re $0\main_sdram_command_re[0:0] + update \main_sdram_address_storage $0\main_sdram_address_storage[12:0] + update \main_sdram_address_re $0\main_sdram_address_re[0:0] + update \main_sdram_baddress_storage $0\main_sdram_baddress_storage[1:0] + update \main_sdram_baddress_re $0\main_sdram_baddress_re[0:0] + update \main_sdram_wrdata_storage $0\main_sdram_wrdata_storage[15:0] + update \main_sdram_wrdata_re $0\main_sdram_wrdata_re[0:0] + update \main_sdram_status $0\main_sdram_status[15:0] + update \main_sdram_dfi_p0_address $0\main_sdram_dfi_p0_address[12:0] + update \main_sdram_dfi_p0_bank $0\main_sdram_dfi_p0_bank[1:0] + update \main_sdram_dfi_p0_cas_n $0\main_sdram_dfi_p0_cas_n[0:0] + update \main_sdram_dfi_p0_cs_n $0\main_sdram_dfi_p0_cs_n[0:0] + update \main_sdram_dfi_p0_ras_n $0\main_sdram_dfi_p0_ras_n[0:0] + update \main_sdram_dfi_p0_we_n $0\main_sdram_dfi_p0_we_n[0:0] + update \main_sdram_dfi_p0_wrdata_en $0\main_sdram_dfi_p0_wrdata_en[0:0] + update \main_sdram_dfi_p0_rddata_en $0\main_sdram_dfi_p0_rddata_en[0:0] + update \main_sdram_cmd_payload_a $0\main_sdram_cmd_payload_a[12:0] + update \main_sdram_cmd_payload_ba $0\main_sdram_cmd_payload_ba[1:0] + update \main_sdram_cmd_payload_cas $0\main_sdram_cmd_payload_cas[0:0] + update \main_sdram_cmd_payload_ras $0\main_sdram_cmd_payload_ras[0:0] + update \main_sdram_cmd_payload_we $0\main_sdram_cmd_payload_we[0:0] + update \main_sdram_timer_count1 $0\main_sdram_timer_count1[9:0] + update \main_sdram_postponer_req_o $0\main_sdram_postponer_req_o[0:0] + update \main_sdram_postponer_count $0\main_sdram_postponer_count[0:0] + update \main_sdram_sequencer_done1 $0\main_sdram_sequencer_done1[0:0] + update \main_sdram_sequencer_counter $0\main_sdram_sequencer_counter[3:0] + update \main_sdram_sequencer_count $0\main_sdram_sequencer_count[0:0] + update \main_sdram_bankmachine0_cmd_buffer_lookahead_level $0\main_sdram_bankmachine0_cmd_buffer_lookahead_level[3:0] + update \main_sdram_bankmachine0_cmd_buffer_lookahead_produce $0\main_sdram_bankmachine0_cmd_buffer_lookahead_produce[2:0] + update \main_sdram_bankmachine0_cmd_buffer_lookahead_consume $0\main_sdram_bankmachine0_cmd_buffer_lookahead_consume[2:0] + update \main_sdram_bankmachine0_cmd_buffer_source_valid $0\main_sdram_bankmachine0_cmd_buffer_source_valid[0:0] + update \main_sdram_bankmachine0_cmd_buffer_source_first $0\main_sdram_bankmachine0_cmd_buffer_source_first[0:0] + update \main_sdram_bankmachine0_cmd_buffer_source_last $0\main_sdram_bankmachine0_cmd_buffer_source_last[0:0] + update \main_sdram_bankmachine0_cmd_buffer_source_payload_we $0\main_sdram_bankmachine0_cmd_buffer_source_payload_we[0:0] + update \main_sdram_bankmachine0_cmd_buffer_source_payload_addr $0\main_sdram_bankmachine0_cmd_buffer_source_payload_addr[21:0] + update \main_sdram_bankmachine0_row $0\main_sdram_bankmachine0_row[12:0] + update \main_sdram_bankmachine0_row_opened $0\main_sdram_bankmachine0_row_opened[0:0] + update \main_sdram_bankmachine0_twtpcon_ready $0\main_sdram_bankmachine0_twtpcon_ready[0:0] + update \main_sdram_bankmachine0_twtpcon_count $0\main_sdram_bankmachine0_twtpcon_count[2:0] + update \main_sdram_bankmachine1_cmd_buffer_lookahead_level $0\main_sdram_bankmachine1_cmd_buffer_lookahead_level[3:0] + update \main_sdram_bankmachine1_cmd_buffer_lookahead_produce $0\main_sdram_bankmachine1_cmd_buffer_lookahead_produce[2:0] + update \main_sdram_bankmachine1_cmd_buffer_lookahead_consume $0\main_sdram_bankmachine1_cmd_buffer_lookahead_consume[2:0] + update \main_sdram_bankmachine1_cmd_buffer_source_valid $0\main_sdram_bankmachine1_cmd_buffer_source_valid[0:0] + update \main_sdram_bankmachine1_cmd_buffer_source_first $0\main_sdram_bankmachine1_cmd_buffer_source_first[0:0] + update \main_sdram_bankmachine1_cmd_buffer_source_last $0\main_sdram_bankmachine1_cmd_buffer_source_last[0:0] + update \main_sdram_bankmachine1_cmd_buffer_source_payload_we $0\main_sdram_bankmachine1_cmd_buffer_source_payload_we[0:0] + update \main_sdram_bankmachine1_cmd_buffer_source_payload_addr $0\main_sdram_bankmachine1_cmd_buffer_source_payload_addr[21:0] + update \main_sdram_bankmachine1_row $0\main_sdram_bankmachine1_row[12:0] + update \main_sdram_bankmachine1_row_opened $0\main_sdram_bankmachine1_row_opened[0:0] + update \main_sdram_bankmachine1_twtpcon_ready $0\main_sdram_bankmachine1_twtpcon_ready[0:0] + update \main_sdram_bankmachine1_twtpcon_count $0\main_sdram_bankmachine1_twtpcon_count[2:0] + update \main_sdram_bankmachine2_cmd_buffer_lookahead_level $0\main_sdram_bankmachine2_cmd_buffer_lookahead_level[3:0] + update \main_sdram_bankmachine2_cmd_buffer_lookahead_produce $0\main_sdram_bankmachine2_cmd_buffer_lookahead_produce[2:0] + update \main_sdram_bankmachine2_cmd_buffer_lookahead_consume $0\main_sdram_bankmachine2_cmd_buffer_lookahead_consume[2:0] + update \main_sdram_bankmachine2_cmd_buffer_source_valid $0\main_sdram_bankmachine2_cmd_buffer_source_valid[0:0] + update \main_sdram_bankmachine2_cmd_buffer_source_first $0\main_sdram_bankmachine2_cmd_buffer_source_first[0:0] + update \main_sdram_bankmachine2_cmd_buffer_source_last $0\main_sdram_bankmachine2_cmd_buffer_source_last[0:0] + update \main_sdram_bankmachine2_cmd_buffer_source_payload_we $0\main_sdram_bankmachine2_cmd_buffer_source_payload_we[0:0] + update \main_sdram_bankmachine2_cmd_buffer_source_payload_addr $0\main_sdram_bankmachine2_cmd_buffer_source_payload_addr[21:0] + update \main_sdram_bankmachine2_row $0\main_sdram_bankmachine2_row[12:0] + update \main_sdram_bankmachine2_row_opened $0\main_sdram_bankmachine2_row_opened[0:0] + update \main_sdram_bankmachine2_twtpcon_ready $0\main_sdram_bankmachine2_twtpcon_ready[0:0] + update \main_sdram_bankmachine2_twtpcon_count $0\main_sdram_bankmachine2_twtpcon_count[2:0] + update \main_sdram_bankmachine3_cmd_buffer_lookahead_level $0\main_sdram_bankmachine3_cmd_buffer_lookahead_level[3:0] + update \main_sdram_bankmachine3_cmd_buffer_lookahead_produce $0\main_sdram_bankmachine3_cmd_buffer_lookahead_produce[2:0] + update \main_sdram_bankmachine3_cmd_buffer_lookahead_consume $0\main_sdram_bankmachine3_cmd_buffer_lookahead_consume[2:0] + update \main_sdram_bankmachine3_cmd_buffer_source_valid $0\main_sdram_bankmachine3_cmd_buffer_source_valid[0:0] + update \main_sdram_bankmachine3_cmd_buffer_source_first $0\main_sdram_bankmachine3_cmd_buffer_source_first[0:0] + update \main_sdram_bankmachine3_cmd_buffer_source_last $0\main_sdram_bankmachine3_cmd_buffer_source_last[0:0] + update \main_sdram_bankmachine3_cmd_buffer_source_payload_we $0\main_sdram_bankmachine3_cmd_buffer_source_payload_we[0:0] + update \main_sdram_bankmachine3_cmd_buffer_source_payload_addr $0\main_sdram_bankmachine3_cmd_buffer_source_payload_addr[21:0] + update \main_sdram_bankmachine3_row $0\main_sdram_bankmachine3_row[12:0] + update \main_sdram_bankmachine3_row_opened $0\main_sdram_bankmachine3_row_opened[0:0] + update \main_sdram_bankmachine3_twtpcon_ready $0\main_sdram_bankmachine3_twtpcon_ready[0:0] + update \main_sdram_bankmachine3_twtpcon_count $0\main_sdram_bankmachine3_twtpcon_count[2:0] + update \main_sdram_choose_cmd_grant $0\main_sdram_choose_cmd_grant[1:0] + update \main_sdram_choose_req_grant $0\main_sdram_choose_req_grant[1:0] + update \main_sdram_tccdcon_ready $0\main_sdram_tccdcon_ready[0:0] + update \main_sdram_tccdcon_count $0\main_sdram_tccdcon_count[0:0] + update \main_sdram_twtrcon_ready $0\main_sdram_twtrcon_ready[0:0] + update \main_sdram_twtrcon_count $0\main_sdram_twtrcon_count[2:0] + update \main_sdram_time0 $0\main_sdram_time0[4:0] + update \main_sdram_time1 $0\main_sdram_time1[3:0] + update \main_converter_counter $0\main_converter_counter[0:0] + update \main_converter_dat_r $0\main_converter_dat_r[31:0] + update \main_cmd_consumed $0\main_cmd_consumed[0:0] + update \main_wdata_consumed $0\main_wdata_consumed[0:0] + update \main_miso $0\main_miso[7:0] + update \main_control_storage $0\main_control_storage[15:0] + update \main_control_re $0\main_control_re[0:0] + update \main_mosi_storage $0\main_mosi_storage[7:0] + update \main_mosi_re $0\main_mosi_re[0:0] + update \main_cs_storage $0\main_cs_storage[0:0] + update \main_cs_re $0\main_cs_re[0:0] + update \main_loopback_storage $0\main_loopback_storage[0:0] + update \main_loopback_re $0\main_loopback_re[0:0] + update \main_count $0\main_count[2:0] + update \main_clk_divider1 $0\main_clk_divider1[15:0] + update \main_mosi_data $0\main_mosi_data[7:0] + update \main_mosi_sel $0\main_mosi_sel[2:0] + update \main_miso_data $0\main_miso_data[7:0] + update \libresocsim_clocker_storage $0\libresocsim_clocker_storage[8:0] + update \libresocsim_clocker_re $0\libresocsim_clocker_re[0:0] + update \libresocsim_clocker_clk0 $0\libresocsim_clocker_clk0[0:0] + update \libresocsim_clocker_clks $0\libresocsim_clocker_clks[8:0] + update \libresocsim_clocker_clk_d $0\libresocsim_clocker_clk_d[0:0] + update \libresocsim_init_count $0\libresocsim_init_count[7:0] + update \libresocsim_cmdw_count $0\libresocsim_cmdw_count[7:0] + update \libresocsim_cmdr_timeout $0\libresocsim_cmdr_timeout[31:0] + update \libresocsim_cmdr_count $0\libresocsim_cmdr_count[7:0] + update \libresocsim_cmdr_cmdr_run $0\libresocsim_cmdr_cmdr_run[0:0] + update \libresocsim_cmdr_cmdr_converter_source_first $0\libresocsim_cmdr_cmdr_converter_source_first[0:0] + update \libresocsim_cmdr_cmdr_converter_source_last $0\libresocsim_cmdr_cmdr_converter_source_last[0:0] + update \libresocsim_cmdr_cmdr_converter_source_payload_data $0\libresocsim_cmdr_cmdr_converter_source_payload_data[7:0] + update \libresocsim_cmdr_cmdr_converter_source_payload_valid_token_count $0\libresocsim_cmdr_cmdr_converter_source_payload_valid_token_count[3:0] + update \libresocsim_cmdr_cmdr_converter_demux $0\libresocsim_cmdr_cmdr_converter_demux[2:0] + update \libresocsim_cmdr_cmdr_converter_strobe_all $0\libresocsim_cmdr_cmdr_converter_strobe_all[0:0] + update \libresocsim_cmdr_cmdr_buf_source_valid $0\libresocsim_cmdr_cmdr_buf_source_valid[0:0] + update \libresocsim_cmdr_cmdr_buf_source_first $0\libresocsim_cmdr_cmdr_buf_source_first[0:0] + update \libresocsim_cmdr_cmdr_buf_source_last $0\libresocsim_cmdr_cmdr_buf_source_last[0:0] + update \libresocsim_cmdr_cmdr_buf_source_payload_data $0\libresocsim_cmdr_cmdr_buf_source_payload_data[7:0] + update \libresocsim_cmdr_cmdr_reset $0\libresocsim_cmdr_cmdr_reset[0:0] + update \libresocsim_dataw_count $0\libresocsim_dataw_count[7:0] + update \libresocsim_dataw_crcr_run $0\libresocsim_dataw_crcr_run[0:0] + update \libresocsim_dataw_crcr_converter_source_first $0\libresocsim_dataw_crcr_converter_source_first[0:0] + update \libresocsim_dataw_crcr_converter_source_last $0\libresocsim_dataw_crcr_converter_source_last[0:0] + update \libresocsim_dataw_crcr_converter_source_payload_data $0\libresocsim_dataw_crcr_converter_source_payload_data[7:0] + update \libresocsim_dataw_crcr_converter_source_payload_valid_token_count $0\libresocsim_dataw_crcr_converter_source_payload_valid_token_count[3:0] + update \libresocsim_dataw_crcr_converter_demux $0\libresocsim_dataw_crcr_converter_demux[2:0] + update \libresocsim_dataw_crcr_converter_strobe_all $0\libresocsim_dataw_crcr_converter_strobe_all[0:0] + update \libresocsim_dataw_crcr_buf_source_valid $0\libresocsim_dataw_crcr_buf_source_valid[0:0] + update \libresocsim_dataw_crcr_buf_source_first $0\libresocsim_dataw_crcr_buf_source_first[0:0] + update \libresocsim_dataw_crcr_buf_source_last $0\libresocsim_dataw_crcr_buf_source_last[0:0] + update \libresocsim_dataw_crcr_buf_source_payload_data $0\libresocsim_dataw_crcr_buf_source_payload_data[7:0] + update \libresocsim_dataw_crcr_reset $0\libresocsim_dataw_crcr_reset[0:0] + update \libresocsim_datar_timeout $0\libresocsim_datar_timeout[31:0] + update \libresocsim_datar_count $0\libresocsim_datar_count[9:0] + update \libresocsim_datar_datar_run $0\libresocsim_datar_datar_run[0:0] + update \libresocsim_datar_datar_converter_source_first $0\libresocsim_datar_datar_converter_source_first[0:0] + update \libresocsim_datar_datar_converter_source_last $0\libresocsim_datar_datar_converter_source_last[0:0] + update \libresocsim_datar_datar_converter_source_payload_data $0\libresocsim_datar_datar_converter_source_payload_data[7:0] + update \libresocsim_datar_datar_converter_source_payload_valid_token_count $0\libresocsim_datar_datar_converter_source_payload_valid_token_count[1:0] + update \libresocsim_datar_datar_converter_demux $0\libresocsim_datar_datar_converter_demux[0:0] + update \libresocsim_datar_datar_converter_strobe_all $0\libresocsim_datar_datar_converter_strobe_all[0:0] + update \libresocsim_datar_datar_buf_source_valid $0\libresocsim_datar_datar_buf_source_valid[0:0] + update \libresocsim_datar_datar_buf_source_first $0\libresocsim_datar_datar_buf_source_first[0:0] + update \libresocsim_datar_datar_buf_source_last $0\libresocsim_datar_datar_buf_source_last[0:0] + update \libresocsim_datar_datar_buf_source_payload_data $0\libresocsim_datar_datar_buf_source_payload_data[7:0] + update \libresocsim_datar_datar_reset $0\libresocsim_datar_datar_reset[0:0] + update \libresocsim_sdcore_cmd_argument_storage $0\libresocsim_sdcore_cmd_argument_storage[31:0] + update \libresocsim_sdcore_cmd_argument_re $0\libresocsim_sdcore_cmd_argument_re[0:0] + update \libresocsim_sdcore_cmd_command_storage $0\libresocsim_sdcore_cmd_command_storage[31:0] + update \libresocsim_sdcore_cmd_command_re $0\libresocsim_sdcore_cmd_command_re[0:0] + update \libresocsim_sdcore_cmd_response_status $0\libresocsim_sdcore_cmd_response_status[127:0] + update \libresocsim_sdcore_block_length_storage $0\libresocsim_sdcore_block_length_storage[9:0] + update \libresocsim_sdcore_block_length_re $0\libresocsim_sdcore_block_length_re[0:0] + update \libresocsim_sdcore_block_count_storage $0\libresocsim_sdcore_block_count_storage[31:0] + update \libresocsim_sdcore_block_count_re $0\libresocsim_sdcore_block_count_re[0:0] + update \libresocsim_sdcore_crc7_inserter_crcreg0 $0\libresocsim_sdcore_crc7_inserter_crcreg0[6:0] + update \libresocsim_sdcore_crc16_inserter_cnt $0\libresocsim_sdcore_crc16_inserter_cnt[2:0] + update \libresocsim_sdcore_crc16_inserter_crc0_crcreg0 $0\libresocsim_sdcore_crc16_inserter_crc0_crcreg0[15:0] + update \libresocsim_sdcore_crc16_inserter_crc1_crcreg0 $0\libresocsim_sdcore_crc16_inserter_crc1_crcreg0[15:0] + update \libresocsim_sdcore_crc16_inserter_crc2_crcreg0 $0\libresocsim_sdcore_crc16_inserter_crc2_crcreg0[15:0] + update \libresocsim_sdcore_crc16_inserter_crc3_crcreg0 $0\libresocsim_sdcore_crc16_inserter_crc3_crcreg0[15:0] + update \libresocsim_sdcore_crc16_inserter_crctmp0 $0\libresocsim_sdcore_crc16_inserter_crctmp0[15:0] + update \libresocsim_sdcore_crc16_inserter_crctmp1 $0\libresocsim_sdcore_crc16_inserter_crctmp1[15:0] + update \libresocsim_sdcore_crc16_inserter_crctmp2 $0\libresocsim_sdcore_crc16_inserter_crctmp2[15:0] + update \libresocsim_sdcore_crc16_inserter_crctmp3 $0\libresocsim_sdcore_crc16_inserter_crctmp3[15:0] + update \libresocsim_sdcore_crc16_checker_val $0\libresocsim_sdcore_crc16_checker_val[7:0] + update \libresocsim_sdcore_crc16_checker_cnt $0\libresocsim_sdcore_crc16_checker_cnt[3:0] + update \libresocsim_sdcore_crc16_checker_crc0_crcreg0 $0\libresocsim_sdcore_crc16_checker_crc0_crcreg0[15:0] + update \libresocsim_sdcore_crc16_checker_crc1_crcreg0 $0\libresocsim_sdcore_crc16_checker_crc1_crcreg0[15:0] + update \libresocsim_sdcore_crc16_checker_crc2_crcreg0 $0\libresocsim_sdcore_crc16_checker_crc2_crcreg0[15:0] + update \libresocsim_sdcore_crc16_checker_crc3_crcreg0 $0\libresocsim_sdcore_crc16_checker_crc3_crcreg0[15:0] + update \libresocsim_sdcore_crc16_checker_crctmp0 $0\libresocsim_sdcore_crc16_checker_crctmp0[15:0] + update \libresocsim_sdcore_crc16_checker_crctmp1 $0\libresocsim_sdcore_crc16_checker_crctmp1[15:0] + update \libresocsim_sdcore_crc16_checker_crctmp2 $0\libresocsim_sdcore_crc16_checker_crctmp2[15:0] + update \libresocsim_sdcore_crc16_checker_crctmp3 $0\libresocsim_sdcore_crc16_checker_crctmp3[15:0] + update \libresocsim_sdcore_crc16_checker_fifo0 $0\libresocsim_sdcore_crc16_checker_fifo0[15:0] + update \libresocsim_sdcore_crc16_checker_fifo1 $0\libresocsim_sdcore_crc16_checker_fifo1[15:0] + update \libresocsim_sdcore_crc16_checker_fifo2 $0\libresocsim_sdcore_crc16_checker_fifo2[15:0] + update \libresocsim_sdcore_crc16_checker_fifo3 $0\libresocsim_sdcore_crc16_checker_fifo3[15:0] + update \libresocsim_sdcore_cmd_count $0\libresocsim_sdcore_cmd_count[2:0] + update \libresocsim_sdcore_cmd_done $0\libresocsim_sdcore_cmd_done[0:0] + update \libresocsim_sdcore_cmd_error $0\libresocsim_sdcore_cmd_error[0:0] + update \libresocsim_sdcore_cmd_timeout $0\libresocsim_sdcore_cmd_timeout[0:0] + update \libresocsim_sdcore_data_count $0\libresocsim_sdcore_data_count[31:0] + update \libresocsim_sdcore_data_done $0\libresocsim_sdcore_data_done[0:0] + update \libresocsim_sdcore_data_error $0\libresocsim_sdcore_data_error[0:0] + update \libresocsim_sdcore_data_timeout $0\libresocsim_sdcore_data_timeout[0:0] + update \libresocsim_sdblock2mem_fifo_level $0\libresocsim_sdblock2mem_fifo_level[5:0] + update \libresocsim_sdblock2mem_fifo_produce $0\libresocsim_sdblock2mem_fifo_produce[4:0] + update \libresocsim_sdblock2mem_fifo_consume $0\libresocsim_sdblock2mem_fifo_consume[4:0] + update \libresocsim_sdblock2mem_converter_source_first $0\libresocsim_sdblock2mem_converter_source_first[0:0] + update \libresocsim_sdblock2mem_converter_source_last $0\libresocsim_sdblock2mem_converter_source_last[0:0] + update \libresocsim_sdblock2mem_converter_source_payload_data $0\libresocsim_sdblock2mem_converter_source_payload_data[31:0] + update \libresocsim_sdblock2mem_converter_source_payload_valid_token_count $0\libresocsim_sdblock2mem_converter_source_payload_valid_token_count[2:0] + update \libresocsim_sdblock2mem_converter_demux $0\libresocsim_sdblock2mem_converter_demux[1:0] + update \libresocsim_sdblock2mem_converter_strobe_all $0\libresocsim_sdblock2mem_converter_strobe_all[0:0] + update \libresocsim_sdblock2mem_wishbonedmawriter_base_storage $0\libresocsim_sdblock2mem_wishbonedmawriter_base_storage[63:0] + update \libresocsim_sdblock2mem_wishbonedmawriter_base_re $0\libresocsim_sdblock2mem_wishbonedmawriter_base_re[0:0] + update \libresocsim_sdblock2mem_wishbonedmawriter_length_storage $0\libresocsim_sdblock2mem_wishbonedmawriter_length_storage[31:0] + update \libresocsim_sdblock2mem_wishbonedmawriter_length_re $0\libresocsim_sdblock2mem_wishbonedmawriter_length_re[0:0] + update \libresocsim_sdblock2mem_wishbonedmawriter_enable_storage $0\libresocsim_sdblock2mem_wishbonedmawriter_enable_storage[0:0] + update \libresocsim_sdblock2mem_wishbonedmawriter_enable_re $0\libresocsim_sdblock2mem_wishbonedmawriter_enable_re[0:0] + update \libresocsim_sdblock2mem_wishbonedmawriter_loop_storage $0\libresocsim_sdblock2mem_wishbonedmawriter_loop_storage[0:0] + update \libresocsim_sdblock2mem_wishbonedmawriter_loop_re $0\libresocsim_sdblock2mem_wishbonedmawriter_loop_re[0:0] + update \libresocsim_sdblock2mem_wishbonedmawriter_offset $0\libresocsim_sdblock2mem_wishbonedmawriter_offset[31:0] + update \libresocsim_sdmem2block_dma_data $0\libresocsim_sdmem2block_dma_data[31:0] + update \libresocsim_sdmem2block_dma_base_storage $0\libresocsim_sdmem2block_dma_base_storage[63:0] + update \libresocsim_sdmem2block_dma_base_re $0\libresocsim_sdmem2block_dma_base_re[0:0] + update \libresocsim_sdmem2block_dma_length_storage $0\libresocsim_sdmem2block_dma_length_storage[31:0] + update \libresocsim_sdmem2block_dma_length_re $0\libresocsim_sdmem2block_dma_length_re[0:0] + update \libresocsim_sdmem2block_dma_enable_storage $0\libresocsim_sdmem2block_dma_enable_storage[0:0] + update \libresocsim_sdmem2block_dma_enable_re $0\libresocsim_sdmem2block_dma_enable_re[0:0] + update \libresocsim_sdmem2block_dma_loop_storage $0\libresocsim_sdmem2block_dma_loop_storage[0:0] + update \libresocsim_sdmem2block_dma_loop_re $0\libresocsim_sdmem2block_dma_loop_re[0:0] + update \libresocsim_sdmem2block_dma_offset $0\libresocsim_sdmem2block_dma_offset[31:0] + update \libresocsim_sdmem2block_converter_mux $0\libresocsim_sdmem2block_converter_mux[1:0] + update \libresocsim_sdmem2block_fifo_level $0\libresocsim_sdmem2block_fifo_level[5:0] + update \libresocsim_sdmem2block_fifo_produce $0\libresocsim_sdmem2block_fifo_produce[4:0] + update \libresocsim_sdmem2block_fifo_consume $0\libresocsim_sdmem2block_fifo_consume[4:0] + update \libresocsim_miso $0\libresocsim_miso[7:0] + update \libresocsim_control_storage $0\libresocsim_control_storage[15:0] + update \libresocsim_control_re $0\libresocsim_control_re[0:0] + update \libresocsim_mosi_storage $0\libresocsim_mosi_storage[7:0] + update \libresocsim_mosi_re $0\libresocsim_mosi_re[0:0] + update \libresocsim_cs_storage $0\libresocsim_cs_storage[0:0] + update \libresocsim_cs_re $0\libresocsim_cs_re[0:0] + update \libresocsim_loopback_storage $0\libresocsim_loopback_storage[0:0] + update \libresocsim_loopback_re $0\libresocsim_loopback_re[0:0] + update \libresocsim_count $0\libresocsim_count[2:0] + update \libresocsim_clk_divider1 $0\libresocsim_clk_divider1[15:0] + update \libresocsim_mosi_data $0\libresocsim_mosi_data[7:0] + update \libresocsim_mosi_sel $0\libresocsim_mosi_sel[2:0] + update \libresocsim_miso_data $0\libresocsim_miso_data[7:0] + update \libresocsim_storage $0\libresocsim_storage[15:0] + update \libresocsim_re $0\libresocsim_re[0:0] + update \builder_converter0_state $0\builder_converter0_state[0:0] + update \builder_converter1_state $0\builder_converter1_state[0:0] + update \builder_refresher_state $0\builder_refresher_state[1:0] + update \builder_bankmachine0_state $0\builder_bankmachine0_state[2:0] + update \builder_bankmachine1_state $0\builder_bankmachine1_state[2:0] + update \builder_bankmachine2_state $0\builder_bankmachine2_state[2:0] + update \builder_bankmachine3_state $0\builder_bankmachine3_state[2:0] + update \builder_multiplexer_state $0\builder_multiplexer_state[2:0] + update \builder_new_master_wdata_ready $0\builder_new_master_wdata_ready[0:0] + update \builder_new_master_rdata_valid0 $0\builder_new_master_rdata_valid0[0:0] + update \builder_new_master_rdata_valid1 $0\builder_new_master_rdata_valid1[0:0] + update \builder_new_master_rdata_valid2 $0\builder_new_master_rdata_valid2[0:0] + update \builder_new_master_rdata_valid3 $0\builder_new_master_rdata_valid3[0:0] + update \builder_converter_state $0\builder_converter_state[0:0] + update \builder_spimaster0_state $0\builder_spimaster0_state[1:0] + update \builder_sdphy_sdphyinit_state $0\builder_sdphy_sdphyinit_state[0:0] + update \builder_sdphy_sdphycmdw_state $0\builder_sdphy_sdphycmdw_state[1:0] + update \builder_sdphy_sdphycmdr_state $0\builder_sdphy_sdphycmdr_state[2:0] + update \builder_sdphy_sdphycrcr_state $0\builder_sdphy_sdphycrcr_state[0:0] + update \builder_sdphy_fsm_state $0\builder_sdphy_fsm_state[2:0] + update \builder_sdphy_sdphydatar_state $0\builder_sdphy_sdphydatar_state[2:0] + update \builder_sdcore_crcupstreaminserter_state $0\builder_sdcore_crcupstreaminserter_state[0:0] + update \builder_sdcore_fsm_state $0\builder_sdcore_fsm_state[2:0] + update \builder_sdblock2memdma_state $0\builder_sdblock2memdma_state[1:0] + update \builder_sdmem2blockdma_fsm_state $0\builder_sdmem2blockdma_fsm_state[0:0] + update \builder_sdmem2blockdma_resetinserter_state $0\builder_sdmem2blockdma_resetinserter_state[1:0] + update \builder_spimaster1_state $0\builder_spimaster1_state[1:0] + update \builder_libresocsim_adr $0\builder_libresocsim_adr[13:0] + update \builder_libresocsim_we $0\builder_libresocsim_we[0:0] + update \builder_libresocsim_dat_w $0\builder_libresocsim_dat_w[7:0] + update \builder_grant $0\builder_grant[1:0] + update \builder_slave_sel_r $0\builder_slave_sel_r[4:0] + update \builder_count $0\builder_count[19:0] + update \builder_interface0_bank_bus_dat_r $0\builder_interface0_bank_bus_dat_r[7:0] + update \builder_interface1_bank_bus_dat_r $0\builder_interface1_bank_bus_dat_r[7:0] + update \builder_interface2_bank_bus_dat_r $0\builder_interface2_bank_bus_dat_r[7:0] + update \builder_interface3_bank_bus_dat_r $0\builder_interface3_bank_bus_dat_r[7:0] + update \builder_interface4_bank_bus_dat_r $0\builder_interface4_bank_bus_dat_r[7:0] + update \builder_interface5_bank_bus_dat_r $0\builder_interface5_bank_bus_dat_r[7:0] + update \builder_interface6_bank_bus_dat_r $0\builder_interface6_bank_bus_dat_r[7:0] + update \builder_interface7_bank_bus_dat_r $0\builder_interface7_bank_bus_dat_r[7:0] + update \builder_interface8_bank_bus_dat_r $0\builder_interface8_bank_bus_dat_r[7:0] + update \builder_interface9_bank_bus_dat_r $0\builder_interface9_bank_bus_dat_r[7:0] + update \builder_interface10_bank_bus_dat_r $0\builder_interface10_bank_bus_dat_r[7:0] + update \builder_interface11_bank_bus_dat_r $0\builder_interface11_bank_bus_dat_r[7:0] + update \builder_interface12_bank_bus_dat_r $0\builder_interface12_bank_bus_dat_r[7:0] + update \builder_state $0\builder_state[1:0] + update \builder_multiregimpl0_regs0 $0\builder_multiregimpl0_regs0[0:0] + update \builder_multiregimpl0_regs1 $0\builder_multiregimpl0_regs1[0:0] + update \builder_multiregimpl1_regs0 $0\builder_multiregimpl1_regs0[7:0] + update \builder_multiregimpl1_regs1 $0\builder_multiregimpl1_regs1[7:0] + update \builder_multiregimpl2_regs0 $0\builder_multiregimpl2_regs0[7:0] + update \builder_multiregimpl2_regs1 $0\builder_multiregimpl2_regs1[7:0] + end + attribute \src "build/ls180/gateware/ls180.v:707.5-707.44" + process $proc$build/ls180/gateware/ls180.v:707$2828 + assign { } { } + assign $1\main_sdram_bankmachine2_row_open[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine2_row_open $1\main_sdram_bankmachine2_row_open[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:708.5-708.45" + process $proc$build/ls180/gateware/ls180.v:708$2829 + assign { } { } + assign $1\main_sdram_bankmachine2_row_close[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine2_row_close $1\main_sdram_bankmachine2_row_close[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:709.5-709.54" + process $proc$build/ls180/gateware/ls180.v:709$2830 + assign { } { } + assign $1\main_sdram_bankmachine2_row_col_n_addr_sel[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine2_row_col_n_addr_sel $1\main_sdram_bankmachine2_row_col_n_addr_sel[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:711.32-711.76" + process $proc$build/ls180/gateware/ls180.v:711$2831 + assign { } { } + assign $1\main_sdram_bankmachine2_twtpcon_ready[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine2_twtpcon_ready $1\main_sdram_bankmachine2_twtpcon_ready[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:712.11-712.55" + process $proc$build/ls180/gateware/ls180.v:712$2832 + assign { } { } + assign $1\main_sdram_bankmachine2_twtpcon_count[2:0] 3'000 + sync always + sync init + update \main_sdram_bankmachine2_twtpcon_count $1\main_sdram_bankmachine2_twtpcon_count[2:0] + end + attribute \src "build/ls180/gateware/ls180.v:714.32-714.75" + process $proc$build/ls180/gateware/ls180.v:714$2833 + assign { } { } + assign $0\main_sdram_bankmachine2_trccon_ready[0:0] 1'1 + sync always + update \main_sdram_bankmachine2_trccon_ready $0\main_sdram_bankmachine2_trccon_ready[0:0] + sync init + end + attribute \src "build/ls180/gateware/ls180.v:716.32-716.76" + process $proc$build/ls180/gateware/ls180.v:716$2834 + assign { } { } + assign $0\main_sdram_bankmachine2_trascon_ready[0:0] 1'1 + sync always + update \main_sdram_bankmachine2_trascon_ready $0\main_sdram_bankmachine2_trascon_ready[0:0] + sync init + end + attribute \src "build/ls180/gateware/ls180.v:72.5-72.50" + process $proc$build/ls180/gateware/ls180.v:72$2574 + assign { } { } + assign $0\main_libresocsim_libresoc_xics_icp_ack[0:0] 1'0 + sync always + update \main_libresocsim_libresoc_xics_icp_ack $0\main_libresocsim_libresoc_xics_icp_ack[0:0] + sync init + end + attribute \src "build/ls180/gateware/ls180.v:722.5-722.51" + process $proc$build/ls180/gateware/ls180.v:722$2835 + assign { } { } + assign $1\main_sdram_bankmachine3_req_wdata_ready[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine3_req_wdata_ready $1\main_sdram_bankmachine3_req_wdata_ready[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:723.5-723.51" + process $proc$build/ls180/gateware/ls180.v:723$2836 + assign { } { } + assign $1\main_sdram_bankmachine3_req_rdata_valid[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine3_req_rdata_valid $1\main_sdram_bankmachine3_req_rdata_valid[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:725.5-725.47" + process $proc$build/ls180/gateware/ls180.v:725$2837 + assign { } { } + assign $1\main_sdram_bankmachine3_refresh_gnt[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine3_refresh_gnt $1\main_sdram_bankmachine3_refresh_gnt[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:726.5-726.45" + process $proc$build/ls180/gateware/ls180.v:726$2838 + assign { } { } + assign $1\main_sdram_bankmachine3_cmd_valid[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine3_cmd_valid $1\main_sdram_bankmachine3_cmd_valid[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:727.5-727.45" + process $proc$build/ls180/gateware/ls180.v:727$2839 + assign { } { } + assign $1\main_sdram_bankmachine3_cmd_ready[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine3_cmd_ready $1\main_sdram_bankmachine3_cmd_ready[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:728.12-728.57" + process $proc$build/ls180/gateware/ls180.v:728$2840 + assign { } { } + assign $1\main_sdram_bankmachine3_cmd_payload_a[12:0] 13'0000000000000 + sync always + sync init + update \main_sdram_bankmachine3_cmd_payload_a $1\main_sdram_bankmachine3_cmd_payload_a[12:0] + end + attribute \src "build/ls180/gateware/ls180.v:730.5-730.51" + process $proc$build/ls180/gateware/ls180.v:730$2841 + assign { } { } + assign $1\main_sdram_bankmachine3_cmd_payload_cas[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine3_cmd_payload_cas $1\main_sdram_bankmachine3_cmd_payload_cas[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:731.5-731.51" + process $proc$build/ls180/gateware/ls180.v:731$2842 + assign { } { } + assign $1\main_sdram_bankmachine3_cmd_payload_ras[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine3_cmd_payload_ras $1\main_sdram_bankmachine3_cmd_payload_ras[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:732.5-732.50" + process $proc$build/ls180/gateware/ls180.v:732$2843 + assign { } { } + assign $1\main_sdram_bankmachine3_cmd_payload_we[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine3_cmd_payload_we $1\main_sdram_bankmachine3_cmd_payload_we[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:733.5-733.54" + process $proc$build/ls180/gateware/ls180.v:733$2844 + assign { } { } + assign $1\main_sdram_bankmachine3_cmd_payload_is_cmd[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine3_cmd_payload_is_cmd $1\main_sdram_bankmachine3_cmd_payload_is_cmd[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:734.5-734.55" + process $proc$build/ls180/gateware/ls180.v:734$2845 + assign { } { } + assign $1\main_sdram_bankmachine3_cmd_payload_is_read[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine3_cmd_payload_is_read $1\main_sdram_bankmachine3_cmd_payload_is_read[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:735.5-735.56" + process $proc$build/ls180/gateware/ls180.v:735$2846 + assign { } { } + assign $1\main_sdram_bankmachine3_cmd_payload_is_write[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine3_cmd_payload_is_write $1\main_sdram_bankmachine3_cmd_payload_is_write[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:736.5-736.50" + process $proc$build/ls180/gateware/ls180.v:736$2847 + assign { } { } + assign $1\main_sdram_bankmachine3_auto_precharge[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine3_auto_precharge $1\main_sdram_bankmachine3_auto_precharge[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:739.5-739.67" + process $proc$build/ls180/gateware/ls180.v:739$2848 + assign { } { } + assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_sink_first[0:0] 1'0 + sync always + update \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_first $0\main_sdram_bankmachine3_cmd_buffer_lookahead_sink_first[0:0] + sync init + end + attribute \src "build/ls180/gateware/ls180.v:740.5-740.66" + process $proc$build/ls180/gateware/ls180.v:740$2849 + assign { } { } + assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_sink_last[0:0] 1'0 + sync always + update \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_last $0\main_sdram_bankmachine3_cmd_buffer_lookahead_sink_last[0:0] + sync init + end + attribute \src "build/ls180/gateware/ls180.v:755.11-755.68" + process $proc$build/ls180/gateware/ls180.v:755$2850 + assign { } { } + assign $1\main_sdram_bankmachine3_cmd_buffer_lookahead_level[3:0] 4'0000 + sync always + sync init + update \main_sdram_bankmachine3_cmd_buffer_lookahead_level $1\main_sdram_bankmachine3_cmd_buffer_lookahead_level[3:0] + end + attribute \src "build/ls180/gateware/ls180.v:756.5-756.64" + process $proc$build/ls180/gateware/ls180.v:756$2851 + assign { } { } + assign $0\main_sdram_bankmachine3_cmd_buffer_lookahead_replace[0:0] 1'0 + sync always + update \main_sdram_bankmachine3_cmd_buffer_lookahead_replace $0\main_sdram_bankmachine3_cmd_buffer_lookahead_replace[0:0] + sync init + end + attribute \src "build/ls180/gateware/ls180.v:757.11-757.70" + process $proc$build/ls180/gateware/ls180.v:757$2852 + assign { } { } + assign $1\main_sdram_bankmachine3_cmd_buffer_lookahead_produce[2:0] 3'000 + sync always + sync init + update \main_sdram_bankmachine3_cmd_buffer_lookahead_produce $1\main_sdram_bankmachine3_cmd_buffer_lookahead_produce[2:0] + end + attribute \src "build/ls180/gateware/ls180.v:758.11-758.70" + process $proc$build/ls180/gateware/ls180.v:758$2853 + assign { } { } + assign $1\main_sdram_bankmachine3_cmd_buffer_lookahead_consume[2:0] 3'000 + sync always + sync init + update \main_sdram_bankmachine3_cmd_buffer_lookahead_consume $1\main_sdram_bankmachine3_cmd_buffer_lookahead_consume[2:0] + end + attribute \src "build/ls180/gateware/ls180.v:759.11-759.73" + process $proc$build/ls180/gateware/ls180.v:759$2854 + assign { } { } + assign $1\main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr[2:0] 3'000 + sync always + sync init + update \main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr $1\main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr[2:0] + end + attribute \src "build/ls180/gateware/ls180.v:76.5-76.50" + process $proc$build/ls180/gateware/ls180.v:76$2575 + assign { } { } + assign $0\main_libresocsim_libresoc_xics_icp_err[0:0] 1'0 + sync always + update \main_libresocsim_libresoc_xics_icp_err $0\main_libresocsim_libresoc_xics_icp_err[0:0] + sync init + end + attribute \src "build/ls180/gateware/ls180.v:780.5-780.59" + process $proc$build/ls180/gateware/ls180.v:780$2855 + assign { } { } + assign $1\main_sdram_bankmachine3_cmd_buffer_source_valid[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine3_cmd_buffer_source_valid $1\main_sdram_bankmachine3_cmd_buffer_source_valid[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:782.5-782.59" + process $proc$build/ls180/gateware/ls180.v:782$2856 + assign { } { } + assign $1\main_sdram_bankmachine3_cmd_buffer_source_first[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine3_cmd_buffer_source_first $1\main_sdram_bankmachine3_cmd_buffer_source_first[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:783.5-783.58" + process $proc$build/ls180/gateware/ls180.v:783$2857 + assign { } { } + assign $1\main_sdram_bankmachine3_cmd_buffer_source_last[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine3_cmd_buffer_source_last $1\main_sdram_bankmachine3_cmd_buffer_source_last[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:784.5-784.64" + process $proc$build/ls180/gateware/ls180.v:784$2858 + assign { } { } + assign $1\main_sdram_bankmachine3_cmd_buffer_source_payload_we[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine3_cmd_buffer_source_payload_we $1\main_sdram_bankmachine3_cmd_buffer_source_payload_we[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:785.12-785.74" + process $proc$build/ls180/gateware/ls180.v:785$2859 + assign { } { } + assign $1\main_sdram_bankmachine3_cmd_buffer_source_payload_addr[21:0] 22'0000000000000000000000 + sync always + sync init + update \main_sdram_bankmachine3_cmd_buffer_source_payload_addr $1\main_sdram_bankmachine3_cmd_buffer_source_payload_addr[21:0] + end + attribute \src "build/ls180/gateware/ls180.v:786.12-786.47" + process $proc$build/ls180/gateware/ls180.v:786$2860 + assign { } { } + assign $1\main_sdram_bankmachine3_row[12:0] 13'0000000000000 + sync always + sync init + update \main_sdram_bankmachine3_row $1\main_sdram_bankmachine3_row[12:0] + end + attribute \src "build/ls180/gateware/ls180.v:787.5-787.46" + process $proc$build/ls180/gateware/ls180.v:787$2861 + assign { } { } + assign $1\main_sdram_bankmachine3_row_opened[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine3_row_opened $1\main_sdram_bankmachine3_row_opened[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:789.5-789.44" + process $proc$build/ls180/gateware/ls180.v:789$2862 + assign { } { } + assign $1\main_sdram_bankmachine3_row_open[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine3_row_open $1\main_sdram_bankmachine3_row_open[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:79.12-79.60" + process $proc$build/ls180/gateware/ls180.v:79$2576 + assign { } { } + assign $0\main_libresocsim_libresoc_xics_ics_dat_r[31:0] 0 + sync always + update \main_libresocsim_libresoc_xics_ics_dat_r $0\main_libresocsim_libresoc_xics_ics_dat_r[31:0] + sync init + end + attribute \src "build/ls180/gateware/ls180.v:790.5-790.45" + process $proc$build/ls180/gateware/ls180.v:790$2863 + assign { } { } + assign $1\main_sdram_bankmachine3_row_close[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine3_row_close $1\main_sdram_bankmachine3_row_close[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:791.5-791.54" + process $proc$build/ls180/gateware/ls180.v:791$2864 + assign { } { } + assign $1\main_sdram_bankmachine3_row_col_n_addr_sel[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine3_row_col_n_addr_sel $1\main_sdram_bankmachine3_row_col_n_addr_sel[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:793.32-793.76" + process $proc$build/ls180/gateware/ls180.v:793$2865 + assign { } { } + assign $1\main_sdram_bankmachine3_twtpcon_ready[0:0] 1'0 + sync always + sync init + update \main_sdram_bankmachine3_twtpcon_ready $1\main_sdram_bankmachine3_twtpcon_ready[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:794.11-794.55" + process $proc$build/ls180/gateware/ls180.v:794$2866 + assign { } { } + assign $1\main_sdram_bankmachine3_twtpcon_count[2:0] 3'000 + sync always + sync init + update \main_sdram_bankmachine3_twtpcon_count $1\main_sdram_bankmachine3_twtpcon_count[2:0] + end + attribute \src "build/ls180/gateware/ls180.v:796.32-796.75" + process $proc$build/ls180/gateware/ls180.v:796$2867 + assign { } { } + assign $0\main_sdram_bankmachine3_trccon_ready[0:0] 1'1 + sync always + update \main_sdram_bankmachine3_trccon_ready $0\main_sdram_bankmachine3_trccon_ready[0:0] + sync init + end + attribute \src "build/ls180/gateware/ls180.v:798.32-798.76" + process $proc$build/ls180/gateware/ls180.v:798$2868 + assign { } { } + assign $0\main_sdram_bankmachine3_trascon_ready[0:0] 1'1 + sync always + update \main_sdram_bankmachine3_trascon_ready $0\main_sdram_bankmachine3_trascon_ready[0:0] + sync init + end + attribute \src "build/ls180/gateware/ls180.v:801.5-801.44" + process $proc$build/ls180/gateware/ls180.v:801$2869 + assign { } { } + assign $0\main_sdram_choose_cmd_want_reads[0:0] 1'0 + sync always + update \main_sdram_choose_cmd_want_reads $0\main_sdram_choose_cmd_want_reads[0:0] + sync init + end + attribute \src "build/ls180/gateware/ls180.v:802.5-802.45" + process $proc$build/ls180/gateware/ls180.v:802$2870 + assign { } { } + assign $0\main_sdram_choose_cmd_want_writes[0:0] 1'0 + sync always + update \main_sdram_choose_cmd_want_writes $0\main_sdram_choose_cmd_want_writes[0:0] + sync init + end + attribute \src "build/ls180/gateware/ls180.v:803.5-803.43" + process $proc$build/ls180/gateware/ls180.v:803$2871 + assign { } { } + assign $0\main_sdram_choose_cmd_want_cmds[0:0] 1'0 + sync always + update \main_sdram_choose_cmd_want_cmds $0\main_sdram_choose_cmd_want_cmds[0:0] + sync init + end + attribute \src "build/ls180/gateware/ls180.v:804.5-804.48" + process $proc$build/ls180/gateware/ls180.v:804$2872 + assign { } { } + assign $0\main_sdram_choose_cmd_want_activates[0:0] 1'0 + sync always + update \main_sdram_choose_cmd_want_activates $0\main_sdram_choose_cmd_want_activates[0:0] + sync init + end + attribute \src "build/ls180/gateware/ls180.v:806.5-806.43" + process $proc$build/ls180/gateware/ls180.v:806$2873 + assign { } { } + assign $0\main_sdram_choose_cmd_cmd_ready[0:0] 1'0 + sync always + update \main_sdram_choose_cmd_cmd_ready $0\main_sdram_choose_cmd_cmd_ready[0:0] + sync init + end + attribute \src "build/ls180/gateware/ls180.v:809.5-809.49" + process $proc$build/ls180/gateware/ls180.v:809$2874 + assign { } { } + assign $1\main_sdram_choose_cmd_cmd_payload_cas[0:0] 1'0 + sync always + sync init + update \main_sdram_choose_cmd_cmd_payload_cas $1\main_sdram_choose_cmd_cmd_payload_cas[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:810.5-810.49" + process $proc$build/ls180/gateware/ls180.v:810$2875 + assign { } { } + assign $1\main_sdram_choose_cmd_cmd_payload_ras[0:0] 1'0 + sync always + sync init + update \main_sdram_choose_cmd_cmd_payload_ras $1\main_sdram_choose_cmd_cmd_payload_ras[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:811.5-811.48" + process $proc$build/ls180/gateware/ls180.v:811$2876 + assign { } { } + assign $1\main_sdram_choose_cmd_cmd_payload_we[0:0] 1'0 + sync always + sync init + update \main_sdram_choose_cmd_cmd_payload_we $1\main_sdram_choose_cmd_cmd_payload_we[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:815.11-815.46" + process $proc$build/ls180/gateware/ls180.v:815$2877 + assign { } { } + assign $1\main_sdram_choose_cmd_valids[3:0] 4'0000 + sync always + sync init + update \main_sdram_choose_cmd_valids $1\main_sdram_choose_cmd_valids[3:0] + end + attribute \src "build/ls180/gateware/ls180.v:817.11-817.45" + process $proc$build/ls180/gateware/ls180.v:817$2878 + assign { } { } + assign $1\main_sdram_choose_cmd_grant[1:0] 2'00 + sync always + sync init + update \main_sdram_choose_cmd_grant $1\main_sdram_choose_cmd_grant[1:0] + end + attribute \src "build/ls180/gateware/ls180.v:819.5-819.44" + process $proc$build/ls180/gateware/ls180.v:819$2879 + assign { } { } + assign $1\main_sdram_choose_req_want_reads[0:0] 1'0 + sync always + sync init + update \main_sdram_choose_req_want_reads $1\main_sdram_choose_req_want_reads[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:820.5-820.45" + process $proc$build/ls180/gateware/ls180.v:820$2880 + assign { } { } + assign $1\main_sdram_choose_req_want_writes[0:0] 1'0 + sync always + sync init + update \main_sdram_choose_req_want_writes $1\main_sdram_choose_req_want_writes[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:822.5-822.48" + process $proc$build/ls180/gateware/ls180.v:822$2881 + assign { } { } + assign $1\main_sdram_choose_req_want_activates[0:0] 1'0 + sync always + sync init + update \main_sdram_choose_req_want_activates $1\main_sdram_choose_req_want_activates[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:824.5-824.43" + process $proc$build/ls180/gateware/ls180.v:824$2882 + assign { } { } + assign $1\main_sdram_choose_req_cmd_ready[0:0] 1'0 + sync always + sync init + update \main_sdram_choose_req_cmd_ready $1\main_sdram_choose_req_cmd_ready[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:827.5-827.49" + process $proc$build/ls180/gateware/ls180.v:827$2883 + assign { } { } + assign $1\main_sdram_choose_req_cmd_payload_cas[0:0] 1'0 + sync always + sync init + update \main_sdram_choose_req_cmd_payload_cas $1\main_sdram_choose_req_cmd_payload_cas[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:828.5-828.49" + process $proc$build/ls180/gateware/ls180.v:828$2884 + assign { } { } + assign $1\main_sdram_choose_req_cmd_payload_ras[0:0] 1'0 + sync always + sync init + update \main_sdram_choose_req_cmd_payload_ras $1\main_sdram_choose_req_cmd_payload_ras[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:829.5-829.48" + process $proc$build/ls180/gateware/ls180.v:829$2885 + assign { } { } + assign $1\main_sdram_choose_req_cmd_payload_we[0:0] 1'0 + sync always + sync init + update \main_sdram_choose_req_cmd_payload_we $1\main_sdram_choose_req_cmd_payload_we[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:83.5-83.50" + process $proc$build/ls180/gateware/ls180.v:83$2577 + assign { } { } + assign $0\main_libresocsim_libresoc_xics_ics_ack[0:0] 1'0 + sync always + update \main_libresocsim_libresoc_xics_ics_ack $0\main_libresocsim_libresoc_xics_ics_ack[0:0] + sync init + end + attribute \src "build/ls180/gateware/ls180.v:833.11-833.46" + process $proc$build/ls180/gateware/ls180.v:833$2886 + assign { } { } + assign $1\main_sdram_choose_req_valids[3:0] 4'0000 + sync always + sync init + update \main_sdram_choose_req_valids $1\main_sdram_choose_req_valids[3:0] + end + attribute \src "build/ls180/gateware/ls180.v:835.11-835.45" + process $proc$build/ls180/gateware/ls180.v:835$2887 + assign { } { } + assign $1\main_sdram_choose_req_grant[1:0] 2'00 + sync always + sync init + update \main_sdram_choose_req_grant $1\main_sdram_choose_req_grant[1:0] + end + attribute \src "build/ls180/gateware/ls180.v:837.12-837.36" + process $proc$build/ls180/gateware/ls180.v:837$2888 + assign { } { } + assign $0\main_sdram_nop_a[12:0] 13'0000000000000 + sync always + update \main_sdram_nop_a $0\main_sdram_nop_a[12:0] + sync init + end + attribute \src "build/ls180/gateware/ls180.v:838.11-838.35" + process $proc$build/ls180/gateware/ls180.v:838$2889 + assign { } { } + assign $0\main_sdram_nop_ba[1:0] 2'00 + sync always + update \main_sdram_nop_ba $0\main_sdram_nop_ba[1:0] + sync init + end + attribute \src "build/ls180/gateware/ls180.v:839.11-839.40" + process $proc$build/ls180/gateware/ls180.v:839$2890 + assign { } { } + assign $1\main_sdram_steerer_sel[1:0] 2'00 + sync always + sync init + update \main_sdram_steerer_sel $1\main_sdram_steerer_sel[1:0] + end + attribute \src "build/ls180/gateware/ls180.v:840.5-840.31" + process $proc$build/ls180/gateware/ls180.v:840$2891 + assign { } { } + assign $0\main_sdram_steerer0[0:0] 1'1 + sync always + update \main_sdram_steerer0 $0\main_sdram_steerer0[0:0] + sync init + end + attribute \src "build/ls180/gateware/ls180.v:841.5-841.31" + process $proc$build/ls180/gateware/ls180.v:841$2892 + assign { } { } + assign $0\main_sdram_steerer1[0:0] 1'1 + sync always + update \main_sdram_steerer1 $0\main_sdram_steerer1[0:0] + sync init + end + attribute \src "build/ls180/gateware/ls180.v:843.32-843.63" + process $proc$build/ls180/gateware/ls180.v:843$2893 + assign { } { } + assign $0\main_sdram_trrdcon_ready[0:0] 1'1 + sync always + update \main_sdram_trrdcon_ready $0\main_sdram_trrdcon_ready[0:0] + sync init + end + attribute \src "build/ls180/gateware/ls180.v:845.32-845.63" + process $proc$build/ls180/gateware/ls180.v:845$2894 + assign { } { } + assign $0\main_sdram_tfawcon_ready[0:0] 1'1 + sync always + update \main_sdram_tfawcon_ready $0\main_sdram_tfawcon_ready[0:0] + sync init + end + attribute \src "build/ls180/gateware/ls180.v:847.32-847.63" + process $proc$build/ls180/gateware/ls180.v:847$2895 + assign { } { } + assign $1\main_sdram_tccdcon_ready[0:0] 1'0 + sync always + sync init + update \main_sdram_tccdcon_ready $1\main_sdram_tccdcon_ready[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:848.5-848.36" + process $proc$build/ls180/gateware/ls180.v:848$2896 + assign { } { } + assign $1\main_sdram_tccdcon_count[0:0] 1'0 + sync always + sync init + update \main_sdram_tccdcon_count $1\main_sdram_tccdcon_count[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:850.32-850.63" + process $proc$build/ls180/gateware/ls180.v:850$2897 + assign { } { } + assign $1\main_sdram_twtrcon_ready[0:0] 1'0 + sync always + sync init + update \main_sdram_twtrcon_ready $1\main_sdram_twtrcon_ready[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:851.11-851.42" + process $proc$build/ls180/gateware/ls180.v:851$2898 + assign { } { } + assign $1\main_sdram_twtrcon_count[2:0] 3'000 + sync always + sync init + update \main_sdram_twtrcon_count $1\main_sdram_twtrcon_count[2:0] + end + attribute \src "build/ls180/gateware/ls180.v:854.5-854.26" + process $proc$build/ls180/gateware/ls180.v:854$2899 + assign { } { } + assign $1\main_sdram_en0[0:0] 1'0 + sync always + sync init + update \main_sdram_en0 $1\main_sdram_en0[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:856.11-856.34" + process $proc$build/ls180/gateware/ls180.v:856$2900 + assign { } { } + assign $1\main_sdram_time0[4:0] 5'00000 + sync always + sync init + update \main_sdram_time0 $1\main_sdram_time0[4:0] + end + attribute \src "build/ls180/gateware/ls180.v:857.5-857.26" + process $proc$build/ls180/gateware/ls180.v:857$2901 + assign { } { } + assign $1\main_sdram_en1[0:0] 1'0 + sync always + sync init + update \main_sdram_en1 $1\main_sdram_en1[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:859.11-859.34" + process $proc$build/ls180/gateware/ls180.v:859$2902 + assign { } { } + assign $1\main_sdram_time1[3:0] 4'0000 + sync always + sync init + update \main_sdram_time1 $1\main_sdram_time1[3:0] + end + attribute \src "build/ls180/gateware/ls180.v:87.5-87.50" + process $proc$build/ls180/gateware/ls180.v:87$2578 + assign { } { } + assign $0\main_libresocsim_libresoc_xics_ics_err[0:0] 1'0 + sync always + update \main_libresocsim_libresoc_xics_ics_err $0\main_libresocsim_libresoc_xics_ics_err[0:0] + sync init + end + attribute \src "build/ls180/gateware/ls180.v:88.11-88.52" + process $proc$build/ls180/gateware/ls180.v:88$2579 + assign { } { } + assign $0\main_libresocsim_libresoc_dmi_addr[3:0] 4'0000 + sync always + update \main_libresocsim_libresoc_dmi_addr $0\main_libresocsim_libresoc_dmi_addr[3:0] + sync init + end + attribute \src "build/ls180/gateware/ls180.v:880.5-880.29" + process $proc$build/ls180/gateware/ls180.v:880$2903 + assign { } { } + assign $1\main_wb_sdram_ack[0:0] 1'0 + sync always + sync init + update \main_wb_sdram_ack $1\main_wb_sdram_ack[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:884.5-884.29" + process $proc$build/ls180/gateware/ls180.v:884$2904 + assign { } { } + assign $0\main_wb_sdram_err[0:0] 1'0 + sync always + update \main_wb_sdram_err $0\main_wb_sdram_err[0:0] + sync init + end + attribute \src "build/ls180/gateware/ls180.v:885.12-885.40" + process $proc$build/ls180/gateware/ls180.v:885$2905 + assign { } { } + assign $1\main_litedram_wb_adr[29:0] 30'000000000000000000000000000000 + sync always + sync init + update \main_litedram_wb_adr $1\main_litedram_wb_adr[29:0] + end + attribute \src "build/ls180/gateware/ls180.v:886.12-886.42" + process $proc$build/ls180/gateware/ls180.v:886$2906 + assign { } { } + assign $1\main_litedram_wb_dat_w[15:0] 16'0000000000000000 + sync always + sync init + update \main_litedram_wb_dat_w $1\main_litedram_wb_dat_w[15:0] + end + attribute \src "build/ls180/gateware/ls180.v:888.11-888.38" + process $proc$build/ls180/gateware/ls180.v:888$2907 + assign { } { } + assign $1\main_litedram_wb_sel[1:0] 2'00 + sync always + sync init + update \main_litedram_wb_sel $1\main_litedram_wb_sel[1:0] + end + attribute \src "build/ls180/gateware/ls180.v:889.5-889.32" + process $proc$build/ls180/gateware/ls180.v:889$2908 + assign { } { } + assign $1\main_litedram_wb_cyc[0:0] 1'0 + sync always + sync init + update \main_litedram_wb_cyc $1\main_litedram_wb_cyc[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:89.12-89.53" + process $proc$build/ls180/gateware/ls180.v:89$2580 + assign { } { } + assign $0\main_libresocsim_libresoc_dmi_din[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + update \main_libresocsim_libresoc_dmi_din $0\main_libresocsim_libresoc_dmi_din[63:0] + sync init + end + attribute \src "build/ls180/gateware/ls180.v:890.5-890.32" + process $proc$build/ls180/gateware/ls180.v:890$2909 + assign { } { } + assign $1\main_litedram_wb_stb[0:0] 1'0 + sync always + sync init + update \main_litedram_wb_stb $1\main_litedram_wb_stb[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:892.5-892.31" + process $proc$build/ls180/gateware/ls180.v:892$2910 + assign { } { } + assign $1\main_litedram_wb_we[0:0] 1'0 + sync always + sync init + update \main_litedram_wb_we $1\main_litedram_wb_we[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:893.5-893.31" + process $proc$build/ls180/gateware/ls180.v:893$2911 + assign { } { } + assign $1\main_converter_skip[0:0] 1'0 + sync always + sync init + update \main_converter_skip $1\main_converter_skip[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:894.5-894.34" + process $proc$build/ls180/gateware/ls180.v:894$2912 + assign { } { } + assign $1\main_converter_counter[0:0] 1'0 + sync always + sync init + update \main_converter_counter $1\main_converter_counter[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:896.12-896.40" + process $proc$build/ls180/gateware/ls180.v:896$2913 + assign { } { } + assign $1\main_converter_dat_r[31:0] 0 + sync always + sync init + update \main_converter_dat_r $1\main_converter_dat_r[31:0] + end + attribute \src "build/ls180/gateware/ls180.v:897.5-897.29" + process $proc$build/ls180/gateware/ls180.v:897$2914 + assign { } { } + assign $1\main_cmd_consumed[0:0] 1'0 + sync always + sync init + update \main_cmd_consumed $1\main_cmd_consumed[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:898.5-898.31" + process $proc$build/ls180/gateware/ls180.v:898$2915 + assign { } { } + assign $1\main_wdata_consumed[0:0] 1'0 + sync always + sync init + update \main_wdata_consumed $1\main_wdata_consumed[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:908.5-908.22" + process $proc$build/ls180/gateware/ls180.v:908$2916 + assign { } { } + assign $1\main_done0[0:0] 1'0 + sync always + sync init + update \main_done0 $1\main_done0[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:909.5-909.20" + process $proc$build/ls180/gateware/ls180.v:909$2917 + assign { } { } + assign $1\main_irq[0:0] 1'0 + sync always + sync init + update \main_irq $1\main_irq[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:91.5-91.44" + process $proc$build/ls180/gateware/ls180.v:91$2581 + assign { } { } + assign $0\main_libresocsim_libresoc_dmi_wr[0:0] 1'0 + sync always + update \main_libresocsim_libresoc_dmi_wr $0\main_libresocsim_libresoc_dmi_wr[0:0] + sync init + end + attribute \src "build/ls180/gateware/ls180.v:911.11-911.27" + process $proc$build/ls180/gateware/ls180.v:911$2918 + assign { } { } + assign $1\main_miso[7:0] 8'00000000 + sync always + sync init + update \main_miso $1\main_miso[7:0] + end + attribute \src "build/ls180/gateware/ls180.v:914.12-914.37" + process $proc$build/ls180/gateware/ls180.v:914$2919 + assign { } { } + assign $0\main_clk_divider0[15:0] 16'0000000000000111 + sync always + update \main_clk_divider0 $0\main_clk_divider0[15:0] + sync init + end + attribute \src "build/ls180/gateware/ls180.v:915.5-915.23" + process $proc$build/ls180/gateware/ls180.v:915$2920 + assign { } { } + assign $1\main_start1[0:0] 1'0 + sync always + sync init + update \main_start1 $1\main_start1[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:917.12-917.40" + process $proc$build/ls180/gateware/ls180.v:917$2921 + assign { } { } + assign $1\main_control_storage[15:0] 16'0000000000000000 + sync always + sync init + update \main_control_storage $1\main_control_storage[15:0] + end + attribute \src "build/ls180/gateware/ls180.v:918.5-918.27" + process $proc$build/ls180/gateware/ls180.v:918$2922 + assign { } { } + assign $1\main_control_re[0:0] 1'0 + sync always + sync init + update \main_control_re $1\main_control_re[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:922.11-922.35" + process $proc$build/ls180/gateware/ls180.v:922$2923 + assign { } { } + assign $1\main_mosi_storage[7:0] 8'00000000 + sync always + sync init + update \main_mosi_storage $1\main_mosi_storage[7:0] + end + attribute \src "build/ls180/gateware/ls180.v:923.5-923.24" + process $proc$build/ls180/gateware/ls180.v:923$2924 + assign { } { } + assign $1\main_mosi_re[0:0] 1'0 + sync always + sync init + update \main_mosi_re $1\main_mosi_re[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:927.5-927.27" + process $proc$build/ls180/gateware/ls180.v:927$2925 + assign { } { } + assign $1\main_cs_storage[0:0] 1'1 + sync always + sync init + update \main_cs_storage $1\main_cs_storage[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:928.5-928.22" + process $proc$build/ls180/gateware/ls180.v:928$2926 + assign { } { } + assign $1\main_cs_re[0:0] 1'0 + sync always + sync init + update \main_cs_re $1\main_cs_re[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:929.5-929.33" + process $proc$build/ls180/gateware/ls180.v:929$2927 + assign { } { } + assign $1\main_loopback_storage[0:0] 1'0 + sync always + sync init + update \main_loopback_storage $1\main_loopback_storage[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:93.5-93.45" + process $proc$build/ls180/gateware/ls180.v:93$2582 + assign { } { } + assign $0\main_libresocsim_libresoc_dmi_req[0:0] 1'0 + sync always + update \main_libresocsim_libresoc_dmi_req $0\main_libresocsim_libresoc_dmi_req[0:0] + sync init + end + attribute \src "build/ls180/gateware/ls180.v:930.5-930.28" + process $proc$build/ls180/gateware/ls180.v:930$2928 + assign { } { } + assign $1\main_loopback_re[0:0] 1'0 + sync always + sync init + update \main_loopback_re $1\main_loopback_re[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:931.5-931.27" + process $proc$build/ls180/gateware/ls180.v:931$2929 + assign { } { } + assign $1\main_clk_enable[0:0] 1'0 + sync always + sync init + update \main_clk_enable $1\main_clk_enable[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:932.5-932.26" + process $proc$build/ls180/gateware/ls180.v:932$2930 + assign { } { } + assign $1\main_cs_enable[0:0] 1'0 + sync always + sync init + update \main_cs_enable $1\main_cs_enable[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:933.11-933.28" + process $proc$build/ls180/gateware/ls180.v:933$2931 + assign { } { } + assign $1\main_count[2:0] 3'000 + sync always + sync init + update \main_count $1\main_count[2:0] + end + attribute \src "build/ls180/gateware/ls180.v:934.5-934.27" + process $proc$build/ls180/gateware/ls180.v:934$2932 + assign { } { } + assign $1\main_mosi_latch[0:0] 1'0 + sync always + sync init + update \main_mosi_latch $1\main_mosi_latch[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:935.5-935.27" + process $proc$build/ls180/gateware/ls180.v:935$2933 + assign { } { } + assign $1\main_miso_latch[0:0] 1'0 + sync always + sync init + update \main_miso_latch $1\main_miso_latch[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:936.12-936.37" + process $proc$build/ls180/gateware/ls180.v:936$2934 + assign { } { } + assign $1\main_clk_divider1[15:0] 16'0000000000000000 + sync always + sync init + update \main_clk_divider1 $1\main_clk_divider1[15:0] + end + attribute \src "build/ls180/gateware/ls180.v:9367.1-9377.4" + process $proc$build/ls180/gateware/ls180.v:9367$2459 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0$memwr$\mem$build/ls180/gateware/ls180.v:9375$4_ADDR[15:0]$2469 16'xxxxxxxxxxxxxxxx + assign $0$memwr$\mem$build/ls180/gateware/ls180.v:9375$4_DATA[31:0]$2470 32'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\mem$build/ls180/gateware/ls180.v:9375$4_EN[31:0]$2471 0 + assign $0$memwr$\mem$build/ls180/gateware/ls180.v:9373$3_ADDR[15:0]$2466 16'xxxxxxxxxxxxxxxx + assign $0$memwr$\mem$build/ls180/gateware/ls180.v:9373$3_DATA[31:0]$2467 32'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\mem$build/ls180/gateware/ls180.v:9373$3_EN[31:0]$2468 0 + assign $0$memwr$\mem$build/ls180/gateware/ls180.v:9371$2_ADDR[15:0]$2463 16'xxxxxxxxxxxxxxxx + assign $0$memwr$\mem$build/ls180/gateware/ls180.v:9371$2_DATA[31:0]$2464 32'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\mem$build/ls180/gateware/ls180.v:9371$2_EN[31:0]$2465 0 + assign $0$memwr$\mem$build/ls180/gateware/ls180.v:9369$1_ADDR[15:0]$2460 16'xxxxxxxxxxxxxxxx + assign $0$memwr$\mem$build/ls180/gateware/ls180.v:9369$1_DATA[31:0]$2461 32'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\mem$build/ls180/gateware/ls180.v:9369$1_EN[31:0]$2462 0 + assign $0\memadr[15:0] \main_libresocsim_adr + attribute \src "build/ls180/gateware/ls180.v:9368.2-9369.65" + switch \main_libresocsim_we [0] + attribute \src "build/ls180/gateware/ls180.v:9368.6-9368.28" + case 1'1 + assign $0$memwr$\mem$build/ls180/gateware/ls180.v:9369$1_ADDR[15:0]$2460 \main_libresocsim_adr + assign $0$memwr$\mem$build/ls180/gateware/ls180.v:9369$1_DATA[31:0]$2461 { 24'000000000000000000000000 \main_libresocsim_dat_w [7:0] } + assign $0$memwr$\mem$build/ls180/gateware/ls180.v:9369$1_EN[31:0]$2462 255 + case + end + attribute \src "build/ls180/gateware/ls180.v:9370.2-9371.67" + switch \main_libresocsim_we [1] + attribute \src "build/ls180/gateware/ls180.v:9370.6-9370.28" + case 1'1 + assign $0$memwr$\mem$build/ls180/gateware/ls180.v:9371$2_ADDR[15:0]$2463 \main_libresocsim_adr + assign $0$memwr$\mem$build/ls180/gateware/ls180.v:9371$2_DATA[31:0]$2464 { 16'0000000000000000 \main_libresocsim_dat_w [15:8] 8'xxxxxxxx } + assign $0$memwr$\mem$build/ls180/gateware/ls180.v:9371$2_EN[31:0]$2465 65280 + case + end + attribute \src "build/ls180/gateware/ls180.v:9372.2-9373.69" + switch \main_libresocsim_we [2] + attribute \src "build/ls180/gateware/ls180.v:9372.6-9372.28" + case 1'1 + assign $0$memwr$\mem$build/ls180/gateware/ls180.v:9373$3_ADDR[15:0]$2466 \main_libresocsim_adr + assign $0$memwr$\mem$build/ls180/gateware/ls180.v:9373$3_DATA[31:0]$2467 { 8'00000000 \main_libresocsim_dat_w [23:16] 16'xxxxxxxxxxxxxxxx } + assign $0$memwr$\mem$build/ls180/gateware/ls180.v:9373$3_EN[31:0]$2468 16711680 + case + end + attribute \src "build/ls180/gateware/ls180.v:9374.2-9375.69" + switch \main_libresocsim_we [3] + attribute \src "build/ls180/gateware/ls180.v:9374.6-9374.28" + case 1'1 + assign $0$memwr$\mem$build/ls180/gateware/ls180.v:9375$4_ADDR[15:0]$2469 \main_libresocsim_adr + assign $0$memwr$\mem$build/ls180/gateware/ls180.v:9375$4_DATA[31:0]$2470 { \main_libresocsim_dat_w [31:24] 24'xxxxxxxxxxxxxxxxxxxxxxxx } + assign $0$memwr$\mem$build/ls180/gateware/ls180.v:9375$4_EN[31:0]$2471 32'11111111000000000000000000000000 + case + end + sync posedge \sys_clk_1 + update \memadr $0\memadr[15:0] + update $memwr$\mem$build/ls180/gateware/ls180.v:9369$1_ADDR $0$memwr$\mem$build/ls180/gateware/ls180.v:9369$1_ADDR[15:0]$2460 + update $memwr$\mem$build/ls180/gateware/ls180.v:9369$1_DATA $0$memwr$\mem$build/ls180/gateware/ls180.v:9369$1_DATA[31:0]$2461 + update $memwr$\mem$build/ls180/gateware/ls180.v:9369$1_EN $0$memwr$\mem$build/ls180/gateware/ls180.v:9369$1_EN[31:0]$2462 + update $memwr$\mem$build/ls180/gateware/ls180.v:9371$2_ADDR $0$memwr$\mem$build/ls180/gateware/ls180.v:9371$2_ADDR[15:0]$2463 + update $memwr$\mem$build/ls180/gateware/ls180.v:9371$2_DATA $0$memwr$\mem$build/ls180/gateware/ls180.v:9371$2_DATA[31:0]$2464 + update $memwr$\mem$build/ls180/gateware/ls180.v:9371$2_EN $0$memwr$\mem$build/ls180/gateware/ls180.v:9371$2_EN[31:0]$2465 + update $memwr$\mem$build/ls180/gateware/ls180.v:9373$3_ADDR $0$memwr$\mem$build/ls180/gateware/ls180.v:9373$3_ADDR[15:0]$2466 + update $memwr$\mem$build/ls180/gateware/ls180.v:9373$3_DATA $0$memwr$\mem$build/ls180/gateware/ls180.v:9373$3_DATA[31:0]$2467 + update $memwr$\mem$build/ls180/gateware/ls180.v:9373$3_EN $0$memwr$\mem$build/ls180/gateware/ls180.v:9373$3_EN[31:0]$2468 + update $memwr$\mem$build/ls180/gateware/ls180.v:9375$4_ADDR $0$memwr$\mem$build/ls180/gateware/ls180.v:9375$4_ADDR[15:0]$2469 + update $memwr$\mem$build/ls180/gateware/ls180.v:9375$4_DATA $0$memwr$\mem$build/ls180/gateware/ls180.v:9375$4_DATA[31:0]$2470 + update $memwr$\mem$build/ls180/gateware/ls180.v:9375$4_EN $0$memwr$\mem$build/ls180/gateware/ls180.v:9375$4_EN[31:0]$2471 + end + attribute \src "build/ls180/gateware/ls180.v:9388.1-9392.4" + process $proc$build/ls180/gateware/ls180.v:9388$2473 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0$memwr$\storage$build/ls180/gateware/ls180.v:9390$5_ADDR[3:0]$2474 4'xxxx + assign $0$memwr$\storage$build/ls180/gateware/ls180.v:9390$5_DATA[9:0]$2475 10'xxxxxxxxxx + assign $0$memwr$\storage$build/ls180/gateware/ls180.v:9390$5_EN[9:0]$2476 10'0000000000 + assign $0\memdat[9:0] $memrd$\storage$build/ls180/gateware/ls180.v:9391$2477_DATA + attribute \src "build/ls180/gateware/ls180.v:9389.2-9390.99" + switch \main_libresocsim_uart_tx_fifo_wrport_we + attribute \src "build/ls180/gateware/ls180.v:9389.6-9389.45" + case 1'1 + assign $0$memwr$\storage$build/ls180/gateware/ls180.v:9390$5_ADDR[3:0]$2474 \main_libresocsim_uart_tx_fifo_wrport_adr + assign $0$memwr$\storage$build/ls180/gateware/ls180.v:9390$5_DATA[9:0]$2475 \main_libresocsim_uart_tx_fifo_wrport_dat_w + assign $0$memwr$\storage$build/ls180/gateware/ls180.v:9390$5_EN[9:0]$2476 10'1111111111 + case + end + sync posedge \sys_clk_1 + update \memdat $0\memdat[9:0] + update $memwr$\storage$build/ls180/gateware/ls180.v:9390$5_ADDR $0$memwr$\storage$build/ls180/gateware/ls180.v:9390$5_ADDR[3:0]$2474 + update $memwr$\storage$build/ls180/gateware/ls180.v:9390$5_DATA $0$memwr$\storage$build/ls180/gateware/ls180.v:9390$5_DATA[9:0]$2475 + update $memwr$\storage$build/ls180/gateware/ls180.v:9390$5_EN $0$memwr$\storage$build/ls180/gateware/ls180.v:9390$5_EN[9:0]$2476 + end + attribute \src "build/ls180/gateware/ls180.v:939.11-939.32" + process $proc$build/ls180/gateware/ls180.v:939$2935 + assign { } { } + assign $1\main_mosi_data[7:0] 8'00000000 + sync always + sync init + update \main_mosi_data $1\main_mosi_data[7:0] + end + attribute \src "build/ls180/gateware/ls180.v:9394.1-9397.4" + process $proc$build/ls180/gateware/ls180.v:9394$2478 + assign $0\memdat_1[9:0] \memdat_1 + attribute \src "build/ls180/gateware/ls180.v:9395.2-9396.65" + switch \main_libresocsim_uart_tx_fifo_rdport_re + attribute \src "build/ls180/gateware/ls180.v:9395.6-9395.45" + case 1'1 + assign $0\memdat_1[9:0] $memrd$\storage$build/ls180/gateware/ls180.v:9396$2479_DATA + case + end + sync posedge \sys_clk_1 + update \memdat_1 $0\memdat_1[9:0] + end + attribute \src "build/ls180/gateware/ls180.v:940.11-940.31" + process $proc$build/ls180/gateware/ls180.v:940$2936 + assign { } { } + assign $1\main_mosi_sel[2:0] 3'000 + sync always + sync init + update \main_mosi_sel $1\main_mosi_sel[2:0] + end + attribute \src "build/ls180/gateware/ls180.v:9405.1-9409.4" + process $proc$build/ls180/gateware/ls180.v:9405$2480 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0$memwr$\storage_1$build/ls180/gateware/ls180.v:9407$6_ADDR[3:0]$2481 4'xxxx + assign $0$memwr$\storage_1$build/ls180/gateware/ls180.v:9407$6_DATA[9:0]$2482 10'xxxxxxxxxx + assign $0$memwr$\storage_1$build/ls180/gateware/ls180.v:9407$6_EN[9:0]$2483 10'0000000000 + assign $0\memdat_2[9:0] $memrd$\storage_1$build/ls180/gateware/ls180.v:9408$2484_DATA + attribute \src "build/ls180/gateware/ls180.v:9406.2-9407.101" + switch \main_libresocsim_uart_rx_fifo_wrport_we + attribute \src "build/ls180/gateware/ls180.v:9406.6-9406.45" + case 1'1 + assign $0$memwr$\storage_1$build/ls180/gateware/ls180.v:9407$6_ADDR[3:0]$2481 \main_libresocsim_uart_rx_fifo_wrport_adr + assign $0$memwr$\storage_1$build/ls180/gateware/ls180.v:9407$6_DATA[9:0]$2482 \main_libresocsim_uart_rx_fifo_wrport_dat_w + assign $0$memwr$\storage_1$build/ls180/gateware/ls180.v:9407$6_EN[9:0]$2483 10'1111111111 + case + end + sync posedge \sys_clk_1 + update \memdat_2 $0\memdat_2[9:0] + update $memwr$\storage_1$build/ls180/gateware/ls180.v:9407$6_ADDR $0$memwr$\storage_1$build/ls180/gateware/ls180.v:9407$6_ADDR[3:0]$2481 + update $memwr$\storage_1$build/ls180/gateware/ls180.v:9407$6_DATA $0$memwr$\storage_1$build/ls180/gateware/ls180.v:9407$6_DATA[9:0]$2482 + update $memwr$\storage_1$build/ls180/gateware/ls180.v:9407$6_EN $0$memwr$\storage_1$build/ls180/gateware/ls180.v:9407$6_EN[9:0]$2483 + end + attribute \src "build/ls180/gateware/ls180.v:941.11-941.32" + process $proc$build/ls180/gateware/ls180.v:941$2937 + assign { } { } + assign $1\main_miso_data[7:0] 8'00000000 + sync always + sync init + update \main_miso_data $1\main_miso_data[7:0] + end + attribute \src "build/ls180/gateware/ls180.v:9411.1-9414.4" + process $proc$build/ls180/gateware/ls180.v:9411$2485 + assign $0\memdat_3[9:0] \memdat_3 + attribute \src "build/ls180/gateware/ls180.v:9412.2-9413.67" + switch \main_libresocsim_uart_rx_fifo_rdport_re + attribute \src "build/ls180/gateware/ls180.v:9412.6-9412.45" + case 1'1 + assign $0\memdat_3[9:0] $memrd$\storage_1$build/ls180/gateware/ls180.v:9413$2486_DATA + case + end + sync posedge \sys_clk_1 + update \memdat_3 $0\memdat_3[9:0] + end + attribute \src "build/ls180/gateware/ls180.v:9421.1-9425.4" + process $proc$build/ls180/gateware/ls180.v:9421$2487 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0$memwr$\storage_2$build/ls180/gateware/ls180.v:9423$7_ADDR[2:0]$2488 3'xxx + assign $0$memwr$\storage_2$build/ls180/gateware/ls180.v:9423$7_DATA[24:0]$2489 25'xxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\storage_2$build/ls180/gateware/ls180.v:9423$7_EN[24:0]$2490 25'0000000000000000000000000 + assign $0\memdat_4[24:0] $memrd$\storage_2$build/ls180/gateware/ls180.v:9424$2491_DATA + attribute \src "build/ls180/gateware/ls180.v:9422.2-9423.131" + switch \main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_we + attribute \src "build/ls180/gateware/ls180.v:9422.6-9422.60" + case 1'1 + assign $0$memwr$\storage_2$build/ls180/gateware/ls180.v:9423$7_ADDR[2:0]$2488 \main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_adr + assign $0$memwr$\storage_2$build/ls180/gateware/ls180.v:9423$7_DATA[24:0]$2489 \main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_dat_w + assign $0$memwr$\storage_2$build/ls180/gateware/ls180.v:9423$7_EN[24:0]$2490 25'1111111111111111111111111 + case + end + sync posedge \sys_clk_1 + update \memdat_4 $0\memdat_4[24:0] + update $memwr$\storage_2$build/ls180/gateware/ls180.v:9423$7_ADDR $0$memwr$\storage_2$build/ls180/gateware/ls180.v:9423$7_ADDR[2:0]$2488 + update $memwr$\storage_2$build/ls180/gateware/ls180.v:9423$7_DATA $0$memwr$\storage_2$build/ls180/gateware/ls180.v:9423$7_DATA[24:0]$2489 + update $memwr$\storage_2$build/ls180/gateware/ls180.v:9423$7_EN $0$memwr$\storage_2$build/ls180/gateware/ls180.v:9423$7_EN[24:0]$2490 + end + attribute \src "build/ls180/gateware/ls180.v:9427.1-9428.4" + process $proc$build/ls180/gateware/ls180.v:9427$2492 + sync posedge \sys_clk_1 + end + attribute \src "build/ls180/gateware/ls180.v:9435.1-9439.4" + process $proc$build/ls180/gateware/ls180.v:9435$2494 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0$memwr$\storage_3$build/ls180/gateware/ls180.v:9437$8_ADDR[2:0]$2495 3'xxx + assign $0$memwr$\storage_3$build/ls180/gateware/ls180.v:9437$8_DATA[24:0]$2496 25'xxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\storage_3$build/ls180/gateware/ls180.v:9437$8_EN[24:0]$2497 25'0000000000000000000000000 + assign $0\memdat_5[24:0] $memrd$\storage_3$build/ls180/gateware/ls180.v:9438$2498_DATA + attribute \src "build/ls180/gateware/ls180.v:9436.2-9437.131" + switch \main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_we + attribute \src "build/ls180/gateware/ls180.v:9436.6-9436.60" + case 1'1 + assign $0$memwr$\storage_3$build/ls180/gateware/ls180.v:9437$8_ADDR[2:0]$2495 \main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_adr + assign $0$memwr$\storage_3$build/ls180/gateware/ls180.v:9437$8_DATA[24:0]$2496 \main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_dat_w + assign $0$memwr$\storage_3$build/ls180/gateware/ls180.v:9437$8_EN[24:0]$2497 25'1111111111111111111111111 + case + end + sync posedge \sys_clk_1 + update \memdat_5 $0\memdat_5[24:0] + update $memwr$\storage_3$build/ls180/gateware/ls180.v:9437$8_ADDR $0$memwr$\storage_3$build/ls180/gateware/ls180.v:9437$8_ADDR[2:0]$2495 + update $memwr$\storage_3$build/ls180/gateware/ls180.v:9437$8_DATA $0$memwr$\storage_3$build/ls180/gateware/ls180.v:9437$8_DATA[24:0]$2496 + update $memwr$\storage_3$build/ls180/gateware/ls180.v:9437$8_EN $0$memwr$\storage_3$build/ls180/gateware/ls180.v:9437$8_EN[24:0]$2497 + end + attribute \src "build/ls180/gateware/ls180.v:944.11-944.47" + process $proc$build/ls180/gateware/ls180.v:944$2938 + assign { } { } + assign $1\libresocsim_clocker_storage[8:0] 9'100000000 + sync always + sync init + update \libresocsim_clocker_storage $1\libresocsim_clocker_storage[8:0] + end + attribute \src "build/ls180/gateware/ls180.v:9441.1-9442.4" + process $proc$build/ls180/gateware/ls180.v:9441$2499 + sync posedge \sys_clk_1 + end + attribute \src "build/ls180/gateware/ls180.v:9449.1-9453.4" + process $proc$build/ls180/gateware/ls180.v:9449$2501 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0$memwr$\storage_4$build/ls180/gateware/ls180.v:9451$9_ADDR[2:0]$2502 3'xxx + assign $0$memwr$\storage_4$build/ls180/gateware/ls180.v:9451$9_DATA[24:0]$2503 25'xxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\storage_4$build/ls180/gateware/ls180.v:9451$9_EN[24:0]$2504 25'0000000000000000000000000 + assign $0\memdat_6[24:0] $memrd$\storage_4$build/ls180/gateware/ls180.v:9452$2505_DATA + attribute \src "build/ls180/gateware/ls180.v:9450.2-9451.131" + switch \main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_we + attribute \src "build/ls180/gateware/ls180.v:9450.6-9450.60" + case 1'1 + assign $0$memwr$\storage_4$build/ls180/gateware/ls180.v:9451$9_ADDR[2:0]$2502 \main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_adr + assign $0$memwr$\storage_4$build/ls180/gateware/ls180.v:9451$9_DATA[24:0]$2503 \main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_dat_w + assign $0$memwr$\storage_4$build/ls180/gateware/ls180.v:9451$9_EN[24:0]$2504 25'1111111111111111111111111 + case + end + sync posedge \sys_clk_1 + update \memdat_6 $0\memdat_6[24:0] + update $memwr$\storage_4$build/ls180/gateware/ls180.v:9451$9_ADDR $0$memwr$\storage_4$build/ls180/gateware/ls180.v:9451$9_ADDR[2:0]$2502 + update $memwr$\storage_4$build/ls180/gateware/ls180.v:9451$9_DATA $0$memwr$\storage_4$build/ls180/gateware/ls180.v:9451$9_DATA[24:0]$2503 + update $memwr$\storage_4$build/ls180/gateware/ls180.v:9451$9_EN $0$memwr$\storage_4$build/ls180/gateware/ls180.v:9451$9_EN[24:0]$2504 + end + attribute \src "build/ls180/gateware/ls180.v:945.5-945.34" + process $proc$build/ls180/gateware/ls180.v:945$2939 + assign { } { } + assign $1\libresocsim_clocker_re[0:0] 1'0 + sync always + sync init + update \libresocsim_clocker_re $1\libresocsim_clocker_re[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:9455.1-9456.4" + process $proc$build/ls180/gateware/ls180.v:9455$2506 + sync posedge \sys_clk_1 + end + attribute \src "build/ls180/gateware/ls180.v:9463.1-9467.4" + process $proc$build/ls180/gateware/ls180.v:9463$2508 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0$memwr$\storage_5$build/ls180/gateware/ls180.v:9465$10_ADDR[2:0]$2509 3'xxx + assign $0$memwr$\storage_5$build/ls180/gateware/ls180.v:9465$10_DATA[24:0]$2510 25'xxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\storage_5$build/ls180/gateware/ls180.v:9465$10_EN[24:0]$2511 25'0000000000000000000000000 + assign $0\memdat_7[24:0] $memrd$\storage_5$build/ls180/gateware/ls180.v:9466$2512_DATA + attribute \src "build/ls180/gateware/ls180.v:9464.2-9465.131" + switch \main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_we + attribute \src "build/ls180/gateware/ls180.v:9464.6-9464.60" + case 1'1 + assign $0$memwr$\storage_5$build/ls180/gateware/ls180.v:9465$10_ADDR[2:0]$2509 \main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_adr + assign $0$memwr$\storage_5$build/ls180/gateware/ls180.v:9465$10_DATA[24:0]$2510 \main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_dat_w + assign $0$memwr$\storage_5$build/ls180/gateware/ls180.v:9465$10_EN[24:0]$2511 25'1111111111111111111111111 + case + end + sync posedge \sys_clk_1 + update \memdat_7 $0\memdat_7[24:0] + update $memwr$\storage_5$build/ls180/gateware/ls180.v:9465$10_ADDR $0$memwr$\storage_5$build/ls180/gateware/ls180.v:9465$10_ADDR[2:0]$2509 + update $memwr$\storage_5$build/ls180/gateware/ls180.v:9465$10_DATA $0$memwr$\storage_5$build/ls180/gateware/ls180.v:9465$10_DATA[24:0]$2510 + update $memwr$\storage_5$build/ls180/gateware/ls180.v:9465$10_EN $0$memwr$\storage_5$build/ls180/gateware/ls180.v:9465$10_EN[24:0]$2511 + end + attribute \src "build/ls180/gateware/ls180.v:9469.1-9470.4" + process $proc$build/ls180/gateware/ls180.v:9469$2513 + sync posedge \sys_clk_1 + end + attribute \src "build/ls180/gateware/ls180.v:947.5-947.36" + process $proc$build/ls180/gateware/ls180.v:947$2940 + assign { } { } + assign $1\libresocsim_clocker_clk0[0:0] 1'0 + sync always + sync init + update \libresocsim_clocker_clk0 $1\libresocsim_clocker_clk0[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:9477.1-9481.4" + process $proc$build/ls180/gateware/ls180.v:9477$2515 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0$memwr$\storage_6$build/ls180/gateware/ls180.v:9479$11_ADDR[4:0]$2516 5'xxxxx + assign $0$memwr$\storage_6$build/ls180/gateware/ls180.v:9479$11_DATA[9:0]$2517 10'xxxxxxxxxx + assign $0$memwr$\storage_6$build/ls180/gateware/ls180.v:9479$11_EN[9:0]$2518 10'0000000000 + assign $0\memdat_8[9:0] $memrd$\storage_6$build/ls180/gateware/ls180.v:9480$2519_DATA + attribute \src "build/ls180/gateware/ls180.v:9478.2-9479.99" + switch \libresocsim_sdblock2mem_fifo_wrport_we + attribute \src "build/ls180/gateware/ls180.v:9478.6-9478.44" + case 1'1 + assign $0$memwr$\storage_6$build/ls180/gateware/ls180.v:9479$11_ADDR[4:0]$2516 \libresocsim_sdblock2mem_fifo_wrport_adr + assign $0$memwr$\storage_6$build/ls180/gateware/ls180.v:9479$11_DATA[9:0]$2517 \libresocsim_sdblock2mem_fifo_wrport_dat_w + assign $0$memwr$\storage_6$build/ls180/gateware/ls180.v:9479$11_EN[9:0]$2518 10'1111111111 + case + end + sync posedge \sys_clk_1 + update \memdat_8 $0\memdat_8[9:0] + update $memwr$\storage_6$build/ls180/gateware/ls180.v:9479$11_ADDR $0$memwr$\storage_6$build/ls180/gateware/ls180.v:9479$11_ADDR[4:0]$2516 + update $memwr$\storage_6$build/ls180/gateware/ls180.v:9479$11_DATA $0$memwr$\storage_6$build/ls180/gateware/ls180.v:9479$11_DATA[9:0]$2517 + update $memwr$\storage_6$build/ls180/gateware/ls180.v:9479$11_EN $0$memwr$\storage_6$build/ls180/gateware/ls180.v:9479$11_EN[9:0]$2518 + end + attribute \src "build/ls180/gateware/ls180.v:9483.1-9484.4" + process $proc$build/ls180/gateware/ls180.v:9483$2520 + sync posedge \sys_clk_1 + end + attribute \src "build/ls180/gateware/ls180.v:949.11-949.42" + process $proc$build/ls180/gateware/ls180.v:949$2941 + assign { } { } + assign $1\libresocsim_clocker_clks[8:0] 9'000000000 + sync always + sync init + update \libresocsim_clocker_clks $1\libresocsim_clocker_clks[8:0] + end + attribute \src "build/ls180/gateware/ls180.v:9491.1-9495.4" + process $proc$build/ls180/gateware/ls180.v:9491$2522 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0$memwr$\storage_7$build/ls180/gateware/ls180.v:9493$12_ADDR[4:0]$2523 5'xxxxx + assign $0$memwr$\storage_7$build/ls180/gateware/ls180.v:9493$12_DATA[9:0]$2524 10'xxxxxxxxxx + assign $0$memwr$\storage_7$build/ls180/gateware/ls180.v:9493$12_EN[9:0]$2525 10'0000000000 + assign $0\memdat_9[9:0] $memrd$\storage_7$build/ls180/gateware/ls180.v:9494$2526_DATA + attribute \src "build/ls180/gateware/ls180.v:9492.2-9493.99" + switch \libresocsim_sdmem2block_fifo_wrport_we + attribute \src "build/ls180/gateware/ls180.v:9492.6-9492.44" + case 1'1 + assign $0$memwr$\storage_7$build/ls180/gateware/ls180.v:9493$12_ADDR[4:0]$2523 \libresocsim_sdmem2block_fifo_wrport_adr + assign $0$memwr$\storage_7$build/ls180/gateware/ls180.v:9493$12_DATA[9:0]$2524 \libresocsim_sdmem2block_fifo_wrport_dat_w + assign $0$memwr$\storage_7$build/ls180/gateware/ls180.v:9493$12_EN[9:0]$2525 10'1111111111 + case + end + sync posedge \sys_clk_1 + update \memdat_9 $0\memdat_9[9:0] + update $memwr$\storage_7$build/ls180/gateware/ls180.v:9493$12_ADDR $0$memwr$\storage_7$build/ls180/gateware/ls180.v:9493$12_ADDR[4:0]$2523 + update $memwr$\storage_7$build/ls180/gateware/ls180.v:9493$12_DATA $0$memwr$\storage_7$build/ls180/gateware/ls180.v:9493$12_DATA[9:0]$2524 + update $memwr$\storage_7$build/ls180/gateware/ls180.v:9493$12_EN $0$memwr$\storage_7$build/ls180/gateware/ls180.v:9493$12_EN[9:0]$2525 + end + attribute \src "build/ls180/gateware/ls180.v:9497.1-9498.4" + process $proc$build/ls180/gateware/ls180.v:9497$2527 + sync posedge \sys_clk_1 + end + attribute \src "build/ls180/gateware/ls180.v:950.5-950.36" + process $proc$build/ls180/gateware/ls180.v:950$2942 + assign { } { } + assign $1\libresocsim_clocker_clk1[0:0] 1'0 + sync always + sync init + update \libresocsim_clocker_clk1 $1\libresocsim_clocker_clk1[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:951.5-951.37" + process $proc$build/ls180/gateware/ls180.v:951$2943 + assign { } { } + assign $1\libresocsim_clocker_clk_d[0:0] 1'0 + sync always + sync init + update \libresocsim_clocker_clk_d $1\libresocsim_clocker_clk_d[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:955.5-955.41" + process $proc$build/ls180/gateware/ls180.v:955$2944 + assign { } { } + assign $0\libresocsim_init_initialize_w[0:0] 1'0 + sync always + update \libresocsim_init_initialize_w $0\libresocsim_init_initialize_w[0:0] + sync init + end + attribute \src "build/ls180/gateware/ls180.v:96.12-96.71" + process $proc$build/ls180/gateware/ls180.v:96$2583 + assign { } { } + assign $1\main_libresocsim_interface0_converted_interface_adr[29:0] 30'000000000000000000000000000000 + sync always + sync init + update \main_libresocsim_interface0_converted_interface_adr $1\main_libresocsim_interface0_converted_interface_adr[29:0] + end + attribute \src "build/ls180/gateware/ls180.v:960.5-960.49" + process $proc$build/ls180/gateware/ls180.v:960$2945 + assign { } { } + assign $1\libresocsim_init_pads_out_payload_clk[0:0] 1'0 + sync always + sync init + update \libresocsim_init_pads_out_payload_clk $1\libresocsim_init_pads_out_payload_clk[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:961.5-961.51" + process $proc$build/ls180/gateware/ls180.v:961$2946 + assign { } { } + assign $1\libresocsim_init_pads_out_payload_cmd_o[0:0] 1'0 + sync always + sync init + update \libresocsim_init_pads_out_payload_cmd_o $1\libresocsim_init_pads_out_payload_cmd_o[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:962.5-962.52" + process $proc$build/ls180/gateware/ls180.v:962$2947 + assign { } { } + assign $1\libresocsim_init_pads_out_payload_cmd_oe[0:0] 1'0 + sync always + sync init + update \libresocsim_init_pads_out_payload_cmd_oe $1\libresocsim_init_pads_out_payload_cmd_oe[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:963.11-963.58" + process $proc$build/ls180/gateware/ls180.v:963$2948 + assign { } { } + assign $1\libresocsim_init_pads_out_payload_data_o[3:0] 4'0000 + sync always + sync init + update \libresocsim_init_pads_out_payload_data_o $1\libresocsim_init_pads_out_payload_data_o[3:0] + end + attribute \src "build/ls180/gateware/ls180.v:964.5-964.53" + process $proc$build/ls180/gateware/ls180.v:964$2949 + assign { } { } + assign $1\libresocsim_init_pads_out_payload_data_oe[0:0] 1'0 + sync always + sync init + update \libresocsim_init_pads_out_payload_data_oe $1\libresocsim_init_pads_out_payload_data_oe[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:965.11-965.40" + process $proc$build/ls180/gateware/ls180.v:965$2950 + assign { } { } + assign $1\libresocsim_init_count[7:0] 8'00000000 + sync always + sync init + update \libresocsim_init_count $1\libresocsim_init_count[7:0] + end + attribute \src "build/ls180/gateware/ls180.v:97.12-97.73" + process $proc$build/ls180/gateware/ls180.v:97$2584 + assign { } { } + assign $1\main_libresocsim_interface0_converted_interface_dat_w[31:0] 0 + sync always + sync init + update \main_libresocsim_interface0_converted_interface_dat_w $1\main_libresocsim_interface0_converted_interface_dat_w[31:0] + end + attribute \src "build/ls180/gateware/ls180.v:970.5-970.49" + process $proc$build/ls180/gateware/ls180.v:970$2951 + assign { } { } + assign $1\libresocsim_cmdw_pads_out_payload_clk[0:0] 1'0 + sync always + sync init + update \libresocsim_cmdw_pads_out_payload_clk $1\libresocsim_cmdw_pads_out_payload_clk[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:971.5-971.51" + process $proc$build/ls180/gateware/ls180.v:971$2952 + assign { } { } + assign $1\libresocsim_cmdw_pads_out_payload_cmd_o[0:0] 1'0 + sync always + sync init + update \libresocsim_cmdw_pads_out_payload_cmd_o $1\libresocsim_cmdw_pads_out_payload_cmd_o[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:972.5-972.52" + process $proc$build/ls180/gateware/ls180.v:972$2953 + assign { } { } + assign $1\libresocsim_cmdw_pads_out_payload_cmd_oe[0:0] 1'0 + sync always + sync init + update \libresocsim_cmdw_pads_out_payload_cmd_oe $1\libresocsim_cmdw_pads_out_payload_cmd_oe[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:973.11-973.58" + process $proc$build/ls180/gateware/ls180.v:973$2954 + assign { } { } + assign $0\libresocsim_cmdw_pads_out_payload_data_o[3:0] 4'0000 + sync always + update \libresocsim_cmdw_pads_out_payload_data_o $0\libresocsim_cmdw_pads_out_payload_data_o[3:0] + sync init + end + attribute \src "build/ls180/gateware/ls180.v:974.5-974.53" + process $proc$build/ls180/gateware/ls180.v:974$2955 + assign { } { } + assign $0\libresocsim_cmdw_pads_out_payload_data_oe[0:0] 1'0 + sync always + update \libresocsim_cmdw_pads_out_payload_data_oe $0\libresocsim_cmdw_pads_out_payload_data_oe[0:0] + sync init + end + attribute \src "build/ls180/gateware/ls180.v:975.5-975.39" + process $proc$build/ls180/gateware/ls180.v:975$2956 + assign { } { } + assign $1\libresocsim_cmdw_sink_valid[0:0] 1'0 + sync always + sync init + update \libresocsim_cmdw_sink_valid $1\libresocsim_cmdw_sink_valid[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:976.5-976.39" + process $proc$build/ls180/gateware/ls180.v:976$2957 + assign { } { } + assign $1\libresocsim_cmdw_sink_ready[0:0] 1'0 + sync always + sync init + update \libresocsim_cmdw_sink_ready $1\libresocsim_cmdw_sink_ready[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:977.5-977.38" + process $proc$build/ls180/gateware/ls180.v:977$2958 + assign { } { } + assign $1\libresocsim_cmdw_sink_last[0:0] 1'0 + sync always + sync init + update \libresocsim_cmdw_sink_last $1\libresocsim_cmdw_sink_last[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:978.11-978.52" + process $proc$build/ls180/gateware/ls180.v:978$2959 + assign { } { } + assign $1\libresocsim_cmdw_sink_payload_data[7:0] 8'00000000 + sync always + sync init + update \libresocsim_cmdw_sink_payload_data $1\libresocsim_cmdw_sink_payload_data[7:0] + end + attribute \src "build/ls180/gateware/ls180.v:979.5-979.33" + process $proc$build/ls180/gateware/ls180.v:979$2960 + assign { } { } + assign $1\libresocsim_cmdw_done[0:0] 1'0 + sync always + sync init + update \libresocsim_cmdw_done $1\libresocsim_cmdw_done[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:980.11-980.40" + process $proc$build/ls180/gateware/ls180.v:980$2961 + assign { } { } + assign $1\libresocsim_cmdw_count[7:0] 8'00000000 + sync always + sync init + update \libresocsim_cmdw_count $1\libresocsim_cmdw_count[7:0] + end + attribute \src "build/ls180/gateware/ls180.v:983.5-983.50" + process $proc$build/ls180/gateware/ls180.v:983$2962 + assign { } { } + assign $0\libresocsim_cmdr_pads_in_pads_in_first[0:0] 1'0 + sync always + update \libresocsim_cmdr_pads_in_pads_in_first $0\libresocsim_cmdr_pads_in_pads_in_first[0:0] + sync init + end + attribute \src "build/ls180/gateware/ls180.v:984.5-984.49" + process $proc$build/ls180/gateware/ls180.v:984$2963 + assign { } { } + assign $0\libresocsim_cmdr_pads_in_pads_in_last[0:0] 1'0 + sync always + update \libresocsim_cmdr_pads_in_pads_in_last $0\libresocsim_cmdr_pads_in_pads_in_last[0:0] + sync init + end + attribute \src "build/ls180/gateware/ls180.v:985.5-985.56" + process $proc$build/ls180/gateware/ls180.v:985$2964 + assign { } { } + assign $0\libresocsim_cmdr_pads_in_pads_in_payload_clk[0:0] 1'0 + sync always + update \libresocsim_cmdr_pads_in_pads_in_payload_clk $0\libresocsim_cmdr_pads_in_pads_in_payload_clk[0:0] + sync init + end + attribute \src "build/ls180/gateware/ls180.v:987.5-987.58" + process $proc$build/ls180/gateware/ls180.v:987$2965 + assign { } { } + assign $0\libresocsim_cmdr_pads_in_pads_in_payload_cmd_o[0:0] 1'0 + sync always + update \libresocsim_cmdr_pads_in_pads_in_payload_cmd_o $0\libresocsim_cmdr_pads_in_pads_in_payload_cmd_o[0:0] + sync init + end + attribute \src "build/ls180/gateware/ls180.v:988.5-988.59" + process $proc$build/ls180/gateware/ls180.v:988$2966 + assign { } { } + assign $0\libresocsim_cmdr_pads_in_pads_in_payload_cmd_oe[0:0] 1'0 + sync always + update \libresocsim_cmdr_pads_in_pads_in_payload_cmd_oe $0\libresocsim_cmdr_pads_in_pads_in_payload_cmd_oe[0:0] + sync init + end + attribute \src "build/ls180/gateware/ls180.v:99.11-99.69" + process $proc$build/ls180/gateware/ls180.v:99$2585 + assign { } { } + assign $1\main_libresocsim_interface0_converted_interface_sel[3:0] 4'0000 + sync always + sync init + update \main_libresocsim_interface0_converted_interface_sel $1\main_libresocsim_interface0_converted_interface_sel[3:0] + end + attribute \src "build/ls180/gateware/ls180.v:990.11-990.65" + process $proc$build/ls180/gateware/ls180.v:990$2967 + assign { } { } + assign $0\libresocsim_cmdr_pads_in_pads_in_payload_data_o[3:0] 4'0000 + sync always + update \libresocsim_cmdr_pads_in_pads_in_payload_data_o $0\libresocsim_cmdr_pads_in_pads_in_payload_data_o[3:0] + sync init + end + attribute \src "build/ls180/gateware/ls180.v:991.5-991.60" + process $proc$build/ls180/gateware/ls180.v:991$2968 + assign { } { } + assign $0\libresocsim_cmdr_pads_in_pads_in_payload_data_oe[0:0] 1'0 + sync always + update \libresocsim_cmdr_pads_in_pads_in_payload_data_oe $0\libresocsim_cmdr_pads_in_pads_in_payload_data_oe[0:0] + sync init + end + attribute \src "build/ls180/gateware/ls180.v:993.5-993.49" + process $proc$build/ls180/gateware/ls180.v:993$2969 + assign { } { } + assign $1\libresocsim_cmdr_pads_out_payload_clk[0:0] 1'0 + sync always + sync init + update \libresocsim_cmdr_pads_out_payload_clk $1\libresocsim_cmdr_pads_out_payload_clk[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:994.5-994.51" + process $proc$build/ls180/gateware/ls180.v:994$2970 + assign { } { } + assign $1\libresocsim_cmdr_pads_out_payload_cmd_o[0:0] 1'0 + sync always + sync init + update \libresocsim_cmdr_pads_out_payload_cmd_o $1\libresocsim_cmdr_pads_out_payload_cmd_o[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:995.5-995.52" + process $proc$build/ls180/gateware/ls180.v:995$2971 + assign { } { } + assign $1\libresocsim_cmdr_pads_out_payload_cmd_oe[0:0] 1'0 + sync always + sync init + update \libresocsim_cmdr_pads_out_payload_cmd_oe $1\libresocsim_cmdr_pads_out_payload_cmd_oe[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:996.11-996.58" + process $proc$build/ls180/gateware/ls180.v:996$2972 + assign { } { } + assign $0\libresocsim_cmdr_pads_out_payload_data_o[3:0] 4'0000 + sync always + update \libresocsim_cmdr_pads_out_payload_data_o $0\libresocsim_cmdr_pads_out_payload_data_o[3:0] + sync init + end + attribute \src "build/ls180/gateware/ls180.v:997.5-997.53" + process $proc$build/ls180/gateware/ls180.v:997$2973 + assign { } { } + assign $0\libresocsim_cmdr_pads_out_payload_data_oe[0:0] 1'0 + sync always + update \libresocsim_cmdr_pads_out_payload_data_oe $0\libresocsim_cmdr_pads_out_payload_data_oe[0:0] + sync init + end + attribute \src "build/ls180/gateware/ls180.v:998.5-998.39" + process $proc$build/ls180/gateware/ls180.v:998$2974 + assign { } { } + assign $1\libresocsim_cmdr_sink_valid[0:0] 1'0 + sync always + sync init + update \libresocsim_cmdr_sink_valid $1\libresocsim_cmdr_sink_valid[0:0] + end + attribute \src "build/ls180/gateware/ls180.v:999.5-999.39" + process $proc$build/ls180/gateware/ls180.v:999$2975 + assign { } { } + assign $1\libresocsim_cmdr_sink_ready[0:0] 1'0 + sync always + sync init + update \libresocsim_cmdr_sink_ready $1\libresocsim_cmdr_sink_ready[0:0] + end + connect \main_libresocsim_libresoc_reset \main_libresocsim_soccontroller_reset + connect \libresocsim_sdblock2mem_sink_sink_valid0 \libresocsim_sdcore_source_source_valid + connect \libresocsim_sdcore_source_source_ready \libresocsim_sdblock2mem_sink_sink_ready0 + connect \libresocsim_sdblock2mem_sink_sink_first \libresocsim_sdcore_source_source_first + connect \libresocsim_sdblock2mem_sink_sink_last \libresocsim_sdcore_source_source_last + connect \libresocsim_sdblock2mem_sink_sink_payload_data0 \libresocsim_sdcore_source_source_payload_data + connect \libresocsim_sdcore_sink_sink_valid \libresocsim_sdmem2block_source_source_valid0 + connect \libresocsim_sdmem2block_source_source_ready0 \libresocsim_sdcore_sink_sink_ready + connect \libresocsim_sdcore_sink_sink_first \libresocsim_sdmem2block_source_source_first0 + connect \libresocsim_sdcore_sink_sink_last \libresocsim_sdmem2block_source_source_last0 + connect \libresocsim_sdcore_sink_sink_payload_data \libresocsim_sdmem2block_source_source_payload_data0 + connect \main_libresocsim_soccontroller_bus_error \builder_error + connect \main_libresocsim_converter0_reset $not$build/ls180/gateware/ls180.v:2593$14_Y + connect \main_libresocsim_libresoc_ibus_dat_r { \main_libresocsim_interface0_converted_interface_dat_r \main_libresocsim_converter0_dat_r [63:32] } + connect \main_libresocsim_converter1_reset $not$build/ls180/gateware/ls180.v:2653$25_Y + connect \main_libresocsim_libresoc_dbus_dat_r { \main_libresocsim_interface1_converted_interface_dat_r \main_libresocsim_converter1_dat_r [63:32] } + connect \main_libresocsim_soccontroller_reset \main_libresocsim_soccontroller_reset_re + connect \main_libresocsim_soccontroller_bus_errors_status \main_libresocsim_soccontroller_bus_errors + connect \main_libresocsim_adr \main_libresocsim_ram_bus_adr [15:0] + connect \main_libresocsim_ram_bus_dat_r \main_libresocsim_dat_r + connect \main_libresocsim_dat_w \main_libresocsim_ram_bus_dat_w + connect \main_libresocsim_uart_uart_sink_valid \main_libresocsim_source_valid + connect \main_libresocsim_source_ready \main_libresocsim_uart_uart_sink_ready + connect \main_libresocsim_uart_uart_sink_first \main_libresocsim_source_first + connect \main_libresocsim_uart_uart_sink_last \main_libresocsim_source_last + connect \main_libresocsim_uart_uart_sink_payload_data \main_libresocsim_source_payload_data + connect \main_libresocsim_sink_valid \main_libresocsim_uart_uart_source_valid + connect \main_libresocsim_uart_uart_source_ready \main_libresocsim_sink_ready + connect \main_libresocsim_sink_first \main_libresocsim_uart_uart_source_first + connect \main_libresocsim_sink_last \main_libresocsim_uart_uart_source_last + connect \main_libresocsim_sink_payload_data \main_libresocsim_uart_uart_source_payload_data + connect \main_libresocsim_uart_tx_fifo_sink_valid \main_libresocsim_uart_rxtx_re + connect \main_libresocsim_uart_tx_fifo_sink_payload_data \main_libresocsim_uart_rxtx_r + connect \main_libresocsim_uart_txfull_status $not$build/ls180/gateware/ls180.v:2737$49_Y + connect \main_libresocsim_uart_txempty_status $not$build/ls180/gateware/ls180.v:2738$50_Y + connect \main_libresocsim_uart_uart_source_valid \main_libresocsim_uart_tx_fifo_source_valid + connect \main_libresocsim_uart_tx_fifo_source_ready \main_libresocsim_uart_uart_source_ready + connect \main_libresocsim_uart_uart_source_first \main_libresocsim_uart_tx_fifo_source_first + connect \main_libresocsim_uart_uart_source_last \main_libresocsim_uart_tx_fifo_source_last + connect \main_libresocsim_uart_uart_source_payload_data \main_libresocsim_uart_tx_fifo_source_payload_data + connect \main_libresocsim_uart_tx_trigger $not$build/ls180/gateware/ls180.v:2744$51_Y + connect \main_libresocsim_uart_rx_fifo_sink_valid \main_libresocsim_uart_uart_sink_valid + connect \main_libresocsim_uart_uart_sink_ready \main_libresocsim_uart_rx_fifo_sink_ready + connect \main_libresocsim_uart_rx_fifo_sink_first \main_libresocsim_uart_uart_sink_first + connect \main_libresocsim_uart_rx_fifo_sink_last \main_libresocsim_uart_uart_sink_last + connect \main_libresocsim_uart_rx_fifo_sink_payload_data \main_libresocsim_uart_uart_sink_payload_data + connect \main_libresocsim_uart_rxempty_status $not$build/ls180/gateware/ls180.v:2750$52_Y + connect \main_libresocsim_uart_rxfull_status $not$build/ls180/gateware/ls180.v:2751$53_Y + connect \main_libresocsim_uart_rxtx_w \main_libresocsim_uart_rx_fifo_source_payload_data + connect \main_libresocsim_uart_rx_fifo_source_ready $or$build/ls180/gateware/ls180.v:2753$55_Y + connect \main_libresocsim_uart_rx_trigger $not$build/ls180/gateware/ls180.v:2754$56_Y + connect \main_libresocsim_uart_irq $or$build/ls180/gateware/ls180.v:2777$65_Y + connect \main_libresocsim_uart_tx_status \main_libresocsim_uart_tx_trigger + connect \main_libresocsim_uart_rx_status \main_libresocsim_uart_rx_trigger + connect \main_libresocsim_uart_tx_fifo_syncfifo_din { \main_libresocsim_uart_tx_fifo_fifo_in_last \main_libresocsim_uart_tx_fifo_fifo_in_first \main_libresocsim_uart_tx_fifo_fifo_in_payload_data } + connect { \main_libresocsim_uart_tx_fifo_fifo_out_last \main_libresocsim_uart_tx_fifo_fifo_out_first \main_libresocsim_uart_tx_fifo_fifo_out_payload_data } \main_libresocsim_uart_tx_fifo_syncfifo_dout + connect \main_libresocsim_uart_tx_fifo_sink_ready \main_libresocsim_uart_tx_fifo_syncfifo_writable + connect \main_libresocsim_uart_tx_fifo_syncfifo_we \main_libresocsim_uart_tx_fifo_sink_valid + connect \main_libresocsim_uart_tx_fifo_fifo_in_first \main_libresocsim_uart_tx_fifo_sink_first + connect \main_libresocsim_uart_tx_fifo_fifo_in_last \main_libresocsim_uart_tx_fifo_sink_last + connect \main_libresocsim_uart_tx_fifo_fifo_in_payload_data \main_libresocsim_uart_tx_fifo_sink_payload_data + connect \main_libresocsim_uart_tx_fifo_source_valid \main_libresocsim_uart_tx_fifo_readable + connect \main_libresocsim_uart_tx_fifo_source_first \main_libresocsim_uart_tx_fifo_fifo_out_first + connect \main_libresocsim_uart_tx_fifo_source_last \main_libresocsim_uart_tx_fifo_fifo_out_last + connect \main_libresocsim_uart_tx_fifo_source_payload_data \main_libresocsim_uart_tx_fifo_fifo_out_payload_data + connect \main_libresocsim_uart_tx_fifo_re \main_libresocsim_uart_tx_fifo_source_ready + connect \main_libresocsim_uart_tx_fifo_syncfifo_re $and$build/ls180/gateware/ls180.v:2792$68_Y + connect \main_libresocsim_uart_tx_fifo_level1 $add$build/ls180/gateware/ls180.v:2793$69_Y + connect \main_libresocsim_uart_tx_fifo_wrport_dat_w \main_libresocsim_uart_tx_fifo_syncfifo_din + connect \main_libresocsim_uart_tx_fifo_wrport_we $and$build/ls180/gateware/ls180.v:2803$73_Y + connect \main_libresocsim_uart_tx_fifo_do_read $and$build/ls180/gateware/ls180.v:2804$74_Y + connect \main_libresocsim_uart_tx_fifo_rdport_adr \main_libresocsim_uart_tx_fifo_consume + connect \main_libresocsim_uart_tx_fifo_syncfifo_dout \main_libresocsim_uart_tx_fifo_rdport_dat_r + connect \main_libresocsim_uart_tx_fifo_rdport_re \main_libresocsim_uart_tx_fifo_do_read + connect \main_libresocsim_uart_tx_fifo_syncfifo_writable $ne$build/ls180/gateware/ls180.v:2808$75_Y + connect \main_libresocsim_uart_tx_fifo_syncfifo_readable $ne$build/ls180/gateware/ls180.v:2809$76_Y + connect \main_libresocsim_uart_rx_fifo_syncfifo_din { \main_libresocsim_uart_rx_fifo_fifo_in_last \main_libresocsim_uart_rx_fifo_fifo_in_first \main_libresocsim_uart_rx_fifo_fifo_in_payload_data } + connect { \main_libresocsim_uart_rx_fifo_fifo_out_last \main_libresocsim_uart_rx_fifo_fifo_out_first \main_libresocsim_uart_rx_fifo_fifo_out_payload_data } \main_libresocsim_uart_rx_fifo_syncfifo_dout + connect \main_libresocsim_uart_rx_fifo_sink_ready \main_libresocsim_uart_rx_fifo_syncfifo_writable + connect \main_libresocsim_uart_rx_fifo_syncfifo_we \main_libresocsim_uart_rx_fifo_sink_valid + connect \main_libresocsim_uart_rx_fifo_fifo_in_first \main_libresocsim_uart_rx_fifo_sink_first + connect \main_libresocsim_uart_rx_fifo_fifo_in_last \main_libresocsim_uart_rx_fifo_sink_last + connect \main_libresocsim_uart_rx_fifo_fifo_in_payload_data \main_libresocsim_uart_rx_fifo_sink_payload_data + connect \main_libresocsim_uart_rx_fifo_source_valid \main_libresocsim_uart_rx_fifo_readable + connect \main_libresocsim_uart_rx_fifo_source_first \main_libresocsim_uart_rx_fifo_fifo_out_first + connect \main_libresocsim_uart_rx_fifo_source_last \main_libresocsim_uart_rx_fifo_fifo_out_last + connect \main_libresocsim_uart_rx_fifo_source_payload_data \main_libresocsim_uart_rx_fifo_fifo_out_payload_data + connect \main_libresocsim_uart_rx_fifo_re \main_libresocsim_uart_rx_fifo_source_ready + connect \main_libresocsim_uart_rx_fifo_syncfifo_re $and$build/ls180/gateware/ls180.v:2822$79_Y + connect \main_libresocsim_uart_rx_fifo_level1 $add$build/ls180/gateware/ls180.v:2823$80_Y + connect \main_libresocsim_uart_rx_fifo_wrport_dat_w \main_libresocsim_uart_rx_fifo_syncfifo_din + connect \main_libresocsim_uart_rx_fifo_wrport_we $and$build/ls180/gateware/ls180.v:2833$84_Y + connect \main_libresocsim_uart_rx_fifo_do_read $and$build/ls180/gateware/ls180.v:2834$85_Y + connect \main_libresocsim_uart_rx_fifo_rdport_adr \main_libresocsim_uart_rx_fifo_consume + connect \main_libresocsim_uart_rx_fifo_syncfifo_dout \main_libresocsim_uart_rx_fifo_rdport_dat_r + connect \main_libresocsim_uart_rx_fifo_rdport_re \main_libresocsim_uart_rx_fifo_do_read + connect \main_libresocsim_uart_rx_fifo_syncfifo_writable $ne$build/ls180/gateware/ls180.v:2838$86_Y + connect \main_libresocsim_uart_rx_fifo_syncfifo_readable $ne$build/ls180/gateware/ls180.v:2839$87_Y + connect \main_libresocsim_timer_zero_trigger $ne$build/ls180/gateware/ls180.v:2840$88_Y + connect \main_libresocsim_timer_eventmanager_status_w \main_libresocsim_timer_zero_status + connect \main_libresocsim_timer_eventmanager_pending_w \main_libresocsim_timer_zero_pending + connect \main_libresocsim_timer_irq $and$build/ls180/gateware/ls180.v:2849$91_Y + connect \main_libresocsim_timer_zero_status \main_libresocsim_timer_zero_trigger + connect \sys_clk_1 \sys_clk + connect \por_clk \sys_clk + connect \sys_rst \main_int_rst + connect \main_dfi_p0_address \main_sdram_master_p0_address + connect \main_dfi_p0_bank \main_sdram_master_p0_bank + connect \main_dfi_p0_cas_n \main_sdram_master_p0_cas_n + connect \main_dfi_p0_cs_n \main_sdram_master_p0_cs_n + connect \main_dfi_p0_ras_n \main_sdram_master_p0_ras_n + connect \main_dfi_p0_we_n \main_sdram_master_p0_we_n + connect \main_dfi_p0_cke \main_sdram_master_p0_cke + connect \main_dfi_p0_odt \main_sdram_master_p0_odt + connect \main_dfi_p0_reset_n \main_sdram_master_p0_reset_n + connect \main_dfi_p0_act_n \main_sdram_master_p0_act_n + connect \main_dfi_p0_wrdata \main_sdram_master_p0_wrdata + connect \main_dfi_p0_wrdata_en \main_sdram_master_p0_wrdata_en + connect \main_dfi_p0_wrdata_mask \main_sdram_master_p0_wrdata_mask + connect \main_dfi_p0_rddata_en \main_sdram_master_p0_rddata_en + connect \main_sdram_master_p0_rddata \main_dfi_p0_rddata + connect \main_sdram_master_p0_rddata_valid \main_dfi_p0_rddata_valid + connect \main_sdram_slave_p0_address \main_sdram_dfi_p0_address + connect \main_sdram_slave_p0_bank \main_sdram_dfi_p0_bank + connect \main_sdram_slave_p0_cas_n \main_sdram_dfi_p0_cas_n + connect \main_sdram_slave_p0_cs_n \main_sdram_dfi_p0_cs_n + connect \main_sdram_slave_p0_ras_n \main_sdram_dfi_p0_ras_n + connect \main_sdram_slave_p0_we_n \main_sdram_dfi_p0_we_n + connect \main_sdram_slave_p0_cke \main_sdram_dfi_p0_cke + connect \main_sdram_slave_p0_odt \main_sdram_dfi_p0_odt + connect \main_sdram_slave_p0_reset_n \main_sdram_dfi_p0_reset_n + connect \main_sdram_slave_p0_act_n \main_sdram_dfi_p0_act_n + connect \main_sdram_slave_p0_wrdata \main_sdram_dfi_p0_wrdata + connect \main_sdram_slave_p0_wrdata_en \main_sdram_dfi_p0_wrdata_en + connect \main_sdram_slave_p0_wrdata_mask \main_sdram_dfi_p0_wrdata_mask + connect \main_sdram_slave_p0_rddata_en \main_sdram_dfi_p0_rddata_en + connect \main_sdram_dfi_p0_rddata \main_sdram_slave_p0_rddata + connect \main_sdram_dfi_p0_rddata_valid \main_sdram_slave_p0_rddata_valid + connect \main_sdram_inti_p0_cke \main_sdram_cke + connect \main_sdram_inti_p0_odt \main_sdram_odt + connect \main_sdram_inti_p0_reset_n \main_sdram_reset_n + connect \main_sdram_inti_p0_address \main_sdram_address_storage + connect \main_sdram_inti_p0_bank \main_sdram_baddress_storage + connect \main_sdram_inti_p0_wrdata_en $and$build/ls180/gateware/ls180.v:2968$99_Y + connect \main_sdram_inti_p0_rddata_en $and$build/ls180/gateware/ls180.v:2969$100_Y + connect \main_sdram_inti_p0_wrdata \main_sdram_wrdata_storage + connect \main_sdram_inti_p0_wrdata_mask 2'00 + connect \main_sdram_bankmachine0_req_valid \main_sdram_interface_bank0_valid + connect \main_sdram_interface_bank0_ready \main_sdram_bankmachine0_req_ready + connect \main_sdram_bankmachine0_req_we \main_sdram_interface_bank0_we + connect \main_sdram_bankmachine0_req_addr \main_sdram_interface_bank0_addr + connect \main_sdram_interface_bank0_lock \main_sdram_bankmachine0_req_lock + connect \main_sdram_interface_bank0_wdata_ready \main_sdram_bankmachine0_req_wdata_ready + connect \main_sdram_interface_bank0_rdata_valid \main_sdram_bankmachine0_req_rdata_valid + connect \main_sdram_bankmachine1_req_valid \main_sdram_interface_bank1_valid + connect \main_sdram_interface_bank1_ready \main_sdram_bankmachine1_req_ready + connect \main_sdram_bankmachine1_req_we \main_sdram_interface_bank1_we + connect \main_sdram_bankmachine1_req_addr \main_sdram_interface_bank1_addr + connect \main_sdram_interface_bank1_lock \main_sdram_bankmachine1_req_lock + connect \main_sdram_interface_bank1_wdata_ready \main_sdram_bankmachine1_req_wdata_ready + connect \main_sdram_interface_bank1_rdata_valid \main_sdram_bankmachine1_req_rdata_valid + connect \main_sdram_bankmachine2_req_valid \main_sdram_interface_bank2_valid + connect \main_sdram_interface_bank2_ready \main_sdram_bankmachine2_req_ready + connect \main_sdram_bankmachine2_req_we \main_sdram_interface_bank2_we + connect \main_sdram_bankmachine2_req_addr \main_sdram_interface_bank2_addr + connect \main_sdram_interface_bank2_lock \main_sdram_bankmachine2_req_lock + connect \main_sdram_interface_bank2_wdata_ready \main_sdram_bankmachine2_req_wdata_ready + connect \main_sdram_interface_bank2_rdata_valid \main_sdram_bankmachine2_req_rdata_valid + connect \main_sdram_bankmachine3_req_valid \main_sdram_interface_bank3_valid + connect \main_sdram_interface_bank3_ready \main_sdram_bankmachine3_req_ready + connect \main_sdram_bankmachine3_req_we \main_sdram_interface_bank3_we + connect \main_sdram_bankmachine3_req_addr \main_sdram_interface_bank3_addr + connect \main_sdram_interface_bank3_lock \main_sdram_bankmachine3_req_lock + connect \main_sdram_interface_bank3_wdata_ready \main_sdram_bankmachine3_req_wdata_ready + connect \main_sdram_interface_bank3_rdata_valid \main_sdram_bankmachine3_req_rdata_valid + connect \main_sdram_timer_wait $not$build/ls180/gateware/ls180.v:3000$101_Y + connect \main_sdram_postponer_req_i \main_sdram_timer_done0 + connect \main_sdram_wants_refresh \main_sdram_postponer_req_o + connect \main_sdram_timer_done1 $eq$build/ls180/gateware/ls180.v:3003$102_Y + connect \main_sdram_timer_done0 \main_sdram_timer_done1 + connect \main_sdram_timer_count0 \main_sdram_timer_count1 + connect \main_sdram_sequencer_start1 $or$build/ls180/gateware/ls180.v:3006$104_Y + connect \main_sdram_sequencer_done0 $and$build/ls180/gateware/ls180.v:3007$106_Y + connect \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_valid \main_sdram_bankmachine0_req_valid + connect \main_sdram_bankmachine0_req_ready \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_ready + connect \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_payload_we \main_sdram_bankmachine0_req_we + connect \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_payload_addr \main_sdram_bankmachine0_req_addr + connect \main_sdram_bankmachine0_cmd_buffer_sink_valid \main_sdram_bankmachine0_cmd_buffer_lookahead_source_valid + connect \main_sdram_bankmachine0_cmd_buffer_lookahead_source_ready \main_sdram_bankmachine0_cmd_buffer_sink_ready + connect \main_sdram_bankmachine0_cmd_buffer_sink_first \main_sdram_bankmachine0_cmd_buffer_lookahead_source_first + connect \main_sdram_bankmachine0_cmd_buffer_sink_last \main_sdram_bankmachine0_cmd_buffer_lookahead_source_last + connect \main_sdram_bankmachine0_cmd_buffer_sink_payload_we \main_sdram_bankmachine0_cmd_buffer_lookahead_source_payload_we + connect \main_sdram_bankmachine0_cmd_buffer_sink_payload_addr \main_sdram_bankmachine0_cmd_buffer_lookahead_source_payload_addr + connect \main_sdram_bankmachine0_cmd_buffer_source_ready $or$build/ls180/gateware/ls180.v:3049$108_Y + connect \main_sdram_bankmachine0_req_lock $or$build/ls180/gateware/ls180.v:3050$109_Y + connect \main_sdram_bankmachine0_row_hit $eq$build/ls180/gateware/ls180.v:3051$110_Y + connect \main_sdram_bankmachine0_cmd_payload_ba 2'00 + connect \main_sdram_bankmachine0_twtpcon_valid $and$build/ls180/gateware/ls180.v:3061$115_Y + connect \main_sdram_bankmachine0_trccon_valid $and$build/ls180/gateware/ls180.v:3062$117_Y + connect \main_sdram_bankmachine0_trascon_valid $and$build/ls180/gateware/ls180.v:3063$119_Y + connect \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_din { \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_last \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_first \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_addr \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_we } + connect { \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_last \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_first \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we } \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout + connect \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_ready \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable + connect \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_we \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_valid + connect \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_first \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_first + connect \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_last \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_last + connect \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_we \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_payload_we + connect \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_in_payload_addr \main_sdram_bankmachine0_cmd_buffer_lookahead_sink_payload_addr + connect \main_sdram_bankmachine0_cmd_buffer_lookahead_source_valid \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable + connect \main_sdram_bankmachine0_cmd_buffer_lookahead_source_first \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_first + connect \main_sdram_bankmachine0_cmd_buffer_lookahead_source_last \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_last + connect \main_sdram_bankmachine0_cmd_buffer_lookahead_source_payload_we \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_we + connect \main_sdram_bankmachine0_cmd_buffer_lookahead_source_payload_addr \main_sdram_bankmachine0_cmd_buffer_lookahead_fifo_out_payload_addr + connect \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_re \main_sdram_bankmachine0_cmd_buffer_lookahead_source_ready + connect \main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_dat_w \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_din + connect \main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_we $and$build/ls180/gateware/ls180.v:3095$127_Y + connect \main_sdram_bankmachine0_cmd_buffer_lookahead_do_read $and$build/ls180/gateware/ls180.v:3096$128_Y + connect \main_sdram_bankmachine0_cmd_buffer_lookahead_rdport_adr \main_sdram_bankmachine0_cmd_buffer_lookahead_consume + connect \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_dout \main_sdram_bankmachine0_cmd_buffer_lookahead_rdport_dat_r + connect \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_writable $ne$build/ls180/gateware/ls180.v:3099$129_Y + connect \main_sdram_bankmachine0_cmd_buffer_lookahead_syncfifo0_readable $ne$build/ls180/gateware/ls180.v:3100$130_Y + connect \main_sdram_bankmachine0_cmd_buffer_sink_ready $or$build/ls180/gateware/ls180.v:3101$132_Y + connect \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_valid \main_sdram_bankmachine1_req_valid + connect \main_sdram_bankmachine1_req_ready \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_ready + connect \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_payload_we \main_sdram_bankmachine1_req_we + connect \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_payload_addr \main_sdram_bankmachine1_req_addr + connect \main_sdram_bankmachine1_cmd_buffer_sink_valid \main_sdram_bankmachine1_cmd_buffer_lookahead_source_valid + connect \main_sdram_bankmachine1_cmd_buffer_lookahead_source_ready \main_sdram_bankmachine1_cmd_buffer_sink_ready + connect \main_sdram_bankmachine1_cmd_buffer_sink_first \main_sdram_bankmachine1_cmd_buffer_lookahead_source_first + connect \main_sdram_bankmachine1_cmd_buffer_sink_last \main_sdram_bankmachine1_cmd_buffer_lookahead_source_last + connect \main_sdram_bankmachine1_cmd_buffer_sink_payload_we \main_sdram_bankmachine1_cmd_buffer_lookahead_source_payload_we + connect \main_sdram_bankmachine1_cmd_buffer_sink_payload_addr \main_sdram_bankmachine1_cmd_buffer_lookahead_source_payload_addr + connect \main_sdram_bankmachine1_cmd_buffer_source_ready $or$build/ls180/gateware/ls180.v:3206$138_Y + connect \main_sdram_bankmachine1_req_lock $or$build/ls180/gateware/ls180.v:3207$139_Y + connect \main_sdram_bankmachine1_row_hit $eq$build/ls180/gateware/ls180.v:3208$140_Y + connect \main_sdram_bankmachine1_cmd_payload_ba 2'01 + connect \main_sdram_bankmachine1_twtpcon_valid $and$build/ls180/gateware/ls180.v:3218$145_Y + connect \main_sdram_bankmachine1_trccon_valid $and$build/ls180/gateware/ls180.v:3219$147_Y + connect \main_sdram_bankmachine1_trascon_valid $and$build/ls180/gateware/ls180.v:3220$149_Y + connect \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_din { \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_last \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_first \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_addr \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_we } + connect { \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_last \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_first \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we } \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout + connect \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_ready \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable + connect \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_we \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_valid + connect \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_first \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_first + connect \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_last \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_last + connect \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_we \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_payload_we + connect \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_in_payload_addr \main_sdram_bankmachine1_cmd_buffer_lookahead_sink_payload_addr + connect \main_sdram_bankmachine1_cmd_buffer_lookahead_source_valid \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable + connect \main_sdram_bankmachine1_cmd_buffer_lookahead_source_first \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_first + connect \main_sdram_bankmachine1_cmd_buffer_lookahead_source_last \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_last + connect \main_sdram_bankmachine1_cmd_buffer_lookahead_source_payload_we \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_we + connect \main_sdram_bankmachine1_cmd_buffer_lookahead_source_payload_addr \main_sdram_bankmachine1_cmd_buffer_lookahead_fifo_out_payload_addr + connect \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_re \main_sdram_bankmachine1_cmd_buffer_lookahead_source_ready + connect \main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_dat_w \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_din + connect \main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_we $and$build/ls180/gateware/ls180.v:3252$157_Y + connect \main_sdram_bankmachine1_cmd_buffer_lookahead_do_read $and$build/ls180/gateware/ls180.v:3253$158_Y + connect \main_sdram_bankmachine1_cmd_buffer_lookahead_rdport_adr \main_sdram_bankmachine1_cmd_buffer_lookahead_consume + connect \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_dout \main_sdram_bankmachine1_cmd_buffer_lookahead_rdport_dat_r + connect \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_writable $ne$build/ls180/gateware/ls180.v:3256$159_Y + connect \main_sdram_bankmachine1_cmd_buffer_lookahead_syncfifo1_readable $ne$build/ls180/gateware/ls180.v:3257$160_Y + connect \main_sdram_bankmachine1_cmd_buffer_sink_ready $or$build/ls180/gateware/ls180.v:3258$162_Y + connect \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_valid \main_sdram_bankmachine2_req_valid + connect \main_sdram_bankmachine2_req_ready \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_ready + connect \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_payload_we \main_sdram_bankmachine2_req_we + connect \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_payload_addr \main_sdram_bankmachine2_req_addr + connect \main_sdram_bankmachine2_cmd_buffer_sink_valid \main_sdram_bankmachine2_cmd_buffer_lookahead_source_valid + connect \main_sdram_bankmachine2_cmd_buffer_lookahead_source_ready \main_sdram_bankmachine2_cmd_buffer_sink_ready + connect \main_sdram_bankmachine2_cmd_buffer_sink_first \main_sdram_bankmachine2_cmd_buffer_lookahead_source_first + connect \main_sdram_bankmachine2_cmd_buffer_sink_last \main_sdram_bankmachine2_cmd_buffer_lookahead_source_last + connect \main_sdram_bankmachine2_cmd_buffer_sink_payload_we \main_sdram_bankmachine2_cmd_buffer_lookahead_source_payload_we + connect \main_sdram_bankmachine2_cmd_buffer_sink_payload_addr \main_sdram_bankmachine2_cmd_buffer_lookahead_source_payload_addr + connect \main_sdram_bankmachine2_cmd_buffer_source_ready $or$build/ls180/gateware/ls180.v:3363$168_Y + connect \main_sdram_bankmachine2_req_lock $or$build/ls180/gateware/ls180.v:3364$169_Y + connect \main_sdram_bankmachine2_row_hit $eq$build/ls180/gateware/ls180.v:3365$170_Y + connect \main_sdram_bankmachine2_cmd_payload_ba 2'10 + connect \main_sdram_bankmachine2_twtpcon_valid $and$build/ls180/gateware/ls180.v:3375$175_Y + connect \main_sdram_bankmachine2_trccon_valid $and$build/ls180/gateware/ls180.v:3376$177_Y + connect \main_sdram_bankmachine2_trascon_valid $and$build/ls180/gateware/ls180.v:3377$179_Y + connect \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_din { \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_last \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_first \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_addr \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_we } + connect { \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_last \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_first \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we } \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout + connect \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_ready \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable + connect \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_we \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_valid + connect \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_first \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_first + connect \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_last \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_last + connect \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_we \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_payload_we + connect \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_in_payload_addr \main_sdram_bankmachine2_cmd_buffer_lookahead_sink_payload_addr + connect \main_sdram_bankmachine2_cmd_buffer_lookahead_source_valid \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable + connect \main_sdram_bankmachine2_cmd_buffer_lookahead_source_first \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_first + connect \main_sdram_bankmachine2_cmd_buffer_lookahead_source_last \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_last + connect \main_sdram_bankmachine2_cmd_buffer_lookahead_source_payload_we \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_we + connect \main_sdram_bankmachine2_cmd_buffer_lookahead_source_payload_addr \main_sdram_bankmachine2_cmd_buffer_lookahead_fifo_out_payload_addr + connect \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_re \main_sdram_bankmachine2_cmd_buffer_lookahead_source_ready + connect \main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_dat_w \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_din + connect \main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_we $and$build/ls180/gateware/ls180.v:3409$187_Y + connect \main_sdram_bankmachine2_cmd_buffer_lookahead_do_read $and$build/ls180/gateware/ls180.v:3410$188_Y + connect \main_sdram_bankmachine2_cmd_buffer_lookahead_rdport_adr \main_sdram_bankmachine2_cmd_buffer_lookahead_consume + connect \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_dout \main_sdram_bankmachine2_cmd_buffer_lookahead_rdport_dat_r + connect \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_writable $ne$build/ls180/gateware/ls180.v:3413$189_Y + connect \main_sdram_bankmachine2_cmd_buffer_lookahead_syncfifo2_readable $ne$build/ls180/gateware/ls180.v:3414$190_Y + connect \main_sdram_bankmachine2_cmd_buffer_sink_ready $or$build/ls180/gateware/ls180.v:3415$192_Y + connect \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_valid \main_sdram_bankmachine3_req_valid + connect \main_sdram_bankmachine3_req_ready \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_ready + connect \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_payload_we \main_sdram_bankmachine3_req_we + connect \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_payload_addr \main_sdram_bankmachine3_req_addr + connect \main_sdram_bankmachine3_cmd_buffer_sink_valid \main_sdram_bankmachine3_cmd_buffer_lookahead_source_valid + connect \main_sdram_bankmachine3_cmd_buffer_lookahead_source_ready \main_sdram_bankmachine3_cmd_buffer_sink_ready + connect \main_sdram_bankmachine3_cmd_buffer_sink_first \main_sdram_bankmachine3_cmd_buffer_lookahead_source_first + connect \main_sdram_bankmachine3_cmd_buffer_sink_last \main_sdram_bankmachine3_cmd_buffer_lookahead_source_last + connect \main_sdram_bankmachine3_cmd_buffer_sink_payload_we \main_sdram_bankmachine3_cmd_buffer_lookahead_source_payload_we + connect \main_sdram_bankmachine3_cmd_buffer_sink_payload_addr \main_sdram_bankmachine3_cmd_buffer_lookahead_source_payload_addr + connect \main_sdram_bankmachine3_cmd_buffer_source_ready $or$build/ls180/gateware/ls180.v:3520$198_Y + connect \main_sdram_bankmachine3_req_lock $or$build/ls180/gateware/ls180.v:3521$199_Y + connect \main_sdram_bankmachine3_row_hit $eq$build/ls180/gateware/ls180.v:3522$200_Y + connect \main_sdram_bankmachine3_cmd_payload_ba 2'11 + connect \main_sdram_bankmachine3_twtpcon_valid $and$build/ls180/gateware/ls180.v:3532$205_Y + connect \main_sdram_bankmachine3_trccon_valid $and$build/ls180/gateware/ls180.v:3533$207_Y + connect \main_sdram_bankmachine3_trascon_valid $and$build/ls180/gateware/ls180.v:3534$209_Y + connect \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_din { \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_last \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_first \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_addr \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_we } + connect { \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_last \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_first \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we } \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout + connect \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_ready \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable + connect \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_we \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_valid + connect \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_first \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_first + connect \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_last \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_last + connect \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_we \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_payload_we + connect \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_in_payload_addr \main_sdram_bankmachine3_cmd_buffer_lookahead_sink_payload_addr + connect \main_sdram_bankmachine3_cmd_buffer_lookahead_source_valid \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable + connect \main_sdram_bankmachine3_cmd_buffer_lookahead_source_first \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_first + connect \main_sdram_bankmachine3_cmd_buffer_lookahead_source_last \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_last + connect \main_sdram_bankmachine3_cmd_buffer_lookahead_source_payload_we \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_we + connect \main_sdram_bankmachine3_cmd_buffer_lookahead_source_payload_addr \main_sdram_bankmachine3_cmd_buffer_lookahead_fifo_out_payload_addr + connect \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_re \main_sdram_bankmachine3_cmd_buffer_lookahead_source_ready + connect \main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_dat_w \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_din + connect \main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_we $and$build/ls180/gateware/ls180.v:3566$217_Y + connect \main_sdram_bankmachine3_cmd_buffer_lookahead_do_read $and$build/ls180/gateware/ls180.v:3567$218_Y + connect \main_sdram_bankmachine3_cmd_buffer_lookahead_rdport_adr \main_sdram_bankmachine3_cmd_buffer_lookahead_consume + connect \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_dout \main_sdram_bankmachine3_cmd_buffer_lookahead_rdport_dat_r + connect \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_writable $ne$build/ls180/gateware/ls180.v:3570$219_Y + connect \main_sdram_bankmachine3_cmd_buffer_lookahead_syncfifo3_readable $ne$build/ls180/gateware/ls180.v:3571$220_Y + connect \main_sdram_bankmachine3_cmd_buffer_sink_ready $or$build/ls180/gateware/ls180.v:3572$222_Y + connect \main_sdram_choose_req_want_cmds 1'1 + connect \main_sdram_trrdcon_valid $and$build/ls180/gateware/ls180.v:3668$233_Y + connect \main_sdram_tfawcon_valid $and$build/ls180/gateware/ls180.v:3669$239_Y + connect \main_sdram_ras_allowed $and$build/ls180/gateware/ls180.v:3670$240_Y + connect \main_sdram_tccdcon_valid $and$build/ls180/gateware/ls180.v:3671$243_Y + connect \main_sdram_cas_allowed \main_sdram_tccdcon_ready + connect \main_sdram_twtrcon_valid $and$build/ls180/gateware/ls180.v:3673$245_Y + connect \main_sdram_read_available $or$build/ls180/gateware/ls180.v:3674$252_Y + connect \main_sdram_write_available $or$build/ls180/gateware/ls180.v:3675$259_Y + connect \main_sdram_max_time0 $eq$build/ls180/gateware/ls180.v:3676$260_Y + connect \main_sdram_max_time1 $eq$build/ls180/gateware/ls180.v:3677$261_Y + connect \main_sdram_bankmachine0_refresh_req \main_sdram_cmd_valid + connect \main_sdram_bankmachine1_refresh_req \main_sdram_cmd_valid + connect \main_sdram_bankmachine2_refresh_req \main_sdram_cmd_valid + connect \main_sdram_bankmachine3_refresh_req \main_sdram_cmd_valid + connect \main_sdram_go_to_refresh $and$build/ls180/gateware/ls180.v:3682$264_Y + connect \main_sdram_interface_rdata \main_sdram_dfi_p0_rddata + connect \main_sdram_dfi_p0_wrdata \main_sdram_interface_wdata + connect \main_sdram_dfi_p0_wrdata_mask $not$build/ls180/gateware/ls180.v:3685$265_Y + connect \main_sdram_choose_cmd_request \main_sdram_choose_cmd_valids + connect \main_sdram_choose_cmd_cmd_valid \builder_comb_rhs_array_muxed0 + connect \main_sdram_choose_cmd_cmd_payload_a \builder_comb_rhs_array_muxed1 + connect \main_sdram_choose_cmd_cmd_payload_ba \builder_comb_rhs_array_muxed2 + connect \main_sdram_choose_cmd_cmd_payload_is_read \builder_comb_rhs_array_muxed3 + connect \main_sdram_choose_cmd_cmd_payload_is_write \builder_comb_rhs_array_muxed4 + connect \main_sdram_choose_cmd_cmd_payload_is_cmd \builder_comb_rhs_array_muxed5 + connect \main_sdram_choose_cmd_ce $or$build/ls180/gateware/ls180.v:3718$323_Y + connect \main_sdram_choose_req_request \main_sdram_choose_req_valids + connect \main_sdram_choose_req_cmd_valid \builder_comb_rhs_array_muxed6 + connect \main_sdram_choose_req_cmd_payload_a \builder_comb_rhs_array_muxed7 + connect \main_sdram_choose_req_cmd_payload_ba \builder_comb_rhs_array_muxed8 + connect \main_sdram_choose_req_cmd_payload_is_read \builder_comb_rhs_array_muxed9 + connect \main_sdram_choose_req_cmd_payload_is_write \builder_comb_rhs_array_muxed10 + connect \main_sdram_choose_req_cmd_payload_is_cmd \builder_comb_rhs_array_muxed11 + connect \main_sdram_choose_req_ce $or$build/ls180/gateware/ls180.v:3787$409_Y + connect \main_sdram_dfi_p0_reset_n 1'1 + connect \main_sdram_dfi_p0_cke \main_sdram_steerer0 + connect \main_sdram_dfi_p0_odt \main_sdram_steerer1 + connect \builder_roundrobin0_request $and$build/ls180/gateware/ls180.v:3864$441_Y + connect \builder_roundrobin0_ce $and$build/ls180/gateware/ls180.v:3865$444_Y + connect \main_sdram_interface_bank0_addr \builder_comb_rhs_array_muxed12 + connect \main_sdram_interface_bank0_we \builder_comb_rhs_array_muxed13 + connect \main_sdram_interface_bank0_valid \builder_comb_rhs_array_muxed14 + connect \builder_roundrobin1_request $and$build/ls180/gateware/ls180.v:3869$457_Y + connect \builder_roundrobin1_ce $and$build/ls180/gateware/ls180.v:3870$460_Y + connect \main_sdram_interface_bank1_addr \builder_comb_rhs_array_muxed15 + connect \main_sdram_interface_bank1_we \builder_comb_rhs_array_muxed16 + connect \main_sdram_interface_bank1_valid \builder_comb_rhs_array_muxed17 + connect \builder_roundrobin2_request $and$build/ls180/gateware/ls180.v:3874$473_Y + connect \builder_roundrobin2_ce $and$build/ls180/gateware/ls180.v:3875$476_Y + connect \main_sdram_interface_bank2_addr \builder_comb_rhs_array_muxed18 + connect \main_sdram_interface_bank2_we \builder_comb_rhs_array_muxed19 + connect \main_sdram_interface_bank2_valid \builder_comb_rhs_array_muxed20 + connect \builder_roundrobin3_request $and$build/ls180/gateware/ls180.v:3879$489_Y + connect \builder_roundrobin3_ce $and$build/ls180/gateware/ls180.v:3880$492_Y + connect \main_sdram_interface_bank3_addr \builder_comb_rhs_array_muxed21 + connect \main_sdram_interface_bank3_we \builder_comb_rhs_array_muxed22 + connect \main_sdram_interface_bank3_valid \builder_comb_rhs_array_muxed23 + connect \main_port_cmd_ready $or$build/ls180/gateware/ls180.v:3884$556_Y + connect \main_port_wdata_ready \builder_new_master_wdata_ready + connect \main_port_rdata_valid \builder_new_master_rdata_valid3 + connect \main_port_rdata_payload_data \main_sdram_interface_rdata + connect \builder_roundrobin0_grant 1'0 + connect \builder_roundrobin1_grant 1'0 + connect \builder_roundrobin2_grant 1'0 + connect \builder_roundrobin3_grant 1'0 + connect \main_converter_reset $not$build/ls180/gateware/ls180.v:3906$558_Y + connect \main_wb_sdram_dat_r { \main_litedram_wb_dat_r \main_converter_dat_r [31:16] } + connect \main_port_cmd_payload_addr $sub$build/ls180/gateware/ls180.v:3966$569_Y [23:0] + connect \main_port_cmd_payload_we \main_litedram_wb_we + connect \main_port_wdata_payload_data \main_litedram_wb_dat_w + connect \main_port_wdata_payload_we \main_litedram_wb_sel + connect \main_litedram_wb_dat_r \main_port_rdata_payload_data + connect \main_port_flush $not$build/ls180/gateware/ls180.v:3971$570_Y + connect \main_port_cmd_last $not$build/ls180/gateware/ls180.v:3972$571_Y + connect \main_port_cmd_valid $and$build/ls180/gateware/ls180.v:3973$574_Y + connect \main_port_wdata_valid $and$build/ls180/gateware/ls180.v:3974$578_Y + connect \main_port_rdata_ready $and$build/ls180/gateware/ls180.v:3975$581_Y + connect \main_litedram_wb_ack $and$build/ls180/gateware/ls180.v:3976$586_Y + connect \main_ack_cmd $or$build/ls180/gateware/ls180.v:3977$588_Y + connect \main_ack_wdata $or$build/ls180/gateware/ls180.v:3978$590_Y + connect \main_ack_rdata $and$build/ls180/gateware/ls180.v:3979$591_Y + connect \main_start0 \main_start1 + connect \main_length0 \main_length1 + connect \main_mosi \main_mosi_storage + connect \main_done1 \main_done0 + connect \main_miso_status \main_miso + connect \main_cs \main_cs_storage + connect \main_loopback \main_loopback_storage + connect \main_clk_rise $eq$build/ls180/gateware/ls180.v:3987$593_Y + connect \main_clk_fall $eq$build/ls180/gateware/ls180.v:3988$595_Y + connect \libresocsim_status 1'0 + connect \libresocsim_sdpads_clk $or$build/ls180/gateware/ls180.v:4039$603_Y + connect \libresocsim_sdpads_cmd_oe $or$build/ls180/gateware/ls180.v:4040$607_Y + connect \libresocsim_sdpads_cmd_o $or$build/ls180/gateware/ls180.v:4041$611_Y + connect \libresocsim_sdpads_data_oe $or$build/ls180/gateware/ls180.v:4042$615_Y + connect \libresocsim_sdpads_data_o $or$build/ls180/gateware/ls180.v:4043$619_Y + connect \libresocsim_init_pads_out_ready \libresocsim_clocker_ce + connect \libresocsim_cmdw_pads_out_ready \libresocsim_clocker_ce + connect \libresocsim_cmdr_pads_out_ready \libresocsim_clocker_ce + connect \libresocsim_dataw_pads_out_ready \libresocsim_clocker_ce + connect \libresocsim_datar_pads_out_ready \libresocsim_clocker_ce + connect \libresocsim_init_pads_in_valid \libresocsim_clocker_ce + connect \libresocsim_init_pads_in_payload_cmd_i \libresocsim_sdpads_cmd_i + connect \libresocsim_init_pads_in_payload_data_i \libresocsim_sdpads_data_i + connect \libresocsim_cmdw_pads_in_valid \libresocsim_clocker_ce + connect \libresocsim_cmdw_pads_in_payload_cmd_i \libresocsim_sdpads_cmd_i + connect \libresocsim_cmdw_pads_in_payload_data_i \libresocsim_sdpads_data_i + connect \libresocsim_cmdr_pads_in_pads_in_valid \libresocsim_clocker_ce + connect \libresocsim_cmdr_pads_in_pads_in_payload_cmd_i \libresocsim_sdpads_cmd_i + connect \libresocsim_cmdr_pads_in_pads_in_payload_data_i \libresocsim_sdpads_data_i + connect \libresocsim_dataw_pads_in_valid \libresocsim_clocker_ce + connect \libresocsim_dataw_pads_in_payload_cmd_i \libresocsim_sdpads_cmd_i + connect \libresocsim_dataw_pads_in_payload_data_i \libresocsim_sdpads_data_i + connect \libresocsim_datar_pads_in_pads_in_valid \libresocsim_clocker_ce + connect \libresocsim_datar_pads_in_pads_in_payload_cmd_i \libresocsim_sdpads_cmd_i + connect \libresocsim_datar_pads_in_pads_in_payload_data_i \libresocsim_sdpads_data_i + connect \libresocsim_clocker_stop $or$build/ls180/gateware/ls180.v:4064$620_Y + connect \libresocsim_clocker_ce $and$build/ls180/gateware/ls180.v:4094$623_Y + connect \libresocsim_cmdr_cmdr_pads_in_valid \libresocsim_cmdr_pads_in_pads_in_valid + connect \libresocsim_cmdr_pads_in_pads_in_ready \libresocsim_cmdr_cmdr_pads_in_ready + connect \libresocsim_cmdr_cmdr_pads_in_first \libresocsim_cmdr_pads_in_pads_in_first + connect \libresocsim_cmdr_cmdr_pads_in_last \libresocsim_cmdr_pads_in_pads_in_last + connect \libresocsim_cmdr_cmdr_pads_in_payload_clk \libresocsim_cmdr_pads_in_pads_in_payload_clk + connect \libresocsim_cmdr_cmdr_pads_in_payload_cmd_i \libresocsim_cmdr_pads_in_pads_in_payload_cmd_i + connect \libresocsim_cmdr_cmdr_pads_in_payload_cmd_o \libresocsim_cmdr_pads_in_pads_in_payload_cmd_o + connect \libresocsim_cmdr_cmdr_pads_in_payload_cmd_oe \libresocsim_cmdr_pads_in_pads_in_payload_cmd_oe + connect \libresocsim_cmdr_cmdr_pads_in_payload_data_i \libresocsim_cmdr_pads_in_pads_in_payload_data_i + connect \libresocsim_cmdr_cmdr_pads_in_payload_data_o \libresocsim_cmdr_pads_in_pads_in_payload_data_o + connect \libresocsim_cmdr_cmdr_pads_in_payload_data_oe \libresocsim_cmdr_pads_in_pads_in_payload_data_oe + connect \libresocsim_cmdr_cmdr_start $eq$build/ls180/gateware/ls180.v:4217$633_Y + connect \libresocsim_cmdr_cmdr_converter_sink_valid $and$build/ls180/gateware/ls180.v:4218$635_Y + connect \libresocsim_cmdr_cmdr_converter_sink_payload_data \libresocsim_cmdr_cmdr_pads_in_payload_cmd_i + connect \libresocsim_cmdr_cmdr_buf_sink_valid \libresocsim_cmdr_cmdr_source_source_valid1 + connect \libresocsim_cmdr_cmdr_source_source_ready1 \libresocsim_cmdr_cmdr_buf_sink_ready + connect \libresocsim_cmdr_cmdr_buf_sink_first \libresocsim_cmdr_cmdr_source_source_first1 + connect \libresocsim_cmdr_cmdr_buf_sink_last \libresocsim_cmdr_cmdr_source_source_last1 + connect \libresocsim_cmdr_cmdr_buf_sink_payload_data \libresocsim_cmdr_cmdr_source_source_payload_data1 + connect \libresocsim_cmdr_cmdr_source_source_valid0 \libresocsim_cmdr_cmdr_buf_source_valid + connect \libresocsim_cmdr_cmdr_buf_source_ready \libresocsim_cmdr_cmdr_source_source_ready0 + connect \libresocsim_cmdr_cmdr_source_source_first0 \libresocsim_cmdr_cmdr_buf_source_first + connect \libresocsim_cmdr_cmdr_source_source_last0 \libresocsim_cmdr_cmdr_buf_source_last + connect \libresocsim_cmdr_cmdr_source_source_payload_data0 \libresocsim_cmdr_cmdr_buf_source_payload_data + connect \libresocsim_cmdr_cmdr_source_source_valid1 \libresocsim_cmdr_cmdr_converter_source_valid + connect \libresocsim_cmdr_cmdr_converter_source_ready \libresocsim_cmdr_cmdr_source_source_ready1 + connect \libresocsim_cmdr_cmdr_source_source_first1 \libresocsim_cmdr_cmdr_converter_source_first + connect \libresocsim_cmdr_cmdr_source_source_last1 \libresocsim_cmdr_cmdr_converter_source_last + connect \libresocsim_cmdr_cmdr_source_source_payload_data1 \libresocsim_cmdr_cmdr_converter_source_payload_data + connect \libresocsim_cmdr_cmdr_converter_sink_ready $or$build/ls180/gateware/ls180.v:4235$637_Y + connect \libresocsim_cmdr_cmdr_converter_source_valid \libresocsim_cmdr_cmdr_converter_strobe_all + connect \libresocsim_cmdr_cmdr_converter_load_part $and$build/ls180/gateware/ls180.v:4237$638_Y + connect \libresocsim_cmdr_cmdr_buf_sink_ready $or$build/ls180/gateware/ls180.v:4238$640_Y + connect \libresocsim_dataw_crcr_pads_in_valid \libresocsim_dataw_pads_in_pads_in_valid + connect \libresocsim_dataw_pads_in_pads_in_ready \libresocsim_dataw_crcr_pads_in_ready + connect \libresocsim_dataw_crcr_pads_in_first \libresocsim_dataw_pads_in_pads_in_first + connect \libresocsim_dataw_crcr_pads_in_last \libresocsim_dataw_pads_in_pads_in_last + connect \libresocsim_dataw_crcr_pads_in_payload_clk \libresocsim_dataw_pads_in_pads_in_payload_clk + connect \libresocsim_dataw_crcr_pads_in_payload_cmd_i \libresocsim_dataw_pads_in_pads_in_payload_cmd_i + connect \libresocsim_dataw_crcr_pads_in_payload_cmd_o \libresocsim_dataw_pads_in_pads_in_payload_cmd_o + connect \libresocsim_dataw_crcr_pads_in_payload_cmd_oe \libresocsim_dataw_pads_in_pads_in_payload_cmd_oe + connect \libresocsim_dataw_crcr_pads_in_payload_data_i \libresocsim_dataw_pads_in_pads_in_payload_data_i + connect \libresocsim_dataw_crcr_pads_in_payload_data_o \libresocsim_dataw_pads_in_pads_in_payload_data_o + connect \libresocsim_dataw_crcr_pads_in_payload_data_oe \libresocsim_dataw_pads_in_pads_in_payload_data_oe + connect \libresocsim_dataw_crcr_start $eq$build/ls180/gateware/ls180.v:4344$655_Y + connect \libresocsim_dataw_crcr_converter_sink_valid $and$build/ls180/gateware/ls180.v:4345$656_Y + connect \libresocsim_dataw_crcr_converter_sink_payload_data \libresocsim_dataw_crcr_pads_in_payload_data_i [0] + connect \libresocsim_dataw_crcr_buf_sink_valid \libresocsim_dataw_crcr_source_source_valid1 + connect \libresocsim_dataw_crcr_source_source_ready1 \libresocsim_dataw_crcr_buf_sink_ready + connect \libresocsim_dataw_crcr_buf_sink_first \libresocsim_dataw_crcr_source_source_first1 + connect \libresocsim_dataw_crcr_buf_sink_last \libresocsim_dataw_crcr_source_source_last1 + connect \libresocsim_dataw_crcr_buf_sink_payload_data \libresocsim_dataw_crcr_source_source_payload_data1 + connect \libresocsim_dataw_crcr_source_source_valid0 \libresocsim_dataw_crcr_buf_source_valid + connect \libresocsim_dataw_crcr_buf_source_ready \libresocsim_dataw_crcr_source_source_ready0 + connect \libresocsim_dataw_crcr_source_source_first0 \libresocsim_dataw_crcr_buf_source_first + connect \libresocsim_dataw_crcr_source_source_last0 \libresocsim_dataw_crcr_buf_source_last + connect \libresocsim_dataw_crcr_source_source_payload_data0 \libresocsim_dataw_crcr_buf_source_payload_data + connect \libresocsim_dataw_crcr_source_source_valid1 \libresocsim_dataw_crcr_converter_source_valid + connect \libresocsim_dataw_crcr_converter_source_ready \libresocsim_dataw_crcr_source_source_ready1 + connect \libresocsim_dataw_crcr_source_source_first1 \libresocsim_dataw_crcr_converter_source_first + connect \libresocsim_dataw_crcr_source_source_last1 \libresocsim_dataw_crcr_converter_source_last + connect \libresocsim_dataw_crcr_source_source_payload_data1 \libresocsim_dataw_crcr_converter_source_payload_data + connect \libresocsim_dataw_crcr_converter_sink_ready $or$build/ls180/gateware/ls180.v:4362$658_Y + connect \libresocsim_dataw_crcr_converter_source_valid \libresocsim_dataw_crcr_converter_strobe_all + connect \libresocsim_dataw_crcr_converter_load_part $and$build/ls180/gateware/ls180.v:4364$659_Y + connect \libresocsim_dataw_crcr_buf_sink_ready $or$build/ls180/gateware/ls180.v:4365$661_Y + connect \libresocsim_datar_datar_pads_in_valid \libresocsim_datar_pads_in_pads_in_valid + connect \libresocsim_datar_pads_in_pads_in_ready \libresocsim_datar_datar_pads_in_ready + connect \libresocsim_datar_datar_pads_in_first \libresocsim_datar_pads_in_pads_in_first + connect \libresocsim_datar_datar_pads_in_last \libresocsim_datar_pads_in_pads_in_last + connect \libresocsim_datar_datar_pads_in_payload_clk \libresocsim_datar_pads_in_pads_in_payload_clk + connect \libresocsim_datar_datar_pads_in_payload_cmd_i \libresocsim_datar_pads_in_pads_in_payload_cmd_i + connect \libresocsim_datar_datar_pads_in_payload_cmd_o \libresocsim_datar_pads_in_pads_in_payload_cmd_o + connect \libresocsim_datar_datar_pads_in_payload_cmd_oe \libresocsim_datar_pads_in_pads_in_payload_cmd_oe + connect \libresocsim_datar_datar_pads_in_payload_data_i \libresocsim_datar_pads_in_pads_in_payload_data_i + connect \libresocsim_datar_datar_pads_in_payload_data_o \libresocsim_datar_pads_in_pads_in_payload_data_o + connect \libresocsim_datar_datar_pads_in_payload_data_oe \libresocsim_datar_pads_in_pads_in_payload_data_oe + connect \libresocsim_datar_datar_start $eq$build/ls180/gateware/ls180.v:4478$670_Y + connect \libresocsim_datar_datar_converter_sink_valid $and$build/ls180/gateware/ls180.v:4479$671_Y + connect \libresocsim_datar_datar_converter_sink_payload_data \libresocsim_datar_datar_pads_in_payload_data_i + connect \libresocsim_datar_datar_buf_sink_valid \libresocsim_datar_datar_source_source_valid1 + connect \libresocsim_datar_datar_source_source_ready1 \libresocsim_datar_datar_buf_sink_ready + connect \libresocsim_datar_datar_buf_sink_first \libresocsim_datar_datar_source_source_first1 + connect \libresocsim_datar_datar_buf_sink_last \libresocsim_datar_datar_source_source_last1 + connect \libresocsim_datar_datar_buf_sink_payload_data \libresocsim_datar_datar_source_source_payload_data1 + connect \libresocsim_datar_datar_source_source_valid0 \libresocsim_datar_datar_buf_source_valid + connect \libresocsim_datar_datar_buf_source_ready \libresocsim_datar_datar_source_source_ready0 + connect \libresocsim_datar_datar_source_source_first0 \libresocsim_datar_datar_buf_source_first + connect \libresocsim_datar_datar_source_source_last0 \libresocsim_datar_datar_buf_source_last + connect \libresocsim_datar_datar_source_source_payload_data0 \libresocsim_datar_datar_buf_source_payload_data + connect \libresocsim_datar_datar_source_source_valid1 \libresocsim_datar_datar_converter_source_valid + connect \libresocsim_datar_datar_converter_source_ready \libresocsim_datar_datar_source_source_ready1 + connect \libresocsim_datar_datar_source_source_first1 \libresocsim_datar_datar_converter_source_first + connect \libresocsim_datar_datar_source_source_last1 \libresocsim_datar_datar_converter_source_last + connect \libresocsim_datar_datar_source_source_payload_data1 \libresocsim_datar_datar_converter_source_payload_data + connect \libresocsim_datar_datar_converter_sink_ready $or$build/ls180/gateware/ls180.v:4496$673_Y + connect \libresocsim_datar_datar_converter_source_valid \libresocsim_datar_datar_converter_strobe_all + connect \libresocsim_datar_datar_converter_load_part $and$build/ls180/gateware/ls180.v:4498$674_Y + connect \libresocsim_datar_datar_buf_sink_ready $or$build/ls180/gateware/ls180.v:4499$676_Y + connect \libresocsim_sdcore_crc16_inserter_sink_valid \libresocsim_sdcore_sink_sink_valid + connect \libresocsim_sdcore_sink_sink_ready \libresocsim_sdcore_crc16_inserter_sink_ready + connect \libresocsim_sdcore_crc16_inserter_sink_first \libresocsim_sdcore_sink_sink_first + connect \libresocsim_sdcore_crc16_inserter_sink_last \libresocsim_sdcore_sink_sink_last + connect \libresocsim_sdcore_crc16_inserter_sink_payload_data \libresocsim_sdcore_sink_sink_payload_data + connect \libresocsim_sdcore_source_source_valid \libresocsim_sdcore_crc16_checker_source_valid + connect \libresocsim_sdcore_crc16_checker_source_ready \libresocsim_sdcore_source_source_ready + connect \libresocsim_sdcore_source_source_first \libresocsim_sdcore_crc16_checker_source_first + connect \libresocsim_sdcore_source_source_last \libresocsim_sdcore_crc16_checker_source_last + connect \libresocsim_sdcore_source_source_payload_data \libresocsim_sdcore_crc16_checker_source_payload_data + connect \libresocsim_sdcore_cmd_type \libresocsim_sdcore_cmd_command_storage [1:0] + connect \libresocsim_sdcore_data_type \libresocsim_sdcore_cmd_command_storage [6:5] + connect \libresocsim_sdcore_cmd_event_status { 1'0 \libresocsim_sdcore_cmd_timeout \libresocsim_sdcore_cmd_error \libresocsim_sdcore_cmd_done } + connect \libresocsim_sdcore_data_event_status { $not$build/ls180/gateware/ls180.v:4615$691_Y \libresocsim_sdcore_data_timeout \libresocsim_sdcore_data_error \libresocsim_sdcore_data_done } + connect \libresocsim_sdcore_crc7_inserter_val { 2'01 \libresocsim_sdcore_cmd_command_storage [13:8] \libresocsim_sdcore_cmd_argument_storage } + connect \libresocsim_sdcore_crc7_inserter_clr 1'1 + connect \libresocsim_sdcore_crc7_inserter_enable 1'1 + connect \libresocsim_sdcore_crc7_inserter_crcreg1 { \libresocsim_sdcore_crc7_inserter_crcreg0 [5:3] $xor$build/ls180/gateware/ls180.v:4619$694_Y \libresocsim_sdcore_crc7_inserter_crcreg0 [1:0] $xor$build/ls180/gateware/ls180.v:4619$692_Y } + connect \libresocsim_sdcore_crc7_inserter_crcreg2 { \libresocsim_sdcore_crc7_inserter_crcreg1 [5:3] $xor$build/ls180/gateware/ls180.v:4620$697_Y \libresocsim_sdcore_crc7_inserter_crcreg1 [1:0] $xor$build/ls180/gateware/ls180.v:4620$695_Y } + connect \libresocsim_sdcore_crc7_inserter_crcreg3 { \libresocsim_sdcore_crc7_inserter_crcreg2 [5:3] $xor$build/ls180/gateware/ls180.v:4621$700_Y \libresocsim_sdcore_crc7_inserter_crcreg2 [1:0] $xor$build/ls180/gateware/ls180.v:4621$698_Y } + connect \libresocsim_sdcore_crc7_inserter_crcreg4 { \libresocsim_sdcore_crc7_inserter_crcreg3 [5:3] $xor$build/ls180/gateware/ls180.v:4622$703_Y \libresocsim_sdcore_crc7_inserter_crcreg3 [1:0] $xor$build/ls180/gateware/ls180.v:4622$701_Y } + connect \libresocsim_sdcore_crc7_inserter_crcreg5 { \libresocsim_sdcore_crc7_inserter_crcreg4 [5:3] $xor$build/ls180/gateware/ls180.v:4623$706_Y \libresocsim_sdcore_crc7_inserter_crcreg4 [1:0] $xor$build/ls180/gateware/ls180.v:4623$704_Y } + connect \libresocsim_sdcore_crc7_inserter_crcreg6 { \libresocsim_sdcore_crc7_inserter_crcreg5 [5:3] $xor$build/ls180/gateware/ls180.v:4624$709_Y \libresocsim_sdcore_crc7_inserter_crcreg5 [1:0] $xor$build/ls180/gateware/ls180.v:4624$707_Y } + connect \libresocsim_sdcore_crc7_inserter_crcreg7 { \libresocsim_sdcore_crc7_inserter_crcreg6 [5:3] $xor$build/ls180/gateware/ls180.v:4625$712_Y \libresocsim_sdcore_crc7_inserter_crcreg6 [1:0] $xor$build/ls180/gateware/ls180.v:4625$710_Y } + connect \libresocsim_sdcore_crc7_inserter_crcreg8 { \libresocsim_sdcore_crc7_inserter_crcreg7 [5:3] $xor$build/ls180/gateware/ls180.v:4626$715_Y \libresocsim_sdcore_crc7_inserter_crcreg7 [1:0] $xor$build/ls180/gateware/ls180.v:4626$713_Y } + connect \libresocsim_sdcore_crc7_inserter_crcreg9 { \libresocsim_sdcore_crc7_inserter_crcreg8 [5:3] $xor$build/ls180/gateware/ls180.v:4627$718_Y \libresocsim_sdcore_crc7_inserter_crcreg8 [1:0] $xor$build/ls180/gateware/ls180.v:4627$716_Y } + connect \libresocsim_sdcore_crc7_inserter_crcreg10 { \libresocsim_sdcore_crc7_inserter_crcreg9 [5:3] $xor$build/ls180/gateware/ls180.v:4628$721_Y \libresocsim_sdcore_crc7_inserter_crcreg9 [1:0] $xor$build/ls180/gateware/ls180.v:4628$719_Y } + connect \libresocsim_sdcore_crc7_inserter_crcreg11 { \libresocsim_sdcore_crc7_inserter_crcreg10 [5:3] $xor$build/ls180/gateware/ls180.v:4629$724_Y \libresocsim_sdcore_crc7_inserter_crcreg10 [1:0] $xor$build/ls180/gateware/ls180.v:4629$722_Y } + connect \libresocsim_sdcore_crc7_inserter_crcreg12 { \libresocsim_sdcore_crc7_inserter_crcreg11 [5:3] $xor$build/ls180/gateware/ls180.v:4630$727_Y \libresocsim_sdcore_crc7_inserter_crcreg11 [1:0] $xor$build/ls180/gateware/ls180.v:4630$725_Y } + connect \libresocsim_sdcore_crc7_inserter_crcreg13 { \libresocsim_sdcore_crc7_inserter_crcreg12 [5:3] $xor$build/ls180/gateware/ls180.v:4631$730_Y \libresocsim_sdcore_crc7_inserter_crcreg12 [1:0] $xor$build/ls180/gateware/ls180.v:4631$728_Y } + connect \libresocsim_sdcore_crc7_inserter_crcreg14 { \libresocsim_sdcore_crc7_inserter_crcreg13 [5:3] $xor$build/ls180/gateware/ls180.v:4632$733_Y \libresocsim_sdcore_crc7_inserter_crcreg13 [1:0] $xor$build/ls180/gateware/ls180.v:4632$731_Y } + connect \libresocsim_sdcore_crc7_inserter_crcreg15 { \libresocsim_sdcore_crc7_inserter_crcreg14 [5:3] $xor$build/ls180/gateware/ls180.v:4633$736_Y \libresocsim_sdcore_crc7_inserter_crcreg14 [1:0] $xor$build/ls180/gateware/ls180.v:4633$734_Y } + connect \libresocsim_sdcore_crc7_inserter_crcreg16 { \libresocsim_sdcore_crc7_inserter_crcreg15 [5:3] $xor$build/ls180/gateware/ls180.v:4634$739_Y \libresocsim_sdcore_crc7_inserter_crcreg15 [1:0] $xor$build/ls180/gateware/ls180.v:4634$737_Y } + connect \libresocsim_sdcore_crc7_inserter_crcreg17 { \libresocsim_sdcore_crc7_inserter_crcreg16 [5:3] $xor$build/ls180/gateware/ls180.v:4635$742_Y \libresocsim_sdcore_crc7_inserter_crcreg16 [1:0] $xor$build/ls180/gateware/ls180.v:4635$740_Y } + connect \libresocsim_sdcore_crc7_inserter_crcreg18 { \libresocsim_sdcore_crc7_inserter_crcreg17 [5:3] $xor$build/ls180/gateware/ls180.v:4636$745_Y \libresocsim_sdcore_crc7_inserter_crcreg17 [1:0] $xor$build/ls180/gateware/ls180.v:4636$743_Y } + connect \libresocsim_sdcore_crc7_inserter_crcreg19 { \libresocsim_sdcore_crc7_inserter_crcreg18 [5:3] $xor$build/ls180/gateware/ls180.v:4637$748_Y \libresocsim_sdcore_crc7_inserter_crcreg18 [1:0] $xor$build/ls180/gateware/ls180.v:4637$746_Y } + connect \libresocsim_sdcore_crc7_inserter_crcreg20 { \libresocsim_sdcore_crc7_inserter_crcreg19 [5:3] $xor$build/ls180/gateware/ls180.v:4638$751_Y \libresocsim_sdcore_crc7_inserter_crcreg19 [1:0] $xor$build/ls180/gateware/ls180.v:4638$749_Y } + connect \libresocsim_sdcore_crc7_inserter_crcreg21 { \libresocsim_sdcore_crc7_inserter_crcreg20 [5:3] $xor$build/ls180/gateware/ls180.v:4639$754_Y \libresocsim_sdcore_crc7_inserter_crcreg20 [1:0] $xor$build/ls180/gateware/ls180.v:4639$752_Y } + connect \libresocsim_sdcore_crc7_inserter_crcreg22 { \libresocsim_sdcore_crc7_inserter_crcreg21 [5:3] $xor$build/ls180/gateware/ls180.v:4640$757_Y \libresocsim_sdcore_crc7_inserter_crcreg21 [1:0] $xor$build/ls180/gateware/ls180.v:4640$755_Y } + connect \libresocsim_sdcore_crc7_inserter_crcreg23 { \libresocsim_sdcore_crc7_inserter_crcreg22 [5:3] $xor$build/ls180/gateware/ls180.v:4641$760_Y \libresocsim_sdcore_crc7_inserter_crcreg22 [1:0] $xor$build/ls180/gateware/ls180.v:4641$758_Y } + connect \libresocsim_sdcore_crc7_inserter_crcreg24 { \libresocsim_sdcore_crc7_inserter_crcreg23 [5:3] $xor$build/ls180/gateware/ls180.v:4642$763_Y \libresocsim_sdcore_crc7_inserter_crcreg23 [1:0] $xor$build/ls180/gateware/ls180.v:4642$761_Y } + connect \libresocsim_sdcore_crc7_inserter_crcreg25 { \libresocsim_sdcore_crc7_inserter_crcreg24 [5:3] $xor$build/ls180/gateware/ls180.v:4643$766_Y \libresocsim_sdcore_crc7_inserter_crcreg24 [1:0] $xor$build/ls180/gateware/ls180.v:4643$764_Y } + connect \libresocsim_sdcore_crc7_inserter_crcreg26 { \libresocsim_sdcore_crc7_inserter_crcreg25 [5:3] $xor$build/ls180/gateware/ls180.v:4644$769_Y \libresocsim_sdcore_crc7_inserter_crcreg25 [1:0] $xor$build/ls180/gateware/ls180.v:4644$767_Y } + connect \libresocsim_sdcore_crc7_inserter_crcreg27 { \libresocsim_sdcore_crc7_inserter_crcreg26 [5:3] $xor$build/ls180/gateware/ls180.v:4645$772_Y \libresocsim_sdcore_crc7_inserter_crcreg26 [1:0] $xor$build/ls180/gateware/ls180.v:4645$770_Y } + connect \libresocsim_sdcore_crc7_inserter_crcreg28 { \libresocsim_sdcore_crc7_inserter_crcreg27 [5:3] $xor$build/ls180/gateware/ls180.v:4646$775_Y \libresocsim_sdcore_crc7_inserter_crcreg27 [1:0] $xor$build/ls180/gateware/ls180.v:4646$773_Y } + connect \libresocsim_sdcore_crc7_inserter_crcreg29 { \libresocsim_sdcore_crc7_inserter_crcreg28 [5:3] $xor$build/ls180/gateware/ls180.v:4647$778_Y \libresocsim_sdcore_crc7_inserter_crcreg28 [1:0] $xor$build/ls180/gateware/ls180.v:4647$776_Y } + connect \libresocsim_sdcore_crc7_inserter_crcreg30 { \libresocsim_sdcore_crc7_inserter_crcreg29 [5:3] $xor$build/ls180/gateware/ls180.v:4648$781_Y \libresocsim_sdcore_crc7_inserter_crcreg29 [1:0] $xor$build/ls180/gateware/ls180.v:4648$779_Y } + connect \libresocsim_sdcore_crc7_inserter_crcreg31 { \libresocsim_sdcore_crc7_inserter_crcreg30 [5:3] $xor$build/ls180/gateware/ls180.v:4649$784_Y \libresocsim_sdcore_crc7_inserter_crcreg30 [1:0] $xor$build/ls180/gateware/ls180.v:4649$782_Y } + connect \libresocsim_sdcore_crc7_inserter_crcreg32 { \libresocsim_sdcore_crc7_inserter_crcreg31 [5:3] $xor$build/ls180/gateware/ls180.v:4650$787_Y \libresocsim_sdcore_crc7_inserter_crcreg31 [1:0] $xor$build/ls180/gateware/ls180.v:4650$785_Y } + connect \libresocsim_sdcore_crc7_inserter_crcreg33 { \libresocsim_sdcore_crc7_inserter_crcreg32 [5:3] $xor$build/ls180/gateware/ls180.v:4651$790_Y \libresocsim_sdcore_crc7_inserter_crcreg32 [1:0] $xor$build/ls180/gateware/ls180.v:4651$788_Y } + connect \libresocsim_sdcore_crc7_inserter_crcreg34 { \libresocsim_sdcore_crc7_inserter_crcreg33 [5:3] $xor$build/ls180/gateware/ls180.v:4652$793_Y \libresocsim_sdcore_crc7_inserter_crcreg33 [1:0] $xor$build/ls180/gateware/ls180.v:4652$791_Y } + connect \libresocsim_sdcore_crc7_inserter_crcreg35 { \libresocsim_sdcore_crc7_inserter_crcreg34 [5:3] $xor$build/ls180/gateware/ls180.v:4653$796_Y \libresocsim_sdcore_crc7_inserter_crcreg34 [1:0] $xor$build/ls180/gateware/ls180.v:4653$794_Y } + connect \libresocsim_sdcore_crc7_inserter_crcreg36 { \libresocsim_sdcore_crc7_inserter_crcreg35 [5:3] $xor$build/ls180/gateware/ls180.v:4654$799_Y \libresocsim_sdcore_crc7_inserter_crcreg35 [1:0] $xor$build/ls180/gateware/ls180.v:4654$797_Y } + connect \libresocsim_sdcore_crc7_inserter_crcreg37 { \libresocsim_sdcore_crc7_inserter_crcreg36 [5:3] $xor$build/ls180/gateware/ls180.v:4655$802_Y \libresocsim_sdcore_crc7_inserter_crcreg36 [1:0] $xor$build/ls180/gateware/ls180.v:4655$800_Y } + connect \libresocsim_sdcore_crc7_inserter_crcreg38 { \libresocsim_sdcore_crc7_inserter_crcreg37 [5:3] $xor$build/ls180/gateware/ls180.v:4656$805_Y \libresocsim_sdcore_crc7_inserter_crcreg37 [1:0] $xor$build/ls180/gateware/ls180.v:4656$803_Y } + connect \libresocsim_sdcore_crc7_inserter_crcreg39 { \libresocsim_sdcore_crc7_inserter_crcreg38 [5:3] $xor$build/ls180/gateware/ls180.v:4657$808_Y \libresocsim_sdcore_crc7_inserter_crcreg38 [1:0] $xor$build/ls180/gateware/ls180.v:4657$806_Y } + connect \libresocsim_sdcore_crc7_inserter_crcreg40 { \libresocsim_sdcore_crc7_inserter_crcreg39 [5:3] $xor$build/ls180/gateware/ls180.v:4658$811_Y \libresocsim_sdcore_crc7_inserter_crcreg39 [1:0] $xor$build/ls180/gateware/ls180.v:4658$809_Y } + connect \libresocsim_sdcore_crc16_inserter_crc0_val { \libresocsim_sdcore_crc16_inserter_sink_payload_data [4] \libresocsim_sdcore_crc16_inserter_sink_payload_data [0] } + connect \libresocsim_sdcore_crc16_inserter_crc0_clr $and$build/ls180/gateware/ls180.v:4668$814_Y + connect \libresocsim_sdcore_crc16_inserter_crc0_enable $and$build/ls180/gateware/ls180.v:4669$815_Y + connect \libresocsim_sdcore_crc16_inserter_crc1_val { \libresocsim_sdcore_crc16_inserter_sink_payload_data [5] \libresocsim_sdcore_crc16_inserter_sink_payload_data [1] } + connect \libresocsim_sdcore_crc16_inserter_crc1_clr $and$build/ls180/gateware/ls180.v:4671$817_Y + connect \libresocsim_sdcore_crc16_inserter_crc1_enable $and$build/ls180/gateware/ls180.v:4672$818_Y + connect \libresocsim_sdcore_crc16_inserter_crc2_val { \libresocsim_sdcore_crc16_inserter_sink_payload_data [6] \libresocsim_sdcore_crc16_inserter_sink_payload_data [2] } + connect \libresocsim_sdcore_crc16_inserter_crc2_clr $and$build/ls180/gateware/ls180.v:4674$820_Y + connect \libresocsim_sdcore_crc16_inserter_crc2_enable $and$build/ls180/gateware/ls180.v:4675$821_Y + connect \libresocsim_sdcore_crc16_inserter_crc3_val { \libresocsim_sdcore_crc16_inserter_sink_payload_data [7] \libresocsim_sdcore_crc16_inserter_sink_payload_data [3] } + connect \libresocsim_sdcore_crc16_inserter_crc3_clr $and$build/ls180/gateware/ls180.v:4677$823_Y + connect \libresocsim_sdcore_crc16_inserter_crc3_enable $and$build/ls180/gateware/ls180.v:4678$824_Y + connect \libresocsim_sdcore_crc16_inserter_crc0_crcreg1 { \libresocsim_sdcore_crc16_inserter_crc0_crcreg0 [14:12] $xor$build/ls180/gateware/ls180.v:4679$829_Y \libresocsim_sdcore_crc16_inserter_crc0_crcreg0 [10:5] $xor$build/ls180/gateware/ls180.v:4679$827_Y \libresocsim_sdcore_crc16_inserter_crc0_crcreg0 [3:0] $xor$build/ls180/gateware/ls180.v:4679$825_Y } + connect \libresocsim_sdcore_crc16_inserter_crc0_crcreg2 { \libresocsim_sdcore_crc16_inserter_crc0_crcreg1 [14:12] $xor$build/ls180/gateware/ls180.v:4680$834_Y \libresocsim_sdcore_crc16_inserter_crc0_crcreg1 [10:5] $xor$build/ls180/gateware/ls180.v:4680$832_Y \libresocsim_sdcore_crc16_inserter_crc0_crcreg1 [3:0] $xor$build/ls180/gateware/ls180.v:4680$830_Y } + connect \libresocsim_sdcore_crc16_inserter_crc1_crcreg1 { \libresocsim_sdcore_crc16_inserter_crc1_crcreg0 [14:12] $xor$build/ls180/gateware/ls180.v:4689$840_Y \libresocsim_sdcore_crc16_inserter_crc1_crcreg0 [10:5] $xor$build/ls180/gateware/ls180.v:4689$838_Y \libresocsim_sdcore_crc16_inserter_crc1_crcreg0 [3:0] $xor$build/ls180/gateware/ls180.v:4689$836_Y } + connect \libresocsim_sdcore_crc16_inserter_crc1_crcreg2 { \libresocsim_sdcore_crc16_inserter_crc1_crcreg1 [14:12] $xor$build/ls180/gateware/ls180.v:4690$845_Y \libresocsim_sdcore_crc16_inserter_crc1_crcreg1 [10:5] $xor$build/ls180/gateware/ls180.v:4690$843_Y \libresocsim_sdcore_crc16_inserter_crc1_crcreg1 [3:0] $xor$build/ls180/gateware/ls180.v:4690$841_Y } + connect \libresocsim_sdcore_crc16_inserter_crc2_crcreg1 { \libresocsim_sdcore_crc16_inserter_crc2_crcreg0 [14:12] $xor$build/ls180/gateware/ls180.v:4699$851_Y \libresocsim_sdcore_crc16_inserter_crc2_crcreg0 [10:5] $xor$build/ls180/gateware/ls180.v:4699$849_Y \libresocsim_sdcore_crc16_inserter_crc2_crcreg0 [3:0] $xor$build/ls180/gateware/ls180.v:4699$847_Y } + connect \libresocsim_sdcore_crc16_inserter_crc2_crcreg2 { \libresocsim_sdcore_crc16_inserter_crc2_crcreg1 [14:12] $xor$build/ls180/gateware/ls180.v:4700$856_Y \libresocsim_sdcore_crc16_inserter_crc2_crcreg1 [10:5] $xor$build/ls180/gateware/ls180.v:4700$854_Y \libresocsim_sdcore_crc16_inserter_crc2_crcreg1 [3:0] $xor$build/ls180/gateware/ls180.v:4700$852_Y } + connect \libresocsim_sdcore_crc16_inserter_crc3_crcreg1 { \libresocsim_sdcore_crc16_inserter_crc3_crcreg0 [14:12] $xor$build/ls180/gateware/ls180.v:4709$862_Y \libresocsim_sdcore_crc16_inserter_crc3_crcreg0 [10:5] $xor$build/ls180/gateware/ls180.v:4709$860_Y \libresocsim_sdcore_crc16_inserter_crc3_crcreg0 [3:0] $xor$build/ls180/gateware/ls180.v:4709$858_Y } + connect \libresocsim_sdcore_crc16_inserter_crc3_crcreg2 { \libresocsim_sdcore_crc16_inserter_crc3_crcreg1 [14:12] $xor$build/ls180/gateware/ls180.v:4710$867_Y \libresocsim_sdcore_crc16_inserter_crc3_crcreg1 [10:5] $xor$build/ls180/gateware/ls180.v:4710$865_Y \libresocsim_sdcore_crc16_inserter_crc3_crcreg1 [3:0] $xor$build/ls180/gateware/ls180.v:4710$863_Y } + connect \libresocsim_sdcore_crc16_checker_crc0_val { \libresocsim_sdcore_crc16_checker_val [7] \libresocsim_sdcore_crc16_checker_val [3] } + connect \libresocsim_sdcore_crc16_checker_crc0_enable $and$build/ls180/gateware/ls180.v:4806$883_Y + connect \libresocsim_sdcore_crc16_checker_crc1_val { \libresocsim_sdcore_crc16_checker_val [6] \libresocsim_sdcore_crc16_checker_val [2] } + connect \libresocsim_sdcore_crc16_checker_crc1_enable $and$build/ls180/gateware/ls180.v:4816$886_Y + connect \libresocsim_sdcore_crc16_checker_crc2_val { \libresocsim_sdcore_crc16_checker_val [5] \libresocsim_sdcore_crc16_checker_val [1] } + connect \libresocsim_sdcore_crc16_checker_crc2_enable $and$build/ls180/gateware/ls180.v:4826$889_Y + connect \libresocsim_sdcore_crc16_checker_crc3_val { \libresocsim_sdcore_crc16_checker_val [4] \libresocsim_sdcore_crc16_checker_val [0] } + connect \libresocsim_sdcore_crc16_checker_crc3_enable $and$build/ls180/gateware/ls180.v:4836$892_Y + connect \libresocsim_sdcore_crc16_checker_source_payload_data \libresocsim_sdcore_crc16_checker_val + connect \libresocsim_sdcore_crc16_checker_source_last \libresocsim_sdcore_crc16_checker_sink_last + connect \libresocsim_sdcore_crc16_checker_crc0_crcreg1 { \libresocsim_sdcore_crc16_checker_crc0_crcreg0 [14:12] $xor$build/ls180/gateware/ls180.v:4861$904_Y \libresocsim_sdcore_crc16_checker_crc0_crcreg0 [10:5] $xor$build/ls180/gateware/ls180.v:4861$902_Y \libresocsim_sdcore_crc16_checker_crc0_crcreg0 [3:0] $xor$build/ls180/gateware/ls180.v:4861$900_Y } + connect \libresocsim_sdcore_crc16_checker_crc0_crcreg2 { \libresocsim_sdcore_crc16_checker_crc0_crcreg1 [14:12] $xor$build/ls180/gateware/ls180.v:4862$909_Y \libresocsim_sdcore_crc16_checker_crc0_crcreg1 [10:5] $xor$build/ls180/gateware/ls180.v:4862$907_Y \libresocsim_sdcore_crc16_checker_crc0_crcreg1 [3:0] $xor$build/ls180/gateware/ls180.v:4862$905_Y } + connect \libresocsim_sdcore_crc16_checker_crc1_crcreg1 { \libresocsim_sdcore_crc16_checker_crc1_crcreg0 [14:12] $xor$build/ls180/gateware/ls180.v:4871$915_Y \libresocsim_sdcore_crc16_checker_crc1_crcreg0 [10:5] $xor$build/ls180/gateware/ls180.v:4871$913_Y \libresocsim_sdcore_crc16_checker_crc1_crcreg0 [3:0] $xor$build/ls180/gateware/ls180.v:4871$911_Y } + connect \libresocsim_sdcore_crc16_checker_crc1_crcreg2 { \libresocsim_sdcore_crc16_checker_crc1_crcreg1 [14:12] $xor$build/ls180/gateware/ls180.v:4872$920_Y \libresocsim_sdcore_crc16_checker_crc1_crcreg1 [10:5] $xor$build/ls180/gateware/ls180.v:4872$918_Y \libresocsim_sdcore_crc16_checker_crc1_crcreg1 [3:0] $xor$build/ls180/gateware/ls180.v:4872$916_Y } + connect \libresocsim_sdcore_crc16_checker_crc2_crcreg1 { \libresocsim_sdcore_crc16_checker_crc2_crcreg0 [14:12] $xor$build/ls180/gateware/ls180.v:4881$926_Y \libresocsim_sdcore_crc16_checker_crc2_crcreg0 [10:5] $xor$build/ls180/gateware/ls180.v:4881$924_Y \libresocsim_sdcore_crc16_checker_crc2_crcreg0 [3:0] $xor$build/ls180/gateware/ls180.v:4881$922_Y } + connect \libresocsim_sdcore_crc16_checker_crc2_crcreg2 { \libresocsim_sdcore_crc16_checker_crc2_crcreg1 [14:12] $xor$build/ls180/gateware/ls180.v:4882$931_Y \libresocsim_sdcore_crc16_checker_crc2_crcreg1 [10:5] $xor$build/ls180/gateware/ls180.v:4882$929_Y \libresocsim_sdcore_crc16_checker_crc2_crcreg1 [3:0] $xor$build/ls180/gateware/ls180.v:4882$927_Y } + connect \libresocsim_sdcore_crc16_checker_crc3_crcreg1 { \libresocsim_sdcore_crc16_checker_crc3_crcreg0 [14:12] $xor$build/ls180/gateware/ls180.v:4891$937_Y \libresocsim_sdcore_crc16_checker_crc3_crcreg0 [10:5] $xor$build/ls180/gateware/ls180.v:4891$935_Y \libresocsim_sdcore_crc16_checker_crc3_crcreg0 [3:0] $xor$build/ls180/gateware/ls180.v:4891$933_Y } + connect \libresocsim_sdcore_crc16_checker_crc3_crcreg2 { \libresocsim_sdcore_crc16_checker_crc3_crcreg1 [14:12] $xor$build/ls180/gateware/ls180.v:4892$942_Y \libresocsim_sdcore_crc16_checker_crc3_crcreg1 [10:5] $xor$build/ls180/gateware/ls180.v:4892$940_Y \libresocsim_sdcore_crc16_checker_crc3_crcreg1 [3:0] $xor$build/ls180/gateware/ls180.v:4892$938_Y } + connect \libresocsim_sdblock2mem_fifo_sink_valid \libresocsim_sdblock2mem_sink_sink_valid0 + connect \libresocsim_sdblock2mem_sink_sink_ready0 \libresocsim_sdblock2mem_fifo_sink_ready + connect \libresocsim_sdblock2mem_fifo_sink_first \libresocsim_sdblock2mem_sink_sink_first + connect \libresocsim_sdblock2mem_fifo_sink_last \libresocsim_sdblock2mem_sink_sink_last + connect \libresocsim_sdblock2mem_fifo_sink_payload_data \libresocsim_sdblock2mem_sink_sink_payload_data0 + connect \libresocsim_sdblock2mem_converter_sink_valid \libresocsim_sdblock2mem_fifo_source_valid + connect \libresocsim_sdblock2mem_fifo_source_ready \libresocsim_sdblock2mem_converter_sink_ready + connect \libresocsim_sdblock2mem_converter_sink_first \libresocsim_sdblock2mem_fifo_source_first + connect \libresocsim_sdblock2mem_converter_sink_last \libresocsim_sdblock2mem_fifo_source_last + connect \libresocsim_sdblock2mem_converter_sink_payload_data \libresocsim_sdblock2mem_fifo_source_payload_data + connect \libresocsim_sdblock2mem_wishbonedmawriter_sink_valid \libresocsim_sdblock2mem_source_source_valid + connect \libresocsim_sdblock2mem_source_source_ready \libresocsim_sdblock2mem_wishbonedmawriter_sink_ready + connect \libresocsim_sdblock2mem_wishbonedmawriter_sink_first \libresocsim_sdblock2mem_source_source_first + connect \libresocsim_sdblock2mem_wishbonedmawriter_sink_last \libresocsim_sdblock2mem_source_source_last + connect \libresocsim_sdblock2mem_wishbonedmawriter_sink_payload_data \libresocsim_sdblock2mem_source_source_payload_data + connect \libresocsim_sdblock2mem_fifo_syncfifo_din { \libresocsim_sdblock2mem_fifo_fifo_in_last \libresocsim_sdblock2mem_fifo_fifo_in_first \libresocsim_sdblock2mem_fifo_fifo_in_payload_data } + connect { \libresocsim_sdblock2mem_fifo_fifo_out_last \libresocsim_sdblock2mem_fifo_fifo_out_first \libresocsim_sdblock2mem_fifo_fifo_out_payload_data } \libresocsim_sdblock2mem_fifo_syncfifo_dout + connect \libresocsim_sdblock2mem_fifo_sink_ready \libresocsim_sdblock2mem_fifo_syncfifo_writable + connect \libresocsim_sdblock2mem_fifo_syncfifo_we \libresocsim_sdblock2mem_fifo_sink_valid + connect \libresocsim_sdblock2mem_fifo_fifo_in_first \libresocsim_sdblock2mem_fifo_sink_first + connect \libresocsim_sdblock2mem_fifo_fifo_in_last \libresocsim_sdblock2mem_fifo_sink_last + connect \libresocsim_sdblock2mem_fifo_fifo_in_payload_data \libresocsim_sdblock2mem_fifo_sink_payload_data + connect \libresocsim_sdblock2mem_fifo_source_valid \libresocsim_sdblock2mem_fifo_syncfifo_readable + connect \libresocsim_sdblock2mem_fifo_source_first \libresocsim_sdblock2mem_fifo_fifo_out_first + connect \libresocsim_sdblock2mem_fifo_source_last \libresocsim_sdblock2mem_fifo_fifo_out_last + connect \libresocsim_sdblock2mem_fifo_source_payload_data \libresocsim_sdblock2mem_fifo_fifo_out_payload_data + connect \libresocsim_sdblock2mem_fifo_syncfifo_re \libresocsim_sdblock2mem_fifo_source_ready + connect \libresocsim_sdblock2mem_fifo_wrport_dat_w \libresocsim_sdblock2mem_fifo_syncfifo_din + connect \libresocsim_sdblock2mem_fifo_wrport_we $and$build/ls180/gateware/ls180.v:5128$972_Y + connect \libresocsim_sdblock2mem_fifo_do_read $and$build/ls180/gateware/ls180.v:5129$973_Y + connect \libresocsim_sdblock2mem_fifo_rdport_adr \libresocsim_sdblock2mem_fifo_consume + connect \libresocsim_sdblock2mem_fifo_syncfifo_dout \libresocsim_sdblock2mem_fifo_rdport_dat_r + connect \libresocsim_sdblock2mem_fifo_syncfifo_writable $ne$build/ls180/gateware/ls180.v:5132$974_Y + connect \libresocsim_sdblock2mem_fifo_syncfifo_readable $ne$build/ls180/gateware/ls180.v:5133$975_Y + connect \libresocsim_sdblock2mem_source_source_valid \libresocsim_sdblock2mem_converter_source_valid + connect \libresocsim_sdblock2mem_converter_source_ready \libresocsim_sdblock2mem_source_source_ready + connect \libresocsim_sdblock2mem_source_source_first \libresocsim_sdblock2mem_converter_source_first + connect \libresocsim_sdblock2mem_source_source_last \libresocsim_sdblock2mem_converter_source_last + connect \libresocsim_sdblock2mem_source_source_payload_data \libresocsim_sdblock2mem_converter_source_payload_data + connect \libresocsim_sdblock2mem_converter_sink_ready $or$build/ls180/gateware/ls180.v:5139$977_Y + connect \libresocsim_sdblock2mem_converter_source_valid \libresocsim_sdblock2mem_converter_strobe_all + connect \libresocsim_sdblock2mem_converter_load_part $and$build/ls180/gateware/ls180.v:5141$978_Y + connect \libresocsim_interface0_bus_stb \libresocsim_sdblock2mem_sink_sink_valid1 + connect \libresocsim_interface0_bus_cyc \libresocsim_sdblock2mem_sink_sink_valid1 + connect \libresocsim_interface0_bus_we 1'1 + connect \libresocsim_interface0_bus_sel 4'1111 + connect \libresocsim_interface0_bus_adr \libresocsim_sdblock2mem_sink_sink_payload_address + connect \libresocsim_interface0_bus_dat_w { \libresocsim_sdblock2mem_sink_sink_payload_data1 [7:0] \libresocsim_sdblock2mem_sink_sink_payload_data1 [15:8] \libresocsim_sdblock2mem_sink_sink_payload_data1 [23:16] \libresocsim_sdblock2mem_sink_sink_payload_data1 [31:24] } + connect \libresocsim_sdblock2mem_sink_sink_ready1 \libresocsim_interface0_bus_ack + connect \libresocsim_sdblock2mem_wishbonedmawriter_base \libresocsim_sdblock2mem_wishbonedmawriter_base_storage [33:2] + connect \libresocsim_sdblock2mem_wishbonedmawriter_length { 2'00 \libresocsim_sdblock2mem_wishbonedmawriter_length_storage [31:2] } + connect \libresocsim_sdblock2mem_wishbonedmawriter_reset $not$build/ls180/gateware/ls180.v:5151$979_Y + connect \libresocsim_sdmem2block_converter_sink_valid \libresocsim_sdmem2block_dma_source_valid + connect \libresocsim_sdmem2block_dma_source_ready \libresocsim_sdmem2block_converter_sink_ready + connect \libresocsim_sdmem2block_converter_sink_first \libresocsim_sdmem2block_dma_source_first + connect \libresocsim_sdmem2block_converter_sink_last \libresocsim_sdmem2block_dma_source_last + connect \libresocsim_sdmem2block_converter_sink_payload_data \libresocsim_sdmem2block_dma_source_payload_data + connect \libresocsim_sdmem2block_fifo_sink_valid \libresocsim_sdmem2block_source_source_valid1 + connect \libresocsim_sdmem2block_source_source_ready1 \libresocsim_sdmem2block_fifo_sink_ready + connect \libresocsim_sdmem2block_fifo_sink_first \libresocsim_sdmem2block_source_source_first1 + connect \libresocsim_sdmem2block_fifo_sink_last \libresocsim_sdmem2block_source_source_last1 + connect \libresocsim_sdmem2block_fifo_sink_payload_data \libresocsim_sdmem2block_source_source_payload_data1 + connect \libresocsim_sdmem2block_source_source_valid0 \libresocsim_sdmem2block_fifo_source_valid + connect \libresocsim_sdmem2block_fifo_source_ready \libresocsim_sdmem2block_source_source_ready0 + connect \libresocsim_sdmem2block_source_source_first0 \libresocsim_sdmem2block_fifo_source_first + connect \libresocsim_sdmem2block_source_source_last0 \libresocsim_sdmem2block_fifo_source_last + connect \libresocsim_sdmem2block_source_source_payload_data0 \libresocsim_sdmem2block_fifo_source_payload_data + connect \libresocsim_sdmem2block_dma_base \libresocsim_sdmem2block_dma_base_storage [33:2] + connect \libresocsim_sdmem2block_dma_length { 2'00 \libresocsim_sdmem2block_dma_length_storage [31:2] } + connect \libresocsim_sdmem2block_dma_offset_status \libresocsim_sdmem2block_dma_offset + connect \libresocsim_sdmem2block_dma_reset $not$build/ls180/gateware/ls180.v:5210$986_Y + connect \libresocsim_sdmem2block_source_source_valid1 \libresocsim_sdmem2block_converter_source_valid + connect \libresocsim_sdmem2block_converter_source_ready \libresocsim_sdmem2block_source_source_ready1 + connect \libresocsim_sdmem2block_source_source_first1 \libresocsim_sdmem2block_converter_source_first + connect \libresocsim_sdmem2block_source_source_last1 \libresocsim_sdmem2block_converter_source_last + connect \libresocsim_sdmem2block_source_source_payload_data1 \libresocsim_sdmem2block_converter_source_payload_data + connect \libresocsim_sdmem2block_converter_first $eq$build/ls180/gateware/ls180.v:5291$994_Y + connect \libresocsim_sdmem2block_converter_last $eq$build/ls180/gateware/ls180.v:5292$995_Y + connect \libresocsim_sdmem2block_converter_source_valid \libresocsim_sdmem2block_converter_sink_valid + connect \libresocsim_sdmem2block_converter_source_first $and$build/ls180/gateware/ls180.v:5294$996_Y + connect \libresocsim_sdmem2block_converter_source_last $and$build/ls180/gateware/ls180.v:5295$997_Y + connect \libresocsim_sdmem2block_converter_sink_ready $and$build/ls180/gateware/ls180.v:5296$998_Y + connect \libresocsim_sdmem2block_converter_source_payload_valid_token_count \libresocsim_sdmem2block_converter_last + connect \libresocsim_sdmem2block_fifo_syncfifo_din { \libresocsim_sdmem2block_fifo_fifo_in_last \libresocsim_sdmem2block_fifo_fifo_in_first \libresocsim_sdmem2block_fifo_fifo_in_payload_data } + connect { \libresocsim_sdmem2block_fifo_fifo_out_last \libresocsim_sdmem2block_fifo_fifo_out_first \libresocsim_sdmem2block_fifo_fifo_out_payload_data } \libresocsim_sdmem2block_fifo_syncfifo_dout + connect \libresocsim_sdmem2block_fifo_sink_ready \libresocsim_sdmem2block_fifo_syncfifo_writable + connect \libresocsim_sdmem2block_fifo_syncfifo_we \libresocsim_sdmem2block_fifo_sink_valid + connect \libresocsim_sdmem2block_fifo_fifo_in_first \libresocsim_sdmem2block_fifo_sink_first + connect \libresocsim_sdmem2block_fifo_fifo_in_last \libresocsim_sdmem2block_fifo_sink_last + connect \libresocsim_sdmem2block_fifo_fifo_in_payload_data \libresocsim_sdmem2block_fifo_sink_payload_data + connect \libresocsim_sdmem2block_fifo_source_valid \libresocsim_sdmem2block_fifo_syncfifo_readable + connect \libresocsim_sdmem2block_fifo_source_first \libresocsim_sdmem2block_fifo_fifo_out_first + connect \libresocsim_sdmem2block_fifo_source_last \libresocsim_sdmem2block_fifo_fifo_out_last + connect \libresocsim_sdmem2block_fifo_source_payload_data \libresocsim_sdmem2block_fifo_fifo_out_payload_data + connect \libresocsim_sdmem2block_fifo_syncfifo_re \libresocsim_sdmem2block_fifo_source_ready + connect \libresocsim_sdmem2block_fifo_wrport_dat_w \libresocsim_sdmem2block_fifo_syncfifo_din + connect \libresocsim_sdmem2block_fifo_wrport_we $and$build/ls180/gateware/ls180.v:5336$1003_Y + connect \libresocsim_sdmem2block_fifo_do_read $and$build/ls180/gateware/ls180.v:5337$1004_Y + connect \libresocsim_sdmem2block_fifo_rdport_adr \libresocsim_sdmem2block_fifo_consume + connect \libresocsim_sdmem2block_fifo_syncfifo_dout \libresocsim_sdmem2block_fifo_rdport_dat_r + connect \libresocsim_sdmem2block_fifo_syncfifo_writable $ne$build/ls180/gateware/ls180.v:5340$1005_Y + connect \libresocsim_sdmem2block_fifo_syncfifo_readable $ne$build/ls180/gateware/ls180.v:5341$1006_Y + connect \libresocsim_start0 \libresocsim_start1 + connect \libresocsim_length0 \libresocsim_length1 + connect \libresocsim_mosi \libresocsim_mosi_storage + connect \libresocsim_done1 \libresocsim_done0 + connect \libresocsim_miso_status \libresocsim_miso + connect \libresocsim_cs \libresocsim_cs_storage + connect \libresocsim_loopback \libresocsim_loopback_storage + connect \libresocsim_clk_rise $eq$build/ls180/gateware/ls180.v:5349$1008_Y + connect \libresocsim_clk_fall $eq$build/ls180/gateware/ls180.v:5350$1010_Y + connect \libresocsim_clk_divider0 \libresocsim_storage + connect \builder_shared_adr \builder_comb_rhs_array_muxed24 [29:0] + connect \builder_shared_dat_w \builder_comb_rhs_array_muxed25 + connect \builder_shared_sel \builder_comb_rhs_array_muxed26 + connect \builder_shared_cyc \builder_comb_rhs_array_muxed27 + connect \builder_shared_stb \builder_comb_rhs_array_muxed28 + connect \builder_shared_we \builder_comb_rhs_array_muxed29 + connect \builder_shared_cti \builder_comb_rhs_array_muxed30 + connect \builder_shared_bte \builder_comb_rhs_array_muxed31 + connect \main_libresocsim_interface0_converted_interface_dat_r \builder_shared_dat_r + connect \main_libresocsim_interface1_converted_interface_dat_r \builder_shared_dat_r + connect \libresocsim_interface0_bus_dat_r \builder_shared_dat_r + connect \libresocsim_interface1_bus_dat_r \builder_shared_dat_r + connect \main_libresocsim_interface0_converted_interface_ack $and$build/ls180/gateware/ls180.v:5450$1020_Y + connect \main_libresocsim_interface1_converted_interface_ack $and$build/ls180/gateware/ls180.v:5451$1022_Y + connect \libresocsim_interface0_bus_ack $and$build/ls180/gateware/ls180.v:5452$1024_Y + connect \libresocsim_interface1_bus_ack $and$build/ls180/gateware/ls180.v:5453$1026_Y + connect \main_libresocsim_interface0_converted_interface_err $and$build/ls180/gateware/ls180.v:5454$1028_Y + connect \main_libresocsim_interface1_converted_interface_err $and$build/ls180/gateware/ls180.v:5455$1030_Y + connect \libresocsim_interface0_bus_err $and$build/ls180/gateware/ls180.v:5456$1032_Y + connect \libresocsim_interface1_bus_err $and$build/ls180/gateware/ls180.v:5457$1034_Y + connect \builder_request { \libresocsim_interface1_bus_cyc \libresocsim_interface0_bus_cyc \main_libresocsim_interface1_converted_interface_cyc \main_libresocsim_interface0_converted_interface_cyc } + connect \main_libresocsim_ram_bus_adr \builder_shared_adr + connect \main_libresocsim_ram_bus_dat_w \builder_shared_dat_w + connect \main_libresocsim_ram_bus_sel \builder_shared_sel + connect \main_libresocsim_ram_bus_stb \builder_shared_stb + connect \main_libresocsim_ram_bus_we \builder_shared_we + connect \main_libresocsim_ram_bus_cti \builder_shared_cti + connect \main_libresocsim_ram_bus_bte \builder_shared_bte + connect \main_libresocsim_libresoc_xics_icp_adr \builder_shared_adr + connect \main_libresocsim_libresoc_xics_icp_dat_w \builder_shared_dat_w + connect \main_libresocsim_libresoc_xics_icp_sel \builder_shared_sel + connect \main_libresocsim_libresoc_xics_icp_stb \builder_shared_stb + connect \main_libresocsim_libresoc_xics_icp_we \builder_shared_we + connect \main_libresocsim_libresoc_xics_icp_cti \builder_shared_cti + connect \main_libresocsim_libresoc_xics_icp_bte \builder_shared_bte + connect \main_libresocsim_libresoc_xics_ics_adr \builder_shared_adr + connect \main_libresocsim_libresoc_xics_ics_dat_w \builder_shared_dat_w + connect \main_libresocsim_libresoc_xics_ics_sel \builder_shared_sel + connect \main_libresocsim_libresoc_xics_ics_stb \builder_shared_stb + connect \main_libresocsim_libresoc_xics_ics_we \builder_shared_we + connect \main_libresocsim_libresoc_xics_ics_cti \builder_shared_cti + connect \main_libresocsim_libresoc_xics_ics_bte \builder_shared_bte + connect \main_wb_sdram_adr \builder_shared_adr + connect \main_wb_sdram_dat_w \builder_shared_dat_w + connect \main_wb_sdram_sel \builder_shared_sel + connect \main_wb_sdram_stb \builder_shared_stb + connect \main_wb_sdram_we \builder_shared_we + connect \main_wb_sdram_cti \builder_shared_cti + connect \main_wb_sdram_bte \builder_shared_bte + connect \builder_libresocsim_wishbone_adr \builder_shared_adr + connect \builder_libresocsim_wishbone_dat_w \builder_shared_dat_w + connect \builder_libresocsim_wishbone_sel \builder_shared_sel + connect \builder_libresocsim_wishbone_stb \builder_shared_stb + connect \builder_libresocsim_wishbone_we \builder_shared_we + connect \builder_libresocsim_wishbone_cti \builder_shared_cti + connect \builder_libresocsim_wishbone_bte \builder_shared_bte + connect \main_libresocsim_ram_bus_cyc $and$build/ls180/gateware/ls180.v:5502$1041_Y + connect \main_libresocsim_libresoc_xics_icp_cyc $and$build/ls180/gateware/ls180.v:5503$1042_Y + connect \main_libresocsim_libresoc_xics_ics_cyc $and$build/ls180/gateware/ls180.v:5504$1043_Y + connect \main_wb_sdram_cyc $and$build/ls180/gateware/ls180.v:5505$1044_Y + connect \builder_libresocsim_wishbone_cyc $and$build/ls180/gateware/ls180.v:5506$1045_Y + connect \builder_shared_err $or$build/ls180/gateware/ls180.v:5507$1049_Y + connect \builder_wait $and$build/ls180/gateware/ls180.v:5508$1052_Y + connect \builder_done $eq$build/ls180/gateware/ls180.v:5521$1067_Y + connect \builder_csrbank0_sel $eq$build/ls180/gateware/ls180.v:5522$1068_Y + connect \builder_csrbank0_reset0_r \builder_interface0_bank_bus_dat_w [0] + connect \builder_csrbank0_reset0_re $and$build/ls180/gateware/ls180.v:5524$1071_Y + connect \builder_csrbank0_reset0_we $and$build/ls180/gateware/ls180.v:5525$1075_Y + connect \builder_csrbank0_scratch3_r \builder_interface0_bank_bus_dat_w + connect \builder_csrbank0_scratch3_re $and$build/ls180/gateware/ls180.v:5527$1078_Y + connect \builder_csrbank0_scratch3_we $and$build/ls180/gateware/ls180.v:5528$1082_Y + connect \builder_csrbank0_scratch2_r \builder_interface0_bank_bus_dat_w + connect \builder_csrbank0_scratch2_re $and$build/ls180/gateware/ls180.v:5530$1085_Y + connect \builder_csrbank0_scratch2_we $and$build/ls180/gateware/ls180.v:5531$1089_Y + connect \builder_csrbank0_scratch1_r \builder_interface0_bank_bus_dat_w + connect \builder_csrbank0_scratch1_re $and$build/ls180/gateware/ls180.v:5533$1092_Y + connect \builder_csrbank0_scratch1_we $and$build/ls180/gateware/ls180.v:5534$1096_Y + connect \builder_csrbank0_scratch0_r \builder_interface0_bank_bus_dat_w + connect \builder_csrbank0_scratch0_re $and$build/ls180/gateware/ls180.v:5536$1099_Y + connect \builder_csrbank0_scratch0_we $and$build/ls180/gateware/ls180.v:5537$1103_Y + connect \builder_csrbank0_bus_errors3_r \builder_interface0_bank_bus_dat_w + connect \builder_csrbank0_bus_errors3_re $and$build/ls180/gateware/ls180.v:5539$1106_Y + connect \builder_csrbank0_bus_errors3_we $and$build/ls180/gateware/ls180.v:5540$1110_Y + connect \builder_csrbank0_bus_errors2_r \builder_interface0_bank_bus_dat_w + connect \builder_csrbank0_bus_errors2_re $and$build/ls180/gateware/ls180.v:5542$1113_Y + connect \builder_csrbank0_bus_errors2_we $and$build/ls180/gateware/ls180.v:5543$1117_Y + connect \builder_csrbank0_bus_errors1_r \builder_interface0_bank_bus_dat_w + connect \builder_csrbank0_bus_errors1_re $and$build/ls180/gateware/ls180.v:5545$1120_Y + connect \builder_csrbank0_bus_errors1_we $and$build/ls180/gateware/ls180.v:5546$1124_Y + connect \builder_csrbank0_bus_errors0_r \builder_interface0_bank_bus_dat_w + connect \builder_csrbank0_bus_errors0_re $and$build/ls180/gateware/ls180.v:5548$1127_Y + connect \builder_csrbank0_bus_errors0_we $and$build/ls180/gateware/ls180.v:5549$1131_Y + connect \builder_csrbank0_reset0_w \main_libresocsim_soccontroller_reset_storage + connect \builder_csrbank0_scratch3_w \main_libresocsim_soccontroller_scratch_storage [31:24] + connect \builder_csrbank0_scratch2_w \main_libresocsim_soccontroller_scratch_storage [23:16] + connect \builder_csrbank0_scratch1_w \main_libresocsim_soccontroller_scratch_storage [15:8] + connect \builder_csrbank0_scratch0_w \main_libresocsim_soccontroller_scratch_storage [7:0] + connect \builder_csrbank0_bus_errors3_w \main_libresocsim_soccontroller_bus_errors_status [31:24] + connect \builder_csrbank0_bus_errors2_w \main_libresocsim_soccontroller_bus_errors_status [23:16] + connect \builder_csrbank0_bus_errors1_w \main_libresocsim_soccontroller_bus_errors_status [15:8] + connect \builder_csrbank0_bus_errors0_w \main_libresocsim_soccontroller_bus_errors_status [7:0] + connect \main_libresocsim_soccontroller_bus_errors_we \builder_csrbank0_bus_errors0_we + connect \builder_csrbank1_sel $eq$build/ls180/gateware/ls180.v:5560$1132_Y + connect \builder_csrbank1_in_r \builder_interface1_bank_bus_dat_w + connect \builder_csrbank1_in_re $and$build/ls180/gateware/ls180.v:5562$1135_Y + connect \builder_csrbank1_in_we $and$build/ls180/gateware/ls180.v:5563$1139_Y + connect \builder_csrbank1_in_w \main_gpio_in_status + connect \main_gpio_in_we \builder_csrbank1_in_we + connect \builder_csrbank2_sel $eq$build/ls180/gateware/ls180.v:5566$1140_Y + connect \builder_csrbank2_in_r \builder_interface2_bank_bus_dat_w + connect \builder_csrbank2_in_re $and$build/ls180/gateware/ls180.v:5568$1143_Y + connect \builder_csrbank2_in_we $and$build/ls180/gateware/ls180.v:5569$1147_Y + connect \builder_csrbank2_in_w \main_gpio_out_status + connect \main_gpio_out_we \builder_csrbank2_in_we + connect \builder_csrbank3_sel $eq$build/ls180/gateware/ls180.v:5572$1148_Y + connect \builder_csrbank3_dma_base7_r \builder_interface3_bank_bus_dat_w + connect \builder_csrbank3_dma_base7_re $and$build/ls180/gateware/ls180.v:5574$1151_Y + connect \builder_csrbank3_dma_base7_we $and$build/ls180/gateware/ls180.v:5575$1155_Y + connect \builder_csrbank3_dma_base6_r \builder_interface3_bank_bus_dat_w + connect \builder_csrbank3_dma_base6_re $and$build/ls180/gateware/ls180.v:5577$1158_Y + connect \builder_csrbank3_dma_base6_we $and$build/ls180/gateware/ls180.v:5578$1162_Y + connect \builder_csrbank3_dma_base5_r \builder_interface3_bank_bus_dat_w + connect \builder_csrbank3_dma_base5_re $and$build/ls180/gateware/ls180.v:5580$1165_Y + connect \builder_csrbank3_dma_base5_we $and$build/ls180/gateware/ls180.v:5581$1169_Y + connect \builder_csrbank3_dma_base4_r \builder_interface3_bank_bus_dat_w + connect \builder_csrbank3_dma_base4_re $and$build/ls180/gateware/ls180.v:5583$1172_Y + connect \builder_csrbank3_dma_base4_we $and$build/ls180/gateware/ls180.v:5584$1176_Y + connect \builder_csrbank3_dma_base3_r \builder_interface3_bank_bus_dat_w + connect \builder_csrbank3_dma_base3_re $and$build/ls180/gateware/ls180.v:5586$1179_Y + connect \builder_csrbank3_dma_base3_we $and$build/ls180/gateware/ls180.v:5587$1183_Y + connect \builder_csrbank3_dma_base2_r \builder_interface3_bank_bus_dat_w + connect \builder_csrbank3_dma_base2_re $and$build/ls180/gateware/ls180.v:5589$1186_Y + connect \builder_csrbank3_dma_base2_we $and$build/ls180/gateware/ls180.v:5590$1190_Y + connect \builder_csrbank3_dma_base1_r \builder_interface3_bank_bus_dat_w + connect \builder_csrbank3_dma_base1_re $and$build/ls180/gateware/ls180.v:5592$1193_Y + connect \builder_csrbank3_dma_base1_we $and$build/ls180/gateware/ls180.v:5593$1197_Y + connect \builder_csrbank3_dma_base0_r \builder_interface3_bank_bus_dat_w + connect \builder_csrbank3_dma_base0_re $and$build/ls180/gateware/ls180.v:5595$1200_Y + connect \builder_csrbank3_dma_base0_we $and$build/ls180/gateware/ls180.v:5596$1204_Y + connect \builder_csrbank3_dma_length3_r \builder_interface3_bank_bus_dat_w + connect \builder_csrbank3_dma_length3_re $and$build/ls180/gateware/ls180.v:5598$1207_Y + connect \builder_csrbank3_dma_length3_we $and$build/ls180/gateware/ls180.v:5599$1211_Y + connect \builder_csrbank3_dma_length2_r \builder_interface3_bank_bus_dat_w + connect \builder_csrbank3_dma_length2_re $and$build/ls180/gateware/ls180.v:5601$1214_Y + connect \builder_csrbank3_dma_length2_we $and$build/ls180/gateware/ls180.v:5602$1218_Y + connect \builder_csrbank3_dma_length1_r \builder_interface3_bank_bus_dat_w + connect \builder_csrbank3_dma_length1_re $and$build/ls180/gateware/ls180.v:5604$1221_Y + connect \builder_csrbank3_dma_length1_we $and$build/ls180/gateware/ls180.v:5605$1225_Y + connect \builder_csrbank3_dma_length0_r \builder_interface3_bank_bus_dat_w + connect \builder_csrbank3_dma_length0_re $and$build/ls180/gateware/ls180.v:5607$1228_Y + connect \builder_csrbank3_dma_length0_we $and$build/ls180/gateware/ls180.v:5608$1232_Y + connect \builder_csrbank3_dma_enable0_r \builder_interface3_bank_bus_dat_w [0] + connect \builder_csrbank3_dma_enable0_re $and$build/ls180/gateware/ls180.v:5610$1235_Y + connect \builder_csrbank3_dma_enable0_we $and$build/ls180/gateware/ls180.v:5611$1239_Y + connect \builder_csrbank3_dma_done_r \builder_interface3_bank_bus_dat_w [0] + connect \builder_csrbank3_dma_done_re $and$build/ls180/gateware/ls180.v:5613$1242_Y + connect \builder_csrbank3_dma_done_we $and$build/ls180/gateware/ls180.v:5614$1246_Y + connect \builder_csrbank3_dma_loop0_r \builder_interface3_bank_bus_dat_w [0] + connect \builder_csrbank3_dma_loop0_re $and$build/ls180/gateware/ls180.v:5616$1249_Y + connect \builder_csrbank3_dma_loop0_we $and$build/ls180/gateware/ls180.v:5617$1253_Y + connect \builder_csrbank3_dma_base7_w \libresocsim_sdblock2mem_wishbonedmawriter_base_storage [63:56] + connect \builder_csrbank3_dma_base6_w \libresocsim_sdblock2mem_wishbonedmawriter_base_storage [55:48] + connect \builder_csrbank3_dma_base5_w \libresocsim_sdblock2mem_wishbonedmawriter_base_storage [47:40] + connect \builder_csrbank3_dma_base4_w \libresocsim_sdblock2mem_wishbonedmawriter_base_storage [39:32] + connect \builder_csrbank3_dma_base3_w \libresocsim_sdblock2mem_wishbonedmawriter_base_storage [31:24] + connect \builder_csrbank3_dma_base2_w \libresocsim_sdblock2mem_wishbonedmawriter_base_storage [23:16] + connect \builder_csrbank3_dma_base1_w \libresocsim_sdblock2mem_wishbonedmawriter_base_storage [15:8] + connect \builder_csrbank3_dma_base0_w \libresocsim_sdblock2mem_wishbonedmawriter_base_storage [7:0] + connect \builder_csrbank3_dma_length3_w \libresocsim_sdblock2mem_wishbonedmawriter_length_storage [31:24] + connect \builder_csrbank3_dma_length2_w \libresocsim_sdblock2mem_wishbonedmawriter_length_storage [23:16] + connect \builder_csrbank3_dma_length1_w \libresocsim_sdblock2mem_wishbonedmawriter_length_storage [15:8] + connect \builder_csrbank3_dma_length0_w \libresocsim_sdblock2mem_wishbonedmawriter_length_storage [7:0] + connect \builder_csrbank3_dma_enable0_w \libresocsim_sdblock2mem_wishbonedmawriter_enable_storage + connect \builder_csrbank3_dma_done_w \libresocsim_sdblock2mem_wishbonedmawriter_status + connect \libresocsim_sdblock2mem_wishbonedmawriter_we \builder_csrbank3_dma_done_we + connect \builder_csrbank3_dma_loop0_w \libresocsim_sdblock2mem_wishbonedmawriter_loop_storage + connect \builder_csrbank4_sel $eq$build/ls180/gateware/ls180.v:5634$1254_Y + connect \builder_csrbank4_cmd_argument3_r \builder_interface4_bank_bus_dat_w + connect \builder_csrbank4_cmd_argument3_re $and$build/ls180/gateware/ls180.v:5636$1257_Y + connect \builder_csrbank4_cmd_argument3_we $and$build/ls180/gateware/ls180.v:5637$1261_Y + connect \builder_csrbank4_cmd_argument2_r \builder_interface4_bank_bus_dat_w + connect \builder_csrbank4_cmd_argument2_re $and$build/ls180/gateware/ls180.v:5639$1264_Y + connect \builder_csrbank4_cmd_argument2_we $and$build/ls180/gateware/ls180.v:5640$1268_Y + connect \builder_csrbank4_cmd_argument1_r \builder_interface4_bank_bus_dat_w + connect \builder_csrbank4_cmd_argument1_re $and$build/ls180/gateware/ls180.v:5642$1271_Y + connect \builder_csrbank4_cmd_argument1_we $and$build/ls180/gateware/ls180.v:5643$1275_Y + connect \builder_csrbank4_cmd_argument0_r \builder_interface4_bank_bus_dat_w + connect \builder_csrbank4_cmd_argument0_re $and$build/ls180/gateware/ls180.v:5645$1278_Y + connect \builder_csrbank4_cmd_argument0_we $and$build/ls180/gateware/ls180.v:5646$1282_Y + connect \builder_csrbank4_cmd_command3_r \builder_interface4_bank_bus_dat_w + connect \builder_csrbank4_cmd_command3_re $and$build/ls180/gateware/ls180.v:5648$1285_Y + connect \builder_csrbank4_cmd_command3_we $and$build/ls180/gateware/ls180.v:5649$1289_Y + connect \builder_csrbank4_cmd_command2_r \builder_interface4_bank_bus_dat_w + connect \builder_csrbank4_cmd_command2_re $and$build/ls180/gateware/ls180.v:5651$1292_Y + connect \builder_csrbank4_cmd_command2_we $and$build/ls180/gateware/ls180.v:5652$1296_Y + connect \builder_csrbank4_cmd_command1_r \builder_interface4_bank_bus_dat_w + connect \builder_csrbank4_cmd_command1_re $and$build/ls180/gateware/ls180.v:5654$1299_Y + connect \builder_csrbank4_cmd_command1_we $and$build/ls180/gateware/ls180.v:5655$1303_Y + connect \builder_csrbank4_cmd_command0_r \builder_interface4_bank_bus_dat_w + connect \builder_csrbank4_cmd_command0_re $and$build/ls180/gateware/ls180.v:5657$1306_Y + connect \builder_csrbank4_cmd_command0_we $and$build/ls180/gateware/ls180.v:5658$1310_Y + connect \libresocsim_sdcore_cmd_send_r \builder_interface4_bank_bus_dat_w [0] + connect \libresocsim_sdcore_cmd_send_re $and$build/ls180/gateware/ls180.v:5660$1313_Y + connect \libresocsim_sdcore_cmd_send_we $and$build/ls180/gateware/ls180.v:5661$1317_Y + connect \builder_csrbank4_cmd_response15_r \builder_interface4_bank_bus_dat_w + connect \builder_csrbank4_cmd_response15_re $and$build/ls180/gateware/ls180.v:5663$1320_Y + connect \builder_csrbank4_cmd_response15_we $and$build/ls180/gateware/ls180.v:5664$1324_Y + connect \builder_csrbank4_cmd_response14_r \builder_interface4_bank_bus_dat_w + connect \builder_csrbank4_cmd_response14_re $and$build/ls180/gateware/ls180.v:5666$1327_Y + connect \builder_csrbank4_cmd_response14_we $and$build/ls180/gateware/ls180.v:5667$1331_Y + connect \builder_csrbank4_cmd_response13_r \builder_interface4_bank_bus_dat_w + connect \builder_csrbank4_cmd_response13_re $and$build/ls180/gateware/ls180.v:5669$1334_Y + connect \builder_csrbank4_cmd_response13_we $and$build/ls180/gateware/ls180.v:5670$1338_Y + connect \builder_csrbank4_cmd_response12_r \builder_interface4_bank_bus_dat_w + connect \builder_csrbank4_cmd_response12_re $and$build/ls180/gateware/ls180.v:5672$1341_Y + connect \builder_csrbank4_cmd_response12_we $and$build/ls180/gateware/ls180.v:5673$1345_Y + connect \builder_csrbank4_cmd_response11_r \builder_interface4_bank_bus_dat_w + connect \builder_csrbank4_cmd_response11_re $and$build/ls180/gateware/ls180.v:5675$1348_Y + connect \builder_csrbank4_cmd_response11_we $and$build/ls180/gateware/ls180.v:5676$1352_Y + connect \builder_csrbank4_cmd_response10_r \builder_interface4_bank_bus_dat_w + connect \builder_csrbank4_cmd_response10_re $and$build/ls180/gateware/ls180.v:5678$1355_Y + connect \builder_csrbank4_cmd_response10_we $and$build/ls180/gateware/ls180.v:5679$1359_Y + connect \builder_csrbank4_cmd_response9_r \builder_interface4_bank_bus_dat_w + connect \builder_csrbank4_cmd_response9_re $and$build/ls180/gateware/ls180.v:5681$1362_Y + connect \builder_csrbank4_cmd_response9_we $and$build/ls180/gateware/ls180.v:5682$1366_Y + connect \builder_csrbank4_cmd_response8_r \builder_interface4_bank_bus_dat_w + connect \builder_csrbank4_cmd_response8_re $and$build/ls180/gateware/ls180.v:5684$1369_Y + connect \builder_csrbank4_cmd_response8_we $and$build/ls180/gateware/ls180.v:5685$1373_Y + connect \builder_csrbank4_cmd_response7_r \builder_interface4_bank_bus_dat_w + connect \builder_csrbank4_cmd_response7_re $and$build/ls180/gateware/ls180.v:5687$1376_Y + connect \builder_csrbank4_cmd_response7_we $and$build/ls180/gateware/ls180.v:5688$1380_Y + connect \builder_csrbank4_cmd_response6_r \builder_interface4_bank_bus_dat_w + connect \builder_csrbank4_cmd_response6_re $and$build/ls180/gateware/ls180.v:5690$1383_Y + connect \builder_csrbank4_cmd_response6_we $and$build/ls180/gateware/ls180.v:5691$1387_Y + connect \builder_csrbank4_cmd_response5_r \builder_interface4_bank_bus_dat_w + connect \builder_csrbank4_cmd_response5_re $and$build/ls180/gateware/ls180.v:5693$1390_Y + connect \builder_csrbank4_cmd_response5_we $and$build/ls180/gateware/ls180.v:5694$1394_Y + connect \builder_csrbank4_cmd_response4_r \builder_interface4_bank_bus_dat_w + connect \builder_csrbank4_cmd_response4_re $and$build/ls180/gateware/ls180.v:5696$1397_Y + connect \builder_csrbank4_cmd_response4_we $and$build/ls180/gateware/ls180.v:5697$1401_Y + connect \builder_csrbank4_cmd_response3_r \builder_interface4_bank_bus_dat_w + connect \builder_csrbank4_cmd_response3_re $and$build/ls180/gateware/ls180.v:5699$1404_Y + connect \builder_csrbank4_cmd_response3_we $and$build/ls180/gateware/ls180.v:5700$1408_Y + connect \builder_csrbank4_cmd_response2_r \builder_interface4_bank_bus_dat_w + connect \builder_csrbank4_cmd_response2_re $and$build/ls180/gateware/ls180.v:5702$1411_Y + connect \builder_csrbank4_cmd_response2_we $and$build/ls180/gateware/ls180.v:5703$1415_Y + connect \builder_csrbank4_cmd_response1_r \builder_interface4_bank_bus_dat_w + connect \builder_csrbank4_cmd_response1_re $and$build/ls180/gateware/ls180.v:5705$1418_Y + connect \builder_csrbank4_cmd_response1_we $and$build/ls180/gateware/ls180.v:5706$1422_Y + connect \builder_csrbank4_cmd_response0_r \builder_interface4_bank_bus_dat_w + connect \builder_csrbank4_cmd_response0_re $and$build/ls180/gateware/ls180.v:5708$1425_Y + connect \builder_csrbank4_cmd_response0_we $and$build/ls180/gateware/ls180.v:5709$1429_Y + connect \builder_csrbank4_cmd_event_r \builder_interface4_bank_bus_dat_w [3:0] + connect \builder_csrbank4_cmd_event_re $and$build/ls180/gateware/ls180.v:5711$1432_Y + connect \builder_csrbank4_cmd_event_we $and$build/ls180/gateware/ls180.v:5712$1436_Y + connect \builder_csrbank4_data_event_r \builder_interface4_bank_bus_dat_w [3:0] + connect \builder_csrbank4_data_event_re $and$build/ls180/gateware/ls180.v:5714$1439_Y + connect \builder_csrbank4_data_event_we $and$build/ls180/gateware/ls180.v:5715$1443_Y + connect \builder_csrbank4_block_length1_r \builder_interface4_bank_bus_dat_w [1:0] + connect \builder_csrbank4_block_length1_re $and$build/ls180/gateware/ls180.v:5717$1446_Y + connect \builder_csrbank4_block_length1_we $and$build/ls180/gateware/ls180.v:5718$1450_Y + connect \builder_csrbank4_block_length0_r \builder_interface4_bank_bus_dat_w + connect \builder_csrbank4_block_length0_re $and$build/ls180/gateware/ls180.v:5720$1453_Y + connect \builder_csrbank4_block_length0_we $and$build/ls180/gateware/ls180.v:5721$1457_Y + connect \builder_csrbank4_block_count3_r \builder_interface4_bank_bus_dat_w + connect \builder_csrbank4_block_count3_re $and$build/ls180/gateware/ls180.v:5723$1460_Y + connect \builder_csrbank4_block_count3_we $and$build/ls180/gateware/ls180.v:5724$1464_Y + connect \builder_csrbank4_block_count2_r \builder_interface4_bank_bus_dat_w + connect \builder_csrbank4_block_count2_re $and$build/ls180/gateware/ls180.v:5726$1467_Y + connect \builder_csrbank4_block_count2_we $and$build/ls180/gateware/ls180.v:5727$1471_Y + connect \builder_csrbank4_block_count1_r \builder_interface4_bank_bus_dat_w + connect \builder_csrbank4_block_count1_re $and$build/ls180/gateware/ls180.v:5729$1474_Y + connect \builder_csrbank4_block_count1_we $and$build/ls180/gateware/ls180.v:5730$1478_Y + connect \builder_csrbank4_block_count0_r \builder_interface4_bank_bus_dat_w + connect \builder_csrbank4_block_count0_re $and$build/ls180/gateware/ls180.v:5732$1481_Y + connect \builder_csrbank4_block_count0_we $and$build/ls180/gateware/ls180.v:5733$1485_Y + connect \builder_csrbank4_cmd_argument3_w \libresocsim_sdcore_cmd_argument_storage [31:24] + connect \builder_csrbank4_cmd_argument2_w \libresocsim_sdcore_cmd_argument_storage [23:16] + connect \builder_csrbank4_cmd_argument1_w \libresocsim_sdcore_cmd_argument_storage [15:8] + connect \builder_csrbank4_cmd_argument0_w \libresocsim_sdcore_cmd_argument_storage [7:0] + connect \builder_csrbank4_cmd_command3_w \libresocsim_sdcore_cmd_command_storage [31:24] + connect \builder_csrbank4_cmd_command2_w \libresocsim_sdcore_cmd_command_storage [23:16] + connect \builder_csrbank4_cmd_command1_w \libresocsim_sdcore_cmd_command_storage [15:8] + connect \builder_csrbank4_cmd_command0_w \libresocsim_sdcore_cmd_command_storage [7:0] + connect \builder_csrbank4_cmd_response15_w \libresocsim_sdcore_cmd_response_status [127:120] + connect \builder_csrbank4_cmd_response14_w \libresocsim_sdcore_cmd_response_status [119:112] + connect \builder_csrbank4_cmd_response13_w \libresocsim_sdcore_cmd_response_status [111:104] + connect \builder_csrbank4_cmd_response12_w \libresocsim_sdcore_cmd_response_status [103:96] + connect \builder_csrbank4_cmd_response11_w \libresocsim_sdcore_cmd_response_status [95:88] + connect \builder_csrbank4_cmd_response10_w \libresocsim_sdcore_cmd_response_status [87:80] + connect \builder_csrbank4_cmd_response9_w \libresocsim_sdcore_cmd_response_status [79:72] + connect \builder_csrbank4_cmd_response8_w \libresocsim_sdcore_cmd_response_status [71:64] + connect \builder_csrbank4_cmd_response7_w \libresocsim_sdcore_cmd_response_status [63:56] + connect \builder_csrbank4_cmd_response6_w \libresocsim_sdcore_cmd_response_status [55:48] + connect \builder_csrbank4_cmd_response5_w \libresocsim_sdcore_cmd_response_status [47:40] + connect \builder_csrbank4_cmd_response4_w \libresocsim_sdcore_cmd_response_status [39:32] + connect \builder_csrbank4_cmd_response3_w \libresocsim_sdcore_cmd_response_status [31:24] + connect \builder_csrbank4_cmd_response2_w \libresocsim_sdcore_cmd_response_status [23:16] + connect \builder_csrbank4_cmd_response1_w \libresocsim_sdcore_cmd_response_status [15:8] + connect \builder_csrbank4_cmd_response0_w \libresocsim_sdcore_cmd_response_status [7:0] + connect \libresocsim_sdcore_cmd_response_we \builder_csrbank4_cmd_response0_we + connect \builder_csrbank4_cmd_event_w \libresocsim_sdcore_cmd_event_status + connect \libresocsim_sdcore_cmd_event_we \builder_csrbank4_cmd_event_we + connect \builder_csrbank4_data_event_w \libresocsim_sdcore_data_event_status + connect \libresocsim_sdcore_data_event_we \builder_csrbank4_data_event_we + connect \builder_csrbank4_block_length1_w \libresocsim_sdcore_block_length_storage [9:8] + connect \builder_csrbank4_block_length0_w \libresocsim_sdcore_block_length_storage [7:0] + connect \builder_csrbank4_block_count3_w \libresocsim_sdcore_block_count_storage [31:24] + connect \builder_csrbank4_block_count2_w \libresocsim_sdcore_block_count_storage [23:16] + connect \builder_csrbank4_block_count1_w \libresocsim_sdcore_block_count_storage [15:8] + connect \builder_csrbank4_block_count0_w \libresocsim_sdcore_block_count_storage [7:0] + connect \builder_csrbank5_sel $eq$build/ls180/gateware/ls180.v:5769$1486_Y + connect \builder_csrbank5_dma_base7_r \builder_interface5_bank_bus_dat_w + connect \builder_csrbank5_dma_base7_re $and$build/ls180/gateware/ls180.v:5771$1489_Y + connect \builder_csrbank5_dma_base7_we $and$build/ls180/gateware/ls180.v:5772$1493_Y + connect \builder_csrbank5_dma_base6_r \builder_interface5_bank_bus_dat_w + connect \builder_csrbank5_dma_base6_re $and$build/ls180/gateware/ls180.v:5774$1496_Y + connect \builder_csrbank5_dma_base6_we $and$build/ls180/gateware/ls180.v:5775$1500_Y + connect \builder_csrbank5_dma_base5_r \builder_interface5_bank_bus_dat_w + connect \builder_csrbank5_dma_base5_re $and$build/ls180/gateware/ls180.v:5777$1503_Y + connect \builder_csrbank5_dma_base5_we $and$build/ls180/gateware/ls180.v:5778$1507_Y + connect \builder_csrbank5_dma_base4_r \builder_interface5_bank_bus_dat_w + connect \builder_csrbank5_dma_base4_re $and$build/ls180/gateware/ls180.v:5780$1510_Y + connect \builder_csrbank5_dma_base4_we $and$build/ls180/gateware/ls180.v:5781$1514_Y + connect \builder_csrbank5_dma_base3_r \builder_interface5_bank_bus_dat_w + connect \builder_csrbank5_dma_base3_re $and$build/ls180/gateware/ls180.v:5783$1517_Y + connect \builder_csrbank5_dma_base3_we $and$build/ls180/gateware/ls180.v:5784$1521_Y + connect \builder_csrbank5_dma_base2_r \builder_interface5_bank_bus_dat_w + connect \builder_csrbank5_dma_base2_re $and$build/ls180/gateware/ls180.v:5786$1524_Y + connect \builder_csrbank5_dma_base2_we $and$build/ls180/gateware/ls180.v:5787$1528_Y + connect \builder_csrbank5_dma_base1_r \builder_interface5_bank_bus_dat_w + connect \builder_csrbank5_dma_base1_re $and$build/ls180/gateware/ls180.v:5789$1531_Y + connect \builder_csrbank5_dma_base1_we $and$build/ls180/gateware/ls180.v:5790$1535_Y + connect \builder_csrbank5_dma_base0_r \builder_interface5_bank_bus_dat_w + connect \builder_csrbank5_dma_base0_re $and$build/ls180/gateware/ls180.v:5792$1538_Y + connect \builder_csrbank5_dma_base0_we $and$build/ls180/gateware/ls180.v:5793$1542_Y + connect \builder_csrbank5_dma_length3_r \builder_interface5_bank_bus_dat_w + connect \builder_csrbank5_dma_length3_re $and$build/ls180/gateware/ls180.v:5795$1545_Y + connect \builder_csrbank5_dma_length3_we $and$build/ls180/gateware/ls180.v:5796$1549_Y + connect \builder_csrbank5_dma_length2_r \builder_interface5_bank_bus_dat_w + connect \builder_csrbank5_dma_length2_re $and$build/ls180/gateware/ls180.v:5798$1552_Y + connect \builder_csrbank5_dma_length2_we $and$build/ls180/gateware/ls180.v:5799$1556_Y + connect \builder_csrbank5_dma_length1_r \builder_interface5_bank_bus_dat_w + connect \builder_csrbank5_dma_length1_re $and$build/ls180/gateware/ls180.v:5801$1559_Y + connect \builder_csrbank5_dma_length1_we $and$build/ls180/gateware/ls180.v:5802$1563_Y + connect \builder_csrbank5_dma_length0_r \builder_interface5_bank_bus_dat_w + connect \builder_csrbank5_dma_length0_re $and$build/ls180/gateware/ls180.v:5804$1566_Y + connect \builder_csrbank5_dma_length0_we $and$build/ls180/gateware/ls180.v:5805$1570_Y + connect \builder_csrbank5_dma_enable0_r \builder_interface5_bank_bus_dat_w [0] + connect \builder_csrbank5_dma_enable0_re $and$build/ls180/gateware/ls180.v:5807$1573_Y + connect \builder_csrbank5_dma_enable0_we $and$build/ls180/gateware/ls180.v:5808$1577_Y + connect \builder_csrbank5_dma_done_r \builder_interface5_bank_bus_dat_w [0] + connect \builder_csrbank5_dma_done_re $and$build/ls180/gateware/ls180.v:5810$1580_Y + connect \builder_csrbank5_dma_done_we $and$build/ls180/gateware/ls180.v:5811$1584_Y + connect \builder_csrbank5_dma_loop0_r \builder_interface5_bank_bus_dat_w [0] + connect \builder_csrbank5_dma_loop0_re $and$build/ls180/gateware/ls180.v:5813$1587_Y + connect \builder_csrbank5_dma_loop0_we $and$build/ls180/gateware/ls180.v:5814$1591_Y + connect \builder_csrbank5_dma_offset3_r \builder_interface5_bank_bus_dat_w + connect \builder_csrbank5_dma_offset3_re $and$build/ls180/gateware/ls180.v:5816$1594_Y + connect \builder_csrbank5_dma_offset3_we $and$build/ls180/gateware/ls180.v:5817$1598_Y + connect \builder_csrbank5_dma_offset2_r \builder_interface5_bank_bus_dat_w + connect \builder_csrbank5_dma_offset2_re $and$build/ls180/gateware/ls180.v:5819$1601_Y + connect \builder_csrbank5_dma_offset2_we $and$build/ls180/gateware/ls180.v:5820$1605_Y + connect \builder_csrbank5_dma_offset1_r \builder_interface5_bank_bus_dat_w + connect \builder_csrbank5_dma_offset1_re $and$build/ls180/gateware/ls180.v:5822$1608_Y + connect \builder_csrbank5_dma_offset1_we $and$build/ls180/gateware/ls180.v:5823$1612_Y + connect \builder_csrbank5_dma_offset0_r \builder_interface5_bank_bus_dat_w + connect \builder_csrbank5_dma_offset0_re $and$build/ls180/gateware/ls180.v:5825$1615_Y + connect \builder_csrbank5_dma_offset0_we $and$build/ls180/gateware/ls180.v:5826$1619_Y + connect \builder_csrbank5_dma_base7_w \libresocsim_sdmem2block_dma_base_storage [63:56] + connect \builder_csrbank5_dma_base6_w \libresocsim_sdmem2block_dma_base_storage [55:48] + connect \builder_csrbank5_dma_base5_w \libresocsim_sdmem2block_dma_base_storage [47:40] + connect \builder_csrbank5_dma_base4_w \libresocsim_sdmem2block_dma_base_storage [39:32] + connect \builder_csrbank5_dma_base3_w \libresocsim_sdmem2block_dma_base_storage [31:24] + connect \builder_csrbank5_dma_base2_w \libresocsim_sdmem2block_dma_base_storage [23:16] + connect \builder_csrbank5_dma_base1_w \libresocsim_sdmem2block_dma_base_storage [15:8] + connect \builder_csrbank5_dma_base0_w \libresocsim_sdmem2block_dma_base_storage [7:0] + connect \builder_csrbank5_dma_length3_w \libresocsim_sdmem2block_dma_length_storage [31:24] + connect \builder_csrbank5_dma_length2_w \libresocsim_sdmem2block_dma_length_storage [23:16] + connect \builder_csrbank5_dma_length1_w \libresocsim_sdmem2block_dma_length_storage [15:8] + connect \builder_csrbank5_dma_length0_w \libresocsim_sdmem2block_dma_length_storage [7:0] + connect \builder_csrbank5_dma_enable0_w \libresocsim_sdmem2block_dma_enable_storage + connect \builder_csrbank5_dma_done_w \libresocsim_sdmem2block_dma_done_status + connect \libresocsim_sdmem2block_dma_done_we \builder_csrbank5_dma_done_we + connect \builder_csrbank5_dma_loop0_w \libresocsim_sdmem2block_dma_loop_storage + connect \builder_csrbank5_dma_offset3_w \libresocsim_sdmem2block_dma_offset_status [31:24] + connect \builder_csrbank5_dma_offset2_w \libresocsim_sdmem2block_dma_offset_status [23:16] + connect \builder_csrbank5_dma_offset1_w \libresocsim_sdmem2block_dma_offset_status [15:8] + connect \builder_csrbank5_dma_offset0_w \libresocsim_sdmem2block_dma_offset_status [7:0] + connect \libresocsim_sdmem2block_dma_offset_we \builder_csrbank5_dma_offset0_we + connect \builder_csrbank6_sel $eq$build/ls180/gateware/ls180.v:5848$1620_Y + connect \builder_csrbank6_card_detect_r \builder_interface6_bank_bus_dat_w [0] + connect \builder_csrbank6_card_detect_re $and$build/ls180/gateware/ls180.v:5850$1623_Y + connect \builder_csrbank6_card_detect_we $and$build/ls180/gateware/ls180.v:5851$1627_Y + connect \builder_csrbank6_clocker_divider1_r \builder_interface6_bank_bus_dat_w [0] + connect \builder_csrbank6_clocker_divider1_re $and$build/ls180/gateware/ls180.v:5853$1630_Y + connect \builder_csrbank6_clocker_divider1_we $and$build/ls180/gateware/ls180.v:5854$1634_Y + connect \builder_csrbank6_clocker_divider0_r \builder_interface6_bank_bus_dat_w + connect \builder_csrbank6_clocker_divider0_re $and$build/ls180/gateware/ls180.v:5856$1637_Y + connect \builder_csrbank6_clocker_divider0_we $and$build/ls180/gateware/ls180.v:5857$1641_Y + connect \libresocsim_init_initialize_r \builder_interface6_bank_bus_dat_w [0] + connect \libresocsim_init_initialize_re $and$build/ls180/gateware/ls180.v:5859$1644_Y + connect \libresocsim_init_initialize_we $and$build/ls180/gateware/ls180.v:5860$1648_Y + connect \builder_csrbank6_card_detect_w \libresocsim_status + connect \libresocsim_we \builder_csrbank6_card_detect_we + connect \builder_csrbank6_clocker_divider1_w \libresocsim_clocker_storage [8] + connect \builder_csrbank6_clocker_divider0_w \libresocsim_clocker_storage [7:0] + connect \builder_csrbank7_sel $eq$build/ls180/gateware/ls180.v:5865$1649_Y + connect \builder_csrbank7_dfii_control0_r \builder_interface7_bank_bus_dat_w [3:0] + connect \builder_csrbank7_dfii_control0_re $and$build/ls180/gateware/ls180.v:5867$1652_Y + connect \builder_csrbank7_dfii_control0_we $and$build/ls180/gateware/ls180.v:5868$1656_Y + connect \builder_csrbank7_dfii_pi0_command0_r \builder_interface7_bank_bus_dat_w [5:0] + connect \builder_csrbank7_dfii_pi0_command0_re $and$build/ls180/gateware/ls180.v:5870$1659_Y + connect \builder_csrbank7_dfii_pi0_command0_we $and$build/ls180/gateware/ls180.v:5871$1663_Y + connect \main_sdram_command_issue_r \builder_interface7_bank_bus_dat_w [0] + connect \main_sdram_command_issue_re $and$build/ls180/gateware/ls180.v:5873$1666_Y + connect \main_sdram_command_issue_we $and$build/ls180/gateware/ls180.v:5874$1670_Y + connect \builder_csrbank7_dfii_pi0_address1_r \builder_interface7_bank_bus_dat_w [4:0] + connect \builder_csrbank7_dfii_pi0_address1_re $and$build/ls180/gateware/ls180.v:5876$1673_Y + connect \builder_csrbank7_dfii_pi0_address1_we $and$build/ls180/gateware/ls180.v:5877$1677_Y + connect \builder_csrbank7_dfii_pi0_address0_r \builder_interface7_bank_bus_dat_w + connect \builder_csrbank7_dfii_pi0_address0_re $and$build/ls180/gateware/ls180.v:5879$1680_Y + connect \builder_csrbank7_dfii_pi0_address0_we $and$build/ls180/gateware/ls180.v:5880$1684_Y + connect \builder_csrbank7_dfii_pi0_baddress0_r \builder_interface7_bank_bus_dat_w [1:0] + connect \builder_csrbank7_dfii_pi0_baddress0_re $and$build/ls180/gateware/ls180.v:5882$1687_Y + connect \builder_csrbank7_dfii_pi0_baddress0_we $and$build/ls180/gateware/ls180.v:5883$1691_Y + connect \builder_csrbank7_dfii_pi0_wrdata1_r \builder_interface7_bank_bus_dat_w + connect \builder_csrbank7_dfii_pi0_wrdata1_re $and$build/ls180/gateware/ls180.v:5885$1694_Y + connect \builder_csrbank7_dfii_pi0_wrdata1_we $and$build/ls180/gateware/ls180.v:5886$1698_Y + connect \builder_csrbank7_dfii_pi0_wrdata0_r \builder_interface7_bank_bus_dat_w + connect \builder_csrbank7_dfii_pi0_wrdata0_re $and$build/ls180/gateware/ls180.v:5888$1701_Y + connect \builder_csrbank7_dfii_pi0_wrdata0_we $and$build/ls180/gateware/ls180.v:5889$1705_Y + connect \builder_csrbank7_dfii_pi0_rddata1_r \builder_interface7_bank_bus_dat_w + connect \builder_csrbank7_dfii_pi0_rddata1_re $and$build/ls180/gateware/ls180.v:5891$1708_Y + connect \builder_csrbank7_dfii_pi0_rddata1_we $and$build/ls180/gateware/ls180.v:5892$1712_Y + connect \builder_csrbank7_dfii_pi0_rddata0_r \builder_interface7_bank_bus_dat_w + connect \builder_csrbank7_dfii_pi0_rddata0_re $and$build/ls180/gateware/ls180.v:5894$1715_Y + connect \builder_csrbank7_dfii_pi0_rddata0_we $and$build/ls180/gateware/ls180.v:5895$1719_Y + connect \main_sdram_sel \main_sdram_storage [0] + connect \main_sdram_cke \main_sdram_storage [1] + connect \main_sdram_odt \main_sdram_storage [2] + connect \main_sdram_reset_n \main_sdram_storage [3] + connect \builder_csrbank7_dfii_control0_w \main_sdram_storage + connect \builder_csrbank7_dfii_pi0_command0_w \main_sdram_command_storage + connect \builder_csrbank7_dfii_pi0_address1_w \main_sdram_address_storage [12:8] + connect \builder_csrbank7_dfii_pi0_address0_w \main_sdram_address_storage [7:0] + connect \builder_csrbank7_dfii_pi0_baddress0_w \main_sdram_baddress_storage + connect \builder_csrbank7_dfii_pi0_wrdata1_w \main_sdram_wrdata_storage [15:8] + connect \builder_csrbank7_dfii_pi0_wrdata0_w \main_sdram_wrdata_storage [7:0] + connect \builder_csrbank7_dfii_pi0_rddata1_w \main_sdram_status [15:8] + connect \builder_csrbank7_dfii_pi0_rddata0_w \main_sdram_status [7:0] + connect \main_sdram_we \builder_csrbank7_dfii_pi0_rddata0_we + connect \builder_csrbank8_sel $eq$build/ls180/gateware/ls180.v:5910$1720_Y + connect \builder_csrbank8_control1_r \builder_interface8_bank_bus_dat_w + connect \builder_csrbank8_control1_re $and$build/ls180/gateware/ls180.v:5912$1723_Y + connect \builder_csrbank8_control1_we $and$build/ls180/gateware/ls180.v:5913$1727_Y + connect \builder_csrbank8_control0_r \builder_interface8_bank_bus_dat_w + connect \builder_csrbank8_control0_re $and$build/ls180/gateware/ls180.v:5915$1730_Y + connect \builder_csrbank8_control0_we $and$build/ls180/gateware/ls180.v:5916$1734_Y + connect \builder_csrbank8_status_r \builder_interface8_bank_bus_dat_w [0] + connect \builder_csrbank8_status_re $and$build/ls180/gateware/ls180.v:5918$1737_Y + connect \builder_csrbank8_status_we $and$build/ls180/gateware/ls180.v:5919$1741_Y + connect \builder_csrbank8_mosi0_r \builder_interface8_bank_bus_dat_w + connect \builder_csrbank8_mosi0_re $and$build/ls180/gateware/ls180.v:5921$1744_Y + connect \builder_csrbank8_mosi0_we $and$build/ls180/gateware/ls180.v:5922$1748_Y + connect \builder_csrbank8_miso_r \builder_interface8_bank_bus_dat_w + connect \builder_csrbank8_miso_re $and$build/ls180/gateware/ls180.v:5924$1751_Y + connect \builder_csrbank8_miso_we $and$build/ls180/gateware/ls180.v:5925$1755_Y + connect \builder_csrbank8_cs0_r \builder_interface8_bank_bus_dat_w [0] + connect \builder_csrbank8_cs0_re $and$build/ls180/gateware/ls180.v:5927$1758_Y + connect \builder_csrbank8_cs0_we $and$build/ls180/gateware/ls180.v:5928$1762_Y + connect \builder_csrbank8_loopback0_r \builder_interface8_bank_bus_dat_w [0] + connect \builder_csrbank8_loopback0_re $and$build/ls180/gateware/ls180.v:5930$1765_Y + connect \builder_csrbank8_loopback0_we $and$build/ls180/gateware/ls180.v:5931$1769_Y + connect \main_length1 \main_control_storage [15:8] + connect \builder_csrbank8_control1_w \main_control_storage [15:8] + connect \builder_csrbank8_control0_w \main_control_storage [7:0] + connect \main_status_status \main_done1 + connect \builder_csrbank8_status_w \main_status_status + connect \main_status_we \builder_csrbank8_status_we + connect \builder_csrbank8_mosi0_w \main_mosi_storage + connect \builder_csrbank8_miso_w \main_miso_status + connect \main_miso_we \builder_csrbank8_miso_we + connect \main_sel \main_cs_storage + connect \builder_csrbank8_cs0_w \main_cs_storage + connect \builder_csrbank8_loopback0_w \main_loopback_storage + connect \builder_csrbank9_sel $eq$build/ls180/gateware/ls180.v:5950$1771_Y + connect \builder_csrbank9_control1_r \builder_interface9_bank_bus_dat_w + connect \builder_csrbank9_control1_re $and$build/ls180/gateware/ls180.v:5952$1774_Y + connect \builder_csrbank9_control1_we $and$build/ls180/gateware/ls180.v:5953$1778_Y + connect \builder_csrbank9_control0_r \builder_interface9_bank_bus_dat_w + connect \builder_csrbank9_control0_re $and$build/ls180/gateware/ls180.v:5955$1781_Y + connect \builder_csrbank9_control0_we $and$build/ls180/gateware/ls180.v:5956$1785_Y + connect \builder_csrbank9_status_r \builder_interface9_bank_bus_dat_w [0] + connect \builder_csrbank9_status_re $and$build/ls180/gateware/ls180.v:5958$1788_Y + connect \builder_csrbank9_status_we $and$build/ls180/gateware/ls180.v:5959$1792_Y + connect \builder_csrbank9_mosi0_r \builder_interface9_bank_bus_dat_w + connect \builder_csrbank9_mosi0_re $and$build/ls180/gateware/ls180.v:5961$1795_Y + connect \builder_csrbank9_mosi0_we $and$build/ls180/gateware/ls180.v:5962$1799_Y + connect \builder_csrbank9_miso_r \builder_interface9_bank_bus_dat_w + connect \builder_csrbank9_miso_re $and$build/ls180/gateware/ls180.v:5964$1802_Y + connect \builder_csrbank9_miso_we $and$build/ls180/gateware/ls180.v:5965$1806_Y + connect \builder_csrbank9_cs0_r \builder_interface9_bank_bus_dat_w [0] + connect \builder_csrbank9_cs0_re $and$build/ls180/gateware/ls180.v:5967$1809_Y + connect \builder_csrbank9_cs0_we $and$build/ls180/gateware/ls180.v:5968$1813_Y + connect \builder_csrbank9_loopback0_r \builder_interface9_bank_bus_dat_w [0] + connect \builder_csrbank9_loopback0_re $and$build/ls180/gateware/ls180.v:5970$1816_Y + connect \builder_csrbank9_loopback0_we $and$build/ls180/gateware/ls180.v:5971$1820_Y + connect \builder_csrbank9_clk_divider1_r \builder_interface9_bank_bus_dat_w + connect \builder_csrbank9_clk_divider1_re $and$build/ls180/gateware/ls180.v:5973$1823_Y + connect \builder_csrbank9_clk_divider1_we $and$build/ls180/gateware/ls180.v:5974$1827_Y + connect \builder_csrbank9_clk_divider0_r \builder_interface9_bank_bus_dat_w + connect \builder_csrbank9_clk_divider0_re $and$build/ls180/gateware/ls180.v:5976$1830_Y + connect \builder_csrbank9_clk_divider0_we $and$build/ls180/gateware/ls180.v:5977$1834_Y + connect \libresocsim_length1 \libresocsim_control_storage [15:8] + connect \builder_csrbank9_control1_w \libresocsim_control_storage [15:8] + connect \builder_csrbank9_control0_w \libresocsim_control_storage [7:0] + connect \libresocsim_status_status \libresocsim_done1 + connect \builder_csrbank9_status_w \libresocsim_status_status + connect \libresocsim_status_we \builder_csrbank9_status_we + connect \builder_csrbank9_mosi0_w \libresocsim_mosi_storage + connect \builder_csrbank9_miso_w \libresocsim_miso_status + connect \libresocsim_miso_we \builder_csrbank9_miso_we + connect \libresocsim_sel \libresocsim_cs_storage + connect \builder_csrbank9_cs0_w \libresocsim_cs_storage + connect \builder_csrbank9_loopback0_w \libresocsim_loopback_storage + connect \builder_csrbank9_clk_divider1_w \libresocsim_storage [15:8] + connect \builder_csrbank9_clk_divider0_w \libresocsim_storage [7:0] + connect \builder_csrbank10_sel $eq$build/ls180/gateware/ls180.v:5998$1836_Y + connect \builder_csrbank10_load3_r \builder_interface10_bank_bus_dat_w + connect \builder_csrbank10_load3_re $and$build/ls180/gateware/ls180.v:6000$1839_Y + connect \builder_csrbank10_load3_we $and$build/ls180/gateware/ls180.v:6001$1843_Y + connect \builder_csrbank10_load2_r \builder_interface10_bank_bus_dat_w + connect \builder_csrbank10_load2_re $and$build/ls180/gateware/ls180.v:6003$1846_Y + connect \builder_csrbank10_load2_we $and$build/ls180/gateware/ls180.v:6004$1850_Y + connect \builder_csrbank10_load1_r \builder_interface10_bank_bus_dat_w + connect \builder_csrbank10_load1_re $and$build/ls180/gateware/ls180.v:6006$1853_Y + connect \builder_csrbank10_load1_we $and$build/ls180/gateware/ls180.v:6007$1857_Y + connect \builder_csrbank10_load0_r \builder_interface10_bank_bus_dat_w + connect \builder_csrbank10_load0_re $and$build/ls180/gateware/ls180.v:6009$1860_Y + connect \builder_csrbank10_load0_we $and$build/ls180/gateware/ls180.v:6010$1864_Y + connect \builder_csrbank10_reload3_r \builder_interface10_bank_bus_dat_w + connect \builder_csrbank10_reload3_re $and$build/ls180/gateware/ls180.v:6012$1867_Y + connect \builder_csrbank10_reload3_we $and$build/ls180/gateware/ls180.v:6013$1871_Y + connect \builder_csrbank10_reload2_r \builder_interface10_bank_bus_dat_w + connect \builder_csrbank10_reload2_re $and$build/ls180/gateware/ls180.v:6015$1874_Y + connect \builder_csrbank10_reload2_we $and$build/ls180/gateware/ls180.v:6016$1878_Y + connect \builder_csrbank10_reload1_r \builder_interface10_bank_bus_dat_w + connect \builder_csrbank10_reload1_re $and$build/ls180/gateware/ls180.v:6018$1881_Y + connect \builder_csrbank10_reload1_we $and$build/ls180/gateware/ls180.v:6019$1885_Y + connect \builder_csrbank10_reload0_r \builder_interface10_bank_bus_dat_w + connect \builder_csrbank10_reload0_re $and$build/ls180/gateware/ls180.v:6021$1888_Y + connect \builder_csrbank10_reload0_we $and$build/ls180/gateware/ls180.v:6022$1892_Y + connect \builder_csrbank10_en0_r \builder_interface10_bank_bus_dat_w [0] + connect \builder_csrbank10_en0_re $and$build/ls180/gateware/ls180.v:6024$1895_Y + connect \builder_csrbank10_en0_we $and$build/ls180/gateware/ls180.v:6025$1899_Y + connect \builder_csrbank10_update_value0_r \builder_interface10_bank_bus_dat_w [0] + connect \builder_csrbank10_update_value0_re $and$build/ls180/gateware/ls180.v:6027$1902_Y + connect \builder_csrbank10_update_value0_we $and$build/ls180/gateware/ls180.v:6028$1906_Y + connect \builder_csrbank10_value3_r \builder_interface10_bank_bus_dat_w + connect \builder_csrbank10_value3_re $and$build/ls180/gateware/ls180.v:6030$1909_Y + connect \builder_csrbank10_value3_we $and$build/ls180/gateware/ls180.v:6031$1913_Y + connect \builder_csrbank10_value2_r \builder_interface10_bank_bus_dat_w + connect \builder_csrbank10_value2_re $and$build/ls180/gateware/ls180.v:6033$1916_Y + connect \builder_csrbank10_value2_we $and$build/ls180/gateware/ls180.v:6034$1920_Y + connect \builder_csrbank10_value1_r \builder_interface10_bank_bus_dat_w + connect \builder_csrbank10_value1_re $and$build/ls180/gateware/ls180.v:6036$1923_Y + connect \builder_csrbank10_value1_we $and$build/ls180/gateware/ls180.v:6037$1927_Y + connect \builder_csrbank10_value0_r \builder_interface10_bank_bus_dat_w + connect \builder_csrbank10_value0_re $and$build/ls180/gateware/ls180.v:6039$1930_Y + connect \builder_csrbank10_value0_we $and$build/ls180/gateware/ls180.v:6040$1934_Y + connect \main_libresocsim_timer_eventmanager_status_r \builder_interface10_bank_bus_dat_w [0] + connect \main_libresocsim_timer_eventmanager_status_re $and$build/ls180/gateware/ls180.v:6042$1937_Y + connect \main_libresocsim_timer_eventmanager_status_we $and$build/ls180/gateware/ls180.v:6043$1941_Y + connect \main_libresocsim_timer_eventmanager_pending_r \builder_interface10_bank_bus_dat_w [0] + connect \main_libresocsim_timer_eventmanager_pending_re $and$build/ls180/gateware/ls180.v:6045$1944_Y + connect \main_libresocsim_timer_eventmanager_pending_we $and$build/ls180/gateware/ls180.v:6046$1948_Y + connect \builder_csrbank10_ev_enable0_r \builder_interface10_bank_bus_dat_w [0] + connect \builder_csrbank10_ev_enable0_re $and$build/ls180/gateware/ls180.v:6048$1951_Y + connect \builder_csrbank10_ev_enable0_we $and$build/ls180/gateware/ls180.v:6049$1955_Y + connect \builder_csrbank10_load3_w \main_libresocsim_timer_load_storage [31:24] + connect \builder_csrbank10_load2_w \main_libresocsim_timer_load_storage [23:16] + connect \builder_csrbank10_load1_w \main_libresocsim_timer_load_storage [15:8] + connect \builder_csrbank10_load0_w \main_libresocsim_timer_load_storage [7:0] + connect \builder_csrbank10_reload3_w \main_libresocsim_timer_reload_storage [31:24] + connect \builder_csrbank10_reload2_w \main_libresocsim_timer_reload_storage [23:16] + connect \builder_csrbank10_reload1_w \main_libresocsim_timer_reload_storage [15:8] + connect \builder_csrbank10_reload0_w \main_libresocsim_timer_reload_storage [7:0] + connect \builder_csrbank10_en0_w \main_libresocsim_timer_en_storage + connect \builder_csrbank10_update_value0_w \main_libresocsim_timer_update_value_storage + connect \builder_csrbank10_value3_w \main_libresocsim_timer_value_status [31:24] + connect \builder_csrbank10_value2_w \main_libresocsim_timer_value_status [23:16] + connect \builder_csrbank10_value1_w \main_libresocsim_timer_value_status [15:8] + connect \builder_csrbank10_value0_w \main_libresocsim_timer_value_status [7:0] + connect \main_libresocsim_timer_value_we \builder_csrbank10_value0_we + connect \builder_csrbank10_ev_enable0_w \main_libresocsim_timer_eventmanager_storage + connect \builder_csrbank11_sel $eq$build/ls180/gateware/ls180.v:6066$1956_Y + connect \main_libresocsim_uart_rxtx_r \builder_interface11_bank_bus_dat_w + connect \main_libresocsim_uart_rxtx_re $and$build/ls180/gateware/ls180.v:6068$1959_Y + connect \main_libresocsim_uart_rxtx_we $and$build/ls180/gateware/ls180.v:6069$1963_Y + connect \builder_csrbank11_txfull_r \builder_interface11_bank_bus_dat_w [0] + connect \builder_csrbank11_txfull_re $and$build/ls180/gateware/ls180.v:6071$1966_Y + connect \builder_csrbank11_txfull_we $and$build/ls180/gateware/ls180.v:6072$1970_Y + connect \builder_csrbank11_rxempty_r \builder_interface11_bank_bus_dat_w [0] + connect \builder_csrbank11_rxempty_re $and$build/ls180/gateware/ls180.v:6074$1973_Y + connect \builder_csrbank11_rxempty_we $and$build/ls180/gateware/ls180.v:6075$1977_Y + connect \main_libresocsim_uart_eventmanager_status_r \builder_interface11_bank_bus_dat_w [1:0] + connect \main_libresocsim_uart_eventmanager_status_re $and$build/ls180/gateware/ls180.v:6077$1980_Y + connect \main_libresocsim_uart_eventmanager_status_we $and$build/ls180/gateware/ls180.v:6078$1984_Y + connect \main_libresocsim_uart_eventmanager_pending_r \builder_interface11_bank_bus_dat_w [1:0] + connect \main_libresocsim_uart_eventmanager_pending_re $and$build/ls180/gateware/ls180.v:6080$1987_Y + connect \main_libresocsim_uart_eventmanager_pending_we $and$build/ls180/gateware/ls180.v:6081$1991_Y + connect \builder_csrbank11_ev_enable0_r \builder_interface11_bank_bus_dat_w [1:0] + connect \builder_csrbank11_ev_enable0_re $and$build/ls180/gateware/ls180.v:6083$1994_Y + connect \builder_csrbank11_ev_enable0_we $and$build/ls180/gateware/ls180.v:6084$1998_Y + connect \builder_csrbank11_txempty_r \builder_interface11_bank_bus_dat_w [0] + connect \builder_csrbank11_txempty_re $and$build/ls180/gateware/ls180.v:6086$2001_Y + connect \builder_csrbank11_txempty_we $and$build/ls180/gateware/ls180.v:6087$2005_Y + connect \builder_csrbank11_rxfull_r \builder_interface11_bank_bus_dat_w [0] + connect \builder_csrbank11_rxfull_re $and$build/ls180/gateware/ls180.v:6089$2008_Y + connect \builder_csrbank11_rxfull_we $and$build/ls180/gateware/ls180.v:6090$2012_Y + connect \builder_csrbank11_txfull_w \main_libresocsim_uart_txfull_status + connect \main_libresocsim_uart_txfull_we \builder_csrbank11_txfull_we + connect \builder_csrbank11_rxempty_w \main_libresocsim_uart_rxempty_status + connect \main_libresocsim_uart_rxempty_we \builder_csrbank11_rxempty_we + connect \builder_csrbank11_ev_enable0_w \main_libresocsim_uart_eventmanager_storage + connect \builder_csrbank11_txempty_w \main_libresocsim_uart_txempty_status + connect \main_libresocsim_uart_txempty_we \builder_csrbank11_txempty_we + connect \builder_csrbank11_rxfull_w \main_libresocsim_uart_rxfull_status + connect \main_libresocsim_uart_rxfull_we \builder_csrbank11_rxfull_we + connect \builder_csrbank12_sel $eq$build/ls180/gateware/ls180.v:6100$2013_Y + connect \builder_csrbank12_tuning_word3_r \builder_interface12_bank_bus_dat_w + connect \builder_csrbank12_tuning_word3_re $and$build/ls180/gateware/ls180.v:6102$2016_Y + connect \builder_csrbank12_tuning_word3_we $and$build/ls180/gateware/ls180.v:6103$2020_Y + connect \builder_csrbank12_tuning_word2_r \builder_interface12_bank_bus_dat_w + connect \builder_csrbank12_tuning_word2_re $and$build/ls180/gateware/ls180.v:6105$2023_Y + connect \builder_csrbank12_tuning_word2_we $and$build/ls180/gateware/ls180.v:6106$2027_Y + connect \builder_csrbank12_tuning_word1_r \builder_interface12_bank_bus_dat_w + connect \builder_csrbank12_tuning_word1_re $and$build/ls180/gateware/ls180.v:6108$2030_Y + connect \builder_csrbank12_tuning_word1_we $and$build/ls180/gateware/ls180.v:6109$2034_Y + connect \builder_csrbank12_tuning_word0_r \builder_interface12_bank_bus_dat_w + connect \builder_csrbank12_tuning_word0_re $and$build/ls180/gateware/ls180.v:6111$2037_Y + connect \builder_csrbank12_tuning_word0_we $and$build/ls180/gateware/ls180.v:6112$2041_Y + connect \builder_csrbank12_tuning_word3_w \main_libresocsim_storage [31:24] + connect \builder_csrbank12_tuning_word2_w \main_libresocsim_storage [23:16] + connect \builder_csrbank12_tuning_word1_w \main_libresocsim_storage [15:8] + connect \builder_csrbank12_tuning_word0_w \main_libresocsim_storage [7:0] + connect \builder_csr_interconnect_adr \builder_libresocsim_adr + connect \builder_csr_interconnect_we \builder_libresocsim_we + connect \builder_csr_interconnect_dat_w \builder_libresocsim_dat_w + connect \builder_libresocsim_dat_r \builder_csr_interconnect_dat_r + connect \builder_interface0_bank_bus_adr \builder_csr_interconnect_adr + connect \builder_interface1_bank_bus_adr \builder_csr_interconnect_adr + connect \builder_interface2_bank_bus_adr \builder_csr_interconnect_adr + connect \builder_interface3_bank_bus_adr \builder_csr_interconnect_adr + connect \builder_interface4_bank_bus_adr \builder_csr_interconnect_adr + connect \builder_interface5_bank_bus_adr \builder_csr_interconnect_adr + connect \builder_interface6_bank_bus_adr \builder_csr_interconnect_adr + connect \builder_interface7_bank_bus_adr \builder_csr_interconnect_adr + connect \builder_interface8_bank_bus_adr \builder_csr_interconnect_adr + connect \builder_interface9_bank_bus_adr \builder_csr_interconnect_adr + connect \builder_interface10_bank_bus_adr \builder_csr_interconnect_adr + connect \builder_interface11_bank_bus_adr \builder_csr_interconnect_adr + connect \builder_interface12_bank_bus_adr \builder_csr_interconnect_adr + connect \builder_interface0_bank_bus_we \builder_csr_interconnect_we + connect \builder_interface1_bank_bus_we \builder_csr_interconnect_we + connect \builder_interface2_bank_bus_we \builder_csr_interconnect_we + connect \builder_interface3_bank_bus_we \builder_csr_interconnect_we + connect \builder_interface4_bank_bus_we \builder_csr_interconnect_we + connect \builder_interface5_bank_bus_we \builder_csr_interconnect_we + connect \builder_interface6_bank_bus_we \builder_csr_interconnect_we + connect \builder_interface7_bank_bus_we \builder_csr_interconnect_we + connect \builder_interface8_bank_bus_we \builder_csr_interconnect_we + connect \builder_interface9_bank_bus_we \builder_csr_interconnect_we + connect \builder_interface10_bank_bus_we \builder_csr_interconnect_we + connect \builder_interface11_bank_bus_we \builder_csr_interconnect_we + connect \builder_interface12_bank_bus_we \builder_csr_interconnect_we + connect \builder_interface0_bank_bus_dat_w \builder_csr_interconnect_dat_w + connect \builder_interface1_bank_bus_dat_w \builder_csr_interconnect_dat_w + connect \builder_interface2_bank_bus_dat_w \builder_csr_interconnect_dat_w + connect \builder_interface3_bank_bus_dat_w \builder_csr_interconnect_dat_w + connect \builder_interface4_bank_bus_dat_w \builder_csr_interconnect_dat_w + connect \builder_interface5_bank_bus_dat_w \builder_csr_interconnect_dat_w + connect \builder_interface6_bank_bus_dat_w \builder_csr_interconnect_dat_w + connect \builder_interface7_bank_bus_dat_w \builder_csr_interconnect_dat_w + connect \builder_interface8_bank_bus_dat_w \builder_csr_interconnect_dat_w + connect \builder_interface9_bank_bus_dat_w \builder_csr_interconnect_dat_w + connect \builder_interface10_bank_bus_dat_w \builder_csr_interconnect_dat_w + connect \builder_interface11_bank_bus_dat_w \builder_csr_interconnect_dat_w + connect \builder_interface12_bank_bus_dat_w \builder_csr_interconnect_dat_w + connect \builder_csr_interconnect_dat_r $or$build/ls180/gateware/ls180.v:6160$2053_Y + connect \main_libresocsim_rx \builder_multiregimpl0_regs1 + connect \sdrio_clk \sys_clk_1 + connect \sdrio_clk_1 \sys_clk_1 + connect \sdrio_clk_2 \sys_clk_1 + connect \sdrio_clk_3 \sys_clk_1 + connect \sdrio_clk_4 \sys_clk_1 + connect \sdrio_clk_5 \sys_clk_1 + connect \sdrio_clk_6 \sys_clk_1 + connect \sdrio_clk_7 \sys_clk_1 + connect \sdrio_clk_8 \sys_clk_1 + connect \sdrio_clk_9 \sys_clk_1 + connect \sdrio_clk_10 \sys_clk_1 + connect \sdrio_clk_11 \sys_clk_1 + connect \sdrio_clk_12 \sys_clk_1 + connect \sdrio_clk_13 \sys_clk_1 + connect \sdrio_clk_14 \sys_clk_1 + connect \sdrio_clk_15 \sys_clk_1 + connect \sdrio_clk_16 \sys_clk_1 + connect \sdrio_clk_17 \sys_clk_1 + connect \sdrio_clk_18 \sys_clk_1 + connect \sdrio_clk_19 \sys_clk_1 + connect \sdrio_clk_20 \sys_clk_1 + connect \sdrio_clk_21 \sys_clk_1 + connect \sdrio_clk_22 \sys_clk_1 + connect \sdrio_clk_23 \sys_clk_1 + connect \sdrio_clk_24 \sys_clk_1 + connect \sdrio_clk_25 \sys_clk_1 + connect \sdrio_clk_26 \sys_clk_1 + connect \sdrio_clk_27 \sys_clk_1 + connect \sdrio_clk_28 \sys_clk_1 + connect \sdrio_clk_29 \sys_clk_1 + connect \sdrio_clk_30 \sys_clk_1 + connect \sdrio_clk_31 \sys_clk_1 + connect \sdrio_clk_32 \sys_clk_1 + connect \sdrio_clk_33 \sys_clk_1 + connect \sdrio_clk_34 \sys_clk_1 + connect \sdrio_clk_35 \sys_clk_1 + connect \main_gpio_in_status \builder_multiregimpl1_regs1 + connect \main_gpio_out_status \builder_multiregimpl2_regs1 + connect \sdrio_clk_36 \sys_clk_1 + connect \sdrio_clk_37 \sys_clk_1 + connect \sdrio_clk_38 \sys_clk_1 + connect \sdrio_clk_39 \sys_clk_1 + connect \sdrio_clk_40 \sys_clk_1 + connect \sdrio_clk_41 \sys_clk_1 + connect \sdrio_clk_42 \sys_clk_1 + connect \sdrio_clk_43 \sys_clk_1 + connect \sdrio_clk_44 \sys_clk_1 + connect \sdrio_clk_45 \sys_clk_1 + connect \sdrio_clk_46 \sys_clk_1 + connect \sdrio_clk_47 \sys_clk_1 + connect \sdrio_clk_48 \sys_clk_1 + connect \sdrio_clk_49 \sys_clk_1 + connect \sdrio_clk_50 \sys_clk_1 + connect \sdrio_clk_51 \sys_clk_1 + connect \sdrio_clk_52 \sys_clk_1 + connect \sdrio_clk_53 \sys_clk_1 + connect \sdrio_clk_54 \sys_clk_1 + connect \sdrio_clk_55 \sys_clk_1 + connect \sdrio_clk_56 \sys_clk_1 + connect \sdrio_clk_57 \sys_clk_1 + connect \sdrio_clk_58 \sys_clk_1 + connect \sdrio_clk_59 \sys_clk_1 + connect \sdrio_clk_60 \sys_clk_1 + connect \sdrio_clk_61 \sys_clk_1 + connect \sdrio_clk_62 \sys_clk_1 + connect \sdrio_clk_63 \sys_clk_1 + connect \sdrio_clk_64 \sys_clk_1 + connect \sdrio_clk_65 \sys_clk_1 + connect \sdrio_clk_66 \sys_clk_1 + connect \sdrio_clk_67 \sys_clk_1 + connect \sdrio_clk_68 \sys_clk_1 + connect \sdrio_clk_69 \sys_clk_1 + connect \sdrio_clk_70 \sys_clk_1 + connect \sdrio_clk_71 \sys_clk_1 + connect \sdrio_clk_72 \sys_clk_1 + connect \sdrio_clk_73 \sys_clk_1 + connect \sdrio_clk_74 \sys_clk_1 + connect \sdrio_clk_75 \sys_clk_1 + connect \sdrio_clk_76 \sys_clk_1 + connect \sdrio_clk_77 \sys_clk_1 + connect \sdrio_clk_78 \sys_clk_1 + connect \sdrio_clk_79 \sys_clk_1 + connect \sdrio_clk_80 \sys_clk_1 + connect \sdrio_clk_81 \sys_clk_1 + connect \sdrio_clk_82 \sys_clk_1 + connect \sdrio_clk_83 \sys_clk_1 + connect \main_libresocsim_dat_r $memrd$\mem$build/ls180/gateware/ls180.v:9379$2472_DATA + connect \main_libresocsim_uart_tx_fifo_wrport_dat_r \memdat + connect \main_libresocsim_uart_tx_fifo_rdport_dat_r \memdat_1 + connect \main_libresocsim_uart_rx_fifo_wrport_dat_r \memdat_2 + connect \main_libresocsim_uart_rx_fifo_rdport_dat_r \memdat_3 + connect \main_sdram_bankmachine0_cmd_buffer_lookahead_wrport_dat_r \memdat_4 + connect \main_sdram_bankmachine0_cmd_buffer_lookahead_rdport_dat_r $memrd$\storage_2$build/ls180/gateware/ls180.v:9431$2493_DATA + connect \main_sdram_bankmachine1_cmd_buffer_lookahead_wrport_dat_r \memdat_5 + connect \main_sdram_bankmachine1_cmd_buffer_lookahead_rdport_dat_r $memrd$\storage_3$build/ls180/gateware/ls180.v:9445$2500_DATA + connect \main_sdram_bankmachine2_cmd_buffer_lookahead_wrport_dat_r \memdat_6 + connect \main_sdram_bankmachine2_cmd_buffer_lookahead_rdport_dat_r $memrd$\storage_4$build/ls180/gateware/ls180.v:9459$2507_DATA + connect \main_sdram_bankmachine3_cmd_buffer_lookahead_wrport_dat_r \memdat_7 + connect \main_sdram_bankmachine3_cmd_buffer_lookahead_rdport_dat_r $memrd$\storage_5$build/ls180/gateware/ls180.v:9473$2514_DATA + connect \libresocsim_sdblock2mem_fifo_wrport_dat_r \memdat_8 + connect \libresocsim_sdblock2mem_fifo_rdport_dat_r $memrd$\storage_6$build/ls180/gateware/ls180.v:9487$2521_DATA + connect \libresocsim_sdmem2block_fifo_wrport_dat_r \memdat_9 + connect \libresocsim_sdmem2block_fifo_rdport_dat_r $memrd$\storage_7$build/ls180/gateware/ls180.v:9501$2528_DATA + connect \sdram_dq [0] $ternary$build/ls180/gateware/ls180.v:9564$2530_Y + connect \builder_inferedsdrtristate0__i \sdram_dq [0] + connect \sdram_dq [1] $ternary$build/ls180/gateware/ls180.v:9567$2531_Y + connect \builder_inferedsdrtristate1__i \sdram_dq [1] + connect \sdram_dq [2] $ternary$build/ls180/gateware/ls180.v:9570$2532_Y + connect \builder_inferedsdrtristate2__i \sdram_dq [2] + connect \sdram_dq [3] $ternary$build/ls180/gateware/ls180.v:9573$2533_Y + connect \builder_inferedsdrtristate3__i \sdram_dq [3] + connect \sdram_dq [4] $ternary$build/ls180/gateware/ls180.v:9576$2534_Y + connect \builder_inferedsdrtristate4__i \sdram_dq [4] + connect \sdram_dq [5] $ternary$build/ls180/gateware/ls180.v:9579$2535_Y + connect \builder_inferedsdrtristate5__i \sdram_dq [5] + connect \sdram_dq [6] $ternary$build/ls180/gateware/ls180.v:9582$2536_Y + connect \builder_inferedsdrtristate6__i \sdram_dq [6] + connect \sdram_dq [7] $ternary$build/ls180/gateware/ls180.v:9585$2537_Y + connect \builder_inferedsdrtristate7__i \sdram_dq [7] + connect \sdram_dq [8] $ternary$build/ls180/gateware/ls180.v:9588$2538_Y + connect \builder_inferedsdrtristate8__i \sdram_dq [8] + connect \sdram_dq [9] $ternary$build/ls180/gateware/ls180.v:9591$2539_Y + connect \builder_inferedsdrtristate9__i \sdram_dq [9] + connect \sdram_dq [10] $ternary$build/ls180/gateware/ls180.v:9594$2540_Y + connect \builder_inferedsdrtristate10__i \sdram_dq [10] + connect \sdram_dq [11] $ternary$build/ls180/gateware/ls180.v:9597$2541_Y + connect \builder_inferedsdrtristate11__i \sdram_dq [11] + connect \sdram_dq [12] $ternary$build/ls180/gateware/ls180.v:9600$2542_Y + connect \builder_inferedsdrtristate12__i \sdram_dq [12] + connect \sdram_dq [13] $ternary$build/ls180/gateware/ls180.v:9603$2543_Y + connect \builder_inferedsdrtristate13__i \sdram_dq [13] + connect \sdram_dq [14] $ternary$build/ls180/gateware/ls180.v:9606$2544_Y + connect \builder_inferedsdrtristate14__i \sdram_dq [14] + connect \sdram_dq [15] $ternary$build/ls180/gateware/ls180.v:9609$2545_Y + connect \builder_inferedsdrtristate15__i \sdram_dq [15] + connect \sdcard_cmd $ternary$build/ls180/gateware/ls180.v:9612$2546_Y + connect \builder_inferedsdrtristate16__i \sdcard_cmd + connect \sdcard_data [0] $ternary$build/ls180/gateware/ls180.v:9615$2547_Y + connect \builder_inferedsdrtristate17__i \sdcard_data [0] + connect \sdcard_data [1] $ternary$build/ls180/gateware/ls180.v:9618$2548_Y + connect \builder_inferedsdrtristate18__i \sdcard_data [1] + connect \sdcard_data [2] $ternary$build/ls180/gateware/ls180.v:9621$2549_Y + connect \builder_inferedsdrtristate19__i \sdcard_data [2] + connect \sdcard_data [3] $ternary$build/ls180/gateware/ls180.v:9624$2550_Y + connect \builder_inferedsdrtristate20__i \sdcard_data [3] +end +attribute \src "issuer_ls180.v:130593.1-130651.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.fus.ldst0.lsd_l" +attribute \generator "nMigen" +module \lsd_l + attribute \src "issuer_ls180.v:130594.7-130594.20" + wire $0\initial[0:0] + attribute \src "issuer_ls180.v:130639.3-130647.6" + wire $0\q_int$next[0:0]$6138 + attribute \src "issuer_ls180.v:130637.3-130638.27" + wire $0\q_int[0:0] + attribute \src "issuer_ls180.v:130639.3-130647.6" + wire $1\q_int$next[0:0]$6139 + attribute \src "issuer_ls180.v:130616.7-130616.19" + wire $1\q_int[0:0] + attribute \src "issuer_ls180.v:130629.17-130629.96" + wire $and$issuer_ls180.v:130629$6128_Y + attribute \src "issuer_ls180.v:130634.17-130634.96" + wire $and$issuer_ls180.v:130634$6133_Y + attribute \src "issuer_ls180.v:130631.18-130631.93" + wire $not$issuer_ls180.v:130631$6130_Y + attribute \src "issuer_ls180.v:130633.17-130633.92" + wire $not$issuer_ls180.v:130633$6132_Y + attribute \src "issuer_ls180.v:130636.17-130636.92" + wire $not$issuer_ls180.v:130636$6135_Y + attribute \src "issuer_ls180.v:130630.18-130630.98" + wire $or$issuer_ls180.v:130630$6129_Y + attribute \src "issuer_ls180.v:130632.18-130632.99" + wire $or$issuer_ls180.v:130632$6131_Y + attribute \src "issuer_ls180.v:130635.17-130635.97" + wire $or$issuer_ls180.v:130635$6134_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire \$13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" + wire input 5 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" + wire input 1 \coresync_rst + attribute \src "issuer_ls180.v:130594.7-130594.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire output 4 \q_lsd + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" + wire \qlq_lsd + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + wire \qn_lsd + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire input 3 \r_lsd + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire input 2 \s_lsd + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $and $and$issuer_ls180.v:130629$6128 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$7 + connect \Y $and$issuer_ls180.v:130629$6128_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $and $and$issuer_ls180.v:130634$6133 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$1 + connect \Y $and$issuer_ls180.v:130634$6133_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + cell $not $not$issuer_ls180.v:130631$6130 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_lsd + connect \Y $not$issuer_ls180.v:130631$6130_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $not $not$issuer_ls180.v:130633$6132 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_lsd + connect \Y $not$issuer_ls180.v:130633$6132_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $not $not$issuer_ls180.v:130636$6135 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_lsd + connect \Y $not$issuer_ls180.v:130636$6135_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $or $or$issuer_ls180.v:130630$6129 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$9 + connect \B \s_lsd + connect \Y $or$issuer_ls180.v:130630$6129_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + cell $or $or$issuer_ls180.v:130632$6131 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_lsd + connect \B \q_int + connect \Y $or$issuer_ls180.v:130632$6131_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $or $or$issuer_ls180.v:130635$6134 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$3 + connect \B \s_lsd + connect \Y $or$issuer_ls180.v:130635$6134_Y + end + attribute \src "issuer_ls180.v:130594.7-130594.20" + process $proc$issuer_ls180.v:130594$6140 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "issuer_ls180.v:130616.7-130616.19" + process $proc$issuer_ls180.v:130616$6141 + assign { } { } + assign $1\q_int[0:0] 1'0 + sync always + sync init + update \q_int $1\q_int[0:0] + end + attribute \src "issuer_ls180.v:130637.3-130638.27" + process $proc$issuer_ls180.v:130637$6136 + assign { } { } + assign $0\q_int[0:0] \q_int$next + sync posedge \coresync_clk + update \q_int $0\q_int[0:0] + end + attribute \src "issuer_ls180.v:130639.3-130647.6" + process $proc$issuer_ls180.v:130639$6137 + assign { } { } + assign { } { } + assign $0\q_int$next[0:0]$6138 $1\q_int$next[0:0]$6139 + attribute \src "issuer_ls180.v:130640.5-130640.29" + switch \initial + attribute \src "issuer_ls180.v:130640.9-130640.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\q_int$next[0:0]$6139 1'0 + case + assign $1\q_int$next[0:0]$6139 \$5 + end + sync always + update \q_int$next $0\q_int$next[0:0]$6138 + end + connect \$9 $and$issuer_ls180.v:130629$6128_Y + connect \$11 $or$issuer_ls180.v:130630$6129_Y + connect \$13 $not$issuer_ls180.v:130631$6130_Y + connect \$15 $or$issuer_ls180.v:130632$6131_Y + connect \$1 $not$issuer_ls180.v:130633$6132_Y + connect \$3 $and$issuer_ls180.v:130634$6133_Y + connect \$5 $or$issuer_ls180.v:130635$6134_Y + connect \$7 $not$issuer_ls180.v:130636$6135_Y + connect \qlq_lsd \$15 + connect \qn_lsd \$13 + connect \q_lsd \$11 +end +attribute \src "issuer_ls180.v:130655.1-131121.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.l0.lsmem" +attribute \generator "nMigen" +module \lsmem + attribute \src "issuer_ls180.v:131004.3-131024.6" + wire width 45 $0\dbus__adr$next[44:0]$6222 + attribute \src "issuer_ls180.v:130890.3-130891.35" + wire width 45 $0\dbus__adr[44:0] + attribute \src "issuer_ls180.v:130900.3-130922.6" + wire $0\dbus__cyc$next[0:0]$6201 + attribute \src "issuer_ls180.v:130898.3-130899.35" + wire $0\dbus__cyc[0:0] + attribute \src "issuer_ls180.v:131046.3-131066.6" + wire width 64 $0\dbus__dat_w$next[63:0]$6230 + attribute \src "issuer_ls180.v:130886.3-130887.39" + wire width 64 $0\dbus__dat_w[63:0] + attribute \src "issuer_ls180.v:130958.3-130983.6" + wire width 8 $0\dbus__sel$next[7:0]$6212 + attribute \src "issuer_ls180.v:130894.3-130895.35" + wire width 8 $0\dbus__sel[7:0] + attribute \src "issuer_ls180.v:130923.3-130945.6" + wire $0\dbus__stb$next[0:0]$6206 + attribute \src "issuer_ls180.v:130896.3-130897.35" + wire $0\dbus__stb[0:0] + attribute \src "issuer_ls180.v:131025.3-131045.6" + wire $0\dbus__we$next[0:0]$6226 + attribute \src "issuer_ls180.v:130888.3-130889.33" + wire $0\dbus__we[0:0] + attribute \src "issuer_ls180.v:130656.7-130656.20" + wire $0\initial[0:0] + attribute \src "issuer_ls180.v:131103.3-131117.6" + wire width 45 $0\m_badaddr_o$next[44:0]$6242 + attribute \src "issuer_ls180.v:130880.3-130881.39" + wire width 45 $0\m_badaddr_o[44:0] + attribute \src "issuer_ls180.v:130946.3-130957.6" + wire $0\m_busy_o[0:0] + attribute \src "issuer_ls180.v:130984.3-131003.6" + wire width 64 $0\m_ld_data_o$next[63:0]$6217 + attribute \src "issuer_ls180.v:130892.3-130893.39" + wire width 64 $0\m_ld_data_o[63:0] + attribute \src "issuer_ls180.v:131067.3-131084.6" + wire $0\m_load_err_o$next[0:0]$6234 + attribute \src "issuer_ls180.v:130884.3-130885.41" + wire $0\m_load_err_o[0:0] + attribute \src "issuer_ls180.v:131085.3-131102.6" + wire $0\m_store_err_o$next[0:0]$6238 + attribute \src "issuer_ls180.v:130882.3-130883.43" + wire $0\m_store_err_o[0:0] + attribute \src "issuer_ls180.v:131004.3-131024.6" + wire width 45 $1\dbus__adr$next[44:0]$6223 + attribute \src "issuer_ls180.v:130761.14-130761.42" + wire width 45 $1\dbus__adr[44:0] + attribute \src "issuer_ls180.v:130900.3-130922.6" + wire $1\dbus__cyc$next[0:0]$6202 + attribute \src "issuer_ls180.v:130766.7-130766.23" + wire $1\dbus__cyc[0:0] + attribute \src "issuer_ls180.v:131046.3-131066.6" + wire width 64 $1\dbus__dat_w$next[63:0]$6231 + attribute \src "issuer_ls180.v:130773.14-130773.48" + wire width 64 $1\dbus__dat_w[63:0] + attribute \src "issuer_ls180.v:130958.3-130983.6" + wire width 8 $1\dbus__sel$next[7:0]$6213 + attribute \src "issuer_ls180.v:130780.13-130780.30" + wire width 8 $1\dbus__sel[7:0] + attribute \src "issuer_ls180.v:130923.3-130945.6" + wire $1\dbus__stb$next[0:0]$6207 + attribute \src "issuer_ls180.v:130785.7-130785.23" + wire $1\dbus__stb[0:0] + attribute \src "issuer_ls180.v:131025.3-131045.6" + wire $1\dbus__we$next[0:0]$6227 + attribute \src "issuer_ls180.v:130790.7-130790.22" + wire $1\dbus__we[0:0] + attribute \src "issuer_ls180.v:131103.3-131117.6" + wire width 45 $1\m_badaddr_o$next[44:0]$6243 + attribute \src "issuer_ls180.v:130794.14-130794.44" + wire width 45 $1\m_badaddr_o[44:0] + attribute \src "issuer_ls180.v:130946.3-130957.6" + wire $1\m_busy_o[0:0] + attribute \src "issuer_ls180.v:130984.3-131003.6" + wire width 64 $1\m_ld_data_o$next[63:0]$6218 + attribute \src "issuer_ls180.v:130801.14-130801.48" + wire width 64 $1\m_ld_data_o[63:0] + attribute \src "issuer_ls180.v:131067.3-131084.6" + wire $1\m_load_err_o$next[0:0]$6235 + attribute \src "issuer_ls180.v:130805.7-130805.26" + wire $1\m_load_err_o[0:0] + attribute \src "issuer_ls180.v:131085.3-131102.6" + wire $1\m_store_err_o$next[0:0]$6239 + attribute \src "issuer_ls180.v:130811.7-130811.27" + wire $1\m_store_err_o[0:0] + attribute \src "issuer_ls180.v:131004.3-131024.6" + wire width 45 $2\dbus__adr$next[44:0]$6224 + attribute \src "issuer_ls180.v:130900.3-130922.6" + wire $2\dbus__cyc$next[0:0]$6203 + attribute \src "issuer_ls180.v:131046.3-131066.6" + wire width 64 $2\dbus__dat_w$next[63:0]$6232 + attribute \src "issuer_ls180.v:130958.3-130983.6" + wire width 8 $2\dbus__sel$next[7:0]$6214 + attribute \src "issuer_ls180.v:130923.3-130945.6" + wire $2\dbus__stb$next[0:0]$6208 + attribute \src "issuer_ls180.v:131025.3-131045.6" + wire $2\dbus__we$next[0:0]$6228 + attribute \src "issuer_ls180.v:131103.3-131117.6" + wire width 45 $2\m_badaddr_o$next[44:0]$6244 + attribute \src "issuer_ls180.v:130984.3-131003.6" + wire width 64 $2\m_ld_data_o$next[63:0]$6219 + attribute \src "issuer_ls180.v:131067.3-131084.6" + wire $2\m_load_err_o$next[0:0]$6236 + attribute \src "issuer_ls180.v:131085.3-131102.6" + wire $2\m_store_err_o$next[0:0]$6240 + attribute \src "issuer_ls180.v:130900.3-130922.6" + wire $3\dbus__cyc$next[0:0]$6204 + attribute \src "issuer_ls180.v:130958.3-130983.6" + wire width 8 $3\dbus__sel$next[7:0]$6215 + attribute \src "issuer_ls180.v:130923.3-130945.6" + wire $3\dbus__stb$next[0:0]$6209 + attribute \src "issuer_ls180.v:130984.3-131003.6" + wire width 64 $3\m_ld_data_o$next[63:0]$6220 + attribute \src "issuer_ls180.v:130836.18-130836.116" + wire $and$issuer_ls180.v:130836$6146_Y + attribute \src "issuer_ls180.v:130839.18-130839.111" + wire $and$issuer_ls180.v:130839$6149_Y + attribute \src "issuer_ls180.v:130844.18-130844.116" + wire $and$issuer_ls180.v:130844$6154_Y + attribute \src "issuer_ls180.v:130846.18-130846.111" + wire $and$issuer_ls180.v:130846$6156_Y + attribute \src "issuer_ls180.v:130848.17-130848.114" + wire $and$issuer_ls180.v:130848$6158_Y + attribute \src "issuer_ls180.v:130852.18-130852.116" + wire $and$issuer_ls180.v:130852$6162_Y + attribute \src "issuer_ls180.v:130854.18-130854.111" + wire $and$issuer_ls180.v:130854$6164_Y + attribute \src "issuer_ls180.v:130860.18-130860.116" + wire $and$issuer_ls180.v:130860$6170_Y + attribute \src "issuer_ls180.v:130862.18-130862.111" + wire $and$issuer_ls180.v:130862$6172_Y + attribute \src "issuer_ls180.v:130864.18-130864.116" + wire $and$issuer_ls180.v:130864$6174_Y + attribute \src "issuer_ls180.v:130866.18-130866.111" + wire $and$issuer_ls180.v:130866$6176_Y + attribute \src "issuer_ls180.v:130868.18-130868.116" + wire $and$issuer_ls180.v:130868$6178_Y + attribute \src "issuer_ls180.v:130870.17-130870.108" + wire $and$issuer_ls180.v:130870$6180_Y + attribute \src "issuer_ls180.v:130871.18-130871.111" + wire $and$issuer_ls180.v:130871$6181_Y + attribute \src "issuer_ls180.v:130872.18-130872.120" + wire $and$issuer_ls180.v:130872$6182_Y + attribute \src "issuer_ls180.v:130875.18-130875.120" + wire $and$issuer_ls180.v:130875$6185_Y + attribute \src "issuer_ls180.v:130877.18-130877.120" + wire $and$issuer_ls180.v:130877$6187_Y + attribute \src "issuer_ls180.v:130833.18-130833.110" + wire $not$issuer_ls180.v:130833$6143_Y + attribute \src "issuer_ls180.v:130838.18-130838.110" + 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$and$issuer_ls180.v:130836$6146 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$15 + connect \B \x_valid_i + connect \Y $and$issuer_ls180.v:130836$6146_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113" + cell $and $and$issuer_ls180.v:130839$6149 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$17 + connect \B \$19 + connect \Y $and$issuer_ls180.v:130839$6149_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113" + cell $and $and$issuer_ls180.v:130844$6154 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$29 + connect \B \x_valid_i + connect \Y $and$issuer_ls180.v:130844$6154_Y + end + attribute \src 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end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113" + cell $and $and$issuer_ls180.v:130854$6164 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$45 + connect \B \$47 + connect \Y $and$issuer_ls180.v:130854$6164_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113" + cell $and $and$issuer_ls180.v:130860$6170 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$57 + connect \B \x_valid_i + connect \Y $and$issuer_ls180.v:130860$6170_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113" + cell $and $and$issuer_ls180.v:130862$6172 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$59 + connect \B \$61 + connect \Y $and$issuer_ls180.v:130862$6172_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113" + cell $and $and$issuer_ls180.v:130864$6174 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$65 + connect \B \x_valid_i + connect \Y $and$issuer_ls180.v:130864$6174_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113" + cell $and $and$issuer_ls180.v:130866$6176 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$67 + connect \B \$69 + connect \Y $and$issuer_ls180.v:130866$6176_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113" + cell $and $and$issuer_ls180.v:130868$6178 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$73 + connect \B \x_valid_i + connect \Y $and$issuer_ls180.v:130868$6178_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113" + cell $and $and$issuer_ls180.v:130870$6180 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$3 + connect \B \$5 + connect \Y $and$issuer_ls180.v:130870$6180_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113" + cell $and $and$issuer_ls180.v:130871$6181 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$75 + connect \B \$77 + connect \Y $and$issuer_ls180.v:130871$6181_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:131" + cell $and $and$issuer_ls180.v:130872$6182 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dbus__cyc + connect \B \dbus__err + connect \Y $and$issuer_ls180.v:130872$6182_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:131" + cell $and $and$issuer_ls180.v:130875$6185 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dbus__cyc + connect \B \dbus__err + connect \Y $and$issuer_ls180.v:130875$6185_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:131" + cell $and $and$issuer_ls180.v:130877$6187 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dbus__cyc + connect \B \dbus__err + connect \Y $and$issuer_ls180.v:130877$6187_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:105" + cell $not $not$issuer_ls180.v:130833$6143 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \m_valid_i + connect \Y $not$issuer_ls180.v:130833$6143_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113" + cell $not $not$issuer_ls180.v:130838$6148 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \x_stall_i + connect \Y $not$issuer_ls180.v:130838$6148_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:105" + cell $not $not$issuer_ls180.v:130841$6151 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \m_valid_i + connect \Y $not$issuer_ls180.v:130841$6151_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113" + cell $not $not$issuer_ls180.v:130845$6155 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \x_stall_i + connect \Y $not$issuer_ls180.v:130845$6155_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:105" + cell $not $not$issuer_ls180.v:130849$6159 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \m_valid_i + connect \Y $not$issuer_ls180.v:130849$6159_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113" + cell $not $not$issuer_ls180.v:130853$6163 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \x_stall_i + connect \Y $not$issuer_ls180.v:130853$6163_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:105" + cell $not $not$issuer_ls180.v:130856$6166 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \m_valid_i + connect \Y $not$issuer_ls180.v:130856$6166_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113" + cell $not $not$issuer_ls180.v:130859$6169 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \x_stall_i + connect \Y $not$issuer_ls180.v:130859$6169_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113" + cell $not $not$issuer_ls180.v:130861$6171 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \x_stall_i + connect \Y $not$issuer_ls180.v:130861$6171_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113" + cell $not $not$issuer_ls180.v:130865$6175 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \x_stall_i + connect \Y $not$issuer_ls180.v:130865$6175_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113" + cell $not $not$issuer_ls180.v:130869$6179 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \x_stall_i + connect \Y $not$issuer_ls180.v:130869$6179_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:137" + cell $not $not$issuer_ls180.v:130873$6183 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \m_stall_i + connect \Y $not$issuer_ls180.v:130873$6183_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:133" + cell $not $not$issuer_ls180.v:130874$6184 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dbus__we + connect \Y $not$issuer_ls180.v:130874$6184_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:137" + cell $not $not$issuer_ls180.v:130876$6186 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \m_stall_i + connect \Y $not$issuer_ls180.v:130876$6186_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:137" + cell $not $not$issuer_ls180.v:130878$6188 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \m_stall_i + connect \Y $not$issuer_ls180.v:130878$6188_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:105" + cell $or $or$issuer_ls180.v:130832$6142 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dbus__ack + connect \B \dbus__err + connect \Y $or$issuer_ls180.v:130832$6142_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:105" + cell $or $or$issuer_ls180.v:130834$6144 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$9 + connect \B \$11 + connect \Y $or$issuer_ls180.v:130834$6144_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113" + cell $or $or$issuer_ls180.v:130835$6145 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \x_ld_i + connect \B \x_st_i + connect \Y $or$issuer_ls180.v:130835$6145_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113" + cell $or $or$issuer_ls180.v:130837$6147 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \x_ld_i + connect \B \x_st_i + connect \Y $or$issuer_ls180.v:130837$6147_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:105" + cell $or $or$issuer_ls180.v:130840$6150 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dbus__ack + connect \B \dbus__err + connect \Y $or$issuer_ls180.v:130840$6150_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:105" + cell $or $or$issuer_ls180.v:130842$6152 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$23 + connect \B \$25 + connect \Y $or$issuer_ls180.v:130842$6152_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113" + cell $or $or$issuer_ls180.v:130843$6153 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \x_ld_i + connect \B \x_st_i + connect \Y $or$issuer_ls180.v:130843$6153_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:105" + cell $or $or$issuer_ls180.v:130847$6157 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dbus__ack + connect \B \dbus__err + connect \Y $or$issuer_ls180.v:130847$6157_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:105" + cell $or $or$issuer_ls180.v:130850$6160 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$37 + connect \B \$39 + connect \Y $or$issuer_ls180.v:130850$6160_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113" + cell $or $or$issuer_ls180.v:130851$6161 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \x_ld_i + connect \B \x_st_i + connect \Y $or$issuer_ls180.v:130851$6161_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:105" + cell $or $or$issuer_ls180.v:130855$6165 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dbus__ack + connect \B \dbus__err + connect \Y $or$issuer_ls180.v:130855$6165_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:105" + cell $or $or$issuer_ls180.v:130857$6167 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$51 + connect \B \$53 + connect \Y $or$issuer_ls180.v:130857$6167_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113" + cell $or $or$issuer_ls180.v:130858$6168 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \x_ld_i + connect \B \x_st_i + connect \Y $or$issuer_ls180.v:130858$6168_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113" + cell $or $or$issuer_ls180.v:130863$6173 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \x_ld_i + connect \B \x_st_i + connect \Y $or$issuer_ls180.v:130863$6173_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113" + cell $or $or$issuer_ls180.v:130867$6177 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \x_ld_i + connect \B \x_st_i + connect \Y $or$issuer_ls180.v:130867$6177_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:145" + cell $or $or$issuer_ls180.v:130879$6189 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \m_load_err_o + connect \B \m_store_err_o + connect \Y $or$issuer_ls180.v:130879$6189_Y + end + attribute \src "issuer_ls180.v:130656.7-130656.20" + process $proc$issuer_ls180.v:130656$6245 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "issuer_ls180.v:130761.14-130761.42" + process $proc$issuer_ls180.v:130761$6246 + assign { } { } + assign $1\dbus__adr[44:0] 45'000000000000000000000000000000000000000000000 + sync always + sync init + update \dbus__adr $1\dbus__adr[44:0] + end + attribute \src "issuer_ls180.v:130766.7-130766.23" + process $proc$issuer_ls180.v:130766$6247 + assign { } { } + assign $1\dbus__cyc[0:0] 1'0 + sync always + sync init + update \dbus__cyc $1\dbus__cyc[0:0] + end + attribute \src "issuer_ls180.v:130773.14-130773.48" + process $proc$issuer_ls180.v:130773$6248 + assign { } { } + assign $1\dbus__dat_w[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \dbus__dat_w $1\dbus__dat_w[63:0] + end + attribute \src "issuer_ls180.v:130780.13-130780.30" + process $proc$issuer_ls180.v:130780$6249 + assign { } { } + assign $1\dbus__sel[7:0] 8'00000000 + sync always + sync init + update \dbus__sel $1\dbus__sel[7:0] + end + attribute \src "issuer_ls180.v:130785.7-130785.23" + process $proc$issuer_ls180.v:130785$6250 + assign { } { } + assign $1\dbus__stb[0:0] 1'0 + sync always + sync init + update \dbus__stb $1\dbus__stb[0:0] + end + attribute \src "issuer_ls180.v:130790.7-130790.22" + process $proc$issuer_ls180.v:130790$6251 + assign { } { } + assign $1\dbus__we[0:0] 1'0 + sync always + sync init + update \dbus__we $1\dbus__we[0:0] + end + attribute \src "issuer_ls180.v:130794.14-130794.44" + process $proc$issuer_ls180.v:130794$6252 + assign { } { } + assign $1\m_badaddr_o[44:0] 45'000000000000000000000000000000000000000000000 + sync always + sync init + update \m_badaddr_o $1\m_badaddr_o[44:0] + end + attribute \src "issuer_ls180.v:130801.14-130801.48" + process $proc$issuer_ls180.v:130801$6253 + assign { } { } + assign $1\m_ld_data_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \m_ld_data_o $1\m_ld_data_o[63:0] + end + attribute \src "issuer_ls180.v:130805.7-130805.26" + process $proc$issuer_ls180.v:130805$6254 + assign { } { } + assign $1\m_load_err_o[0:0] 1'0 + sync always + sync init + update \m_load_err_o $1\m_load_err_o[0:0] + end + attribute \src "issuer_ls180.v:130811.7-130811.27" + process $proc$issuer_ls180.v:130811$6255 + assign { } { } + assign $1\m_store_err_o[0:0] 1'0 + sync always + sync init + update \m_store_err_o $1\m_store_err_o[0:0] + end + attribute \src "issuer_ls180.v:130880.3-130881.39" + process $proc$issuer_ls180.v:130880$6190 + assign { } { } + assign $0\m_badaddr_o[44:0] \m_badaddr_o$next + sync posedge \coresync_clk + update \m_badaddr_o $0\m_badaddr_o[44:0] + end + attribute \src "issuer_ls180.v:130882.3-130883.43" + process $proc$issuer_ls180.v:130882$6191 + assign { } { } + assign $0\m_store_err_o[0:0] \m_store_err_o$next + sync posedge \coresync_clk + update \m_store_err_o $0\m_store_err_o[0:0] + end + attribute \src "issuer_ls180.v:130884.3-130885.41" + process $proc$issuer_ls180.v:130884$6192 + assign { } { } + assign $0\m_load_err_o[0:0] \m_load_err_o$next + sync posedge \coresync_clk + update \m_load_err_o $0\m_load_err_o[0:0] + end + attribute \src "issuer_ls180.v:130886.3-130887.39" + process $proc$issuer_ls180.v:130886$6193 + assign { } { } + assign $0\dbus__dat_w[63:0] \dbus__dat_w$next + sync posedge \coresync_clk + update \dbus__dat_w $0\dbus__dat_w[63:0] + end + attribute \src "issuer_ls180.v:130888.3-130889.33" + process $proc$issuer_ls180.v:130888$6194 + assign { } { } + assign $0\dbus__we[0:0] \dbus__we$next + sync posedge \coresync_clk + update \dbus__we $0\dbus__we[0:0] + end + attribute \src "issuer_ls180.v:130890.3-130891.35" + process $proc$issuer_ls180.v:130890$6195 + assign { } { } + assign $0\dbus__adr[44:0] \dbus__adr$next + sync posedge \coresync_clk + update \dbus__adr $0\dbus__adr[44:0] + end + attribute \src "issuer_ls180.v:130892.3-130893.39" + process $proc$issuer_ls180.v:130892$6196 + assign { } { } + assign $0\m_ld_data_o[63:0] \m_ld_data_o$next + sync posedge \coresync_clk + update \m_ld_data_o $0\m_ld_data_o[63:0] + end + attribute \src "issuer_ls180.v:130894.3-130895.35" + process $proc$issuer_ls180.v:130894$6197 + assign { } { } + assign $0\dbus__sel[7:0] \dbus__sel$next + sync posedge \coresync_clk + update \dbus__sel $0\dbus__sel[7:0] + end + attribute \src "issuer_ls180.v:130896.3-130897.35" + process $proc$issuer_ls180.v:130896$6198 + assign { } { } + assign $0\dbus__stb[0:0] \dbus__stb$next + sync posedge \coresync_clk + update \dbus__stb $0\dbus__stb[0:0] + end + attribute \src "issuer_ls180.v:130898.3-130899.35" + process $proc$issuer_ls180.v:130898$6199 + assign { } { } + assign $0\dbus__cyc[0:0] \dbus__cyc$next + sync posedge \coresync_clk + update \dbus__cyc $0\dbus__cyc[0:0] + end + attribute \src "issuer_ls180.v:130900.3-130922.6" + process $proc$issuer_ls180.v:130900$6200 + assign { } { } + assign { } { } + assign { } { } + assign $0\dbus__cyc$next[0:0]$6201 $3\dbus__cyc$next[0:0]$6204 + attribute \src "issuer_ls180.v:130901.5-130901.29" + switch \initial + attribute \src "issuer_ls180.v:130901.9-130901.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:104" + switch { \$7 \dbus__cyc } + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\dbus__cyc$next[0:0]$6202 $2\dbus__cyc$next[0:0]$6203 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:105" + switch \$13 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\dbus__cyc$next[0:0]$6203 1'0 + case + assign $2\dbus__cyc$next[0:0]$6203 \dbus__cyc + end + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\dbus__cyc$next[0:0]$6202 1'1 + case + assign $1\dbus__cyc$next[0:0]$6202 \dbus__cyc + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\dbus__cyc$next[0:0]$6204 1'0 + case + assign $3\dbus__cyc$next[0:0]$6204 $1\dbus__cyc$next[0:0]$6202 + end + sync always + update \dbus__cyc$next $0\dbus__cyc$next[0:0]$6201 + end + attribute \src "issuer_ls180.v:130923.3-130945.6" + process $proc$issuer_ls180.v:130923$6205 + assign { } { } + assign { } { } + assign { } { } + assign $0\dbus__stb$next[0:0]$6206 $3\dbus__stb$next[0:0]$6209 + attribute \src "issuer_ls180.v:130924.5-130924.29" + switch \initial + attribute \src "issuer_ls180.v:130924.9-130924.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:104" + switch { \$21 \dbus__cyc } + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\dbus__stb$next[0:0]$6207 $2\dbus__stb$next[0:0]$6208 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:105" + switch \$27 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\dbus__stb$next[0:0]$6208 1'0 + case + assign $2\dbus__stb$next[0:0]$6208 \dbus__stb + end + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\dbus__stb$next[0:0]$6207 1'1 + case + assign $1\dbus__stb$next[0:0]$6207 \dbus__stb + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\dbus__stb$next[0:0]$6209 1'0 + case + assign $3\dbus__stb$next[0:0]$6209 $1\dbus__stb$next[0:0]$6207 + end + sync always + update \dbus__stb$next $0\dbus__stb$next[0:0]$6206 + end + attribute \src "issuer_ls180.v:130946.3-130957.6" + process $proc$issuer_ls180.v:130946$6210 + assign { } { } + assign $0\m_busy_o[0:0] $1\m_busy_o[0:0] + attribute \src "issuer_ls180.v:130947.5-130947.29" + switch \initial + attribute \src "issuer_ls180.v:130947.9-130947.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:145" + switch \$95 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\m_busy_o[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case + assign { } { } + assign $1\m_busy_o[0:0] \dbus__cyc + end + sync always + update \m_busy_o $0\m_busy_o[0:0] + end + attribute \src "issuer_ls180.v:130958.3-130983.6" + process $proc$issuer_ls180.v:130958$6211 + assign { } { } + assign { } { } + assign { } { } + assign $0\dbus__sel$next[7:0]$6212 $3\dbus__sel$next[7:0]$6215 + attribute \src "issuer_ls180.v:130959.5-130959.29" + switch \initial + attribute \src "issuer_ls180.v:130959.9-130959.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:104" + switch { \$35 \dbus__cyc } + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\dbus__sel$next[7:0]$6213 $2\dbus__sel$next[7:0]$6214 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:105" + switch \$41 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\dbus__sel$next[7:0]$6214 8'00000000 + case + assign $2\dbus__sel$next[7:0]$6214 \dbus__sel + end + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\dbus__sel$next[7:0]$6213 \x_mask_i + attribute \src "issuer_ls180.v:0.0-0.0" + case + assign { } { } + assign $1\dbus__sel$next[7:0]$6213 8'00000000 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\dbus__sel$next[7:0]$6215 8'00000000 + case + assign $3\dbus__sel$next[7:0]$6215 $1\dbus__sel$next[7:0]$6213 + end + sync always + update \dbus__sel$next $0\dbus__sel$next[7:0]$6212 + end + attribute \src "issuer_ls180.v:130984.3-131003.6" + process $proc$issuer_ls180.v:130984$6216 + assign { } { } + assign { } { } + assign { } { } + assign $0\m_ld_data_o$next[63:0]$6217 $3\m_ld_data_o$next[63:0]$6220 + attribute \src "issuer_ls180.v:130985.5-130985.29" + switch \initial + attribute \src "issuer_ls180.v:130985.9-130985.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:104" + switch { \$49 \dbus__cyc } + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\m_ld_data_o$next[63:0]$6218 $2\m_ld_data_o$next[63:0]$6219 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:105" + switch \$55 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\m_ld_data_o$next[63:0]$6219 \dbus__dat_r + case + assign $2\m_ld_data_o$next[63:0]$6219 \m_ld_data_o + end + case + assign $1\m_ld_data_o$next[63:0]$6218 \m_ld_data_o + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\m_ld_data_o$next[63:0]$6220 64'0000000000000000000000000000000000000000000000000000000000000000 + case + assign $3\m_ld_data_o$next[63:0]$6220 $1\m_ld_data_o$next[63:0]$6218 + end + sync always + update \m_ld_data_o$next $0\m_ld_data_o$next[63:0]$6217 + end + attribute \src "issuer_ls180.v:131004.3-131024.6" + process $proc$issuer_ls180.v:131004$6221 + assign { } { } + assign { } { } + assign { } { } + assign $0\dbus__adr$next[44:0]$6222 $2\dbus__adr$next[44:0]$6224 + attribute \src "issuer_ls180.v:131005.5-131005.29" + switch \initial + attribute \src "issuer_ls180.v:131005.9-131005.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:104" + switch { \$63 \dbus__cyc } + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'-1 + assign $1\dbus__adr$next[44:0]$6223 \dbus__adr + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\dbus__adr$next[44:0]$6223 \x_addr_i [47:3] + attribute \src "issuer_ls180.v:0.0-0.0" + case + assign { } { } + assign $1\dbus__adr$next[44:0]$6223 45'000000000000000000000000000000000000000000000 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\dbus__adr$next[44:0]$6224 45'000000000000000000000000000000000000000000000 + case + assign $2\dbus__adr$next[44:0]$6224 $1\dbus__adr$next[44:0]$6223 + end + sync always + update \dbus__adr$next $0\dbus__adr$next[44:0]$6222 + end + attribute \src "issuer_ls180.v:131025.3-131045.6" + process $proc$issuer_ls180.v:131025$6225 + assign { } { } + assign { } { } + assign { } { } + assign $0\dbus__we$next[0:0]$6226 $2\dbus__we$next[0:0]$6228 + attribute \src "issuer_ls180.v:131026.5-131026.29" + switch \initial + attribute \src "issuer_ls180.v:131026.9-131026.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:104" + switch { \$71 \dbus__cyc } + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'-1 + assign $1\dbus__we$next[0:0]$6227 \dbus__we + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\dbus__we$next[0:0]$6227 \x_st_i + attribute \src "issuer_ls180.v:0.0-0.0" + case + assign { } { } + assign $1\dbus__we$next[0:0]$6227 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\dbus__we$next[0:0]$6228 1'0 + case + assign $2\dbus__we$next[0:0]$6228 $1\dbus__we$next[0:0]$6227 + end + sync always + update \dbus__we$next $0\dbus__we$next[0:0]$6226 + end + attribute \src "issuer_ls180.v:131046.3-131066.6" + process $proc$issuer_ls180.v:131046$6229 + assign { } { } + assign { } { } + assign { } { } + assign $0\dbus__dat_w$next[63:0]$6230 $2\dbus__dat_w$next[63:0]$6232 + attribute \src "issuer_ls180.v:131047.5-131047.29" + switch \initial + attribute \src "issuer_ls180.v:131047.9-131047.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:104" + switch { \$79 \dbus__cyc } + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'-1 + assign $1\dbus__dat_w$next[63:0]$6231 \dbus__dat_w + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\dbus__dat_w$next[63:0]$6231 \x_st_data_i + attribute \src "issuer_ls180.v:0.0-0.0" + case + assign { } { } + assign $1\dbus__dat_w$next[63:0]$6231 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\dbus__dat_w$next[63:0]$6232 64'0000000000000000000000000000000000000000000000000000000000000000 + case + assign $2\dbus__dat_w$next[63:0]$6232 $1\dbus__dat_w$next[63:0]$6231 + end + sync always + update \dbus__dat_w$next $0\dbus__dat_w$next[63:0]$6230 + end + attribute \src "issuer_ls180.v:131067.3-131084.6" + process $proc$issuer_ls180.v:131067$6233 + assign { } { } + assign { } { } + assign { } { } + assign $0\m_load_err_o$next[0:0]$6234 $2\m_load_err_o$next[0:0]$6236 + attribute \src "issuer_ls180.v:131068.5-131068.29" + switch \initial + attribute \src "issuer_ls180.v:131068.9-131068.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:131" + switch { \$83 \$81 } + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\m_load_err_o$next[0:0]$6235 \$85 + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\m_load_err_o$next[0:0]$6235 1'0 + case + assign $1\m_load_err_o$next[0:0]$6235 \m_load_err_o + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\m_load_err_o$next[0:0]$6236 1'0 + case + assign $2\m_load_err_o$next[0:0]$6236 $1\m_load_err_o$next[0:0]$6235 + end + sync always + update \m_load_err_o$next $0\m_load_err_o$next[0:0]$6234 + end + attribute \src "issuer_ls180.v:131085.3-131102.6" + process $proc$issuer_ls180.v:131085$6237 + assign { } { } + assign { } { } + assign { } { } + assign $0\m_store_err_o$next[0:0]$6238 $2\m_store_err_o$next[0:0]$6240 + attribute \src "issuer_ls180.v:131086.5-131086.29" + switch \initial + attribute \src "issuer_ls180.v:131086.9-131086.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:131" + switch { \$89 \$87 } + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\m_store_err_o$next[0:0]$6239 \dbus__we + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\m_store_err_o$next[0:0]$6239 1'0 + case + assign $1\m_store_err_o$next[0:0]$6239 \m_store_err_o + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\m_store_err_o$next[0:0]$6240 1'0 + case + assign $2\m_store_err_o$next[0:0]$6240 $1\m_store_err_o$next[0:0]$6239 + end + sync always + update \m_store_err_o$next $0\m_store_err_o$next[0:0]$6238 + end + attribute \src "issuer_ls180.v:131103.3-131117.6" + process $proc$issuer_ls180.v:131103$6241 + assign { } { } + assign { } { } + assign { } { } + assign $0\m_badaddr_o$next[44:0]$6242 $2\m_badaddr_o$next[44:0]$6244 + attribute \src "issuer_ls180.v:131104.5-131104.29" + switch \initial + attribute \src "issuer_ls180.v:131104.9-131104.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:131" + switch { \$93 \$91 } + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\m_badaddr_o$next[44:0]$6243 \dbus__adr + case + assign $1\m_badaddr_o$next[44:0]$6243 \m_badaddr_o + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\m_badaddr_o$next[44:0]$6244 45'000000000000000000000000000000000000000000000 + case + assign $2\m_badaddr_o$next[44:0]$6244 $1\m_badaddr_o$next[44:0]$6243 + end + sync always + update \m_badaddr_o$next $0\m_badaddr_o$next[44:0]$6242 + end + connect \$9 $or$issuer_ls180.v:130832$6142_Y + connect \$11 $not$issuer_ls180.v:130833$6143_Y + connect \$13 $or$issuer_ls180.v:130834$6144_Y + connect \$15 $or$issuer_ls180.v:130835$6145_Y + connect \$17 $and$issuer_ls180.v:130836$6146_Y + connect \$1 $or$issuer_ls180.v:130837$6147_Y + connect \$19 $not$issuer_ls180.v:130838$6148_Y + connect \$21 $and$issuer_ls180.v:130839$6149_Y + connect \$23 $or$issuer_ls180.v:130840$6150_Y + connect \$25 $not$issuer_ls180.v:130841$6151_Y + connect \$27 $or$issuer_ls180.v:130842$6152_Y + connect \$29 $or$issuer_ls180.v:130843$6153_Y + connect \$31 $and$issuer_ls180.v:130844$6154_Y + connect \$33 $not$issuer_ls180.v:130845$6155_Y + connect \$35 $and$issuer_ls180.v:130846$6156_Y + connect \$37 $or$issuer_ls180.v:130847$6157_Y + connect \$3 $and$issuer_ls180.v:130848$6158_Y + connect \$39 $not$issuer_ls180.v:130849$6159_Y + connect \$41 $or$issuer_ls180.v:130850$6160_Y + connect \$43 $or$issuer_ls180.v:130851$6161_Y + connect \$45 $and$issuer_ls180.v:130852$6162_Y + connect \$47 $not$issuer_ls180.v:130853$6163_Y + connect \$49 $and$issuer_ls180.v:130854$6164_Y + connect \$51 $or$issuer_ls180.v:130855$6165_Y + connect \$53 $not$issuer_ls180.v:130856$6166_Y + connect \$55 $or$issuer_ls180.v:130857$6167_Y + connect \$57 $or$issuer_ls180.v:130858$6168_Y + connect \$5 $not$issuer_ls180.v:130859$6169_Y + connect \$59 $and$issuer_ls180.v:130860$6170_Y + connect \$61 $not$issuer_ls180.v:130861$6171_Y + connect \$63 $and$issuer_ls180.v:130862$6172_Y + connect \$65 $or$issuer_ls180.v:130863$6173_Y + connect \$67 $and$issuer_ls180.v:130864$6174_Y + connect \$69 $not$issuer_ls180.v:130865$6175_Y + connect \$71 $and$issuer_ls180.v:130866$6176_Y + connect \$73 $or$issuer_ls180.v:130867$6177_Y + connect \$75 $and$issuer_ls180.v:130868$6178_Y + connect \$77 $not$issuer_ls180.v:130869$6179_Y + connect \$7 $and$issuer_ls180.v:130870$6180_Y + connect \$79 $and$issuer_ls180.v:130871$6181_Y + connect \$81 $and$issuer_ls180.v:130872$6182_Y + connect \$83 $not$issuer_ls180.v:130873$6183_Y + connect \$85 $not$issuer_ls180.v:130874$6184_Y + connect \$87 $and$issuer_ls180.v:130875$6185_Y + connect \$89 $not$issuer_ls180.v:130876$6186_Y + connect \$91 $and$issuer_ls180.v:130877$6187_Y + connect \$93 $not$issuer_ls180.v:130878$6188_Y + connect \$95 $or$issuer_ls180.v:130879$6189_Y + connect \x_stall_i 1'0 + connect \m_stall_i 1'0 + connect \x_busy_o \dbus__cyc +end +attribute \src "issuer_ls180.v:131125.1-132080.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.fus.alu0.alu_alu0.pipe1.main" +attribute \generator "nMigen" +module \main + attribute \src "issuer_ls180.v:131652.3-131674.6" + wire width 64 $0\a_i[63:0] + attribute \src "issuer_ls180.v:131751.3-131777.6" + wire $0\a_lt[0:0] + attribute \src "issuer_ls180.v:132032.3-132042.6" + wire width 64 $0\a_n[63:0] + attribute \src "issuer_ls180.v:132002.3-132011.6" + wire width 66 $0\add_a[65:0] + attribute \src "issuer_ls180.v:132012.3-132021.6" + wire width 66 $0\add_b[65:0] + attribute \src "issuer_ls180.v:132022.3-132031.6" + wire width 66 $0\add_o[65:0] + attribute \src "issuer_ls180.v:131890.3-131912.6" + wire width 64 $0\b_i[63:0] + attribute \src "issuer_ls180.v:131876.3-131889.6" + wire width 2 $0\ca[1:0] + attribute \src "issuer_ls180.v:132043.3-132053.6" + wire $0\carry_32[0:0] + attribute \src "issuer_ls180.v:132054.3-132064.6" + wire $0\carry_64[0:0] + attribute \src "issuer_ls180.v:131778.3-131803.6" + wire width 4 $0\cr_a[3:0] + attribute \src "issuer_ls180.v:131804.3-131818.6" + wire $0\cr_a_ok[0:0] + attribute \src "issuer_ls180.v:131982.3-132001.6" + wire width 8 $0\eqs[7:0] + attribute \src "issuer_ls180.v:131126.7-131126.20" + wire $0\initial[0:0] + attribute \src "issuer_ls180.v:131642.3-131651.6" + wire $0\is_32bit[0:0] + attribute \src "issuer_ls180.v:131713.3-131731.6" + wire $0\msb_a[0:0] + attribute \src "issuer_ls180.v:131732.3-131750.6" + wire $0\msb_b[0:0] + attribute \src "issuer_ls180.v:131819.3-131856.6" + wire width 64 $0\o[63:0] + attribute \src "issuer_ls180.v:131857.3-131875.6" + wire $0\o_ok[0:0] + attribute \src "issuer_ls180.v:131935.3-131948.6" + wire width 2 $0\ov[1:0] + attribute \src "issuer_ls180.v:131971.3-131981.6" + wire width 8 $0\src1[7:0] + attribute \src "issuer_ls180.v:131686.3-131712.6" + wire width 5 $0\tval[4:0] + attribute \src "issuer_ls180.v:131913.3-131923.6" + wire width 2 $0\xer_ca$20[1:0]$6331 + attribute \src "issuer_ls180.v:131924.3-131934.6" + wire $0\xer_ca_ok[0:0] + attribute \src "issuer_ls180.v:131949.3-131959.6" + wire width 2 $0\xer_ov[1:0] + attribute \src "issuer_ls180.v:131960.3-131970.6" + wire $0\xer_ov_ok[0:0] + attribute \src "issuer_ls180.v:131675.3-131685.6" + wire $0\zerohi[0:0] + attribute \src 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"/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:61" + wire width 64 \a_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:95" + wire \a_lt + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:93" + wire width 64 \a_n + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:57" + wire width 66 \add_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:58" + wire width 66 \add_b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:59" + wire width 66 \add_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 input 17 \alu_op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 output 40 \alu_op__data_len$18 + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 input 2 \alu_op__fn_unit + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 output 25 \alu_op__fn_unit$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 input 3 \alu_op__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 output 26 \alu_op__imm_data__data$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 4 \alu_op__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 27 \alu_op__imm_data__ok$5 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 input 13 \alu_op__input_carry + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 output 36 \alu_op__input_carry$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 18 \alu_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 output 41 \alu_op__insn$19 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 input 1 \alu_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 output 24 \alu_op__insn_type$2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 9 \alu_op__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 32 \alu_op__invert_in$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 11 \alu_op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 34 \alu_op__invert_out$12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 15 \alu_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 38 \alu_op__is_32bit$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 16 \alu_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 39 \alu_op__is_signed$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 7 \alu_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 30 \alu_op__oe__oe$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 8 \alu_op__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 31 \alu_op__oe__ok$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 14 \alu_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 37 \alu_op__output_carry$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 6 \alu_op__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 29 \alu_op__rc__ok$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 5 \alu_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 28 \alu_op__rc__rc$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 12 \alu_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 35 \alu_op__write_cr0$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 10 \alu_op__zero_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 33 \alu_op__zero_a$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:62" + wire width 64 \b_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:146" + wire width 2 \ca + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:96" + wire \carry_32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:97" + wire \carry_64 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 4 output 44 \cr_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 45 \cr_a_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:174" + wire width 8 \eqs + attribute \src "issuer_ls180.v:131126.7-131126.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:50" + wire \is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:100" + wire \msb_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:101" + wire \msb_b + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 input 51 \muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 output 23 \muxid$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 output 42 \o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 43 \o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:152" + wire width 2 \ov + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 19 \ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 20 \rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:175" + wire width 8 \src1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:94" + wire width 5 \tval + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 2 input 22 \xer_ca + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 2 output 46 \xer_ca$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 47 \xer_ca_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 2 output 48 \xer_ov + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 49 \xer_ov_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire input 21 \xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 50 \xer_so$21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:99" + wire \zerohi + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:98" + wire \zerolo + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:82" + cell $add $add$issuer_ls180.v:131617$6292 + parameter \A_SIGNED 0 + parameter \A_WIDTH 66 + parameter \B_SIGNED 0 + parameter \B_WIDTH 66 + parameter \Y_WIDTH 67 + connect \A \add_a + connect \B \add_b + connect \Y $add$issuer_ls180.v:131617$6292_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:21" + cell $and $and$issuer_ls180.v:131591$6266 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$113 + connect \B \$115 + connect \Y $and$issuer_ls180.v:131591$6266_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:21" + cell $and $and$issuer_ls180.v:131595$6270 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$121 + connect \B \$123 + connect \Y $and$issuer_ls180.v:131595$6270_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:112" + cell $and $and$issuer_ls180.v:131628$6303 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \zerolo + connect \B \$69 + connect \Y $and$issuer_ls180.v:131628$6303_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:112" + cell $and $and$issuer_ls180.v:131633$6308 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \zerolo + connect \B \$79 + connect \Y $and$issuer_ls180.v:131633$6308_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:112" + cell $and $and$issuer_ls180.v:131636$6311 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \zerolo + connect \B \$85 + connect \Y $and$issuer_ls180.v:131636$6311_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:112" + cell $and $and$issuer_ls180.v:131639$6314 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \zerolo + connect \B \$91 + connect \Y $and$issuer_ls180.v:131639$6314_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:162" + cell $eq $eq$issuer_ls180.v:131582$6257 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \alu_op__data_len + connect \B 1'1 + connect \Y $eq$issuer_ls180.v:131582$6257_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:164" + cell $eq $eq$issuer_ls180.v:131583$6258 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \alu_op__data_len + connect \B 2'10 + connect \Y $eq$issuer_ls180.v:131583$6258_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:166" + cell $eq $eq$issuer_ls180.v:131584$6259 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \alu_op__data_len + connect \B 3'100 + connect \Y $eq$issuer_ls180.v:131584$6259_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:178" + cell $eq $eq$issuer_ls180.v:131596$6271 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \src1 + connect \B \rb [7:0] + connect \Y $eq$issuer_ls180.v:131596$6271_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:178" + cell $eq $eq$issuer_ls180.v:131597$6272 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \src1 + connect \B \rb [15:8] + connect \Y $eq$issuer_ls180.v:131597$6272_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:178" + cell $eq $eq$issuer_ls180.v:131598$6273 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \src1 + connect \B \rb [23:16] + connect \Y $eq$issuer_ls180.v:131598$6273_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:178" + cell $eq $eq$issuer_ls180.v:131599$6274 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \src1 + connect \B \rb [31:24] + connect \Y $eq$issuer_ls180.v:131599$6274_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:178" + cell $eq $eq$issuer_ls180.v:131600$6275 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \src1 + connect \B \rb [39:32] + connect \Y $eq$issuer_ls180.v:131600$6275_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:178" + cell $eq $eq$issuer_ls180.v:131601$6276 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \src1 + connect \B \rb [47:40] + connect \Y $eq$issuer_ls180.v:131601$6276_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:178" + cell $eq $eq$issuer_ls180.v:131602$6277 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \src1 + connect \B \rb [55:48] + connect \Y $eq$issuer_ls180.v:131602$6277_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:178" + cell $eq $eq$issuer_ls180.v:131603$6278 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \src1 + connect \B \rb [63:56] + connect \Y $eq$issuer_ls180.v:131603$6278_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:52" + cell $eq $eq$issuer_ls180.v:131604$6279 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \alu_op__insn_type + connect \B 7'0001010 + connect \Y $eq$issuer_ls180.v:131604$6279_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:63" + cell $eq $eq$issuer_ls180.v:131606$6281 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \alu_op__insn_type + connect \B 7'0001010 + connect \Y $eq$issuer_ls180.v:131606$6281_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:63" + cell $eq $eq$issuer_ls180.v:131607$6282 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \alu_op__insn_type + connect \B 7'0001010 + connect \Y $eq$issuer_ls180.v:131607$6282_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:77" + cell $eq $eq$issuer_ls180.v:131608$6283 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \alu_op__insn_type + connect \B 7'0000010 + connect \Y $eq$issuer_ls180.v:131608$6283_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:78" + cell $eq $eq$issuer_ls180.v:131609$6284 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \alu_op__insn_type + connect \B 7'0001010 + connect \Y $eq$issuer_ls180.v:131609$6284_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:77" + cell $eq $eq$issuer_ls180.v:131611$6286 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \alu_op__insn_type + connect \B 7'0000010 + connect \Y $eq$issuer_ls180.v:131611$6286_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:78" + cell $eq $eq$issuer_ls180.v:131612$6287 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \alu_op__insn_type + connect \B 7'0001010 + connect \Y $eq$issuer_ls180.v:131612$6287_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:77" + cell $eq $eq$issuer_ls180.v:131614$6289 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \alu_op__insn_type + connect \B 7'0000010 + connect \Y $eq$issuer_ls180.v:131614$6289_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:78" + cell $eq $eq$issuer_ls180.v:131615$6290 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \alu_op__insn_type + connect \B 7'0001010 + connect \Y $eq$issuer_ls180.v:131615$6290_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:119" + cell $ne $ne$issuer_ls180.v:131629$6304 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \msb_a + connect \B \msb_b + connect \Y $ne$issuer_ls180.v:131629$6304_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:119" + cell $ne $ne$issuer_ls180.v:131640$6315 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \msb_a + connect \B \msb_b + connect \Y $ne$issuer_ls180.v:131640$6315_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:21" + cell $not $not$issuer_ls180.v:131590$6265 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$116 + connect \Y $not$issuer_ls180.v:131590$6265_Y + end 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1 + connect \A \$58 + connect \Y $not$issuer_ls180.v:131623$6298_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:110" + cell $not $not$issuer_ls180.v:131626$6301 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$64 + connect \Y $not$issuer_ls180.v:131626$6301_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:128" + cell $not $not$issuer_ls180.v:131630$6305 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \a_lt + connect \Y $not$issuer_ls180.v:131630$6305_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:128" + cell $not $not$issuer_ls180.v:131631$6306 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \a_lt + connect \Y $not$issuer_ls180.v:131631$6306_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:78" + cell $or $or$issuer_ls180.v:131610$6285 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$30 + connect \B \$32 + connect \Y $or$issuer_ls180.v:131610$6285_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:78" + cell $or $or$issuer_ls180.v:131613$6288 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$36 + connect \B \$38 + connect \Y $or$issuer_ls180.v:131613$6288_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:78" + cell $or $or$issuer_ls180.v:131616$6291 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$42 + connect \B \$44 + connect \Y $or$issuer_ls180.v:131616$6291_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:112" + cell $or $or$issuer_ls180.v:131627$6302 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \is_32bit + connect \B \zerohi + connect \Y $or$issuer_ls180.v:131627$6302_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:112" + cell $or $or$issuer_ls180.v:131632$6307 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \is_32bit + connect \B \zerohi + connect \Y $or$issuer_ls180.v:131632$6307_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:112" + cell $or $or$issuer_ls180.v:131635$6310 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \is_32bit + connect \B \zerohi + connect \Y $or$issuer_ls180.v:131635$6310_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:112" + cell $or $or$issuer_ls180.v:131638$6313 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \is_32bit + connect \B \zerohi + connect \Y $or$issuer_ls180.v:131638$6313_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:181" + cell $reduce_or $reduce_or$issuer_ls180.v:131581$6256 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \eqs + connect \Y $reduce_or$issuer_ls180.v:131581$6256_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:179" + cell $reduce_or $reduce_or$issuer_ls180.v:131585$6260 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \eqs + connect \Y $reduce_or$issuer_ls180.v:131585$6260_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:109" + cell $reduce_or $reduce_or$issuer_ls180.v:131622$6297 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \Y_WIDTH 1 + connect \A \$59 + connect \Y $reduce_or$issuer_ls180.v:131622$6297_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:110" + cell $reduce_or $reduce_or$issuer_ls180.v:131625$6300 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \Y_WIDTH 1 + connect \A \$65 + connect \Y $reduce_or$issuer_ls180.v:131625$6300_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:116" + cell $mux $ternary$issuer_ls180.v:131634$6309 + parameter \WIDTH 1 + connect \A \a_n [63] + connect \B \a_n [31] + connect \S \is_32bit + connect \Y $ternary$issuer_ls180.v:131634$6309_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:117" + cell $mux $ternary$issuer_ls180.v:131637$6312 + parameter \WIDTH 1 + connect \A \rb [63] + connect \B \rb [31] + connect \S \is_32bit + connect \Y $ternary$issuer_ls180.v:131637$6312_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:127" + cell $mux $ternary$issuer_ls180.v:131641$6316 + parameter \WIDTH 1 + connect \A \carry_64 + connect \B \carry_32 + connect \S \is_32bit + connect \Y $ternary$issuer_ls180.v:131641$6316_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:148" + cell $xor $xor$issuer_ls180.v:131586$6261 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \a_i [32] + connect \B \b_i [32] + connect \Y $xor$issuer_ls180.v:131586$6261_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:148" + cell $xor $xor$issuer_ls180.v:131587$6262 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \add_o [33] + connect \B \$109 + connect \Y $xor$issuer_ls180.v:131587$6262_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:21" + cell $xor $xor$issuer_ls180.v:131588$6263 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \ca [0] + connect \B \add_o [64] + connect \Y $xor$issuer_ls180.v:131588$6263_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:21" + cell $xor $xor$issuer_ls180.v:131589$6264 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \a_i [63] + connect \B \b_i [63] + connect \Y $xor$issuer_ls180.v:131589$6264_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:21" + cell $xor $xor$issuer_ls180.v:131592$6267 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \ca [1] + connect \B \add_o [32] + connect \Y $xor$issuer_ls180.v:131592$6267_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:21" + cell $xor $xor$issuer_ls180.v:131593$6268 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \a_i [31] + connect \B \b_i [31] + connect \Y $xor$issuer_ls180.v:131593$6268_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:106" + cell $xor $xor$issuer_ls180.v:131619$6294 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \add_o [33] + connect \B \ra [32] + connect \Y $xor$issuer_ls180.v:131619$6294_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:106" + cell $xor $xor$issuer_ls180.v:131620$6295 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$53 + connect \B \rb [32] + connect \Y $xor$issuer_ls180.v:131620$6295_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:109" + cell $xor $xor$issuer_ls180.v:131621$6296 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 32 + parameter \Y_WIDTH 32 + connect \A \a_n [31:0] + connect \B \rb [31:0] + connect \Y $xor$issuer_ls180.v:131621$6296_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:110" + cell $xor $xor$issuer_ls180.v:131624$6299 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 32 + parameter \Y_WIDTH 32 + connect \A \a_n [63:32] + connect \B \rb [63:32] + connect \Y $xor$issuer_ls180.v:131624$6299_Y + end + attribute \src "issuer_ls180.v:131126.7-131126.20" + process $proc$issuer_ls180.v:131126$6346 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "issuer_ls180.v:131642.3-131651.6" + process $proc$issuer_ls180.v:131642$6317 + assign { } { } + assign { } { } + assign $0\is_32bit[0:0] $1\is_32bit[0:0] + attribute \src "issuer_ls180.v:131643.5-131643.29" + switch \initial + attribute \src "issuer_ls180.v:131643.9-131643.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:52" + switch \$22 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\is_32bit[0:0] \$24 + case + assign $1\is_32bit[0:0] 1'0 + end + sync always + update \is_32bit $0\is_32bit[0:0] + end + attribute \src "issuer_ls180.v:131652.3-131674.6" + process $proc$issuer_ls180.v:131652$6318 + assign { } { } + assign $0\a_i[63:0] $1\a_i[63:0] + attribute \src "issuer_ls180.v:131653.5-131653.29" + switch \initial + attribute \src "issuer_ls180.v:131653.9-131653.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:63" + switch { \is_32bit \$26 } + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\a_i[63:0] \ra + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\a_i[63:0] $2\a_i[63:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:67" + switch \alu_op__is_signed + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\a_i[63:0] { \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31:0] } + attribute \src "issuer_ls180.v:0.0-0.0" + case + assign { } { } + assign $2\a_i[63:0] { 32'00000000000000000000000000000000 \ra [31:0] } + end + attribute \src "issuer_ls180.v:0.0-0.0" + case + assign { } { } + assign $1\a_i[63:0] \ra + end + sync always + update \a_i $0\a_i[63:0] + end + attribute \src "issuer_ls180.v:131675.3-131685.6" + process $proc$issuer_ls180.v:131675$6319 + assign { } { } + assign { } { } + assign $0\zerohi[0:0] $1\zerohi[0:0] + attribute \src "issuer_ls180.v:131676.5-131676.29" + switch \initial + attribute \src "issuer_ls180.v:131676.9-131676.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:87" + switch \alu_op__insn_type + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'0001010 + assign { } { } + assign $1\zerohi[0:0] \$63 + case + assign $1\zerohi[0:0] 1'0 + end + sync always + update \zerohi $0\zerohi[0:0] + end + attribute \src "issuer_ls180.v:131686.3-131712.6" + process $proc$issuer_ls180.v:131686$6320 + assign { } { } + assign { } { } + assign $0\tval[4:0] $1\tval[4:0] + attribute \src "issuer_ls180.v:131687.5-131687.29" + switch \initial + attribute \src "issuer_ls180.v:131687.9-131687.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:87" + switch \alu_op__insn_type + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'0001010 + assign { } { } + assign $1\tval[4:0] $2\tval[4:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:112" + switch \$71 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { $2\tval[4:0] [4:3] $2\tval[4:0] [1:0] } 4'0000 + assign $2\tval[4:0] [2] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case + assign { } { } + assign $2\tval[4:0] $3\tval[4:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:119" + switch \$73 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\tval[4:0] { \msb_a \msb_b 1'0 \msb_b \msb_a } + attribute \src "issuer_ls180.v:0.0-0.0" + case + assign { } { } + assign $3\tval[4:0] { \a_lt \$77 1'0 \a_lt \$75 } + end + end + case + assign $1\tval[4:0] 5'00000 + end + sync always + update \tval $0\tval[4:0] + end + attribute \src "issuer_ls180.v:131713.3-131731.6" + process $proc$issuer_ls180.v:131713$6321 + assign { } { } + assign { } { } + assign $0\msb_a[0:0] $1\msb_a[0:0] + attribute \src "issuer_ls180.v:131714.5-131714.29" + switch \initial + attribute \src "issuer_ls180.v:131714.9-131714.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:87" + switch \alu_op__insn_type + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'0001010 + assign { } { } + assign $1\msb_a[0:0] $2\msb_a[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:112" + switch \$81 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign $2\msb_a[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case + assign { } { } + assign $2\msb_a[0:0] \$83 + end + case + assign $1\msb_a[0:0] 1'0 + end + sync always + update \msb_a $0\msb_a[0:0] + end + attribute \src "issuer_ls180.v:131732.3-131750.6" + process $proc$issuer_ls180.v:131732$6322 + assign { } { } + assign { } { } + assign $0\msb_b[0:0] $1\msb_b[0:0] + attribute \src "issuer_ls180.v:131733.5-131733.29" + switch \initial + attribute \src "issuer_ls180.v:131733.9-131733.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:87" + switch \alu_op__insn_type + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'0001010 + assign { } { } + assign $1\msb_b[0:0] $2\msb_b[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:112" + switch \$87 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign $2\msb_b[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case + assign { } { } + assign $2\msb_b[0:0] \$89 + end + case + assign $1\msb_b[0:0] 1'0 + end + sync always + update \msb_b $0\msb_b[0:0] + end + attribute \src "issuer_ls180.v:131751.3-131777.6" + process $proc$issuer_ls180.v:131751$6323 + assign { } { } + assign { } { } + assign $0\a_lt[0:0] $1\a_lt[0:0] + attribute \src "issuer_ls180.v:131752.5-131752.29" + switch \initial + attribute \src "issuer_ls180.v:131752.9-131752.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:87" + switch \alu_op__insn_type + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'0001010 + assign { } { } + assign $1\a_lt[0:0] $2\a_lt[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:112" + switch \$93 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign $2\a_lt[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case + assign { } { } + assign $2\a_lt[0:0] $3\a_lt[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:119" + switch \$95 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign $3\a_lt[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case + assign { } { } + assign $3\a_lt[0:0] \$97 + end + end + case + assign $1\a_lt[0:0] 1'0 + end + sync always + update \a_lt $0\a_lt[0:0] + end + attribute \src "issuer_ls180.v:131778.3-131803.6" + process $proc$issuer_ls180.v:131778$6324 + assign { } { } + assign { } { } + assign $0\cr_a[3:0] $1\cr_a[3:0] + attribute \src "issuer_ls180.v:131779.5-131779.29" + switch \initial + attribute \src "issuer_ls180.v:131779.9-131779.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:87" + switch \alu_op__insn_type + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'0001010 + assign { } { } + assign $1\cr_a[3:0] [1:0] { \tval [2] \xer_so } + assign $1\cr_a[3:0] [3:2] $2\cr_a[3:2] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:130" + switch \alu_op__is_signed + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\cr_a[3:2] \tval [4:3] + attribute \src "issuer_ls180.v:0.0-0.0" + case + assign { } { } + assign $2\cr_a[3:2] \tval [1:0] + end + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'0001100 + assign { } { } + assign $1\cr_a[3:0] { 1'0 \$99 2'00 } + case + assign $1\cr_a[3:0] 4'0000 + end + sync always + update \cr_a $0\cr_a[3:0] + end + attribute \src "issuer_ls180.v:131804.3-131818.6" + process $proc$issuer_ls180.v:131804$6325 + assign { } { } + assign { } { } + assign $0\cr_a_ok[0:0] $1\cr_a_ok[0:0] + attribute \src "issuer_ls180.v:131805.5-131805.29" + switch \initial + attribute \src "issuer_ls180.v:131805.9-131805.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:87" + switch \alu_op__insn_type + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'0001010 + assign { } { } + assign $1\cr_a_ok[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'0001100 + assign { } { } + assign $1\cr_a_ok[0:0] 1'1 + case + assign $1\cr_a_ok[0:0] 1'0 + end + sync always + update \cr_a_ok $0\cr_a_ok[0:0] + end + attribute \src "issuer_ls180.v:131819.3-131856.6" + process $proc$issuer_ls180.v:131819$6326 + assign { } { } + assign { } { } + assign $0\o[63:0] $1\o[63:0] + attribute \src "issuer_ls180.v:131820.5-131820.29" + switch \initial + attribute \src "issuer_ls180.v:131820.9-131820.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:87" + switch \alu_op__insn_type + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'0000010 + assign { } { } + assign $1\o[63:0] \add_o [64:1] + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'0011111 + assign { } { } + assign { } { } + assign { } { } + assign $1\o[63:0] $4\o[63:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:162" + switch \$101 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\o[63:0] { \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7] \ra [7:0] } + case + assign $2\o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:164" + switch \$103 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\o[63:0] { \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15] \ra [15:0] } + case + assign $3\o[63:0] $2\o[63:0] + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:166" + switch \$105 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\o[63:0] { \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31:0] } + case + assign $4\o[63:0] $3\o[63:0] + end + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'0001100 + assign $1\o[63:0] [63:1] 63'000000000000000000000000000000000000000000000000000000000000000 + assign $1\o[63:0] [0] \$107 + case + assign $1\o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \o $0\o[63:0] + end + attribute \src "issuer_ls180.v:131857.3-131875.6" + process $proc$issuer_ls180.v:131857$6327 + assign { } { } + assign { } { } + assign $0\o_ok[0:0] $1\o_ok[0:0] + attribute \src "issuer_ls180.v:131858.5-131858.29" + switch \initial + attribute \src "issuer_ls180.v:131858.9-131858.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:87" + switch \alu_op__insn_type + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'0000010 + assign { } { } + assign $1\o_ok[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'0011111 + assign { } { } + assign $1\o_ok[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'0001100 + assign { } { } + assign $1\o_ok[0:0] 1'0 + case + assign $1\o_ok[0:0] 1'0 + end + sync always + update \o_ok $0\o_ok[0:0] + end + attribute \src "issuer_ls180.v:131876.3-131889.6" + process $proc$issuer_ls180.v:131876$6328 + assign { } { } + assign { } { } + assign $0\ca[1:0] $1\ca[1:0] + attribute \src "issuer_ls180.v:131877.5-131877.29" + switch \initial + attribute \src "issuer_ls180.v:131877.9-131877.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:87" + switch \alu_op__insn_type + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'0000010 + assign { } { } + assign $1\ca[1:0] [0] \add_o [65] + assign $1\ca[1:0] [1] \$111 + case + assign $1\ca[1:0] 2'00 + end + sync always + update \ca $0\ca[1:0] + end + attribute \src "issuer_ls180.v:131890.3-131912.6" + process $proc$issuer_ls180.v:131890$6329 + assign { } { } + assign $0\b_i[63:0] $1\b_i[63:0] + attribute \src "issuer_ls180.v:131891.5-131891.29" + switch \initial + attribute \src "issuer_ls180.v:131891.9-131891.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:63" + switch { \is_32bit \$28 } + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\b_i[63:0] \rb + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\b_i[63:0] $2\b_i[63:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:67" + switch \alu_op__is_signed + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\b_i[63:0] { \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31:0] } + attribute \src "issuer_ls180.v:0.0-0.0" + case + assign { } { } + assign $2\b_i[63:0] { 32'00000000000000000000000000000000 \rb [31:0] } + end + attribute \src "issuer_ls180.v:0.0-0.0" + case + assign { } { } + assign $1\b_i[63:0] \rb + end + sync always + update \b_i $0\b_i[63:0] + end + attribute \src "issuer_ls180.v:131913.3-131923.6" + process $proc$issuer_ls180.v:131913$6330 + assign { } { } + assign { } { } + assign $0\xer_ca$20[1:0]$6331 $1\xer_ca$20[1:0]$6332 + attribute \src "issuer_ls180.v:131914.5-131914.29" + switch \initial + attribute \src "issuer_ls180.v:131914.9-131914.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:87" + switch \alu_op__insn_type + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'0000010 + assign { } { } + assign $1\xer_ca$20[1:0]$6332 \ca + case + assign $1\xer_ca$20[1:0]$6332 2'00 + end + sync always + update \xer_ca$20 $0\xer_ca$20[1:0]$6331 + end + attribute \src "issuer_ls180.v:131924.3-131934.6" + process $proc$issuer_ls180.v:131924$6333 + assign { } { } + assign { } { } + assign $0\xer_ca_ok[0:0] $1\xer_ca_ok[0:0] + attribute \src "issuer_ls180.v:131925.5-131925.29" + switch \initial + attribute \src "issuer_ls180.v:131925.9-131925.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:87" + switch \alu_op__insn_type + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'0000010 + assign { } { } + assign $1\xer_ca_ok[0:0] 1'1 + case + assign $1\xer_ca_ok[0:0] 1'0 + end + sync always + update \xer_ca_ok $0\xer_ca_ok[0:0] + end + attribute \src "issuer_ls180.v:131935.3-131948.6" + process $proc$issuer_ls180.v:131935$6334 + assign { } { } + assign { } { } + assign $0\ov[1:0] $1\ov[1:0] + attribute \src "issuer_ls180.v:131936.5-131936.29" + switch \initial + attribute \src "issuer_ls180.v:131936.9-131936.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:87" + switch \alu_op__insn_type + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'0000010 + assign { } { } + assign $1\ov[1:0] [0] \$119 + assign $1\ov[1:0] [1] \$127 + case + assign $1\ov[1:0] 2'00 + end + sync always + update \ov $0\ov[1:0] + end + attribute \src "issuer_ls180.v:131949.3-131959.6" + process $proc$issuer_ls180.v:131949$6335 + assign { } { } + assign { } { } + assign $0\xer_ov[1:0] $1\xer_ov[1:0] + attribute \src "issuer_ls180.v:131950.5-131950.29" + switch \initial + attribute \src "issuer_ls180.v:131950.9-131950.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:87" + switch \alu_op__insn_type + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'0000010 + assign { } { } + assign $1\xer_ov[1:0] \ov + case + assign $1\xer_ov[1:0] 2'00 + end + sync always + update \xer_ov $0\xer_ov[1:0] + end + attribute \src "issuer_ls180.v:131960.3-131970.6" + process $proc$issuer_ls180.v:131960$6336 + assign { } { } + assign { } { } + assign $0\xer_ov_ok[0:0] $1\xer_ov_ok[0:0] + attribute \src "issuer_ls180.v:131961.5-131961.29" + switch \initial + attribute \src "issuer_ls180.v:131961.9-131961.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:87" + switch \alu_op__insn_type + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'0000010 + assign { } { } + assign $1\xer_ov_ok[0:0] 1'1 + case + assign $1\xer_ov_ok[0:0] 1'0 + end + sync always + update \xer_ov_ok $0\xer_ov_ok[0:0] + end + attribute \src "issuer_ls180.v:131971.3-131981.6" + process $proc$issuer_ls180.v:131971$6337 + assign { } { } + assign { } { } + assign $0\src1[7:0] $1\src1[7:0] + attribute \src "issuer_ls180.v:131972.5-131972.29" + switch \initial + attribute \src "issuer_ls180.v:131972.9-131972.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:87" + switch \alu_op__insn_type + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'0001100 + assign { } { } + assign $1\src1[7:0] \ra [7:0] + case + assign $1\src1[7:0] 8'00000000 + end + sync always + update \src1 $0\src1[7:0] + end + attribute \src "issuer_ls180.v:131982.3-132001.6" + process $proc$issuer_ls180.v:131982$6338 + assign { } { } + assign { } { } + assign $0\eqs[7:0] $1\eqs[7:0] + attribute \src "issuer_ls180.v:131983.5-131983.29" + switch \initial + attribute \src "issuer_ls180.v:131983.9-131983.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:87" + switch \alu_op__insn_type + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'0001100 + assign { } { } + assign $1\eqs[7:0] [0] \$129 + assign $1\eqs[7:0] [1] \$131 + assign $1\eqs[7:0] [2] \$133 + assign $1\eqs[7:0] [3] \$135 + assign $1\eqs[7:0] [4] \$137 + assign $1\eqs[7:0] [5] \$139 + assign $1\eqs[7:0] [6] \$141 + assign $1\eqs[7:0] [7] \$143 + case + assign $1\eqs[7:0] 8'00000000 + end + sync always + update \eqs $0\eqs[7:0] + end + attribute \src "issuer_ls180.v:132002.3-132011.6" + process $proc$issuer_ls180.v:132002$6339 + assign { } { } + assign { } { } + assign $0\add_a[65:0] $1\add_a[65:0] + attribute \src "issuer_ls180.v:132003.5-132003.29" + switch \initial + attribute \src "issuer_ls180.v:132003.9-132003.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:78" + switch \$34 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\add_a[65:0] { 1'0 \a_i \xer_ca [0] } + case + assign $1\add_a[65:0] 66'000000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \add_a $0\add_a[65:0] + end + attribute \src "issuer_ls180.v:132012.3-132021.6" + process $proc$issuer_ls180.v:132012$6340 + assign { } { } + assign { } { } + assign $0\add_b[65:0] $1\add_b[65:0] + attribute \src "issuer_ls180.v:132013.5-132013.29" + switch \initial + attribute \src "issuer_ls180.v:132013.9-132013.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:78" + switch \$40 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\add_b[65:0] { 1'0 \b_i 1'1 } + case + assign $1\add_b[65:0] 66'000000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \add_b $0\add_b[65:0] + end + attribute \src "issuer_ls180.v:132022.3-132031.6" + process $proc$issuer_ls180.v:132022$6341 + assign { } { } + assign { } { } + assign $0\add_o[65:0] $1\add_o[65:0] + attribute \src "issuer_ls180.v:132023.5-132023.29" + switch \initial + attribute \src "issuer_ls180.v:132023.9-132023.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:78" + switch \$46 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\add_o[65:0] \$48 [65:0] + case + assign $1\add_o[65:0] 66'000000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \add_o $0\add_o[65:0] + end + attribute \src "issuer_ls180.v:132032.3-132042.6" + process $proc$issuer_ls180.v:132032$6342 + assign { } { } + assign { } { } + assign $0\a_n[63:0] $1\a_n[63:0] + attribute \src "issuer_ls180.v:132033.5-132033.29" + switch \initial + attribute \src "issuer_ls180.v:132033.9-132033.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:87" + switch \alu_op__insn_type + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'0001010 + assign { } { } + assign $1\a_n[63:0] \$51 + case + assign $1\a_n[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \a_n $0\a_n[63:0] + end + attribute \src "issuer_ls180.v:132043.3-132053.6" + process $proc$issuer_ls180.v:132043$6343 + assign { } { } + assign { } { } + assign $0\carry_32[0:0] $1\carry_32[0:0] + attribute \src "issuer_ls180.v:132044.5-132044.29" + switch \initial + attribute \src "issuer_ls180.v:132044.9-132044.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:87" + switch \alu_op__insn_type + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'0001010 + assign { } { } + assign $1\carry_32[0:0] \$55 + case + assign $1\carry_32[0:0] 1'0 + end + sync always + update \carry_32 $0\carry_32[0:0] + end + attribute \src "issuer_ls180.v:132054.3-132064.6" + process $proc$issuer_ls180.v:132054$6344 + assign { } { } + assign { } { } + assign $0\carry_64[0:0] $1\carry_64[0:0] + attribute \src "issuer_ls180.v:132055.5-132055.29" + switch \initial + attribute \src "issuer_ls180.v:132055.9-132055.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:87" + switch \alu_op__insn_type + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'0001010 + assign { } { } + assign $1\carry_64[0:0] \add_o [65] + case + assign $1\carry_64[0:0] 1'0 + end + sync always + update \carry_64 $0\carry_64[0:0] + end + attribute \src "issuer_ls180.v:132065.3-132075.6" + process $proc$issuer_ls180.v:132065$6345 + assign { } { } + assign { } { } + assign $0\zerolo[0:0] $1\zerolo[0:0] + attribute \src "issuer_ls180.v:132066.5-132066.29" + switch \initial + attribute \src "issuer_ls180.v:132066.9-132066.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:87" + switch \alu_op__insn_type + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'0001010 + assign { } { } + assign $1\zerolo[0:0] \$57 + case + assign $1\zerolo[0:0] 1'0 + end + sync always + update \zerolo $0\zerolo[0:0] + end + connect \$99 $reduce_or$issuer_ls180.v:131581$6256_Y + connect \$101 $eq$issuer_ls180.v:131582$6257_Y + connect \$103 $eq$issuer_ls180.v:131583$6258_Y + connect \$105 $eq$issuer_ls180.v:131584$6259_Y + connect \$107 $reduce_or$issuer_ls180.v:131585$6260_Y + connect \$109 $xor$issuer_ls180.v:131586$6261_Y + connect \$111 $xor$issuer_ls180.v:131587$6262_Y + connect \$113 $xor$issuer_ls180.v:131588$6263_Y + connect \$116 $xor$issuer_ls180.v:131589$6264_Y + connect \$115 $not$issuer_ls180.v:131590$6265_Y + connect \$119 $and$issuer_ls180.v:131591$6266_Y + connect \$121 $xor$issuer_ls180.v:131592$6267_Y + connect \$124 $xor$issuer_ls180.v:131593$6268_Y + connect \$123 $not$issuer_ls180.v:131594$6269_Y + connect \$127 $and$issuer_ls180.v:131595$6270_Y + connect \$129 $eq$issuer_ls180.v:131596$6271_Y + connect \$131 $eq$issuer_ls180.v:131597$6272_Y + connect \$133 $eq$issuer_ls180.v:131598$6273_Y + connect \$135 $eq$issuer_ls180.v:131599$6274_Y + connect \$137 $eq$issuer_ls180.v:131600$6275_Y + connect \$139 $eq$issuer_ls180.v:131601$6276_Y + connect \$141 $eq$issuer_ls180.v:131602$6277_Y + connect \$143 $eq$issuer_ls180.v:131603$6278_Y + connect \$22 $eq$issuer_ls180.v:131604$6279_Y + connect \$24 $not$issuer_ls180.v:131605$6280_Y + connect \$26 $eq$issuer_ls180.v:131606$6281_Y + connect \$28 $eq$issuer_ls180.v:131607$6282_Y + connect \$30 $eq$issuer_ls180.v:131608$6283_Y + connect \$32 $eq$issuer_ls180.v:131609$6284_Y + connect \$34 $or$issuer_ls180.v:131610$6285_Y + connect \$36 $eq$issuer_ls180.v:131611$6286_Y + connect \$38 $eq$issuer_ls180.v:131612$6287_Y + connect \$40 $or$issuer_ls180.v:131613$6288_Y + connect \$42 $eq$issuer_ls180.v:131614$6289_Y + connect \$44 $eq$issuer_ls180.v:131615$6290_Y + connect \$46 $or$issuer_ls180.v:131616$6291_Y + connect \$49 $add$issuer_ls180.v:131617$6292_Y + connect \$51 $not$issuer_ls180.v:131618$6293_Y + connect \$53 $xor$issuer_ls180.v:131619$6294_Y + connect \$55 $xor$issuer_ls180.v:131620$6295_Y + connect \$59 $xor$issuer_ls180.v:131621$6296_Y + connect \$58 $reduce_or$issuer_ls180.v:131622$6297_Y + connect \$57 $not$issuer_ls180.v:131623$6298_Y + connect \$65 $xor$issuer_ls180.v:131624$6299_Y + connect \$64 $reduce_or$issuer_ls180.v:131625$6300_Y + connect \$63 $not$issuer_ls180.v:131626$6301_Y + connect \$69 $or$issuer_ls180.v:131627$6302_Y + connect \$71 $and$issuer_ls180.v:131628$6303_Y + connect \$73 $ne$issuer_ls180.v:131629$6304_Y + connect \$75 $not$issuer_ls180.v:131630$6305_Y + connect \$77 $not$issuer_ls180.v:131631$6306_Y + connect \$79 $or$issuer_ls180.v:131632$6307_Y + connect \$81 $and$issuer_ls180.v:131633$6308_Y + connect \$83 $ternary$issuer_ls180.v:131634$6309_Y + connect \$85 $or$issuer_ls180.v:131635$6310_Y + connect \$87 $and$issuer_ls180.v:131636$6311_Y + connect \$89 $ternary$issuer_ls180.v:131637$6312_Y + connect \$91 $or$issuer_ls180.v:131638$6313_Y + connect \$93 $and$issuer_ls180.v:131639$6314_Y + connect \$95 $ne$issuer_ls180.v:131640$6315_Y + connect \$97 $ternary$issuer_ls180.v:131641$6316_Y + connect \$48 \$49 + connect { \alu_op__insn$19 \alu_op__data_len$18 \alu_op__is_signed$17 \alu_op__is_32bit$16 \alu_op__output_carry$15 \alu_op__input_carry$14 \alu_op__write_cr0$13 \alu_op__invert_out$12 \alu_op__zero_a$11 \alu_op__invert_in$10 \alu_op__oe__ok$9 \alu_op__oe__oe$8 \alu_op__rc__ok$7 \alu_op__rc__rc$6 \alu_op__imm_data__ok$5 \alu_op__imm_data__data$4 \alu_op__fn_unit$3 \alu_op__insn_type$2 } { \alu_op__insn \alu_op__data_len \alu_op__is_signed \alu_op__is_32bit \alu_op__output_carry \alu_op__input_carry \alu_op__write_cr0 \alu_op__invert_out \alu_op__zero_a \alu_op__invert_in \alu_op__oe__ok \alu_op__oe__oe \alu_op__rc__ok \alu_op__rc__rc \alu_op__imm_data__ok \alu_op__imm_data__data \alu_op__fn_unit \alu_op__insn_type } + connect \muxid$1 \muxid + connect \xer_so$21 \xer_so +end +attribute \src "issuer_ls180.v:132084.1-132488.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.fus.shiftrot0.alu_shift_rot0.pipe1.main" +attribute \generator "nMigen" +module \main$111 + attribute \src "issuer_ls180.v:132085.7-132085.20" + wire $0\initial[0:0] + attribute \src "issuer_ls180.v:132440.3-132470.6" + wire width 4 $0\mode[3:0] + attribute \src "issuer_ls180.v:132405.3-132439.6" + wire $0\o_ok[0:0] + attribute \src "issuer_ls180.v:132440.3-132470.6" + wire width 4 $1\mode[3:0] + attribute \src "issuer_ls180.v:132405.3-132439.6" + wire $1\o_ok[0:0] + attribute \src "issuer_ls180.v:132085.7-132085.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/main_stage.py:46" + wire width 5 \mb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/main_stage.py:48" + wire \mb_extra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/main_stage.py:47" + wire width 5 \me + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/main_stage.py:69" + wire width 4 \mode + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 input 42 \muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 output 21 \muxid$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 output 38 \o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 39 \o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 17 \ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 18 \rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 19 \rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:59" + wire \rotator_arith + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:65" + wire \rotator_carry_out_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:60" + wire \rotator_clear_left + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:61" + wire \rotator_clear_right + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:57" + wire \rotator_is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:51" + wire width 5 \rotator_mb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:53" + wire \rotator_mb_extra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:50" + wire width 5 \rotator_me + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:54" + wire width 64 \rotator_ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:64" + wire width 64 \rotator_result_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:58" + wire \rotator_right_shift + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:55" + wire width 64 \rotator_rs + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:56" + wire width 7 \rotator_shift + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:62" + wire \rotator_sign_ext_rs + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 input 2 \sr_op__fn_unit + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 output 23 \sr_op__fn_unit$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 input 3 \sr_op__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 output 24 \sr_op__imm_data__data$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 4 \sr_op__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 25 \sr_op__imm_data__ok$5 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 input 10 \sr_op__input_carry + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 output 31 \sr_op__input_carry$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 12 \sr_op__input_cr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 33 \sr_op__input_cr$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 16 \sr_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 output 37 \sr_op__insn$17 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 input 1 \sr_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 output 22 \sr_op__insn_type$2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 14 \sr_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 35 \sr_op__is_32bit$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 15 \sr_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 36 \sr_op__is_signed$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 7 \sr_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 28 \sr_op__oe__oe$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 8 \sr_op__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 29 \sr_op__oe__ok$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 11 \sr_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 32 \sr_op__output_carry$12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 13 \sr_op__output_cr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 34 \sr_op__output_cr$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 6 \sr_op__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 27 \sr_op__rc__ok$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 5 \sr_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 26 \sr_op__rc__rc$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 9 \sr_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 30 \sr_op__write_cr0$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 2 output 41 \xer_ca + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire input 20 \xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 40 \xer_so$18 + attribute \module_not_derived 1 + attribute \src "issuer_ls180.v:132389.11-132404.4" + cell \rotator \rotator + connect \arith \rotator_arith + connect \carry_out_o \rotator_carry_out_o + connect \clear_left \rotator_clear_left + connect \clear_right \rotator_clear_right + connect \is_32bit \rotator_is_32bit + connect \mb \rotator_mb + connect \mb_extra \rotator_mb_extra + connect \me \rotator_me + connect \ra \rotator_ra + connect \result_o \rotator_result_o + connect \right_shift \rotator_right_shift + connect \rs \rotator_rs + connect \shift \rotator_shift + connect \sign_ext_rs \rotator_sign_ext_rs + end + attribute \src "issuer_ls180.v:132085.7-132085.20" + process $proc$issuer_ls180.v:132085$6349 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "issuer_ls180.v:132405.3-132439.6" + process $proc$issuer_ls180.v:132405$6347 + assign { } { } + assign { } { } + assign $0\o_ok[0:0] $1\o_ok[0:0] + attribute \src "issuer_ls180.v:132406.5-132406.29" + switch \initial + attribute \src "issuer_ls180.v:132406.9-132406.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/main_stage.py:70" + switch \sr_op__insn_type + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'0111100 + assign $1\o_ok[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'0111101 + assign $1\o_ok[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'0111000 + assign $1\o_ok[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'0111001 + assign $1\o_ok[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'0111010 + assign $1\o_ok[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'0100000 + assign $1\o_ok[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case + assign { } { } + assign $1\o_ok[0:0] 1'0 + end + sync always + update \o_ok $0\o_ok[0:0] + end + attribute \src "issuer_ls180.v:132440.3-132470.6" + process $proc$issuer_ls180.v:132440$6348 + assign { } { } + assign { } { } + assign $0\mode[3:0] $1\mode[3:0] + attribute \src "issuer_ls180.v:132441.5-132441.29" + switch \initial + attribute \src "issuer_ls180.v:132441.9-132441.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/main_stage.py:70" + switch \sr_op__insn_type + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'0111100 + assign { } { } + assign $1\mode[3:0] 4'0000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'0111101 + assign { } { } + assign $1\mode[3:0] 4'0001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'0111000 + assign { } { } + assign $1\mode[3:0] 4'0110 + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'0111001 + assign { } { } + assign $1\mode[3:0] 4'0010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'0111010 + assign { } { } + assign $1\mode[3:0] 4'0100 + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'0100000 + assign { } { } + assign $1\mode[3:0] 4'1000 + case + assign $1\mode[3:0] 4'0000 + end + sync always + update \mode $0\mode[3:0] + end + connect { \sr_op__insn$17 \sr_op__is_signed$16 \sr_op__is_32bit$15 \sr_op__output_cr$14 \sr_op__input_cr$13 \sr_op__output_carry$12 \sr_op__input_carry$11 \sr_op__write_cr0$10 \sr_op__oe__ok$9 \sr_op__oe__oe$8 \sr_op__rc__ok$7 \sr_op__rc__rc$6 \sr_op__imm_data__ok$5 \sr_op__imm_data__data$4 \sr_op__fn_unit$3 \sr_op__insn_type$2 } { \sr_op__insn \sr_op__is_signed \sr_op__is_32bit \sr_op__output_cr \sr_op__input_cr \sr_op__output_carry \sr_op__input_carry \sr_op__write_cr0 \sr_op__oe__ok \sr_op__oe__oe \sr_op__rc__ok \sr_op__rc__rc \sr_op__imm_data__ok \sr_op__imm_data__data \sr_op__fn_unit \sr_op__insn_type } + connect \muxid$1 \muxid + connect \xer_so$18 \xer_so + connect \xer_ca { \rotator_carry_out_o \rotator_carry_out_o } + connect \o \rotator_result_o + connect { \rotator_sign_ext_rs \rotator_clear_right \rotator_clear_left \rotator_right_shift } \mode + connect \rotator_arith \sr_op__is_signed + connect \rotator_is_32bit \sr_op__is_32bit + connect \rotator_shift \rb [6:0] + connect \rotator_ra \ra + connect \rotator_rs \rc + connect \rotator_mb_extra \mb_extra + connect \rotator_mb \mb + connect \rotator_me \me + connect \mb_extra \sr_op__insn [5] + connect \me \sr_op__insn [5:1] + connect \mb \sr_op__insn [10:6] +end +attribute \src "issuer_ls180.v:132492.1-133022.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.fus.branch0.alu_branch0.pipe.main" +attribute \generator "nMigen" +module \main$22 + attribute \src "issuer_ls180.v:132929.3-132952.6" + wire $0\bc_taken[0:0] + attribute \src "issuer_ls180.v:132808.3-132819.6" + wire width 64 $0\br_addr[63:0] + attribute \src "issuer_ls180.v:132820.3-132846.6" + wire width 64 $0\br_imm_addr[63:0] + attribute \src "issuer_ls180.v:132847.3-132865.6" + wire $0\br_taken[0:0] + attribute \src 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attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 output 15 \br_op__fn_unit$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 input 5 \br_op__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 output 17 \br_op__imm_data__data$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 6 \br_op__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 18 \br_op__imm_data__ok$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 4 \br_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 output 16 \br_op__insn$5 + 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attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 input 2 \br_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 output 14 \br_op__insn_type$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 8 \br_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 20 \br_op__is_32bit$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 7 \br_op__lk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 19 \br_op__lk$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:89" + wire \br_taken + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 4 input 11 \cr_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:110" + wire \cr_bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:129" + wire width 64 \ctr_m + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:124" + wire width 64 \ctr_n + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:115" + wire \ctr_write + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:135" + wire \ctr_zero_bo1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 9 \fast1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 output 21 \fast1$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 22 \fast1_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 10 \fast2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 output 23 \fast2$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 24 \fast2_ok + attribute \src "issuer_ls180.v:132493.7-132493.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 input 27 \muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 output 12 \muxid$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 output 25 \nia + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 26 \nia_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:95" + cell $add $add$issuer_ls180.v:132792$6352 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 64 + parameter \Y_WIDTH 65 + connect \A \br_imm_addr + connect \B \br_op__cia + connect \Y $add$issuer_ls180.v:132792$6352_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:175" + cell $add $add$issuer_ls180.v:132807$6368 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 65 + connect \A \br_op__cia + connect \B 3'100 + connect \Y $add$issuer_ls180.v:132807$6368_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:138" + cell $and $and$issuer_ls180.v:132799$6359 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \ctr_zero_bo1 + connect \B \$29 + connect \Y $and$issuer_ls180.v:132799$6359_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:140" + cell $and $and$issuer_ls180.v:132800$6360 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \ctr_zero_bo1 + connect \B \cr_bit + connect \Y $and$issuer_ls180.v:132800$6360_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:160" + cell $and $and$issuer_ls180.v:132806$6367 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \br_op__insn [10] + connect \B \$44 + connect \Y $and$issuer_ls180.v:132806$6367_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:92" + cell $eq $eq$issuer_ls180.v:132790$6350 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \br_op__insn_type + connect \B 7'0001000 + connect \Y $eq$issuer_ls180.v:132790$6350_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:121" + cell $eq $eq$issuer_ls180.v:132793$6353 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cr_bit + connect \B \bo [3] + connect \Y $eq$issuer_ls180.v:132793$6353_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:137" + cell $eq $eq$issuer_ls180.v:132795$6355 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \bo [4:3] + connect \B 1'0 + connect \Y $eq$issuer_ls180.v:132795$6355_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:139" + cell $eq $eq$issuer_ls180.v:132796$6356 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \bo [4:3] + connect \B 1'1 + connect \Y $eq$issuer_ls180.v:132796$6356_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:141" + cell $eq $eq$issuer_ls180.v:132797$6357 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \bo [4] + connect \B 1'1 + connect \Y $eq$issuer_ls180.v:132797$6357_Y + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:265" + cell $pos $extend$issuer_ls180.v:132802$6362 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \Y_WIDTH 64 + connect \A \fast1 [31:0] + connect \Y $extend$issuer_ls180.v:132802$6362_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:138" + cell $not $not$issuer_ls180.v:132798$6358 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cr_bit + connect \Y $not$issuer_ls180.v:132798$6358_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:160" + cell $not $not$issuer_ls180.v:132805$6366 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \br_op__insn [6] + connect \Y $not$issuer_ls180.v:132805$6366_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:92" + cell $or $or$issuer_ls180.v:132791$6351 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \br_op__insn [1] + connect \B \$12 + connect \Y $or$issuer_ls180.v:132791$6351_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:121" + cell $or $or$issuer_ls180.v:132794$6354 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$19 + connect \B \bo [4] + connect \Y $or$issuer_ls180.v:132794$6354_Y + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:265" + cell $pos $pos$issuer_ls180.v:132802$6363 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A $extend$issuer_ls180.v:132802$6362_Y + connect \Y $pos$issuer_ls180.v:132802$6363_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:136" + cell $reduce_or $reduce_or$issuer_ls180.v:132803$6364 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 1 + connect \A \ctr_n + connect \Y $reduce_or$issuer_ls180.v:132803$6364_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:125" + cell $sub $sub$issuer_ls180.v:132801$6361 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 65 + connect \A \fast1 + connect \B 1'1 + connect \Y $sub$issuer_ls180.v:132801$6361_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:136" + cell $xor $xor$issuer_ls180.v:132804$6365 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \bo [1] + connect \B \$40 + connect \Y $xor$issuer_ls180.v:132804$6365_Y + end + attribute \src "issuer_ls180.v:132493.7-132493.20" + process $proc$issuer_ls180.v:132493$6386 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "issuer_ls180.v:132808.3-132819.6" + process $proc$issuer_ls180.v:132808$6369 + assign { } { } + assign $0\br_addr[63:0] $1\br_addr[63:0] + attribute \src "issuer_ls180.v:132809.5-132809.29" + switch \initial + attribute \src "issuer_ls180.v:132809.9-132809.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:92" + switch \$14 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\br_addr[63:0] \br_imm_addr + attribute \src "issuer_ls180.v:0.0-0.0" + case + assign { } { } + assign $1\br_addr[63:0] \$16 [63:0] + end + sync always + update \br_addr $0\br_addr[63:0] + end + attribute \src "issuer_ls180.v:132820.3-132846.6" + process $proc$issuer_ls180.v:132820$6370 + assign { } { } + assign { } { } + assign $0\br_imm_addr[63:0] $1\br_imm_addr[63:0] + attribute \src "issuer_ls180.v:132821.5-132821.29" + switch \initial + attribute \src "issuer_ls180.v:132821.9-132821.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:145" + switch \br_op__insn_type + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'0000110 + assign { } { } + assign $1\br_imm_addr[63:0] { \br_op__insn [25] \br_op__insn [25] \br_op__insn [25] \br_op__insn [25] \br_op__insn [25] \br_op__insn [25] \br_op__insn [25] \br_op__insn [25] \br_op__insn [25] \br_op__insn [25] \br_op__insn [25] \br_op__insn [25] \br_op__insn [25] \br_op__insn [25] \br_op__insn [25] \br_op__insn [25] \br_op__insn [25] \br_op__insn [25] \br_op__insn [25] \br_op__insn [25] \br_op__insn [25] \br_op__insn [25] \br_op__insn [25] \br_op__insn [25] \br_op__insn [25] \br_op__insn [25] \br_op__insn [25] \br_op__insn [25] \br_op__insn [25] \br_op__insn [25] \br_op__insn [25] \br_op__insn [25] \br_op__insn [25] \br_op__insn [25] \br_op__insn [25] \br_op__insn [25] \br_op__insn [25] \br_op__insn [25] \br_op__insn [25:2] 2'00 } + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'0000111 + assign { } { } + assign $1\br_imm_addr[63:0] { \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15] \br_op__insn [15:2] 2'00 } + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'0001000 + assign { } { } + assign $1\br_imm_addr[63:0] $2\br_imm_addr[63:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:160" + switch \$46 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\br_imm_addr[63:0] { \fast1 [63:2] 2'00 } + attribute \src "issuer_ls180.v:0.0-0.0" + case + assign { } { } + assign $2\br_imm_addr[63:0] { \fast2 [63:2] 2'00 } + end + case + assign $1\br_imm_addr[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \br_imm_addr $0\br_imm_addr[63:0] + end + attribute \src "issuer_ls180.v:132847.3-132865.6" + process $proc$issuer_ls180.v:132847$6371 + assign { } { } + assign { } { } + assign $0\br_taken[0:0] $1\br_taken[0:0] + attribute \src "issuer_ls180.v:132848.5-132848.29" + switch \initial + attribute \src "issuer_ls180.v:132848.9-132848.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:145" + switch \br_op__insn_type + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'0000110 + assign { } { } + assign $1\br_taken[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'0000111 + assign { } { } + assign $1\br_taken[0:0] \bc_taken + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'0001000 + assign { } { } + assign $1\br_taken[0:0] \bc_taken + case + assign $1\br_taken[0:0] 1'0 + end + sync always + update \br_taken $0\br_taken[0:0] + end + attribute \src "issuer_ls180.v:132866.3-132880.6" + process $proc$issuer_ls180.v:132866$6372 + assign { } { } + assign { } { } + assign $0\fast1_ok[0:0] $1\fast1_ok[0:0] + attribute \src "issuer_ls180.v:132867.5-132867.29" + switch \initial + attribute \src "issuer_ls180.v:132867.9-132867.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:145" + switch \br_op__insn_type + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'0000111 + assign { } { } + assign $1\fast1_ok[0:0] \ctr_write + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'0001000 + assign { } { } + assign $1\fast1_ok[0:0] \ctr_write + case + assign $1\fast1_ok[0:0] 1'0 + end + sync always + update \fast1_ok $0\fast1_ok[0:0] + end + attribute \src "issuer_ls180.v:132881.3-132890.6" + process $proc$issuer_ls180.v:132881$6373 + assign { } { } + assign { } { } + assign $0\fast2$11[63:0]$6374 $1\fast2$11[63:0]$6375 + attribute \src "issuer_ls180.v:132882.5-132882.29" + switch \initial + attribute \src "issuer_ls180.v:132882.9-132882.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:172" + switch \br_op__lk + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fast2$11[63:0]$6375 \$48 [63:0] + case + assign $1\fast2$11[63:0]$6375 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \fast2$11 $0\fast2$11[63:0]$6374 + end + attribute \src "issuer_ls180.v:132891.3-132900.6" + process $proc$issuer_ls180.v:132891$6376 + assign { } { } + assign { } { } + assign $0\fast2_ok[0:0] $1\fast2_ok[0:0] + attribute \src "issuer_ls180.v:132892.5-132892.29" + switch \initial + attribute \src "issuer_ls180.v:132892.9-132892.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:172" + switch \br_op__lk + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\fast2_ok[0:0] 1'1 + case + assign $1\fast2_ok[0:0] 1'0 + end + sync always + update \fast2_ok $0\fast2_ok[0:0] + end + attribute \src "issuer_ls180.v:132901.3-132915.6" + process $proc$issuer_ls180.v:132901$6377 + assign { } { } + assign { } { } + assign $0\cr_bit[0:0] $1\cr_bit[0:0] + attribute \src "issuer_ls180.v:132902.5-132902.29" + switch \initial + attribute \src "issuer_ls180.v:132902.9-132902.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:112" + switch \bi + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\cr_bit[0:0] \cr_a [3] + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\cr_bit[0:0] \cr_a [2] + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\cr_bit[0:0] \cr_a [1] + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'-- + assign { } { } + assign $1\cr_bit[0:0] \cr_a [0] + case + assign $1\cr_bit[0:0] 1'0 + end + sync always + update \cr_bit $0\cr_bit[0:0] + end + attribute \src "issuer_ls180.v:132916.3-132928.6" + process $proc$issuer_ls180.v:132916$6378 + assign { } { } + assign { } { } + assign $0\ctr_write[0:0] $1\ctr_write[0:0] + attribute \src "issuer_ls180.v:132917.5-132917.29" + switch \initial + attribute \src "issuer_ls180.v:132917.9-132917.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:120" + switch \bo [2] + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign $1\ctr_write[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case + assign { } { } + assign $1\ctr_write[0:0] 1'1 + end + sync always + update \ctr_write $0\ctr_write[0:0] + end + attribute \src "issuer_ls180.v:132929.3-132952.6" + process $proc$issuer_ls180.v:132929$6379 + assign { } { } + assign { } { } + assign $0\bc_taken[0:0] $1\bc_taken[0:0] + attribute \src "issuer_ls180.v:132930.5-132930.29" + switch \initial + attribute \src "issuer_ls180.v:132930.9-132930.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:120" + switch \bo [2] + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\bc_taken[0:0] \$21 + attribute \src "issuer_ls180.v:0.0-0.0" + case + assign { } { } + assign $1\bc_taken[0:0] $2\bc_taken[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:137" + switch { \$27 \$25 \$23 } + attribute \src "issuer_ls180.v:0.0-0.0" + case 3'--1 + assign { } { } + assign $2\bc_taken[0:0] \$31 + attribute \src "issuer_ls180.v:0.0-0.0" + case 3'-1- + assign { } { } + assign $2\bc_taken[0:0] \$33 + attribute \src "issuer_ls180.v:0.0-0.0" + case 3'1-- + assign { } { } + assign $2\bc_taken[0:0] \ctr_zero_bo1 + case + assign $2\bc_taken[0:0] 1'0 + end + end + sync always + update \bc_taken $0\bc_taken[0:0] + end + attribute \src "issuer_ls180.v:132953.3-132965.6" + process $proc$issuer_ls180.v:132953$6380 + assign { } { } + assign { } { } + assign $0\ctr_n[63:0] $1\ctr_n[63:0] + attribute \src "issuer_ls180.v:132954.5-132954.29" + switch \initial + attribute \src "issuer_ls180.v:132954.9-132954.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:120" + switch \bo [2] + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign $1\ctr_n[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "issuer_ls180.v:0.0-0.0" + case + assign { } { } + assign $1\ctr_n[63:0] \$35 [63:0] + end + sync always + update \ctr_n $0\ctr_n[63:0] + end + attribute \src "issuer_ls180.v:132966.3-132978.6" + process $proc$issuer_ls180.v:132966$6381 + assign { } { } + assign { } { } + assign $0\fast1$10[63:0]$6382 $1\fast1$10[63:0]$6383 + attribute \src "issuer_ls180.v:132967.5-132967.29" + switch \initial + attribute \src "issuer_ls180.v:132967.9-132967.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:120" + switch \bo [2] + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign $1\fast1$10[63:0]$6383 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "issuer_ls180.v:0.0-0.0" + case + assign { } { } + assign $1\fast1$10[63:0]$6383 \ctr_n + end + sync always + update \fast1$10 $0\fast1$10[63:0]$6382 + end + attribute \src "issuer_ls180.v:132979.3-132999.6" + process $proc$issuer_ls180.v:132979$6384 + assign { } { } + assign { } { } + assign $0\ctr_m[63:0] $1\ctr_m[63:0] + attribute \src "issuer_ls180.v:132980.5-132980.29" + switch \initial + attribute \src "issuer_ls180.v:132980.9-132980.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:120" + switch \bo [2] + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign $1\ctr_m[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "issuer_ls180.v:0.0-0.0" + case + assign { } { } + assign $1\ctr_m[63:0] $2\ctr_m[63:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:130" + switch \br_op__is_32bit + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\ctr_m[63:0] \$38 + attribute \src "issuer_ls180.v:0.0-0.0" + case + assign { } { } + assign $2\ctr_m[63:0] \fast1 + end + end + sync always + update \ctr_m $0\ctr_m[63:0] + end + attribute \src "issuer_ls180.v:133000.3-133012.6" + process $proc$issuer_ls180.v:133000$6385 + assign { } { } + assign { } { } + assign $0\ctr_zero_bo1[0:0] $1\ctr_zero_bo1[0:0] + attribute \src "issuer_ls180.v:133001.5-133001.29" + switch \initial + attribute \src "issuer_ls180.v:133001.9-133001.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:120" + switch \bo [2] + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign $1\ctr_zero_bo1[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case + assign { } { } + assign $1\ctr_zero_bo1[0:0] \$42 + end + sync always + update \ctr_zero_bo1 $0\ctr_zero_bo1[0:0] + end + connect \$12 $eq$issuer_ls180.v:132790$6350_Y + connect \$14 $or$issuer_ls180.v:132791$6351_Y + connect \$17 $add$issuer_ls180.v:132792$6352_Y + connect \$19 $eq$issuer_ls180.v:132793$6353_Y + connect \$21 $or$issuer_ls180.v:132794$6354_Y + connect \$23 $eq$issuer_ls180.v:132795$6355_Y + connect \$25 $eq$issuer_ls180.v:132796$6356_Y + connect \$27 $eq$issuer_ls180.v:132797$6357_Y + connect \$29 $not$issuer_ls180.v:132798$6358_Y + connect \$31 $and$issuer_ls180.v:132799$6359_Y + connect \$33 $and$issuer_ls180.v:132800$6360_Y + connect \$36 $sub$issuer_ls180.v:132801$6361_Y + connect \$38 $pos$issuer_ls180.v:132802$6363_Y + connect \$40 $reduce_or$issuer_ls180.v:132803$6364_Y + connect \$42 $xor$issuer_ls180.v:132804$6365_Y + connect \$44 $not$issuer_ls180.v:132805$6366_Y + connect \$46 $and$issuer_ls180.v:132806$6367_Y + connect \$49 $add$issuer_ls180.v:132807$6368_Y + connect \$16 \$17 + connect \$35 \$36 + connect \$48 \$49 + connect { \br_op__is_32bit$9 \br_op__lk$8 \br_op__imm_data__ok$7 \br_op__imm_data__data$6 \br_op__insn$5 \br_op__fn_unit$4 \br_op__insn_type$3 \br_op__cia$2 } { \br_op__is_32bit \br_op__lk \br_op__imm_data__ok \br_op__imm_data__data \br_op__insn \br_op__fn_unit \br_op__insn_type \br_op__cia } + connect \muxid$1 \muxid + connect \nia_ok \br_taken + connect \nia \br_addr + connect \bi \br_op__insn [17:16] + connect \bo \br_op__insn [25:21] +end +attribute \src "issuer_ls180.v:133026.1-133899.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.fus.trap0.alu_trap0.pipe.main" +attribute \generator "nMigen" +module \main$35 + attribute \src "issuer_ls180.v:133864.3-133875.6" + wire width 64 $0\a[63:0] + attribute \src "issuer_ls180.v:133401.3-133412.6" + wire width 64 $0\a_s[63:0] + attribute \src "issuer_ls180.v:133876.3-133887.6" + wire width 64 $0\b[63:0] + attribute \src "issuer_ls180.v:133814.3-133825.6" + wire width 64 $0\b_s[63:0] + attribute \src "issuer_ls180.v:133477.3-133508.6" + wire width 64 $0\fast1$10[63:0]$6428 + attribute \src "issuer_ls180.v:133509.3-133540.6" + wire $0\fast1_ok[0:0] + attribute \src "issuer_ls180.v:133541.3-133612.6" + wire width 64 $0\fast2$11[63:0]$6433 + attribute \src "issuer_ls180.v:133613.3-133644.6" + wire $0\fast2_ok[0:0] + attribute \src "issuer_ls180.v:133027.7-133027.20" + wire $0\initial[0:0] + attribute \src "issuer_ls180.v:133645.3-133813.6" + wire width 64 $0\msr[63:0] + attribute \src "issuer_ls180.v:133645.3-133813.6" + wire $0\msr_ok[0:0] + attribute \src "issuer_ls180.v:133413.3-133444.6" + wire width 64 $0\nia[63:0] + attribute \src "issuer_ls180.v:133445.3-133476.6" + wire $0\nia_ok[0:0] + attribute \src "issuer_ls180.v:133826.3-133844.6" + wire width 64 $0\o[63:0] + attribute \src "issuer_ls180.v:133845.3-133863.6" + wire $0\o_ok[0:0] + attribute \src "issuer_ls180.v:133645.3-133813.6" + wire width 2 $10\msr[5:4] + attribute \src "issuer_ls180.v:133645.3-133813.6" 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"issuer_ls180.v:133509.3-133540.6" + wire $1\fast1_ok[0:0] + attribute \src "issuer_ls180.v:133541.3-133612.6" + wire width 64 $1\fast2$11[63:0]$6434 + attribute \src "issuer_ls180.v:133613.3-133644.6" + wire $1\fast2_ok[0:0] + attribute \src "issuer_ls180.v:133645.3-133813.6" + wire width 64 $1\msr[63:0] + attribute \src "issuer_ls180.v:133645.3-133813.6" + wire $1\msr_ok[0:0] + attribute \src "issuer_ls180.v:133413.3-133444.6" + wire width 64 $1\nia[63:0] + attribute \src "issuer_ls180.v:133445.3-133476.6" + wire $1\nia_ok[0:0] + attribute \src "issuer_ls180.v:133826.3-133844.6" + wire width 64 $1\o[63:0] + attribute \src "issuer_ls180.v:133845.3-133863.6" + wire $1\o_ok[0:0] + attribute \src "issuer_ls180.v:133477.3-133508.6" + wire width 64 $2\fast1$10[63:0]$6430 + attribute \src "issuer_ls180.v:133509.3-133540.6" + wire $2\fast1_ok[0:0] + attribute \src "issuer_ls180.v:133541.3-133612.6" + wire width 64 $2\fast2$11[63:0]$6435 + attribute \src "issuer_ls180.v:133613.3-133644.6" + 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"/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 11 \fast1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 output 24 \fast1$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 25 \fast1_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 12 \fast2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 output 26 \fast2$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 27 \fast2_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:157" + wire \gt_s + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:159" + wire \gt_u + attribute \src "issuer_ls180.v:133027.7-133027.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:156" + wire \lt_s + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:158" + wire \lt_u + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 output 30 \msr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 31 \msr_ok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 input 32 \muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 output 13 \muxid$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 output 28 \nia + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 29 \nia_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 output 22 \o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 23 \o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 9 \ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 10 \rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:175" + wire \should_trap + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:133" + wire width 5 \to + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:170" + wire width 5 \trap_bits + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 input 5 \trap_op__cia + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 output 18 \trap_op__cia$6 + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 input 2 \trap_op__fn_unit + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 output 15 \trap_op__fn_unit$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 3 \trap_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 output 16 \trap_op__insn$4 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 input 1 \trap_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 output 14 \trap_op__insn_type$2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 6 \trap_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 19 \trap_op__is_32bit$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 input 4 \trap_op__msr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 output 17 \trap_op__msr$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 13 input 8 \trap_op__trapaddr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 13 output 21 \trap_op__trapaddr$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 input 7 \trap_op__traptype + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 output 20 \trap_op__traptype$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:306" + cell $add $add$issuer_ls180.v:133381$6403 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 65 + connect \A \trap_op__cia + connect \B 3'100 + connect \Y $add$issuer_ls180.v:133381$6403_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:176" + cell $and $and$issuer_ls180.v:133375$6396 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 5 + connect \A \trap_bits + connect \B \to + connect \Y $and$issuer_ls180.v:133375$6396_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:192" + cell $and $and$issuer_ls180.v:133383$6405 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 7 + connect \A \trap_op__traptype + connect \B 2'10 + connect \Y $and$issuer_ls180.v:133383$6405_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:194" + cell $and $and$issuer_ls180.v:133385$6407 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 7 + connect \A \trap_op__traptype + connect \B 1'1 + connect \Y $and$issuer_ls180.v:133385$6407_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:196" + cell $and $and$issuer_ls180.v:133387$6409 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 7 + connect \A \trap_op__traptype + connect \B 4'1000 + connect \Y $and$issuer_ls180.v:133387$6409_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:204" + cell $and $and$issuer_ls180.v:133389$6411 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 7 + connect \A \trap_op__traptype + connect \B 7'1000000 + connect \Y $and$issuer_ls180.v:133389$6411_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:232" + cell $and $and$issuer_ls180.v:133395$6418 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$63 + connect \B \$65 + connect \Y $and$issuer_ls180.v:133395$6418_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:287" + cell $and $and$issuer_ls180.v:133400$6423 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$73 + connect \B \$75 + connect \Y $and$issuer_ls180.v:133400$6423_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:166" + cell $eq $eq$issuer_ls180.v:133374$6395 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 64 + parameter \Y_WIDTH 1 + connect \A \a + connect \B \b + connect \Y $eq$issuer_ls180.v:133374$6395_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:189" + cell $eq $eq$issuer_ls180.v:133382$6404 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \trap_op__traptype + connect \B 1'0 + connect \Y $eq$issuer_ls180.v:133382$6404_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:225" + cell $eq $eq$issuer_ls180.v:133392$6415 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \trap_op__insn_type + connect \B 7'1001000 + connect \Y $eq$issuer_ls180.v:133392$6415_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:231" + cell $eq $eq$issuer_ls180.v:133393$6416 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \trap_op__msr [34:32] + connect \B 3'010 + connect \Y $eq$issuer_ls180.v:133393$6416_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:232" + cell $eq $eq$issuer_ls180.v:133394$6417 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \ra [34:32] + connect \B 3'000 + connect \Y $eq$issuer_ls180.v:133394$6417_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:286" + cell $eq $eq$issuer_ls180.v:133398$6421 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \trap_op__msr [34:32] + connect \B 3'010 + connect \Y $eq$issuer_ls180.v:133398$6421_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:287" + cell $eq $eq$issuer_ls180.v:133399$6422 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \fast2 [34:32] + connect \B 3'000 + connect \Y $eq$issuer_ls180.v:133399$6422_Y + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:265" + cell $pos $extend$issuer_ls180.v:133368$6387 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \Y_WIDTH 64 + connect \A \ra [31:0] + connect \Y $extend$issuer_ls180.v:133368$6387_Y + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:265" + cell $pos $extend$issuer_ls180.v:133369$6389 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \Y_WIDTH 64 + connect \A \rb [31:0] + connect \Y $extend$issuer_ls180.v:133369$6389_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:188" + cell $pos $extend$issuer_ls180.v:133380$6401 + parameter \A_SIGNED 0 + parameter \A_WIDTH 20 + parameter \Y_WIDTH 64 + connect \A \$35 + connect \Y $extend$issuer_ls180.v:133380$6401_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + cell $pos $extend$issuer_ls180.v:133391$6413 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 65 + connect \A \trap_op__msr + connect \Y $extend$issuer_ls180.v:133391$6413_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:163" + cell $gt $gt$issuer_ls180.v:133371$6392 + parameter \A_SIGNED 1 + parameter \A_WIDTH 64 + parameter \B_SIGNED 1 + parameter \B_WIDTH 64 + parameter \Y_WIDTH 1 + connect \A \a_s + connect \B \b_s + connect \Y $gt$issuer_ls180.v:133371$6392_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:165" + cell $gt $gt$issuer_ls180.v:133373$6394 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 64 + parameter \Y_WIDTH 1 + connect \A \a + connect \B \b + connect \Y $gt$issuer_ls180.v:133373$6394_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:162" + cell $lt $lt$issuer_ls180.v:133370$6391 + parameter \A_SIGNED 1 + parameter \A_WIDTH 64 + parameter \B_SIGNED 1 + parameter \B_WIDTH 64 + parameter \Y_WIDTH 1 + connect \A \a_s + connect \B \b_s + connect \Y $lt$issuer_ls180.v:133370$6391_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:164" + cell $lt $lt$issuer_ls180.v:133372$6393 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 64 + parameter \Y_WIDTH 1 + connect \A \a + connect \B \b + connect \Y $lt$issuer_ls180.v:133372$6393_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:247" + cell $not $not$issuer_ls180.v:133396$6419 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \trap_op__msr [60] + connect \Y $not$issuer_ls180.v:133396$6419_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:273" + cell $not $not$issuer_ls180.v:133397$6420 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \trap_op__insn [9] + connect \Y $not$issuer_ls180.v:133397$6420_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:176" + cell $or $or$issuer_ls180.v:133378$6399 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$26 + connect \B \$30 + connect \Y $or$issuer_ls180.v:133378$6399_Y + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:265" + cell $pos $pos$issuer_ls180.v:133368$6388 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A $extend$issuer_ls180.v:133368$6387_Y + connect \Y $pos$issuer_ls180.v:133368$6388_Y + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:265" + cell $pos $pos$issuer_ls180.v:133369$6390 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A $extend$issuer_ls180.v:133369$6389_Y + connect \Y $pos$issuer_ls180.v:133369$6390_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:188" + cell $pos $pos$issuer_ls180.v:133380$6402 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A $extend$issuer_ls180.v:133380$6401_Y + connect \Y $pos$issuer_ls180.v:133380$6402_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + cell $pos $pos$issuer_ls180.v:133391$6414 + parameter \A_SIGNED 0 + parameter \A_WIDTH 65 + parameter \Y_WIDTH 65 + connect \A $extend$issuer_ls180.v:133391$6413_Y + connect \Y $pos$issuer_ls180.v:133391$6414_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:176" + cell $reduce_or $reduce_or$issuer_ls180.v:133376$6397 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \$27 + connect \Y $reduce_or$issuer_ls180.v:133376$6397_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:176" + cell $reduce_or $reduce_or$issuer_ls180.v:133377$6398 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \trap_op__traptype + connect \Y $reduce_or$issuer_ls180.v:133377$6398_Y + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" + cell $reduce_or $reduce_or$issuer_ls180.v:133384$6406 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \$44 + connect \Y $reduce_or$issuer_ls180.v:133384$6406_Y + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" + cell $reduce_or $reduce_or$issuer_ls180.v:133386$6408 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \$48 + connect \Y $reduce_or$issuer_ls180.v:133386$6408_Y + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" + cell $reduce_or $reduce_or$issuer_ls180.v:133388$6410 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \$52 + connect \Y $reduce_or$issuer_ls180.v:133388$6410_Y + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" + cell $reduce_or $reduce_or$issuer_ls180.v:133390$6412 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \$56 + connect \Y $reduce_or$issuer_ls180.v:133390$6412_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:188" + cell $sshl $sshl$issuer_ls180.v:133379$6400 + parameter \A_SIGNED 0 + parameter \A_WIDTH 13 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 20 + connect \A \trap_op__trapaddr + connect \B 3'100 + connect \Y $sshl$issuer_ls180.v:133379$6400_Y + end + attribute \src "issuer_ls180.v:133027.7-133027.20" + process $proc$issuer_ls180.v:133027$6448 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "issuer_ls180.v:133401.3-133412.6" + process $proc$issuer_ls180.v:133401$6424 + assign { } { } + assign $0\a_s[63:0] $1\a_s[63:0] + attribute \src "issuer_ls180.v:133402.5-133402.29" + switch \initial + attribute \src "issuer_ls180.v:133402.9-133402.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:144" + switch \trap_op__is_32bit + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\a_s[63:0] { \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31] \ra [31:0] } + attribute \src "issuer_ls180.v:0.0-0.0" + case + assign { } { } + assign $1\a_s[63:0] \ra + end + sync always + update \a_s $0\a_s[63:0] + end + attribute \src "issuer_ls180.v:133413.3-133444.6" + process $proc$issuer_ls180.v:133413$6425 + assign { } { } + assign { } { } + assign $0\nia[63:0] $1\nia[63:0] + attribute \src "issuer_ls180.v:133414.5-133414.29" + switch \initial + attribute \src "issuer_ls180.v:133414.9-133414.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:179" + switch \trap_op__insn_type + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'0111111 + assign { } { } + assign $1\nia[63:0] $2\nia[63:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:186" + switch \should_trap + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\nia[63:0] \$34 + case + assign $2\nia[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'1001000 , 7'1001010 + assign $1\nia[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'1000111 + assign $1\nia[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'1000110 + assign { } { } + assign $1\nia[63:0] { \fast1 [63:2] 2'00 } + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'1001001 + assign { } { } + assign $1\nia[63:0] 64'0000000000000000000000000000000000000000000000000000110000000000 + case + assign $1\nia[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \nia $0\nia[63:0] + end + attribute \src "issuer_ls180.v:133445.3-133476.6" + process $proc$issuer_ls180.v:133445$6426 + assign { } { } + assign { } { } + assign $0\nia_ok[0:0] $1\nia_ok[0:0] + attribute \src "issuer_ls180.v:133446.5-133446.29" + switch \initial + attribute \src "issuer_ls180.v:133446.9-133446.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:179" + switch \trap_op__insn_type + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'0111111 + assign { } { } + assign $1\nia_ok[0:0] $2\nia_ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:186" + switch \should_trap + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\nia_ok[0:0] 1'1 + case + assign $2\nia_ok[0:0] 1'0 + end + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'1001000 , 7'1001010 + assign $1\nia_ok[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'1000111 + assign $1\nia_ok[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'1000110 + assign { } { } + assign $1\nia_ok[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'1001001 + assign { } { } + assign $1\nia_ok[0:0] 1'1 + case + assign $1\nia_ok[0:0] 1'0 + end + sync always + update \nia_ok $0\nia_ok[0:0] + end + attribute \src "issuer_ls180.v:133477.3-133508.6" + process $proc$issuer_ls180.v:133477$6427 + assign { } { } + assign { } { } + assign $0\fast1$10[63:0]$6428 $1\fast1$10[63:0]$6429 + attribute \src "issuer_ls180.v:133478.5-133478.29" + switch \initial + attribute \src "issuer_ls180.v:133478.9-133478.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:179" + switch \trap_op__insn_type + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'0111111 + assign { } { } + assign $1\fast1$10[63:0]$6429 $2\fast1$10[63:0]$6430 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:186" + switch \should_trap + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\fast1$10[63:0]$6430 \trap_op__cia + case + assign $2\fast1$10[63:0]$6430 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'1001000 , 7'1001010 + assign $1\fast1$10[63:0]$6429 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'1000111 + assign $1\fast1$10[63:0]$6429 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'1000110 + assign $1\fast1$10[63:0]$6429 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'1001001 + assign { } { } + assign $1\fast1$10[63:0]$6429 \$38 [63:0] + case + assign $1\fast1$10[63:0]$6429 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \fast1$10 $0\fast1$10[63:0]$6428 + end + attribute \src "issuer_ls180.v:133509.3-133540.6" + process $proc$issuer_ls180.v:133509$6431 + assign { } { } + assign { } { } + assign $0\fast1_ok[0:0] $1\fast1_ok[0:0] + attribute \src "issuer_ls180.v:133510.5-133510.29" + switch \initial + attribute \src "issuer_ls180.v:133510.9-133510.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:179" + switch \trap_op__insn_type + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'0111111 + assign { } { } + assign $1\fast1_ok[0:0] $2\fast1_ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:186" + switch \should_trap + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\fast1_ok[0:0] 1'1 + case + assign $2\fast1_ok[0:0] 1'0 + end + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'1001000 , 7'1001010 + assign $1\fast1_ok[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'1000111 + assign $1\fast1_ok[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'1000110 + assign $1\fast1_ok[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'1001001 + assign { } { } + assign $1\fast1_ok[0:0] 1'1 + case + assign $1\fast1_ok[0:0] 1'0 + end + sync always + update \fast1_ok $0\fast1_ok[0:0] + end + attribute \src "issuer_ls180.v:133541.3-133612.6" + process $proc$issuer_ls180.v:133541$6432 + assign { } { } + assign { } { } + assign $0\fast2$11[63:0]$6433 $1\fast2$11[63:0]$6434 + attribute \src "issuer_ls180.v:133542.5-133542.29" + switch \initial + attribute \src "issuer_ls180.v:133542.9-133542.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:179" + switch \trap_op__insn_type + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'0111111 + assign { } { } + assign $1\fast2$11[63:0]$6434 $2\fast2$11[63:0]$6435 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:186" + switch \should_trap + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign { $2\fast2$11[63:0]$6435 [30:27] $2\fast2$11[63:0]$6435 [21] } 5'00000 + assign $2\fast2$11[63:0]$6435 [15:0] \trap_op__msr [15:0] + assign $2\fast2$11[63:0]$6435 [26:22] \trap_op__msr [26:22] + assign $2\fast2$11[63:0]$6435 [63:31] \trap_op__msr [63:31] + assign $2\fast2$11[63:0]$6435 [17] $3\fast2$11[17:17]$6436 + assign $2\fast2$11[63:0]$6435 [18] $4\fast2$11[18:18]$6437 + assign $2\fast2$11[63:0]$6435 [20] $5\fast2$11[20:20]$6438 + assign $2\fast2$11[63:0]$6435 [16] $6\fast2$11[16:16]$6439 + assign $2\fast2$11[63:0]$6435 [19] $7\fast2$11[19:19]$6440 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:189" + switch \$41 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fast2$11[17:17]$6436 1'1 + case + assign $3\fast2$11[17:17]$6436 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:192" + switch \$43 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\fast2$11[18:18]$6437 1'1 + case + assign $4\fast2$11[18:18]$6437 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:194" + switch \$47 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\fast2$11[20:20]$6438 1'1 + case + assign $5\fast2$11[20:20]$6438 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:196" + switch \$51 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $6\fast2$11[16:16]$6439 1'1 + case + assign $6\fast2$11[16:16]$6439 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:204" + switch \$55 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $7\fast2$11[19:19]$6440 1'1 + case + assign $7\fast2$11[19:19]$6440 1'0 + end + case + assign $2\fast2$11[63:0]$6435 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'1001000 , 7'1001010 + assign $1\fast2$11[63:0]$6434 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'1000111 + assign $1\fast2$11[63:0]$6434 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'1000110 + assign $1\fast2$11[63:0]$6434 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'1001001 + assign { } { } + assign { $1\fast2$11[63:0]$6434 [30:27] $1\fast2$11[63:0]$6434 [21:16] } 10'0000000000 + assign $1\fast2$11[63:0]$6434 [15:0] \trap_op__msr [15:0] + assign $1\fast2$11[63:0]$6434 [26:22] \trap_op__msr [26:22] + assign $1\fast2$11[63:0]$6434 [63:31] \trap_op__msr [63:31] + case + assign $1\fast2$11[63:0]$6434 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \fast2$11 $0\fast2$11[63:0]$6433 + end + attribute \src "issuer_ls180.v:133613.3-133644.6" + process $proc$issuer_ls180.v:133613$6441 + assign { } { } + assign { } { } + assign $0\fast2_ok[0:0] $1\fast2_ok[0:0] + attribute \src "issuer_ls180.v:133614.5-133614.29" + switch \initial + attribute \src "issuer_ls180.v:133614.9-133614.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:179" + switch \trap_op__insn_type + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'0111111 + assign { } { } + assign $1\fast2_ok[0:0] $2\fast2_ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:186" + switch \should_trap + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\fast2_ok[0:0] 1'1 + case + assign $2\fast2_ok[0:0] 1'0 + end + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'1001000 , 7'1001010 + assign $1\fast2_ok[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'1000111 + assign $1\fast2_ok[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'1000110 + assign $1\fast2_ok[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'1001001 + assign { } { } + assign $1\fast2_ok[0:0] 1'1 + case + assign $1\fast2_ok[0:0] 1'0 + end + sync always + update \fast2_ok $0\fast2_ok[0:0] + end + attribute \src "issuer_ls180.v:133645.3-133813.6" + process $proc$issuer_ls180.v:133645$6442 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\msr[63:0] $1\msr[63:0] + assign $0\msr_ok[0:0] $1\msr_ok[0:0] + attribute \src "issuer_ls180.v:133646.5-133646.29" + switch \initial + attribute \src "issuer_ls180.v:133646.9-133646.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:179" + switch \trap_op__insn_type + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'0111111 + assign { } { } + assign { } { } + assign $1\msr[63:0] $2\msr[63:0] + assign $1\msr_ok[0:0] $2\msr_ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:186" + switch \should_trap + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $2\msr[63:0] [62:59] $2\msr[63:0] [57:33] $2\msr[63:0] [31:26] $2\msr[63:0] [24] $2\msr[63:0] [22:16] $2\msr[63:0] [12] $2\msr[63:0] [7:6] $2\msr[63:0] [2] } { \trap_op__msr [62:59] \trap_op__msr [57:33] \trap_op__msr [31:26] \trap_op__msr [24] \trap_op__msr [22:16] \trap_op__msr [12] \trap_op__msr [7:6] \trap_op__msr [2] } + assign $2\msr[63:0] [63] 1'1 + assign $2\msr[63:0] [15] 1'0 + assign $2\msr[63:0] [14] 1'0 + assign $2\msr[63:0] [5] 1'0 + assign $2\msr[63:0] [4] 1'0 + assign $2\msr[63:0] [1] 1'0 + assign $2\msr[63:0] [0] 1'1 + assign $2\msr[63:0] [11] 1'0 + assign $2\msr[63:0] [8] 1'0 + assign $2\msr[63:0] [23] 1'0 + assign $2\msr[63:0] [32] 1'0 + assign $2\msr[63:0] [25] 1'0 + assign $2\msr[63:0] [13] 1'0 + assign $2\msr[63:0] [3] 1'0 + assign $2\msr[63:0] [10] 1'0 + assign $2\msr[63:0] [9] 1'0 + assign $2\msr[63:0] [58] 1'0 + assign $2\msr_ok[0:0] 1'1 + case + assign $2\msr[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\msr_ok[0:0] 1'0 + end + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'1001000 , 7'1001010 + assign { } { } + assign { } { } + assign $1\msr[63:0] [0] \$59 [0] + assign $1\msr[63:0] [11:1] $3\msr[11:1] + assign $1\msr[63:0] [59:13] $4\msr[59:13] + assign $1\msr[63:0] [63:61] $5\msr[63:61] + assign $1\msr[63:0] [12] $12\msr[12:12] + assign $1\msr[63:0] [60] $13\msr[60:60] + assign $1\msr_ok[0:0] 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:218" + switch \trap_op__insn [21] + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign $3\msr[11:1] [10:1] \$59 [11:2] + assign { $4\msr[59:13] [46:3] $4\msr[59:13] [1:0] } { \$59 [59:16] \$59 [14:13] } + assign $5\msr[63:61] \$59 [63:61] + assign $3\msr[11:1] [0] \ra [1] + assign $4\msr[59:13] [2] \ra [15] + attribute \src "issuer_ls180.v:0.0-0.0" + case + assign { } { } + assign { } { } + assign { } { } + assign { $3\msr[11:1] [10:5] $3\msr[11:1] [2:0] } { $6\msr[11:1] [10:5] $6\msr[11:1] [2:0] } + assign { $4\msr[59:13] [46:3] $4\msr[59:13] [1:0] } { $7\msr[59:13] [46:3] $7\msr[59:13] [1:0] } + assign $5\msr[63:61] $8\msr[63:61] + assign $3\msr[11:1] [4:3] $10\msr[5:4] + assign $4\msr[59:13] [2] $11\msr[15:15] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:225" + switch \$61 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign $6\msr[11:1] \ra [11:1] + assign { $7\msr[59:13] [46:22] $7\msr[59:13] [18:0] } { \ra [59:35] \ra [31:13] } + assign $8\msr[63:61] \ra [63:61] + assign $7\msr[59:13] [21:19] $9\msr[34:32] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:232" + switch \$67 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $9\msr[34:32] \trap_op__msr [34:32] + case + assign $9\msr[34:32] \ra [34:32] + end + attribute \src "issuer_ls180.v:0.0-0.0" + case + assign { } { } + assign $7\msr[59:13] [46:19] \$59 [59:32] + assign $8\msr[63:61] \$59 [63:61] + assign $6\msr[11:1] \ra [11:1] + assign $7\msr[59:13] [18:0] \ra [31:13] + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:48" + switch $7\msr[59:13] [1] + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign $11\msr[15:15] 1'1 + assign $10\msr[5:4] [1] 1'1 + assign $10\msr[5:4] [0] 1'1 + case + assign $10\msr[5:4] $6\msr[11:1] [4:3] + assign $11\msr[15:15] $7\msr[59:13] [2] + end + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:247" + switch \$69 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign $13\msr[60:60] \trap_op__msr [60] + assign $12\msr[12:12] \trap_op__msr [12] + case + assign $12\msr[12:12] \$59 [12] + assign $13\msr[60:60] \$59 [60] + end + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'1000111 + assign $1\msr[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\msr_ok[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'1000110 + assign { $1\msr[63:0] [30:27] $1\msr[63:0] [21:16] } 10'0000000000 + assign { } { } + assign { $1\msr[63:0] [14:13] $1\msr[63:0] [11:6] $1\msr[63:0] [3:0] } { \fast2 [14:13] \fast2 [11:6] \fast2 [3:0] } + assign $1\msr[63:0] [26:22] \fast2 [26:22] + assign { $1\msr[63:0] [63:35] $1\msr[63:0] [31] } { \fast2 [63:35] \fast2 [31] } + assign $1\msr[63:0] [12] $14\msr[12:12] + assign $1\msr[63:0] [5:4] $16\msr[5:4] + assign $1\msr[63:0] [15] $17\msr[15:15] + assign $1\msr[63:0] [34:32] $18\msr[34:32] + assign $1\msr_ok[0:0] 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:273" + switch \$71 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $14\msr[12:12] $15\msr[12:12] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:274" + switch \trap_op__msr [60] + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $15\msr[12:12] \fast2 [12] + attribute \src "issuer_ls180.v:0.0-0.0" + case + assign { } { } + assign $15\msr[12:12] \trap_op__msr [12] + end + case + assign $14\msr[12:12] \fast2 [12] + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:48" + switch \fast2 [14] + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign $17\msr[15:15] 1'1 + assign $16\msr[5:4] [1] 1'1 + assign $16\msr[5:4] [0] 1'1 + case + assign $16\msr[5:4] \fast2 [5:4] + assign $17\msr[15:15] \fast2 [15] + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:287" + switch \$77 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $18\msr[34:32] \trap_op__msr [34:32] + case + assign $18\msr[34:32] \fast2 [34:32] + end + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'1001001 + assign { } { } + assign { } { } + assign { $1\msr[63:0] [62:59] $1\msr[63:0] [57:33] $1\msr[63:0] [31:26] $1\msr[63:0] [24] $1\msr[63:0] [22:16] $1\msr[63:0] [12] $1\msr[63:0] [7:6] $1\msr[63:0] [2] } { \trap_op__msr [62:59] \trap_op__msr [57:33] \trap_op__msr [31:26] \trap_op__msr [24] \trap_op__msr [22:16] \trap_op__msr [12] \trap_op__msr [7:6] \trap_op__msr [2] } + assign $1\msr[63:0] [63] 1'1 + assign $1\msr[63:0] [15] 1'0 + assign $1\msr[63:0] [14] 1'0 + assign $1\msr[63:0] [5] 1'0 + assign $1\msr[63:0] [4] 1'0 + assign $1\msr[63:0] [1] 1'0 + assign $1\msr[63:0] [0] 1'1 + assign $1\msr[63:0] [11] 1'0 + assign $1\msr[63:0] [8] 1'0 + assign $1\msr[63:0] [23] 1'0 + assign $1\msr[63:0] [32] 1'0 + assign $1\msr[63:0] [25] 1'0 + assign $1\msr[63:0] [13] 1'0 + assign $1\msr[63:0] [3] 1'0 + assign $1\msr[63:0] [10] 1'0 + assign $1\msr[63:0] [9] 1'0 + assign $1\msr[63:0] [58] 1'0 + assign $1\msr_ok[0:0] 1'1 + case + assign $1\msr[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\msr_ok[0:0] 1'0 + end + sync always + update \msr $0\msr[63:0] + update \msr_ok $0\msr_ok[0:0] + end + attribute \src "issuer_ls180.v:133814.3-133825.6" + process $proc$issuer_ls180.v:133814$6443 + assign { } { } + assign $0\b_s[63:0] $1\b_s[63:0] + attribute \src "issuer_ls180.v:133815.5-133815.29" + switch \initial + attribute \src "issuer_ls180.v:133815.9-133815.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:144" + switch \trap_op__is_32bit + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\b_s[63:0] { \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31] \rb [31:0] } + attribute \src "issuer_ls180.v:0.0-0.0" + case + assign { } { } + assign $1\b_s[63:0] \rb + end + sync always + update \b_s $0\b_s[63:0] + end + attribute \src "issuer_ls180.v:133826.3-133844.6" + process $proc$issuer_ls180.v:133826$6444 + assign { } { } + assign { } { } + assign $0\o[63:0] $1\o[63:0] + attribute \src "issuer_ls180.v:133827.5-133827.29" + switch \initial + attribute \src "issuer_ls180.v:133827.9-133827.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:179" + switch \trap_op__insn_type + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'0111111 + assign $1\o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'1001000 , 7'1001010 + assign $1\o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'1000111 + assign { } { } + assign $1\o[63:0] \trap_op__msr + case + assign $1\o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \o $0\o[63:0] + end + attribute \src "issuer_ls180.v:133845.3-133863.6" + process $proc$issuer_ls180.v:133845$6445 + assign { } { } + assign { } { } + assign $0\o_ok[0:0] $1\o_ok[0:0] + attribute \src "issuer_ls180.v:133846.5-133846.29" + switch \initial + attribute \src "issuer_ls180.v:133846.9-133846.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:179" + switch \trap_op__insn_type + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'0111111 + assign $1\o_ok[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'1001000 , 7'1001010 + assign $1\o_ok[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'1000111 + assign { } { } + assign $1\o_ok[0:0] 1'1 + case + assign $1\o_ok[0:0] 1'0 + end + sync always + update \o_ok $0\o_ok[0:0] + end + attribute \src "issuer_ls180.v:133864.3-133875.6" + process $proc$issuer_ls180.v:133864$6446 + assign { } { } + assign $0\a[63:0] $1\a[63:0] + attribute \src "issuer_ls180.v:133865.5-133865.29" + switch \initial + attribute \src "issuer_ls180.v:133865.9-133865.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:144" + switch \trap_op__is_32bit + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\a[63:0] \$12 + attribute \src "issuer_ls180.v:0.0-0.0" + case + assign { } { } + assign $1\a[63:0] \ra + end + sync always + update \a $0\a[63:0] + end + attribute \src "issuer_ls180.v:133876.3-133887.6" + process $proc$issuer_ls180.v:133876$6447 + assign { } { } + assign $0\b[63:0] $1\b[63:0] + attribute \src "issuer_ls180.v:133877.5-133877.29" + switch \initial + attribute \src "issuer_ls180.v:133877.9-133877.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:144" + switch \trap_op__is_32bit + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\b[63:0] \$14 + attribute \src "issuer_ls180.v:0.0-0.0" + case + assign { } { } + assign $1\b[63:0] \rb + end + sync always + update \b $0\b[63:0] + end + connect \$12 $pos$issuer_ls180.v:133368$6388_Y + connect \$14 $pos$issuer_ls180.v:133369$6390_Y + connect \$16 $lt$issuer_ls180.v:133370$6391_Y + connect \$18 $gt$issuer_ls180.v:133371$6392_Y + connect \$20 $lt$issuer_ls180.v:133372$6393_Y + connect \$22 $gt$issuer_ls180.v:133373$6394_Y + connect \$24 $eq$issuer_ls180.v:133374$6395_Y + connect \$27 $and$issuer_ls180.v:133375$6396_Y + connect \$26 $reduce_or$issuer_ls180.v:133376$6397_Y + connect \$30 $reduce_or$issuer_ls180.v:133377$6398_Y + connect \$32 $or$issuer_ls180.v:133378$6399_Y + connect \$35 $sshl$issuer_ls180.v:133379$6400_Y + connect \$34 $pos$issuer_ls180.v:133380$6402_Y + connect \$39 $add$issuer_ls180.v:133381$6403_Y + connect \$41 $eq$issuer_ls180.v:133382$6404_Y + connect \$44 $and$issuer_ls180.v:133383$6405_Y + connect \$43 $reduce_or$issuer_ls180.v:133384$6406_Y + connect \$48 $and$issuer_ls180.v:133385$6407_Y + connect \$47 $reduce_or$issuer_ls180.v:133386$6408_Y + connect \$52 $and$issuer_ls180.v:133387$6409_Y + connect \$51 $reduce_or$issuer_ls180.v:133388$6410_Y + connect \$56 $and$issuer_ls180.v:133389$6411_Y + connect \$55 $reduce_or$issuer_ls180.v:133390$6412_Y + connect \$59 $pos$issuer_ls180.v:133391$6414_Y + connect \$61 $eq$issuer_ls180.v:133392$6415_Y + connect \$63 $eq$issuer_ls180.v:133393$6416_Y + connect \$65 $eq$issuer_ls180.v:133394$6417_Y + connect \$67 $and$issuer_ls180.v:133395$6418_Y + connect \$69 $not$issuer_ls180.v:133396$6419_Y + connect \$71 $not$issuer_ls180.v:133397$6420_Y + connect \$73 $eq$issuer_ls180.v:133398$6421_Y + connect \$75 $eq$issuer_ls180.v:133399$6422_Y + connect \$77 $and$issuer_ls180.v:133400$6423_Y + connect \$38 \$39 + connect { \trap_op__trapaddr$9 \trap_op__traptype$8 \trap_op__is_32bit$7 \trap_op__cia$6 \trap_op__msr$5 \trap_op__insn$4 \trap_op__fn_unit$3 \trap_op__insn_type$2 } { \trap_op__trapaddr \trap_op__traptype \trap_op__is_32bit \trap_op__cia \trap_op__msr \trap_op__insn \trap_op__fn_unit \trap_op__insn_type } + connect \muxid$1 \muxid + connect \should_trap \$32 + connect \trap_bits { \lt_s \gt_s \equal \lt_u \gt_u } + connect \equal \$24 + connect \gt_u \$22 + connect \lt_u \$20 + connect \gt_s \$18 + connect \lt_s \$16 + connect \to \trap_op__insn [25:21] +end +attribute \src "issuer_ls180.v:133903.1-134646.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.fus.logical0.alu_logical0.logical_pipe1.main" +attribute \generator "nMigen" +module \main$48 + attribute \src "issuer_ls180.v:134613.3-134623.6" + wire width 32 $0\a32[31:0] + attribute \src "issuer_ls180.v:134558.3-134568.6" + wire width 64 $0\b[63:0] + attribute \src "issuer_ls180.v:134536.3-134546.6" + wire width 64 $0\bpermd_rb[63:0] + attribute \src "issuer_ls180.v:134525.3-134535.6" + wire width 64 $0\bpermd_rs[63:0] + attribute \src "issuer_ls180.v:134514.3-134524.6" + wire width 64 $0\clz_sig_in[63:0] + attribute \src "issuer_ls180.v:134624.3-134642.6" + wire width 64 $0\cntz_i[63:0] + attribute \src "issuer_ls180.v:134602.3-134612.6" + wire $0\count_right[0:0] + attribute \src "issuer_ls180.v:133904.7-133904.20" + wire $0\initial[0:0] + attribute \src "issuer_ls180.v:134459.3-134513.6" + wire width 64 $0\o[63:0] + attribute \src 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"/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:103" + wire width 32 \a32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:28" + wire width 64 \b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:55" + wire width 64 \bpermd_ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:56" + wire width 64 \bpermd_rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:54" + wire width 64 \bpermd_rs + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:13" + wire width 7 \clz_lz + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:11" + wire width 64 \clz_sig_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:102" + wire width 64 \cntz_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:99" + wire \count_right + attribute \src "issuer_ls180.v:133904.7-133904.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 input 17 \logical_op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 output 39 \logical_op__data_len$18 + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 input 2 \logical_op__fn_unit + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 output 24 \logical_op__fn_unit$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 input 3 \logical_op__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 output 25 \logical_op__imm_data__data$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 4 \logical_op__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 26 \logical_op__imm_data__ok$5 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 input 11 \logical_op__input_carry + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 output 33 \logical_op__input_carry$12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 18 \logical_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 output 40 \logical_op__insn$19 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 input 1 \logical_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 output 23 \logical_op__insn_type$2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 9 \logical_op__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 31 \logical_op__invert_in$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 12 \logical_op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 34 \logical_op__invert_out$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 15 \logical_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 37 \logical_op__is_32bit$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 16 \logical_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 38 \logical_op__is_signed$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 7 \logical_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 29 \logical_op__oe__oe$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 8 \logical_op__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 30 \logical_op__oe__ok$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 14 \logical_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 36 \logical_op__output_carry$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 6 \logical_op__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 28 \logical_op__rc__ok$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 5 \logical_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 27 \logical_op__rc__rc$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 13 \logical_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 35 \logical_op__write_cr0$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 10 \logical_op__zero_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 32 \logical_op__zero_a$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 input 44 \muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 output 22 \muxid$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 output 41 \o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 42 \o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:84" + wire \par0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:85" + wire \par1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:27" + wire width 64 \popcount_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:29" + wire width 64 \popcount_data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:30" + wire width 64 \popcount_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 19 \ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 20 \rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire input 21 \xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 43 \xer_so$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:54" + cell $and $and$issuer_ls180.v:134406$6495 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A \ra + connect \B \rb + connect \Y $and$issuer_ls180.v:134406$6495_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + cell $eq $eq$issuer_ls180.v:134365$6449 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \ra [39:32] + connect \B \rb [39:32] + connect \Y $eq$issuer_ls180.v:134365$6449_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + cell $eq $eq$issuer_ls180.v:134366$6450 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \ra [39:32] + connect \B \rb [39:32] + connect \Y $eq$issuer_ls180.v:134366$6450_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + cell $eq $eq$issuer_ls180.v:134367$6451 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \ra [39:32] + connect \B \rb [39:32] + connect \Y $eq$issuer_ls180.v:134367$6451_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + cell $eq $eq$issuer_ls180.v:134368$6452 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \ra [39:32] + connect \B \rb [39:32] + connect \Y $eq$issuer_ls180.v:134368$6452_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + cell $eq $eq$issuer_ls180.v:134369$6453 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \ra [47:40] + connect \B \rb [47:40] + connect \Y $eq$issuer_ls180.v:134369$6453_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + cell $eq $eq$issuer_ls180.v:134370$6454 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter 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parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \ra [23:16] + connect \B \rb [23:16] + connect \Y $eq$issuer_ls180.v:134431$6520_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + cell $eq $eq$issuer_ls180.v:134432$6521 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \ra [23:16] + connect \B \rb [23:16] + connect \Y $eq$issuer_ls180.v:134432$6521_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + cell $eq $eq$issuer_ls180.v:134433$6522 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \ra [31:24] + connect \B \rb [31:24] + connect \Y $eq$issuer_ls180.v:134433$6522_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + cell $eq $eq$issuer_ls180.v:134434$6523 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \ra [31:24] + connect \B \rb [31:24] + connect \Y $eq$issuer_ls180.v:134434$6523_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + cell $eq $eq$issuer_ls180.v:134435$6524 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \ra [31:24] + connect \B \rb [31:24] + connect \Y $eq$issuer_ls180.v:134435$6524_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + cell $eq $eq$issuer_ls180.v:134436$6525 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \ra [31:24] + connect \B \rb [31:24] + connect \Y $eq$issuer_ls180.v:134436$6525_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + cell $eq $eq$issuer_ls180.v:134437$6526 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \ra [31:24] + connect \B \rb [31:24] + connect \Y $eq$issuer_ls180.v:134437$6526_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + cell $eq $eq$issuer_ls180.v:134438$6527 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \ra [31:24] + connect \B \rb [31:24] + connect \Y $eq$issuer_ls180.v:134438$6527_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + cell $eq $eq$issuer_ls180.v:134439$6528 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \ra [31:24] + connect \B \rb [31:24] + connect \Y $eq$issuer_ls180.v:134439$6528_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + cell $eq $eq$issuer_ls180.v:134440$6529 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \ra [31:24] + connect \B \rb [31:24] + connect \Y $eq$issuer_ls180.v:134440$6529_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + cell $eq $eq$issuer_ls180.v:134441$6530 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \ra [39:32] + connect \B \rb [39:32] + connect \Y $eq$issuer_ls180.v:134441$6530_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + cell $eq $eq$issuer_ls180.v:134442$6531 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \ra [39:32] + connect \B \rb [39:32] + connect \Y $eq$issuer_ls180.v:134442$6531_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + cell $eq $eq$issuer_ls180.v:134443$6532 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \ra [39:32] + connect \B \rb [39:32] + connect \Y $eq$issuer_ls180.v:134443$6532_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" + cell $eq $eq$issuer_ls180.v:134444$6533 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \ra [39:32] + connect \B \rb [39:32] + connect \Y $eq$issuer_ls180.v:134444$6533_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:89" + cell $pos $extend$issuer_ls180.v:134395$6479 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 64 + connect \A \$158 + connect \Y $extend$issuer_ls180.v:134395$6479_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:13" + cell $pos $extend$issuer_ls180.v:134397$6482 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \Y_WIDTH 8 + connect \A \clz_lz + connect \Y $extend$issuer_ls180.v:134397$6482_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:113" + cell $pos $extend$issuer_ls180.v:134399$6485 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 64 + connect \A \$166 + connect \Y $extend$issuer_ls180.v:134399$6485_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + cell $pos $extend$issuer_ls180.v:134400$6487 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 64 + connect \A \logical_op__data_len + connect \Y $extend$issuer_ls180.v:134400$6487_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:107" + cell $pos $extend$issuer_ls180.v:134404$6492 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \Y_WIDTH 64 + connect \A \$176 + connect \Y $extend$issuer_ls180.v:134404$6492_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:56" + cell $or $or$issuer_ls180.v:134407$6496 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A \ra + connect \B \rb + connect \Y $or$issuer_ls180.v:134407$6496_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:89" + cell $pos $pos$issuer_ls180.v:134395$6480 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A $extend$issuer_ls180.v:134395$6479_Y + connect \Y $pos$issuer_ls180.v:134395$6480_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:13" + cell $pos $pos$issuer_ls180.v:134397$6483 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 8 + connect \A $extend$issuer_ls180.v:134397$6482_Y + connect \Y $pos$issuer_ls180.v:134397$6483_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:113" + cell $pos $pos$issuer_ls180.v:134399$6486 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A $extend$issuer_ls180.v:134399$6485_Y + connect \Y $pos$issuer_ls180.v:134399$6486_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + cell $pos $pos$issuer_ls180.v:134400$6488 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A $extend$issuer_ls180.v:134400$6487_Y + connect \Y $pos$issuer_ls180.v:134400$6488_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:107" + cell $pos $pos$issuer_ls180.v:134404$6493 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A $extend$issuer_ls180.v:134404$6492_Y + connect \Y $pos$issuer_ls180.v:134404$6493_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:86" + cell $reduce_xor $reduce_xor$issuer_ls180.v:134401$6489 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A { \ra [24] \ra [16] \ra [8] \ra [0] } + connect \Y $reduce_xor$issuer_ls180.v:134401$6489_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:87" + cell $reduce_xor $reduce_xor$issuer_ls180.v:134402$6490 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A { \ra [56] \ra [48] \ra [40] \ra [32] } + connect \Y $reduce_xor$issuer_ls180.v:134402$6490_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:113" + cell $sub $sub$issuer_ls180.v:134396$6481 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 8 + connect \A \clz_lz + connect \B 6'100000 + connect \Y $sub$issuer_ls180.v:134396$6481_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:113" + cell $mux $ternary$issuer_ls180.v:134398$6484 + parameter \WIDTH 8 + connect \A \$164 + connect \B \$162 + connect \S \logical_op__is_32bit + connect \Y $ternary$issuer_ls180.v:134398$6484_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:107" + cell $mux $ternary$issuer_ls180.v:134403$6491 + parameter \WIDTH 32 + connect \A \a32 + connect \B { \a32 [0] \a32 [1] \a32 [2] \a32 [3] \a32 [4] \a32 [5] \a32 [6] \a32 [7] \a32 [8] \a32 [9] \a32 [10] \a32 [11] \a32 [12] \a32 [13] \a32 [14] \a32 [15] \a32 [16] \a32 [17] \a32 [18] \a32 [19] \a32 [20] \a32 [21] \a32 [22] \a32 [23] \a32 [24] \a32 [25] \a32 [26] \a32 [27] \a32 [28] \a32 [29] \a32 [30] \a32 [31] } + connect \S \count_right + connect \Y $ternary$issuer_ls180.v:134403$6491_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:109" + cell $mux $ternary$issuer_ls180.v:134405$6494 + parameter \WIDTH 64 + connect \A \ra + connect \B { \ra [0] \ra [1] \ra [2] \ra [3] \ra [4] \ra [5] \ra [6] \ra [7] \ra [8] \ra [9] \ra [10] \ra [11] \ra [12] \ra [13] \ra [14] \ra [15] \ra [16] \ra [17] \ra [18] \ra [19] \ra [20] \ra [21] \ra [22] \ra [23] \ra [24] \ra [25] \ra [26] \ra [27] \ra [28] \ra [29] \ra [30] \ra [31] \ra [32] \ra [33] \ra [34] \ra [35] \ra [36] \ra [37] \ra [38] \ra [39] \ra [40] \ra [41] \ra [42] \ra [43] \ra [44] \ra [45] \ra [46] \ra [47] \ra [48] \ra [49] \ra [50] \ra [51] \ra [52] \ra [53] \ra [54] \ra [55] \ra [56] \ra [57] \ra [58] \ra [59] \ra [60] \ra [61] \ra [62] \ra [63] } + connect \S \count_right + connect \Y $ternary$issuer_ls180.v:134405$6494_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:89" + cell $xor $xor$issuer_ls180.v:134394$6478 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \par0 + connect \B \par1 + connect \Y $xor$issuer_ls180.v:134394$6478_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:58" + cell $xor $xor$issuer_ls180.v:134408$6497 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A \ra + connect \B \rb + connect \Y $xor$issuer_ls180.v:134408$6497_Y + end + attribute \module_not_derived 1 + attribute \src "issuer_ls180.v:134445.10-134449.4" + cell \bpermd \bpermd + connect \ra \bpermd_ra + connect \rb \bpermd_rb + connect \rs \bpermd_rs + end + attribute \module_not_derived 1 + attribute \src "issuer_ls180.v:134450.7-134453.4" + cell \clz \clz + connect \lz \clz_lz + connect \sig_in \clz_sig_in + end + attribute \module_not_derived 1 + attribute \src "issuer_ls180.v:134454.12-134458.4" + cell \popcount \popcount + connect \a \popcount_a + connect \data_len \popcount_data_len + connect \o \popcount_o + end + attribute \src "issuer_ls180.v:133904.7-133904.20" + process $proc$issuer_ls180.v:133904$6546 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "issuer_ls180.v:134459.3-134513.6" + process $proc$issuer_ls180.v:134459$6534 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\o_ok[0:0] $1\o_ok[0:0] + assign $0\o[63:0] $1\o[63:0] + attribute \src "issuer_ls180.v:134460.5-134460.29" + switch \initial + attribute \src "issuer_ls180.v:134460.9-134460.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:48" + switch \logical_op__insn_type + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'0000100 + assign $1\o_ok[0:0] 1'1 + assign { } { } + assign $1\o[63:0] \$21 + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'0110101 + assign $1\o_ok[0:0] 1'1 + assign { } { } + assign $1\o[63:0] \$23 + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'1000011 + assign $1\o_ok[0:0] 1'1 + assign { } { } + assign $1\o[63:0] \$25 + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'0001011 + assign $1\o_ok[0:0] 1'1 + assign { } { } + assign $1\o[63:0] { \$139 \$141 \$143 \$145 \$147 \$149 \$151 \$153 \$123 \$125 \$127 \$129 \$131 \$133 \$135 \$137 \$107 \$109 \$111 \$113 \$115 \$117 \$119 \$121 \$91 \$93 \$95 \$97 \$99 \$101 \$103 \$105 \$75 \$77 \$79 \$81 \$83 \$85 \$87 \$89 \$59 \$61 \$63 \$65 \$67 \$69 \$71 \$73 \$43 \$45 \$47 \$49 \$51 \$53 \$55 \$57 \$27 \$29 \$31 \$33 \$35 \$37 \$39 \$41 } + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'0110110 + assign $1\o_ok[0:0] 1'1 + assign { } { } + assign $1\o[63:0] \popcount_o + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'0110111 + assign $1\o_ok[0:0] 1'1 + assign { } { } + assign $1\o[63:0] $2\o[63:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:88" + switch \$155 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\o[63:0] \$157 + attribute \src "issuer_ls180.v:0.0-0.0" + case + assign { $2\o[63:0] [63:33] $2\o[63:0] [31:1] } 62'00000000000000000000000000000000000000000000000000000000000000 + assign $2\o[63:0] [0] \par0 + assign $2\o[63:0] [32] \par1 + end + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'0001110 + assign $1\o_ok[0:0] 1'1 + assign { } { } + assign $1\o[63:0] \$161 + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'0001001 + assign $1\o_ok[0:0] 1'1 + assign { } { } + assign $1\o[63:0] \bpermd_ra + attribute \src "issuer_ls180.v:0.0-0.0" + case + assign { } { } + assign $1\o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\o_ok[0:0] 1'0 + end + sync always + update \o_ok $0\o_ok[0:0] + update \o $0\o[63:0] + end + attribute \src "issuer_ls180.v:134514.3-134524.6" + process $proc$issuer_ls180.v:134514$6535 + assign { } { } + assign { } { } + assign $0\clz_sig_in[63:0] $1\clz_sig_in[63:0] + attribute \src "issuer_ls180.v:134515.5-134515.29" + switch \initial + attribute \src "issuer_ls180.v:134515.9-134515.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:48" + switch \logical_op__insn_type + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'0001110 + assign { } { } + assign $1\clz_sig_in[63:0] \cntz_i + case + assign $1\clz_sig_in[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \clz_sig_in $0\clz_sig_in[63:0] + end + attribute \src "issuer_ls180.v:134525.3-134535.6" + process $proc$issuer_ls180.v:134525$6536 + assign { } { } + assign { } { } + assign $0\bpermd_rs[63:0] $1\bpermd_rs[63:0] + attribute \src "issuer_ls180.v:134526.5-134526.29" + switch \initial + attribute \src "issuer_ls180.v:134526.9-134526.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:48" + switch \logical_op__insn_type + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'0001001 + assign { } { } + assign $1\bpermd_rs[63:0] \ra + case + assign $1\bpermd_rs[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \bpermd_rs $0\bpermd_rs[63:0] + end + attribute \src "issuer_ls180.v:134536.3-134546.6" + process $proc$issuer_ls180.v:134536$6537 + assign { } { } + assign { } { } + assign $0\bpermd_rb[63:0] $1\bpermd_rb[63:0] + attribute \src "issuer_ls180.v:134537.5-134537.29" + switch \initial + attribute \src "issuer_ls180.v:134537.9-134537.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:48" + switch \logical_op__insn_type + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'0001001 + assign { } { } + assign $1\bpermd_rb[63:0] \rb + case + assign $1\bpermd_rb[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \bpermd_rb $0\bpermd_rb[63:0] + end + attribute \src "issuer_ls180.v:134547.3-134557.6" + process $proc$issuer_ls180.v:134547$6538 + assign { } { } + assign { } { } + assign $0\popcount_a[63:0] $1\popcount_a[63:0] + attribute \src "issuer_ls180.v:134548.5-134548.29" + switch \initial + attribute \src "issuer_ls180.v:134548.9-134548.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:48" + switch \logical_op__insn_type + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'0110110 + assign { } { } + assign $1\popcount_a[63:0] \ra + case + assign $1\popcount_a[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \popcount_a $0\popcount_a[63:0] + end + attribute \src "issuer_ls180.v:134558.3-134568.6" + process $proc$issuer_ls180.v:134558$6539 + assign { } { } + assign { } { } + assign $0\b[63:0] $1\b[63:0] + attribute \src "issuer_ls180.v:134559.5-134559.29" + switch \initial + attribute \src "issuer_ls180.v:134559.9-134559.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:48" + switch \logical_op__insn_type + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'0110110 + assign { } { } + assign $1\b[63:0] \rb + case + assign $1\b[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \b $0\b[63:0] + end + attribute \src "issuer_ls180.v:134569.3-134579.6" + process $proc$issuer_ls180.v:134569$6540 + assign { } { } + assign { } { } + assign $0\popcount_data_len[63:0] $1\popcount_data_len[63:0] + attribute \src "issuer_ls180.v:134570.5-134570.29" + switch \initial + attribute \src "issuer_ls180.v:134570.9-134570.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:48" + switch \logical_op__insn_type + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'0110110 + assign { } { } + assign $1\popcount_data_len[63:0] \$169 + case + assign $1\popcount_data_len[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \popcount_data_len $0\popcount_data_len[63:0] + end + attribute \src "issuer_ls180.v:134580.3-134590.6" + process $proc$issuer_ls180.v:134580$6541 + assign { } { } + assign { } { } + assign $0\par0[0:0] $1\par0[0:0] + attribute \src "issuer_ls180.v:134581.5-134581.29" + switch \initial + attribute \src "issuer_ls180.v:134581.9-134581.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:48" + switch \logical_op__insn_type + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'0110111 + assign { } { } + assign $1\par0[0:0] \$171 + case + assign $1\par0[0:0] 1'0 + end + sync always + update \par0 $0\par0[0:0] + end + attribute \src "issuer_ls180.v:134591.3-134601.6" + process $proc$issuer_ls180.v:134591$6542 + assign { } { } + assign { } { } + assign $0\par1[0:0] $1\par1[0:0] + attribute \src "issuer_ls180.v:134592.5-134592.29" + switch \initial + attribute \src "issuer_ls180.v:134592.9-134592.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:48" + switch \logical_op__insn_type + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'0110111 + assign { } { } + assign $1\par1[0:0] \$173 + case + assign $1\par1[0:0] 1'0 + end + sync always + update \par1 $0\par1[0:0] + end + attribute \src "issuer_ls180.v:134602.3-134612.6" + process $proc$issuer_ls180.v:134602$6543 + assign { } { } + assign { } { } + assign $0\count_right[0:0] $1\count_right[0:0] + attribute \src "issuer_ls180.v:134603.5-134603.29" + switch \initial + attribute \src "issuer_ls180.v:134603.9-134603.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:48" + switch \logical_op__insn_type + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'0001110 + assign { } { } + assign $1\count_right[0:0] \logical_op__insn [10] + case + assign $1\count_right[0:0] 1'0 + end + sync always + update \count_right $0\count_right[0:0] + end + attribute \src "issuer_ls180.v:134613.3-134623.6" + process $proc$issuer_ls180.v:134613$6544 + assign { } { } + assign { } { } + assign $0\a32[31:0] $1\a32[31:0] + attribute \src "issuer_ls180.v:134614.5-134614.29" + switch \initial + attribute \src "issuer_ls180.v:134614.9-134614.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:48" + switch \logical_op__insn_type + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'0001110 + assign { } { } + assign $1\a32[31:0] \ra [31:0] + case + assign $1\a32[31:0] 0 + end + sync always + update \a32 $0\a32[31:0] + end + attribute \src "issuer_ls180.v:134624.3-134642.6" + process $proc$issuer_ls180.v:134624$6545 + assign { } { } + assign { } { } + assign $0\cntz_i[63:0] $1\cntz_i[63:0] + attribute \src "issuer_ls180.v:134625.5-134625.29" + switch \initial + attribute \src "issuer_ls180.v:134625.9-134625.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:48" + switch \logical_op__insn_type + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'0001110 + assign { } { } + assign $1\cntz_i[63:0] $2\cntz_i[63:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:106" + switch \logical_op__is_32bit + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\cntz_i[63:0] \$175 + attribute \src "issuer_ls180.v:0.0-0.0" + case + assign { } { } + assign $2\cntz_i[63:0] \$179 + end + case + assign $1\cntz_i[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \cntz_i $0\cntz_i[63:0] + end + connect \$99 $eq$issuer_ls180.v:134365$6449_Y + connect \$101 $eq$issuer_ls180.v:134366$6450_Y + connect \$103 $eq$issuer_ls180.v:134367$6451_Y + connect \$105 $eq$issuer_ls180.v:134368$6452_Y + connect \$107 $eq$issuer_ls180.v:134369$6453_Y + connect \$109 $eq$issuer_ls180.v:134370$6454_Y + connect \$111 $eq$issuer_ls180.v:134371$6455_Y + connect \$113 $eq$issuer_ls180.v:134372$6456_Y + connect \$115 $eq$issuer_ls180.v:134373$6457_Y + connect \$117 $eq$issuer_ls180.v:134374$6458_Y + connect \$119 $eq$issuer_ls180.v:134375$6459_Y + connect \$121 $eq$issuer_ls180.v:134376$6460_Y + connect \$123 $eq$issuer_ls180.v:134377$6461_Y + connect \$125 $eq$issuer_ls180.v:134378$6462_Y + connect \$127 $eq$issuer_ls180.v:134379$6463_Y + connect \$129 $eq$issuer_ls180.v:134380$6464_Y + connect \$131 $eq$issuer_ls180.v:134381$6465_Y + connect \$133 $eq$issuer_ls180.v:134382$6466_Y + connect \$135 $eq$issuer_ls180.v:134383$6467_Y + connect \$137 $eq$issuer_ls180.v:134384$6468_Y + connect \$139 $eq$issuer_ls180.v:134385$6469_Y + connect \$141 $eq$issuer_ls180.v:134386$6470_Y + connect \$143 $eq$issuer_ls180.v:134387$6471_Y + connect \$145 $eq$issuer_ls180.v:134388$6472_Y + connect \$147 $eq$issuer_ls180.v:134389$6473_Y + connect \$149 $eq$issuer_ls180.v:134390$6474_Y + connect \$151 $eq$issuer_ls180.v:134391$6475_Y + connect \$153 $eq$issuer_ls180.v:134392$6476_Y + connect \$155 $eq$issuer_ls180.v:134393$6477_Y + connect \$158 $xor$issuer_ls180.v:134394$6478_Y + connect \$157 $pos$issuer_ls180.v:134395$6480_Y + connect \$162 $sub$issuer_ls180.v:134396$6481_Y + connect \$164 $pos$issuer_ls180.v:134397$6483_Y + connect \$166 $ternary$issuer_ls180.v:134398$6484_Y + connect \$161 $pos$issuer_ls180.v:134399$6486_Y + connect \$169 $pos$issuer_ls180.v:134400$6488_Y + connect \$171 $reduce_xor$issuer_ls180.v:134401$6489_Y + connect \$173 $reduce_xor$issuer_ls180.v:134402$6490_Y + connect \$176 $ternary$issuer_ls180.v:134403$6491_Y + connect \$175 $pos$issuer_ls180.v:134404$6493_Y + connect \$179 $ternary$issuer_ls180.v:134405$6494_Y + connect \$21 $and$issuer_ls180.v:134406$6495_Y + connect \$23 $or$issuer_ls180.v:134407$6496_Y + connect \$25 $xor$issuer_ls180.v:134408$6497_Y + connect \$27 $eq$issuer_ls180.v:134409$6498_Y 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$eq$issuer_ls180.v:134430$6519_Y + connect \$71 $eq$issuer_ls180.v:134431$6520_Y + connect \$73 $eq$issuer_ls180.v:134432$6521_Y + connect \$75 $eq$issuer_ls180.v:134433$6522_Y + connect \$77 $eq$issuer_ls180.v:134434$6523_Y + connect \$79 $eq$issuer_ls180.v:134435$6524_Y + connect \$81 $eq$issuer_ls180.v:134436$6525_Y + connect \$83 $eq$issuer_ls180.v:134437$6526_Y + connect \$85 $eq$issuer_ls180.v:134438$6527_Y + connect \$87 $eq$issuer_ls180.v:134439$6528_Y + connect \$89 $eq$issuer_ls180.v:134440$6529_Y + connect \$91 $eq$issuer_ls180.v:134441$6530_Y + connect \$93 $eq$issuer_ls180.v:134442$6531_Y + connect \$95 $eq$issuer_ls180.v:134443$6532_Y + connect \$97 $eq$issuer_ls180.v:134444$6533_Y + connect { \logical_op__insn$19 \logical_op__data_len$18 \logical_op__is_signed$17 \logical_op__is_32bit$16 \logical_op__output_carry$15 \logical_op__write_cr0$14 \logical_op__invert_out$13 \logical_op__input_carry$12 \logical_op__zero_a$11 \logical_op__invert_in$10 \logical_op__oe__ok$9 \logical_op__oe__oe$8 \logical_op__rc__ok$7 \logical_op__rc__rc$6 \logical_op__imm_data__ok$5 \logical_op__imm_data__data$4 \logical_op__fn_unit$3 \logical_op__insn_type$2 } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in \logical_op__oe__ok \logical_op__oe__oe \logical_op__rc__ok \logical_op__rc__rc \logical_op__imm_data__ok \logical_op__imm_data__data \logical_op__fn_unit \logical_op__insn_type } + connect \muxid$1 \muxid + connect \xer_so$20 \xer_so +end +attribute \src "issuer_ls180.v:134650.1-135159.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.fus.cr0.alu_cr0.pipe.main" +attribute \generator "nMigen" +module \main$9 + attribute \src "issuer_ls180.v:135014.3-135024.6" + wire width 2 $0\BC[1:0] + attribute \src "issuer_ls180.v:135068.3-135078.6" + wire width 2 $0\ba[1:0] + attribute \src "issuer_ls180.v:135079.3-135089.6" + wire width 2 $0\bb[1:0] + attribute \src "issuer_ls180.v:135090.3-135110.6" + wire $0\bit_a[0:0] + attribute \src "issuer_ls180.v:135111.3-135131.6" + wire $0\bit_b[0:0] + attribute \src "issuer_ls180.v:135132.3-135142.6" + wire $0\bit_o[0:0] + attribute \src "issuer_ls180.v:135057.3-135067.6" + wire width 2 $0\bt[1:0] + attribute \src "issuer_ls180.v:134926.3-134960.6" + wire width 4 $0\cr_a$6[3:0]$6561 + attribute \src "issuer_ls180.v:134926.3-134960.6" + wire $0\cr_a_ok[0:0] + attribute \src "issuer_ls180.v:135025.3-135045.6" + wire $0\cr_bit[0:0] + attribute \src "issuer_ls180.v:135143.3-135153.6" + wire width 32 $0\full_cr$5[31:0]$6576 + attribute \src "issuer_ls180.v:134961.3-134971.6" + wire $0\full_cr_ok[0:0] + attribute \src "issuer_ls180.v:134651.7-134651.20" + wire $0\initial[0:0] + attribute \src "issuer_ls180.v:135046.3-135056.6" + wire width 4 $0\lut[3:0] + attribute \src "issuer_ls180.v:134972.3-135013.6" + wire width 64 $0\o[63:0] + attribute \src "issuer_ls180.v:134972.3-135013.6" + wire $0\o_ok[0:0] + attribute \src "issuer_ls180.v:135014.3-135024.6" + wire width 2 $1\BC[1:0] + attribute \src "issuer_ls180.v:135068.3-135078.6" + wire width 2 $1\ba[1:0] + attribute \src "issuer_ls180.v:135079.3-135089.6" + wire width 2 $1\bb[1:0] + attribute \src "issuer_ls180.v:135090.3-135110.6" + wire $1\bit_a[0:0] + attribute \src "issuer_ls180.v:135111.3-135131.6" + wire $1\bit_b[0:0] + attribute \src "issuer_ls180.v:135132.3-135142.6" + wire $1\bit_o[0:0] + attribute \src "issuer_ls180.v:135057.3-135067.6" + wire width 2 $1\bt[1:0] + attribute \src "issuer_ls180.v:134926.3-134960.6" + wire width 4 $1\cr_a$6[3:0]$6562 + attribute \src "issuer_ls180.v:134926.3-134960.6" + wire $1\cr_a_ok[0:0] + attribute \src "issuer_ls180.v:135025.3-135045.6" + wire $1\cr_bit[0:0] + attribute \src "issuer_ls180.v:135143.3-135153.6" + wire width 32 $1\full_cr$5[31:0]$6577 + attribute \src "issuer_ls180.v:134961.3-134971.6" + wire $1\full_cr_ok[0:0] + attribute \src "issuer_ls180.v:135046.3-135056.6" + wire width 4 $1\lut[3:0] + attribute \src "issuer_ls180.v:134972.3-135013.6" + wire width 64 $1\o[63:0] + attribute \src "issuer_ls180.v:134972.3-135013.6" + wire $1\o_ok[0:0] + attribute \src "issuer_ls180.v:135090.3-135110.6" + wire $2\bit_a[0:0] + attribute \src "issuer_ls180.v:135111.3-135131.6" + wire $2\bit_b[0:0] + attribute \src "issuer_ls180.v:134926.3-134960.6" + wire width 4 $2\cr_a$6[3:0]$6563 + attribute \src "issuer_ls180.v:135025.3-135045.6" + wire $2\cr_bit[0:0] + attribute \src "issuer_ls180.v:134972.3-135013.6" + wire width 64 $2\o[63:0] + attribute \src "issuer_ls180.v:134922.18-134922.96" + wire width 64 $extend$issuer_ls180.v:134922$6553_Y + attribute \src "issuer_ls180.v:134924.18-134924.98" + wire width 65 $extend$issuer_ls180.v:134924$6556_Y + attribute \src "issuer_ls180.v:134925.17-134925.92" + wire width 5 $extend$issuer_ls180.v:134925$6558_Y + attribute \src "issuer_ls180.v:134922.18-134922.96" + wire width 64 $pos$issuer_ls180.v:134922$6554_Y + attribute \src "issuer_ls180.v:134924.18-134924.98" + wire width 65 $pos$issuer_ls180.v:134924$6557_Y + attribute \src "issuer_ls180.v:134925.17-134925.92" + wire width 5 $pos$issuer_ls180.v:134925$6559_Y + attribute \src "issuer_ls180.v:134916.18-134916.116" + wire width 3 $sub$issuer_ls180.v:134916$6547_Y + attribute \src "issuer_ls180.v:134917.18-134917.116" + wire width 3 $sub$issuer_ls180.v:134917$6548_Y + attribute \src "issuer_ls180.v:134918.18-134918.116" + wire width 3 $sub$issuer_ls180.v:134918$6549_Y + attribute \src "issuer_ls180.v:134919.18-134919.114" + wire $ternary$issuer_ls180.v:134919$6550_Y + attribute \src "issuer_ls180.v:134920.18-134920.115" + wire $ternary$issuer_ls180.v:134920$6551_Y + attribute \src "issuer_ls180.v:134921.18-134921.112" + wire $ternary$issuer_ls180.v:134921$6552_Y + attribute \src "issuer_ls180.v:134923.18-134923.108" + wire width 64 $ternary$issuer_ls180.v:134923$6555_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:86" + wire width 3 \$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:87" + wire width 3 \$12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:87" + wire width 3 \$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:88" + wire width 3 \$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:88" + wire width 3 \$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:99" + wire \$18 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:100" + wire \$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:100" + wire \$22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \$24 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:140" + wire width 65 \$26 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:140" + wire width 64 \$27 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 5 \$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:86" + wire width 3 \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:131" + wire width 2 \BC + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:82" + wire width 2 \ba + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:83" + wire width 2 \bb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:91" + wire \bit_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:92" + wire \bit_b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:97" + wire \bit_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:81" + wire width 2 \bt + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 4 input 7 \cr_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 4 output 18 \cr_a$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 19 \cr_a_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 4 input 8 \cr_b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:136" + wire \cr_bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 4 input 9 \cr_c + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 input 2 \cr_op__fn_unit + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 output 12 \cr_op__fn_unit$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 3 \cr_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 output 13 \cr_op__insn$4 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 input 1 \cr_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 output 11 \cr_op__insn_type$2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 32 input 6 \full_cr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 32 output 16 \full_cr$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 17 \full_cr_ok + attribute \src "issuer_ls180.v:134651.7-134651.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:70" + wire width 4 \lut + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 input 20 \muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 output 10 \muxid$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 output 14 \o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 15 \o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 4 \ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 5 \rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + cell $pos $extend$issuer_ls180.v:134922$6553 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \Y_WIDTH 64 + connect \A \full_cr + connect \Y $extend$issuer_ls180.v:134922$6553_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:140" + cell $pos $extend$issuer_ls180.v:134924$6556 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 65 + connect \A \$27 + connect \Y $extend$issuer_ls180.v:134924$6556_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + cell $pos $extend$issuer_ls180.v:134925$6558 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 5 + connect \A \cr_a + connect \Y $extend$issuer_ls180.v:134925$6558_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + cell $pos $pos$issuer_ls180.v:134922$6554 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A $extend$issuer_ls180.v:134922$6553_Y + connect \Y $pos$issuer_ls180.v:134922$6554_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:140" + cell $pos $pos$issuer_ls180.v:134924$6557 + parameter \A_SIGNED 0 + parameter \A_WIDTH 65 + parameter \Y_WIDTH 65 + connect \A $extend$issuer_ls180.v:134924$6556_Y + connect \Y $pos$issuer_ls180.v:134924$6557_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + cell $pos $pos$issuer_ls180.v:134925$6559 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \Y_WIDTH 5 + connect \A $extend$issuer_ls180.v:134925$6558_Y + connect \Y $pos$issuer_ls180.v:134925$6559_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:86" + cell $sub $sub$issuer_ls180.v:134916$6547 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 3 + connect \A 2'11 + connect \B \cr_op__insn [22:21] + connect \Y $sub$issuer_ls180.v:134916$6547_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:87" + cell $sub $sub$issuer_ls180.v:134917$6548 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 3 + connect \A 2'11 + connect \B \cr_op__insn [17:16] + connect \Y $sub$issuer_ls180.v:134917$6548_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:88" + cell $sub $sub$issuer_ls180.v:134918$6549 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 3 + connect \A 2'11 + connect \B \cr_op__insn [12:11] + connect \Y $sub$issuer_ls180.v:134918$6549_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:99" + cell $mux $ternary$issuer_ls180.v:134919$6550 + parameter \WIDTH 1 + connect \A \lut [1] + connect \B \lut [3] + connect \S \bit_a + connect \Y $ternary$issuer_ls180.v:134919$6550_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:100" + cell $mux $ternary$issuer_ls180.v:134920$6551 + parameter \WIDTH 1 + connect \A \lut [0] + connect \B \lut [2] + connect \S \bit_a + connect \Y $ternary$issuer_ls180.v:134920$6551_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:100" + cell $mux $ternary$issuer_ls180.v:134921$6552 + parameter \WIDTH 1 + connect \A \$20 + connect \B \$18 + connect \S \bit_b + connect \Y $ternary$issuer_ls180.v:134921$6552_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:140" + cell $mux $ternary$issuer_ls180.v:134923$6555 + parameter \WIDTH 64 + connect \A \rb + connect \B \ra + connect \S \cr_bit + connect \Y $ternary$issuer_ls180.v:134923$6555_Y + end + attribute \src "issuer_ls180.v:134651.7-134651.20" + process $proc$issuer_ls180.v:134651$6578 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "issuer_ls180.v:134926.3-134960.6" + process $proc$issuer_ls180.v:134926$6560 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\cr_a_ok[0:0] $1\cr_a_ok[0:0] + assign $0\cr_a$6[3:0]$6561 $1\cr_a$6[3:0]$6562 + attribute \src "issuer_ls180.v:134927.5-134927.29" + switch \initial + attribute \src "issuer_ls180.v:134927.9-134927.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:52" + switch \cr_op__insn_type + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'0101010 + assign { } { } + assign { } { } + assign $1\cr_a$6[3:0]$6562 \$7 [3:0] + assign $1\cr_a_ok[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'1000101 + assign { } { } + assign { } { } + assign { } { } + assign $1\cr_a$6[3:0]$6562 $2\cr_a$6[3:0]$6563 + assign $1\cr_a_ok[0:0] 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:105" + switch \bt + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'00 + assign $2\cr_a$6[3:0]$6563 [3:1] \cr_c [3:1] + assign $2\cr_a$6[3:0]$6563 [0] \bit_o + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'01 + assign { $2\cr_a$6[3:0]$6563 [3:2] $2\cr_a$6[3:0]$6563 [0] } { \cr_c [3:2] \cr_c [0] } + assign $2\cr_a$6[3:0]$6563 [1] \bit_o + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'10 + assign { $2\cr_a$6[3:0]$6563 [3] $2\cr_a$6[3:0]$6563 [1:0] } { \cr_c [3] \cr_c [1:0] } + assign $2\cr_a$6[3:0]$6563 [2] \bit_o + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'-- + assign $2\cr_a$6[3:0]$6563 [2:0] \cr_c [2:0] + assign $2\cr_a$6[3:0]$6563 [3] \bit_o + case + assign $2\cr_a$6[3:0]$6563 \cr_c + end + case + assign $1\cr_a_ok[0:0] 1'0 + assign $1\cr_a$6[3:0]$6562 4'0000 + end + sync always + update \cr_a_ok $0\cr_a_ok[0:0] + update \cr_a$6 $0\cr_a$6[3:0]$6561 + end + attribute \src "issuer_ls180.v:134961.3-134971.6" + process $proc$issuer_ls180.v:134961$6564 + assign { } { } + assign { } { } + assign $0\full_cr_ok[0:0] $1\full_cr_ok[0:0] + attribute \src "issuer_ls180.v:134962.5-134962.29" + switch \initial + attribute \src "issuer_ls180.v:134962.9-134962.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:52" + switch \cr_op__insn_type + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'0110000 + assign { } { } + assign $1\full_cr_ok[0:0] 1'1 + case + assign $1\full_cr_ok[0:0] 1'0 + end + sync always + update \full_cr_ok $0\full_cr_ok[0:0] + end + attribute \src "issuer_ls180.v:134972.3-135013.6" + process $proc$issuer_ls180.v:134972$6565 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\o_ok[0:0] $1\o_ok[0:0] + assign $0\o[63:0] $1\o[63:0] + attribute \src "issuer_ls180.v:134973.5-134973.29" + switch \initial + attribute \src "issuer_ls180.v:134973.9-134973.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:52" + switch \cr_op__insn_type + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'0101101 + assign { } { } + assign { } { } + assign $1\o[63:0] \$24 + assign $1\o_ok[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'0100011 + assign { } { } + assign { } { } + assign $1\o[63:0] \$26 [63:0] + assign $1\o_ok[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'0111011 + assign { } { } + assign { } { } + assign $1\o[63:0] $2\o[63:0] + assign $1\o_ok[0:0] 1'1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:144" + switch { \cr_a [2] \cr_a [3] } + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $2\o[63:0] 64'1111111111111111111111111111111111111111111111111111111111111111 + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'1- + assign { } { } + assign $2\o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000001 + attribute \src "issuer_ls180.v:0.0-0.0" + case + assign { } { } + assign $2\o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + case + assign $1\o_ok[0:0] 1'0 + assign $1\o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \o_ok $0\o_ok[0:0] + update \o $0\o[63:0] + end + attribute \src "issuer_ls180.v:135014.3-135024.6" + process $proc$issuer_ls180.v:135014$6566 + assign { } { } + assign { } { } + assign $0\BC[1:0] $1\BC[1:0] + attribute \src "issuer_ls180.v:135015.5-135015.29" + switch \initial + attribute \src "issuer_ls180.v:135015.9-135015.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:52" + switch \cr_op__insn_type + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'0100011 + assign { } { } + assign $1\BC[1:0] \cr_op__insn [7:6] + case + assign $1\BC[1:0] 2'00 + end + sync always + update \BC $0\BC[1:0] + end + attribute \src "issuer_ls180.v:135025.3-135045.6" + process $proc$issuer_ls180.v:135025$6567 + assign { } { } + assign { } { } + assign $0\cr_bit[0:0] $1\cr_bit[0:0] + attribute \src "issuer_ls180.v:135026.5-135026.29" + switch \initial + attribute \src "issuer_ls180.v:135026.9-135026.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:52" + switch \cr_op__insn_type + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'0100011 + assign { } { } + assign $1\cr_bit[0:0] $2\cr_bit[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:137" + switch \BC + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'00 + assign { } { } + assign $2\cr_bit[0:0] \cr_a [3] + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'01 + assign { } { } + assign $2\cr_bit[0:0] \cr_a [2] + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'10 + assign { } { } + assign $2\cr_bit[0:0] \cr_a [1] + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'-- + assign { } { } + assign $2\cr_bit[0:0] \cr_a [0] + case + assign $2\cr_bit[0:0] 1'0 + end + case + assign $1\cr_bit[0:0] 1'0 + end + sync always + update \cr_bit $0\cr_bit[0:0] + end + attribute \src "issuer_ls180.v:135046.3-135056.6" + process $proc$issuer_ls180.v:135046$6568 + assign { } { } + assign { } { } + assign $0\lut[3:0] $1\lut[3:0] + attribute \src "issuer_ls180.v:135047.5-135047.29" + switch \initial + attribute \src "issuer_ls180.v:135047.9-135047.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:52" + switch \cr_op__insn_type + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'1000101 + assign { } { } + assign $1\lut[3:0] \cr_op__insn [9:6] + case + assign $1\lut[3:0] 4'0000 + end + sync always + update \lut $0\lut[3:0] + end + attribute \src "issuer_ls180.v:135057.3-135067.6" + process $proc$issuer_ls180.v:135057$6569 + assign { } { } + assign { } { } + assign $0\bt[1:0] $1\bt[1:0] + attribute \src "issuer_ls180.v:135058.5-135058.29" + switch \initial + attribute \src "issuer_ls180.v:135058.9-135058.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:52" + switch \cr_op__insn_type + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'1000101 + assign { } { } + assign $1\bt[1:0] \$9 [1:0] + case + assign $1\bt[1:0] 2'00 + end + sync always + update \bt $0\bt[1:0] + end + attribute \src "issuer_ls180.v:135068.3-135078.6" + process $proc$issuer_ls180.v:135068$6570 + assign { } { } + assign { } { } + assign $0\ba[1:0] $1\ba[1:0] + attribute \src "issuer_ls180.v:135069.5-135069.29" + switch \initial + attribute \src "issuer_ls180.v:135069.9-135069.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:52" + switch \cr_op__insn_type + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'1000101 + assign { } { } + assign $1\ba[1:0] \$12 [1:0] + case + assign $1\ba[1:0] 2'00 + end + sync always + update \ba $0\ba[1:0] + end + attribute \src "issuer_ls180.v:135079.3-135089.6" + process $proc$issuer_ls180.v:135079$6571 + assign { } { } + assign { } { } + assign $0\bb[1:0] $1\bb[1:0] + attribute \src "issuer_ls180.v:135080.5-135080.29" + switch \initial + attribute \src "issuer_ls180.v:135080.9-135080.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:52" + switch \cr_op__insn_type + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'1000101 + assign { } { } + assign $1\bb[1:0] \$15 [1:0] + case + assign $1\bb[1:0] 2'00 + end + sync always + update \bb $0\bb[1:0] + end + attribute \src "issuer_ls180.v:135090.3-135110.6" + process $proc$issuer_ls180.v:135090$6572 + assign { } { } + assign { } { } + assign $0\bit_a[0:0] $1\bit_a[0:0] + attribute \src "issuer_ls180.v:135091.5-135091.29" + switch \initial + attribute \src "issuer_ls180.v:135091.9-135091.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:52" + switch \cr_op__insn_type + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'1000101 + assign { } { } + assign $1\bit_a[0:0] $2\bit_a[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:93" + switch \ba + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'00 + assign { } { } + assign $2\bit_a[0:0] \cr_a [0] + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'01 + assign { } { } + assign $2\bit_a[0:0] \cr_a [1] + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'10 + assign { } { } + assign $2\bit_a[0:0] \cr_a [2] + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'-- + assign { } { } + assign $2\bit_a[0:0] \cr_a [3] + case + assign $2\bit_a[0:0] 1'0 + end + case + assign $1\bit_a[0:0] 1'0 + end + sync always + update \bit_a $0\bit_a[0:0] + end + attribute \src "issuer_ls180.v:135111.3-135131.6" + process $proc$issuer_ls180.v:135111$6573 + assign { } { } + assign { } { } + assign $0\bit_b[0:0] $1\bit_b[0:0] + attribute \src "issuer_ls180.v:135112.5-135112.29" + switch \initial + attribute \src "issuer_ls180.v:135112.9-135112.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:52" + switch \cr_op__insn_type + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'1000101 + assign { } { } + assign $1\bit_b[0:0] $2\bit_b[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:94" + switch \bb + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'00 + assign { } { } + assign $2\bit_b[0:0] \cr_b [0] + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'01 + assign { } { } + assign $2\bit_b[0:0] \cr_b [1] + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'10 + assign { } { } + assign $2\bit_b[0:0] \cr_b [2] + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'-- + assign { } { } + assign $2\bit_b[0:0] \cr_b [3] + case + assign $2\bit_b[0:0] 1'0 + end + case + assign $1\bit_b[0:0] 1'0 + end + sync always + update \bit_b $0\bit_b[0:0] + end + attribute \src "issuer_ls180.v:135132.3-135142.6" + process $proc$issuer_ls180.v:135132$6574 + assign { } { } + assign { } { } + assign $0\bit_o[0:0] $1\bit_o[0:0] + attribute \src "issuer_ls180.v:135133.5-135133.29" + switch \initial + attribute \src "issuer_ls180.v:135133.9-135133.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:52" + switch \cr_op__insn_type + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'1000101 + assign { } { } + assign $1\bit_o[0:0] \$22 + case + assign $1\bit_o[0:0] 1'0 + end + sync always + update \bit_o $0\bit_o[0:0] + end + attribute \src "issuer_ls180.v:135143.3-135153.6" + process $proc$issuer_ls180.v:135143$6575 + assign { } { } + assign { } { } + assign $0\full_cr$5[31:0]$6576 $1\full_cr$5[31:0]$6577 + attribute \src "issuer_ls180.v:135144.5-135144.29" + switch \initial + attribute \src "issuer_ls180.v:135144.9-135144.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:52" + switch \cr_op__insn_type + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'0110000 + assign { } { } + assign $1\full_cr$5[31:0]$6577 \ra [31:0] + case + assign $1\full_cr$5[31:0]$6577 0 + end + sync always + update \full_cr$5 $0\full_cr$5[31:0]$6576 + end + connect \$10 $sub$issuer_ls180.v:134916$6547_Y + connect \$13 $sub$issuer_ls180.v:134917$6548_Y + connect \$16 $sub$issuer_ls180.v:134918$6549_Y + connect \$18 $ternary$issuer_ls180.v:134919$6550_Y + connect \$20 $ternary$issuer_ls180.v:134920$6551_Y + connect \$22 $ternary$issuer_ls180.v:134921$6552_Y + connect \$24 $pos$issuer_ls180.v:134922$6554_Y + connect \$27 $ternary$issuer_ls180.v:134923$6555_Y + connect \$26 $pos$issuer_ls180.v:134924$6557_Y + connect \$7 $pos$issuer_ls180.v:134925$6559_Y + connect \$9 \$10 + connect \$12 \$13 + connect \$15 \$16 + connect { \cr_op__insn$4 \cr_op__fn_unit$3 \cr_op__insn_type$2 } { \cr_op__insn \cr_op__fn_unit \cr_op__insn_type } + connect \muxid$1 \muxid +end +attribute \src "issuer_ls180.v:135163.1-136318.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.fus.mul0" +attribute \generator "nMigen" +module \mul0 + attribute \src "issuer_ls180.v:135889.3-135890.25" + wire $0\all_rd_dly[0:0] + attribute \src "issuer_ls180.v:135887.3-135888.40" + wire $0\alu_done_dly[0:0] + attribute \src "issuer_ls180.v:136230.3-136238.6" + wire $0\alu_l_r_alu$next[0:0]$6784 + attribute \src "issuer_ls180.v:135815.3-135816.39" + wire $0\alu_l_r_alu[0:0] + attribute \src "issuer_ls180.v:136070.3-136102.6" + wire width 12 $0\alu_mul0_mul_op__fn_unit$next[11:0]$6709 + attribute \src "issuer_ls180.v:135843.3-135844.65" + wire width 12 $0\alu_mul0_mul_op__fn_unit[11:0] + attribute \src "issuer_ls180.v:136070.3-136102.6" + wire width 64 $0\alu_mul0_mul_op__imm_data__data$next[63:0]$6710 + attribute \src "issuer_ls180.v:135845.3-135846.79" + wire width 64 $0\alu_mul0_mul_op__imm_data__data[63:0] + attribute \src "issuer_ls180.v:136070.3-136102.6" + wire $0\alu_mul0_mul_op__imm_data__ok$next[0:0]$6711 + attribute \src "issuer_ls180.v:135847.3-135848.75" + wire $0\alu_mul0_mul_op__imm_data__ok[0:0] + attribute \src "issuer_ls180.v:136070.3-136102.6" + wire width 32 $0\alu_mul0_mul_op__insn$next[31:0]$6712 + attribute \src "issuer_ls180.v:135863.3-135864.59" + wire width 32 $0\alu_mul0_mul_op__insn[31:0] + attribute \src "issuer_ls180.v:136070.3-136102.6" + wire width 7 $0\alu_mul0_mul_op__insn_type$next[6:0]$6713 + attribute \src "issuer_ls180.v:135841.3-135842.69" + wire width 7 $0\alu_mul0_mul_op__insn_type[6:0] + attribute \src "issuer_ls180.v:136070.3-136102.6" + wire $0\alu_mul0_mul_op__is_32bit$next[0:0]$6714 + attribute \src "issuer_ls180.v:135859.3-135860.67" + wire $0\alu_mul0_mul_op__is_32bit[0:0] + attribute \src "issuer_ls180.v:136070.3-136102.6" + wire $0\alu_mul0_mul_op__is_signed$next[0:0]$6715 + attribute \src "issuer_ls180.v:135861.3-135862.69" + wire $0\alu_mul0_mul_op__is_signed[0:0] + attribute \src "issuer_ls180.v:136070.3-136102.6" + wire $0\alu_mul0_mul_op__oe__oe$next[0:0]$6716 + attribute \src "issuer_ls180.v:135853.3-135854.63" + wire $0\alu_mul0_mul_op__oe__oe[0:0] + attribute \src "issuer_ls180.v:136070.3-136102.6" + wire $0\alu_mul0_mul_op__oe__ok$next[0:0]$6717 + attribute \src "issuer_ls180.v:135855.3-135856.63" + wire $0\alu_mul0_mul_op__oe__ok[0:0] + attribute \src "issuer_ls180.v:136070.3-136102.6" + wire $0\alu_mul0_mul_op__rc__ok$next[0:0]$6718 + attribute \src "issuer_ls180.v:135851.3-135852.63" + wire $0\alu_mul0_mul_op__rc__ok[0:0] + attribute \src "issuer_ls180.v:136070.3-136102.6" + wire $0\alu_mul0_mul_op__rc__rc$next[0:0]$6719 + attribute \src "issuer_ls180.v:135849.3-135850.63" + wire $0\alu_mul0_mul_op__rc__rc[0:0] + attribute \src "issuer_ls180.v:136070.3-136102.6" + wire $0\alu_mul0_mul_op__write_cr0$next[0:0]$6720 + attribute \src "issuer_ls180.v:135857.3-135858.69" + wire $0\alu_mul0_mul_op__write_cr0[0:0] + attribute \src "issuer_ls180.v:136221.3-136229.6" + wire $0\alui_l_r_alui$next[0:0]$6781 + attribute \src "issuer_ls180.v:135817.3-135818.43" + wire $0\alui_l_r_alui[0:0] + attribute \src "issuer_ls180.v:136103.3-136124.6" + wire width 64 $0\data_r0__o$next[63:0]$6740 + attribute \src "issuer_ls180.v:135837.3-135838.37" + wire width 64 $0\data_r0__o[63:0] + attribute \src "issuer_ls180.v:136103.3-136124.6" + wire $0\data_r0__o_ok$next[0:0]$6741 + attribute \src "issuer_ls180.v:135839.3-135840.43" + wire $0\data_r0__o_ok[0:0] + attribute \src "issuer_ls180.v:136125.3-136146.6" + wire width 4 $0\data_r1__cr_a$next[3:0]$6748 + attribute \src "issuer_ls180.v:135833.3-135834.43" + wire width 4 $0\data_r1__cr_a[3:0] + attribute \src "issuer_ls180.v:136125.3-136146.6" + wire $0\data_r1__cr_a_ok$next[0:0]$6749 + attribute \src "issuer_ls180.v:135835.3-135836.49" + wire $0\data_r1__cr_a_ok[0:0] + attribute \src "issuer_ls180.v:136147.3-136168.6" + wire width 2 $0\data_r2__xer_ov$next[1:0]$6756 + attribute \src "issuer_ls180.v:135829.3-135830.47" + wire width 2 $0\data_r2__xer_ov[1:0] + attribute \src "issuer_ls180.v:136147.3-136168.6" + wire $0\data_r2__xer_ov_ok$next[0:0]$6757 + attribute \src "issuer_ls180.v:135831.3-135832.53" + wire $0\data_r2__xer_ov_ok[0:0] + attribute \src "issuer_ls180.v:136169.3-136190.6" + wire $0\data_r3__xer_so$next[0:0]$6764 + attribute \src "issuer_ls180.v:135825.3-135826.47" + wire $0\data_r3__xer_so[0:0] + attribute \src "issuer_ls180.v:136169.3-136190.6" + wire $0\data_r3__xer_so_ok$next[0:0]$6765 + attribute \src "issuer_ls180.v:135827.3-135828.53" + wire $0\data_r3__xer_so_ok[0:0] + attribute \src "issuer_ls180.v:136239.3-136248.6" + wire width 64 $0\dest1_o[63:0] + attribute \src "issuer_ls180.v:136249.3-136258.6" + wire width 4 $0\dest2_o[3:0] + attribute \src "issuer_ls180.v:136259.3-136268.6" + wire width 2 $0\dest3_o[1:0] + attribute \src "issuer_ls180.v:136269.3-136278.6" + wire $0\dest4_o[0:0] + attribute \src "issuer_ls180.v:135164.7-135164.20" + wire $0\initial[0:0] + attribute \src "issuer_ls180.v:136025.3-136033.6" + wire $0\opc_l_r_opc$next[0:0]$6694 + attribute \src "issuer_ls180.v:135873.3-135874.39" + wire $0\opc_l_r_opc[0:0] + attribute \src "issuer_ls180.v:136016.3-136024.6" + wire $0\opc_l_s_opc$next[0:0]$6691 + attribute \src "issuer_ls180.v:135875.3-135876.39" + wire $0\opc_l_s_opc[0:0] + attribute \src "issuer_ls180.v:136279.3-136287.6" + wire width 4 $0\prev_wr_go$next[3:0]$6791 + attribute \src "issuer_ls180.v:135885.3-135886.37" + wire width 4 $0\prev_wr_go[3:0] + attribute \src "issuer_ls180.v:135970.3-135979.6" + wire $0\req_done[0:0] + attribute \src "issuer_ls180.v:136061.3-136069.6" + wire width 4 $0\req_l_r_req$next[3:0]$6706 + attribute \src "issuer_ls180.v:135865.3-135866.39" + wire width 4 $0\req_l_r_req[3:0] + attribute \src "issuer_ls180.v:136052.3-136060.6" + wire width 4 $0\req_l_s_req$next[3:0]$6703 + attribute \src "issuer_ls180.v:135867.3-135868.39" + wire width 4 $0\req_l_s_req[3:0] + attribute \src "issuer_ls180.v:135989.3-135997.6" + wire $0\rok_l_r_rdok$next[0:0]$6682 + attribute \src "issuer_ls180.v:135881.3-135882.41" + wire $0\rok_l_r_rdok[0:0] + attribute \src "issuer_ls180.v:135980.3-135988.6" + wire $0\rok_l_s_rdok$next[0:0]$6679 + attribute \src "issuer_ls180.v:135883.3-135884.41" + wire $0\rok_l_s_rdok[0:0] + attribute \src "issuer_ls180.v:136007.3-136015.6" + wire $0\rst_l_r_rst$next[0:0]$6688 + attribute \src "issuer_ls180.v:135877.3-135878.39" + wire $0\rst_l_r_rst[0:0] + attribute \src "issuer_ls180.v:135998.3-136006.6" + wire $0\rst_l_s_rst$next[0:0]$6685 + attribute \src "issuer_ls180.v:135879.3-135880.39" + wire $0\rst_l_s_rst[0:0] + attribute \src "issuer_ls180.v:136043.3-136051.6" + wire width 3 $0\src_l_r_src$next[2:0]$6700 + attribute \src "issuer_ls180.v:135869.3-135870.39" + wire width 3 $0\src_l_r_src[2:0] + attribute \src "issuer_ls180.v:136034.3-136042.6" + wire width 3 $0\src_l_s_src$next[2:0]$6697 + attribute \src "issuer_ls180.v:135871.3-135872.39" + wire width 3 $0\src_l_s_src[2:0] + attribute \src "issuer_ls180.v:136191.3-136200.6" + wire width 64 $0\src_r0$next[63:0]$6772 + attribute \src "issuer_ls180.v:135823.3-135824.29" + wire width 64 $0\src_r0[63:0] + attribute \src "issuer_ls180.v:136201.3-136210.6" + wire width 64 $0\src_r1$next[63:0]$6775 + attribute \src "issuer_ls180.v:135821.3-135822.29" + wire width 64 $0\src_r1[63:0] + attribute \src "issuer_ls180.v:136211.3-136220.6" + wire $0\src_r2$next[0:0]$6778 + attribute \src "issuer_ls180.v:135819.3-135820.29" + wire $0\src_r2[0:0] + attribute \src "issuer_ls180.v:135288.7-135288.24" + wire $1\all_rd_dly[0:0] + attribute \src "issuer_ls180.v:135298.7-135298.26" + wire $1\alu_done_dly[0:0] + attribute \src "issuer_ls180.v:136230.3-136238.6" + wire $1\alu_l_r_alu$next[0:0]$6785 + attribute \src "issuer_ls180.v:135306.7-135306.25" + wire $1\alu_l_r_alu[0:0] + attribute \src "issuer_ls180.v:136070.3-136102.6" + wire width 12 $1\alu_mul0_mul_op__fn_unit$next[11:0]$6721 + attribute \src "issuer_ls180.v:135327.14-135327.48" + wire width 12 $1\alu_mul0_mul_op__fn_unit[11:0] + attribute \src "issuer_ls180.v:136070.3-136102.6" + wire width 64 $1\alu_mul0_mul_op__imm_data__data$next[63:0]$6722 + attribute \src "issuer_ls180.v:135331.14-135331.68" + wire width 64 $1\alu_mul0_mul_op__imm_data__data[63:0] + attribute \src "issuer_ls180.v:136070.3-136102.6" + wire $1\alu_mul0_mul_op__imm_data__ok$next[0:0]$6723 + attribute \src "issuer_ls180.v:135335.7-135335.43" + wire $1\alu_mul0_mul_op__imm_data__ok[0:0] + attribute \src "issuer_ls180.v:136070.3-136102.6" + wire width 32 $1\alu_mul0_mul_op__insn$next[31:0]$6724 + attribute \src "issuer_ls180.v:135339.14-135339.43" + wire width 32 $1\alu_mul0_mul_op__insn[31:0] + attribute \src "issuer_ls180.v:136070.3-136102.6" + wire width 7 $1\alu_mul0_mul_op__insn_type$next[6:0]$6725 + attribute \src "issuer_ls180.v:135417.13-135417.47" + wire width 7 $1\alu_mul0_mul_op__insn_type[6:0] + attribute \src "issuer_ls180.v:136070.3-136102.6" + wire $1\alu_mul0_mul_op__is_32bit$next[0:0]$6726 + attribute \src "issuer_ls180.v:135421.7-135421.39" + wire $1\alu_mul0_mul_op__is_32bit[0:0] + attribute \src "issuer_ls180.v:136070.3-136102.6" + wire $1\alu_mul0_mul_op__is_signed$next[0:0]$6727 + attribute \src "issuer_ls180.v:135425.7-135425.40" + wire $1\alu_mul0_mul_op__is_signed[0:0] + attribute \src "issuer_ls180.v:136070.3-136102.6" + wire $1\alu_mul0_mul_op__oe__oe$next[0:0]$6728 + attribute \src "issuer_ls180.v:135429.7-135429.37" + wire $1\alu_mul0_mul_op__oe__oe[0:0] + attribute \src "issuer_ls180.v:136070.3-136102.6" + wire $1\alu_mul0_mul_op__oe__ok$next[0:0]$6729 + attribute \src "issuer_ls180.v:135433.7-135433.37" + wire $1\alu_mul0_mul_op__oe__ok[0:0] + attribute \src "issuer_ls180.v:136070.3-136102.6" + wire $1\alu_mul0_mul_op__rc__ok$next[0:0]$6730 + attribute \src "issuer_ls180.v:135437.7-135437.37" + wire $1\alu_mul0_mul_op__rc__ok[0:0] + attribute \src "issuer_ls180.v:136070.3-136102.6" + wire $1\alu_mul0_mul_op__rc__rc$next[0:0]$6731 + attribute \src "issuer_ls180.v:135441.7-135441.37" + wire $1\alu_mul0_mul_op__rc__rc[0:0] + attribute \src "issuer_ls180.v:136070.3-136102.6" + wire $1\alu_mul0_mul_op__write_cr0$next[0:0]$6732 + attribute \src "issuer_ls180.v:135445.7-135445.40" + wire $1\alu_mul0_mul_op__write_cr0[0:0] + attribute \src "issuer_ls180.v:136221.3-136229.6" + wire $1\alui_l_r_alui$next[0:0]$6782 + attribute \src "issuer_ls180.v:135475.7-135475.27" + wire $1\alui_l_r_alui[0:0] + attribute \src "issuer_ls180.v:136103.3-136124.6" + wire width 64 $1\data_r0__o$next[63:0]$6742 + attribute \src "issuer_ls180.v:135509.14-135509.47" + wire width 64 $1\data_r0__o[63:0] + attribute \src "issuer_ls180.v:136103.3-136124.6" + wire $1\data_r0__o_ok$next[0:0]$6743 + attribute \src "issuer_ls180.v:135513.7-135513.27" + wire $1\data_r0__o_ok[0:0] + attribute \src "issuer_ls180.v:136125.3-136146.6" + wire width 4 $1\data_r1__cr_a$next[3:0]$6750 + attribute \src "issuer_ls180.v:135517.13-135517.33" + wire width 4 $1\data_r1__cr_a[3:0] + attribute \src "issuer_ls180.v:136125.3-136146.6" + wire $1\data_r1__cr_a_ok$next[0:0]$6751 + attribute \src "issuer_ls180.v:135521.7-135521.30" + wire $1\data_r1__cr_a_ok[0:0] + attribute \src "issuer_ls180.v:136147.3-136168.6" + wire width 2 $1\data_r2__xer_ov$next[1:0]$6758 + attribute \src "issuer_ls180.v:135525.13-135525.35" + wire width 2 $1\data_r2__xer_ov[1:0] + attribute \src "issuer_ls180.v:136147.3-136168.6" + wire $1\data_r2__xer_ov_ok$next[0:0]$6759 + attribute \src "issuer_ls180.v:135529.7-135529.32" + wire $1\data_r2__xer_ov_ok[0:0] + attribute \src "issuer_ls180.v:136169.3-136190.6" + wire $1\data_r3__xer_so$next[0:0]$6766 + attribute \src "issuer_ls180.v:135533.7-135533.29" + wire $1\data_r3__xer_so[0:0] + attribute \src "issuer_ls180.v:136169.3-136190.6" + wire $1\data_r3__xer_so_ok$next[0:0]$6767 + attribute \src "issuer_ls180.v:135537.7-135537.32" + wire $1\data_r3__xer_so_ok[0:0] + attribute \src "issuer_ls180.v:136239.3-136248.6" + wire width 64 $1\dest1_o[63:0] + attribute \src "issuer_ls180.v:136249.3-136258.6" + wire width 4 $1\dest2_o[3:0] + attribute \src "issuer_ls180.v:136259.3-136268.6" + wire width 2 $1\dest3_o[1:0] + attribute \src "issuer_ls180.v:136269.3-136278.6" + wire $1\dest4_o[0:0] + attribute \src "issuer_ls180.v:136025.3-136033.6" + wire $1\opc_l_r_opc$next[0:0]$6695 + attribute \src "issuer_ls180.v:135557.7-135557.25" + wire $1\opc_l_r_opc[0:0] + attribute \src "issuer_ls180.v:136016.3-136024.6" + wire $1\opc_l_s_opc$next[0:0]$6692 + attribute \src "issuer_ls180.v:135561.7-135561.25" + wire $1\opc_l_s_opc[0:0] + attribute \src "issuer_ls180.v:136279.3-136287.6" + wire width 4 $1\prev_wr_go$next[3:0]$6792 + attribute \src "issuer_ls180.v:135676.13-135676.30" + wire width 4 $1\prev_wr_go[3:0] + attribute \src "issuer_ls180.v:135970.3-135979.6" + wire $1\req_done[0:0] + attribute \src "issuer_ls180.v:136061.3-136069.6" + wire width 4 $1\req_l_r_req$next[3:0]$6707 + attribute \src "issuer_ls180.v:135684.13-135684.31" + wire width 4 $1\req_l_r_req[3:0] + attribute \src "issuer_ls180.v:136052.3-136060.6" + wire width 4 $1\req_l_s_req$next[3:0]$6704 + attribute \src "issuer_ls180.v:135688.13-135688.31" + wire width 4 $1\req_l_s_req[3:0] + attribute \src "issuer_ls180.v:135989.3-135997.6" + wire $1\rok_l_r_rdok$next[0:0]$6683 + attribute \src "issuer_ls180.v:135700.7-135700.26" + wire $1\rok_l_r_rdok[0:0] + attribute \src "issuer_ls180.v:135980.3-135988.6" + wire $1\rok_l_s_rdok$next[0:0]$6680 + attribute \src "issuer_ls180.v:135704.7-135704.26" + wire $1\rok_l_s_rdok[0:0] + attribute \src "issuer_ls180.v:136007.3-136015.6" + wire $1\rst_l_r_rst$next[0:0]$6689 + attribute \src "issuer_ls180.v:135708.7-135708.25" + wire $1\rst_l_r_rst[0:0] + attribute \src "issuer_ls180.v:135998.3-136006.6" + wire $1\rst_l_s_rst$next[0:0]$6686 + attribute \src "issuer_ls180.v:135712.7-135712.25" + wire $1\rst_l_s_rst[0:0] + attribute \src "issuer_ls180.v:136043.3-136051.6" + wire width 3 $1\src_l_r_src$next[2:0]$6701 + attribute \src "issuer_ls180.v:135726.13-135726.31" + wire width 3 $1\src_l_r_src[2:0] + attribute \src "issuer_ls180.v:136034.3-136042.6" + wire width 3 $1\src_l_s_src$next[2:0]$6698 + attribute \src "issuer_ls180.v:135730.13-135730.31" + wire width 3 $1\src_l_s_src[2:0] + attribute \src "issuer_ls180.v:136191.3-136200.6" + wire width 64 $1\src_r0$next[63:0]$6773 + attribute \src "issuer_ls180.v:135736.14-135736.43" + wire width 64 $1\src_r0[63:0] + attribute \src "issuer_ls180.v:136201.3-136210.6" + wire width 64 $1\src_r1$next[63:0]$6776 + attribute \src "issuer_ls180.v:135740.14-135740.43" + wire width 64 $1\src_r1[63:0] + attribute \src "issuer_ls180.v:136211.3-136220.6" + wire $1\src_r2$next[0:0]$6779 + attribute \src "issuer_ls180.v:135744.7-135744.20" + wire $1\src_r2[0:0] + attribute \src "issuer_ls180.v:136070.3-136102.6" + wire width 64 $2\alu_mul0_mul_op__imm_data__data$next[63:0]$6733 + attribute \src "issuer_ls180.v:136070.3-136102.6" + wire $2\alu_mul0_mul_op__imm_data__ok$next[0:0]$6734 + attribute \src "issuer_ls180.v:136070.3-136102.6" + wire $2\alu_mul0_mul_op__oe__oe$next[0:0]$6735 + attribute \src "issuer_ls180.v:136070.3-136102.6" + wire $2\alu_mul0_mul_op__oe__ok$next[0:0]$6736 + attribute \src "issuer_ls180.v:136070.3-136102.6" + wire $2\alu_mul0_mul_op__rc__ok$next[0:0]$6737 + attribute \src "issuer_ls180.v:136070.3-136102.6" + wire $2\alu_mul0_mul_op__rc__rc$next[0:0]$6738 + attribute \src "issuer_ls180.v:136103.3-136124.6" + wire width 64 $2\data_r0__o$next[63:0]$6744 + attribute \src "issuer_ls180.v:136103.3-136124.6" + wire $2\data_r0__o_ok$next[0:0]$6745 + attribute \src "issuer_ls180.v:136125.3-136146.6" + wire width 4 $2\data_r1__cr_a$next[3:0]$6752 + attribute \src "issuer_ls180.v:136125.3-136146.6" + wire $2\data_r1__cr_a_ok$next[0:0]$6753 + attribute \src "issuer_ls180.v:136147.3-136168.6" + wire width 2 $2\data_r2__xer_ov$next[1:0]$6760 + attribute \src "issuer_ls180.v:136147.3-136168.6" + wire $2\data_r2__xer_ov_ok$next[0:0]$6761 + attribute \src "issuer_ls180.v:136169.3-136190.6" + wire $2\data_r3__xer_so$next[0:0]$6768 + attribute \src "issuer_ls180.v:136169.3-136190.6" + wire $2\data_r3__xer_so_ok$next[0:0]$6769 + attribute \src "issuer_ls180.v:136103.3-136124.6" + wire $3\data_r0__o_ok$next[0:0]$6746 + attribute \src "issuer_ls180.v:136125.3-136146.6" + wire $3\data_r1__cr_a_ok$next[0:0]$6754 + attribute \src "issuer_ls180.v:136147.3-136168.6" + wire $3\data_r2__xer_ov_ok$next[0:0]$6762 + attribute \src "issuer_ls180.v:136169.3-136190.6" + wire $3\data_r3__xer_so_ok$next[0:0]$6770 + attribute \src "issuer_ls180.v:135755.19-135755.113" + wire width 3 $and$issuer_ls180.v:135755$6579_Y + attribute \src "issuer_ls180.v:135756.19-135756.125" + wire $and$issuer_ls180.v:135756$6580_Y + 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"/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" + cell $and $and$issuer_ls180.v:135777$6601 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cu_busy_o + connect \B \$22 + connect \Y $and$issuer_ls180.v:135777$6601_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" + cell $and $and$issuer_ls180.v:135782$6606 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_any + connect \B \$38 + connect \Y $and$issuer_ls180.v:135782$6606_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" + cell $and $and$issuer_ls180.v:135783$6607 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \req_l_q_req + connect \B \cu_wrmask_o + connect \Y $and$issuer_ls180.v:135783$6607_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" + cell $and $and$issuer_ls180.v:135785$6609 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$40 + connect \B \$44 + connect \Y $and$issuer_ls180.v:135785$6609_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" + cell $and $and$issuer_ls180.v:135787$6611 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$48 + connect \B \alu_mul0_n_ready_i + connect \Y $and$issuer_ls180.v:135787$6611_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" + cell $and $and$issuer_ls180.v:135788$6612 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$50 + connect \B \alu_mul0_n_valid_o + connect \Y $and$issuer_ls180.v:135788$6612_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" + cell $and $and$issuer_ls180.v:135789$6613 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$52 + connect \B \cu_busy_o + connect \Y $and$issuer_ls180.v:135789$6613_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:237" + cell $and $and$issuer_ls180.v:135795$6619 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \alu_mul0_n_valid_o + connect \B \cu_busy_o + connect \Y $and$issuer_ls180.v:135795$6619_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:252" + cell $and $and$issuer_ls180.v:135796$6620 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \alu_pulsem + connect \B \cu_wrmask_o + connect \Y $and$issuer_ls180.v:135796$6620_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" + cell $and $and$issuer_ls180.v:135798$6622 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \o_ok + connect \B \cu_busy_o + connect \Y $and$issuer_ls180.v:135798$6622_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" + cell $and $and$issuer_ls180.v:135799$6623 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cr_a_ok + connect \B \cu_busy_o + connect \Y $and$issuer_ls180.v:135799$6623_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" + cell $and $and$issuer_ls180.v:135800$6624 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \xer_ov_ok + connect \B \cu_busy_o + connect \Y $and$issuer_ls180.v:135800$6624_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" + cell $and $and$issuer_ls180.v:135801$6625 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \xer_so_ok + connect \B \cu_busy_o + connect \Y $and$issuer_ls180.v:135801$6625_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:327" + cell $and $and$issuer_ls180.v:135808$6632 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \alu_mul0_p_ready_o + connect \B \alui_l_q_alui + connect \Y $and$issuer_ls180.v:135808$6632_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:334" + cell $and $and$issuer_ls180.v:135810$6634 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \alu_mul0_n_valid_o + connect \B \alu_l_q_alu + connect \Y $and$issuer_ls180.v:135810$6634_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" + cell $and $and$issuer_ls180.v:135811$6635 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \src_l_q_src + connect \B { \cu_busy_o \cu_busy_o \cu_busy_o } + connect \Y $and$issuer_ls180.v:135811$6635_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" + cell $and $and$issuer_ls180.v:135813$6637 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \$92 + connect \B { 1'1 \$94 1'1 } + connect \Y $and$issuer_ls180.v:135813$6637_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" + cell $eq $eq$issuer_ls180.v:135784$6608 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$42 + connect \B 1'0 + connect \Y $eq$issuer_ls180.v:135784$6608_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" + cell $eq $eq$issuer_ls180.v:135786$6610 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cu_wrmask_o + connect \B 1'0 + connect \Y $eq$issuer_ls180.v:135786$6610_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + cell $not $not$issuer_ls180.v:135767$6591 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \all_rd_dly + connect \Y $not$issuer_ls180.v:135767$6591_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + cell $not $not$issuer_ls180.v:135769$6593 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \alu_done_dly + connect \Y $not$issuer_ls180.v:135769$6593_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" + cell $not $not$issuer_ls180.v:135772$6596 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \cu_wrmask_o + connect \Y $not$issuer_ls180.v:135772$6596_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" + cell $not $not$issuer_ls180.v:135775$6599 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$23 + connect \Y $not$issuer_ls180.v:135775$6599_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" + cell $not $not$issuer_ls180.v:135781$6605 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \alu_mul0_n_ready_i + connect \Y $not$issuer_ls180.v:135781$6605_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" + cell $not $not$issuer_ls180.v:135792$6616 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \cu_rd__rel_o + connect \Y $not$issuer_ls180.v:135792$6616_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:173" + cell $not $not$issuer_ls180.v:135812$6636 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \alu_mul0_mul_op__imm_data__ok + connect \Y $not$issuer_ls180.v:135812$6636_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" + cell $not $not$issuer_ls180.v:135814$6638 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \cu_rdmaskn_i + connect \Y $not$issuer_ls180.v:135814$6638_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" + cell $or $or$issuer_ls180.v:135780$6604 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$32 + connect \B \$34 + connect \Y $or$issuer_ls180.v:135780$6604_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:230" + cell $or $or$issuer_ls180.v:135790$6614 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \req_done + connect \B \cu_go_die_i + connect \Y $or$issuer_ls180.v:135790$6614_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:231" + cell $or $or$issuer_ls180.v:135791$6615 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cu_issue_i + connect \B \cu_go_die_i + connect \Y $or$issuer_ls180.v:135791$6615_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:232" + cell $or $or$issuer_ls180.v:135793$6617 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \cu_wr__go_i + connect \B { \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i } + connect \Y $or$issuer_ls180.v:135793$6617_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:233" + cell $or $or$issuer_ls180.v:135794$6618 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \cu_rd__go_i + connect \B { \cu_go_die_i \cu_go_die_i \cu_go_die_i } + connect \Y $or$issuer_ls180.v:135794$6618_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:253" + cell $or $or$issuer_ls180.v:135797$6621 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \reset_w + connect \B \prev_wr_go + connect \Y $or$issuer_ls180.v:135797$6621_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" + cell $or $or$issuer_ls180.v:135803$6627 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \$5 + connect \B \cu_rd__go_i + connect \Y $or$issuer_ls180.v:135803$6627_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" + cell $reduce_and $reduce_and$issuer_ls180.v:135809$6633 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \$7 + connect \Y $reduce_and$issuer_ls180.v:135809$6633_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" + cell $reduce_or $reduce_or$issuer_ls180.v:135774$6598 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \$26 + connect \Y $reduce_or$issuer_ls180.v:135774$6598_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" + cell $reduce_or $reduce_or$issuer_ls180.v:135778$6602 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \cu_wr__go_i + connect \Y $reduce_or$issuer_ls180.v:135778$6602_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" + cell $reduce_or $reduce_or$issuer_ls180.v:135779$6603 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \prev_wr_go + connect \Y $reduce_or$issuer_ls180.v:135779$6603_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:168" + cell $mux $ternary$issuer_ls180.v:135802$6626 + parameter \WIDTH 1 + connect \A \src_l_q_src [1] + connect \B \opc_l_q_opc + connect \S \alu_mul0_mul_op__imm_data__ok + connect \Y $ternary$issuer_ls180.v:135802$6626_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:169" + cell $mux $ternary$issuer_ls180.v:135804$6628 + parameter \WIDTH 64 + connect \A \src2_i + connect \B \alu_mul0_mul_op__imm_data__data + connect \S \alu_mul0_mul_op__imm_data__ok + connect \Y $ternary$issuer_ls180.v:135804$6628_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + cell $mux $ternary$issuer_ls180.v:135805$6629 + parameter \WIDTH 64 + connect \A \src_r0 + connect \B \src1_i + connect \S \src_l_q_src [0] + connect \Y $ternary$issuer_ls180.v:135805$6629_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + cell $mux $ternary$issuer_ls180.v:135806$6630 + parameter \WIDTH 64 + connect \A \src_r1 + connect \B \src_or_imm + connect \S \src_sel + connect \Y $ternary$issuer_ls180.v:135806$6630_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + cell $mux $ternary$issuer_ls180.v:135807$6631 + parameter \WIDTH 1 + connect \A \src_r2 + connect \B \src3_i + connect \S \src_l_q_src [2] + connect \Y $ternary$issuer_ls180.v:135807$6631_Y + end + attribute \module_not_derived 1 + attribute \src "issuer_ls180.v:135891.15-135897.4" + cell \alu_l$104 \alu_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_alu \alu_l_q_alu + connect \r_alu \alu_l_r_alu + connect \s_alu \alu_l_s_alu + end + attribute \module_not_derived 1 + attribute \src "issuer_ls180.v:135898.12-135928.4" + cell \alu_mul0 \alu_mul0 + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \cr_a \alu_mul0_cr_a + connect \cr_a_ok \cr_a_ok + connect \mul_op__fn_unit \alu_mul0_mul_op__fn_unit + connect \mul_op__imm_data__data \alu_mul0_mul_op__imm_data__data + connect \mul_op__imm_data__ok \alu_mul0_mul_op__imm_data__ok + connect \mul_op__insn \alu_mul0_mul_op__insn + connect \mul_op__insn_type \alu_mul0_mul_op__insn_type + connect \mul_op__is_32bit \alu_mul0_mul_op__is_32bit + connect \mul_op__is_signed \alu_mul0_mul_op__is_signed + connect \mul_op__oe__oe \alu_mul0_mul_op__oe__oe + connect \mul_op__oe__ok \alu_mul0_mul_op__oe__ok + connect \mul_op__rc__ok \alu_mul0_mul_op__rc__ok + connect \mul_op__rc__rc \alu_mul0_mul_op__rc__rc + connect \mul_op__write_cr0 \alu_mul0_mul_op__write_cr0 + connect \n_ready_i \alu_mul0_n_ready_i + connect \n_valid_o \alu_mul0_n_valid_o + connect \o \alu_mul0_o + connect \o_ok \o_ok + connect \p_ready_o \alu_mul0_p_ready_o + connect \p_valid_i \alu_mul0_p_valid_i + connect \ra \alu_mul0_ra + connect \rb \alu_mul0_rb + connect \xer_ov \alu_mul0_xer_ov + connect \xer_ov_ok \xer_ov_ok + connect \xer_so \alu_mul0_xer_so + connect \xer_so$1 \alu_mul0_xer_so$1 + connect \xer_so_ok \xer_so_ok + end + attribute \module_not_derived 1 + attribute \src "issuer_ls180.v:135929.16-135935.4" + cell \alui_l$103 \alui_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_alui \alui_l_q_alui + connect \r_alui \alui_l_r_alui + connect \s_alui \alui_l_s_alui + end + attribute \module_not_derived 1 + attribute \src "issuer_ls180.v:135936.14-135942.4" + cell \opc_l$99 \opc_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_opc \opc_l_q_opc + connect \r_opc \opc_l_r_opc + connect \s_opc \opc_l_s_opc + end + attribute \module_not_derived 1 + attribute \src "issuer_ls180.v:135943.15-135949.4" + cell \req_l$100 \req_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_req \req_l_q_req + connect \r_req \req_l_r_req + connect \s_req \req_l_s_req + end + attribute \module_not_derived 1 + attribute \src "issuer_ls180.v:135950.15-135956.4" + cell \rok_l$102 \rok_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_rdok \rok_l_q_rdok + connect \r_rdok \rok_l_r_rdok + connect \s_rdok \rok_l_s_rdok + end + attribute \module_not_derived 1 + attribute \src "issuer_ls180.v:135957.15-135962.4" + cell \rst_l$101 \rst_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \r_rst \rst_l_r_rst + connect \s_rst \rst_l_s_rst + end + attribute \module_not_derived 1 + attribute \src "issuer_ls180.v:135963.14-135969.4" + cell \src_l$98 \src_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_src \src_l_q_src + connect \r_src \src_l_r_src + connect \s_src \src_l_s_src + end + attribute \src "issuer_ls180.v:135164.7-135164.20" + process $proc$issuer_ls180.v:135164$6793 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "issuer_ls180.v:135288.7-135288.24" + process $proc$issuer_ls180.v:135288$6794 + assign { } { } + assign $1\all_rd_dly[0:0] 1'0 + sync always + sync init + update \all_rd_dly $1\all_rd_dly[0:0] + end + attribute \src "issuer_ls180.v:135298.7-135298.26" + process $proc$issuer_ls180.v:135298$6795 + assign { } { } + assign $1\alu_done_dly[0:0] 1'0 + sync always + sync init + update \alu_done_dly $1\alu_done_dly[0:0] + end + attribute \src "issuer_ls180.v:135306.7-135306.25" + process $proc$issuer_ls180.v:135306$6796 + assign { } { } + assign $1\alu_l_r_alu[0:0] 1'1 + sync always + sync init + update \alu_l_r_alu $1\alu_l_r_alu[0:0] + end + attribute \src "issuer_ls180.v:135327.14-135327.48" + process $proc$issuer_ls180.v:135327$6797 + assign { } { } + assign $1\alu_mul0_mul_op__fn_unit[11:0] 12'000000000000 + sync always + sync init + update \alu_mul0_mul_op__fn_unit $1\alu_mul0_mul_op__fn_unit[11:0] + end + attribute \src "issuer_ls180.v:135331.14-135331.68" + process $proc$issuer_ls180.v:135331$6798 + assign { } { } + assign $1\alu_mul0_mul_op__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \alu_mul0_mul_op__imm_data__data $1\alu_mul0_mul_op__imm_data__data[63:0] + end + attribute \src "issuer_ls180.v:135335.7-135335.43" + process $proc$issuer_ls180.v:135335$6799 + assign { } { } + assign $1\alu_mul0_mul_op__imm_data__ok[0:0] 1'0 + sync always + sync init + update \alu_mul0_mul_op__imm_data__ok $1\alu_mul0_mul_op__imm_data__ok[0:0] + end + attribute \src "issuer_ls180.v:135339.14-135339.43" + process $proc$issuer_ls180.v:135339$6800 + assign { } { } + assign $1\alu_mul0_mul_op__insn[31:0] 0 + sync always + sync init + update \alu_mul0_mul_op__insn $1\alu_mul0_mul_op__insn[31:0] + end + attribute \src "issuer_ls180.v:135417.13-135417.47" + process $proc$issuer_ls180.v:135417$6801 + assign { } { } + assign $1\alu_mul0_mul_op__insn_type[6:0] 7'0000000 + sync always + sync init + update \alu_mul0_mul_op__insn_type $1\alu_mul0_mul_op__insn_type[6:0] + end + attribute \src "issuer_ls180.v:135421.7-135421.39" + process $proc$issuer_ls180.v:135421$6802 + assign { } { } + assign $1\alu_mul0_mul_op__is_32bit[0:0] 1'0 + sync always + sync init + update \alu_mul0_mul_op__is_32bit $1\alu_mul0_mul_op__is_32bit[0:0] + end + attribute \src "issuer_ls180.v:135425.7-135425.40" + process $proc$issuer_ls180.v:135425$6803 + assign { } { } + assign $1\alu_mul0_mul_op__is_signed[0:0] 1'0 + sync always + sync init + update \alu_mul0_mul_op__is_signed $1\alu_mul0_mul_op__is_signed[0:0] + end + attribute \src "issuer_ls180.v:135429.7-135429.37" + process $proc$issuer_ls180.v:135429$6804 + assign { } { } + assign $1\alu_mul0_mul_op__oe__oe[0:0] 1'0 + sync always + sync init + update \alu_mul0_mul_op__oe__oe $1\alu_mul0_mul_op__oe__oe[0:0] + end + attribute \src "issuer_ls180.v:135433.7-135433.37" + process $proc$issuer_ls180.v:135433$6805 + assign { } { } + assign $1\alu_mul0_mul_op__oe__ok[0:0] 1'0 + sync always + sync init + update \alu_mul0_mul_op__oe__ok $1\alu_mul0_mul_op__oe__ok[0:0] + end + attribute \src "issuer_ls180.v:135437.7-135437.37" + process $proc$issuer_ls180.v:135437$6806 + assign { } { } + assign $1\alu_mul0_mul_op__rc__ok[0:0] 1'0 + sync always + sync init + update \alu_mul0_mul_op__rc__ok $1\alu_mul0_mul_op__rc__ok[0:0] + end + attribute \src "issuer_ls180.v:135441.7-135441.37" + process $proc$issuer_ls180.v:135441$6807 + assign { } { } + assign $1\alu_mul0_mul_op__rc__rc[0:0] 1'0 + sync always + sync init + update \alu_mul0_mul_op__rc__rc $1\alu_mul0_mul_op__rc__rc[0:0] + end + attribute \src "issuer_ls180.v:135445.7-135445.40" + process $proc$issuer_ls180.v:135445$6808 + assign { } { } + assign $1\alu_mul0_mul_op__write_cr0[0:0] 1'0 + sync always + sync init + update \alu_mul0_mul_op__write_cr0 $1\alu_mul0_mul_op__write_cr0[0:0] + end + attribute \src "issuer_ls180.v:135475.7-135475.27" + process $proc$issuer_ls180.v:135475$6809 + assign { } { } + assign $1\alui_l_r_alui[0:0] 1'1 + sync always + sync init + update \alui_l_r_alui $1\alui_l_r_alui[0:0] + end + attribute \src "issuer_ls180.v:135509.14-135509.47" + process $proc$issuer_ls180.v:135509$6810 + assign { } { } + assign $1\data_r0__o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \data_r0__o $1\data_r0__o[63:0] + end + attribute \src "issuer_ls180.v:135513.7-135513.27" + process $proc$issuer_ls180.v:135513$6811 + assign { } { } + assign $1\data_r0__o_ok[0:0] 1'0 + sync always + sync init + update \data_r0__o_ok $1\data_r0__o_ok[0:0] + end + attribute \src "issuer_ls180.v:135517.13-135517.33" + process $proc$issuer_ls180.v:135517$6812 + assign { } { } + assign $1\data_r1__cr_a[3:0] 4'0000 + sync always + sync init + update \data_r1__cr_a $1\data_r1__cr_a[3:0] + end + attribute \src "issuer_ls180.v:135521.7-135521.30" + process $proc$issuer_ls180.v:135521$6813 + assign { } { } + assign $1\data_r1__cr_a_ok[0:0] 1'0 + sync always + sync init + update \data_r1__cr_a_ok $1\data_r1__cr_a_ok[0:0] + end + attribute \src "issuer_ls180.v:135525.13-135525.35" + process $proc$issuer_ls180.v:135525$6814 + assign { } { } + assign $1\data_r2__xer_ov[1:0] 2'00 + sync always + sync init + update \data_r2__xer_ov $1\data_r2__xer_ov[1:0] + end + attribute \src "issuer_ls180.v:135529.7-135529.32" + process $proc$issuer_ls180.v:135529$6815 + assign { } { } + assign $1\data_r2__xer_ov_ok[0:0] 1'0 + sync always + sync init + update \data_r2__xer_ov_ok $1\data_r2__xer_ov_ok[0:0] + end + attribute \src "issuer_ls180.v:135533.7-135533.29" + process $proc$issuer_ls180.v:135533$6816 + assign { } { } + assign $1\data_r3__xer_so[0:0] 1'0 + sync always + sync init + update \data_r3__xer_so $1\data_r3__xer_so[0:0] + end + attribute \src "issuer_ls180.v:135537.7-135537.32" + process $proc$issuer_ls180.v:135537$6817 + assign { } { } + assign $1\data_r3__xer_so_ok[0:0] 1'0 + sync always + sync init + update \data_r3__xer_so_ok $1\data_r3__xer_so_ok[0:0] + end + attribute \src "issuer_ls180.v:135557.7-135557.25" + process $proc$issuer_ls180.v:135557$6818 + assign { } { } + assign $1\opc_l_r_opc[0:0] 1'1 + sync always + sync init + update \opc_l_r_opc $1\opc_l_r_opc[0:0] + end + attribute \src "issuer_ls180.v:135561.7-135561.25" + process $proc$issuer_ls180.v:135561$6819 + assign { } { } + assign $1\opc_l_s_opc[0:0] 1'0 + sync always + sync init + update \opc_l_s_opc $1\opc_l_s_opc[0:0] + end + attribute \src "issuer_ls180.v:135676.13-135676.30" + process $proc$issuer_ls180.v:135676$6820 + assign { } { } + assign $1\prev_wr_go[3:0] 4'0000 + sync always + sync init + update \prev_wr_go $1\prev_wr_go[3:0] + end + attribute \src "issuer_ls180.v:135684.13-135684.31" + process $proc$issuer_ls180.v:135684$6821 + assign { } { } + assign $1\req_l_r_req[3:0] 4'1111 + sync always + sync init + update \req_l_r_req $1\req_l_r_req[3:0] + end + attribute \src "issuer_ls180.v:135688.13-135688.31" + process $proc$issuer_ls180.v:135688$6822 + assign { } { } + assign $1\req_l_s_req[3:0] 4'0000 + sync always + sync init + update \req_l_s_req $1\req_l_s_req[3:0] + end + attribute \src "issuer_ls180.v:135700.7-135700.26" + process $proc$issuer_ls180.v:135700$6823 + assign { } { } + assign $1\rok_l_r_rdok[0:0] 1'1 + sync always + sync init + update \rok_l_r_rdok $1\rok_l_r_rdok[0:0] + end + attribute \src "issuer_ls180.v:135704.7-135704.26" + process $proc$issuer_ls180.v:135704$6824 + assign { } { } + assign $1\rok_l_s_rdok[0:0] 1'0 + sync always + sync init + update \rok_l_s_rdok $1\rok_l_s_rdok[0:0] + end + attribute \src "issuer_ls180.v:135708.7-135708.25" + process $proc$issuer_ls180.v:135708$6825 + assign { } { } + assign $1\rst_l_r_rst[0:0] 1'1 + sync always + sync init + update \rst_l_r_rst $1\rst_l_r_rst[0:0] + end + attribute \src "issuer_ls180.v:135712.7-135712.25" + process $proc$issuer_ls180.v:135712$6826 + assign { } { } + assign $1\rst_l_s_rst[0:0] 1'0 + sync always + sync init + update \rst_l_s_rst $1\rst_l_s_rst[0:0] + end + attribute \src "issuer_ls180.v:135726.13-135726.31" + process $proc$issuer_ls180.v:135726$6827 + assign { } { } + assign $1\src_l_r_src[2:0] 3'111 + sync always + sync init + update \src_l_r_src $1\src_l_r_src[2:0] + end + attribute \src "issuer_ls180.v:135730.13-135730.31" + process $proc$issuer_ls180.v:135730$6828 + assign { } { } + assign $1\src_l_s_src[2:0] 3'000 + sync always + sync init + update \src_l_s_src $1\src_l_s_src[2:0] + end + attribute \src "issuer_ls180.v:135736.14-135736.43" + process $proc$issuer_ls180.v:135736$6829 + assign { } { } + assign $1\src_r0[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \src_r0 $1\src_r0[63:0] + end + attribute \src "issuer_ls180.v:135740.14-135740.43" + process $proc$issuer_ls180.v:135740$6830 + assign { } { } + assign $1\src_r1[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \src_r1 $1\src_r1[63:0] + end + attribute \src "issuer_ls180.v:135744.7-135744.20" + process $proc$issuer_ls180.v:135744$6831 + assign { } { } + assign $1\src_r2[0:0] 1'0 + sync always + sync init + update \src_r2 $1\src_r2[0:0] + end + attribute \src "issuer_ls180.v:135815.3-135816.39" + process $proc$issuer_ls180.v:135815$6639 + assign { } { } + assign $0\alu_l_r_alu[0:0] \alu_l_r_alu$next + sync posedge \coresync_clk + update \alu_l_r_alu $0\alu_l_r_alu[0:0] + end + attribute \src "issuer_ls180.v:135817.3-135818.43" + process $proc$issuer_ls180.v:135817$6640 + assign { } { } + assign $0\alui_l_r_alui[0:0] \alui_l_r_alui$next + sync posedge \coresync_clk + update \alui_l_r_alui $0\alui_l_r_alui[0:0] + end + attribute \src "issuer_ls180.v:135819.3-135820.29" + process $proc$issuer_ls180.v:135819$6641 + assign { } { } + assign $0\src_r2[0:0] \src_r2$next + sync posedge \coresync_clk + update \src_r2 $0\src_r2[0:0] + end + attribute \src "issuer_ls180.v:135821.3-135822.29" + process $proc$issuer_ls180.v:135821$6642 + assign { } { } + assign $0\src_r1[63:0] \src_r1$next + sync posedge \coresync_clk + update \src_r1 $0\src_r1[63:0] + end + attribute \src "issuer_ls180.v:135823.3-135824.29" + process $proc$issuer_ls180.v:135823$6643 + assign { } { } + assign $0\src_r0[63:0] \src_r0$next + sync posedge \coresync_clk + update \src_r0 $0\src_r0[63:0] + end + attribute \src "issuer_ls180.v:135825.3-135826.47" + process $proc$issuer_ls180.v:135825$6644 + assign { } { } + assign $0\data_r3__xer_so[0:0] \data_r3__xer_so$next + sync posedge \coresync_clk + update \data_r3__xer_so $0\data_r3__xer_so[0:0] + end + attribute \src "issuer_ls180.v:135827.3-135828.53" + process $proc$issuer_ls180.v:135827$6645 + assign { } { } + assign $0\data_r3__xer_so_ok[0:0] \data_r3__xer_so_ok$next + sync posedge \coresync_clk + update \data_r3__xer_so_ok $0\data_r3__xer_so_ok[0:0] + end + attribute \src "issuer_ls180.v:135829.3-135830.47" + process $proc$issuer_ls180.v:135829$6646 + assign { } { } + assign $0\data_r2__xer_ov[1:0] \data_r2__xer_ov$next + sync posedge \coresync_clk + update \data_r2__xer_ov $0\data_r2__xer_ov[1:0] + end + attribute \src "issuer_ls180.v:135831.3-135832.53" + process $proc$issuer_ls180.v:135831$6647 + assign { } { } + assign $0\data_r2__xer_ov_ok[0:0] \data_r2__xer_ov_ok$next + sync posedge \coresync_clk + update \data_r2__xer_ov_ok $0\data_r2__xer_ov_ok[0:0] + end + attribute \src "issuer_ls180.v:135833.3-135834.43" + process $proc$issuer_ls180.v:135833$6648 + assign { } { } + assign $0\data_r1__cr_a[3:0] \data_r1__cr_a$next + sync posedge \coresync_clk + update \data_r1__cr_a $0\data_r1__cr_a[3:0] + end + attribute \src "issuer_ls180.v:135835.3-135836.49" + process $proc$issuer_ls180.v:135835$6649 + assign { } { } + assign $0\data_r1__cr_a_ok[0:0] \data_r1__cr_a_ok$next + sync posedge \coresync_clk + update \data_r1__cr_a_ok $0\data_r1__cr_a_ok[0:0] + end + attribute \src "issuer_ls180.v:135837.3-135838.37" + process $proc$issuer_ls180.v:135837$6650 + assign { } { } + assign $0\data_r0__o[63:0] \data_r0__o$next + sync posedge \coresync_clk + update \data_r0__o $0\data_r0__o[63:0] + end + attribute \src "issuer_ls180.v:135839.3-135840.43" + process $proc$issuer_ls180.v:135839$6651 + assign { } { } + assign $0\data_r0__o_ok[0:0] \data_r0__o_ok$next + sync posedge \coresync_clk + update \data_r0__o_ok $0\data_r0__o_ok[0:0] + end + attribute \src "issuer_ls180.v:135841.3-135842.69" + process $proc$issuer_ls180.v:135841$6652 + assign { } { } + assign $0\alu_mul0_mul_op__insn_type[6:0] \alu_mul0_mul_op__insn_type$next + sync posedge \coresync_clk + update \alu_mul0_mul_op__insn_type $0\alu_mul0_mul_op__insn_type[6:0] + end + attribute \src "issuer_ls180.v:135843.3-135844.65" + process $proc$issuer_ls180.v:135843$6653 + assign { } { } + assign $0\alu_mul0_mul_op__fn_unit[11:0] \alu_mul0_mul_op__fn_unit$next + sync posedge \coresync_clk + update \alu_mul0_mul_op__fn_unit $0\alu_mul0_mul_op__fn_unit[11:0] + end + attribute \src "issuer_ls180.v:135845.3-135846.79" + process $proc$issuer_ls180.v:135845$6654 + assign { } { } + assign $0\alu_mul0_mul_op__imm_data__data[63:0] \alu_mul0_mul_op__imm_data__data$next + sync posedge \coresync_clk + update \alu_mul0_mul_op__imm_data__data $0\alu_mul0_mul_op__imm_data__data[63:0] + end + attribute \src "issuer_ls180.v:135847.3-135848.75" + process $proc$issuer_ls180.v:135847$6655 + assign { } { } + assign $0\alu_mul0_mul_op__imm_data__ok[0:0] \alu_mul0_mul_op__imm_data__ok$next + sync posedge \coresync_clk + update \alu_mul0_mul_op__imm_data__ok $0\alu_mul0_mul_op__imm_data__ok[0:0] + end + attribute \src "issuer_ls180.v:135849.3-135850.63" + process $proc$issuer_ls180.v:135849$6656 + assign { } { } + assign $0\alu_mul0_mul_op__rc__rc[0:0] \alu_mul0_mul_op__rc__rc$next + sync posedge \coresync_clk + update \alu_mul0_mul_op__rc__rc $0\alu_mul0_mul_op__rc__rc[0:0] + end + attribute \src "issuer_ls180.v:135851.3-135852.63" + process $proc$issuer_ls180.v:135851$6657 + assign { } { } + assign $0\alu_mul0_mul_op__rc__ok[0:0] \alu_mul0_mul_op__rc__ok$next + sync posedge \coresync_clk + update \alu_mul0_mul_op__rc__ok $0\alu_mul0_mul_op__rc__ok[0:0] + end + attribute \src "issuer_ls180.v:135853.3-135854.63" + process $proc$issuer_ls180.v:135853$6658 + assign { } { } + assign $0\alu_mul0_mul_op__oe__oe[0:0] \alu_mul0_mul_op__oe__oe$next + sync posedge \coresync_clk + update \alu_mul0_mul_op__oe__oe $0\alu_mul0_mul_op__oe__oe[0:0] + end + attribute \src "issuer_ls180.v:135855.3-135856.63" + process $proc$issuer_ls180.v:135855$6659 + assign { } { } + assign $0\alu_mul0_mul_op__oe__ok[0:0] \alu_mul0_mul_op__oe__ok$next + sync posedge \coresync_clk + update \alu_mul0_mul_op__oe__ok $0\alu_mul0_mul_op__oe__ok[0:0] + end + attribute \src "issuer_ls180.v:135857.3-135858.69" + process $proc$issuer_ls180.v:135857$6660 + assign { } { } + assign $0\alu_mul0_mul_op__write_cr0[0:0] \alu_mul0_mul_op__write_cr0$next + sync posedge \coresync_clk + update \alu_mul0_mul_op__write_cr0 $0\alu_mul0_mul_op__write_cr0[0:0] + end + attribute \src "issuer_ls180.v:135859.3-135860.67" + process $proc$issuer_ls180.v:135859$6661 + assign { } { } + assign $0\alu_mul0_mul_op__is_32bit[0:0] \alu_mul0_mul_op__is_32bit$next + sync posedge \coresync_clk + update \alu_mul0_mul_op__is_32bit $0\alu_mul0_mul_op__is_32bit[0:0] + end + attribute \src "issuer_ls180.v:135861.3-135862.69" + process $proc$issuer_ls180.v:135861$6662 + assign { } { } + assign $0\alu_mul0_mul_op__is_signed[0:0] \alu_mul0_mul_op__is_signed$next + sync posedge \coresync_clk + update \alu_mul0_mul_op__is_signed $0\alu_mul0_mul_op__is_signed[0:0] + end + attribute \src "issuer_ls180.v:135863.3-135864.59" + process $proc$issuer_ls180.v:135863$6663 + assign { } { } + assign $0\alu_mul0_mul_op__insn[31:0] \alu_mul0_mul_op__insn$next + sync posedge \coresync_clk + update \alu_mul0_mul_op__insn $0\alu_mul0_mul_op__insn[31:0] + end + attribute \src "issuer_ls180.v:135865.3-135866.39" + process $proc$issuer_ls180.v:135865$6664 + assign { } { } + assign $0\req_l_r_req[3:0] \req_l_r_req$next + sync posedge \coresync_clk + update \req_l_r_req $0\req_l_r_req[3:0] + end + attribute \src "issuer_ls180.v:135867.3-135868.39" + process $proc$issuer_ls180.v:135867$6665 + assign { } { } + assign $0\req_l_s_req[3:0] \req_l_s_req$next + sync posedge \coresync_clk + update \req_l_s_req $0\req_l_s_req[3:0] + end + attribute \src "issuer_ls180.v:135869.3-135870.39" + process $proc$issuer_ls180.v:135869$6666 + assign { } { } + assign $0\src_l_r_src[2:0] \src_l_r_src$next + sync posedge \coresync_clk + update \src_l_r_src $0\src_l_r_src[2:0] + end + attribute \src "issuer_ls180.v:135871.3-135872.39" + process $proc$issuer_ls180.v:135871$6667 + assign { } { } + assign $0\src_l_s_src[2:0] \src_l_s_src$next + sync posedge \coresync_clk + update \src_l_s_src $0\src_l_s_src[2:0] + end + attribute \src "issuer_ls180.v:135873.3-135874.39" + process $proc$issuer_ls180.v:135873$6668 + assign { } { } + assign $0\opc_l_r_opc[0:0] \opc_l_r_opc$next + sync posedge \coresync_clk + update \opc_l_r_opc $0\opc_l_r_opc[0:0] + end + attribute \src "issuer_ls180.v:135875.3-135876.39" + process $proc$issuer_ls180.v:135875$6669 + assign { } { } + assign $0\opc_l_s_opc[0:0] \opc_l_s_opc$next + sync posedge \coresync_clk + update \opc_l_s_opc $0\opc_l_s_opc[0:0] + end + attribute \src "issuer_ls180.v:135877.3-135878.39" + process $proc$issuer_ls180.v:135877$6670 + assign { } { } + assign $0\rst_l_r_rst[0:0] \rst_l_r_rst$next + sync posedge \coresync_clk + update \rst_l_r_rst $0\rst_l_r_rst[0:0] + end + attribute \src "issuer_ls180.v:135879.3-135880.39" + process $proc$issuer_ls180.v:135879$6671 + assign { } { } + assign $0\rst_l_s_rst[0:0] \rst_l_s_rst$next + sync posedge \coresync_clk + update \rst_l_s_rst $0\rst_l_s_rst[0:0] + end + attribute \src "issuer_ls180.v:135881.3-135882.41" + process $proc$issuer_ls180.v:135881$6672 + assign { } { } + assign $0\rok_l_r_rdok[0:0] \rok_l_r_rdok$next + sync posedge \coresync_clk + update \rok_l_r_rdok $0\rok_l_r_rdok[0:0] + end + attribute \src "issuer_ls180.v:135883.3-135884.41" + process $proc$issuer_ls180.v:135883$6673 + assign { } { } + assign $0\rok_l_s_rdok[0:0] \rok_l_s_rdok$next + sync posedge \coresync_clk + update \rok_l_s_rdok $0\rok_l_s_rdok[0:0] + end + attribute \src "issuer_ls180.v:135885.3-135886.37" + process $proc$issuer_ls180.v:135885$6674 + assign { } { } + assign $0\prev_wr_go[3:0] \prev_wr_go$next + sync posedge \coresync_clk + update \prev_wr_go $0\prev_wr_go[3:0] + end + attribute \src "issuer_ls180.v:135887.3-135888.40" + process $proc$issuer_ls180.v:135887$6675 + assign { } { } + assign $0\alu_done_dly[0:0] \alu_mul0_n_valid_o + sync posedge \coresync_clk + update \alu_done_dly $0\alu_done_dly[0:0] + end + attribute \src "issuer_ls180.v:135889.3-135890.25" + process $proc$issuer_ls180.v:135889$6676 + assign { } { } + assign $0\all_rd_dly[0:0] \$10 + sync posedge \coresync_clk + update \all_rd_dly $0\all_rd_dly[0:0] + end + attribute \src "issuer_ls180.v:135970.3-135979.6" + process $proc$issuer_ls180.v:135970$6677 + assign { } { } + assign { } { } + assign $0\req_done[0:0] $1\req_done[0:0] + attribute \src "issuer_ls180.v:135971.5-135971.29" + switch \initial + attribute \src "issuer_ls180.v:135971.9-135971.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" + switch \$54 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\req_done[0:0] 1'1 + case + assign $1\req_done[0:0] \$46 + end + sync always + update \req_done $0\req_done[0:0] + end + attribute \src "issuer_ls180.v:135980.3-135988.6" + process $proc$issuer_ls180.v:135980$6678 + assign { } { } + assign { } { } + assign $0\rok_l_s_rdok$next[0:0]$6679 $1\rok_l_s_rdok$next[0:0]$6680 + attribute \src "issuer_ls180.v:135981.5-135981.29" + switch \initial + attribute \src "issuer_ls180.v:135981.9-135981.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\rok_l_s_rdok$next[0:0]$6680 1'0 + case + assign $1\rok_l_s_rdok$next[0:0]$6680 \cu_issue_i + end + sync always + update \rok_l_s_rdok$next $0\rok_l_s_rdok$next[0:0]$6679 + end + attribute \src "issuer_ls180.v:135989.3-135997.6" + process $proc$issuer_ls180.v:135989$6681 + assign { } { } + assign { } { } + assign $0\rok_l_r_rdok$next[0:0]$6682 $1\rok_l_r_rdok$next[0:0]$6683 + attribute \src "issuer_ls180.v:135990.5-135990.29" + switch \initial + attribute \src "issuer_ls180.v:135990.9-135990.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\rok_l_r_rdok$next[0:0]$6683 1'1 + case + assign $1\rok_l_r_rdok$next[0:0]$6683 \$64 + end + sync always + update \rok_l_r_rdok$next $0\rok_l_r_rdok$next[0:0]$6682 + end + attribute \src "issuer_ls180.v:135998.3-136006.6" + process $proc$issuer_ls180.v:135998$6684 + assign { } { } + assign { } { } + assign $0\rst_l_s_rst$next[0:0]$6685 $1\rst_l_s_rst$next[0:0]$6686 + attribute \src "issuer_ls180.v:135999.5-135999.29" + switch \initial + attribute \src "issuer_ls180.v:135999.9-135999.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\rst_l_s_rst$next[0:0]$6686 1'0 + case + assign $1\rst_l_s_rst$next[0:0]$6686 \all_rd + end + sync always + update \rst_l_s_rst$next $0\rst_l_s_rst$next[0:0]$6685 + end + attribute \src "issuer_ls180.v:136007.3-136015.6" + process $proc$issuer_ls180.v:136007$6687 + assign { } { } + assign { } { } + assign $0\rst_l_r_rst$next[0:0]$6688 $1\rst_l_r_rst$next[0:0]$6689 + attribute \src "issuer_ls180.v:136008.5-136008.29" + switch \initial + attribute \src "issuer_ls180.v:136008.9-136008.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\rst_l_r_rst$next[0:0]$6689 1'1 + case + assign $1\rst_l_r_rst$next[0:0]$6689 \rst_r + end + sync always + update \rst_l_r_rst$next $0\rst_l_r_rst$next[0:0]$6688 + end + attribute \src "issuer_ls180.v:136016.3-136024.6" + process $proc$issuer_ls180.v:136016$6690 + assign { } { } + assign { } { } + assign $0\opc_l_s_opc$next[0:0]$6691 $1\opc_l_s_opc$next[0:0]$6692 + attribute \src "issuer_ls180.v:136017.5-136017.29" + switch \initial + attribute \src "issuer_ls180.v:136017.9-136017.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\opc_l_s_opc$next[0:0]$6692 1'0 + case + assign $1\opc_l_s_opc$next[0:0]$6692 \cu_issue_i + end + sync always + update \opc_l_s_opc$next $0\opc_l_s_opc$next[0:0]$6691 + end + attribute \src "issuer_ls180.v:136025.3-136033.6" + process $proc$issuer_ls180.v:136025$6693 + assign { } { } + assign { } { } + assign $0\opc_l_r_opc$next[0:0]$6694 $1\opc_l_r_opc$next[0:0]$6695 + attribute \src "issuer_ls180.v:136026.5-136026.29" + switch \initial + attribute \src "issuer_ls180.v:136026.9-136026.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\opc_l_r_opc$next[0:0]$6695 1'1 + case + assign $1\opc_l_r_opc$next[0:0]$6695 \req_done + end + sync always + update \opc_l_r_opc$next $0\opc_l_r_opc$next[0:0]$6694 + end + attribute \src "issuer_ls180.v:136034.3-136042.6" + process $proc$issuer_ls180.v:136034$6696 + assign { } { } + assign { } { } + assign $0\src_l_s_src$next[2:0]$6697 $1\src_l_s_src$next[2:0]$6698 + attribute \src "issuer_ls180.v:136035.5-136035.29" + switch \initial + attribute \src "issuer_ls180.v:136035.9-136035.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\src_l_s_src$next[2:0]$6698 3'000 + case + assign $1\src_l_s_src$next[2:0]$6698 { \cu_issue_i \cu_issue_i \cu_issue_i } + end + sync always + update \src_l_s_src$next $0\src_l_s_src$next[2:0]$6697 + end + attribute \src "issuer_ls180.v:136043.3-136051.6" + process $proc$issuer_ls180.v:136043$6699 + assign { } { } + assign { } { } + assign $0\src_l_r_src$next[2:0]$6700 $1\src_l_r_src$next[2:0]$6701 + attribute \src "issuer_ls180.v:136044.5-136044.29" + switch \initial + attribute \src "issuer_ls180.v:136044.9-136044.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\src_l_r_src$next[2:0]$6701 3'111 + case + assign $1\src_l_r_src$next[2:0]$6701 \reset_r + end + sync always + update \src_l_r_src$next $0\src_l_r_src$next[2:0]$6700 + end + attribute \src "issuer_ls180.v:136052.3-136060.6" + process $proc$issuer_ls180.v:136052$6702 + assign { } { } + assign { } { } + assign $0\req_l_s_req$next[3:0]$6703 $1\req_l_s_req$next[3:0]$6704 + attribute \src "issuer_ls180.v:136053.5-136053.29" + switch \initial + attribute \src "issuer_ls180.v:136053.9-136053.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\req_l_s_req$next[3:0]$6704 4'0000 + case + assign $1\req_l_s_req$next[3:0]$6704 \$66 + end + sync always + update \req_l_s_req$next $0\req_l_s_req$next[3:0]$6703 + end + attribute \src "issuer_ls180.v:136061.3-136069.6" + process $proc$issuer_ls180.v:136061$6705 + assign { } { } + assign { } { } + assign $0\req_l_r_req$next[3:0]$6706 $1\req_l_r_req$next[3:0]$6707 + attribute \src "issuer_ls180.v:136062.5-136062.29" + switch \initial + attribute \src "issuer_ls180.v:136062.9-136062.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\req_l_r_req$next[3:0]$6707 4'1111 + case + assign $1\req_l_r_req$next[3:0]$6707 \$68 + end + sync always + update \req_l_r_req$next $0\req_l_r_req$next[3:0]$6706 + end + attribute \src "issuer_ls180.v:136070.3-136102.6" + process $proc$issuer_ls180.v:136070$6708 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\alu_mul0_mul_op__fn_unit$next[11:0]$6709 $1\alu_mul0_mul_op__fn_unit$next[11:0]$6721 + assign { } { } + assign { } { } + assign $0\alu_mul0_mul_op__insn$next[31:0]$6712 $1\alu_mul0_mul_op__insn$next[31:0]$6724 + assign $0\alu_mul0_mul_op__insn_type$next[6:0]$6713 $1\alu_mul0_mul_op__insn_type$next[6:0]$6725 + assign $0\alu_mul0_mul_op__is_32bit$next[0:0]$6714 $1\alu_mul0_mul_op__is_32bit$next[0:0]$6726 + assign $0\alu_mul0_mul_op__is_signed$next[0:0]$6715 $1\alu_mul0_mul_op__is_signed$next[0:0]$6727 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\alu_mul0_mul_op__write_cr0$next[0:0]$6720 $1\alu_mul0_mul_op__write_cr0$next[0:0]$6732 + assign $0\alu_mul0_mul_op__imm_data__data$next[63:0]$6710 $2\alu_mul0_mul_op__imm_data__data$next[63:0]$6733 + assign $0\alu_mul0_mul_op__imm_data__ok$next[0:0]$6711 $2\alu_mul0_mul_op__imm_data__ok$next[0:0]$6734 + assign $0\alu_mul0_mul_op__oe__oe$next[0:0]$6716 $2\alu_mul0_mul_op__oe__oe$next[0:0]$6735 + assign $0\alu_mul0_mul_op__oe__ok$next[0:0]$6717 $2\alu_mul0_mul_op__oe__ok$next[0:0]$6736 + assign $0\alu_mul0_mul_op__rc__ok$next[0:0]$6718 $2\alu_mul0_mul_op__rc__ok$next[0:0]$6737 + assign $0\alu_mul0_mul_op__rc__rc$next[0:0]$6719 $2\alu_mul0_mul_op__rc__rc$next[0:0]$6738 + attribute \src "issuer_ls180.v:136071.5-136071.29" + switch \initial + attribute \src "issuer_ls180.v:136071.9-136071.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:257" + switch \cu_issue_i + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { $1\alu_mul0_mul_op__insn$next[31:0]$6724 $1\alu_mul0_mul_op__is_signed$next[0:0]$6727 $1\alu_mul0_mul_op__is_32bit$next[0:0]$6726 $1\alu_mul0_mul_op__write_cr0$next[0:0]$6732 $1\alu_mul0_mul_op__oe__ok$next[0:0]$6729 $1\alu_mul0_mul_op__oe__oe$next[0:0]$6728 $1\alu_mul0_mul_op__rc__ok$next[0:0]$6730 $1\alu_mul0_mul_op__rc__rc$next[0:0]$6731 $1\alu_mul0_mul_op__imm_data__ok$next[0:0]$6723 $1\alu_mul0_mul_op__imm_data__data$next[63:0]$6722 $1\alu_mul0_mul_op__fn_unit$next[11:0]$6721 $1\alu_mul0_mul_op__insn_type$next[6:0]$6725 } { \oper_i_alu_mul0__insn \oper_i_alu_mul0__is_signed \oper_i_alu_mul0__is_32bit \oper_i_alu_mul0__write_cr0 \oper_i_alu_mul0__oe__ok \oper_i_alu_mul0__oe__oe \oper_i_alu_mul0__rc__ok \oper_i_alu_mul0__rc__rc \oper_i_alu_mul0__imm_data__ok \oper_i_alu_mul0__imm_data__data \oper_i_alu_mul0__fn_unit \oper_i_alu_mul0__insn_type } + case + assign $1\alu_mul0_mul_op__fn_unit$next[11:0]$6721 \alu_mul0_mul_op__fn_unit + assign $1\alu_mul0_mul_op__imm_data__data$next[63:0]$6722 \alu_mul0_mul_op__imm_data__data + assign $1\alu_mul0_mul_op__imm_data__ok$next[0:0]$6723 \alu_mul0_mul_op__imm_data__ok + assign $1\alu_mul0_mul_op__insn$next[31:0]$6724 \alu_mul0_mul_op__insn + assign $1\alu_mul0_mul_op__insn_type$next[6:0]$6725 \alu_mul0_mul_op__insn_type + assign $1\alu_mul0_mul_op__is_32bit$next[0:0]$6726 \alu_mul0_mul_op__is_32bit + assign $1\alu_mul0_mul_op__is_signed$next[0:0]$6727 \alu_mul0_mul_op__is_signed + assign $1\alu_mul0_mul_op__oe__oe$next[0:0]$6728 \alu_mul0_mul_op__oe__oe + assign $1\alu_mul0_mul_op__oe__ok$next[0:0]$6729 \alu_mul0_mul_op__oe__ok + assign $1\alu_mul0_mul_op__rc__ok$next[0:0]$6730 \alu_mul0_mul_op__rc__ok + assign $1\alu_mul0_mul_op__rc__rc$next[0:0]$6731 \alu_mul0_mul_op__rc__rc + assign $1\alu_mul0_mul_op__write_cr0$next[0:0]$6732 \alu_mul0_mul_op__write_cr0 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $2\alu_mul0_mul_op__imm_data__data$next[63:0]$6733 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\alu_mul0_mul_op__imm_data__ok$next[0:0]$6734 1'0 + assign $2\alu_mul0_mul_op__rc__rc$next[0:0]$6738 1'0 + assign $2\alu_mul0_mul_op__rc__ok$next[0:0]$6737 1'0 + assign $2\alu_mul0_mul_op__oe__oe$next[0:0]$6735 1'0 + assign $2\alu_mul0_mul_op__oe__ok$next[0:0]$6736 1'0 + case + assign $2\alu_mul0_mul_op__imm_data__data$next[63:0]$6733 $1\alu_mul0_mul_op__imm_data__data$next[63:0]$6722 + assign $2\alu_mul0_mul_op__imm_data__ok$next[0:0]$6734 $1\alu_mul0_mul_op__imm_data__ok$next[0:0]$6723 + assign $2\alu_mul0_mul_op__oe__oe$next[0:0]$6735 $1\alu_mul0_mul_op__oe__oe$next[0:0]$6728 + assign $2\alu_mul0_mul_op__oe__ok$next[0:0]$6736 $1\alu_mul0_mul_op__oe__ok$next[0:0]$6729 + assign $2\alu_mul0_mul_op__rc__ok$next[0:0]$6737 $1\alu_mul0_mul_op__rc__ok$next[0:0]$6730 + assign $2\alu_mul0_mul_op__rc__rc$next[0:0]$6738 $1\alu_mul0_mul_op__rc__rc$next[0:0]$6731 + end + sync always + update \alu_mul0_mul_op__fn_unit$next $0\alu_mul0_mul_op__fn_unit$next[11:0]$6709 + update \alu_mul0_mul_op__imm_data__data$next $0\alu_mul0_mul_op__imm_data__data$next[63:0]$6710 + update \alu_mul0_mul_op__imm_data__ok$next $0\alu_mul0_mul_op__imm_data__ok$next[0:0]$6711 + update \alu_mul0_mul_op__insn$next $0\alu_mul0_mul_op__insn$next[31:0]$6712 + update \alu_mul0_mul_op__insn_type$next $0\alu_mul0_mul_op__insn_type$next[6:0]$6713 + update \alu_mul0_mul_op__is_32bit$next $0\alu_mul0_mul_op__is_32bit$next[0:0]$6714 + update \alu_mul0_mul_op__is_signed$next $0\alu_mul0_mul_op__is_signed$next[0:0]$6715 + update \alu_mul0_mul_op__oe__oe$next $0\alu_mul0_mul_op__oe__oe$next[0:0]$6716 + update \alu_mul0_mul_op__oe__ok$next $0\alu_mul0_mul_op__oe__ok$next[0:0]$6717 + update \alu_mul0_mul_op__rc__ok$next $0\alu_mul0_mul_op__rc__ok$next[0:0]$6718 + update \alu_mul0_mul_op__rc__rc$next $0\alu_mul0_mul_op__rc__rc$next[0:0]$6719 + update \alu_mul0_mul_op__write_cr0$next $0\alu_mul0_mul_op__write_cr0$next[0:0]$6720 + end + attribute \src "issuer_ls180.v:136103.3-136124.6" + process $proc$issuer_ls180.v:136103$6739 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\data_r0__o$next[63:0]$6740 $2\data_r0__o$next[63:0]$6744 + assign { } { } + assign $0\data_r0__o_ok$next[0:0]$6741 $3\data_r0__o_ok$next[0:0]$6746 + attribute \src "issuer_ls180.v:136104.5-136104.29" + switch \initial + attribute \src "issuer_ls180.v:136104.9-136104.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" + switch \alu_pulse + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $1\data_r0__o_ok$next[0:0]$6743 $1\data_r0__o$next[63:0]$6742 } { \o_ok \alu_mul0_o } + case + assign $1\data_r0__o$next[63:0]$6742 \data_r0__o + assign $1\data_r0__o_ok$next[0:0]$6743 \data_r0__o_ok + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" + switch \cu_issue_i + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $2\data_r0__o_ok$next[0:0]$6745 $2\data_r0__o$next[63:0]$6744 } 65'00000000000000000000000000000000000000000000000000000000000000000 + case + assign $2\data_r0__o$next[63:0]$6744 $1\data_r0__o$next[63:0]$6742 + assign $2\data_r0__o_ok$next[0:0]$6745 $1\data_r0__o_ok$next[0:0]$6743 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\data_r0__o_ok$next[0:0]$6746 1'0 + case + assign $3\data_r0__o_ok$next[0:0]$6746 $2\data_r0__o_ok$next[0:0]$6745 + end + sync always + update \data_r0__o$next $0\data_r0__o$next[63:0]$6740 + update \data_r0__o_ok$next $0\data_r0__o_ok$next[0:0]$6741 + end + attribute \src "issuer_ls180.v:136125.3-136146.6" + process $proc$issuer_ls180.v:136125$6747 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\data_r1__cr_a$next[3:0]$6748 $2\data_r1__cr_a$next[3:0]$6752 + assign { } { } + assign $0\data_r1__cr_a_ok$next[0:0]$6749 $3\data_r1__cr_a_ok$next[0:0]$6754 + attribute \src "issuer_ls180.v:136126.5-136126.29" + switch \initial + attribute \src "issuer_ls180.v:136126.9-136126.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" + switch \alu_pulse + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $1\data_r1__cr_a_ok$next[0:0]$6751 $1\data_r1__cr_a$next[3:0]$6750 } { \cr_a_ok \alu_mul0_cr_a } + case + assign $1\data_r1__cr_a$next[3:0]$6750 \data_r1__cr_a + assign $1\data_r1__cr_a_ok$next[0:0]$6751 \data_r1__cr_a_ok + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" + switch \cu_issue_i + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $2\data_r1__cr_a_ok$next[0:0]$6753 $2\data_r1__cr_a$next[3:0]$6752 } 5'00000 + case + assign $2\data_r1__cr_a$next[3:0]$6752 $1\data_r1__cr_a$next[3:0]$6750 + assign $2\data_r1__cr_a_ok$next[0:0]$6753 $1\data_r1__cr_a_ok$next[0:0]$6751 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\data_r1__cr_a_ok$next[0:0]$6754 1'0 + case + assign $3\data_r1__cr_a_ok$next[0:0]$6754 $2\data_r1__cr_a_ok$next[0:0]$6753 + end + sync always + update \data_r1__cr_a$next $0\data_r1__cr_a$next[3:0]$6748 + update \data_r1__cr_a_ok$next $0\data_r1__cr_a_ok$next[0:0]$6749 + end + attribute \src "issuer_ls180.v:136147.3-136168.6" + process $proc$issuer_ls180.v:136147$6755 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\data_r2__xer_ov$next[1:0]$6756 $2\data_r2__xer_ov$next[1:0]$6760 + assign { } { } + assign $0\data_r2__xer_ov_ok$next[0:0]$6757 $3\data_r2__xer_ov_ok$next[0:0]$6762 + attribute \src "issuer_ls180.v:136148.5-136148.29" + switch \initial + attribute \src "issuer_ls180.v:136148.9-136148.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" + switch \alu_pulse + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $1\data_r2__xer_ov_ok$next[0:0]$6759 $1\data_r2__xer_ov$next[1:0]$6758 } { \xer_ov_ok \alu_mul0_xer_ov } + case + assign $1\data_r2__xer_ov$next[1:0]$6758 \data_r2__xer_ov + assign $1\data_r2__xer_ov_ok$next[0:0]$6759 \data_r2__xer_ov_ok + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" + switch \cu_issue_i + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $2\data_r2__xer_ov_ok$next[0:0]$6761 $2\data_r2__xer_ov$next[1:0]$6760 } 3'000 + case + assign $2\data_r2__xer_ov$next[1:0]$6760 $1\data_r2__xer_ov$next[1:0]$6758 + assign $2\data_r2__xer_ov_ok$next[0:0]$6761 $1\data_r2__xer_ov_ok$next[0:0]$6759 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\data_r2__xer_ov_ok$next[0:0]$6762 1'0 + case + assign $3\data_r2__xer_ov_ok$next[0:0]$6762 $2\data_r2__xer_ov_ok$next[0:0]$6761 + end + sync always + update \data_r2__xer_ov$next $0\data_r2__xer_ov$next[1:0]$6756 + update \data_r2__xer_ov_ok$next $0\data_r2__xer_ov_ok$next[0:0]$6757 + end + attribute \src "issuer_ls180.v:136169.3-136190.6" + process $proc$issuer_ls180.v:136169$6763 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\data_r3__xer_so$next[0:0]$6764 $2\data_r3__xer_so$next[0:0]$6768 + assign { } { } + assign $0\data_r3__xer_so_ok$next[0:0]$6765 $3\data_r3__xer_so_ok$next[0:0]$6770 + attribute \src "issuer_ls180.v:136170.5-136170.29" + switch \initial + attribute \src "issuer_ls180.v:136170.9-136170.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" + switch \alu_pulse + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $1\data_r3__xer_so_ok$next[0:0]$6767 $1\data_r3__xer_so$next[0:0]$6766 } { \xer_so_ok \alu_mul0_xer_so } + case + assign $1\data_r3__xer_so$next[0:0]$6766 \data_r3__xer_so + assign $1\data_r3__xer_so_ok$next[0:0]$6767 \data_r3__xer_so_ok + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" + switch \cu_issue_i + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $2\data_r3__xer_so_ok$next[0:0]$6769 $2\data_r3__xer_so$next[0:0]$6768 } 2'00 + case + assign $2\data_r3__xer_so$next[0:0]$6768 $1\data_r3__xer_so$next[0:0]$6766 + assign $2\data_r3__xer_so_ok$next[0:0]$6769 $1\data_r3__xer_so_ok$next[0:0]$6767 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\data_r3__xer_so_ok$next[0:0]$6770 1'0 + case + assign $3\data_r3__xer_so_ok$next[0:0]$6770 $2\data_r3__xer_so_ok$next[0:0]$6769 + end + sync always + update \data_r3__xer_so$next $0\data_r3__xer_so$next[0:0]$6764 + update \data_r3__xer_so_ok$next $0\data_r3__xer_so_ok$next[0:0]$6765 + end + attribute \src "issuer_ls180.v:136191.3-136200.6" + process $proc$issuer_ls180.v:136191$6771 + assign { } { } + assign { } { } + assign $0\src_r0$next[63:0]$6772 $1\src_r0$next[63:0]$6773 + attribute \src "issuer_ls180.v:136192.5-136192.29" + switch \initial + attribute \src "issuer_ls180.v:136192.9-136192.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" + switch \src_l_q_src [0] + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\src_r0$next[63:0]$6773 \src1_i + case + assign $1\src_r0$next[63:0]$6773 \src_r0 + end + sync always + update \src_r0$next $0\src_r0$next[63:0]$6772 + end + attribute \src "issuer_ls180.v:136201.3-136210.6" + process $proc$issuer_ls180.v:136201$6774 + assign { } { } + assign { } { } + assign $0\src_r1$next[63:0]$6775 $1\src_r1$next[63:0]$6776 + attribute \src "issuer_ls180.v:136202.5-136202.29" + switch \initial + attribute \src "issuer_ls180.v:136202.9-136202.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" + switch \src_sel + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\src_r1$next[63:0]$6776 \src_or_imm + case + assign $1\src_r1$next[63:0]$6776 \src_r1 + end + sync always + update \src_r1$next $0\src_r1$next[63:0]$6775 + end + attribute \src "issuer_ls180.v:136211.3-136220.6" + process $proc$issuer_ls180.v:136211$6777 + assign { } { } + assign { } { } + assign $0\src_r2$next[0:0]$6778 $1\src_r2$next[0:0]$6779 + attribute \src "issuer_ls180.v:136212.5-136212.29" + switch \initial + attribute \src "issuer_ls180.v:136212.9-136212.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" + switch \src_l_q_src [2] + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\src_r2$next[0:0]$6779 \src3_i + case + assign $1\src_r2$next[0:0]$6779 \src_r2 + end + sync always + update \src_r2$next $0\src_r2$next[0:0]$6778 + end + attribute \src "issuer_ls180.v:136221.3-136229.6" + process $proc$issuer_ls180.v:136221$6780 + assign { } { } + assign { } { } + assign $0\alui_l_r_alui$next[0:0]$6781 $1\alui_l_r_alui$next[0:0]$6782 + attribute \src "issuer_ls180.v:136222.5-136222.29" + switch \initial + attribute \src "issuer_ls180.v:136222.9-136222.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\alui_l_r_alui$next[0:0]$6782 1'1 + case + assign $1\alui_l_r_alui$next[0:0]$6782 \$88 + end + sync always + update \alui_l_r_alui$next $0\alui_l_r_alui$next[0:0]$6781 + end + attribute \src "issuer_ls180.v:136230.3-136238.6" + process $proc$issuer_ls180.v:136230$6783 + assign { } { } + assign { } { } + assign $0\alu_l_r_alu$next[0:0]$6784 $1\alu_l_r_alu$next[0:0]$6785 + attribute \src "issuer_ls180.v:136231.5-136231.29" + switch \initial + attribute \src "issuer_ls180.v:136231.9-136231.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\alu_l_r_alu$next[0:0]$6785 1'1 + case + assign $1\alu_l_r_alu$next[0:0]$6785 \$90 + end + sync always + update \alu_l_r_alu$next $0\alu_l_r_alu$next[0:0]$6784 + end + attribute \src "issuer_ls180.v:136239.3-136248.6" + process $proc$issuer_ls180.v:136239$6786 + assign { } { } + assign { } { } + assign $0\dest1_o[63:0] $1\dest1_o[63:0] + attribute \src "issuer_ls180.v:136240.5-136240.29" + switch \initial + attribute \src "issuer_ls180.v:136240.9-136240.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" + switch \$114 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dest1_o[63:0] \data_r0__o + case + assign $1\dest1_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \dest1_o $0\dest1_o[63:0] + end + attribute \src "issuer_ls180.v:136249.3-136258.6" + process $proc$issuer_ls180.v:136249$6787 + assign { } { } + assign { } { } + assign $0\dest2_o[3:0] $1\dest2_o[3:0] + attribute \src "issuer_ls180.v:136250.5-136250.29" + switch \initial + attribute \src "issuer_ls180.v:136250.9-136250.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" + switch \$116 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dest2_o[3:0] \data_r1__cr_a + case + assign $1\dest2_o[3:0] 4'0000 + end + sync always + update \dest2_o $0\dest2_o[3:0] + end + attribute \src "issuer_ls180.v:136259.3-136268.6" + process $proc$issuer_ls180.v:136259$6788 + assign { } { } + assign { } { } + assign $0\dest3_o[1:0] $1\dest3_o[1:0] + attribute \src "issuer_ls180.v:136260.5-136260.29" + switch \initial + attribute \src "issuer_ls180.v:136260.9-136260.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" + switch \$118 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dest3_o[1:0] \data_r2__xer_ov + case + assign $1\dest3_o[1:0] 2'00 + end + sync always + update \dest3_o $0\dest3_o[1:0] + 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attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 output 17 \mul_op__insn_type$2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 10 \mul_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 26 \mul_op__is_32bit$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 11 \mul_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 27 \mul_op__is_signed$12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 7 \mul_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 23 \mul_op__oe__oe$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 8 \mul_op__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 24 \mul_op__oe__ok$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 6 \mul_op__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 22 \mul_op__rc__ok$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 5 \mul_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 21 \mul_op__rc__rc$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 9 \mul_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 25 \mul_op__write_cr0$10 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 input 34 \muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 output 16 \muxid$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:11" + wire output 32 \neg_res + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:12" + wire output 33 \neg_res32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 13 \ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 output 29 \ra$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 14 \rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 output 30 \rb$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:33" + wire \sign32_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:34" + wire \sign32_b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:31" + wire \sign_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:32" + wire \sign_b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire input 15 \xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire output 31 \xer_so$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:38" + cell $and $and$issuer_ls180.v:136616$6833 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$17 + connect \B \mul_op__is_signed + connect \Y $and$issuer_ls180.v:136616$6833_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:39" + cell $and $and$issuer_ls180.v:136618$6835 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$21 + connect \B \mul_op__is_signed + connect \Y $and$issuer_ls180.v:136618$6835_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:40" + cell $and $and$issuer_ls180.v:136619$6836 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \ra [31] + connect \B \mul_op__is_signed + connect \Y $and$issuer_ls180.v:136619$6836_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:41" + cell $and $and$issuer_ls180.v:136620$6837 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \rb [31] + connect \B \mul_op__is_signed + connect \Y $and$issuer_ls180.v:136620$6837_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:52" + cell $pos $extend$issuer_ls180.v:136623$6840 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 65 + connect \A \ra + connect \Y $extend$issuer_ls180.v:136623$6840_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + cell $pos $extend$issuer_ls180.v:136624$6842 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 65 + connect \A \ra + connect \Y $extend$issuer_ls180.v:136624$6842_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:53" + cell $pos $extend$issuer_ls180.v:136626$6845 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 65 + connect \A \rb + connect \Y $extend$issuer_ls180.v:136626$6845_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + cell $pos $extend$issuer_ls180.v:136627$6847 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 65 + connect \A \rb + connect \Y $extend$issuer_ls180.v:136627$6847_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:52" + cell $neg $neg$issuer_ls180.v:136623$6841 + parameter \A_SIGNED 0 + parameter \A_WIDTH 65 + parameter \Y_WIDTH 65 + connect \A $extend$issuer_ls180.v:136623$6840_Y + connect \Y $neg$issuer_ls180.v:136623$6841_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:53" + cell $neg $neg$issuer_ls180.v:136626$6846 + parameter \A_SIGNED 0 + parameter \A_WIDTH 65 + parameter \Y_WIDTH 65 + connect \A $extend$issuer_ls180.v:136626$6845_Y + connect \Y $neg$issuer_ls180.v:136626$6846_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + cell $pos $pos$issuer_ls180.v:136624$6843 + parameter \A_SIGNED 0 + parameter \A_WIDTH 65 + parameter \Y_WIDTH 65 + connect \A $extend$issuer_ls180.v:136624$6842_Y + connect \Y $pos$issuer_ls180.v:136624$6843_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + cell $pos $pos$issuer_ls180.v:136627$6848 + parameter \A_SIGNED 0 + parameter \A_WIDTH 65 + parameter \Y_WIDTH 65 + connect \A $extend$issuer_ls180.v:136627$6847_Y + connect \Y $pos$issuer_ls180.v:136627$6848_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:38" + cell $mux $ternary$issuer_ls180.v:136615$6832 + parameter \WIDTH 1 + connect \A \ra [63] + connect \B \ra [31] + connect \S \mul_op__is_32bit + connect \Y $ternary$issuer_ls180.v:136615$6832_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:39" + cell $mux $ternary$issuer_ls180.v:136617$6834 + parameter \WIDTH 1 + connect \A \rb [63] + connect \B \rb [31] + connect \S \mul_op__is_32bit + connect \Y $ternary$issuer_ls180.v:136617$6834_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:52" + cell $mux $ternary$issuer_ls180.v:136625$6844 + parameter \WIDTH 65 + connect \A \$36 + connect \B \$34 + connect \S \sign_a + connect \Y $ternary$issuer_ls180.v:136625$6844_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:53" + cell $mux $ternary$issuer_ls180.v:136628$6849 + parameter \WIDTH 65 + connect \A \$43 + connect \B \$41 + connect \S \sign_b + connect \Y $ternary$issuer_ls180.v:136628$6849_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:34" + cell $mux $ternary$issuer_ls180.v:136629$6850 + parameter \WIDTH 32 + connect \A \abs_a [63:32] + connect \B 0 + connect \S \is_32bit + connect \Y $ternary$issuer_ls180.v:136629$6850_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:34" + cell $mux $ternary$issuer_ls180.v:136630$6851 + parameter \WIDTH 32 + connect \A \abs_b [63:32] + connect \B 0 + connect \S \is_32bit + connect \Y $ternary$issuer_ls180.v:136630$6851_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:44" + cell $xor $xor$issuer_ls180.v:136621$6838 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \sign_a + connect \B \sign_b + connect \Y $xor$issuer_ls180.v:136621$6838_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:45" + cell $xor $xor$issuer_ls180.v:136622$6839 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \sign32_a + connect \B \sign32_b + connect \Y $xor$issuer_ls180.v:136622$6839_Y + end + connect \$17 $ternary$issuer_ls180.v:136615$6832_Y + connect \$19 $and$issuer_ls180.v:136616$6833_Y + connect \$21 $ternary$issuer_ls180.v:136617$6834_Y + connect \$23 $and$issuer_ls180.v:136618$6835_Y + connect \$25 $and$issuer_ls180.v:136619$6836_Y + connect \$27 $and$issuer_ls180.v:136620$6837_Y + connect \$29 $xor$issuer_ls180.v:136621$6838_Y + connect \$31 $xor$issuer_ls180.v:136622$6839_Y + connect \$34 $neg$issuer_ls180.v:136623$6841_Y + connect \$36 $pos$issuer_ls180.v:136624$6843_Y + connect \$38 $ternary$issuer_ls180.v:136625$6844_Y + connect \$41 $neg$issuer_ls180.v:136626$6846_Y + connect \$43 $pos$issuer_ls180.v:136627$6848_Y + connect \$45 $ternary$issuer_ls180.v:136628$6849_Y + connect \$47 $ternary$issuer_ls180.v:136629$6850_Y + connect \$49 $ternary$issuer_ls180.v:136630$6851_Y + connect \$33 \$38 + connect \$40 \$45 + connect { \mul_op__insn$13 \mul_op__is_signed$12 \mul_op__is_32bit$11 \mul_op__write_cr0$10 \mul_op__oe__ok$9 \mul_op__oe__oe$8 \mul_op__rc__ok$7 \mul_op__rc__rc$6 \mul_op__imm_data__ok$5 \mul_op__imm_data__data$4 \mul_op__fn_unit$3 \mul_op__insn_type$2 } { \mul_op__insn \mul_op__is_signed \mul_op__is_32bit \mul_op__write_cr0 \mul_op__oe__ok \mul_op__oe__oe \mul_op__rc__ok \mul_op__rc__rc \mul_op__imm_data__ok \mul_op__imm_data__data \mul_op__fn_unit \mul_op__insn_type } + connect \muxid$1 \muxid + connect \xer_so$16 \xer_so + connect \rb$15 [63:32] \$49 + connect \rb$15 [31:0] \abs_b [31:0] + connect \ra$14 [63:32] \$47 + connect \ra$14 [31:0] \abs_a [31:0] + connect \abs_b \$45 [63:0] + connect \abs_a \$38 [63:0] + connect \neg_res32 \$31 + connect \neg_res \$29 + connect \sign32_b \$27 + connect \sign32_a \$25 + connect \sign_b \$23 + connect \sign_a \$19 + connect \is_32bit \mul_op__is_32bit +end +attribute \src "issuer_ls180.v:136653.1-136910.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.fus.mul0.alu_mul0.mul_pipe2.mul2" +attribute \generator "nMigen" +module \mul2 + attribute \src "issuer_ls180.v:136903.18-136903.98" + wire width 129 $extend$issuer_ls180.v:136903$6853_Y + attribute \src "issuer_ls180.v:136902.18-136902.99" + wire width 128 $mul$issuer_ls180.v:136902$6852_Y + attribute \src "issuer_ls180.v:136903.18-136903.98" + wire width 129 $pos$issuer_ls180.v:136903$6854_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/main_stage.py:28" + wire width 129 \$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/main_stage.py:28" + wire width 128 \$18 + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 input 2 \mul_op__fn_unit + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 output 20 \mul_op__fn_unit$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 input 3 \mul_op__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 output 21 \mul_op__imm_data__data$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 4 \mul_op__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 22 \mul_op__imm_data__ok$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 12 \mul_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 output 30 \mul_op__insn$13 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 input 1 \mul_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 output 19 \mul_op__insn_type$2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 10 \mul_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 28 \mul_op__is_32bit$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 11 \mul_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 29 \mul_op__is_signed$12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 7 \mul_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 25 \mul_op__oe__oe$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 8 \mul_op__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 26 \mul_op__oe__ok$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 6 \mul_op__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 24 \mul_op__rc__ok$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 5 \mul_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 23 \mul_op__rc__rc$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 9 \mul_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 27 \mul_op__write_cr0$10 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 input 35 \muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 output 18 \muxid$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:11" + wire input 16 \neg_res + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:23" + wire output 33 \neg_res$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:12" + wire input 17 \neg_res32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:24" + wire output 34 \neg_res32$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 129 output 31 \o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 13 \ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 14 \rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire input 15 \xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire output 32 \xer_so$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/main_stage.py:28" + cell $pos $extend$issuer_ls180.v:136903$6853 + parameter \A_SIGNED 0 + parameter \A_WIDTH 128 + parameter \Y_WIDTH 129 + connect \A \$18 + connect \Y $extend$issuer_ls180.v:136903$6853_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/main_stage.py:28" + cell $mul $mul$issuer_ls180.v:136902$6852 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 64 + parameter \Y_WIDTH 128 + connect \A \ra + connect \B \rb + connect \Y $mul$issuer_ls180.v:136902$6852_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/main_stage.py:28" + cell $pos $pos$issuer_ls180.v:136903$6854 + parameter \A_SIGNED 0 + parameter \A_WIDTH 129 + parameter \Y_WIDTH 129 + connect \A $extend$issuer_ls180.v:136903$6853_Y + connect \Y $pos$issuer_ls180.v:136903$6854_Y + end + connect \$18 $mul$issuer_ls180.v:136902$6852_Y + connect \$17 $pos$issuer_ls180.v:136903$6854_Y + connect { \mul_op__insn$13 \mul_op__is_signed$12 \mul_op__is_32bit$11 \mul_op__write_cr0$10 \mul_op__oe__ok$9 \mul_op__oe__oe$8 \mul_op__rc__ok$7 \mul_op__rc__rc$6 \mul_op__imm_data__ok$5 \mul_op__imm_data__data$4 \mul_op__fn_unit$3 \mul_op__insn_type$2 } { \mul_op__insn \mul_op__is_signed \mul_op__is_32bit \mul_op__write_cr0 \mul_op__oe__ok \mul_op__oe__oe \mul_op__rc__ok \mul_op__rc__rc \mul_op__imm_data__ok \mul_op__imm_data__data \mul_op__fn_unit \mul_op__insn_type } + connect \muxid$1 \muxid + connect \xer_so$14 \xer_so + connect \neg_res32$16 \neg_res32 + connect \neg_res$15 \neg_res + connect \o \$17 +end +attribute \src "issuer_ls180.v:136914.1-137293.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.fus.mul0.alu_mul0.mul_pipe3.mul3" +attribute \generator "nMigen" +module \mul3 + attribute \src "issuer_ls180.v:136915.7-136915.20" + wire $0\initial[0:0] + attribute \src "issuer_ls180.v:137246.3-137264.6" + wire $0\mul_ov[0:0] + attribute \src "issuer_ls180.v:137208.3-137226.6" + wire width 64 $0\o$14[63:0]$6871 + attribute \src "issuer_ls180.v:137227.3-137245.6" + wire $0\o_ok[0:0] + attribute \src "issuer_ls180.v:137265.3-137275.6" + wire width 2 $0\xer_ov[1:0] + attribute \src "issuer_ls180.v:137276.3-137286.6" + wire $0\xer_ov_ok[0:0] + attribute \src "issuer_ls180.v:137246.3-137264.6" + wire $1\mul_ov[0:0] + attribute \src "issuer_ls180.v:137208.3-137226.6" + wire width 64 $1\o$14[63:0]$6872 + attribute \src "issuer_ls180.v:137227.3-137245.6" + wire $1\o_ok[0:0] + attribute \src "issuer_ls180.v:137265.3-137275.6" + wire width 2 $1\xer_ov[1:0] + attribute \src "issuer_ls180.v:137276.3-137286.6" + wire $1\xer_ov_ok[0:0] + attribute \src "issuer_ls180.v:137246.3-137264.6" + wire $2\mul_ov[0:0] + attribute \src "issuer_ls180.v:137202.18-137202.104" + wire $and$issuer_ls180.v:137202$6863_Y + attribute \src "issuer_ls180.v:137206.18-137206.104" + wire $and$issuer_ls180.v:137206$6867_Y + attribute \src "issuer_ls180.v:137196.18-137196.95" + wire width 130 $extend$issuer_ls180.v:137196$6855_Y + attribute \src "issuer_ls180.v:137197.18-137197.90" + wire width 130 $extend$issuer_ls180.v:137197$6857_Y + attribute \src "issuer_ls180.v:137207.18-137207.95" + wire width 2 $extend$issuer_ls180.v:137207$6868_Y + attribute \src "issuer_ls180.v:137196.18-137196.95" + wire width 130 $neg$issuer_ls180.v:137196$6856_Y + attribute \src "issuer_ls180.v:137201.18-137201.98" + wire $not$issuer_ls180.v:137201$6862_Y + attribute \src "issuer_ls180.v:137205.18-137205.98" + wire $not$issuer_ls180.v:137205$6866_Y + attribute \src "issuer_ls180.v:137197.18-137197.90" + wire width 130 $pos$issuer_ls180.v:137197$6858_Y + attribute \src "issuer_ls180.v:137207.18-137207.95" + wire width 2 $pos$issuer_ls180.v:137207$6869_Y + attribute \src "issuer_ls180.v:137200.18-137200.106" + wire $reduce_and$issuer_ls180.v:137200$6861_Y + attribute \src "issuer_ls180.v:137204.18-137204.107" + wire $reduce_and$issuer_ls180.v:137204$6865_Y + attribute \src "issuer_ls180.v:137199.18-137199.106" + wire $reduce_or$issuer_ls180.v:137199$6860_Y + attribute \src "issuer_ls180.v:137203.18-137203.107" + wire $reduce_or$issuer_ls180.v:137203$6864_Y + attribute \src "issuer_ls180.v:137198.18-137198.114" + wire width 130 $ternary$issuer_ls180.v:137198$6859_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:41" + wire width 130 \$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:41" + wire width 130 \$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 130 \$19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:41" + wire width 130 \$21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:65" + wire \$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:65" + wire \$25 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:65" + wire \$26 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:65" + wire \$29 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:70" + wire \$31 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:70" + wire \$33 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:70" + wire \$34 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:70" + wire \$37 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 2 \$39 + attribute \src "issuer_ls180.v:136915.7-136915.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:36" + wire \is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:40" + wire width 129 \mul_o + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 input 2 \mul_op__fn_unit + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 output 18 \mul_op__fn_unit$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 input 3 \mul_op__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 output 19 \mul_op__imm_data__data$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 4 \mul_op__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 20 \mul_op__imm_data__ok$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 12 \mul_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 output 28 \mul_op__insn$13 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 input 1 \mul_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 output 17 \mul_op__insn_type$2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 10 \mul_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 26 \mul_op__is_32bit$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 11 \mul_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 27 \mul_op__is_signed$12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 7 \mul_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 23 \mul_op__oe__oe$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 8 \mul_op__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 24 \mul_op__oe__ok$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 6 \mul_op__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 22 \mul_op__rc__ok$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 5 \mul_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 21 \mul_op__rc__rc$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 9 \mul_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 25 \mul_op__write_cr0$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:60" + wire \mul_ov + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 input 35 \muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 output 16 \muxid$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:23" + wire input 15 \neg_res + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 129 input 13 \o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 output 29 \o$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 30 \o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 2 output 31 \xer_ov + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 32 \xer_ov_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire input 14 \xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 33 \xer_so$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 34 \xer_so_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:65" + cell $and $and$issuer_ls180.v:137202$6863 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$23 + connect \B \$25 + connect \Y $and$issuer_ls180.v:137202$6863_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:70" + cell $and $and$issuer_ls180.v:137206$6867 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$31 + connect \B \$33 + connect \Y $and$issuer_ls180.v:137206$6867_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:41" + cell $pos $extend$issuer_ls180.v:137196$6855 + parameter \A_SIGNED 0 + parameter \A_WIDTH 129 + parameter \Y_WIDTH 130 + connect \A \o + connect \Y $extend$issuer_ls180.v:137196$6855_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + cell $pos $extend$issuer_ls180.v:137197$6857 + parameter \A_SIGNED 0 + parameter \A_WIDTH 129 + parameter \Y_WIDTH 130 + connect \A \o + connect \Y $extend$issuer_ls180.v:137197$6857_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + cell $pos $extend$issuer_ls180.v:137207$6868 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 2 + connect \A \xer_so + connect \Y $extend$issuer_ls180.v:137207$6868_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:41" + cell $neg $neg$issuer_ls180.v:137196$6856 + parameter \A_SIGNED 0 + parameter \A_WIDTH 130 + parameter \Y_WIDTH 130 + connect \A $extend$issuer_ls180.v:137196$6855_Y + connect \Y $neg$issuer_ls180.v:137196$6856_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:65" + cell $not $not$issuer_ls180.v:137201$6862 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$26 + connect \Y $not$issuer_ls180.v:137201$6862_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:70" + cell $not $not$issuer_ls180.v:137205$6866 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$34 + connect \Y $not$issuer_ls180.v:137205$6866_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + cell $pos $pos$issuer_ls180.v:137197$6858 + parameter \A_SIGNED 0 + parameter \A_WIDTH 130 + parameter \Y_WIDTH 130 + connect \A $extend$issuer_ls180.v:137197$6857_Y + connect \Y $pos$issuer_ls180.v:137197$6858_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + cell $pos $pos$issuer_ls180.v:137207$6869 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 2 + connect \A $extend$issuer_ls180.v:137207$6868_Y + connect \Y $pos$issuer_ls180.v:137207$6869_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:65" + cell $reduce_and $reduce_and$issuer_ls180.v:137200$6861 + parameter \A_SIGNED 0 + parameter \A_WIDTH 33 + parameter \Y_WIDTH 1 + connect \A \mul_o [63:31] + connect \Y $reduce_and$issuer_ls180.v:137200$6861_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:70" + cell $reduce_and $reduce_and$issuer_ls180.v:137204$6865 + parameter \A_SIGNED 0 + parameter \A_WIDTH 65 + parameter \Y_WIDTH 1 + connect \A \mul_o [127:63] + connect \Y $reduce_and$issuer_ls180.v:137204$6865_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:65" + cell $reduce_or $reduce_or$issuer_ls180.v:137199$6860 + parameter \A_SIGNED 0 + parameter \A_WIDTH 33 + parameter \Y_WIDTH 1 + connect \A \mul_o [63:31] + connect \Y $reduce_or$issuer_ls180.v:137199$6860_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:70" + cell $reduce_or $reduce_or$issuer_ls180.v:137203$6864 + parameter \A_SIGNED 0 + parameter \A_WIDTH 65 + parameter \Y_WIDTH 1 + connect \A \mul_o [127:63] + connect \Y $reduce_or$issuer_ls180.v:137203$6864_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:41" + cell $mux $ternary$issuer_ls180.v:137198$6859 + parameter \WIDTH 130 + connect \A \$19 + connect \B \$17 + connect \S \neg_res + connect \Y $ternary$issuer_ls180.v:137198$6859_Y + end + attribute \src "issuer_ls180.v:136915.7-136915.20" + process $proc$issuer_ls180.v:136915$6877 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "issuer_ls180.v:137208.3-137226.6" + process $proc$issuer_ls180.v:137208$6870 + assign { } { } + assign { } { } + assign $0\o$14[63:0]$6871 $1\o$14[63:0]$6872 + attribute \src "issuer_ls180.v:137209.5-137209.29" + switch \initial + attribute \src "issuer_ls180.v:137209.9-137209.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:44" + switch \mul_op__insn_type + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'0110100 + assign { } { } + assign $1\o$14[63:0]$6872 { \mul_o [63:32] \mul_o [63:32] } + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'0110011 + assign { } { } + assign $1\o$14[63:0]$6872 \mul_o [127:64] + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'0110010 + assign { } { } + assign $1\o$14[63:0]$6872 \mul_o [63:0] + case + assign $1\o$14[63:0]$6872 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \o$14 $0\o$14[63:0]$6871 + end + attribute \src "issuer_ls180.v:137227.3-137245.6" + process $proc$issuer_ls180.v:137227$6873 + assign { } { } + assign { } { } + assign $0\o_ok[0:0] $1\o_ok[0:0] + attribute \src "issuer_ls180.v:137228.5-137228.29" + switch \initial + attribute \src "issuer_ls180.v:137228.9-137228.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:44" + switch \mul_op__insn_type + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'0110100 + assign { } { } + assign $1\o_ok[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'0110011 + assign { } { } + assign $1\o_ok[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'0110010 + assign { } { } + assign $1\o_ok[0:0] 1'1 + case + assign $1\o_ok[0:0] 1'0 + end + sync always + update \o_ok $0\o_ok[0:0] + end + attribute \src "issuer_ls180.v:137246.3-137264.6" + process $proc$issuer_ls180.v:137246$6874 + assign { } { } + assign { } { } + assign $0\mul_ov[0:0] $1\mul_ov[0:0] + attribute \src "issuer_ls180.v:137247.5-137247.29" + switch \initial + attribute \src "issuer_ls180.v:137247.9-137247.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:44" + switch \mul_op__insn_type + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'0110010 + assign { } { } + assign $1\mul_ov[0:0] $2\mul_ov[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:61" + switch \is_32bit + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\mul_ov[0:0] \$29 + attribute \src "issuer_ls180.v:0.0-0.0" + case + assign { } { } + assign $2\mul_ov[0:0] \$37 + end + case + assign $1\mul_ov[0:0] 1'0 + end + sync always + update \mul_ov $0\mul_ov[0:0] + end + attribute \src "issuer_ls180.v:137265.3-137275.6" + process $proc$issuer_ls180.v:137265$6875 + assign { } { } + assign { } { } + assign $0\xer_ov[1:0] $1\xer_ov[1:0] + attribute \src "issuer_ls180.v:137266.5-137266.29" + switch \initial + attribute \src "issuer_ls180.v:137266.9-137266.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:44" + switch \mul_op__insn_type + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'0110010 + assign { } { } + assign $1\xer_ov[1:0] { \mul_ov \mul_ov } + case + assign $1\xer_ov[1:0] 2'00 + end + sync always + update \xer_ov $0\xer_ov[1:0] + end + attribute \src "issuer_ls180.v:137276.3-137286.6" + process $proc$issuer_ls180.v:137276$6876 + assign { } { } + assign { } { } + assign $0\xer_ov_ok[0:0] $1\xer_ov_ok[0:0] + attribute \src "issuer_ls180.v:137277.5-137277.29" + switch \initial + attribute \src "issuer_ls180.v:137277.9-137277.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:44" + switch \mul_op__insn_type + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'0110010 + assign { } { } + assign $1\xer_ov_ok[0:0] 1'1 + case + assign $1\xer_ov_ok[0:0] 1'0 + end + sync always + update \xer_ov_ok $0\xer_ov_ok[0:0] + end + connect \$17 $neg$issuer_ls180.v:137196$6856_Y + connect \$19 $pos$issuer_ls180.v:137197$6858_Y + connect \$21 $ternary$issuer_ls180.v:137198$6859_Y + connect \$23 $reduce_or$issuer_ls180.v:137199$6860_Y + connect \$26 $reduce_and$issuer_ls180.v:137200$6861_Y + connect \$25 $not$issuer_ls180.v:137201$6862_Y + connect \$29 $and$issuer_ls180.v:137202$6863_Y + connect \$31 $reduce_or$issuer_ls180.v:137203$6864_Y + connect \$34 $reduce_and$issuer_ls180.v:137204$6865_Y + connect \$33 $not$issuer_ls180.v:137205$6866_Y + connect \$37 $and$issuer_ls180.v:137206$6867_Y + connect \$39 $pos$issuer_ls180.v:137207$6869_Y + connect \$16 \$21 + connect { \mul_op__insn$13 \mul_op__is_signed$12 \mul_op__is_32bit$11 \mul_op__write_cr0$10 \mul_op__oe__ok$9 \mul_op__oe__oe$8 \mul_op__rc__ok$7 \mul_op__rc__rc$6 \mul_op__imm_data__ok$5 \mul_op__imm_data__data$4 \mul_op__fn_unit$3 \mul_op__insn_type$2 } { \mul_op__insn \mul_op__is_signed \mul_op__is_32bit \mul_op__write_cr0 \mul_op__oe__ok \mul_op__oe__oe \mul_op__rc__ok \mul_op__rc__rc \mul_op__imm_data__ok \mul_op__imm_data__data \mul_op__fn_unit \mul_op__insn_type } + connect \muxid$1 \muxid + connect { \xer_so_ok \xer_so$15 } \$39 + connect \mul_o \$21 [128:0] + connect \is_32bit \mul_op__is_32bit +end +attribute \src "issuer_ls180.v:137297.1-138493.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.fus.mul0.alu_mul0.mul_pipe1" +attribute \generator "nMigen" +module \mul_pipe1 + attribute \src "issuer_ls180.v:137298.7-137298.20" + wire $0\initial[0:0] + attribute \src "issuer_ls180.v:138370.3-138405.6" + wire width 12 $0\mul_op__fn_unit$next[11:0]$6906 + attribute \src "issuer_ls180.v:138235.3-138236.47" + wire width 12 $0\mul_op__fn_unit[11:0] + attribute \src "issuer_ls180.v:138370.3-138405.6" + wire width 64 $0\mul_op__imm_data__data$next[63:0]$6907 + attribute \src "issuer_ls180.v:138237.3-138238.61" + wire width 64 $0\mul_op__imm_data__data[63:0] + attribute \src "issuer_ls180.v:138370.3-138405.6" + wire $0\mul_op__imm_data__ok$next[0:0]$6908 + attribute \src "issuer_ls180.v:138239.3-138240.57" + wire $0\mul_op__imm_data__ok[0:0] + attribute \src "issuer_ls180.v:138370.3-138405.6" + wire width 32 $0\mul_op__insn$next[31:0]$6909 + attribute \src "issuer_ls180.v:138255.3-138256.41" + wire width 32 $0\mul_op__insn[31:0] + attribute \src "issuer_ls180.v:138370.3-138405.6" + wire width 7 $0\mul_op__insn_type$next[6:0]$6910 + attribute \src "issuer_ls180.v:138233.3-138234.51" + wire width 7 $0\mul_op__insn_type[6:0] + attribute \src "issuer_ls180.v:138370.3-138405.6" + wire $0\mul_op__is_32bit$next[0:0]$6911 + attribute \src "issuer_ls180.v:138251.3-138252.49" + wire $0\mul_op__is_32bit[0:0] + attribute \src "issuer_ls180.v:138370.3-138405.6" + wire $0\mul_op__is_signed$next[0:0]$6912 + attribute \src "issuer_ls180.v:138253.3-138254.51" + wire $0\mul_op__is_signed[0:0] + attribute \src "issuer_ls180.v:138370.3-138405.6" + wire $0\mul_op__oe__oe$next[0:0]$6913 + attribute \src "issuer_ls180.v:138245.3-138246.45" + wire $0\mul_op__oe__oe[0:0] + attribute \src "issuer_ls180.v:138370.3-138405.6" + wire $0\mul_op__oe__ok$next[0:0]$6914 + attribute \src "issuer_ls180.v:138247.3-138248.45" + wire $0\mul_op__oe__ok[0:0] + attribute \src "issuer_ls180.v:138370.3-138405.6" + wire $0\mul_op__rc__ok$next[0:0]$6915 + attribute \src "issuer_ls180.v:138243.3-138244.45" + wire $0\mul_op__rc__ok[0:0] + attribute \src "issuer_ls180.v:138370.3-138405.6" + wire $0\mul_op__rc__rc$next[0:0]$6916 + attribute \src "issuer_ls180.v:138241.3-138242.45" + wire $0\mul_op__rc__rc[0:0] + attribute \src "issuer_ls180.v:138370.3-138405.6" + wire $0\mul_op__write_cr0$next[0:0]$6917 + attribute \src "issuer_ls180.v:138249.3-138250.51" + wire $0\mul_op__write_cr0[0:0] + attribute \src "issuer_ls180.v:138357.3-138369.6" + wire width 2 $0\muxid$next[1:0]$6903 + attribute \src "issuer_ls180.v:138257.3-138258.27" + wire width 2 $0\muxid[1:0] + attribute \src "issuer_ls180.v:138445.3-138457.6" + wire $0\neg_res$next[0:0]$6946 + attribute \src "issuer_ls180.v:138458.3-138470.6" + wire $0\neg_res32$next[0:0]$6949 + attribute \src "issuer_ls180.v:138223.3-138224.35" + wire $0\neg_res32[0:0] + attribute \src "issuer_ls180.v:138225.3-138226.31" + wire $0\neg_res[0:0] + attribute \src "issuer_ls180.v:138339.3-138356.6" + wire $0\r_busy$next[0:0]$6899 + attribute \src "issuer_ls180.v:138259.3-138260.29" + wire $0\r_busy[0:0] + attribute \src "issuer_ls180.v:138406.3-138418.6" + wire width 64 $0\ra$next[63:0]$6937 + attribute \src "issuer_ls180.v:138231.3-138232.21" + wire width 64 $0\ra[63:0] + attribute \src "issuer_ls180.v:138419.3-138431.6" + wire width 64 $0\rb$next[63:0]$6940 + attribute \src "issuer_ls180.v:138229.3-138230.21" + wire width 64 $0\rb[63:0] + attribute \src "issuer_ls180.v:138432.3-138444.6" + wire $0\xer_so$next[0:0]$6943 + attribute \src "issuer_ls180.v:138227.3-138228.29" + wire $0\xer_so[0:0] + attribute \src "issuer_ls180.v:138370.3-138405.6" + wire width 12 $1\mul_op__fn_unit$next[11:0]$6918 + attribute \src "issuer_ls180.v:137800.14-137800.39" + wire width 12 $1\mul_op__fn_unit[11:0] + attribute \src "issuer_ls180.v:138370.3-138405.6" + wire width 64 $1\mul_op__imm_data__data$next[63:0]$6919 + attribute \src "issuer_ls180.v:137835.14-137835.59" + wire width 64 $1\mul_op__imm_data__data[63:0] + attribute \src "issuer_ls180.v:138370.3-138405.6" + wire $1\mul_op__imm_data__ok$next[0:0]$6920 + attribute \src "issuer_ls180.v:137844.7-137844.34" + wire $1\mul_op__imm_data__ok[0:0] + attribute \src "issuer_ls180.v:138370.3-138405.6" + wire width 32 $1\mul_op__insn$next[31:0]$6921 + attribute \src "issuer_ls180.v:137853.14-137853.34" + wire width 32 $1\mul_op__insn[31:0] + attribute \src "issuer_ls180.v:138370.3-138405.6" + wire width 7 $1\mul_op__insn_type$next[6:0]$6922 + attribute \src "issuer_ls180.v:137936.13-137936.38" + wire width 7 $1\mul_op__insn_type[6:0] + attribute \src "issuer_ls180.v:138370.3-138405.6" + wire $1\mul_op__is_32bit$next[0:0]$6923 + attribute \src "issuer_ls180.v:138093.7-138093.30" + wire $1\mul_op__is_32bit[0:0] + attribute \src "issuer_ls180.v:138370.3-138405.6" + wire $1\mul_op__is_signed$next[0:0]$6924 + attribute \src "issuer_ls180.v:138102.7-138102.31" + wire $1\mul_op__is_signed[0:0] + attribute \src "issuer_ls180.v:138370.3-138405.6" + wire $1\mul_op__oe__oe$next[0:0]$6925 + attribute \src "issuer_ls180.v:138111.7-138111.28" + wire $1\mul_op__oe__oe[0:0] + attribute \src "issuer_ls180.v:138370.3-138405.6" + wire $1\mul_op__oe__ok$next[0:0]$6926 + attribute \src "issuer_ls180.v:138120.7-138120.28" + wire $1\mul_op__oe__ok[0:0] + attribute \src "issuer_ls180.v:138370.3-138405.6" + wire $1\mul_op__rc__ok$next[0:0]$6927 + attribute \src "issuer_ls180.v:138129.7-138129.28" + wire $1\mul_op__rc__ok[0:0] + attribute \src "issuer_ls180.v:138370.3-138405.6" + wire $1\mul_op__rc__rc$next[0:0]$6928 + attribute \src "issuer_ls180.v:138138.7-138138.28" + wire $1\mul_op__rc__rc[0:0] + attribute \src "issuer_ls180.v:138370.3-138405.6" + wire $1\mul_op__write_cr0$next[0:0]$6929 + attribute \src "issuer_ls180.v:138147.7-138147.31" + wire $1\mul_op__write_cr0[0:0] + attribute \src "issuer_ls180.v:138357.3-138369.6" + wire width 2 $1\muxid$next[1:0]$6904 + attribute \src "issuer_ls180.v:138156.13-138156.25" + wire width 2 $1\muxid[1:0] + attribute \src "issuer_ls180.v:138445.3-138457.6" + wire $1\neg_res$next[0:0]$6947 + attribute \src "issuer_ls180.v:138458.3-138470.6" + wire $1\neg_res32$next[0:0]$6950 + attribute \src "issuer_ls180.v:138178.7-138178.23" + wire $1\neg_res32[0:0] + attribute \src "issuer_ls180.v:138171.7-138171.21" + wire $1\neg_res[0:0] + attribute \src "issuer_ls180.v:138339.3-138356.6" + wire $1\r_busy$next[0:0]$6900 + attribute \src "issuer_ls180.v:138192.7-138192.20" + wire $1\r_busy[0:0] + attribute \src "issuer_ls180.v:138406.3-138418.6" + wire width 64 $1\ra$next[63:0]$6938 + attribute \src "issuer_ls180.v:138197.14-138197.39" + wire width 64 $1\ra[63:0] + attribute \src "issuer_ls180.v:138419.3-138431.6" + wire width 64 $1\rb$next[63:0]$6941 + attribute \src "issuer_ls180.v:138206.14-138206.39" + wire width 64 $1\rb[63:0] + attribute \src "issuer_ls180.v:138432.3-138444.6" + wire $1\xer_so$next[0:0]$6944 + attribute \src "issuer_ls180.v:138215.7-138215.20" + wire $1\xer_so[0:0] + attribute \src "issuer_ls180.v:138370.3-138405.6" + wire width 64 $2\mul_op__imm_data__data$next[63:0]$6930 + attribute \src "issuer_ls180.v:138370.3-138405.6" + wire $2\mul_op__imm_data__ok$next[0:0]$6931 + attribute \src "issuer_ls180.v:138370.3-138405.6" + wire $2\mul_op__oe__oe$next[0:0]$6932 + attribute \src "issuer_ls180.v:138370.3-138405.6" + wire $2\mul_op__oe__ok$next[0:0]$6933 + attribute \src "issuer_ls180.v:138370.3-138405.6" + wire $2\mul_op__rc__ok$next[0:0]$6934 + attribute \src "issuer_ls180.v:138370.3-138405.6" + wire $2\mul_op__rc__rc$next[0:0]$6935 + attribute \src "issuer_ls180.v:138339.3-138356.6" + wire $2\r_busy$next[0:0]$6901 + attribute \src "issuer_ls180.v:138222.18-138222.118" + wire $and$issuer_ls180.v:138222$6878_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" + wire \$50 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" + wire input 40 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" + wire input 1 \coresync_rst + attribute \src "issuer_ls180.v:137298.7-137298.15" + wire \initial + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 \input_mul_op__fn_unit + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 \input_mul_op__fn_unit$19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \input_mul_op__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \input_mul_op__imm_data__data$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_mul_op__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_mul_op__imm_data__ok$21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \input_mul_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \input_mul_op__insn$29 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \input_mul_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \input_mul_op__insn_type$18 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_mul_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_mul_op__is_32bit$27 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_mul_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_mul_op__is_signed$28 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_mul_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_mul_op__oe__oe$24 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_mul_op__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_mul_op__oe__ok$25 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_mul_op__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_mul_op__rc__ok$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_mul_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_mul_op__rc__rc$22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_mul_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_mul_op__write_cr0$26 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \input_muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \input_muxid$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \input_ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \input_ra$30 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \input_rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \input_rb$31 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire \input_xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire \input_xer_so$32 + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 \mul1_mul_op__fn_unit + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 \mul1_mul_op__fn_unit$35 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \mul1_mul_op__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \mul1_mul_op__imm_data__data$36 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul1_mul_op__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul1_mul_op__imm_data__ok$37 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \mul1_mul_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \mul1_mul_op__insn$45 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \mul1_mul_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \mul1_mul_op__insn_type$34 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul1_mul_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul1_mul_op__is_32bit$43 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul1_mul_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul1_mul_op__is_signed$44 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul1_mul_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul1_mul_op__oe__oe$40 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul1_mul_op__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul1_mul_op__oe__ok$41 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul1_mul_op__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul1_mul_op__rc__ok$39 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul1_mul_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul1_mul_op__rc__rc$38 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul1_mul_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul1_mul_op__write_cr0$42 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \mul1_muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \mul1_muxid$33 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:11" + wire \mul1_neg_res + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:12" + wire \mul1_neg_res32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \mul1_ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \mul1_ra$46 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \mul1_rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \mul1_rb$47 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire \mul1_xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire \mul1_xer_so$48 + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 output 6 \mul_op__fn_unit + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 input 26 \mul_op__fn_unit$3 + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 \mul_op__fn_unit$54 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 \mul_op__fn_unit$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 output 7 \mul_op__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 input 27 \mul_op__imm_data__data$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \mul_op__imm_data__data$55 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \mul_op__imm_data__data$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 8 \mul_op__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 28 \mul_op__imm_data__ok$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_op__imm_data__ok$56 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_op__imm_data__ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 output 16 \mul_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 36 \mul_op__insn$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \mul_op__insn$64 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \mul_op__insn$next + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 output 5 \mul_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 input 25 \mul_op__insn_type$2 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \mul_op__insn_type$53 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \mul_op__insn_type$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 14 \mul_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 34 \mul_op__is_32bit$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_op__is_32bit$62 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_op__is_32bit$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 15 \mul_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 35 \mul_op__is_signed$12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_op__is_signed$63 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_op__is_signed$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 11 \mul_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_op__oe__oe$59 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 31 \mul_op__oe__oe$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_op__oe__oe$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 12 \mul_op__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_op__oe__ok$60 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 32 \mul_op__oe__ok$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_op__oe__ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 10 \mul_op__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_op__rc__ok$58 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 30 \mul_op__rc__ok$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_op__rc__ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 9 \mul_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_op__rc__rc$57 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 29 \mul_op__rc__rc$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_op__rc__rc$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 13 \mul_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 33 \mul_op__write_cr0$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_op__write_cr0$61 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_op__write_cr0$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 output 4 \muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 input 24 \muxid$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \muxid$52 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \muxid$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:619" + wire \n_i_rdy_data + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" + wire input 3 \n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" + wire output 2 \n_valid_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:11" + wire output 20 \neg_res + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:11" + wire \neg_res$68 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:11" + wire \neg_res$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:12" + wire output 21 \neg_res32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:12" + wire \neg_res32$69 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:12" + wire \neg_res32$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" + wire output 23 \p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" + wire input 22 \p_valid_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:621" + wire \p_valid_i$49 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" + wire \p_valid_i_p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615" + wire \r_busy + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615" + wire \r_busy$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 output 17 \ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 37 \ra$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \ra$65 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \ra$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 output 18 \rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 38 \rb$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \rb$66 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \rb$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire output 19 \xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire input 39 \xer_so$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire \xer_so$67 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire \xer_so$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" + cell $and $and$issuer_ls180.v:138222$6878 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \p_valid_i$49 + connect \B \p_ready_o + connect \Y $and$issuer_ls180.v:138222$6878_Y + end + attribute \module_not_derived 1 + attribute \src "issuer_ls180.v:138261.14-138294.4" + cell \input$92 \input + connect \mul_op__fn_unit \input_mul_op__fn_unit + connect \mul_op__fn_unit$3 \input_mul_op__fn_unit$19 + connect \mul_op__imm_data__data \input_mul_op__imm_data__data + connect \mul_op__imm_data__data$4 \input_mul_op__imm_data__data$20 + connect \mul_op__imm_data__ok \input_mul_op__imm_data__ok + connect \mul_op__imm_data__ok$5 \input_mul_op__imm_data__ok$21 + connect \mul_op__insn \input_mul_op__insn + connect \mul_op__insn$13 \input_mul_op__insn$29 + connect \mul_op__insn_type \input_mul_op__insn_type + connect \mul_op__insn_type$2 \input_mul_op__insn_type$18 + connect \mul_op__is_32bit \input_mul_op__is_32bit + connect \mul_op__is_32bit$11 \input_mul_op__is_32bit$27 + connect \mul_op__is_signed \input_mul_op__is_signed + connect \mul_op__is_signed$12 \input_mul_op__is_signed$28 + connect \mul_op__oe__oe \input_mul_op__oe__oe + connect \mul_op__oe__oe$8 \input_mul_op__oe__oe$24 + connect \mul_op__oe__ok \input_mul_op__oe__ok + connect \mul_op__oe__ok$9 \input_mul_op__oe__ok$25 + connect \mul_op__rc__ok \input_mul_op__rc__ok + connect \mul_op__rc__ok$7 \input_mul_op__rc__ok$23 + connect \mul_op__rc__rc \input_mul_op__rc__rc + connect \mul_op__rc__rc$6 \input_mul_op__rc__rc$22 + connect \mul_op__write_cr0 \input_mul_op__write_cr0 + connect \mul_op__write_cr0$10 \input_mul_op__write_cr0$26 + connect \muxid \input_muxid + connect \muxid$1 \input_muxid$17 + connect \ra \input_ra + connect \ra$14 \input_ra$30 + connect \rb \input_rb + connect \rb$15 \input_rb$31 + connect \xer_so \input_xer_so + connect \xer_so$16 \input_xer_so$32 + end + attribute \module_not_derived 1 + attribute \src "issuer_ls180.v:138295.8-138330.4" + cell \mul1 \mul1 + connect \mul_op__fn_unit \mul1_mul_op__fn_unit + connect \mul_op__fn_unit$3 \mul1_mul_op__fn_unit$35 + connect \mul_op__imm_data__data \mul1_mul_op__imm_data__data + connect \mul_op__imm_data__data$4 \mul1_mul_op__imm_data__data$36 + connect \mul_op__imm_data__ok \mul1_mul_op__imm_data__ok + connect \mul_op__imm_data__ok$5 \mul1_mul_op__imm_data__ok$37 + connect \mul_op__insn \mul1_mul_op__insn + connect \mul_op__insn$13 \mul1_mul_op__insn$45 + connect \mul_op__insn_type \mul1_mul_op__insn_type + connect \mul_op__insn_type$2 \mul1_mul_op__insn_type$34 + connect \mul_op__is_32bit \mul1_mul_op__is_32bit + connect \mul_op__is_32bit$11 \mul1_mul_op__is_32bit$43 + connect \mul_op__is_signed \mul1_mul_op__is_signed + connect \mul_op__is_signed$12 \mul1_mul_op__is_signed$44 + connect \mul_op__oe__oe \mul1_mul_op__oe__oe + connect \mul_op__oe__oe$8 \mul1_mul_op__oe__oe$40 + connect \mul_op__oe__ok \mul1_mul_op__oe__ok + connect \mul_op__oe__ok$9 \mul1_mul_op__oe__ok$41 + connect \mul_op__rc__ok \mul1_mul_op__rc__ok + connect \mul_op__rc__ok$7 \mul1_mul_op__rc__ok$39 + connect \mul_op__rc__rc \mul1_mul_op__rc__rc + connect \mul_op__rc__rc$6 \mul1_mul_op__rc__rc$38 + connect \mul_op__write_cr0 \mul1_mul_op__write_cr0 + connect \mul_op__write_cr0$10 \mul1_mul_op__write_cr0$42 + connect \muxid \mul1_muxid + connect \muxid$1 \mul1_muxid$33 + connect \neg_res \mul1_neg_res + connect \neg_res32 \mul1_neg_res32 + connect \ra \mul1_ra + connect \ra$14 \mul1_ra$46 + connect \rb \mul1_rb + connect \rb$15 \mul1_rb$47 + connect \xer_so \mul1_xer_so + connect \xer_so$16 \mul1_xer_so$48 + end + attribute \module_not_derived 1 + attribute \src "issuer_ls180.v:138331.10-138334.4" + cell \n$91 \n + connect \n_ready_i \n_ready_i + connect \n_valid_o \n_valid_o + end + attribute \module_not_derived 1 + attribute \src "issuer_ls180.v:138335.10-138338.4" + cell \p$90 \p + connect \p_ready_o \p_ready_o + connect \p_valid_i \p_valid_i + end + attribute \src "issuer_ls180.v:137298.7-137298.20" + process $proc$issuer_ls180.v:137298$6951 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "issuer_ls180.v:137800.14-137800.39" + process $proc$issuer_ls180.v:137800$6952 + assign { } { } + assign $1\mul_op__fn_unit[11:0] 12'000000000000 + sync always + sync init + update \mul_op__fn_unit $1\mul_op__fn_unit[11:0] + end + attribute \src "issuer_ls180.v:137835.14-137835.59" + process $proc$issuer_ls180.v:137835$6953 + assign { } { } + assign $1\mul_op__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \mul_op__imm_data__data $1\mul_op__imm_data__data[63:0] + end + attribute \src "issuer_ls180.v:137844.7-137844.34" + process $proc$issuer_ls180.v:137844$6954 + assign { } { } + assign $1\mul_op__imm_data__ok[0:0] 1'0 + sync always + sync init + update \mul_op__imm_data__ok $1\mul_op__imm_data__ok[0:0] + end + attribute \src "issuer_ls180.v:137853.14-137853.34" + process $proc$issuer_ls180.v:137853$6955 + assign { } { } + assign $1\mul_op__insn[31:0] 0 + sync always + sync init + update \mul_op__insn $1\mul_op__insn[31:0] + end + attribute \src "issuer_ls180.v:137936.13-137936.38" + process $proc$issuer_ls180.v:137936$6956 + assign { } { } + assign $1\mul_op__insn_type[6:0] 7'0000000 + sync always + sync init + update \mul_op__insn_type $1\mul_op__insn_type[6:0] + end + attribute \src "issuer_ls180.v:138093.7-138093.30" + process $proc$issuer_ls180.v:138093$6957 + assign { } { } + assign $1\mul_op__is_32bit[0:0] 1'0 + sync always + sync init + update \mul_op__is_32bit $1\mul_op__is_32bit[0:0] + end + attribute \src "issuer_ls180.v:138102.7-138102.31" + process $proc$issuer_ls180.v:138102$6958 + assign { } { } + assign $1\mul_op__is_signed[0:0] 1'0 + sync always + sync init + update \mul_op__is_signed $1\mul_op__is_signed[0:0] + end + attribute \src "issuer_ls180.v:138111.7-138111.28" + process $proc$issuer_ls180.v:138111$6959 + assign { } { } + assign $1\mul_op__oe__oe[0:0] 1'0 + sync always + sync init + update \mul_op__oe__oe $1\mul_op__oe__oe[0:0] + end + attribute \src "issuer_ls180.v:138120.7-138120.28" + process $proc$issuer_ls180.v:138120$6960 + assign { } { } + assign $1\mul_op__oe__ok[0:0] 1'0 + sync always + sync init + update \mul_op__oe__ok $1\mul_op__oe__ok[0:0] + end + attribute \src "issuer_ls180.v:138129.7-138129.28" + process $proc$issuer_ls180.v:138129$6961 + assign { } { } + assign $1\mul_op__rc__ok[0:0] 1'0 + sync always + sync init + update \mul_op__rc__ok $1\mul_op__rc__ok[0:0] + end + attribute \src "issuer_ls180.v:138138.7-138138.28" + process $proc$issuer_ls180.v:138138$6962 + assign { } { } + assign $1\mul_op__rc__rc[0:0] 1'0 + sync always + sync init + update \mul_op__rc__rc $1\mul_op__rc__rc[0:0] + end + attribute \src "issuer_ls180.v:138147.7-138147.31" + process $proc$issuer_ls180.v:138147$6963 + assign { } { } + assign $1\mul_op__write_cr0[0:0] 1'0 + sync always + sync init + update \mul_op__write_cr0 $1\mul_op__write_cr0[0:0] + end + attribute \src "issuer_ls180.v:138156.13-138156.25" + process $proc$issuer_ls180.v:138156$6964 + assign { } { } + assign $1\muxid[1:0] 2'00 + sync always + sync init + update \muxid $1\muxid[1:0] + end + attribute \src "issuer_ls180.v:138171.7-138171.21" + process $proc$issuer_ls180.v:138171$6965 + assign { } { } + assign $1\neg_res[0:0] 1'0 + sync always + sync init + update \neg_res $1\neg_res[0:0] + end + attribute \src "issuer_ls180.v:138178.7-138178.23" + process $proc$issuer_ls180.v:138178$6966 + assign { } { } + assign $1\neg_res32[0:0] 1'0 + sync always + sync init + update \neg_res32 $1\neg_res32[0:0] + end + attribute \src "issuer_ls180.v:138192.7-138192.20" + process $proc$issuer_ls180.v:138192$6967 + assign { } { } + assign $1\r_busy[0:0] 1'0 + sync always + sync init + update \r_busy $1\r_busy[0:0] + end + attribute \src "issuer_ls180.v:138197.14-138197.39" + process $proc$issuer_ls180.v:138197$6968 + assign { } { } + assign $1\ra[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \ra $1\ra[63:0] + end + attribute \src "issuer_ls180.v:138206.14-138206.39" + process $proc$issuer_ls180.v:138206$6969 + assign { } { } + assign $1\rb[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \rb $1\rb[63:0] + end + attribute \src "issuer_ls180.v:138215.7-138215.20" + process $proc$issuer_ls180.v:138215$6970 + assign { } { } + assign $1\xer_so[0:0] 1'0 + sync always + sync init + update \xer_so $1\xer_so[0:0] + end + attribute \src "issuer_ls180.v:138223.3-138224.35" + process $proc$issuer_ls180.v:138223$6879 + assign { } { } + assign $0\neg_res32[0:0] \neg_res32$next + sync posedge \coresync_clk + update \neg_res32 $0\neg_res32[0:0] + end + attribute \src "issuer_ls180.v:138225.3-138226.31" + process $proc$issuer_ls180.v:138225$6880 + assign { } { } + assign $0\neg_res[0:0] \neg_res$next + sync posedge \coresync_clk + update \neg_res $0\neg_res[0:0] + end + attribute \src "issuer_ls180.v:138227.3-138228.29" + process $proc$issuer_ls180.v:138227$6881 + assign { } { } + assign $0\xer_so[0:0] \xer_so$next + sync posedge \coresync_clk + update \xer_so $0\xer_so[0:0] + end + attribute \src "issuer_ls180.v:138229.3-138230.21" + process $proc$issuer_ls180.v:138229$6882 + assign { } { } + assign $0\rb[63:0] \rb$next + sync posedge \coresync_clk + update \rb $0\rb[63:0] + end + attribute \src "issuer_ls180.v:138231.3-138232.21" + process $proc$issuer_ls180.v:138231$6883 + assign { } { } + assign $0\ra[63:0] \ra$next + sync posedge \coresync_clk + update \ra $0\ra[63:0] + end + attribute \src "issuer_ls180.v:138233.3-138234.51" + process $proc$issuer_ls180.v:138233$6884 + assign { } { } + assign $0\mul_op__insn_type[6:0] \mul_op__insn_type$next + sync posedge \coresync_clk + update \mul_op__insn_type $0\mul_op__insn_type[6:0] + end + attribute \src "issuer_ls180.v:138235.3-138236.47" + process $proc$issuer_ls180.v:138235$6885 + assign { } { } + assign $0\mul_op__fn_unit[11:0] \mul_op__fn_unit$next + sync posedge \coresync_clk + update \mul_op__fn_unit $0\mul_op__fn_unit[11:0] + end + attribute \src "issuer_ls180.v:138237.3-138238.61" + process $proc$issuer_ls180.v:138237$6886 + assign { } { } + assign $0\mul_op__imm_data__data[63:0] \mul_op__imm_data__data$next + sync posedge \coresync_clk + update \mul_op__imm_data__data $0\mul_op__imm_data__data[63:0] + end + attribute \src "issuer_ls180.v:138239.3-138240.57" + process $proc$issuer_ls180.v:138239$6887 + assign { } { } + assign $0\mul_op__imm_data__ok[0:0] \mul_op__imm_data__ok$next + sync posedge \coresync_clk + update \mul_op__imm_data__ok $0\mul_op__imm_data__ok[0:0] + end + attribute \src "issuer_ls180.v:138241.3-138242.45" + process $proc$issuer_ls180.v:138241$6888 + assign { } { } + assign $0\mul_op__rc__rc[0:0] \mul_op__rc__rc$next + sync posedge \coresync_clk + update \mul_op__rc__rc $0\mul_op__rc__rc[0:0] + end + attribute \src "issuer_ls180.v:138243.3-138244.45" + process $proc$issuer_ls180.v:138243$6889 + assign { } { } + assign $0\mul_op__rc__ok[0:0] \mul_op__rc__ok$next + sync posedge \coresync_clk + update \mul_op__rc__ok $0\mul_op__rc__ok[0:0] + end + attribute \src "issuer_ls180.v:138245.3-138246.45" + process $proc$issuer_ls180.v:138245$6890 + assign { } { } + assign $0\mul_op__oe__oe[0:0] \mul_op__oe__oe$next + sync posedge \coresync_clk + update \mul_op__oe__oe $0\mul_op__oe__oe[0:0] + end + attribute \src "issuer_ls180.v:138247.3-138248.45" + process $proc$issuer_ls180.v:138247$6891 + assign { } { } + assign $0\mul_op__oe__ok[0:0] \mul_op__oe__ok$next + sync posedge \coresync_clk + update \mul_op__oe__ok $0\mul_op__oe__ok[0:0] + end + attribute \src "issuer_ls180.v:138249.3-138250.51" + process $proc$issuer_ls180.v:138249$6892 + assign { } { } + assign $0\mul_op__write_cr0[0:0] \mul_op__write_cr0$next + sync posedge \coresync_clk + update \mul_op__write_cr0 $0\mul_op__write_cr0[0:0] + end + attribute \src "issuer_ls180.v:138251.3-138252.49" + process $proc$issuer_ls180.v:138251$6893 + assign { } { } + assign $0\mul_op__is_32bit[0:0] \mul_op__is_32bit$next + sync posedge \coresync_clk + update \mul_op__is_32bit $0\mul_op__is_32bit[0:0] + end + attribute \src "issuer_ls180.v:138253.3-138254.51" + process $proc$issuer_ls180.v:138253$6894 + assign { } { } + assign $0\mul_op__is_signed[0:0] \mul_op__is_signed$next + sync posedge \coresync_clk + update \mul_op__is_signed $0\mul_op__is_signed[0:0] + end + attribute \src "issuer_ls180.v:138255.3-138256.41" + process $proc$issuer_ls180.v:138255$6895 + assign { } { } + assign $0\mul_op__insn[31:0] \mul_op__insn$next + sync posedge \coresync_clk + update \mul_op__insn $0\mul_op__insn[31:0] + end + attribute \src "issuer_ls180.v:138257.3-138258.27" + process $proc$issuer_ls180.v:138257$6896 + assign { } { } + assign $0\muxid[1:0] \muxid$next + sync posedge \coresync_clk + update \muxid $0\muxid[1:0] + end + attribute \src "issuer_ls180.v:138259.3-138260.29" + process $proc$issuer_ls180.v:138259$6897 + assign { } { } + assign $0\r_busy[0:0] \r_busy$next + sync posedge \coresync_clk + update \r_busy $0\r_busy[0:0] + end + attribute \src "issuer_ls180.v:138339.3-138356.6" + process $proc$issuer_ls180.v:138339$6898 + assign { } { } + assign { } { } + assign { } { } + assign $0\r_busy$next[0:0]$6899 $2\r_busy$next[0:0]$6901 + attribute \src "issuer_ls180.v:138340.5-138340.29" + switch \initial + attribute \src "issuer_ls180.v:138340.9-138340.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\r_busy$next[0:0]$6900 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\r_busy$next[0:0]$6900 1'0 + case + assign $1\r_busy$next[0:0]$6900 \r_busy + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\r_busy$next[0:0]$6901 1'0 + case + assign $2\r_busy$next[0:0]$6901 $1\r_busy$next[0:0]$6900 + end + sync always + update \r_busy$next $0\r_busy$next[0:0]$6899 + end + attribute \src "issuer_ls180.v:138357.3-138369.6" + process $proc$issuer_ls180.v:138357$6902 + assign { } { } + assign { } { } + assign $0\muxid$next[1:0]$6903 $1\muxid$next[1:0]$6904 + attribute \src "issuer_ls180.v:138358.5-138358.29" + switch \initial + attribute \src "issuer_ls180.v:138358.9-138358.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\muxid$next[1:0]$6904 \muxid$52 + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\muxid$next[1:0]$6904 \muxid$52 + case + assign $1\muxid$next[1:0]$6904 \muxid + end + sync always + update \muxid$next $0\muxid$next[1:0]$6903 + end + attribute \src "issuer_ls180.v:138370.3-138405.6" + process $proc$issuer_ls180.v:138370$6905 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\mul_op__fn_unit$next[11:0]$6906 $1\mul_op__fn_unit$next[11:0]$6918 + assign { } { } + assign { } { } + assign $0\mul_op__insn$next[31:0]$6909 $1\mul_op__insn$next[31:0]$6921 + assign $0\mul_op__insn_type$next[6:0]$6910 $1\mul_op__insn_type$next[6:0]$6922 + assign $0\mul_op__is_32bit$next[0:0]$6911 $1\mul_op__is_32bit$next[0:0]$6923 + assign $0\mul_op__is_signed$next[0:0]$6912 $1\mul_op__is_signed$next[0:0]$6924 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\mul_op__write_cr0$next[0:0]$6917 $1\mul_op__write_cr0$next[0:0]$6929 + assign $0\mul_op__imm_data__data$next[63:0]$6907 $2\mul_op__imm_data__data$next[63:0]$6930 + assign $0\mul_op__imm_data__ok$next[0:0]$6908 $2\mul_op__imm_data__ok$next[0:0]$6931 + assign $0\mul_op__oe__oe$next[0:0]$6913 $2\mul_op__oe__oe$next[0:0]$6932 + assign $0\mul_op__oe__ok$next[0:0]$6914 $2\mul_op__oe__ok$next[0:0]$6933 + assign $0\mul_op__rc__ok$next[0:0]$6915 $2\mul_op__rc__ok$next[0:0]$6934 + assign $0\mul_op__rc__rc$next[0:0]$6916 $2\mul_op__rc__rc$next[0:0]$6935 + attribute \src "issuer_ls180.v:138371.5-138371.29" + switch \initial + attribute \src "issuer_ls180.v:138371.9-138371.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'-1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { $1\mul_op__insn$next[31:0]$6921 $1\mul_op__is_signed$next[0:0]$6924 $1\mul_op__is_32bit$next[0:0]$6923 $1\mul_op__write_cr0$next[0:0]$6929 $1\mul_op__oe__ok$next[0:0]$6926 $1\mul_op__oe__oe$next[0:0]$6925 $1\mul_op__rc__ok$next[0:0]$6927 $1\mul_op__rc__rc$next[0:0]$6928 $1\mul_op__imm_data__ok$next[0:0]$6920 $1\mul_op__imm_data__data$next[63:0]$6919 $1\mul_op__fn_unit$next[11:0]$6918 $1\mul_op__insn_type$next[6:0]$6922 } { \mul_op__insn$64 \mul_op__is_signed$63 \mul_op__is_32bit$62 \mul_op__write_cr0$61 \mul_op__oe__ok$60 \mul_op__oe__oe$59 \mul_op__rc__ok$58 \mul_op__rc__rc$57 \mul_op__imm_data__ok$56 \mul_op__imm_data__data$55 \mul_op__fn_unit$54 \mul_op__insn_type$53 } + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'1- + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { $1\mul_op__insn$next[31:0]$6921 $1\mul_op__is_signed$next[0:0]$6924 $1\mul_op__is_32bit$next[0:0]$6923 $1\mul_op__write_cr0$next[0:0]$6929 $1\mul_op__oe__ok$next[0:0]$6926 $1\mul_op__oe__oe$next[0:0]$6925 $1\mul_op__rc__ok$next[0:0]$6927 $1\mul_op__rc__rc$next[0:0]$6928 $1\mul_op__imm_data__ok$next[0:0]$6920 $1\mul_op__imm_data__data$next[63:0]$6919 $1\mul_op__fn_unit$next[11:0]$6918 $1\mul_op__insn_type$next[6:0]$6922 } { \mul_op__insn$64 \mul_op__is_signed$63 \mul_op__is_32bit$62 \mul_op__write_cr0$61 \mul_op__oe__ok$60 \mul_op__oe__oe$59 \mul_op__rc__ok$58 \mul_op__rc__rc$57 \mul_op__imm_data__ok$56 \mul_op__imm_data__data$55 \mul_op__fn_unit$54 \mul_op__insn_type$53 } + case + assign $1\mul_op__fn_unit$next[11:0]$6918 \mul_op__fn_unit + assign $1\mul_op__imm_data__data$next[63:0]$6919 \mul_op__imm_data__data + assign $1\mul_op__imm_data__ok$next[0:0]$6920 \mul_op__imm_data__ok + assign $1\mul_op__insn$next[31:0]$6921 \mul_op__insn + assign $1\mul_op__insn_type$next[6:0]$6922 \mul_op__insn_type + assign $1\mul_op__is_32bit$next[0:0]$6923 \mul_op__is_32bit + assign $1\mul_op__is_signed$next[0:0]$6924 \mul_op__is_signed + assign $1\mul_op__oe__oe$next[0:0]$6925 \mul_op__oe__oe + assign $1\mul_op__oe__ok$next[0:0]$6926 \mul_op__oe__ok + assign $1\mul_op__rc__ok$next[0:0]$6927 \mul_op__rc__ok + assign $1\mul_op__rc__rc$next[0:0]$6928 \mul_op__rc__rc + assign $1\mul_op__write_cr0$next[0:0]$6929 \mul_op__write_cr0 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $2\mul_op__imm_data__data$next[63:0]$6930 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\mul_op__imm_data__ok$next[0:0]$6931 1'0 + assign $2\mul_op__rc__rc$next[0:0]$6935 1'0 + assign $2\mul_op__rc__ok$next[0:0]$6934 1'0 + assign $2\mul_op__oe__oe$next[0:0]$6932 1'0 + assign $2\mul_op__oe__ok$next[0:0]$6933 1'0 + case + assign $2\mul_op__imm_data__data$next[63:0]$6930 $1\mul_op__imm_data__data$next[63:0]$6919 + assign $2\mul_op__imm_data__ok$next[0:0]$6931 $1\mul_op__imm_data__ok$next[0:0]$6920 + assign $2\mul_op__oe__oe$next[0:0]$6932 $1\mul_op__oe__oe$next[0:0]$6925 + assign $2\mul_op__oe__ok$next[0:0]$6933 $1\mul_op__oe__ok$next[0:0]$6926 + assign $2\mul_op__rc__ok$next[0:0]$6934 $1\mul_op__rc__ok$next[0:0]$6927 + assign $2\mul_op__rc__rc$next[0:0]$6935 $1\mul_op__rc__rc$next[0:0]$6928 + end + sync always + update \mul_op__fn_unit$next $0\mul_op__fn_unit$next[11:0]$6906 + update \mul_op__imm_data__data$next $0\mul_op__imm_data__data$next[63:0]$6907 + update \mul_op__imm_data__ok$next $0\mul_op__imm_data__ok$next[0:0]$6908 + update \mul_op__insn$next $0\mul_op__insn$next[31:0]$6909 + update \mul_op__insn_type$next $0\mul_op__insn_type$next[6:0]$6910 + update \mul_op__is_32bit$next $0\mul_op__is_32bit$next[0:0]$6911 + update \mul_op__is_signed$next $0\mul_op__is_signed$next[0:0]$6912 + update \mul_op__oe__oe$next $0\mul_op__oe__oe$next[0:0]$6913 + update \mul_op__oe__ok$next $0\mul_op__oe__ok$next[0:0]$6914 + update \mul_op__rc__ok$next $0\mul_op__rc__ok$next[0:0]$6915 + update \mul_op__rc__rc$next $0\mul_op__rc__rc$next[0:0]$6916 + update \mul_op__write_cr0$next $0\mul_op__write_cr0$next[0:0]$6917 + end + attribute \src "issuer_ls180.v:138406.3-138418.6" + process $proc$issuer_ls180.v:138406$6936 + assign { } { } + assign { } { } + assign $0\ra$next[63:0]$6937 $1\ra$next[63:0]$6938 + attribute \src "issuer_ls180.v:138407.5-138407.29" + switch \initial + attribute \src "issuer_ls180.v:138407.9-138407.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\ra$next[63:0]$6938 \ra$65 + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\ra$next[63:0]$6938 \ra$65 + case + assign $1\ra$next[63:0]$6938 \ra + end + sync always + update \ra$next $0\ra$next[63:0]$6937 + end + attribute \src "issuer_ls180.v:138419.3-138431.6" + process $proc$issuer_ls180.v:138419$6939 + assign { } { } + assign { } { } + assign $0\rb$next[63:0]$6940 $1\rb$next[63:0]$6941 + attribute \src "issuer_ls180.v:138420.5-138420.29" + switch \initial + attribute \src "issuer_ls180.v:138420.9-138420.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\rb$next[63:0]$6941 \rb$66 + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\rb$next[63:0]$6941 \rb$66 + case + assign $1\rb$next[63:0]$6941 \rb + end + sync always + update \rb$next $0\rb$next[63:0]$6940 + end + attribute \src "issuer_ls180.v:138432.3-138444.6" + process $proc$issuer_ls180.v:138432$6942 + assign { } { } + assign { } { } + assign $0\xer_so$next[0:0]$6943 $1\xer_so$next[0:0]$6944 + attribute \src "issuer_ls180.v:138433.5-138433.29" + switch \initial + attribute \src "issuer_ls180.v:138433.9-138433.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\xer_so$next[0:0]$6944 \xer_so$67 + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\xer_so$next[0:0]$6944 \xer_so$67 + case + assign $1\xer_so$next[0:0]$6944 \xer_so + end + sync always + update \xer_so$next $0\xer_so$next[0:0]$6943 + end + attribute \src "issuer_ls180.v:138445.3-138457.6" + process $proc$issuer_ls180.v:138445$6945 + assign { } { } + assign { } { } + assign $0\neg_res$next[0:0]$6946 $1\neg_res$next[0:0]$6947 + attribute \src "issuer_ls180.v:138446.5-138446.29" + switch \initial + attribute \src "issuer_ls180.v:138446.9-138446.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\neg_res$next[0:0]$6947 \neg_res$68 + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\neg_res$next[0:0]$6947 \neg_res$68 + case + assign $1\neg_res$next[0:0]$6947 \neg_res + end + sync always + update \neg_res$next $0\neg_res$next[0:0]$6946 + end + attribute \src "issuer_ls180.v:138458.3-138470.6" + process $proc$issuer_ls180.v:138458$6948 + assign { } { } + assign { } { } + assign $0\neg_res32$next[0:0]$6949 $1\neg_res32$next[0:0]$6950 + attribute \src "issuer_ls180.v:138459.5-138459.29" + switch \initial + attribute \src "issuer_ls180.v:138459.9-138459.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\neg_res32$next[0:0]$6950 \neg_res32$69 + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\neg_res32$next[0:0]$6950 \neg_res32$69 + case + assign $1\neg_res32$next[0:0]$6950 \neg_res32 + end + sync always + update \neg_res32$next $0\neg_res32$next[0:0]$6949 + end + connect \$50 $and$issuer_ls180.v:138222$6878_Y + connect \p_ready_o \n_i_rdy_data + connect \n_valid_o \r_busy + connect \neg_res32$69 \mul1_neg_res32 + connect \neg_res$68 \mul1_neg_res + connect \xer_so$67 \mul1_xer_so$48 + connect \rb$66 \mul1_rb$47 + connect \ra$65 \mul1_ra$46 + connect { \mul_op__insn$64 \mul_op__is_signed$63 \mul_op__is_32bit$62 \mul_op__write_cr0$61 \mul_op__oe__ok$60 \mul_op__oe__oe$59 \mul_op__rc__ok$58 \mul_op__rc__rc$57 \mul_op__imm_data__ok$56 \mul_op__imm_data__data$55 \mul_op__fn_unit$54 \mul_op__insn_type$53 } { \mul1_mul_op__insn$45 \mul1_mul_op__is_signed$44 \mul1_mul_op__is_32bit$43 \mul1_mul_op__write_cr0$42 \mul1_mul_op__oe__ok$41 \mul1_mul_op__oe__oe$40 \mul1_mul_op__rc__ok$39 \mul1_mul_op__rc__rc$38 \mul1_mul_op__imm_data__ok$37 \mul1_mul_op__imm_data__data$36 \mul1_mul_op__fn_unit$35 \mul1_mul_op__insn_type$34 } + connect \muxid$52 \mul1_muxid$33 + connect \p_valid_i_p_ready_o \$50 + connect \n_i_rdy_data \n_ready_i + connect \p_valid_i$49 \p_valid_i + connect \mul1_xer_so \input_xer_so$32 + connect \mul1_rb \input_rb$31 + connect \mul1_ra \input_ra$30 + connect { \mul1_mul_op__insn \mul1_mul_op__is_signed \mul1_mul_op__is_32bit \mul1_mul_op__write_cr0 \mul1_mul_op__oe__ok \mul1_mul_op__oe__oe \mul1_mul_op__rc__ok \mul1_mul_op__rc__rc \mul1_mul_op__imm_data__ok \mul1_mul_op__imm_data__data \mul1_mul_op__fn_unit \mul1_mul_op__insn_type } { \input_mul_op__insn$29 \input_mul_op__is_signed$28 \input_mul_op__is_32bit$27 \input_mul_op__write_cr0$26 \input_mul_op__oe__ok$25 \input_mul_op__oe__oe$24 \input_mul_op__rc__ok$23 \input_mul_op__rc__rc$22 \input_mul_op__imm_data__ok$21 \input_mul_op__imm_data__data$20 \input_mul_op__fn_unit$19 \input_mul_op__insn_type$18 } + connect \mul1_muxid \input_muxid$17 + connect \input_xer_so \xer_so$16 + connect \input_rb \rb$15 + connect \input_ra \ra$14 + connect { \input_mul_op__insn \input_mul_op__is_signed \input_mul_op__is_32bit \input_mul_op__write_cr0 \input_mul_op__oe__ok \input_mul_op__oe__oe \input_mul_op__rc__ok \input_mul_op__rc__rc \input_mul_op__imm_data__ok \input_mul_op__imm_data__data \input_mul_op__fn_unit \input_mul_op__insn_type } { \mul_op__insn$13 \mul_op__is_signed$12 \mul_op__is_32bit$11 \mul_op__write_cr0$10 \mul_op__oe__ok$9 \mul_op__oe__oe$8 \mul_op__rc__ok$7 \mul_op__rc__rc$6 \mul_op__imm_data__ok$5 \mul_op__imm_data__data$4 \mul_op__fn_unit$3 \mul_op__insn_type$2 } + connect \input_muxid \muxid$1 +end +attribute \src "issuer_ls180.v:138497.1-139402.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.fus.mul0.alu_mul0.mul_pipe2" +attribute \generator "nMigen" +module \mul_pipe2 + attribute \src "issuer_ls180.v:138498.7-138498.20" + wire $0\initial[0:0] + attribute \src "issuer_ls180.v:139296.3-139331.6" + wire width 12 $0\mul_op__fn_unit$3$next[11:0]$7014 + attribute \src "issuer_ls180.v:139194.3-139195.53" + wire width 12 $0\mul_op__fn_unit$3[11:0]$6982 + attribute \src "issuer_ls180.v:138779.14-138779.43" + wire width 12 $0\mul_op__fn_unit$3[11:0]$7058 + attribute \src "issuer_ls180.v:139296.3-139331.6" + wire width 64 $0\mul_op__imm_data__data$4$next[63:0]$7015 + attribute \src "issuer_ls180.v:139196.3-139197.67" + wire width 64 $0\mul_op__imm_data__data$4[63:0]$6984 + attribute \src "issuer_ls180.v:138803.14-138803.63" + wire width 64 $0\mul_op__imm_data__data$4[63:0]$7060 + attribute \src "issuer_ls180.v:139296.3-139331.6" + wire $0\mul_op__imm_data__ok$5$next[0:0]$7016 + attribute \src "issuer_ls180.v:139198.3-139199.63" + wire $0\mul_op__imm_data__ok$5[0:0]$6986 + attribute \src "issuer_ls180.v:138812.7-138812.38" + wire $0\mul_op__imm_data__ok$5[0:0]$7062 + attribute \src "issuer_ls180.v:139296.3-139331.6" + wire width 32 $0\mul_op__insn$13$next[31:0]$7017 + attribute \src "issuer_ls180.v:139214.3-139215.49" + wire width 32 $0\mul_op__insn$13[31:0]$7002 + attribute \src "issuer_ls180.v:138819.14-138819.39" + wire width 32 $0\mul_op__insn$13[31:0]$7064 + attribute \src "issuer_ls180.v:139296.3-139331.6" + wire width 7 $0\mul_op__insn_type$2$next[6:0]$7018 + attribute \src "issuer_ls180.v:139192.3-139193.57" + wire width 7 $0\mul_op__insn_type$2[6:0]$6980 + attribute \src "issuer_ls180.v:138976.13-138976.42" + wire width 7 $0\mul_op__insn_type$2[6:0]$7066 + attribute \src "issuer_ls180.v:139296.3-139331.6" + wire $0\mul_op__is_32bit$11$next[0:0]$7019 + attribute \src "issuer_ls180.v:139210.3-139211.57" + wire $0\mul_op__is_32bit$11[0:0]$6998 + attribute \src "issuer_ls180.v:139059.7-139059.35" + wire $0\mul_op__is_32bit$11[0:0]$7068 + attribute \src "issuer_ls180.v:139296.3-139331.6" + wire $0\mul_op__is_signed$12$next[0:0]$7020 + attribute \src "issuer_ls180.v:139212.3-139213.59" + wire $0\mul_op__is_signed$12[0:0]$7000 + attribute \src "issuer_ls180.v:139068.7-139068.36" + wire $0\mul_op__is_signed$12[0:0]$7070 + attribute \src "issuer_ls180.v:139296.3-139331.6" + wire $0\mul_op__oe__oe$8$next[0:0]$7021 + attribute \src "issuer_ls180.v:139204.3-139205.51" + wire $0\mul_op__oe__oe$8[0:0]$6992 + attribute \src "issuer_ls180.v:139079.7-139079.32" + wire $0\mul_op__oe__oe$8[0:0]$7072 + attribute \src "issuer_ls180.v:139296.3-139331.6" + wire $0\mul_op__oe__ok$9$next[0:0]$7022 + attribute \src "issuer_ls180.v:139206.3-139207.51" + wire $0\mul_op__oe__ok$9[0:0]$6994 + attribute \src "issuer_ls180.v:139088.7-139088.32" + wire $0\mul_op__oe__ok$9[0:0]$7074 + attribute \src "issuer_ls180.v:139296.3-139331.6" + wire $0\mul_op__rc__ok$7$next[0:0]$7023 + attribute \src "issuer_ls180.v:139202.3-139203.51" + wire $0\mul_op__rc__ok$7[0:0]$6990 + attribute \src "issuer_ls180.v:139097.7-139097.32" + wire $0\mul_op__rc__ok$7[0:0]$7076 + attribute \src "issuer_ls180.v:139296.3-139331.6" + wire $0\mul_op__rc__rc$6$next[0:0]$7024 + attribute \src "issuer_ls180.v:139200.3-139201.51" + wire $0\mul_op__rc__rc$6[0:0]$6988 + attribute \src "issuer_ls180.v:139106.7-139106.32" + wire $0\mul_op__rc__rc$6[0:0]$7078 + attribute \src "issuer_ls180.v:139296.3-139331.6" + wire $0\mul_op__write_cr0$10$next[0:0]$7025 + attribute \src "issuer_ls180.v:139208.3-139209.59" + wire $0\mul_op__write_cr0$10[0:0]$6996 + attribute \src "issuer_ls180.v:139113.7-139113.36" + wire $0\mul_op__write_cr0$10[0:0]$7080 + attribute \src "issuer_ls180.v:139283.3-139295.6" + wire width 2 $0\muxid$1$next[1:0]$7011 + attribute \src "issuer_ls180.v:139216.3-139217.33" + wire width 2 $0\muxid$1[1:0]$7004 + attribute \src "issuer_ls180.v:139122.13-139122.29" + wire width 2 $0\muxid$1[1:0]$7082 + attribute \src "issuer_ls180.v:139358.3-139370.6" + wire $0\neg_res$15$next[0:0]$7051 + attribute \src "issuer_ls180.v:139186.3-139187.39" + wire $0\neg_res$15[0:0]$6975 + attribute \src "issuer_ls180.v:139137.7-139137.26" + wire $0\neg_res$15[0:0]$7084 + attribute \src "issuer_ls180.v:139371.3-139383.6" + wire $0\neg_res32$16$next[0:0]$7054 + attribute \src "issuer_ls180.v:139184.3-139185.43" + wire $0\neg_res32$16[0:0]$6973 + attribute \src "issuer_ls180.v:139146.7-139146.28" + wire $0\neg_res32$16[0:0]$7086 + attribute \src "issuer_ls180.v:139332.3-139344.6" + wire width 129 $0\o$next[128:0]$7045 + attribute \src "issuer_ls180.v:139190.3-139191.19" + wire width 129 $0\o[128:0] + attribute \src "issuer_ls180.v:139265.3-139282.6" + wire $0\r_busy$next[0:0]$7007 + attribute \src "issuer_ls180.v:139218.3-139219.29" + wire $0\r_busy[0:0] + attribute \src "issuer_ls180.v:139345.3-139357.6" + wire $0\xer_so$14$next[0:0]$7048 + attribute \src "issuer_ls180.v:139188.3-139189.37" + wire $0\xer_so$14[0:0]$6977 + attribute \src "issuer_ls180.v:139178.7-139178.25" + wire $0\xer_so$14[0:0]$7090 + attribute \src "issuer_ls180.v:139296.3-139331.6" + wire width 12 $1\mul_op__fn_unit$3$next[11:0]$7026 + attribute \src "issuer_ls180.v:139296.3-139331.6" + wire width 64 $1\mul_op__imm_data__data$4$next[63:0]$7027 + attribute \src "issuer_ls180.v:139296.3-139331.6" + wire $1\mul_op__imm_data__ok$5$next[0:0]$7028 + attribute \src "issuer_ls180.v:139296.3-139331.6" + wire width 32 $1\mul_op__insn$13$next[31:0]$7029 + attribute \src "issuer_ls180.v:139296.3-139331.6" + wire width 7 $1\mul_op__insn_type$2$next[6:0]$7030 + attribute \src "issuer_ls180.v:139296.3-139331.6" + wire $1\mul_op__is_32bit$11$next[0:0]$7031 + attribute \src "issuer_ls180.v:139296.3-139331.6" + wire $1\mul_op__is_signed$12$next[0:0]$7032 + attribute \src "issuer_ls180.v:139296.3-139331.6" + wire $1\mul_op__oe__oe$8$next[0:0]$7033 + attribute \src "issuer_ls180.v:139296.3-139331.6" + wire $1\mul_op__oe__ok$9$next[0:0]$7034 + attribute \src "issuer_ls180.v:139296.3-139331.6" + wire $1\mul_op__rc__ok$7$next[0:0]$7035 + attribute \src "issuer_ls180.v:139296.3-139331.6" + wire $1\mul_op__rc__rc$6$next[0:0]$7036 + attribute \src "issuer_ls180.v:139296.3-139331.6" + wire $1\mul_op__write_cr0$10$next[0:0]$7037 + attribute \src "issuer_ls180.v:139283.3-139295.6" + wire width 2 $1\muxid$1$next[1:0]$7012 + attribute \src "issuer_ls180.v:139358.3-139370.6" + wire $1\neg_res$15$next[0:0]$7052 + attribute \src "issuer_ls180.v:139371.3-139383.6" + wire $1\neg_res32$16$next[0:0]$7055 + attribute \src "issuer_ls180.v:139332.3-139344.6" + wire width 129 $1\o$next[128:0]$7046 + attribute \src "issuer_ls180.v:139153.15-139153.57" + wire width 129 $1\o[128:0] + attribute \src "issuer_ls180.v:139265.3-139282.6" + wire $1\r_busy$next[0:0]$7008 + attribute \src "issuer_ls180.v:139167.7-139167.20" + wire $1\r_busy[0:0] + attribute \src "issuer_ls180.v:139345.3-139357.6" + wire $1\xer_so$14$next[0:0]$7049 + attribute \src "issuer_ls180.v:139296.3-139331.6" + wire width 64 $2\mul_op__imm_data__data$4$next[63:0]$7038 + attribute \src "issuer_ls180.v:139296.3-139331.6" + wire $2\mul_op__imm_data__ok$5$next[0:0]$7039 + attribute \src "issuer_ls180.v:139296.3-139331.6" + wire $2\mul_op__oe__oe$8$next[0:0]$7040 + attribute \src "issuer_ls180.v:139296.3-139331.6" + wire $2\mul_op__oe__ok$9$next[0:0]$7041 + attribute \src "issuer_ls180.v:139296.3-139331.6" + wire $2\mul_op__rc__ok$7$next[0:0]$7042 + attribute \src "issuer_ls180.v:139296.3-139331.6" + wire $2\mul_op__rc__rc$6$next[0:0]$7043 + attribute \src "issuer_ls180.v:139265.3-139282.6" + wire $2\r_busy$next[0:0]$7009 + attribute \src "issuer_ls180.v:139183.18-139183.118" + wire $and$issuer_ls180.v:139183$6971_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" + wire \$34 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" + wire input 41 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" + wire input 1 \coresync_rst + attribute \src "issuer_ls180.v:138498.7-138498.15" + wire \initial + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 \mul2_mul_op__fn_unit + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 \mul2_mul_op__fn_unit$19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \mul2_mul_op__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \mul2_mul_op__imm_data__data$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul2_mul_op__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul2_mul_op__imm_data__ok$21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \mul2_mul_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \mul2_mul_op__insn$29 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \mul2_mul_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \mul2_mul_op__insn_type$18 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul2_mul_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul2_mul_op__is_32bit$27 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul2_mul_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul2_mul_op__is_signed$28 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul2_mul_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul2_mul_op__oe__oe$24 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul2_mul_op__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul2_mul_op__oe__ok$25 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul2_mul_op__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul2_mul_op__rc__ok$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul2_mul_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul2_mul_op__rc__rc$22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul2_mul_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul2_mul_op__write_cr0$26 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \mul2_muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \mul2_muxid$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:11" + wire \mul2_neg_res + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:23" + wire \mul2_neg_res$31 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:12" + wire \mul2_neg_res32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:24" + wire \mul2_neg_res32$32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 129 \mul2_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \mul2_ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \mul2_rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire \mul2_xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire \mul2_xer_so$30 + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 input 6 \mul_op__fn_unit + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 output 26 \mul_op__fn_unit$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 \mul_op__fn_unit$3$next + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 \mul_op__fn_unit$38 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 input 7 \mul_op__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \mul_op__imm_data__data$39 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 output 27 \mul_op__imm_data__data$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \mul_op__imm_data__data$4$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 8 \mul_op__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_op__imm_data__ok$40 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 28 \mul_op__imm_data__ok$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_op__imm_data__ok$5$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 16 \mul_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 output 36 \mul_op__insn$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \mul_op__insn$13$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \mul_op__insn$48 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 input 5 \mul_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 output 25 \mul_op__insn_type$2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \mul_op__insn_type$2$next + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \mul_op__insn_type$37 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 14 \mul_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 34 \mul_op__is_32bit$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_op__is_32bit$11$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_op__is_32bit$46 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 15 \mul_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 35 \mul_op__is_signed$12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_op__is_signed$12$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_op__is_signed$47 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 11 \mul_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_op__oe__oe$43 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 31 \mul_op__oe__oe$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_op__oe__oe$8$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 12 \mul_op__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_op__oe__ok$44 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 32 \mul_op__oe__ok$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_op__oe__ok$9$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 10 \mul_op__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_op__rc__ok$42 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 30 \mul_op__rc__ok$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_op__rc__ok$7$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 9 \mul_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_op__rc__rc$41 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 29 \mul_op__rc__rc$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_op__rc__rc$6$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 13 \mul_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 33 \mul_op__write_cr0$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_op__write_cr0$10$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_op__write_cr0$45 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 input 4 \muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 output 24 \muxid$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \muxid$1$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \muxid$36 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:619" + wire \n_i_rdy_data + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" + wire input 23 \n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" + wire output 22 \n_valid_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:11" + wire input 20 \neg_res + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:23" + wire output 39 \neg_res$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:23" + wire \neg_res$15$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:23" + wire \neg_res$51 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:12" + wire input 21 \neg_res32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:24" + wire output 40 \neg_res32$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:24" + wire \neg_res32$16$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:24" + wire \neg_res32$52 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 129 output 37 \o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 129 \o$49 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 129 \o$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" + wire output 3 \p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" + wire input 2 \p_valid_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:621" + wire \p_valid_i$33 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" + wire \p_valid_i_p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615" + wire \r_busy + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615" + wire \r_busy$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 17 \ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 18 \rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire input 19 \xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire output 38 \xer_so$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire \xer_so$14$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire \xer_so$50 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" + cell $and $and$issuer_ls180.v:139183$6971 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \p_valid_i$33 + connect \B \p_ready_o + connect \Y $and$issuer_ls180.v:139183$6971_Y + end + attribute \module_not_derived 1 + attribute \src "issuer_ls180.v:139220.8-139256.4" + cell \mul2 \mul2 + connect \mul_op__fn_unit \mul2_mul_op__fn_unit + connect \mul_op__fn_unit$3 \mul2_mul_op__fn_unit$19 + connect \mul_op__imm_data__data \mul2_mul_op__imm_data__data + connect \mul_op__imm_data__data$4 \mul2_mul_op__imm_data__data$20 + connect \mul_op__imm_data__ok \mul2_mul_op__imm_data__ok + connect \mul_op__imm_data__ok$5 \mul2_mul_op__imm_data__ok$21 + connect \mul_op__insn \mul2_mul_op__insn + connect \mul_op__insn$13 \mul2_mul_op__insn$29 + connect \mul_op__insn_type \mul2_mul_op__insn_type + connect \mul_op__insn_type$2 \mul2_mul_op__insn_type$18 + connect \mul_op__is_32bit \mul2_mul_op__is_32bit + connect \mul_op__is_32bit$11 \mul2_mul_op__is_32bit$27 + connect \mul_op__is_signed \mul2_mul_op__is_signed + connect \mul_op__is_signed$12 \mul2_mul_op__is_signed$28 + connect \mul_op__oe__oe \mul2_mul_op__oe__oe + connect \mul_op__oe__oe$8 \mul2_mul_op__oe__oe$24 + connect \mul_op__oe__ok \mul2_mul_op__oe__ok + connect \mul_op__oe__ok$9 \mul2_mul_op__oe__ok$25 + connect \mul_op__rc__ok \mul2_mul_op__rc__ok + connect \mul_op__rc__ok$7 \mul2_mul_op__rc__ok$23 + connect \mul_op__rc__rc \mul2_mul_op__rc__rc + connect \mul_op__rc__rc$6 \mul2_mul_op__rc__rc$22 + connect \mul_op__write_cr0 \mul2_mul_op__write_cr0 + connect \mul_op__write_cr0$10 \mul2_mul_op__write_cr0$26 + connect \muxid \mul2_muxid + connect \muxid$1 \mul2_muxid$17 + connect \neg_res \mul2_neg_res + connect \neg_res$15 \mul2_neg_res$31 + connect \neg_res32 \mul2_neg_res32 + connect \neg_res32$16 \mul2_neg_res32$32 + connect \o \mul2_o + connect \ra \mul2_ra + connect \rb \mul2_rb + connect \xer_so \mul2_xer_so + connect \xer_so$14 \mul2_xer_so$30 + end + attribute \module_not_derived 1 + attribute \src "issuer_ls180.v:139257.10-139260.4" + cell \n$94 \n + connect \n_ready_i \n_ready_i + connect \n_valid_o \n_valid_o + end + attribute \module_not_derived 1 + attribute \src "issuer_ls180.v:139261.10-139264.4" + cell \p$93 \p + connect \p_ready_o \p_ready_o + connect \p_valid_i \p_valid_i + end + attribute \src "issuer_ls180.v:138498.7-138498.20" + process $proc$issuer_ls180.v:138498$7056 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "issuer_ls180.v:138779.14-138779.43" + process $proc$issuer_ls180.v:138779$7057 + assign { } { } + assign $0\mul_op__fn_unit$3[11:0]$7058 12'000000000000 + sync always + sync init + update \mul_op__fn_unit$3 $0\mul_op__fn_unit$3[11:0]$7058 + end + attribute \src "issuer_ls180.v:138803.14-138803.63" + process $proc$issuer_ls180.v:138803$7059 + assign { } { } + assign $0\mul_op__imm_data__data$4[63:0]$7060 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \mul_op__imm_data__data$4 $0\mul_op__imm_data__data$4[63:0]$7060 + end + attribute \src "issuer_ls180.v:138812.7-138812.38" + process $proc$issuer_ls180.v:138812$7061 + assign { } { } + assign $0\mul_op__imm_data__ok$5[0:0]$7062 1'0 + sync always + sync init + update \mul_op__imm_data__ok$5 $0\mul_op__imm_data__ok$5[0:0]$7062 + end + attribute \src "issuer_ls180.v:138819.14-138819.39" + process $proc$issuer_ls180.v:138819$7063 + assign { } { } + assign $0\mul_op__insn$13[31:0]$7064 0 + sync always + sync init + update \mul_op__insn$13 $0\mul_op__insn$13[31:0]$7064 + end + attribute \src "issuer_ls180.v:138976.13-138976.42" + process $proc$issuer_ls180.v:138976$7065 + assign { } { } + assign $0\mul_op__insn_type$2[6:0]$7066 7'0000000 + sync always + sync init + update \mul_op__insn_type$2 $0\mul_op__insn_type$2[6:0]$7066 + end + attribute \src "issuer_ls180.v:139059.7-139059.35" + process $proc$issuer_ls180.v:139059$7067 + assign { } { } + assign $0\mul_op__is_32bit$11[0:0]$7068 1'0 + sync always + sync init + update \mul_op__is_32bit$11 $0\mul_op__is_32bit$11[0:0]$7068 + end + attribute \src "issuer_ls180.v:139068.7-139068.36" + process $proc$issuer_ls180.v:139068$7069 + assign { } { } + assign $0\mul_op__is_signed$12[0:0]$7070 1'0 + sync always + sync init + update \mul_op__is_signed$12 $0\mul_op__is_signed$12[0:0]$7070 + end + attribute \src "issuer_ls180.v:139079.7-139079.32" + process $proc$issuer_ls180.v:139079$7071 + assign { } { } + assign $0\mul_op__oe__oe$8[0:0]$7072 1'0 + sync always + sync init + update \mul_op__oe__oe$8 $0\mul_op__oe__oe$8[0:0]$7072 + end + attribute \src "issuer_ls180.v:139088.7-139088.32" + process $proc$issuer_ls180.v:139088$7073 + assign { } { } + assign $0\mul_op__oe__ok$9[0:0]$7074 1'0 + sync always + sync init + update \mul_op__oe__ok$9 $0\mul_op__oe__ok$9[0:0]$7074 + end + attribute \src "issuer_ls180.v:139097.7-139097.32" + process $proc$issuer_ls180.v:139097$7075 + assign { } { } + assign $0\mul_op__rc__ok$7[0:0]$7076 1'0 + sync always + sync init + update \mul_op__rc__ok$7 $0\mul_op__rc__ok$7[0:0]$7076 + end + attribute \src "issuer_ls180.v:139106.7-139106.32" + process $proc$issuer_ls180.v:139106$7077 + assign { } { } + assign $0\mul_op__rc__rc$6[0:0]$7078 1'0 + sync always + sync init + update \mul_op__rc__rc$6 $0\mul_op__rc__rc$6[0:0]$7078 + end + attribute \src "issuer_ls180.v:139113.7-139113.36" + process $proc$issuer_ls180.v:139113$7079 + assign { } { } + assign $0\mul_op__write_cr0$10[0:0]$7080 1'0 + sync always + sync init + update \mul_op__write_cr0$10 $0\mul_op__write_cr0$10[0:0]$7080 + end + attribute \src "issuer_ls180.v:139122.13-139122.29" + process $proc$issuer_ls180.v:139122$7081 + assign { } { } + assign $0\muxid$1[1:0]$7082 2'00 + sync always + sync init + update \muxid$1 $0\muxid$1[1:0]$7082 + end + attribute \src "issuer_ls180.v:139137.7-139137.26" + process $proc$issuer_ls180.v:139137$7083 + assign { } { } + assign $0\neg_res$15[0:0]$7084 1'0 + sync always + sync init + update \neg_res$15 $0\neg_res$15[0:0]$7084 + end + attribute \src "issuer_ls180.v:139146.7-139146.28" + process $proc$issuer_ls180.v:139146$7085 + assign { } { } + assign $0\neg_res32$16[0:0]$7086 1'0 + sync always + sync init + update \neg_res32$16 $0\neg_res32$16[0:0]$7086 + end + attribute \src "issuer_ls180.v:139153.15-139153.57" + process $proc$issuer_ls180.v:139153$7087 + assign { } { } + assign $1\o[128:0] 129'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \o $1\o[128:0] + end + attribute \src "issuer_ls180.v:139167.7-139167.20" + process $proc$issuer_ls180.v:139167$7088 + assign { } { } + assign $1\r_busy[0:0] 1'0 + sync always + sync init + update \r_busy $1\r_busy[0:0] + end + attribute \src "issuer_ls180.v:139178.7-139178.25" + process $proc$issuer_ls180.v:139178$7089 + assign { } { } + assign $0\xer_so$14[0:0]$7090 1'0 + sync always + sync init + update \xer_so$14 $0\xer_so$14[0:0]$7090 + end + attribute \src "issuer_ls180.v:139184.3-139185.43" + process $proc$issuer_ls180.v:139184$6972 + assign { } { } + assign $0\neg_res32$16[0:0]$6973 \neg_res32$16$next + sync posedge \coresync_clk + update \neg_res32$16 $0\neg_res32$16[0:0]$6973 + end + attribute \src "issuer_ls180.v:139186.3-139187.39" + process $proc$issuer_ls180.v:139186$6974 + assign { } { } + assign $0\neg_res$15[0:0]$6975 \neg_res$15$next + sync posedge \coresync_clk + update \neg_res$15 $0\neg_res$15[0:0]$6975 + end + attribute \src "issuer_ls180.v:139188.3-139189.37" + process $proc$issuer_ls180.v:139188$6976 + assign { } { } + assign $0\xer_so$14[0:0]$6977 \xer_so$14$next + sync posedge \coresync_clk + update \xer_so$14 $0\xer_so$14[0:0]$6977 + end + attribute \src "issuer_ls180.v:139190.3-139191.19" + process $proc$issuer_ls180.v:139190$6978 + assign { } { } + assign $0\o[128:0] \o$next + sync posedge \coresync_clk + update \o $0\o[128:0] + end + attribute \src "issuer_ls180.v:139192.3-139193.57" + process $proc$issuer_ls180.v:139192$6979 + assign { } { } + assign $0\mul_op__insn_type$2[6:0]$6980 \mul_op__insn_type$2$next + sync posedge \coresync_clk + update \mul_op__insn_type$2 $0\mul_op__insn_type$2[6:0]$6980 + end + attribute \src "issuer_ls180.v:139194.3-139195.53" + process $proc$issuer_ls180.v:139194$6981 + assign { } { } + assign $0\mul_op__fn_unit$3[11:0]$6982 \mul_op__fn_unit$3$next + sync posedge \coresync_clk + update \mul_op__fn_unit$3 $0\mul_op__fn_unit$3[11:0]$6982 + end + attribute \src "issuer_ls180.v:139196.3-139197.67" + process $proc$issuer_ls180.v:139196$6983 + assign { } { } + assign $0\mul_op__imm_data__data$4[63:0]$6984 \mul_op__imm_data__data$4$next + sync posedge \coresync_clk + update \mul_op__imm_data__data$4 $0\mul_op__imm_data__data$4[63:0]$6984 + end + attribute \src "issuer_ls180.v:139198.3-139199.63" + process $proc$issuer_ls180.v:139198$6985 + assign { } { } + assign $0\mul_op__imm_data__ok$5[0:0]$6986 \mul_op__imm_data__ok$5$next + sync posedge \coresync_clk + update \mul_op__imm_data__ok$5 $0\mul_op__imm_data__ok$5[0:0]$6986 + end + attribute \src "issuer_ls180.v:139200.3-139201.51" + process $proc$issuer_ls180.v:139200$6987 + assign { } { } + assign $0\mul_op__rc__rc$6[0:0]$6988 \mul_op__rc__rc$6$next + sync posedge \coresync_clk + update \mul_op__rc__rc$6 $0\mul_op__rc__rc$6[0:0]$6988 + end + attribute \src "issuer_ls180.v:139202.3-139203.51" + process $proc$issuer_ls180.v:139202$6989 + assign { } { } + assign $0\mul_op__rc__ok$7[0:0]$6990 \mul_op__rc__ok$7$next + sync posedge \coresync_clk + update \mul_op__rc__ok$7 $0\mul_op__rc__ok$7[0:0]$6990 + end + attribute \src "issuer_ls180.v:139204.3-139205.51" + process $proc$issuer_ls180.v:139204$6991 + assign { } { } + assign $0\mul_op__oe__oe$8[0:0]$6992 \mul_op__oe__oe$8$next + sync posedge \coresync_clk + update \mul_op__oe__oe$8 $0\mul_op__oe__oe$8[0:0]$6992 + end + attribute \src "issuer_ls180.v:139206.3-139207.51" + process $proc$issuer_ls180.v:139206$6993 + assign { } { } + assign $0\mul_op__oe__ok$9[0:0]$6994 \mul_op__oe__ok$9$next + sync posedge \coresync_clk + update \mul_op__oe__ok$9 $0\mul_op__oe__ok$9[0:0]$6994 + end + attribute \src "issuer_ls180.v:139208.3-139209.59" + process $proc$issuer_ls180.v:139208$6995 + assign { } { } + assign $0\mul_op__write_cr0$10[0:0]$6996 \mul_op__write_cr0$10$next + sync posedge \coresync_clk + update \mul_op__write_cr0$10 $0\mul_op__write_cr0$10[0:0]$6996 + end + attribute \src "issuer_ls180.v:139210.3-139211.57" + process $proc$issuer_ls180.v:139210$6997 + assign { } { } + assign $0\mul_op__is_32bit$11[0:0]$6998 \mul_op__is_32bit$11$next + sync posedge \coresync_clk + update \mul_op__is_32bit$11 $0\mul_op__is_32bit$11[0:0]$6998 + end + attribute \src "issuer_ls180.v:139212.3-139213.59" + process $proc$issuer_ls180.v:139212$6999 + assign { } { } + assign $0\mul_op__is_signed$12[0:0]$7000 \mul_op__is_signed$12$next + sync posedge \coresync_clk + update \mul_op__is_signed$12 $0\mul_op__is_signed$12[0:0]$7000 + end + attribute \src "issuer_ls180.v:139214.3-139215.49" + process $proc$issuer_ls180.v:139214$7001 + assign { } { } + assign $0\mul_op__insn$13[31:0]$7002 \mul_op__insn$13$next + sync posedge \coresync_clk + update \mul_op__insn$13 $0\mul_op__insn$13[31:0]$7002 + end + attribute \src "issuer_ls180.v:139216.3-139217.33" + process $proc$issuer_ls180.v:139216$7003 + assign { } { } + assign $0\muxid$1[1:0]$7004 \muxid$1$next + sync posedge \coresync_clk + update \muxid$1 $0\muxid$1[1:0]$7004 + end + attribute \src "issuer_ls180.v:139218.3-139219.29" + process $proc$issuer_ls180.v:139218$7005 + assign { } { } + assign $0\r_busy[0:0] \r_busy$next + sync posedge \coresync_clk + update \r_busy $0\r_busy[0:0] + end + attribute \src "issuer_ls180.v:139265.3-139282.6" + process $proc$issuer_ls180.v:139265$7006 + assign { } { } + assign { } { } + assign { } { } + assign $0\r_busy$next[0:0]$7007 $2\r_busy$next[0:0]$7009 + attribute \src "issuer_ls180.v:139266.5-139266.29" + switch \initial + attribute \src "issuer_ls180.v:139266.9-139266.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\r_busy$next[0:0]$7008 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\r_busy$next[0:0]$7008 1'0 + case + assign $1\r_busy$next[0:0]$7008 \r_busy + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\r_busy$next[0:0]$7009 1'0 + case + assign $2\r_busy$next[0:0]$7009 $1\r_busy$next[0:0]$7008 + end + sync always + update \r_busy$next $0\r_busy$next[0:0]$7007 + end + attribute \src "issuer_ls180.v:139283.3-139295.6" + process $proc$issuer_ls180.v:139283$7010 + assign { } { } + assign { } { } + assign $0\muxid$1$next[1:0]$7011 $1\muxid$1$next[1:0]$7012 + attribute \src "issuer_ls180.v:139284.5-139284.29" + switch \initial + attribute \src "issuer_ls180.v:139284.9-139284.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\muxid$1$next[1:0]$7012 \muxid$36 + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\muxid$1$next[1:0]$7012 \muxid$36 + case + assign $1\muxid$1$next[1:0]$7012 \muxid$1 + end + sync always + update \muxid$1$next $0\muxid$1$next[1:0]$7011 + end + attribute \src "issuer_ls180.v:139296.3-139331.6" + process $proc$issuer_ls180.v:139296$7013 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\mul_op__fn_unit$3$next[11:0]$7014 $1\mul_op__fn_unit$3$next[11:0]$7026 + assign { } { } + assign { } { } + assign $0\mul_op__insn$13$next[31:0]$7017 $1\mul_op__insn$13$next[31:0]$7029 + assign $0\mul_op__insn_type$2$next[6:0]$7018 $1\mul_op__insn_type$2$next[6:0]$7030 + assign $0\mul_op__is_32bit$11$next[0:0]$7019 $1\mul_op__is_32bit$11$next[0:0]$7031 + assign $0\mul_op__is_signed$12$next[0:0]$7020 $1\mul_op__is_signed$12$next[0:0]$7032 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\mul_op__write_cr0$10$next[0:0]$7025 $1\mul_op__write_cr0$10$next[0:0]$7037 + assign $0\mul_op__imm_data__data$4$next[63:0]$7015 $2\mul_op__imm_data__data$4$next[63:0]$7038 + assign $0\mul_op__imm_data__ok$5$next[0:0]$7016 $2\mul_op__imm_data__ok$5$next[0:0]$7039 + assign $0\mul_op__oe__oe$8$next[0:0]$7021 $2\mul_op__oe__oe$8$next[0:0]$7040 + assign $0\mul_op__oe__ok$9$next[0:0]$7022 $2\mul_op__oe__ok$9$next[0:0]$7041 + assign $0\mul_op__rc__ok$7$next[0:0]$7023 $2\mul_op__rc__ok$7$next[0:0]$7042 + assign $0\mul_op__rc__rc$6$next[0:0]$7024 $2\mul_op__rc__rc$6$next[0:0]$7043 + attribute \src "issuer_ls180.v:139297.5-139297.29" + switch \initial + attribute \src "issuer_ls180.v:139297.9-139297.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'-1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { $1\mul_op__insn$13$next[31:0]$7029 $1\mul_op__is_signed$12$next[0:0]$7032 $1\mul_op__is_32bit$11$next[0:0]$7031 $1\mul_op__write_cr0$10$next[0:0]$7037 $1\mul_op__oe__ok$9$next[0:0]$7034 $1\mul_op__oe__oe$8$next[0:0]$7033 $1\mul_op__rc__ok$7$next[0:0]$7035 $1\mul_op__rc__rc$6$next[0:0]$7036 $1\mul_op__imm_data__ok$5$next[0:0]$7028 $1\mul_op__imm_data__data$4$next[63:0]$7027 $1\mul_op__fn_unit$3$next[11:0]$7026 $1\mul_op__insn_type$2$next[6:0]$7030 } { \mul_op__insn$48 \mul_op__is_signed$47 \mul_op__is_32bit$46 \mul_op__write_cr0$45 \mul_op__oe__ok$44 \mul_op__oe__oe$43 \mul_op__rc__ok$42 \mul_op__rc__rc$41 \mul_op__imm_data__ok$40 \mul_op__imm_data__data$39 \mul_op__fn_unit$38 \mul_op__insn_type$37 } + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'1- + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { $1\mul_op__insn$13$next[31:0]$7029 $1\mul_op__is_signed$12$next[0:0]$7032 $1\mul_op__is_32bit$11$next[0:0]$7031 $1\mul_op__write_cr0$10$next[0:0]$7037 $1\mul_op__oe__ok$9$next[0:0]$7034 $1\mul_op__oe__oe$8$next[0:0]$7033 $1\mul_op__rc__ok$7$next[0:0]$7035 $1\mul_op__rc__rc$6$next[0:0]$7036 $1\mul_op__imm_data__ok$5$next[0:0]$7028 $1\mul_op__imm_data__data$4$next[63:0]$7027 $1\mul_op__fn_unit$3$next[11:0]$7026 $1\mul_op__insn_type$2$next[6:0]$7030 } { \mul_op__insn$48 \mul_op__is_signed$47 \mul_op__is_32bit$46 \mul_op__write_cr0$45 \mul_op__oe__ok$44 \mul_op__oe__oe$43 \mul_op__rc__ok$42 \mul_op__rc__rc$41 \mul_op__imm_data__ok$40 \mul_op__imm_data__data$39 \mul_op__fn_unit$38 \mul_op__insn_type$37 } + case + assign $1\mul_op__fn_unit$3$next[11:0]$7026 \mul_op__fn_unit$3 + assign $1\mul_op__imm_data__data$4$next[63:0]$7027 \mul_op__imm_data__data$4 + assign $1\mul_op__imm_data__ok$5$next[0:0]$7028 \mul_op__imm_data__ok$5 + assign $1\mul_op__insn$13$next[31:0]$7029 \mul_op__insn$13 + assign $1\mul_op__insn_type$2$next[6:0]$7030 \mul_op__insn_type$2 + assign $1\mul_op__is_32bit$11$next[0:0]$7031 \mul_op__is_32bit$11 + assign $1\mul_op__is_signed$12$next[0:0]$7032 \mul_op__is_signed$12 + assign $1\mul_op__oe__oe$8$next[0:0]$7033 \mul_op__oe__oe$8 + assign $1\mul_op__oe__ok$9$next[0:0]$7034 \mul_op__oe__ok$9 + assign $1\mul_op__rc__ok$7$next[0:0]$7035 \mul_op__rc__ok$7 + assign $1\mul_op__rc__rc$6$next[0:0]$7036 \mul_op__rc__rc$6 + assign $1\mul_op__write_cr0$10$next[0:0]$7037 \mul_op__write_cr0$10 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $2\mul_op__imm_data__data$4$next[63:0]$7038 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\mul_op__imm_data__ok$5$next[0:0]$7039 1'0 + assign $2\mul_op__rc__rc$6$next[0:0]$7043 1'0 + assign $2\mul_op__rc__ok$7$next[0:0]$7042 1'0 + assign $2\mul_op__oe__oe$8$next[0:0]$7040 1'0 + assign $2\mul_op__oe__ok$9$next[0:0]$7041 1'0 + case + assign $2\mul_op__imm_data__data$4$next[63:0]$7038 $1\mul_op__imm_data__data$4$next[63:0]$7027 + assign $2\mul_op__imm_data__ok$5$next[0:0]$7039 $1\mul_op__imm_data__ok$5$next[0:0]$7028 + assign $2\mul_op__oe__oe$8$next[0:0]$7040 $1\mul_op__oe__oe$8$next[0:0]$7033 + assign $2\mul_op__oe__ok$9$next[0:0]$7041 $1\mul_op__oe__ok$9$next[0:0]$7034 + assign $2\mul_op__rc__ok$7$next[0:0]$7042 $1\mul_op__rc__ok$7$next[0:0]$7035 + assign $2\mul_op__rc__rc$6$next[0:0]$7043 $1\mul_op__rc__rc$6$next[0:0]$7036 + end + sync always + update \mul_op__fn_unit$3$next $0\mul_op__fn_unit$3$next[11:0]$7014 + update \mul_op__imm_data__data$4$next $0\mul_op__imm_data__data$4$next[63:0]$7015 + update \mul_op__imm_data__ok$5$next $0\mul_op__imm_data__ok$5$next[0:0]$7016 + update \mul_op__insn$13$next $0\mul_op__insn$13$next[31:0]$7017 + update \mul_op__insn_type$2$next $0\mul_op__insn_type$2$next[6:0]$7018 + update \mul_op__is_32bit$11$next $0\mul_op__is_32bit$11$next[0:0]$7019 + update \mul_op__is_signed$12$next $0\mul_op__is_signed$12$next[0:0]$7020 + update \mul_op__oe__oe$8$next $0\mul_op__oe__oe$8$next[0:0]$7021 + update \mul_op__oe__ok$9$next $0\mul_op__oe__ok$9$next[0:0]$7022 + update \mul_op__rc__ok$7$next $0\mul_op__rc__ok$7$next[0:0]$7023 + update \mul_op__rc__rc$6$next $0\mul_op__rc__rc$6$next[0:0]$7024 + update \mul_op__write_cr0$10$next $0\mul_op__write_cr0$10$next[0:0]$7025 + end + attribute \src "issuer_ls180.v:139332.3-139344.6" + process $proc$issuer_ls180.v:139332$7044 + assign { } { } + assign { } { } + assign $0\o$next[128:0]$7045 $1\o$next[128:0]$7046 + attribute \src "issuer_ls180.v:139333.5-139333.29" + switch \initial + attribute \src "issuer_ls180.v:139333.9-139333.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\o$next[128:0]$7046 \o$49 + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\o$next[128:0]$7046 \o$49 + case + assign $1\o$next[128:0]$7046 \o + end + sync always + update \o$next $0\o$next[128:0]$7045 + end + attribute \src "issuer_ls180.v:139345.3-139357.6" + process $proc$issuer_ls180.v:139345$7047 + assign { } { } + assign { } { } + assign $0\xer_so$14$next[0:0]$7048 $1\xer_so$14$next[0:0]$7049 + attribute \src "issuer_ls180.v:139346.5-139346.29" + switch \initial + attribute \src "issuer_ls180.v:139346.9-139346.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\xer_so$14$next[0:0]$7049 \xer_so$50 + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\xer_so$14$next[0:0]$7049 \xer_so$50 + case + assign $1\xer_so$14$next[0:0]$7049 \xer_so$14 + end + sync always + update \xer_so$14$next $0\xer_so$14$next[0:0]$7048 + end + attribute \src "issuer_ls180.v:139358.3-139370.6" + process $proc$issuer_ls180.v:139358$7050 + assign { } { } + assign { } { } + assign $0\neg_res$15$next[0:0]$7051 $1\neg_res$15$next[0:0]$7052 + attribute \src "issuer_ls180.v:139359.5-139359.29" + switch \initial + attribute \src "issuer_ls180.v:139359.9-139359.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\neg_res$15$next[0:0]$7052 \neg_res$51 + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\neg_res$15$next[0:0]$7052 \neg_res$51 + case + assign $1\neg_res$15$next[0:0]$7052 \neg_res$15 + end + sync always + update \neg_res$15$next $0\neg_res$15$next[0:0]$7051 + end + attribute \src "issuer_ls180.v:139371.3-139383.6" + process $proc$issuer_ls180.v:139371$7053 + assign { } { } + assign { } { } + assign $0\neg_res32$16$next[0:0]$7054 $1\neg_res32$16$next[0:0]$7055 + attribute \src "issuer_ls180.v:139372.5-139372.29" + switch \initial + attribute \src "issuer_ls180.v:139372.9-139372.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\neg_res32$16$next[0:0]$7055 \neg_res32$52 + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\neg_res32$16$next[0:0]$7055 \neg_res32$52 + case + assign $1\neg_res32$16$next[0:0]$7055 \neg_res32$16 + end + sync always + update \neg_res32$16$next $0\neg_res32$16$next[0:0]$7054 + end + connect \$34 $and$issuer_ls180.v:139183$6971_Y + connect \p_ready_o \n_i_rdy_data + connect \n_valid_o \r_busy + connect \neg_res32$52 \mul2_neg_res32$32 + connect \neg_res$51 \mul2_neg_res$31 + connect \xer_so$50 \mul2_xer_so$30 + connect \o$49 \mul2_o + connect { \mul_op__insn$48 \mul_op__is_signed$47 \mul_op__is_32bit$46 \mul_op__write_cr0$45 \mul_op__oe__ok$44 \mul_op__oe__oe$43 \mul_op__rc__ok$42 \mul_op__rc__rc$41 \mul_op__imm_data__ok$40 \mul_op__imm_data__data$39 \mul_op__fn_unit$38 \mul_op__insn_type$37 } { \mul2_mul_op__insn$29 \mul2_mul_op__is_signed$28 \mul2_mul_op__is_32bit$27 \mul2_mul_op__write_cr0$26 \mul2_mul_op__oe__ok$25 \mul2_mul_op__oe__oe$24 \mul2_mul_op__rc__ok$23 \mul2_mul_op__rc__rc$22 \mul2_mul_op__imm_data__ok$21 \mul2_mul_op__imm_data__data$20 \mul2_mul_op__fn_unit$19 \mul2_mul_op__insn_type$18 } + connect \muxid$36 \mul2_muxid$17 + connect \p_valid_i_p_ready_o \$34 + connect \n_i_rdy_data \n_ready_i + connect \p_valid_i$33 \p_valid_i + connect \mul2_neg_res32 \neg_res32 + connect \mul2_neg_res \neg_res + connect \mul2_xer_so \xer_so + connect \mul2_rb \rb + connect \mul2_ra \ra + connect { \mul2_mul_op__insn \mul2_mul_op__is_signed \mul2_mul_op__is_32bit \mul2_mul_op__write_cr0 \mul2_mul_op__oe__ok \mul2_mul_op__oe__oe \mul2_mul_op__rc__ok \mul2_mul_op__rc__rc \mul2_mul_op__imm_data__ok \mul2_mul_op__imm_data__data \mul2_mul_op__fn_unit \mul2_mul_op__insn_type } { \mul_op__insn \mul_op__is_signed \mul_op__is_32bit \mul_op__write_cr0 \mul_op__oe__ok \mul_op__oe__oe \mul_op__rc__ok \mul_op__rc__rc \mul_op__imm_data__ok \mul_op__imm_data__data \mul_op__fn_unit \mul_op__insn_type } + connect \mul2_muxid \muxid +end +attribute \src "issuer_ls180.v:139406.1-140681.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.fus.mul0.alu_mul0.mul_pipe3" +attribute \generator "nMigen" +module \mul_pipe3 + attribute \src "issuer_ls180.v:140599.3-140617.6" + wire width 4 $0\cr_a$next[3:0]$7174 + attribute \src "issuer_ls180.v:140391.3-140392.25" + wire width 4 $0\cr_a[3:0] + attribute \src "issuer_ls180.v:140599.3-140617.6" + wire $0\cr_a_ok$next[0:0]$7175 + attribute \src "issuer_ls180.v:140393.3-140394.31" + wire $0\cr_a_ok[0:0] + attribute \src "issuer_ls180.v:139407.7-139407.20" + wire $0\initial[0:0] + attribute \src "issuer_ls180.v:140544.3-140579.6" + wire width 12 $0\mul_op__fn_unit$3$next[11:0]$7137 + attribute \src "issuer_ls180.v:140401.3-140402.53" + wire width 12 $0\mul_op__fn_unit$3[11:0]$7105 + attribute \src "issuer_ls180.v:139708.14-139708.43" + wire width 12 $0\mul_op__fn_unit$3[11:0]$7195 + attribute \src "issuer_ls180.v:140544.3-140579.6" + wire width 64 $0\mul_op__imm_data__data$4$next[63:0]$7138 + attribute \src "issuer_ls180.v:140403.3-140404.67" + wire width 64 $0\mul_op__imm_data__data$4[63:0]$7107 + attribute \src "issuer_ls180.v:139730.14-139730.63" + wire width 64 $0\mul_op__imm_data__data$4[63:0]$7197 + attribute \src "issuer_ls180.v:140544.3-140579.6" + wire $0\mul_op__imm_data__ok$5$next[0:0]$7139 + attribute \src "issuer_ls180.v:140405.3-140406.63" + wire $0\mul_op__imm_data__ok$5[0:0]$7109 + attribute \src "issuer_ls180.v:139739.7-139739.38" + wire $0\mul_op__imm_data__ok$5[0:0]$7199 + attribute \src "issuer_ls180.v:140544.3-140579.6" + wire width 32 $0\mul_op__insn$13$next[31:0]$7140 + attribute \src "issuer_ls180.v:140421.3-140422.49" + wire width 32 $0\mul_op__insn$13[31:0]$7125 + attribute \src "issuer_ls180.v:139748.14-139748.39" + wire width 32 $0\mul_op__insn$13[31:0]$7201 + attribute \src "issuer_ls180.v:140544.3-140579.6" + wire width 7 $0\mul_op__insn_type$2$next[6:0]$7141 + attribute \src "issuer_ls180.v:140399.3-140400.57" + wire width 7 $0\mul_op__insn_type$2[6:0]$7103 + attribute \src "issuer_ls180.v:139905.13-139905.42" + wire width 7 $0\mul_op__insn_type$2[6:0]$7203 + attribute \src "issuer_ls180.v:140544.3-140579.6" + wire $0\mul_op__is_32bit$11$next[0:0]$7142 + attribute \src "issuer_ls180.v:140417.3-140418.57" + wire $0\mul_op__is_32bit$11[0:0]$7121 + attribute \src "issuer_ls180.v:139988.7-139988.35" + wire $0\mul_op__is_32bit$11[0:0]$7205 + attribute \src "issuer_ls180.v:140544.3-140579.6" + wire $0\mul_op__is_signed$12$next[0:0]$7143 + attribute \src "issuer_ls180.v:140419.3-140420.59" + wire $0\mul_op__is_signed$12[0:0]$7123 + attribute \src "issuer_ls180.v:139997.7-139997.36" + wire $0\mul_op__is_signed$12[0:0]$7207 + attribute \src "issuer_ls180.v:140544.3-140579.6" + wire $0\mul_op__oe__oe$8$next[0:0]$7144 + attribute \src "issuer_ls180.v:140411.3-140412.51" + wire $0\mul_op__oe__oe$8[0:0]$7115 + attribute \src "issuer_ls180.v:140008.7-140008.32" + wire $0\mul_op__oe__oe$8[0:0]$7209 + attribute \src "issuer_ls180.v:140544.3-140579.6" + wire $0\mul_op__oe__ok$9$next[0:0]$7145 + attribute \src "issuer_ls180.v:140413.3-140414.51" + wire $0\mul_op__oe__ok$9[0:0]$7117 + attribute \src "issuer_ls180.v:140017.7-140017.32" + wire $0\mul_op__oe__ok$9[0:0]$7211 + attribute \src "issuer_ls180.v:140544.3-140579.6" + wire $0\mul_op__rc__ok$7$next[0:0]$7146 + attribute \src "issuer_ls180.v:140409.3-140410.51" + wire $0\mul_op__rc__ok$7[0:0]$7113 + attribute \src "issuer_ls180.v:140026.7-140026.32" + wire $0\mul_op__rc__ok$7[0:0]$7213 + attribute \src "issuer_ls180.v:140544.3-140579.6" + wire $0\mul_op__rc__rc$6$next[0:0]$7147 + attribute \src "issuer_ls180.v:140407.3-140408.51" + wire $0\mul_op__rc__rc$6[0:0]$7111 + attribute \src "issuer_ls180.v:140033.7-140033.32" + wire $0\mul_op__rc__rc$6[0:0]$7215 + attribute \src "issuer_ls180.v:140544.3-140579.6" + wire $0\mul_op__write_cr0$10$next[0:0]$7148 + attribute \src "issuer_ls180.v:140415.3-140416.59" + wire $0\mul_op__write_cr0$10[0:0]$7119 + attribute \src "issuer_ls180.v:140042.7-140042.36" + wire $0\mul_op__write_cr0$10[0:0]$7217 + attribute \src "issuer_ls180.v:140531.3-140543.6" + wire width 2 $0\muxid$1$next[1:0]$7134 + attribute \src "issuer_ls180.v:140423.3-140424.33" + wire width 2 $0\muxid$1[1:0]$7127 + attribute \src "issuer_ls180.v:140051.13-140051.29" + wire width 2 $0\muxid$1[1:0]$7219 + attribute \src "issuer_ls180.v:140580.3-140598.6" + wire width 64 $0\o$14$next[63:0]$7169 + attribute \src "issuer_ls180.v:140395.3-140396.27" + wire width 64 $0\o$14[63:0]$7100 + attribute \src "issuer_ls180.v:140072.14-140072.43" + wire width 64 $0\o$14[63:0]$7221 + attribute \src "issuer_ls180.v:140580.3-140598.6" + wire $0\o_ok$next[0:0]$7168 + attribute \src "issuer_ls180.v:140397.3-140398.25" + wire $0\o_ok[0:0] + attribute \src "issuer_ls180.v:140513.3-140530.6" + wire $0\r_busy$next[0:0]$7130 + attribute \src "issuer_ls180.v:140425.3-140426.29" + wire $0\r_busy[0:0] + attribute \src "issuer_ls180.v:140618.3-140636.6" + wire width 2 $0\xer_ov$next[1:0]$7180 + attribute \src "issuer_ls180.v:140387.3-140388.29" + wire width 2 $0\xer_ov[1:0] + attribute \src "issuer_ls180.v:140618.3-140636.6" + wire $0\xer_ov_ok$next[0:0]$7181 + attribute \src "issuer_ls180.v:140389.3-140390.35" + wire $0\xer_ov_ok[0:0] + attribute \src "issuer_ls180.v:140637.3-140655.6" + wire $0\xer_so$15$next[0:0]$7187 + attribute \src "issuer_ls180.v:140383.3-140384.37" + wire $0\xer_so$15[0:0]$7093 + attribute \src "issuer_ls180.v:140368.7-140368.25" + wire $0\xer_so$15[0:0]$7227 + attribute \src "issuer_ls180.v:140637.3-140655.6" + wire $0\xer_so_ok$next[0:0]$7186 + attribute \src "issuer_ls180.v:140385.3-140386.35" + wire $0\xer_so_ok[0:0] + attribute \src "issuer_ls180.v:140599.3-140617.6" + wire width 4 $1\cr_a$next[3:0]$7176 + attribute \src "issuer_ls180.v:139416.13-139416.24" + wire width 4 $1\cr_a[3:0] + attribute \src "issuer_ls180.v:140599.3-140617.6" + wire $1\cr_a_ok$next[0:0]$7177 + attribute \src "issuer_ls180.v:139425.7-139425.21" + wire $1\cr_a_ok[0:0] + attribute \src "issuer_ls180.v:140544.3-140579.6" + wire width 12 $1\mul_op__fn_unit$3$next[11:0]$7149 + attribute \src "issuer_ls180.v:140544.3-140579.6" + wire width 64 $1\mul_op__imm_data__data$4$next[63:0]$7150 + attribute \src "issuer_ls180.v:140544.3-140579.6" + wire $1\mul_op__imm_data__ok$5$next[0:0]$7151 + attribute \src "issuer_ls180.v:140544.3-140579.6" + wire width 32 $1\mul_op__insn$13$next[31:0]$7152 + attribute \src "issuer_ls180.v:140544.3-140579.6" + wire width 7 $1\mul_op__insn_type$2$next[6:0]$7153 + attribute \src "issuer_ls180.v:140544.3-140579.6" + wire $1\mul_op__is_32bit$11$next[0:0]$7154 + attribute \src "issuer_ls180.v:140544.3-140579.6" + wire $1\mul_op__is_signed$12$next[0:0]$7155 + attribute \src "issuer_ls180.v:140544.3-140579.6" + wire $1\mul_op__oe__oe$8$next[0:0]$7156 + attribute \src "issuer_ls180.v:140544.3-140579.6" + wire $1\mul_op__oe__ok$9$next[0:0]$7157 + attribute \src "issuer_ls180.v:140544.3-140579.6" + wire $1\mul_op__rc__ok$7$next[0:0]$7158 + attribute \src "issuer_ls180.v:140544.3-140579.6" + wire $1\mul_op__rc__rc$6$next[0:0]$7159 + attribute \src "issuer_ls180.v:140544.3-140579.6" + wire $1\mul_op__write_cr0$10$next[0:0]$7160 + attribute \src "issuer_ls180.v:140531.3-140543.6" + wire width 2 $1\muxid$1$next[1:0]$7135 + attribute \src "issuer_ls180.v:140580.3-140598.6" + wire width 64 $1\o$14$next[63:0]$7171 + attribute \src "issuer_ls180.v:140580.3-140598.6" + wire $1\o_ok$next[0:0]$7170 + attribute \src "issuer_ls180.v:140079.7-140079.18" + wire $1\o_ok[0:0] + attribute \src "issuer_ls180.v:140513.3-140530.6" + wire $1\r_busy$next[0:0]$7131 + attribute \src "issuer_ls180.v:140345.7-140345.20" + wire $1\r_busy[0:0] + attribute \src "issuer_ls180.v:140618.3-140636.6" + wire width 2 $1\xer_ov$next[1:0]$7182 + attribute \src "issuer_ls180.v:140350.13-140350.26" + wire width 2 $1\xer_ov[1:0] + attribute \src "issuer_ls180.v:140618.3-140636.6" + wire $1\xer_ov_ok$next[0:0]$7183 + attribute \src "issuer_ls180.v:140357.7-140357.23" + wire $1\xer_ov_ok[0:0] + attribute \src "issuer_ls180.v:140637.3-140655.6" + wire $1\xer_so$15$next[0:0]$7189 + attribute \src "issuer_ls180.v:140637.3-140655.6" + wire $1\xer_so_ok$next[0:0]$7188 + attribute \src "issuer_ls180.v:140375.7-140375.23" + wire $1\xer_so_ok[0:0] + attribute \src "issuer_ls180.v:140599.3-140617.6" + wire $2\cr_a_ok$next[0:0]$7178 + attribute \src "issuer_ls180.v:140544.3-140579.6" + wire width 64 $2\mul_op__imm_data__data$4$next[63:0]$7161 + attribute \src "issuer_ls180.v:140544.3-140579.6" + wire $2\mul_op__imm_data__ok$5$next[0:0]$7162 + attribute \src "issuer_ls180.v:140544.3-140579.6" + wire $2\mul_op__oe__oe$8$next[0:0]$7163 + attribute \src "issuer_ls180.v:140544.3-140579.6" + wire $2\mul_op__oe__ok$9$next[0:0]$7164 + attribute \src "issuer_ls180.v:140544.3-140579.6" + wire $2\mul_op__rc__ok$7$next[0:0]$7165 + attribute \src "issuer_ls180.v:140544.3-140579.6" + wire $2\mul_op__rc__rc$6$next[0:0]$7166 + attribute \src "issuer_ls180.v:140580.3-140598.6" + wire $2\o_ok$next[0:0]$7172 + attribute \src "issuer_ls180.v:140513.3-140530.6" + wire $2\r_busy$next[0:0]$7132 + attribute \src "issuer_ls180.v:140618.3-140636.6" + wire $2\xer_ov_ok$next[0:0]$7184 + attribute \src "issuer_ls180.v:140637.3-140655.6" + wire $2\xer_so_ok$next[0:0]$7190 + attribute \src "issuer_ls180.v:140382.18-140382.118" + wire $and$issuer_ls180.v:140382$7091_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" + wire \$56 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" + wire input 44 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" + wire input 1 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 4 output 38 \cr_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 4 \cr_a$51 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 4 \cr_a$73 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 4 \cr_a$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 39 \cr_a_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \cr_a_ok$50 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \cr_a_ok$52 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \cr_a_ok$74 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \cr_a_ok$next + attribute \src "issuer_ls180.v:139407.7-139407.15" + wire \initial + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 \mul3_mul_op__fn_unit + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 \mul3_mul_op__fn_unit$18 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \mul3_mul_op__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \mul3_mul_op__imm_data__data$19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul3_mul_op__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul3_mul_op__imm_data__ok$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \mul3_mul_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \mul3_mul_op__insn$28 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \mul3_mul_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \mul3_mul_op__insn_type$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul3_mul_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul3_mul_op__is_32bit$26 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul3_mul_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul3_mul_op__is_signed$27 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul3_mul_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul3_mul_op__oe__oe$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul3_mul_op__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul3_mul_op__oe__ok$24 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul3_mul_op__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul3_mul_op__rc__ok$22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul3_mul_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul3_mul_op__rc__rc$21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul3_mul_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul3_mul_op__write_cr0$25 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \mul3_muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \mul3_muxid$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:23" + wire \mul3_neg_res + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 129 \mul3_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 \mul3_o$29 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \mul3_o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 2 \mul3_xer_ov + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \mul3_xer_ov_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire \mul3_xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \mul3_xer_so$30 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \mul3_xer_so_ok + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 input 6 \mul_op__fn_unit + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 output 25 \mul_op__fn_unit$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 \mul_op__fn_unit$3$next + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 \mul_op__fn_unit$60 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 input 7 \mul_op__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 output 26 \mul_op__imm_data__data$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \mul_op__imm_data__data$4$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \mul_op__imm_data__data$61 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 8 \mul_op__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 27 \mul_op__imm_data__ok$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_op__imm_data__ok$5$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_op__imm_data__ok$62 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 16 \mul_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 output 35 \mul_op__insn$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \mul_op__insn$13$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \mul_op__insn$70 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 input 5 \mul_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 output 24 \mul_op__insn_type$2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \mul_op__insn_type$2$next + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \mul_op__insn_type$59 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 14 \mul_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 33 \mul_op__is_32bit$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_op__is_32bit$11$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_op__is_32bit$68 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 15 \mul_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 34 \mul_op__is_signed$12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_op__is_signed$12$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_op__is_signed$69 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 11 \mul_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_op__oe__oe$65 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 30 \mul_op__oe__oe$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_op__oe__oe$8$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 12 \mul_op__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_op__oe__ok$66 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 31 \mul_op__oe__ok$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_op__oe__ok$9$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 10 \mul_op__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_op__rc__ok$64 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 29 \mul_op__rc__ok$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_op__rc__ok$7$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 9 \mul_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 28 \mul_op__rc__rc$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_op__rc__rc$6$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_op__rc__rc$63 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 13 \mul_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 32 \mul_op__write_cr0$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_op__write_cr0$10$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \mul_op__write_cr0$67 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 input 4 \muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 output 23 \muxid$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \muxid$1$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \muxid$58 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:619" + wire \n_i_rdy_data + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" + wire input 22 \n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" + wire output 21 \n_valid_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:23" + wire input 19 \neg_res + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:24" + wire input 20 \neg_res32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:24" + wire \neg_res32$49 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 129 input 17 \o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 output 36 \o$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 \o$14$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 \o$71 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 37 \o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \o_ok$72 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \o_ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 4 \output_cr_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 4 \output_cr_a$46 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \output_cr_a_ok + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 \output_mul_op__fn_unit + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 \output_mul_op__fn_unit$33 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \output_mul_op__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \output_mul_op__imm_data__data$34 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_mul_op__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_mul_op__imm_data__ok$35 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \output_mul_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \output_mul_op__insn$43 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \output_mul_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \output_mul_op__insn_type$32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_mul_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_mul_op__is_32bit$41 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_mul_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_mul_op__is_signed$42 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_mul_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_mul_op__oe__oe$38 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_mul_op__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_mul_op__oe__ok$39 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_mul_op__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_mul_op__rc__ok$37 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_mul_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_mul_op__rc__rc$36 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_mul_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_mul_op__write_cr0$40 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \output_muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \output_muxid$31 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 \output_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 \output_o$44 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \output_o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \output_o_ok$45 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 2 \output_xer_ov + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 2 \output_xer_ov$47 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \output_xer_ov_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \output_xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \output_xer_so$48 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \output_xer_so_ok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" + wire output 3 \p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" + wire input 2 \p_valid_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:621" + wire \p_valid_i$55 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" + wire \p_valid_i_p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615" + wire \r_busy + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615" + wire \r_busy$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 2 output 40 \xer_ov + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 2 \xer_ov$75 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 2 \xer_ov$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 41 \xer_ov_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \xer_ov_ok$53 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \xer_ov_ok$76 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \xer_ov_ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire input 18 \xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 42 \xer_so$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \xer_so$15$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \xer_so$77 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 43 \xer_so_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \xer_so_ok$54 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \xer_so_ok$78 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \xer_so_ok$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" + cell $and $and$issuer_ls180.v:140382$7091 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \p_valid_i$55 + connect \B \p_ready_o + connect \Y $and$issuer_ls180.v:140382$7091_Y + end + attribute \module_not_derived 1 + attribute \src "issuer_ls180.v:140427.8-140463.4" + cell \mul3 \mul3 + connect \mul_op__fn_unit \mul3_mul_op__fn_unit + connect \mul_op__fn_unit$3 \mul3_mul_op__fn_unit$18 + connect \mul_op__imm_data__data \mul3_mul_op__imm_data__data + connect \mul_op__imm_data__data$4 \mul3_mul_op__imm_data__data$19 + connect \mul_op__imm_data__ok \mul3_mul_op__imm_data__ok + connect \mul_op__imm_data__ok$5 \mul3_mul_op__imm_data__ok$20 + connect \mul_op__insn \mul3_mul_op__insn + connect \mul_op__insn$13 \mul3_mul_op__insn$28 + connect \mul_op__insn_type \mul3_mul_op__insn_type + connect \mul_op__insn_type$2 \mul3_mul_op__insn_type$17 + connect \mul_op__is_32bit \mul3_mul_op__is_32bit + connect \mul_op__is_32bit$11 \mul3_mul_op__is_32bit$26 + connect \mul_op__is_signed \mul3_mul_op__is_signed + connect \mul_op__is_signed$12 \mul3_mul_op__is_signed$27 + connect \mul_op__oe__oe \mul3_mul_op__oe__oe + connect \mul_op__oe__oe$8 \mul3_mul_op__oe__oe$23 + connect \mul_op__oe__ok \mul3_mul_op__oe__ok + connect \mul_op__oe__ok$9 \mul3_mul_op__oe__ok$24 + connect \mul_op__rc__ok \mul3_mul_op__rc__ok + connect \mul_op__rc__ok$7 \mul3_mul_op__rc__ok$22 + connect \mul_op__rc__rc \mul3_mul_op__rc__rc + connect \mul_op__rc__rc$6 \mul3_mul_op__rc__rc$21 + connect \mul_op__write_cr0 \mul3_mul_op__write_cr0 + connect \mul_op__write_cr0$10 \mul3_mul_op__write_cr0$25 + connect \muxid \mul3_muxid + connect \muxid$1 \mul3_muxid$16 + connect \neg_res \mul3_neg_res + connect \o \mul3_o + connect \o$14 \mul3_o$29 + connect \o_ok \mul3_o_ok + connect \xer_ov \mul3_xer_ov + connect \xer_ov_ok \mul3_xer_ov_ok + connect \xer_so \mul3_xer_so + connect \xer_so$15 \mul3_xer_so$30 + connect \xer_so_ok \mul3_xer_so_ok + end + attribute \module_not_derived 1 + attribute \src "issuer_ls180.v:140464.10-140467.4" + cell \n$96 \n + connect \n_ready_i \n_ready_i + connect \n_valid_o \n_valid_o + end + attribute \module_not_derived 1 + attribute \src "issuer_ls180.v:140468.15-140508.4" + cell \output$97 \output + connect \cr_a \output_cr_a + connect \cr_a$16 \output_cr_a$46 + connect \cr_a_ok \output_cr_a_ok + connect \mul_op__fn_unit \output_mul_op__fn_unit + connect \mul_op__fn_unit$3 \output_mul_op__fn_unit$33 + connect \mul_op__imm_data__data \output_mul_op__imm_data__data + connect \mul_op__imm_data__data$4 \output_mul_op__imm_data__data$34 + connect \mul_op__imm_data__ok \output_mul_op__imm_data__ok + connect \mul_op__imm_data__ok$5 \output_mul_op__imm_data__ok$35 + connect \mul_op__insn \output_mul_op__insn + connect \mul_op__insn$13 \output_mul_op__insn$43 + connect \mul_op__insn_type \output_mul_op__insn_type + connect \mul_op__insn_type$2 \output_mul_op__insn_type$32 + connect \mul_op__is_32bit \output_mul_op__is_32bit + connect \mul_op__is_32bit$11 \output_mul_op__is_32bit$41 + connect \mul_op__is_signed \output_mul_op__is_signed + connect \mul_op__is_signed$12 \output_mul_op__is_signed$42 + connect \mul_op__oe__oe \output_mul_op__oe__oe + connect \mul_op__oe__oe$8 \output_mul_op__oe__oe$38 + connect \mul_op__oe__ok \output_mul_op__oe__ok + connect \mul_op__oe__ok$9 \output_mul_op__oe__ok$39 + connect \mul_op__rc__ok \output_mul_op__rc__ok + connect \mul_op__rc__ok$7 \output_mul_op__rc__ok$37 + connect \mul_op__rc__rc \output_mul_op__rc__rc + connect \mul_op__rc__rc$6 \output_mul_op__rc__rc$36 + connect \mul_op__write_cr0 \output_mul_op__write_cr0 + connect \mul_op__write_cr0$10 \output_mul_op__write_cr0$40 + connect \muxid \output_muxid + connect \muxid$1 \output_muxid$31 + connect \o \output_o + connect \o$14 \output_o$44 + connect \o_ok \output_o_ok + connect \o_ok$15 \output_o_ok$45 + connect \xer_ov \output_xer_ov + connect \xer_ov$17 \output_xer_ov$47 + connect \xer_ov_ok \output_xer_ov_ok + connect \xer_so \output_xer_so + connect \xer_so$18 \output_xer_so$48 + connect \xer_so_ok \output_xer_so_ok + end + attribute \module_not_derived 1 + attribute \src "issuer_ls180.v:140509.10-140512.4" + cell \p$95 \p + connect \p_ready_o \p_ready_o + connect \p_valid_i \p_valid_i + end + attribute \src "issuer_ls180.v:139407.7-139407.20" + process $proc$issuer_ls180.v:139407$7191 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "issuer_ls180.v:139416.13-139416.24" + process $proc$issuer_ls180.v:139416$7192 + assign { } { } + assign $1\cr_a[3:0] 4'0000 + sync always + sync init + update \cr_a $1\cr_a[3:0] + end + attribute \src "issuer_ls180.v:139425.7-139425.21" + process $proc$issuer_ls180.v:139425$7193 + assign { } { } + assign $1\cr_a_ok[0:0] 1'0 + sync always + sync init + update \cr_a_ok $1\cr_a_ok[0:0] + end + attribute \src "issuer_ls180.v:139708.14-139708.43" + process $proc$issuer_ls180.v:139708$7194 + assign { } { } + assign $0\mul_op__fn_unit$3[11:0]$7195 12'000000000000 + sync always + sync init + update \mul_op__fn_unit$3 $0\mul_op__fn_unit$3[11:0]$7195 + end + attribute \src "issuer_ls180.v:139730.14-139730.63" + process $proc$issuer_ls180.v:139730$7196 + assign { } { } + assign $0\mul_op__imm_data__data$4[63:0]$7197 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \mul_op__imm_data__data$4 $0\mul_op__imm_data__data$4[63:0]$7197 + end + attribute \src "issuer_ls180.v:139739.7-139739.38" + process $proc$issuer_ls180.v:139739$7198 + assign { } { } + assign $0\mul_op__imm_data__ok$5[0:0]$7199 1'0 + sync always + sync init + update \mul_op__imm_data__ok$5 $0\mul_op__imm_data__ok$5[0:0]$7199 + end + attribute \src "issuer_ls180.v:139748.14-139748.39" + process $proc$issuer_ls180.v:139748$7200 + assign { } { } + assign $0\mul_op__insn$13[31:0]$7201 0 + sync always + sync init + update \mul_op__insn$13 $0\mul_op__insn$13[31:0]$7201 + end + attribute \src "issuer_ls180.v:139905.13-139905.42" + process $proc$issuer_ls180.v:139905$7202 + assign { } { } + assign $0\mul_op__insn_type$2[6:0]$7203 7'0000000 + sync always + sync init + update \mul_op__insn_type$2 $0\mul_op__insn_type$2[6:0]$7203 + end + attribute \src "issuer_ls180.v:139988.7-139988.35" + process $proc$issuer_ls180.v:139988$7204 + assign { } { } + assign $0\mul_op__is_32bit$11[0:0]$7205 1'0 + sync always + sync init + update \mul_op__is_32bit$11 $0\mul_op__is_32bit$11[0:0]$7205 + end + attribute \src "issuer_ls180.v:139997.7-139997.36" + process $proc$issuer_ls180.v:139997$7206 + assign { } { } + assign $0\mul_op__is_signed$12[0:0]$7207 1'0 + sync always + sync init + update \mul_op__is_signed$12 $0\mul_op__is_signed$12[0:0]$7207 + end + attribute \src "issuer_ls180.v:140008.7-140008.32" + process $proc$issuer_ls180.v:140008$7208 + assign { } { } + assign $0\mul_op__oe__oe$8[0:0]$7209 1'0 + sync always + sync init + update \mul_op__oe__oe$8 $0\mul_op__oe__oe$8[0:0]$7209 + end + attribute \src "issuer_ls180.v:140017.7-140017.32" + process $proc$issuer_ls180.v:140017$7210 + assign { } { } + assign $0\mul_op__oe__ok$9[0:0]$7211 1'0 + sync always + sync init + update \mul_op__oe__ok$9 $0\mul_op__oe__ok$9[0:0]$7211 + end + attribute \src "issuer_ls180.v:140026.7-140026.32" + process $proc$issuer_ls180.v:140026$7212 + assign { } { } + assign $0\mul_op__rc__ok$7[0:0]$7213 1'0 + sync always + sync init + update \mul_op__rc__ok$7 $0\mul_op__rc__ok$7[0:0]$7213 + end + attribute \src "issuer_ls180.v:140033.7-140033.32" + process $proc$issuer_ls180.v:140033$7214 + assign { } { } + assign $0\mul_op__rc__rc$6[0:0]$7215 1'0 + sync always + sync init + update \mul_op__rc__rc$6 $0\mul_op__rc__rc$6[0:0]$7215 + end + attribute \src "issuer_ls180.v:140042.7-140042.36" + process $proc$issuer_ls180.v:140042$7216 + assign { } { } + assign $0\mul_op__write_cr0$10[0:0]$7217 1'0 + sync always + sync init + update \mul_op__write_cr0$10 $0\mul_op__write_cr0$10[0:0]$7217 + end + attribute \src "issuer_ls180.v:140051.13-140051.29" + process $proc$issuer_ls180.v:140051$7218 + assign { } { } + assign $0\muxid$1[1:0]$7219 2'00 + sync always + sync init + update \muxid$1 $0\muxid$1[1:0]$7219 + end + attribute \src "issuer_ls180.v:140072.14-140072.43" + process $proc$issuer_ls180.v:140072$7220 + assign { } { } + assign $0\o$14[63:0]$7221 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \o$14 $0\o$14[63:0]$7221 + end + attribute \src "issuer_ls180.v:140079.7-140079.18" + process $proc$issuer_ls180.v:140079$7222 + assign { } { } + assign $1\o_ok[0:0] 1'0 + sync always + sync init + update \o_ok $1\o_ok[0:0] + end + attribute \src "issuer_ls180.v:140345.7-140345.20" + process $proc$issuer_ls180.v:140345$7223 + assign { } { } + assign $1\r_busy[0:0] 1'0 + sync always + sync init + update \r_busy $1\r_busy[0:0] + end + attribute \src "issuer_ls180.v:140350.13-140350.26" + process $proc$issuer_ls180.v:140350$7224 + assign { } { } + assign $1\xer_ov[1:0] 2'00 + sync always + sync init + update \xer_ov $1\xer_ov[1:0] + end + attribute \src "issuer_ls180.v:140357.7-140357.23" + process $proc$issuer_ls180.v:140357$7225 + assign { } { } + assign $1\xer_ov_ok[0:0] 1'0 + sync always + sync init + update \xer_ov_ok $1\xer_ov_ok[0:0] + end + attribute \src "issuer_ls180.v:140368.7-140368.25" + process $proc$issuer_ls180.v:140368$7226 + assign { } { } + assign $0\xer_so$15[0:0]$7227 1'0 + sync always + sync init + update \xer_so$15 $0\xer_so$15[0:0]$7227 + end + attribute \src "issuer_ls180.v:140375.7-140375.23" + process $proc$issuer_ls180.v:140375$7228 + assign { } { } + assign $1\xer_so_ok[0:0] 1'0 + sync always + sync init + update \xer_so_ok $1\xer_so_ok[0:0] + end + attribute \src "issuer_ls180.v:140383.3-140384.37" + process $proc$issuer_ls180.v:140383$7092 + assign { } { } + assign $0\xer_so$15[0:0]$7093 \xer_so$15$next + sync posedge \coresync_clk + update \xer_so$15 $0\xer_so$15[0:0]$7093 + end + attribute \src "issuer_ls180.v:140385.3-140386.35" + process $proc$issuer_ls180.v:140385$7094 + assign { } { } + assign $0\xer_so_ok[0:0] \xer_so_ok$next + sync posedge \coresync_clk + update \xer_so_ok $0\xer_so_ok[0:0] + end + attribute \src "issuer_ls180.v:140387.3-140388.29" + process $proc$issuer_ls180.v:140387$7095 + assign { } { } + assign $0\xer_ov[1:0] \xer_ov$next + sync posedge \coresync_clk + update \xer_ov $0\xer_ov[1:0] + end + attribute \src "issuer_ls180.v:140389.3-140390.35" + process $proc$issuer_ls180.v:140389$7096 + assign { } { } + assign $0\xer_ov_ok[0:0] \xer_ov_ok$next + sync posedge \coresync_clk + update \xer_ov_ok $0\xer_ov_ok[0:0] + end + attribute \src "issuer_ls180.v:140391.3-140392.25" + process $proc$issuer_ls180.v:140391$7097 + assign { } { } + assign $0\cr_a[3:0] \cr_a$next + sync posedge \coresync_clk + update \cr_a $0\cr_a[3:0] + end + attribute \src "issuer_ls180.v:140393.3-140394.31" + process $proc$issuer_ls180.v:140393$7098 + assign { } { } + assign $0\cr_a_ok[0:0] \cr_a_ok$next + sync posedge \coresync_clk + update \cr_a_ok $0\cr_a_ok[0:0] + end + attribute \src "issuer_ls180.v:140395.3-140396.27" + process $proc$issuer_ls180.v:140395$7099 + assign { } { } + assign $0\o$14[63:0]$7100 \o$14$next + sync posedge \coresync_clk + update \o$14 $0\o$14[63:0]$7100 + end + attribute \src "issuer_ls180.v:140397.3-140398.25" + process $proc$issuer_ls180.v:140397$7101 + assign { } { } + assign $0\o_ok[0:0] \o_ok$next + sync posedge \coresync_clk + update \o_ok $0\o_ok[0:0] + end + attribute \src "issuer_ls180.v:140399.3-140400.57" + process $proc$issuer_ls180.v:140399$7102 + assign { } { } + assign $0\mul_op__insn_type$2[6:0]$7103 \mul_op__insn_type$2$next + sync posedge \coresync_clk + update \mul_op__insn_type$2 $0\mul_op__insn_type$2[6:0]$7103 + end + attribute \src "issuer_ls180.v:140401.3-140402.53" + process $proc$issuer_ls180.v:140401$7104 + assign { } { } + assign $0\mul_op__fn_unit$3[11:0]$7105 \mul_op__fn_unit$3$next + sync posedge \coresync_clk + update \mul_op__fn_unit$3 $0\mul_op__fn_unit$3[11:0]$7105 + end + attribute \src "issuer_ls180.v:140403.3-140404.67" + process $proc$issuer_ls180.v:140403$7106 + assign { } { } + assign $0\mul_op__imm_data__data$4[63:0]$7107 \mul_op__imm_data__data$4$next + sync posedge \coresync_clk + update \mul_op__imm_data__data$4 $0\mul_op__imm_data__data$4[63:0]$7107 + end + attribute \src "issuer_ls180.v:140405.3-140406.63" + process $proc$issuer_ls180.v:140405$7108 + assign { } { } + assign $0\mul_op__imm_data__ok$5[0:0]$7109 \mul_op__imm_data__ok$5$next + sync posedge \coresync_clk + update \mul_op__imm_data__ok$5 $0\mul_op__imm_data__ok$5[0:0]$7109 + end + attribute \src "issuer_ls180.v:140407.3-140408.51" + process $proc$issuer_ls180.v:140407$7110 + assign { } { } + assign $0\mul_op__rc__rc$6[0:0]$7111 \mul_op__rc__rc$6$next + sync posedge \coresync_clk + update \mul_op__rc__rc$6 $0\mul_op__rc__rc$6[0:0]$7111 + end + attribute \src "issuer_ls180.v:140409.3-140410.51" + process $proc$issuer_ls180.v:140409$7112 + assign { } { } + assign $0\mul_op__rc__ok$7[0:0]$7113 \mul_op__rc__ok$7$next + sync posedge \coresync_clk + update \mul_op__rc__ok$7 $0\mul_op__rc__ok$7[0:0]$7113 + end + attribute \src "issuer_ls180.v:140411.3-140412.51" + process $proc$issuer_ls180.v:140411$7114 + assign { } { } + assign $0\mul_op__oe__oe$8[0:0]$7115 \mul_op__oe__oe$8$next + sync posedge \coresync_clk + update \mul_op__oe__oe$8 $0\mul_op__oe__oe$8[0:0]$7115 + end + attribute \src "issuer_ls180.v:140413.3-140414.51" + process $proc$issuer_ls180.v:140413$7116 + assign { } { } + assign $0\mul_op__oe__ok$9[0:0]$7117 \mul_op__oe__ok$9$next + sync posedge \coresync_clk + update \mul_op__oe__ok$9 $0\mul_op__oe__ok$9[0:0]$7117 + end + attribute \src "issuer_ls180.v:140415.3-140416.59" + process $proc$issuer_ls180.v:140415$7118 + assign { } { } + assign $0\mul_op__write_cr0$10[0:0]$7119 \mul_op__write_cr0$10$next + sync posedge \coresync_clk + update \mul_op__write_cr0$10 $0\mul_op__write_cr0$10[0:0]$7119 + end + attribute \src "issuer_ls180.v:140417.3-140418.57" + process $proc$issuer_ls180.v:140417$7120 + assign { } { } + assign $0\mul_op__is_32bit$11[0:0]$7121 \mul_op__is_32bit$11$next + sync posedge \coresync_clk + update \mul_op__is_32bit$11 $0\mul_op__is_32bit$11[0:0]$7121 + end + attribute \src "issuer_ls180.v:140419.3-140420.59" + process $proc$issuer_ls180.v:140419$7122 + assign { } { } + assign $0\mul_op__is_signed$12[0:0]$7123 \mul_op__is_signed$12$next + sync posedge \coresync_clk + update \mul_op__is_signed$12 $0\mul_op__is_signed$12[0:0]$7123 + end + attribute \src "issuer_ls180.v:140421.3-140422.49" + process $proc$issuer_ls180.v:140421$7124 + assign { } { } + assign $0\mul_op__insn$13[31:0]$7125 \mul_op__insn$13$next + sync posedge \coresync_clk + update \mul_op__insn$13 $0\mul_op__insn$13[31:0]$7125 + end + attribute \src "issuer_ls180.v:140423.3-140424.33" + process $proc$issuer_ls180.v:140423$7126 + assign { } { } + assign $0\muxid$1[1:0]$7127 \muxid$1$next + sync posedge \coresync_clk + update \muxid$1 $0\muxid$1[1:0]$7127 + end + attribute \src "issuer_ls180.v:140425.3-140426.29" + process $proc$issuer_ls180.v:140425$7128 + assign { } { } + assign $0\r_busy[0:0] \r_busy$next + sync posedge \coresync_clk + update \r_busy $0\r_busy[0:0] + end + attribute \src "issuer_ls180.v:140513.3-140530.6" + process $proc$issuer_ls180.v:140513$7129 + assign { } { } + assign { } { } + assign { } { } + assign $0\r_busy$next[0:0]$7130 $2\r_busy$next[0:0]$7132 + attribute \src "issuer_ls180.v:140514.5-140514.29" + switch \initial + attribute \src "issuer_ls180.v:140514.9-140514.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\r_busy$next[0:0]$7131 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\r_busy$next[0:0]$7131 1'0 + case + assign $1\r_busy$next[0:0]$7131 \r_busy + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\r_busy$next[0:0]$7132 1'0 + case + assign $2\r_busy$next[0:0]$7132 $1\r_busy$next[0:0]$7131 + end + sync always + update \r_busy$next $0\r_busy$next[0:0]$7130 + end + attribute \src "issuer_ls180.v:140531.3-140543.6" + process $proc$issuer_ls180.v:140531$7133 + assign { } { } + assign { } { } + assign $0\muxid$1$next[1:0]$7134 $1\muxid$1$next[1:0]$7135 + attribute \src "issuer_ls180.v:140532.5-140532.29" + switch \initial + attribute \src "issuer_ls180.v:140532.9-140532.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\muxid$1$next[1:0]$7135 \muxid$58 + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\muxid$1$next[1:0]$7135 \muxid$58 + case + assign $1\muxid$1$next[1:0]$7135 \muxid$1 + end + sync always + update \muxid$1$next $0\muxid$1$next[1:0]$7134 + end + attribute \src "issuer_ls180.v:140544.3-140579.6" + process $proc$issuer_ls180.v:140544$7136 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\mul_op__fn_unit$3$next[11:0]$7137 $1\mul_op__fn_unit$3$next[11:0]$7149 + assign { } { } + assign { } { } + assign $0\mul_op__insn$13$next[31:0]$7140 $1\mul_op__insn$13$next[31:0]$7152 + assign $0\mul_op__insn_type$2$next[6:0]$7141 $1\mul_op__insn_type$2$next[6:0]$7153 + assign $0\mul_op__is_32bit$11$next[0:0]$7142 $1\mul_op__is_32bit$11$next[0:0]$7154 + assign $0\mul_op__is_signed$12$next[0:0]$7143 $1\mul_op__is_signed$12$next[0:0]$7155 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\mul_op__write_cr0$10$next[0:0]$7148 $1\mul_op__write_cr0$10$next[0:0]$7160 + assign $0\mul_op__imm_data__data$4$next[63:0]$7138 $2\mul_op__imm_data__data$4$next[63:0]$7161 + assign $0\mul_op__imm_data__ok$5$next[0:0]$7139 $2\mul_op__imm_data__ok$5$next[0:0]$7162 + assign $0\mul_op__oe__oe$8$next[0:0]$7144 $2\mul_op__oe__oe$8$next[0:0]$7163 + assign $0\mul_op__oe__ok$9$next[0:0]$7145 $2\mul_op__oe__ok$9$next[0:0]$7164 + assign $0\mul_op__rc__ok$7$next[0:0]$7146 $2\mul_op__rc__ok$7$next[0:0]$7165 + assign $0\mul_op__rc__rc$6$next[0:0]$7147 $2\mul_op__rc__rc$6$next[0:0]$7166 + attribute \src "issuer_ls180.v:140545.5-140545.29" + switch \initial + attribute \src "issuer_ls180.v:140545.9-140545.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'-1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { $1\mul_op__insn$13$next[31:0]$7152 $1\mul_op__is_signed$12$next[0:0]$7155 $1\mul_op__is_32bit$11$next[0:0]$7154 $1\mul_op__write_cr0$10$next[0:0]$7160 $1\mul_op__oe__ok$9$next[0:0]$7157 $1\mul_op__oe__oe$8$next[0:0]$7156 $1\mul_op__rc__ok$7$next[0:0]$7158 $1\mul_op__rc__rc$6$next[0:0]$7159 $1\mul_op__imm_data__ok$5$next[0:0]$7151 $1\mul_op__imm_data__data$4$next[63:0]$7150 $1\mul_op__fn_unit$3$next[11:0]$7149 $1\mul_op__insn_type$2$next[6:0]$7153 } { \mul_op__insn$70 \mul_op__is_signed$69 \mul_op__is_32bit$68 \mul_op__write_cr0$67 \mul_op__oe__ok$66 \mul_op__oe__oe$65 \mul_op__rc__ok$64 \mul_op__rc__rc$63 \mul_op__imm_data__ok$62 \mul_op__imm_data__data$61 \mul_op__fn_unit$60 \mul_op__insn_type$59 } + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'1- + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { $1\mul_op__insn$13$next[31:0]$7152 $1\mul_op__is_signed$12$next[0:0]$7155 $1\mul_op__is_32bit$11$next[0:0]$7154 $1\mul_op__write_cr0$10$next[0:0]$7160 $1\mul_op__oe__ok$9$next[0:0]$7157 $1\mul_op__oe__oe$8$next[0:0]$7156 $1\mul_op__rc__ok$7$next[0:0]$7158 $1\mul_op__rc__rc$6$next[0:0]$7159 $1\mul_op__imm_data__ok$5$next[0:0]$7151 $1\mul_op__imm_data__data$4$next[63:0]$7150 $1\mul_op__fn_unit$3$next[11:0]$7149 $1\mul_op__insn_type$2$next[6:0]$7153 } { \mul_op__insn$70 \mul_op__is_signed$69 \mul_op__is_32bit$68 \mul_op__write_cr0$67 \mul_op__oe__ok$66 \mul_op__oe__oe$65 \mul_op__rc__ok$64 \mul_op__rc__rc$63 \mul_op__imm_data__ok$62 \mul_op__imm_data__data$61 \mul_op__fn_unit$60 \mul_op__insn_type$59 } + case + assign $1\mul_op__fn_unit$3$next[11:0]$7149 \mul_op__fn_unit$3 + assign $1\mul_op__imm_data__data$4$next[63:0]$7150 \mul_op__imm_data__data$4 + assign $1\mul_op__imm_data__ok$5$next[0:0]$7151 \mul_op__imm_data__ok$5 + assign $1\mul_op__insn$13$next[31:0]$7152 \mul_op__insn$13 + assign $1\mul_op__insn_type$2$next[6:0]$7153 \mul_op__insn_type$2 + assign $1\mul_op__is_32bit$11$next[0:0]$7154 \mul_op__is_32bit$11 + assign $1\mul_op__is_signed$12$next[0:0]$7155 \mul_op__is_signed$12 + assign $1\mul_op__oe__oe$8$next[0:0]$7156 \mul_op__oe__oe$8 + assign $1\mul_op__oe__ok$9$next[0:0]$7157 \mul_op__oe__ok$9 + assign $1\mul_op__rc__ok$7$next[0:0]$7158 \mul_op__rc__ok$7 + assign $1\mul_op__rc__rc$6$next[0:0]$7159 \mul_op__rc__rc$6 + assign $1\mul_op__write_cr0$10$next[0:0]$7160 \mul_op__write_cr0$10 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $2\mul_op__imm_data__data$4$next[63:0]$7161 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\mul_op__imm_data__ok$5$next[0:0]$7162 1'0 + assign $2\mul_op__rc__rc$6$next[0:0]$7166 1'0 + assign $2\mul_op__rc__ok$7$next[0:0]$7165 1'0 + assign $2\mul_op__oe__oe$8$next[0:0]$7163 1'0 + assign $2\mul_op__oe__ok$9$next[0:0]$7164 1'0 + case + assign $2\mul_op__imm_data__data$4$next[63:0]$7161 $1\mul_op__imm_data__data$4$next[63:0]$7150 + assign $2\mul_op__imm_data__ok$5$next[0:0]$7162 $1\mul_op__imm_data__ok$5$next[0:0]$7151 + assign $2\mul_op__oe__oe$8$next[0:0]$7163 $1\mul_op__oe__oe$8$next[0:0]$7156 + assign $2\mul_op__oe__ok$9$next[0:0]$7164 $1\mul_op__oe__ok$9$next[0:0]$7157 + assign $2\mul_op__rc__ok$7$next[0:0]$7165 $1\mul_op__rc__ok$7$next[0:0]$7158 + assign $2\mul_op__rc__rc$6$next[0:0]$7166 $1\mul_op__rc__rc$6$next[0:0]$7159 + end + sync always + update \mul_op__fn_unit$3$next $0\mul_op__fn_unit$3$next[11:0]$7137 + update \mul_op__imm_data__data$4$next $0\mul_op__imm_data__data$4$next[63:0]$7138 + update \mul_op__imm_data__ok$5$next $0\mul_op__imm_data__ok$5$next[0:0]$7139 + update \mul_op__insn$13$next $0\mul_op__insn$13$next[31:0]$7140 + update \mul_op__insn_type$2$next $0\mul_op__insn_type$2$next[6:0]$7141 + update \mul_op__is_32bit$11$next $0\mul_op__is_32bit$11$next[0:0]$7142 + update \mul_op__is_signed$12$next $0\mul_op__is_signed$12$next[0:0]$7143 + update \mul_op__oe__oe$8$next $0\mul_op__oe__oe$8$next[0:0]$7144 + update \mul_op__oe__ok$9$next $0\mul_op__oe__ok$9$next[0:0]$7145 + update \mul_op__rc__ok$7$next $0\mul_op__rc__ok$7$next[0:0]$7146 + update \mul_op__rc__rc$6$next $0\mul_op__rc__rc$6$next[0:0]$7147 + update \mul_op__write_cr0$10$next $0\mul_op__write_cr0$10$next[0:0]$7148 + end + attribute \src "issuer_ls180.v:140580.3-140598.6" + process $proc$issuer_ls180.v:140580$7167 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\o$14$next[63:0]$7169 $1\o$14$next[63:0]$7171 + assign $0\o_ok$next[0:0]$7168 $2\o_ok$next[0:0]$7172 + attribute \src "issuer_ls180.v:140581.5-140581.29" + switch \initial + attribute \src "issuer_ls180.v:140581.9-140581.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'-1 + assign { } { } + assign { } { } + assign { $1\o_ok$next[0:0]$7170 $1\o$14$next[63:0]$7171 } { \o_ok$72 \o$71 } + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'1- + assign { } { } + assign { } { } + assign { $1\o_ok$next[0:0]$7170 $1\o$14$next[63:0]$7171 } { \o_ok$72 \o$71 } + case + assign $1\o_ok$next[0:0]$7170 \o_ok + assign $1\o$14$next[63:0]$7171 \o$14 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\o_ok$next[0:0]$7172 1'0 + case + assign $2\o_ok$next[0:0]$7172 $1\o_ok$next[0:0]$7170 + end + sync always + update \o_ok$next $0\o_ok$next[0:0]$7168 + update \o$14$next $0\o$14$next[63:0]$7169 + end + attribute \src "issuer_ls180.v:140599.3-140617.6" + process $proc$issuer_ls180.v:140599$7173 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\cr_a$next[3:0]$7174 $1\cr_a$next[3:0]$7176 + assign { } { } + assign $0\cr_a_ok$next[0:0]$7175 $2\cr_a_ok$next[0:0]$7178 + attribute \src "issuer_ls180.v:140600.5-140600.29" + switch \initial + attribute \src "issuer_ls180.v:140600.9-140600.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'-1 + assign { } { } + assign { } { } + assign { $1\cr_a_ok$next[0:0]$7177 $1\cr_a$next[3:0]$7176 } { \cr_a_ok$74 \cr_a$73 } + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'1- + assign { } { } + assign { } { } + assign { $1\cr_a_ok$next[0:0]$7177 $1\cr_a$next[3:0]$7176 } { \cr_a_ok$74 \cr_a$73 } + case + assign $1\cr_a$next[3:0]$7176 \cr_a + assign $1\cr_a_ok$next[0:0]$7177 \cr_a_ok + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\cr_a_ok$next[0:0]$7178 1'0 + case + assign $2\cr_a_ok$next[0:0]$7178 $1\cr_a_ok$next[0:0]$7177 + end + sync always + update \cr_a$next $0\cr_a$next[3:0]$7174 + update \cr_a_ok$next $0\cr_a_ok$next[0:0]$7175 + end + attribute \src "issuer_ls180.v:140618.3-140636.6" + process $proc$issuer_ls180.v:140618$7179 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\xer_ov$next[1:0]$7180 $1\xer_ov$next[1:0]$7182 + assign { } { } + assign $0\xer_ov_ok$next[0:0]$7181 $2\xer_ov_ok$next[0:0]$7184 + attribute \src "issuer_ls180.v:140619.5-140619.29" + switch \initial + attribute \src "issuer_ls180.v:140619.9-140619.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'-1 + assign { } { } + assign { } { } + assign { $1\xer_ov_ok$next[0:0]$7183 $1\xer_ov$next[1:0]$7182 } { \xer_ov_ok$76 \xer_ov$75 } + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'1- + assign { } { } + assign { } { } + assign { $1\xer_ov_ok$next[0:0]$7183 $1\xer_ov$next[1:0]$7182 } { \xer_ov_ok$76 \xer_ov$75 } + case + assign $1\xer_ov$next[1:0]$7182 \xer_ov + assign $1\xer_ov_ok$next[0:0]$7183 \xer_ov_ok + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\xer_ov_ok$next[0:0]$7184 1'0 + case + assign $2\xer_ov_ok$next[0:0]$7184 $1\xer_ov_ok$next[0:0]$7183 + end + sync always + update \xer_ov$next $0\xer_ov$next[1:0]$7180 + update \xer_ov_ok$next $0\xer_ov_ok$next[0:0]$7181 + end + attribute \src "issuer_ls180.v:140637.3-140655.6" + process $proc$issuer_ls180.v:140637$7185 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\xer_so$15$next[0:0]$7187 $1\xer_so$15$next[0:0]$7189 + assign $0\xer_so_ok$next[0:0]$7186 $2\xer_so_ok$next[0:0]$7190 + attribute \src "issuer_ls180.v:140638.5-140638.29" + switch \initial + attribute \src "issuer_ls180.v:140638.9-140638.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'-1 + assign { } { } + assign { } { } + assign { $1\xer_so_ok$next[0:0]$7188 $1\xer_so$15$next[0:0]$7189 } { \xer_so_ok$78 \xer_so$77 } + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'1- + assign { } { } + assign { } { } + assign { $1\xer_so_ok$next[0:0]$7188 $1\xer_so$15$next[0:0]$7189 } { \xer_so_ok$78 \xer_so$77 } + case + assign $1\xer_so_ok$next[0:0]$7188 \xer_so_ok + assign $1\xer_so$15$next[0:0]$7189 \xer_so$15 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\xer_so_ok$next[0:0]$7190 1'0 + case + assign $2\xer_so_ok$next[0:0]$7190 $1\xer_so_ok$next[0:0]$7188 + end + sync always + update \xer_so_ok$next $0\xer_so_ok$next[0:0]$7186 + update \xer_so$15$next $0\xer_so$15$next[0:0]$7187 + end + connect \$56 $and$issuer_ls180.v:140382$7091_Y + connect \cr_a$51 4'0000 + connect \cr_a_ok$52 1'0 + connect \p_ready_o \n_i_rdy_data + connect \n_valid_o \r_busy + connect { \xer_so_ok$78 \xer_so$77 } { \output_xer_so_ok \output_xer_so$48 } + connect { \xer_ov_ok$76 \xer_ov$75 } { \output_xer_ov_ok \output_xer_ov$47 } + connect { \cr_a_ok$74 \cr_a$73 } { \output_cr_a_ok \output_cr_a$46 } + connect { \o_ok$72 \o$71 } { \output_o_ok$45 \output_o$44 } + connect { \mul_op__insn$70 \mul_op__is_signed$69 \mul_op__is_32bit$68 \mul_op__write_cr0$67 \mul_op__oe__ok$66 \mul_op__oe__oe$65 \mul_op__rc__ok$64 \mul_op__rc__rc$63 \mul_op__imm_data__ok$62 \mul_op__imm_data__data$61 \mul_op__fn_unit$60 \mul_op__insn_type$59 } { \output_mul_op__insn$43 \output_mul_op__is_signed$42 \output_mul_op__is_32bit$41 \output_mul_op__write_cr0$40 \output_mul_op__oe__ok$39 \output_mul_op__oe__oe$38 \output_mul_op__rc__ok$37 \output_mul_op__rc__rc$36 \output_mul_op__imm_data__ok$35 \output_mul_op__imm_data__data$34 \output_mul_op__fn_unit$33 \output_mul_op__insn_type$32 } + connect \muxid$58 \output_muxid$31 + connect \p_valid_i_p_ready_o \$56 + connect \n_i_rdy_data \n_ready_i + connect \p_valid_i$55 \p_valid_i + connect { \xer_so_ok$54 \output_xer_so } { \mul3_xer_so_ok \mul3_xer_so$30 } + connect { \xer_ov_ok$53 \output_xer_ov } { \mul3_xer_ov_ok \mul3_xer_ov } + connect { \cr_a_ok$50 \output_cr_a } 5'00000 + connect { \output_o_ok \output_o } { \mul3_o_ok \mul3_o$29 } + connect { \output_mul_op__insn \output_mul_op__is_signed \output_mul_op__is_32bit \output_mul_op__write_cr0 \output_mul_op__oe__ok \output_mul_op__oe__oe \output_mul_op__rc__ok \output_mul_op__rc__rc \output_mul_op__imm_data__ok \output_mul_op__imm_data__data \output_mul_op__fn_unit \output_mul_op__insn_type } { \mul3_mul_op__insn$28 \mul3_mul_op__is_signed$27 \mul3_mul_op__is_32bit$26 \mul3_mul_op__write_cr0$25 \mul3_mul_op__oe__ok$24 \mul3_mul_op__oe__oe$23 \mul3_mul_op__rc__ok$22 \mul3_mul_op__rc__rc$21 \mul3_mul_op__imm_data__ok$20 \mul3_mul_op__imm_data__data$19 \mul3_mul_op__fn_unit$18 \mul3_mul_op__insn_type$17 } + connect \output_muxid \mul3_muxid$16 + connect \neg_res32$49 \neg_res32 + connect \mul3_neg_res \neg_res + connect \mul3_xer_so \xer_so + connect \mul3_o \o + connect { \mul3_mul_op__insn \mul3_mul_op__is_signed \mul3_mul_op__is_32bit \mul3_mul_op__write_cr0 \mul3_mul_op__oe__ok \mul3_mul_op__oe__oe \mul3_mul_op__rc__ok \mul3_mul_op__rc__rc \mul3_mul_op__imm_data__ok \mul3_mul_op__imm_data__data \mul3_mul_op__fn_unit \mul3_mul_op__insn_type } { \mul_op__insn \mul_op__is_signed \mul_op__is_32bit \mul_op__write_cr0 \mul_op__oe__ok \mul_op__oe__oe \mul_op__rc__ok \mul_op__rc__rc \mul_op__imm_data__ok \mul_op__imm_data__data \mul_op__fn_unit \mul_op__insn_type } + connect \mul3_muxid \muxid +end +attribute \src "issuer_ls180.v:140685.1-140696.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.fus.alu0.alu_alu0.n" +attribute \generator "nMigen" +module \n + attribute \src "issuer_ls180.v:140694.17-140694.111" + wire $and$issuer_ls180.v:140694$7229_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" + wire input 1 \n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" + wire input 2 \n_valid_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:251" + wire \trigger + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" + cell $and $and$issuer_ls180.v:140694$7229 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \n_ready_i + connect \B \n_valid_o + connect \Y $and$issuer_ls180.v:140694$7229_Y + end + connect \$1 $and$issuer_ls180.v:140694$7229_Y + connect \trigger \$1 +end +attribute \src "issuer_ls180.v:140700.1-140711.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.fus.shiftrot0.alu_shift_rot0.n" +attribute \generator "nMigen" +module \n$106 + attribute \src "issuer_ls180.v:140709.17-140709.111" + wire $and$issuer_ls180.v:140709$7230_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" + wire input 1 \n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" + wire input 2 \n_valid_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:251" + wire \trigger + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" + cell $and $and$issuer_ls180.v:140709$7230 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \n_ready_i + connect \B \n_valid_o + connect \Y $and$issuer_ls180.v:140709$7230_Y + end + connect \$1 $and$issuer_ls180.v:140709$7230_Y + connect \trigger \$1 +end +attribute \src "issuer_ls180.v:140715.1-140726.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.fus.shiftrot0.alu_shift_rot0.pipe1.n" +attribute \generator "nMigen" +module \n$109 + attribute \src "issuer_ls180.v:140724.17-140724.111" + wire $and$issuer_ls180.v:140724$7231_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" + wire input 1 \n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" + wire input 2 \n_valid_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:251" + wire \trigger + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" + cell $and $and$issuer_ls180.v:140724$7231 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \n_ready_i + connect \B \n_valid_o + connect \Y $and$issuer_ls180.v:140724$7231_Y + end + connect \$1 $and$issuer_ls180.v:140724$7231_Y + connect \trigger \$1 +end +attribute \src "issuer_ls180.v:140730.1-140741.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.fus.shiftrot0.alu_shift_rot0.pipe2.n" +attribute \generator "nMigen" +module \n$114 + attribute \src "issuer_ls180.v:140739.17-140739.111" + wire $and$issuer_ls180.v:140739$7232_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" + wire input 1 \n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" + wire input 2 \n_valid_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:251" + wire \trigger + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" + cell $and $and$issuer_ls180.v:140739$7232 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \n_ready_i + connect \B \n_valid_o + connect \Y $and$issuer_ls180.v:140739$7232_Y + end + connect \$1 $and$issuer_ls180.v:140739$7232_Y + connect \trigger \$1 +end +attribute \src "issuer_ls180.v:140745.1-140756.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.fus.branch0.alu_branch0.n" +attribute \generator "nMigen" +module \n$18 + attribute \src "issuer_ls180.v:140754.17-140754.111" + wire $and$issuer_ls180.v:140754$7233_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" + wire input 1 \n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" + wire input 2 \n_valid_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:251" + wire \trigger + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" + cell $and $and$issuer_ls180.v:140754$7233 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \n_ready_i + connect \B \n_valid_o + connect \Y $and$issuer_ls180.v:140754$7233_Y + end + connect \$1 $and$issuer_ls180.v:140754$7233_Y + connect \trigger \$1 +end +attribute \src "issuer_ls180.v:140760.1-140771.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.fus.alu0.alu_alu0.pipe1.n" +attribute \generator "nMigen" +module \n$2 + attribute \src "issuer_ls180.v:140769.17-140769.111" + wire $and$issuer_ls180.v:140769$7234_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" + wire input 1 \n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" + wire input 2 \n_valid_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:251" + wire \trigger + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" + cell $and $and$issuer_ls180.v:140769$7234 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \n_ready_i + connect \B \n_valid_o + connect \Y $and$issuer_ls180.v:140769$7234_Y + end + connect \$1 $and$issuer_ls180.v:140769$7234_Y + connect \trigger \$1 +end +attribute \src "issuer_ls180.v:140775.1-140786.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.fus.branch0.alu_branch0.pipe.n" +attribute \generator "nMigen" +module \n$21 + attribute \src "issuer_ls180.v:140784.17-140784.111" + wire $and$issuer_ls180.v:140784$7235_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" + wire input 1 \n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" + wire input 2 \n_valid_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:251" + wire \trigger + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" + cell $and $and$issuer_ls180.v:140784$7235 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \n_ready_i + connect \B \n_valid_o + connect \Y $and$issuer_ls180.v:140784$7235_Y + end + connect \$1 $and$issuer_ls180.v:140784$7235_Y + connect \trigger \$1 +end +attribute \src "issuer_ls180.v:140790.1-140801.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.fus.trap0.alu_trap0.n" +attribute \generator "nMigen" +module \n$31 + attribute \src "issuer_ls180.v:140799.17-140799.111" + wire $and$issuer_ls180.v:140799$7236_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" + wire input 1 \n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" + wire input 2 \n_valid_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:251" + wire \trigger + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" + cell $and $and$issuer_ls180.v:140799$7236 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \n_ready_i + connect \B \n_valid_o + connect \Y $and$issuer_ls180.v:140799$7236_Y + end + connect \$1 $and$issuer_ls180.v:140799$7236_Y + connect \trigger \$1 +end +attribute \src "issuer_ls180.v:140805.1-140816.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.fus.trap0.alu_trap0.pipe.n" +attribute \generator "nMigen" +module \n$34 + attribute \src "issuer_ls180.v:140814.17-140814.111" + wire $and$issuer_ls180.v:140814$7237_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" + wire input 1 \n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" + wire input 2 \n_valid_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:251" + wire \trigger + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" + cell $and $and$issuer_ls180.v:140814$7237 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \n_ready_i + connect \B \n_valid_o + connect \Y $and$issuer_ls180.v:140814$7237_Y + end + connect \$1 $and$issuer_ls180.v:140814$7237_Y + connect \trigger \$1 +end +attribute \src "issuer_ls180.v:140820.1-140831.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.fus.alu0.alu_alu0.pipe2.n" +attribute \generator "nMigen" +module \n$4 + attribute \src "issuer_ls180.v:140829.17-140829.111" + wire $and$issuer_ls180.v:140829$7238_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" + wire input 1 \n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" + wire input 2 \n_valid_o + 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connect \A \n_ready_i + connect \B \n_valid_o + connect \Y $and$issuer_ls180.v:141039$7252_Y + end + connect \$1 $and$issuer_ls180.v:141039$7252_Y + connect \trigger \$1 +end +attribute \src "issuer_ls180.v:141045.1-141056.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.fus.mul0.alu_mul0.mul_pipe3.n" +attribute \generator "nMigen" +module \n$96 + attribute \src "issuer_ls180.v:141054.17-141054.111" + wire $and$issuer_ls180.v:141054$7253_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" + wire input 1 \n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" + wire input 2 \n_valid_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:251" + wire \trigger + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" + cell $and $and$issuer_ls180.v:141054$7253 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \n_ready_i + connect \B \n_valid_o + connect \Y $and$issuer_ls180.v:141054$7253_Y + end + connect \$1 $and$issuer_ls180.v:141054$7253_Y + connect \trigger \$1 +end +attribute \src "issuer_ls180.v:141060.1-141118.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.fus.alu0.opc_l" +attribute \generator "nMigen" +module \opc_l + attribute \src "issuer_ls180.v:141061.7-141061.20" + wire $0\initial[0:0] + attribute \src "issuer_ls180.v:141106.3-141114.6" + wire $0\q_int$next[0:0]$7264 + attribute \src "issuer_ls180.v:141104.3-141105.27" + wire $0\q_int[0:0] + attribute \src "issuer_ls180.v:141106.3-141114.6" + wire $1\q_int$next[0:0]$7265 + attribute \src "issuer_ls180.v:141083.7-141083.19" + wire $1\q_int[0:0] + attribute \src "issuer_ls180.v:141096.17-141096.96" + wire $and$issuer_ls180.v:141096$7254_Y + attribute \src "issuer_ls180.v:141101.17-141101.96" + wire $and$issuer_ls180.v:141101$7259_Y + attribute \src "issuer_ls180.v:141098.18-141098.93" + wire $not$issuer_ls180.v:141098$7256_Y + attribute \src "issuer_ls180.v:141100.17-141100.92" + wire $not$issuer_ls180.v:141100$7258_Y + attribute \src "issuer_ls180.v:141103.17-141103.92" + wire $not$issuer_ls180.v:141103$7261_Y + attribute \src "issuer_ls180.v:141097.18-141097.98" + wire $or$issuer_ls180.v:141097$7255_Y + attribute \src "issuer_ls180.v:141099.18-141099.99" + wire $or$issuer_ls180.v:141099$7257_Y + attribute \src "issuer_ls180.v:141102.17-141102.97" + wire $or$issuer_ls180.v:141102$7260_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire \$13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" + wire input 5 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" + wire input 1 \coresync_rst + attribute \src "issuer_ls180.v:141061.7-141061.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire output 4 \q_opc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" + wire \qlq_opc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + wire \qn_opc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire input 3 \r_opc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire input 2 \s_opc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $and $and$issuer_ls180.v:141096$7254 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$7 + connect \Y $and$issuer_ls180.v:141096$7254_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $and $and$issuer_ls180.v:141101$7259 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$1 + connect \Y $and$issuer_ls180.v:141101$7259_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + cell $not $not$issuer_ls180.v:141098$7256 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_opc + connect \Y $not$issuer_ls180.v:141098$7256_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $not $not$issuer_ls180.v:141100$7258 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_opc + connect \Y $not$issuer_ls180.v:141100$7258_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $not $not$issuer_ls180.v:141103$7261 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_opc + connect \Y $not$issuer_ls180.v:141103$7261_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $or $or$issuer_ls180.v:141097$7255 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$9 + connect \B \s_opc + connect \Y $or$issuer_ls180.v:141097$7255_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + cell $or $or$issuer_ls180.v:141099$7257 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_opc + connect \B \q_int + connect \Y $or$issuer_ls180.v:141099$7257_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $or $or$issuer_ls180.v:141102$7260 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$3 + connect \B \s_opc + connect \Y $or$issuer_ls180.v:141102$7260_Y + end + attribute \src "issuer_ls180.v:141061.7-141061.20" + process $proc$issuer_ls180.v:141061$7266 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "issuer_ls180.v:141083.7-141083.19" + process $proc$issuer_ls180.v:141083$7267 + assign { } { } + assign $1\q_int[0:0] 1'0 + sync always + sync init + update \q_int $1\q_int[0:0] + end + attribute \src "issuer_ls180.v:141104.3-141105.27" + process $proc$issuer_ls180.v:141104$7262 + assign { } { } + assign $0\q_int[0:0] \q_int$next + sync posedge \coresync_clk + update \q_int $0\q_int[0:0] + end + attribute \src "issuer_ls180.v:141106.3-141114.6" + process $proc$issuer_ls180.v:141106$7263 + assign { } { } + assign { } { } + assign $0\q_int$next[0:0]$7264 $1\q_int$next[0:0]$7265 + attribute \src "issuer_ls180.v:141107.5-141107.29" + switch \initial + attribute \src "issuer_ls180.v:141107.9-141107.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\q_int$next[0:0]$7265 1'0 + case + assign $1\q_int$next[0:0]$7265 \$5 + end + sync always + update \q_int$next $0\q_int$next[0:0]$7264 + end + connect \$9 $and$issuer_ls180.v:141096$7254_Y + connect \$11 $or$issuer_ls180.v:141097$7255_Y + connect \$13 $not$issuer_ls180.v:141098$7256_Y + connect \$15 $or$issuer_ls180.v:141099$7257_Y + connect \$1 $not$issuer_ls180.v:141100$7258_Y + connect \$3 $and$issuer_ls180.v:141101$7259_Y + connect \$5 $or$issuer_ls180.v:141102$7260_Y + connect \$7 $not$issuer_ls180.v:141103$7261_Y + connect \qlq_opc \$15 + connect \qn_opc \$13 + connect \q_opc \$11 +end +attribute \src "issuer_ls180.v:141122.1-141180.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.fus.cr0.opc_l" +attribute \generator "nMigen" +module \opc_l$11 + attribute \src "issuer_ls180.v:141123.7-141123.20" + wire $0\initial[0:0] + attribute \src "issuer_ls180.v:141168.3-141176.6" + wire $0\q_int$next[0:0]$7278 + attribute \src "issuer_ls180.v:141166.3-141167.27" + wire $0\q_int[0:0] + attribute \src "issuer_ls180.v:141168.3-141176.6" + wire $1\q_int$next[0:0]$7279 + attribute \src "issuer_ls180.v:141145.7-141145.19" + wire $1\q_int[0:0] + attribute \src "issuer_ls180.v:141158.17-141158.96" + wire $and$issuer_ls180.v:141158$7268_Y + attribute \src "issuer_ls180.v:141163.17-141163.96" + wire $and$issuer_ls180.v:141163$7273_Y + attribute \src "issuer_ls180.v:141160.18-141160.93" + wire $not$issuer_ls180.v:141160$7270_Y + attribute \src "issuer_ls180.v:141162.17-141162.92" + wire $not$issuer_ls180.v:141162$7272_Y + attribute \src "issuer_ls180.v:141165.17-141165.92" + wire $not$issuer_ls180.v:141165$7275_Y + attribute \src "issuer_ls180.v:141159.18-141159.98" + wire $or$issuer_ls180.v:141159$7269_Y + attribute \src "issuer_ls180.v:141161.18-141161.99" + wire $or$issuer_ls180.v:141161$7271_Y + attribute \src "issuer_ls180.v:141164.17-141164.97" + wire $or$issuer_ls180.v:141164$7274_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire \$13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" + wire input 5 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" + wire input 1 \coresync_rst + attribute \src "issuer_ls180.v:141123.7-141123.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire output 4 \q_opc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" + wire \qlq_opc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + wire \qn_opc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire input 3 \r_opc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire input 2 \s_opc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $and $and$issuer_ls180.v:141158$7268 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$7 + connect \Y $and$issuer_ls180.v:141158$7268_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $and $and$issuer_ls180.v:141163$7273 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$1 + connect \Y $and$issuer_ls180.v:141163$7273_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + cell $not $not$issuer_ls180.v:141160$7270 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_opc + connect \Y $not$issuer_ls180.v:141160$7270_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $not $not$issuer_ls180.v:141162$7272 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_opc + connect \Y $not$issuer_ls180.v:141162$7272_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $not $not$issuer_ls180.v:141165$7275 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_opc + connect \Y $not$issuer_ls180.v:141165$7275_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $or $or$issuer_ls180.v:141159$7269 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$9 + connect \B \s_opc + connect \Y $or$issuer_ls180.v:141159$7269_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + cell $or $or$issuer_ls180.v:141161$7271 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_opc + connect \B \q_int + connect \Y $or$issuer_ls180.v:141161$7271_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $or $or$issuer_ls180.v:141164$7274 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$3 + connect \B \s_opc + connect \Y $or$issuer_ls180.v:141164$7274_Y + end + attribute \src "issuer_ls180.v:141123.7-141123.20" + process $proc$issuer_ls180.v:141123$7280 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "issuer_ls180.v:141145.7-141145.19" + process $proc$issuer_ls180.v:141145$7281 + assign { } { } + assign $1\q_int[0:0] 1'0 + sync always + sync init + update \q_int $1\q_int[0:0] + end + attribute \src "issuer_ls180.v:141166.3-141167.27" + process $proc$issuer_ls180.v:141166$7276 + assign { } { } + assign $0\q_int[0:0] \q_int$next + sync posedge \coresync_clk + update \q_int $0\q_int[0:0] + end + attribute \src "issuer_ls180.v:141168.3-141176.6" + process $proc$issuer_ls180.v:141168$7277 + assign { } { } + assign { } { } + assign $0\q_int$next[0:0]$7278 $1\q_int$next[0:0]$7279 + attribute \src "issuer_ls180.v:141169.5-141169.29" + switch \initial + attribute \src "issuer_ls180.v:141169.9-141169.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\q_int$next[0:0]$7279 1'0 + case + assign $1\q_int$next[0:0]$7279 \$5 + end + sync always + update \q_int$next $0\q_int$next[0:0]$7278 + end + connect \$9 $and$issuer_ls180.v:141158$7268_Y + connect \$11 $or$issuer_ls180.v:141159$7269_Y + connect \$13 $not$issuer_ls180.v:141160$7270_Y + connect \$15 $or$issuer_ls180.v:141161$7271_Y + connect \$1 $not$issuer_ls180.v:141162$7272_Y + connect \$3 $and$issuer_ls180.v:141163$7273_Y + connect \$5 $or$issuer_ls180.v:141164$7274_Y + connect \$7 $not$issuer_ls180.v:141165$7275_Y + connect \qlq_opc \$15 + connect \qn_opc \$13 + connect \q_opc \$11 +end +attribute \src "issuer_ls180.v:141184.1-141242.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.fus.shiftrot0.opc_l" +attribute \generator "nMigen" +module \opc_l$117 + attribute \src "issuer_ls180.v:141185.7-141185.20" + wire $0\initial[0:0] + attribute \src "issuer_ls180.v:141230.3-141238.6" + wire $0\q_int$next[0:0]$7292 + attribute \src "issuer_ls180.v:141228.3-141229.27" + wire $0\q_int[0:0] + attribute \src "issuer_ls180.v:141230.3-141238.6" + wire $1\q_int$next[0:0]$7293 + attribute \src "issuer_ls180.v:141207.7-141207.19" + wire $1\q_int[0:0] + attribute \src "issuer_ls180.v:141220.17-141220.96" + wire $and$issuer_ls180.v:141220$7282_Y + attribute \src "issuer_ls180.v:141225.17-141225.96" + wire $and$issuer_ls180.v:141225$7287_Y + attribute \src "issuer_ls180.v:141222.18-141222.93" + wire $not$issuer_ls180.v:141222$7284_Y + attribute \src "issuer_ls180.v:141224.17-141224.92" + wire $not$issuer_ls180.v:141224$7286_Y + attribute \src "issuer_ls180.v:141227.17-141227.92" + wire $not$issuer_ls180.v:141227$7289_Y + attribute \src "issuer_ls180.v:141221.18-141221.98" + wire $or$issuer_ls180.v:141221$7283_Y + attribute \src "issuer_ls180.v:141223.18-141223.99" + wire $or$issuer_ls180.v:141223$7285_Y + attribute \src "issuer_ls180.v:141226.17-141226.97" + wire $or$issuer_ls180.v:141226$7288_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire \$13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" + wire input 5 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" + wire input 1 \coresync_rst + attribute \src "issuer_ls180.v:141185.7-141185.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire output 4 \q_opc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" + wire \qlq_opc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + wire \qn_opc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire input 3 \r_opc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire input 2 \s_opc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $and $and$issuer_ls180.v:141220$7282 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$7 + connect \Y $and$issuer_ls180.v:141220$7282_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $and $and$issuer_ls180.v:141225$7287 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$1 + connect \Y $and$issuer_ls180.v:141225$7287_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + cell $not $not$issuer_ls180.v:141222$7284 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_opc + connect \Y $not$issuer_ls180.v:141222$7284_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $not $not$issuer_ls180.v:141224$7286 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_opc + connect \Y $not$issuer_ls180.v:141224$7286_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $not $not$issuer_ls180.v:141227$7289 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_opc + connect \Y $not$issuer_ls180.v:141227$7289_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $or $or$issuer_ls180.v:141221$7283 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$9 + connect \B \s_opc + connect \Y $or$issuer_ls180.v:141221$7283_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + cell $or $or$issuer_ls180.v:141223$7285 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_opc + connect \B \q_int + connect \Y $or$issuer_ls180.v:141223$7285_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $or $or$issuer_ls180.v:141226$7288 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$3 + connect \B \s_opc + connect \Y $or$issuer_ls180.v:141226$7288_Y + end + attribute \src "issuer_ls180.v:141185.7-141185.20" + process $proc$issuer_ls180.v:141185$7294 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "issuer_ls180.v:141207.7-141207.19" + process $proc$issuer_ls180.v:141207$7295 + assign { } { } + assign $1\q_int[0:0] 1'0 + sync always + sync init + update \q_int $1\q_int[0:0] + end + attribute \src "issuer_ls180.v:141228.3-141229.27" + process $proc$issuer_ls180.v:141228$7290 + assign { } { } + assign $0\q_int[0:0] \q_int$next + sync posedge \coresync_clk + update \q_int $0\q_int[0:0] + end + attribute \src "issuer_ls180.v:141230.3-141238.6" + process $proc$issuer_ls180.v:141230$7291 + assign { } { } + assign { } { } + assign $0\q_int$next[0:0]$7292 $1\q_int$next[0:0]$7293 + attribute \src "issuer_ls180.v:141231.5-141231.29" + switch \initial + attribute \src "issuer_ls180.v:141231.9-141231.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\q_int$next[0:0]$7293 1'0 + case + assign $1\q_int$next[0:0]$7293 \$5 + end + sync always + update \q_int$next $0\q_int$next[0:0]$7292 + end + connect \$9 $and$issuer_ls180.v:141220$7282_Y + connect \$11 $or$issuer_ls180.v:141221$7283_Y + connect \$13 $not$issuer_ls180.v:141222$7284_Y + connect \$15 $or$issuer_ls180.v:141223$7285_Y + connect \$1 $not$issuer_ls180.v:141224$7286_Y + connect \$3 $and$issuer_ls180.v:141225$7287_Y + connect \$5 $or$issuer_ls180.v:141226$7288_Y + connect \$7 $not$issuer_ls180.v:141227$7289_Y + connect \qlq_opc \$15 + connect \qn_opc \$13 + connect \q_opc \$11 +end +attribute \src "issuer_ls180.v:141246.1-141304.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.fus.ldst0.opc_l" +attribute \generator "nMigen" +module \opc_l$123 + attribute \src "issuer_ls180.v:141247.7-141247.20" + wire $0\initial[0:0] + attribute \src "issuer_ls180.v:141292.3-141300.6" + wire $0\q_int$next[0:0]$7306 + attribute \src "issuer_ls180.v:141290.3-141291.27" + wire $0\q_int[0:0] + attribute \src "issuer_ls180.v:141292.3-141300.6" + wire $1\q_int$next[0:0]$7307 + attribute \src "issuer_ls180.v:141269.7-141269.19" + wire $1\q_int[0:0] + attribute \src "issuer_ls180.v:141282.17-141282.96" + wire $and$issuer_ls180.v:141282$7296_Y + attribute \src "issuer_ls180.v:141287.17-141287.96" + wire $and$issuer_ls180.v:141287$7301_Y + attribute \src "issuer_ls180.v:141284.18-141284.93" + wire $not$issuer_ls180.v:141284$7298_Y + attribute \src "issuer_ls180.v:141286.17-141286.92" + wire $not$issuer_ls180.v:141286$7300_Y + attribute \src "issuer_ls180.v:141289.17-141289.92" + wire $not$issuer_ls180.v:141289$7303_Y + attribute \src "issuer_ls180.v:141283.18-141283.98" + wire $or$issuer_ls180.v:141283$7297_Y + attribute \src "issuer_ls180.v:141285.18-141285.99" + wire $or$issuer_ls180.v:141285$7299_Y + attribute \src "issuer_ls180.v:141288.17-141288.97" + wire $or$issuer_ls180.v:141288$7302_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire \$13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" + wire input 5 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" + wire input 1 \coresync_rst + attribute \src "issuer_ls180.v:141247.7-141247.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire output 4 \q_opc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" + wire \qlq_opc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + wire \qn_opc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire input 3 \r_opc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire input 2 \s_opc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $and $and$issuer_ls180.v:141282$7296 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$7 + connect \Y $and$issuer_ls180.v:141282$7296_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $and $and$issuer_ls180.v:141287$7301 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$1 + connect \Y $and$issuer_ls180.v:141287$7301_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + cell $not $not$issuer_ls180.v:141284$7298 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_opc + connect \Y $not$issuer_ls180.v:141284$7298_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $not $not$issuer_ls180.v:141286$7300 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_opc + connect \Y $not$issuer_ls180.v:141286$7300_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $not $not$issuer_ls180.v:141289$7303 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_opc + connect \Y $not$issuer_ls180.v:141289$7303_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $or $or$issuer_ls180.v:141283$7297 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$9 + connect \B \s_opc + connect \Y $or$issuer_ls180.v:141283$7297_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + cell $or $or$issuer_ls180.v:141285$7299 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_opc + connect \B \q_int + connect \Y $or$issuer_ls180.v:141285$7299_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $or $or$issuer_ls180.v:141288$7302 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$3 + connect \B \s_opc + connect \Y $or$issuer_ls180.v:141288$7302_Y + end + attribute \src "issuer_ls180.v:141247.7-141247.20" + process $proc$issuer_ls180.v:141247$7308 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "issuer_ls180.v:141269.7-141269.19" + process $proc$issuer_ls180.v:141269$7309 + assign { } { } + assign $1\q_int[0:0] 1'0 + sync always + sync init + update \q_int $1\q_int[0:0] + end + attribute \src "issuer_ls180.v:141290.3-141291.27" + process $proc$issuer_ls180.v:141290$7304 + assign { } { } + assign $0\q_int[0:0] \q_int$next + sync posedge \coresync_clk + update \q_int $0\q_int[0:0] + end + attribute \src "issuer_ls180.v:141292.3-141300.6" + process $proc$issuer_ls180.v:141292$7305 + assign { } { } + assign { } { } + assign $0\q_int$next[0:0]$7306 $1\q_int$next[0:0]$7307 + attribute \src "issuer_ls180.v:141293.5-141293.29" + switch \initial + attribute \src "issuer_ls180.v:141293.9-141293.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\q_int$next[0:0]$7307 1'0 + case + assign $1\q_int$next[0:0]$7307 \$5 + end + sync always + update \q_int$next $0\q_int$next[0:0]$7306 + end + connect \$9 $and$issuer_ls180.v:141282$7296_Y + connect \$11 $or$issuer_ls180.v:141283$7297_Y + connect \$13 $not$issuer_ls180.v:141284$7298_Y + connect \$15 $or$issuer_ls180.v:141285$7299_Y + connect \$1 $not$issuer_ls180.v:141286$7300_Y + connect \$3 $and$issuer_ls180.v:141287$7301_Y + connect \$5 $or$issuer_ls180.v:141288$7302_Y + connect \$7 $not$issuer_ls180.v:141289$7303_Y + connect \qlq_opc \$15 + connect \qn_opc \$13 + connect \q_opc \$11 +end +attribute \src "issuer_ls180.v:141308.1-141366.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.fus.branch0.opc_l" +attribute \generator "nMigen" +module \opc_l$24 + attribute \src "issuer_ls180.v:141309.7-141309.20" + wire $0\initial[0:0] + attribute \src "issuer_ls180.v:141354.3-141362.6" + wire $0\q_int$next[0:0]$7320 + attribute \src "issuer_ls180.v:141352.3-141353.27" + wire $0\q_int[0:0] + attribute \src "issuer_ls180.v:141354.3-141362.6" + wire $1\q_int$next[0:0]$7321 + attribute \src "issuer_ls180.v:141331.7-141331.19" + wire $1\q_int[0:0] + attribute \src "issuer_ls180.v:141344.17-141344.96" + wire $and$issuer_ls180.v:141344$7310_Y + attribute \src "issuer_ls180.v:141349.17-141349.96" + wire $and$issuer_ls180.v:141349$7315_Y + attribute \src "issuer_ls180.v:141346.18-141346.93" + wire $not$issuer_ls180.v:141346$7312_Y + attribute \src "issuer_ls180.v:141348.17-141348.92" + wire $not$issuer_ls180.v:141348$7314_Y + attribute \src "issuer_ls180.v:141351.17-141351.92" + wire $not$issuer_ls180.v:141351$7317_Y + attribute \src "issuer_ls180.v:141345.18-141345.98" + wire $or$issuer_ls180.v:141345$7311_Y + attribute \src "issuer_ls180.v:141347.18-141347.99" + wire $or$issuer_ls180.v:141347$7313_Y + attribute \src "issuer_ls180.v:141350.17-141350.97" + wire $or$issuer_ls180.v:141350$7316_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire \$13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" + wire input 5 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" + wire input 1 \coresync_rst + attribute \src "issuer_ls180.v:141309.7-141309.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire output 4 \q_opc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" + wire \qlq_opc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + wire \qn_opc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire input 3 \r_opc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire input 2 \s_opc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $and $and$issuer_ls180.v:141344$7310 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$7 + connect \Y $and$issuer_ls180.v:141344$7310_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $and $and$issuer_ls180.v:141349$7315 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$1 + connect \Y $and$issuer_ls180.v:141349$7315_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + cell $not $not$issuer_ls180.v:141346$7312 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_opc + connect \Y $not$issuer_ls180.v:141346$7312_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $not $not$issuer_ls180.v:141348$7314 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_opc + connect \Y $not$issuer_ls180.v:141348$7314_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $not $not$issuer_ls180.v:141351$7317 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_opc + connect \Y $not$issuer_ls180.v:141351$7317_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $or $or$issuer_ls180.v:141345$7311 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$9 + connect \B \s_opc + connect \Y $or$issuer_ls180.v:141345$7311_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + cell $or $or$issuer_ls180.v:141347$7313 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_opc + connect \B \q_int + connect \Y $or$issuer_ls180.v:141347$7313_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $or $or$issuer_ls180.v:141350$7316 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$3 + connect \B \s_opc + connect \Y $or$issuer_ls180.v:141350$7316_Y + end + attribute \src "issuer_ls180.v:141309.7-141309.20" + process $proc$issuer_ls180.v:141309$7322 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "issuer_ls180.v:141331.7-141331.19" + process $proc$issuer_ls180.v:141331$7323 + assign { } { } + assign $1\q_int[0:0] 1'0 + sync always + sync init + update \q_int $1\q_int[0:0] + end + attribute \src "issuer_ls180.v:141352.3-141353.27" + process $proc$issuer_ls180.v:141352$7318 + assign { } { } + assign $0\q_int[0:0] \q_int$next + sync posedge \coresync_clk + update \q_int $0\q_int[0:0] + end + attribute \src "issuer_ls180.v:141354.3-141362.6" + process $proc$issuer_ls180.v:141354$7319 + assign { } { } + assign { } { } + assign $0\q_int$next[0:0]$7320 $1\q_int$next[0:0]$7321 + attribute \src "issuer_ls180.v:141355.5-141355.29" + switch \initial + attribute \src "issuer_ls180.v:141355.9-141355.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\q_int$next[0:0]$7321 1'0 + case + assign $1\q_int$next[0:0]$7321 \$5 + end + sync always + update \q_int$next $0\q_int$next[0:0]$7320 + end + connect \$9 $and$issuer_ls180.v:141344$7310_Y + connect \$11 $or$issuer_ls180.v:141345$7311_Y + connect \$13 $not$issuer_ls180.v:141346$7312_Y + connect \$15 $or$issuer_ls180.v:141347$7313_Y + connect \$1 $not$issuer_ls180.v:141348$7314_Y + connect \$3 $and$issuer_ls180.v:141349$7315_Y + connect \$5 $or$issuer_ls180.v:141350$7316_Y + connect \$7 $not$issuer_ls180.v:141351$7317_Y + connect \qlq_opc \$15 + connect \qn_opc \$13 + connect \q_opc \$11 +end +attribute \src "issuer_ls180.v:141370.1-141428.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.fus.trap0.opc_l" +attribute \generator "nMigen" +module \opc_l$37 + attribute \src "issuer_ls180.v:141371.7-141371.20" + wire $0\initial[0:0] + attribute \src "issuer_ls180.v:141416.3-141424.6" + wire $0\q_int$next[0:0]$7334 + attribute \src "issuer_ls180.v:141414.3-141415.27" + wire $0\q_int[0:0] + attribute \src "issuer_ls180.v:141416.3-141424.6" + wire $1\q_int$next[0:0]$7335 + attribute \src "issuer_ls180.v:141393.7-141393.19" + wire $1\q_int[0:0] + attribute \src "issuer_ls180.v:141406.17-141406.96" + wire $and$issuer_ls180.v:141406$7324_Y + attribute \src "issuer_ls180.v:141411.17-141411.96" + wire $and$issuer_ls180.v:141411$7329_Y + attribute \src "issuer_ls180.v:141408.18-141408.93" + wire $not$issuer_ls180.v:141408$7326_Y + attribute \src "issuer_ls180.v:141410.17-141410.92" + wire $not$issuer_ls180.v:141410$7328_Y + attribute \src "issuer_ls180.v:141413.17-141413.92" + wire $not$issuer_ls180.v:141413$7331_Y + attribute \src "issuer_ls180.v:141407.18-141407.98" + wire $or$issuer_ls180.v:141407$7325_Y + attribute \src "issuer_ls180.v:141409.18-141409.99" + wire $or$issuer_ls180.v:141409$7327_Y + attribute \src "issuer_ls180.v:141412.17-141412.97" + wire $or$issuer_ls180.v:141412$7330_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire \$13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" + wire input 5 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" + wire input 1 \coresync_rst + attribute \src "issuer_ls180.v:141371.7-141371.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire output 4 \q_opc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" + wire \qlq_opc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + wire \qn_opc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire input 3 \r_opc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire input 2 \s_opc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $and $and$issuer_ls180.v:141406$7324 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$7 + connect \Y $and$issuer_ls180.v:141406$7324_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $and $and$issuer_ls180.v:141411$7329 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$1 + connect \Y $and$issuer_ls180.v:141411$7329_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + cell $not $not$issuer_ls180.v:141408$7326 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_opc + connect \Y $not$issuer_ls180.v:141408$7326_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $not $not$issuer_ls180.v:141410$7328 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_opc + connect \Y $not$issuer_ls180.v:141410$7328_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $not $not$issuer_ls180.v:141413$7331 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_opc + connect \Y $not$issuer_ls180.v:141413$7331_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $or $or$issuer_ls180.v:141407$7325 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$9 + connect \B \s_opc + connect \Y $or$issuer_ls180.v:141407$7325_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + cell $or $or$issuer_ls180.v:141409$7327 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_opc + connect \B \q_int + connect \Y $or$issuer_ls180.v:141409$7327_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $or $or$issuer_ls180.v:141412$7330 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$3 + connect \B \s_opc + connect \Y $or$issuer_ls180.v:141412$7330_Y + end + attribute \src "issuer_ls180.v:141371.7-141371.20" + process $proc$issuer_ls180.v:141371$7336 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "issuer_ls180.v:141393.7-141393.19" + process $proc$issuer_ls180.v:141393$7337 + assign { } { } + assign $1\q_int[0:0] 1'0 + sync always + sync init + update \q_int $1\q_int[0:0] + end + attribute \src "issuer_ls180.v:141414.3-141415.27" + process $proc$issuer_ls180.v:141414$7332 + assign { } { } + assign $0\q_int[0:0] \q_int$next + sync posedge \coresync_clk + update \q_int $0\q_int[0:0] + end + attribute \src "issuer_ls180.v:141416.3-141424.6" + process $proc$issuer_ls180.v:141416$7333 + assign { } { } + assign { } { } + assign $0\q_int$next[0:0]$7334 $1\q_int$next[0:0]$7335 + attribute \src "issuer_ls180.v:141417.5-141417.29" + switch \initial + attribute \src "issuer_ls180.v:141417.9-141417.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\q_int$next[0:0]$7335 1'0 + case + assign $1\q_int$next[0:0]$7335 \$5 + end + sync always + update \q_int$next $0\q_int$next[0:0]$7334 + end + connect \$9 $and$issuer_ls180.v:141406$7324_Y + connect \$11 $or$issuer_ls180.v:141407$7325_Y + connect \$13 $not$issuer_ls180.v:141408$7326_Y + connect \$15 $or$issuer_ls180.v:141409$7327_Y + connect \$1 $not$issuer_ls180.v:141410$7328_Y + connect \$3 $and$issuer_ls180.v:141411$7329_Y + connect \$5 $or$issuer_ls180.v:141412$7330_Y + connect \$7 $not$issuer_ls180.v:141413$7331_Y + connect \qlq_opc \$15 + connect \qn_opc \$13 + connect \q_opc \$11 +end +attribute \src "issuer_ls180.v:141432.1-141490.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.fus.logical0.opc_l" +attribute \generator "nMigen" +module \opc_l$53 + attribute \src "issuer_ls180.v:141433.7-141433.20" + wire $0\initial[0:0] + attribute \src "issuer_ls180.v:141478.3-141486.6" + wire $0\q_int$next[0:0]$7348 + attribute \src "issuer_ls180.v:141476.3-141477.27" + wire $0\q_int[0:0] + attribute \src "issuer_ls180.v:141478.3-141486.6" + wire $1\q_int$next[0:0]$7349 + attribute \src "issuer_ls180.v:141455.7-141455.19" + wire $1\q_int[0:0] + attribute \src "issuer_ls180.v:141468.17-141468.96" + wire $and$issuer_ls180.v:141468$7338_Y + attribute \src "issuer_ls180.v:141473.17-141473.96" + wire $and$issuer_ls180.v:141473$7343_Y + attribute \src "issuer_ls180.v:141470.18-141470.93" + wire $not$issuer_ls180.v:141470$7340_Y + attribute \src "issuer_ls180.v:141472.17-141472.92" + wire $not$issuer_ls180.v:141472$7342_Y + attribute \src "issuer_ls180.v:141475.17-141475.92" + wire $not$issuer_ls180.v:141475$7345_Y + attribute \src "issuer_ls180.v:141469.18-141469.98" + wire $or$issuer_ls180.v:141469$7339_Y + attribute \src "issuer_ls180.v:141471.18-141471.99" + wire $or$issuer_ls180.v:141471$7341_Y + attribute \src "issuer_ls180.v:141474.17-141474.97" + wire $or$issuer_ls180.v:141474$7344_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire \$13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" + wire input 5 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" + wire input 1 \coresync_rst + attribute \src "issuer_ls180.v:141433.7-141433.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire output 4 \q_opc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" + wire \qlq_opc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + wire \qn_opc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire input 3 \r_opc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire input 2 \s_opc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $and $and$issuer_ls180.v:141468$7338 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$7 + connect \Y $and$issuer_ls180.v:141468$7338_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $and $and$issuer_ls180.v:141473$7343 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$1 + connect \Y $and$issuer_ls180.v:141473$7343_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + cell $not $not$issuer_ls180.v:141470$7340 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_opc + connect \Y $not$issuer_ls180.v:141470$7340_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $not $not$issuer_ls180.v:141472$7342 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_opc + connect \Y $not$issuer_ls180.v:141472$7342_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $not $not$issuer_ls180.v:141475$7345 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_opc + connect \Y $not$issuer_ls180.v:141475$7345_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $or $or$issuer_ls180.v:141469$7339 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$9 + connect \B \s_opc + connect \Y $or$issuer_ls180.v:141469$7339_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + cell $or $or$issuer_ls180.v:141471$7341 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_opc + connect \B \q_int + connect \Y $or$issuer_ls180.v:141471$7341_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $or $or$issuer_ls180.v:141474$7344 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$3 + connect \B \s_opc + connect \Y $or$issuer_ls180.v:141474$7344_Y + end + attribute \src "issuer_ls180.v:141433.7-141433.20" + process $proc$issuer_ls180.v:141433$7350 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "issuer_ls180.v:141455.7-141455.19" + process $proc$issuer_ls180.v:141455$7351 + assign { } { } + assign $1\q_int[0:0] 1'0 + sync always + sync init + update \q_int $1\q_int[0:0] + end + attribute \src "issuer_ls180.v:141476.3-141477.27" + process $proc$issuer_ls180.v:141476$7346 + assign { } { } + assign $0\q_int[0:0] \q_int$next + sync posedge \coresync_clk + update \q_int $0\q_int[0:0] + end + attribute \src "issuer_ls180.v:141478.3-141486.6" + process $proc$issuer_ls180.v:141478$7347 + assign { } { } + assign { } { } + assign $0\q_int$next[0:0]$7348 $1\q_int$next[0:0]$7349 + attribute \src "issuer_ls180.v:141479.5-141479.29" + switch \initial + attribute \src "issuer_ls180.v:141479.9-141479.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\q_int$next[0:0]$7349 1'0 + case + assign $1\q_int$next[0:0]$7349 \$5 + end + sync always + update \q_int$next $0\q_int$next[0:0]$7348 + end + connect \$9 $and$issuer_ls180.v:141468$7338_Y + connect \$11 $or$issuer_ls180.v:141469$7339_Y + connect \$13 $not$issuer_ls180.v:141470$7340_Y + connect \$15 $or$issuer_ls180.v:141471$7341_Y + connect \$1 $not$issuer_ls180.v:141472$7342_Y + connect \$3 $and$issuer_ls180.v:141473$7343_Y + connect \$5 $or$issuer_ls180.v:141474$7344_Y + connect \$7 $not$issuer_ls180.v:141475$7345_Y + connect \qlq_opc \$15 + connect \qn_opc \$13 + connect \q_opc \$11 +end +attribute \src "issuer_ls180.v:141494.1-141552.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.fus.spr0.opc_l" +attribute \generator "nMigen" +module \opc_l$65 + attribute \src "issuer_ls180.v:141495.7-141495.20" + wire $0\initial[0:0] + attribute \src "issuer_ls180.v:141540.3-141548.6" + wire $0\q_int$next[0:0]$7362 + attribute \src "issuer_ls180.v:141538.3-141539.27" + wire $0\q_int[0:0] + attribute \src "issuer_ls180.v:141540.3-141548.6" + wire $1\q_int$next[0:0]$7363 + attribute \src "issuer_ls180.v:141517.7-141517.19" + wire $1\q_int[0:0] + attribute \src "issuer_ls180.v:141530.17-141530.96" + wire $and$issuer_ls180.v:141530$7352_Y + attribute \src "issuer_ls180.v:141535.17-141535.96" + wire $and$issuer_ls180.v:141535$7357_Y + attribute \src "issuer_ls180.v:141532.18-141532.93" + wire $not$issuer_ls180.v:141532$7354_Y + attribute \src "issuer_ls180.v:141534.17-141534.92" + wire $not$issuer_ls180.v:141534$7356_Y + attribute \src "issuer_ls180.v:141537.17-141537.92" + wire $not$issuer_ls180.v:141537$7359_Y + attribute \src "issuer_ls180.v:141531.18-141531.98" + wire $or$issuer_ls180.v:141531$7353_Y + attribute \src "issuer_ls180.v:141533.18-141533.99" + wire $or$issuer_ls180.v:141533$7355_Y + attribute \src "issuer_ls180.v:141536.17-141536.97" + wire $or$issuer_ls180.v:141536$7358_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire \$13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" + wire input 5 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" + wire input 1 \coresync_rst + attribute \src "issuer_ls180.v:141495.7-141495.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire output 4 \q_opc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" + wire \qlq_opc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + wire \qn_opc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire input 3 \r_opc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire input 2 \s_opc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $and $and$issuer_ls180.v:141530$7352 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$7 + connect \Y $and$issuer_ls180.v:141530$7352_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $and $and$issuer_ls180.v:141535$7357 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$1 + connect \Y $and$issuer_ls180.v:141535$7357_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + cell $not $not$issuer_ls180.v:141532$7354 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_opc + connect \Y $not$issuer_ls180.v:141532$7354_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $not $not$issuer_ls180.v:141534$7356 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_opc + connect \Y $not$issuer_ls180.v:141534$7356_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $not $not$issuer_ls180.v:141537$7359 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_opc + connect \Y $not$issuer_ls180.v:141537$7359_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $or $or$issuer_ls180.v:141531$7353 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$9 + connect \B \s_opc + connect \Y $or$issuer_ls180.v:141531$7353_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + cell $or $or$issuer_ls180.v:141533$7355 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_opc + connect \B \q_int + connect \Y $or$issuer_ls180.v:141533$7355_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $or $or$issuer_ls180.v:141536$7358 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$3 + connect \B \s_opc + connect \Y $or$issuer_ls180.v:141536$7358_Y + end + attribute \src "issuer_ls180.v:141495.7-141495.20" + process $proc$issuer_ls180.v:141495$7364 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "issuer_ls180.v:141517.7-141517.19" + process $proc$issuer_ls180.v:141517$7365 + assign { } { } + assign $1\q_int[0:0] 1'0 + sync always + sync init + update \q_int $1\q_int[0:0] + end + attribute \src "issuer_ls180.v:141538.3-141539.27" + process $proc$issuer_ls180.v:141538$7360 + assign { } { } + assign $0\q_int[0:0] \q_int$next + sync posedge \coresync_clk + update \q_int $0\q_int[0:0] + end + attribute \src "issuer_ls180.v:141540.3-141548.6" + process $proc$issuer_ls180.v:141540$7361 + assign { } { } + assign { } { } + assign $0\q_int$next[0:0]$7362 $1\q_int$next[0:0]$7363 + attribute \src "issuer_ls180.v:141541.5-141541.29" + switch \initial + attribute \src "issuer_ls180.v:141541.9-141541.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\q_int$next[0:0]$7363 1'0 + case + assign $1\q_int$next[0:0]$7363 \$5 + end + sync always + update \q_int$next $0\q_int$next[0:0]$7362 + end + connect \$9 $and$issuer_ls180.v:141530$7352_Y + connect \$11 $or$issuer_ls180.v:141531$7353_Y + connect \$13 $not$issuer_ls180.v:141532$7354_Y + connect \$15 $or$issuer_ls180.v:141533$7355_Y + connect \$1 $not$issuer_ls180.v:141534$7356_Y + connect \$3 $and$issuer_ls180.v:141535$7357_Y + connect \$5 $or$issuer_ls180.v:141536$7358_Y + connect \$7 $not$issuer_ls180.v:141537$7359_Y + connect \qlq_opc \$15 + connect \qn_opc \$13 + connect \q_opc \$11 +end +attribute \src "issuer_ls180.v:141556.1-141614.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.opc_l" +attribute \generator "nMigen" +module \opc_l$82 + attribute \src "issuer_ls180.v:141557.7-141557.20" + wire $0\initial[0:0] + attribute \src "issuer_ls180.v:141602.3-141610.6" + wire $0\q_int$next[0:0]$7376 + attribute \src "issuer_ls180.v:141600.3-141601.27" + wire $0\q_int[0:0] + attribute \src "issuer_ls180.v:141602.3-141610.6" + wire $1\q_int$next[0:0]$7377 + attribute \src "issuer_ls180.v:141579.7-141579.19" + wire $1\q_int[0:0] + attribute \src "issuer_ls180.v:141592.17-141592.96" + wire $and$issuer_ls180.v:141592$7366_Y + attribute \src "issuer_ls180.v:141597.17-141597.96" + wire $and$issuer_ls180.v:141597$7371_Y + attribute \src "issuer_ls180.v:141594.18-141594.93" + wire $not$issuer_ls180.v:141594$7368_Y + attribute \src "issuer_ls180.v:141596.17-141596.92" + wire $not$issuer_ls180.v:141596$7370_Y + attribute \src "issuer_ls180.v:141599.17-141599.92" + wire $not$issuer_ls180.v:141599$7373_Y + attribute \src "issuer_ls180.v:141593.18-141593.98" + wire $or$issuer_ls180.v:141593$7367_Y + attribute \src "issuer_ls180.v:141595.18-141595.99" + wire $or$issuer_ls180.v:141595$7369_Y + attribute \src "issuer_ls180.v:141598.17-141598.97" + wire $or$issuer_ls180.v:141598$7372_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire \$13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" + wire input 5 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" + wire input 1 \coresync_rst + attribute \src "issuer_ls180.v:141557.7-141557.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire output 4 \q_opc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" + wire \qlq_opc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + wire \qn_opc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire input 3 \r_opc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire input 2 \s_opc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $and $and$issuer_ls180.v:141592$7366 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$7 + connect \Y $and$issuer_ls180.v:141592$7366_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $and $and$issuer_ls180.v:141597$7371 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$1 + connect \Y $and$issuer_ls180.v:141597$7371_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + cell $not $not$issuer_ls180.v:141594$7368 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_opc + connect \Y $not$issuer_ls180.v:141594$7368_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $not $not$issuer_ls180.v:141596$7370 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_opc + connect \Y $not$issuer_ls180.v:141596$7370_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $not $not$issuer_ls180.v:141599$7373 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_opc + connect \Y $not$issuer_ls180.v:141599$7373_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $or $or$issuer_ls180.v:141593$7367 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$9 + connect \B \s_opc + connect \Y $or$issuer_ls180.v:141593$7367_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + cell $or $or$issuer_ls180.v:141595$7369 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_opc + connect \B \q_int + connect \Y $or$issuer_ls180.v:141595$7369_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $or $or$issuer_ls180.v:141598$7372 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$3 + connect \B \s_opc + connect \Y $or$issuer_ls180.v:141598$7372_Y + end + attribute \src "issuer_ls180.v:141557.7-141557.20" + process $proc$issuer_ls180.v:141557$7378 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "issuer_ls180.v:141579.7-141579.19" + process $proc$issuer_ls180.v:141579$7379 + assign { } { } + assign $1\q_int[0:0] 1'0 + sync always + sync init + update \q_int $1\q_int[0:0] + end + attribute \src "issuer_ls180.v:141600.3-141601.27" + process $proc$issuer_ls180.v:141600$7374 + assign { } { } + assign $0\q_int[0:0] \q_int$next + sync posedge \coresync_clk + update \q_int $0\q_int[0:0] + end + attribute \src "issuer_ls180.v:141602.3-141610.6" + process $proc$issuer_ls180.v:141602$7375 + assign { } { } + assign { } { } + assign $0\q_int$next[0:0]$7376 $1\q_int$next[0:0]$7377 + attribute \src "issuer_ls180.v:141603.5-141603.29" + switch \initial + attribute \src "issuer_ls180.v:141603.9-141603.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\q_int$next[0:0]$7377 1'0 + case + assign $1\q_int$next[0:0]$7377 \$5 + end + sync always + update \q_int$next $0\q_int$next[0:0]$7376 + end + connect \$9 $and$issuer_ls180.v:141592$7366_Y + connect \$11 $or$issuer_ls180.v:141593$7367_Y + connect \$13 $not$issuer_ls180.v:141594$7368_Y + connect \$15 $or$issuer_ls180.v:141595$7369_Y + connect \$1 $not$issuer_ls180.v:141596$7370_Y + connect \$3 $and$issuer_ls180.v:141597$7371_Y + connect \$5 $or$issuer_ls180.v:141598$7372_Y + connect \$7 $not$issuer_ls180.v:141599$7373_Y + connect \qlq_opc \$15 + connect \qn_opc \$13 + connect \q_opc \$11 +end +attribute \src "issuer_ls180.v:141618.1-141676.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.fus.mul0.opc_l" +attribute \generator "nMigen" +module \opc_l$99 + attribute \src "issuer_ls180.v:141619.7-141619.20" + wire $0\initial[0:0] + attribute \src "issuer_ls180.v:141664.3-141672.6" + wire $0\q_int$next[0:0]$7390 + attribute \src "issuer_ls180.v:141662.3-141663.27" + wire $0\q_int[0:0] + attribute \src "issuer_ls180.v:141664.3-141672.6" + wire $1\q_int$next[0:0]$7391 + attribute \src "issuer_ls180.v:141641.7-141641.19" + wire $1\q_int[0:0] + attribute \src "issuer_ls180.v:141654.17-141654.96" + wire $and$issuer_ls180.v:141654$7380_Y + attribute \src "issuer_ls180.v:141659.17-141659.96" + wire $and$issuer_ls180.v:141659$7385_Y + attribute \src "issuer_ls180.v:141656.18-141656.93" + wire $not$issuer_ls180.v:141656$7382_Y + attribute \src "issuer_ls180.v:141658.17-141658.92" + wire $not$issuer_ls180.v:141658$7384_Y + attribute \src "issuer_ls180.v:141661.17-141661.92" + wire $not$issuer_ls180.v:141661$7387_Y + attribute \src "issuer_ls180.v:141655.18-141655.98" + wire $or$issuer_ls180.v:141655$7381_Y + attribute \src "issuer_ls180.v:141657.18-141657.99" + wire $or$issuer_ls180.v:141657$7383_Y + attribute \src "issuer_ls180.v:141660.17-141660.97" + wire $or$issuer_ls180.v:141660$7386_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire \$13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" + wire input 5 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" + wire input 1 \coresync_rst + attribute \src "issuer_ls180.v:141619.7-141619.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire output 4 \q_opc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" + wire \qlq_opc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + wire \qn_opc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire input 3 \r_opc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire input 2 \s_opc + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $and $and$issuer_ls180.v:141654$7380 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter 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\enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 output 26 \alu_op__insn_type$2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 9 \alu_op__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 34 \alu_op__invert_in$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 11 \alu_op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 36 \alu_op__invert_out$12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 15 \alu_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 40 \alu_op__is_32bit$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 16 \alu_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 41 \alu_op__is_signed$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 7 \alu_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 32 \alu_op__oe__oe$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 8 \alu_op__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 33 \alu_op__oe__ok$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 14 \alu_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 39 \alu_op__output_carry$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 6 \alu_op__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 31 \alu_op__rc__ok$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 5 \alu_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 30 \alu_op__rc__rc$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 12 \alu_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 37 \alu_op__write_cr0$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 10 \alu_op__zero_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 35 \alu_op__zero_a$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:71" + wire width 4 \cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 4 input 21 \cr_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 4 output 46 \cr_a$22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 47 \cr_a_ok + attribute \src "issuer_ls180.v:141681.7-141681.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:69" + wire \is_cmp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:70" + wire \is_cmpeqb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:67" + wire \is_negative + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:65" + wire \is_nzero + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:66" + wire \is_positive + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:68" + wire \msb_test + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 input 54 \muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 output 25 \muxid$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 input 19 \o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 output 44 \o$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:38" + wire width 65 \o$28 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire input 20 \o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 45 \o_ok$21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:28" + wire \oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:29" + wire \oe$49 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:27" + wire \so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:50" + wire width 64 \target + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 2 input 22 \xer_ca + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 2 output 48 \xer_ca$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 49 \xer_ca_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 2 input 23 \xer_ov + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 2 output 50 \xer_ov$24 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 51 \xer_ov_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire input 24 \xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 52 \xer_so$25 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 53 \xer_so_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:29" + cell $and $and$issuer_ls180.v:142026$7394 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \alu_op__oe__oe + connect \B \alu_op__oe__ok + connect \Y $and$issuer_ls180.v:142026$7394_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:83" + cell $and $and$issuer_ls180.v:142034$7404 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \is_nzero + connect \B \$41 + connect \Y $and$issuer_ls180.v:142034$7404_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:30" + cell $and $and$issuer_ls180.v:142037$7407 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \alu_op__oe__oe + connect \B \alu_op__oe__ok + connect \Y $and$issuer_ls180.v:142037$7407_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:77" + cell $eq $eq$issuer_ls180.v:142030$7400 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \alu_op__insn_type + connect \B 7'0001010 + connect \Y $eq$issuer_ls180.v:142030$7400_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:78" + cell $eq $eq$issuer_ls180.v:142031$7401 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \alu_op__insn_type + connect \B 7'0001100 + connect \Y $eq$issuer_ls180.v:142031$7401_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:41" + cell $pos $extend$issuer_ls180.v:142028$7396 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 65 + connect \A \$30 + connect \Y $extend$issuer_ls180.v:142028$7396_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + cell $pos $extend$issuer_ls180.v:142029$7398 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 65 + connect \A \o + connect \Y $extend$issuer_ls180.v:142029$7398_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:41" + cell $not $not$issuer_ls180.v:142027$7395 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A \o + connect \Y $not$issuer_ls180.v:142027$7395_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:83" + cell $not $not$issuer_ls180.v:142033$7403 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \msb_test + connect \Y $not$issuer_ls180.v:142033$7403_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:88" + cell $not $not$issuer_ls180.v:142036$7406 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \is_nzero + connect \Y $not$issuer_ls180.v:142036$7406_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:85" + cell $or $or$issuer_ls180.v:142035$7405 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \is_cmpeqb + connect \B \is_cmp + connect \Y $or$issuer_ls180.v:142035$7405_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:33" + cell $or $or$issuer_ls180.v:142038$7408 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \xer_so + connect \B \xer_ov [0] + connect \Y $or$issuer_ls180.v:142038$7408_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:41" + cell $pos $pos$issuer_ls180.v:142028$7397 + parameter \A_SIGNED 0 + parameter \A_WIDTH 65 + parameter \Y_WIDTH 65 + connect \A $extend$issuer_ls180.v:142028$7396_Y + connect \Y $pos$issuer_ls180.v:142028$7397_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + cell $pos $pos$issuer_ls180.v:142029$7399 + parameter \A_SIGNED 0 + parameter \A_WIDTH 65 + parameter \Y_WIDTH 65 + connect \A $extend$issuer_ls180.v:142029$7398_Y + connect \Y $pos$issuer_ls180.v:142029$7399_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:81" + cell $reduce_or $reduce_or$issuer_ls180.v:142032$7402 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 1 + connect \A \target + connect \Y $reduce_or$issuer_ls180.v:142032$7402_Y + end + attribute \src "issuer_ls180.v:141681.7-141681.20" + process $proc$issuer_ls180.v:141681$7422 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "issuer_ls180.v:142039.3-142050.6" + process $proc$issuer_ls180.v:142039$7409 + assign { } { } + assign $0\so[0:0] $1\so[0:0] + attribute \src "issuer_ls180.v:142040.5-142040.29" + switch \initial + attribute \src "issuer_ls180.v:142040.9-142040.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:30" + switch \oe + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\so[0:0] \xer_so$25 + attribute \src "issuer_ls180.v:0.0-0.0" + case + assign { } { } + assign $1\so[0:0] \xer_so + end + sync always + update \so $0\so[0:0] + end + attribute \src "issuer_ls180.v:142051.3-142062.6" + process $proc$issuer_ls180.v:142051$7410 + assign { } { } + assign $0\cr0[3:0] $1\cr0[3:0] + attribute \src "issuer_ls180.v:142052.5-142052.29" + switch \initial + attribute \src "issuer_ls180.v:142052.9-142052.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:85" + switch \$45 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\cr0[3:0] \cr_a + attribute \src "issuer_ls180.v:0.0-0.0" + case + assign { } { } + assign $1\cr0[3:0] { \is_negative \is_positive \$47 \so } + end + sync always + update \cr0 $0\cr0[3:0] + end + attribute \src "issuer_ls180.v:142063.3-142074.6" + process $proc$issuer_ls180.v:142063$7411 + assign { } { } + assign $0\o$28[64:0]$7412 $1\o$28[64:0]$7413 + attribute \src "issuer_ls180.v:142064.5-142064.29" + switch \initial + attribute \src "issuer_ls180.v:142064.9-142064.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:40" + switch \alu_op__invert_out + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\o$28[64:0]$7413 \$29 + attribute \src "issuer_ls180.v:0.0-0.0" + case + assign { } { } + assign $1\o$28[64:0]$7413 \$33 + end + sync always + update \o$28 $0\o$28[64:0]$7412 + end + attribute \src "issuer_ls180.v:142075.3-142084.6" + process $proc$issuer_ls180.v:142075$7414 + assign { } { } + assign { } { } + assign $0\xer_so$25[0:0]$7415 $1\xer_so$25[0:0]$7416 + attribute \src "issuer_ls180.v:142076.5-142076.29" + switch \initial + attribute \src "issuer_ls180.v:142076.9-142076.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:31" + switch \oe$49 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\xer_so$25[0:0]$7416 \$52 + case + assign $1\xer_so$25[0:0]$7416 1'0 + end + sync always + update \xer_so$25 $0\xer_so$25[0:0]$7415 + end + attribute \src "issuer_ls180.v:142085.3-142094.6" + process $proc$issuer_ls180.v:142085$7417 + assign { } { } + assign { } { } + assign $0\xer_so_ok[0:0] $1\xer_so_ok[0:0] + attribute \src "issuer_ls180.v:142086.5-142086.29" + switch \initial + attribute \src "issuer_ls180.v:142086.9-142086.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:31" + switch \oe$49 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\xer_so_ok[0:0] 1'1 + case + assign $1\xer_so_ok[0:0] 1'0 + end + sync always + update \xer_so_ok $0\xer_so_ok[0:0] + end + attribute \src "issuer_ls180.v:142095.3-142104.6" + process $proc$issuer_ls180.v:142095$7418 + assign { } { } + assign { } { } + assign $0\xer_ov$24[1:0]$7419 $1\xer_ov$24[1:0]$7420 + attribute \src "issuer_ls180.v:142096.5-142096.29" + switch \initial + attribute \src "issuer_ls180.v:142096.9-142096.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:31" + switch \oe$49 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\xer_ov$24[1:0]$7420 \xer_ov + case + assign $1\xer_ov$24[1:0]$7420 2'00 + end + sync always + update \xer_ov$24 $0\xer_ov$24[1:0]$7419 + end + attribute \src "issuer_ls180.v:142105.3-142114.6" + process $proc$issuer_ls180.v:142105$7421 + assign { } { } + assign { } { } + assign $0\xer_ov_ok[0:0] $1\xer_ov_ok[0:0] + attribute \src "issuer_ls180.v:142106.5-142106.29" + switch \initial + attribute \src "issuer_ls180.v:142106.9-142106.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:31" + switch \oe$49 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\xer_ov_ok[0:0] 1'1 + case + assign $1\xer_ov_ok[0:0] 1'0 + end + sync always + update \xer_ov_ok $0\xer_ov_ok[0:0] + end + connect \$26 $and$issuer_ls180.v:142026$7394_Y + connect \$30 $not$issuer_ls180.v:142027$7395_Y + connect \$29 $pos$issuer_ls180.v:142028$7397_Y + connect \$33 $pos$issuer_ls180.v:142029$7399_Y + connect \$35 $eq$issuer_ls180.v:142030$7400_Y + connect \$37 $eq$issuer_ls180.v:142031$7401_Y + connect \$39 $reduce_or$issuer_ls180.v:142032$7402_Y + connect \$41 $not$issuer_ls180.v:142033$7403_Y + connect \$43 $and$issuer_ls180.v:142034$7404_Y + connect \$45 $or$issuer_ls180.v:142035$7405_Y + connect \$47 $not$issuer_ls180.v:142036$7406_Y + connect \$50 $and$issuer_ls180.v:142037$7407_Y + connect \$52 $or$issuer_ls180.v:142038$7408_Y + connect \oe$49 \$50 + connect { \alu_op__insn$19 \alu_op__data_len$18 \alu_op__is_signed$17 \alu_op__is_32bit$16 \alu_op__output_carry$15 \alu_op__input_carry$14 \alu_op__write_cr0$13 \alu_op__invert_out$12 \alu_op__zero_a$11 \alu_op__invert_in$10 \alu_op__oe__ok$9 \alu_op__oe__oe$8 \alu_op__rc__ok$7 \alu_op__rc__rc$6 \alu_op__imm_data__ok$5 \alu_op__imm_data__data$4 \alu_op__fn_unit$3 \alu_op__insn_type$2 } { \alu_op__insn \alu_op__data_len \alu_op__is_signed \alu_op__is_32bit \alu_op__output_carry \alu_op__input_carry \alu_op__write_cr0 \alu_op__invert_out \alu_op__zero_a \alu_op__invert_in \alu_op__oe__ok \alu_op__oe__oe \alu_op__rc__ok \alu_op__rc__rc \alu_op__imm_data__ok \alu_op__imm_data__data \alu_op__fn_unit \alu_op__insn_type } + connect \muxid$1 \muxid + connect \cr_a_ok \alu_op__write_cr0 + connect \cr_a$22 \cr0 + connect \o_ok$21 \o_ok + connect \o$20 \o$28 [63:0] + connect \is_positive \$43 + connect \is_negative \msb_test + connect \is_nzero \$39 + connect \msb_test \target [63] + connect \is_cmpeqb \$37 + connect \is_cmp \$35 + connect \xer_ca_ok \alu_op__output_carry + connect \xer_ca$23 \xer_ca + connect \target \o$28 [63:0] + connect \oe \$26 +end +attribute \src "issuer_ls180.v:142136.1-142480.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.fus.shiftrot0.alu_shift_rot0.pipe2.output" +attribute \generator "nMigen" +module \output$115 + attribute \src "issuer_ls180.v:142452.3-142463.6" + wire width 4 $0\cr0[3:0] + attribute \src "issuer_ls180.v:142137.7-142137.20" + wire $0\initial[0:0] + attribute \src "issuer_ls180.v:142452.3-142463.6" + wire width 4 $1\cr0[3:0] + attribute \src "issuer_ls180.v:142449.18-142449.112" + wire $and$issuer_ls180.v:142449$7429_Y + attribute \src "issuer_ls180.v:142445.18-142445.122" + wire $eq$issuer_ls180.v:142445$7425_Y + attribute \src "issuer_ls180.v:142446.18-142446.122" + wire $eq$issuer_ls180.v:142446$7426_Y + attribute \src "issuer_ls180.v:142444.18-142444.101" + wire width 65 $extend$issuer_ls180.v:142444$7423_Y + attribute \src "issuer_ls180.v:142448.18-142448.107" + wire $not$issuer_ls180.v:142448$7428_Y + attribute \src "issuer_ls180.v:142451.18-142451.107" + wire $not$issuer_ls180.v:142451$7431_Y + attribute \src "issuer_ls180.v:142450.18-142450.115" + wire $or$issuer_ls180.v:142450$7430_Y + attribute \src "issuer_ls180.v:142444.18-142444.101" + wire width 65 $pos$issuer_ls180.v:142444$7424_Y + attribute \src "issuer_ls180.v:142447.18-142447.105" + wire $reduce_or$issuer_ls180.v:142447$7427_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 65 \$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:77" + wire \$25 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:78" + wire \$27 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:81" + wire \$29 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:83" + wire \$31 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:83" + wire \$33 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:85" + wire \$35 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:88" + wire \$37 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:71" + wire width 4 \cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 4 input 19 \cr_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 4 output 41 \cr_a$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 42 \cr_a_ok + attribute \src "issuer_ls180.v:142137.7-142137.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:69" + wire \is_cmp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:70" + wire \is_cmpeqb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:67" + wire \is_negative + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:65" + wire \is_nzero + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:66" + wire \is_positive + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:68" + wire \msb_test + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 input 45 \muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 output 22 \muxid$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 input 17 \o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 output 39 \o$18 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:38" + wire width 65 \o$22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire input 18 \o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 40 \o_ok$19 + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 input 2 \sr_op__fn_unit + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 output 24 \sr_op__fn_unit$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 input 3 \sr_op__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 output 25 \sr_op__imm_data__data$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 4 \sr_op__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 26 \sr_op__imm_data__ok$5 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 input 10 \sr_op__input_carry + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 output 32 \sr_op__input_carry$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 12 \sr_op__input_cr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 34 \sr_op__input_cr$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 16 \sr_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 output 38 \sr_op__insn$17 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 input 1 \sr_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 output 23 \sr_op__insn_type$2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 14 \sr_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 36 \sr_op__is_32bit$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 15 \sr_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 37 \sr_op__is_signed$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 7 \sr_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 29 \sr_op__oe__oe$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 8 \sr_op__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 30 \sr_op__oe__ok$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 11 \sr_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 33 \sr_op__output_carry$12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 13 \sr_op__output_cr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 35 \sr_op__output_cr$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 6 \sr_op__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 28 \sr_op__rc__ok$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 5 \sr_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 27 \sr_op__rc__rc$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 9 \sr_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 31 \sr_op__write_cr0$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:50" + wire width 64 \target + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 2 input 21 \xer_ca + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 2 output 43 \xer_ca$21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 44 \xer_ca_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire input 20 \xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:83" + cell $and $and$issuer_ls180.v:142449$7429 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \is_nzero + connect \B \$31 + connect \Y $and$issuer_ls180.v:142449$7429_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:77" + cell $eq $eq$issuer_ls180.v:142445$7425 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \sr_op__insn_type + connect \B 7'0001010 + connect \Y $eq$issuer_ls180.v:142445$7425_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:78" + cell $eq $eq$issuer_ls180.v:142446$7426 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \sr_op__insn_type + connect \B 7'0001100 + connect \Y $eq$issuer_ls180.v:142446$7426_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + cell $pos $extend$issuer_ls180.v:142444$7423 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 65 + connect \A \o + connect \Y $extend$issuer_ls180.v:142444$7423_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:83" + cell $not $not$issuer_ls180.v:142448$7428 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \msb_test + connect \Y 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"/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 39 \logical_op__is_signed$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 7 \logical_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 30 \logical_op__oe__oe$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 8 \logical_op__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 31 \logical_op__oe__ok$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 14 \logical_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 37 \logical_op__output_carry$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 6 \logical_op__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 29 \logical_op__rc__ok$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 5 \logical_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 28 \logical_op__rc__rc$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 13 \logical_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 36 \logical_op__write_cr0$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 10 \logical_op__zero_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 33 \logical_op__zero_a$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:68" + wire \msb_test + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 input 46 \muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 output 23 \muxid$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 input 19 \o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 output 42 \o$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:38" + wire width 65 \o$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire input 20 \o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 43 \o_ok$21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:50" + wire width 64 \target + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire input 22 \xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:83" + cell $and $and$issuer_ls180.v:142805$7443 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \is_nzero + connect \B \$36 + connect \Y $and$issuer_ls180.v:142805$7443_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:77" + cell $eq $eq$issuer_ls180.v:142801$7439 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \logical_op__insn_type + connect \B 7'0001010 + connect \Y $eq$issuer_ls180.v:142801$7439_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:78" + cell $eq $eq$issuer_ls180.v:142802$7440 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \logical_op__insn_type + connect \B 7'0001100 + connect \Y $eq$issuer_ls180.v:142802$7440_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:41" + cell $pos $extend$issuer_ls180.v:142799$7435 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 65 + connect \A \$25 + connect \Y $extend$issuer_ls180.v:142799$7435_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + cell $pos $extend$issuer_ls180.v:142800$7437 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 65 + connect \A \o + connect \Y $extend$issuer_ls180.v:142800$7437_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:41" + cell $not $not$issuer_ls180.v:142798$7434 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A \o + connect \Y $not$issuer_ls180.v:142798$7434_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:83" + cell $not $not$issuer_ls180.v:142804$7442 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \msb_test + connect \Y $not$issuer_ls180.v:142804$7442_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:88" + cell $not $not$issuer_ls180.v:142807$7445 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \is_nzero + connect \Y $not$issuer_ls180.v:142807$7445_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:85" + cell $or $or$issuer_ls180.v:142806$7444 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \is_cmpeqb + connect \B \is_cmp + connect \Y $or$issuer_ls180.v:142806$7444_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:41" + cell $pos $pos$issuer_ls180.v:142799$7436 + parameter \A_SIGNED 0 + parameter \A_WIDTH 65 + parameter \Y_WIDTH 65 + connect \A $extend$issuer_ls180.v:142799$7435_Y + connect \Y $pos$issuer_ls180.v:142799$7436_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + cell $pos $pos$issuer_ls180.v:142800$7438 + parameter \A_SIGNED 0 + parameter \A_WIDTH 65 + parameter \Y_WIDTH 65 + connect \A $extend$issuer_ls180.v:142800$7437_Y + connect \Y $pos$issuer_ls180.v:142800$7438_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:81" + cell $reduce_or $reduce_or$issuer_ls180.v:142803$7441 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 1 + connect \A \target + connect \Y $reduce_or$issuer_ls180.v:142803$7441_Y + end + attribute \src "issuer_ls180.v:142485.7-142485.20" + process $proc$issuer_ls180.v:142485$7450 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "issuer_ls180.v:142808.3-142819.6" + process $proc$issuer_ls180.v:142808$7446 + assign { } { } + assign $0\o$23[64:0]$7447 $1\o$23[64:0]$7448 + attribute \src "issuer_ls180.v:142809.5-142809.29" + switch \initial + attribute \src "issuer_ls180.v:142809.9-142809.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:40" + switch \logical_op__invert_out + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\o$23[64:0]$7448 \$24 + attribute \src "issuer_ls180.v:0.0-0.0" + case + assign { } { } + assign $1\o$23[64:0]$7448 \$28 + end + sync always + update \o$23 $0\o$23[64:0]$7447 + end + attribute \src "issuer_ls180.v:142820.3-142831.6" + process $proc$issuer_ls180.v:142820$7449 + assign { } { } + assign $0\cr0[3:0] $1\cr0[3:0] + attribute \src "issuer_ls180.v:142821.5-142821.29" + switch \initial + attribute \src "issuer_ls180.v:142821.9-142821.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:85" + switch \$40 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\cr0[3:0] \cr_a + attribute \src "issuer_ls180.v:0.0-0.0" + case + assign { } { } + assign $1\cr0[3:0] { \is_negative \is_positive \$42 \xer_so } + end + sync always + update \cr0 $0\cr0[3:0] + end + connect \$25 $not$issuer_ls180.v:142798$7434_Y + connect \$24 $pos$issuer_ls180.v:142799$7436_Y + connect \$28 $pos$issuer_ls180.v:142800$7438_Y + connect \$30 $eq$issuer_ls180.v:142801$7439_Y + connect \$32 $eq$issuer_ls180.v:142802$7440_Y + connect \$34 $reduce_or$issuer_ls180.v:142803$7441_Y + connect \$36 $not$issuer_ls180.v:142804$7442_Y + connect \$38 $and$issuer_ls180.v:142805$7443_Y + connect \$40 $or$issuer_ls180.v:142806$7444_Y + connect \$42 $not$issuer_ls180.v:142807$7445_Y + connect { \logical_op__insn$19 \logical_op__data_len$18 \logical_op__is_signed$17 \logical_op__is_32bit$16 \logical_op__output_carry$15 \logical_op__write_cr0$14 \logical_op__invert_out$13 \logical_op__input_carry$12 \logical_op__zero_a$11 \logical_op__invert_in$10 \logical_op__oe__ok$9 \logical_op__oe__oe$8 \logical_op__rc__ok$7 \logical_op__rc__rc$6 \logical_op__imm_data__ok$5 \logical_op__imm_data__data$4 \logical_op__fn_unit$3 \logical_op__insn_type$2 } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in \logical_op__oe__ok \logical_op__oe__oe \logical_op__rc__ok \logical_op__rc__rc \logical_op__imm_data__ok \logical_op__imm_data__data \logical_op__fn_unit \logical_op__insn_type } + connect \muxid$1 \muxid + connect \cr_a_ok \logical_op__write_cr0 + connect \cr_a$22 \cr0 + connect \o_ok$21 \o_ok + connect \o$20 \o$23 [63:0] + connect \is_positive \$38 + connect \is_negative \msb_test + connect \is_nzero \$34 + connect \msb_test \target [63] + connect \is_cmpeqb \$32 + connect \is_cmp \$30 + connect \target \o$23 [63:0] +end +attribute \src "issuer_ls180.v:142849.1-143293.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_end.output" +attribute \generator "nMigen" +module \output$80 + attribute \src "issuer_ls180.v:143214.3-143225.6" + wire width 4 $0\cr0[3:0] + attribute \src "issuer_ls180.v:142850.7-142850.20" + wire $0\initial[0:0] + attribute \src "issuer_ls180.v:143226.3-143237.6" + wire width 65 $0\o$27[64:0]$7469 + attribute \src "issuer_ls180.v:143202.3-143213.6" + wire $0\so[0:0] + attribute \src "issuer_ls180.v:143258.3-143267.6" + wire width 2 $0\xer_ov$23[1:0]$7476 + attribute \src "issuer_ls180.v:143268.3-143277.6" + wire $0\xer_ov_ok[0:0] + attribute \src "issuer_ls180.v:143238.3-143247.6" + wire $0\xer_so$24[0:0]$7472 + attribute \src "issuer_ls180.v:143248.3-143257.6" + wire $0\xer_so_ok[0:0] + attribute \src "issuer_ls180.v:143214.3-143225.6" + wire width 4 $1\cr0[3:0] + attribute \src "issuer_ls180.v:143226.3-143237.6" + wire width 65 $1\o$27[64:0]$7470 + attribute \src "issuer_ls180.v:143202.3-143213.6" + wire $1\so[0:0] + attribute \src "issuer_ls180.v:143258.3-143267.6" + wire width 2 $1\xer_ov$23[1:0]$7477 + attribute \src "issuer_ls180.v:143268.3-143277.6" + wire $1\xer_ov_ok[0:0] + attribute \src "issuer_ls180.v:143238.3-143247.6" + wire $1\xer_so$24[0:0]$7473 + attribute \src "issuer_ls180.v:143248.3-143257.6" + wire $1\xer_so_ok[0:0] + attribute \src "issuer_ls180.v:143189.18-143189.136" + wire $and$issuer_ls180.v:143189$7451_Y + attribute \src "issuer_ls180.v:143197.18-143197.112" + wire $and$issuer_ls180.v:143197$7461_Y + attribute \src "issuer_ls180.v:143200.18-143200.133" + wire $and$issuer_ls180.v:143200$7464_Y + attribute \src "issuer_ls180.v:143193.18-143193.127" + wire $eq$issuer_ls180.v:143193$7457_Y + attribute \src "issuer_ls180.v:143194.18-143194.127" + wire $eq$issuer_ls180.v:143194$7458_Y + attribute \src "issuer_ls180.v:143191.18-143191.103" + wire width 65 $extend$issuer_ls180.v:143191$7453_Y + attribute \src "issuer_ls180.v:143192.18-143192.101" + wire width 65 $extend$issuer_ls180.v:143192$7455_Y + attribute \src "issuer_ls180.v:143190.18-143190.100" + wire width 64 $not$issuer_ls180.v:143190$7452_Y + attribute \src "issuer_ls180.v:143196.18-143196.107" + wire $not$issuer_ls180.v:143196$7460_Y + attribute \src "issuer_ls180.v:143199.18-143199.107" + wire $not$issuer_ls180.v:143199$7463_Y + attribute \src "issuer_ls180.v:143198.18-143198.115" + wire $or$issuer_ls180.v:143198$7462_Y + attribute \src "issuer_ls180.v:143201.18-143201.112" + wire $or$issuer_ls180.v:143201$7465_Y + attribute \src "issuer_ls180.v:143191.18-143191.103" + wire width 65 $pos$issuer_ls180.v:143191$7454_Y + attribute \src "issuer_ls180.v:143192.18-143192.101" + wire width 65 $pos$issuer_ls180.v:143192$7456_Y + attribute \src "issuer_ls180.v:143195.18-143195.105" + wire $reduce_or$issuer_ls180.v:143195$7459_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:29" + wire \$25 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:41" + wire width 65 \$28 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:41" + wire width 64 \$29 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 65 \$32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:77" + wire \$34 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:78" + wire \$36 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:81" + wire \$38 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:83" + wire \$40 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:83" + wire \$42 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:85" + wire \$44 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:88" + wire \$46 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:30" + wire \$49 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:33" + wire \$51 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:71" + wire width 4 \cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 4 input 21 \cr_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 4 output 45 \cr_a$22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 46 \cr_a_ok + attribute \src "issuer_ls180.v:142850.7-142850.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:69" + wire \is_cmp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:70" + wire \is_cmpeqb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:67" + wire \is_negative + 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attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 input 2 \logical_op__fn_unit + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 output 26 \logical_op__fn_unit$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 input 3 \logical_op__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 output 27 \logical_op__imm_data__data$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 4 \logical_op__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 28 \logical_op__imm_data__ok$5 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 input 11 \logical_op__input_carry + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 output 35 \logical_op__input_carry$12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 18 \logical_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 output 42 \logical_op__insn$19 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 input 1 \logical_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 output 25 \logical_op__insn_type$2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 9 \logical_op__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 33 \logical_op__invert_in$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 12 \logical_op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 36 \logical_op__invert_out$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 15 \logical_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 39 \logical_op__is_32bit$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 16 \logical_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 40 \logical_op__is_signed$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 7 \logical_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 31 \logical_op__oe__oe$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 8 \logical_op__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 32 \logical_op__oe__ok$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 14 \logical_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 38 \logical_op__output_carry$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 6 \logical_op__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 30 \logical_op__rc__ok$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 5 \logical_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 29 \logical_op__rc__rc$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 13 \logical_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 37 \logical_op__write_cr0$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 10 \logical_op__zero_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 34 \logical_op__zero_a$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:68" + wire \msb_test + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 input 51 \muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 output 24 \muxid$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 input 19 \o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 output 43 \o$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:38" + wire width 65 \o$27 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire input 20 \o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 44 \o_ok$21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:28" + wire \oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:29" + wire \oe$48 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:27" + wire \so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:50" + wire width 64 \target + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 2 input 22 \xer_ov + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 2 output 47 \xer_ov$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 48 \xer_ov_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire input 23 \xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 49 \xer_so$24 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 50 \xer_so_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:29" + cell $and $and$issuer_ls180.v:143189$7451 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \logical_op__oe__oe + connect \B \logical_op__oe__ok + connect \Y $and$issuer_ls180.v:143189$7451_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:83" + cell $and $and$issuer_ls180.v:143197$7461 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \is_nzero + connect \B \$40 + connect \Y $and$issuer_ls180.v:143197$7461_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:30" + cell $and $and$issuer_ls180.v:143200$7464 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \logical_op__oe__oe + connect \B \logical_op__oe__ok + connect \Y $and$issuer_ls180.v:143200$7464_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:77" + cell $eq $eq$issuer_ls180.v:143193$7457 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \logical_op__insn_type + connect \B 7'0001010 + connect \Y $eq$issuer_ls180.v:143193$7457_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:78" + cell $eq $eq$issuer_ls180.v:143194$7458 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \logical_op__insn_type + connect \B 7'0001100 + connect \Y $eq$issuer_ls180.v:143194$7458_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:41" + cell $pos $extend$issuer_ls180.v:143191$7453 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 65 + connect \A \$29 + connect \Y $extend$issuer_ls180.v:143191$7453_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + cell $pos $extend$issuer_ls180.v:143192$7455 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 65 + connect \A \o + connect \Y $extend$issuer_ls180.v:143192$7455_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:41" + cell $not $not$issuer_ls180.v:143190$7452 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A \o + connect \Y $not$issuer_ls180.v:143190$7452_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:83" + cell $not $not$issuer_ls180.v:143196$7460 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \msb_test + connect \Y $not$issuer_ls180.v:143196$7460_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:88" + cell $not $not$issuer_ls180.v:143199$7463 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \is_nzero + connect \Y $not$issuer_ls180.v:143199$7463_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:85" + cell $or $or$issuer_ls180.v:143198$7462 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \is_cmpeqb + connect \B \is_cmp + connect \Y $or$issuer_ls180.v:143198$7462_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:33" + cell $or $or$issuer_ls180.v:143201$7465 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \xer_so + connect \B \xer_ov [0] + connect \Y $or$issuer_ls180.v:143201$7465_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:41" + cell $pos $pos$issuer_ls180.v:143191$7454 + parameter \A_SIGNED 0 + parameter \A_WIDTH 65 + parameter \Y_WIDTH 65 + connect \A $extend$issuer_ls180.v:143191$7453_Y + connect \Y $pos$issuer_ls180.v:143191$7454_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + cell $pos $pos$issuer_ls180.v:143192$7456 + parameter \A_SIGNED 0 + parameter \A_WIDTH 65 + parameter \Y_WIDTH 65 + connect \A $extend$issuer_ls180.v:143192$7455_Y + connect \Y $pos$issuer_ls180.v:143192$7456_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:81" + cell $reduce_or $reduce_or$issuer_ls180.v:143195$7459 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 1 + connect \A \target + connect \Y $reduce_or$issuer_ls180.v:143195$7459_Y + end + attribute \src "issuer_ls180.v:142850.7-142850.20" + process $proc$issuer_ls180.v:142850$7479 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "issuer_ls180.v:143202.3-143213.6" + process $proc$issuer_ls180.v:143202$7466 + assign { } { } + assign $0\so[0:0] $1\so[0:0] + attribute \src "issuer_ls180.v:143203.5-143203.29" + switch \initial + attribute \src "issuer_ls180.v:143203.9-143203.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:30" + switch \oe + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\so[0:0] \xer_so$24 + attribute \src "issuer_ls180.v:0.0-0.0" + case + assign { } { } + assign $1\so[0:0] \xer_so + end + sync always + update \so $0\so[0:0] + end + attribute \src "issuer_ls180.v:143214.3-143225.6" + process $proc$issuer_ls180.v:143214$7467 + assign { } { } + assign $0\cr0[3:0] $1\cr0[3:0] + attribute \src "issuer_ls180.v:143215.5-143215.29" + switch \initial + attribute \src "issuer_ls180.v:143215.9-143215.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:85" + switch \$44 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\cr0[3:0] \cr_a + attribute \src "issuer_ls180.v:0.0-0.0" + case + assign { } { } + assign $1\cr0[3:0] { \is_negative \is_positive \$46 \so } + end + sync always + update \cr0 $0\cr0[3:0] + end + attribute \src "issuer_ls180.v:143226.3-143237.6" + process $proc$issuer_ls180.v:143226$7468 + assign { } { } + assign $0\o$27[64:0]$7469 $1\o$27[64:0]$7470 + attribute \src "issuer_ls180.v:143227.5-143227.29" + switch \initial + attribute \src "issuer_ls180.v:143227.9-143227.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:40" + switch \logical_op__invert_out + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\o$27[64:0]$7470 \$28 + attribute \src "issuer_ls180.v:0.0-0.0" + case + assign { } { } + assign $1\o$27[64:0]$7470 \$32 + end + sync always + update \o$27 $0\o$27[64:0]$7469 + end + attribute \src "issuer_ls180.v:143238.3-143247.6" + process $proc$issuer_ls180.v:143238$7471 + assign { } { } + assign { } { } + assign $0\xer_so$24[0:0]$7472 $1\xer_so$24[0:0]$7473 + attribute \src "issuer_ls180.v:143239.5-143239.29" + switch \initial + attribute \src "issuer_ls180.v:143239.9-143239.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:31" + switch \oe$48 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\xer_so$24[0:0]$7473 \$51 + case + assign $1\xer_so$24[0:0]$7473 1'0 + end + sync always + update \xer_so$24 $0\xer_so$24[0:0]$7472 + end + attribute \src "issuer_ls180.v:143248.3-143257.6" + process $proc$issuer_ls180.v:143248$7474 + assign { } { } + assign { } { } + assign $0\xer_so_ok[0:0] $1\xer_so_ok[0:0] + attribute \src "issuer_ls180.v:143249.5-143249.29" + switch \initial + attribute \src "issuer_ls180.v:143249.9-143249.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:31" + switch \oe$48 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\xer_so_ok[0:0] 1'1 + case + assign $1\xer_so_ok[0:0] 1'0 + end + sync always + update \xer_so_ok $0\xer_so_ok[0:0] + end + attribute \src "issuer_ls180.v:143258.3-143267.6" + process $proc$issuer_ls180.v:143258$7475 + assign { } { } + assign { } { } + assign $0\xer_ov$23[1:0]$7476 $1\xer_ov$23[1:0]$7477 + attribute \src "issuer_ls180.v:143259.5-143259.29" + switch \initial + attribute \src "issuer_ls180.v:143259.9-143259.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:31" + switch \oe$48 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\xer_ov$23[1:0]$7477 \xer_ov + case + assign $1\xer_ov$23[1:0]$7477 2'00 + end + sync always + update \xer_ov$23 $0\xer_ov$23[1:0]$7476 + end + attribute \src "issuer_ls180.v:143268.3-143277.6" + process $proc$issuer_ls180.v:143268$7478 + assign { } { } + assign { } { } + assign $0\xer_ov_ok[0:0] $1\xer_ov_ok[0:0] + attribute \src "issuer_ls180.v:143269.5-143269.29" + switch \initial + attribute \src "issuer_ls180.v:143269.9-143269.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:31" + switch \oe$48 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\xer_ov_ok[0:0] 1'1 + case + assign $1\xer_ov_ok[0:0] 1'0 + end + sync always + update \xer_ov_ok $0\xer_ov_ok[0:0] + end + connect \$25 $and$issuer_ls180.v:143189$7451_Y + connect \$29 $not$issuer_ls180.v:143190$7452_Y + connect \$28 $pos$issuer_ls180.v:143191$7454_Y + connect \$32 $pos$issuer_ls180.v:143192$7456_Y + connect \$34 $eq$issuer_ls180.v:143193$7457_Y + connect \$36 $eq$issuer_ls180.v:143194$7458_Y + connect \$38 $reduce_or$issuer_ls180.v:143195$7459_Y + connect \$40 $not$issuer_ls180.v:143196$7460_Y + connect \$42 $and$issuer_ls180.v:143197$7461_Y + connect \$44 $or$issuer_ls180.v:143198$7462_Y + connect \$46 $not$issuer_ls180.v:143199$7463_Y + connect \$49 $and$issuer_ls180.v:143200$7464_Y + connect \$51 $or$issuer_ls180.v:143201$7465_Y + connect \oe$48 \$49 + connect { \logical_op__insn$19 \logical_op__data_len$18 \logical_op__is_signed$17 \logical_op__is_32bit$16 \logical_op__output_carry$15 \logical_op__write_cr0$14 \logical_op__invert_out$13 \logical_op__input_carry$12 \logical_op__zero_a$11 \logical_op__invert_in$10 \logical_op__oe__ok$9 \logical_op__oe__oe$8 \logical_op__rc__ok$7 \logical_op__rc__rc$6 \logical_op__imm_data__ok$5 \logical_op__imm_data__data$4 \logical_op__fn_unit$3 \logical_op__insn_type$2 } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in \logical_op__oe__ok \logical_op__oe__oe \logical_op__rc__ok \logical_op__rc__rc \logical_op__imm_data__ok \logical_op__imm_data__data \logical_op__fn_unit \logical_op__insn_type } + connect \muxid$1 \muxid + connect \cr_a_ok \logical_op__write_cr0 + connect \cr_a$22 \cr0 + connect \o_ok$21 \o_ok + connect \o$20 \o$27 [63:0] + connect \is_positive \$42 + connect \is_negative \msb_test + connect \is_nzero \$38 + connect \msb_test \target [63] + connect \is_cmpeqb \$36 + connect \is_cmp \$34 + connect \target \o$27 [63:0] + connect \oe \$25 +end +attribute \src "issuer_ls180.v:143297.1-143692.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.fus.mul0.alu_mul0.mul_pipe3.output" +attribute \generator "nMigen" +module \output$97 + attribute \src "issuer_ls180.v:143624.3-143635.6" + wire width 4 $0\cr0[3:0] + attribute \src "issuer_ls180.v:143298.7-143298.20" + wire $0\initial[0:0] + attribute \src "issuer_ls180.v:143612.3-143623.6" + wire $0\so[0:0] + attribute \src "issuer_ls180.v:143656.3-143665.6" + wire width 2 $0\xer_ov$17[1:0]$7499 + attribute \src "issuer_ls180.v:143666.3-143675.6" + wire $0\xer_ov_ok[0:0] + attribute \src "issuer_ls180.v:143636.3-143645.6" + wire $0\xer_so$18[0:0]$7495 + attribute \src "issuer_ls180.v:143646.3-143655.6" + wire $0\xer_so_ok[0:0] + attribute \src "issuer_ls180.v:143624.3-143635.6" + wire width 4 $1\cr0[3:0] + attribute \src "issuer_ls180.v:143612.3-143623.6" + wire $1\so[0:0] + attribute \src "issuer_ls180.v:143656.3-143665.6" + wire width 2 $1\xer_ov$17[1:0]$7500 + attribute \src "issuer_ls180.v:143666.3-143675.6" + wire $1\xer_ov_ok[0:0] + attribute \src "issuer_ls180.v:143636.3-143645.6" + wire $1\xer_so$18[0:0]$7496 + attribute \src "issuer_ls180.v:143646.3-143655.6" + wire $1\xer_so_ok[0:0] + attribute \src "issuer_ls180.v:143601.18-143601.128" + wire $and$issuer_ls180.v:143601$7480_Y + attribute \src "issuer_ls180.v:143607.18-143607.112" + wire $and$issuer_ls180.v:143607$7487_Y + attribute \src "issuer_ls180.v:143610.18-143610.125" + wire $and$issuer_ls180.v:143610$7490_Y + attribute \src "issuer_ls180.v:143603.18-143603.123" + wire $eq$issuer_ls180.v:143603$7483_Y + attribute \src "issuer_ls180.v:143604.18-143604.123" + wire $eq$issuer_ls180.v:143604$7484_Y + attribute \src "issuer_ls180.v:143602.18-143602.101" + wire width 65 $extend$issuer_ls180.v:143602$7481_Y + attribute \src "issuer_ls180.v:143606.18-143606.107" + wire $not$issuer_ls180.v:143606$7486_Y + attribute \src "issuer_ls180.v:143609.18-143609.107" + wire $not$issuer_ls180.v:143609$7489_Y + attribute \src "issuer_ls180.v:143608.18-143608.115" + wire $or$issuer_ls180.v:143608$7488_Y + attribute \src "issuer_ls180.v:143611.18-143611.112" + wire $or$issuer_ls180.v:143611$7491_Y + attribute \src "issuer_ls180.v:143602.18-143602.101" + wire width 65 $pos$issuer_ls180.v:143602$7482_Y + attribute \src "issuer_ls180.v:143605.18-143605.105" + wire $reduce_or$issuer_ls180.v:143605$7485_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:29" + wire \$19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 65 \$22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:77" + wire \$24 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:78" + wire \$26 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:81" + wire \$28 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:83" + wire \$30 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:83" + wire \$32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:85" + wire \$34 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:88" + wire \$36 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:30" + wire \$39 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:33" + wire \$41 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:71" + wire width 4 \cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 4 input 15 \cr_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 4 output 33 \cr_a$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 34 \cr_a_ok + attribute \src "issuer_ls180.v:143298.7-143298.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:69" + wire \is_cmp + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:70" + wire \is_cmpeqb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:67" + wire \is_negative + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:65" + wire \is_nzero + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:66" + wire \is_positive + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:68" + wire \msb_test + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 input 2 \mul_op__fn_unit + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 output 20 \mul_op__fn_unit$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 input 3 \mul_op__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 output 21 \mul_op__imm_data__data$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 4 \mul_op__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 22 \mul_op__imm_data__ok$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 12 \mul_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 output 30 \mul_op__insn$13 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 input 1 \mul_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 output 19 \mul_op__insn_type$2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 10 \mul_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 28 \mul_op__is_32bit$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 11 \mul_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 29 \mul_op__is_signed$12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 7 \mul_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 25 \mul_op__oe__oe$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 8 \mul_op__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 26 \mul_op__oe__ok$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 6 \mul_op__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 24 \mul_op__rc__ok$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 5 \mul_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 23 \mul_op__rc__rc$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 9 \mul_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 27 \mul_op__write_cr0$10 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 input 39 \muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 output 18 \muxid$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 input 13 \o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 output 31 \o$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:38" + wire width 65 \o$21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire input 14 \o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 32 \o_ok$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:28" + wire \oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:29" + wire \oe$38 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:27" + wire \so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:50" + wire width 64 \target + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 2 input 16 \xer_ov + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 2 output 35 \xer_ov$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 36 \xer_ov_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire input 17 \xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 37 \xer_so$18 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 38 \xer_so_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:29" + cell $and $and$issuer_ls180.v:143601$7480 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \mul_op__oe__oe + connect \B \mul_op__oe__ok + connect \Y $and$issuer_ls180.v:143601$7480_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:83" + cell $and $and$issuer_ls180.v:143607$7487 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \is_nzero + connect \B \$30 + connect \Y $and$issuer_ls180.v:143607$7487_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:30" + cell $and $and$issuer_ls180.v:143610$7490 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \mul_op__oe__oe + connect \B \mul_op__oe__ok + connect \Y $and$issuer_ls180.v:143610$7490_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:77" + cell $eq $eq$issuer_ls180.v:143603$7483 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \mul_op__insn_type + connect \B 7'0001010 + connect \Y $eq$issuer_ls180.v:143603$7483_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:78" + cell $eq $eq$issuer_ls180.v:143604$7484 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \mul_op__insn_type + connect \B 7'0001100 + connect \Y $eq$issuer_ls180.v:143604$7484_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + cell $pos $extend$issuer_ls180.v:143602$7481 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 65 + connect \A \o + connect \Y $extend$issuer_ls180.v:143602$7481_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:83" + cell $not $not$issuer_ls180.v:143606$7486 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \msb_test + connect \Y $not$issuer_ls180.v:143606$7486_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:88" + cell $not $not$issuer_ls180.v:143609$7489 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \is_nzero + connect \Y $not$issuer_ls180.v:143609$7489_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:85" + cell $or $or$issuer_ls180.v:143608$7488 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \is_cmpeqb + connect \B \is_cmp + connect \Y $or$issuer_ls180.v:143608$7488_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:33" + cell $or $or$issuer_ls180.v:143611$7491 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \xer_so + connect \B \xer_ov [0] + connect \Y $or$issuer_ls180.v:143611$7491_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + cell $pos $pos$issuer_ls180.v:143602$7482 + parameter \A_SIGNED 0 + parameter \A_WIDTH 65 + parameter \Y_WIDTH 65 + connect \A $extend$issuer_ls180.v:143602$7481_Y + connect \Y $pos$issuer_ls180.v:143602$7482_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:81" + cell $reduce_or $reduce_or$issuer_ls180.v:143605$7485 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 1 + connect \A \target + connect \Y $reduce_or$issuer_ls180.v:143605$7485_Y + end + attribute \src "issuer_ls180.v:143298.7-143298.20" + process $proc$issuer_ls180.v:143298$7502 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "issuer_ls180.v:143612.3-143623.6" + process $proc$issuer_ls180.v:143612$7492 + assign { } { } + assign $0\so[0:0] $1\so[0:0] + attribute \src "issuer_ls180.v:143613.5-143613.29" + switch \initial + attribute \src "issuer_ls180.v:143613.9-143613.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:30" + switch \oe + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\so[0:0] \xer_so$18 + attribute \src "issuer_ls180.v:0.0-0.0" + case + assign { } { } + assign $1\so[0:0] \xer_so + end + sync always + update \so $0\so[0:0] + end + attribute \src "issuer_ls180.v:143624.3-143635.6" + process $proc$issuer_ls180.v:143624$7493 + assign { } { } + assign $0\cr0[3:0] $1\cr0[3:0] + attribute \src "issuer_ls180.v:143625.5-143625.29" + switch \initial + attribute \src "issuer_ls180.v:143625.9-143625.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:85" + switch \$34 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\cr0[3:0] \cr_a + attribute \src "issuer_ls180.v:0.0-0.0" + case + assign { } { } + assign $1\cr0[3:0] { \is_negative \is_positive \$36 \so } + end + sync always + update \cr0 $0\cr0[3:0] + end + attribute \src "issuer_ls180.v:143636.3-143645.6" + process $proc$issuer_ls180.v:143636$7494 + assign { } { } + assign { } { } + assign $0\xer_so$18[0:0]$7495 $1\xer_so$18[0:0]$7496 + attribute \src "issuer_ls180.v:143637.5-143637.29" + switch \initial + attribute \src "issuer_ls180.v:143637.9-143637.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:31" + switch \oe$38 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\xer_so$18[0:0]$7496 \$41 + case + assign $1\xer_so$18[0:0]$7496 1'0 + end + sync always + update \xer_so$18 $0\xer_so$18[0:0]$7495 + end + attribute \src "issuer_ls180.v:143646.3-143655.6" + process $proc$issuer_ls180.v:143646$7497 + assign { } { } + assign { } { } + assign $0\xer_so_ok[0:0] $1\xer_so_ok[0:0] + attribute \src "issuer_ls180.v:143647.5-143647.29" + switch \initial + attribute \src "issuer_ls180.v:143647.9-143647.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:31" + switch \oe$38 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\xer_so_ok[0:0] 1'1 + case + assign $1\xer_so_ok[0:0] 1'0 + end + sync always + update \xer_so_ok $0\xer_so_ok[0:0] + end + attribute \src "issuer_ls180.v:143656.3-143665.6" + process $proc$issuer_ls180.v:143656$7498 + assign { } { } + assign { } { } + assign $0\xer_ov$17[1:0]$7499 $1\xer_ov$17[1:0]$7500 + attribute \src "issuer_ls180.v:143657.5-143657.29" + switch \initial + attribute \src "issuer_ls180.v:143657.9-143657.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:31" + switch \oe$38 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\xer_ov$17[1:0]$7500 \xer_ov + case + assign $1\xer_ov$17[1:0]$7500 2'00 + end + sync always + update \xer_ov$17 $0\xer_ov$17[1:0]$7499 + end + attribute \src "issuer_ls180.v:143666.3-143675.6" + process $proc$issuer_ls180.v:143666$7501 + assign { } { } + assign { } { } + assign $0\xer_ov_ok[0:0] $1\xer_ov_ok[0:0] + attribute \src "issuer_ls180.v:143667.5-143667.29" + switch \initial + attribute \src "issuer_ls180.v:143667.9-143667.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:31" + switch \oe$38 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\xer_ov_ok[0:0] 1'1 + case + assign $1\xer_ov_ok[0:0] 1'0 + end + sync always + update \xer_ov_ok $0\xer_ov_ok[0:0] + end + connect \$19 $and$issuer_ls180.v:143601$7480_Y + connect \$22 $pos$issuer_ls180.v:143602$7482_Y + connect \$24 $eq$issuer_ls180.v:143603$7483_Y + connect \$26 $eq$issuer_ls180.v:143604$7484_Y + connect \$28 $reduce_or$issuer_ls180.v:143605$7485_Y + connect \$30 $not$issuer_ls180.v:143606$7486_Y + connect \$32 $and$issuer_ls180.v:143607$7487_Y + connect \$34 $or$issuer_ls180.v:143608$7488_Y + connect \$36 $not$issuer_ls180.v:143609$7489_Y + connect \$39 $and$issuer_ls180.v:143610$7490_Y + connect \$41 $or$issuer_ls180.v:143611$7491_Y + connect \oe$38 \$39 + connect { \mul_op__insn$13 \mul_op__is_signed$12 \mul_op__is_32bit$11 \mul_op__write_cr0$10 \mul_op__oe__ok$9 \mul_op__oe__oe$8 \mul_op__rc__ok$7 \mul_op__rc__rc$6 \mul_op__imm_data__ok$5 \mul_op__imm_data__data$4 \mul_op__fn_unit$3 \mul_op__insn_type$2 } { \mul_op__insn \mul_op__is_signed \mul_op__is_32bit \mul_op__write_cr0 \mul_op__oe__ok \mul_op__oe__oe \mul_op__rc__ok \mul_op__rc__rc \mul_op__imm_data__ok \mul_op__imm_data__data \mul_op__fn_unit \mul_op__insn_type } + connect \muxid$1 \muxid + connect \cr_a_ok \mul_op__write_cr0 + connect \cr_a$16 \cr0 + connect \o_ok$15 \o_ok + connect \o$14 \o$21 [63:0] + connect \is_positive \$32 + connect \is_negative \msb_test + connect \is_nzero \$28 + connect \msb_test \target [63] + connect \is_cmpeqb \$26 + connect \is_cmp \$24 + connect \target \o$21 [63:0] + connect \o$21 \$22 + connect \oe \$19 +end +attribute \src "issuer_ls180.v:143696.1-144166.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_end.output_stage" +attribute \generator "nMigen" +module \output_stage + attribute \src "issuer_ls180.v:143697.7-143697.20" + wire $0\initial[0:0] + attribute \src "issuer_ls180.v:144083.3-144154.6" + wire width 64 $0\o[63:0] + attribute \src "issuer_ls180.v:144049.3-144082.6" + wire $0\ov[0:0] + attribute \src "issuer_ls180.v:144083.3-144154.6" + wire width 64 $1\o[63:0] + attribute \src "issuer_ls180.v:144049.3-144082.6" + wire $1\ov[0:0] + attribute \src "issuer_ls180.v:144083.3-144154.6" + wire width 64 $2\o[63:0] + attribute \src "issuer_ls180.v:144049.3-144082.6" + wire $2\ov[0:0] + attribute \src "issuer_ls180.v:144083.3-144154.6" + wire width 64 $3\o[63:0] + attribute \src "issuer_ls180.v:144049.3-144082.6" + wire $3\ov[0:0] + attribute \src "issuer_ls180.v:144083.3-144154.6" + wire width 64 $4\o[63:0] + attribute \src "issuer_ls180.v:144083.3-144154.6" + wire width 64 $5\o[63:0] + attribute \src "issuer_ls180.v:144083.3-144154.6" + wire width 64 $6\o[63:0] + attribute \src "issuer_ls180.v:144083.3-144154.6" + wire width 64 $7\o[63:0] + attribute \src "issuer_ls180.v:144083.3-144154.6" + wire width 64 $8\o[63:0] + attribute \src "issuer_ls180.v:144040.18-144040.122" + wire $and$issuer_ls180.v:144040$7516_Y + attribute \src "issuer_ls180.v:144032.18-144032.109" + wire width 65 $extend$issuer_ls180.v:144032$7504_Y + attribute \src "issuer_ls180.v:144033.18-144033.100" + wire width 65 $extend$issuer_ls180.v:144033$7506_Y + attribute \src "issuer_ls180.v:144035.18-144035.113" + wire width 65 $extend$issuer_ls180.v:144035$7509_Y + attribute \src "issuer_ls180.v:144036.18-144036.104" + wire width 65 $extend$issuer_ls180.v:144036$7511_Y + attribute \src "issuer_ls180.v:144043.18-144043.114" + wire width 64 $extend$issuer_ls180.v:144043$7519_Y + attribute \src "issuer_ls180.v:144044.18-144044.114" + wire width 64 $extend$issuer_ls180.v:144044$7521_Y + attribute \src "issuer_ls180.v:144045.18-144045.114" + wire width 64 $extend$issuer_ls180.v:144045$7523_Y + attribute \src "issuer_ls180.v:144046.18-144046.114" + wire width 64 $extend$issuer_ls180.v:144046$7525_Y + attribute \src "issuer_ls180.v:144048.18-144048.115" + wire width 64 $extend$issuer_ls180.v:144048$7528_Y + attribute \src "issuer_ls180.v:144041.18-144041.128" + wire $ne$issuer_ls180.v:144041$7517_Y + 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\enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 input 2 \logical_op__fn_unit + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 output 29 \logical_op__fn_unit$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 input 3 \logical_op__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 output 30 \logical_op__imm_data__data$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 4 \logical_op__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 31 \logical_op__imm_data__ok$5 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 input 11 \logical_op__input_carry + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 output 38 \logical_op__input_carry$12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 18 \logical_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 output 45 \logical_op__insn$19 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 input 1 \logical_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 output 28 \logical_op__insn_type$2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 9 \logical_op__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 36 \logical_op__invert_in$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 12 \logical_op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 39 \logical_op__invert_out$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 15 \logical_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 42 \logical_op__is_32bit$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 16 \logical_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 43 \logical_op__is_signed$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 7 \logical_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 34 \logical_op__oe__oe$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 8 \logical_op__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 35 \logical_op__oe__ok$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 14 \logical_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 41 \logical_op__output_carry$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 6 \logical_op__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 33 \logical_op__rc__ok$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 5 \logical_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 32 \logical_op__rc__rc$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 13 \logical_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 40 \logical_op__write_cr0$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 10 \logical_op__zero_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 37 \logical_op__zero_a$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 input 51 \muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 output 27 \muxid$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 output 46 \o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 47 \o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:75" + wire \ov + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:26" + wire width 65 \quotient_65 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:24" + wire \quotient_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:40" + wire width 64 input 25 \quotient_root + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:41" + wire width 192 input 26 \remainder + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:27" + wire width 64 \remainder_64 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:25" + wire \remainder_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 2 output 48 \xer_ov + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 49 \xer_ov_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire input 19 \xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 50 \xer_so$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:80" + cell $and $and$issuer_ls180.v:144040$7516 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \logical_op__is_signed + connect \B \$38 + connect \Y $and$issuer_ls180.v:144040$7516_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:65" + cell $pos $extend$issuer_ls180.v:144032$7504 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 65 + connect \A \quotient_root + connect \Y $extend$issuer_ls180.v:144032$7504_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:40" + cell $pos $extend$issuer_ls180.v:144033$7506 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 65 + connect \A \quotient_root + connect \Y $extend$issuer_ls180.v:144033$7506_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:67" + cell $pos $extend$issuer_ls180.v:144035$7509 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 65 + connect \A \remainder [127:64] + connect \Y $extend$issuer_ls180.v:144035$7509_Y + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:265" + cell $pos $extend$issuer_ls180.v:144036$7511 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 65 + connect \A \remainder [127:64] + connect \Y $extend$issuer_ls180.v:144036$7511_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:102" + cell $pos $extend$issuer_ls180.v:144043$7519 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \Y_WIDTH 64 + connect \A \quotient_65 [31:0] + connect \Y $extend$issuer_ls180.v:144043$7519_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:104" + cell $pos $extend$issuer_ls180.v:144044$7521 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \Y_WIDTH 64 + connect \A \quotient_65 [31:0] + connect \Y $extend$issuer_ls180.v:144044$7521_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:111" + cell $pos $extend$issuer_ls180.v:144045$7523 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \Y_WIDTH 64 + connect \A \quotient_65 [31:0] + connect \Y $extend$issuer_ls180.v:144045$7523_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:113" + cell $pos $extend$issuer_ls180.v:144046$7525 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \Y_WIDTH 64 + connect \A \quotient_65 [31:0] + connect \Y $extend$issuer_ls180.v:144046$7525_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:122" + cell $pos $extend$issuer_ls180.v:144048$7528 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \Y_WIDTH 64 + connect \A \remainder_64 [31:0] + connect \Y $extend$issuer_ls180.v:144048$7528_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:84" + cell $ne $ne$issuer_ls180.v:144041$7517 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \quotient_65 [32] + connect \B \quotient_65 [31] + connect \Y $ne$issuer_ls180.v:144041$7517_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:65" + cell $neg $neg$issuer_ls180.v:144032$7505 + parameter \A_SIGNED 0 + parameter \A_WIDTH 65 + parameter \Y_WIDTH 65 + connect \A $extend$issuer_ls180.v:144032$7504_Y + connect \Y $neg$issuer_ls180.v:144032$7505_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:67" + cell $neg $neg$issuer_ls180.v:144035$7510 + parameter \A_SIGNED 0 + parameter \A_WIDTH 65 + parameter \Y_WIDTH 65 + connect \A $extend$issuer_ls180.v:144035$7509_Y + connect \Y $neg$issuer_ls180.v:144035$7510_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:78" + cell $not $not$issuer_ls180.v:144038$7514 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \logical_op__is_32bit + connect \Y $not$issuer_ls180.v:144038$7514_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:96" + cell $not $not$issuer_ls180.v:144042$7518 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \ov + connect \Y $not$issuer_ls180.v:144042$7518_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:40" + cell $pos $pos$issuer_ls180.v:144033$7507 + parameter \A_SIGNED 0 + parameter \A_WIDTH 65 + parameter \Y_WIDTH 65 + connect \A $extend$issuer_ls180.v:144033$7506_Y + connect \Y $pos$issuer_ls180.v:144033$7507_Y + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:265" + cell $pos $pos$issuer_ls180.v:144036$7512 + parameter \A_SIGNED 0 + parameter \A_WIDTH 65 + parameter \Y_WIDTH 65 + connect \A $extend$issuer_ls180.v:144036$7511_Y + connect \Y $pos$issuer_ls180.v:144036$7512_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:102" + cell $pos $pos$issuer_ls180.v:144043$7520 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A $extend$issuer_ls180.v:144043$7519_Y + connect \Y $pos$issuer_ls180.v:144043$7520_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:104" + cell $pos $pos$issuer_ls180.v:144044$7522 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A $extend$issuer_ls180.v:144044$7521_Y + connect \Y $pos$issuer_ls180.v:144044$7522_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:111" + cell $pos $pos$issuer_ls180.v:144045$7524 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A $extend$issuer_ls180.v:144045$7523_Y + connect \Y $pos$issuer_ls180.v:144045$7524_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:113" + cell $pos $pos$issuer_ls180.v:144046$7526 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A $extend$issuer_ls180.v:144046$7525_Y + connect \Y $pos$issuer_ls180.v:144046$7526_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:120" + cell $pos $pos$issuer_ls180.v:144047$7527 + parameter \A_SIGNED 1 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A { \remainder_64 [31] \remainder_64 [31] \remainder_64 [31] \remainder_64 [31] \remainder_64 [31] \remainder_64 [31] \remainder_64 [31] \remainder_64 [31] \remainder_64 [31] \remainder_64 [31] \remainder_64 [31] \remainder_64 [31] \remainder_64 [31] \remainder_64 [31] \remainder_64 [31] \remainder_64 [31] \remainder_64 [31] \remainder_64 [31] \remainder_64 [31] \remainder_64 [31] \remainder_64 [31] \remainder_64 [31] \remainder_64 [31] \remainder_64 [31] \remainder_64 [31] \remainder_64 [31] \remainder_64 [31] \remainder_64 [31] \remainder_64 [31] \remainder_64 [31] \remainder_64 [31] \remainder_64 [31] \remainder_64 [31:0] } + connect \Y $pos$issuer_ls180.v:144047$7527_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:122" + cell $pos $pos$issuer_ls180.v:144048$7529 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A $extend$issuer_ls180.v:144048$7528_Y + connect \Y $pos$issuer_ls180.v:144048$7529_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:65" + cell $mux $ternary$issuer_ls180.v:144034$7508 + parameter \WIDTH 65 + connect \A \$25 + connect \B \$23 + connect \S \quotient_neg + connect \Y $ternary$issuer_ls180.v:144034$7508_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:67" + cell $mux $ternary$issuer_ls180.v:144037$7513 + parameter \WIDTH 65 + connect \A \$32 + connect \B \$30 + connect \S \remainder_neg + connect \Y $ternary$issuer_ls180.v:144037$7513_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:55" + cell $xor $xor$issuer_ls180.v:144031$7503 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dividend_neg + connect \B \divisor_neg + connect \Y $xor$issuer_ls180.v:144031$7503_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:80" + cell $xor $xor$issuer_ls180.v:144039$7515 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \quotient_65 [64] + connect \B \quotient_65 [63] + connect \Y $xor$issuer_ls180.v:144039$7515_Y + end + attribute \src "issuer_ls180.v:143697.7-143697.20" + process $proc$issuer_ls180.v:143697$7532 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "issuer_ls180.v:144049.3-144082.6" + process $proc$issuer_ls180.v:144049$7530 + assign { } { } + assign $0\ov[0:0] $1\ov[0:0] + attribute \src "issuer_ls180.v:144050.5-144050.29" + switch \initial + attribute \src "issuer_ls180.v:144050.9-144050.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:76" + switch { \logical_op__is_signed \$36 \div_by_zero } + attribute \src "issuer_ls180.v:0.0-0.0" + case 3'--1 + assign { } { } + assign $1\ov[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 3'-1- + assign { } { } + assign { } { } + assign $1\ov[0:0] $2\ov[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:80" + switch \$40 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\ov[0:0] 1'1 + case + assign $2\ov[0:0] \dive_abs_ov64 + end + attribute \src "issuer_ls180.v:0.0-0.0" + case 3'1-- + assign { } { } + assign { } { } + assign $1\ov[0:0] $3\ov[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:84" + switch \$42 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\ov[0:0] 1'1 + case + assign $3\ov[0:0] \dive_abs_ov32 + end + attribute \src "issuer_ls180.v:0.0-0.0" + case + assign { } { } + assign $1\ov[0:0] \dive_abs_ov32 + end + sync always + update \ov $0\ov[0:0] + end + attribute \src "issuer_ls180.v:144083.3-144154.6" + process $proc$issuer_ls180.v:144083$7531 + assign { } { } + assign { } { } + assign $0\o[63:0] $1\o[63:0] + attribute \src "issuer_ls180.v:144084.5-144084.29" + switch \initial + attribute \src "issuer_ls180.v:144084.9-144084.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:96" + switch \$44 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\o[63:0] $2\o[63:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:97" + switch \logical_op__insn_type + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'0011110 + assign { } { } + assign $2\o[63:0] $3\o[63:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:99" + switch \logical_op__is_32bit + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\o[63:0] $4\o[63:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:100" + switch \logical_op__is_signed + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\o[63:0] \$46 + attribute \src "issuer_ls180.v:0.0-0.0" + case + assign { } { } + assign $4\o[63:0] \$48 + end + attribute \src "issuer_ls180.v:0.0-0.0" + case + assign { } { } + assign $3\o[63:0] \quotient_65 [63:0] + end + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'0011101 + assign { } { } + assign $2\o[63:0] $5\o[63:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:108" + switch \logical_op__is_32bit + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\o[63:0] $6\o[63:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:109" + switch \logical_op__is_signed + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $6\o[63:0] \$50 + attribute \src "issuer_ls180.v:0.0-0.0" + case + assign { } { } + assign $6\o[63:0] \$52 + end + attribute \src "issuer_ls180.v:0.0-0.0" + case + assign { } { } + assign $5\o[63:0] \quotient_65 [63:0] + end + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'0101111 + assign { } { } + assign $2\o[63:0] $7\o[63:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:117" + switch \logical_op__is_32bit + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $7\o[63:0] $8\o[63:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:118" + switch \logical_op__is_signed + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $8\o[63:0] \$54 + attribute \src "issuer_ls180.v:0.0-0.0" + case + assign { } { } + assign $8\o[63:0] \$56 + end + attribute \src "issuer_ls180.v:0.0-0.0" + case + assign { } { } + assign $7\o[63:0] \remainder_64 + end + case + assign $2\o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + case + assign $1\o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \o $0\o[63:0] + end + connect \$21 $xor$issuer_ls180.v:144031$7503_Y + connect \$23 $neg$issuer_ls180.v:144032$7505_Y + connect \$25 $pos$issuer_ls180.v:144033$7507_Y + connect \$27 $ternary$issuer_ls180.v:144034$7508_Y + connect \$30 $neg$issuer_ls180.v:144035$7510_Y + connect \$32 $pos$issuer_ls180.v:144036$7512_Y + connect \$34 $ternary$issuer_ls180.v:144037$7513_Y + connect \$36 $not$issuer_ls180.v:144038$7514_Y + connect \$38 $xor$issuer_ls180.v:144039$7515_Y + connect \$40 $and$issuer_ls180.v:144040$7516_Y + connect \$42 $ne$issuer_ls180.v:144041$7517_Y + connect \$44 $not$issuer_ls180.v:144042$7518_Y + connect \$46 $pos$issuer_ls180.v:144043$7520_Y + connect \$48 $pos$issuer_ls180.v:144044$7522_Y + connect \$50 $pos$issuer_ls180.v:144045$7524_Y + connect \$52 $pos$issuer_ls180.v:144046$7526_Y + connect \$54 $pos$issuer_ls180.v:144047$7527_Y + connect \$56 $pos$issuer_ls180.v:144048$7529_Y + connect \$29 \$34 + connect { \logical_op__insn$19 \logical_op__data_len$18 \logical_op__is_signed$17 \logical_op__is_32bit$16 \logical_op__output_carry$15 \logical_op__write_cr0$14 \logical_op__invert_out$13 \logical_op__input_carry$12 \logical_op__zero_a$11 \logical_op__invert_in$10 \logical_op__oe__ok$9 \logical_op__oe__oe$8 \logical_op__rc__ok$7 \logical_op__rc__rc$6 \logical_op__imm_data__ok$5 \logical_op__imm_data__data$4 \logical_op__fn_unit$3 \logical_op__insn_type$2 } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in \logical_op__oe__ok \logical_op__oe__oe \logical_op__rc__ok \logical_op__rc__rc \logical_op__imm_data__ok \logical_op__imm_data__data \logical_op__fn_unit \logical_op__insn_type } + connect \muxid$1 \muxid + connect \xer_so$20 \xer_so + connect \o_ok 1'1 + connect \xer_ov { \ov \ov } + connect \xer_ov_ok 1'1 + connect \remainder_64 \$34 [63:0] + connect \quotient_65 \$27 + connect \remainder_neg \dividend_neg + connect \quotient_neg \$21 +end +attribute \src "issuer_ls180.v:144170.1-144181.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.fus.alu0.alu_alu0.p" +attribute \generator "nMigen" +module \p + attribute \src "issuer_ls180.v:144179.17-144179.111" + wire $and$issuer_ls180.v:144179$7533_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" + wire input 1 \p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" + wire input 2 \p_valid_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:158" + wire \trigger + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" + cell $and $and$issuer_ls180.v:144179$7533 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \p_valid_i + connect \B \p_ready_o + connect \Y $and$issuer_ls180.v:144179$7533_Y + end + connect \$1 $and$issuer_ls180.v:144179$7533_Y + connect \trigger \$1 +end +attribute \src "issuer_ls180.v:144185.1-144196.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.fus.alu0.alu_alu0.pipe1.p" +attribute \generator "nMigen" +module \p$1 + attribute \src "issuer_ls180.v:144194.17-144194.111" + wire $and$issuer_ls180.v:144194$7534_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" + wire input 1 \p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" + wire input 2 \p_valid_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:158" + wire \trigger + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" + cell $and $and$issuer_ls180.v:144194$7534 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \p_valid_i + connect \B \p_ready_o + connect \Y $and$issuer_ls180.v:144194$7534_Y + end + connect \$1 $and$issuer_ls180.v:144194$7534_Y + connect \trigger \$1 +end +attribute \src "issuer_ls180.v:144200.1-144211.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.fus.shiftrot0.alu_shift_rot0.p" +attribute \generator "nMigen" +module \p$105 + attribute \src "issuer_ls180.v:144209.17-144209.111" + wire $and$issuer_ls180.v:144209$7535_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" + wire input 1 \p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" + wire input 2 \p_valid_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:158" + wire \trigger + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" + cell $and $and$issuer_ls180.v:144209$7535 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \p_valid_i + connect \B \p_ready_o + connect \Y $and$issuer_ls180.v:144209$7535_Y + end + connect \$1 $and$issuer_ls180.v:144209$7535_Y + connect \trigger \$1 +end +attribute \src "issuer_ls180.v:144215.1-144226.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.fus.shiftrot0.alu_shift_rot0.pipe1.p" +attribute \generator "nMigen" +module \p$108 + attribute \src "issuer_ls180.v:144224.17-144224.111" + wire $and$issuer_ls180.v:144224$7536_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" + wire input 1 \p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" + wire input 2 \p_valid_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:158" + wire \trigger + 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attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" + wire input 2 \p_valid_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:158" + wire \trigger + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" + cell $and $and$issuer_ls180.v:144494$7554 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \p_valid_i + connect \B \p_ready_o + connect \Y $and$issuer_ls180.v:144494$7554_Y + end + connect \$1 $and$issuer_ls180.v:144494$7554_Y + connect \trigger \$1 +end +attribute \src "issuer_ls180.v:144500.1-144511.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.fus.mul0.alu_mul0.mul_pipe1.p" +attribute \generator "nMigen" +module \p$90 + attribute \src "issuer_ls180.v:144509.17-144509.111" + wire $and$issuer_ls180.v:144509$7555_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" + wire input 1 \p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" + wire input 2 \p_valid_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:158" + wire \trigger + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" + cell $and $and$issuer_ls180.v:144509$7555 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \p_valid_i + connect \B \p_ready_o + connect \Y $and$issuer_ls180.v:144509$7555_Y + end + connect \$1 $and$issuer_ls180.v:144509$7555_Y + connect \trigger \$1 +end +attribute \src "issuer_ls180.v:144515.1-144526.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.fus.mul0.alu_mul0.mul_pipe2.p" +attribute \generator "nMigen" +module \p$93 + attribute \src "issuer_ls180.v:144524.17-144524.111" + wire $and$issuer_ls180.v:144524$7556_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" + wire input 1 \p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" + wire input 2 \p_valid_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:158" + wire \trigger + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" + cell $and $and$issuer_ls180.v:144524$7556 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \p_valid_i + connect \B \p_ready_o + connect \Y $and$issuer_ls180.v:144524$7556_Y + end + connect \$1 $and$issuer_ls180.v:144524$7556_Y + connect \trigger \$1 +end +attribute \src "issuer_ls180.v:144530.1-144541.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy 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"/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:84" + cell $eq $eq$issuer_ls180.v:144556$7558 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \i + connect \B 1'0 + connect \Y $eq$issuer_ls180.v:144556$7558_Y + end + attribute \src "issuer_ls180.v:144546.7-144546.20" + process $proc$issuer_ls180.v:144546$7560 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "issuer_ls180.v:144557.3-144566.6" + process $proc$issuer_ls180.v:144557$7559 + assign { } { } + assign { } { } + assign $0\o[0:0] $1\o[0:0] + attribute \src "issuer_ls180.v:144558.5-144558.29" + switch \initial + attribute \src "issuer_ls180.v:144558.9-144558.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" + switch \i + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\o[0:0] 1'0 + case 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attribute \src "issuer_ls180.v:145014.3-145039.6" + wire $0\valid_l_s_valid[0:0] + attribute \src "issuer_ls180.v:145066.3-145091.6" + wire width 48 $0\x_addr_i[47:0] + attribute \src "issuer_ls180.v:145040.3-145065.6" + wire width 8 $0\x_mask_i[7:0] + attribute \src "issuer_ls180.v:145189.3-145198.6" + wire width 64 $0\x_st_data_i[63:0] + attribute \src "issuer_ls180.v:145349.3-145364.6" + wire $1\adrok_l_r_addr_acked[0:0] + attribute \src "issuer_ls180.v:145313.3-145348.6" + wire $1\adrok_l_s_addr_acked$next[0:0]$7651 + attribute \src "issuer_ls180.v:144667.7-144667.34" + wire $1\adrok_l_s_addr_acked[0:0] + attribute \src "issuer_ls180.v:144963.3-144971.6" + wire $1\busy_delay$next[0:0]$7619 + attribute \src "issuer_ls180.v:144671.7-144671.24" + wire $1\busy_delay[0:0] + attribute \src "issuer_ls180.v:145297.3-145312.6" + wire $1\busy_l_r_busy[0:0] + attribute \src "issuer_ls180.v:145287.3-145296.6" + wire $1\busy_l_s_busy[0:0] + attribute \src "issuer_ls180.v:145277.3-145286.6" + wire $1\cyc_l_r_cyc[0:0] + attribute \src "issuer_ls180.v:145258.3-145267.6" + wire $1\cyc_l_s_cyc[0:0] + attribute \src "issuer_ls180.v:145219.3-145257.6" + wire width 2 $1\fsm_state$next[1:0]$7637 + attribute \src "issuer_ls180.v:144693.13-144693.29" + wire width 2 $1\fsm_state[1:0] + attribute \src "issuer_ls180.v:145159.3-145168.6" + wire $1\ld_active_r_ld_active[0:0] + attribute \src "issuer_ls180.v:144707.7-144707.21" + wire $1\lds_dly[0:0] + attribute \src "issuer_ls180.v:145092.3-145122.6" + wire $1\ldst_port0_addr_ok_o[0:0] + attribute \src "issuer_ls180.v:145149.3-145158.6" + wire width 64 $1\ldst_port0_ld_data_o[63:0] + attribute \src "issuer_ls180.v:145169.3-145178.6" + wire $1\ldst_port0_ld_data_o_ok[0:0] + attribute \src "issuer_ls180.v:144998.3-145013.6" + wire width 4 $1\lenexp_addr_i[3:0] + attribute \src "issuer_ls180.v:144982.3-144997.6" + wire width 4 $1\lenexp_len_i[3:0] + attribute \src "issuer_ls180.v:145268.3-145276.6" + wire $1\lsui_active_dly$next[0:0]$7645 + attribute \src "issuer_ls180.v:144750.7-144750.29" + wire $1\lsui_active_dly[0:0] + attribute \src "issuer_ls180.v:145199.3-145218.6" + wire $1\lsui_busy[0:0] + attribute \src "issuer_ls180.v:144762.7-144762.25" + wire $1\reset_delay[0:0] + attribute \src "issuer_ls180.v:145139.3-145148.6" + wire $1\reset_l_r_reset[0:0] + attribute \src "issuer_ls180.v:145123.3-145138.6" + wire $1\reset_l_s_reset[0:0] + attribute \src "issuer_ls180.v:144972.3-144981.6" + wire $1\st_active_r_st_active[0:0] + attribute \src "issuer_ls180.v:144953.3-144962.6" + wire $1\st_done_r_st_done[0:0] + attribute \src "issuer_ls180.v:144938.3-144952.6" + wire $1\st_done_s_st_done$next[0:0]$7614 + attribute \src "issuer_ls180.v:144782.7-144782.31" + wire $1\st_done_s_st_done[0:0] + attribute \src "issuer_ls180.v:145179.3-145188.6" + wire width 64 $1\stdata[63:0] + attribute \src "issuer_ls180.v:144790.7-144790.21" + wire $1\sts_dly[0:0] + attribute \src "issuer_ls180.v:145014.3-145039.6" + wire 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"/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" + wire \sts_dly + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" + wire \sts_dly$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" + wire \sts_rise + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire \valid_l_q_valid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire \valid_l_r_valid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire \valid_l_s_valid + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:43" + wire width 48 output 9 \x_addr_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:59" + wire input 17 \x_busy_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:45" + wire output 19 \x_ld_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:44" + wire width 8 output 8 \x_mask_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:47" + wire width 64 output 16 \x_st_data_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:46" + wire output 20 \x_st_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:50" + wire output 22 \x_valid_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:205" + cell $and $and$issuer_ls180.v:144819$7562 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \ldst_port0_busy_o + connect \B \$9 + connect \Y $and$issuer_ls180.v:144819$7562_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + cell $and $and$issuer_ls180.v:144821$7564 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \lds + connect \B \$13 + connect \Y $and$issuer_ls180.v:144821$7564_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:256" + cell $and $and$issuer_ls180.v:144823$7566 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \st_active_q_st_active + connect \B \ldst_port0_st_data_i_ok + connect \Y $and$issuer_ls180.v:144823$7566_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + cell $and $and$issuer_ls180.v:144824$7567 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \sts + connect \B \$17 + connect \Y $and$issuer_ls180.v:144824$7567_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:222" + cell $and $and$issuer_ls180.v:144827$7572 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \ldst_port0_addr_i_ok + connect \B \adrok_l_qn_addr_acked + connect \Y $and$issuer_ls180.v:144827$7572_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:222" + cell $and $and$issuer_ls180.v:144828$7573 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \ldst_port0_addr_i_ok + connect \B \adrok_l_qn_addr_acked + connect \Y $and$issuer_ls180.v:144828$7573_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:222" + cell $and $and$issuer_ls180.v:144829$7574 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \ldst_port0_addr_i_ok + connect \B \adrok_l_qn_addr_acked + connect \Y $and$issuer_ls180.v:144829$7574_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:222" + cell $and $and$issuer_ls180.v:144830$7575 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \ldst_port0_addr_i_ok + connect \B \adrok_l_qn_addr_acked + connect \Y $and$issuer_ls180.v:144830$7575_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:248" + cell $and $and$issuer_ls180.v:144831$7576 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \ld_active_q_ld_active + connect \B \adrok_l_q_addr_acked + connect \Y $and$issuer_ls180.v:144831$7576_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:246" + cell $and $and$issuer_ls180.v:144836$7581 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 176 + parameter \Y_WIDTH 176 + connect \A \m_ld_data_o + connect \B \lenexp_rexp_o + connect \Y $and$issuer_ls180.v:144836$7581_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:248" + cell $and $and$issuer_ls180.v:144839$7584 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \ld_active_q_ld_active + connect \B \adrok_l_q_addr_acked + connect \Y $and$issuer_ls180.v:144839$7584_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:248" + cell $and $and$issuer_ls180.v:144840$7585 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \ld_active_q_ld_active + connect \B \adrok_l_q_addr_acked + connect \Y $and$issuer_ls180.v:144840$7585_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:256" + cell $and $and$issuer_ls180.v:144842$7587 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \st_active_q_st_active + connect \B \ldst_port0_st_data_i_ok + connect \Y $and$issuer_ls180.v:144842$7587_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:256" + cell $and $and$issuer_ls180.v:144846$7591 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \st_active_q_st_active + connect \B \ldst_port0_st_data_i_ok + connect \Y $and$issuer_ls180.v:144846$7591_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:88" + cell $and $and$issuer_ls180.v:144848$7593 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$63 + connect \B \valid_l_q_valid + connect \Y $and$issuer_ls180.v:144848$7593_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:88" + cell $and $and$issuer_ls180.v:144850$7595 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$67 + connect \B \valid_l_q_valid + connect \Y $and$issuer_ls180.v:144850$7595_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:99" + cell $and $and$issuer_ls180.v:144854$7599 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$73 + connect \B \$75 + connect \Y $and$issuer_ls180.v:144854$7599_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:222" + cell $and $and$issuer_ls180.v:144855$7600 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \ldst_port0_addr_i_ok + connect \B \adrok_l_qn_addr_acked + connect \Y $and$issuer_ls180.v:144855$7600_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + cell $and $and$issuer_ls180.v:144858$7603 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \lsui_active + connect \B \$81 + connect \Y $and$issuer_ls180.v:144858$7603_Y + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:265" + cell $pos $extend$issuer_ls180.v:144825$7568 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 4 + connect \A \ldst_port0_addr_i [2:0] + connect \Y $extend$issuer_ls180.v:144825$7568_Y + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:265" + cell $pos $extend$issuer_ls180.v:144826$7570 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 4 + connect \A \ldst_port0_addr_i [2:0] + connect \Y $extend$issuer_ls180.v:144826$7570_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:247" + cell $mul $mul$issuer_ls180.v:144837$7582 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 8 + connect \A \lenexp_addr_i + connect \B 4'1000 + connect \Y $mul$issuer_ls180.v:144837$7582_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:260" + cell $mul $mul$issuer_ls180.v:144843$7588 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 8 + connect \A \lenexp_addr_i + connect \B 4'1000 + connect \Y $mul$issuer_ls180.v:144843$7588_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:205" + cell $not $not$issuer_ls180.v:144818$7561 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \busy_delay + connect \Y $not$issuer_ls180.v:144818$7561_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + cell $not $not$issuer_ls180.v:144820$7563 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \lds_dly + connect \Y $not$issuer_ls180.v:144820$7563_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + cell $not $not$issuer_ls180.v:144822$7565 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \sts_dly + connect \Y $not$issuer_ls180.v:144822$7565_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:64" + cell $not $not$issuer_ls180.v:144832$7577 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \lsui_busy + connect \Y $not$issuer_ls180.v:144832$7577_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:61" + cell $not $not$issuer_ls180.v:144835$7580 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$38 + connect \Y $not$issuer_ls180.v:144835$7580_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:64" + cell $not $not$issuer_ls180.v:144841$7586 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \lsui_busy + connect \Y $not$issuer_ls180.v:144841$7586_Y + end + attribute \src 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connect \A \ldst_port0_busy_o + connect \Y $not$issuer_ls180.v:144853$7598_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:108" + cell $not $not$issuer_ls180.v:144856$7601 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \x_busy_o + connect \Y $not$issuer_ls180.v:144856$7601_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + cell $not $not$issuer_ls180.v:144857$7602 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \lsui_active_dly + connect \Y $not$issuer_ls180.v:144857$7602_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:61" + cell $or $or$issuer_ls180.v:144833$7578 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \x_busy_o + connect \B \lsui_busy + connect \Y $or$issuer_ls180.v:144833$7578_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:212" + cell $or $or$issuer_ls180.v:144834$7579 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \ldst_port0_is_ld_i + connect \B \ldst_port0_is_st_i + connect \Y $or$issuer_ls180.v:144834$7579_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:88" + cell $or $or$issuer_ls180.v:144847$7592 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \ldst_port0_is_ld_i + connect \B \ldst_port0_is_st_i + connect \Y $or$issuer_ls180.v:144847$7592_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:88" + cell $or $or$issuer_ls180.v:144849$7594 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \ldst_port0_is_ld_i + connect \B \ldst_port0_is_st_i + connect \Y $or$issuer_ls180.v:144849$7594_Y + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:265" + cell $pos $pos$issuer_ls180.v:144825$7569 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A $extend$issuer_ls180.v:144825$7568_Y + connect \Y $pos$issuer_ls180.v:144825$7569_Y + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:265" + cell $pos $pos$issuer_ls180.v:144826$7571 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A $extend$issuer_ls180.v:144826$7570_Y + connect \Y $pos$issuer_ls180.v:144826$7571_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:260" + cell $sshl $sshl$issuer_ls180.v:144845$7590 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 319 + connect \A \ldst_port0_st_data_i + connect \B \$57 + connect \Y $sshl$issuer_ls180.v:144845$7590_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:247" + cell $sshr $sshr$issuer_ls180.v:144838$7583 + parameter \A_SIGNED 0 + parameter \A_WIDTH 176 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 176 + connect \A \$42 + connect \B \$44 + connect \Y $sshr$issuer_ls180.v:144838$7583_Y + end + attribute \module_not_derived 1 + attribute \src "issuer_ls180.v:144875.11-144882.4" + cell \adrok_l \adrok_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_addr_acked \adrok_l_q_addr_acked + connect \qn_addr_acked \adrok_l_qn_addr_acked + connect \r_addr_acked \adrok_l_r_addr_acked + connect \s_addr_acked \adrok_l_s_addr_acked + end + attribute \module_not_derived 1 + attribute \src "issuer_ls180.v:144883.10-144889.4" + cell \busy_l \busy_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_busy \busy_l_q_busy + connect \r_busy \busy_l_r_busy + connect \s_busy \busy_l_s_busy + end + attribute \module_not_derived 1 + attribute \src "issuer_ls180.v:144890.9-144896.4" + cell \cyc_l \cyc_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_cyc \cyc_l_q_cyc + connect \r_cyc \cyc_l_r_cyc + connect \s_cyc \cyc_l_s_cyc + end + attribute \module_not_derived 1 + attribute \src "issuer_ls180.v:144897.13-144903.4" + cell \ld_active \ld_active + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_ld_active \ld_active_q_ld_active + connect \r_ld_active \ld_active_r_ld_active + connect \s_ld_active \ld_active_s_ld_active + end + attribute \module_not_derived 1 + attribute \src "issuer_ls180.v:144904.10-144909.4" + cell \lenexp \lenexp + connect \addr_i \lenexp_addr_i + connect \len_i \lenexp_len_i + connect \lexp_o \lenexp_lexp_o + connect \rexp_o \lenexp_rexp_o + end + attribute \module_not_derived 1 + attribute \src "issuer_ls180.v:144910.11-144916.4" + cell \reset_l \reset_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_reset \reset_l_q_reset + connect \r_reset \reset_l_r_reset + connect \s_reset \reset_l_s_reset + end + attribute \module_not_derived 1 + attribute \src "issuer_ls180.v:144917.13-144923.4" + cell \st_active \st_active + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_st_active \st_active_q_st_active + connect \r_st_active \st_active_r_st_active + connect \s_st_active \st_active_s_st_active + end + attribute \module_not_derived 1 + attribute \src "issuer_ls180.v:144924.11-144930.4" + cell \st_done \st_done + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_st_done \st_done_q_st_done + connect \r_st_done \st_done_r_st_done + connect \s_st_done \st_done_s_st_done + end + attribute \module_not_derived 1 + attribute \src "issuer_ls180.v:144931.11-144937.4" + cell \valid_l \valid_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_valid \valid_l_q_valid + connect \r_valid \valid_l_r_valid + connect \s_valid \valid_l_s_valid + end + attribute \src "issuer_ls180.v:144573.7-144573.20" + process $proc$issuer_ls180.v:144573$7658 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "issuer_ls180.v:144667.7-144667.34" + process $proc$issuer_ls180.v:144667$7659 + assign { } { } + assign $1\adrok_l_s_addr_acked[0:0] 1'0 + sync always + sync init + update \adrok_l_s_addr_acked $1\adrok_l_s_addr_acked[0:0] + end + attribute \src "issuer_ls180.v:144671.7-144671.24" + process $proc$issuer_ls180.v:144671$7660 + assign { } { } + assign $1\busy_delay[0:0] 1'0 + sync always + sync init + update \busy_delay $1\busy_delay[0:0] + end + attribute \src "issuer_ls180.v:144693.13-144693.29" + process $proc$issuer_ls180.v:144693$7661 + assign { } { } + assign $1\fsm_state[1:0] 2'00 + sync always + sync init + update \fsm_state $1\fsm_state[1:0] + end + attribute \src "issuer_ls180.v:144707.7-144707.21" + process $proc$issuer_ls180.v:144707$7662 + assign { } { } + assign $1\lds_dly[0:0] 1'0 + sync always + sync init + update \lds_dly $1\lds_dly[0:0] + end + attribute \src "issuer_ls180.v:144750.7-144750.29" + process $proc$issuer_ls180.v:144750$7663 + assign { } { } + assign $1\lsui_active_dly[0:0] 1'0 + sync always + sync init + update \lsui_active_dly $1\lsui_active_dly[0:0] + end + attribute \src "issuer_ls180.v:144762.7-144762.25" + process $proc$issuer_ls180.v:144762$7664 + assign { } { } + assign $1\reset_delay[0:0] 1'0 + sync always + sync init + update \reset_delay $1\reset_delay[0:0] + end + attribute \src "issuer_ls180.v:144782.7-144782.31" + process $proc$issuer_ls180.v:144782$7665 + assign { } { } + assign $1\st_done_s_st_done[0:0] 1'0 + sync always + sync init + update \st_done_s_st_done $1\st_done_s_st_done[0:0] + end + attribute \src "issuer_ls180.v:144790.7-144790.21" + process $proc$issuer_ls180.v:144790$7666 + assign { } { } + assign $1\sts_dly[0:0] 1'0 + sync always + sync init + update \sts_dly $1\sts_dly[0:0] + end + attribute \src "issuer_ls180.v:144859.3-144860.47" + process $proc$issuer_ls180.v:144859$7604 + assign { } { } + assign $0\lsui_active_dly[0:0] \lsui_active_dly$next + sync posedge \coresync_clk + update \lsui_active_dly $0\lsui_active_dly[0:0] + end + attribute \src "issuer_ls180.v:144861.3-144862.35" + process $proc$issuer_ls180.v:144861$7605 + assign { } { } + assign $0\fsm_state[1:0] \fsm_state$next + sync posedge \coresync_clk + update \fsm_state $0\fsm_state[1:0] + end + attribute \src "issuer_ls180.v:144863.3-144864.36" + process $proc$issuer_ls180.v:144863$7606 + assign { } { } + assign $0\reset_delay[0:0] \reset_l_q_reset + sync posedge \coresync_clk + update \reset_delay $0\reset_delay[0:0] + end + attribute \src "issuer_ls180.v:144865.3-144866.35" + process $proc$issuer_ls180.v:144865$7607 + assign { } { } + assign $0\sts_dly[0:0] \ldst_port0_is_st_i + sync posedge \coresync_clk + update \sts_dly $0\sts_dly[0:0] + end + attribute \src "issuer_ls180.v:144867.3-144868.35" + process $proc$issuer_ls180.v:144867$7608 + assign { } { } + assign $0\lds_dly[0:0] \ldst_port0_is_ld_i + sync posedge \coresync_clk + update \lds_dly $0\lds_dly[0:0] + end + attribute \src "issuer_ls180.v:144869.3-144870.37" + process $proc$issuer_ls180.v:144869$7609 + assign { } { } + assign $0\busy_delay[0:0] \busy_delay$next + sync posedge \coresync_clk + update \busy_delay $0\busy_delay[0:0] + end + attribute \src "issuer_ls180.v:144871.3-144872.57" + process $proc$issuer_ls180.v:144871$7610 + assign { } { } + assign $0\adrok_l_s_addr_acked[0:0] \adrok_l_s_addr_acked$next + sync posedge \coresync_clk + update \adrok_l_s_addr_acked $0\adrok_l_s_addr_acked[0:0] + end + attribute \src "issuer_ls180.v:144873.3-144874.51" + process $proc$issuer_ls180.v:144873$7611 + assign { } { } + assign $0\st_done_s_st_done[0:0] \st_done_s_st_done$next + sync posedge \coresync_clk + update \st_done_s_st_done $0\st_done_s_st_done[0:0] + end + attribute \src "issuer_ls180.v:144938.3-144952.6" + process $proc$issuer_ls180.v:144938$7612 + assign { } { } + assign { } { } + assign { } { } + assign $0\st_done_s_st_done$next[0:0]$7613 $2\st_done_s_st_done$next[0:0]$7615 + attribute \src "issuer_ls180.v:144939.5-144939.29" + switch \initial + attribute \src "issuer_ls180.v:144939.9-144939.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:256" + switch \$1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\st_done_s_st_done$next[0:0]$7614 1'1 + case + assign $1\st_done_s_st_done$next[0:0]$7614 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\st_done_s_st_done$next[0:0]$7615 1'0 + case + assign $2\st_done_s_st_done$next[0:0]$7615 $1\st_done_s_st_done$next[0:0]$7614 + end + sync always + update \st_done_s_st_done$next $0\st_done_s_st_done$next[0:0]$7613 + end + attribute \src "issuer_ls180.v:144953.3-144962.6" + process $proc$issuer_ls180.v:144953$7616 + assign { } { } + assign { } { } + assign $0\st_done_r_st_done[0:0] $1\st_done_r_st_done[0:0] + attribute \src "issuer_ls180.v:144954.5-144954.29" + switch \initial + attribute \src "issuer_ls180.v:144954.9-144954.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:275" + switch \reset_l_q_reset + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\st_done_r_st_done[0:0] 1'1 + case + assign $1\st_done_r_st_done[0:0] 1'0 + end + sync always + update \st_done_r_st_done $0\st_done_r_st_done[0:0] + end + attribute \src "issuer_ls180.v:144963.3-144971.6" + process $proc$issuer_ls180.v:144963$7617 + assign { } { } + assign { } { } + assign $0\busy_delay$next[0:0]$7618 $1\busy_delay$next[0:0]$7619 + attribute \src "issuer_ls180.v:144964.5-144964.29" + switch \initial + attribute \src "issuer_ls180.v:144964.9-144964.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\busy_delay$next[0:0]$7619 1'0 + case + assign $1\busy_delay$next[0:0]$7619 \ldst_port0_busy_o + end + sync always + update \busy_delay$next $0\busy_delay$next[0:0]$7618 + end + attribute \src "issuer_ls180.v:144972.3-144981.6" + process $proc$issuer_ls180.v:144972$7620 + assign { } { } + assign { } { } + assign $0\st_active_r_st_active[0:0] $1\st_active_r_st_active[0:0] + attribute \src "issuer_ls180.v:144973.5-144973.29" + switch \initial + attribute \src "issuer_ls180.v:144973.9-144973.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:275" + switch \reset_l_q_reset + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\st_active_r_st_active[0:0] 1'1 + case + assign $1\st_active_r_st_active[0:0] 1'0 + end + sync always + update \st_active_r_st_active $0\st_active_r_st_active[0:0] + end + attribute \src "issuer_ls180.v:144982.3-144997.6" + process $proc$issuer_ls180.v:144982$7621 + assign { } { } + assign { } { } + assign { } { } + assign $0\lenexp_len_i[3:0] $2\lenexp_len_i[3:0] + attribute \src "issuer_ls180.v:144983.5-144983.29" + switch \initial + attribute \src "issuer_ls180.v:144983.9-144983.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:217" + switch \ld_active_q_ld_active + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\lenexp_len_i[3:0] \ldst_port0_data_len + case + assign $1\lenexp_len_i[3:0] 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:229" + switch \st_active_q_st_active + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\lenexp_len_i[3:0] \ldst_port0_data_len + case + assign $2\lenexp_len_i[3:0] $1\lenexp_len_i[3:0] + end + sync always + update \lenexp_len_i $0\lenexp_len_i[3:0] + end + attribute \src "issuer_ls180.v:144998.3-145013.6" + process $proc$issuer_ls180.v:144998$7622 + assign { } { } + assign { } { } + assign { } { } + assign $0\lenexp_addr_i[3:0] $2\lenexp_addr_i[3:0] + attribute \src "issuer_ls180.v:144999.5-144999.29" + switch \initial + attribute \src "issuer_ls180.v:144999.9-144999.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:217" + switch \ld_active_q_ld_active + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\lenexp_addr_i[3:0] \$21 + case + assign $1\lenexp_addr_i[3:0] 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:229" + switch \st_active_q_st_active + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\lenexp_addr_i[3:0] \$23 + case + assign $2\lenexp_addr_i[3:0] $1\lenexp_addr_i[3:0] + end + sync always + update \lenexp_addr_i $0\lenexp_addr_i[3:0] + end + attribute \src "issuer_ls180.v:145014.3-145039.6" + process $proc$issuer_ls180.v:145014$7623 + assign { } { } + assign { } { } + assign { } { } + assign $0\valid_l_s_valid[0:0] $3\valid_l_s_valid[0:0] + attribute \src "issuer_ls180.v:145015.5-145015.29" + switch \initial + attribute \src "issuer_ls180.v:145015.9-145015.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:217" + switch \ld_active_q_ld_active + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\valid_l_s_valid[0:0] $2\valid_l_s_valid[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:222" + switch \$25 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\valid_l_s_valid[0:0] 1'1 + case + assign $2\valid_l_s_valid[0:0] 1'0 + end + case + assign $1\valid_l_s_valid[0:0] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:229" + switch \st_active_q_st_active + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\valid_l_s_valid[0:0] $4\valid_l_s_valid[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:234" + switch \ldst_port0_addr_i_ok + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\valid_l_s_valid[0:0] 1'1 + case + assign $4\valid_l_s_valid[0:0] $1\valid_l_s_valid[0:0] + end + case + assign $3\valid_l_s_valid[0:0] $1\valid_l_s_valid[0:0] + end + sync always + update \valid_l_s_valid $0\valid_l_s_valid[0:0] + end + attribute \src "issuer_ls180.v:145040.3-145065.6" + process $proc$issuer_ls180.v:145040$7624 + assign { } { } + assign { } { } + assign { } { } + assign $0\x_mask_i[7:0] $3\x_mask_i[7:0] + attribute \src "issuer_ls180.v:145041.5-145041.29" + switch \initial + attribute \src "issuer_ls180.v:145041.9-145041.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:217" + switch \ld_active_q_ld_active + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\x_mask_i[7:0] $2\x_mask_i[7:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:222" + switch \$27 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\x_mask_i[7:0] \lenexp_lexp_o [7:0] + case + assign $2\x_mask_i[7:0] 8'00000000 + end + case + assign $1\x_mask_i[7:0] 8'00000000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:229" + switch \st_active_q_st_active + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\x_mask_i[7:0] $4\x_mask_i[7:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:234" + switch \ldst_port0_addr_i_ok + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\x_mask_i[7:0] \lenexp_lexp_o [7:0] + case + assign $4\x_mask_i[7:0] $1\x_mask_i[7:0] + end + case + assign $3\x_mask_i[7:0] $1\x_mask_i[7:0] + end + sync always + update \x_mask_i $0\x_mask_i[7:0] + end + attribute \src "issuer_ls180.v:145066.3-145091.6" + process $proc$issuer_ls180.v:145066$7625 + assign { } { } + assign { } { } + assign { } { } + assign $0\x_addr_i[47:0] $3\x_addr_i[47:0] + attribute \src "issuer_ls180.v:145067.5-145067.29" + switch \initial + attribute \src "issuer_ls180.v:145067.9-145067.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:217" + switch \ld_active_q_ld_active + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\x_addr_i[47:0] $2\x_addr_i[47:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:222" + switch \$29 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\x_addr_i[47:0] \ldst_port0_addr_i + case + assign $2\x_addr_i[47:0] 48'000000000000000000000000000000000000000000000000 + end + case + assign $1\x_addr_i[47:0] 48'000000000000000000000000000000000000000000000000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:229" + switch \st_active_q_st_active + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\x_addr_i[47:0] $4\x_addr_i[47:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:234" + switch \ldst_port0_addr_i_ok + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\x_addr_i[47:0] \ldst_port0_addr_i + case + assign $4\x_addr_i[47:0] $1\x_addr_i[47:0] + end + case + assign $3\x_addr_i[47:0] $1\x_addr_i[47:0] + end + sync always + update \x_addr_i $0\x_addr_i[47:0] + end + attribute \src "issuer_ls180.v:145092.3-145122.6" + process $proc$issuer_ls180.v:145092$7626 + assign { } { } + assign { } { } + assign { } { } + assign $0\ldst_port0_addr_ok_o[0:0] $3\ldst_port0_addr_ok_o[0:0] + attribute \src "issuer_ls180.v:145093.5-145093.29" + switch \initial + attribute \src "issuer_ls180.v:145093.9-145093.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:217" + switch \ld_active_q_ld_active + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\ldst_port0_addr_ok_o[0:0] $2\ldst_port0_addr_ok_o[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:222" + switch \$31 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\ldst_port0_addr_ok_o[0:0] 1'1 + case + assign $2\ldst_port0_addr_ok_o[0:0] 1'0 + end + case + assign $1\ldst_port0_addr_ok_o[0:0] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:229" + switch \st_active_q_st_active + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\ldst_port0_addr_ok_o[0:0] $4\ldst_port0_addr_ok_o[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:234" + switch \ldst_port0_addr_i_ok + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\ldst_port0_addr_ok_o[0:0] $5\ldst_port0_addr_ok_o[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:236" + switch \adrok_l_qn_addr_acked + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\ldst_port0_addr_ok_o[0:0] 1'1 + case + assign $5\ldst_port0_addr_ok_o[0:0] $1\ldst_port0_addr_ok_o[0:0] + end + case + assign $4\ldst_port0_addr_ok_o[0:0] $1\ldst_port0_addr_ok_o[0:0] + end + case + assign $3\ldst_port0_addr_ok_o[0:0] $1\ldst_port0_addr_ok_o[0:0] + end + sync always + update \ldst_port0_addr_ok_o $0\ldst_port0_addr_ok_o[0:0] + end + attribute \src "issuer_ls180.v:145123.3-145138.6" + process $proc$issuer_ls180.v:145123$7627 + assign { } { } + assign { } { } + assign { } { } + assign $0\reset_l_s_reset[0:0] $2\reset_l_s_reset[0:0] + attribute \src "issuer_ls180.v:145124.5-145124.29" + switch \initial + attribute \src "issuer_ls180.v:145124.9-145124.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:248" + switch \$33 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\reset_l_s_reset[0:0] \$35 + case + assign $1\reset_l_s_reset[0:0] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:265" + switch \st_done_q_st_done + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\reset_l_s_reset[0:0] \$37 + case + assign $2\reset_l_s_reset[0:0] $1\reset_l_s_reset[0:0] + end + sync always + update \reset_l_s_reset $0\reset_l_s_reset[0:0] + end + attribute \src "issuer_ls180.v:145139.3-145148.6" + process $proc$issuer_ls180.v:145139$7628 + assign { } { } + assign { } { } + assign $0\reset_l_r_reset[0:0] $1\reset_l_r_reset[0:0] + attribute \src "issuer_ls180.v:145140.5-145140.29" + switch \initial + attribute \src "issuer_ls180.v:145140.9-145140.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:275" + switch \reset_l_q_reset + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\reset_l_r_reset[0:0] 1'1 + case + assign $1\reset_l_r_reset[0:0] 1'0 + end + sync always + update \reset_l_r_reset $0\reset_l_r_reset[0:0] + end + attribute \src "issuer_ls180.v:145149.3-145158.6" + process $proc$issuer_ls180.v:145149$7629 + assign { } { } + assign { } { } + assign $0\ldst_port0_ld_data_o[63:0] $1\ldst_port0_ld_data_o[63:0] + attribute \src "issuer_ls180.v:145150.5-145150.29" + switch \initial + attribute \src "issuer_ls180.v:145150.9-145150.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:248" + switch \$48 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\ldst_port0_ld_data_o[63:0] \lddata + case + assign $1\ldst_port0_ld_data_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \ldst_port0_ld_data_o $0\ldst_port0_ld_data_o[63:0] + end + attribute \src "issuer_ls180.v:145159.3-145168.6" + process $proc$issuer_ls180.v:145159$7630 + assign { } { } + assign { } { } + assign $0\ld_active_r_ld_active[0:0] $1\ld_active_r_ld_active[0:0] + attribute \src "issuer_ls180.v:145160.5-145160.29" + switch \initial + attribute \src "issuer_ls180.v:145160.9-145160.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:275" + switch \reset_l_q_reset + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\ld_active_r_ld_active[0:0] 1'1 + case + assign $1\ld_active_r_ld_active[0:0] 1'0 + end + sync always + update \ld_active_r_ld_active $0\ld_active_r_ld_active[0:0] + end + attribute \src "issuer_ls180.v:145169.3-145178.6" + process $proc$issuer_ls180.v:145169$7631 + assign { } { } + assign { } { } + assign $0\ldst_port0_ld_data_o_ok[0:0] $1\ldst_port0_ld_data_o_ok[0:0] + attribute \src "issuer_ls180.v:145170.5-145170.29" + switch \initial + attribute \src "issuer_ls180.v:145170.9-145170.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:248" + switch \$50 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\ldst_port0_ld_data_o_ok[0:0] \$52 + case + assign $1\ldst_port0_ld_data_o_ok[0:0] 1'0 + end + sync always + update \ldst_port0_ld_data_o_ok $0\ldst_port0_ld_data_o_ok[0:0] + end + attribute \src "issuer_ls180.v:145179.3-145188.6" + process $proc$issuer_ls180.v:145179$7632 + assign { } { } + assign { } { } + assign $0\stdata[63:0] $1\stdata[63:0] + attribute \src "issuer_ls180.v:145180.5-145180.29" + switch \initial + attribute \src "issuer_ls180.v:145180.9-145180.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:256" + switch \$54 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\stdata[63:0] \$56 [63:0] + case + assign $1\stdata[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \stdata $0\stdata[63:0] + end + attribute \src "issuer_ls180.v:145189.3-145198.6" + process $proc$issuer_ls180.v:145189$7633 + assign { } { } + assign { } { } + assign $0\x_st_data_i[63:0] $1\x_st_data_i[63:0] + attribute \src "issuer_ls180.v:145190.5-145190.29" + switch \initial + attribute \src "issuer_ls180.v:145190.9-145190.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:256" + switch \$61 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\x_st_data_i[63:0] \stdata + case + assign $1\x_st_data_i[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \x_st_data_i $0\x_st_data_i[63:0] + end + attribute \src "issuer_ls180.v:145199.3-145218.6" + process $proc$issuer_ls180.v:145199$7634 + assign { } { } + assign { } { } + assign $0\lsui_busy[0:0] $1\lsui_busy[0:0] + attribute \src "issuer_ls180.v:145200.5-145200.29" + switch \initial + attribute \src "issuer_ls180.v:145200.9-145200.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:85" + switch \fsm_state + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\lsui_busy[0:0] $2\lsui_busy[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:88" + switch \$65 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\lsui_busy[0:0] 1'1 + case + assign $2\lsui_busy[0:0] 1'0 + end + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\lsui_busy[0:0] 1'1 + case + assign $1\lsui_busy[0:0] 1'0 + end + sync always + update \lsui_busy $0\lsui_busy[0:0] + end + attribute \src "issuer_ls180.v:145219.3-145257.6" + process $proc$issuer_ls180.v:145219$7635 + assign { } { } + assign { } { } + assign { } { } + assign $0\fsm_state$next[1:0]$7636 $5\fsm_state$next[1:0]$7641 + attribute \src "issuer_ls180.v:145220.5-145220.29" + switch \initial + attribute \src "issuer_ls180.v:145220.9-145220.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:85" + switch \fsm_state + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\fsm_state$next[1:0]$7637 $2\fsm_state$next[1:0]$7638 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:88" + switch \$69 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\fsm_state$next[1:0]$7638 2'01 + case + assign $2\fsm_state$next[1:0]$7638 \fsm_state + end + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\fsm_state$next[1:0]$7637 $3\fsm_state$next[1:0]$7639 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:95" + switch \$71 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\fsm_state$next[1:0]$7639 2'10 + case + assign $3\fsm_state$next[1:0]$7639 \fsm_state + end + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\fsm_state$next[1:0]$7637 $4\fsm_state$next[1:0]$7640 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:99" + switch \$77 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\fsm_state$next[1:0]$7640 2'00 + case + assign $4\fsm_state$next[1:0]$7640 \fsm_state + end + case + assign $1\fsm_state$next[1:0]$7637 \fsm_state + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\fsm_state$next[1:0]$7641 2'00 + case + assign $5\fsm_state$next[1:0]$7641 $1\fsm_state$next[1:0]$7637 + end + sync always + update \fsm_state$next $0\fsm_state$next[1:0]$7636 + end + attribute \src "issuer_ls180.v:145258.3-145267.6" + process $proc$issuer_ls180.v:145258$7642 + assign { } { } + assign { } { } + assign $0\cyc_l_s_cyc[0:0] $1\cyc_l_s_cyc[0:0] + attribute \src "issuer_ls180.v:145259.5-145259.29" + switch \initial + attribute \src "issuer_ls180.v:145259.9-145259.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:288" + switch \reset_l_s_reset + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\cyc_l_s_cyc[0:0] 1'1 + case + assign $1\cyc_l_s_cyc[0:0] 1'0 + end + sync always + update \cyc_l_s_cyc $0\cyc_l_s_cyc[0:0] + end + attribute \src "issuer_ls180.v:145268.3-145276.6" + process $proc$issuer_ls180.v:145268$7643 + assign { } { } + assign { } { } + assign $0\lsui_active_dly$next[0:0]$7644 $1\lsui_active_dly$next[0:0]$7645 + attribute \src "issuer_ls180.v:145269.5-145269.29" + switch \initial + attribute \src "issuer_ls180.v:145269.9-145269.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\lsui_active_dly$next[0:0]$7645 1'0 + case + assign $1\lsui_active_dly$next[0:0]$7645 \lsui_active + end + sync always + update \lsui_active_dly$next $0\lsui_active_dly$next[0:0]$7644 + end + attribute \src "issuer_ls180.v:145277.3-145286.6" + process $proc$issuer_ls180.v:145277$7646 + assign { } { } + assign { } { } + assign $0\cyc_l_r_cyc[0:0] $1\cyc_l_r_cyc[0:0] + attribute \src "issuer_ls180.v:145278.5-145278.29" + switch \initial + attribute \src "issuer_ls180.v:145278.9-145278.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:291" + switch \cyc_l_q_cyc + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\cyc_l_r_cyc[0:0] 1'1 + case + assign $1\cyc_l_r_cyc[0:0] 1'0 + end + sync always + update \cyc_l_r_cyc $0\cyc_l_r_cyc[0:0] + end + attribute \src "issuer_ls180.v:145287.3-145296.6" + process $proc$issuer_ls180.v:145287$7647 + assign { } { } + assign { } { } + assign $0\busy_l_s_busy[0:0] $1\busy_l_s_busy[0:0] + attribute \src "issuer_ls180.v:145288.5-145288.29" + switch \initial + attribute \src "issuer_ls180.v:145288.9-145288.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:212" + switch \$3 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\busy_l_s_busy[0:0] \$5 + case + assign $1\busy_l_s_busy[0:0] 1'0 + end + sync always + update \busy_l_s_busy $0\busy_l_s_busy[0:0] + end + attribute \src "issuer_ls180.v:145297.3-145312.6" + process $proc$issuer_ls180.v:145297$7648 + assign { } { } + assign { } { } + assign { } { } + assign $0\busy_l_r_busy[0:0] $2\busy_l_r_busy[0:0] + attribute \src "issuer_ls180.v:145298.5-145298.29" + switch \initial + attribute \src "issuer_ls180.v:145298.9-145298.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:283" + switch \ldst_port0_addr_exc_o + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\busy_l_r_busy[0:0] 1'1 + case + assign $1\busy_l_r_busy[0:0] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:291" + switch \cyc_l_q_cyc + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\busy_l_r_busy[0:0] 1'1 + case + assign $2\busy_l_r_busy[0:0] $1\busy_l_r_busy[0:0] + end + sync always + update \busy_l_r_busy $0\busy_l_r_busy[0:0] + end + attribute \src "issuer_ls180.v:145313.3-145348.6" + process $proc$issuer_ls180.v:145313$7649 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\adrok_l_s_addr_acked$next[0:0]$7650 $6\adrok_l_s_addr_acked$next[0:0]$7656 + attribute \src "issuer_ls180.v:145314.5-145314.29" + switch \initial + attribute \src "issuer_ls180.v:145314.9-145314.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:217" + switch \ld_active_q_ld_active + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\adrok_l_s_addr_acked$next[0:0]$7651 $2\adrok_l_s_addr_acked$next[0:0]$7652 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:222" + switch \$7 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\adrok_l_s_addr_acked$next[0:0]$7652 1'1 + case + assign $2\adrok_l_s_addr_acked$next[0:0]$7652 1'0 + end + case + assign $1\adrok_l_s_addr_acked$next[0:0]$7651 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:229" + switch \st_active_q_st_active + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\adrok_l_s_addr_acked$next[0:0]$7653 $4\adrok_l_s_addr_acked$next[0:0]$7654 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:234" + switch \ldst_port0_addr_i_ok + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\adrok_l_s_addr_acked$next[0:0]$7654 $5\adrok_l_s_addr_acked$next[0:0]$7655 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:236" + switch \adrok_l_qn_addr_acked + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\adrok_l_s_addr_acked$next[0:0]$7655 1'1 + case + assign $5\adrok_l_s_addr_acked$next[0:0]$7655 $1\adrok_l_s_addr_acked$next[0:0]$7651 + end + case + assign $4\adrok_l_s_addr_acked$next[0:0]$7654 $1\adrok_l_s_addr_acked$next[0:0]$7651 + end + case + assign $3\adrok_l_s_addr_acked$next[0:0]$7653 $1\adrok_l_s_addr_acked$next[0:0]$7651 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $6\adrok_l_s_addr_acked$next[0:0]$7656 1'0 + case + assign $6\adrok_l_s_addr_acked$next[0:0]$7656 $3\adrok_l_s_addr_acked$next[0:0]$7653 + end + sync always + update \adrok_l_s_addr_acked$next $0\adrok_l_s_addr_acked$next[0:0]$7650 + end + attribute \src "issuer_ls180.v:145349.3-145364.6" + process $proc$issuer_ls180.v:145349$7657 + assign { } { } + assign { } { } + assign { } { } + assign $0\adrok_l_r_addr_acked[0:0] $2\adrok_l_r_addr_acked[0:0] + attribute \src "issuer_ls180.v:145350.5-145350.29" + switch \initial + attribute \src "issuer_ls180.v:145350.9-145350.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:271" + switch \reset_delay + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\adrok_l_r_addr_acked[0:0] 1'1 + case + assign $1\adrok_l_r_addr_acked[0:0] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:275" + switch \reset_l_q_reset + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\adrok_l_r_addr_acked[0:0] 1'1 + case + assign $2\adrok_l_r_addr_acked[0:0] $1\adrok_l_r_addr_acked[0:0] + end + sync always + update \adrok_l_r_addr_acked $0\adrok_l_r_addr_acked[0:0] + end + connect \$9 $not$issuer_ls180.v:144818$7561_Y + connect \$11 $and$issuer_ls180.v:144819$7562_Y + connect \$13 $not$issuer_ls180.v:144820$7563_Y + connect \$15 $and$issuer_ls180.v:144821$7564_Y + connect \$17 $not$issuer_ls180.v:144822$7565_Y + connect \$1 $and$issuer_ls180.v:144823$7566_Y + connect \$19 $and$issuer_ls180.v:144824$7567_Y + connect \$21 $pos$issuer_ls180.v:144825$7569_Y + connect \$23 $pos$issuer_ls180.v:144826$7571_Y + connect \$25 $and$issuer_ls180.v:144827$7572_Y + connect \$27 $and$issuer_ls180.v:144828$7573_Y + connect \$29 $and$issuer_ls180.v:144829$7574_Y + connect \$31 $and$issuer_ls180.v:144830$7575_Y + connect \$33 $and$issuer_ls180.v:144831$7576_Y + connect \$35 $not$issuer_ls180.v:144832$7577_Y + connect \$38 $or$issuer_ls180.v:144833$7578_Y + connect \$3 $or$issuer_ls180.v:144834$7579_Y + connect \$37 $not$issuer_ls180.v:144835$7580_Y + connect \$42 $and$issuer_ls180.v:144836$7581_Y + connect \$44 $mul$issuer_ls180.v:144837$7582_Y + connect \$46 $sshr$issuer_ls180.v:144838$7583_Y + connect \$48 $and$issuer_ls180.v:144839$7584_Y + connect \$50 $and$issuer_ls180.v:144840$7585_Y + connect \$52 $not$issuer_ls180.v:144841$7586_Y + connect \$54 $and$issuer_ls180.v:144842$7587_Y + connect \$57 $mul$issuer_ls180.v:144843$7588_Y + connect \$5 $not$issuer_ls180.v:144844$7589_Y + connect \$59 $sshl$issuer_ls180.v:144845$7590_Y + connect \$61 $and$issuer_ls180.v:144846$7591_Y + connect \$63 $or$issuer_ls180.v:144847$7592_Y + connect \$65 $and$issuer_ls180.v:144848$7593_Y + connect \$67 $or$issuer_ls180.v:144849$7594_Y + connect \$69 $and$issuer_ls180.v:144850$7595_Y + connect \$71 $not$issuer_ls180.v:144851$7596_Y + connect \$73 $not$issuer_ls180.v:144852$7597_Y + connect \$75 $not$issuer_ls180.v:144853$7598_Y + connect \$77 $and$issuer_ls180.v:144854$7599_Y + connect \$7 $and$issuer_ls180.v:144855$7600_Y + connect \$79 $not$issuer_ls180.v:144856$7601_Y + connect \$81 $not$issuer_ls180.v:144857$7602_Y + connect \$83 $and$issuer_ls180.v:144858$7603_Y + connect \$41 \$46 + connect \$56 \$59 + connect \valid_l_r_valid \lsui_active_rise + connect \lsui_active_rise \$83 + connect \lsui_active \$79 + connect \x_valid_i \valid_l_q_valid + connect \m_valid_i \valid_l_q_valid + connect \x_st_i \ldst_port0_is_st_i + connect \x_ld_i \ldst_port0_is_ld_i + connect \ldst_port0_busy_o \busy_l_q_busy + connect \reset_delay$next \reset_l_q_reset + connect \lddata \$46 [63:0] + connect \st_active_s_st_active \sts_rise + connect \sts_rise \$19 + connect \sts_dly$next \sts + connect \ld_active_s_ld_active \lds_rise + connect \lds_rise \$15 + connect \lds_dly$next \lds + connect \busy_edge \$11 + connect \sts \ldst_port0_is_st_i + connect \lds \ldst_port0_is_ld_i +end +attribute \src "issuer_ls180.v:145390.1-146155.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.fus.cr0.alu_cr0.pipe" +attribute \generator "nMigen" +module \pipe + attribute \src "issuer_ls180.v:146118.3-146136.6" + wire width 4 $0\cr_a$6$next[3:0]$7713 + attribute \src "issuer_ls180.v:145982.3-145983.31" + wire width 4 $0\cr_a$6[3:0]$7669 + attribute \src "issuer_ls180.v:145404.13-145404.28" + wire width 4 $0\cr_a$6[3:0]$7719 + attribute \src "issuer_ls180.v:146118.3-146136.6" + wire $0\cr_a_ok$next[0:0]$7712 + attribute \src "issuer_ls180.v:145984.3-145985.31" + wire $0\cr_a_ok[0:0] + attribute \src "issuer_ls180.v:146065.3-146079.6" + wire width 12 $0\cr_op__fn_unit$3$next[11:0]$7693 + attribute \src "issuer_ls180.v:145996.3-145997.51" + wire width 12 $0\cr_op__fn_unit$3[11:0]$7679 + attribute \src "issuer_ls180.v:145463.14-145463.42" + wire width 12 $0\cr_op__fn_unit$3[11:0]$7722 + attribute \src "issuer_ls180.v:146065.3-146079.6" + wire width 32 $0\cr_op__insn$4$next[31:0]$7694 + attribute \src "issuer_ls180.v:145998.3-145999.45" + wire width 32 $0\cr_op__insn$4[31:0]$7681 + attribute \src "issuer_ls180.v:145472.14-145472.37" + wire width 32 $0\cr_op__insn$4[31:0]$7724 + attribute \src "issuer_ls180.v:146065.3-146079.6" + wire width 7 $0\cr_op__insn_type$2$next[6:0]$7695 + attribute \src "issuer_ls180.v:145994.3-145995.55" + wire width 7 $0\cr_op__insn_type$2[6:0]$7677 + attribute \src "issuer_ls180.v:145703.13-145703.41" + wire width 7 $0\cr_op__insn_type$2[6:0]$7726 + attribute \src "issuer_ls180.v:146099.3-146117.6" + wire width 32 $0\full_cr$5$next[31:0]$7706 + attribute \src "issuer_ls180.v:145986.3-145987.37" + wire width 32 $0\full_cr$5[31:0]$7672 + attribute \src "issuer_ls180.v:145712.14-145712.33" + wire width 32 $0\full_cr$5[31:0]$7728 + attribute \src "issuer_ls180.v:146099.3-146117.6" + wire $0\full_cr_ok$next[0:0]$7707 + attribute \src "issuer_ls180.v:145988.3-145989.37" + wire $0\full_cr_ok[0:0] + attribute \src "issuer_ls180.v:145391.7-145391.20" + wire $0\initial[0:0] + attribute \src "issuer_ls180.v:146052.3-146064.6" + wire width 2 $0\muxid$1$next[1:0]$7690 + attribute \src "issuer_ls180.v:146000.3-146001.33" + wire width 2 $0\muxid$1[1:0]$7683 + attribute \src "issuer_ls180.v:145940.13-145940.29" + wire width 2 $0\muxid$1[1:0]$7731 + attribute \src "issuer_ls180.v:146080.3-146098.6" + wire width 64 $0\o$next[63:0]$7700 + attribute \src "issuer_ls180.v:145990.3-145991.19" + wire width 64 $0\o[63:0] + attribute \src "issuer_ls180.v:146080.3-146098.6" + wire $0\o_ok$next[0:0]$7701 + attribute \src "issuer_ls180.v:145992.3-145993.25" + wire $0\o_ok[0:0] + attribute \src "issuer_ls180.v:146034.3-146051.6" + wire $0\r_busy$next[0:0]$7686 + attribute \src "issuer_ls180.v:146002.3-146003.29" + wire $0\r_busy[0:0] + attribute \src "issuer_ls180.v:146118.3-146136.6" + wire width 4 $1\cr_a$6$next[3:0]$7715 + attribute \src "issuer_ls180.v:146118.3-146136.6" + wire $1\cr_a_ok$next[0:0]$7714 + attribute \src "issuer_ls180.v:145409.7-145409.21" + wire $1\cr_a_ok[0:0] + attribute \src "issuer_ls180.v:146065.3-146079.6" + wire width 12 $1\cr_op__fn_unit$3$next[11:0]$7696 + attribute \src "issuer_ls180.v:146065.3-146079.6" + wire width 32 $1\cr_op__insn$4$next[31:0]$7697 + attribute \src "issuer_ls180.v:146065.3-146079.6" + wire width 7 $1\cr_op__insn_type$2$next[6:0]$7698 + attribute \src "issuer_ls180.v:146099.3-146117.6" + wire width 32 $1\full_cr$5$next[31:0]$7708 + attribute \src "issuer_ls180.v:146099.3-146117.6" + wire $1\full_cr_ok$next[0:0]$7709 + attribute \src "issuer_ls180.v:145717.7-145717.24" + wire $1\full_cr_ok[0:0] + attribute \src "issuer_ls180.v:146052.3-146064.6" + wire width 2 $1\muxid$1$next[1:0]$7691 + attribute \src "issuer_ls180.v:146080.3-146098.6" + wire width 64 $1\o$next[63:0]$7702 + attribute \src "issuer_ls180.v:145953.14-145953.38" + wire width 64 $1\o[63:0] + attribute \src "issuer_ls180.v:146080.3-146098.6" + wire $1\o_ok$next[0:0]$7703 + attribute \src "issuer_ls180.v:145960.7-145960.18" + wire $1\o_ok[0:0] + attribute \src "issuer_ls180.v:146034.3-146051.6" + wire $1\r_busy$next[0:0]$7687 + attribute \src "issuer_ls180.v:145974.7-145974.20" + wire $1\r_busy[0:0] + attribute \src "issuer_ls180.v:146118.3-146136.6" + wire $2\cr_a_ok$next[0:0]$7716 + attribute \src "issuer_ls180.v:146099.3-146117.6" + wire $2\full_cr_ok$next[0:0]$7710 + attribute \src "issuer_ls180.v:146080.3-146098.6" + wire $2\o_ok$next[0:0]$7704 + attribute \src "issuer_ls180.v:146034.3-146051.6" + wire $2\r_busy$next[0:0]$7688 + attribute \src "issuer_ls180.v:145981.18-145981.118" + wire $and$issuer_ls180.v:145981$7667_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" + wire \$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" + wire input 26 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" + wire input 1 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 4 input 11 \cr_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 4 \cr_a$24 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 4 output 24 \cr_a$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 4 \cr_a$6$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 25 \cr_a_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \cr_a_ok$25 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \cr_a_ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 4 input 12 \cr_b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 4 input 13 \cr_c + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 input 6 \cr_op__fn_unit + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 \cr_op__fn_unit$18 + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 output 18 \cr_op__fn_unit$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 \cr_op__fn_unit$3$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 7 \cr_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \cr_op__insn$19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 output 19 \cr_op__insn$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \cr_op__insn$4$next + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 input 5 \cr_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \cr_op__insn_type$17 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 output 17 \cr_op__insn_type$2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \cr_op__insn_type$2$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 32 input 10 \full_cr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 32 \full_cr$22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 32 output 22 \full_cr$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 32 \full_cr$5$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 23 \full_cr_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \full_cr_ok$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \full_cr_ok$next + attribute \src "issuer_ls180.v:145391.7-145391.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 4 \main_cr_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 4 \main_cr_a$12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \main_cr_a_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 4 \main_cr_b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 4 \main_cr_c + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 \main_cr_op__fn_unit + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 \main_cr_op__fn_unit$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \main_cr_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \main_cr_op__insn$10 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \main_cr_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \main_cr_op__insn_type$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 32 \main_full_cr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 32 \main_full_cr$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \main_full_cr_ok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \main_muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \main_muxid$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 \main_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \main_o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \main_ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \main_rb + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 input 4 \muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 output 16 \muxid$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \muxid$1$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \muxid$16 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:619" + wire \n_i_rdy_data + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" + wire input 15 \n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" + wire output 14 \n_valid_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 output 20 \o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 \o$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 \o$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 21 \o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \o_ok$21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \o_ok$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" + wire output 3 \p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" + wire input 2 \p_valid_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:621" + wire \p_valid_i$13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" + wire \p_valid_i_p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615" + wire \r_busy + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615" + wire \r_busy$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 8 \ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 9 \rb + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" + cell $and $and$issuer_ls180.v:145981$7667 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \p_valid_i$13 + connect \B \p_ready_o + connect \Y $and$issuer_ls180.v:145981$7667_Y + end + attribute \module_not_derived 1 + attribute \src "issuer_ls180.v:146004.12-146025.4" + cell \main$9 \main + connect \cr_a \main_cr_a + connect \cr_a$6 \main_cr_a$12 + connect \cr_a_ok \main_cr_a_ok + connect \cr_b \main_cr_b + connect \cr_c \main_cr_c + connect \cr_op__fn_unit \main_cr_op__fn_unit + connect \cr_op__fn_unit$3 \main_cr_op__fn_unit$9 + connect \cr_op__insn \main_cr_op__insn + connect \cr_op__insn$4 \main_cr_op__insn$10 + connect \cr_op__insn_type \main_cr_op__insn_type + connect \cr_op__insn_type$2 \main_cr_op__insn_type$8 + connect \full_cr \main_full_cr + connect \full_cr$5 \main_full_cr$11 + connect \full_cr_ok \main_full_cr_ok + connect \muxid \main_muxid + connect \muxid$1 \main_muxid$7 + connect \o \main_o + connect \o_ok \main_o_ok + connect \ra \main_ra + connect \rb \main_rb + end + attribute \module_not_derived 1 + attribute \src "issuer_ls180.v:146026.9-146029.4" + cell \n$8 \n + connect \n_ready_i \n_ready_i + connect \n_valid_o \n_valid_o + end + attribute \module_not_derived 1 + attribute \src "issuer_ls180.v:146030.9-146033.4" + cell \p$7 \p + connect \p_ready_o \p_ready_o + connect \p_valid_i \p_valid_i + end + attribute \src "issuer_ls180.v:145391.7-145391.20" + process $proc$issuer_ls180.v:145391$7717 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "issuer_ls180.v:145404.13-145404.28" + process $proc$issuer_ls180.v:145404$7718 + assign { } { } + assign $0\cr_a$6[3:0]$7719 4'0000 + sync always + sync init + update \cr_a$6 $0\cr_a$6[3:0]$7719 + end + attribute \src "issuer_ls180.v:145409.7-145409.21" + process $proc$issuer_ls180.v:145409$7720 + assign { } { } + assign $1\cr_a_ok[0:0] 1'0 + sync always + sync init + update \cr_a_ok $1\cr_a_ok[0:0] + end + attribute \src "issuer_ls180.v:145463.14-145463.42" + process $proc$issuer_ls180.v:145463$7721 + assign { } { } + assign $0\cr_op__fn_unit$3[11:0]$7722 12'000000000000 + sync always + sync init + update \cr_op__fn_unit$3 $0\cr_op__fn_unit$3[11:0]$7722 + end + attribute \src "issuer_ls180.v:145472.14-145472.37" + process $proc$issuer_ls180.v:145472$7723 + assign { } { } + assign $0\cr_op__insn$4[31:0]$7724 0 + sync always + sync init + update \cr_op__insn$4 $0\cr_op__insn$4[31:0]$7724 + end + attribute \src "issuer_ls180.v:145703.13-145703.41" + process $proc$issuer_ls180.v:145703$7725 + assign { } { } + assign $0\cr_op__insn_type$2[6:0]$7726 7'0000000 + sync always + sync init + update \cr_op__insn_type$2 $0\cr_op__insn_type$2[6:0]$7726 + end + attribute \src "issuer_ls180.v:145712.14-145712.33" + process $proc$issuer_ls180.v:145712$7727 + assign { } { } + assign $0\full_cr$5[31:0]$7728 0 + sync always + sync init + update \full_cr$5 $0\full_cr$5[31:0]$7728 + end + attribute \src "issuer_ls180.v:145717.7-145717.24" + process $proc$issuer_ls180.v:145717$7729 + assign { } { } + assign $1\full_cr_ok[0:0] 1'0 + sync always + sync init + update \full_cr_ok $1\full_cr_ok[0:0] + end + attribute \src "issuer_ls180.v:145940.13-145940.29" + process $proc$issuer_ls180.v:145940$7730 + assign { } { } + assign $0\muxid$1[1:0]$7731 2'00 + sync always + sync init + update \muxid$1 $0\muxid$1[1:0]$7731 + end + attribute \src "issuer_ls180.v:145953.14-145953.38" + process $proc$issuer_ls180.v:145953$7732 + assign { } { } + assign $1\o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \o $1\o[63:0] + end + attribute \src "issuer_ls180.v:145960.7-145960.18" + process $proc$issuer_ls180.v:145960$7733 + assign { } { } + assign $1\o_ok[0:0] 1'0 + sync always + sync init + update \o_ok $1\o_ok[0:0] + end + attribute \src "issuer_ls180.v:145974.7-145974.20" + process $proc$issuer_ls180.v:145974$7734 + assign { } { } + assign $1\r_busy[0:0] 1'0 + sync always + sync init + update \r_busy $1\r_busy[0:0] + end + attribute \src "issuer_ls180.v:145982.3-145983.31" + process $proc$issuer_ls180.v:145982$7668 + assign { } { } + assign $0\cr_a$6[3:0]$7669 \cr_a$6$next + sync posedge \coresync_clk + update \cr_a$6 $0\cr_a$6[3:0]$7669 + end + attribute \src "issuer_ls180.v:145984.3-145985.31" + process $proc$issuer_ls180.v:145984$7670 + assign { } { } + assign $0\cr_a_ok[0:0] \cr_a_ok$next + sync posedge \coresync_clk + update \cr_a_ok $0\cr_a_ok[0:0] + end + attribute \src "issuer_ls180.v:145986.3-145987.37" + process $proc$issuer_ls180.v:145986$7671 + assign { } { } + assign $0\full_cr$5[31:0]$7672 \full_cr$5$next + sync posedge \coresync_clk + update \full_cr$5 $0\full_cr$5[31:0]$7672 + end + attribute \src "issuer_ls180.v:145988.3-145989.37" + process $proc$issuer_ls180.v:145988$7673 + assign { } { } + assign $0\full_cr_ok[0:0] \full_cr_ok$next + sync posedge \coresync_clk + update \full_cr_ok $0\full_cr_ok[0:0] + end + attribute \src "issuer_ls180.v:145990.3-145991.19" + process $proc$issuer_ls180.v:145990$7674 + assign { } { } + assign $0\o[63:0] \o$next + sync posedge \coresync_clk + update \o $0\o[63:0] + end + attribute \src "issuer_ls180.v:145992.3-145993.25" + process $proc$issuer_ls180.v:145992$7675 + assign { } { } + assign $0\o_ok[0:0] \o_ok$next + sync posedge \coresync_clk + update \o_ok $0\o_ok[0:0] + end + attribute \src "issuer_ls180.v:145994.3-145995.55" + process $proc$issuer_ls180.v:145994$7676 + assign { } { } + assign $0\cr_op__insn_type$2[6:0]$7677 \cr_op__insn_type$2$next + sync posedge \coresync_clk + update \cr_op__insn_type$2 $0\cr_op__insn_type$2[6:0]$7677 + end + attribute \src "issuer_ls180.v:145996.3-145997.51" + process $proc$issuer_ls180.v:145996$7678 + assign { } { } + assign $0\cr_op__fn_unit$3[11:0]$7679 \cr_op__fn_unit$3$next + sync posedge \coresync_clk + update \cr_op__fn_unit$3 $0\cr_op__fn_unit$3[11:0]$7679 + end + attribute \src "issuer_ls180.v:145998.3-145999.45" + process $proc$issuer_ls180.v:145998$7680 + assign { } { } + assign $0\cr_op__insn$4[31:0]$7681 \cr_op__insn$4$next + sync posedge \coresync_clk + update \cr_op__insn$4 $0\cr_op__insn$4[31:0]$7681 + end + attribute \src "issuer_ls180.v:146000.3-146001.33" + process $proc$issuer_ls180.v:146000$7682 + assign { } { } + assign $0\muxid$1[1:0]$7683 \muxid$1$next + sync posedge \coresync_clk + update \muxid$1 $0\muxid$1[1:0]$7683 + end + attribute \src "issuer_ls180.v:146002.3-146003.29" + process $proc$issuer_ls180.v:146002$7684 + assign { } { } + assign $0\r_busy[0:0] \r_busy$next + sync posedge \coresync_clk + update \r_busy $0\r_busy[0:0] + end + attribute \src "issuer_ls180.v:146034.3-146051.6" + process $proc$issuer_ls180.v:146034$7685 + assign { } { } + assign { } { } + assign { } { } + assign $0\r_busy$next[0:0]$7686 $2\r_busy$next[0:0]$7688 + attribute \src "issuer_ls180.v:146035.5-146035.29" + switch \initial + attribute \src "issuer_ls180.v:146035.9-146035.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\r_busy$next[0:0]$7687 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\r_busy$next[0:0]$7687 1'0 + case + assign $1\r_busy$next[0:0]$7687 \r_busy + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\r_busy$next[0:0]$7688 1'0 + case + assign $2\r_busy$next[0:0]$7688 $1\r_busy$next[0:0]$7687 + end + sync always + update \r_busy$next $0\r_busy$next[0:0]$7686 + end + attribute \src "issuer_ls180.v:146052.3-146064.6" + process $proc$issuer_ls180.v:146052$7689 + assign { } { } + assign { } { } + assign $0\muxid$1$next[1:0]$7690 $1\muxid$1$next[1:0]$7691 + attribute \src "issuer_ls180.v:146053.5-146053.29" + switch \initial + attribute \src "issuer_ls180.v:146053.9-146053.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\muxid$1$next[1:0]$7691 \muxid$16 + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\muxid$1$next[1:0]$7691 \muxid$16 + case + assign $1\muxid$1$next[1:0]$7691 \muxid$1 + end + sync always + update \muxid$1$next $0\muxid$1$next[1:0]$7690 + end + attribute \src "issuer_ls180.v:146065.3-146079.6" + process $proc$issuer_ls180.v:146065$7692 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\cr_op__fn_unit$3$next[11:0]$7693 $1\cr_op__fn_unit$3$next[11:0]$7696 + assign $0\cr_op__insn$4$next[31:0]$7694 $1\cr_op__insn$4$next[31:0]$7697 + assign $0\cr_op__insn_type$2$next[6:0]$7695 $1\cr_op__insn_type$2$next[6:0]$7698 + attribute \src "issuer_ls180.v:146066.5-146066.29" + switch \initial + attribute \src "issuer_ls180.v:146066.9-146066.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'-1 + assign { } { } + assign { } { } + assign { } { } + assign { $1\cr_op__insn$4$next[31:0]$7697 $1\cr_op__fn_unit$3$next[11:0]$7696 $1\cr_op__insn_type$2$next[6:0]$7698 } { \cr_op__insn$19 \cr_op__fn_unit$18 \cr_op__insn_type$17 } + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'1- + assign { } { } + assign { } { } + assign { } { } + assign { $1\cr_op__insn$4$next[31:0]$7697 $1\cr_op__fn_unit$3$next[11:0]$7696 $1\cr_op__insn_type$2$next[6:0]$7698 } { \cr_op__insn$19 \cr_op__fn_unit$18 \cr_op__insn_type$17 } + case + assign $1\cr_op__fn_unit$3$next[11:0]$7696 \cr_op__fn_unit$3 + assign $1\cr_op__insn$4$next[31:0]$7697 \cr_op__insn$4 + assign $1\cr_op__insn_type$2$next[6:0]$7698 \cr_op__insn_type$2 + end + sync always + update \cr_op__fn_unit$3$next $0\cr_op__fn_unit$3$next[11:0]$7693 + update \cr_op__insn$4$next $0\cr_op__insn$4$next[31:0]$7694 + update \cr_op__insn_type$2$next $0\cr_op__insn_type$2$next[6:0]$7695 + end + attribute \src "issuer_ls180.v:146080.3-146098.6" + process $proc$issuer_ls180.v:146080$7699 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\o$next[63:0]$7700 $1\o$next[63:0]$7702 + assign { } { } + assign $0\o_ok$next[0:0]$7701 $2\o_ok$next[0:0]$7704 + attribute \src "issuer_ls180.v:146081.5-146081.29" + switch \initial + attribute \src "issuer_ls180.v:146081.9-146081.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'-1 + assign { } { } + assign { } { } + assign { $1\o_ok$next[0:0]$7703 $1\o$next[63:0]$7702 } { \o_ok$21 \o$20 } + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'1- + assign { } { } + assign { } { } + assign { $1\o_ok$next[0:0]$7703 $1\o$next[63:0]$7702 } { \o_ok$21 \o$20 } + case + assign $1\o$next[63:0]$7702 \o + assign $1\o_ok$next[0:0]$7703 \o_ok + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\o_ok$next[0:0]$7704 1'0 + case + assign $2\o_ok$next[0:0]$7704 $1\o_ok$next[0:0]$7703 + end + sync always + update \o$next $0\o$next[63:0]$7700 + update \o_ok$next $0\o_ok$next[0:0]$7701 + end + attribute \src "issuer_ls180.v:146099.3-146117.6" + process $proc$issuer_ls180.v:146099$7705 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\full_cr$5$next[31:0]$7706 $1\full_cr$5$next[31:0]$7708 + assign { } { } + assign $0\full_cr_ok$next[0:0]$7707 $2\full_cr_ok$next[0:0]$7710 + attribute \src "issuer_ls180.v:146100.5-146100.29" + switch \initial + attribute \src "issuer_ls180.v:146100.9-146100.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'-1 + assign { } { } + assign { } { } + assign { $1\full_cr_ok$next[0:0]$7709 $1\full_cr$5$next[31:0]$7708 } { \full_cr_ok$23 \full_cr$22 } + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'1- + assign { } { } + assign { } { } + assign { $1\full_cr_ok$next[0:0]$7709 $1\full_cr$5$next[31:0]$7708 } { \full_cr_ok$23 \full_cr$22 } + case + assign $1\full_cr$5$next[31:0]$7708 \full_cr$5 + assign $1\full_cr_ok$next[0:0]$7709 \full_cr_ok + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\full_cr_ok$next[0:0]$7710 1'0 + case + assign $2\full_cr_ok$next[0:0]$7710 $1\full_cr_ok$next[0:0]$7709 + end + sync always + update \full_cr$5$next $0\full_cr$5$next[31:0]$7706 + update \full_cr_ok$next $0\full_cr_ok$next[0:0]$7707 + end + attribute \src "issuer_ls180.v:146118.3-146136.6" + process $proc$issuer_ls180.v:146118$7711 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\cr_a$6$next[3:0]$7713 $1\cr_a$6$next[3:0]$7715 + assign $0\cr_a_ok$next[0:0]$7712 $2\cr_a_ok$next[0:0]$7716 + attribute \src "issuer_ls180.v:146119.5-146119.29" + switch \initial + attribute \src "issuer_ls180.v:146119.9-146119.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'-1 + assign { } { } + assign { } { } + assign { $1\cr_a_ok$next[0:0]$7714 $1\cr_a$6$next[3:0]$7715 } { \cr_a_ok$25 \cr_a$24 } + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'1- + assign { } { } + assign { } { } + assign { $1\cr_a_ok$next[0:0]$7714 $1\cr_a$6$next[3:0]$7715 } { \cr_a_ok$25 \cr_a$24 } + case + assign $1\cr_a_ok$next[0:0]$7714 \cr_a_ok + assign $1\cr_a$6$next[3:0]$7715 \cr_a$6 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\cr_a_ok$next[0:0]$7716 1'0 + case + assign $2\cr_a_ok$next[0:0]$7716 $1\cr_a_ok$next[0:0]$7714 + end + sync always + update \cr_a_ok$next $0\cr_a_ok$next[0:0]$7712 + update \cr_a$6$next $0\cr_a$6$next[3:0]$7713 + end + connect \$14 $and$issuer_ls180.v:145981$7667_Y + connect \p_ready_o \n_i_rdy_data + connect \n_valid_o \r_busy + connect { \cr_a_ok$25 \cr_a$24 } { \main_cr_a_ok \main_cr_a$12 } + connect { \full_cr_ok$23 \full_cr$22 } { \main_full_cr_ok \main_full_cr$11 } + connect { \o_ok$21 \o$20 } { \main_o_ok \main_o } + connect { \cr_op__insn$19 \cr_op__fn_unit$18 \cr_op__insn_type$17 } { \main_cr_op__insn$10 \main_cr_op__fn_unit$9 \main_cr_op__insn_type$8 } + connect \muxid$16 \main_muxid$7 + connect \p_valid_i_p_ready_o \$14 + connect \n_i_rdy_data \n_ready_i + connect \p_valid_i$13 \p_valid_i + connect \main_cr_c \cr_c + connect \main_cr_b \cr_b + connect \main_cr_a \cr_a + connect \main_full_cr \full_cr + connect \main_rb \rb + connect \main_ra \ra + connect { \main_cr_op__insn \main_cr_op__fn_unit \main_cr_op__insn_type } { \cr_op__insn \cr_op__fn_unit \cr_op__insn_type } + connect \main_muxid \muxid +end +attribute \src "issuer_ls180.v:146159.1-147004.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.fus.branch0.alu_branch0.pipe" +attribute \generator "nMigen" +module \pipe$19 + attribute \src "issuer_ls180.v:146904.3-146931.6" + wire width 64 $0\br_op__cia$2$next[63:0]$7771 + attribute \src "issuer_ls180.v:146816.3-146817.43" + wire width 64 $0\br_op__cia$2[63:0]$7745 + attribute \src "issuer_ls180.v:146167.14-146167.51" + wire width 64 $0\br_op__cia$2[63:0]$7809 + attribute \src "issuer_ls180.v:146904.3-146931.6" + wire width 12 $0\br_op__fn_unit$4$next[11:0]$7772 + attribute \src "issuer_ls180.v:146820.3-146821.51" + wire width 12 $0\br_op__fn_unit$4[11:0]$7749 + attribute \src "issuer_ls180.v:146217.14-146217.42" + wire width 12 $0\br_op__fn_unit$4[11:0]$7811 + attribute \src "issuer_ls180.v:146904.3-146931.6" + wire width 64 $0\br_op__imm_data__data$6$next[63:0]$7773 + attribute \src "issuer_ls180.v:146824.3-146825.65" + wire width 64 $0\br_op__imm_data__data$6[63:0]$7753 + attribute \src "issuer_ls180.v:146226.14-146226.62" + wire width 64 $0\br_op__imm_data__data$6[63:0]$7813 + attribute \src "issuer_ls180.v:146904.3-146931.6" + wire $0\br_op__imm_data__ok$7$next[0:0]$7774 + attribute \src "issuer_ls180.v:146826.3-146827.61" + wire $0\br_op__imm_data__ok$7[0:0]$7755 + attribute \src "issuer_ls180.v:146235.7-146235.37" + wire $0\br_op__imm_data__ok$7[0:0]$7815 + attribute \src "issuer_ls180.v:146904.3-146931.6" + wire width 32 $0\br_op__insn$5$next[31:0]$7775 + attribute \src "issuer_ls180.v:146822.3-146823.45" + wire width 32 $0\br_op__insn$5[31:0]$7751 + attribute \src "issuer_ls180.v:146244.14-146244.37" + wire width 32 $0\br_op__insn$5[31:0]$7817 + attribute \src "issuer_ls180.v:146904.3-146931.6" + wire width 7 $0\br_op__insn_type$3$next[6:0]$7776 + attribute \src "issuer_ls180.v:146818.3-146819.55" + wire width 7 $0\br_op__insn_type$3[6:0]$7747 + attribute \src "issuer_ls180.v:146475.13-146475.41" + wire width 7 $0\br_op__insn_type$3[6:0]$7819 + attribute \src "issuer_ls180.v:146904.3-146931.6" + wire $0\br_op__is_32bit$9$next[0:0]$7777 + attribute \src "issuer_ls180.v:146830.3-146831.53" + wire $0\br_op__is_32bit$9[0:0]$7759 + attribute \src "issuer_ls180.v:146484.7-146484.33" + wire $0\br_op__is_32bit$9[0:0]$7821 + attribute \src "issuer_ls180.v:146904.3-146931.6" + wire $0\br_op__lk$8$next[0:0]$7778 + attribute \src "issuer_ls180.v:146828.3-146829.41" + wire $0\br_op__lk$8[0:0]$7757 + attribute \src "issuer_ls180.v:146493.7-146493.27" + wire $0\br_op__lk$8[0:0]$7823 + attribute \src "issuer_ls180.v:146932.3-146950.6" + wire width 64 $0\fast1$10$next[63:0]$7790 + attribute \src "issuer_ls180.v:146812.3-146813.35" + wire width 64 $0\fast1$10[63:0]$7742 + attribute \src "issuer_ls180.v:146506.14-146506.47" + wire width 64 $0\fast1$10[63:0]$7825 + attribute \src "issuer_ls180.v:146932.3-146950.6" + wire $0\fast1_ok$next[0:0]$7791 + attribute \src "issuer_ls180.v:146814.3-146815.33" + wire $0\fast1_ok[0:0] + attribute \src "issuer_ls180.v:146951.3-146969.6" + wire width 64 $0\fast2$11$next[63:0]$7796 + attribute \src "issuer_ls180.v:146808.3-146809.35" + wire width 64 $0\fast2$11[63:0]$7739 + attribute \src "issuer_ls180.v:146522.14-146522.47" + wire width 64 $0\fast2$11[63:0]$7828 + attribute \src "issuer_ls180.v:146951.3-146969.6" + wire $0\fast2_ok$next[0:0]$7797 + attribute \src "issuer_ls180.v:146810.3-146811.33" + wire $0\fast2_ok[0:0] + attribute \src "issuer_ls180.v:146160.7-146160.20" + wire $0\initial[0:0] + attribute \src "issuer_ls180.v:146891.3-146903.6" + wire width 2 $0\muxid$1$next[1:0]$7768 + attribute \src "issuer_ls180.v:146832.3-146833.33" + wire width 2 $0\muxid$1[1:0]$7761 + attribute \src "issuer_ls180.v:146766.13-146766.29" + wire width 2 $0\muxid$1[1:0]$7831 + attribute \src "issuer_ls180.v:146970.3-146988.6" + wire width 64 $0\nia$next[63:0]$7802 + attribute \src "issuer_ls180.v:146804.3-146805.23" + wire width 64 $0\nia[63:0] + attribute \src "issuer_ls180.v:146970.3-146988.6" + wire $0\nia_ok$next[0:0]$7803 + attribute \src "issuer_ls180.v:146806.3-146807.29" + wire $0\nia_ok[0:0] + attribute \src "issuer_ls180.v:146873.3-146890.6" + wire $0\r_busy$next[0:0]$7764 + attribute \src "issuer_ls180.v:146834.3-146835.29" + wire $0\r_busy[0:0] + attribute \src "issuer_ls180.v:146904.3-146931.6" + wire width 64 $1\br_op__cia$2$next[63:0]$7779 + attribute \src "issuer_ls180.v:146904.3-146931.6" + wire width 12 $1\br_op__fn_unit$4$next[11:0]$7780 + attribute \src "issuer_ls180.v:146904.3-146931.6" + wire width 64 $1\br_op__imm_data__data$6$next[63:0]$7781 + attribute \src "issuer_ls180.v:146904.3-146931.6" + wire $1\br_op__imm_data__ok$7$next[0:0]$7782 + attribute \src "issuer_ls180.v:146904.3-146931.6" + wire width 32 $1\br_op__insn$5$next[31:0]$7783 + attribute \src "issuer_ls180.v:146904.3-146931.6" + wire width 7 $1\br_op__insn_type$3$next[6:0]$7784 + attribute \src "issuer_ls180.v:146904.3-146931.6" + wire $1\br_op__is_32bit$9$next[0:0]$7785 + attribute \src "issuer_ls180.v:146904.3-146931.6" + wire $1\br_op__lk$8$next[0:0]$7786 + attribute \src "issuer_ls180.v:146932.3-146950.6" + wire width 64 $1\fast1$10$next[63:0]$7792 + attribute \src "issuer_ls180.v:146932.3-146950.6" + wire $1\fast1_ok$next[0:0]$7793 + attribute \src "issuer_ls180.v:146513.7-146513.22" + wire $1\fast1_ok[0:0] + attribute \src "issuer_ls180.v:146951.3-146969.6" + wire width 64 $1\fast2$11$next[63:0]$7798 + attribute \src "issuer_ls180.v:146951.3-146969.6" + wire $1\fast2_ok$next[0:0]$7799 + attribute \src "issuer_ls180.v:146529.7-146529.22" + wire $1\fast2_ok[0:0] + attribute \src "issuer_ls180.v:146891.3-146903.6" + wire width 2 $1\muxid$1$next[1:0]$7769 + attribute \src "issuer_ls180.v:146970.3-146988.6" + wire width 64 $1\nia$next[63:0]$7804 + attribute \src "issuer_ls180.v:146779.14-146779.40" + wire width 64 $1\nia[63:0] + attribute \src "issuer_ls180.v:146970.3-146988.6" + wire $1\nia_ok$next[0:0]$7805 + attribute \src "issuer_ls180.v:146786.7-146786.20" + wire $1\nia_ok[0:0] + attribute \src "issuer_ls180.v:146873.3-146890.6" + wire $1\r_busy$next[0:0]$7765 + attribute \src "issuer_ls180.v:146800.7-146800.20" + wire $1\r_busy[0:0] + attribute \src "issuer_ls180.v:146904.3-146931.6" + wire width 64 $2\br_op__imm_data__data$6$next[63:0]$7787 + attribute \src "issuer_ls180.v:146904.3-146931.6" + wire $2\br_op__imm_data__ok$7$next[0:0]$7788 + attribute \src "issuer_ls180.v:146932.3-146950.6" + wire $2\fast1_ok$next[0:0]$7794 + attribute \src "issuer_ls180.v:146951.3-146969.6" + wire $2\fast2_ok$next[0:0]$7800 + attribute \src "issuer_ls180.v:146970.3-146988.6" + wire $2\nia_ok$next[0:0]$7806 + attribute \src "issuer_ls180.v:146873.3-146890.6" + wire $2\r_busy$next[0:0]$7766 + attribute \src "issuer_ls180.v:146803.18-146803.118" + wire $and$issuer_ls180.v:146803$7735_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" + wire \$24 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 input 5 \br_op__cia + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 output 19 \br_op__cia$2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \br_op__cia$2$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \br_op__cia$27 + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 input 7 \br_op__fn_unit + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 \br_op__fn_unit$29 + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 output 21 \br_op__fn_unit$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 \br_op__fn_unit$4$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 input 9 \br_op__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \br_op__imm_data__data$31 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 output 23 \br_op__imm_data__data$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \br_op__imm_data__data$6$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 10 \br_op__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \br_op__imm_data__ok$32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 24 \br_op__imm_data__ok$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \br_op__imm_data__ok$7$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 8 \br_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \br_op__insn$30 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 output 22 \br_op__insn$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \br_op__insn$5$next + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 input 6 \br_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \br_op__insn_type$28 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 output 20 \br_op__insn_type$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \br_op__insn_type$3$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 12 \br_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \br_op__is_32bit$34 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 26 \br_op__is_32bit$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \br_op__is_32bit$9$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 11 \br_op__lk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \br_op__lk$33 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 25 \br_op__lk$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \br_op__lk$8$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" + wire input 33 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" + wire input 1 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 4 input 15 \cr_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 13 \fast1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 output 27 \fast1$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 \fast1$10$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 \fast1$35 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 28 \fast1_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \fast1_ok$36 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \fast1_ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 14 \fast2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 output 29 \fast2$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 \fast2$11$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 \fast2$37 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 30 \fast2_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \fast2_ok$38 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \fast2_ok$next + attribute \src "issuer_ls180.v:146160.7-146160.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \main_br_op__cia + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \main_br_op__cia$13 + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 \main_br_op__fn_unit + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 \main_br_op__fn_unit$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \main_br_op__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \main_br_op__imm_data__data$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_br_op__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_br_op__imm_data__ok$18 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \main_br_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \main_br_op__insn$16 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \main_br_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \main_br_op__insn_type$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_br_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_br_op__is_32bit$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_br_op__lk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_br_op__lk$19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 4 \main_cr_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \main_fast1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 \main_fast1$21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \main_fast1_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \main_fast2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 \main_fast2$22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \main_fast2_ok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \main_muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \main_muxid$12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 \main_nia + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \main_nia_ok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 input 4 \muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 output 18 \muxid$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \muxid$1$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \muxid$26 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:619" + wire \n_i_rdy_data + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" + wire input 17 \n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" + wire output 16 \n_valid_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 output 31 \nia + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 \nia$39 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 \nia$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 32 \nia_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \nia_ok$40 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \nia_ok$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" + wire output 3 \p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" + wire input 2 \p_valid_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:621" + wire \p_valid_i$23 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" + wire \p_valid_i_p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615" + wire \r_busy + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615" + wire \r_busy$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" + cell $and $and$issuer_ls180.v:146803$7735 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \p_valid_i$23 + connect \B \p_ready_o + connect \Y $and$issuer_ls180.v:146803$7735_Y + end + attribute \module_not_derived 1 + attribute \src "issuer_ls180.v:146836.13-146864.4" + cell \main$22 \main + connect \br_op__cia \main_br_op__cia + connect \br_op__cia$2 \main_br_op__cia$13 + connect \br_op__fn_unit \main_br_op__fn_unit + connect \br_op__fn_unit$4 \main_br_op__fn_unit$15 + connect \br_op__imm_data__data \main_br_op__imm_data__data + connect \br_op__imm_data__data$6 \main_br_op__imm_data__data$17 + connect \br_op__imm_data__ok \main_br_op__imm_data__ok + connect \br_op__imm_data__ok$7 \main_br_op__imm_data__ok$18 + connect \br_op__insn \main_br_op__insn + connect \br_op__insn$5 \main_br_op__insn$16 + connect \br_op__insn_type \main_br_op__insn_type + connect \br_op__insn_type$3 \main_br_op__insn_type$14 + connect \br_op__is_32bit \main_br_op__is_32bit + connect \br_op__is_32bit$9 \main_br_op__is_32bit$20 + connect \br_op__lk \main_br_op__lk + connect \br_op__lk$8 \main_br_op__lk$19 + connect \cr_a \main_cr_a + connect \fast1 \main_fast1 + connect \fast1$10 \main_fast1$21 + connect \fast1_ok \main_fast1_ok + connect \fast2 \main_fast2 + connect \fast2$11 \main_fast2$22 + connect \fast2_ok \main_fast2_ok + connect \muxid \main_muxid + connect \muxid$1 \main_muxid$12 + connect \nia \main_nia + connect \nia_ok \main_nia_ok + end + attribute \module_not_derived 1 + attribute \src "issuer_ls180.v:146865.10-146868.4" + cell \n$21 \n + connect \n_ready_i \n_ready_i + connect \n_valid_o \n_valid_o + end + attribute \module_not_derived 1 + attribute \src "issuer_ls180.v:146869.10-146872.4" + cell \p$20 \p + connect \p_ready_o \p_ready_o + connect \p_valid_i \p_valid_i + end + attribute \src "issuer_ls180.v:146160.7-146160.20" + process $proc$issuer_ls180.v:146160$7807 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "issuer_ls180.v:146167.14-146167.51" + process $proc$issuer_ls180.v:146167$7808 + assign { } { } + assign $0\br_op__cia$2[63:0]$7809 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \br_op__cia$2 $0\br_op__cia$2[63:0]$7809 + end + attribute \src "issuer_ls180.v:146217.14-146217.42" + process $proc$issuer_ls180.v:146217$7810 + assign { } { } + assign $0\br_op__fn_unit$4[11:0]$7811 12'000000000000 + sync always + sync init + update \br_op__fn_unit$4 $0\br_op__fn_unit$4[11:0]$7811 + end + attribute \src "issuer_ls180.v:146226.14-146226.62" + process $proc$issuer_ls180.v:146226$7812 + assign { } { } + assign $0\br_op__imm_data__data$6[63:0]$7813 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \br_op__imm_data__data$6 $0\br_op__imm_data__data$6[63:0]$7813 + end + attribute \src "issuer_ls180.v:146235.7-146235.37" + process $proc$issuer_ls180.v:146235$7814 + assign { } { } + assign $0\br_op__imm_data__ok$7[0:0]$7815 1'0 + sync always + sync init + update \br_op__imm_data__ok$7 $0\br_op__imm_data__ok$7[0:0]$7815 + end + attribute \src "issuer_ls180.v:146244.14-146244.37" + process $proc$issuer_ls180.v:146244$7816 + assign { } { } + assign $0\br_op__insn$5[31:0]$7817 0 + sync always + sync init + update \br_op__insn$5 $0\br_op__insn$5[31:0]$7817 + end + attribute \src "issuer_ls180.v:146475.13-146475.41" + process $proc$issuer_ls180.v:146475$7818 + assign { } { } + assign $0\br_op__insn_type$3[6:0]$7819 7'0000000 + sync always + sync init + update \br_op__insn_type$3 $0\br_op__insn_type$3[6:0]$7819 + end + attribute \src "issuer_ls180.v:146484.7-146484.33" + process $proc$issuer_ls180.v:146484$7820 + assign { } { } + assign $0\br_op__is_32bit$9[0:0]$7821 1'0 + sync always + sync init + update \br_op__is_32bit$9 $0\br_op__is_32bit$9[0:0]$7821 + end + attribute \src "issuer_ls180.v:146493.7-146493.27" + process $proc$issuer_ls180.v:146493$7822 + assign { } { } + assign $0\br_op__lk$8[0:0]$7823 1'0 + sync always + sync init + update \br_op__lk$8 $0\br_op__lk$8[0:0]$7823 + end + attribute \src "issuer_ls180.v:146506.14-146506.47" + process $proc$issuer_ls180.v:146506$7824 + assign { } { } + assign $0\fast1$10[63:0]$7825 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \fast1$10 $0\fast1$10[63:0]$7825 + end + attribute \src "issuer_ls180.v:146513.7-146513.22" + process $proc$issuer_ls180.v:146513$7826 + assign { } { } + assign $1\fast1_ok[0:0] 1'0 + sync always + sync init + update \fast1_ok $1\fast1_ok[0:0] + end + attribute \src "issuer_ls180.v:146522.14-146522.47" + process $proc$issuer_ls180.v:146522$7827 + assign { } { } + assign $0\fast2$11[63:0]$7828 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \fast2$11 $0\fast2$11[63:0]$7828 + end + attribute \src "issuer_ls180.v:146529.7-146529.22" + process $proc$issuer_ls180.v:146529$7829 + assign { } { } + assign $1\fast2_ok[0:0] 1'0 + sync always + sync init + update \fast2_ok $1\fast2_ok[0:0] + end + attribute \src "issuer_ls180.v:146766.13-146766.29" + process $proc$issuer_ls180.v:146766$7830 + assign { } { } + assign $0\muxid$1[1:0]$7831 2'00 + sync always + sync init + update \muxid$1 $0\muxid$1[1:0]$7831 + end + attribute \src "issuer_ls180.v:146779.14-146779.40" + process $proc$issuer_ls180.v:146779$7832 + assign { } { } + assign $1\nia[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \nia $1\nia[63:0] + end + attribute \src "issuer_ls180.v:146786.7-146786.20" + process $proc$issuer_ls180.v:146786$7833 + assign { } { } + assign $1\nia_ok[0:0] 1'0 + sync always + sync init + update \nia_ok $1\nia_ok[0:0] + end + attribute \src "issuer_ls180.v:146800.7-146800.20" + process $proc$issuer_ls180.v:146800$7834 + assign { } { } + assign $1\r_busy[0:0] 1'0 + sync always + sync init + update \r_busy $1\r_busy[0:0] + end + attribute \src "issuer_ls180.v:146804.3-146805.23" + process $proc$issuer_ls180.v:146804$7736 + assign { } { } + assign $0\nia[63:0] \nia$next + sync posedge \coresync_clk + update \nia $0\nia[63:0] + end + attribute \src "issuer_ls180.v:146806.3-146807.29" + process $proc$issuer_ls180.v:146806$7737 + assign { } { } + assign $0\nia_ok[0:0] \nia_ok$next + sync posedge \coresync_clk + update \nia_ok $0\nia_ok[0:0] + end + attribute \src "issuer_ls180.v:146808.3-146809.35" + process $proc$issuer_ls180.v:146808$7738 + assign { } { } + assign $0\fast2$11[63:0]$7739 \fast2$11$next + sync posedge \coresync_clk + update \fast2$11 $0\fast2$11[63:0]$7739 + end + attribute \src "issuer_ls180.v:146810.3-146811.33" + process $proc$issuer_ls180.v:146810$7740 + assign { } { } + assign $0\fast2_ok[0:0] \fast2_ok$next + sync posedge \coresync_clk + update \fast2_ok $0\fast2_ok[0:0] + end + attribute \src "issuer_ls180.v:146812.3-146813.35" + process $proc$issuer_ls180.v:146812$7741 + assign { } { } + assign $0\fast1$10[63:0]$7742 \fast1$10$next + sync posedge \coresync_clk + update \fast1$10 $0\fast1$10[63:0]$7742 + end + attribute \src "issuer_ls180.v:146814.3-146815.33" + process $proc$issuer_ls180.v:146814$7743 + assign { } { } + assign $0\fast1_ok[0:0] \fast1_ok$next + sync posedge \coresync_clk + update \fast1_ok $0\fast1_ok[0:0] + end + attribute \src "issuer_ls180.v:146816.3-146817.43" + process $proc$issuer_ls180.v:146816$7744 + assign { } { } + assign $0\br_op__cia$2[63:0]$7745 \br_op__cia$2$next + sync posedge \coresync_clk + update \br_op__cia$2 $0\br_op__cia$2[63:0]$7745 + end + attribute \src "issuer_ls180.v:146818.3-146819.55" + process $proc$issuer_ls180.v:146818$7746 + assign { } { } + assign $0\br_op__insn_type$3[6:0]$7747 \br_op__insn_type$3$next + sync posedge \coresync_clk + update \br_op__insn_type$3 $0\br_op__insn_type$3[6:0]$7747 + end + attribute \src "issuer_ls180.v:146820.3-146821.51" + process $proc$issuer_ls180.v:146820$7748 + assign { } { } + assign $0\br_op__fn_unit$4[11:0]$7749 \br_op__fn_unit$4$next + sync posedge \coresync_clk + update \br_op__fn_unit$4 $0\br_op__fn_unit$4[11:0]$7749 + end + attribute \src "issuer_ls180.v:146822.3-146823.45" + process $proc$issuer_ls180.v:146822$7750 + assign { } { } + assign $0\br_op__insn$5[31:0]$7751 \br_op__insn$5$next + sync posedge \coresync_clk + update \br_op__insn$5 $0\br_op__insn$5[31:0]$7751 + end + attribute \src "issuer_ls180.v:146824.3-146825.65" + process $proc$issuer_ls180.v:146824$7752 + assign { } { } + assign $0\br_op__imm_data__data$6[63:0]$7753 \br_op__imm_data__data$6$next + sync posedge \coresync_clk + update \br_op__imm_data__data$6 $0\br_op__imm_data__data$6[63:0]$7753 + end + attribute \src "issuer_ls180.v:146826.3-146827.61" + process $proc$issuer_ls180.v:146826$7754 + assign { } { } + assign $0\br_op__imm_data__ok$7[0:0]$7755 \br_op__imm_data__ok$7$next + sync posedge \coresync_clk + update \br_op__imm_data__ok$7 $0\br_op__imm_data__ok$7[0:0]$7755 + end + attribute \src "issuer_ls180.v:146828.3-146829.41" + process $proc$issuer_ls180.v:146828$7756 + assign { } { } + assign $0\br_op__lk$8[0:0]$7757 \br_op__lk$8$next + sync posedge \coresync_clk + update \br_op__lk$8 $0\br_op__lk$8[0:0]$7757 + end + attribute \src "issuer_ls180.v:146830.3-146831.53" + process $proc$issuer_ls180.v:146830$7758 + assign { } { } + assign $0\br_op__is_32bit$9[0:0]$7759 \br_op__is_32bit$9$next + sync posedge \coresync_clk + update \br_op__is_32bit$9 $0\br_op__is_32bit$9[0:0]$7759 + end + attribute \src "issuer_ls180.v:146832.3-146833.33" + process $proc$issuer_ls180.v:146832$7760 + assign { } { } + assign $0\muxid$1[1:0]$7761 \muxid$1$next + sync posedge \coresync_clk + update \muxid$1 $0\muxid$1[1:0]$7761 + end + attribute \src "issuer_ls180.v:146834.3-146835.29" + process $proc$issuer_ls180.v:146834$7762 + assign { } { } + assign $0\r_busy[0:0] \r_busy$next + sync posedge \coresync_clk + update \r_busy $0\r_busy[0:0] + end + attribute \src "issuer_ls180.v:146873.3-146890.6" + process $proc$issuer_ls180.v:146873$7763 + assign { } { } + assign { } { } + assign { } { } + assign $0\r_busy$next[0:0]$7764 $2\r_busy$next[0:0]$7766 + attribute \src "issuer_ls180.v:146874.5-146874.29" + switch \initial + attribute \src "issuer_ls180.v:146874.9-146874.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\r_busy$next[0:0]$7765 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\r_busy$next[0:0]$7765 1'0 + case + assign $1\r_busy$next[0:0]$7765 \r_busy + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\r_busy$next[0:0]$7766 1'0 + case + assign $2\r_busy$next[0:0]$7766 $1\r_busy$next[0:0]$7765 + end + sync always + update \r_busy$next $0\r_busy$next[0:0]$7764 + end + attribute \src "issuer_ls180.v:146891.3-146903.6" + process $proc$issuer_ls180.v:146891$7767 + assign { } { } + assign { } { } + assign $0\muxid$1$next[1:0]$7768 $1\muxid$1$next[1:0]$7769 + attribute \src "issuer_ls180.v:146892.5-146892.29" + switch \initial + attribute \src "issuer_ls180.v:146892.9-146892.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\muxid$1$next[1:0]$7769 \muxid$26 + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\muxid$1$next[1:0]$7769 \muxid$26 + case + assign $1\muxid$1$next[1:0]$7769 \muxid$1 + end + sync always + update \muxid$1$next $0\muxid$1$next[1:0]$7768 + end + attribute \src "issuer_ls180.v:146904.3-146931.6" + process $proc$issuer_ls180.v:146904$7770 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\br_op__cia$2$next[63:0]$7771 $1\br_op__cia$2$next[63:0]$7779 + assign $0\br_op__fn_unit$4$next[11:0]$7772 $1\br_op__fn_unit$4$next[11:0]$7780 + assign { } { } + assign { } { } + assign $0\br_op__insn$5$next[31:0]$7775 $1\br_op__insn$5$next[31:0]$7783 + assign $0\br_op__insn_type$3$next[6:0]$7776 $1\br_op__insn_type$3$next[6:0]$7784 + assign $0\br_op__is_32bit$9$next[0:0]$7777 $1\br_op__is_32bit$9$next[0:0]$7785 + assign $0\br_op__lk$8$next[0:0]$7778 $1\br_op__lk$8$next[0:0]$7786 + assign $0\br_op__imm_data__data$6$next[63:0]$7773 $2\br_op__imm_data__data$6$next[63:0]$7787 + assign $0\br_op__imm_data__ok$7$next[0:0]$7774 $2\br_op__imm_data__ok$7$next[0:0]$7788 + attribute \src "issuer_ls180.v:146905.5-146905.29" + switch \initial + attribute \src "issuer_ls180.v:146905.9-146905.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'-1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { $1\br_op__is_32bit$9$next[0:0]$7785 $1\br_op__lk$8$next[0:0]$7786 $1\br_op__imm_data__ok$7$next[0:0]$7782 $1\br_op__imm_data__data$6$next[63:0]$7781 $1\br_op__insn$5$next[31:0]$7783 $1\br_op__fn_unit$4$next[11:0]$7780 $1\br_op__insn_type$3$next[6:0]$7784 $1\br_op__cia$2$next[63:0]$7779 } { \br_op__is_32bit$34 \br_op__lk$33 \br_op__imm_data__ok$32 \br_op__imm_data__data$31 \br_op__insn$30 \br_op__fn_unit$29 \br_op__insn_type$28 \br_op__cia$27 } + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'1- + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { $1\br_op__is_32bit$9$next[0:0]$7785 $1\br_op__lk$8$next[0:0]$7786 $1\br_op__imm_data__ok$7$next[0:0]$7782 $1\br_op__imm_data__data$6$next[63:0]$7781 $1\br_op__insn$5$next[31:0]$7783 $1\br_op__fn_unit$4$next[11:0]$7780 $1\br_op__insn_type$3$next[6:0]$7784 $1\br_op__cia$2$next[63:0]$7779 } { \br_op__is_32bit$34 \br_op__lk$33 \br_op__imm_data__ok$32 \br_op__imm_data__data$31 \br_op__insn$30 \br_op__fn_unit$29 \br_op__insn_type$28 \br_op__cia$27 } + case + assign $1\br_op__cia$2$next[63:0]$7779 \br_op__cia$2 + assign $1\br_op__fn_unit$4$next[11:0]$7780 \br_op__fn_unit$4 + assign $1\br_op__imm_data__data$6$next[63:0]$7781 \br_op__imm_data__data$6 + assign $1\br_op__imm_data__ok$7$next[0:0]$7782 \br_op__imm_data__ok$7 + assign $1\br_op__insn$5$next[31:0]$7783 \br_op__insn$5 + assign $1\br_op__insn_type$3$next[6:0]$7784 \br_op__insn_type$3 + assign $1\br_op__is_32bit$9$next[0:0]$7785 \br_op__is_32bit$9 + assign $1\br_op__lk$8$next[0:0]$7786 \br_op__lk$8 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign $2\br_op__imm_data__data$6$next[63:0]$7787 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\br_op__imm_data__ok$7$next[0:0]$7788 1'0 + case + assign $2\br_op__imm_data__data$6$next[63:0]$7787 $1\br_op__imm_data__data$6$next[63:0]$7781 + assign $2\br_op__imm_data__ok$7$next[0:0]$7788 $1\br_op__imm_data__ok$7$next[0:0]$7782 + end + sync always + update \br_op__cia$2$next $0\br_op__cia$2$next[63:0]$7771 + update \br_op__fn_unit$4$next $0\br_op__fn_unit$4$next[11:0]$7772 + update \br_op__imm_data__data$6$next $0\br_op__imm_data__data$6$next[63:0]$7773 + update \br_op__imm_data__ok$7$next $0\br_op__imm_data__ok$7$next[0:0]$7774 + update \br_op__insn$5$next $0\br_op__insn$5$next[31:0]$7775 + update \br_op__insn_type$3$next $0\br_op__insn_type$3$next[6:0]$7776 + update \br_op__is_32bit$9$next $0\br_op__is_32bit$9$next[0:0]$7777 + update \br_op__lk$8$next $0\br_op__lk$8$next[0:0]$7778 + end + attribute \src "issuer_ls180.v:146932.3-146950.6" + process $proc$issuer_ls180.v:146932$7789 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\fast1$10$next[63:0]$7790 $1\fast1$10$next[63:0]$7792 + assign { } { } + assign $0\fast1_ok$next[0:0]$7791 $2\fast1_ok$next[0:0]$7794 + attribute \src "issuer_ls180.v:146933.5-146933.29" + switch \initial + attribute \src "issuer_ls180.v:146933.9-146933.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'-1 + assign { } { } + assign { } { } + assign { $1\fast1_ok$next[0:0]$7793 $1\fast1$10$next[63:0]$7792 } { \fast1_ok$36 \fast1$35 } + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'1- + assign { } { } + assign { } { } + assign { $1\fast1_ok$next[0:0]$7793 $1\fast1$10$next[63:0]$7792 } { \fast1_ok$36 \fast1$35 } + case + assign $1\fast1$10$next[63:0]$7792 \fast1$10 + assign $1\fast1_ok$next[0:0]$7793 \fast1_ok + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\fast1_ok$next[0:0]$7794 1'0 + case + assign $2\fast1_ok$next[0:0]$7794 $1\fast1_ok$next[0:0]$7793 + end + sync always + update \fast1$10$next $0\fast1$10$next[63:0]$7790 + update \fast1_ok$next $0\fast1_ok$next[0:0]$7791 + end + attribute \src "issuer_ls180.v:146951.3-146969.6" + process $proc$issuer_ls180.v:146951$7795 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\fast2$11$next[63:0]$7796 $1\fast2$11$next[63:0]$7798 + assign { } { } + assign $0\fast2_ok$next[0:0]$7797 $2\fast2_ok$next[0:0]$7800 + attribute \src "issuer_ls180.v:146952.5-146952.29" + switch \initial + attribute \src "issuer_ls180.v:146952.9-146952.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'-1 + assign { } { } + assign { } { } + assign { $1\fast2_ok$next[0:0]$7799 $1\fast2$11$next[63:0]$7798 } { \fast2_ok$38 \fast2$37 } + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'1- + assign { } { } + assign { } { } + assign { $1\fast2_ok$next[0:0]$7799 $1\fast2$11$next[63:0]$7798 } { \fast2_ok$38 \fast2$37 } + case + assign $1\fast2$11$next[63:0]$7798 \fast2$11 + assign $1\fast2_ok$next[0:0]$7799 \fast2_ok + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\fast2_ok$next[0:0]$7800 1'0 + case + assign $2\fast2_ok$next[0:0]$7800 $1\fast2_ok$next[0:0]$7799 + end + sync always + update \fast2$11$next $0\fast2$11$next[63:0]$7796 + update \fast2_ok$next $0\fast2_ok$next[0:0]$7797 + end + attribute \src "issuer_ls180.v:146970.3-146988.6" + process $proc$issuer_ls180.v:146970$7801 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\nia$next[63:0]$7802 $1\nia$next[63:0]$7804 + assign { } { } + assign $0\nia_ok$next[0:0]$7803 $2\nia_ok$next[0:0]$7806 + attribute \src "issuer_ls180.v:146971.5-146971.29" + switch \initial + attribute \src "issuer_ls180.v:146971.9-146971.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'-1 + assign { } { } + assign { } { } + assign { $1\nia_ok$next[0:0]$7805 $1\nia$next[63:0]$7804 } { \nia_ok$40 \nia$39 } + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'1- + assign { } { } + assign { } { } + assign { $1\nia_ok$next[0:0]$7805 $1\nia$next[63:0]$7804 } { \nia_ok$40 \nia$39 } + case + assign $1\nia$next[63:0]$7804 \nia + assign $1\nia_ok$next[0:0]$7805 \nia_ok + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\nia_ok$next[0:0]$7806 1'0 + case + assign $2\nia_ok$next[0:0]$7806 $1\nia_ok$next[0:0]$7805 + end + sync always + update \nia$next $0\nia$next[63:0]$7802 + update \nia_ok$next $0\nia_ok$next[0:0]$7803 + end + connect \$24 $and$issuer_ls180.v:146803$7735_Y + connect \p_ready_o \n_i_rdy_data + connect \n_valid_o \r_busy + connect { \nia_ok$40 \nia$39 } { \main_nia_ok \main_nia } + connect { \fast2_ok$38 \fast2$37 } { \main_fast2_ok \main_fast2$22 } + connect { \fast1_ok$36 \fast1$35 } { \main_fast1_ok \main_fast1$21 } + connect { \br_op__is_32bit$34 \br_op__lk$33 \br_op__imm_data__ok$32 \br_op__imm_data__data$31 \br_op__insn$30 \br_op__fn_unit$29 \br_op__insn_type$28 \br_op__cia$27 } { \main_br_op__is_32bit$20 \main_br_op__lk$19 \main_br_op__imm_data__ok$18 \main_br_op__imm_data__data$17 \main_br_op__insn$16 \main_br_op__fn_unit$15 \main_br_op__insn_type$14 \main_br_op__cia$13 } + connect \muxid$26 \main_muxid$12 + connect \p_valid_i_p_ready_o \$24 + connect \n_i_rdy_data \n_ready_i + connect \p_valid_i$23 \p_valid_i + connect \main_cr_a \cr_a + connect \main_fast2 \fast2 + connect \main_fast1 \fast1 + connect { \main_br_op__is_32bit \main_br_op__lk \main_br_op__imm_data__ok \main_br_op__imm_data__data \main_br_op__insn \main_br_op__fn_unit \main_br_op__insn_type \main_br_op__cia } { \br_op__is_32bit \br_op__lk \br_op__imm_data__ok \br_op__imm_data__data \br_op__insn \br_op__fn_unit \br_op__insn_type \br_op__cia } + connect \main_muxid \muxid +end +attribute \src "issuer_ls180.v:147008.1-147939.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.fus.trap0.alu_trap0.pipe" +attribute \generator "nMigen" +module \pipe$32 + attribute \src "issuer_ls180.v:147845.3-147863.6" + wire width 64 $0\fast1$10$next[63:0]$7898 + attribute \src "issuer_ls180.v:147705.3-147706.35" + wire width 64 $0\fast1$10[63:0]$7844 + attribute \src "issuer_ls180.v:147020.14-147020.47" + wire width 64 $0\fast1$10[63:0]$7923 + attribute \src "issuer_ls180.v:147845.3-147863.6" + wire $0\fast1_ok$next[0:0]$7899 + attribute \src "issuer_ls180.v:147707.3-147708.33" + wire $0\fast1_ok[0:0] + attribute \src "issuer_ls180.v:147864.3-147882.6" + wire width 64 $0\fast2$11$next[63:0]$7904 + attribute \src "issuer_ls180.v:147701.3-147702.35" + wire width 64 $0\fast2$11[63:0]$7841 + attribute \src "issuer_ls180.v:147036.14-147036.47" + wire width 64 $0\fast2$11[63:0]$7926 + attribute \src "issuer_ls180.v:147864.3-147882.6" + wire $0\fast2_ok$next[0:0]$7905 + attribute \src "issuer_ls180.v:147703.3-147704.33" + wire $0\fast2_ok[0:0] + attribute \src "issuer_ls180.v:147009.7-147009.20" + wire $0\initial[0:0] + attribute \src "issuer_ls180.v:147902.3-147920.6" + wire width 64 $0\msr$next[63:0]$7916 + attribute \src "issuer_ls180.v:147693.3-147694.23" + wire width 64 $0\msr[63:0] + attribute \src "issuer_ls180.v:147902.3-147920.6" + wire $0\msr_ok$next[0:0]$7917 + attribute \src "issuer_ls180.v:147695.3-147696.29" + wire $0\msr_ok[0:0] + attribute \src "issuer_ls180.v:147793.3-147805.6" + wire width 2 $0\muxid$1$next[1:0]$7872 + attribute \src "issuer_ls180.v:147729.3-147730.33" + wire width 2 $0\muxid$1[1:0]$7865 + attribute \src "issuer_ls180.v:147304.13-147304.29" + wire width 2 $0\muxid$1[1:0]$7931 + attribute \src "issuer_ls180.v:147883.3-147901.6" + wire width 64 $0\nia$next[63:0]$7910 + attribute \src "issuer_ls180.v:147697.3-147698.23" + wire width 64 $0\nia[63:0] + attribute \src "issuer_ls180.v:147883.3-147901.6" + wire $0\nia_ok$next[0:0]$7911 + attribute \src "issuer_ls180.v:147699.3-147700.29" + wire $0\nia_ok[0:0] + attribute \src "issuer_ls180.v:147826.3-147844.6" + wire width 64 $0\o$next[63:0]$7892 + attribute \src "issuer_ls180.v:147709.3-147710.19" + wire width 64 $0\o[63:0] + attribute \src "issuer_ls180.v:147826.3-147844.6" + wire $0\o_ok$next[0:0]$7893 + attribute \src "issuer_ls180.v:147711.3-147712.25" + wire $0\o_ok[0:0] + attribute \src "issuer_ls180.v:147775.3-147792.6" + wire $0\r_busy$next[0:0]$7868 + attribute \src "issuer_ls180.v:147731.3-147732.29" + wire $0\r_busy[0:0] + attribute \src "issuer_ls180.v:147806.3-147825.6" + wire width 64 $0\trap_op__cia$6$next[63:0]$7875 + attribute \src "issuer_ls180.v:147721.3-147722.47" + wire width 64 $0\trap_op__cia$6[63:0]$7857 + attribute \src "issuer_ls180.v:147365.14-147365.53" + wire width 64 $0\trap_op__cia$6[63:0]$7938 + attribute \src "issuer_ls180.v:147806.3-147825.6" + wire width 12 $0\trap_op__fn_unit$3$next[11:0]$7876 + attribute \src "issuer_ls180.v:147715.3-147716.55" + wire width 12 $0\trap_op__fn_unit$3[11:0]$7851 + attribute \src "issuer_ls180.v:147413.14-147413.44" + wire width 12 $0\trap_op__fn_unit$3[11:0]$7940 + attribute \src "issuer_ls180.v:147806.3-147825.6" + wire width 32 $0\trap_op__insn$4$next[31:0]$7877 + attribute \src "issuer_ls180.v:147717.3-147718.49" + wire width 32 $0\trap_op__insn$4[31:0]$7853 + attribute \src "issuer_ls180.v:147422.14-147422.39" + wire width 32 $0\trap_op__insn$4[31:0]$7942 + attribute \src "issuer_ls180.v:147806.3-147825.6" + wire width 7 $0\trap_op__insn_type$2$next[6:0]$7878 + attribute \src "issuer_ls180.v:147713.3-147714.59" + wire width 7 $0\trap_op__insn_type$2[6:0]$7849 + attribute \src "issuer_ls180.v:147577.13-147577.43" + wire width 7 $0\trap_op__insn_type$2[6:0]$7944 + attribute \src "issuer_ls180.v:147806.3-147825.6" + wire $0\trap_op__is_32bit$7$next[0:0]$7879 + attribute \src "issuer_ls180.v:147723.3-147724.57" + wire $0\trap_op__is_32bit$7[0:0]$7859 + attribute \src "issuer_ls180.v:147662.7-147662.35" + wire $0\trap_op__is_32bit$7[0:0]$7946 + attribute \src "issuer_ls180.v:147806.3-147825.6" + wire width 64 $0\trap_op__msr$5$next[63:0]$7880 + attribute \src "issuer_ls180.v:147719.3-147720.47" + wire width 64 $0\trap_op__msr$5[63:0]$7855 + attribute \src "issuer_ls180.v:147671.14-147671.53" + wire width 64 $0\trap_op__msr$5[63:0]$7948 + attribute \src "issuer_ls180.v:147806.3-147825.6" + wire width 13 $0\trap_op__trapaddr$9$next[12:0]$7881 + attribute \src "issuer_ls180.v:147727.3-147728.57" + wire width 13 $0\trap_op__trapaddr$9[12:0]$7863 + attribute \src "issuer_ls180.v:147680.14-147680.46" + wire width 13 $0\trap_op__trapaddr$9[12:0]$7950 + attribute \src "issuer_ls180.v:147806.3-147825.6" + wire width 7 $0\trap_op__traptype$8$next[6:0]$7882 + attribute \src "issuer_ls180.v:147725.3-147726.57" + wire width 7 $0\trap_op__traptype$8[6:0]$7861 + attribute \src "issuer_ls180.v:147689.13-147689.42" + wire width 7 $0\trap_op__traptype$8[6:0]$7952 + attribute \src "issuer_ls180.v:147845.3-147863.6" + wire width 64 $1\fast1$10$next[63:0]$7900 + attribute \src "issuer_ls180.v:147845.3-147863.6" + wire $1\fast1_ok$next[0:0]$7901 + attribute \src "issuer_ls180.v:147027.7-147027.22" + wire $1\fast1_ok[0:0] + attribute \src "issuer_ls180.v:147864.3-147882.6" + wire width 64 $1\fast2$11$next[63:0]$7906 + attribute \src "issuer_ls180.v:147864.3-147882.6" + wire $1\fast2_ok$next[0:0]$7907 + attribute \src "issuer_ls180.v:147043.7-147043.22" + wire $1\fast2_ok[0:0] + attribute \src "issuer_ls180.v:147902.3-147920.6" + wire width 64 $1\msr$next[63:0]$7918 + attribute \src "issuer_ls180.v:147288.14-147288.40" + wire width 64 $1\msr[63:0] + attribute \src "issuer_ls180.v:147902.3-147920.6" + wire $1\msr_ok$next[0:0]$7919 + attribute \src "issuer_ls180.v:147295.7-147295.20" + wire $1\msr_ok[0:0] + attribute \src "issuer_ls180.v:147793.3-147805.6" + wire width 2 $1\muxid$1$next[1:0]$7873 + attribute \src "issuer_ls180.v:147883.3-147901.6" + wire width 64 $1\nia$next[63:0]$7912 + attribute \src "issuer_ls180.v:147317.14-147317.40" + wire width 64 $1\nia[63:0] + attribute \src "issuer_ls180.v:147883.3-147901.6" + wire $1\nia_ok$next[0:0]$7913 + attribute \src "issuer_ls180.v:147324.7-147324.20" + wire $1\nia_ok[0:0] + attribute \src "issuer_ls180.v:147826.3-147844.6" + wire width 64 $1\o$next[63:0]$7894 + attribute \src "issuer_ls180.v:147331.14-147331.38" + wire width 64 $1\o[63:0] + attribute \src "issuer_ls180.v:147826.3-147844.6" + wire $1\o_ok$next[0:0]$7895 + attribute \src "issuer_ls180.v:147338.7-147338.18" + wire $1\o_ok[0:0] + attribute \src "issuer_ls180.v:147775.3-147792.6" + wire $1\r_busy$next[0:0]$7869 + attribute \src "issuer_ls180.v:147352.7-147352.20" + wire $1\r_busy[0:0] + attribute \src "issuer_ls180.v:147806.3-147825.6" + wire width 64 $1\trap_op__cia$6$next[63:0]$7883 + attribute \src "issuer_ls180.v:147806.3-147825.6" + wire width 12 $1\trap_op__fn_unit$3$next[11:0]$7884 + attribute \src "issuer_ls180.v:147806.3-147825.6" + wire width 32 $1\trap_op__insn$4$next[31:0]$7885 + attribute \src "issuer_ls180.v:147806.3-147825.6" + wire width 7 $1\trap_op__insn_type$2$next[6:0]$7886 + attribute \src "issuer_ls180.v:147806.3-147825.6" + wire $1\trap_op__is_32bit$7$next[0:0]$7887 + attribute \src "issuer_ls180.v:147806.3-147825.6" + wire width 64 $1\trap_op__msr$5$next[63:0]$7888 + attribute \src "issuer_ls180.v:147806.3-147825.6" + wire width 13 $1\trap_op__trapaddr$9$next[12:0]$7889 + attribute \src "issuer_ls180.v:147806.3-147825.6" + wire width 7 $1\trap_op__traptype$8$next[6:0]$7890 + attribute \src "issuer_ls180.v:147845.3-147863.6" + wire $2\fast1_ok$next[0:0]$7902 + attribute \src "issuer_ls180.v:147864.3-147882.6" + wire $2\fast2_ok$next[0:0]$7908 + attribute \src "issuer_ls180.v:147902.3-147920.6" + wire $2\msr_ok$next[0:0]$7920 + attribute \src "issuer_ls180.v:147883.3-147901.6" + wire $2\nia_ok$next[0:0]$7914 + attribute \src "issuer_ls180.v:147826.3-147844.6" + wire $2\o_ok$next[0:0]$7896 + attribute \src "issuer_ls180.v:147775.3-147792.6" + wire $2\r_busy$next[0:0]$7870 + attribute \src "issuer_ls180.v:147692.18-147692.118" + wire $and$issuer_ls180.v:147692$7835_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" + wire \$24 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" + wire input 38 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" + wire input 1 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 15 \fast1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 output 30 \fast1$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 \fast1$10$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 \fast1$37 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 31 \fast1_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \fast1_ok$38 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \fast1_ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 16 \fast2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 output 32 \fast2$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 \fast2$11$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 \fast2$39 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 33 \fast2_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \fast2_ok$40 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \fast2_ok$next + attribute \src "issuer_ls180.v:147009.7-147009.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \main_fast1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 \main_fast1$21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \main_fast1_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \main_fast2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 \main_fast2$22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \main_fast2_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 \main_msr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \main_msr_ok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \main_muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \main_muxid$12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 \main_nia + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \main_nia_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 \main_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \main_o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \main_ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \main_rb + attribute \src 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13 \main_trap_op__trapaddr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 13 \main_trap_op__trapaddr$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \main_trap_op__traptype + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \main_trap_op__traptype$19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 output 36 \msr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 \msr$43 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 \msr$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 37 \msr_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \msr_ok$44 + attribute \src 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\enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 input 5 \trap_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 output 20 \trap_op__insn_type$2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \trap_op__insn_type$2$next + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \trap_op__insn_type$27 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 10 \trap_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \trap_op__is_32bit$32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 25 \trap_op__is_32bit$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \trap_op__is_32bit$7$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 input 8 \trap_op__msr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \trap_op__msr$30 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 output 23 \trap_op__msr$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \trap_op__msr$5$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 13 input 12 \trap_op__trapaddr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 13 \trap_op__trapaddr$34 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 13 output 27 \trap_op__trapaddr$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 13 \trap_op__trapaddr$9$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 input 11 \trap_op__traptype + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \trap_op__traptype$33 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 output 26 \trap_op__traptype$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \trap_op__traptype$8$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" + cell $and $and$issuer_ls180.v:147692$7835 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \p_valid_i$23 + connect \B \p_ready_o + connect \Y $and$issuer_ls180.v:147692$7835_Y + end + attribute \module_not_derived 1 + attribute \src "issuer_ls180.v:147733.13-147766.4" + cell \main$35 \main + connect \fast1 \main_fast1 + connect \fast1$10 \main_fast1$21 + connect \fast1_ok \main_fast1_ok + connect \fast2 \main_fast2 + connect \fast2$11 \main_fast2$22 + connect \fast2_ok \main_fast2_ok + connect \msr \main_msr + connect \msr_ok \main_msr_ok + connect \muxid \main_muxid + connect \muxid$1 \main_muxid$12 + connect \nia \main_nia + connect \nia_ok \main_nia_ok + connect \o \main_o + connect \o_ok \main_o_ok + connect \ra \main_ra + connect \rb \main_rb + connect \trap_op__cia \main_trap_op__cia + connect \trap_op__cia$6 \main_trap_op__cia$17 + connect \trap_op__fn_unit \main_trap_op__fn_unit + connect \trap_op__fn_unit$3 \main_trap_op__fn_unit$14 + connect \trap_op__insn \main_trap_op__insn + connect \trap_op__insn$4 \main_trap_op__insn$15 + connect \trap_op__insn_type \main_trap_op__insn_type + connect \trap_op__insn_type$2 \main_trap_op__insn_type$13 + connect \trap_op__is_32bit \main_trap_op__is_32bit + connect \trap_op__is_32bit$7 \main_trap_op__is_32bit$18 + connect \trap_op__msr \main_trap_op__msr + connect \trap_op__msr$5 \main_trap_op__msr$16 + connect \trap_op__trapaddr \main_trap_op__trapaddr + connect \trap_op__trapaddr$9 \main_trap_op__trapaddr$20 + connect \trap_op__traptype \main_trap_op__traptype + connect \trap_op__traptype$8 \main_trap_op__traptype$19 + end + attribute \module_not_derived 1 + attribute \src "issuer_ls180.v:147767.10-147770.4" + cell \n$34 \n + connect \n_ready_i \n_ready_i + connect \n_valid_o \n_valid_o + end + attribute \module_not_derived 1 + attribute \src "issuer_ls180.v:147771.10-147774.4" + cell \p$33 \p + connect \p_ready_o \p_ready_o + connect \p_valid_i \p_valid_i + end + attribute \src "issuer_ls180.v:147009.7-147009.20" + process $proc$issuer_ls180.v:147009$7921 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "issuer_ls180.v:147020.14-147020.47" + process $proc$issuer_ls180.v:147020$7922 + assign { } { } + assign $0\fast1$10[63:0]$7923 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \fast1$10 $0\fast1$10[63:0]$7923 + end + attribute \src "issuer_ls180.v:147027.7-147027.22" + process $proc$issuer_ls180.v:147027$7924 + assign { } { } + assign $1\fast1_ok[0:0] 1'0 + sync always + sync init + update \fast1_ok $1\fast1_ok[0:0] + end + attribute \src "issuer_ls180.v:147036.14-147036.47" + process $proc$issuer_ls180.v:147036$7925 + assign { } { } + assign $0\fast2$11[63:0]$7926 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \fast2$11 $0\fast2$11[63:0]$7926 + end + attribute \src "issuer_ls180.v:147043.7-147043.22" + process $proc$issuer_ls180.v:147043$7927 + assign { } { } + assign $1\fast2_ok[0:0] 1'0 + sync always + sync init + update \fast2_ok $1\fast2_ok[0:0] + end + attribute \src "issuer_ls180.v:147288.14-147288.40" + process $proc$issuer_ls180.v:147288$7928 + assign { } { } + assign $1\msr[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \msr $1\msr[63:0] + end + attribute \src "issuer_ls180.v:147295.7-147295.20" + process $proc$issuer_ls180.v:147295$7929 + assign { } { } + assign $1\msr_ok[0:0] 1'0 + sync always + sync init + update \msr_ok $1\msr_ok[0:0] + end + attribute \src "issuer_ls180.v:147304.13-147304.29" + process $proc$issuer_ls180.v:147304$7930 + assign { } { } + assign $0\muxid$1[1:0]$7931 2'00 + sync always + sync init + update \muxid$1 $0\muxid$1[1:0]$7931 + end + attribute \src "issuer_ls180.v:147317.14-147317.40" + process $proc$issuer_ls180.v:147317$7932 + assign { } { } + assign $1\nia[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \nia $1\nia[63:0] + end + attribute \src "issuer_ls180.v:147324.7-147324.20" + process $proc$issuer_ls180.v:147324$7933 + assign { } { } + assign $1\nia_ok[0:0] 1'0 + sync always + sync init + update \nia_ok $1\nia_ok[0:0] + end + attribute \src "issuer_ls180.v:147331.14-147331.38" + process $proc$issuer_ls180.v:147331$7934 + assign { } { } + assign $1\o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \o $1\o[63:0] + end + attribute \src "issuer_ls180.v:147338.7-147338.18" + process $proc$issuer_ls180.v:147338$7935 + assign { } { } + assign $1\o_ok[0:0] 1'0 + sync always + sync init + update \o_ok $1\o_ok[0:0] + end + attribute \src "issuer_ls180.v:147352.7-147352.20" + process $proc$issuer_ls180.v:147352$7936 + assign { } { } + assign $1\r_busy[0:0] 1'0 + sync always + sync init + update \r_busy $1\r_busy[0:0] + end + attribute \src "issuer_ls180.v:147365.14-147365.53" + process $proc$issuer_ls180.v:147365$7937 + assign { } { } + assign $0\trap_op__cia$6[63:0]$7938 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \trap_op__cia$6 $0\trap_op__cia$6[63:0]$7938 + end + attribute \src "issuer_ls180.v:147413.14-147413.44" + process $proc$issuer_ls180.v:147413$7939 + assign { } { } + assign $0\trap_op__fn_unit$3[11:0]$7940 12'000000000000 + sync always + sync init + update \trap_op__fn_unit$3 $0\trap_op__fn_unit$3[11:0]$7940 + end + attribute \src "issuer_ls180.v:147422.14-147422.39" + process $proc$issuer_ls180.v:147422$7941 + assign { } { } + assign $0\trap_op__insn$4[31:0]$7942 0 + sync always + sync init + update \trap_op__insn$4 $0\trap_op__insn$4[31:0]$7942 + end + attribute \src "issuer_ls180.v:147577.13-147577.43" + process $proc$issuer_ls180.v:147577$7943 + assign { } { } + assign $0\trap_op__insn_type$2[6:0]$7944 7'0000000 + sync always + sync init + update \trap_op__insn_type$2 $0\trap_op__insn_type$2[6:0]$7944 + end + attribute \src "issuer_ls180.v:147662.7-147662.35" + process $proc$issuer_ls180.v:147662$7945 + assign { } { } + assign $0\trap_op__is_32bit$7[0:0]$7946 1'0 + sync always + sync init + update \trap_op__is_32bit$7 $0\trap_op__is_32bit$7[0:0]$7946 + end + attribute \src "issuer_ls180.v:147671.14-147671.53" + process $proc$issuer_ls180.v:147671$7947 + assign { } { } + assign $0\trap_op__msr$5[63:0]$7948 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \trap_op__msr$5 $0\trap_op__msr$5[63:0]$7948 + end + attribute \src "issuer_ls180.v:147680.14-147680.46" + process $proc$issuer_ls180.v:147680$7949 + assign { } { } + assign $0\trap_op__trapaddr$9[12:0]$7950 13'0000000000000 + sync always + sync init + update \trap_op__trapaddr$9 $0\trap_op__trapaddr$9[12:0]$7950 + end + attribute \src "issuer_ls180.v:147689.13-147689.42" + process $proc$issuer_ls180.v:147689$7951 + assign { } { } + assign $0\trap_op__traptype$8[6:0]$7952 7'0000000 + sync always + sync init + update \trap_op__traptype$8 $0\trap_op__traptype$8[6:0]$7952 + end + attribute \src "issuer_ls180.v:147693.3-147694.23" + process $proc$issuer_ls180.v:147693$7836 + assign { } { } + assign $0\msr[63:0] \msr$next + sync posedge \coresync_clk + update \msr $0\msr[63:0] + end + attribute \src "issuer_ls180.v:147695.3-147696.29" + process $proc$issuer_ls180.v:147695$7837 + assign { } { } + assign $0\msr_ok[0:0] \msr_ok$next + sync posedge \coresync_clk + update \msr_ok $0\msr_ok[0:0] + end + attribute \src "issuer_ls180.v:147697.3-147698.23" + process $proc$issuer_ls180.v:147697$7838 + assign { } { } + assign $0\nia[63:0] \nia$next + sync posedge \coresync_clk + update \nia $0\nia[63:0] + end + attribute \src "issuer_ls180.v:147699.3-147700.29" + process $proc$issuer_ls180.v:147699$7839 + assign { } { } + assign $0\nia_ok[0:0] \nia_ok$next + sync posedge \coresync_clk + update \nia_ok $0\nia_ok[0:0] + end + attribute \src "issuer_ls180.v:147701.3-147702.35" + process $proc$issuer_ls180.v:147701$7840 + assign { } { } + assign $0\fast2$11[63:0]$7841 \fast2$11$next + sync posedge \coresync_clk + update \fast2$11 $0\fast2$11[63:0]$7841 + end + attribute \src "issuer_ls180.v:147703.3-147704.33" + process $proc$issuer_ls180.v:147703$7842 + assign { } { } + assign $0\fast2_ok[0:0] \fast2_ok$next + sync posedge \coresync_clk + update \fast2_ok $0\fast2_ok[0:0] + end + attribute \src "issuer_ls180.v:147705.3-147706.35" + process $proc$issuer_ls180.v:147705$7843 + assign { } { } + assign $0\fast1$10[63:0]$7844 \fast1$10$next + sync posedge \coresync_clk + update \fast1$10 $0\fast1$10[63:0]$7844 + end + attribute \src "issuer_ls180.v:147707.3-147708.33" + process $proc$issuer_ls180.v:147707$7845 + assign { } { } + assign $0\fast1_ok[0:0] \fast1_ok$next + sync posedge \coresync_clk + update \fast1_ok $0\fast1_ok[0:0] + end + attribute \src "issuer_ls180.v:147709.3-147710.19" + process $proc$issuer_ls180.v:147709$7846 + assign { } { } + assign $0\o[63:0] \o$next + sync posedge \coresync_clk + update \o $0\o[63:0] + end + attribute \src "issuer_ls180.v:147711.3-147712.25" + process $proc$issuer_ls180.v:147711$7847 + assign { } { } + assign $0\o_ok[0:0] \o_ok$next + sync posedge \coresync_clk + update \o_ok $0\o_ok[0:0] + end + attribute \src "issuer_ls180.v:147713.3-147714.59" + process $proc$issuer_ls180.v:147713$7848 + assign { } { } + assign $0\trap_op__insn_type$2[6:0]$7849 \trap_op__insn_type$2$next + sync posedge \coresync_clk + update \trap_op__insn_type$2 $0\trap_op__insn_type$2[6:0]$7849 + end + attribute \src "issuer_ls180.v:147715.3-147716.55" + process $proc$issuer_ls180.v:147715$7850 + assign { } { } + assign $0\trap_op__fn_unit$3[11:0]$7851 \trap_op__fn_unit$3$next + sync posedge \coresync_clk + update \trap_op__fn_unit$3 $0\trap_op__fn_unit$3[11:0]$7851 + end + attribute \src "issuer_ls180.v:147717.3-147718.49" + process $proc$issuer_ls180.v:147717$7852 + assign { } { } + assign $0\trap_op__insn$4[31:0]$7853 \trap_op__insn$4$next + sync posedge \coresync_clk + update \trap_op__insn$4 $0\trap_op__insn$4[31:0]$7853 + end + attribute \src "issuer_ls180.v:147719.3-147720.47" + process $proc$issuer_ls180.v:147719$7854 + assign { } { } + assign $0\trap_op__msr$5[63:0]$7855 \trap_op__msr$5$next + sync posedge \coresync_clk + update \trap_op__msr$5 $0\trap_op__msr$5[63:0]$7855 + end + attribute \src "issuer_ls180.v:147721.3-147722.47" + process $proc$issuer_ls180.v:147721$7856 + assign { } { } + assign $0\trap_op__cia$6[63:0]$7857 \trap_op__cia$6$next + sync posedge \coresync_clk + update \trap_op__cia$6 $0\trap_op__cia$6[63:0]$7857 + end + attribute \src "issuer_ls180.v:147723.3-147724.57" + process $proc$issuer_ls180.v:147723$7858 + assign { } { } + assign $0\trap_op__is_32bit$7[0:0]$7859 \trap_op__is_32bit$7$next + sync posedge \coresync_clk + update \trap_op__is_32bit$7 $0\trap_op__is_32bit$7[0:0]$7859 + end + attribute \src "issuer_ls180.v:147725.3-147726.57" + process $proc$issuer_ls180.v:147725$7860 + assign { } { } + assign $0\trap_op__traptype$8[6:0]$7861 \trap_op__traptype$8$next + sync posedge \coresync_clk + update \trap_op__traptype$8 $0\trap_op__traptype$8[6:0]$7861 + end + attribute \src "issuer_ls180.v:147727.3-147728.57" + process $proc$issuer_ls180.v:147727$7862 + assign { } { } + assign $0\trap_op__trapaddr$9[12:0]$7863 \trap_op__trapaddr$9$next + sync posedge \coresync_clk + update \trap_op__trapaddr$9 $0\trap_op__trapaddr$9[12:0]$7863 + end + attribute \src "issuer_ls180.v:147729.3-147730.33" + process $proc$issuer_ls180.v:147729$7864 + assign { } { } + assign $0\muxid$1[1:0]$7865 \muxid$1$next + sync posedge \coresync_clk + update \muxid$1 $0\muxid$1[1:0]$7865 + end + attribute \src "issuer_ls180.v:147731.3-147732.29" + process $proc$issuer_ls180.v:147731$7866 + assign { } { } + assign $0\r_busy[0:0] \r_busy$next + sync posedge \coresync_clk + update \r_busy $0\r_busy[0:0] + end + attribute \src "issuer_ls180.v:147775.3-147792.6" + process $proc$issuer_ls180.v:147775$7867 + assign { } { } + assign { } { } + assign { } { } + assign $0\r_busy$next[0:0]$7868 $2\r_busy$next[0:0]$7870 + attribute \src "issuer_ls180.v:147776.5-147776.29" + switch \initial + attribute \src "issuer_ls180.v:147776.9-147776.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\r_busy$next[0:0]$7869 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\r_busy$next[0:0]$7869 1'0 + case + assign $1\r_busy$next[0:0]$7869 \r_busy + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\r_busy$next[0:0]$7870 1'0 + case + assign $2\r_busy$next[0:0]$7870 $1\r_busy$next[0:0]$7869 + end + sync always + update \r_busy$next $0\r_busy$next[0:0]$7868 + end + attribute \src "issuer_ls180.v:147793.3-147805.6" + process $proc$issuer_ls180.v:147793$7871 + assign { } { } + assign { } { } + assign $0\muxid$1$next[1:0]$7872 $1\muxid$1$next[1:0]$7873 + attribute \src "issuer_ls180.v:147794.5-147794.29" + switch \initial + attribute \src "issuer_ls180.v:147794.9-147794.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\muxid$1$next[1:0]$7873 \muxid$26 + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\muxid$1$next[1:0]$7873 \muxid$26 + case + assign $1\muxid$1$next[1:0]$7873 \muxid$1 + end + sync always + update \muxid$1$next $0\muxid$1$next[1:0]$7872 + end + attribute \src "issuer_ls180.v:147806.3-147825.6" + process $proc$issuer_ls180.v:147806$7874 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\trap_op__cia$6$next[63:0]$7875 $1\trap_op__cia$6$next[63:0]$7883 + assign $0\trap_op__fn_unit$3$next[11:0]$7876 $1\trap_op__fn_unit$3$next[11:0]$7884 + assign $0\trap_op__insn$4$next[31:0]$7877 $1\trap_op__insn$4$next[31:0]$7885 + assign $0\trap_op__insn_type$2$next[6:0]$7878 $1\trap_op__insn_type$2$next[6:0]$7886 + assign $0\trap_op__is_32bit$7$next[0:0]$7879 $1\trap_op__is_32bit$7$next[0:0]$7887 + assign $0\trap_op__msr$5$next[63:0]$7880 $1\trap_op__msr$5$next[63:0]$7888 + assign $0\trap_op__trapaddr$9$next[12:0]$7881 $1\trap_op__trapaddr$9$next[12:0]$7889 + assign $0\trap_op__traptype$8$next[6:0]$7882 $1\trap_op__traptype$8$next[6:0]$7890 + attribute \src "issuer_ls180.v:147807.5-147807.29" + switch \initial + attribute \src "issuer_ls180.v:147807.9-147807.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'-1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { $1\trap_op__trapaddr$9$next[12:0]$7889 $1\trap_op__traptype$8$next[6:0]$7890 $1\trap_op__is_32bit$7$next[0:0]$7887 $1\trap_op__cia$6$next[63:0]$7883 $1\trap_op__msr$5$next[63:0]$7888 $1\trap_op__insn$4$next[31:0]$7885 $1\trap_op__fn_unit$3$next[11:0]$7884 $1\trap_op__insn_type$2$next[6:0]$7886 } { \trap_op__trapaddr$34 \trap_op__traptype$33 \trap_op__is_32bit$32 \trap_op__cia$31 \trap_op__msr$30 \trap_op__insn$29 \trap_op__fn_unit$28 \trap_op__insn_type$27 } + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'1- + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { $1\trap_op__trapaddr$9$next[12:0]$7889 $1\trap_op__traptype$8$next[6:0]$7890 $1\trap_op__is_32bit$7$next[0:0]$7887 $1\trap_op__cia$6$next[63:0]$7883 $1\trap_op__msr$5$next[63:0]$7888 $1\trap_op__insn$4$next[31:0]$7885 $1\trap_op__fn_unit$3$next[11:0]$7884 $1\trap_op__insn_type$2$next[6:0]$7886 } { \trap_op__trapaddr$34 \trap_op__traptype$33 \trap_op__is_32bit$32 \trap_op__cia$31 \trap_op__msr$30 \trap_op__insn$29 \trap_op__fn_unit$28 \trap_op__insn_type$27 } + case + assign $1\trap_op__cia$6$next[63:0]$7883 \trap_op__cia$6 + assign $1\trap_op__fn_unit$3$next[11:0]$7884 \trap_op__fn_unit$3 + assign $1\trap_op__insn$4$next[31:0]$7885 \trap_op__insn$4 + assign $1\trap_op__insn_type$2$next[6:0]$7886 \trap_op__insn_type$2 + assign $1\trap_op__is_32bit$7$next[0:0]$7887 \trap_op__is_32bit$7 + assign $1\trap_op__msr$5$next[63:0]$7888 \trap_op__msr$5 + assign $1\trap_op__trapaddr$9$next[12:0]$7889 \trap_op__trapaddr$9 + assign $1\trap_op__traptype$8$next[6:0]$7890 \trap_op__traptype$8 + end + sync always + update \trap_op__cia$6$next $0\trap_op__cia$6$next[63:0]$7875 + update \trap_op__fn_unit$3$next $0\trap_op__fn_unit$3$next[11:0]$7876 + update \trap_op__insn$4$next $0\trap_op__insn$4$next[31:0]$7877 + update \trap_op__insn_type$2$next $0\trap_op__insn_type$2$next[6:0]$7878 + update \trap_op__is_32bit$7$next $0\trap_op__is_32bit$7$next[0:0]$7879 + update \trap_op__msr$5$next $0\trap_op__msr$5$next[63:0]$7880 + update \trap_op__trapaddr$9$next $0\trap_op__trapaddr$9$next[12:0]$7881 + update \trap_op__traptype$8$next $0\trap_op__traptype$8$next[6:0]$7882 + end + attribute \src "issuer_ls180.v:147826.3-147844.6" + process $proc$issuer_ls180.v:147826$7891 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\o$next[63:0]$7892 $1\o$next[63:0]$7894 + assign { } { } + assign $0\o_ok$next[0:0]$7893 $2\o_ok$next[0:0]$7896 + attribute \src "issuer_ls180.v:147827.5-147827.29" + switch \initial + attribute \src "issuer_ls180.v:147827.9-147827.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'-1 + assign { } { } + assign { } { } + assign { $1\o_ok$next[0:0]$7895 $1\o$next[63:0]$7894 } { \o_ok$36 \o$35 } + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'1- + assign { } { } + assign { } { } + assign { $1\o_ok$next[0:0]$7895 $1\o$next[63:0]$7894 } { \o_ok$36 \o$35 } + case + assign $1\o$next[63:0]$7894 \o + assign $1\o_ok$next[0:0]$7895 \o_ok + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\o_ok$next[0:0]$7896 1'0 + case + assign $2\o_ok$next[0:0]$7896 $1\o_ok$next[0:0]$7895 + end + sync always + update \o$next $0\o$next[63:0]$7892 + update \o_ok$next $0\o_ok$next[0:0]$7893 + end + attribute \src "issuer_ls180.v:147845.3-147863.6" + process $proc$issuer_ls180.v:147845$7897 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\fast1$10$next[63:0]$7898 $1\fast1$10$next[63:0]$7900 + assign { } { } + assign $0\fast1_ok$next[0:0]$7899 $2\fast1_ok$next[0:0]$7902 + attribute \src "issuer_ls180.v:147846.5-147846.29" + switch \initial + attribute \src "issuer_ls180.v:147846.9-147846.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'-1 + assign { } { } + assign { } { } + assign { $1\fast1_ok$next[0:0]$7901 $1\fast1$10$next[63:0]$7900 } { \fast1_ok$38 \fast1$37 } + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'1- + assign { } { } + assign { } { } + assign { $1\fast1_ok$next[0:0]$7901 $1\fast1$10$next[63:0]$7900 } { \fast1_ok$38 \fast1$37 } + case + assign $1\fast1$10$next[63:0]$7900 \fast1$10 + assign $1\fast1_ok$next[0:0]$7901 \fast1_ok + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\fast1_ok$next[0:0]$7902 1'0 + case + assign $2\fast1_ok$next[0:0]$7902 $1\fast1_ok$next[0:0]$7901 + end + sync always + update \fast1$10$next $0\fast1$10$next[63:0]$7898 + update \fast1_ok$next $0\fast1_ok$next[0:0]$7899 + end + attribute \src "issuer_ls180.v:147864.3-147882.6" + process $proc$issuer_ls180.v:147864$7903 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\fast2$11$next[63:0]$7904 $1\fast2$11$next[63:0]$7906 + assign { } { } + assign $0\fast2_ok$next[0:0]$7905 $2\fast2_ok$next[0:0]$7908 + attribute \src "issuer_ls180.v:147865.5-147865.29" + switch \initial + attribute \src "issuer_ls180.v:147865.9-147865.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'-1 + assign { } { } + assign { } { } + assign { $1\fast2_ok$next[0:0]$7907 $1\fast2$11$next[63:0]$7906 } { \fast2_ok$40 \fast2$39 } + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'1- + assign { } { } + assign { } { } + assign { $1\fast2_ok$next[0:0]$7907 $1\fast2$11$next[63:0]$7906 } { \fast2_ok$40 \fast2$39 } + case + assign $1\fast2$11$next[63:0]$7906 \fast2$11 + assign $1\fast2_ok$next[0:0]$7907 \fast2_ok + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\fast2_ok$next[0:0]$7908 1'0 + case + assign $2\fast2_ok$next[0:0]$7908 $1\fast2_ok$next[0:0]$7907 + end + sync always + update \fast2$11$next $0\fast2$11$next[63:0]$7904 + update \fast2_ok$next $0\fast2_ok$next[0:0]$7905 + end + attribute \src "issuer_ls180.v:147883.3-147901.6" + process $proc$issuer_ls180.v:147883$7909 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\nia$next[63:0]$7910 $1\nia$next[63:0]$7912 + assign { } { } + assign $0\nia_ok$next[0:0]$7911 $2\nia_ok$next[0:0]$7914 + attribute \src "issuer_ls180.v:147884.5-147884.29" + switch \initial + attribute \src "issuer_ls180.v:147884.9-147884.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'-1 + assign { } { } + assign { } { } + assign { $1\nia_ok$next[0:0]$7913 $1\nia$next[63:0]$7912 } { \nia_ok$42 \nia$41 } + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'1- + assign { } { } + assign { } { } + assign { $1\nia_ok$next[0:0]$7913 $1\nia$next[63:0]$7912 } { \nia_ok$42 \nia$41 } + case + assign $1\nia$next[63:0]$7912 \nia + assign $1\nia_ok$next[0:0]$7913 \nia_ok + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\nia_ok$next[0:0]$7914 1'0 + case + assign $2\nia_ok$next[0:0]$7914 $1\nia_ok$next[0:0]$7913 + end + sync always + update \nia$next $0\nia$next[63:0]$7910 + update \nia_ok$next $0\nia_ok$next[0:0]$7911 + end + attribute \src "issuer_ls180.v:147902.3-147920.6" + process $proc$issuer_ls180.v:147902$7915 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\msr$next[63:0]$7916 $1\msr$next[63:0]$7918 + assign { } { } + assign $0\msr_ok$next[0:0]$7917 $2\msr_ok$next[0:0]$7920 + attribute \src "issuer_ls180.v:147903.5-147903.29" + switch \initial + attribute \src "issuer_ls180.v:147903.9-147903.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'-1 + assign { } { } + assign { } { } + assign { $1\msr_ok$next[0:0]$7919 $1\msr$next[63:0]$7918 } { \msr_ok$44 \msr$43 } + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'1- + assign { } { } + assign { } { } + assign { $1\msr_ok$next[0:0]$7919 $1\msr$next[63:0]$7918 } { \msr_ok$44 \msr$43 } + case + assign $1\msr$next[63:0]$7918 \msr + assign $1\msr_ok$next[0:0]$7919 \msr_ok + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\msr_ok$next[0:0]$7920 1'0 + case + assign $2\msr_ok$next[0:0]$7920 $1\msr_ok$next[0:0]$7919 + end + sync always + update \msr$next $0\msr$next[63:0]$7916 + update \msr_ok$next $0\msr_ok$next[0:0]$7917 + end + connect \$24 $and$issuer_ls180.v:147692$7835_Y + connect \p_ready_o \n_i_rdy_data + connect \n_valid_o \r_busy + connect { \msr_ok$44 \msr$43 } { \main_msr_ok \main_msr } + connect { \nia_ok$42 \nia$41 } { \main_nia_ok \main_nia } + connect { \fast2_ok$40 \fast2$39 } { \main_fast2_ok \main_fast2$22 } + connect { \fast1_ok$38 \fast1$37 } { \main_fast1_ok \main_fast1$21 } + connect { \o_ok$36 \o$35 } { \main_o_ok \main_o } + connect { \trap_op__trapaddr$34 \trap_op__traptype$33 \trap_op__is_32bit$32 \trap_op__cia$31 \trap_op__msr$30 \trap_op__insn$29 \trap_op__fn_unit$28 \trap_op__insn_type$27 } { \main_trap_op__trapaddr$20 \main_trap_op__traptype$19 \main_trap_op__is_32bit$18 \main_trap_op__cia$17 \main_trap_op__msr$16 \main_trap_op__insn$15 \main_trap_op__fn_unit$14 \main_trap_op__insn_type$13 } + connect \muxid$26 \main_muxid$12 + connect \p_valid_i_p_ready_o \$24 + connect \n_i_rdy_data \n_ready_i + connect \p_valid_i$23 \p_valid_i + connect \main_fast2 \fast2 + connect \main_fast1 \fast1 + connect \main_rb \rb + connect \main_ra \ra + connect { \main_trap_op__trapaddr \main_trap_op__traptype \main_trap_op__is_32bit \main_trap_op__cia \main_trap_op__msr \main_trap_op__insn \main_trap_op__fn_unit \main_trap_op__insn_type } { \trap_op__trapaddr \trap_op__traptype \trap_op__is_32bit \trap_op__cia \trap_op__msr \trap_op__insn \trap_op__fn_unit \trap_op__insn_type } + connect \main_muxid \muxid +end +attribute \src "issuer_ls180.v:147943.1-148858.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.fus.spr0.alu_spr0.pipe" +attribute \generator "nMigen" +module \pipe$61 + attribute \src "issuer_ls180.v:148761.3-148779.6" + wire width 64 $0\fast1$7$next[63:0]$8012 + attribute \src "issuer_ls180.v:148614.3-148615.33" + wire width 64 $0\fast1$7[63:0]$7964 + attribute \src "issuer_ls180.v:147957.14-147957.46" + wire width 64 $0\fast1$7[63:0]$8036 + attribute \src "issuer_ls180.v:148761.3-148779.6" + wire $0\fast1_ok$next[0:0]$8011 + attribute \src "issuer_ls180.v:148616.3-148617.33" + wire $0\fast1_ok[0:0] + attribute \src "issuer_ls180.v:147944.7-147944.20" + wire $0\initial[0:0] + attribute \src "issuer_ls180.v:148694.3-148706.6" + wire width 2 $0\muxid$1$next[1:0]$7987 + attribute \src "issuer_ls180.v:148634.3-148635.33" + wire width 2 $0\muxid$1[1:0]$7980 + attribute \src "issuer_ls180.v:147971.13-147971.29" + wire width 2 $0\muxid$1[1:0]$8039 + attribute \src "issuer_ls180.v:148723.3-148741.6" + wire width 64 $0\o$next[63:0]$7999 + attribute \src "issuer_ls180.v:148622.3-148623.19" + wire width 64 $0\o[63:0] + attribute \src "issuer_ls180.v:148723.3-148741.6" + wire $0\o_ok$next[0:0]$8000 + attribute \src "issuer_ls180.v:148624.3-148625.25" + wire $0\o_ok[0:0] + attribute \src "issuer_ls180.v:148676.3-148693.6" + wire $0\r_busy$next[0:0]$7983 + attribute \src "issuer_ls180.v:148636.3-148637.29" + wire $0\r_busy[0:0] + attribute \src "issuer_ls180.v:148742.3-148760.6" + wire width 64 $0\spr1$6$next[63:0]$8005 + attribute \src "issuer_ls180.v:148618.3-148619.31" + wire width 64 $0\spr1$6[63:0]$7967 + attribute \src "issuer_ls180.v:148016.14-148016.45" + wire width 64 $0\spr1$6[63:0]$8044 + attribute \src "issuer_ls180.v:148742.3-148760.6" + wire $0\spr1_ok$next[0:0]$8006 + attribute \src "issuer_ls180.v:148620.3-148621.31" + wire $0\spr1_ok[0:0] + attribute \src "issuer_ls180.v:148707.3-148722.6" + wire width 12 $0\spr_op__fn_unit$3$next[11:0]$7990 + attribute \src "issuer_ls180.v:148628.3-148629.53" + wire width 12 $0\spr_op__fn_unit$3[11:0]$7974 + attribute \src "issuer_ls180.v:148301.14-148301.43" + wire width 12 $0\spr_op__fn_unit$3[11:0]$8047 + attribute \src "issuer_ls180.v:148707.3-148722.6" + wire width 32 $0\spr_op__insn$4$next[31:0]$7991 + attribute \src "issuer_ls180.v:148630.3-148631.47" + wire width 32 $0\spr_op__insn$4[31:0]$7976 + attribute \src "issuer_ls180.v:148310.14-148310.38" + wire width 32 $0\spr_op__insn$4[31:0]$8049 + attribute \src "issuer_ls180.v:148707.3-148722.6" + wire width 7 $0\spr_op__insn_type$2$next[6:0]$7992 + attribute \src "issuer_ls180.v:148626.3-148627.57" + wire width 7 $0\spr_op__insn_type$2[6:0]$7972 + attribute \src "issuer_ls180.v:148465.13-148465.42" + wire width 7 $0\spr_op__insn_type$2[6:0]$8051 + attribute \src "issuer_ls180.v:148707.3-148722.6" + wire $0\spr_op__is_32bit$5$next[0:0]$7993 + attribute \src "issuer_ls180.v:148632.3-148633.55" + wire $0\spr_op__is_32bit$5[0:0]$7978 + attribute \src "issuer_ls180.v:148550.7-148550.34" + wire $0\spr_op__is_32bit$5[0:0]$8053 + attribute \src "issuer_ls180.v:148818.3-148836.6" + wire width 2 $0\xer_ca$10$next[1:0]$8029 + attribute \src "issuer_ls180.v:148602.3-148603.37" + wire width 2 $0\xer_ca$10[1:0]$7955 + attribute \src "issuer_ls180.v:148557.13-148557.31" + wire width 2 $0\xer_ca$10[1:0]$8055 + attribute \src "issuer_ls180.v:148818.3-148836.6" + wire $0\xer_ca_ok$next[0:0]$8030 + attribute \src "issuer_ls180.v:148604.3-148605.35" + wire $0\xer_ca_ok[0:0] + attribute \src "issuer_ls180.v:148799.3-148817.6" + wire width 2 $0\xer_ov$9$next[1:0]$8024 + attribute \src "issuer_ls180.v:148606.3-148607.35" + wire width 2 $0\xer_ov$9[1:0]$7958 + attribute \src "issuer_ls180.v:148575.13-148575.30" + wire width 2 $0\xer_ov$9[1:0]$8058 + attribute \src "issuer_ls180.v:148799.3-148817.6" + wire $0\xer_ov_ok$next[0:0]$8023 + attribute \src "issuer_ls180.v:148608.3-148609.35" + wire $0\xer_ov_ok[0:0] + attribute \src "issuer_ls180.v:148780.3-148798.6" + wire $0\xer_so$8$next[0:0]$8018 + attribute \src "issuer_ls180.v:148610.3-148611.35" + wire $0\xer_so$8[0:0]$7961 + attribute \src "issuer_ls180.v:148591.7-148591.24" + wire $0\xer_so$8[0:0]$8061 + attribute \src "issuer_ls180.v:148780.3-148798.6" + wire $0\xer_so_ok$next[0:0]$8017 + attribute \src "issuer_ls180.v:148612.3-148613.35" + wire $0\xer_so_ok[0:0] + attribute \src "issuer_ls180.v:148761.3-148779.6" + wire width 64 $1\fast1$7$next[63:0]$8014 + attribute \src "issuer_ls180.v:148761.3-148779.6" + wire $1\fast1_ok$next[0:0]$8013 + attribute \src "issuer_ls180.v:147962.7-147962.22" + wire $1\fast1_ok[0:0] + attribute \src "issuer_ls180.v:148694.3-148706.6" + wire width 2 $1\muxid$1$next[1:0]$7988 + attribute \src "issuer_ls180.v:148723.3-148741.6" + wire width 64 $1\o$next[63:0]$8001 + attribute \src "issuer_ls180.v:147984.14-147984.38" + wire width 64 $1\o[63:0] + attribute \src "issuer_ls180.v:148723.3-148741.6" + wire $1\o_ok$next[0:0]$8002 + attribute \src "issuer_ls180.v:147991.7-147991.18" + wire $1\o_ok[0:0] + attribute \src "issuer_ls180.v:148676.3-148693.6" + wire $1\r_busy$next[0:0]$7984 + attribute \src "issuer_ls180.v:148005.7-148005.20" + wire $1\r_busy[0:0] + attribute \src "issuer_ls180.v:148742.3-148760.6" + wire width 64 $1\spr1$6$next[63:0]$8007 + attribute \src "issuer_ls180.v:148742.3-148760.6" + wire $1\spr1_ok$next[0:0]$8008 + attribute \src "issuer_ls180.v:148021.7-148021.21" + wire $1\spr1_ok[0:0] + attribute \src "issuer_ls180.v:148707.3-148722.6" + wire width 12 $1\spr_op__fn_unit$3$next[11:0]$7994 + attribute \src "issuer_ls180.v:148707.3-148722.6" + wire width 32 $1\spr_op__insn$4$next[31:0]$7995 + attribute \src "issuer_ls180.v:148707.3-148722.6" + wire width 7 $1\spr_op__insn_type$2$next[6:0]$7996 + attribute \src "issuer_ls180.v:148707.3-148722.6" + wire $1\spr_op__is_32bit$5$next[0:0]$7997 + attribute \src "issuer_ls180.v:148818.3-148836.6" + wire width 2 $1\xer_ca$10$next[1:0]$8031 + attribute \src "issuer_ls180.v:148818.3-148836.6" + wire $1\xer_ca_ok$next[0:0]$8032 + attribute \src "issuer_ls180.v:148564.7-148564.23" + wire $1\xer_ca_ok[0:0] + attribute \src "issuer_ls180.v:148799.3-148817.6" + wire width 2 $1\xer_ov$9$next[1:0]$8026 + attribute \src "issuer_ls180.v:148799.3-148817.6" + wire $1\xer_ov_ok$next[0:0]$8025 + attribute \src "issuer_ls180.v:148580.7-148580.23" + wire $1\xer_ov_ok[0:0] + attribute \src "issuer_ls180.v:148780.3-148798.6" + wire $1\xer_so$8$next[0:0]$8020 + attribute \src "issuer_ls180.v:148780.3-148798.6" + wire $1\xer_so_ok$next[0:0]$8019 + attribute \src "issuer_ls180.v:148596.7-148596.23" + wire $1\xer_so_ok[0:0] + attribute \src "issuer_ls180.v:148761.3-148779.6" + wire $2\fast1_ok$next[0:0]$8015 + attribute \src "issuer_ls180.v:148723.3-148741.6" + wire $2\o_ok$next[0:0]$8003 + attribute \src "issuer_ls180.v:148676.3-148693.6" + wire $2\r_busy$next[0:0]$7985 + attribute \src "issuer_ls180.v:148742.3-148760.6" + wire $2\spr1_ok$next[0:0]$8009 + attribute \src "issuer_ls180.v:148818.3-148836.6" + wire $2\xer_ca_ok$next[0:0]$8033 + attribute \src "issuer_ls180.v:148799.3-148817.6" + wire $2\xer_ov_ok$next[0:0]$8027 + attribute \src "issuer_ls180.v:148780.3-148798.6" + wire $2\xer_so_ok$next[0:0]$8021 + attribute \src "issuer_ls180.v:148601.18-148601.118" + wire $and$issuer_ls180.v:148601$7953_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" + wire \$22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" + wire input 34 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" + wire input 1 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 11 \fast1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 \fast1$33 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 output 26 \fast1$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 \fast1$7$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 27 \fast1_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \fast1_ok$34 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \fast1_ok$next + attribute \src "issuer_ls180.v:147944.7-147944.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 input 4 \muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 output 17 \muxid$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \muxid$1$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \muxid$24 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:619" + wire \n_i_rdy_data + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" + wire input 16 \n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" + wire output 15 \n_valid_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 output 22 \o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 \o$29 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 \o$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 23 \o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \o_ok$30 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \o_ok$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" + wire output 3 \p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" + wire input 2 \p_valid_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:621" + wire \p_valid_i$21 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" + wire \p_valid_i_p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615" + wire \r_busy + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615" + wire \r_busy$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 9 \ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 10 \spr1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 \spr1$31 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 output 24 \spr1$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 \spr1$6$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 25 \spr1_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \spr1_ok$32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \spr1_ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \spr_main_fast1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 \spr_main_fast1$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \spr_main_fast1_ok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \spr_main_muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \spr_main_muxid$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 \spr_main_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \spr_main_o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \spr_main_ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \spr_main_spr1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 \spr_main_spr1$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \spr_main_spr1_ok + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 \spr_main_spr_op__fn_unit + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 \spr_main_spr_op__fn_unit$13 + attribute \src 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attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \spr_op__insn_type$25 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 8 \spr_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \spr_op__is_32bit$28 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 21 \spr_op__is_32bit$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \spr_op__is_32bit$5$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 2 input 14 \xer_ca + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 2 output 32 \xer_ca$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 2 \xer_ca$10$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 2 \xer_ca$39 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 33 \xer_ca_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \xer_ca_ok$40 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \xer_ca_ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 2 input 13 \xer_ov + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 2 \xer_ov$37 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 2 output 30 \xer_ov$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 2 \xer_ov$9$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 31 \xer_ov_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \xer_ov_ok$38 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \xer_ov_ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire input 12 \xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \xer_so$35 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 28 \xer_so$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \xer_so$8$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 29 \xer_so_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \xer_so_ok$36 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \xer_so_ok$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" + cell $and $and$issuer_ls180.v:148601$7953 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \p_valid_i$21 + connect \B \p_ready_o + connect \Y $and$issuer_ls180.v:148601$7953_Y + end + attribute \module_not_derived 1 + attribute \src "issuer_ls180.v:148638.10-148641.4" + cell \n$63 \n + connect \n_ready_i \n_ready_i + connect \n_valid_o \n_valid_o + end + attribute \module_not_derived 1 + attribute \src "issuer_ls180.v:148642.10-148645.4" + cell \p$62 \p + connect \p_ready_o \p_ready_o + connect \p_valid_i \p_valid_i + end + attribute \module_not_derived 1 + attribute \src "issuer_ls180.v:148646.12-148675.4" + cell \spr_main \spr_main + connect \fast1 \spr_main_fast1 + connect \fast1$7 \spr_main_fast1$17 + connect \fast1_ok \spr_main_fast1_ok + connect \muxid \spr_main_muxid + connect \muxid$1 \spr_main_muxid$11 + connect \o \spr_main_o + connect \o_ok \spr_main_o_ok + connect \ra \spr_main_ra + connect \spr1 \spr_main_spr1 + connect \spr1$6 \spr_main_spr1$16 + connect \spr1_ok \spr_main_spr1_ok + connect \spr_op__fn_unit \spr_main_spr_op__fn_unit + connect \spr_op__fn_unit$3 \spr_main_spr_op__fn_unit$13 + connect \spr_op__insn \spr_main_spr_op__insn + connect \spr_op__insn$4 \spr_main_spr_op__insn$14 + connect \spr_op__insn_type \spr_main_spr_op__insn_type + connect \spr_op__insn_type$2 \spr_main_spr_op__insn_type$12 + connect \spr_op__is_32bit \spr_main_spr_op__is_32bit + connect \spr_op__is_32bit$5 \spr_main_spr_op__is_32bit$15 + connect \xer_ca \spr_main_xer_ca + connect \xer_ca$10 \spr_main_xer_ca$20 + connect \xer_ca_ok \spr_main_xer_ca_ok + connect \xer_ov \spr_main_xer_ov + connect \xer_ov$9 \spr_main_xer_ov$19 + connect \xer_ov_ok \spr_main_xer_ov_ok + connect \xer_so \spr_main_xer_so + connect \xer_so$8 \spr_main_xer_so$18 + connect \xer_so_ok \spr_main_xer_so_ok + end + attribute \src "issuer_ls180.v:147944.7-147944.20" + process $proc$issuer_ls180.v:147944$8034 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "issuer_ls180.v:147957.14-147957.46" + process $proc$issuer_ls180.v:147957$8035 + assign { } { } + assign $0\fast1$7[63:0]$8036 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \fast1$7 $0\fast1$7[63:0]$8036 + end + attribute \src "issuer_ls180.v:147962.7-147962.22" + process $proc$issuer_ls180.v:147962$8037 + assign { } { } + assign $1\fast1_ok[0:0] 1'0 + sync always + sync init + update \fast1_ok $1\fast1_ok[0:0] + end + attribute \src "issuer_ls180.v:147971.13-147971.29" + process $proc$issuer_ls180.v:147971$8038 + assign { } { } + assign $0\muxid$1[1:0]$8039 2'00 + sync always + sync init + update \muxid$1 $0\muxid$1[1:0]$8039 + end + attribute \src "issuer_ls180.v:147984.14-147984.38" + process $proc$issuer_ls180.v:147984$8040 + assign { } { } + assign $1\o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \o $1\o[63:0] + end + attribute \src "issuer_ls180.v:147991.7-147991.18" + process $proc$issuer_ls180.v:147991$8041 + assign { } { } + assign $1\o_ok[0:0] 1'0 + sync always + sync init + update \o_ok $1\o_ok[0:0] + end + attribute \src "issuer_ls180.v:148005.7-148005.20" + process $proc$issuer_ls180.v:148005$8042 + assign { } { } + assign $1\r_busy[0:0] 1'0 + sync always + sync init + update \r_busy $1\r_busy[0:0] + end + attribute \src "issuer_ls180.v:148016.14-148016.45" + process $proc$issuer_ls180.v:148016$8043 + assign { } { } + assign $0\spr1$6[63:0]$8044 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \spr1$6 $0\spr1$6[63:0]$8044 + end + attribute \src "issuer_ls180.v:148021.7-148021.21" + process $proc$issuer_ls180.v:148021$8045 + assign { } { } + assign $1\spr1_ok[0:0] 1'0 + sync always + sync init + update \spr1_ok $1\spr1_ok[0:0] + end + attribute \src "issuer_ls180.v:148301.14-148301.43" + process $proc$issuer_ls180.v:148301$8046 + assign { } { } + assign $0\spr_op__fn_unit$3[11:0]$8047 12'000000000000 + sync always + sync init + update \spr_op__fn_unit$3 $0\spr_op__fn_unit$3[11:0]$8047 + end + attribute \src "issuer_ls180.v:148310.14-148310.38" + process $proc$issuer_ls180.v:148310$8048 + assign { } { } + assign $0\spr_op__insn$4[31:0]$8049 0 + sync always + sync init + update \spr_op__insn$4 $0\spr_op__insn$4[31:0]$8049 + end + attribute \src "issuer_ls180.v:148465.13-148465.42" + process $proc$issuer_ls180.v:148465$8050 + assign { } { } + assign $0\spr_op__insn_type$2[6:0]$8051 7'0000000 + sync always + sync init + update \spr_op__insn_type$2 $0\spr_op__insn_type$2[6:0]$8051 + end + attribute \src "issuer_ls180.v:148550.7-148550.34" + process $proc$issuer_ls180.v:148550$8052 + assign { } { } + assign $0\spr_op__is_32bit$5[0:0]$8053 1'0 + sync always + sync init + update \spr_op__is_32bit$5 $0\spr_op__is_32bit$5[0:0]$8053 + end + attribute \src "issuer_ls180.v:148557.13-148557.31" + process $proc$issuer_ls180.v:148557$8054 + assign { } { } + assign $0\xer_ca$10[1:0]$8055 2'00 + sync always + sync init + update \xer_ca$10 $0\xer_ca$10[1:0]$8055 + end + attribute \src "issuer_ls180.v:148564.7-148564.23" + process $proc$issuer_ls180.v:148564$8056 + assign { } { } + assign $1\xer_ca_ok[0:0] 1'0 + sync always + sync init + update \xer_ca_ok $1\xer_ca_ok[0:0] + end + attribute \src "issuer_ls180.v:148575.13-148575.30" + process $proc$issuer_ls180.v:148575$8057 + assign { } { } + assign $0\xer_ov$9[1:0]$8058 2'00 + sync always + sync init + update \xer_ov$9 $0\xer_ov$9[1:0]$8058 + end + attribute \src "issuer_ls180.v:148580.7-148580.23" + process $proc$issuer_ls180.v:148580$8059 + assign { } { } + assign $1\xer_ov_ok[0:0] 1'0 + sync always + sync init + update \xer_ov_ok $1\xer_ov_ok[0:0] + end + attribute \src "issuer_ls180.v:148591.7-148591.24" + process $proc$issuer_ls180.v:148591$8060 + assign { } { } + assign $0\xer_so$8[0:0]$8061 1'0 + sync always + sync init + update \xer_so$8 $0\xer_so$8[0:0]$8061 + end + attribute \src "issuer_ls180.v:148596.7-148596.23" + process $proc$issuer_ls180.v:148596$8062 + assign { } { } + assign $1\xer_so_ok[0:0] 1'0 + sync always + sync init + update \xer_so_ok $1\xer_so_ok[0:0] + end + attribute \src "issuer_ls180.v:148602.3-148603.37" + process $proc$issuer_ls180.v:148602$7954 + assign { } { } + assign $0\xer_ca$10[1:0]$7955 \xer_ca$10$next + sync posedge \coresync_clk + update \xer_ca$10 $0\xer_ca$10[1:0]$7955 + end + attribute \src "issuer_ls180.v:148604.3-148605.35" + process $proc$issuer_ls180.v:148604$7956 + assign { } { } + assign $0\xer_ca_ok[0:0] \xer_ca_ok$next + sync posedge \coresync_clk + update \xer_ca_ok $0\xer_ca_ok[0:0] + end + attribute \src "issuer_ls180.v:148606.3-148607.35" + process $proc$issuer_ls180.v:148606$7957 + assign { } { } + assign $0\xer_ov$9[1:0]$7958 \xer_ov$9$next + sync posedge \coresync_clk + update \xer_ov$9 $0\xer_ov$9[1:0]$7958 + end + attribute \src "issuer_ls180.v:148608.3-148609.35" + process $proc$issuer_ls180.v:148608$7959 + assign { } { } + assign $0\xer_ov_ok[0:0] \xer_ov_ok$next + sync posedge \coresync_clk + update \xer_ov_ok $0\xer_ov_ok[0:0] + end + attribute \src "issuer_ls180.v:148610.3-148611.35" + process $proc$issuer_ls180.v:148610$7960 + assign { } { } + assign $0\xer_so$8[0:0]$7961 \xer_so$8$next + sync posedge \coresync_clk + update \xer_so$8 $0\xer_so$8[0:0]$7961 + end + attribute \src "issuer_ls180.v:148612.3-148613.35" + process $proc$issuer_ls180.v:148612$7962 + assign { } { } + assign $0\xer_so_ok[0:0] \xer_so_ok$next + sync posedge \coresync_clk + update \xer_so_ok $0\xer_so_ok[0:0] + end + attribute \src "issuer_ls180.v:148614.3-148615.33" + process $proc$issuer_ls180.v:148614$7963 + assign { } { } + assign $0\fast1$7[63:0]$7964 \fast1$7$next + sync posedge \coresync_clk + update \fast1$7 $0\fast1$7[63:0]$7964 + end + attribute \src "issuer_ls180.v:148616.3-148617.33" + process $proc$issuer_ls180.v:148616$7965 + assign { } { } + assign $0\fast1_ok[0:0] \fast1_ok$next + sync posedge \coresync_clk + update \fast1_ok $0\fast1_ok[0:0] + end + attribute \src "issuer_ls180.v:148618.3-148619.31" + process $proc$issuer_ls180.v:148618$7966 + assign { } { } + assign $0\spr1$6[63:0]$7967 \spr1$6$next + sync posedge \coresync_clk + update \spr1$6 $0\spr1$6[63:0]$7967 + end + attribute \src "issuer_ls180.v:148620.3-148621.31" + process $proc$issuer_ls180.v:148620$7968 + assign { } { } + assign $0\spr1_ok[0:0] \spr1_ok$next + sync posedge \coresync_clk + update \spr1_ok $0\spr1_ok[0:0] + end + attribute \src "issuer_ls180.v:148622.3-148623.19" + process $proc$issuer_ls180.v:148622$7969 + assign { } { } + assign $0\o[63:0] \o$next + sync posedge \coresync_clk + update \o $0\o[63:0] + end + attribute \src "issuer_ls180.v:148624.3-148625.25" + process $proc$issuer_ls180.v:148624$7970 + assign { } { } + assign $0\o_ok[0:0] \o_ok$next + sync posedge \coresync_clk + update \o_ok $0\o_ok[0:0] + end + attribute \src "issuer_ls180.v:148626.3-148627.57" + process $proc$issuer_ls180.v:148626$7971 + assign { } { } + assign $0\spr_op__insn_type$2[6:0]$7972 \spr_op__insn_type$2$next + sync posedge \coresync_clk + update \spr_op__insn_type$2 $0\spr_op__insn_type$2[6:0]$7972 + end + attribute \src "issuer_ls180.v:148628.3-148629.53" + process $proc$issuer_ls180.v:148628$7973 + assign { } { } + assign $0\spr_op__fn_unit$3[11:0]$7974 \spr_op__fn_unit$3$next + sync posedge \coresync_clk + update \spr_op__fn_unit$3 $0\spr_op__fn_unit$3[11:0]$7974 + end + attribute \src "issuer_ls180.v:148630.3-148631.47" + process $proc$issuer_ls180.v:148630$7975 + assign { } { } + assign $0\spr_op__insn$4[31:0]$7976 \spr_op__insn$4$next + sync posedge \coresync_clk + update \spr_op__insn$4 $0\spr_op__insn$4[31:0]$7976 + end + attribute \src "issuer_ls180.v:148632.3-148633.55" + process $proc$issuer_ls180.v:148632$7977 + assign { } { } + assign $0\spr_op__is_32bit$5[0:0]$7978 \spr_op__is_32bit$5$next + sync posedge \coresync_clk + update \spr_op__is_32bit$5 $0\spr_op__is_32bit$5[0:0]$7978 + end + attribute \src "issuer_ls180.v:148634.3-148635.33" + process $proc$issuer_ls180.v:148634$7979 + assign { } { } + assign $0\muxid$1[1:0]$7980 \muxid$1$next + sync posedge \coresync_clk + update \muxid$1 $0\muxid$1[1:0]$7980 + end + attribute \src "issuer_ls180.v:148636.3-148637.29" + process $proc$issuer_ls180.v:148636$7981 + assign { } { } + assign $0\r_busy[0:0] \r_busy$next + sync posedge \coresync_clk + update \r_busy $0\r_busy[0:0] + end + attribute \src "issuer_ls180.v:148676.3-148693.6" + process $proc$issuer_ls180.v:148676$7982 + assign { } { } + assign { } { } + assign { } { } + assign $0\r_busy$next[0:0]$7983 $2\r_busy$next[0:0]$7985 + attribute \src "issuer_ls180.v:148677.5-148677.29" + switch \initial + attribute \src "issuer_ls180.v:148677.9-148677.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\r_busy$next[0:0]$7984 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\r_busy$next[0:0]$7984 1'0 + case + assign $1\r_busy$next[0:0]$7984 \r_busy + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\r_busy$next[0:0]$7985 1'0 + case + assign $2\r_busy$next[0:0]$7985 $1\r_busy$next[0:0]$7984 + end + sync always + update \r_busy$next $0\r_busy$next[0:0]$7983 + end + attribute \src "issuer_ls180.v:148694.3-148706.6" + process $proc$issuer_ls180.v:148694$7986 + assign { } { } + assign { } { } + assign $0\muxid$1$next[1:0]$7987 $1\muxid$1$next[1:0]$7988 + attribute \src "issuer_ls180.v:148695.5-148695.29" + switch \initial + attribute \src "issuer_ls180.v:148695.9-148695.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\muxid$1$next[1:0]$7988 \muxid$24 + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\muxid$1$next[1:0]$7988 \muxid$24 + case + assign $1\muxid$1$next[1:0]$7988 \muxid$1 + end + sync always + update \muxid$1$next $0\muxid$1$next[1:0]$7987 + end + attribute \src "issuer_ls180.v:148707.3-148722.6" + process $proc$issuer_ls180.v:148707$7989 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\spr_op__fn_unit$3$next[11:0]$7990 $1\spr_op__fn_unit$3$next[11:0]$7994 + assign $0\spr_op__insn$4$next[31:0]$7991 $1\spr_op__insn$4$next[31:0]$7995 + assign $0\spr_op__insn_type$2$next[6:0]$7992 $1\spr_op__insn_type$2$next[6:0]$7996 + assign $0\spr_op__is_32bit$5$next[0:0]$7993 $1\spr_op__is_32bit$5$next[0:0]$7997 + attribute \src "issuer_ls180.v:148708.5-148708.29" + switch \initial + attribute \src "issuer_ls180.v:148708.9-148708.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'-1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { $1\spr_op__is_32bit$5$next[0:0]$7997 $1\spr_op__insn$4$next[31:0]$7995 $1\spr_op__fn_unit$3$next[11:0]$7994 $1\spr_op__insn_type$2$next[6:0]$7996 } { \spr_op__is_32bit$28 \spr_op__insn$27 \spr_op__fn_unit$26 \spr_op__insn_type$25 } + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'1- + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { $1\spr_op__is_32bit$5$next[0:0]$7997 $1\spr_op__insn$4$next[31:0]$7995 $1\spr_op__fn_unit$3$next[11:0]$7994 $1\spr_op__insn_type$2$next[6:0]$7996 } { \spr_op__is_32bit$28 \spr_op__insn$27 \spr_op__fn_unit$26 \spr_op__insn_type$25 } + case + assign $1\spr_op__fn_unit$3$next[11:0]$7994 \spr_op__fn_unit$3 + assign $1\spr_op__insn$4$next[31:0]$7995 \spr_op__insn$4 + assign $1\spr_op__insn_type$2$next[6:0]$7996 \spr_op__insn_type$2 + assign $1\spr_op__is_32bit$5$next[0:0]$7997 \spr_op__is_32bit$5 + end + sync always + update \spr_op__fn_unit$3$next $0\spr_op__fn_unit$3$next[11:0]$7990 + update \spr_op__insn$4$next $0\spr_op__insn$4$next[31:0]$7991 + update \spr_op__insn_type$2$next $0\spr_op__insn_type$2$next[6:0]$7992 + update \spr_op__is_32bit$5$next $0\spr_op__is_32bit$5$next[0:0]$7993 + end + attribute \src "issuer_ls180.v:148723.3-148741.6" + process $proc$issuer_ls180.v:148723$7998 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\o$next[63:0]$7999 $1\o$next[63:0]$8001 + assign { } { } + assign $0\o_ok$next[0:0]$8000 $2\o_ok$next[0:0]$8003 + attribute \src "issuer_ls180.v:148724.5-148724.29" + switch \initial + attribute \src "issuer_ls180.v:148724.9-148724.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'-1 + assign { } { } + assign { } { } + assign { $1\o_ok$next[0:0]$8002 $1\o$next[63:0]$8001 } { \o_ok$30 \o$29 } + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'1- + assign { } { } + assign { } { } + assign { $1\o_ok$next[0:0]$8002 $1\o$next[63:0]$8001 } { \o_ok$30 \o$29 } + case + assign $1\o$next[63:0]$8001 \o + assign $1\o_ok$next[0:0]$8002 \o_ok + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\o_ok$next[0:0]$8003 1'0 + case + assign $2\o_ok$next[0:0]$8003 $1\o_ok$next[0:0]$8002 + end + sync always + update \o$next $0\o$next[63:0]$7999 + update \o_ok$next $0\o_ok$next[0:0]$8000 + end + attribute \src "issuer_ls180.v:148742.3-148760.6" + process $proc$issuer_ls180.v:148742$8004 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\spr1$6$next[63:0]$8005 $1\spr1$6$next[63:0]$8007 + assign { } { } + assign $0\spr1_ok$next[0:0]$8006 $2\spr1_ok$next[0:0]$8009 + attribute \src "issuer_ls180.v:148743.5-148743.29" + switch \initial + attribute \src "issuer_ls180.v:148743.9-148743.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'-1 + assign { } { } + assign { } { } + assign { $1\spr1_ok$next[0:0]$8008 $1\spr1$6$next[63:0]$8007 } { \spr1_ok$32 \spr1$31 } + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'1- + assign { } { } + assign { } { } + assign { $1\spr1_ok$next[0:0]$8008 $1\spr1$6$next[63:0]$8007 } { \spr1_ok$32 \spr1$31 } + case + assign $1\spr1$6$next[63:0]$8007 \spr1$6 + assign $1\spr1_ok$next[0:0]$8008 \spr1_ok + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\spr1_ok$next[0:0]$8009 1'0 + case + assign $2\spr1_ok$next[0:0]$8009 $1\spr1_ok$next[0:0]$8008 + end + sync always + update \spr1$6$next $0\spr1$6$next[63:0]$8005 + update \spr1_ok$next $0\spr1_ok$next[0:0]$8006 + end + attribute \src "issuer_ls180.v:148761.3-148779.6" + process $proc$issuer_ls180.v:148761$8010 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\fast1$7$next[63:0]$8012 $1\fast1$7$next[63:0]$8014 + assign $0\fast1_ok$next[0:0]$8011 $2\fast1_ok$next[0:0]$8015 + attribute \src "issuer_ls180.v:148762.5-148762.29" + switch \initial + attribute \src "issuer_ls180.v:148762.9-148762.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'-1 + assign { } { } + assign { } { } + assign { $1\fast1_ok$next[0:0]$8013 $1\fast1$7$next[63:0]$8014 } { \fast1_ok$34 \fast1$33 } + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'1- + assign { } { } + assign { } { } + assign { $1\fast1_ok$next[0:0]$8013 $1\fast1$7$next[63:0]$8014 } { \fast1_ok$34 \fast1$33 } + case + assign $1\fast1_ok$next[0:0]$8013 \fast1_ok + assign $1\fast1$7$next[63:0]$8014 \fast1$7 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\fast1_ok$next[0:0]$8015 1'0 + case + assign $2\fast1_ok$next[0:0]$8015 $1\fast1_ok$next[0:0]$8013 + end + sync always + update \fast1_ok$next $0\fast1_ok$next[0:0]$8011 + update \fast1$7$next $0\fast1$7$next[63:0]$8012 + end + attribute \src "issuer_ls180.v:148780.3-148798.6" + process $proc$issuer_ls180.v:148780$8016 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\xer_so$8$next[0:0]$8018 $1\xer_so$8$next[0:0]$8020 + assign $0\xer_so_ok$next[0:0]$8017 $2\xer_so_ok$next[0:0]$8021 + attribute \src "issuer_ls180.v:148781.5-148781.29" + switch \initial + attribute \src "issuer_ls180.v:148781.9-148781.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'-1 + assign { } { } + assign { } { } + assign { $1\xer_so_ok$next[0:0]$8019 $1\xer_so$8$next[0:0]$8020 } { \xer_so_ok$36 \xer_so$35 } + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'1- + assign { } { } + assign { } { } + assign { $1\xer_so_ok$next[0:0]$8019 $1\xer_so$8$next[0:0]$8020 } { \xer_so_ok$36 \xer_so$35 } + case + assign $1\xer_so_ok$next[0:0]$8019 \xer_so_ok + assign $1\xer_so$8$next[0:0]$8020 \xer_so$8 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\xer_so_ok$next[0:0]$8021 1'0 + case + assign $2\xer_so_ok$next[0:0]$8021 $1\xer_so_ok$next[0:0]$8019 + end + sync always + update \xer_so_ok$next $0\xer_so_ok$next[0:0]$8017 + update \xer_so$8$next $0\xer_so$8$next[0:0]$8018 + end + attribute \src "issuer_ls180.v:148799.3-148817.6" + process $proc$issuer_ls180.v:148799$8022 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\xer_ov$9$next[1:0]$8024 $1\xer_ov$9$next[1:0]$8026 + assign $0\xer_ov_ok$next[0:0]$8023 $2\xer_ov_ok$next[0:0]$8027 + attribute \src "issuer_ls180.v:148800.5-148800.29" + switch \initial + attribute \src "issuer_ls180.v:148800.9-148800.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'-1 + assign { } { } + assign { } { } + assign { $1\xer_ov_ok$next[0:0]$8025 $1\xer_ov$9$next[1:0]$8026 } { \xer_ov_ok$38 \xer_ov$37 } + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'1- + assign { } { } + assign { } { } + assign { $1\xer_ov_ok$next[0:0]$8025 $1\xer_ov$9$next[1:0]$8026 } { \xer_ov_ok$38 \xer_ov$37 } + case + assign $1\xer_ov_ok$next[0:0]$8025 \xer_ov_ok + assign $1\xer_ov$9$next[1:0]$8026 \xer_ov$9 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\xer_ov_ok$next[0:0]$8027 1'0 + case + assign $2\xer_ov_ok$next[0:0]$8027 $1\xer_ov_ok$next[0:0]$8025 + end + sync always + update \xer_ov_ok$next $0\xer_ov_ok$next[0:0]$8023 + update \xer_ov$9$next $0\xer_ov$9$next[1:0]$8024 + end + attribute \src "issuer_ls180.v:148818.3-148836.6" + process $proc$issuer_ls180.v:148818$8028 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\xer_ca$10$next[1:0]$8029 $1\xer_ca$10$next[1:0]$8031 + assign { } { } + assign $0\xer_ca_ok$next[0:0]$8030 $2\xer_ca_ok$next[0:0]$8033 + attribute \src "issuer_ls180.v:148819.5-148819.29" + switch \initial + attribute \src "issuer_ls180.v:148819.9-148819.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'-1 + assign { } { } + assign { } { } + assign { $1\xer_ca_ok$next[0:0]$8032 $1\xer_ca$10$next[1:0]$8031 } { \xer_ca_ok$40 \xer_ca$39 } + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'1- + assign { } { } + assign { } { } + assign { $1\xer_ca_ok$next[0:0]$8032 $1\xer_ca$10$next[1:0]$8031 } { \xer_ca_ok$40 \xer_ca$39 } + case + assign $1\xer_ca$10$next[1:0]$8031 \xer_ca$10 + assign $1\xer_ca_ok$next[0:0]$8032 \xer_ca_ok + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\xer_ca_ok$next[0:0]$8033 1'0 + case + assign $2\xer_ca_ok$next[0:0]$8033 $1\xer_ca_ok$next[0:0]$8032 + end + sync always + update \xer_ca$10$next $0\xer_ca$10$next[1:0]$8029 + update \xer_ca_ok$next $0\xer_ca_ok$next[0:0]$8030 + end + connect \$22 $and$issuer_ls180.v:148601$7953_Y + connect \p_ready_o \n_i_rdy_data + connect \n_valid_o \r_busy + connect { \xer_ca_ok$40 \xer_ca$39 } { \spr_main_xer_ca_ok \spr_main_xer_ca$20 } + connect { \xer_ov_ok$38 \xer_ov$37 } { \spr_main_xer_ov_ok \spr_main_xer_ov$19 } + connect { \xer_so_ok$36 \xer_so$35 } { \spr_main_xer_so_ok \spr_main_xer_so$18 } + connect { \fast1_ok$34 \fast1$33 } { \spr_main_fast1_ok \spr_main_fast1$17 } + connect { \spr1_ok$32 \spr1$31 } { \spr_main_spr1_ok \spr_main_spr1$16 } + connect { \o_ok$30 \o$29 } { \spr_main_o_ok \spr_main_o } + connect { \spr_op__is_32bit$28 \spr_op__insn$27 \spr_op__fn_unit$26 \spr_op__insn_type$25 } { \spr_main_spr_op__is_32bit$15 \spr_main_spr_op__insn$14 \spr_main_spr_op__fn_unit$13 \spr_main_spr_op__insn_type$12 } + connect \muxid$24 \spr_main_muxid$11 + connect \p_valid_i_p_ready_o \$22 + connect \n_i_rdy_data \n_ready_i + connect \p_valid_i$21 \p_valid_i + connect \spr_main_xer_ca \xer_ca + connect \spr_main_xer_ov \xer_ov + connect \spr_main_xer_so \xer_so + connect \spr_main_fast1 \fast1 + connect \spr_main_spr1 \spr1 + connect \spr_main_ra \ra + connect { \spr_main_spr_op__is_32bit \spr_main_spr_op__insn \spr_main_spr_op__fn_unit \spr_main_spr_op__insn_type } { \spr_op__is_32bit \spr_op__insn \spr_op__fn_unit \spr_op__insn_type } + connect \spr_main_muxid \muxid +end +attribute \src "issuer_ls180.v:148862.1-150333.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.fus.alu0.alu_alu0.pipe1" +attribute \generator "nMigen" +module \pipe1 + attribute \src "issuer_ls180.v:150247.3-150288.6" + wire width 4 $0\alu_op__data_len$next[3:0]$8126 + attribute \src "issuer_ls180.v:150023.3-150024.49" + wire width 4 $0\alu_op__data_len[3:0] + attribute \src "issuer_ls180.v:150247.3-150288.6" + wire width 12 $0\alu_op__fn_unit$next[11:0]$8127 + attribute \src "issuer_ls180.v:149993.3-149994.47" + wire width 12 $0\alu_op__fn_unit[11:0] + attribute \src "issuer_ls180.v:150247.3-150288.6" + wire width 64 $0\alu_op__imm_data__data$next[63:0]$8128 + attribute \src "issuer_ls180.v:149995.3-149996.61" + wire width 64 $0\alu_op__imm_data__data[63:0] + attribute \src "issuer_ls180.v:150247.3-150288.6" + wire $0\alu_op__imm_data__ok$next[0:0]$8129 + attribute \src "issuer_ls180.v:149997.3-149998.57" + wire $0\alu_op__imm_data__ok[0:0] + attribute \src "issuer_ls180.v:150247.3-150288.6" + wire width 2 $0\alu_op__input_carry$next[1:0]$8130 + attribute \src "issuer_ls180.v:150015.3-150016.55" + wire width 2 $0\alu_op__input_carry[1:0] + attribute \src "issuer_ls180.v:150247.3-150288.6" + wire width 32 $0\alu_op__insn$next[31:0]$8131 + attribute \src "issuer_ls180.v:150025.3-150026.41" + wire width 32 $0\alu_op__insn[31:0] + attribute \src "issuer_ls180.v:150247.3-150288.6" + wire width 7 $0\alu_op__insn_type$next[6:0]$8132 + attribute \src "issuer_ls180.v:149991.3-149992.51" + wire width 7 $0\alu_op__insn_type[6:0] + attribute \src "issuer_ls180.v:150247.3-150288.6" + wire $0\alu_op__invert_in$next[0:0]$8133 + attribute \src "issuer_ls180.v:150007.3-150008.51" + wire $0\alu_op__invert_in[0:0] + attribute \src "issuer_ls180.v:150247.3-150288.6" + wire $0\alu_op__invert_out$next[0:0]$8134 + attribute \src "issuer_ls180.v:150011.3-150012.53" + wire $0\alu_op__invert_out[0:0] + attribute \src "issuer_ls180.v:150247.3-150288.6" + wire $0\alu_op__is_32bit$next[0:0]$8135 + attribute \src "issuer_ls180.v:150019.3-150020.49" + wire $0\alu_op__is_32bit[0:0] + attribute \src "issuer_ls180.v:150247.3-150288.6" + wire $0\alu_op__is_signed$next[0:0]$8136 + attribute \src "issuer_ls180.v:150021.3-150022.51" + wire $0\alu_op__is_signed[0:0] + attribute \src "issuer_ls180.v:150247.3-150288.6" + wire $0\alu_op__oe__oe$next[0:0]$8137 + attribute \src "issuer_ls180.v:150003.3-150004.45" + wire $0\alu_op__oe__oe[0:0] + attribute \src "issuer_ls180.v:150247.3-150288.6" + wire $0\alu_op__oe__ok$next[0:0]$8138 + attribute \src "issuer_ls180.v:150005.3-150006.45" + wire $0\alu_op__oe__ok[0:0] + attribute \src "issuer_ls180.v:150247.3-150288.6" + wire $0\alu_op__output_carry$next[0:0]$8139 + attribute \src "issuer_ls180.v:150017.3-150018.57" + wire $0\alu_op__output_carry[0:0] + attribute \src "issuer_ls180.v:150247.3-150288.6" + wire $0\alu_op__rc__ok$next[0:0]$8140 + attribute \src "issuer_ls180.v:150001.3-150002.45" + wire $0\alu_op__rc__ok[0:0] + attribute \src "issuer_ls180.v:150247.3-150288.6" + wire $0\alu_op__rc__rc$next[0:0]$8141 + attribute \src "issuer_ls180.v:149999.3-150000.45" + wire $0\alu_op__rc__rc[0:0] + attribute \src "issuer_ls180.v:150247.3-150288.6" + wire $0\alu_op__write_cr0$next[0:0]$8142 + attribute \src "issuer_ls180.v:150013.3-150014.51" + wire $0\alu_op__write_cr0[0:0] + attribute \src "issuer_ls180.v:150247.3-150288.6" + wire $0\alu_op__zero_a$next[0:0]$8143 + attribute \src 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width 2 $1\muxid[1:0] + attribute \src "issuer_ls180.v:150289.3-150307.6" + wire width 64 $1\o$next[63:0]$8171 + attribute \src "issuer_ls180.v:149894.14-149894.38" + wire width 64 $1\o[63:0] + attribute \src "issuer_ls180.v:150289.3-150307.6" + wire $1\o_ok$next[0:0]$8172 + attribute \src "issuer_ls180.v:149901.7-149901.18" + wire $1\o_ok[0:0] + attribute \src "issuer_ls180.v:150216.3-150233.6" + wire $1\r_busy$next[0:0]$8120 + attribute \src "issuer_ls180.v:149915.7-149915.20" + wire $1\r_busy[0:0] + attribute \src "issuer_ls180.v:150159.3-150177.6" + wire width 2 $1\xer_ca$next[1:0]$8104 + attribute \src "issuer_ls180.v:149924.13-149924.26" + wire width 2 $1\xer_ca[1:0] + attribute \src "issuer_ls180.v:150159.3-150177.6" + wire $1\xer_ca_ok$next[0:0]$8103 + attribute \src "issuer_ls180.v:149933.7-149933.23" + wire $1\xer_ca_ok[0:0] + attribute \src "issuer_ls180.v:150178.3-150196.6" + wire width 2 $1\xer_ov$next[1:0]$8109 + attribute \src "issuer_ls180.v:149940.13-149940.26" + wire width 2 $1\xer_ov[1:0] + attribute \src "issuer_ls180.v:150178.3-150196.6" + wire $1\xer_ov_ok$next[0:0]$8110 + attribute \src "issuer_ls180.v:149947.7-149947.23" + wire $1\xer_ov_ok[0:0] + attribute \src "issuer_ls180.v:150197.3-150215.6" + wire $1\xer_so$next[0:0]$8115 + attribute \src "issuer_ls180.v:149954.7-149954.20" + wire $1\xer_so[0:0] + attribute \src "issuer_ls180.v:150197.3-150215.6" + wire $1\xer_so_ok$next[0:0]$8116 + attribute \src "issuer_ls180.v:149963.7-149963.23" + wire $1\xer_so_ok[0:0] + attribute \src "issuer_ls180.v:150247.3-150288.6" + wire width 64 $2\alu_op__imm_data__data$next[63:0]$8162 + attribute \src "issuer_ls180.v:150247.3-150288.6" + wire $2\alu_op__imm_data__ok$next[0:0]$8163 + attribute \src "issuer_ls180.v:150247.3-150288.6" + wire $2\alu_op__oe__oe$next[0:0]$8164 + attribute \src "issuer_ls180.v:150247.3-150288.6" + wire $2\alu_op__oe__ok$next[0:0]$8165 + attribute \src "issuer_ls180.v:150247.3-150288.6" + wire $2\alu_op__rc__ok$next[0:0]$8166 + attribute \src "issuer_ls180.v:150247.3-150288.6" + wire $2\alu_op__rc__rc$next[0:0]$8167 + attribute \src "issuer_ls180.v:150140.3-150158.6" + wire $2\cr_a_ok$next[0:0]$8099 + attribute \src "issuer_ls180.v:150289.3-150307.6" + wire $2\o_ok$next[0:0]$8173 + attribute \src "issuer_ls180.v:150216.3-150233.6" + wire $2\r_busy$next[0:0]$8121 + attribute \src "issuer_ls180.v:150159.3-150177.6" + wire $2\xer_ca_ok$next[0:0]$8105 + attribute \src "issuer_ls180.v:150178.3-150196.6" + wire $2\xer_ov_ok$next[0:0]$8111 + attribute \src "issuer_ls180.v:150197.3-150215.6" + wire $2\xer_so_ok$next[0:0]$8117 + attribute \src "issuer_ls180.v:149970.18-149970.118" + wire $and$issuer_ls180.v:149970$8063_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" + wire \$67 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 output 21 \alu_op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 input 52 \alu_op__data_len$18 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \alu_op__data_len$86 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \alu_op__data_len$next + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 output 6 \alu_op__fn_unit + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 input 37 \alu_op__fn_unit$3 + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 \alu_op__fn_unit$71 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 \alu_op__fn_unit$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 output 7 \alu_op__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 input 38 \alu_op__imm_data__data$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \alu_op__imm_data__data$72 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \alu_op__imm_data__data$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 8 \alu_op__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 39 \alu_op__imm_data__ok$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__imm_data__ok$73 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__imm_data__ok$next + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 output 17 \alu_op__input_carry + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 input 48 \alu_op__input_carry$14 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \alu_op__input_carry$82 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \alu_op__input_carry$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 output 22 \alu_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 53 \alu_op__insn$19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \alu_op__insn$87 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \alu_op__insn$next + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 output 5 \alu_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 input 36 \alu_op__insn_type$2 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \alu_op__insn_type$70 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \alu_op__insn_type$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 13 \alu_op__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 44 \alu_op__invert_in$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__invert_in$78 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__invert_in$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 15 \alu_op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 46 \alu_op__invert_out$12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__invert_out$80 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__invert_out$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 19 \alu_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 50 \alu_op__is_32bit$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__is_32bit$84 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__is_32bit$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 20 \alu_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 51 \alu_op__is_signed$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__is_signed$85 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__is_signed$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 11 \alu_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__oe__oe$76 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 42 \alu_op__oe__oe$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__oe__oe$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 12 \alu_op__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__oe__ok$77 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 43 \alu_op__oe__ok$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__oe__ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 18 \alu_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 49 \alu_op__output_carry$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__output_carry$83 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__output_carry$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 10 \alu_op__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 41 \alu_op__rc__ok$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__rc__ok$75 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__rc__ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 9 \alu_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 40 \alu_op__rc__rc$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__rc__rc$74 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__rc__rc$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 16 \alu_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 47 \alu_op__write_cr0$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__write_cr0$81 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__write_cr0$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 14 \alu_op__zero_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 45 \alu_op__zero_a$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__zero_a$79 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__zero_a$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" + wire input 58 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" + wire input 1 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 4 output 25 \cr_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 4 \cr_a$90 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 4 \cr_a$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 26 \cr_a_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \cr_a_ok$91 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \cr_a_ok$next + attribute \src "issuer_ls180.v:148863.7-148863.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \input_alu_op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \input_alu_op__data_len$39 + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 \input_alu_op__fn_unit + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 \input_alu_op__fn_unit$24 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \input_alu_op__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \input_alu_op__imm_data__data$25 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_alu_op__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_alu_op__imm_data__ok$26 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \input_alu_op__input_carry + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \input_alu_op__input_carry$35 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \input_alu_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \input_alu_op__insn$40 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \input_alu_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \input_alu_op__insn_type$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_alu_op__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_alu_op__invert_in$31 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_alu_op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_alu_op__invert_out$33 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_alu_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_alu_op__is_32bit$37 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_alu_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_alu_op__is_signed$38 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_alu_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_alu_op__oe__oe$29 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_alu_op__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_alu_op__oe__ok$30 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_alu_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_alu_op__output_carry$36 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_alu_op__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_alu_op__rc__ok$28 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_alu_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_alu_op__rc__rc$27 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_alu_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_alu_op__write_cr0$34 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_alu_op__zero_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_alu_op__zero_a$32 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \input_muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \input_muxid$22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \input_ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \input_ra$41 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \input_rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \input_rb$42 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 2 \input_xer_ca + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 2 \input_xer_ca$44 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire \input_xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire \input_xer_so$43 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \main_alu_op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \main_alu_op__data_len$62 + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 \main_alu_op__fn_unit + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 \main_alu_op__fn_unit$47 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \main_alu_op__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \main_alu_op__imm_data__data$48 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_alu_op__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_alu_op__imm_data__ok$49 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \main_alu_op__input_carry + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \main_alu_op__input_carry$58 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \main_alu_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \main_alu_op__insn$63 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \main_alu_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \main_alu_op__insn_type$46 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_alu_op__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_alu_op__invert_in$54 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_alu_op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_alu_op__invert_out$56 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_alu_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_alu_op__is_32bit$60 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_alu_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_alu_op__is_signed$61 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_alu_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_alu_op__oe__oe$52 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_alu_op__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_alu_op__oe__ok$53 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_alu_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_alu_op__output_carry$59 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_alu_op__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_alu_op__rc__ok$51 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_alu_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_alu_op__rc__rc$50 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_alu_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_alu_op__write_cr0$57 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_alu_op__zero_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_alu_op__zero_a$55 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 4 \main_cr_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \main_cr_a_ok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \main_muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \main_muxid$45 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 \main_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \main_o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \main_ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \main_rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 2 \main_xer_ca + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 2 \main_xer_ca$64 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \main_xer_ca_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 2 \main_xer_ov + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \main_xer_ov_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire \main_xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \main_xer_so$65 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 output 4 \muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 input 35 \muxid$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \muxid$69 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \muxid$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:619" + wire \n_i_rdy_data + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" + wire input 3 \n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" + wire output 2 \n_valid_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 output 23 \o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 \o$88 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 \o$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 24 \o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \o_ok$89 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \o_ok$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" + wire output 34 \p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" + wire input 33 \p_valid_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:621" + wire \p_valid_i$66 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" + wire \p_valid_i_p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615" + wire \r_busy + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615" + wire \r_busy$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 54 \ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 55 \rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 2 output 27 \xer_ca + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 2 input 57 \xer_ca$21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 2 \xer_ca$92 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 2 \xer_ca$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 28 \xer_ca_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \xer_ca_ok$93 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \xer_ca_ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 2 output 29 \xer_ov + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 2 \xer_ov$94 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 2 \xer_ov$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 30 \xer_ov_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \xer_ov_ok$95 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \xer_ov_ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 31 \xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire input 56 \xer_so$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \xer_so$96 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \xer_so$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 32 \xer_so_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \xer_so_ok$97 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \xer_so_ok$98 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \xer_so_ok$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" + cell $and $and$issuer_ls180.v:149970$8063 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \p_valid_i$66 + connect \B \p_ready_o + connect \Y $and$issuer_ls180.v:149970$8063_Y + end + attribute \module_not_derived 1 + attribute \src "issuer_ls180.v:150031.11-150078.4" + cell \input \input + connect \alu_op__data_len \input_alu_op__data_len + connect \alu_op__data_len$18 \input_alu_op__data_len$39 + connect \alu_op__fn_unit \input_alu_op__fn_unit + connect \alu_op__fn_unit$3 \input_alu_op__fn_unit$24 + connect \alu_op__imm_data__data \input_alu_op__imm_data__data + connect \alu_op__imm_data__data$4 \input_alu_op__imm_data__data$25 + connect \alu_op__imm_data__ok \input_alu_op__imm_data__ok + connect \alu_op__imm_data__ok$5 \input_alu_op__imm_data__ok$26 + connect \alu_op__input_carry \input_alu_op__input_carry + connect \alu_op__input_carry$14 \input_alu_op__input_carry$35 + connect \alu_op__insn \input_alu_op__insn + connect \alu_op__insn$19 \input_alu_op__insn$40 + connect \alu_op__insn_type \input_alu_op__insn_type + connect \alu_op__insn_type$2 \input_alu_op__insn_type$23 + connect \alu_op__invert_in \input_alu_op__invert_in + connect \alu_op__invert_in$10 \input_alu_op__invert_in$31 + connect \alu_op__invert_out \input_alu_op__invert_out + connect \alu_op__invert_out$12 \input_alu_op__invert_out$33 + connect \alu_op__is_32bit \input_alu_op__is_32bit + connect \alu_op__is_32bit$16 \input_alu_op__is_32bit$37 + connect \alu_op__is_signed \input_alu_op__is_signed + connect \alu_op__is_signed$17 \input_alu_op__is_signed$38 + connect \alu_op__oe__oe \input_alu_op__oe__oe + connect \alu_op__oe__oe$8 \input_alu_op__oe__oe$29 + connect \alu_op__oe__ok \input_alu_op__oe__ok + connect \alu_op__oe__ok$9 \input_alu_op__oe__ok$30 + connect \alu_op__output_carry \input_alu_op__output_carry + connect \alu_op__output_carry$15 \input_alu_op__output_carry$36 + connect \alu_op__rc__ok \input_alu_op__rc__ok + connect \alu_op__rc__ok$7 \input_alu_op__rc__ok$28 + connect \alu_op__rc__rc \input_alu_op__rc__rc + connect \alu_op__rc__rc$6 \input_alu_op__rc__rc$27 + connect \alu_op__write_cr0 \input_alu_op__write_cr0 + connect \alu_op__write_cr0$13 \input_alu_op__write_cr0$34 + connect \alu_op__zero_a \input_alu_op__zero_a + connect \alu_op__zero_a$11 \input_alu_op__zero_a$32 + connect \muxid \input_muxid + connect \muxid$1 \input_muxid$22 + connect \ra \input_ra + connect \ra$20 \input_ra$41 + connect \rb \input_rb + connect \rb$21 \input_rb$42 + connect \xer_ca \input_xer_ca + connect \xer_ca$23 \input_xer_ca$44 + connect \xer_so \input_xer_so + connect \xer_so$22 \input_xer_so$43 + end + attribute \module_not_derived 1 + attribute \src "issuer_ls180.v:150079.8-150131.4" + cell \main \main + connect \alu_op__data_len \main_alu_op__data_len + connect \alu_op__data_len$18 \main_alu_op__data_len$62 + connect \alu_op__fn_unit \main_alu_op__fn_unit + connect \alu_op__fn_unit$3 \main_alu_op__fn_unit$47 + connect \alu_op__imm_data__data \main_alu_op__imm_data__data + connect \alu_op__imm_data__data$4 \main_alu_op__imm_data__data$48 + connect \alu_op__imm_data__ok \main_alu_op__imm_data__ok + connect \alu_op__imm_data__ok$5 \main_alu_op__imm_data__ok$49 + connect \alu_op__input_carry \main_alu_op__input_carry + connect \alu_op__input_carry$14 \main_alu_op__input_carry$58 + connect \alu_op__insn \main_alu_op__insn + connect \alu_op__insn$19 \main_alu_op__insn$63 + connect \alu_op__insn_type \main_alu_op__insn_type + connect \alu_op__insn_type$2 \main_alu_op__insn_type$46 + connect \alu_op__invert_in \main_alu_op__invert_in + connect \alu_op__invert_in$10 \main_alu_op__invert_in$54 + connect \alu_op__invert_out \main_alu_op__invert_out + connect \alu_op__invert_out$12 \main_alu_op__invert_out$56 + connect \alu_op__is_32bit \main_alu_op__is_32bit + connect \alu_op__is_32bit$16 \main_alu_op__is_32bit$60 + connect \alu_op__is_signed \main_alu_op__is_signed + connect \alu_op__is_signed$17 \main_alu_op__is_signed$61 + connect \alu_op__oe__oe \main_alu_op__oe__oe + connect \alu_op__oe__oe$8 \main_alu_op__oe__oe$52 + connect \alu_op__oe__ok \main_alu_op__oe__ok + connect \alu_op__oe__ok$9 \main_alu_op__oe__ok$53 + connect \alu_op__output_carry \main_alu_op__output_carry + connect \alu_op__output_carry$15 \main_alu_op__output_carry$59 + connect \alu_op__rc__ok \main_alu_op__rc__ok + connect \alu_op__rc__ok$7 \main_alu_op__rc__ok$51 + connect \alu_op__rc__rc \main_alu_op__rc__rc + connect \alu_op__rc__rc$6 \main_alu_op__rc__rc$50 + connect \alu_op__write_cr0 \main_alu_op__write_cr0 + connect \alu_op__write_cr0$13 \main_alu_op__write_cr0$57 + connect \alu_op__zero_a \main_alu_op__zero_a + connect \alu_op__zero_a$11 \main_alu_op__zero_a$55 + connect \cr_a \main_cr_a + connect \cr_a_ok \main_cr_a_ok + connect \muxid \main_muxid + connect \muxid$1 \main_muxid$45 + connect \o \main_o + connect \o_ok \main_o_ok + connect \ra \main_ra + connect \rb \main_rb + connect \xer_ca \main_xer_ca + connect \xer_ca$20 \main_xer_ca$64 + connect \xer_ca_ok \main_xer_ca_ok + connect \xer_ov \main_xer_ov + connect \xer_ov_ok \main_xer_ov_ok + connect \xer_so \main_xer_so + connect \xer_so$21 \main_xer_so$65 + end + attribute \module_not_derived 1 + attribute \src "issuer_ls180.v:150132.9-150135.4" + cell \n$2 \n + connect \n_ready_i \n_ready_i + connect \n_valid_o \n_valid_o + end + attribute \module_not_derived 1 + attribute \src "issuer_ls180.v:150136.9-150139.4" + cell \p$1 \p + connect \p_ready_o \p_ready_o + connect \p_valid_i \p_valid_i + end + attribute \src "issuer_ls180.v:148863.7-148863.20" + process $proc$issuer_ls180.v:148863$8174 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "issuer_ls180.v:148868.13-148868.36" + process $proc$issuer_ls180.v:148868$8175 + assign { } { } + assign $1\alu_op__data_len[3:0] 4'0000 + sync always + sync init + update \alu_op__data_len $1\alu_op__data_len[3:0] + end + attribute \src "issuer_ls180.v:148890.14-148890.39" + process $proc$issuer_ls180.v:148890$8176 + assign { } { } + assign $1\alu_op__fn_unit[11:0] 12'000000000000 + sync always + sync init + update \alu_op__fn_unit $1\alu_op__fn_unit[11:0] + end + attribute \src "issuer_ls180.v:148925.14-148925.59" + process $proc$issuer_ls180.v:148925$8177 + assign { } { } + assign $1\alu_op__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \alu_op__imm_data__data $1\alu_op__imm_data__data[63:0] + end + attribute \src "issuer_ls180.v:148934.7-148934.34" + process $proc$issuer_ls180.v:148934$8178 + assign { } { } + assign $1\alu_op__imm_data__ok[0:0] 1'0 + sync always + sync init + update \alu_op__imm_data__ok $1\alu_op__imm_data__ok[0:0] + end + attribute \src "issuer_ls180.v:148947.13-148947.39" + process $proc$issuer_ls180.v:148947$8179 + assign { } { } + assign $1\alu_op__input_carry[1:0] 2'00 + sync always + sync init + update \alu_op__input_carry $1\alu_op__input_carry[1:0] + end + attribute \src "issuer_ls180.v:148964.14-148964.34" + process $proc$issuer_ls180.v:148964$8180 + assign { } { } + assign $1\alu_op__insn[31:0] 0 + sync always + sync init + update \alu_op__insn $1\alu_op__insn[31:0] + end + attribute \src "issuer_ls180.v:149047.13-149047.38" + process $proc$issuer_ls180.v:149047$8181 + assign { } { } + assign $1\alu_op__insn_type[6:0] 7'0000000 + sync always + sync init + update \alu_op__insn_type $1\alu_op__insn_type[6:0] + end + attribute \src "issuer_ls180.v:149204.7-149204.31" + process $proc$issuer_ls180.v:149204$8182 + assign { } { } + assign $1\alu_op__invert_in[0:0] 1'0 + sync always + sync init + update \alu_op__invert_in $1\alu_op__invert_in[0:0] + end + attribute \src "issuer_ls180.v:149213.7-149213.32" + process $proc$issuer_ls180.v:149213$8183 + assign { } { } + assign $1\alu_op__invert_out[0:0] 1'0 + sync always + sync init + update \alu_op__invert_out $1\alu_op__invert_out[0:0] + end + attribute \src "issuer_ls180.v:149222.7-149222.30" + process $proc$issuer_ls180.v:149222$8184 + assign { } { } + assign $1\alu_op__is_32bit[0:0] 1'0 + sync always + sync init + update \alu_op__is_32bit $1\alu_op__is_32bit[0:0] + end + attribute \src "issuer_ls180.v:149231.7-149231.31" + process $proc$issuer_ls180.v:149231$8185 + assign { } { } + assign $1\alu_op__is_signed[0:0] 1'0 + sync always + sync init + update \alu_op__is_signed $1\alu_op__is_signed[0:0] + end + attribute \src "issuer_ls180.v:149240.7-149240.28" + process $proc$issuer_ls180.v:149240$8186 + assign { } { } + assign $1\alu_op__oe__oe[0:0] 1'0 + sync always + sync init + update \alu_op__oe__oe $1\alu_op__oe__oe[0:0] + end + attribute \src "issuer_ls180.v:149249.7-149249.28" + process $proc$issuer_ls180.v:149249$8187 + assign { } { } + assign $1\alu_op__oe__ok[0:0] 1'0 + sync always + sync init + update \alu_op__oe__ok $1\alu_op__oe__ok[0:0] + end + attribute \src "issuer_ls180.v:149258.7-149258.34" + process $proc$issuer_ls180.v:149258$8188 + assign { } { } + assign $1\alu_op__output_carry[0:0] 1'0 + sync always + sync init + update \alu_op__output_carry $1\alu_op__output_carry[0:0] + end + attribute \src "issuer_ls180.v:149267.7-149267.28" + process $proc$issuer_ls180.v:149267$8189 + assign { } { } + assign $1\alu_op__rc__ok[0:0] 1'0 + sync always + sync init + update \alu_op__rc__ok $1\alu_op__rc__ok[0:0] + end + attribute \src "issuer_ls180.v:149276.7-149276.28" + process $proc$issuer_ls180.v:149276$8190 + assign { } { } + assign $1\alu_op__rc__rc[0:0] 1'0 + sync always + sync init + update \alu_op__rc__rc $1\alu_op__rc__rc[0:0] + end + attribute \src "issuer_ls180.v:149285.7-149285.31" + process $proc$issuer_ls180.v:149285$8191 + assign { } { } + assign $1\alu_op__write_cr0[0:0] 1'0 + sync always + sync init + update \alu_op__write_cr0 $1\alu_op__write_cr0[0:0] + end + attribute \src "issuer_ls180.v:149294.7-149294.28" + process $proc$issuer_ls180.v:149294$8192 + assign { } { } + assign $1\alu_op__zero_a[0:0] 1'0 + sync always + sync init + update \alu_op__zero_a $1\alu_op__zero_a[0:0] + end + attribute \src "issuer_ls180.v:149307.13-149307.24" + process $proc$issuer_ls180.v:149307$8193 + assign { } { } + assign $1\cr_a[3:0] 4'0000 + sync always + sync init + update \cr_a $1\cr_a[3:0] + end + attribute \src "issuer_ls180.v:149314.7-149314.21" + process $proc$issuer_ls180.v:149314$8194 + assign { } { } + assign $1\cr_a_ok[0:0] 1'0 + sync always + sync init + update \cr_a_ok $1\cr_a_ok[0:0] + end + attribute \src "issuer_ls180.v:149879.13-149879.25" + process $proc$issuer_ls180.v:149879$8195 + assign { } { } + assign $1\muxid[1:0] 2'00 + sync always + sync init + update \muxid $1\muxid[1:0] + end + attribute \src "issuer_ls180.v:149894.14-149894.38" + process $proc$issuer_ls180.v:149894$8196 + assign { } { } + assign $1\o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \o $1\o[63:0] + end + attribute \src "issuer_ls180.v:149901.7-149901.18" + process $proc$issuer_ls180.v:149901$8197 + assign { } { } + assign $1\o_ok[0:0] 1'0 + sync always + sync init + update \o_ok $1\o_ok[0:0] + end + attribute \src "issuer_ls180.v:149915.7-149915.20" + process $proc$issuer_ls180.v:149915$8198 + assign { } { } + assign $1\r_busy[0:0] 1'0 + sync always + sync init + update \r_busy $1\r_busy[0:0] + end + attribute \src "issuer_ls180.v:149924.13-149924.26" + process $proc$issuer_ls180.v:149924$8199 + assign { } { } + assign $1\xer_ca[1:0] 2'00 + sync always + sync init + update \xer_ca $1\xer_ca[1:0] + end + attribute \src "issuer_ls180.v:149933.7-149933.23" + process $proc$issuer_ls180.v:149933$8200 + assign { } { } + assign $1\xer_ca_ok[0:0] 1'0 + sync always + sync init + update \xer_ca_ok $1\xer_ca_ok[0:0] + end + attribute \src "issuer_ls180.v:149940.13-149940.26" + process $proc$issuer_ls180.v:149940$8201 + assign { } { } + assign $1\xer_ov[1:0] 2'00 + sync always + sync init + update \xer_ov $1\xer_ov[1:0] + end + attribute \src "issuer_ls180.v:149947.7-149947.23" + process $proc$issuer_ls180.v:149947$8202 + assign { } { } + assign $1\xer_ov_ok[0:0] 1'0 + sync always + sync init + update \xer_ov_ok $1\xer_ov_ok[0:0] + end + attribute \src "issuer_ls180.v:149954.7-149954.20" + process $proc$issuer_ls180.v:149954$8203 + assign { } { } + assign $1\xer_so[0:0] 1'0 + sync always + sync init + update \xer_so $1\xer_so[0:0] + end + attribute \src "issuer_ls180.v:149963.7-149963.23" + process $proc$issuer_ls180.v:149963$8204 + assign { } { } + assign $1\xer_so_ok[0:0] 1'0 + sync always + sync init + update \xer_so_ok $1\xer_so_ok[0:0] + end + attribute \src "issuer_ls180.v:149971.3-149972.29" + process $proc$issuer_ls180.v:149971$8064 + assign { } { } + assign $0\xer_so[0:0] \xer_so$next + sync posedge \coresync_clk + update \xer_so $0\xer_so[0:0] + end + attribute \src "issuer_ls180.v:149973.3-149974.35" + process $proc$issuer_ls180.v:149973$8065 + assign { } { } + assign $0\xer_so_ok[0:0] \xer_so_ok$next + sync posedge \coresync_clk + update \xer_so_ok $0\xer_so_ok[0:0] + end + attribute \src "issuer_ls180.v:149975.3-149976.29" + process $proc$issuer_ls180.v:149975$8066 + assign { } { } + assign $0\xer_ov[1:0] \xer_ov$next + sync posedge \coresync_clk + update \xer_ov $0\xer_ov[1:0] + end + attribute \src "issuer_ls180.v:149977.3-149978.35" + process $proc$issuer_ls180.v:149977$8067 + assign { } { } + assign $0\xer_ov_ok[0:0] \xer_ov_ok$next + sync posedge \coresync_clk + update \xer_ov_ok $0\xer_ov_ok[0:0] + end + attribute \src "issuer_ls180.v:149979.3-149980.29" + process $proc$issuer_ls180.v:149979$8068 + assign { } { } + assign $0\xer_ca[1:0] \xer_ca$next + sync posedge \coresync_clk + update \xer_ca $0\xer_ca[1:0] + end + attribute \src "issuer_ls180.v:149981.3-149982.35" + process $proc$issuer_ls180.v:149981$8069 + assign { } { } + assign $0\xer_ca_ok[0:0] \xer_ca_ok$next + sync posedge \coresync_clk + update \xer_ca_ok $0\xer_ca_ok[0:0] + end + attribute \src "issuer_ls180.v:149983.3-149984.25" + process $proc$issuer_ls180.v:149983$8070 + assign { } { } + assign $0\cr_a[3:0] \cr_a$next + sync posedge \coresync_clk + update \cr_a $0\cr_a[3:0] + end + attribute \src "issuer_ls180.v:149985.3-149986.31" + process $proc$issuer_ls180.v:149985$8071 + assign { } { } + assign $0\cr_a_ok[0:0] \cr_a_ok$next + sync posedge \coresync_clk + update \cr_a_ok $0\cr_a_ok[0:0] + end + attribute \src "issuer_ls180.v:149987.3-149988.19" + process $proc$issuer_ls180.v:149987$8072 + assign { } { } + assign $0\o[63:0] \o$next + sync posedge \coresync_clk + update \o $0\o[63:0] + end + attribute \src "issuer_ls180.v:149989.3-149990.25" + process $proc$issuer_ls180.v:149989$8073 + assign { } { } + assign $0\o_ok[0:0] \o_ok$next + sync posedge \coresync_clk + update \o_ok $0\o_ok[0:0] + end + attribute \src "issuer_ls180.v:149991.3-149992.51" + process $proc$issuer_ls180.v:149991$8074 + assign { } { } + assign $0\alu_op__insn_type[6:0] \alu_op__insn_type$next + sync posedge \coresync_clk + update \alu_op__insn_type $0\alu_op__insn_type[6:0] + end + attribute \src "issuer_ls180.v:149993.3-149994.47" + process $proc$issuer_ls180.v:149993$8075 + assign { } { } + assign $0\alu_op__fn_unit[11:0] \alu_op__fn_unit$next + sync posedge \coresync_clk + update \alu_op__fn_unit $0\alu_op__fn_unit[11:0] + end + attribute \src "issuer_ls180.v:149995.3-149996.61" + process $proc$issuer_ls180.v:149995$8076 + assign { } { } + assign $0\alu_op__imm_data__data[63:0] \alu_op__imm_data__data$next + sync posedge \coresync_clk + update \alu_op__imm_data__data $0\alu_op__imm_data__data[63:0] + end + attribute \src "issuer_ls180.v:149997.3-149998.57" + process $proc$issuer_ls180.v:149997$8077 + assign { } { } + assign $0\alu_op__imm_data__ok[0:0] \alu_op__imm_data__ok$next + sync posedge \coresync_clk + update \alu_op__imm_data__ok $0\alu_op__imm_data__ok[0:0] + end + attribute \src "issuer_ls180.v:149999.3-150000.45" + process $proc$issuer_ls180.v:149999$8078 + assign { } { } + assign $0\alu_op__rc__rc[0:0] \alu_op__rc__rc$next + sync posedge \coresync_clk + update \alu_op__rc__rc $0\alu_op__rc__rc[0:0] + end + attribute \src "issuer_ls180.v:150001.3-150002.45" + process $proc$issuer_ls180.v:150001$8079 + assign { } { } + assign $0\alu_op__rc__ok[0:0] \alu_op__rc__ok$next + sync posedge \coresync_clk + update \alu_op__rc__ok $0\alu_op__rc__ok[0:0] + end + attribute \src "issuer_ls180.v:150003.3-150004.45" + process $proc$issuer_ls180.v:150003$8080 + assign { } { } + assign $0\alu_op__oe__oe[0:0] \alu_op__oe__oe$next + sync posedge \coresync_clk + update \alu_op__oe__oe $0\alu_op__oe__oe[0:0] + end + attribute \src "issuer_ls180.v:150005.3-150006.45" + process $proc$issuer_ls180.v:150005$8081 + assign { } { } + assign $0\alu_op__oe__ok[0:0] \alu_op__oe__ok$next + sync posedge \coresync_clk + update \alu_op__oe__ok $0\alu_op__oe__ok[0:0] + end + attribute \src "issuer_ls180.v:150007.3-150008.51" + process $proc$issuer_ls180.v:150007$8082 + assign { } { } + assign $0\alu_op__invert_in[0:0] \alu_op__invert_in$next + sync posedge \coresync_clk + update \alu_op__invert_in $0\alu_op__invert_in[0:0] + end + attribute \src "issuer_ls180.v:150009.3-150010.45" + process $proc$issuer_ls180.v:150009$8083 + assign { } { } + assign $0\alu_op__zero_a[0:0] \alu_op__zero_a$next + sync posedge \coresync_clk + update \alu_op__zero_a $0\alu_op__zero_a[0:0] + end + attribute \src "issuer_ls180.v:150011.3-150012.53" + process $proc$issuer_ls180.v:150011$8084 + assign { } { } + assign $0\alu_op__invert_out[0:0] \alu_op__invert_out$next + sync posedge \coresync_clk + update \alu_op__invert_out $0\alu_op__invert_out[0:0] + end + attribute \src "issuer_ls180.v:150013.3-150014.51" + process $proc$issuer_ls180.v:150013$8085 + assign { } { } + assign $0\alu_op__write_cr0[0:0] \alu_op__write_cr0$next + sync posedge \coresync_clk + update \alu_op__write_cr0 $0\alu_op__write_cr0[0:0] + end + attribute \src "issuer_ls180.v:150015.3-150016.55" + process $proc$issuer_ls180.v:150015$8086 + assign { } { } + assign $0\alu_op__input_carry[1:0] \alu_op__input_carry$next + sync posedge \coresync_clk + update \alu_op__input_carry $0\alu_op__input_carry[1:0] + end + attribute \src "issuer_ls180.v:150017.3-150018.57" + process $proc$issuer_ls180.v:150017$8087 + assign { } { } + assign $0\alu_op__output_carry[0:0] \alu_op__output_carry$next + sync posedge \coresync_clk + update \alu_op__output_carry $0\alu_op__output_carry[0:0] + end + attribute \src "issuer_ls180.v:150019.3-150020.49" + process $proc$issuer_ls180.v:150019$8088 + assign { } { } + assign $0\alu_op__is_32bit[0:0] \alu_op__is_32bit$next + sync posedge \coresync_clk + update \alu_op__is_32bit $0\alu_op__is_32bit[0:0] + end + attribute \src "issuer_ls180.v:150021.3-150022.51" + process $proc$issuer_ls180.v:150021$8089 + assign { } { } + assign $0\alu_op__is_signed[0:0] \alu_op__is_signed$next + sync posedge \coresync_clk + update \alu_op__is_signed $0\alu_op__is_signed[0:0] + end + attribute \src "issuer_ls180.v:150023.3-150024.49" + process $proc$issuer_ls180.v:150023$8090 + assign { } { } + assign $0\alu_op__data_len[3:0] \alu_op__data_len$next + sync posedge \coresync_clk + update \alu_op__data_len $0\alu_op__data_len[3:0] + end + attribute \src "issuer_ls180.v:150025.3-150026.41" + process $proc$issuer_ls180.v:150025$8091 + assign { } { } + assign $0\alu_op__insn[31:0] \alu_op__insn$next + sync posedge \coresync_clk + update \alu_op__insn $0\alu_op__insn[31:0] + end + attribute \src "issuer_ls180.v:150027.3-150028.27" + process $proc$issuer_ls180.v:150027$8092 + assign { } { } + assign $0\muxid[1:0] \muxid$next + sync posedge \coresync_clk + update \muxid $0\muxid[1:0] + end + attribute \src "issuer_ls180.v:150029.3-150030.29" + process $proc$issuer_ls180.v:150029$8093 + assign { } { } + assign $0\r_busy[0:0] \r_busy$next + sync posedge \coresync_clk + update \r_busy $0\r_busy[0:0] + end + attribute \src "issuer_ls180.v:150140.3-150158.6" + process $proc$issuer_ls180.v:150140$8094 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\cr_a$next[3:0]$8095 $1\cr_a$next[3:0]$8097 + assign { } { } + assign $0\cr_a_ok$next[0:0]$8096 $2\cr_a_ok$next[0:0]$8099 + attribute \src "issuer_ls180.v:150141.5-150141.29" + switch \initial + attribute \src "issuer_ls180.v:150141.9-150141.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'-1 + assign { } { } + assign { } { } + assign { $1\cr_a_ok$next[0:0]$8098 $1\cr_a$next[3:0]$8097 } { \cr_a_ok$91 \cr_a$90 } + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'1- + assign { } { } + assign { } { } + assign { $1\cr_a_ok$next[0:0]$8098 $1\cr_a$next[3:0]$8097 } { \cr_a_ok$91 \cr_a$90 } + case + assign $1\cr_a$next[3:0]$8097 \cr_a + assign $1\cr_a_ok$next[0:0]$8098 \cr_a_ok + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\cr_a_ok$next[0:0]$8099 1'0 + case + assign $2\cr_a_ok$next[0:0]$8099 $1\cr_a_ok$next[0:0]$8098 + end + sync always + update \cr_a$next $0\cr_a$next[3:0]$8095 + update \cr_a_ok$next $0\cr_a_ok$next[0:0]$8096 + end + attribute \src "issuer_ls180.v:150159.3-150177.6" + process $proc$issuer_ls180.v:150159$8100 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\xer_ca$next[1:0]$8102 $1\xer_ca$next[1:0]$8104 + assign $0\xer_ca_ok$next[0:0]$8101 $2\xer_ca_ok$next[0:0]$8105 + attribute \src "issuer_ls180.v:150160.5-150160.29" + switch \initial + attribute \src "issuer_ls180.v:150160.9-150160.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'-1 + assign { } { } + assign { } { } + assign { $1\xer_ca_ok$next[0:0]$8103 $1\xer_ca$next[1:0]$8104 } { \xer_ca_ok$93 \xer_ca$92 } + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'1- + assign { } { } + assign { } { } + assign { $1\xer_ca_ok$next[0:0]$8103 $1\xer_ca$next[1:0]$8104 } { \xer_ca_ok$93 \xer_ca$92 } + case + assign $1\xer_ca_ok$next[0:0]$8103 \xer_ca_ok + assign $1\xer_ca$next[1:0]$8104 \xer_ca + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\xer_ca_ok$next[0:0]$8105 1'0 + case + assign $2\xer_ca_ok$next[0:0]$8105 $1\xer_ca_ok$next[0:0]$8103 + end + sync always + update \xer_ca_ok$next $0\xer_ca_ok$next[0:0]$8101 + update \xer_ca$next $0\xer_ca$next[1:0]$8102 + end + attribute \src "issuer_ls180.v:150178.3-150196.6" + process $proc$issuer_ls180.v:150178$8106 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\xer_ov$next[1:0]$8107 $1\xer_ov$next[1:0]$8109 + assign { } { } + assign $0\xer_ov_ok$next[0:0]$8108 $2\xer_ov_ok$next[0:0]$8111 + attribute \src "issuer_ls180.v:150179.5-150179.29" + switch \initial + attribute \src "issuer_ls180.v:150179.9-150179.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'-1 + assign { } { } + assign { } { } + assign { $1\xer_ov_ok$next[0:0]$8110 $1\xer_ov$next[1:0]$8109 } { \xer_ov_ok$95 \xer_ov$94 } + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'1- + assign { } { } + assign { } { } + assign { $1\xer_ov_ok$next[0:0]$8110 $1\xer_ov$next[1:0]$8109 } { \xer_ov_ok$95 \xer_ov$94 } + case + assign $1\xer_ov$next[1:0]$8109 \xer_ov + assign $1\xer_ov_ok$next[0:0]$8110 \xer_ov_ok + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\xer_ov_ok$next[0:0]$8111 1'0 + case + assign $2\xer_ov_ok$next[0:0]$8111 $1\xer_ov_ok$next[0:0]$8110 + end + sync always + update \xer_ov$next $0\xer_ov$next[1:0]$8107 + update \xer_ov_ok$next $0\xer_ov_ok$next[0:0]$8108 + end + attribute \src "issuer_ls180.v:150197.3-150215.6" + process $proc$issuer_ls180.v:150197$8112 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\xer_so$next[0:0]$8113 $1\xer_so$next[0:0]$8115 + assign { } { } + assign $0\xer_so_ok$next[0:0]$8114 $2\xer_so_ok$next[0:0]$8117 + attribute \src "issuer_ls180.v:150198.5-150198.29" + switch \initial + attribute \src "issuer_ls180.v:150198.9-150198.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'-1 + assign { } { } + assign { } { } + assign { $1\xer_so_ok$next[0:0]$8116 $1\xer_so$next[0:0]$8115 } { \xer_so_ok$97 \xer_so$96 } + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'1- + assign { } { } + assign { } { } + assign { $1\xer_so_ok$next[0:0]$8116 $1\xer_so$next[0:0]$8115 } { \xer_so_ok$97 \xer_so$96 } + case + assign $1\xer_so$next[0:0]$8115 \xer_so + assign $1\xer_so_ok$next[0:0]$8116 \xer_so_ok + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\xer_so_ok$next[0:0]$8117 1'0 + case + assign $2\xer_so_ok$next[0:0]$8117 $1\xer_so_ok$next[0:0]$8116 + end + sync always + update \xer_so$next $0\xer_so$next[0:0]$8113 + update \xer_so_ok$next $0\xer_so_ok$next[0:0]$8114 + end + attribute \src "issuer_ls180.v:150216.3-150233.6" + process $proc$issuer_ls180.v:150216$8118 + assign { } { } + assign { } { } + assign { } { } + assign $0\r_busy$next[0:0]$8119 $2\r_busy$next[0:0]$8121 + attribute \src "issuer_ls180.v:150217.5-150217.29" + switch \initial + attribute \src "issuer_ls180.v:150217.9-150217.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\r_busy$next[0:0]$8120 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\r_busy$next[0:0]$8120 1'0 + case + assign $1\r_busy$next[0:0]$8120 \r_busy + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\r_busy$next[0:0]$8121 1'0 + case + assign $2\r_busy$next[0:0]$8121 $1\r_busy$next[0:0]$8120 + end + sync always + update \r_busy$next $0\r_busy$next[0:0]$8119 + end + attribute \src "issuer_ls180.v:150234.3-150246.6" + process $proc$issuer_ls180.v:150234$8122 + assign { } { } + assign { } { } + assign $0\muxid$next[1:0]$8123 $1\muxid$next[1:0]$8124 + attribute \src "issuer_ls180.v:150235.5-150235.29" + switch \initial + attribute \src "issuer_ls180.v:150235.9-150235.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\muxid$next[1:0]$8124 \muxid$69 + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\muxid$next[1:0]$8124 \muxid$69 + case + assign $1\muxid$next[1:0]$8124 \muxid + end + sync always + update \muxid$next $0\muxid$next[1:0]$8123 + end + attribute \src "issuer_ls180.v:150247.3-150288.6" + process $proc$issuer_ls180.v:150247$8125 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\alu_op__data_len$next[3:0]$8126 $1\alu_op__data_len$next[3:0]$8144 + assign $0\alu_op__fn_unit$next[11:0]$8127 $1\alu_op__fn_unit$next[11:0]$8145 + assign { } { } + assign { } { } + assign $0\alu_op__input_carry$next[1:0]$8130 $1\alu_op__input_carry$next[1:0]$8148 + assign $0\alu_op__insn$next[31:0]$8131 $1\alu_op__insn$next[31:0]$8149 + assign $0\alu_op__insn_type$next[6:0]$8132 $1\alu_op__insn_type$next[6:0]$8150 + assign $0\alu_op__invert_in$next[0:0]$8133 $1\alu_op__invert_in$next[0:0]$8151 + assign $0\alu_op__invert_out$next[0:0]$8134 $1\alu_op__invert_out$next[0:0]$8152 + assign $0\alu_op__is_32bit$next[0:0]$8135 $1\alu_op__is_32bit$next[0:0]$8153 + assign $0\alu_op__is_signed$next[0:0]$8136 $1\alu_op__is_signed$next[0:0]$8154 + assign { } { } + assign { } { } + assign $0\alu_op__output_carry$next[0:0]$8139 $1\alu_op__output_carry$next[0:0]$8157 + assign { } { } + assign { } { } + assign $0\alu_op__write_cr0$next[0:0]$8142 $1\alu_op__write_cr0$next[0:0]$8160 + assign $0\alu_op__zero_a$next[0:0]$8143 $1\alu_op__zero_a$next[0:0]$8161 + assign $0\alu_op__imm_data__data$next[63:0]$8128 $2\alu_op__imm_data__data$next[63:0]$8162 + assign $0\alu_op__imm_data__ok$next[0:0]$8129 $2\alu_op__imm_data__ok$next[0:0]$8163 + assign $0\alu_op__oe__oe$next[0:0]$8137 $2\alu_op__oe__oe$next[0:0]$8164 + assign $0\alu_op__oe__ok$next[0:0]$8138 $2\alu_op__oe__ok$next[0:0]$8165 + assign $0\alu_op__rc__ok$next[0:0]$8140 $2\alu_op__rc__ok$next[0:0]$8166 + assign $0\alu_op__rc__rc$next[0:0]$8141 $2\alu_op__rc__rc$next[0:0]$8167 + attribute \src "issuer_ls180.v:150248.5-150248.29" + switch \initial + attribute \src "issuer_ls180.v:150248.9-150248.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'-1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { $1\alu_op__insn$next[31:0]$8149 $1\alu_op__data_len$next[3:0]$8144 $1\alu_op__is_signed$next[0:0]$8154 $1\alu_op__is_32bit$next[0:0]$8153 $1\alu_op__output_carry$next[0:0]$8157 $1\alu_op__input_carry$next[1:0]$8148 $1\alu_op__write_cr0$next[0:0]$8160 $1\alu_op__invert_out$next[0:0]$8152 $1\alu_op__zero_a$next[0:0]$8161 $1\alu_op__invert_in$next[0:0]$8151 $1\alu_op__oe__ok$next[0:0]$8156 $1\alu_op__oe__oe$next[0:0]$8155 $1\alu_op__rc__ok$next[0:0]$8158 $1\alu_op__rc__rc$next[0:0]$8159 $1\alu_op__imm_data__ok$next[0:0]$8147 $1\alu_op__imm_data__data$next[63:0]$8146 $1\alu_op__fn_unit$next[11:0]$8145 $1\alu_op__insn_type$next[6:0]$8150 } { \alu_op__insn$87 \alu_op__data_len$86 \alu_op__is_signed$85 \alu_op__is_32bit$84 \alu_op__output_carry$83 \alu_op__input_carry$82 \alu_op__write_cr0$81 \alu_op__invert_out$80 \alu_op__zero_a$79 \alu_op__invert_in$78 \alu_op__oe__ok$77 \alu_op__oe__oe$76 \alu_op__rc__ok$75 \alu_op__rc__rc$74 \alu_op__imm_data__ok$73 \alu_op__imm_data__data$72 \alu_op__fn_unit$71 \alu_op__insn_type$70 } + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'1- + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { $1\alu_op__insn$next[31:0]$8149 $1\alu_op__data_len$next[3:0]$8144 $1\alu_op__is_signed$next[0:0]$8154 $1\alu_op__is_32bit$next[0:0]$8153 $1\alu_op__output_carry$next[0:0]$8157 $1\alu_op__input_carry$next[1:0]$8148 $1\alu_op__write_cr0$next[0:0]$8160 $1\alu_op__invert_out$next[0:0]$8152 $1\alu_op__zero_a$next[0:0]$8161 $1\alu_op__invert_in$next[0:0]$8151 $1\alu_op__oe__ok$next[0:0]$8156 $1\alu_op__oe__oe$next[0:0]$8155 $1\alu_op__rc__ok$next[0:0]$8158 $1\alu_op__rc__rc$next[0:0]$8159 $1\alu_op__imm_data__ok$next[0:0]$8147 $1\alu_op__imm_data__data$next[63:0]$8146 $1\alu_op__fn_unit$next[11:0]$8145 $1\alu_op__insn_type$next[6:0]$8150 } { \alu_op__insn$87 \alu_op__data_len$86 \alu_op__is_signed$85 \alu_op__is_32bit$84 \alu_op__output_carry$83 \alu_op__input_carry$82 \alu_op__write_cr0$81 \alu_op__invert_out$80 \alu_op__zero_a$79 \alu_op__invert_in$78 \alu_op__oe__ok$77 \alu_op__oe__oe$76 \alu_op__rc__ok$75 \alu_op__rc__rc$74 \alu_op__imm_data__ok$73 \alu_op__imm_data__data$72 \alu_op__fn_unit$71 \alu_op__insn_type$70 } + case + assign $1\alu_op__data_len$next[3:0]$8144 \alu_op__data_len + assign $1\alu_op__fn_unit$next[11:0]$8145 \alu_op__fn_unit + assign $1\alu_op__imm_data__data$next[63:0]$8146 \alu_op__imm_data__data + assign $1\alu_op__imm_data__ok$next[0:0]$8147 \alu_op__imm_data__ok + assign $1\alu_op__input_carry$next[1:0]$8148 \alu_op__input_carry + assign $1\alu_op__insn$next[31:0]$8149 \alu_op__insn + assign $1\alu_op__insn_type$next[6:0]$8150 \alu_op__insn_type + assign $1\alu_op__invert_in$next[0:0]$8151 \alu_op__invert_in + assign $1\alu_op__invert_out$next[0:0]$8152 \alu_op__invert_out + assign $1\alu_op__is_32bit$next[0:0]$8153 \alu_op__is_32bit + assign $1\alu_op__is_signed$next[0:0]$8154 \alu_op__is_signed + assign $1\alu_op__oe__oe$next[0:0]$8155 \alu_op__oe__oe + assign $1\alu_op__oe__ok$next[0:0]$8156 \alu_op__oe__ok + assign $1\alu_op__output_carry$next[0:0]$8157 \alu_op__output_carry + assign $1\alu_op__rc__ok$next[0:0]$8158 \alu_op__rc__ok + assign $1\alu_op__rc__rc$next[0:0]$8159 \alu_op__rc__rc + assign $1\alu_op__write_cr0$next[0:0]$8160 \alu_op__write_cr0 + assign $1\alu_op__zero_a$next[0:0]$8161 \alu_op__zero_a + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $2\alu_op__imm_data__data$next[63:0]$8162 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\alu_op__imm_data__ok$next[0:0]$8163 1'0 + assign $2\alu_op__rc__rc$next[0:0]$8167 1'0 + assign $2\alu_op__rc__ok$next[0:0]$8166 1'0 + assign $2\alu_op__oe__oe$next[0:0]$8164 1'0 + assign $2\alu_op__oe__ok$next[0:0]$8165 1'0 + case + assign $2\alu_op__imm_data__data$next[63:0]$8162 $1\alu_op__imm_data__data$next[63:0]$8146 + assign $2\alu_op__imm_data__ok$next[0:0]$8163 $1\alu_op__imm_data__ok$next[0:0]$8147 + assign $2\alu_op__oe__oe$next[0:0]$8164 $1\alu_op__oe__oe$next[0:0]$8155 + assign $2\alu_op__oe__ok$next[0:0]$8165 $1\alu_op__oe__ok$next[0:0]$8156 + assign $2\alu_op__rc__ok$next[0:0]$8166 $1\alu_op__rc__ok$next[0:0]$8158 + assign $2\alu_op__rc__rc$next[0:0]$8167 $1\alu_op__rc__rc$next[0:0]$8159 + end + sync always + update \alu_op__data_len$next $0\alu_op__data_len$next[3:0]$8126 + update \alu_op__fn_unit$next $0\alu_op__fn_unit$next[11:0]$8127 + update \alu_op__imm_data__data$next $0\alu_op__imm_data__data$next[63:0]$8128 + update \alu_op__imm_data__ok$next $0\alu_op__imm_data__ok$next[0:0]$8129 + update \alu_op__input_carry$next $0\alu_op__input_carry$next[1:0]$8130 + update \alu_op__insn$next $0\alu_op__insn$next[31:0]$8131 + update \alu_op__insn_type$next $0\alu_op__insn_type$next[6:0]$8132 + update \alu_op__invert_in$next $0\alu_op__invert_in$next[0:0]$8133 + update \alu_op__invert_out$next $0\alu_op__invert_out$next[0:0]$8134 + update \alu_op__is_32bit$next $0\alu_op__is_32bit$next[0:0]$8135 + update \alu_op__is_signed$next $0\alu_op__is_signed$next[0:0]$8136 + update \alu_op__oe__oe$next $0\alu_op__oe__oe$next[0:0]$8137 + update \alu_op__oe__ok$next $0\alu_op__oe__ok$next[0:0]$8138 + update \alu_op__output_carry$next $0\alu_op__output_carry$next[0:0]$8139 + update \alu_op__rc__ok$next $0\alu_op__rc__ok$next[0:0]$8140 + update \alu_op__rc__rc$next $0\alu_op__rc__rc$next[0:0]$8141 + update \alu_op__write_cr0$next $0\alu_op__write_cr0$next[0:0]$8142 + update \alu_op__zero_a$next $0\alu_op__zero_a$next[0:0]$8143 + end + attribute \src "issuer_ls180.v:150289.3-150307.6" + process $proc$issuer_ls180.v:150289$8168 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\o$next[63:0]$8169 $1\o$next[63:0]$8171 + assign { } { } + assign $0\o_ok$next[0:0]$8170 $2\o_ok$next[0:0]$8173 + attribute \src "issuer_ls180.v:150290.5-150290.29" + switch \initial + attribute \src "issuer_ls180.v:150290.9-150290.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'-1 + assign { } { } + assign { } { } + assign { $1\o_ok$next[0:0]$8172 $1\o$next[63:0]$8171 } { \o_ok$89 \o$88 } + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'1- + assign { } { } + assign { } { } + assign { $1\o_ok$next[0:0]$8172 $1\o$next[63:0]$8171 } { \o_ok$89 \o$88 } + case + assign $1\o$next[63:0]$8171 \o + assign $1\o_ok$next[0:0]$8172 \o_ok + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\o_ok$next[0:0]$8173 1'0 + case + assign $2\o_ok$next[0:0]$8173 $1\o_ok$next[0:0]$8172 + end + sync always + update \o$next $0\o$next[63:0]$8169 + update \o_ok$next $0\o_ok$next[0:0]$8170 + end + connect \$67 $and$issuer_ls180.v:149970$8063_Y + connect \xer_so_ok$98 1'0 + connect \p_ready_o \n_i_rdy_data + connect \n_valid_o \r_busy + connect { \xer_so_ok$97 \xer_so$96 } { 1'0 \main_xer_so$65 } + connect { \xer_ov_ok$95 \xer_ov$94 } { \main_xer_ov_ok \main_xer_ov } + connect { \xer_ca_ok$93 \xer_ca$92 } { \main_xer_ca_ok \main_xer_ca$64 } + connect { \cr_a_ok$91 \cr_a$90 } { \main_cr_a_ok \main_cr_a } + connect { \o_ok$89 \o$88 } { \main_o_ok \main_o } + connect { \alu_op__insn$87 \alu_op__data_len$86 \alu_op__is_signed$85 \alu_op__is_32bit$84 \alu_op__output_carry$83 \alu_op__input_carry$82 \alu_op__write_cr0$81 \alu_op__invert_out$80 \alu_op__zero_a$79 \alu_op__invert_in$78 \alu_op__oe__ok$77 \alu_op__oe__oe$76 \alu_op__rc__ok$75 \alu_op__rc__rc$74 \alu_op__imm_data__ok$73 \alu_op__imm_data__data$72 \alu_op__fn_unit$71 \alu_op__insn_type$70 } { \main_alu_op__insn$63 \main_alu_op__data_len$62 \main_alu_op__is_signed$61 \main_alu_op__is_32bit$60 \main_alu_op__output_carry$59 \main_alu_op__input_carry$58 \main_alu_op__write_cr0$57 \main_alu_op__invert_out$56 \main_alu_op__zero_a$55 \main_alu_op__invert_in$54 \main_alu_op__oe__ok$53 \main_alu_op__oe__oe$52 \main_alu_op__rc__ok$51 \main_alu_op__rc__rc$50 \main_alu_op__imm_data__ok$49 \main_alu_op__imm_data__data$48 \main_alu_op__fn_unit$47 \main_alu_op__insn_type$46 } + connect \muxid$69 \main_muxid$45 + connect \p_valid_i_p_ready_o \$67 + connect \n_i_rdy_data \n_ready_i + connect \p_valid_i$66 \p_valid_i + connect \main_xer_ca \input_xer_ca$44 + connect \main_xer_so \input_xer_so$43 + connect \main_rb \input_rb$42 + connect \main_ra \input_ra$41 + connect { \main_alu_op__insn \main_alu_op__data_len \main_alu_op__is_signed \main_alu_op__is_32bit \main_alu_op__output_carry \main_alu_op__input_carry \main_alu_op__write_cr0 \main_alu_op__invert_out \main_alu_op__zero_a \main_alu_op__invert_in \main_alu_op__oe__ok \main_alu_op__oe__oe \main_alu_op__rc__ok \main_alu_op__rc__rc \main_alu_op__imm_data__ok \main_alu_op__imm_data__data \main_alu_op__fn_unit \main_alu_op__insn_type } { \input_alu_op__insn$40 \input_alu_op__data_len$39 \input_alu_op__is_signed$38 \input_alu_op__is_32bit$37 \input_alu_op__output_carry$36 \input_alu_op__input_carry$35 \input_alu_op__write_cr0$34 \input_alu_op__invert_out$33 \input_alu_op__zero_a$32 \input_alu_op__invert_in$31 \input_alu_op__oe__ok$30 \input_alu_op__oe__oe$29 \input_alu_op__rc__ok$28 \input_alu_op__rc__rc$27 \input_alu_op__imm_data__ok$26 \input_alu_op__imm_data__data$25 \input_alu_op__fn_unit$24 \input_alu_op__insn_type$23 } + connect \main_muxid \input_muxid$22 + connect \input_xer_ca \xer_ca$21 + connect \input_xer_so \xer_so$20 + connect \input_rb \rb + connect \input_ra \ra + connect { \input_alu_op__insn \input_alu_op__data_len \input_alu_op__is_signed \input_alu_op__is_32bit \input_alu_op__output_carry \input_alu_op__input_carry \input_alu_op__write_cr0 \input_alu_op__invert_out \input_alu_op__zero_a \input_alu_op__invert_in \input_alu_op__oe__ok \input_alu_op__oe__oe \input_alu_op__rc__ok \input_alu_op__rc__rc \input_alu_op__imm_data__ok \input_alu_op__imm_data__data \input_alu_op__fn_unit \input_alu_op__insn_type } { \alu_op__insn$19 \alu_op__data_len$18 \alu_op__is_signed$17 \alu_op__is_32bit$16 \alu_op__output_carry$15 \alu_op__input_carry$14 \alu_op__write_cr0$13 \alu_op__invert_out$12 \alu_op__zero_a$11 \alu_op__invert_in$10 \alu_op__oe__ok$9 \alu_op__oe__oe$8 \alu_op__rc__ok$7 \alu_op__rc__rc$6 \alu_op__imm_data__ok$5 \alu_op__imm_data__data$4 \alu_op__fn_unit$3 \alu_op__insn_type$2 } + connect \input_muxid \muxid$1 +end +attribute \src "issuer_ls180.v:150337.1-151728.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.fus.shiftrot0.alu_shift_rot0.pipe1" +attribute \generator "nMigen" +module \pipe1$107 + attribute \src "issuer_ls180.v:151642.3-151660.6" + wire width 4 $0\cr_a$next[3:0]$8285 + attribute \src "issuer_ls180.v:151410.3-151411.25" + wire width 4 $0\cr_a[3:0] + attribute \src "issuer_ls180.v:151642.3-151660.6" + wire $0\cr_a_ok$next[0:0]$8286 + attribute \src "issuer_ls180.v:151412.3-151413.31" + wire $0\cr_a_ok[0:0] + attribute \src "issuer_ls180.v:150338.7-150338.20" + wire $0\initial[0:0] + attribute \src "issuer_ls180.v:151570.3-151582.6" + wire width 2 $0\muxid$next[1:0]$8237 + attribute \src "issuer_ls180.v:151450.3-151451.27" + wire width 2 $0\muxid[1:0] + attribute \src "issuer_ls180.v:151623.3-151641.6" + wire width 64 $0\o$next[63:0]$8279 + attribute \src "issuer_ls180.v:151414.3-151415.19" + wire width 64 $0\o[63:0] + attribute \src "issuer_ls180.v:151623.3-151641.6" + wire $0\o_ok$next[0:0]$8280 + attribute \src "issuer_ls180.v:151416.3-151417.25" + wire $0\o_ok[0:0] + attribute \src "issuer_ls180.v:151552.3-151569.6" + wire $0\r_busy$next[0:0]$8233 + attribute \src "issuer_ls180.v:151452.3-151453.29" + wire $0\r_busy[0:0] + attribute \src "issuer_ls180.v:151583.3-151622.6" + wire width 12 $0\sr_op__fn_unit$next[11:0]$8240 + attribute \src "issuer_ls180.v:151420.3-151421.45" + wire width 12 $0\sr_op__fn_unit[11:0] + attribute \src "issuer_ls180.v:151583.3-151622.6" + wire width 64 $0\sr_op__imm_data__data$next[63:0]$8241 + attribute \src "issuer_ls180.v:151422.3-151423.59" + wire width 64 $0\sr_op__imm_data__data[63:0] + attribute \src "issuer_ls180.v:151583.3-151622.6" + wire $0\sr_op__imm_data__ok$next[0:0]$8242 + attribute \src "issuer_ls180.v:151424.3-151425.55" + wire $0\sr_op__imm_data__ok[0:0] + attribute \src "issuer_ls180.v:151583.3-151622.6" + wire width 2 $0\sr_op__input_carry$next[1:0]$8243 + attribute \src "issuer_ls180.v:151436.3-151437.53" + wire width 2 $0\sr_op__input_carry[1:0] + attribute \src "issuer_ls180.v:151583.3-151622.6" + wire $0\sr_op__input_cr$next[0:0]$8244 + attribute \src "issuer_ls180.v:151440.3-151441.47" + wire $0\sr_op__input_cr[0:0] + attribute \src "issuer_ls180.v:151583.3-151622.6" + wire width 32 $0\sr_op__insn$next[31:0]$8245 + attribute \src "issuer_ls180.v:151448.3-151449.39" + wire width 32 $0\sr_op__insn[31:0] + attribute \src "issuer_ls180.v:151583.3-151622.6" + wire width 7 $0\sr_op__insn_type$next[6:0]$8246 + attribute \src "issuer_ls180.v:151418.3-151419.49" + wire width 7 $0\sr_op__insn_type[6:0] + attribute \src "issuer_ls180.v:151583.3-151622.6" + wire $0\sr_op__is_32bit$next[0:0]$8247 + attribute \src "issuer_ls180.v:151444.3-151445.47" + wire $0\sr_op__is_32bit[0:0] + attribute \src "issuer_ls180.v:151583.3-151622.6" + wire $0\sr_op__is_signed$next[0:0]$8248 + attribute \src "issuer_ls180.v:151446.3-151447.49" + wire $0\sr_op__is_signed[0:0] + attribute \src "issuer_ls180.v:151583.3-151622.6" + wire $0\sr_op__oe__oe$next[0:0]$8249 + attribute \src "issuer_ls180.v:151430.3-151431.43" + wire $0\sr_op__oe__oe[0:0] + attribute \src "issuer_ls180.v:151583.3-151622.6" + wire $0\sr_op__oe__ok$next[0:0]$8250 + attribute \src "issuer_ls180.v:151432.3-151433.43" + wire $0\sr_op__oe__ok[0:0] + attribute \src "issuer_ls180.v:151583.3-151622.6" + wire $0\sr_op__output_carry$next[0:0]$8251 + attribute \src "issuer_ls180.v:151438.3-151439.55" + wire $0\sr_op__output_carry[0:0] + attribute \src "issuer_ls180.v:151583.3-151622.6" + wire $0\sr_op__output_cr$next[0:0]$8252 + attribute \src "issuer_ls180.v:151442.3-151443.49" + wire $0\sr_op__output_cr[0:0] + attribute \src "issuer_ls180.v:151583.3-151622.6" + wire $0\sr_op__rc__ok$next[0:0]$8253 + attribute \src "issuer_ls180.v:151428.3-151429.43" + wire $0\sr_op__rc__ok[0:0] + attribute \src "issuer_ls180.v:151583.3-151622.6" + wire $0\sr_op__rc__rc$next[0:0]$8254 + attribute \src "issuer_ls180.v:151426.3-151427.43" + wire $0\sr_op__rc__rc[0:0] + attribute \src "issuer_ls180.v:151583.3-151622.6" + wire $0\sr_op__write_cr0$next[0:0]$8255 + attribute \src "issuer_ls180.v:151434.3-151435.49" + wire $0\sr_op__write_cr0[0:0] + attribute \src "issuer_ls180.v:151680.3-151698.6" + wire width 2 $0\xer_ca$next[1:0]$8298 + attribute \src "issuer_ls180.v:151402.3-151403.29" + wire width 2 $0\xer_ca[1:0] + attribute \src "issuer_ls180.v:151680.3-151698.6" + wire $0\xer_ca_ok$next[0:0]$8297 + attribute \src "issuer_ls180.v:151404.3-151405.35" + wire $0\xer_ca_ok[0:0] + attribute \src "issuer_ls180.v:151661.3-151679.6" + wire $0\xer_so$next[0:0]$8291 + attribute \src "issuer_ls180.v:151406.3-151407.29" + wire $0\xer_so[0:0] + attribute \src "issuer_ls180.v:151661.3-151679.6" + wire $0\xer_so_ok$next[0:0]$8292 + attribute \src "issuer_ls180.v:151408.3-151409.35" + wire $0\xer_so_ok[0:0] + attribute \src "issuer_ls180.v:151642.3-151660.6" + wire width 4 $1\cr_a$next[3:0]$8287 + attribute \src "issuer_ls180.v:150347.13-150347.24" + wire width 4 $1\cr_a[3:0] + attribute \src "issuer_ls180.v:151642.3-151660.6" + wire $1\cr_a_ok$next[0:0]$8288 + attribute \src "issuer_ls180.v:150356.7-150356.21" + wire $1\cr_a_ok[0:0] + attribute \src "issuer_ls180.v:151570.3-151582.6" + wire width 2 $1\muxid$next[1:0]$8238 + attribute \src "issuer_ls180.v:150901.13-150901.25" + wire width 2 $1\muxid[1:0] + attribute \src "issuer_ls180.v:151623.3-151641.6" + wire width 64 $1\o$next[63:0]$8281 + attribute \src "issuer_ls180.v:150916.14-150916.38" + wire width 64 $1\o[63:0] + attribute \src "issuer_ls180.v:151623.3-151641.6" + wire $1\o_ok$next[0:0]$8282 + attribute \src "issuer_ls180.v:150923.7-150923.18" + wire $1\o_ok[0:0] + attribute \src "issuer_ls180.v:151552.3-151569.6" + wire $1\r_busy$next[0:0]$8234 + attribute \src "issuer_ls180.v:150937.7-150937.20" + wire $1\r_busy[0:0] + attribute \src "issuer_ls180.v:151583.3-151622.6" + wire width 12 $1\sr_op__fn_unit$next[11:0]$8256 + attribute \src "issuer_ls180.v:150961.14-150961.38" + wire width 12 $1\sr_op__fn_unit[11:0] + attribute \src "issuer_ls180.v:151583.3-151622.6" + wire width 64 $1\sr_op__imm_data__data$next[63:0]$8257 + attribute \src "issuer_ls180.v:150996.14-150996.58" + wire width 64 $1\sr_op__imm_data__data[63:0] + attribute \src "issuer_ls180.v:151583.3-151622.6" + wire $1\sr_op__imm_data__ok$next[0:0]$8258 + attribute \src "issuer_ls180.v:151005.7-151005.33" + wire $1\sr_op__imm_data__ok[0:0] + attribute \src "issuer_ls180.v:151583.3-151622.6" + wire width 2 $1\sr_op__input_carry$next[1:0]$8259 + attribute \src "issuer_ls180.v:151018.13-151018.38" + wire width 2 $1\sr_op__input_carry[1:0] + attribute \src "issuer_ls180.v:151583.3-151622.6" + wire $1\sr_op__input_cr$next[0:0]$8260 + attribute \src "issuer_ls180.v:151035.7-151035.29" + wire $1\sr_op__input_cr[0:0] + attribute \src "issuer_ls180.v:151583.3-151622.6" + wire width 32 $1\sr_op__insn$next[31:0]$8261 + attribute \src "issuer_ls180.v:151044.14-151044.33" + wire width 32 $1\sr_op__insn[31:0] + attribute \src "issuer_ls180.v:151583.3-151622.6" + wire width 7 $1\sr_op__insn_type$next[6:0]$8262 + attribute \src "issuer_ls180.v:151127.13-151127.37" + wire width 7 $1\sr_op__insn_type[6:0] + attribute \src "issuer_ls180.v:151583.3-151622.6" + wire $1\sr_op__is_32bit$next[0:0]$8263 + attribute \src "issuer_ls180.v:151284.7-151284.29" + wire $1\sr_op__is_32bit[0:0] + attribute \src "issuer_ls180.v:151583.3-151622.6" + wire $1\sr_op__is_signed$next[0:0]$8264 + attribute \src "issuer_ls180.v:151293.7-151293.30" + wire $1\sr_op__is_signed[0:0] + attribute \src "issuer_ls180.v:151583.3-151622.6" + wire $1\sr_op__oe__oe$next[0:0]$8265 + attribute \src "issuer_ls180.v:151302.7-151302.27" + wire $1\sr_op__oe__oe[0:0] + attribute \src "issuer_ls180.v:151583.3-151622.6" + wire $1\sr_op__oe__ok$next[0:0]$8266 + attribute \src "issuer_ls180.v:151311.7-151311.27" + wire $1\sr_op__oe__ok[0:0] + attribute \src "issuer_ls180.v:151583.3-151622.6" + wire $1\sr_op__output_carry$next[0:0]$8267 + attribute \src "issuer_ls180.v:151320.7-151320.33" + wire $1\sr_op__output_carry[0:0] + attribute \src "issuer_ls180.v:151583.3-151622.6" + wire $1\sr_op__output_cr$next[0:0]$8268 + attribute \src "issuer_ls180.v:151329.7-151329.30" + wire $1\sr_op__output_cr[0:0] + attribute \src "issuer_ls180.v:151583.3-151622.6" + wire $1\sr_op__rc__ok$next[0:0]$8269 + attribute \src "issuer_ls180.v:151338.7-151338.27" + wire $1\sr_op__rc__ok[0:0] + attribute \src "issuer_ls180.v:151583.3-151622.6" + wire $1\sr_op__rc__rc$next[0:0]$8270 + attribute \src "issuer_ls180.v:151347.7-151347.27" + wire $1\sr_op__rc__rc[0:0] + attribute \src "issuer_ls180.v:151583.3-151622.6" + wire $1\sr_op__write_cr0$next[0:0]$8271 + attribute \src "issuer_ls180.v:151356.7-151356.30" + wire $1\sr_op__write_cr0[0:0] + attribute \src "issuer_ls180.v:151680.3-151698.6" + wire width 2 $1\xer_ca$next[1:0]$8300 + attribute \src "issuer_ls180.v:151365.13-151365.26" + wire width 2 $1\xer_ca[1:0] + attribute \src "issuer_ls180.v:151680.3-151698.6" + wire $1\xer_ca_ok$next[0:0]$8299 + attribute \src "issuer_ls180.v:151376.7-151376.23" + wire $1\xer_ca_ok[0:0] + attribute \src "issuer_ls180.v:151661.3-151679.6" + wire $1\xer_so$next[0:0]$8293 + attribute \src "issuer_ls180.v:151385.7-151385.20" + wire $1\xer_so[0:0] + attribute \src "issuer_ls180.v:151661.3-151679.6" + wire $1\xer_so_ok$next[0:0]$8294 + attribute \src "issuer_ls180.v:151394.7-151394.23" + wire $1\xer_so_ok[0:0] + attribute \src "issuer_ls180.v:151642.3-151660.6" + wire $2\cr_a_ok$next[0:0]$8289 + attribute \src "issuer_ls180.v:151623.3-151641.6" + wire $2\o_ok$next[0:0]$8283 + attribute \src "issuer_ls180.v:151552.3-151569.6" + wire $2\r_busy$next[0:0]$8235 + attribute \src "issuer_ls180.v:151583.3-151622.6" + wire width 64 $2\sr_op__imm_data__data$next[63:0]$8272 + attribute \src "issuer_ls180.v:151583.3-151622.6" + wire $2\sr_op__imm_data__ok$next[0:0]$8273 + attribute \src "issuer_ls180.v:151583.3-151622.6" + wire $2\sr_op__oe__oe$next[0:0]$8274 + attribute \src "issuer_ls180.v:151583.3-151622.6" + wire $2\sr_op__oe__ok$next[0:0]$8275 + attribute \src "issuer_ls180.v:151583.3-151622.6" + wire $2\sr_op__rc__ok$next[0:0]$8276 + attribute \src "issuer_ls180.v:151583.3-151622.6" + wire $2\sr_op__rc__rc$next[0:0]$8277 + attribute \src "issuer_ls180.v:151680.3-151698.6" + wire $2\xer_ca_ok$next[0:0]$8301 + attribute \src "issuer_ls180.v:151661.3-151679.6" + wire $2\xer_so_ok$next[0:0]$8295 + attribute \src "issuer_ls180.v:151401.18-151401.118" + wire $and$issuer_ls180.v:151401$8205_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" + wire \$62 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" + wire input 53 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" + wire input 1 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 4 output 23 \cr_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 4 \cr_a$83 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 4 \cr_a$85 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 4 \cr_a$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 24 \cr_a_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \cr_a_ok$84 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \cr_a_ok$86 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \cr_a_ok$next + attribute \src "issuer_ls180.v:150338.7-150338.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \input_muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \input_muxid$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \input_ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \input_ra$37 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \input_rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \input_rb$38 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \input_rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \input_rc$39 + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 \input_sr_op__fn_unit + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 \input_sr_op__fn_unit$22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \input_sr_op__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \input_sr_op__imm_data__data$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_sr_op__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_sr_op__imm_data__ok$24 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \input_sr_op__input_carry + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \input_sr_op__input_carry$30 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_sr_op__input_cr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_sr_op__input_cr$32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \input_sr_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \input_sr_op__insn$36 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \input_sr_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \input_sr_op__insn_type$21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_sr_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_sr_op__is_32bit$34 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_sr_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_sr_op__is_signed$35 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_sr_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_sr_op__oe__oe$27 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_sr_op__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_sr_op__oe__ok$28 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_sr_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_sr_op__output_carry$31 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_sr_op__output_cr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_sr_op__output_cr$33 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_sr_op__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_sr_op__rc__ok$26 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_sr_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_sr_op__rc__rc$25 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_sr_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_sr_op__write_cr0$29 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 2 \input_xer_ca + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 2 \input_xer_ca$41 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire \input_xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire \input_xer_so$40 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \main_muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \main_muxid$42 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 \main_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \main_o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \main_ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \main_rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \main_rc + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 \main_sr_op__fn_unit + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 \main_sr_op__fn_unit$44 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \main_sr_op__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \main_sr_op__imm_data__data$45 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_sr_op__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_sr_op__imm_data__ok$46 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \main_sr_op__input_carry + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \main_sr_op__input_carry$52 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_sr_op__input_cr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_sr_op__input_cr$54 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \main_sr_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \main_sr_op__insn$58 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute 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\enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \main_sr_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \main_sr_op__insn_type$43 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_sr_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_sr_op__is_32bit$56 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_sr_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_sr_op__is_signed$57 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_sr_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_sr_op__oe__oe$49 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_sr_op__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_sr_op__oe__ok$50 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_sr_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_sr_op__output_carry$53 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_sr_op__output_cr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_sr_op__output_cr$55 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_sr_op__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_sr_op__rc__ok$48 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_sr_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_sr_op__rc__rc$47 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_sr_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \main_sr_op__write_cr0$51 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 2 \main_xer_ca + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire \main_xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \main_xer_so$59 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 output 4 \muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 input 31 \muxid$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \muxid$64 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \muxid$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:619" + wire \n_i_rdy_data + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" + wire input 3 \n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" + wire output 2 \n_valid_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 output 21 \o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 \o$81 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 \o$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 22 \o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \o_ok$82 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \o_ok$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" + wire output 30 \p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" + wire input 29 \p_valid_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:621" + wire \p_valid_i$61 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" + wire \p_valid_i_p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615" + wire \r_busy + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615" + wire \r_busy$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 48 \ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 49 \rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 50 \rc + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 output 6 \sr_op__fn_unit + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 input 33 \sr_op__fn_unit$3 + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 \sr_op__fn_unit$66 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 \sr_op__fn_unit$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 output 7 \sr_op__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 input 34 \sr_op__imm_data__data$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \sr_op__imm_data__data$67 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \sr_op__imm_data__data$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 8 \sr_op__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 35 \sr_op__imm_data__ok$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \sr_op__imm_data__ok$68 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \sr_op__imm_data__ok$next + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 output 14 \sr_op__input_carry + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 input 41 \sr_op__input_carry$11 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \sr_op__input_carry$74 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \sr_op__input_carry$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 16 \sr_op__input_cr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 43 \sr_op__input_cr$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \sr_op__input_cr$76 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \sr_op__input_cr$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 output 20 \sr_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 47 \sr_op__insn$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \sr_op__insn$80 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \sr_op__insn$next + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute 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\enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 output 5 \sr_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 input 32 \sr_op__insn_type$2 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \sr_op__insn_type$65 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \sr_op__insn_type$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 18 \sr_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 45 \sr_op__is_32bit$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \sr_op__is_32bit$78 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \sr_op__is_32bit$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 19 \sr_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 46 \sr_op__is_signed$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \sr_op__is_signed$79 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \sr_op__is_signed$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 11 \sr_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \sr_op__oe__oe$71 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 38 \sr_op__oe__oe$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \sr_op__oe__oe$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 12 \sr_op__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \sr_op__oe__ok$72 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 39 \sr_op__oe__ok$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \sr_op__oe__ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 15 \sr_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 42 \sr_op__output_carry$12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \sr_op__output_carry$75 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \sr_op__output_carry$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 17 \sr_op__output_cr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 44 \sr_op__output_cr$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \sr_op__output_cr$77 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \sr_op__output_cr$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 10 \sr_op__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 37 \sr_op__rc__ok$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \sr_op__rc__ok$70 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \sr_op__rc__ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 9 \sr_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 36 \sr_op__rc__rc$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \sr_op__rc__rc$69 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \sr_op__rc__rc$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 13 \sr_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 40 \sr_op__write_cr0$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \sr_op__write_cr0$73 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \sr_op__write_cr0$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 2 output 27 \xer_ca + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 2 input 52 \xer_ca$19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 2 \xer_ca$60 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 2 \xer_ca$90 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 2 \xer_ca$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 28 \xer_ca_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \xer_ca_ok$91 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \xer_ca_ok$92 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \xer_ca_ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 25 \xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire input 51 \xer_so$18 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \xer_so$87 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \xer_so$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 26 \xer_so_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \xer_so_ok$88 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \xer_so_ok$89 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \xer_so_ok$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" + cell $and $and$issuer_ls180.v:151401$8205 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \p_valid_i$61 + connect \B \p_ready_o + connect \Y $and$issuer_ls180.v:151401$8205_Y + end + attribute \module_not_derived 1 + attribute \src "issuer_ls180.v:151454.15-151499.4" + cell \input$110 \input + connect \muxid \input_muxid + connect \muxid$1 \input_muxid$20 + connect \ra \input_ra + connect \ra$18 \input_ra$37 + connect \rb \input_rb + connect \rb$19 \input_rb$38 + connect \rc \input_rc + connect \rc$20 \input_rc$39 + connect \sr_op__fn_unit \input_sr_op__fn_unit + connect \sr_op__fn_unit$3 \input_sr_op__fn_unit$22 + connect \sr_op__imm_data__data \input_sr_op__imm_data__data + connect \sr_op__imm_data__data$4 \input_sr_op__imm_data__data$23 + connect \sr_op__imm_data__ok \input_sr_op__imm_data__ok + connect \sr_op__imm_data__ok$5 \input_sr_op__imm_data__ok$24 + connect \sr_op__input_carry \input_sr_op__input_carry + connect \sr_op__input_carry$11 \input_sr_op__input_carry$30 + connect \sr_op__input_cr \input_sr_op__input_cr + connect \sr_op__input_cr$13 \input_sr_op__input_cr$32 + connect \sr_op__insn \input_sr_op__insn + connect \sr_op__insn$17 \input_sr_op__insn$36 + connect \sr_op__insn_type \input_sr_op__insn_type + connect \sr_op__insn_type$2 \input_sr_op__insn_type$21 + connect \sr_op__is_32bit \input_sr_op__is_32bit + connect \sr_op__is_32bit$15 \input_sr_op__is_32bit$34 + connect \sr_op__is_signed \input_sr_op__is_signed + connect \sr_op__is_signed$16 \input_sr_op__is_signed$35 + connect \sr_op__oe__oe \input_sr_op__oe__oe + connect \sr_op__oe__oe$8 \input_sr_op__oe__oe$27 + connect \sr_op__oe__ok \input_sr_op__oe__ok + connect \sr_op__oe__ok$9 \input_sr_op__oe__ok$28 + connect \sr_op__output_carry \input_sr_op__output_carry + connect \sr_op__output_carry$12 \input_sr_op__output_carry$31 + connect \sr_op__output_cr \input_sr_op__output_cr + connect \sr_op__output_cr$14 \input_sr_op__output_cr$33 + connect \sr_op__rc__ok \input_sr_op__rc__ok + connect \sr_op__rc__ok$7 \input_sr_op__rc__ok$26 + connect \sr_op__rc__rc \input_sr_op__rc__rc + connect \sr_op__rc__rc$6 \input_sr_op__rc__rc$25 + connect \sr_op__write_cr0 \input_sr_op__write_cr0 + connect \sr_op__write_cr0$10 \input_sr_op__write_cr0$29 + connect \xer_ca \input_xer_ca + connect \xer_ca$22 \input_xer_ca$41 + connect \xer_so \input_xer_so + connect \xer_so$21 \input_xer_so$40 + end + attribute \module_not_derived 1 + attribute \src "issuer_ls180.v:151500.14-151543.4" + cell \main$111 \main + connect \muxid \main_muxid + connect \muxid$1 \main_muxid$42 + connect \o \main_o + connect \o_ok \main_o_ok + connect \ra \main_ra + connect \rb \main_rb + connect \rc \main_rc + connect \sr_op__fn_unit \main_sr_op__fn_unit + connect \sr_op__fn_unit$3 \main_sr_op__fn_unit$44 + connect \sr_op__imm_data__data \main_sr_op__imm_data__data + connect \sr_op__imm_data__data$4 \main_sr_op__imm_data__data$45 + connect \sr_op__imm_data__ok \main_sr_op__imm_data__ok + connect \sr_op__imm_data__ok$5 \main_sr_op__imm_data__ok$46 + connect \sr_op__input_carry \main_sr_op__input_carry + connect \sr_op__input_carry$11 \main_sr_op__input_carry$52 + connect \sr_op__input_cr \main_sr_op__input_cr + connect \sr_op__input_cr$13 \main_sr_op__input_cr$54 + connect \sr_op__insn \main_sr_op__insn + connect \sr_op__insn$17 \main_sr_op__insn$58 + connect \sr_op__insn_type \main_sr_op__insn_type + connect \sr_op__insn_type$2 \main_sr_op__insn_type$43 + connect \sr_op__is_32bit \main_sr_op__is_32bit + connect \sr_op__is_32bit$15 \main_sr_op__is_32bit$56 + connect \sr_op__is_signed \main_sr_op__is_signed + connect \sr_op__is_signed$16 \main_sr_op__is_signed$57 + connect \sr_op__oe__oe \main_sr_op__oe__oe + connect \sr_op__oe__oe$8 \main_sr_op__oe__oe$49 + connect \sr_op__oe__ok \main_sr_op__oe__ok + connect \sr_op__oe__ok$9 \main_sr_op__oe__ok$50 + connect \sr_op__output_carry \main_sr_op__output_carry + connect \sr_op__output_carry$12 \main_sr_op__output_carry$53 + connect \sr_op__output_cr \main_sr_op__output_cr + connect \sr_op__output_cr$14 \main_sr_op__output_cr$55 + connect \sr_op__rc__ok \main_sr_op__rc__ok + connect \sr_op__rc__ok$7 \main_sr_op__rc__ok$48 + connect \sr_op__rc__rc \main_sr_op__rc__rc + connect \sr_op__rc__rc$6 \main_sr_op__rc__rc$47 + connect \sr_op__write_cr0 \main_sr_op__write_cr0 + connect \sr_op__write_cr0$10 \main_sr_op__write_cr0$51 + connect \xer_ca \main_xer_ca + connect \xer_so \main_xer_so + connect \xer_so$18 \main_xer_so$59 + end + attribute \module_not_derived 1 + attribute \src "issuer_ls180.v:151544.11-151547.4" + cell \n$109 \n + connect \n_ready_i \n_ready_i + connect \n_valid_o \n_valid_o + end + attribute \module_not_derived 1 + attribute \src "issuer_ls180.v:151548.11-151551.4" + cell \p$108 \p + connect \p_ready_o \p_ready_o + connect \p_valid_i \p_valid_i + end + attribute \src "issuer_ls180.v:150338.7-150338.20" + process $proc$issuer_ls180.v:150338$8302 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "issuer_ls180.v:150347.13-150347.24" + process $proc$issuer_ls180.v:150347$8303 + assign { } { } + assign $1\cr_a[3:0] 4'0000 + sync always + sync init + update \cr_a $1\cr_a[3:0] + end + attribute \src "issuer_ls180.v:150356.7-150356.21" + process $proc$issuer_ls180.v:150356$8304 + assign { } { } + assign $1\cr_a_ok[0:0] 1'0 + sync always + sync init + update \cr_a_ok $1\cr_a_ok[0:0] + end + attribute \src "issuer_ls180.v:150901.13-150901.25" + process $proc$issuer_ls180.v:150901$8305 + assign { } { } + assign $1\muxid[1:0] 2'00 + sync always + sync init + update \muxid $1\muxid[1:0] + end + attribute \src "issuer_ls180.v:150916.14-150916.38" + process $proc$issuer_ls180.v:150916$8306 + assign { } { } + assign $1\o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \o $1\o[63:0] + end + attribute \src "issuer_ls180.v:150923.7-150923.18" + process $proc$issuer_ls180.v:150923$8307 + assign { } { } + assign $1\o_ok[0:0] 1'0 + sync always + sync init + update \o_ok $1\o_ok[0:0] + end + attribute \src "issuer_ls180.v:150937.7-150937.20" + process $proc$issuer_ls180.v:150937$8308 + assign { } { } + assign $1\r_busy[0:0] 1'0 + sync always + sync init + update \r_busy $1\r_busy[0:0] + end + attribute \src "issuer_ls180.v:150961.14-150961.38" + process $proc$issuer_ls180.v:150961$8309 + assign { } { } + assign $1\sr_op__fn_unit[11:0] 12'000000000000 + sync always + sync init + update \sr_op__fn_unit $1\sr_op__fn_unit[11:0] + end + attribute \src "issuer_ls180.v:150996.14-150996.58" + process $proc$issuer_ls180.v:150996$8310 + assign { } { } + assign $1\sr_op__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \sr_op__imm_data__data $1\sr_op__imm_data__data[63:0] + end + attribute \src "issuer_ls180.v:151005.7-151005.33" + process $proc$issuer_ls180.v:151005$8311 + assign { } { } + assign $1\sr_op__imm_data__ok[0:0] 1'0 + sync always + sync init + update \sr_op__imm_data__ok $1\sr_op__imm_data__ok[0:0] + end + attribute \src "issuer_ls180.v:151018.13-151018.38" + process $proc$issuer_ls180.v:151018$8312 + assign { } { } + assign $1\sr_op__input_carry[1:0] 2'00 + sync always + sync init + update \sr_op__input_carry $1\sr_op__input_carry[1:0] + end + attribute \src "issuer_ls180.v:151035.7-151035.29" + process $proc$issuer_ls180.v:151035$8313 + assign { } { } + assign $1\sr_op__input_cr[0:0] 1'0 + sync always + sync init + update \sr_op__input_cr $1\sr_op__input_cr[0:0] + end + attribute \src "issuer_ls180.v:151044.14-151044.33" + process $proc$issuer_ls180.v:151044$8314 + assign { } { } + assign $1\sr_op__insn[31:0] 0 + sync always + sync init + update \sr_op__insn $1\sr_op__insn[31:0] + end + attribute \src "issuer_ls180.v:151127.13-151127.37" + process $proc$issuer_ls180.v:151127$8315 + assign { } { } + assign $1\sr_op__insn_type[6:0] 7'0000000 + sync always + sync init + update \sr_op__insn_type $1\sr_op__insn_type[6:0] + end + attribute \src "issuer_ls180.v:151284.7-151284.29" + process $proc$issuer_ls180.v:151284$8316 + assign { } { } + assign $1\sr_op__is_32bit[0:0] 1'0 + sync always + sync init + update \sr_op__is_32bit $1\sr_op__is_32bit[0:0] + end + attribute \src "issuer_ls180.v:151293.7-151293.30" + process $proc$issuer_ls180.v:151293$8317 + assign { } { } + assign $1\sr_op__is_signed[0:0] 1'0 + sync always + sync init + update \sr_op__is_signed $1\sr_op__is_signed[0:0] + end + attribute \src "issuer_ls180.v:151302.7-151302.27" + process $proc$issuer_ls180.v:151302$8318 + assign { } { } + assign $1\sr_op__oe__oe[0:0] 1'0 + sync always + sync init + update \sr_op__oe__oe $1\sr_op__oe__oe[0:0] + end + attribute \src "issuer_ls180.v:151311.7-151311.27" + process $proc$issuer_ls180.v:151311$8319 + assign { } { } + assign $1\sr_op__oe__ok[0:0] 1'0 + sync always + sync init + update \sr_op__oe__ok $1\sr_op__oe__ok[0:0] + end + attribute \src "issuer_ls180.v:151320.7-151320.33" + process $proc$issuer_ls180.v:151320$8320 + assign { } { } + assign $1\sr_op__output_carry[0:0] 1'0 + sync always + sync init + update \sr_op__output_carry $1\sr_op__output_carry[0:0] + end + attribute \src "issuer_ls180.v:151329.7-151329.30" + process $proc$issuer_ls180.v:151329$8321 + assign { } { } + assign $1\sr_op__output_cr[0:0] 1'0 + sync always + sync init + update \sr_op__output_cr $1\sr_op__output_cr[0:0] + end + attribute \src "issuer_ls180.v:151338.7-151338.27" + process $proc$issuer_ls180.v:151338$8322 + assign { } { } + assign $1\sr_op__rc__ok[0:0] 1'0 + sync always + sync init + update \sr_op__rc__ok $1\sr_op__rc__ok[0:0] + end + attribute \src "issuer_ls180.v:151347.7-151347.27" + process $proc$issuer_ls180.v:151347$8323 + assign { } { } + assign $1\sr_op__rc__rc[0:0] 1'0 + sync always + sync init + update \sr_op__rc__rc $1\sr_op__rc__rc[0:0] + end + attribute \src "issuer_ls180.v:151356.7-151356.30" + process $proc$issuer_ls180.v:151356$8324 + assign { } { } + assign $1\sr_op__write_cr0[0:0] 1'0 + sync always + sync init + update \sr_op__write_cr0 $1\sr_op__write_cr0[0:0] + end + attribute \src "issuer_ls180.v:151365.13-151365.26" + process $proc$issuer_ls180.v:151365$8325 + assign { } { } + assign $1\xer_ca[1:0] 2'00 + sync always + sync init + update \xer_ca $1\xer_ca[1:0] + end + attribute \src "issuer_ls180.v:151376.7-151376.23" + process $proc$issuer_ls180.v:151376$8326 + assign { } { } + assign $1\xer_ca_ok[0:0] 1'0 + sync always + sync init + update \xer_ca_ok $1\xer_ca_ok[0:0] + end + attribute \src "issuer_ls180.v:151385.7-151385.20" + process $proc$issuer_ls180.v:151385$8327 + assign { } { } + assign $1\xer_so[0:0] 1'0 + sync always + sync init + update \xer_so $1\xer_so[0:0] + end + attribute \src "issuer_ls180.v:151394.7-151394.23" + process $proc$issuer_ls180.v:151394$8328 + assign { } { } + assign $1\xer_so_ok[0:0] 1'0 + sync always + sync init + update \xer_so_ok $1\xer_so_ok[0:0] + end + attribute \src "issuer_ls180.v:151402.3-151403.29" + process $proc$issuer_ls180.v:151402$8206 + assign { } { } + assign $0\xer_ca[1:0] \xer_ca$next + sync posedge \coresync_clk + update \xer_ca $0\xer_ca[1:0] + end + attribute \src "issuer_ls180.v:151404.3-151405.35" + process $proc$issuer_ls180.v:151404$8207 + assign { } { } + assign $0\xer_ca_ok[0:0] \xer_ca_ok$next + sync posedge \coresync_clk + update \xer_ca_ok $0\xer_ca_ok[0:0] + end + attribute \src "issuer_ls180.v:151406.3-151407.29" + process $proc$issuer_ls180.v:151406$8208 + assign { } { } + assign $0\xer_so[0:0] \xer_so$next + sync posedge \coresync_clk + update \xer_so $0\xer_so[0:0] + end + attribute \src "issuer_ls180.v:151408.3-151409.35" + process $proc$issuer_ls180.v:151408$8209 + assign { } { } + assign $0\xer_so_ok[0:0] \xer_so_ok$next + sync posedge \coresync_clk + update \xer_so_ok $0\xer_so_ok[0:0] + end + attribute \src "issuer_ls180.v:151410.3-151411.25" + process $proc$issuer_ls180.v:151410$8210 + assign { } { } + assign $0\cr_a[3:0] \cr_a$next + sync posedge \coresync_clk + update \cr_a $0\cr_a[3:0] + end + attribute \src "issuer_ls180.v:151412.3-151413.31" + process $proc$issuer_ls180.v:151412$8211 + assign { } { } + assign $0\cr_a_ok[0:0] \cr_a_ok$next + sync posedge \coresync_clk + update \cr_a_ok $0\cr_a_ok[0:0] + end + attribute \src "issuer_ls180.v:151414.3-151415.19" + process $proc$issuer_ls180.v:151414$8212 + assign { } { } + assign $0\o[63:0] \o$next + sync posedge \coresync_clk + update \o $0\o[63:0] + end + attribute \src "issuer_ls180.v:151416.3-151417.25" + process $proc$issuer_ls180.v:151416$8213 + assign { } { } + assign $0\o_ok[0:0] \o_ok$next + sync posedge \coresync_clk + update \o_ok $0\o_ok[0:0] + end + attribute \src "issuer_ls180.v:151418.3-151419.49" + process $proc$issuer_ls180.v:151418$8214 + assign { } { } + assign $0\sr_op__insn_type[6:0] \sr_op__insn_type$next + sync posedge \coresync_clk + update \sr_op__insn_type $0\sr_op__insn_type[6:0] + end + attribute \src "issuer_ls180.v:151420.3-151421.45" + process $proc$issuer_ls180.v:151420$8215 + assign { } { } + assign $0\sr_op__fn_unit[11:0] \sr_op__fn_unit$next + sync posedge \coresync_clk + update \sr_op__fn_unit $0\sr_op__fn_unit[11:0] + end + attribute \src "issuer_ls180.v:151422.3-151423.59" + process $proc$issuer_ls180.v:151422$8216 + assign { } { } + assign $0\sr_op__imm_data__data[63:0] \sr_op__imm_data__data$next + sync posedge \coresync_clk + update \sr_op__imm_data__data $0\sr_op__imm_data__data[63:0] + end + attribute \src "issuer_ls180.v:151424.3-151425.55" + process $proc$issuer_ls180.v:151424$8217 + assign { } { } + assign $0\sr_op__imm_data__ok[0:0] \sr_op__imm_data__ok$next + sync posedge \coresync_clk + update \sr_op__imm_data__ok $0\sr_op__imm_data__ok[0:0] + end + attribute \src "issuer_ls180.v:151426.3-151427.43" + process $proc$issuer_ls180.v:151426$8218 + assign { } { } + assign $0\sr_op__rc__rc[0:0] \sr_op__rc__rc$next + sync posedge \coresync_clk + update \sr_op__rc__rc $0\sr_op__rc__rc[0:0] + end + attribute \src "issuer_ls180.v:151428.3-151429.43" + process $proc$issuer_ls180.v:151428$8219 + assign { } { } + assign $0\sr_op__rc__ok[0:0] \sr_op__rc__ok$next + sync posedge \coresync_clk + update \sr_op__rc__ok $0\sr_op__rc__ok[0:0] + end + attribute \src "issuer_ls180.v:151430.3-151431.43" + process $proc$issuer_ls180.v:151430$8220 + assign { } { } + assign $0\sr_op__oe__oe[0:0] \sr_op__oe__oe$next + sync posedge \coresync_clk + update \sr_op__oe__oe $0\sr_op__oe__oe[0:0] + end + attribute \src "issuer_ls180.v:151432.3-151433.43" + process $proc$issuer_ls180.v:151432$8221 + assign { } { } + assign $0\sr_op__oe__ok[0:0] \sr_op__oe__ok$next + sync posedge \coresync_clk + update \sr_op__oe__ok $0\sr_op__oe__ok[0:0] + end + attribute \src "issuer_ls180.v:151434.3-151435.49" + process $proc$issuer_ls180.v:151434$8222 + assign { } { } + assign $0\sr_op__write_cr0[0:0] \sr_op__write_cr0$next + sync posedge \coresync_clk + update \sr_op__write_cr0 $0\sr_op__write_cr0[0:0] + end + attribute \src "issuer_ls180.v:151436.3-151437.53" + process $proc$issuer_ls180.v:151436$8223 + assign { } { } + assign $0\sr_op__input_carry[1:0] \sr_op__input_carry$next + sync posedge \coresync_clk + update \sr_op__input_carry $0\sr_op__input_carry[1:0] + end + attribute \src "issuer_ls180.v:151438.3-151439.55" + process $proc$issuer_ls180.v:151438$8224 + assign { } { } + assign $0\sr_op__output_carry[0:0] \sr_op__output_carry$next + sync posedge \coresync_clk + update \sr_op__output_carry $0\sr_op__output_carry[0:0] + end + attribute \src "issuer_ls180.v:151440.3-151441.47" + process $proc$issuer_ls180.v:151440$8225 + assign { } { } + assign $0\sr_op__input_cr[0:0] \sr_op__input_cr$next + sync posedge \coresync_clk + update \sr_op__input_cr $0\sr_op__input_cr[0:0] + end + attribute \src "issuer_ls180.v:151442.3-151443.49" + process $proc$issuer_ls180.v:151442$8226 + assign { } { } + assign $0\sr_op__output_cr[0:0] \sr_op__output_cr$next + sync posedge \coresync_clk + update \sr_op__output_cr $0\sr_op__output_cr[0:0] + end + attribute \src "issuer_ls180.v:151444.3-151445.47" + process $proc$issuer_ls180.v:151444$8227 + assign { } { } + assign $0\sr_op__is_32bit[0:0] \sr_op__is_32bit$next + sync posedge \coresync_clk + update \sr_op__is_32bit $0\sr_op__is_32bit[0:0] + end + attribute \src "issuer_ls180.v:151446.3-151447.49" + process $proc$issuer_ls180.v:151446$8228 + assign { } { } + assign $0\sr_op__is_signed[0:0] \sr_op__is_signed$next + sync posedge \coresync_clk + update \sr_op__is_signed $0\sr_op__is_signed[0:0] + end + attribute \src "issuer_ls180.v:151448.3-151449.39" + process $proc$issuer_ls180.v:151448$8229 + assign { } { } + assign $0\sr_op__insn[31:0] \sr_op__insn$next + sync posedge \coresync_clk + update \sr_op__insn $0\sr_op__insn[31:0] + end + attribute \src "issuer_ls180.v:151450.3-151451.27" + process $proc$issuer_ls180.v:151450$8230 + assign { } { } + assign $0\muxid[1:0] \muxid$next + sync posedge \coresync_clk + update \muxid $0\muxid[1:0] + end + attribute \src "issuer_ls180.v:151452.3-151453.29" + process $proc$issuer_ls180.v:151452$8231 + assign { } { } + assign $0\r_busy[0:0] \r_busy$next + sync posedge \coresync_clk + update \r_busy $0\r_busy[0:0] + end + attribute \src "issuer_ls180.v:151552.3-151569.6" + process $proc$issuer_ls180.v:151552$8232 + assign { } { } + assign { } { } + assign { } { } + assign $0\r_busy$next[0:0]$8233 $2\r_busy$next[0:0]$8235 + attribute \src "issuer_ls180.v:151553.5-151553.29" + switch \initial + attribute \src "issuer_ls180.v:151553.9-151553.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\r_busy$next[0:0]$8234 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\r_busy$next[0:0]$8234 1'0 + case + assign $1\r_busy$next[0:0]$8234 \r_busy + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\r_busy$next[0:0]$8235 1'0 + case + assign $2\r_busy$next[0:0]$8235 $1\r_busy$next[0:0]$8234 + end + sync always + update \r_busy$next $0\r_busy$next[0:0]$8233 + end + attribute \src "issuer_ls180.v:151570.3-151582.6" + process $proc$issuer_ls180.v:151570$8236 + assign { } { } + assign { } { } + assign $0\muxid$next[1:0]$8237 $1\muxid$next[1:0]$8238 + attribute \src "issuer_ls180.v:151571.5-151571.29" + switch \initial + attribute \src "issuer_ls180.v:151571.9-151571.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\muxid$next[1:0]$8238 \muxid$64 + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\muxid$next[1:0]$8238 \muxid$64 + case + assign $1\muxid$next[1:0]$8238 \muxid + end + sync always + update \muxid$next $0\muxid$next[1:0]$8237 + end + attribute \src "issuer_ls180.v:151583.3-151622.6" + process $proc$issuer_ls180.v:151583$8239 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\sr_op__fn_unit$next[11:0]$8240 $1\sr_op__fn_unit$next[11:0]$8256 + assign { } { } + assign { } { } + assign $0\sr_op__input_carry$next[1:0]$8243 $1\sr_op__input_carry$next[1:0]$8259 + assign $0\sr_op__input_cr$next[0:0]$8244 $1\sr_op__input_cr$next[0:0]$8260 + assign $0\sr_op__insn$next[31:0]$8245 $1\sr_op__insn$next[31:0]$8261 + assign $0\sr_op__insn_type$next[6:0]$8246 $1\sr_op__insn_type$next[6:0]$8262 + assign $0\sr_op__is_32bit$next[0:0]$8247 $1\sr_op__is_32bit$next[0:0]$8263 + assign $0\sr_op__is_signed$next[0:0]$8248 $1\sr_op__is_signed$next[0:0]$8264 + assign { } { } + assign { } { } + assign $0\sr_op__output_carry$next[0:0]$8251 $1\sr_op__output_carry$next[0:0]$8267 + assign $0\sr_op__output_cr$next[0:0]$8252 $1\sr_op__output_cr$next[0:0]$8268 + assign { } { } + assign { } { } + assign $0\sr_op__write_cr0$next[0:0]$8255 $1\sr_op__write_cr0$next[0:0]$8271 + assign $0\sr_op__imm_data__data$next[63:0]$8241 $2\sr_op__imm_data__data$next[63:0]$8272 + assign $0\sr_op__imm_data__ok$next[0:0]$8242 $2\sr_op__imm_data__ok$next[0:0]$8273 + assign $0\sr_op__oe__oe$next[0:0]$8249 $2\sr_op__oe__oe$next[0:0]$8274 + assign $0\sr_op__oe__ok$next[0:0]$8250 $2\sr_op__oe__ok$next[0:0]$8275 + assign $0\sr_op__rc__ok$next[0:0]$8253 $2\sr_op__rc__ok$next[0:0]$8276 + assign $0\sr_op__rc__rc$next[0:0]$8254 $2\sr_op__rc__rc$next[0:0]$8277 + attribute \src "issuer_ls180.v:151584.5-151584.29" + switch \initial + attribute \src "issuer_ls180.v:151584.9-151584.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'-1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { $1\sr_op__insn$next[31:0]$8261 $1\sr_op__is_signed$next[0:0]$8264 $1\sr_op__is_32bit$next[0:0]$8263 $1\sr_op__output_cr$next[0:0]$8268 $1\sr_op__input_cr$next[0:0]$8260 $1\sr_op__output_carry$next[0:0]$8267 $1\sr_op__input_carry$next[1:0]$8259 $1\sr_op__write_cr0$next[0:0]$8271 $1\sr_op__oe__ok$next[0:0]$8266 $1\sr_op__oe__oe$next[0:0]$8265 $1\sr_op__rc__ok$next[0:0]$8269 $1\sr_op__rc__rc$next[0:0]$8270 $1\sr_op__imm_data__ok$next[0:0]$8258 $1\sr_op__imm_data__data$next[63:0]$8257 $1\sr_op__fn_unit$next[11:0]$8256 $1\sr_op__insn_type$next[6:0]$8262 } { \sr_op__insn$80 \sr_op__is_signed$79 \sr_op__is_32bit$78 \sr_op__output_cr$77 \sr_op__input_cr$76 \sr_op__output_carry$75 \sr_op__input_carry$74 \sr_op__write_cr0$73 \sr_op__oe__ok$72 \sr_op__oe__oe$71 \sr_op__rc__ok$70 \sr_op__rc__rc$69 \sr_op__imm_data__ok$68 \sr_op__imm_data__data$67 \sr_op__fn_unit$66 \sr_op__insn_type$65 } + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'1- + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { $1\sr_op__insn$next[31:0]$8261 $1\sr_op__is_signed$next[0:0]$8264 $1\sr_op__is_32bit$next[0:0]$8263 $1\sr_op__output_cr$next[0:0]$8268 $1\sr_op__input_cr$next[0:0]$8260 $1\sr_op__output_carry$next[0:0]$8267 $1\sr_op__input_carry$next[1:0]$8259 $1\sr_op__write_cr0$next[0:0]$8271 $1\sr_op__oe__ok$next[0:0]$8266 $1\sr_op__oe__oe$next[0:0]$8265 $1\sr_op__rc__ok$next[0:0]$8269 $1\sr_op__rc__rc$next[0:0]$8270 $1\sr_op__imm_data__ok$next[0:0]$8258 $1\sr_op__imm_data__data$next[63:0]$8257 $1\sr_op__fn_unit$next[11:0]$8256 $1\sr_op__insn_type$next[6:0]$8262 } { \sr_op__insn$80 \sr_op__is_signed$79 \sr_op__is_32bit$78 \sr_op__output_cr$77 \sr_op__input_cr$76 \sr_op__output_carry$75 \sr_op__input_carry$74 \sr_op__write_cr0$73 \sr_op__oe__ok$72 \sr_op__oe__oe$71 \sr_op__rc__ok$70 \sr_op__rc__rc$69 \sr_op__imm_data__ok$68 \sr_op__imm_data__data$67 \sr_op__fn_unit$66 \sr_op__insn_type$65 } + case + assign $1\sr_op__fn_unit$next[11:0]$8256 \sr_op__fn_unit + assign $1\sr_op__imm_data__data$next[63:0]$8257 \sr_op__imm_data__data + assign $1\sr_op__imm_data__ok$next[0:0]$8258 \sr_op__imm_data__ok + assign $1\sr_op__input_carry$next[1:0]$8259 \sr_op__input_carry + assign $1\sr_op__input_cr$next[0:0]$8260 \sr_op__input_cr + assign $1\sr_op__insn$next[31:0]$8261 \sr_op__insn + assign $1\sr_op__insn_type$next[6:0]$8262 \sr_op__insn_type + assign $1\sr_op__is_32bit$next[0:0]$8263 \sr_op__is_32bit + assign $1\sr_op__is_signed$next[0:0]$8264 \sr_op__is_signed + assign $1\sr_op__oe__oe$next[0:0]$8265 \sr_op__oe__oe + assign $1\sr_op__oe__ok$next[0:0]$8266 \sr_op__oe__ok + assign $1\sr_op__output_carry$next[0:0]$8267 \sr_op__output_carry + assign $1\sr_op__output_cr$next[0:0]$8268 \sr_op__output_cr + assign $1\sr_op__rc__ok$next[0:0]$8269 \sr_op__rc__ok + assign $1\sr_op__rc__rc$next[0:0]$8270 \sr_op__rc__rc + assign $1\sr_op__write_cr0$next[0:0]$8271 \sr_op__write_cr0 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $2\sr_op__imm_data__data$next[63:0]$8272 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\sr_op__imm_data__ok$next[0:0]$8273 1'0 + assign $2\sr_op__rc__rc$next[0:0]$8277 1'0 + assign $2\sr_op__rc__ok$next[0:0]$8276 1'0 + assign $2\sr_op__oe__oe$next[0:0]$8274 1'0 + assign $2\sr_op__oe__ok$next[0:0]$8275 1'0 + case + assign $2\sr_op__imm_data__data$next[63:0]$8272 $1\sr_op__imm_data__data$next[63:0]$8257 + assign $2\sr_op__imm_data__ok$next[0:0]$8273 $1\sr_op__imm_data__ok$next[0:0]$8258 + assign $2\sr_op__oe__oe$next[0:0]$8274 $1\sr_op__oe__oe$next[0:0]$8265 + assign $2\sr_op__oe__ok$next[0:0]$8275 $1\sr_op__oe__ok$next[0:0]$8266 + assign $2\sr_op__rc__ok$next[0:0]$8276 $1\sr_op__rc__ok$next[0:0]$8269 + assign $2\sr_op__rc__rc$next[0:0]$8277 $1\sr_op__rc__rc$next[0:0]$8270 + end + sync always + update \sr_op__fn_unit$next $0\sr_op__fn_unit$next[11:0]$8240 + update \sr_op__imm_data__data$next $0\sr_op__imm_data__data$next[63:0]$8241 + update \sr_op__imm_data__ok$next $0\sr_op__imm_data__ok$next[0:0]$8242 + update \sr_op__input_carry$next $0\sr_op__input_carry$next[1:0]$8243 + update \sr_op__input_cr$next $0\sr_op__input_cr$next[0:0]$8244 + update \sr_op__insn$next $0\sr_op__insn$next[31:0]$8245 + update \sr_op__insn_type$next $0\sr_op__insn_type$next[6:0]$8246 + update \sr_op__is_32bit$next $0\sr_op__is_32bit$next[0:0]$8247 + update \sr_op__is_signed$next $0\sr_op__is_signed$next[0:0]$8248 + update \sr_op__oe__oe$next $0\sr_op__oe__oe$next[0:0]$8249 + update \sr_op__oe__ok$next $0\sr_op__oe__ok$next[0:0]$8250 + update \sr_op__output_carry$next $0\sr_op__output_carry$next[0:0]$8251 + update \sr_op__output_cr$next $0\sr_op__output_cr$next[0:0]$8252 + update \sr_op__rc__ok$next $0\sr_op__rc__ok$next[0:0]$8253 + update \sr_op__rc__rc$next $0\sr_op__rc__rc$next[0:0]$8254 + update \sr_op__write_cr0$next $0\sr_op__write_cr0$next[0:0]$8255 + end + attribute \src "issuer_ls180.v:151623.3-151641.6" + process $proc$issuer_ls180.v:151623$8278 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\o$next[63:0]$8279 $1\o$next[63:0]$8281 + assign { } { } + assign $0\o_ok$next[0:0]$8280 $2\o_ok$next[0:0]$8283 + attribute \src "issuer_ls180.v:151624.5-151624.29" + switch \initial + attribute \src "issuer_ls180.v:151624.9-151624.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'-1 + assign { } { } + assign { } { } + assign { $1\o_ok$next[0:0]$8282 $1\o$next[63:0]$8281 } { \o_ok$82 \o$81 } + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'1- + assign { } { } + assign { } { } + assign { $1\o_ok$next[0:0]$8282 $1\o$next[63:0]$8281 } { \o_ok$82 \o$81 } + case + assign $1\o$next[63:0]$8281 \o + assign $1\o_ok$next[0:0]$8282 \o_ok + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\o_ok$next[0:0]$8283 1'0 + case + assign $2\o_ok$next[0:0]$8283 $1\o_ok$next[0:0]$8282 + end + sync always + update \o$next $0\o$next[63:0]$8279 + update \o_ok$next $0\o_ok$next[0:0]$8280 + end + attribute \src "issuer_ls180.v:151642.3-151660.6" + process $proc$issuer_ls180.v:151642$8284 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\cr_a$next[3:0]$8285 $1\cr_a$next[3:0]$8287 + assign { } { } + assign $0\cr_a_ok$next[0:0]$8286 $2\cr_a_ok$next[0:0]$8289 + attribute \src "issuer_ls180.v:151643.5-151643.29" + switch \initial + attribute \src "issuer_ls180.v:151643.9-151643.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'-1 + assign { } { } + assign { } { } + assign { $1\cr_a_ok$next[0:0]$8288 $1\cr_a$next[3:0]$8287 } { \cr_a_ok$84 \cr_a$83 } + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'1- + assign { } { } + assign { } { } + assign { $1\cr_a_ok$next[0:0]$8288 $1\cr_a$next[3:0]$8287 } { \cr_a_ok$84 \cr_a$83 } + case + assign $1\cr_a$next[3:0]$8287 \cr_a + assign $1\cr_a_ok$next[0:0]$8288 \cr_a_ok + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\cr_a_ok$next[0:0]$8289 1'0 + case + assign $2\cr_a_ok$next[0:0]$8289 $1\cr_a_ok$next[0:0]$8288 + end + sync always + update \cr_a$next $0\cr_a$next[3:0]$8285 + update \cr_a_ok$next $0\cr_a_ok$next[0:0]$8286 + end + attribute \src "issuer_ls180.v:151661.3-151679.6" + process $proc$issuer_ls180.v:151661$8290 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\xer_so$next[0:0]$8291 $1\xer_so$next[0:0]$8293 + assign { } { } + assign $0\xer_so_ok$next[0:0]$8292 $2\xer_so_ok$next[0:0]$8295 + attribute \src "issuer_ls180.v:151662.5-151662.29" + switch \initial + attribute \src "issuer_ls180.v:151662.9-151662.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'-1 + assign { } { } + assign { } { } + assign { $1\xer_so_ok$next[0:0]$8294 $1\xer_so$next[0:0]$8293 } { \xer_so_ok$88 \xer_so$87 } + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'1- + assign { } { } + assign { } { } + assign { $1\xer_so_ok$next[0:0]$8294 $1\xer_so$next[0:0]$8293 } { \xer_so_ok$88 \xer_so$87 } + case + assign $1\xer_so$next[0:0]$8293 \xer_so + assign $1\xer_so_ok$next[0:0]$8294 \xer_so_ok + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\xer_so_ok$next[0:0]$8295 1'0 + case + assign $2\xer_so_ok$next[0:0]$8295 $1\xer_so_ok$next[0:0]$8294 + end + sync always + update \xer_so$next $0\xer_so$next[0:0]$8291 + update \xer_so_ok$next $0\xer_so_ok$next[0:0]$8292 + end + attribute \src "issuer_ls180.v:151680.3-151698.6" + process $proc$issuer_ls180.v:151680$8296 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\xer_ca$next[1:0]$8298 $1\xer_ca$next[1:0]$8300 + assign $0\xer_ca_ok$next[0:0]$8297 $2\xer_ca_ok$next[0:0]$8301 + attribute \src "issuer_ls180.v:151681.5-151681.29" + switch \initial + attribute \src "issuer_ls180.v:151681.9-151681.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'-1 + assign { } { } + assign { } { } + assign { $1\xer_ca_ok$next[0:0]$8299 $1\xer_ca$next[1:0]$8300 } { \xer_ca_ok$91 \xer_ca$90 } + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'1- + assign { } { } + assign { } { } + assign { $1\xer_ca_ok$next[0:0]$8299 $1\xer_ca$next[1:0]$8300 } { \xer_ca_ok$91 \xer_ca$90 } + case + assign $1\xer_ca_ok$next[0:0]$8299 \xer_ca_ok + assign $1\xer_ca$next[1:0]$8300 \xer_ca + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\xer_ca_ok$next[0:0]$8301 1'0 + case + assign $2\xer_ca_ok$next[0:0]$8301 $1\xer_ca_ok$next[0:0]$8299 + end + sync always + update \xer_ca_ok$next $0\xer_ca_ok$next[0:0]$8297 + update \xer_ca$next $0\xer_ca$next[1:0]$8298 + end + connect \$62 $and$issuer_ls180.v:151401$8205_Y + connect \cr_a$85 4'0000 + connect \cr_a_ok$86 1'0 + connect \xer_so_ok$89 1'0 + connect \xer_ca_ok$92 1'0 + connect \p_ready_o \n_i_rdy_data + connect \n_valid_o \r_busy + connect { \xer_ca_ok$91 \xer_ca$90 } { 1'0 \main_xer_ca } + connect { \xer_so_ok$88 \xer_so$87 } { 1'0 \main_xer_so$59 } + connect { \cr_a_ok$84 \cr_a$83 } 5'00000 + connect { \o_ok$82 \o$81 } { \main_o_ok \main_o } + connect { \sr_op__insn$80 \sr_op__is_signed$79 \sr_op__is_32bit$78 \sr_op__output_cr$77 \sr_op__input_cr$76 \sr_op__output_carry$75 \sr_op__input_carry$74 \sr_op__write_cr0$73 \sr_op__oe__ok$72 \sr_op__oe__oe$71 \sr_op__rc__ok$70 \sr_op__rc__rc$69 \sr_op__imm_data__ok$68 \sr_op__imm_data__data$67 \sr_op__fn_unit$66 \sr_op__insn_type$65 } { \main_sr_op__insn$58 \main_sr_op__is_signed$57 \main_sr_op__is_32bit$56 \main_sr_op__output_cr$55 \main_sr_op__input_cr$54 \main_sr_op__output_carry$53 \main_sr_op__input_carry$52 \main_sr_op__write_cr0$51 \main_sr_op__oe__ok$50 \main_sr_op__oe__oe$49 \main_sr_op__rc__ok$48 \main_sr_op__rc__rc$47 \main_sr_op__imm_data__ok$46 \main_sr_op__imm_data__data$45 \main_sr_op__fn_unit$44 \main_sr_op__insn_type$43 } + connect \muxid$64 \main_muxid$42 + connect \p_valid_i_p_ready_o \$62 + connect \n_i_rdy_data \n_ready_i + connect \p_valid_i$61 \p_valid_i + connect \xer_ca$60 \input_xer_ca$41 + connect \main_xer_so \input_xer_so$40 + connect \main_rc \input_rc$39 + connect \main_rb \input_rb$38 + connect \main_ra \input_ra$37 + connect { \main_sr_op__insn \main_sr_op__is_signed \main_sr_op__is_32bit \main_sr_op__output_cr \main_sr_op__input_cr \main_sr_op__output_carry \main_sr_op__input_carry \main_sr_op__write_cr0 \main_sr_op__oe__ok \main_sr_op__oe__oe \main_sr_op__rc__ok \main_sr_op__rc__rc \main_sr_op__imm_data__ok \main_sr_op__imm_data__data \main_sr_op__fn_unit \main_sr_op__insn_type } { \input_sr_op__insn$36 \input_sr_op__is_signed$35 \input_sr_op__is_32bit$34 \input_sr_op__output_cr$33 \input_sr_op__input_cr$32 \input_sr_op__output_carry$31 \input_sr_op__input_carry$30 \input_sr_op__write_cr0$29 \input_sr_op__oe__ok$28 \input_sr_op__oe__oe$27 \input_sr_op__rc__ok$26 \input_sr_op__rc__rc$25 \input_sr_op__imm_data__ok$24 \input_sr_op__imm_data__data$23 \input_sr_op__fn_unit$22 \input_sr_op__insn_type$21 } + connect \main_muxid \input_muxid$20 + connect \input_xer_ca \xer_ca$19 + connect \input_xer_so \xer_so$18 + connect \input_rc \rc + connect \input_rb \rb + connect \input_ra \ra + connect { \input_sr_op__insn \input_sr_op__is_signed \input_sr_op__is_32bit \input_sr_op__output_cr \input_sr_op__input_cr \input_sr_op__output_carry \input_sr_op__input_carry \input_sr_op__write_cr0 \input_sr_op__oe__ok \input_sr_op__oe__oe \input_sr_op__rc__ok \input_sr_op__rc__rc \input_sr_op__imm_data__ok \input_sr_op__imm_data__data \input_sr_op__fn_unit \input_sr_op__insn_type } { \sr_op__insn$17 \sr_op__is_signed$16 \sr_op__is_32bit$15 \sr_op__output_cr$14 \sr_op__input_cr$13 \sr_op__output_carry$12 \sr_op__input_carry$11 \sr_op__write_cr0$10 \sr_op__oe__ok$9 \sr_op__oe__oe$8 \sr_op__rc__ok$7 \sr_op__rc__rc$6 \sr_op__imm_data__ok$5 \sr_op__imm_data__data$4 \sr_op__fn_unit$3 \sr_op__insn_type$2 } + connect \input_muxid \muxid$1 +end +attribute \src "issuer_ls180.v:151732.1-152902.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.fus.alu0.alu_alu0.pipe2" +attribute \generator "nMigen" +module \pipe2 + attribute \src "issuer_ls180.v:152746.3-152787.6" + wire width 4 $0\alu_op__data_len$18$next[3:0]$8397 + attribute \src "issuer_ls180.v:152643.3-152644.57" + wire width 4 $0\alu_op__data_len$18[3:0]$8383 + attribute \src "issuer_ls180.v:151740.13-151740.41" + wire width 4 $0\alu_op__data_len$18[3:0]$8471 + attribute \src "issuer_ls180.v:152746.3-152787.6" + wire width 12 $0\alu_op__fn_unit$3$next[11:0]$8398 + attribute \src "issuer_ls180.v:152613.3-152614.53" + wire width 12 $0\alu_op__fn_unit$3[11:0]$8353 + attribute \src "issuer_ls180.v:151775.14-151775.43" + wire width 12 $0\alu_op__fn_unit$3[11:0]$8473 + attribute \src "issuer_ls180.v:152746.3-152787.6" + wire width 64 $0\alu_op__imm_data__data$4$next[63:0]$8399 + attribute \src "issuer_ls180.v:152615.3-152616.67" + wire width 64 $0\alu_op__imm_data__data$4[63:0]$8355 + attribute \src "issuer_ls180.v:151797.14-151797.63" + wire width 64 $0\alu_op__imm_data__data$4[63:0]$8475 + attribute \src "issuer_ls180.v:152746.3-152787.6" + wire $0\alu_op__imm_data__ok$5$next[0:0]$8400 + attribute \src "issuer_ls180.v:152617.3-152618.63" + wire $0\alu_op__imm_data__ok$5[0:0]$8357 + attribute \src "issuer_ls180.v:151806.7-151806.38" + wire $0\alu_op__imm_data__ok$5[0:0]$8477 + attribute \src "issuer_ls180.v:152746.3-152787.6" + wire width 2 $0\alu_op__input_carry$14$next[1:0]$8401 + attribute \src "issuer_ls180.v:152635.3-152636.63" + wire width 2 $0\alu_op__input_carry$14[1:0]$8375 + attribute \src "issuer_ls180.v:151823.13-151823.44" + wire width 2 $0\alu_op__input_carry$14[1:0]$8479 + attribute \src "issuer_ls180.v:152746.3-152787.6" + wire width 32 $0\alu_op__insn$19$next[31:0]$8402 + attribute \src "issuer_ls180.v:152645.3-152646.49" + wire width 32 $0\alu_op__insn$19[31:0]$8385 + attribute \src "issuer_ls180.v:151836.14-151836.39" + wire width 32 $0\alu_op__insn$19[31:0]$8481 + attribute \src "issuer_ls180.v:152746.3-152787.6" + wire width 7 $0\alu_op__insn_type$2$next[6:0]$8403 + attribute \src "issuer_ls180.v:152611.3-152612.57" + wire width 7 $0\alu_op__insn_type$2[6:0]$8351 + attribute \src "issuer_ls180.v:151993.13-151993.42" + wire width 7 $0\alu_op__insn_type$2[6:0]$8483 + attribute \src "issuer_ls180.v:152746.3-152787.6" + wire $0\alu_op__invert_in$10$next[0:0]$8404 + attribute \src "issuer_ls180.v:152627.3-152628.59" + wire $0\alu_op__invert_in$10[0:0]$8367 + attribute \src "issuer_ls180.v:152076.7-152076.36" + wire $0\alu_op__invert_in$10[0:0]$8485 + attribute \src "issuer_ls180.v:152746.3-152787.6" + wire $0\alu_op__invert_out$12$next[0:0]$8405 + attribute \src "issuer_ls180.v:152631.3-152632.61" + wire $0\alu_op__invert_out$12[0:0]$8371 + attribute \src "issuer_ls180.v:152085.7-152085.37" + wire $0\alu_op__invert_out$12[0:0]$8487 + attribute \src "issuer_ls180.v:152746.3-152787.6" + wire $0\alu_op__is_32bit$16$next[0:0]$8406 + attribute \src "issuer_ls180.v:152639.3-152640.57" + wire $0\alu_op__is_32bit$16[0:0]$8379 + attribute \src "issuer_ls180.v:152094.7-152094.35" + wire $0\alu_op__is_32bit$16[0:0]$8489 + attribute \src "issuer_ls180.v:152746.3-152787.6" + wire $0\alu_op__is_signed$17$next[0:0]$8407 + attribute \src "issuer_ls180.v:152641.3-152642.59" + wire $0\alu_op__is_signed$17[0:0]$8381 + attribute \src "issuer_ls180.v:152103.7-152103.36" + wire $0\alu_op__is_signed$17[0:0]$8491 + attribute \src "issuer_ls180.v:152746.3-152787.6" + wire $0\alu_op__oe__oe$8$next[0:0]$8408 + attribute \src "issuer_ls180.v:152623.3-152624.51" + wire $0\alu_op__oe__oe$8[0:0]$8363 + attribute \src "issuer_ls180.v:152114.7-152114.32" + wire $0\alu_op__oe__oe$8[0:0]$8493 + attribute \src "issuer_ls180.v:152746.3-152787.6" + wire $0\alu_op__oe__ok$9$next[0:0]$8409 + attribute \src "issuer_ls180.v:152625.3-152626.51" + wire $0\alu_op__oe__ok$9[0:0]$8365 + attribute \src "issuer_ls180.v:152123.7-152123.32" + wire $0\alu_op__oe__ok$9[0:0]$8495 + attribute \src "issuer_ls180.v:152746.3-152787.6" + wire $0\alu_op__output_carry$15$next[0:0]$8410 + attribute \src "issuer_ls180.v:152637.3-152638.65" + wire $0\alu_op__output_carry$15[0:0]$8377 + attribute \src "issuer_ls180.v:152130.7-152130.39" + wire $0\alu_op__output_carry$15[0:0]$8497 + attribute \src "issuer_ls180.v:152746.3-152787.6" + wire $0\alu_op__rc__ok$7$next[0:0]$8411 + attribute \src "issuer_ls180.v:152621.3-152622.51" + wire $0\alu_op__rc__ok$7[0:0]$8361 + attribute \src "issuer_ls180.v:152141.7-152141.32" + wire $0\alu_op__rc__ok$7[0:0]$8499 + attribute \src "issuer_ls180.v:152746.3-152787.6" + wire $0\alu_op__rc__rc$6$next[0:0]$8412 + attribute \src "issuer_ls180.v:152619.3-152620.51" + wire $0\alu_op__rc__rc$6[0:0]$8359 + attribute \src "issuer_ls180.v:152148.7-152148.32" + wire $0\alu_op__rc__rc$6[0:0]$8501 + attribute \src "issuer_ls180.v:152746.3-152787.6" + wire $0\alu_op__write_cr0$13$next[0:0]$8413 + attribute \src "issuer_ls180.v:152633.3-152634.59" + wire $0\alu_op__write_cr0$13[0:0]$8373 + attribute \src "issuer_ls180.v:152157.7-152157.36" + wire $0\alu_op__write_cr0$13[0:0]$8503 + attribute \src "issuer_ls180.v:152746.3-152787.6" + wire $0\alu_op__zero_a$11$next[0:0]$8414 + attribute \src "issuer_ls180.v:152629.3-152630.53" + wire $0\alu_op__zero_a$11[0:0]$8369 + attribute \src "issuer_ls180.v:152166.7-152166.33" + wire $0\alu_op__zero_a$11[0:0]$8505 + attribute \src "issuer_ls180.v:152807.3-152825.6" + wire width 4 $0\cr_a$22$next[3:0]$8446 + attribute \src "issuer_ls180.v:152603.3-152604.33" + wire width 4 $0\cr_a$22[3:0]$8343 + attribute \src "issuer_ls180.v:152179.13-152179.29" + wire width 4 $0\cr_a$22[3:0]$8507 + attribute \src "issuer_ls180.v:152807.3-152825.6" + wire $0\cr_a_ok$23$next[0:0]$8447 + attribute \src "issuer_ls180.v:152605.3-152606.39" + wire $0\cr_a_ok$23[0:0]$8345 + attribute \src "issuer_ls180.v:152188.7-152188.26" + wire $0\cr_a_ok$23[0:0]$8509 + attribute \src "issuer_ls180.v:151733.7-151733.20" + wire $0\initial[0:0] + attribute \src "issuer_ls180.v:152733.3-152745.6" + wire width 2 $0\muxid$1$next[1:0]$8394 + attribute \src "issuer_ls180.v:152647.3-152648.33" + wire width 2 $0\muxid$1[1:0]$8387 + attribute \src "issuer_ls180.v:152199.13-152199.29" + wire width 2 $0\muxid$1[1:0]$8511 + attribute \src "issuer_ls180.v:152788.3-152806.6" + wire width 64 $0\o$20$next[63:0]$8440 + attribute \src "issuer_ls180.v:152607.3-152608.27" + wire width 64 $0\o$20[63:0]$8347 + attribute \src "issuer_ls180.v:152214.14-152214.43" + wire width 64 $0\o$20[63:0]$8513 + attribute \src "issuer_ls180.v:152788.3-152806.6" + wire $0\o_ok$21$next[0:0]$8441 + attribute \src "issuer_ls180.v:152609.3-152610.33" + wire $0\o_ok$21[0:0]$8349 + attribute \src "issuer_ls180.v:152223.7-152223.23" + wire $0\o_ok$21[0:0]$8515 + attribute \src "issuer_ls180.v:152715.3-152732.6" + wire $0\r_busy$next[0:0]$8390 + attribute \src "issuer_ls180.v:152649.3-152650.29" + wire $0\r_busy[0:0] + attribute \src "issuer_ls180.v:152826.3-152844.6" + wire width 2 $0\xer_ca$24$next[1:0]$8452 + attribute \src "issuer_ls180.v:152599.3-152600.37" + wire width 2 $0\xer_ca$24[1:0]$8339 + attribute \src "issuer_ls180.v:152534.13-152534.31" + wire width 2 $0\xer_ca$24[1:0]$8518 + attribute \src "issuer_ls180.v:152826.3-152844.6" + wire $0\xer_ca_ok$25$next[0:0]$8453 + attribute \src "issuer_ls180.v:152601.3-152602.43" + wire $0\xer_ca_ok$25[0:0]$8341 + attribute \src "issuer_ls180.v:152543.7-152543.28" + wire $0\xer_ca_ok$25[0:0]$8520 + attribute \src "issuer_ls180.v:152845.3-152863.6" + wire width 2 $0\xer_ov$26$next[1:0]$8458 + attribute \src "issuer_ls180.v:152595.3-152596.37" + wire width 2 $0\xer_ov$26[1:0]$8335 + attribute \src "issuer_ls180.v:152554.13-152554.31" + wire width 2 $0\xer_ov$26[1:0]$8522 + attribute \src "issuer_ls180.v:152845.3-152863.6" + wire $0\xer_ov_ok$27$next[0:0]$8459 + attribute \src "issuer_ls180.v:152597.3-152598.43" + wire $0\xer_ov_ok$27[0:0]$8337 + attribute \src "issuer_ls180.v:152563.7-152563.28" + wire $0\xer_ov_ok$27[0:0]$8524 + attribute \src "issuer_ls180.v:152864.3-152882.6" + wire $0\xer_so$28$next[0:0]$8464 + attribute \src "issuer_ls180.v:152591.3-152592.37" + wire $0\xer_so$28[0:0]$8331 + attribute \src "issuer_ls180.v:152574.7-152574.25" + wire $0\xer_so$28[0:0]$8526 + attribute \src "issuer_ls180.v:152864.3-152882.6" + wire $0\xer_so_ok$29$next[0:0]$8465 + attribute \src "issuer_ls180.v:152593.3-152594.43" + wire $0\xer_so_ok$29[0:0]$8333 + attribute \src "issuer_ls180.v:152583.7-152583.28" + wire $0\xer_so_ok$29[0:0]$8528 + attribute \src "issuer_ls180.v:152746.3-152787.6" + wire width 4 $1\alu_op__data_len$18$next[3:0]$8415 + attribute \src "issuer_ls180.v:152746.3-152787.6" + wire width 12 $1\alu_op__fn_unit$3$next[11:0]$8416 + attribute \src "issuer_ls180.v:152746.3-152787.6" + wire width 64 $1\alu_op__imm_data__data$4$next[63:0]$8417 + attribute \src "issuer_ls180.v:152746.3-152787.6" + wire $1\alu_op__imm_data__ok$5$next[0:0]$8418 + attribute \src "issuer_ls180.v:152746.3-152787.6" + wire width 2 $1\alu_op__input_carry$14$next[1:0]$8419 + attribute \src "issuer_ls180.v:152746.3-152787.6" + wire width 32 $1\alu_op__insn$19$next[31:0]$8420 + attribute \src "issuer_ls180.v:152746.3-152787.6" + wire width 7 $1\alu_op__insn_type$2$next[6:0]$8421 + attribute \src "issuer_ls180.v:152746.3-152787.6" + wire $1\alu_op__invert_in$10$next[0:0]$8422 + attribute \src "issuer_ls180.v:152746.3-152787.6" + wire $1\alu_op__invert_out$12$next[0:0]$8423 + attribute \src "issuer_ls180.v:152746.3-152787.6" + wire $1\alu_op__is_32bit$16$next[0:0]$8424 + attribute \src "issuer_ls180.v:152746.3-152787.6" + wire $1\alu_op__is_signed$17$next[0:0]$8425 + attribute \src "issuer_ls180.v:152746.3-152787.6" + wire $1\alu_op__oe__oe$8$next[0:0]$8426 + attribute \src "issuer_ls180.v:152746.3-152787.6" + wire $1\alu_op__oe__ok$9$next[0:0]$8427 + attribute \src "issuer_ls180.v:152746.3-152787.6" + wire $1\alu_op__output_carry$15$next[0:0]$8428 + attribute \src "issuer_ls180.v:152746.3-152787.6" + wire $1\alu_op__rc__ok$7$next[0:0]$8429 + attribute \src "issuer_ls180.v:152746.3-152787.6" + wire $1\alu_op__rc__rc$6$next[0:0]$8430 + attribute \src "issuer_ls180.v:152746.3-152787.6" + wire $1\alu_op__write_cr0$13$next[0:0]$8431 + attribute \src "issuer_ls180.v:152746.3-152787.6" + wire $1\alu_op__zero_a$11$next[0:0]$8432 + attribute \src "issuer_ls180.v:152807.3-152825.6" + wire width 4 $1\cr_a$22$next[3:0]$8448 + attribute \src "issuer_ls180.v:152807.3-152825.6" + wire $1\cr_a_ok$23$next[0:0]$8449 + attribute \src "issuer_ls180.v:152733.3-152745.6" + wire width 2 $1\muxid$1$next[1:0]$8395 + attribute \src "issuer_ls180.v:152788.3-152806.6" + wire width 64 $1\o$20$next[63:0]$8442 + attribute \src "issuer_ls180.v:152788.3-152806.6" + wire $1\o_ok$21$next[0:0]$8443 + attribute \src "issuer_ls180.v:152715.3-152732.6" + wire $1\r_busy$next[0:0]$8391 + attribute \src "issuer_ls180.v:152527.7-152527.20" + wire $1\r_busy[0:0] + attribute \src "issuer_ls180.v:152826.3-152844.6" + wire width 2 $1\xer_ca$24$next[1:0]$8454 + attribute \src "issuer_ls180.v:152826.3-152844.6" + wire $1\xer_ca_ok$25$next[0:0]$8455 + attribute \src "issuer_ls180.v:152845.3-152863.6" + wire width 2 $1\xer_ov$26$next[1:0]$8460 + attribute \src "issuer_ls180.v:152845.3-152863.6" + wire $1\xer_ov_ok$27$next[0:0]$8461 + attribute \src "issuer_ls180.v:152864.3-152882.6" + wire $1\xer_so$28$next[0:0]$8466 + attribute \src "issuer_ls180.v:152864.3-152882.6" + wire $1\xer_so_ok$29$next[0:0]$8467 + attribute \src "issuer_ls180.v:152746.3-152787.6" + wire width 64 $2\alu_op__imm_data__data$4$next[63:0]$8433 + attribute \src "issuer_ls180.v:152746.3-152787.6" + wire $2\alu_op__imm_data__ok$5$next[0:0]$8434 + attribute \src "issuer_ls180.v:152746.3-152787.6" + wire $2\alu_op__oe__oe$8$next[0:0]$8435 + attribute \src "issuer_ls180.v:152746.3-152787.6" + wire $2\alu_op__oe__ok$9$next[0:0]$8436 + attribute \src "issuer_ls180.v:152746.3-152787.6" + wire $2\alu_op__rc__ok$7$next[0:0]$8437 + attribute \src "issuer_ls180.v:152746.3-152787.6" + wire $2\alu_op__rc__rc$6$next[0:0]$8438 + attribute \src "issuer_ls180.v:152807.3-152825.6" + wire $2\cr_a_ok$23$next[0:0]$8450 + attribute \src "issuer_ls180.v:152788.3-152806.6" + wire $2\o_ok$21$next[0:0]$8444 + attribute \src "issuer_ls180.v:152715.3-152732.6" + wire $2\r_busy$next[0:0]$8392 + attribute \src "issuer_ls180.v:152826.3-152844.6" + wire $2\xer_ca_ok$25$next[0:0]$8456 + attribute \src "issuer_ls180.v:152845.3-152863.6" + wire $2\xer_ov_ok$27$next[0:0]$8462 + attribute \src "issuer_ls180.v:152864.3-152882.6" + wire $2\xer_so_ok$29$next[0:0]$8468 + attribute \src "issuer_ls180.v:152590.18-152590.118" + wire $and$issuer_ls180.v:152590$8329_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" + wire \$60 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 input 21 \alu_op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 output 52 \alu_op__data_len$18 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \alu_op__data_len$18$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \alu_op__data_len$79 + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 input 6 \alu_op__fn_unit + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 output 37 \alu_op__fn_unit$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 \alu_op__fn_unit$3$next + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 \alu_op__fn_unit$64 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 input 7 \alu_op__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 output 38 \alu_op__imm_data__data$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \alu_op__imm_data__data$4$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \alu_op__imm_data__data$65 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 8 \alu_op__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 39 \alu_op__imm_data__ok$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__imm_data__ok$5$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__imm_data__ok$66 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 input 17 \alu_op__input_carry + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 output 48 \alu_op__input_carry$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \alu_op__input_carry$14$next + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \alu_op__input_carry$75 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 22 \alu_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 output 53 \alu_op__insn$19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \alu_op__insn$19$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \alu_op__insn$80 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 input 5 \alu_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 output 36 \alu_op__insn_type$2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \alu_op__insn_type$2$next + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \alu_op__insn_type$63 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 13 \alu_op__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 44 \alu_op__invert_in$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__invert_in$10$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__invert_in$71 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 15 \alu_op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 46 \alu_op__invert_out$12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__invert_out$12$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__invert_out$73 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 19 \alu_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 50 \alu_op__is_32bit$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__is_32bit$16$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__is_32bit$77 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 20 \alu_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 51 \alu_op__is_signed$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__is_signed$17$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__is_signed$78 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 11 \alu_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__oe__oe$69 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 42 \alu_op__oe__oe$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__oe__oe$8$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 12 \alu_op__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__oe__ok$70 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 43 \alu_op__oe__ok$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__oe__ok$9$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 18 \alu_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 49 \alu_op__output_carry$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__output_carry$15$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__output_carry$76 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 10 \alu_op__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__rc__ok$68 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 41 \alu_op__rc__ok$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__rc__ok$7$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 9 \alu_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 40 \alu_op__rc__rc$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__rc__rc$6$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__rc__rc$67 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 16 \alu_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 47 \alu_op__write_cr0$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__write_cr0$13$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__write_cr0$74 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 14 \alu_op__zero_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 45 \alu_op__zero_a$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__zero_a$11$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \alu_op__zero_a$72 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" + wire input 64 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" + wire input 1 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 4 input 25 \cr_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 4 output 56 \cr_a$22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 4 \cr_a$22$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 4 \cr_a$83 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire input 26 \cr_a_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 57 \cr_a_ok$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + 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"OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \output_alu_op__insn_type$31 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_alu_op__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_alu_op__invert_in$39 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_alu_op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_alu_op__invert_out$41 + attribute \src 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\output_alu_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_alu_op__output_carry$44 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_alu_op__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_alu_op__rc__ok$36 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_alu_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_alu_op__rc__rc$35 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_alu_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_alu_op__write_cr0$42 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_alu_op__zero_a + attribute \src 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attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \output_o_ok$50 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 2 \output_xer_ca + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 2 \output_xer_ca$52 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \output_xer_ca_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 2 \output_xer_ov + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 2 \output_xer_ov$53 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \output_xer_ov_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \output_xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \output_xer_so$54 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \output_xer_so_ok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" + wire output 3 \p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" + wire input 2 \p_valid_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:621" + wire \p_valid_i$59 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" + wire \p_valid_i_p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615" + wire \r_busy + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615" + wire \r_busy$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 2 input 27 \xer_ca + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 2 output 58 \xer_ca$24 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 2 \xer_ca$24$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 2 \xer_ca$85 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire input 28 \xer_ca_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 59 \xer_ca_ok$25 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \xer_ca_ok$25$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \xer_ca_ok$56 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \xer_ca_ok$86 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 2 input 29 \xer_ov + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 2 output 60 \xer_ov$26 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 2 \xer_ov$26$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 2 \xer_ov$87 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire input 30 \xer_ov_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 61 \xer_ov_ok$27 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \xer_ov_ok$27$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \xer_ov_ok$57 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \xer_ov_ok$88 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire input 31 \xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 62 \xer_so$28 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \xer_so$28$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \xer_so$89 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire input 32 \xer_so_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 63 \xer_so_ok$29 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \xer_so_ok$29$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \xer_so_ok$58 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \xer_so_ok$90 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" + cell $and $and$issuer_ls180.v:152590$8329 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \p_valid_i$59 + connect \B \p_ready_o + connect \Y $and$issuer_ls180.v:152590$8329_Y + end + attribute \module_not_derived 1 + attribute \src "issuer_ls180.v:152651.9-152654.4" + cell \n$4 \n + connect \n_ready_i \n_ready_i + connect \n_valid_o \n_valid_o + end + attribute \module_not_derived 1 + attribute \src "issuer_ls180.v:152655.12-152710.4" + cell \output \output + connect \alu_op__data_len \output_alu_op__data_len + connect \alu_op__data_len$18 \output_alu_op__data_len$47 + connect \alu_op__fn_unit \output_alu_op__fn_unit + connect \alu_op__fn_unit$3 \output_alu_op__fn_unit$32 + connect \alu_op__imm_data__data \output_alu_op__imm_data__data + connect \alu_op__imm_data__data$4 \output_alu_op__imm_data__data$33 + connect \alu_op__imm_data__ok \output_alu_op__imm_data__ok + connect \alu_op__imm_data__ok$5 \output_alu_op__imm_data__ok$34 + connect \alu_op__input_carry \output_alu_op__input_carry + connect \alu_op__input_carry$14 \output_alu_op__input_carry$43 + connect \alu_op__insn \output_alu_op__insn + connect \alu_op__insn$19 \output_alu_op__insn$48 + connect \alu_op__insn_type \output_alu_op__insn_type + connect \alu_op__insn_type$2 \output_alu_op__insn_type$31 + connect \alu_op__invert_in \output_alu_op__invert_in + connect \alu_op__invert_in$10 \output_alu_op__invert_in$39 + connect \alu_op__invert_out \output_alu_op__invert_out + connect \alu_op__invert_out$12 \output_alu_op__invert_out$41 + connect \alu_op__is_32bit \output_alu_op__is_32bit + connect \alu_op__is_32bit$16 \output_alu_op__is_32bit$45 + connect \alu_op__is_signed \output_alu_op__is_signed + connect \alu_op__is_signed$17 \output_alu_op__is_signed$46 + connect \alu_op__oe__oe \output_alu_op__oe__oe + connect \alu_op__oe__oe$8 \output_alu_op__oe__oe$37 + connect \alu_op__oe__ok \output_alu_op__oe__ok + connect \alu_op__oe__ok$9 \output_alu_op__oe__ok$38 + connect \alu_op__output_carry \output_alu_op__output_carry + connect \alu_op__output_carry$15 \output_alu_op__output_carry$44 + connect \alu_op__rc__ok \output_alu_op__rc__ok + connect \alu_op__rc__ok$7 \output_alu_op__rc__ok$36 + connect \alu_op__rc__rc \output_alu_op__rc__rc + connect \alu_op__rc__rc$6 \output_alu_op__rc__rc$35 + connect \alu_op__write_cr0 \output_alu_op__write_cr0 + connect \alu_op__write_cr0$13 \output_alu_op__write_cr0$42 + connect \alu_op__zero_a \output_alu_op__zero_a + connect \alu_op__zero_a$11 \output_alu_op__zero_a$40 + connect \cr_a \output_cr_a + connect \cr_a$22 \output_cr_a$51 + connect \cr_a_ok \output_cr_a_ok + connect \muxid \output_muxid + connect \muxid$1 \output_muxid$30 + connect \o \output_o + connect \o$20 \output_o$49 + connect \o_ok \output_o_ok + connect \o_ok$21 \output_o_ok$50 + connect \xer_ca \output_xer_ca + connect \xer_ca$23 \output_xer_ca$52 + connect \xer_ca_ok \output_xer_ca_ok + connect \xer_ov \output_xer_ov + connect \xer_ov$24 \output_xer_ov$53 + connect \xer_ov_ok \output_xer_ov_ok + connect \xer_so \output_xer_so + connect \xer_so$25 \output_xer_so$54 + connect \xer_so_ok \output_xer_so_ok + end + attribute \module_not_derived 1 + attribute \src "issuer_ls180.v:152711.9-152714.4" + cell \p$3 \p + connect \p_ready_o \p_ready_o + connect \p_valid_i \p_valid_i + end + attribute \src "issuer_ls180.v:151733.7-151733.20" + process $proc$issuer_ls180.v:151733$8469 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "issuer_ls180.v:151740.13-151740.41" + process $proc$issuer_ls180.v:151740$8470 + assign { } { } + assign $0\alu_op__data_len$18[3:0]$8471 4'0000 + sync always + sync init + update \alu_op__data_len$18 $0\alu_op__data_len$18[3:0]$8471 + end + attribute \src "issuer_ls180.v:151775.14-151775.43" + process $proc$issuer_ls180.v:151775$8472 + assign { } { } + assign $0\alu_op__fn_unit$3[11:0]$8473 12'000000000000 + sync always + sync init + update \alu_op__fn_unit$3 $0\alu_op__fn_unit$3[11:0]$8473 + end + attribute \src "issuer_ls180.v:151797.14-151797.63" + process $proc$issuer_ls180.v:151797$8474 + assign { } { } + assign $0\alu_op__imm_data__data$4[63:0]$8475 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \alu_op__imm_data__data$4 $0\alu_op__imm_data__data$4[63:0]$8475 + end + attribute \src "issuer_ls180.v:151806.7-151806.38" + process $proc$issuer_ls180.v:151806$8476 + assign { } { } + assign $0\alu_op__imm_data__ok$5[0:0]$8477 1'0 + sync always + sync init + update \alu_op__imm_data__ok$5 $0\alu_op__imm_data__ok$5[0:0]$8477 + end + attribute \src "issuer_ls180.v:151823.13-151823.44" + process $proc$issuer_ls180.v:151823$8478 + assign { } { } + assign $0\alu_op__input_carry$14[1:0]$8479 2'00 + sync always + sync init + update \alu_op__input_carry$14 $0\alu_op__input_carry$14[1:0]$8479 + end + attribute \src "issuer_ls180.v:151836.14-151836.39" + process $proc$issuer_ls180.v:151836$8480 + assign { } { } + assign $0\alu_op__insn$19[31:0]$8481 0 + sync always + sync init + update \alu_op__insn$19 $0\alu_op__insn$19[31:0]$8481 + end + attribute \src "issuer_ls180.v:151993.13-151993.42" + process $proc$issuer_ls180.v:151993$8482 + assign { } { } + assign $0\alu_op__insn_type$2[6:0]$8483 7'0000000 + sync always + sync init + update \alu_op__insn_type$2 $0\alu_op__insn_type$2[6:0]$8483 + end + attribute \src "issuer_ls180.v:152076.7-152076.36" + process $proc$issuer_ls180.v:152076$8484 + assign { } { } + assign $0\alu_op__invert_in$10[0:0]$8485 1'0 + sync always + sync init + update \alu_op__invert_in$10 $0\alu_op__invert_in$10[0:0]$8485 + end + attribute \src "issuer_ls180.v:152085.7-152085.37" + process $proc$issuer_ls180.v:152085$8486 + assign { } { } + assign $0\alu_op__invert_out$12[0:0]$8487 1'0 + sync always + sync init + update \alu_op__invert_out$12 $0\alu_op__invert_out$12[0:0]$8487 + end + attribute \src "issuer_ls180.v:152094.7-152094.35" + process $proc$issuer_ls180.v:152094$8488 + assign { } { } + assign $0\alu_op__is_32bit$16[0:0]$8489 1'0 + sync always + sync init + update \alu_op__is_32bit$16 $0\alu_op__is_32bit$16[0:0]$8489 + end + attribute \src "issuer_ls180.v:152103.7-152103.36" + process $proc$issuer_ls180.v:152103$8490 + assign { } { } + assign $0\alu_op__is_signed$17[0:0]$8491 1'0 + sync always + sync init + update \alu_op__is_signed$17 $0\alu_op__is_signed$17[0:0]$8491 + end + attribute \src "issuer_ls180.v:152114.7-152114.32" + process $proc$issuer_ls180.v:152114$8492 + assign { } { } + assign $0\alu_op__oe__oe$8[0:0]$8493 1'0 + sync always + sync init + update \alu_op__oe__oe$8 $0\alu_op__oe__oe$8[0:0]$8493 + end + attribute \src "issuer_ls180.v:152123.7-152123.32" + process $proc$issuer_ls180.v:152123$8494 + assign { } { } + assign $0\alu_op__oe__ok$9[0:0]$8495 1'0 + sync always + sync init + update \alu_op__oe__ok$9 $0\alu_op__oe__ok$9[0:0]$8495 + end + attribute \src "issuer_ls180.v:152130.7-152130.39" + process $proc$issuer_ls180.v:152130$8496 + assign { } { } + assign $0\alu_op__output_carry$15[0:0]$8497 1'0 + sync always + sync init + update \alu_op__output_carry$15 $0\alu_op__output_carry$15[0:0]$8497 + end + attribute \src "issuer_ls180.v:152141.7-152141.32" + process $proc$issuer_ls180.v:152141$8498 + assign { } { } + assign $0\alu_op__rc__ok$7[0:0]$8499 1'0 + sync always + sync init + update \alu_op__rc__ok$7 $0\alu_op__rc__ok$7[0:0]$8499 + end + attribute \src "issuer_ls180.v:152148.7-152148.32" + process $proc$issuer_ls180.v:152148$8500 + assign { } { } + assign $0\alu_op__rc__rc$6[0:0]$8501 1'0 + sync always + sync init + update \alu_op__rc__rc$6 $0\alu_op__rc__rc$6[0:0]$8501 + end + attribute \src "issuer_ls180.v:152157.7-152157.36" + process $proc$issuer_ls180.v:152157$8502 + assign { } { } + assign $0\alu_op__write_cr0$13[0:0]$8503 1'0 + sync always + sync init + update \alu_op__write_cr0$13 $0\alu_op__write_cr0$13[0:0]$8503 + end + attribute \src "issuer_ls180.v:152166.7-152166.33" + process $proc$issuer_ls180.v:152166$8504 + assign { } { } + assign $0\alu_op__zero_a$11[0:0]$8505 1'0 + sync always + sync init + update \alu_op__zero_a$11 $0\alu_op__zero_a$11[0:0]$8505 + end + attribute \src "issuer_ls180.v:152179.13-152179.29" + process $proc$issuer_ls180.v:152179$8506 + assign { } { } + assign $0\cr_a$22[3:0]$8507 4'0000 + sync always + sync init + update \cr_a$22 $0\cr_a$22[3:0]$8507 + end + attribute \src "issuer_ls180.v:152188.7-152188.26" + process $proc$issuer_ls180.v:152188$8508 + assign { } { } + assign $0\cr_a_ok$23[0:0]$8509 1'0 + sync always + sync init + update \cr_a_ok$23 $0\cr_a_ok$23[0:0]$8509 + end + attribute \src "issuer_ls180.v:152199.13-152199.29" + process $proc$issuer_ls180.v:152199$8510 + assign { } { } + assign $0\muxid$1[1:0]$8511 2'00 + sync always + sync init + update \muxid$1 $0\muxid$1[1:0]$8511 + end + attribute \src "issuer_ls180.v:152214.14-152214.43" + process $proc$issuer_ls180.v:152214$8512 + assign { } { } + assign $0\o$20[63:0]$8513 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \o$20 $0\o$20[63:0]$8513 + end + attribute \src "issuer_ls180.v:152223.7-152223.23" + process $proc$issuer_ls180.v:152223$8514 + assign { } { } + assign $0\o_ok$21[0:0]$8515 1'0 + sync always + sync init + update \o_ok$21 $0\o_ok$21[0:0]$8515 + end + attribute \src "issuer_ls180.v:152527.7-152527.20" + process $proc$issuer_ls180.v:152527$8516 + assign { } { } + assign $1\r_busy[0:0] 1'0 + sync always + sync init + update \r_busy $1\r_busy[0:0] + end + attribute \src "issuer_ls180.v:152534.13-152534.31" + process $proc$issuer_ls180.v:152534$8517 + assign { } { } + assign $0\xer_ca$24[1:0]$8518 2'00 + sync always + sync init + update \xer_ca$24 $0\xer_ca$24[1:0]$8518 + end + attribute \src "issuer_ls180.v:152543.7-152543.28" + process $proc$issuer_ls180.v:152543$8519 + assign { } { } + assign $0\xer_ca_ok$25[0:0]$8520 1'0 + sync always + sync init + update \xer_ca_ok$25 $0\xer_ca_ok$25[0:0]$8520 + end + attribute \src "issuer_ls180.v:152554.13-152554.31" + process $proc$issuer_ls180.v:152554$8521 + assign { } { } + assign $0\xer_ov$26[1:0]$8522 2'00 + sync always + sync init + update \xer_ov$26 $0\xer_ov$26[1:0]$8522 + end + attribute \src "issuer_ls180.v:152563.7-152563.28" + process $proc$issuer_ls180.v:152563$8523 + assign { } { } + assign $0\xer_ov_ok$27[0:0]$8524 1'0 + sync always + sync init + update \xer_ov_ok$27 $0\xer_ov_ok$27[0:0]$8524 + end + attribute \src "issuer_ls180.v:152574.7-152574.25" + process $proc$issuer_ls180.v:152574$8525 + assign { } { } + assign $0\xer_so$28[0:0]$8526 1'0 + sync always + sync init + update \xer_so$28 $0\xer_so$28[0:0]$8526 + end + attribute \src "issuer_ls180.v:152583.7-152583.28" + process $proc$issuer_ls180.v:152583$8527 + assign { } { } + assign $0\xer_so_ok$29[0:0]$8528 1'0 + sync always + sync init + update \xer_so_ok$29 $0\xer_so_ok$29[0:0]$8528 + end + attribute \src "issuer_ls180.v:152591.3-152592.37" + process $proc$issuer_ls180.v:152591$8330 + assign { } { } + assign $0\xer_so$28[0:0]$8331 \xer_so$28$next + sync posedge \coresync_clk + update \xer_so$28 $0\xer_so$28[0:0]$8331 + end + attribute \src "issuer_ls180.v:152593.3-152594.43" + process $proc$issuer_ls180.v:152593$8332 + assign { } { } + assign $0\xer_so_ok$29[0:0]$8333 \xer_so_ok$29$next + sync posedge \coresync_clk + update \xer_so_ok$29 $0\xer_so_ok$29[0:0]$8333 + end + attribute \src "issuer_ls180.v:152595.3-152596.37" + process $proc$issuer_ls180.v:152595$8334 + assign { } { } + assign $0\xer_ov$26[1:0]$8335 \xer_ov$26$next + sync posedge \coresync_clk + update \xer_ov$26 $0\xer_ov$26[1:0]$8335 + end + attribute \src "issuer_ls180.v:152597.3-152598.43" + process $proc$issuer_ls180.v:152597$8336 + assign { } { } + assign $0\xer_ov_ok$27[0:0]$8337 \xer_ov_ok$27$next + sync posedge \coresync_clk + update \xer_ov_ok$27 $0\xer_ov_ok$27[0:0]$8337 + end + attribute \src "issuer_ls180.v:152599.3-152600.37" + process $proc$issuer_ls180.v:152599$8338 + assign { } { } + assign $0\xer_ca$24[1:0]$8339 \xer_ca$24$next + sync posedge \coresync_clk + update \xer_ca$24 $0\xer_ca$24[1:0]$8339 + end + attribute \src "issuer_ls180.v:152601.3-152602.43" + process $proc$issuer_ls180.v:152601$8340 + assign { } { } + assign $0\xer_ca_ok$25[0:0]$8341 \xer_ca_ok$25$next + sync posedge \coresync_clk + update \xer_ca_ok$25 $0\xer_ca_ok$25[0:0]$8341 + end + attribute \src "issuer_ls180.v:152603.3-152604.33" + process $proc$issuer_ls180.v:152603$8342 + assign { } { } + assign $0\cr_a$22[3:0]$8343 \cr_a$22$next + sync posedge \coresync_clk + update \cr_a$22 $0\cr_a$22[3:0]$8343 + end + attribute \src "issuer_ls180.v:152605.3-152606.39" + process $proc$issuer_ls180.v:152605$8344 + assign { } { } + assign $0\cr_a_ok$23[0:0]$8345 \cr_a_ok$23$next + sync posedge \coresync_clk + update \cr_a_ok$23 $0\cr_a_ok$23[0:0]$8345 + end + attribute \src "issuer_ls180.v:152607.3-152608.27" + process $proc$issuer_ls180.v:152607$8346 + assign { } { } + assign $0\o$20[63:0]$8347 \o$20$next + sync posedge \coresync_clk + update \o$20 $0\o$20[63:0]$8347 + end + attribute \src "issuer_ls180.v:152609.3-152610.33" + process $proc$issuer_ls180.v:152609$8348 + assign { } { } + assign $0\o_ok$21[0:0]$8349 \o_ok$21$next + sync posedge \coresync_clk + update \o_ok$21 $0\o_ok$21[0:0]$8349 + end + attribute \src "issuer_ls180.v:152611.3-152612.57" + process $proc$issuer_ls180.v:152611$8350 + assign { } { } + assign $0\alu_op__insn_type$2[6:0]$8351 \alu_op__insn_type$2$next + sync posedge \coresync_clk + update \alu_op__insn_type$2 $0\alu_op__insn_type$2[6:0]$8351 + end + attribute \src "issuer_ls180.v:152613.3-152614.53" + process $proc$issuer_ls180.v:152613$8352 + assign { } { } + assign $0\alu_op__fn_unit$3[11:0]$8353 \alu_op__fn_unit$3$next + sync posedge \coresync_clk + update \alu_op__fn_unit$3 $0\alu_op__fn_unit$3[11:0]$8353 + end + attribute \src "issuer_ls180.v:152615.3-152616.67" + process $proc$issuer_ls180.v:152615$8354 + assign { } { } + assign $0\alu_op__imm_data__data$4[63:0]$8355 \alu_op__imm_data__data$4$next + sync posedge \coresync_clk + update \alu_op__imm_data__data$4 $0\alu_op__imm_data__data$4[63:0]$8355 + end + attribute \src "issuer_ls180.v:152617.3-152618.63" + process $proc$issuer_ls180.v:152617$8356 + assign { } { } + assign $0\alu_op__imm_data__ok$5[0:0]$8357 \alu_op__imm_data__ok$5$next + sync posedge \coresync_clk + update \alu_op__imm_data__ok$5 $0\alu_op__imm_data__ok$5[0:0]$8357 + end + attribute \src "issuer_ls180.v:152619.3-152620.51" + process $proc$issuer_ls180.v:152619$8358 + assign { } { } + assign $0\alu_op__rc__rc$6[0:0]$8359 \alu_op__rc__rc$6$next + sync posedge \coresync_clk + update \alu_op__rc__rc$6 $0\alu_op__rc__rc$6[0:0]$8359 + end + attribute \src "issuer_ls180.v:152621.3-152622.51" + process $proc$issuer_ls180.v:152621$8360 + assign { } { } + assign $0\alu_op__rc__ok$7[0:0]$8361 \alu_op__rc__ok$7$next + sync posedge \coresync_clk + update \alu_op__rc__ok$7 $0\alu_op__rc__ok$7[0:0]$8361 + end + attribute \src "issuer_ls180.v:152623.3-152624.51" + process $proc$issuer_ls180.v:152623$8362 + assign { } { } + assign $0\alu_op__oe__oe$8[0:0]$8363 \alu_op__oe__oe$8$next + sync posedge \coresync_clk + update \alu_op__oe__oe$8 $0\alu_op__oe__oe$8[0:0]$8363 + end + attribute \src "issuer_ls180.v:152625.3-152626.51" + process $proc$issuer_ls180.v:152625$8364 + assign { } { } + assign $0\alu_op__oe__ok$9[0:0]$8365 \alu_op__oe__ok$9$next + sync posedge \coresync_clk + update \alu_op__oe__ok$9 $0\alu_op__oe__ok$9[0:0]$8365 + end + attribute \src "issuer_ls180.v:152627.3-152628.59" + process $proc$issuer_ls180.v:152627$8366 + assign { } { } + assign $0\alu_op__invert_in$10[0:0]$8367 \alu_op__invert_in$10$next + sync posedge \coresync_clk + update \alu_op__invert_in$10 $0\alu_op__invert_in$10[0:0]$8367 + end + attribute \src "issuer_ls180.v:152629.3-152630.53" + process $proc$issuer_ls180.v:152629$8368 + assign { } { } + assign $0\alu_op__zero_a$11[0:0]$8369 \alu_op__zero_a$11$next + sync posedge \coresync_clk + update \alu_op__zero_a$11 $0\alu_op__zero_a$11[0:0]$8369 + end + attribute \src "issuer_ls180.v:152631.3-152632.61" + process $proc$issuer_ls180.v:152631$8370 + assign { } { } + assign $0\alu_op__invert_out$12[0:0]$8371 \alu_op__invert_out$12$next + sync posedge \coresync_clk + update \alu_op__invert_out$12 $0\alu_op__invert_out$12[0:0]$8371 + end + attribute \src "issuer_ls180.v:152633.3-152634.59" + process $proc$issuer_ls180.v:152633$8372 + assign { } { } + assign $0\alu_op__write_cr0$13[0:0]$8373 \alu_op__write_cr0$13$next + sync posedge \coresync_clk + update \alu_op__write_cr0$13 $0\alu_op__write_cr0$13[0:0]$8373 + end + attribute \src "issuer_ls180.v:152635.3-152636.63" + process $proc$issuer_ls180.v:152635$8374 + assign { } { } + assign $0\alu_op__input_carry$14[1:0]$8375 \alu_op__input_carry$14$next + sync posedge \coresync_clk + update \alu_op__input_carry$14 $0\alu_op__input_carry$14[1:0]$8375 + end + attribute \src "issuer_ls180.v:152637.3-152638.65" + process $proc$issuer_ls180.v:152637$8376 + assign { } { } + assign $0\alu_op__output_carry$15[0:0]$8377 \alu_op__output_carry$15$next + sync posedge \coresync_clk + update \alu_op__output_carry$15 $0\alu_op__output_carry$15[0:0]$8377 + end + attribute \src "issuer_ls180.v:152639.3-152640.57" + process $proc$issuer_ls180.v:152639$8378 + assign { } { } + assign $0\alu_op__is_32bit$16[0:0]$8379 \alu_op__is_32bit$16$next + sync posedge \coresync_clk + update \alu_op__is_32bit$16 $0\alu_op__is_32bit$16[0:0]$8379 + end + attribute \src "issuer_ls180.v:152641.3-152642.59" + process $proc$issuer_ls180.v:152641$8380 + assign { } { } + assign $0\alu_op__is_signed$17[0:0]$8381 \alu_op__is_signed$17$next + sync posedge \coresync_clk + update \alu_op__is_signed$17 $0\alu_op__is_signed$17[0:0]$8381 + end + attribute \src "issuer_ls180.v:152643.3-152644.57" + process $proc$issuer_ls180.v:152643$8382 + assign { } { } + assign $0\alu_op__data_len$18[3:0]$8383 \alu_op__data_len$18$next + sync posedge \coresync_clk + update \alu_op__data_len$18 $0\alu_op__data_len$18[3:0]$8383 + end + attribute \src "issuer_ls180.v:152645.3-152646.49" + process $proc$issuer_ls180.v:152645$8384 + assign { } { } + assign $0\alu_op__insn$19[31:0]$8385 \alu_op__insn$19$next + sync posedge \coresync_clk + update \alu_op__insn$19 $0\alu_op__insn$19[31:0]$8385 + end + attribute \src "issuer_ls180.v:152647.3-152648.33" + process $proc$issuer_ls180.v:152647$8386 + assign { } { } + assign $0\muxid$1[1:0]$8387 \muxid$1$next + sync posedge \coresync_clk + update \muxid$1 $0\muxid$1[1:0]$8387 + end + attribute \src "issuer_ls180.v:152649.3-152650.29" + process $proc$issuer_ls180.v:152649$8388 + assign { } { } + assign $0\r_busy[0:0] \r_busy$next + sync posedge \coresync_clk + update \r_busy $0\r_busy[0:0] + end + attribute \src "issuer_ls180.v:152715.3-152732.6" + process $proc$issuer_ls180.v:152715$8389 + assign { } { } + assign { } { } + assign { } { } + assign $0\r_busy$next[0:0]$8390 $2\r_busy$next[0:0]$8392 + attribute \src "issuer_ls180.v:152716.5-152716.29" + switch \initial + attribute \src "issuer_ls180.v:152716.9-152716.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\r_busy$next[0:0]$8391 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\r_busy$next[0:0]$8391 1'0 + case + assign $1\r_busy$next[0:0]$8391 \r_busy + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\r_busy$next[0:0]$8392 1'0 + case + assign $2\r_busy$next[0:0]$8392 $1\r_busy$next[0:0]$8391 + end + sync always + update \r_busy$next $0\r_busy$next[0:0]$8390 + end + attribute \src "issuer_ls180.v:152733.3-152745.6" + process $proc$issuer_ls180.v:152733$8393 + assign { } { } + assign { } { } + assign $0\muxid$1$next[1:0]$8394 $1\muxid$1$next[1:0]$8395 + attribute \src "issuer_ls180.v:152734.5-152734.29" + switch \initial + attribute \src "issuer_ls180.v:152734.9-152734.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\muxid$1$next[1:0]$8395 \muxid$62 + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\muxid$1$next[1:0]$8395 \muxid$62 + case + assign $1\muxid$1$next[1:0]$8395 \muxid$1 + end + sync always + update \muxid$1$next $0\muxid$1$next[1:0]$8394 + end + attribute \src "issuer_ls180.v:152746.3-152787.6" + process $proc$issuer_ls180.v:152746$8396 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\alu_op__data_len$18$next[3:0]$8397 $1\alu_op__data_len$18$next[3:0]$8415 + assign $0\alu_op__fn_unit$3$next[11:0]$8398 $1\alu_op__fn_unit$3$next[11:0]$8416 + assign { } { } + assign { } { } + assign $0\alu_op__input_carry$14$next[1:0]$8401 $1\alu_op__input_carry$14$next[1:0]$8419 + assign $0\alu_op__insn$19$next[31:0]$8402 $1\alu_op__insn$19$next[31:0]$8420 + assign $0\alu_op__insn_type$2$next[6:0]$8403 $1\alu_op__insn_type$2$next[6:0]$8421 + assign $0\alu_op__invert_in$10$next[0:0]$8404 $1\alu_op__invert_in$10$next[0:0]$8422 + assign $0\alu_op__invert_out$12$next[0:0]$8405 $1\alu_op__invert_out$12$next[0:0]$8423 + assign $0\alu_op__is_32bit$16$next[0:0]$8406 $1\alu_op__is_32bit$16$next[0:0]$8424 + assign $0\alu_op__is_signed$17$next[0:0]$8407 $1\alu_op__is_signed$17$next[0:0]$8425 + assign { } { } + assign { } { } + assign $0\alu_op__output_carry$15$next[0:0]$8410 $1\alu_op__output_carry$15$next[0:0]$8428 + assign { } { } + assign { } { } + assign $0\alu_op__write_cr0$13$next[0:0]$8413 $1\alu_op__write_cr0$13$next[0:0]$8431 + assign $0\alu_op__zero_a$11$next[0:0]$8414 $1\alu_op__zero_a$11$next[0:0]$8432 + assign $0\alu_op__imm_data__data$4$next[63:0]$8399 $2\alu_op__imm_data__data$4$next[63:0]$8433 + assign $0\alu_op__imm_data__ok$5$next[0:0]$8400 $2\alu_op__imm_data__ok$5$next[0:0]$8434 + assign $0\alu_op__oe__oe$8$next[0:0]$8408 $2\alu_op__oe__oe$8$next[0:0]$8435 + assign $0\alu_op__oe__ok$9$next[0:0]$8409 $2\alu_op__oe__ok$9$next[0:0]$8436 + assign $0\alu_op__rc__ok$7$next[0:0]$8411 $2\alu_op__rc__ok$7$next[0:0]$8437 + assign $0\alu_op__rc__rc$6$next[0:0]$8412 $2\alu_op__rc__rc$6$next[0:0]$8438 + attribute \src "issuer_ls180.v:152747.5-152747.29" + switch \initial + attribute \src "issuer_ls180.v:152747.9-152747.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'-1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { $1\alu_op__insn$19$next[31:0]$8420 $1\alu_op__data_len$18$next[3:0]$8415 $1\alu_op__is_signed$17$next[0:0]$8425 $1\alu_op__is_32bit$16$next[0:0]$8424 $1\alu_op__output_carry$15$next[0:0]$8428 $1\alu_op__input_carry$14$next[1:0]$8419 $1\alu_op__write_cr0$13$next[0:0]$8431 $1\alu_op__invert_out$12$next[0:0]$8423 $1\alu_op__zero_a$11$next[0:0]$8432 $1\alu_op__invert_in$10$next[0:0]$8422 $1\alu_op__oe__ok$9$next[0:0]$8427 $1\alu_op__oe__oe$8$next[0:0]$8426 $1\alu_op__rc__ok$7$next[0:0]$8429 $1\alu_op__rc__rc$6$next[0:0]$8430 $1\alu_op__imm_data__ok$5$next[0:0]$8418 $1\alu_op__imm_data__data$4$next[63:0]$8417 $1\alu_op__fn_unit$3$next[11:0]$8416 $1\alu_op__insn_type$2$next[6:0]$8421 } { \alu_op__insn$80 \alu_op__data_len$79 \alu_op__is_signed$78 \alu_op__is_32bit$77 \alu_op__output_carry$76 \alu_op__input_carry$75 \alu_op__write_cr0$74 \alu_op__invert_out$73 \alu_op__zero_a$72 \alu_op__invert_in$71 \alu_op__oe__ok$70 \alu_op__oe__oe$69 \alu_op__rc__ok$68 \alu_op__rc__rc$67 \alu_op__imm_data__ok$66 \alu_op__imm_data__data$65 \alu_op__fn_unit$64 \alu_op__insn_type$63 } + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'1- + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { $1\alu_op__insn$19$next[31:0]$8420 $1\alu_op__data_len$18$next[3:0]$8415 $1\alu_op__is_signed$17$next[0:0]$8425 $1\alu_op__is_32bit$16$next[0:0]$8424 $1\alu_op__output_carry$15$next[0:0]$8428 $1\alu_op__input_carry$14$next[1:0]$8419 $1\alu_op__write_cr0$13$next[0:0]$8431 $1\alu_op__invert_out$12$next[0:0]$8423 $1\alu_op__zero_a$11$next[0:0]$8432 $1\alu_op__invert_in$10$next[0:0]$8422 $1\alu_op__oe__ok$9$next[0:0]$8427 $1\alu_op__oe__oe$8$next[0:0]$8426 $1\alu_op__rc__ok$7$next[0:0]$8429 $1\alu_op__rc__rc$6$next[0:0]$8430 $1\alu_op__imm_data__ok$5$next[0:0]$8418 $1\alu_op__imm_data__data$4$next[63:0]$8417 $1\alu_op__fn_unit$3$next[11:0]$8416 $1\alu_op__insn_type$2$next[6:0]$8421 } { \alu_op__insn$80 \alu_op__data_len$79 \alu_op__is_signed$78 \alu_op__is_32bit$77 \alu_op__output_carry$76 \alu_op__input_carry$75 \alu_op__write_cr0$74 \alu_op__invert_out$73 \alu_op__zero_a$72 \alu_op__invert_in$71 \alu_op__oe__ok$70 \alu_op__oe__oe$69 \alu_op__rc__ok$68 \alu_op__rc__rc$67 \alu_op__imm_data__ok$66 \alu_op__imm_data__data$65 \alu_op__fn_unit$64 \alu_op__insn_type$63 } + case + assign $1\alu_op__data_len$18$next[3:0]$8415 \alu_op__data_len$18 + assign $1\alu_op__fn_unit$3$next[11:0]$8416 \alu_op__fn_unit$3 + assign $1\alu_op__imm_data__data$4$next[63:0]$8417 \alu_op__imm_data__data$4 + assign $1\alu_op__imm_data__ok$5$next[0:0]$8418 \alu_op__imm_data__ok$5 + assign $1\alu_op__input_carry$14$next[1:0]$8419 \alu_op__input_carry$14 + assign $1\alu_op__insn$19$next[31:0]$8420 \alu_op__insn$19 + assign $1\alu_op__insn_type$2$next[6:0]$8421 \alu_op__insn_type$2 + assign $1\alu_op__invert_in$10$next[0:0]$8422 \alu_op__invert_in$10 + assign $1\alu_op__invert_out$12$next[0:0]$8423 \alu_op__invert_out$12 + assign $1\alu_op__is_32bit$16$next[0:0]$8424 \alu_op__is_32bit$16 + assign $1\alu_op__is_signed$17$next[0:0]$8425 \alu_op__is_signed$17 + assign $1\alu_op__oe__oe$8$next[0:0]$8426 \alu_op__oe__oe$8 + assign $1\alu_op__oe__ok$9$next[0:0]$8427 \alu_op__oe__ok$9 + assign $1\alu_op__output_carry$15$next[0:0]$8428 \alu_op__output_carry$15 + assign $1\alu_op__rc__ok$7$next[0:0]$8429 \alu_op__rc__ok$7 + assign $1\alu_op__rc__rc$6$next[0:0]$8430 \alu_op__rc__rc$6 + assign $1\alu_op__write_cr0$13$next[0:0]$8431 \alu_op__write_cr0$13 + assign $1\alu_op__zero_a$11$next[0:0]$8432 \alu_op__zero_a$11 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $2\alu_op__imm_data__data$4$next[63:0]$8433 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\alu_op__imm_data__ok$5$next[0:0]$8434 1'0 + assign $2\alu_op__rc__rc$6$next[0:0]$8438 1'0 + assign $2\alu_op__rc__ok$7$next[0:0]$8437 1'0 + assign $2\alu_op__oe__oe$8$next[0:0]$8435 1'0 + assign $2\alu_op__oe__ok$9$next[0:0]$8436 1'0 + case + assign $2\alu_op__imm_data__data$4$next[63:0]$8433 $1\alu_op__imm_data__data$4$next[63:0]$8417 + assign $2\alu_op__imm_data__ok$5$next[0:0]$8434 $1\alu_op__imm_data__ok$5$next[0:0]$8418 + assign $2\alu_op__oe__oe$8$next[0:0]$8435 $1\alu_op__oe__oe$8$next[0:0]$8426 + assign $2\alu_op__oe__ok$9$next[0:0]$8436 $1\alu_op__oe__ok$9$next[0:0]$8427 + assign $2\alu_op__rc__ok$7$next[0:0]$8437 $1\alu_op__rc__ok$7$next[0:0]$8429 + assign $2\alu_op__rc__rc$6$next[0:0]$8438 $1\alu_op__rc__rc$6$next[0:0]$8430 + end + sync always + update \alu_op__data_len$18$next $0\alu_op__data_len$18$next[3:0]$8397 + update \alu_op__fn_unit$3$next $0\alu_op__fn_unit$3$next[11:0]$8398 + update \alu_op__imm_data__data$4$next $0\alu_op__imm_data__data$4$next[63:0]$8399 + update \alu_op__imm_data__ok$5$next $0\alu_op__imm_data__ok$5$next[0:0]$8400 + update \alu_op__input_carry$14$next $0\alu_op__input_carry$14$next[1:0]$8401 + update \alu_op__insn$19$next $0\alu_op__insn$19$next[31:0]$8402 + update \alu_op__insn_type$2$next $0\alu_op__insn_type$2$next[6:0]$8403 + update \alu_op__invert_in$10$next $0\alu_op__invert_in$10$next[0:0]$8404 + update \alu_op__invert_out$12$next $0\alu_op__invert_out$12$next[0:0]$8405 + update \alu_op__is_32bit$16$next $0\alu_op__is_32bit$16$next[0:0]$8406 + update \alu_op__is_signed$17$next $0\alu_op__is_signed$17$next[0:0]$8407 + update \alu_op__oe__oe$8$next $0\alu_op__oe__oe$8$next[0:0]$8408 + update \alu_op__oe__ok$9$next $0\alu_op__oe__ok$9$next[0:0]$8409 + update \alu_op__output_carry$15$next $0\alu_op__output_carry$15$next[0:0]$8410 + update \alu_op__rc__ok$7$next $0\alu_op__rc__ok$7$next[0:0]$8411 + update \alu_op__rc__rc$6$next $0\alu_op__rc__rc$6$next[0:0]$8412 + update \alu_op__write_cr0$13$next $0\alu_op__write_cr0$13$next[0:0]$8413 + update \alu_op__zero_a$11$next $0\alu_op__zero_a$11$next[0:0]$8414 + end + attribute \src "issuer_ls180.v:152788.3-152806.6" + process $proc$issuer_ls180.v:152788$8439 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\o$20$next[63:0]$8440 $1\o$20$next[63:0]$8442 + assign { } { } + assign $0\o_ok$21$next[0:0]$8441 $2\o_ok$21$next[0:0]$8444 + attribute \src "issuer_ls180.v:152789.5-152789.29" + switch \initial + attribute \src "issuer_ls180.v:152789.9-152789.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'-1 + assign { } { } + assign { } { } + assign { $1\o_ok$21$next[0:0]$8443 $1\o$20$next[63:0]$8442 } { \o_ok$82 \o$81 } + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'1- + assign { } { } + assign { } { } + assign { $1\o_ok$21$next[0:0]$8443 $1\o$20$next[63:0]$8442 } { \o_ok$82 \o$81 } + case + assign $1\o$20$next[63:0]$8442 \o$20 + assign $1\o_ok$21$next[0:0]$8443 \o_ok$21 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\o_ok$21$next[0:0]$8444 1'0 + case + assign $2\o_ok$21$next[0:0]$8444 $1\o_ok$21$next[0:0]$8443 + end + sync always + update \o$20$next $0\o$20$next[63:0]$8440 + update \o_ok$21$next $0\o_ok$21$next[0:0]$8441 + end + attribute \src "issuer_ls180.v:152807.3-152825.6" + process $proc$issuer_ls180.v:152807$8445 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\cr_a$22$next[3:0]$8446 $1\cr_a$22$next[3:0]$8448 + assign { } { } + assign $0\cr_a_ok$23$next[0:0]$8447 $2\cr_a_ok$23$next[0:0]$8450 + attribute \src "issuer_ls180.v:152808.5-152808.29" + switch \initial + attribute \src "issuer_ls180.v:152808.9-152808.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'-1 + assign { } { } + assign { } { } + assign { $1\cr_a_ok$23$next[0:0]$8449 $1\cr_a$22$next[3:0]$8448 } { \cr_a_ok$84 \cr_a$83 } + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'1- + assign { } { } + assign { } { } + assign { $1\cr_a_ok$23$next[0:0]$8449 $1\cr_a$22$next[3:0]$8448 } { \cr_a_ok$84 \cr_a$83 } + case + assign $1\cr_a$22$next[3:0]$8448 \cr_a$22 + assign $1\cr_a_ok$23$next[0:0]$8449 \cr_a_ok$23 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\cr_a_ok$23$next[0:0]$8450 1'0 + case + assign $2\cr_a_ok$23$next[0:0]$8450 $1\cr_a_ok$23$next[0:0]$8449 + end + sync always + update \cr_a$22$next $0\cr_a$22$next[3:0]$8446 + update \cr_a_ok$23$next $0\cr_a_ok$23$next[0:0]$8447 + end + attribute \src "issuer_ls180.v:152826.3-152844.6" + process $proc$issuer_ls180.v:152826$8451 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\xer_ca$24$next[1:0]$8452 $1\xer_ca$24$next[1:0]$8454 + assign { } { } + assign $0\xer_ca_ok$25$next[0:0]$8453 $2\xer_ca_ok$25$next[0:0]$8456 + attribute \src "issuer_ls180.v:152827.5-152827.29" + switch \initial + attribute \src "issuer_ls180.v:152827.9-152827.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'-1 + assign { } { } + assign { } { } + assign { $1\xer_ca_ok$25$next[0:0]$8455 $1\xer_ca$24$next[1:0]$8454 } { \xer_ca_ok$86 \xer_ca$85 } + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'1- + assign { } { } + assign { } { } + assign { $1\xer_ca_ok$25$next[0:0]$8455 $1\xer_ca$24$next[1:0]$8454 } { \xer_ca_ok$86 \xer_ca$85 } + case + assign $1\xer_ca$24$next[1:0]$8454 \xer_ca$24 + assign $1\xer_ca_ok$25$next[0:0]$8455 \xer_ca_ok$25 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\xer_ca_ok$25$next[0:0]$8456 1'0 + case + assign $2\xer_ca_ok$25$next[0:0]$8456 $1\xer_ca_ok$25$next[0:0]$8455 + end + sync always + update \xer_ca$24$next $0\xer_ca$24$next[1:0]$8452 + update \xer_ca_ok$25$next $0\xer_ca_ok$25$next[0:0]$8453 + end + attribute \src "issuer_ls180.v:152845.3-152863.6" + process $proc$issuer_ls180.v:152845$8457 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\xer_ov$26$next[1:0]$8458 $1\xer_ov$26$next[1:0]$8460 + assign { } { } + assign $0\xer_ov_ok$27$next[0:0]$8459 $2\xer_ov_ok$27$next[0:0]$8462 + attribute \src "issuer_ls180.v:152846.5-152846.29" + switch \initial + attribute \src "issuer_ls180.v:152846.9-152846.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'-1 + assign { } { } + assign { } { } + assign { $1\xer_ov_ok$27$next[0:0]$8461 $1\xer_ov$26$next[1:0]$8460 } { \xer_ov_ok$88 \xer_ov$87 } + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'1- + assign { } { } + assign { } { } + assign { $1\xer_ov_ok$27$next[0:0]$8461 $1\xer_ov$26$next[1:0]$8460 } { \xer_ov_ok$88 \xer_ov$87 } + case + assign $1\xer_ov$26$next[1:0]$8460 \xer_ov$26 + assign $1\xer_ov_ok$27$next[0:0]$8461 \xer_ov_ok$27 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\xer_ov_ok$27$next[0:0]$8462 1'0 + case + assign $2\xer_ov_ok$27$next[0:0]$8462 $1\xer_ov_ok$27$next[0:0]$8461 + end + sync always + update \xer_ov$26$next $0\xer_ov$26$next[1:0]$8458 + update \xer_ov_ok$27$next $0\xer_ov_ok$27$next[0:0]$8459 + end + attribute \src "issuer_ls180.v:152864.3-152882.6" + process $proc$issuer_ls180.v:152864$8463 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\xer_so$28$next[0:0]$8464 $1\xer_so$28$next[0:0]$8466 + assign { } { } + assign $0\xer_so_ok$29$next[0:0]$8465 $2\xer_so_ok$29$next[0:0]$8468 + attribute \src "issuer_ls180.v:152865.5-152865.29" + switch \initial + attribute \src "issuer_ls180.v:152865.9-152865.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'-1 + assign { } { } + assign { } { } + assign { $1\xer_so_ok$29$next[0:0]$8467 $1\xer_so$28$next[0:0]$8466 } { \xer_so_ok$90 \xer_so$89 } + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'1- + assign { } { } + assign { } { } + assign { $1\xer_so_ok$29$next[0:0]$8467 $1\xer_so$28$next[0:0]$8466 } { \xer_so_ok$90 \xer_so$89 } + case + assign $1\xer_so$28$next[0:0]$8466 \xer_so$28 + assign $1\xer_so_ok$29$next[0:0]$8467 \xer_so_ok$29 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\xer_so_ok$29$next[0:0]$8468 1'0 + case + assign $2\xer_so_ok$29$next[0:0]$8468 $1\xer_so_ok$29$next[0:0]$8467 + end + sync always + update \xer_so$28$next $0\xer_so$28$next[0:0]$8464 + update \xer_so_ok$29$next $0\xer_so_ok$29$next[0:0]$8465 + end + connect \$60 $and$issuer_ls180.v:152590$8329_Y + connect \p_ready_o \n_i_rdy_data + connect \n_valid_o \r_busy + connect { \xer_so_ok$90 \xer_so$89 } { \output_xer_so_ok \output_xer_so$54 } + connect { \xer_ov_ok$88 \xer_ov$87 } { \output_xer_ov_ok \output_xer_ov$53 } + connect { \xer_ca_ok$86 \xer_ca$85 } { \output_xer_ca_ok \output_xer_ca$52 } + connect { \cr_a_ok$84 \cr_a$83 } { \output_cr_a_ok \output_cr_a$51 } + connect { \o_ok$82 \o$81 } { \output_o_ok$50 \output_o$49 } + connect { \alu_op__insn$80 \alu_op__data_len$79 \alu_op__is_signed$78 \alu_op__is_32bit$77 \alu_op__output_carry$76 \alu_op__input_carry$75 \alu_op__write_cr0$74 \alu_op__invert_out$73 \alu_op__zero_a$72 \alu_op__invert_in$71 \alu_op__oe__ok$70 \alu_op__oe__oe$69 \alu_op__rc__ok$68 \alu_op__rc__rc$67 \alu_op__imm_data__ok$66 \alu_op__imm_data__data$65 \alu_op__fn_unit$64 \alu_op__insn_type$63 } { \output_alu_op__insn$48 \output_alu_op__data_len$47 \output_alu_op__is_signed$46 \output_alu_op__is_32bit$45 \output_alu_op__output_carry$44 \output_alu_op__input_carry$43 \output_alu_op__write_cr0$42 \output_alu_op__invert_out$41 \output_alu_op__zero_a$40 \output_alu_op__invert_in$39 \output_alu_op__oe__ok$38 \output_alu_op__oe__oe$37 \output_alu_op__rc__ok$36 \output_alu_op__rc__rc$35 \output_alu_op__imm_data__ok$34 \output_alu_op__imm_data__data$33 \output_alu_op__fn_unit$32 \output_alu_op__insn_type$31 } + connect \muxid$62 \output_muxid$30 + connect \p_valid_i_p_ready_o \$60 + connect \n_i_rdy_data \n_ready_i + connect \p_valid_i$59 \p_valid_i + connect { \xer_so_ok$58 \output_xer_so } { \xer_so_ok \xer_so } + connect { \xer_ov_ok$57 \output_xer_ov } { \xer_ov_ok \xer_ov } + connect { \xer_ca_ok$56 \output_xer_ca } { \xer_ca_ok \xer_ca } + connect { \cr_a_ok$55 \output_cr_a } { \cr_a_ok \cr_a } + connect { \output_o_ok \output_o } { \o_ok \o } + connect { \output_alu_op__insn \output_alu_op__data_len \output_alu_op__is_signed \output_alu_op__is_32bit \output_alu_op__output_carry \output_alu_op__input_carry \output_alu_op__write_cr0 \output_alu_op__invert_out \output_alu_op__zero_a \output_alu_op__invert_in \output_alu_op__oe__ok \output_alu_op__oe__oe \output_alu_op__rc__ok \output_alu_op__rc__rc \output_alu_op__imm_data__ok \output_alu_op__imm_data__data \output_alu_op__fn_unit \output_alu_op__insn_type } { \alu_op__insn \alu_op__data_len \alu_op__is_signed \alu_op__is_32bit \alu_op__output_carry \alu_op__input_carry \alu_op__write_cr0 \alu_op__invert_out \alu_op__zero_a \alu_op__invert_in \alu_op__oe__ok \alu_op__oe__oe \alu_op__rc__ok \alu_op__rc__rc \alu_op__imm_data__ok \alu_op__imm_data__data \alu_op__fn_unit \alu_op__insn_type } + connect \output_muxid \muxid +end +attribute \src "issuer_ls180.v:152906.1-153942.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.fus.shiftrot0.alu_shift_rot0.pipe2" +attribute \generator "nMigen" +module \pipe2$112 + attribute \src "issuer_ls180.v:153888.3-153906.6" + wire width 4 $0\cr_a$20$next[3:0]$8630 + attribute \src "issuer_ls180.v:153699.3-153700.33" + wire width 4 $0\cr_a$20[3:0]$8535 + attribute \src "issuer_ls180.v:152918.13-152918.29" + wire width 4 $0\cr_a$20[3:0]$8643 + attribute \src "issuer_ls180.v:153888.3-153906.6" + wire $0\cr_a_ok$21$next[0:0]$8631 + attribute \src "issuer_ls180.v:153701.3-153702.39" + wire $0\cr_a_ok$21[0:0]$8537 + attribute \src "issuer_ls180.v:152927.7-152927.26" + wire $0\cr_a_ok$21[0:0]$8645 + attribute \src "issuer_ls180.v:152907.7-152907.20" + wire $0\initial[0:0] + attribute \src "issuer_ls180.v:153816.3-153828.6" + wire width 2 $0\muxid$1$next[1:0]$8582 + attribute \src "issuer_ls180.v:153739.3-153740.33" + wire width 2 $0\muxid$1[1:0]$8575 + attribute \src "issuer_ls180.v:152938.13-152938.29" + wire width 2 $0\muxid$1[1:0]$8647 + attribute \src "issuer_ls180.v:153869.3-153887.6" + wire width 64 $0\o$18$next[63:0]$8624 + attribute \src "issuer_ls180.v:153703.3-153704.27" + wire width 64 $0\o$18[63:0]$8539 + attribute \src "issuer_ls180.v:152953.14-152953.43" + wire width 64 $0\o$18[63:0]$8649 + attribute \src "issuer_ls180.v:153869.3-153887.6" + wire $0\o_ok$19$next[0:0]$8625 + attribute \src "issuer_ls180.v:153705.3-153706.33" + wire $0\o_ok$19[0:0]$8541 + attribute \src "issuer_ls180.v:152962.7-152962.23" + wire $0\o_ok$19[0:0]$8651 + attribute \src "issuer_ls180.v:153798.3-153815.6" + wire $0\r_busy$next[0:0]$8578 + attribute \src "issuer_ls180.v:153741.3-153742.29" + wire $0\r_busy[0:0] + attribute \src "issuer_ls180.v:153829.3-153868.6" + wire width 12 $0\sr_op__fn_unit$3$next[11:0]$8585 + attribute \src "issuer_ls180.v:153709.3-153710.51" + wire width 12 $0\sr_op__fn_unit$3[11:0]$8545 + attribute \src "issuer_ls180.v:153281.14-153281.42" + wire width 12 $0\sr_op__fn_unit$3[11:0]$8654 + attribute \src "issuer_ls180.v:153829.3-153868.6" + wire width 64 $0\sr_op__imm_data__data$4$next[63:0]$8586 + attribute \src "issuer_ls180.v:153711.3-153712.65" + wire width 64 $0\sr_op__imm_data__data$4[63:0]$8547 + attribute \src "issuer_ls180.v:153303.14-153303.62" + wire width 64 $0\sr_op__imm_data__data$4[63:0]$8656 + attribute \src "issuer_ls180.v:153829.3-153868.6" + wire $0\sr_op__imm_data__ok$5$next[0:0]$8587 + attribute \src "issuer_ls180.v:153713.3-153714.61" + wire $0\sr_op__imm_data__ok$5[0:0]$8549 + attribute \src "issuer_ls180.v:153312.7-153312.37" + wire $0\sr_op__imm_data__ok$5[0:0]$8658 + attribute \src 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"OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \output_sr_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \output_sr_op__insn_type$25 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_sr_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_sr_op__is_32bit$38 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_sr_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_sr_op__is_signed$39 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_sr_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_sr_op__oe__oe$31 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_sr_op__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_sr_op__oe__ok$32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_sr_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_sr_op__output_carry$35 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_sr_op__output_cr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_sr_op__output_cr$37 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_sr_op__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_sr_op__rc__ok$30 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_sr_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_sr_op__rc__rc$29 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_sr_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_sr_op__write_cr0$33 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 2 \output_xer_ca + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 2 \output_xer_ca$44 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \output_xer_ca_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \output_xer_so + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" + wire output 3 \p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" + wire input 2 \p_valid_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:621" + wire \p_valid_i$48 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" + wire \p_valid_i_p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615" + wire \r_busy + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615" + wire \r_busy$next + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 input 6 \sr_op__fn_unit + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 output 33 \sr_op__fn_unit$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 \sr_op__fn_unit$3$next + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 \sr_op__fn_unit$53 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 input 7 \sr_op__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 output 34 \sr_op__imm_data__data$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \sr_op__imm_data__data$4$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \sr_op__imm_data__data$54 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 8 \sr_op__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 35 \sr_op__imm_data__ok$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \sr_op__imm_data__ok$5$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \sr_op__imm_data__ok$55 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 input 14 \sr_op__input_carry + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 output 41 \sr_op__input_carry$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \sr_op__input_carry$11$next + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \sr_op__input_carry$61 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 16 \sr_op__input_cr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 43 \sr_op__input_cr$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \sr_op__input_cr$13$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \sr_op__input_cr$63 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 20 \sr_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 output 47 \sr_op__insn$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \sr_op__insn$17$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \sr_op__insn$67 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 input 5 \sr_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 output 32 \sr_op__insn_type$2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \sr_op__insn_type$2$next + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \sr_op__insn_type$52 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 18 \sr_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 45 \sr_op__is_32bit$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \sr_op__is_32bit$15$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \sr_op__is_32bit$65 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 19 \sr_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 46 \sr_op__is_signed$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \sr_op__is_signed$16$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \sr_op__is_signed$66 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 11 \sr_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \sr_op__oe__oe$58 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 38 \sr_op__oe__oe$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \sr_op__oe__oe$8$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 12 \sr_op__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \sr_op__oe__ok$59 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 39 \sr_op__oe__ok$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \sr_op__oe__ok$9$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 15 \sr_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 42 \sr_op__output_carry$12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \sr_op__output_carry$12$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \sr_op__output_carry$62 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 17 \sr_op__output_cr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 44 \sr_op__output_cr$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \sr_op__output_cr$14$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \sr_op__output_cr$64 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 10 \sr_op__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \sr_op__rc__ok$57 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 37 \sr_op__rc__ok$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \sr_op__rc__ok$7$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 9 \sr_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \sr_op__rc__rc$56 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 36 \sr_op__rc__rc$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \sr_op__rc__rc$6$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 13 \sr_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 40 \sr_op__write_cr0$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \sr_op__write_cr0$10$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \sr_op__write_cr0$60 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 2 input 27 \xer_ca + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 2 output 52 \xer_ca$22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 2 \xer_ca$22$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 2 \xer_ca$72 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire input 28 \xer_ca_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 53 \xer_ca_ok$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \xer_ca_ok$23$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \xer_ca_ok$47 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \xer_ca_ok$73 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire input 25 \xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire input 26 \xer_so_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \xer_so_ok$46 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" + cell $and $and$issuer_ls180.v:153694$8529 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \p_valid_i$48 + connect \B \p_ready_o + connect \Y $and$issuer_ls180.v:153694$8529_Y + end + attribute \module_not_derived 1 + attribute \src "issuer_ls180.v:153743.11-153746.4" + cell \n$114 \n + connect \n_ready_i \n_ready_i + connect \n_valid_o \n_valid_o + end + attribute \module_not_derived 1 + attribute \src "issuer_ls180.v:153747.16-153793.4" + cell \output$115 \output + connect \cr_a \output_cr_a + connect \cr_a$20 \output_cr_a$43 + connect \cr_a_ok \output_cr_a_ok + connect \muxid \output_muxid + connect \muxid$1 \output_muxid$24 + connect \o \output_o + connect \o$18 \output_o$41 + connect \o_ok \output_o_ok + connect \o_ok$19 \output_o_ok$42 + connect \sr_op__fn_unit \output_sr_op__fn_unit + connect \sr_op__fn_unit$3 \output_sr_op__fn_unit$26 + connect \sr_op__imm_data__data \output_sr_op__imm_data__data + connect \sr_op__imm_data__data$4 \output_sr_op__imm_data__data$27 + connect \sr_op__imm_data__ok \output_sr_op__imm_data__ok + connect \sr_op__imm_data__ok$5 \output_sr_op__imm_data__ok$28 + connect \sr_op__input_carry \output_sr_op__input_carry + connect \sr_op__input_carry$11 \output_sr_op__input_carry$34 + connect \sr_op__input_cr \output_sr_op__input_cr + connect \sr_op__input_cr$13 \output_sr_op__input_cr$36 + connect \sr_op__insn \output_sr_op__insn + connect \sr_op__insn$17 \output_sr_op__insn$40 + connect \sr_op__insn_type \output_sr_op__insn_type + connect \sr_op__insn_type$2 \output_sr_op__insn_type$25 + connect \sr_op__is_32bit \output_sr_op__is_32bit + connect \sr_op__is_32bit$15 \output_sr_op__is_32bit$38 + connect \sr_op__is_signed \output_sr_op__is_signed + connect \sr_op__is_signed$16 \output_sr_op__is_signed$39 + connect \sr_op__oe__oe \output_sr_op__oe__oe + connect \sr_op__oe__oe$8 \output_sr_op__oe__oe$31 + connect \sr_op__oe__ok \output_sr_op__oe__ok + connect \sr_op__oe__ok$9 \output_sr_op__oe__ok$32 + connect \sr_op__output_carry \output_sr_op__output_carry + connect \sr_op__output_carry$12 \output_sr_op__output_carry$35 + connect \sr_op__output_cr \output_sr_op__output_cr + connect \sr_op__output_cr$14 \output_sr_op__output_cr$37 + connect \sr_op__rc__ok \output_sr_op__rc__ok + connect \sr_op__rc__ok$7 \output_sr_op__rc__ok$30 + connect \sr_op__rc__rc \output_sr_op__rc__rc + connect \sr_op__rc__rc$6 \output_sr_op__rc__rc$29 + connect \sr_op__write_cr0 \output_sr_op__write_cr0 + connect \sr_op__write_cr0$10 \output_sr_op__write_cr0$33 + connect \xer_ca \output_xer_ca + connect \xer_ca$21 \output_xer_ca$44 + connect \xer_ca_ok \output_xer_ca_ok + connect \xer_so \output_xer_so + end + attribute \module_not_derived 1 + attribute \src "issuer_ls180.v:153794.11-153797.4" + cell \p$113 \p + connect \p_ready_o \p_ready_o + connect \p_valid_i \p_valid_i + end + attribute \src "issuer_ls180.v:152907.7-152907.20" + process $proc$issuer_ls180.v:152907$8641 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "issuer_ls180.v:152918.13-152918.29" + process $proc$issuer_ls180.v:152918$8642 + assign { } { } + assign $0\cr_a$20[3:0]$8643 4'0000 + sync always + sync init + update \cr_a$20 $0\cr_a$20[3:0]$8643 + end + attribute \src "issuer_ls180.v:152927.7-152927.26" + process $proc$issuer_ls180.v:152927$8644 + assign { } { } + assign $0\cr_a_ok$21[0:0]$8645 1'0 + sync always + sync init + update \cr_a_ok$21 $0\cr_a_ok$21[0:0]$8645 + end + attribute \src "issuer_ls180.v:152938.13-152938.29" + process $proc$issuer_ls180.v:152938$8646 + assign { } { } + assign $0\muxid$1[1:0]$8647 2'00 + sync always + sync init + update \muxid$1 $0\muxid$1[1:0]$8647 + end + attribute \src "issuer_ls180.v:152953.14-152953.43" + process $proc$issuer_ls180.v:152953$8648 + assign { } { } + assign $0\o$18[63:0]$8649 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \o$18 $0\o$18[63:0]$8649 + end + attribute \src "issuer_ls180.v:152962.7-152962.23" + process $proc$issuer_ls180.v:152962$8650 + assign { } { } + assign $0\o_ok$19[0:0]$8651 1'0 + sync always + sync init + update \o_ok$19 $0\o_ok$19[0:0]$8651 + end + attribute \src "issuer_ls180.v:153248.7-153248.20" + process $proc$issuer_ls180.v:153248$8652 + assign { } { } + assign $1\r_busy[0:0] 1'0 + sync always + sync init + update \r_busy $1\r_busy[0:0] + end + attribute \src "issuer_ls180.v:153281.14-153281.42" + process $proc$issuer_ls180.v:153281$8653 + assign { } { } + assign $0\sr_op__fn_unit$3[11:0]$8654 12'000000000000 + sync always + sync init + update \sr_op__fn_unit$3 $0\sr_op__fn_unit$3[11:0]$8654 + end + attribute \src "issuer_ls180.v:153303.14-153303.62" + process $proc$issuer_ls180.v:153303$8655 + assign { } { } + assign $0\sr_op__imm_data__data$4[63:0]$8656 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \sr_op__imm_data__data$4 $0\sr_op__imm_data__data$4[63:0]$8656 + end + attribute \src "issuer_ls180.v:153312.7-153312.37" + process $proc$issuer_ls180.v:153312$8657 + assign { } { } + assign $0\sr_op__imm_data__ok$5[0:0]$8658 1'0 + sync always + sync init + update \sr_op__imm_data__ok$5 $0\sr_op__imm_data__ok$5[0:0]$8658 + end + attribute \src "issuer_ls180.v:153329.13-153329.43" + process $proc$issuer_ls180.v:153329$8659 + assign { } { } + assign $0\sr_op__input_carry$11[1:0]$8660 2'00 + sync always + sync init + update \sr_op__input_carry$11 $0\sr_op__input_carry$11[1:0]$8660 + end + attribute \src "issuer_ls180.v:153342.7-153342.34" + process $proc$issuer_ls180.v:153342$8661 + assign { } { } + assign $0\sr_op__input_cr$13[0:0]$8662 1'0 + sync always + sync init + update \sr_op__input_cr$13 $0\sr_op__input_cr$13[0:0]$8662 + end + attribute \src "issuer_ls180.v:153351.14-153351.38" + process $proc$issuer_ls180.v:153351$8663 + assign { } { } + assign $0\sr_op__insn$17[31:0]$8664 0 + sync always + sync init + update \sr_op__insn$17 $0\sr_op__insn$17[31:0]$8664 + end + attribute \src "issuer_ls180.v:153508.13-153508.41" + process $proc$issuer_ls180.v:153508$8665 + assign { } { } + assign $0\sr_op__insn_type$2[6:0]$8666 7'0000000 + sync always + sync init + update \sr_op__insn_type$2 $0\sr_op__insn_type$2[6:0]$8666 + end + attribute \src "issuer_ls180.v:153591.7-153591.34" + process $proc$issuer_ls180.v:153591$8667 + assign { } { } + assign $0\sr_op__is_32bit$15[0:0]$8668 1'0 + sync always + sync init + update \sr_op__is_32bit$15 $0\sr_op__is_32bit$15[0:0]$8668 + end + attribute \src "issuer_ls180.v:153600.7-153600.35" + process $proc$issuer_ls180.v:153600$8669 + assign { } { } + assign $0\sr_op__is_signed$16[0:0]$8670 1'0 + sync always + sync init + update \sr_op__is_signed$16 $0\sr_op__is_signed$16[0:0]$8670 + end + attribute \src "issuer_ls180.v:153611.7-153611.31" + process $proc$issuer_ls180.v:153611$8671 + assign { } { } + assign $0\sr_op__oe__oe$8[0:0]$8672 1'0 + sync always + sync init + update \sr_op__oe__oe$8 $0\sr_op__oe__oe$8[0:0]$8672 + end + attribute \src "issuer_ls180.v:153620.7-153620.31" + process $proc$issuer_ls180.v:153620$8673 + assign { } { } + assign $0\sr_op__oe__ok$9[0:0]$8674 1'0 + sync always + sync init + update \sr_op__oe__ok$9 $0\sr_op__oe__ok$9[0:0]$8674 + end + attribute \src "issuer_ls180.v:153627.7-153627.38" + process $proc$issuer_ls180.v:153627$8675 + assign { } { } + assign $0\sr_op__output_carry$12[0:0]$8676 1'0 + sync always + sync init + update \sr_op__output_carry$12 $0\sr_op__output_carry$12[0:0]$8676 + end + attribute \src "issuer_ls180.v:153636.7-153636.35" + process $proc$issuer_ls180.v:153636$8677 + assign { } { } + assign $0\sr_op__output_cr$14[0:0]$8678 1'0 + sync always + sync init + update \sr_op__output_cr$14 $0\sr_op__output_cr$14[0:0]$8678 + end + attribute \src "issuer_ls180.v:153647.7-153647.31" + process $proc$issuer_ls180.v:153647$8679 + assign { } { } + assign $0\sr_op__rc__ok$7[0:0]$8680 1'0 + sync always + sync init + update \sr_op__rc__ok$7 $0\sr_op__rc__ok$7[0:0]$8680 + end + attribute \src "issuer_ls180.v:153656.7-153656.31" + process $proc$issuer_ls180.v:153656$8681 + assign { } { } + assign $0\sr_op__rc__rc$6[0:0]$8682 1'0 + sync always + sync init + update \sr_op__rc__rc$6 $0\sr_op__rc__rc$6[0:0]$8682 + end + attribute \src "issuer_ls180.v:153663.7-153663.35" + process $proc$issuer_ls180.v:153663$8683 + assign { } { } + assign $0\sr_op__write_cr0$10[0:0]$8684 1'0 + sync always + sync init + update \sr_op__write_cr0$10 $0\sr_op__write_cr0$10[0:0]$8684 + end + attribute \src "issuer_ls180.v:153672.13-153672.31" + process $proc$issuer_ls180.v:153672$8685 + assign { } { } + assign $0\xer_ca$22[1:0]$8686 2'00 + sync always + sync init + update \xer_ca$22 $0\xer_ca$22[1:0]$8686 + end + attribute \src "issuer_ls180.v:153681.7-153681.28" + process $proc$issuer_ls180.v:153681$8687 + assign { } { } + assign $0\xer_ca_ok$23[0:0]$8688 1'0 + sync always + sync init + update \xer_ca_ok$23 $0\xer_ca_ok$23[0:0]$8688 + end + attribute \src "issuer_ls180.v:153695.3-153696.37" + process $proc$issuer_ls180.v:153695$8530 + assign { } { } + assign $0\xer_ca$22[1:0]$8531 \xer_ca$22$next + sync posedge \coresync_clk + update \xer_ca$22 $0\xer_ca$22[1:0]$8531 + end + attribute \src "issuer_ls180.v:153697.3-153698.43" + process $proc$issuer_ls180.v:153697$8532 + assign { } { } + assign $0\xer_ca_ok$23[0:0]$8533 \xer_ca_ok$23$next + sync posedge \coresync_clk + update \xer_ca_ok$23 $0\xer_ca_ok$23[0:0]$8533 + end + attribute \src "issuer_ls180.v:153699.3-153700.33" + process $proc$issuer_ls180.v:153699$8534 + assign { } { } + assign $0\cr_a$20[3:0]$8535 \cr_a$20$next + sync posedge \coresync_clk + update \cr_a$20 $0\cr_a$20[3:0]$8535 + end + attribute \src "issuer_ls180.v:153701.3-153702.39" + process $proc$issuer_ls180.v:153701$8536 + assign { } { } + assign $0\cr_a_ok$21[0:0]$8537 \cr_a_ok$21$next + sync posedge \coresync_clk + update \cr_a_ok$21 $0\cr_a_ok$21[0:0]$8537 + end + attribute \src "issuer_ls180.v:153703.3-153704.27" + process $proc$issuer_ls180.v:153703$8538 + assign { } { } + assign $0\o$18[63:0]$8539 \o$18$next + sync posedge \coresync_clk + update \o$18 $0\o$18[63:0]$8539 + end + attribute \src "issuer_ls180.v:153705.3-153706.33" + process $proc$issuer_ls180.v:153705$8540 + assign { } { } + assign $0\o_ok$19[0:0]$8541 \o_ok$19$next + sync posedge \coresync_clk + update \o_ok$19 $0\o_ok$19[0:0]$8541 + end + attribute \src "issuer_ls180.v:153707.3-153708.55" + process $proc$issuer_ls180.v:153707$8542 + assign { } { } + assign $0\sr_op__insn_type$2[6:0]$8543 \sr_op__insn_type$2$next + sync posedge \coresync_clk + update \sr_op__insn_type$2 $0\sr_op__insn_type$2[6:0]$8543 + end + attribute \src "issuer_ls180.v:153709.3-153710.51" + process $proc$issuer_ls180.v:153709$8544 + assign { } { } + assign $0\sr_op__fn_unit$3[11:0]$8545 \sr_op__fn_unit$3$next + sync posedge \coresync_clk + update \sr_op__fn_unit$3 $0\sr_op__fn_unit$3[11:0]$8545 + end + attribute \src "issuer_ls180.v:153711.3-153712.65" + process $proc$issuer_ls180.v:153711$8546 + assign { } { } + assign $0\sr_op__imm_data__data$4[63:0]$8547 \sr_op__imm_data__data$4$next + sync posedge \coresync_clk + update \sr_op__imm_data__data$4 $0\sr_op__imm_data__data$4[63:0]$8547 + end + attribute \src "issuer_ls180.v:153713.3-153714.61" + process $proc$issuer_ls180.v:153713$8548 + assign { } { } + assign $0\sr_op__imm_data__ok$5[0:0]$8549 \sr_op__imm_data__ok$5$next + sync posedge \coresync_clk + update \sr_op__imm_data__ok$5 $0\sr_op__imm_data__ok$5[0:0]$8549 + end + attribute \src "issuer_ls180.v:153715.3-153716.49" + process $proc$issuer_ls180.v:153715$8550 + assign { } { } + assign $0\sr_op__rc__rc$6[0:0]$8551 \sr_op__rc__rc$6$next + sync posedge \coresync_clk + update \sr_op__rc__rc$6 $0\sr_op__rc__rc$6[0:0]$8551 + end + attribute \src "issuer_ls180.v:153717.3-153718.49" + process $proc$issuer_ls180.v:153717$8552 + assign { } { } + assign $0\sr_op__rc__ok$7[0:0]$8553 \sr_op__rc__ok$7$next + sync posedge \coresync_clk + update \sr_op__rc__ok$7 $0\sr_op__rc__ok$7[0:0]$8553 + end + attribute \src "issuer_ls180.v:153719.3-153720.49" + process $proc$issuer_ls180.v:153719$8554 + assign { } { } + assign $0\sr_op__oe__oe$8[0:0]$8555 \sr_op__oe__oe$8$next + sync posedge \coresync_clk + update \sr_op__oe__oe$8 $0\sr_op__oe__oe$8[0:0]$8555 + end + attribute \src "issuer_ls180.v:153721.3-153722.49" + process $proc$issuer_ls180.v:153721$8556 + assign { } { } + assign $0\sr_op__oe__ok$9[0:0]$8557 \sr_op__oe__ok$9$next + sync posedge \coresync_clk + update \sr_op__oe__ok$9 $0\sr_op__oe__ok$9[0:0]$8557 + end + attribute \src "issuer_ls180.v:153723.3-153724.57" + process $proc$issuer_ls180.v:153723$8558 + assign { } { } + assign $0\sr_op__write_cr0$10[0:0]$8559 \sr_op__write_cr0$10$next + sync posedge \coresync_clk + update \sr_op__write_cr0$10 $0\sr_op__write_cr0$10[0:0]$8559 + end + attribute \src "issuer_ls180.v:153725.3-153726.61" + process $proc$issuer_ls180.v:153725$8560 + assign { } { } + assign $0\sr_op__input_carry$11[1:0]$8561 \sr_op__input_carry$11$next + sync posedge \coresync_clk + update \sr_op__input_carry$11 $0\sr_op__input_carry$11[1:0]$8561 + end + attribute \src "issuer_ls180.v:153727.3-153728.63" + process $proc$issuer_ls180.v:153727$8562 + assign { } { } + assign $0\sr_op__output_carry$12[0:0]$8563 \sr_op__output_carry$12$next + sync posedge \coresync_clk + update \sr_op__output_carry$12 $0\sr_op__output_carry$12[0:0]$8563 + end + attribute \src "issuer_ls180.v:153729.3-153730.55" + process $proc$issuer_ls180.v:153729$8564 + assign { } { } + assign $0\sr_op__input_cr$13[0:0]$8565 \sr_op__input_cr$13$next + sync posedge \coresync_clk + update \sr_op__input_cr$13 $0\sr_op__input_cr$13[0:0]$8565 + end + attribute \src "issuer_ls180.v:153731.3-153732.57" + process $proc$issuer_ls180.v:153731$8566 + assign { } { } + assign $0\sr_op__output_cr$14[0:0]$8567 \sr_op__output_cr$14$next + sync posedge \coresync_clk + update \sr_op__output_cr$14 $0\sr_op__output_cr$14[0:0]$8567 + end + attribute \src "issuer_ls180.v:153733.3-153734.55" + process $proc$issuer_ls180.v:153733$8568 + assign { } { } + assign $0\sr_op__is_32bit$15[0:0]$8569 \sr_op__is_32bit$15$next + sync posedge \coresync_clk + update \sr_op__is_32bit$15 $0\sr_op__is_32bit$15[0:0]$8569 + end + attribute \src "issuer_ls180.v:153735.3-153736.57" + process $proc$issuer_ls180.v:153735$8570 + assign { } { } + assign $0\sr_op__is_signed$16[0:0]$8571 \sr_op__is_signed$16$next + sync posedge \coresync_clk + update \sr_op__is_signed$16 $0\sr_op__is_signed$16[0:0]$8571 + end + attribute \src "issuer_ls180.v:153737.3-153738.47" + process $proc$issuer_ls180.v:153737$8572 + assign { } { } + assign $0\sr_op__insn$17[31:0]$8573 \sr_op__insn$17$next + sync posedge \coresync_clk + update \sr_op__insn$17 $0\sr_op__insn$17[31:0]$8573 + end + attribute \src "issuer_ls180.v:153739.3-153740.33" + process $proc$issuer_ls180.v:153739$8574 + assign { } { } + assign $0\muxid$1[1:0]$8575 \muxid$1$next + sync posedge \coresync_clk + update \muxid$1 $0\muxid$1[1:0]$8575 + end + attribute \src "issuer_ls180.v:153741.3-153742.29" + process $proc$issuer_ls180.v:153741$8576 + assign { } { } + assign $0\r_busy[0:0] \r_busy$next + sync posedge \coresync_clk + update \r_busy $0\r_busy[0:0] + end + attribute \src "issuer_ls180.v:153798.3-153815.6" + process $proc$issuer_ls180.v:153798$8577 + assign { } { } + assign { } { } + assign { } { } + assign $0\r_busy$next[0:0]$8578 $2\r_busy$next[0:0]$8580 + attribute \src "issuer_ls180.v:153799.5-153799.29" + switch \initial + attribute \src "issuer_ls180.v:153799.9-153799.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\r_busy$next[0:0]$8579 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\r_busy$next[0:0]$8579 1'0 + case + assign $1\r_busy$next[0:0]$8579 \r_busy + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\r_busy$next[0:0]$8580 1'0 + case + assign $2\r_busy$next[0:0]$8580 $1\r_busy$next[0:0]$8579 + end + sync always + update \r_busy$next $0\r_busy$next[0:0]$8578 + end + attribute \src "issuer_ls180.v:153816.3-153828.6" + process $proc$issuer_ls180.v:153816$8581 + assign { } { } + assign { } { } + assign $0\muxid$1$next[1:0]$8582 $1\muxid$1$next[1:0]$8583 + attribute \src "issuer_ls180.v:153817.5-153817.29" + switch \initial + attribute \src "issuer_ls180.v:153817.9-153817.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\muxid$1$next[1:0]$8583 \muxid$51 + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\muxid$1$next[1:0]$8583 \muxid$51 + case + assign $1\muxid$1$next[1:0]$8583 \muxid$1 + end + sync always + update \muxid$1$next $0\muxid$1$next[1:0]$8582 + end + attribute \src "issuer_ls180.v:153829.3-153868.6" + process $proc$issuer_ls180.v:153829$8584 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\sr_op__fn_unit$3$next[11:0]$8585 $1\sr_op__fn_unit$3$next[11:0]$8601 + assign { } { } + assign { } { } + assign $0\sr_op__input_carry$11$next[1:0]$8588 $1\sr_op__input_carry$11$next[1:0]$8604 + assign $0\sr_op__input_cr$13$next[0:0]$8589 $1\sr_op__input_cr$13$next[0:0]$8605 + assign $0\sr_op__insn$17$next[31:0]$8590 $1\sr_op__insn$17$next[31:0]$8606 + assign $0\sr_op__insn_type$2$next[6:0]$8591 $1\sr_op__insn_type$2$next[6:0]$8607 + assign $0\sr_op__is_32bit$15$next[0:0]$8592 $1\sr_op__is_32bit$15$next[0:0]$8608 + assign $0\sr_op__is_signed$16$next[0:0]$8593 $1\sr_op__is_signed$16$next[0:0]$8609 + assign { } { } + assign { } { } + assign $0\sr_op__output_carry$12$next[0:0]$8596 $1\sr_op__output_carry$12$next[0:0]$8612 + assign $0\sr_op__output_cr$14$next[0:0]$8597 $1\sr_op__output_cr$14$next[0:0]$8613 + assign { } { } + assign { } { } + assign $0\sr_op__write_cr0$10$next[0:0]$8600 $1\sr_op__write_cr0$10$next[0:0]$8616 + assign $0\sr_op__imm_data__data$4$next[63:0]$8586 $2\sr_op__imm_data__data$4$next[63:0]$8617 + assign $0\sr_op__imm_data__ok$5$next[0:0]$8587 $2\sr_op__imm_data__ok$5$next[0:0]$8618 + assign $0\sr_op__oe__oe$8$next[0:0]$8594 $2\sr_op__oe__oe$8$next[0:0]$8619 + assign $0\sr_op__oe__ok$9$next[0:0]$8595 $2\sr_op__oe__ok$9$next[0:0]$8620 + assign $0\sr_op__rc__ok$7$next[0:0]$8598 $2\sr_op__rc__ok$7$next[0:0]$8621 + assign $0\sr_op__rc__rc$6$next[0:0]$8599 $2\sr_op__rc__rc$6$next[0:0]$8622 + attribute \src "issuer_ls180.v:153830.5-153830.29" + switch \initial + attribute \src "issuer_ls180.v:153830.9-153830.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'-1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { $1\sr_op__insn$17$next[31:0]$8606 $1\sr_op__is_signed$16$next[0:0]$8609 $1\sr_op__is_32bit$15$next[0:0]$8608 $1\sr_op__output_cr$14$next[0:0]$8613 $1\sr_op__input_cr$13$next[0:0]$8605 $1\sr_op__output_carry$12$next[0:0]$8612 $1\sr_op__input_carry$11$next[1:0]$8604 $1\sr_op__write_cr0$10$next[0:0]$8616 $1\sr_op__oe__ok$9$next[0:0]$8611 $1\sr_op__oe__oe$8$next[0:0]$8610 $1\sr_op__rc__ok$7$next[0:0]$8614 $1\sr_op__rc__rc$6$next[0:0]$8615 $1\sr_op__imm_data__ok$5$next[0:0]$8603 $1\sr_op__imm_data__data$4$next[63:0]$8602 $1\sr_op__fn_unit$3$next[11:0]$8601 $1\sr_op__insn_type$2$next[6:0]$8607 } { \sr_op__insn$67 \sr_op__is_signed$66 \sr_op__is_32bit$65 \sr_op__output_cr$64 \sr_op__input_cr$63 \sr_op__output_carry$62 \sr_op__input_carry$61 \sr_op__write_cr0$60 \sr_op__oe__ok$59 \sr_op__oe__oe$58 \sr_op__rc__ok$57 \sr_op__rc__rc$56 \sr_op__imm_data__ok$55 \sr_op__imm_data__data$54 \sr_op__fn_unit$53 \sr_op__insn_type$52 } + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'1- + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { $1\sr_op__insn$17$next[31:0]$8606 $1\sr_op__is_signed$16$next[0:0]$8609 $1\sr_op__is_32bit$15$next[0:0]$8608 $1\sr_op__output_cr$14$next[0:0]$8613 $1\sr_op__input_cr$13$next[0:0]$8605 $1\sr_op__output_carry$12$next[0:0]$8612 $1\sr_op__input_carry$11$next[1:0]$8604 $1\sr_op__write_cr0$10$next[0:0]$8616 $1\sr_op__oe__ok$9$next[0:0]$8611 $1\sr_op__oe__oe$8$next[0:0]$8610 $1\sr_op__rc__ok$7$next[0:0]$8614 $1\sr_op__rc__rc$6$next[0:0]$8615 $1\sr_op__imm_data__ok$5$next[0:0]$8603 $1\sr_op__imm_data__data$4$next[63:0]$8602 $1\sr_op__fn_unit$3$next[11:0]$8601 $1\sr_op__insn_type$2$next[6:0]$8607 } { \sr_op__insn$67 \sr_op__is_signed$66 \sr_op__is_32bit$65 \sr_op__output_cr$64 \sr_op__input_cr$63 \sr_op__output_carry$62 \sr_op__input_carry$61 \sr_op__write_cr0$60 \sr_op__oe__ok$59 \sr_op__oe__oe$58 \sr_op__rc__ok$57 \sr_op__rc__rc$56 \sr_op__imm_data__ok$55 \sr_op__imm_data__data$54 \sr_op__fn_unit$53 \sr_op__insn_type$52 } + case + assign $1\sr_op__fn_unit$3$next[11:0]$8601 \sr_op__fn_unit$3 + assign $1\sr_op__imm_data__data$4$next[63:0]$8602 \sr_op__imm_data__data$4 + assign $1\sr_op__imm_data__ok$5$next[0:0]$8603 \sr_op__imm_data__ok$5 + assign $1\sr_op__input_carry$11$next[1:0]$8604 \sr_op__input_carry$11 + assign $1\sr_op__input_cr$13$next[0:0]$8605 \sr_op__input_cr$13 + assign $1\sr_op__insn$17$next[31:0]$8606 \sr_op__insn$17 + assign $1\sr_op__insn_type$2$next[6:0]$8607 \sr_op__insn_type$2 + assign $1\sr_op__is_32bit$15$next[0:0]$8608 \sr_op__is_32bit$15 + assign $1\sr_op__is_signed$16$next[0:0]$8609 \sr_op__is_signed$16 + assign $1\sr_op__oe__oe$8$next[0:0]$8610 \sr_op__oe__oe$8 + assign $1\sr_op__oe__ok$9$next[0:0]$8611 \sr_op__oe__ok$9 + assign $1\sr_op__output_carry$12$next[0:0]$8612 \sr_op__output_carry$12 + assign $1\sr_op__output_cr$14$next[0:0]$8613 \sr_op__output_cr$14 + assign $1\sr_op__rc__ok$7$next[0:0]$8614 \sr_op__rc__ok$7 + assign $1\sr_op__rc__rc$6$next[0:0]$8615 \sr_op__rc__rc$6 + assign $1\sr_op__write_cr0$10$next[0:0]$8616 \sr_op__write_cr0$10 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $2\sr_op__imm_data__data$4$next[63:0]$8617 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\sr_op__imm_data__ok$5$next[0:0]$8618 1'0 + assign $2\sr_op__rc__rc$6$next[0:0]$8622 1'0 + assign $2\sr_op__rc__ok$7$next[0:0]$8621 1'0 + assign $2\sr_op__oe__oe$8$next[0:0]$8619 1'0 + assign $2\sr_op__oe__ok$9$next[0:0]$8620 1'0 + case + assign $2\sr_op__imm_data__data$4$next[63:0]$8617 $1\sr_op__imm_data__data$4$next[63:0]$8602 + assign $2\sr_op__imm_data__ok$5$next[0:0]$8618 $1\sr_op__imm_data__ok$5$next[0:0]$8603 + assign $2\sr_op__oe__oe$8$next[0:0]$8619 $1\sr_op__oe__oe$8$next[0:0]$8610 + assign $2\sr_op__oe__ok$9$next[0:0]$8620 $1\sr_op__oe__ok$9$next[0:0]$8611 + assign $2\sr_op__rc__ok$7$next[0:0]$8621 $1\sr_op__rc__ok$7$next[0:0]$8614 + assign $2\sr_op__rc__rc$6$next[0:0]$8622 $1\sr_op__rc__rc$6$next[0:0]$8615 + end + sync always + update \sr_op__fn_unit$3$next $0\sr_op__fn_unit$3$next[11:0]$8585 + update \sr_op__imm_data__data$4$next $0\sr_op__imm_data__data$4$next[63:0]$8586 + update \sr_op__imm_data__ok$5$next $0\sr_op__imm_data__ok$5$next[0:0]$8587 + update \sr_op__input_carry$11$next $0\sr_op__input_carry$11$next[1:0]$8588 + update \sr_op__input_cr$13$next $0\sr_op__input_cr$13$next[0:0]$8589 + update \sr_op__insn$17$next $0\sr_op__insn$17$next[31:0]$8590 + update \sr_op__insn_type$2$next $0\sr_op__insn_type$2$next[6:0]$8591 + update \sr_op__is_32bit$15$next $0\sr_op__is_32bit$15$next[0:0]$8592 + update \sr_op__is_signed$16$next $0\sr_op__is_signed$16$next[0:0]$8593 + update \sr_op__oe__oe$8$next $0\sr_op__oe__oe$8$next[0:0]$8594 + update \sr_op__oe__ok$9$next $0\sr_op__oe__ok$9$next[0:0]$8595 + update \sr_op__output_carry$12$next $0\sr_op__output_carry$12$next[0:0]$8596 + update \sr_op__output_cr$14$next $0\sr_op__output_cr$14$next[0:0]$8597 + update \sr_op__rc__ok$7$next $0\sr_op__rc__ok$7$next[0:0]$8598 + update \sr_op__rc__rc$6$next $0\sr_op__rc__rc$6$next[0:0]$8599 + update \sr_op__write_cr0$10$next $0\sr_op__write_cr0$10$next[0:0]$8600 + end + attribute \src "issuer_ls180.v:153869.3-153887.6" + process $proc$issuer_ls180.v:153869$8623 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\o$18$next[63:0]$8624 $1\o$18$next[63:0]$8626 + assign { } { } + assign $0\o_ok$19$next[0:0]$8625 $2\o_ok$19$next[0:0]$8628 + attribute \src "issuer_ls180.v:153870.5-153870.29" + switch \initial + attribute \src "issuer_ls180.v:153870.9-153870.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'-1 + assign { } { } + assign { } { } + assign { $1\o_ok$19$next[0:0]$8627 $1\o$18$next[63:0]$8626 } { \o_ok$69 \o$68 } + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'1- + assign { } { } + assign { } { } + assign { $1\o_ok$19$next[0:0]$8627 $1\o$18$next[63:0]$8626 } { \o_ok$69 \o$68 } + case + assign $1\o$18$next[63:0]$8626 \o$18 + assign $1\o_ok$19$next[0:0]$8627 \o_ok$19 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\o_ok$19$next[0:0]$8628 1'0 + case + assign $2\o_ok$19$next[0:0]$8628 $1\o_ok$19$next[0:0]$8627 + end + sync always + update \o$18$next $0\o$18$next[63:0]$8624 + update \o_ok$19$next $0\o_ok$19$next[0:0]$8625 + end + attribute \src "issuer_ls180.v:153888.3-153906.6" + process $proc$issuer_ls180.v:153888$8629 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\cr_a$20$next[3:0]$8630 $1\cr_a$20$next[3:0]$8632 + assign { } { } + assign $0\cr_a_ok$21$next[0:0]$8631 $2\cr_a_ok$21$next[0:0]$8634 + attribute \src "issuer_ls180.v:153889.5-153889.29" + switch \initial + attribute \src "issuer_ls180.v:153889.9-153889.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'-1 + assign { } { } + assign { } { } + assign { $1\cr_a_ok$21$next[0:0]$8633 $1\cr_a$20$next[3:0]$8632 } { \cr_a_ok$71 \cr_a$70 } + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'1- + assign { } { } + assign { } { } + assign { $1\cr_a_ok$21$next[0:0]$8633 $1\cr_a$20$next[3:0]$8632 } { \cr_a_ok$71 \cr_a$70 } + case + assign $1\cr_a$20$next[3:0]$8632 \cr_a$20 + assign $1\cr_a_ok$21$next[0:0]$8633 \cr_a_ok$21 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\cr_a_ok$21$next[0:0]$8634 1'0 + case + assign $2\cr_a_ok$21$next[0:0]$8634 $1\cr_a_ok$21$next[0:0]$8633 + end + sync always + update \cr_a$20$next $0\cr_a$20$next[3:0]$8630 + update \cr_a_ok$21$next $0\cr_a_ok$21$next[0:0]$8631 + end + attribute \src "issuer_ls180.v:153907.3-153925.6" + process $proc$issuer_ls180.v:153907$8635 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\xer_ca$22$next[1:0]$8636 $1\xer_ca$22$next[1:0]$8638 + assign { } { } + assign $0\xer_ca_ok$23$next[0:0]$8637 $2\xer_ca_ok$23$next[0:0]$8640 + attribute \src "issuer_ls180.v:153908.5-153908.29" + switch \initial + attribute \src "issuer_ls180.v:153908.9-153908.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'-1 + assign { } { } + assign { } { } + assign { $1\xer_ca_ok$23$next[0:0]$8639 $1\xer_ca$22$next[1:0]$8638 } { \xer_ca_ok$73 \xer_ca$72 } + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'1- + assign { } { } + assign { } { } + assign { $1\xer_ca_ok$23$next[0:0]$8639 $1\xer_ca$22$next[1:0]$8638 } { \xer_ca_ok$73 \xer_ca$72 } + case + assign $1\xer_ca$22$next[1:0]$8638 \xer_ca$22 + assign $1\xer_ca_ok$23$next[0:0]$8639 \xer_ca_ok$23 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\xer_ca_ok$23$next[0:0]$8640 1'0 + case + assign $2\xer_ca_ok$23$next[0:0]$8640 $1\xer_ca_ok$23$next[0:0]$8639 + end + sync always + update \xer_ca$22$next $0\xer_ca$22$next[1:0]$8636 + update \xer_ca_ok$23$next $0\xer_ca_ok$23$next[0:0]$8637 + end + connect \$49 $and$issuer_ls180.v:153694$8529_Y + connect \p_ready_o \n_i_rdy_data + connect \n_valid_o \r_busy + connect { \xer_ca_ok$73 \xer_ca$72 } { \output_xer_ca_ok \output_xer_ca$44 } + connect { \cr_a_ok$71 \cr_a$70 } { \output_cr_a_ok \output_cr_a$43 } + connect { \o_ok$69 \o$68 } { \output_o_ok$42 \output_o$41 } + connect { \sr_op__insn$67 \sr_op__is_signed$66 \sr_op__is_32bit$65 \sr_op__output_cr$64 \sr_op__input_cr$63 \sr_op__output_carry$62 \sr_op__input_carry$61 \sr_op__write_cr0$60 \sr_op__oe__ok$59 \sr_op__oe__oe$58 \sr_op__rc__ok$57 \sr_op__rc__rc$56 \sr_op__imm_data__ok$55 \sr_op__imm_data__data$54 \sr_op__fn_unit$53 \sr_op__insn_type$52 } { \output_sr_op__insn$40 \output_sr_op__is_signed$39 \output_sr_op__is_32bit$38 \output_sr_op__output_cr$37 \output_sr_op__input_cr$36 \output_sr_op__output_carry$35 \output_sr_op__input_carry$34 \output_sr_op__write_cr0$33 \output_sr_op__oe__ok$32 \output_sr_op__oe__oe$31 \output_sr_op__rc__ok$30 \output_sr_op__rc__rc$29 \output_sr_op__imm_data__ok$28 \output_sr_op__imm_data__data$27 \output_sr_op__fn_unit$26 \output_sr_op__insn_type$25 } + connect \muxid$51 \output_muxid$24 + connect \p_valid_i_p_ready_o \$49 + connect \n_i_rdy_data \n_ready_i + connect \p_valid_i$48 \p_valid_i + connect { \xer_ca_ok$47 \output_xer_ca } { \xer_ca_ok \xer_ca } + connect { \xer_so_ok$46 \output_xer_so } { \xer_so_ok \xer_so } + connect { \cr_a_ok$45 \output_cr_a } { \cr_a_ok \cr_a } + connect { \output_o_ok \output_o } { \o_ok \o } + connect { \output_sr_op__insn \output_sr_op__is_signed \output_sr_op__is_32bit \output_sr_op__output_cr \output_sr_op__input_cr \output_sr_op__output_carry \output_sr_op__input_carry \output_sr_op__write_cr0 \output_sr_op__oe__ok \output_sr_op__oe__oe \output_sr_op__rc__ok \output_sr_op__rc__rc \output_sr_op__imm_data__ok \output_sr_op__imm_data__data \output_sr_op__fn_unit \output_sr_op__insn_type } { \sr_op__insn \sr_op__is_signed \sr_op__is_32bit \sr_op__output_cr \sr_op__input_cr \sr_op__output_carry \sr_op__input_carry \sr_op__write_cr0 \sr_op__oe__ok \sr_op__oe__oe \sr_op__rc__ok \sr_op__rc__rc \sr_op__imm_data__ok \sr_op__imm_data__data \sr_op__fn_unit \sr_op__insn_type } + connect \output_muxid \muxid +end +attribute \src "issuer_ls180.v:153946.1-155428.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_end" +attribute \generator "nMigen" +module \pipe_end + attribute \src "issuer_ls180.v:155266.3-155284.6" + wire width 4 $0\cr_a$next[3:0]$8745 + attribute \src "issuer_ls180.v:155085.3-155086.25" + wire width 4 $0\cr_a[3:0] + attribute \src "issuer_ls180.v:155266.3-155284.6" + wire $0\cr_a_ok$next[0:0]$8746 + attribute \src "issuer_ls180.v:155087.3-155088.31" + wire $0\cr_a_ok[0:0] + attribute \src "issuer_ls180.v:153947.7-153947.20" + wire $0\initial[0:0] + attribute \src "issuer_ls180.v:155354.3-155395.6" + wire width 4 $0\logical_op__data_len$18$next[3:0]$8770 + attribute \src "issuer_ls180.v:155125.3-155126.65" + wire width 4 $0\logical_op__data_len$18[3:0]$8732 + attribute \src "issuer_ls180.v:153988.13-153988.45" + wire width 4 $0\logical_op__data_len$18[3:0]$8816 + attribute \src "issuer_ls180.v:155354.3-155395.6" + wire width 12 $0\logical_op__fn_unit$3$next[11:0]$8771 + attribute \src "issuer_ls180.v:155095.3-155096.61" + wire width 12 $0\logical_op__fn_unit$3[11:0]$8702 + attribute \src "issuer_ls180.v:154023.14-154023.47" + wire width 12 $0\logical_op__fn_unit$3[11:0]$8818 + attribute \src "issuer_ls180.v:155354.3-155395.6" + wire width 64 $0\logical_op__imm_data__data$4$next[63:0]$8772 + attribute \src "issuer_ls180.v:155097.3-155098.75" + wire width 64 $0\logical_op__imm_data__data$4[63:0]$8704 + attribute \src "issuer_ls180.v:154045.14-154045.67" + wire width 64 $0\logical_op__imm_data__data$4[63:0]$8820 + attribute \src "issuer_ls180.v:155354.3-155395.6" + wire $0\logical_op__imm_data__ok$5$next[0:0]$8773 + attribute \src "issuer_ls180.v:155099.3-155100.71" + wire $0\logical_op__imm_data__ok$5[0:0]$8706 + attribute \src "issuer_ls180.v:154054.7-154054.42" + wire $0\logical_op__imm_data__ok$5[0:0]$8822 + attribute \src "issuer_ls180.v:155354.3-155395.6" + wire width 2 $0\logical_op__input_carry$12$next[1:0]$8774 + attribute \src "issuer_ls180.v:155113.3-155114.71" + wire width 2 $0\logical_op__input_carry$12[1:0]$8720 + attribute \src "issuer_ls180.v:154071.13-154071.48" + wire width 2 $0\logical_op__input_carry$12[1:0]$8824 + attribute \src "issuer_ls180.v:155354.3-155395.6" + wire width 32 $0\logical_op__insn$19$next[31:0]$8775 + attribute \src "issuer_ls180.v:155127.3-155128.57" + wire width 32 $0\logical_op__insn$19[31:0]$8734 + attribute \src "issuer_ls180.v:154084.14-154084.43" + wire width 32 $0\logical_op__insn$19[31:0]$8826 + attribute \src "issuer_ls180.v:155354.3-155395.6" + wire width 7 $0\logical_op__insn_type$2$next[6:0]$8776 + attribute \src "issuer_ls180.v:155093.3-155094.65" + wire width 7 $0\logical_op__insn_type$2[6:0]$8700 + attribute \src "issuer_ls180.v:154241.13-154241.46" + wire width 7 $0\logical_op__insn_type$2[6:0]$8828 + attribute \src "issuer_ls180.v:155354.3-155395.6" + wire $0\logical_op__invert_in$10$next[0:0]$8777 + attribute \src "issuer_ls180.v:155109.3-155110.67" + wire $0\logical_op__invert_in$10[0:0]$8716 + attribute \src "issuer_ls180.v:154324.7-154324.40" + wire $0\logical_op__invert_in$10[0:0]$8830 + attribute \src "issuer_ls180.v:155354.3-155395.6" + wire $0\logical_op__invert_out$13$next[0:0]$8778 + attribute \src "issuer_ls180.v:155115.3-155116.69" + wire $0\logical_op__invert_out$13[0:0]$8722 + attribute \src "issuer_ls180.v:154333.7-154333.41" + wire $0\logical_op__invert_out$13[0:0]$8832 + attribute \src "issuer_ls180.v:155354.3-155395.6" + wire $0\logical_op__is_32bit$16$next[0:0]$8779 + attribute \src "issuer_ls180.v:155121.3-155122.65" + wire $0\logical_op__is_32bit$16[0:0]$8728 + attribute \src "issuer_ls180.v:154342.7-154342.39" + wire $0\logical_op__is_32bit$16[0:0]$8834 + attribute \src "issuer_ls180.v:155354.3-155395.6" + wire $0\logical_op__is_signed$17$next[0:0]$8780 + attribute \src "issuer_ls180.v:155123.3-155124.67" + wire $0\logical_op__is_signed$17[0:0]$8730 + attribute \src "issuer_ls180.v:154351.7-154351.40" + wire $0\logical_op__is_signed$17[0:0]$8836 + attribute \src "issuer_ls180.v:155354.3-155395.6" + wire $0\logical_op__oe__oe$8$next[0:0]$8781 + attribute \src "issuer_ls180.v:155105.3-155106.59" + wire $0\logical_op__oe__oe$8[0:0]$8712 + attribute \src "issuer_ls180.v:154360.7-154360.36" + wire $0\logical_op__oe__oe$8[0:0]$8838 + attribute \src "issuer_ls180.v:155354.3-155395.6" + wire $0\logical_op__oe__ok$9$next[0:0]$8782 + attribute \src "issuer_ls180.v:155107.3-155108.59" + wire $0\logical_op__oe__ok$9[0:0]$8714 + attribute \src "issuer_ls180.v:154371.7-154371.36" + wire $0\logical_op__oe__ok$9[0:0]$8840 + attribute \src "issuer_ls180.v:155354.3-155395.6" + wire $0\logical_op__output_carry$15$next[0:0]$8783 + attribute \src "issuer_ls180.v:155119.3-155120.73" + wire $0\logical_op__output_carry$15[0:0]$8726 + attribute \src "issuer_ls180.v:154378.7-154378.43" + wire $0\logical_op__output_carry$15[0:0]$8842 + attribute \src "issuer_ls180.v:155354.3-155395.6" + wire $0\logical_op__rc__ok$7$next[0:0]$8784 + attribute \src "issuer_ls180.v:155103.3-155104.59" + wire $0\logical_op__rc__ok$7[0:0]$8710 + attribute \src "issuer_ls180.v:154387.7-154387.36" + wire $0\logical_op__rc__ok$7[0:0]$8844 + attribute \src "issuer_ls180.v:155354.3-155395.6" + wire $0\logical_op__rc__rc$6$next[0:0]$8785 + attribute \src "issuer_ls180.v:155101.3-155102.59" + wire $0\logical_op__rc__rc$6[0:0]$8708 + attribute \src "issuer_ls180.v:154396.7-154396.36" + wire $0\logical_op__rc__rc$6[0:0]$8846 + attribute \src "issuer_ls180.v:155354.3-155395.6" + wire $0\logical_op__write_cr0$14$next[0:0]$8786 + attribute \src "issuer_ls180.v:155117.3-155118.67" + wire $0\logical_op__write_cr0$14[0:0]$8724 + attribute \src "issuer_ls180.v:154405.7-154405.40" + wire $0\logical_op__write_cr0$14[0:0]$8848 + attribute \src "issuer_ls180.v:155354.3-155395.6" + wire $0\logical_op__zero_a$11$next[0:0]$8787 + attribute \src "issuer_ls180.v:155111.3-155112.61" + wire $0\logical_op__zero_a$11[0:0]$8718 + attribute \src "issuer_ls180.v:154414.7-154414.37" + wire $0\logical_op__zero_a$11[0:0]$8850 + attribute \src "issuer_ls180.v:155341.3-155353.6" + wire width 2 $0\muxid$1$next[1:0]$8767 + attribute \src "issuer_ls180.v:155129.3-155130.33" + wire width 2 $0\muxid$1[1:0]$8736 + attribute \src "issuer_ls180.v:154423.13-154423.29" + wire width 2 $0\muxid$1[1:0]$8852 + attribute \src "issuer_ls180.v:155247.3-155265.6" + wire width 64 $0\o$next[63:0]$8739 + attribute \src "issuer_ls180.v:155089.3-155090.19" + wire width 64 $0\o[63:0] + attribute \src "issuer_ls180.v:155247.3-155265.6" + wire $0\o_ok$next[0:0]$8740 + attribute \src "issuer_ls180.v:155091.3-155092.25" + wire $0\o_ok[0:0] + attribute \src "issuer_ls180.v:155323.3-155340.6" + wire $0\r_busy$next[0:0]$8763 + attribute \src "issuer_ls180.v:155131.3-155132.29" + wire $0\r_busy[0:0] + attribute \src "issuer_ls180.v:155285.3-155303.6" + wire width 2 $0\xer_ov$next[1:0]$8751 + attribute \src "issuer_ls180.v:155081.3-155082.29" + wire width 2 $0\xer_ov[1:0] + attribute \src "issuer_ls180.v:155285.3-155303.6" + wire $0\xer_ov_ok$next[0:0]$8752 + attribute \src "issuer_ls180.v:155083.3-155084.35" + wire $0\xer_ov_ok[0:0] + attribute \src "issuer_ls180.v:155304.3-155322.6" + wire $0\xer_so$20$next[0:0]$8758 + attribute \src "issuer_ls180.v:155077.3-155078.37" + wire $0\xer_so$20[0:0]$8691 + attribute \src "issuer_ls180.v:155062.7-155062.25" + wire $0\xer_so$20[0:0]$8859 + attribute \src "issuer_ls180.v:155304.3-155322.6" + wire $0\xer_so_ok$next[0:0]$8757 + attribute \src "issuer_ls180.v:155079.3-155080.35" + wire $0\xer_so_ok[0:0] + attribute \src "issuer_ls180.v:155266.3-155284.6" + wire width 4 $1\cr_a$next[3:0]$8747 + attribute \src "issuer_ls180.v:153956.13-153956.24" + wire width 4 $1\cr_a[3:0] + attribute \src "issuer_ls180.v:155266.3-155284.6" + wire $1\cr_a_ok$next[0:0]$8748 + attribute \src "issuer_ls180.v:153965.7-153965.21" + wire $1\cr_a_ok[0:0] + attribute \src "issuer_ls180.v:155354.3-155395.6" + wire width 4 $1\logical_op__data_len$18$next[3:0]$8788 + attribute \src "issuer_ls180.v:155354.3-155395.6" + wire width 12 $1\logical_op__fn_unit$3$next[11:0]$8789 + attribute \src "issuer_ls180.v:155354.3-155395.6" + wire width 64 $1\logical_op__imm_data__data$4$next[63:0]$8790 + attribute \src "issuer_ls180.v:155354.3-155395.6" + wire $1\logical_op__imm_data__ok$5$next[0:0]$8791 + attribute \src "issuer_ls180.v:155354.3-155395.6" + wire width 2 $1\logical_op__input_carry$12$next[1:0]$8792 + attribute \src "issuer_ls180.v:155354.3-155395.6" + wire width 32 $1\logical_op__insn$19$next[31:0]$8793 + attribute \src "issuer_ls180.v:155354.3-155395.6" + wire width 7 $1\logical_op__insn_type$2$next[6:0]$8794 + attribute \src "issuer_ls180.v:155354.3-155395.6" + wire $1\logical_op__invert_in$10$next[0:0]$8795 + attribute \src "issuer_ls180.v:155354.3-155395.6" + wire $1\logical_op__invert_out$13$next[0:0]$8796 + attribute \src "issuer_ls180.v:155354.3-155395.6" + wire $1\logical_op__is_32bit$16$next[0:0]$8797 + attribute \src "issuer_ls180.v:155354.3-155395.6" + wire $1\logical_op__is_signed$17$next[0:0]$8798 + attribute \src "issuer_ls180.v:155354.3-155395.6" + wire $1\logical_op__oe__oe$8$next[0:0]$8799 + attribute \src "issuer_ls180.v:155354.3-155395.6" + wire $1\logical_op__oe__ok$9$next[0:0]$8800 + attribute \src "issuer_ls180.v:155354.3-155395.6" + wire $1\logical_op__output_carry$15$next[0:0]$8801 + attribute \src "issuer_ls180.v:155354.3-155395.6" + wire $1\logical_op__rc__ok$7$next[0:0]$8802 + attribute \src "issuer_ls180.v:155354.3-155395.6" + wire $1\logical_op__rc__rc$6$next[0:0]$8803 + attribute \src "issuer_ls180.v:155354.3-155395.6" + wire $1\logical_op__write_cr0$14$next[0:0]$8804 + attribute \src "issuer_ls180.v:155354.3-155395.6" + wire $1\logical_op__zero_a$11$next[0:0]$8805 + attribute \src "issuer_ls180.v:155341.3-155353.6" + wire width 2 $1\muxid$1$next[1:0]$8768 + attribute \src "issuer_ls180.v:155247.3-155265.6" + wire width 64 $1\o$next[63:0]$8741 + attribute \src "issuer_ls180.v:154436.14-154436.38" + wire width 64 $1\o[63:0] + attribute \src "issuer_ls180.v:155247.3-155265.6" + wire $1\o_ok$next[0:0]$8742 + attribute \src "issuer_ls180.v:154443.7-154443.18" + wire $1\o_ok[0:0] + attribute \src "issuer_ls180.v:155323.3-155340.6" + wire $1\r_busy$next[0:0]$8764 + attribute \src "issuer_ls180.v:155027.7-155027.20" + wire $1\r_busy[0:0] + attribute \src "issuer_ls180.v:155285.3-155303.6" + wire width 2 $1\xer_ov$next[1:0]$8753 + attribute \src "issuer_ls180.v:155042.13-155042.26" + wire width 2 $1\xer_ov[1:0] + attribute \src "issuer_ls180.v:155285.3-155303.6" + wire $1\xer_ov_ok$next[0:0]$8754 + attribute \src "issuer_ls180.v:155049.7-155049.23" + wire $1\xer_ov_ok[0:0] + attribute \src "issuer_ls180.v:155304.3-155322.6" + wire $1\xer_so$20$next[0:0]$8760 + attribute \src "issuer_ls180.v:155304.3-155322.6" + wire $1\xer_so_ok$next[0:0]$8759 + attribute \src "issuer_ls180.v:155067.7-155067.23" + wire $1\xer_so_ok[0:0] + attribute \src "issuer_ls180.v:155266.3-155284.6" + wire $2\cr_a_ok$next[0:0]$8749 + attribute \src "issuer_ls180.v:155354.3-155395.6" + wire width 64 $2\logical_op__imm_data__data$4$next[63:0]$8806 + attribute \src "issuer_ls180.v:155354.3-155395.6" + wire $2\logical_op__imm_data__ok$5$next[0:0]$8807 + attribute \src "issuer_ls180.v:155354.3-155395.6" + wire $2\logical_op__oe__oe$8$next[0:0]$8808 + attribute \src "issuer_ls180.v:155354.3-155395.6" + wire $2\logical_op__oe__ok$9$next[0:0]$8809 + attribute \src "issuer_ls180.v:155354.3-155395.6" + wire $2\logical_op__rc__ok$7$next[0:0]$8810 + attribute \src "issuer_ls180.v:155354.3-155395.6" + wire $2\logical_op__rc__rc$6$next[0:0]$8811 + attribute \src "issuer_ls180.v:155247.3-155265.6" + wire $2\o_ok$next[0:0]$8743 + attribute \src "issuer_ls180.v:155323.3-155340.6" + wire $2\r_busy$next[0:0]$8765 + attribute \src "issuer_ls180.v:155285.3-155303.6" + wire $2\xer_ov_ok$next[0:0]$8755 + attribute \src "issuer_ls180.v:155304.3-155322.6" + wire $2\xer_so_ok$next[0:0]$8761 + attribute \src "issuer_ls180.v:155076.18-155076.118" + wire $and$issuer_ls180.v:155076$8689_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" + wire \$74 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" + wire input 62 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" + wire input 1 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 4 output 56 \cr_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 4 \cr_a$68 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 4 \cr_a$97 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 4 \cr_a$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 57 \cr_a_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \cr_a_ok$67 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \cr_a_ok$69 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \cr_a_ok$98 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \cr_a_ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire input 30 \div_by_zero + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire input 28 \dive_abs_ov32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire input 29 \dive_abs_ov64 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire input 27 \dividend_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire input 26 \divisor_neg + attribute \src "issuer_ls180.v:153947.7-153947.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 input 21 \logical_op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 output 52 \logical_op__data_len$18 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \logical_op__data_len$18$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \logical_op__data_len$93 + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 input 6 \logical_op__fn_unit + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 output 37 \logical_op__fn_unit$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 \logical_op__fn_unit$3$next + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 \logical_op__fn_unit$78 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 input 7 \logical_op__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 output 38 \logical_op__imm_data__data$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \logical_op__imm_data__data$4$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \logical_op__imm_data__data$79 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 8 \logical_op__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 39 \logical_op__imm_data__ok$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__imm_data__ok$5$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__imm_data__ok$80 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 input 15 \logical_op__input_carry + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 output 46 \logical_op__input_carry$12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \logical_op__input_carry$12$next + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \logical_op__input_carry$87 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 22 \logical_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 output 53 \logical_op__insn$19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \logical_op__insn$19$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \logical_op__insn$94 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 input 5 \logical_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 output 36 \logical_op__insn_type$2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \logical_op__insn_type$2$next + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \logical_op__insn_type$77 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 13 \logical_op__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 44 \logical_op__invert_in$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__invert_in$10$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__invert_in$85 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 16 \logical_op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 47 \logical_op__invert_out$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__invert_out$13$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__invert_out$88 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 19 \logical_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 50 \logical_op__is_32bit$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__is_32bit$16$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__is_32bit$91 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 20 \logical_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 51 \logical_op__is_signed$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__is_signed$17$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__is_signed$92 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 11 \logical_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 42 \logical_op__oe__oe$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__oe__oe$8$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__oe__oe$83 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 12 \logical_op__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__oe__ok$84 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 43 \logical_op__oe__ok$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__oe__ok$9$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 18 \logical_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 49 \logical_op__output_carry$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__output_carry$15$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__output_carry$90 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 10 \logical_op__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 41 \logical_op__rc__ok$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__rc__ok$7$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__rc__ok$82 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 9 \logical_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 40 \logical_op__rc__rc$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__rc__rc$6$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__rc__rc$81 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 17 \logical_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 48 \logical_op__write_cr0$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__write_cr0$14$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__write_cr0$89 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 14 \logical_op__zero_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 45 \logical_op__zero_a$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__zero_a$11$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__zero_a$86 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 input 4 \muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 output 35 \muxid$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \muxid$1$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \muxid$76 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:619" + wire \n_i_rdy_data + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" + wire input 34 \n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" + wire output 33 \n_valid_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 output 54 \o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 \o$95 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 \o$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 55 \o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \o_ok$96 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \o_ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 4 \output_cr_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 4 \output_cr_a$62 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \output_cr_a_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \output_logical_op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \output_logical_op__data_len$58 + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 \output_logical_op__fn_unit + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 \output_logical_op__fn_unit$43 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \output_logical_op__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \output_logical_op__imm_data__data$44 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_logical_op__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_logical_op__imm_data__ok$45 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \output_logical_op__input_carry + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \output_logical_op__input_carry$52 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \output_logical_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \output_logical_op__insn$59 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \output_logical_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \output_logical_op__insn_type$42 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_logical_op__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_logical_op__invert_in$50 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_logical_op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_logical_op__invert_out$53 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_logical_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_logical_op__is_32bit$56 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_logical_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_logical_op__is_signed$57 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_logical_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_logical_op__oe__oe$48 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_logical_op__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_logical_op__oe__ok$49 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_logical_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_logical_op__output_carry$55 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_logical_op__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_logical_op__rc__ok$47 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_logical_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_logical_op__rc__rc$46 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_logical_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_logical_op__write_cr0$54 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_logical_op__zero_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_logical_op__zero_a$51 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \output_muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \output_muxid$41 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 \output_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 \output_o$60 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \output_o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \output_o_ok$61 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire \output_stage_div_by_zero + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire \output_stage_dive_abs_ov32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire \output_stage_dive_abs_ov64 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire \output_stage_dividend_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire \output_stage_divisor_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \output_stage_logical_op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \output_stage_logical_op__data_len$38 + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 \output_stage_logical_op__fn_unit + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 \output_stage_logical_op__fn_unit$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \output_stage_logical_op__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \output_stage_logical_op__imm_data__data$24 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_stage_logical_op__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_stage_logical_op__imm_data__ok$25 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \output_stage_logical_op__input_carry + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \output_stage_logical_op__input_carry$32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \output_stage_logical_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \output_stage_logical_op__insn$39 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \output_stage_logical_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \output_stage_logical_op__insn_type$22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_stage_logical_op__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_stage_logical_op__invert_in$30 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_stage_logical_op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_stage_logical_op__invert_out$33 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_stage_logical_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_stage_logical_op__is_32bit$36 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_stage_logical_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_stage_logical_op__is_signed$37 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_stage_logical_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_stage_logical_op__oe__oe$28 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_stage_logical_op__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_stage_logical_op__oe__ok$29 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_stage_logical_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_stage_logical_op__output_carry$35 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_stage_logical_op__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_stage_logical_op__rc__ok$27 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_stage_logical_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_stage_logical_op__rc__rc$26 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_stage_logical_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_stage_logical_op__write_cr0$34 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_stage_logical_op__zero_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \output_stage_logical_op__zero_a$31 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \output_stage_muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \output_stage_muxid$21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 \output_stage_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \output_stage_o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:40" + wire width 64 \output_stage_quotient_root + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:41" + wire width 192 \output_stage_remainder + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 2 \output_stage_xer_ov + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \output_stage_xer_ov_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire \output_stage_xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \output_stage_xer_so$40 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 2 \output_xer_ov + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 2 \output_xer_ov$63 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \output_xer_ov_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \output_xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \output_xer_so$64 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \output_xer_so_ok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" + wire output 3 \p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" + wire input 2 \p_valid_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:621" + wire \p_valid_i$73 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" + wire \p_valid_i_p_ready_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:40" + wire width 64 input 31 \quotient_root + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615" + wire \r_busy + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615" + wire \r_busy$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 23 \ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \ra$65 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 24 \rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \rb$66 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:41" + wire width 192 input 32 \remainder + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 2 output 58 \xer_ov + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 2 \xer_ov$99 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 2 \xer_ov$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 59 \xer_ov_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \xer_ov_ok$100 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \xer_ov_ok$70 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \xer_ov_ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire input 25 \xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \xer_so$101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 60 \xer_so$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \xer_so$20$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 61 \xer_so_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \xer_so_ok$102 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \xer_so_ok$71 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \xer_so_ok$72 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire \xer_so_ok$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" + cell $and $and$issuer_ls180.v:155076$8689 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \p_valid_i$73 + connect \B \p_ready_o + connect \Y $and$issuer_ls180.v:155076$8689_Y + end + attribute \module_not_derived 1 + attribute \src "issuer_ls180.v:155133.10-155136.4" + cell \n$79 \n + connect \n_ready_i \n_ready_i + connect \n_valid_o \n_valid_o + end + attribute \module_not_derived 1 + attribute \src "issuer_ls180.v:155137.15-155189.4" + cell \output$80 \output + connect \cr_a \output_cr_a + connect \cr_a$22 \output_cr_a$62 + connect \cr_a_ok \output_cr_a_ok + connect \logical_op__data_len \output_logical_op__data_len + connect \logical_op__data_len$18 \output_logical_op__data_len$58 + connect \logical_op__fn_unit \output_logical_op__fn_unit + connect \logical_op__fn_unit$3 \output_logical_op__fn_unit$43 + connect \logical_op__imm_data__data \output_logical_op__imm_data__data + connect \logical_op__imm_data__data$4 \output_logical_op__imm_data__data$44 + connect \logical_op__imm_data__ok \output_logical_op__imm_data__ok + connect \logical_op__imm_data__ok$5 \output_logical_op__imm_data__ok$45 + connect \logical_op__input_carry \output_logical_op__input_carry + connect \logical_op__input_carry$12 \output_logical_op__input_carry$52 + connect \logical_op__insn \output_logical_op__insn + connect \logical_op__insn$19 \output_logical_op__insn$59 + connect \logical_op__insn_type \output_logical_op__insn_type + connect \logical_op__insn_type$2 \output_logical_op__insn_type$42 + connect \logical_op__invert_in \output_logical_op__invert_in + connect \logical_op__invert_in$10 \output_logical_op__invert_in$50 + connect \logical_op__invert_out \output_logical_op__invert_out + connect \logical_op__invert_out$13 \output_logical_op__invert_out$53 + connect \logical_op__is_32bit \output_logical_op__is_32bit + connect \logical_op__is_32bit$16 \output_logical_op__is_32bit$56 + connect \logical_op__is_signed \output_logical_op__is_signed + connect \logical_op__is_signed$17 \output_logical_op__is_signed$57 + connect \logical_op__oe__oe \output_logical_op__oe__oe + connect \logical_op__oe__oe$8 \output_logical_op__oe__oe$48 + connect \logical_op__oe__ok \output_logical_op__oe__ok + connect \logical_op__oe__ok$9 \output_logical_op__oe__ok$49 + connect \logical_op__output_carry \output_logical_op__output_carry + connect \logical_op__output_carry$15 \output_logical_op__output_carry$55 + connect \logical_op__rc__ok \output_logical_op__rc__ok + connect \logical_op__rc__ok$7 \output_logical_op__rc__ok$47 + connect \logical_op__rc__rc \output_logical_op__rc__rc + connect \logical_op__rc__rc$6 \output_logical_op__rc__rc$46 + connect \logical_op__write_cr0 \output_logical_op__write_cr0 + connect \logical_op__write_cr0$14 \output_logical_op__write_cr0$54 + connect \logical_op__zero_a \output_logical_op__zero_a + connect \logical_op__zero_a$11 \output_logical_op__zero_a$51 + connect \muxid \output_muxid + connect \muxid$1 \output_muxid$41 + connect \o \output_o + connect \o$20 \output_o$60 + connect \o_ok \output_o_ok + connect \o_ok$21 \output_o_ok$61 + connect \xer_ov \output_xer_ov + connect \xer_ov$23 \output_xer_ov$63 + connect \xer_ov_ok \output_xer_ov_ok + connect \xer_so \output_xer_so + connect \xer_so$24 \output_xer_so$64 + connect \xer_so_ok \output_xer_so_ok + end + attribute \module_not_derived 1 + attribute \src "issuer_ls180.v:155190.16-155242.4" + cell \output_stage \output_stage + connect \div_by_zero \output_stage_div_by_zero + connect \dive_abs_ov32 \output_stage_dive_abs_ov32 + connect \dive_abs_ov64 \output_stage_dive_abs_ov64 + connect \dividend_neg \output_stage_dividend_neg + connect \divisor_neg \output_stage_divisor_neg + connect \logical_op__data_len \output_stage_logical_op__data_len + connect \logical_op__data_len$18 \output_stage_logical_op__data_len$38 + connect \logical_op__fn_unit \output_stage_logical_op__fn_unit + connect \logical_op__fn_unit$3 \output_stage_logical_op__fn_unit$23 + connect \logical_op__imm_data__data \output_stage_logical_op__imm_data__data + connect \logical_op__imm_data__data$4 \output_stage_logical_op__imm_data__data$24 + connect \logical_op__imm_data__ok \output_stage_logical_op__imm_data__ok + connect \logical_op__imm_data__ok$5 \output_stage_logical_op__imm_data__ok$25 + connect \logical_op__input_carry \output_stage_logical_op__input_carry + connect \logical_op__input_carry$12 \output_stage_logical_op__input_carry$32 + connect \logical_op__insn \output_stage_logical_op__insn + connect \logical_op__insn$19 \output_stage_logical_op__insn$39 + connect \logical_op__insn_type \output_stage_logical_op__insn_type + connect \logical_op__insn_type$2 \output_stage_logical_op__insn_type$22 + connect \logical_op__invert_in \output_stage_logical_op__invert_in + connect \logical_op__invert_in$10 \output_stage_logical_op__invert_in$30 + connect \logical_op__invert_out \output_stage_logical_op__invert_out + connect \logical_op__invert_out$13 \output_stage_logical_op__invert_out$33 + connect \logical_op__is_32bit \output_stage_logical_op__is_32bit + connect \logical_op__is_32bit$16 \output_stage_logical_op__is_32bit$36 + connect \logical_op__is_signed \output_stage_logical_op__is_signed + connect \logical_op__is_signed$17 \output_stage_logical_op__is_signed$37 + connect \logical_op__oe__oe \output_stage_logical_op__oe__oe + connect \logical_op__oe__oe$8 \output_stage_logical_op__oe__oe$28 + connect \logical_op__oe__ok \output_stage_logical_op__oe__ok + connect \logical_op__oe__ok$9 \output_stage_logical_op__oe__ok$29 + connect \logical_op__output_carry \output_stage_logical_op__output_carry + connect \logical_op__output_carry$15 \output_stage_logical_op__output_carry$35 + connect \logical_op__rc__ok \output_stage_logical_op__rc__ok + connect \logical_op__rc__ok$7 \output_stage_logical_op__rc__ok$27 + connect \logical_op__rc__rc \output_stage_logical_op__rc__rc + connect \logical_op__rc__rc$6 \output_stage_logical_op__rc__rc$26 + connect \logical_op__write_cr0 \output_stage_logical_op__write_cr0 + connect \logical_op__write_cr0$14 \output_stage_logical_op__write_cr0$34 + connect \logical_op__zero_a \output_stage_logical_op__zero_a + connect \logical_op__zero_a$11 \output_stage_logical_op__zero_a$31 + connect \muxid \output_stage_muxid + connect \muxid$1 \output_stage_muxid$21 + connect \o \output_stage_o + connect \o_ok \output_stage_o_ok + connect \quotient_root \output_stage_quotient_root + connect \remainder \output_stage_remainder + connect \xer_ov \output_stage_xer_ov + connect \xer_ov_ok \output_stage_xer_ov_ok + connect \xer_so \output_stage_xer_so + connect \xer_so$20 \output_stage_xer_so$40 + end + attribute \module_not_derived 1 + attribute \src "issuer_ls180.v:155243.10-155246.4" + cell \p$78 \p + connect \p_ready_o \p_ready_o + connect \p_valid_i \p_valid_i + end + attribute \src "issuer_ls180.v:153947.7-153947.20" + process $proc$issuer_ls180.v:153947$8812 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "issuer_ls180.v:153956.13-153956.24" + process $proc$issuer_ls180.v:153956$8813 + assign { } { } + assign $1\cr_a[3:0] 4'0000 + sync always + sync init + update \cr_a $1\cr_a[3:0] + end + attribute \src "issuer_ls180.v:153965.7-153965.21" + process $proc$issuer_ls180.v:153965$8814 + assign { } { } + assign $1\cr_a_ok[0:0] 1'0 + sync always + sync init + update \cr_a_ok $1\cr_a_ok[0:0] + end + attribute \src "issuer_ls180.v:153988.13-153988.45" + process $proc$issuer_ls180.v:153988$8815 + assign { } { } + assign $0\logical_op__data_len$18[3:0]$8816 4'0000 + sync always + sync init + update \logical_op__data_len$18 $0\logical_op__data_len$18[3:0]$8816 + end + attribute \src "issuer_ls180.v:154023.14-154023.47" + process $proc$issuer_ls180.v:154023$8817 + assign { } { } + assign $0\logical_op__fn_unit$3[11:0]$8818 12'000000000000 + sync always + sync init + update \logical_op__fn_unit$3 $0\logical_op__fn_unit$3[11:0]$8818 + end + attribute \src "issuer_ls180.v:154045.14-154045.67" + process $proc$issuer_ls180.v:154045$8819 + assign { } { } + assign $0\logical_op__imm_data__data$4[63:0]$8820 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \logical_op__imm_data__data$4 $0\logical_op__imm_data__data$4[63:0]$8820 + end + attribute \src "issuer_ls180.v:154054.7-154054.42" + process $proc$issuer_ls180.v:154054$8821 + assign { } { } + assign $0\logical_op__imm_data__ok$5[0:0]$8822 1'0 + sync always + sync init + update \logical_op__imm_data__ok$5 $0\logical_op__imm_data__ok$5[0:0]$8822 + end + attribute \src "issuer_ls180.v:154071.13-154071.48" + process $proc$issuer_ls180.v:154071$8823 + assign { } { } + assign $0\logical_op__input_carry$12[1:0]$8824 2'00 + sync always + sync init + update \logical_op__input_carry$12 $0\logical_op__input_carry$12[1:0]$8824 + end + attribute \src "issuer_ls180.v:154084.14-154084.43" + process $proc$issuer_ls180.v:154084$8825 + assign { } { } + assign $0\logical_op__insn$19[31:0]$8826 0 + sync always + sync init + update \logical_op__insn$19 $0\logical_op__insn$19[31:0]$8826 + end + attribute \src "issuer_ls180.v:154241.13-154241.46" + process $proc$issuer_ls180.v:154241$8827 + assign { } { } + assign $0\logical_op__insn_type$2[6:0]$8828 7'0000000 + sync always + sync init + update \logical_op__insn_type$2 $0\logical_op__insn_type$2[6:0]$8828 + end + attribute \src "issuer_ls180.v:154324.7-154324.40" + process $proc$issuer_ls180.v:154324$8829 + assign { } { } + assign $0\logical_op__invert_in$10[0:0]$8830 1'0 + sync always + sync init + update \logical_op__invert_in$10 $0\logical_op__invert_in$10[0:0]$8830 + end + attribute \src "issuer_ls180.v:154333.7-154333.41" + process $proc$issuer_ls180.v:154333$8831 + assign { } { } + assign $0\logical_op__invert_out$13[0:0]$8832 1'0 + sync always + sync init + update \logical_op__invert_out$13 $0\logical_op__invert_out$13[0:0]$8832 + end + attribute \src "issuer_ls180.v:154342.7-154342.39" + process $proc$issuer_ls180.v:154342$8833 + assign { } { } + assign $0\logical_op__is_32bit$16[0:0]$8834 1'0 + sync always + sync init + update \logical_op__is_32bit$16 $0\logical_op__is_32bit$16[0:0]$8834 + end + attribute \src "issuer_ls180.v:154351.7-154351.40" + process $proc$issuer_ls180.v:154351$8835 + assign { } { } + assign $0\logical_op__is_signed$17[0:0]$8836 1'0 + sync always + sync init + update \logical_op__is_signed$17 $0\logical_op__is_signed$17[0:0]$8836 + end + attribute \src "issuer_ls180.v:154360.7-154360.36" + process $proc$issuer_ls180.v:154360$8837 + assign { } { } + assign $0\logical_op__oe__oe$8[0:0]$8838 1'0 + sync always + sync init + update \logical_op__oe__oe$8 $0\logical_op__oe__oe$8[0:0]$8838 + end + attribute \src "issuer_ls180.v:154371.7-154371.36" + process $proc$issuer_ls180.v:154371$8839 + assign { } { } + assign $0\logical_op__oe__ok$9[0:0]$8840 1'0 + sync always + sync init + update \logical_op__oe__ok$9 $0\logical_op__oe__ok$9[0:0]$8840 + end + attribute \src "issuer_ls180.v:154378.7-154378.43" + process $proc$issuer_ls180.v:154378$8841 + assign { } { } + assign $0\logical_op__output_carry$15[0:0]$8842 1'0 + sync always + sync init + update \logical_op__output_carry$15 $0\logical_op__output_carry$15[0:0]$8842 + end + attribute \src "issuer_ls180.v:154387.7-154387.36" + process $proc$issuer_ls180.v:154387$8843 + assign { } { } + assign $0\logical_op__rc__ok$7[0:0]$8844 1'0 + sync always + sync init + update \logical_op__rc__ok$7 $0\logical_op__rc__ok$7[0:0]$8844 + end + attribute \src "issuer_ls180.v:154396.7-154396.36" + process $proc$issuer_ls180.v:154396$8845 + assign { } { } + assign $0\logical_op__rc__rc$6[0:0]$8846 1'0 + sync always + sync init + update \logical_op__rc__rc$6 $0\logical_op__rc__rc$6[0:0]$8846 + end + attribute \src "issuer_ls180.v:154405.7-154405.40" + process $proc$issuer_ls180.v:154405$8847 + assign { } { } + assign $0\logical_op__write_cr0$14[0:0]$8848 1'0 + sync always + sync init + update \logical_op__write_cr0$14 $0\logical_op__write_cr0$14[0:0]$8848 + end + attribute \src "issuer_ls180.v:154414.7-154414.37" + process $proc$issuer_ls180.v:154414$8849 + assign { } { } + assign $0\logical_op__zero_a$11[0:0]$8850 1'0 + sync always + sync init + update \logical_op__zero_a$11 $0\logical_op__zero_a$11[0:0]$8850 + end + attribute \src "issuer_ls180.v:154423.13-154423.29" + process $proc$issuer_ls180.v:154423$8851 + assign { } { } + assign $0\muxid$1[1:0]$8852 2'00 + sync always + sync init + update \muxid$1 $0\muxid$1[1:0]$8852 + end + attribute \src "issuer_ls180.v:154436.14-154436.38" + process $proc$issuer_ls180.v:154436$8853 + assign { } { } + assign $1\o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \o $1\o[63:0] + end + attribute \src "issuer_ls180.v:154443.7-154443.18" + process $proc$issuer_ls180.v:154443$8854 + assign { } { } + assign $1\o_ok[0:0] 1'0 + sync always + sync init + update \o_ok $1\o_ok[0:0] + end + attribute \src "issuer_ls180.v:155027.7-155027.20" + process $proc$issuer_ls180.v:155027$8855 + assign { } { } + assign $1\r_busy[0:0] 1'0 + sync always + sync init + update \r_busy $1\r_busy[0:0] + end + attribute \src "issuer_ls180.v:155042.13-155042.26" + process $proc$issuer_ls180.v:155042$8856 + assign { } { } + assign $1\xer_ov[1:0] 2'00 + sync always + sync init + update \xer_ov $1\xer_ov[1:0] + end + attribute \src "issuer_ls180.v:155049.7-155049.23" + process $proc$issuer_ls180.v:155049$8857 + assign { } { } + assign $1\xer_ov_ok[0:0] 1'0 + sync always + sync init + update \xer_ov_ok $1\xer_ov_ok[0:0] + end + attribute \src "issuer_ls180.v:155062.7-155062.25" + process $proc$issuer_ls180.v:155062$8858 + assign { } { } + assign $0\xer_so$20[0:0]$8859 1'0 + sync always + sync init + update \xer_so$20 $0\xer_so$20[0:0]$8859 + end + attribute \src "issuer_ls180.v:155067.7-155067.23" + process $proc$issuer_ls180.v:155067$8860 + assign { } { } + assign $1\xer_so_ok[0:0] 1'0 + sync always + sync init + update \xer_so_ok $1\xer_so_ok[0:0] + end + attribute \src "issuer_ls180.v:155077.3-155078.37" + process $proc$issuer_ls180.v:155077$8690 + assign { } { } + assign $0\xer_so$20[0:0]$8691 \xer_so$20$next + sync posedge \coresync_clk + update \xer_so$20 $0\xer_so$20[0:0]$8691 + end + attribute \src "issuer_ls180.v:155079.3-155080.35" + process $proc$issuer_ls180.v:155079$8692 + assign { } { } + assign $0\xer_so_ok[0:0] \xer_so_ok$next + sync posedge \coresync_clk + update \xer_so_ok $0\xer_so_ok[0:0] + end + attribute \src "issuer_ls180.v:155081.3-155082.29" + process $proc$issuer_ls180.v:155081$8693 + assign { } { } + assign $0\xer_ov[1:0] \xer_ov$next + sync posedge \coresync_clk + update \xer_ov $0\xer_ov[1:0] + end + attribute \src "issuer_ls180.v:155083.3-155084.35" + process $proc$issuer_ls180.v:155083$8694 + assign { } { } + assign $0\xer_ov_ok[0:0] \xer_ov_ok$next + sync posedge \coresync_clk + update \xer_ov_ok $0\xer_ov_ok[0:0] + end + attribute \src "issuer_ls180.v:155085.3-155086.25" + process $proc$issuer_ls180.v:155085$8695 + assign { } { } + assign $0\cr_a[3:0] \cr_a$next + sync posedge \coresync_clk + update \cr_a $0\cr_a[3:0] + end + attribute \src "issuer_ls180.v:155087.3-155088.31" + process $proc$issuer_ls180.v:155087$8696 + assign { } { } + assign $0\cr_a_ok[0:0] \cr_a_ok$next + sync posedge \coresync_clk + update \cr_a_ok $0\cr_a_ok[0:0] + end + attribute \src "issuer_ls180.v:155089.3-155090.19" + process $proc$issuer_ls180.v:155089$8697 + assign { } { } + assign $0\o[63:0] \o$next + sync posedge \coresync_clk + update \o $0\o[63:0] + end + attribute \src "issuer_ls180.v:155091.3-155092.25" + process $proc$issuer_ls180.v:155091$8698 + assign { } { } + assign $0\o_ok[0:0] \o_ok$next + sync posedge \coresync_clk + update \o_ok $0\o_ok[0:0] + end + attribute \src "issuer_ls180.v:155093.3-155094.65" + process $proc$issuer_ls180.v:155093$8699 + assign { } { } + assign $0\logical_op__insn_type$2[6:0]$8700 \logical_op__insn_type$2$next + sync posedge \coresync_clk + update \logical_op__insn_type$2 $0\logical_op__insn_type$2[6:0]$8700 + end + attribute \src "issuer_ls180.v:155095.3-155096.61" + process $proc$issuer_ls180.v:155095$8701 + assign { } { } + assign $0\logical_op__fn_unit$3[11:0]$8702 \logical_op__fn_unit$3$next + sync posedge \coresync_clk + update \logical_op__fn_unit$3 $0\logical_op__fn_unit$3[11:0]$8702 + end + attribute \src "issuer_ls180.v:155097.3-155098.75" + process $proc$issuer_ls180.v:155097$8703 + assign { } { } + assign $0\logical_op__imm_data__data$4[63:0]$8704 \logical_op__imm_data__data$4$next + sync posedge \coresync_clk + update \logical_op__imm_data__data$4 $0\logical_op__imm_data__data$4[63:0]$8704 + end + attribute \src "issuer_ls180.v:155099.3-155100.71" + process $proc$issuer_ls180.v:155099$8705 + assign { } { } + assign $0\logical_op__imm_data__ok$5[0:0]$8706 \logical_op__imm_data__ok$5$next + sync posedge \coresync_clk + update \logical_op__imm_data__ok$5 $0\logical_op__imm_data__ok$5[0:0]$8706 + end + attribute \src "issuer_ls180.v:155101.3-155102.59" + process $proc$issuer_ls180.v:155101$8707 + assign { } { } + assign $0\logical_op__rc__rc$6[0:0]$8708 \logical_op__rc__rc$6$next + sync posedge \coresync_clk + update \logical_op__rc__rc$6 $0\logical_op__rc__rc$6[0:0]$8708 + end + attribute \src "issuer_ls180.v:155103.3-155104.59" + process $proc$issuer_ls180.v:155103$8709 + assign { } { } + assign $0\logical_op__rc__ok$7[0:0]$8710 \logical_op__rc__ok$7$next + sync posedge \coresync_clk + update \logical_op__rc__ok$7 $0\logical_op__rc__ok$7[0:0]$8710 + end + attribute \src "issuer_ls180.v:155105.3-155106.59" + process $proc$issuer_ls180.v:155105$8711 + assign { } { } + assign $0\logical_op__oe__oe$8[0:0]$8712 \logical_op__oe__oe$8$next + sync posedge \coresync_clk + update \logical_op__oe__oe$8 $0\logical_op__oe__oe$8[0:0]$8712 + end + attribute \src "issuer_ls180.v:155107.3-155108.59" + process $proc$issuer_ls180.v:155107$8713 + assign { } { } + assign $0\logical_op__oe__ok$9[0:0]$8714 \logical_op__oe__ok$9$next + sync posedge \coresync_clk + update \logical_op__oe__ok$9 $0\logical_op__oe__ok$9[0:0]$8714 + end + attribute \src "issuer_ls180.v:155109.3-155110.67" + process $proc$issuer_ls180.v:155109$8715 + assign { } { } + assign $0\logical_op__invert_in$10[0:0]$8716 \logical_op__invert_in$10$next + sync posedge \coresync_clk + update \logical_op__invert_in$10 $0\logical_op__invert_in$10[0:0]$8716 + end + attribute \src "issuer_ls180.v:155111.3-155112.61" + process $proc$issuer_ls180.v:155111$8717 + assign { } { } + assign $0\logical_op__zero_a$11[0:0]$8718 \logical_op__zero_a$11$next + sync posedge \coresync_clk + update \logical_op__zero_a$11 $0\logical_op__zero_a$11[0:0]$8718 + end + attribute \src "issuer_ls180.v:155113.3-155114.71" + process $proc$issuer_ls180.v:155113$8719 + assign { } { } + assign $0\logical_op__input_carry$12[1:0]$8720 \logical_op__input_carry$12$next + sync posedge \coresync_clk + update \logical_op__input_carry$12 $0\logical_op__input_carry$12[1:0]$8720 + end + attribute \src "issuer_ls180.v:155115.3-155116.69" + process $proc$issuer_ls180.v:155115$8721 + assign { } { } + assign $0\logical_op__invert_out$13[0:0]$8722 \logical_op__invert_out$13$next + sync posedge \coresync_clk + update \logical_op__invert_out$13 $0\logical_op__invert_out$13[0:0]$8722 + end + attribute \src "issuer_ls180.v:155117.3-155118.67" + process $proc$issuer_ls180.v:155117$8723 + assign { } { } + assign $0\logical_op__write_cr0$14[0:0]$8724 \logical_op__write_cr0$14$next + sync posedge \coresync_clk + update \logical_op__write_cr0$14 $0\logical_op__write_cr0$14[0:0]$8724 + end + attribute \src "issuer_ls180.v:155119.3-155120.73" + process $proc$issuer_ls180.v:155119$8725 + assign { } { } + assign $0\logical_op__output_carry$15[0:0]$8726 \logical_op__output_carry$15$next + sync posedge \coresync_clk + update \logical_op__output_carry$15 $0\logical_op__output_carry$15[0:0]$8726 + end + attribute \src "issuer_ls180.v:155121.3-155122.65" + process $proc$issuer_ls180.v:155121$8727 + assign { } { } + assign $0\logical_op__is_32bit$16[0:0]$8728 \logical_op__is_32bit$16$next + sync posedge \coresync_clk + update \logical_op__is_32bit$16 $0\logical_op__is_32bit$16[0:0]$8728 + end + attribute \src "issuer_ls180.v:155123.3-155124.67" + process $proc$issuer_ls180.v:155123$8729 + assign { } { } + assign $0\logical_op__is_signed$17[0:0]$8730 \logical_op__is_signed$17$next + sync posedge \coresync_clk + update \logical_op__is_signed$17 $0\logical_op__is_signed$17[0:0]$8730 + end + attribute \src "issuer_ls180.v:155125.3-155126.65" + process $proc$issuer_ls180.v:155125$8731 + assign { } { } + assign $0\logical_op__data_len$18[3:0]$8732 \logical_op__data_len$18$next + sync posedge \coresync_clk + update \logical_op__data_len$18 $0\logical_op__data_len$18[3:0]$8732 + end + attribute \src "issuer_ls180.v:155127.3-155128.57" + process $proc$issuer_ls180.v:155127$8733 + assign { } { } + assign $0\logical_op__insn$19[31:0]$8734 \logical_op__insn$19$next + sync posedge \coresync_clk + update \logical_op__insn$19 $0\logical_op__insn$19[31:0]$8734 + end + attribute \src "issuer_ls180.v:155129.3-155130.33" + process $proc$issuer_ls180.v:155129$8735 + assign { } { } + assign $0\muxid$1[1:0]$8736 \muxid$1$next + sync posedge \coresync_clk + update \muxid$1 $0\muxid$1[1:0]$8736 + end + attribute \src "issuer_ls180.v:155131.3-155132.29" + process $proc$issuer_ls180.v:155131$8737 + assign { } { } + assign $0\r_busy[0:0] \r_busy$next + sync posedge \coresync_clk + update \r_busy $0\r_busy[0:0] + end + attribute \src "issuer_ls180.v:155247.3-155265.6" + process $proc$issuer_ls180.v:155247$8738 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\o$next[63:0]$8739 $1\o$next[63:0]$8741 + assign { } { } + assign $0\o_ok$next[0:0]$8740 $2\o_ok$next[0:0]$8743 + attribute \src "issuer_ls180.v:155248.5-155248.29" + switch \initial + attribute \src "issuer_ls180.v:155248.9-155248.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'-1 + assign { } { } + assign { } { } + assign { $1\o_ok$next[0:0]$8742 $1\o$next[63:0]$8741 } { \o_ok$96 \o$95 } + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'1- + assign { } { } + assign { } { } + assign { $1\o_ok$next[0:0]$8742 $1\o$next[63:0]$8741 } { \o_ok$96 \o$95 } + case + assign $1\o$next[63:0]$8741 \o + assign $1\o_ok$next[0:0]$8742 \o_ok + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\o_ok$next[0:0]$8743 1'0 + case + assign $2\o_ok$next[0:0]$8743 $1\o_ok$next[0:0]$8742 + end + sync always + update \o$next $0\o$next[63:0]$8739 + update \o_ok$next $0\o_ok$next[0:0]$8740 + end + attribute \src "issuer_ls180.v:155266.3-155284.6" + process $proc$issuer_ls180.v:155266$8744 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\cr_a$next[3:0]$8745 $1\cr_a$next[3:0]$8747 + assign { } { } + assign $0\cr_a_ok$next[0:0]$8746 $2\cr_a_ok$next[0:0]$8749 + attribute \src "issuer_ls180.v:155267.5-155267.29" + switch \initial + attribute \src "issuer_ls180.v:155267.9-155267.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'-1 + assign { } { } + assign { } { } + assign { $1\cr_a_ok$next[0:0]$8748 $1\cr_a$next[3:0]$8747 } { \cr_a_ok$98 \cr_a$97 } + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'1- + assign { } { } + assign { } { } + assign { $1\cr_a_ok$next[0:0]$8748 $1\cr_a$next[3:0]$8747 } { \cr_a_ok$98 \cr_a$97 } + case + assign $1\cr_a$next[3:0]$8747 \cr_a + assign $1\cr_a_ok$next[0:0]$8748 \cr_a_ok + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\cr_a_ok$next[0:0]$8749 1'0 + case + assign $2\cr_a_ok$next[0:0]$8749 $1\cr_a_ok$next[0:0]$8748 + end + sync always + update \cr_a$next $0\cr_a$next[3:0]$8745 + update \cr_a_ok$next $0\cr_a_ok$next[0:0]$8746 + end + attribute \src "issuer_ls180.v:155285.3-155303.6" + process $proc$issuer_ls180.v:155285$8750 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\xer_ov$next[1:0]$8751 $1\xer_ov$next[1:0]$8753 + assign { } { } + assign $0\xer_ov_ok$next[0:0]$8752 $2\xer_ov_ok$next[0:0]$8755 + attribute \src "issuer_ls180.v:155286.5-155286.29" + switch \initial + attribute \src "issuer_ls180.v:155286.9-155286.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'-1 + assign { } { } + assign { } { } + assign { $1\xer_ov_ok$next[0:0]$8754 $1\xer_ov$next[1:0]$8753 } { \xer_ov_ok$100 \xer_ov$99 } + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'1- + assign { } { } + assign { } { } + assign { $1\xer_ov_ok$next[0:0]$8754 $1\xer_ov$next[1:0]$8753 } { \xer_ov_ok$100 \xer_ov$99 } + case + assign $1\xer_ov$next[1:0]$8753 \xer_ov + assign $1\xer_ov_ok$next[0:0]$8754 \xer_ov_ok + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\xer_ov_ok$next[0:0]$8755 1'0 + case + assign $2\xer_ov_ok$next[0:0]$8755 $1\xer_ov_ok$next[0:0]$8754 + end + sync always + update \xer_ov$next $0\xer_ov$next[1:0]$8751 + update \xer_ov_ok$next $0\xer_ov_ok$next[0:0]$8752 + end + attribute \src "issuer_ls180.v:155304.3-155322.6" + process $proc$issuer_ls180.v:155304$8756 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\xer_so$20$next[0:0]$8758 $1\xer_so$20$next[0:0]$8760 + assign $0\xer_so_ok$next[0:0]$8757 $2\xer_so_ok$next[0:0]$8761 + attribute \src "issuer_ls180.v:155305.5-155305.29" + switch \initial + attribute \src "issuer_ls180.v:155305.9-155305.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'-1 + assign { } { } + assign { } { } + assign { $1\xer_so_ok$next[0:0]$8759 $1\xer_so$20$next[0:0]$8760 } { \xer_so_ok$102 \xer_so$101 } + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'1- + assign { } { } + assign { } { } + assign { $1\xer_so_ok$next[0:0]$8759 $1\xer_so$20$next[0:0]$8760 } { \xer_so_ok$102 \xer_so$101 } + case + assign $1\xer_so_ok$next[0:0]$8759 \xer_so_ok + assign $1\xer_so$20$next[0:0]$8760 \xer_so$20 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\xer_so_ok$next[0:0]$8761 1'0 + case + assign $2\xer_so_ok$next[0:0]$8761 $1\xer_so_ok$next[0:0]$8759 + end + sync always + update \xer_so_ok$next $0\xer_so_ok$next[0:0]$8757 + update \xer_so$20$next $0\xer_so$20$next[0:0]$8758 + end + attribute \src "issuer_ls180.v:155323.3-155340.6" + process $proc$issuer_ls180.v:155323$8762 + assign { } { } + assign { } { } + assign { } { } + assign $0\r_busy$next[0:0]$8763 $2\r_busy$next[0:0]$8765 + attribute \src "issuer_ls180.v:155324.5-155324.29" + switch \initial + attribute \src "issuer_ls180.v:155324.9-155324.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\r_busy$next[0:0]$8764 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\r_busy$next[0:0]$8764 1'0 + case + assign $1\r_busy$next[0:0]$8764 \r_busy + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\r_busy$next[0:0]$8765 1'0 + case + assign $2\r_busy$next[0:0]$8765 $1\r_busy$next[0:0]$8764 + end + sync always + update \r_busy$next $0\r_busy$next[0:0]$8763 + end + attribute \src "issuer_ls180.v:155341.3-155353.6" + process $proc$issuer_ls180.v:155341$8766 + assign { } { } + assign { } { } + assign $0\muxid$1$next[1:0]$8767 $1\muxid$1$next[1:0]$8768 + attribute \src "issuer_ls180.v:155342.5-155342.29" + switch \initial + attribute \src "issuer_ls180.v:155342.9-155342.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\muxid$1$next[1:0]$8768 \muxid$76 + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\muxid$1$next[1:0]$8768 \muxid$76 + case + assign $1\muxid$1$next[1:0]$8768 \muxid$1 + end + sync always + update \muxid$1$next $0\muxid$1$next[1:0]$8767 + end + attribute \src "issuer_ls180.v:155354.3-155395.6" + process $proc$issuer_ls180.v:155354$8769 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\logical_op__data_len$18$next[3:0]$8770 $1\logical_op__data_len$18$next[3:0]$8788 + assign $0\logical_op__fn_unit$3$next[11:0]$8771 $1\logical_op__fn_unit$3$next[11:0]$8789 + assign { } { } + assign { } { } + assign $0\logical_op__input_carry$12$next[1:0]$8774 $1\logical_op__input_carry$12$next[1:0]$8792 + assign $0\logical_op__insn$19$next[31:0]$8775 $1\logical_op__insn$19$next[31:0]$8793 + assign $0\logical_op__insn_type$2$next[6:0]$8776 $1\logical_op__insn_type$2$next[6:0]$8794 + assign $0\logical_op__invert_in$10$next[0:0]$8777 $1\logical_op__invert_in$10$next[0:0]$8795 + assign $0\logical_op__invert_out$13$next[0:0]$8778 $1\logical_op__invert_out$13$next[0:0]$8796 + assign $0\logical_op__is_32bit$16$next[0:0]$8779 $1\logical_op__is_32bit$16$next[0:0]$8797 + assign $0\logical_op__is_signed$17$next[0:0]$8780 $1\logical_op__is_signed$17$next[0:0]$8798 + assign { } { } + assign { } { } + assign $0\logical_op__output_carry$15$next[0:0]$8783 $1\logical_op__output_carry$15$next[0:0]$8801 + assign { } { } + assign { } { } + assign $0\logical_op__write_cr0$14$next[0:0]$8786 $1\logical_op__write_cr0$14$next[0:0]$8804 + assign $0\logical_op__zero_a$11$next[0:0]$8787 $1\logical_op__zero_a$11$next[0:0]$8805 + assign $0\logical_op__imm_data__data$4$next[63:0]$8772 $2\logical_op__imm_data__data$4$next[63:0]$8806 + assign $0\logical_op__imm_data__ok$5$next[0:0]$8773 $2\logical_op__imm_data__ok$5$next[0:0]$8807 + assign $0\logical_op__oe__oe$8$next[0:0]$8781 $2\logical_op__oe__oe$8$next[0:0]$8808 + assign $0\logical_op__oe__ok$9$next[0:0]$8782 $2\logical_op__oe__ok$9$next[0:0]$8809 + assign $0\logical_op__rc__ok$7$next[0:0]$8784 $2\logical_op__rc__ok$7$next[0:0]$8810 + assign $0\logical_op__rc__rc$6$next[0:0]$8785 $2\logical_op__rc__rc$6$next[0:0]$8811 + attribute \src "issuer_ls180.v:155355.5-155355.29" + switch \initial + attribute \src "issuer_ls180.v:155355.9-155355.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'-1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { $1\logical_op__insn$19$next[31:0]$8793 $1\logical_op__data_len$18$next[3:0]$8788 $1\logical_op__is_signed$17$next[0:0]$8798 $1\logical_op__is_32bit$16$next[0:0]$8797 $1\logical_op__output_carry$15$next[0:0]$8801 $1\logical_op__write_cr0$14$next[0:0]$8804 $1\logical_op__invert_out$13$next[0:0]$8796 $1\logical_op__input_carry$12$next[1:0]$8792 $1\logical_op__zero_a$11$next[0:0]$8805 $1\logical_op__invert_in$10$next[0:0]$8795 $1\logical_op__oe__ok$9$next[0:0]$8800 $1\logical_op__oe__oe$8$next[0:0]$8799 $1\logical_op__rc__ok$7$next[0:0]$8802 $1\logical_op__rc__rc$6$next[0:0]$8803 $1\logical_op__imm_data__ok$5$next[0:0]$8791 $1\logical_op__imm_data__data$4$next[63:0]$8790 $1\logical_op__fn_unit$3$next[11:0]$8789 $1\logical_op__insn_type$2$next[6:0]$8794 } { \logical_op__insn$94 \logical_op__data_len$93 \logical_op__is_signed$92 \logical_op__is_32bit$91 \logical_op__output_carry$90 \logical_op__write_cr0$89 \logical_op__invert_out$88 \logical_op__input_carry$87 \logical_op__zero_a$86 \logical_op__invert_in$85 \logical_op__oe__ok$84 \logical_op__oe__oe$83 \logical_op__rc__ok$82 \logical_op__rc__rc$81 \logical_op__imm_data__ok$80 \logical_op__imm_data__data$79 \logical_op__fn_unit$78 \logical_op__insn_type$77 } + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'1- + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { $1\logical_op__insn$19$next[31:0]$8793 $1\logical_op__data_len$18$next[3:0]$8788 $1\logical_op__is_signed$17$next[0:0]$8798 $1\logical_op__is_32bit$16$next[0:0]$8797 $1\logical_op__output_carry$15$next[0:0]$8801 $1\logical_op__write_cr0$14$next[0:0]$8804 $1\logical_op__invert_out$13$next[0:0]$8796 $1\logical_op__input_carry$12$next[1:0]$8792 $1\logical_op__zero_a$11$next[0:0]$8805 $1\logical_op__invert_in$10$next[0:0]$8795 $1\logical_op__oe__ok$9$next[0:0]$8800 $1\logical_op__oe__oe$8$next[0:0]$8799 $1\logical_op__rc__ok$7$next[0:0]$8802 $1\logical_op__rc__rc$6$next[0:0]$8803 $1\logical_op__imm_data__ok$5$next[0:0]$8791 $1\logical_op__imm_data__data$4$next[63:0]$8790 $1\logical_op__fn_unit$3$next[11:0]$8789 $1\logical_op__insn_type$2$next[6:0]$8794 } { \logical_op__insn$94 \logical_op__data_len$93 \logical_op__is_signed$92 \logical_op__is_32bit$91 \logical_op__output_carry$90 \logical_op__write_cr0$89 \logical_op__invert_out$88 \logical_op__input_carry$87 \logical_op__zero_a$86 \logical_op__invert_in$85 \logical_op__oe__ok$84 \logical_op__oe__oe$83 \logical_op__rc__ok$82 \logical_op__rc__rc$81 \logical_op__imm_data__ok$80 \logical_op__imm_data__data$79 \logical_op__fn_unit$78 \logical_op__insn_type$77 } + case + assign $1\logical_op__data_len$18$next[3:0]$8788 \logical_op__data_len$18 + assign $1\logical_op__fn_unit$3$next[11:0]$8789 \logical_op__fn_unit$3 + assign $1\logical_op__imm_data__data$4$next[63:0]$8790 \logical_op__imm_data__data$4 + assign $1\logical_op__imm_data__ok$5$next[0:0]$8791 \logical_op__imm_data__ok$5 + assign $1\logical_op__input_carry$12$next[1:0]$8792 \logical_op__input_carry$12 + assign $1\logical_op__insn$19$next[31:0]$8793 \logical_op__insn$19 + assign $1\logical_op__insn_type$2$next[6:0]$8794 \logical_op__insn_type$2 + assign $1\logical_op__invert_in$10$next[0:0]$8795 \logical_op__invert_in$10 + assign $1\logical_op__invert_out$13$next[0:0]$8796 \logical_op__invert_out$13 + assign $1\logical_op__is_32bit$16$next[0:0]$8797 \logical_op__is_32bit$16 + assign $1\logical_op__is_signed$17$next[0:0]$8798 \logical_op__is_signed$17 + assign $1\logical_op__oe__oe$8$next[0:0]$8799 \logical_op__oe__oe$8 + assign $1\logical_op__oe__ok$9$next[0:0]$8800 \logical_op__oe__ok$9 + assign $1\logical_op__output_carry$15$next[0:0]$8801 \logical_op__output_carry$15 + assign $1\logical_op__rc__ok$7$next[0:0]$8802 \logical_op__rc__ok$7 + assign $1\logical_op__rc__rc$6$next[0:0]$8803 \logical_op__rc__rc$6 + assign $1\logical_op__write_cr0$14$next[0:0]$8804 \logical_op__write_cr0$14 + assign $1\logical_op__zero_a$11$next[0:0]$8805 \logical_op__zero_a$11 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $2\logical_op__imm_data__data$4$next[63:0]$8806 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\logical_op__imm_data__ok$5$next[0:0]$8807 1'0 + assign $2\logical_op__rc__rc$6$next[0:0]$8811 1'0 + assign $2\logical_op__rc__ok$7$next[0:0]$8810 1'0 + assign $2\logical_op__oe__oe$8$next[0:0]$8808 1'0 + assign $2\logical_op__oe__ok$9$next[0:0]$8809 1'0 + case + assign $2\logical_op__imm_data__data$4$next[63:0]$8806 $1\logical_op__imm_data__data$4$next[63:0]$8790 + assign $2\logical_op__imm_data__ok$5$next[0:0]$8807 $1\logical_op__imm_data__ok$5$next[0:0]$8791 + assign $2\logical_op__oe__oe$8$next[0:0]$8808 $1\logical_op__oe__oe$8$next[0:0]$8799 + assign $2\logical_op__oe__ok$9$next[0:0]$8809 $1\logical_op__oe__ok$9$next[0:0]$8800 + assign $2\logical_op__rc__ok$7$next[0:0]$8810 $1\logical_op__rc__ok$7$next[0:0]$8802 + assign $2\logical_op__rc__rc$6$next[0:0]$8811 $1\logical_op__rc__rc$6$next[0:0]$8803 + end + sync always + update \logical_op__data_len$18$next $0\logical_op__data_len$18$next[3:0]$8770 + update \logical_op__fn_unit$3$next $0\logical_op__fn_unit$3$next[11:0]$8771 + update \logical_op__imm_data__data$4$next $0\logical_op__imm_data__data$4$next[63:0]$8772 + update \logical_op__imm_data__ok$5$next $0\logical_op__imm_data__ok$5$next[0:0]$8773 + update \logical_op__input_carry$12$next $0\logical_op__input_carry$12$next[1:0]$8774 + update \logical_op__insn$19$next $0\logical_op__insn$19$next[31:0]$8775 + update \logical_op__insn_type$2$next $0\logical_op__insn_type$2$next[6:0]$8776 + update \logical_op__invert_in$10$next $0\logical_op__invert_in$10$next[0:0]$8777 + update \logical_op__invert_out$13$next $0\logical_op__invert_out$13$next[0:0]$8778 + update \logical_op__is_32bit$16$next $0\logical_op__is_32bit$16$next[0:0]$8779 + update \logical_op__is_signed$17$next $0\logical_op__is_signed$17$next[0:0]$8780 + update \logical_op__oe__oe$8$next $0\logical_op__oe__oe$8$next[0:0]$8781 + update \logical_op__oe__ok$9$next $0\logical_op__oe__ok$9$next[0:0]$8782 + update \logical_op__output_carry$15$next $0\logical_op__output_carry$15$next[0:0]$8783 + update \logical_op__rc__ok$7$next $0\logical_op__rc__ok$7$next[0:0]$8784 + update \logical_op__rc__rc$6$next $0\logical_op__rc__rc$6$next[0:0]$8785 + update \logical_op__write_cr0$14$next $0\logical_op__write_cr0$14$next[0:0]$8786 + update \logical_op__zero_a$11$next $0\logical_op__zero_a$11$next[0:0]$8787 + end + connect \$74 $and$issuer_ls180.v:155076$8689_Y + connect \cr_a$68 4'0000 + connect \cr_a_ok$69 1'0 + connect \xer_so_ok$72 1'0 + connect \p_ready_o \n_i_rdy_data + connect \n_valid_o \r_busy + connect { \xer_so_ok$102 \xer_so$101 } { \output_xer_so_ok \output_xer_so$64 } + connect { \xer_ov_ok$100 \xer_ov$99 } { \output_xer_ov_ok \output_xer_ov$63 } + connect { \cr_a_ok$98 \cr_a$97 } { \output_cr_a_ok \output_cr_a$62 } + connect { \o_ok$96 \o$95 } { \output_o_ok$61 \output_o$60 } + connect { \logical_op__insn$94 \logical_op__data_len$93 \logical_op__is_signed$92 \logical_op__is_32bit$91 \logical_op__output_carry$90 \logical_op__write_cr0$89 \logical_op__invert_out$88 \logical_op__input_carry$87 \logical_op__zero_a$86 \logical_op__invert_in$85 \logical_op__oe__ok$84 \logical_op__oe__oe$83 \logical_op__rc__ok$82 \logical_op__rc__rc$81 \logical_op__imm_data__ok$80 \logical_op__imm_data__data$79 \logical_op__fn_unit$78 \logical_op__insn_type$77 } { \output_logical_op__insn$59 \output_logical_op__data_len$58 \output_logical_op__is_signed$57 \output_logical_op__is_32bit$56 \output_logical_op__output_carry$55 \output_logical_op__write_cr0$54 \output_logical_op__invert_out$53 \output_logical_op__input_carry$52 \output_logical_op__zero_a$51 \output_logical_op__invert_in$50 \output_logical_op__oe__ok$49 \output_logical_op__oe__oe$48 \output_logical_op__rc__ok$47 \output_logical_op__rc__rc$46 \output_logical_op__imm_data__ok$45 \output_logical_op__imm_data__data$44 \output_logical_op__fn_unit$43 \output_logical_op__insn_type$42 } + connect \muxid$76 \output_muxid$41 + connect \p_valid_i_p_ready_o \$74 + connect \n_i_rdy_data \n_ready_i + connect \p_valid_i$73 \p_valid_i + connect { \xer_so_ok$71 \output_xer_so } { 1'0 \output_stage_xer_so$40 } + connect { \xer_ov_ok$70 \output_xer_ov } { \output_stage_xer_ov_ok \output_stage_xer_ov } + connect { \cr_a_ok$67 \output_cr_a } 5'00000 + connect { \output_o_ok \output_o } { \output_stage_o_ok \output_stage_o } + connect { \output_logical_op__insn \output_logical_op__data_len \output_logical_op__is_signed \output_logical_op__is_32bit \output_logical_op__output_carry \output_logical_op__write_cr0 \output_logical_op__invert_out \output_logical_op__input_carry \output_logical_op__zero_a \output_logical_op__invert_in \output_logical_op__oe__ok \output_logical_op__oe__oe \output_logical_op__rc__ok \output_logical_op__rc__rc \output_logical_op__imm_data__ok \output_logical_op__imm_data__data \output_logical_op__fn_unit \output_logical_op__insn_type } { \output_stage_logical_op__insn$39 \output_stage_logical_op__data_len$38 \output_stage_logical_op__is_signed$37 \output_stage_logical_op__is_32bit$36 \output_stage_logical_op__output_carry$35 \output_stage_logical_op__write_cr0$34 \output_stage_logical_op__invert_out$33 \output_stage_logical_op__input_carry$32 \output_stage_logical_op__zero_a$31 \output_stage_logical_op__invert_in$30 \output_stage_logical_op__oe__ok$29 \output_stage_logical_op__oe__oe$28 \output_stage_logical_op__rc__ok$27 \output_stage_logical_op__rc__rc$26 \output_stage_logical_op__imm_data__ok$25 \output_stage_logical_op__imm_data__data$24 \output_stage_logical_op__fn_unit$23 \output_stage_logical_op__insn_type$22 } + connect \output_muxid \output_stage_muxid$21 + connect \output_stage_remainder \remainder + connect \output_stage_quotient_root \quotient_root + connect \output_stage_div_by_zero \div_by_zero + connect \output_stage_dive_abs_ov64 \dive_abs_ov64 + connect \output_stage_dive_abs_ov32 \dive_abs_ov32 + connect \output_stage_dividend_neg \dividend_neg + connect \output_stage_divisor_neg \divisor_neg + connect \output_stage_xer_so \xer_so + connect \rb$66 \rb + connect \ra$65 \ra + connect { \output_stage_logical_op__insn \output_stage_logical_op__data_len \output_stage_logical_op__is_signed \output_stage_logical_op__is_32bit \output_stage_logical_op__output_carry \output_stage_logical_op__write_cr0 \output_stage_logical_op__invert_out \output_stage_logical_op__input_carry \output_stage_logical_op__zero_a \output_stage_logical_op__invert_in \output_stage_logical_op__oe__ok \output_stage_logical_op__oe__oe \output_stage_logical_op__rc__ok \output_stage_logical_op__rc__rc \output_stage_logical_op__imm_data__ok \output_stage_logical_op__imm_data__data \output_stage_logical_op__fn_unit \output_stage_logical_op__insn_type } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in \logical_op__oe__ok \logical_op__oe__oe \logical_op__rc__ok \logical_op__rc__rc \logical_op__imm_data__ok \logical_op__imm_data__data \logical_op__fn_unit \logical_op__insn_type } + connect \output_stage_muxid \muxid +end +attribute \src "issuer_ls180.v:155432.1-156410.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_0" +attribute \generator "nMigen" +module \pipe_middle_0 + attribute \src "issuer_ls180.v:156335.3-156349.6" + wire $0\div_by_zero$54$next[0:0]$9040 + attribute \src "issuer_ls180.v:156009.3-156010.47" + wire $0\div_by_zero$54[0:0]$8875 + attribute \src "issuer_ls180.v:155455.7-155455.30" + wire $0\div_by_zero$54[0:0]$9057 + attribute \src "issuer_ls180.v:156131.3-156142.6" + wire width 64 $0\div_state_next_divisor[63:0] + attribute \src "issuer_ls180.v:156119.3-156130.6" + wire width 128 $0\div_state_next_i_dividend_quotient[127:0] + attribute \src "issuer_ls180.v:156107.3-156118.6" + wire width 7 $0\div_state_next_i_q_bits_known[6:0] + attribute \src "issuer_ls180.v:156305.3-156319.6" + wire $0\dive_abs_ov32$52$next[0:0]$9032 + attribute \src "issuer_ls180.v:156013.3-156014.51" + wire $0\dive_abs_ov32$52[0:0]$8879 + attribute \src "issuer_ls180.v:155479.7-155479.32" + wire $0\dive_abs_ov32$52[0:0]$9059 + attribute \src "issuer_ls180.v:156320.3-156334.6" + wire $0\dive_abs_ov64$53$next[0:0]$9036 + attribute \src "issuer_ls180.v:156011.3-156012.51" + wire $0\dive_abs_ov64$53[0:0]$8877 + attribute \src "issuer_ls180.v:155487.7-155487.32" + wire $0\dive_abs_ov64$53[0:0]$9061 + attribute \src "issuer_ls180.v:156350.3-156364.6" + wire width 128 $0\dividend$68$next[127:0]$9044 + attribute \src "issuer_ls180.v:156007.3-156008.41" + wire width 128 $0\dividend$68[127:0]$8873 + attribute \src "issuer_ls180.v:155493.15-155493.68" + wire width 128 $0\dividend$68[127:0]$9063 + attribute \src "issuer_ls180.v:156290.3-156304.6" + wire $0\dividend_neg$51$next[0:0]$9028 + attribute \src "issuer_ls180.v:156015.3-156016.49" + wire $0\dividend_neg$51[0:0]$8881 + attribute \src "issuer_ls180.v:155501.7-155501.31" + wire $0\dividend_neg$51[0:0]$9065 + attribute \src "issuer_ls180.v:156275.3-156289.6" + wire $0\divisor_neg$50$next[0:0]$9024 + attribute \src "issuer_ls180.v:156017.3-156018.47" + wire $0\divisor_neg$50[0:0]$8883 + attribute \src "issuer_ls180.v:155509.7-155509.30" + wire $0\divisor_neg$50[0:0]$9067 + attribute \src "issuer_ls180.v:156365.3-156379.6" + wire width 64 $0\divisor_radicand$65$next[63:0]$9048 + attribute \src "issuer_ls180.v:156005.3-156006.57" + wire width 64 $0\divisor_radicand$65[63:0]$8871 + attribute \src "issuer_ls180.v:155515.14-155515.58" + wire width 64 $0\divisor_radicand$65[63:0]$9069 + attribute \src "issuer_ls180.v:156143.3-156170.6" + wire $0\empty$next[0:0]$8941 + attribute \src "issuer_ls180.v:156063.3-156064.27" + wire $0\empty[0:0] + attribute \src "issuer_ls180.v:155433.7-155433.20" + wire $0\initial[0:0] + attribute \src "issuer_ls180.v:156186.3-156229.6" + wire width 4 $0\logical_op__data_len$45$next[3:0]$8951 + attribute \src "issuer_ls180.v:156057.3-156058.65" + wire width 4 $0\logical_op__data_len$45[3:0]$8923 + attribute \src "issuer_ls180.v:155527.13-155527.45" + wire width 4 $0\logical_op__data_len$45[3:0]$9072 + attribute \src "issuer_ls180.v:156186.3-156229.6" + wire width 12 $0\logical_op__fn_unit$30$next[11:0]$8952 + attribute \src "issuer_ls180.v:156027.3-156028.63" + wire width 12 $0\logical_op__fn_unit$30[11:0]$8893 + attribute \src "issuer_ls180.v:155574.14-155574.48" + wire width 12 $0\logical_op__fn_unit$30[11:0]$9074 + attribute \src "issuer_ls180.v:156186.3-156229.6" + wire width 64 $0\logical_op__imm_data__data$31$next[63:0]$8953 + attribute \src "issuer_ls180.v:156029.3-156030.77" + wire width 64 $0\logical_op__imm_data__data$31[63:0]$8895 + attribute \src "issuer_ls180.v:155580.14-155580.68" + wire width 64 $0\logical_op__imm_data__data$31[63:0]$9076 + attribute \src "issuer_ls180.v:156186.3-156229.6" + wire $0\logical_op__imm_data__ok$32$next[0:0]$8954 + attribute \src "issuer_ls180.v:156031.3-156032.73" + wire $0\logical_op__imm_data__ok$32[0:0]$8897 + attribute \src "issuer_ls180.v:155588.7-155588.43" + wire $0\logical_op__imm_data__ok$32[0:0]$9078 + attribute \src "issuer_ls180.v:156186.3-156229.6" + wire width 2 $0\logical_op__input_carry$39$next[1:0]$8955 + attribute \src "issuer_ls180.v:156045.3-156046.71" + wire width 2 $0\logical_op__input_carry$39[1:0]$8911 + attribute \src "issuer_ls180.v:155610.13-155610.48" + wire width 2 $0\logical_op__input_carry$39[1:0]$9080 + attribute \src "issuer_ls180.v:156186.3-156229.6" + wire width 32 $0\logical_op__insn$46$next[31:0]$8956 + attribute \src "issuer_ls180.v:156059.3-156060.57" + wire width 32 $0\logical_op__insn$46[31:0]$8925 + attribute \src "issuer_ls180.v:155618.14-155618.43" + wire width 32 $0\logical_op__insn$46[31:0]$9082 + attribute \src "issuer_ls180.v:156186.3-156229.6" + wire width 7 $0\logical_op__insn_type$29$next[6:0]$8957 + attribute \src "issuer_ls180.v:156025.3-156026.67" + wire width 7 $0\logical_op__insn_type$29[6:0]$8891 + attribute \src "issuer_ls180.v:155848.13-155848.47" + wire width 7 $0\logical_op__insn_type$29[6:0]$9084 + attribute \src "issuer_ls180.v:156186.3-156229.6" + wire $0\logical_op__invert_in$37$next[0:0]$8958 + attribute \src "issuer_ls180.v:156041.3-156042.67" + wire $0\logical_op__invert_in$37[0:0]$8907 + attribute \src "issuer_ls180.v:155856.7-155856.40" + wire $0\logical_op__invert_in$37[0:0]$9086 + attribute \src "issuer_ls180.v:156186.3-156229.6" + wire $0\logical_op__invert_out$40$next[0:0]$8959 + attribute \src "issuer_ls180.v:156047.3-156048.69" + wire $0\logical_op__invert_out$40[0:0]$8913 + attribute \src "issuer_ls180.v:155864.7-155864.41" + wire $0\logical_op__invert_out$40[0:0]$9088 + attribute \src "issuer_ls180.v:156186.3-156229.6" + wire $0\logical_op__is_32bit$43$next[0:0]$8960 + attribute \src "issuer_ls180.v:156053.3-156054.65" + wire $0\logical_op__is_32bit$43[0:0]$8919 + attribute \src "issuer_ls180.v:155872.7-155872.39" + wire $0\logical_op__is_32bit$43[0:0]$9090 + attribute \src "issuer_ls180.v:156186.3-156229.6" + wire $0\logical_op__is_signed$44$next[0:0]$8961 + attribute \src "issuer_ls180.v:156055.3-156056.67" + wire $0\logical_op__is_signed$44[0:0]$8921 + attribute \src "issuer_ls180.v:155880.7-155880.40" + wire $0\logical_op__is_signed$44[0:0]$9092 + attribute \src "issuer_ls180.v:156186.3-156229.6" + wire $0\logical_op__oe__oe$35$next[0:0]$8962 + attribute \src "issuer_ls180.v:156037.3-156038.61" + wire $0\logical_op__oe__oe$35[0:0]$8903 + attribute \src "issuer_ls180.v:155886.7-155886.37" + wire $0\logical_op__oe__oe$35[0:0]$9094 + attribute \src "issuer_ls180.v:156186.3-156229.6" + wire $0\logical_op__oe__ok$36$next[0:0]$8963 + attribute \src "issuer_ls180.v:156039.3-156040.61" + wire $0\logical_op__oe__ok$36[0:0]$8905 + attribute \src "issuer_ls180.v:155894.7-155894.37" + wire $0\logical_op__oe__ok$36[0:0]$9096 + attribute \src "issuer_ls180.v:156186.3-156229.6" + wire $0\logical_op__output_carry$42$next[0:0]$8964 + attribute \src "issuer_ls180.v:156051.3-156052.73" + wire $0\logical_op__output_carry$42[0:0]$8917 + attribute \src "issuer_ls180.v:155904.7-155904.43" + wire $0\logical_op__output_carry$42[0:0]$9098 + attribute \src "issuer_ls180.v:156186.3-156229.6" + wire $0\logical_op__rc__ok$34$next[0:0]$8965 + attribute \src "issuer_ls180.v:156035.3-156036.61" + wire $0\logical_op__rc__ok$34[0:0]$8901 + attribute \src "issuer_ls180.v:155910.7-155910.37" + wire $0\logical_op__rc__ok$34[0:0]$9100 + attribute \src "issuer_ls180.v:156186.3-156229.6" + wire $0\logical_op__rc__rc$33$next[0:0]$8966 + attribute \src "issuer_ls180.v:156033.3-156034.61" + wire $0\logical_op__rc__rc$33[0:0]$8899 + attribute \src "issuer_ls180.v:155918.7-155918.37" + wire $0\logical_op__rc__rc$33[0:0]$9102 + attribute \src "issuer_ls180.v:156186.3-156229.6" + wire $0\logical_op__write_cr0$41$next[0:0]$8967 + attribute \src "issuer_ls180.v:156049.3-156050.67" + wire $0\logical_op__write_cr0$41[0:0]$8915 + attribute \src "issuer_ls180.v:155928.7-155928.40" + wire $0\logical_op__write_cr0$41[0:0]$9104 + attribute \src "issuer_ls180.v:156186.3-156229.6" + wire $0\logical_op__zero_a$38$next[0:0]$8968 + attribute \src "issuer_ls180.v:156043.3-156044.61" + wire $0\logical_op__zero_a$38[0:0]$8909 + attribute \src "issuer_ls180.v:155936.7-155936.37" + wire $0\logical_op__zero_a$38[0:0]$9106 + attribute \src "issuer_ls180.v:156171.3-156185.6" + wire width 2 $0\muxid$28$next[1:0]$8947 + attribute \src "issuer_ls180.v:156061.3-156062.35" + wire width 2 $0\muxid$28[1:0]$8927 + attribute \src "issuer_ls180.v:155944.13-155944.30" + wire width 2 $0\muxid$28[1:0]$9108 + attribute \src "issuer_ls180.v:156380.3-156394.6" + wire width 2 $0\operation$69$next[1:0]$9052 + attribute \src "issuer_ls180.v:156003.3-156004.43" + wire width 2 $0\operation$69[1:0]$8869 + attribute \src "issuer_ls180.v:155954.13-155954.34" + wire width 2 $0\operation$69[1:0]$9110 + attribute \src "issuer_ls180.v:156230.3-156244.6" + wire width 64 $0\ra$47$next[63:0]$9012 + attribute \src "issuer_ls180.v:156023.3-156024.29" + wire width 64 $0\ra$47[63:0]$8889 + attribute \src "issuer_ls180.v:155968.14-155968.44" + wire width 64 $0\ra$47[63:0]$9112 + attribute \src "issuer_ls180.v:156245.3-156259.6" + wire width 64 $0\rb$48$next[63:0]$9016 + attribute \src "issuer_ls180.v:156021.3-156022.29" + wire width 64 $0\rb$48[63:0]$8887 + attribute \src "issuer_ls180.v:155976.14-155976.44" + wire width 64 $0\rb$48[63:0]$9114 + attribute \src "issuer_ls180.v:156098.3-156106.6" + wire width 128 $0\saved_state_dividend_quotient$next[127:0]$8935 + attribute \src "issuer_ls180.v:156065.3-156066.75" + wire width 128 $0\saved_state_dividend_quotient[127:0] + attribute \src "issuer_ls180.v:156089.3-156097.6" + wire width 7 $0\saved_state_q_bits_known$next[6:0]$8932 + attribute \src "issuer_ls180.v:156067.3-156068.65" + wire width 7 $0\saved_state_q_bits_known[6:0] + attribute \src "issuer_ls180.v:156260.3-156274.6" + wire $0\xer_so$49$next[0:0]$9020 + attribute \src "issuer_ls180.v:156019.3-156020.37" + wire $0\xer_so$49[0:0]$8885 + attribute \src "issuer_ls180.v:155994.7-155994.25" + wire $0\xer_so$49[0:0]$9118 + attribute \src "issuer_ls180.v:156335.3-156349.6" + wire $1\div_by_zero$54$next[0:0]$9041 + attribute \src "issuer_ls180.v:156131.3-156142.6" + wire width 64 $1\div_state_next_divisor[63:0] + attribute \src "issuer_ls180.v:156119.3-156130.6" + wire width 128 $1\div_state_next_i_dividend_quotient[127:0] + attribute \src "issuer_ls180.v:156107.3-156118.6" + wire width 7 $1\div_state_next_i_q_bits_known[6:0] + attribute \src "issuer_ls180.v:156305.3-156319.6" + wire $1\dive_abs_ov32$52$next[0:0]$9033 + attribute \src "issuer_ls180.v:156320.3-156334.6" + wire $1\dive_abs_ov64$53$next[0:0]$9037 + attribute \src "issuer_ls180.v:156350.3-156364.6" + wire width 128 $1\dividend$68$next[127:0]$9045 + attribute \src "issuer_ls180.v:156290.3-156304.6" + wire $1\dividend_neg$51$next[0:0]$9029 + attribute \src "issuer_ls180.v:156275.3-156289.6" + wire $1\divisor_neg$50$next[0:0]$9025 + attribute \src "issuer_ls180.v:156365.3-156379.6" + wire width 64 $1\divisor_radicand$65$next[63:0]$9049 + attribute \src "issuer_ls180.v:156143.3-156170.6" + wire $1\empty$next[0:0]$8942 + attribute \src "issuer_ls180.v:155519.7-155519.19" + wire $1\empty[0:0] + attribute \src "issuer_ls180.v:156186.3-156229.6" + wire width 4 $1\logical_op__data_len$45$next[3:0]$8969 + attribute \src "issuer_ls180.v:156186.3-156229.6" + wire width 12 $1\logical_op__fn_unit$30$next[11:0]$8970 + attribute \src "issuer_ls180.v:156186.3-156229.6" + wire width 64 $1\logical_op__imm_data__data$31$next[63:0]$8971 + attribute \src "issuer_ls180.v:156186.3-156229.6" + wire $1\logical_op__imm_data__ok$32$next[0:0]$8972 + attribute \src "issuer_ls180.v:156186.3-156229.6" + wire width 2 $1\logical_op__input_carry$39$next[1:0]$8973 + attribute \src "issuer_ls180.v:156186.3-156229.6" + wire width 32 $1\logical_op__insn$46$next[31:0]$8974 + attribute \src "issuer_ls180.v:156186.3-156229.6" + wire width 7 $1\logical_op__insn_type$29$next[6:0]$8975 + attribute \src "issuer_ls180.v:156186.3-156229.6" + wire $1\logical_op__invert_in$37$next[0:0]$8976 + attribute \src "issuer_ls180.v:156186.3-156229.6" + wire $1\logical_op__invert_out$40$next[0:0]$8977 + attribute \src "issuer_ls180.v:156186.3-156229.6" + wire $1\logical_op__is_32bit$43$next[0:0]$8978 + attribute \src "issuer_ls180.v:156186.3-156229.6" + wire $1\logical_op__is_signed$44$next[0:0]$8979 + attribute \src "issuer_ls180.v:156186.3-156229.6" + wire $1\logical_op__oe__oe$35$next[0:0]$8980 + attribute \src "issuer_ls180.v:156186.3-156229.6" + wire $1\logical_op__oe__ok$36$next[0:0]$8981 + attribute \src "issuer_ls180.v:156186.3-156229.6" + wire $1\logical_op__output_carry$42$next[0:0]$8982 + attribute \src "issuer_ls180.v:156186.3-156229.6" + wire $1\logical_op__rc__ok$34$next[0:0]$8983 + attribute \src "issuer_ls180.v:156186.3-156229.6" + wire $1\logical_op__rc__rc$33$next[0:0]$8984 + attribute \src "issuer_ls180.v:156186.3-156229.6" + wire $1\logical_op__write_cr0$41$next[0:0]$8985 + attribute \src "issuer_ls180.v:156186.3-156229.6" + wire $1\logical_op__zero_a$38$next[0:0]$8986 + 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$and$issuer_ls180.v:156002$8867_Y + attribute \src "issuer_ls180.v:156000.18-156000.124" + wire $eq$issuer_ls180.v:156000$8865_Y + attribute \src "issuer_ls180.v:155998.18-155998.92" + wire width 192 $extend$issuer_ls180.v:155998$8862_Y + attribute \src "issuer_ls180.v:155999.18-155999.93" + wire $not$issuer_ls180.v:155999$8864_Y + attribute \src "issuer_ls180.v:155998.18-155998.92" + wire width 192 $pos$issuer_ls180.v:155998$8863_Y + attribute \src "issuer_ls180.v:155997.18-155997.138" + wire width 191 $sshl$issuer_ls180.v:155997$8861_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:162" + wire width 192 \$55 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:162" + wire width 191 \$56 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:163" + wire \$59 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:109" + wire \$61 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:163" + wire \$63 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:177" + wire \$66 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" + wire input 65 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" + wire input 1 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire input 30 \div_by_zero + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire output 62 \div_by_zero$27 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire \div_by_zero$54 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire \div_by_zero$54$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:89" + wire width 128 \div_state_init_dividend + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:105" + wire width 128 \div_state_init_o_dividend_quotient + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:103" + wire width 7 \div_state_init_o_q_bits_known + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:59" + wire width 64 \div_state_next_divisor + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:105" + wire width 128 \div_state_next_i_dividend_quotient + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:103" + wire width 7 \div_state_next_i_q_bits_known + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:105" + wire width 128 \div_state_next_o_dividend_quotient + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:103" + wire width 7 \div_state_next_o_q_bits_known + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire input 28 \dive_abs_ov32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire output 60 \dive_abs_ov32$25 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire \dive_abs_ov32$52 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire \dive_abs_ov32$52$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire input 29 \dive_abs_ov64 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire output 61 \dive_abs_ov64$26 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire \dive_abs_ov64$53 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire \dive_abs_ov64$53$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:18" + wire width 128 input 31 \dividend + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:18" + wire width 128 \dividend$68 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:18" + wire width 128 \dividend$68$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire input 27 \dividend_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire output 59 \dividend_neg$24 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire \dividend_neg$51 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire \dividend_neg$51$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire input 26 \divisor_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire output 58 \divisor_neg$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire \divisor_neg$50 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire \divisor_neg$50$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:19" + wire width 64 input 32 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:19" + wire width 64 \divisor_radicand$65 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:19" + wire width 64 \divisor_radicand$65$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:133" + wire \empty + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:133" + wire \empty$next + attribute \src "issuer_ls180.v:155433.7-155433.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 input 21 \logical_op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 output 53 \logical_op__data_len$18 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \logical_op__data_len$45 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \logical_op__data_len$45$next + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 input 6 \logical_op__fn_unit + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 output 38 \logical_op__fn_unit$3 + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 \logical_op__fn_unit$30 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 \logical_op__fn_unit$30$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 input 7 \logical_op__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \logical_op__imm_data__data$31 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \logical_op__imm_data__data$31$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 output 39 \logical_op__imm_data__data$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 8 \logical_op__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__imm_data__ok$32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__imm_data__ok$32$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 40 \logical_op__imm_data__ok$5 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 input 15 \logical_op__input_carry + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 output 47 \logical_op__input_carry$12 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \logical_op__input_carry$39 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \logical_op__input_carry$39$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 22 \logical_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 output 54 \logical_op__insn$19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \logical_op__insn$46 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \logical_op__insn$46$next + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 input 5 \logical_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 output 37 \logical_op__insn_type$2 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \logical_op__insn_type$29 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \logical_op__insn_type$29$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 13 \logical_op__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 45 \logical_op__invert_in$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__invert_in$37 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__invert_in$37$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 16 \logical_op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 48 \logical_op__invert_out$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__invert_out$40 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__invert_out$40$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 19 \logical_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 51 \logical_op__is_32bit$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__is_32bit$43 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__is_32bit$43$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 20 \logical_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 52 \logical_op__is_signed$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__is_signed$44 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__is_signed$44$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 11 \logical_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__oe__oe$35 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__oe__oe$35$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 43 \logical_op__oe__oe$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 12 \logical_op__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__oe__ok$36 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__oe__ok$36$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 44 \logical_op__oe__ok$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 18 \logical_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 50 \logical_op__output_carry$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__output_carry$42 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__output_carry$42$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 10 \logical_op__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__rc__ok$34 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__rc__ok$34$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 42 \logical_op__rc__ok$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 9 \logical_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__rc__rc$33 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__rc__rc$33$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 41 \logical_op__rc__rc$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 17 \logical_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 49 \logical_op__write_cr0$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__write_cr0$41 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__write_cr0$41$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 14 \logical_op__zero_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 46 \logical_op__zero_a$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__zero_a$38 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__zero_a$38$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 input 4 \muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 output 36 \muxid$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \muxid$28 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \muxid$28$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" + wire input 35 \n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" + wire output 34 \n_valid_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:21" + wire width 2 input 33 \operation + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:21" + wire width 2 \operation$69 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:21" + wire width 2 \operation$69$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" + wire output 3 \p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" + wire input 2 \p_valid_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:40" + wire width 64 output 63 \quotient_root + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 23 \ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 output 55 \ra$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \ra$47 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \ra$47$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 24 \rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 output 56 \rb$21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \rb$48 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \rb$48$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:41" + wire width 192 output 64 \remainder + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:105" + wire width 128 \saved_state_dividend_quotient + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:105" + wire width 128 \saved_state_dividend_quotient$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:103" + wire width 7 \saved_state_q_bits_known + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:103" + wire width 7 \saved_state_q_bits_known$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire input 25 \xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire output 57 \xer_so$22 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire \xer_so$49 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire \xer_so$49$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:163" + cell $and $and$issuer_ls180.v:156001$8866 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$59 + connect \B \$61 + connect \Y $and$issuer_ls180.v:156001$8866_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:177" + cell $and $and$issuer_ls180.v:156002$8867 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \n_ready_i + connect \B \n_valid_o + connect \Y $and$issuer_ls180.v:156002$8867_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:109" + cell $eq $eq$issuer_ls180.v:156000$8865 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \div_state_next_o_q_bits_known + connect \B 7'1000000 + connect \Y $eq$issuer_ls180.v:156000$8865_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:162" + cell $pos $extend$issuer_ls180.v:155998$8862 + parameter \A_SIGNED 0 + parameter \A_WIDTH 191 + parameter \Y_WIDTH 192 + connect \A \$56 + connect \Y $extend$issuer_ls180.v:155998$8862_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:163" + cell $not $not$issuer_ls180.v:155999$8864 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \empty + connect \Y $not$issuer_ls180.v:155999$8864_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:162" + cell $pos $pos$issuer_ls180.v:155998$8863 + parameter \A_SIGNED 0 + parameter \A_WIDTH 192 + parameter \Y_WIDTH 192 + connect \A $extend$issuer_ls180.v:155998$8862_Y + connect \Y $pos$issuer_ls180.v:155998$8863_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:162" + cell $sshl $sshl$issuer_ls180.v:155997$8861 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 191 + connect \A \div_state_next_o_dividend_quotient [127:64] + connect \B 7'1000000 + connect \Y $sshl$issuer_ls180.v:155997$8861_Y + end + attribute \module_not_derived 1 + attribute \src "issuer_ls180.v:156069.18-156073.4" + cell \div_state_init \div_state_init + connect \dividend \div_state_init_dividend + connect \o_dividend_quotient \div_state_init_o_dividend_quotient + connect \o_q_bits_known \div_state_init_o_q_bits_known + end + attribute \module_not_derived 1 + attribute \src "issuer_ls180.v:156074.18-156080.4" + cell \div_state_next \div_state_next + connect \divisor \div_state_next_divisor + connect \i_dividend_quotient \div_state_next_i_dividend_quotient + connect \i_q_bits_known \div_state_next_i_q_bits_known + connect \o_dividend_quotient \div_state_next_o_dividend_quotient + connect \o_q_bits_known \div_state_next_o_q_bits_known + end + attribute \module_not_derived 1 + attribute \src "issuer_ls180.v:156081.10-156084.4" + cell \n$77 \n + connect \n_ready_i \n_ready_i + connect \n_valid_o \n_valid_o + end + attribute \module_not_derived 1 + attribute \src "issuer_ls180.v:156085.10-156088.4" + cell \p$76 \p + connect \p_ready_o \p_ready_o + connect \p_valid_i \p_valid_i + end + attribute \src "issuer_ls180.v:155433.7-155433.20" + process $proc$issuer_ls180.v:155433$9055 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "issuer_ls180.v:155455.7-155455.30" + process $proc$issuer_ls180.v:155455$9056 + assign { } { } + assign $0\div_by_zero$54[0:0]$9057 1'0 + sync always + sync init + update \div_by_zero$54 $0\div_by_zero$54[0:0]$9057 + end + attribute \src "issuer_ls180.v:155479.7-155479.32" + process $proc$issuer_ls180.v:155479$9058 + assign { } { } + assign $0\dive_abs_ov32$52[0:0]$9059 1'0 + sync always + sync init + update \dive_abs_ov32$52 $0\dive_abs_ov32$52[0:0]$9059 + end + attribute \src "issuer_ls180.v:155487.7-155487.32" + process $proc$issuer_ls180.v:155487$9060 + assign { } { } + assign $0\dive_abs_ov64$53[0:0]$9061 1'0 + sync always + sync init + update \dive_abs_ov64$53 $0\dive_abs_ov64$53[0:0]$9061 + end + attribute \src "issuer_ls180.v:155493.15-155493.68" + process $proc$issuer_ls180.v:155493$9062 + assign { } { } + assign $0\dividend$68[127:0]$9063 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \dividend$68 $0\dividend$68[127:0]$9063 + end + attribute \src "issuer_ls180.v:155501.7-155501.31" + process $proc$issuer_ls180.v:155501$9064 + assign { } { } + assign $0\dividend_neg$51[0:0]$9065 1'0 + sync always + sync init + update \dividend_neg$51 $0\dividend_neg$51[0:0]$9065 + end + attribute \src "issuer_ls180.v:155509.7-155509.30" + process $proc$issuer_ls180.v:155509$9066 + assign { } { } + assign $0\divisor_neg$50[0:0]$9067 1'0 + sync always + sync init + update \divisor_neg$50 $0\divisor_neg$50[0:0]$9067 + end + attribute \src "issuer_ls180.v:155515.14-155515.58" + process $proc$issuer_ls180.v:155515$9068 + assign { } { } + assign $0\divisor_radicand$65[63:0]$9069 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \divisor_radicand$65 $0\divisor_radicand$65[63:0]$9069 + end + attribute \src "issuer_ls180.v:155519.7-155519.19" + process $proc$issuer_ls180.v:155519$9070 + assign { } { } + assign $1\empty[0:0] 1'1 + sync always + sync init + update \empty $1\empty[0:0] + end + attribute \src "issuer_ls180.v:155527.13-155527.45" + process $proc$issuer_ls180.v:155527$9071 + assign { } { } + assign $0\logical_op__data_len$45[3:0]$9072 4'0000 + sync always + sync init + update \logical_op__data_len$45 $0\logical_op__data_len$45[3:0]$9072 + end + attribute \src "issuer_ls180.v:155574.14-155574.48" + process $proc$issuer_ls180.v:155574$9073 + assign { } { } + assign $0\logical_op__fn_unit$30[11:0]$9074 12'000000000000 + sync always + sync init + update \logical_op__fn_unit$30 $0\logical_op__fn_unit$30[11:0]$9074 + end + attribute \src "issuer_ls180.v:155580.14-155580.68" + process $proc$issuer_ls180.v:155580$9075 + assign { } { } + assign $0\logical_op__imm_data__data$31[63:0]$9076 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \logical_op__imm_data__data$31 $0\logical_op__imm_data__data$31[63:0]$9076 + end + attribute \src "issuer_ls180.v:155588.7-155588.43" + process $proc$issuer_ls180.v:155588$9077 + assign { } { } + assign $0\logical_op__imm_data__ok$32[0:0]$9078 1'0 + sync always + sync init + update \logical_op__imm_data__ok$32 $0\logical_op__imm_data__ok$32[0:0]$9078 + end + attribute \src "issuer_ls180.v:155610.13-155610.48" + process $proc$issuer_ls180.v:155610$9079 + assign { } { } + assign $0\logical_op__input_carry$39[1:0]$9080 2'00 + sync always + sync init + update \logical_op__input_carry$39 $0\logical_op__input_carry$39[1:0]$9080 + end + attribute \src "issuer_ls180.v:155618.14-155618.43" + process $proc$issuer_ls180.v:155618$9081 + assign { } { } + assign $0\logical_op__insn$46[31:0]$9082 0 + sync always + sync init + update \logical_op__insn$46 $0\logical_op__insn$46[31:0]$9082 + end + attribute \src "issuer_ls180.v:155848.13-155848.47" + process $proc$issuer_ls180.v:155848$9083 + assign { } { } + assign $0\logical_op__insn_type$29[6:0]$9084 7'0000000 + sync always + sync init + update \logical_op__insn_type$29 $0\logical_op__insn_type$29[6:0]$9084 + end + attribute \src "issuer_ls180.v:155856.7-155856.40" + process $proc$issuer_ls180.v:155856$9085 + assign { } { } + assign $0\logical_op__invert_in$37[0:0]$9086 1'0 + sync always + sync init + update \logical_op__invert_in$37 $0\logical_op__invert_in$37[0:0]$9086 + end + attribute \src "issuer_ls180.v:155864.7-155864.41" + process $proc$issuer_ls180.v:155864$9087 + assign { } { } + assign $0\logical_op__invert_out$40[0:0]$9088 1'0 + sync always + sync init + update \logical_op__invert_out$40 $0\logical_op__invert_out$40[0:0]$9088 + end + attribute \src "issuer_ls180.v:155872.7-155872.39" + process $proc$issuer_ls180.v:155872$9089 + assign { } { } + assign $0\logical_op__is_32bit$43[0:0]$9090 1'0 + sync always + sync init + update \logical_op__is_32bit$43 $0\logical_op__is_32bit$43[0:0]$9090 + end + attribute \src "issuer_ls180.v:155880.7-155880.40" + process $proc$issuer_ls180.v:155880$9091 + assign { } { } + assign $0\logical_op__is_signed$44[0:0]$9092 1'0 + sync always + sync init + update \logical_op__is_signed$44 $0\logical_op__is_signed$44[0:0]$9092 + end + attribute \src "issuer_ls180.v:155886.7-155886.37" + process $proc$issuer_ls180.v:155886$9093 + assign { } { } + assign $0\logical_op__oe__oe$35[0:0]$9094 1'0 + sync always + sync init + update \logical_op__oe__oe$35 $0\logical_op__oe__oe$35[0:0]$9094 + end + attribute \src "issuer_ls180.v:155894.7-155894.37" + process $proc$issuer_ls180.v:155894$9095 + assign { } { } + assign $0\logical_op__oe__ok$36[0:0]$9096 1'0 + sync always + sync init + update \logical_op__oe__ok$36 $0\logical_op__oe__ok$36[0:0]$9096 + end + attribute \src "issuer_ls180.v:155904.7-155904.43" + process $proc$issuer_ls180.v:155904$9097 + assign { } { } + assign $0\logical_op__output_carry$42[0:0]$9098 1'0 + sync always + sync init + update \logical_op__output_carry$42 $0\logical_op__output_carry$42[0:0]$9098 + end + attribute \src "issuer_ls180.v:155910.7-155910.37" + process $proc$issuer_ls180.v:155910$9099 + assign { } { } + assign $0\logical_op__rc__ok$34[0:0]$9100 1'0 + sync always + sync init + update \logical_op__rc__ok$34 $0\logical_op__rc__ok$34[0:0]$9100 + end + attribute \src "issuer_ls180.v:155918.7-155918.37" + process $proc$issuer_ls180.v:155918$9101 + assign { } { } + assign $0\logical_op__rc__rc$33[0:0]$9102 1'0 + sync always + sync init + update \logical_op__rc__rc$33 $0\logical_op__rc__rc$33[0:0]$9102 + end + attribute \src "issuer_ls180.v:155928.7-155928.40" + process $proc$issuer_ls180.v:155928$9103 + assign { } { } + assign $0\logical_op__write_cr0$41[0:0]$9104 1'0 + sync always + sync init + update \logical_op__write_cr0$41 $0\logical_op__write_cr0$41[0:0]$9104 + end + attribute \src "issuer_ls180.v:155936.7-155936.37" + process $proc$issuer_ls180.v:155936$9105 + assign { } { } + assign $0\logical_op__zero_a$38[0:0]$9106 1'0 + sync always + sync init + update \logical_op__zero_a$38 $0\logical_op__zero_a$38[0:0]$9106 + end + attribute \src "issuer_ls180.v:155944.13-155944.30" + process $proc$issuer_ls180.v:155944$9107 + assign { } { } + assign $0\muxid$28[1:0]$9108 2'00 + sync always + sync init + update \muxid$28 $0\muxid$28[1:0]$9108 + end + attribute \src "issuer_ls180.v:155954.13-155954.34" + process $proc$issuer_ls180.v:155954$9109 + assign { } { } + assign $0\operation$69[1:0]$9110 2'00 + sync always + sync init + update \operation$69 $0\operation$69[1:0]$9110 + end + attribute \src "issuer_ls180.v:155968.14-155968.44" + process $proc$issuer_ls180.v:155968$9111 + assign { } { } + assign $0\ra$47[63:0]$9112 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \ra$47 $0\ra$47[63:0]$9112 + end + attribute \src "issuer_ls180.v:155976.14-155976.44" + process $proc$issuer_ls180.v:155976$9113 + assign { } { } + assign $0\rb$48[63:0]$9114 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \rb$48 $0\rb$48[63:0]$9114 + end + attribute \src "issuer_ls180.v:155982.15-155982.84" + process $proc$issuer_ls180.v:155982$9115 + assign { } { } + assign $1\saved_state_dividend_quotient[127:0] 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \saved_state_dividend_quotient $1\saved_state_dividend_quotient[127:0] + end + attribute \src "issuer_ls180.v:155986.13-155986.45" + process $proc$issuer_ls180.v:155986$9116 + assign { } { } + assign $1\saved_state_q_bits_known[6:0] 7'0000000 + sync always + sync init + update \saved_state_q_bits_known $1\saved_state_q_bits_known[6:0] + end + attribute \src "issuer_ls180.v:155994.7-155994.25" + process $proc$issuer_ls180.v:155994$9117 + assign { } { } + assign $0\xer_so$49[0:0]$9118 1'0 + sync always + sync init + update \xer_so$49 $0\xer_so$49[0:0]$9118 + end + attribute \src "issuer_ls180.v:156003.3-156004.43" + process $proc$issuer_ls180.v:156003$8868 + assign { } { } + assign $0\operation$69[1:0]$8869 \operation$69$next + sync posedge \coresync_clk + update \operation$69 $0\operation$69[1:0]$8869 + end + attribute \src "issuer_ls180.v:156005.3-156006.57" + process $proc$issuer_ls180.v:156005$8870 + assign { } { } + assign $0\divisor_radicand$65[63:0]$8871 \divisor_radicand$65$next + sync posedge \coresync_clk + update \divisor_radicand$65 $0\divisor_radicand$65[63:0]$8871 + end + attribute \src "issuer_ls180.v:156007.3-156008.41" + process $proc$issuer_ls180.v:156007$8872 + assign { } { } + assign $0\dividend$68[127:0]$8873 \dividend$68$next + sync posedge \coresync_clk + update \dividend$68 $0\dividend$68[127:0]$8873 + end + attribute \src "issuer_ls180.v:156009.3-156010.47" + process $proc$issuer_ls180.v:156009$8874 + assign { } { } + assign $0\div_by_zero$54[0:0]$8875 \div_by_zero$54$next + sync posedge \coresync_clk + update \div_by_zero$54 $0\div_by_zero$54[0:0]$8875 + end + attribute \src "issuer_ls180.v:156011.3-156012.51" + process $proc$issuer_ls180.v:156011$8876 + assign { } { } + assign $0\dive_abs_ov64$53[0:0]$8877 \dive_abs_ov64$53$next + sync posedge \coresync_clk + update \dive_abs_ov64$53 $0\dive_abs_ov64$53[0:0]$8877 + end + attribute \src "issuer_ls180.v:156013.3-156014.51" + process $proc$issuer_ls180.v:156013$8878 + assign { } { } + assign $0\dive_abs_ov32$52[0:0]$8879 \dive_abs_ov32$52$next + sync posedge \coresync_clk + update \dive_abs_ov32$52 $0\dive_abs_ov32$52[0:0]$8879 + end + attribute \src "issuer_ls180.v:156015.3-156016.49" + process $proc$issuer_ls180.v:156015$8880 + assign { } { } + assign $0\dividend_neg$51[0:0]$8881 \dividend_neg$51$next + sync posedge \coresync_clk + update \dividend_neg$51 $0\dividend_neg$51[0:0]$8881 + end + attribute \src "issuer_ls180.v:156017.3-156018.47" + process $proc$issuer_ls180.v:156017$8882 + assign { } { } + assign $0\divisor_neg$50[0:0]$8883 \divisor_neg$50$next + sync posedge \coresync_clk + update \divisor_neg$50 $0\divisor_neg$50[0:0]$8883 + end + attribute \src "issuer_ls180.v:156019.3-156020.37" + process $proc$issuer_ls180.v:156019$8884 + assign { } { } + assign $0\xer_so$49[0:0]$8885 \xer_so$49$next + sync posedge \coresync_clk + update \xer_so$49 $0\xer_so$49[0:0]$8885 + end + attribute \src "issuer_ls180.v:156021.3-156022.29" + process $proc$issuer_ls180.v:156021$8886 + assign { } { } + assign $0\rb$48[63:0]$8887 \rb$48$next + sync posedge \coresync_clk + update \rb$48 $0\rb$48[63:0]$8887 + end + attribute \src "issuer_ls180.v:156023.3-156024.29" + process $proc$issuer_ls180.v:156023$8888 + assign { } { } + assign $0\ra$47[63:0]$8889 \ra$47$next + sync posedge \coresync_clk + update \ra$47 $0\ra$47[63:0]$8889 + end + attribute \src "issuer_ls180.v:156025.3-156026.67" + process $proc$issuer_ls180.v:156025$8890 + assign { } { } + assign $0\logical_op__insn_type$29[6:0]$8891 \logical_op__insn_type$29$next + sync posedge \coresync_clk + update \logical_op__insn_type$29 $0\logical_op__insn_type$29[6:0]$8891 + end + attribute \src "issuer_ls180.v:156027.3-156028.63" + process $proc$issuer_ls180.v:156027$8892 + assign { } { } + assign $0\logical_op__fn_unit$30[11:0]$8893 \logical_op__fn_unit$30$next + sync posedge \coresync_clk + update \logical_op__fn_unit$30 $0\logical_op__fn_unit$30[11:0]$8893 + end + attribute \src "issuer_ls180.v:156029.3-156030.77" + process $proc$issuer_ls180.v:156029$8894 + assign { } { } + assign $0\logical_op__imm_data__data$31[63:0]$8895 \logical_op__imm_data__data$31$next + sync posedge \coresync_clk + update \logical_op__imm_data__data$31 $0\logical_op__imm_data__data$31[63:0]$8895 + end + attribute \src "issuer_ls180.v:156031.3-156032.73" + process $proc$issuer_ls180.v:156031$8896 + assign { } { } + assign $0\logical_op__imm_data__ok$32[0:0]$8897 \logical_op__imm_data__ok$32$next + sync posedge \coresync_clk + update \logical_op__imm_data__ok$32 $0\logical_op__imm_data__ok$32[0:0]$8897 + end + attribute \src "issuer_ls180.v:156033.3-156034.61" + process $proc$issuer_ls180.v:156033$8898 + assign { } { } + assign $0\logical_op__rc__rc$33[0:0]$8899 \logical_op__rc__rc$33$next + sync posedge \coresync_clk + update \logical_op__rc__rc$33 $0\logical_op__rc__rc$33[0:0]$8899 + end + attribute \src "issuer_ls180.v:156035.3-156036.61" + process $proc$issuer_ls180.v:156035$8900 + assign { } { } + assign $0\logical_op__rc__ok$34[0:0]$8901 \logical_op__rc__ok$34$next + sync posedge \coresync_clk + update \logical_op__rc__ok$34 $0\logical_op__rc__ok$34[0:0]$8901 + end + attribute \src "issuer_ls180.v:156037.3-156038.61" + process $proc$issuer_ls180.v:156037$8902 + assign { } { } + assign $0\logical_op__oe__oe$35[0:0]$8903 \logical_op__oe__oe$35$next + sync posedge \coresync_clk + update \logical_op__oe__oe$35 $0\logical_op__oe__oe$35[0:0]$8903 + end + attribute \src "issuer_ls180.v:156039.3-156040.61" + process $proc$issuer_ls180.v:156039$8904 + assign { } { } + assign $0\logical_op__oe__ok$36[0:0]$8905 \logical_op__oe__ok$36$next + sync posedge \coresync_clk + update \logical_op__oe__ok$36 $0\logical_op__oe__ok$36[0:0]$8905 + end + attribute \src "issuer_ls180.v:156041.3-156042.67" + process $proc$issuer_ls180.v:156041$8906 + assign { } { } + assign $0\logical_op__invert_in$37[0:0]$8907 \logical_op__invert_in$37$next + sync posedge \coresync_clk + update \logical_op__invert_in$37 $0\logical_op__invert_in$37[0:0]$8907 + end + attribute \src "issuer_ls180.v:156043.3-156044.61" + process $proc$issuer_ls180.v:156043$8908 + assign { } { } + assign $0\logical_op__zero_a$38[0:0]$8909 \logical_op__zero_a$38$next + sync posedge \coresync_clk + update \logical_op__zero_a$38 $0\logical_op__zero_a$38[0:0]$8909 + end + attribute \src "issuer_ls180.v:156045.3-156046.71" + process $proc$issuer_ls180.v:156045$8910 + assign { } { } + assign $0\logical_op__input_carry$39[1:0]$8911 \logical_op__input_carry$39$next + sync posedge \coresync_clk + update \logical_op__input_carry$39 $0\logical_op__input_carry$39[1:0]$8911 + end + attribute \src "issuer_ls180.v:156047.3-156048.69" + process $proc$issuer_ls180.v:156047$8912 + assign { } { } + assign $0\logical_op__invert_out$40[0:0]$8913 \logical_op__invert_out$40$next + sync posedge \coresync_clk + update \logical_op__invert_out$40 $0\logical_op__invert_out$40[0:0]$8913 + end + attribute \src "issuer_ls180.v:156049.3-156050.67" + process $proc$issuer_ls180.v:156049$8914 + assign { } { } + assign $0\logical_op__write_cr0$41[0:0]$8915 \logical_op__write_cr0$41$next + sync posedge \coresync_clk + update \logical_op__write_cr0$41 $0\logical_op__write_cr0$41[0:0]$8915 + end + attribute \src "issuer_ls180.v:156051.3-156052.73" + process $proc$issuer_ls180.v:156051$8916 + assign { } { } + assign $0\logical_op__output_carry$42[0:0]$8917 \logical_op__output_carry$42$next + sync posedge \coresync_clk + update \logical_op__output_carry$42 $0\logical_op__output_carry$42[0:0]$8917 + end + attribute \src "issuer_ls180.v:156053.3-156054.65" + process $proc$issuer_ls180.v:156053$8918 + assign { } { } + assign $0\logical_op__is_32bit$43[0:0]$8919 \logical_op__is_32bit$43$next + sync posedge \coresync_clk + update \logical_op__is_32bit$43 $0\logical_op__is_32bit$43[0:0]$8919 + end + attribute \src "issuer_ls180.v:156055.3-156056.67" + process $proc$issuer_ls180.v:156055$8920 + assign { } { } + assign $0\logical_op__is_signed$44[0:0]$8921 \logical_op__is_signed$44$next + sync posedge \coresync_clk + update \logical_op__is_signed$44 $0\logical_op__is_signed$44[0:0]$8921 + end + attribute \src "issuer_ls180.v:156057.3-156058.65" + process $proc$issuer_ls180.v:156057$8922 + assign { } { } + assign $0\logical_op__data_len$45[3:0]$8923 \logical_op__data_len$45$next + sync posedge \coresync_clk + update \logical_op__data_len$45 $0\logical_op__data_len$45[3:0]$8923 + end + attribute \src "issuer_ls180.v:156059.3-156060.57" + process $proc$issuer_ls180.v:156059$8924 + assign { } { } + assign $0\logical_op__insn$46[31:0]$8925 \logical_op__insn$46$next + sync posedge \coresync_clk + update \logical_op__insn$46 $0\logical_op__insn$46[31:0]$8925 + end + attribute \src "issuer_ls180.v:156061.3-156062.35" + process $proc$issuer_ls180.v:156061$8926 + assign { } { } + assign $0\muxid$28[1:0]$8927 \muxid$28$next + sync posedge \coresync_clk + update \muxid$28 $0\muxid$28[1:0]$8927 + end + attribute \src "issuer_ls180.v:156063.3-156064.27" + process $proc$issuer_ls180.v:156063$8928 + assign { } { } + assign $0\empty[0:0] \empty$next + sync posedge \coresync_clk + update \empty $0\empty[0:0] + end + attribute \src "issuer_ls180.v:156065.3-156066.75" + process $proc$issuer_ls180.v:156065$8929 + assign { } { } + assign $0\saved_state_dividend_quotient[127:0] \saved_state_dividend_quotient$next + sync posedge \coresync_clk + update \saved_state_dividend_quotient $0\saved_state_dividend_quotient[127:0] + end + attribute \src "issuer_ls180.v:156067.3-156068.65" + process $proc$issuer_ls180.v:156067$8930 + assign { } { } + assign $0\saved_state_q_bits_known[6:0] \saved_state_q_bits_known$next + sync posedge \coresync_clk + update \saved_state_q_bits_known $0\saved_state_q_bits_known[6:0] + end + attribute \src "issuer_ls180.v:156089.3-156097.6" + process $proc$issuer_ls180.v:156089$8931 + assign { } { } + assign { } { } + assign $0\saved_state_q_bits_known$next[6:0]$8932 $1\saved_state_q_bits_known$next[6:0]$8933 + attribute \src "issuer_ls180.v:156090.5-156090.29" + switch \initial + attribute \src "issuer_ls180.v:156090.9-156090.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\saved_state_q_bits_known$next[6:0]$8933 7'0000000 + case + assign $1\saved_state_q_bits_known$next[6:0]$8933 \div_state_next_o_q_bits_known + end + sync always + update \saved_state_q_bits_known$next $0\saved_state_q_bits_known$next[6:0]$8932 + end + attribute \src "issuer_ls180.v:156098.3-156106.6" + process $proc$issuer_ls180.v:156098$8934 + assign { } { } + assign { } { } + assign $0\saved_state_dividend_quotient$next[127:0]$8935 $1\saved_state_dividend_quotient$next[127:0]$8936 + attribute \src "issuer_ls180.v:156099.5-156099.29" + switch \initial + attribute \src "issuer_ls180.v:156099.9-156099.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\saved_state_dividend_quotient$next[127:0]$8936 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + case + assign $1\saved_state_dividend_quotient$next[127:0]$8936 \div_state_next_o_dividend_quotient + end + sync always + update \saved_state_dividend_quotient$next $0\saved_state_dividend_quotient$next[127:0]$8935 + end + attribute \src "issuer_ls180.v:156107.3-156118.6" + process $proc$issuer_ls180.v:156107$8937 + assign { } { } + assign $0\div_state_next_i_q_bits_known[6:0] $1\div_state_next_i_q_bits_known[6:0] + attribute \src "issuer_ls180.v:156108.5-156108.29" + switch \initial + attribute \src "issuer_ls180.v:156108.9-156108.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:167" + switch \empty + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\div_state_next_i_q_bits_known[6:0] \div_state_init_o_q_bits_known + attribute \src "issuer_ls180.v:0.0-0.0" + case + assign { } { } + assign $1\div_state_next_i_q_bits_known[6:0] \saved_state_q_bits_known + end + sync always + update \div_state_next_i_q_bits_known $0\div_state_next_i_q_bits_known[6:0] + end + attribute \src "issuer_ls180.v:156119.3-156130.6" + process $proc$issuer_ls180.v:156119$8938 + assign { } { } + assign $0\div_state_next_i_dividend_quotient[127:0] $1\div_state_next_i_dividend_quotient[127:0] + attribute \src "issuer_ls180.v:156120.5-156120.29" + switch \initial + attribute \src "issuer_ls180.v:156120.9-156120.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:167" + switch \empty + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\div_state_next_i_dividend_quotient[127:0] \div_state_init_o_dividend_quotient + attribute \src "issuer_ls180.v:0.0-0.0" + case + assign { } { } + assign $1\div_state_next_i_dividend_quotient[127:0] \saved_state_dividend_quotient + end + sync always + update \div_state_next_i_dividend_quotient $0\div_state_next_i_dividend_quotient[127:0] + end + attribute \src "issuer_ls180.v:156131.3-156142.6" + process $proc$issuer_ls180.v:156131$8939 + assign { } { } + assign $0\div_state_next_divisor[63:0] $1\div_state_next_divisor[63:0] + attribute \src "issuer_ls180.v:156132.5-156132.29" + switch \initial + attribute \src "issuer_ls180.v:156132.9-156132.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:167" + switch \empty + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\div_state_next_divisor[63:0] \divisor_radicand + attribute \src "issuer_ls180.v:0.0-0.0" + case + assign { } { } + assign $1\div_state_next_divisor[63:0] \divisor_radicand$65 + end + sync always + update \div_state_next_divisor $0\div_state_next_divisor[63:0] + end + attribute \src "issuer_ls180.v:156143.3-156170.6" + process $proc$issuer_ls180.v:156143$8940 + assign { } { } + assign { } { } + assign { } { } + assign $0\empty$next[0:0]$8941 $4\empty$next[0:0]$8945 + attribute \src "issuer_ls180.v:156144.5-156144.29" + switch \initial + attribute \src "issuer_ls180.v:156144.9-156144.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:167" + switch \empty + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\empty$next[0:0]$8942 $2\empty$next[0:0]$8943 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:170" + switch \p_valid_i + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\empty$next[0:0]$8943 1'0 + case + assign $2\empty$next[0:0]$8943 \empty + end + attribute \src "issuer_ls180.v:0.0-0.0" + case + assign { } { } + assign $1\empty$next[0:0]$8942 $3\empty$next[0:0]$8944 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:177" + switch \$66 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\empty$next[0:0]$8944 1'1 + case + assign $3\empty$next[0:0]$8944 \empty + end + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\empty$next[0:0]$8945 1'1 + case + assign $4\empty$next[0:0]$8945 $1\empty$next[0:0]$8942 + end + sync always + update \empty$next $0\empty$next[0:0]$8941 + end + attribute \src "issuer_ls180.v:156171.3-156185.6" + process $proc$issuer_ls180.v:156171$8946 + assign { } { } + assign { } { } + assign $0\muxid$28$next[1:0]$8947 $1\muxid$28$next[1:0]$8948 + attribute \src "issuer_ls180.v:156172.5-156172.29" + switch \initial + attribute \src "issuer_ls180.v:156172.9-156172.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:167" + switch \empty + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\muxid$28$next[1:0]$8948 $2\muxid$28$next[1:0]$8949 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:170" + switch \p_valid_i + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\muxid$28$next[1:0]$8949 \muxid + case + assign $2\muxid$28$next[1:0]$8949 \muxid$28 + end + case + assign $1\muxid$28$next[1:0]$8948 \muxid$28 + end + sync always + update \muxid$28$next $0\muxid$28$next[1:0]$8947 + end + attribute \src "issuer_ls180.v:156186.3-156229.6" + process $proc$issuer_ls180.v:156186$8950 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\logical_op__data_len$45$next[3:0]$8951 $1\logical_op__data_len$45$next[3:0]$8969 + assign $0\logical_op__fn_unit$30$next[11:0]$8952 $1\logical_op__fn_unit$30$next[11:0]$8970 + assign { } { } + assign { } { } + assign $0\logical_op__input_carry$39$next[1:0]$8955 $1\logical_op__input_carry$39$next[1:0]$8973 + assign $0\logical_op__insn$46$next[31:0]$8956 $1\logical_op__insn$46$next[31:0]$8974 + assign $0\logical_op__insn_type$29$next[6:0]$8957 $1\logical_op__insn_type$29$next[6:0]$8975 + assign $0\logical_op__invert_in$37$next[0:0]$8958 $1\logical_op__invert_in$37$next[0:0]$8976 + assign $0\logical_op__invert_out$40$next[0:0]$8959 $1\logical_op__invert_out$40$next[0:0]$8977 + assign $0\logical_op__is_32bit$43$next[0:0]$8960 $1\logical_op__is_32bit$43$next[0:0]$8978 + assign $0\logical_op__is_signed$44$next[0:0]$8961 $1\logical_op__is_signed$44$next[0:0]$8979 + assign { } { } + assign { } { } + assign $0\logical_op__output_carry$42$next[0:0]$8964 $1\logical_op__output_carry$42$next[0:0]$8982 + assign { } { } + assign { } { } + assign $0\logical_op__write_cr0$41$next[0:0]$8967 $1\logical_op__write_cr0$41$next[0:0]$8985 + assign $0\logical_op__zero_a$38$next[0:0]$8968 $1\logical_op__zero_a$38$next[0:0]$8986 + assign $0\logical_op__imm_data__data$31$next[63:0]$8953 $3\logical_op__imm_data__data$31$next[63:0]$9005 + assign $0\logical_op__imm_data__ok$32$next[0:0]$8954 $3\logical_op__imm_data__ok$32$next[0:0]$9006 + assign $0\logical_op__oe__oe$35$next[0:0]$8962 $3\logical_op__oe__oe$35$next[0:0]$9007 + assign $0\logical_op__oe__ok$36$next[0:0]$8963 $3\logical_op__oe__ok$36$next[0:0]$9008 + assign $0\logical_op__rc__ok$34$next[0:0]$8965 $3\logical_op__rc__ok$34$next[0:0]$9009 + assign $0\logical_op__rc__rc$33$next[0:0]$8966 $3\logical_op__rc__rc$33$next[0:0]$9010 + attribute \src "issuer_ls180.v:156187.5-156187.29" + switch \initial + attribute \src "issuer_ls180.v:156187.9-156187.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:167" + switch \empty + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\logical_op__data_len$45$next[3:0]$8969 $2\logical_op__data_len$45$next[3:0]$8987 + assign $1\logical_op__fn_unit$30$next[11:0]$8970 $2\logical_op__fn_unit$30$next[11:0]$8988 + assign $1\logical_op__imm_data__data$31$next[63:0]$8971 $2\logical_op__imm_data__data$31$next[63:0]$8989 + assign $1\logical_op__imm_data__ok$32$next[0:0]$8972 $2\logical_op__imm_data__ok$32$next[0:0]$8990 + assign $1\logical_op__input_carry$39$next[1:0]$8973 $2\logical_op__input_carry$39$next[1:0]$8991 + assign $1\logical_op__insn$46$next[31:0]$8974 $2\logical_op__insn$46$next[31:0]$8992 + assign $1\logical_op__insn_type$29$next[6:0]$8975 $2\logical_op__insn_type$29$next[6:0]$8993 + assign $1\logical_op__invert_in$37$next[0:0]$8976 $2\logical_op__invert_in$37$next[0:0]$8994 + assign $1\logical_op__invert_out$40$next[0:0]$8977 $2\logical_op__invert_out$40$next[0:0]$8995 + assign $1\logical_op__is_32bit$43$next[0:0]$8978 $2\logical_op__is_32bit$43$next[0:0]$8996 + assign $1\logical_op__is_signed$44$next[0:0]$8979 $2\logical_op__is_signed$44$next[0:0]$8997 + assign $1\logical_op__oe__oe$35$next[0:0]$8980 $2\logical_op__oe__oe$35$next[0:0]$8998 + assign $1\logical_op__oe__ok$36$next[0:0]$8981 $2\logical_op__oe__ok$36$next[0:0]$8999 + assign $1\logical_op__output_carry$42$next[0:0]$8982 $2\logical_op__output_carry$42$next[0:0]$9000 + assign $1\logical_op__rc__ok$34$next[0:0]$8983 $2\logical_op__rc__ok$34$next[0:0]$9001 + assign $1\logical_op__rc__rc$33$next[0:0]$8984 $2\logical_op__rc__rc$33$next[0:0]$9002 + assign $1\logical_op__write_cr0$41$next[0:0]$8985 $2\logical_op__write_cr0$41$next[0:0]$9003 + assign $1\logical_op__zero_a$38$next[0:0]$8986 $2\logical_op__zero_a$38$next[0:0]$9004 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:170" + switch \p_valid_i + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { $2\logical_op__insn$46$next[31:0]$8992 $2\logical_op__data_len$45$next[3:0]$8987 $2\logical_op__is_signed$44$next[0:0]$8997 $2\logical_op__is_32bit$43$next[0:0]$8996 $2\logical_op__output_carry$42$next[0:0]$9000 $2\logical_op__write_cr0$41$next[0:0]$9003 $2\logical_op__invert_out$40$next[0:0]$8995 $2\logical_op__input_carry$39$next[1:0]$8991 $2\logical_op__zero_a$38$next[0:0]$9004 $2\logical_op__invert_in$37$next[0:0]$8994 $2\logical_op__oe__ok$36$next[0:0]$8999 $2\logical_op__oe__oe$35$next[0:0]$8998 $2\logical_op__rc__ok$34$next[0:0]$9001 $2\logical_op__rc__rc$33$next[0:0]$9002 $2\logical_op__imm_data__ok$32$next[0:0]$8990 $2\logical_op__imm_data__data$31$next[63:0]$8989 $2\logical_op__fn_unit$30$next[11:0]$8988 $2\logical_op__insn_type$29$next[6:0]$8993 } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in \logical_op__oe__ok \logical_op__oe__oe \logical_op__rc__ok \logical_op__rc__rc \logical_op__imm_data__ok \logical_op__imm_data__data \logical_op__fn_unit \logical_op__insn_type } + case + assign $2\logical_op__data_len$45$next[3:0]$8987 \logical_op__data_len$45 + assign $2\logical_op__fn_unit$30$next[11:0]$8988 \logical_op__fn_unit$30 + assign $2\logical_op__imm_data__data$31$next[63:0]$8989 \logical_op__imm_data__data$31 + assign $2\logical_op__imm_data__ok$32$next[0:0]$8990 \logical_op__imm_data__ok$32 + assign $2\logical_op__input_carry$39$next[1:0]$8991 \logical_op__input_carry$39 + assign $2\logical_op__insn$46$next[31:0]$8992 \logical_op__insn$46 + assign $2\logical_op__insn_type$29$next[6:0]$8993 \logical_op__insn_type$29 + assign $2\logical_op__invert_in$37$next[0:0]$8994 \logical_op__invert_in$37 + assign $2\logical_op__invert_out$40$next[0:0]$8995 \logical_op__invert_out$40 + assign $2\logical_op__is_32bit$43$next[0:0]$8996 \logical_op__is_32bit$43 + assign $2\logical_op__is_signed$44$next[0:0]$8997 \logical_op__is_signed$44 + assign $2\logical_op__oe__oe$35$next[0:0]$8998 \logical_op__oe__oe$35 + assign $2\logical_op__oe__ok$36$next[0:0]$8999 \logical_op__oe__ok$36 + assign $2\logical_op__output_carry$42$next[0:0]$9000 \logical_op__output_carry$42 + assign $2\logical_op__rc__ok$34$next[0:0]$9001 \logical_op__rc__ok$34 + assign $2\logical_op__rc__rc$33$next[0:0]$9002 \logical_op__rc__rc$33 + assign $2\logical_op__write_cr0$41$next[0:0]$9003 \logical_op__write_cr0$41 + assign $2\logical_op__zero_a$38$next[0:0]$9004 \logical_op__zero_a$38 + end + case + assign $1\logical_op__data_len$45$next[3:0]$8969 \logical_op__data_len$45 + assign $1\logical_op__fn_unit$30$next[11:0]$8970 \logical_op__fn_unit$30 + assign $1\logical_op__imm_data__data$31$next[63:0]$8971 \logical_op__imm_data__data$31 + assign $1\logical_op__imm_data__ok$32$next[0:0]$8972 \logical_op__imm_data__ok$32 + assign $1\logical_op__input_carry$39$next[1:0]$8973 \logical_op__input_carry$39 + assign $1\logical_op__insn$46$next[31:0]$8974 \logical_op__insn$46 + assign $1\logical_op__insn_type$29$next[6:0]$8975 \logical_op__insn_type$29 + assign $1\logical_op__invert_in$37$next[0:0]$8976 \logical_op__invert_in$37 + assign $1\logical_op__invert_out$40$next[0:0]$8977 \logical_op__invert_out$40 + assign $1\logical_op__is_32bit$43$next[0:0]$8978 \logical_op__is_32bit$43 + assign $1\logical_op__is_signed$44$next[0:0]$8979 \logical_op__is_signed$44 + assign $1\logical_op__oe__oe$35$next[0:0]$8980 \logical_op__oe__oe$35 + assign $1\logical_op__oe__ok$36$next[0:0]$8981 \logical_op__oe__ok$36 + assign $1\logical_op__output_carry$42$next[0:0]$8982 \logical_op__output_carry$42 + assign $1\logical_op__rc__ok$34$next[0:0]$8983 \logical_op__rc__ok$34 + assign $1\logical_op__rc__rc$33$next[0:0]$8984 \logical_op__rc__rc$33 + assign $1\logical_op__write_cr0$41$next[0:0]$8985 \logical_op__write_cr0$41 + assign $1\logical_op__zero_a$38$next[0:0]$8986 \logical_op__zero_a$38 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $3\logical_op__imm_data__data$31$next[63:0]$9005 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $3\logical_op__imm_data__ok$32$next[0:0]$9006 1'0 + assign $3\logical_op__rc__rc$33$next[0:0]$9010 1'0 + assign $3\logical_op__rc__ok$34$next[0:0]$9009 1'0 + assign $3\logical_op__oe__oe$35$next[0:0]$9007 1'0 + assign $3\logical_op__oe__ok$36$next[0:0]$9008 1'0 + case + assign $3\logical_op__imm_data__data$31$next[63:0]$9005 $1\logical_op__imm_data__data$31$next[63:0]$8971 + assign $3\logical_op__imm_data__ok$32$next[0:0]$9006 $1\logical_op__imm_data__ok$32$next[0:0]$8972 + assign $3\logical_op__oe__oe$35$next[0:0]$9007 $1\logical_op__oe__oe$35$next[0:0]$8980 + assign $3\logical_op__oe__ok$36$next[0:0]$9008 $1\logical_op__oe__ok$36$next[0:0]$8981 + assign $3\logical_op__rc__ok$34$next[0:0]$9009 $1\logical_op__rc__ok$34$next[0:0]$8983 + assign $3\logical_op__rc__rc$33$next[0:0]$9010 $1\logical_op__rc__rc$33$next[0:0]$8984 + end + sync always + update \logical_op__data_len$45$next $0\logical_op__data_len$45$next[3:0]$8951 + update \logical_op__fn_unit$30$next $0\logical_op__fn_unit$30$next[11:0]$8952 + update \logical_op__imm_data__data$31$next $0\logical_op__imm_data__data$31$next[63:0]$8953 + update \logical_op__imm_data__ok$32$next $0\logical_op__imm_data__ok$32$next[0:0]$8954 + update \logical_op__input_carry$39$next $0\logical_op__input_carry$39$next[1:0]$8955 + update \logical_op__insn$46$next $0\logical_op__insn$46$next[31:0]$8956 + update \logical_op__insn_type$29$next $0\logical_op__insn_type$29$next[6:0]$8957 + update \logical_op__invert_in$37$next $0\logical_op__invert_in$37$next[0:0]$8958 + update \logical_op__invert_out$40$next $0\logical_op__invert_out$40$next[0:0]$8959 + update \logical_op__is_32bit$43$next $0\logical_op__is_32bit$43$next[0:0]$8960 + update \logical_op__is_signed$44$next $0\logical_op__is_signed$44$next[0:0]$8961 + update \logical_op__oe__oe$35$next $0\logical_op__oe__oe$35$next[0:0]$8962 + update \logical_op__oe__ok$36$next $0\logical_op__oe__ok$36$next[0:0]$8963 + update \logical_op__output_carry$42$next $0\logical_op__output_carry$42$next[0:0]$8964 + update \logical_op__rc__ok$34$next $0\logical_op__rc__ok$34$next[0:0]$8965 + update \logical_op__rc__rc$33$next $0\logical_op__rc__rc$33$next[0:0]$8966 + update \logical_op__write_cr0$41$next $0\logical_op__write_cr0$41$next[0:0]$8967 + update \logical_op__zero_a$38$next $0\logical_op__zero_a$38$next[0:0]$8968 + end + attribute \src "issuer_ls180.v:156230.3-156244.6" + process $proc$issuer_ls180.v:156230$9011 + assign { } { } + assign { } { } + assign $0\ra$47$next[63:0]$9012 $1\ra$47$next[63:0]$9013 + attribute \src "issuer_ls180.v:156231.5-156231.29" + switch \initial + attribute \src "issuer_ls180.v:156231.9-156231.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:167" + switch \empty + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\ra$47$next[63:0]$9013 $2\ra$47$next[63:0]$9014 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:170" + switch \p_valid_i + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\ra$47$next[63:0]$9014 \ra + case + assign $2\ra$47$next[63:0]$9014 \ra$47 + end + case + assign $1\ra$47$next[63:0]$9013 \ra$47 + end + sync always + update \ra$47$next $0\ra$47$next[63:0]$9012 + end + attribute \src "issuer_ls180.v:156245.3-156259.6" + process $proc$issuer_ls180.v:156245$9015 + assign { } { } + assign { } { } + assign $0\rb$48$next[63:0]$9016 $1\rb$48$next[63:0]$9017 + attribute \src "issuer_ls180.v:156246.5-156246.29" + switch \initial + attribute \src "issuer_ls180.v:156246.9-156246.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:167" + switch \empty + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\rb$48$next[63:0]$9017 $2\rb$48$next[63:0]$9018 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:170" + switch \p_valid_i + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\rb$48$next[63:0]$9018 \rb + case + assign $2\rb$48$next[63:0]$9018 \rb$48 + end + case + assign $1\rb$48$next[63:0]$9017 \rb$48 + end + sync always + update \rb$48$next $0\rb$48$next[63:0]$9016 + end + attribute \src "issuer_ls180.v:156260.3-156274.6" + process $proc$issuer_ls180.v:156260$9019 + assign { } { } + assign { } { } + assign $0\xer_so$49$next[0:0]$9020 $1\xer_so$49$next[0:0]$9021 + attribute \src "issuer_ls180.v:156261.5-156261.29" + switch \initial + attribute \src "issuer_ls180.v:156261.9-156261.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:167" + switch \empty + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\xer_so$49$next[0:0]$9021 $2\xer_so$49$next[0:0]$9022 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:170" + switch \p_valid_i + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\xer_so$49$next[0:0]$9022 \xer_so + case + assign $2\xer_so$49$next[0:0]$9022 \xer_so$49 + end + case + assign $1\xer_so$49$next[0:0]$9021 \xer_so$49 + end + sync always + update \xer_so$49$next $0\xer_so$49$next[0:0]$9020 + end + attribute \src "issuer_ls180.v:156275.3-156289.6" + process $proc$issuer_ls180.v:156275$9023 + assign { } { } + assign { } { } + assign $0\divisor_neg$50$next[0:0]$9024 $1\divisor_neg$50$next[0:0]$9025 + attribute \src "issuer_ls180.v:156276.5-156276.29" + switch \initial + attribute \src "issuer_ls180.v:156276.9-156276.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:167" + switch \empty + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\divisor_neg$50$next[0:0]$9025 $2\divisor_neg$50$next[0:0]$9026 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:170" + switch \p_valid_i + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\divisor_neg$50$next[0:0]$9026 \divisor_neg + case + assign $2\divisor_neg$50$next[0:0]$9026 \divisor_neg$50 + end + case + assign $1\divisor_neg$50$next[0:0]$9025 \divisor_neg$50 + end + sync always + update \divisor_neg$50$next $0\divisor_neg$50$next[0:0]$9024 + end + attribute \src "issuer_ls180.v:156290.3-156304.6" + process $proc$issuer_ls180.v:156290$9027 + assign { } { } + assign { } { } + assign $0\dividend_neg$51$next[0:0]$9028 $1\dividend_neg$51$next[0:0]$9029 + attribute \src "issuer_ls180.v:156291.5-156291.29" + switch \initial + attribute \src "issuer_ls180.v:156291.9-156291.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:167" + switch \empty + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dividend_neg$51$next[0:0]$9029 $2\dividend_neg$51$next[0:0]$9030 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:170" + switch \p_valid_i + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\dividend_neg$51$next[0:0]$9030 \dividend_neg + case + assign $2\dividend_neg$51$next[0:0]$9030 \dividend_neg$51 + end + case + assign $1\dividend_neg$51$next[0:0]$9029 \dividend_neg$51 + end + sync always + update \dividend_neg$51$next $0\dividend_neg$51$next[0:0]$9028 + end + attribute \src "issuer_ls180.v:156305.3-156319.6" + process $proc$issuer_ls180.v:156305$9031 + assign { } { } + assign { } { } + assign $0\dive_abs_ov32$52$next[0:0]$9032 $1\dive_abs_ov32$52$next[0:0]$9033 + attribute \src "issuer_ls180.v:156306.5-156306.29" + switch \initial + attribute \src "issuer_ls180.v:156306.9-156306.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:167" + switch \empty + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dive_abs_ov32$52$next[0:0]$9033 $2\dive_abs_ov32$52$next[0:0]$9034 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:170" + switch \p_valid_i + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\dive_abs_ov32$52$next[0:0]$9034 \dive_abs_ov32 + case + assign $2\dive_abs_ov32$52$next[0:0]$9034 \dive_abs_ov32$52 + end + case + assign $1\dive_abs_ov32$52$next[0:0]$9033 \dive_abs_ov32$52 + end + sync always + update \dive_abs_ov32$52$next $0\dive_abs_ov32$52$next[0:0]$9032 + end + attribute \src "issuer_ls180.v:156320.3-156334.6" + process $proc$issuer_ls180.v:156320$9035 + assign { } { } + assign { } { } + assign $0\dive_abs_ov64$53$next[0:0]$9036 $1\dive_abs_ov64$53$next[0:0]$9037 + attribute \src "issuer_ls180.v:156321.5-156321.29" + switch \initial + attribute \src "issuer_ls180.v:156321.9-156321.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:167" + switch \empty + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dive_abs_ov64$53$next[0:0]$9037 $2\dive_abs_ov64$53$next[0:0]$9038 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:170" + switch \p_valid_i + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\dive_abs_ov64$53$next[0:0]$9038 \dive_abs_ov64 + case + assign $2\dive_abs_ov64$53$next[0:0]$9038 \dive_abs_ov64$53 + end + case + assign $1\dive_abs_ov64$53$next[0:0]$9037 \dive_abs_ov64$53 + end + sync always + update \dive_abs_ov64$53$next $0\dive_abs_ov64$53$next[0:0]$9036 + end + attribute \src "issuer_ls180.v:156335.3-156349.6" + process $proc$issuer_ls180.v:156335$9039 + assign { } { } + assign { } { } + assign $0\div_by_zero$54$next[0:0]$9040 $1\div_by_zero$54$next[0:0]$9041 + attribute \src "issuer_ls180.v:156336.5-156336.29" + switch \initial + attribute \src "issuer_ls180.v:156336.9-156336.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:167" + switch \empty + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\div_by_zero$54$next[0:0]$9041 $2\div_by_zero$54$next[0:0]$9042 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:170" + switch \p_valid_i + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\div_by_zero$54$next[0:0]$9042 \div_by_zero + case + assign $2\div_by_zero$54$next[0:0]$9042 \div_by_zero$54 + end + case + assign $1\div_by_zero$54$next[0:0]$9041 \div_by_zero$54 + end + sync always + update \div_by_zero$54$next $0\div_by_zero$54$next[0:0]$9040 + end + attribute \src "issuer_ls180.v:156350.3-156364.6" + process $proc$issuer_ls180.v:156350$9043 + assign { } { } + assign { } { } + assign $0\dividend$68$next[127:0]$9044 $1\dividend$68$next[127:0]$9045 + attribute \src "issuer_ls180.v:156351.5-156351.29" + switch \initial + attribute \src "issuer_ls180.v:156351.9-156351.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:167" + switch \empty + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dividend$68$next[127:0]$9045 $2\dividend$68$next[127:0]$9046 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:170" + switch \p_valid_i + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\dividend$68$next[127:0]$9046 \dividend + case + assign $2\dividend$68$next[127:0]$9046 \dividend$68 + end + case + assign $1\dividend$68$next[127:0]$9045 \dividend$68 + end + sync always + update \dividend$68$next $0\dividend$68$next[127:0]$9044 + end + attribute \src "issuer_ls180.v:156365.3-156379.6" + process $proc$issuer_ls180.v:156365$9047 + assign { } { } + assign { } { } + assign $0\divisor_radicand$65$next[63:0]$9048 $1\divisor_radicand$65$next[63:0]$9049 + attribute \src "issuer_ls180.v:156366.5-156366.29" + switch \initial + attribute \src "issuer_ls180.v:156366.9-156366.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:167" + switch \empty + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\divisor_radicand$65$next[63:0]$9049 $2\divisor_radicand$65$next[63:0]$9050 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:170" + switch \p_valid_i + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\divisor_radicand$65$next[63:0]$9050 \divisor_radicand + case + assign $2\divisor_radicand$65$next[63:0]$9050 \divisor_radicand$65 + end + case + assign $1\divisor_radicand$65$next[63:0]$9049 \divisor_radicand$65 + end + sync always + update \divisor_radicand$65$next $0\divisor_radicand$65$next[63:0]$9048 + end + attribute \src "issuer_ls180.v:156380.3-156394.6" + process $proc$issuer_ls180.v:156380$9051 + assign { } { } + assign { } { } + assign $0\operation$69$next[1:0]$9052 $1\operation$69$next[1:0]$9053 + attribute \src "issuer_ls180.v:156381.5-156381.29" + switch \initial + attribute \src "issuer_ls180.v:156381.9-156381.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:167" + switch \empty + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\operation$69$next[1:0]$9053 $2\operation$69$next[1:0]$9054 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:170" + switch \p_valid_i + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\operation$69$next[1:0]$9054 \operation + case + assign $2\operation$69$next[1:0]$9054 \operation$69 + end + case + assign $1\operation$69$next[1:0]$9053 \operation$69 + end + sync always + update \operation$69$next $0\operation$69$next[1:0]$9052 + end + connect \$56 $sshl$issuer_ls180.v:155997$8861_Y + connect \$55 $pos$issuer_ls180.v:155998$8863_Y + connect \$59 $not$issuer_ls180.v:155999$8864_Y + connect \$61 $eq$issuer_ls180.v:156000$8865_Y + connect \$63 $and$issuer_ls180.v:156001$8866_Y + connect \$66 $and$issuer_ls180.v:156002$8867_Y + connect \p_ready_o \empty + connect \n_valid_o \$63 + connect \remainder \$55 + connect \quotient_root \div_state_next_o_dividend_quotient [63:0] + connect \div_by_zero$27 \div_by_zero$54 + connect \dive_abs_ov64$26 \dive_abs_ov64$53 + connect \dive_abs_ov32$25 \dive_abs_ov32$52 + connect \dividend_neg$24 \dividend_neg$51 + connect \divisor_neg$23 \divisor_neg$50 + connect \xer_so$22 \xer_so$49 + connect \rb$21 \rb$48 + connect \ra$20 \ra$47 + connect { \logical_op__insn$19 \logical_op__data_len$18 \logical_op__is_signed$17 \logical_op__is_32bit$16 \logical_op__output_carry$15 \logical_op__write_cr0$14 \logical_op__invert_out$13 \logical_op__input_carry$12 \logical_op__zero_a$11 \logical_op__invert_in$10 \logical_op__oe__ok$9 \logical_op__oe__oe$8 \logical_op__rc__ok$7 \logical_op__rc__rc$6 \logical_op__imm_data__ok$5 \logical_op__imm_data__data$4 \logical_op__fn_unit$3 \logical_op__insn_type$2 } { \logical_op__insn$46 \logical_op__data_len$45 \logical_op__is_signed$44 \logical_op__is_32bit$43 \logical_op__output_carry$42 \logical_op__write_cr0$41 \logical_op__invert_out$40 \logical_op__input_carry$39 \logical_op__zero_a$38 \logical_op__invert_in$37 \logical_op__oe__ok$36 \logical_op__oe__oe$35 \logical_op__rc__ok$34 \logical_op__rc__rc$33 \logical_op__imm_data__ok$32 \logical_op__imm_data__data$31 \logical_op__fn_unit$30 \logical_op__insn_type$29 } + connect \muxid$1 \muxid$28 + connect \div_state_init_dividend \dividend +end +attribute \src "issuer_ls180.v:156414.1-157938.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_start" +attribute \generator "nMigen" +module \pipe_start + attribute \src "issuer_ls180.v:157744.3-157756.6" + wire $0\div_by_zero$next[0:0]$9164 + attribute \src "issuer_ls180.v:157530.3-157531.39" + wire $0\div_by_zero[0:0] + attribute \src "issuer_ls180.v:157718.3-157730.6" + wire $0\dive_abs_ov32$next[0:0]$9158 + attribute \src "issuer_ls180.v:157534.3-157535.43" + wire $0\dive_abs_ov32[0:0] + attribute \src "issuer_ls180.v:157731.3-157743.6" + wire $0\dive_abs_ov64$next[0:0]$9161 + attribute \src "issuer_ls180.v:157532.3-157533.43" + wire $0\dive_abs_ov64[0:0] + attribute \src "issuer_ls180.v:157757.3-157769.6" + wire width 128 $0\dividend$next[127:0]$9167 + attribute \src "issuer_ls180.v:157528.3-157529.33" + wire width 128 $0\dividend[127:0] + attribute \src "issuer_ls180.v:157705.3-157717.6" + wire $0\dividend_neg$next[0:0]$9155 + attribute \src "issuer_ls180.v:157536.3-157537.41" + wire $0\dividend_neg[0:0] + attribute \src "issuer_ls180.v:157692.3-157704.6" + wire $0\divisor_neg$next[0:0]$9152 + attribute \src "issuer_ls180.v:157538.3-157539.39" + wire $0\divisor_neg[0:0] + attribute \src "issuer_ls180.v:157770.3-157782.6" + wire width 64 $0\divisor_radicand$next[63:0]$9170 + attribute \src "issuer_ls180.v:157526.3-157527.49" + wire width 64 $0\divisor_radicand[63:0] + attribute \src "issuer_ls180.v:156415.7-156415.20" + wire $0\initial[0:0] + attribute \src "issuer_ls180.v:157827.3-157868.6" + wire width 4 $0\logical_op__data_len$next[3:0]$9183 + attribute \src "issuer_ls180.v:157578.3-157579.57" + wire width 4 $0\logical_op__data_len[3:0] + attribute \src "issuer_ls180.v:157827.3-157868.6" + wire width 12 $0\logical_op__fn_unit$next[11:0]$9184 + attribute \src "issuer_ls180.v:157548.3-157549.55" + wire width 12 $0\logical_op__fn_unit[11:0] + attribute \src "issuer_ls180.v:157827.3-157868.6" + wire width 64 $0\logical_op__imm_data__data$next[63:0]$9185 + attribute \src "issuer_ls180.v:157550.3-157551.69" + wire width 64 $0\logical_op__imm_data__data[63:0] + attribute \src "issuer_ls180.v:157827.3-157868.6" + wire $0\logical_op__imm_data__ok$next[0:0]$9186 + attribute \src "issuer_ls180.v:157552.3-157553.65" + wire $0\logical_op__imm_data__ok[0:0] + attribute \src "issuer_ls180.v:157827.3-157868.6" + wire width 2 $0\logical_op__input_carry$next[1:0]$9187 + attribute \src "issuer_ls180.v:157566.3-157567.63" + wire width 2 $0\logical_op__input_carry[1:0] + attribute \src "issuer_ls180.v:157827.3-157868.6" + wire width 32 $0\logical_op__insn$next[31:0]$9188 + attribute \src "issuer_ls180.v:157580.3-157581.49" + wire width 32 $0\logical_op__insn[31:0] + attribute \src "issuer_ls180.v:157827.3-157868.6" + wire width 7 $0\logical_op__insn_type$next[6:0]$9189 + attribute \src "issuer_ls180.v:157546.3-157547.59" + wire width 7 $0\logical_op__insn_type[6:0] + attribute \src "issuer_ls180.v:157827.3-157868.6" + wire $0\logical_op__invert_in$next[0:0]$9190 + attribute \src "issuer_ls180.v:157562.3-157563.59" + wire $0\logical_op__invert_in[0:0] + attribute \src "issuer_ls180.v:157827.3-157868.6" + wire $0\logical_op__invert_out$next[0:0]$9191 + attribute \src "issuer_ls180.v:157568.3-157569.61" + wire $0\logical_op__invert_out[0:0] + attribute \src "issuer_ls180.v:157827.3-157868.6" + wire $0\logical_op__is_32bit$next[0:0]$9192 + attribute \src "issuer_ls180.v:157574.3-157575.57" + wire $0\logical_op__is_32bit[0:0] + attribute \src "issuer_ls180.v:157827.3-157868.6" + wire $0\logical_op__is_signed$next[0:0]$9193 + attribute \src "issuer_ls180.v:157576.3-157577.59" + wire $0\logical_op__is_signed[0:0] + attribute \src "issuer_ls180.v:157827.3-157868.6" + wire $0\logical_op__oe__oe$next[0:0]$9194 + attribute \src "issuer_ls180.v:157558.3-157559.53" + wire $0\logical_op__oe__oe[0:0] + attribute \src "issuer_ls180.v:157827.3-157868.6" + wire $0\logical_op__oe__ok$next[0:0]$9195 + attribute \src "issuer_ls180.v:157560.3-157561.53" + wire $0\logical_op__oe__ok[0:0] + attribute \src "issuer_ls180.v:157827.3-157868.6" + wire $0\logical_op__output_carry$next[0:0]$9196 + attribute \src "issuer_ls180.v:157572.3-157573.65" + wire $0\logical_op__output_carry[0:0] + attribute \src "issuer_ls180.v:157827.3-157868.6" + wire $0\logical_op__rc__ok$next[0:0]$9197 + attribute \src "issuer_ls180.v:157556.3-157557.53" + wire $0\logical_op__rc__ok[0:0] + attribute \src "issuer_ls180.v:157827.3-157868.6" + wire $0\logical_op__rc__rc$next[0:0]$9198 + attribute \src "issuer_ls180.v:157554.3-157555.53" + wire $0\logical_op__rc__rc[0:0] + attribute \src "issuer_ls180.v:157827.3-157868.6" + wire $0\logical_op__write_cr0$next[0:0]$9199 + attribute \src "issuer_ls180.v:157570.3-157571.59" + wire $0\logical_op__write_cr0[0:0] + attribute \src "issuer_ls180.v:157827.3-157868.6" + wire $0\logical_op__zero_a$next[0:0]$9200 + attribute \src "issuer_ls180.v:157564.3-157565.53" + wire $0\logical_op__zero_a[0:0] + attribute \src "issuer_ls180.v:157814.3-157826.6" + wire width 2 $0\muxid$next[1:0]$9180 + attribute \src "issuer_ls180.v:157582.3-157583.27" + wire width 2 $0\muxid[1:0] + attribute \src "issuer_ls180.v:157783.3-157795.6" + wire width 2 $0\operation$next[1:0]$9173 + attribute \src "issuer_ls180.v:157524.3-157525.35" + wire width 2 $0\operation[1:0] + attribute \src "issuer_ls180.v:157796.3-157813.6" + wire $0\r_busy$next[0:0]$9176 + attribute \src "issuer_ls180.v:157584.3-157585.29" + wire $0\r_busy[0:0] + attribute \src "issuer_ls180.v:157869.3-157881.6" + wire width 64 $0\ra$next[63:0]$9226 + attribute \src "issuer_ls180.v:157544.3-157545.21" + wire width 64 $0\ra[63:0] + attribute \src "issuer_ls180.v:157882.3-157894.6" + wire width 64 $0\rb$next[63:0]$9229 + attribute \src "issuer_ls180.v:157542.3-157543.21" + wire width 64 $0\rb[63:0] + attribute \src "issuer_ls180.v:157895.3-157907.6" + wire $0\xer_so$next[0:0]$9232 + attribute \src "issuer_ls180.v:157540.3-157541.29" + wire $0\xer_so[0:0] + attribute \src "issuer_ls180.v:157744.3-157756.6" + wire $1\div_by_zero$next[0:0]$9165 + attribute \src "issuer_ls180.v:156424.7-156424.25" + wire $1\div_by_zero[0:0] + attribute \src "issuer_ls180.v:157718.3-157730.6" + wire $1\dive_abs_ov32$next[0:0]$9159 + attribute \src "issuer_ls180.v:156431.7-156431.27" + wire $1\dive_abs_ov32[0:0] + attribute \src "issuer_ls180.v:157731.3-157743.6" + wire $1\dive_abs_ov64$next[0:0]$9162 + attribute \src "issuer_ls180.v:156438.7-156438.27" + wire $1\dive_abs_ov64[0:0] + attribute \src "issuer_ls180.v:157757.3-157769.6" + wire width 128 $1\dividend$next[127:0]$9168 + attribute \src "issuer_ls180.v:156445.15-156445.63" + wire width 128 $1\dividend[127:0] + attribute \src "issuer_ls180.v:157705.3-157717.6" + wire $1\dividend_neg$next[0:0]$9156 + attribute \src "issuer_ls180.v:156452.7-156452.26" + wire $1\dividend_neg[0:0] + attribute \src "issuer_ls180.v:157692.3-157704.6" + wire $1\divisor_neg$next[0:0]$9153 + attribute \src "issuer_ls180.v:156459.7-156459.25" + wire $1\divisor_neg[0:0] + attribute \src "issuer_ls180.v:157770.3-157782.6" + wire width 64 $1\divisor_radicand$next[63:0]$9171 + attribute \src "issuer_ls180.v:156466.14-156466.53" + wire width 64 $1\divisor_radicand[63:0] + attribute \src "issuer_ls180.v:157827.3-157868.6" + wire width 4 $1\logical_op__data_len$next[3:0]$9201 + attribute \src "issuer_ls180.v:156743.13-156743.40" + wire width 4 $1\logical_op__data_len[3:0] + attribute \src "issuer_ls180.v:157827.3-157868.6" + wire width 12 $1\logical_op__fn_unit$next[11:0]$9202 + attribute \src "issuer_ls180.v:156765.14-156765.43" + wire width 12 $1\logical_op__fn_unit[11:0] + attribute \src "issuer_ls180.v:157827.3-157868.6" + wire width 64 $1\logical_op__imm_data__data$next[63:0]$9203 + attribute \src "issuer_ls180.v:156800.14-156800.63" + wire width 64 $1\logical_op__imm_data__data[63:0] + attribute \src "issuer_ls180.v:157827.3-157868.6" + wire $1\logical_op__imm_data__ok$next[0:0]$9204 + attribute \src "issuer_ls180.v:156809.7-156809.38" + wire $1\logical_op__imm_data__ok[0:0] + attribute \src "issuer_ls180.v:157827.3-157868.6" + wire width 2 $1\logical_op__input_carry$next[1:0]$9205 + attribute \src "issuer_ls180.v:156822.13-156822.43" + wire width 2 $1\logical_op__input_carry[1:0] + attribute \src "issuer_ls180.v:157827.3-157868.6" + wire width 32 $1\logical_op__insn$next[31:0]$9206 + attribute \src "issuer_ls180.v:156839.14-156839.38" + wire width 32 $1\logical_op__insn[31:0] + attribute \src "issuer_ls180.v:157827.3-157868.6" + wire width 7 $1\logical_op__insn_type$next[6:0]$9207 + attribute \src "issuer_ls180.v:156922.13-156922.42" + wire width 7 $1\logical_op__insn_type[6:0] + attribute \src "issuer_ls180.v:157827.3-157868.6" + wire $1\logical_op__invert_in$next[0:0]$9208 + attribute \src "issuer_ls180.v:157079.7-157079.35" + wire $1\logical_op__invert_in[0:0] + attribute \src "issuer_ls180.v:157827.3-157868.6" + wire $1\logical_op__invert_out$next[0:0]$9209 + attribute \src "issuer_ls180.v:157088.7-157088.36" + wire $1\logical_op__invert_out[0:0] + attribute \src "issuer_ls180.v:157827.3-157868.6" + wire $1\logical_op__is_32bit$next[0:0]$9210 + attribute \src "issuer_ls180.v:157097.7-157097.34" + wire $1\logical_op__is_32bit[0:0] + attribute \src "issuer_ls180.v:157827.3-157868.6" + wire $1\logical_op__is_signed$next[0:0]$9211 + attribute \src "issuer_ls180.v:157106.7-157106.35" + wire $1\logical_op__is_signed[0:0] + attribute \src "issuer_ls180.v:157827.3-157868.6" + wire $1\logical_op__oe__oe$next[0:0]$9212 + attribute \src "issuer_ls180.v:157115.7-157115.32" + wire $1\logical_op__oe__oe[0:0] + attribute \src "issuer_ls180.v:157827.3-157868.6" + wire $1\logical_op__oe__ok$next[0:0]$9213 + attribute \src "issuer_ls180.v:157124.7-157124.32" + wire $1\logical_op__oe__ok[0:0] + attribute \src "issuer_ls180.v:157827.3-157868.6" + wire $1\logical_op__output_carry$next[0:0]$9214 + attribute \src "issuer_ls180.v:157133.7-157133.38" + wire $1\logical_op__output_carry[0:0] + attribute \src "issuer_ls180.v:157827.3-157868.6" + wire $1\logical_op__rc__ok$next[0:0]$9215 + attribute \src "issuer_ls180.v:157142.7-157142.32" + wire $1\logical_op__rc__ok[0:0] + attribute \src "issuer_ls180.v:157827.3-157868.6" + wire $1\logical_op__rc__rc$next[0:0]$9216 + attribute \src "issuer_ls180.v:157151.7-157151.32" + wire $1\logical_op__rc__rc[0:0] + attribute \src "issuer_ls180.v:157827.3-157868.6" + wire $1\logical_op__write_cr0$next[0:0]$9217 + attribute \src "issuer_ls180.v:157160.7-157160.35" + wire $1\logical_op__write_cr0[0:0] + attribute \src "issuer_ls180.v:157827.3-157868.6" + wire $1\logical_op__zero_a$next[0:0]$9218 + attribute \src "issuer_ls180.v:157169.7-157169.32" + wire $1\logical_op__zero_a[0:0] + attribute \src "issuer_ls180.v:157814.3-157826.6" + wire width 2 $1\muxid$next[1:0]$9181 + attribute \src "issuer_ls180.v:157178.13-157178.25" + wire width 2 $1\muxid[1:0] + attribute \src "issuer_ls180.v:157783.3-157795.6" + wire width 2 $1\operation$next[1:0]$9174 + attribute \src "issuer_ls180.v:157193.13-157193.29" + wire width 2 $1\operation[1:0] + attribute \src "issuer_ls180.v:157796.3-157813.6" + wire $1\r_busy$next[0:0]$9177 + attribute \src "issuer_ls180.v:157207.7-157207.20" + wire $1\r_busy[0:0] + attribute \src "issuer_ls180.v:157869.3-157881.6" + wire width 64 $1\ra$next[63:0]$9227 + attribute \src "issuer_ls180.v:157212.14-157212.39" + wire width 64 $1\ra[63:0] + attribute \src "issuer_ls180.v:157882.3-157894.6" + wire width 64 $1\rb$next[63:0]$9230 + attribute \src "issuer_ls180.v:157223.14-157223.39" + wire width 64 $1\rb[63:0] + attribute \src "issuer_ls180.v:157895.3-157907.6" + wire $1\xer_so$next[0:0]$9233 + attribute \src "issuer_ls180.v:157516.7-157516.20" + wire $1\xer_so[0:0] + attribute \src "issuer_ls180.v:157827.3-157868.6" + wire width 64 $2\logical_op__imm_data__data$next[63:0]$9219 + attribute \src "issuer_ls180.v:157827.3-157868.6" + wire $2\logical_op__imm_data__ok$next[0:0]$9220 + attribute \src "issuer_ls180.v:157827.3-157868.6" + wire $2\logical_op__oe__oe$next[0:0]$9221 + attribute \src "issuer_ls180.v:157827.3-157868.6" + wire $2\logical_op__oe__ok$next[0:0]$9222 + attribute \src "issuer_ls180.v:157827.3-157868.6" + wire $2\logical_op__rc__ok$next[0:0]$9223 + attribute \src "issuer_ls180.v:157827.3-157868.6" + wire $2\logical_op__rc__rc$next[0:0]$9224 + attribute \src "issuer_ls180.v:157796.3-157813.6" + wire $2\r_busy$next[0:0]$9178 + attribute \src "issuer_ls180.v:157523.18-157523.118" + wire $and$issuer_ls180.v:157523$9119_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" + wire \$66 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" + wire input 58 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" + wire input 1 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire output 30 \div_by_zero + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire \div_by_zero$96 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" + wire \div_by_zero$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire output 28 \dive_abs_ov32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire \dive_abs_ov32$94 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" + wire \dive_abs_ov32$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire output 29 \dive_abs_ov64 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire \dive_abs_ov64$95 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" + wire \dive_abs_ov64$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:18" + wire width 128 output 31 \dividend + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:18" + wire width 128 \dividend$97 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:18" + wire width 128 \dividend$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire output 27 \dividend_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire \dividend_neg$93 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" + wire \dividend_neg$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire output 26 \divisor_neg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire \divisor_neg$92 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" + wire \divisor_neg$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:19" + wire width 64 output 32 \divisor_radicand + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:19" + wire width 64 \divisor_radicand$98 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:19" + wire width 64 \divisor_radicand$next + attribute \src "issuer_ls180.v:156415.7-156415.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \input_logical_op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \input_logical_op__data_len$40 + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 \input_logical_op__fn_unit + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 \input_logical_op__fn_unit$25 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \input_logical_op__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \input_logical_op__imm_data__data$26 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_logical_op__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_logical_op__imm_data__ok$27 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \input_logical_op__input_carry + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \input_logical_op__input_carry$34 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \input_logical_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \input_logical_op__insn$41 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \input_logical_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \input_logical_op__insn_type$24 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_logical_op__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_logical_op__invert_in$32 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_logical_op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_logical_op__invert_out$35 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_logical_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_logical_op__is_32bit$38 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_logical_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_logical_op__is_signed$39 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_logical_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_logical_op__oe__oe$30 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_logical_op__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_logical_op__oe__ok$31 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_logical_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_logical_op__output_carry$37 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_logical_op__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_logical_op__rc__ok$29 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_logical_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_logical_op__rc__rc$28 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_logical_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_logical_op__write_cr0$36 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_logical_op__zero_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \input_logical_op__zero_a$33 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \input_muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \input_muxid$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \input_ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \input_ra$42 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \input_rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 \input_rb$43 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire \input_xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire \input_xer_so$44 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 output 21 \logical_op__data_len + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 input 53 \logical_op__data_len$18 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \logical_op__data_len$85 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 4 \logical_op__data_len$next + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 output 6 \logical_op__fn_unit + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 input 38 \logical_op__fn_unit$3 + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 \logical_op__fn_unit$70 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 \logical_op__fn_unit$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 output 7 \logical_op__imm_data__data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 input 39 \logical_op__imm_data__data$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \logical_op__imm_data__data$71 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 64 \logical_op__imm_data__data$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 8 \logical_op__imm_data__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 40 \logical_op__imm_data__ok$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__imm_data__ok$72 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__imm_data__ok$next + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 output 15 \logical_op__input_carry + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 input 47 \logical_op__input_carry$12 + attribute \enum_base_type "CryIn" + attribute \enum_value_00 "ZERO" + attribute \enum_value_01 "ONE" + attribute \enum_value_10 "CA" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \logical_op__input_carry$79 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 2 \logical_op__input_carry$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 output 22 \logical_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 54 \logical_op__insn$19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \logical_op__insn$86 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 \logical_op__insn$next + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 output 5 \logical_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 input 37 \logical_op__insn_type$2 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \logical_op__insn_type$69 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 \logical_op__insn_type$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 13 \logical_op__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 45 \logical_op__invert_in$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__invert_in$77 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__invert_in$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 16 \logical_op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 48 \logical_op__invert_out$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__invert_out$80 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__invert_out$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 19 \logical_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 51 \logical_op__is_32bit$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__is_32bit$83 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__is_32bit$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 20 \logical_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 52 \logical_op__is_signed$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__is_signed$84 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__is_signed$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 11 \logical_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__oe__oe$75 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 43 \logical_op__oe__oe$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__oe__oe$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 12 \logical_op__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__oe__ok$76 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 44 \logical_op__oe__ok$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__oe__ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 18 \logical_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 50 \logical_op__output_carry$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__output_carry$82 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__output_carry$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 10 \logical_op__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 42 \logical_op__rc__ok$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__rc__ok$74 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__rc__ok$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 9 \logical_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 41 \logical_op__rc__rc$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__rc__rc$73 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__rc__rc$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 17 \logical_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 49 \logical_op__write_cr0$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__write_cr0$81 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__write_cr0$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 14 \logical_op__zero_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 46 \logical_op__zero_a$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__zero_a$78 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire \logical_op__zero_a$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 output 4 \muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 input 36 \muxid$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \muxid$68 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 \muxid$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:619" + wire \n_i_rdy_data + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" + wire input 3 \n_ready_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" + wire output 2 \n_valid_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:21" + wire width 2 output 33 \operation + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:21" + wire width 2 \operation$99 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:21" + wire width 2 \operation$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" + wire output 35 \p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" + wire input 34 \p_valid_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:621" + wire \p_valid_i$65 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" + wire \p_valid_i_p_ready_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615" + wire \r_busy + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615" + wire \r_busy$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 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\logical_op__is_32bit$16 \input_logical_op__is_32bit$38 + connect \logical_op__is_signed \input_logical_op__is_signed + connect \logical_op__is_signed$17 \input_logical_op__is_signed$39 + connect \logical_op__oe__oe \input_logical_op__oe__oe + connect \logical_op__oe__oe$8 \input_logical_op__oe__oe$30 + connect \logical_op__oe__ok \input_logical_op__oe__ok + connect \logical_op__oe__ok$9 \input_logical_op__oe__ok$31 + connect \logical_op__output_carry \input_logical_op__output_carry + connect \logical_op__output_carry$15 \input_logical_op__output_carry$37 + connect \logical_op__rc__ok \input_logical_op__rc__ok + connect \logical_op__rc__ok$7 \input_logical_op__rc__ok$29 + connect \logical_op__rc__rc \input_logical_op__rc__rc + connect \logical_op__rc__rc$6 \input_logical_op__rc__rc$28 + connect \logical_op__write_cr0 \input_logical_op__write_cr0 + connect \logical_op__write_cr0$14 \input_logical_op__write_cr0$36 + connect \logical_op__zero_a \input_logical_op__zero_a + connect \logical_op__zero_a$11 \input_logical_op__zero_a$33 + connect \muxid \input_muxid + connect \muxid$1 \input_muxid$23 + connect \ra \input_ra + connect \ra$20 \input_ra$42 + connect \rb \input_rb + connect \rb$21 \input_rb$43 + connect \xer_so \input_xer_so + connect \xer_so$22 \input_xer_so$44 + end + attribute \module_not_derived 1 + attribute \src "issuer_ls180.v:157632.10-157635.4" + cell \n$74 \n + connect \n_ready_i \n_ready_i + connect \n_valid_o \n_valid_o + end + attribute \module_not_derived 1 + attribute \src "issuer_ls180.v:157636.10-157639.4" + cell \p$73 \p + connect \p_ready_o \p_ready_o + connect \p_valid_i \p_valid_i + end + attribute \module_not_derived 1 + attribute \src "issuer_ls180.v:157640.15-157691.4" + cell \setup_stage \setup_stage + connect \div_by_zero \setup_stage_div_by_zero + connect \dive_abs_ov32 \setup_stage_dive_abs_ov32 + connect \dive_abs_ov64 \setup_stage_dive_abs_ov64 + connect \dividend \setup_stage_dividend + connect \dividend_neg \setup_stage_dividend_neg + connect \divisor_neg \setup_stage_divisor_neg + connect \divisor_radicand \setup_stage_divisor_radicand + connect \logical_op__data_len \setup_stage_logical_op__data_len + connect \logical_op__data_len$18 \setup_stage_logical_op__data_len$62 + connect \logical_op__fn_unit \setup_stage_logical_op__fn_unit + connect \logical_op__fn_unit$3 \setup_stage_logical_op__fn_unit$47 + connect \logical_op__imm_data__data \setup_stage_logical_op__imm_data__data + connect \logical_op__imm_data__data$4 \setup_stage_logical_op__imm_data__data$48 + connect \logical_op__imm_data__ok \setup_stage_logical_op__imm_data__ok + connect \logical_op__imm_data__ok$5 \setup_stage_logical_op__imm_data__ok$49 + connect \logical_op__input_carry \setup_stage_logical_op__input_carry + connect \logical_op__input_carry$12 \setup_stage_logical_op__input_carry$56 + connect \logical_op__insn \setup_stage_logical_op__insn + connect \logical_op__insn$19 \setup_stage_logical_op__insn$63 + connect \logical_op__insn_type \setup_stage_logical_op__insn_type + connect \logical_op__insn_type$2 \setup_stage_logical_op__insn_type$46 + connect \logical_op__invert_in \setup_stage_logical_op__invert_in + connect \logical_op__invert_in$10 \setup_stage_logical_op__invert_in$54 + connect \logical_op__invert_out \setup_stage_logical_op__invert_out + connect \logical_op__invert_out$13 \setup_stage_logical_op__invert_out$57 + connect \logical_op__is_32bit \setup_stage_logical_op__is_32bit + connect \logical_op__is_32bit$16 \setup_stage_logical_op__is_32bit$60 + connect \logical_op__is_signed \setup_stage_logical_op__is_signed + connect \logical_op__is_signed$17 \setup_stage_logical_op__is_signed$61 + connect \logical_op__oe__oe \setup_stage_logical_op__oe__oe + connect \logical_op__oe__oe$8 \setup_stage_logical_op__oe__oe$52 + connect \logical_op__oe__ok \setup_stage_logical_op__oe__ok + connect \logical_op__oe__ok$9 \setup_stage_logical_op__oe__ok$53 + connect \logical_op__output_carry \setup_stage_logical_op__output_carry + connect \logical_op__output_carry$15 \setup_stage_logical_op__output_carry$59 + connect \logical_op__rc__ok \setup_stage_logical_op__rc__ok + connect \logical_op__rc__ok$7 \setup_stage_logical_op__rc__ok$51 + connect \logical_op__rc__rc \setup_stage_logical_op__rc__rc + connect \logical_op__rc__rc$6 \setup_stage_logical_op__rc__rc$50 + connect \logical_op__write_cr0 \setup_stage_logical_op__write_cr0 + connect \logical_op__write_cr0$14 \setup_stage_logical_op__write_cr0$58 + connect \logical_op__zero_a \setup_stage_logical_op__zero_a + connect \logical_op__zero_a$11 \setup_stage_logical_op__zero_a$55 + connect \muxid \setup_stage_muxid + connect \muxid$1 \setup_stage_muxid$45 + connect \operation \setup_stage_operation + connect \ra \setup_stage_ra + connect \rb \setup_stage_rb + connect \xer_so \setup_stage_xer_so + connect \xer_so$20 \setup_stage_xer_so$64 + end + attribute \src "issuer_ls180.v:156415.7-156415.20" + process $proc$issuer_ls180.v:156415$9234 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "issuer_ls180.v:156424.7-156424.25" + process $proc$issuer_ls180.v:156424$9235 + assign { } { } + assign $1\div_by_zero[0:0] 1'0 + sync always + sync init + update \div_by_zero $1\div_by_zero[0:0] + end + attribute \src "issuer_ls180.v:156431.7-156431.27" + process $proc$issuer_ls180.v:156431$9236 + assign { } { } + assign $1\dive_abs_ov32[0:0] 1'0 + sync always + sync init + update \dive_abs_ov32 $1\dive_abs_ov32[0:0] + end + attribute \src "issuer_ls180.v:156438.7-156438.27" + process $proc$issuer_ls180.v:156438$9237 + assign { } { } + assign $1\dive_abs_ov64[0:0] 1'0 + sync always + sync init + update \dive_abs_ov64 $1\dive_abs_ov64[0:0] + end + attribute \src "issuer_ls180.v:156445.15-156445.63" + process $proc$issuer_ls180.v:156445$9238 + assign { } { } + assign $1\dividend[127:0] 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \dividend $1\dividend[127:0] + end + attribute \src "issuer_ls180.v:156452.7-156452.26" + process $proc$issuer_ls180.v:156452$9239 + assign { } { } + assign $1\dividend_neg[0:0] 1'0 + sync always + sync init + update \dividend_neg $1\dividend_neg[0:0] + end + attribute \src "issuer_ls180.v:156459.7-156459.25" + process $proc$issuer_ls180.v:156459$9240 + assign { } { } + assign $1\divisor_neg[0:0] 1'0 + sync always + sync init + update \divisor_neg $1\divisor_neg[0:0] + end + attribute \src "issuer_ls180.v:156466.14-156466.53" + process $proc$issuer_ls180.v:156466$9241 + assign { } { } + assign $1\divisor_radicand[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \divisor_radicand $1\divisor_radicand[63:0] + end + attribute \src "issuer_ls180.v:156743.13-156743.40" + process $proc$issuer_ls180.v:156743$9242 + assign { } { } + assign $1\logical_op__data_len[3:0] 4'0000 + sync always + sync init + update \logical_op__data_len $1\logical_op__data_len[3:0] + end + attribute \src "issuer_ls180.v:156765.14-156765.43" + process $proc$issuer_ls180.v:156765$9243 + assign { } { } + assign $1\logical_op__fn_unit[11:0] 12'000000000000 + sync always + sync init + update \logical_op__fn_unit $1\logical_op__fn_unit[11:0] + end + attribute \src "issuer_ls180.v:156800.14-156800.63" + process $proc$issuer_ls180.v:156800$9244 + assign { } { } + assign $1\logical_op__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \logical_op__imm_data__data $1\logical_op__imm_data__data[63:0] + end + attribute \src "issuer_ls180.v:156809.7-156809.38" + process $proc$issuer_ls180.v:156809$9245 + assign { } { } + assign $1\logical_op__imm_data__ok[0:0] 1'0 + sync always + sync init + update \logical_op__imm_data__ok $1\logical_op__imm_data__ok[0:0] + end + attribute \src "issuer_ls180.v:156822.13-156822.43" + process $proc$issuer_ls180.v:156822$9246 + assign { } { } + assign $1\logical_op__input_carry[1:0] 2'00 + sync always + sync init + update \logical_op__input_carry $1\logical_op__input_carry[1:0] + end + attribute \src "issuer_ls180.v:156839.14-156839.38" + process $proc$issuer_ls180.v:156839$9247 + assign { } { } + assign $1\logical_op__insn[31:0] 0 + sync always + sync init + update \logical_op__insn $1\logical_op__insn[31:0] + end + attribute \src "issuer_ls180.v:156922.13-156922.42" + process $proc$issuer_ls180.v:156922$9248 + assign { } { } + assign $1\logical_op__insn_type[6:0] 7'0000000 + sync always + sync init + update \logical_op__insn_type $1\logical_op__insn_type[6:0] + end + attribute \src "issuer_ls180.v:157079.7-157079.35" + process $proc$issuer_ls180.v:157079$9249 + assign { } { } + assign $1\logical_op__invert_in[0:0] 1'0 + sync always + sync init + update \logical_op__invert_in $1\logical_op__invert_in[0:0] + end + attribute \src "issuer_ls180.v:157088.7-157088.36" + process $proc$issuer_ls180.v:157088$9250 + assign { } { } + assign $1\logical_op__invert_out[0:0] 1'0 + sync always + sync init + update \logical_op__invert_out $1\logical_op__invert_out[0:0] + end + attribute \src "issuer_ls180.v:157097.7-157097.34" + process $proc$issuer_ls180.v:157097$9251 + assign { } { } + assign $1\logical_op__is_32bit[0:0] 1'0 + sync always + sync init + update \logical_op__is_32bit $1\logical_op__is_32bit[0:0] + end + attribute \src "issuer_ls180.v:157106.7-157106.35" + process $proc$issuer_ls180.v:157106$9252 + assign { } { } + assign $1\logical_op__is_signed[0:0] 1'0 + sync always + sync init + update \logical_op__is_signed $1\logical_op__is_signed[0:0] + end + attribute \src "issuer_ls180.v:157115.7-157115.32" + process $proc$issuer_ls180.v:157115$9253 + assign { } { } + assign $1\logical_op__oe__oe[0:0] 1'0 + sync always + sync init + update \logical_op__oe__oe $1\logical_op__oe__oe[0:0] + end + attribute \src "issuer_ls180.v:157124.7-157124.32" + process $proc$issuer_ls180.v:157124$9254 + assign { } { } + assign $1\logical_op__oe__ok[0:0] 1'0 + sync always + sync init + update \logical_op__oe__ok $1\logical_op__oe__ok[0:0] + end + attribute \src "issuer_ls180.v:157133.7-157133.38" + process $proc$issuer_ls180.v:157133$9255 + assign { } { } + assign $1\logical_op__output_carry[0:0] 1'0 + sync always + sync init + update \logical_op__output_carry $1\logical_op__output_carry[0:0] + end + attribute \src "issuer_ls180.v:157142.7-157142.32" + process $proc$issuer_ls180.v:157142$9256 + assign { } { } + assign $1\logical_op__rc__ok[0:0] 1'0 + sync always + sync init + update \logical_op__rc__ok $1\logical_op__rc__ok[0:0] + end + attribute \src "issuer_ls180.v:157151.7-157151.32" + process $proc$issuer_ls180.v:157151$9257 + assign { } { } + assign $1\logical_op__rc__rc[0:0] 1'0 + sync always + sync init + update \logical_op__rc__rc $1\logical_op__rc__rc[0:0] + end + attribute \src "issuer_ls180.v:157160.7-157160.35" + process $proc$issuer_ls180.v:157160$9258 + assign { } { } + assign $1\logical_op__write_cr0[0:0] 1'0 + sync always + sync init + update \logical_op__write_cr0 $1\logical_op__write_cr0[0:0] + end + attribute \src "issuer_ls180.v:157169.7-157169.32" + process $proc$issuer_ls180.v:157169$9259 + assign { } { } + assign $1\logical_op__zero_a[0:0] 1'0 + sync always + sync init + update \logical_op__zero_a $1\logical_op__zero_a[0:0] + end + attribute \src "issuer_ls180.v:157178.13-157178.25" + process $proc$issuer_ls180.v:157178$9260 + assign { } { } + assign $1\muxid[1:0] 2'00 + sync always + sync init + update \muxid $1\muxid[1:0] + end + attribute \src "issuer_ls180.v:157193.13-157193.29" + process $proc$issuer_ls180.v:157193$9261 + assign { } { } + assign $1\operation[1:0] 2'00 + sync always + sync init + update \operation $1\operation[1:0] + end + attribute \src "issuer_ls180.v:157207.7-157207.20" + process $proc$issuer_ls180.v:157207$9262 + assign { } { } + assign $1\r_busy[0:0] 1'0 + sync always + sync init + update \r_busy $1\r_busy[0:0] + end + attribute \src "issuer_ls180.v:157212.14-157212.39" + process $proc$issuer_ls180.v:157212$9263 + assign { } { } + assign $1\ra[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \ra $1\ra[63:0] + end + attribute \src "issuer_ls180.v:157223.14-157223.39" + process $proc$issuer_ls180.v:157223$9264 + assign { } { } + assign $1\rb[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \rb $1\rb[63:0] + end + attribute \src "issuer_ls180.v:157516.7-157516.20" + process $proc$issuer_ls180.v:157516$9265 + assign { } { } + assign $1\xer_so[0:0] 1'0 + sync always + sync init + update \xer_so $1\xer_so[0:0] + end + attribute \src "issuer_ls180.v:157524.3-157525.35" + process $proc$issuer_ls180.v:157524$9120 + assign { } { } + assign $0\operation[1:0] \operation$next + sync posedge \coresync_clk + update \operation $0\operation[1:0] + end + attribute \src "issuer_ls180.v:157526.3-157527.49" + process $proc$issuer_ls180.v:157526$9121 + assign { } { } + assign $0\divisor_radicand[63:0] \divisor_radicand$next + sync posedge \coresync_clk + update \divisor_radicand $0\divisor_radicand[63:0] + end + attribute \src "issuer_ls180.v:157528.3-157529.33" + process $proc$issuer_ls180.v:157528$9122 + assign { } { } + assign $0\dividend[127:0] \dividend$next + sync posedge \coresync_clk + update \dividend $0\dividend[127:0] + end + attribute \src "issuer_ls180.v:157530.3-157531.39" + process $proc$issuer_ls180.v:157530$9123 + assign { } { } + assign $0\div_by_zero[0:0] \div_by_zero$next + sync posedge \coresync_clk + update \div_by_zero $0\div_by_zero[0:0] + end + attribute \src "issuer_ls180.v:157532.3-157533.43" + process $proc$issuer_ls180.v:157532$9124 + assign { } { } + assign $0\dive_abs_ov64[0:0] \dive_abs_ov64$next + sync posedge \coresync_clk + update \dive_abs_ov64 $0\dive_abs_ov64[0:0] + end + attribute \src "issuer_ls180.v:157534.3-157535.43" + process $proc$issuer_ls180.v:157534$9125 + assign { } { } + assign $0\dive_abs_ov32[0:0] \dive_abs_ov32$next + sync posedge \coresync_clk + update \dive_abs_ov32 $0\dive_abs_ov32[0:0] + end + attribute \src "issuer_ls180.v:157536.3-157537.41" + process $proc$issuer_ls180.v:157536$9126 + assign { } { } + assign $0\dividend_neg[0:0] \dividend_neg$next + sync posedge \coresync_clk + update \dividend_neg $0\dividend_neg[0:0] + end + attribute \src "issuer_ls180.v:157538.3-157539.39" + process $proc$issuer_ls180.v:157538$9127 + assign { } { } + assign $0\divisor_neg[0:0] \divisor_neg$next + sync posedge \coresync_clk + update \divisor_neg $0\divisor_neg[0:0] + end + attribute \src "issuer_ls180.v:157540.3-157541.29" + process $proc$issuer_ls180.v:157540$9128 + assign { } { } + assign $0\xer_so[0:0] \xer_so$next + sync posedge \coresync_clk + update \xer_so $0\xer_so[0:0] + end + attribute \src "issuer_ls180.v:157542.3-157543.21" + process $proc$issuer_ls180.v:157542$9129 + assign { } { } + assign $0\rb[63:0] \rb$next + sync posedge \coresync_clk + update \rb $0\rb[63:0] + end + attribute \src "issuer_ls180.v:157544.3-157545.21" + process $proc$issuer_ls180.v:157544$9130 + assign { } { } + assign $0\ra[63:0] \ra$next + sync posedge \coresync_clk + update \ra $0\ra[63:0] + end + attribute \src "issuer_ls180.v:157546.3-157547.59" + process $proc$issuer_ls180.v:157546$9131 + assign { } { } + assign $0\logical_op__insn_type[6:0] \logical_op__insn_type$next + sync posedge \coresync_clk + update \logical_op__insn_type $0\logical_op__insn_type[6:0] + end + attribute \src "issuer_ls180.v:157548.3-157549.55" + process $proc$issuer_ls180.v:157548$9132 + assign { } { } + assign $0\logical_op__fn_unit[11:0] \logical_op__fn_unit$next + sync posedge \coresync_clk + update \logical_op__fn_unit $0\logical_op__fn_unit[11:0] + end + attribute \src "issuer_ls180.v:157550.3-157551.69" + process $proc$issuer_ls180.v:157550$9133 + assign { } { } + assign $0\logical_op__imm_data__data[63:0] \logical_op__imm_data__data$next + sync posedge \coresync_clk + update \logical_op__imm_data__data $0\logical_op__imm_data__data[63:0] + end + attribute \src "issuer_ls180.v:157552.3-157553.65" + process $proc$issuer_ls180.v:157552$9134 + assign { } { } + assign $0\logical_op__imm_data__ok[0:0] \logical_op__imm_data__ok$next + sync posedge \coresync_clk + update \logical_op__imm_data__ok $0\logical_op__imm_data__ok[0:0] + end + attribute \src "issuer_ls180.v:157554.3-157555.53" + process $proc$issuer_ls180.v:157554$9135 + assign { } { } + assign $0\logical_op__rc__rc[0:0] \logical_op__rc__rc$next + sync posedge \coresync_clk + update \logical_op__rc__rc $0\logical_op__rc__rc[0:0] + end + attribute \src "issuer_ls180.v:157556.3-157557.53" + process $proc$issuer_ls180.v:157556$9136 + assign { } { } + assign $0\logical_op__rc__ok[0:0] \logical_op__rc__ok$next + sync posedge \coresync_clk + update \logical_op__rc__ok $0\logical_op__rc__ok[0:0] + end + attribute \src "issuer_ls180.v:157558.3-157559.53" + process $proc$issuer_ls180.v:157558$9137 + assign { } { } + assign $0\logical_op__oe__oe[0:0] \logical_op__oe__oe$next + sync posedge \coresync_clk + update \logical_op__oe__oe $0\logical_op__oe__oe[0:0] + end + attribute \src "issuer_ls180.v:157560.3-157561.53" + process $proc$issuer_ls180.v:157560$9138 + assign { } { } + assign $0\logical_op__oe__ok[0:0] \logical_op__oe__ok$next + sync posedge \coresync_clk + update \logical_op__oe__ok $0\logical_op__oe__ok[0:0] + end + attribute \src "issuer_ls180.v:157562.3-157563.59" + process $proc$issuer_ls180.v:157562$9139 + assign { } { } + assign $0\logical_op__invert_in[0:0] \logical_op__invert_in$next + sync posedge \coresync_clk + update \logical_op__invert_in $0\logical_op__invert_in[0:0] + end + attribute \src "issuer_ls180.v:157564.3-157565.53" + process $proc$issuer_ls180.v:157564$9140 + assign { } { } + assign $0\logical_op__zero_a[0:0] \logical_op__zero_a$next + sync posedge \coresync_clk + update \logical_op__zero_a $0\logical_op__zero_a[0:0] + end + attribute \src "issuer_ls180.v:157566.3-157567.63" + process $proc$issuer_ls180.v:157566$9141 + assign { } { } + assign $0\logical_op__input_carry[1:0] \logical_op__input_carry$next + sync posedge \coresync_clk + update \logical_op__input_carry $0\logical_op__input_carry[1:0] + end + attribute \src "issuer_ls180.v:157568.3-157569.61" + process $proc$issuer_ls180.v:157568$9142 + assign { } { } + assign $0\logical_op__invert_out[0:0] \logical_op__invert_out$next + sync posedge \coresync_clk + update \logical_op__invert_out $0\logical_op__invert_out[0:0] + end + attribute \src "issuer_ls180.v:157570.3-157571.59" + process $proc$issuer_ls180.v:157570$9143 + assign { } { } + assign $0\logical_op__write_cr0[0:0] \logical_op__write_cr0$next + sync posedge \coresync_clk + update \logical_op__write_cr0 $0\logical_op__write_cr0[0:0] + end + attribute \src "issuer_ls180.v:157572.3-157573.65" + process $proc$issuer_ls180.v:157572$9144 + assign { } { } + assign $0\logical_op__output_carry[0:0] \logical_op__output_carry$next + sync posedge \coresync_clk + update \logical_op__output_carry $0\logical_op__output_carry[0:0] + end + attribute \src "issuer_ls180.v:157574.3-157575.57" + process $proc$issuer_ls180.v:157574$9145 + assign { } { } + assign $0\logical_op__is_32bit[0:0] \logical_op__is_32bit$next + sync posedge \coresync_clk + update \logical_op__is_32bit $0\logical_op__is_32bit[0:0] + end + attribute \src "issuer_ls180.v:157576.3-157577.59" + process $proc$issuer_ls180.v:157576$9146 + assign { } { } + assign $0\logical_op__is_signed[0:0] \logical_op__is_signed$next + sync posedge \coresync_clk + update \logical_op__is_signed $0\logical_op__is_signed[0:0] + end + attribute \src "issuer_ls180.v:157578.3-157579.57" + process $proc$issuer_ls180.v:157578$9147 + assign { } { } + assign $0\logical_op__data_len[3:0] \logical_op__data_len$next + sync posedge \coresync_clk + update \logical_op__data_len $0\logical_op__data_len[3:0] + end + attribute \src "issuer_ls180.v:157580.3-157581.49" + process $proc$issuer_ls180.v:157580$9148 + assign { } { } + assign $0\logical_op__insn[31:0] \logical_op__insn$next + sync posedge \coresync_clk + update \logical_op__insn $0\logical_op__insn[31:0] + end + attribute \src "issuer_ls180.v:157582.3-157583.27" + process $proc$issuer_ls180.v:157582$9149 + assign { } { } + assign $0\muxid[1:0] \muxid$next + sync posedge \coresync_clk + update \muxid $0\muxid[1:0] + end + attribute \src "issuer_ls180.v:157584.3-157585.29" + process $proc$issuer_ls180.v:157584$9150 + assign { } { } + assign $0\r_busy[0:0] \r_busy$next + sync posedge \coresync_clk + update \r_busy $0\r_busy[0:0] + end + attribute \src "issuer_ls180.v:157692.3-157704.6" + process $proc$issuer_ls180.v:157692$9151 + assign { } { } + assign { } { } + assign $0\divisor_neg$next[0:0]$9152 $1\divisor_neg$next[0:0]$9153 + attribute \src "issuer_ls180.v:157693.5-157693.29" + switch \initial + attribute \src "issuer_ls180.v:157693.9-157693.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\divisor_neg$next[0:0]$9153 \divisor_neg$92 + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\divisor_neg$next[0:0]$9153 \divisor_neg$92 + case + assign $1\divisor_neg$next[0:0]$9153 \divisor_neg + end + sync always + update \divisor_neg$next $0\divisor_neg$next[0:0]$9152 + end + attribute \src "issuer_ls180.v:157705.3-157717.6" + process $proc$issuer_ls180.v:157705$9154 + assign { } { } + assign { } { } + assign $0\dividend_neg$next[0:0]$9155 $1\dividend_neg$next[0:0]$9156 + attribute \src "issuer_ls180.v:157706.5-157706.29" + switch \initial + attribute \src "issuer_ls180.v:157706.9-157706.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\dividend_neg$next[0:0]$9156 \dividend_neg$93 + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\dividend_neg$next[0:0]$9156 \dividend_neg$93 + case + assign $1\dividend_neg$next[0:0]$9156 \dividend_neg + end + sync always + update \dividend_neg$next $0\dividend_neg$next[0:0]$9155 + end + attribute \src "issuer_ls180.v:157718.3-157730.6" + process $proc$issuer_ls180.v:157718$9157 + assign { } { } + assign { } { } + assign $0\dive_abs_ov32$next[0:0]$9158 $1\dive_abs_ov32$next[0:0]$9159 + attribute \src "issuer_ls180.v:157719.5-157719.29" + switch \initial + attribute \src "issuer_ls180.v:157719.9-157719.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\dive_abs_ov32$next[0:0]$9159 \dive_abs_ov32$94 + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\dive_abs_ov32$next[0:0]$9159 \dive_abs_ov32$94 + case + assign $1\dive_abs_ov32$next[0:0]$9159 \dive_abs_ov32 + end + sync always + update \dive_abs_ov32$next $0\dive_abs_ov32$next[0:0]$9158 + end + attribute \src "issuer_ls180.v:157731.3-157743.6" + process $proc$issuer_ls180.v:157731$9160 + assign { } { } + assign { } { } + assign $0\dive_abs_ov64$next[0:0]$9161 $1\dive_abs_ov64$next[0:0]$9162 + attribute \src "issuer_ls180.v:157732.5-157732.29" + switch \initial + attribute \src "issuer_ls180.v:157732.9-157732.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\dive_abs_ov64$next[0:0]$9162 \dive_abs_ov64$95 + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\dive_abs_ov64$next[0:0]$9162 \dive_abs_ov64$95 + case + assign $1\dive_abs_ov64$next[0:0]$9162 \dive_abs_ov64 + end + sync always + update \dive_abs_ov64$next $0\dive_abs_ov64$next[0:0]$9161 + end + attribute \src "issuer_ls180.v:157744.3-157756.6" + process $proc$issuer_ls180.v:157744$9163 + assign { } { } + assign { } { } + assign $0\div_by_zero$next[0:0]$9164 $1\div_by_zero$next[0:0]$9165 + attribute \src "issuer_ls180.v:157745.5-157745.29" + switch \initial + attribute \src "issuer_ls180.v:157745.9-157745.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\div_by_zero$next[0:0]$9165 \div_by_zero$96 + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\div_by_zero$next[0:0]$9165 \div_by_zero$96 + case + assign $1\div_by_zero$next[0:0]$9165 \div_by_zero + end + sync always + update \div_by_zero$next $0\div_by_zero$next[0:0]$9164 + end + attribute \src "issuer_ls180.v:157757.3-157769.6" + process $proc$issuer_ls180.v:157757$9166 + assign { } { } + assign { } { } + assign $0\dividend$next[127:0]$9167 $1\dividend$next[127:0]$9168 + attribute \src "issuer_ls180.v:157758.5-157758.29" + switch \initial + attribute \src "issuer_ls180.v:157758.9-157758.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\dividend$next[127:0]$9168 \dividend$97 + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\dividend$next[127:0]$9168 \dividend$97 + case + assign $1\dividend$next[127:0]$9168 \dividend + end + sync always + update \dividend$next $0\dividend$next[127:0]$9167 + end + attribute \src "issuer_ls180.v:157770.3-157782.6" + process $proc$issuer_ls180.v:157770$9169 + assign { } { } + assign { } { } + assign $0\divisor_radicand$next[63:0]$9170 $1\divisor_radicand$next[63:0]$9171 + attribute \src "issuer_ls180.v:157771.5-157771.29" + switch \initial + attribute \src "issuer_ls180.v:157771.9-157771.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\divisor_radicand$next[63:0]$9171 \divisor_radicand$98 + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\divisor_radicand$next[63:0]$9171 \divisor_radicand$98 + case + assign $1\divisor_radicand$next[63:0]$9171 \divisor_radicand + end + sync always + update \divisor_radicand$next $0\divisor_radicand$next[63:0]$9170 + end + attribute \src "issuer_ls180.v:157783.3-157795.6" + process $proc$issuer_ls180.v:157783$9172 + assign { } { } + assign { } { } + assign $0\operation$next[1:0]$9173 $1\operation$next[1:0]$9174 + attribute \src "issuer_ls180.v:157784.5-157784.29" + switch \initial + attribute \src "issuer_ls180.v:157784.9-157784.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\operation$next[1:0]$9174 \operation$99 + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\operation$next[1:0]$9174 \operation$99 + case + assign $1\operation$next[1:0]$9174 \operation + end + sync always + update \operation$next $0\operation$next[1:0]$9173 + end + attribute \src "issuer_ls180.v:157796.3-157813.6" + process $proc$issuer_ls180.v:157796$9175 + assign { } { } + assign { } { } + assign { } { } + assign $0\r_busy$next[0:0]$9176 $2\r_busy$next[0:0]$9178 + attribute \src "issuer_ls180.v:157797.5-157797.29" + switch \initial + attribute \src "issuer_ls180.v:157797.9-157797.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\r_busy$next[0:0]$9177 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\r_busy$next[0:0]$9177 1'0 + case + assign $1\r_busy$next[0:0]$9177 \r_busy + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\r_busy$next[0:0]$9178 1'0 + case + assign $2\r_busy$next[0:0]$9178 $1\r_busy$next[0:0]$9177 + end + sync always + update \r_busy$next $0\r_busy$next[0:0]$9176 + end + attribute \src "issuer_ls180.v:157814.3-157826.6" + process $proc$issuer_ls180.v:157814$9179 + assign { } { } + assign { } { } + assign $0\muxid$next[1:0]$9180 $1\muxid$next[1:0]$9181 + attribute \src "issuer_ls180.v:157815.5-157815.29" + switch \initial + attribute \src "issuer_ls180.v:157815.9-157815.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\muxid$next[1:0]$9181 \muxid$68 + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\muxid$next[1:0]$9181 \muxid$68 + case + assign $1\muxid$next[1:0]$9181 \muxid + end + sync always + update \muxid$next $0\muxid$next[1:0]$9180 + end + attribute \src "issuer_ls180.v:157827.3-157868.6" + process $proc$issuer_ls180.v:157827$9182 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\logical_op__data_len$next[3:0]$9183 $1\logical_op__data_len$next[3:0]$9201 + assign $0\logical_op__fn_unit$next[11:0]$9184 $1\logical_op__fn_unit$next[11:0]$9202 + assign { } { } + assign { } { } + assign $0\logical_op__input_carry$next[1:0]$9187 $1\logical_op__input_carry$next[1:0]$9205 + assign $0\logical_op__insn$next[31:0]$9188 $1\logical_op__insn$next[31:0]$9206 + assign $0\logical_op__insn_type$next[6:0]$9189 $1\logical_op__insn_type$next[6:0]$9207 + assign $0\logical_op__invert_in$next[0:0]$9190 $1\logical_op__invert_in$next[0:0]$9208 + assign $0\logical_op__invert_out$next[0:0]$9191 $1\logical_op__invert_out$next[0:0]$9209 + assign $0\logical_op__is_32bit$next[0:0]$9192 $1\logical_op__is_32bit$next[0:0]$9210 + assign $0\logical_op__is_signed$next[0:0]$9193 $1\logical_op__is_signed$next[0:0]$9211 + assign { } { } + assign { } { } + assign $0\logical_op__output_carry$next[0:0]$9196 $1\logical_op__output_carry$next[0:0]$9214 + assign { } { } + assign { } { } + assign $0\logical_op__write_cr0$next[0:0]$9199 $1\logical_op__write_cr0$next[0:0]$9217 + assign $0\logical_op__zero_a$next[0:0]$9200 $1\logical_op__zero_a$next[0:0]$9218 + assign $0\logical_op__imm_data__data$next[63:0]$9185 $2\logical_op__imm_data__data$next[63:0]$9219 + assign $0\logical_op__imm_data__ok$next[0:0]$9186 $2\logical_op__imm_data__ok$next[0:0]$9220 + assign $0\logical_op__oe__oe$next[0:0]$9194 $2\logical_op__oe__oe$next[0:0]$9221 + assign $0\logical_op__oe__ok$next[0:0]$9195 $2\logical_op__oe__ok$next[0:0]$9222 + assign $0\logical_op__rc__ok$next[0:0]$9197 $2\logical_op__rc__ok$next[0:0]$9223 + assign $0\logical_op__rc__rc$next[0:0]$9198 $2\logical_op__rc__rc$next[0:0]$9224 + attribute \src "issuer_ls180.v:157828.5-157828.29" + switch \initial + attribute \src "issuer_ls180.v:157828.9-157828.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'-1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { $1\logical_op__insn$next[31:0]$9206 $1\logical_op__data_len$next[3:0]$9201 $1\logical_op__is_signed$next[0:0]$9211 $1\logical_op__is_32bit$next[0:0]$9210 $1\logical_op__output_carry$next[0:0]$9214 $1\logical_op__write_cr0$next[0:0]$9217 $1\logical_op__invert_out$next[0:0]$9209 $1\logical_op__input_carry$next[1:0]$9205 $1\logical_op__zero_a$next[0:0]$9218 $1\logical_op__invert_in$next[0:0]$9208 $1\logical_op__oe__ok$next[0:0]$9213 $1\logical_op__oe__oe$next[0:0]$9212 $1\logical_op__rc__ok$next[0:0]$9215 $1\logical_op__rc__rc$next[0:0]$9216 $1\logical_op__imm_data__ok$next[0:0]$9204 $1\logical_op__imm_data__data$next[63:0]$9203 $1\logical_op__fn_unit$next[11:0]$9202 $1\logical_op__insn_type$next[6:0]$9207 } { \logical_op__insn$86 \logical_op__data_len$85 \logical_op__is_signed$84 \logical_op__is_32bit$83 \logical_op__output_carry$82 \logical_op__write_cr0$81 \logical_op__invert_out$80 \logical_op__input_carry$79 \logical_op__zero_a$78 \logical_op__invert_in$77 \logical_op__oe__ok$76 \logical_op__oe__oe$75 \logical_op__rc__ok$74 \logical_op__rc__rc$73 \logical_op__imm_data__ok$72 \logical_op__imm_data__data$71 \logical_op__fn_unit$70 \logical_op__insn_type$69 } + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'1- + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { $1\logical_op__insn$next[31:0]$9206 $1\logical_op__data_len$next[3:0]$9201 $1\logical_op__is_signed$next[0:0]$9211 $1\logical_op__is_32bit$next[0:0]$9210 $1\logical_op__output_carry$next[0:0]$9214 $1\logical_op__write_cr0$next[0:0]$9217 $1\logical_op__invert_out$next[0:0]$9209 $1\logical_op__input_carry$next[1:0]$9205 $1\logical_op__zero_a$next[0:0]$9218 $1\logical_op__invert_in$next[0:0]$9208 $1\logical_op__oe__ok$next[0:0]$9213 $1\logical_op__oe__oe$next[0:0]$9212 $1\logical_op__rc__ok$next[0:0]$9215 $1\logical_op__rc__rc$next[0:0]$9216 $1\logical_op__imm_data__ok$next[0:0]$9204 $1\logical_op__imm_data__data$next[63:0]$9203 $1\logical_op__fn_unit$next[11:0]$9202 $1\logical_op__insn_type$next[6:0]$9207 } { \logical_op__insn$86 \logical_op__data_len$85 \logical_op__is_signed$84 \logical_op__is_32bit$83 \logical_op__output_carry$82 \logical_op__write_cr0$81 \logical_op__invert_out$80 \logical_op__input_carry$79 \logical_op__zero_a$78 \logical_op__invert_in$77 \logical_op__oe__ok$76 \logical_op__oe__oe$75 \logical_op__rc__ok$74 \logical_op__rc__rc$73 \logical_op__imm_data__ok$72 \logical_op__imm_data__data$71 \logical_op__fn_unit$70 \logical_op__insn_type$69 } + case + assign $1\logical_op__data_len$next[3:0]$9201 \logical_op__data_len + assign $1\logical_op__fn_unit$next[11:0]$9202 \logical_op__fn_unit + assign $1\logical_op__imm_data__data$next[63:0]$9203 \logical_op__imm_data__data + assign $1\logical_op__imm_data__ok$next[0:0]$9204 \logical_op__imm_data__ok + assign $1\logical_op__input_carry$next[1:0]$9205 \logical_op__input_carry + assign $1\logical_op__insn$next[31:0]$9206 \logical_op__insn + assign $1\logical_op__insn_type$next[6:0]$9207 \logical_op__insn_type + assign $1\logical_op__invert_in$next[0:0]$9208 \logical_op__invert_in + assign $1\logical_op__invert_out$next[0:0]$9209 \logical_op__invert_out + assign $1\logical_op__is_32bit$next[0:0]$9210 \logical_op__is_32bit + assign $1\logical_op__is_signed$next[0:0]$9211 \logical_op__is_signed + assign $1\logical_op__oe__oe$next[0:0]$9212 \logical_op__oe__oe + assign $1\logical_op__oe__ok$next[0:0]$9213 \logical_op__oe__ok + assign $1\logical_op__output_carry$next[0:0]$9214 \logical_op__output_carry + assign $1\logical_op__rc__ok$next[0:0]$9215 \logical_op__rc__ok + assign $1\logical_op__rc__rc$next[0:0]$9216 \logical_op__rc__rc + assign $1\logical_op__write_cr0$next[0:0]$9217 \logical_op__write_cr0 + assign $1\logical_op__zero_a$next[0:0]$9218 \logical_op__zero_a + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $2\logical_op__imm_data__data$next[63:0]$9219 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\logical_op__imm_data__ok$next[0:0]$9220 1'0 + assign $2\logical_op__rc__rc$next[0:0]$9224 1'0 + assign $2\logical_op__rc__ok$next[0:0]$9223 1'0 + assign $2\logical_op__oe__oe$next[0:0]$9221 1'0 + assign $2\logical_op__oe__ok$next[0:0]$9222 1'0 + case + assign $2\logical_op__imm_data__data$next[63:0]$9219 $1\logical_op__imm_data__data$next[63:0]$9203 + assign $2\logical_op__imm_data__ok$next[0:0]$9220 $1\logical_op__imm_data__ok$next[0:0]$9204 + assign $2\logical_op__oe__oe$next[0:0]$9221 $1\logical_op__oe__oe$next[0:0]$9212 + assign $2\logical_op__oe__ok$next[0:0]$9222 $1\logical_op__oe__ok$next[0:0]$9213 + assign $2\logical_op__rc__ok$next[0:0]$9223 $1\logical_op__rc__ok$next[0:0]$9215 + assign $2\logical_op__rc__rc$next[0:0]$9224 $1\logical_op__rc__rc$next[0:0]$9216 + end + sync always + update \logical_op__data_len$next $0\logical_op__data_len$next[3:0]$9183 + update \logical_op__fn_unit$next $0\logical_op__fn_unit$next[11:0]$9184 + update \logical_op__imm_data__data$next $0\logical_op__imm_data__data$next[63:0]$9185 + update \logical_op__imm_data__ok$next $0\logical_op__imm_data__ok$next[0:0]$9186 + update \logical_op__input_carry$next $0\logical_op__input_carry$next[1:0]$9187 + update \logical_op__insn$next $0\logical_op__insn$next[31:0]$9188 + update \logical_op__insn_type$next $0\logical_op__insn_type$next[6:0]$9189 + update \logical_op__invert_in$next $0\logical_op__invert_in$next[0:0]$9190 + update \logical_op__invert_out$next $0\logical_op__invert_out$next[0:0]$9191 + update \logical_op__is_32bit$next $0\logical_op__is_32bit$next[0:0]$9192 + update \logical_op__is_signed$next $0\logical_op__is_signed$next[0:0]$9193 + update \logical_op__oe__oe$next $0\logical_op__oe__oe$next[0:0]$9194 + update \logical_op__oe__ok$next $0\logical_op__oe__ok$next[0:0]$9195 + update \logical_op__output_carry$next $0\logical_op__output_carry$next[0:0]$9196 + update \logical_op__rc__ok$next $0\logical_op__rc__ok$next[0:0]$9197 + update \logical_op__rc__rc$next $0\logical_op__rc__rc$next[0:0]$9198 + update \logical_op__write_cr0$next $0\logical_op__write_cr0$next[0:0]$9199 + update \logical_op__zero_a$next $0\logical_op__zero_a$next[0:0]$9200 + end + attribute \src "issuer_ls180.v:157869.3-157881.6" + process $proc$issuer_ls180.v:157869$9225 + assign { } { } + assign { } { } + assign $0\ra$next[63:0]$9226 $1\ra$next[63:0]$9227 + attribute \src "issuer_ls180.v:157870.5-157870.29" + switch \initial + attribute \src "issuer_ls180.v:157870.9-157870.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\ra$next[63:0]$9227 \ra$87 + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\ra$next[63:0]$9227 \ra$87 + case + assign $1\ra$next[63:0]$9227 \ra + end + sync always + update \ra$next $0\ra$next[63:0]$9226 + end + attribute \src "issuer_ls180.v:157882.3-157894.6" + process $proc$issuer_ls180.v:157882$9228 + assign { } { } + assign { } { } + assign $0\rb$next[63:0]$9229 $1\rb$next[63:0]$9230 + attribute \src "issuer_ls180.v:157883.5-157883.29" + switch \initial + attribute \src "issuer_ls180.v:157883.9-157883.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\rb$next[63:0]$9230 \rb$89 + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\rb$next[63:0]$9230 \rb$89 + case + assign $1\rb$next[63:0]$9230 \rb + end + sync always + update \rb$next $0\rb$next[63:0]$9229 + end + attribute \src "issuer_ls180.v:157895.3-157907.6" + process $proc$issuer_ls180.v:157895$9231 + assign { } { } + assign { } { } + assign $0\xer_so$next[0:0]$9232 $1\xer_so$next[0:0]$9233 + attribute \src "issuer_ls180.v:157896.5-157896.29" + switch \initial + attribute \src "issuer_ls180.v:157896.9-157896.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" + switch { \n_i_rdy_data \p_valid_i_p_ready_o } + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\xer_so$next[0:0]$9233 \xer_so$91 + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\xer_so$next[0:0]$9233 \xer_so$91 + case + assign $1\xer_so$next[0:0]$9233 \xer_so + end + sync always + update \xer_so$next $0\xer_so$next[0:0]$9232 + end + connect \$66 $and$issuer_ls180.v:157523$9119_Y + connect \ra$88 64'0000000000000000000000000000000000000000000000000000000000000000 + connect \rb$90 64'0000000000000000000000000000000000000000000000000000000000000000 + connect \p_ready_o \n_i_rdy_data + connect \n_valid_o \r_busy + connect \operation$99 \setup_stage_operation + connect \divisor_radicand$98 \setup_stage_divisor_radicand + connect \dividend$97 \setup_stage_dividend + connect \div_by_zero$96 \setup_stage_div_by_zero + connect \dive_abs_ov64$95 \setup_stage_dive_abs_ov64 + connect \dive_abs_ov32$94 \setup_stage_dive_abs_ov32 + connect \dividend_neg$93 \setup_stage_dividend_neg + connect \divisor_neg$92 \setup_stage_divisor_neg + connect \xer_so$91 \setup_stage_xer_so$64 + connect \rb$89 64'0000000000000000000000000000000000000000000000000000000000000000 + connect \ra$87 64'0000000000000000000000000000000000000000000000000000000000000000 + connect { \logical_op__insn$86 \logical_op__data_len$85 \logical_op__is_signed$84 \logical_op__is_32bit$83 \logical_op__output_carry$82 \logical_op__write_cr0$81 \logical_op__invert_out$80 \logical_op__input_carry$79 \logical_op__zero_a$78 \logical_op__invert_in$77 \logical_op__oe__ok$76 \logical_op__oe__oe$75 \logical_op__rc__ok$74 \logical_op__rc__rc$73 \logical_op__imm_data__ok$72 \logical_op__imm_data__data$71 \logical_op__fn_unit$70 \logical_op__insn_type$69 } { \setup_stage_logical_op__insn$63 \setup_stage_logical_op__data_len$62 \setup_stage_logical_op__is_signed$61 \setup_stage_logical_op__is_32bit$60 \setup_stage_logical_op__output_carry$59 \setup_stage_logical_op__write_cr0$58 \setup_stage_logical_op__invert_out$57 \setup_stage_logical_op__input_carry$56 \setup_stage_logical_op__zero_a$55 \setup_stage_logical_op__invert_in$54 \setup_stage_logical_op__oe__ok$53 \setup_stage_logical_op__oe__oe$52 \setup_stage_logical_op__rc__ok$51 \setup_stage_logical_op__rc__rc$50 \setup_stage_logical_op__imm_data__ok$49 \setup_stage_logical_op__imm_data__data$48 \setup_stage_logical_op__fn_unit$47 \setup_stage_logical_op__insn_type$46 } + connect \muxid$68 \setup_stage_muxid$45 + connect \p_valid_i_p_ready_o \$66 + connect \n_i_rdy_data \n_ready_i + connect \p_valid_i$65 \p_valid_i + connect \setup_stage_xer_so \input_xer_so$44 + connect \setup_stage_rb \input_rb$43 + connect \setup_stage_ra \input_ra$42 + connect { \setup_stage_logical_op__insn \setup_stage_logical_op__data_len \setup_stage_logical_op__is_signed \setup_stage_logical_op__is_32bit \setup_stage_logical_op__output_carry \setup_stage_logical_op__write_cr0 \setup_stage_logical_op__invert_out \setup_stage_logical_op__input_carry \setup_stage_logical_op__zero_a \setup_stage_logical_op__invert_in \setup_stage_logical_op__oe__ok \setup_stage_logical_op__oe__oe \setup_stage_logical_op__rc__ok \setup_stage_logical_op__rc__rc \setup_stage_logical_op__imm_data__ok \setup_stage_logical_op__imm_data__data \setup_stage_logical_op__fn_unit \setup_stage_logical_op__insn_type } { \input_logical_op__insn$41 \input_logical_op__data_len$40 \input_logical_op__is_signed$39 \input_logical_op__is_32bit$38 \input_logical_op__output_carry$37 \input_logical_op__write_cr0$36 \input_logical_op__invert_out$35 \input_logical_op__input_carry$34 \input_logical_op__zero_a$33 \input_logical_op__invert_in$32 \input_logical_op__oe__ok$31 \input_logical_op__oe__oe$30 \input_logical_op__rc__ok$29 \input_logical_op__rc__rc$28 \input_logical_op__imm_data__ok$27 \input_logical_op__imm_data__data$26 \input_logical_op__fn_unit$25 \input_logical_op__insn_type$24 } + connect \setup_stage_muxid \input_muxid$23 + connect \input_xer_so \xer_so$22 + connect \input_rb \rb$21 + connect \input_ra \ra$20 + connect { \input_logical_op__insn \input_logical_op__data_len \input_logical_op__is_signed \input_logical_op__is_32bit \input_logical_op__output_carry \input_logical_op__write_cr0 \input_logical_op__invert_out \input_logical_op__input_carry \input_logical_op__zero_a \input_logical_op__invert_in \input_logical_op__oe__ok \input_logical_op__oe__oe \input_logical_op__rc__ok \input_logical_op__rc__rc \input_logical_op__imm_data__ok \input_logical_op__imm_data__data \input_logical_op__fn_unit \input_logical_op__insn_type } { \logical_op__insn$19 \logical_op__data_len$18 \logical_op__is_signed$17 \logical_op__is_32bit$16 \logical_op__output_carry$15 \logical_op__write_cr0$14 \logical_op__invert_out$13 \logical_op__input_carry$12 \logical_op__zero_a$11 \logical_op__invert_in$10 \logical_op__oe__ok$9 \logical_op__oe__oe$8 \logical_op__rc__ok$7 \logical_op__rc__rc$6 \logical_op__imm_data__ok$5 \logical_op__imm_data__data$4 \logical_op__fn_unit$3 \logical_op__insn_type$2 } + connect \input_muxid \muxid$1 +end +attribute \src "issuer_ls180.v:157942.1-158584.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.fus.logical0.alu_logical0.logical_pipe1.main.popcount" +attribute \generator "nMigen" +module \popcount + attribute \src "issuer_ls180.v:157943.7-157943.20" + wire $0\initial[0:0] + attribute \src "issuer_ls180.v:158431.3-158457.6" + wire width 64 $0\o[63:0] + attribute \src "issuer_ls180.v:158431.3-158457.6" + wire width 64 $1\o[63:0] + attribute \src "issuer_ls180.v:158355.19-158355.132" + wire width 4 $add$issuer_ls180.v:158355$9266_Y + attribute \src "issuer_ls180.v:158356.19-158356.132" + wire width 4 $add$issuer_ls180.v:158356$9267_Y + attribute \src "issuer_ls180.v:158357.19-158357.132" + wire width 4 $add$issuer_ls180.v:158357$9268_Y + attribute \src "issuer_ls180.v:158358.19-158358.132" + wire width 4 $add$issuer_ls180.v:158358$9269_Y + attribute \src "issuer_ls180.v:158359.19-158359.134" + wire width 4 $add$issuer_ls180.v:158359$9270_Y + attribute \src "issuer_ls180.v:158360.19-158360.134" + wire width 4 $add$issuer_ls180.v:158360$9271_Y + attribute \src "issuer_ls180.v:158361.18-158361.125" + wire width 3 $add$issuer_ls180.v:158361$9272_Y + attribute \src "issuer_ls180.v:158362.19-158362.134" + wire width 4 $add$issuer_ls180.v:158362$9273_Y + attribute \src "issuer_ls180.v:158363.19-158363.134" + wire width 4 $add$issuer_ls180.v:158363$9274_Y + attribute \src "issuer_ls180.v:158364.19-158364.134" + wire width 4 $add$issuer_ls180.v:158364$9275_Y + attribute \src "issuer_ls180.v:158365.19-158365.134" + wire width 4 $add$issuer_ls180.v:158365$9276_Y + attribute \src "issuer_ls180.v:158366.19-158366.134" + wire width 4 $add$issuer_ls180.v:158366$9277_Y + attribute \src "issuer_ls180.v:158367.19-158367.134" + wire width 4 $add$issuer_ls180.v:158367$9278_Y + attribute \src "issuer_ls180.v:158368.19-158368.134" + wire width 4 $add$issuer_ls180.v:158368$9279_Y + attribute \src "issuer_ls180.v:158369.19-158369.134" + wire width 4 $add$issuer_ls180.v:158369$9280_Y + attribute \src "issuer_ls180.v:158370.19-158370.134" + wire width 4 $add$issuer_ls180.v:158370$9281_Y + attribute \src "issuer_ls180.v:158371.19-158371.132" + wire width 5 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connect \Y $add$issuer_ls180.v:158373$9284_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $add$issuer_ls180.v:158374$9285 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 5 + connect \A { 2'00 \pop_3_4 } + connect \B { 2'00 \pop_3_5 } + connect \Y $add$issuer_ls180.v:158374$9285_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $add$issuer_ls180.v:158375$9286 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 5 + connect \A { 2'00 \pop_3_6 } + connect \B { 2'00 \pop_3_7 } + connect \Y $add$issuer_ls180.v:158375$9286_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $add$issuer_ls180.v:158376$9287 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter 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parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 5 + connect \A { 2'00 \pop_3_14 } + connect \B { 2'00 \pop_3_15 } + connect \Y $add$issuer_ls180.v:158379$9290_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $add$issuer_ls180.v:158380$9291 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 6 + connect \A { 2'00 \pop_4_0 } + connect \B { 2'00 \pop_4_1 } + connect \Y $add$issuer_ls180.v:158380$9291_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $add$issuer_ls180.v:158381$9292 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 6 + connect \A { 2'00 \pop_4_2 } + connect \B { 2'00 \pop_4_3 } + connect \Y $add$issuer_ls180.v:158381$9292_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $add$issuer_ls180.v:158382$9293 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 6 + connect \A { 2'00 \pop_4_4 } + connect \B { 2'00 \pop_4_5 } + connect \Y $add$issuer_ls180.v:158382$9293_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $add$issuer_ls180.v:158383$9294 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A { 2'00 \a [10] } + connect \B { 2'00 \a [11] } + connect \Y $add$issuer_ls180.v:158383$9294_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $add$issuer_ls180.v:158384$9295 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 6 + connect \A { 2'00 \pop_4_6 } + connect \B { 2'00 \pop_4_7 } + connect \Y $add$issuer_ls180.v:158384$9295_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $add$issuer_ls180.v:158385$9296 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 7 + connect \A { 2'00 \pop_5_0 } + connect \B { 2'00 \pop_5_1 } + connect \Y $add$issuer_ls180.v:158385$9296_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $add$issuer_ls180.v:158386$9297 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 7 + connect \A { 2'00 \pop_5_2 } + connect \B { 2'00 \pop_5_3 } + connect \Y $add$issuer_ls180.v:158386$9297_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $add$issuer_ls180.v:158387$9298 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 8 + connect \A { 2'00 \pop_6_0 } + connect \B { 2'00 \pop_6_1 } + connect \Y $add$issuer_ls180.v:158387$9298_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $add$issuer_ls180.v:158398$9317 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A { 2'00 \a [12] } + connect \B { 2'00 \a [13] } + connect \Y $add$issuer_ls180.v:158398$9317_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $add$issuer_ls180.v:158402$9324 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A { 2'00 \a [14] } + connect \B { 2'00 \a [15] } + connect \Y $add$issuer_ls180.v:158402$9324_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $add$issuer_ls180.v:158403$9325 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A { 2'00 \a [16] } + connect \B { 2'00 \a [17] } + connect \Y $add$issuer_ls180.v:158403$9325_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $add$issuer_ls180.v:158404$9326 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A { 2'00 \a [0] } + connect \B { 2'00 \a [1] } + connect \Y $add$issuer_ls180.v:158404$9326_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $add$issuer_ls180.v:158405$9327 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A { 2'00 \a [18] } + connect \B { 2'00 \a [19] } + connect \Y $add$issuer_ls180.v:158405$9327_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $add$issuer_ls180.v:158406$9328 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A { 2'00 \a [20] } + connect \B { 2'00 \a [21] } + connect \Y $add$issuer_ls180.v:158406$9328_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $add$issuer_ls180.v:158407$9329 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A { 2'00 \a [22] } + connect \B { 2'00 \a [23] } + connect \Y $add$issuer_ls180.v:158407$9329_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $add$issuer_ls180.v:158408$9330 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A { 2'00 \a [24] } + connect \B { 2'00 \a [25] } + connect \Y $add$issuer_ls180.v:158408$9330_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $add$issuer_ls180.v:158409$9331 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A { 2'00 \a [26] } + connect \B { 2'00 \a [27] } + connect \Y $add$issuer_ls180.v:158409$9331_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $add$issuer_ls180.v:158410$9332 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A { 2'00 \a [28] } + connect \B { 2'00 \a [29] } + connect \Y $add$issuer_ls180.v:158410$9332_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $add$issuer_ls180.v:158411$9333 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A { 2'00 \a [30] } + connect \B { 2'00 \a [31] } + connect \Y $add$issuer_ls180.v:158411$9333_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $add$issuer_ls180.v:158412$9334 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A { 2'00 \a [32] } + connect \B { 2'00 \a [33] } + connect \Y $add$issuer_ls180.v:158412$9334_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $add$issuer_ls180.v:158413$9335 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A { 2'00 \a [34] } + connect \B { 2'00 \a [35] } + connect \Y $add$issuer_ls180.v:158413$9335_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $add$issuer_ls180.v:158414$9336 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A { 2'00 \a [36] } + connect \B { 2'00 \a [37] } + connect \Y $add$issuer_ls180.v:158414$9336_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $add$issuer_ls180.v:158415$9337 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A { 2'00 \a [2] } + connect \B { 2'00 \a [3] } + connect \Y $add$issuer_ls180.v:158415$9337_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $add$issuer_ls180.v:158416$9338 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A { 2'00 \a [38] } + connect \B { 2'00 \a [39] } + connect \Y $add$issuer_ls180.v:158416$9338_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $add$issuer_ls180.v:158417$9339 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A { 2'00 \a [40] } + connect \B { 2'00 \a [41] } + connect \Y $add$issuer_ls180.v:158417$9339_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $add$issuer_ls180.v:158418$9340 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A { 2'00 \a [42] } + connect \B { 2'00 \a [43] } + connect \Y $add$issuer_ls180.v:158418$9340_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $add$issuer_ls180.v:158419$9341 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A { 2'00 \a [44] } + connect \B { 2'00 \a [45] } + connect \Y $add$issuer_ls180.v:158419$9341_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $add$issuer_ls180.v:158420$9342 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A { 2'00 \a [46] } + connect \B { 2'00 \a [47] } + connect \Y $add$issuer_ls180.v:158420$9342_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $add$issuer_ls180.v:158421$9343 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A { 2'00 \a [48] } + connect \B { 2'00 \a [49] } + connect \Y $add$issuer_ls180.v:158421$9343_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $add$issuer_ls180.v:158422$9344 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A { 2'00 \a [50] } + connect \B { 2'00 \a [51] } + connect \Y $add$issuer_ls180.v:158422$9344_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $add$issuer_ls180.v:158423$9345 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A { 2'00 \a [52] } + connect \B { 2'00 \a [53] } + connect \Y $add$issuer_ls180.v:158423$9345_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $add$issuer_ls180.v:158424$9346 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A { 2'00 \a [54] } + connect \B { 2'00 \a [55] } + connect \Y $add$issuer_ls180.v:158424$9346_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $add$issuer_ls180.v:158425$9347 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A { 2'00 \a [56] } + connect \B { 2'00 \a [57] } + connect \Y $add$issuer_ls180.v:158425$9347_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $add$issuer_ls180.v:158426$9348 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A { 2'00 \a [4] } + connect \B { 2'00 \a [5] } + connect \Y $add$issuer_ls180.v:158426$9348_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $add$issuer_ls180.v:158427$9349 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A { 2'00 \a [58] } + connect \B { 2'00 \a [59] } + connect \Y $add$issuer_ls180.v:158427$9349_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $add$issuer_ls180.v:158428$9350 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A { 2'00 \a [60] } + connect \B { 2'00 \a [61] } + connect \Y $add$issuer_ls180.v:158428$9350_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $add$issuer_ls180.v:158429$9351 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A { 2'00 \a [62] } + connect \B { 2'00 \a [63] } + connect \Y $add$issuer_ls180.v:158429$9351_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" + cell $add $add$issuer_ls180.v:158430$9352 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A { 2'00 \pop_2_0 } + connect \B { 2'00 \pop_2_1 } + connect \Y $add$issuer_ls180.v:158430$9352_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:55" + cell $eq $eq$issuer_ls180.v:158388$9299 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \data_len + connect \B 1'1 + connect \Y $eq$issuer_ls180.v:158388$9299_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:59" + cell $eq $eq$issuer_ls180.v:158389$9300 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \data_len + connect \B 3'100 + connect \Y $eq$issuer_ls180.v:158389$9300_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + cell $pos $extend$issuer_ls180.v:158390$9301 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 8 + connect \A \pop_4_0 + connect \Y $extend$issuer_ls180.v:158390$9301_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + cell $pos $extend$issuer_ls180.v:158391$9303 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 8 + connect \A \pop_4_1 + connect \Y $extend$issuer_ls180.v:158391$9303_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + cell $pos $extend$issuer_ls180.v:158392$9305 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 8 + connect \A \pop_4_2 + connect \Y $extend$issuer_ls180.v:158392$9305_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + cell $pos $extend$issuer_ls180.v:158393$9307 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 8 + connect \A \pop_4_3 + connect \Y $extend$issuer_ls180.v:158393$9307_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + cell $pos $extend$issuer_ls180.v:158394$9309 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 8 + connect \A \pop_4_4 + connect \Y $extend$issuer_ls180.v:158394$9309_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + cell $pos $extend$issuer_ls180.v:158395$9311 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 8 + connect \A \pop_4_5 + connect \Y $extend$issuer_ls180.v:158395$9311_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + cell $pos $extend$issuer_ls180.v:158396$9313 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 8 + connect \A \pop_4_6 + connect \Y $extend$issuer_ls180.v:158396$9313_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + cell $pos $extend$issuer_ls180.v:158397$9315 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 8 + connect \A \pop_4_7 + connect \Y $extend$issuer_ls180.v:158397$9315_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + cell $pos $extend$issuer_ls180.v:158399$9318 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \Y_WIDTH 32 + connect \A \pop_6_0 + connect \Y $extend$issuer_ls180.v:158399$9318_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + cell $pos $extend$issuer_ls180.v:158400$9320 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \Y_WIDTH 32 + connect \A \pop_6_1 + connect \Y $extend$issuer_ls180.v:158400$9320_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + cell $pos $extend$issuer_ls180.v:158401$9322 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \Y_WIDTH 64 + connect \A \pop_7_0 + connect \Y $extend$issuer_ls180.v:158401$9322_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + cell $pos $pos$issuer_ls180.v:158390$9302 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 8 + connect \A $extend$issuer_ls180.v:158390$9301_Y + connect \Y $pos$issuer_ls180.v:158390$9302_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + cell $pos $pos$issuer_ls180.v:158391$9304 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 8 + connect \A $extend$issuer_ls180.v:158391$9303_Y + connect \Y $pos$issuer_ls180.v:158391$9304_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + cell $pos $pos$issuer_ls180.v:158392$9306 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 8 + connect \A $extend$issuer_ls180.v:158392$9305_Y + connect \Y $pos$issuer_ls180.v:158392$9306_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + cell $pos $pos$issuer_ls180.v:158393$9308 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 8 + connect \A $extend$issuer_ls180.v:158393$9307_Y + connect \Y $pos$issuer_ls180.v:158393$9308_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + cell $pos $pos$issuer_ls180.v:158394$9310 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 8 + connect \A $extend$issuer_ls180.v:158394$9309_Y + connect \Y $pos$issuer_ls180.v:158394$9310_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + cell $pos $pos$issuer_ls180.v:158395$9312 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 8 + connect \A $extend$issuer_ls180.v:158395$9311_Y + connect \Y $pos$issuer_ls180.v:158395$9312_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + cell $pos $pos$issuer_ls180.v:158396$9314 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 8 + connect \A $extend$issuer_ls180.v:158396$9313_Y + connect \Y $pos$issuer_ls180.v:158396$9314_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + cell $pos $pos$issuer_ls180.v:158397$9316 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 8 + connect \A $extend$issuer_ls180.v:158397$9315_Y + connect \Y $pos$issuer_ls180.v:158397$9316_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + cell $pos $pos$issuer_ls180.v:158399$9319 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \Y_WIDTH 32 + connect \A $extend$issuer_ls180.v:158399$9318_Y + connect \Y $pos$issuer_ls180.v:158399$9319_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + cell $pos $pos$issuer_ls180.v:158400$9321 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \Y_WIDTH 32 + connect \A $extend$issuer_ls180.v:158400$9320_Y + connect \Y $pos$issuer_ls180.v:158400$9321_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" + cell $pos $pos$issuer_ls180.v:158401$9323 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A $extend$issuer_ls180.v:158401$9322_Y + connect \Y $pos$issuer_ls180.v:158401$9323_Y + end + attribute \src "issuer_ls180.v:157943.7-157943.20" + process $proc$issuer_ls180.v:157943$9354 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "issuer_ls180.v:158431.3-158457.6" + process $proc$issuer_ls180.v:158431$9353 + assign { } { } + assign $0\o[63:0] $1\o[63:0] + attribute \src "issuer_ls180.v:158432.5-158432.29" + switch \initial + attribute \src "issuer_ls180.v:158432.9-158432.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:55" + switch { \$192 \$190 } + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\o[63:0] [7:0] \$194 + assign $1\o[63:0] [15:8] \$196 + assign $1\o[63:0] [23:16] \$198 + assign $1\o[63:0] [31:24] \$200 + assign $1\o[63:0] [39:32] \$202 + assign $1\o[63:0] [47:40] \$204 + assign $1\o[63:0] [55:48] \$206 + assign $1\o[63:0] [63:56] \$208 + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\o[63:0] [31:0] \$210 + assign $1\o[63:0] [63:32] \$212 + attribute \src "issuer_ls180.v:0.0-0.0" + case + assign { } { } + assign $1\o[63:0] \$214 + end + sync always + update \o $0\o[63:0] + end + connect \$101 $add$issuer_ls180.v:158355$9266_Y + connect \$104 $add$issuer_ls180.v:158356$9267_Y + connect \$107 $add$issuer_ls180.v:158357$9268_Y + connect \$110 $add$issuer_ls180.v:158358$9269_Y + connect \$113 $add$issuer_ls180.v:158359$9270_Y + connect \$116 $add$issuer_ls180.v:158360$9271_Y + connect \$11 $add$issuer_ls180.v:158361$9272_Y + connect \$119 $add$issuer_ls180.v:158362$9273_Y + connect \$122 $add$issuer_ls180.v:158363$9274_Y + connect \$125 $add$issuer_ls180.v:158364$9275_Y + connect \$128 $add$issuer_ls180.v:158365$9276_Y + connect \$131 $add$issuer_ls180.v:158366$9277_Y + connect \$134 $add$issuer_ls180.v:158367$9278_Y + connect \$137 $add$issuer_ls180.v:158368$9279_Y + connect \$140 $add$issuer_ls180.v:158369$9280_Y + connect \$143 $add$issuer_ls180.v:158370$9281_Y + connect \$146 $add$issuer_ls180.v:158371$9282_Y + connect \$14 $add$issuer_ls180.v:158372$9283_Y + connect \$149 $add$issuer_ls180.v:158373$9284_Y + connect \$152 $add$issuer_ls180.v:158374$9285_Y + connect \$155 $add$issuer_ls180.v:158375$9286_Y + connect \$158 $add$issuer_ls180.v:158376$9287_Y + connect \$161 $add$issuer_ls180.v:158377$9288_Y + connect \$164 $add$issuer_ls180.v:158378$9289_Y + connect \$167 $add$issuer_ls180.v:158379$9290_Y + connect \$170 $add$issuer_ls180.v:158380$9291_Y + connect \$173 $add$issuer_ls180.v:158381$9292_Y + connect \$176 $add$issuer_ls180.v:158382$9293_Y + connect \$17 $add$issuer_ls180.v:158383$9294_Y + connect \$179 $add$issuer_ls180.v:158384$9295_Y + connect \$182 $add$issuer_ls180.v:158385$9296_Y + connect \$185 $add$issuer_ls180.v:158386$9297_Y + connect \$188 $add$issuer_ls180.v:158387$9298_Y + connect \$190 $eq$issuer_ls180.v:158388$9299_Y + connect \$192 $eq$issuer_ls180.v:158389$9300_Y + connect \$194 $pos$issuer_ls180.v:158390$9302_Y + connect \$196 $pos$issuer_ls180.v:158391$9304_Y + connect \$198 $pos$issuer_ls180.v:158392$9306_Y + connect \$200 $pos$issuer_ls180.v:158393$9308_Y + connect \$202 $pos$issuer_ls180.v:158394$9310_Y + connect \$204 $pos$issuer_ls180.v:158395$9312_Y + connect \$206 $pos$issuer_ls180.v:158396$9314_Y + connect \$208 $pos$issuer_ls180.v:158397$9316_Y + connect \$20 $add$issuer_ls180.v:158398$9317_Y + connect \$210 $pos$issuer_ls180.v:158399$9319_Y + connect \$212 $pos$issuer_ls180.v:158400$9321_Y + connect \$214 $pos$issuer_ls180.v:158401$9323_Y + connect \$23 $add$issuer_ls180.v:158402$9324_Y + connect \$26 $add$issuer_ls180.v:158403$9325_Y + connect \$2 $add$issuer_ls180.v:158404$9326_Y + connect \$29 $add$issuer_ls180.v:158405$9327_Y + connect \$32 $add$issuer_ls180.v:158406$9328_Y + connect \$35 $add$issuer_ls180.v:158407$9329_Y + connect \$38 $add$issuer_ls180.v:158408$9330_Y + connect \$41 $add$issuer_ls180.v:158409$9331_Y + connect \$44 $add$issuer_ls180.v:158410$9332_Y + connect \$47 $add$issuer_ls180.v:158411$9333_Y + connect \$50 $add$issuer_ls180.v:158412$9334_Y + connect \$53 $add$issuer_ls180.v:158413$9335_Y + connect \$56 $add$issuer_ls180.v:158414$9336_Y + connect \$5 $add$issuer_ls180.v:158415$9337_Y + connect \$59 $add$issuer_ls180.v:158416$9338_Y + connect \$62 $add$issuer_ls180.v:158417$9339_Y + connect \$65 $add$issuer_ls180.v:158418$9340_Y + connect \$68 $add$issuer_ls180.v:158419$9341_Y + connect \$71 $add$issuer_ls180.v:158420$9342_Y + connect \$74 $add$issuer_ls180.v:158421$9343_Y + connect \$77 $add$issuer_ls180.v:158422$9344_Y + connect \$80 $add$issuer_ls180.v:158423$9345_Y + connect \$83 $add$issuer_ls180.v:158424$9346_Y + connect \$86 $add$issuer_ls180.v:158425$9347_Y + connect \$8 $add$issuer_ls180.v:158426$9348_Y + connect \$89 $add$issuer_ls180.v:158427$9349_Y + connect \$92 $add$issuer_ls180.v:158428$9350_Y + connect \$95 $add$issuer_ls180.v:158429$9351_Y + connect \$98 $add$issuer_ls180.v:158430$9352_Y + connect \$1 \$2 + connect \$4 \$5 + connect \$7 \$8 + connect \$10 \$11 + connect \$13 \$14 + connect \$16 \$17 + connect \$19 \$20 + connect \$22 \$23 + connect \$25 \$26 + connect \$28 \$29 + connect \$31 \$32 + connect \$34 \$35 + connect \$37 \$38 + connect \$40 \$41 + connect \$43 \$44 + connect \$46 \$47 + connect \$49 \$50 + connect \$52 \$53 + connect \$55 \$56 + connect \$58 \$59 + connect \$61 \$62 + connect \$64 \$65 + connect \$67 \$68 + connect \$70 \$71 + connect \$73 \$74 + connect \$76 \$77 + connect \$79 \$80 + connect \$82 \$83 + connect \$85 \$86 + connect \$88 \$89 + connect \$91 \$92 + connect \$94 \$95 + connect \$97 \$98 + connect \$100 \$101 + connect \$103 \$104 + connect \$106 \$107 + connect \$109 \$110 + connect \$112 \$113 + connect \$115 \$116 + connect \$118 \$119 + connect \$121 \$122 + connect \$124 \$125 + connect \$127 \$128 + connect \$130 \$131 + connect \$133 \$134 + connect \$136 \$137 + connect \$139 \$140 + connect \$142 \$143 + connect \$145 \$146 + connect \$148 \$149 + connect \$151 \$152 + connect \$154 \$155 + connect \$157 \$158 + connect \$160 \$161 + connect \$163 \$164 + connect \$166 \$167 + connect \$169 \$170 + connect \$172 \$173 + connect \$175 \$176 + connect \$178 \$179 + connect \$181 \$182 + connect \$184 \$185 + connect \$187 \$188 + connect \pop_7_0 \$188 [6:0] + connect \pop_6_1 \$185 [5:0] + connect \pop_6_0 \$182 [5:0] + connect \pop_5_3 \$179 [4:0] + connect \pop_5_2 \$176 [4:0] + connect \pop_5_1 \$173 [4:0] + connect \pop_5_0 \$170 [4:0] + connect \pop_4_7 \$167 [3:0] + connect \pop_4_6 \$164 [3:0] + connect \pop_4_5 \$161 [3:0] + connect \pop_4_4 \$158 [3:0] + connect \pop_4_3 \$155 [3:0] + connect \pop_4_2 \$152 [3:0] + connect \pop_4_1 \$149 [3:0] + connect \pop_4_0 \$146 [3:0] + connect \pop_3_15 \$143 [2:0] + connect \pop_3_14 \$140 [2:0] + connect \pop_3_13 \$137 [2:0] + connect \pop_3_12 \$134 [2:0] + connect \pop_3_11 \$131 [2:0] + connect \pop_3_10 \$128 [2:0] + connect \pop_3_9 \$125 [2:0] + connect \pop_3_8 \$122 [2:0] + connect \pop_3_7 \$119 [2:0] + connect \pop_3_6 \$116 [2:0] + connect \pop_3_5 \$113 [2:0] + connect \pop_3_4 \$110 [2:0] + connect \pop_3_3 \$107 [2:0] + connect \pop_3_2 \$104 [2:0] + connect \pop_3_1 \$101 [2:0] + connect \pop_3_0 \$98 [2:0] + connect \pop_2_31 \$95 [1:0] + connect \pop_2_30 \$92 [1:0] + connect \pop_2_29 \$89 [1:0] + connect \pop_2_28 \$86 [1:0] + connect \pop_2_27 \$83 [1:0] + connect \pop_2_26 \$80 [1:0] + connect \pop_2_25 \$77 [1:0] + connect \pop_2_24 \$74 [1:0] + connect \pop_2_23 \$71 [1:0] + connect \pop_2_22 \$68 [1:0] + connect \pop_2_21 \$65 [1:0] + connect \pop_2_20 \$62 [1:0] + connect \pop_2_19 \$59 [1:0] + connect \pop_2_18 \$56 [1:0] + connect \pop_2_17 \$53 [1:0] + connect \pop_2_16 \$50 [1:0] + connect \pop_2_15 \$47 [1:0] + connect \pop_2_14 \$44 [1:0] + connect \pop_2_13 \$41 [1:0] + connect \pop_2_12 \$38 [1:0] + connect \pop_2_11 \$35 [1:0] + connect \pop_2_10 \$32 [1:0] + connect \pop_2_9 \$29 [1:0] + connect \pop_2_8 \$26 [1:0] + connect \pop_2_7 \$23 [1:0] + connect \pop_2_6 \$20 [1:0] + connect \pop_2_5 \$17 [1:0] + connect \pop_2_4 \$14 [1:0] + connect \pop_2_3 \$11 [1:0] + connect \pop_2_2 \$8 [1:0] + connect \pop_2_1 \$5 [1:0] + connect \pop_2_0 \$2 [1:0] +end +attribute \src "issuer_ls180.v:158588.1-158672.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.dec_ALU.dec_cr_in.ppick" +attribute \generator "nMigen" +module \ppick + attribute \src "issuer_ls180.v:158645.17-158645.91" + wire $not$issuer_ls180.v:158645$9355_Y + attribute \src "issuer_ls180.v:158647.18-158647.93" + wire $not$issuer_ls180.v:158647$9357_Y + attribute \src "issuer_ls180.v:158649.18-158649.93" + wire $not$issuer_ls180.v:158649$9359_Y + attribute \src "issuer_ls180.v:158650.17-158650.138" + wire width 8 $not$issuer_ls180.v:158650$9360_Y + attribute \src "issuer_ls180.v:158652.18-158652.93" + wire $not$issuer_ls180.v:158652$9362_Y + attribute \src "issuer_ls180.v:158654.18-158654.93" + wire $not$issuer_ls180.v:158654$9364_Y + attribute \src "issuer_ls180.v:158656.18-158656.93" + wire $not$issuer_ls180.v:158656$9366_Y + attribute \src "issuer_ls180.v:158659.17-158659.91" + wire $not$issuer_ls180.v:158659$9369_Y + attribute \src "issuer_ls180.v:158646.18-158646.116" + wire $reduce_or$issuer_ls180.v:158646$9356_Y + attribute \src "issuer_ls180.v:158648.18-158648.122" + wire $reduce_or$issuer_ls180.v:158648$9358_Y + attribute \src "issuer_ls180.v:158651.18-158651.128" + wire $reduce_or$issuer_ls180.v:158651$9361_Y + attribute \src "issuer_ls180.v:158653.18-158653.134" + wire $reduce_or$issuer_ls180.v:158653$9363_Y + attribute \src "issuer_ls180.v:158655.18-158655.140" + wire $reduce_or$issuer_ls180.v:158655$9365_Y + attribute \src "issuer_ls180.v:158657.18-158657.90" + wire $reduce_or$issuer_ls180.v:158657$9367_Y + attribute \src "issuer_ls180.v:158658.17-158658.103" + wire $reduce_or$issuer_ls180.v:158658$9368_Y + attribute \src "issuer_ls180.v:158660.17-158660.109" + wire $reduce_or$issuer_ls180.v:158660$9370_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" + wire width 8 \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$12 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$16 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$19 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$20 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$23 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$24 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$27 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$28 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" + wire \$31 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$4 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$8 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" + wire \en_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" + wire width 8 input 2 \i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:49" + wire width 8 \ni + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" + wire width 8 output 1 \o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t0 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t2 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t4 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t6 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$issuer_ls180.v:158645$9355 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$8 + connect \Y $not$issuer_ls180.v:158645$9355_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$issuer_ls180.v:158647$9357 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$12 + connect \Y $not$issuer_ls180.v:158647$9357_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$issuer_ls180.v:158649$9359 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$16 + connect \Y $not$issuer_ls180.v:158649$9359_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" + cell $not $not$issuer_ls180.v:158650$9360 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 8 + connect \A { \i [0] \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] } + connect \Y $not$issuer_ls180.v:158650$9360_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$issuer_ls180.v:158652$9362 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$20 + connect \Y $not$issuer_ls180.v:158652$9362_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$issuer_ls180.v:158654$9364 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$24 + connect \Y $not$issuer_ls180.v:158654$9364_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$issuer_ls180.v:158656$9366 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$28 + connect \Y $not$issuer_ls180.v:158656$9366_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$issuer_ls180.v:158659$9369 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$4 + connect \Y $not$issuer_ls180.v:158659$9369_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$issuer_ls180.v:158646$9356 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A { \i [5] \i [6] \i [7] \ni [3] } + connect \Y $reduce_or$issuer_ls180.v:158646$9356_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$issuer_ls180.v:158648$9358 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A { \i [4] \i [5] \i [6] \i [7] \ni [4] } + connect \Y $reduce_or$issuer_ls180.v:158648$9358_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$issuer_ls180.v:158651$9361 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A { \i [3] \i [4] \i [5] \i [6] \i [7] \ni [5] } + connect \Y $reduce_or$issuer_ls180.v:158651$9361_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$issuer_ls180.v:158653$9363 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A { \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [6] } + connect \Y $reduce_or$issuer_ls180.v:158653$9363_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$issuer_ls180.v:158655$9365 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A { \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [7] } + connect \Y $reduce_or$issuer_ls180.v:158655$9365_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" + cell $reduce_or $reduce_or$issuer_ls180.v:158657$9367 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \o + connect \Y $reduce_or$issuer_ls180.v:158657$9367_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$issuer_ls180.v:158658$9368 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A { \i [7] \ni [1] } + connect \Y $reduce_or$issuer_ls180.v:158658$9368_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$issuer_ls180.v:158660$9370 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A { \i [6] \i [7] \ni [2] } + connect \Y $reduce_or$issuer_ls180.v:158660$9370_Y + end + connect \$7 $not$issuer_ls180.v:158645$9355_Y + connect \$12 $reduce_or$issuer_ls180.v:158646$9356_Y + connect \$11 $not$issuer_ls180.v:158647$9357_Y + connect \$16 $reduce_or$issuer_ls180.v:158648$9358_Y + connect \$15 $not$issuer_ls180.v:158649$9359_Y + connect \$1 $not$issuer_ls180.v:158650$9360_Y + connect \$20 $reduce_or$issuer_ls180.v:158651$9361_Y + connect \$19 $not$issuer_ls180.v:158652$9362_Y + connect \$24 $reduce_or$issuer_ls180.v:158653$9363_Y + connect \$23 $not$issuer_ls180.v:158654$9364_Y + connect \$28 $reduce_or$issuer_ls180.v:158655$9365_Y + connect \$27 $not$issuer_ls180.v:158656$9366_Y + connect \$31 $reduce_or$issuer_ls180.v:158657$9367_Y + connect \$4 $reduce_or$issuer_ls180.v:158658$9368_Y + connect \$3 $not$issuer_ls180.v:158659$9369_Y + connect \$8 $reduce_or$issuer_ls180.v:158660$9370_Y + connect \en_o \$31 + connect \o { \t0 \t1 \t2 \t3 \t4 \t5 \t6 \t7 } + connect \t7 \$27 + connect \t6 \$23 + connect \t5 \$19 + connect \t4 \$15 + connect \t3 \$11 + connect \t2 \$7 + connect \t1 \$3 + connect \t0 \i [7] + connect \ni \$1 +end +attribute \src "issuer_ls180.v:158676.1-158760.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.dec_ALU.dec_cr_out.ppick" +attribute \generator "nMigen" +module \ppick$136 + attribute \src "issuer_ls180.v:158733.17-158733.91" + wire $not$issuer_ls180.v:158733$9371_Y + attribute \src "issuer_ls180.v:158735.18-158735.93" + wire $not$issuer_ls180.v:158735$9373_Y + attribute \src "issuer_ls180.v:158737.18-158737.93" + wire $not$issuer_ls180.v:158737$9375_Y + attribute \src "issuer_ls180.v:158738.17-158738.138" + wire width 8 $not$issuer_ls180.v:158738$9376_Y + attribute \src "issuer_ls180.v:158740.18-158740.93" + wire $not$issuer_ls180.v:158740$9378_Y + attribute \src "issuer_ls180.v:158742.18-158742.93" + wire $not$issuer_ls180.v:158742$9380_Y + attribute \src "issuer_ls180.v:158744.18-158744.93" + wire $not$issuer_ls180.v:158744$9382_Y + attribute \src "issuer_ls180.v:158747.17-158747.91" + wire $not$issuer_ls180.v:158747$9385_Y + attribute \src "issuer_ls180.v:158734.18-158734.116" + wire $reduce_or$issuer_ls180.v:158734$9372_Y + attribute \src "issuer_ls180.v:158736.18-158736.122" + wire $reduce_or$issuer_ls180.v:158736$9374_Y + attribute \src "issuer_ls180.v:158739.18-158739.128" + wire $reduce_or$issuer_ls180.v:158739$9377_Y + attribute \src "issuer_ls180.v:158741.18-158741.134" + wire $reduce_or$issuer_ls180.v:158741$9379_Y + attribute \src "issuer_ls180.v:158743.18-158743.140" + wire $reduce_or$issuer_ls180.v:158743$9381_Y + attribute \src "issuer_ls180.v:158745.18-158745.90" + wire $reduce_or$issuer_ls180.v:158745$9383_Y + attribute \src "issuer_ls180.v:158746.17-158746.103" + wire $reduce_or$issuer_ls180.v:158746$9384_Y + attribute \src "issuer_ls180.v:158748.17-158748.109" + wire $reduce_or$issuer_ls180.v:158748$9386_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" + wire width 8 \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$12 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$16 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$19 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$20 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$23 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$24 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$27 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$28 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" + wire \$31 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$4 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$8 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" + wire output 1 \en_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" + wire width 8 input 3 \i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:49" + wire width 8 \ni + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" + wire width 8 output 2 \o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t0 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t2 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t4 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t6 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$issuer_ls180.v:158733$9371 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$8 + connect \Y $not$issuer_ls180.v:158733$9371_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$issuer_ls180.v:158735$9373 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$12 + connect \Y $not$issuer_ls180.v:158735$9373_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$issuer_ls180.v:158737$9375 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$16 + connect \Y $not$issuer_ls180.v:158737$9375_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" + cell $not $not$issuer_ls180.v:158738$9376 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 8 + connect \A { \i [0] \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] } + connect \Y $not$issuer_ls180.v:158738$9376_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$issuer_ls180.v:158740$9378 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$20 + connect \Y $not$issuer_ls180.v:158740$9378_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$issuer_ls180.v:158742$9380 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$24 + connect \Y $not$issuer_ls180.v:158742$9380_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$issuer_ls180.v:158744$9382 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$28 + connect \Y $not$issuer_ls180.v:158744$9382_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$issuer_ls180.v:158747$9385 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$4 + connect \Y $not$issuer_ls180.v:158747$9385_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$issuer_ls180.v:158734$9372 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A { \i [5] \i [6] \i [7] \ni [3] } + connect \Y $reduce_or$issuer_ls180.v:158734$9372_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$issuer_ls180.v:158736$9374 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A { \i [4] \i [5] \i [6] \i [7] \ni [4] } + connect \Y $reduce_or$issuer_ls180.v:158736$9374_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$issuer_ls180.v:158739$9377 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A { \i [3] \i [4] \i [5] \i [6] \i [7] \ni [5] } + connect \Y $reduce_or$issuer_ls180.v:158739$9377_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$issuer_ls180.v:158741$9379 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A { \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [6] } + connect \Y $reduce_or$issuer_ls180.v:158741$9379_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$issuer_ls180.v:158743$9381 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A { \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [7] } + connect \Y $reduce_or$issuer_ls180.v:158743$9381_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" + cell $reduce_or $reduce_or$issuer_ls180.v:158745$9383 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \o + connect \Y $reduce_or$issuer_ls180.v:158745$9383_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$issuer_ls180.v:158746$9384 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A { \i [7] \ni [1] } + connect \Y $reduce_or$issuer_ls180.v:158746$9384_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$issuer_ls180.v:158748$9386 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A { \i [6] \i [7] \ni [2] } + connect \Y $reduce_or$issuer_ls180.v:158748$9386_Y + end + connect \$7 $not$issuer_ls180.v:158733$9371_Y + connect \$12 $reduce_or$issuer_ls180.v:158734$9372_Y + connect \$11 $not$issuer_ls180.v:158735$9373_Y + connect \$16 $reduce_or$issuer_ls180.v:158736$9374_Y + connect \$15 $not$issuer_ls180.v:158737$9375_Y + connect \$1 $not$issuer_ls180.v:158738$9376_Y + connect \$20 $reduce_or$issuer_ls180.v:158739$9377_Y + connect \$19 $not$issuer_ls180.v:158740$9378_Y + connect \$24 $reduce_or$issuer_ls180.v:158741$9379_Y + connect \$23 $not$issuer_ls180.v:158742$9380_Y + connect \$28 $reduce_or$issuer_ls180.v:158743$9381_Y + connect \$27 $not$issuer_ls180.v:158744$9382_Y + connect \$31 $reduce_or$issuer_ls180.v:158745$9383_Y + connect \$4 $reduce_or$issuer_ls180.v:158746$9384_Y + connect \$3 $not$issuer_ls180.v:158747$9385_Y + connect \$8 $reduce_or$issuer_ls180.v:158748$9386_Y + connect \en_o \$31 + connect \o { \t0 \t1 \t2 \t3 \t4 \t5 \t6 \t7 } + connect \t7 \$27 + connect \t6 \$23 + connect \t5 \$19 + connect \t4 \$15 + connect \t3 \$11 + connect \t2 \$7 + connect \t1 \$3 + connect \t0 \i [7] + connect \ni \$1 +end +attribute \src "issuer_ls180.v:158764.1-158848.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.dec_CR.dec_cr_in.ppick" +attribute \generator "nMigen" +module \ppick$141 + attribute \src "issuer_ls180.v:158821.17-158821.91" + wire $not$issuer_ls180.v:158821$9387_Y + attribute \src "issuer_ls180.v:158823.18-158823.93" + wire $not$issuer_ls180.v:158823$9389_Y + attribute \src "issuer_ls180.v:158825.18-158825.93" + wire $not$issuer_ls180.v:158825$9391_Y + attribute \src "issuer_ls180.v:158826.17-158826.138" + wire width 8 $not$issuer_ls180.v:158826$9392_Y + attribute \src "issuer_ls180.v:158828.18-158828.93" + wire $not$issuer_ls180.v:158828$9394_Y + attribute \src "issuer_ls180.v:158830.18-158830.93" + wire $not$issuer_ls180.v:158830$9396_Y + attribute \src "issuer_ls180.v:158832.18-158832.93" + wire $not$issuer_ls180.v:158832$9398_Y + attribute \src "issuer_ls180.v:158835.17-158835.91" + wire $not$issuer_ls180.v:158835$9401_Y + attribute \src "issuer_ls180.v:158822.18-158822.116" + wire $reduce_or$issuer_ls180.v:158822$9388_Y + attribute \src "issuer_ls180.v:158824.18-158824.122" + wire $reduce_or$issuer_ls180.v:158824$9390_Y + attribute \src "issuer_ls180.v:158827.18-158827.128" + wire $reduce_or$issuer_ls180.v:158827$9393_Y + attribute \src "issuer_ls180.v:158829.18-158829.134" + wire $reduce_or$issuer_ls180.v:158829$9395_Y + attribute \src "issuer_ls180.v:158831.18-158831.140" + wire $reduce_or$issuer_ls180.v:158831$9397_Y + attribute \src "issuer_ls180.v:158833.18-158833.90" + wire $reduce_or$issuer_ls180.v:158833$9399_Y + attribute \src "issuer_ls180.v:158834.17-158834.103" + wire $reduce_or$issuer_ls180.v:158834$9400_Y + attribute \src "issuer_ls180.v:158836.17-158836.109" + wire $reduce_or$issuer_ls180.v:158836$9402_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" + wire width 8 \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$12 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$16 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$19 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$20 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$23 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$24 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$27 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$28 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" + wire \$31 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$4 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$8 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" + wire \en_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" + wire width 8 input 2 \i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:49" + wire width 8 \ni + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" + wire width 8 output 1 \o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t0 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t2 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t4 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t6 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$issuer_ls180.v:158821$9387 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$8 + connect \Y $not$issuer_ls180.v:158821$9387_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$issuer_ls180.v:158823$9389 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$12 + connect \Y $not$issuer_ls180.v:158823$9389_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$issuer_ls180.v:158825$9391 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$16 + connect \Y $not$issuer_ls180.v:158825$9391_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" + cell $not $not$issuer_ls180.v:158826$9392 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 8 + connect \A { \i [0] \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] } + connect \Y $not$issuer_ls180.v:158826$9392_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$issuer_ls180.v:158828$9394 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$20 + connect \Y $not$issuer_ls180.v:158828$9394_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$issuer_ls180.v:158830$9396 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$24 + connect \Y $not$issuer_ls180.v:158830$9396_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$issuer_ls180.v:158832$9398 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$28 + connect \Y $not$issuer_ls180.v:158832$9398_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$issuer_ls180.v:158835$9401 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$4 + connect \Y $not$issuer_ls180.v:158835$9401_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$issuer_ls180.v:158822$9388 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A { \i [5] \i [6] \i [7] \ni [3] } + connect \Y $reduce_or$issuer_ls180.v:158822$9388_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$issuer_ls180.v:158824$9390 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A { \i [4] \i [5] \i [6] \i [7] \ni [4] } + connect \Y $reduce_or$issuer_ls180.v:158824$9390_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$issuer_ls180.v:158827$9393 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A { \i [3] \i [4] \i [5] \i [6] \i [7] \ni [5] } + connect \Y $reduce_or$issuer_ls180.v:158827$9393_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$issuer_ls180.v:158829$9395 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A { \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [6] } + connect \Y $reduce_or$issuer_ls180.v:158829$9395_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$issuer_ls180.v:158831$9397 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A { \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [7] } + connect \Y $reduce_or$issuer_ls180.v:158831$9397_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" + cell $reduce_or $reduce_or$issuer_ls180.v:158833$9399 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \o + connect \Y $reduce_or$issuer_ls180.v:158833$9399_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$issuer_ls180.v:158834$9400 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A { \i [7] \ni [1] } + connect \Y $reduce_or$issuer_ls180.v:158834$9400_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$issuer_ls180.v:158836$9402 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A { \i [6] \i [7] \ni [2] } + connect \Y $reduce_or$issuer_ls180.v:158836$9402_Y + end + connect \$7 $not$issuer_ls180.v:158821$9387_Y + connect \$12 $reduce_or$issuer_ls180.v:158822$9388_Y + connect \$11 $not$issuer_ls180.v:158823$9389_Y + connect \$16 $reduce_or$issuer_ls180.v:158824$9390_Y + connect \$15 $not$issuer_ls180.v:158825$9391_Y + connect \$1 $not$issuer_ls180.v:158826$9392_Y + connect \$20 $reduce_or$issuer_ls180.v:158827$9393_Y + connect \$19 $not$issuer_ls180.v:158828$9394_Y + connect \$24 $reduce_or$issuer_ls180.v:158829$9395_Y + connect \$23 $not$issuer_ls180.v:158830$9396_Y + connect \$28 $reduce_or$issuer_ls180.v:158831$9397_Y + connect \$27 $not$issuer_ls180.v:158832$9398_Y + connect \$31 $reduce_or$issuer_ls180.v:158833$9399_Y + connect \$4 $reduce_or$issuer_ls180.v:158834$9400_Y + connect \$3 $not$issuer_ls180.v:158835$9401_Y + connect \$8 $reduce_or$issuer_ls180.v:158836$9402_Y + connect \en_o \$31 + connect \o { \t0 \t1 \t2 \t3 \t4 \t5 \t6 \t7 } + connect \t7 \$27 + connect \t6 \$23 + connect \t5 \$19 + connect \t4 \$15 + connect \t3 \$11 + connect \t2 \$7 + connect \t1 \$3 + connect \t0 \i [7] + connect \ni \$1 +end +attribute \src "issuer_ls180.v:158852.1-158936.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.dec_CR.dec_cr_out.ppick" +attribute \generator "nMigen" +module \ppick$143 + attribute \src "issuer_ls180.v:158909.17-158909.91" + wire $not$issuer_ls180.v:158909$9403_Y + attribute \src "issuer_ls180.v:158911.18-158911.93" + wire $not$issuer_ls180.v:158911$9405_Y + attribute \src "issuer_ls180.v:158913.18-158913.93" + wire $not$issuer_ls180.v:158913$9407_Y + attribute \src "issuer_ls180.v:158914.17-158914.138" + wire width 8 $not$issuer_ls180.v:158914$9408_Y + attribute \src "issuer_ls180.v:158916.18-158916.93" + wire $not$issuer_ls180.v:158916$9410_Y + attribute \src "issuer_ls180.v:158918.18-158918.93" + wire $not$issuer_ls180.v:158918$9412_Y + attribute \src "issuer_ls180.v:158920.18-158920.93" + wire $not$issuer_ls180.v:158920$9414_Y + attribute \src "issuer_ls180.v:158923.17-158923.91" + wire $not$issuer_ls180.v:158923$9417_Y + attribute \src "issuer_ls180.v:158910.18-158910.116" + wire $reduce_or$issuer_ls180.v:158910$9404_Y + attribute \src "issuer_ls180.v:158912.18-158912.122" + wire $reduce_or$issuer_ls180.v:158912$9406_Y + attribute \src "issuer_ls180.v:158915.18-158915.128" + wire $reduce_or$issuer_ls180.v:158915$9409_Y + attribute \src "issuer_ls180.v:158917.18-158917.134" + wire $reduce_or$issuer_ls180.v:158917$9411_Y + attribute \src "issuer_ls180.v:158919.18-158919.140" + wire $reduce_or$issuer_ls180.v:158919$9413_Y + attribute \src "issuer_ls180.v:158921.18-158921.90" + wire $reduce_or$issuer_ls180.v:158921$9415_Y + attribute \src "issuer_ls180.v:158922.17-158922.103" + wire $reduce_or$issuer_ls180.v:158922$9416_Y + attribute \src "issuer_ls180.v:158924.17-158924.109" + wire $reduce_or$issuer_ls180.v:158924$9418_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" + wire width 8 \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$12 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$16 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$19 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$20 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$23 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$24 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$27 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$28 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" + wire \$31 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$4 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$8 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" + wire output 1 \en_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" + wire width 8 input 3 \i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:49" + wire width 8 \ni + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" + wire width 8 output 2 \o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t0 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t2 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t4 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t6 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$issuer_ls180.v:158909$9403 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$8 + connect \Y $not$issuer_ls180.v:158909$9403_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$issuer_ls180.v:158911$9405 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$12 + connect \Y $not$issuer_ls180.v:158911$9405_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$issuer_ls180.v:158913$9407 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$16 + connect \Y $not$issuer_ls180.v:158913$9407_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" + cell $not $not$issuer_ls180.v:158914$9408 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 8 + connect \A { \i [0] \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] } + connect \Y $not$issuer_ls180.v:158914$9408_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$issuer_ls180.v:158916$9410 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$20 + connect \Y $not$issuer_ls180.v:158916$9410_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$issuer_ls180.v:158918$9412 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$24 + connect \Y $not$issuer_ls180.v:158918$9412_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$issuer_ls180.v:158920$9414 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$28 + connect \Y $not$issuer_ls180.v:158920$9414_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$issuer_ls180.v:158923$9417 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$4 + connect \Y $not$issuer_ls180.v:158923$9417_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$issuer_ls180.v:158910$9404 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A { \i [5] \i [6] \i [7] \ni [3] } + connect \Y $reduce_or$issuer_ls180.v:158910$9404_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$issuer_ls180.v:158912$9406 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A { \i [4] \i [5] \i [6] \i [7] \ni [4] } + connect \Y $reduce_or$issuer_ls180.v:158912$9406_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$issuer_ls180.v:158915$9409 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A { \i [3] \i [4] \i [5] \i [6] \i [7] \ni [5] } + connect \Y $reduce_or$issuer_ls180.v:158915$9409_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$issuer_ls180.v:158917$9411 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A { \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [6] } + connect \Y $reduce_or$issuer_ls180.v:158917$9411_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$issuer_ls180.v:158919$9413 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A { \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [7] } + connect \Y $reduce_or$issuer_ls180.v:158919$9413_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" + cell $reduce_or $reduce_or$issuer_ls180.v:158921$9415 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \o + connect \Y $reduce_or$issuer_ls180.v:158921$9415_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$issuer_ls180.v:158922$9416 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A { \i [7] \ni [1] } + connect \Y $reduce_or$issuer_ls180.v:158922$9416_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$issuer_ls180.v:158924$9418 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A { \i [6] \i [7] \ni [2] } + connect \Y $reduce_or$issuer_ls180.v:158924$9418_Y + end + connect \$7 $not$issuer_ls180.v:158909$9403_Y + connect \$12 $reduce_or$issuer_ls180.v:158910$9404_Y + connect \$11 $not$issuer_ls180.v:158911$9405_Y + connect \$16 $reduce_or$issuer_ls180.v:158912$9406_Y + connect \$15 $not$issuer_ls180.v:158913$9407_Y + connect \$1 $not$issuer_ls180.v:158914$9408_Y + connect \$20 $reduce_or$issuer_ls180.v:158915$9409_Y + connect \$19 $not$issuer_ls180.v:158916$9410_Y + connect \$24 $reduce_or$issuer_ls180.v:158917$9411_Y + connect \$23 $not$issuer_ls180.v:158918$9412_Y + connect \$28 $reduce_or$issuer_ls180.v:158919$9413_Y + connect \$27 $not$issuer_ls180.v:158920$9414_Y + connect \$31 $reduce_or$issuer_ls180.v:158921$9415_Y + connect \$4 $reduce_or$issuer_ls180.v:158922$9416_Y + connect \$3 $not$issuer_ls180.v:158923$9417_Y + connect \$8 $reduce_or$issuer_ls180.v:158924$9418_Y + connect \en_o \$31 + connect \o { \t0 \t1 \t2 \t3 \t4 \t5 \t6 \t7 } + connect \t7 \$27 + connect \t6 \$23 + connect \t5 \$19 + connect \t4 \$15 + connect \t3 \$11 + connect \t2 \$7 + connect \t1 \$3 + connect \t0 \i [7] + connect \ni \$1 +end +attribute \src "issuer_ls180.v:158940.1-159024.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.dec_BRANCH.dec_cr_in.ppick" +attribute \generator "nMigen" +module \ppick$148 + attribute \src "issuer_ls180.v:158997.17-158997.91" + wire $not$issuer_ls180.v:158997$9419_Y + attribute \src "issuer_ls180.v:158999.18-158999.93" + wire $not$issuer_ls180.v:158999$9421_Y + attribute \src "issuer_ls180.v:159001.18-159001.93" + wire $not$issuer_ls180.v:159001$9423_Y + attribute \src "issuer_ls180.v:159002.17-159002.138" + wire width 8 $not$issuer_ls180.v:159002$9424_Y + attribute \src "issuer_ls180.v:159004.18-159004.93" + wire $not$issuer_ls180.v:159004$9426_Y + attribute \src "issuer_ls180.v:159006.18-159006.93" + wire $not$issuer_ls180.v:159006$9428_Y + attribute \src "issuer_ls180.v:159008.18-159008.93" + wire $not$issuer_ls180.v:159008$9430_Y + attribute \src "issuer_ls180.v:159011.17-159011.91" + wire $not$issuer_ls180.v:159011$9433_Y + attribute \src "issuer_ls180.v:158998.18-158998.116" + wire $reduce_or$issuer_ls180.v:158998$9420_Y + attribute \src "issuer_ls180.v:159000.18-159000.122" + wire $reduce_or$issuer_ls180.v:159000$9422_Y + attribute \src "issuer_ls180.v:159003.18-159003.128" + wire $reduce_or$issuer_ls180.v:159003$9425_Y + attribute \src "issuer_ls180.v:159005.18-159005.134" + wire $reduce_or$issuer_ls180.v:159005$9427_Y + attribute \src "issuer_ls180.v:159007.18-159007.140" + wire $reduce_or$issuer_ls180.v:159007$9429_Y + attribute \src "issuer_ls180.v:159009.18-159009.90" + wire $reduce_or$issuer_ls180.v:159009$9431_Y + attribute \src "issuer_ls180.v:159010.17-159010.103" + wire $reduce_or$issuer_ls180.v:159010$9432_Y + attribute \src "issuer_ls180.v:159012.17-159012.109" + wire $reduce_or$issuer_ls180.v:159012$9434_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" + wire width 8 \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$12 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$16 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$19 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$20 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$23 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$24 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$27 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$28 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" + wire \$31 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$4 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$8 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" + wire \en_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" + wire width 8 input 2 \i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:49" + wire width 8 \ni + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" + wire width 8 output 1 \o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t0 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t2 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t4 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t6 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$issuer_ls180.v:158997$9419 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$8 + connect \Y $not$issuer_ls180.v:158997$9419_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$issuer_ls180.v:158999$9421 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$12 + connect \Y $not$issuer_ls180.v:158999$9421_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$issuer_ls180.v:159001$9423 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$16 + connect \Y $not$issuer_ls180.v:159001$9423_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" + cell $not $not$issuer_ls180.v:159002$9424 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 8 + connect \A { \i [0] \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] } + connect \Y $not$issuer_ls180.v:159002$9424_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$issuer_ls180.v:159004$9426 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$20 + connect \Y $not$issuer_ls180.v:159004$9426_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$issuer_ls180.v:159006$9428 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$24 + connect \Y $not$issuer_ls180.v:159006$9428_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$issuer_ls180.v:159008$9430 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$28 + connect \Y $not$issuer_ls180.v:159008$9430_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$issuer_ls180.v:159011$9433 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$4 + connect \Y $not$issuer_ls180.v:159011$9433_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$issuer_ls180.v:158998$9420 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A { \i [5] \i [6] \i [7] \ni [3] } + connect \Y $reduce_or$issuer_ls180.v:158998$9420_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$issuer_ls180.v:159000$9422 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A { \i [4] \i [5] \i [6] \i [7] \ni [4] } + connect \Y $reduce_or$issuer_ls180.v:159000$9422_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$issuer_ls180.v:159003$9425 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A { \i [3] \i [4] \i [5] \i [6] \i [7] \ni [5] } + connect \Y $reduce_or$issuer_ls180.v:159003$9425_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$issuer_ls180.v:159005$9427 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A { \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [6] } + connect \Y $reduce_or$issuer_ls180.v:159005$9427_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$issuer_ls180.v:159007$9429 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A { \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [7] } + connect \Y $reduce_or$issuer_ls180.v:159007$9429_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" + cell $reduce_or $reduce_or$issuer_ls180.v:159009$9431 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \o + connect \Y $reduce_or$issuer_ls180.v:159009$9431_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$issuer_ls180.v:159010$9432 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A { \i [7] \ni [1] } + connect \Y $reduce_or$issuer_ls180.v:159010$9432_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$issuer_ls180.v:159012$9434 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A { \i [6] \i [7] \ni [2] } + connect \Y $reduce_or$issuer_ls180.v:159012$9434_Y + end + connect \$7 $not$issuer_ls180.v:158997$9419_Y + connect \$12 $reduce_or$issuer_ls180.v:158998$9420_Y + connect \$11 $not$issuer_ls180.v:158999$9421_Y + connect \$16 $reduce_or$issuer_ls180.v:159000$9422_Y + connect \$15 $not$issuer_ls180.v:159001$9423_Y + connect \$1 $not$issuer_ls180.v:159002$9424_Y + connect \$20 $reduce_or$issuer_ls180.v:159003$9425_Y + connect \$19 $not$issuer_ls180.v:159004$9426_Y + connect \$24 $reduce_or$issuer_ls180.v:159005$9427_Y + connect \$23 $not$issuer_ls180.v:159006$9428_Y + connect \$28 $reduce_or$issuer_ls180.v:159007$9429_Y + connect \$27 $not$issuer_ls180.v:159008$9430_Y + connect \$31 $reduce_or$issuer_ls180.v:159009$9431_Y + connect \$4 $reduce_or$issuer_ls180.v:159010$9432_Y + connect \$3 $not$issuer_ls180.v:159011$9433_Y + connect \$8 $reduce_or$issuer_ls180.v:159012$9434_Y + connect \en_o \$31 + connect \o { \t0 \t1 \t2 \t3 \t4 \t5 \t6 \t7 } + connect \t7 \$27 + connect \t6 \$23 + connect \t5 \$19 + connect \t4 \$15 + connect \t3 \$11 + connect \t2 \$7 + connect \t1 \$3 + connect \t0 \i [7] + connect \ni \$1 +end +attribute \src "issuer_ls180.v:159028.1-159112.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.dec_BRANCH.dec_cr_out.ppick" +attribute \generator "nMigen" +module \ppick$150 + attribute \src "issuer_ls180.v:159085.17-159085.91" + wire $not$issuer_ls180.v:159085$9435_Y + attribute \src "issuer_ls180.v:159087.18-159087.93" + wire $not$issuer_ls180.v:159087$9437_Y + attribute \src "issuer_ls180.v:159089.18-159089.93" + wire $not$issuer_ls180.v:159089$9439_Y + attribute \src "issuer_ls180.v:159090.17-159090.138" + wire width 8 $not$issuer_ls180.v:159090$9440_Y + attribute \src "issuer_ls180.v:159092.18-159092.93" + wire $not$issuer_ls180.v:159092$9442_Y + attribute \src "issuer_ls180.v:159094.18-159094.93" + wire $not$issuer_ls180.v:159094$9444_Y + attribute \src "issuer_ls180.v:159096.18-159096.93" + wire $not$issuer_ls180.v:159096$9446_Y + attribute \src "issuer_ls180.v:159099.17-159099.91" + wire $not$issuer_ls180.v:159099$9449_Y + attribute \src "issuer_ls180.v:159086.18-159086.116" + wire $reduce_or$issuer_ls180.v:159086$9436_Y + attribute \src "issuer_ls180.v:159088.18-159088.122" + wire $reduce_or$issuer_ls180.v:159088$9438_Y + attribute \src "issuer_ls180.v:159091.18-159091.128" + wire $reduce_or$issuer_ls180.v:159091$9441_Y + attribute \src "issuer_ls180.v:159093.18-159093.134" + wire $reduce_or$issuer_ls180.v:159093$9443_Y + attribute \src "issuer_ls180.v:159095.18-159095.140" + wire $reduce_or$issuer_ls180.v:159095$9445_Y + attribute \src "issuer_ls180.v:159097.18-159097.90" + wire $reduce_or$issuer_ls180.v:159097$9447_Y + attribute \src "issuer_ls180.v:159098.17-159098.103" + wire $reduce_or$issuer_ls180.v:159098$9448_Y + attribute \src "issuer_ls180.v:159100.17-159100.109" + wire $reduce_or$issuer_ls180.v:159100$9450_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" + wire width 8 \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$12 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$16 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$19 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$20 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$23 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$24 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$27 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$28 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" + wire \$31 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$4 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$8 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" + wire output 1 \en_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" + wire width 8 input 3 \i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:49" + wire width 8 \ni + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" + wire width 8 output 2 \o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t0 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t2 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t4 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t6 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$issuer_ls180.v:159085$9435 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$8 + connect \Y $not$issuer_ls180.v:159085$9435_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$issuer_ls180.v:159087$9437 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$12 + connect \Y $not$issuer_ls180.v:159087$9437_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$issuer_ls180.v:159089$9439 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$16 + connect \Y $not$issuer_ls180.v:159089$9439_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" + cell $not $not$issuer_ls180.v:159090$9440 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 8 + connect \A { \i [0] \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] } + connect \Y $not$issuer_ls180.v:159090$9440_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$issuer_ls180.v:159092$9442 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$20 + connect \Y $not$issuer_ls180.v:159092$9442_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$issuer_ls180.v:159094$9444 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$24 + connect \Y $not$issuer_ls180.v:159094$9444_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$issuer_ls180.v:159096$9446 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$28 + connect \Y $not$issuer_ls180.v:159096$9446_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$issuer_ls180.v:159099$9449 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$4 + connect \Y $not$issuer_ls180.v:159099$9449_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$issuer_ls180.v:159086$9436 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A { \i [5] \i [6] \i [7] \ni [3] } + connect \Y $reduce_or$issuer_ls180.v:159086$9436_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$issuer_ls180.v:159088$9438 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A { \i [4] \i [5] \i [6] \i [7] \ni [4] } + connect \Y $reduce_or$issuer_ls180.v:159088$9438_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$issuer_ls180.v:159091$9441 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A { \i [3] \i [4] \i [5] \i [6] \i [7] \ni [5] } + connect \Y $reduce_or$issuer_ls180.v:159091$9441_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$issuer_ls180.v:159093$9443 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A { \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [6] } + connect \Y $reduce_or$issuer_ls180.v:159093$9443_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$issuer_ls180.v:159095$9445 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A { \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [7] } + connect \Y $reduce_or$issuer_ls180.v:159095$9445_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" + cell $reduce_or $reduce_or$issuer_ls180.v:159097$9447 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \o + connect \Y $reduce_or$issuer_ls180.v:159097$9447_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$issuer_ls180.v:159098$9448 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A { \i [7] \ni [1] } + connect \Y $reduce_or$issuer_ls180.v:159098$9448_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$issuer_ls180.v:159100$9450 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A { \i [6] \i [7] \ni [2] } + connect \Y $reduce_or$issuer_ls180.v:159100$9450_Y + end + connect \$7 $not$issuer_ls180.v:159085$9435_Y + connect \$12 $reduce_or$issuer_ls180.v:159086$9436_Y + connect \$11 $not$issuer_ls180.v:159087$9437_Y + connect \$16 $reduce_or$issuer_ls180.v:159088$9438_Y + connect \$15 $not$issuer_ls180.v:159089$9439_Y + connect \$1 $not$issuer_ls180.v:159090$9440_Y + connect \$20 $reduce_or$issuer_ls180.v:159091$9441_Y + connect \$19 $not$issuer_ls180.v:159092$9442_Y + connect \$24 $reduce_or$issuer_ls180.v:159093$9443_Y + connect \$23 $not$issuer_ls180.v:159094$9444_Y + connect \$28 $reduce_or$issuer_ls180.v:159095$9445_Y + connect \$27 $not$issuer_ls180.v:159096$9446_Y + connect \$31 $reduce_or$issuer_ls180.v:159097$9447_Y + connect \$4 $reduce_or$issuer_ls180.v:159098$9448_Y + connect \$3 $not$issuer_ls180.v:159099$9449_Y + connect \$8 $reduce_or$issuer_ls180.v:159100$9450_Y + connect \en_o \$31 + connect \o { \t0 \t1 \t2 \t3 \t4 \t5 \t6 \t7 } + connect \t7 \$27 + connect \t6 \$23 + connect \t5 \$19 + connect \t4 \$15 + connect \t3 \$11 + connect \t2 \$7 + connect \t1 \$3 + connect \t0 \i [7] + connect \ni \$1 +end +attribute \src "issuer_ls180.v:159116.1-159200.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.dec_LOGICAL.dec_cr_in.ppick" +attribute \generator "nMigen" +module \ppick$156 + attribute \src "issuer_ls180.v:159173.17-159173.91" + wire $not$issuer_ls180.v:159173$9451_Y + attribute \src "issuer_ls180.v:159175.18-159175.93" + wire $not$issuer_ls180.v:159175$9453_Y + attribute \src "issuer_ls180.v:159177.18-159177.93" + wire $not$issuer_ls180.v:159177$9455_Y + attribute \src "issuer_ls180.v:159178.17-159178.138" + wire width 8 $not$issuer_ls180.v:159178$9456_Y + attribute \src "issuer_ls180.v:159180.18-159180.93" + wire $not$issuer_ls180.v:159180$9458_Y + attribute \src "issuer_ls180.v:159182.18-159182.93" + wire $not$issuer_ls180.v:159182$9460_Y + attribute \src "issuer_ls180.v:159184.18-159184.93" + wire $not$issuer_ls180.v:159184$9462_Y + attribute \src "issuer_ls180.v:159187.17-159187.91" + wire $not$issuer_ls180.v:159187$9465_Y + attribute \src "issuer_ls180.v:159174.18-159174.116" + wire $reduce_or$issuer_ls180.v:159174$9452_Y + attribute \src "issuer_ls180.v:159176.18-159176.122" + wire $reduce_or$issuer_ls180.v:159176$9454_Y + attribute \src "issuer_ls180.v:159179.18-159179.128" + wire $reduce_or$issuer_ls180.v:159179$9457_Y + attribute \src "issuer_ls180.v:159181.18-159181.134" + wire $reduce_or$issuer_ls180.v:159181$9459_Y + attribute \src "issuer_ls180.v:159183.18-159183.140" + wire $reduce_or$issuer_ls180.v:159183$9461_Y + attribute \src "issuer_ls180.v:159185.18-159185.90" + wire $reduce_or$issuer_ls180.v:159185$9463_Y + attribute \src "issuer_ls180.v:159186.17-159186.103" + wire $reduce_or$issuer_ls180.v:159186$9464_Y + attribute \src "issuer_ls180.v:159188.17-159188.109" + wire $reduce_or$issuer_ls180.v:159188$9466_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" + wire width 8 \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$12 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$16 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$19 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$20 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$23 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$24 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$27 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$28 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" + wire \$31 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$4 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$8 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" + wire \en_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" + wire width 8 input 2 \i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:49" + wire width 8 \ni + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" + wire width 8 output 1 \o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t0 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t2 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t4 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t6 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$issuer_ls180.v:159173$9451 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$8 + connect \Y $not$issuer_ls180.v:159173$9451_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$issuer_ls180.v:159175$9453 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$12 + connect \Y $not$issuer_ls180.v:159175$9453_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$issuer_ls180.v:159177$9455 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$16 + connect \Y $not$issuer_ls180.v:159177$9455_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" + cell $not $not$issuer_ls180.v:159178$9456 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 8 + connect \A { \i [0] \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] } + connect \Y $not$issuer_ls180.v:159178$9456_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$issuer_ls180.v:159180$9458 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$20 + connect \Y $not$issuer_ls180.v:159180$9458_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$issuer_ls180.v:159182$9460 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$24 + connect \Y $not$issuer_ls180.v:159182$9460_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$issuer_ls180.v:159184$9462 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$28 + connect \Y $not$issuer_ls180.v:159184$9462_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$issuer_ls180.v:159187$9465 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$4 + connect \Y $not$issuer_ls180.v:159187$9465_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$issuer_ls180.v:159174$9452 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A { \i [5] \i [6] \i [7] \ni [3] } + connect \Y $reduce_or$issuer_ls180.v:159174$9452_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$issuer_ls180.v:159176$9454 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A { \i [4] \i [5] \i [6] \i [7] \ni [4] } + connect \Y $reduce_or$issuer_ls180.v:159176$9454_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$issuer_ls180.v:159179$9457 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A { \i [3] \i [4] \i [5] \i [6] \i [7] \ni [5] } + connect \Y $reduce_or$issuer_ls180.v:159179$9457_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$issuer_ls180.v:159181$9459 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A { \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [6] } + connect \Y $reduce_or$issuer_ls180.v:159181$9459_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$issuer_ls180.v:159183$9461 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A { \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [7] } + connect \Y $reduce_or$issuer_ls180.v:159183$9461_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" + cell $reduce_or $reduce_or$issuer_ls180.v:159185$9463 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \o + connect \Y $reduce_or$issuer_ls180.v:159185$9463_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$issuer_ls180.v:159186$9464 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A { \i [7] \ni [1] } + connect \Y $reduce_or$issuer_ls180.v:159186$9464_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$issuer_ls180.v:159188$9466 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A { \i [6] \i [7] \ni [2] } + connect \Y $reduce_or$issuer_ls180.v:159188$9466_Y + end + connect \$7 $not$issuer_ls180.v:159173$9451_Y + connect \$12 $reduce_or$issuer_ls180.v:159174$9452_Y + connect \$11 $not$issuer_ls180.v:159175$9453_Y + connect \$16 $reduce_or$issuer_ls180.v:159176$9454_Y + connect \$15 $not$issuer_ls180.v:159177$9455_Y + connect \$1 $not$issuer_ls180.v:159178$9456_Y + connect \$20 $reduce_or$issuer_ls180.v:159179$9457_Y + connect \$19 $not$issuer_ls180.v:159180$9458_Y + connect \$24 $reduce_or$issuer_ls180.v:159181$9459_Y + connect \$23 $not$issuer_ls180.v:159182$9460_Y + connect \$28 $reduce_or$issuer_ls180.v:159183$9461_Y + connect \$27 $not$issuer_ls180.v:159184$9462_Y + connect \$31 $reduce_or$issuer_ls180.v:159185$9463_Y + connect \$4 $reduce_or$issuer_ls180.v:159186$9464_Y + connect \$3 $not$issuer_ls180.v:159187$9465_Y + connect \$8 $reduce_or$issuer_ls180.v:159188$9466_Y + connect \en_o \$31 + connect \o { \t0 \t1 \t2 \t3 \t4 \t5 \t6 \t7 } + connect \t7 \$27 + connect \t6 \$23 + connect \t5 \$19 + connect \t4 \$15 + connect \t3 \$11 + connect \t2 \$7 + connect \t1 \$3 + connect \t0 \i [7] + connect \ni \$1 +end +attribute \src "issuer_ls180.v:159204.1-159288.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.dec_LOGICAL.dec_cr_out.ppick" +attribute \generator "nMigen" +module \ppick$158 + attribute \src "issuer_ls180.v:159261.17-159261.91" + wire $not$issuer_ls180.v:159261$9467_Y + attribute \src "issuer_ls180.v:159263.18-159263.93" + wire $not$issuer_ls180.v:159263$9469_Y + attribute \src "issuer_ls180.v:159265.18-159265.93" + wire $not$issuer_ls180.v:159265$9471_Y + attribute \src "issuer_ls180.v:159266.17-159266.138" + wire width 8 $not$issuer_ls180.v:159266$9472_Y + attribute \src "issuer_ls180.v:159268.18-159268.93" + wire $not$issuer_ls180.v:159268$9474_Y + attribute \src "issuer_ls180.v:159270.18-159270.93" + wire $not$issuer_ls180.v:159270$9476_Y + attribute \src "issuer_ls180.v:159272.18-159272.93" + wire $not$issuer_ls180.v:159272$9478_Y + attribute \src "issuer_ls180.v:159275.17-159275.91" + wire $not$issuer_ls180.v:159275$9481_Y + attribute \src "issuer_ls180.v:159262.18-159262.116" + wire $reduce_or$issuer_ls180.v:159262$9468_Y + attribute \src "issuer_ls180.v:159264.18-159264.122" + wire $reduce_or$issuer_ls180.v:159264$9470_Y + attribute \src "issuer_ls180.v:159267.18-159267.128" + wire $reduce_or$issuer_ls180.v:159267$9473_Y + attribute \src "issuer_ls180.v:159269.18-159269.134" + wire $reduce_or$issuer_ls180.v:159269$9475_Y + attribute \src "issuer_ls180.v:159271.18-159271.140" + wire $reduce_or$issuer_ls180.v:159271$9477_Y + attribute \src "issuer_ls180.v:159273.18-159273.90" + wire $reduce_or$issuer_ls180.v:159273$9479_Y + attribute \src "issuer_ls180.v:159274.17-159274.103" + wire $reduce_or$issuer_ls180.v:159274$9480_Y + attribute \src "issuer_ls180.v:159276.17-159276.109" + wire $reduce_or$issuer_ls180.v:159276$9482_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" + wire width 8 \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$12 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$16 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$19 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$20 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$23 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$24 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$27 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$28 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" + wire \$31 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$4 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$8 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" + wire output 1 \en_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" + wire width 8 input 3 \i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:49" + wire width 8 \ni + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" + wire width 8 output 2 \o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t0 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t2 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t4 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t6 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$issuer_ls180.v:159261$9467 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$8 + connect \Y $not$issuer_ls180.v:159261$9467_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$issuer_ls180.v:159263$9469 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$12 + connect \Y $not$issuer_ls180.v:159263$9469_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$issuer_ls180.v:159265$9471 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$16 + connect \Y $not$issuer_ls180.v:159265$9471_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" + cell $not $not$issuer_ls180.v:159266$9472 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 8 + connect \A { \i [0] \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] } + connect \Y $not$issuer_ls180.v:159266$9472_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$issuer_ls180.v:159268$9474 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$20 + connect \Y $not$issuer_ls180.v:159268$9474_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$issuer_ls180.v:159270$9476 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$24 + connect \Y $not$issuer_ls180.v:159270$9476_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$issuer_ls180.v:159272$9478 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$28 + connect \Y $not$issuer_ls180.v:159272$9478_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$issuer_ls180.v:159275$9481 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$4 + connect \Y $not$issuer_ls180.v:159275$9481_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$issuer_ls180.v:159262$9468 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A { \i [5] \i [6] \i [7] \ni [3] } + connect \Y $reduce_or$issuer_ls180.v:159262$9468_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$issuer_ls180.v:159264$9470 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A { \i [4] \i [5] \i [6] \i [7] \ni [4] } + connect \Y $reduce_or$issuer_ls180.v:159264$9470_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$issuer_ls180.v:159267$9473 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A { \i [3] \i [4] \i [5] \i [6] \i [7] \ni [5] } + connect \Y $reduce_or$issuer_ls180.v:159267$9473_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$issuer_ls180.v:159269$9475 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A { \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [6] } + connect \Y $reduce_or$issuer_ls180.v:159269$9475_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$issuer_ls180.v:159271$9477 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A { \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [7] } + connect \Y $reduce_or$issuer_ls180.v:159271$9477_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" + cell $reduce_or $reduce_or$issuer_ls180.v:159273$9479 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \o + connect \Y $reduce_or$issuer_ls180.v:159273$9479_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$issuer_ls180.v:159274$9480 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A { \i [7] \ni [1] } + connect \Y $reduce_or$issuer_ls180.v:159274$9480_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$issuer_ls180.v:159276$9482 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A { \i [6] \i [7] \ni [2] } + connect \Y $reduce_or$issuer_ls180.v:159276$9482_Y + end + connect \$7 $not$issuer_ls180.v:159261$9467_Y + connect \$12 $reduce_or$issuer_ls180.v:159262$9468_Y + connect \$11 $not$issuer_ls180.v:159263$9469_Y + connect \$16 $reduce_or$issuer_ls180.v:159264$9470_Y + connect \$15 $not$issuer_ls180.v:159265$9471_Y + connect \$1 $not$issuer_ls180.v:159266$9472_Y + connect \$20 $reduce_or$issuer_ls180.v:159267$9473_Y + connect \$19 $not$issuer_ls180.v:159268$9474_Y + connect \$24 $reduce_or$issuer_ls180.v:159269$9475_Y + connect \$23 $not$issuer_ls180.v:159270$9476_Y + connect \$28 $reduce_or$issuer_ls180.v:159271$9477_Y + connect \$27 $not$issuer_ls180.v:159272$9478_Y + connect \$31 $reduce_or$issuer_ls180.v:159273$9479_Y + connect \$4 $reduce_or$issuer_ls180.v:159274$9480_Y + connect \$3 $not$issuer_ls180.v:159275$9481_Y + connect \$8 $reduce_or$issuer_ls180.v:159276$9482_Y + connect \en_o \$31 + connect \o { \t0 \t1 \t2 \t3 \t4 \t5 \t6 \t7 } + connect \t7 \$27 + connect \t6 \$23 + connect \t5 \$19 + connect \t4 \$15 + connect \t3 \$11 + connect \t2 \$7 + connect \t1 \$3 + connect \t0 \i [7] + connect \ni \$1 +end +attribute \src "issuer_ls180.v:159292.1-159376.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.dec_SPR.dec_cr_in.ppick" +attribute \generator "nMigen" +module \ppick$165 + attribute \src "issuer_ls180.v:159349.17-159349.91" + wire $not$issuer_ls180.v:159349$9483_Y + attribute \src "issuer_ls180.v:159351.18-159351.93" + wire $not$issuer_ls180.v:159351$9485_Y + attribute \src "issuer_ls180.v:159353.18-159353.93" + wire $not$issuer_ls180.v:159353$9487_Y + attribute \src "issuer_ls180.v:159354.17-159354.138" + wire width 8 $not$issuer_ls180.v:159354$9488_Y + attribute \src "issuer_ls180.v:159356.18-159356.93" + wire $not$issuer_ls180.v:159356$9490_Y + attribute \src "issuer_ls180.v:159358.18-159358.93" + wire $not$issuer_ls180.v:159358$9492_Y + attribute \src "issuer_ls180.v:159360.18-159360.93" + wire $not$issuer_ls180.v:159360$9494_Y + attribute \src "issuer_ls180.v:159363.17-159363.91" + wire $not$issuer_ls180.v:159363$9497_Y + attribute \src "issuer_ls180.v:159350.18-159350.116" + wire $reduce_or$issuer_ls180.v:159350$9484_Y + attribute \src "issuer_ls180.v:159352.18-159352.122" + wire $reduce_or$issuer_ls180.v:159352$9486_Y + attribute \src "issuer_ls180.v:159355.18-159355.128" + wire $reduce_or$issuer_ls180.v:159355$9489_Y + attribute \src "issuer_ls180.v:159357.18-159357.134" + wire $reduce_or$issuer_ls180.v:159357$9491_Y + attribute \src "issuer_ls180.v:159359.18-159359.140" + wire $reduce_or$issuer_ls180.v:159359$9493_Y + attribute \src "issuer_ls180.v:159361.18-159361.90" + wire $reduce_or$issuer_ls180.v:159361$9495_Y + attribute \src "issuer_ls180.v:159362.17-159362.103" + wire $reduce_or$issuer_ls180.v:159362$9496_Y + attribute \src "issuer_ls180.v:159364.17-159364.109" + wire $reduce_or$issuer_ls180.v:159364$9498_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" + wire width 8 \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$12 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$16 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$19 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$20 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$23 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$24 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$27 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$28 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" + wire \$31 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$4 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$8 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" + wire \en_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" + wire width 8 input 2 \i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:49" + wire width 8 \ni + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" + wire width 8 output 1 \o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t0 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t2 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t4 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t6 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$issuer_ls180.v:159349$9483 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$8 + connect \Y $not$issuer_ls180.v:159349$9483_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$issuer_ls180.v:159351$9485 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$12 + connect \Y $not$issuer_ls180.v:159351$9485_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$issuer_ls180.v:159353$9487 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$16 + connect \Y $not$issuer_ls180.v:159353$9487_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" + cell $not $not$issuer_ls180.v:159354$9488 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 8 + connect \A { \i [0] \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] } + connect \Y $not$issuer_ls180.v:159354$9488_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$issuer_ls180.v:159356$9490 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$20 + connect \Y $not$issuer_ls180.v:159356$9490_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$issuer_ls180.v:159358$9492 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$24 + connect \Y $not$issuer_ls180.v:159358$9492_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$issuer_ls180.v:159360$9494 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$28 + connect \Y $not$issuer_ls180.v:159360$9494_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$issuer_ls180.v:159363$9497 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$4 + connect \Y $not$issuer_ls180.v:159363$9497_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$issuer_ls180.v:159350$9484 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A { \i [5] \i [6] \i [7] \ni [3] } + connect \Y $reduce_or$issuer_ls180.v:159350$9484_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$issuer_ls180.v:159352$9486 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A { \i [4] \i [5] \i [6] \i [7] \ni [4] } + connect \Y $reduce_or$issuer_ls180.v:159352$9486_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$issuer_ls180.v:159355$9489 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A { \i [3] \i [4] \i [5] \i [6] \i [7] \ni [5] } + connect \Y $reduce_or$issuer_ls180.v:159355$9489_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$issuer_ls180.v:159357$9491 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A { \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [6] } + connect \Y $reduce_or$issuer_ls180.v:159357$9491_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$issuer_ls180.v:159359$9493 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A { \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [7] } + connect \Y $reduce_or$issuer_ls180.v:159359$9493_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" + cell $reduce_or $reduce_or$issuer_ls180.v:159361$9495 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \o + connect \Y $reduce_or$issuer_ls180.v:159361$9495_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$issuer_ls180.v:159362$9496 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A { \i [7] \ni [1] } + connect \Y $reduce_or$issuer_ls180.v:159362$9496_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$issuer_ls180.v:159364$9498 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A { \i [6] \i [7] \ni [2] } + connect \Y $reduce_or$issuer_ls180.v:159364$9498_Y + end + connect \$7 $not$issuer_ls180.v:159349$9483_Y + connect \$12 $reduce_or$issuer_ls180.v:159350$9484_Y + connect \$11 $not$issuer_ls180.v:159351$9485_Y + connect \$16 $reduce_or$issuer_ls180.v:159352$9486_Y + connect \$15 $not$issuer_ls180.v:159353$9487_Y + connect \$1 $not$issuer_ls180.v:159354$9488_Y + connect \$20 $reduce_or$issuer_ls180.v:159355$9489_Y + connect \$19 $not$issuer_ls180.v:159356$9490_Y + connect \$24 $reduce_or$issuer_ls180.v:159357$9491_Y + connect \$23 $not$issuer_ls180.v:159358$9492_Y + connect \$28 $reduce_or$issuer_ls180.v:159359$9493_Y + connect \$27 $not$issuer_ls180.v:159360$9494_Y + connect \$31 $reduce_or$issuer_ls180.v:159361$9495_Y + connect \$4 $reduce_or$issuer_ls180.v:159362$9496_Y + connect \$3 $not$issuer_ls180.v:159363$9497_Y + connect \$8 $reduce_or$issuer_ls180.v:159364$9498_Y + connect \en_o \$31 + connect \o { \t0 \t1 \t2 \t3 \t4 \t5 \t6 \t7 } + connect \t7 \$27 + connect \t6 \$23 + connect \t5 \$19 + connect \t4 \$15 + connect \t3 \$11 + connect \t2 \$7 + connect \t1 \$3 + connect \t0 \i [7] + connect \ni \$1 +end +attribute \src "issuer_ls180.v:159380.1-159464.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.dec_SPR.dec_cr_out.ppick" +attribute \generator "nMigen" +module \ppick$167 + attribute \src "issuer_ls180.v:159437.17-159437.91" + wire $not$issuer_ls180.v:159437$9499_Y + attribute \src "issuer_ls180.v:159439.18-159439.93" + wire $not$issuer_ls180.v:159439$9501_Y + attribute \src "issuer_ls180.v:159441.18-159441.93" + wire $not$issuer_ls180.v:159441$9503_Y + attribute \src "issuer_ls180.v:159442.17-159442.138" + wire width 8 $not$issuer_ls180.v:159442$9504_Y + attribute \src "issuer_ls180.v:159444.18-159444.93" + wire $not$issuer_ls180.v:159444$9506_Y + attribute \src "issuer_ls180.v:159446.18-159446.93" + wire $not$issuer_ls180.v:159446$9508_Y + attribute \src "issuer_ls180.v:159448.18-159448.93" + wire $not$issuer_ls180.v:159448$9510_Y + attribute \src "issuer_ls180.v:159451.17-159451.91" + wire $not$issuer_ls180.v:159451$9513_Y + attribute \src "issuer_ls180.v:159438.18-159438.116" + wire $reduce_or$issuer_ls180.v:159438$9500_Y + attribute \src "issuer_ls180.v:159440.18-159440.122" + wire $reduce_or$issuer_ls180.v:159440$9502_Y + attribute \src "issuer_ls180.v:159443.18-159443.128" + wire $reduce_or$issuer_ls180.v:159443$9505_Y + attribute \src "issuer_ls180.v:159445.18-159445.134" + wire $reduce_or$issuer_ls180.v:159445$9507_Y + attribute \src "issuer_ls180.v:159447.18-159447.140" + wire $reduce_or$issuer_ls180.v:159447$9509_Y + attribute \src "issuer_ls180.v:159449.18-159449.90" + wire $reduce_or$issuer_ls180.v:159449$9511_Y + attribute \src "issuer_ls180.v:159450.17-159450.103" + wire $reduce_or$issuer_ls180.v:159450$9512_Y + attribute \src "issuer_ls180.v:159452.17-159452.109" + wire $reduce_or$issuer_ls180.v:159452$9514_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" + wire width 8 \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$12 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$16 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$19 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$20 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$23 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$24 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$27 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$28 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" + wire \$31 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$4 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$8 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" + wire output 1 \en_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" + wire width 8 input 3 \i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:49" + wire width 8 \ni + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" + wire width 8 output 2 \o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t0 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t2 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t4 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t6 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$issuer_ls180.v:159437$9499 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$8 + connect \Y $not$issuer_ls180.v:159437$9499_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$issuer_ls180.v:159439$9501 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$12 + connect \Y $not$issuer_ls180.v:159439$9501_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$issuer_ls180.v:159441$9503 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$16 + connect \Y $not$issuer_ls180.v:159441$9503_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" + cell $not $not$issuer_ls180.v:159442$9504 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 8 + connect \A { \i [0] \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] } + connect \Y $not$issuer_ls180.v:159442$9504_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$issuer_ls180.v:159444$9506 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$20 + connect \Y $not$issuer_ls180.v:159444$9506_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$issuer_ls180.v:159446$9508 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$24 + connect \Y $not$issuer_ls180.v:159446$9508_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$issuer_ls180.v:159448$9510 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$28 + connect \Y $not$issuer_ls180.v:159448$9510_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$issuer_ls180.v:159451$9513 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$4 + connect \Y $not$issuer_ls180.v:159451$9513_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$issuer_ls180.v:159438$9500 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A { \i [5] \i [6] \i [7] \ni [3] } + connect \Y $reduce_or$issuer_ls180.v:159438$9500_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$issuer_ls180.v:159440$9502 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A { \i [4] \i [5] \i [6] \i [7] \ni [4] } + connect \Y $reduce_or$issuer_ls180.v:159440$9502_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$issuer_ls180.v:159443$9505 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A { \i [3] \i [4] \i [5] \i [6] \i [7] \ni [5] } + connect \Y $reduce_or$issuer_ls180.v:159443$9505_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$issuer_ls180.v:159445$9507 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A { \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [6] } + connect \Y $reduce_or$issuer_ls180.v:159445$9507_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$issuer_ls180.v:159447$9509 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A { \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [7] } + connect \Y $reduce_or$issuer_ls180.v:159447$9509_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" + cell $reduce_or $reduce_or$issuer_ls180.v:159449$9511 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \o + connect \Y $reduce_or$issuer_ls180.v:159449$9511_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$issuer_ls180.v:159450$9512 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A { \i [7] \ni [1] } + connect \Y $reduce_or$issuer_ls180.v:159450$9512_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$issuer_ls180.v:159452$9514 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A { \i [6] \i [7] \ni [2] } + connect \Y $reduce_or$issuer_ls180.v:159452$9514_Y + end + connect \$7 $not$issuer_ls180.v:159437$9499_Y + connect \$12 $reduce_or$issuer_ls180.v:159438$9500_Y + connect \$11 $not$issuer_ls180.v:159439$9501_Y + connect \$16 $reduce_or$issuer_ls180.v:159440$9502_Y + connect \$15 $not$issuer_ls180.v:159441$9503_Y + connect \$1 $not$issuer_ls180.v:159442$9504_Y + connect \$20 $reduce_or$issuer_ls180.v:159443$9505_Y + connect \$19 $not$issuer_ls180.v:159444$9506_Y + connect \$24 $reduce_or$issuer_ls180.v:159445$9507_Y + connect \$23 $not$issuer_ls180.v:159446$9508_Y + connect \$28 $reduce_or$issuer_ls180.v:159447$9509_Y + connect \$27 $not$issuer_ls180.v:159448$9510_Y + connect \$31 $reduce_or$issuer_ls180.v:159449$9511_Y + connect \$4 $reduce_or$issuer_ls180.v:159450$9512_Y + connect \$3 $not$issuer_ls180.v:159451$9513_Y + connect \$8 $reduce_or$issuer_ls180.v:159452$9514_Y + connect \en_o \$31 + connect \o { \t0 \t1 \t2 \t3 \t4 \t5 \t6 \t7 } + connect \t7 \$27 + connect \t6 \$23 + connect \t5 \$19 + connect \t4 \$15 + connect \t3 \$11 + connect \t2 \$7 + connect \t1 \$3 + connect \t0 \i [7] + connect \ni \$1 +end +attribute \src "issuer_ls180.v:159468.1-159552.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.dec_DIV.dec_cr_in.ppick" +attribute \generator "nMigen" +module \ppick$172 + attribute \src "issuer_ls180.v:159525.17-159525.91" + wire $not$issuer_ls180.v:159525$9515_Y + attribute \src "issuer_ls180.v:159527.18-159527.93" + wire $not$issuer_ls180.v:159527$9517_Y + attribute \src "issuer_ls180.v:159529.18-159529.93" + wire $not$issuer_ls180.v:159529$9519_Y + attribute \src "issuer_ls180.v:159530.17-159530.138" + wire width 8 $not$issuer_ls180.v:159530$9520_Y + attribute \src "issuer_ls180.v:159532.18-159532.93" + wire $not$issuer_ls180.v:159532$9522_Y + attribute \src "issuer_ls180.v:159534.18-159534.93" + wire $not$issuer_ls180.v:159534$9524_Y + attribute \src "issuer_ls180.v:159536.18-159536.93" + wire $not$issuer_ls180.v:159536$9526_Y + attribute \src "issuer_ls180.v:159539.17-159539.91" + wire $not$issuer_ls180.v:159539$9529_Y + attribute \src "issuer_ls180.v:159526.18-159526.116" + wire $reduce_or$issuer_ls180.v:159526$9516_Y + attribute \src "issuer_ls180.v:159528.18-159528.122" + wire $reduce_or$issuer_ls180.v:159528$9518_Y + attribute \src "issuer_ls180.v:159531.18-159531.128" + wire $reduce_or$issuer_ls180.v:159531$9521_Y + attribute \src "issuer_ls180.v:159533.18-159533.134" + wire $reduce_or$issuer_ls180.v:159533$9523_Y + attribute \src "issuer_ls180.v:159535.18-159535.140" + wire $reduce_or$issuer_ls180.v:159535$9525_Y + attribute \src "issuer_ls180.v:159537.18-159537.90" + wire $reduce_or$issuer_ls180.v:159537$9527_Y + attribute \src "issuer_ls180.v:159538.17-159538.103" + wire $reduce_or$issuer_ls180.v:159538$9528_Y + attribute \src "issuer_ls180.v:159540.17-159540.109" + wire $reduce_or$issuer_ls180.v:159540$9530_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" + wire width 8 \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$12 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$16 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$19 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$20 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$23 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$24 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$27 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$28 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" + wire \$31 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$4 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$8 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" + wire \en_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" + wire width 8 input 2 \i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:49" + wire width 8 \ni + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" + wire width 8 output 1 \o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t0 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t2 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t4 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t6 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$issuer_ls180.v:159525$9515 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$8 + connect \Y $not$issuer_ls180.v:159525$9515_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$issuer_ls180.v:159527$9517 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$12 + connect \Y $not$issuer_ls180.v:159527$9517_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$issuer_ls180.v:159529$9519 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$16 + connect \Y $not$issuer_ls180.v:159529$9519_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" + cell $not $not$issuer_ls180.v:159530$9520 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 8 + connect \A { \i [0] \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] } + connect \Y $not$issuer_ls180.v:159530$9520_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$issuer_ls180.v:159532$9522 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$20 + connect \Y $not$issuer_ls180.v:159532$9522_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$issuer_ls180.v:159534$9524 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$24 + connect \Y $not$issuer_ls180.v:159534$9524_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$issuer_ls180.v:159536$9526 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$28 + connect \Y $not$issuer_ls180.v:159536$9526_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$issuer_ls180.v:159539$9529 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$4 + connect \Y $not$issuer_ls180.v:159539$9529_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$issuer_ls180.v:159526$9516 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A { \i [5] \i [6] \i [7] \ni [3] } + connect \Y $reduce_or$issuer_ls180.v:159526$9516_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$issuer_ls180.v:159528$9518 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A { \i [4] \i [5] \i [6] \i [7] \ni [4] } + connect \Y $reduce_or$issuer_ls180.v:159528$9518_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$issuer_ls180.v:159531$9521 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A { \i [3] \i [4] \i [5] \i [6] \i [7] \ni [5] } + connect \Y $reduce_or$issuer_ls180.v:159531$9521_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$issuer_ls180.v:159533$9523 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A { \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [6] } + connect \Y $reduce_or$issuer_ls180.v:159533$9523_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$issuer_ls180.v:159535$9525 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A { \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [7] } + connect \Y $reduce_or$issuer_ls180.v:159535$9525_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" + cell $reduce_or $reduce_or$issuer_ls180.v:159537$9527 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \o + connect \Y $reduce_or$issuer_ls180.v:159537$9527_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$issuer_ls180.v:159538$9528 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A { \i [7] \ni [1] } + connect \Y $reduce_or$issuer_ls180.v:159538$9528_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$issuer_ls180.v:159540$9530 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A { \i [6] \i [7] \ni [2] } + connect \Y $reduce_or$issuer_ls180.v:159540$9530_Y + end + connect \$7 $not$issuer_ls180.v:159525$9515_Y + connect \$12 $reduce_or$issuer_ls180.v:159526$9516_Y + connect \$11 $not$issuer_ls180.v:159527$9517_Y + connect \$16 $reduce_or$issuer_ls180.v:159528$9518_Y + connect \$15 $not$issuer_ls180.v:159529$9519_Y + connect \$1 $not$issuer_ls180.v:159530$9520_Y + connect \$20 $reduce_or$issuer_ls180.v:159531$9521_Y + connect \$19 $not$issuer_ls180.v:159532$9522_Y + connect \$24 $reduce_or$issuer_ls180.v:159533$9523_Y + connect \$23 $not$issuer_ls180.v:159534$9524_Y + connect \$28 $reduce_or$issuer_ls180.v:159535$9525_Y + connect \$27 $not$issuer_ls180.v:159536$9526_Y + connect \$31 $reduce_or$issuer_ls180.v:159537$9527_Y + connect \$4 $reduce_or$issuer_ls180.v:159538$9528_Y + connect \$3 $not$issuer_ls180.v:159539$9529_Y + connect \$8 $reduce_or$issuer_ls180.v:159540$9530_Y + connect \en_o \$31 + connect \o { \t0 \t1 \t2 \t3 \t4 \t5 \t6 \t7 } + connect \t7 \$27 + connect \t6 \$23 + connect \t5 \$19 + connect \t4 \$15 + connect \t3 \$11 + connect \t2 \$7 + connect \t1 \$3 + connect \t0 \i [7] + connect \ni \$1 +end +attribute \src "issuer_ls180.v:159556.1-159640.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.dec_DIV.dec_cr_out.ppick" +attribute \generator "nMigen" +module \ppick$174 + attribute \src "issuer_ls180.v:159613.17-159613.91" + wire $not$issuer_ls180.v:159613$9531_Y + attribute \src "issuer_ls180.v:159615.18-159615.93" + wire $not$issuer_ls180.v:159615$9533_Y + attribute \src "issuer_ls180.v:159617.18-159617.93" + wire $not$issuer_ls180.v:159617$9535_Y + attribute \src "issuer_ls180.v:159618.17-159618.138" + wire width 8 $not$issuer_ls180.v:159618$9536_Y + attribute \src "issuer_ls180.v:159620.18-159620.93" + wire $not$issuer_ls180.v:159620$9538_Y + attribute \src "issuer_ls180.v:159622.18-159622.93" + wire $not$issuer_ls180.v:159622$9540_Y + attribute \src "issuer_ls180.v:159624.18-159624.93" + wire $not$issuer_ls180.v:159624$9542_Y + attribute \src "issuer_ls180.v:159627.17-159627.91" + wire $not$issuer_ls180.v:159627$9545_Y + attribute \src "issuer_ls180.v:159614.18-159614.116" + wire $reduce_or$issuer_ls180.v:159614$9532_Y + attribute \src "issuer_ls180.v:159616.18-159616.122" + wire $reduce_or$issuer_ls180.v:159616$9534_Y + attribute \src "issuer_ls180.v:159619.18-159619.128" + wire $reduce_or$issuer_ls180.v:159619$9537_Y + attribute \src "issuer_ls180.v:159621.18-159621.134" + wire $reduce_or$issuer_ls180.v:159621$9539_Y + attribute \src "issuer_ls180.v:159623.18-159623.140" + wire $reduce_or$issuer_ls180.v:159623$9541_Y + attribute \src "issuer_ls180.v:159625.18-159625.90" + wire $reduce_or$issuer_ls180.v:159625$9543_Y + attribute \src "issuer_ls180.v:159626.17-159626.103" + wire $reduce_or$issuer_ls180.v:159626$9544_Y + attribute \src "issuer_ls180.v:159628.17-159628.109" + wire $reduce_or$issuer_ls180.v:159628$9546_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" + wire width 8 \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$12 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$16 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$19 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$20 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$23 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$24 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$27 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$28 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" + wire \$31 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$4 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$8 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" + wire output 1 \en_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" + wire width 8 input 3 \i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:49" + wire width 8 \ni + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" + wire width 8 output 2 \o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t0 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t2 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t4 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t6 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$issuer_ls180.v:159613$9531 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$8 + connect \Y $not$issuer_ls180.v:159613$9531_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$issuer_ls180.v:159615$9533 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$12 + connect \Y $not$issuer_ls180.v:159615$9533_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$issuer_ls180.v:159617$9535 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$16 + connect \Y $not$issuer_ls180.v:159617$9535_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" + cell $not $not$issuer_ls180.v:159618$9536 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 8 + connect \A { \i [0] \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] } + connect \Y $not$issuer_ls180.v:159618$9536_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$issuer_ls180.v:159620$9538 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$20 + connect \Y $not$issuer_ls180.v:159620$9538_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$issuer_ls180.v:159622$9540 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$24 + connect \Y $not$issuer_ls180.v:159622$9540_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$issuer_ls180.v:159624$9542 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$28 + connect \Y $not$issuer_ls180.v:159624$9542_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$issuer_ls180.v:159627$9545 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$4 + connect \Y $not$issuer_ls180.v:159627$9545_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$issuer_ls180.v:159614$9532 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A { \i [5] \i [6] \i [7] \ni [3] } + connect \Y $reduce_or$issuer_ls180.v:159614$9532_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$issuer_ls180.v:159616$9534 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A { \i [4] \i [5] \i [6] \i [7] \ni [4] } + connect \Y $reduce_or$issuer_ls180.v:159616$9534_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$issuer_ls180.v:159619$9537 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A { \i [3] \i [4] \i [5] \i [6] \i [7] \ni [5] } + connect \Y $reduce_or$issuer_ls180.v:159619$9537_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$issuer_ls180.v:159621$9539 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A { \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [6] } + connect \Y $reduce_or$issuer_ls180.v:159621$9539_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$issuer_ls180.v:159623$9541 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A { \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [7] } + connect \Y $reduce_or$issuer_ls180.v:159623$9541_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" + cell $reduce_or $reduce_or$issuer_ls180.v:159625$9543 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \o + connect \Y $reduce_or$issuer_ls180.v:159625$9543_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$issuer_ls180.v:159626$9544 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A { \i [7] \ni [1] } + connect \Y $reduce_or$issuer_ls180.v:159626$9544_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$issuer_ls180.v:159628$9546 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A { \i [6] \i [7] \ni [2] } + connect \Y $reduce_or$issuer_ls180.v:159628$9546_Y + end + connect \$7 $not$issuer_ls180.v:159613$9531_Y + connect \$12 $reduce_or$issuer_ls180.v:159614$9532_Y + connect \$11 $not$issuer_ls180.v:159615$9533_Y + connect \$16 $reduce_or$issuer_ls180.v:159616$9534_Y + connect \$15 $not$issuer_ls180.v:159617$9535_Y + connect \$1 $not$issuer_ls180.v:159618$9536_Y + connect \$20 $reduce_or$issuer_ls180.v:159619$9537_Y + connect \$19 $not$issuer_ls180.v:159620$9538_Y + connect \$24 $reduce_or$issuer_ls180.v:159621$9539_Y + connect \$23 $not$issuer_ls180.v:159622$9540_Y + connect \$28 $reduce_or$issuer_ls180.v:159623$9541_Y + connect \$27 $not$issuer_ls180.v:159624$9542_Y + connect \$31 $reduce_or$issuer_ls180.v:159625$9543_Y + connect \$4 $reduce_or$issuer_ls180.v:159626$9544_Y + connect \$3 $not$issuer_ls180.v:159627$9545_Y + connect \$8 $reduce_or$issuer_ls180.v:159628$9546_Y + connect \en_o \$31 + connect \o { \t0 \t1 \t2 \t3 \t4 \t5 \t6 \t7 } + connect \t7 \$27 + connect \t6 \$23 + connect \t5 \$19 + connect \t4 \$15 + connect \t3 \$11 + connect \t2 \$7 + connect \t1 \$3 + connect \t0 \i [7] + connect \ni \$1 +end +attribute \src "issuer_ls180.v:159644.1-159728.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.dec_MUL.dec_cr_in.ppick" +attribute \generator "nMigen" +module \ppick$181 + attribute \src "issuer_ls180.v:159701.17-159701.91" + wire $not$issuer_ls180.v:159701$9547_Y + attribute \src "issuer_ls180.v:159703.18-159703.93" + wire $not$issuer_ls180.v:159703$9549_Y + attribute \src "issuer_ls180.v:159705.18-159705.93" + wire $not$issuer_ls180.v:159705$9551_Y + attribute \src "issuer_ls180.v:159706.17-159706.138" + wire width 8 $not$issuer_ls180.v:159706$9552_Y + attribute \src "issuer_ls180.v:159708.18-159708.93" + wire $not$issuer_ls180.v:159708$9554_Y + attribute \src "issuer_ls180.v:159710.18-159710.93" + wire $not$issuer_ls180.v:159710$9556_Y + attribute \src "issuer_ls180.v:159712.18-159712.93" + wire $not$issuer_ls180.v:159712$9558_Y + attribute \src "issuer_ls180.v:159715.17-159715.91" + wire $not$issuer_ls180.v:159715$9561_Y + attribute \src "issuer_ls180.v:159702.18-159702.116" + wire $reduce_or$issuer_ls180.v:159702$9548_Y + attribute \src "issuer_ls180.v:159704.18-159704.122" + wire $reduce_or$issuer_ls180.v:159704$9550_Y + attribute \src "issuer_ls180.v:159707.18-159707.128" + wire $reduce_or$issuer_ls180.v:159707$9553_Y + attribute \src "issuer_ls180.v:159709.18-159709.134" + wire $reduce_or$issuer_ls180.v:159709$9555_Y + attribute \src "issuer_ls180.v:159711.18-159711.140" + wire $reduce_or$issuer_ls180.v:159711$9557_Y + attribute \src "issuer_ls180.v:159713.18-159713.90" + wire $reduce_or$issuer_ls180.v:159713$9559_Y + attribute \src "issuer_ls180.v:159714.17-159714.103" + wire $reduce_or$issuer_ls180.v:159714$9560_Y + attribute \src "issuer_ls180.v:159716.17-159716.109" + wire $reduce_or$issuer_ls180.v:159716$9562_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" + wire width 8 \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$12 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$16 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$19 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$20 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$23 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$24 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$27 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$28 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" + wire \$31 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$4 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$8 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" + wire \en_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" + wire width 8 input 2 \i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:49" + wire width 8 \ni + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" + wire width 8 output 1 \o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t0 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t2 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t4 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t6 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$issuer_ls180.v:159701$9547 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$8 + connect \Y $not$issuer_ls180.v:159701$9547_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$issuer_ls180.v:159703$9549 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$12 + connect \Y $not$issuer_ls180.v:159703$9549_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$issuer_ls180.v:159705$9551 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$16 + connect \Y $not$issuer_ls180.v:159705$9551_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" + cell $not $not$issuer_ls180.v:159706$9552 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 8 + connect \A { \i [0] \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] } + connect \Y $not$issuer_ls180.v:159706$9552_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$issuer_ls180.v:159708$9554 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$20 + connect \Y $not$issuer_ls180.v:159708$9554_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$issuer_ls180.v:159710$9556 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$24 + connect \Y $not$issuer_ls180.v:159710$9556_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$issuer_ls180.v:159712$9558 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$28 + connect \Y $not$issuer_ls180.v:159712$9558_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$issuer_ls180.v:159715$9561 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$4 + connect \Y $not$issuer_ls180.v:159715$9561_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$issuer_ls180.v:159702$9548 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A { \i [5] \i [6] \i [7] \ni [3] } + connect \Y $reduce_or$issuer_ls180.v:159702$9548_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$issuer_ls180.v:159704$9550 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A { \i [4] \i [5] \i [6] \i [7] \ni [4] } + connect \Y $reduce_or$issuer_ls180.v:159704$9550_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$issuer_ls180.v:159707$9553 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A { \i [3] \i [4] \i [5] \i [6] \i [7] \ni [5] } + connect \Y $reduce_or$issuer_ls180.v:159707$9553_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$issuer_ls180.v:159709$9555 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A { \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [6] } + connect \Y $reduce_or$issuer_ls180.v:159709$9555_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$issuer_ls180.v:159711$9557 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A { \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [7] } + connect \Y $reduce_or$issuer_ls180.v:159711$9557_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" + cell $reduce_or $reduce_or$issuer_ls180.v:159713$9559 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \o + connect \Y $reduce_or$issuer_ls180.v:159713$9559_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$issuer_ls180.v:159714$9560 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A { \i [7] \ni [1] } + connect \Y $reduce_or$issuer_ls180.v:159714$9560_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$issuer_ls180.v:159716$9562 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A { \i [6] \i [7] \ni [2] } + connect \Y $reduce_or$issuer_ls180.v:159716$9562_Y + end + connect \$7 $not$issuer_ls180.v:159701$9547_Y + connect \$12 $reduce_or$issuer_ls180.v:159702$9548_Y + connect \$11 $not$issuer_ls180.v:159703$9549_Y + connect \$16 $reduce_or$issuer_ls180.v:159704$9550_Y + connect \$15 $not$issuer_ls180.v:159705$9551_Y + connect \$1 $not$issuer_ls180.v:159706$9552_Y + connect \$20 $reduce_or$issuer_ls180.v:159707$9553_Y + connect \$19 $not$issuer_ls180.v:159708$9554_Y + connect \$24 $reduce_or$issuer_ls180.v:159709$9555_Y + connect \$23 $not$issuer_ls180.v:159710$9556_Y + connect \$28 $reduce_or$issuer_ls180.v:159711$9557_Y + connect \$27 $not$issuer_ls180.v:159712$9558_Y + connect \$31 $reduce_or$issuer_ls180.v:159713$9559_Y + connect \$4 $reduce_or$issuer_ls180.v:159714$9560_Y + connect \$3 $not$issuer_ls180.v:159715$9561_Y + connect \$8 $reduce_or$issuer_ls180.v:159716$9562_Y + connect \en_o \$31 + connect \o { \t0 \t1 \t2 \t3 \t4 \t5 \t6 \t7 } + connect \t7 \$27 + connect \t6 \$23 + connect \t5 \$19 + connect \t4 \$15 + connect \t3 \$11 + connect \t2 \$7 + connect \t1 \$3 + connect \t0 \i [7] + connect \ni \$1 +end +attribute \src "issuer_ls180.v:159732.1-159816.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.dec_MUL.dec_cr_out.ppick" +attribute \generator "nMigen" +module \ppick$183 + attribute \src "issuer_ls180.v:159789.17-159789.91" + wire $not$issuer_ls180.v:159789$9563_Y + attribute \src "issuer_ls180.v:159791.18-159791.93" + wire $not$issuer_ls180.v:159791$9565_Y + attribute \src "issuer_ls180.v:159793.18-159793.93" + wire $not$issuer_ls180.v:159793$9567_Y + attribute \src "issuer_ls180.v:159794.17-159794.138" + wire width 8 $not$issuer_ls180.v:159794$9568_Y + attribute \src "issuer_ls180.v:159796.18-159796.93" + wire $not$issuer_ls180.v:159796$9570_Y + attribute \src "issuer_ls180.v:159798.18-159798.93" + wire $not$issuer_ls180.v:159798$9572_Y + attribute \src "issuer_ls180.v:159800.18-159800.93" + wire $not$issuer_ls180.v:159800$9574_Y + attribute \src "issuer_ls180.v:159803.17-159803.91" + wire $not$issuer_ls180.v:159803$9577_Y + attribute \src "issuer_ls180.v:159790.18-159790.116" + wire $reduce_or$issuer_ls180.v:159790$9564_Y + attribute \src "issuer_ls180.v:159792.18-159792.122" + wire $reduce_or$issuer_ls180.v:159792$9566_Y + attribute \src "issuer_ls180.v:159795.18-159795.128" + wire $reduce_or$issuer_ls180.v:159795$9569_Y + attribute \src "issuer_ls180.v:159797.18-159797.134" + wire $reduce_or$issuer_ls180.v:159797$9571_Y + attribute \src "issuer_ls180.v:159799.18-159799.140" + wire $reduce_or$issuer_ls180.v:159799$9573_Y + attribute \src "issuer_ls180.v:159801.18-159801.90" + wire $reduce_or$issuer_ls180.v:159801$9575_Y + attribute \src "issuer_ls180.v:159802.17-159802.103" + wire $reduce_or$issuer_ls180.v:159802$9576_Y + attribute \src "issuer_ls180.v:159804.17-159804.109" + wire $reduce_or$issuer_ls180.v:159804$9578_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" + wire width 8 \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$12 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$16 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$19 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$20 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$23 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$24 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$27 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$28 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" + wire \$31 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$4 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$8 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" + wire output 1 \en_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" + wire width 8 input 3 \i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:49" + wire width 8 \ni + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" + wire width 8 output 2 \o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t0 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t2 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t4 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t6 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$issuer_ls180.v:159789$9563 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$8 + connect \Y $not$issuer_ls180.v:159789$9563_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$issuer_ls180.v:159791$9565 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$12 + connect \Y $not$issuer_ls180.v:159791$9565_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$issuer_ls180.v:159793$9567 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$16 + connect \Y $not$issuer_ls180.v:159793$9567_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" + cell $not $not$issuer_ls180.v:159794$9568 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 8 + connect \A { \i [0] \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] } + connect \Y $not$issuer_ls180.v:159794$9568_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$issuer_ls180.v:159796$9570 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$20 + connect \Y $not$issuer_ls180.v:159796$9570_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$issuer_ls180.v:159798$9572 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$24 + connect \Y $not$issuer_ls180.v:159798$9572_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$issuer_ls180.v:159800$9574 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$28 + connect \Y $not$issuer_ls180.v:159800$9574_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$issuer_ls180.v:159803$9577 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$4 + connect \Y $not$issuer_ls180.v:159803$9577_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$issuer_ls180.v:159790$9564 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A { \i [5] \i [6] \i [7] \ni [3] } + connect \Y $reduce_or$issuer_ls180.v:159790$9564_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$issuer_ls180.v:159792$9566 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A { \i [4] \i [5] \i [6] \i [7] \ni [4] } + connect \Y $reduce_or$issuer_ls180.v:159792$9566_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$issuer_ls180.v:159795$9569 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A { \i [3] \i [4] \i [5] \i [6] \i [7] \ni [5] } + connect \Y $reduce_or$issuer_ls180.v:159795$9569_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$issuer_ls180.v:159797$9571 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A { \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [6] } + connect \Y $reduce_or$issuer_ls180.v:159797$9571_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$issuer_ls180.v:159799$9573 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A { \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [7] } + connect \Y $reduce_or$issuer_ls180.v:159799$9573_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" + cell $reduce_or $reduce_or$issuer_ls180.v:159801$9575 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \o + connect \Y $reduce_or$issuer_ls180.v:159801$9575_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$issuer_ls180.v:159802$9576 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A { \i [7] \ni [1] } + connect \Y $reduce_or$issuer_ls180.v:159802$9576_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$issuer_ls180.v:159804$9578 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A { \i [6] \i [7] \ni [2] } + connect \Y $reduce_or$issuer_ls180.v:159804$9578_Y + end + connect \$7 $not$issuer_ls180.v:159789$9563_Y + connect \$12 $reduce_or$issuer_ls180.v:159790$9564_Y + connect \$11 $not$issuer_ls180.v:159791$9565_Y + connect \$16 $reduce_or$issuer_ls180.v:159792$9566_Y + connect \$15 $not$issuer_ls180.v:159793$9567_Y + connect \$1 $not$issuer_ls180.v:159794$9568_Y + connect \$20 $reduce_or$issuer_ls180.v:159795$9569_Y + connect \$19 $not$issuer_ls180.v:159796$9570_Y + connect \$24 $reduce_or$issuer_ls180.v:159797$9571_Y + connect \$23 $not$issuer_ls180.v:159798$9572_Y + connect \$28 $reduce_or$issuer_ls180.v:159799$9573_Y + connect \$27 $not$issuer_ls180.v:159800$9574_Y + connect \$31 $reduce_or$issuer_ls180.v:159801$9575_Y + connect \$4 $reduce_or$issuer_ls180.v:159802$9576_Y + connect \$3 $not$issuer_ls180.v:159803$9577_Y + connect \$8 $reduce_or$issuer_ls180.v:159804$9578_Y + connect \en_o \$31 + connect \o { \t0 \t1 \t2 \t3 \t4 \t5 \t6 \t7 } + connect \t7 \$27 + connect \t6 \$23 + connect \t5 \$19 + connect \t4 \$15 + connect \t3 \$11 + connect \t2 \$7 + connect \t1 \$3 + connect \t0 \i [7] + connect \ni \$1 +end +attribute \src "issuer_ls180.v:159820.1-159904.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.dec_SHIFT_ROT.dec_cr_in.ppick" +attribute \generator "nMigen" +module \ppick$189 + attribute \src "issuer_ls180.v:159877.17-159877.91" + wire $not$issuer_ls180.v:159877$9579_Y + attribute \src "issuer_ls180.v:159879.18-159879.93" + wire $not$issuer_ls180.v:159879$9581_Y + attribute \src "issuer_ls180.v:159881.18-159881.93" + wire $not$issuer_ls180.v:159881$9583_Y + attribute \src "issuer_ls180.v:159882.17-159882.138" + wire width 8 $not$issuer_ls180.v:159882$9584_Y + attribute \src "issuer_ls180.v:159884.18-159884.93" + wire $not$issuer_ls180.v:159884$9586_Y + attribute \src "issuer_ls180.v:159886.18-159886.93" + wire $not$issuer_ls180.v:159886$9588_Y + attribute \src "issuer_ls180.v:159888.18-159888.93" + wire $not$issuer_ls180.v:159888$9590_Y + attribute \src "issuer_ls180.v:159891.17-159891.91" + wire $not$issuer_ls180.v:159891$9593_Y + attribute \src "issuer_ls180.v:159878.18-159878.116" + wire $reduce_or$issuer_ls180.v:159878$9580_Y + attribute \src "issuer_ls180.v:159880.18-159880.122" + wire $reduce_or$issuer_ls180.v:159880$9582_Y + attribute \src "issuer_ls180.v:159883.18-159883.128" + wire $reduce_or$issuer_ls180.v:159883$9585_Y + attribute \src "issuer_ls180.v:159885.18-159885.134" + wire $reduce_or$issuer_ls180.v:159885$9587_Y + attribute \src "issuer_ls180.v:159887.18-159887.140" + wire $reduce_or$issuer_ls180.v:159887$9589_Y + attribute \src "issuer_ls180.v:159889.18-159889.90" + wire $reduce_or$issuer_ls180.v:159889$9591_Y + attribute \src "issuer_ls180.v:159890.17-159890.103" + wire $reduce_or$issuer_ls180.v:159890$9592_Y + attribute \src "issuer_ls180.v:159892.17-159892.109" + wire $reduce_or$issuer_ls180.v:159892$9594_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" + wire width 8 \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$12 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$16 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$19 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$20 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$23 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$24 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$27 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$28 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" + wire \$31 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$4 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$8 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" + wire \en_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" + wire width 8 input 2 \i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:49" + wire width 8 \ni + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" + wire width 8 output 1 \o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t0 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t2 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t4 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t6 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$issuer_ls180.v:159877$9579 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$8 + connect \Y $not$issuer_ls180.v:159877$9579_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$issuer_ls180.v:159879$9581 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$12 + connect \Y $not$issuer_ls180.v:159879$9581_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$issuer_ls180.v:159881$9583 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$16 + connect \Y $not$issuer_ls180.v:159881$9583_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" + cell $not $not$issuer_ls180.v:159882$9584 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 8 + connect \A { \i [0] \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] } + connect \Y $not$issuer_ls180.v:159882$9584_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$issuer_ls180.v:159884$9586 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$20 + connect \Y $not$issuer_ls180.v:159884$9586_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$issuer_ls180.v:159886$9588 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$24 + connect \Y $not$issuer_ls180.v:159886$9588_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$issuer_ls180.v:159888$9590 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$28 + connect \Y $not$issuer_ls180.v:159888$9590_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$issuer_ls180.v:159891$9593 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$4 + connect \Y $not$issuer_ls180.v:159891$9593_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$issuer_ls180.v:159878$9580 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A { \i [5] \i [6] \i [7] \ni [3] } + connect \Y $reduce_or$issuer_ls180.v:159878$9580_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$issuer_ls180.v:159880$9582 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A { \i [4] \i [5] \i [6] \i [7] \ni [4] } + connect \Y $reduce_or$issuer_ls180.v:159880$9582_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$issuer_ls180.v:159883$9585 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A { \i [3] \i [4] \i [5] \i [6] \i [7] \ni [5] } + connect \Y $reduce_or$issuer_ls180.v:159883$9585_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$issuer_ls180.v:159885$9587 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A { \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [6] } + connect \Y $reduce_or$issuer_ls180.v:159885$9587_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$issuer_ls180.v:159887$9589 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A { \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [7] } + connect \Y $reduce_or$issuer_ls180.v:159887$9589_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" + cell $reduce_or $reduce_or$issuer_ls180.v:159889$9591 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \o + connect \Y $reduce_or$issuer_ls180.v:159889$9591_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$issuer_ls180.v:159890$9592 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A { \i [7] \ni [1] } + connect \Y $reduce_or$issuer_ls180.v:159890$9592_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$issuer_ls180.v:159892$9594 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A { \i [6] \i [7] \ni [2] } + connect \Y $reduce_or$issuer_ls180.v:159892$9594_Y + end + connect \$7 $not$issuer_ls180.v:159877$9579_Y + connect \$12 $reduce_or$issuer_ls180.v:159878$9580_Y + connect \$11 $not$issuer_ls180.v:159879$9581_Y + connect \$16 $reduce_or$issuer_ls180.v:159880$9582_Y + connect \$15 $not$issuer_ls180.v:159881$9583_Y + connect \$1 $not$issuer_ls180.v:159882$9584_Y + connect \$20 $reduce_or$issuer_ls180.v:159883$9585_Y + connect \$19 $not$issuer_ls180.v:159884$9586_Y + connect \$24 $reduce_or$issuer_ls180.v:159885$9587_Y + connect \$23 $not$issuer_ls180.v:159886$9588_Y + connect \$28 $reduce_or$issuer_ls180.v:159887$9589_Y + connect \$27 $not$issuer_ls180.v:159888$9590_Y + connect \$31 $reduce_or$issuer_ls180.v:159889$9591_Y + connect \$4 $reduce_or$issuer_ls180.v:159890$9592_Y + connect \$3 $not$issuer_ls180.v:159891$9593_Y + connect \$8 $reduce_or$issuer_ls180.v:159892$9594_Y + connect \en_o \$31 + connect \o { \t0 \t1 \t2 \t3 \t4 \t5 \t6 \t7 } + connect \t7 \$27 + connect \t6 \$23 + connect \t5 \$19 + connect \t4 \$15 + connect \t3 \$11 + connect \t2 \$7 + connect \t1 \$3 + connect \t0 \i [7] + connect \ni \$1 +end +attribute \src "issuer_ls180.v:159908.1-159992.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.dec_SHIFT_ROT.dec_cr_out.ppick" +attribute \generator "nMigen" +module \ppick$191 + attribute \src "issuer_ls180.v:159965.17-159965.91" + wire $not$issuer_ls180.v:159965$9595_Y + attribute \src "issuer_ls180.v:159967.18-159967.93" + wire $not$issuer_ls180.v:159967$9597_Y + attribute \src "issuer_ls180.v:159969.18-159969.93" + wire $not$issuer_ls180.v:159969$9599_Y + attribute \src "issuer_ls180.v:159970.17-159970.138" + wire width 8 $not$issuer_ls180.v:159970$9600_Y + attribute \src "issuer_ls180.v:159972.18-159972.93" + wire $not$issuer_ls180.v:159972$9602_Y + attribute \src "issuer_ls180.v:159974.18-159974.93" + wire $not$issuer_ls180.v:159974$9604_Y + attribute \src "issuer_ls180.v:159976.18-159976.93" + wire $not$issuer_ls180.v:159976$9606_Y + attribute \src "issuer_ls180.v:159979.17-159979.91" + wire $not$issuer_ls180.v:159979$9609_Y + attribute \src "issuer_ls180.v:159966.18-159966.116" + wire $reduce_or$issuer_ls180.v:159966$9596_Y + attribute \src "issuer_ls180.v:159968.18-159968.122" + wire $reduce_or$issuer_ls180.v:159968$9598_Y + attribute \src "issuer_ls180.v:159971.18-159971.128" + wire $reduce_or$issuer_ls180.v:159971$9601_Y + attribute \src "issuer_ls180.v:159973.18-159973.134" + wire $reduce_or$issuer_ls180.v:159973$9603_Y + attribute \src "issuer_ls180.v:159975.18-159975.140" + wire $reduce_or$issuer_ls180.v:159975$9605_Y + attribute \src "issuer_ls180.v:159977.18-159977.90" + wire $reduce_or$issuer_ls180.v:159977$9607_Y + attribute \src "issuer_ls180.v:159978.17-159978.103" + wire $reduce_or$issuer_ls180.v:159978$9608_Y + attribute \src "issuer_ls180.v:159980.17-159980.109" + wire $reduce_or$issuer_ls180.v:159980$9610_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" + wire width 8 \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$12 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$16 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$19 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$20 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$23 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$24 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$27 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$28 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" + wire \$31 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$4 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$8 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" + wire output 1 \en_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" + wire width 8 input 3 \i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:49" + wire width 8 \ni + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" + wire width 8 output 2 \o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t0 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t2 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t4 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t6 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$issuer_ls180.v:159965$9595 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$8 + connect \Y $not$issuer_ls180.v:159965$9595_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$issuer_ls180.v:159967$9597 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$12 + connect \Y $not$issuer_ls180.v:159967$9597_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$issuer_ls180.v:159969$9599 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$16 + connect \Y $not$issuer_ls180.v:159969$9599_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" + cell $not $not$issuer_ls180.v:159970$9600 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 8 + connect \A { \i [0] \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] } + connect \Y $not$issuer_ls180.v:159970$9600_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$issuer_ls180.v:159972$9602 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$20 + connect \Y $not$issuer_ls180.v:159972$9602_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$issuer_ls180.v:159974$9604 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$24 + connect \Y $not$issuer_ls180.v:159974$9604_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$issuer_ls180.v:159976$9606 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$28 + connect \Y $not$issuer_ls180.v:159976$9606_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$issuer_ls180.v:159979$9609 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$4 + connect \Y $not$issuer_ls180.v:159979$9609_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$issuer_ls180.v:159966$9596 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A { \i [5] \i [6] \i [7] \ni [3] } + connect \Y $reduce_or$issuer_ls180.v:159966$9596_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$issuer_ls180.v:159968$9598 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A { \i [4] \i [5] \i [6] \i [7] \ni [4] } + connect \Y $reduce_or$issuer_ls180.v:159968$9598_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$issuer_ls180.v:159971$9601 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A { \i [3] \i [4] \i [5] \i [6] \i [7] \ni [5] } + connect \Y $reduce_or$issuer_ls180.v:159971$9601_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$issuer_ls180.v:159973$9603 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A { \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [6] } + connect \Y $reduce_or$issuer_ls180.v:159973$9603_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$issuer_ls180.v:159975$9605 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A { \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [7] } + connect \Y $reduce_or$issuer_ls180.v:159975$9605_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" + cell $reduce_or $reduce_or$issuer_ls180.v:159977$9607 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \o + connect \Y $reduce_or$issuer_ls180.v:159977$9607_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$issuer_ls180.v:159978$9608 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A { \i [7] \ni [1] } + connect \Y $reduce_or$issuer_ls180.v:159978$9608_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$issuer_ls180.v:159980$9610 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A { \i [6] \i [7] \ni [2] } + connect \Y $reduce_or$issuer_ls180.v:159980$9610_Y + end + connect \$7 $not$issuer_ls180.v:159965$9595_Y + connect \$12 $reduce_or$issuer_ls180.v:159966$9596_Y + connect \$11 $not$issuer_ls180.v:159967$9597_Y + connect \$16 $reduce_or$issuer_ls180.v:159968$9598_Y + connect \$15 $not$issuer_ls180.v:159969$9599_Y + connect \$1 $not$issuer_ls180.v:159970$9600_Y + connect \$20 $reduce_or$issuer_ls180.v:159971$9601_Y + connect \$19 $not$issuer_ls180.v:159972$9602_Y + connect \$24 $reduce_or$issuer_ls180.v:159973$9603_Y + connect \$23 $not$issuer_ls180.v:159974$9604_Y + connect \$28 $reduce_or$issuer_ls180.v:159975$9605_Y + connect \$27 $not$issuer_ls180.v:159976$9606_Y + connect \$31 $reduce_or$issuer_ls180.v:159977$9607_Y + connect \$4 $reduce_or$issuer_ls180.v:159978$9608_Y + connect \$3 $not$issuer_ls180.v:159979$9609_Y + connect \$8 $reduce_or$issuer_ls180.v:159980$9610_Y + connect \en_o \$31 + connect \o { \t0 \t1 \t2 \t3 \t4 \t5 \t6 \t7 } + connect \t7 \$27 + connect \t6 \$23 + connect \t5 \$19 + connect \t4 \$15 + connect \t3 \$11 + connect \t2 \$7 + connect \t1 \$3 + connect \t0 \i [7] + connect \ni \$1 +end +attribute \src "issuer_ls180.v:159996.1-160080.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.dec_LDST.dec_cr_in.ppick" +attribute \generator "nMigen" +module \ppick$197 + attribute \src "issuer_ls180.v:160053.17-160053.91" + wire $not$issuer_ls180.v:160053$9611_Y + attribute \src "issuer_ls180.v:160055.18-160055.93" + wire $not$issuer_ls180.v:160055$9613_Y + attribute \src "issuer_ls180.v:160057.18-160057.93" + wire $not$issuer_ls180.v:160057$9615_Y + attribute \src "issuer_ls180.v:160058.17-160058.138" + wire width 8 $not$issuer_ls180.v:160058$9616_Y + attribute \src "issuer_ls180.v:160060.18-160060.93" + wire $not$issuer_ls180.v:160060$9618_Y + attribute \src "issuer_ls180.v:160062.18-160062.93" + wire $not$issuer_ls180.v:160062$9620_Y + attribute \src "issuer_ls180.v:160064.18-160064.93" + wire $not$issuer_ls180.v:160064$9622_Y + attribute \src "issuer_ls180.v:160067.17-160067.91" + wire $not$issuer_ls180.v:160067$9625_Y + attribute \src "issuer_ls180.v:160054.18-160054.116" + wire $reduce_or$issuer_ls180.v:160054$9612_Y + attribute \src "issuer_ls180.v:160056.18-160056.122" + wire $reduce_or$issuer_ls180.v:160056$9614_Y + attribute \src "issuer_ls180.v:160059.18-160059.128" + wire $reduce_or$issuer_ls180.v:160059$9617_Y + attribute \src "issuer_ls180.v:160061.18-160061.134" + wire $reduce_or$issuer_ls180.v:160061$9619_Y + attribute \src "issuer_ls180.v:160063.18-160063.140" + wire $reduce_or$issuer_ls180.v:160063$9621_Y + attribute \src "issuer_ls180.v:160065.18-160065.90" + wire $reduce_or$issuer_ls180.v:160065$9623_Y + attribute \src "issuer_ls180.v:160066.17-160066.103" + wire $reduce_or$issuer_ls180.v:160066$9624_Y + attribute \src "issuer_ls180.v:160068.17-160068.109" + wire $reduce_or$issuer_ls180.v:160068$9626_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" + wire width 8 \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$12 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$16 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$19 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$20 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$23 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$24 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$27 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$28 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" + wire \$31 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$4 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$8 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" + wire \en_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" + wire width 8 input 2 \i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:49" + wire width 8 \ni + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" + wire width 8 output 1 \o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t0 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t2 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t4 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t6 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$issuer_ls180.v:160053$9611 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$8 + connect \Y $not$issuer_ls180.v:160053$9611_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$issuer_ls180.v:160055$9613 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$12 + connect \Y $not$issuer_ls180.v:160055$9613_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$issuer_ls180.v:160057$9615 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$16 + connect \Y $not$issuer_ls180.v:160057$9615_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" + cell $not $not$issuer_ls180.v:160058$9616 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 8 + connect \A { \i [0] \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] } + connect \Y $not$issuer_ls180.v:160058$9616_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$issuer_ls180.v:160060$9618 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$20 + connect \Y $not$issuer_ls180.v:160060$9618_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$issuer_ls180.v:160062$9620 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$24 + connect \Y $not$issuer_ls180.v:160062$9620_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$issuer_ls180.v:160064$9622 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$28 + connect \Y $not$issuer_ls180.v:160064$9622_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$issuer_ls180.v:160067$9625 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$4 + connect \Y $not$issuer_ls180.v:160067$9625_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$issuer_ls180.v:160054$9612 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A { \i [5] \i [6] \i [7] \ni [3] } + connect \Y $reduce_or$issuer_ls180.v:160054$9612_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$issuer_ls180.v:160056$9614 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A { \i [4] \i [5] \i [6] \i [7] \ni [4] } + connect \Y $reduce_or$issuer_ls180.v:160056$9614_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$issuer_ls180.v:160059$9617 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A { \i [3] \i [4] \i [5] \i [6] \i [7] \ni [5] } + connect \Y $reduce_or$issuer_ls180.v:160059$9617_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$issuer_ls180.v:160061$9619 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A { \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [6] } + connect \Y $reduce_or$issuer_ls180.v:160061$9619_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$issuer_ls180.v:160063$9621 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A { \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [7] } + connect \Y $reduce_or$issuer_ls180.v:160063$9621_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" + cell $reduce_or $reduce_or$issuer_ls180.v:160065$9623 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \o + connect \Y $reduce_or$issuer_ls180.v:160065$9623_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$issuer_ls180.v:160066$9624 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A { \i [7] \ni [1] } + connect \Y $reduce_or$issuer_ls180.v:160066$9624_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$issuer_ls180.v:160068$9626 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A { \i [6] \i [7] \ni [2] } + connect \Y $reduce_or$issuer_ls180.v:160068$9626_Y + end + connect \$7 $not$issuer_ls180.v:160053$9611_Y + connect \$12 $reduce_or$issuer_ls180.v:160054$9612_Y + connect \$11 $not$issuer_ls180.v:160055$9613_Y + connect \$16 $reduce_or$issuer_ls180.v:160056$9614_Y + connect \$15 $not$issuer_ls180.v:160057$9615_Y + connect \$1 $not$issuer_ls180.v:160058$9616_Y + connect \$20 $reduce_or$issuer_ls180.v:160059$9617_Y + connect \$19 $not$issuer_ls180.v:160060$9618_Y + connect \$24 $reduce_or$issuer_ls180.v:160061$9619_Y + connect \$23 $not$issuer_ls180.v:160062$9620_Y + connect \$28 $reduce_or$issuer_ls180.v:160063$9621_Y + connect \$27 $not$issuer_ls180.v:160064$9622_Y + connect \$31 $reduce_or$issuer_ls180.v:160065$9623_Y + connect \$4 $reduce_or$issuer_ls180.v:160066$9624_Y + connect \$3 $not$issuer_ls180.v:160067$9625_Y + connect \$8 $reduce_or$issuer_ls180.v:160068$9626_Y + connect \en_o \$31 + connect \o { \t0 \t1 \t2 \t3 \t4 \t5 \t6 \t7 } + connect \t7 \$27 + connect \t6 \$23 + connect \t5 \$19 + connect \t4 \$15 + connect \t3 \$11 + connect \t2 \$7 + connect \t1 \$3 + connect \t0 \i [7] + connect \ni \$1 +end +attribute \src "issuer_ls180.v:160084.1-160168.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.dec_LDST.dec_cr_out.ppick" +attribute \generator "nMigen" +module \ppick$199 + attribute \src "issuer_ls180.v:160141.17-160141.91" + wire $not$issuer_ls180.v:160141$9627_Y + attribute \src "issuer_ls180.v:160143.18-160143.93" + wire $not$issuer_ls180.v:160143$9629_Y + attribute \src "issuer_ls180.v:160145.18-160145.93" + wire $not$issuer_ls180.v:160145$9631_Y + attribute \src "issuer_ls180.v:160146.17-160146.138" + wire width 8 $not$issuer_ls180.v:160146$9632_Y + attribute \src "issuer_ls180.v:160148.18-160148.93" + wire $not$issuer_ls180.v:160148$9634_Y + attribute \src "issuer_ls180.v:160150.18-160150.93" + wire $not$issuer_ls180.v:160150$9636_Y + attribute \src "issuer_ls180.v:160152.18-160152.93" + wire $not$issuer_ls180.v:160152$9638_Y + attribute \src "issuer_ls180.v:160155.17-160155.91" + wire $not$issuer_ls180.v:160155$9641_Y + attribute \src "issuer_ls180.v:160142.18-160142.116" + wire $reduce_or$issuer_ls180.v:160142$9628_Y + attribute \src "issuer_ls180.v:160144.18-160144.122" + wire $reduce_or$issuer_ls180.v:160144$9630_Y + attribute \src "issuer_ls180.v:160147.18-160147.128" + wire $reduce_or$issuer_ls180.v:160147$9633_Y + attribute \src "issuer_ls180.v:160149.18-160149.134" + wire $reduce_or$issuer_ls180.v:160149$9635_Y + attribute \src "issuer_ls180.v:160151.18-160151.140" + wire $reduce_or$issuer_ls180.v:160151$9637_Y + attribute \src "issuer_ls180.v:160153.18-160153.90" + wire $reduce_or$issuer_ls180.v:160153$9639_Y + attribute \src "issuer_ls180.v:160154.17-160154.103" + wire $reduce_or$issuer_ls180.v:160154$9640_Y + attribute \src "issuer_ls180.v:160156.17-160156.109" + wire $reduce_or$issuer_ls180.v:160156$9642_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" + wire width 8 \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$12 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$16 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$19 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$20 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$23 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$24 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$27 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$28 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" + wire \$31 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$4 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$8 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" + wire output 1 \en_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" + wire width 8 input 3 \i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:49" + wire width 8 \ni + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" + wire width 8 output 2 \o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t0 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t2 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t4 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t6 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$issuer_ls180.v:160141$9627 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$8 + connect \Y $not$issuer_ls180.v:160141$9627_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$issuer_ls180.v:160143$9629 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$12 + connect \Y $not$issuer_ls180.v:160143$9629_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$issuer_ls180.v:160145$9631 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$16 + connect \Y $not$issuer_ls180.v:160145$9631_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" + cell $not $not$issuer_ls180.v:160146$9632 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 8 + connect \A { \i [0] \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] } + connect \Y $not$issuer_ls180.v:160146$9632_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$issuer_ls180.v:160148$9634 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$20 + connect \Y $not$issuer_ls180.v:160148$9634_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$issuer_ls180.v:160150$9636 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$24 + connect \Y $not$issuer_ls180.v:160150$9636_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$issuer_ls180.v:160152$9638 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$28 + connect \Y $not$issuer_ls180.v:160152$9638_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$issuer_ls180.v:160155$9641 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$4 + connect \Y $not$issuer_ls180.v:160155$9641_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$issuer_ls180.v:160142$9628 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A { \i [5] \i [6] \i [7] \ni [3] } + connect \Y $reduce_or$issuer_ls180.v:160142$9628_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$issuer_ls180.v:160144$9630 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A { \i [4] \i [5] \i [6] \i [7] \ni [4] } + connect \Y $reduce_or$issuer_ls180.v:160144$9630_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$issuer_ls180.v:160147$9633 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A { \i [3] \i [4] \i [5] \i [6] \i [7] \ni [5] } + connect \Y $reduce_or$issuer_ls180.v:160147$9633_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$issuer_ls180.v:160149$9635 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A { \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [6] } + connect \Y $reduce_or$issuer_ls180.v:160149$9635_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$issuer_ls180.v:160151$9637 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A { \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [7] } + connect \Y $reduce_or$issuer_ls180.v:160151$9637_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" + cell $reduce_or $reduce_or$issuer_ls180.v:160153$9639 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \o + connect \Y $reduce_or$issuer_ls180.v:160153$9639_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$issuer_ls180.v:160154$9640 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A { \i [7] \ni [1] } + connect \Y $reduce_or$issuer_ls180.v:160154$9640_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$issuer_ls180.v:160156$9642 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A { \i [6] \i [7] \ni [2] } + connect \Y $reduce_or$issuer_ls180.v:160156$9642_Y + end + connect \$7 $not$issuer_ls180.v:160141$9627_Y + connect \$12 $reduce_or$issuer_ls180.v:160142$9628_Y + connect \$11 $not$issuer_ls180.v:160143$9629_Y + connect \$16 $reduce_or$issuer_ls180.v:160144$9630_Y + connect \$15 $not$issuer_ls180.v:160145$9631_Y + connect \$1 $not$issuer_ls180.v:160146$9632_Y + connect \$20 $reduce_or$issuer_ls180.v:160147$9633_Y + connect \$19 $not$issuer_ls180.v:160148$9634_Y + connect \$24 $reduce_or$issuer_ls180.v:160149$9635_Y + connect \$23 $not$issuer_ls180.v:160150$9636_Y + connect \$28 $reduce_or$issuer_ls180.v:160151$9637_Y + connect \$27 $not$issuer_ls180.v:160152$9638_Y + connect \$31 $reduce_or$issuer_ls180.v:160153$9639_Y + connect \$4 $reduce_or$issuer_ls180.v:160154$9640_Y + connect \$3 $not$issuer_ls180.v:160155$9641_Y + connect \$8 $reduce_or$issuer_ls180.v:160156$9642_Y + connect \en_o \$31 + connect \o { \t0 \t1 \t2 \t3 \t4 \t5 \t6 \t7 } + connect \t7 \$27 + connect \t6 \$23 + connect \t5 \$19 + connect \t4 \$15 + connect \t3 \$11 + connect \t2 \$7 + connect \t1 \$3 + connect \t0 \i [7] + connect \ni \$1 +end +attribute \src "issuer_ls180.v:160172.1-160256.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.dec2.dec_cr_in.ppick" +attribute \generator "nMigen" +module \ppick$206 + attribute \src "issuer_ls180.v:160229.17-160229.91" + wire $not$issuer_ls180.v:160229$9643_Y + attribute \src "issuer_ls180.v:160231.18-160231.93" + wire $not$issuer_ls180.v:160231$9645_Y + attribute \src "issuer_ls180.v:160233.18-160233.93" + wire $not$issuer_ls180.v:160233$9647_Y + attribute \src "issuer_ls180.v:160234.17-160234.138" + wire width 8 $not$issuer_ls180.v:160234$9648_Y + attribute \src "issuer_ls180.v:160236.18-160236.93" + wire $not$issuer_ls180.v:160236$9650_Y + attribute \src "issuer_ls180.v:160238.18-160238.93" + wire $not$issuer_ls180.v:160238$9652_Y + attribute \src "issuer_ls180.v:160240.18-160240.93" + wire $not$issuer_ls180.v:160240$9654_Y + attribute \src "issuer_ls180.v:160243.17-160243.91" + wire $not$issuer_ls180.v:160243$9657_Y + attribute \src "issuer_ls180.v:160230.18-160230.116" + wire $reduce_or$issuer_ls180.v:160230$9644_Y + attribute \src "issuer_ls180.v:160232.18-160232.122" + wire $reduce_or$issuer_ls180.v:160232$9646_Y + attribute \src "issuer_ls180.v:160235.18-160235.128" + wire $reduce_or$issuer_ls180.v:160235$9649_Y + attribute \src "issuer_ls180.v:160237.18-160237.134" + wire $reduce_or$issuer_ls180.v:160237$9651_Y + attribute \src "issuer_ls180.v:160239.18-160239.140" + wire $reduce_or$issuer_ls180.v:160239$9653_Y + attribute \src "issuer_ls180.v:160241.18-160241.90" + wire $reduce_or$issuer_ls180.v:160241$9655_Y + attribute \src "issuer_ls180.v:160242.17-160242.103" + wire $reduce_or$issuer_ls180.v:160242$9656_Y + attribute \src "issuer_ls180.v:160244.17-160244.109" + wire $reduce_or$issuer_ls180.v:160244$9658_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" + wire width 8 \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$12 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$16 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$19 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$20 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$23 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$24 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$27 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$28 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" + wire \$31 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$4 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$8 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" + wire \en_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" + wire width 8 input 2 \i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:49" + wire width 8 \ni + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" + wire width 8 output 1 \o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t0 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t2 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t4 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t6 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$issuer_ls180.v:160229$9643 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$8 + connect \Y $not$issuer_ls180.v:160229$9643_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$issuer_ls180.v:160231$9645 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$12 + connect \Y $not$issuer_ls180.v:160231$9645_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$issuer_ls180.v:160233$9647 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$16 + connect \Y $not$issuer_ls180.v:160233$9647_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" + cell $not $not$issuer_ls180.v:160234$9648 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 8 + connect \A { \i [0] \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] } + connect \Y $not$issuer_ls180.v:160234$9648_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$issuer_ls180.v:160236$9650 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$20 + connect \Y $not$issuer_ls180.v:160236$9650_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$issuer_ls180.v:160238$9652 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$24 + connect \Y $not$issuer_ls180.v:160238$9652_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$issuer_ls180.v:160240$9654 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$28 + connect \Y $not$issuer_ls180.v:160240$9654_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$issuer_ls180.v:160243$9657 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$4 + connect \Y $not$issuer_ls180.v:160243$9657_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$issuer_ls180.v:160230$9644 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A { \i [5] \i [6] \i [7] \ni [3] } + connect \Y $reduce_or$issuer_ls180.v:160230$9644_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$issuer_ls180.v:160232$9646 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A { \i [4] \i [5] \i [6] \i [7] \ni [4] } + connect \Y $reduce_or$issuer_ls180.v:160232$9646_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$issuer_ls180.v:160235$9649 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A { \i [3] \i [4] \i [5] \i [6] \i [7] \ni [5] } + connect \Y $reduce_or$issuer_ls180.v:160235$9649_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$issuer_ls180.v:160237$9651 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A { \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [6] } + connect \Y $reduce_or$issuer_ls180.v:160237$9651_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$issuer_ls180.v:160239$9653 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A { \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [7] } + connect \Y $reduce_or$issuer_ls180.v:160239$9653_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" + cell $reduce_or $reduce_or$issuer_ls180.v:160241$9655 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \o + connect \Y $reduce_or$issuer_ls180.v:160241$9655_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$issuer_ls180.v:160242$9656 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A { \i [7] \ni [1] } + connect \Y $reduce_or$issuer_ls180.v:160242$9656_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$issuer_ls180.v:160244$9658 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A { \i [6] \i [7] \ni [2] } + connect \Y $reduce_or$issuer_ls180.v:160244$9658_Y + end + connect \$7 $not$issuer_ls180.v:160229$9643_Y + connect \$12 $reduce_or$issuer_ls180.v:160230$9644_Y + connect \$11 $not$issuer_ls180.v:160231$9645_Y + connect \$16 $reduce_or$issuer_ls180.v:160232$9646_Y + connect \$15 $not$issuer_ls180.v:160233$9647_Y + connect \$1 $not$issuer_ls180.v:160234$9648_Y + connect \$20 $reduce_or$issuer_ls180.v:160235$9649_Y + connect \$19 $not$issuer_ls180.v:160236$9650_Y + connect \$24 $reduce_or$issuer_ls180.v:160237$9651_Y + connect \$23 $not$issuer_ls180.v:160238$9652_Y + connect \$28 $reduce_or$issuer_ls180.v:160239$9653_Y + connect \$27 $not$issuer_ls180.v:160240$9654_Y + connect \$31 $reduce_or$issuer_ls180.v:160241$9655_Y + connect \$4 $reduce_or$issuer_ls180.v:160242$9656_Y + connect \$3 $not$issuer_ls180.v:160243$9657_Y + connect \$8 $reduce_or$issuer_ls180.v:160244$9658_Y + connect \en_o \$31 + connect \o { \t0 \t1 \t2 \t3 \t4 \t5 \t6 \t7 } + connect \t7 \$27 + connect \t6 \$23 + connect \t5 \$19 + connect \t4 \$15 + connect \t3 \$11 + connect \t2 \$7 + connect \t1 \$3 + connect \t0 \i [7] + connect \ni \$1 +end +attribute \src "issuer_ls180.v:160260.1-160344.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.dec2.dec_cr_out.ppick" +attribute \generator "nMigen" +module \ppick$208 + attribute \src "issuer_ls180.v:160317.17-160317.91" + wire $not$issuer_ls180.v:160317$9659_Y + attribute \src "issuer_ls180.v:160319.18-160319.93" + wire $not$issuer_ls180.v:160319$9661_Y + attribute \src "issuer_ls180.v:160321.18-160321.93" + wire $not$issuer_ls180.v:160321$9663_Y + attribute \src "issuer_ls180.v:160322.17-160322.138" + wire width 8 $not$issuer_ls180.v:160322$9664_Y + attribute \src "issuer_ls180.v:160324.18-160324.93" + wire $not$issuer_ls180.v:160324$9666_Y + attribute \src "issuer_ls180.v:160326.18-160326.93" + wire $not$issuer_ls180.v:160326$9668_Y + attribute \src "issuer_ls180.v:160328.18-160328.93" + wire $not$issuer_ls180.v:160328$9670_Y + attribute \src "issuer_ls180.v:160331.17-160331.91" + wire $not$issuer_ls180.v:160331$9673_Y + attribute \src "issuer_ls180.v:160318.18-160318.116" + wire $reduce_or$issuer_ls180.v:160318$9660_Y + attribute \src "issuer_ls180.v:160320.18-160320.122" + wire $reduce_or$issuer_ls180.v:160320$9662_Y + attribute \src "issuer_ls180.v:160323.18-160323.128" + wire $reduce_or$issuer_ls180.v:160323$9665_Y + attribute \src "issuer_ls180.v:160325.18-160325.134" + wire $reduce_or$issuer_ls180.v:160325$9667_Y + attribute \src "issuer_ls180.v:160327.18-160327.140" + wire $reduce_or$issuer_ls180.v:160327$9669_Y + attribute \src "issuer_ls180.v:160329.18-160329.90" + wire $reduce_or$issuer_ls180.v:160329$9671_Y + attribute \src "issuer_ls180.v:160330.17-160330.103" + wire $reduce_or$issuer_ls180.v:160330$9672_Y + attribute \src "issuer_ls180.v:160332.17-160332.109" + wire $reduce_or$issuer_ls180.v:160332$9674_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" + wire width 8 \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$12 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$16 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$19 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$20 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$23 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$24 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$27 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$28 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" + wire \$31 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$4 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$8 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" + wire output 1 \en_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" + wire width 8 input 3 \i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:49" + wire width 8 \ni + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" + wire width 8 output 2 \o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t0 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t2 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t4 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t6 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$issuer_ls180.v:160317$9659 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$8 + connect \Y $not$issuer_ls180.v:160317$9659_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$issuer_ls180.v:160319$9661 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$12 + connect \Y $not$issuer_ls180.v:160319$9661_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$issuer_ls180.v:160321$9663 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$16 + connect \Y $not$issuer_ls180.v:160321$9663_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" + cell $not $not$issuer_ls180.v:160322$9664 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 8 + connect \A { \i [0] \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] } + connect \Y $not$issuer_ls180.v:160322$9664_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$issuer_ls180.v:160324$9666 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$20 + connect \Y $not$issuer_ls180.v:160324$9666_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$issuer_ls180.v:160326$9668 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$24 + connect \Y $not$issuer_ls180.v:160326$9668_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$issuer_ls180.v:160328$9670 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$28 + connect \Y $not$issuer_ls180.v:160328$9670_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$issuer_ls180.v:160331$9673 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$4 + connect \Y $not$issuer_ls180.v:160331$9673_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$issuer_ls180.v:160318$9660 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A { \i [5] \i [6] \i [7] \ni [3] } + connect \Y $reduce_or$issuer_ls180.v:160318$9660_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$issuer_ls180.v:160320$9662 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A { \i [4] \i [5] \i [6] \i [7] \ni [4] } + connect \Y $reduce_or$issuer_ls180.v:160320$9662_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$issuer_ls180.v:160323$9665 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A { \i [3] \i [4] \i [5] \i [6] \i [7] \ni [5] } + connect \Y $reduce_or$issuer_ls180.v:160323$9665_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$issuer_ls180.v:160325$9667 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A { \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [6] } + connect \Y $reduce_or$issuer_ls180.v:160325$9667_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$issuer_ls180.v:160327$9669 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A { \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [7] } + connect \Y $reduce_or$issuer_ls180.v:160327$9669_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" + cell $reduce_or $reduce_or$issuer_ls180.v:160329$9671 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \o + connect \Y $reduce_or$issuer_ls180.v:160329$9671_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$issuer_ls180.v:160330$9672 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A { \i [7] \ni [1] } + connect \Y $reduce_or$issuer_ls180.v:160330$9672_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$issuer_ls180.v:160332$9674 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A { \i [6] \i [7] \ni [2] } + connect \Y $reduce_or$issuer_ls180.v:160332$9674_Y + end + connect \$7 $not$issuer_ls180.v:160317$9659_Y + connect \$12 $reduce_or$issuer_ls180.v:160318$9660_Y + connect \$11 $not$issuer_ls180.v:160319$9661_Y + connect \$16 $reduce_or$issuer_ls180.v:160320$9662_Y + connect \$15 $not$issuer_ls180.v:160321$9663_Y + connect \$1 $not$issuer_ls180.v:160322$9664_Y + connect \$20 $reduce_or$issuer_ls180.v:160323$9665_Y + connect \$19 $not$issuer_ls180.v:160324$9666_Y + connect \$24 $reduce_or$issuer_ls180.v:160325$9667_Y + connect \$23 $not$issuer_ls180.v:160326$9668_Y + connect \$28 $reduce_or$issuer_ls180.v:160327$9669_Y + connect \$27 $not$issuer_ls180.v:160328$9670_Y + connect \$31 $reduce_or$issuer_ls180.v:160329$9671_Y + connect \$4 $reduce_or$issuer_ls180.v:160330$9672_Y + connect \$3 $not$issuer_ls180.v:160331$9673_Y + connect \$8 $reduce_or$issuer_ls180.v:160332$9674_Y + connect \en_o \$31 + connect \o { \t0 \t1 \t2 \t3 \t4 \t5 \t6 \t7 } + connect \t7 \$27 + connect \t6 \$23 + connect \t5 \$19 + connect \t4 \$15 + connect \t3 \$11 + connect \t2 \$7 + connect \t1 \$3 + connect \t0 \i [7] + connect \ni \$1 +end +attribute \src "issuer_ls180.v:160348.1-160378.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.rdpick_CR_cr_a" +attribute \generator "nMigen" +module \rdpick_CR_cr_a + attribute \src "issuer_ls180.v:160369.17-160369.89" + wire width 2 $not$issuer_ls180.v:160369$9675_Y + attribute \src "issuer_ls180.v:160371.17-160371.91" + wire $not$issuer_ls180.v:160371$9677_Y + attribute \src "issuer_ls180.v:160370.17-160370.103" + wire $reduce_or$issuer_ls180.v:160370$9676_Y + attribute \src "issuer_ls180.v:160372.17-160372.89" + wire $reduce_or$issuer_ls180.v:160372$9678_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" + wire width 2 \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$4 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" + wire output 2 \en_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" + wire width 2 input 3 \i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:49" + wire width 2 \ni + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" + wire width 2 output 1 \o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t0 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" + cell $not $not$issuer_ls180.v:160369$9675 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 2 + connect \A \i + connect \Y $not$issuer_ls180.v:160369$9675_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$issuer_ls180.v:160371$9677 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$4 + connect \Y $not$issuer_ls180.v:160371$9677_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$issuer_ls180.v:160370$9676 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A { \i [0] \ni [1] } + connect \Y $reduce_or$issuer_ls180.v:160370$9676_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" + cell $reduce_or $reduce_or$issuer_ls180.v:160372$9678 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \o + connect \Y $reduce_or$issuer_ls180.v:160372$9678_Y + end + connect \$1 $not$issuer_ls180.v:160369$9675_Y + connect \$4 $reduce_or$issuer_ls180.v:160370$9676_Y + connect \$3 $not$issuer_ls180.v:160371$9677_Y + connect \$7 $reduce_or$issuer_ls180.v:160372$9678_Y + connect \en_o \$7 + connect \o { \t1 \t0 } + connect \t1 \$3 + connect \t0 \i [0] + connect \ni \$1 +end +attribute \src "issuer_ls180.v:160382.1-160403.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.rdpick_CR_cr_b" +attribute \generator "nMigen" +module \rdpick_CR_cr_b + attribute \src "issuer_ls180.v:160397.17-160397.89" + wire $not$issuer_ls180.v:160397$9679_Y + attribute \src "issuer_ls180.v:160398.17-160398.89" + wire $reduce_or$issuer_ls180.v:160398$9680_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" + wire output 2 \en_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" + wire input 3 \i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:49" + wire \ni + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" + wire output 1 \o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t0 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" + cell $not $not$issuer_ls180.v:160397$9679 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \i + connect \Y $not$issuer_ls180.v:160397$9679_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" + cell $reduce_or $reduce_or$issuer_ls180.v:160398$9680 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \o + connect \Y $reduce_or$issuer_ls180.v:160398$9680_Y + end + connect \$1 $not$issuer_ls180.v:160397$9679_Y + connect \$3 $reduce_or$issuer_ls180.v:160398$9680_Y + connect \en_o \$3 + connect \o \t0 + connect \t0 \i + connect \ni \$1 +end +attribute \src "issuer_ls180.v:160407.1-160428.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.rdpick_CR_cr_c" +attribute \generator "nMigen" +module \rdpick_CR_cr_c + attribute \src "issuer_ls180.v:160422.17-160422.89" + wire $not$issuer_ls180.v:160422$9681_Y + attribute \src "issuer_ls180.v:160423.17-160423.89" + wire $reduce_or$issuer_ls180.v:160423$9682_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" + wire output 2 \en_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" + wire input 3 \i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:49" + wire \ni + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" + wire output 1 \o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t0 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" + cell $not $not$issuer_ls180.v:160422$9681 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \i + connect \Y $not$issuer_ls180.v:160422$9681_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" + cell $reduce_or $reduce_or$issuer_ls180.v:160423$9682 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \o + connect \Y $reduce_or$issuer_ls180.v:160423$9682_Y + end + connect \$1 $not$issuer_ls180.v:160422$9681_Y + connect \$3 $reduce_or$issuer_ls180.v:160423$9682_Y + connect \en_o \$3 + connect \o \t0 + connect \t0 \i + connect \ni \$1 +end +attribute \src "issuer_ls180.v:160432.1-160453.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.rdpick_CR_full_cr" +attribute \generator "nMigen" +module \rdpick_CR_full_cr + attribute \src "issuer_ls180.v:160447.17-160447.89" + wire $not$issuer_ls180.v:160447$9683_Y + attribute \src "issuer_ls180.v:160448.17-160448.89" + wire $reduce_or$issuer_ls180.v:160448$9684_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" + wire output 2 \en_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" + wire input 3 \i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:49" + wire \ni + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" + wire output 1 \o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t0 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" + cell $not $not$issuer_ls180.v:160447$9683 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \i + connect \Y $not$issuer_ls180.v:160447$9683_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" + cell $reduce_or $reduce_or$issuer_ls180.v:160448$9684 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \o + connect \Y $reduce_or$issuer_ls180.v:160448$9684_Y + end + connect \$1 $not$issuer_ls180.v:160447$9683_Y + connect \$3 $reduce_or$issuer_ls180.v:160448$9684_Y + connect \en_o \$3 + connect \o \t0 + connect \t0 \i + connect \ni \$1 +end +attribute \src "issuer_ls180.v:160457.1-160496.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.rdpick_FAST_fast1" +attribute \generator "nMigen" +module \rdpick_FAST_fast1 + attribute \src "issuer_ls180.v:160484.17-160484.91" + wire $not$issuer_ls180.v:160484$9685_Y + attribute \src "issuer_ls180.v:160486.17-160486.89" + wire width 3 $not$issuer_ls180.v:160486$9687_Y + attribute \src "issuer_ls180.v:160488.17-160488.91" + wire $not$issuer_ls180.v:160488$9689_Y + attribute \src "issuer_ls180.v:160485.18-160485.90" + wire $reduce_or$issuer_ls180.v:160485$9686_Y + attribute \src "issuer_ls180.v:160487.17-160487.103" + wire $reduce_or$issuer_ls180.v:160487$9688_Y + attribute \src "issuer_ls180.v:160489.17-160489.105" + wire $reduce_or$issuer_ls180.v:160489$9690_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" + wire width 3 \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$4 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$8 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" + wire output 2 \en_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" + wire width 3 input 3 \i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:49" + wire width 3 \ni + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" + wire width 3 output 1 \o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t0 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t2 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$issuer_ls180.v:160484$9685 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$8 + connect \Y $not$issuer_ls180.v:160484$9685_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" + cell $not $not$issuer_ls180.v:160486$9687 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \i + connect \Y $not$issuer_ls180.v:160486$9687_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$issuer_ls180.v:160488$9689 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$4 + connect \Y $not$issuer_ls180.v:160488$9689_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" + cell $reduce_or $reduce_or$issuer_ls180.v:160485$9686 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \o + connect \Y $reduce_or$issuer_ls180.v:160485$9686_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$issuer_ls180.v:160487$9688 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A { \i [0] \ni [1] } + connect \Y $reduce_or$issuer_ls180.v:160487$9688_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$issuer_ls180.v:160489$9690 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A { \i [1:0] \ni [2] } + connect \Y $reduce_or$issuer_ls180.v:160489$9690_Y + end + connect \$7 $not$issuer_ls180.v:160484$9685_Y + connect \$11 $reduce_or$issuer_ls180.v:160485$9686_Y + connect \$1 $not$issuer_ls180.v:160486$9687_Y + connect \$4 $reduce_or$issuer_ls180.v:160487$9688_Y + connect \$3 $not$issuer_ls180.v:160488$9689_Y + connect \$8 $reduce_or$issuer_ls180.v:160489$9690_Y + connect \en_o \$11 + connect \o { \t2 \t1 \t0 } + connect \t2 \$7 + connect \t1 \$3 + connect \t0 \i [0] + connect \ni \$1 +end +attribute \src "issuer_ls180.v:160500.1-160530.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.rdpick_FAST_fast2" +attribute \generator "nMigen" +module \rdpick_FAST_fast2 + attribute \src "issuer_ls180.v:160521.17-160521.89" + wire width 2 $not$issuer_ls180.v:160521$9691_Y + attribute \src "issuer_ls180.v:160523.17-160523.91" + wire $not$issuer_ls180.v:160523$9693_Y + attribute \src "issuer_ls180.v:160522.17-160522.103" + wire $reduce_or$issuer_ls180.v:160522$9692_Y + attribute \src "issuer_ls180.v:160524.17-160524.89" + wire $reduce_or$issuer_ls180.v:160524$9694_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" + wire width 2 \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$4 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" + wire output 2 \en_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" + wire width 2 input 3 \i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:49" + wire width 2 \ni + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" + wire width 2 output 1 \o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t0 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" + cell $not $not$issuer_ls180.v:160521$9691 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 2 + connect \A \i + connect \Y $not$issuer_ls180.v:160521$9691_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$issuer_ls180.v:160523$9693 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$4 + connect \Y $not$issuer_ls180.v:160523$9693_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$issuer_ls180.v:160522$9692 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A { \i [0] \ni [1] } + connect \Y $reduce_or$issuer_ls180.v:160522$9692_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" + cell $reduce_or $reduce_or$issuer_ls180.v:160524$9694 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \o + connect \Y $reduce_or$issuer_ls180.v:160524$9694_Y + end + connect \$1 $not$issuer_ls180.v:160521$9691_Y + connect \$4 $reduce_or$issuer_ls180.v:160522$9692_Y + connect \$3 $not$issuer_ls180.v:160523$9693_Y + connect \$7 $reduce_or$issuer_ls180.v:160524$9694_Y + connect \en_o \$7 + connect \o { \t1 \t0 } + connect \t1 \$3 + connect \t0 \i [0] + connect \ni \$1 +end +attribute \src "issuer_ls180.v:160534.1-160627.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.rdpick_INT_ra" +attribute \generator "nMigen" +module \rdpick_INT_ra + attribute \src "issuer_ls180.v:160597.17-160597.91" + wire $not$issuer_ls180.v:160597$9695_Y + attribute \src "issuer_ls180.v:160599.18-160599.93" + wire $not$issuer_ls180.v:160599$9697_Y + attribute \src "issuer_ls180.v:160601.18-160601.93" + wire $not$issuer_ls180.v:160601$9699_Y + attribute \src "issuer_ls180.v:160602.17-160602.89" + wire width 9 $not$issuer_ls180.v:160602$9700_Y + attribute \src "issuer_ls180.v:160604.18-160604.93" + wire $not$issuer_ls180.v:160604$9702_Y + attribute \src "issuer_ls180.v:160606.18-160606.93" + wire $not$issuer_ls180.v:160606$9704_Y + attribute \src "issuer_ls180.v:160608.18-160608.93" + wire $not$issuer_ls180.v:160608$9706_Y + attribute \src "issuer_ls180.v:160610.18-160610.93" + wire $not$issuer_ls180.v:160610$9708_Y + attribute \src "issuer_ls180.v:160613.17-160613.91" + wire $not$issuer_ls180.v:160613$9711_Y + attribute \src "issuer_ls180.v:160598.18-160598.106" + wire $reduce_or$issuer_ls180.v:160598$9696_Y + attribute \src "issuer_ls180.v:160600.18-160600.106" + wire $reduce_or$issuer_ls180.v:160600$9698_Y + attribute \src "issuer_ls180.v:160603.18-160603.106" + wire $reduce_or$issuer_ls180.v:160603$9701_Y + attribute \src "issuer_ls180.v:160605.18-160605.106" + wire $reduce_or$issuer_ls180.v:160605$9703_Y + attribute \src "issuer_ls180.v:160607.18-160607.106" + wire $reduce_or$issuer_ls180.v:160607$9705_Y + attribute \src "issuer_ls180.v:160609.18-160609.106" + wire $reduce_or$issuer_ls180.v:160609$9707_Y + attribute \src "issuer_ls180.v:160611.18-160611.90" + wire $reduce_or$issuer_ls180.v:160611$9709_Y + attribute \src "issuer_ls180.v:160612.17-160612.103" + wire $reduce_or$issuer_ls180.v:160612$9710_Y + attribute \src "issuer_ls180.v:160614.17-160614.105" + wire $reduce_or$issuer_ls180.v:160614$9712_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" + wire width 9 \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$12 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$16 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$19 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$20 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$23 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$24 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$27 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$28 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$31 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$32 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" + wire \$35 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$4 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$8 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" + wire output 2 \en_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" + wire width 9 input 3 \i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:49" + wire width 9 \ni + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" + wire width 9 output 1 \o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t0 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t2 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t4 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t6 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t8 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$issuer_ls180.v:160597$9695 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$8 + connect \Y $not$issuer_ls180.v:160597$9695_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$issuer_ls180.v:160599$9697 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$12 + connect \Y $not$issuer_ls180.v:160599$9697_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$issuer_ls180.v:160601$9699 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$16 + connect \Y $not$issuer_ls180.v:160601$9699_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" + cell $not $not$issuer_ls180.v:160602$9700 + parameter \A_SIGNED 0 + parameter \A_WIDTH 9 + parameter \Y_WIDTH 9 + connect \A \i + connect \Y $not$issuer_ls180.v:160602$9700_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$issuer_ls180.v:160604$9702 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$20 + connect \Y $not$issuer_ls180.v:160604$9702_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$issuer_ls180.v:160606$9704 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$24 + connect \Y $not$issuer_ls180.v:160606$9704_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$issuer_ls180.v:160608$9706 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$28 + connect \Y $not$issuer_ls180.v:160608$9706_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$issuer_ls180.v:160610$9708 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$32 + connect \Y $not$issuer_ls180.v:160610$9708_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$issuer_ls180.v:160613$9711 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$4 + connect \Y $not$issuer_ls180.v:160613$9711_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$issuer_ls180.v:160598$9696 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A { \i [2:0] \ni [3] } + connect \Y $reduce_or$issuer_ls180.v:160598$9696_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$issuer_ls180.v:160600$9698 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A { \i [3:0] \ni [4] } + connect \Y $reduce_or$issuer_ls180.v:160600$9698_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$issuer_ls180.v:160603$9701 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A { \i [4:0] \ni [5] } + connect \Y $reduce_or$issuer_ls180.v:160603$9701_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$issuer_ls180.v:160605$9703 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A { \i [5:0] \ni [6] } + connect \Y $reduce_or$issuer_ls180.v:160605$9703_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$issuer_ls180.v:160607$9705 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A { \i [6:0] \ni [7] } + connect \Y $reduce_or$issuer_ls180.v:160607$9705_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$issuer_ls180.v:160609$9707 + parameter \A_SIGNED 0 + parameter \A_WIDTH 9 + parameter \Y_WIDTH 1 + connect \A { \i [7:0] \ni [8] } + connect \Y $reduce_or$issuer_ls180.v:160609$9707_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" + cell $reduce_or $reduce_or$issuer_ls180.v:160611$9709 + parameter \A_SIGNED 0 + parameter \A_WIDTH 9 + parameter \Y_WIDTH 1 + connect \A \o + connect \Y $reduce_or$issuer_ls180.v:160611$9709_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$issuer_ls180.v:160612$9710 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A { \i [0] \ni [1] } + connect \Y $reduce_or$issuer_ls180.v:160612$9710_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$issuer_ls180.v:160614$9712 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A { \i [1:0] \ni [2] } + connect \Y $reduce_or$issuer_ls180.v:160614$9712_Y + end + connect \$7 $not$issuer_ls180.v:160597$9695_Y + connect \$12 $reduce_or$issuer_ls180.v:160598$9696_Y + connect \$11 $not$issuer_ls180.v:160599$9697_Y + connect \$16 $reduce_or$issuer_ls180.v:160600$9698_Y + connect \$15 $not$issuer_ls180.v:160601$9699_Y + connect \$1 $not$issuer_ls180.v:160602$9700_Y + connect \$20 $reduce_or$issuer_ls180.v:160603$9701_Y + connect \$19 $not$issuer_ls180.v:160604$9702_Y + connect \$24 $reduce_or$issuer_ls180.v:160605$9703_Y + connect \$23 $not$issuer_ls180.v:160606$9704_Y + connect \$28 $reduce_or$issuer_ls180.v:160607$9705_Y + connect \$27 $not$issuer_ls180.v:160608$9706_Y + connect \$32 $reduce_or$issuer_ls180.v:160609$9707_Y + connect \$31 $not$issuer_ls180.v:160610$9708_Y + connect \$35 $reduce_or$issuer_ls180.v:160611$9709_Y + connect \$4 $reduce_or$issuer_ls180.v:160612$9710_Y + connect \$3 $not$issuer_ls180.v:160613$9711_Y + connect \$8 $reduce_or$issuer_ls180.v:160614$9712_Y + connect \en_o \$35 + connect \o { \t8 \t7 \t6 \t5 \t4 \t3 \t2 \t1 \t0 } + connect \t8 \$31 + connect \t7 \$27 + connect \t6 \$23 + connect \t5 \$19 + connect \t4 \$15 + connect \t3 \$11 + connect \t2 \$7 + connect \t1 \$3 + connect \t0 \i [0] + connect \ni \$1 +end +attribute \src "issuer_ls180.v:160631.1-160715.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.rdpick_INT_rb" +attribute \generator "nMigen" +module \rdpick_INT_rb + attribute \src "issuer_ls180.v:160688.17-160688.91" + wire $not$issuer_ls180.v:160688$9713_Y + attribute \src "issuer_ls180.v:160690.18-160690.93" + wire $not$issuer_ls180.v:160690$9715_Y + attribute \src "issuer_ls180.v:160692.18-160692.93" + wire $not$issuer_ls180.v:160692$9717_Y + attribute \src "issuer_ls180.v:160693.17-160693.89" + wire width 8 $not$issuer_ls180.v:160693$9718_Y + attribute \src "issuer_ls180.v:160695.18-160695.93" + wire $not$issuer_ls180.v:160695$9720_Y + attribute \src "issuer_ls180.v:160697.18-160697.93" + wire $not$issuer_ls180.v:160697$9722_Y + attribute \src "issuer_ls180.v:160699.18-160699.93" + wire $not$issuer_ls180.v:160699$9724_Y + attribute \src "issuer_ls180.v:160702.17-160702.91" + wire $not$issuer_ls180.v:160702$9727_Y + attribute \src "issuer_ls180.v:160689.18-160689.106" + wire $reduce_or$issuer_ls180.v:160689$9714_Y + attribute \src "issuer_ls180.v:160691.18-160691.106" + wire $reduce_or$issuer_ls180.v:160691$9716_Y + attribute \src "issuer_ls180.v:160694.18-160694.106" + wire $reduce_or$issuer_ls180.v:160694$9719_Y + attribute \src "issuer_ls180.v:160696.18-160696.106" + wire $reduce_or$issuer_ls180.v:160696$9721_Y + attribute \src "issuer_ls180.v:160698.18-160698.106" + wire $reduce_or$issuer_ls180.v:160698$9723_Y + attribute \src "issuer_ls180.v:160700.18-160700.90" + wire $reduce_or$issuer_ls180.v:160700$9725_Y + attribute \src "issuer_ls180.v:160701.17-160701.103" + wire $reduce_or$issuer_ls180.v:160701$9726_Y + attribute \src "issuer_ls180.v:160703.17-160703.105" + wire $reduce_or$issuer_ls180.v:160703$9728_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" + wire width 8 \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$12 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$16 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$19 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$20 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$23 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$24 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$27 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$28 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" + wire \$31 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$4 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$8 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" + wire output 2 \en_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" + wire width 8 input 3 \i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:49" + wire width 8 \ni + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" + wire width 8 output 1 \o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t0 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t2 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t4 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t6 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$issuer_ls180.v:160688$9713 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$8 + connect \Y $not$issuer_ls180.v:160688$9713_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$issuer_ls180.v:160690$9715 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$12 + connect \Y $not$issuer_ls180.v:160690$9715_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$issuer_ls180.v:160692$9717 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$16 + connect \Y $not$issuer_ls180.v:160692$9717_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" + cell $not $not$issuer_ls180.v:160693$9718 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 8 + connect \A \i + connect \Y $not$issuer_ls180.v:160693$9718_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$issuer_ls180.v:160695$9720 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$20 + connect \Y $not$issuer_ls180.v:160695$9720_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$issuer_ls180.v:160697$9722 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$24 + connect \Y $not$issuer_ls180.v:160697$9722_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$issuer_ls180.v:160699$9724 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$28 + connect \Y $not$issuer_ls180.v:160699$9724_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$issuer_ls180.v:160702$9727 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$4 + connect \Y $not$issuer_ls180.v:160702$9727_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$issuer_ls180.v:160689$9714 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A { \i [2:0] \ni [3] } + connect \Y $reduce_or$issuer_ls180.v:160689$9714_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$issuer_ls180.v:160691$9716 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A { \i [3:0] \ni [4] } + connect \Y $reduce_or$issuer_ls180.v:160691$9716_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$issuer_ls180.v:160694$9719 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A { \i [4:0] \ni [5] } + connect \Y $reduce_or$issuer_ls180.v:160694$9719_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$issuer_ls180.v:160696$9721 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A { \i [5:0] \ni [6] } + connect \Y $reduce_or$issuer_ls180.v:160696$9721_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$issuer_ls180.v:160698$9723 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A { \i [6:0] \ni [7] } + connect \Y $reduce_or$issuer_ls180.v:160698$9723_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" + cell $reduce_or $reduce_or$issuer_ls180.v:160700$9725 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \o + connect \Y $reduce_or$issuer_ls180.v:160700$9725_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$issuer_ls180.v:160701$9726 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A { \i [0] \ni [1] } + connect \Y $reduce_or$issuer_ls180.v:160701$9726_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$issuer_ls180.v:160703$9728 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A { \i [1:0] \ni [2] } + connect \Y $reduce_or$issuer_ls180.v:160703$9728_Y + end + connect \$7 $not$issuer_ls180.v:160688$9713_Y + connect \$12 $reduce_or$issuer_ls180.v:160689$9714_Y + connect \$11 $not$issuer_ls180.v:160690$9715_Y + connect \$16 $reduce_or$issuer_ls180.v:160691$9716_Y + connect \$15 $not$issuer_ls180.v:160692$9717_Y + connect \$1 $not$issuer_ls180.v:160693$9718_Y + connect \$20 $reduce_or$issuer_ls180.v:160694$9719_Y + connect \$19 $not$issuer_ls180.v:160695$9720_Y + connect \$24 $reduce_or$issuer_ls180.v:160696$9721_Y + connect \$23 $not$issuer_ls180.v:160697$9722_Y + connect \$28 $reduce_or$issuer_ls180.v:160698$9723_Y + connect \$27 $not$issuer_ls180.v:160699$9724_Y + connect \$31 $reduce_or$issuer_ls180.v:160700$9725_Y + connect \$4 $reduce_or$issuer_ls180.v:160701$9726_Y + connect \$3 $not$issuer_ls180.v:160702$9727_Y + connect \$8 $reduce_or$issuer_ls180.v:160703$9728_Y + connect \en_o \$31 + connect \o { \t7 \t6 \t5 \t4 \t3 \t2 \t1 \t0 } + connect \t7 \$27 + connect \t6 \$23 + connect \t5 \$19 + connect \t4 \$15 + connect \t3 \$11 + connect \t2 \$7 + connect \t1 \$3 + connect \t0 \i [0] + connect \ni \$1 +end +attribute \src "issuer_ls180.v:160719.1-160749.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.rdpick_INT_rc" +attribute \generator "nMigen" +module \rdpick_INT_rc + attribute \src "issuer_ls180.v:160740.17-160740.89" + wire width 2 $not$issuer_ls180.v:160740$9729_Y + attribute \src "issuer_ls180.v:160742.17-160742.91" + wire $not$issuer_ls180.v:160742$9731_Y + attribute \src "issuer_ls180.v:160741.17-160741.103" + wire $reduce_or$issuer_ls180.v:160741$9730_Y + attribute \src "issuer_ls180.v:160743.17-160743.89" + wire $reduce_or$issuer_ls180.v:160743$9732_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" + wire width 2 \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$4 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" + wire output 2 \en_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" + wire width 2 input 3 \i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:49" + wire width 2 \ni + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" + wire width 2 output 1 \o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t0 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" + cell $not $not$issuer_ls180.v:160740$9729 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 2 + connect \A \i + connect \Y $not$issuer_ls180.v:160740$9729_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$issuer_ls180.v:160742$9731 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$4 + connect \Y $not$issuer_ls180.v:160742$9731_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$issuer_ls180.v:160741$9730 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A { \i [0] \ni [1] } + connect \Y $reduce_or$issuer_ls180.v:160741$9730_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" + cell $reduce_or $reduce_or$issuer_ls180.v:160743$9732 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \o + connect \Y $reduce_or$issuer_ls180.v:160743$9732_Y + end + connect \$1 $not$issuer_ls180.v:160740$9729_Y + connect \$4 $reduce_or$issuer_ls180.v:160741$9730_Y + connect \$3 $not$issuer_ls180.v:160742$9731_Y + connect \$7 $reduce_or$issuer_ls180.v:160743$9732_Y + connect \en_o \$7 + connect \o { \t1 \t0 } + connect \t1 \$3 + connect \t0 \i [0] + connect \ni \$1 +end +attribute \src "issuer_ls180.v:160753.1-160774.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.rdpick_SPR_spr1" +attribute \generator "nMigen" +module \rdpick_SPR_spr1 + attribute \src "issuer_ls180.v:160768.17-160768.89" + wire $not$issuer_ls180.v:160768$9733_Y + attribute \src "issuer_ls180.v:160769.17-160769.89" + wire $reduce_or$issuer_ls180.v:160769$9734_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" + wire output 2 \en_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" + wire input 3 \i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:49" + wire \ni + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" + wire output 1 \o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t0 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" + cell $not $not$issuer_ls180.v:160768$9733 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \i + connect \Y $not$issuer_ls180.v:160768$9733_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" + cell $reduce_or $reduce_or$issuer_ls180.v:160769$9734 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \o + connect \Y $reduce_or$issuer_ls180.v:160769$9734_Y + end + connect \$1 $not$issuer_ls180.v:160768$9733_Y + connect \$3 $reduce_or$issuer_ls180.v:160769$9734_Y + connect \en_o \$3 + connect \o \t0 + connect \t0 \i + connect \ni \$1 +end +attribute \src "issuer_ls180.v:160778.1-160817.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.rdpick_XER_xer_ca" +attribute \generator "nMigen" +module \rdpick_XER_xer_ca + attribute \src "issuer_ls180.v:160805.17-160805.91" + wire $not$issuer_ls180.v:160805$9735_Y + attribute \src "issuer_ls180.v:160807.17-160807.89" + wire width 3 $not$issuer_ls180.v:160807$9737_Y + attribute \src "issuer_ls180.v:160809.17-160809.91" + wire $not$issuer_ls180.v:160809$9739_Y + attribute \src "issuer_ls180.v:160806.18-160806.90" + wire $reduce_or$issuer_ls180.v:160806$9736_Y + attribute \src "issuer_ls180.v:160808.17-160808.103" + wire $reduce_or$issuer_ls180.v:160808$9738_Y + attribute \src "issuer_ls180.v:160810.17-160810.105" + wire $reduce_or$issuer_ls180.v:160810$9740_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" + wire width 3 \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$4 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$8 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" + wire output 2 \en_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" + wire width 3 input 3 \i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:49" + wire width 3 \ni + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" + wire width 3 output 1 \o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t0 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t2 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$issuer_ls180.v:160805$9735 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$8 + connect \Y $not$issuer_ls180.v:160805$9735_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" + cell $not $not$issuer_ls180.v:160807$9737 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \i + connect \Y $not$issuer_ls180.v:160807$9737_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$issuer_ls180.v:160809$9739 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$4 + connect \Y $not$issuer_ls180.v:160809$9739_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" + cell $reduce_or $reduce_or$issuer_ls180.v:160806$9736 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \o + connect \Y $reduce_or$issuer_ls180.v:160806$9736_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$issuer_ls180.v:160808$9738 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A { \i [0] \ni [1] } + connect \Y $reduce_or$issuer_ls180.v:160808$9738_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$issuer_ls180.v:160810$9740 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A { \i [1:0] \ni [2] } + connect \Y $reduce_or$issuer_ls180.v:160810$9740_Y + end + connect \$7 $not$issuer_ls180.v:160805$9735_Y + connect \$11 $reduce_or$issuer_ls180.v:160806$9736_Y + connect \$1 $not$issuer_ls180.v:160807$9737_Y + connect \$4 $reduce_or$issuer_ls180.v:160808$9738_Y + connect \$3 $not$issuer_ls180.v:160809$9739_Y + connect \$8 $reduce_or$issuer_ls180.v:160810$9740_Y + connect \en_o \$11 + connect \o { \t2 \t1 \t0 } + connect \t2 \$7 + connect \t1 \$3 + connect \t0 \i [0] + connect \ni \$1 +end +attribute \src "issuer_ls180.v:160821.1-160842.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.rdpick_XER_xer_ov" +attribute \generator "nMigen" +module \rdpick_XER_xer_ov + attribute \src "issuer_ls180.v:160836.17-160836.89" + wire $not$issuer_ls180.v:160836$9741_Y + attribute \src "issuer_ls180.v:160837.17-160837.89" + wire $reduce_or$issuer_ls180.v:160837$9742_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" + wire output 2 \en_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" + wire input 3 \i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:49" + wire \ni + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" + wire output 1 \o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t0 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" + cell $not $not$issuer_ls180.v:160836$9741 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \i + connect \Y $not$issuer_ls180.v:160836$9741_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" + cell $reduce_or $reduce_or$issuer_ls180.v:160837$9742 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \o + connect \Y $reduce_or$issuer_ls180.v:160837$9742_Y + end + connect \$1 $not$issuer_ls180.v:160836$9741_Y + connect \$3 $reduce_or$issuer_ls180.v:160837$9742_Y + connect \en_o \$3 + connect \o \t0 + connect \t0 \i + connect \ni \$1 +end +attribute \src "issuer_ls180.v:160846.1-160912.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.rdpick_XER_xer_so" +attribute \generator "nMigen" +module \rdpick_XER_xer_so + attribute \src "issuer_ls180.v:160891.17-160891.91" + wire $not$issuer_ls180.v:160891$9743_Y + attribute \src "issuer_ls180.v:160893.18-160893.93" + wire $not$issuer_ls180.v:160893$9745_Y + attribute \src "issuer_ls180.v:160895.18-160895.93" + wire $not$issuer_ls180.v:160895$9747_Y + attribute \src "issuer_ls180.v:160896.17-160896.89" + wire width 6 $not$issuer_ls180.v:160896$9748_Y + attribute \src "issuer_ls180.v:160898.18-160898.93" + wire $not$issuer_ls180.v:160898$9750_Y + attribute \src "issuer_ls180.v:160901.17-160901.91" + wire $not$issuer_ls180.v:160901$9753_Y + attribute \src "issuer_ls180.v:160892.18-160892.106" + wire $reduce_or$issuer_ls180.v:160892$9744_Y + attribute \src "issuer_ls180.v:160894.18-160894.106" + wire $reduce_or$issuer_ls180.v:160894$9746_Y + attribute \src "issuer_ls180.v:160897.18-160897.106" + wire $reduce_or$issuer_ls180.v:160897$9749_Y + attribute \src "issuer_ls180.v:160899.18-160899.90" + wire $reduce_or$issuer_ls180.v:160899$9751_Y + attribute \src "issuer_ls180.v:160900.17-160900.103" + wire $reduce_or$issuer_ls180.v:160900$9752_Y + attribute \src "issuer_ls180.v:160902.17-160902.105" + wire $reduce_or$issuer_ls180.v:160902$9754_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" + wire width 6 \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$12 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$16 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$19 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$20 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" + wire \$23 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$4 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$8 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" + wire output 2 \en_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" + wire width 6 input 3 \i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:49" + wire width 6 \ni + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" + wire width 6 output 1 \o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t0 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t2 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t4 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$issuer_ls180.v:160891$9743 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$8 + connect \Y $not$issuer_ls180.v:160891$9743_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$issuer_ls180.v:160893$9745 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$12 + connect \Y $not$issuer_ls180.v:160893$9745_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$issuer_ls180.v:160895$9747 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$16 + connect \Y $not$issuer_ls180.v:160895$9747_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" + cell $not $not$issuer_ls180.v:160896$9748 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \Y_WIDTH 6 + connect \A \i + connect \Y $not$issuer_ls180.v:160896$9748_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$issuer_ls180.v:160898$9750 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$20 + connect \Y $not$issuer_ls180.v:160898$9750_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$issuer_ls180.v:160901$9753 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$4 + connect \Y $not$issuer_ls180.v:160901$9753_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$issuer_ls180.v:160892$9744 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A { \i [2:0] \ni [3] } + connect \Y $reduce_or$issuer_ls180.v:160892$9744_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$issuer_ls180.v:160894$9746 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A { \i [3:0] \ni [4] } + connect \Y $reduce_or$issuer_ls180.v:160894$9746_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$issuer_ls180.v:160897$9749 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A { \i [4:0] \ni [5] } + connect \Y $reduce_or$issuer_ls180.v:160897$9749_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" + cell $reduce_or $reduce_or$issuer_ls180.v:160899$9751 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \o + connect \Y $reduce_or$issuer_ls180.v:160899$9751_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$issuer_ls180.v:160900$9752 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A { \i [0] \ni [1] } + connect \Y $reduce_or$issuer_ls180.v:160900$9752_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$issuer_ls180.v:160902$9754 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A { \i [1:0] \ni [2] } + connect \Y $reduce_or$issuer_ls180.v:160902$9754_Y + end + connect \$7 $not$issuer_ls180.v:160891$9743_Y + connect \$12 $reduce_or$issuer_ls180.v:160892$9744_Y + connect \$11 $not$issuer_ls180.v:160893$9745_Y + connect \$16 $reduce_or$issuer_ls180.v:160894$9746_Y + connect \$15 $not$issuer_ls180.v:160895$9747_Y + connect \$1 $not$issuer_ls180.v:160896$9748_Y + connect \$20 $reduce_or$issuer_ls180.v:160897$9749_Y + connect \$19 $not$issuer_ls180.v:160898$9750_Y + connect \$23 $reduce_or$issuer_ls180.v:160899$9751_Y + connect \$4 $reduce_or$issuer_ls180.v:160900$9752_Y + connect \$3 $not$issuer_ls180.v:160901$9753_Y + connect \$8 $reduce_or$issuer_ls180.v:160902$9754_Y + connect \en_o \$23 + connect \o { \t5 \t4 \t3 \t2 \t1 \t0 } + connect \t5 \$19 + connect \t4 \$15 + connect \t3 \$11 + connect \t2 \$7 + connect \t1 \$3 + connect \t0 \i [0] + connect \ni \$1 +end +attribute \src "issuer_ls180.v:160916.1-161387.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.cr.reg_0" +attribute \generator "nMigen" +module \reg_0 + attribute \src "issuer_ls180.v:160917.7-160917.20" + wire $0\initial[0:0] + attribute \src "issuer_ls180.v:161247.3-161286.6" + wire width 4 $0\r0__data_o$next[3:0]$9810 + attribute \src "issuer_ls180.v:161002.3-161003.37" + wire width 4 $0\r0__data_o[3:0] + attribute \src "issuer_ls180.v:161317.3-161356.6" + wire width 4 $0\r20__data_o$next[3:0]$9824 + attribute \src "issuer_ls180.v:161000.3-161001.39" + wire width 4 $0\r20__data_o[3:0] + attribute \src "issuer_ls180.v:161080.3-161106.6" + wire width 4 $0\reg$next[3:0]$9776 + attribute \src "issuer_ls180.v:160998.3-160999.25" + wire width 4 $0\reg[3:0] + attribute \src "issuer_ls180.v:161010.3-161049.6" + wire width 4 $0\src10__data_o$next[3:0]$9767 + attribute \src "issuer_ls180.v:161008.3-161009.43" + wire width 4 $0\src10__data_o[3:0] + attribute \src "issuer_ls180.v:161107.3-161146.6" + wire width 4 $0\src20__data_o$next[3:0]$9782 + attribute \src "issuer_ls180.v:161006.3-161007.43" + wire width 4 $0\src20__data_o[3:0] + attribute \src "issuer_ls180.v:161177.3-161216.6" + wire width 4 $0\src30__data_o$next[3:0]$9796 + attribute \src "issuer_ls180.v:161004.3-161005.43" + wire width 4 $0\src30__data_o[3:0] + attribute \src "issuer_ls180.v:161287.3-161316.6" + wire $0\wr_detect$10[0:0]$9818 + attribute \src "issuer_ls180.v:161357.3-161386.6" + wire $0\wr_detect$13[0:0]$9832 + attribute \src "issuer_ls180.v:161147.3-161176.6" + wire $0\wr_detect$4[0:0]$9790 + attribute \src "issuer_ls180.v:161217.3-161246.6" + wire $0\wr_detect$7[0:0]$9804 + attribute \src "issuer_ls180.v:161050.3-161079.6" + wire $0\wr_detect[0:0] + attribute \src "issuer_ls180.v:161247.3-161286.6" + wire width 4 $1\r0__data_o$next[3:0]$9811 + attribute \src "issuer_ls180.v:160942.13-160942.30" + wire width 4 $1\r0__data_o[3:0] + attribute \src "issuer_ls180.v:161317.3-161356.6" + wire width 4 $1\r20__data_o$next[3:0]$9825 + attribute \src "issuer_ls180.v:160949.13-160949.31" + wire width 4 $1\r20__data_o[3:0] + attribute \src "issuer_ls180.v:161080.3-161106.6" + wire width 4 $1\reg$next[3:0]$9777 + attribute \src "issuer_ls180.v:160955.13-160955.25" + wire width 4 $1\reg[3:0] + attribute \src "issuer_ls180.v:161010.3-161049.6" + wire width 4 $1\src10__data_o$next[3:0]$9768 + attribute \src "issuer_ls180.v:160960.13-160960.33" + wire width 4 $1\src10__data_o[3:0] + attribute \src "issuer_ls180.v:161107.3-161146.6" + wire width 4 $1\src20__data_o$next[3:0]$9783 + attribute \src "issuer_ls180.v:160967.13-160967.33" + wire width 4 $1\src20__data_o[3:0] + attribute \src "issuer_ls180.v:161177.3-161216.6" + wire width 4 $1\src30__data_o$next[3:0]$9797 + attribute \src "issuer_ls180.v:160974.13-160974.33" + wire width 4 $1\src30__data_o[3:0] + attribute \src "issuer_ls180.v:161287.3-161316.6" + wire $1\wr_detect$10[0:0]$9819 + attribute \src "issuer_ls180.v:161357.3-161386.6" + wire $1\wr_detect$13[0:0]$9833 + attribute \src "issuer_ls180.v:161147.3-161176.6" + wire $1\wr_detect$4[0:0]$9791 + attribute \src "issuer_ls180.v:161217.3-161246.6" + wire $1\wr_detect$7[0:0]$9805 + attribute \src "issuer_ls180.v:161050.3-161079.6" + wire $1\wr_detect[0:0] + attribute \src "issuer_ls180.v:161247.3-161286.6" + wire width 4 $2\r0__data_o$next[3:0]$9812 + attribute \src "issuer_ls180.v:161317.3-161356.6" + wire width 4 $2\r20__data_o$next[3:0]$9826 + attribute \src "issuer_ls180.v:161080.3-161106.6" + wire width 4 $2\reg$next[3:0]$9778 + attribute \src "issuer_ls180.v:161010.3-161049.6" + wire width 4 $2\src10__data_o$next[3:0]$9769 + attribute \src "issuer_ls180.v:161107.3-161146.6" + wire width 4 $2\src20__data_o$next[3:0]$9784 + attribute \src "issuer_ls180.v:161177.3-161216.6" + wire width 4 $2\src30__data_o$next[3:0]$9798 + attribute \src "issuer_ls180.v:161287.3-161316.6" + wire $2\wr_detect$10[0:0]$9820 + attribute \src "issuer_ls180.v:161357.3-161386.6" + wire $2\wr_detect$13[0:0]$9834 + attribute \src "issuer_ls180.v:161147.3-161176.6" + wire $2\wr_detect$4[0:0]$9792 + attribute \src "issuer_ls180.v:161217.3-161246.6" + wire $2\wr_detect$7[0:0]$9806 + attribute \src "issuer_ls180.v:161050.3-161079.6" + wire $2\wr_detect[0:0] + attribute \src "issuer_ls180.v:161247.3-161286.6" + wire width 4 $3\r0__data_o$next[3:0]$9813 + attribute \src "issuer_ls180.v:161317.3-161356.6" + wire width 4 $3\r20__data_o$next[3:0]$9827 + attribute \src "issuer_ls180.v:161080.3-161106.6" + wire width 4 $3\reg$next[3:0]$9779 + attribute \src "issuer_ls180.v:161010.3-161049.6" + wire width 4 $3\src10__data_o$next[3:0]$9770 + attribute \src "issuer_ls180.v:161107.3-161146.6" + wire width 4 $3\src20__data_o$next[3:0]$9785 + attribute \src "issuer_ls180.v:161177.3-161216.6" + wire width 4 $3\src30__data_o$next[3:0]$9799 + attribute \src "issuer_ls180.v:161287.3-161316.6" + wire $3\wr_detect$10[0:0]$9821 + attribute \src "issuer_ls180.v:161357.3-161386.6" + wire $3\wr_detect$13[0:0]$9835 + attribute \src "issuer_ls180.v:161147.3-161176.6" + wire $3\wr_detect$4[0:0]$9793 + attribute \src "issuer_ls180.v:161217.3-161246.6" + wire $3\wr_detect$7[0:0]$9807 + attribute \src "issuer_ls180.v:161050.3-161079.6" + wire $3\wr_detect[0:0] + attribute \src "issuer_ls180.v:161247.3-161286.6" + wire width 4 $4\r0__data_o$next[3:0]$9814 + attribute \src "issuer_ls180.v:161317.3-161356.6" + wire width 4 $4\r20__data_o$next[3:0]$9828 + attribute \src "issuer_ls180.v:161080.3-161106.6" + wire width 4 $4\reg$next[3:0]$9780 + attribute \src "issuer_ls180.v:161010.3-161049.6" + wire width 4 $4\src10__data_o$next[3:0]$9771 + attribute \src "issuer_ls180.v:161107.3-161146.6" + wire width 4 $4\src20__data_o$next[3:0]$9786 + attribute \src "issuer_ls180.v:161177.3-161216.6" + wire width 4 $4\src30__data_o$next[3:0]$9800 + attribute \src "issuer_ls180.v:161287.3-161316.6" + wire $4\wr_detect$10[0:0]$9822 + attribute \src "issuer_ls180.v:161357.3-161386.6" + wire $4\wr_detect$13[0:0]$9836 + attribute \src "issuer_ls180.v:161147.3-161176.6" + wire $4\wr_detect$4[0:0]$9794 + attribute \src "issuer_ls180.v:161217.3-161246.6" + wire $4\wr_detect$7[0:0]$9808 + attribute \src "issuer_ls180.v:161050.3-161079.6" + wire $4\wr_detect[0:0] + attribute \src "issuer_ls180.v:161247.3-161286.6" + wire width 4 $5\r0__data_o$next[3:0]$9815 + attribute \src "issuer_ls180.v:161317.3-161356.6" + wire width 4 $5\r20__data_o$next[3:0]$9829 + attribute \src "issuer_ls180.v:161010.3-161049.6" + wire width 4 $5\src10__data_o$next[3:0]$9772 + attribute \src "issuer_ls180.v:161107.3-161146.6" + wire width 4 $5\src20__data_o$next[3:0]$9787 + attribute \src "issuer_ls180.v:161177.3-161216.6" + wire width 4 $5\src30__data_o$next[3:0]$9801 + attribute \src "issuer_ls180.v:161247.3-161286.6" + wire width 4 $6\r0__data_o$next[3:0]$9816 + attribute \src "issuer_ls180.v:161317.3-161356.6" + wire width 4 $6\r20__data_o$next[3:0]$9830 + attribute \src "issuer_ls180.v:161010.3-161049.6" + wire width 4 $6\src10__data_o$next[3:0]$9773 + attribute \src "issuer_ls180.v:161107.3-161146.6" + wire width 4 $6\src20__data_o$next[3:0]$9788 + attribute \src "issuer_ls180.v:161177.3-161216.6" + wire width 4 $6\src30__data_o$next[3:0]$9802 + attribute \src "issuer_ls180.v:160993.17-160993.104" + wire $not$issuer_ls180.v:160993$9755_Y + attribute \src "issuer_ls180.v:160994.18-160994.105" + wire $not$issuer_ls180.v:160994$9756_Y + attribute \src "issuer_ls180.v:160995.17-160995.100" + wire $not$issuer_ls180.v:160995$9757_Y + attribute \src "issuer_ls180.v:160996.17-160996.103" + wire $not$issuer_ls180.v:160996$9758_Y + attribute \src "issuer_ls180.v:160997.17-160997.103" + wire $not$issuer_ls180.v:160997$9759_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + wire \$12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + wire \$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + wire \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" + wire input 18 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" + wire input 1 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 input 9 \dest10__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire input 8 \dest10__wen + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 input 11 \dest20__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire input 10 \dest20__wen + attribute \src "issuer_ls180.v:160917.7-160917.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 output 12 \r0__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 \r0__data_o$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire input 13 \r0__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 output 14 \r20__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 \r20__data_o$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire input 15 \r20__ren + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" + wire width 4 \reg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" + wire width 4 \reg$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 output 3 \src10__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 \src10__data_o$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire input 2 \src10__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 output 5 \src20__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 \src20__data_o$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire input 4 \src20__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 output 7 \src30__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 \src30__data_o$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire input 6 \src30__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 input 16 \w0__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire input 17 \w0__wen + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" + wire \wr_detect + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" + wire \wr_detect$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" + wire \wr_detect$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" + wire \wr_detect$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" + wire \wr_detect$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + cell $not $not$issuer_ls180.v:160993$9755 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_detect$10 + connect \Y $not$issuer_ls180.v:160993$9755_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + cell $not $not$issuer_ls180.v:160994$9756 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_detect$13 + connect \Y $not$issuer_ls180.v:160994$9756_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + cell $not $not$issuer_ls180.v:160995$9757 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_detect + connect \Y $not$issuer_ls180.v:160995$9757_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + cell $not $not$issuer_ls180.v:160996$9758 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_detect$4 + connect \Y $not$issuer_ls180.v:160996$9758_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + cell $not $not$issuer_ls180.v:160997$9759 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_detect$7 + connect \Y $not$issuer_ls180.v:160997$9759_Y + end + attribute \src "issuer_ls180.v:160917.7-160917.20" + process $proc$issuer_ls180.v:160917$9837 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "issuer_ls180.v:160942.13-160942.30" + process $proc$issuer_ls180.v:160942$9838 + assign { } { } + assign $1\r0__data_o[3:0] 4'0000 + sync always + sync init + update \r0__data_o $1\r0__data_o[3:0] + end + attribute \src "issuer_ls180.v:160949.13-160949.31" + process $proc$issuer_ls180.v:160949$9839 + assign { } { } + assign $1\r20__data_o[3:0] 4'0000 + sync always + sync init + update \r20__data_o $1\r20__data_o[3:0] + end + attribute \src "issuer_ls180.v:160955.13-160955.25" + process $proc$issuer_ls180.v:160955$9840 + assign { } { } + assign $1\reg[3:0] 4'0000 + sync always + sync init + update \reg $1\reg[3:0] + end + attribute \src "issuer_ls180.v:160960.13-160960.33" + process $proc$issuer_ls180.v:160960$9841 + assign { } { } + assign $1\src10__data_o[3:0] 4'0000 + sync always + sync init + update \src10__data_o $1\src10__data_o[3:0] + end + attribute \src "issuer_ls180.v:160967.13-160967.33" + process $proc$issuer_ls180.v:160967$9842 + assign { } { } + assign $1\src20__data_o[3:0] 4'0000 + sync always + sync init + update \src20__data_o $1\src20__data_o[3:0] + end + attribute \src "issuer_ls180.v:160974.13-160974.33" + process $proc$issuer_ls180.v:160974$9843 + assign { } { } + assign $1\src30__data_o[3:0] 4'0000 + sync always + sync init + update \src30__data_o $1\src30__data_o[3:0] + end + attribute \src "issuer_ls180.v:160998.3-160999.25" + process $proc$issuer_ls180.v:160998$9760 + assign { } { } + assign $0\reg[3:0] \reg$next + sync posedge \coresync_clk + update \reg $0\reg[3:0] + end + attribute \src "issuer_ls180.v:161000.3-161001.39" + process $proc$issuer_ls180.v:161000$9761 + assign { } { } + assign $0\r20__data_o[3:0] \r20__data_o$next + sync posedge \coresync_clk + update \r20__data_o $0\r20__data_o[3:0] + end + attribute \src "issuer_ls180.v:161002.3-161003.37" + process $proc$issuer_ls180.v:161002$9762 + assign { } { } + assign $0\r0__data_o[3:0] \r0__data_o$next + sync posedge \coresync_clk + update \r0__data_o $0\r0__data_o[3:0] + end + attribute \src "issuer_ls180.v:161004.3-161005.43" + process $proc$issuer_ls180.v:161004$9763 + assign { } { } + assign $0\src30__data_o[3:0] \src30__data_o$next + sync posedge \coresync_clk + update \src30__data_o $0\src30__data_o[3:0] + end + attribute \src "issuer_ls180.v:161006.3-161007.43" + process $proc$issuer_ls180.v:161006$9764 + assign { } { } + assign $0\src20__data_o[3:0] \src20__data_o$next + sync posedge \coresync_clk + update \src20__data_o $0\src20__data_o[3:0] + end + attribute \src "issuer_ls180.v:161008.3-161009.43" + process $proc$issuer_ls180.v:161008$9765 + assign { } { } + assign $0\src10__data_o[3:0] \src10__data_o$next + sync posedge \coresync_clk + update \src10__data_o $0\src10__data_o[3:0] + end + attribute \src "issuer_ls180.v:161010.3-161049.6" + process $proc$issuer_ls180.v:161010$9766 + assign { } { } + assign { } { } + assign { } { } + assign $0\src10__data_o$next[3:0]$9767 $6\src10__data_o$next[3:0]$9773 + attribute \src "issuer_ls180.v:161011.5-161011.29" + switch \initial + attribute \src "issuer_ls180.v:161011.9-161011.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \src10__ren + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\src10__data_o$next[3:0]$9768 $5\src10__data_o$next[3:0]$9772 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest10__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\src10__data_o$next[3:0]$9769 \dest10__data_i + case + assign $2\src10__data_o$next[3:0]$9769 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest20__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\src10__data_o$next[3:0]$9770 \dest20__data_i + case + assign $3\src10__data_o$next[3:0]$9770 $2\src10__data_o$next[3:0]$9769 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w0__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\src10__data_o$next[3:0]$9771 \w0__data_i + case + assign $4\src10__data_o$next[3:0]$9771 $3\src10__data_o$next[3:0]$9770 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + switch \$1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\src10__data_o$next[3:0]$9772 \reg + case + assign $5\src10__data_o$next[3:0]$9772 $4\src10__data_o$next[3:0]$9771 + end + case + assign $1\src10__data_o$next[3:0]$9768 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $6\src10__data_o$next[3:0]$9773 4'0000 + case + assign $6\src10__data_o$next[3:0]$9773 $1\src10__data_o$next[3:0]$9768 + end + sync always + update \src10__data_o$next $0\src10__data_o$next[3:0]$9767 + end + attribute \src "issuer_ls180.v:161050.3-161079.6" + process $proc$issuer_ls180.v:161050$9774 + assign { } { } + assign { } { } + assign $0\wr_detect[0:0] $1\wr_detect[0:0] + attribute \src "issuer_ls180.v:161051.5-161051.29" + switch \initial + attribute \src "issuer_ls180.v:161051.9-161051.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \src10__ren + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\wr_detect[0:0] $4\wr_detect[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest10__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\wr_detect[0:0] 1'1 + case + assign $2\wr_detect[0:0] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest20__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\wr_detect[0:0] 1'1 + case + assign $3\wr_detect[0:0] $2\wr_detect[0:0] + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w0__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\wr_detect[0:0] 1'1 + case + assign $4\wr_detect[0:0] $3\wr_detect[0:0] + end + case + assign $1\wr_detect[0:0] 1'0 + end + sync always + update \wr_detect $0\wr_detect[0:0] + end + attribute \src "issuer_ls180.v:161080.3-161106.6" + process $proc$issuer_ls180.v:161080$9775 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\reg$next[3:0]$9776 $4\reg$next[3:0]$9780 + attribute \src "issuer_ls180.v:161081.5-161081.29" + switch \initial + attribute \src "issuer_ls180.v:161081.9-161081.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" + switch \dest10__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\reg$next[3:0]$9777 \dest10__data_i + case + assign $1\reg$next[3:0]$9777 \reg + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" + switch \dest20__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\reg$next[3:0]$9778 \dest20__data_i + case + assign $2\reg$next[3:0]$9778 $1\reg$next[3:0]$9777 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" + switch \w0__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\reg$next[3:0]$9779 \w0__data_i + case + assign $3\reg$next[3:0]$9779 $2\reg$next[3:0]$9778 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\reg$next[3:0]$9780 4'0000 + case + assign $4\reg$next[3:0]$9780 $3\reg$next[3:0]$9779 + end + sync always + update \reg$next $0\reg$next[3:0]$9776 + end + attribute \src "issuer_ls180.v:161107.3-161146.6" + process $proc$issuer_ls180.v:161107$9781 + assign { } { } + assign { } { } + assign { } { } + assign $0\src20__data_o$next[3:0]$9782 $6\src20__data_o$next[3:0]$9788 + attribute \src "issuer_ls180.v:161108.5-161108.29" + switch \initial + attribute \src "issuer_ls180.v:161108.9-161108.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \src20__ren + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\src20__data_o$next[3:0]$9783 $5\src20__data_o$next[3:0]$9787 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest10__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\src20__data_o$next[3:0]$9784 \dest10__data_i + case + assign $2\src20__data_o$next[3:0]$9784 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest20__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\src20__data_o$next[3:0]$9785 \dest20__data_i + case + assign $3\src20__data_o$next[3:0]$9785 $2\src20__data_o$next[3:0]$9784 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w0__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\src20__data_o$next[3:0]$9786 \w0__data_i + case + assign $4\src20__data_o$next[3:0]$9786 $3\src20__data_o$next[3:0]$9785 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + switch \$3 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\src20__data_o$next[3:0]$9787 \reg + case + assign $5\src20__data_o$next[3:0]$9787 $4\src20__data_o$next[3:0]$9786 + end + case + assign $1\src20__data_o$next[3:0]$9783 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $6\src20__data_o$next[3:0]$9788 4'0000 + case + assign $6\src20__data_o$next[3:0]$9788 $1\src20__data_o$next[3:0]$9783 + end + sync always + update \src20__data_o$next $0\src20__data_o$next[3:0]$9782 + end + attribute \src "issuer_ls180.v:161147.3-161176.6" + process $proc$issuer_ls180.v:161147$9789 + assign { } { } + assign { } { } + assign $0\wr_detect$4[0:0]$9790 $1\wr_detect$4[0:0]$9791 + attribute \src "issuer_ls180.v:161148.5-161148.29" + switch \initial + attribute \src "issuer_ls180.v:161148.9-161148.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \src20__ren + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\wr_detect$4[0:0]$9791 $4\wr_detect$4[0:0]$9794 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest10__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\wr_detect$4[0:0]$9792 1'1 + case + assign $2\wr_detect$4[0:0]$9792 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest20__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\wr_detect$4[0:0]$9793 1'1 + case + assign $3\wr_detect$4[0:0]$9793 $2\wr_detect$4[0:0]$9792 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w0__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\wr_detect$4[0:0]$9794 1'1 + case + assign $4\wr_detect$4[0:0]$9794 $3\wr_detect$4[0:0]$9793 + end + case + assign $1\wr_detect$4[0:0]$9791 1'0 + end + sync always + update \wr_detect$4 $0\wr_detect$4[0:0]$9790 + end + attribute \src "issuer_ls180.v:161177.3-161216.6" + process $proc$issuer_ls180.v:161177$9795 + assign { } { } + assign { } { } + assign { } { } + assign $0\src30__data_o$next[3:0]$9796 $6\src30__data_o$next[3:0]$9802 + attribute \src "issuer_ls180.v:161178.5-161178.29" + switch \initial + attribute \src "issuer_ls180.v:161178.9-161178.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \src30__ren + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\src30__data_o$next[3:0]$9797 $5\src30__data_o$next[3:0]$9801 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest10__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\src30__data_o$next[3:0]$9798 \dest10__data_i + case + assign $2\src30__data_o$next[3:0]$9798 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest20__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\src30__data_o$next[3:0]$9799 \dest20__data_i + case + assign $3\src30__data_o$next[3:0]$9799 $2\src30__data_o$next[3:0]$9798 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w0__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\src30__data_o$next[3:0]$9800 \w0__data_i + case + assign $4\src30__data_o$next[3:0]$9800 $3\src30__data_o$next[3:0]$9799 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + switch \$6 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\src30__data_o$next[3:0]$9801 \reg + case + assign $5\src30__data_o$next[3:0]$9801 $4\src30__data_o$next[3:0]$9800 + end + case + assign $1\src30__data_o$next[3:0]$9797 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $6\src30__data_o$next[3:0]$9802 4'0000 + case + assign $6\src30__data_o$next[3:0]$9802 $1\src30__data_o$next[3:0]$9797 + end + sync always + update \src30__data_o$next $0\src30__data_o$next[3:0]$9796 + end + attribute \src "issuer_ls180.v:161217.3-161246.6" + process $proc$issuer_ls180.v:161217$9803 + assign { } { } + assign { } { } + assign $0\wr_detect$7[0:0]$9804 $1\wr_detect$7[0:0]$9805 + attribute \src "issuer_ls180.v:161218.5-161218.29" + switch \initial + attribute \src "issuer_ls180.v:161218.9-161218.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \src30__ren + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\wr_detect$7[0:0]$9805 $4\wr_detect$7[0:0]$9808 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest10__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\wr_detect$7[0:0]$9806 1'1 + case + assign $2\wr_detect$7[0:0]$9806 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest20__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\wr_detect$7[0:0]$9807 1'1 + case + assign $3\wr_detect$7[0:0]$9807 $2\wr_detect$7[0:0]$9806 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w0__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\wr_detect$7[0:0]$9808 1'1 + case + assign $4\wr_detect$7[0:0]$9808 $3\wr_detect$7[0:0]$9807 + end + case + assign $1\wr_detect$7[0:0]$9805 1'0 + end + sync always + update \wr_detect$7 $0\wr_detect$7[0:0]$9804 + end + attribute \src "issuer_ls180.v:161247.3-161286.6" + process $proc$issuer_ls180.v:161247$9809 + assign { } { } + assign { } { } + assign { } { } + assign $0\r0__data_o$next[3:0]$9810 $6\r0__data_o$next[3:0]$9816 + attribute \src "issuer_ls180.v:161248.5-161248.29" + switch \initial + attribute \src "issuer_ls180.v:161248.9-161248.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \r0__ren + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\r0__data_o$next[3:0]$9811 $5\r0__data_o$next[3:0]$9815 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest10__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\r0__data_o$next[3:0]$9812 \dest10__data_i + case + assign $2\r0__data_o$next[3:0]$9812 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest20__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\r0__data_o$next[3:0]$9813 \dest20__data_i + case + assign $3\r0__data_o$next[3:0]$9813 $2\r0__data_o$next[3:0]$9812 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w0__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\r0__data_o$next[3:0]$9814 \w0__data_i + case + assign $4\r0__data_o$next[3:0]$9814 $3\r0__data_o$next[3:0]$9813 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + switch \$9 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\r0__data_o$next[3:0]$9815 \reg + case + assign $5\r0__data_o$next[3:0]$9815 $4\r0__data_o$next[3:0]$9814 + end + case + assign $1\r0__data_o$next[3:0]$9811 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $6\r0__data_o$next[3:0]$9816 4'0000 + case + assign $6\r0__data_o$next[3:0]$9816 $1\r0__data_o$next[3:0]$9811 + end + sync always + update \r0__data_o$next $0\r0__data_o$next[3:0]$9810 + end + attribute \src "issuer_ls180.v:161287.3-161316.6" + process $proc$issuer_ls180.v:161287$9817 + assign { } { } + assign { } { } + assign $0\wr_detect$10[0:0]$9818 $1\wr_detect$10[0:0]$9819 + attribute \src "issuer_ls180.v:161288.5-161288.29" + switch \initial + attribute \src "issuer_ls180.v:161288.9-161288.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \r0__ren + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\wr_detect$10[0:0]$9819 $4\wr_detect$10[0:0]$9822 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest10__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\wr_detect$10[0:0]$9820 1'1 + case + assign $2\wr_detect$10[0:0]$9820 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest20__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\wr_detect$10[0:0]$9821 1'1 + case + assign $3\wr_detect$10[0:0]$9821 $2\wr_detect$10[0:0]$9820 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w0__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\wr_detect$10[0:0]$9822 1'1 + case + assign $4\wr_detect$10[0:0]$9822 $3\wr_detect$10[0:0]$9821 + end + case + assign $1\wr_detect$10[0:0]$9819 1'0 + end + sync always + update \wr_detect$10 $0\wr_detect$10[0:0]$9818 + end + attribute \src "issuer_ls180.v:161317.3-161356.6" + process $proc$issuer_ls180.v:161317$9823 + assign { } { } + assign { } { } + assign { } { } + assign $0\r20__data_o$next[3:0]$9824 $6\r20__data_o$next[3:0]$9830 + attribute \src "issuer_ls180.v:161318.5-161318.29" + switch \initial + attribute \src "issuer_ls180.v:161318.9-161318.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \r20__ren + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\r20__data_o$next[3:0]$9825 $5\r20__data_o$next[3:0]$9829 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest10__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\r20__data_o$next[3:0]$9826 \dest10__data_i + case + assign $2\r20__data_o$next[3:0]$9826 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest20__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\r20__data_o$next[3:0]$9827 \dest20__data_i + case + assign $3\r20__data_o$next[3:0]$9827 $2\r20__data_o$next[3:0]$9826 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w0__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\r20__data_o$next[3:0]$9828 \w0__data_i + case + assign $4\r20__data_o$next[3:0]$9828 $3\r20__data_o$next[3:0]$9827 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + switch \$12 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\r20__data_o$next[3:0]$9829 \reg + case + assign $5\r20__data_o$next[3:0]$9829 $4\r20__data_o$next[3:0]$9828 + end + case + assign $1\r20__data_o$next[3:0]$9825 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $6\r20__data_o$next[3:0]$9830 4'0000 + case + assign $6\r20__data_o$next[3:0]$9830 $1\r20__data_o$next[3:0]$9825 + end + sync always + update \r20__data_o$next $0\r20__data_o$next[3:0]$9824 + end + attribute \src "issuer_ls180.v:161357.3-161386.6" + process $proc$issuer_ls180.v:161357$9831 + assign { } { } + assign { } { } + assign $0\wr_detect$13[0:0]$9832 $1\wr_detect$13[0:0]$9833 + attribute \src "issuer_ls180.v:161358.5-161358.29" + switch \initial + attribute \src "issuer_ls180.v:161358.9-161358.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \r20__ren + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\wr_detect$13[0:0]$9833 $4\wr_detect$13[0:0]$9836 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest10__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\wr_detect$13[0:0]$9834 1'1 + case + assign $2\wr_detect$13[0:0]$9834 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest20__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\wr_detect$13[0:0]$9835 1'1 + case + assign $3\wr_detect$13[0:0]$9835 $2\wr_detect$13[0:0]$9834 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w0__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\wr_detect$13[0:0]$9836 1'1 + case + assign $4\wr_detect$13[0:0]$9836 $3\wr_detect$13[0:0]$9835 + end + case + assign $1\wr_detect$13[0:0]$9833 1'0 + end + sync always + update \wr_detect$13 $0\wr_detect$13[0:0]$9832 + end + connect \$9 $not$issuer_ls180.v:160993$9755_Y + connect \$12 $not$issuer_ls180.v:160994$9756_Y + connect \$1 $not$issuer_ls180.v:160995$9757_Y + connect \$3 $not$issuer_ls180.v:160996$9758_Y + connect \$6 $not$issuer_ls180.v:160997$9759_Y +end +attribute \src "issuer_ls180.v:161391.1-161836.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.xer.reg_0" +attribute \generator "nMigen" +module \reg_0$129 + attribute \src "issuer_ls180.v:161392.7-161392.20" + wire $0\initial[0:0] + attribute \src "issuer_ls180.v:161721.3-161766.6" + wire width 2 $0\r0__data_o$next[1:0]$9896 + attribute \src "issuer_ls180.v:161467.3-161468.37" + wire width 2 $0\r0__data_o[1:0] + attribute \src "issuer_ls180.v:161803.3-161835.6" + wire width 2 $0\reg$next[1:0]$9912 + attribute \src "issuer_ls180.v:161465.3-161466.25" + wire width 2 $0\reg[1:0] + attribute \src "issuer_ls180.v:161475.3-161520.6" + wire width 2 $0\src10__data_o$next[1:0]$9854 + attribute \src "issuer_ls180.v:161473.3-161474.43" + wire width 2 $0\src10__data_o[1:0] + attribute \src "issuer_ls180.v:161557.3-161602.6" + wire width 2 $0\src20__data_o$next[1:0]$9864 + attribute \src "issuer_ls180.v:161471.3-161472.43" + wire width 2 $0\src20__data_o[1:0] + attribute \src "issuer_ls180.v:161639.3-161684.6" + wire width 2 $0\src30__data_o$next[1:0]$9880 + attribute \src "issuer_ls180.v:161469.3-161470.43" + wire width 2 $0\src30__data_o[1:0] + attribute \src "issuer_ls180.v:161767.3-161802.6" + wire $0\wr_detect$10[0:0]$9905 + attribute \src "issuer_ls180.v:161603.3-161638.6" + wire $0\wr_detect$4[0:0]$9873 + attribute \src "issuer_ls180.v:161685.3-161720.6" + wire $0\wr_detect$7[0:0]$9889 + attribute \src "issuer_ls180.v:161521.3-161556.6" + wire $0\wr_detect[0:0] + attribute \src "issuer_ls180.v:161721.3-161766.6" + wire width 2 $1\r0__data_o$next[1:0]$9897 + attribute \src "issuer_ls180.v:161419.13-161419.30" + wire width 2 $1\r0__data_o[1:0] + attribute \src "issuer_ls180.v:161803.3-161835.6" + wire width 2 $1\reg$next[1:0]$9913 + attribute \src "issuer_ls180.v:161425.13-161425.25" + wire width 2 $1\reg[1:0] + attribute \src "issuer_ls180.v:161475.3-161520.6" + wire width 2 $1\src10__data_o$next[1:0]$9855 + attribute \src "issuer_ls180.v:161430.13-161430.33" + wire width 2 $1\src10__data_o[1:0] + attribute \src "issuer_ls180.v:161557.3-161602.6" + wire width 2 $1\src20__data_o$next[1:0]$9865 + attribute \src "issuer_ls180.v:161437.13-161437.33" + wire width 2 $1\src20__data_o[1:0] + attribute \src "issuer_ls180.v:161639.3-161684.6" + wire width 2 $1\src30__data_o$next[1:0]$9881 + attribute \src "issuer_ls180.v:161444.13-161444.33" + wire width 2 $1\src30__data_o[1:0] + attribute \src "issuer_ls180.v:161767.3-161802.6" + wire $1\wr_detect$10[0:0]$9906 + attribute \src "issuer_ls180.v:161603.3-161638.6" + wire $1\wr_detect$4[0:0]$9874 + attribute \src "issuer_ls180.v:161685.3-161720.6" + wire $1\wr_detect$7[0:0]$9890 + attribute \src "issuer_ls180.v:161521.3-161556.6" + wire $1\wr_detect[0:0] + attribute \src "issuer_ls180.v:161721.3-161766.6" + wire width 2 $2\r0__data_o$next[1:0]$9898 + attribute \src "issuer_ls180.v:161803.3-161835.6" + wire width 2 $2\reg$next[1:0]$9914 + attribute \src "issuer_ls180.v:161475.3-161520.6" + wire width 2 $2\src10__data_o$next[1:0]$9856 + attribute \src "issuer_ls180.v:161557.3-161602.6" + wire width 2 $2\src20__data_o$next[1:0]$9866 + attribute \src "issuer_ls180.v:161639.3-161684.6" + wire width 2 $2\src30__data_o$next[1:0]$9882 + attribute \src "issuer_ls180.v:161767.3-161802.6" + wire $2\wr_detect$10[0:0]$9907 + attribute \src "issuer_ls180.v:161603.3-161638.6" + wire $2\wr_detect$4[0:0]$9875 + attribute \src "issuer_ls180.v:161685.3-161720.6" + wire $2\wr_detect$7[0:0]$9891 + attribute \src "issuer_ls180.v:161521.3-161556.6" + wire $2\wr_detect[0:0] + attribute \src "issuer_ls180.v:161721.3-161766.6" + wire width 2 $3\r0__data_o$next[1:0]$9899 + attribute \src "issuer_ls180.v:161803.3-161835.6" + wire width 2 $3\reg$next[1:0]$9915 + attribute \src "issuer_ls180.v:161475.3-161520.6" + wire width 2 $3\src10__data_o$next[1:0]$9857 + attribute \src "issuer_ls180.v:161557.3-161602.6" + wire width 2 $3\src20__data_o$next[1:0]$9867 + attribute \src "issuer_ls180.v:161639.3-161684.6" + wire width 2 $3\src30__data_o$next[1:0]$9883 + attribute \src "issuer_ls180.v:161767.3-161802.6" + wire $3\wr_detect$10[0:0]$9908 + attribute \src "issuer_ls180.v:161603.3-161638.6" + wire $3\wr_detect$4[0:0]$9876 + attribute \src "issuer_ls180.v:161685.3-161720.6" + wire $3\wr_detect$7[0:0]$9892 + attribute \src "issuer_ls180.v:161521.3-161556.6" + wire $3\wr_detect[0:0] + attribute \src "issuer_ls180.v:161721.3-161766.6" + wire width 2 $4\r0__data_o$next[1:0]$9900 + attribute \src "issuer_ls180.v:161803.3-161835.6" + wire width 2 $4\reg$next[1:0]$9916 + attribute \src "issuer_ls180.v:161475.3-161520.6" + wire width 2 $4\src10__data_o$next[1:0]$9858 + attribute \src "issuer_ls180.v:161557.3-161602.6" + wire width 2 $4\src20__data_o$next[1:0]$9868 + attribute \src "issuer_ls180.v:161639.3-161684.6" + wire width 2 $4\src30__data_o$next[1:0]$9884 + attribute \src "issuer_ls180.v:161767.3-161802.6" + wire $4\wr_detect$10[0:0]$9909 + attribute \src "issuer_ls180.v:161603.3-161638.6" + wire $4\wr_detect$4[0:0]$9877 + attribute \src "issuer_ls180.v:161685.3-161720.6" + wire $4\wr_detect$7[0:0]$9893 + attribute \src "issuer_ls180.v:161521.3-161556.6" + wire $4\wr_detect[0:0] + attribute \src "issuer_ls180.v:161721.3-161766.6" + wire width 2 $5\r0__data_o$next[1:0]$9901 + attribute \src "issuer_ls180.v:161803.3-161835.6" + wire width 2 $5\reg$next[1:0]$9917 + attribute \src "issuer_ls180.v:161475.3-161520.6" + wire width 2 $5\src10__data_o$next[1:0]$9859 + attribute \src "issuer_ls180.v:161557.3-161602.6" + wire width 2 $5\src20__data_o$next[1:0]$9869 + attribute \src "issuer_ls180.v:161639.3-161684.6" + wire width 2 $5\src30__data_o$next[1:0]$9885 + attribute \src "issuer_ls180.v:161767.3-161802.6" + wire $5\wr_detect$10[0:0]$9910 + attribute \src "issuer_ls180.v:161603.3-161638.6" + wire $5\wr_detect$4[0:0]$9878 + attribute \src "issuer_ls180.v:161685.3-161720.6" + wire $5\wr_detect$7[0:0]$9894 + attribute \src "issuer_ls180.v:161521.3-161556.6" + wire $5\wr_detect[0:0] + attribute \src "issuer_ls180.v:161721.3-161766.6" + wire width 2 $6\r0__data_o$next[1:0]$9902 + attribute \src "issuer_ls180.v:161475.3-161520.6" + wire width 2 $6\src10__data_o$next[1:0]$9860 + attribute \src "issuer_ls180.v:161557.3-161602.6" + wire width 2 $6\src20__data_o$next[1:0]$9870 + attribute \src "issuer_ls180.v:161639.3-161684.6" + wire width 2 $6\src30__data_o$next[1:0]$9886 + attribute \src "issuer_ls180.v:161721.3-161766.6" + wire width 2 $7\r0__data_o$next[1:0]$9903 + attribute \src "issuer_ls180.v:161475.3-161520.6" + wire width 2 $7\src10__data_o$next[1:0]$9861 + attribute \src "issuer_ls180.v:161557.3-161602.6" + wire width 2 $7\src20__data_o$next[1:0]$9871 + attribute \src "issuer_ls180.v:161639.3-161684.6" + wire width 2 $7\src30__data_o$next[1:0]$9887 + attribute \src "issuer_ls180.v:161461.17-161461.104" + wire $not$issuer_ls180.v:161461$9844_Y + attribute \src "issuer_ls180.v:161462.17-161462.100" + wire $not$issuer_ls180.v:161462$9845_Y + attribute \src "issuer_ls180.v:161463.17-161463.103" + wire $not$issuer_ls180.v:161463$9846_Y + attribute \src "issuer_ls180.v:161464.17-161464.103" + wire $not$issuer_ls180.v:161464$9847_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + wire \$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + wire \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" + wire input 18 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" + wire input 1 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 2 input 9 \dest10__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire input 8 \dest10__wen + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 2 input 11 \dest20__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire input 10 \dest20__wen + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 2 input 13 \dest30__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire input 12 \dest30__wen + attribute \src "issuer_ls180.v:161392.7-161392.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 2 output 14 \r0__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 2 \r0__data_o$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire input 15 \r0__ren + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" + wire width 2 \reg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" + wire width 2 \reg$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 2 output 3 \src10__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 2 \src10__data_o$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire input 2 \src10__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 2 output 5 \src20__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 2 \src20__data_o$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire input 4 \src20__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 2 output 7 \src30__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 2 \src30__data_o$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire input 6 \src30__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 2 input 16 \w0__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire input 17 \w0__wen + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" + wire \wr_detect + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" + wire \wr_detect$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" + wire \wr_detect$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" + wire \wr_detect$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + cell $not $not$issuer_ls180.v:161461$9844 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_detect$10 + connect \Y $not$issuer_ls180.v:161461$9844_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + cell $not $not$issuer_ls180.v:161462$9845 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_detect + connect \Y $not$issuer_ls180.v:161462$9845_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + cell $not $not$issuer_ls180.v:161463$9846 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_detect$4 + connect \Y $not$issuer_ls180.v:161463$9846_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + cell $not $not$issuer_ls180.v:161464$9847 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_detect$7 + connect \Y $not$issuer_ls180.v:161464$9847_Y + end + attribute \src "issuer_ls180.v:161392.7-161392.20" + process $proc$issuer_ls180.v:161392$9918 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "issuer_ls180.v:161419.13-161419.30" + process $proc$issuer_ls180.v:161419$9919 + assign { } { } + assign $1\r0__data_o[1:0] 2'00 + sync always + sync init + update \r0__data_o $1\r0__data_o[1:0] + end + attribute \src "issuer_ls180.v:161425.13-161425.25" + process $proc$issuer_ls180.v:161425$9920 + assign { } { } + assign $1\reg[1:0] 2'00 + sync always + sync init + update \reg $1\reg[1:0] + end + attribute \src "issuer_ls180.v:161430.13-161430.33" + process $proc$issuer_ls180.v:161430$9921 + assign { } { } + assign $1\src10__data_o[1:0] 2'00 + sync always + sync init + update \src10__data_o $1\src10__data_o[1:0] + end + attribute \src "issuer_ls180.v:161437.13-161437.33" + process $proc$issuer_ls180.v:161437$9922 + assign { } { } + assign $1\src20__data_o[1:0] 2'00 + sync always + sync init + update \src20__data_o $1\src20__data_o[1:0] + end + attribute \src "issuer_ls180.v:161444.13-161444.33" + process $proc$issuer_ls180.v:161444$9923 + assign { } { } + assign $1\src30__data_o[1:0] 2'00 + sync always + sync init + update \src30__data_o $1\src30__data_o[1:0] + end + attribute \src "issuer_ls180.v:161465.3-161466.25" + process $proc$issuer_ls180.v:161465$9848 + assign { } { } + assign $0\reg[1:0] \reg$next + sync posedge \coresync_clk + update \reg $0\reg[1:0] + end + attribute \src "issuer_ls180.v:161467.3-161468.37" + process $proc$issuer_ls180.v:161467$9849 + assign { } { } + assign $0\r0__data_o[1:0] \r0__data_o$next + sync posedge \coresync_clk + update \r0__data_o $0\r0__data_o[1:0] + end + attribute \src "issuer_ls180.v:161469.3-161470.43" + process $proc$issuer_ls180.v:161469$9850 + assign { } { } + assign $0\src30__data_o[1:0] \src30__data_o$next + sync posedge \coresync_clk + update \src30__data_o $0\src30__data_o[1:0] + end + attribute \src "issuer_ls180.v:161471.3-161472.43" + process $proc$issuer_ls180.v:161471$9851 + assign { } { } + assign $0\src20__data_o[1:0] \src20__data_o$next + sync posedge \coresync_clk + update \src20__data_o $0\src20__data_o[1:0] + end + attribute \src "issuer_ls180.v:161473.3-161474.43" + process $proc$issuer_ls180.v:161473$9852 + assign { } { } + assign $0\src10__data_o[1:0] \src10__data_o$next + sync posedge \coresync_clk + update \src10__data_o $0\src10__data_o[1:0] + end + attribute \src "issuer_ls180.v:161475.3-161520.6" + process $proc$issuer_ls180.v:161475$9853 + assign { } { } + assign { } { } + assign { } { } + assign $0\src10__data_o$next[1:0]$9854 $7\src10__data_o$next[1:0]$9861 + attribute \src "issuer_ls180.v:161476.5-161476.29" + switch \initial + attribute \src "issuer_ls180.v:161476.9-161476.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \src10__ren + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\src10__data_o$next[1:0]$9855 $6\src10__data_o$next[1:0]$9860 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest10__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\src10__data_o$next[1:0]$9856 \dest10__data_i + case + assign $2\src10__data_o$next[1:0]$9856 2'00 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest20__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\src10__data_o$next[1:0]$9857 \dest20__data_i + case + assign $3\src10__data_o$next[1:0]$9857 $2\src10__data_o$next[1:0]$9856 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest30__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\src10__data_o$next[1:0]$9858 \dest30__data_i + case + assign $4\src10__data_o$next[1:0]$9858 $3\src10__data_o$next[1:0]$9857 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w0__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\src10__data_o$next[1:0]$9859 \w0__data_i + case + assign $5\src10__data_o$next[1:0]$9859 $4\src10__data_o$next[1:0]$9858 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + switch \$1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $6\src10__data_o$next[1:0]$9860 \reg + case + assign $6\src10__data_o$next[1:0]$9860 $5\src10__data_o$next[1:0]$9859 + end + case + assign $1\src10__data_o$next[1:0]$9855 2'00 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $7\src10__data_o$next[1:0]$9861 2'00 + case + assign $7\src10__data_o$next[1:0]$9861 $1\src10__data_o$next[1:0]$9855 + end + sync always + update \src10__data_o$next $0\src10__data_o$next[1:0]$9854 + end + attribute \src "issuer_ls180.v:161521.3-161556.6" + process $proc$issuer_ls180.v:161521$9862 + assign { } { } + assign { } { } + assign $0\wr_detect[0:0] $1\wr_detect[0:0] + attribute \src "issuer_ls180.v:161522.5-161522.29" + switch \initial + attribute \src "issuer_ls180.v:161522.9-161522.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \src10__ren + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\wr_detect[0:0] $5\wr_detect[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest10__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\wr_detect[0:0] 1'1 + case + assign $2\wr_detect[0:0] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest20__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\wr_detect[0:0] 1'1 + case + assign $3\wr_detect[0:0] $2\wr_detect[0:0] + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest30__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\wr_detect[0:0] 1'1 + case + assign $4\wr_detect[0:0] $3\wr_detect[0:0] + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w0__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\wr_detect[0:0] 1'1 + case + assign $5\wr_detect[0:0] $4\wr_detect[0:0] + end + case + assign $1\wr_detect[0:0] 1'0 + end + sync always + update \wr_detect $0\wr_detect[0:0] + end + attribute \src "issuer_ls180.v:161557.3-161602.6" + process $proc$issuer_ls180.v:161557$9863 + assign { } { } + assign { } { } + assign { } { } + assign $0\src20__data_o$next[1:0]$9864 $7\src20__data_o$next[1:0]$9871 + attribute \src "issuer_ls180.v:161558.5-161558.29" + switch \initial + attribute \src "issuer_ls180.v:161558.9-161558.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \src20__ren + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\src20__data_o$next[1:0]$9865 $6\src20__data_o$next[1:0]$9870 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest10__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\src20__data_o$next[1:0]$9866 \dest10__data_i + case + assign $2\src20__data_o$next[1:0]$9866 2'00 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest20__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\src20__data_o$next[1:0]$9867 \dest20__data_i + case + assign $3\src20__data_o$next[1:0]$9867 $2\src20__data_o$next[1:0]$9866 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest30__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\src20__data_o$next[1:0]$9868 \dest30__data_i + case + assign $4\src20__data_o$next[1:0]$9868 $3\src20__data_o$next[1:0]$9867 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w0__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\src20__data_o$next[1:0]$9869 \w0__data_i + case + assign $5\src20__data_o$next[1:0]$9869 $4\src20__data_o$next[1:0]$9868 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + switch \$3 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $6\src20__data_o$next[1:0]$9870 \reg + case + assign $6\src20__data_o$next[1:0]$9870 $5\src20__data_o$next[1:0]$9869 + end + case + assign $1\src20__data_o$next[1:0]$9865 2'00 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $7\src20__data_o$next[1:0]$9871 2'00 + case + assign $7\src20__data_o$next[1:0]$9871 $1\src20__data_o$next[1:0]$9865 + end + sync always + update \src20__data_o$next $0\src20__data_o$next[1:0]$9864 + end + attribute \src "issuer_ls180.v:161603.3-161638.6" + process $proc$issuer_ls180.v:161603$9872 + assign { } { } + assign { } { } + assign $0\wr_detect$4[0:0]$9873 $1\wr_detect$4[0:0]$9874 + attribute \src "issuer_ls180.v:161604.5-161604.29" + switch \initial + attribute \src "issuer_ls180.v:161604.9-161604.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \src20__ren + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\wr_detect$4[0:0]$9874 $5\wr_detect$4[0:0]$9878 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest10__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\wr_detect$4[0:0]$9875 1'1 + case + assign $2\wr_detect$4[0:0]$9875 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest20__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\wr_detect$4[0:0]$9876 1'1 + case + assign $3\wr_detect$4[0:0]$9876 $2\wr_detect$4[0:0]$9875 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest30__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\wr_detect$4[0:0]$9877 1'1 + case + assign $4\wr_detect$4[0:0]$9877 $3\wr_detect$4[0:0]$9876 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w0__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\wr_detect$4[0:0]$9878 1'1 + case + assign $5\wr_detect$4[0:0]$9878 $4\wr_detect$4[0:0]$9877 + end + case + assign $1\wr_detect$4[0:0]$9874 1'0 + end + sync always + update \wr_detect$4 $0\wr_detect$4[0:0]$9873 + end + attribute \src "issuer_ls180.v:161639.3-161684.6" + process $proc$issuer_ls180.v:161639$9879 + assign { } { } + assign { } { } + assign { } { } + assign $0\src30__data_o$next[1:0]$9880 $7\src30__data_o$next[1:0]$9887 + attribute \src "issuer_ls180.v:161640.5-161640.29" + switch \initial + attribute \src "issuer_ls180.v:161640.9-161640.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \src30__ren + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\src30__data_o$next[1:0]$9881 $6\src30__data_o$next[1:0]$9886 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest10__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\src30__data_o$next[1:0]$9882 \dest10__data_i + case + assign $2\src30__data_o$next[1:0]$9882 2'00 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest20__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\src30__data_o$next[1:0]$9883 \dest20__data_i + case + assign $3\src30__data_o$next[1:0]$9883 $2\src30__data_o$next[1:0]$9882 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest30__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\src30__data_o$next[1:0]$9884 \dest30__data_i + case + assign $4\src30__data_o$next[1:0]$9884 $3\src30__data_o$next[1:0]$9883 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w0__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\src30__data_o$next[1:0]$9885 \w0__data_i + case + assign $5\src30__data_o$next[1:0]$9885 $4\src30__data_o$next[1:0]$9884 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + switch \$6 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $6\src30__data_o$next[1:0]$9886 \reg + case + assign $6\src30__data_o$next[1:0]$9886 $5\src30__data_o$next[1:0]$9885 + end + case + assign $1\src30__data_o$next[1:0]$9881 2'00 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $7\src30__data_o$next[1:0]$9887 2'00 + case + assign $7\src30__data_o$next[1:0]$9887 $1\src30__data_o$next[1:0]$9881 + end + sync always + update \src30__data_o$next $0\src30__data_o$next[1:0]$9880 + end + attribute \src "issuer_ls180.v:161685.3-161720.6" + process $proc$issuer_ls180.v:161685$9888 + assign { } { } + assign { } { } + assign $0\wr_detect$7[0:0]$9889 $1\wr_detect$7[0:0]$9890 + attribute \src "issuer_ls180.v:161686.5-161686.29" + switch \initial + attribute \src "issuer_ls180.v:161686.9-161686.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \src30__ren + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\wr_detect$7[0:0]$9890 $5\wr_detect$7[0:0]$9894 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest10__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\wr_detect$7[0:0]$9891 1'1 + case + assign $2\wr_detect$7[0:0]$9891 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest20__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\wr_detect$7[0:0]$9892 1'1 + case + assign $3\wr_detect$7[0:0]$9892 $2\wr_detect$7[0:0]$9891 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest30__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\wr_detect$7[0:0]$9893 1'1 + case + assign $4\wr_detect$7[0:0]$9893 $3\wr_detect$7[0:0]$9892 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w0__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\wr_detect$7[0:0]$9894 1'1 + case + assign $5\wr_detect$7[0:0]$9894 $4\wr_detect$7[0:0]$9893 + end + case + assign $1\wr_detect$7[0:0]$9890 1'0 + end + sync always + update \wr_detect$7 $0\wr_detect$7[0:0]$9889 + end + attribute \src "issuer_ls180.v:161721.3-161766.6" + process $proc$issuer_ls180.v:161721$9895 + assign { } { } + assign { } { } + assign { } { } + assign $0\r0__data_o$next[1:0]$9896 $7\r0__data_o$next[1:0]$9903 + attribute \src "issuer_ls180.v:161722.5-161722.29" + switch \initial + attribute \src "issuer_ls180.v:161722.9-161722.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \r0__ren + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\r0__data_o$next[1:0]$9897 $6\r0__data_o$next[1:0]$9902 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest10__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\r0__data_o$next[1:0]$9898 \dest10__data_i + case + assign $2\r0__data_o$next[1:0]$9898 2'00 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest20__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\r0__data_o$next[1:0]$9899 \dest20__data_i + case + assign $3\r0__data_o$next[1:0]$9899 $2\r0__data_o$next[1:0]$9898 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest30__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\r0__data_o$next[1:0]$9900 \dest30__data_i + case + assign $4\r0__data_o$next[1:0]$9900 $3\r0__data_o$next[1:0]$9899 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w0__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\r0__data_o$next[1:0]$9901 \w0__data_i + case + assign $5\r0__data_o$next[1:0]$9901 $4\r0__data_o$next[1:0]$9900 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + switch \$9 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $6\r0__data_o$next[1:0]$9902 \reg + case + assign $6\r0__data_o$next[1:0]$9902 $5\r0__data_o$next[1:0]$9901 + end + case + assign $1\r0__data_o$next[1:0]$9897 2'00 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $7\r0__data_o$next[1:0]$9903 2'00 + case + assign $7\r0__data_o$next[1:0]$9903 $1\r0__data_o$next[1:0]$9897 + end + sync always + update \r0__data_o$next $0\r0__data_o$next[1:0]$9896 + end + attribute \src "issuer_ls180.v:161767.3-161802.6" + process $proc$issuer_ls180.v:161767$9904 + assign { } { } + assign { } { } + assign $0\wr_detect$10[0:0]$9905 $1\wr_detect$10[0:0]$9906 + attribute \src "issuer_ls180.v:161768.5-161768.29" + switch \initial + attribute \src "issuer_ls180.v:161768.9-161768.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \r0__ren + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\wr_detect$10[0:0]$9906 $5\wr_detect$10[0:0]$9910 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest10__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\wr_detect$10[0:0]$9907 1'1 + case + assign $2\wr_detect$10[0:0]$9907 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest20__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\wr_detect$10[0:0]$9908 1'1 + case + assign $3\wr_detect$10[0:0]$9908 $2\wr_detect$10[0:0]$9907 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest30__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\wr_detect$10[0:0]$9909 1'1 + case + assign $4\wr_detect$10[0:0]$9909 $3\wr_detect$10[0:0]$9908 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w0__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\wr_detect$10[0:0]$9910 1'1 + case + assign $5\wr_detect$10[0:0]$9910 $4\wr_detect$10[0:0]$9909 + end + case + assign $1\wr_detect$10[0:0]$9906 1'0 + end + sync always + update \wr_detect$10 $0\wr_detect$10[0:0]$9905 + end + attribute \src "issuer_ls180.v:161803.3-161835.6" + process $proc$issuer_ls180.v:161803$9911 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\reg$next[1:0]$9912 $5\reg$next[1:0]$9917 + attribute \src "issuer_ls180.v:161804.5-161804.29" + switch \initial + attribute \src "issuer_ls180.v:161804.9-161804.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" + switch \dest10__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\reg$next[1:0]$9913 \dest10__data_i + case + assign $1\reg$next[1:0]$9913 \reg + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" + switch \dest20__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\reg$next[1:0]$9914 \dest20__data_i + case + assign $2\reg$next[1:0]$9914 $1\reg$next[1:0]$9913 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" + switch \dest30__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\reg$next[1:0]$9915 \dest30__data_i + case + assign $3\reg$next[1:0]$9915 $2\reg$next[1:0]$9914 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" + switch \w0__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\reg$next[1:0]$9916 \w0__data_i + case + assign $4\reg$next[1:0]$9916 $3\reg$next[1:0]$9915 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\reg$next[1:0]$9917 2'00 + case + assign $5\reg$next[1:0]$9917 $4\reg$next[1:0]$9916 + end + sync always + update \reg$next $0\reg$next[1:0]$9912 + end + connect \$9 $not$issuer_ls180.v:161461$9844_Y + connect \$1 $not$issuer_ls180.v:161462$9845_Y + connect \$3 $not$issuer_ls180.v:161463$9846_Y + connect \$6 $not$issuer_ls180.v:161464$9847_Y +end +attribute \src "issuer_ls180.v:161840.1-162059.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.state.reg_0" +attribute \generator "nMigen" +module \reg_0$132 + attribute \src "issuer_ls180.v:161892.3-161931.6" + wire width 64 $0\cia0__data_o$next[63:0]$9930 + attribute \src "issuer_ls180.v:161890.3-161891.41" + wire width 64 $0\cia0__data_o[63:0] + attribute \src "issuer_ls180.v:161841.7-161841.20" + wire $0\initial[0:0] + attribute \src "issuer_ls180.v:161962.3-162001.6" + wire width 64 $0\msr0__data_o$next[63:0]$9939 + attribute \src "issuer_ls180.v:161888.3-161889.41" + wire width 64 $0\msr0__data_o[63:0] + attribute \src "issuer_ls180.v:162032.3-162058.6" + wire width 64 $0\reg$next[63:0]$9953 + attribute \src "issuer_ls180.v:161886.3-161887.25" + wire width 64 $0\reg[63:0] + attribute \src "issuer_ls180.v:162002.3-162031.6" + wire $0\wr_detect$4[0:0]$9947 + attribute \src "issuer_ls180.v:161932.3-161961.6" + wire $0\wr_detect[0:0] + attribute \src "issuer_ls180.v:161892.3-161931.6" + wire width 64 $1\cia0__data_o$next[63:0]$9931 + attribute \src "issuer_ls180.v:161848.14-161848.49" + wire width 64 $1\cia0__data_o[63:0] + attribute \src "issuer_ls180.v:161962.3-162001.6" + wire width 64 $1\msr0__data_o$next[63:0]$9940 + attribute \src "issuer_ls180.v:161865.14-161865.49" + wire width 64 $1\msr0__data_o[63:0] + attribute \src "issuer_ls180.v:162032.3-162058.6" + wire width 64 $1\reg$next[63:0]$9954 + attribute \src "issuer_ls180.v:161877.14-161877.42" + wire width 64 $1\reg[63:0] + attribute \src "issuer_ls180.v:162002.3-162031.6" + wire $1\wr_detect$4[0:0]$9948 + attribute \src "issuer_ls180.v:161932.3-161961.6" + wire $1\wr_detect[0:0] + attribute \src "issuer_ls180.v:161892.3-161931.6" + wire width 64 $2\cia0__data_o$next[63:0]$9932 + attribute \src "issuer_ls180.v:161962.3-162001.6" + wire width 64 $2\msr0__data_o$next[63:0]$9941 + attribute \src "issuer_ls180.v:162032.3-162058.6" + wire width 64 $2\reg$next[63:0]$9955 + attribute \src "issuer_ls180.v:162002.3-162031.6" + wire $2\wr_detect$4[0:0]$9949 + attribute \src "issuer_ls180.v:161932.3-161961.6" + wire $2\wr_detect[0:0] + attribute \src "issuer_ls180.v:161892.3-161931.6" + wire width 64 $3\cia0__data_o$next[63:0]$9933 + attribute \src "issuer_ls180.v:161962.3-162001.6" + wire width 64 $3\msr0__data_o$next[63:0]$9942 + attribute \src "issuer_ls180.v:162032.3-162058.6" + wire width 64 $3\reg$next[63:0]$9956 + attribute \src "issuer_ls180.v:162002.3-162031.6" + wire $3\wr_detect$4[0:0]$9950 + attribute \src "issuer_ls180.v:161932.3-161961.6" + wire $3\wr_detect[0:0] + attribute \src "issuer_ls180.v:161892.3-161931.6" + wire width 64 $4\cia0__data_o$next[63:0]$9934 + attribute \src "issuer_ls180.v:161962.3-162001.6" + wire width 64 $4\msr0__data_o$next[63:0]$9943 + attribute \src "issuer_ls180.v:162032.3-162058.6" + wire width 64 $4\reg$next[63:0]$9957 + attribute \src "issuer_ls180.v:162002.3-162031.6" + wire $4\wr_detect$4[0:0]$9951 + attribute \src "issuer_ls180.v:161932.3-161961.6" + wire $4\wr_detect[0:0] + attribute \src "issuer_ls180.v:161892.3-161931.6" + wire width 64 $5\cia0__data_o$next[63:0]$9935 + attribute \src "issuer_ls180.v:161962.3-162001.6" + wire width 64 $5\msr0__data_o$next[63:0]$9944 + attribute \src "issuer_ls180.v:161892.3-161931.6" + wire width 64 $6\cia0__data_o$next[63:0]$9936 + attribute \src "issuer_ls180.v:161962.3-162001.6" + wire width 64 $6\msr0__data_o$next[63:0]$9945 + attribute \src "issuer_ls180.v:161884.17-161884.100" + wire $not$issuer_ls180.v:161884$9924_Y + attribute \src "issuer_ls180.v:161885.17-161885.103" + wire $not$issuer_ls180.v:161885$9925_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 64 output 3 \cia0__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 64 \cia0__data_o$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire input 2 \cia0__ren + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" + wire input 12 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" + wire input 1 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 64 input 11 \d_wr10__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire input 10 \d_wr10__wen + attribute \src "issuer_ls180.v:161841.7-161841.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 64 input 9 \msr0__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 64 output 5 \msr0__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 64 \msr0__data_o$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire input 4 \msr0__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire input 8 \msr0__wen + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 64 input 7 \nia0__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire input 6 \nia0__wen + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" + wire width 64 \reg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" + wire width 64 \reg$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" + wire \wr_detect + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" + wire \wr_detect$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + cell $not $not$issuer_ls180.v:161884$9924 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_detect + connect \Y $not$issuer_ls180.v:161884$9924_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + cell $not $not$issuer_ls180.v:161885$9925 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_detect$4 + connect \Y $not$issuer_ls180.v:161885$9925_Y + end + attribute \src "issuer_ls180.v:161841.7-161841.20" + process $proc$issuer_ls180.v:161841$9958 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "issuer_ls180.v:161848.14-161848.49" + process $proc$issuer_ls180.v:161848$9959 + assign { } { } + assign $1\cia0__data_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \cia0__data_o $1\cia0__data_o[63:0] + end + attribute \src "issuer_ls180.v:161865.14-161865.49" + process $proc$issuer_ls180.v:161865$9960 + assign { } { } + assign $1\msr0__data_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \msr0__data_o $1\msr0__data_o[63:0] + end + attribute \src "issuer_ls180.v:161877.14-161877.42" + process $proc$issuer_ls180.v:161877$9961 + assign { } { } + assign $1\reg[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \reg $1\reg[63:0] + end + attribute \src "issuer_ls180.v:161886.3-161887.25" + process $proc$issuer_ls180.v:161886$9926 + assign { } { } + assign $0\reg[63:0] \reg$next + sync posedge \coresync_clk + update \reg $0\reg[63:0] + end + attribute \src "issuer_ls180.v:161888.3-161889.41" + process $proc$issuer_ls180.v:161888$9927 + assign { } { } + assign $0\msr0__data_o[63:0] \msr0__data_o$next + sync posedge \coresync_clk + update \msr0__data_o $0\msr0__data_o[63:0] + end + attribute \src "issuer_ls180.v:161890.3-161891.41" + process $proc$issuer_ls180.v:161890$9928 + assign { } { } + assign $0\cia0__data_o[63:0] \cia0__data_o$next + sync posedge \coresync_clk + update \cia0__data_o $0\cia0__data_o[63:0] + end + attribute \src "issuer_ls180.v:161892.3-161931.6" + process $proc$issuer_ls180.v:161892$9929 + assign { } { } + assign { } { } + assign { } { } + assign $0\cia0__data_o$next[63:0]$9930 $6\cia0__data_o$next[63:0]$9936 + attribute \src "issuer_ls180.v:161893.5-161893.29" + switch \initial + attribute \src "issuer_ls180.v:161893.9-161893.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \cia0__ren + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\cia0__data_o$next[63:0]$9931 $5\cia0__data_o$next[63:0]$9935 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \nia0__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\cia0__data_o$next[63:0]$9932 \nia0__data_i + case + assign $2\cia0__data_o$next[63:0]$9932 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \msr0__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\cia0__data_o$next[63:0]$9933 \msr0__data_i + case + assign $3\cia0__data_o$next[63:0]$9933 $2\cia0__data_o$next[63:0]$9932 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \d_wr10__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\cia0__data_o$next[63:0]$9934 \d_wr10__data_i + case + assign $4\cia0__data_o$next[63:0]$9934 $3\cia0__data_o$next[63:0]$9933 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + switch \$1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\cia0__data_o$next[63:0]$9935 \reg + case + assign $5\cia0__data_o$next[63:0]$9935 $4\cia0__data_o$next[63:0]$9934 + end + case + assign $1\cia0__data_o$next[63:0]$9931 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $6\cia0__data_o$next[63:0]$9936 64'0000000000000000000000000000000000000000000000000000000000000000 + case + assign $6\cia0__data_o$next[63:0]$9936 $1\cia0__data_o$next[63:0]$9931 + end + sync always + update \cia0__data_o$next $0\cia0__data_o$next[63:0]$9930 + end + attribute \src "issuer_ls180.v:161932.3-161961.6" + process $proc$issuer_ls180.v:161932$9937 + assign { } { } + assign { } { } + assign $0\wr_detect[0:0] $1\wr_detect[0:0] + attribute \src "issuer_ls180.v:161933.5-161933.29" + switch \initial + attribute \src "issuer_ls180.v:161933.9-161933.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \cia0__ren + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\wr_detect[0:0] $4\wr_detect[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \nia0__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\wr_detect[0:0] 1'1 + case + assign $2\wr_detect[0:0] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \msr0__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\wr_detect[0:0] 1'1 + case + assign $3\wr_detect[0:0] $2\wr_detect[0:0] + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \d_wr10__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\wr_detect[0:0] 1'1 + case + assign $4\wr_detect[0:0] $3\wr_detect[0:0] + end + case + assign $1\wr_detect[0:0] 1'0 + end + sync always + update \wr_detect $0\wr_detect[0:0] + end + attribute \src "issuer_ls180.v:161962.3-162001.6" + process $proc$issuer_ls180.v:161962$9938 + assign { } { } + assign { } { } + assign { } { } + assign $0\msr0__data_o$next[63:0]$9939 $6\msr0__data_o$next[63:0]$9945 + attribute \src "issuer_ls180.v:161963.5-161963.29" + switch \initial + attribute \src "issuer_ls180.v:161963.9-161963.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \msr0__ren + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\msr0__data_o$next[63:0]$9940 $5\msr0__data_o$next[63:0]$9944 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \nia0__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\msr0__data_o$next[63:0]$9941 \nia0__data_i + case + assign $2\msr0__data_o$next[63:0]$9941 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \msr0__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\msr0__data_o$next[63:0]$9942 \msr0__data_i + case + assign $3\msr0__data_o$next[63:0]$9942 $2\msr0__data_o$next[63:0]$9941 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \d_wr10__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\msr0__data_o$next[63:0]$9943 \d_wr10__data_i + case + assign $4\msr0__data_o$next[63:0]$9943 $3\msr0__data_o$next[63:0]$9942 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + switch \$3 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\msr0__data_o$next[63:0]$9944 \reg + case + assign $5\msr0__data_o$next[63:0]$9944 $4\msr0__data_o$next[63:0]$9943 + end + case + assign $1\msr0__data_o$next[63:0]$9940 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $6\msr0__data_o$next[63:0]$9945 64'0000000000000000000000000000000000000000000000000000000000000000 + case + assign $6\msr0__data_o$next[63:0]$9945 $1\msr0__data_o$next[63:0]$9940 + end + sync always + update \msr0__data_o$next $0\msr0__data_o$next[63:0]$9939 + end + attribute \src "issuer_ls180.v:162002.3-162031.6" + process $proc$issuer_ls180.v:162002$9946 + assign { } { } + assign { } { } + assign $0\wr_detect$4[0:0]$9947 $1\wr_detect$4[0:0]$9948 + attribute \src "issuer_ls180.v:162003.5-162003.29" + switch \initial + attribute \src "issuer_ls180.v:162003.9-162003.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \msr0__ren + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\wr_detect$4[0:0]$9948 $4\wr_detect$4[0:0]$9951 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \nia0__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\wr_detect$4[0:0]$9949 1'1 + case + assign $2\wr_detect$4[0:0]$9949 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \msr0__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\wr_detect$4[0:0]$9950 1'1 + case + assign $3\wr_detect$4[0:0]$9950 $2\wr_detect$4[0:0]$9949 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \d_wr10__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\wr_detect$4[0:0]$9951 1'1 + case + assign $4\wr_detect$4[0:0]$9951 $3\wr_detect$4[0:0]$9950 + end + case + assign $1\wr_detect$4[0:0]$9948 1'0 + end + sync always + update \wr_detect$4 $0\wr_detect$4[0:0]$9947 + end + attribute \src "issuer_ls180.v:162032.3-162058.6" + process $proc$issuer_ls180.v:162032$9952 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\reg$next[63:0]$9953 $4\reg$next[63:0]$9957 + attribute \src "issuer_ls180.v:162033.5-162033.29" + switch \initial + attribute \src "issuer_ls180.v:162033.9-162033.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" + switch \nia0__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\reg$next[63:0]$9954 \nia0__data_i + case + assign $1\reg$next[63:0]$9954 \reg + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" + switch \msr0__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\reg$next[63:0]$9955 \msr0__data_i + case + assign $2\reg$next[63:0]$9955 $1\reg$next[63:0]$9954 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" + switch \d_wr10__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\reg$next[63:0]$9956 \d_wr10__data_i + case + assign $3\reg$next[63:0]$9956 $2\reg$next[63:0]$9955 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\reg$next[63:0]$9957 64'0000000000000000000000000000000000000000000000000000000000000000 + case + assign $4\reg$next[63:0]$9957 $3\reg$next[63:0]$9956 + end + sync always + update \reg$next $0\reg$next[63:0]$9953 + end + connect \$1 $not$issuer_ls180.v:161884$9924_Y + connect \$3 $not$issuer_ls180.v:161885$9925_Y +end +attribute \src "issuer_ls180.v:162063.1-162534.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.cr.reg_1" +attribute \generator "nMigen" +module \reg_1 + attribute \src "issuer_ls180.v:162064.7-162064.20" + wire $0\initial[0:0] + attribute \src "issuer_ls180.v:162394.3-162433.6" + wire width 4 $0\r1__data_o$next[3:0]$10017 + attribute \src "issuer_ls180.v:162149.3-162150.37" + wire width 4 $0\r1__data_o[3:0] + attribute \src "issuer_ls180.v:162464.3-162503.6" + wire width 4 $0\r21__data_o$next[3:0]$10031 + attribute \src "issuer_ls180.v:162147.3-162148.39" + wire width 4 $0\r21__data_o[3:0] + attribute \src "issuer_ls180.v:162227.3-162253.6" + wire width 4 $0\reg$next[3:0]$9983 + attribute \src "issuer_ls180.v:162145.3-162146.25" + wire width 4 $0\reg[3:0] + attribute \src "issuer_ls180.v:162157.3-162196.6" + wire width 4 $0\src11__data_o$next[3:0]$9974 + attribute \src "issuer_ls180.v:162155.3-162156.43" + wire width 4 $0\src11__data_o[3:0] + attribute \src "issuer_ls180.v:162254.3-162293.6" + wire width 4 $0\src21__data_o$next[3:0]$9989 + attribute \src "issuer_ls180.v:162153.3-162154.43" + wire width 4 $0\src21__data_o[3:0] + attribute \src "issuer_ls180.v:162324.3-162363.6" + wire width 4 $0\src31__data_o$next[3:0]$10003 + attribute \src "issuer_ls180.v:162151.3-162152.43" + wire width 4 $0\src31__data_o[3:0] + attribute \src "issuer_ls180.v:162434.3-162463.6" + wire $0\wr_detect$10[0:0]$10025 + attribute \src "issuer_ls180.v:162504.3-162533.6" + wire $0\wr_detect$13[0:0]$10039 + attribute \src "issuer_ls180.v:162294.3-162323.6" + wire $0\wr_detect$4[0:0]$9997 + attribute \src "issuer_ls180.v:162364.3-162393.6" + wire $0\wr_detect$7[0:0]$10011 + attribute \src "issuer_ls180.v:162197.3-162226.6" + wire $0\wr_detect[0:0] + attribute \src "issuer_ls180.v:162394.3-162433.6" + wire width 4 $1\r1__data_o$next[3:0]$10018 + attribute \src "issuer_ls180.v:162089.13-162089.30" + wire width 4 $1\r1__data_o[3:0] + attribute \src "issuer_ls180.v:162464.3-162503.6" + wire width 4 $1\r21__data_o$next[3:0]$10032 + attribute \src "issuer_ls180.v:162096.13-162096.31" + wire width 4 $1\r21__data_o[3:0] + attribute \src "issuer_ls180.v:162227.3-162253.6" + wire width 4 $1\reg$next[3:0]$9984 + attribute \src "issuer_ls180.v:162102.13-162102.25" + wire width 4 $1\reg[3:0] + attribute \src "issuer_ls180.v:162157.3-162196.6" + wire width 4 $1\src11__data_o$next[3:0]$9975 + attribute \src "issuer_ls180.v:162107.13-162107.33" + wire width 4 $1\src11__data_o[3:0] + attribute \src "issuer_ls180.v:162254.3-162293.6" + wire width 4 $1\src21__data_o$next[3:0]$9990 + attribute \src "issuer_ls180.v:162114.13-162114.33" + wire width 4 $1\src21__data_o[3:0] + attribute \src "issuer_ls180.v:162324.3-162363.6" + wire width 4 $1\src31__data_o$next[3:0]$10004 + attribute \src "issuer_ls180.v:162121.13-162121.33" + wire width 4 $1\src31__data_o[3:0] + attribute \src "issuer_ls180.v:162434.3-162463.6" + wire $1\wr_detect$10[0:0]$10026 + attribute \src "issuer_ls180.v:162504.3-162533.6" + wire $1\wr_detect$13[0:0]$10040 + attribute \src "issuer_ls180.v:162294.3-162323.6" + wire $1\wr_detect$4[0:0]$9998 + attribute \src "issuer_ls180.v:162364.3-162393.6" + wire $1\wr_detect$7[0:0]$10012 + attribute \src "issuer_ls180.v:162197.3-162226.6" + wire $1\wr_detect[0:0] + attribute \src "issuer_ls180.v:162394.3-162433.6" + wire width 4 $2\r1__data_o$next[3:0]$10019 + attribute \src "issuer_ls180.v:162464.3-162503.6" + wire width 4 $2\r21__data_o$next[3:0]$10033 + attribute \src "issuer_ls180.v:162227.3-162253.6" + wire width 4 $2\reg$next[3:0]$9985 + attribute \src "issuer_ls180.v:162157.3-162196.6" + wire width 4 $2\src11__data_o$next[3:0]$9976 + attribute \src "issuer_ls180.v:162254.3-162293.6" + wire width 4 $2\src21__data_o$next[3:0]$9991 + attribute \src "issuer_ls180.v:162324.3-162363.6" + wire width 4 $2\src31__data_o$next[3:0]$10005 + attribute \src "issuer_ls180.v:162434.3-162463.6" + wire $2\wr_detect$10[0:0]$10027 + attribute \src "issuer_ls180.v:162504.3-162533.6" + wire $2\wr_detect$13[0:0]$10041 + attribute \src "issuer_ls180.v:162294.3-162323.6" + wire $2\wr_detect$4[0:0]$9999 + attribute \src "issuer_ls180.v:162364.3-162393.6" + wire $2\wr_detect$7[0:0]$10013 + attribute \src "issuer_ls180.v:162197.3-162226.6" + wire $2\wr_detect[0:0] + attribute \src "issuer_ls180.v:162394.3-162433.6" + wire width 4 $3\r1__data_o$next[3:0]$10020 + attribute \src "issuer_ls180.v:162464.3-162503.6" + wire width 4 $3\r21__data_o$next[3:0]$10034 + attribute \src "issuer_ls180.v:162227.3-162253.6" + wire width 4 $3\reg$next[3:0]$9986 + attribute \src "issuer_ls180.v:162157.3-162196.6" + wire width 4 $3\src11__data_o$next[3:0]$9977 + attribute \src "issuer_ls180.v:162254.3-162293.6" + wire width 4 $3\src21__data_o$next[3:0]$9992 + attribute \src "issuer_ls180.v:162324.3-162363.6" + wire width 4 $3\src31__data_o$next[3:0]$10006 + attribute \src "issuer_ls180.v:162434.3-162463.6" + wire $3\wr_detect$10[0:0]$10028 + attribute \src "issuer_ls180.v:162504.3-162533.6" + wire $3\wr_detect$13[0:0]$10042 + attribute \src "issuer_ls180.v:162294.3-162323.6" + wire $3\wr_detect$4[0:0]$10000 + attribute \src "issuer_ls180.v:162364.3-162393.6" + wire $3\wr_detect$7[0:0]$10014 + attribute \src "issuer_ls180.v:162197.3-162226.6" + wire $3\wr_detect[0:0] + attribute \src "issuer_ls180.v:162394.3-162433.6" + wire width 4 $4\r1__data_o$next[3:0]$10021 + attribute \src "issuer_ls180.v:162464.3-162503.6" + wire width 4 $4\r21__data_o$next[3:0]$10035 + attribute \src "issuer_ls180.v:162227.3-162253.6" + wire width 4 $4\reg$next[3:0]$9987 + attribute \src "issuer_ls180.v:162157.3-162196.6" + wire width 4 $4\src11__data_o$next[3:0]$9978 + attribute \src "issuer_ls180.v:162254.3-162293.6" + wire width 4 $4\src21__data_o$next[3:0]$9993 + attribute \src "issuer_ls180.v:162324.3-162363.6" + wire width 4 $4\src31__data_o$next[3:0]$10007 + attribute \src "issuer_ls180.v:162434.3-162463.6" + wire $4\wr_detect$10[0:0]$10029 + attribute \src "issuer_ls180.v:162504.3-162533.6" + wire $4\wr_detect$13[0:0]$10043 + attribute \src "issuer_ls180.v:162294.3-162323.6" + wire $4\wr_detect$4[0:0]$10001 + attribute \src "issuer_ls180.v:162364.3-162393.6" + wire $4\wr_detect$7[0:0]$10015 + attribute \src "issuer_ls180.v:162197.3-162226.6" + wire $4\wr_detect[0:0] + attribute \src "issuer_ls180.v:162394.3-162433.6" + wire width 4 $5\r1__data_o$next[3:0]$10022 + attribute \src "issuer_ls180.v:162464.3-162503.6" + wire width 4 $5\r21__data_o$next[3:0]$10036 + attribute \src "issuer_ls180.v:162157.3-162196.6" + wire width 4 $5\src11__data_o$next[3:0]$9979 + attribute \src "issuer_ls180.v:162254.3-162293.6" + wire width 4 $5\src21__data_o$next[3:0]$9994 + attribute \src "issuer_ls180.v:162324.3-162363.6" + wire width 4 $5\src31__data_o$next[3:0]$10008 + attribute \src "issuer_ls180.v:162394.3-162433.6" + wire width 4 $6\r1__data_o$next[3:0]$10023 + attribute \src "issuer_ls180.v:162464.3-162503.6" + wire width 4 $6\r21__data_o$next[3:0]$10037 + attribute \src "issuer_ls180.v:162157.3-162196.6" + wire width 4 $6\src11__data_o$next[3:0]$9980 + attribute \src "issuer_ls180.v:162254.3-162293.6" + wire width 4 $6\src21__data_o$next[3:0]$9995 + attribute \src "issuer_ls180.v:162324.3-162363.6" + wire width 4 $6\src31__data_o$next[3:0]$10009 + attribute \src "issuer_ls180.v:162140.17-162140.104" + wire $not$issuer_ls180.v:162140$9962_Y + attribute \src "issuer_ls180.v:162141.18-162141.105" + wire $not$issuer_ls180.v:162141$9963_Y + attribute \src "issuer_ls180.v:162142.17-162142.100" + wire $not$issuer_ls180.v:162142$9964_Y + attribute \src "issuer_ls180.v:162143.17-162143.103" + wire $not$issuer_ls180.v:162143$9965_Y + attribute \src "issuer_ls180.v:162144.17-162144.103" + wire $not$issuer_ls180.v:162144$9966_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + wire \$12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + wire \$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + wire \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" + wire input 18 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" + wire input 1 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 input 9 \dest11__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire input 8 \dest11__wen + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 input 11 \dest21__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire input 10 \dest21__wen + attribute \src "issuer_ls180.v:162064.7-162064.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 output 12 \r1__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 \r1__data_o$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire input 13 \r1__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 output 14 \r21__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 \r21__data_o$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire input 15 \r21__ren + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" + wire width 4 \reg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" + wire width 4 \reg$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 output 3 \src11__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 \src11__data_o$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire input 2 \src11__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 output 5 \src21__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 \src21__data_o$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire input 4 \src21__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 output 7 \src31__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 \src31__data_o$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire input 6 \src31__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 input 16 \w1__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire input 17 \w1__wen + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" + wire \wr_detect + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" + wire \wr_detect$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" + wire \wr_detect$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" + wire \wr_detect$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" + wire \wr_detect$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + cell $not $not$issuer_ls180.v:162140$9962 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_detect$10 + connect \Y $not$issuer_ls180.v:162140$9962_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + cell $not $not$issuer_ls180.v:162141$9963 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_detect$13 + connect \Y $not$issuer_ls180.v:162141$9963_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + cell $not $not$issuer_ls180.v:162142$9964 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_detect + connect \Y $not$issuer_ls180.v:162142$9964_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + cell $not $not$issuer_ls180.v:162143$9965 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_detect$4 + connect \Y $not$issuer_ls180.v:162143$9965_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + cell $not $not$issuer_ls180.v:162144$9966 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_detect$7 + connect \Y $not$issuer_ls180.v:162144$9966_Y + end + attribute \src "issuer_ls180.v:162064.7-162064.20" + process $proc$issuer_ls180.v:162064$10044 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "issuer_ls180.v:162089.13-162089.30" + process $proc$issuer_ls180.v:162089$10045 + assign { } { } + assign $1\r1__data_o[3:0] 4'0000 + sync always + sync init + update \r1__data_o $1\r1__data_o[3:0] + end + attribute \src "issuer_ls180.v:162096.13-162096.31" + process $proc$issuer_ls180.v:162096$10046 + assign { } { } + assign $1\r21__data_o[3:0] 4'0000 + sync always + sync init + update \r21__data_o $1\r21__data_o[3:0] + end + attribute \src "issuer_ls180.v:162102.13-162102.25" + process $proc$issuer_ls180.v:162102$10047 + assign { } { } + assign $1\reg[3:0] 4'0000 + sync always + sync init + update \reg $1\reg[3:0] + end + attribute \src "issuer_ls180.v:162107.13-162107.33" + process $proc$issuer_ls180.v:162107$10048 + assign { } { } + assign $1\src11__data_o[3:0] 4'0000 + sync always + sync init + update \src11__data_o $1\src11__data_o[3:0] + end + attribute \src "issuer_ls180.v:162114.13-162114.33" + process $proc$issuer_ls180.v:162114$10049 + assign { } { } + assign $1\src21__data_o[3:0] 4'0000 + sync always + sync init + update \src21__data_o $1\src21__data_o[3:0] + end + attribute \src "issuer_ls180.v:162121.13-162121.33" + process $proc$issuer_ls180.v:162121$10050 + assign { } { } + assign $1\src31__data_o[3:0] 4'0000 + sync always + sync init + update \src31__data_o $1\src31__data_o[3:0] + end + attribute \src "issuer_ls180.v:162145.3-162146.25" + process $proc$issuer_ls180.v:162145$9967 + assign { } { } + assign $0\reg[3:0] \reg$next + sync posedge \coresync_clk + update \reg $0\reg[3:0] + end + attribute \src "issuer_ls180.v:162147.3-162148.39" + process $proc$issuer_ls180.v:162147$9968 + assign { } { } + assign $0\r21__data_o[3:0] \r21__data_o$next + sync posedge \coresync_clk + update \r21__data_o $0\r21__data_o[3:0] + end + attribute \src "issuer_ls180.v:162149.3-162150.37" + process $proc$issuer_ls180.v:162149$9969 + assign { } { } + assign $0\r1__data_o[3:0] \r1__data_o$next + sync posedge \coresync_clk + update \r1__data_o $0\r1__data_o[3:0] + end + attribute \src "issuer_ls180.v:162151.3-162152.43" + process $proc$issuer_ls180.v:162151$9970 + assign { } { } + assign $0\src31__data_o[3:0] \src31__data_o$next + sync posedge \coresync_clk + update \src31__data_o $0\src31__data_o[3:0] + end + attribute \src "issuer_ls180.v:162153.3-162154.43" + process $proc$issuer_ls180.v:162153$9971 + assign { } { } + assign $0\src21__data_o[3:0] \src21__data_o$next + sync posedge \coresync_clk + update \src21__data_o $0\src21__data_o[3:0] + end + attribute \src "issuer_ls180.v:162155.3-162156.43" + process $proc$issuer_ls180.v:162155$9972 + assign { } { } + assign $0\src11__data_o[3:0] \src11__data_o$next + sync posedge \coresync_clk + update \src11__data_o $0\src11__data_o[3:0] + end + attribute \src "issuer_ls180.v:162157.3-162196.6" + process $proc$issuer_ls180.v:162157$9973 + assign { } { } + assign { } { } + assign { } { } + assign $0\src11__data_o$next[3:0]$9974 $6\src11__data_o$next[3:0]$9980 + attribute \src "issuer_ls180.v:162158.5-162158.29" + switch \initial + attribute \src "issuer_ls180.v:162158.9-162158.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \src11__ren + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\src11__data_o$next[3:0]$9975 $5\src11__data_o$next[3:0]$9979 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest11__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\src11__data_o$next[3:0]$9976 \dest11__data_i + case + assign $2\src11__data_o$next[3:0]$9976 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest21__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\src11__data_o$next[3:0]$9977 \dest21__data_i + case + assign $3\src11__data_o$next[3:0]$9977 $2\src11__data_o$next[3:0]$9976 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w1__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\src11__data_o$next[3:0]$9978 \w1__data_i + case + assign $4\src11__data_o$next[3:0]$9978 $3\src11__data_o$next[3:0]$9977 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + switch \$1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\src11__data_o$next[3:0]$9979 \reg + case + assign $5\src11__data_o$next[3:0]$9979 $4\src11__data_o$next[3:0]$9978 + end + case + assign $1\src11__data_o$next[3:0]$9975 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $6\src11__data_o$next[3:0]$9980 4'0000 + case + assign $6\src11__data_o$next[3:0]$9980 $1\src11__data_o$next[3:0]$9975 + end + sync always + update \src11__data_o$next $0\src11__data_o$next[3:0]$9974 + end + attribute \src "issuer_ls180.v:162197.3-162226.6" + process $proc$issuer_ls180.v:162197$9981 + assign { } { } + assign { } { } + assign $0\wr_detect[0:0] $1\wr_detect[0:0] + attribute \src "issuer_ls180.v:162198.5-162198.29" + switch \initial + attribute \src "issuer_ls180.v:162198.9-162198.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \src11__ren + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\wr_detect[0:0] $4\wr_detect[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest11__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\wr_detect[0:0] 1'1 + case + assign $2\wr_detect[0:0] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest21__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\wr_detect[0:0] 1'1 + case + assign $3\wr_detect[0:0] $2\wr_detect[0:0] + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w1__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\wr_detect[0:0] 1'1 + case + assign $4\wr_detect[0:0] $3\wr_detect[0:0] + end + case + assign $1\wr_detect[0:0] 1'0 + end + sync always + update \wr_detect $0\wr_detect[0:0] + end + attribute \src "issuer_ls180.v:162227.3-162253.6" + process $proc$issuer_ls180.v:162227$9982 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\reg$next[3:0]$9983 $4\reg$next[3:0]$9987 + attribute \src "issuer_ls180.v:162228.5-162228.29" + switch \initial + attribute \src "issuer_ls180.v:162228.9-162228.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" + switch \dest11__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\reg$next[3:0]$9984 \dest11__data_i + case + assign $1\reg$next[3:0]$9984 \reg + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" + switch \dest21__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\reg$next[3:0]$9985 \dest21__data_i + case + assign $2\reg$next[3:0]$9985 $1\reg$next[3:0]$9984 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" + switch \w1__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\reg$next[3:0]$9986 \w1__data_i + case + assign $3\reg$next[3:0]$9986 $2\reg$next[3:0]$9985 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\reg$next[3:0]$9987 4'0000 + case + assign $4\reg$next[3:0]$9987 $3\reg$next[3:0]$9986 + end + sync always + update \reg$next $0\reg$next[3:0]$9983 + end + attribute \src "issuer_ls180.v:162254.3-162293.6" + process $proc$issuer_ls180.v:162254$9988 + assign { } { } + assign { } { } + assign { } { } + assign $0\src21__data_o$next[3:0]$9989 $6\src21__data_o$next[3:0]$9995 + attribute \src "issuer_ls180.v:162255.5-162255.29" + switch \initial + attribute \src "issuer_ls180.v:162255.9-162255.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \src21__ren + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\src21__data_o$next[3:0]$9990 $5\src21__data_o$next[3:0]$9994 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest11__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\src21__data_o$next[3:0]$9991 \dest11__data_i + case + assign $2\src21__data_o$next[3:0]$9991 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest21__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\src21__data_o$next[3:0]$9992 \dest21__data_i + case + assign $3\src21__data_o$next[3:0]$9992 $2\src21__data_o$next[3:0]$9991 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w1__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\src21__data_o$next[3:0]$9993 \w1__data_i + case + assign $4\src21__data_o$next[3:0]$9993 $3\src21__data_o$next[3:0]$9992 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + switch \$3 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\src21__data_o$next[3:0]$9994 \reg + case + assign $5\src21__data_o$next[3:0]$9994 $4\src21__data_o$next[3:0]$9993 + end + case + assign $1\src21__data_o$next[3:0]$9990 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $6\src21__data_o$next[3:0]$9995 4'0000 + case + assign $6\src21__data_o$next[3:0]$9995 $1\src21__data_o$next[3:0]$9990 + end + sync always + update \src21__data_o$next $0\src21__data_o$next[3:0]$9989 + end + attribute \src "issuer_ls180.v:162294.3-162323.6" + process $proc$issuer_ls180.v:162294$9996 + assign { } { } + assign { } { } + assign $0\wr_detect$4[0:0]$9997 $1\wr_detect$4[0:0]$9998 + attribute \src "issuer_ls180.v:162295.5-162295.29" + switch \initial + attribute \src "issuer_ls180.v:162295.9-162295.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \src21__ren + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\wr_detect$4[0:0]$9998 $4\wr_detect$4[0:0]$10001 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest11__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\wr_detect$4[0:0]$9999 1'1 + case + assign $2\wr_detect$4[0:0]$9999 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest21__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\wr_detect$4[0:0]$10000 1'1 + case + assign $3\wr_detect$4[0:0]$10000 $2\wr_detect$4[0:0]$9999 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w1__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\wr_detect$4[0:0]$10001 1'1 + case + assign $4\wr_detect$4[0:0]$10001 $3\wr_detect$4[0:0]$10000 + end + case + assign $1\wr_detect$4[0:0]$9998 1'0 + end + sync always + update \wr_detect$4 $0\wr_detect$4[0:0]$9997 + end + attribute \src "issuer_ls180.v:162324.3-162363.6" + process $proc$issuer_ls180.v:162324$10002 + assign { } { } + assign { } { } + assign { } { } + assign $0\src31__data_o$next[3:0]$10003 $6\src31__data_o$next[3:0]$10009 + attribute \src "issuer_ls180.v:162325.5-162325.29" + switch \initial + attribute \src "issuer_ls180.v:162325.9-162325.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \src31__ren + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\src31__data_o$next[3:0]$10004 $5\src31__data_o$next[3:0]$10008 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest11__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\src31__data_o$next[3:0]$10005 \dest11__data_i + case + assign $2\src31__data_o$next[3:0]$10005 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest21__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\src31__data_o$next[3:0]$10006 \dest21__data_i + case + assign $3\src31__data_o$next[3:0]$10006 $2\src31__data_o$next[3:0]$10005 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w1__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\src31__data_o$next[3:0]$10007 \w1__data_i + case + assign $4\src31__data_o$next[3:0]$10007 $3\src31__data_o$next[3:0]$10006 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + switch \$6 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\src31__data_o$next[3:0]$10008 \reg + case + assign $5\src31__data_o$next[3:0]$10008 $4\src31__data_o$next[3:0]$10007 + end + case + assign $1\src31__data_o$next[3:0]$10004 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $6\src31__data_o$next[3:0]$10009 4'0000 + case + assign $6\src31__data_o$next[3:0]$10009 $1\src31__data_o$next[3:0]$10004 + end + sync always + update \src31__data_o$next $0\src31__data_o$next[3:0]$10003 + end + attribute \src "issuer_ls180.v:162364.3-162393.6" + process $proc$issuer_ls180.v:162364$10010 + assign { } { } + assign { } { } + assign $0\wr_detect$7[0:0]$10011 $1\wr_detect$7[0:0]$10012 + attribute \src "issuer_ls180.v:162365.5-162365.29" + switch \initial + attribute \src "issuer_ls180.v:162365.9-162365.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \src31__ren + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\wr_detect$7[0:0]$10012 $4\wr_detect$7[0:0]$10015 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest11__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\wr_detect$7[0:0]$10013 1'1 + case + assign $2\wr_detect$7[0:0]$10013 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest21__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\wr_detect$7[0:0]$10014 1'1 + case + assign $3\wr_detect$7[0:0]$10014 $2\wr_detect$7[0:0]$10013 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w1__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\wr_detect$7[0:0]$10015 1'1 + case + assign $4\wr_detect$7[0:0]$10015 $3\wr_detect$7[0:0]$10014 + end + case + assign $1\wr_detect$7[0:0]$10012 1'0 + end + sync always + update \wr_detect$7 $0\wr_detect$7[0:0]$10011 + end + attribute \src "issuer_ls180.v:162394.3-162433.6" + process $proc$issuer_ls180.v:162394$10016 + assign { } { } + assign { } { } + assign { } { } + assign $0\r1__data_o$next[3:0]$10017 $6\r1__data_o$next[3:0]$10023 + attribute \src "issuer_ls180.v:162395.5-162395.29" + switch \initial + attribute \src "issuer_ls180.v:162395.9-162395.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \r1__ren + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\r1__data_o$next[3:0]$10018 $5\r1__data_o$next[3:0]$10022 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest11__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\r1__data_o$next[3:0]$10019 \dest11__data_i + case + assign $2\r1__data_o$next[3:0]$10019 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest21__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\r1__data_o$next[3:0]$10020 \dest21__data_i + case + assign $3\r1__data_o$next[3:0]$10020 $2\r1__data_o$next[3:0]$10019 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w1__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\r1__data_o$next[3:0]$10021 \w1__data_i + case + assign $4\r1__data_o$next[3:0]$10021 $3\r1__data_o$next[3:0]$10020 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + switch \$9 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\r1__data_o$next[3:0]$10022 \reg + case + assign $5\r1__data_o$next[3:0]$10022 $4\r1__data_o$next[3:0]$10021 + end + case + assign $1\r1__data_o$next[3:0]$10018 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $6\r1__data_o$next[3:0]$10023 4'0000 + case + assign $6\r1__data_o$next[3:0]$10023 $1\r1__data_o$next[3:0]$10018 + end + sync always + update \r1__data_o$next $0\r1__data_o$next[3:0]$10017 + end + attribute \src "issuer_ls180.v:162434.3-162463.6" + process $proc$issuer_ls180.v:162434$10024 + assign { } { } + assign { } { } + assign $0\wr_detect$10[0:0]$10025 $1\wr_detect$10[0:0]$10026 + attribute \src "issuer_ls180.v:162435.5-162435.29" + switch \initial + attribute \src "issuer_ls180.v:162435.9-162435.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \r1__ren + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\wr_detect$10[0:0]$10026 $4\wr_detect$10[0:0]$10029 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest11__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\wr_detect$10[0:0]$10027 1'1 + case + assign $2\wr_detect$10[0:0]$10027 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest21__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\wr_detect$10[0:0]$10028 1'1 + case + assign $3\wr_detect$10[0:0]$10028 $2\wr_detect$10[0:0]$10027 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w1__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\wr_detect$10[0:0]$10029 1'1 + case + assign $4\wr_detect$10[0:0]$10029 $3\wr_detect$10[0:0]$10028 + end + case + assign $1\wr_detect$10[0:0]$10026 1'0 + end + sync always + update \wr_detect$10 $0\wr_detect$10[0:0]$10025 + end + attribute \src "issuer_ls180.v:162464.3-162503.6" + process $proc$issuer_ls180.v:162464$10030 + assign { } { } + assign { } { } + assign { } { } + assign $0\r21__data_o$next[3:0]$10031 $6\r21__data_o$next[3:0]$10037 + attribute \src "issuer_ls180.v:162465.5-162465.29" + switch \initial + attribute \src "issuer_ls180.v:162465.9-162465.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \r21__ren + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\r21__data_o$next[3:0]$10032 $5\r21__data_o$next[3:0]$10036 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest11__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\r21__data_o$next[3:0]$10033 \dest11__data_i + case + assign $2\r21__data_o$next[3:0]$10033 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest21__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\r21__data_o$next[3:0]$10034 \dest21__data_i + case + assign $3\r21__data_o$next[3:0]$10034 $2\r21__data_o$next[3:0]$10033 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w1__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\r21__data_o$next[3:0]$10035 \w1__data_i + case + assign $4\r21__data_o$next[3:0]$10035 $3\r21__data_o$next[3:0]$10034 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + switch \$12 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\r21__data_o$next[3:0]$10036 \reg + case + assign $5\r21__data_o$next[3:0]$10036 $4\r21__data_o$next[3:0]$10035 + end + case + assign $1\r21__data_o$next[3:0]$10032 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $6\r21__data_o$next[3:0]$10037 4'0000 + case + assign $6\r21__data_o$next[3:0]$10037 $1\r21__data_o$next[3:0]$10032 + end + sync always + update \r21__data_o$next $0\r21__data_o$next[3:0]$10031 + end + attribute \src "issuer_ls180.v:162504.3-162533.6" + process $proc$issuer_ls180.v:162504$10038 + assign { } { } + assign { } { } + assign $0\wr_detect$13[0:0]$10039 $1\wr_detect$13[0:0]$10040 + attribute \src "issuer_ls180.v:162505.5-162505.29" + switch \initial + attribute \src "issuer_ls180.v:162505.9-162505.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \r21__ren + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\wr_detect$13[0:0]$10040 $4\wr_detect$13[0:0]$10043 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest11__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\wr_detect$13[0:0]$10041 1'1 + case + assign $2\wr_detect$13[0:0]$10041 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest21__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\wr_detect$13[0:0]$10042 1'1 + case + assign $3\wr_detect$13[0:0]$10042 $2\wr_detect$13[0:0]$10041 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w1__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\wr_detect$13[0:0]$10043 1'1 + case + assign $4\wr_detect$13[0:0]$10043 $3\wr_detect$13[0:0]$10042 + end + case + assign $1\wr_detect$13[0:0]$10040 1'0 + end + sync always + update \wr_detect$13 $0\wr_detect$13[0:0]$10039 + end + connect \$9 $not$issuer_ls180.v:162140$9962_Y + connect \$12 $not$issuer_ls180.v:162141$9963_Y + connect \$1 $not$issuer_ls180.v:162142$9964_Y + connect \$3 $not$issuer_ls180.v:162143$9965_Y + connect \$6 $not$issuer_ls180.v:162144$9966_Y +end +attribute \src "issuer_ls180.v:162538.1-162983.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.xer.reg_1" +attribute \generator "nMigen" +module \reg_1$130 + attribute \src "issuer_ls180.v:162539.7-162539.20" + wire $0\initial[0:0] + attribute \src "issuer_ls180.v:162868.3-162913.6" + wire width 2 $0\r1__data_o$next[1:0]$10103 + attribute \src "issuer_ls180.v:162614.3-162615.37" + wire width 2 $0\r1__data_o[1:0] + attribute \src "issuer_ls180.v:162950.3-162982.6" + wire width 2 $0\reg$next[1:0]$10119 + attribute \src "issuer_ls180.v:162612.3-162613.25" + wire width 2 $0\reg[1:0] + attribute \src "issuer_ls180.v:162622.3-162667.6" + wire width 2 $0\src11__data_o$next[1:0]$10061 + attribute \src "issuer_ls180.v:162620.3-162621.43" + wire width 2 $0\src11__data_o[1:0] + attribute \src "issuer_ls180.v:162704.3-162749.6" + wire width 2 $0\src21__data_o$next[1:0]$10071 + attribute \src "issuer_ls180.v:162618.3-162619.43" + wire width 2 $0\src21__data_o[1:0] + attribute \src "issuer_ls180.v:162786.3-162831.6" + wire width 2 $0\src31__data_o$next[1:0]$10087 + attribute \src "issuer_ls180.v:162616.3-162617.43" + wire width 2 $0\src31__data_o[1:0] + attribute \src "issuer_ls180.v:162914.3-162949.6" + wire $0\wr_detect$10[0:0]$10112 + attribute \src "issuer_ls180.v:162750.3-162785.6" + wire $0\wr_detect$4[0:0]$10080 + attribute \src "issuer_ls180.v:162832.3-162867.6" + wire $0\wr_detect$7[0:0]$10096 + attribute \src "issuer_ls180.v:162668.3-162703.6" + wire $0\wr_detect[0:0] + attribute \src "issuer_ls180.v:162868.3-162913.6" + wire width 2 $1\r1__data_o$next[1:0]$10104 + attribute \src "issuer_ls180.v:162566.13-162566.30" + wire width 2 $1\r1__data_o[1:0] + attribute \src "issuer_ls180.v:162950.3-162982.6" + wire width 2 $1\reg$next[1:0]$10120 + attribute \src "issuer_ls180.v:162572.13-162572.25" + wire width 2 $1\reg[1:0] + attribute \src "issuer_ls180.v:162622.3-162667.6" + wire width 2 $1\src11__data_o$next[1:0]$10062 + attribute \src "issuer_ls180.v:162577.13-162577.33" + wire width 2 $1\src11__data_o[1:0] + attribute \src "issuer_ls180.v:162704.3-162749.6" + wire width 2 $1\src21__data_o$next[1:0]$10072 + attribute \src "issuer_ls180.v:162584.13-162584.33" + wire width 2 $1\src21__data_o[1:0] + attribute \src "issuer_ls180.v:162786.3-162831.6" + wire width 2 $1\src31__data_o$next[1:0]$10088 + attribute \src "issuer_ls180.v:162591.13-162591.33" + wire width 2 $1\src31__data_o[1:0] + attribute \src "issuer_ls180.v:162914.3-162949.6" + wire $1\wr_detect$10[0:0]$10113 + attribute \src "issuer_ls180.v:162750.3-162785.6" + wire $1\wr_detect$4[0:0]$10081 + attribute \src "issuer_ls180.v:162832.3-162867.6" + wire $1\wr_detect$7[0:0]$10097 + attribute \src "issuer_ls180.v:162668.3-162703.6" + wire $1\wr_detect[0:0] + attribute \src "issuer_ls180.v:162868.3-162913.6" + wire width 2 $2\r1__data_o$next[1:0]$10105 + attribute \src "issuer_ls180.v:162950.3-162982.6" + wire width 2 $2\reg$next[1:0]$10121 + attribute \src "issuer_ls180.v:162622.3-162667.6" + wire width 2 $2\src11__data_o$next[1:0]$10063 + attribute \src "issuer_ls180.v:162704.3-162749.6" + wire width 2 $2\src21__data_o$next[1:0]$10073 + attribute \src "issuer_ls180.v:162786.3-162831.6" + wire width 2 $2\src31__data_o$next[1:0]$10089 + attribute \src "issuer_ls180.v:162914.3-162949.6" + wire $2\wr_detect$10[0:0]$10114 + attribute \src "issuer_ls180.v:162750.3-162785.6" + wire $2\wr_detect$4[0:0]$10082 + attribute \src "issuer_ls180.v:162832.3-162867.6" + wire $2\wr_detect$7[0:0]$10098 + attribute \src "issuer_ls180.v:162668.3-162703.6" + wire $2\wr_detect[0:0] + attribute \src "issuer_ls180.v:162868.3-162913.6" + wire width 2 $3\r1__data_o$next[1:0]$10106 + attribute \src "issuer_ls180.v:162950.3-162982.6" + wire width 2 $3\reg$next[1:0]$10122 + attribute \src "issuer_ls180.v:162622.3-162667.6" + wire width 2 $3\src11__data_o$next[1:0]$10064 + attribute \src "issuer_ls180.v:162704.3-162749.6" + wire width 2 $3\src21__data_o$next[1:0]$10074 + attribute \src "issuer_ls180.v:162786.3-162831.6" + wire width 2 $3\src31__data_o$next[1:0]$10090 + attribute \src "issuer_ls180.v:162914.3-162949.6" + wire $3\wr_detect$10[0:0]$10115 + attribute \src "issuer_ls180.v:162750.3-162785.6" + wire $3\wr_detect$4[0:0]$10083 + attribute \src "issuer_ls180.v:162832.3-162867.6" + wire $3\wr_detect$7[0:0]$10099 + attribute \src "issuer_ls180.v:162668.3-162703.6" + wire $3\wr_detect[0:0] + attribute \src "issuer_ls180.v:162868.3-162913.6" + wire width 2 $4\r1__data_o$next[1:0]$10107 + attribute \src "issuer_ls180.v:162950.3-162982.6" + wire width 2 $4\reg$next[1:0]$10123 + attribute \src "issuer_ls180.v:162622.3-162667.6" + wire width 2 $4\src11__data_o$next[1:0]$10065 + attribute \src "issuer_ls180.v:162704.3-162749.6" + wire width 2 $4\src21__data_o$next[1:0]$10075 + attribute \src "issuer_ls180.v:162786.3-162831.6" + wire width 2 $4\src31__data_o$next[1:0]$10091 + attribute \src "issuer_ls180.v:162914.3-162949.6" + wire $4\wr_detect$10[0:0]$10116 + attribute \src "issuer_ls180.v:162750.3-162785.6" + wire $4\wr_detect$4[0:0]$10084 + attribute \src "issuer_ls180.v:162832.3-162867.6" + wire $4\wr_detect$7[0:0]$10100 + attribute \src "issuer_ls180.v:162668.3-162703.6" + wire $4\wr_detect[0:0] + attribute \src "issuer_ls180.v:162868.3-162913.6" + wire width 2 $5\r1__data_o$next[1:0]$10108 + attribute \src "issuer_ls180.v:162950.3-162982.6" + wire width 2 $5\reg$next[1:0]$10124 + attribute \src "issuer_ls180.v:162622.3-162667.6" + wire width 2 $5\src11__data_o$next[1:0]$10066 + attribute \src "issuer_ls180.v:162704.3-162749.6" + wire width 2 $5\src21__data_o$next[1:0]$10076 + attribute \src "issuer_ls180.v:162786.3-162831.6" + wire width 2 $5\src31__data_o$next[1:0]$10092 + attribute \src "issuer_ls180.v:162914.3-162949.6" + wire $5\wr_detect$10[0:0]$10117 + attribute \src "issuer_ls180.v:162750.3-162785.6" + wire $5\wr_detect$4[0:0]$10085 + attribute \src "issuer_ls180.v:162832.3-162867.6" + wire $5\wr_detect$7[0:0]$10101 + attribute \src "issuer_ls180.v:162668.3-162703.6" + wire $5\wr_detect[0:0] + attribute \src "issuer_ls180.v:162868.3-162913.6" + wire width 2 $6\r1__data_o$next[1:0]$10109 + attribute \src "issuer_ls180.v:162622.3-162667.6" + wire width 2 $6\src11__data_o$next[1:0]$10067 + attribute \src "issuer_ls180.v:162704.3-162749.6" + wire width 2 $6\src21__data_o$next[1:0]$10077 + attribute \src "issuer_ls180.v:162786.3-162831.6" + wire width 2 $6\src31__data_o$next[1:0]$10093 + attribute \src "issuer_ls180.v:162868.3-162913.6" + wire width 2 $7\r1__data_o$next[1:0]$10110 + attribute \src "issuer_ls180.v:162622.3-162667.6" + wire width 2 $7\src11__data_o$next[1:0]$10068 + attribute \src "issuer_ls180.v:162704.3-162749.6" + wire width 2 $7\src21__data_o$next[1:0]$10078 + attribute \src "issuer_ls180.v:162786.3-162831.6" + wire width 2 $7\src31__data_o$next[1:0]$10094 + attribute \src "issuer_ls180.v:162608.17-162608.104" + wire $not$issuer_ls180.v:162608$10051_Y + attribute \src "issuer_ls180.v:162609.17-162609.100" + wire $not$issuer_ls180.v:162609$10052_Y + attribute \src "issuer_ls180.v:162610.17-162610.103" + wire $not$issuer_ls180.v:162610$10053_Y + attribute \src "issuer_ls180.v:162611.17-162611.103" + wire $not$issuer_ls180.v:162611$10054_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + wire \$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + wire \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" + wire input 18 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" + wire input 1 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 2 input 9 \dest11__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire input 8 \dest11__wen + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 2 input 11 \dest21__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire input 10 \dest21__wen + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 2 input 13 \dest31__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire input 12 \dest31__wen + attribute \src "issuer_ls180.v:162539.7-162539.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 2 output 14 \r1__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 2 \r1__data_o$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire input 15 \r1__ren + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" + wire width 2 \reg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" + wire width 2 \reg$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 2 output 3 \src11__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 2 \src11__data_o$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire input 2 \src11__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 2 output 5 \src21__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 2 \src21__data_o$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire input 4 \src21__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 2 output 7 \src31__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 2 \src31__data_o$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire input 6 \src31__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 2 input 16 \w1__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire input 17 \w1__wen + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" + wire \wr_detect + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" + wire \wr_detect$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" + wire \wr_detect$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" + wire \wr_detect$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + cell $not $not$issuer_ls180.v:162608$10051 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_detect$10 + connect \Y $not$issuer_ls180.v:162608$10051_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + cell $not $not$issuer_ls180.v:162609$10052 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_detect + connect \Y $not$issuer_ls180.v:162609$10052_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + cell $not $not$issuer_ls180.v:162610$10053 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_detect$4 + connect \Y $not$issuer_ls180.v:162610$10053_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + cell $not $not$issuer_ls180.v:162611$10054 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_detect$7 + connect \Y $not$issuer_ls180.v:162611$10054_Y + end + attribute \src "issuer_ls180.v:162539.7-162539.20" + process $proc$issuer_ls180.v:162539$10125 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "issuer_ls180.v:162566.13-162566.30" + process $proc$issuer_ls180.v:162566$10126 + assign { } { } + assign $1\r1__data_o[1:0] 2'00 + sync always + sync init + update \r1__data_o $1\r1__data_o[1:0] + end + attribute \src "issuer_ls180.v:162572.13-162572.25" + process $proc$issuer_ls180.v:162572$10127 + assign { } { } + assign $1\reg[1:0] 2'00 + sync always + sync init + update \reg $1\reg[1:0] + end + attribute \src "issuer_ls180.v:162577.13-162577.33" + process $proc$issuer_ls180.v:162577$10128 + assign { } { } + assign $1\src11__data_o[1:0] 2'00 + sync always + sync init + update \src11__data_o $1\src11__data_o[1:0] + end + attribute \src "issuer_ls180.v:162584.13-162584.33" + process $proc$issuer_ls180.v:162584$10129 + assign { } { } + assign $1\src21__data_o[1:0] 2'00 + sync always + sync init + update \src21__data_o $1\src21__data_o[1:0] + end + attribute \src "issuer_ls180.v:162591.13-162591.33" + process $proc$issuer_ls180.v:162591$10130 + assign { } { } + assign $1\src31__data_o[1:0] 2'00 + sync always + sync init + update \src31__data_o $1\src31__data_o[1:0] + end + attribute \src "issuer_ls180.v:162612.3-162613.25" + process $proc$issuer_ls180.v:162612$10055 + assign { } { } + assign $0\reg[1:0] \reg$next + sync posedge \coresync_clk + update \reg $0\reg[1:0] + end + attribute \src "issuer_ls180.v:162614.3-162615.37" + process $proc$issuer_ls180.v:162614$10056 + assign { } { } + assign $0\r1__data_o[1:0] \r1__data_o$next + sync posedge \coresync_clk + update \r1__data_o $0\r1__data_o[1:0] + end + attribute \src "issuer_ls180.v:162616.3-162617.43" + process $proc$issuer_ls180.v:162616$10057 + assign { } { } + assign $0\src31__data_o[1:0] \src31__data_o$next + sync posedge \coresync_clk + update \src31__data_o $0\src31__data_o[1:0] + end + attribute \src "issuer_ls180.v:162618.3-162619.43" + process $proc$issuer_ls180.v:162618$10058 + assign { } { } + assign $0\src21__data_o[1:0] \src21__data_o$next + sync posedge \coresync_clk + update \src21__data_o $0\src21__data_o[1:0] + end + attribute \src "issuer_ls180.v:162620.3-162621.43" + process $proc$issuer_ls180.v:162620$10059 + assign { } { } + assign $0\src11__data_o[1:0] \src11__data_o$next + sync posedge \coresync_clk + update \src11__data_o $0\src11__data_o[1:0] + end + attribute \src "issuer_ls180.v:162622.3-162667.6" + process $proc$issuer_ls180.v:162622$10060 + assign { } { } + assign { } { } + assign { } { } + assign $0\src11__data_o$next[1:0]$10061 $7\src11__data_o$next[1:0]$10068 + attribute \src "issuer_ls180.v:162623.5-162623.29" + switch \initial + attribute \src "issuer_ls180.v:162623.9-162623.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \src11__ren + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\src11__data_o$next[1:0]$10062 $6\src11__data_o$next[1:0]$10067 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest11__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\src11__data_o$next[1:0]$10063 \dest11__data_i + case + assign $2\src11__data_o$next[1:0]$10063 2'00 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest21__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\src11__data_o$next[1:0]$10064 \dest21__data_i + case + assign $3\src11__data_o$next[1:0]$10064 $2\src11__data_o$next[1:0]$10063 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest31__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\src11__data_o$next[1:0]$10065 \dest31__data_i + case + assign $4\src11__data_o$next[1:0]$10065 $3\src11__data_o$next[1:0]$10064 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w1__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\src11__data_o$next[1:0]$10066 \w1__data_i + case + assign $5\src11__data_o$next[1:0]$10066 $4\src11__data_o$next[1:0]$10065 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + switch \$1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $6\src11__data_o$next[1:0]$10067 \reg + case + assign $6\src11__data_o$next[1:0]$10067 $5\src11__data_o$next[1:0]$10066 + end + case + assign $1\src11__data_o$next[1:0]$10062 2'00 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $7\src11__data_o$next[1:0]$10068 2'00 + case + assign $7\src11__data_o$next[1:0]$10068 $1\src11__data_o$next[1:0]$10062 + end + sync always + update \src11__data_o$next $0\src11__data_o$next[1:0]$10061 + end + attribute \src "issuer_ls180.v:162668.3-162703.6" + process $proc$issuer_ls180.v:162668$10069 + assign { } { } + assign { } { } + assign $0\wr_detect[0:0] $1\wr_detect[0:0] + attribute \src "issuer_ls180.v:162669.5-162669.29" + switch \initial + attribute \src "issuer_ls180.v:162669.9-162669.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \src11__ren + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\wr_detect[0:0] $5\wr_detect[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest11__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\wr_detect[0:0] 1'1 + case + assign $2\wr_detect[0:0] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest21__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\wr_detect[0:0] 1'1 + case + assign $3\wr_detect[0:0] $2\wr_detect[0:0] + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest31__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\wr_detect[0:0] 1'1 + case + assign $4\wr_detect[0:0] $3\wr_detect[0:0] + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w1__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\wr_detect[0:0] 1'1 + case + assign $5\wr_detect[0:0] $4\wr_detect[0:0] + end + case + assign $1\wr_detect[0:0] 1'0 + end + sync always + update \wr_detect $0\wr_detect[0:0] + end + attribute \src "issuer_ls180.v:162704.3-162749.6" + process $proc$issuer_ls180.v:162704$10070 + assign { } { } + assign { } { } + assign { } { } + assign $0\src21__data_o$next[1:0]$10071 $7\src21__data_o$next[1:0]$10078 + attribute \src "issuer_ls180.v:162705.5-162705.29" + switch \initial + attribute \src "issuer_ls180.v:162705.9-162705.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \src21__ren + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\src21__data_o$next[1:0]$10072 $6\src21__data_o$next[1:0]$10077 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest11__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\src21__data_o$next[1:0]$10073 \dest11__data_i + case + assign $2\src21__data_o$next[1:0]$10073 2'00 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest21__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\src21__data_o$next[1:0]$10074 \dest21__data_i + case + assign $3\src21__data_o$next[1:0]$10074 $2\src21__data_o$next[1:0]$10073 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest31__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\src21__data_o$next[1:0]$10075 \dest31__data_i + case + assign $4\src21__data_o$next[1:0]$10075 $3\src21__data_o$next[1:0]$10074 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w1__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\src21__data_o$next[1:0]$10076 \w1__data_i + case + assign $5\src21__data_o$next[1:0]$10076 $4\src21__data_o$next[1:0]$10075 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + switch \$3 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $6\src21__data_o$next[1:0]$10077 \reg + case + assign $6\src21__data_o$next[1:0]$10077 $5\src21__data_o$next[1:0]$10076 + end + case + assign $1\src21__data_o$next[1:0]$10072 2'00 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $7\src21__data_o$next[1:0]$10078 2'00 + case + assign $7\src21__data_o$next[1:0]$10078 $1\src21__data_o$next[1:0]$10072 + end + sync always + update \src21__data_o$next $0\src21__data_o$next[1:0]$10071 + end + attribute \src "issuer_ls180.v:162750.3-162785.6" + process $proc$issuer_ls180.v:162750$10079 + assign { } { } + assign { } { } + assign $0\wr_detect$4[0:0]$10080 $1\wr_detect$4[0:0]$10081 + attribute \src "issuer_ls180.v:162751.5-162751.29" + switch \initial + attribute \src "issuer_ls180.v:162751.9-162751.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \src21__ren + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\wr_detect$4[0:0]$10081 $5\wr_detect$4[0:0]$10085 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest11__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\wr_detect$4[0:0]$10082 1'1 + case + assign $2\wr_detect$4[0:0]$10082 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest21__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\wr_detect$4[0:0]$10083 1'1 + case + assign $3\wr_detect$4[0:0]$10083 $2\wr_detect$4[0:0]$10082 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest31__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\wr_detect$4[0:0]$10084 1'1 + case + assign $4\wr_detect$4[0:0]$10084 $3\wr_detect$4[0:0]$10083 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w1__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\wr_detect$4[0:0]$10085 1'1 + case + assign $5\wr_detect$4[0:0]$10085 $4\wr_detect$4[0:0]$10084 + end + case + assign $1\wr_detect$4[0:0]$10081 1'0 + end + sync always + update \wr_detect$4 $0\wr_detect$4[0:0]$10080 + end + attribute \src "issuer_ls180.v:162786.3-162831.6" + process $proc$issuer_ls180.v:162786$10086 + assign { } { } + assign { } { } + assign { } { } + assign $0\src31__data_o$next[1:0]$10087 $7\src31__data_o$next[1:0]$10094 + attribute \src "issuer_ls180.v:162787.5-162787.29" + switch \initial + attribute \src "issuer_ls180.v:162787.9-162787.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \src31__ren + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\src31__data_o$next[1:0]$10088 $6\src31__data_o$next[1:0]$10093 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest11__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\src31__data_o$next[1:0]$10089 \dest11__data_i + case + assign $2\src31__data_o$next[1:0]$10089 2'00 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest21__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\src31__data_o$next[1:0]$10090 \dest21__data_i + case + assign $3\src31__data_o$next[1:0]$10090 $2\src31__data_o$next[1:0]$10089 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest31__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\src31__data_o$next[1:0]$10091 \dest31__data_i + case + assign $4\src31__data_o$next[1:0]$10091 $3\src31__data_o$next[1:0]$10090 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w1__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\src31__data_o$next[1:0]$10092 \w1__data_i + case + assign $5\src31__data_o$next[1:0]$10092 $4\src31__data_o$next[1:0]$10091 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + switch \$6 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $6\src31__data_o$next[1:0]$10093 \reg + case + assign $6\src31__data_o$next[1:0]$10093 $5\src31__data_o$next[1:0]$10092 + end + case + assign $1\src31__data_o$next[1:0]$10088 2'00 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $7\src31__data_o$next[1:0]$10094 2'00 + case + assign $7\src31__data_o$next[1:0]$10094 $1\src31__data_o$next[1:0]$10088 + end + sync always + update \src31__data_o$next $0\src31__data_o$next[1:0]$10087 + end + attribute \src "issuer_ls180.v:162832.3-162867.6" + process $proc$issuer_ls180.v:162832$10095 + assign { } { } + assign { } { } + assign $0\wr_detect$7[0:0]$10096 $1\wr_detect$7[0:0]$10097 + attribute \src "issuer_ls180.v:162833.5-162833.29" + switch \initial + attribute \src "issuer_ls180.v:162833.9-162833.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \src31__ren + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\wr_detect$7[0:0]$10097 $5\wr_detect$7[0:0]$10101 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest11__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\wr_detect$7[0:0]$10098 1'1 + case + assign $2\wr_detect$7[0:0]$10098 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest21__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\wr_detect$7[0:0]$10099 1'1 + case + assign $3\wr_detect$7[0:0]$10099 $2\wr_detect$7[0:0]$10098 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest31__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\wr_detect$7[0:0]$10100 1'1 + case + assign $4\wr_detect$7[0:0]$10100 $3\wr_detect$7[0:0]$10099 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w1__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\wr_detect$7[0:0]$10101 1'1 + case + assign $5\wr_detect$7[0:0]$10101 $4\wr_detect$7[0:0]$10100 + end + case + assign $1\wr_detect$7[0:0]$10097 1'0 + end + sync always + update \wr_detect$7 $0\wr_detect$7[0:0]$10096 + end + attribute \src "issuer_ls180.v:162868.3-162913.6" + process $proc$issuer_ls180.v:162868$10102 + assign { } { } + assign { } { } + assign { } { } + assign $0\r1__data_o$next[1:0]$10103 $7\r1__data_o$next[1:0]$10110 + attribute \src "issuer_ls180.v:162869.5-162869.29" + switch \initial + attribute \src "issuer_ls180.v:162869.9-162869.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \r1__ren + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\r1__data_o$next[1:0]$10104 $6\r1__data_o$next[1:0]$10109 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest11__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\r1__data_o$next[1:0]$10105 \dest11__data_i + case + assign $2\r1__data_o$next[1:0]$10105 2'00 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest21__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\r1__data_o$next[1:0]$10106 \dest21__data_i + case + assign $3\r1__data_o$next[1:0]$10106 $2\r1__data_o$next[1:0]$10105 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest31__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\r1__data_o$next[1:0]$10107 \dest31__data_i + case + assign $4\r1__data_o$next[1:0]$10107 $3\r1__data_o$next[1:0]$10106 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w1__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\r1__data_o$next[1:0]$10108 \w1__data_i + case + assign $5\r1__data_o$next[1:0]$10108 $4\r1__data_o$next[1:0]$10107 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + switch \$9 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $6\r1__data_o$next[1:0]$10109 \reg + case + assign $6\r1__data_o$next[1:0]$10109 $5\r1__data_o$next[1:0]$10108 + end + case + assign $1\r1__data_o$next[1:0]$10104 2'00 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $7\r1__data_o$next[1:0]$10110 2'00 + case + assign $7\r1__data_o$next[1:0]$10110 $1\r1__data_o$next[1:0]$10104 + end + sync always + update \r1__data_o$next $0\r1__data_o$next[1:0]$10103 + end + attribute \src "issuer_ls180.v:162914.3-162949.6" + process $proc$issuer_ls180.v:162914$10111 + assign { } { } + assign { } { } + assign $0\wr_detect$10[0:0]$10112 $1\wr_detect$10[0:0]$10113 + attribute \src "issuer_ls180.v:162915.5-162915.29" + switch \initial + attribute \src "issuer_ls180.v:162915.9-162915.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \r1__ren + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\wr_detect$10[0:0]$10113 $5\wr_detect$10[0:0]$10117 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest11__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\wr_detect$10[0:0]$10114 1'1 + case + assign $2\wr_detect$10[0:0]$10114 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest21__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\wr_detect$10[0:0]$10115 1'1 + case + assign $3\wr_detect$10[0:0]$10115 $2\wr_detect$10[0:0]$10114 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest31__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\wr_detect$10[0:0]$10116 1'1 + case + assign $4\wr_detect$10[0:0]$10116 $3\wr_detect$10[0:0]$10115 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w1__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\wr_detect$10[0:0]$10117 1'1 + case + assign $5\wr_detect$10[0:0]$10117 $4\wr_detect$10[0:0]$10116 + end + case + assign $1\wr_detect$10[0:0]$10113 1'0 + end + sync always + update \wr_detect$10 $0\wr_detect$10[0:0]$10112 + end + attribute \src "issuer_ls180.v:162950.3-162982.6" + process $proc$issuer_ls180.v:162950$10118 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\reg$next[1:0]$10119 $5\reg$next[1:0]$10124 + attribute \src "issuer_ls180.v:162951.5-162951.29" + switch \initial + attribute \src "issuer_ls180.v:162951.9-162951.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" + switch \dest11__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\reg$next[1:0]$10120 \dest11__data_i + case + assign $1\reg$next[1:0]$10120 \reg + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" + switch \dest21__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\reg$next[1:0]$10121 \dest21__data_i + case + assign $2\reg$next[1:0]$10121 $1\reg$next[1:0]$10120 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" + switch \dest31__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\reg$next[1:0]$10122 \dest31__data_i + case + assign $3\reg$next[1:0]$10122 $2\reg$next[1:0]$10121 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" + switch \w1__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\reg$next[1:0]$10123 \w1__data_i + case + assign $4\reg$next[1:0]$10123 $3\reg$next[1:0]$10122 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\reg$next[1:0]$10124 2'00 + case + assign $5\reg$next[1:0]$10124 $4\reg$next[1:0]$10123 + end + sync always + update \reg$next $0\reg$next[1:0]$10119 + end + connect \$9 $not$issuer_ls180.v:162608$10051_Y + connect \$1 $not$issuer_ls180.v:162609$10052_Y + connect \$3 $not$issuer_ls180.v:162610$10053_Y + connect \$6 $not$issuer_ls180.v:162611$10054_Y +end +attribute \src "issuer_ls180.v:162987.1-163206.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.state.reg_1" +attribute \generator "nMigen" +module \reg_1$133 + attribute \src "issuer_ls180.v:163039.3-163078.6" + wire width 64 $0\cia1__data_o$next[63:0]$10137 + attribute \src "issuer_ls180.v:163037.3-163038.41" + wire width 64 $0\cia1__data_o[63:0] + attribute \src "issuer_ls180.v:162988.7-162988.20" + wire $0\initial[0:0] + attribute \src "issuer_ls180.v:163109.3-163148.6" + wire width 64 $0\msr1__data_o$next[63:0]$10146 + attribute \src "issuer_ls180.v:163035.3-163036.41" + wire width 64 $0\msr1__data_o[63:0] + attribute \src "issuer_ls180.v:163179.3-163205.6" + wire width 64 $0\reg$next[63:0]$10160 + attribute \src "issuer_ls180.v:163033.3-163034.25" + wire width 64 $0\reg[63:0] + attribute \src "issuer_ls180.v:163149.3-163178.6" + wire $0\wr_detect$4[0:0]$10154 + attribute \src "issuer_ls180.v:163079.3-163108.6" + wire $0\wr_detect[0:0] + attribute \src "issuer_ls180.v:163039.3-163078.6" + wire width 64 $1\cia1__data_o$next[63:0]$10138 + attribute \src "issuer_ls180.v:162995.14-162995.49" + wire width 64 $1\cia1__data_o[63:0] + attribute \src "issuer_ls180.v:163109.3-163148.6" + wire width 64 $1\msr1__data_o$next[63:0]$10147 + attribute \src "issuer_ls180.v:163012.14-163012.49" + wire width 64 $1\msr1__data_o[63:0] + attribute \src "issuer_ls180.v:163179.3-163205.6" + wire width 64 $1\reg$next[63:0]$10161 + attribute \src "issuer_ls180.v:163024.14-163024.42" + wire width 64 $1\reg[63:0] + attribute \src "issuer_ls180.v:163149.3-163178.6" + wire $1\wr_detect$4[0:0]$10155 + attribute \src "issuer_ls180.v:163079.3-163108.6" + wire $1\wr_detect[0:0] + attribute \src "issuer_ls180.v:163039.3-163078.6" + wire width 64 $2\cia1__data_o$next[63:0]$10139 + attribute \src "issuer_ls180.v:163109.3-163148.6" + wire width 64 $2\msr1__data_o$next[63:0]$10148 + attribute \src "issuer_ls180.v:163179.3-163205.6" + wire width 64 $2\reg$next[63:0]$10162 + attribute \src "issuer_ls180.v:163149.3-163178.6" + wire $2\wr_detect$4[0:0]$10156 + attribute \src "issuer_ls180.v:163079.3-163108.6" + wire $2\wr_detect[0:0] + attribute \src "issuer_ls180.v:163039.3-163078.6" + wire width 64 $3\cia1__data_o$next[63:0]$10140 + attribute \src "issuer_ls180.v:163109.3-163148.6" + wire width 64 $3\msr1__data_o$next[63:0]$10149 + attribute \src "issuer_ls180.v:163179.3-163205.6" + wire width 64 $3\reg$next[63:0]$10163 + attribute \src "issuer_ls180.v:163149.3-163178.6" + wire $3\wr_detect$4[0:0]$10157 + attribute \src "issuer_ls180.v:163079.3-163108.6" + wire $3\wr_detect[0:0] + attribute \src "issuer_ls180.v:163039.3-163078.6" + wire width 64 $4\cia1__data_o$next[63:0]$10141 + attribute \src "issuer_ls180.v:163109.3-163148.6" + wire width 64 $4\msr1__data_o$next[63:0]$10150 + attribute \src "issuer_ls180.v:163179.3-163205.6" + wire width 64 $4\reg$next[63:0]$10164 + attribute \src "issuer_ls180.v:163149.3-163178.6" + wire $4\wr_detect$4[0:0]$10158 + attribute \src "issuer_ls180.v:163079.3-163108.6" + wire $4\wr_detect[0:0] + attribute \src "issuer_ls180.v:163039.3-163078.6" + wire width 64 $5\cia1__data_o$next[63:0]$10142 + attribute \src "issuer_ls180.v:163109.3-163148.6" + wire width 64 $5\msr1__data_o$next[63:0]$10151 + attribute \src "issuer_ls180.v:163039.3-163078.6" + wire width 64 $6\cia1__data_o$next[63:0]$10143 + attribute \src "issuer_ls180.v:163109.3-163148.6" + wire width 64 $6\msr1__data_o$next[63:0]$10152 + attribute \src "issuer_ls180.v:163031.17-163031.100" + wire $not$issuer_ls180.v:163031$10131_Y + attribute \src "issuer_ls180.v:163032.17-163032.103" + wire $not$issuer_ls180.v:163032$10132_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 64 output 3 \cia1__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 64 \cia1__data_o$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire input 2 \cia1__ren + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" + wire input 12 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" + wire input 1 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 64 input 11 \d_wr11__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire input 10 \d_wr11__wen + attribute \src "issuer_ls180.v:162988.7-162988.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 64 input 9 \msr1__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 64 output 5 \msr1__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 64 \msr1__data_o$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire input 4 \msr1__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire input 8 \msr1__wen + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 64 input 7 \nia1__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire input 6 \nia1__wen + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" + wire width 64 \reg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" + wire width 64 \reg$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" + wire \wr_detect + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" + wire \wr_detect$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + cell $not $not$issuer_ls180.v:163031$10131 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_detect + connect \Y $not$issuer_ls180.v:163031$10131_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + cell $not $not$issuer_ls180.v:163032$10132 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_detect$4 + connect \Y $not$issuer_ls180.v:163032$10132_Y + end + attribute \src "issuer_ls180.v:162988.7-162988.20" + process $proc$issuer_ls180.v:162988$10165 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "issuer_ls180.v:162995.14-162995.49" + process $proc$issuer_ls180.v:162995$10166 + assign { } { } + assign $1\cia1__data_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \cia1__data_o $1\cia1__data_o[63:0] + end + attribute \src "issuer_ls180.v:163012.14-163012.49" + process $proc$issuer_ls180.v:163012$10167 + assign { } { } + assign $1\msr1__data_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \msr1__data_o $1\msr1__data_o[63:0] + end + attribute \src "issuer_ls180.v:163024.14-163024.42" + process $proc$issuer_ls180.v:163024$10168 + assign { } { } + assign $1\reg[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \reg $1\reg[63:0] + end + attribute \src "issuer_ls180.v:163033.3-163034.25" + process $proc$issuer_ls180.v:163033$10133 + assign { } { } + assign $0\reg[63:0] \reg$next + sync posedge \coresync_clk + update \reg $0\reg[63:0] + end + attribute \src "issuer_ls180.v:163035.3-163036.41" + process $proc$issuer_ls180.v:163035$10134 + assign { } { } + assign $0\msr1__data_o[63:0] \msr1__data_o$next + sync posedge \coresync_clk + update \msr1__data_o $0\msr1__data_o[63:0] + end + attribute \src "issuer_ls180.v:163037.3-163038.41" + process $proc$issuer_ls180.v:163037$10135 + assign { } { } + assign $0\cia1__data_o[63:0] \cia1__data_o$next + sync posedge \coresync_clk + update \cia1__data_o $0\cia1__data_o[63:0] + end + attribute \src "issuer_ls180.v:163039.3-163078.6" + process $proc$issuer_ls180.v:163039$10136 + assign { } { } + assign { } { } + assign { } { } + assign $0\cia1__data_o$next[63:0]$10137 $6\cia1__data_o$next[63:0]$10143 + attribute \src "issuer_ls180.v:163040.5-163040.29" + switch \initial + attribute \src "issuer_ls180.v:163040.9-163040.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \cia1__ren + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\cia1__data_o$next[63:0]$10138 $5\cia1__data_o$next[63:0]$10142 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \nia1__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\cia1__data_o$next[63:0]$10139 \nia1__data_i + case + assign $2\cia1__data_o$next[63:0]$10139 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \msr1__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\cia1__data_o$next[63:0]$10140 \msr1__data_i + case + assign $3\cia1__data_o$next[63:0]$10140 $2\cia1__data_o$next[63:0]$10139 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \d_wr11__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\cia1__data_o$next[63:0]$10141 \d_wr11__data_i + case + assign $4\cia1__data_o$next[63:0]$10141 $3\cia1__data_o$next[63:0]$10140 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + switch \$1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\cia1__data_o$next[63:0]$10142 \reg + case + assign $5\cia1__data_o$next[63:0]$10142 $4\cia1__data_o$next[63:0]$10141 + end + case + assign $1\cia1__data_o$next[63:0]$10138 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $6\cia1__data_o$next[63:0]$10143 64'0000000000000000000000000000000000000000000000000000000000000000 + case + assign $6\cia1__data_o$next[63:0]$10143 $1\cia1__data_o$next[63:0]$10138 + end + sync always + update \cia1__data_o$next $0\cia1__data_o$next[63:0]$10137 + end + attribute \src "issuer_ls180.v:163079.3-163108.6" + process $proc$issuer_ls180.v:163079$10144 + assign { } { } + assign { } { } + assign $0\wr_detect[0:0] $1\wr_detect[0:0] + attribute \src "issuer_ls180.v:163080.5-163080.29" + switch \initial + attribute \src "issuer_ls180.v:163080.9-163080.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \cia1__ren + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\wr_detect[0:0] $4\wr_detect[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \nia1__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\wr_detect[0:0] 1'1 + case + assign $2\wr_detect[0:0] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \msr1__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\wr_detect[0:0] 1'1 + case + assign $3\wr_detect[0:0] $2\wr_detect[0:0] + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \d_wr11__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\wr_detect[0:0] 1'1 + case + assign $4\wr_detect[0:0] $3\wr_detect[0:0] + end + case + assign $1\wr_detect[0:0] 1'0 + end + sync always + update \wr_detect $0\wr_detect[0:0] + end + attribute \src "issuer_ls180.v:163109.3-163148.6" + process $proc$issuer_ls180.v:163109$10145 + assign { } { } + assign { } { } + assign { } { } + assign $0\msr1__data_o$next[63:0]$10146 $6\msr1__data_o$next[63:0]$10152 + attribute \src "issuer_ls180.v:163110.5-163110.29" + switch \initial + attribute \src "issuer_ls180.v:163110.9-163110.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \msr1__ren + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\msr1__data_o$next[63:0]$10147 $5\msr1__data_o$next[63:0]$10151 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \nia1__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\msr1__data_o$next[63:0]$10148 \nia1__data_i + case + assign $2\msr1__data_o$next[63:0]$10148 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \msr1__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\msr1__data_o$next[63:0]$10149 \msr1__data_i + case + assign $3\msr1__data_o$next[63:0]$10149 $2\msr1__data_o$next[63:0]$10148 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \d_wr11__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\msr1__data_o$next[63:0]$10150 \d_wr11__data_i + case + assign $4\msr1__data_o$next[63:0]$10150 $3\msr1__data_o$next[63:0]$10149 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + switch \$3 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\msr1__data_o$next[63:0]$10151 \reg + case + assign $5\msr1__data_o$next[63:0]$10151 $4\msr1__data_o$next[63:0]$10150 + end + case + assign $1\msr1__data_o$next[63:0]$10147 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $6\msr1__data_o$next[63:0]$10152 64'0000000000000000000000000000000000000000000000000000000000000000 + case + assign $6\msr1__data_o$next[63:0]$10152 $1\msr1__data_o$next[63:0]$10147 + end + sync always + update \msr1__data_o$next $0\msr1__data_o$next[63:0]$10146 + end + attribute \src "issuer_ls180.v:163149.3-163178.6" + process $proc$issuer_ls180.v:163149$10153 + assign { } { } + assign { } { } + assign $0\wr_detect$4[0:0]$10154 $1\wr_detect$4[0:0]$10155 + attribute \src "issuer_ls180.v:163150.5-163150.29" + switch \initial + attribute \src "issuer_ls180.v:163150.9-163150.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \msr1__ren + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\wr_detect$4[0:0]$10155 $4\wr_detect$4[0:0]$10158 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \nia1__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\wr_detect$4[0:0]$10156 1'1 + case + assign $2\wr_detect$4[0:0]$10156 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \msr1__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\wr_detect$4[0:0]$10157 1'1 + case + assign $3\wr_detect$4[0:0]$10157 $2\wr_detect$4[0:0]$10156 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \d_wr11__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\wr_detect$4[0:0]$10158 1'1 + case + assign $4\wr_detect$4[0:0]$10158 $3\wr_detect$4[0:0]$10157 + end + case + assign $1\wr_detect$4[0:0]$10155 1'0 + end + sync always + update \wr_detect$4 $0\wr_detect$4[0:0]$10154 + end + attribute \src "issuer_ls180.v:163179.3-163205.6" + process $proc$issuer_ls180.v:163179$10159 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\reg$next[63:0]$10160 $4\reg$next[63:0]$10164 + attribute \src "issuer_ls180.v:163180.5-163180.29" + switch \initial + attribute \src "issuer_ls180.v:163180.9-163180.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" + switch \nia1__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\reg$next[63:0]$10161 \nia1__data_i + case + assign $1\reg$next[63:0]$10161 \reg + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" + switch \msr1__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\reg$next[63:0]$10162 \msr1__data_i + case + assign $2\reg$next[63:0]$10162 $1\reg$next[63:0]$10161 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" + switch \d_wr11__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\reg$next[63:0]$10163 \d_wr11__data_i + case + assign $3\reg$next[63:0]$10163 $2\reg$next[63:0]$10162 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\reg$next[63:0]$10164 64'0000000000000000000000000000000000000000000000000000000000000000 + case + assign $4\reg$next[63:0]$10164 $3\reg$next[63:0]$10163 + end + sync always + update \reg$next $0\reg$next[63:0]$10160 + end + connect \$1 $not$issuer_ls180.v:163031$10131_Y + connect \$3 $not$issuer_ls180.v:163032$10132_Y +end +attribute \src "issuer_ls180.v:163210.1-163681.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.cr.reg_2" +attribute \generator "nMigen" +module \reg_2 + attribute \src "issuer_ls180.v:163211.7-163211.20" + wire $0\initial[0:0] + attribute \src "issuer_ls180.v:163611.3-163650.6" + wire width 4 $0\r22__data_o$next[3:0]$10238 + attribute \src "issuer_ls180.v:163294.3-163295.39" + wire width 4 $0\r22__data_o[3:0] + attribute \src "issuer_ls180.v:163541.3-163580.6" + wire width 4 $0\r2__data_o$next[3:0]$10224 + attribute \src "issuer_ls180.v:163296.3-163297.37" + wire width 4 $0\r2__data_o[3:0] + attribute \src "issuer_ls180.v:163374.3-163400.6" + wire width 4 $0\reg$next[3:0]$10190 + attribute \src "issuer_ls180.v:163292.3-163293.25" + wire width 4 $0\reg[3:0] + attribute \src "issuer_ls180.v:163304.3-163343.6" + wire width 4 $0\src12__data_o$next[3:0]$10181 + attribute \src "issuer_ls180.v:163302.3-163303.43" + wire width 4 $0\src12__data_o[3:0] + attribute \src "issuer_ls180.v:163401.3-163440.6" + wire width 4 $0\src22__data_o$next[3:0]$10196 + attribute \src "issuer_ls180.v:163300.3-163301.43" + wire width 4 $0\src22__data_o[3:0] + attribute \src "issuer_ls180.v:163471.3-163510.6" + wire width 4 $0\src32__data_o$next[3:0]$10210 + attribute \src "issuer_ls180.v:163298.3-163299.43" + wire width 4 $0\src32__data_o[3:0] + attribute \src "issuer_ls180.v:163581.3-163610.6" + wire $0\wr_detect$10[0:0]$10232 + attribute \src "issuer_ls180.v:163651.3-163680.6" + wire $0\wr_detect$13[0:0]$10246 + attribute \src "issuer_ls180.v:163441.3-163470.6" + wire $0\wr_detect$4[0:0]$10204 + attribute \src "issuer_ls180.v:163511.3-163540.6" + wire $0\wr_detect$7[0:0]$10218 + attribute \src "issuer_ls180.v:163344.3-163373.6" + wire $0\wr_detect[0:0] + attribute \src "issuer_ls180.v:163611.3-163650.6" + wire width 4 $1\r22__data_o$next[3:0]$10239 + attribute \src "issuer_ls180.v:163236.13-163236.31" + wire width 4 $1\r22__data_o[3:0] + attribute \src "issuer_ls180.v:163541.3-163580.6" + wire width 4 $1\r2__data_o$next[3:0]$10225 + attribute \src "issuer_ls180.v:163243.13-163243.30" + wire width 4 $1\r2__data_o[3:0] + attribute \src "issuer_ls180.v:163374.3-163400.6" + wire width 4 $1\reg$next[3:0]$10191 + attribute \src "issuer_ls180.v:163249.13-163249.25" + wire width 4 $1\reg[3:0] + attribute \src "issuer_ls180.v:163304.3-163343.6" + wire width 4 $1\src12__data_o$next[3:0]$10182 + attribute \src "issuer_ls180.v:163254.13-163254.33" + wire width 4 $1\src12__data_o[3:0] + attribute \src "issuer_ls180.v:163401.3-163440.6" + wire width 4 $1\src22__data_o$next[3:0]$10197 + attribute \src "issuer_ls180.v:163261.13-163261.33" + wire width 4 $1\src22__data_o[3:0] + attribute \src "issuer_ls180.v:163471.3-163510.6" + wire width 4 $1\src32__data_o$next[3:0]$10211 + attribute \src "issuer_ls180.v:163268.13-163268.33" + wire width 4 $1\src32__data_o[3:0] + attribute \src "issuer_ls180.v:163581.3-163610.6" + wire $1\wr_detect$10[0:0]$10233 + attribute \src "issuer_ls180.v:163651.3-163680.6" + wire $1\wr_detect$13[0:0]$10247 + attribute \src "issuer_ls180.v:163441.3-163470.6" + wire $1\wr_detect$4[0:0]$10205 + attribute \src "issuer_ls180.v:163511.3-163540.6" + wire $1\wr_detect$7[0:0]$10219 + attribute \src "issuer_ls180.v:163344.3-163373.6" + wire $1\wr_detect[0:0] + attribute \src "issuer_ls180.v:163611.3-163650.6" + wire width 4 $2\r22__data_o$next[3:0]$10240 + attribute \src "issuer_ls180.v:163541.3-163580.6" + wire width 4 $2\r2__data_o$next[3:0]$10226 + attribute \src "issuer_ls180.v:163374.3-163400.6" + wire width 4 $2\reg$next[3:0]$10192 + attribute \src "issuer_ls180.v:163304.3-163343.6" + wire width 4 $2\src12__data_o$next[3:0]$10183 + attribute \src "issuer_ls180.v:163401.3-163440.6" + wire width 4 $2\src22__data_o$next[3:0]$10198 + attribute \src "issuer_ls180.v:163471.3-163510.6" + wire width 4 $2\src32__data_o$next[3:0]$10212 + attribute \src "issuer_ls180.v:163581.3-163610.6" + wire $2\wr_detect$10[0:0]$10234 + attribute \src "issuer_ls180.v:163651.3-163680.6" + wire $2\wr_detect$13[0:0]$10248 + attribute \src "issuer_ls180.v:163441.3-163470.6" + wire $2\wr_detect$4[0:0]$10206 + attribute \src "issuer_ls180.v:163511.3-163540.6" + wire $2\wr_detect$7[0:0]$10220 + attribute \src "issuer_ls180.v:163344.3-163373.6" + wire $2\wr_detect[0:0] + attribute \src "issuer_ls180.v:163611.3-163650.6" + wire width 4 $3\r22__data_o$next[3:0]$10241 + attribute \src "issuer_ls180.v:163541.3-163580.6" + wire width 4 $3\r2__data_o$next[3:0]$10227 + attribute \src "issuer_ls180.v:163374.3-163400.6" + wire width 4 $3\reg$next[3:0]$10193 + attribute \src "issuer_ls180.v:163304.3-163343.6" + wire width 4 $3\src12__data_o$next[3:0]$10184 + attribute \src "issuer_ls180.v:163401.3-163440.6" + wire width 4 $3\src22__data_o$next[3:0]$10199 + attribute \src "issuer_ls180.v:163471.3-163510.6" + wire width 4 $3\src32__data_o$next[3:0]$10213 + attribute \src "issuer_ls180.v:163581.3-163610.6" + wire $3\wr_detect$10[0:0]$10235 + attribute \src "issuer_ls180.v:163651.3-163680.6" + wire $3\wr_detect$13[0:0]$10249 + attribute \src "issuer_ls180.v:163441.3-163470.6" + wire $3\wr_detect$4[0:0]$10207 + attribute \src "issuer_ls180.v:163511.3-163540.6" + wire $3\wr_detect$7[0:0]$10221 + attribute \src "issuer_ls180.v:163344.3-163373.6" + wire $3\wr_detect[0:0] + attribute \src "issuer_ls180.v:163611.3-163650.6" + wire width 4 $4\r22__data_o$next[3:0]$10242 + attribute \src "issuer_ls180.v:163541.3-163580.6" + wire width 4 $4\r2__data_o$next[3:0]$10228 + attribute \src "issuer_ls180.v:163374.3-163400.6" + wire width 4 $4\reg$next[3:0]$10194 + attribute \src "issuer_ls180.v:163304.3-163343.6" + wire width 4 $4\src12__data_o$next[3:0]$10185 + attribute \src "issuer_ls180.v:163401.3-163440.6" + wire width 4 $4\src22__data_o$next[3:0]$10200 + attribute \src "issuer_ls180.v:163471.3-163510.6" + wire width 4 $4\src32__data_o$next[3:0]$10214 + attribute \src "issuer_ls180.v:163581.3-163610.6" + wire $4\wr_detect$10[0:0]$10236 + attribute \src "issuer_ls180.v:163651.3-163680.6" + wire $4\wr_detect$13[0:0]$10250 + attribute \src "issuer_ls180.v:163441.3-163470.6" + wire $4\wr_detect$4[0:0]$10208 + attribute \src "issuer_ls180.v:163511.3-163540.6" + wire $4\wr_detect$7[0:0]$10222 + attribute \src "issuer_ls180.v:163344.3-163373.6" + wire $4\wr_detect[0:0] + attribute \src "issuer_ls180.v:163611.3-163650.6" + wire width 4 $5\r22__data_o$next[3:0]$10243 + attribute \src "issuer_ls180.v:163541.3-163580.6" + wire width 4 $5\r2__data_o$next[3:0]$10229 + attribute \src "issuer_ls180.v:163304.3-163343.6" + wire width 4 $5\src12__data_o$next[3:0]$10186 + attribute \src "issuer_ls180.v:163401.3-163440.6" + wire width 4 $5\src22__data_o$next[3:0]$10201 + attribute \src "issuer_ls180.v:163471.3-163510.6" + wire width 4 $5\src32__data_o$next[3:0]$10215 + attribute \src "issuer_ls180.v:163611.3-163650.6" + wire width 4 $6\r22__data_o$next[3:0]$10244 + attribute \src "issuer_ls180.v:163541.3-163580.6" + wire width 4 $6\r2__data_o$next[3:0]$10230 + attribute \src "issuer_ls180.v:163304.3-163343.6" + wire width 4 $6\src12__data_o$next[3:0]$10187 + attribute \src "issuer_ls180.v:163401.3-163440.6" + wire width 4 $6\src22__data_o$next[3:0]$10202 + attribute \src "issuer_ls180.v:163471.3-163510.6" + wire width 4 $6\src32__data_o$next[3:0]$10216 + attribute \src "issuer_ls180.v:163287.17-163287.104" + wire $not$issuer_ls180.v:163287$10169_Y + attribute \src "issuer_ls180.v:163288.18-163288.105" + wire $not$issuer_ls180.v:163288$10170_Y + attribute \src "issuer_ls180.v:163289.17-163289.100" + wire $not$issuer_ls180.v:163289$10171_Y + attribute \src "issuer_ls180.v:163290.17-163290.103" + wire $not$issuer_ls180.v:163290$10172_Y + attribute \src "issuer_ls180.v:163291.17-163291.103" + wire $not$issuer_ls180.v:163291$10173_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + wire \$12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + wire \$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + wire \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" + wire input 18 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" + wire input 1 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 input 9 \dest12__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire input 8 \dest12__wen + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 input 11 \dest22__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire input 10 \dest22__wen + attribute \src "issuer_ls180.v:163211.7-163211.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 output 14 \r22__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 \r22__data_o$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire input 15 \r22__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 output 12 \r2__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 \r2__data_o$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire input 13 \r2__ren + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" + wire width 4 \reg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" + wire width 4 \reg$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 output 3 \src12__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 \src12__data_o$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire input 2 \src12__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 output 5 \src22__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 \src22__data_o$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire input 4 \src22__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 output 7 \src32__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 \src32__data_o$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire input 6 \src32__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 input 16 \w2__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire input 17 \w2__wen + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" + wire \wr_detect + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" + wire \wr_detect$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" + wire \wr_detect$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" + wire \wr_detect$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" + wire \wr_detect$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + cell $not $not$issuer_ls180.v:163287$10169 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_detect$10 + connect \Y $not$issuer_ls180.v:163287$10169_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + cell $not $not$issuer_ls180.v:163288$10170 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_detect$13 + connect \Y $not$issuer_ls180.v:163288$10170_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + cell $not $not$issuer_ls180.v:163289$10171 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_detect + connect \Y $not$issuer_ls180.v:163289$10171_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + cell $not $not$issuer_ls180.v:163290$10172 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_detect$4 + connect \Y $not$issuer_ls180.v:163290$10172_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + cell $not $not$issuer_ls180.v:163291$10173 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_detect$7 + connect \Y $not$issuer_ls180.v:163291$10173_Y + end + attribute \src "issuer_ls180.v:163211.7-163211.20" + process $proc$issuer_ls180.v:163211$10251 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "issuer_ls180.v:163236.13-163236.31" + process $proc$issuer_ls180.v:163236$10252 + assign { } { } + assign $1\r22__data_o[3:0] 4'0000 + sync always + sync init + update \r22__data_o $1\r22__data_o[3:0] + end + attribute \src "issuer_ls180.v:163243.13-163243.30" + process $proc$issuer_ls180.v:163243$10253 + assign { } { } + assign $1\r2__data_o[3:0] 4'0000 + sync always + sync init + update \r2__data_o $1\r2__data_o[3:0] + end + attribute \src "issuer_ls180.v:163249.13-163249.25" + process $proc$issuer_ls180.v:163249$10254 + assign { } { } + assign $1\reg[3:0] 4'0000 + sync always + sync init + update \reg $1\reg[3:0] + end + attribute \src "issuer_ls180.v:163254.13-163254.33" + process $proc$issuer_ls180.v:163254$10255 + assign { } { } + assign $1\src12__data_o[3:0] 4'0000 + sync always + sync init + update \src12__data_o $1\src12__data_o[3:0] + end + attribute \src "issuer_ls180.v:163261.13-163261.33" + process $proc$issuer_ls180.v:163261$10256 + assign { } { } + assign $1\src22__data_o[3:0] 4'0000 + sync always + sync init + update \src22__data_o $1\src22__data_o[3:0] + end + attribute \src "issuer_ls180.v:163268.13-163268.33" + process $proc$issuer_ls180.v:163268$10257 + assign { } { } + assign $1\src32__data_o[3:0] 4'0000 + sync always + sync init + update \src32__data_o $1\src32__data_o[3:0] + end + attribute \src "issuer_ls180.v:163292.3-163293.25" + process $proc$issuer_ls180.v:163292$10174 + assign { } { } + assign $0\reg[3:0] \reg$next + sync posedge \coresync_clk + update \reg $0\reg[3:0] + end + attribute \src "issuer_ls180.v:163294.3-163295.39" + process $proc$issuer_ls180.v:163294$10175 + assign { } { } + assign $0\r22__data_o[3:0] \r22__data_o$next + sync posedge \coresync_clk + update \r22__data_o $0\r22__data_o[3:0] + end + attribute \src "issuer_ls180.v:163296.3-163297.37" + process $proc$issuer_ls180.v:163296$10176 + assign { } { } + assign $0\r2__data_o[3:0] \r2__data_o$next + sync posedge \coresync_clk + update \r2__data_o $0\r2__data_o[3:0] + end + attribute \src "issuer_ls180.v:163298.3-163299.43" + process $proc$issuer_ls180.v:163298$10177 + assign { } { } + assign $0\src32__data_o[3:0] \src32__data_o$next + sync posedge \coresync_clk + update \src32__data_o $0\src32__data_o[3:0] + end + attribute \src "issuer_ls180.v:163300.3-163301.43" + process $proc$issuer_ls180.v:163300$10178 + assign { } { } + assign $0\src22__data_o[3:0] \src22__data_o$next + sync posedge \coresync_clk + update \src22__data_o $0\src22__data_o[3:0] + end + attribute \src "issuer_ls180.v:163302.3-163303.43" + process $proc$issuer_ls180.v:163302$10179 + assign { } { } + assign $0\src12__data_o[3:0] \src12__data_o$next + sync posedge \coresync_clk + update \src12__data_o $0\src12__data_o[3:0] + end + attribute \src "issuer_ls180.v:163304.3-163343.6" + process $proc$issuer_ls180.v:163304$10180 + assign { } { } + assign { } { } + assign { } { } + assign $0\src12__data_o$next[3:0]$10181 $6\src12__data_o$next[3:0]$10187 + attribute \src "issuer_ls180.v:163305.5-163305.29" + switch \initial + attribute \src "issuer_ls180.v:163305.9-163305.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \src12__ren + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\src12__data_o$next[3:0]$10182 $5\src12__data_o$next[3:0]$10186 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest12__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\src12__data_o$next[3:0]$10183 \dest12__data_i + case + assign $2\src12__data_o$next[3:0]$10183 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest22__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\src12__data_o$next[3:0]$10184 \dest22__data_i + case + assign $3\src12__data_o$next[3:0]$10184 $2\src12__data_o$next[3:0]$10183 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w2__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\src12__data_o$next[3:0]$10185 \w2__data_i + case + assign $4\src12__data_o$next[3:0]$10185 $3\src12__data_o$next[3:0]$10184 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + switch \$1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\src12__data_o$next[3:0]$10186 \reg + case + assign $5\src12__data_o$next[3:0]$10186 $4\src12__data_o$next[3:0]$10185 + end + case + assign $1\src12__data_o$next[3:0]$10182 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $6\src12__data_o$next[3:0]$10187 4'0000 + case + assign $6\src12__data_o$next[3:0]$10187 $1\src12__data_o$next[3:0]$10182 + end + sync always + update \src12__data_o$next $0\src12__data_o$next[3:0]$10181 + end + attribute \src "issuer_ls180.v:163344.3-163373.6" + process $proc$issuer_ls180.v:163344$10188 + assign { } { } + assign { } { } + assign $0\wr_detect[0:0] $1\wr_detect[0:0] + attribute \src "issuer_ls180.v:163345.5-163345.29" + switch \initial + attribute \src "issuer_ls180.v:163345.9-163345.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \src12__ren + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\wr_detect[0:0] $4\wr_detect[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest12__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\wr_detect[0:0] 1'1 + case + assign $2\wr_detect[0:0] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest22__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\wr_detect[0:0] 1'1 + case + assign $3\wr_detect[0:0] $2\wr_detect[0:0] + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w2__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\wr_detect[0:0] 1'1 + case + assign $4\wr_detect[0:0] $3\wr_detect[0:0] + end + case + assign $1\wr_detect[0:0] 1'0 + end + sync always + update \wr_detect $0\wr_detect[0:0] + end + attribute \src "issuer_ls180.v:163374.3-163400.6" + process $proc$issuer_ls180.v:163374$10189 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\reg$next[3:0]$10190 $4\reg$next[3:0]$10194 + attribute \src "issuer_ls180.v:163375.5-163375.29" + switch \initial + attribute \src "issuer_ls180.v:163375.9-163375.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" + switch \dest12__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\reg$next[3:0]$10191 \dest12__data_i + case + assign $1\reg$next[3:0]$10191 \reg + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" + switch \dest22__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\reg$next[3:0]$10192 \dest22__data_i + case + assign $2\reg$next[3:0]$10192 $1\reg$next[3:0]$10191 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" + switch \w2__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\reg$next[3:0]$10193 \w2__data_i + case + assign $3\reg$next[3:0]$10193 $2\reg$next[3:0]$10192 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\reg$next[3:0]$10194 4'0000 + case + assign $4\reg$next[3:0]$10194 $3\reg$next[3:0]$10193 + end + sync always + update \reg$next $0\reg$next[3:0]$10190 + end + attribute \src "issuer_ls180.v:163401.3-163440.6" + process $proc$issuer_ls180.v:163401$10195 + assign { } { } + assign { } { } + assign { } { } + assign $0\src22__data_o$next[3:0]$10196 $6\src22__data_o$next[3:0]$10202 + attribute \src "issuer_ls180.v:163402.5-163402.29" + switch \initial + attribute \src "issuer_ls180.v:163402.9-163402.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \src22__ren + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\src22__data_o$next[3:0]$10197 $5\src22__data_o$next[3:0]$10201 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest12__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\src22__data_o$next[3:0]$10198 \dest12__data_i + case + assign $2\src22__data_o$next[3:0]$10198 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest22__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\src22__data_o$next[3:0]$10199 \dest22__data_i + case + assign $3\src22__data_o$next[3:0]$10199 $2\src22__data_o$next[3:0]$10198 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w2__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\src22__data_o$next[3:0]$10200 \w2__data_i + case + assign $4\src22__data_o$next[3:0]$10200 $3\src22__data_o$next[3:0]$10199 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + switch \$3 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\src22__data_o$next[3:0]$10201 \reg + case + assign $5\src22__data_o$next[3:0]$10201 $4\src22__data_o$next[3:0]$10200 + end + case + assign $1\src22__data_o$next[3:0]$10197 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $6\src22__data_o$next[3:0]$10202 4'0000 + case + assign $6\src22__data_o$next[3:0]$10202 $1\src22__data_o$next[3:0]$10197 + end + sync always + update \src22__data_o$next $0\src22__data_o$next[3:0]$10196 + end + attribute \src "issuer_ls180.v:163441.3-163470.6" + process $proc$issuer_ls180.v:163441$10203 + assign { } { } + assign { } { } + assign $0\wr_detect$4[0:0]$10204 $1\wr_detect$4[0:0]$10205 + attribute \src "issuer_ls180.v:163442.5-163442.29" + switch \initial + attribute \src "issuer_ls180.v:163442.9-163442.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \src22__ren + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\wr_detect$4[0:0]$10205 $4\wr_detect$4[0:0]$10208 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest12__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\wr_detect$4[0:0]$10206 1'1 + case + assign $2\wr_detect$4[0:0]$10206 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest22__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\wr_detect$4[0:0]$10207 1'1 + case + assign $3\wr_detect$4[0:0]$10207 $2\wr_detect$4[0:0]$10206 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w2__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\wr_detect$4[0:0]$10208 1'1 + case + assign $4\wr_detect$4[0:0]$10208 $3\wr_detect$4[0:0]$10207 + end + case + assign $1\wr_detect$4[0:0]$10205 1'0 + end + sync always + update \wr_detect$4 $0\wr_detect$4[0:0]$10204 + end + attribute \src "issuer_ls180.v:163471.3-163510.6" + process $proc$issuer_ls180.v:163471$10209 + assign { } { } + assign { } { } + assign { } { } + assign $0\src32__data_o$next[3:0]$10210 $6\src32__data_o$next[3:0]$10216 + attribute \src "issuer_ls180.v:163472.5-163472.29" + switch \initial + attribute \src "issuer_ls180.v:163472.9-163472.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \src32__ren + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\src32__data_o$next[3:0]$10211 $5\src32__data_o$next[3:0]$10215 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest12__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\src32__data_o$next[3:0]$10212 \dest12__data_i + case + assign $2\src32__data_o$next[3:0]$10212 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest22__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\src32__data_o$next[3:0]$10213 \dest22__data_i + case + assign $3\src32__data_o$next[3:0]$10213 $2\src32__data_o$next[3:0]$10212 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w2__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\src32__data_o$next[3:0]$10214 \w2__data_i + case + assign $4\src32__data_o$next[3:0]$10214 $3\src32__data_o$next[3:0]$10213 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + switch \$6 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\src32__data_o$next[3:0]$10215 \reg + case + assign $5\src32__data_o$next[3:0]$10215 $4\src32__data_o$next[3:0]$10214 + end + case + assign $1\src32__data_o$next[3:0]$10211 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $6\src32__data_o$next[3:0]$10216 4'0000 + case + assign $6\src32__data_o$next[3:0]$10216 $1\src32__data_o$next[3:0]$10211 + end + sync always + update \src32__data_o$next $0\src32__data_o$next[3:0]$10210 + end + attribute \src "issuer_ls180.v:163511.3-163540.6" + process $proc$issuer_ls180.v:163511$10217 + assign { } { } + assign { } { } + assign $0\wr_detect$7[0:0]$10218 $1\wr_detect$7[0:0]$10219 + attribute \src "issuer_ls180.v:163512.5-163512.29" + switch \initial + attribute \src "issuer_ls180.v:163512.9-163512.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \src32__ren + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\wr_detect$7[0:0]$10219 $4\wr_detect$7[0:0]$10222 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest12__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\wr_detect$7[0:0]$10220 1'1 + case + assign $2\wr_detect$7[0:0]$10220 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest22__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\wr_detect$7[0:0]$10221 1'1 + case + assign $3\wr_detect$7[0:0]$10221 $2\wr_detect$7[0:0]$10220 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w2__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\wr_detect$7[0:0]$10222 1'1 + case + assign $4\wr_detect$7[0:0]$10222 $3\wr_detect$7[0:0]$10221 + end + case + assign $1\wr_detect$7[0:0]$10219 1'0 + end + sync always + update \wr_detect$7 $0\wr_detect$7[0:0]$10218 + end + attribute \src "issuer_ls180.v:163541.3-163580.6" + process $proc$issuer_ls180.v:163541$10223 + assign { } { } + assign { } { } + assign { } { } + assign $0\r2__data_o$next[3:0]$10224 $6\r2__data_o$next[3:0]$10230 + attribute \src "issuer_ls180.v:163542.5-163542.29" + switch \initial + attribute \src "issuer_ls180.v:163542.9-163542.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \r2__ren + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\r2__data_o$next[3:0]$10225 $5\r2__data_o$next[3:0]$10229 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest12__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\r2__data_o$next[3:0]$10226 \dest12__data_i + case + assign $2\r2__data_o$next[3:0]$10226 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest22__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\r2__data_o$next[3:0]$10227 \dest22__data_i + case + assign $3\r2__data_o$next[3:0]$10227 $2\r2__data_o$next[3:0]$10226 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w2__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\r2__data_o$next[3:0]$10228 \w2__data_i + case + assign $4\r2__data_o$next[3:0]$10228 $3\r2__data_o$next[3:0]$10227 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + switch \$9 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\r2__data_o$next[3:0]$10229 \reg + case + assign $5\r2__data_o$next[3:0]$10229 $4\r2__data_o$next[3:0]$10228 + end + case + assign $1\r2__data_o$next[3:0]$10225 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $6\r2__data_o$next[3:0]$10230 4'0000 + case + assign $6\r2__data_o$next[3:0]$10230 $1\r2__data_o$next[3:0]$10225 + end + sync always + update \r2__data_o$next $0\r2__data_o$next[3:0]$10224 + end + attribute \src "issuer_ls180.v:163581.3-163610.6" + process $proc$issuer_ls180.v:163581$10231 + assign { } { } + assign { } { } + assign $0\wr_detect$10[0:0]$10232 $1\wr_detect$10[0:0]$10233 + attribute \src "issuer_ls180.v:163582.5-163582.29" + switch \initial + attribute \src "issuer_ls180.v:163582.9-163582.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \r2__ren + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\wr_detect$10[0:0]$10233 $4\wr_detect$10[0:0]$10236 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest12__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\wr_detect$10[0:0]$10234 1'1 + case + assign $2\wr_detect$10[0:0]$10234 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest22__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\wr_detect$10[0:0]$10235 1'1 + case + assign $3\wr_detect$10[0:0]$10235 $2\wr_detect$10[0:0]$10234 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w2__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\wr_detect$10[0:0]$10236 1'1 + case + assign $4\wr_detect$10[0:0]$10236 $3\wr_detect$10[0:0]$10235 + end + case + assign $1\wr_detect$10[0:0]$10233 1'0 + end + sync always + update \wr_detect$10 $0\wr_detect$10[0:0]$10232 + end + attribute \src "issuer_ls180.v:163611.3-163650.6" + process $proc$issuer_ls180.v:163611$10237 + assign { } { } + assign { } { } + assign { } { } + assign $0\r22__data_o$next[3:0]$10238 $6\r22__data_o$next[3:0]$10244 + attribute \src "issuer_ls180.v:163612.5-163612.29" + switch \initial + attribute \src "issuer_ls180.v:163612.9-163612.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \r22__ren + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\r22__data_o$next[3:0]$10239 $5\r22__data_o$next[3:0]$10243 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest12__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\r22__data_o$next[3:0]$10240 \dest12__data_i + case + assign $2\r22__data_o$next[3:0]$10240 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest22__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\r22__data_o$next[3:0]$10241 \dest22__data_i + case + assign $3\r22__data_o$next[3:0]$10241 $2\r22__data_o$next[3:0]$10240 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w2__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\r22__data_o$next[3:0]$10242 \w2__data_i + case + assign $4\r22__data_o$next[3:0]$10242 $3\r22__data_o$next[3:0]$10241 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + switch \$12 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\r22__data_o$next[3:0]$10243 \reg + case + assign $5\r22__data_o$next[3:0]$10243 $4\r22__data_o$next[3:0]$10242 + end + case + assign $1\r22__data_o$next[3:0]$10239 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $6\r22__data_o$next[3:0]$10244 4'0000 + case + assign $6\r22__data_o$next[3:0]$10244 $1\r22__data_o$next[3:0]$10239 + end + sync always + update \r22__data_o$next $0\r22__data_o$next[3:0]$10238 + end + attribute \src "issuer_ls180.v:163651.3-163680.6" + process $proc$issuer_ls180.v:163651$10245 + assign { } { } + assign { } { } + assign $0\wr_detect$13[0:0]$10246 $1\wr_detect$13[0:0]$10247 + attribute \src "issuer_ls180.v:163652.5-163652.29" + switch \initial + attribute \src "issuer_ls180.v:163652.9-163652.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \r22__ren + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\wr_detect$13[0:0]$10247 $4\wr_detect$13[0:0]$10250 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest12__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\wr_detect$13[0:0]$10248 1'1 + case + assign $2\wr_detect$13[0:0]$10248 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest22__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\wr_detect$13[0:0]$10249 1'1 + case + assign $3\wr_detect$13[0:0]$10249 $2\wr_detect$13[0:0]$10248 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w2__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\wr_detect$13[0:0]$10250 1'1 + case + assign $4\wr_detect$13[0:0]$10250 $3\wr_detect$13[0:0]$10249 + end + case + assign $1\wr_detect$13[0:0]$10247 1'0 + end + sync always + update \wr_detect$13 $0\wr_detect$13[0:0]$10246 + end + connect \$9 $not$issuer_ls180.v:163287$10169_Y + connect \$12 $not$issuer_ls180.v:163288$10170_Y + connect \$1 $not$issuer_ls180.v:163289$10171_Y + connect \$3 $not$issuer_ls180.v:163290$10172_Y + connect \$6 $not$issuer_ls180.v:163291$10173_Y +end +attribute \src "issuer_ls180.v:163685.1-164130.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.xer.reg_2" +attribute \generator "nMigen" +module \reg_2$131 + attribute \src "issuer_ls180.v:163686.7-163686.20" + wire $0\initial[0:0] + attribute \src "issuer_ls180.v:164015.3-164060.6" + wire width 2 $0\r2__data_o$next[1:0]$10310 + attribute \src "issuer_ls180.v:163761.3-163762.37" + wire width 2 $0\r2__data_o[1:0] + attribute \src "issuer_ls180.v:164097.3-164129.6" + wire width 2 $0\reg$next[1:0]$10326 + attribute \src "issuer_ls180.v:163759.3-163760.25" + wire width 2 $0\reg[1:0] + attribute \src "issuer_ls180.v:163769.3-163814.6" + wire width 2 $0\src12__data_o$next[1:0]$10268 + attribute \src "issuer_ls180.v:163767.3-163768.43" + wire width 2 $0\src12__data_o[1:0] + attribute \src "issuer_ls180.v:163851.3-163896.6" + wire width 2 $0\src22__data_o$next[1:0]$10278 + attribute \src "issuer_ls180.v:163765.3-163766.43" + wire width 2 $0\src22__data_o[1:0] + attribute \src "issuer_ls180.v:163933.3-163978.6" + wire width 2 $0\src32__data_o$next[1:0]$10294 + attribute \src "issuer_ls180.v:163763.3-163764.43" + wire width 2 $0\src32__data_o[1:0] + attribute \src "issuer_ls180.v:164061.3-164096.6" + wire $0\wr_detect$10[0:0]$10319 + attribute \src "issuer_ls180.v:163897.3-163932.6" + wire $0\wr_detect$4[0:0]$10287 + attribute \src "issuer_ls180.v:163979.3-164014.6" + wire $0\wr_detect$7[0:0]$10303 + attribute \src "issuer_ls180.v:163815.3-163850.6" + wire $0\wr_detect[0:0] + attribute \src "issuer_ls180.v:164015.3-164060.6" + wire width 2 $1\r2__data_o$next[1:0]$10311 + attribute \src "issuer_ls180.v:163713.13-163713.30" + wire width 2 $1\r2__data_o[1:0] + attribute \src "issuer_ls180.v:164097.3-164129.6" + wire width 2 $1\reg$next[1:0]$10327 + attribute \src "issuer_ls180.v:163719.13-163719.25" + wire width 2 $1\reg[1:0] + attribute \src "issuer_ls180.v:163769.3-163814.6" + wire width 2 $1\src12__data_o$next[1:0]$10269 + attribute \src "issuer_ls180.v:163724.13-163724.33" + wire width 2 $1\src12__data_o[1:0] + attribute \src "issuer_ls180.v:163851.3-163896.6" + wire width 2 $1\src22__data_o$next[1:0]$10279 + attribute \src "issuer_ls180.v:163731.13-163731.33" + wire width 2 $1\src22__data_o[1:0] + attribute \src "issuer_ls180.v:163933.3-163978.6" + wire width 2 $1\src32__data_o$next[1:0]$10295 + attribute \src "issuer_ls180.v:163738.13-163738.33" + wire width 2 $1\src32__data_o[1:0] + attribute \src "issuer_ls180.v:164061.3-164096.6" + wire $1\wr_detect$10[0:0]$10320 + attribute \src "issuer_ls180.v:163897.3-163932.6" + wire $1\wr_detect$4[0:0]$10288 + attribute \src "issuer_ls180.v:163979.3-164014.6" + wire $1\wr_detect$7[0:0]$10304 + attribute \src "issuer_ls180.v:163815.3-163850.6" + wire $1\wr_detect[0:0] + attribute \src "issuer_ls180.v:164015.3-164060.6" + wire width 2 $2\r2__data_o$next[1:0]$10312 + attribute \src "issuer_ls180.v:164097.3-164129.6" + wire width 2 $2\reg$next[1:0]$10328 + attribute \src "issuer_ls180.v:163769.3-163814.6" + wire width 2 $2\src12__data_o$next[1:0]$10270 + attribute \src "issuer_ls180.v:163851.3-163896.6" + wire width 2 $2\src22__data_o$next[1:0]$10280 + attribute \src "issuer_ls180.v:163933.3-163978.6" + wire width 2 $2\src32__data_o$next[1:0]$10296 + attribute \src "issuer_ls180.v:164061.3-164096.6" + wire $2\wr_detect$10[0:0]$10321 + attribute \src "issuer_ls180.v:163897.3-163932.6" + wire $2\wr_detect$4[0:0]$10289 + attribute \src "issuer_ls180.v:163979.3-164014.6" + wire $2\wr_detect$7[0:0]$10305 + attribute \src "issuer_ls180.v:163815.3-163850.6" + wire $2\wr_detect[0:0] + attribute \src "issuer_ls180.v:164015.3-164060.6" + wire width 2 $3\r2__data_o$next[1:0]$10313 + attribute \src "issuer_ls180.v:164097.3-164129.6" + wire width 2 $3\reg$next[1:0]$10329 + attribute \src "issuer_ls180.v:163769.3-163814.6" + wire width 2 $3\src12__data_o$next[1:0]$10271 + attribute \src "issuer_ls180.v:163851.3-163896.6" + wire width 2 $3\src22__data_o$next[1:0]$10281 + attribute \src "issuer_ls180.v:163933.3-163978.6" + wire width 2 $3\src32__data_o$next[1:0]$10297 + attribute \src "issuer_ls180.v:164061.3-164096.6" + wire $3\wr_detect$10[0:0]$10322 + attribute \src "issuer_ls180.v:163897.3-163932.6" + wire $3\wr_detect$4[0:0]$10290 + attribute \src "issuer_ls180.v:163979.3-164014.6" + wire $3\wr_detect$7[0:0]$10306 + attribute \src "issuer_ls180.v:163815.3-163850.6" + wire $3\wr_detect[0:0] + attribute \src "issuer_ls180.v:164015.3-164060.6" + wire width 2 $4\r2__data_o$next[1:0]$10314 + attribute \src "issuer_ls180.v:164097.3-164129.6" + wire width 2 $4\reg$next[1:0]$10330 + attribute \src "issuer_ls180.v:163769.3-163814.6" + wire width 2 $4\src12__data_o$next[1:0]$10272 + attribute \src "issuer_ls180.v:163851.3-163896.6" + wire width 2 $4\src22__data_o$next[1:0]$10282 + attribute \src "issuer_ls180.v:163933.3-163978.6" + wire width 2 $4\src32__data_o$next[1:0]$10298 + attribute \src "issuer_ls180.v:164061.3-164096.6" + wire $4\wr_detect$10[0:0]$10323 + attribute \src "issuer_ls180.v:163897.3-163932.6" + wire $4\wr_detect$4[0:0]$10291 + attribute \src "issuer_ls180.v:163979.3-164014.6" + wire $4\wr_detect$7[0:0]$10307 + attribute \src "issuer_ls180.v:163815.3-163850.6" + wire $4\wr_detect[0:0] + attribute \src "issuer_ls180.v:164015.3-164060.6" + wire width 2 $5\r2__data_o$next[1:0]$10315 + attribute \src "issuer_ls180.v:164097.3-164129.6" + wire width 2 $5\reg$next[1:0]$10331 + attribute \src "issuer_ls180.v:163769.3-163814.6" + wire width 2 $5\src12__data_o$next[1:0]$10273 + attribute \src "issuer_ls180.v:163851.3-163896.6" + wire width 2 $5\src22__data_o$next[1:0]$10283 + attribute \src "issuer_ls180.v:163933.3-163978.6" + wire width 2 $5\src32__data_o$next[1:0]$10299 + attribute \src "issuer_ls180.v:164061.3-164096.6" + wire $5\wr_detect$10[0:0]$10324 + attribute \src "issuer_ls180.v:163897.3-163932.6" + wire $5\wr_detect$4[0:0]$10292 + attribute \src "issuer_ls180.v:163979.3-164014.6" + wire $5\wr_detect$7[0:0]$10308 + attribute \src "issuer_ls180.v:163815.3-163850.6" + wire $5\wr_detect[0:0] + attribute \src "issuer_ls180.v:164015.3-164060.6" + wire width 2 $6\r2__data_o$next[1:0]$10316 + attribute \src "issuer_ls180.v:163769.3-163814.6" + wire width 2 $6\src12__data_o$next[1:0]$10274 + attribute \src "issuer_ls180.v:163851.3-163896.6" + wire width 2 $6\src22__data_o$next[1:0]$10284 + attribute \src "issuer_ls180.v:163933.3-163978.6" + wire width 2 $6\src32__data_o$next[1:0]$10300 + attribute \src "issuer_ls180.v:164015.3-164060.6" + wire width 2 $7\r2__data_o$next[1:0]$10317 + attribute \src "issuer_ls180.v:163769.3-163814.6" + wire width 2 $7\src12__data_o$next[1:0]$10275 + attribute \src "issuer_ls180.v:163851.3-163896.6" + wire width 2 $7\src22__data_o$next[1:0]$10285 + attribute \src "issuer_ls180.v:163933.3-163978.6" + wire width 2 $7\src32__data_o$next[1:0]$10301 + attribute \src "issuer_ls180.v:163755.17-163755.104" + wire $not$issuer_ls180.v:163755$10258_Y + attribute \src "issuer_ls180.v:163756.17-163756.100" + wire $not$issuer_ls180.v:163756$10259_Y + attribute \src "issuer_ls180.v:163757.17-163757.103" + wire $not$issuer_ls180.v:163757$10260_Y + attribute \src "issuer_ls180.v:163758.17-163758.103" + wire $not$issuer_ls180.v:163758$10261_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + wire \$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + wire \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" + wire input 18 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" + wire input 1 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 2 input 9 \dest12__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire input 8 \dest12__wen + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 2 input 11 \dest22__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire input 10 \dest22__wen + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 2 input 13 \dest32__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire input 12 \dest32__wen + attribute \src "issuer_ls180.v:163686.7-163686.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 2 output 14 \r2__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 2 \r2__data_o$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire input 15 \r2__ren + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" + wire width 2 \reg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" + wire width 2 \reg$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 2 output 3 \src12__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 2 \src12__data_o$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire input 2 \src12__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 2 output 5 \src22__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 2 \src22__data_o$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire input 4 \src22__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 2 output 7 \src32__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 2 \src32__data_o$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire input 6 \src32__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 2 input 16 \w2__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire input 17 \w2__wen + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" + wire \wr_detect + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" + wire \wr_detect$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" + wire \wr_detect$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" + wire \wr_detect$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + cell $not $not$issuer_ls180.v:163755$10258 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_detect$10 + connect \Y $not$issuer_ls180.v:163755$10258_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + cell $not $not$issuer_ls180.v:163756$10259 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_detect + connect \Y $not$issuer_ls180.v:163756$10259_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + cell $not $not$issuer_ls180.v:163757$10260 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_detect$4 + connect \Y $not$issuer_ls180.v:163757$10260_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + cell $not $not$issuer_ls180.v:163758$10261 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_detect$7 + connect \Y $not$issuer_ls180.v:163758$10261_Y + end + attribute \src "issuer_ls180.v:163686.7-163686.20" + process $proc$issuer_ls180.v:163686$10332 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "issuer_ls180.v:163713.13-163713.30" + process $proc$issuer_ls180.v:163713$10333 + assign { } { } + assign $1\r2__data_o[1:0] 2'00 + sync always + sync init + update \r2__data_o $1\r2__data_o[1:0] + end + attribute \src "issuer_ls180.v:163719.13-163719.25" + process $proc$issuer_ls180.v:163719$10334 + assign { } { } + assign $1\reg[1:0] 2'00 + sync always + sync init + update \reg $1\reg[1:0] + end + attribute \src "issuer_ls180.v:163724.13-163724.33" + process $proc$issuer_ls180.v:163724$10335 + assign { } { } + assign $1\src12__data_o[1:0] 2'00 + sync always + sync init + update \src12__data_o $1\src12__data_o[1:0] + end + attribute \src "issuer_ls180.v:163731.13-163731.33" + process $proc$issuer_ls180.v:163731$10336 + assign { } { } + assign $1\src22__data_o[1:0] 2'00 + sync always + sync init + update \src22__data_o $1\src22__data_o[1:0] + end + attribute \src "issuer_ls180.v:163738.13-163738.33" + process $proc$issuer_ls180.v:163738$10337 + assign { } { } + assign $1\src32__data_o[1:0] 2'00 + sync always + sync init + update \src32__data_o $1\src32__data_o[1:0] + end + attribute \src "issuer_ls180.v:163759.3-163760.25" + process $proc$issuer_ls180.v:163759$10262 + assign { } { } + assign $0\reg[1:0] \reg$next + sync posedge \coresync_clk + update \reg $0\reg[1:0] + end + attribute \src "issuer_ls180.v:163761.3-163762.37" + process $proc$issuer_ls180.v:163761$10263 + assign { } { } + assign $0\r2__data_o[1:0] \r2__data_o$next + sync posedge \coresync_clk + update \r2__data_o $0\r2__data_o[1:0] + end + attribute \src "issuer_ls180.v:163763.3-163764.43" + process $proc$issuer_ls180.v:163763$10264 + assign { } { } + assign $0\src32__data_o[1:0] \src32__data_o$next + sync posedge \coresync_clk + update \src32__data_o $0\src32__data_o[1:0] + end + attribute \src "issuer_ls180.v:163765.3-163766.43" + process $proc$issuer_ls180.v:163765$10265 + assign { } { } + assign $0\src22__data_o[1:0] \src22__data_o$next + sync posedge \coresync_clk + update \src22__data_o $0\src22__data_o[1:0] + end + attribute \src "issuer_ls180.v:163767.3-163768.43" + process $proc$issuer_ls180.v:163767$10266 + assign { } { } + assign $0\src12__data_o[1:0] \src12__data_o$next + sync posedge \coresync_clk + update \src12__data_o $0\src12__data_o[1:0] + end + attribute \src "issuer_ls180.v:163769.3-163814.6" + process $proc$issuer_ls180.v:163769$10267 + assign { } { } + assign { } { } + assign { } { } + assign $0\src12__data_o$next[1:0]$10268 $7\src12__data_o$next[1:0]$10275 + attribute \src "issuer_ls180.v:163770.5-163770.29" + switch \initial + attribute \src "issuer_ls180.v:163770.9-163770.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \src12__ren + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\src12__data_o$next[1:0]$10269 $6\src12__data_o$next[1:0]$10274 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest12__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\src12__data_o$next[1:0]$10270 \dest12__data_i + case + assign $2\src12__data_o$next[1:0]$10270 2'00 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest22__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\src12__data_o$next[1:0]$10271 \dest22__data_i + case + assign $3\src12__data_o$next[1:0]$10271 $2\src12__data_o$next[1:0]$10270 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest32__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\src12__data_o$next[1:0]$10272 \dest32__data_i + case + assign $4\src12__data_o$next[1:0]$10272 $3\src12__data_o$next[1:0]$10271 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w2__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\src12__data_o$next[1:0]$10273 \w2__data_i + case + assign $5\src12__data_o$next[1:0]$10273 $4\src12__data_o$next[1:0]$10272 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + switch \$1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $6\src12__data_o$next[1:0]$10274 \reg + case + assign $6\src12__data_o$next[1:0]$10274 $5\src12__data_o$next[1:0]$10273 + end + case + assign $1\src12__data_o$next[1:0]$10269 2'00 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $7\src12__data_o$next[1:0]$10275 2'00 + case + assign $7\src12__data_o$next[1:0]$10275 $1\src12__data_o$next[1:0]$10269 + end + sync always + update \src12__data_o$next $0\src12__data_o$next[1:0]$10268 + end + attribute \src "issuer_ls180.v:163815.3-163850.6" + process $proc$issuer_ls180.v:163815$10276 + assign { } { } + assign { } { } + assign $0\wr_detect[0:0] $1\wr_detect[0:0] + attribute \src "issuer_ls180.v:163816.5-163816.29" + switch \initial + attribute \src "issuer_ls180.v:163816.9-163816.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \src12__ren + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\wr_detect[0:0] $5\wr_detect[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest12__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\wr_detect[0:0] 1'1 + case + assign $2\wr_detect[0:0] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest22__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\wr_detect[0:0] 1'1 + case + assign $3\wr_detect[0:0] $2\wr_detect[0:0] + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest32__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\wr_detect[0:0] 1'1 + case + assign $4\wr_detect[0:0] $3\wr_detect[0:0] + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w2__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\wr_detect[0:0] 1'1 + case + assign $5\wr_detect[0:0] $4\wr_detect[0:0] + end + case + assign $1\wr_detect[0:0] 1'0 + end + sync always + update \wr_detect $0\wr_detect[0:0] + end + attribute \src "issuer_ls180.v:163851.3-163896.6" + process $proc$issuer_ls180.v:163851$10277 + assign { } { } + assign { } { } + assign { } { } + assign $0\src22__data_o$next[1:0]$10278 $7\src22__data_o$next[1:0]$10285 + attribute \src "issuer_ls180.v:163852.5-163852.29" + switch \initial + attribute \src "issuer_ls180.v:163852.9-163852.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \src22__ren + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\src22__data_o$next[1:0]$10279 $6\src22__data_o$next[1:0]$10284 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest12__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\src22__data_o$next[1:0]$10280 \dest12__data_i + case + assign $2\src22__data_o$next[1:0]$10280 2'00 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest22__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\src22__data_o$next[1:0]$10281 \dest22__data_i + case + assign $3\src22__data_o$next[1:0]$10281 $2\src22__data_o$next[1:0]$10280 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest32__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\src22__data_o$next[1:0]$10282 \dest32__data_i + case + assign $4\src22__data_o$next[1:0]$10282 $3\src22__data_o$next[1:0]$10281 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w2__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\src22__data_o$next[1:0]$10283 \w2__data_i + case + assign $5\src22__data_o$next[1:0]$10283 $4\src22__data_o$next[1:0]$10282 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + switch \$3 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $6\src22__data_o$next[1:0]$10284 \reg + case + assign $6\src22__data_o$next[1:0]$10284 $5\src22__data_o$next[1:0]$10283 + end + case + assign $1\src22__data_o$next[1:0]$10279 2'00 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $7\src22__data_o$next[1:0]$10285 2'00 + case + assign $7\src22__data_o$next[1:0]$10285 $1\src22__data_o$next[1:0]$10279 + end + sync always + update \src22__data_o$next $0\src22__data_o$next[1:0]$10278 + end + attribute \src "issuer_ls180.v:163897.3-163932.6" + process $proc$issuer_ls180.v:163897$10286 + assign { } { } + assign { } { } + assign $0\wr_detect$4[0:0]$10287 $1\wr_detect$4[0:0]$10288 + attribute \src "issuer_ls180.v:163898.5-163898.29" + switch \initial + attribute \src "issuer_ls180.v:163898.9-163898.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \src22__ren + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\wr_detect$4[0:0]$10288 $5\wr_detect$4[0:0]$10292 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest12__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\wr_detect$4[0:0]$10289 1'1 + case + assign $2\wr_detect$4[0:0]$10289 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest22__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\wr_detect$4[0:0]$10290 1'1 + case + assign $3\wr_detect$4[0:0]$10290 $2\wr_detect$4[0:0]$10289 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest32__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\wr_detect$4[0:0]$10291 1'1 + case + assign $4\wr_detect$4[0:0]$10291 $3\wr_detect$4[0:0]$10290 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w2__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\wr_detect$4[0:0]$10292 1'1 + case + assign $5\wr_detect$4[0:0]$10292 $4\wr_detect$4[0:0]$10291 + end + case + assign $1\wr_detect$4[0:0]$10288 1'0 + end + sync always + update \wr_detect$4 $0\wr_detect$4[0:0]$10287 + end + attribute \src "issuer_ls180.v:163933.3-163978.6" + process $proc$issuer_ls180.v:163933$10293 + assign { } { } + assign { } { } + assign { } { } + assign $0\src32__data_o$next[1:0]$10294 $7\src32__data_o$next[1:0]$10301 + attribute \src "issuer_ls180.v:163934.5-163934.29" + switch \initial + attribute \src "issuer_ls180.v:163934.9-163934.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \src32__ren + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\src32__data_o$next[1:0]$10295 $6\src32__data_o$next[1:0]$10300 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest12__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\src32__data_o$next[1:0]$10296 \dest12__data_i + case + assign $2\src32__data_o$next[1:0]$10296 2'00 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest22__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\src32__data_o$next[1:0]$10297 \dest22__data_i + case + assign $3\src32__data_o$next[1:0]$10297 $2\src32__data_o$next[1:0]$10296 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest32__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\src32__data_o$next[1:0]$10298 \dest32__data_i + case + assign $4\src32__data_o$next[1:0]$10298 $3\src32__data_o$next[1:0]$10297 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w2__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\src32__data_o$next[1:0]$10299 \w2__data_i + case + assign $5\src32__data_o$next[1:0]$10299 $4\src32__data_o$next[1:0]$10298 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + switch \$6 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $6\src32__data_o$next[1:0]$10300 \reg + case + assign $6\src32__data_o$next[1:0]$10300 $5\src32__data_o$next[1:0]$10299 + end + case + assign $1\src32__data_o$next[1:0]$10295 2'00 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $7\src32__data_o$next[1:0]$10301 2'00 + case + assign $7\src32__data_o$next[1:0]$10301 $1\src32__data_o$next[1:0]$10295 + end + sync always + update \src32__data_o$next $0\src32__data_o$next[1:0]$10294 + end + attribute \src "issuer_ls180.v:163979.3-164014.6" + process $proc$issuer_ls180.v:163979$10302 + assign { } { } + assign { } { } + assign $0\wr_detect$7[0:0]$10303 $1\wr_detect$7[0:0]$10304 + attribute \src "issuer_ls180.v:163980.5-163980.29" + switch \initial + attribute \src "issuer_ls180.v:163980.9-163980.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \src32__ren + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\wr_detect$7[0:0]$10304 $5\wr_detect$7[0:0]$10308 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest12__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\wr_detect$7[0:0]$10305 1'1 + case + assign $2\wr_detect$7[0:0]$10305 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest22__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\wr_detect$7[0:0]$10306 1'1 + case + assign $3\wr_detect$7[0:0]$10306 $2\wr_detect$7[0:0]$10305 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest32__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\wr_detect$7[0:0]$10307 1'1 + case + assign $4\wr_detect$7[0:0]$10307 $3\wr_detect$7[0:0]$10306 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w2__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\wr_detect$7[0:0]$10308 1'1 + case + assign $5\wr_detect$7[0:0]$10308 $4\wr_detect$7[0:0]$10307 + end + case + assign $1\wr_detect$7[0:0]$10304 1'0 + end + sync always + update \wr_detect$7 $0\wr_detect$7[0:0]$10303 + end + attribute \src "issuer_ls180.v:164015.3-164060.6" + process $proc$issuer_ls180.v:164015$10309 + assign { } { } + assign { } { } + assign { } { } + assign $0\r2__data_o$next[1:0]$10310 $7\r2__data_o$next[1:0]$10317 + attribute \src "issuer_ls180.v:164016.5-164016.29" + switch \initial + attribute \src "issuer_ls180.v:164016.9-164016.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \r2__ren + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\r2__data_o$next[1:0]$10311 $6\r2__data_o$next[1:0]$10316 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest12__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\r2__data_o$next[1:0]$10312 \dest12__data_i + case + assign $2\r2__data_o$next[1:0]$10312 2'00 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest22__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\r2__data_o$next[1:0]$10313 \dest22__data_i + case + assign $3\r2__data_o$next[1:0]$10313 $2\r2__data_o$next[1:0]$10312 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest32__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\r2__data_o$next[1:0]$10314 \dest32__data_i + case + assign $4\r2__data_o$next[1:0]$10314 $3\r2__data_o$next[1:0]$10313 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w2__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\r2__data_o$next[1:0]$10315 \w2__data_i + case + assign $5\r2__data_o$next[1:0]$10315 $4\r2__data_o$next[1:0]$10314 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + switch \$9 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $6\r2__data_o$next[1:0]$10316 \reg + case + assign $6\r2__data_o$next[1:0]$10316 $5\r2__data_o$next[1:0]$10315 + end + case + assign $1\r2__data_o$next[1:0]$10311 2'00 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $7\r2__data_o$next[1:0]$10317 2'00 + case + assign $7\r2__data_o$next[1:0]$10317 $1\r2__data_o$next[1:0]$10311 + end + sync always + update \r2__data_o$next $0\r2__data_o$next[1:0]$10310 + end + attribute \src "issuer_ls180.v:164061.3-164096.6" + process $proc$issuer_ls180.v:164061$10318 + assign { } { } + assign { } { } + assign $0\wr_detect$10[0:0]$10319 $1\wr_detect$10[0:0]$10320 + attribute \src "issuer_ls180.v:164062.5-164062.29" + switch \initial + attribute \src "issuer_ls180.v:164062.9-164062.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \r2__ren + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\wr_detect$10[0:0]$10320 $5\wr_detect$10[0:0]$10324 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest12__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\wr_detect$10[0:0]$10321 1'1 + case + assign $2\wr_detect$10[0:0]$10321 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest22__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\wr_detect$10[0:0]$10322 1'1 + case + assign $3\wr_detect$10[0:0]$10322 $2\wr_detect$10[0:0]$10321 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest32__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\wr_detect$10[0:0]$10323 1'1 + case + assign $4\wr_detect$10[0:0]$10323 $3\wr_detect$10[0:0]$10322 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w2__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\wr_detect$10[0:0]$10324 1'1 + case + assign $5\wr_detect$10[0:0]$10324 $4\wr_detect$10[0:0]$10323 + end + case + assign $1\wr_detect$10[0:0]$10320 1'0 + end + sync always + update \wr_detect$10 $0\wr_detect$10[0:0]$10319 + end + attribute \src "issuer_ls180.v:164097.3-164129.6" + process $proc$issuer_ls180.v:164097$10325 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\reg$next[1:0]$10326 $5\reg$next[1:0]$10331 + attribute \src "issuer_ls180.v:164098.5-164098.29" + switch \initial + attribute \src "issuer_ls180.v:164098.9-164098.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" + switch \dest12__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\reg$next[1:0]$10327 \dest12__data_i + case + assign $1\reg$next[1:0]$10327 \reg + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" + switch \dest22__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\reg$next[1:0]$10328 \dest22__data_i + case + assign $2\reg$next[1:0]$10328 $1\reg$next[1:0]$10327 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" + switch \dest32__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\reg$next[1:0]$10329 \dest32__data_i + case + assign $3\reg$next[1:0]$10329 $2\reg$next[1:0]$10328 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" + switch \w2__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\reg$next[1:0]$10330 \w2__data_i + case + assign $4\reg$next[1:0]$10330 $3\reg$next[1:0]$10329 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\reg$next[1:0]$10331 2'00 + case + assign $5\reg$next[1:0]$10331 $4\reg$next[1:0]$10330 + end + sync always + update \reg$next $0\reg$next[1:0]$10326 + end + connect \$9 $not$issuer_ls180.v:163755$10258_Y + connect \$1 $not$issuer_ls180.v:163756$10259_Y + connect \$3 $not$issuer_ls180.v:163757$10260_Y + connect \$6 $not$issuer_ls180.v:163758$10261_Y +end +attribute \src "issuer_ls180.v:164134.1-164353.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.state.reg_2" +attribute \generator "nMigen" +module \reg_2$134 + attribute \src "issuer_ls180.v:164186.3-164225.6" + wire width 64 $0\cia2__data_o$next[63:0]$10344 + attribute \src "issuer_ls180.v:164184.3-164185.41" + wire width 64 $0\cia2__data_o[63:0] + attribute \src "issuer_ls180.v:164135.7-164135.20" + wire $0\initial[0:0] + attribute \src "issuer_ls180.v:164256.3-164295.6" + wire width 64 $0\msr2__data_o$next[63:0]$10353 + attribute \src "issuer_ls180.v:164182.3-164183.41" + wire width 64 $0\msr2__data_o[63:0] + attribute \src "issuer_ls180.v:164326.3-164352.6" + wire width 64 $0\reg$next[63:0]$10367 + attribute \src "issuer_ls180.v:164180.3-164181.25" + wire width 64 $0\reg[63:0] + attribute \src "issuer_ls180.v:164296.3-164325.6" + wire $0\wr_detect$4[0:0]$10361 + attribute \src "issuer_ls180.v:164226.3-164255.6" + wire $0\wr_detect[0:0] + attribute \src "issuer_ls180.v:164186.3-164225.6" + wire width 64 $1\cia2__data_o$next[63:0]$10345 + attribute \src "issuer_ls180.v:164142.14-164142.49" + wire width 64 $1\cia2__data_o[63:0] + attribute \src "issuer_ls180.v:164256.3-164295.6" + wire width 64 $1\msr2__data_o$next[63:0]$10354 + attribute \src "issuer_ls180.v:164159.14-164159.49" + wire width 64 $1\msr2__data_o[63:0] + attribute \src "issuer_ls180.v:164326.3-164352.6" + wire width 64 $1\reg$next[63:0]$10368 + attribute \src "issuer_ls180.v:164171.14-164171.42" + wire width 64 $1\reg[63:0] + attribute \src "issuer_ls180.v:164296.3-164325.6" + wire $1\wr_detect$4[0:0]$10362 + attribute \src "issuer_ls180.v:164226.3-164255.6" + wire $1\wr_detect[0:0] + attribute \src "issuer_ls180.v:164186.3-164225.6" + wire width 64 $2\cia2__data_o$next[63:0]$10346 + attribute \src "issuer_ls180.v:164256.3-164295.6" + wire width 64 $2\msr2__data_o$next[63:0]$10355 + attribute \src "issuer_ls180.v:164326.3-164352.6" + wire width 64 $2\reg$next[63:0]$10369 + attribute \src "issuer_ls180.v:164296.3-164325.6" + wire $2\wr_detect$4[0:0]$10363 + attribute \src "issuer_ls180.v:164226.3-164255.6" + wire $2\wr_detect[0:0] + attribute \src "issuer_ls180.v:164186.3-164225.6" + wire width 64 $3\cia2__data_o$next[63:0]$10347 + attribute \src "issuer_ls180.v:164256.3-164295.6" + wire width 64 $3\msr2__data_o$next[63:0]$10356 + attribute \src "issuer_ls180.v:164326.3-164352.6" + wire width 64 $3\reg$next[63:0]$10370 + attribute \src "issuer_ls180.v:164296.3-164325.6" + wire $3\wr_detect$4[0:0]$10364 + attribute \src "issuer_ls180.v:164226.3-164255.6" + wire $3\wr_detect[0:0] + attribute \src "issuer_ls180.v:164186.3-164225.6" + wire width 64 $4\cia2__data_o$next[63:0]$10348 + attribute \src "issuer_ls180.v:164256.3-164295.6" + wire width 64 $4\msr2__data_o$next[63:0]$10357 + attribute \src "issuer_ls180.v:164326.3-164352.6" + wire width 64 $4\reg$next[63:0]$10371 + attribute \src "issuer_ls180.v:164296.3-164325.6" + wire $4\wr_detect$4[0:0]$10365 + attribute \src "issuer_ls180.v:164226.3-164255.6" + wire $4\wr_detect[0:0] + attribute \src "issuer_ls180.v:164186.3-164225.6" + wire width 64 $5\cia2__data_o$next[63:0]$10349 + attribute \src "issuer_ls180.v:164256.3-164295.6" + wire width 64 $5\msr2__data_o$next[63:0]$10358 + attribute \src "issuer_ls180.v:164186.3-164225.6" + wire width 64 $6\cia2__data_o$next[63:0]$10350 + attribute \src "issuer_ls180.v:164256.3-164295.6" + wire width 64 $6\msr2__data_o$next[63:0]$10359 + attribute \src "issuer_ls180.v:164178.17-164178.100" + wire $not$issuer_ls180.v:164178$10338_Y + attribute \src "issuer_ls180.v:164179.17-164179.103" + wire $not$issuer_ls180.v:164179$10339_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 64 output 3 \cia2__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 64 \cia2__data_o$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire input 2 \cia2__ren + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" + wire input 12 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" + wire input 1 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 64 input 11 \d_wr12__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire input 10 \d_wr12__wen + attribute \src "issuer_ls180.v:164135.7-164135.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 64 input 9 \msr2__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 64 output 5 \msr2__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 64 \msr2__data_o$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire input 4 \msr2__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire input 8 \msr2__wen + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 64 input 7 \nia2__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire input 6 \nia2__wen + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" + wire width 64 \reg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" + wire width 64 \reg$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" + wire \wr_detect + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" + wire \wr_detect$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + cell $not $not$issuer_ls180.v:164178$10338 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_detect + connect \Y $not$issuer_ls180.v:164178$10338_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + cell $not $not$issuer_ls180.v:164179$10339 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_detect$4 + connect \Y $not$issuer_ls180.v:164179$10339_Y + end + attribute \src "issuer_ls180.v:164135.7-164135.20" + process $proc$issuer_ls180.v:164135$10372 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "issuer_ls180.v:164142.14-164142.49" + process $proc$issuer_ls180.v:164142$10373 + assign { } { } + assign $1\cia2__data_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \cia2__data_o $1\cia2__data_o[63:0] + end + attribute \src "issuer_ls180.v:164159.14-164159.49" + process $proc$issuer_ls180.v:164159$10374 + assign { } { } + assign $1\msr2__data_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \msr2__data_o $1\msr2__data_o[63:0] + end + attribute \src "issuer_ls180.v:164171.14-164171.42" + process $proc$issuer_ls180.v:164171$10375 + assign { } { } + assign $1\reg[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \reg $1\reg[63:0] + end + attribute \src "issuer_ls180.v:164180.3-164181.25" + process $proc$issuer_ls180.v:164180$10340 + assign { } { } + assign $0\reg[63:0] \reg$next + sync posedge \coresync_clk + update \reg $0\reg[63:0] + end + attribute \src "issuer_ls180.v:164182.3-164183.41" + process $proc$issuer_ls180.v:164182$10341 + assign { } { } + assign $0\msr2__data_o[63:0] \msr2__data_o$next + sync posedge \coresync_clk + update \msr2__data_o $0\msr2__data_o[63:0] + end + attribute \src "issuer_ls180.v:164184.3-164185.41" + process $proc$issuer_ls180.v:164184$10342 + assign { } { } + assign $0\cia2__data_o[63:0] \cia2__data_o$next + sync posedge \coresync_clk + update \cia2__data_o $0\cia2__data_o[63:0] + end + attribute \src "issuer_ls180.v:164186.3-164225.6" + process $proc$issuer_ls180.v:164186$10343 + assign { } { } + assign { } { } + assign { } { } + assign $0\cia2__data_o$next[63:0]$10344 $6\cia2__data_o$next[63:0]$10350 + attribute \src "issuer_ls180.v:164187.5-164187.29" + switch \initial + attribute \src "issuer_ls180.v:164187.9-164187.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \cia2__ren + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\cia2__data_o$next[63:0]$10345 $5\cia2__data_o$next[63:0]$10349 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \nia2__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\cia2__data_o$next[63:0]$10346 \nia2__data_i + case + assign $2\cia2__data_o$next[63:0]$10346 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \msr2__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\cia2__data_o$next[63:0]$10347 \msr2__data_i + case + assign $3\cia2__data_o$next[63:0]$10347 $2\cia2__data_o$next[63:0]$10346 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \d_wr12__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\cia2__data_o$next[63:0]$10348 \d_wr12__data_i + case + assign $4\cia2__data_o$next[63:0]$10348 $3\cia2__data_o$next[63:0]$10347 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + switch \$1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\cia2__data_o$next[63:0]$10349 \reg + case + assign $5\cia2__data_o$next[63:0]$10349 $4\cia2__data_o$next[63:0]$10348 + end + case + assign $1\cia2__data_o$next[63:0]$10345 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $6\cia2__data_o$next[63:0]$10350 64'0000000000000000000000000000000000000000000000000000000000000000 + case + assign $6\cia2__data_o$next[63:0]$10350 $1\cia2__data_o$next[63:0]$10345 + end + sync always + update \cia2__data_o$next $0\cia2__data_o$next[63:0]$10344 + end + attribute \src "issuer_ls180.v:164226.3-164255.6" + process $proc$issuer_ls180.v:164226$10351 + assign { } { } + assign { } { } + assign $0\wr_detect[0:0] $1\wr_detect[0:0] + attribute \src "issuer_ls180.v:164227.5-164227.29" + switch \initial + attribute \src "issuer_ls180.v:164227.9-164227.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \cia2__ren + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\wr_detect[0:0] $4\wr_detect[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \nia2__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\wr_detect[0:0] 1'1 + case + assign $2\wr_detect[0:0] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \msr2__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\wr_detect[0:0] 1'1 + case + assign $3\wr_detect[0:0] $2\wr_detect[0:0] + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \d_wr12__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\wr_detect[0:0] 1'1 + case + assign $4\wr_detect[0:0] $3\wr_detect[0:0] + end + case + assign $1\wr_detect[0:0] 1'0 + end + sync always + update \wr_detect $0\wr_detect[0:0] + end + attribute \src "issuer_ls180.v:164256.3-164295.6" + process $proc$issuer_ls180.v:164256$10352 + assign { } { } + assign { } { } + assign { } { } + assign $0\msr2__data_o$next[63:0]$10353 $6\msr2__data_o$next[63:0]$10359 + attribute \src "issuer_ls180.v:164257.5-164257.29" + switch \initial + attribute \src "issuer_ls180.v:164257.9-164257.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \msr2__ren + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\msr2__data_o$next[63:0]$10354 $5\msr2__data_o$next[63:0]$10358 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \nia2__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\msr2__data_o$next[63:0]$10355 \nia2__data_i + case + assign $2\msr2__data_o$next[63:0]$10355 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \msr2__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\msr2__data_o$next[63:0]$10356 \msr2__data_i + case + assign $3\msr2__data_o$next[63:0]$10356 $2\msr2__data_o$next[63:0]$10355 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \d_wr12__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\msr2__data_o$next[63:0]$10357 \d_wr12__data_i + case + assign $4\msr2__data_o$next[63:0]$10357 $3\msr2__data_o$next[63:0]$10356 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + switch \$3 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\msr2__data_o$next[63:0]$10358 \reg + case + assign $5\msr2__data_o$next[63:0]$10358 $4\msr2__data_o$next[63:0]$10357 + end + case + assign $1\msr2__data_o$next[63:0]$10354 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $6\msr2__data_o$next[63:0]$10359 64'0000000000000000000000000000000000000000000000000000000000000000 + case + assign $6\msr2__data_o$next[63:0]$10359 $1\msr2__data_o$next[63:0]$10354 + end + sync always + update \msr2__data_o$next $0\msr2__data_o$next[63:0]$10353 + end + attribute \src "issuer_ls180.v:164296.3-164325.6" + process $proc$issuer_ls180.v:164296$10360 + assign { } { } + assign { } { } + assign $0\wr_detect$4[0:0]$10361 $1\wr_detect$4[0:0]$10362 + attribute \src "issuer_ls180.v:164297.5-164297.29" + switch \initial + attribute \src "issuer_ls180.v:164297.9-164297.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \msr2__ren + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\wr_detect$4[0:0]$10362 $4\wr_detect$4[0:0]$10365 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \nia2__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\wr_detect$4[0:0]$10363 1'1 + case + assign $2\wr_detect$4[0:0]$10363 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \msr2__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\wr_detect$4[0:0]$10364 1'1 + case + assign $3\wr_detect$4[0:0]$10364 $2\wr_detect$4[0:0]$10363 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \d_wr12__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\wr_detect$4[0:0]$10365 1'1 + case + assign $4\wr_detect$4[0:0]$10365 $3\wr_detect$4[0:0]$10364 + end + case + assign $1\wr_detect$4[0:0]$10362 1'0 + end + sync always + update \wr_detect$4 $0\wr_detect$4[0:0]$10361 + end + attribute \src "issuer_ls180.v:164326.3-164352.6" + process $proc$issuer_ls180.v:164326$10366 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\reg$next[63:0]$10367 $4\reg$next[63:0]$10371 + attribute \src "issuer_ls180.v:164327.5-164327.29" + switch \initial + attribute \src "issuer_ls180.v:164327.9-164327.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" + switch \nia2__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\reg$next[63:0]$10368 \nia2__data_i + case + assign $1\reg$next[63:0]$10368 \reg + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" + switch \msr2__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\reg$next[63:0]$10369 \msr2__data_i + case + assign $2\reg$next[63:0]$10369 $1\reg$next[63:0]$10368 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" + switch \d_wr12__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\reg$next[63:0]$10370 \d_wr12__data_i + case + assign $3\reg$next[63:0]$10370 $2\reg$next[63:0]$10369 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\reg$next[63:0]$10371 64'0000000000000000000000000000000000000000000000000000000000000000 + case + assign $4\reg$next[63:0]$10371 $3\reg$next[63:0]$10370 + end + sync always + update \reg$next $0\reg$next[63:0]$10367 + end + connect \$1 $not$issuer_ls180.v:164178$10338_Y + connect \$3 $not$issuer_ls180.v:164179$10339_Y +end +attribute \src "issuer_ls180.v:164357.1-164828.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.cr.reg_3" +attribute \generator "nMigen" +module \reg_3 + attribute \src "issuer_ls180.v:164358.7-164358.20" + wire $0\initial[0:0] + attribute \src "issuer_ls180.v:164758.3-164797.6" + wire width 4 $0\r23__data_o$next[3:0]$10445 + attribute \src "issuer_ls180.v:164441.3-164442.39" + wire width 4 $0\r23__data_o[3:0] + attribute \src "issuer_ls180.v:164688.3-164727.6" + wire width 4 $0\r3__data_o$next[3:0]$10431 + attribute \src "issuer_ls180.v:164443.3-164444.37" + wire width 4 $0\r3__data_o[3:0] + attribute \src "issuer_ls180.v:164521.3-164547.6" + wire width 4 $0\reg$next[3:0]$10397 + attribute \src "issuer_ls180.v:164439.3-164440.25" + wire width 4 $0\reg[3:0] + attribute \src "issuer_ls180.v:164451.3-164490.6" + wire width 4 $0\src13__data_o$next[3:0]$10388 + attribute \src "issuer_ls180.v:164449.3-164450.43" + wire width 4 $0\src13__data_o[3:0] + attribute \src "issuer_ls180.v:164548.3-164587.6" + wire width 4 $0\src23__data_o$next[3:0]$10403 + attribute \src "issuer_ls180.v:164447.3-164448.43" + wire width 4 $0\src23__data_o[3:0] + attribute \src "issuer_ls180.v:164618.3-164657.6" + wire width 4 $0\src33__data_o$next[3:0]$10417 + attribute \src "issuer_ls180.v:164445.3-164446.43" + wire width 4 $0\src33__data_o[3:0] + attribute \src "issuer_ls180.v:164728.3-164757.6" + wire $0\wr_detect$10[0:0]$10439 + attribute \src "issuer_ls180.v:164798.3-164827.6" + wire $0\wr_detect$13[0:0]$10453 + attribute \src "issuer_ls180.v:164588.3-164617.6" + wire $0\wr_detect$4[0:0]$10411 + attribute \src "issuer_ls180.v:164658.3-164687.6" + wire $0\wr_detect$7[0:0]$10425 + attribute \src "issuer_ls180.v:164491.3-164520.6" + wire $0\wr_detect[0:0] + attribute \src "issuer_ls180.v:164758.3-164797.6" + wire width 4 $1\r23__data_o$next[3:0]$10446 + attribute \src "issuer_ls180.v:164383.13-164383.31" + wire width 4 $1\r23__data_o[3:0] + attribute \src "issuer_ls180.v:164688.3-164727.6" + wire width 4 $1\r3__data_o$next[3:0]$10432 + attribute \src "issuer_ls180.v:164390.13-164390.30" + wire width 4 $1\r3__data_o[3:0] + attribute \src "issuer_ls180.v:164521.3-164547.6" + wire width 4 $1\reg$next[3:0]$10398 + attribute \src "issuer_ls180.v:164396.13-164396.25" + wire width 4 $1\reg[3:0] + attribute \src "issuer_ls180.v:164451.3-164490.6" + wire width 4 $1\src13__data_o$next[3:0]$10389 + attribute \src "issuer_ls180.v:164401.13-164401.33" + wire width 4 $1\src13__data_o[3:0] + attribute \src "issuer_ls180.v:164548.3-164587.6" + wire width 4 $1\src23__data_o$next[3:0]$10404 + attribute \src "issuer_ls180.v:164408.13-164408.33" + wire width 4 $1\src23__data_o[3:0] + attribute \src "issuer_ls180.v:164618.3-164657.6" + wire width 4 $1\src33__data_o$next[3:0]$10418 + attribute \src "issuer_ls180.v:164415.13-164415.33" + wire width 4 $1\src33__data_o[3:0] + attribute \src "issuer_ls180.v:164728.3-164757.6" + wire $1\wr_detect$10[0:0]$10440 + attribute \src "issuer_ls180.v:164798.3-164827.6" + wire $1\wr_detect$13[0:0]$10454 + attribute \src "issuer_ls180.v:164588.3-164617.6" + wire $1\wr_detect$4[0:0]$10412 + attribute \src "issuer_ls180.v:164658.3-164687.6" + wire $1\wr_detect$7[0:0]$10426 + attribute \src "issuer_ls180.v:164491.3-164520.6" + wire $1\wr_detect[0:0] + attribute \src "issuer_ls180.v:164758.3-164797.6" + wire width 4 $2\r23__data_o$next[3:0]$10447 + attribute \src "issuer_ls180.v:164688.3-164727.6" + wire width 4 $2\r3__data_o$next[3:0]$10433 + attribute \src "issuer_ls180.v:164521.3-164547.6" + wire width 4 $2\reg$next[3:0]$10399 + attribute \src "issuer_ls180.v:164451.3-164490.6" + wire width 4 $2\src13__data_o$next[3:0]$10390 + attribute \src "issuer_ls180.v:164548.3-164587.6" + wire width 4 $2\src23__data_o$next[3:0]$10405 + attribute \src "issuer_ls180.v:164618.3-164657.6" + wire width 4 $2\src33__data_o$next[3:0]$10419 + attribute \src "issuer_ls180.v:164728.3-164757.6" + wire $2\wr_detect$10[0:0]$10441 + attribute \src "issuer_ls180.v:164798.3-164827.6" + wire $2\wr_detect$13[0:0]$10455 + attribute \src "issuer_ls180.v:164588.3-164617.6" + wire $2\wr_detect$4[0:0]$10413 + attribute \src "issuer_ls180.v:164658.3-164687.6" + wire $2\wr_detect$7[0:0]$10427 + attribute \src "issuer_ls180.v:164491.3-164520.6" + wire $2\wr_detect[0:0] + attribute \src "issuer_ls180.v:164758.3-164797.6" + wire width 4 $3\r23__data_o$next[3:0]$10448 + attribute \src "issuer_ls180.v:164688.3-164727.6" + wire width 4 $3\r3__data_o$next[3:0]$10434 + attribute \src "issuer_ls180.v:164521.3-164547.6" + wire width 4 $3\reg$next[3:0]$10400 + attribute \src "issuer_ls180.v:164451.3-164490.6" + wire width 4 $3\src13__data_o$next[3:0]$10391 + attribute \src "issuer_ls180.v:164548.3-164587.6" + wire width 4 $3\src23__data_o$next[3:0]$10406 + attribute \src "issuer_ls180.v:164618.3-164657.6" + wire width 4 $3\src33__data_o$next[3:0]$10420 + attribute \src "issuer_ls180.v:164728.3-164757.6" + wire $3\wr_detect$10[0:0]$10442 + attribute \src "issuer_ls180.v:164798.3-164827.6" + wire $3\wr_detect$13[0:0]$10456 + attribute \src "issuer_ls180.v:164588.3-164617.6" + wire $3\wr_detect$4[0:0]$10414 + attribute \src "issuer_ls180.v:164658.3-164687.6" + wire $3\wr_detect$7[0:0]$10428 + attribute \src "issuer_ls180.v:164491.3-164520.6" + wire $3\wr_detect[0:0] + attribute \src "issuer_ls180.v:164758.3-164797.6" + wire width 4 $4\r23__data_o$next[3:0]$10449 + attribute \src "issuer_ls180.v:164688.3-164727.6" + wire width 4 $4\r3__data_o$next[3:0]$10435 + attribute \src "issuer_ls180.v:164521.3-164547.6" + wire width 4 $4\reg$next[3:0]$10401 + attribute \src "issuer_ls180.v:164451.3-164490.6" + wire width 4 $4\src13__data_o$next[3:0]$10392 + attribute \src "issuer_ls180.v:164548.3-164587.6" + wire width 4 $4\src23__data_o$next[3:0]$10407 + attribute \src "issuer_ls180.v:164618.3-164657.6" + wire width 4 $4\src33__data_o$next[3:0]$10421 + attribute \src "issuer_ls180.v:164728.3-164757.6" + wire $4\wr_detect$10[0:0]$10443 + attribute \src "issuer_ls180.v:164798.3-164827.6" + wire $4\wr_detect$13[0:0]$10457 + attribute \src "issuer_ls180.v:164588.3-164617.6" + wire $4\wr_detect$4[0:0]$10415 + attribute \src "issuer_ls180.v:164658.3-164687.6" + wire $4\wr_detect$7[0:0]$10429 + attribute \src "issuer_ls180.v:164491.3-164520.6" + wire $4\wr_detect[0:0] + attribute \src "issuer_ls180.v:164758.3-164797.6" + wire width 4 $5\r23__data_o$next[3:0]$10450 + attribute \src "issuer_ls180.v:164688.3-164727.6" + wire width 4 $5\r3__data_o$next[3:0]$10436 + attribute \src "issuer_ls180.v:164451.3-164490.6" + wire width 4 $5\src13__data_o$next[3:0]$10393 + attribute \src "issuer_ls180.v:164548.3-164587.6" + wire width 4 $5\src23__data_o$next[3:0]$10408 + attribute \src "issuer_ls180.v:164618.3-164657.6" + wire width 4 $5\src33__data_o$next[3:0]$10422 + attribute \src "issuer_ls180.v:164758.3-164797.6" + wire width 4 $6\r23__data_o$next[3:0]$10451 + attribute \src "issuer_ls180.v:164688.3-164727.6" + wire width 4 $6\r3__data_o$next[3:0]$10437 + attribute \src "issuer_ls180.v:164451.3-164490.6" + wire width 4 $6\src13__data_o$next[3:0]$10394 + attribute \src "issuer_ls180.v:164548.3-164587.6" + wire width 4 $6\src23__data_o$next[3:0]$10409 + attribute \src "issuer_ls180.v:164618.3-164657.6" + wire width 4 $6\src33__data_o$next[3:0]$10423 + attribute \src "issuer_ls180.v:164434.17-164434.104" + wire $not$issuer_ls180.v:164434$10376_Y + attribute \src "issuer_ls180.v:164435.18-164435.105" + wire $not$issuer_ls180.v:164435$10377_Y + attribute \src "issuer_ls180.v:164436.17-164436.100" + wire $not$issuer_ls180.v:164436$10378_Y + attribute \src "issuer_ls180.v:164437.17-164437.103" + wire $not$issuer_ls180.v:164437$10379_Y + attribute \src "issuer_ls180.v:164438.17-164438.103" + wire $not$issuer_ls180.v:164438$10380_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + wire \$12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + wire \$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + wire \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" + wire input 18 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" + wire input 1 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 input 9 \dest13__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire input 8 \dest13__wen + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 input 11 \dest23__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire input 10 \dest23__wen + attribute \src "issuer_ls180.v:164358.7-164358.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 output 14 \r23__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 \r23__data_o$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire input 15 \r23__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 output 12 \r3__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 \r3__data_o$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire input 13 \r3__ren + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" + wire width 4 \reg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" + wire width 4 \reg$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 output 3 \src13__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 \src13__data_o$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire input 2 \src13__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 output 5 \src23__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 \src23__data_o$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire input 4 \src23__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 output 7 \src33__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 \src33__data_o$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire input 6 \src33__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 input 16 \w3__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire input 17 \w3__wen + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" + wire \wr_detect + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" + wire \wr_detect$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" + wire \wr_detect$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" + wire \wr_detect$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" + wire \wr_detect$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + cell $not $not$issuer_ls180.v:164434$10376 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_detect$10 + connect \Y $not$issuer_ls180.v:164434$10376_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + cell $not $not$issuer_ls180.v:164435$10377 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_detect$13 + connect \Y $not$issuer_ls180.v:164435$10377_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + cell $not $not$issuer_ls180.v:164436$10378 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_detect + connect \Y $not$issuer_ls180.v:164436$10378_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + cell $not $not$issuer_ls180.v:164437$10379 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_detect$4 + connect \Y $not$issuer_ls180.v:164437$10379_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + cell $not $not$issuer_ls180.v:164438$10380 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_detect$7 + connect \Y $not$issuer_ls180.v:164438$10380_Y + end + attribute \src "issuer_ls180.v:164358.7-164358.20" + process $proc$issuer_ls180.v:164358$10458 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "issuer_ls180.v:164383.13-164383.31" + process $proc$issuer_ls180.v:164383$10459 + assign { } { } + assign $1\r23__data_o[3:0] 4'0000 + sync always + sync init + update \r23__data_o $1\r23__data_o[3:0] + end + attribute \src "issuer_ls180.v:164390.13-164390.30" + process $proc$issuer_ls180.v:164390$10460 + assign { } { } + assign $1\r3__data_o[3:0] 4'0000 + sync always + sync init + update \r3__data_o $1\r3__data_o[3:0] + end + attribute \src "issuer_ls180.v:164396.13-164396.25" + process $proc$issuer_ls180.v:164396$10461 + assign { } { } + assign $1\reg[3:0] 4'0000 + sync always + sync init + update \reg $1\reg[3:0] + end + attribute \src "issuer_ls180.v:164401.13-164401.33" + process $proc$issuer_ls180.v:164401$10462 + assign { } { } + assign $1\src13__data_o[3:0] 4'0000 + sync always + sync init + update \src13__data_o $1\src13__data_o[3:0] + end + attribute \src "issuer_ls180.v:164408.13-164408.33" + process $proc$issuer_ls180.v:164408$10463 + assign { } { } + assign $1\src23__data_o[3:0] 4'0000 + sync always + sync init + update \src23__data_o $1\src23__data_o[3:0] + end + attribute \src "issuer_ls180.v:164415.13-164415.33" + process $proc$issuer_ls180.v:164415$10464 + assign { } { } + assign $1\src33__data_o[3:0] 4'0000 + sync always + sync init + update \src33__data_o $1\src33__data_o[3:0] + end + attribute \src "issuer_ls180.v:164439.3-164440.25" + process $proc$issuer_ls180.v:164439$10381 + assign { } { } + assign $0\reg[3:0] \reg$next + sync posedge \coresync_clk + update \reg $0\reg[3:0] + end + attribute \src "issuer_ls180.v:164441.3-164442.39" + process $proc$issuer_ls180.v:164441$10382 + assign { } { } + assign $0\r23__data_o[3:0] \r23__data_o$next + sync posedge \coresync_clk + update \r23__data_o $0\r23__data_o[3:0] + end + attribute \src "issuer_ls180.v:164443.3-164444.37" + process $proc$issuer_ls180.v:164443$10383 + assign { } { } + assign $0\r3__data_o[3:0] \r3__data_o$next + sync posedge \coresync_clk + update \r3__data_o $0\r3__data_o[3:0] + end + attribute \src "issuer_ls180.v:164445.3-164446.43" + process $proc$issuer_ls180.v:164445$10384 + assign { } { } + assign $0\src33__data_o[3:0] \src33__data_o$next + sync posedge \coresync_clk + update \src33__data_o $0\src33__data_o[3:0] + end + attribute \src "issuer_ls180.v:164447.3-164448.43" + process $proc$issuer_ls180.v:164447$10385 + assign { } { } + assign $0\src23__data_o[3:0] \src23__data_o$next + sync posedge \coresync_clk + update \src23__data_o $0\src23__data_o[3:0] + end + attribute \src "issuer_ls180.v:164449.3-164450.43" + process $proc$issuer_ls180.v:164449$10386 + assign { } { } + assign $0\src13__data_o[3:0] \src13__data_o$next + sync posedge \coresync_clk + update \src13__data_o $0\src13__data_o[3:0] + end + attribute \src "issuer_ls180.v:164451.3-164490.6" + process $proc$issuer_ls180.v:164451$10387 + assign { } { } + assign { } { } + assign { } { } + assign $0\src13__data_o$next[3:0]$10388 $6\src13__data_o$next[3:0]$10394 + attribute \src "issuer_ls180.v:164452.5-164452.29" + switch \initial + attribute \src "issuer_ls180.v:164452.9-164452.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \src13__ren + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\src13__data_o$next[3:0]$10389 $5\src13__data_o$next[3:0]$10393 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest13__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\src13__data_o$next[3:0]$10390 \dest13__data_i + case + assign $2\src13__data_o$next[3:0]$10390 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest23__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\src13__data_o$next[3:0]$10391 \dest23__data_i + case + assign $3\src13__data_o$next[3:0]$10391 $2\src13__data_o$next[3:0]$10390 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w3__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\src13__data_o$next[3:0]$10392 \w3__data_i + case + assign $4\src13__data_o$next[3:0]$10392 $3\src13__data_o$next[3:0]$10391 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + switch \$1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\src13__data_o$next[3:0]$10393 \reg + case + assign $5\src13__data_o$next[3:0]$10393 $4\src13__data_o$next[3:0]$10392 + end + case + assign $1\src13__data_o$next[3:0]$10389 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $6\src13__data_o$next[3:0]$10394 4'0000 + case + assign $6\src13__data_o$next[3:0]$10394 $1\src13__data_o$next[3:0]$10389 + end + sync always + update \src13__data_o$next $0\src13__data_o$next[3:0]$10388 + end + attribute \src "issuer_ls180.v:164491.3-164520.6" + process $proc$issuer_ls180.v:164491$10395 + assign { } { } + assign { } { } + assign $0\wr_detect[0:0] $1\wr_detect[0:0] + attribute \src "issuer_ls180.v:164492.5-164492.29" + switch \initial + attribute \src "issuer_ls180.v:164492.9-164492.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \src13__ren + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\wr_detect[0:0] $4\wr_detect[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest13__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\wr_detect[0:0] 1'1 + case + assign $2\wr_detect[0:0] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest23__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\wr_detect[0:0] 1'1 + case + assign $3\wr_detect[0:0] $2\wr_detect[0:0] + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w3__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\wr_detect[0:0] 1'1 + case + assign $4\wr_detect[0:0] $3\wr_detect[0:0] + end + case + assign $1\wr_detect[0:0] 1'0 + end + sync always + update \wr_detect $0\wr_detect[0:0] + end + attribute \src "issuer_ls180.v:164521.3-164547.6" + process $proc$issuer_ls180.v:164521$10396 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\reg$next[3:0]$10397 $4\reg$next[3:0]$10401 + attribute \src "issuer_ls180.v:164522.5-164522.29" + switch \initial + attribute \src "issuer_ls180.v:164522.9-164522.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" + switch \dest13__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\reg$next[3:0]$10398 \dest13__data_i + case + assign $1\reg$next[3:0]$10398 \reg + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" + switch \dest23__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\reg$next[3:0]$10399 \dest23__data_i + case + assign $2\reg$next[3:0]$10399 $1\reg$next[3:0]$10398 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" + switch \w3__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\reg$next[3:0]$10400 \w3__data_i + case + assign $3\reg$next[3:0]$10400 $2\reg$next[3:0]$10399 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\reg$next[3:0]$10401 4'0000 + case + assign $4\reg$next[3:0]$10401 $3\reg$next[3:0]$10400 + end + sync always + update \reg$next $0\reg$next[3:0]$10397 + end + attribute \src "issuer_ls180.v:164548.3-164587.6" + process $proc$issuer_ls180.v:164548$10402 + assign { } { } + assign { } { } + assign { } { } + assign $0\src23__data_o$next[3:0]$10403 $6\src23__data_o$next[3:0]$10409 + attribute \src "issuer_ls180.v:164549.5-164549.29" + switch \initial + attribute \src "issuer_ls180.v:164549.9-164549.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \src23__ren + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\src23__data_o$next[3:0]$10404 $5\src23__data_o$next[3:0]$10408 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest13__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\src23__data_o$next[3:0]$10405 \dest13__data_i + case + assign $2\src23__data_o$next[3:0]$10405 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest23__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\src23__data_o$next[3:0]$10406 \dest23__data_i + case + assign $3\src23__data_o$next[3:0]$10406 $2\src23__data_o$next[3:0]$10405 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w3__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\src23__data_o$next[3:0]$10407 \w3__data_i + case + assign $4\src23__data_o$next[3:0]$10407 $3\src23__data_o$next[3:0]$10406 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + switch \$3 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\src23__data_o$next[3:0]$10408 \reg + case + assign $5\src23__data_o$next[3:0]$10408 $4\src23__data_o$next[3:0]$10407 + end + case + assign $1\src23__data_o$next[3:0]$10404 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $6\src23__data_o$next[3:0]$10409 4'0000 + case + assign $6\src23__data_o$next[3:0]$10409 $1\src23__data_o$next[3:0]$10404 + end + sync always + update \src23__data_o$next $0\src23__data_o$next[3:0]$10403 + end + attribute \src "issuer_ls180.v:164588.3-164617.6" + process $proc$issuer_ls180.v:164588$10410 + assign { } { } + assign { } { } + assign $0\wr_detect$4[0:0]$10411 $1\wr_detect$4[0:0]$10412 + attribute \src "issuer_ls180.v:164589.5-164589.29" + switch \initial + attribute \src "issuer_ls180.v:164589.9-164589.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \src23__ren + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\wr_detect$4[0:0]$10412 $4\wr_detect$4[0:0]$10415 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest13__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\wr_detect$4[0:0]$10413 1'1 + case + assign $2\wr_detect$4[0:0]$10413 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest23__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\wr_detect$4[0:0]$10414 1'1 + case + assign $3\wr_detect$4[0:0]$10414 $2\wr_detect$4[0:0]$10413 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w3__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\wr_detect$4[0:0]$10415 1'1 + case + assign $4\wr_detect$4[0:0]$10415 $3\wr_detect$4[0:0]$10414 + end + case + assign $1\wr_detect$4[0:0]$10412 1'0 + end + sync always + update \wr_detect$4 $0\wr_detect$4[0:0]$10411 + end + attribute \src "issuer_ls180.v:164618.3-164657.6" + process $proc$issuer_ls180.v:164618$10416 + assign { } { } + assign { } { } + assign { } { } + assign $0\src33__data_o$next[3:0]$10417 $6\src33__data_o$next[3:0]$10423 + attribute \src "issuer_ls180.v:164619.5-164619.29" + switch \initial + attribute \src "issuer_ls180.v:164619.9-164619.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \src33__ren + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\src33__data_o$next[3:0]$10418 $5\src33__data_o$next[3:0]$10422 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest13__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\src33__data_o$next[3:0]$10419 \dest13__data_i + case + assign $2\src33__data_o$next[3:0]$10419 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest23__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\src33__data_o$next[3:0]$10420 \dest23__data_i + case + assign $3\src33__data_o$next[3:0]$10420 $2\src33__data_o$next[3:0]$10419 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w3__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\src33__data_o$next[3:0]$10421 \w3__data_i + case + assign $4\src33__data_o$next[3:0]$10421 $3\src33__data_o$next[3:0]$10420 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + switch \$6 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\src33__data_o$next[3:0]$10422 \reg + case + assign $5\src33__data_o$next[3:0]$10422 $4\src33__data_o$next[3:0]$10421 + end + case + assign $1\src33__data_o$next[3:0]$10418 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $6\src33__data_o$next[3:0]$10423 4'0000 + case + assign $6\src33__data_o$next[3:0]$10423 $1\src33__data_o$next[3:0]$10418 + end + sync always + update \src33__data_o$next $0\src33__data_o$next[3:0]$10417 + end + attribute \src "issuer_ls180.v:164658.3-164687.6" + process $proc$issuer_ls180.v:164658$10424 + assign { } { } + assign { } { } + assign $0\wr_detect$7[0:0]$10425 $1\wr_detect$7[0:0]$10426 + attribute \src "issuer_ls180.v:164659.5-164659.29" + switch \initial + attribute \src "issuer_ls180.v:164659.9-164659.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \src33__ren + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\wr_detect$7[0:0]$10426 $4\wr_detect$7[0:0]$10429 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest13__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\wr_detect$7[0:0]$10427 1'1 + case + assign $2\wr_detect$7[0:0]$10427 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest23__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\wr_detect$7[0:0]$10428 1'1 + case + assign $3\wr_detect$7[0:0]$10428 $2\wr_detect$7[0:0]$10427 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w3__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\wr_detect$7[0:0]$10429 1'1 + case + assign $4\wr_detect$7[0:0]$10429 $3\wr_detect$7[0:0]$10428 + end + case + assign $1\wr_detect$7[0:0]$10426 1'0 + end + sync always + update \wr_detect$7 $0\wr_detect$7[0:0]$10425 + end + attribute \src "issuer_ls180.v:164688.3-164727.6" + process $proc$issuer_ls180.v:164688$10430 + assign { } { } + assign { } { } + assign { } { } + assign $0\r3__data_o$next[3:0]$10431 $6\r3__data_o$next[3:0]$10437 + attribute \src "issuer_ls180.v:164689.5-164689.29" + switch \initial + attribute \src "issuer_ls180.v:164689.9-164689.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \r3__ren + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\r3__data_o$next[3:0]$10432 $5\r3__data_o$next[3:0]$10436 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest13__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\r3__data_o$next[3:0]$10433 \dest13__data_i + case + assign $2\r3__data_o$next[3:0]$10433 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest23__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\r3__data_o$next[3:0]$10434 \dest23__data_i + case + assign $3\r3__data_o$next[3:0]$10434 $2\r3__data_o$next[3:0]$10433 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w3__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\r3__data_o$next[3:0]$10435 \w3__data_i + case + assign $4\r3__data_o$next[3:0]$10435 $3\r3__data_o$next[3:0]$10434 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + switch \$9 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\r3__data_o$next[3:0]$10436 \reg + case + assign $5\r3__data_o$next[3:0]$10436 $4\r3__data_o$next[3:0]$10435 + end + case + assign $1\r3__data_o$next[3:0]$10432 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $6\r3__data_o$next[3:0]$10437 4'0000 + case + assign $6\r3__data_o$next[3:0]$10437 $1\r3__data_o$next[3:0]$10432 + end + sync always + update \r3__data_o$next $0\r3__data_o$next[3:0]$10431 + end + attribute \src "issuer_ls180.v:164728.3-164757.6" + process $proc$issuer_ls180.v:164728$10438 + assign { } { } + assign { } { } + assign $0\wr_detect$10[0:0]$10439 $1\wr_detect$10[0:0]$10440 + attribute \src "issuer_ls180.v:164729.5-164729.29" + switch \initial + attribute \src "issuer_ls180.v:164729.9-164729.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \r3__ren + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\wr_detect$10[0:0]$10440 $4\wr_detect$10[0:0]$10443 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest13__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\wr_detect$10[0:0]$10441 1'1 + case + assign $2\wr_detect$10[0:0]$10441 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest23__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\wr_detect$10[0:0]$10442 1'1 + case + assign $3\wr_detect$10[0:0]$10442 $2\wr_detect$10[0:0]$10441 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w3__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\wr_detect$10[0:0]$10443 1'1 + case + assign $4\wr_detect$10[0:0]$10443 $3\wr_detect$10[0:0]$10442 + end + case + assign $1\wr_detect$10[0:0]$10440 1'0 + end + sync always + update \wr_detect$10 $0\wr_detect$10[0:0]$10439 + end + attribute \src "issuer_ls180.v:164758.3-164797.6" + process $proc$issuer_ls180.v:164758$10444 + assign { } { } + assign { } { } + assign { } { } + assign $0\r23__data_o$next[3:0]$10445 $6\r23__data_o$next[3:0]$10451 + attribute \src "issuer_ls180.v:164759.5-164759.29" + switch \initial + attribute \src "issuer_ls180.v:164759.9-164759.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \r23__ren + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\r23__data_o$next[3:0]$10446 $5\r23__data_o$next[3:0]$10450 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest13__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\r23__data_o$next[3:0]$10447 \dest13__data_i + case + assign $2\r23__data_o$next[3:0]$10447 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest23__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\r23__data_o$next[3:0]$10448 \dest23__data_i + case + assign $3\r23__data_o$next[3:0]$10448 $2\r23__data_o$next[3:0]$10447 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w3__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\r23__data_o$next[3:0]$10449 \w3__data_i + case + assign $4\r23__data_o$next[3:0]$10449 $3\r23__data_o$next[3:0]$10448 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + switch \$12 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\r23__data_o$next[3:0]$10450 \reg + case + assign $5\r23__data_o$next[3:0]$10450 $4\r23__data_o$next[3:0]$10449 + end + case + assign $1\r23__data_o$next[3:0]$10446 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $6\r23__data_o$next[3:0]$10451 4'0000 + case + assign $6\r23__data_o$next[3:0]$10451 $1\r23__data_o$next[3:0]$10446 + end + sync always + update \r23__data_o$next $0\r23__data_o$next[3:0]$10445 + end + attribute \src "issuer_ls180.v:164798.3-164827.6" + process $proc$issuer_ls180.v:164798$10452 + assign { } { } + assign { } { } + assign $0\wr_detect$13[0:0]$10453 $1\wr_detect$13[0:0]$10454 + attribute \src "issuer_ls180.v:164799.5-164799.29" + switch \initial + attribute \src "issuer_ls180.v:164799.9-164799.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \r23__ren + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\wr_detect$13[0:0]$10454 $4\wr_detect$13[0:0]$10457 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest13__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\wr_detect$13[0:0]$10455 1'1 + case + assign $2\wr_detect$13[0:0]$10455 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest23__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\wr_detect$13[0:0]$10456 1'1 + case + assign $3\wr_detect$13[0:0]$10456 $2\wr_detect$13[0:0]$10455 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w3__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\wr_detect$13[0:0]$10457 1'1 + case + assign $4\wr_detect$13[0:0]$10457 $3\wr_detect$13[0:0]$10456 + end + case + assign $1\wr_detect$13[0:0]$10454 1'0 + end + sync always + update \wr_detect$13 $0\wr_detect$13[0:0]$10453 + end + connect \$9 $not$issuer_ls180.v:164434$10376_Y + connect \$12 $not$issuer_ls180.v:164435$10377_Y + connect \$1 $not$issuer_ls180.v:164436$10378_Y + connect \$3 $not$issuer_ls180.v:164437$10379_Y + connect \$6 $not$issuer_ls180.v:164438$10380_Y +end +attribute \src "issuer_ls180.v:164832.1-165051.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.state.reg_3" +attribute \generator "nMigen" +module \reg_3$135 + attribute \src "issuer_ls180.v:164884.3-164923.6" + wire width 64 $0\cia3__data_o$next[63:0]$10471 + attribute \src "issuer_ls180.v:164882.3-164883.41" + wire width 64 $0\cia3__data_o[63:0] + attribute \src "issuer_ls180.v:164833.7-164833.20" + wire $0\initial[0:0] + attribute \src "issuer_ls180.v:164954.3-164993.6" + wire width 64 $0\msr3__data_o$next[63:0]$10480 + attribute \src "issuer_ls180.v:164880.3-164881.41" + wire width 64 $0\msr3__data_o[63:0] + attribute \src "issuer_ls180.v:165024.3-165050.6" + wire width 64 $0\reg$next[63:0]$10494 + attribute \src "issuer_ls180.v:164878.3-164879.25" + wire width 64 $0\reg[63:0] + attribute \src "issuer_ls180.v:164994.3-165023.6" + wire $0\wr_detect$4[0:0]$10488 + attribute \src "issuer_ls180.v:164924.3-164953.6" + wire $0\wr_detect[0:0] + attribute \src "issuer_ls180.v:164884.3-164923.6" + wire width 64 $1\cia3__data_o$next[63:0]$10472 + attribute \src "issuer_ls180.v:164840.14-164840.49" + wire width 64 $1\cia3__data_o[63:0] + attribute \src "issuer_ls180.v:164954.3-164993.6" + wire width 64 $1\msr3__data_o$next[63:0]$10481 + attribute \src "issuer_ls180.v:164857.14-164857.49" + wire width 64 $1\msr3__data_o[63:0] + attribute \src "issuer_ls180.v:165024.3-165050.6" + wire width 64 $1\reg$next[63:0]$10495 + attribute \src "issuer_ls180.v:164869.14-164869.42" + wire width 64 $1\reg[63:0] + attribute \src "issuer_ls180.v:164994.3-165023.6" + wire $1\wr_detect$4[0:0]$10489 + attribute \src "issuer_ls180.v:164924.3-164953.6" + wire $1\wr_detect[0:0] + attribute \src "issuer_ls180.v:164884.3-164923.6" + wire width 64 $2\cia3__data_o$next[63:0]$10473 + attribute \src "issuer_ls180.v:164954.3-164993.6" + wire width 64 $2\msr3__data_o$next[63:0]$10482 + attribute \src "issuer_ls180.v:165024.3-165050.6" + wire width 64 $2\reg$next[63:0]$10496 + attribute \src "issuer_ls180.v:164994.3-165023.6" + wire $2\wr_detect$4[0:0]$10490 + attribute \src "issuer_ls180.v:164924.3-164953.6" + wire $2\wr_detect[0:0] + attribute \src "issuer_ls180.v:164884.3-164923.6" + wire width 64 $3\cia3__data_o$next[63:0]$10474 + attribute \src "issuer_ls180.v:164954.3-164993.6" + wire width 64 $3\msr3__data_o$next[63:0]$10483 + attribute \src "issuer_ls180.v:165024.3-165050.6" + wire width 64 $3\reg$next[63:0]$10497 + attribute \src "issuer_ls180.v:164994.3-165023.6" + wire $3\wr_detect$4[0:0]$10491 + attribute \src "issuer_ls180.v:164924.3-164953.6" + wire $3\wr_detect[0:0] + attribute \src "issuer_ls180.v:164884.3-164923.6" + wire width 64 $4\cia3__data_o$next[63:0]$10475 + attribute \src "issuer_ls180.v:164954.3-164993.6" + wire width 64 $4\msr3__data_o$next[63:0]$10484 + attribute \src "issuer_ls180.v:165024.3-165050.6" + wire width 64 $4\reg$next[63:0]$10498 + attribute \src "issuer_ls180.v:164994.3-165023.6" + wire $4\wr_detect$4[0:0]$10492 + attribute \src "issuer_ls180.v:164924.3-164953.6" + wire $4\wr_detect[0:0] + attribute \src "issuer_ls180.v:164884.3-164923.6" + wire width 64 $5\cia3__data_o$next[63:0]$10476 + attribute \src "issuer_ls180.v:164954.3-164993.6" + wire width 64 $5\msr3__data_o$next[63:0]$10485 + attribute \src "issuer_ls180.v:164884.3-164923.6" + wire width 64 $6\cia3__data_o$next[63:0]$10477 + attribute \src "issuer_ls180.v:164954.3-164993.6" + wire width 64 $6\msr3__data_o$next[63:0]$10486 + attribute \src "issuer_ls180.v:164876.17-164876.100" + wire $not$issuer_ls180.v:164876$10465_Y + attribute \src "issuer_ls180.v:164877.17-164877.103" + wire $not$issuer_ls180.v:164877$10466_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 64 output 3 \cia3__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 64 \cia3__data_o$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire input 2 \cia3__ren + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" + wire input 12 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" + wire input 1 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 64 input 11 \d_wr13__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire input 10 \d_wr13__wen + attribute \src "issuer_ls180.v:164833.7-164833.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 64 input 9 \msr3__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 64 output 5 \msr3__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 64 \msr3__data_o$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire input 4 \msr3__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire input 8 \msr3__wen + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 64 input 7 \nia3__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire input 6 \nia3__wen + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" + wire width 64 \reg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" + wire width 64 \reg$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" + wire \wr_detect + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" + wire \wr_detect$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + cell $not $not$issuer_ls180.v:164876$10465 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_detect + connect \Y $not$issuer_ls180.v:164876$10465_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + cell $not $not$issuer_ls180.v:164877$10466 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_detect$4 + connect \Y $not$issuer_ls180.v:164877$10466_Y + end + attribute \src "issuer_ls180.v:164833.7-164833.20" + process $proc$issuer_ls180.v:164833$10499 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "issuer_ls180.v:164840.14-164840.49" + process $proc$issuer_ls180.v:164840$10500 + assign { } { } + assign $1\cia3__data_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \cia3__data_o $1\cia3__data_o[63:0] + end + attribute \src "issuer_ls180.v:164857.14-164857.49" + process $proc$issuer_ls180.v:164857$10501 + assign { } { } + assign $1\msr3__data_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \msr3__data_o $1\msr3__data_o[63:0] + end + attribute \src "issuer_ls180.v:164869.14-164869.42" + process $proc$issuer_ls180.v:164869$10502 + assign { } { } + assign $1\reg[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \reg $1\reg[63:0] + end + attribute \src "issuer_ls180.v:164878.3-164879.25" + process $proc$issuer_ls180.v:164878$10467 + assign { } { } + assign $0\reg[63:0] \reg$next + sync posedge \coresync_clk + update \reg $0\reg[63:0] + end + attribute \src "issuer_ls180.v:164880.3-164881.41" + process $proc$issuer_ls180.v:164880$10468 + assign { } { } + assign $0\msr3__data_o[63:0] \msr3__data_o$next + sync posedge \coresync_clk + update \msr3__data_o $0\msr3__data_o[63:0] + end + attribute \src "issuer_ls180.v:164882.3-164883.41" + process $proc$issuer_ls180.v:164882$10469 + assign { } { } + assign $0\cia3__data_o[63:0] \cia3__data_o$next + sync posedge \coresync_clk + update \cia3__data_o $0\cia3__data_o[63:0] + end + attribute \src "issuer_ls180.v:164884.3-164923.6" + process $proc$issuer_ls180.v:164884$10470 + assign { } { } + assign { } { } + assign { } { } + assign $0\cia3__data_o$next[63:0]$10471 $6\cia3__data_o$next[63:0]$10477 + attribute \src "issuer_ls180.v:164885.5-164885.29" + switch \initial + attribute \src "issuer_ls180.v:164885.9-164885.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \cia3__ren + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\cia3__data_o$next[63:0]$10472 $5\cia3__data_o$next[63:0]$10476 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \nia3__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\cia3__data_o$next[63:0]$10473 \nia3__data_i + case + assign $2\cia3__data_o$next[63:0]$10473 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \msr3__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\cia3__data_o$next[63:0]$10474 \msr3__data_i + case + assign $3\cia3__data_o$next[63:0]$10474 $2\cia3__data_o$next[63:0]$10473 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \d_wr13__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\cia3__data_o$next[63:0]$10475 \d_wr13__data_i + case + assign $4\cia3__data_o$next[63:0]$10475 $3\cia3__data_o$next[63:0]$10474 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + switch \$1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\cia3__data_o$next[63:0]$10476 \reg + case + assign $5\cia3__data_o$next[63:0]$10476 $4\cia3__data_o$next[63:0]$10475 + end + case + assign $1\cia3__data_o$next[63:0]$10472 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $6\cia3__data_o$next[63:0]$10477 64'0000000000000000000000000000000000000000000000000000000000000000 + case + assign $6\cia3__data_o$next[63:0]$10477 $1\cia3__data_o$next[63:0]$10472 + end + sync always + update \cia3__data_o$next $0\cia3__data_o$next[63:0]$10471 + end + attribute \src "issuer_ls180.v:164924.3-164953.6" + process $proc$issuer_ls180.v:164924$10478 + assign { } { } + assign { } { } + assign $0\wr_detect[0:0] $1\wr_detect[0:0] + attribute \src "issuer_ls180.v:164925.5-164925.29" + switch \initial + attribute \src "issuer_ls180.v:164925.9-164925.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \cia3__ren + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\wr_detect[0:0] $4\wr_detect[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \nia3__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\wr_detect[0:0] 1'1 + case + assign $2\wr_detect[0:0] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \msr3__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\wr_detect[0:0] 1'1 + case + assign $3\wr_detect[0:0] $2\wr_detect[0:0] + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \d_wr13__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\wr_detect[0:0] 1'1 + case + assign $4\wr_detect[0:0] $3\wr_detect[0:0] + end + case + assign $1\wr_detect[0:0] 1'0 + end + sync always + update \wr_detect $0\wr_detect[0:0] + end + attribute \src "issuer_ls180.v:164954.3-164993.6" + process $proc$issuer_ls180.v:164954$10479 + assign { } { } + assign { } { } + assign { } { } + assign $0\msr3__data_o$next[63:0]$10480 $6\msr3__data_o$next[63:0]$10486 + attribute \src "issuer_ls180.v:164955.5-164955.29" + switch \initial + attribute \src "issuer_ls180.v:164955.9-164955.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \msr3__ren + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\msr3__data_o$next[63:0]$10481 $5\msr3__data_o$next[63:0]$10485 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \nia3__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\msr3__data_o$next[63:0]$10482 \nia3__data_i + case + assign $2\msr3__data_o$next[63:0]$10482 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \msr3__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\msr3__data_o$next[63:0]$10483 \msr3__data_i + case + assign $3\msr3__data_o$next[63:0]$10483 $2\msr3__data_o$next[63:0]$10482 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \d_wr13__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\msr3__data_o$next[63:0]$10484 \d_wr13__data_i + case + assign $4\msr3__data_o$next[63:0]$10484 $3\msr3__data_o$next[63:0]$10483 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + switch \$3 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\msr3__data_o$next[63:0]$10485 \reg + case + assign $5\msr3__data_o$next[63:0]$10485 $4\msr3__data_o$next[63:0]$10484 + end + case + assign $1\msr3__data_o$next[63:0]$10481 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $6\msr3__data_o$next[63:0]$10486 64'0000000000000000000000000000000000000000000000000000000000000000 + case + assign $6\msr3__data_o$next[63:0]$10486 $1\msr3__data_o$next[63:0]$10481 + end + sync always + update \msr3__data_o$next $0\msr3__data_o$next[63:0]$10480 + end + attribute \src "issuer_ls180.v:164994.3-165023.6" + process $proc$issuer_ls180.v:164994$10487 + assign { } { } + assign { } { } + assign $0\wr_detect$4[0:0]$10488 $1\wr_detect$4[0:0]$10489 + attribute \src "issuer_ls180.v:164995.5-164995.29" + switch \initial + attribute \src "issuer_ls180.v:164995.9-164995.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \msr3__ren + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\wr_detect$4[0:0]$10489 $4\wr_detect$4[0:0]$10492 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \nia3__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\wr_detect$4[0:0]$10490 1'1 + case + assign $2\wr_detect$4[0:0]$10490 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \msr3__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\wr_detect$4[0:0]$10491 1'1 + case + assign $3\wr_detect$4[0:0]$10491 $2\wr_detect$4[0:0]$10490 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \d_wr13__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\wr_detect$4[0:0]$10492 1'1 + case + assign $4\wr_detect$4[0:0]$10492 $3\wr_detect$4[0:0]$10491 + end + case + assign $1\wr_detect$4[0:0]$10489 1'0 + end + sync always + update \wr_detect$4 $0\wr_detect$4[0:0]$10488 + end + attribute \src "issuer_ls180.v:165024.3-165050.6" + process $proc$issuer_ls180.v:165024$10493 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\reg$next[63:0]$10494 $4\reg$next[63:0]$10498 + attribute \src "issuer_ls180.v:165025.5-165025.29" + switch \initial + attribute \src "issuer_ls180.v:165025.9-165025.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" + switch \nia3__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\reg$next[63:0]$10495 \nia3__data_i + case + assign $1\reg$next[63:0]$10495 \reg + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" + switch \msr3__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\reg$next[63:0]$10496 \msr3__data_i + case + assign $2\reg$next[63:0]$10496 $1\reg$next[63:0]$10495 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" + switch \d_wr13__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\reg$next[63:0]$10497 \d_wr13__data_i + case + assign $3\reg$next[63:0]$10497 $2\reg$next[63:0]$10496 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\reg$next[63:0]$10498 64'0000000000000000000000000000000000000000000000000000000000000000 + case + assign $4\reg$next[63:0]$10498 $3\reg$next[63:0]$10497 + end + sync always + update \reg$next $0\reg$next[63:0]$10494 + end + connect \$1 $not$issuer_ls180.v:164876$10465_Y + connect \$3 $not$issuer_ls180.v:164877$10466_Y +end +attribute \src "issuer_ls180.v:165055.1-165526.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.cr.reg_4" +attribute \generator "nMigen" +module \reg_4 + attribute \src "issuer_ls180.v:165056.7-165056.20" + wire $0\initial[0:0] + attribute \src "issuer_ls180.v:165456.3-165495.6" + wire width 4 $0\r24__data_o$next[3:0]$10572 + attribute \src "issuer_ls180.v:165139.3-165140.39" + wire width 4 $0\r24__data_o[3:0] + attribute \src "issuer_ls180.v:165386.3-165425.6" + wire width 4 $0\r4__data_o$next[3:0]$10558 + attribute \src "issuer_ls180.v:165141.3-165142.37" + wire width 4 $0\r4__data_o[3:0] + attribute \src "issuer_ls180.v:165219.3-165245.6" + wire width 4 $0\reg$next[3:0]$10524 + attribute \src "issuer_ls180.v:165137.3-165138.25" + wire width 4 $0\reg[3:0] + attribute \src "issuer_ls180.v:165149.3-165188.6" + wire width 4 $0\src14__data_o$next[3:0]$10515 + attribute \src "issuer_ls180.v:165147.3-165148.43" + wire width 4 $0\src14__data_o[3:0] + attribute \src "issuer_ls180.v:165246.3-165285.6" + wire width 4 $0\src24__data_o$next[3:0]$10530 + attribute \src "issuer_ls180.v:165145.3-165146.43" + wire width 4 $0\src24__data_o[3:0] + attribute \src "issuer_ls180.v:165316.3-165355.6" + wire width 4 $0\src34__data_o$next[3:0]$10544 + attribute \src "issuer_ls180.v:165143.3-165144.43" + wire width 4 $0\src34__data_o[3:0] + attribute \src "issuer_ls180.v:165426.3-165455.6" + wire $0\wr_detect$10[0:0]$10566 + attribute \src "issuer_ls180.v:165496.3-165525.6" + wire $0\wr_detect$13[0:0]$10580 + attribute \src "issuer_ls180.v:165286.3-165315.6" + wire $0\wr_detect$4[0:0]$10538 + attribute \src "issuer_ls180.v:165356.3-165385.6" + wire $0\wr_detect$7[0:0]$10552 + attribute \src "issuer_ls180.v:165189.3-165218.6" + wire $0\wr_detect[0:0] + attribute \src "issuer_ls180.v:165456.3-165495.6" + wire width 4 $1\r24__data_o$next[3:0]$10573 + attribute \src "issuer_ls180.v:165081.13-165081.31" + wire width 4 $1\r24__data_o[3:0] + attribute \src "issuer_ls180.v:165386.3-165425.6" + wire width 4 $1\r4__data_o$next[3:0]$10559 + attribute \src "issuer_ls180.v:165088.13-165088.30" + wire width 4 $1\r4__data_o[3:0] + attribute \src "issuer_ls180.v:165219.3-165245.6" + wire width 4 $1\reg$next[3:0]$10525 + attribute \src "issuer_ls180.v:165094.13-165094.25" + wire width 4 $1\reg[3:0] + attribute \src "issuer_ls180.v:165149.3-165188.6" + wire width 4 $1\src14__data_o$next[3:0]$10516 + attribute \src "issuer_ls180.v:165099.13-165099.33" + wire width 4 $1\src14__data_o[3:0] + attribute \src "issuer_ls180.v:165246.3-165285.6" + wire width 4 $1\src24__data_o$next[3:0]$10531 + attribute \src "issuer_ls180.v:165106.13-165106.33" + wire width 4 $1\src24__data_o[3:0] + attribute \src "issuer_ls180.v:165316.3-165355.6" + wire width 4 $1\src34__data_o$next[3:0]$10545 + attribute \src "issuer_ls180.v:165113.13-165113.33" + wire width 4 $1\src34__data_o[3:0] + attribute \src "issuer_ls180.v:165426.3-165455.6" + wire $1\wr_detect$10[0:0]$10567 + attribute \src "issuer_ls180.v:165496.3-165525.6" + wire $1\wr_detect$13[0:0]$10581 + attribute \src "issuer_ls180.v:165286.3-165315.6" + wire $1\wr_detect$4[0:0]$10539 + attribute \src "issuer_ls180.v:165356.3-165385.6" + wire $1\wr_detect$7[0:0]$10553 + attribute \src "issuer_ls180.v:165189.3-165218.6" + wire $1\wr_detect[0:0] + attribute \src "issuer_ls180.v:165456.3-165495.6" + wire width 4 $2\r24__data_o$next[3:0]$10574 + attribute \src "issuer_ls180.v:165386.3-165425.6" + wire width 4 $2\r4__data_o$next[3:0]$10560 + attribute \src "issuer_ls180.v:165219.3-165245.6" + wire width 4 $2\reg$next[3:0]$10526 + attribute \src "issuer_ls180.v:165149.3-165188.6" + wire width 4 $2\src14__data_o$next[3:0]$10517 + attribute \src "issuer_ls180.v:165246.3-165285.6" + wire width 4 $2\src24__data_o$next[3:0]$10532 + attribute \src "issuer_ls180.v:165316.3-165355.6" + wire width 4 $2\src34__data_o$next[3:0]$10546 + attribute \src "issuer_ls180.v:165426.3-165455.6" + wire $2\wr_detect$10[0:0]$10568 + attribute \src "issuer_ls180.v:165496.3-165525.6" + wire $2\wr_detect$13[0:0]$10582 + attribute \src "issuer_ls180.v:165286.3-165315.6" + wire $2\wr_detect$4[0:0]$10540 + attribute \src "issuer_ls180.v:165356.3-165385.6" + wire $2\wr_detect$7[0:0]$10554 + attribute \src "issuer_ls180.v:165189.3-165218.6" + wire $2\wr_detect[0:0] + attribute \src "issuer_ls180.v:165456.3-165495.6" + wire width 4 $3\r24__data_o$next[3:0]$10575 + attribute \src "issuer_ls180.v:165386.3-165425.6" + wire width 4 $3\r4__data_o$next[3:0]$10561 + attribute \src "issuer_ls180.v:165219.3-165245.6" + wire width 4 $3\reg$next[3:0]$10527 + attribute \src "issuer_ls180.v:165149.3-165188.6" + wire width 4 $3\src14__data_o$next[3:0]$10518 + attribute \src "issuer_ls180.v:165246.3-165285.6" + wire width 4 $3\src24__data_o$next[3:0]$10533 + attribute \src "issuer_ls180.v:165316.3-165355.6" + wire width 4 $3\src34__data_o$next[3:0]$10547 + attribute \src "issuer_ls180.v:165426.3-165455.6" + wire $3\wr_detect$10[0:0]$10569 + attribute \src "issuer_ls180.v:165496.3-165525.6" + wire $3\wr_detect$13[0:0]$10583 + attribute \src "issuer_ls180.v:165286.3-165315.6" + wire $3\wr_detect$4[0:0]$10541 + attribute \src "issuer_ls180.v:165356.3-165385.6" + wire $3\wr_detect$7[0:0]$10555 + attribute \src "issuer_ls180.v:165189.3-165218.6" + wire $3\wr_detect[0:0] + attribute \src "issuer_ls180.v:165456.3-165495.6" + wire width 4 $4\r24__data_o$next[3:0]$10576 + attribute \src "issuer_ls180.v:165386.3-165425.6" + wire width 4 $4\r4__data_o$next[3:0]$10562 + attribute \src "issuer_ls180.v:165219.3-165245.6" + wire width 4 $4\reg$next[3:0]$10528 + attribute \src "issuer_ls180.v:165149.3-165188.6" + wire width 4 $4\src14__data_o$next[3:0]$10519 + attribute \src "issuer_ls180.v:165246.3-165285.6" + wire width 4 $4\src24__data_o$next[3:0]$10534 + attribute \src "issuer_ls180.v:165316.3-165355.6" + wire width 4 $4\src34__data_o$next[3:0]$10548 + attribute \src "issuer_ls180.v:165426.3-165455.6" + wire $4\wr_detect$10[0:0]$10570 + attribute \src "issuer_ls180.v:165496.3-165525.6" + wire $4\wr_detect$13[0:0]$10584 + attribute \src "issuer_ls180.v:165286.3-165315.6" + wire $4\wr_detect$4[0:0]$10542 + attribute \src "issuer_ls180.v:165356.3-165385.6" + wire $4\wr_detect$7[0:0]$10556 + attribute \src "issuer_ls180.v:165189.3-165218.6" + wire $4\wr_detect[0:0] + attribute \src "issuer_ls180.v:165456.3-165495.6" + wire width 4 $5\r24__data_o$next[3:0]$10577 + attribute \src "issuer_ls180.v:165386.3-165425.6" + wire width 4 $5\r4__data_o$next[3:0]$10563 + attribute \src "issuer_ls180.v:165149.3-165188.6" + wire width 4 $5\src14__data_o$next[3:0]$10520 + attribute \src "issuer_ls180.v:165246.3-165285.6" + wire width 4 $5\src24__data_o$next[3:0]$10535 + attribute \src "issuer_ls180.v:165316.3-165355.6" + wire width 4 $5\src34__data_o$next[3:0]$10549 + attribute \src "issuer_ls180.v:165456.3-165495.6" + wire width 4 $6\r24__data_o$next[3:0]$10578 + attribute \src "issuer_ls180.v:165386.3-165425.6" + wire width 4 $6\r4__data_o$next[3:0]$10564 + attribute \src "issuer_ls180.v:165149.3-165188.6" + wire width 4 $6\src14__data_o$next[3:0]$10521 + attribute \src "issuer_ls180.v:165246.3-165285.6" + wire width 4 $6\src24__data_o$next[3:0]$10536 + attribute \src "issuer_ls180.v:165316.3-165355.6" + wire width 4 $6\src34__data_o$next[3:0]$10550 + attribute \src "issuer_ls180.v:165132.17-165132.104" + wire $not$issuer_ls180.v:165132$10503_Y + attribute \src "issuer_ls180.v:165133.18-165133.105" + wire $not$issuer_ls180.v:165133$10504_Y + attribute \src "issuer_ls180.v:165134.17-165134.100" + wire $not$issuer_ls180.v:165134$10505_Y + attribute \src "issuer_ls180.v:165135.17-165135.103" + wire $not$issuer_ls180.v:165135$10506_Y + attribute \src "issuer_ls180.v:165136.17-165136.103" + wire $not$issuer_ls180.v:165136$10507_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + wire \$12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + wire \$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + wire \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" + wire input 18 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" + wire input 1 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 input 9 \dest14__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire input 8 \dest14__wen + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 input 11 \dest24__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire input 10 \dest24__wen + attribute \src "issuer_ls180.v:165056.7-165056.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 output 14 \r24__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 \r24__data_o$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire input 15 \r24__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 output 12 \r4__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 \r4__data_o$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire input 13 \r4__ren + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" + wire width 4 \reg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" + wire width 4 \reg$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 output 3 \src14__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 \src14__data_o$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire input 2 \src14__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 output 5 \src24__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 \src24__data_o$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire input 4 \src24__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 output 7 \src34__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 \src34__data_o$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire input 6 \src34__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 input 16 \w4__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire input 17 \w4__wen + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" + wire \wr_detect + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" + wire \wr_detect$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" + wire \wr_detect$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" + wire \wr_detect$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" + wire \wr_detect$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + cell $not $not$issuer_ls180.v:165132$10503 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_detect$10 + connect \Y $not$issuer_ls180.v:165132$10503_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + cell $not $not$issuer_ls180.v:165133$10504 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_detect$13 + connect \Y $not$issuer_ls180.v:165133$10504_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + cell $not $not$issuer_ls180.v:165134$10505 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_detect + connect \Y $not$issuer_ls180.v:165134$10505_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + cell $not $not$issuer_ls180.v:165135$10506 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_detect$4 + connect \Y $not$issuer_ls180.v:165135$10506_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + cell $not $not$issuer_ls180.v:165136$10507 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_detect$7 + connect \Y $not$issuer_ls180.v:165136$10507_Y + end + attribute \src "issuer_ls180.v:165056.7-165056.20" + process $proc$issuer_ls180.v:165056$10585 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "issuer_ls180.v:165081.13-165081.31" + process $proc$issuer_ls180.v:165081$10586 + assign { } { } + assign $1\r24__data_o[3:0] 4'0000 + sync always + sync init + update \r24__data_o $1\r24__data_o[3:0] + end + attribute \src "issuer_ls180.v:165088.13-165088.30" + process $proc$issuer_ls180.v:165088$10587 + assign { } { } + assign $1\r4__data_o[3:0] 4'0000 + sync always + sync init + update \r4__data_o $1\r4__data_o[3:0] + end + attribute \src "issuer_ls180.v:165094.13-165094.25" + process $proc$issuer_ls180.v:165094$10588 + assign { } { } + assign $1\reg[3:0] 4'0000 + sync always + sync init + update \reg $1\reg[3:0] + end + attribute \src "issuer_ls180.v:165099.13-165099.33" + process $proc$issuer_ls180.v:165099$10589 + assign { } { } + assign $1\src14__data_o[3:0] 4'0000 + sync always + sync init + update \src14__data_o $1\src14__data_o[3:0] + end + attribute \src "issuer_ls180.v:165106.13-165106.33" + process $proc$issuer_ls180.v:165106$10590 + assign { } { } + assign $1\src24__data_o[3:0] 4'0000 + sync always + sync init + update \src24__data_o $1\src24__data_o[3:0] + end + attribute \src "issuer_ls180.v:165113.13-165113.33" + process $proc$issuer_ls180.v:165113$10591 + assign { } { } + assign $1\src34__data_o[3:0] 4'0000 + sync always + sync init + update \src34__data_o $1\src34__data_o[3:0] + end + attribute \src "issuer_ls180.v:165137.3-165138.25" + process $proc$issuer_ls180.v:165137$10508 + assign { } { } + assign $0\reg[3:0] \reg$next + sync posedge \coresync_clk + update \reg $0\reg[3:0] + end + attribute \src "issuer_ls180.v:165139.3-165140.39" + process $proc$issuer_ls180.v:165139$10509 + assign { } { } + assign $0\r24__data_o[3:0] \r24__data_o$next + sync posedge \coresync_clk + update \r24__data_o $0\r24__data_o[3:0] + end + attribute \src "issuer_ls180.v:165141.3-165142.37" + process $proc$issuer_ls180.v:165141$10510 + assign { } { } + assign $0\r4__data_o[3:0] \r4__data_o$next + sync posedge \coresync_clk + update \r4__data_o $0\r4__data_o[3:0] + end + attribute \src "issuer_ls180.v:165143.3-165144.43" + process $proc$issuer_ls180.v:165143$10511 + assign { } { } + assign $0\src34__data_o[3:0] \src34__data_o$next + sync posedge \coresync_clk + update \src34__data_o $0\src34__data_o[3:0] + end + attribute \src "issuer_ls180.v:165145.3-165146.43" + process $proc$issuer_ls180.v:165145$10512 + assign { } { } + assign $0\src24__data_o[3:0] \src24__data_o$next + sync posedge \coresync_clk + update \src24__data_o $0\src24__data_o[3:0] + end + attribute \src "issuer_ls180.v:165147.3-165148.43" + process $proc$issuer_ls180.v:165147$10513 + assign { } { } + assign $0\src14__data_o[3:0] \src14__data_o$next + sync posedge \coresync_clk + update \src14__data_o $0\src14__data_o[3:0] + end + attribute \src "issuer_ls180.v:165149.3-165188.6" + process $proc$issuer_ls180.v:165149$10514 + assign { } { } + assign { } { } + assign { } { } + assign $0\src14__data_o$next[3:0]$10515 $6\src14__data_o$next[3:0]$10521 + attribute \src "issuer_ls180.v:165150.5-165150.29" + switch \initial + attribute \src "issuer_ls180.v:165150.9-165150.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \src14__ren + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\src14__data_o$next[3:0]$10516 $5\src14__data_o$next[3:0]$10520 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest14__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\src14__data_o$next[3:0]$10517 \dest14__data_i + case + assign $2\src14__data_o$next[3:0]$10517 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest24__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\src14__data_o$next[3:0]$10518 \dest24__data_i + case + assign $3\src14__data_o$next[3:0]$10518 $2\src14__data_o$next[3:0]$10517 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w4__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\src14__data_o$next[3:0]$10519 \w4__data_i + case + assign $4\src14__data_o$next[3:0]$10519 $3\src14__data_o$next[3:0]$10518 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + switch \$1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\src14__data_o$next[3:0]$10520 \reg + case + assign $5\src14__data_o$next[3:0]$10520 $4\src14__data_o$next[3:0]$10519 + end + case + assign $1\src14__data_o$next[3:0]$10516 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $6\src14__data_o$next[3:0]$10521 4'0000 + case + assign $6\src14__data_o$next[3:0]$10521 $1\src14__data_o$next[3:0]$10516 + end + sync always + update \src14__data_o$next $0\src14__data_o$next[3:0]$10515 + end + attribute \src "issuer_ls180.v:165189.3-165218.6" + process $proc$issuer_ls180.v:165189$10522 + assign { } { } + assign { } { } + assign $0\wr_detect[0:0] $1\wr_detect[0:0] + attribute \src "issuer_ls180.v:165190.5-165190.29" + switch \initial + attribute \src "issuer_ls180.v:165190.9-165190.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \src14__ren + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\wr_detect[0:0] $4\wr_detect[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest14__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\wr_detect[0:0] 1'1 + case + assign $2\wr_detect[0:0] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest24__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\wr_detect[0:0] 1'1 + case + assign $3\wr_detect[0:0] $2\wr_detect[0:0] + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w4__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\wr_detect[0:0] 1'1 + case + assign $4\wr_detect[0:0] $3\wr_detect[0:0] + end + case + assign $1\wr_detect[0:0] 1'0 + end + sync always + update \wr_detect $0\wr_detect[0:0] + end + attribute \src "issuer_ls180.v:165219.3-165245.6" + process $proc$issuer_ls180.v:165219$10523 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\reg$next[3:0]$10524 $4\reg$next[3:0]$10528 + attribute \src "issuer_ls180.v:165220.5-165220.29" + switch \initial + attribute \src "issuer_ls180.v:165220.9-165220.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" + switch \dest14__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\reg$next[3:0]$10525 \dest14__data_i + case + assign $1\reg$next[3:0]$10525 \reg + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" + switch \dest24__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\reg$next[3:0]$10526 \dest24__data_i + case + assign $2\reg$next[3:0]$10526 $1\reg$next[3:0]$10525 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" + switch \w4__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\reg$next[3:0]$10527 \w4__data_i + case + assign $3\reg$next[3:0]$10527 $2\reg$next[3:0]$10526 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\reg$next[3:0]$10528 4'0000 + case + assign $4\reg$next[3:0]$10528 $3\reg$next[3:0]$10527 + end + sync always + update \reg$next $0\reg$next[3:0]$10524 + end + attribute \src "issuer_ls180.v:165246.3-165285.6" + process $proc$issuer_ls180.v:165246$10529 + assign { } { } + assign { } { } + assign { } { } + assign $0\src24__data_o$next[3:0]$10530 $6\src24__data_o$next[3:0]$10536 + attribute \src "issuer_ls180.v:165247.5-165247.29" + switch \initial + attribute \src "issuer_ls180.v:165247.9-165247.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \src24__ren + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\src24__data_o$next[3:0]$10531 $5\src24__data_o$next[3:0]$10535 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest14__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\src24__data_o$next[3:0]$10532 \dest14__data_i + case + assign $2\src24__data_o$next[3:0]$10532 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest24__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\src24__data_o$next[3:0]$10533 \dest24__data_i + case + assign $3\src24__data_o$next[3:0]$10533 $2\src24__data_o$next[3:0]$10532 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w4__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\src24__data_o$next[3:0]$10534 \w4__data_i + case + assign $4\src24__data_o$next[3:0]$10534 $3\src24__data_o$next[3:0]$10533 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + switch \$3 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\src24__data_o$next[3:0]$10535 \reg + case + assign $5\src24__data_o$next[3:0]$10535 $4\src24__data_o$next[3:0]$10534 + end + case + assign $1\src24__data_o$next[3:0]$10531 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $6\src24__data_o$next[3:0]$10536 4'0000 + case + assign $6\src24__data_o$next[3:0]$10536 $1\src24__data_o$next[3:0]$10531 + end + sync always + update \src24__data_o$next $0\src24__data_o$next[3:0]$10530 + end + attribute \src "issuer_ls180.v:165286.3-165315.6" + process $proc$issuer_ls180.v:165286$10537 + assign { } { } + assign { } { } + assign $0\wr_detect$4[0:0]$10538 $1\wr_detect$4[0:0]$10539 + attribute \src "issuer_ls180.v:165287.5-165287.29" + switch \initial + attribute \src "issuer_ls180.v:165287.9-165287.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \src24__ren + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\wr_detect$4[0:0]$10539 $4\wr_detect$4[0:0]$10542 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest14__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\wr_detect$4[0:0]$10540 1'1 + case + assign $2\wr_detect$4[0:0]$10540 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest24__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\wr_detect$4[0:0]$10541 1'1 + case + assign $3\wr_detect$4[0:0]$10541 $2\wr_detect$4[0:0]$10540 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w4__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\wr_detect$4[0:0]$10542 1'1 + case + assign $4\wr_detect$4[0:0]$10542 $3\wr_detect$4[0:0]$10541 + end + case + assign $1\wr_detect$4[0:0]$10539 1'0 + end + sync always + update \wr_detect$4 $0\wr_detect$4[0:0]$10538 + end + attribute \src "issuer_ls180.v:165316.3-165355.6" + process $proc$issuer_ls180.v:165316$10543 + assign { } { } + assign { } { } + assign { } { } + assign $0\src34__data_o$next[3:0]$10544 $6\src34__data_o$next[3:0]$10550 + attribute \src "issuer_ls180.v:165317.5-165317.29" + switch \initial + attribute \src "issuer_ls180.v:165317.9-165317.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \src34__ren + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\src34__data_o$next[3:0]$10545 $5\src34__data_o$next[3:0]$10549 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest14__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\src34__data_o$next[3:0]$10546 \dest14__data_i + case + assign $2\src34__data_o$next[3:0]$10546 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest24__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\src34__data_o$next[3:0]$10547 \dest24__data_i + case + assign $3\src34__data_o$next[3:0]$10547 $2\src34__data_o$next[3:0]$10546 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w4__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\src34__data_o$next[3:0]$10548 \w4__data_i + case + assign $4\src34__data_o$next[3:0]$10548 $3\src34__data_o$next[3:0]$10547 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + switch \$6 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\src34__data_o$next[3:0]$10549 \reg + case + assign $5\src34__data_o$next[3:0]$10549 $4\src34__data_o$next[3:0]$10548 + end + case + assign $1\src34__data_o$next[3:0]$10545 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $6\src34__data_o$next[3:0]$10550 4'0000 + case + assign $6\src34__data_o$next[3:0]$10550 $1\src34__data_o$next[3:0]$10545 + end + sync always + update \src34__data_o$next $0\src34__data_o$next[3:0]$10544 + end + attribute \src "issuer_ls180.v:165356.3-165385.6" + process $proc$issuer_ls180.v:165356$10551 + assign { } { } + assign { } { } + assign $0\wr_detect$7[0:0]$10552 $1\wr_detect$7[0:0]$10553 + attribute \src "issuer_ls180.v:165357.5-165357.29" + switch \initial + attribute \src "issuer_ls180.v:165357.9-165357.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \src34__ren + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\wr_detect$7[0:0]$10553 $4\wr_detect$7[0:0]$10556 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest14__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\wr_detect$7[0:0]$10554 1'1 + case + assign $2\wr_detect$7[0:0]$10554 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest24__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\wr_detect$7[0:0]$10555 1'1 + case + assign $3\wr_detect$7[0:0]$10555 $2\wr_detect$7[0:0]$10554 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w4__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\wr_detect$7[0:0]$10556 1'1 + case + assign $4\wr_detect$7[0:0]$10556 $3\wr_detect$7[0:0]$10555 + end + case + assign $1\wr_detect$7[0:0]$10553 1'0 + end + sync always + update \wr_detect$7 $0\wr_detect$7[0:0]$10552 + end + attribute \src "issuer_ls180.v:165386.3-165425.6" + process $proc$issuer_ls180.v:165386$10557 + assign { } { } + assign { } { } + assign { } { } + assign $0\r4__data_o$next[3:0]$10558 $6\r4__data_o$next[3:0]$10564 + attribute \src "issuer_ls180.v:165387.5-165387.29" + switch \initial + attribute \src "issuer_ls180.v:165387.9-165387.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \r4__ren + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\r4__data_o$next[3:0]$10559 $5\r4__data_o$next[3:0]$10563 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest14__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\r4__data_o$next[3:0]$10560 \dest14__data_i + case + assign $2\r4__data_o$next[3:0]$10560 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest24__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\r4__data_o$next[3:0]$10561 \dest24__data_i + case + assign $3\r4__data_o$next[3:0]$10561 $2\r4__data_o$next[3:0]$10560 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w4__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\r4__data_o$next[3:0]$10562 \w4__data_i + case + assign $4\r4__data_o$next[3:0]$10562 $3\r4__data_o$next[3:0]$10561 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + switch \$9 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\r4__data_o$next[3:0]$10563 \reg + case + assign $5\r4__data_o$next[3:0]$10563 $4\r4__data_o$next[3:0]$10562 + end + case + assign $1\r4__data_o$next[3:0]$10559 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $6\r4__data_o$next[3:0]$10564 4'0000 + case + assign $6\r4__data_o$next[3:0]$10564 $1\r4__data_o$next[3:0]$10559 + end + sync always + update \r4__data_o$next $0\r4__data_o$next[3:0]$10558 + end + attribute \src "issuer_ls180.v:165426.3-165455.6" + process $proc$issuer_ls180.v:165426$10565 + assign { } { } + assign { } { } + assign $0\wr_detect$10[0:0]$10566 $1\wr_detect$10[0:0]$10567 + attribute \src "issuer_ls180.v:165427.5-165427.29" + switch \initial + attribute \src "issuer_ls180.v:165427.9-165427.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \r4__ren + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\wr_detect$10[0:0]$10567 $4\wr_detect$10[0:0]$10570 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest14__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\wr_detect$10[0:0]$10568 1'1 + case + assign $2\wr_detect$10[0:0]$10568 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest24__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\wr_detect$10[0:0]$10569 1'1 + case + assign $3\wr_detect$10[0:0]$10569 $2\wr_detect$10[0:0]$10568 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w4__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\wr_detect$10[0:0]$10570 1'1 + case + assign $4\wr_detect$10[0:0]$10570 $3\wr_detect$10[0:0]$10569 + end + case + assign $1\wr_detect$10[0:0]$10567 1'0 + end + sync always + update \wr_detect$10 $0\wr_detect$10[0:0]$10566 + end + attribute \src "issuer_ls180.v:165456.3-165495.6" + process $proc$issuer_ls180.v:165456$10571 + assign { } { } + assign { } { } + assign { } { } + assign $0\r24__data_o$next[3:0]$10572 $6\r24__data_o$next[3:0]$10578 + attribute \src "issuer_ls180.v:165457.5-165457.29" + switch \initial + attribute \src "issuer_ls180.v:165457.9-165457.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \r24__ren + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\r24__data_o$next[3:0]$10573 $5\r24__data_o$next[3:0]$10577 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest14__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\r24__data_o$next[3:0]$10574 \dest14__data_i + case + assign $2\r24__data_o$next[3:0]$10574 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest24__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\r24__data_o$next[3:0]$10575 \dest24__data_i + case + assign $3\r24__data_o$next[3:0]$10575 $2\r24__data_o$next[3:0]$10574 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w4__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\r24__data_o$next[3:0]$10576 \w4__data_i + case + assign $4\r24__data_o$next[3:0]$10576 $3\r24__data_o$next[3:0]$10575 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + switch \$12 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\r24__data_o$next[3:0]$10577 \reg + case + assign $5\r24__data_o$next[3:0]$10577 $4\r24__data_o$next[3:0]$10576 + end + case + assign $1\r24__data_o$next[3:0]$10573 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $6\r24__data_o$next[3:0]$10578 4'0000 + case + assign $6\r24__data_o$next[3:0]$10578 $1\r24__data_o$next[3:0]$10573 + end + sync always + update \r24__data_o$next $0\r24__data_o$next[3:0]$10572 + end + attribute \src "issuer_ls180.v:165496.3-165525.6" + process $proc$issuer_ls180.v:165496$10579 + assign { } { } + assign { } { } + assign $0\wr_detect$13[0:0]$10580 $1\wr_detect$13[0:0]$10581 + attribute \src "issuer_ls180.v:165497.5-165497.29" + switch \initial + attribute \src "issuer_ls180.v:165497.9-165497.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \r24__ren + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\wr_detect$13[0:0]$10581 $4\wr_detect$13[0:0]$10584 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest14__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\wr_detect$13[0:0]$10582 1'1 + case + assign $2\wr_detect$13[0:0]$10582 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest24__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\wr_detect$13[0:0]$10583 1'1 + case + assign $3\wr_detect$13[0:0]$10583 $2\wr_detect$13[0:0]$10582 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w4__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\wr_detect$13[0:0]$10584 1'1 + case + assign $4\wr_detect$13[0:0]$10584 $3\wr_detect$13[0:0]$10583 + end + case + assign $1\wr_detect$13[0:0]$10581 1'0 + end + sync always + update \wr_detect$13 $0\wr_detect$13[0:0]$10580 + end + connect \$9 $not$issuer_ls180.v:165132$10503_Y + connect \$12 $not$issuer_ls180.v:165133$10504_Y + connect \$1 $not$issuer_ls180.v:165134$10505_Y + connect \$3 $not$issuer_ls180.v:165135$10506_Y + connect \$6 $not$issuer_ls180.v:165136$10507_Y +end +attribute \src "issuer_ls180.v:165530.1-166001.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.cr.reg_5" +attribute \generator "nMigen" +module \reg_5 + attribute \src "issuer_ls180.v:165531.7-165531.20" + wire $0\initial[0:0] + attribute \src "issuer_ls180.v:165931.3-165970.6" + wire width 4 $0\r25__data_o$next[3:0]$10661 + attribute \src "issuer_ls180.v:165614.3-165615.39" + wire width 4 $0\r25__data_o[3:0] + attribute \src "issuer_ls180.v:165861.3-165900.6" + wire width 4 $0\r5__data_o$next[3:0]$10647 + attribute \src "issuer_ls180.v:165616.3-165617.37" + wire width 4 $0\r5__data_o[3:0] + attribute \src "issuer_ls180.v:165694.3-165720.6" + wire width 4 $0\reg$next[3:0]$10613 + attribute \src "issuer_ls180.v:165612.3-165613.25" + wire width 4 $0\reg[3:0] + attribute \src "issuer_ls180.v:165624.3-165663.6" + wire width 4 $0\src15__data_o$next[3:0]$10604 + attribute \src "issuer_ls180.v:165622.3-165623.43" + wire width 4 $0\src15__data_o[3:0] + attribute \src "issuer_ls180.v:165721.3-165760.6" + wire width 4 $0\src25__data_o$next[3:0]$10619 + attribute \src "issuer_ls180.v:165620.3-165621.43" + wire width 4 $0\src25__data_o[3:0] + attribute \src "issuer_ls180.v:165791.3-165830.6" + wire width 4 $0\src35__data_o$next[3:0]$10633 + attribute \src "issuer_ls180.v:165618.3-165619.43" + wire width 4 $0\src35__data_o[3:0] + attribute \src "issuer_ls180.v:165901.3-165930.6" + wire $0\wr_detect$10[0:0]$10655 + attribute \src "issuer_ls180.v:165971.3-166000.6" + wire $0\wr_detect$13[0:0]$10669 + attribute \src "issuer_ls180.v:165761.3-165790.6" + wire $0\wr_detect$4[0:0]$10627 + attribute \src "issuer_ls180.v:165831.3-165860.6" + wire $0\wr_detect$7[0:0]$10641 + attribute \src "issuer_ls180.v:165664.3-165693.6" + wire $0\wr_detect[0:0] + attribute \src "issuer_ls180.v:165931.3-165970.6" + wire width 4 $1\r25__data_o$next[3:0]$10662 + attribute \src "issuer_ls180.v:165556.13-165556.31" + wire width 4 $1\r25__data_o[3:0] + attribute \src "issuer_ls180.v:165861.3-165900.6" + wire width 4 $1\r5__data_o$next[3:0]$10648 + attribute \src "issuer_ls180.v:165563.13-165563.30" + wire width 4 $1\r5__data_o[3:0] + attribute \src "issuer_ls180.v:165694.3-165720.6" + wire width 4 $1\reg$next[3:0]$10614 + attribute \src "issuer_ls180.v:165569.13-165569.25" + wire width 4 $1\reg[3:0] + attribute \src "issuer_ls180.v:165624.3-165663.6" + wire width 4 $1\src15__data_o$next[3:0]$10605 + attribute \src "issuer_ls180.v:165574.13-165574.33" + wire width 4 $1\src15__data_o[3:0] + attribute \src "issuer_ls180.v:165721.3-165760.6" + wire width 4 $1\src25__data_o$next[3:0]$10620 + attribute \src "issuer_ls180.v:165581.13-165581.33" + wire width 4 $1\src25__data_o[3:0] + attribute \src "issuer_ls180.v:165791.3-165830.6" + wire width 4 $1\src35__data_o$next[3:0]$10634 + attribute \src "issuer_ls180.v:165588.13-165588.33" + wire width 4 $1\src35__data_o[3:0] + attribute \src "issuer_ls180.v:165901.3-165930.6" + wire $1\wr_detect$10[0:0]$10656 + attribute \src "issuer_ls180.v:165971.3-166000.6" + wire $1\wr_detect$13[0:0]$10670 + attribute \src "issuer_ls180.v:165761.3-165790.6" + wire $1\wr_detect$4[0:0]$10628 + attribute \src "issuer_ls180.v:165831.3-165860.6" + wire $1\wr_detect$7[0:0]$10642 + attribute \src "issuer_ls180.v:165664.3-165693.6" + wire $1\wr_detect[0:0] + attribute \src "issuer_ls180.v:165931.3-165970.6" + wire width 4 $2\r25__data_o$next[3:0]$10663 + attribute \src "issuer_ls180.v:165861.3-165900.6" + wire width 4 $2\r5__data_o$next[3:0]$10649 + attribute \src "issuer_ls180.v:165694.3-165720.6" + wire width 4 $2\reg$next[3:0]$10615 + attribute \src "issuer_ls180.v:165624.3-165663.6" + wire width 4 $2\src15__data_o$next[3:0]$10606 + attribute \src "issuer_ls180.v:165721.3-165760.6" + wire width 4 $2\src25__data_o$next[3:0]$10621 + attribute \src "issuer_ls180.v:165791.3-165830.6" + wire width 4 $2\src35__data_o$next[3:0]$10635 + attribute \src "issuer_ls180.v:165901.3-165930.6" + wire $2\wr_detect$10[0:0]$10657 + attribute \src "issuer_ls180.v:165971.3-166000.6" + wire $2\wr_detect$13[0:0]$10671 + attribute \src "issuer_ls180.v:165761.3-165790.6" + wire $2\wr_detect$4[0:0]$10629 + attribute \src "issuer_ls180.v:165831.3-165860.6" + wire $2\wr_detect$7[0:0]$10643 + attribute \src "issuer_ls180.v:165664.3-165693.6" + wire $2\wr_detect[0:0] + attribute \src "issuer_ls180.v:165931.3-165970.6" + wire width 4 $3\r25__data_o$next[3:0]$10664 + attribute \src "issuer_ls180.v:165861.3-165900.6" + wire width 4 $3\r5__data_o$next[3:0]$10650 + attribute \src "issuer_ls180.v:165694.3-165720.6" + wire width 4 $3\reg$next[3:0]$10616 + attribute \src "issuer_ls180.v:165624.3-165663.6" + wire width 4 $3\src15__data_o$next[3:0]$10607 + attribute \src "issuer_ls180.v:165721.3-165760.6" + wire width 4 $3\src25__data_o$next[3:0]$10622 + attribute \src "issuer_ls180.v:165791.3-165830.6" + wire width 4 $3\src35__data_o$next[3:0]$10636 + attribute \src "issuer_ls180.v:165901.3-165930.6" + wire $3\wr_detect$10[0:0]$10658 + attribute \src "issuer_ls180.v:165971.3-166000.6" + wire $3\wr_detect$13[0:0]$10672 + attribute \src "issuer_ls180.v:165761.3-165790.6" + wire $3\wr_detect$4[0:0]$10630 + attribute \src "issuer_ls180.v:165831.3-165860.6" + wire $3\wr_detect$7[0:0]$10644 + attribute \src "issuer_ls180.v:165664.3-165693.6" + wire $3\wr_detect[0:0] + attribute \src "issuer_ls180.v:165931.3-165970.6" + wire width 4 $4\r25__data_o$next[3:0]$10665 + attribute \src "issuer_ls180.v:165861.3-165900.6" + wire width 4 $4\r5__data_o$next[3:0]$10651 + attribute \src "issuer_ls180.v:165694.3-165720.6" + wire width 4 $4\reg$next[3:0]$10617 + attribute \src "issuer_ls180.v:165624.3-165663.6" + wire width 4 $4\src15__data_o$next[3:0]$10608 + attribute \src "issuer_ls180.v:165721.3-165760.6" + wire width 4 $4\src25__data_o$next[3:0]$10623 + attribute \src "issuer_ls180.v:165791.3-165830.6" + wire width 4 $4\src35__data_o$next[3:0]$10637 + attribute \src "issuer_ls180.v:165901.3-165930.6" + wire $4\wr_detect$10[0:0]$10659 + attribute \src "issuer_ls180.v:165971.3-166000.6" + wire $4\wr_detect$13[0:0]$10673 + attribute \src "issuer_ls180.v:165761.3-165790.6" + wire $4\wr_detect$4[0:0]$10631 + attribute \src "issuer_ls180.v:165831.3-165860.6" + wire $4\wr_detect$7[0:0]$10645 + attribute \src "issuer_ls180.v:165664.3-165693.6" + wire $4\wr_detect[0:0] + attribute \src "issuer_ls180.v:165931.3-165970.6" + wire width 4 $5\r25__data_o$next[3:0]$10666 + attribute \src "issuer_ls180.v:165861.3-165900.6" + wire width 4 $5\r5__data_o$next[3:0]$10652 + attribute \src "issuer_ls180.v:165624.3-165663.6" + wire width 4 $5\src15__data_o$next[3:0]$10609 + attribute \src "issuer_ls180.v:165721.3-165760.6" + wire width 4 $5\src25__data_o$next[3:0]$10624 + attribute \src "issuer_ls180.v:165791.3-165830.6" + wire width 4 $5\src35__data_o$next[3:0]$10638 + attribute \src "issuer_ls180.v:165931.3-165970.6" + wire width 4 $6\r25__data_o$next[3:0]$10667 + attribute \src "issuer_ls180.v:165861.3-165900.6" + wire width 4 $6\r5__data_o$next[3:0]$10653 + attribute \src "issuer_ls180.v:165624.3-165663.6" + wire width 4 $6\src15__data_o$next[3:0]$10610 + attribute \src "issuer_ls180.v:165721.3-165760.6" + wire width 4 $6\src25__data_o$next[3:0]$10625 + attribute \src "issuer_ls180.v:165791.3-165830.6" + wire width 4 $6\src35__data_o$next[3:0]$10639 + attribute \src "issuer_ls180.v:165607.17-165607.104" + wire $not$issuer_ls180.v:165607$10592_Y + attribute \src "issuer_ls180.v:165608.18-165608.105" + wire $not$issuer_ls180.v:165608$10593_Y + attribute \src "issuer_ls180.v:165609.17-165609.100" + wire $not$issuer_ls180.v:165609$10594_Y + attribute \src "issuer_ls180.v:165610.17-165610.103" + wire $not$issuer_ls180.v:165610$10595_Y + attribute \src "issuer_ls180.v:165611.17-165611.103" + wire $not$issuer_ls180.v:165611$10596_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + wire \$12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + wire \$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + wire \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" + wire input 18 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" + wire input 1 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 input 9 \dest15__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire input 8 \dest15__wen + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 input 11 \dest25__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire input 10 \dest25__wen + attribute \src "issuer_ls180.v:165531.7-165531.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 output 14 \r25__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 \r25__data_o$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire input 15 \r25__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 output 12 \r5__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 \r5__data_o$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire input 13 \r5__ren + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" + wire width 4 \reg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" + wire width 4 \reg$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 output 3 \src15__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 \src15__data_o$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire input 2 \src15__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 output 5 \src25__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 \src25__data_o$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire input 4 \src25__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 output 7 \src35__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 \src35__data_o$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire input 6 \src35__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 input 16 \w5__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire input 17 \w5__wen + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" + wire \wr_detect + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" + wire \wr_detect$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" + wire \wr_detect$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" + wire \wr_detect$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" + wire \wr_detect$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + cell $not $not$issuer_ls180.v:165607$10592 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_detect$10 + connect \Y $not$issuer_ls180.v:165607$10592_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + cell $not $not$issuer_ls180.v:165608$10593 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_detect$13 + connect \Y $not$issuer_ls180.v:165608$10593_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + cell $not $not$issuer_ls180.v:165609$10594 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_detect + connect \Y $not$issuer_ls180.v:165609$10594_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + cell $not $not$issuer_ls180.v:165610$10595 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_detect$4 + connect \Y $not$issuer_ls180.v:165610$10595_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + cell $not $not$issuer_ls180.v:165611$10596 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_detect$7 + connect \Y $not$issuer_ls180.v:165611$10596_Y + end + attribute \src "issuer_ls180.v:165531.7-165531.20" + process $proc$issuer_ls180.v:165531$10674 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "issuer_ls180.v:165556.13-165556.31" + process $proc$issuer_ls180.v:165556$10675 + assign { } { } + assign $1\r25__data_o[3:0] 4'0000 + sync always + sync init + update \r25__data_o $1\r25__data_o[3:0] + end + attribute \src "issuer_ls180.v:165563.13-165563.30" + process $proc$issuer_ls180.v:165563$10676 + assign { } { } + assign $1\r5__data_o[3:0] 4'0000 + sync always + sync init + update \r5__data_o $1\r5__data_o[3:0] + end + attribute \src "issuer_ls180.v:165569.13-165569.25" + process $proc$issuer_ls180.v:165569$10677 + assign { } { } + assign $1\reg[3:0] 4'0000 + sync always + sync init + update \reg $1\reg[3:0] + end + attribute \src "issuer_ls180.v:165574.13-165574.33" + process $proc$issuer_ls180.v:165574$10678 + assign { } { } + assign $1\src15__data_o[3:0] 4'0000 + sync always + sync init + update \src15__data_o $1\src15__data_o[3:0] + end + attribute \src "issuer_ls180.v:165581.13-165581.33" + process $proc$issuer_ls180.v:165581$10679 + assign { } { } + assign $1\src25__data_o[3:0] 4'0000 + sync always + sync init + update \src25__data_o $1\src25__data_o[3:0] + end + attribute \src "issuer_ls180.v:165588.13-165588.33" + process $proc$issuer_ls180.v:165588$10680 + assign { } { } + assign $1\src35__data_o[3:0] 4'0000 + sync always + sync init + update \src35__data_o $1\src35__data_o[3:0] + end + attribute \src "issuer_ls180.v:165612.3-165613.25" + process $proc$issuer_ls180.v:165612$10597 + assign { } { } + assign $0\reg[3:0] \reg$next + sync posedge \coresync_clk + update \reg $0\reg[3:0] + end + attribute \src "issuer_ls180.v:165614.3-165615.39" + process $proc$issuer_ls180.v:165614$10598 + assign { } { } + assign $0\r25__data_o[3:0] \r25__data_o$next + sync posedge \coresync_clk + update \r25__data_o $0\r25__data_o[3:0] + end + attribute \src "issuer_ls180.v:165616.3-165617.37" + process $proc$issuer_ls180.v:165616$10599 + assign { } { } + assign $0\r5__data_o[3:0] \r5__data_o$next + sync posedge \coresync_clk + update \r5__data_o $0\r5__data_o[3:0] + end + attribute \src "issuer_ls180.v:165618.3-165619.43" + process $proc$issuer_ls180.v:165618$10600 + assign { } { } + assign $0\src35__data_o[3:0] \src35__data_o$next + sync posedge \coresync_clk + update \src35__data_o $0\src35__data_o[3:0] + end + attribute \src "issuer_ls180.v:165620.3-165621.43" + process $proc$issuer_ls180.v:165620$10601 + assign { } { } + assign $0\src25__data_o[3:0] \src25__data_o$next + sync posedge \coresync_clk + update \src25__data_o $0\src25__data_o[3:0] + end + attribute \src "issuer_ls180.v:165622.3-165623.43" + process $proc$issuer_ls180.v:165622$10602 + assign { } { } + assign $0\src15__data_o[3:0] \src15__data_o$next + sync posedge \coresync_clk + update \src15__data_o $0\src15__data_o[3:0] + end + attribute \src "issuer_ls180.v:165624.3-165663.6" + process $proc$issuer_ls180.v:165624$10603 + assign { } { } + assign { } { } + assign { } { } + assign $0\src15__data_o$next[3:0]$10604 $6\src15__data_o$next[3:0]$10610 + attribute \src "issuer_ls180.v:165625.5-165625.29" + switch \initial + attribute \src "issuer_ls180.v:165625.9-165625.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \src15__ren + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\src15__data_o$next[3:0]$10605 $5\src15__data_o$next[3:0]$10609 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest15__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\src15__data_o$next[3:0]$10606 \dest15__data_i + case + assign $2\src15__data_o$next[3:0]$10606 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest25__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\src15__data_o$next[3:0]$10607 \dest25__data_i + case + assign $3\src15__data_o$next[3:0]$10607 $2\src15__data_o$next[3:0]$10606 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w5__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\src15__data_o$next[3:0]$10608 \w5__data_i + case + assign $4\src15__data_o$next[3:0]$10608 $3\src15__data_o$next[3:0]$10607 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + switch \$1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\src15__data_o$next[3:0]$10609 \reg + case + assign $5\src15__data_o$next[3:0]$10609 $4\src15__data_o$next[3:0]$10608 + end + case + assign $1\src15__data_o$next[3:0]$10605 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $6\src15__data_o$next[3:0]$10610 4'0000 + case + assign $6\src15__data_o$next[3:0]$10610 $1\src15__data_o$next[3:0]$10605 + end + sync always + update \src15__data_o$next $0\src15__data_o$next[3:0]$10604 + end + attribute \src "issuer_ls180.v:165664.3-165693.6" + process $proc$issuer_ls180.v:165664$10611 + assign { } { } + assign { } { } + assign $0\wr_detect[0:0] $1\wr_detect[0:0] + attribute \src "issuer_ls180.v:165665.5-165665.29" + switch \initial + attribute \src "issuer_ls180.v:165665.9-165665.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \src15__ren + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\wr_detect[0:0] $4\wr_detect[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest15__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\wr_detect[0:0] 1'1 + case + assign $2\wr_detect[0:0] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest25__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\wr_detect[0:0] 1'1 + case + assign $3\wr_detect[0:0] $2\wr_detect[0:0] + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w5__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\wr_detect[0:0] 1'1 + case + assign $4\wr_detect[0:0] $3\wr_detect[0:0] + end + case + assign $1\wr_detect[0:0] 1'0 + end + sync always + update \wr_detect $0\wr_detect[0:0] + end + attribute \src "issuer_ls180.v:165694.3-165720.6" + process $proc$issuer_ls180.v:165694$10612 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\reg$next[3:0]$10613 $4\reg$next[3:0]$10617 + attribute \src "issuer_ls180.v:165695.5-165695.29" + switch \initial + attribute \src "issuer_ls180.v:165695.9-165695.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" + switch \dest15__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\reg$next[3:0]$10614 \dest15__data_i + case + assign $1\reg$next[3:0]$10614 \reg + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" + switch \dest25__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\reg$next[3:0]$10615 \dest25__data_i + case + assign $2\reg$next[3:0]$10615 $1\reg$next[3:0]$10614 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" + switch \w5__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\reg$next[3:0]$10616 \w5__data_i + case + assign $3\reg$next[3:0]$10616 $2\reg$next[3:0]$10615 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\reg$next[3:0]$10617 4'0000 + case + assign $4\reg$next[3:0]$10617 $3\reg$next[3:0]$10616 + end + sync always + update \reg$next $0\reg$next[3:0]$10613 + end + attribute \src "issuer_ls180.v:165721.3-165760.6" + process $proc$issuer_ls180.v:165721$10618 + assign { } { } + assign { } { } + assign { } { } + assign $0\src25__data_o$next[3:0]$10619 $6\src25__data_o$next[3:0]$10625 + attribute \src "issuer_ls180.v:165722.5-165722.29" + switch \initial + attribute \src "issuer_ls180.v:165722.9-165722.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \src25__ren + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\src25__data_o$next[3:0]$10620 $5\src25__data_o$next[3:0]$10624 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest15__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\src25__data_o$next[3:0]$10621 \dest15__data_i + case + assign $2\src25__data_o$next[3:0]$10621 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest25__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\src25__data_o$next[3:0]$10622 \dest25__data_i + case + assign $3\src25__data_o$next[3:0]$10622 $2\src25__data_o$next[3:0]$10621 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w5__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\src25__data_o$next[3:0]$10623 \w5__data_i + case + assign $4\src25__data_o$next[3:0]$10623 $3\src25__data_o$next[3:0]$10622 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + switch \$3 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\src25__data_o$next[3:0]$10624 \reg + case + assign $5\src25__data_o$next[3:0]$10624 $4\src25__data_o$next[3:0]$10623 + end + case + assign $1\src25__data_o$next[3:0]$10620 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $6\src25__data_o$next[3:0]$10625 4'0000 + case + assign $6\src25__data_o$next[3:0]$10625 $1\src25__data_o$next[3:0]$10620 + end + sync always + update \src25__data_o$next $0\src25__data_o$next[3:0]$10619 + end + attribute \src "issuer_ls180.v:165761.3-165790.6" + process $proc$issuer_ls180.v:165761$10626 + assign { } { } + assign { } { } + assign $0\wr_detect$4[0:0]$10627 $1\wr_detect$4[0:0]$10628 + attribute \src "issuer_ls180.v:165762.5-165762.29" + switch \initial + attribute \src "issuer_ls180.v:165762.9-165762.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \src25__ren + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\wr_detect$4[0:0]$10628 $4\wr_detect$4[0:0]$10631 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest15__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\wr_detect$4[0:0]$10629 1'1 + case + assign $2\wr_detect$4[0:0]$10629 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest25__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\wr_detect$4[0:0]$10630 1'1 + case + assign $3\wr_detect$4[0:0]$10630 $2\wr_detect$4[0:0]$10629 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w5__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\wr_detect$4[0:0]$10631 1'1 + case + assign $4\wr_detect$4[0:0]$10631 $3\wr_detect$4[0:0]$10630 + end + case + assign $1\wr_detect$4[0:0]$10628 1'0 + end + sync always + update \wr_detect$4 $0\wr_detect$4[0:0]$10627 + end + attribute \src "issuer_ls180.v:165791.3-165830.6" + process $proc$issuer_ls180.v:165791$10632 + assign { } { } + assign { } { } + assign { } { } + assign $0\src35__data_o$next[3:0]$10633 $6\src35__data_o$next[3:0]$10639 + attribute \src "issuer_ls180.v:165792.5-165792.29" + switch \initial + attribute \src "issuer_ls180.v:165792.9-165792.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \src35__ren + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\src35__data_o$next[3:0]$10634 $5\src35__data_o$next[3:0]$10638 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest15__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\src35__data_o$next[3:0]$10635 \dest15__data_i + case + assign $2\src35__data_o$next[3:0]$10635 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest25__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\src35__data_o$next[3:0]$10636 \dest25__data_i + case + assign $3\src35__data_o$next[3:0]$10636 $2\src35__data_o$next[3:0]$10635 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w5__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\src35__data_o$next[3:0]$10637 \w5__data_i + case + assign $4\src35__data_o$next[3:0]$10637 $3\src35__data_o$next[3:0]$10636 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + switch \$6 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\src35__data_o$next[3:0]$10638 \reg + case + assign $5\src35__data_o$next[3:0]$10638 $4\src35__data_o$next[3:0]$10637 + end + case + assign $1\src35__data_o$next[3:0]$10634 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $6\src35__data_o$next[3:0]$10639 4'0000 + case + assign $6\src35__data_o$next[3:0]$10639 $1\src35__data_o$next[3:0]$10634 + end + sync always + update \src35__data_o$next $0\src35__data_o$next[3:0]$10633 + end + attribute \src "issuer_ls180.v:165831.3-165860.6" + process $proc$issuer_ls180.v:165831$10640 + assign { } { } + assign { } { } + assign $0\wr_detect$7[0:0]$10641 $1\wr_detect$7[0:0]$10642 + attribute \src "issuer_ls180.v:165832.5-165832.29" + switch \initial + attribute \src "issuer_ls180.v:165832.9-165832.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \src35__ren + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\wr_detect$7[0:0]$10642 $4\wr_detect$7[0:0]$10645 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest15__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\wr_detect$7[0:0]$10643 1'1 + case + assign $2\wr_detect$7[0:0]$10643 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest25__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\wr_detect$7[0:0]$10644 1'1 + case + assign $3\wr_detect$7[0:0]$10644 $2\wr_detect$7[0:0]$10643 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w5__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\wr_detect$7[0:0]$10645 1'1 + case + assign $4\wr_detect$7[0:0]$10645 $3\wr_detect$7[0:0]$10644 + end + case + assign $1\wr_detect$7[0:0]$10642 1'0 + end + sync always + update \wr_detect$7 $0\wr_detect$7[0:0]$10641 + end + attribute \src "issuer_ls180.v:165861.3-165900.6" + process $proc$issuer_ls180.v:165861$10646 + assign { } { } + assign { } { } + assign { } { } + assign $0\r5__data_o$next[3:0]$10647 $6\r5__data_o$next[3:0]$10653 + attribute \src "issuer_ls180.v:165862.5-165862.29" + switch \initial + attribute \src "issuer_ls180.v:165862.9-165862.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \r5__ren + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\r5__data_o$next[3:0]$10648 $5\r5__data_o$next[3:0]$10652 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest15__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\r5__data_o$next[3:0]$10649 \dest15__data_i + case + assign $2\r5__data_o$next[3:0]$10649 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest25__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\r5__data_o$next[3:0]$10650 \dest25__data_i + case + assign $3\r5__data_o$next[3:0]$10650 $2\r5__data_o$next[3:0]$10649 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w5__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\r5__data_o$next[3:0]$10651 \w5__data_i + case + assign $4\r5__data_o$next[3:0]$10651 $3\r5__data_o$next[3:0]$10650 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + switch \$9 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\r5__data_o$next[3:0]$10652 \reg + case + assign $5\r5__data_o$next[3:0]$10652 $4\r5__data_o$next[3:0]$10651 + end + case + assign $1\r5__data_o$next[3:0]$10648 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $6\r5__data_o$next[3:0]$10653 4'0000 + case + assign $6\r5__data_o$next[3:0]$10653 $1\r5__data_o$next[3:0]$10648 + end + sync always + update \r5__data_o$next $0\r5__data_o$next[3:0]$10647 + end + attribute \src "issuer_ls180.v:165901.3-165930.6" + process $proc$issuer_ls180.v:165901$10654 + assign { } { } + assign { } { } + assign $0\wr_detect$10[0:0]$10655 $1\wr_detect$10[0:0]$10656 + attribute \src "issuer_ls180.v:165902.5-165902.29" + switch \initial + attribute \src "issuer_ls180.v:165902.9-165902.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \r5__ren + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\wr_detect$10[0:0]$10656 $4\wr_detect$10[0:0]$10659 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest15__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\wr_detect$10[0:0]$10657 1'1 + case + assign $2\wr_detect$10[0:0]$10657 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest25__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\wr_detect$10[0:0]$10658 1'1 + case + assign $3\wr_detect$10[0:0]$10658 $2\wr_detect$10[0:0]$10657 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w5__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\wr_detect$10[0:0]$10659 1'1 + case + assign $4\wr_detect$10[0:0]$10659 $3\wr_detect$10[0:0]$10658 + end + case + assign $1\wr_detect$10[0:0]$10656 1'0 + end + sync always + update \wr_detect$10 $0\wr_detect$10[0:0]$10655 + end + attribute \src "issuer_ls180.v:165931.3-165970.6" + process $proc$issuer_ls180.v:165931$10660 + assign { } { } + assign { } { } + assign { } { } + assign $0\r25__data_o$next[3:0]$10661 $6\r25__data_o$next[3:0]$10667 + attribute \src "issuer_ls180.v:165932.5-165932.29" + switch \initial + attribute \src "issuer_ls180.v:165932.9-165932.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \r25__ren + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\r25__data_o$next[3:0]$10662 $5\r25__data_o$next[3:0]$10666 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest15__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\r25__data_o$next[3:0]$10663 \dest15__data_i + case + assign $2\r25__data_o$next[3:0]$10663 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest25__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\r25__data_o$next[3:0]$10664 \dest25__data_i + case + assign $3\r25__data_o$next[3:0]$10664 $2\r25__data_o$next[3:0]$10663 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w5__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\r25__data_o$next[3:0]$10665 \w5__data_i + case + assign $4\r25__data_o$next[3:0]$10665 $3\r25__data_o$next[3:0]$10664 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + switch \$12 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\r25__data_o$next[3:0]$10666 \reg + case + assign $5\r25__data_o$next[3:0]$10666 $4\r25__data_o$next[3:0]$10665 + end + case + assign $1\r25__data_o$next[3:0]$10662 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $6\r25__data_o$next[3:0]$10667 4'0000 + case + assign $6\r25__data_o$next[3:0]$10667 $1\r25__data_o$next[3:0]$10662 + end + sync always + update \r25__data_o$next $0\r25__data_o$next[3:0]$10661 + end + attribute \src "issuer_ls180.v:165971.3-166000.6" + process $proc$issuer_ls180.v:165971$10668 + assign { } { } + assign { } { } + assign $0\wr_detect$13[0:0]$10669 $1\wr_detect$13[0:0]$10670 + attribute \src "issuer_ls180.v:165972.5-165972.29" + switch \initial + attribute \src "issuer_ls180.v:165972.9-165972.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \r25__ren + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\wr_detect$13[0:0]$10670 $4\wr_detect$13[0:0]$10673 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest15__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\wr_detect$13[0:0]$10671 1'1 + case + assign $2\wr_detect$13[0:0]$10671 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest25__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\wr_detect$13[0:0]$10672 1'1 + case + assign $3\wr_detect$13[0:0]$10672 $2\wr_detect$13[0:0]$10671 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w5__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\wr_detect$13[0:0]$10673 1'1 + case + assign $4\wr_detect$13[0:0]$10673 $3\wr_detect$13[0:0]$10672 + end + case + assign $1\wr_detect$13[0:0]$10670 1'0 + end + sync always + update \wr_detect$13 $0\wr_detect$13[0:0]$10669 + end + connect \$9 $not$issuer_ls180.v:165607$10592_Y + connect \$12 $not$issuer_ls180.v:165608$10593_Y + connect \$1 $not$issuer_ls180.v:165609$10594_Y + connect \$3 $not$issuer_ls180.v:165610$10595_Y + connect \$6 $not$issuer_ls180.v:165611$10596_Y +end +attribute \src "issuer_ls180.v:166005.1-166476.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.cr.reg_6" +attribute \generator "nMigen" +module \reg_6 + attribute \src "issuer_ls180.v:166006.7-166006.20" + wire $0\initial[0:0] + attribute \src "issuer_ls180.v:166406.3-166445.6" + wire width 4 $0\r26__data_o$next[3:0]$10750 + attribute \src "issuer_ls180.v:166089.3-166090.39" + wire width 4 $0\r26__data_o[3:0] + attribute \src "issuer_ls180.v:166336.3-166375.6" + wire width 4 $0\r6__data_o$next[3:0]$10736 + attribute \src "issuer_ls180.v:166091.3-166092.37" + wire width 4 $0\r6__data_o[3:0] + attribute \src "issuer_ls180.v:166169.3-166195.6" + wire width 4 $0\reg$next[3:0]$10702 + attribute \src "issuer_ls180.v:166087.3-166088.25" + wire width 4 $0\reg[3:0] + attribute \src "issuer_ls180.v:166099.3-166138.6" + wire width 4 $0\src16__data_o$next[3:0]$10693 + attribute \src "issuer_ls180.v:166097.3-166098.43" + wire width 4 $0\src16__data_o[3:0] + attribute \src "issuer_ls180.v:166196.3-166235.6" + wire width 4 $0\src26__data_o$next[3:0]$10708 + attribute \src "issuer_ls180.v:166095.3-166096.43" + wire width 4 $0\src26__data_o[3:0] + attribute \src "issuer_ls180.v:166266.3-166305.6" + wire width 4 $0\src36__data_o$next[3:0]$10722 + attribute \src "issuer_ls180.v:166093.3-166094.43" + wire width 4 $0\src36__data_o[3:0] + attribute \src "issuer_ls180.v:166376.3-166405.6" + wire $0\wr_detect$10[0:0]$10744 + attribute \src "issuer_ls180.v:166446.3-166475.6" + wire $0\wr_detect$13[0:0]$10758 + attribute \src "issuer_ls180.v:166236.3-166265.6" + wire $0\wr_detect$4[0:0]$10716 + attribute \src "issuer_ls180.v:166306.3-166335.6" + wire $0\wr_detect$7[0:0]$10730 + attribute \src "issuer_ls180.v:166139.3-166168.6" + wire $0\wr_detect[0:0] + attribute \src "issuer_ls180.v:166406.3-166445.6" + wire width 4 $1\r26__data_o$next[3:0]$10751 + attribute \src "issuer_ls180.v:166031.13-166031.31" + wire width 4 $1\r26__data_o[3:0] + attribute \src "issuer_ls180.v:166336.3-166375.6" + wire width 4 $1\r6__data_o$next[3:0]$10737 + attribute \src "issuer_ls180.v:166038.13-166038.30" + wire width 4 $1\r6__data_o[3:0] + attribute \src "issuer_ls180.v:166169.3-166195.6" + wire width 4 $1\reg$next[3:0]$10703 + attribute \src "issuer_ls180.v:166044.13-166044.25" + wire width 4 $1\reg[3:0] + attribute \src "issuer_ls180.v:166099.3-166138.6" + wire width 4 $1\src16__data_o$next[3:0]$10694 + attribute \src "issuer_ls180.v:166049.13-166049.33" + wire width 4 $1\src16__data_o[3:0] + attribute \src "issuer_ls180.v:166196.3-166235.6" + wire width 4 $1\src26__data_o$next[3:0]$10709 + attribute \src "issuer_ls180.v:166056.13-166056.33" + wire width 4 $1\src26__data_o[3:0] + attribute \src "issuer_ls180.v:166266.3-166305.6" + wire width 4 $1\src36__data_o$next[3:0]$10723 + attribute \src "issuer_ls180.v:166063.13-166063.33" + wire width 4 $1\src36__data_o[3:0] + attribute \src "issuer_ls180.v:166376.3-166405.6" + wire $1\wr_detect$10[0:0]$10745 + attribute \src "issuer_ls180.v:166446.3-166475.6" + wire $1\wr_detect$13[0:0]$10759 + attribute \src "issuer_ls180.v:166236.3-166265.6" + wire $1\wr_detect$4[0:0]$10717 + attribute \src "issuer_ls180.v:166306.3-166335.6" + wire $1\wr_detect$7[0:0]$10731 + attribute \src "issuer_ls180.v:166139.3-166168.6" + wire $1\wr_detect[0:0] + attribute \src "issuer_ls180.v:166406.3-166445.6" + wire width 4 $2\r26__data_o$next[3:0]$10752 + attribute \src "issuer_ls180.v:166336.3-166375.6" + wire width 4 $2\r6__data_o$next[3:0]$10738 + attribute \src "issuer_ls180.v:166169.3-166195.6" + wire width 4 $2\reg$next[3:0]$10704 + attribute \src "issuer_ls180.v:166099.3-166138.6" + wire width 4 $2\src16__data_o$next[3:0]$10695 + attribute \src "issuer_ls180.v:166196.3-166235.6" + wire width 4 $2\src26__data_o$next[3:0]$10710 + attribute \src "issuer_ls180.v:166266.3-166305.6" + wire width 4 $2\src36__data_o$next[3:0]$10724 + attribute \src "issuer_ls180.v:166376.3-166405.6" + wire $2\wr_detect$10[0:0]$10746 + attribute \src "issuer_ls180.v:166446.3-166475.6" + wire $2\wr_detect$13[0:0]$10760 + attribute \src "issuer_ls180.v:166236.3-166265.6" + wire $2\wr_detect$4[0:0]$10718 + attribute \src "issuer_ls180.v:166306.3-166335.6" + wire $2\wr_detect$7[0:0]$10732 + attribute \src "issuer_ls180.v:166139.3-166168.6" + wire $2\wr_detect[0:0] + attribute \src "issuer_ls180.v:166406.3-166445.6" + wire width 4 $3\r26__data_o$next[3:0]$10753 + attribute \src "issuer_ls180.v:166336.3-166375.6" + wire width 4 $3\r6__data_o$next[3:0]$10739 + attribute \src "issuer_ls180.v:166169.3-166195.6" + wire width 4 $3\reg$next[3:0]$10705 + attribute \src "issuer_ls180.v:166099.3-166138.6" + wire width 4 $3\src16__data_o$next[3:0]$10696 + attribute \src "issuer_ls180.v:166196.3-166235.6" + wire width 4 $3\src26__data_o$next[3:0]$10711 + attribute \src "issuer_ls180.v:166266.3-166305.6" + wire width 4 $3\src36__data_o$next[3:0]$10725 + attribute \src "issuer_ls180.v:166376.3-166405.6" + wire $3\wr_detect$10[0:0]$10747 + attribute \src "issuer_ls180.v:166446.3-166475.6" + wire $3\wr_detect$13[0:0]$10761 + attribute \src "issuer_ls180.v:166236.3-166265.6" + wire $3\wr_detect$4[0:0]$10719 + attribute \src "issuer_ls180.v:166306.3-166335.6" + wire $3\wr_detect$7[0:0]$10733 + attribute \src "issuer_ls180.v:166139.3-166168.6" + wire $3\wr_detect[0:0] + attribute \src "issuer_ls180.v:166406.3-166445.6" + wire width 4 $4\r26__data_o$next[3:0]$10754 + attribute \src "issuer_ls180.v:166336.3-166375.6" + wire width 4 $4\r6__data_o$next[3:0]$10740 + attribute \src "issuer_ls180.v:166169.3-166195.6" + wire width 4 $4\reg$next[3:0]$10706 + attribute \src "issuer_ls180.v:166099.3-166138.6" + wire width 4 $4\src16__data_o$next[3:0]$10697 + attribute \src "issuer_ls180.v:166196.3-166235.6" + wire width 4 $4\src26__data_o$next[3:0]$10712 + attribute \src "issuer_ls180.v:166266.3-166305.6" + wire width 4 $4\src36__data_o$next[3:0]$10726 + attribute \src "issuer_ls180.v:166376.3-166405.6" + wire $4\wr_detect$10[0:0]$10748 + attribute \src "issuer_ls180.v:166446.3-166475.6" + wire $4\wr_detect$13[0:0]$10762 + attribute \src "issuer_ls180.v:166236.3-166265.6" + wire $4\wr_detect$4[0:0]$10720 + attribute \src "issuer_ls180.v:166306.3-166335.6" + wire $4\wr_detect$7[0:0]$10734 + attribute \src "issuer_ls180.v:166139.3-166168.6" + wire $4\wr_detect[0:0] + attribute \src "issuer_ls180.v:166406.3-166445.6" + wire width 4 $5\r26__data_o$next[3:0]$10755 + attribute \src "issuer_ls180.v:166336.3-166375.6" + wire width 4 $5\r6__data_o$next[3:0]$10741 + attribute \src "issuer_ls180.v:166099.3-166138.6" + wire width 4 $5\src16__data_o$next[3:0]$10698 + attribute \src "issuer_ls180.v:166196.3-166235.6" + wire width 4 $5\src26__data_o$next[3:0]$10713 + attribute \src "issuer_ls180.v:166266.3-166305.6" + wire width 4 $5\src36__data_o$next[3:0]$10727 + attribute \src "issuer_ls180.v:166406.3-166445.6" + wire width 4 $6\r26__data_o$next[3:0]$10756 + attribute \src "issuer_ls180.v:166336.3-166375.6" + wire width 4 $6\r6__data_o$next[3:0]$10742 + attribute \src "issuer_ls180.v:166099.3-166138.6" + wire width 4 $6\src16__data_o$next[3:0]$10699 + attribute \src "issuer_ls180.v:166196.3-166235.6" + wire width 4 $6\src26__data_o$next[3:0]$10714 + attribute \src "issuer_ls180.v:166266.3-166305.6" + wire width 4 $6\src36__data_o$next[3:0]$10728 + attribute \src "issuer_ls180.v:166082.17-166082.104" + wire $not$issuer_ls180.v:166082$10681_Y + attribute \src "issuer_ls180.v:166083.18-166083.105" + wire $not$issuer_ls180.v:166083$10682_Y + attribute \src "issuer_ls180.v:166084.17-166084.100" + wire $not$issuer_ls180.v:166084$10683_Y + attribute \src "issuer_ls180.v:166085.17-166085.103" + wire $not$issuer_ls180.v:166085$10684_Y + attribute \src "issuer_ls180.v:166086.17-166086.103" + wire $not$issuer_ls180.v:166086$10685_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + wire \$12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + wire \$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + wire \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" + wire input 18 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" + wire input 1 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 input 9 \dest16__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire input 8 \dest16__wen + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 input 11 \dest26__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire input 10 \dest26__wen + attribute \src "issuer_ls180.v:166006.7-166006.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 output 14 \r26__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 \r26__data_o$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire input 15 \r26__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 output 12 \r6__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 \r6__data_o$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire input 13 \r6__ren + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" + wire width 4 \reg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" + wire width 4 \reg$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 output 3 \src16__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 \src16__data_o$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire input 2 \src16__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 output 5 \src26__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 \src26__data_o$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire input 4 \src26__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 output 7 \src36__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 \src36__data_o$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire input 6 \src36__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 input 16 \w6__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire input 17 \w6__wen + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" + wire \wr_detect + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" + wire \wr_detect$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" + wire \wr_detect$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" + wire \wr_detect$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" + wire \wr_detect$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + cell $not $not$issuer_ls180.v:166082$10681 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_detect$10 + connect \Y $not$issuer_ls180.v:166082$10681_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + cell $not $not$issuer_ls180.v:166083$10682 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_detect$13 + connect \Y $not$issuer_ls180.v:166083$10682_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + cell $not $not$issuer_ls180.v:166084$10683 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_detect + connect \Y $not$issuer_ls180.v:166084$10683_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + cell $not $not$issuer_ls180.v:166085$10684 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_detect$4 + connect \Y $not$issuer_ls180.v:166085$10684_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + cell $not $not$issuer_ls180.v:166086$10685 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_detect$7 + connect \Y $not$issuer_ls180.v:166086$10685_Y + end + attribute \src "issuer_ls180.v:166006.7-166006.20" + process $proc$issuer_ls180.v:166006$10763 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "issuer_ls180.v:166031.13-166031.31" + process $proc$issuer_ls180.v:166031$10764 + assign { } { } + assign $1\r26__data_o[3:0] 4'0000 + sync always + sync init + update \r26__data_o $1\r26__data_o[3:0] + end + attribute \src "issuer_ls180.v:166038.13-166038.30" + process $proc$issuer_ls180.v:166038$10765 + assign { } { } + assign $1\r6__data_o[3:0] 4'0000 + sync always + sync init + update \r6__data_o $1\r6__data_o[3:0] + end + attribute \src "issuer_ls180.v:166044.13-166044.25" + process $proc$issuer_ls180.v:166044$10766 + assign { } { } + assign $1\reg[3:0] 4'0000 + sync always + sync init + update \reg $1\reg[3:0] + end + attribute \src "issuer_ls180.v:166049.13-166049.33" + process $proc$issuer_ls180.v:166049$10767 + assign { } { } + assign $1\src16__data_o[3:0] 4'0000 + sync always + sync init + update \src16__data_o $1\src16__data_o[3:0] + end + attribute \src "issuer_ls180.v:166056.13-166056.33" + process $proc$issuer_ls180.v:166056$10768 + assign { } { } + assign $1\src26__data_o[3:0] 4'0000 + sync always + sync init + update \src26__data_o $1\src26__data_o[3:0] + end + attribute \src "issuer_ls180.v:166063.13-166063.33" + process $proc$issuer_ls180.v:166063$10769 + assign { } { } + assign $1\src36__data_o[3:0] 4'0000 + sync always + sync init + update \src36__data_o $1\src36__data_o[3:0] + end + attribute \src "issuer_ls180.v:166087.3-166088.25" + process $proc$issuer_ls180.v:166087$10686 + assign { } { } + assign $0\reg[3:0] \reg$next + sync posedge \coresync_clk + update \reg $0\reg[3:0] + end + attribute \src "issuer_ls180.v:166089.3-166090.39" + process $proc$issuer_ls180.v:166089$10687 + assign { } { } + assign $0\r26__data_o[3:0] \r26__data_o$next + sync posedge \coresync_clk + update \r26__data_o $0\r26__data_o[3:0] + end + attribute \src "issuer_ls180.v:166091.3-166092.37" + process $proc$issuer_ls180.v:166091$10688 + assign { } { } + assign $0\r6__data_o[3:0] \r6__data_o$next + sync posedge \coresync_clk + update \r6__data_o $0\r6__data_o[3:0] + end + attribute \src "issuer_ls180.v:166093.3-166094.43" + process $proc$issuer_ls180.v:166093$10689 + assign { } { } + assign $0\src36__data_o[3:0] \src36__data_o$next + sync posedge \coresync_clk + update \src36__data_o $0\src36__data_o[3:0] + end + attribute \src "issuer_ls180.v:166095.3-166096.43" + process $proc$issuer_ls180.v:166095$10690 + assign { } { } + assign $0\src26__data_o[3:0] \src26__data_o$next + sync posedge \coresync_clk + update \src26__data_o $0\src26__data_o[3:0] + end + attribute \src "issuer_ls180.v:166097.3-166098.43" + process $proc$issuer_ls180.v:166097$10691 + assign { } { } + assign $0\src16__data_o[3:0] \src16__data_o$next + sync posedge \coresync_clk + update \src16__data_o $0\src16__data_o[3:0] + end + attribute \src "issuer_ls180.v:166099.3-166138.6" + process $proc$issuer_ls180.v:166099$10692 + assign { } { } + assign { } { } + assign { } { } + assign $0\src16__data_o$next[3:0]$10693 $6\src16__data_o$next[3:0]$10699 + attribute \src "issuer_ls180.v:166100.5-166100.29" + switch \initial + attribute \src "issuer_ls180.v:166100.9-166100.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \src16__ren + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\src16__data_o$next[3:0]$10694 $5\src16__data_o$next[3:0]$10698 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest16__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\src16__data_o$next[3:0]$10695 \dest16__data_i + case + assign $2\src16__data_o$next[3:0]$10695 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest26__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\src16__data_o$next[3:0]$10696 \dest26__data_i + case + assign $3\src16__data_o$next[3:0]$10696 $2\src16__data_o$next[3:0]$10695 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w6__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\src16__data_o$next[3:0]$10697 \w6__data_i + case + assign $4\src16__data_o$next[3:0]$10697 $3\src16__data_o$next[3:0]$10696 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + switch \$1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\src16__data_o$next[3:0]$10698 \reg + case + assign $5\src16__data_o$next[3:0]$10698 $4\src16__data_o$next[3:0]$10697 + end + case + assign $1\src16__data_o$next[3:0]$10694 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $6\src16__data_o$next[3:0]$10699 4'0000 + case + assign $6\src16__data_o$next[3:0]$10699 $1\src16__data_o$next[3:0]$10694 + end + sync always + update \src16__data_o$next $0\src16__data_o$next[3:0]$10693 + end + attribute \src "issuer_ls180.v:166139.3-166168.6" + process $proc$issuer_ls180.v:166139$10700 + assign { } { } + assign { } { } + assign $0\wr_detect[0:0] $1\wr_detect[0:0] + attribute \src "issuer_ls180.v:166140.5-166140.29" + switch \initial + attribute \src "issuer_ls180.v:166140.9-166140.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \src16__ren + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\wr_detect[0:0] $4\wr_detect[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest16__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\wr_detect[0:0] 1'1 + case + assign $2\wr_detect[0:0] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest26__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\wr_detect[0:0] 1'1 + case + assign $3\wr_detect[0:0] $2\wr_detect[0:0] + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w6__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\wr_detect[0:0] 1'1 + case + assign $4\wr_detect[0:0] $3\wr_detect[0:0] + end + case + assign $1\wr_detect[0:0] 1'0 + end + sync always + update \wr_detect $0\wr_detect[0:0] + end + attribute \src "issuer_ls180.v:166169.3-166195.6" + process $proc$issuer_ls180.v:166169$10701 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\reg$next[3:0]$10702 $4\reg$next[3:0]$10706 + attribute \src "issuer_ls180.v:166170.5-166170.29" + switch \initial + attribute \src "issuer_ls180.v:166170.9-166170.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" + switch \dest16__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\reg$next[3:0]$10703 \dest16__data_i + case + assign $1\reg$next[3:0]$10703 \reg + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" + switch \dest26__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\reg$next[3:0]$10704 \dest26__data_i + case + assign $2\reg$next[3:0]$10704 $1\reg$next[3:0]$10703 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" + switch \w6__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\reg$next[3:0]$10705 \w6__data_i + case + assign $3\reg$next[3:0]$10705 $2\reg$next[3:0]$10704 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\reg$next[3:0]$10706 4'0000 + case + assign $4\reg$next[3:0]$10706 $3\reg$next[3:0]$10705 + end + sync always + update \reg$next $0\reg$next[3:0]$10702 + end + attribute \src "issuer_ls180.v:166196.3-166235.6" + process $proc$issuer_ls180.v:166196$10707 + assign { } { } + assign { } { } + assign { } { } + assign $0\src26__data_o$next[3:0]$10708 $6\src26__data_o$next[3:0]$10714 + attribute \src "issuer_ls180.v:166197.5-166197.29" + switch \initial + attribute \src "issuer_ls180.v:166197.9-166197.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \src26__ren + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\src26__data_o$next[3:0]$10709 $5\src26__data_o$next[3:0]$10713 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest16__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\src26__data_o$next[3:0]$10710 \dest16__data_i + case + assign $2\src26__data_o$next[3:0]$10710 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest26__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\src26__data_o$next[3:0]$10711 \dest26__data_i + case + assign $3\src26__data_o$next[3:0]$10711 $2\src26__data_o$next[3:0]$10710 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w6__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\src26__data_o$next[3:0]$10712 \w6__data_i + case + assign $4\src26__data_o$next[3:0]$10712 $3\src26__data_o$next[3:0]$10711 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + switch \$3 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\src26__data_o$next[3:0]$10713 \reg + case + assign $5\src26__data_o$next[3:0]$10713 $4\src26__data_o$next[3:0]$10712 + end + case + assign $1\src26__data_o$next[3:0]$10709 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $6\src26__data_o$next[3:0]$10714 4'0000 + case + assign $6\src26__data_o$next[3:0]$10714 $1\src26__data_o$next[3:0]$10709 + end + sync always + update \src26__data_o$next $0\src26__data_o$next[3:0]$10708 + end + attribute \src "issuer_ls180.v:166236.3-166265.6" + process $proc$issuer_ls180.v:166236$10715 + assign { } { } + assign { } { } + assign $0\wr_detect$4[0:0]$10716 $1\wr_detect$4[0:0]$10717 + attribute \src "issuer_ls180.v:166237.5-166237.29" + switch \initial + attribute \src "issuer_ls180.v:166237.9-166237.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \src26__ren + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\wr_detect$4[0:0]$10717 $4\wr_detect$4[0:0]$10720 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest16__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\wr_detect$4[0:0]$10718 1'1 + case + assign $2\wr_detect$4[0:0]$10718 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest26__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\wr_detect$4[0:0]$10719 1'1 + case + assign $3\wr_detect$4[0:0]$10719 $2\wr_detect$4[0:0]$10718 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w6__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\wr_detect$4[0:0]$10720 1'1 + case + assign $4\wr_detect$4[0:0]$10720 $3\wr_detect$4[0:0]$10719 + end + case + assign $1\wr_detect$4[0:0]$10717 1'0 + end + sync always + update \wr_detect$4 $0\wr_detect$4[0:0]$10716 + end + attribute \src "issuer_ls180.v:166266.3-166305.6" + process $proc$issuer_ls180.v:166266$10721 + assign { } { } + assign { } { } + assign { } { } + assign $0\src36__data_o$next[3:0]$10722 $6\src36__data_o$next[3:0]$10728 + attribute \src "issuer_ls180.v:166267.5-166267.29" + switch \initial + attribute \src "issuer_ls180.v:166267.9-166267.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \src36__ren + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\src36__data_o$next[3:0]$10723 $5\src36__data_o$next[3:0]$10727 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest16__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\src36__data_o$next[3:0]$10724 \dest16__data_i + case + assign $2\src36__data_o$next[3:0]$10724 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest26__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\src36__data_o$next[3:0]$10725 \dest26__data_i + case + assign $3\src36__data_o$next[3:0]$10725 $2\src36__data_o$next[3:0]$10724 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w6__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\src36__data_o$next[3:0]$10726 \w6__data_i + case + assign $4\src36__data_o$next[3:0]$10726 $3\src36__data_o$next[3:0]$10725 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + switch \$6 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\src36__data_o$next[3:0]$10727 \reg + case + assign $5\src36__data_o$next[3:0]$10727 $4\src36__data_o$next[3:0]$10726 + end + case + assign $1\src36__data_o$next[3:0]$10723 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $6\src36__data_o$next[3:0]$10728 4'0000 + case + assign $6\src36__data_o$next[3:0]$10728 $1\src36__data_o$next[3:0]$10723 + end + sync always + update \src36__data_o$next $0\src36__data_o$next[3:0]$10722 + end + attribute \src "issuer_ls180.v:166306.3-166335.6" + process $proc$issuer_ls180.v:166306$10729 + assign { } { } + assign { } { } + assign $0\wr_detect$7[0:0]$10730 $1\wr_detect$7[0:0]$10731 + attribute \src "issuer_ls180.v:166307.5-166307.29" + switch \initial + attribute \src "issuer_ls180.v:166307.9-166307.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \src36__ren + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\wr_detect$7[0:0]$10731 $4\wr_detect$7[0:0]$10734 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest16__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\wr_detect$7[0:0]$10732 1'1 + case + assign $2\wr_detect$7[0:0]$10732 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest26__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\wr_detect$7[0:0]$10733 1'1 + case + assign $3\wr_detect$7[0:0]$10733 $2\wr_detect$7[0:0]$10732 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w6__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\wr_detect$7[0:0]$10734 1'1 + case + assign $4\wr_detect$7[0:0]$10734 $3\wr_detect$7[0:0]$10733 + end + case + assign $1\wr_detect$7[0:0]$10731 1'0 + end + sync always + update \wr_detect$7 $0\wr_detect$7[0:0]$10730 + end + attribute \src "issuer_ls180.v:166336.3-166375.6" + process $proc$issuer_ls180.v:166336$10735 + assign { } { } + assign { } { } + assign { } { } + assign $0\r6__data_o$next[3:0]$10736 $6\r6__data_o$next[3:0]$10742 + attribute \src "issuer_ls180.v:166337.5-166337.29" + switch \initial + attribute \src "issuer_ls180.v:166337.9-166337.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \r6__ren + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\r6__data_o$next[3:0]$10737 $5\r6__data_o$next[3:0]$10741 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest16__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\r6__data_o$next[3:0]$10738 \dest16__data_i + case + assign $2\r6__data_o$next[3:0]$10738 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest26__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\r6__data_o$next[3:0]$10739 \dest26__data_i + case + assign $3\r6__data_o$next[3:0]$10739 $2\r6__data_o$next[3:0]$10738 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w6__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\r6__data_o$next[3:0]$10740 \w6__data_i + case + assign $4\r6__data_o$next[3:0]$10740 $3\r6__data_o$next[3:0]$10739 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + switch \$9 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\r6__data_o$next[3:0]$10741 \reg + case + assign $5\r6__data_o$next[3:0]$10741 $4\r6__data_o$next[3:0]$10740 + end + case + assign $1\r6__data_o$next[3:0]$10737 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $6\r6__data_o$next[3:0]$10742 4'0000 + case + assign $6\r6__data_o$next[3:0]$10742 $1\r6__data_o$next[3:0]$10737 + end + sync always + update \r6__data_o$next $0\r6__data_o$next[3:0]$10736 + end + attribute \src "issuer_ls180.v:166376.3-166405.6" + process $proc$issuer_ls180.v:166376$10743 + assign { } { } + assign { } { } + assign $0\wr_detect$10[0:0]$10744 $1\wr_detect$10[0:0]$10745 + attribute \src "issuer_ls180.v:166377.5-166377.29" + switch \initial + attribute \src "issuer_ls180.v:166377.9-166377.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \r6__ren + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\wr_detect$10[0:0]$10745 $4\wr_detect$10[0:0]$10748 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest16__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\wr_detect$10[0:0]$10746 1'1 + case + assign $2\wr_detect$10[0:0]$10746 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest26__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\wr_detect$10[0:0]$10747 1'1 + case + assign $3\wr_detect$10[0:0]$10747 $2\wr_detect$10[0:0]$10746 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w6__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\wr_detect$10[0:0]$10748 1'1 + case + assign $4\wr_detect$10[0:0]$10748 $3\wr_detect$10[0:0]$10747 + end + case + assign $1\wr_detect$10[0:0]$10745 1'0 + end + sync always + update \wr_detect$10 $0\wr_detect$10[0:0]$10744 + end + attribute \src "issuer_ls180.v:166406.3-166445.6" + process $proc$issuer_ls180.v:166406$10749 + assign { } { } + assign { } { } + assign { } { } + assign $0\r26__data_o$next[3:0]$10750 $6\r26__data_o$next[3:0]$10756 + attribute \src "issuer_ls180.v:166407.5-166407.29" + switch \initial + attribute \src "issuer_ls180.v:166407.9-166407.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \r26__ren + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\r26__data_o$next[3:0]$10751 $5\r26__data_o$next[3:0]$10755 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest16__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\r26__data_o$next[3:0]$10752 \dest16__data_i + case + assign $2\r26__data_o$next[3:0]$10752 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest26__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\r26__data_o$next[3:0]$10753 \dest26__data_i + case + assign $3\r26__data_o$next[3:0]$10753 $2\r26__data_o$next[3:0]$10752 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w6__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\r26__data_o$next[3:0]$10754 \w6__data_i + case + assign $4\r26__data_o$next[3:0]$10754 $3\r26__data_o$next[3:0]$10753 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + switch \$12 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\r26__data_o$next[3:0]$10755 \reg + case + assign $5\r26__data_o$next[3:0]$10755 $4\r26__data_o$next[3:0]$10754 + end + case + assign $1\r26__data_o$next[3:0]$10751 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $6\r26__data_o$next[3:0]$10756 4'0000 + case + assign $6\r26__data_o$next[3:0]$10756 $1\r26__data_o$next[3:0]$10751 + end + sync always + update \r26__data_o$next $0\r26__data_o$next[3:0]$10750 + end + attribute \src "issuer_ls180.v:166446.3-166475.6" + process $proc$issuer_ls180.v:166446$10757 + assign { } { } + assign { } { } + assign $0\wr_detect$13[0:0]$10758 $1\wr_detect$13[0:0]$10759 + attribute \src "issuer_ls180.v:166447.5-166447.29" + switch \initial + attribute \src "issuer_ls180.v:166447.9-166447.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \r26__ren + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\wr_detect$13[0:0]$10759 $4\wr_detect$13[0:0]$10762 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest16__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\wr_detect$13[0:0]$10760 1'1 + case + assign $2\wr_detect$13[0:0]$10760 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest26__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\wr_detect$13[0:0]$10761 1'1 + case + assign $3\wr_detect$13[0:0]$10761 $2\wr_detect$13[0:0]$10760 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w6__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\wr_detect$13[0:0]$10762 1'1 + case + assign $4\wr_detect$13[0:0]$10762 $3\wr_detect$13[0:0]$10761 + end + case + assign $1\wr_detect$13[0:0]$10759 1'0 + end + sync always + update \wr_detect$13 $0\wr_detect$13[0:0]$10758 + end + connect \$9 $not$issuer_ls180.v:166082$10681_Y + connect \$12 $not$issuer_ls180.v:166083$10682_Y + connect \$1 $not$issuer_ls180.v:166084$10683_Y + connect \$3 $not$issuer_ls180.v:166085$10684_Y + connect \$6 $not$issuer_ls180.v:166086$10685_Y +end +attribute \src "issuer_ls180.v:166480.1-166951.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.cr.reg_7" +attribute \generator "nMigen" +module \reg_7 + attribute \src "issuer_ls180.v:166481.7-166481.20" + wire $0\initial[0:0] + attribute \src "issuer_ls180.v:166881.3-166920.6" + wire width 4 $0\r27__data_o$next[3:0]$10839 + attribute \src "issuer_ls180.v:166564.3-166565.39" + wire width 4 $0\r27__data_o[3:0] + attribute \src "issuer_ls180.v:166811.3-166850.6" + wire width 4 $0\r7__data_o$next[3:0]$10825 + attribute \src "issuer_ls180.v:166566.3-166567.37" + wire width 4 $0\r7__data_o[3:0] + attribute \src "issuer_ls180.v:166644.3-166670.6" + wire width 4 $0\reg$next[3:0]$10791 + attribute \src "issuer_ls180.v:166562.3-166563.25" + wire width 4 $0\reg[3:0] + attribute \src "issuer_ls180.v:166574.3-166613.6" + wire width 4 $0\src17__data_o$next[3:0]$10782 + attribute \src "issuer_ls180.v:166572.3-166573.43" + wire width 4 $0\src17__data_o[3:0] + attribute \src "issuer_ls180.v:166671.3-166710.6" + wire width 4 $0\src27__data_o$next[3:0]$10797 + attribute \src "issuer_ls180.v:166570.3-166571.43" + wire width 4 $0\src27__data_o[3:0] + attribute \src "issuer_ls180.v:166741.3-166780.6" + wire width 4 $0\src37__data_o$next[3:0]$10811 + attribute \src "issuer_ls180.v:166568.3-166569.43" + wire width 4 $0\src37__data_o[3:0] + attribute \src "issuer_ls180.v:166851.3-166880.6" + wire $0\wr_detect$10[0:0]$10833 + attribute \src "issuer_ls180.v:166921.3-166950.6" + wire $0\wr_detect$13[0:0]$10847 + attribute \src "issuer_ls180.v:166711.3-166740.6" + wire $0\wr_detect$4[0:0]$10805 + attribute \src "issuer_ls180.v:166781.3-166810.6" + wire $0\wr_detect$7[0:0]$10819 + attribute \src "issuer_ls180.v:166614.3-166643.6" + wire $0\wr_detect[0:0] + attribute \src "issuer_ls180.v:166881.3-166920.6" + wire width 4 $1\r27__data_o$next[3:0]$10840 + attribute \src "issuer_ls180.v:166506.13-166506.31" + wire width 4 $1\r27__data_o[3:0] + attribute \src "issuer_ls180.v:166811.3-166850.6" + wire width 4 $1\r7__data_o$next[3:0]$10826 + attribute \src "issuer_ls180.v:166513.13-166513.30" + wire width 4 $1\r7__data_o[3:0] + attribute \src "issuer_ls180.v:166644.3-166670.6" + wire width 4 $1\reg$next[3:0]$10792 + attribute \src "issuer_ls180.v:166519.13-166519.25" + wire width 4 $1\reg[3:0] + attribute \src "issuer_ls180.v:166574.3-166613.6" + wire width 4 $1\src17__data_o$next[3:0]$10783 + attribute \src "issuer_ls180.v:166524.13-166524.33" + wire width 4 $1\src17__data_o[3:0] + attribute \src "issuer_ls180.v:166671.3-166710.6" + wire width 4 $1\src27__data_o$next[3:0]$10798 + attribute \src "issuer_ls180.v:166531.13-166531.33" + wire width 4 $1\src27__data_o[3:0] + attribute \src "issuer_ls180.v:166741.3-166780.6" + wire width 4 $1\src37__data_o$next[3:0]$10812 + attribute \src "issuer_ls180.v:166538.13-166538.33" + wire width 4 $1\src37__data_o[3:0] + attribute \src "issuer_ls180.v:166851.3-166880.6" + wire $1\wr_detect$10[0:0]$10834 + attribute \src "issuer_ls180.v:166921.3-166950.6" + wire $1\wr_detect$13[0:0]$10848 + attribute \src "issuer_ls180.v:166711.3-166740.6" + wire $1\wr_detect$4[0:0]$10806 + attribute \src "issuer_ls180.v:166781.3-166810.6" + wire $1\wr_detect$7[0:0]$10820 + attribute \src "issuer_ls180.v:166614.3-166643.6" + wire $1\wr_detect[0:0] + attribute \src "issuer_ls180.v:166881.3-166920.6" + wire width 4 $2\r27__data_o$next[3:0]$10841 + attribute \src "issuer_ls180.v:166811.3-166850.6" + wire width 4 $2\r7__data_o$next[3:0]$10827 + attribute \src "issuer_ls180.v:166644.3-166670.6" + wire width 4 $2\reg$next[3:0]$10793 + attribute \src "issuer_ls180.v:166574.3-166613.6" + wire width 4 $2\src17__data_o$next[3:0]$10784 + attribute \src "issuer_ls180.v:166671.3-166710.6" + wire width 4 $2\src27__data_o$next[3:0]$10799 + attribute \src "issuer_ls180.v:166741.3-166780.6" + wire width 4 $2\src37__data_o$next[3:0]$10813 + attribute \src "issuer_ls180.v:166851.3-166880.6" + wire $2\wr_detect$10[0:0]$10835 + attribute \src "issuer_ls180.v:166921.3-166950.6" + wire $2\wr_detect$13[0:0]$10849 + attribute \src "issuer_ls180.v:166711.3-166740.6" + wire $2\wr_detect$4[0:0]$10807 + attribute \src "issuer_ls180.v:166781.3-166810.6" + wire $2\wr_detect$7[0:0]$10821 + attribute \src "issuer_ls180.v:166614.3-166643.6" + wire $2\wr_detect[0:0] + attribute \src "issuer_ls180.v:166881.3-166920.6" + wire width 4 $3\r27__data_o$next[3:0]$10842 + attribute \src "issuer_ls180.v:166811.3-166850.6" + wire width 4 $3\r7__data_o$next[3:0]$10828 + attribute \src "issuer_ls180.v:166644.3-166670.6" + wire width 4 $3\reg$next[3:0]$10794 + attribute \src "issuer_ls180.v:166574.3-166613.6" + wire width 4 $3\src17__data_o$next[3:0]$10785 + attribute \src "issuer_ls180.v:166671.3-166710.6" + wire width 4 $3\src27__data_o$next[3:0]$10800 + attribute \src "issuer_ls180.v:166741.3-166780.6" + wire width 4 $3\src37__data_o$next[3:0]$10814 + attribute \src "issuer_ls180.v:166851.3-166880.6" + wire $3\wr_detect$10[0:0]$10836 + attribute \src "issuer_ls180.v:166921.3-166950.6" + wire $3\wr_detect$13[0:0]$10850 + attribute \src "issuer_ls180.v:166711.3-166740.6" + wire $3\wr_detect$4[0:0]$10808 + attribute \src "issuer_ls180.v:166781.3-166810.6" + wire $3\wr_detect$7[0:0]$10822 + attribute \src "issuer_ls180.v:166614.3-166643.6" + wire $3\wr_detect[0:0] + attribute \src "issuer_ls180.v:166881.3-166920.6" + wire width 4 $4\r27__data_o$next[3:0]$10843 + attribute \src "issuer_ls180.v:166811.3-166850.6" + wire width 4 $4\r7__data_o$next[3:0]$10829 + attribute \src "issuer_ls180.v:166644.3-166670.6" + wire width 4 $4\reg$next[3:0]$10795 + attribute \src "issuer_ls180.v:166574.3-166613.6" + wire width 4 $4\src17__data_o$next[3:0]$10786 + attribute \src "issuer_ls180.v:166671.3-166710.6" + wire width 4 $4\src27__data_o$next[3:0]$10801 + attribute \src "issuer_ls180.v:166741.3-166780.6" + wire width 4 $4\src37__data_o$next[3:0]$10815 + attribute \src "issuer_ls180.v:166851.3-166880.6" + wire $4\wr_detect$10[0:0]$10837 + attribute \src "issuer_ls180.v:166921.3-166950.6" + wire $4\wr_detect$13[0:0]$10851 + attribute \src "issuer_ls180.v:166711.3-166740.6" + wire $4\wr_detect$4[0:0]$10809 + attribute \src "issuer_ls180.v:166781.3-166810.6" + wire $4\wr_detect$7[0:0]$10823 + attribute \src "issuer_ls180.v:166614.3-166643.6" + wire $4\wr_detect[0:0] + attribute \src "issuer_ls180.v:166881.3-166920.6" + wire width 4 $5\r27__data_o$next[3:0]$10844 + attribute \src "issuer_ls180.v:166811.3-166850.6" + wire width 4 $5\r7__data_o$next[3:0]$10830 + attribute \src "issuer_ls180.v:166574.3-166613.6" + wire width 4 $5\src17__data_o$next[3:0]$10787 + attribute \src "issuer_ls180.v:166671.3-166710.6" + wire width 4 $5\src27__data_o$next[3:0]$10802 + attribute \src "issuer_ls180.v:166741.3-166780.6" + wire width 4 $5\src37__data_o$next[3:0]$10816 + attribute \src "issuer_ls180.v:166881.3-166920.6" + wire width 4 $6\r27__data_o$next[3:0]$10845 + attribute \src "issuer_ls180.v:166811.3-166850.6" + wire width 4 $6\r7__data_o$next[3:0]$10831 + attribute \src "issuer_ls180.v:166574.3-166613.6" + wire width 4 $6\src17__data_o$next[3:0]$10788 + attribute \src "issuer_ls180.v:166671.3-166710.6" + wire width 4 $6\src27__data_o$next[3:0]$10803 + attribute \src "issuer_ls180.v:166741.3-166780.6" + wire width 4 $6\src37__data_o$next[3:0]$10817 + attribute \src "issuer_ls180.v:166557.17-166557.104" + wire $not$issuer_ls180.v:166557$10770_Y + attribute \src "issuer_ls180.v:166558.18-166558.105" + wire $not$issuer_ls180.v:166558$10771_Y + attribute \src "issuer_ls180.v:166559.17-166559.100" + wire $not$issuer_ls180.v:166559$10772_Y + attribute \src "issuer_ls180.v:166560.17-166560.103" + wire $not$issuer_ls180.v:166560$10773_Y + attribute \src "issuer_ls180.v:166561.17-166561.103" + wire $not$issuer_ls180.v:166561$10774_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + wire \$12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + wire \$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + wire \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" + wire input 18 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" + wire input 1 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 input 9 \dest17__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire input 8 \dest17__wen + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 input 11 \dest27__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire input 10 \dest27__wen + attribute \src "issuer_ls180.v:166481.7-166481.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 output 14 \r27__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 \r27__data_o$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire input 15 \r27__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 output 12 \r7__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 \r7__data_o$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire input 13 \r7__ren + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" + wire width 4 \reg + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" + wire width 4 \reg$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 output 3 \src17__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 \src17__data_o$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire input 2 \src17__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 output 5 \src27__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 \src27__data_o$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire input 4 \src27__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 output 7 \src37__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 \src37__data_o$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire input 6 \src37__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 input 16 \w7__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire input 17 \w7__wen + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" + wire \wr_detect + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" + wire \wr_detect$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" + wire \wr_detect$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" + wire \wr_detect$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" + wire \wr_detect$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + cell $not $not$issuer_ls180.v:166557$10770 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_detect$10 + connect \Y $not$issuer_ls180.v:166557$10770_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + cell $not $not$issuer_ls180.v:166558$10771 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_detect$13 + connect \Y $not$issuer_ls180.v:166558$10771_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + cell $not $not$issuer_ls180.v:166559$10772 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_detect + connect \Y $not$issuer_ls180.v:166559$10772_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + cell $not $not$issuer_ls180.v:166560$10773 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_detect$4 + connect \Y $not$issuer_ls180.v:166560$10773_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + cell $not $not$issuer_ls180.v:166561$10774 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_detect$7 + connect \Y $not$issuer_ls180.v:166561$10774_Y + end + attribute \src "issuer_ls180.v:166481.7-166481.20" + process $proc$issuer_ls180.v:166481$10852 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "issuer_ls180.v:166506.13-166506.31" + process $proc$issuer_ls180.v:166506$10853 + assign { } { } + assign $1\r27__data_o[3:0] 4'0000 + sync always + sync init + update \r27__data_o $1\r27__data_o[3:0] + end + attribute \src "issuer_ls180.v:166513.13-166513.30" + process $proc$issuer_ls180.v:166513$10854 + assign { } { } + assign $1\r7__data_o[3:0] 4'0000 + sync always + sync init + update \r7__data_o $1\r7__data_o[3:0] + end + attribute \src "issuer_ls180.v:166519.13-166519.25" + process $proc$issuer_ls180.v:166519$10855 + assign { } { } + assign $1\reg[3:0] 4'0000 + sync always + sync init + update \reg $1\reg[3:0] + end + attribute \src "issuer_ls180.v:166524.13-166524.33" + process $proc$issuer_ls180.v:166524$10856 + assign { } { } + assign $1\src17__data_o[3:0] 4'0000 + sync always + sync init + update \src17__data_o $1\src17__data_o[3:0] + end + attribute \src "issuer_ls180.v:166531.13-166531.33" + process $proc$issuer_ls180.v:166531$10857 + assign { } { } + assign $1\src27__data_o[3:0] 4'0000 + sync always + sync init + update \src27__data_o $1\src27__data_o[3:0] + end + attribute \src "issuer_ls180.v:166538.13-166538.33" + process $proc$issuer_ls180.v:166538$10858 + assign { } { } + assign $1\src37__data_o[3:0] 4'0000 + sync always + sync init + update \src37__data_o $1\src37__data_o[3:0] + end + attribute \src "issuer_ls180.v:166562.3-166563.25" + process $proc$issuer_ls180.v:166562$10775 + assign { } { } + assign $0\reg[3:0] \reg$next + sync posedge \coresync_clk + update \reg $0\reg[3:0] + end + attribute \src "issuer_ls180.v:166564.3-166565.39" + process $proc$issuer_ls180.v:166564$10776 + assign { } { } + assign $0\r27__data_o[3:0] \r27__data_o$next + sync posedge \coresync_clk + update \r27__data_o $0\r27__data_o[3:0] + end + attribute \src "issuer_ls180.v:166566.3-166567.37" + process $proc$issuer_ls180.v:166566$10777 + assign { } { } + assign $0\r7__data_o[3:0] \r7__data_o$next + sync posedge \coresync_clk + update \r7__data_o $0\r7__data_o[3:0] + end + attribute \src "issuer_ls180.v:166568.3-166569.43" + process $proc$issuer_ls180.v:166568$10778 + assign { } { } + assign $0\src37__data_o[3:0] \src37__data_o$next + sync posedge \coresync_clk + update \src37__data_o $0\src37__data_o[3:0] + end + attribute \src "issuer_ls180.v:166570.3-166571.43" + process $proc$issuer_ls180.v:166570$10779 + assign { } { } + assign $0\src27__data_o[3:0] \src27__data_o$next + sync posedge \coresync_clk + update \src27__data_o $0\src27__data_o[3:0] + end + attribute \src "issuer_ls180.v:166572.3-166573.43" + process $proc$issuer_ls180.v:166572$10780 + assign { } { } + assign $0\src17__data_o[3:0] \src17__data_o$next + sync posedge \coresync_clk + update \src17__data_o $0\src17__data_o[3:0] + end + attribute \src "issuer_ls180.v:166574.3-166613.6" + process $proc$issuer_ls180.v:166574$10781 + assign { } { } + assign { } { } + assign { } { } + assign $0\src17__data_o$next[3:0]$10782 $6\src17__data_o$next[3:0]$10788 + attribute \src "issuer_ls180.v:166575.5-166575.29" + switch \initial + attribute \src "issuer_ls180.v:166575.9-166575.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \src17__ren + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\src17__data_o$next[3:0]$10783 $5\src17__data_o$next[3:0]$10787 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest17__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\src17__data_o$next[3:0]$10784 \dest17__data_i + case + assign $2\src17__data_o$next[3:0]$10784 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest27__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\src17__data_o$next[3:0]$10785 \dest27__data_i + case + assign $3\src17__data_o$next[3:0]$10785 $2\src17__data_o$next[3:0]$10784 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w7__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\src17__data_o$next[3:0]$10786 \w7__data_i + case + assign $4\src17__data_o$next[3:0]$10786 $3\src17__data_o$next[3:0]$10785 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + switch \$1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\src17__data_o$next[3:0]$10787 \reg + case + assign $5\src17__data_o$next[3:0]$10787 $4\src17__data_o$next[3:0]$10786 + end + case + assign $1\src17__data_o$next[3:0]$10783 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $6\src17__data_o$next[3:0]$10788 4'0000 + case + assign $6\src17__data_o$next[3:0]$10788 $1\src17__data_o$next[3:0]$10783 + end + sync always + update \src17__data_o$next $0\src17__data_o$next[3:0]$10782 + end + attribute \src "issuer_ls180.v:166614.3-166643.6" + process $proc$issuer_ls180.v:166614$10789 + assign { } { } + assign { } { } + assign $0\wr_detect[0:0] $1\wr_detect[0:0] + attribute \src "issuer_ls180.v:166615.5-166615.29" + switch \initial + attribute \src "issuer_ls180.v:166615.9-166615.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \src17__ren + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\wr_detect[0:0] $4\wr_detect[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest17__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\wr_detect[0:0] 1'1 + case + assign $2\wr_detect[0:0] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest27__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\wr_detect[0:0] 1'1 + case + assign $3\wr_detect[0:0] $2\wr_detect[0:0] + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w7__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\wr_detect[0:0] 1'1 + case + assign $4\wr_detect[0:0] $3\wr_detect[0:0] + end + case + assign $1\wr_detect[0:0] 1'0 + end + sync always + update \wr_detect $0\wr_detect[0:0] + end + attribute \src "issuer_ls180.v:166644.3-166670.6" + process $proc$issuer_ls180.v:166644$10790 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\reg$next[3:0]$10791 $4\reg$next[3:0]$10795 + attribute \src "issuer_ls180.v:166645.5-166645.29" + switch \initial + attribute \src "issuer_ls180.v:166645.9-166645.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" + switch \dest17__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\reg$next[3:0]$10792 \dest17__data_i + case + assign $1\reg$next[3:0]$10792 \reg + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" + switch \dest27__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\reg$next[3:0]$10793 \dest27__data_i + case + assign $2\reg$next[3:0]$10793 $1\reg$next[3:0]$10792 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" + switch \w7__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\reg$next[3:0]$10794 \w7__data_i + case + assign $3\reg$next[3:0]$10794 $2\reg$next[3:0]$10793 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\reg$next[3:0]$10795 4'0000 + case + assign $4\reg$next[3:0]$10795 $3\reg$next[3:0]$10794 + end + sync always + update \reg$next $0\reg$next[3:0]$10791 + end + attribute \src "issuer_ls180.v:166671.3-166710.6" + process $proc$issuer_ls180.v:166671$10796 + assign { } { } + assign { } { } + assign { } { } + assign $0\src27__data_o$next[3:0]$10797 $6\src27__data_o$next[3:0]$10803 + attribute \src "issuer_ls180.v:166672.5-166672.29" + switch \initial + attribute \src "issuer_ls180.v:166672.9-166672.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \src27__ren + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\src27__data_o$next[3:0]$10798 $5\src27__data_o$next[3:0]$10802 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest17__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\src27__data_o$next[3:0]$10799 \dest17__data_i + case + assign $2\src27__data_o$next[3:0]$10799 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest27__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\src27__data_o$next[3:0]$10800 \dest27__data_i + case + assign $3\src27__data_o$next[3:0]$10800 $2\src27__data_o$next[3:0]$10799 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w7__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\src27__data_o$next[3:0]$10801 \w7__data_i + case + assign $4\src27__data_o$next[3:0]$10801 $3\src27__data_o$next[3:0]$10800 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + switch \$3 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\src27__data_o$next[3:0]$10802 \reg + case + assign $5\src27__data_o$next[3:0]$10802 $4\src27__data_o$next[3:0]$10801 + end + case + assign $1\src27__data_o$next[3:0]$10798 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $6\src27__data_o$next[3:0]$10803 4'0000 + case + assign $6\src27__data_o$next[3:0]$10803 $1\src27__data_o$next[3:0]$10798 + end + sync always + update \src27__data_o$next $0\src27__data_o$next[3:0]$10797 + end + attribute \src "issuer_ls180.v:166711.3-166740.6" + process $proc$issuer_ls180.v:166711$10804 + assign { } { } + assign { } { } + assign $0\wr_detect$4[0:0]$10805 $1\wr_detect$4[0:0]$10806 + attribute \src "issuer_ls180.v:166712.5-166712.29" + switch \initial + attribute \src "issuer_ls180.v:166712.9-166712.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \src27__ren + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\wr_detect$4[0:0]$10806 $4\wr_detect$4[0:0]$10809 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest17__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\wr_detect$4[0:0]$10807 1'1 + case + assign $2\wr_detect$4[0:0]$10807 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest27__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\wr_detect$4[0:0]$10808 1'1 + case + assign $3\wr_detect$4[0:0]$10808 $2\wr_detect$4[0:0]$10807 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w7__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\wr_detect$4[0:0]$10809 1'1 + case + assign $4\wr_detect$4[0:0]$10809 $3\wr_detect$4[0:0]$10808 + end + case + assign $1\wr_detect$4[0:0]$10806 1'0 + end + sync always + update \wr_detect$4 $0\wr_detect$4[0:0]$10805 + end + attribute \src "issuer_ls180.v:166741.3-166780.6" + process $proc$issuer_ls180.v:166741$10810 + assign { } { } + assign { } { } + assign { } { } + assign $0\src37__data_o$next[3:0]$10811 $6\src37__data_o$next[3:0]$10817 + attribute \src "issuer_ls180.v:166742.5-166742.29" + switch \initial + attribute \src "issuer_ls180.v:166742.9-166742.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \src37__ren + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\src37__data_o$next[3:0]$10812 $5\src37__data_o$next[3:0]$10816 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest17__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\src37__data_o$next[3:0]$10813 \dest17__data_i + case + assign $2\src37__data_o$next[3:0]$10813 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest27__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\src37__data_o$next[3:0]$10814 \dest27__data_i + case + assign $3\src37__data_o$next[3:0]$10814 $2\src37__data_o$next[3:0]$10813 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w7__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\src37__data_o$next[3:0]$10815 \w7__data_i + case + assign $4\src37__data_o$next[3:0]$10815 $3\src37__data_o$next[3:0]$10814 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + switch \$6 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\src37__data_o$next[3:0]$10816 \reg + case + assign $5\src37__data_o$next[3:0]$10816 $4\src37__data_o$next[3:0]$10815 + end + case + assign $1\src37__data_o$next[3:0]$10812 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $6\src37__data_o$next[3:0]$10817 4'0000 + case + assign $6\src37__data_o$next[3:0]$10817 $1\src37__data_o$next[3:0]$10812 + end + sync always + update \src37__data_o$next $0\src37__data_o$next[3:0]$10811 + end + attribute \src "issuer_ls180.v:166781.3-166810.6" + process $proc$issuer_ls180.v:166781$10818 + assign { } { } + assign { } { } + assign $0\wr_detect$7[0:0]$10819 $1\wr_detect$7[0:0]$10820 + attribute \src "issuer_ls180.v:166782.5-166782.29" + switch \initial + attribute \src "issuer_ls180.v:166782.9-166782.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \src37__ren + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\wr_detect$7[0:0]$10820 $4\wr_detect$7[0:0]$10823 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest17__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\wr_detect$7[0:0]$10821 1'1 + case + assign $2\wr_detect$7[0:0]$10821 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest27__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\wr_detect$7[0:0]$10822 1'1 + case + assign $3\wr_detect$7[0:0]$10822 $2\wr_detect$7[0:0]$10821 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w7__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\wr_detect$7[0:0]$10823 1'1 + case + assign $4\wr_detect$7[0:0]$10823 $3\wr_detect$7[0:0]$10822 + end + case + assign $1\wr_detect$7[0:0]$10820 1'0 + end + sync always + update \wr_detect$7 $0\wr_detect$7[0:0]$10819 + end + attribute \src "issuer_ls180.v:166811.3-166850.6" + process $proc$issuer_ls180.v:166811$10824 + assign { } { } + assign { } { } + assign { } { } + assign $0\r7__data_o$next[3:0]$10825 $6\r7__data_o$next[3:0]$10831 + attribute \src "issuer_ls180.v:166812.5-166812.29" + switch \initial + attribute \src "issuer_ls180.v:166812.9-166812.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \r7__ren + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\r7__data_o$next[3:0]$10826 $5\r7__data_o$next[3:0]$10830 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest17__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\r7__data_o$next[3:0]$10827 \dest17__data_i + case + assign $2\r7__data_o$next[3:0]$10827 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest27__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\r7__data_o$next[3:0]$10828 \dest27__data_i + case + assign $3\r7__data_o$next[3:0]$10828 $2\r7__data_o$next[3:0]$10827 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w7__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\r7__data_o$next[3:0]$10829 \w7__data_i + case + assign $4\r7__data_o$next[3:0]$10829 $3\r7__data_o$next[3:0]$10828 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + switch \$9 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\r7__data_o$next[3:0]$10830 \reg + case + assign $5\r7__data_o$next[3:0]$10830 $4\r7__data_o$next[3:0]$10829 + end + case + assign $1\r7__data_o$next[3:0]$10826 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $6\r7__data_o$next[3:0]$10831 4'0000 + case + assign $6\r7__data_o$next[3:0]$10831 $1\r7__data_o$next[3:0]$10826 + end + sync always + update \r7__data_o$next $0\r7__data_o$next[3:0]$10825 + end + attribute \src "issuer_ls180.v:166851.3-166880.6" + process $proc$issuer_ls180.v:166851$10832 + assign { } { } + assign { } { } + assign $0\wr_detect$10[0:0]$10833 $1\wr_detect$10[0:0]$10834 + attribute \src "issuer_ls180.v:166852.5-166852.29" + switch \initial + attribute \src "issuer_ls180.v:166852.9-166852.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \r7__ren + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\wr_detect$10[0:0]$10834 $4\wr_detect$10[0:0]$10837 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest17__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\wr_detect$10[0:0]$10835 1'1 + case + assign $2\wr_detect$10[0:0]$10835 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest27__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\wr_detect$10[0:0]$10836 1'1 + case + assign $3\wr_detect$10[0:0]$10836 $2\wr_detect$10[0:0]$10835 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w7__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\wr_detect$10[0:0]$10837 1'1 + case + assign $4\wr_detect$10[0:0]$10837 $3\wr_detect$10[0:0]$10836 + end + case + assign $1\wr_detect$10[0:0]$10834 1'0 + end + sync always + update \wr_detect$10 $0\wr_detect$10[0:0]$10833 + end + attribute \src "issuer_ls180.v:166881.3-166920.6" + process $proc$issuer_ls180.v:166881$10838 + assign { } { } + assign { } { } + assign { } { } + assign $0\r27__data_o$next[3:0]$10839 $6\r27__data_o$next[3:0]$10845 + attribute \src "issuer_ls180.v:166882.5-166882.29" + switch \initial + attribute \src "issuer_ls180.v:166882.9-166882.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \r27__ren + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\r27__data_o$next[3:0]$10840 $5\r27__data_o$next[3:0]$10844 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest17__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\r27__data_o$next[3:0]$10841 \dest17__data_i + case + assign $2\r27__data_o$next[3:0]$10841 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest27__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\r27__data_o$next[3:0]$10842 \dest27__data_i + case + assign $3\r27__data_o$next[3:0]$10842 $2\r27__data_o$next[3:0]$10841 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w7__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\r27__data_o$next[3:0]$10843 \w7__data_i + case + assign $4\r27__data_o$next[3:0]$10843 $3\r27__data_o$next[3:0]$10842 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" + switch \$12 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\r27__data_o$next[3:0]$10844 \reg + case + assign $5\r27__data_o$next[3:0]$10844 $4\r27__data_o$next[3:0]$10843 + end + case + assign $1\r27__data_o$next[3:0]$10840 4'0000 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $6\r27__data_o$next[3:0]$10845 4'0000 + case + assign $6\r27__data_o$next[3:0]$10845 $1\r27__data_o$next[3:0]$10840 + end + sync always + update \r27__data_o$next $0\r27__data_o$next[3:0]$10839 + end + attribute \src "issuer_ls180.v:166921.3-166950.6" + process $proc$issuer_ls180.v:166921$10846 + assign { } { } + assign { } { } + assign $0\wr_detect$13[0:0]$10847 $1\wr_detect$13[0:0]$10848 + attribute \src "issuer_ls180.v:166922.5-166922.29" + switch \initial + attribute \src "issuer_ls180.v:166922.9-166922.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" + switch \r27__ren + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\wr_detect$13[0:0]$10848 $4\wr_detect$13[0:0]$10851 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest17__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\wr_detect$13[0:0]$10849 1'1 + case + assign $2\wr_detect$13[0:0]$10849 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \dest27__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\wr_detect$13[0:0]$10850 1'1 + case + assign $3\wr_detect$13[0:0]$10850 $2\wr_detect$13[0:0]$10849 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" + switch \w7__wen + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\wr_detect$13[0:0]$10851 1'1 + case + assign $4\wr_detect$13[0:0]$10851 $3\wr_detect$13[0:0]$10850 + end + case + assign $1\wr_detect$13[0:0]$10848 1'0 + end + sync always + update \wr_detect$13 $0\wr_detect$13[0:0]$10847 + end + connect \$9 $not$issuer_ls180.v:166557$10770_Y + connect \$12 $not$issuer_ls180.v:166558$10771_Y + connect \$1 $not$issuer_ls180.v:166559$10772_Y + connect \$3 $not$issuer_ls180.v:166560$10773_Y + connect \$6 $not$issuer_ls180.v:166561$10774_Y +end +attribute \src "issuer_ls180.v:166955.1-167013.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.fus.alu0.req_l" +attribute \generator "nMigen" +module \req_l + attribute \src "issuer_ls180.v:166956.7-166956.20" + wire $0\initial[0:0] + attribute \src "issuer_ls180.v:167001.3-167009.6" + wire width 5 $0\q_int$next[4:0]$10869 + attribute \src "issuer_ls180.v:166999.3-167000.27" + wire width 5 $0\q_int[4:0] + attribute \src "issuer_ls180.v:167001.3-167009.6" + wire width 5 $1\q_int$next[4:0]$10870 + attribute \src "issuer_ls180.v:166978.13-166978.26" + wire width 5 $1\q_int[4:0] + attribute \src "issuer_ls180.v:166991.17-166991.96" + wire width 5 $and$issuer_ls180.v:166991$10859_Y + attribute \src "issuer_ls180.v:166996.17-166996.96" + wire width 5 $and$issuer_ls180.v:166996$10864_Y + attribute \src "issuer_ls180.v:166993.18-166993.93" + wire width 5 $not$issuer_ls180.v:166993$10861_Y + attribute \src "issuer_ls180.v:166995.17-166995.92" + wire width 5 $not$issuer_ls180.v:166995$10863_Y + attribute \src "issuer_ls180.v:166998.17-166998.92" + wire width 5 $not$issuer_ls180.v:166998$10866_Y + attribute \src "issuer_ls180.v:166992.18-166992.98" + wire width 5 $or$issuer_ls180.v:166992$10860_Y + attribute \src "issuer_ls180.v:166994.18-166994.99" + wire width 5 $or$issuer_ls180.v:166994$10862_Y + attribute \src "issuer_ls180.v:166997.17-166997.97" + wire width 5 $or$issuer_ls180.v:166997$10865_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire width 5 \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire width 5 \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire width 5 \$13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + wire width 5 \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire width 5 \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire width 5 \$5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire width 5 \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire width 5 \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" + wire input 5 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" + wire input 1 \coresync_rst + attribute \src "issuer_ls180.v:166956.7-166956.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire width 5 \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire width 5 \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire width 5 output 2 \q_req + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" + wire width 5 \qlq_req + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + wire width 5 \qn_req + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire width 5 input 4 \r_req + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire width 5 input 3 \s_req + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $and $and$issuer_ls180.v:166991$10859 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 5 + connect \A \q_int + connect \B \$7 + connect \Y $and$issuer_ls180.v:166991$10859_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $and $and$issuer_ls180.v:166996$10864 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 5 + connect \A \q_int + connect \B \$1 + connect \Y $and$issuer_ls180.v:166996$10864_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + cell $not $not$issuer_ls180.v:166993$10861 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \Y_WIDTH 5 + connect \A \q_req + connect \Y $not$issuer_ls180.v:166993$10861_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $not $not$issuer_ls180.v:166995$10863 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \Y_WIDTH 5 + connect \A \r_req + connect \Y $not$issuer_ls180.v:166995$10863_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $not $not$issuer_ls180.v:166998$10866 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \Y_WIDTH 5 + connect \A \r_req + connect \Y $not$issuer_ls180.v:166998$10866_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $or $or$issuer_ls180.v:166992$10860 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 5 + connect \A \$9 + connect \B \s_req + connect \Y $or$issuer_ls180.v:166992$10860_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + cell $or $or$issuer_ls180.v:166994$10862 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 5 + connect \A \q_req + connect \B \q_int + connect \Y $or$issuer_ls180.v:166994$10862_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $or $or$issuer_ls180.v:166997$10865 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 5 + connect \A \$3 + connect \B \s_req + connect \Y $or$issuer_ls180.v:166997$10865_Y + end + attribute \src "issuer_ls180.v:166956.7-166956.20" + process $proc$issuer_ls180.v:166956$10871 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "issuer_ls180.v:166978.13-166978.26" + process $proc$issuer_ls180.v:166978$10872 + assign { } { } + assign $1\q_int[4:0] 5'00000 + sync always + sync init + update \q_int $1\q_int[4:0] + end + attribute \src "issuer_ls180.v:166999.3-167000.27" + process $proc$issuer_ls180.v:166999$10867 + assign { } { } + assign $0\q_int[4:0] \q_int$next + sync posedge \coresync_clk + update \q_int $0\q_int[4:0] + end + attribute \src "issuer_ls180.v:167001.3-167009.6" + process $proc$issuer_ls180.v:167001$10868 + assign { } { } + assign { } { } + assign $0\q_int$next[4:0]$10869 $1\q_int$next[4:0]$10870 + attribute \src "issuer_ls180.v:167002.5-167002.29" + switch \initial + attribute \src "issuer_ls180.v:167002.9-167002.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\q_int$next[4:0]$10870 5'00000 + case + assign $1\q_int$next[4:0]$10870 \$5 + end + sync always + update \q_int$next $0\q_int$next[4:0]$10869 + end + connect \$9 $and$issuer_ls180.v:166991$10859_Y + connect \$11 $or$issuer_ls180.v:166992$10860_Y + connect \$13 $not$issuer_ls180.v:166993$10861_Y + connect \$15 $or$issuer_ls180.v:166994$10862_Y + connect \$1 $not$issuer_ls180.v:166995$10863_Y + connect \$3 $and$issuer_ls180.v:166996$10864_Y + connect \$5 $or$issuer_ls180.v:166997$10865_Y + connect \$7 $not$issuer_ls180.v:166998$10866_Y + connect \qlq_req \$15 + connect \qn_req \$13 + connect \q_req \$11 +end +attribute \src "issuer_ls180.v:167017.1-167075.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.fus.mul0.req_l" +attribute \generator "nMigen" +module \req_l$100 + attribute \src "issuer_ls180.v:167018.7-167018.20" + wire $0\initial[0:0] + attribute \src "issuer_ls180.v:167063.3-167071.6" + wire width 4 $0\q_int$next[3:0]$10883 + attribute \src "issuer_ls180.v:167061.3-167062.27" + wire width 4 $0\q_int[3:0] + attribute \src "issuer_ls180.v:167063.3-167071.6" + wire width 4 $1\q_int$next[3:0]$10884 + attribute \src "issuer_ls180.v:167040.13-167040.25" + wire width 4 $1\q_int[3:0] + attribute \src "issuer_ls180.v:167053.17-167053.96" + wire width 4 $and$issuer_ls180.v:167053$10873_Y + attribute \src "issuer_ls180.v:167058.17-167058.96" + wire width 4 $and$issuer_ls180.v:167058$10878_Y + attribute \src "issuer_ls180.v:167055.18-167055.93" + wire width 4 $not$issuer_ls180.v:167055$10875_Y + attribute \src "issuer_ls180.v:167057.17-167057.92" + wire width 4 $not$issuer_ls180.v:167057$10877_Y + attribute \src "issuer_ls180.v:167060.17-167060.92" + wire width 4 $not$issuer_ls180.v:167060$10880_Y + attribute \src "issuer_ls180.v:167054.18-167054.98" + wire width 4 $or$issuer_ls180.v:167054$10874_Y + attribute \src "issuer_ls180.v:167056.18-167056.99" + wire width 4 $or$issuer_ls180.v:167056$10876_Y + attribute \src "issuer_ls180.v:167059.17-167059.97" + wire width 4 $or$issuer_ls180.v:167059$10879_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire width 4 \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire width 4 \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire width 4 \$13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + wire width 4 \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire width 4 \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire width 4 \$5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire width 4 \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire width 4 \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" + wire input 5 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" + wire input 1 \coresync_rst + attribute \src "issuer_ls180.v:167018.7-167018.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire width 4 \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire width 4 \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire width 4 output 2 \q_req + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" + wire width 4 \qlq_req + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + wire width 4 \qn_req + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire width 4 input 4 \r_req + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire width 4 input 3 \s_req + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $and $and$issuer_ls180.v:167053$10873 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \q_int + connect \B \$7 + connect \Y $and$issuer_ls180.v:167053$10873_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $and $and$issuer_ls180.v:167058$10878 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \q_int + connect \B \$1 + connect \Y $and$issuer_ls180.v:167058$10878_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + cell $not $not$issuer_ls180.v:167055$10875 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \q_req + connect \Y $not$issuer_ls180.v:167055$10875_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $not $not$issuer_ls180.v:167057$10877 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \r_req + connect \Y $not$issuer_ls180.v:167057$10877_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $not $not$issuer_ls180.v:167060$10880 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \r_req + connect \Y $not$issuer_ls180.v:167060$10880_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $or $or$issuer_ls180.v:167054$10874 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \$9 + connect \B \s_req + connect \Y $or$issuer_ls180.v:167054$10874_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + cell $or $or$issuer_ls180.v:167056$10876 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \q_req + connect \B \q_int + connect \Y $or$issuer_ls180.v:167056$10876_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $or $or$issuer_ls180.v:167059$10879 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \$3 + connect \B \s_req + connect \Y $or$issuer_ls180.v:167059$10879_Y + end + attribute \src "issuer_ls180.v:167018.7-167018.20" + process $proc$issuer_ls180.v:167018$10885 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "issuer_ls180.v:167040.13-167040.25" + process $proc$issuer_ls180.v:167040$10886 + assign { } { } + assign $1\q_int[3:0] 4'0000 + sync always + sync init + update \q_int $1\q_int[3:0] + end + attribute \src "issuer_ls180.v:167061.3-167062.27" + process $proc$issuer_ls180.v:167061$10881 + assign { } { } + assign $0\q_int[3:0] \q_int$next + sync posedge \coresync_clk + update \q_int $0\q_int[3:0] + end + attribute \src "issuer_ls180.v:167063.3-167071.6" + process $proc$issuer_ls180.v:167063$10882 + assign { } { } + assign { } { } + assign $0\q_int$next[3:0]$10883 $1\q_int$next[3:0]$10884 + attribute \src "issuer_ls180.v:167064.5-167064.29" + switch \initial + attribute \src "issuer_ls180.v:167064.9-167064.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\q_int$next[3:0]$10884 4'0000 + case + assign $1\q_int$next[3:0]$10884 \$5 + end + sync always + update \q_int$next $0\q_int$next[3:0]$10883 + end + connect \$9 $and$issuer_ls180.v:167053$10873_Y + connect \$11 $or$issuer_ls180.v:167054$10874_Y + connect \$13 $not$issuer_ls180.v:167055$10875_Y + connect \$15 $or$issuer_ls180.v:167056$10876_Y + connect \$1 $not$issuer_ls180.v:167057$10877_Y + connect \$3 $and$issuer_ls180.v:167058$10878_Y + connect \$5 $or$issuer_ls180.v:167059$10879_Y + connect \$7 $not$issuer_ls180.v:167060$10880_Y + connect \qlq_req \$15 + connect \qn_req \$13 + connect \q_req \$11 +end +attribute \src "issuer_ls180.v:167079.1-167137.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.fus.shiftrot0.req_l" +attribute \generator "nMigen" +module \req_l$118 + attribute \src "issuer_ls180.v:167080.7-167080.20" + wire $0\initial[0:0] + attribute \src "issuer_ls180.v:167125.3-167133.6" + wire width 3 $0\q_int$next[2:0]$10897 + attribute \src "issuer_ls180.v:167123.3-167124.27" + wire width 3 $0\q_int[2:0] + attribute \src "issuer_ls180.v:167125.3-167133.6" + wire width 3 $1\q_int$next[2:0]$10898 + attribute \src "issuer_ls180.v:167102.13-167102.25" + wire width 3 $1\q_int[2:0] + attribute \src "issuer_ls180.v:167115.17-167115.96" + wire width 3 $and$issuer_ls180.v:167115$10887_Y + attribute \src "issuer_ls180.v:167120.17-167120.96" + wire width 3 $and$issuer_ls180.v:167120$10892_Y + attribute \src "issuer_ls180.v:167117.18-167117.93" + wire width 3 $not$issuer_ls180.v:167117$10889_Y + attribute \src "issuer_ls180.v:167119.17-167119.92" + wire width 3 $not$issuer_ls180.v:167119$10891_Y + attribute \src "issuer_ls180.v:167122.17-167122.92" + wire width 3 $not$issuer_ls180.v:167122$10894_Y + attribute \src "issuer_ls180.v:167116.18-167116.98" + wire width 3 $or$issuer_ls180.v:167116$10888_Y + attribute \src "issuer_ls180.v:167118.18-167118.99" + wire width 3 $or$issuer_ls180.v:167118$10890_Y + attribute \src "issuer_ls180.v:167121.17-167121.97" + wire width 3 $or$issuer_ls180.v:167121$10893_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire width 3 \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire width 3 \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire width 3 \$13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + wire width 3 \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire width 3 \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire width 3 \$5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire width 3 \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire width 3 \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" + wire input 5 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" + wire input 1 \coresync_rst + attribute \src "issuer_ls180.v:167080.7-167080.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire width 3 \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire width 3 \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire width 3 output 2 \q_req + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" + wire width 3 \qlq_req + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + wire width 3 \qn_req + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire width 3 input 4 \r_req + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire width 3 input 3 \s_req + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $and $and$issuer_ls180.v:167115$10887 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \q_int + connect \B \$7 + connect \Y $and$issuer_ls180.v:167115$10887_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $and $and$issuer_ls180.v:167120$10892 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \q_int + connect \B \$1 + connect \Y $and$issuer_ls180.v:167120$10892_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + cell $not $not$issuer_ls180.v:167117$10889 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \q_req + connect \Y $not$issuer_ls180.v:167117$10889_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $not $not$issuer_ls180.v:167119$10891 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \r_req + connect \Y $not$issuer_ls180.v:167119$10891_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $not $not$issuer_ls180.v:167122$10894 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \r_req + connect \Y $not$issuer_ls180.v:167122$10894_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $or $or$issuer_ls180.v:167116$10888 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \$9 + connect \B \s_req + connect \Y $or$issuer_ls180.v:167116$10888_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + cell $or $or$issuer_ls180.v:167118$10890 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \q_req + connect \B \q_int + connect \Y $or$issuer_ls180.v:167118$10890_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $or $or$issuer_ls180.v:167121$10893 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \$3 + connect \B \s_req + connect \Y $or$issuer_ls180.v:167121$10893_Y + end + attribute \src "issuer_ls180.v:167080.7-167080.20" + process $proc$issuer_ls180.v:167080$10899 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "issuer_ls180.v:167102.13-167102.25" + process $proc$issuer_ls180.v:167102$10900 + assign { } { } + assign $1\q_int[2:0] 3'000 + sync always + sync init + update \q_int $1\q_int[2:0] + end + attribute \src "issuer_ls180.v:167123.3-167124.27" + process $proc$issuer_ls180.v:167123$10895 + assign { } { } + assign $0\q_int[2:0] \q_int$next + sync posedge \coresync_clk + update \q_int $0\q_int[2:0] + end + attribute \src "issuer_ls180.v:167125.3-167133.6" + process $proc$issuer_ls180.v:167125$10896 + assign { } { } + assign { } { } + assign $0\q_int$next[2:0]$10897 $1\q_int$next[2:0]$10898 + attribute \src "issuer_ls180.v:167126.5-167126.29" + switch \initial + attribute \src "issuer_ls180.v:167126.9-167126.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\q_int$next[2:0]$10898 3'000 + case + assign $1\q_int$next[2:0]$10898 \$5 + end + sync always + update \q_int$next $0\q_int$next[2:0]$10897 + end + connect \$9 $and$issuer_ls180.v:167115$10887_Y + connect \$11 $or$issuer_ls180.v:167116$10888_Y + connect \$13 $not$issuer_ls180.v:167117$10889_Y + connect \$15 $or$issuer_ls180.v:167118$10890_Y + connect \$1 $not$issuer_ls180.v:167119$10891_Y + connect \$3 $and$issuer_ls180.v:167120$10892_Y + connect \$5 $or$issuer_ls180.v:167121$10893_Y + connect \$7 $not$issuer_ls180.v:167122$10894_Y + connect \qlq_req \$15 + connect \qn_req \$13 + connect \q_req \$11 +end +attribute \src "issuer_ls180.v:167141.1-167199.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.fus.cr0.req_l" +attribute \generator "nMigen" +module \req_l$12 + attribute \src "issuer_ls180.v:167142.7-167142.20" + wire $0\initial[0:0] + attribute \src "issuer_ls180.v:167187.3-167195.6" + wire width 3 $0\q_int$next[2:0]$10911 + attribute \src "issuer_ls180.v:167185.3-167186.27" + wire width 3 $0\q_int[2:0] + attribute \src "issuer_ls180.v:167187.3-167195.6" + wire width 3 $1\q_int$next[2:0]$10912 + attribute \src "issuer_ls180.v:167164.13-167164.25" + wire width 3 $1\q_int[2:0] + attribute \src "issuer_ls180.v:167177.17-167177.96" + wire width 3 $and$issuer_ls180.v:167177$10901_Y + attribute \src "issuer_ls180.v:167182.17-167182.96" + wire width 3 $and$issuer_ls180.v:167182$10906_Y + attribute \src "issuer_ls180.v:167179.18-167179.93" + wire width 3 $not$issuer_ls180.v:167179$10903_Y + attribute \src "issuer_ls180.v:167181.17-167181.92" + wire width 3 $not$issuer_ls180.v:167181$10905_Y + attribute \src "issuer_ls180.v:167184.17-167184.92" + wire width 3 $not$issuer_ls180.v:167184$10908_Y + attribute \src "issuer_ls180.v:167178.18-167178.98" + wire width 3 $or$issuer_ls180.v:167178$10902_Y + attribute \src "issuer_ls180.v:167180.18-167180.99" + wire width 3 $or$issuer_ls180.v:167180$10904_Y + attribute \src "issuer_ls180.v:167183.17-167183.97" + wire width 3 $or$issuer_ls180.v:167183$10907_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire width 3 \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire width 3 \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire width 3 \$13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + wire width 3 \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire width 3 \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire width 3 \$5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire width 3 \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire width 3 \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" + wire input 5 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" + wire input 1 \coresync_rst + attribute \src "issuer_ls180.v:167142.7-167142.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire width 3 \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire width 3 \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire width 3 output 2 \q_req + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" + wire width 3 \qlq_req + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + wire width 3 \qn_req + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire width 3 input 4 \r_req + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire width 3 input 3 \s_req + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $and $and$issuer_ls180.v:167177$10901 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \q_int + connect \B \$7 + connect \Y $and$issuer_ls180.v:167177$10901_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $and $and$issuer_ls180.v:167182$10906 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \q_int + connect \B \$1 + connect \Y $and$issuer_ls180.v:167182$10906_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + cell $not $not$issuer_ls180.v:167179$10903 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \q_req + connect \Y $not$issuer_ls180.v:167179$10903_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $not $not$issuer_ls180.v:167181$10905 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \r_req + connect \Y $not$issuer_ls180.v:167181$10905_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $not $not$issuer_ls180.v:167184$10908 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \r_req + connect \Y $not$issuer_ls180.v:167184$10908_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $or $or$issuer_ls180.v:167178$10902 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \$9 + connect \B \s_req + connect \Y $or$issuer_ls180.v:167178$10902_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + cell $or $or$issuer_ls180.v:167180$10904 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \q_req + connect \B \q_int + connect \Y $or$issuer_ls180.v:167180$10904_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $or $or$issuer_ls180.v:167183$10907 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \$3 + connect \B \s_req + connect \Y $or$issuer_ls180.v:167183$10907_Y + end + attribute \src "issuer_ls180.v:167142.7-167142.20" + process $proc$issuer_ls180.v:167142$10913 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "issuer_ls180.v:167164.13-167164.25" + process $proc$issuer_ls180.v:167164$10914 + assign { } { } + assign $1\q_int[2:0] 3'000 + sync always + sync init + update \q_int $1\q_int[2:0] + end + attribute \src "issuer_ls180.v:167185.3-167186.27" + process $proc$issuer_ls180.v:167185$10909 + assign { } { } + assign $0\q_int[2:0] \q_int$next + sync posedge \coresync_clk + update \q_int $0\q_int[2:0] + end + attribute \src "issuer_ls180.v:167187.3-167195.6" + process $proc$issuer_ls180.v:167187$10910 + assign { } { } + assign { } { } + assign $0\q_int$next[2:0]$10911 $1\q_int$next[2:0]$10912 + attribute \src "issuer_ls180.v:167188.5-167188.29" + switch \initial + attribute \src "issuer_ls180.v:167188.9-167188.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\q_int$next[2:0]$10912 3'000 + case + assign $1\q_int$next[2:0]$10912 \$5 + end + sync always + update \q_int$next $0\q_int$next[2:0]$10911 + end + connect \$9 $and$issuer_ls180.v:167177$10901_Y + connect \$11 $or$issuer_ls180.v:167178$10902_Y + connect \$13 $not$issuer_ls180.v:167179$10903_Y + connect \$15 $or$issuer_ls180.v:167180$10904_Y + connect \$1 $not$issuer_ls180.v:167181$10905_Y + connect \$3 $and$issuer_ls180.v:167182$10906_Y + connect \$5 $or$issuer_ls180.v:167183$10907_Y + connect \$7 $not$issuer_ls180.v:167184$10908_Y + connect \qlq_req \$15 + connect \qn_req \$13 + connect \q_req \$11 +end +attribute \src "issuer_ls180.v:167203.1-167261.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.fus.branch0.req_l" +attribute \generator "nMigen" +module \req_l$25 + attribute \src "issuer_ls180.v:167204.7-167204.20" + wire $0\initial[0:0] + attribute \src "issuer_ls180.v:167249.3-167257.6" + wire width 3 $0\q_int$next[2:0]$10925 + attribute \src "issuer_ls180.v:167247.3-167248.27" + wire width 3 $0\q_int[2:0] + attribute \src "issuer_ls180.v:167249.3-167257.6" + wire width 3 $1\q_int$next[2:0]$10926 + attribute \src "issuer_ls180.v:167226.13-167226.25" + wire width 3 $1\q_int[2:0] + attribute \src "issuer_ls180.v:167239.17-167239.96" + wire width 3 $and$issuer_ls180.v:167239$10915_Y + attribute \src "issuer_ls180.v:167244.17-167244.96" + wire width 3 $and$issuer_ls180.v:167244$10920_Y + attribute \src "issuer_ls180.v:167241.18-167241.93" + wire width 3 $not$issuer_ls180.v:167241$10917_Y + attribute \src "issuer_ls180.v:167243.17-167243.92" + wire width 3 $not$issuer_ls180.v:167243$10919_Y + attribute \src "issuer_ls180.v:167246.17-167246.92" + wire width 3 $not$issuer_ls180.v:167246$10922_Y + attribute \src "issuer_ls180.v:167240.18-167240.98" + wire width 3 $or$issuer_ls180.v:167240$10916_Y + attribute \src "issuer_ls180.v:167242.18-167242.99" + wire width 3 $or$issuer_ls180.v:167242$10918_Y + attribute \src "issuer_ls180.v:167245.17-167245.97" + wire width 3 $or$issuer_ls180.v:167245$10921_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire width 3 \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire width 3 \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire width 3 \$13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + wire width 3 \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire width 3 \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire width 3 \$5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire width 3 \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire width 3 \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" + wire input 5 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" + wire input 1 \coresync_rst + attribute \src "issuer_ls180.v:167204.7-167204.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire width 3 \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire width 3 \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire width 3 output 2 \q_req + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" + wire width 3 \qlq_req + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + wire width 3 \qn_req + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire width 3 input 4 \r_req + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire width 3 input 3 \s_req + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $and $and$issuer_ls180.v:167239$10915 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \q_int + connect \B \$7 + connect \Y $and$issuer_ls180.v:167239$10915_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $and $and$issuer_ls180.v:167244$10920 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \q_int + connect \B \$1 + connect \Y $and$issuer_ls180.v:167244$10920_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + cell $not $not$issuer_ls180.v:167241$10917 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \q_req + connect \Y $not$issuer_ls180.v:167241$10917_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $not $not$issuer_ls180.v:167243$10919 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \r_req + connect \Y $not$issuer_ls180.v:167243$10919_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $not $not$issuer_ls180.v:167246$10922 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \r_req + connect \Y $not$issuer_ls180.v:167246$10922_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $or $or$issuer_ls180.v:167240$10916 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \$9 + connect \B \s_req + connect \Y $or$issuer_ls180.v:167240$10916_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + cell $or $or$issuer_ls180.v:167242$10918 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \q_req + connect \B \q_int + connect \Y $or$issuer_ls180.v:167242$10918_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $or $or$issuer_ls180.v:167245$10921 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \$3 + connect \B \s_req + connect \Y $or$issuer_ls180.v:167245$10921_Y + end + attribute \src "issuer_ls180.v:167204.7-167204.20" + process $proc$issuer_ls180.v:167204$10927 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "issuer_ls180.v:167226.13-167226.25" + process $proc$issuer_ls180.v:167226$10928 + assign { } { } + assign $1\q_int[2:0] 3'000 + sync always + sync init + update \q_int $1\q_int[2:0] + end + attribute \src "issuer_ls180.v:167247.3-167248.27" + process $proc$issuer_ls180.v:167247$10923 + assign { } { } + assign $0\q_int[2:0] \q_int$next + sync posedge \coresync_clk + update \q_int $0\q_int[2:0] + end + attribute \src "issuer_ls180.v:167249.3-167257.6" + process $proc$issuer_ls180.v:167249$10924 + assign { } { } + assign { } { } + assign $0\q_int$next[2:0]$10925 $1\q_int$next[2:0]$10926 + attribute \src "issuer_ls180.v:167250.5-167250.29" + switch \initial + attribute \src "issuer_ls180.v:167250.9-167250.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\q_int$next[2:0]$10926 3'000 + case + assign $1\q_int$next[2:0]$10926 \$5 + end + sync always + update \q_int$next $0\q_int$next[2:0]$10925 + end + connect \$9 $and$issuer_ls180.v:167239$10915_Y + connect \$11 $or$issuer_ls180.v:167240$10916_Y + connect \$13 $not$issuer_ls180.v:167241$10917_Y + connect \$15 $or$issuer_ls180.v:167242$10918_Y + connect \$1 $not$issuer_ls180.v:167243$10919_Y + connect \$3 $and$issuer_ls180.v:167244$10920_Y + connect \$5 $or$issuer_ls180.v:167245$10921_Y + connect \$7 $not$issuer_ls180.v:167246$10922_Y + connect \qlq_req \$15 + connect \qn_req \$13 + connect \q_req \$11 +end +attribute \src "issuer_ls180.v:167265.1-167323.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.fus.trap0.req_l" +attribute \generator "nMigen" +module \req_l$38 + attribute \src "issuer_ls180.v:167266.7-167266.20" + wire $0\initial[0:0] + attribute \src "issuer_ls180.v:167311.3-167319.6" + wire width 5 $0\q_int$next[4:0]$10939 + attribute \src "issuer_ls180.v:167309.3-167310.27" + wire width 5 $0\q_int[4:0] + attribute \src "issuer_ls180.v:167311.3-167319.6" + wire width 5 $1\q_int$next[4:0]$10940 + attribute \src "issuer_ls180.v:167288.13-167288.26" + wire width 5 $1\q_int[4:0] + attribute \src "issuer_ls180.v:167301.17-167301.96" + wire width 5 $and$issuer_ls180.v:167301$10929_Y + attribute \src "issuer_ls180.v:167306.17-167306.96" + wire width 5 $and$issuer_ls180.v:167306$10934_Y + attribute \src "issuer_ls180.v:167303.18-167303.93" + wire width 5 $not$issuer_ls180.v:167303$10931_Y + attribute \src "issuer_ls180.v:167305.17-167305.92" + wire width 5 $not$issuer_ls180.v:167305$10933_Y + attribute \src "issuer_ls180.v:167308.17-167308.92" + wire width 5 $not$issuer_ls180.v:167308$10936_Y + attribute \src "issuer_ls180.v:167302.18-167302.98" + wire width 5 $or$issuer_ls180.v:167302$10930_Y + attribute \src "issuer_ls180.v:167304.18-167304.99" + wire width 5 $or$issuer_ls180.v:167304$10932_Y + attribute \src "issuer_ls180.v:167307.17-167307.97" + wire width 5 $or$issuer_ls180.v:167307$10935_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire width 5 \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire width 5 \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire width 5 \$13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + wire width 5 \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire width 5 \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire width 5 \$5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire width 5 \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire width 5 \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" + wire input 5 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" + wire input 1 \coresync_rst + attribute \src "issuer_ls180.v:167266.7-167266.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire width 5 \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire width 5 \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire width 5 output 2 \q_req + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" + wire width 5 \qlq_req + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + wire width 5 \qn_req + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire width 5 input 4 \r_req + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire width 5 input 3 \s_req + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $and $and$issuer_ls180.v:167301$10929 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 5 + connect \A \q_int + connect \B \$7 + connect \Y $and$issuer_ls180.v:167301$10929_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $and $and$issuer_ls180.v:167306$10934 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 5 + connect \A \q_int + connect \B \$1 + connect \Y $and$issuer_ls180.v:167306$10934_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + cell $not $not$issuer_ls180.v:167303$10931 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \Y_WIDTH 5 + connect \A \q_req + connect \Y $not$issuer_ls180.v:167303$10931_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $not $not$issuer_ls180.v:167305$10933 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \Y_WIDTH 5 + connect \A \r_req + connect \Y $not$issuer_ls180.v:167305$10933_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $not $not$issuer_ls180.v:167308$10936 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \Y_WIDTH 5 + connect \A \r_req + connect \Y $not$issuer_ls180.v:167308$10936_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $or $or$issuer_ls180.v:167302$10930 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 5 + connect \A \$9 + connect \B \s_req + connect \Y $or$issuer_ls180.v:167302$10930_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + cell $or $or$issuer_ls180.v:167304$10932 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 5 + connect \A \q_req + connect \B \q_int + connect \Y $or$issuer_ls180.v:167304$10932_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $or $or$issuer_ls180.v:167307$10935 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 5 + connect \A \$3 + connect \B \s_req + connect \Y $or$issuer_ls180.v:167307$10935_Y + end + attribute \src "issuer_ls180.v:167266.7-167266.20" + process $proc$issuer_ls180.v:167266$10941 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "issuer_ls180.v:167288.13-167288.26" + process $proc$issuer_ls180.v:167288$10942 + assign { } { } + assign $1\q_int[4:0] 5'00000 + sync always + sync init + update \q_int $1\q_int[4:0] + end + attribute \src "issuer_ls180.v:167309.3-167310.27" + process $proc$issuer_ls180.v:167309$10937 + assign { } { } + assign $0\q_int[4:0] \q_int$next + sync posedge \coresync_clk + update \q_int $0\q_int[4:0] + end + attribute \src "issuer_ls180.v:167311.3-167319.6" + process $proc$issuer_ls180.v:167311$10938 + assign { } { } + assign { } { } + assign $0\q_int$next[4:0]$10939 $1\q_int$next[4:0]$10940 + attribute \src "issuer_ls180.v:167312.5-167312.29" + switch \initial + attribute \src "issuer_ls180.v:167312.9-167312.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\q_int$next[4:0]$10940 5'00000 + case + assign $1\q_int$next[4:0]$10940 \$5 + end + sync always + update \q_int$next $0\q_int$next[4:0]$10939 + end + connect \$9 $and$issuer_ls180.v:167301$10929_Y + connect \$11 $or$issuer_ls180.v:167302$10930_Y + connect \$13 $not$issuer_ls180.v:167303$10931_Y + connect \$15 $or$issuer_ls180.v:167304$10932_Y + connect \$1 $not$issuer_ls180.v:167305$10933_Y + connect \$3 $and$issuer_ls180.v:167306$10934_Y + connect \$5 $or$issuer_ls180.v:167307$10935_Y + connect \$7 $not$issuer_ls180.v:167308$10936_Y + connect \qlq_req \$15 + connect \qn_req \$13 + connect \q_req \$11 +end +attribute \src "issuer_ls180.v:167327.1-167385.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.fus.logical0.req_l" +attribute \generator "nMigen" +module \req_l$54 + attribute \src "issuer_ls180.v:167328.7-167328.20" + wire $0\initial[0:0] + attribute \src "issuer_ls180.v:167373.3-167381.6" + wire width 2 $0\q_int$next[1:0]$10953 + attribute \src "issuer_ls180.v:167371.3-167372.27" + wire width 2 $0\q_int[1:0] + attribute \src "issuer_ls180.v:167373.3-167381.6" + wire width 2 $1\q_int$next[1:0]$10954 + attribute \src "issuer_ls180.v:167350.13-167350.25" + wire width 2 $1\q_int[1:0] + attribute \src "issuer_ls180.v:167363.17-167363.96" + wire width 2 $and$issuer_ls180.v:167363$10943_Y + attribute \src "issuer_ls180.v:167368.17-167368.96" + wire width 2 $and$issuer_ls180.v:167368$10948_Y + attribute \src "issuer_ls180.v:167365.18-167365.93" + wire width 2 $not$issuer_ls180.v:167365$10945_Y + attribute \src "issuer_ls180.v:167367.17-167367.92" + wire width 2 $not$issuer_ls180.v:167367$10947_Y + attribute \src "issuer_ls180.v:167370.17-167370.92" + wire width 2 $not$issuer_ls180.v:167370$10950_Y + attribute \src "issuer_ls180.v:167364.18-167364.98" + wire width 2 $or$issuer_ls180.v:167364$10944_Y + attribute \src "issuer_ls180.v:167366.18-167366.99" + wire width 2 $or$issuer_ls180.v:167366$10946_Y + attribute \src "issuer_ls180.v:167369.17-167369.97" + wire width 2 $or$issuer_ls180.v:167369$10949_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire width 2 \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire width 2 \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire width 2 \$13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + wire width 2 \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire width 2 \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire width 2 \$5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire width 2 \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire width 2 \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" + wire input 5 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" + wire input 1 \coresync_rst + attribute \src "issuer_ls180.v:167328.7-167328.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire width 2 \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire width 2 \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire width 2 output 2 \q_req + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" + wire width 2 \qlq_req + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + wire width 2 \qn_req + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire width 2 input 4 \r_req + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire width 2 input 3 \s_req + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $and $and$issuer_ls180.v:167363$10943 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 2 + connect \A \q_int + connect \B \$7 + connect \Y $and$issuer_ls180.v:167363$10943_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $and $and$issuer_ls180.v:167368$10948 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 2 + connect \A \q_int + connect \B \$1 + connect \Y $and$issuer_ls180.v:167368$10948_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + cell $not $not$issuer_ls180.v:167365$10945 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 2 + connect \A \q_req + connect \Y $not$issuer_ls180.v:167365$10945_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $not $not$issuer_ls180.v:167367$10947 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 2 + connect \A \r_req + connect \Y $not$issuer_ls180.v:167367$10947_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $not $not$issuer_ls180.v:167370$10950 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 2 + connect \A \r_req + connect \Y $not$issuer_ls180.v:167370$10950_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $or $or$issuer_ls180.v:167364$10944 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 2 + connect \A \$9 + connect \B \s_req + connect \Y $or$issuer_ls180.v:167364$10944_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + cell $or $or$issuer_ls180.v:167366$10946 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 2 + connect \A \q_req + connect \B \q_int + connect \Y $or$issuer_ls180.v:167366$10946_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $or $or$issuer_ls180.v:167369$10949 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 2 + connect \A \$3 + connect \B \s_req + connect \Y $or$issuer_ls180.v:167369$10949_Y + end + attribute \src "issuer_ls180.v:167328.7-167328.20" + process $proc$issuer_ls180.v:167328$10955 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "issuer_ls180.v:167350.13-167350.25" + process $proc$issuer_ls180.v:167350$10956 + assign { } { } + assign $1\q_int[1:0] 2'00 + sync always + sync init + update \q_int $1\q_int[1:0] + end + attribute \src "issuer_ls180.v:167371.3-167372.27" + process $proc$issuer_ls180.v:167371$10951 + assign { } { } + assign $0\q_int[1:0] \q_int$next + sync posedge \coresync_clk + update \q_int $0\q_int[1:0] + end + attribute \src "issuer_ls180.v:167373.3-167381.6" + process $proc$issuer_ls180.v:167373$10952 + assign { } { } + assign { } { } + assign $0\q_int$next[1:0]$10953 $1\q_int$next[1:0]$10954 + attribute \src "issuer_ls180.v:167374.5-167374.29" + switch \initial + attribute \src "issuer_ls180.v:167374.9-167374.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\q_int$next[1:0]$10954 2'00 + case + assign $1\q_int$next[1:0]$10954 \$5 + end + sync always + update \q_int$next $0\q_int$next[1:0]$10953 + end + connect \$9 $and$issuer_ls180.v:167363$10943_Y + connect \$11 $or$issuer_ls180.v:167364$10944_Y + connect \$13 $not$issuer_ls180.v:167365$10945_Y + connect \$15 $or$issuer_ls180.v:167366$10946_Y + connect \$1 $not$issuer_ls180.v:167367$10947_Y + connect \$3 $and$issuer_ls180.v:167368$10948_Y + connect \$5 $or$issuer_ls180.v:167369$10949_Y + connect \$7 $not$issuer_ls180.v:167370$10950_Y + connect \qlq_req \$15 + connect \qn_req \$13 + connect \q_req \$11 +end +attribute \src "issuer_ls180.v:167389.1-167447.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.fus.spr0.req_l" +attribute \generator "nMigen" +module \req_l$66 + attribute \src "issuer_ls180.v:167390.7-167390.20" + wire $0\initial[0:0] + attribute \src "issuer_ls180.v:167435.3-167443.6" + wire width 6 $0\q_int$next[5:0]$10967 + attribute \src "issuer_ls180.v:167433.3-167434.27" + wire width 6 $0\q_int[5:0] + attribute \src "issuer_ls180.v:167435.3-167443.6" + wire width 6 $1\q_int$next[5:0]$10968 + attribute \src "issuer_ls180.v:167412.13-167412.26" + wire width 6 $1\q_int[5:0] + attribute \src "issuer_ls180.v:167425.17-167425.96" + wire width 6 $and$issuer_ls180.v:167425$10957_Y + attribute \src "issuer_ls180.v:167430.17-167430.96" + wire width 6 $and$issuer_ls180.v:167430$10962_Y + attribute \src "issuer_ls180.v:167427.18-167427.93" + wire width 6 $not$issuer_ls180.v:167427$10959_Y + attribute \src "issuer_ls180.v:167429.17-167429.92" + wire width 6 $not$issuer_ls180.v:167429$10961_Y + attribute \src "issuer_ls180.v:167432.17-167432.92" + wire width 6 $not$issuer_ls180.v:167432$10964_Y + attribute \src "issuer_ls180.v:167426.18-167426.98" + wire width 6 $or$issuer_ls180.v:167426$10958_Y + attribute \src "issuer_ls180.v:167428.18-167428.99" + wire width 6 $or$issuer_ls180.v:167428$10960_Y + attribute \src "issuer_ls180.v:167431.17-167431.97" + wire width 6 $or$issuer_ls180.v:167431$10963_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire width 6 \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire width 6 \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire width 6 \$13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + wire width 6 \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire width 6 \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire width 6 \$5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire width 6 \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire width 6 \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" + wire input 5 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" + wire input 1 \coresync_rst + attribute \src "issuer_ls180.v:167390.7-167390.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire width 6 \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire width 6 \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire width 6 output 2 \q_req + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" + wire width 6 \qlq_req + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + wire width 6 \qn_req + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire width 6 input 4 \r_req + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire width 6 input 3 \s_req + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $and $and$issuer_ls180.v:167425$10957 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 6 + connect \A \q_int + connect \B \$7 + connect \Y $and$issuer_ls180.v:167425$10957_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $and $and$issuer_ls180.v:167430$10962 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 6 + connect \A \q_int + connect \B \$1 + connect \Y $and$issuer_ls180.v:167430$10962_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + cell $not $not$issuer_ls180.v:167427$10959 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \Y_WIDTH 6 + connect \A \q_req + connect \Y $not$issuer_ls180.v:167427$10959_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $not $not$issuer_ls180.v:167429$10961 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \Y_WIDTH 6 + connect \A \r_req + connect \Y $not$issuer_ls180.v:167429$10961_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $not $not$issuer_ls180.v:167432$10964 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \Y_WIDTH 6 + connect \A \r_req + connect \Y $not$issuer_ls180.v:167432$10964_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $or $or$issuer_ls180.v:167426$10958 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 6 + connect \A \$9 + connect \B \s_req + connect \Y $or$issuer_ls180.v:167426$10958_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + cell $or $or$issuer_ls180.v:167428$10960 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 6 + connect \A \q_req + connect \B \q_int + connect \Y $or$issuer_ls180.v:167428$10960_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $or $or$issuer_ls180.v:167431$10963 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 6 + connect \A \$3 + connect \B \s_req + connect \Y $or$issuer_ls180.v:167431$10963_Y + end + attribute \src "issuer_ls180.v:167390.7-167390.20" + process $proc$issuer_ls180.v:167390$10969 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "issuer_ls180.v:167412.13-167412.26" + process $proc$issuer_ls180.v:167412$10970 + assign { } { } + assign $1\q_int[5:0] 6'000000 + sync always + sync init + update \q_int $1\q_int[5:0] + end + attribute \src "issuer_ls180.v:167433.3-167434.27" + process $proc$issuer_ls180.v:167433$10965 + assign { } { } + assign $0\q_int[5:0] \q_int$next + sync posedge \coresync_clk + update \q_int $0\q_int[5:0] + end + attribute \src "issuer_ls180.v:167435.3-167443.6" + process $proc$issuer_ls180.v:167435$10966 + assign { } { } + assign { } { } + assign $0\q_int$next[5:0]$10967 $1\q_int$next[5:0]$10968 + attribute \src "issuer_ls180.v:167436.5-167436.29" + switch \initial + attribute \src "issuer_ls180.v:167436.9-167436.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\q_int$next[5:0]$10968 6'000000 + case + assign $1\q_int$next[5:0]$10968 \$5 + end + sync always + update \q_int$next $0\q_int$next[5:0]$10967 + end + connect \$9 $and$issuer_ls180.v:167425$10957_Y + connect \$11 $or$issuer_ls180.v:167426$10958_Y + connect \$13 $not$issuer_ls180.v:167427$10959_Y + connect \$15 $or$issuer_ls180.v:167428$10960_Y + connect \$1 $not$issuer_ls180.v:167429$10961_Y + connect \$3 $and$issuer_ls180.v:167430$10962_Y + connect \$5 $or$issuer_ls180.v:167431$10963_Y + connect \$7 $not$issuer_ls180.v:167432$10964_Y + connect \qlq_req \$15 + connect \qn_req \$13 + connect \q_req \$11 +end +attribute \src "issuer_ls180.v:167451.1-167509.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.req_l" +attribute \generator "nMigen" +module \req_l$83 + attribute \src "issuer_ls180.v:167452.7-167452.20" + wire $0\initial[0:0] + attribute \src "issuer_ls180.v:167497.3-167505.6" + wire width 4 $0\q_int$next[3:0]$10981 + attribute \src "issuer_ls180.v:167495.3-167496.27" + wire width 4 $0\q_int[3:0] + attribute \src "issuer_ls180.v:167497.3-167505.6" + wire width 4 $1\q_int$next[3:0]$10982 + attribute \src "issuer_ls180.v:167474.13-167474.25" + wire width 4 $1\q_int[3:0] + attribute \src "issuer_ls180.v:167487.17-167487.96" + wire width 4 $and$issuer_ls180.v:167487$10971_Y + attribute \src "issuer_ls180.v:167492.17-167492.96" + wire width 4 $and$issuer_ls180.v:167492$10976_Y + attribute \src "issuer_ls180.v:167489.18-167489.93" + wire width 4 $not$issuer_ls180.v:167489$10973_Y + attribute \src "issuer_ls180.v:167491.17-167491.92" + wire width 4 $not$issuer_ls180.v:167491$10975_Y + attribute \src "issuer_ls180.v:167494.17-167494.92" + wire width 4 $not$issuer_ls180.v:167494$10978_Y + attribute \src "issuer_ls180.v:167488.18-167488.98" + wire width 4 $or$issuer_ls180.v:167488$10972_Y + attribute \src "issuer_ls180.v:167490.18-167490.99" + wire width 4 $or$issuer_ls180.v:167490$10974_Y + attribute \src "issuer_ls180.v:167493.17-167493.97" + wire width 4 $or$issuer_ls180.v:167493$10977_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire width 4 \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire width 4 \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire width 4 \$13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + wire width 4 \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire width 4 \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire width 4 \$5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire width 4 \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire width 4 \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" + wire input 5 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" + wire input 1 \coresync_rst + attribute \src "issuer_ls180.v:167452.7-167452.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire width 4 \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire width 4 \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire width 4 output 2 \q_req + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" + wire width 4 \qlq_req + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + wire width 4 \qn_req + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire width 4 input 4 \r_req + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire width 4 input 3 \s_req + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $and $and$issuer_ls180.v:167487$10971 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \q_int + connect \B \$7 + connect \Y $and$issuer_ls180.v:167487$10971_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $and $and$issuer_ls180.v:167492$10976 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \q_int + connect \B \$1 + connect \Y $and$issuer_ls180.v:167492$10976_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + cell $not $not$issuer_ls180.v:167489$10973 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \q_req + connect \Y $not$issuer_ls180.v:167489$10973_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $not $not$issuer_ls180.v:167491$10975 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \r_req + connect \Y $not$issuer_ls180.v:167491$10975_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $not $not$issuer_ls180.v:167494$10978 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \r_req + connect \Y $not$issuer_ls180.v:167494$10978_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $or $or$issuer_ls180.v:167488$10972 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \$9 + connect \B \s_req + connect \Y $or$issuer_ls180.v:167488$10972_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + cell $or $or$issuer_ls180.v:167490$10974 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \q_req + connect \B \q_int + connect \Y $or$issuer_ls180.v:167490$10974_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $or $or$issuer_ls180.v:167493$10977 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \$3 + connect \B \s_req + connect \Y $or$issuer_ls180.v:167493$10977_Y + end + attribute \src "issuer_ls180.v:167452.7-167452.20" + process $proc$issuer_ls180.v:167452$10983 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "issuer_ls180.v:167474.13-167474.25" + process $proc$issuer_ls180.v:167474$10984 + assign { } { } + assign $1\q_int[3:0] 4'0000 + sync always + sync init + update \q_int $1\q_int[3:0] + end + attribute \src "issuer_ls180.v:167495.3-167496.27" + process $proc$issuer_ls180.v:167495$10979 + assign { } { } + assign $0\q_int[3:0] \q_int$next + sync posedge \coresync_clk + update \q_int $0\q_int[3:0] + end + attribute \src "issuer_ls180.v:167497.3-167505.6" + process $proc$issuer_ls180.v:167497$10980 + assign { } { } + assign { } { } + assign $0\q_int$next[3:0]$10981 $1\q_int$next[3:0]$10982 + attribute \src "issuer_ls180.v:167498.5-167498.29" + switch \initial + attribute \src "issuer_ls180.v:167498.9-167498.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\q_int$next[3:0]$10982 4'0000 + case + assign $1\q_int$next[3:0]$10982 \$5 + end + sync always + update \q_int$next $0\q_int$next[3:0]$10981 + end + connect \$9 $and$issuer_ls180.v:167487$10971_Y + connect \$11 $or$issuer_ls180.v:167488$10972_Y + connect \$13 $not$issuer_ls180.v:167489$10973_Y + connect \$15 $or$issuer_ls180.v:167490$10974_Y + connect \$1 $not$issuer_ls180.v:167491$10975_Y + connect \$3 $and$issuer_ls180.v:167492$10976_Y + connect \$5 $or$issuer_ls180.v:167493$10977_Y + connect \$7 $not$issuer_ls180.v:167494$10978_Y + connect \qlq_req \$15 + connect \qn_req \$13 + connect \q_req \$11 +end +attribute \src "issuer_ls180.v:167513.1-167562.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.l0.pimem.reset_l" +attribute \generator "nMigen" +module \reset_l + attribute \src "issuer_ls180.v:167514.7-167514.20" + wire $0\initial[0:0] + attribute \src "issuer_ls180.v:167550.3-167558.6" + wire $0\q_int$next[0:0]$10992 + attribute \src "issuer_ls180.v:167548.3-167549.27" + wire $0\q_int[0:0] + attribute \src "issuer_ls180.v:167550.3-167558.6" + wire $1\q_int$next[0:0]$10993 + attribute \src "issuer_ls180.v:167530.7-167530.19" + wire $1\q_int[0:0] + attribute \src "issuer_ls180.v:167545.17-167545.96" + wire $and$issuer_ls180.v:167545$10987_Y + attribute \src "issuer_ls180.v:167544.17-167544.94" + wire $not$issuer_ls180.v:167544$10986_Y + attribute \src "issuer_ls180.v:167547.17-167547.94" + wire $not$issuer_ls180.v:167547$10989_Y + attribute \src "issuer_ls180.v:167543.17-167543.100" + wire $or$issuer_ls180.v:167543$10985_Y + attribute \src "issuer_ls180.v:167546.17-167546.99" + wire $or$issuer_ls180.v:167546$10988_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + wire \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" + wire input 5 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" + wire input 1 \coresync_rst + attribute \src "issuer_ls180.v:167514.7-167514.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire output 4 \q_reset + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" + wire \qlq_reset + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + wire \qn_reset + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire input 3 \r_reset + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire input 2 \s_reset + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $and $and$issuer_ls180.v:167545$10987 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$1 + connect \Y $and$issuer_ls180.v:167545$10987_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $not $not$issuer_ls180.v:167544$10986 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_reset + connect \Y $not$issuer_ls180.v:167544$10986_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + cell $not $not$issuer_ls180.v:167547$10989 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_reset + connect \Y $not$issuer_ls180.v:167547$10989_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + cell $or $or$issuer_ls180.v:167543$10985 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_reset + connect \B \q_int + connect \Y $or$issuer_ls180.v:167543$10985_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $or $or$issuer_ls180.v:167546$10988 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$3 + connect \B \s_reset + connect \Y $or$issuer_ls180.v:167546$10988_Y + end + attribute \src "issuer_ls180.v:167514.7-167514.20" + process $proc$issuer_ls180.v:167514$10994 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "issuer_ls180.v:167530.7-167530.19" + process $proc$issuer_ls180.v:167530$10995 + assign { } { } + assign $1\q_int[0:0] 1'0 + sync always + sync init + update \q_int $1\q_int[0:0] + end + attribute \src "issuer_ls180.v:167548.3-167549.27" + process $proc$issuer_ls180.v:167548$10990 + assign { } { } + assign $0\q_int[0:0] \q_int$next + sync posedge \coresync_clk + update \q_int $0\q_int[0:0] + end + attribute \src "issuer_ls180.v:167550.3-167558.6" + process $proc$issuer_ls180.v:167550$10991 + assign { } { } + assign { } { } + assign $0\q_int$next[0:0]$10992 $1\q_int$next[0:0]$10993 + attribute \src "issuer_ls180.v:167551.5-167551.29" + switch \initial + attribute \src "issuer_ls180.v:167551.9-167551.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\q_int$next[0:0]$10993 1'0 + case + assign $1\q_int$next[0:0]$10993 \$5 + end + sync always + update \q_int$next $0\q_int$next[0:0]$10992 + end + connect \$9 $or$issuer_ls180.v:167543$10985_Y + connect \$1 $not$issuer_ls180.v:167544$10986_Y + connect \$3 $and$issuer_ls180.v:167545$10987_Y + connect \$5 $or$issuer_ls180.v:167546$10988_Y + connect \$7 $not$issuer_ls180.v:167547$10989_Y + connect \qlq_reset \$9 + connect \qn_reset \$7 + connect \q_reset \q_int +end +attribute \src "issuer_ls180.v:167566.1-167615.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.l0.l0.reset_l" +attribute \generator "nMigen" +module \reset_l$128 + attribute \src "issuer_ls180.v:167567.7-167567.20" + wire $0\initial[0:0] + attribute \src "issuer_ls180.v:167603.3-167611.6" + wire $0\q_int$next[0:0]$11003 + attribute \src "issuer_ls180.v:167601.3-167602.27" + wire $0\q_int[0:0] + attribute \src "issuer_ls180.v:167603.3-167611.6" + wire $1\q_int$next[0:0]$11004 + attribute \src "issuer_ls180.v:167583.7-167583.19" + wire $1\q_int[0:0] + attribute \src "issuer_ls180.v:167598.17-167598.96" + wire $and$issuer_ls180.v:167598$10998_Y + attribute \src "issuer_ls180.v:167597.17-167597.94" + wire $not$issuer_ls180.v:167597$10997_Y + attribute \src "issuer_ls180.v:167600.17-167600.94" + wire $not$issuer_ls180.v:167600$11000_Y + attribute \src "issuer_ls180.v:167596.17-167596.100" + wire $or$issuer_ls180.v:167596$10996_Y + attribute \src "issuer_ls180.v:167599.17-167599.99" + wire $or$issuer_ls180.v:167599$10999_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + wire \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" + wire input 5 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" + wire input 1 \coresync_rst + attribute \src "issuer_ls180.v:167567.7-167567.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire output 4 \q_reset + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" + wire \qlq_reset + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + wire \qn_reset + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire input 3 \r_reset + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire input 2 \s_reset + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $and $and$issuer_ls180.v:167598$10998 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$1 + connect \Y $and$issuer_ls180.v:167598$10998_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $not $not$issuer_ls180.v:167597$10997 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_reset + connect \Y $not$issuer_ls180.v:167597$10997_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + cell $not $not$issuer_ls180.v:167600$11000 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_reset + connect \Y $not$issuer_ls180.v:167600$11000_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + cell $or $or$issuer_ls180.v:167596$10996 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_reset + connect \B \q_int + connect \Y $or$issuer_ls180.v:167596$10996_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $or $or$issuer_ls180.v:167599$10999 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$3 + connect \B \s_reset + connect \Y $or$issuer_ls180.v:167599$10999_Y + end + attribute \src "issuer_ls180.v:167567.7-167567.20" + process $proc$issuer_ls180.v:167567$11005 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "issuer_ls180.v:167583.7-167583.19" + process $proc$issuer_ls180.v:167583$11006 + assign { } { } + assign $1\q_int[0:0] 1'0 + sync always + sync init + update \q_int $1\q_int[0:0] + end + attribute \src "issuer_ls180.v:167601.3-167602.27" + process $proc$issuer_ls180.v:167601$11001 + assign { } { } + assign $0\q_int[0:0] \q_int$next + sync posedge \coresync_clk + update \q_int $0\q_int[0:0] + end + attribute \src "issuer_ls180.v:167603.3-167611.6" + process $proc$issuer_ls180.v:167603$11002 + assign { } { } + assign { } { } + assign $0\q_int$next[0:0]$11003 $1\q_int$next[0:0]$11004 + attribute \src "issuer_ls180.v:167604.5-167604.29" + switch \initial + attribute \src "issuer_ls180.v:167604.9-167604.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\q_int$next[0:0]$11004 1'0 + case + assign $1\q_int$next[0:0]$11004 \$5 + end + sync always + update \q_int$next $0\q_int$next[0:0]$11003 + end + connect \$9 $or$issuer_ls180.v:167596$10996_Y + connect \$1 $not$issuer_ls180.v:167597$10997_Y + connect \$3 $and$issuer_ls180.v:167598$10998_Y + connect \$5 $or$issuer_ls180.v:167599$10999_Y + connect \$7 $not$issuer_ls180.v:167600$11000_Y + connect \qlq_reset \$9 + connect \qn_reset \$7 + connect \q_reset \q_int +end +attribute \src "issuer_ls180.v:167619.1-168206.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.fus.shiftrot0.alu_shift_rot0.pipe1.main.rotator.right_mask" +attribute \generator "nMigen" +module \right_mask + attribute \src "issuer_ls180.v:167620.7-167620.20" + wire $0\initial[0:0] + attribute \src "issuer_ls180.v:167818.3-168205.6" + wire width 64 $0\mask[63:0] + attribute \src "issuer_ls180.v:167818.3-168205.6" + wire $10\mask[9:9] + attribute \src "issuer_ls180.v:167818.3-168205.6" + wire $11\mask[10:10] + attribute \src "issuer_ls180.v:167818.3-168205.6" + wire $12\mask[11:11] + attribute \src "issuer_ls180.v:167818.3-168205.6" + wire $13\mask[12:12] + attribute \src "issuer_ls180.v:167818.3-168205.6" + wire $14\mask[13:13] + attribute \src "issuer_ls180.v:167818.3-168205.6" + wire $15\mask[14:14] + attribute \src "issuer_ls180.v:167818.3-168205.6" + wire $16\mask[15:15] + attribute \src "issuer_ls180.v:167818.3-168205.6" + wire $17\mask[16:16] + attribute \src "issuer_ls180.v:167818.3-168205.6" + wire $18\mask[17:17] + attribute \src "issuer_ls180.v:167818.3-168205.6" + wire $19\mask[18:18] + attribute \src "issuer_ls180.v:167818.3-168205.6" + wire $1\mask[0:0] + attribute \src "issuer_ls180.v:167818.3-168205.6" + wire $20\mask[19:19] + attribute \src "issuer_ls180.v:167818.3-168205.6" + wire $21\mask[20:20] + attribute \src "issuer_ls180.v:167818.3-168205.6" + wire $22\mask[21:21] + attribute \src "issuer_ls180.v:167818.3-168205.6" + wire $23\mask[22:22] + attribute \src "issuer_ls180.v:167818.3-168205.6" + wire $24\mask[23:23] + attribute \src "issuer_ls180.v:167818.3-168205.6" + wire $25\mask[24:24] + attribute \src "issuer_ls180.v:167818.3-168205.6" + wire $26\mask[25:25] + attribute \src "issuer_ls180.v:167818.3-168205.6" + wire $27\mask[26:26] + attribute \src "issuer_ls180.v:167818.3-168205.6" + wire $28\mask[27:27] + attribute \src "issuer_ls180.v:167818.3-168205.6" + wire $29\mask[28:28] + attribute \src "issuer_ls180.v:167818.3-168205.6" + wire $2\mask[1:1] + attribute \src "issuer_ls180.v:167818.3-168205.6" + wire $30\mask[29:29] + attribute \src "issuer_ls180.v:167818.3-168205.6" + wire $31\mask[30:30] + attribute \src "issuer_ls180.v:167818.3-168205.6" + wire $32\mask[31:31] + attribute \src "issuer_ls180.v:167818.3-168205.6" + wire $33\mask[32:32] + attribute \src "issuer_ls180.v:167818.3-168205.6" + wire $34\mask[33:33] + attribute \src "issuer_ls180.v:167818.3-168205.6" + wire $35\mask[34:34] + attribute \src "issuer_ls180.v:167818.3-168205.6" + wire $36\mask[35:35] + attribute \src "issuer_ls180.v:167818.3-168205.6" + wire $37\mask[36:36] + attribute \src "issuer_ls180.v:167818.3-168205.6" + wire $38\mask[37:37] + attribute \src "issuer_ls180.v:167818.3-168205.6" + wire $39\mask[38:38] + attribute \src "issuer_ls180.v:167818.3-168205.6" + wire $3\mask[2:2] + attribute \src "issuer_ls180.v:167818.3-168205.6" + wire $40\mask[39:39] + attribute \src "issuer_ls180.v:167818.3-168205.6" + wire $41\mask[40:40] + attribute \src "issuer_ls180.v:167818.3-168205.6" + wire $42\mask[41:41] + attribute \src "issuer_ls180.v:167818.3-168205.6" + wire $43\mask[42:42] + attribute \src "issuer_ls180.v:167818.3-168205.6" + wire $44\mask[43:43] + attribute \src "issuer_ls180.v:167818.3-168205.6" + wire $45\mask[44:44] + attribute \src "issuer_ls180.v:167818.3-168205.6" + wire $46\mask[45:45] + attribute \src "issuer_ls180.v:167818.3-168205.6" + wire $47\mask[46:46] + attribute \src "issuer_ls180.v:167818.3-168205.6" + wire $48\mask[47:47] + attribute \src "issuer_ls180.v:167818.3-168205.6" + wire $49\mask[48:48] + attribute \src "issuer_ls180.v:167818.3-168205.6" + wire $4\mask[3:3] + attribute \src "issuer_ls180.v:167818.3-168205.6" + wire $50\mask[49:49] + attribute \src "issuer_ls180.v:167818.3-168205.6" + wire $51\mask[50:50] + attribute \src "issuer_ls180.v:167818.3-168205.6" + wire $52\mask[51:51] + attribute \src "issuer_ls180.v:167818.3-168205.6" + wire $53\mask[52:52] + attribute \src "issuer_ls180.v:167818.3-168205.6" + wire $54\mask[53:53] + attribute \src "issuer_ls180.v:167818.3-168205.6" + wire $55\mask[54:54] + attribute \src "issuer_ls180.v:167818.3-168205.6" + wire $56\mask[55:55] + attribute \src "issuer_ls180.v:167818.3-168205.6" + wire $57\mask[56:56] + attribute \src "issuer_ls180.v:167818.3-168205.6" + wire $58\mask[57:57] + attribute \src "issuer_ls180.v:167818.3-168205.6" + wire $59\mask[58:58] + attribute \src "issuer_ls180.v:167818.3-168205.6" + wire $5\mask[4:4] + attribute \src "issuer_ls180.v:167818.3-168205.6" + wire $60\mask[59:59] + attribute \src "issuer_ls180.v:167818.3-168205.6" + wire $61\mask[60:60] + attribute \src "issuer_ls180.v:167818.3-168205.6" + wire $62\mask[61:61] + attribute \src "issuer_ls180.v:167818.3-168205.6" + wire $63\mask[62:62] + attribute \src "issuer_ls180.v:167818.3-168205.6" + wire $64\mask[63:63] + attribute \src "issuer_ls180.v:167818.3-168205.6" + wire $6\mask[5:5] + attribute \src "issuer_ls180.v:167818.3-168205.6" + wire $7\mask[6:6] + attribute \src "issuer_ls180.v:167818.3-168205.6" + wire $8\mask[7:7] + attribute \src "issuer_ls180.v:167818.3-168205.6" + wire $9\mask[8:8] + attribute \src "issuer_ls180.v:167754.17-167754.96" + wire $gt$issuer_ls180.v:167754$11007_Y + attribute \src "issuer_ls180.v:167755.18-167755.98" + wire $gt$issuer_ls180.v:167755$11008_Y + attribute \src "issuer_ls180.v:167756.19-167756.99" + wire $gt$issuer_ls180.v:167756$11009_Y + attribute \src "issuer_ls180.v:167757.19-167757.99" + wire $gt$issuer_ls180.v:167757$11010_Y + attribute \src "issuer_ls180.v:167758.19-167758.99" + wire $gt$issuer_ls180.v:167758$11011_Y + attribute \src "issuer_ls180.v:167759.19-167759.99" + wire $gt$issuer_ls180.v:167759$11012_Y + attribute \src "issuer_ls180.v:167760.19-167760.99" + wire $gt$issuer_ls180.v:167760$11013_Y + attribute \src "issuer_ls180.v:167761.19-167761.99" + wire $gt$issuer_ls180.v:167761$11014_Y + attribute \src "issuer_ls180.v:167762.19-167762.99" + wire $gt$issuer_ls180.v:167762$11015_Y + attribute \src "issuer_ls180.v:167763.19-167763.99" + wire $gt$issuer_ls180.v:167763$11016_Y + attribute \src "issuer_ls180.v:167764.19-167764.99" + wire $gt$issuer_ls180.v:167764$11017_Y + attribute \src "issuer_ls180.v:167765.18-167765.97" + wire $gt$issuer_ls180.v:167765$11018_Y + attribute \src "issuer_ls180.v:167766.19-167766.99" + wire $gt$issuer_ls180.v:167766$11019_Y + attribute \src "issuer_ls180.v:167767.19-167767.99" + wire $gt$issuer_ls180.v:167767$11020_Y + attribute \src "issuer_ls180.v:167768.19-167768.99" + wire $gt$issuer_ls180.v:167768$11021_Y + attribute \src "issuer_ls180.v:167769.19-167769.99" + wire $gt$issuer_ls180.v:167769$11022_Y + attribute \src "issuer_ls180.v:167770.19-167770.99" + wire $gt$issuer_ls180.v:167770$11023_Y + attribute \src "issuer_ls180.v:167771.18-167771.97" + wire $gt$issuer_ls180.v:167771$11024_Y + attribute \src "issuer_ls180.v:167772.18-167772.97" + wire $gt$issuer_ls180.v:167772$11025_Y + attribute \src "issuer_ls180.v:167773.18-167773.97" + wire $gt$issuer_ls180.v:167773$11026_Y + attribute \src "issuer_ls180.v:167774.17-167774.96" + wire $gt$issuer_ls180.v:167774$11027_Y + attribute \src "issuer_ls180.v:167775.18-167775.97" + wire $gt$issuer_ls180.v:167775$11028_Y + attribute \src "issuer_ls180.v:167776.18-167776.97" + wire $gt$issuer_ls180.v:167776$11029_Y + attribute \src "issuer_ls180.v:167777.18-167777.97" + wire $gt$issuer_ls180.v:167777$11030_Y + attribute \src "issuer_ls180.v:167778.18-167778.97" + wire $gt$issuer_ls180.v:167778$11031_Y + attribute \src "issuer_ls180.v:167779.18-167779.97" + wire $gt$issuer_ls180.v:167779$11032_Y + attribute \src "issuer_ls180.v:167780.18-167780.97" + wire $gt$issuer_ls180.v:167780$11033_Y + attribute \src "issuer_ls180.v:167781.18-167781.97" + wire $gt$issuer_ls180.v:167781$11034_Y + attribute \src "issuer_ls180.v:167782.18-167782.98" + wire $gt$issuer_ls180.v:167782$11035_Y + attribute \src "issuer_ls180.v:167783.18-167783.98" + wire $gt$issuer_ls180.v:167783$11036_Y + attribute \src "issuer_ls180.v:167784.18-167784.98" + wire $gt$issuer_ls180.v:167784$11037_Y + attribute \src "issuer_ls180.v:167785.17-167785.96" + wire $gt$issuer_ls180.v:167785$11038_Y + attribute \src "issuer_ls180.v:167786.18-167786.98" + wire $gt$issuer_ls180.v:167786$11039_Y + attribute \src "issuer_ls180.v:167787.18-167787.98" + wire $gt$issuer_ls180.v:167787$11040_Y + attribute \src "issuer_ls180.v:167788.18-167788.98" + wire $gt$issuer_ls180.v:167788$11041_Y + attribute \src "issuer_ls180.v:167789.18-167789.98" + wire $gt$issuer_ls180.v:167789$11042_Y + attribute \src "issuer_ls180.v:167790.18-167790.98" + wire $gt$issuer_ls180.v:167790$11043_Y + attribute \src "issuer_ls180.v:167791.18-167791.98" + wire $gt$issuer_ls180.v:167791$11044_Y + attribute \src "issuer_ls180.v:167792.18-167792.98" + wire $gt$issuer_ls180.v:167792$11045_Y + attribute \src "issuer_ls180.v:167793.18-167793.98" + wire $gt$issuer_ls180.v:167793$11046_Y + attribute \src "issuer_ls180.v:167794.18-167794.98" + wire $gt$issuer_ls180.v:167794$11047_Y + attribute \src "issuer_ls180.v:167795.18-167795.98" + wire $gt$issuer_ls180.v:167795$11048_Y + attribute \src "issuer_ls180.v:167796.17-167796.96" + wire $gt$issuer_ls180.v:167796$11049_Y + attribute \src "issuer_ls180.v:167797.18-167797.98" + wire $gt$issuer_ls180.v:167797$11050_Y + attribute \src "issuer_ls180.v:167798.18-167798.98" + wire $gt$issuer_ls180.v:167798$11051_Y + attribute \src "issuer_ls180.v:167799.18-167799.98" + wire $gt$issuer_ls180.v:167799$11052_Y + attribute \src "issuer_ls180.v:167800.18-167800.98" + wire $gt$issuer_ls180.v:167800$11053_Y + attribute \src "issuer_ls180.v:167801.18-167801.98" + wire $gt$issuer_ls180.v:167801$11054_Y + attribute \src "issuer_ls180.v:167802.18-167802.98" + wire $gt$issuer_ls180.v:167802$11055_Y + attribute \src "issuer_ls180.v:167803.18-167803.98" + wire $gt$issuer_ls180.v:167803$11056_Y + attribute \src "issuer_ls180.v:167804.18-167804.98" + wire $gt$issuer_ls180.v:167804$11057_Y + attribute \src "issuer_ls180.v:167805.18-167805.98" + wire $gt$issuer_ls180.v:167805$11058_Y + attribute \src "issuer_ls180.v:167806.18-167806.98" + wire $gt$issuer_ls180.v:167806$11059_Y + attribute \src "issuer_ls180.v:167807.17-167807.96" + wire $gt$issuer_ls180.v:167807$11060_Y + attribute \src "issuer_ls180.v:167808.18-167808.98" + wire $gt$issuer_ls180.v:167808$11061_Y + attribute \src "issuer_ls180.v:167809.18-167809.98" + wire $gt$issuer_ls180.v:167809$11062_Y + attribute \src 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"/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + wire \$95 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + wire \$97 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + wire \$99 + attribute \src "issuer_ls180.v:167620.7-167620.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:12" + wire width 64 output 1 \mask + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:11" + wire width 7 input 2 \shift + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + cell $gt $gt$issuer_ls180.v:167754$11007 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 3'100 + connect \Y $gt$issuer_ls180.v:167754$11007_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + cell $gt $gt$issuer_ls180.v:167755$11008 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 6'110001 + connect \Y $gt$issuer_ls180.v:167755$11008_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + cell $gt $gt$issuer_ls180.v:167756$11009 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 6'110010 + connect \Y $gt$issuer_ls180.v:167756$11009_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + cell $gt $gt$issuer_ls180.v:167757$11010 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 6'110011 + connect \Y $gt$issuer_ls180.v:167757$11010_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + cell $gt $gt$issuer_ls180.v:167758$11011 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 6'110100 + connect \Y $gt$issuer_ls180.v:167758$11011_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + cell $gt $gt$issuer_ls180.v:167759$11012 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 6'110101 + connect \Y $gt$issuer_ls180.v:167759$11012_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + cell $gt $gt$issuer_ls180.v:167760$11013 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 6'110110 + connect \Y $gt$issuer_ls180.v:167760$11013_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + cell $gt $gt$issuer_ls180.v:167761$11014 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 6'110111 + connect \Y $gt$issuer_ls180.v:167761$11014_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + cell $gt $gt$issuer_ls180.v:167762$11015 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 6'111000 + connect \Y $gt$issuer_ls180.v:167762$11015_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + cell $gt $gt$issuer_ls180.v:167763$11016 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 6'111001 + connect \Y $gt$issuer_ls180.v:167763$11016_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + cell $gt $gt$issuer_ls180.v:167764$11017 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 6'111010 + connect \Y $gt$issuer_ls180.v:167764$11017_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + cell $gt $gt$issuer_ls180.v:167765$11018 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 3'101 + connect \Y $gt$issuer_ls180.v:167765$11018_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + cell $gt $gt$issuer_ls180.v:167766$11019 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 6'111011 + connect \Y $gt$issuer_ls180.v:167766$11019_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + cell $gt $gt$issuer_ls180.v:167767$11020 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 6'111100 + connect \Y $gt$issuer_ls180.v:167767$11020_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + cell $gt $gt$issuer_ls180.v:167768$11021 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 6'111101 + connect \Y $gt$issuer_ls180.v:167768$11021_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + cell $gt $gt$issuer_ls180.v:167769$11022 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 6'111110 + connect \Y $gt$issuer_ls180.v:167769$11022_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + cell $gt $gt$issuer_ls180.v:167770$11023 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 6'111111 + connect \Y $gt$issuer_ls180.v:167770$11023_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + cell $gt $gt$issuer_ls180.v:167771$11024 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 3'110 + connect \Y $gt$issuer_ls180.v:167771$11024_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + cell $gt $gt$issuer_ls180.v:167772$11025 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 3'111 + connect \Y $gt$issuer_ls180.v:167772$11025_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + cell $gt $gt$issuer_ls180.v:167773$11026 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 4'1000 + connect \Y $gt$issuer_ls180.v:167773$11026_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + cell $gt $gt$issuer_ls180.v:167774$11027 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 1'0 + connect \Y $gt$issuer_ls180.v:167774$11027_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + cell $gt $gt$issuer_ls180.v:167775$11028 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 4'1001 + connect \Y $gt$issuer_ls180.v:167775$11028_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + cell $gt $gt$issuer_ls180.v:167776$11029 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 4'1010 + connect \Y $gt$issuer_ls180.v:167776$11029_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + cell $gt $gt$issuer_ls180.v:167777$11030 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 4'1011 + connect \Y $gt$issuer_ls180.v:167777$11030_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + cell $gt $gt$issuer_ls180.v:167778$11031 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 4'1100 + connect \Y $gt$issuer_ls180.v:167778$11031_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + cell $gt $gt$issuer_ls180.v:167779$11032 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 4'1101 + connect \Y $gt$issuer_ls180.v:167779$11032_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + cell $gt $gt$issuer_ls180.v:167780$11033 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 4'1110 + connect \Y $gt$issuer_ls180.v:167780$11033_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + cell $gt $gt$issuer_ls180.v:167781$11034 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 4'1111 + connect \Y $gt$issuer_ls180.v:167781$11034_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + cell $gt $gt$issuer_ls180.v:167782$11035 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 5'10000 + connect \Y $gt$issuer_ls180.v:167782$11035_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + cell $gt $gt$issuer_ls180.v:167783$11036 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 5'10001 + connect \Y $gt$issuer_ls180.v:167783$11036_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + cell $gt $gt$issuer_ls180.v:167784$11037 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 5'10010 + connect \Y $gt$issuer_ls180.v:167784$11037_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + cell $gt $gt$issuer_ls180.v:167785$11038 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 1'1 + connect \Y $gt$issuer_ls180.v:167785$11038_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + cell $gt $gt$issuer_ls180.v:167786$11039 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 5'10011 + connect \Y $gt$issuer_ls180.v:167786$11039_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + cell $gt $gt$issuer_ls180.v:167787$11040 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 5'10100 + connect \Y $gt$issuer_ls180.v:167787$11040_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + cell $gt $gt$issuer_ls180.v:167788$11041 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 5'10101 + connect \Y $gt$issuer_ls180.v:167788$11041_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + cell $gt $gt$issuer_ls180.v:167789$11042 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 5'10110 + connect \Y $gt$issuer_ls180.v:167789$11042_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + cell $gt $gt$issuer_ls180.v:167790$11043 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 5'10111 + connect \Y $gt$issuer_ls180.v:167790$11043_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + cell $gt $gt$issuer_ls180.v:167791$11044 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 5'11000 + connect \Y $gt$issuer_ls180.v:167791$11044_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + cell $gt $gt$issuer_ls180.v:167792$11045 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 5'11001 + connect \Y $gt$issuer_ls180.v:167792$11045_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + cell $gt $gt$issuer_ls180.v:167793$11046 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 5'11010 + connect \Y $gt$issuer_ls180.v:167793$11046_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + cell $gt $gt$issuer_ls180.v:167794$11047 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 5'11011 + connect \Y $gt$issuer_ls180.v:167794$11047_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + cell $gt $gt$issuer_ls180.v:167795$11048 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 5'11100 + connect \Y $gt$issuer_ls180.v:167795$11048_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + cell $gt $gt$issuer_ls180.v:167796$11049 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 2'10 + connect \Y $gt$issuer_ls180.v:167796$11049_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + cell $gt $gt$issuer_ls180.v:167797$11050 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 5'11101 + connect \Y $gt$issuer_ls180.v:167797$11050_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + cell $gt $gt$issuer_ls180.v:167798$11051 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 5'11110 + connect \Y $gt$issuer_ls180.v:167798$11051_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + cell $gt $gt$issuer_ls180.v:167799$11052 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 5'11111 + connect \Y $gt$issuer_ls180.v:167799$11052_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + cell $gt $gt$issuer_ls180.v:167800$11053 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 6'100000 + connect \Y $gt$issuer_ls180.v:167800$11053_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + cell $gt $gt$issuer_ls180.v:167801$11054 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 6'100001 + connect \Y $gt$issuer_ls180.v:167801$11054_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + cell $gt $gt$issuer_ls180.v:167802$11055 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 6'100010 + connect \Y $gt$issuer_ls180.v:167802$11055_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + cell $gt $gt$issuer_ls180.v:167803$11056 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 6'100011 + connect \Y $gt$issuer_ls180.v:167803$11056_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + cell $gt $gt$issuer_ls180.v:167804$11057 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 6'100100 + connect \Y $gt$issuer_ls180.v:167804$11057_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + cell $gt $gt$issuer_ls180.v:167805$11058 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 6'100101 + connect \Y $gt$issuer_ls180.v:167805$11058_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + cell $gt $gt$issuer_ls180.v:167806$11059 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 6'100110 + connect \Y $gt$issuer_ls180.v:167806$11059_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + cell $gt $gt$issuer_ls180.v:167807$11060 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 2'11 + connect \Y $gt$issuer_ls180.v:167807$11060_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + cell $gt $gt$issuer_ls180.v:167808$11061 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 6'100111 + connect \Y $gt$issuer_ls180.v:167808$11061_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + cell $gt $gt$issuer_ls180.v:167809$11062 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 6'101000 + connect \Y $gt$issuer_ls180.v:167809$11062_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + cell $gt $gt$issuer_ls180.v:167810$11063 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 6'101001 + connect \Y $gt$issuer_ls180.v:167810$11063_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + cell $gt $gt$issuer_ls180.v:167811$11064 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 6'101010 + connect \Y $gt$issuer_ls180.v:167811$11064_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + cell $gt $gt$issuer_ls180.v:167812$11065 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 6'101011 + connect \Y $gt$issuer_ls180.v:167812$11065_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + cell $gt $gt$issuer_ls180.v:167813$11066 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 6'101100 + connect \Y $gt$issuer_ls180.v:167813$11066_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + cell $gt $gt$issuer_ls180.v:167814$11067 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 6'101101 + connect \Y $gt$issuer_ls180.v:167814$11067_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + cell $gt $gt$issuer_ls180.v:167815$11068 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 6'101110 + connect \Y $gt$issuer_ls180.v:167815$11068_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + cell $gt $gt$issuer_ls180.v:167816$11069 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 6'101111 + connect \Y $gt$issuer_ls180.v:167816$11069_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + cell $gt $gt$issuer_ls180.v:167817$11070 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \shift + connect \B 6'110000 + connect \Y $gt$issuer_ls180.v:167817$11070_Y + end + attribute \src "issuer_ls180.v:167620.7-167620.20" + process $proc$issuer_ls180.v:167620$11072 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "issuer_ls180.v:167818.3-168205.6" + process $proc$issuer_ls180.v:167818$11071 + assign { } { } + assign { } { } + assign $0\mask[63:0] [0] $1\mask[0:0] + assign $0\mask[63:0] [1] $2\mask[1:1] + assign $0\mask[63:0] [2] $3\mask[2:2] + assign $0\mask[63:0] [3] $4\mask[3:3] + assign $0\mask[63:0] [4] $5\mask[4:4] + assign $0\mask[63:0] [5] $6\mask[5:5] + assign $0\mask[63:0] [6] $7\mask[6:6] + assign $0\mask[63:0] [7] $8\mask[7:7] + assign $0\mask[63:0] [8] $9\mask[8:8] + assign $0\mask[63:0] [9] $10\mask[9:9] + assign $0\mask[63:0] [10] $11\mask[10:10] + assign $0\mask[63:0] [11] $12\mask[11:11] + assign $0\mask[63:0] [12] $13\mask[12:12] + assign $0\mask[63:0] [13] $14\mask[13:13] + assign $0\mask[63:0] [14] $15\mask[14:14] + assign $0\mask[63:0] [15] $16\mask[15:15] + assign $0\mask[63:0] [16] $17\mask[16:16] + assign $0\mask[63:0] [17] $18\mask[17:17] + assign $0\mask[63:0] [18] $19\mask[18:18] + assign $0\mask[63:0] [19] $20\mask[19:19] + assign $0\mask[63:0] [20] $21\mask[20:20] + assign $0\mask[63:0] [21] $22\mask[21:21] + assign $0\mask[63:0] [22] $23\mask[22:22] + assign $0\mask[63:0] [23] $24\mask[23:23] + assign $0\mask[63:0] [24] $25\mask[24:24] + assign $0\mask[63:0] [25] $26\mask[25:25] + assign $0\mask[63:0] [26] $27\mask[26:26] + assign $0\mask[63:0] [27] $28\mask[27:27] + assign $0\mask[63:0] [28] $29\mask[28:28] + assign $0\mask[63:0] [29] $30\mask[29:29] + assign $0\mask[63:0] [30] $31\mask[30:30] + assign $0\mask[63:0] [31] $32\mask[31:31] + assign $0\mask[63:0] [32] $33\mask[32:32] + assign $0\mask[63:0] [33] $34\mask[33:33] + assign $0\mask[63:0] [34] $35\mask[34:34] + assign $0\mask[63:0] [35] $36\mask[35:35] + assign $0\mask[63:0] [36] $37\mask[36:36] + assign $0\mask[63:0] [37] $38\mask[37:37] + assign $0\mask[63:0] [38] $39\mask[38:38] + assign $0\mask[63:0] [39] $40\mask[39:39] + assign $0\mask[63:0] [40] $41\mask[40:40] + assign $0\mask[63:0] [41] $42\mask[41:41] + assign $0\mask[63:0] [42] $43\mask[42:42] + assign $0\mask[63:0] [43] $44\mask[43:43] + assign $0\mask[63:0] [44] $45\mask[44:44] + assign $0\mask[63:0] [45] $46\mask[45:45] + assign $0\mask[63:0] [46] $47\mask[46:46] + assign $0\mask[63:0] [47] $48\mask[47:47] + assign $0\mask[63:0] [48] $49\mask[48:48] + assign $0\mask[63:0] [49] $50\mask[49:49] + assign $0\mask[63:0] [50] $51\mask[50:50] + assign $0\mask[63:0] [51] $52\mask[51:51] + assign $0\mask[63:0] [52] $53\mask[52:52] + assign $0\mask[63:0] [53] $54\mask[53:53] + assign $0\mask[63:0] [54] $55\mask[54:54] + assign $0\mask[63:0] [55] $56\mask[55:55] + assign $0\mask[63:0] [56] $57\mask[56:56] + assign $0\mask[63:0] [57] $58\mask[57:57] + assign $0\mask[63:0] [58] $59\mask[58:58] + assign $0\mask[63:0] [59] $60\mask[59:59] + assign $0\mask[63:0] [60] $61\mask[60:60] + assign $0\mask[63:0] [61] $62\mask[61:61] + assign $0\mask[63:0] [62] $63\mask[62:62] + assign $0\mask[63:0] [63] $64\mask[63:63] + attribute \src "issuer_ls180.v:167819.5-167819.29" + switch \initial + attribute \src "issuer_ls180.v:167819.9-167819.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + switch \$1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\mask[0:0] 1'1 + case + assign $1\mask[0:0] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + switch \$3 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\mask[1:1] 1'1 + case + assign $2\mask[1:1] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + switch \$5 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\mask[2:2] 1'1 + case + assign $3\mask[2:2] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + switch \$7 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\mask[3:3] 1'1 + case + assign $4\mask[3:3] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + switch \$9 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\mask[4:4] 1'1 + case + assign $5\mask[4:4] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + switch \$11 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $6\mask[5:5] 1'1 + case + assign $6\mask[5:5] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + switch \$13 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $7\mask[6:6] 1'1 + case + assign $7\mask[6:6] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + switch \$15 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $8\mask[7:7] 1'1 + case + assign $8\mask[7:7] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + switch \$17 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $9\mask[8:8] 1'1 + case + assign $9\mask[8:8] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + switch \$19 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $10\mask[9:9] 1'1 + case + assign $10\mask[9:9] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + switch \$21 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $11\mask[10:10] 1'1 + case + assign $11\mask[10:10] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + switch \$23 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $12\mask[11:11] 1'1 + case + assign $12\mask[11:11] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + switch \$25 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $13\mask[12:12] 1'1 + case + assign $13\mask[12:12] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + switch \$27 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $14\mask[13:13] 1'1 + case + assign $14\mask[13:13] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + switch \$29 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $15\mask[14:14] 1'1 + case + assign $15\mask[14:14] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + switch \$31 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $16\mask[15:15] 1'1 + case + assign $16\mask[15:15] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + switch \$33 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $17\mask[16:16] 1'1 + case + assign $17\mask[16:16] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + switch \$35 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $18\mask[17:17] 1'1 + case + assign $18\mask[17:17] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + switch \$37 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $19\mask[18:18] 1'1 + case + assign $19\mask[18:18] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + switch \$39 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $20\mask[19:19] 1'1 + case + assign $20\mask[19:19] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + switch \$41 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $21\mask[20:20] 1'1 + case + assign $21\mask[20:20] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + switch \$43 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $22\mask[21:21] 1'1 + case + assign $22\mask[21:21] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + switch \$45 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $23\mask[22:22] 1'1 + case + assign $23\mask[22:22] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + switch \$47 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $24\mask[23:23] 1'1 + case + assign $24\mask[23:23] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + switch \$49 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $25\mask[24:24] 1'1 + case + assign $25\mask[24:24] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + switch \$51 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $26\mask[25:25] 1'1 + case + assign $26\mask[25:25] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + switch \$53 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $27\mask[26:26] 1'1 + case + assign $27\mask[26:26] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + switch \$55 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $28\mask[27:27] 1'1 + case + assign $28\mask[27:27] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + switch \$57 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $29\mask[28:28] 1'1 + case + assign $29\mask[28:28] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + switch \$59 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $30\mask[29:29] 1'1 + case + assign $30\mask[29:29] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + switch \$61 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $31\mask[30:30] 1'1 + case + assign $31\mask[30:30] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + switch \$63 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $32\mask[31:31] 1'1 + case + assign $32\mask[31:31] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + switch \$65 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $33\mask[32:32] 1'1 + case + assign $33\mask[32:32] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + switch \$67 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $34\mask[33:33] 1'1 + case + assign $34\mask[33:33] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + switch \$69 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $35\mask[34:34] 1'1 + case + assign $35\mask[34:34] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + switch \$71 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $36\mask[35:35] 1'1 + case + assign $36\mask[35:35] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + switch \$73 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $37\mask[36:36] 1'1 + case + assign $37\mask[36:36] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + switch \$75 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $38\mask[37:37] 1'1 + case + assign $38\mask[37:37] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + switch \$77 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $39\mask[38:38] 1'1 + case + assign $39\mask[38:38] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + switch \$79 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $40\mask[39:39] 1'1 + case + assign $40\mask[39:39] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + switch \$81 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $41\mask[40:40] 1'1 + case + assign $41\mask[40:40] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + switch \$83 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $42\mask[41:41] 1'1 + case + assign $42\mask[41:41] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + switch \$85 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $43\mask[42:42] 1'1 + case + assign $43\mask[42:42] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + switch \$87 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $44\mask[43:43] 1'1 + case + assign $44\mask[43:43] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + switch \$89 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $45\mask[44:44] 1'1 + case + assign $45\mask[44:44] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + switch \$91 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $46\mask[45:45] 1'1 + case + assign $46\mask[45:45] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + switch \$93 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $47\mask[46:46] 1'1 + case + assign $47\mask[46:46] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + switch \$95 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $48\mask[47:47] 1'1 + case + assign $48\mask[47:47] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + switch \$97 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $49\mask[48:48] 1'1 + case + assign $49\mask[48:48] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + switch \$99 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $50\mask[49:49] 1'1 + case + assign $50\mask[49:49] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + switch \$101 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $51\mask[50:50] 1'1 + case + assign $51\mask[50:50] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + switch \$103 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $52\mask[51:51] 1'1 + case + assign $52\mask[51:51] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + switch \$105 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $53\mask[52:52] 1'1 + case + assign $53\mask[52:52] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + switch \$107 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $54\mask[53:53] 1'1 + case + assign $54\mask[53:53] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + switch \$109 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $55\mask[54:54] 1'1 + case + assign $55\mask[54:54] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + switch \$111 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $56\mask[55:55] 1'1 + case + assign $56\mask[55:55] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + switch \$113 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $57\mask[56:56] 1'1 + case + assign $57\mask[56:56] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + switch \$115 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $58\mask[57:57] 1'1 + case + assign $58\mask[57:57] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + switch \$117 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $59\mask[58:58] 1'1 + case + assign $59\mask[58:58] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + switch \$119 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $60\mask[59:59] 1'1 + case + assign $60\mask[59:59] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + switch \$121 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $61\mask[60:60] 1'1 + case + assign $61\mask[60:60] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + switch \$123 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $62\mask[61:61] 1'1 + case + assign $62\mask[61:61] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + switch \$125 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $63\mask[62:62] 1'1 + case + assign $63\mask[62:62] 1'0 + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:18" + switch \$127 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $64\mask[63:63] 1'1 + case + assign $64\mask[63:63] 1'0 + end + sync always + update \mask $0\mask[63:0] + end + connect \$9 $gt$issuer_ls180.v:167754$11007_Y + connect \$99 $gt$issuer_ls180.v:167755$11008_Y + connect \$101 $gt$issuer_ls180.v:167756$11009_Y + connect \$103 $gt$issuer_ls180.v:167757$11010_Y + connect \$105 $gt$issuer_ls180.v:167758$11011_Y + connect \$107 $gt$issuer_ls180.v:167759$11012_Y + connect \$109 $gt$issuer_ls180.v:167760$11013_Y + connect \$111 $gt$issuer_ls180.v:167761$11014_Y + connect \$113 $gt$issuer_ls180.v:167762$11015_Y + connect \$115 $gt$issuer_ls180.v:167763$11016_Y + connect \$117 $gt$issuer_ls180.v:167764$11017_Y + connect \$11 $gt$issuer_ls180.v:167765$11018_Y + connect \$119 $gt$issuer_ls180.v:167766$11019_Y + connect \$121 $gt$issuer_ls180.v:167767$11020_Y + connect \$123 $gt$issuer_ls180.v:167768$11021_Y + connect \$125 $gt$issuer_ls180.v:167769$11022_Y + connect \$127 $gt$issuer_ls180.v:167770$11023_Y + connect \$13 $gt$issuer_ls180.v:167771$11024_Y + connect \$15 $gt$issuer_ls180.v:167772$11025_Y + connect \$17 $gt$issuer_ls180.v:167773$11026_Y + connect \$1 $gt$issuer_ls180.v:167774$11027_Y + connect \$19 $gt$issuer_ls180.v:167775$11028_Y + connect \$21 $gt$issuer_ls180.v:167776$11029_Y + connect \$23 $gt$issuer_ls180.v:167777$11030_Y + connect \$25 $gt$issuer_ls180.v:167778$11031_Y + connect \$27 $gt$issuer_ls180.v:167779$11032_Y + connect \$29 $gt$issuer_ls180.v:167780$11033_Y + connect \$31 $gt$issuer_ls180.v:167781$11034_Y + connect \$33 $gt$issuer_ls180.v:167782$11035_Y + connect \$35 $gt$issuer_ls180.v:167783$11036_Y + connect \$37 $gt$issuer_ls180.v:167784$11037_Y + connect \$3 $gt$issuer_ls180.v:167785$11038_Y + connect \$39 $gt$issuer_ls180.v:167786$11039_Y + connect \$41 $gt$issuer_ls180.v:167787$11040_Y + connect \$43 $gt$issuer_ls180.v:167788$11041_Y + connect \$45 $gt$issuer_ls180.v:167789$11042_Y + connect \$47 $gt$issuer_ls180.v:167790$11043_Y + connect \$49 $gt$issuer_ls180.v:167791$11044_Y + connect \$51 $gt$issuer_ls180.v:167792$11045_Y + connect \$53 $gt$issuer_ls180.v:167793$11046_Y + connect \$55 $gt$issuer_ls180.v:167794$11047_Y + connect \$57 $gt$issuer_ls180.v:167795$11048_Y + connect \$5 $gt$issuer_ls180.v:167796$11049_Y + connect \$59 $gt$issuer_ls180.v:167797$11050_Y + connect \$61 $gt$issuer_ls180.v:167798$11051_Y + connect \$63 $gt$issuer_ls180.v:167799$11052_Y + connect \$65 $gt$issuer_ls180.v:167800$11053_Y + connect \$67 $gt$issuer_ls180.v:167801$11054_Y + connect \$69 $gt$issuer_ls180.v:167802$11055_Y + connect \$71 $gt$issuer_ls180.v:167803$11056_Y + connect \$73 $gt$issuer_ls180.v:167804$11057_Y + connect \$75 $gt$issuer_ls180.v:167805$11058_Y + connect \$77 $gt$issuer_ls180.v:167806$11059_Y + connect \$7 $gt$issuer_ls180.v:167807$11060_Y + connect \$79 $gt$issuer_ls180.v:167808$11061_Y + connect \$81 $gt$issuer_ls180.v:167809$11062_Y + connect \$83 $gt$issuer_ls180.v:167810$11063_Y + connect \$85 $gt$issuer_ls180.v:167811$11064_Y + connect \$87 $gt$issuer_ls180.v:167812$11065_Y + connect \$89 $gt$issuer_ls180.v:167813$11066_Y + connect \$91 $gt$issuer_ls180.v:167814$11067_Y + connect \$93 $gt$issuer_ls180.v:167815$11068_Y + connect \$95 $gt$issuer_ls180.v:167816$11069_Y + connect \$97 $gt$issuer_ls180.v:167817$11070_Y +end +attribute \src "issuer_ls180.v:168210.1-168268.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.fus.alu0.rok_l" +attribute \generator "nMigen" +module \rok_l + attribute \src "issuer_ls180.v:168211.7-168211.20" + wire $0\initial[0:0] + attribute \src "issuer_ls180.v:168256.3-168264.6" + wire $0\q_int$next[0:0]$11083 + attribute \src "issuer_ls180.v:168254.3-168255.27" + wire $0\q_int[0:0] + attribute \src "issuer_ls180.v:168256.3-168264.6" + wire $1\q_int$next[0:0]$11084 + attribute \src "issuer_ls180.v:168233.7-168233.19" + wire $1\q_int[0:0] + attribute \src "issuer_ls180.v:168246.17-168246.96" + wire $and$issuer_ls180.v:168246$11073_Y + attribute \src "issuer_ls180.v:168251.17-168251.96" + wire $and$issuer_ls180.v:168251$11078_Y + attribute \src "issuer_ls180.v:168248.18-168248.94" + wire $not$issuer_ls180.v:168248$11075_Y + attribute \src "issuer_ls180.v:168250.17-168250.93" + wire $not$issuer_ls180.v:168250$11077_Y + attribute \src "issuer_ls180.v:168253.17-168253.93" + wire $not$issuer_ls180.v:168253$11080_Y + attribute \src "issuer_ls180.v:168247.18-168247.99" + wire $or$issuer_ls180.v:168247$11074_Y + attribute \src "issuer_ls180.v:168249.18-168249.100" + wire $or$issuer_ls180.v:168249$11076_Y + attribute \src "issuer_ls180.v:168252.17-168252.98" + wire $or$issuer_ls180.v:168252$11079_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire \$13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" + wire input 5 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" + wire input 1 \coresync_rst + attribute \src "issuer_ls180.v:168211.7-168211.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire output 2 \q_rdok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" + wire \qlq_rdok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + wire \qn_rdok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire input 4 \r_rdok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire input 3 \s_rdok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $and $and$issuer_ls180.v:168246$11073 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$7 + connect \Y $and$issuer_ls180.v:168246$11073_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $and $and$issuer_ls180.v:168251$11078 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$1 + connect \Y $and$issuer_ls180.v:168251$11078_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + cell $not $not$issuer_ls180.v:168248$11075 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_rdok + connect \Y $not$issuer_ls180.v:168248$11075_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $not $not$issuer_ls180.v:168250$11077 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_rdok + connect \Y $not$issuer_ls180.v:168250$11077_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $not $not$issuer_ls180.v:168253$11080 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_rdok + connect \Y $not$issuer_ls180.v:168253$11080_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $or $or$issuer_ls180.v:168247$11074 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$9 + connect \B \s_rdok + connect \Y $or$issuer_ls180.v:168247$11074_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + cell $or $or$issuer_ls180.v:168249$11076 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_rdok + connect \B \q_int + connect \Y $or$issuer_ls180.v:168249$11076_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $or $or$issuer_ls180.v:168252$11079 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$3 + connect \B \s_rdok + connect \Y $or$issuer_ls180.v:168252$11079_Y + end + attribute \src "issuer_ls180.v:168211.7-168211.20" + process $proc$issuer_ls180.v:168211$11085 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "issuer_ls180.v:168233.7-168233.19" + process $proc$issuer_ls180.v:168233$11086 + assign { } { } + assign $1\q_int[0:0] 1'0 + sync always + sync init + update \q_int $1\q_int[0:0] + end + attribute \src "issuer_ls180.v:168254.3-168255.27" + process $proc$issuer_ls180.v:168254$11081 + assign { } { } + assign $0\q_int[0:0] \q_int$next + sync posedge \coresync_clk + update \q_int $0\q_int[0:0] + end + attribute \src "issuer_ls180.v:168256.3-168264.6" + process $proc$issuer_ls180.v:168256$11082 + assign { } { } + assign { } { } + assign $0\q_int$next[0:0]$11083 $1\q_int$next[0:0]$11084 + attribute \src "issuer_ls180.v:168257.5-168257.29" + switch \initial + attribute \src "issuer_ls180.v:168257.9-168257.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\q_int$next[0:0]$11084 1'0 + case + assign $1\q_int$next[0:0]$11084 \$5 + end + sync always + update \q_int$next $0\q_int$next[0:0]$11083 + end + connect \$9 $and$issuer_ls180.v:168246$11073_Y + connect \$11 $or$issuer_ls180.v:168247$11074_Y + connect \$13 $not$issuer_ls180.v:168248$11075_Y + connect \$15 $or$issuer_ls180.v:168249$11076_Y + connect \$1 $not$issuer_ls180.v:168250$11077_Y + connect \$3 $and$issuer_ls180.v:168251$11078_Y + connect \$5 $or$issuer_ls180.v:168252$11079_Y + connect \$7 $not$issuer_ls180.v:168253$11080_Y + connect \qlq_rdok \$15 + connect \qn_rdok \$13 + connect \q_rdok \$11 +end +attribute \src "issuer_ls180.v:168272.1-168330.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.fus.mul0.rok_l" +attribute \generator "nMigen" +module \rok_l$102 + attribute \src "issuer_ls180.v:168273.7-168273.20" + wire $0\initial[0:0] + attribute \src "issuer_ls180.v:168318.3-168326.6" + wire $0\q_int$next[0:0]$11097 + attribute \src "issuer_ls180.v:168316.3-168317.27" + wire $0\q_int[0:0] + attribute \src "issuer_ls180.v:168318.3-168326.6" + wire $1\q_int$next[0:0]$11098 + attribute \src "issuer_ls180.v:168295.7-168295.19" + wire $1\q_int[0:0] + attribute \src "issuer_ls180.v:168308.17-168308.96" + wire $and$issuer_ls180.v:168308$11087_Y + attribute \src "issuer_ls180.v:168313.17-168313.96" + wire $and$issuer_ls180.v:168313$11092_Y + attribute \src "issuer_ls180.v:168310.18-168310.94" + wire $not$issuer_ls180.v:168310$11089_Y + attribute \src "issuer_ls180.v:168312.17-168312.93" + wire $not$issuer_ls180.v:168312$11091_Y + attribute \src "issuer_ls180.v:168315.17-168315.93" + wire $not$issuer_ls180.v:168315$11094_Y + attribute \src "issuer_ls180.v:168309.18-168309.99" + wire $or$issuer_ls180.v:168309$11088_Y + attribute \src "issuer_ls180.v:168311.18-168311.100" + wire $or$issuer_ls180.v:168311$11090_Y + attribute \src "issuer_ls180.v:168314.17-168314.98" + wire $or$issuer_ls180.v:168314$11093_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire \$13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" + wire input 5 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" + wire input 1 \coresync_rst + attribute \src "issuer_ls180.v:168273.7-168273.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire output 2 \q_rdok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" + wire \qlq_rdok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + wire \qn_rdok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire input 4 \r_rdok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire input 3 \s_rdok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $and $and$issuer_ls180.v:168308$11087 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$7 + connect \Y $and$issuer_ls180.v:168308$11087_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $and $and$issuer_ls180.v:168313$11092 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$1 + connect \Y $and$issuer_ls180.v:168313$11092_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + cell $not $not$issuer_ls180.v:168310$11089 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_rdok + connect \Y $not$issuer_ls180.v:168310$11089_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $not $not$issuer_ls180.v:168312$11091 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_rdok + connect \Y $not$issuer_ls180.v:168312$11091_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $not $not$issuer_ls180.v:168315$11094 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_rdok + connect \Y $not$issuer_ls180.v:168315$11094_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $or $or$issuer_ls180.v:168309$11088 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$9 + connect \B \s_rdok + connect \Y $or$issuer_ls180.v:168309$11088_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + cell $or $or$issuer_ls180.v:168311$11090 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_rdok + connect \B \q_int + connect \Y $or$issuer_ls180.v:168311$11090_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $or $or$issuer_ls180.v:168314$11093 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$3 + connect \B \s_rdok + connect \Y $or$issuer_ls180.v:168314$11093_Y + end + attribute \src "issuer_ls180.v:168273.7-168273.20" + process $proc$issuer_ls180.v:168273$11099 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "issuer_ls180.v:168295.7-168295.19" + process $proc$issuer_ls180.v:168295$11100 + assign { } { } + assign $1\q_int[0:0] 1'0 + sync always + sync init + update \q_int $1\q_int[0:0] + end + attribute \src "issuer_ls180.v:168316.3-168317.27" + process $proc$issuer_ls180.v:168316$11095 + assign { } { } + assign $0\q_int[0:0] \q_int$next + sync posedge \coresync_clk + update \q_int $0\q_int[0:0] + end + attribute \src "issuer_ls180.v:168318.3-168326.6" + process $proc$issuer_ls180.v:168318$11096 + assign { } { } + assign { } { } + assign $0\q_int$next[0:0]$11097 $1\q_int$next[0:0]$11098 + attribute \src "issuer_ls180.v:168319.5-168319.29" + switch \initial + attribute \src "issuer_ls180.v:168319.9-168319.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\q_int$next[0:0]$11098 1'0 + case + assign $1\q_int$next[0:0]$11098 \$5 + end + sync always + update \q_int$next $0\q_int$next[0:0]$11097 + end + connect \$9 $and$issuer_ls180.v:168308$11087_Y + connect \$11 $or$issuer_ls180.v:168309$11088_Y + connect \$13 $not$issuer_ls180.v:168310$11089_Y + connect \$15 $or$issuer_ls180.v:168311$11090_Y + connect \$1 $not$issuer_ls180.v:168312$11091_Y + connect \$3 $and$issuer_ls180.v:168313$11092_Y + connect \$5 $or$issuer_ls180.v:168314$11093_Y + connect \$7 $not$issuer_ls180.v:168315$11094_Y + connect \qlq_rdok \$15 + connect \qn_rdok \$13 + connect \q_rdok \$11 +end +attribute \src "issuer_ls180.v:168334.1-168392.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.fus.shiftrot0.rok_l" +attribute \generator "nMigen" +module \rok_l$120 + attribute \src "issuer_ls180.v:168335.7-168335.20" + wire $0\initial[0:0] + attribute \src "issuer_ls180.v:168380.3-168388.6" + wire $0\q_int$next[0:0]$11111 + attribute \src "issuer_ls180.v:168378.3-168379.27" + wire $0\q_int[0:0] + attribute \src "issuer_ls180.v:168380.3-168388.6" + wire $1\q_int$next[0:0]$11112 + attribute \src "issuer_ls180.v:168357.7-168357.19" + wire $1\q_int[0:0] + attribute \src "issuer_ls180.v:168370.17-168370.96" + wire $and$issuer_ls180.v:168370$11101_Y + attribute \src "issuer_ls180.v:168375.17-168375.96" + wire $and$issuer_ls180.v:168375$11106_Y + attribute \src "issuer_ls180.v:168372.18-168372.94" + wire $not$issuer_ls180.v:168372$11103_Y + attribute \src "issuer_ls180.v:168374.17-168374.93" + wire $not$issuer_ls180.v:168374$11105_Y + attribute \src "issuer_ls180.v:168377.17-168377.93" + wire $not$issuer_ls180.v:168377$11108_Y + attribute \src "issuer_ls180.v:168371.18-168371.99" + wire $or$issuer_ls180.v:168371$11102_Y + attribute \src "issuer_ls180.v:168373.18-168373.100" + wire $or$issuer_ls180.v:168373$11104_Y + attribute \src "issuer_ls180.v:168376.17-168376.98" + wire $or$issuer_ls180.v:168376$11107_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire \$13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" + wire input 5 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" + wire input 1 \coresync_rst + attribute \src "issuer_ls180.v:168335.7-168335.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire output 2 \q_rdok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" + wire \qlq_rdok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + wire \qn_rdok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire input 4 \r_rdok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire input 3 \s_rdok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $and $and$issuer_ls180.v:168370$11101 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$7 + connect \Y $and$issuer_ls180.v:168370$11101_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $and $and$issuer_ls180.v:168375$11106 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$1 + connect \Y $and$issuer_ls180.v:168375$11106_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + cell $not $not$issuer_ls180.v:168372$11103 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_rdok + connect \Y $not$issuer_ls180.v:168372$11103_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $not $not$issuer_ls180.v:168374$11105 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_rdok + connect \Y $not$issuer_ls180.v:168374$11105_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $not $not$issuer_ls180.v:168377$11108 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_rdok + connect \Y $not$issuer_ls180.v:168377$11108_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $or $or$issuer_ls180.v:168371$11102 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$9 + connect \B \s_rdok + connect \Y $or$issuer_ls180.v:168371$11102_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + cell $or $or$issuer_ls180.v:168373$11104 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_rdok + connect \B \q_int + connect \Y $or$issuer_ls180.v:168373$11104_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $or $or$issuer_ls180.v:168376$11107 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$3 + connect \B \s_rdok + connect \Y $or$issuer_ls180.v:168376$11107_Y + end + attribute \src "issuer_ls180.v:168335.7-168335.20" + process $proc$issuer_ls180.v:168335$11113 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "issuer_ls180.v:168357.7-168357.19" + process $proc$issuer_ls180.v:168357$11114 + assign { } { } + assign $1\q_int[0:0] 1'0 + sync always + sync init + update \q_int $1\q_int[0:0] + end + attribute \src "issuer_ls180.v:168378.3-168379.27" + process $proc$issuer_ls180.v:168378$11109 + assign { } { } + assign $0\q_int[0:0] \q_int$next + sync posedge \coresync_clk + update \q_int $0\q_int[0:0] + end + attribute \src "issuer_ls180.v:168380.3-168388.6" + process $proc$issuer_ls180.v:168380$11110 + assign { } { } + assign { } { } + assign $0\q_int$next[0:0]$11111 $1\q_int$next[0:0]$11112 + attribute \src "issuer_ls180.v:168381.5-168381.29" + switch \initial + attribute \src "issuer_ls180.v:168381.9-168381.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\q_int$next[0:0]$11112 1'0 + case + assign $1\q_int$next[0:0]$11112 \$5 + end + sync always + update \q_int$next $0\q_int$next[0:0]$11111 + end + connect \$9 $and$issuer_ls180.v:168370$11101_Y + connect \$11 $or$issuer_ls180.v:168371$11102_Y + connect \$13 $not$issuer_ls180.v:168372$11103_Y + connect \$15 $or$issuer_ls180.v:168373$11104_Y + connect \$1 $not$issuer_ls180.v:168374$11105_Y + connect \$3 $and$issuer_ls180.v:168375$11106_Y + connect \$5 $or$issuer_ls180.v:168376$11107_Y + connect \$7 $not$issuer_ls180.v:168377$11108_Y + connect \qlq_rdok \$15 + connect \qn_rdok \$13 + connect \q_rdok \$11 +end +attribute \src "issuer_ls180.v:168396.1-168454.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.fus.cr0.rok_l" +attribute \generator "nMigen" +module \rok_l$14 + attribute \src "issuer_ls180.v:168397.7-168397.20" + wire $0\initial[0:0] + attribute \src "issuer_ls180.v:168442.3-168450.6" + wire $0\q_int$next[0:0]$11125 + attribute \src "issuer_ls180.v:168440.3-168441.27" + wire $0\q_int[0:0] + attribute \src "issuer_ls180.v:168442.3-168450.6" + wire $1\q_int$next[0:0]$11126 + attribute \src "issuer_ls180.v:168419.7-168419.19" + wire $1\q_int[0:0] + attribute \src "issuer_ls180.v:168432.17-168432.96" + wire $and$issuer_ls180.v:168432$11115_Y + attribute \src "issuer_ls180.v:168437.17-168437.96" + wire $and$issuer_ls180.v:168437$11120_Y + attribute \src "issuer_ls180.v:168434.18-168434.94" + wire $not$issuer_ls180.v:168434$11117_Y + attribute \src "issuer_ls180.v:168436.17-168436.93" + wire $not$issuer_ls180.v:168436$11119_Y + attribute \src "issuer_ls180.v:168439.17-168439.93" + wire $not$issuer_ls180.v:168439$11122_Y + attribute \src "issuer_ls180.v:168433.18-168433.99" + wire $or$issuer_ls180.v:168433$11116_Y + attribute \src "issuer_ls180.v:168435.18-168435.100" + wire $or$issuer_ls180.v:168435$11118_Y + attribute \src "issuer_ls180.v:168438.17-168438.98" + wire $or$issuer_ls180.v:168438$11121_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire \$13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" + wire input 5 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" + wire input 1 \coresync_rst + attribute \src "issuer_ls180.v:168397.7-168397.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire output 2 \q_rdok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" + wire \qlq_rdok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + wire \qn_rdok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire input 4 \r_rdok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire input 3 \s_rdok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $and $and$issuer_ls180.v:168432$11115 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$7 + connect \Y $and$issuer_ls180.v:168432$11115_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $and $and$issuer_ls180.v:168437$11120 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$1 + connect \Y $and$issuer_ls180.v:168437$11120_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + cell $not $not$issuer_ls180.v:168434$11117 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_rdok + connect \Y $not$issuer_ls180.v:168434$11117_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $not $not$issuer_ls180.v:168436$11119 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_rdok + connect \Y $not$issuer_ls180.v:168436$11119_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $not $not$issuer_ls180.v:168439$11122 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_rdok + connect \Y $not$issuer_ls180.v:168439$11122_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $or $or$issuer_ls180.v:168433$11116 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$9 + connect \B \s_rdok + connect \Y $or$issuer_ls180.v:168433$11116_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + cell $or $or$issuer_ls180.v:168435$11118 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_rdok + connect \B \q_int + connect \Y $or$issuer_ls180.v:168435$11118_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $or $or$issuer_ls180.v:168438$11121 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$3 + connect \B \s_rdok + connect \Y $or$issuer_ls180.v:168438$11121_Y + end + attribute \src "issuer_ls180.v:168397.7-168397.20" + process $proc$issuer_ls180.v:168397$11127 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "issuer_ls180.v:168419.7-168419.19" + process $proc$issuer_ls180.v:168419$11128 + assign { } { } + assign $1\q_int[0:0] 1'0 + sync always + sync init + update \q_int $1\q_int[0:0] + end + attribute \src "issuer_ls180.v:168440.3-168441.27" + process $proc$issuer_ls180.v:168440$11123 + assign { } { } + assign $0\q_int[0:0] \q_int$next + sync posedge \coresync_clk + update \q_int $0\q_int[0:0] + end + attribute \src "issuer_ls180.v:168442.3-168450.6" + process $proc$issuer_ls180.v:168442$11124 + assign { } { } + assign { } { } + assign $0\q_int$next[0:0]$11125 $1\q_int$next[0:0]$11126 + attribute \src "issuer_ls180.v:168443.5-168443.29" + switch \initial + attribute \src "issuer_ls180.v:168443.9-168443.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\q_int$next[0:0]$11126 1'0 + case + assign $1\q_int$next[0:0]$11126 \$5 + end + sync always + update \q_int$next $0\q_int$next[0:0]$11125 + end + connect \$9 $and$issuer_ls180.v:168432$11115_Y + connect \$11 $or$issuer_ls180.v:168433$11116_Y + connect \$13 $not$issuer_ls180.v:168434$11117_Y + connect \$15 $or$issuer_ls180.v:168435$11118_Y + connect \$1 $not$issuer_ls180.v:168436$11119_Y + connect \$3 $and$issuer_ls180.v:168437$11120_Y + connect \$5 $or$issuer_ls180.v:168438$11121_Y + connect \$7 $not$issuer_ls180.v:168439$11122_Y + connect \qlq_rdok \$15 + connect \qn_rdok \$13 + connect \q_rdok \$11 +end +attribute \src "issuer_ls180.v:168458.1-168516.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.fus.branch0.rok_l" +attribute \generator "nMigen" +module \rok_l$27 + attribute \src "issuer_ls180.v:168459.7-168459.20" + wire $0\initial[0:0] + attribute \src "issuer_ls180.v:168504.3-168512.6" + wire $0\q_int$next[0:0]$11139 + attribute \src "issuer_ls180.v:168502.3-168503.27" + wire $0\q_int[0:0] + attribute \src "issuer_ls180.v:168504.3-168512.6" + wire $1\q_int$next[0:0]$11140 + attribute \src "issuer_ls180.v:168481.7-168481.19" + wire $1\q_int[0:0] + attribute \src "issuer_ls180.v:168494.17-168494.96" + wire $and$issuer_ls180.v:168494$11129_Y + attribute \src "issuer_ls180.v:168499.17-168499.96" + wire $and$issuer_ls180.v:168499$11134_Y + attribute \src "issuer_ls180.v:168496.18-168496.94" + wire $not$issuer_ls180.v:168496$11131_Y + attribute \src "issuer_ls180.v:168498.17-168498.93" + wire $not$issuer_ls180.v:168498$11133_Y + attribute \src "issuer_ls180.v:168501.17-168501.93" + wire $not$issuer_ls180.v:168501$11136_Y + attribute \src "issuer_ls180.v:168495.18-168495.99" + wire $or$issuer_ls180.v:168495$11130_Y + attribute \src "issuer_ls180.v:168497.18-168497.100" + wire $or$issuer_ls180.v:168497$11132_Y + attribute \src "issuer_ls180.v:168500.17-168500.98" + wire $or$issuer_ls180.v:168500$11135_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire \$13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" + wire input 5 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" + wire input 1 \coresync_rst + attribute \src "issuer_ls180.v:168459.7-168459.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire output 2 \q_rdok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" + wire \qlq_rdok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + wire \qn_rdok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire input 4 \r_rdok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire input 3 \s_rdok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $and $and$issuer_ls180.v:168494$11129 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$7 + connect \Y $and$issuer_ls180.v:168494$11129_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $and $and$issuer_ls180.v:168499$11134 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$1 + connect \Y $and$issuer_ls180.v:168499$11134_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + cell $not $not$issuer_ls180.v:168496$11131 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_rdok + connect \Y $not$issuer_ls180.v:168496$11131_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $not $not$issuer_ls180.v:168498$11133 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_rdok + connect \Y $not$issuer_ls180.v:168498$11133_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $not $not$issuer_ls180.v:168501$11136 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_rdok + connect \Y $not$issuer_ls180.v:168501$11136_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $or $or$issuer_ls180.v:168495$11130 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$9 + connect \B \s_rdok + connect \Y $or$issuer_ls180.v:168495$11130_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + cell $or $or$issuer_ls180.v:168497$11132 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_rdok + connect \B \q_int + connect \Y $or$issuer_ls180.v:168497$11132_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $or $or$issuer_ls180.v:168500$11135 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$3 + connect \B \s_rdok + connect \Y $or$issuer_ls180.v:168500$11135_Y + end + attribute \src "issuer_ls180.v:168459.7-168459.20" + process $proc$issuer_ls180.v:168459$11141 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "issuer_ls180.v:168481.7-168481.19" + process $proc$issuer_ls180.v:168481$11142 + assign { } { } + assign $1\q_int[0:0] 1'0 + sync always + sync init + update \q_int $1\q_int[0:0] + end + attribute \src "issuer_ls180.v:168502.3-168503.27" + process $proc$issuer_ls180.v:168502$11137 + assign { } { } + assign $0\q_int[0:0] \q_int$next + sync posedge \coresync_clk + update \q_int $0\q_int[0:0] + end + attribute \src "issuer_ls180.v:168504.3-168512.6" + process $proc$issuer_ls180.v:168504$11138 + assign { } { } + assign { } { } + assign $0\q_int$next[0:0]$11139 $1\q_int$next[0:0]$11140 + attribute \src "issuer_ls180.v:168505.5-168505.29" + switch \initial + attribute \src "issuer_ls180.v:168505.9-168505.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\q_int$next[0:0]$11140 1'0 + case + assign $1\q_int$next[0:0]$11140 \$5 + end + sync always + update \q_int$next $0\q_int$next[0:0]$11139 + end + connect \$9 $and$issuer_ls180.v:168494$11129_Y + connect \$11 $or$issuer_ls180.v:168495$11130_Y + connect \$13 $not$issuer_ls180.v:168496$11131_Y + connect \$15 $or$issuer_ls180.v:168497$11132_Y + connect \$1 $not$issuer_ls180.v:168498$11133_Y + connect \$3 $and$issuer_ls180.v:168499$11134_Y + connect \$5 $or$issuer_ls180.v:168500$11135_Y + connect \$7 $not$issuer_ls180.v:168501$11136_Y + connect \qlq_rdok \$15 + connect \qn_rdok \$13 + connect \q_rdok \$11 +end +attribute \src "issuer_ls180.v:168520.1-168578.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.fus.trap0.rok_l" +attribute \generator "nMigen" +module \rok_l$40 + attribute \src "issuer_ls180.v:168521.7-168521.20" + wire $0\initial[0:0] + attribute \src "issuer_ls180.v:168566.3-168574.6" + wire $0\q_int$next[0:0]$11153 + attribute \src "issuer_ls180.v:168564.3-168565.27" + wire $0\q_int[0:0] + attribute \src "issuer_ls180.v:168566.3-168574.6" + wire $1\q_int$next[0:0]$11154 + attribute \src "issuer_ls180.v:168543.7-168543.19" + wire $1\q_int[0:0] + attribute \src "issuer_ls180.v:168556.17-168556.96" + wire $and$issuer_ls180.v:168556$11143_Y + attribute \src "issuer_ls180.v:168561.17-168561.96" + wire $and$issuer_ls180.v:168561$11148_Y + attribute \src "issuer_ls180.v:168558.18-168558.94" + wire $not$issuer_ls180.v:168558$11145_Y + attribute \src "issuer_ls180.v:168560.17-168560.93" + wire $not$issuer_ls180.v:168560$11147_Y + attribute \src "issuer_ls180.v:168563.17-168563.93" + wire $not$issuer_ls180.v:168563$11150_Y + attribute \src "issuer_ls180.v:168557.18-168557.99" + wire $or$issuer_ls180.v:168557$11144_Y + attribute \src "issuer_ls180.v:168559.18-168559.100" + wire $or$issuer_ls180.v:168559$11146_Y + attribute \src "issuer_ls180.v:168562.17-168562.98" + wire $or$issuer_ls180.v:168562$11149_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire \$13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" + wire input 5 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" + wire input 1 \coresync_rst + attribute \src "issuer_ls180.v:168521.7-168521.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire output 2 \q_rdok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" + wire \qlq_rdok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + wire \qn_rdok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire input 4 \r_rdok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire input 3 \s_rdok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $and $and$issuer_ls180.v:168556$11143 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$7 + connect \Y $and$issuer_ls180.v:168556$11143_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $and $and$issuer_ls180.v:168561$11148 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$1 + connect \Y $and$issuer_ls180.v:168561$11148_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + cell $not $not$issuer_ls180.v:168558$11145 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_rdok + connect \Y $not$issuer_ls180.v:168558$11145_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $not $not$issuer_ls180.v:168560$11147 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_rdok + connect \Y $not$issuer_ls180.v:168560$11147_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $not $not$issuer_ls180.v:168563$11150 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_rdok + connect \Y $not$issuer_ls180.v:168563$11150_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $or $or$issuer_ls180.v:168557$11144 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$9 + connect \B \s_rdok + connect \Y $or$issuer_ls180.v:168557$11144_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + cell $or $or$issuer_ls180.v:168559$11146 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_rdok + connect \B \q_int + connect \Y $or$issuer_ls180.v:168559$11146_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $or $or$issuer_ls180.v:168562$11149 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$3 + connect \B \s_rdok + connect \Y $or$issuer_ls180.v:168562$11149_Y + end + attribute \src "issuer_ls180.v:168521.7-168521.20" + process $proc$issuer_ls180.v:168521$11155 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "issuer_ls180.v:168543.7-168543.19" + process $proc$issuer_ls180.v:168543$11156 + assign { } { } + assign $1\q_int[0:0] 1'0 + sync always + sync init + update \q_int $1\q_int[0:0] + end + attribute \src "issuer_ls180.v:168564.3-168565.27" + process $proc$issuer_ls180.v:168564$11151 + assign { } { } + assign $0\q_int[0:0] \q_int$next + sync posedge \coresync_clk + update \q_int $0\q_int[0:0] + end + attribute \src "issuer_ls180.v:168566.3-168574.6" + process $proc$issuer_ls180.v:168566$11152 + assign { } { } + assign { } { } + assign $0\q_int$next[0:0]$11153 $1\q_int$next[0:0]$11154 + attribute \src "issuer_ls180.v:168567.5-168567.29" + switch \initial + attribute \src "issuer_ls180.v:168567.9-168567.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\q_int$next[0:0]$11154 1'0 + case + assign $1\q_int$next[0:0]$11154 \$5 + end + sync always + update \q_int$next $0\q_int$next[0:0]$11153 + end + connect \$9 $and$issuer_ls180.v:168556$11143_Y + connect \$11 $or$issuer_ls180.v:168557$11144_Y + connect \$13 $not$issuer_ls180.v:168558$11145_Y + connect \$15 $or$issuer_ls180.v:168559$11146_Y + connect \$1 $not$issuer_ls180.v:168560$11147_Y + connect \$3 $and$issuer_ls180.v:168561$11148_Y + connect \$5 $or$issuer_ls180.v:168562$11149_Y + connect \$7 $not$issuer_ls180.v:168563$11150_Y + connect \qlq_rdok \$15 + connect \qn_rdok \$13 + connect \q_rdok \$11 +end +attribute \src "issuer_ls180.v:168582.1-168640.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.fus.logical0.rok_l" +attribute \generator "nMigen" +module \rok_l$56 + attribute \src "issuer_ls180.v:168583.7-168583.20" + wire $0\initial[0:0] + attribute \src "issuer_ls180.v:168628.3-168636.6" + wire $0\q_int$next[0:0]$11167 + attribute \src "issuer_ls180.v:168626.3-168627.27" + wire $0\q_int[0:0] + attribute \src "issuer_ls180.v:168628.3-168636.6" + wire $1\q_int$next[0:0]$11168 + attribute \src "issuer_ls180.v:168605.7-168605.19" + wire $1\q_int[0:0] + attribute \src "issuer_ls180.v:168618.17-168618.96" + wire $and$issuer_ls180.v:168618$11157_Y + attribute \src "issuer_ls180.v:168623.17-168623.96" + wire $and$issuer_ls180.v:168623$11162_Y + attribute \src "issuer_ls180.v:168620.18-168620.94" + wire $not$issuer_ls180.v:168620$11159_Y + attribute \src "issuer_ls180.v:168622.17-168622.93" + wire $not$issuer_ls180.v:168622$11161_Y + attribute \src "issuer_ls180.v:168625.17-168625.93" + wire $not$issuer_ls180.v:168625$11164_Y + attribute \src "issuer_ls180.v:168619.18-168619.99" + wire $or$issuer_ls180.v:168619$11158_Y + attribute \src "issuer_ls180.v:168621.18-168621.100" + wire $or$issuer_ls180.v:168621$11160_Y + attribute \src "issuer_ls180.v:168624.17-168624.98" + wire $or$issuer_ls180.v:168624$11163_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire \$13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" + wire input 5 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" + wire input 1 \coresync_rst + attribute \src "issuer_ls180.v:168583.7-168583.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire output 2 \q_rdok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" + wire \qlq_rdok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + wire \qn_rdok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire input 4 \r_rdok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire input 3 \s_rdok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $and $and$issuer_ls180.v:168618$11157 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$7 + connect \Y $and$issuer_ls180.v:168618$11157_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $and $and$issuer_ls180.v:168623$11162 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$1 + connect \Y $and$issuer_ls180.v:168623$11162_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + cell $not $not$issuer_ls180.v:168620$11159 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_rdok + connect \Y $not$issuer_ls180.v:168620$11159_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $not $not$issuer_ls180.v:168622$11161 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_rdok + connect \Y $not$issuer_ls180.v:168622$11161_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $not $not$issuer_ls180.v:168625$11164 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_rdok + connect \Y $not$issuer_ls180.v:168625$11164_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $or $or$issuer_ls180.v:168619$11158 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$9 + connect \B \s_rdok + connect \Y $or$issuer_ls180.v:168619$11158_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + cell $or $or$issuer_ls180.v:168621$11160 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_rdok + connect \B \q_int + connect \Y $or$issuer_ls180.v:168621$11160_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $or $or$issuer_ls180.v:168624$11163 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$3 + connect \B \s_rdok + connect \Y $or$issuer_ls180.v:168624$11163_Y + end + attribute \src "issuer_ls180.v:168583.7-168583.20" + process $proc$issuer_ls180.v:168583$11169 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "issuer_ls180.v:168605.7-168605.19" + process $proc$issuer_ls180.v:168605$11170 + assign { } { } + assign $1\q_int[0:0] 1'0 + sync always + sync init + update \q_int $1\q_int[0:0] + end + attribute \src "issuer_ls180.v:168626.3-168627.27" + process $proc$issuer_ls180.v:168626$11165 + assign { } { } + assign $0\q_int[0:0] \q_int$next + sync posedge \coresync_clk + update \q_int $0\q_int[0:0] + end + attribute \src "issuer_ls180.v:168628.3-168636.6" + process $proc$issuer_ls180.v:168628$11166 + assign { } { } + assign { } { } + assign $0\q_int$next[0:0]$11167 $1\q_int$next[0:0]$11168 + attribute \src "issuer_ls180.v:168629.5-168629.29" + switch \initial + attribute \src "issuer_ls180.v:168629.9-168629.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\q_int$next[0:0]$11168 1'0 + case + assign $1\q_int$next[0:0]$11168 \$5 + end + sync always + update \q_int$next $0\q_int$next[0:0]$11167 + end + connect \$9 $and$issuer_ls180.v:168618$11157_Y + connect \$11 $or$issuer_ls180.v:168619$11158_Y + connect \$13 $not$issuer_ls180.v:168620$11159_Y + connect \$15 $or$issuer_ls180.v:168621$11160_Y + connect \$1 $not$issuer_ls180.v:168622$11161_Y + connect \$3 $and$issuer_ls180.v:168623$11162_Y + connect \$5 $or$issuer_ls180.v:168624$11163_Y + connect \$7 $not$issuer_ls180.v:168625$11164_Y + connect \qlq_rdok \$15 + connect \qn_rdok \$13 + connect \q_rdok \$11 +end +attribute \src "issuer_ls180.v:168644.1-168702.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.fus.spr0.rok_l" +attribute \generator "nMigen" +module \rok_l$68 + attribute \src "issuer_ls180.v:168645.7-168645.20" + wire $0\initial[0:0] + attribute \src "issuer_ls180.v:168690.3-168698.6" + wire $0\q_int$next[0:0]$11181 + attribute \src "issuer_ls180.v:168688.3-168689.27" + wire $0\q_int[0:0] + attribute \src "issuer_ls180.v:168690.3-168698.6" + wire $1\q_int$next[0:0]$11182 + attribute \src "issuer_ls180.v:168667.7-168667.19" + wire $1\q_int[0:0] + attribute \src "issuer_ls180.v:168680.17-168680.96" + wire $and$issuer_ls180.v:168680$11171_Y + attribute \src "issuer_ls180.v:168685.17-168685.96" + wire $and$issuer_ls180.v:168685$11176_Y + attribute \src "issuer_ls180.v:168682.18-168682.94" + wire $not$issuer_ls180.v:168682$11173_Y + attribute \src "issuer_ls180.v:168684.17-168684.93" + wire $not$issuer_ls180.v:168684$11175_Y + attribute \src "issuer_ls180.v:168687.17-168687.93" + wire $not$issuer_ls180.v:168687$11178_Y + attribute \src "issuer_ls180.v:168681.18-168681.99" + wire $or$issuer_ls180.v:168681$11172_Y + attribute \src "issuer_ls180.v:168683.18-168683.100" + wire $or$issuer_ls180.v:168683$11174_Y + attribute \src "issuer_ls180.v:168686.17-168686.98" + wire $or$issuer_ls180.v:168686$11177_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire \$13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" + wire input 5 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" + wire input 1 \coresync_rst + attribute \src "issuer_ls180.v:168645.7-168645.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire output 2 \q_rdok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" + wire \qlq_rdok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + wire \qn_rdok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire input 4 \r_rdok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire input 3 \s_rdok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $and $and$issuer_ls180.v:168680$11171 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$7 + connect \Y $and$issuer_ls180.v:168680$11171_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $and $and$issuer_ls180.v:168685$11176 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$1 + connect \Y $and$issuer_ls180.v:168685$11176_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + cell $not $not$issuer_ls180.v:168682$11173 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_rdok + connect \Y $not$issuer_ls180.v:168682$11173_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $not $not$issuer_ls180.v:168684$11175 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_rdok + connect \Y $not$issuer_ls180.v:168684$11175_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $not $not$issuer_ls180.v:168687$11178 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_rdok + connect \Y $not$issuer_ls180.v:168687$11178_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $or $or$issuer_ls180.v:168681$11172 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$9 + connect \B \s_rdok + connect \Y $or$issuer_ls180.v:168681$11172_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + cell $or $or$issuer_ls180.v:168683$11174 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_rdok + connect \B \q_int + connect \Y $or$issuer_ls180.v:168683$11174_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $or $or$issuer_ls180.v:168686$11177 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$3 + connect \B \s_rdok + connect \Y $or$issuer_ls180.v:168686$11177_Y + end + attribute \src "issuer_ls180.v:168645.7-168645.20" + process $proc$issuer_ls180.v:168645$11183 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "issuer_ls180.v:168667.7-168667.19" + process $proc$issuer_ls180.v:168667$11184 + assign { } { } + assign $1\q_int[0:0] 1'0 + sync always + sync init + update \q_int $1\q_int[0:0] + end + attribute \src "issuer_ls180.v:168688.3-168689.27" + process $proc$issuer_ls180.v:168688$11179 + assign { } { } + assign $0\q_int[0:0] \q_int$next + sync posedge \coresync_clk + update \q_int $0\q_int[0:0] + end + attribute \src "issuer_ls180.v:168690.3-168698.6" + process $proc$issuer_ls180.v:168690$11180 + assign { } { } + assign { } { } + assign $0\q_int$next[0:0]$11181 $1\q_int$next[0:0]$11182 + attribute \src "issuer_ls180.v:168691.5-168691.29" + switch \initial + attribute \src "issuer_ls180.v:168691.9-168691.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\q_int$next[0:0]$11182 1'0 + case + assign $1\q_int$next[0:0]$11182 \$5 + end + sync always + update \q_int$next $0\q_int$next[0:0]$11181 + end + connect \$9 $and$issuer_ls180.v:168680$11171_Y + connect \$11 $or$issuer_ls180.v:168681$11172_Y + connect \$13 $not$issuer_ls180.v:168682$11173_Y + connect \$15 $or$issuer_ls180.v:168683$11174_Y + connect \$1 $not$issuer_ls180.v:168684$11175_Y + connect \$3 $and$issuer_ls180.v:168685$11176_Y + connect \$5 $or$issuer_ls180.v:168686$11177_Y + connect \$7 $not$issuer_ls180.v:168687$11178_Y + connect \qlq_rdok \$15 + connect \qn_rdok \$13 + connect \q_rdok \$11 +end +attribute \src "issuer_ls180.v:168706.1-168764.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.rok_l" +attribute \generator "nMigen" +module \rok_l$85 + attribute \src "issuer_ls180.v:168707.7-168707.20" + wire $0\initial[0:0] + attribute \src "issuer_ls180.v:168752.3-168760.6" + wire $0\q_int$next[0:0]$11195 + attribute \src "issuer_ls180.v:168750.3-168751.27" + wire $0\q_int[0:0] + attribute \src "issuer_ls180.v:168752.3-168760.6" + wire $1\q_int$next[0:0]$11196 + attribute \src "issuer_ls180.v:168729.7-168729.19" + wire $1\q_int[0:0] + attribute \src "issuer_ls180.v:168742.17-168742.96" + wire $and$issuer_ls180.v:168742$11185_Y + attribute \src "issuer_ls180.v:168747.17-168747.96" + wire $and$issuer_ls180.v:168747$11190_Y + attribute \src "issuer_ls180.v:168744.18-168744.94" + wire $not$issuer_ls180.v:168744$11187_Y + attribute \src "issuer_ls180.v:168746.17-168746.93" + wire $not$issuer_ls180.v:168746$11189_Y + attribute \src "issuer_ls180.v:168749.17-168749.93" + wire $not$issuer_ls180.v:168749$11192_Y + attribute \src "issuer_ls180.v:168743.18-168743.99" + wire $or$issuer_ls180.v:168743$11186_Y + attribute \src "issuer_ls180.v:168745.18-168745.100" + wire $or$issuer_ls180.v:168745$11188_Y + attribute \src "issuer_ls180.v:168748.17-168748.98" + wire $or$issuer_ls180.v:168748$11191_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire \$13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" + wire input 5 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" + wire input 1 \coresync_rst + attribute \src "issuer_ls180.v:168707.7-168707.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire output 2 \q_rdok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" + wire \qlq_rdok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + wire \qn_rdok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire input 4 \r_rdok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire input 3 \s_rdok + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $and $and$issuer_ls180.v:168742$11185 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$7 + connect \Y $and$issuer_ls180.v:168742$11185_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $and $and$issuer_ls180.v:168747$11190 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$1 + connect \Y $and$issuer_ls180.v:168747$11190_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + cell $not $not$issuer_ls180.v:168744$11187 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_rdok + connect \Y $not$issuer_ls180.v:168744$11187_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $not $not$issuer_ls180.v:168746$11189 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_rdok + connect \Y $not$issuer_ls180.v:168746$11189_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $not $not$issuer_ls180.v:168749$11192 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_rdok + connect \Y $not$issuer_ls180.v:168749$11192_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $or $or$issuer_ls180.v:168743$11186 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$9 + connect \B \s_rdok + connect \Y $or$issuer_ls180.v:168743$11186_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + cell $or $or$issuer_ls180.v:168745$11188 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_rdok + connect \B \q_int + connect \Y $or$issuer_ls180.v:168745$11188_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $or $or$issuer_ls180.v:168748$11191 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$3 + connect \B \s_rdok + connect \Y $or$issuer_ls180.v:168748$11191_Y + end + attribute \src "issuer_ls180.v:168707.7-168707.20" + process $proc$issuer_ls180.v:168707$11197 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "issuer_ls180.v:168729.7-168729.19" + process $proc$issuer_ls180.v:168729$11198 + assign { } { } + assign $1\q_int[0:0] 1'0 + sync always + sync init + update \q_int $1\q_int[0:0] + end + attribute \src "issuer_ls180.v:168750.3-168751.27" + process $proc$issuer_ls180.v:168750$11193 + assign { } { } + assign $0\q_int[0:0] \q_int$next + sync posedge \coresync_clk + update \q_int $0\q_int[0:0] + end + attribute \src "issuer_ls180.v:168752.3-168760.6" + process $proc$issuer_ls180.v:168752$11194 + assign { } { } + assign { } { } + assign $0\q_int$next[0:0]$11195 $1\q_int$next[0:0]$11196 + attribute \src "issuer_ls180.v:168753.5-168753.29" + switch \initial + attribute \src "issuer_ls180.v:168753.9-168753.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\q_int$next[0:0]$11196 1'0 + case + assign $1\q_int$next[0:0]$11196 \$5 + end + sync always + update \q_int$next $0\q_int$next[0:0]$11195 + end + connect \$9 $and$issuer_ls180.v:168742$11185_Y + connect \$11 $or$issuer_ls180.v:168743$11186_Y + connect \$13 $not$issuer_ls180.v:168744$11187_Y + connect \$15 $or$issuer_ls180.v:168745$11188_Y + connect \$1 $not$issuer_ls180.v:168746$11189_Y + connect \$3 $and$issuer_ls180.v:168747$11190_Y + connect \$5 $or$issuer_ls180.v:168748$11191_Y + connect \$7 $not$issuer_ls180.v:168749$11192_Y + connect \qlq_rdok \$15 + connect \qn_rdok \$13 + connect \q_rdok \$11 +end +attribute \src "issuer_ls180.v:168768.1-169119.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.fus.shiftrot0.alu_shift_rot0.pipe1.main.rotator" +attribute \generator "nMigen" +module \rotator + attribute \src "issuer_ls180.v:169037.3-169046.6" + wire $0\carry_out_o[0:0] + attribute \src "issuer_ls180.v:168969.3-168983.6" + wire width 32 $0\hi32[31:0] + attribute \src "issuer_ls180.v:168769.7-168769.20" + wire $0\initial[0:0] + attribute \src "issuer_ls180.v:169059.3-169092.6" + wire width 7 $0\mb$8[6:0]$11246 + attribute \src "issuer_ls180.v:169093.3-169107.6" + wire width 7 $0\me$13[6:0]$11251 + attribute \src "issuer_ls180.v:168994.3-169005.6" + wire width 64 $0\mr[63:0] + attribute \src "issuer_ls180.v:169006.3-169017.6" + wire width 2 $0\output_mode[1:0] + attribute \src "issuer_ls180.v:169018.3-169036.6" + wire width 64 $0\result_o[63:0] + attribute \src "issuer_ls180.v:168984.3-168993.6" + wire width 7 $0\right_mask_shift[6:0] + attribute \src "issuer_ls180.v:169047.3-169058.6" + wire width 6 $0\rot_count[5:0] + attribute \src "issuer_ls180.v:169037.3-169046.6" + wire $1\carry_out_o[0:0] + attribute \src "issuer_ls180.v:168969.3-168983.6" + wire width 32 $1\hi32[31:0] + attribute \src "issuer_ls180.v:169059.3-169092.6" + wire width 7 $1\mb$8[6:0]$11247 + attribute \src "issuer_ls180.v:169093.3-169107.6" + wire width 7 $1\me$13[6:0]$11252 + attribute \src "issuer_ls180.v:168994.3-169005.6" + wire width 64 $1\mr[63:0] + attribute \src "issuer_ls180.v:169006.3-169017.6" + wire width 2 $1\output_mode[1:0] + attribute \src "issuer_ls180.v:169018.3-169036.6" + wire width 64 $1\result_o[63:0] + attribute \src "issuer_ls180.v:168984.3-168993.6" + wire width 7 $1\right_mask_shift[6:0] + attribute \src "issuer_ls180.v:169047.3-169058.6" + wire width 6 $1\rot_count[5:0] + attribute \src "issuer_ls180.v:169059.3-169092.6" + wire width 2 $2\mb$8[6:5]$11248 + attribute \src "issuer_ls180.v:169059.3-169092.6" + wire width 2 $3\mb$8[6:5]$11249 + attribute \src "issuer_ls180.v:168920.18-168920.118" + wire $and$issuer_ls180.v:168920$11202_Y + attribute \src "issuer_ls180.v:168922.18-168922.114" + wire $and$issuer_ls180.v:168922$11204_Y + attribute \src "issuer_ls180.v:168931.18-168931.113" + wire $and$issuer_ls180.v:168931$11213_Y + attribute \src "issuer_ls180.v:168933.18-168933.114" + wire $and$issuer_ls180.v:168933$11215_Y + attribute \src "issuer_ls180.v:168935.18-168935.114" + wire $and$issuer_ls180.v:168935$11217_Y + attribute \src "issuer_ls180.v:168936.18-168936.103" + wire width 64 $and$issuer_ls180.v:168936$11218_Y + attribute \src "issuer_ls180.v:168937.18-168937.106" + wire width 64 $and$issuer_ls180.v:168937$11219_Y + attribute \src "issuer_ls180.v:168939.18-168939.103" + wire width 64 $and$issuer_ls180.v:168939$11221_Y + attribute \src "issuer_ls180.v:168941.18-168941.105" + wire width 64 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cell $not $not$issuer_ls180.v:168923$11205 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \Y_WIDTH 6 + connect \A \sh [5:0] + connect \Y $not$issuer_ls180.v:168923$11205_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:152" + cell $not $not$issuer_ls180.v:168929$11211 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A \left_mask_mask + connect \Y $not$issuer_ls180.v:168929$11211_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:161" + cell $not $not$issuer_ls180.v:168930$11212 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \clear_right + connect \Y $not$issuer_ls180.v:168930$11212_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:110" + cell $not $not$issuer_ls180.v:168938$11220 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \is_32bit + connect \Y $not$issuer_ls180.v:168938$11220_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:170" + cell $not $not$issuer_ls180.v:168940$11222 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A \$51 + connect \Y $not$issuer_ls180.v:168940$11222_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:172" + cell $not $not$issuer_ls180.v:168946$11228 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A \$63 + connect \Y $not$issuer_ls180.v:168946$11228_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:176" + cell $not $not$issuer_ls180.v:168951$11233 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A \mr + connect \Y $not$issuer_ls180.v:168951$11233_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:178" + cell $not $not$issuer_ls180.v:168953$11235 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A \ml + connect \Y $not$issuer_ls180.v:168953$11235_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:161" + cell $or $or$issuer_ls180.v:168932$11214 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$36 + connect \B \right_shift + connect \Y $or$issuer_ls180.v:168932$11214_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:170" + cell $or $or$issuer_ls180.v:168942$11224 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A \$48 + connect \B \$54 + connect \Y $or$issuer_ls180.v:168942$11224_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:172" + cell $or $or$issuer_ls180.v:168943$11225 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A \mr + connect \B \ml + connect \Y $or$issuer_ls180.v:168943$11225_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:172" + cell $or $or$issuer_ls180.v:168945$11227 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A \mr + connect \B \ml + connect \Y $or$issuer_ls180.v:168945$11227_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:172" + cell $or $or$issuer_ls180.v:168948$11230 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A \$60 + connect \B \$66 + connect \Y $or$issuer_ls180.v:168948$11230_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:176" + cell $or $or$issuer_ls180.v:168952$11234 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A \rot + connect \B \$72 + connect \Y $or$issuer_ls180.v:168952$11234_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:51" + cell $pos $pos$issuer_ls180.v:168918$11200 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \Y_WIDTH 7 + connect \A $extend$issuer_ls180.v:168918$11199_Y + connect \Y $pos$issuer_ls180.v:168918$11200_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:178" + cell $reduce_or $reduce_or$issuer_ls180.v:168955$11237 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 1 + connect \A \$79 + connect \Y $reduce_or$issuer_ls180.v:168955$11237_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:144" + cell $sub $sub$issuer_ls180.v:168925$11207 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 8 + connect \A 7'1000000 + connect \B \mb$8 + connect \Y $sub$issuer_ls180.v:168925$11207_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:151" + cell $sub $sub$issuer_ls180.v:168928$11210 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 8 + connect \A 6'111111 + connect \B \me$13 + connect \Y $sub$issuer_ls180.v:168928$11210_Y + end + attribute \module_not_derived 1 + attribute \src "issuer_ls180.v:168956.13-168959.4" + cell \left_mask \left_mask + connect \mask \left_mask_mask + connect \shift \left_mask_shift + end + attribute \module_not_derived 1 + attribute \src "issuer_ls180.v:168960.14-168963.4" + cell \right_mask \right_mask + connect \mask \right_mask_mask + connect \shift \right_mask_shift + end + attribute \module_not_derived 1 + attribute \src "issuer_ls180.v:168964.8-168968.4" + cell \rotl \rotl + connect \a \rotl_a + connect \b \rotl_b + connect \o \rotl_o + end + attribute \src "issuer_ls180.v:168769.7-168769.20" + process $proc$issuer_ls180.v:168769$11253 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "issuer_ls180.v:168969.3-168983.6" + process $proc$issuer_ls180.v:168969$11238 + assign { } { } + assign $0\hi32[31:0] $1\hi32[31:0] + attribute \src "issuer_ls180.v:168970.5-168970.29" + switch \initial + attribute \src "issuer_ls180.v:168970.9-168970.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:85" + switch { \sign_ext_rs \is_32bit } + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\hi32[31:0] \rs [31:0] + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\hi32[31:0] { \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] } + attribute \src "issuer_ls180.v:0.0-0.0" + case + assign { } { } + assign $1\hi32[31:0] \rs [63:32] + end + sync always + update \hi32 $0\hi32[31:0] + end + attribute \src "issuer_ls180.v:168984.3-168993.6" + process $proc$issuer_ls180.v:168984$11239 + assign { } { } + assign { } { } + assign $0\right_mask_shift[6:0] $1\right_mask_shift[6:0] + attribute \src "issuer_ls180.v:168985.5-168985.29" + switch \initial + attribute \src "issuer_ls180.v:168985.9-168985.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:143" + switch \$22 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\right_mask_shift[6:0] \$24 [6:0] + case + assign $1\right_mask_shift[6:0] 7'0000000 + end + sync always + update \right_mask_shift $0\right_mask_shift[6:0] + end + attribute \src "issuer_ls180.v:168994.3-169005.6" + process $proc$issuer_ls180.v:168994$11240 + assign { } { } + assign $0\mr[63:0] $1\mr[63:0] + attribute \src "issuer_ls180.v:168995.5-168995.29" + switch \initial + attribute \src "issuer_ls180.v:168995.9-168995.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:143" + switch \$27 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\mr[63:0] \right_mask_mask + attribute \src "issuer_ls180.v:0.0-0.0" + case + assign { } { } + assign $1\mr[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \mr $0\mr[63:0] + end + attribute \src "issuer_ls180.v:169006.3-169017.6" + process $proc$issuer_ls180.v:169006$11241 + assign { } { } + assign $0\output_mode[1:0] $1\output_mode[1:0] + attribute \src "issuer_ls180.v:169007.5-169007.29" + switch \initial + attribute \src "issuer_ls180.v:169007.9-169007.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:161" + switch \$38 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\output_mode[1:0] { 1'1 \$40 } + attribute \src "issuer_ls180.v:0.0-0.0" + case + assign { } { } + assign $1\output_mode[1:0] { 1'0 \$44 } + end + sync always + update \output_mode $0\output_mode[1:0] + end + attribute \src "issuer_ls180.v:169018.3-169036.6" + process $proc$issuer_ls180.v:169018$11242 + assign { } { } + assign { } { } + assign $0\result_o[63:0] $1\result_o[63:0] + attribute \src "issuer_ls180.v:169019.5-169019.29" + switch \initial + attribute \src "issuer_ls180.v:169019.9-169019.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:168" + switch \output_mode + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\result_o[63:0] \$56 + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\result_o[63:0] \$68 + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\result_o[63:0] \$70 + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'11 + assign { } { } + assign $1\result_o[63:0] \$74 + case + assign $1\result_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \result_o $0\result_o[63:0] + end + attribute \src "issuer_ls180.v:169037.3-169046.6" + process $proc$issuer_ls180.v:169037$11243 + assign { } { } + assign { } { } + assign $0\carry_out_o[0:0] $1\carry_out_o[0:0] + attribute \src "issuer_ls180.v:169038.5-169038.29" + switch \initial + attribute \src "issuer_ls180.v:169038.9-169038.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:168" + switch \output_mode + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'11 + assign { } { } + assign $1\carry_out_o[0:0] \$76 + case + assign $1\carry_out_o[0:0] 1'0 + end + sync always + update \carry_out_o $0\carry_out_o[0:0] + end + attribute \src "issuer_ls180.v:169047.3-169058.6" + process $proc$issuer_ls180.v:169047$11244 + assign { } { } + assign $0\rot_count[5:0] $1\rot_count[5:0] + attribute \src "issuer_ls180.v:169048.5-169048.29" + switch \initial + attribute \src "issuer_ls180.v:169048.9-169048.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:98" + switch \right_shift + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\rot_count[5:0] \$1 [5:0] + attribute \src "issuer_ls180.v:0.0-0.0" + case + assign { } { } + assign $1\rot_count[5:0] \shift [5:0] + end + sync always + update \rot_count $0\rot_count[5:0] + end + attribute \src "issuer_ls180.v:169059.3-169092.6" + process $proc$issuer_ls180.v:169059$11245 + assign { } { } + assign $0\mb$8[6:0]$11246 $1\mb$8[6:0]$11247 + attribute \src "issuer_ls180.v:169060.5-169060.29" + switch \initial + attribute \src "issuer_ls180.v:169060.9-169060.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:116" + switch { \right_shift \clear_left } + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\mb$8[6:0]$11247 [4:0] \$9 [4:0] + assign $1\mb$8[6:0]$11247 [6:5] $2\mb$8[6:5]$11248 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:118" + switch \is_32bit + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\mb$8[6:5]$11248 2'01 + attribute \src "issuer_ls180.v:0.0-0.0" + case + assign { } { } + assign $2\mb$8[6:5]$11248 { 1'0 \mb_extra } + end + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\mb$8[6:0]$11247 [4:0] \sh [4:0] + assign $1\mb$8[6:0]$11247 [6:5] $3\mb$8[6:5]$11249 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:125" + switch \is_32bit + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\mb$8[6:5]$11249 { \sh [5] \$11 } + case + assign $3\mb$8[6:5]$11249 \sh [6:5] + end + attribute \src "issuer_ls180.v:0.0-0.0" + case + assign { } { } + assign $1\mb$8[6:0]$11247 { 1'0 \is_32bit 5'00000 } + end + sync always + update \mb$8 $0\mb$8[6:0]$11246 + end + attribute \src "issuer_ls180.v:169093.3-169107.6" + process $proc$issuer_ls180.v:169093$11250 + assign { } { } + assign $0\me$13[6:0]$11251 $1\me$13[6:0]$11252 + attribute \src "issuer_ls180.v:169094.5-169094.29" + switch \initial + attribute \src "issuer_ls180.v:169094.9-169094.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:131" + switch { \$18 \$14 } + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\me$13[6:0]$11252 { 2'01 \me } + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'1- + assign { } { } + assign $1\me$13[6:0]$11252 { 1'0 \mb_extra \mb } + attribute \src "issuer_ls180.v:0.0-0.0" + case + assign { } { } + assign $1\me$13[6:0]$11252 { \sh [6] \$20 } + end + sync always + update \me$13 $0\me$13[6:0]$11251 + end + connect \$9 $pos$issuer_ls180.v:168918$11200_Y + connect \$11 $not$issuer_ls180.v:168919$11201_Y + connect \$14 $and$issuer_ls180.v:168920$11202_Y + connect \$16 $not$issuer_ls180.v:168921$11203_Y + connect \$18 $and$issuer_ls180.v:168922$11204_Y + connect \$20 $not$issuer_ls180.v:168923$11205_Y + connect \$22 $le$issuer_ls180.v:168924$11206_Y + connect \$25 $sub$issuer_ls180.v:168925$11207_Y + connect \$27 $le$issuer_ls180.v:168926$11208_Y + connect \$2 $neg$issuer_ls180.v:168927$11209_Y + connect \$30 $sub$issuer_ls180.v:168928$11210_Y + connect \$32 $not$issuer_ls180.v:168929$11211_Y + connect \$34 $not$issuer_ls180.v:168930$11212_Y + connect \$36 $and$issuer_ls180.v:168931$11213_Y + connect \$38 $or$issuer_ls180.v:168932$11214_Y + connect \$40 $and$issuer_ls180.v:168933$11215_Y + connect \$42 $gt$issuer_ls180.v:168934$11216_Y + connect \$44 $and$issuer_ls180.v:168935$11217_Y + connect \$46 $and$issuer_ls180.v:168936$11218_Y + connect \$48 $and$issuer_ls180.v:168937$11219_Y + connect \$4 $not$issuer_ls180.v:168938$11220_Y + connect \$51 $and$issuer_ls180.v:168939$11221_Y + connect \$50 $not$issuer_ls180.v:168940$11222_Y + connect \$54 $and$issuer_ls180.v:168941$11223_Y + connect \$56 $or$issuer_ls180.v:168942$11224_Y + connect \$58 $or$issuer_ls180.v:168943$11225_Y + connect \$60 $and$issuer_ls180.v:168944$11226_Y + connect \$63 $or$issuer_ls180.v:168945$11227_Y + connect \$62 $not$issuer_ls180.v:168946$11228_Y + connect \$66 $and$issuer_ls180.v:168947$11229_Y + connect \$68 $or$issuer_ls180.v:168948$11230_Y + connect \$6 $and$issuer_ls180.v:168949$11231_Y + connect \$70 $and$issuer_ls180.v:168950$11232_Y + connect \$72 $not$issuer_ls180.v:168951$11233_Y + connect \$74 $or$issuer_ls180.v:168952$11234_Y + connect \$77 $not$issuer_ls180.v:168953$11235_Y + connect \$79 $and$issuer_ls180.v:168954$11236_Y + connect \$76 $reduce_or$issuer_ls180.v:168955$11237_Y + connect \$1 \$2 + connect \$24 \$25 + connect \$29 \$30 + connect \ml \$32 + connect \left_mask_shift \$30 [6:0] + connect \sh { \$6 \shift [5:0] } + connect \rot \rotl_o + connect \rotl_b \rot_count + connect \rotl_a \repl32 + connect \shift_signed \shift [5:0] + connect \repl32 { \hi32 \rs [31:0] } +end +attribute \src "issuer_ls180.v:169123.1-169137.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.fus.shiftrot0.alu_shift_rot0.pipe1.main.rotator.rotl" +attribute \generator "nMigen" +module \rotl + attribute \src "issuer_ls180.v:169135.17-169135.32" + wire width 128 $shr$issuer_ls180.v:169135$11255_Y + attribute \src "issuer_ls180.v:169134.17-169134.100" + wire width 8 $sub$issuer_ls180.v:169134$11254_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotl.py:19" + wire width 64 \$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotl.py:18" + wire width 8 \$2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotl.py:8" + wire width 64 input 3 \a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotl.py:9" + wire width 6 input 1 \b + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotl.py:11" + wire width 64 output 2 \o + attribute \src "issuer_ls180.v:169135.17-169135.32" + cell $shr $shr$issuer_ls180.v:169135$11255 + parameter \A_SIGNED 0 + parameter \A_WIDTH 128 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 128 + connect \A { \a \a } + connect \B \$2 + connect \Y $shr$issuer_ls180.v:169135$11255_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotl.py:18" + cell $sub $sub$issuer_ls180.v:169134$11254 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 8 + connect \A 7'1000000 + connect \B \b + connect \Y $sub$issuer_ls180.v:169134$11254_Y + end + connect \$2 $sub$issuer_ls180.v:169134$11254_Y + connect \$1 $shr$issuer_ls180.v:169135$11255_Y [63:0] + connect \o \$1 +end +attribute \src "issuer_ls180.v:169141.1-169199.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.fus.alu0.rst_l" +attribute \generator "nMigen" +module \rst_l + attribute \src "issuer_ls180.v:169142.7-169142.20" + wire $0\initial[0:0] + attribute \src "issuer_ls180.v:169187.3-169195.6" + wire $0\q_int$next[0:0]$11266 + attribute \src "issuer_ls180.v:169185.3-169186.27" + wire $0\q_int[0:0] + attribute \src "issuer_ls180.v:169187.3-169195.6" + wire $1\q_int$next[0:0]$11267 + attribute \src "issuer_ls180.v:169164.7-169164.19" + wire $1\q_int[0:0] + attribute \src "issuer_ls180.v:169177.17-169177.96" + wire $and$issuer_ls180.v:169177$11256_Y + attribute \src "issuer_ls180.v:169182.17-169182.96" + wire $and$issuer_ls180.v:169182$11261_Y + attribute \src "issuer_ls180.v:169179.18-169179.93" + wire $not$issuer_ls180.v:169179$11258_Y + attribute \src "issuer_ls180.v:169181.17-169181.92" + wire $not$issuer_ls180.v:169181$11260_Y + attribute \src "issuer_ls180.v:169184.17-169184.92" + wire $not$issuer_ls180.v:169184$11263_Y + attribute \src "issuer_ls180.v:169178.18-169178.98" + wire $or$issuer_ls180.v:169178$11257_Y + attribute \src "issuer_ls180.v:169180.18-169180.99" + wire $or$issuer_ls180.v:169180$11259_Y + attribute \src "issuer_ls180.v:169183.17-169183.97" + wire $or$issuer_ls180.v:169183$11262_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire \$13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" + wire input 4 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" + wire input 1 \coresync_rst + attribute \src "issuer_ls180.v:169142.7-169142.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire \q_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" + wire \qlq_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + wire \qn_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire input 3 \r_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire input 2 \s_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $and $and$issuer_ls180.v:169177$11256 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$7 + connect \Y $and$issuer_ls180.v:169177$11256_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $and $and$issuer_ls180.v:169182$11261 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$1 + connect \Y $and$issuer_ls180.v:169182$11261_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + cell $not $not$issuer_ls180.v:169179$11258 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_rst + connect \Y $not$issuer_ls180.v:169179$11258_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $not $not$issuer_ls180.v:169181$11260 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_rst + connect \Y $not$issuer_ls180.v:169181$11260_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $not $not$issuer_ls180.v:169184$11263 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_rst + connect \Y $not$issuer_ls180.v:169184$11263_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $or $or$issuer_ls180.v:169178$11257 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$9 + connect \B \s_rst + connect \Y $or$issuer_ls180.v:169178$11257_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + cell $or $or$issuer_ls180.v:169180$11259 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_rst + connect \B \q_int + connect \Y $or$issuer_ls180.v:169180$11259_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $or $or$issuer_ls180.v:169183$11262 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$3 + connect \B \s_rst + connect \Y $or$issuer_ls180.v:169183$11262_Y + end + attribute \src "issuer_ls180.v:169142.7-169142.20" + process $proc$issuer_ls180.v:169142$11268 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "issuer_ls180.v:169164.7-169164.19" + process $proc$issuer_ls180.v:169164$11269 + assign { } { } + assign $1\q_int[0:0] 1'0 + sync always + sync init + update \q_int $1\q_int[0:0] + end + attribute \src "issuer_ls180.v:169185.3-169186.27" + process $proc$issuer_ls180.v:169185$11264 + assign { } { } + assign $0\q_int[0:0] \q_int$next + sync posedge \coresync_clk + update \q_int $0\q_int[0:0] + end + attribute \src "issuer_ls180.v:169187.3-169195.6" + process $proc$issuer_ls180.v:169187$11265 + assign { } { } + assign { } { } + assign $0\q_int$next[0:0]$11266 $1\q_int$next[0:0]$11267 + attribute \src "issuer_ls180.v:169188.5-169188.29" + switch \initial + attribute \src "issuer_ls180.v:169188.9-169188.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\q_int$next[0:0]$11267 1'0 + case + assign $1\q_int$next[0:0]$11267 \$5 + end + sync always + update \q_int$next $0\q_int$next[0:0]$11266 + end + connect \$9 $and$issuer_ls180.v:169177$11256_Y + connect \$11 $or$issuer_ls180.v:169178$11257_Y + connect \$13 $not$issuer_ls180.v:169179$11258_Y + connect \$15 $or$issuer_ls180.v:169180$11259_Y + connect \$1 $not$issuer_ls180.v:169181$11260_Y + connect \$3 $and$issuer_ls180.v:169182$11261_Y + connect \$5 $or$issuer_ls180.v:169183$11262_Y + connect \$7 $not$issuer_ls180.v:169184$11263_Y + connect \qlq_rst \$15 + connect \qn_rst \$13 + connect \q_rst \$11 +end +attribute \src "issuer_ls180.v:169203.1-169261.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.fus.mul0.rst_l" +attribute \generator "nMigen" +module \rst_l$101 + attribute \src "issuer_ls180.v:169204.7-169204.20" + wire $0\initial[0:0] + attribute \src "issuer_ls180.v:169249.3-169257.6" + wire $0\q_int$next[0:0]$11280 + attribute \src "issuer_ls180.v:169247.3-169248.27" + wire $0\q_int[0:0] + attribute \src "issuer_ls180.v:169249.3-169257.6" + wire $1\q_int$next[0:0]$11281 + attribute \src "issuer_ls180.v:169226.7-169226.19" + wire $1\q_int[0:0] + attribute \src "issuer_ls180.v:169239.17-169239.96" + wire $and$issuer_ls180.v:169239$11270_Y + attribute \src "issuer_ls180.v:169244.17-169244.96" + wire $and$issuer_ls180.v:169244$11275_Y + attribute \src "issuer_ls180.v:169241.18-169241.93" + wire $not$issuer_ls180.v:169241$11272_Y + attribute \src "issuer_ls180.v:169243.17-169243.92" + wire $not$issuer_ls180.v:169243$11274_Y + attribute \src "issuer_ls180.v:169246.17-169246.92" + wire $not$issuer_ls180.v:169246$11277_Y + attribute \src "issuer_ls180.v:169240.18-169240.98" + wire $or$issuer_ls180.v:169240$11271_Y + attribute \src "issuer_ls180.v:169242.18-169242.99" + wire $or$issuer_ls180.v:169242$11273_Y + attribute \src "issuer_ls180.v:169245.17-169245.97" + wire $or$issuer_ls180.v:169245$11276_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire \$13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" + wire input 4 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" + wire input 1 \coresync_rst + attribute \src "issuer_ls180.v:169204.7-169204.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire \q_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" + wire \qlq_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + wire \qn_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire input 3 \r_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire input 2 \s_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $and $and$issuer_ls180.v:169239$11270 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$7 + connect \Y $and$issuer_ls180.v:169239$11270_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $and $and$issuer_ls180.v:169244$11275 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$1 + connect \Y $and$issuer_ls180.v:169244$11275_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + cell $not $not$issuer_ls180.v:169241$11272 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_rst + connect \Y $not$issuer_ls180.v:169241$11272_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $not $not$issuer_ls180.v:169243$11274 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_rst + connect \Y $not$issuer_ls180.v:169243$11274_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $not $not$issuer_ls180.v:169246$11277 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_rst + connect \Y $not$issuer_ls180.v:169246$11277_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $or $or$issuer_ls180.v:169240$11271 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$9 + connect \B \s_rst + connect \Y $or$issuer_ls180.v:169240$11271_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + cell $or $or$issuer_ls180.v:169242$11273 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_rst + connect \B \q_int + connect \Y $or$issuer_ls180.v:169242$11273_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $or $or$issuer_ls180.v:169245$11276 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$3 + connect \B \s_rst + connect \Y $or$issuer_ls180.v:169245$11276_Y + end + attribute \src "issuer_ls180.v:169204.7-169204.20" + process $proc$issuer_ls180.v:169204$11282 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "issuer_ls180.v:169226.7-169226.19" + process $proc$issuer_ls180.v:169226$11283 + assign { } { } + assign $1\q_int[0:0] 1'0 + sync always + sync init + update \q_int $1\q_int[0:0] + end + attribute \src "issuer_ls180.v:169247.3-169248.27" + process $proc$issuer_ls180.v:169247$11278 + assign { } { } + assign $0\q_int[0:0] \q_int$next + sync posedge \coresync_clk + update \q_int $0\q_int[0:0] + end + attribute \src "issuer_ls180.v:169249.3-169257.6" + process $proc$issuer_ls180.v:169249$11279 + assign { } { } + assign { } { } + assign $0\q_int$next[0:0]$11280 $1\q_int$next[0:0]$11281 + attribute \src "issuer_ls180.v:169250.5-169250.29" + switch \initial + attribute \src "issuer_ls180.v:169250.9-169250.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\q_int$next[0:0]$11281 1'0 + case + assign $1\q_int$next[0:0]$11281 \$5 + end + sync always + update \q_int$next $0\q_int$next[0:0]$11280 + end + connect \$9 $and$issuer_ls180.v:169239$11270_Y + connect \$11 $or$issuer_ls180.v:169240$11271_Y + connect \$13 $not$issuer_ls180.v:169241$11272_Y + connect \$15 $or$issuer_ls180.v:169242$11273_Y + connect \$1 $not$issuer_ls180.v:169243$11274_Y + connect \$3 $and$issuer_ls180.v:169244$11275_Y + connect \$5 $or$issuer_ls180.v:169245$11276_Y + connect \$7 $not$issuer_ls180.v:169246$11277_Y + connect \qlq_rst \$15 + connect \qn_rst \$13 + connect \q_rst \$11 +end +attribute \src "issuer_ls180.v:169265.1-169323.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.fus.shiftrot0.rst_l" +attribute \generator "nMigen" +module \rst_l$119 + attribute \src "issuer_ls180.v:169266.7-169266.20" + wire $0\initial[0:0] + attribute \src "issuer_ls180.v:169311.3-169319.6" + wire $0\q_int$next[0:0]$11294 + attribute \src "issuer_ls180.v:169309.3-169310.27" + wire $0\q_int[0:0] + attribute \src "issuer_ls180.v:169311.3-169319.6" + wire $1\q_int$next[0:0]$11295 + attribute \src "issuer_ls180.v:169288.7-169288.19" + wire $1\q_int[0:0] + attribute \src "issuer_ls180.v:169301.17-169301.96" + wire $and$issuer_ls180.v:169301$11284_Y + attribute \src "issuer_ls180.v:169306.17-169306.96" + wire $and$issuer_ls180.v:169306$11289_Y + attribute \src "issuer_ls180.v:169303.18-169303.93" + wire $not$issuer_ls180.v:169303$11286_Y + attribute \src "issuer_ls180.v:169305.17-169305.92" + wire $not$issuer_ls180.v:169305$11288_Y + attribute \src "issuer_ls180.v:169308.17-169308.92" + wire $not$issuer_ls180.v:169308$11291_Y + attribute \src "issuer_ls180.v:169302.18-169302.98" + wire $or$issuer_ls180.v:169302$11285_Y + attribute \src "issuer_ls180.v:169304.18-169304.99" + wire $or$issuer_ls180.v:169304$11287_Y + attribute \src "issuer_ls180.v:169307.17-169307.97" + wire $or$issuer_ls180.v:169307$11290_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire \$13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" + wire input 4 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" + wire input 1 \coresync_rst + attribute \src "issuer_ls180.v:169266.7-169266.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire \q_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" + wire \qlq_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + wire \qn_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire input 3 \r_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire input 2 \s_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $and $and$issuer_ls180.v:169301$11284 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$7 + connect \Y $and$issuer_ls180.v:169301$11284_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $and $and$issuer_ls180.v:169306$11289 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$1 + connect \Y $and$issuer_ls180.v:169306$11289_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + cell $not $not$issuer_ls180.v:169303$11286 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_rst + connect \Y $not$issuer_ls180.v:169303$11286_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $not $not$issuer_ls180.v:169305$11288 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_rst + connect \Y $not$issuer_ls180.v:169305$11288_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $not $not$issuer_ls180.v:169308$11291 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_rst + connect \Y $not$issuer_ls180.v:169308$11291_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $or $or$issuer_ls180.v:169302$11285 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$9 + connect \B \s_rst + connect \Y $or$issuer_ls180.v:169302$11285_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + cell $or $or$issuer_ls180.v:169304$11287 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_rst + connect \B \q_int + connect \Y $or$issuer_ls180.v:169304$11287_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $or $or$issuer_ls180.v:169307$11290 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$3 + connect \B \s_rst + connect \Y $or$issuer_ls180.v:169307$11290_Y + end + attribute \src "issuer_ls180.v:169266.7-169266.20" + process $proc$issuer_ls180.v:169266$11296 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "issuer_ls180.v:169288.7-169288.19" + process $proc$issuer_ls180.v:169288$11297 + assign { } { } + assign $1\q_int[0:0] 1'0 + sync always + sync init + update \q_int $1\q_int[0:0] + end + attribute \src "issuer_ls180.v:169309.3-169310.27" + process $proc$issuer_ls180.v:169309$11292 + assign { } { } + assign $0\q_int[0:0] \q_int$next + sync posedge \coresync_clk + update \q_int $0\q_int[0:0] + end + attribute \src "issuer_ls180.v:169311.3-169319.6" + process $proc$issuer_ls180.v:169311$11293 + assign { } { } + assign { } { } + assign $0\q_int$next[0:0]$11294 $1\q_int$next[0:0]$11295 + attribute \src "issuer_ls180.v:169312.5-169312.29" + switch \initial + attribute \src "issuer_ls180.v:169312.9-169312.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\q_int$next[0:0]$11295 1'0 + case + assign $1\q_int$next[0:0]$11295 \$5 + end + sync always + update \q_int$next $0\q_int$next[0:0]$11294 + end + connect \$9 $and$issuer_ls180.v:169301$11284_Y + connect \$11 $or$issuer_ls180.v:169302$11285_Y + connect \$13 $not$issuer_ls180.v:169303$11286_Y + connect \$15 $or$issuer_ls180.v:169304$11287_Y + connect \$1 $not$issuer_ls180.v:169305$11288_Y + connect \$3 $and$issuer_ls180.v:169306$11289_Y + connect \$5 $or$issuer_ls180.v:169307$11290_Y + connect \$7 $not$issuer_ls180.v:169308$11291_Y + connect \qlq_rst \$15 + connect \qn_rst \$13 + connect \q_rst \$11 +end +attribute \src "issuer_ls180.v:169327.1-169385.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.fus.ldst0.rst_l" +attribute \generator "nMigen" +module \rst_l$126 + attribute \src "issuer_ls180.v:169328.7-169328.20" + wire $0\initial[0:0] + attribute \src "issuer_ls180.v:169373.3-169381.6" + wire $0\q_int$next[0:0]$11308 + attribute \src "issuer_ls180.v:169371.3-169372.27" + wire $0\q_int[0:0] + attribute \src "issuer_ls180.v:169373.3-169381.6" + wire $1\q_int$next[0:0]$11309 + attribute \src "issuer_ls180.v:169350.7-169350.19" + wire $1\q_int[0:0] + attribute \src "issuer_ls180.v:169363.17-169363.96" + wire $and$issuer_ls180.v:169363$11298_Y + attribute \src "issuer_ls180.v:169368.17-169368.96" + wire $and$issuer_ls180.v:169368$11303_Y + attribute \src "issuer_ls180.v:169365.18-169365.93" + wire $not$issuer_ls180.v:169365$11300_Y + attribute \src "issuer_ls180.v:169367.17-169367.92" + wire $not$issuer_ls180.v:169367$11302_Y + attribute \src "issuer_ls180.v:169370.17-169370.92" + wire $not$issuer_ls180.v:169370$11305_Y + attribute \src "issuer_ls180.v:169364.18-169364.98" + wire $or$issuer_ls180.v:169364$11299_Y + attribute \src "issuer_ls180.v:169366.18-169366.99" + wire $or$issuer_ls180.v:169366$11301_Y + attribute \src "issuer_ls180.v:169369.17-169369.97" + wire $or$issuer_ls180.v:169369$11304_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire \$13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" + wire input 5 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" + wire input 1 \coresync_rst + attribute \src "issuer_ls180.v:169328.7-169328.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire output 4 \q_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" + wire \qlq_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + wire \qn_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire input 3 \r_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire input 2 \s_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $and $and$issuer_ls180.v:169363$11298 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$7 + connect \Y $and$issuer_ls180.v:169363$11298_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $and $and$issuer_ls180.v:169368$11303 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$1 + connect \Y $and$issuer_ls180.v:169368$11303_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + cell $not $not$issuer_ls180.v:169365$11300 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_rst + connect \Y $not$issuer_ls180.v:169365$11300_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $not $not$issuer_ls180.v:169367$11302 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_rst + connect \Y $not$issuer_ls180.v:169367$11302_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $not $not$issuer_ls180.v:169370$11305 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_rst + connect \Y $not$issuer_ls180.v:169370$11305_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $or $or$issuer_ls180.v:169364$11299 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$9 + connect \B \s_rst + connect \Y $or$issuer_ls180.v:169364$11299_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + cell $or $or$issuer_ls180.v:169366$11301 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_rst + connect \B \q_int + connect \Y $or$issuer_ls180.v:169366$11301_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $or $or$issuer_ls180.v:169369$11304 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$3 + connect \B \s_rst + connect \Y $or$issuer_ls180.v:169369$11304_Y + end + attribute \src "issuer_ls180.v:169328.7-169328.20" + process $proc$issuer_ls180.v:169328$11310 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "issuer_ls180.v:169350.7-169350.19" + process $proc$issuer_ls180.v:169350$11311 + assign { } { } + assign $1\q_int[0:0] 1'0 + sync always + sync init + update \q_int $1\q_int[0:0] + end + attribute \src "issuer_ls180.v:169371.3-169372.27" + process $proc$issuer_ls180.v:169371$11306 + assign { } { } + assign $0\q_int[0:0] \q_int$next + sync posedge \coresync_clk + update \q_int $0\q_int[0:0] + end + attribute \src "issuer_ls180.v:169373.3-169381.6" + process $proc$issuer_ls180.v:169373$11307 + assign { } { } + assign { } { } + assign $0\q_int$next[0:0]$11308 $1\q_int$next[0:0]$11309 + attribute \src "issuer_ls180.v:169374.5-169374.29" + switch \initial + attribute \src "issuer_ls180.v:169374.9-169374.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\q_int$next[0:0]$11309 1'0 + case + assign $1\q_int$next[0:0]$11309 \$5 + end + sync always + update \q_int$next $0\q_int$next[0:0]$11308 + end + connect \$9 $and$issuer_ls180.v:169363$11298_Y + connect \$11 $or$issuer_ls180.v:169364$11299_Y + connect \$13 $not$issuer_ls180.v:169365$11300_Y + connect \$15 $or$issuer_ls180.v:169366$11301_Y + connect \$1 $not$issuer_ls180.v:169367$11302_Y + connect \$3 $and$issuer_ls180.v:169368$11303_Y + connect \$5 $or$issuer_ls180.v:169369$11304_Y + connect \$7 $not$issuer_ls180.v:169370$11305_Y + connect \qlq_rst \$15 + connect \qn_rst \$13 + connect \q_rst \$11 +end +attribute \src "issuer_ls180.v:169389.1-169447.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.fus.cr0.rst_l" +attribute \generator "nMigen" +module \rst_l$13 + attribute \src "issuer_ls180.v:169390.7-169390.20" + wire $0\initial[0:0] + attribute \src "issuer_ls180.v:169435.3-169443.6" + wire $0\q_int$next[0:0]$11322 + attribute \src "issuer_ls180.v:169433.3-169434.27" + wire $0\q_int[0:0] + attribute \src "issuer_ls180.v:169435.3-169443.6" + wire $1\q_int$next[0:0]$11323 + attribute \src "issuer_ls180.v:169412.7-169412.19" + wire $1\q_int[0:0] + attribute \src "issuer_ls180.v:169425.17-169425.96" + wire $and$issuer_ls180.v:169425$11312_Y + attribute \src "issuer_ls180.v:169430.17-169430.96" + wire $and$issuer_ls180.v:169430$11317_Y + attribute \src "issuer_ls180.v:169427.18-169427.93" + wire $not$issuer_ls180.v:169427$11314_Y + attribute \src "issuer_ls180.v:169429.17-169429.92" + wire $not$issuer_ls180.v:169429$11316_Y + attribute \src "issuer_ls180.v:169432.17-169432.92" + wire $not$issuer_ls180.v:169432$11319_Y + attribute \src "issuer_ls180.v:169426.18-169426.98" + wire $or$issuer_ls180.v:169426$11313_Y + attribute \src "issuer_ls180.v:169428.18-169428.99" + wire $or$issuer_ls180.v:169428$11315_Y + attribute \src "issuer_ls180.v:169431.17-169431.97" + wire $or$issuer_ls180.v:169431$11318_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire \$13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" + wire input 4 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" + wire input 1 \coresync_rst + attribute \src "issuer_ls180.v:169390.7-169390.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire \q_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" + wire \qlq_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + wire \qn_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire input 3 \r_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire input 2 \s_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $and $and$issuer_ls180.v:169425$11312 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$7 + connect \Y $and$issuer_ls180.v:169425$11312_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $and $and$issuer_ls180.v:169430$11317 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$1 + connect \Y $and$issuer_ls180.v:169430$11317_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + cell $not $not$issuer_ls180.v:169427$11314 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_rst + connect \Y $not$issuer_ls180.v:169427$11314_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $not $not$issuer_ls180.v:169429$11316 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_rst + connect \Y $not$issuer_ls180.v:169429$11316_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $not $not$issuer_ls180.v:169432$11319 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_rst + connect \Y $not$issuer_ls180.v:169432$11319_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $or $or$issuer_ls180.v:169426$11313 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$9 + connect \B \s_rst + connect \Y $or$issuer_ls180.v:169426$11313_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + cell $or $or$issuer_ls180.v:169428$11315 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_rst + connect \B \q_int + connect \Y $or$issuer_ls180.v:169428$11315_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $or $or$issuer_ls180.v:169431$11318 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$3 + connect \B \s_rst + connect \Y $or$issuer_ls180.v:169431$11318_Y + end + attribute \src "issuer_ls180.v:169390.7-169390.20" + process $proc$issuer_ls180.v:169390$11324 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "issuer_ls180.v:169412.7-169412.19" + process $proc$issuer_ls180.v:169412$11325 + assign { } { } + assign $1\q_int[0:0] 1'0 + sync always + sync init + update \q_int $1\q_int[0:0] + end + attribute \src "issuer_ls180.v:169433.3-169434.27" + process $proc$issuer_ls180.v:169433$11320 + assign { } { } + assign $0\q_int[0:0] \q_int$next + sync posedge \coresync_clk + update \q_int $0\q_int[0:0] + end + attribute \src "issuer_ls180.v:169435.3-169443.6" + process $proc$issuer_ls180.v:169435$11321 + assign { } { } + assign { } { } + assign $0\q_int$next[0:0]$11322 $1\q_int$next[0:0]$11323 + attribute \src "issuer_ls180.v:169436.5-169436.29" + switch \initial + attribute \src "issuer_ls180.v:169436.9-169436.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\q_int$next[0:0]$11323 1'0 + case + assign $1\q_int$next[0:0]$11323 \$5 + end + sync always + update \q_int$next $0\q_int$next[0:0]$11322 + end + connect \$9 $and$issuer_ls180.v:169425$11312_Y + connect \$11 $or$issuer_ls180.v:169426$11313_Y + connect \$13 $not$issuer_ls180.v:169427$11314_Y + connect \$15 $or$issuer_ls180.v:169428$11315_Y + connect \$1 $not$issuer_ls180.v:169429$11316_Y + connect \$3 $and$issuer_ls180.v:169430$11317_Y + connect \$5 $or$issuer_ls180.v:169431$11318_Y + connect \$7 $not$issuer_ls180.v:169432$11319_Y + connect \qlq_rst \$15 + connect \qn_rst \$13 + connect \q_rst \$11 +end +attribute \src "issuer_ls180.v:169451.1-169509.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.fus.branch0.rst_l" +attribute \generator "nMigen" +module \rst_l$26 + attribute \src "issuer_ls180.v:169452.7-169452.20" + wire $0\initial[0:0] + attribute \src "issuer_ls180.v:169497.3-169505.6" + wire $0\q_int$next[0:0]$11336 + attribute \src "issuer_ls180.v:169495.3-169496.27" + wire $0\q_int[0:0] + attribute \src "issuer_ls180.v:169497.3-169505.6" + wire $1\q_int$next[0:0]$11337 + attribute \src "issuer_ls180.v:169474.7-169474.19" + wire $1\q_int[0:0] + attribute \src "issuer_ls180.v:169487.17-169487.96" + wire $and$issuer_ls180.v:169487$11326_Y + attribute \src "issuer_ls180.v:169492.17-169492.96" + wire $and$issuer_ls180.v:169492$11331_Y + attribute \src "issuer_ls180.v:169489.18-169489.93" + wire $not$issuer_ls180.v:169489$11328_Y + attribute \src "issuer_ls180.v:169491.17-169491.92" + wire $not$issuer_ls180.v:169491$11330_Y + attribute \src "issuer_ls180.v:169494.17-169494.92" + wire $not$issuer_ls180.v:169494$11333_Y + attribute \src "issuer_ls180.v:169488.18-169488.98" + wire $or$issuer_ls180.v:169488$11327_Y + attribute \src "issuer_ls180.v:169490.18-169490.99" + wire $or$issuer_ls180.v:169490$11329_Y + attribute \src "issuer_ls180.v:169493.17-169493.97" + wire $or$issuer_ls180.v:169493$11332_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire \$13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" + wire input 4 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" + wire input 1 \coresync_rst + attribute \src "issuer_ls180.v:169452.7-169452.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire \q_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" + wire \qlq_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + wire \qn_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire input 3 \r_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire input 2 \s_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $and $and$issuer_ls180.v:169487$11326 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$7 + connect \Y $and$issuer_ls180.v:169487$11326_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $and $and$issuer_ls180.v:169492$11331 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$1 + connect \Y $and$issuer_ls180.v:169492$11331_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + cell $not $not$issuer_ls180.v:169489$11328 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_rst + connect \Y $not$issuer_ls180.v:169489$11328_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $not $not$issuer_ls180.v:169491$11330 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_rst + connect \Y $not$issuer_ls180.v:169491$11330_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $not $not$issuer_ls180.v:169494$11333 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_rst + connect \Y $not$issuer_ls180.v:169494$11333_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $or $or$issuer_ls180.v:169488$11327 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$9 + connect \B \s_rst + connect \Y $or$issuer_ls180.v:169488$11327_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + cell $or $or$issuer_ls180.v:169490$11329 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_rst + connect \B \q_int + connect \Y $or$issuer_ls180.v:169490$11329_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $or $or$issuer_ls180.v:169493$11332 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$3 + connect \B \s_rst + connect \Y $or$issuer_ls180.v:169493$11332_Y + end + attribute \src "issuer_ls180.v:169452.7-169452.20" + process $proc$issuer_ls180.v:169452$11338 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "issuer_ls180.v:169474.7-169474.19" + process $proc$issuer_ls180.v:169474$11339 + assign { } { } + assign $1\q_int[0:0] 1'0 + sync always + sync init + update \q_int $1\q_int[0:0] + end + attribute \src "issuer_ls180.v:169495.3-169496.27" + process $proc$issuer_ls180.v:169495$11334 + assign { } { } + assign $0\q_int[0:0] \q_int$next + sync posedge \coresync_clk + update \q_int $0\q_int[0:0] + end + attribute \src "issuer_ls180.v:169497.3-169505.6" + process $proc$issuer_ls180.v:169497$11335 + assign { } { } + assign { } { } + assign $0\q_int$next[0:0]$11336 $1\q_int$next[0:0]$11337 + attribute \src "issuer_ls180.v:169498.5-169498.29" + switch \initial + attribute \src "issuer_ls180.v:169498.9-169498.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\q_int$next[0:0]$11337 1'0 + case + assign $1\q_int$next[0:0]$11337 \$5 + end + sync always + update \q_int$next $0\q_int$next[0:0]$11336 + end + connect \$9 $and$issuer_ls180.v:169487$11326_Y + connect \$11 $or$issuer_ls180.v:169488$11327_Y + connect \$13 $not$issuer_ls180.v:169489$11328_Y + connect \$15 $or$issuer_ls180.v:169490$11329_Y + connect \$1 $not$issuer_ls180.v:169491$11330_Y + connect \$3 $and$issuer_ls180.v:169492$11331_Y + connect \$5 $or$issuer_ls180.v:169493$11332_Y + connect \$7 $not$issuer_ls180.v:169494$11333_Y + connect \qlq_rst \$15 + connect \qn_rst \$13 + connect \q_rst \$11 +end +attribute \src "issuer_ls180.v:169513.1-169571.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.fus.trap0.rst_l" +attribute \generator "nMigen" +module \rst_l$39 + attribute \src "issuer_ls180.v:169514.7-169514.20" + wire $0\initial[0:0] + attribute \src "issuer_ls180.v:169559.3-169567.6" + wire $0\q_int$next[0:0]$11350 + attribute \src "issuer_ls180.v:169557.3-169558.27" + wire $0\q_int[0:0] + attribute \src "issuer_ls180.v:169559.3-169567.6" + wire $1\q_int$next[0:0]$11351 + attribute \src "issuer_ls180.v:169536.7-169536.19" + wire $1\q_int[0:0] + attribute \src "issuer_ls180.v:169549.17-169549.96" + wire $and$issuer_ls180.v:169549$11340_Y + attribute \src "issuer_ls180.v:169554.17-169554.96" + wire $and$issuer_ls180.v:169554$11345_Y + attribute \src "issuer_ls180.v:169551.18-169551.93" + wire $not$issuer_ls180.v:169551$11342_Y + attribute \src "issuer_ls180.v:169553.17-169553.92" + wire $not$issuer_ls180.v:169553$11344_Y + attribute \src "issuer_ls180.v:169556.17-169556.92" + wire $not$issuer_ls180.v:169556$11347_Y + attribute \src "issuer_ls180.v:169550.18-169550.98" + wire $or$issuer_ls180.v:169550$11341_Y + attribute \src "issuer_ls180.v:169552.18-169552.99" + wire $or$issuer_ls180.v:169552$11343_Y + attribute \src "issuer_ls180.v:169555.17-169555.97" + wire $or$issuer_ls180.v:169555$11346_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire \$13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" + wire input 4 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" + wire input 1 \coresync_rst + attribute \src "issuer_ls180.v:169514.7-169514.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire \q_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" + wire \qlq_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + wire \qn_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire input 3 \r_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire input 2 \s_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $and $and$issuer_ls180.v:169549$11340 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$7 + connect \Y $and$issuer_ls180.v:169549$11340_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $and $and$issuer_ls180.v:169554$11345 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$1 + connect \Y $and$issuer_ls180.v:169554$11345_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + cell $not $not$issuer_ls180.v:169551$11342 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_rst + connect \Y $not$issuer_ls180.v:169551$11342_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $not $not$issuer_ls180.v:169553$11344 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_rst + connect \Y $not$issuer_ls180.v:169553$11344_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $not $not$issuer_ls180.v:169556$11347 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_rst + connect \Y $not$issuer_ls180.v:169556$11347_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $or $or$issuer_ls180.v:169550$11341 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$9 + connect \B \s_rst + connect \Y $or$issuer_ls180.v:169550$11341_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + cell $or $or$issuer_ls180.v:169552$11343 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_rst + connect \B \q_int + connect \Y $or$issuer_ls180.v:169552$11343_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $or $or$issuer_ls180.v:169555$11346 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$3 + connect \B \s_rst + connect \Y $or$issuer_ls180.v:169555$11346_Y + end + attribute \src "issuer_ls180.v:169514.7-169514.20" + process $proc$issuer_ls180.v:169514$11352 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "issuer_ls180.v:169536.7-169536.19" + process $proc$issuer_ls180.v:169536$11353 + assign { } { } + assign $1\q_int[0:0] 1'0 + sync always + sync init + update \q_int $1\q_int[0:0] + end + attribute \src "issuer_ls180.v:169557.3-169558.27" + process $proc$issuer_ls180.v:169557$11348 + assign { } { } + assign $0\q_int[0:0] \q_int$next + sync posedge \coresync_clk + update \q_int $0\q_int[0:0] + end + attribute \src "issuer_ls180.v:169559.3-169567.6" + process $proc$issuer_ls180.v:169559$11349 + assign { } { } + assign { } { } + assign $0\q_int$next[0:0]$11350 $1\q_int$next[0:0]$11351 + attribute \src "issuer_ls180.v:169560.5-169560.29" + switch \initial + attribute \src "issuer_ls180.v:169560.9-169560.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\q_int$next[0:0]$11351 1'0 + case + assign $1\q_int$next[0:0]$11351 \$5 + end + sync always + update \q_int$next $0\q_int$next[0:0]$11350 + end + connect \$9 $and$issuer_ls180.v:169549$11340_Y + connect \$11 $or$issuer_ls180.v:169550$11341_Y + connect \$13 $not$issuer_ls180.v:169551$11342_Y + connect \$15 $or$issuer_ls180.v:169552$11343_Y + connect \$1 $not$issuer_ls180.v:169553$11344_Y + connect \$3 $and$issuer_ls180.v:169554$11345_Y + connect \$5 $or$issuer_ls180.v:169555$11346_Y + connect \$7 $not$issuer_ls180.v:169556$11347_Y + connect \qlq_rst \$15 + connect \qn_rst \$13 + connect \q_rst \$11 +end +attribute \src "issuer_ls180.v:169575.1-169633.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.fus.logical0.rst_l" +attribute \generator "nMigen" +module \rst_l$55 + attribute \src "issuer_ls180.v:169576.7-169576.20" + wire $0\initial[0:0] + attribute \src "issuer_ls180.v:169621.3-169629.6" + wire $0\q_int$next[0:0]$11364 + attribute \src "issuer_ls180.v:169619.3-169620.27" + wire $0\q_int[0:0] + attribute \src "issuer_ls180.v:169621.3-169629.6" + wire $1\q_int$next[0:0]$11365 + attribute \src "issuer_ls180.v:169598.7-169598.19" + wire $1\q_int[0:0] + attribute \src "issuer_ls180.v:169611.17-169611.96" + wire $and$issuer_ls180.v:169611$11354_Y + attribute \src "issuer_ls180.v:169616.17-169616.96" + wire $and$issuer_ls180.v:169616$11359_Y + attribute \src "issuer_ls180.v:169613.18-169613.93" + wire $not$issuer_ls180.v:169613$11356_Y + attribute \src "issuer_ls180.v:169615.17-169615.92" + wire $not$issuer_ls180.v:169615$11358_Y + attribute \src "issuer_ls180.v:169618.17-169618.92" + wire $not$issuer_ls180.v:169618$11361_Y + attribute \src "issuer_ls180.v:169612.18-169612.98" + wire $or$issuer_ls180.v:169612$11355_Y + attribute \src "issuer_ls180.v:169614.18-169614.99" + wire $or$issuer_ls180.v:169614$11357_Y + attribute \src "issuer_ls180.v:169617.17-169617.97" + wire $or$issuer_ls180.v:169617$11360_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire \$13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" + wire input 4 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" + wire input 1 \coresync_rst + attribute \src "issuer_ls180.v:169576.7-169576.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire \q_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" + wire \qlq_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + wire \qn_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire input 3 \r_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire input 2 \s_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $and $and$issuer_ls180.v:169611$11354 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$7 + connect \Y $and$issuer_ls180.v:169611$11354_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $and $and$issuer_ls180.v:169616$11359 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$1 + connect \Y $and$issuer_ls180.v:169616$11359_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + cell $not $not$issuer_ls180.v:169613$11356 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_rst + connect \Y $not$issuer_ls180.v:169613$11356_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $not $not$issuer_ls180.v:169615$11358 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_rst + connect \Y $not$issuer_ls180.v:169615$11358_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $not $not$issuer_ls180.v:169618$11361 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_rst + connect \Y $not$issuer_ls180.v:169618$11361_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $or $or$issuer_ls180.v:169612$11355 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$9 + connect \B \s_rst + connect \Y $or$issuer_ls180.v:169612$11355_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + cell $or $or$issuer_ls180.v:169614$11357 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_rst + connect \B \q_int + connect \Y $or$issuer_ls180.v:169614$11357_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $or $or$issuer_ls180.v:169617$11360 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$3 + connect \B \s_rst + connect \Y $or$issuer_ls180.v:169617$11360_Y + end + attribute \src "issuer_ls180.v:169576.7-169576.20" + process $proc$issuer_ls180.v:169576$11366 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "issuer_ls180.v:169598.7-169598.19" + process $proc$issuer_ls180.v:169598$11367 + assign { } { } + assign $1\q_int[0:0] 1'0 + sync always + sync init + update \q_int $1\q_int[0:0] + end + attribute \src "issuer_ls180.v:169619.3-169620.27" + process $proc$issuer_ls180.v:169619$11362 + assign { } { } + assign $0\q_int[0:0] \q_int$next + sync posedge \coresync_clk + update \q_int $0\q_int[0:0] + end + attribute \src "issuer_ls180.v:169621.3-169629.6" + process $proc$issuer_ls180.v:169621$11363 + assign { } { } + assign { } { } + assign $0\q_int$next[0:0]$11364 $1\q_int$next[0:0]$11365 + attribute \src "issuer_ls180.v:169622.5-169622.29" + switch \initial + attribute \src "issuer_ls180.v:169622.9-169622.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\q_int$next[0:0]$11365 1'0 + case + assign $1\q_int$next[0:0]$11365 \$5 + end + sync always + update \q_int$next $0\q_int$next[0:0]$11364 + end + connect \$9 $and$issuer_ls180.v:169611$11354_Y + connect \$11 $or$issuer_ls180.v:169612$11355_Y + connect \$13 $not$issuer_ls180.v:169613$11356_Y + connect \$15 $or$issuer_ls180.v:169614$11357_Y + connect \$1 $not$issuer_ls180.v:169615$11358_Y + connect \$3 $and$issuer_ls180.v:169616$11359_Y + connect \$5 $or$issuer_ls180.v:169617$11360_Y + connect \$7 $not$issuer_ls180.v:169618$11361_Y + connect \qlq_rst \$15 + connect \qn_rst \$13 + connect \q_rst \$11 +end +attribute \src "issuer_ls180.v:169637.1-169695.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.fus.spr0.rst_l" +attribute \generator "nMigen" +module \rst_l$67 + attribute \src "issuer_ls180.v:169638.7-169638.20" + wire $0\initial[0:0] + attribute \src "issuer_ls180.v:169683.3-169691.6" + wire $0\q_int$next[0:0]$11378 + attribute \src "issuer_ls180.v:169681.3-169682.27" + wire $0\q_int[0:0] + attribute \src "issuer_ls180.v:169683.3-169691.6" + wire $1\q_int$next[0:0]$11379 + attribute \src "issuer_ls180.v:169660.7-169660.19" + wire $1\q_int[0:0] + attribute \src "issuer_ls180.v:169673.17-169673.96" + wire $and$issuer_ls180.v:169673$11368_Y + attribute \src "issuer_ls180.v:169678.17-169678.96" + wire $and$issuer_ls180.v:169678$11373_Y + attribute \src "issuer_ls180.v:169675.18-169675.93" + wire $not$issuer_ls180.v:169675$11370_Y + attribute \src "issuer_ls180.v:169677.17-169677.92" + wire $not$issuer_ls180.v:169677$11372_Y + attribute \src "issuer_ls180.v:169680.17-169680.92" + wire $not$issuer_ls180.v:169680$11375_Y + attribute \src "issuer_ls180.v:169674.18-169674.98" + wire $or$issuer_ls180.v:169674$11369_Y + attribute \src "issuer_ls180.v:169676.18-169676.99" + wire $or$issuer_ls180.v:169676$11371_Y + attribute \src "issuer_ls180.v:169679.17-169679.97" + wire $or$issuer_ls180.v:169679$11374_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire \$13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" + wire input 4 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" + wire input 1 \coresync_rst + attribute \src "issuer_ls180.v:169638.7-169638.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire \q_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" + wire \qlq_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + wire \qn_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire input 3 \r_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire input 2 \s_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $and $and$issuer_ls180.v:169673$11368 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$7 + connect \Y $and$issuer_ls180.v:169673$11368_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $and $and$issuer_ls180.v:169678$11373 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$1 + connect \Y $and$issuer_ls180.v:169678$11373_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + cell $not $not$issuer_ls180.v:169675$11370 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_rst + connect \Y $not$issuer_ls180.v:169675$11370_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $not $not$issuer_ls180.v:169677$11372 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_rst + connect \Y $not$issuer_ls180.v:169677$11372_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $not $not$issuer_ls180.v:169680$11375 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_rst + connect \Y $not$issuer_ls180.v:169680$11375_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $or $or$issuer_ls180.v:169674$11369 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$9 + connect \B \s_rst + connect \Y $or$issuer_ls180.v:169674$11369_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + cell $or $or$issuer_ls180.v:169676$11371 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_rst + connect \B \q_int + connect \Y $or$issuer_ls180.v:169676$11371_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $or $or$issuer_ls180.v:169679$11374 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$3 + connect \B \s_rst + connect \Y $or$issuer_ls180.v:169679$11374_Y + end + attribute \src "issuer_ls180.v:169638.7-169638.20" + process $proc$issuer_ls180.v:169638$11380 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "issuer_ls180.v:169660.7-169660.19" + process $proc$issuer_ls180.v:169660$11381 + assign { } { } + assign $1\q_int[0:0] 1'0 + sync always + sync init + update \q_int $1\q_int[0:0] + end + attribute \src "issuer_ls180.v:169681.3-169682.27" + process $proc$issuer_ls180.v:169681$11376 + assign { } { } + assign $0\q_int[0:0] \q_int$next + sync posedge \coresync_clk + update \q_int $0\q_int[0:0] + end + attribute \src "issuer_ls180.v:169683.3-169691.6" + process $proc$issuer_ls180.v:169683$11377 + assign { } { } + assign { } { } + assign $0\q_int$next[0:0]$11378 $1\q_int$next[0:0]$11379 + attribute \src "issuer_ls180.v:169684.5-169684.29" + switch \initial + attribute \src "issuer_ls180.v:169684.9-169684.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\q_int$next[0:0]$11379 1'0 + case + assign $1\q_int$next[0:0]$11379 \$5 + end + sync always + update \q_int$next $0\q_int$next[0:0]$11378 + end + connect \$9 $and$issuer_ls180.v:169673$11368_Y + connect \$11 $or$issuer_ls180.v:169674$11369_Y + connect \$13 $not$issuer_ls180.v:169675$11370_Y + connect \$15 $or$issuer_ls180.v:169676$11371_Y + connect \$1 $not$issuer_ls180.v:169677$11372_Y + connect \$3 $and$issuer_ls180.v:169678$11373_Y + connect \$5 $or$issuer_ls180.v:169679$11374_Y + connect \$7 $not$issuer_ls180.v:169680$11375_Y + connect \qlq_rst \$15 + connect \qn_rst \$13 + connect \q_rst \$11 +end +attribute \src "issuer_ls180.v:169699.1-169757.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.rst_l" +attribute \generator "nMigen" +module \rst_l$84 + attribute \src "issuer_ls180.v:169700.7-169700.20" + wire $0\initial[0:0] + attribute \src "issuer_ls180.v:169745.3-169753.6" + wire $0\q_int$next[0:0]$11392 + attribute \src "issuer_ls180.v:169743.3-169744.27" + wire $0\q_int[0:0] + attribute \src "issuer_ls180.v:169745.3-169753.6" + wire $1\q_int$next[0:0]$11393 + attribute \src "issuer_ls180.v:169722.7-169722.19" + wire $1\q_int[0:0] + attribute \src "issuer_ls180.v:169735.17-169735.96" + wire $and$issuer_ls180.v:169735$11382_Y + attribute \src "issuer_ls180.v:169740.17-169740.96" + wire $and$issuer_ls180.v:169740$11387_Y + attribute \src "issuer_ls180.v:169737.18-169737.93" + wire $not$issuer_ls180.v:169737$11384_Y + attribute \src "issuer_ls180.v:169739.17-169739.92" + wire $not$issuer_ls180.v:169739$11386_Y + attribute \src "issuer_ls180.v:169742.17-169742.92" + wire $not$issuer_ls180.v:169742$11389_Y + attribute \src "issuer_ls180.v:169736.18-169736.98" + wire $or$issuer_ls180.v:169736$11383_Y + attribute \src "issuer_ls180.v:169738.18-169738.99" + wire $or$issuer_ls180.v:169738$11385_Y + attribute \src "issuer_ls180.v:169741.17-169741.97" + wire $or$issuer_ls180.v:169741$11388_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire \$13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" + wire input 4 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" + wire input 1 \coresync_rst + attribute \src "issuer_ls180.v:169700.7-169700.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire \q_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" + wire \qlq_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + wire \qn_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire input 3 \r_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire input 2 \s_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $and $and$issuer_ls180.v:169735$11382 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$7 + connect \Y $and$issuer_ls180.v:169735$11382_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $and $and$issuer_ls180.v:169740$11387 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$1 + connect \Y $and$issuer_ls180.v:169740$11387_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + cell $not $not$issuer_ls180.v:169737$11384 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_rst + connect \Y $not$issuer_ls180.v:169737$11384_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $not $not$issuer_ls180.v:169739$11386 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_rst + connect \Y $not$issuer_ls180.v:169739$11386_Y + end + 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"OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 input 1 \logical_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 output 23 \logical_op__insn_type$2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 9 \logical_op__invert_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 31 \logical_op__invert_in$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 12 \logical_op__invert_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 34 \logical_op__invert_out$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 15 \logical_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 37 \logical_op__is_32bit$16 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 16 \logical_op__is_signed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 38 \logical_op__is_signed$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 7 \logical_op__oe__oe + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 29 \logical_op__oe__oe$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 8 \logical_op__oe__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 30 \logical_op__oe__ok$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 14 \logical_op__output_carry + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 36 \logical_op__output_carry$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 6 \logical_op__rc__ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 28 \logical_op__rc__ok$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 5 \logical_op__rc__rc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 27 \logical_op__rc__rc$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 13 \logical_op__write_cr0 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 35 \logical_op__write_cr0$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 10 \logical_op__zero_a + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 32 \logical_op__zero_a$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 input 50 \muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 output 22 \muxid$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:21" + wire width 2 output 49 \operation + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 19 \ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 20 \rb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire input 21 \xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire output 41 \xer_so$20 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:45" + cell $and $and$issuer_ls180.v:170101$11397 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$21 + connect \B \logical_op__is_signed + connect \Y $and$issuer_ls180.v:170101$11397_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:46" + cell $and $and$issuer_ls180.v:170103$11399 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$25 + connect \B \logical_op__is_signed + connect \Y $and$issuer_ls180.v:170103$11399_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:58" + cell $and $and$issuer_ls180.v:170112$11412 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$43 + connect \B \$45 + connect \Y $and$issuer_ls180.v:170112$11412_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:61" + cell $and $and$issuer_ls180.v:170115$11415 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$49 + connect \B \$51 + connect \Y $and$issuer_ls180.v:170115$11415_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:58" + cell $eq $eq$issuer_ls180.v:170111$11411 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \logical_op__insn_type + connect \B 7'0011110 + connect \Y $eq$issuer_ls180.v:170111$11411_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:61" + cell $eq $eq$issuer_ls180.v:170114$11414 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \logical_op__insn_type + connect \B 7'0011110 + connect \Y $eq$issuer_ls180.v:170114$11414_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:67" + cell $eq $eq$issuer_ls180.v:170117$11417 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \divisor_radicand + connect \B 1'0 + connect \Y $eq$issuer_ls180.v:170117$11417_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:53" + cell $pos $extend$issuer_ls180.v:170104$11400 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 65 + connect \A \rb + connect \Y $extend$issuer_ls180.v:170104$11400_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + cell $pos $extend$issuer_ls180.v:170105$11402 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 65 + connect \A \rb + connect \Y $extend$issuer_ls180.v:170105$11402_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:54" + cell $pos $extend$issuer_ls180.v:170107$11405 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 65 + connect \A \ra + connect \Y $extend$issuer_ls180.v:170107$11405_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + cell $pos $extend$issuer_ls180.v:170108$11407 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 65 + connect \A \ra + connect \Y $extend$issuer_ls180.v:170108$11407_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:79" + cell $pos $extend$issuer_ls180.v:170120$11420 + parameter \A_SIGNED 0 + parameter \A_WIDTH 95 + parameter \Y_WIDTH 128 + connect \A \$62 + connect \Y $extend$issuer_ls180.v:170120$11420_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:57" + cell $ge $ge$issuer_ls180.v:170110$11410 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 64 + parameter \Y_WIDTH 1 + connect \A \abs_dend + connect \B \abs_dor + connect \Y $ge$issuer_ls180.v:170110$11410_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:60" + cell $ge $ge$issuer_ls180.v:170113$11413 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 32 + parameter \Y_WIDTH 1 + connect \A \abs_dend [31:0] + connect \B \abs_dor [31:0] + connect \Y $ge$issuer_ls180.v:170113$11413_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:53" + cell $neg $neg$issuer_ls180.v:170104$11401 + parameter \A_SIGNED 0 + parameter \A_WIDTH 65 + parameter \Y_WIDTH 65 + connect \A $extend$issuer_ls180.v:170104$11400_Y + connect \Y $neg$issuer_ls180.v:170104$11401_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:54" + cell $neg $neg$issuer_ls180.v:170107$11406 + parameter \A_SIGNED 0 + parameter \A_WIDTH 65 + parameter \Y_WIDTH 65 + connect \A $extend$issuer_ls180.v:170107$11405_Y + connect \Y $neg$issuer_ls180.v:170107$11406_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + cell $pos $pos$issuer_ls180.v:170105$11403 + parameter \A_SIGNED 0 + parameter \A_WIDTH 65 + parameter \Y_WIDTH 65 + connect \A $extend$issuer_ls180.v:170105$11402_Y + connect \Y $pos$issuer_ls180.v:170105$11403_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + cell $pos $pos$issuer_ls180.v:170108$11408 + parameter \A_SIGNED 0 + parameter \A_WIDTH 65 + parameter \Y_WIDTH 65 + connect \A $extend$issuer_ls180.v:170108$11407_Y + connect \Y $pos$issuer_ls180.v:170108$11408_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:79" + cell $pos $pos$issuer_ls180.v:170120$11421 + parameter \A_SIGNED 0 + parameter \A_WIDTH 128 + parameter \Y_WIDTH 128 + connect \A $extend$issuer_ls180.v:170120$11420_Y + connect \Y $pos$issuer_ls180.v:170120$11421_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:79" + cell $sshl $sshl$issuer_ls180.v:170119$11419 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 95 + connect \A \abs_dend [31:0] + connect \B 6'100000 + connect \Y $sshl$issuer_ls180.v:170119$11419_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:81" + cell $sshl $sshl$issuer_ls180.v:170121$11422 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 191 + connect \A \abs_dend + connect \B 7'1000000 + connect \Y $sshl$issuer_ls180.v:170121$11422_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:45" + cell $mux $ternary$issuer_ls180.v:170100$11396 + parameter \WIDTH 1 + connect \A \ra [63] + connect \B \ra [31] + connect \S \logical_op__is_32bit + connect \Y $ternary$issuer_ls180.v:170100$11396_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:46" + cell $mux $ternary$issuer_ls180.v:170102$11398 + parameter \WIDTH 1 + connect \A \rb [63] + connect \B \rb [31] + connect \S \logical_op__is_32bit + connect \Y $ternary$issuer_ls180.v:170102$11398_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:53" + cell $mux $ternary$issuer_ls180.v:170106$11404 + parameter \WIDTH 65 + connect \A \$32 + connect \B \$30 + connect \S \divisor_neg + connect \Y $ternary$issuer_ls180.v:170106$11404_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:54" + cell $mux $ternary$issuer_ls180.v:170109$11409 + parameter \WIDTH 65 + connect \A \$39 + connect \B \$37 + connect \S \dividend_neg + connect \Y $ternary$issuer_ls180.v:170109$11409_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:34" + cell $mux $ternary$issuer_ls180.v:170116$11416 + parameter \WIDTH 32 + connect \A \abs_dor [63:32] + connect \B 0 + connect \S \logical_op__is_32bit + connect \Y $ternary$issuer_ls180.v:170116$11416_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:34" + cell $mux $ternary$issuer_ls180.v:170118$11418 + parameter \WIDTH 32 + connect \A \abs_dend [63:32] + connect \B 0 + connect \S \logical_op__is_32bit + connect \Y $ternary$issuer_ls180.v:170118$11418_Y + end + attribute \src "issuer_ls180.v:169762.7-169762.20" + process $proc$issuer_ls180.v:169762$11424 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "issuer_ls180.v:170122.3-170147.6" + process $proc$issuer_ls180.v:170122$11423 + assign { } { } + assign { } { } + assign $0\dividend[127:0] $1\dividend[127:0] + attribute \src "issuer_ls180.v:170123.5-170123.29" + switch \initial + attribute \src "issuer_ls180.v:170123.9-170123.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:72" + switch \logical_op__insn_type + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'0011101 , 7'0101111 + assign $1\dividend[127:0] [127:64] 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $1\dividend[127:0] [31:0] \abs_dend [31:0] + assign $1\dividend[127:0] [63:32] \$59 + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'0011110 + assign { } { } + assign $1\dividend[127:0] $2\dividend[127:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:78" + switch \logical_op__is_32bit + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\dividend[127:0] \$61 + attribute \src "issuer_ls180.v:0.0-0.0" + case + assign { } { } + assign $2\dividend[127:0] \$65 [127:0] + end + case + assign $1\dividend[127:0] 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \dividend $0\dividend[127:0] + end + connect \$21 $ternary$issuer_ls180.v:170100$11396_Y + connect \$23 $and$issuer_ls180.v:170101$11397_Y + connect \$25 $ternary$issuer_ls180.v:170102$11398_Y + connect \$27 $and$issuer_ls180.v:170103$11399_Y + connect \$30 $neg$issuer_ls180.v:170104$11401_Y + connect \$32 $pos$issuer_ls180.v:170105$11403_Y + connect \$34 $ternary$issuer_ls180.v:170106$11404_Y + connect \$37 $neg$issuer_ls180.v:170107$11406_Y + connect \$39 $pos$issuer_ls180.v:170108$11408_Y + connect \$41 $ternary$issuer_ls180.v:170109$11409_Y + connect \$43 $ge$issuer_ls180.v:170110$11410_Y + connect \$45 $eq$issuer_ls180.v:170111$11411_Y + connect \$47 $and$issuer_ls180.v:170112$11412_Y + connect \$49 $ge$issuer_ls180.v:170113$11413_Y + connect \$51 $eq$issuer_ls180.v:170114$11414_Y + connect \$53 $and$issuer_ls180.v:170115$11415_Y + connect \$55 $ternary$issuer_ls180.v:170116$11416_Y + connect \$57 $eq$issuer_ls180.v:170117$11417_Y + connect \$59 $ternary$issuer_ls180.v:170118$11418_Y + connect \$62 $sshl$issuer_ls180.v:170119$11419_Y + connect \$61 $pos$issuer_ls180.v:170120$11421_Y + connect \$66 $sshl$issuer_ls180.v:170121$11422_Y + connect \$29 \$34 + connect \$36 \$41 + connect \$65 \$66 + connect { \logical_op__insn$19 \logical_op__data_len$18 \logical_op__is_signed$17 \logical_op__is_32bit$16 \logical_op__output_carry$15 \logical_op__write_cr0$14 \logical_op__invert_out$13 \logical_op__input_carry$12 \logical_op__zero_a$11 \logical_op__invert_in$10 \logical_op__oe__ok$9 \logical_op__oe__oe$8 \logical_op__rc__ok$7 \logical_op__rc__rc$6 \logical_op__imm_data__ok$5 \logical_op__imm_data__data$4 \logical_op__fn_unit$3 \logical_op__insn_type$2 } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in \logical_op__oe__ok \logical_op__oe__oe \logical_op__rc__ok \logical_op__rc__rc \logical_op__imm_data__ok \logical_op__imm_data__data \logical_op__fn_unit \logical_op__insn_type } + connect \muxid$1 \muxid + connect \xer_so$20 \xer_so + connect \div_by_zero \$57 + connect \divisor_radicand [63:32] \$55 + connect \divisor_radicand [31:0] \abs_dor [31:0] + connect \dive_abs_ov32 \$53 + connect \dive_abs_ov64 \$47 + connect \abs_dend \$41 [63:0] + connect \abs_dor \$34 [63:0] + connect \divisor_neg \$27 + connect \dividend_neg \$23 + connect \operation 2'01 +end +attribute \src "issuer_ls180.v:170168.1-171359.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.fus.shiftrot0" +attribute \generator "nMigen" +module \shiftrot0 + attribute \src "issuer_ls180.v:170932.3-170933.25" + wire $0\all_rd_dly[0:0] + attribute \src "issuer_ls180.v:170930.3-170931.46" + wire $0\alu_done_dly[0:0] + attribute \src "issuer_ls180.v:171279.3-171287.6" + wire $0\alu_l_r_alu$next[0:0]$11639 + attribute \src "issuer_ls180.v:170850.3-170851.39" + wire $0\alu_l_r_alu[0:0] + attribute \src "issuer_ls180.v:171117.3-171153.6" + wire width 12 $0\alu_shift_rot0_sr_op__fn_unit$next[11:0]$11558 + attribute \src "issuer_ls180.v:170878.3-170879.75" + wire width 12 $0\alu_shift_rot0_sr_op__fn_unit[11:0] + attribute \src "issuer_ls180.v:171117.3-171153.6" + wire width 64 $0\alu_shift_rot0_sr_op__imm_data__data$next[63:0]$11559 + attribute \src "issuer_ls180.v:170880.3-170881.89" + wire width 64 $0\alu_shift_rot0_sr_op__imm_data__data[63:0] + attribute \src "issuer_ls180.v:171117.3-171153.6" + wire $0\alu_shift_rot0_sr_op__imm_data__ok$next[0:0]$11560 + attribute \src "issuer_ls180.v:170882.3-170883.85" + wire $0\alu_shift_rot0_sr_op__imm_data__ok[0:0] + attribute \src "issuer_ls180.v:171117.3-171153.6" + wire width 2 $0\alu_shift_rot0_sr_op__input_carry$next[1:0]$11561 + attribute \src "issuer_ls180.v:170894.3-170895.83" + wire width 2 $0\alu_shift_rot0_sr_op__input_carry[1:0] + attribute \src "issuer_ls180.v:171117.3-171153.6" + wire $0\alu_shift_rot0_sr_op__input_cr$next[0:0]$11562 + attribute \src "issuer_ls180.v:170898.3-170899.77" + wire $0\alu_shift_rot0_sr_op__input_cr[0:0] + attribute \src "issuer_ls180.v:171117.3-171153.6" + wire width 32 $0\alu_shift_rot0_sr_op__insn$next[31:0]$11563 + attribute \src "issuer_ls180.v:170906.3-170907.69" + wire width 32 $0\alu_shift_rot0_sr_op__insn[31:0] + attribute \src "issuer_ls180.v:171117.3-171153.6" + wire width 7 $0\alu_shift_rot0_sr_op__insn_type$next[6:0]$11564 + attribute \src "issuer_ls180.v:170876.3-170877.79" + wire width 7 $0\alu_shift_rot0_sr_op__insn_type[6:0] + attribute \src "issuer_ls180.v:171117.3-171153.6" + wire $0\alu_shift_rot0_sr_op__is_32bit$next[0:0]$11565 + attribute \src "issuer_ls180.v:170902.3-170903.77" + wire $0\alu_shift_rot0_sr_op__is_32bit[0:0] + attribute \src "issuer_ls180.v:171117.3-171153.6" + wire $0\alu_shift_rot0_sr_op__is_signed$next[0:0]$11566 + attribute \src "issuer_ls180.v:170904.3-170905.79" + wire $0\alu_shift_rot0_sr_op__is_signed[0:0] + attribute \src "issuer_ls180.v:171117.3-171153.6" + wire $0\alu_shift_rot0_sr_op__oe__oe$next[0:0]$11567 + attribute \src "issuer_ls180.v:170888.3-170889.73" + wire $0\alu_shift_rot0_sr_op__oe__oe[0:0] + attribute \src "issuer_ls180.v:171117.3-171153.6" + wire $0\alu_shift_rot0_sr_op__oe__ok$next[0:0]$11568 + attribute \src "issuer_ls180.v:170890.3-170891.73" + wire $0\alu_shift_rot0_sr_op__oe__ok[0:0] + attribute \src "issuer_ls180.v:171117.3-171153.6" + wire $0\alu_shift_rot0_sr_op__output_carry$next[0:0]$11569 + attribute \src "issuer_ls180.v:170896.3-170897.85" + wire $0\alu_shift_rot0_sr_op__output_carry[0:0] + attribute \src "issuer_ls180.v:171117.3-171153.6" + wire $0\alu_shift_rot0_sr_op__output_cr$next[0:0]$11570 + attribute \src "issuer_ls180.v:170900.3-170901.79" + wire $0\alu_shift_rot0_sr_op__output_cr[0:0] + attribute \src "issuer_ls180.v:171117.3-171153.6" + wire $0\alu_shift_rot0_sr_op__rc__ok$next[0:0]$11571 + attribute \src "issuer_ls180.v:170886.3-170887.73" + wire $0\alu_shift_rot0_sr_op__rc__ok[0:0] + attribute \src "issuer_ls180.v:171117.3-171153.6" + wire $0\alu_shift_rot0_sr_op__rc__rc$next[0:0]$11572 + attribute \src "issuer_ls180.v:170884.3-170885.73" + wire $0\alu_shift_rot0_sr_op__rc__rc[0:0] + attribute \src "issuer_ls180.v:171117.3-171153.6" + wire $0\alu_shift_rot0_sr_op__write_cr0$next[0:0]$11573 + attribute \src "issuer_ls180.v:170892.3-170893.79" + wire $0\alu_shift_rot0_sr_op__write_cr0[0:0] + attribute \src "issuer_ls180.v:171270.3-171278.6" + wire $0\alui_l_r_alui$next[0:0]$11636 + attribute \src "issuer_ls180.v:170852.3-170853.43" + wire $0\alui_l_r_alui[0:0] + attribute \src "issuer_ls180.v:171154.3-171175.6" + wire width 64 $0\data_r0__o$next[63:0]$11597 + attribute \src "issuer_ls180.v:170872.3-170873.37" + wire width 64 $0\data_r0__o[63:0] + attribute \src "issuer_ls180.v:171154.3-171175.6" + wire $0\data_r0__o_ok$next[0:0]$11598 + attribute \src "issuer_ls180.v:170874.3-170875.43" + wire $0\data_r0__o_ok[0:0] + attribute \src "issuer_ls180.v:171176.3-171197.6" + wire width 4 $0\data_r1__cr_a$next[3:0]$11605 + attribute \src "issuer_ls180.v:170868.3-170869.43" + wire width 4 $0\data_r1__cr_a[3:0] + attribute \src "issuer_ls180.v:171176.3-171197.6" + wire $0\data_r1__cr_a_ok$next[0:0]$11606 + attribute \src "issuer_ls180.v:170870.3-170871.49" + wire $0\data_r1__cr_a_ok[0:0] + attribute \src "issuer_ls180.v:171198.3-171219.6" + wire width 2 $0\data_r2__xer_ca$next[1:0]$11613 + attribute \src "issuer_ls180.v:170864.3-170865.47" + wire width 2 $0\data_r2__xer_ca[1:0] + attribute \src "issuer_ls180.v:171198.3-171219.6" + wire $0\data_r2__xer_ca_ok$next[0:0]$11614 + attribute \src "issuer_ls180.v:170866.3-170867.53" + wire $0\data_r2__xer_ca_ok[0:0] + attribute \src "issuer_ls180.v:171288.3-171297.6" + wire width 64 $0\dest1_o[63:0] + attribute \src "issuer_ls180.v:171298.3-171307.6" + wire width 4 $0\dest2_o[3:0] + attribute \src "issuer_ls180.v:171308.3-171317.6" + wire width 2 $0\dest3_o[1:0] + attribute \src "issuer_ls180.v:170169.7-170169.20" + wire $0\initial[0:0] + attribute \src "issuer_ls180.v:171072.3-171080.6" + wire $0\opc_l_r_opc$next[0:0]$11543 + attribute \src "issuer_ls180.v:170916.3-170917.39" + wire $0\opc_l_r_opc[0:0] + attribute \src "issuer_ls180.v:171063.3-171071.6" + wire $0\opc_l_s_opc$next[0:0]$11540 + attribute \src "issuer_ls180.v:170918.3-170919.39" + wire $0\opc_l_s_opc[0:0] + attribute \src "issuer_ls180.v:171318.3-171326.6" + wire width 3 $0\prev_wr_go$next[2:0]$11645 + attribute \src "issuer_ls180.v:170928.3-170929.37" + wire width 3 $0\prev_wr_go[2:0] + attribute \src "issuer_ls180.v:171017.3-171026.6" + wire $0\req_done[0:0] + attribute \src "issuer_ls180.v:171108.3-171116.6" + wire width 3 $0\req_l_r_req$next[2:0]$11555 + attribute \src "issuer_ls180.v:170908.3-170909.39" + wire width 3 $0\req_l_r_req[2:0] + attribute \src "issuer_ls180.v:171099.3-171107.6" + wire width 3 $0\req_l_s_req$next[2:0]$11552 + attribute \src "issuer_ls180.v:170910.3-170911.39" + wire width 3 $0\req_l_s_req[2:0] + attribute \src "issuer_ls180.v:171036.3-171044.6" + wire $0\rok_l_r_rdok$next[0:0]$11531 + attribute \src "issuer_ls180.v:170924.3-170925.41" + wire $0\rok_l_r_rdok[0:0] + attribute \src "issuer_ls180.v:171027.3-171035.6" + wire $0\rok_l_s_rdok$next[0:0]$11528 + attribute \src "issuer_ls180.v:170926.3-170927.41" + wire $0\rok_l_s_rdok[0:0] + attribute \src "issuer_ls180.v:171054.3-171062.6" + wire $0\rst_l_r_rst$next[0:0]$11537 + attribute \src "issuer_ls180.v:170920.3-170921.39" + wire $0\rst_l_r_rst[0:0] + attribute \src "issuer_ls180.v:171045.3-171053.6" + wire $0\rst_l_s_rst$next[0:0]$11534 + attribute \src "issuer_ls180.v:170922.3-170923.39" + wire $0\rst_l_s_rst[0:0] + attribute \src "issuer_ls180.v:171090.3-171098.6" + wire width 5 $0\src_l_r_src$next[4:0]$11549 + attribute \src "issuer_ls180.v:170912.3-170913.39" + wire width 5 $0\src_l_r_src[4:0] + attribute \src "issuer_ls180.v:171081.3-171089.6" + wire width 5 $0\src_l_s_src$next[4:0]$11546 + attribute \src "issuer_ls180.v:170914.3-170915.39" + wire width 5 $0\src_l_s_src[4:0] + attribute \src "issuer_ls180.v:171220.3-171229.6" + wire width 64 $0\src_r0$next[63:0]$11621 + attribute \src "issuer_ls180.v:170862.3-170863.29" + wire width 64 $0\src_r0[63:0] + attribute \src "issuer_ls180.v:171230.3-171239.6" + wire width 64 $0\src_r1$next[63:0]$11624 + attribute \src "issuer_ls180.v:170860.3-170861.29" + wire width 64 $0\src_r1[63:0] + attribute \src "issuer_ls180.v:171240.3-171249.6" + wire width 64 $0\src_r2$next[63:0]$11627 + attribute \src "issuer_ls180.v:170858.3-170859.29" + wire width 64 $0\src_r2[63:0] + attribute \src "issuer_ls180.v:171250.3-171259.6" + wire $0\src_r3$next[0:0]$11630 + attribute \src "issuer_ls180.v:170856.3-170857.29" + wire $0\src_r3[0:0] + attribute \src "issuer_ls180.v:171260.3-171269.6" + wire width 2 $0\src_r4$next[1:0]$11633 + attribute \src "issuer_ls180.v:170854.3-170855.29" + wire width 2 $0\src_r4[1:0] + attribute \src "issuer_ls180.v:170291.7-170291.24" + wire $1\all_rd_dly[0:0] + attribute \src "issuer_ls180.v:170301.7-170301.26" + wire $1\alu_done_dly[0:0] + attribute \src "issuer_ls180.v:171279.3-171287.6" + wire $1\alu_l_r_alu$next[0:0]$11640 + attribute \src "issuer_ls180.v:170309.7-170309.25" + wire $1\alu_l_r_alu[0:0] + attribute \src "issuer_ls180.v:171117.3-171153.6" + wire width 12 $1\alu_shift_rot0_sr_op__fn_unit$next[11:0]$11574 + attribute \src "issuer_ls180.v:170350.14-170350.53" + wire width 12 $1\alu_shift_rot0_sr_op__fn_unit[11:0] + attribute \src "issuer_ls180.v:171117.3-171153.6" + wire width 64 $1\alu_shift_rot0_sr_op__imm_data__data$next[63:0]$11575 + attribute \src "issuer_ls180.v:170354.14-170354.73" + wire width 64 $1\alu_shift_rot0_sr_op__imm_data__data[63:0] + attribute \src "issuer_ls180.v:171117.3-171153.6" + wire $1\alu_shift_rot0_sr_op__imm_data__ok$next[0:0]$11576 + attribute \src "issuer_ls180.v:170358.7-170358.48" + wire $1\alu_shift_rot0_sr_op__imm_data__ok[0:0] + attribute \src "issuer_ls180.v:171117.3-171153.6" + wire width 2 $1\alu_shift_rot0_sr_op__input_carry$next[1:0]$11577 + attribute \src "issuer_ls180.v:170366.13-170366.53" + wire width 2 $1\alu_shift_rot0_sr_op__input_carry[1:0] + attribute \src "issuer_ls180.v:171117.3-171153.6" + wire $1\alu_shift_rot0_sr_op__input_cr$next[0:0]$11578 + attribute \src "issuer_ls180.v:170370.7-170370.44" + wire $1\alu_shift_rot0_sr_op__input_cr[0:0] + attribute \src "issuer_ls180.v:171117.3-171153.6" + wire width 32 $1\alu_shift_rot0_sr_op__insn$next[31:0]$11579 + attribute \src "issuer_ls180.v:170374.14-170374.48" + wire width 32 $1\alu_shift_rot0_sr_op__insn[31:0] + attribute \src "issuer_ls180.v:171117.3-171153.6" + wire width 7 $1\alu_shift_rot0_sr_op__insn_type$next[6:0]$11580 + attribute \src "issuer_ls180.v:170452.13-170452.52" + wire width 7 $1\alu_shift_rot0_sr_op__insn_type[6:0] + attribute \src "issuer_ls180.v:171117.3-171153.6" + wire $1\alu_shift_rot0_sr_op__is_32bit$next[0:0]$11581 + attribute \src "issuer_ls180.v:170456.7-170456.44" + wire $1\alu_shift_rot0_sr_op__is_32bit[0:0] + attribute \src "issuer_ls180.v:171117.3-171153.6" + wire $1\alu_shift_rot0_sr_op__is_signed$next[0:0]$11582 + attribute \src "issuer_ls180.v:170460.7-170460.45" + wire $1\alu_shift_rot0_sr_op__is_signed[0:0] + attribute \src "issuer_ls180.v:171117.3-171153.6" + wire $1\alu_shift_rot0_sr_op__oe__oe$next[0:0]$11583 + attribute \src "issuer_ls180.v:170464.7-170464.42" + wire $1\alu_shift_rot0_sr_op__oe__oe[0:0] + attribute \src "issuer_ls180.v:171117.3-171153.6" + wire $1\alu_shift_rot0_sr_op__oe__ok$next[0:0]$11584 + attribute \src "issuer_ls180.v:170468.7-170468.42" + wire $1\alu_shift_rot0_sr_op__oe__ok[0:0] + attribute \src "issuer_ls180.v:171117.3-171153.6" + wire $1\alu_shift_rot0_sr_op__output_carry$next[0:0]$11585 + attribute \src "issuer_ls180.v:170472.7-170472.48" + wire $1\alu_shift_rot0_sr_op__output_carry[0:0] + attribute \src "issuer_ls180.v:171117.3-171153.6" + wire $1\alu_shift_rot0_sr_op__output_cr$next[0:0]$11586 + attribute \src "issuer_ls180.v:170476.7-170476.45" + wire $1\alu_shift_rot0_sr_op__output_cr[0:0] + attribute \src "issuer_ls180.v:171117.3-171153.6" + wire $1\alu_shift_rot0_sr_op__rc__ok$next[0:0]$11587 + attribute \src "issuer_ls180.v:170480.7-170480.42" + wire $1\alu_shift_rot0_sr_op__rc__ok[0:0] + attribute \src "issuer_ls180.v:171117.3-171153.6" + wire $1\alu_shift_rot0_sr_op__rc__rc$next[0:0]$11588 + attribute \src "issuer_ls180.v:170484.7-170484.42" + wire $1\alu_shift_rot0_sr_op__rc__rc[0:0] + attribute \src "issuer_ls180.v:171117.3-171153.6" + wire $1\alu_shift_rot0_sr_op__write_cr0$next[0:0]$11589 + attribute \src "issuer_ls180.v:170488.7-170488.45" + wire $1\alu_shift_rot0_sr_op__write_cr0[0:0] + attribute \src "issuer_ls180.v:171270.3-171278.6" + wire $1\alui_l_r_alui$next[0:0]$11637 + attribute \src "issuer_ls180.v:170500.7-170500.27" + wire $1\alui_l_r_alui[0:0] + attribute \src "issuer_ls180.v:171154.3-171175.6" + wire width 64 $1\data_r0__o$next[63:0]$11599 + attribute \src "issuer_ls180.v:170534.14-170534.47" + wire width 64 $1\data_r0__o[63:0] + attribute \src "issuer_ls180.v:171154.3-171175.6" + wire $1\data_r0__o_ok$next[0:0]$11600 + attribute \src "issuer_ls180.v:170538.7-170538.27" + wire $1\data_r0__o_ok[0:0] + attribute \src "issuer_ls180.v:171176.3-171197.6" + wire width 4 $1\data_r1__cr_a$next[3:0]$11607 + attribute \src "issuer_ls180.v:170542.13-170542.33" + wire width 4 $1\data_r1__cr_a[3:0] + attribute \src "issuer_ls180.v:171176.3-171197.6" + wire $1\data_r1__cr_a_ok$next[0:0]$11608 + attribute \src "issuer_ls180.v:170546.7-170546.30" + wire $1\data_r1__cr_a_ok[0:0] + attribute \src "issuer_ls180.v:171198.3-171219.6" + wire width 2 $1\data_r2__xer_ca$next[1:0]$11615 + attribute \src "issuer_ls180.v:170550.13-170550.35" + wire width 2 $1\data_r2__xer_ca[1:0] + attribute \src "issuer_ls180.v:171198.3-171219.6" + wire $1\data_r2__xer_ca_ok$next[0:0]$11616 + attribute \src "issuer_ls180.v:170554.7-170554.32" + wire $1\data_r2__xer_ca_ok[0:0] + attribute \src "issuer_ls180.v:171288.3-171297.6" + wire width 64 $1\dest1_o[63:0] + attribute \src "issuer_ls180.v:171298.3-171307.6" + wire width 4 $1\dest2_o[3:0] + attribute \src "issuer_ls180.v:171308.3-171317.6" + wire width 2 $1\dest3_o[1:0] + attribute \src "issuer_ls180.v:171072.3-171080.6" + wire $1\opc_l_r_opc$next[0:0]$11544 + attribute \src "issuer_ls180.v:170571.7-170571.25" + wire $1\opc_l_r_opc[0:0] + attribute \src "issuer_ls180.v:171063.3-171071.6" + wire $1\opc_l_s_opc$next[0:0]$11541 + attribute \src "issuer_ls180.v:170575.7-170575.25" + wire $1\opc_l_s_opc[0:0] + attribute \src "issuer_ls180.v:171318.3-171326.6" + wire width 3 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\A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \o_ok + connect \B \cu_busy_o + connect \Y $and$issuer_ls180.v:170833$11467_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" + cell $and $and$issuer_ls180.v:170834$11468 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cr_a_ok + connect \B \cu_busy_o + connect \Y $and$issuer_ls180.v:170834$11468_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" + cell $and $and$issuer_ls180.v:170835$11469 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \xer_ca_ok + connect \B \cu_busy_o + connect \Y $and$issuer_ls180.v:170835$11469_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:327" + cell $and $and$issuer_ls180.v:170845$11479 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \alu_shift_rot0_p_ready_o + connect \B \alui_l_q_alui + connect \Y $and$issuer_ls180.v:170845$11479_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:334" + cell $and $and$issuer_ls180.v:170846$11480 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \alu_shift_rot0_n_valid_o + connect \B \alu_l_q_alu + connect \Y $and$issuer_ls180.v:170846$11480_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" + cell $and $and$issuer_ls180.v:170847$11481 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 5 + connect \A \src_l_q_src + connect \B { \cu_busy_o \cu_busy_o \cu_busy_o \cu_busy_o \cu_busy_o } + connect \Y $and$issuer_ls180.v:170847$11481_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" + cell $and $and$issuer_ls180.v:170849$11483 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 5 + connect \A \$94 + connect \B { 3'111 \$96 1'1 } + connect \Y $and$issuer_ls180.v:170849$11483_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" + cell $eq $eq$issuer_ls180.v:170819$11453 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$42 + connect \B 1'0 + connect \Y $eq$issuer_ls180.v:170819$11453_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" + cell $eq $eq$issuer_ls180.v:170821$11455 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cu_wrmask_o + connect \B 1'0 + connect \Y $eq$issuer_ls180.v:170821$11455_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" + cell $not $not$issuer_ls180.v:170791$11425 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \Y_WIDTH 5 + connect \A \cu_rdmaskn_i + connect \Y $not$issuer_ls180.v:170791$11425_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + cell $not $not$issuer_ls180.v:170802$11436 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \all_rd_dly + connect \Y $not$issuer_ls180.v:170802$11436_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + cell $not $not$issuer_ls180.v:170804$11438 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \alu_done_dly + connect \Y $not$issuer_ls180.v:170804$11438_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" + cell $not $not$issuer_ls180.v:170807$11441 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \cu_wrmask_o + connect \Y $not$issuer_ls180.v:170807$11441_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" + cell $not $not$issuer_ls180.v:170810$11444 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$23 + connect \Y $not$issuer_ls180.v:170810$11444_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" + cell $not $not$issuer_ls180.v:170816$11450 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \alu_shift_rot0_n_ready_i + connect \Y $not$issuer_ls180.v:170816$11450_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" + cell $not $not$issuer_ls180.v:170827$11461 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \Y_WIDTH 5 + connect \A \cu_rd__rel_o + connect \Y $not$issuer_ls180.v:170827$11461_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:173" + cell $not $not$issuer_ls180.v:170848$11482 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \alu_shift_rot0_sr_op__imm_data__ok + connect \Y $not$issuer_ls180.v:170848$11482_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" + cell $or $or$issuer_ls180.v:170815$11449 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$32 + connect \B \$34 + connect \Y $or$issuer_ls180.v:170815$11449_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:230" + cell $or $or$issuer_ls180.v:170825$11459 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \req_done + connect \B \cu_go_die_i + connect \Y $or$issuer_ls180.v:170825$11459_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:231" + cell $or $or$issuer_ls180.v:170826$11460 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cu_issue_i + connect \B \cu_go_die_i + connect \Y $or$issuer_ls180.v:170826$11460_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:232" + cell $or $or$issuer_ls180.v:170828$11462 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \cu_wr__go_i + connect \B { \cu_go_die_i \cu_go_die_i \cu_go_die_i } + connect \Y $or$issuer_ls180.v:170828$11462_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:233" + cell $or $or$issuer_ls180.v:170829$11463 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 5 + connect \A \cu_rd__go_i + connect \B { \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i } + connect \Y $or$issuer_ls180.v:170829$11463_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:253" + cell $or $or$issuer_ls180.v:170832$11466 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \reset_w + connect \B \prev_wr_go + connect \Y $or$issuer_ls180.v:170832$11466_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" + cell $or $or$issuer_ls180.v:170838$11472 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 5 + connect \A \$5 + connect \B \cu_rd__go_i + connect \Y $or$issuer_ls180.v:170838$11472_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" + cell $reduce_and $reduce_and$issuer_ls180.v:170844$11478 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \$7 + connect \Y $reduce_and$issuer_ls180.v:170844$11478_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" + cell $reduce_or $reduce_or$issuer_ls180.v:170809$11443 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \$26 + connect \Y $reduce_or$issuer_ls180.v:170809$11443_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" + cell $reduce_or $reduce_or$issuer_ls180.v:170813$11447 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \cu_wr__go_i + connect \Y $reduce_or$issuer_ls180.v:170813$11447_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" + cell $reduce_or $reduce_or$issuer_ls180.v:170814$11448 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \prev_wr_go + connect \Y $reduce_or$issuer_ls180.v:170814$11448_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:168" + cell $mux $ternary$issuer_ls180.v:170836$11470 + parameter \WIDTH 1 + connect \A \src_l_q_src [1] + connect \B \opc_l_q_opc + connect \S \alu_shift_rot0_sr_op__imm_data__ok + connect \Y $ternary$issuer_ls180.v:170836$11470_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:169" + cell $mux $ternary$issuer_ls180.v:170837$11471 + parameter \WIDTH 64 + connect \A \src2_i + connect \B \alu_shift_rot0_sr_op__imm_data__data + connect \S \alu_shift_rot0_sr_op__imm_data__ok + connect \Y $ternary$issuer_ls180.v:170837$11471_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + cell $mux $ternary$issuer_ls180.v:170839$11473 + parameter \WIDTH 64 + connect \A \src_r0 + connect \B \src1_i + connect \S \src_l_q_src [0] + connect \Y $ternary$issuer_ls180.v:170839$11473_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + cell $mux $ternary$issuer_ls180.v:170840$11474 + parameter \WIDTH 64 + connect \A \src_r1 + connect \B \src_or_imm + connect \S \src_sel + connect \Y $ternary$issuer_ls180.v:170840$11474_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + cell $mux $ternary$issuer_ls180.v:170841$11475 + parameter \WIDTH 64 + connect \A \src_r2 + connect \B \src3_i + connect \S \src_l_q_src [2] + connect \Y $ternary$issuer_ls180.v:170841$11475_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + cell $mux $ternary$issuer_ls180.v:170842$11476 + parameter \WIDTH 1 + connect \A \src_r3 + connect \B \src4_i + connect \S \src_l_q_src [3] + connect \Y $ternary$issuer_ls180.v:170842$11476_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + cell $mux $ternary$issuer_ls180.v:170843$11477 + parameter \WIDTH 2 + connect \A \src_r4 + connect \B \src5_i + connect \S \src_l_q_src [4] + connect \Y $ternary$issuer_ls180.v:170843$11477_Y + end + attribute \module_not_derived 1 + attribute \src "issuer_ls180.v:170934.15-170940.4" + cell \alu_l$122 \alu_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_alu \alu_l_q_alu + connect \r_alu \alu_l_r_alu + connect \s_alu \alu_l_s_alu + end + attribute \module_not_derived 1 + attribute \src "issuer_ls180.v:170941.18-170975.4" + cell \alu_shift_rot0 \alu_shift_rot0 + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \cr_a \alu_shift_rot0_cr_a + connect \cr_a_ok \cr_a_ok + connect \n_ready_i \alu_shift_rot0_n_ready_i + connect \n_valid_o \alu_shift_rot0_n_valid_o + connect \o \alu_shift_rot0_o + connect \o_ok \o_ok + connect \p_ready_o \alu_shift_rot0_p_ready_o + connect \p_valid_i \alu_shift_rot0_p_valid_i + connect \ra \alu_shift_rot0_ra + connect \rb \alu_shift_rot0_rb + connect \rc \alu_shift_rot0_rc + connect \sr_op__fn_unit \alu_shift_rot0_sr_op__fn_unit + connect \sr_op__imm_data__data \alu_shift_rot0_sr_op__imm_data__data + connect \sr_op__imm_data__ok \alu_shift_rot0_sr_op__imm_data__ok + connect \sr_op__input_carry \alu_shift_rot0_sr_op__input_carry + connect \sr_op__input_cr \alu_shift_rot0_sr_op__input_cr + connect \sr_op__insn \alu_shift_rot0_sr_op__insn + connect \sr_op__insn_type \alu_shift_rot0_sr_op__insn_type + connect \sr_op__is_32bit \alu_shift_rot0_sr_op__is_32bit + connect \sr_op__is_signed \alu_shift_rot0_sr_op__is_signed + connect \sr_op__oe__oe \alu_shift_rot0_sr_op__oe__oe + connect \sr_op__oe__ok \alu_shift_rot0_sr_op__oe__ok + connect \sr_op__output_carry \alu_shift_rot0_sr_op__output_carry + connect \sr_op__output_cr \alu_shift_rot0_sr_op__output_cr + connect \sr_op__rc__ok \alu_shift_rot0_sr_op__rc__ok + connect \sr_op__rc__rc \alu_shift_rot0_sr_op__rc__rc + connect \sr_op__write_cr0 \alu_shift_rot0_sr_op__write_cr0 + connect \xer_ca \alu_shift_rot0_xer_ca + connect \xer_ca$1 \alu_shift_rot0_xer_ca$1 + connect \xer_ca_ok \xer_ca_ok + connect \xer_so \alu_shift_rot0_xer_so + end + attribute \module_not_derived 1 + attribute \src "issuer_ls180.v:170976.16-170982.4" + cell \alui_l$121 \alui_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_alui \alui_l_q_alui + connect \r_alui \alui_l_r_alui + connect \s_alui \alui_l_s_alui + end + attribute \module_not_derived 1 + attribute \src "issuer_ls180.v:170983.15-170989.4" + cell \opc_l$117 \opc_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_opc \opc_l_q_opc + connect \r_opc \opc_l_r_opc + connect \s_opc \opc_l_s_opc + end + attribute \module_not_derived 1 + attribute \src "issuer_ls180.v:170990.15-170996.4" + cell \req_l$118 \req_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_req \req_l_q_req + connect \r_req \req_l_r_req + connect \s_req \req_l_s_req + end + attribute \module_not_derived 1 + attribute \src "issuer_ls180.v:170997.15-171003.4" + cell \rok_l$120 \rok_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_rdok \rok_l_q_rdok + connect \r_rdok \rok_l_r_rdok + connect \s_rdok \rok_l_s_rdok + end + attribute \module_not_derived 1 + attribute \src "issuer_ls180.v:171004.15-171009.4" + cell \rst_l$119 \rst_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \r_rst \rst_l_r_rst + connect \s_rst \rst_l_s_rst + end + attribute \module_not_derived 1 + attribute \src "issuer_ls180.v:171010.15-171016.4" + cell \src_l$116 \src_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_src \src_l_q_src + connect \r_src \src_l_r_src + connect \s_src \src_l_s_src + end + attribute \src "issuer_ls180.v:170169.7-170169.20" + process $proc$issuer_ls180.v:170169$11647 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "issuer_ls180.v:170291.7-170291.24" + process $proc$issuer_ls180.v:170291$11648 + assign { } { } + assign $1\all_rd_dly[0:0] 1'0 + sync always + sync init + update \all_rd_dly $1\all_rd_dly[0:0] + end + attribute \src "issuer_ls180.v:170301.7-170301.26" + process $proc$issuer_ls180.v:170301$11649 + assign { } { } + assign $1\alu_done_dly[0:0] 1'0 + sync always + sync init + update \alu_done_dly $1\alu_done_dly[0:0] + end + attribute \src "issuer_ls180.v:170309.7-170309.25" + process $proc$issuer_ls180.v:170309$11650 + assign { } { } + assign $1\alu_l_r_alu[0:0] 1'1 + sync always + sync init + update \alu_l_r_alu $1\alu_l_r_alu[0:0] + end + attribute \src "issuer_ls180.v:170350.14-170350.53" + process $proc$issuer_ls180.v:170350$11651 + assign { } { } + assign $1\alu_shift_rot0_sr_op__fn_unit[11:0] 12'000000000000 + sync always + sync init + update \alu_shift_rot0_sr_op__fn_unit $1\alu_shift_rot0_sr_op__fn_unit[11:0] + end + attribute \src "issuer_ls180.v:170354.14-170354.73" + process $proc$issuer_ls180.v:170354$11652 + assign { } { } + assign $1\alu_shift_rot0_sr_op__imm_data__data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \alu_shift_rot0_sr_op__imm_data__data $1\alu_shift_rot0_sr_op__imm_data__data[63:0] + end + attribute \src "issuer_ls180.v:170358.7-170358.48" + process $proc$issuer_ls180.v:170358$11653 + assign { } { } + assign $1\alu_shift_rot0_sr_op__imm_data__ok[0:0] 1'0 + sync always + sync init + update \alu_shift_rot0_sr_op__imm_data__ok $1\alu_shift_rot0_sr_op__imm_data__ok[0:0] + end + attribute \src "issuer_ls180.v:170366.13-170366.53" + process $proc$issuer_ls180.v:170366$11654 + assign { } { } + assign $1\alu_shift_rot0_sr_op__input_carry[1:0] 2'00 + sync always + sync init + update \alu_shift_rot0_sr_op__input_carry $1\alu_shift_rot0_sr_op__input_carry[1:0] + end + attribute \src "issuer_ls180.v:170370.7-170370.44" + process $proc$issuer_ls180.v:170370$11655 + assign { } { } + assign $1\alu_shift_rot0_sr_op__input_cr[0:0] 1'0 + sync always + sync init + update \alu_shift_rot0_sr_op__input_cr $1\alu_shift_rot0_sr_op__input_cr[0:0] + end + attribute \src "issuer_ls180.v:170374.14-170374.48" + process $proc$issuer_ls180.v:170374$11656 + assign { } { } + assign $1\alu_shift_rot0_sr_op__insn[31:0] 0 + sync always + sync init + update \alu_shift_rot0_sr_op__insn $1\alu_shift_rot0_sr_op__insn[31:0] + end + attribute \src "issuer_ls180.v:170452.13-170452.52" + process $proc$issuer_ls180.v:170452$11657 + assign { } { } + assign $1\alu_shift_rot0_sr_op__insn_type[6:0] 7'0000000 + sync always + sync init + update \alu_shift_rot0_sr_op__insn_type $1\alu_shift_rot0_sr_op__insn_type[6:0] + end + attribute \src "issuer_ls180.v:170456.7-170456.44" + process $proc$issuer_ls180.v:170456$11658 + assign { } { } + assign $1\alu_shift_rot0_sr_op__is_32bit[0:0] 1'0 + sync always + sync init + update \alu_shift_rot0_sr_op__is_32bit $1\alu_shift_rot0_sr_op__is_32bit[0:0] + end + attribute \src "issuer_ls180.v:170460.7-170460.45" + process $proc$issuer_ls180.v:170460$11659 + assign { } { } + assign $1\alu_shift_rot0_sr_op__is_signed[0:0] 1'0 + sync always + sync init + update \alu_shift_rot0_sr_op__is_signed $1\alu_shift_rot0_sr_op__is_signed[0:0] + end + attribute \src "issuer_ls180.v:170464.7-170464.42" + process $proc$issuer_ls180.v:170464$11660 + assign { } { } + assign $1\alu_shift_rot0_sr_op__oe__oe[0:0] 1'0 + sync always + sync init + update \alu_shift_rot0_sr_op__oe__oe $1\alu_shift_rot0_sr_op__oe__oe[0:0] + end + attribute \src "issuer_ls180.v:170468.7-170468.42" + process $proc$issuer_ls180.v:170468$11661 + assign { } { } + assign $1\alu_shift_rot0_sr_op__oe__ok[0:0] 1'0 + sync always + sync init + update \alu_shift_rot0_sr_op__oe__ok $1\alu_shift_rot0_sr_op__oe__ok[0:0] + end + attribute \src "issuer_ls180.v:170472.7-170472.48" + process $proc$issuer_ls180.v:170472$11662 + assign { } { } + assign $1\alu_shift_rot0_sr_op__output_carry[0:0] 1'0 + sync always + sync init + update \alu_shift_rot0_sr_op__output_carry $1\alu_shift_rot0_sr_op__output_carry[0:0] + end + attribute \src "issuer_ls180.v:170476.7-170476.45" + process $proc$issuer_ls180.v:170476$11663 + assign { } { } + assign $1\alu_shift_rot0_sr_op__output_cr[0:0] 1'0 + sync always + sync init + update \alu_shift_rot0_sr_op__output_cr $1\alu_shift_rot0_sr_op__output_cr[0:0] + end + attribute \src "issuer_ls180.v:170480.7-170480.42" + process $proc$issuer_ls180.v:170480$11664 + assign { } { } + assign $1\alu_shift_rot0_sr_op__rc__ok[0:0] 1'0 + sync always + sync init + update \alu_shift_rot0_sr_op__rc__ok $1\alu_shift_rot0_sr_op__rc__ok[0:0] + end + attribute \src "issuer_ls180.v:170484.7-170484.42" + process $proc$issuer_ls180.v:170484$11665 + assign { } { } + assign $1\alu_shift_rot0_sr_op__rc__rc[0:0] 1'0 + sync always + sync init + update \alu_shift_rot0_sr_op__rc__rc $1\alu_shift_rot0_sr_op__rc__rc[0:0] + end + attribute \src "issuer_ls180.v:170488.7-170488.45" + process $proc$issuer_ls180.v:170488$11666 + assign { } { } + assign $1\alu_shift_rot0_sr_op__write_cr0[0:0] 1'0 + sync always + sync init + update \alu_shift_rot0_sr_op__write_cr0 $1\alu_shift_rot0_sr_op__write_cr0[0:0] + end + attribute \src "issuer_ls180.v:170500.7-170500.27" + process $proc$issuer_ls180.v:170500$11667 + assign { } { } + assign $1\alui_l_r_alui[0:0] 1'1 + sync always + sync init + update \alui_l_r_alui $1\alui_l_r_alui[0:0] + end + attribute \src "issuer_ls180.v:170534.14-170534.47" + process $proc$issuer_ls180.v:170534$11668 + assign { } { } + assign $1\data_r0__o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \data_r0__o $1\data_r0__o[63:0] + end + attribute \src "issuer_ls180.v:170538.7-170538.27" + process $proc$issuer_ls180.v:170538$11669 + assign { } { } + assign $1\data_r0__o_ok[0:0] 1'0 + sync always + sync init + update \data_r0__o_ok $1\data_r0__o_ok[0:0] + end + attribute \src "issuer_ls180.v:170542.13-170542.33" + process $proc$issuer_ls180.v:170542$11670 + assign { } { } + assign $1\data_r1__cr_a[3:0] 4'0000 + sync always + sync init + update \data_r1__cr_a $1\data_r1__cr_a[3:0] + end + attribute \src "issuer_ls180.v:170546.7-170546.30" + process $proc$issuer_ls180.v:170546$11671 + assign { } { } + assign $1\data_r1__cr_a_ok[0:0] 1'0 + sync always + sync init + update \data_r1__cr_a_ok $1\data_r1__cr_a_ok[0:0] + end + attribute \src "issuer_ls180.v:170550.13-170550.35" + process $proc$issuer_ls180.v:170550$11672 + assign { } { } + assign $1\data_r2__xer_ca[1:0] 2'00 + sync always + sync init + update \data_r2__xer_ca $1\data_r2__xer_ca[1:0] + end + attribute \src "issuer_ls180.v:170554.7-170554.32" + process $proc$issuer_ls180.v:170554$11673 + assign { } { } + assign $1\data_r2__xer_ca_ok[0:0] 1'0 + sync always + sync init + update \data_r2__xer_ca_ok $1\data_r2__xer_ca_ok[0:0] + end + attribute \src "issuer_ls180.v:170571.7-170571.25" + process $proc$issuer_ls180.v:170571$11674 + assign { } { } + assign $1\opc_l_r_opc[0:0] 1'1 + sync always + sync init + update \opc_l_r_opc $1\opc_l_r_opc[0:0] + end + attribute \src "issuer_ls180.v:170575.7-170575.25" + process $proc$issuer_ls180.v:170575$11675 + assign { } { } + assign $1\opc_l_s_opc[0:0] 1'0 + sync always + sync init + update \opc_l_s_opc $1\opc_l_s_opc[0:0] + end + attribute \src "issuer_ls180.v:170702.13-170702.30" + process $proc$issuer_ls180.v:170702$11676 + assign { } { } + assign $1\prev_wr_go[2:0] 3'000 + sync always + sync init + update \prev_wr_go $1\prev_wr_go[2:0] + end + attribute \src "issuer_ls180.v:170710.13-170710.31" + process $proc$issuer_ls180.v:170710$11677 + assign { } { } + assign $1\req_l_r_req[2:0] 3'111 + sync always + sync init + update \req_l_r_req $1\req_l_r_req[2:0] + end + attribute \src "issuer_ls180.v:170714.13-170714.31" + process $proc$issuer_ls180.v:170714$11678 + assign { } { } + assign $1\req_l_s_req[2:0] 3'000 + sync always + sync init + update \req_l_s_req $1\req_l_s_req[2:0] + end + attribute \src "issuer_ls180.v:170726.7-170726.26" + process $proc$issuer_ls180.v:170726$11679 + assign { } { } + assign $1\rok_l_r_rdok[0:0] 1'1 + sync always + sync init + update \rok_l_r_rdok $1\rok_l_r_rdok[0:0] + end + attribute \src "issuer_ls180.v:170730.7-170730.26" + process $proc$issuer_ls180.v:170730$11680 + assign { } { } + assign $1\rok_l_s_rdok[0:0] 1'0 + sync always + sync init + update \rok_l_s_rdok $1\rok_l_s_rdok[0:0] + end + attribute \src "issuer_ls180.v:170734.7-170734.25" + process $proc$issuer_ls180.v:170734$11681 + assign { } { } + assign $1\rst_l_r_rst[0:0] 1'1 + sync always + sync init + update \rst_l_r_rst $1\rst_l_r_rst[0:0] + end + attribute \src "issuer_ls180.v:170738.7-170738.25" + process $proc$issuer_ls180.v:170738$11682 + assign { } { } + assign $1\rst_l_s_rst[0:0] 1'0 + sync always + sync init + update \rst_l_s_rst $1\rst_l_s_rst[0:0] + end + attribute \src "issuer_ls180.v:170756.13-170756.32" + process $proc$issuer_ls180.v:170756$11683 + assign { } { } + assign $1\src_l_r_src[4:0] 5'11111 + sync always + sync init + update \src_l_r_src $1\src_l_r_src[4:0] + end + attribute \src "issuer_ls180.v:170760.13-170760.32" + process $proc$issuer_ls180.v:170760$11684 + assign { } { } + assign $1\src_l_s_src[4:0] 5'00000 + sync always + sync init + update \src_l_s_src $1\src_l_s_src[4:0] + end + attribute \src "issuer_ls180.v:170766.14-170766.43" + process $proc$issuer_ls180.v:170766$11685 + assign { } { } + assign $1\src_r0[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \src_r0 $1\src_r0[63:0] + end + attribute \src "issuer_ls180.v:170770.14-170770.43" + process $proc$issuer_ls180.v:170770$11686 + assign { } { } + assign $1\src_r1[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \src_r1 $1\src_r1[63:0] + end + attribute \src "issuer_ls180.v:170774.14-170774.43" + process $proc$issuer_ls180.v:170774$11687 + assign { } { } + assign $1\src_r2[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \src_r2 $1\src_r2[63:0] + end + attribute \src "issuer_ls180.v:170778.7-170778.20" + process $proc$issuer_ls180.v:170778$11688 + assign { } { } + assign $1\src_r3[0:0] 1'0 + sync always + sync init + update \src_r3 $1\src_r3[0:0] + end + attribute \src "issuer_ls180.v:170782.13-170782.26" + process $proc$issuer_ls180.v:170782$11689 + assign { } { } + assign $1\src_r4[1:0] 2'00 + sync always + sync init + update \src_r4 $1\src_r4[1:0] + end + attribute \src "issuer_ls180.v:170850.3-170851.39" + process $proc$issuer_ls180.v:170850$11484 + assign { } { } + assign $0\alu_l_r_alu[0:0] \alu_l_r_alu$next + sync posedge \coresync_clk + update \alu_l_r_alu $0\alu_l_r_alu[0:0] + end + attribute \src "issuer_ls180.v:170852.3-170853.43" + process $proc$issuer_ls180.v:170852$11485 + assign { } { } + assign $0\alui_l_r_alui[0:0] \alui_l_r_alui$next + sync posedge \coresync_clk + update \alui_l_r_alui $0\alui_l_r_alui[0:0] + end + attribute \src "issuer_ls180.v:170854.3-170855.29" + process $proc$issuer_ls180.v:170854$11486 + assign { } { } + assign $0\src_r4[1:0] \src_r4$next + sync posedge \coresync_clk + update \src_r4 $0\src_r4[1:0] + end + attribute \src "issuer_ls180.v:170856.3-170857.29" + process $proc$issuer_ls180.v:170856$11487 + assign { } { } + assign $0\src_r3[0:0] \src_r3$next + sync posedge \coresync_clk + update \src_r3 $0\src_r3[0:0] + end + attribute \src "issuer_ls180.v:170858.3-170859.29" + process $proc$issuer_ls180.v:170858$11488 + assign { } { } + assign $0\src_r2[63:0] \src_r2$next + sync posedge \coresync_clk + update \src_r2 $0\src_r2[63:0] + end + attribute \src "issuer_ls180.v:170860.3-170861.29" + process $proc$issuer_ls180.v:170860$11489 + assign { } { } + assign $0\src_r1[63:0] \src_r1$next + sync posedge \coresync_clk + update \src_r1 $0\src_r1[63:0] + end + attribute \src "issuer_ls180.v:170862.3-170863.29" + process $proc$issuer_ls180.v:170862$11490 + assign { } { } + assign $0\src_r0[63:0] \src_r0$next + sync posedge \coresync_clk + update \src_r0 $0\src_r0[63:0] + end + attribute \src "issuer_ls180.v:170864.3-170865.47" + process $proc$issuer_ls180.v:170864$11491 + assign { } { } + assign $0\data_r2__xer_ca[1:0] \data_r2__xer_ca$next + sync posedge \coresync_clk + update \data_r2__xer_ca $0\data_r2__xer_ca[1:0] + end + attribute \src "issuer_ls180.v:170866.3-170867.53" + process $proc$issuer_ls180.v:170866$11492 + assign { } { } + assign $0\data_r2__xer_ca_ok[0:0] \data_r2__xer_ca_ok$next + sync posedge \coresync_clk + update \data_r2__xer_ca_ok $0\data_r2__xer_ca_ok[0:0] + end + attribute \src "issuer_ls180.v:170868.3-170869.43" + process $proc$issuer_ls180.v:170868$11493 + assign { } { } + assign $0\data_r1__cr_a[3:0] \data_r1__cr_a$next + sync posedge \coresync_clk + update \data_r1__cr_a $0\data_r1__cr_a[3:0] + end + attribute \src "issuer_ls180.v:170870.3-170871.49" + process $proc$issuer_ls180.v:170870$11494 + assign { } { } + assign $0\data_r1__cr_a_ok[0:0] \data_r1__cr_a_ok$next + sync posedge \coresync_clk + update \data_r1__cr_a_ok $0\data_r1__cr_a_ok[0:0] + end + attribute \src "issuer_ls180.v:170872.3-170873.37" + process $proc$issuer_ls180.v:170872$11495 + assign { } { } + assign $0\data_r0__o[63:0] \data_r0__o$next + sync posedge \coresync_clk + update \data_r0__o $0\data_r0__o[63:0] + end + attribute \src "issuer_ls180.v:170874.3-170875.43" + process $proc$issuer_ls180.v:170874$11496 + assign { } { } + assign $0\data_r0__o_ok[0:0] \data_r0__o_ok$next + sync posedge \coresync_clk + update \data_r0__o_ok $0\data_r0__o_ok[0:0] + end + attribute \src "issuer_ls180.v:170876.3-170877.79" + process $proc$issuer_ls180.v:170876$11497 + assign { } { } + assign $0\alu_shift_rot0_sr_op__insn_type[6:0] \alu_shift_rot0_sr_op__insn_type$next + sync posedge \coresync_clk + update \alu_shift_rot0_sr_op__insn_type $0\alu_shift_rot0_sr_op__insn_type[6:0] + end + attribute \src "issuer_ls180.v:170878.3-170879.75" + process $proc$issuer_ls180.v:170878$11498 + assign { } { } + assign $0\alu_shift_rot0_sr_op__fn_unit[11:0] \alu_shift_rot0_sr_op__fn_unit$next + sync posedge \coresync_clk + update \alu_shift_rot0_sr_op__fn_unit $0\alu_shift_rot0_sr_op__fn_unit[11:0] + end + attribute \src "issuer_ls180.v:170880.3-170881.89" + process $proc$issuer_ls180.v:170880$11499 + assign { } { } + assign $0\alu_shift_rot0_sr_op__imm_data__data[63:0] \alu_shift_rot0_sr_op__imm_data__data$next + sync posedge \coresync_clk + update \alu_shift_rot0_sr_op__imm_data__data $0\alu_shift_rot0_sr_op__imm_data__data[63:0] + end + attribute \src "issuer_ls180.v:170882.3-170883.85" + process $proc$issuer_ls180.v:170882$11500 + assign { } { } + assign $0\alu_shift_rot0_sr_op__imm_data__ok[0:0] \alu_shift_rot0_sr_op__imm_data__ok$next + sync posedge \coresync_clk + update \alu_shift_rot0_sr_op__imm_data__ok $0\alu_shift_rot0_sr_op__imm_data__ok[0:0] + end + attribute \src "issuer_ls180.v:170884.3-170885.73" + process $proc$issuer_ls180.v:170884$11501 + assign { } { } + assign $0\alu_shift_rot0_sr_op__rc__rc[0:0] \alu_shift_rot0_sr_op__rc__rc$next + sync posedge \coresync_clk + update \alu_shift_rot0_sr_op__rc__rc $0\alu_shift_rot0_sr_op__rc__rc[0:0] + end + attribute \src "issuer_ls180.v:170886.3-170887.73" + process $proc$issuer_ls180.v:170886$11502 + assign { } { } + assign $0\alu_shift_rot0_sr_op__rc__ok[0:0] \alu_shift_rot0_sr_op__rc__ok$next + sync posedge \coresync_clk + update \alu_shift_rot0_sr_op__rc__ok $0\alu_shift_rot0_sr_op__rc__ok[0:0] + end + attribute \src "issuer_ls180.v:170888.3-170889.73" + process $proc$issuer_ls180.v:170888$11503 + assign { } { } + assign $0\alu_shift_rot0_sr_op__oe__oe[0:0] \alu_shift_rot0_sr_op__oe__oe$next + sync posedge \coresync_clk + update \alu_shift_rot0_sr_op__oe__oe $0\alu_shift_rot0_sr_op__oe__oe[0:0] + end + attribute \src "issuer_ls180.v:170890.3-170891.73" + process $proc$issuer_ls180.v:170890$11504 + assign { } { } + assign $0\alu_shift_rot0_sr_op__oe__ok[0:0] \alu_shift_rot0_sr_op__oe__ok$next + sync posedge \coresync_clk + update \alu_shift_rot0_sr_op__oe__ok $0\alu_shift_rot0_sr_op__oe__ok[0:0] + end + attribute \src "issuer_ls180.v:170892.3-170893.79" + process $proc$issuer_ls180.v:170892$11505 + assign { } { } + assign $0\alu_shift_rot0_sr_op__write_cr0[0:0] \alu_shift_rot0_sr_op__write_cr0$next + sync posedge \coresync_clk + update \alu_shift_rot0_sr_op__write_cr0 $0\alu_shift_rot0_sr_op__write_cr0[0:0] + end + attribute \src "issuer_ls180.v:170894.3-170895.83" + process $proc$issuer_ls180.v:170894$11506 + assign { } { } + assign $0\alu_shift_rot0_sr_op__input_carry[1:0] \alu_shift_rot0_sr_op__input_carry$next + sync posedge \coresync_clk + update \alu_shift_rot0_sr_op__input_carry $0\alu_shift_rot0_sr_op__input_carry[1:0] + end + attribute \src "issuer_ls180.v:170896.3-170897.85" + process $proc$issuer_ls180.v:170896$11507 + assign { } { } + assign $0\alu_shift_rot0_sr_op__output_carry[0:0] \alu_shift_rot0_sr_op__output_carry$next + sync posedge \coresync_clk + update \alu_shift_rot0_sr_op__output_carry $0\alu_shift_rot0_sr_op__output_carry[0:0] + end + attribute \src "issuer_ls180.v:170898.3-170899.77" + process $proc$issuer_ls180.v:170898$11508 + assign { } { } + assign $0\alu_shift_rot0_sr_op__input_cr[0:0] \alu_shift_rot0_sr_op__input_cr$next + sync posedge \coresync_clk + update \alu_shift_rot0_sr_op__input_cr $0\alu_shift_rot0_sr_op__input_cr[0:0] + end + attribute \src "issuer_ls180.v:170900.3-170901.79" + process $proc$issuer_ls180.v:170900$11509 + assign { } { } + assign $0\alu_shift_rot0_sr_op__output_cr[0:0] \alu_shift_rot0_sr_op__output_cr$next + sync posedge \coresync_clk + update \alu_shift_rot0_sr_op__output_cr $0\alu_shift_rot0_sr_op__output_cr[0:0] + end + attribute \src "issuer_ls180.v:170902.3-170903.77" + process $proc$issuer_ls180.v:170902$11510 + assign { } { } + assign $0\alu_shift_rot0_sr_op__is_32bit[0:0] \alu_shift_rot0_sr_op__is_32bit$next + sync posedge \coresync_clk + update \alu_shift_rot0_sr_op__is_32bit $0\alu_shift_rot0_sr_op__is_32bit[0:0] + end + attribute \src "issuer_ls180.v:170904.3-170905.79" + process $proc$issuer_ls180.v:170904$11511 + assign { } { } + assign $0\alu_shift_rot0_sr_op__is_signed[0:0] \alu_shift_rot0_sr_op__is_signed$next + sync posedge \coresync_clk + update \alu_shift_rot0_sr_op__is_signed $0\alu_shift_rot0_sr_op__is_signed[0:0] + end + attribute \src "issuer_ls180.v:170906.3-170907.69" + process $proc$issuer_ls180.v:170906$11512 + assign { } { } + assign $0\alu_shift_rot0_sr_op__insn[31:0] \alu_shift_rot0_sr_op__insn$next + sync posedge \coresync_clk + update \alu_shift_rot0_sr_op__insn $0\alu_shift_rot0_sr_op__insn[31:0] + end + attribute \src "issuer_ls180.v:170908.3-170909.39" + process $proc$issuer_ls180.v:170908$11513 + assign { } { } + assign $0\req_l_r_req[2:0] \req_l_r_req$next + sync posedge \coresync_clk + update \req_l_r_req $0\req_l_r_req[2:0] + end + attribute \src "issuer_ls180.v:170910.3-170911.39" + process $proc$issuer_ls180.v:170910$11514 + assign { } { } + assign $0\req_l_s_req[2:0] \req_l_s_req$next + sync posedge \coresync_clk + update \req_l_s_req $0\req_l_s_req[2:0] + end + attribute \src "issuer_ls180.v:170912.3-170913.39" + process $proc$issuer_ls180.v:170912$11515 + assign { } { } + assign $0\src_l_r_src[4:0] \src_l_r_src$next + sync posedge \coresync_clk + update \src_l_r_src $0\src_l_r_src[4:0] + end + attribute \src "issuer_ls180.v:170914.3-170915.39" + process $proc$issuer_ls180.v:170914$11516 + assign { } { } + assign $0\src_l_s_src[4:0] \src_l_s_src$next + sync posedge \coresync_clk + update \src_l_s_src $0\src_l_s_src[4:0] + end + attribute \src "issuer_ls180.v:170916.3-170917.39" + process $proc$issuer_ls180.v:170916$11517 + assign { } { } + assign $0\opc_l_r_opc[0:0] \opc_l_r_opc$next + sync posedge \coresync_clk + update \opc_l_r_opc $0\opc_l_r_opc[0:0] + end + attribute \src "issuer_ls180.v:170918.3-170919.39" + process $proc$issuer_ls180.v:170918$11518 + assign { } { } + assign $0\opc_l_s_opc[0:0] \opc_l_s_opc$next + sync posedge \coresync_clk + update \opc_l_s_opc $0\opc_l_s_opc[0:0] + end + attribute \src "issuer_ls180.v:170920.3-170921.39" + process $proc$issuer_ls180.v:170920$11519 + assign { } { } + assign $0\rst_l_r_rst[0:0] \rst_l_r_rst$next + sync posedge \coresync_clk + update \rst_l_r_rst $0\rst_l_r_rst[0:0] + end + attribute \src "issuer_ls180.v:170922.3-170923.39" + process $proc$issuer_ls180.v:170922$11520 + assign { } { } + assign $0\rst_l_s_rst[0:0] \rst_l_s_rst$next + sync posedge \coresync_clk + update \rst_l_s_rst $0\rst_l_s_rst[0:0] + end + attribute \src "issuer_ls180.v:170924.3-170925.41" + process $proc$issuer_ls180.v:170924$11521 + assign { } { } + assign $0\rok_l_r_rdok[0:0] \rok_l_r_rdok$next + sync posedge \coresync_clk + update \rok_l_r_rdok $0\rok_l_r_rdok[0:0] + end + attribute \src "issuer_ls180.v:170926.3-170927.41" + process $proc$issuer_ls180.v:170926$11522 + assign { } { } + assign $0\rok_l_s_rdok[0:0] \rok_l_s_rdok$next + sync posedge \coresync_clk + update \rok_l_s_rdok $0\rok_l_s_rdok[0:0] + end + attribute \src "issuer_ls180.v:170928.3-170929.37" + process $proc$issuer_ls180.v:170928$11523 + assign { } { } + assign $0\prev_wr_go[2:0] \prev_wr_go$next + sync posedge \coresync_clk + update \prev_wr_go $0\prev_wr_go[2:0] + end + attribute \src "issuer_ls180.v:170930.3-170931.46" + process $proc$issuer_ls180.v:170930$11524 + assign { } { } + assign $0\alu_done_dly[0:0] \alu_shift_rot0_n_valid_o + sync posedge \coresync_clk + update \alu_done_dly $0\alu_done_dly[0:0] + end + attribute \src "issuer_ls180.v:170932.3-170933.25" + process $proc$issuer_ls180.v:170932$11525 + assign { } { } + assign $0\all_rd_dly[0:0] \$10 + sync posedge \coresync_clk + update \all_rd_dly $0\all_rd_dly[0:0] + end + attribute \src "issuer_ls180.v:171017.3-171026.6" + process $proc$issuer_ls180.v:171017$11526 + assign { } { } + assign { } { } + assign $0\req_done[0:0] $1\req_done[0:0] + attribute \src "issuer_ls180.v:171018.5-171018.29" + switch \initial + attribute \src "issuer_ls180.v:171018.9-171018.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" + switch \$54 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\req_done[0:0] 1'1 + case + assign $1\req_done[0:0] \$46 + end + sync always + update \req_done $0\req_done[0:0] + end + attribute \src "issuer_ls180.v:171027.3-171035.6" + process $proc$issuer_ls180.v:171027$11527 + assign { } { } + assign { } { } + assign $0\rok_l_s_rdok$next[0:0]$11528 $1\rok_l_s_rdok$next[0:0]$11529 + attribute \src "issuer_ls180.v:171028.5-171028.29" + switch \initial + attribute \src "issuer_ls180.v:171028.9-171028.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\rok_l_s_rdok$next[0:0]$11529 1'0 + case + assign $1\rok_l_s_rdok$next[0:0]$11529 \cu_issue_i + end + sync always + update \rok_l_s_rdok$next $0\rok_l_s_rdok$next[0:0]$11528 + end + attribute \src "issuer_ls180.v:171036.3-171044.6" + process $proc$issuer_ls180.v:171036$11530 + assign { } { } + assign { } { } + assign $0\rok_l_r_rdok$next[0:0]$11531 $1\rok_l_r_rdok$next[0:0]$11532 + attribute \src "issuer_ls180.v:171037.5-171037.29" + switch \initial + attribute \src "issuer_ls180.v:171037.9-171037.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\rok_l_r_rdok$next[0:0]$11532 1'1 + case + assign $1\rok_l_r_rdok$next[0:0]$11532 \$64 + end + sync always + update \rok_l_r_rdok$next $0\rok_l_r_rdok$next[0:0]$11531 + end + attribute \src "issuer_ls180.v:171045.3-171053.6" + process $proc$issuer_ls180.v:171045$11533 + assign { } { } + assign { } { } + assign $0\rst_l_s_rst$next[0:0]$11534 $1\rst_l_s_rst$next[0:0]$11535 + attribute \src "issuer_ls180.v:171046.5-171046.29" + switch \initial + attribute \src "issuer_ls180.v:171046.9-171046.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\rst_l_s_rst$next[0:0]$11535 1'0 + case + assign $1\rst_l_s_rst$next[0:0]$11535 \all_rd + end + sync always + update \rst_l_s_rst$next $0\rst_l_s_rst$next[0:0]$11534 + end + attribute \src "issuer_ls180.v:171054.3-171062.6" + process $proc$issuer_ls180.v:171054$11536 + assign { } { } + assign { } { } + assign $0\rst_l_r_rst$next[0:0]$11537 $1\rst_l_r_rst$next[0:0]$11538 + attribute \src "issuer_ls180.v:171055.5-171055.29" + switch \initial + attribute \src "issuer_ls180.v:171055.9-171055.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\rst_l_r_rst$next[0:0]$11538 1'1 + case + assign $1\rst_l_r_rst$next[0:0]$11538 \rst_r + end + sync always + update \rst_l_r_rst$next $0\rst_l_r_rst$next[0:0]$11537 + end + attribute \src "issuer_ls180.v:171063.3-171071.6" + process $proc$issuer_ls180.v:171063$11539 + assign { } { } + assign { } { } + assign $0\opc_l_s_opc$next[0:0]$11540 $1\opc_l_s_opc$next[0:0]$11541 + attribute \src "issuer_ls180.v:171064.5-171064.29" + switch \initial + attribute \src "issuer_ls180.v:171064.9-171064.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\opc_l_s_opc$next[0:0]$11541 1'0 + case + assign $1\opc_l_s_opc$next[0:0]$11541 \cu_issue_i + end + sync always + update \opc_l_s_opc$next $0\opc_l_s_opc$next[0:0]$11540 + end + attribute \src "issuer_ls180.v:171072.3-171080.6" + process $proc$issuer_ls180.v:171072$11542 + assign { } { } + assign { } { } + assign $0\opc_l_r_opc$next[0:0]$11543 $1\opc_l_r_opc$next[0:0]$11544 + attribute \src "issuer_ls180.v:171073.5-171073.29" + switch \initial + attribute \src "issuer_ls180.v:171073.9-171073.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\opc_l_r_opc$next[0:0]$11544 1'1 + case + assign $1\opc_l_r_opc$next[0:0]$11544 \req_done + end + sync always + update \opc_l_r_opc$next $0\opc_l_r_opc$next[0:0]$11543 + end + attribute \src "issuer_ls180.v:171081.3-171089.6" + process $proc$issuer_ls180.v:171081$11545 + assign { } { } + assign { } { } + assign $0\src_l_s_src$next[4:0]$11546 $1\src_l_s_src$next[4:0]$11547 + attribute \src "issuer_ls180.v:171082.5-171082.29" + switch \initial + attribute \src "issuer_ls180.v:171082.9-171082.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\src_l_s_src$next[4:0]$11547 5'00000 + case + assign $1\src_l_s_src$next[4:0]$11547 { \cu_issue_i \cu_issue_i \cu_issue_i \cu_issue_i \cu_issue_i } + end + sync always + update \src_l_s_src$next $0\src_l_s_src$next[4:0]$11546 + end + attribute \src "issuer_ls180.v:171090.3-171098.6" + process $proc$issuer_ls180.v:171090$11548 + assign { } { } + assign { } { } + assign $0\src_l_r_src$next[4:0]$11549 $1\src_l_r_src$next[4:0]$11550 + attribute \src "issuer_ls180.v:171091.5-171091.29" + switch \initial + attribute \src "issuer_ls180.v:171091.9-171091.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\src_l_r_src$next[4:0]$11550 5'11111 + case + assign $1\src_l_r_src$next[4:0]$11550 \reset_r + end + sync always + update \src_l_r_src$next $0\src_l_r_src$next[4:0]$11549 + end + attribute \src "issuer_ls180.v:171099.3-171107.6" + process $proc$issuer_ls180.v:171099$11551 + assign { } { } + assign { } { } + assign $0\req_l_s_req$next[2:0]$11552 $1\req_l_s_req$next[2:0]$11553 + attribute \src "issuer_ls180.v:171100.5-171100.29" + switch \initial + attribute \src "issuer_ls180.v:171100.9-171100.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\req_l_s_req$next[2:0]$11553 3'000 + case + assign $1\req_l_s_req$next[2:0]$11553 \$66 + end + sync always + update \req_l_s_req$next $0\req_l_s_req$next[2:0]$11552 + end + attribute \src "issuer_ls180.v:171108.3-171116.6" + process $proc$issuer_ls180.v:171108$11554 + assign { } { } + assign { } { } + assign $0\req_l_r_req$next[2:0]$11555 $1\req_l_r_req$next[2:0]$11556 + attribute \src "issuer_ls180.v:171109.5-171109.29" + switch \initial + attribute \src "issuer_ls180.v:171109.9-171109.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\req_l_r_req$next[2:0]$11556 3'111 + case + assign $1\req_l_r_req$next[2:0]$11556 \$68 + end + sync always + update \req_l_r_req$next $0\req_l_r_req$next[2:0]$11555 + end + attribute \src "issuer_ls180.v:171117.3-171153.6" + process $proc$issuer_ls180.v:171117$11557 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\alu_shift_rot0_sr_op__fn_unit$next[11:0]$11558 $1\alu_shift_rot0_sr_op__fn_unit$next[11:0]$11574 + assign { } { } + assign { } { } + assign $0\alu_shift_rot0_sr_op__input_carry$next[1:0]$11561 $1\alu_shift_rot0_sr_op__input_carry$next[1:0]$11577 + assign $0\alu_shift_rot0_sr_op__input_cr$next[0:0]$11562 $1\alu_shift_rot0_sr_op__input_cr$next[0:0]$11578 + assign $0\alu_shift_rot0_sr_op__insn$next[31:0]$11563 $1\alu_shift_rot0_sr_op__insn$next[31:0]$11579 + assign $0\alu_shift_rot0_sr_op__insn_type$next[6:0]$11564 $1\alu_shift_rot0_sr_op__insn_type$next[6:0]$11580 + assign $0\alu_shift_rot0_sr_op__is_32bit$next[0:0]$11565 $1\alu_shift_rot0_sr_op__is_32bit$next[0:0]$11581 + assign $0\alu_shift_rot0_sr_op__is_signed$next[0:0]$11566 $1\alu_shift_rot0_sr_op__is_signed$next[0:0]$11582 + assign { } { } + assign { } { } + assign $0\alu_shift_rot0_sr_op__output_carry$next[0:0]$11569 $1\alu_shift_rot0_sr_op__output_carry$next[0:0]$11585 + assign $0\alu_shift_rot0_sr_op__output_cr$next[0:0]$11570 $1\alu_shift_rot0_sr_op__output_cr$next[0:0]$11586 + assign { } { } + assign { } { } + assign $0\alu_shift_rot0_sr_op__write_cr0$next[0:0]$11573 $1\alu_shift_rot0_sr_op__write_cr0$next[0:0]$11589 + assign $0\alu_shift_rot0_sr_op__imm_data__data$next[63:0]$11559 $2\alu_shift_rot0_sr_op__imm_data__data$next[63:0]$11590 + assign $0\alu_shift_rot0_sr_op__imm_data__ok$next[0:0]$11560 $2\alu_shift_rot0_sr_op__imm_data__ok$next[0:0]$11591 + assign $0\alu_shift_rot0_sr_op__oe__oe$next[0:0]$11567 $2\alu_shift_rot0_sr_op__oe__oe$next[0:0]$11592 + assign $0\alu_shift_rot0_sr_op__oe__ok$next[0:0]$11568 $2\alu_shift_rot0_sr_op__oe__ok$next[0:0]$11593 + assign $0\alu_shift_rot0_sr_op__rc__ok$next[0:0]$11571 $2\alu_shift_rot0_sr_op__rc__ok$next[0:0]$11594 + assign $0\alu_shift_rot0_sr_op__rc__rc$next[0:0]$11572 $2\alu_shift_rot0_sr_op__rc__rc$next[0:0]$11595 + attribute \src "issuer_ls180.v:171118.5-171118.29" + switch \initial + attribute \src "issuer_ls180.v:171118.9-171118.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:257" + switch \cu_issue_i + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { $1\alu_shift_rot0_sr_op__insn$next[31:0]$11579 $1\alu_shift_rot0_sr_op__is_signed$next[0:0]$11582 $1\alu_shift_rot0_sr_op__is_32bit$next[0:0]$11581 $1\alu_shift_rot0_sr_op__output_cr$next[0:0]$11586 $1\alu_shift_rot0_sr_op__input_cr$next[0:0]$11578 $1\alu_shift_rot0_sr_op__output_carry$next[0:0]$11585 $1\alu_shift_rot0_sr_op__input_carry$next[1:0]$11577 $1\alu_shift_rot0_sr_op__write_cr0$next[0:0]$11589 $1\alu_shift_rot0_sr_op__oe__ok$next[0:0]$11584 $1\alu_shift_rot0_sr_op__oe__oe$next[0:0]$11583 $1\alu_shift_rot0_sr_op__rc__ok$next[0:0]$11587 $1\alu_shift_rot0_sr_op__rc__rc$next[0:0]$11588 $1\alu_shift_rot0_sr_op__imm_data__ok$next[0:0]$11576 $1\alu_shift_rot0_sr_op__imm_data__data$next[63:0]$11575 $1\alu_shift_rot0_sr_op__fn_unit$next[11:0]$11574 $1\alu_shift_rot0_sr_op__insn_type$next[6:0]$11580 } { \oper_i_alu_shift_rot0__insn \oper_i_alu_shift_rot0__is_signed \oper_i_alu_shift_rot0__is_32bit \oper_i_alu_shift_rot0__output_cr \oper_i_alu_shift_rot0__input_cr \oper_i_alu_shift_rot0__output_carry \oper_i_alu_shift_rot0__input_carry \oper_i_alu_shift_rot0__write_cr0 \oper_i_alu_shift_rot0__oe__ok \oper_i_alu_shift_rot0__oe__oe \oper_i_alu_shift_rot0__rc__ok \oper_i_alu_shift_rot0__rc__rc \oper_i_alu_shift_rot0__imm_data__ok \oper_i_alu_shift_rot0__imm_data__data \oper_i_alu_shift_rot0__fn_unit \oper_i_alu_shift_rot0__insn_type } + case + assign $1\alu_shift_rot0_sr_op__fn_unit$next[11:0]$11574 \alu_shift_rot0_sr_op__fn_unit + assign $1\alu_shift_rot0_sr_op__imm_data__data$next[63:0]$11575 \alu_shift_rot0_sr_op__imm_data__data + assign $1\alu_shift_rot0_sr_op__imm_data__ok$next[0:0]$11576 \alu_shift_rot0_sr_op__imm_data__ok + assign $1\alu_shift_rot0_sr_op__input_carry$next[1:0]$11577 \alu_shift_rot0_sr_op__input_carry + assign $1\alu_shift_rot0_sr_op__input_cr$next[0:0]$11578 \alu_shift_rot0_sr_op__input_cr + assign $1\alu_shift_rot0_sr_op__insn$next[31:0]$11579 \alu_shift_rot0_sr_op__insn + assign $1\alu_shift_rot0_sr_op__insn_type$next[6:0]$11580 \alu_shift_rot0_sr_op__insn_type + assign $1\alu_shift_rot0_sr_op__is_32bit$next[0:0]$11581 \alu_shift_rot0_sr_op__is_32bit + assign $1\alu_shift_rot0_sr_op__is_signed$next[0:0]$11582 \alu_shift_rot0_sr_op__is_signed + assign $1\alu_shift_rot0_sr_op__oe__oe$next[0:0]$11583 \alu_shift_rot0_sr_op__oe__oe + assign $1\alu_shift_rot0_sr_op__oe__ok$next[0:0]$11584 \alu_shift_rot0_sr_op__oe__ok + assign $1\alu_shift_rot0_sr_op__output_carry$next[0:0]$11585 \alu_shift_rot0_sr_op__output_carry + assign $1\alu_shift_rot0_sr_op__output_cr$next[0:0]$11586 \alu_shift_rot0_sr_op__output_cr + assign $1\alu_shift_rot0_sr_op__rc__ok$next[0:0]$11587 \alu_shift_rot0_sr_op__rc__ok + assign $1\alu_shift_rot0_sr_op__rc__rc$next[0:0]$11588 \alu_shift_rot0_sr_op__rc__rc + assign $1\alu_shift_rot0_sr_op__write_cr0$next[0:0]$11589 \alu_shift_rot0_sr_op__write_cr0 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $2\alu_shift_rot0_sr_op__imm_data__data$next[63:0]$11590 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $2\alu_shift_rot0_sr_op__imm_data__ok$next[0:0]$11591 1'0 + assign $2\alu_shift_rot0_sr_op__rc__rc$next[0:0]$11595 1'0 + assign $2\alu_shift_rot0_sr_op__rc__ok$next[0:0]$11594 1'0 + assign $2\alu_shift_rot0_sr_op__oe__oe$next[0:0]$11592 1'0 + assign $2\alu_shift_rot0_sr_op__oe__ok$next[0:0]$11593 1'0 + case + assign $2\alu_shift_rot0_sr_op__imm_data__data$next[63:0]$11590 $1\alu_shift_rot0_sr_op__imm_data__data$next[63:0]$11575 + assign $2\alu_shift_rot0_sr_op__imm_data__ok$next[0:0]$11591 $1\alu_shift_rot0_sr_op__imm_data__ok$next[0:0]$11576 + assign $2\alu_shift_rot0_sr_op__oe__oe$next[0:0]$11592 $1\alu_shift_rot0_sr_op__oe__oe$next[0:0]$11583 + assign $2\alu_shift_rot0_sr_op__oe__ok$next[0:0]$11593 $1\alu_shift_rot0_sr_op__oe__ok$next[0:0]$11584 + assign $2\alu_shift_rot0_sr_op__rc__ok$next[0:0]$11594 $1\alu_shift_rot0_sr_op__rc__ok$next[0:0]$11587 + assign $2\alu_shift_rot0_sr_op__rc__rc$next[0:0]$11595 $1\alu_shift_rot0_sr_op__rc__rc$next[0:0]$11588 + end + sync always + update \alu_shift_rot0_sr_op__fn_unit$next $0\alu_shift_rot0_sr_op__fn_unit$next[11:0]$11558 + update \alu_shift_rot0_sr_op__imm_data__data$next $0\alu_shift_rot0_sr_op__imm_data__data$next[63:0]$11559 + update \alu_shift_rot0_sr_op__imm_data__ok$next $0\alu_shift_rot0_sr_op__imm_data__ok$next[0:0]$11560 + update \alu_shift_rot0_sr_op__input_carry$next $0\alu_shift_rot0_sr_op__input_carry$next[1:0]$11561 + update \alu_shift_rot0_sr_op__input_cr$next $0\alu_shift_rot0_sr_op__input_cr$next[0:0]$11562 + update \alu_shift_rot0_sr_op__insn$next $0\alu_shift_rot0_sr_op__insn$next[31:0]$11563 + update \alu_shift_rot0_sr_op__insn_type$next $0\alu_shift_rot0_sr_op__insn_type$next[6:0]$11564 + update \alu_shift_rot0_sr_op__is_32bit$next $0\alu_shift_rot0_sr_op__is_32bit$next[0:0]$11565 + update \alu_shift_rot0_sr_op__is_signed$next $0\alu_shift_rot0_sr_op__is_signed$next[0:0]$11566 + update \alu_shift_rot0_sr_op__oe__oe$next $0\alu_shift_rot0_sr_op__oe__oe$next[0:0]$11567 + update \alu_shift_rot0_sr_op__oe__ok$next $0\alu_shift_rot0_sr_op__oe__ok$next[0:0]$11568 + update \alu_shift_rot0_sr_op__output_carry$next $0\alu_shift_rot0_sr_op__output_carry$next[0:0]$11569 + update \alu_shift_rot0_sr_op__output_cr$next $0\alu_shift_rot0_sr_op__output_cr$next[0:0]$11570 + update \alu_shift_rot0_sr_op__rc__ok$next $0\alu_shift_rot0_sr_op__rc__ok$next[0:0]$11571 + update \alu_shift_rot0_sr_op__rc__rc$next $0\alu_shift_rot0_sr_op__rc__rc$next[0:0]$11572 + update \alu_shift_rot0_sr_op__write_cr0$next $0\alu_shift_rot0_sr_op__write_cr0$next[0:0]$11573 + end + attribute \src "issuer_ls180.v:171154.3-171175.6" + process $proc$issuer_ls180.v:171154$11596 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\data_r0__o$next[63:0]$11597 $2\data_r0__o$next[63:0]$11601 + assign { } { } + assign $0\data_r0__o_ok$next[0:0]$11598 $3\data_r0__o_ok$next[0:0]$11603 + attribute \src "issuer_ls180.v:171155.5-171155.29" + switch \initial + attribute \src "issuer_ls180.v:171155.9-171155.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" + switch \alu_pulse + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $1\data_r0__o_ok$next[0:0]$11600 $1\data_r0__o$next[63:0]$11599 } { \o_ok \alu_shift_rot0_o } + case + assign $1\data_r0__o$next[63:0]$11599 \data_r0__o + assign $1\data_r0__o_ok$next[0:0]$11600 \data_r0__o_ok + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" + switch \cu_issue_i + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $2\data_r0__o_ok$next[0:0]$11602 $2\data_r0__o$next[63:0]$11601 } 65'00000000000000000000000000000000000000000000000000000000000000000 + case + assign $2\data_r0__o$next[63:0]$11601 $1\data_r0__o$next[63:0]$11599 + assign $2\data_r0__o_ok$next[0:0]$11602 $1\data_r0__o_ok$next[0:0]$11600 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\data_r0__o_ok$next[0:0]$11603 1'0 + case + assign $3\data_r0__o_ok$next[0:0]$11603 $2\data_r0__o_ok$next[0:0]$11602 + end + sync always + update \data_r0__o$next $0\data_r0__o$next[63:0]$11597 + update \data_r0__o_ok$next $0\data_r0__o_ok$next[0:0]$11598 + end + attribute \src "issuer_ls180.v:171176.3-171197.6" + process $proc$issuer_ls180.v:171176$11604 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\data_r1__cr_a$next[3:0]$11605 $2\data_r1__cr_a$next[3:0]$11609 + assign { } { } + assign $0\data_r1__cr_a_ok$next[0:0]$11606 $3\data_r1__cr_a_ok$next[0:0]$11611 + attribute \src "issuer_ls180.v:171177.5-171177.29" + switch \initial + attribute \src "issuer_ls180.v:171177.9-171177.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" + switch \alu_pulse + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $1\data_r1__cr_a_ok$next[0:0]$11608 $1\data_r1__cr_a$next[3:0]$11607 } { \cr_a_ok \alu_shift_rot0_cr_a } + case + assign $1\data_r1__cr_a$next[3:0]$11607 \data_r1__cr_a + assign $1\data_r1__cr_a_ok$next[0:0]$11608 \data_r1__cr_a_ok + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" + switch \cu_issue_i + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $2\data_r1__cr_a_ok$next[0:0]$11610 $2\data_r1__cr_a$next[3:0]$11609 } 5'00000 + case + assign $2\data_r1__cr_a$next[3:0]$11609 $1\data_r1__cr_a$next[3:0]$11607 + assign $2\data_r1__cr_a_ok$next[0:0]$11610 $1\data_r1__cr_a_ok$next[0:0]$11608 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\data_r1__cr_a_ok$next[0:0]$11611 1'0 + case + assign $3\data_r1__cr_a_ok$next[0:0]$11611 $2\data_r1__cr_a_ok$next[0:0]$11610 + end + sync always + update \data_r1__cr_a$next $0\data_r1__cr_a$next[3:0]$11605 + update \data_r1__cr_a_ok$next $0\data_r1__cr_a_ok$next[0:0]$11606 + end + attribute \src "issuer_ls180.v:171198.3-171219.6" + process $proc$issuer_ls180.v:171198$11612 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\data_r2__xer_ca$next[1:0]$11613 $2\data_r2__xer_ca$next[1:0]$11617 + assign { } { } + assign $0\data_r2__xer_ca_ok$next[0:0]$11614 $3\data_r2__xer_ca_ok$next[0:0]$11619 + attribute \src "issuer_ls180.v:171199.5-171199.29" + switch \initial + attribute \src "issuer_ls180.v:171199.9-171199.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" + switch \alu_pulse + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $1\data_r2__xer_ca_ok$next[0:0]$11616 $1\data_r2__xer_ca$next[1:0]$11615 } { \xer_ca_ok \alu_shift_rot0_xer_ca } + case + assign $1\data_r2__xer_ca$next[1:0]$11615 \data_r2__xer_ca + assign $1\data_r2__xer_ca_ok$next[0:0]$11616 \data_r2__xer_ca_ok + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" + switch \cu_issue_i + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $2\data_r2__xer_ca_ok$next[0:0]$11618 $2\data_r2__xer_ca$next[1:0]$11617 } 3'000 + case + assign $2\data_r2__xer_ca$next[1:0]$11617 $1\data_r2__xer_ca$next[1:0]$11615 + assign $2\data_r2__xer_ca_ok$next[0:0]$11618 $1\data_r2__xer_ca_ok$next[0:0]$11616 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\data_r2__xer_ca_ok$next[0:0]$11619 1'0 + case + assign $3\data_r2__xer_ca_ok$next[0:0]$11619 $2\data_r2__xer_ca_ok$next[0:0]$11618 + end + sync always + update \data_r2__xer_ca$next $0\data_r2__xer_ca$next[1:0]$11613 + update \data_r2__xer_ca_ok$next $0\data_r2__xer_ca_ok$next[0:0]$11614 + end + attribute \src "issuer_ls180.v:171220.3-171229.6" + process $proc$issuer_ls180.v:171220$11620 + assign { } { } + assign { } { } + assign $0\src_r0$next[63:0]$11621 $1\src_r0$next[63:0]$11622 + attribute \src "issuer_ls180.v:171221.5-171221.29" + switch \initial + attribute \src "issuer_ls180.v:171221.9-171221.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" + switch \src_l_q_src [0] + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\src_r0$next[63:0]$11622 \src1_i + case + assign $1\src_r0$next[63:0]$11622 \src_r0 + end + sync always + update \src_r0$next $0\src_r0$next[63:0]$11621 + end + attribute \src "issuer_ls180.v:171230.3-171239.6" + process $proc$issuer_ls180.v:171230$11623 + assign { } { } + assign { } { } + assign $0\src_r1$next[63:0]$11624 $1\src_r1$next[63:0]$11625 + attribute \src "issuer_ls180.v:171231.5-171231.29" + switch \initial + attribute \src "issuer_ls180.v:171231.9-171231.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" + switch \src_sel + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\src_r1$next[63:0]$11625 \src_or_imm + case + assign $1\src_r1$next[63:0]$11625 \src_r1 + end + sync always + update \src_r1$next $0\src_r1$next[63:0]$11624 + end + attribute \src "issuer_ls180.v:171240.3-171249.6" + process $proc$issuer_ls180.v:171240$11626 + assign { } { } + assign { } { } + assign $0\src_r2$next[63:0]$11627 $1\src_r2$next[63:0]$11628 + attribute \src "issuer_ls180.v:171241.5-171241.29" + switch \initial + attribute \src "issuer_ls180.v:171241.9-171241.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" + switch \src_l_q_src [2] + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\src_r2$next[63:0]$11628 \src3_i + case + assign $1\src_r2$next[63:0]$11628 \src_r2 + end + sync always + update \src_r2$next $0\src_r2$next[63:0]$11627 + end + attribute \src "issuer_ls180.v:171250.3-171259.6" + process $proc$issuer_ls180.v:171250$11629 + assign { } { } + assign { } { } + assign $0\src_r3$next[0:0]$11630 $1\src_r3$next[0:0]$11631 + attribute \src "issuer_ls180.v:171251.5-171251.29" + switch \initial + attribute \src "issuer_ls180.v:171251.9-171251.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" + switch \src_l_q_src [3] + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\src_r3$next[0:0]$11631 \src4_i + case + assign $1\src_r3$next[0:0]$11631 \src_r3 + end + sync always + update \src_r3$next $0\src_r3$next[0:0]$11630 + end + attribute \src "issuer_ls180.v:171260.3-171269.6" + process $proc$issuer_ls180.v:171260$11632 + assign { } { } + assign { } { } + assign $0\src_r4$next[1:0]$11633 $1\src_r4$next[1:0]$11634 + attribute \src "issuer_ls180.v:171261.5-171261.29" + switch \initial + attribute \src "issuer_ls180.v:171261.9-171261.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" + switch \src_l_q_src [4] + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\src_r4$next[1:0]$11634 \src5_i + case + assign $1\src_r4$next[1:0]$11634 \src_r4 + end + sync always + update \src_r4$next $0\src_r4$next[1:0]$11633 + end + attribute \src "issuer_ls180.v:171270.3-171278.6" + process $proc$issuer_ls180.v:171270$11635 + assign { } { } + assign { } { } + assign $0\alui_l_r_alui$next[0:0]$11636 $1\alui_l_r_alui$next[0:0]$11637 + attribute \src "issuer_ls180.v:171271.5-171271.29" + switch \initial + attribute \src "issuer_ls180.v:171271.9-171271.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\alui_l_r_alui$next[0:0]$11637 1'1 + case + assign $1\alui_l_r_alui$next[0:0]$11637 \$90 + end + sync always + update \alui_l_r_alui$next $0\alui_l_r_alui$next[0:0]$11636 + end + attribute \src "issuer_ls180.v:171279.3-171287.6" + process $proc$issuer_ls180.v:171279$11638 + assign { } { } + assign { } { } + assign $0\alu_l_r_alu$next[0:0]$11639 $1\alu_l_r_alu$next[0:0]$11640 + attribute \src "issuer_ls180.v:171280.5-171280.29" + switch \initial + attribute \src "issuer_ls180.v:171280.9-171280.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\alu_l_r_alu$next[0:0]$11640 1'1 + case + assign $1\alu_l_r_alu$next[0:0]$11640 \$92 + end + sync always + update \alu_l_r_alu$next $0\alu_l_r_alu$next[0:0]$11639 + end + attribute \src "issuer_ls180.v:171288.3-171297.6" + process $proc$issuer_ls180.v:171288$11641 + assign { } { } + assign { } { } + assign $0\dest1_o[63:0] $1\dest1_o[63:0] + attribute \src "issuer_ls180.v:171289.5-171289.29" + switch \initial + attribute \src "issuer_ls180.v:171289.9-171289.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" + switch \$114 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dest1_o[63:0] \data_r0__o + case + assign $1\dest1_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \dest1_o $0\dest1_o[63:0] + end + attribute \src "issuer_ls180.v:171298.3-171307.6" + process $proc$issuer_ls180.v:171298$11642 + assign { } { } + assign { } { } + assign $0\dest2_o[3:0] $1\dest2_o[3:0] + attribute \src "issuer_ls180.v:171299.5-171299.29" + switch \initial + attribute \src "issuer_ls180.v:171299.9-171299.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" + switch \$116 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dest2_o[3:0] \data_r1__cr_a + case + assign $1\dest2_o[3:0] 4'0000 + end + sync always + update \dest2_o $0\dest2_o[3:0] + end + attribute \src "issuer_ls180.v:171308.3-171317.6" + process $proc$issuer_ls180.v:171308$11643 + assign { } { } + assign { } { } + assign $0\dest3_o[1:0] $1\dest3_o[1:0] + attribute \src "issuer_ls180.v:171309.5-171309.29" + switch \initial + attribute \src "issuer_ls180.v:171309.9-171309.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" + switch \$118 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dest3_o[1:0] \data_r2__xer_ca + case + assign $1\dest3_o[1:0] 2'00 + end + sync always + update \dest3_o $0\dest3_o[1:0] + end + attribute \src "issuer_ls180.v:171318.3-171326.6" + process $proc$issuer_ls180.v:171318$11644 + assign { } { } + assign { } { } + assign $0\prev_wr_go$next[2:0]$11645 $1\prev_wr_go$next[2:0]$11646 + attribute \src "issuer_ls180.v:171319.5-171319.29" + switch \initial + attribute \src "issuer_ls180.v:171319.9-171319.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\prev_wr_go$next[2:0]$11646 3'000 + case + assign $1\prev_wr_go$next[2:0]$11646 \$20 + end + sync always + update \prev_wr_go$next $0\prev_wr_go$next[2:0]$11645 + end + connect \$100 $not$issuer_ls180.v:170791$11425_Y + connect \$102 $and$issuer_ls180.v:170792$11426_Y + connect \$104 $and$issuer_ls180.v:170793$11427_Y + connect \$106 $and$issuer_ls180.v:170794$11428_Y + connect \$108 $and$issuer_ls180.v:170795$11429_Y + connect \$10 $and$issuer_ls180.v:170796$11430_Y + connect \$110 $and$issuer_ls180.v:170797$11431_Y + connect \$112 $and$issuer_ls180.v:170798$11432_Y + connect \$114 $and$issuer_ls180.v:170799$11433_Y + connect \$116 $and$issuer_ls180.v:170800$11434_Y + connect \$118 $and$issuer_ls180.v:170801$11435_Y + connect \$12 $not$issuer_ls180.v:170802$11436_Y + connect \$14 $and$issuer_ls180.v:170803$11437_Y + connect \$16 $not$issuer_ls180.v:170804$11438_Y + connect \$18 $and$issuer_ls180.v:170805$11439_Y + connect \$20 $and$issuer_ls180.v:170806$11440_Y + connect \$24 $not$issuer_ls180.v:170807$11441_Y + connect \$26 $and$issuer_ls180.v:170808$11442_Y + connect \$23 $reduce_or$issuer_ls180.v:170809$11443_Y + connect \$22 $not$issuer_ls180.v:170810$11444_Y + connect \$2 $and$issuer_ls180.v:170811$11445_Y + connect \$30 $and$issuer_ls180.v:170812$11446_Y + connect \$32 $reduce_or$issuer_ls180.v:170813$11447_Y + connect \$34 $reduce_or$issuer_ls180.v:170814$11448_Y + connect \$36 $or$issuer_ls180.v:170815$11449_Y + connect \$38 $not$issuer_ls180.v:170816$11450_Y + connect \$40 $and$issuer_ls180.v:170817$11451_Y + connect \$42 $and$issuer_ls180.v:170818$11452_Y + connect \$44 $eq$issuer_ls180.v:170819$11453_Y + connect \$46 $and$issuer_ls180.v:170820$11454_Y + connect \$48 $eq$issuer_ls180.v:170821$11455_Y + connect \$50 $and$issuer_ls180.v:170822$11456_Y + connect \$52 $and$issuer_ls180.v:170823$11457_Y + connect \$54 $and$issuer_ls180.v:170824$11458_Y + connect \$56 $or$issuer_ls180.v:170825$11459_Y + connect \$58 $or$issuer_ls180.v:170826$11460_Y + connect \$5 $not$issuer_ls180.v:170827$11461_Y + connect \$60 $or$issuer_ls180.v:170828$11462_Y + connect \$62 $or$issuer_ls180.v:170829$11463_Y + connect \$64 $and$issuer_ls180.v:170830$11464_Y + connect \$66 $and$issuer_ls180.v:170831$11465_Y + connect \$68 $or$issuer_ls180.v:170832$11466_Y + connect \$70 $and$issuer_ls180.v:170833$11467_Y + connect \$72 $and$issuer_ls180.v:170834$11468_Y + connect \$74 $and$issuer_ls180.v:170835$11469_Y + connect \$76 $ternary$issuer_ls180.v:170836$11470_Y + connect \$78 $ternary$issuer_ls180.v:170837$11471_Y + connect \$7 $or$issuer_ls180.v:170838$11472_Y + connect \$80 $ternary$issuer_ls180.v:170839$11473_Y + connect \$82 $ternary$issuer_ls180.v:170840$11474_Y + connect \$84 $ternary$issuer_ls180.v:170841$11475_Y + connect \$86 $ternary$issuer_ls180.v:170842$11476_Y + connect \$88 $ternary$issuer_ls180.v:170843$11477_Y + connect \$4 $reduce_and$issuer_ls180.v:170844$11478_Y + connect \$90 $and$issuer_ls180.v:170845$11479_Y + connect \$92 $and$issuer_ls180.v:170846$11480_Y + connect \$94 $and$issuer_ls180.v:170847$11481_Y + connect \$96 $not$issuer_ls180.v:170848$11482_Y + connect \$98 $and$issuer_ls180.v:170849$11483_Y + connect \cu_go_die_i 1'0 + connect \cu_shadown_i 1'1 + connect \cu_wr__rel_o \$112 + connect \cu_rd__rel_o \$102 + connect \cu_busy_o \opc_l_q_opc + connect \alu_l_s_alu \all_rd_pulse + connect \alu_shift_rot0_n_ready_i \alu_l_q_alu + connect \alui_l_s_alui \all_rd_pulse + connect \alu_shift_rot0_p_valid_i \alui_l_q_alui + connect \alu_shift_rot0_xer_ca$1 \$88 + connect \alu_shift_rot0_xer_so \$86 + connect \alu_shift_rot0_rc \$84 + connect \alu_shift_rot0_rb \$82 + connect \alu_shift_rot0_ra \$80 + connect \src_or_imm \$78 + connect \src_sel \$76 + connect \cu_wrmask_o { \$74 \$72 \$70 } + connect \reset_r \$62 + connect \reset_w \$60 + connect \rst_r \$58 + connect \reset \$56 + connect \wr_any \$36 + connect \cu_done_o \$30 + connect \alu_pulsem { \alu_pulse \alu_pulse \alu_pulse } + connect \alu_pulse \alu_done_rise + connect \alu_done_rise \$18 + connect \alu_done_dly$next \alu_done + connect \alu_done \alu_shift_rot0_n_valid_o + connect \all_rd_pulse \all_rd_rise + connect \all_rd_rise \$14 + connect \all_rd_dly$next \all_rd + connect \all_rd \$10 +end +attribute \src "issuer_ls180.v:171363.1-171540.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.spr" +attribute \generator "nMigen" +module \spr + attribute \src "issuer_ls180.v:171512.3-171515.6" + wire width 7 $0$memwr$\memory$issuer_ls180.v:171514$11800_ADDR[6:0]$11803 + attribute \src "issuer_ls180.v:171512.3-171515.6" + wire width 64 $0$memwr$\memory$issuer_ls180.v:171514$11800_DATA[63:0]$11804 + attribute \src "issuer_ls180.v:171512.3-171515.6" + wire width 64 $0$memwr$\memory$issuer_ls180.v:171514$11800_EN[63:0]$11805 + attribute \src "issuer_ls180.v:171512.3-171515.6" + wire width 7 $0\_0_[6:0] + attribute \src "issuer_ls180.v:171364.7-171364.20" + wire $0\initial[0:0] + attribute \src "issuer_ls180.v:171517.3-171525.6" + wire $0\ren_delay$next[0:0]$11808 + attribute \src "issuer_ls180.v:171396.3-171397.35" + wire $0\ren_delay[0:0] + attribute \src "issuer_ls180.v:171526.3-171535.6" + wire width 64 $0\spr1__data_o[63:0] + attribute \src "issuer_ls180.v:171517.3-171525.6" + wire $1\ren_delay$next[0:0]$11809 + attribute \src "issuer_ls180.v:171380.7-171380.23" + wire $1\ren_delay[0:0] + attribute \src "issuer_ls180.v:171526.3-171535.6" + wire width 64 $1\spr1__data_o[63:0] + attribute \src "issuer_ls180.v:171516.26-171516.32" + wire width 64 $memrd$\memory$issuer_ls180.v:171516$11806_DATA + attribute \src "issuer_ls180.v:0.0-0.0" + wire width 7 $memwr$\memory$issuer_ls180.v:171514$11800_ADDR + attribute \src "issuer_ls180.v:0.0-0.0" + wire width 64 $memwr$\memory$issuer_ls180.v:171514$11800_DATA + attribute \src "issuer_ls180.v:0.0-0.0" + wire width 64 $memwr$\memory$issuer_ls180.v:171514$11800_EN + attribute \src "issuer_ls180.v:171511.13-171511.16" + wire width 7 \_0_ + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" + wire input 8 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" + wire input 7 \coresync_rst + attribute \src "issuer_ls180.v:171364.7-171364.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:210" + wire width 7 \memory_r_addr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:210" + wire width 64 \memory_r_data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:218" + wire width 7 \memory_w_addr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:218" + wire width 64 \memory_w_data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:218" + wire \memory_w_en + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:243" + wire \ren_delay + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:243" + wire \ren_delay$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 7 input 2 \spr1__addr + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 7 input 5 \spr1__addr$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 64 input 4 \spr1__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 64 output 1 \spr1__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire input 3 \spr1__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire input 6 \spr1__wen + attribute \src "issuer_ls180.v:171398.14-171398.20" + memory width 64 size 110 \memory + attribute \src "issuer_ls180.v:0.0-0.0" + cell $meminit $meminit$\memory$issuer_ls180.v:0$11811 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 11811 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 0 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "issuer_ls180.v:0.0-0.0" + cell $meminit $meminit$\memory$issuer_ls180.v:0$11812 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 11812 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 1 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "issuer_ls180.v:0.0-0.0" + cell $meminit $meminit$\memory$issuer_ls180.v:0$11813 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 11813 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 2 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "issuer_ls180.v:0.0-0.0" + cell $meminit $meminit$\memory$issuer_ls180.v:0$11814 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 11814 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 3 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "issuer_ls180.v:0.0-0.0" + cell $meminit $meminit$\memory$issuer_ls180.v:0$11815 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 11815 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 4 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "issuer_ls180.v:0.0-0.0" + cell $meminit $meminit$\memory$issuer_ls180.v:0$11816 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 11816 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 5 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "issuer_ls180.v:0.0-0.0" + cell $meminit $meminit$\memory$issuer_ls180.v:0$11817 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 11817 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 6 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "issuer_ls180.v:0.0-0.0" + cell $meminit $meminit$\memory$issuer_ls180.v:0$11818 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 11818 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 7 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "issuer_ls180.v:0.0-0.0" + cell $meminit $meminit$\memory$issuer_ls180.v:0$11819 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 11819 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 8 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "issuer_ls180.v:0.0-0.0" + cell $meminit $meminit$\memory$issuer_ls180.v:0$11820 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 11820 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 9 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "issuer_ls180.v:0.0-0.0" + cell $meminit $meminit$\memory$issuer_ls180.v:0$11821 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 11821 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 10 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "issuer_ls180.v:0.0-0.0" + cell $meminit $meminit$\memory$issuer_ls180.v:0$11822 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 11822 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 11 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "issuer_ls180.v:0.0-0.0" + cell $meminit $meminit$\memory$issuer_ls180.v:0$11823 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 11823 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 12 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "issuer_ls180.v:0.0-0.0" + cell $meminit $meminit$\memory$issuer_ls180.v:0$11824 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 11824 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 13 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "issuer_ls180.v:0.0-0.0" + cell $meminit $meminit$\memory$issuer_ls180.v:0$11825 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 11825 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 14 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "issuer_ls180.v:0.0-0.0" + cell $meminit $meminit$\memory$issuer_ls180.v:0$11826 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 11826 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 15 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "issuer_ls180.v:0.0-0.0" + cell $meminit $meminit$\memory$issuer_ls180.v:0$11827 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 11827 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 16 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "issuer_ls180.v:0.0-0.0" + cell $meminit $meminit$\memory$issuer_ls180.v:0$11828 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 11828 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 17 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "issuer_ls180.v:0.0-0.0" + cell $meminit $meminit$\memory$issuer_ls180.v:0$11829 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 11829 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 18 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "issuer_ls180.v:0.0-0.0" + cell $meminit $meminit$\memory$issuer_ls180.v:0$11830 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 11830 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 19 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "issuer_ls180.v:0.0-0.0" + cell $meminit $meminit$\memory$issuer_ls180.v:0$11831 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 11831 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 20 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "issuer_ls180.v:0.0-0.0" + cell $meminit $meminit$\memory$issuer_ls180.v:0$11832 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 11832 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 21 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "issuer_ls180.v:0.0-0.0" + cell $meminit $meminit$\memory$issuer_ls180.v:0$11833 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 11833 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 22 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "issuer_ls180.v:0.0-0.0" + cell $meminit $meminit$\memory$issuer_ls180.v:0$11834 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 11834 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 23 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "issuer_ls180.v:0.0-0.0" + cell $meminit $meminit$\memory$issuer_ls180.v:0$11835 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 11835 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 24 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "issuer_ls180.v:0.0-0.0" + cell $meminit $meminit$\memory$issuer_ls180.v:0$11836 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 11836 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 25 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "issuer_ls180.v:0.0-0.0" + cell $meminit $meminit$\memory$issuer_ls180.v:0$11837 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 11837 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 26 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "issuer_ls180.v:0.0-0.0" + cell $meminit $meminit$\memory$issuer_ls180.v:0$11838 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 11838 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 27 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "issuer_ls180.v:0.0-0.0" + cell $meminit $meminit$\memory$issuer_ls180.v:0$11839 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 11839 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 28 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "issuer_ls180.v:0.0-0.0" + cell $meminit $meminit$\memory$issuer_ls180.v:0$11840 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 11840 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 29 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "issuer_ls180.v:0.0-0.0" + cell $meminit $meminit$\memory$issuer_ls180.v:0$11841 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 11841 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 30 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "issuer_ls180.v:0.0-0.0" + cell $meminit $meminit$\memory$issuer_ls180.v:0$11842 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 11842 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 31 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "issuer_ls180.v:0.0-0.0" + cell $meminit $meminit$\memory$issuer_ls180.v:0$11843 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 11843 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 32 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "issuer_ls180.v:0.0-0.0" + cell $meminit $meminit$\memory$issuer_ls180.v:0$11844 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 11844 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 33 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "issuer_ls180.v:0.0-0.0" + cell $meminit $meminit$\memory$issuer_ls180.v:0$11845 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 11845 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 34 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "issuer_ls180.v:0.0-0.0" + cell $meminit $meminit$\memory$issuer_ls180.v:0$11846 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 11846 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 35 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "issuer_ls180.v:0.0-0.0" + cell $meminit $meminit$\memory$issuer_ls180.v:0$11847 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 11847 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 36 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "issuer_ls180.v:0.0-0.0" + cell $meminit $meminit$\memory$issuer_ls180.v:0$11848 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 11848 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 37 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "issuer_ls180.v:0.0-0.0" + cell $meminit $meminit$\memory$issuer_ls180.v:0$11849 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 11849 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 38 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "issuer_ls180.v:0.0-0.0" + cell $meminit $meminit$\memory$issuer_ls180.v:0$11850 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 11850 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 39 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "issuer_ls180.v:0.0-0.0" + cell $meminit $meminit$\memory$issuer_ls180.v:0$11851 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 11851 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 40 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "issuer_ls180.v:0.0-0.0" + cell $meminit $meminit$\memory$issuer_ls180.v:0$11852 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 11852 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 41 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "issuer_ls180.v:0.0-0.0" + cell $meminit $meminit$\memory$issuer_ls180.v:0$11853 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 11853 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 42 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "issuer_ls180.v:0.0-0.0" + cell $meminit $meminit$\memory$issuer_ls180.v:0$11854 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 11854 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 43 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "issuer_ls180.v:0.0-0.0" + cell $meminit $meminit$\memory$issuer_ls180.v:0$11855 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 11855 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 44 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "issuer_ls180.v:0.0-0.0" + cell $meminit $meminit$\memory$issuer_ls180.v:0$11856 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 11856 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 45 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "issuer_ls180.v:0.0-0.0" + cell $meminit $meminit$\memory$issuer_ls180.v:0$11857 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 11857 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 46 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "issuer_ls180.v:0.0-0.0" + cell $meminit $meminit$\memory$issuer_ls180.v:0$11858 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 11858 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 47 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "issuer_ls180.v:0.0-0.0" + cell $meminit $meminit$\memory$issuer_ls180.v:0$11859 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 11859 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 48 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "issuer_ls180.v:0.0-0.0" + cell $meminit $meminit$\memory$issuer_ls180.v:0$11860 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 11860 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 49 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "issuer_ls180.v:0.0-0.0" + cell $meminit $meminit$\memory$issuer_ls180.v:0$11861 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 11861 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 50 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "issuer_ls180.v:0.0-0.0" + cell $meminit $meminit$\memory$issuer_ls180.v:0$11862 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 11862 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 51 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "issuer_ls180.v:0.0-0.0" + cell $meminit $meminit$\memory$issuer_ls180.v:0$11863 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 11863 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 52 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "issuer_ls180.v:0.0-0.0" + cell $meminit $meminit$\memory$issuer_ls180.v:0$11864 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 11864 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 53 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "issuer_ls180.v:0.0-0.0" + cell $meminit $meminit$\memory$issuer_ls180.v:0$11865 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 11865 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 54 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "issuer_ls180.v:0.0-0.0" + cell $meminit $meminit$\memory$issuer_ls180.v:0$11866 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 11866 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 55 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "issuer_ls180.v:0.0-0.0" + cell $meminit $meminit$\memory$issuer_ls180.v:0$11867 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 11867 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 56 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "issuer_ls180.v:0.0-0.0" + cell $meminit $meminit$\memory$issuer_ls180.v:0$11868 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 11868 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 57 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "issuer_ls180.v:0.0-0.0" + cell $meminit $meminit$\memory$issuer_ls180.v:0$11869 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 11869 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 58 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "issuer_ls180.v:0.0-0.0" + cell $meminit $meminit$\memory$issuer_ls180.v:0$11870 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 11870 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 59 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "issuer_ls180.v:0.0-0.0" + cell $meminit $meminit$\memory$issuer_ls180.v:0$11871 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 11871 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 60 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "issuer_ls180.v:0.0-0.0" + cell $meminit $meminit$\memory$issuer_ls180.v:0$11872 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 11872 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 61 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "issuer_ls180.v:0.0-0.0" + cell $meminit $meminit$\memory$issuer_ls180.v:0$11873 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 11873 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 62 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "issuer_ls180.v:0.0-0.0" + cell $meminit $meminit$\memory$issuer_ls180.v:0$11874 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 11874 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 63 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "issuer_ls180.v:0.0-0.0" + cell $meminit $meminit$\memory$issuer_ls180.v:0$11875 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 11875 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 64 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "issuer_ls180.v:0.0-0.0" + cell $meminit $meminit$\memory$issuer_ls180.v:0$11876 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 11876 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 65 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "issuer_ls180.v:0.0-0.0" + cell $meminit $meminit$\memory$issuer_ls180.v:0$11877 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 11877 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 66 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "issuer_ls180.v:0.0-0.0" + cell $meminit $meminit$\memory$issuer_ls180.v:0$11878 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 11878 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 67 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "issuer_ls180.v:0.0-0.0" + cell $meminit $meminit$\memory$issuer_ls180.v:0$11879 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 11879 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 68 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "issuer_ls180.v:0.0-0.0" + cell $meminit $meminit$\memory$issuer_ls180.v:0$11880 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 11880 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 69 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "issuer_ls180.v:0.0-0.0" + cell $meminit $meminit$\memory$issuer_ls180.v:0$11881 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 11881 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 70 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "issuer_ls180.v:0.0-0.0" + cell $meminit $meminit$\memory$issuer_ls180.v:0$11882 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 11882 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 71 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "issuer_ls180.v:0.0-0.0" + cell $meminit $meminit$\memory$issuer_ls180.v:0$11883 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 11883 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 72 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "issuer_ls180.v:0.0-0.0" + cell $meminit $meminit$\memory$issuer_ls180.v:0$11884 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 11884 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 73 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "issuer_ls180.v:0.0-0.0" + cell $meminit $meminit$\memory$issuer_ls180.v:0$11885 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 11885 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 74 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "issuer_ls180.v:0.0-0.0" + cell $meminit $meminit$\memory$issuer_ls180.v:0$11886 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 11886 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 75 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "issuer_ls180.v:0.0-0.0" + cell $meminit $meminit$\memory$issuer_ls180.v:0$11887 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 11887 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 76 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "issuer_ls180.v:0.0-0.0" + cell $meminit $meminit$\memory$issuer_ls180.v:0$11888 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 11888 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 77 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "issuer_ls180.v:0.0-0.0" + cell $meminit $meminit$\memory$issuer_ls180.v:0$11889 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 11889 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 78 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "issuer_ls180.v:0.0-0.0" + cell $meminit $meminit$\memory$issuer_ls180.v:0$11890 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 11890 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 79 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "issuer_ls180.v:0.0-0.0" + cell $meminit $meminit$\memory$issuer_ls180.v:0$11891 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 11891 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 80 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "issuer_ls180.v:0.0-0.0" + cell $meminit $meminit$\memory$issuer_ls180.v:0$11892 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 11892 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 81 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "issuer_ls180.v:0.0-0.0" + cell $meminit $meminit$\memory$issuer_ls180.v:0$11893 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 11893 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 82 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "issuer_ls180.v:0.0-0.0" + cell $meminit $meminit$\memory$issuer_ls180.v:0$11894 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 11894 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 83 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "issuer_ls180.v:0.0-0.0" + cell $meminit $meminit$\memory$issuer_ls180.v:0$11895 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 11895 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 84 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "issuer_ls180.v:0.0-0.0" + cell $meminit $meminit$\memory$issuer_ls180.v:0$11896 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 11896 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 85 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "issuer_ls180.v:0.0-0.0" + cell $meminit $meminit$\memory$issuer_ls180.v:0$11897 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 11897 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 86 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "issuer_ls180.v:0.0-0.0" + cell $meminit $meminit$\memory$issuer_ls180.v:0$11898 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 11898 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 87 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "issuer_ls180.v:0.0-0.0" + cell $meminit $meminit$\memory$issuer_ls180.v:0$11899 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 11899 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 88 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "issuer_ls180.v:0.0-0.0" + cell $meminit $meminit$\memory$issuer_ls180.v:0$11900 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 11900 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 89 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "issuer_ls180.v:0.0-0.0" + cell $meminit $meminit$\memory$issuer_ls180.v:0$11901 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 11901 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 90 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "issuer_ls180.v:0.0-0.0" + cell $meminit $meminit$\memory$issuer_ls180.v:0$11902 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 11902 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 91 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "issuer_ls180.v:0.0-0.0" + cell $meminit $meminit$\memory$issuer_ls180.v:0$11903 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 11903 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 92 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "issuer_ls180.v:0.0-0.0" + cell $meminit $meminit$\memory$issuer_ls180.v:0$11904 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 11904 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 93 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "issuer_ls180.v:0.0-0.0" + cell $meminit $meminit$\memory$issuer_ls180.v:0$11905 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 11905 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 94 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "issuer_ls180.v:0.0-0.0" + cell $meminit $meminit$\memory$issuer_ls180.v:0$11906 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 11906 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 95 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "issuer_ls180.v:0.0-0.0" + cell $meminit $meminit$\memory$issuer_ls180.v:0$11907 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 11907 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 96 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "issuer_ls180.v:0.0-0.0" + cell $meminit $meminit$\memory$issuer_ls180.v:0$11908 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 11908 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 97 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "issuer_ls180.v:0.0-0.0" + cell $meminit $meminit$\memory$issuer_ls180.v:0$11909 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 11909 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 98 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "issuer_ls180.v:0.0-0.0" + cell $meminit $meminit$\memory$issuer_ls180.v:0$11910 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 11910 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 99 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "issuer_ls180.v:0.0-0.0" + cell $meminit $meminit$\memory$issuer_ls180.v:0$11911 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 11911 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 100 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "issuer_ls180.v:0.0-0.0" + cell $meminit $meminit$\memory$issuer_ls180.v:0$11912 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 11912 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 101 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "issuer_ls180.v:0.0-0.0" + cell $meminit $meminit$\memory$issuer_ls180.v:0$11913 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 11913 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 102 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "issuer_ls180.v:0.0-0.0" + cell $meminit $meminit$\memory$issuer_ls180.v:0$11914 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 11914 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 103 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "issuer_ls180.v:0.0-0.0" + cell $meminit $meminit$\memory$issuer_ls180.v:0$11915 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 11915 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 104 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "issuer_ls180.v:0.0-0.0" + cell $meminit $meminit$\memory$issuer_ls180.v:0$11916 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 11916 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 105 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "issuer_ls180.v:0.0-0.0" + cell $meminit $meminit$\memory$issuer_ls180.v:0$11917 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 11917 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 106 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "issuer_ls180.v:0.0-0.0" + cell $meminit $meminit$\memory$issuer_ls180.v:0$11918 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 11918 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 107 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "issuer_ls180.v:0.0-0.0" + cell $meminit $meminit$\memory$issuer_ls180.v:0$11919 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 11919 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 108 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "issuer_ls180.v:0.0-0.0" + cell $meminit $meminit$\memory$issuer_ls180.v:0$11920 + parameter \ABITS 32 + parameter \MEMID "\\memory" + parameter \PRIORITY 11920 + parameter \WIDTH 64 + parameter \WORDS 1 + connect \ADDR 109 + connect \DATA 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "issuer_ls180.v:171516.26-171516.32" + cell $memrd $memrd$\memory$issuer_ls180.v:171516$11806 + parameter \ABITS 7 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\memory" + parameter \TRANSPARENT 0 + parameter \WIDTH 64 + connect \ADDR \_0_ + connect \CLK 1'x + connect \DATA $memrd$\memory$issuer_ls180.v:171516$11806_DATA + connect \EN 1'x + end + attribute \src "issuer_ls180.v:0.0-0.0" + cell $memwr $memwr$\memory$issuer_ls180.v:0$11921 + parameter \ABITS 7 + parameter \CLK_ENABLE 0 + parameter \CLK_POLARITY 0 + parameter \MEMID "\\memory" + parameter \PRIORITY 11921 + parameter \WIDTH 64 + connect \ADDR $memwr$\memory$issuer_ls180.v:171514$11800_ADDR + connect \CLK 1'x + connect \DATA $memwr$\memory$issuer_ls180.v:171514$11800_DATA + connect \EN $memwr$\memory$issuer_ls180.v:171514$11800_EN + end + attribute \src "issuer_ls180.v:0.0-0.0" + process $proc$issuer_ls180.v:0$11924 + sync always + sync init + end + attribute \src "issuer_ls180.v:171364.7-171364.20" + process $proc$issuer_ls180.v:171364$11922 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "issuer_ls180.v:171380.7-171380.23" + process $proc$issuer_ls180.v:171380$11923 + assign { } { } + assign $1\ren_delay[0:0] 1'0 + sync always + sync init + update \ren_delay $1\ren_delay[0:0] + end + attribute \src "issuer_ls180.v:171396.3-171397.35" + process $proc$issuer_ls180.v:171396$11801 + assign { } { } + assign $0\ren_delay[0:0] \ren_delay$next + sync posedge \coresync_clk + update \ren_delay $0\ren_delay[0:0] + end + attribute \src "issuer_ls180.v:171512.3-171515.6" + process $proc$issuer_ls180.v:171512$11802 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0$memwr$\memory$issuer_ls180.v:171514$11800_ADDR[6:0]$11803 7'xxxxxxx + assign $0$memwr$\memory$issuer_ls180.v:171514$11800_DATA[63:0]$11804 64'xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx + assign $0$memwr$\memory$issuer_ls180.v:171514$11800_EN[63:0]$11805 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $0\_0_[6:0] \spr1__addr + attribute \src "issuer_ls180.v:171514.5-171514.59" + switch \spr1__wen + attribute \src "issuer_ls180.v:171514.9-171514.18" + case 1'1 + assign $0$memwr$\memory$issuer_ls180.v:171514$11800_ADDR[6:0]$11803 \spr1__addr$1 + assign $0$memwr$\memory$issuer_ls180.v:171514$11800_DATA[63:0]$11804 \spr1__data_i + assign $0$memwr$\memory$issuer_ls180.v:171514$11800_EN[63:0]$11805 64'1111111111111111111111111111111111111111111111111111111111111111 + case + end + sync posedge \coresync_clk + update \_0_ $0\_0_[6:0] + update $memwr$\memory$issuer_ls180.v:171514$11800_ADDR $0$memwr$\memory$issuer_ls180.v:171514$11800_ADDR[6:0]$11803 + update $memwr$\memory$issuer_ls180.v:171514$11800_DATA $0$memwr$\memory$issuer_ls180.v:171514$11800_DATA[63:0]$11804 + update $memwr$\memory$issuer_ls180.v:171514$11800_EN $0$memwr$\memory$issuer_ls180.v:171514$11800_EN[63:0]$11805 + end + attribute \src "issuer_ls180.v:171517.3-171525.6" + process $proc$issuer_ls180.v:171517$11807 + assign { } { } + assign { } { } + assign $0\ren_delay$next[0:0]$11808 $1\ren_delay$next[0:0]$11809 + attribute \src "issuer_ls180.v:171518.5-171518.29" + switch \initial + attribute \src "issuer_ls180.v:171518.9-171518.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\ren_delay$next[0:0]$11809 1'0 + case + assign $1\ren_delay$next[0:0]$11809 \spr1__ren + end + sync always + update \ren_delay$next $0\ren_delay$next[0:0]$11808 + end + attribute \src "issuer_ls180.v:171526.3-171535.6" + process $proc$issuer_ls180.v:171526$11810 + assign { } { } + assign { } { } + assign $0\spr1__data_o[63:0] $1\spr1__data_o[63:0] + attribute \src "issuer_ls180.v:171527.5-171527.29" + switch \initial + attribute \src "issuer_ls180.v:171527.9-171527.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:245" + switch \ren_delay + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\spr1__data_o[63:0] \memory_r_data + case + assign $1\spr1__data_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \spr1__data_o $0\spr1__data_o[63:0] + end + connect \memory_r_data $memrd$\memory$issuer_ls180.v:171516$11806_DATA + connect \memory_w_data \spr1__data_i + connect \memory_w_en \spr1__wen + connect \memory_w_addr \spr1__addr$1 + connect \memory_r_addr \spr1__addr +end +attribute \src "issuer_ls180.v:171544.1-172791.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.fus.spr0" +attribute \generator "nMigen" +module \spr0 + attribute \src "issuer_ls180.v:172288.3-172289.25" + wire $0\all_rd_dly[0:0] + attribute \src "issuer_ls180.v:172286.3-172287.40" + wire $0\alu_done_dly[0:0] + attribute \src "issuer_ls180.v:172682.3-172690.6" + wire $0\alu_l_r_alu$next[0:0]$12138 + attribute \src "issuer_ls180.v:172216.3-172217.39" + wire $0\alu_l_r_alu[0:0] + attribute \src "issuer_ls180.v:172468.3-172480.6" + wire width 12 $0\alu_spr0_spr_op__fn_unit$next[11:0]$12060 + attribute \src "issuer_ls180.v:172258.3-172259.65" + wire width 12 $0\alu_spr0_spr_op__fn_unit[11:0] + attribute \src "issuer_ls180.v:172468.3-172480.6" + wire width 32 $0\alu_spr0_spr_op__insn$next[31:0]$12061 + attribute \src "issuer_ls180.v:172260.3-172261.59" + wire width 32 $0\alu_spr0_spr_op__insn[31:0] + attribute \src "issuer_ls180.v:172468.3-172480.6" + wire width 7 $0\alu_spr0_spr_op__insn_type$next[6:0]$12062 + attribute \src "issuer_ls180.v:172256.3-172257.69" + wire width 7 $0\alu_spr0_spr_op__insn_type[6:0] + attribute \src "issuer_ls180.v:172468.3-172480.6" + wire $0\alu_spr0_spr_op__is_32bit$next[0:0]$12063 + attribute \src "issuer_ls180.v:172262.3-172263.67" + wire $0\alu_spr0_spr_op__is_32bit[0:0] + attribute \src "issuer_ls180.v:172673.3-172681.6" + wire $0\alui_l_r_alui$next[0:0]$12135 + attribute \src "issuer_ls180.v:172218.3-172219.43" + wire $0\alui_l_r_alui[0:0] + attribute \src "issuer_ls180.v:172481.3-172502.6" + wire width 64 $0\data_r0__o$next[63:0]$12069 + attribute \src "issuer_ls180.v:172252.3-172253.37" + wire width 64 $0\data_r0__o[63:0] + attribute \src "issuer_ls180.v:172481.3-172502.6" + wire $0\data_r0__o_ok$next[0:0]$12070 + attribute \src "issuer_ls180.v:172254.3-172255.43" + wire $0\data_r0__o_ok[0:0] + attribute \src "issuer_ls180.v:172503.3-172524.6" + wire width 64 $0\data_r1__spr1$next[63:0]$12077 + attribute \src "issuer_ls180.v:172248.3-172249.43" + wire width 64 $0\data_r1__spr1[63:0] + attribute \src "issuer_ls180.v:172503.3-172524.6" + wire $0\data_r1__spr1_ok$next[0:0]$12078 + attribute \src "issuer_ls180.v:172250.3-172251.49" + wire $0\data_r1__spr1_ok[0:0] + attribute \src "issuer_ls180.v:172525.3-172546.6" + wire width 64 $0\data_r2__fast1$next[63:0]$12085 + attribute \src "issuer_ls180.v:172244.3-172245.45" + wire width 64 $0\data_r2__fast1[63:0] + attribute \src "issuer_ls180.v:172525.3-172546.6" + wire $0\data_r2__fast1_ok$next[0:0]$12086 + attribute \src "issuer_ls180.v:172246.3-172247.51" + wire $0\data_r2__fast1_ok[0:0] + attribute \src "issuer_ls180.v:172547.3-172568.6" + wire $0\data_r3__xer_so$next[0:0]$12093 + attribute \src "issuer_ls180.v:172240.3-172241.47" + wire $0\data_r3__xer_so[0:0] + attribute \src "issuer_ls180.v:172547.3-172568.6" + wire $0\data_r3__xer_so_ok$next[0:0]$12094 + attribute \src "issuer_ls180.v:172242.3-172243.53" + wire $0\data_r3__xer_so_ok[0:0] + attribute \src "issuer_ls180.v:172569.3-172590.6" + wire width 2 $0\data_r4__xer_ov$next[1:0]$12101 + attribute \src "issuer_ls180.v:172236.3-172237.47" + wire width 2 $0\data_r4__xer_ov[1:0] + attribute \src "issuer_ls180.v:172569.3-172590.6" + wire $0\data_r4__xer_ov_ok$next[0:0]$12102 + attribute \src "issuer_ls180.v:172238.3-172239.53" + wire $0\data_r4__xer_ov_ok[0:0] + attribute \src "issuer_ls180.v:172591.3-172612.6" + wire width 2 $0\data_r5__xer_ca$next[1:0]$12109 + attribute \src "issuer_ls180.v:172232.3-172233.47" + wire width 2 $0\data_r5__xer_ca[1:0] + attribute \src "issuer_ls180.v:172591.3-172612.6" + wire $0\data_r5__xer_ca_ok$next[0:0]$12110 + attribute \src "issuer_ls180.v:172234.3-172235.53" + wire $0\data_r5__xer_ca_ok[0:0] + attribute \src "issuer_ls180.v:172691.3-172700.6" + wire width 64 $0\dest1_o[63:0] + attribute \src "issuer_ls180.v:172701.3-172710.6" + wire width 64 $0\dest2_o[63:0] + attribute \src "issuer_ls180.v:172711.3-172720.6" + wire width 64 $0\dest3_o[63:0] + attribute \src "issuer_ls180.v:172721.3-172730.6" + wire $0\dest4_o[0:0] + attribute \src "issuer_ls180.v:172731.3-172740.6" + wire width 2 $0\dest5_o[1:0] + attribute \src "issuer_ls180.v:172741.3-172750.6" + wire width 2 $0\dest6_o[1:0] + attribute \src "issuer_ls180.v:171545.7-171545.20" + wire $0\initial[0:0] + attribute \src "issuer_ls180.v:172423.3-172431.6" + wire $0\opc_l_r_opc$next[0:0]$12045 + attribute \src "issuer_ls180.v:172272.3-172273.39" + wire $0\opc_l_r_opc[0:0] + attribute \src "issuer_ls180.v:172414.3-172422.6" + wire $0\opc_l_s_opc$next[0:0]$12042 + attribute \src "issuer_ls180.v:172274.3-172275.39" + wire $0\opc_l_s_opc[0:0] + attribute \src "issuer_ls180.v:172751.3-172759.6" + wire width 6 $0\prev_wr_go$next[5:0]$12147 + attribute \src "issuer_ls180.v:172284.3-172285.37" + wire width 6 $0\prev_wr_go[5:0] + attribute \src "issuer_ls180.v:172368.3-172377.6" + wire $0\req_done[0:0] + attribute \src "issuer_ls180.v:172459.3-172467.6" + wire width 6 $0\req_l_r_req$next[5:0]$12057 + attribute \src "issuer_ls180.v:172264.3-172265.39" + wire width 6 $0\req_l_r_req[5:0] + attribute \src "issuer_ls180.v:172450.3-172458.6" + wire width 6 $0\req_l_s_req$next[5:0]$12054 + attribute \src "issuer_ls180.v:172266.3-172267.39" + wire width 6 $0\req_l_s_req[5:0] + attribute \src "issuer_ls180.v:172387.3-172395.6" + wire $0\rok_l_r_rdok$next[0:0]$12033 + attribute \src "issuer_ls180.v:172280.3-172281.41" + wire $0\rok_l_r_rdok[0:0] + attribute \src "issuer_ls180.v:172378.3-172386.6" + wire $0\rok_l_s_rdok$next[0:0]$12030 + attribute \src "issuer_ls180.v:172282.3-172283.41" + wire $0\rok_l_s_rdok[0:0] + attribute \src "issuer_ls180.v:172405.3-172413.6" + wire $0\rst_l_r_rst$next[0:0]$12039 + attribute \src "issuer_ls180.v:172276.3-172277.39" + wire $0\rst_l_r_rst[0:0] + attribute \src "issuer_ls180.v:172396.3-172404.6" + wire $0\rst_l_s_rst$next[0:0]$12036 + attribute \src "issuer_ls180.v:172278.3-172279.39" + wire $0\rst_l_s_rst[0:0] + attribute \src "issuer_ls180.v:172441.3-172449.6" + wire width 6 $0\src_l_r_src$next[5:0]$12051 + attribute \src "issuer_ls180.v:172268.3-172269.39" + wire width 6 $0\src_l_r_src[5:0] + attribute \src "issuer_ls180.v:172432.3-172440.6" + wire width 6 $0\src_l_s_src$next[5:0]$12048 + attribute \src "issuer_ls180.v:172270.3-172271.39" + wire width 6 $0\src_l_s_src[5:0] + attribute \src "issuer_ls180.v:172613.3-172622.6" + wire width 64 $0\src_r0$next[63:0]$12117 + attribute \src "issuer_ls180.v:172230.3-172231.29" + wire width 64 $0\src_r0[63:0] + attribute \src "issuer_ls180.v:172623.3-172632.6" + wire width 64 $0\src_r1$next[63:0]$12120 + attribute \src "issuer_ls180.v:172228.3-172229.29" + wire width 64 $0\src_r1[63:0] + attribute \src "issuer_ls180.v:172633.3-172642.6" + wire width 64 $0\src_r2$next[63:0]$12123 + attribute \src "issuer_ls180.v:172226.3-172227.29" + wire width 64 $0\src_r2[63:0] + attribute \src "issuer_ls180.v:172643.3-172652.6" + wire $0\src_r3$next[0:0]$12126 + attribute \src "issuer_ls180.v:172224.3-172225.29" + wire $0\src_r3[0:0] + attribute \src "issuer_ls180.v:172653.3-172662.6" + wire width 2 $0\src_r4$next[1:0]$12129 + attribute \src "issuer_ls180.v:172222.3-172223.29" + wire width 2 $0\src_r4[1:0] + attribute \src "issuer_ls180.v:172663.3-172672.6" + wire width 2 $0\src_r5$next[1:0]$12132 + attribute \src "issuer_ls180.v:172220.3-172221.29" + wire width 2 $0\src_r5[1:0] + attribute \src "issuer_ls180.v:171681.7-171681.24" + wire $1\all_rd_dly[0:0] + attribute \src "issuer_ls180.v:171691.7-171691.26" + wire $1\alu_done_dly[0:0] + attribute \src "issuer_ls180.v:172682.3-172690.6" + wire $1\alu_l_r_alu$next[0:0]$12139 + attribute \src "issuer_ls180.v:171699.7-171699.25" + wire $1\alu_l_r_alu[0:0] + attribute \src "issuer_ls180.v:172468.3-172480.6" + wire width 12 $1\alu_spr0_spr_op__fn_unit$next[11:0]$12064 + attribute \src "issuer_ls180.v:171742.14-171742.48" + wire width 12 $1\alu_spr0_spr_op__fn_unit[11:0] + attribute \src "issuer_ls180.v:172468.3-172480.6" + wire width 32 $1\alu_spr0_spr_op__insn$next[31:0]$12065 + attribute \src "issuer_ls180.v:171746.14-171746.43" + wire width 32 $1\alu_spr0_spr_op__insn[31:0] + attribute \src "issuer_ls180.v:172468.3-172480.6" + wire width 7 $1\alu_spr0_spr_op__insn_type$next[6:0]$12066 + attribute \src "issuer_ls180.v:171824.13-171824.47" + wire width 7 $1\alu_spr0_spr_op__insn_type[6:0] + attribute \src "issuer_ls180.v:172468.3-172480.6" + wire $1\alu_spr0_spr_op__is_32bit$next[0:0]$12067 + attribute \src "issuer_ls180.v:171828.7-171828.39" + wire $1\alu_spr0_spr_op__is_32bit[0:0] + attribute \src "issuer_ls180.v:172673.3-172681.6" + wire $1\alui_l_r_alui$next[0:0]$12136 + attribute \src "issuer_ls180.v:171846.7-171846.27" + wire $1\alui_l_r_alui[0:0] + attribute \src "issuer_ls180.v:172481.3-172502.6" + wire width 64 $1\data_r0__o$next[63:0]$12071 + attribute \src "issuer_ls180.v:171878.14-171878.47" + wire width 64 $1\data_r0__o[63:0] + attribute \src "issuer_ls180.v:172481.3-172502.6" + wire $1\data_r0__o_ok$next[0:0]$12072 + attribute \src "issuer_ls180.v:171882.7-171882.27" + wire $1\data_r0__o_ok[0:0] + attribute \src "issuer_ls180.v:172503.3-172524.6" + wire width 64 $1\data_r1__spr1$next[63:0]$12079 + attribute \src "issuer_ls180.v:171886.14-171886.50" + wire width 64 $1\data_r1__spr1[63:0] + attribute \src "issuer_ls180.v:172503.3-172524.6" + wire $1\data_r1__spr1_ok$next[0:0]$12080 + attribute \src "issuer_ls180.v:171890.7-171890.30" + wire $1\data_r1__spr1_ok[0:0] + attribute \src "issuer_ls180.v:172525.3-172546.6" + wire width 64 $1\data_r2__fast1$next[63:0]$12087 + attribute \src "issuer_ls180.v:171894.14-171894.51" + wire width 64 $1\data_r2__fast1[63:0] + attribute \src "issuer_ls180.v:172525.3-172546.6" + wire $1\data_r2__fast1_ok$next[0:0]$12088 + attribute \src "issuer_ls180.v:171898.7-171898.31" + wire $1\data_r2__fast1_ok[0:0] + attribute \src "issuer_ls180.v:172547.3-172568.6" + wire $1\data_r3__xer_so$next[0:0]$12095 + attribute \src "issuer_ls180.v:171902.7-171902.29" + wire $1\data_r3__xer_so[0:0] + attribute \src "issuer_ls180.v:172547.3-172568.6" + wire $1\data_r3__xer_so_ok$next[0:0]$12096 + attribute \src "issuer_ls180.v:171906.7-171906.32" + wire $1\data_r3__xer_so_ok[0:0] + attribute \src "issuer_ls180.v:172569.3-172590.6" + wire width 2 $1\data_r4__xer_ov$next[1:0]$12103 + attribute \src "issuer_ls180.v:171910.13-171910.35" + wire width 2 $1\data_r4__xer_ov[1:0] + attribute \src "issuer_ls180.v:172569.3-172590.6" + wire $1\data_r4__xer_ov_ok$next[0:0]$12104 + attribute \src "issuer_ls180.v:171914.7-171914.32" + wire $1\data_r4__xer_ov_ok[0:0] + attribute \src "issuer_ls180.v:172591.3-172612.6" + wire width 2 $1\data_r5__xer_ca$next[1:0]$12111 + attribute \src "issuer_ls180.v:171918.13-171918.35" + wire width 2 $1\data_r5__xer_ca[1:0] + attribute \src "issuer_ls180.v:172591.3-172612.6" + wire $1\data_r5__xer_ca_ok$next[0:0]$12112 + attribute \src "issuer_ls180.v:171922.7-171922.32" + wire $1\data_r5__xer_ca_ok[0:0] + attribute \src "issuer_ls180.v:172691.3-172700.6" + wire width 64 $1\dest1_o[63:0] + attribute \src "issuer_ls180.v:172701.3-172710.6" + wire width 64 $1\dest2_o[63:0] + attribute \src "issuer_ls180.v:172711.3-172720.6" + wire width 64 $1\dest3_o[63:0] + attribute \src "issuer_ls180.v:172721.3-172730.6" + wire $1\dest4_o[0:0] + attribute \src "issuer_ls180.v:172731.3-172740.6" + wire width 2 $1\dest5_o[1:0] + attribute \src "issuer_ls180.v:172741.3-172750.6" + wire width 2 $1\dest6_o[1:0] + attribute \src "issuer_ls180.v:172423.3-172431.6" + wire $1\opc_l_r_opc$next[0:0]$12046 + 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$and $and$issuer_ls180.v:172179$11954 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 6 + connect \A \cu_wr__rel_o + connect \B \$28 + connect \Y $and$issuer_ls180.v:172179$11954_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" + cell $and $and$issuer_ls180.v:172182$11957 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cu_busy_o + connect \B \$26 + connect \Y $and$issuer_ls180.v:172182$11957_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" + cell $and $and$issuer_ls180.v:172187$11962 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wr_any + connect \B \$42 + connect \Y $and$issuer_ls180.v:172187$11962_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" + cell $and $and$issuer_ls180.v:172188$11963 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 6 + connect \A \req_l_q_req + connect \B \cu_wrmask_o + connect \Y $and$issuer_ls180.v:172188$11963_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" + cell $and $and$issuer_ls180.v:172190$11965 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$44 + connect \B \$48 + connect \Y $and$issuer_ls180.v:172190$11965_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" + cell $and $and$issuer_ls180.v:172192$11967 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$52 + connect \B \alu_spr0_n_ready_i + connect \Y $and$issuer_ls180.v:172192$11967_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" + cell $and $and$issuer_ls180.v:172193$11968 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$54 + connect \B \alu_spr0_n_valid_o + connect \Y $and$issuer_ls180.v:172193$11968_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" + cell $and $and$issuer_ls180.v:172194$11969 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$56 + connect \B \cu_busy_o + connect \Y $and$issuer_ls180.v:172194$11969_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:237" + cell $and $and$issuer_ls180.v:172199$11974 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \alu_spr0_n_valid_o + connect \B \cu_busy_o + connect \Y $and$issuer_ls180.v:172199$11974_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:188" + cell $and $and$issuer_ls180.v:172200$11975 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cu_busy_o + connect \B \rok_l_q_rdok + connect \Y $and$issuer_ls180.v:172200$11975_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:252" + cell $and $and$issuer_ls180.v:172201$11976 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 6 + connect \A \alu_pulsem + connect \B \cu_wrmask_o + connect \Y $and$issuer_ls180.v:172201$11976_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" + cell $and $and$issuer_ls180.v:172203$11978 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \o_ok + connect \B \cu_busy_o + connect \Y $and$issuer_ls180.v:172203$11978_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" + cell $and $and$issuer_ls180.v:172204$11979 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \spr1_ok + connect \B \cu_busy_o + connect \Y $and$issuer_ls180.v:172204$11979_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" + cell $and $and$issuer_ls180.v:172205$11980 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \fast1_ok + connect \B \cu_busy_o + connect \Y $and$issuer_ls180.v:172205$11980_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" + cell $and $and$issuer_ls180.v:172206$11981 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \xer_so_ok + connect \B \cu_busy_o + connect \Y $and$issuer_ls180.v:172206$11981_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" + cell $and $and$issuer_ls180.v:172207$11982 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \xer_ov_ok + connect \B \cu_busy_o + connect \Y $and$issuer_ls180.v:172207$11982_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" + cell $and $and$issuer_ls180.v:172208$11983 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \xer_ca_ok + connect \B \cu_busy_o + connect \Y $and$issuer_ls180.v:172208$11983_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:327" + cell $and $and$issuer_ls180.v:172215$11990 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \alu_spr0_p_ready_o + connect \B \alui_l_q_alui + connect \Y $and$issuer_ls180.v:172215$11990_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" + cell $eq $eq$issuer_ls180.v:172189$11964 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$46 + connect \B 1'0 + connect \Y $eq$issuer_ls180.v:172189$11964_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" + cell $eq $eq$issuer_ls180.v:172191$11966 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cu_wrmask_o + connect \B 1'0 + connect \Y $eq$issuer_ls180.v:172191$11966_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" + cell $not $not$issuer_ls180.v:172150$11925 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \Y_WIDTH 6 + connect \A \cu_rd__rel_o + connect \Y $not$issuer_ls180.v:172150$11925_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" + cell $not $not$issuer_ls180.v:172154$11929 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \Y_WIDTH 6 + connect \A \cu_rdmaskn_i + connect \Y $not$issuer_ls180.v:172154$11929_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + cell $not $not$issuer_ls180.v:172173$11948 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \all_rd_dly + connect \Y $not$issuer_ls180.v:172173$11948_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + cell $not $not$issuer_ls180.v:172175$11950 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \alu_done_dly + connect \Y $not$issuer_ls180.v:172175$11950_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" + cell $not $not$issuer_ls180.v:172178$11953 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \Y_WIDTH 6 + connect \A \cu_wrmask_o + connect \Y $not$issuer_ls180.v:172178$11953_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" + cell $not $not$issuer_ls180.v:172181$11956 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$27 + connect \Y $not$issuer_ls180.v:172181$11956_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" + cell $not $not$issuer_ls180.v:172186$11961 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \alu_spr0_n_ready_i + connect \Y $not$issuer_ls180.v:172186$11961_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" + cell $or $or$issuer_ls180.v:172161$11936 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 6 + connect \A \$9 + connect \B \cu_rd__go_i + connect \Y $or$issuer_ls180.v:172161$11936_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" + cell $or $or$issuer_ls180.v:172185$11960 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$36 + connect \B \$38 + connect \Y $or$issuer_ls180.v:172185$11960_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:230" + cell $or $or$issuer_ls180.v:172195$11970 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \req_done + connect \B \cu_go_die_i + connect \Y $or$issuer_ls180.v:172195$11970_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:231" + cell $or $or$issuer_ls180.v:172196$11971 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cu_issue_i + connect \B \cu_go_die_i + connect \Y $or$issuer_ls180.v:172196$11971_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:232" + cell $or $or$issuer_ls180.v:172197$11972 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 6 + connect \A \cu_wr__go_i + connect \B { \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i } + connect \Y $or$issuer_ls180.v:172197$11972_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:233" + cell $or $or$issuer_ls180.v:172198$11973 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 6 + connect \A \cu_rd__go_i + connect \B { \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i } + connect \Y $or$issuer_ls180.v:172198$11973_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:253" + cell $or $or$issuer_ls180.v:172202$11977 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 6 + connect \A \reset_w + connect \B \prev_wr_go + connect \Y $or$issuer_ls180.v:172202$11977_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" + cell $reduce_and $reduce_and$issuer_ls180.v:172167$11942 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \$11 + connect \Y $reduce_and$issuer_ls180.v:172167$11942_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" + cell $reduce_or $reduce_or$issuer_ls180.v:172180$11955 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \$30 + connect \Y $reduce_or$issuer_ls180.v:172180$11955_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" + cell $reduce_or $reduce_or$issuer_ls180.v:172183$11958 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \cu_wr__go_i + connect \Y $reduce_or$issuer_ls180.v:172183$11958_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" + cell $reduce_or $reduce_or$issuer_ls180.v:172184$11959 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \prev_wr_go + connect \Y $reduce_or$issuer_ls180.v:172184$11959_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + cell $mux $ternary$issuer_ls180.v:172209$11984 + parameter \WIDTH 64 + connect \A \src_r0 + connect \B \src1_i + connect \S \src_l_q_src [0] + connect \Y $ternary$issuer_ls180.v:172209$11984_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + cell $mux $ternary$issuer_ls180.v:172210$11985 + parameter \WIDTH 64 + connect \A \src_r1 + connect \B \src2_i + connect \S \src_l_q_src [1] + connect \Y $ternary$issuer_ls180.v:172210$11985_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + cell $mux $ternary$issuer_ls180.v:172211$11986 + parameter \WIDTH 64 + connect \A \src_r2 + connect \B \src3_i + connect \S \src_l_q_src [2] + connect \Y $ternary$issuer_ls180.v:172211$11986_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + cell $mux $ternary$issuer_ls180.v:172212$11987 + parameter \WIDTH 1 + connect \A \src_r3 + connect \B \src4_i + connect \S \src_l_q_src [3] + connect \Y $ternary$issuer_ls180.v:172212$11987_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + cell $mux $ternary$issuer_ls180.v:172213$11988 + parameter \WIDTH 2 + connect \A \src_r4 + connect \B \src5_i + connect \S \src_l_q_src [4] + connect \Y $ternary$issuer_ls180.v:172213$11988_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + cell $mux $ternary$issuer_ls180.v:172214$11989 + parameter \WIDTH 2 + connect \A \src_r5 + connect \B \src6_i + connect \S \src_l_q_src [5] + connect \Y $ternary$issuer_ls180.v:172214$11989_Y + end + attribute \module_not_derived 1 + attribute \src "issuer_ls180.v:172290.14-172296.4" + cell \alu_l$70 \alu_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_alu \alu_l_q_alu + connect \r_alu \alu_l_r_alu + connect \s_alu \alu_l_s_alu + end + attribute \module_not_derived 1 + attribute \src "issuer_ls180.v:172297.12-172326.4" + cell \alu_spr0 \alu_spr0 + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \fast1 \alu_spr0_fast1 + connect \fast1$2 \alu_spr0_fast1$2 + connect \fast1_ok \fast1_ok + connect \n_ready_i \alu_spr0_n_ready_i + connect \n_valid_o \alu_spr0_n_valid_o + connect \o \alu_spr0_o + connect \o_ok \o_ok + connect \p_ready_o \alu_spr0_p_ready_o + connect \p_valid_i \alu_spr0_p_valid_i + connect \ra \alu_spr0_ra + connect \spr1 \alu_spr0_spr1 + connect \spr1$1 \alu_spr0_spr1$1 + connect \spr1_ok \spr1_ok + connect \spr_op__fn_unit \alu_spr0_spr_op__fn_unit + connect \spr_op__insn \alu_spr0_spr_op__insn + connect \spr_op__insn_type \alu_spr0_spr_op__insn_type + connect \spr_op__is_32bit \alu_spr0_spr_op__is_32bit + connect \xer_ca \alu_spr0_xer_ca + connect \xer_ca$5 \alu_spr0_xer_ca$5 + connect \xer_ca_ok \xer_ca_ok + connect \xer_ov \alu_spr0_xer_ov + connect \xer_ov$4 \alu_spr0_xer_ov$4 + connect \xer_ov_ok \xer_ov_ok + connect \xer_so \alu_spr0_xer_so + connect \xer_so$3 \alu_spr0_xer_so$3 + connect \xer_so_ok \xer_so_ok + end + attribute \module_not_derived 1 + attribute \src "issuer_ls180.v:172327.15-172333.4" + cell \alui_l$69 \alui_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_alui \alui_l_q_alui + connect \r_alui \alui_l_r_alui + connect \s_alui \alui_l_s_alui + end + attribute \module_not_derived 1 + attribute \src "issuer_ls180.v:172334.14-172340.4" + cell \opc_l$65 \opc_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_opc \opc_l_q_opc + connect \r_opc \opc_l_r_opc + connect \s_opc \opc_l_s_opc + end + attribute \module_not_derived 1 + attribute \src "issuer_ls180.v:172341.14-172347.4" + cell \req_l$66 \req_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_req \req_l_q_req + connect \r_req \req_l_r_req + connect \s_req \req_l_s_req + end + attribute \module_not_derived 1 + attribute \src "issuer_ls180.v:172348.14-172354.4" + cell \rok_l$68 \rok_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_rdok \rok_l_q_rdok + connect \r_rdok \rok_l_r_rdok + connect \s_rdok \rok_l_s_rdok + end + attribute \module_not_derived 1 + attribute \src "issuer_ls180.v:172355.14-172360.4" + cell \rst_l$67 \rst_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \r_rst \rst_l_r_rst + connect \s_rst \rst_l_s_rst + end + attribute \module_not_derived 1 + attribute \src "issuer_ls180.v:172361.14-172367.4" + cell \src_l$64 \src_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_src \src_l_q_src + connect \r_src \src_l_r_src + connect \s_src \src_l_s_src + end + attribute \src "issuer_ls180.v:171545.7-171545.20" + process $proc$issuer_ls180.v:171545$12149 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "issuer_ls180.v:171681.7-171681.24" + process $proc$issuer_ls180.v:171681$12150 + assign { } { } + assign $1\all_rd_dly[0:0] 1'0 + sync always + sync init + update \all_rd_dly $1\all_rd_dly[0:0] + end + attribute \src "issuer_ls180.v:171691.7-171691.26" + process $proc$issuer_ls180.v:171691$12151 + assign { } { } + assign $1\alu_done_dly[0:0] 1'0 + sync always + sync init + update \alu_done_dly $1\alu_done_dly[0:0] + end + attribute \src "issuer_ls180.v:171699.7-171699.25" + process $proc$issuer_ls180.v:171699$12152 + assign { } { } + assign $1\alu_l_r_alu[0:0] 1'1 + sync always + sync init + update \alu_l_r_alu $1\alu_l_r_alu[0:0] + end + attribute \src "issuer_ls180.v:171742.14-171742.48" + process $proc$issuer_ls180.v:171742$12153 + assign { } { } + assign $1\alu_spr0_spr_op__fn_unit[11:0] 12'000000000000 + sync always + sync init + update \alu_spr0_spr_op__fn_unit $1\alu_spr0_spr_op__fn_unit[11:0] + end + attribute \src "issuer_ls180.v:171746.14-171746.43" + process $proc$issuer_ls180.v:171746$12154 + assign { } { } + assign $1\alu_spr0_spr_op__insn[31:0] 0 + sync always + sync init + update \alu_spr0_spr_op__insn $1\alu_spr0_spr_op__insn[31:0] + end + attribute \src "issuer_ls180.v:171824.13-171824.47" + process $proc$issuer_ls180.v:171824$12155 + assign { } { } + assign $1\alu_spr0_spr_op__insn_type[6:0] 7'0000000 + sync always + sync init + update \alu_spr0_spr_op__insn_type $1\alu_spr0_spr_op__insn_type[6:0] + end + attribute \src "issuer_ls180.v:171828.7-171828.39" + process $proc$issuer_ls180.v:171828$12156 + assign { } { } + assign $1\alu_spr0_spr_op__is_32bit[0:0] 1'0 + sync always + sync init + update \alu_spr0_spr_op__is_32bit $1\alu_spr0_spr_op__is_32bit[0:0] + end + attribute \src "issuer_ls180.v:171846.7-171846.27" + process $proc$issuer_ls180.v:171846$12157 + assign { } { } + assign $1\alui_l_r_alui[0:0] 1'1 + sync always + sync init + update \alui_l_r_alui $1\alui_l_r_alui[0:0] + end + attribute \src "issuer_ls180.v:171878.14-171878.47" + process $proc$issuer_ls180.v:171878$12158 + assign { } { } + assign $1\data_r0__o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \data_r0__o $1\data_r0__o[63:0] + end + attribute \src "issuer_ls180.v:171882.7-171882.27" + process $proc$issuer_ls180.v:171882$12159 + assign { } { } + assign $1\data_r0__o_ok[0:0] 1'0 + sync always + sync init + update \data_r0__o_ok $1\data_r0__o_ok[0:0] + end + attribute \src "issuer_ls180.v:171886.14-171886.50" + process $proc$issuer_ls180.v:171886$12160 + assign { } { } + assign $1\data_r1__spr1[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \data_r1__spr1 $1\data_r1__spr1[63:0] + end + attribute \src "issuer_ls180.v:171890.7-171890.30" + process $proc$issuer_ls180.v:171890$12161 + assign { } { } + assign $1\data_r1__spr1_ok[0:0] 1'0 + sync always + sync init + update \data_r1__spr1_ok $1\data_r1__spr1_ok[0:0] + end + attribute \src "issuer_ls180.v:171894.14-171894.51" + process $proc$issuer_ls180.v:171894$12162 + assign { } { } + assign $1\data_r2__fast1[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \data_r2__fast1 $1\data_r2__fast1[63:0] + end + attribute \src "issuer_ls180.v:171898.7-171898.31" + process $proc$issuer_ls180.v:171898$12163 + assign { } { } + assign $1\data_r2__fast1_ok[0:0] 1'0 + sync always + sync init + update \data_r2__fast1_ok $1\data_r2__fast1_ok[0:0] + end + attribute \src "issuer_ls180.v:171902.7-171902.29" + process $proc$issuer_ls180.v:171902$12164 + assign { } { } + assign $1\data_r3__xer_so[0:0] 1'0 + sync always + sync init + update \data_r3__xer_so $1\data_r3__xer_so[0:0] + end + attribute \src "issuer_ls180.v:171906.7-171906.32" + process $proc$issuer_ls180.v:171906$12165 + assign { } { } + assign $1\data_r3__xer_so_ok[0:0] 1'0 + sync always + sync init + update \data_r3__xer_so_ok $1\data_r3__xer_so_ok[0:0] + end + attribute \src "issuer_ls180.v:171910.13-171910.35" + process $proc$issuer_ls180.v:171910$12166 + assign { } { } + assign $1\data_r4__xer_ov[1:0] 2'00 + sync always + sync init + update \data_r4__xer_ov $1\data_r4__xer_ov[1:0] + end + attribute \src "issuer_ls180.v:171914.7-171914.32" + process $proc$issuer_ls180.v:171914$12167 + assign { } { } + assign $1\data_r4__xer_ov_ok[0:0] 1'0 + sync always + sync init + update \data_r4__xer_ov_ok $1\data_r4__xer_ov_ok[0:0] + end + attribute \src "issuer_ls180.v:171918.13-171918.35" + process $proc$issuer_ls180.v:171918$12168 + assign { } { } + assign $1\data_r5__xer_ca[1:0] 2'00 + sync always + sync init + update \data_r5__xer_ca $1\data_r5__xer_ca[1:0] + end + attribute \src "issuer_ls180.v:171922.7-171922.32" + process $proc$issuer_ls180.v:171922$12169 + assign { } { } + assign $1\data_r5__xer_ca_ok[0:0] 1'0 + sync always + sync init + update \data_r5__xer_ca_ok $1\data_r5__xer_ca_ok[0:0] + end + attribute \src "issuer_ls180.v:171950.7-171950.25" + process $proc$issuer_ls180.v:171950$12170 + assign { } { } + assign $1\opc_l_r_opc[0:0] 1'1 + sync always + sync init + update \opc_l_r_opc $1\opc_l_r_opc[0:0] + end + attribute \src "issuer_ls180.v:171954.7-171954.25" + process $proc$issuer_ls180.v:171954$12171 + assign { } { } + assign $1\opc_l_s_opc[0:0] 1'0 + sync always + sync init + update \opc_l_s_opc $1\opc_l_s_opc[0:0] + end + attribute \src "issuer_ls180.v:172053.13-172053.31" + process $proc$issuer_ls180.v:172053$12172 + assign { } { } + assign $1\prev_wr_go[5:0] 6'000000 + sync always + sync init + update \prev_wr_go $1\prev_wr_go[5:0] + end + attribute \src "issuer_ls180.v:172061.13-172061.32" + process $proc$issuer_ls180.v:172061$12173 + assign { } { } + assign $1\req_l_r_req[5:0] 6'111111 + sync always + sync init + update \req_l_r_req $1\req_l_r_req[5:0] + end + attribute \src "issuer_ls180.v:172065.13-172065.32" + process $proc$issuer_ls180.v:172065$12174 + assign { } { } + assign $1\req_l_s_req[5:0] 6'000000 + sync always + sync init + update \req_l_s_req $1\req_l_s_req[5:0] + end + attribute \src "issuer_ls180.v:172077.7-172077.26" + process $proc$issuer_ls180.v:172077$12175 + assign { } { } + assign $1\rok_l_r_rdok[0:0] 1'1 + sync always + sync init + update \rok_l_r_rdok $1\rok_l_r_rdok[0:0] + end + attribute \src "issuer_ls180.v:172081.7-172081.26" + process $proc$issuer_ls180.v:172081$12176 + assign { } { } + assign $1\rok_l_s_rdok[0:0] 1'0 + sync always + sync init + update \rok_l_s_rdok $1\rok_l_s_rdok[0:0] + end + attribute \src "issuer_ls180.v:172085.7-172085.25" + process $proc$issuer_ls180.v:172085$12177 + assign { } { } + assign $1\rst_l_r_rst[0:0] 1'1 + sync always + sync init + update \rst_l_r_rst $1\rst_l_r_rst[0:0] + end + attribute \src "issuer_ls180.v:172089.7-172089.25" + process $proc$issuer_ls180.v:172089$12178 + assign { } { } + assign $1\rst_l_s_rst[0:0] 1'0 + sync always + sync init + update \rst_l_s_rst $1\rst_l_s_rst[0:0] + end + attribute \src "issuer_ls180.v:172111.13-172111.32" + process $proc$issuer_ls180.v:172111$12179 + assign { } { } + assign $1\src_l_r_src[5:0] 6'111111 + sync always + sync init + update \src_l_r_src $1\src_l_r_src[5:0] + end + attribute \src "issuer_ls180.v:172115.13-172115.32" + process $proc$issuer_ls180.v:172115$12180 + assign { } { } + assign $1\src_l_s_src[5:0] 6'000000 + sync always + sync init + update \src_l_s_src $1\src_l_s_src[5:0] + end + attribute \src "issuer_ls180.v:172119.14-172119.43" + process $proc$issuer_ls180.v:172119$12181 + assign { } { } + assign $1\src_r0[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \src_r0 $1\src_r0[63:0] + end + attribute \src "issuer_ls180.v:172123.14-172123.43" + process $proc$issuer_ls180.v:172123$12182 + assign { } { } + assign $1\src_r1[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \src_r1 $1\src_r1[63:0] + end + attribute \src "issuer_ls180.v:172127.14-172127.43" + process $proc$issuer_ls180.v:172127$12183 + assign { } { } + assign $1\src_r2[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \src_r2 $1\src_r2[63:0] + end + attribute \src "issuer_ls180.v:172131.7-172131.20" + process $proc$issuer_ls180.v:172131$12184 + assign { } { } + assign $1\src_r3[0:0] 1'0 + sync always + sync init + update \src_r3 $1\src_r3[0:0] + end + attribute \src "issuer_ls180.v:172135.13-172135.26" + process $proc$issuer_ls180.v:172135$12185 + assign { } { } + assign $1\src_r4[1:0] 2'00 + sync always + sync init + update \src_r4 $1\src_r4[1:0] + end + attribute \src "issuer_ls180.v:172139.13-172139.26" + process $proc$issuer_ls180.v:172139$12186 + assign { } { } + assign $1\src_r5[1:0] 2'00 + sync always + sync init + update \src_r5 $1\src_r5[1:0] + end + attribute \src "issuer_ls180.v:172216.3-172217.39" + process $proc$issuer_ls180.v:172216$11991 + assign { } { } + assign $0\alu_l_r_alu[0:0] \alu_l_r_alu$next + sync posedge \coresync_clk + update \alu_l_r_alu $0\alu_l_r_alu[0:0] + end + attribute \src "issuer_ls180.v:172218.3-172219.43" + process $proc$issuer_ls180.v:172218$11992 + assign { } { } + assign $0\alui_l_r_alui[0:0] \alui_l_r_alui$next + sync posedge \coresync_clk + update \alui_l_r_alui $0\alui_l_r_alui[0:0] + end + attribute \src "issuer_ls180.v:172220.3-172221.29" + process $proc$issuer_ls180.v:172220$11993 + assign { } { } + assign $0\src_r5[1:0] \src_r5$next + sync posedge \coresync_clk + update \src_r5 $0\src_r5[1:0] + end + attribute \src "issuer_ls180.v:172222.3-172223.29" + process $proc$issuer_ls180.v:172222$11994 + assign { } { } + assign $0\src_r4[1:0] \src_r4$next + sync posedge \coresync_clk + update \src_r4 $0\src_r4[1:0] + end + attribute \src "issuer_ls180.v:172224.3-172225.29" + process $proc$issuer_ls180.v:172224$11995 + assign { } { } + assign $0\src_r3[0:0] \src_r3$next + sync posedge \coresync_clk + update \src_r3 $0\src_r3[0:0] + end + attribute \src "issuer_ls180.v:172226.3-172227.29" + process $proc$issuer_ls180.v:172226$11996 + assign { } { } + assign $0\src_r2[63:0] \src_r2$next + sync posedge \coresync_clk + update \src_r2 $0\src_r2[63:0] + end + attribute \src "issuer_ls180.v:172228.3-172229.29" + process $proc$issuer_ls180.v:172228$11997 + assign { } { } + assign $0\src_r1[63:0] \src_r1$next + sync posedge \coresync_clk + update \src_r1 $0\src_r1[63:0] + end + attribute \src "issuer_ls180.v:172230.3-172231.29" + process $proc$issuer_ls180.v:172230$11998 + assign { } { } + assign $0\src_r0[63:0] \src_r0$next + sync posedge \coresync_clk + update \src_r0 $0\src_r0[63:0] + end + attribute \src "issuer_ls180.v:172232.3-172233.47" + process $proc$issuer_ls180.v:172232$11999 + assign { } { } + assign $0\data_r5__xer_ca[1:0] \data_r5__xer_ca$next + sync posedge \coresync_clk + update \data_r5__xer_ca $0\data_r5__xer_ca[1:0] + end + attribute \src "issuer_ls180.v:172234.3-172235.53" + process $proc$issuer_ls180.v:172234$12000 + assign { } { } + assign $0\data_r5__xer_ca_ok[0:0] \data_r5__xer_ca_ok$next + sync posedge \coresync_clk + update \data_r5__xer_ca_ok $0\data_r5__xer_ca_ok[0:0] + end + attribute \src "issuer_ls180.v:172236.3-172237.47" + process $proc$issuer_ls180.v:172236$12001 + assign { } { } + assign $0\data_r4__xer_ov[1:0] \data_r4__xer_ov$next + sync posedge \coresync_clk + update \data_r4__xer_ov $0\data_r4__xer_ov[1:0] + end + attribute \src "issuer_ls180.v:172238.3-172239.53" + process $proc$issuer_ls180.v:172238$12002 + assign { } { } + assign $0\data_r4__xer_ov_ok[0:0] \data_r4__xer_ov_ok$next + sync posedge \coresync_clk + update \data_r4__xer_ov_ok $0\data_r4__xer_ov_ok[0:0] + end + attribute \src "issuer_ls180.v:172240.3-172241.47" + process $proc$issuer_ls180.v:172240$12003 + assign { } { } + assign $0\data_r3__xer_so[0:0] \data_r3__xer_so$next + sync posedge \coresync_clk + update \data_r3__xer_so $0\data_r3__xer_so[0:0] + end + attribute \src "issuer_ls180.v:172242.3-172243.53" + process $proc$issuer_ls180.v:172242$12004 + assign { } { } + assign $0\data_r3__xer_so_ok[0:0] \data_r3__xer_so_ok$next + sync posedge \coresync_clk + update \data_r3__xer_so_ok $0\data_r3__xer_so_ok[0:0] + end + attribute \src "issuer_ls180.v:172244.3-172245.45" + process $proc$issuer_ls180.v:172244$12005 + assign { } { } + assign $0\data_r2__fast1[63:0] \data_r2__fast1$next + sync posedge \coresync_clk + update \data_r2__fast1 $0\data_r2__fast1[63:0] + end + attribute \src "issuer_ls180.v:172246.3-172247.51" + process $proc$issuer_ls180.v:172246$12006 + assign { } { } + assign $0\data_r2__fast1_ok[0:0] \data_r2__fast1_ok$next + sync posedge \coresync_clk + update \data_r2__fast1_ok $0\data_r2__fast1_ok[0:0] + end + attribute \src "issuer_ls180.v:172248.3-172249.43" + process $proc$issuer_ls180.v:172248$12007 + assign { } { } + assign $0\data_r1__spr1[63:0] \data_r1__spr1$next + sync posedge \coresync_clk + update \data_r1__spr1 $0\data_r1__spr1[63:0] + end + attribute \src "issuer_ls180.v:172250.3-172251.49" + process $proc$issuer_ls180.v:172250$12008 + assign { } { } + assign $0\data_r1__spr1_ok[0:0] \data_r1__spr1_ok$next + sync posedge \coresync_clk + update \data_r1__spr1_ok $0\data_r1__spr1_ok[0:0] + end + attribute \src "issuer_ls180.v:172252.3-172253.37" + process $proc$issuer_ls180.v:172252$12009 + assign { } { } + assign $0\data_r0__o[63:0] \data_r0__o$next + sync posedge \coresync_clk + update \data_r0__o $0\data_r0__o[63:0] + end + attribute \src "issuer_ls180.v:172254.3-172255.43" + process $proc$issuer_ls180.v:172254$12010 + assign { } { } + assign $0\data_r0__o_ok[0:0] \data_r0__o_ok$next + sync posedge \coresync_clk + update \data_r0__o_ok $0\data_r0__o_ok[0:0] + end + attribute \src "issuer_ls180.v:172256.3-172257.69" + process $proc$issuer_ls180.v:172256$12011 + assign { } { } + assign $0\alu_spr0_spr_op__insn_type[6:0] \alu_spr0_spr_op__insn_type$next + sync posedge \coresync_clk + update \alu_spr0_spr_op__insn_type $0\alu_spr0_spr_op__insn_type[6:0] + end + attribute \src "issuer_ls180.v:172258.3-172259.65" + process $proc$issuer_ls180.v:172258$12012 + assign { } { } + assign $0\alu_spr0_spr_op__fn_unit[11:0] \alu_spr0_spr_op__fn_unit$next + sync posedge \coresync_clk + update \alu_spr0_spr_op__fn_unit $0\alu_spr0_spr_op__fn_unit[11:0] + end + attribute \src "issuer_ls180.v:172260.3-172261.59" + process $proc$issuer_ls180.v:172260$12013 + assign { } { } + assign $0\alu_spr0_spr_op__insn[31:0] \alu_spr0_spr_op__insn$next + sync posedge \coresync_clk + update \alu_spr0_spr_op__insn $0\alu_spr0_spr_op__insn[31:0] + end + attribute \src "issuer_ls180.v:172262.3-172263.67" + process $proc$issuer_ls180.v:172262$12014 + assign { } { } + assign $0\alu_spr0_spr_op__is_32bit[0:0] \alu_spr0_spr_op__is_32bit$next + sync posedge \coresync_clk + update \alu_spr0_spr_op__is_32bit $0\alu_spr0_spr_op__is_32bit[0:0] + end + attribute \src "issuer_ls180.v:172264.3-172265.39" + process $proc$issuer_ls180.v:172264$12015 + assign { } { } + assign $0\req_l_r_req[5:0] \req_l_r_req$next + sync posedge \coresync_clk + update \req_l_r_req $0\req_l_r_req[5:0] + end + attribute \src "issuer_ls180.v:172266.3-172267.39" + process $proc$issuer_ls180.v:172266$12016 + assign { } { } + assign $0\req_l_s_req[5:0] \req_l_s_req$next + sync posedge \coresync_clk + update \req_l_s_req $0\req_l_s_req[5:0] + end + attribute \src "issuer_ls180.v:172268.3-172269.39" + process $proc$issuer_ls180.v:172268$12017 + assign { } { } + assign $0\src_l_r_src[5:0] \src_l_r_src$next + sync posedge \coresync_clk + update \src_l_r_src $0\src_l_r_src[5:0] + end + attribute \src "issuer_ls180.v:172270.3-172271.39" + process $proc$issuer_ls180.v:172270$12018 + assign { } { } + assign $0\src_l_s_src[5:0] \src_l_s_src$next + sync posedge \coresync_clk + update \src_l_s_src $0\src_l_s_src[5:0] + end + attribute \src "issuer_ls180.v:172272.3-172273.39" + process $proc$issuer_ls180.v:172272$12019 + assign { } { } + assign $0\opc_l_r_opc[0:0] \opc_l_r_opc$next + sync posedge \coresync_clk + update \opc_l_r_opc $0\opc_l_r_opc[0:0] + end + attribute \src "issuer_ls180.v:172274.3-172275.39" + process $proc$issuer_ls180.v:172274$12020 + assign { } { } + assign $0\opc_l_s_opc[0:0] \opc_l_s_opc$next + sync posedge \coresync_clk + update \opc_l_s_opc $0\opc_l_s_opc[0:0] + end + attribute \src "issuer_ls180.v:172276.3-172277.39" + process $proc$issuer_ls180.v:172276$12021 + assign { } { } + assign $0\rst_l_r_rst[0:0] \rst_l_r_rst$next + sync posedge \coresync_clk + update \rst_l_r_rst $0\rst_l_r_rst[0:0] + end + attribute \src "issuer_ls180.v:172278.3-172279.39" + process $proc$issuer_ls180.v:172278$12022 + assign { } { } + assign $0\rst_l_s_rst[0:0] \rst_l_s_rst$next + sync posedge \coresync_clk + update \rst_l_s_rst $0\rst_l_s_rst[0:0] + end + attribute \src "issuer_ls180.v:172280.3-172281.41" + process $proc$issuer_ls180.v:172280$12023 + assign { } { } + assign $0\rok_l_r_rdok[0:0] \rok_l_r_rdok$next + sync posedge \coresync_clk + update \rok_l_r_rdok $0\rok_l_r_rdok[0:0] + end + attribute \src "issuer_ls180.v:172282.3-172283.41" + process $proc$issuer_ls180.v:172282$12024 + assign { } { } + assign $0\rok_l_s_rdok[0:0] \rok_l_s_rdok$next + sync posedge \coresync_clk + update \rok_l_s_rdok $0\rok_l_s_rdok[0:0] + end + attribute \src "issuer_ls180.v:172284.3-172285.37" + process $proc$issuer_ls180.v:172284$12025 + assign { } { } + assign $0\prev_wr_go[5:0] \prev_wr_go$next + sync posedge \coresync_clk + update \prev_wr_go $0\prev_wr_go[5:0] + end + attribute \src "issuer_ls180.v:172286.3-172287.40" + process $proc$issuer_ls180.v:172286$12026 + assign { } { } + assign $0\alu_done_dly[0:0] \alu_spr0_n_valid_o + sync posedge \coresync_clk + update \alu_done_dly $0\alu_done_dly[0:0] + end + attribute \src "issuer_ls180.v:172288.3-172289.25" + process $proc$issuer_ls180.v:172288$12027 + assign { } { } + assign $0\all_rd_dly[0:0] \$14 + sync posedge \coresync_clk + update \all_rd_dly $0\all_rd_dly[0:0] + end + attribute \src "issuer_ls180.v:172368.3-172377.6" + process $proc$issuer_ls180.v:172368$12028 + assign { } { } + assign { } { } + assign $0\req_done[0:0] $1\req_done[0:0] + attribute \src "issuer_ls180.v:172369.5-172369.29" + switch \initial + attribute \src "issuer_ls180.v:172369.9-172369.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" + switch \$58 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\req_done[0:0] 1'1 + case + assign $1\req_done[0:0] \$50 + end + sync always + update \req_done $0\req_done[0:0] + end + attribute \src "issuer_ls180.v:172378.3-172386.6" + process $proc$issuer_ls180.v:172378$12029 + assign { } { } + assign { } { } + assign $0\rok_l_s_rdok$next[0:0]$12030 $1\rok_l_s_rdok$next[0:0]$12031 + attribute \src "issuer_ls180.v:172379.5-172379.29" + switch \initial + attribute \src "issuer_ls180.v:172379.9-172379.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\rok_l_s_rdok$next[0:0]$12031 1'0 + case + assign $1\rok_l_s_rdok$next[0:0]$12031 \cu_issue_i + end + sync always + update \rok_l_s_rdok$next $0\rok_l_s_rdok$next[0:0]$12030 + end + attribute \src "issuer_ls180.v:172387.3-172395.6" + process $proc$issuer_ls180.v:172387$12032 + assign { } { } + assign { } { } + assign $0\rok_l_r_rdok$next[0:0]$12033 $1\rok_l_r_rdok$next[0:0]$12034 + attribute \src "issuer_ls180.v:172388.5-172388.29" + switch \initial + attribute \src "issuer_ls180.v:172388.9-172388.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\rok_l_r_rdok$next[0:0]$12034 1'1 + case + assign $1\rok_l_r_rdok$next[0:0]$12034 \$68 + end + sync always + update \rok_l_r_rdok$next $0\rok_l_r_rdok$next[0:0]$12033 + end + attribute \src "issuer_ls180.v:172396.3-172404.6" + process $proc$issuer_ls180.v:172396$12035 + assign { } { } + assign { } { } + assign $0\rst_l_s_rst$next[0:0]$12036 $1\rst_l_s_rst$next[0:0]$12037 + attribute \src "issuer_ls180.v:172397.5-172397.29" + switch \initial + attribute \src "issuer_ls180.v:172397.9-172397.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\rst_l_s_rst$next[0:0]$12037 1'0 + case + assign $1\rst_l_s_rst$next[0:0]$12037 \all_rd + end + sync always + update \rst_l_s_rst$next $0\rst_l_s_rst$next[0:0]$12036 + end + attribute \src "issuer_ls180.v:172405.3-172413.6" + process $proc$issuer_ls180.v:172405$12038 + assign { } { } + assign { } { } + assign $0\rst_l_r_rst$next[0:0]$12039 $1\rst_l_r_rst$next[0:0]$12040 + attribute \src "issuer_ls180.v:172406.5-172406.29" + switch \initial + attribute \src "issuer_ls180.v:172406.9-172406.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\rst_l_r_rst$next[0:0]$12040 1'1 + case + assign $1\rst_l_r_rst$next[0:0]$12040 \rst_r + end + sync always + update \rst_l_r_rst$next $0\rst_l_r_rst$next[0:0]$12039 + end + attribute \src "issuer_ls180.v:172414.3-172422.6" + process $proc$issuer_ls180.v:172414$12041 + assign { } { } + assign { } { } + assign $0\opc_l_s_opc$next[0:0]$12042 $1\opc_l_s_opc$next[0:0]$12043 + attribute \src "issuer_ls180.v:172415.5-172415.29" + switch \initial + attribute \src "issuer_ls180.v:172415.9-172415.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\opc_l_s_opc$next[0:0]$12043 1'0 + case + assign $1\opc_l_s_opc$next[0:0]$12043 \cu_issue_i + end + sync always + update \opc_l_s_opc$next $0\opc_l_s_opc$next[0:0]$12042 + end + attribute \src "issuer_ls180.v:172423.3-172431.6" + process $proc$issuer_ls180.v:172423$12044 + assign { } { } + assign { } { } + assign $0\opc_l_r_opc$next[0:0]$12045 $1\opc_l_r_opc$next[0:0]$12046 + attribute \src "issuer_ls180.v:172424.5-172424.29" + switch \initial + attribute \src "issuer_ls180.v:172424.9-172424.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\opc_l_r_opc$next[0:0]$12046 1'1 + case + assign $1\opc_l_r_opc$next[0:0]$12046 \req_done + end + sync always + update \opc_l_r_opc$next $0\opc_l_r_opc$next[0:0]$12045 + end + attribute \src "issuer_ls180.v:172432.3-172440.6" + process $proc$issuer_ls180.v:172432$12047 + assign { } { } + assign { } { } + assign $0\src_l_s_src$next[5:0]$12048 $1\src_l_s_src$next[5:0]$12049 + attribute \src "issuer_ls180.v:172433.5-172433.29" + switch \initial + attribute \src "issuer_ls180.v:172433.9-172433.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\src_l_s_src$next[5:0]$12049 6'000000 + case + assign $1\src_l_s_src$next[5:0]$12049 { \cu_issue_i \cu_issue_i \cu_issue_i \cu_issue_i \cu_issue_i \cu_issue_i } + end + sync always + update \src_l_s_src$next $0\src_l_s_src$next[5:0]$12048 + end + attribute \src "issuer_ls180.v:172441.3-172449.6" + process $proc$issuer_ls180.v:172441$12050 + assign { } { } + assign { } { } + assign $0\src_l_r_src$next[5:0]$12051 $1\src_l_r_src$next[5:0]$12052 + attribute \src "issuer_ls180.v:172442.5-172442.29" + switch \initial + attribute \src "issuer_ls180.v:172442.9-172442.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\src_l_r_src$next[5:0]$12052 6'111111 + case + assign $1\src_l_r_src$next[5:0]$12052 \reset_r + end + sync always + update \src_l_r_src$next $0\src_l_r_src$next[5:0]$12051 + end + attribute \src "issuer_ls180.v:172450.3-172458.6" + process $proc$issuer_ls180.v:172450$12053 + assign { } { } + assign { } { } + assign $0\req_l_s_req$next[5:0]$12054 $1\req_l_s_req$next[5:0]$12055 + attribute \src "issuer_ls180.v:172451.5-172451.29" + switch \initial + attribute \src "issuer_ls180.v:172451.9-172451.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\req_l_s_req$next[5:0]$12055 6'000000 + case + assign $1\req_l_s_req$next[5:0]$12055 \$70 + end + sync always + update \req_l_s_req$next $0\req_l_s_req$next[5:0]$12054 + end + attribute \src "issuer_ls180.v:172459.3-172467.6" + process $proc$issuer_ls180.v:172459$12056 + assign { } { } + assign { } { } + assign $0\req_l_r_req$next[5:0]$12057 $1\req_l_r_req$next[5:0]$12058 + attribute \src "issuer_ls180.v:172460.5-172460.29" + switch \initial + attribute \src "issuer_ls180.v:172460.9-172460.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\req_l_r_req$next[5:0]$12058 6'111111 + case + assign $1\req_l_r_req$next[5:0]$12058 \$72 + end + sync always + update \req_l_r_req$next $0\req_l_r_req$next[5:0]$12057 + end + attribute \src "issuer_ls180.v:172468.3-172480.6" + process $proc$issuer_ls180.v:172468$12059 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\alu_spr0_spr_op__fn_unit$next[11:0]$12060 $1\alu_spr0_spr_op__fn_unit$next[11:0]$12064 + assign $0\alu_spr0_spr_op__insn$next[31:0]$12061 $1\alu_spr0_spr_op__insn$next[31:0]$12065 + assign $0\alu_spr0_spr_op__insn_type$next[6:0]$12062 $1\alu_spr0_spr_op__insn_type$next[6:0]$12066 + assign $0\alu_spr0_spr_op__is_32bit$next[0:0]$12063 $1\alu_spr0_spr_op__is_32bit$next[0:0]$12067 + attribute \src "issuer_ls180.v:172469.5-172469.29" + switch \initial + attribute \src "issuer_ls180.v:172469.9-172469.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:257" + switch \cu_issue_i + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { $1\alu_spr0_spr_op__is_32bit$next[0:0]$12067 $1\alu_spr0_spr_op__insn$next[31:0]$12065 $1\alu_spr0_spr_op__fn_unit$next[11:0]$12064 $1\alu_spr0_spr_op__insn_type$next[6:0]$12066 } { \oper_i_alu_spr0__is_32bit \oper_i_alu_spr0__insn \oper_i_alu_spr0__fn_unit \oper_i_alu_spr0__insn_type } + case + assign $1\alu_spr0_spr_op__fn_unit$next[11:0]$12064 \alu_spr0_spr_op__fn_unit + assign $1\alu_spr0_spr_op__insn$next[31:0]$12065 \alu_spr0_spr_op__insn + assign $1\alu_spr0_spr_op__insn_type$next[6:0]$12066 \alu_spr0_spr_op__insn_type + assign $1\alu_spr0_spr_op__is_32bit$next[0:0]$12067 \alu_spr0_spr_op__is_32bit + end + sync always + update \alu_spr0_spr_op__fn_unit$next $0\alu_spr0_spr_op__fn_unit$next[11:0]$12060 + update \alu_spr0_spr_op__insn$next $0\alu_spr0_spr_op__insn$next[31:0]$12061 + update \alu_spr0_spr_op__insn_type$next $0\alu_spr0_spr_op__insn_type$next[6:0]$12062 + update \alu_spr0_spr_op__is_32bit$next $0\alu_spr0_spr_op__is_32bit$next[0:0]$12063 + end + attribute \src "issuer_ls180.v:172481.3-172502.6" + process $proc$issuer_ls180.v:172481$12068 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\data_r0__o$next[63:0]$12069 $2\data_r0__o$next[63:0]$12073 + assign { } { } + assign $0\data_r0__o_ok$next[0:0]$12070 $3\data_r0__o_ok$next[0:0]$12075 + attribute \src "issuer_ls180.v:172482.5-172482.29" + switch \initial + attribute \src "issuer_ls180.v:172482.9-172482.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" + switch \alu_pulse + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $1\data_r0__o_ok$next[0:0]$12072 $1\data_r0__o$next[63:0]$12071 } { \o_ok \alu_spr0_o } + case + assign $1\data_r0__o$next[63:0]$12071 \data_r0__o + assign $1\data_r0__o_ok$next[0:0]$12072 \data_r0__o_ok + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" + switch \cu_issue_i + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $2\data_r0__o_ok$next[0:0]$12074 $2\data_r0__o$next[63:0]$12073 } 65'00000000000000000000000000000000000000000000000000000000000000000 + case + assign $2\data_r0__o$next[63:0]$12073 $1\data_r0__o$next[63:0]$12071 + assign $2\data_r0__o_ok$next[0:0]$12074 $1\data_r0__o_ok$next[0:0]$12072 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\data_r0__o_ok$next[0:0]$12075 1'0 + case + assign $3\data_r0__o_ok$next[0:0]$12075 $2\data_r0__o_ok$next[0:0]$12074 + end + sync always + update \data_r0__o$next $0\data_r0__o$next[63:0]$12069 + update \data_r0__o_ok$next $0\data_r0__o_ok$next[0:0]$12070 + end + attribute \src "issuer_ls180.v:172503.3-172524.6" + process $proc$issuer_ls180.v:172503$12076 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\data_r1__spr1$next[63:0]$12077 $2\data_r1__spr1$next[63:0]$12081 + assign { } { } + assign $0\data_r1__spr1_ok$next[0:0]$12078 $3\data_r1__spr1_ok$next[0:0]$12083 + attribute \src "issuer_ls180.v:172504.5-172504.29" + switch \initial + attribute \src "issuer_ls180.v:172504.9-172504.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" + switch \alu_pulse + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $1\data_r1__spr1_ok$next[0:0]$12080 $1\data_r1__spr1$next[63:0]$12079 } { \spr1_ok \alu_spr0_spr1 } + case + assign $1\data_r1__spr1$next[63:0]$12079 \data_r1__spr1 + assign $1\data_r1__spr1_ok$next[0:0]$12080 \data_r1__spr1_ok + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" + switch \cu_issue_i + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $2\data_r1__spr1_ok$next[0:0]$12082 $2\data_r1__spr1$next[63:0]$12081 } 65'00000000000000000000000000000000000000000000000000000000000000000 + case + assign $2\data_r1__spr1$next[63:0]$12081 $1\data_r1__spr1$next[63:0]$12079 + assign $2\data_r1__spr1_ok$next[0:0]$12082 $1\data_r1__spr1_ok$next[0:0]$12080 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\data_r1__spr1_ok$next[0:0]$12083 1'0 + case + assign $3\data_r1__spr1_ok$next[0:0]$12083 $2\data_r1__spr1_ok$next[0:0]$12082 + end + sync always + update \data_r1__spr1$next $0\data_r1__spr1$next[63:0]$12077 + update \data_r1__spr1_ok$next $0\data_r1__spr1_ok$next[0:0]$12078 + end + attribute \src "issuer_ls180.v:172525.3-172546.6" + process $proc$issuer_ls180.v:172525$12084 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\data_r2__fast1$next[63:0]$12085 $2\data_r2__fast1$next[63:0]$12089 + assign { } { } + assign $0\data_r2__fast1_ok$next[0:0]$12086 $3\data_r2__fast1_ok$next[0:0]$12091 + attribute \src "issuer_ls180.v:172526.5-172526.29" + switch \initial + attribute \src "issuer_ls180.v:172526.9-172526.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" + switch \alu_pulse + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $1\data_r2__fast1_ok$next[0:0]$12088 $1\data_r2__fast1$next[63:0]$12087 } { \fast1_ok \alu_spr0_fast1 } + case + assign $1\data_r2__fast1$next[63:0]$12087 \data_r2__fast1 + assign $1\data_r2__fast1_ok$next[0:0]$12088 \data_r2__fast1_ok + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" + switch \cu_issue_i + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $2\data_r2__fast1_ok$next[0:0]$12090 $2\data_r2__fast1$next[63:0]$12089 } 65'00000000000000000000000000000000000000000000000000000000000000000 + case + assign $2\data_r2__fast1$next[63:0]$12089 $1\data_r2__fast1$next[63:0]$12087 + assign $2\data_r2__fast1_ok$next[0:0]$12090 $1\data_r2__fast1_ok$next[0:0]$12088 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\data_r2__fast1_ok$next[0:0]$12091 1'0 + case + assign $3\data_r2__fast1_ok$next[0:0]$12091 $2\data_r2__fast1_ok$next[0:0]$12090 + end + sync always + update \data_r2__fast1$next $0\data_r2__fast1$next[63:0]$12085 + update \data_r2__fast1_ok$next $0\data_r2__fast1_ok$next[0:0]$12086 + end + attribute \src "issuer_ls180.v:172547.3-172568.6" + process $proc$issuer_ls180.v:172547$12092 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\data_r3__xer_so$next[0:0]$12093 $2\data_r3__xer_so$next[0:0]$12097 + assign { } { } + assign $0\data_r3__xer_so_ok$next[0:0]$12094 $3\data_r3__xer_so_ok$next[0:0]$12099 + attribute \src "issuer_ls180.v:172548.5-172548.29" + switch \initial + attribute \src "issuer_ls180.v:172548.9-172548.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" + switch \alu_pulse + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $1\data_r3__xer_so_ok$next[0:0]$12096 $1\data_r3__xer_so$next[0:0]$12095 } { \xer_so_ok \alu_spr0_xer_so } + case + assign $1\data_r3__xer_so$next[0:0]$12095 \data_r3__xer_so + assign $1\data_r3__xer_so_ok$next[0:0]$12096 \data_r3__xer_so_ok + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" + switch \cu_issue_i + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $2\data_r3__xer_so_ok$next[0:0]$12098 $2\data_r3__xer_so$next[0:0]$12097 } 2'00 + case + assign $2\data_r3__xer_so$next[0:0]$12097 $1\data_r3__xer_so$next[0:0]$12095 + assign $2\data_r3__xer_so_ok$next[0:0]$12098 $1\data_r3__xer_so_ok$next[0:0]$12096 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\data_r3__xer_so_ok$next[0:0]$12099 1'0 + case + assign $3\data_r3__xer_so_ok$next[0:0]$12099 $2\data_r3__xer_so_ok$next[0:0]$12098 + end + sync always + update \data_r3__xer_so$next $0\data_r3__xer_so$next[0:0]$12093 + update \data_r3__xer_so_ok$next $0\data_r3__xer_so_ok$next[0:0]$12094 + end + attribute \src "issuer_ls180.v:172569.3-172590.6" + process $proc$issuer_ls180.v:172569$12100 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\data_r4__xer_ov$next[1:0]$12101 $2\data_r4__xer_ov$next[1:0]$12105 + assign { } { } + assign $0\data_r4__xer_ov_ok$next[0:0]$12102 $3\data_r4__xer_ov_ok$next[0:0]$12107 + attribute \src "issuer_ls180.v:172570.5-172570.29" + switch \initial + attribute \src "issuer_ls180.v:172570.9-172570.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" + switch \alu_pulse + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $1\data_r4__xer_ov_ok$next[0:0]$12104 $1\data_r4__xer_ov$next[1:0]$12103 } { \xer_ov_ok \alu_spr0_xer_ov } + case + assign $1\data_r4__xer_ov$next[1:0]$12103 \data_r4__xer_ov + assign $1\data_r4__xer_ov_ok$next[0:0]$12104 \data_r4__xer_ov_ok + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" + switch \cu_issue_i + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $2\data_r4__xer_ov_ok$next[0:0]$12106 $2\data_r4__xer_ov$next[1:0]$12105 } 3'000 + case + assign $2\data_r4__xer_ov$next[1:0]$12105 $1\data_r4__xer_ov$next[1:0]$12103 + assign $2\data_r4__xer_ov_ok$next[0:0]$12106 $1\data_r4__xer_ov_ok$next[0:0]$12104 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\data_r4__xer_ov_ok$next[0:0]$12107 1'0 + case + assign $3\data_r4__xer_ov_ok$next[0:0]$12107 $2\data_r4__xer_ov_ok$next[0:0]$12106 + end + sync always + update \data_r4__xer_ov$next $0\data_r4__xer_ov$next[1:0]$12101 + update \data_r4__xer_ov_ok$next $0\data_r4__xer_ov_ok$next[0:0]$12102 + end + attribute \src "issuer_ls180.v:172591.3-172612.6" + process $proc$issuer_ls180.v:172591$12108 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\data_r5__xer_ca$next[1:0]$12109 $2\data_r5__xer_ca$next[1:0]$12113 + assign { } { } + assign $0\data_r5__xer_ca_ok$next[0:0]$12110 $3\data_r5__xer_ca_ok$next[0:0]$12115 + attribute \src "issuer_ls180.v:172592.5-172592.29" + switch \initial + attribute \src "issuer_ls180.v:172592.9-172592.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" + switch \alu_pulse + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $1\data_r5__xer_ca_ok$next[0:0]$12112 $1\data_r5__xer_ca$next[1:0]$12111 } { \xer_ca_ok \alu_spr0_xer_ca } + case + assign $1\data_r5__xer_ca$next[1:0]$12111 \data_r5__xer_ca + assign $1\data_r5__xer_ca_ok$next[0:0]$12112 \data_r5__xer_ca_ok + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" + switch \cu_issue_i + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $2\data_r5__xer_ca_ok$next[0:0]$12114 $2\data_r5__xer_ca$next[1:0]$12113 } 3'000 + case + assign $2\data_r5__xer_ca$next[1:0]$12113 $1\data_r5__xer_ca$next[1:0]$12111 + assign $2\data_r5__xer_ca_ok$next[0:0]$12114 $1\data_r5__xer_ca_ok$next[0:0]$12112 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\data_r5__xer_ca_ok$next[0:0]$12115 1'0 + case + assign $3\data_r5__xer_ca_ok$next[0:0]$12115 $2\data_r5__xer_ca_ok$next[0:0]$12114 + end + sync always + update \data_r5__xer_ca$next $0\data_r5__xer_ca$next[1:0]$12109 + update \data_r5__xer_ca_ok$next $0\data_r5__xer_ca_ok$next[0:0]$12110 + end + attribute \src "issuer_ls180.v:172613.3-172622.6" + process $proc$issuer_ls180.v:172613$12116 + assign { } { } + assign { } { } + assign $0\src_r0$next[63:0]$12117 $1\src_r0$next[63:0]$12118 + attribute \src "issuer_ls180.v:172614.5-172614.29" + switch \initial + attribute \src "issuer_ls180.v:172614.9-172614.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" + switch \src_l_q_src [0] + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\src_r0$next[63:0]$12118 \src1_i + case + assign $1\src_r0$next[63:0]$12118 \src_r0 + end + sync always + update \src_r0$next $0\src_r0$next[63:0]$12117 + end + attribute \src "issuer_ls180.v:172623.3-172632.6" + process $proc$issuer_ls180.v:172623$12119 + assign { } { } + assign { } { } + assign $0\src_r1$next[63:0]$12120 $1\src_r1$next[63:0]$12121 + attribute \src "issuer_ls180.v:172624.5-172624.29" + switch \initial + attribute \src "issuer_ls180.v:172624.9-172624.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" + switch \src_l_q_src [1] + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\src_r1$next[63:0]$12121 \src2_i + case + assign $1\src_r1$next[63:0]$12121 \src_r1 + end + sync always + update \src_r1$next $0\src_r1$next[63:0]$12120 + end + attribute \src "issuer_ls180.v:172633.3-172642.6" + process $proc$issuer_ls180.v:172633$12122 + assign { } { } + assign { } { } + assign $0\src_r2$next[63:0]$12123 $1\src_r2$next[63:0]$12124 + attribute \src "issuer_ls180.v:172634.5-172634.29" + switch \initial + attribute \src "issuer_ls180.v:172634.9-172634.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" + switch \src_l_q_src [2] + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\src_r2$next[63:0]$12124 \src3_i + case + assign $1\src_r2$next[63:0]$12124 \src_r2 + end + sync always + update \src_r2$next $0\src_r2$next[63:0]$12123 + end + attribute \src "issuer_ls180.v:172643.3-172652.6" + process $proc$issuer_ls180.v:172643$12125 + assign { } { } + assign { } { } + assign $0\src_r3$next[0:0]$12126 $1\src_r3$next[0:0]$12127 + attribute \src "issuer_ls180.v:172644.5-172644.29" + switch \initial + attribute \src "issuer_ls180.v:172644.9-172644.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" + switch \src_l_q_src [3] + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\src_r3$next[0:0]$12127 \src4_i + case + assign $1\src_r3$next[0:0]$12127 \src_r3 + end + sync always + update \src_r3$next $0\src_r3$next[0:0]$12126 + end + attribute \src "issuer_ls180.v:172653.3-172662.6" + process $proc$issuer_ls180.v:172653$12128 + assign { } { } + assign { } { } + assign $0\src_r4$next[1:0]$12129 $1\src_r4$next[1:0]$12130 + attribute \src "issuer_ls180.v:172654.5-172654.29" + switch \initial + attribute \src "issuer_ls180.v:172654.9-172654.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" + switch \src_l_q_src [4] + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\src_r4$next[1:0]$12130 \src5_i + case + assign $1\src_r4$next[1:0]$12130 \src_r4 + end + sync always + update \src_r4$next $0\src_r4$next[1:0]$12129 + end + attribute \src "issuer_ls180.v:172663.3-172672.6" + process $proc$issuer_ls180.v:172663$12131 + assign { } { } + assign { } { } + assign $0\src_r5$next[1:0]$12132 $1\src_r5$next[1:0]$12133 + attribute \src "issuer_ls180.v:172664.5-172664.29" + switch \initial + attribute \src "issuer_ls180.v:172664.9-172664.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" + switch \src_l_q_src [5] + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\src_r5$next[1:0]$12133 \src6_i + case + assign $1\src_r5$next[1:0]$12133 \src_r5 + end + sync always + update \src_r5$next $0\src_r5$next[1:0]$12132 + end + attribute \src "issuer_ls180.v:172673.3-172681.6" + process $proc$issuer_ls180.v:172673$12134 + assign { } { } + assign { } { } + assign $0\alui_l_r_alui$next[0:0]$12135 $1\alui_l_r_alui$next[0:0]$12136 + attribute \src "issuer_ls180.v:172674.5-172674.29" + switch \initial + attribute \src "issuer_ls180.v:172674.9-172674.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\alui_l_r_alui$next[0:0]$12136 1'1 + case + assign $1\alui_l_r_alui$next[0:0]$12136 \$98 + end + sync always + update \alui_l_r_alui$next $0\alui_l_r_alui$next[0:0]$12135 + end + attribute \src "issuer_ls180.v:172682.3-172690.6" + process $proc$issuer_ls180.v:172682$12137 + assign { } { } + assign { } { } + assign $0\alu_l_r_alu$next[0:0]$12138 $1\alu_l_r_alu$next[0:0]$12139 + attribute \src "issuer_ls180.v:172683.5-172683.29" + switch \initial + attribute \src "issuer_ls180.v:172683.9-172683.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\alu_l_r_alu$next[0:0]$12139 1'1 + case + assign $1\alu_l_r_alu$next[0:0]$12139 \$100 + end + sync always + update \alu_l_r_alu$next $0\alu_l_r_alu$next[0:0]$12138 + end + attribute \src "issuer_ls180.v:172691.3-172700.6" + process $proc$issuer_ls180.v:172691$12140 + assign { } { } + assign { } { } + assign $0\dest1_o[63:0] $1\dest1_o[63:0] + attribute \src "issuer_ls180.v:172692.5-172692.29" + switch \initial + attribute \src "issuer_ls180.v:172692.9-172692.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" + switch \$126 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dest1_o[63:0] \data_r0__o + case + assign $1\dest1_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \dest1_o $0\dest1_o[63:0] + end + attribute \src "issuer_ls180.v:172701.3-172710.6" + process $proc$issuer_ls180.v:172701$12141 + assign { } { } + assign { } { } + assign $0\dest2_o[63:0] $1\dest2_o[63:0] + attribute \src "issuer_ls180.v:172702.5-172702.29" + switch \initial + attribute \src "issuer_ls180.v:172702.9-172702.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" + switch \$128 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dest2_o[63:0] \data_r1__spr1 + case + assign $1\dest2_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \dest2_o $0\dest2_o[63:0] + end + attribute \src "issuer_ls180.v:172711.3-172720.6" + process $proc$issuer_ls180.v:172711$12142 + assign { } { } + assign { } { } + assign $0\dest3_o[63:0] $1\dest3_o[63:0] + attribute \src "issuer_ls180.v:172712.5-172712.29" + switch \initial + attribute \src "issuer_ls180.v:172712.9-172712.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" + switch \$130 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dest3_o[63:0] \data_r2__fast1 + case + assign $1\dest3_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \dest3_o $0\dest3_o[63:0] + end + attribute \src "issuer_ls180.v:172721.3-172730.6" + process $proc$issuer_ls180.v:172721$12143 + assign { } { } + assign { } { } + assign $0\dest4_o[0:0] $1\dest4_o[0:0] + attribute \src "issuer_ls180.v:172722.5-172722.29" + switch \initial + attribute \src "issuer_ls180.v:172722.9-172722.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" + switch \$132 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dest4_o[0:0] \data_r3__xer_so + case + assign $1\dest4_o[0:0] 1'0 + end + sync always + update \dest4_o $0\dest4_o[0:0] + end + attribute \src "issuer_ls180.v:172731.3-172740.6" + process $proc$issuer_ls180.v:172731$12144 + assign { } { } + assign { } { } + assign $0\dest5_o[1:0] $1\dest5_o[1:0] + attribute \src "issuer_ls180.v:172732.5-172732.29" + switch \initial + attribute \src "issuer_ls180.v:172732.9-172732.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" + switch \$134 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dest5_o[1:0] \data_r4__xer_ov + case + assign $1\dest5_o[1:0] 2'00 + end + sync always + update \dest5_o $0\dest5_o[1:0] + end + attribute \src "issuer_ls180.v:172741.3-172750.6" + process $proc$issuer_ls180.v:172741$12145 + assign { } { } + assign { } { } + assign $0\dest6_o[1:0] $1\dest6_o[1:0] + attribute \src "issuer_ls180.v:172742.5-172742.29" + switch \initial + attribute \src "issuer_ls180.v:172742.9-172742.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" + switch \$136 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dest6_o[1:0] \data_r5__xer_ca + case + assign $1\dest6_o[1:0] 2'00 + end + sync always + update \dest6_o $0\dest6_o[1:0] + end + attribute \src "issuer_ls180.v:172751.3-172759.6" + process $proc$issuer_ls180.v:172751$12146 + assign { } { } + assign { } { } + assign $0\prev_wr_go$next[5:0]$12147 $1\prev_wr_go$next[5:0]$12148 + attribute \src "issuer_ls180.v:172752.5-172752.29" + switch \initial + attribute \src "issuer_ls180.v:172752.9-172752.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\prev_wr_go$next[5:0]$12148 6'000000 + case + assign $1\prev_wr_go$next[5:0]$12148 \$24 + end + sync always + update \prev_wr_go$next $0\prev_wr_go$next[5:0]$12147 + end + connect \$9 $not$issuer_ls180.v:172150$11925_Y + connect \$100 $and$issuer_ls180.v:172151$11926_Y + connect \$102 $and$issuer_ls180.v:172152$11927_Y + connect \$104 $and$issuer_ls180.v:172153$11928_Y + connect \$106 $not$issuer_ls180.v:172154$11929_Y + connect \$108 $and$issuer_ls180.v:172155$11930_Y + connect \$110 $and$issuer_ls180.v:172156$11931_Y + connect \$112 $and$issuer_ls180.v:172157$11932_Y + connect \$114 $and$issuer_ls180.v:172158$11933_Y + connect \$116 $and$issuer_ls180.v:172159$11934_Y + connect \$118 $and$issuer_ls180.v:172160$11935_Y + connect \$11 $or$issuer_ls180.v:172161$11936_Y + connect \$120 $and$issuer_ls180.v:172162$11937_Y + connect \$122 $and$issuer_ls180.v:172163$11938_Y + connect \$124 $and$issuer_ls180.v:172164$11939_Y + connect \$126 $and$issuer_ls180.v:172165$11940_Y + connect \$128 $and$issuer_ls180.v:172166$11941_Y + connect \$8 $reduce_and$issuer_ls180.v:172167$11942_Y + connect \$130 $and$issuer_ls180.v:172168$11943_Y + connect \$132 $and$issuer_ls180.v:172169$11944_Y + connect \$134 $and$issuer_ls180.v:172170$11945_Y + connect \$136 $and$issuer_ls180.v:172171$11946_Y + connect \$14 $and$issuer_ls180.v:172172$11947_Y + connect \$16 $not$issuer_ls180.v:172173$11948_Y + connect \$18 $and$issuer_ls180.v:172174$11949_Y + connect \$20 $not$issuer_ls180.v:172175$11950_Y + connect \$22 $and$issuer_ls180.v:172176$11951_Y + connect \$24 $and$issuer_ls180.v:172177$11952_Y + connect \$28 $not$issuer_ls180.v:172178$11953_Y + connect \$30 $and$issuer_ls180.v:172179$11954_Y + connect \$27 $reduce_or$issuer_ls180.v:172180$11955_Y + connect \$26 $not$issuer_ls180.v:172181$11956_Y + connect \$34 $and$issuer_ls180.v:172182$11957_Y + connect \$36 $reduce_or$issuer_ls180.v:172183$11958_Y + connect \$38 $reduce_or$issuer_ls180.v:172184$11959_Y + connect \$40 $or$issuer_ls180.v:172185$11960_Y + connect \$42 $not$issuer_ls180.v:172186$11961_Y + connect \$44 $and$issuer_ls180.v:172187$11962_Y + connect \$46 $and$issuer_ls180.v:172188$11963_Y + connect \$48 $eq$issuer_ls180.v:172189$11964_Y + connect \$50 $and$issuer_ls180.v:172190$11965_Y + connect \$52 $eq$issuer_ls180.v:172191$11966_Y + connect \$54 $and$issuer_ls180.v:172192$11967_Y + connect \$56 $and$issuer_ls180.v:172193$11968_Y + connect \$58 $and$issuer_ls180.v:172194$11969_Y + connect \$60 $or$issuer_ls180.v:172195$11970_Y + connect \$62 $or$issuer_ls180.v:172196$11971_Y + connect \$64 $or$issuer_ls180.v:172197$11972_Y + connect \$66 $or$issuer_ls180.v:172198$11973_Y + connect \$68 $and$issuer_ls180.v:172199$11974_Y + connect \$6 $and$issuer_ls180.v:172200$11975_Y + connect \$70 $and$issuer_ls180.v:172201$11976_Y + connect \$72 $or$issuer_ls180.v:172202$11977_Y + connect \$74 $and$issuer_ls180.v:172203$11978_Y + connect \$76 $and$issuer_ls180.v:172204$11979_Y + connect \$78 $and$issuer_ls180.v:172205$11980_Y + connect \$80 $and$issuer_ls180.v:172206$11981_Y + connect \$82 $and$issuer_ls180.v:172207$11982_Y + connect \$84 $and$issuer_ls180.v:172208$11983_Y + connect \$86 $ternary$issuer_ls180.v:172209$11984_Y + connect \$88 $ternary$issuer_ls180.v:172210$11985_Y + connect \$90 $ternary$issuer_ls180.v:172211$11986_Y + connect \$92 $ternary$issuer_ls180.v:172212$11987_Y + connect \$94 $ternary$issuer_ls180.v:172213$11988_Y + connect \$96 $ternary$issuer_ls180.v:172214$11989_Y + connect \$98 $and$issuer_ls180.v:172215$11990_Y + connect \cu_go_die_i 1'0 + connect \cu_shadown_i 1'1 + connect \cu_wr__rel_o \$124 + connect \cu_rd__rel_o \$108 + connect \cu_busy_o \opc_l_q_opc + connect \alu_l_s_alu \all_rd_pulse + connect \alu_spr0_n_ready_i \alu_l_q_alu + connect \alui_l_s_alui \all_rd_pulse + connect \alu_spr0_p_valid_i \alui_l_q_alui + connect \alu_spr0_xer_ca$5 \$96 + connect \alu_spr0_xer_ov$4 \$94 + connect \alu_spr0_xer_so$3 \$92 + connect \alu_spr0_fast1$2 \$90 + connect \alu_spr0_spr1$1 \$88 + connect \alu_spr0_ra \$86 + connect \cu_wrmask_o { \$84 \$82 \$80 \$78 \$76 \$74 } + connect \reset_r \$66 + connect \reset_w \$64 + connect \rst_r \$62 + connect \reset \$60 + connect \wr_any \$40 + connect \cu_done_o \$34 + connect \alu_pulsem { \alu_pulse \alu_pulse \alu_pulse \alu_pulse \alu_pulse \alu_pulse } + connect \alu_pulse \alu_done_rise + connect \alu_done_rise \$22 + connect \alu_done_dly$next \alu_done + connect \alu_done \alu_spr0_n_valid_o + connect \all_rd_pulse \all_rd_rise + connect \all_rd_rise \$18 + connect \all_rd_dly$next \all_rd + connect \all_rd \$14 +end +attribute \src "issuer_ls180.v:172795.1-173309.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.fus.spr0.alu_spr0.pipe.spr_main" +attribute \generator "nMigen" +module \spr_main + attribute \src "issuer_ls180.v:173062.3-173077.6" + wire width 64 $0\fast1$7[63:0]$12195 + attribute \src "issuer_ls180.v:173139.3-173154.6" + wire $0\fast1_ok[0:0] + attribute \src "issuer_ls180.v:172796.7-172796.20" + wire $0\initial[0:0] + attribute \src "issuer_ls180.v:173097.3-173138.6" + wire width 64 $0\o[63:0] + attribute \src "issuer_ls180.v:173097.3-173138.6" + wire $0\o_ok[0:0] + attribute \src "issuer_ls180.v:173287.3-173305.6" + wire width 64 $0\spr1$6[63:0]$12220 + attribute \src "issuer_ls180.v:173078.3-173096.6" + wire $0\spr1_ok[0:0] + attribute \src "issuer_ls180.v:173242.3-173265.6" + wire width 2 $0\xer_ca$10[1:0]$12214 + attribute \src "issuer_ls180.v:173266.3-173286.6" + wire $0\xer_ca_ok[0:0] + attribute \src "issuer_ls180.v:173197.3-173220.6" + wire width 2 $0\xer_ov$9[1:0]$12208 + attribute \src "issuer_ls180.v:173221.3-173241.6" + wire $0\xer_ov_ok[0:0] + attribute \src "issuer_ls180.v:173155.3-173175.6" + wire $0\xer_so$8[0:0]$12202 + attribute \src "issuer_ls180.v:173176.3-173196.6" + wire $0\xer_so_ok[0:0] + attribute \src "issuer_ls180.v:173062.3-173077.6" + wire width 64 $1\fast1$7[63:0]$12196 + attribute \src "issuer_ls180.v:173139.3-173154.6" + wire $1\fast1_ok[0:0] + attribute \src "issuer_ls180.v:173097.3-173138.6" + wire width 64 $1\o[63:0] + attribute \src "issuer_ls180.v:173097.3-173138.6" + wire $1\o_ok[0:0] + attribute \src "issuer_ls180.v:173287.3-173305.6" + wire width 64 $1\spr1$6[63:0]$12221 + attribute \src "issuer_ls180.v:173078.3-173096.6" + wire $1\spr1_ok[0:0] + attribute \src "issuer_ls180.v:173242.3-173265.6" + wire width 2 $1\xer_ca$10[1:0]$12215 + attribute \src "issuer_ls180.v:173266.3-173286.6" + wire $1\xer_ca_ok[0:0] + attribute \src "issuer_ls180.v:173197.3-173220.6" + wire width 2 $1\xer_ov$9[1:0]$12209 + attribute \src "issuer_ls180.v:173221.3-173241.6" + wire $1\xer_ov_ok[0:0] + attribute \src "issuer_ls180.v:173155.3-173175.6" + wire $1\xer_so$8[0:0]$12203 + attribute \src "issuer_ls180.v:173176.3-173196.6" + wire $1\xer_so_ok[0:0] + attribute \src "issuer_ls180.v:173062.3-173077.6" + wire width 64 $2\fast1$7[63:0]$12197 + attribute \src "issuer_ls180.v:173139.3-173154.6" + wire $2\fast1_ok[0:0] + attribute \src "issuer_ls180.v:173097.3-173138.6" + wire width 64 $2\o[63:0] + attribute \src "issuer_ls180.v:173287.3-173305.6" + wire width 64 $2\spr1$6[63:0]$12222 + attribute \src "issuer_ls180.v:173078.3-173096.6" + wire $2\spr1_ok[0:0] + attribute \src "issuer_ls180.v:173242.3-173265.6" + wire width 2 $2\xer_ca$10[1:0]$12216 + attribute \src "issuer_ls180.v:173266.3-173286.6" + wire $2\xer_ca_ok[0:0] + attribute \src "issuer_ls180.v:173197.3-173220.6" + wire width 2 $2\xer_ov$9[1:0]$12210 + attribute \src "issuer_ls180.v:173221.3-173241.6" + wire $2\xer_ov_ok[0:0] + attribute \src "issuer_ls180.v:173155.3-173175.6" + wire $2\xer_so$8[0:0]$12204 + attribute \src "issuer_ls180.v:173176.3-173196.6" + wire $2\xer_so_ok[0:0] + attribute \src "issuer_ls180.v:173097.3-173138.6" + wire width 46 $3\o[63:18] + attribute \src "issuer_ls180.v:173242.3-173265.6" + wire width 2 $3\xer_ca$10[1:0]$12217 + attribute \src "issuer_ls180.v:173266.3-173286.6" + wire $3\xer_ca_ok[0:0] + attribute \src "issuer_ls180.v:173197.3-173220.6" + wire width 2 $3\xer_ov$9[1:0]$12211 + attribute \src "issuer_ls180.v:173221.3-173241.6" + wire $3\xer_ov_ok[0:0] + attribute \src "issuer_ls180.v:173155.3-173175.6" + wire $3\xer_so$8[0:0]$12205 + attribute \src "issuer_ls180.v:173176.3-173196.6" + wire $3\xer_so_ok[0:0] + attribute \src "issuer_ls180.v:173055.18-173055.106" + wire $eq$issuer_ls180.v:173055$12187_Y + attribute \src "issuer_ls180.v:173056.18-173056.106" + wire $eq$issuer_ls180.v:173056$12188_Y + attribute \src "issuer_ls180.v:173057.18-173057.106" + wire $eq$issuer_ls180.v:173057$12189_Y + attribute \src "issuer_ls180.v:173058.18-173058.106" + wire $eq$issuer_ls180.v:173058$12190_Y + attribute \src "issuer_ls180.v:173059.18-173059.106" + wire $eq$issuer_ls180.v:173059$12191_Y + attribute \src "issuer_ls180.v:173060.18-173060.106" + wire $eq$issuer_ls180.v:173060$12192_Y + attribute \src "issuer_ls180.v:173061.18-173061.106" + wire $eq$issuer_ls180.v:173061$12193_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:56" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:56" + wire \$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:56" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:56" + wire \$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:56" + wire \$19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:56" + wire \$21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:82" + wire \$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 7 \fast1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 output 20 \fast1$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 21 \fast1_ok + attribute \src "issuer_ls180.v:172796.7-172796.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 input 28 \muxid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" + wire width 2 output 11 \muxid$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 output 16 \o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 17 \o_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 5 \ra + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:42" + wire width 10 \spr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 64 input 6 \spr1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 output 18 \spr1$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 19 \spr1_ok + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 input 2 \spr_op__fn_unit + attribute \enum_base_type "Function" + attribute \enum_value_000000000000 "NONE" + attribute \enum_value_000000000010 "ALU" + attribute \enum_value_000000000100 "LDST" + attribute \enum_value_000000001000 "SHIFT_ROT" + attribute \enum_value_000000010000 "LOGICAL" + attribute \enum_value_000000100000 "BRANCH" + attribute \enum_value_000001000000 "CR" + attribute \enum_value_000010000000 "TRAP" + attribute \enum_value_000100000000 "MUL" + attribute \enum_value_001000000000 "DIV" + attribute \enum_value_010000000000 "SPR" + attribute \enum_value_100000000000 "MMU" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 12 output 13 \spr_op__fn_unit$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 input 3 \spr_op__insn + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 32 output 14 \spr_op__insn$4 + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 input 1 \spr_op__insn_type + attribute \enum_base_type "MicrOp" + attribute \enum_value_0000000 "OP_ILLEGAL" + attribute \enum_value_0000001 "OP_NOP" + attribute \enum_value_0000010 "OP_ADD" + attribute \enum_value_0000011 "OP_ADDPCIS" + attribute \enum_value_0000100 "OP_AND" + attribute \enum_value_0000101 "OP_ATTN" + attribute \enum_value_0000110 "OP_B" + attribute \enum_value_0000111 "OP_BC" + attribute \enum_value_0001000 "OP_BCREG" + attribute \enum_value_0001001 "OP_BPERM" + attribute \enum_value_0001010 "OP_CMP" + attribute \enum_value_0001011 "OP_CMPB" + attribute \enum_value_0001100 "OP_CMPEQB" + attribute \enum_value_0001101 "OP_CMPRB" + attribute \enum_value_0001110 "OP_CNTZ" + attribute \enum_value_0001111 "OP_CRAND" + attribute \enum_value_0010000 "OP_CRANDC" + attribute \enum_value_0010001 "OP_CREQV" + attribute \enum_value_0010010 "OP_CRNAND" + attribute \enum_value_0010011 "OP_CRNOR" + attribute \enum_value_0010100 "OP_CROR" + attribute \enum_value_0010101 "OP_CRORC" + attribute \enum_value_0010110 "OP_CRXOR" + attribute \enum_value_0010111 "OP_DARN" + attribute \enum_value_0011000 "OP_DCBF" + attribute \enum_value_0011001 "OP_DCBST" + attribute \enum_value_0011010 "OP_DCBT" + attribute \enum_value_0011011 "OP_DCBTST" + attribute \enum_value_0011100 "OP_DCBZ" + attribute \enum_value_0011101 "OP_DIV" + attribute \enum_value_0011110 "OP_DIVE" + attribute \enum_value_0011111 "OP_EXTS" + attribute \enum_value_0100000 "OP_EXTSWSLI" + attribute \enum_value_0100001 "OP_ICBI" + attribute \enum_value_0100010 "OP_ICBT" + attribute \enum_value_0100011 "OP_ISEL" + attribute \enum_value_0100100 "OP_ISYNC" + attribute \enum_value_0100101 "OP_LOAD" + attribute \enum_value_0100110 "OP_STORE" + attribute \enum_value_0100111 "OP_MADDHD" + attribute \enum_value_0101000 "OP_MADDHDU" + attribute \enum_value_0101001 "OP_MADDLD" + attribute \enum_value_0101010 "OP_MCRF" + attribute \enum_value_0101011 "OP_MCRXR" + attribute \enum_value_0101100 "OP_MCRXRX" + attribute \enum_value_0101101 "OP_MFCR" + attribute \enum_value_0101110 "OP_MFSPR" + attribute \enum_value_0101111 "OP_MOD" + attribute \enum_value_0110000 "OP_MTCRF" + attribute \enum_value_0110001 "OP_MTSPR" + attribute \enum_value_0110010 "OP_MUL_L64" + attribute \enum_value_0110011 "OP_MUL_H64" + attribute \enum_value_0110100 "OP_MUL_H32" + attribute \enum_value_0110101 "OP_OR" + attribute \enum_value_0110110 "OP_POPCNT" + attribute \enum_value_0110111 "OP_PRTY" + attribute \enum_value_0111000 "OP_RLC" + attribute \enum_value_0111001 "OP_RLCL" + attribute \enum_value_0111010 "OP_RLCR" + attribute \enum_value_0111011 "OP_SETB" + attribute \enum_value_0111100 "OP_SHL" + attribute \enum_value_0111101 "OP_SHR" + attribute \enum_value_0111110 "OP_SYNC" + attribute \enum_value_0111111 "OP_TRAP" + attribute \enum_value_1000011 "OP_XOR" + attribute \enum_value_1000100 "OP_SIM_CONFIG" + attribute \enum_value_1000101 "OP_CROP" + attribute \enum_value_1000110 "OP_RFID" + attribute \enum_value_1000111 "OP_MFMSR" + attribute \enum_value_1001000 "OP_MTMSRD" + attribute \enum_value_1001001 "OP_SC" + attribute \enum_value_1001010 "OP_MTMSR" + attribute \enum_value_1001011 "OP_TLBIE" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire width 7 output 12 \spr_op__insn_type$2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire input 4 \spr_op__is_32bit + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" + wire output 15 \spr_op__is_32bit$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 2 input 10 \xer_ca + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 2 output 26 \xer_ca$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 27 \xer_ca_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire width 2 input 9 \xer_ov + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 2 output 24 \xer_ov$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 25 \xer_ov_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" + wire input 8 \xer_so + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 22 \xer_so$8 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 23 \xer_so_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:56" + cell $eq $eq$issuer_ls180.v:173055$12187 + parameter \A_SIGNED 0 + parameter \A_WIDTH 10 + parameter \B_SIGNED 0 + parameter \B_WIDTH 10 + parameter \Y_WIDTH 1 + connect \A \spr + connect \B 10'0000000001 + connect \Y $eq$issuer_ls180.v:173055$12187_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:56" + cell $eq $eq$issuer_ls180.v:173056$12188 + parameter \A_SIGNED 0 + parameter \A_WIDTH 10 + parameter \B_SIGNED 0 + parameter \B_WIDTH 10 + parameter \Y_WIDTH 1 + connect \A \spr + connect \B 10'0000000001 + connect \Y $eq$issuer_ls180.v:173056$12188_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:56" + cell $eq $eq$issuer_ls180.v:173057$12189 + parameter \A_SIGNED 0 + parameter \A_WIDTH 10 + parameter \B_SIGNED 0 + parameter \B_WIDTH 10 + parameter \Y_WIDTH 1 + connect \A \spr + connect \B 10'0000000001 + connect \Y $eq$issuer_ls180.v:173057$12189_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:56" + cell $eq $eq$issuer_ls180.v:173058$12190 + parameter \A_SIGNED 0 + parameter \A_WIDTH 10 + parameter \B_SIGNED 0 + parameter \B_WIDTH 10 + parameter \Y_WIDTH 1 + connect \A \spr + connect \B 10'0000000001 + connect \Y $eq$issuer_ls180.v:173058$12190_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:56" + cell $eq $eq$issuer_ls180.v:173059$12191 + parameter \A_SIGNED 0 + parameter \A_WIDTH 10 + parameter \B_SIGNED 0 + parameter \B_WIDTH 10 + parameter \Y_WIDTH 1 + connect \A \spr + connect \B 10'0000000001 + connect \Y $eq$issuer_ls180.v:173059$12191_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:56" + cell $eq $eq$issuer_ls180.v:173060$12192 + parameter \A_SIGNED 0 + parameter \A_WIDTH 10 + parameter \B_SIGNED 0 + parameter \B_WIDTH 10 + parameter \Y_WIDTH 1 + connect \A \spr + connect \B 10'0000000001 + connect \Y $eq$issuer_ls180.v:173060$12192_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:82" + cell $eq $eq$issuer_ls180.v:173061$12193 + parameter \A_SIGNED 0 + parameter \A_WIDTH 10 + parameter \B_SIGNED 0 + parameter \B_WIDTH 10 + parameter \Y_WIDTH 1 + connect \A \spr + connect \B 10'0000000001 + connect \Y $eq$issuer_ls180.v:173061$12193_Y + end + attribute \src "issuer_ls180.v:172796.7-172796.20" + process $proc$issuer_ls180.v:172796$12223 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "issuer_ls180.v:173062.3-173077.6" + process $proc$issuer_ls180.v:173062$12194 + assign { } { } + assign { } { } + assign $0\fast1$7[63:0]$12195 $1\fast1$7[63:0]$12196 + attribute \src "issuer_ls180.v:173063.5-173063.29" + switch \initial + attribute \src "issuer_ls180.v:173063.9-173063.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:46" + switch \spr_op__insn_type + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'0110001 + assign { } { } + assign $1\fast1$7[63:0]$12196 $2\fast1$7[63:0]$12197 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:49" + switch \spr + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0000001001 , 10'0000001000 , 10'1100101111 , 10'0000011010 , 10'0000011011 , 10'0000000001 , 10'0000010110 + assign { } { } + assign $2\fast1$7[63:0]$12197 \ra + case + assign $2\fast1$7[63:0]$12197 64'0000000000000000000000000000000000000000000000000000000000000000 + end + case + assign $1\fast1$7[63:0]$12196 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \fast1$7 $0\fast1$7[63:0]$12195 + end + attribute \src "issuer_ls180.v:173078.3-173096.6" + process $proc$issuer_ls180.v:173078$12198 + assign { } { } + assign { } { } + assign $0\spr1_ok[0:0] $1\spr1_ok[0:0] + attribute \src "issuer_ls180.v:173079.5-173079.29" + switch \initial + attribute \src "issuer_ls180.v:173079.9-173079.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:46" + switch \spr_op__insn_type + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'0110001 + assign { } { } + assign $1\spr1_ok[0:0] $2\spr1_ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:49" + switch \spr + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0000001001 , 10'0000001000 , 10'1100101111 , 10'0000011010 , 10'0000011011 , 10'0000000001 , 10'0000010110 + assign $2\spr1_ok[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case + assign { } { } + assign $2\spr1_ok[0:0] 1'1 + end + case + assign $1\spr1_ok[0:0] 1'0 + end + sync always + update \spr1_ok $0\spr1_ok[0:0] + end + attribute \src "issuer_ls180.v:173097.3-173138.6" + process $proc$issuer_ls180.v:173097$12199 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\o_ok[0:0] $1\o_ok[0:0] + assign $0\o[63:0] $1\o[63:0] + attribute \src "issuer_ls180.v:173098.5-173098.29" + switch \initial + attribute \src "issuer_ls180.v:173098.9-173098.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:46" + switch \spr_op__insn_type + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'0101110 + assign { } { } + assign { } { } + assign $1\o_ok[0:0] 1'1 + assign $1\o[63:0] $2\o[63:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:77" + switch \spr + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0000001001 , 10'0000001000 , 10'1100101111 , 10'0000011010 , 10'0000011011 , 10'0000000001 , 10'0000010110 , 10'0100001100 + assign { } { } + assign $2\o[63:0] [17:0] \fast1 [17:0] + assign $2\o[63:0] [63:18] $3\o[63:18] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:82" + switch \$23 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\o[63:18] [45:14] 0 + assign $3\o[63:18] [10:2] 9'000000000 + assign $3\o[63:18] [13] \xer_so + assign $3\o[63:18] [12] \xer_ov [0] + assign $3\o[63:18] [1] \xer_ov [1] + assign $3\o[63:18] [11] \xer_ca [0] + assign $3\o[63:18] [0] \xer_ca [1] + case + assign $3\o[63:18] \fast1 [63:18] + end + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0100001101 + assign $2\o[63:0] [63:32] 0 + assign $2\o[63:0] [31:0] \fast1 [63:32] + attribute \src "issuer_ls180.v:0.0-0.0" + case + assign { } { } + assign $2\o[63:0] \spr1 + end + case + assign $1\o_ok[0:0] 1'0 + assign $1\o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \o_ok $0\o_ok[0:0] + update \o $0\o[63:0] + end + attribute \src "issuer_ls180.v:173139.3-173154.6" + process $proc$issuer_ls180.v:173139$12200 + assign { } { } + assign { } { } + assign $0\fast1_ok[0:0] $1\fast1_ok[0:0] + attribute \src "issuer_ls180.v:173140.5-173140.29" + switch \initial + attribute \src "issuer_ls180.v:173140.9-173140.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:46" + switch \spr_op__insn_type + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'0110001 + assign { } { } + assign $1\fast1_ok[0:0] $2\fast1_ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:49" + switch \spr + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0000001001 , 10'0000001000 , 10'1100101111 , 10'0000011010 , 10'0000011011 , 10'0000000001 , 10'0000010110 + assign { } { } + assign $2\fast1_ok[0:0] 1'1 + case + assign $2\fast1_ok[0:0] 1'0 + end + case + assign $1\fast1_ok[0:0] 1'0 + end + sync always + update \fast1_ok $0\fast1_ok[0:0] + end + attribute \src "issuer_ls180.v:173155.3-173175.6" + process $proc$issuer_ls180.v:173155$12201 + assign { } { } + assign { } { } + assign $0\xer_so$8[0:0]$12202 $1\xer_so$8[0:0]$12203 + attribute \src "issuer_ls180.v:173156.5-173156.29" + switch \initial + attribute \src "issuer_ls180.v:173156.9-173156.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:46" + switch \spr_op__insn_type + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'0110001 + assign { } { } + assign $1\xer_so$8[0:0]$12203 $2\xer_so$8[0:0]$12204 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:49" + switch \spr + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0000001001 , 10'0000001000 , 10'1100101111 , 10'0000011010 , 10'0000011011 , 10'0000000001 , 10'0000010110 + assign { } { } + assign $2\xer_so$8[0:0]$12204 $3\xer_so$8[0:0]$12205 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:56" + switch \$11 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\xer_so$8[0:0]$12205 \ra [31] + case + assign $3\xer_so$8[0:0]$12205 1'0 + end + case + assign $2\xer_so$8[0:0]$12204 1'0 + end + case + assign $1\xer_so$8[0:0]$12203 1'0 + end + sync always + update \xer_so$8 $0\xer_so$8[0:0]$12202 + end + attribute \src "issuer_ls180.v:173176.3-173196.6" + process $proc$issuer_ls180.v:173176$12206 + assign { } { } + assign { } { } + assign $0\xer_so_ok[0:0] $1\xer_so_ok[0:0] + attribute \src "issuer_ls180.v:173177.5-173177.29" + switch \initial + attribute \src "issuer_ls180.v:173177.9-173177.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:46" + switch \spr_op__insn_type + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'0110001 + assign { } { } + assign $1\xer_so_ok[0:0] $2\xer_so_ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:49" + switch \spr + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0000001001 , 10'0000001000 , 10'1100101111 , 10'0000011010 , 10'0000011011 , 10'0000000001 , 10'0000010110 + assign { } { } + assign $2\xer_so_ok[0:0] $3\xer_so_ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:56" + switch \$13 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\xer_so_ok[0:0] 1'1 + case + assign $3\xer_so_ok[0:0] 1'0 + end + case + assign $2\xer_so_ok[0:0] 1'0 + end + case + assign $1\xer_so_ok[0:0] 1'0 + end + sync always + update \xer_so_ok $0\xer_so_ok[0:0] + end + attribute \src "issuer_ls180.v:173197.3-173220.6" + process $proc$issuer_ls180.v:173197$12207 + assign { } { } + assign { } { } + assign $0\xer_ov$9[1:0]$12208 $1\xer_ov$9[1:0]$12209 + attribute \src "issuer_ls180.v:173198.5-173198.29" + switch \initial + attribute \src "issuer_ls180.v:173198.9-173198.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:46" + switch \spr_op__insn_type + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'0110001 + assign { } { } + assign $1\xer_ov$9[1:0]$12209 $2\xer_ov$9[1:0]$12210 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:49" + switch \spr + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0000001001 , 10'0000001000 , 10'1100101111 , 10'0000011010 , 10'0000011011 , 10'0000000001 , 10'0000010110 + assign { } { } + assign $2\xer_ov$9[1:0]$12210 $3\xer_ov$9[1:0]$12211 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:56" + switch \$15 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\xer_ov$9[1:0]$12211 [0] \ra [30] + assign $3\xer_ov$9[1:0]$12211 [1] \ra [19] + case + assign $3\xer_ov$9[1:0]$12211 2'00 + end + case + assign $2\xer_ov$9[1:0]$12210 2'00 + end + case + assign $1\xer_ov$9[1:0]$12209 2'00 + end + sync always + update \xer_ov$9 $0\xer_ov$9[1:0]$12208 + end + attribute \src "issuer_ls180.v:173221.3-173241.6" + process $proc$issuer_ls180.v:173221$12212 + assign { } { } + assign { } { } + assign $0\xer_ov_ok[0:0] $1\xer_ov_ok[0:0] + attribute \src "issuer_ls180.v:173222.5-173222.29" + switch \initial + attribute \src "issuer_ls180.v:173222.9-173222.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:46" + switch \spr_op__insn_type + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'0110001 + assign { } { } + assign $1\xer_ov_ok[0:0] $2\xer_ov_ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:49" + switch \spr + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0000001001 , 10'0000001000 , 10'1100101111 , 10'0000011010 , 10'0000011011 , 10'0000000001 , 10'0000010110 + assign { } { } + assign $2\xer_ov_ok[0:0] $3\xer_ov_ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:56" + switch \$17 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\xer_ov_ok[0:0] 1'1 + case + assign $3\xer_ov_ok[0:0] 1'0 + end + case + assign $2\xer_ov_ok[0:0] 1'0 + end + case + assign $1\xer_ov_ok[0:0] 1'0 + end + sync always + update \xer_ov_ok $0\xer_ov_ok[0:0] + end + attribute \src "issuer_ls180.v:173242.3-173265.6" + process $proc$issuer_ls180.v:173242$12213 + assign { } { } + assign { } { } + assign $0\xer_ca$10[1:0]$12214 $1\xer_ca$10[1:0]$12215 + attribute \src "issuer_ls180.v:173243.5-173243.29" + switch \initial + attribute \src "issuer_ls180.v:173243.9-173243.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:46" + switch \spr_op__insn_type + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'0110001 + assign { } { } + assign $1\xer_ca$10[1:0]$12215 $2\xer_ca$10[1:0]$12216 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:49" + switch \spr + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0000001001 , 10'0000001000 , 10'1100101111 , 10'0000011010 , 10'0000011011 , 10'0000000001 , 10'0000010110 + assign { } { } + assign $2\xer_ca$10[1:0]$12216 $3\xer_ca$10[1:0]$12217 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:56" + switch \$19 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\xer_ca$10[1:0]$12217 [0] \ra [29] + assign $3\xer_ca$10[1:0]$12217 [1] \ra [18] + case + assign $3\xer_ca$10[1:0]$12217 2'00 + end + case + assign $2\xer_ca$10[1:0]$12216 2'00 + end + case + assign $1\xer_ca$10[1:0]$12215 2'00 + end + sync always + update \xer_ca$10 $0\xer_ca$10[1:0]$12214 + end + attribute \src "issuer_ls180.v:173266.3-173286.6" + process $proc$issuer_ls180.v:173266$12218 + assign { } { } + assign { } { } + assign $0\xer_ca_ok[0:0] $1\xer_ca_ok[0:0] + attribute \src "issuer_ls180.v:173267.5-173267.29" + switch \initial + attribute \src "issuer_ls180.v:173267.9-173267.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:46" + switch \spr_op__insn_type + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'0110001 + assign { } { } + assign $1\xer_ca_ok[0:0] $2\xer_ca_ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:49" + switch \spr + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0000001001 , 10'0000001000 , 10'1100101111 , 10'0000011010 , 10'0000011011 , 10'0000000001 , 10'0000010110 + assign { } { } + assign $2\xer_ca_ok[0:0] $3\xer_ca_ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:56" + switch \$21 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\xer_ca_ok[0:0] 1'1 + case + assign $3\xer_ca_ok[0:0] 1'0 + end + case + assign $2\xer_ca_ok[0:0] 1'0 + end + case + assign $1\xer_ca_ok[0:0] 1'0 + end + sync always + update \xer_ca_ok $0\xer_ca_ok[0:0] + end + attribute \src "issuer_ls180.v:173287.3-173305.6" + process $proc$issuer_ls180.v:173287$12219 + assign { } { } + assign { } { } + assign $0\spr1$6[63:0]$12220 $1\spr1$6[63:0]$12221 + attribute \src "issuer_ls180.v:173288.5-173288.29" + switch \initial + attribute \src "issuer_ls180.v:173288.9-173288.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:46" + switch \spr_op__insn_type + attribute \src "issuer_ls180.v:0.0-0.0" + case 7'0110001 + assign { } { } + assign $1\spr1$6[63:0]$12221 $2\spr1$6[63:0]$12222 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:49" + switch \spr + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0000001001 , 10'0000001000 , 10'1100101111 , 10'0000011010 , 10'0000011011 , 10'0000000001 , 10'0000010110 + assign $2\spr1$6[63:0]$12222 64'0000000000000000000000000000000000000000000000000000000000000000 + attribute \src "issuer_ls180.v:0.0-0.0" + case + assign { } { } + assign $2\spr1$6[63:0]$12222 \ra + end + case + assign $1\spr1$6[63:0]$12221 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \spr1$6 $0\spr1$6[63:0]$12220 + end + connect \$11 $eq$issuer_ls180.v:173055$12187_Y + connect \$13 $eq$issuer_ls180.v:173056$12188_Y + connect \$15 $eq$issuer_ls180.v:173057$12189_Y + connect \$17 $eq$issuer_ls180.v:173058$12190_Y + connect \$19 $eq$issuer_ls180.v:173059$12191_Y + connect \$21 $eq$issuer_ls180.v:173060$12192_Y + connect \$23 $eq$issuer_ls180.v:173061$12193_Y + connect { \spr_op__is_32bit$5 \spr_op__insn$4 \spr_op__fn_unit$3 \spr_op__insn_type$2 } { \spr_op__is_32bit \spr_op__insn \spr_op__fn_unit \spr_op__insn_type } + connect \muxid$1 \muxid + connect \spr { \spr_op__insn [15:11] \spr_op__insn [20:16] } +end +attribute \src "issuer_ls180.v:173313.1-174128.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.dec2.dec_a.sprmap" +attribute \generator "nMigen" +module \sprmap + attribute \src "issuer_ls180.v:173440.3-173470.6" + wire width 3 $0\fast_o[2:0] + attribute \src "issuer_ls180.v:173471.3-173501.6" + wire $0\fast_o_ok[0:0] + attribute \src "issuer_ls180.v:173314.7-173314.20" + wire $0\initial[0:0] + attribute \src "issuer_ls180.v:173502.3-173814.6" + wire width 10 $0\spr_o[9:0] + attribute \src "issuer_ls180.v:173815.3-174127.6" + wire $0\spr_o_ok[0:0] + attribute \src "issuer_ls180.v:173440.3-173470.6" + wire width 3 $1\fast_o[2:0] + attribute \src "issuer_ls180.v:173471.3-173501.6" + wire $1\fast_o_ok[0:0] + attribute \src "issuer_ls180.v:173502.3-173814.6" + wire width 10 $1\spr_o[9:0] + attribute \src "issuer_ls180.v:173815.3-174127.6" + wire $1\spr_o_ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 3 output 3 \fast_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 4 \fast_o_ok + attribute \src "issuer_ls180.v:173314.7-173314.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:59" + wire width 10 input 5 \spr_i + attribute \enum_base_type "SPR" + attribute \enum_value_0000000001 "XER" + attribute \enum_value_0000000011 "DSCR" + attribute \enum_value_0000001000 "LR" + attribute \enum_value_0000001001 "CTR" + attribute \enum_value_0000001101 "AMR" + attribute \enum_value_0000010001 "DSCR_priv" + attribute \enum_value_0000010010 "DSISR" + attribute \enum_value_0000010011 "DAR" + attribute \enum_value_0000010110 "DEC" + attribute \enum_value_0000011010 "SRR0" + attribute \enum_value_0000011011 "SRR1" + attribute \enum_value_0000011100 "CFAR" + attribute \enum_value_0000011101 "AMR_priv" + attribute \enum_value_0000110000 "PIDR" + attribute \enum_value_0000111101 "IAMR" + attribute \enum_value_0010000000 "TFHAR" + attribute \enum_value_0010000001 "TFIAR" + attribute \enum_value_0010000010 "TEXASR" + attribute \enum_value_0010000011 "TEXASRU" + attribute \enum_value_0010001000 "CTRL" + attribute \enum_value_0010010000 "TIDR" + attribute \enum_value_0010011000 "CTRL_priv" + attribute \enum_value_0010011001 "FSCR" + attribute \enum_value_0010011101 "UAMOR" + attribute \enum_value_0010011110 "GSR" + attribute \enum_value_0010011111 "PSPB" + attribute \enum_value_0010110000 "DPDES" + attribute \enum_value_0010110100 "DAWR0" + attribute \enum_value_0010111010 "RPR" + attribute \enum_value_0010111011 "CIABR" + attribute \enum_value_0010111100 "DAWRX0" + attribute \enum_value_0010111110 "HFSCR" + attribute \enum_value_0100000000 "VRSAVE" + attribute \enum_value_0100000011 "SPRG3" + attribute \enum_value_0100001100 "TB" + attribute \enum_value_0100001101 "TBU" + attribute \enum_value_0100010000 "SPRG0_priv" + attribute \enum_value_0100010001 "SPRG1_priv" + attribute \enum_value_0100010010 "SPRG2_priv" + attribute \enum_value_0100010011 "SPRG3_priv" + attribute \enum_value_0100011011 "CIR" + attribute \enum_value_0100011100 "TBL" + attribute \enum_value_0100011101 "TBU_hypv" + attribute \enum_value_0100011110 "TBU40" + attribute \enum_value_0100011111 "PVR" + attribute \enum_value_0100110000 "HSPRG0" + attribute \enum_value_0100110001 "HSPRG1" + attribute \enum_value_0100110010 "HDSISR" + attribute \enum_value_0100110011 "HDAR" + attribute \enum_value_0100110100 "SPURR" + attribute \enum_value_0100110101 "PURR" + attribute \enum_value_0100110110 "HDEC" + attribute \enum_value_0100111001 "HRMOR" + attribute \enum_value_0100111010 "HSRR0" + attribute \enum_value_0100111011 "HSRR1" + attribute \enum_value_0100111110 "LPCR" + attribute \enum_value_0100111111 "LPIDR" + attribute \enum_value_0101010000 "HMER" + attribute \enum_value_0101010001 "HMEER" + attribute \enum_value_0101010010 "PCR" + attribute \enum_value_0101010011 "HEIR" + attribute \enum_value_0101011101 "AMOR" + attribute \enum_value_0110111110 "TIR" + attribute \enum_value_0111010000 "PTCR" + attribute \enum_value_1100000000 "SIER" + attribute \enum_value_1100000001 "MMCR2" + attribute \enum_value_1100000010 "MMCRA" + attribute \enum_value_1100000011 "PMC1" + attribute \enum_value_1100000100 "PMC2" + attribute \enum_value_1100000101 "PMC3" + attribute \enum_value_1100000110 "PMC4" + attribute \enum_value_1100000111 "PMC5" + attribute \enum_value_1100001000 "PMC6" + attribute \enum_value_1100001011 "MMCR0" + attribute \enum_value_1100001100 "SIAR" + attribute \enum_value_1100001101 "SDAR" + attribute \enum_value_1100001110 "MMCR1" + attribute \enum_value_1100010000 "SIER_priv" + attribute \enum_value_1100010001 "MMCR2_priv" + attribute \enum_value_1100010010 "MMCRA_priv" + attribute \enum_value_1100010011 "PMC1_priv" + attribute \enum_value_1100010100 "PMC2_priv" + attribute \enum_value_1100010101 "PMC3_priv" + attribute \enum_value_1100010110 "PMC4_priv" + attribute \enum_value_1100010111 "PMC5_priv" + attribute \enum_value_1100011000 "PMC6_priv" + attribute \enum_value_1100011011 "MMCR0_priv" + attribute \enum_value_1100011100 "SIAR_priv" + attribute \enum_value_1100011101 "SDAR_priv" + attribute \enum_value_1100011110 "MMCR1_priv" + attribute \enum_value_1100100000 "BESCRS" + attribute \enum_value_1100100001 "BESCRSU" + attribute \enum_value_1100100010 "BESCRR" + attribute \enum_value_1100100011 "BESCRRU" + attribute \enum_value_1100100100 "EBBHR" + attribute \enum_value_1100100101 "EBBRR" + attribute \enum_value_1100100110 "BESCR" + attribute \enum_value_1100101000 "reserved808" + attribute \enum_value_1100101001 "reserved809" + attribute \enum_value_1100101010 "reserved810" + attribute \enum_value_1100101011 "reserved811" + attribute \enum_value_1100101111 "TAR" + attribute \enum_value_1100110000 "ASDR" + attribute \enum_value_1100110111 "PSSCR" + attribute \enum_value_1101010000 "IC" + attribute \enum_value_1101010001 "VTB" + attribute \enum_value_1101010111 "PSSCR_hypv" + attribute \enum_value_1110000000 "PPR" + attribute \enum_value_1110000010 "PPR32" + attribute \enum_value_1111111111 "PIR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 10 output 1 \spr_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 2 \spr_o_ok + attribute \src "issuer_ls180.v:173314.7-173314.20" + process $proc$issuer_ls180.v:173314$12228 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "issuer_ls180.v:173440.3-173470.6" + process $proc$issuer_ls180.v:173440$12224 + assign { } { } + assign { } { } + assign $0\fast_o[2:0] $1\fast_o[2:0] + attribute \src "issuer_ls180.v:173441.5-173441.29" + switch \initial + attribute \src "issuer_ls180.v:173441.9-173441.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:65" + switch \spr_i + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0000000001 + assign { } { } + assign $1\fast_o[2:0] 3'101 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0000001000 + assign { } { } + assign $1\fast_o[2:0] 3'001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0000001001 + assign { } { } + assign $1\fast_o[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0000010110 + assign { } { } + assign $1\fast_o[2:0] 3'110 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0000011010 + assign { } { } + assign $1\fast_o[2:0] 3'011 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0000011011 + assign { } { } + assign $1\fast_o[2:0] 3'100 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0100001100 + assign { } { } + assign $1\fast_o[2:0] 3'111 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'1100101111 + assign { } { } + assign $1\fast_o[2:0] 3'010 + case + assign $1\fast_o[2:0] 3'000 + end + sync always + update \fast_o $0\fast_o[2:0] + end + attribute \src "issuer_ls180.v:173471.3-173501.6" + process $proc$issuer_ls180.v:173471$12225 + assign { } { } + assign { } { } + assign $0\fast_o_ok[0:0] $1\fast_o_ok[0:0] + attribute \src "issuer_ls180.v:173472.5-173472.29" + switch \initial + attribute \src "issuer_ls180.v:173472.9-173472.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:65" + switch \spr_i + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0000000001 + assign { } { } + assign $1\fast_o_ok[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0000001000 + assign { } { } + assign $1\fast_o_ok[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0000001001 + assign { } { } + assign $1\fast_o_ok[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0000010110 + assign { } { } + assign $1\fast_o_ok[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0000011010 + assign { } { } + assign $1\fast_o_ok[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0000011011 + assign { } { } + assign $1\fast_o_ok[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0100001100 + assign { } { } + assign $1\fast_o_ok[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'1100101111 + assign { } { } + assign $1\fast_o_ok[0:0] 1'1 + case + assign $1\fast_o_ok[0:0] 1'0 + end + sync always + update \fast_o_ok $0\fast_o_ok[0:0] + end + attribute \src "issuer_ls180.v:173502.3-173814.6" + process $proc$issuer_ls180.v:173502$12226 + assign { } { } + assign { } { } + assign $0\spr_o[9:0] $1\spr_o[9:0] + attribute \src "issuer_ls180.v:173503.5-173503.29" + switch \initial + attribute \src "issuer_ls180.v:173503.9-173503.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:65" + switch \spr_i + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0000000011 + assign { } { } + assign $1\spr_o[9:0] 10'0000000001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0000001101 + assign { } { } + assign $1\spr_o[9:0] 10'0000000100 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0000010001 + assign { } { } + assign $1\spr_o[9:0] 10'0000000101 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0000010010 + assign { } { } + assign $1\spr_o[9:0] 10'0000000110 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0000010011 + assign { } { } + assign $1\spr_o[9:0] 10'0000000111 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0000011100 + assign { } { } + assign $1\spr_o[9:0] 10'0000001011 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0000011101 + assign { } { } + assign $1\spr_o[9:0] 10'0000001100 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0000110000 + assign { } { } + assign $1\spr_o[9:0] 10'0000001101 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0000111101 + assign { } { } + assign $1\spr_o[9:0] 10'0000001110 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0010000000 + assign { } { } + assign $1\spr_o[9:0] 10'0000001111 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0010000001 + assign { } { } + assign $1\spr_o[9:0] 10'0000010000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0010000010 + assign { } { } + assign $1\spr_o[9:0] 10'0000010001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0010000011 + assign { } { } + assign $1\spr_o[9:0] 10'0000010010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0010001000 + assign { } { } + assign $1\spr_o[9:0] 10'0000010011 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0010010000 + assign { } { } + assign $1\spr_o[9:0] 10'0000010100 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0010011000 + assign { } { } + assign $1\spr_o[9:0] 10'0000010101 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0010011001 + assign { } { } + assign $1\spr_o[9:0] 10'0000010110 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0010011101 + assign { } { } + assign $1\spr_o[9:0] 10'0000010111 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0010011110 + assign { } { } + assign $1\spr_o[9:0] 10'0000011000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0010011111 + assign { } { } + assign $1\spr_o[9:0] 10'0000011001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0010110000 + assign { } { } + assign $1\spr_o[9:0] 10'0000011010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0010110100 + assign { } { } + assign $1\spr_o[9:0] 10'0000011011 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0010111010 + assign { } { } + assign $1\spr_o[9:0] 10'0000011100 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0010111011 + assign { } { } + assign $1\spr_o[9:0] 10'0000011101 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0010111100 + assign { } { } + assign $1\spr_o[9:0] 10'0000011110 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0010111110 + assign { } { } + assign $1\spr_o[9:0] 10'0000011111 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0100000000 + assign { } { } + assign $1\spr_o[9:0] 10'0000100000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0100000011 + assign { } { } + assign $1\spr_o[9:0] 10'0000100001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0100001101 + assign { } { } + assign $1\spr_o[9:0] 10'0000100011 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0100010000 + assign { } { } + assign $1\spr_o[9:0] 10'0000100100 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0100010001 + assign { } { } + assign $1\spr_o[9:0] 10'0000100101 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0100010010 + assign { } { } + assign $1\spr_o[9:0] 10'0000100110 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0100010011 + assign { } { } + assign $1\spr_o[9:0] 10'0000100111 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0100011011 + assign { } { } + assign $1\spr_o[9:0] 10'0000101000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0100011100 + assign { } { } + assign $1\spr_o[9:0] 10'0000101001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0100011101 + assign { } { } + assign $1\spr_o[9:0] 10'0000101010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0100011110 + assign { } { } + assign $1\spr_o[9:0] 10'0000101011 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0100011111 + assign { } { } + assign $1\spr_o[9:0] 10'0000101100 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0100110000 + assign { } { } + assign $1\spr_o[9:0] 10'0000101101 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0100110001 + assign { } { } + assign $1\spr_o[9:0] 10'0000101110 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0100110010 + assign { } { } + assign $1\spr_o[9:0] 10'0000101111 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0100110011 + assign { } { } + assign $1\spr_o[9:0] 10'0000110000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0100110100 + assign { } { } + assign $1\spr_o[9:0] 10'0000110001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0100110101 + assign { } { } + assign $1\spr_o[9:0] 10'0000110010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0100110110 + assign { } { } + assign $1\spr_o[9:0] 10'0000110011 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0100111001 + assign { } { } + assign $1\spr_o[9:0] 10'0000110100 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0100111010 + assign { } { } + assign $1\spr_o[9:0] 10'0000110101 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0100111011 + assign { } { } + assign $1\spr_o[9:0] 10'0000110110 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0100111110 + assign { } { } + assign $1\spr_o[9:0] 10'0000110111 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0100111111 + assign { } { } + assign $1\spr_o[9:0] 10'0000111000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0101010000 + assign { } { } + assign $1\spr_o[9:0] 10'0000111001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0101010001 + assign { } { } + assign $1\spr_o[9:0] 10'0000111010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0101010010 + assign { } { } + assign $1\spr_o[9:0] 10'0000111011 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0101010011 + assign { } { } + assign $1\spr_o[9:0] 10'0000111100 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0101011101 + assign { } { } + assign $1\spr_o[9:0] 10'0000111101 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0110111110 + assign { } { } + assign $1\spr_o[9:0] 10'0000111110 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0111010000 + assign { } { } + assign $1\spr_o[9:0] 10'0000111111 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'1100000000 + assign { } { } + assign $1\spr_o[9:0] 10'0001000000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'1100000001 + assign { } { } + assign $1\spr_o[9:0] 10'0001000001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'1100000010 + assign { } { } + assign $1\spr_o[9:0] 10'0001000010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'1100000011 + assign { } { } + assign $1\spr_o[9:0] 10'0001000011 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'1100000100 + assign { } { } + assign $1\spr_o[9:0] 10'0001000100 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'1100000101 + assign { } { } + assign $1\spr_o[9:0] 10'0001000101 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'1100000110 + assign { } { } + assign $1\spr_o[9:0] 10'0001000110 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'1100000111 + assign { } { } + assign $1\spr_o[9:0] 10'0001000111 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'1100001000 + assign { } { } + assign $1\spr_o[9:0] 10'0001001000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'1100001011 + assign { } { } + assign $1\spr_o[9:0] 10'0001001001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'1100001100 + assign { } { } + assign $1\spr_o[9:0] 10'0001001010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'1100001101 + assign { } { } + assign $1\spr_o[9:0] 10'0001001011 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'1100001110 + assign { } { } + assign $1\spr_o[9:0] 10'0001001100 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'1100010000 + assign { } { } + assign $1\spr_o[9:0] 10'0001001101 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'1100010001 + assign { } { } + assign $1\spr_o[9:0] 10'0001001110 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'1100010010 + assign { } { } + assign $1\spr_o[9:0] 10'0001001111 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'1100010011 + assign { } { } + assign $1\spr_o[9:0] 10'0001010000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'1100010100 + assign { } { } + assign $1\spr_o[9:0] 10'0001010001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'1100010101 + assign { } { } + assign $1\spr_o[9:0] 10'0001010010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'1100010110 + assign { } { } + assign $1\spr_o[9:0] 10'0001010011 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'1100010111 + assign { } { } + assign $1\spr_o[9:0] 10'0001010100 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'1100011000 + assign { } { } + assign $1\spr_o[9:0] 10'0001010101 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'1100011011 + assign { } { } + assign $1\spr_o[9:0] 10'0001010110 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'1100011100 + assign { } { } + assign $1\spr_o[9:0] 10'0001010111 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'1100011101 + assign { } { } + assign $1\spr_o[9:0] 10'0001011000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'1100011110 + assign { } { } + assign $1\spr_o[9:0] 10'0001011001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'1100100000 + assign { } { } + assign $1\spr_o[9:0] 10'0001011010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'1100100001 + assign { } { } + assign $1\spr_o[9:0] 10'0001011011 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'1100100010 + assign { } { } + assign $1\spr_o[9:0] 10'0001011100 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'1100100011 + assign { } { } + assign $1\spr_o[9:0] 10'0001011101 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'1100100100 + assign { } { } + assign $1\spr_o[9:0] 10'0001011110 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'1100100101 + assign { } { } + assign $1\spr_o[9:0] 10'0001011111 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'1100100110 + assign { } { } + assign $1\spr_o[9:0] 10'0001100000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'1100101000 + assign { } { } + assign $1\spr_o[9:0] 10'0001100001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'1100101001 + assign { } { } + assign $1\spr_o[9:0] 10'0001100010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'1100101010 + assign { } { } + assign $1\spr_o[9:0] 10'0001100011 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'1100101011 + assign { } { } + assign $1\spr_o[9:0] 10'0001100100 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'1100110000 + assign { } { } + assign $1\spr_o[9:0] 10'0001100110 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'1100110111 + assign { } { } + assign $1\spr_o[9:0] 10'0001100111 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'1101010000 + assign { } { } + assign $1\spr_o[9:0] 10'0001101000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'1101010001 + assign { } { } + assign $1\spr_o[9:0] 10'0001101001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'1101010111 + assign { } { } + assign $1\spr_o[9:0] 10'0001101010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'1110000000 + assign { } { } + assign $1\spr_o[9:0] 10'0001101011 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'1110000010 + assign { } { } + assign $1\spr_o[9:0] 10'0001101100 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'1111111111 + assign { } { } + assign $1\spr_o[9:0] 10'0001101101 + case + assign $1\spr_o[9:0] 10'0000000000 + end + sync always + update \spr_o $0\spr_o[9:0] + end + attribute \src "issuer_ls180.v:173815.3-174127.6" + process $proc$issuer_ls180.v:173815$12227 + assign { } { } + assign { } { } + assign $0\spr_o_ok[0:0] $1\spr_o_ok[0:0] + attribute \src "issuer_ls180.v:173816.5-173816.29" + switch \initial + attribute \src "issuer_ls180.v:173816.9-173816.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:65" + switch \spr_i + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0000000011 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0000001101 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0000010001 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0000010010 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0000010011 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0000011100 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0000011101 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0000110000 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0000111101 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0010000000 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0010000001 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0010000010 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0010000011 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0010001000 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0010010000 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0010011000 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0010011001 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0010011101 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0010011110 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0010011111 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0010110000 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0010110100 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0010111010 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0010111011 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0010111100 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0010111110 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0100000000 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0100000011 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0100001101 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0100010000 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0100010001 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0100010010 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0100010011 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0100011011 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0100011100 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0100011101 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0100011110 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0100011111 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0100110000 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0100110001 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0100110010 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0100110011 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0100110100 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0100110101 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0100110110 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0100111001 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0100111010 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0100111011 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0100111110 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0100111111 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0101010000 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0101010001 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0101010010 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0101010011 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0101011101 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0110111110 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0111010000 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'1100000000 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'1100000001 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'1100000010 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'1100000011 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'1100000100 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'1100000101 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'1100000110 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'1100000111 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'1100001000 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'1100001011 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'1100001100 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'1100001101 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'1100001110 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'1100010000 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'1100010001 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'1100010010 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'1100010011 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'1100010100 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'1100010101 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'1100010110 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'1100010111 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'1100011000 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'1100011011 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'1100011100 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'1100011101 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'1100011110 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'1100100000 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'1100100001 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'1100100010 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'1100100011 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'1100100100 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'1100100101 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'1100100110 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'1100101000 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'1100101001 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'1100101010 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'1100101011 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'1100110000 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'1100110111 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'1101010000 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'1101010001 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'1101010111 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'1110000000 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'1110000010 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'1111111111 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + case + assign $1\spr_o_ok[0:0] 1'0 + end + sync always + update \spr_o_ok $0\spr_o_ok[0:0] + end +end +attribute \src "issuer_ls180.v:174132.1-174947.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.dec2.dec_o.sprmap" +attribute \generator "nMigen" +module \sprmap$209 + attribute \src "issuer_ls180.v:174259.3-174289.6" + wire width 3 $0\fast_o[2:0] + attribute \src "issuer_ls180.v:174290.3-174320.6" + wire $0\fast_o_ok[0:0] + attribute \src "issuer_ls180.v:174133.7-174133.20" + wire $0\initial[0:0] + attribute \src "issuer_ls180.v:174321.3-174633.6" + wire width 10 $0\spr_o[9:0] + attribute \src "issuer_ls180.v:174634.3-174946.6" + wire $0\spr_o_ok[0:0] + attribute \src "issuer_ls180.v:174259.3-174289.6" + wire width 3 $1\fast_o[2:0] + attribute \src "issuer_ls180.v:174290.3-174320.6" + wire $1\fast_o_ok[0:0] + attribute \src "issuer_ls180.v:174321.3-174633.6" + wire width 10 $1\spr_o[9:0] + attribute \src "issuer_ls180.v:174634.3-174946.6" + wire $1\spr_o_ok[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 3 output 3 \fast_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 4 \fast_o_ok + attribute \src "issuer_ls180.v:174133.7-174133.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:59" + wire width 10 input 5 \spr_i + attribute \enum_base_type "SPR" + attribute \enum_value_0000000001 "XER" + attribute \enum_value_0000000011 "DSCR" + attribute \enum_value_0000001000 "LR" + attribute \enum_value_0000001001 "CTR" + attribute \enum_value_0000001101 "AMR" + attribute \enum_value_0000010001 "DSCR_priv" + attribute \enum_value_0000010010 "DSISR" + attribute \enum_value_0000010011 "DAR" + attribute \enum_value_0000010110 "DEC" + attribute \enum_value_0000011010 "SRR0" + attribute \enum_value_0000011011 "SRR1" + attribute \enum_value_0000011100 "CFAR" + attribute \enum_value_0000011101 "AMR_priv" + attribute \enum_value_0000110000 "PIDR" + attribute \enum_value_0000111101 "IAMR" + attribute \enum_value_0010000000 "TFHAR" + attribute \enum_value_0010000001 "TFIAR" + attribute \enum_value_0010000010 "TEXASR" + attribute \enum_value_0010000011 "TEXASRU" + attribute \enum_value_0010001000 "CTRL" + attribute \enum_value_0010010000 "TIDR" + attribute \enum_value_0010011000 "CTRL_priv" + attribute \enum_value_0010011001 "FSCR" + attribute \enum_value_0010011101 "UAMOR" + attribute \enum_value_0010011110 "GSR" + attribute \enum_value_0010011111 "PSPB" + attribute \enum_value_0010110000 "DPDES" + attribute \enum_value_0010110100 "DAWR0" + attribute \enum_value_0010111010 "RPR" + attribute \enum_value_0010111011 "CIABR" + attribute \enum_value_0010111100 "DAWRX0" + attribute \enum_value_0010111110 "HFSCR" + attribute \enum_value_0100000000 "VRSAVE" + attribute \enum_value_0100000011 "SPRG3" + attribute \enum_value_0100001100 "TB" + attribute \enum_value_0100001101 "TBU" + attribute \enum_value_0100010000 "SPRG0_priv" + attribute \enum_value_0100010001 "SPRG1_priv" + attribute \enum_value_0100010010 "SPRG2_priv" + attribute \enum_value_0100010011 "SPRG3_priv" + attribute \enum_value_0100011011 "CIR" + attribute \enum_value_0100011100 "TBL" + attribute \enum_value_0100011101 "TBU_hypv" + attribute \enum_value_0100011110 "TBU40" + attribute \enum_value_0100011111 "PVR" + attribute \enum_value_0100110000 "HSPRG0" + attribute \enum_value_0100110001 "HSPRG1" + attribute \enum_value_0100110010 "HDSISR" + attribute \enum_value_0100110011 "HDAR" + attribute \enum_value_0100110100 "SPURR" + attribute \enum_value_0100110101 "PURR" + attribute \enum_value_0100110110 "HDEC" + attribute \enum_value_0100111001 "HRMOR" + attribute \enum_value_0100111010 "HSRR0" + attribute \enum_value_0100111011 "HSRR1" + attribute \enum_value_0100111110 "LPCR" + attribute \enum_value_0100111111 "LPIDR" + attribute \enum_value_0101010000 "HMER" + attribute \enum_value_0101010001 "HMEER" + attribute \enum_value_0101010010 "PCR" + attribute \enum_value_0101010011 "HEIR" + attribute \enum_value_0101011101 "AMOR" + attribute \enum_value_0110111110 "TIR" + attribute \enum_value_0111010000 "PTCR" + attribute \enum_value_1100000000 "SIER" + attribute \enum_value_1100000001 "MMCR2" + attribute \enum_value_1100000010 "MMCRA" + attribute \enum_value_1100000011 "PMC1" + attribute \enum_value_1100000100 "PMC2" + attribute \enum_value_1100000101 "PMC3" + attribute \enum_value_1100000110 "PMC4" + attribute \enum_value_1100000111 "PMC5" + attribute \enum_value_1100001000 "PMC6" + attribute \enum_value_1100001011 "MMCR0" + attribute \enum_value_1100001100 "SIAR" + attribute \enum_value_1100001101 "SDAR" + attribute \enum_value_1100001110 "MMCR1" + attribute \enum_value_1100010000 "SIER_priv" + attribute \enum_value_1100010001 "MMCR2_priv" + attribute \enum_value_1100010010 "MMCRA_priv" + attribute \enum_value_1100010011 "PMC1_priv" + attribute \enum_value_1100010100 "PMC2_priv" + attribute \enum_value_1100010101 "PMC3_priv" + attribute \enum_value_1100010110 "PMC4_priv" + attribute \enum_value_1100010111 "PMC5_priv" + attribute \enum_value_1100011000 "PMC6_priv" + attribute \enum_value_1100011011 "MMCR0_priv" + attribute \enum_value_1100011100 "SIAR_priv" + attribute \enum_value_1100011101 "SDAR_priv" + attribute \enum_value_1100011110 "MMCR1_priv" + attribute \enum_value_1100100000 "BESCRS" + attribute \enum_value_1100100001 "BESCRSU" + attribute \enum_value_1100100010 "BESCRR" + attribute \enum_value_1100100011 "BESCRRU" + attribute \enum_value_1100100100 "EBBHR" + attribute \enum_value_1100100101 "EBBRR" + attribute \enum_value_1100100110 "BESCR" + attribute \enum_value_1100101000 "reserved808" + attribute \enum_value_1100101001 "reserved809" + attribute \enum_value_1100101010 "reserved810" + attribute \enum_value_1100101011 "reserved811" + attribute \enum_value_1100101111 "TAR" + attribute \enum_value_1100110000 "ASDR" + attribute \enum_value_1100110111 "PSSCR" + attribute \enum_value_1101010000 "IC" + attribute \enum_value_1101010001 "VTB" + attribute \enum_value_1101010111 "PSSCR_hypv" + attribute \enum_value_1110000000 "PPR" + attribute \enum_value_1110000010 "PPR32" + attribute \enum_value_1111111111 "PIR" + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 10 output 1 \spr_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire output 2 \spr_o_ok + attribute \src "issuer_ls180.v:174133.7-174133.20" + process $proc$issuer_ls180.v:174133$12233 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "issuer_ls180.v:174259.3-174289.6" + process $proc$issuer_ls180.v:174259$12229 + assign { } { } + assign { } { } + assign $0\fast_o[2:0] $1\fast_o[2:0] + attribute \src "issuer_ls180.v:174260.5-174260.29" + switch \initial + attribute \src "issuer_ls180.v:174260.9-174260.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:65" + switch \spr_i + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0000000001 + assign { } { } + assign $1\fast_o[2:0] 3'101 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0000001000 + assign { } { } + assign $1\fast_o[2:0] 3'001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0000001001 + assign { } { } + assign $1\fast_o[2:0] 3'000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0000010110 + assign { } { } + assign $1\fast_o[2:0] 3'110 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0000011010 + assign { } { } + assign $1\fast_o[2:0] 3'011 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0000011011 + assign { } { } + assign $1\fast_o[2:0] 3'100 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0100001100 + assign { } { } + assign $1\fast_o[2:0] 3'111 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'1100101111 + assign { } { } + assign $1\fast_o[2:0] 3'010 + case + assign $1\fast_o[2:0] 3'000 + end + sync always + update \fast_o $0\fast_o[2:0] + end + attribute \src "issuer_ls180.v:174290.3-174320.6" + process $proc$issuer_ls180.v:174290$12230 + assign { } { } + assign { } { } + assign $0\fast_o_ok[0:0] $1\fast_o_ok[0:0] + attribute \src "issuer_ls180.v:174291.5-174291.29" + switch \initial + attribute \src "issuer_ls180.v:174291.9-174291.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:65" + switch \spr_i + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0000000001 + assign { } { } + assign $1\fast_o_ok[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0000001000 + assign { } { } + assign $1\fast_o_ok[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0000001001 + assign { } { } + assign $1\fast_o_ok[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0000010110 + assign { } { } + assign $1\fast_o_ok[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0000011010 + assign { } { } + assign $1\fast_o_ok[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0000011011 + assign { } { } + assign $1\fast_o_ok[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0100001100 + assign { } { } + assign $1\fast_o_ok[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'1100101111 + assign { } { } + assign $1\fast_o_ok[0:0] 1'1 + case + assign $1\fast_o_ok[0:0] 1'0 + end + sync always + update \fast_o_ok $0\fast_o_ok[0:0] + end + attribute \src "issuer_ls180.v:174321.3-174633.6" + process $proc$issuer_ls180.v:174321$12231 + assign { } { } + assign { } { } + assign $0\spr_o[9:0] $1\spr_o[9:0] + attribute \src "issuer_ls180.v:174322.5-174322.29" + switch \initial + attribute \src "issuer_ls180.v:174322.9-174322.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:65" + switch \spr_i + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0000000011 + assign { } { } + assign $1\spr_o[9:0] 10'0000000001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0000001101 + assign { } { } + assign $1\spr_o[9:0] 10'0000000100 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0000010001 + assign { } { } + assign $1\spr_o[9:0] 10'0000000101 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0000010010 + assign { } { } + assign $1\spr_o[9:0] 10'0000000110 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0000010011 + assign { } { } + assign $1\spr_o[9:0] 10'0000000111 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0000011100 + assign { } { } + assign $1\spr_o[9:0] 10'0000001011 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0000011101 + assign { } { } + assign $1\spr_o[9:0] 10'0000001100 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0000110000 + assign { } { } + assign $1\spr_o[9:0] 10'0000001101 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0000111101 + assign { } { } + assign $1\spr_o[9:0] 10'0000001110 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0010000000 + assign { } { } + assign $1\spr_o[9:0] 10'0000001111 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0010000001 + assign { } { } + assign $1\spr_o[9:0] 10'0000010000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0010000010 + assign { } { } + assign $1\spr_o[9:0] 10'0000010001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0010000011 + assign { } { } + assign $1\spr_o[9:0] 10'0000010010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0010001000 + assign { } { } + assign $1\spr_o[9:0] 10'0000010011 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0010010000 + assign { } { } + assign $1\spr_o[9:0] 10'0000010100 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0010011000 + assign { } { } + assign $1\spr_o[9:0] 10'0000010101 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0010011001 + assign { } { } + assign $1\spr_o[9:0] 10'0000010110 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0010011101 + assign { } { } + assign $1\spr_o[9:0] 10'0000010111 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0010011110 + assign { } { } + assign $1\spr_o[9:0] 10'0000011000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0010011111 + assign { } { } + assign $1\spr_o[9:0] 10'0000011001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0010110000 + assign { } { } + assign $1\spr_o[9:0] 10'0000011010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0010110100 + assign { } { } + assign $1\spr_o[9:0] 10'0000011011 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0010111010 + assign { } { } + assign $1\spr_o[9:0] 10'0000011100 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0010111011 + assign { } { } + assign $1\spr_o[9:0] 10'0000011101 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0010111100 + assign { } { } + assign $1\spr_o[9:0] 10'0000011110 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0010111110 + assign { } { } + assign $1\spr_o[9:0] 10'0000011111 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0100000000 + assign { } { } + assign $1\spr_o[9:0] 10'0000100000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0100000011 + assign { } { } + assign $1\spr_o[9:0] 10'0000100001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0100001101 + assign { } { } + assign $1\spr_o[9:0] 10'0000100011 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0100010000 + assign { } { } + assign $1\spr_o[9:0] 10'0000100100 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0100010001 + assign { } { } + assign $1\spr_o[9:0] 10'0000100101 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0100010010 + assign { } { } + assign $1\spr_o[9:0] 10'0000100110 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0100010011 + assign { } { } + assign $1\spr_o[9:0] 10'0000100111 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0100011011 + assign { } { } + assign $1\spr_o[9:0] 10'0000101000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0100011100 + assign { } { } + assign $1\spr_o[9:0] 10'0000101001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0100011101 + assign { } { } + assign $1\spr_o[9:0] 10'0000101010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0100011110 + assign { } { } + assign $1\spr_o[9:0] 10'0000101011 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0100011111 + assign { } { } + assign $1\spr_o[9:0] 10'0000101100 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0100110000 + assign { } { } + assign $1\spr_o[9:0] 10'0000101101 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0100110001 + assign { } { } + assign $1\spr_o[9:0] 10'0000101110 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0100110010 + assign { } { } + assign $1\spr_o[9:0] 10'0000101111 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0100110011 + assign { } { } + assign $1\spr_o[9:0] 10'0000110000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0100110100 + assign { } { } + assign $1\spr_o[9:0] 10'0000110001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0100110101 + assign { } { } + assign $1\spr_o[9:0] 10'0000110010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0100110110 + assign { } { } + assign $1\spr_o[9:0] 10'0000110011 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0100111001 + assign { } { } + assign $1\spr_o[9:0] 10'0000110100 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0100111010 + assign { } { } + assign $1\spr_o[9:0] 10'0000110101 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0100111011 + assign { } { } + assign $1\spr_o[9:0] 10'0000110110 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0100111110 + assign { } { } + assign $1\spr_o[9:0] 10'0000110111 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0100111111 + assign { } { } + assign $1\spr_o[9:0] 10'0000111000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0101010000 + assign { } { } + assign $1\spr_o[9:0] 10'0000111001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0101010001 + assign { } { } + assign $1\spr_o[9:0] 10'0000111010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0101010010 + assign { } { } + assign $1\spr_o[9:0] 10'0000111011 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0101010011 + assign { } { } + assign $1\spr_o[9:0] 10'0000111100 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0101011101 + assign { } { } + assign $1\spr_o[9:0] 10'0000111101 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0110111110 + assign { } { } + assign $1\spr_o[9:0] 10'0000111110 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0111010000 + assign { } { } + assign $1\spr_o[9:0] 10'0000111111 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'1100000000 + assign { } { } + assign $1\spr_o[9:0] 10'0001000000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'1100000001 + assign { } { } + assign $1\spr_o[9:0] 10'0001000001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'1100000010 + assign { } { } + assign $1\spr_o[9:0] 10'0001000010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'1100000011 + assign { } { } + assign $1\spr_o[9:0] 10'0001000011 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'1100000100 + assign { } { } + assign $1\spr_o[9:0] 10'0001000100 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'1100000101 + assign { } { } + assign $1\spr_o[9:0] 10'0001000101 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'1100000110 + assign { } { } + assign $1\spr_o[9:0] 10'0001000110 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'1100000111 + assign { } { } + assign $1\spr_o[9:0] 10'0001000111 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'1100001000 + assign { } { } + assign $1\spr_o[9:0] 10'0001001000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'1100001011 + assign { } { } + assign $1\spr_o[9:0] 10'0001001001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'1100001100 + assign { } { } + assign $1\spr_o[9:0] 10'0001001010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'1100001101 + assign { } { } + assign $1\spr_o[9:0] 10'0001001011 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'1100001110 + assign { } { } + assign $1\spr_o[9:0] 10'0001001100 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'1100010000 + assign { } { } + assign $1\spr_o[9:0] 10'0001001101 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'1100010001 + assign { } { } + assign $1\spr_o[9:0] 10'0001001110 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'1100010010 + assign { } { } + assign $1\spr_o[9:0] 10'0001001111 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'1100010011 + assign { } { } + assign $1\spr_o[9:0] 10'0001010000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'1100010100 + assign { } { } + assign $1\spr_o[9:0] 10'0001010001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'1100010101 + assign { } { } + assign $1\spr_o[9:0] 10'0001010010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'1100010110 + assign { } { } + assign $1\spr_o[9:0] 10'0001010011 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'1100010111 + assign { } { } + assign $1\spr_o[9:0] 10'0001010100 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'1100011000 + assign { } { } + assign $1\spr_o[9:0] 10'0001010101 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'1100011011 + assign { } { } + assign $1\spr_o[9:0] 10'0001010110 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'1100011100 + assign { } { } + assign $1\spr_o[9:0] 10'0001010111 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'1100011101 + assign { } { } + assign $1\spr_o[9:0] 10'0001011000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'1100011110 + assign { } { } + assign $1\spr_o[9:0] 10'0001011001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'1100100000 + assign { } { } + assign $1\spr_o[9:0] 10'0001011010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'1100100001 + assign { } { } + assign $1\spr_o[9:0] 10'0001011011 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'1100100010 + assign { } { } + assign $1\spr_o[9:0] 10'0001011100 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'1100100011 + assign { } { } + assign $1\spr_o[9:0] 10'0001011101 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'1100100100 + assign { } { } + assign $1\spr_o[9:0] 10'0001011110 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'1100100101 + assign { } { } + assign $1\spr_o[9:0] 10'0001011111 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'1100100110 + assign { } { } + assign $1\spr_o[9:0] 10'0001100000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'1100101000 + assign { } { } + assign $1\spr_o[9:0] 10'0001100001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'1100101001 + assign { } { } + assign $1\spr_o[9:0] 10'0001100010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'1100101010 + assign { } { } + assign $1\spr_o[9:0] 10'0001100011 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'1100101011 + assign { } { } + assign $1\spr_o[9:0] 10'0001100100 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'1100110000 + assign { } { } + assign $1\spr_o[9:0] 10'0001100110 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'1100110111 + assign { } { } + assign $1\spr_o[9:0] 10'0001100111 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'1101010000 + assign { } { } + assign $1\spr_o[9:0] 10'0001101000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'1101010001 + assign { } { } + assign $1\spr_o[9:0] 10'0001101001 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'1101010111 + assign { } { } + assign $1\spr_o[9:0] 10'0001101010 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'1110000000 + assign { } { } + assign $1\spr_o[9:0] 10'0001101011 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'1110000010 + assign { } { } + assign $1\spr_o[9:0] 10'0001101100 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'1111111111 + assign { } { } + assign $1\spr_o[9:0] 10'0001101101 + case + assign $1\spr_o[9:0] 10'0000000000 + end + sync always + update \spr_o $0\spr_o[9:0] + end + attribute \src "issuer_ls180.v:174634.3-174946.6" + process $proc$issuer_ls180.v:174634$12232 + assign { } { } + assign { } { } + assign $0\spr_o_ok[0:0] $1\spr_o_ok[0:0] + attribute \src "issuer_ls180.v:174635.5-174635.29" + switch \initial + attribute \src "issuer_ls180.v:174635.9-174635.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:65" + switch \spr_i + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0000000011 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0000001101 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0000010001 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0000010010 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0000010011 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0000011100 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0000011101 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0000110000 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0000111101 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0010000000 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0010000001 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0010000010 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0010000011 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0010001000 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0010010000 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0010011000 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0010011001 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0010011101 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0010011110 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0010011111 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0010110000 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0010110100 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0010111010 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0010111011 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0010111100 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0010111110 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0100000000 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0100000011 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0100001101 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0100010000 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0100010001 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0100010010 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0100010011 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0100011011 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0100011100 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0100011101 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0100011110 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0100011111 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0100110000 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0100110001 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0100110010 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0100110011 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0100110100 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0100110101 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0100110110 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0100111001 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0100111010 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0100111011 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0100111110 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0100111111 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0101010000 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0101010001 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0101010010 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0101010011 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0101011101 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0110111110 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'0111010000 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'1100000000 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'1100000001 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'1100000010 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'1100000011 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'1100000100 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'1100000101 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'1100000110 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'1100000111 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'1100001000 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'1100001011 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'1100001100 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'1100001101 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'1100001110 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'1100010000 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'1100010001 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'1100010010 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'1100010011 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'1100010100 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'1100010101 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'1100010110 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'1100010111 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'1100011000 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'1100011011 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'1100011100 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'1100011101 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'1100011110 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'1100100000 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'1100100001 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'1100100010 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'1100100011 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'1100100100 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'1100100101 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'1100100110 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'1100101000 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'1100101001 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'1100101010 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'1100101011 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'1100110000 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'1100110111 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'1101010000 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'1101010001 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'1101010111 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'1110000000 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'1110000010 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 10'1111111111 + assign { } { } + assign $1\spr_o_ok[0:0] 1'1 + case + assign $1\spr_o_ok[0:0] 1'0 + end + sync always + update \spr_o_ok $0\spr_o_ok[0:0] + end +end +attribute \src "issuer_ls180.v:174951.1-175009.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.fus.alu0.src_l" +attribute \generator "nMigen" +module \src_l + attribute \src "issuer_ls180.v:174952.7-174952.20" + wire $0\initial[0:0] + attribute \src "issuer_ls180.v:174997.3-175005.6" + wire width 4 $0\q_int$next[3:0]$12244 + attribute \src "issuer_ls180.v:174995.3-174996.27" + wire width 4 $0\q_int[3:0] + attribute \src "issuer_ls180.v:174997.3-175005.6" + wire width 4 $1\q_int$next[3:0]$12245 + attribute \src "issuer_ls180.v:174974.13-174974.25" + wire width 4 $1\q_int[3:0] + attribute \src "issuer_ls180.v:174987.17-174987.96" + wire width 4 $and$issuer_ls180.v:174987$12234_Y + attribute \src "issuer_ls180.v:174992.17-174992.96" + wire width 4 $and$issuer_ls180.v:174992$12239_Y + attribute \src "issuer_ls180.v:174989.18-174989.93" + wire width 4 $not$issuer_ls180.v:174989$12236_Y + attribute \src "issuer_ls180.v:174991.17-174991.92" + wire width 4 $not$issuer_ls180.v:174991$12238_Y + attribute \src "issuer_ls180.v:174994.17-174994.92" + wire width 4 $not$issuer_ls180.v:174994$12241_Y + attribute \src "issuer_ls180.v:174988.18-174988.98" + wire width 4 $or$issuer_ls180.v:174988$12235_Y + attribute \src "issuer_ls180.v:174990.18-174990.99" + wire width 4 $or$issuer_ls180.v:174990$12237_Y + attribute \src "issuer_ls180.v:174993.17-174993.97" + wire width 4 $or$issuer_ls180.v:174993$12240_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire width 4 \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire width 4 \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire width 4 \$13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + wire width 4 \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire width 4 \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire width 4 \$5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire width 4 \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire width 4 \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" + wire input 5 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" + wire input 1 \coresync_rst + attribute \src "issuer_ls180.v:174952.7-174952.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire width 4 \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire width 4 \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire width 4 output 4 \q_src + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" + wire width 4 \qlq_src + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + wire width 4 \qn_src + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire width 4 input 3 \r_src + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire width 4 input 2 \s_src + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $and $and$issuer_ls180.v:174987$12234 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \q_int + connect \B \$7 + connect \Y $and$issuer_ls180.v:174987$12234_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $and $and$issuer_ls180.v:174992$12239 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \q_int + connect \B \$1 + connect \Y $and$issuer_ls180.v:174992$12239_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + cell $not $not$issuer_ls180.v:174989$12236 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \q_src + connect \Y $not$issuer_ls180.v:174989$12236_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $not $not$issuer_ls180.v:174991$12238 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \r_src + connect \Y $not$issuer_ls180.v:174991$12238_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $not $not$issuer_ls180.v:174994$12241 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \r_src + connect \Y $not$issuer_ls180.v:174994$12241_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $or $or$issuer_ls180.v:174988$12235 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \$9 + connect \B \s_src + connect \Y $or$issuer_ls180.v:174988$12235_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + cell $or $or$issuer_ls180.v:174990$12237 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \q_src + connect \B \q_int + connect \Y $or$issuer_ls180.v:174990$12237_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $or $or$issuer_ls180.v:174993$12240 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \$3 + connect \B \s_src + connect \Y $or$issuer_ls180.v:174993$12240_Y + end + attribute \src "issuer_ls180.v:174952.7-174952.20" + process $proc$issuer_ls180.v:174952$12246 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "issuer_ls180.v:174974.13-174974.25" + process $proc$issuer_ls180.v:174974$12247 + assign { } { } + assign $1\q_int[3:0] 4'0000 + sync always + sync init + update \q_int $1\q_int[3:0] + end + attribute \src "issuer_ls180.v:174995.3-174996.27" + process $proc$issuer_ls180.v:174995$12242 + assign { } { } + assign $0\q_int[3:0] \q_int$next + sync posedge \coresync_clk + update \q_int $0\q_int[3:0] + end + attribute \src "issuer_ls180.v:174997.3-175005.6" + process $proc$issuer_ls180.v:174997$12243 + assign { } { } + assign { } { } + assign $0\q_int$next[3:0]$12244 $1\q_int$next[3:0]$12245 + attribute \src "issuer_ls180.v:174998.5-174998.29" + switch \initial + attribute \src "issuer_ls180.v:174998.9-174998.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\q_int$next[3:0]$12245 4'0000 + case + assign $1\q_int$next[3:0]$12245 \$5 + end + sync always + update \q_int$next $0\q_int$next[3:0]$12244 + end + connect \$9 $and$issuer_ls180.v:174987$12234_Y + connect \$11 $or$issuer_ls180.v:174988$12235_Y + connect \$13 $not$issuer_ls180.v:174989$12236_Y + connect \$15 $or$issuer_ls180.v:174990$12237_Y + connect \$1 $not$issuer_ls180.v:174991$12238_Y + connect \$3 $and$issuer_ls180.v:174992$12239_Y + connect \$5 $or$issuer_ls180.v:174993$12240_Y + connect \$7 $not$issuer_ls180.v:174994$12241_Y + connect \qlq_src \$15 + connect \qn_src \$13 + connect \q_src \$11 +end +attribute \src "issuer_ls180.v:175013.1-175071.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.fus.cr0.src_l" +attribute \generator "nMigen" +module \src_l$10 + attribute \src "issuer_ls180.v:175014.7-175014.20" + wire $0\initial[0:0] + attribute \src "issuer_ls180.v:175059.3-175067.6" + wire width 6 $0\q_int$next[5:0]$12258 + attribute \src "issuer_ls180.v:175057.3-175058.27" + wire width 6 $0\q_int[5:0] + attribute \src "issuer_ls180.v:175059.3-175067.6" + wire width 6 $1\q_int$next[5:0]$12259 + attribute \src "issuer_ls180.v:175036.13-175036.26" + wire width 6 $1\q_int[5:0] + attribute \src "issuer_ls180.v:175049.17-175049.96" + wire width 6 $and$issuer_ls180.v:175049$12248_Y + attribute \src "issuer_ls180.v:175054.17-175054.96" + wire width 6 $and$issuer_ls180.v:175054$12253_Y + attribute \src "issuer_ls180.v:175051.18-175051.93" + wire width 6 $not$issuer_ls180.v:175051$12250_Y + attribute \src "issuer_ls180.v:175053.17-175053.92" + wire width 6 $not$issuer_ls180.v:175053$12252_Y + attribute \src "issuer_ls180.v:175056.17-175056.92" + wire width 6 $not$issuer_ls180.v:175056$12255_Y + attribute \src "issuer_ls180.v:175050.18-175050.98" + wire width 6 $or$issuer_ls180.v:175050$12249_Y + attribute \src "issuer_ls180.v:175052.18-175052.99" + wire width 6 $or$issuer_ls180.v:175052$12251_Y + attribute \src "issuer_ls180.v:175055.17-175055.97" + wire width 6 $or$issuer_ls180.v:175055$12254_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire width 6 \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire width 6 \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire width 6 \$13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + wire width 6 \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire width 6 \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire width 6 \$5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire width 6 \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire width 6 \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" + wire input 5 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" + wire input 1 \coresync_rst + attribute \src "issuer_ls180.v:175014.7-175014.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire width 6 \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire width 6 \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire width 6 output 4 \q_src + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" + wire width 6 \qlq_src + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + wire width 6 \qn_src + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire width 6 input 3 \r_src + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire width 6 input 2 \s_src + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $and $and$issuer_ls180.v:175049$12248 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 6 + connect \A \q_int + connect \B \$7 + connect \Y $and$issuer_ls180.v:175049$12248_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $and $and$issuer_ls180.v:175054$12253 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 6 + connect \A \q_int + connect \B \$1 + connect \Y $and$issuer_ls180.v:175054$12253_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + cell $not $not$issuer_ls180.v:175051$12250 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \Y_WIDTH 6 + connect \A \q_src + connect \Y $not$issuer_ls180.v:175051$12250_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $not $not$issuer_ls180.v:175053$12252 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \Y_WIDTH 6 + connect \A \r_src + connect \Y $not$issuer_ls180.v:175053$12252_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $not $not$issuer_ls180.v:175056$12255 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \Y_WIDTH 6 + connect \A \r_src + connect \Y $not$issuer_ls180.v:175056$12255_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $or $or$issuer_ls180.v:175050$12249 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 6 + connect \A \$9 + connect \B \s_src + connect \Y $or$issuer_ls180.v:175050$12249_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + cell $or $or$issuer_ls180.v:175052$12251 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 6 + connect \A \q_src + connect \B \q_int + connect \Y $or$issuer_ls180.v:175052$12251_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $or $or$issuer_ls180.v:175055$12254 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 6 + connect \A \$3 + connect \B \s_src + connect \Y $or$issuer_ls180.v:175055$12254_Y + end + attribute \src "issuer_ls180.v:175014.7-175014.20" + process $proc$issuer_ls180.v:175014$12260 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "issuer_ls180.v:175036.13-175036.26" + process $proc$issuer_ls180.v:175036$12261 + assign { } { } + assign $1\q_int[5:0] 6'000000 + sync always + sync init + update \q_int $1\q_int[5:0] + end + attribute \src "issuer_ls180.v:175057.3-175058.27" + process $proc$issuer_ls180.v:175057$12256 + assign { } { } + assign $0\q_int[5:0] \q_int$next + sync posedge \coresync_clk + update \q_int $0\q_int[5:0] + end + attribute \src "issuer_ls180.v:175059.3-175067.6" + process $proc$issuer_ls180.v:175059$12257 + assign { } { } + assign { } { } + assign $0\q_int$next[5:0]$12258 $1\q_int$next[5:0]$12259 + attribute \src "issuer_ls180.v:175060.5-175060.29" + switch \initial + attribute \src "issuer_ls180.v:175060.9-175060.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\q_int$next[5:0]$12259 6'000000 + case + assign $1\q_int$next[5:0]$12259 \$5 + end + sync always + update \q_int$next $0\q_int$next[5:0]$12258 + end + connect \$9 $and$issuer_ls180.v:175049$12248_Y + connect \$11 $or$issuer_ls180.v:175050$12249_Y + connect \$13 $not$issuer_ls180.v:175051$12250_Y + connect \$15 $or$issuer_ls180.v:175052$12251_Y + connect \$1 $not$issuer_ls180.v:175053$12252_Y + connect \$3 $and$issuer_ls180.v:175054$12253_Y + connect \$5 $or$issuer_ls180.v:175055$12254_Y + connect \$7 $not$issuer_ls180.v:175056$12255_Y + connect \qlq_src \$15 + connect \qn_src \$13 + connect \q_src \$11 +end +attribute \src "issuer_ls180.v:175075.1-175133.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.fus.shiftrot0.src_l" +attribute \generator "nMigen" +module \src_l$116 + attribute \src "issuer_ls180.v:175076.7-175076.20" + wire $0\initial[0:0] + attribute \src "issuer_ls180.v:175121.3-175129.6" + wire width 5 $0\q_int$next[4:0]$12272 + attribute \src "issuer_ls180.v:175119.3-175120.27" + wire width 5 $0\q_int[4:0] + attribute \src "issuer_ls180.v:175121.3-175129.6" + wire width 5 $1\q_int$next[4:0]$12273 + attribute \src "issuer_ls180.v:175098.13-175098.26" + wire width 5 $1\q_int[4:0] + attribute \src "issuer_ls180.v:175111.17-175111.96" + wire width 5 $and$issuer_ls180.v:175111$12262_Y + attribute \src "issuer_ls180.v:175116.17-175116.96" + wire width 5 $and$issuer_ls180.v:175116$12267_Y + attribute \src "issuer_ls180.v:175113.18-175113.93" + wire width 5 $not$issuer_ls180.v:175113$12264_Y + attribute \src "issuer_ls180.v:175115.17-175115.92" + wire width 5 $not$issuer_ls180.v:175115$12266_Y + attribute \src "issuer_ls180.v:175118.17-175118.92" + wire width 5 $not$issuer_ls180.v:175118$12269_Y + attribute \src "issuer_ls180.v:175112.18-175112.98" + wire width 5 $or$issuer_ls180.v:175112$12263_Y + attribute \src "issuer_ls180.v:175114.18-175114.99" + wire width 5 $or$issuer_ls180.v:175114$12265_Y + attribute \src "issuer_ls180.v:175117.17-175117.97" + wire width 5 $or$issuer_ls180.v:175117$12268_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire width 5 \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire width 5 \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire width 5 \$13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + wire width 5 \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire width 5 \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire width 5 \$5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire width 5 \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire width 5 \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" + wire input 5 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" + wire input 1 \coresync_rst + attribute \src "issuer_ls180.v:175076.7-175076.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire width 5 \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire width 5 \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire width 5 output 4 \q_src + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" + wire width 5 \qlq_src + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + wire width 5 \qn_src + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire width 5 input 3 \r_src + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire width 5 input 2 \s_src + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $and $and$issuer_ls180.v:175111$12262 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 5 + connect \A \q_int + connect \B \$7 + connect \Y $and$issuer_ls180.v:175111$12262_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $and $and$issuer_ls180.v:175116$12267 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 5 + connect \A \q_int + connect \B \$1 + connect \Y $and$issuer_ls180.v:175116$12267_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + cell $not $not$issuer_ls180.v:175113$12264 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \Y_WIDTH 5 + connect \A \q_src + connect \Y $not$issuer_ls180.v:175113$12264_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $not $not$issuer_ls180.v:175115$12266 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \Y_WIDTH 5 + connect \A \r_src + connect \Y $not$issuer_ls180.v:175115$12266_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $not $not$issuer_ls180.v:175118$12269 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \Y_WIDTH 5 + connect \A \r_src + connect \Y $not$issuer_ls180.v:175118$12269_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $or $or$issuer_ls180.v:175112$12263 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 5 + connect \A \$9 + connect \B \s_src + connect \Y $or$issuer_ls180.v:175112$12263_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + cell $or $or$issuer_ls180.v:175114$12265 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 5 + connect \A \q_src + connect \B \q_int + connect \Y $or$issuer_ls180.v:175114$12265_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $or $or$issuer_ls180.v:175117$12268 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 5 + connect \A \$3 + connect \B \s_src + connect \Y $or$issuer_ls180.v:175117$12268_Y + end + attribute \src "issuer_ls180.v:175076.7-175076.20" + process $proc$issuer_ls180.v:175076$12274 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "issuer_ls180.v:175098.13-175098.26" + process $proc$issuer_ls180.v:175098$12275 + assign { } { } + assign $1\q_int[4:0] 5'00000 + sync always + sync init + update \q_int $1\q_int[4:0] + end + attribute \src "issuer_ls180.v:175119.3-175120.27" + process $proc$issuer_ls180.v:175119$12270 + assign { } { } + assign $0\q_int[4:0] \q_int$next + sync posedge \coresync_clk + update \q_int $0\q_int[4:0] + end + attribute \src "issuer_ls180.v:175121.3-175129.6" + process $proc$issuer_ls180.v:175121$12271 + assign { } { } + assign { } { } + assign $0\q_int$next[4:0]$12272 $1\q_int$next[4:0]$12273 + attribute \src "issuer_ls180.v:175122.5-175122.29" + switch \initial + attribute \src "issuer_ls180.v:175122.9-175122.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\q_int$next[4:0]$12273 5'00000 + case + assign $1\q_int$next[4:0]$12273 \$5 + end + sync always + update \q_int$next $0\q_int$next[4:0]$12272 + end + connect \$9 $and$issuer_ls180.v:175111$12262_Y + connect \$11 $or$issuer_ls180.v:175112$12263_Y + connect \$13 $not$issuer_ls180.v:175113$12264_Y + connect \$15 $or$issuer_ls180.v:175114$12265_Y + connect \$1 $not$issuer_ls180.v:175115$12266_Y + connect \$3 $and$issuer_ls180.v:175116$12267_Y + connect \$5 $or$issuer_ls180.v:175117$12268_Y + connect \$7 $not$issuer_ls180.v:175118$12269_Y + connect \qlq_src \$15 + connect \qn_src \$13 + connect \q_src \$11 +end +attribute \src "issuer_ls180.v:175137.1-175195.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.fus.ldst0.src_l" +attribute \generator "nMigen" +module \src_l$124 + attribute \src "issuer_ls180.v:175138.7-175138.20" + wire $0\initial[0:0] + attribute \src "issuer_ls180.v:175183.3-175191.6" + wire width 3 $0\q_int$next[2:0]$12286 + attribute \src "issuer_ls180.v:175181.3-175182.27" + wire width 3 $0\q_int[2:0] + attribute \src "issuer_ls180.v:175183.3-175191.6" + wire width 3 $1\q_int$next[2:0]$12287 + attribute \src "issuer_ls180.v:175160.13-175160.25" + wire width 3 $1\q_int[2:0] + attribute \src "issuer_ls180.v:175173.17-175173.96" + wire width 3 $and$issuer_ls180.v:175173$12276_Y + attribute \src "issuer_ls180.v:175178.17-175178.96" + wire width 3 $and$issuer_ls180.v:175178$12281_Y + attribute \src "issuer_ls180.v:175175.18-175175.93" + wire width 3 $not$issuer_ls180.v:175175$12278_Y + attribute \src "issuer_ls180.v:175177.17-175177.92" + wire width 3 $not$issuer_ls180.v:175177$12280_Y + attribute \src "issuer_ls180.v:175180.17-175180.92" + wire width 3 $not$issuer_ls180.v:175180$12283_Y + attribute \src "issuer_ls180.v:175174.18-175174.98" + wire width 3 $or$issuer_ls180.v:175174$12277_Y + attribute \src "issuer_ls180.v:175176.18-175176.99" + wire width 3 $or$issuer_ls180.v:175176$12279_Y + attribute \src "issuer_ls180.v:175179.17-175179.97" + wire width 3 $or$issuer_ls180.v:175179$12282_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire width 3 \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire width 3 \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire width 3 \$13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + wire width 3 \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire width 3 \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire width 3 \$5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire width 3 \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire width 3 \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" + wire input 5 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" + wire input 1 \coresync_rst + attribute \src "issuer_ls180.v:175138.7-175138.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire width 3 \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire width 3 \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire width 3 output 4 \q_src + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" + wire width 3 \qlq_src + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + wire width 3 \qn_src + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire width 3 input 3 \r_src + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire width 3 input 2 \s_src + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $and $and$issuer_ls180.v:175173$12276 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \q_int + connect \B \$7 + connect \Y $and$issuer_ls180.v:175173$12276_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $and $and$issuer_ls180.v:175178$12281 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \q_int + connect \B \$1 + connect \Y $and$issuer_ls180.v:175178$12281_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + cell $not $not$issuer_ls180.v:175175$12278 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \q_src + connect \Y $not$issuer_ls180.v:175175$12278_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $not $not$issuer_ls180.v:175177$12280 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \r_src + connect \Y $not$issuer_ls180.v:175177$12280_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $not $not$issuer_ls180.v:175180$12283 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \r_src + connect \Y $not$issuer_ls180.v:175180$12283_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $or $or$issuer_ls180.v:175174$12277 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \$9 + connect \B \s_src + connect \Y $or$issuer_ls180.v:175174$12277_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + cell $or $or$issuer_ls180.v:175176$12279 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \q_src + connect \B \q_int + connect \Y $or$issuer_ls180.v:175176$12279_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $or $or$issuer_ls180.v:175179$12282 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \$3 + connect \B \s_src + connect \Y $or$issuer_ls180.v:175179$12282_Y + end + attribute \src "issuer_ls180.v:175138.7-175138.20" + process $proc$issuer_ls180.v:175138$12288 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "issuer_ls180.v:175160.13-175160.25" + process $proc$issuer_ls180.v:175160$12289 + assign { } { } + assign $1\q_int[2:0] 3'000 + sync always + sync init + update \q_int $1\q_int[2:0] + end + attribute \src "issuer_ls180.v:175181.3-175182.27" + process $proc$issuer_ls180.v:175181$12284 + assign { } { } + assign $0\q_int[2:0] \q_int$next + sync posedge \coresync_clk + update \q_int $0\q_int[2:0] + end + attribute \src "issuer_ls180.v:175183.3-175191.6" + process $proc$issuer_ls180.v:175183$12285 + assign { } { } + assign { } { } + assign $0\q_int$next[2:0]$12286 $1\q_int$next[2:0]$12287 + attribute \src "issuer_ls180.v:175184.5-175184.29" + switch \initial + attribute \src "issuer_ls180.v:175184.9-175184.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\q_int$next[2:0]$12287 3'000 + case + assign $1\q_int$next[2:0]$12287 \$5 + end + sync always + update \q_int$next $0\q_int$next[2:0]$12286 + end + connect \$9 $and$issuer_ls180.v:175173$12276_Y + connect \$11 $or$issuer_ls180.v:175174$12277_Y + connect \$13 $not$issuer_ls180.v:175175$12278_Y + connect \$15 $or$issuer_ls180.v:175176$12279_Y + connect \$1 $not$issuer_ls180.v:175177$12280_Y + connect \$3 $and$issuer_ls180.v:175178$12281_Y + connect \$5 $or$issuer_ls180.v:175179$12282_Y + connect \$7 $not$issuer_ls180.v:175180$12283_Y + connect \qlq_src \$15 + connect \qn_src \$13 + connect \q_src \$11 +end +attribute \src "issuer_ls180.v:175199.1-175257.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.fus.branch0.src_l" +attribute \generator "nMigen" +module \src_l$23 + attribute \src "issuer_ls180.v:175200.7-175200.20" + wire $0\initial[0:0] + attribute \src "issuer_ls180.v:175245.3-175253.6" + wire width 3 $0\q_int$next[2:0]$12300 + attribute \src "issuer_ls180.v:175243.3-175244.27" + wire width 3 $0\q_int[2:0] + attribute \src "issuer_ls180.v:175245.3-175253.6" + wire width 3 $1\q_int$next[2:0]$12301 + attribute \src "issuer_ls180.v:175222.13-175222.25" + wire width 3 $1\q_int[2:0] + attribute \src "issuer_ls180.v:175235.17-175235.96" + wire width 3 $and$issuer_ls180.v:175235$12290_Y + attribute \src "issuer_ls180.v:175240.17-175240.96" + wire width 3 $and$issuer_ls180.v:175240$12295_Y + attribute \src "issuer_ls180.v:175237.18-175237.93" + wire width 3 $not$issuer_ls180.v:175237$12292_Y + attribute \src "issuer_ls180.v:175239.17-175239.92" + wire width 3 $not$issuer_ls180.v:175239$12294_Y + attribute \src "issuer_ls180.v:175242.17-175242.92" + wire width 3 $not$issuer_ls180.v:175242$12297_Y + attribute \src "issuer_ls180.v:175236.18-175236.98" + wire width 3 $or$issuer_ls180.v:175236$12291_Y + attribute \src "issuer_ls180.v:175238.18-175238.99" + wire width 3 $or$issuer_ls180.v:175238$12293_Y + attribute \src "issuer_ls180.v:175241.17-175241.97" + wire width 3 $or$issuer_ls180.v:175241$12296_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire width 3 \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire width 3 \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire width 3 \$13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + wire width 3 \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire width 3 \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire width 3 \$5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire width 3 \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire width 3 \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" + wire input 5 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" + wire input 1 \coresync_rst + attribute \src "issuer_ls180.v:175200.7-175200.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire width 3 \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire width 3 \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire width 3 output 4 \q_src + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" + wire width 3 \qlq_src + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + wire width 3 \qn_src + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire width 3 input 3 \r_src + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire width 3 input 2 \s_src + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $and $and$issuer_ls180.v:175235$12290 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \q_int + connect \B \$7 + connect \Y $and$issuer_ls180.v:175235$12290_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $and $and$issuer_ls180.v:175240$12295 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \q_int + connect \B \$1 + connect \Y $and$issuer_ls180.v:175240$12295_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + cell $not $not$issuer_ls180.v:175237$12292 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \q_src + connect \Y $not$issuer_ls180.v:175237$12292_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $not $not$issuer_ls180.v:175239$12294 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \r_src + connect \Y $not$issuer_ls180.v:175239$12294_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $not $not$issuer_ls180.v:175242$12297 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \r_src + connect \Y $not$issuer_ls180.v:175242$12297_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $or $or$issuer_ls180.v:175236$12291 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \$9 + connect \B \s_src + connect \Y $or$issuer_ls180.v:175236$12291_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + cell $or $or$issuer_ls180.v:175238$12293 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \q_src + connect \B \q_int + connect \Y $or$issuer_ls180.v:175238$12293_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $or $or$issuer_ls180.v:175241$12296 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \$3 + connect \B \s_src + connect \Y $or$issuer_ls180.v:175241$12296_Y + end + attribute \src "issuer_ls180.v:175200.7-175200.20" + process $proc$issuer_ls180.v:175200$12302 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "issuer_ls180.v:175222.13-175222.25" + process $proc$issuer_ls180.v:175222$12303 + assign { } { } + assign $1\q_int[2:0] 3'000 + sync always + sync init + update \q_int $1\q_int[2:0] + end + attribute \src "issuer_ls180.v:175243.3-175244.27" + process $proc$issuer_ls180.v:175243$12298 + assign { } { } + assign $0\q_int[2:0] \q_int$next + sync posedge \coresync_clk + update \q_int $0\q_int[2:0] + end + attribute \src "issuer_ls180.v:175245.3-175253.6" + process $proc$issuer_ls180.v:175245$12299 + assign { } { } + assign { } { } + assign $0\q_int$next[2:0]$12300 $1\q_int$next[2:0]$12301 + attribute \src "issuer_ls180.v:175246.5-175246.29" + switch \initial + attribute \src "issuer_ls180.v:175246.9-175246.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\q_int$next[2:0]$12301 3'000 + case + assign $1\q_int$next[2:0]$12301 \$5 + end + sync always + update \q_int$next $0\q_int$next[2:0]$12300 + end + connect \$9 $and$issuer_ls180.v:175235$12290_Y + connect \$11 $or$issuer_ls180.v:175236$12291_Y + connect \$13 $not$issuer_ls180.v:175237$12292_Y + connect \$15 $or$issuer_ls180.v:175238$12293_Y + connect \$1 $not$issuer_ls180.v:175239$12294_Y + connect \$3 $and$issuer_ls180.v:175240$12295_Y + connect \$5 $or$issuer_ls180.v:175241$12296_Y + connect \$7 $not$issuer_ls180.v:175242$12297_Y + connect \qlq_src \$15 + connect \qn_src \$13 + connect \q_src \$11 +end +attribute \src "issuer_ls180.v:175261.1-175319.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.fus.trap0.src_l" +attribute \generator "nMigen" +module \src_l$36 + attribute \src "issuer_ls180.v:175262.7-175262.20" + wire $0\initial[0:0] + attribute \src "issuer_ls180.v:175307.3-175315.6" + wire width 4 $0\q_int$next[3:0]$12314 + attribute \src "issuer_ls180.v:175305.3-175306.27" + wire width 4 $0\q_int[3:0] + attribute \src "issuer_ls180.v:175307.3-175315.6" + wire width 4 $1\q_int$next[3:0]$12315 + attribute \src "issuer_ls180.v:175284.13-175284.25" + wire width 4 $1\q_int[3:0] + attribute \src "issuer_ls180.v:175297.17-175297.96" + wire width 4 $and$issuer_ls180.v:175297$12304_Y + attribute \src "issuer_ls180.v:175302.17-175302.96" + wire width 4 $and$issuer_ls180.v:175302$12309_Y + attribute \src "issuer_ls180.v:175299.18-175299.93" + wire width 4 $not$issuer_ls180.v:175299$12306_Y + attribute \src "issuer_ls180.v:175301.17-175301.92" + wire width 4 $not$issuer_ls180.v:175301$12308_Y + attribute \src "issuer_ls180.v:175304.17-175304.92" + wire width 4 $not$issuer_ls180.v:175304$12311_Y + attribute \src "issuer_ls180.v:175298.18-175298.98" + wire width 4 $or$issuer_ls180.v:175298$12305_Y + attribute \src "issuer_ls180.v:175300.18-175300.99" + wire width 4 $or$issuer_ls180.v:175300$12307_Y + attribute \src "issuer_ls180.v:175303.17-175303.97" + wire width 4 $or$issuer_ls180.v:175303$12310_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire width 4 \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire width 4 \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire width 4 \$13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + wire width 4 \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire width 4 \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire width 4 \$5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire width 4 \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire width 4 \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" + wire input 5 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" + wire input 1 \coresync_rst + attribute \src "issuer_ls180.v:175262.7-175262.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire width 4 \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire width 4 \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire width 4 output 4 \q_src + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" + wire width 4 \qlq_src + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + wire width 4 \qn_src + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire width 4 input 3 \r_src + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire width 4 input 2 \s_src + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $and $and$issuer_ls180.v:175297$12304 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \q_int + connect \B \$7 + connect \Y $and$issuer_ls180.v:175297$12304_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $and $and$issuer_ls180.v:175302$12309 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \q_int + connect \B \$1 + connect \Y $and$issuer_ls180.v:175302$12309_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + cell $not $not$issuer_ls180.v:175299$12306 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \q_src + connect \Y $not$issuer_ls180.v:175299$12306_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $not $not$issuer_ls180.v:175301$12308 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \r_src + connect \Y $not$issuer_ls180.v:175301$12308_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $not $not$issuer_ls180.v:175304$12311 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \r_src + connect \Y $not$issuer_ls180.v:175304$12311_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $or $or$issuer_ls180.v:175298$12305 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \$9 + connect \B \s_src + connect \Y $or$issuer_ls180.v:175298$12305_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + cell $or $or$issuer_ls180.v:175300$12307 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \q_src + connect \B \q_int + connect \Y $or$issuer_ls180.v:175300$12307_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $or $or$issuer_ls180.v:175303$12310 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \$3 + connect \B \s_src + connect \Y $or$issuer_ls180.v:175303$12310_Y + end + attribute \src "issuer_ls180.v:175262.7-175262.20" + process $proc$issuer_ls180.v:175262$12316 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "issuer_ls180.v:175284.13-175284.25" + process $proc$issuer_ls180.v:175284$12317 + assign { } { } + assign $1\q_int[3:0] 4'0000 + sync always + sync init + update \q_int $1\q_int[3:0] + end + attribute \src "issuer_ls180.v:175305.3-175306.27" + process $proc$issuer_ls180.v:175305$12312 + assign { } { } + assign $0\q_int[3:0] \q_int$next + sync posedge \coresync_clk + update \q_int $0\q_int[3:0] + end + attribute \src "issuer_ls180.v:175307.3-175315.6" + process $proc$issuer_ls180.v:175307$12313 + assign { } { } + assign { } { } + assign $0\q_int$next[3:0]$12314 $1\q_int$next[3:0]$12315 + attribute \src "issuer_ls180.v:175308.5-175308.29" + switch \initial + attribute \src "issuer_ls180.v:175308.9-175308.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\q_int$next[3:0]$12315 4'0000 + case + assign $1\q_int$next[3:0]$12315 \$5 + end + sync always + update \q_int$next $0\q_int$next[3:0]$12314 + end + connect \$9 $and$issuer_ls180.v:175297$12304_Y + connect \$11 $or$issuer_ls180.v:175298$12305_Y + connect \$13 $not$issuer_ls180.v:175299$12306_Y + connect \$15 $or$issuer_ls180.v:175300$12307_Y + connect \$1 $not$issuer_ls180.v:175301$12308_Y + connect \$3 $and$issuer_ls180.v:175302$12309_Y + connect \$5 $or$issuer_ls180.v:175303$12310_Y + connect \$7 $not$issuer_ls180.v:175304$12311_Y + connect \qlq_src \$15 + connect \qn_src \$13 + connect \q_src \$11 +end +attribute \src "issuer_ls180.v:175323.1-175381.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.fus.logical0.src_l" +attribute \generator "nMigen" +module \src_l$52 + attribute \src "issuer_ls180.v:175324.7-175324.20" + wire $0\initial[0:0] + attribute \src "issuer_ls180.v:175369.3-175377.6" + wire width 3 $0\q_int$next[2:0]$12328 + attribute \src "issuer_ls180.v:175367.3-175368.27" + wire width 3 $0\q_int[2:0] + attribute \src "issuer_ls180.v:175369.3-175377.6" + wire width 3 $1\q_int$next[2:0]$12329 + attribute \src "issuer_ls180.v:175346.13-175346.25" + wire width 3 $1\q_int[2:0] + attribute \src "issuer_ls180.v:175359.17-175359.96" + wire width 3 $and$issuer_ls180.v:175359$12318_Y + attribute \src "issuer_ls180.v:175364.17-175364.96" + wire width 3 $and$issuer_ls180.v:175364$12323_Y + attribute \src "issuer_ls180.v:175361.18-175361.93" + wire width 3 $not$issuer_ls180.v:175361$12320_Y + attribute \src "issuer_ls180.v:175363.17-175363.92" + wire width 3 $not$issuer_ls180.v:175363$12322_Y + attribute \src "issuer_ls180.v:175366.17-175366.92" + wire width 3 $not$issuer_ls180.v:175366$12325_Y + attribute \src "issuer_ls180.v:175360.18-175360.98" + wire width 3 $or$issuer_ls180.v:175360$12319_Y + attribute \src "issuer_ls180.v:175362.18-175362.99" + wire width 3 $or$issuer_ls180.v:175362$12321_Y + attribute \src "issuer_ls180.v:175365.17-175365.97" + wire width 3 $or$issuer_ls180.v:175365$12324_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire width 3 \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire width 3 \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire width 3 \$13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + wire width 3 \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire width 3 \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire width 3 \$5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire width 3 \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire width 3 \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" + wire input 5 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" + wire input 1 \coresync_rst + attribute \src "issuer_ls180.v:175324.7-175324.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire width 3 \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire width 3 \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire width 3 output 4 \q_src + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" + wire width 3 \qlq_src + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + wire width 3 \qn_src + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire width 3 input 3 \r_src + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire width 3 input 2 \s_src + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $and $and$issuer_ls180.v:175359$12318 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \q_int + connect \B \$7 + connect \Y $and$issuer_ls180.v:175359$12318_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $and $and$issuer_ls180.v:175364$12323 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \q_int + connect \B \$1 + connect \Y $and$issuer_ls180.v:175364$12323_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + cell $not $not$issuer_ls180.v:175361$12320 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \q_src + connect \Y $not$issuer_ls180.v:175361$12320_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $not $not$issuer_ls180.v:175363$12322 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \r_src + connect \Y $not$issuer_ls180.v:175363$12322_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $not $not$issuer_ls180.v:175366$12325 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \r_src + connect \Y $not$issuer_ls180.v:175366$12325_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $or $or$issuer_ls180.v:175360$12319 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \$9 + connect \B \s_src + connect \Y $or$issuer_ls180.v:175360$12319_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + cell $or $or$issuer_ls180.v:175362$12321 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \q_src + connect \B \q_int + connect \Y $or$issuer_ls180.v:175362$12321_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $or $or$issuer_ls180.v:175365$12324 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \$3 + connect \B \s_src + connect \Y $or$issuer_ls180.v:175365$12324_Y + end + attribute \src "issuer_ls180.v:175324.7-175324.20" + process $proc$issuer_ls180.v:175324$12330 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "issuer_ls180.v:175346.13-175346.25" + process $proc$issuer_ls180.v:175346$12331 + assign { } { } + assign $1\q_int[2:0] 3'000 + sync always + sync init + update \q_int $1\q_int[2:0] + end + attribute \src "issuer_ls180.v:175367.3-175368.27" + process $proc$issuer_ls180.v:175367$12326 + assign { } { } + assign $0\q_int[2:0] \q_int$next + sync posedge \coresync_clk + update \q_int $0\q_int[2:0] + end + attribute \src "issuer_ls180.v:175369.3-175377.6" + process $proc$issuer_ls180.v:175369$12327 + assign { } { } + assign { } { } + assign $0\q_int$next[2:0]$12328 $1\q_int$next[2:0]$12329 + attribute \src "issuer_ls180.v:175370.5-175370.29" + switch \initial + attribute \src "issuer_ls180.v:175370.9-175370.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\q_int$next[2:0]$12329 3'000 + case + assign $1\q_int$next[2:0]$12329 \$5 + end + sync always + update \q_int$next $0\q_int$next[2:0]$12328 + end + connect \$9 $and$issuer_ls180.v:175359$12318_Y + connect \$11 $or$issuer_ls180.v:175360$12319_Y + connect \$13 $not$issuer_ls180.v:175361$12320_Y + connect \$15 $or$issuer_ls180.v:175362$12321_Y + connect \$1 $not$issuer_ls180.v:175363$12322_Y + connect \$3 $and$issuer_ls180.v:175364$12323_Y + connect \$5 $or$issuer_ls180.v:175365$12324_Y + connect \$7 $not$issuer_ls180.v:175366$12325_Y + connect \qlq_src \$15 + connect \qn_src \$13 + connect \q_src \$11 +end +attribute \src "issuer_ls180.v:175385.1-175443.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.fus.spr0.src_l" +attribute \generator "nMigen" +module \src_l$64 + attribute \src "issuer_ls180.v:175386.7-175386.20" + wire $0\initial[0:0] + attribute \src "issuer_ls180.v:175431.3-175439.6" + wire width 6 $0\q_int$next[5:0]$12342 + attribute \src "issuer_ls180.v:175429.3-175430.27" + wire width 6 $0\q_int[5:0] + attribute \src "issuer_ls180.v:175431.3-175439.6" + wire width 6 $1\q_int$next[5:0]$12343 + attribute \src "issuer_ls180.v:175408.13-175408.26" + wire width 6 $1\q_int[5:0] + attribute \src "issuer_ls180.v:175421.17-175421.96" + wire width 6 $and$issuer_ls180.v:175421$12332_Y + attribute \src "issuer_ls180.v:175426.17-175426.96" + wire width 6 $and$issuer_ls180.v:175426$12337_Y + attribute \src "issuer_ls180.v:175423.18-175423.93" + wire width 6 $not$issuer_ls180.v:175423$12334_Y + attribute \src "issuer_ls180.v:175425.17-175425.92" + wire width 6 $not$issuer_ls180.v:175425$12336_Y + attribute \src "issuer_ls180.v:175428.17-175428.92" + wire width 6 $not$issuer_ls180.v:175428$12339_Y + attribute \src "issuer_ls180.v:175422.18-175422.98" + wire width 6 $or$issuer_ls180.v:175422$12333_Y + attribute \src "issuer_ls180.v:175424.18-175424.99" + wire width 6 $or$issuer_ls180.v:175424$12335_Y + attribute \src "issuer_ls180.v:175427.17-175427.97" + wire width 6 $or$issuer_ls180.v:175427$12338_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire width 6 \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire width 6 \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire width 6 \$13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + wire width 6 \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire width 6 \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire width 6 \$5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire width 6 \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire width 6 \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" + wire input 5 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" + wire input 1 \coresync_rst + attribute \src "issuer_ls180.v:175386.7-175386.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire width 6 \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire width 6 \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire width 6 output 4 \q_src + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" + wire width 6 \qlq_src + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + wire width 6 \qn_src + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire width 6 input 3 \r_src + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire width 6 input 2 \s_src + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $and $and$issuer_ls180.v:175421$12332 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 6 + connect \A \q_int + connect \B \$7 + connect \Y $and$issuer_ls180.v:175421$12332_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $and $and$issuer_ls180.v:175426$12337 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 6 + connect \A \q_int + connect \B \$1 + connect \Y $and$issuer_ls180.v:175426$12337_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + cell $not $not$issuer_ls180.v:175423$12334 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \Y_WIDTH 6 + connect \A \q_src + connect \Y $not$issuer_ls180.v:175423$12334_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $not $not$issuer_ls180.v:175425$12336 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \Y_WIDTH 6 + connect \A \r_src + connect \Y $not$issuer_ls180.v:175425$12336_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $not $not$issuer_ls180.v:175428$12339 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \Y_WIDTH 6 + connect \A \r_src + connect \Y $not$issuer_ls180.v:175428$12339_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $or $or$issuer_ls180.v:175422$12333 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 6 + connect \A \$9 + connect \B \s_src + connect \Y $or$issuer_ls180.v:175422$12333_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + cell $or $or$issuer_ls180.v:175424$12335 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 6 + connect \A \q_src + connect \B \q_int + connect \Y $or$issuer_ls180.v:175424$12335_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $or $or$issuer_ls180.v:175427$12338 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 6 + connect \A \$3 + connect \B \s_src + connect \Y $or$issuer_ls180.v:175427$12338_Y + end + attribute \src "issuer_ls180.v:175386.7-175386.20" + process $proc$issuer_ls180.v:175386$12344 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "issuer_ls180.v:175408.13-175408.26" + process $proc$issuer_ls180.v:175408$12345 + assign { } { } + assign $1\q_int[5:0] 6'000000 + sync always + sync init + update \q_int $1\q_int[5:0] + end + attribute \src "issuer_ls180.v:175429.3-175430.27" + process $proc$issuer_ls180.v:175429$12340 + assign { } { } + assign $0\q_int[5:0] \q_int$next + sync posedge \coresync_clk + update \q_int $0\q_int[5:0] + end + attribute \src "issuer_ls180.v:175431.3-175439.6" + process $proc$issuer_ls180.v:175431$12341 + assign { } { } + assign { } { } + assign $0\q_int$next[5:0]$12342 $1\q_int$next[5:0]$12343 + attribute \src "issuer_ls180.v:175432.5-175432.29" + switch \initial + attribute \src "issuer_ls180.v:175432.9-175432.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\q_int$next[5:0]$12343 6'000000 + case + assign $1\q_int$next[5:0]$12343 \$5 + end + sync always + update \q_int$next $0\q_int$next[5:0]$12342 + end + connect \$9 $and$issuer_ls180.v:175421$12332_Y + connect \$11 $or$issuer_ls180.v:175422$12333_Y + connect \$13 $not$issuer_ls180.v:175423$12334_Y + connect \$15 $or$issuer_ls180.v:175424$12335_Y + connect \$1 $not$issuer_ls180.v:175425$12336_Y + connect \$3 $and$issuer_ls180.v:175426$12337_Y + connect \$5 $or$issuer_ls180.v:175427$12338_Y + connect \$7 $not$issuer_ls180.v:175428$12339_Y + connect \qlq_src \$15 + connect \qn_src \$13 + connect \q_src \$11 +end +attribute \src "issuer_ls180.v:175447.1-175505.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.fus.div0.src_l" +attribute \generator "nMigen" +module \src_l$81 + attribute \src "issuer_ls180.v:175448.7-175448.20" + wire $0\initial[0:0] + attribute \src "issuer_ls180.v:175493.3-175501.6" + wire width 3 $0\q_int$next[2:0]$12356 + attribute \src "issuer_ls180.v:175491.3-175492.27" + wire width 3 $0\q_int[2:0] + attribute \src "issuer_ls180.v:175493.3-175501.6" + wire width 3 $1\q_int$next[2:0]$12357 + attribute \src "issuer_ls180.v:175470.13-175470.25" + wire width 3 $1\q_int[2:0] + attribute \src "issuer_ls180.v:175483.17-175483.96" + wire width 3 $and$issuer_ls180.v:175483$12346_Y + attribute \src "issuer_ls180.v:175488.17-175488.96" + wire width 3 $and$issuer_ls180.v:175488$12351_Y + attribute \src "issuer_ls180.v:175485.18-175485.93" + wire width 3 $not$issuer_ls180.v:175485$12348_Y + attribute \src "issuer_ls180.v:175487.17-175487.92" + wire width 3 $not$issuer_ls180.v:175487$12350_Y + attribute \src "issuer_ls180.v:175490.17-175490.92" + wire width 3 $not$issuer_ls180.v:175490$12353_Y + attribute \src "issuer_ls180.v:175484.18-175484.98" + wire width 3 $or$issuer_ls180.v:175484$12347_Y + attribute \src "issuer_ls180.v:175486.18-175486.99" + wire width 3 $or$issuer_ls180.v:175486$12349_Y + attribute \src "issuer_ls180.v:175489.17-175489.97" + wire width 3 $or$issuer_ls180.v:175489$12352_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire width 3 \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire width 3 \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire width 3 \$13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + wire width 3 \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire width 3 \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire width 3 \$5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire width 3 \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire width 3 \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" + wire input 5 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" + wire input 1 \coresync_rst + attribute \src "issuer_ls180.v:175448.7-175448.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire width 3 \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire width 3 \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire width 3 output 4 \q_src + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" + wire width 3 \qlq_src + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + wire width 3 \qn_src + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire width 3 input 3 \r_src + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire width 3 input 2 \s_src + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $and $and$issuer_ls180.v:175483$12346 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \q_int + connect \B \$7 + connect \Y $and$issuer_ls180.v:175483$12346_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $and $and$issuer_ls180.v:175488$12351 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \q_int + connect \B \$1 + connect \Y $and$issuer_ls180.v:175488$12351_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + cell $not $not$issuer_ls180.v:175485$12348 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \q_src + connect \Y $not$issuer_ls180.v:175485$12348_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $not $not$issuer_ls180.v:175487$12350 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \r_src + connect \Y $not$issuer_ls180.v:175487$12350_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $not $not$issuer_ls180.v:175490$12353 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \r_src + connect \Y $not$issuer_ls180.v:175490$12353_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $or $or$issuer_ls180.v:175484$12347 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \$9 + connect \B \s_src + connect \Y $or$issuer_ls180.v:175484$12347_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + cell $or $or$issuer_ls180.v:175486$12349 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \q_src + connect \B \q_int + connect \Y $or$issuer_ls180.v:175486$12349_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $or $or$issuer_ls180.v:175489$12352 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \$3 + connect \B \s_src + connect \Y $or$issuer_ls180.v:175489$12352_Y + end + attribute \src "issuer_ls180.v:175448.7-175448.20" + process $proc$issuer_ls180.v:175448$12358 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "issuer_ls180.v:175470.13-175470.25" + process $proc$issuer_ls180.v:175470$12359 + assign { } { } + assign $1\q_int[2:0] 3'000 + sync always + sync init + update \q_int $1\q_int[2:0] + end + attribute \src "issuer_ls180.v:175491.3-175492.27" + process $proc$issuer_ls180.v:175491$12354 + assign { } { } + assign $0\q_int[2:0] \q_int$next + sync posedge \coresync_clk + update \q_int $0\q_int[2:0] + end + attribute \src "issuer_ls180.v:175493.3-175501.6" + process $proc$issuer_ls180.v:175493$12355 + assign { } { } + assign { } { } + assign $0\q_int$next[2:0]$12356 $1\q_int$next[2:0]$12357 + attribute \src "issuer_ls180.v:175494.5-175494.29" + switch \initial + attribute \src "issuer_ls180.v:175494.9-175494.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\q_int$next[2:0]$12357 3'000 + case + assign $1\q_int$next[2:0]$12357 \$5 + end + sync always + update \q_int$next $0\q_int$next[2:0]$12356 + end + connect \$9 $and$issuer_ls180.v:175483$12346_Y + connect \$11 $or$issuer_ls180.v:175484$12347_Y + connect \$13 $not$issuer_ls180.v:175485$12348_Y + connect \$15 $or$issuer_ls180.v:175486$12349_Y + connect \$1 $not$issuer_ls180.v:175487$12350_Y + connect \$3 $and$issuer_ls180.v:175488$12351_Y + connect \$5 $or$issuer_ls180.v:175489$12352_Y + connect \$7 $not$issuer_ls180.v:175490$12353_Y + connect \qlq_src \$15 + connect \qn_src \$13 + connect \q_src \$11 +end +attribute \src "issuer_ls180.v:175509.1-175567.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.fus.mul0.src_l" +attribute \generator "nMigen" +module \src_l$98 + attribute \src "issuer_ls180.v:175510.7-175510.20" + wire $0\initial[0:0] + attribute \src "issuer_ls180.v:175555.3-175563.6" + wire width 3 $0\q_int$next[2:0]$12370 + attribute \src "issuer_ls180.v:175553.3-175554.27" + wire width 3 $0\q_int[2:0] + attribute \src "issuer_ls180.v:175555.3-175563.6" + wire width 3 $1\q_int$next[2:0]$12371 + attribute \src "issuer_ls180.v:175532.13-175532.25" + wire width 3 $1\q_int[2:0] + attribute \src "issuer_ls180.v:175545.17-175545.96" + wire width 3 $and$issuer_ls180.v:175545$12360_Y + attribute \src "issuer_ls180.v:175550.17-175550.96" + wire width 3 $and$issuer_ls180.v:175550$12365_Y + attribute \src "issuer_ls180.v:175547.18-175547.93" + wire width 3 $not$issuer_ls180.v:175547$12362_Y + attribute \src "issuer_ls180.v:175549.17-175549.92" + wire width 3 $not$issuer_ls180.v:175549$12364_Y + attribute \src "issuer_ls180.v:175552.17-175552.92" + wire width 3 $not$issuer_ls180.v:175552$12367_Y + attribute \src "issuer_ls180.v:175546.18-175546.98" + wire width 3 $or$issuer_ls180.v:175546$12361_Y + attribute \src "issuer_ls180.v:175548.18-175548.99" + wire width 3 $or$issuer_ls180.v:175548$12363_Y + attribute \src "issuer_ls180.v:175551.17-175551.97" + wire width 3 $or$issuer_ls180.v:175551$12366_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire width 3 \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire width 3 \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire width 3 \$13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + wire width 3 \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire width 3 \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire width 3 \$5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire width 3 \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire width 3 \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" + wire input 5 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" + wire input 1 \coresync_rst + attribute \src "issuer_ls180.v:175510.7-175510.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire width 3 \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire width 3 \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire width 3 output 4 \q_src + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" + wire width 3 \qlq_src + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + wire width 3 \qn_src + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire width 3 input 3 \r_src + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire width 3 input 2 \s_src + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $and $and$issuer_ls180.v:175545$12360 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \q_int + connect \B \$7 + connect \Y $and$issuer_ls180.v:175545$12360_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $and $and$issuer_ls180.v:175550$12365 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \q_int + connect \B \$1 + connect \Y $and$issuer_ls180.v:175550$12365_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + cell $not $not$issuer_ls180.v:175547$12362 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \q_src + connect \Y $not$issuer_ls180.v:175547$12362_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $not $not$issuer_ls180.v:175549$12364 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \r_src + connect \Y $not$issuer_ls180.v:175549$12364_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $not $not$issuer_ls180.v:175552$12367 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \r_src + connect \Y $not$issuer_ls180.v:175552$12367_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $or $or$issuer_ls180.v:175546$12361 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \$9 + connect \B \s_src + connect \Y $or$issuer_ls180.v:175546$12361_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + cell $or $or$issuer_ls180.v:175548$12363 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \q_src + connect \B \q_int + connect \Y $or$issuer_ls180.v:175548$12363_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $or $or$issuer_ls180.v:175551$12366 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \$3 + connect \B \s_src + connect \Y $or$issuer_ls180.v:175551$12366_Y + end + attribute \src "issuer_ls180.v:175510.7-175510.20" + process $proc$issuer_ls180.v:175510$12372 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "issuer_ls180.v:175532.13-175532.25" + process $proc$issuer_ls180.v:175532$12373 + assign { } { } + assign $1\q_int[2:0] 3'000 + sync always + sync init + update \q_int $1\q_int[2:0] + end + attribute \src "issuer_ls180.v:175553.3-175554.27" + process $proc$issuer_ls180.v:175553$12368 + assign { } { } + assign $0\q_int[2:0] \q_int$next + sync posedge \coresync_clk + update \q_int $0\q_int[2:0] + end + attribute \src "issuer_ls180.v:175555.3-175563.6" + process $proc$issuer_ls180.v:175555$12369 + assign { } { } + assign { } { } + assign $0\q_int$next[2:0]$12370 $1\q_int$next[2:0]$12371 + attribute \src "issuer_ls180.v:175556.5-175556.29" + switch \initial + attribute \src "issuer_ls180.v:175556.9-175556.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\q_int$next[2:0]$12371 3'000 + case + assign $1\q_int$next[2:0]$12371 \$5 + end + sync always + update \q_int$next $0\q_int$next[2:0]$12370 + end + connect \$9 $and$issuer_ls180.v:175545$12360_Y + connect \$11 $or$issuer_ls180.v:175546$12361_Y + connect \$13 $not$issuer_ls180.v:175547$12362_Y + connect \$15 $or$issuer_ls180.v:175548$12363_Y + connect \$1 $not$issuer_ls180.v:175549$12364_Y + connect \$3 $and$issuer_ls180.v:175550$12365_Y + connect \$5 $or$issuer_ls180.v:175551$12366_Y + connect \$7 $not$issuer_ls180.v:175552$12367_Y + connect \qlq_src \$15 + connect \qn_src \$13 + connect \q_src \$11 +end +attribute \src "issuer_ls180.v:175571.1-175629.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.l0.pimem.st_active" +attribute \generator "nMigen" +module \st_active + attribute \src "issuer_ls180.v:175572.7-175572.20" + wire $0\initial[0:0] + attribute \src "issuer_ls180.v:175617.3-175625.6" + wire $0\q_int$next[0:0]$12384 + attribute \src "issuer_ls180.v:175615.3-175616.27" + wire $0\q_int[0:0] + attribute \src "issuer_ls180.v:175617.3-175625.6" + wire $1\q_int$next[0:0]$12385 + attribute \src "issuer_ls180.v:175594.7-175594.19" + wire $1\q_int[0:0] + attribute \src "issuer_ls180.v:175607.17-175607.96" + wire $and$issuer_ls180.v:175607$12374_Y + attribute \src "issuer_ls180.v:175612.17-175612.96" + wire $and$issuer_ls180.v:175612$12379_Y + attribute \src "issuer_ls180.v:175609.18-175609.99" + wire $not$issuer_ls180.v:175609$12376_Y + attribute \src "issuer_ls180.v:175611.17-175611.98" + wire $not$issuer_ls180.v:175611$12378_Y + attribute \src "issuer_ls180.v:175614.17-175614.98" + wire $not$issuer_ls180.v:175614$12381_Y + attribute \src "issuer_ls180.v:175608.18-175608.104" + wire $or$issuer_ls180.v:175608$12375_Y + attribute \src "issuer_ls180.v:175610.18-175610.105" + wire $or$issuer_ls180.v:175610$12377_Y + attribute \src "issuer_ls180.v:175613.17-175613.103" + wire $or$issuer_ls180.v:175613$12380_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire \$13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" + wire input 5 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" + wire input 1 \coresync_rst + attribute \src "issuer_ls180.v:175572.7-175572.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire output 4 \q_st_active + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" + wire \qlq_st_active + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + wire \qn_st_active + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire input 2 \r_st_active + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire input 3 \s_st_active + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $and $and$issuer_ls180.v:175607$12374 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$7 + connect \Y $and$issuer_ls180.v:175607$12374_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $and $and$issuer_ls180.v:175612$12379 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$1 + connect \Y $and$issuer_ls180.v:175612$12379_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + cell $not $not$issuer_ls180.v:175609$12376 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_st_active + connect \Y $not$issuer_ls180.v:175609$12376_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $not $not$issuer_ls180.v:175611$12378 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_st_active + connect \Y $not$issuer_ls180.v:175611$12378_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $not $not$issuer_ls180.v:175614$12381 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_st_active + connect \Y $not$issuer_ls180.v:175614$12381_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $or $or$issuer_ls180.v:175608$12375 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$9 + connect \B \s_st_active + connect \Y $or$issuer_ls180.v:175608$12375_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + cell $or $or$issuer_ls180.v:175610$12377 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_st_active + connect \B \q_int + connect \Y $or$issuer_ls180.v:175610$12377_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $or $or$issuer_ls180.v:175613$12380 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$3 + connect \B \s_st_active + connect \Y $or$issuer_ls180.v:175613$12380_Y + end + attribute \src "issuer_ls180.v:175572.7-175572.20" + process $proc$issuer_ls180.v:175572$12386 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "issuer_ls180.v:175594.7-175594.19" + process $proc$issuer_ls180.v:175594$12387 + assign { } { } + assign $1\q_int[0:0] 1'0 + sync always + sync init + update \q_int $1\q_int[0:0] + end + attribute \src "issuer_ls180.v:175615.3-175616.27" + process $proc$issuer_ls180.v:175615$12382 + assign { } { } + assign $0\q_int[0:0] \q_int$next + sync posedge \coresync_clk + update \q_int $0\q_int[0:0] + end + attribute \src "issuer_ls180.v:175617.3-175625.6" + process $proc$issuer_ls180.v:175617$12383 + assign { } { } + assign { } { } + assign $0\q_int$next[0:0]$12384 $1\q_int$next[0:0]$12385 + attribute \src "issuer_ls180.v:175618.5-175618.29" + switch \initial + attribute \src "issuer_ls180.v:175618.9-175618.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\q_int$next[0:0]$12385 1'0 + case + assign $1\q_int$next[0:0]$12385 \$5 + end + sync always + update \q_int$next $0\q_int$next[0:0]$12384 + end + connect \$9 $and$issuer_ls180.v:175607$12374_Y + connect \$11 $or$issuer_ls180.v:175608$12375_Y + connect \$13 $not$issuer_ls180.v:175609$12376_Y + connect \$15 $or$issuer_ls180.v:175610$12377_Y + connect \$1 $not$issuer_ls180.v:175611$12378_Y + connect \$3 $and$issuer_ls180.v:175612$12379_Y + connect \$5 $or$issuer_ls180.v:175613$12380_Y + connect \$7 $not$issuer_ls180.v:175614$12381_Y + connect \qlq_st_active \$15 + connect \qn_st_active \$13 + connect \q_st_active \$11 +end +attribute \src "issuer_ls180.v:175633.1-175691.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.l0.pimem.st_done" +attribute \generator "nMigen" +module \st_done + attribute \src "issuer_ls180.v:175634.7-175634.20" + wire $0\initial[0:0] + attribute \src "issuer_ls180.v:175679.3-175687.6" + wire $0\q_int$next[0:0]$12398 + attribute \src "issuer_ls180.v:175677.3-175678.27" + wire $0\q_int[0:0] + attribute \src "issuer_ls180.v:175679.3-175687.6" + wire $1\q_int$next[0:0]$12399 + attribute \src "issuer_ls180.v:175656.7-175656.19" + wire $1\q_int[0:0] + attribute \src "issuer_ls180.v:175669.17-175669.96" + wire $and$issuer_ls180.v:175669$12388_Y + attribute \src "issuer_ls180.v:175674.17-175674.96" + wire $and$issuer_ls180.v:175674$12393_Y + attribute \src "issuer_ls180.v:175671.18-175671.97" + wire $not$issuer_ls180.v:175671$12390_Y + attribute \src "issuer_ls180.v:175673.17-175673.96" + wire $not$issuer_ls180.v:175673$12392_Y + attribute \src "issuer_ls180.v:175676.17-175676.96" + wire $not$issuer_ls180.v:175676$12395_Y + attribute \src "issuer_ls180.v:175670.18-175670.102" + wire $or$issuer_ls180.v:175670$12389_Y + attribute \src "issuer_ls180.v:175672.18-175672.103" + wire $or$issuer_ls180.v:175672$12391_Y + attribute \src "issuer_ls180.v:175675.17-175675.101" + wire $or$issuer_ls180.v:175675$12394_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire \$13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" + wire input 5 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" + wire input 1 \coresync_rst + attribute \src "issuer_ls180.v:175634.7-175634.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire output 4 \q_st_done + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" + wire \qlq_st_done + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + wire \qn_st_done + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire input 3 \r_st_done + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire input 2 \s_st_done + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $and $and$issuer_ls180.v:175669$12388 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$7 + connect \Y $and$issuer_ls180.v:175669$12388_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $and $and$issuer_ls180.v:175674$12393 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$1 + connect \Y $and$issuer_ls180.v:175674$12393_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + cell $not $not$issuer_ls180.v:175671$12390 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_st_done + connect \Y $not$issuer_ls180.v:175671$12390_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $not $not$issuer_ls180.v:175673$12392 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_st_done + connect \Y $not$issuer_ls180.v:175673$12392_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $not $not$issuer_ls180.v:175676$12395 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_st_done + connect \Y $not$issuer_ls180.v:175676$12395_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $or $or$issuer_ls180.v:175670$12389 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$9 + connect \B \s_st_done + connect \Y $or$issuer_ls180.v:175670$12389_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + cell $or $or$issuer_ls180.v:175672$12391 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_st_done + connect \B \q_int + connect \Y $or$issuer_ls180.v:175672$12391_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $or $or$issuer_ls180.v:175675$12394 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$3 + connect \B \s_st_done + connect \Y $or$issuer_ls180.v:175675$12394_Y + end + attribute \src "issuer_ls180.v:175634.7-175634.20" + process $proc$issuer_ls180.v:175634$12400 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "issuer_ls180.v:175656.7-175656.19" + process $proc$issuer_ls180.v:175656$12401 + assign { } { } + assign $1\q_int[0:0] 1'0 + sync always + sync init + update \q_int $1\q_int[0:0] + end + attribute \src "issuer_ls180.v:175677.3-175678.27" + process $proc$issuer_ls180.v:175677$12396 + assign { } { } + assign $0\q_int[0:0] \q_int$next + sync posedge \coresync_clk + update \q_int $0\q_int[0:0] + end + attribute \src "issuer_ls180.v:175679.3-175687.6" + process $proc$issuer_ls180.v:175679$12397 + assign { } { } + assign { } { } + assign $0\q_int$next[0:0]$12398 $1\q_int$next[0:0]$12399 + attribute \src "issuer_ls180.v:175680.5-175680.29" + switch \initial + attribute \src "issuer_ls180.v:175680.9-175680.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\q_int$next[0:0]$12399 1'0 + case + assign $1\q_int$next[0:0]$12399 \$5 + end + sync always + update \q_int$next $0\q_int$next[0:0]$12398 + end + connect \$9 $and$issuer_ls180.v:175669$12388_Y + connect \$11 $or$issuer_ls180.v:175670$12389_Y + connect \$13 $not$issuer_ls180.v:175671$12390_Y + connect \$15 $or$issuer_ls180.v:175672$12391_Y + connect \$1 $not$issuer_ls180.v:175673$12392_Y + connect \$3 $and$issuer_ls180.v:175674$12393_Y + connect \$5 $or$issuer_ls180.v:175675$12394_Y + connect \$7 $not$issuer_ls180.v:175676$12395_Y + connect \qlq_st_done \$15 + connect \qn_st_done \$13 + connect \q_st_done \$11 +end +attribute \src "issuer_ls180.v:175695.1-175950.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.state" +attribute \generator "nMigen" +module \state + attribute \src "issuer_ls180.v:175923.3-175932.6" + wire width 64 $0\cia__data_o[63:0] + attribute \src "issuer_ls180.v:175696.7-175696.20" + wire $0\initial[0:0] + attribute \src "issuer_ls180.v:175904.3-175913.6" + wire width 64 $0\msr__data_o[63:0] + attribute \src "issuer_ls180.v:175895.3-175903.6" + wire width 4 $0\ren_delay$12$next[3:0]$12414 + attribute \src "issuer_ls180.v:175835.3-175836.43" + wire width 4 $0\ren_delay$12[3:0]$12411 + attribute \src "issuer_ls180.v:175816.13-175816.34" + wire width 4 $0\ren_delay$12[3:0]$12424 + attribute \src "issuer_ls180.v:175914.3-175922.6" + wire width 4 $0\ren_delay$next[3:0]$12418 + attribute \src "issuer_ls180.v:175837.3-175838.35" + wire width 4 $0\ren_delay[3:0] + attribute \src "issuer_ls180.v:175923.3-175932.6" + wire width 64 $1\cia__data_o[63:0] + attribute \src "issuer_ls180.v:175904.3-175913.6" + wire width 64 $1\msr__data_o[63:0] + attribute \src "issuer_ls180.v:175895.3-175903.6" + wire width 4 $1\ren_delay$12$next[3:0]$12415 + attribute \src "issuer_ls180.v:175914.3-175922.6" + wire width 4 $1\ren_delay$next[3:0]$12419 + attribute \src "issuer_ls180.v:175814.13-175814.29" + wire width 4 $1\ren_delay[3:0] + attribute \src "issuer_ls180.v:175827.18-175827.95" + wire width 64 $or$issuer_ls180.v:175827$12402_Y + attribute \src "issuer_ls180.v:175829.18-175829.124" + wire width 64 $or$issuer_ls180.v:175829$12404_Y + attribute \src "issuer_ls180.v:175830.18-175830.124" + wire width 64 $or$issuer_ls180.v:175830$12405_Y + attribute \src "issuer_ls180.v:175831.18-175831.97" + wire width 64 $or$issuer_ls180.v:175831$12406_Y + attribute \src "issuer_ls180.v:175833.17-175833.123" + wire width 64 $or$issuer_ls180.v:175833$12408_Y + attribute \src "issuer_ls180.v:175834.17-175834.123" + wire width 64 $or$issuer_ls180.v:175834$12409_Y + attribute \src "issuer_ls180.v:175828.18-175828.100" + wire $reduce_or$issuer_ls180.v:175828$12403_Y + attribute \src "issuer_ls180.v:175832.17-175832.95" + wire $reduce_or$issuer_ls180.v:175832$12407_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" + wire width 64 \$10 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" + wire \$13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + wire width 64 \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + wire width 64 \$17 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" + wire width 64 \$19 + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" + wire \$4 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + wire width 64 \$6 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + wire width 64 \$8 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 64 output 2 \cia__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 input 1 \cia__ren + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" + wire input 12 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" + wire input 11 \coresync_rst + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 64 input 4 \data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 64 input 8 \data_i$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 64 input 9 \data_i$2 + attribute \src "issuer_ls180.v:175696.7-175696.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 64 output 6 \msr__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 input 5 \msr__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 64 \reg_0_cia0__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire \reg_0_cia0__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 64 \reg_0_d_wr10__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire \reg_0_d_wr10__wen + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 64 \reg_0_msr0__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 64 \reg_0_msr0__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire \reg_0_msr0__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire \reg_0_msr0__wen + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 64 \reg_0_nia0__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire \reg_0_nia0__wen + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 64 \reg_1_cia1__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire \reg_1_cia1__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 64 \reg_1_d_wr11__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire \reg_1_d_wr11__wen + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 64 \reg_1_msr1__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 64 \reg_1_msr1__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire \reg_1_msr1__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire \reg_1_msr1__wen + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 64 \reg_1_nia1__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire \reg_1_nia1__wen + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 64 \reg_2_cia2__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire \reg_2_cia2__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 64 \reg_2_d_wr12__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire \reg_2_d_wr12__wen + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 64 \reg_2_msr2__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 64 \reg_2_msr2__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire \reg_2_msr2__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire \reg_2_msr2__wen + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 64 \reg_2_nia2__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire \reg_2_nia2__wen + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 64 \reg_3_cia3__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire \reg_3_cia3__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 64 \reg_3_d_wr13__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire \reg_3_d_wr13__wen + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 64 \reg_3_msr3__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 64 \reg_3_msr3__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire \reg_3_msr3__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire \reg_3_msr3__wen + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 64 \reg_3_nia3__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire \reg_3_nia3__wen + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:170" + wire width 4 \ren_delay + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:170" + wire width 4 \ren_delay$12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:170" + wire width 4 \ren_delay$12$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:170" + wire width 4 \ren_delay$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 input 7 \state_nia_wen + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 input 3 \wen + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 4 input 10 \wen$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" + cell $or $or$issuer_ls180.v:175827$12402 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A \$6 + connect \B \$8 + connect \Y $or$issuer_ls180.v:175827$12402_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + cell $or $or$issuer_ls180.v:175829$12404 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A \reg_0_msr0__data_o + connect \B \reg_1_msr1__data_o + connect \Y $or$issuer_ls180.v:175829$12404_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + cell $or $or$issuer_ls180.v:175830$12405 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A \reg_2_msr2__data_o + connect \B \reg_3_msr3__data_o + connect \Y $or$issuer_ls180.v:175830$12405_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" + cell $or $or$issuer_ls180.v:175831$12406 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A \$15 + connect \B \$17 + connect \Y $or$issuer_ls180.v:175831$12406_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + cell $or $or$issuer_ls180.v:175833$12408 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A \reg_0_cia0__data_o + connect \B \reg_1_cia1__data_o + connect \Y $or$issuer_ls180.v:175833$12408_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + cell $or $or$issuer_ls180.v:175834$12409 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A \reg_2_cia2__data_o + connect \B \reg_3_cia3__data_o + connect \Y $or$issuer_ls180.v:175834$12409_Y + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" + cell $reduce_or $reduce_or$issuer_ls180.v:175828$12403 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \ren_delay$12 + connect \Y $reduce_or$issuer_ls180.v:175828$12403_Y + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" + cell $reduce_or $reduce_or$issuer_ls180.v:175832$12407 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \ren_delay + connect \Y $reduce_or$issuer_ls180.v:175832$12407_Y + end + attribute \module_not_derived 1 + attribute \src "issuer_ls180.v:175839.15-175852.4" + cell \reg_0$132 \reg_0 + connect \cia0__data_o \reg_0_cia0__data_o + connect \cia0__ren \reg_0_cia0__ren + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \d_wr10__data_i \reg_0_d_wr10__data_i + connect \d_wr10__wen \reg_0_d_wr10__wen + connect \msr0__data_i \reg_0_msr0__data_i + connect \msr0__data_o \reg_0_msr0__data_o + connect \msr0__ren \reg_0_msr0__ren + connect \msr0__wen \reg_0_msr0__wen + connect \nia0__data_i \reg_0_nia0__data_i + connect \nia0__wen \reg_0_nia0__wen + end + attribute \module_not_derived 1 + attribute \src "issuer_ls180.v:175853.15-175866.4" + cell \reg_1$133 \reg_1 + connect \cia1__data_o \reg_1_cia1__data_o + connect \cia1__ren \reg_1_cia1__ren + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \d_wr11__data_i \reg_1_d_wr11__data_i + connect \d_wr11__wen \reg_1_d_wr11__wen + connect \msr1__data_i \reg_1_msr1__data_i + connect \msr1__data_o \reg_1_msr1__data_o + connect \msr1__ren \reg_1_msr1__ren + connect \msr1__wen \reg_1_msr1__wen + connect \nia1__data_i \reg_1_nia1__data_i + connect \nia1__wen \reg_1_nia1__wen + end + attribute \module_not_derived 1 + attribute \src "issuer_ls180.v:175867.15-175880.4" + cell \reg_2$134 \reg_2 + connect \cia2__data_o \reg_2_cia2__data_o + connect \cia2__ren \reg_2_cia2__ren + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \d_wr12__data_i \reg_2_d_wr12__data_i + connect \d_wr12__wen \reg_2_d_wr12__wen + connect \msr2__data_i \reg_2_msr2__data_i + connect \msr2__data_o \reg_2_msr2__data_o + connect \msr2__ren \reg_2_msr2__ren + connect \msr2__wen \reg_2_msr2__wen + connect \nia2__data_i \reg_2_nia2__data_i + connect \nia2__wen \reg_2_nia2__wen + end + attribute \module_not_derived 1 + attribute \src "issuer_ls180.v:175881.15-175894.4" + cell \reg_3$135 \reg_3 + connect \cia3__data_o \reg_3_cia3__data_o + connect \cia3__ren \reg_3_cia3__ren + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \d_wr13__data_i \reg_3_d_wr13__data_i + connect \d_wr13__wen \reg_3_d_wr13__wen + connect \msr3__data_i \reg_3_msr3__data_i + connect \msr3__data_o \reg_3_msr3__data_o + connect \msr3__ren \reg_3_msr3__ren + connect \msr3__wen \reg_3_msr3__wen + connect \nia3__data_i \reg_3_nia3__data_i + connect \nia3__wen \reg_3_nia3__wen + end + attribute \src "issuer_ls180.v:175696.7-175696.20" + process $proc$issuer_ls180.v:175696$12421 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "issuer_ls180.v:175814.13-175814.29" + process $proc$issuer_ls180.v:175814$12422 + assign { } { } + assign $1\ren_delay[3:0] 4'0000 + sync always + sync init + update \ren_delay $1\ren_delay[3:0] + end + attribute \src "issuer_ls180.v:175816.13-175816.34" + process $proc$issuer_ls180.v:175816$12423 + assign { } { } + assign $0\ren_delay$12[3:0]$12424 4'0000 + sync always + sync init + update \ren_delay$12 $0\ren_delay$12[3:0]$12424 + end + attribute \src "issuer_ls180.v:175835.3-175836.43" + process $proc$issuer_ls180.v:175835$12410 + assign { } { } + assign $0\ren_delay$12[3:0]$12411 \ren_delay$12$next + sync posedge \coresync_clk + update \ren_delay$12 $0\ren_delay$12[3:0]$12411 + end + attribute \src "issuer_ls180.v:175837.3-175838.35" + process $proc$issuer_ls180.v:175837$12412 + assign { } { } + assign $0\ren_delay[3:0] \ren_delay$next + sync posedge \coresync_clk + update \ren_delay $0\ren_delay[3:0] + end + attribute \src "issuer_ls180.v:175895.3-175903.6" + process $proc$issuer_ls180.v:175895$12413 + assign { } { } + assign { } { } + assign $0\ren_delay$12$next[3:0]$12414 $1\ren_delay$12$next[3:0]$12415 + attribute \src "issuer_ls180.v:175896.5-175896.29" + switch \initial + attribute \src "issuer_ls180.v:175896.9-175896.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\ren_delay$12$next[3:0]$12415 4'0000 + case + assign $1\ren_delay$12$next[3:0]$12415 \msr__ren + end + sync always + update \ren_delay$12$next $0\ren_delay$12$next[3:0]$12414 + end + attribute \src "issuer_ls180.v:175904.3-175913.6" + process $proc$issuer_ls180.v:175904$12416 + assign { } { } + assign { } { } + assign $0\msr__data_o[63:0] $1\msr__data_o[63:0] + attribute \src "issuer_ls180.v:175905.5-175905.29" + switch \initial + attribute \src "issuer_ls180.v:175905.9-175905.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:172" + switch \$13 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\msr__data_o[63:0] \$19 + case + assign $1\msr__data_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \msr__data_o $0\msr__data_o[63:0] + end + attribute \src "issuer_ls180.v:175914.3-175922.6" + process $proc$issuer_ls180.v:175914$12417 + assign { } { } + assign { } { } + assign $0\ren_delay$next[3:0]$12418 $1\ren_delay$next[3:0]$12419 + attribute \src "issuer_ls180.v:175915.5-175915.29" + switch \initial + attribute \src "issuer_ls180.v:175915.9-175915.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\ren_delay$next[3:0]$12419 4'0000 + case + assign $1\ren_delay$next[3:0]$12419 \cia__ren + end + sync always + update \ren_delay$next $0\ren_delay$next[3:0]$12418 + end + attribute \src "issuer_ls180.v:175923.3-175932.6" + process $proc$issuer_ls180.v:175923$12420 + assign { } { } + assign { } { } + assign $0\cia__data_o[63:0] $1\cia__data_o[63:0] + attribute \src "issuer_ls180.v:175924.5-175924.29" + switch \initial + attribute \src "issuer_ls180.v:175924.9-175924.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:172" + switch \$4 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\cia__data_o[63:0] \$10 + case + assign $1\cia__data_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \cia__data_o $0\cia__data_o[63:0] + end + connect \$10 $or$issuer_ls180.v:175827$12402_Y + connect \$13 $reduce_or$issuer_ls180.v:175828$12403_Y + connect \$15 $or$issuer_ls180.v:175829$12404_Y + connect \$17 $or$issuer_ls180.v:175830$12405_Y + connect \$19 $or$issuer_ls180.v:175831$12406_Y + connect \$4 $reduce_or$issuer_ls180.v:175832$12407_Y + connect \$6 $or$issuer_ls180.v:175833$12408_Y + connect \$8 $or$issuer_ls180.v:175834$12409_Y + connect \reg_3_d_wr13__data_i \data_i + connect \reg_2_d_wr12__data_i \data_i + connect \reg_1_d_wr11__data_i \data_i + connect \reg_0_d_wr10__data_i \data_i + connect { \reg_3_d_wr13__wen \reg_2_d_wr12__wen \reg_1_d_wr11__wen \reg_0_d_wr10__wen } \wen + connect \reg_3_msr3__data_i \data_i$2 + connect \reg_2_msr2__data_i \data_i$2 + connect \reg_1_msr1__data_i \data_i$2 + connect \reg_0_msr0__data_i \data_i$2 + connect { \reg_3_msr3__wen \reg_2_msr2__wen \reg_1_msr1__wen \reg_0_msr0__wen } \wen$3 + connect \reg_3_nia3__data_i \data_i$1 + connect \reg_2_nia2__data_i \data_i$1 + connect \reg_1_nia1__data_i \data_i$1 + connect \reg_0_nia0__data_i \data_i$1 + connect { \reg_3_nia3__wen \reg_2_nia2__wen \reg_1_nia1__wen \reg_0_nia0__wen } \state_nia_wen + connect { \reg_3_msr3__ren \reg_2_msr2__ren \reg_1_msr1__ren \reg_0_msr0__ren } \msr__ren + connect { \reg_3_cia3__ren \reg_2_cia2__ren \reg_1_cia1__ren \reg_0_cia0__ren } \cia__ren +end +attribute \src "issuer_ls180.v:175954.1-176012.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.fus.ldst0.sto_l" +attribute \generator "nMigen" +module \sto_l + attribute \src "issuer_ls180.v:175955.7-175955.20" + wire $0\initial[0:0] + attribute \src "issuer_ls180.v:176000.3-176008.6" + wire $0\q_int$next[0:0]$12435 + attribute \src "issuer_ls180.v:175998.3-175999.27" + wire $0\q_int[0:0] + attribute \src "issuer_ls180.v:176000.3-176008.6" + wire $1\q_int$next[0:0]$12436 + attribute \src "issuer_ls180.v:175977.7-175977.19" + wire $1\q_int[0:0] + attribute \src "issuer_ls180.v:175990.17-175990.96" + wire $and$issuer_ls180.v:175990$12425_Y + attribute \src "issuer_ls180.v:175995.17-175995.96" + wire $and$issuer_ls180.v:175995$12430_Y + attribute \src "issuer_ls180.v:175992.18-175992.93" + wire $not$issuer_ls180.v:175992$12427_Y + attribute \src "issuer_ls180.v:175994.17-175994.92" + wire $not$issuer_ls180.v:175994$12429_Y + attribute \src "issuer_ls180.v:175997.17-175997.92" + wire $not$issuer_ls180.v:175997$12432_Y + attribute \src "issuer_ls180.v:175991.18-175991.98" + wire $or$issuer_ls180.v:175991$12426_Y + attribute \src "issuer_ls180.v:175993.18-175993.99" + wire $or$issuer_ls180.v:175993$12428_Y + attribute \src "issuer_ls180.v:175996.17-175996.97" + wire $or$issuer_ls180.v:175996$12431_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire \$13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" + wire input 5 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" + wire input 1 \coresync_rst + attribute \src "issuer_ls180.v:175955.7-175955.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire output 4 \q_sto + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" + wire \qlq_sto + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + wire \qn_sto + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire input 3 \r_sto + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire input 2 \s_sto + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $and $and$issuer_ls180.v:175990$12425 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$7 + connect \Y $and$issuer_ls180.v:175990$12425_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $and $and$issuer_ls180.v:175995$12430 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$1 + connect \Y $and$issuer_ls180.v:175995$12430_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + cell $not $not$issuer_ls180.v:175992$12427 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_sto + connect \Y $not$issuer_ls180.v:175992$12427_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $not $not$issuer_ls180.v:175994$12429 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_sto + connect \Y $not$issuer_ls180.v:175994$12429_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $not $not$issuer_ls180.v:175997$12432 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_sto + connect \Y $not$issuer_ls180.v:175997$12432_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $or $or$issuer_ls180.v:175991$12426 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$9 + connect \B \s_sto + connect \Y $or$issuer_ls180.v:175991$12426_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + cell $or $or$issuer_ls180.v:175993$12428 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_sto + connect \B \q_int + connect \Y $or$issuer_ls180.v:175993$12428_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $or $or$issuer_ls180.v:175996$12431 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$3 + connect \B \s_sto + connect \Y $or$issuer_ls180.v:175996$12431_Y + end + attribute \src "issuer_ls180.v:175955.7-175955.20" + process $proc$issuer_ls180.v:175955$12437 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "issuer_ls180.v:175977.7-175977.19" + process $proc$issuer_ls180.v:175977$12438 + assign { } { } + assign $1\q_int[0:0] 1'0 + sync always + sync init + update \q_int $1\q_int[0:0] + end + attribute \src "issuer_ls180.v:175998.3-175999.27" + process $proc$issuer_ls180.v:175998$12433 + assign { } { } + assign $0\q_int[0:0] \q_int$next + sync posedge \coresync_clk + update \q_int $0\q_int[0:0] + end + attribute \src "issuer_ls180.v:176000.3-176008.6" + process $proc$issuer_ls180.v:176000$12434 + assign { } { } + assign { } { } + assign $0\q_int$next[0:0]$12435 $1\q_int$next[0:0]$12436 + attribute \src "issuer_ls180.v:176001.5-176001.29" + switch \initial + attribute \src "issuer_ls180.v:176001.9-176001.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\q_int$next[0:0]$12436 1'0 + case + assign $1\q_int$next[0:0]$12436 \$5 + end + sync always + update \q_int$next $0\q_int$next[0:0]$12435 + end + connect \$9 $and$issuer_ls180.v:175990$12425_Y + connect \$11 $or$issuer_ls180.v:175991$12426_Y + connect \$13 $not$issuer_ls180.v:175992$12427_Y + connect \$15 $or$issuer_ls180.v:175993$12428_Y + connect \$1 $not$issuer_ls180.v:175994$12429_Y + connect \$3 $and$issuer_ls180.v:175995$12430_Y + connect \$5 $or$issuer_ls180.v:175996$12431_Y + connect \$7 $not$issuer_ls180.v:175997$12432_Y + connect \qlq_sto \$15 + connect \qn_sto \$13 + connect \q_sto \$11 +end +attribute \src "issuer_ls180.v:176017.1-178754.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer" +attribute \generator "nMigen" +module \test_issuer + attribute \src "issuer_ls180.v:178167.3-178273.6" + wire width 8 $0\core_asmcode$next[7:0]$12619 + attribute \src "issuer_ls180.v:177475.3-177476.41" + wire width 8 $0\core_asmcode[7:0] + attribute \src "issuer_ls180.v:178321.3-178357.6" + wire $0\core_bigendian_i$3$next[0:0]$12852 + attribute \src "issuer_ls180.v:177471.3-177472.55" + wire $0\core_bigendian_i$3[0:0]$12504 + attribute \src "issuer_ls180.v:176150.7-176150.34" + wire $0\core_bigendian_i$3[0:0]$12920 + attribute \src "issuer_ls180.v:178062.3-178074.6" + wire width 4 $0\core_cia__ren[3:0] + attribute \src "issuer_ls180.v:178167.3-178273.6" + wire width 64 $0\core_core_core_cia$next[63:0]$12620 + attribute \src "issuer_ls180.v:177551.3-177552.53" + wire width 64 $0\core_core_core_cia[63:0] + attribute \src "issuer_ls180.v:178167.3-178273.6" + wire width 8 $0\core_core_core_cr_rd$next[7:0]$12621 + attribute \src "issuer_ls180.v:177577.3-177578.57" + wire width 8 $0\core_core_core_cr_rd[7:0] + attribute \src "issuer_ls180.v:178167.3-178273.6" + wire $0\core_core_core_cr_rd_ok$next[0:0]$12622 + attribute \src "issuer_ls180.v:177579.3-177580.63" + wire $0\core_core_core_cr_rd_ok[0:0] + attribute \src "issuer_ls180.v:178167.3-178273.6" + wire width 8 $0\core_core_core_cr_wr$next[7:0]$12623 + attribute \src "issuer_ls180.v:177581.3-177582.57" + wire width 8 $0\core_core_core_cr_wr[7:0] + attribute \src "issuer_ls180.v:178167.3-178273.6" + wire width 12 $0\core_core_core_fn_unit$next[11:0]$12624 + attribute \src "issuer_ls180.v:177557.3-177558.61" + wire width 12 $0\core_core_core_fn_unit[11:0] + attribute \src "issuer_ls180.v:178167.3-178273.6" + wire width 2 $0\core_core_core_input_carry$next[1:0]$12625 + attribute \src "issuer_ls180.v:177571.3-177572.69" + wire width 2 $0\core_core_core_input_carry[1:0] + attribute \src "issuer_ls180.v:178167.3-178273.6" + wire width 32 $0\core_core_core_insn$next[31:0]$12626 + attribute \src "issuer_ls180.v:177553.3-177554.55" + wire width 32 $0\core_core_core_insn[31:0] + attribute \src "issuer_ls180.v:178167.3-178273.6" + wire width 7 $0\core_core_core_insn_type$next[6:0]$12627 + attribute \src "issuer_ls180.v:177555.3-177556.65" + wire width 7 $0\core_core_core_insn_type[6:0] + attribute \src "issuer_ls180.v:178167.3-178273.6" + wire $0\core_core_core_is_32bit$next[0:0]$12628 + attribute \src "issuer_ls180.v:177585.3-177586.63" + wire $0\core_core_core_is_32bit[0:0] + attribute \src "issuer_ls180.v:178167.3-178273.6" + wire width 64 $0\core_core_core_msr$next[63:0]$12629 + attribute \src "issuer_ls180.v:177549.3-177550.53" + wire width 64 $0\core_core_core_msr[63:0] + attribute \src "issuer_ls180.v:178167.3-178273.6" + wire $0\core_core_core_oe$next[0:0]$12630 + attribute \src "issuer_ls180.v:177565.3-177566.51" + wire $0\core_core_core_oe[0:0] + attribute \src "issuer_ls180.v:178167.3-178273.6" + wire $0\core_core_core_oe_ok$next[0:0]$12631 + attribute \src "issuer_ls180.v:177567.3-177568.57" + wire $0\core_core_core_oe_ok[0:0] + attribute \src "issuer_ls180.v:178167.3-178273.6" + wire $0\core_core_core_rc$next[0:0]$12632 + attribute \src "issuer_ls180.v:177561.3-177562.51" + wire $0\core_core_core_rc[0:0] + attribute \src "issuer_ls180.v:178167.3-178273.6" + wire $0\core_core_core_rc_ok$next[0:0]$12633 + attribute \src "issuer_ls180.v:177563.3-177564.57" + wire $0\core_core_core_rc_ok[0:0] + attribute \src "issuer_ls180.v:178167.3-178273.6" + wire width 13 $0\core_core_core_trapaddr$next[12:0]$12634 + attribute \src "issuer_ls180.v:177575.3-177576.63" + wire width 13 $0\core_core_core_trapaddr[12:0] + attribute \src "issuer_ls180.v:178167.3-178273.6" + wire width 7 $0\core_core_core_traptype$next[6:0]$12635 + attribute \src "issuer_ls180.v:177573.3-177574.63" + wire width 7 $0\core_core_core_traptype[6:0] + attribute \src "issuer_ls180.v:178167.3-178273.6" + wire width 3 $0\core_core_cr_in1$next[2:0]$12636 + attribute \src "issuer_ls180.v:177531.3-177532.49" + wire width 3 $0\core_core_cr_in1[2:0] + attribute \src "issuer_ls180.v:178167.3-178273.6" + wire $0\core_core_cr_in1_ok$next[0:0]$12637 + attribute \src "issuer_ls180.v:177533.3-177534.55" + wire $0\core_core_cr_in1_ok[0:0] + attribute \src "issuer_ls180.v:178167.3-178273.6" + wire width 3 $0\core_core_cr_in2$1$next[2:0]$12638 + attribute \src "issuer_ls180.v:177539.3-177540.55" + wire width 3 $0\core_core_cr_in2$1[2:0]$12540 + attribute \src "issuer_ls180.v:176323.13-176323.40" + wire width 3 $0\core_core_cr_in2$1[2:0]$12941 + attribute \src "issuer_ls180.v:178167.3-178273.6" + wire width 3 $0\core_core_cr_in2$next[2:0]$12639 + attribute \src "issuer_ls180.v:177535.3-177536.49" + wire width 3 $0\core_core_cr_in2[2:0] + attribute \src "issuer_ls180.v:178167.3-178273.6" + wire $0\core_core_cr_in2_ok$2$next[0:0]$12640 + attribute \src "issuer_ls180.v:177541.3-177542.61" + wire $0\core_core_cr_in2_ok$2[0:0]$12542 + attribute \src "issuer_ls180.v:176331.7-176331.37" + wire $0\core_core_cr_in2_ok$2[0:0]$12944 + attribute \src "issuer_ls180.v:178167.3-178273.6" + wire $0\core_core_cr_in2_ok$next[0:0]$12641 + attribute \src "issuer_ls180.v:177537.3-177538.55" + wire $0\core_core_cr_in2_ok[0:0] + attribute \src "issuer_ls180.v:178167.3-178273.6" + wire width 3 $0\core_core_cr_out$next[2:0]$12642 + attribute \src "issuer_ls180.v:177543.3-177544.49" + wire width 3 $0\core_core_cr_out[2:0] + attribute \src "issuer_ls180.v:178167.3-178273.6" + wire $0\core_core_cr_wr_ok$next[0:0]$12643 + attribute \src "issuer_ls180.v:177583.3-177584.53" + wire $0\core_core_cr_wr_ok[0:0] + attribute \src "issuer_ls180.v:178167.3-178273.6" + wire width 5 $0\core_core_ea$next[4:0]$12644 + attribute \src "issuer_ls180.v:177483.3-177484.41" + wire width 5 $0\core_core_ea[4:0] + attribute \src "issuer_ls180.v:178167.3-178273.6" + wire width 3 $0\core_core_fast1$next[2:0]$12645 + attribute \src "issuer_ls180.v:177513.3-177514.47" + wire width 3 $0\core_core_fast1[2:0] + attribute \src "issuer_ls180.v:178167.3-178273.6" + wire $0\core_core_fast1_ok$next[0:0]$12646 + attribute \src "issuer_ls180.v:177515.3-177516.53" + wire $0\core_core_fast1_ok[0:0] + attribute \src "issuer_ls180.v:178167.3-178273.6" + wire width 3 $0\core_core_fast2$next[2:0]$12647 + attribute \src "issuer_ls180.v:177517.3-177518.47" + wire width 3 $0\core_core_fast2[2:0] + attribute \src "issuer_ls180.v:178167.3-178273.6" + wire $0\core_core_fast2_ok$next[0:0]$12648 + attribute \src "issuer_ls180.v:177519.3-177520.53" + wire $0\core_core_fast2_ok[0:0] + attribute \src "issuer_ls180.v:178167.3-178273.6" + wire width 3 $0\core_core_fasto1$next[2:0]$12649 + attribute \src "issuer_ls180.v:177521.3-177522.49" + wire width 3 $0\core_core_fasto1[2:0] + attribute \src "issuer_ls180.v:178167.3-178273.6" + wire width 3 $0\core_core_fasto2$next[2:0]$12650 + attribute \src "issuer_ls180.v:177527.3-177528.49" + wire width 3 $0\core_core_fasto2[2:0] + attribute \src "issuer_ls180.v:178167.3-178273.6" + wire $0\core_core_lk$next[0:0]$12651 + attribute \src "issuer_ls180.v:177559.3-177560.41" + wire $0\core_core_lk[0:0] + attribute \src "issuer_ls180.v:178599.3-178630.6" + wire width 64 $0\core_core_pc$next[63:0]$12887 + attribute \src "issuer_ls180.v:177591.3-177592.41" + wire width 64 $0\core_core_pc[63:0] + attribute \src "issuer_ls180.v:178167.3-178273.6" + wire width 5 $0\core_core_reg1$next[4:0]$12652 + attribute \src "issuer_ls180.v:177487.3-177488.45" + wire width 5 $0\core_core_reg1[4:0] + attribute \src "issuer_ls180.v:178167.3-178273.6" + wire $0\core_core_reg1_ok$next[0:0]$12653 + attribute \src "issuer_ls180.v:177489.3-177490.51" + wire $0\core_core_reg1_ok[0:0] + attribute \src "issuer_ls180.v:178167.3-178273.6" + wire width 5 $0\core_core_reg2$next[4:0]$12654 + attribute \src "issuer_ls180.v:177491.3-177492.45" + wire width 5 $0\core_core_reg2[4:0] + attribute \src "issuer_ls180.v:178167.3-178273.6" + wire $0\core_core_reg2_ok$next[0:0]$12655 + attribute \src "issuer_ls180.v:177493.3-177494.51" + wire $0\core_core_reg2_ok[0:0] + attribute \src "issuer_ls180.v:178167.3-178273.6" + wire width 5 $0\core_core_reg3$next[4:0]$12656 + attribute \src "issuer_ls180.v:177495.3-177496.45" + wire width 5 $0\core_core_reg3[4:0] + attribute \src "issuer_ls180.v:178167.3-178273.6" + wire $0\core_core_reg3_ok$next[0:0]$12657 + attribute \src "issuer_ls180.v:177497.3-177498.51" + wire $0\core_core_reg3_ok[0:0] + attribute \src "issuer_ls180.v:178167.3-178273.6" + wire width 5 $0\core_core_rego$next[4:0]$12658 + attribute \src "issuer_ls180.v:177477.3-177478.45" + wire width 5 $0\core_core_rego[4:0] + attribute \src "issuer_ls180.v:178167.3-178273.6" + wire width 10 $0\core_core_spr1$next[9:0]$12659 + attribute \src "issuer_ls180.v:177505.3-177506.45" + wire width 10 $0\core_core_spr1[9:0] + attribute \src "issuer_ls180.v:178167.3-178273.6" + wire $0\core_core_spr1_ok$next[0:0]$12660 + attribute \src "issuer_ls180.v:177507.3-177508.51" + wire $0\core_core_spr1_ok[0:0] + attribute \src "issuer_ls180.v:178167.3-178273.6" + wire width 10 $0\core_core_spro$next[9:0]$12661 + attribute \src "issuer_ls180.v:177499.3-177500.45" + wire width 10 $0\core_core_spro[9:0] + attribute \src "issuer_ls180.v:178167.3-178273.6" + wire width 3 $0\core_core_xer_in$next[2:0]$12662 + attribute \src "issuer_ls180.v:177509.3-177510.49" + wire width 3 $0\core_core_xer_in[2:0] + attribute \src "issuer_ls180.v:178167.3-178273.6" + wire $0\core_cr_out_ok$next[0:0]$12663 + attribute \src "issuer_ls180.v:177545.3-177546.45" + wire $0\core_cr_out_ok[0:0] + attribute \src "issuer_ls180.v:178096.3-178116.6" + wire width 64 $0\core_data_i[63:0] + attribute \src "issuer_ls180.v:178599.3-178630.6" + wire width 64 $0\core_dec$next[63:0]$12888 + attribute \src "issuer_ls180.v:177461.3-177462.33" + wire width 64 $0\core_dec[63:0] + attribute \src "issuer_ls180.v:178686.3-178695.6" + wire width 5 $0\core_dmi__addr[4:0] + attribute \src "issuer_ls180.v:178696.3-178705.6" + wire $0\core_dmi__ren[0:0] + attribute \src "issuer_ls180.v:178167.3-178273.6" + wire $0\core_ea_ok$next[0:0]$12664 + attribute \src "issuer_ls180.v:177485.3-177486.37" + wire $0\core_ea_ok[0:0] + attribute \src "issuer_ls180.v:178599.3-178630.6" + wire $0\core_eint$next[0:0]$12889 + attribute \src "issuer_ls180.v:177601.3-177602.35" + wire $0\core_eint[0:0] + attribute \src "issuer_ls180.v:178167.3-178273.6" + wire $0\core_fasto1_ok$next[0:0]$12665 + attribute \src "issuer_ls180.v:177523.3-177524.45" + wire $0\core_fasto1_ok[0:0] + attribute \src "issuer_ls180.v:178167.3-178273.6" + wire $0\core_fasto2_ok$next[0:0]$12666 + attribute \src "issuer_ls180.v:177529.3-177530.45" + wire $0\core_fasto2_ok[0:0] + attribute \src "issuer_ls180.v:177818.3-177827.6" + wire width 8 $0\core_full_rd2__ren[7:0] + attribute \src "issuer_ls180.v:177857.3-177866.6" + wire width 3 $0\core_full_rd__ren[2:0] + attribute \src "issuer_ls180.v:177965.3-177979.6" + wire width 3 $0\core_issue__addr$4[2:0]$12593 + attribute \src "issuer_ls180.v:177896.3-177910.6" + wire width 3 $0\core_issue__addr[2:0] + attribute \src "issuer_ls180.v:177995.3-178009.6" + wire width 64 $0\core_issue__data_i[63:0] + attribute \src "issuer_ls180.v:177911.3-177925.6" + wire $0\core_issue__ren[0:0] + attribute \src "issuer_ls180.v:177980.3-177994.6" + wire $0\core_issue__wen[0:0] + attribute \src "issuer_ls180.v:178675.3-178685.6" + wire $0\core_issue_i[0:0] + attribute \src "issuer_ls180.v:178655.3-178674.6" + wire $0\core_ivalid_i[0:0] + attribute \src "issuer_ls180.v:178599.3-178630.6" + wire width 64 $0\core_msr$next[63:0]$12890 + attribute \src "issuer_ls180.v:177599.3-177600.33" + wire width 64 $0\core_msr[63:0] + attribute \src "issuer_ls180.v:178126.3-178141.6" + wire width 4 $0\core_msr__ren[3:0] + attribute \src "issuer_ls180.v:178284.3-178320.6" + wire width 32 $0\core_raw_insn_i$next[31:0]$12846 + attribute \src "issuer_ls180.v:177473.3-177474.47" + wire width 32 $0\core_raw_insn_i[31:0] + attribute \src "issuer_ls180.v:178167.3-178273.6" + wire $0\core_rego_ok$next[0:0]$12667 + attribute \src "issuer_ls180.v:177479.3-177480.41" + wire $0\core_rego_ok[0:0] + attribute \src "issuer_ls180.v:178167.3-178273.6" + wire $0\core_spro_ok$next[0:0]$12668 + attribute \src "issuer_ls180.v:177501.3-177502.41" + wire $0\core_spro_ok[0:0] + attribute \src "issuer_ls180.v:178521.3-178539.6" + wire $0\core_stopped_i[0:0] + attribute \src "issuer_ls180.v:178075.3-178095.6" + wire width 4 $0\core_wen[3:0] + attribute \src "issuer_ls180.v:178167.3-178273.6" + wire $0\core_xer_out$next[0:0]$12669 + attribute \src "issuer_ls180.v:177511.3-177512.41" + wire $0\core_xer_out[0:0] + attribute \src "issuer_ls180.v:177593.3-177594.43" + wire $0\cu_st__rel_o_dly[0:0] + attribute \src "issuer_ls180.v:177828.3-177836.6" + wire $0\d_cr_delay$next[0:0]$12575 + attribute \src "issuer_ls180.v:177525.3-177526.37" + wire $0\d_cr_delay[0:0] + attribute \src "issuer_ls180.v:178706.3-178714.6" + wire $0\d_reg_delay$next[0:0]$12913 + attribute \src "issuer_ls180.v:177547.3-177548.39" + wire $0\d_reg_delay[0:0] + attribute \src "issuer_ls180.v:177867.3-177875.6" + wire $0\d_xer_delay$next[0:0]$12581 + attribute \src "issuer_ls180.v:177503.3-177504.39" + wire $0\d_xer_delay[0:0] + attribute \src "issuer_ls180.v:178540.3-178558.6" + wire $0\dbg_core_stopped_i[0:0] + attribute \src "issuer_ls180.v:177847.3-177856.6" + wire $0\dbg_d_cr_ack[0:0] + attribute \src "issuer_ls180.v:177837.3-177846.6" + wire width 64 $0\dbg_d_cr_data[63:0] + attribute \src "issuer_ls180.v:178725.3-178734.6" + wire $0\dbg_d_gpr_ack[0:0] + attribute \src "issuer_ls180.v:178715.3-178724.6" + wire width 64 $0\dbg_d_gpr_data[63:0] + attribute \src "issuer_ls180.v:177886.3-177895.6" + wire $0\dbg_d_xer_ack[0:0] + attribute \src "issuer_ls180.v:177876.3-177885.6" + wire width 64 $0\dbg_d_xer_data[63:0] + attribute \src "issuer_ls180.v:178010.3-178025.6" + wire width 64 $0\dec2_cur_dec$next[63:0]$12598 + attribute \src "issuer_ls180.v:177459.3-177460.41" + wire width 64 $0\dec2_cur_dec[63:0] + attribute \src "issuer_ls180.v:178117.3-178125.6" + wire $0\dec2_cur_eint$next[0:0]$12610 + attribute \src "issuer_ls180.v:177597.3-177598.43" + wire $0\dec2_cur_eint[0:0] + attribute \src "issuer_ls180.v:178559.3-178579.6" + wire width 64 $0\dec2_cur_msr$next[63:0]$12881 + attribute \src "issuer_ls180.v:177463.3-177464.41" + wire width 64 $0\dec2_cur_msr[63:0] + attribute \src "issuer_ls180.v:178424.3-178444.6" + wire width 64 $0\dec2_cur_pc$next[63:0]$12861 + attribute \src "issuer_ls180.v:177469.3-177470.39" + wire width 64 $0\dec2_cur_pc[63:0] + attribute \src "issuer_ls180.v:178580.3-178598.6" + wire width 32 $0\dec2_raw_opcode_in[31:0] + attribute \src "issuer_ls180.v:178274.3-178283.6" + wire width 2 $0\delay$next[1:0]$12843 + attribute \src "issuer_ls180.v:177595.3-177596.27" + wire width 2 $0\delay[1:0] + attribute \src "issuer_ls180.v:177926.3-177953.6" + wire width 2 $0\fsm_state$117$next[1:0]$12588 + attribute \src "issuer_ls180.v:177481.3-177482.45" + wire width 2 $0\fsm_state$117[1:0]$12510 + attribute \src "issuer_ls180.v:177274.13-177274.35" + wire width 2 $0\fsm_state$117[1:0]$12989 + attribute \src "issuer_ls180.v:178475.3-178520.6" + wire width 2 $0\fsm_state$next[1:0]$12872 + attribute \src "issuer_ls180.v:177465.3-177466.35" + wire width 2 $0\fsm_state[1:0] + attribute \src "issuer_ls180.v:178631.3-178654.6" + wire width 32 $0\ilatch$next[31:0]$12904 + attribute \src "issuer_ls180.v:177569.3-177570.29" + wire width 32 $0\ilatch[31:0] + attribute \src "issuer_ls180.v:178358.3-178373.6" + wire width 48 $0\imem_a_pc_i[47:0] + attribute \src "issuer_ls180.v:178374.3-178398.6" + wire $0\imem_a_valid_i[0:0] + attribute \src "issuer_ls180.v:178399.3-178423.6" + wire $0\imem_f_valid_i[0:0] + attribute \src "issuer_ls180.v:176018.7-176018.20" + wire $0\initial[0:0] + attribute \src "issuer_ls180.v:178445.3-178474.6" + wire $0\msr_read$next[0:0]$12866 + attribute \src "issuer_ls180.v:177467.3-177468.33" + wire $0\msr_read[0:0] + attribute \src "issuer_ls180.v:177954.3-177964.6" + wire width 64 $0\new_dec[63:0] + attribute \src "issuer_ls180.v:178026.3-178036.6" + wire width 64 $0\new_tb[63:0] + attribute \src "issuer_ls180.v:178046.3-178061.6" + wire width 64 $0\pc[63:0] + attribute \src "issuer_ls180.v:178142.3-178166.6" + wire $0\pc_changed$next[0:0]$12614 + attribute \src "issuer_ls180.v:177587.3-177588.37" + wire $0\pc_changed[0:0] + attribute \src "issuer_ls180.v:178037.3-178045.6" + wire $0\pc_ok_delay$next[0:0]$12603 + attribute \src "issuer_ls180.v:177589.3-177590.39" + wire $0\pc_ok_delay[0:0] + attribute \src "issuer_ls180.v:178167.3-178273.6" + wire width 8 $1\core_asmcode$next[7:0]$12670 + attribute \src "issuer_ls180.v:176144.13-176144.33" + wire width 8 $1\core_asmcode[7:0] + attribute \src "issuer_ls180.v:178321.3-178357.6" + wire $1\core_bigendian_i$3$next[0:0]$12853 + attribute \src "issuer_ls180.v:178062.3-178074.6" + wire width 4 $1\core_cia__ren[3:0] + attribute \src "issuer_ls180.v:178167.3-178273.6" + wire width 64 $1\core_core_core_cia$next[63:0]$12671 + attribute \src "issuer_ls180.v:176158.14-176158.55" + wire width 64 $1\core_core_core_cia[63:0] + attribute \src "issuer_ls180.v:178167.3-178273.6" + wire width 8 $1\core_core_core_cr_rd$next[7:0]$12672 + attribute \src "issuer_ls180.v:176162.13-176162.41" + wire width 8 $1\core_core_core_cr_rd[7:0] + attribute \src "issuer_ls180.v:178167.3-178273.6" + wire $1\core_core_core_cr_rd_ok$next[0:0]$12673 + attribute \src "issuer_ls180.v:176166.7-176166.37" + wire $1\core_core_core_cr_rd_ok[0:0] + attribute \src "issuer_ls180.v:178167.3-178273.6" + wire width 8 $1\core_core_core_cr_wr$next[7:0]$12674 + attribute \src "issuer_ls180.v:176170.13-176170.41" + wire width 8 $1\core_core_core_cr_wr[7:0] + attribute \src "issuer_ls180.v:178167.3-178273.6" + wire width 12 $1\core_core_core_fn_unit$next[11:0]$12675 + attribute \src "issuer_ls180.v:176187.14-176187.46" + wire width 12 $1\core_core_core_fn_unit[11:0] + attribute \src "issuer_ls180.v:178167.3-178273.6" + wire width 2 $1\core_core_core_input_carry$next[1:0]$12676 + attribute \src "issuer_ls180.v:176195.13-176195.46" + wire width 2 $1\core_core_core_input_carry[1:0] + attribute \src "issuer_ls180.v:178167.3-178273.6" + wire width 32 $1\core_core_core_insn$next[31:0]$12677 + attribute \src "issuer_ls180.v:176199.14-176199.41" + wire width 32 $1\core_core_core_insn[31:0] + attribute \src "issuer_ls180.v:178167.3-178273.6" + wire width 7 $1\core_core_core_insn_type$next[6:0]$12678 + attribute \src "issuer_ls180.v:176277.13-176277.45" + wire width 7 $1\core_core_core_insn_type[6:0] + attribute \src "issuer_ls180.v:178167.3-178273.6" + wire $1\core_core_core_is_32bit$next[0:0]$12679 + attribute \src "issuer_ls180.v:176281.7-176281.37" + wire $1\core_core_core_is_32bit[0:0] + attribute \src "issuer_ls180.v:178167.3-178273.6" + wire width 64 $1\core_core_core_msr$next[63:0]$12680 + attribute \src "issuer_ls180.v:176285.14-176285.55" + wire width 64 $1\core_core_core_msr[63:0] + attribute \src "issuer_ls180.v:178167.3-178273.6" + wire $1\core_core_core_oe$next[0:0]$12681 + attribute \src "issuer_ls180.v:176289.7-176289.31" + wire $1\core_core_core_oe[0:0] + attribute \src "issuer_ls180.v:178167.3-178273.6" + wire $1\core_core_core_oe_ok$next[0:0]$12682 + attribute \src "issuer_ls180.v:176293.7-176293.34" + wire $1\core_core_core_oe_ok[0:0] + attribute \src "issuer_ls180.v:178167.3-178273.6" + wire $1\core_core_core_rc$next[0:0]$12683 + attribute \src "issuer_ls180.v:176297.7-176297.31" + wire $1\core_core_core_rc[0:0] + attribute \src "issuer_ls180.v:178167.3-178273.6" + wire $1\core_core_core_rc_ok$next[0:0]$12684 + attribute \src "issuer_ls180.v:176301.7-176301.34" + wire $1\core_core_core_rc_ok[0:0] + attribute \src "issuer_ls180.v:178167.3-178273.6" + wire width 13 $1\core_core_core_trapaddr$next[12:0]$12685 + attribute \src "issuer_ls180.v:176305.14-176305.48" + wire width 13 $1\core_core_core_trapaddr[12:0] + attribute \src "issuer_ls180.v:178167.3-178273.6" + wire width 7 $1\core_core_core_traptype$next[6:0]$12686 + attribute \src "issuer_ls180.v:176309.13-176309.44" + wire width 7 $1\core_core_core_traptype[6:0] + attribute \src "issuer_ls180.v:178167.3-178273.6" + wire width 3 $1\core_core_cr_in1$next[2:0]$12687 + attribute \src "issuer_ls180.v:176313.13-176313.36" + wire width 3 $1\core_core_cr_in1[2:0] + attribute \src "issuer_ls180.v:178167.3-178273.6" + wire $1\core_core_cr_in1_ok$next[0:0]$12688 + attribute \src "issuer_ls180.v:176317.7-176317.33" + wire $1\core_core_cr_in1_ok[0:0] + attribute \src "issuer_ls180.v:178167.3-178273.6" + wire width 3 $1\core_core_cr_in2$1$next[2:0]$12689 + attribute \src "issuer_ls180.v:178167.3-178273.6" + wire width 3 $1\core_core_cr_in2$next[2:0]$12690 + attribute \src "issuer_ls180.v:176321.13-176321.36" + wire width 3 $1\core_core_cr_in2[2:0] + attribute \src "issuer_ls180.v:178167.3-178273.6" + wire $1\core_core_cr_in2_ok$2$next[0:0]$12691 + attribute \src "issuer_ls180.v:178167.3-178273.6" + wire $1\core_core_cr_in2_ok$next[0:0]$12692 + attribute \src "issuer_ls180.v:176329.7-176329.33" + wire $1\core_core_cr_in2_ok[0:0] + attribute \src "issuer_ls180.v:178167.3-178273.6" + wire width 3 $1\core_core_cr_out$next[2:0]$12693 + attribute \src "issuer_ls180.v:176337.13-176337.36" + wire width 3 $1\core_core_cr_out[2:0] + attribute \src "issuer_ls180.v:178167.3-178273.6" + wire $1\core_core_cr_wr_ok$next[0:0]$12694 + attribute \src "issuer_ls180.v:176341.7-176341.32" + wire $1\core_core_cr_wr_ok[0:0] + attribute \src "issuer_ls180.v:178167.3-178273.6" + wire width 5 $1\core_core_ea$next[4:0]$12695 + attribute \src "issuer_ls180.v:176345.13-176345.33" + wire width 5 $1\core_core_ea[4:0] + attribute \src "issuer_ls180.v:178167.3-178273.6" + wire width 3 $1\core_core_fast1$next[2:0]$12696 + attribute \src "issuer_ls180.v:176349.13-176349.35" + wire width 3 $1\core_core_fast1[2:0] + attribute \src "issuer_ls180.v:178167.3-178273.6" + wire $1\core_core_fast1_ok$next[0:0]$12697 + attribute \src "issuer_ls180.v:176353.7-176353.32" + wire $1\core_core_fast1_ok[0:0] + attribute \src "issuer_ls180.v:178167.3-178273.6" + wire width 3 $1\core_core_fast2$next[2:0]$12698 + attribute \src "issuer_ls180.v:176357.13-176357.35" + wire width 3 $1\core_core_fast2[2:0] + attribute \src "issuer_ls180.v:178167.3-178273.6" + wire $1\core_core_fast2_ok$next[0:0]$12699 + attribute \src "issuer_ls180.v:176361.7-176361.32" + wire $1\core_core_fast2_ok[0:0] + attribute \src "issuer_ls180.v:178167.3-178273.6" + wire width 3 $1\core_core_fasto1$next[2:0]$12700 + attribute \src "issuer_ls180.v:176365.13-176365.36" + wire width 3 $1\core_core_fasto1[2:0] + attribute \src "issuer_ls180.v:178167.3-178273.6" + wire width 3 $1\core_core_fasto2$next[2:0]$12701 + attribute \src "issuer_ls180.v:176369.13-176369.36" + wire width 3 $1\core_core_fasto2[2:0] + attribute \src "issuer_ls180.v:178167.3-178273.6" + wire $1\core_core_lk$next[0:0]$12702 + attribute \src "issuer_ls180.v:176373.7-176373.26" + wire $1\core_core_lk[0:0] + attribute \src "issuer_ls180.v:178599.3-178630.6" + wire width 64 $1\core_core_pc$next[63:0]$12891 + attribute \src "issuer_ls180.v:176377.14-176377.49" + wire width 64 $1\core_core_pc[63:0] + attribute \src "issuer_ls180.v:178167.3-178273.6" + wire width 5 $1\core_core_reg1$next[4:0]$12703 + attribute \src "issuer_ls180.v:176381.13-176381.35" + wire width 5 $1\core_core_reg1[4:0] + attribute \src "issuer_ls180.v:178167.3-178273.6" + wire $1\core_core_reg1_ok$next[0:0]$12704 + attribute \src "issuer_ls180.v:176385.7-176385.31" + wire $1\core_core_reg1_ok[0:0] + attribute \src "issuer_ls180.v:178167.3-178273.6" + wire width 5 $1\core_core_reg2$next[4:0]$12705 + attribute \src "issuer_ls180.v:176389.13-176389.35" + wire width 5 $1\core_core_reg2[4:0] + attribute \src "issuer_ls180.v:178167.3-178273.6" + wire $1\core_core_reg2_ok$next[0:0]$12706 + attribute \src "issuer_ls180.v:176393.7-176393.31" + wire $1\core_core_reg2_ok[0:0] + attribute \src "issuer_ls180.v:178167.3-178273.6" + wire width 5 $1\core_core_reg3$next[4:0]$12707 + attribute \src "issuer_ls180.v:176397.13-176397.35" + wire width 5 $1\core_core_reg3[4:0] + attribute \src "issuer_ls180.v:178167.3-178273.6" + wire $1\core_core_reg3_ok$next[0:0]$12708 + attribute \src "issuer_ls180.v:176401.7-176401.31" + wire $1\core_core_reg3_ok[0:0] + attribute \src "issuer_ls180.v:178167.3-178273.6" + wire width 5 $1\core_core_rego$next[4:0]$12709 + attribute \src "issuer_ls180.v:176405.13-176405.35" + wire width 5 $1\core_core_rego[4:0] + attribute \src "issuer_ls180.v:178167.3-178273.6" + wire width 10 $1\core_core_spr1$next[9:0]$12710 + attribute \src "issuer_ls180.v:176522.13-176522.37" + wire width 10 $1\core_core_spr1[9:0] + attribute \src "issuer_ls180.v:178167.3-178273.6" + wire $1\core_core_spr1_ok$next[0:0]$12711 + attribute \src "issuer_ls180.v:176526.7-176526.31" + wire $1\core_core_spr1_ok[0:0] + attribute \src "issuer_ls180.v:178167.3-178273.6" + wire width 10 $1\core_core_spro$next[9:0]$12712 + attribute \src "issuer_ls180.v:176641.13-176641.37" + wire width 10 $1\core_core_spro[9:0] + attribute \src "issuer_ls180.v:178167.3-178273.6" + wire width 3 $1\core_core_xer_in$next[2:0]$12713 + attribute \src "issuer_ls180.v:176647.13-176647.36" + wire width 3 $1\core_core_xer_in[2:0] + attribute \src "issuer_ls180.v:178167.3-178273.6" + wire $1\core_cr_out_ok$next[0:0]$12714 + attribute \src "issuer_ls180.v:176655.7-176655.28" + wire $1\core_cr_out_ok[0:0] + attribute \src "issuer_ls180.v:178096.3-178116.6" + wire width 64 $1\core_data_i[63:0] + attribute \src "issuer_ls180.v:178599.3-178630.6" + wire width 64 $1\core_dec$next[63:0]$12892 + attribute \src "issuer_ls180.v:176669.14-176669.45" + wire width 64 $1\core_dec[63:0] + attribute \src "issuer_ls180.v:178686.3-178695.6" + wire width 5 $1\core_dmi__addr[4:0] + attribute \src "issuer_ls180.v:178696.3-178705.6" + wire $1\core_dmi__ren[0:0] + attribute \src "issuer_ls180.v:178167.3-178273.6" + wire $1\core_ea_ok$next[0:0]$12715 + attribute \src "issuer_ls180.v:176679.7-176679.24" + wire $1\core_ea_ok[0:0] + attribute \src "issuer_ls180.v:178599.3-178630.6" + wire $1\core_eint$next[0:0]$12893 + attribute \src "issuer_ls180.v:176683.7-176683.23" + wire $1\core_eint[0:0] + attribute \src "issuer_ls180.v:178167.3-178273.6" + wire $1\core_fasto1_ok$next[0:0]$12716 + attribute \src "issuer_ls180.v:176687.7-176687.28" + wire $1\core_fasto1_ok[0:0] + attribute \src "issuer_ls180.v:178167.3-178273.6" + wire $1\core_fasto2_ok$next[0:0]$12717 + attribute \src "issuer_ls180.v:176691.7-176691.28" + wire $1\core_fasto2_ok[0:0] + attribute \src "issuer_ls180.v:177818.3-177827.6" + wire width 8 $1\core_full_rd2__ren[7:0] + attribute \src "issuer_ls180.v:177857.3-177866.6" + wire width 3 $1\core_full_rd__ren[2:0] + attribute \src "issuer_ls180.v:177965.3-177979.6" + wire width 3 $1\core_issue__addr$4[2:0]$12594 + attribute \src "issuer_ls180.v:177896.3-177910.6" + wire width 3 $1\core_issue__addr[2:0] + attribute \src "issuer_ls180.v:177995.3-178009.6" + wire width 64 $1\core_issue__data_i[63:0] + attribute \src "issuer_ls180.v:177911.3-177925.6" + wire $1\core_issue__ren[0:0] + attribute \src "issuer_ls180.v:177980.3-177994.6" + wire $1\core_issue__wen[0:0] + attribute \src "issuer_ls180.v:178675.3-178685.6" + wire $1\core_issue_i[0:0] + attribute \src "issuer_ls180.v:178655.3-178674.6" + wire $1\core_ivalid_i[0:0] + attribute \src "issuer_ls180.v:178599.3-178630.6" + wire width 64 $1\core_msr$next[63:0]$12894 + attribute \src "issuer_ls180.v:176719.14-176719.45" + wire width 64 $1\core_msr[63:0] + attribute \src "issuer_ls180.v:178126.3-178141.6" + wire width 4 $1\core_msr__ren[3:0] + attribute \src "issuer_ls180.v:178284.3-178320.6" + wire width 32 $1\core_raw_insn_i$next[31:0]$12847 + attribute \src "issuer_ls180.v:176727.14-176727.37" + wire width 32 $1\core_raw_insn_i[31:0] + attribute \src "issuer_ls180.v:178167.3-178273.6" + wire $1\core_rego_ok$next[0:0]$12718 + attribute \src "issuer_ls180.v:176731.7-176731.26" + wire $1\core_rego_ok[0:0] + attribute \src "issuer_ls180.v:178167.3-178273.6" + wire $1\core_spro_ok$next[0:0]$12719 + attribute \src "issuer_ls180.v:176735.7-176735.26" + wire $1\core_spro_ok[0:0] + attribute \src "issuer_ls180.v:178521.3-178539.6" + wire $1\core_stopped_i[0:0] + attribute \src "issuer_ls180.v:178075.3-178095.6" + wire width 4 $1\core_wen[3:0] + attribute \src "issuer_ls180.v:178167.3-178273.6" + wire $1\core_xer_out$next[0:0]$12720 + attribute \src "issuer_ls180.v:176745.7-176745.26" + wire $1\core_xer_out[0:0] + attribute \src "issuer_ls180.v:176749.7-176749.30" + wire $1\cu_st__rel_o_dly[0:0] + attribute \src "issuer_ls180.v:177828.3-177836.6" + wire $1\d_cr_delay$next[0:0]$12576 + attribute \src "issuer_ls180.v:176755.7-176755.24" + wire $1\d_cr_delay[0:0] + attribute \src "issuer_ls180.v:178706.3-178714.6" + wire $1\d_reg_delay$next[0:0]$12914 + attribute \src "issuer_ls180.v:176759.7-176759.25" + wire $1\d_reg_delay[0:0] + attribute \src "issuer_ls180.v:177867.3-177875.6" + wire $1\d_xer_delay$next[0:0]$12582 + attribute \src "issuer_ls180.v:176763.7-176763.25" + wire $1\d_xer_delay[0:0] + attribute \src "issuer_ls180.v:178540.3-178558.6" + wire $1\dbg_core_stopped_i[0:0] + attribute \src "issuer_ls180.v:177847.3-177856.6" + wire $1\dbg_d_cr_ack[0:0] + attribute \src "issuer_ls180.v:177837.3-177846.6" + wire width 64 $1\dbg_d_cr_data[63:0] + attribute \src "issuer_ls180.v:178725.3-178734.6" + wire $1\dbg_d_gpr_ack[0:0] + attribute \src "issuer_ls180.v:178715.3-178724.6" + wire width 64 $1\dbg_d_gpr_data[63:0] + attribute \src "issuer_ls180.v:177886.3-177895.6" + wire $1\dbg_d_xer_ack[0:0] + attribute \src "issuer_ls180.v:177876.3-177885.6" + wire width 64 $1\dbg_d_xer_data[63:0] + attribute \src "issuer_ls180.v:178010.3-178025.6" + wire width 64 $1\dec2_cur_dec$next[63:0]$12599 + attribute \src "issuer_ls180.v:176851.14-176851.49" + wire width 64 $1\dec2_cur_dec[63:0] + attribute \src "issuer_ls180.v:178117.3-178125.6" + wire $1\dec2_cur_eint$next[0:0]$12611 + attribute \src "issuer_ls180.v:176855.7-176855.27" + wire $1\dec2_cur_eint[0:0] + attribute \src "issuer_ls180.v:178559.3-178579.6" + wire width 64 $1\dec2_cur_msr$next[63:0]$12882 + attribute \src "issuer_ls180.v:176859.14-176859.49" + wire width 64 $1\dec2_cur_msr[63:0] + attribute \src "issuer_ls180.v:178424.3-178444.6" + wire width 64 $1\dec2_cur_pc$next[63:0]$12862 + attribute \src "issuer_ls180.v:176863.14-176863.48" + wire width 64 $1\dec2_cur_pc[63:0] + attribute \src "issuer_ls180.v:178580.3-178598.6" + wire width 32 $1\dec2_raw_opcode_in[31:0] + attribute \src "issuer_ls180.v:178274.3-178283.6" + wire width 2 $1\delay$next[1:0]$12844 + attribute \src "issuer_ls180.v:177256.13-177256.25" + wire width 2 $1\delay[1:0] + attribute \src "issuer_ls180.v:177926.3-177953.6" + wire width 2 $1\fsm_state$117$next[1:0]$12589 + attribute \src "issuer_ls180.v:178475.3-178520.6" + wire width 2 $1\fsm_state$next[1:0]$12873 + attribute \src "issuer_ls180.v:177272.13-177272.29" + wire width 2 $1\fsm_state[1:0] + attribute \src "issuer_ls180.v:178631.3-178654.6" + wire width 32 $1\ilatch$next[31:0]$12905 + attribute \src "issuer_ls180.v:177346.14-177346.28" + wire width 32 $1\ilatch[31:0] + attribute \src "issuer_ls180.v:178358.3-178373.6" + wire width 48 $1\imem_a_pc_i[47:0] + attribute \src "issuer_ls180.v:178374.3-178398.6" + wire $1\imem_a_valid_i[0:0] + attribute \src "issuer_ls180.v:178399.3-178423.6" + wire $1\imem_f_valid_i[0:0] + attribute \src "issuer_ls180.v:178445.3-178474.6" + wire $1\msr_read$next[0:0]$12867 + attribute \src "issuer_ls180.v:177364.7-177364.22" + wire $1\msr_read[0:0] + attribute \src "issuer_ls180.v:177954.3-177964.6" + wire width 64 $1\new_dec[63:0] + attribute \src "issuer_ls180.v:178026.3-178036.6" + wire width 64 $1\new_tb[63:0] + attribute \src "issuer_ls180.v:178046.3-178061.6" + wire width 64 $1\pc[63:0] + attribute \src "issuer_ls180.v:178142.3-178166.6" + wire $1\pc_changed$next[0:0]$12615 + attribute \src "issuer_ls180.v:177376.7-177376.24" + wire $1\pc_changed[0:0] + attribute \src "issuer_ls180.v:178037.3-178045.6" + wire $1\pc_ok_delay$next[0:0]$12604 + attribute \src "issuer_ls180.v:177386.7-177386.25" + wire $1\pc_ok_delay[0:0] + attribute \src "issuer_ls180.v:178167.3-178273.6" + wire width 8 $2\core_asmcode$next[7:0]$12721 + attribute \src "issuer_ls180.v:178321.3-178357.6" + wire $2\core_bigendian_i$3$next[0:0]$12854 + attribute \src "issuer_ls180.v:178167.3-178273.6" + wire width 64 $2\core_core_core_cia$next[63:0]$12722 + attribute \src "issuer_ls180.v:178167.3-178273.6" + wire width 8 $2\core_core_core_cr_rd$next[7:0]$12723 + attribute \src "issuer_ls180.v:178167.3-178273.6" + wire $2\core_core_core_cr_rd_ok$next[0:0]$12724 + attribute \src "issuer_ls180.v:178167.3-178273.6" + wire width 8 $2\core_core_core_cr_wr$next[7:0]$12725 + attribute \src "issuer_ls180.v:178167.3-178273.6" + wire width 12 $2\core_core_core_fn_unit$next[11:0]$12726 + attribute \src "issuer_ls180.v:178167.3-178273.6" + wire width 2 $2\core_core_core_input_carry$next[1:0]$12727 + attribute \src "issuer_ls180.v:178167.3-178273.6" + wire width 32 $2\core_core_core_insn$next[31:0]$12728 + attribute \src "issuer_ls180.v:178167.3-178273.6" + wire width 7 $2\core_core_core_insn_type$next[6:0]$12729 + attribute \src "issuer_ls180.v:178167.3-178273.6" + wire $2\core_core_core_is_32bit$next[0:0]$12730 + attribute \src "issuer_ls180.v:178167.3-178273.6" + wire width 64 $2\core_core_core_msr$next[63:0]$12731 + attribute \src "issuer_ls180.v:178167.3-178273.6" + wire $2\core_core_core_oe$next[0:0]$12732 + attribute \src "issuer_ls180.v:178167.3-178273.6" + wire $2\core_core_core_oe_ok$next[0:0]$12733 + attribute \src "issuer_ls180.v:178167.3-178273.6" + wire $2\core_core_core_rc$next[0:0]$12734 + attribute \src "issuer_ls180.v:178167.3-178273.6" + wire $2\core_core_core_rc_ok$next[0:0]$12735 + attribute \src "issuer_ls180.v:178167.3-178273.6" + wire width 13 $2\core_core_core_trapaddr$next[12:0]$12736 + attribute \src "issuer_ls180.v:178167.3-178273.6" + wire width 7 $2\core_core_core_traptype$next[6:0]$12737 + attribute \src "issuer_ls180.v:178167.3-178273.6" + wire width 3 $2\core_core_cr_in1$next[2:0]$12738 + attribute \src "issuer_ls180.v:178167.3-178273.6" + wire $2\core_core_cr_in1_ok$next[0:0]$12739 + attribute \src "issuer_ls180.v:178167.3-178273.6" + wire width 3 $2\core_core_cr_in2$1$next[2:0]$12740 + attribute \src "issuer_ls180.v:178167.3-178273.6" + wire width 3 $2\core_core_cr_in2$next[2:0]$12741 + attribute \src "issuer_ls180.v:178167.3-178273.6" + wire $2\core_core_cr_in2_ok$2$next[0:0]$12742 + attribute \src "issuer_ls180.v:178167.3-178273.6" + wire $2\core_core_cr_in2_ok$next[0:0]$12743 + attribute \src "issuer_ls180.v:178167.3-178273.6" + wire width 3 $2\core_core_cr_out$next[2:0]$12744 + attribute \src "issuer_ls180.v:178167.3-178273.6" + wire $2\core_core_cr_wr_ok$next[0:0]$12745 + attribute \src "issuer_ls180.v:178167.3-178273.6" + wire width 5 $2\core_core_ea$next[4:0]$12746 + attribute \src "issuer_ls180.v:178167.3-178273.6" + wire width 3 $2\core_core_fast1$next[2:0]$12747 + attribute \src "issuer_ls180.v:178167.3-178273.6" + wire $2\core_core_fast1_ok$next[0:0]$12748 + attribute \src "issuer_ls180.v:178167.3-178273.6" + wire width 3 $2\core_core_fast2$next[2:0]$12749 + attribute \src "issuer_ls180.v:178167.3-178273.6" + wire $2\core_core_fast2_ok$next[0:0]$12750 + attribute \src "issuer_ls180.v:178167.3-178273.6" + wire width 3 $2\core_core_fasto1$next[2:0]$12751 + attribute \src "issuer_ls180.v:178167.3-178273.6" + wire width 3 $2\core_core_fasto2$next[2:0]$12752 + attribute \src "issuer_ls180.v:178167.3-178273.6" + wire $2\core_core_lk$next[0:0]$12753 + attribute \src "issuer_ls180.v:178599.3-178630.6" + wire width 64 $2\core_core_pc$next[63:0]$12895 + attribute \src "issuer_ls180.v:178167.3-178273.6" + wire width 5 $2\core_core_reg1$next[4:0]$12754 + attribute \src "issuer_ls180.v:178167.3-178273.6" + wire $2\core_core_reg1_ok$next[0:0]$12755 + attribute \src "issuer_ls180.v:178167.3-178273.6" + wire width 5 $2\core_core_reg2$next[4:0]$12756 + attribute \src "issuer_ls180.v:178167.3-178273.6" + wire $2\core_core_reg2_ok$next[0:0]$12757 + attribute \src "issuer_ls180.v:178167.3-178273.6" + wire width 5 $2\core_core_reg3$next[4:0]$12758 + attribute \src "issuer_ls180.v:178167.3-178273.6" + wire $2\core_core_reg3_ok$next[0:0]$12759 + attribute \src "issuer_ls180.v:178167.3-178273.6" + wire width 5 $2\core_core_rego$next[4:0]$12760 + attribute \src "issuer_ls180.v:178167.3-178273.6" + wire width 10 $2\core_core_spr1$next[9:0]$12761 + attribute \src "issuer_ls180.v:178167.3-178273.6" + wire $2\core_core_spr1_ok$next[0:0]$12762 + attribute \src "issuer_ls180.v:178167.3-178273.6" + wire width 10 $2\core_core_spro$next[9:0]$12763 + attribute \src "issuer_ls180.v:178167.3-178273.6" + wire width 3 $2\core_core_xer_in$next[2:0]$12764 + attribute \src "issuer_ls180.v:178167.3-178273.6" + wire $2\core_cr_out_ok$next[0:0]$12765 + attribute \src "issuer_ls180.v:178096.3-178116.6" + wire width 64 $2\core_data_i[63:0] + attribute \src "issuer_ls180.v:178599.3-178630.6" + wire width 64 $2\core_dec$next[63:0]$12896 + attribute \src "issuer_ls180.v:178167.3-178273.6" + wire $2\core_ea_ok$next[0:0]$12766 + attribute \src "issuer_ls180.v:178599.3-178630.6" + wire $2\core_eint$next[0:0]$12897 + attribute \src "issuer_ls180.v:178167.3-178273.6" + wire $2\core_fasto1_ok$next[0:0]$12767 + attribute \src "issuer_ls180.v:178167.3-178273.6" + wire $2\core_fasto2_ok$next[0:0]$12768 + attribute \src "issuer_ls180.v:178655.3-178674.6" + wire $2\core_ivalid_i[0:0] + attribute \src "issuer_ls180.v:178599.3-178630.6" + wire width 64 $2\core_msr$next[63:0]$12898 + attribute \src "issuer_ls180.v:178126.3-178141.6" + wire width 4 $2\core_msr__ren[3:0] + attribute \src "issuer_ls180.v:178284.3-178320.6" + wire width 32 $2\core_raw_insn_i$next[31:0]$12848 + attribute \src "issuer_ls180.v:178167.3-178273.6" + wire $2\core_rego_ok$next[0:0]$12769 + attribute \src "issuer_ls180.v:178167.3-178273.6" + wire $2\core_spro_ok$next[0:0]$12770 + attribute \src "issuer_ls180.v:178521.3-178539.6" + wire $2\core_stopped_i[0:0] + attribute \src "issuer_ls180.v:178075.3-178095.6" + wire width 4 $2\core_wen[3:0] + attribute \src "issuer_ls180.v:178167.3-178273.6" + wire $2\core_xer_out$next[0:0]$12771 + attribute \src "issuer_ls180.v:178540.3-178558.6" + wire $2\dbg_core_stopped_i[0:0] + attribute \src "issuer_ls180.v:178010.3-178025.6" + wire width 64 $2\dec2_cur_dec$next[63:0]$12600 + attribute \src "issuer_ls180.v:178559.3-178579.6" + wire width 64 $2\dec2_cur_msr$next[63:0]$12883 + attribute \src "issuer_ls180.v:178424.3-178444.6" + wire width 64 $2\dec2_cur_pc$next[63:0]$12863 + attribute \src "issuer_ls180.v:178580.3-178598.6" + wire width 32 $2\dec2_raw_opcode_in[31:0] + attribute \src "issuer_ls180.v:177926.3-177953.6" + wire width 2 $2\fsm_state$117$next[1:0]$12590 + attribute \src "issuer_ls180.v:178475.3-178520.6" + wire width 2 $2\fsm_state$next[1:0]$12874 + attribute \src "issuer_ls180.v:178631.3-178654.6" + wire width 32 $2\ilatch$next[31:0]$12906 + attribute \src "issuer_ls180.v:178358.3-178373.6" + wire width 48 $2\imem_a_pc_i[47:0] + attribute \src "issuer_ls180.v:178374.3-178398.6" + wire $2\imem_a_valid_i[0:0] + attribute \src "issuer_ls180.v:178399.3-178423.6" + wire $2\imem_f_valid_i[0:0] + attribute \src "issuer_ls180.v:178445.3-178474.6" + wire $2\msr_read$next[0:0]$12868 + attribute \src "issuer_ls180.v:178046.3-178061.6" + wire width 64 $2\pc[63:0] + attribute \src "issuer_ls180.v:178142.3-178166.6" + wire $2\pc_changed$next[0:0]$12616 + attribute \src "issuer_ls180.v:178167.3-178273.6" + wire width 8 $3\core_asmcode$next[7:0]$12772 + attribute \src "issuer_ls180.v:178321.3-178357.6" + wire $3\core_bigendian_i$3$next[0:0]$12855 + attribute \src "issuer_ls180.v:178167.3-178273.6" + wire width 64 $3\core_core_core_cia$next[63:0]$12773 + attribute \src "issuer_ls180.v:178167.3-178273.6" + wire width 8 $3\core_core_core_cr_rd$next[7:0]$12774 + attribute \src "issuer_ls180.v:178167.3-178273.6" + wire $3\core_core_core_cr_rd_ok$next[0:0]$12775 + attribute \src "issuer_ls180.v:178167.3-178273.6" + wire width 8 $3\core_core_core_cr_wr$next[7:0]$12776 + attribute \src "issuer_ls180.v:178167.3-178273.6" + wire width 12 $3\core_core_core_fn_unit$next[11:0]$12777 + attribute \src "issuer_ls180.v:178167.3-178273.6" + wire width 2 $3\core_core_core_input_carry$next[1:0]$12778 + attribute \src "issuer_ls180.v:178167.3-178273.6" + wire width 32 $3\core_core_core_insn$next[31:0]$12779 + attribute \src "issuer_ls180.v:178167.3-178273.6" + wire width 7 $3\core_core_core_insn_type$next[6:0]$12780 + attribute \src "issuer_ls180.v:178167.3-178273.6" + wire $3\core_core_core_is_32bit$next[0:0]$12781 + attribute \src "issuer_ls180.v:178167.3-178273.6" + wire width 64 $3\core_core_core_msr$next[63:0]$12782 + attribute \src "issuer_ls180.v:178167.3-178273.6" + wire $3\core_core_core_oe$next[0:0]$12783 + attribute \src "issuer_ls180.v:178167.3-178273.6" + wire $3\core_core_core_oe_ok$next[0:0]$12784 + attribute \src "issuer_ls180.v:178167.3-178273.6" + wire $3\core_core_core_rc$next[0:0]$12785 + attribute \src "issuer_ls180.v:178167.3-178273.6" + wire $3\core_core_core_rc_ok$next[0:0]$12786 + attribute \src "issuer_ls180.v:178167.3-178273.6" + wire width 13 $3\core_core_core_trapaddr$next[12:0]$12787 + attribute \src "issuer_ls180.v:178167.3-178273.6" + wire width 7 $3\core_core_core_traptype$next[6:0]$12788 + attribute \src "issuer_ls180.v:178167.3-178273.6" + wire width 3 $3\core_core_cr_in1$next[2:0]$12789 + attribute \src "issuer_ls180.v:178167.3-178273.6" + wire $3\core_core_cr_in1_ok$next[0:0]$12790 + attribute \src "issuer_ls180.v:178167.3-178273.6" + wire width 3 $3\core_core_cr_in2$1$next[2:0]$12791 + attribute \src "issuer_ls180.v:178167.3-178273.6" + wire width 3 $3\core_core_cr_in2$next[2:0]$12792 + attribute \src "issuer_ls180.v:178167.3-178273.6" + wire $3\core_core_cr_in2_ok$2$next[0:0]$12793 + attribute \src "issuer_ls180.v:178167.3-178273.6" + wire $3\core_core_cr_in2_ok$next[0:0]$12794 + attribute \src "issuer_ls180.v:178167.3-178273.6" + wire width 3 $3\core_core_cr_out$next[2:0]$12795 + attribute \src "issuer_ls180.v:178167.3-178273.6" + wire $3\core_core_cr_wr_ok$next[0:0]$12796 + attribute \src "issuer_ls180.v:178167.3-178273.6" + wire width 5 $3\core_core_ea$next[4:0]$12797 + attribute \src "issuer_ls180.v:178167.3-178273.6" + wire width 3 $3\core_core_fast1$next[2:0]$12798 + attribute \src "issuer_ls180.v:178167.3-178273.6" + wire $3\core_core_fast1_ok$next[0:0]$12799 + attribute \src "issuer_ls180.v:178167.3-178273.6" + wire width 3 $3\core_core_fast2$next[2:0]$12800 + attribute \src "issuer_ls180.v:178167.3-178273.6" + wire $3\core_core_fast2_ok$next[0:0]$12801 + attribute \src "issuer_ls180.v:178167.3-178273.6" + wire width 3 $3\core_core_fasto1$next[2:0]$12802 + attribute \src "issuer_ls180.v:178167.3-178273.6" + wire width 3 $3\core_core_fasto2$next[2:0]$12803 + attribute \src "issuer_ls180.v:178167.3-178273.6" + wire $3\core_core_lk$next[0:0]$12804 + attribute \src "issuer_ls180.v:178599.3-178630.6" + wire width 64 $3\core_core_pc$next[63:0]$12899 + attribute \src "issuer_ls180.v:178167.3-178273.6" + wire width 5 $3\core_core_reg1$next[4:0]$12805 + attribute \src "issuer_ls180.v:178167.3-178273.6" + wire $3\core_core_reg1_ok$next[0:0]$12806 + attribute \src "issuer_ls180.v:178167.3-178273.6" + wire width 5 $3\core_core_reg2$next[4:0]$12807 + attribute \src "issuer_ls180.v:178167.3-178273.6" + wire $3\core_core_reg2_ok$next[0:0]$12808 + attribute \src "issuer_ls180.v:178167.3-178273.6" + wire width 5 $3\core_core_reg3$next[4:0]$12809 + attribute \src "issuer_ls180.v:178167.3-178273.6" + wire $3\core_core_reg3_ok$next[0:0]$12810 + attribute \src "issuer_ls180.v:178167.3-178273.6" + wire width 5 $3\core_core_rego$next[4:0]$12811 + attribute \src "issuer_ls180.v:178167.3-178273.6" + wire width 10 $3\core_core_spr1$next[9:0]$12812 + attribute \src "issuer_ls180.v:178167.3-178273.6" + wire $3\core_core_spr1_ok$next[0:0]$12813 + attribute \src "issuer_ls180.v:178167.3-178273.6" + wire width 10 $3\core_core_spro$next[9:0]$12814 + attribute \src "issuer_ls180.v:178167.3-178273.6" + wire width 3 $3\core_core_xer_in$next[2:0]$12815 + attribute \src "issuer_ls180.v:178167.3-178273.6" + wire $3\core_cr_out_ok$next[0:0]$12816 + attribute \src "issuer_ls180.v:178096.3-178116.6" + wire width 64 $3\core_data_i[63:0] + attribute \src "issuer_ls180.v:178599.3-178630.6" + wire width 64 $3\core_dec$next[63:0]$12900 + attribute \src "issuer_ls180.v:178167.3-178273.6" + wire $3\core_ea_ok$next[0:0]$12817 + attribute \src "issuer_ls180.v:178599.3-178630.6" + wire $3\core_eint$next[0:0]$12901 + attribute \src "issuer_ls180.v:178167.3-178273.6" + wire $3\core_fasto1_ok$next[0:0]$12818 + attribute \src "issuer_ls180.v:178167.3-178273.6" + wire $3\core_fasto2_ok$next[0:0]$12819 + attribute \src "issuer_ls180.v:178599.3-178630.6" + wire width 64 $3\core_msr$next[63:0]$12902 + attribute \src "issuer_ls180.v:178284.3-178320.6" + wire width 32 $3\core_raw_insn_i$next[31:0]$12849 + attribute \src "issuer_ls180.v:178167.3-178273.6" + wire $3\core_rego_ok$next[0:0]$12820 + attribute \src "issuer_ls180.v:178167.3-178273.6" + wire $3\core_spro_ok$next[0:0]$12821 + attribute \src "issuer_ls180.v:178075.3-178095.6" + wire width 4 $3\core_wen[3:0] + attribute \src "issuer_ls180.v:178167.3-178273.6" + wire $3\core_xer_out$next[0:0]$12822 + attribute \src "issuer_ls180.v:178559.3-178579.6" + wire width 64 $3\dec2_cur_msr$next[63:0]$12884 + attribute \src "issuer_ls180.v:178424.3-178444.6" + wire width 64 $3\dec2_cur_pc$next[63:0]$12864 + attribute \src "issuer_ls180.v:178475.3-178520.6" + wire width 2 $3\fsm_state$next[1:0]$12875 + attribute \src "issuer_ls180.v:178631.3-178654.6" + wire width 32 $3\ilatch$next[31:0]$12907 + attribute \src "issuer_ls180.v:178374.3-178398.6" + wire $3\imem_a_valid_i[0:0] + attribute \src "issuer_ls180.v:178399.3-178423.6" + wire $3\imem_f_valid_i[0:0] + attribute \src "issuer_ls180.v:178445.3-178474.6" + wire $3\msr_read$next[0:0]$12869 + attribute \src "issuer_ls180.v:178142.3-178166.6" + wire $3\pc_changed$next[0:0]$12617 + attribute \src "issuer_ls180.v:178321.3-178357.6" + wire $4\core_bigendian_i$3$next[0:0]$12856 + attribute \src "issuer_ls180.v:178167.3-178273.6" + wire $4\core_core_core_cr_rd_ok$next[0:0]$12823 + attribute \src "issuer_ls180.v:178167.3-178273.6" + wire $4\core_core_core_oe_ok$next[0:0]$12824 + attribute \src "issuer_ls180.v:178167.3-178273.6" + wire $4\core_core_core_rc_ok$next[0:0]$12825 + attribute \src "issuer_ls180.v:178167.3-178273.6" + wire $4\core_core_cr_in1_ok$next[0:0]$12826 + attribute \src "issuer_ls180.v:178167.3-178273.6" + wire $4\core_core_cr_in2_ok$2$next[0:0]$12827 + attribute \src "issuer_ls180.v:178167.3-178273.6" + wire $4\core_core_cr_in2_ok$next[0:0]$12828 + attribute \src "issuer_ls180.v:178167.3-178273.6" + wire $4\core_core_cr_wr_ok$next[0:0]$12829 + attribute \src "issuer_ls180.v:178167.3-178273.6" + wire $4\core_core_fast1_ok$next[0:0]$12830 + attribute \src "issuer_ls180.v:178167.3-178273.6" + wire $4\core_core_fast2_ok$next[0:0]$12831 + attribute \src "issuer_ls180.v:178167.3-178273.6" + wire $4\core_core_reg1_ok$next[0:0]$12832 + attribute \src "issuer_ls180.v:178167.3-178273.6" + wire $4\core_core_reg2_ok$next[0:0]$12833 + attribute \src "issuer_ls180.v:178167.3-178273.6" + wire $4\core_core_reg3_ok$next[0:0]$12834 + attribute \src "issuer_ls180.v:178167.3-178273.6" + wire $4\core_core_spr1_ok$next[0:0]$12835 + attribute \src "issuer_ls180.v:178167.3-178273.6" + wire $4\core_cr_out_ok$next[0:0]$12836 + attribute \src "issuer_ls180.v:178167.3-178273.6" + wire $4\core_ea_ok$next[0:0]$12837 + attribute \src "issuer_ls180.v:178167.3-178273.6" + wire $4\core_fasto1_ok$next[0:0]$12838 + attribute \src "issuer_ls180.v:178167.3-178273.6" + wire $4\core_fasto2_ok$next[0:0]$12839 + attribute \src "issuer_ls180.v:178284.3-178320.6" + wire width 32 $4\core_raw_insn_i$next[31:0]$12850 + attribute \src "issuer_ls180.v:178167.3-178273.6" + wire $4\core_rego_ok$next[0:0]$12840 + attribute \src "issuer_ls180.v:178167.3-178273.6" + wire $4\core_spro_ok$next[0:0]$12841 + attribute \src "issuer_ls180.v:178475.3-178520.6" + wire width 2 $4\fsm_state$next[1:0]$12876 + attribute \src "issuer_ls180.v:178445.3-178474.6" + wire $4\msr_read$next[0:0]$12870 + attribute \src "issuer_ls180.v:178475.3-178520.6" + wire width 2 $5\fsm_state$next[1:0]$12877 + attribute \src "issuer_ls180.v:177414.19-177414.115" + wire width 65 $add$issuer_ls180.v:177414$12452_Y + attribute \src "issuer_ls180.v:177419.18-177419.107" + wire width 65 $add$issuer_ls180.v:177419$12457_Y + attribute \src "issuer_ls180.v:177403.18-177403.101" + wire $and$issuer_ls180.v:177403$12439_Y + attribute \src "issuer_ls180.v:177418.18-177418.109" + wire $and$issuer_ls180.v:177418$12456_Y + attribute \src "issuer_ls180.v:177427.18-177427.101" + wire $and$issuer_ls180.v:177427$12465_Y + attribute \src "issuer_ls180.v:177428.18-177428.114" + wire width 4 $and$issuer_ls180.v:177428$12466_Y + attribute \src "issuer_ls180.v:177435.18-177435.101" + wire $and$issuer_ls180.v:177435$12473_Y + attribute \src "issuer_ls180.v:177438.18-177438.101" + wire $and$issuer_ls180.v:177438$12476_Y + attribute \src "issuer_ls180.v:177441.18-177441.101" + wire $and$issuer_ls180.v:177441$12479_Y + attribute \src "issuer_ls180.v:177444.18-177444.101" + wire $and$issuer_ls180.v:177444$12482_Y + attribute \src "issuer_ls180.v:177447.18-177447.101" + wire $and$issuer_ls180.v:177447$12485_Y + attribute \src "issuer_ls180.v:177452.18-177452.101" + wire $and$issuer_ls180.v:177452$12490_Y + attribute \src "issuer_ls180.v:177456.18-177456.101" + wire $and$issuer_ls180.v:177456$12494_Y + attribute \src "issuer_ls180.v:177411.19-177411.114" + wire width 64 $extend$issuer_ls180.v:177411$12447_Y + attribute \src "issuer_ls180.v:177412.19-177412.113" + wire width 64 $extend$issuer_ls180.v:177412$12449_Y + attribute \src "issuer_ls180.v:177405.19-177405.111" + wire width 7 $mul$issuer_ls180.v:177405$12441_Y + attribute \src "issuer_ls180.v:177407.19-177407.111" + wire width 7 $mul$issuer_ls180.v:177407$12443_Y + attribute \src "issuer_ls180.v:177410.19-177410.123" + wire $ne$issuer_ls180.v:177410$12446_Y + attribute \src "issuer_ls180.v:177416.18-177416.102" + wire $ne$issuer_ls180.v:177416$12454_Y + attribute \src "issuer_ls180.v:177448.17-177448.101" + wire $ne$issuer_ls180.v:177448$12486_Y + attribute \src "issuer_ls180.v:177404.19-177404.100" + wire $not$issuer_ls180.v:177404$12440_Y + attribute \src "issuer_ls180.v:177417.18-177417.103" + wire $not$issuer_ls180.v:177417$12455_Y + attribute \src "issuer_ls180.v:177420.18-177420.98" + wire $not$issuer_ls180.v:177420$12458_Y + attribute \src "issuer_ls180.v:177421.18-177421.106" + wire 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"/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:102" + wire width 3 \dec2_xer_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:103" + wire \dec2_xer_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:144" + wire width 2 \delay + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:144" + wire width 2 \delay$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:62" + wire output 13 \dmi_ack_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:57" + wire width 4 input 8 \dmi_addr_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:58" + wire width 64 input 9 \dmi_din + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:59" + wire width 64 output 10 \dmi_dout + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:60" + wire input 11 \dmi_req_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:61" + wire input 12 \dmi_we_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:214" + wire width 2 \fsm_state + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:350" + wire width 2 \fsm_state$117 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:350" + wire width 2 \fsm_state$117$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:214" + wire width 2 \fsm_state$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" + wire input 20 \ibus__ack + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" + wire width 45 output 14 \ibus__adr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" + wire width 2 input 23 \ibus__bte + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" + wire width 3 input 22 \ibus__cti + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" + wire output 18 \ibus__cyc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" + wire width 64 input 16 \ibus__dat_r + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" + wire width 64 input 15 \ibus__dat_w + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" + wire input 24 \ibus__err + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" + wire width 8 output 17 \ibus__sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" + wire output 19 \ibus__stb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" + wire input 21 \ibus__we + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" + wire output 42 \icp_wb__ack + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" + wire width 28 input 36 \icp_wb__adr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" + wire width 2 input 45 \icp_wb__bte + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" + wire width 3 input 44 \icp_wb__cti + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" + wire input 40 \icp_wb__cyc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" + wire width 32 output 38 \icp_wb__dat_r + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" + wire width 32 input 37 \icp_wb__dat_w + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" + wire input 46 \icp_wb__err + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" + wire width 4 input 39 \icp_wb__sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" + wire input 41 \icp_wb__stb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" + wire input 43 \icp_wb__we + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" + wire output 53 \ics_wb__ack + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" + wire width 28 input 47 \ics_wb__adr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" + wire width 2 input 56 \ics_wb__bte + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" + wire width 3 input 55 \ics_wb__cti + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" + wire input 51 \ics_wb__cyc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" + wire width 32 output 49 \ics_wb__dat_r + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" + wire width 32 input 48 \ics_wb__dat_w + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" + wire input 57 \ics_wb__err + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" + wire width 4 input 50 \ics_wb__sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" + wire input 52 \ics_wb__stb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:235" + wire input 54 \ics_wb__we + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:166" + wire width 32 \ilatch + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:166" + wire width 32 \ilatch$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:24" + wire width 48 \imem_a_pc_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:26" + wire \imem_a_valid_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:32" + wire \imem_f_busy_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:33" + wire width 64 \imem_f_instr_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:28" + wire \imem_f_valid_i + attribute \src "issuer_ls180.v:176018.7-176018.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:237" + wire width 16 input 58 \int_level_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:85" + wire input 3 \memerr_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:192" + wire \msr_read + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:192" + wire \msr_read$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:360" + wire width 64 \new_dec + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:377" + wire width 64 \new_tb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:169" + wire width 64 \nia + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:173" + wire width 64 \pc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:164" + wire \pc_changed + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:164" + wire \pc_changed$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire width 64 input 59 \pc_i + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" + wire input 1 \pc_i_ok + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:81" + wire width 64 output 2 \pc_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:174" + wire \pc_ok_delay + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:174" + wire \pc_ok_delay$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:139" + wire \por_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:140" + wire input 7 \rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:83" + wire \xics_icp_core_irq_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:46" + wire width 8 \xics_icp_ics_i_pri + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:45" + wire width 4 \xics_icp_ics_i_src + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:46" + wire width 8 \xics_ics_icp_o_pri + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:45" + wire width 4 \xics_ics_icp_o_src + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:378" + cell $add $add$issuer_ls180.v:177414$12452 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 65 + connect \A \core_issue__data_o + connect \B 1'1 + connect \Y $add$issuer_ls180.v:177414$12452_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:170" + cell $add $add$issuer_ls180.v:177419$12457 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 3 + parameter \Y_WIDTH 65 + connect \A \dec2_cur_pc + connect \B 3'100 + connect \Y $add$issuer_ls180.v:177419$12457_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:222" + cell $and $and$issuer_ls180.v:177403$12439 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$95 + connect \B \$97 + connect \Y $and$issuer_ls180.v:177403$12439_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + cell $and $and$issuer_ls180.v:177418$12456 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \core_cu_st__rel_o + connect \B \$16 + connect \Y $and$issuer_ls180.v:177418$12456_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:222" + cell $and $and$issuer_ls180.v:177427$12465 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$33 + connect \B \$35 + connect \Y $and$issuer_ls180.v:177427$12465_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:278" + cell $and $and$issuer_ls180.v:177428$12466 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 4 + connect \A \core_state_nia_wen + connect \B 1'1 + connect \Y $and$issuer_ls180.v:177428$12466_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:222" + cell $and $and$issuer_ls180.v:177435$12473 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$49 + connect \B \$51 + connect \Y $and$issuer_ls180.v:177435$12473_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:222" + cell $and $and$issuer_ls180.v:177438$12476 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$55 + connect \B \$57 + connect \Y $and$issuer_ls180.v:177438$12476_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:222" + cell $and $and$issuer_ls180.v:177441$12479 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$61 + connect \B \$63 + connect \Y $and$issuer_ls180.v:177441$12479_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:222" + cell $and $and$issuer_ls180.v:177444$12482 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$67 + connect \B \$69 + connect \Y $and$issuer_ls180.v:177444$12482_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:222" + cell $and $and$issuer_ls180.v:177447$12485 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$73 + connect \B \$75 + connect \Y $and$issuer_ls180.v:177447$12485_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:222" + cell $and $and$issuer_ls180.v:177452$12490 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$81 + connect \B \$83 + connect \Y $and$issuer_ls180.v:177452$12490_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:222" + cell $and $and$issuer_ls180.v:177456$12494 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$89 + connect \B \$91 + connect \Y $and$issuer_ls180.v:177456$12494_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + cell $pos $extend$issuer_ls180.v:177411$12447 + parameter \A_SIGNED 0 + parameter \A_WIDTH 32 + parameter \Y_WIDTH 64 + connect \A \core_full_rd2__data_o + connect \Y $extend$issuer_ls180.v:177411$12447_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + cell $pos $extend$issuer_ls180.v:177412$12449 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \Y_WIDTH 64 + connect \A \core_full_rd__data_o + connect \Y $extend$issuer_ls180.v:177412$12449_Y + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/back/rtlil.py:609" + cell $mul $mul$issuer_ls180.v:177405$12441 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 7 + connect \A \dec2_cur_pc [2] + connect \B 6'100000 + connect \Y $mul$issuer_ls180.v:177405$12441_Y + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/back/rtlil.py:609" + cell $mul $mul$issuer_ls180.v:177407$12443 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 6 + parameter \Y_WIDTH 7 + connect \A \dec2_cur_pc [2] + connect \B 6'100000 + connect \Y $mul$issuer_ls180.v:177407$12443_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:276" + cell $ne $ne$issuer_ls180.v:177410$12446 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A \core_core_core_insn_type + connect \B 7'0000001 + connect \Y $ne$issuer_ls180.v:177410$12446_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:150" + cell $ne $ne$issuer_ls180.v:177416$12454 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \delay + connect \B \$12 + connect \Y $ne$issuer_ls180.v:177416$12454_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:145" + cell $ne $ne$issuer_ls180.v:177448$12486 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \delay + connect \B 1'0 + connect \Y $ne$issuer_ls180.v:177448$12486_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:244" + cell $not $not$issuer_ls180.v:177404$12440 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \msr_read + connect \Y $not$issuer_ls180.v:177404$12440_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + cell $not $not$issuer_ls180.v:177417$12455 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cu_st__rel_o_dly + connect \Y $not$issuer_ls180.v:177417$12455_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:175" + cell $not $not$issuer_ls180.v:177420$12458 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \pc_i_ok + connect \Y $not$issuer_ls180.v:177420$12458_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:280" + cell $not $not$issuer_ls180.v:177421$12459 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \core_corebusy_o + connect \Y $not$issuer_ls180.v:177421$12459_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:284" + cell $not $not$issuer_ls180.v:177422$12460 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \pc_changed + connect \Y $not$issuer_ls180.v:177422$12460_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:280" + cell $not $not$issuer_ls180.v:177423$12461 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \core_corebusy_o + connect \Y $not$issuer_ls180.v:177423$12461_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:284" + cell $not $not$issuer_ls180.v:177424$12462 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \pc_changed + connect \Y $not$issuer_ls180.v:177424$12462_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:222" + cell $not $not$issuer_ls180.v:177425$12463 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dbg_core_stop_o + connect \Y $not$issuer_ls180.v:177425$12463_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:222" + cell $not $not$issuer_ls180.v:177426$12464 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \core_core_reset_i + connect \Y $not$issuer_ls180.v:177426$12464_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:280" + cell $not $not$issuer_ls180.v:177430$12468 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \core_corebusy_o + connect \Y $not$issuer_ls180.v:177430$12468_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:280" + cell $not $not$issuer_ls180.v:177431$12469 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \core_corebusy_o + connect \Y $not$issuer_ls180.v:177431$12469_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:280" + cell $not $not$issuer_ls180.v:177432$12470 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \core_corebusy_o + connect \Y $not$issuer_ls180.v:177432$12470_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:222" + cell $not $not$issuer_ls180.v:177433$12471 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dbg_core_stop_o + connect \Y $not$issuer_ls180.v:177433$12471_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:222" + cell $not $not$issuer_ls180.v:177434$12472 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \core_core_reset_i + connect \Y $not$issuer_ls180.v:177434$12472_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:222" + cell $not $not$issuer_ls180.v:177436$12474 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dbg_core_stop_o + connect \Y $not$issuer_ls180.v:177436$12474_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:222" + cell $not $not$issuer_ls180.v:177437$12475 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \core_core_reset_i + connect \Y $not$issuer_ls180.v:177437$12475_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:222" + cell $not $not$issuer_ls180.v:177439$12477 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dbg_core_stop_o + connect \Y $not$issuer_ls180.v:177439$12477_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:222" + cell $not $not$issuer_ls180.v:177440$12478 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \core_core_reset_i + connect \Y $not$issuer_ls180.v:177440$12478_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:222" + cell $not $not$issuer_ls180.v:177442$12480 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dbg_core_stop_o + connect \Y $not$issuer_ls180.v:177442$12480_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:222" + cell $not $not$issuer_ls180.v:177443$12481 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \core_core_reset_i + connect \Y $not$issuer_ls180.v:177443$12481_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:222" + cell $not $not$issuer_ls180.v:177445$12483 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dbg_core_stop_o + connect \Y $not$issuer_ls180.v:177445$12483_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:222" + cell $not $not$issuer_ls180.v:177446$12484 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \core_core_reset_i + connect \Y $not$issuer_ls180.v:177446$12484_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:244" + cell $not $not$issuer_ls180.v:177449$12487 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \msr_read + connect \Y $not$issuer_ls180.v:177449$12487_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:222" + cell $not $not$issuer_ls180.v:177450$12488 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dbg_core_stop_o + connect \Y $not$issuer_ls180.v:177450$12488_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:222" + cell $not $not$issuer_ls180.v:177451$12489 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \core_core_reset_i + connect \Y $not$issuer_ls180.v:177451$12489_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:280" + cell $not $not$issuer_ls180.v:177453$12491 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \core_corebusy_o + connect \Y $not$issuer_ls180.v:177453$12491_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:222" + cell $not $not$issuer_ls180.v:177454$12492 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dbg_core_stop_o + connect \Y $not$issuer_ls180.v:177454$12492_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:222" + cell $not $not$issuer_ls180.v:177455$12493 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \core_core_reset_i + connect \Y $not$issuer_ls180.v:177455$12493_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:222" + cell $not $not$issuer_ls180.v:177457$12495 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \dbg_core_stop_o + connect \Y $not$issuer_ls180.v:177457$12495_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:222" + cell $not $not$issuer_ls180.v:177458$12496 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \core_core_reset_i + connect \Y $not$issuer_ls180.v:177458$12496_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:150" + cell $or $or$issuer_ls180.v:177415$12453 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A 1'0 + connect \B \dbg_core_rst_o + connect \Y $or$issuer_ls180.v:177415$12453_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + cell $pos $pos$issuer_ls180.v:177411$12448 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A $extend$issuer_ls180.v:177411$12447_Y + connect \Y $pos$issuer_ls180.v:177411$12448_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + cell $pos $pos$issuer_ls180.v:177412$12450 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \Y_WIDTH 64 + connect \A $extend$issuer_ls180.v:177412$12449_Y + connect \Y $pos$issuer_ls180.v:177412$12450_Y + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" + cell $reduce_or $reduce_or$issuer_ls180.v:177429$12467 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \$40 + connect \Y $reduce_or$issuer_ls180.v:177429$12467_Y + end + attribute \src "issuer_ls180.v:177406.19-177406.42" + cell $shr $shr$issuer_ls180.v:177406$12442 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 64 + connect \A \imem_f_instr_o + connect \B \$104 + connect \Y $shr$issuer_ls180.v:177406$12442_Y + end + attribute \src "issuer_ls180.v:177409.19-177409.42" + cell $shr $shr$issuer_ls180.v:177409$12445 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 7 + parameter \Y_WIDTH 64 + connect \A \imem_f_instr_o + connect \B \$108 + connect \Y $shr$issuer_ls180.v:177409$12445_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:146" + cell $sub $sub$issuer_ls180.v:177408$12444 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 3 + connect \A \delay + connect \B 1'1 + connect \Y $sub$issuer_ls180.v:177408$12444_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:362" + cell $sub $sub$issuer_ls180.v:177413$12451 + parameter \A_SIGNED 0 + parameter \A_WIDTH 64 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 65 + connect \A \core_issue__data_o + connect \B 1'1 + connect \Y $sub$issuer_ls180.v:177413$12451_Y + end + attribute \module_not_derived 1 + attribute \src "issuer_ls180.v:177603.8-177687.4" + cell \core \core + connect \bigendian_i \core_bigendian_i$3 + connect \cia__data_o \core_cia__data_o + connect \cia__ren \core_cia__ren + connect \core_core_cia \core_core_core_cia + connect \core_core_cr_rd \core_core_core_cr_rd + connect \core_core_cr_rd_ok \core_core_core_cr_rd_ok + connect \core_core_cr_wr \core_core_core_cr_wr + connect \core_core_fn_unit \core_core_core_fn_unit + connect \core_core_input_carry \core_core_core_input_carry + connect \core_core_insn \core_core_core_insn + connect \core_core_insn_type \core_core_core_insn_type + connect \core_core_is_32bit \core_core_core_is_32bit + connect \core_core_msr \core_core_core_msr + connect \core_core_oe \core_core_core_oe + connect \core_core_oe_ok \core_core_core_oe_ok + connect \core_core_rc \core_core_core_rc + connect \core_core_rc_ok \core_core_core_rc_ok + connect \core_core_trapaddr \core_core_core_trapaddr + connect \core_core_traptype \core_core_core_traptype + connect \core_cr_in1 \core_core_cr_in1 + connect \core_cr_in1_ok \core_core_cr_in1_ok + connect \core_cr_in2 \core_core_cr_in2 + connect \core_cr_in2$1 \core_core_cr_in2$1 + connect \core_cr_in2_ok \core_core_cr_in2_ok + connect \core_cr_in2_ok$2 \core_core_cr_in2_ok$2 + connect \core_cr_out \core_core_cr_out + connect \core_ea \core_core_ea + connect \core_fast1 \core_core_fast1 + connect \core_fast1_ok \core_core_fast1_ok + connect \core_fast2 \core_core_fast2 + connect \core_fast2_ok \core_core_fast2_ok + connect \core_fasto1 \core_core_fasto1 + connect \core_fasto2 \core_core_fasto2 + connect \core_pc \core_core_pc + connect \core_reg1 \core_core_reg1 + connect \core_reg1_ok \core_core_reg1_ok + connect \core_reg2 \core_core_reg2 + connect \core_reg2_ok \core_core_reg2_ok + connect \core_reg3 \core_core_reg3 + connect \core_reg3_ok \core_core_reg3_ok + connect \core_rego \core_core_rego + connect \core_reset_i \core_core_reset_i + connect \core_spr1 \core_core_spr1 + connect \core_spr1_ok \core_core_spr1_ok + connect \core_spro \core_core_spro + connect \core_terminate_o \core_core_terminate_o + connect \core_xer_in \core_core_xer_in + connect \corebusy_o \core_corebusy_o + connect \coresync_clk \core_coresync_clk + connect \cu_ad__go_i \core_cu_ad__go_i + connect \cu_ad__rel_o \core_cu_ad__rel_o + connect \cu_st__go_i \core_cu_st__go_i + connect \cu_st__rel_o \core_cu_st__rel_o + connect \data_i \core_data_i + connect \dbus__ack \dbus__ack + connect \dbus__adr \dbus__adr + connect \dbus__cyc \dbus__cyc + connect \dbus__dat_r \dbus__dat_r + connect \dbus__dat_w \dbus__dat_w + connect \dbus__err \dbus__err + connect \dbus__sel \dbus__sel + connect \dbus__stb \dbus__stb + connect \dbus__we \dbus__we + connect \dmi__addr \core_dmi__addr + connect \dmi__data_o \core_dmi__data_o + connect \dmi__ren \core_dmi__ren + connect \full_rd2__data_o \core_full_rd2__data_o + connect \full_rd2__ren \core_full_rd2__ren + connect \full_rd__data_o \core_full_rd__data_o + connect \full_rd__ren \core_full_rd__ren + connect \issue__addr \core_issue__addr + connect \issue__addr$3 \core_issue__addr$4 + connect \issue__data_i \core_issue__data_i + connect \issue__data_o \core_issue__data_o + connect \issue__ren \core_issue__ren + connect \issue__wen \core_issue__wen + connect \issue_i \core_issue_i + connect \ivalid_i \core_ivalid_i + connect \msr__data_o \core_msr__data_o + connect \msr__ren \core_msr__ren + connect \raw_insn_i \core_raw_insn_i + connect \state_nia_wen \core_state_nia_wen + connect \wen \core_wen + end + attribute \module_not_derived 1 + attribute \src "issuer_ls180.v:177688.7-177713.4" + cell \dbg \dbg + connect \clk \clk + connect \core_dbg_msr \dbg_core_dbg_msr + connect \core_dbg_pc \dbg_core_dbg_pc + connect \core_rst_o \dbg_core_rst_o + connect \core_stop_o \dbg_core_stop_o + connect \core_stopped_i \dbg_core_stopped_i + connect \d_cr_ack \dbg_d_cr_ack + connect \d_cr_data \dbg_d_cr_data + connect \d_cr_req \dbg_d_cr_req + connect \d_gpr_ack \dbg_d_gpr_ack + connect \d_gpr_addr \dbg_d_gpr_addr + connect \d_gpr_data \dbg_d_gpr_data + connect \d_gpr_req \dbg_d_gpr_req + connect \d_xer_ack \dbg_d_xer_ack + connect \d_xer_data \dbg_d_xer_data + connect \d_xer_req \dbg_d_xer_req + connect \dmi_ack_o \dmi_ack_o + connect \dmi_addr_i \dmi_addr_i + connect \dmi_din \dmi_din + connect \dmi_dout \dmi_dout + connect \dmi_req_i \dmi_req_i + connect \dmi_we_i \dmi_we_i + connect \rst \rst + connect \terminate_i \dbg_terminate_i + end + attribute \module_not_derived 1 + attribute \src "issuer_ls180.v:177714.8-177772.4" + cell \dec2 \dec2 + connect \asmcode \dec2_asmcode + connect \bigendian \dec2_bigendian + connect \cia \dec2_cia + connect \cr_in1 \dec2_cr_in1 + connect \cr_in1_ok \dec2_cr_in1_ok + connect \cr_in2 \dec2_cr_in2 + connect \cr_in2$1 \dec2_cr_in2$5 + connect \cr_in2_ok \dec2_cr_in2_ok + connect \cr_in2_ok$2 \dec2_cr_in2_ok$6 + connect \cr_out \dec2_cr_out + connect \cr_out_ok \dec2_cr_out_ok + connect \cr_rd \dec2_cr_rd + connect \cr_rd_ok \dec2_cr_rd_ok + connect \cr_wr \dec2_cr_wr + connect \cr_wr_ok \dec2_cr_wr_ok + connect \cur_dec \dec2_cur_dec + connect \cur_eint \dec2_cur_eint + connect \cur_msr \dec2_cur_msr + connect \cur_pc \dec2_cur_pc + connect \ea \dec2_ea + connect \ea_ok \dec2_ea_ok + connect \fast1 \dec2_fast1 + connect \fast1_ok \dec2_fast1_ok + connect \fast2 \dec2_fast2 + connect \fast2_ok \dec2_fast2_ok + connect \fasto1 \dec2_fasto1 + connect \fasto1_ok \dec2_fasto1_ok + connect \fasto2 \dec2_fasto2 + connect \fasto2_ok \dec2_fasto2_ok + connect \fn_unit \dec2_fn_unit + connect \input_carry \dec2_input_carry + connect \insn \dec2_insn + connect \insn_type \dec2_insn_type + connect \is_32bit \dec2_is_32bit + connect \lk \dec2_lk + connect \msr \dec2_msr + connect \oe \dec2_oe + connect \oe_ok \dec2_oe_ok + connect \raw_opcode_in \dec2_raw_opcode_in + connect \rc \dec2_rc + connect \rc_ok \dec2_rc_ok + connect \reg1 \dec2_reg1 + connect \reg1_ok \dec2_reg1_ok + connect \reg2 \dec2_reg2 + connect \reg2_ok \dec2_reg2_ok + connect \reg3 \dec2_reg3 + connect \reg3_ok \dec2_reg3_ok + connect \rego \dec2_rego + connect \rego_ok \dec2_rego_ok + connect \spr1 \dec2_spr1 + connect \spr1_ok \dec2_spr1_ok + connect \spro \dec2_spro + connect \spro_ok \dec2_spro_ok + connect \trapaddr \dec2_trapaddr + connect \traptype \dec2_traptype + connect \xer_in \dec2_xer_in + connect \xer_out \dec2_xer_out + end + attribute \module_not_derived 1 + attribute \src "issuer_ls180.v:177773.8-177788.4" + cell \imem \imem + connect \a_pc_i \imem_a_pc_i + connect \a_valid_i \imem_a_valid_i + connect \clk \clk + connect \f_busy_o \imem_f_busy_o + connect \f_instr_o \imem_f_instr_o + connect \f_valid_i \imem_f_valid_i + connect \ibus__ack \ibus__ack + connect \ibus__adr \ibus__adr + connect \ibus__cyc \ibus__cyc + connect \ibus__dat_r \ibus__dat_r + connect \ibus__err \ibus__err + connect \ibus__sel \ibus__sel + connect \ibus__stb \ibus__stb + connect \rst \rst + end + attribute \module_not_derived 1 + attribute \src "issuer_ls180.v:177789.12-177803.4" + cell \xics_icp \xics_icp + connect \clk \clk + connect \core_irq_o \xics_icp_core_irq_o + connect \icp_wb__ack \icp_wb__ack + connect \icp_wb__adr \icp_wb__adr + connect \icp_wb__cyc \icp_wb__cyc + connect \icp_wb__dat_r \icp_wb__dat_r + connect \icp_wb__dat_w \icp_wb__dat_w + connect \icp_wb__sel \icp_wb__sel + connect \icp_wb__stb \icp_wb__stb + connect \icp_wb__we \icp_wb__we + connect \ics_i_pri \xics_icp_ics_i_pri + connect \ics_i_src \xics_icp_ics_i_src + connect \rst \rst + end + attribute \module_not_derived 1 + attribute \src "issuer_ls180.v:177804.12-177817.4" + cell \xics_ics \xics_ics + connect \clk \clk + connect \icp_o_pri \xics_ics_icp_o_pri + connect \icp_o_src \xics_ics_icp_o_src + connect \ics_wb__ack \ics_wb__ack + connect \ics_wb__adr \ics_wb__adr + connect \ics_wb__cyc \ics_wb__cyc + connect \ics_wb__dat_r \ics_wb__dat_r + connect \ics_wb__dat_w \ics_wb__dat_w + connect \ics_wb__stb \ics_wb__stb + connect \ics_wb__we \ics_wb__we + connect \int_level_i \int_level_i + connect \rst \rst + end + attribute \src "issuer_ls180.v:176018.7-176018.20" + process $proc$issuer_ls180.v:176018$12917 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "issuer_ls180.v:176144.13-176144.33" + process $proc$issuer_ls180.v:176144$12918 + assign { } { } + assign $1\core_asmcode[7:0] 8'00000000 + sync always + sync init + update \core_asmcode $1\core_asmcode[7:0] + end + attribute \src "issuer_ls180.v:176150.7-176150.34" + process $proc$issuer_ls180.v:176150$12919 + assign { } { } + assign $0\core_bigendian_i$3[0:0]$12920 1'0 + sync always + sync init + update \core_bigendian_i$3 $0\core_bigendian_i$3[0:0]$12920 + end + attribute \src "issuer_ls180.v:176158.14-176158.55" + process $proc$issuer_ls180.v:176158$12921 + assign { } { } + assign $1\core_core_core_cia[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \core_core_core_cia $1\core_core_core_cia[63:0] + end + attribute \src "issuer_ls180.v:176162.13-176162.41" + process $proc$issuer_ls180.v:176162$12922 + assign { } { } + assign $1\core_core_core_cr_rd[7:0] 8'00000000 + sync always + sync init + update \core_core_core_cr_rd $1\core_core_core_cr_rd[7:0] + end + attribute \src "issuer_ls180.v:176166.7-176166.37" + process $proc$issuer_ls180.v:176166$12923 + assign { } { } + assign $1\core_core_core_cr_rd_ok[0:0] 1'0 + sync always + sync init + update \core_core_core_cr_rd_ok $1\core_core_core_cr_rd_ok[0:0] + end + attribute \src "issuer_ls180.v:176170.13-176170.41" + process $proc$issuer_ls180.v:176170$12924 + assign { } { } + assign $1\core_core_core_cr_wr[7:0] 8'00000000 + sync always + sync init + update \core_core_core_cr_wr $1\core_core_core_cr_wr[7:0] + end + attribute \src "issuer_ls180.v:176187.14-176187.46" + process $proc$issuer_ls180.v:176187$12925 + assign { } { } + assign $1\core_core_core_fn_unit[11:0] 12'000000000000 + sync always + sync init + update \core_core_core_fn_unit $1\core_core_core_fn_unit[11:0] + end + attribute \src "issuer_ls180.v:176195.13-176195.46" + process $proc$issuer_ls180.v:176195$12926 + assign { } { } + assign $1\core_core_core_input_carry[1:0] 2'00 + sync always + sync init + update \core_core_core_input_carry $1\core_core_core_input_carry[1:0] + end + attribute \src "issuer_ls180.v:176199.14-176199.41" + process $proc$issuer_ls180.v:176199$12927 + assign { } { } + assign $1\core_core_core_insn[31:0] 0 + sync always + sync init + update \core_core_core_insn $1\core_core_core_insn[31:0] + end + attribute \src "issuer_ls180.v:176277.13-176277.45" + process $proc$issuer_ls180.v:176277$12928 + assign { } { } + assign $1\core_core_core_insn_type[6:0] 7'0000000 + sync always + sync init + update \core_core_core_insn_type $1\core_core_core_insn_type[6:0] + end + attribute \src "issuer_ls180.v:176281.7-176281.37" + process $proc$issuer_ls180.v:176281$12929 + assign { } { } + assign $1\core_core_core_is_32bit[0:0] 1'0 + sync always + sync init + update \core_core_core_is_32bit $1\core_core_core_is_32bit[0:0] + end + attribute \src "issuer_ls180.v:176285.14-176285.55" + process $proc$issuer_ls180.v:176285$12930 + assign { } { } + assign $1\core_core_core_msr[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \core_core_core_msr $1\core_core_core_msr[63:0] + end + attribute \src "issuer_ls180.v:176289.7-176289.31" + process $proc$issuer_ls180.v:176289$12931 + assign { } { } + assign $1\core_core_core_oe[0:0] 1'0 + sync always + sync init + update \core_core_core_oe $1\core_core_core_oe[0:0] + end + attribute \src "issuer_ls180.v:176293.7-176293.34" + process $proc$issuer_ls180.v:176293$12932 + assign { } { } + assign $1\core_core_core_oe_ok[0:0] 1'0 + sync always + sync init + update \core_core_core_oe_ok $1\core_core_core_oe_ok[0:0] + end + attribute \src "issuer_ls180.v:176297.7-176297.31" + process $proc$issuer_ls180.v:176297$12933 + assign { } { } + assign $1\core_core_core_rc[0:0] 1'0 + sync always + sync init + update \core_core_core_rc $1\core_core_core_rc[0:0] + end + attribute \src "issuer_ls180.v:176301.7-176301.34" + process $proc$issuer_ls180.v:176301$12934 + assign { } { } + assign $1\core_core_core_rc_ok[0:0] 1'0 + sync always + sync init + update \core_core_core_rc_ok $1\core_core_core_rc_ok[0:0] + end + attribute \src "issuer_ls180.v:176305.14-176305.48" + process $proc$issuer_ls180.v:176305$12935 + assign { } { } + assign $1\core_core_core_trapaddr[12:0] 13'0000000000000 + sync always + sync init + update \core_core_core_trapaddr $1\core_core_core_trapaddr[12:0] + end + attribute \src "issuer_ls180.v:176309.13-176309.44" + process $proc$issuer_ls180.v:176309$12936 + assign { } { } + assign $1\core_core_core_traptype[6:0] 7'0000000 + sync always + sync init + update \core_core_core_traptype $1\core_core_core_traptype[6:0] + end + attribute \src "issuer_ls180.v:176313.13-176313.36" + process $proc$issuer_ls180.v:176313$12937 + assign { } { } + assign $1\core_core_cr_in1[2:0] 3'000 + sync always + sync init + update \core_core_cr_in1 $1\core_core_cr_in1[2:0] + end + attribute \src "issuer_ls180.v:176317.7-176317.33" + process $proc$issuer_ls180.v:176317$12938 + assign { } { } + assign $1\core_core_cr_in1_ok[0:0] 1'0 + sync always + sync init + update \core_core_cr_in1_ok $1\core_core_cr_in1_ok[0:0] + end + attribute \src "issuer_ls180.v:176321.13-176321.36" + process $proc$issuer_ls180.v:176321$12939 + assign { } { } + assign $1\core_core_cr_in2[2:0] 3'000 + sync always + sync init + update \core_core_cr_in2 $1\core_core_cr_in2[2:0] + end + attribute \src "issuer_ls180.v:176323.13-176323.40" + process $proc$issuer_ls180.v:176323$12940 + assign { } { } + assign $0\core_core_cr_in2$1[2:0]$12941 3'000 + sync always + sync init + update \core_core_cr_in2$1 $0\core_core_cr_in2$1[2:0]$12941 + end + attribute \src "issuer_ls180.v:176329.7-176329.33" + process $proc$issuer_ls180.v:176329$12942 + assign { } { } + assign $1\core_core_cr_in2_ok[0:0] 1'0 + sync always + sync init + update \core_core_cr_in2_ok $1\core_core_cr_in2_ok[0:0] + end + attribute \src "issuer_ls180.v:176331.7-176331.37" + process $proc$issuer_ls180.v:176331$12943 + assign { } { } + assign $0\core_core_cr_in2_ok$2[0:0]$12944 1'0 + sync always + sync init + update \core_core_cr_in2_ok$2 $0\core_core_cr_in2_ok$2[0:0]$12944 + end + attribute \src "issuer_ls180.v:176337.13-176337.36" + process $proc$issuer_ls180.v:176337$12945 + assign { } { } + assign $1\core_core_cr_out[2:0] 3'000 + sync always + sync init + update \core_core_cr_out $1\core_core_cr_out[2:0] + end + attribute \src "issuer_ls180.v:176341.7-176341.32" + process $proc$issuer_ls180.v:176341$12946 + assign { } { } + assign $1\core_core_cr_wr_ok[0:0] 1'0 + sync always + sync init + update \core_core_cr_wr_ok $1\core_core_cr_wr_ok[0:0] + end + attribute \src "issuer_ls180.v:176345.13-176345.33" + process $proc$issuer_ls180.v:176345$12947 + assign { } { } + assign $1\core_core_ea[4:0] 5'00000 + sync always + sync init + update \core_core_ea $1\core_core_ea[4:0] + end + attribute \src "issuer_ls180.v:176349.13-176349.35" + process $proc$issuer_ls180.v:176349$12948 + assign { } { } + assign $1\core_core_fast1[2:0] 3'000 + sync always + sync init + update \core_core_fast1 $1\core_core_fast1[2:0] + end + attribute \src "issuer_ls180.v:176353.7-176353.32" + process $proc$issuer_ls180.v:176353$12949 + assign { } { } + assign $1\core_core_fast1_ok[0:0] 1'0 + sync always + sync init + update \core_core_fast1_ok $1\core_core_fast1_ok[0:0] + end + attribute \src "issuer_ls180.v:176357.13-176357.35" + process $proc$issuer_ls180.v:176357$12950 + assign { } { } + assign $1\core_core_fast2[2:0] 3'000 + sync always + sync init + update \core_core_fast2 $1\core_core_fast2[2:0] + end + attribute \src "issuer_ls180.v:176361.7-176361.32" + process $proc$issuer_ls180.v:176361$12951 + assign { } { } + assign $1\core_core_fast2_ok[0:0] 1'0 + sync always + sync init + update \core_core_fast2_ok $1\core_core_fast2_ok[0:0] + end + attribute \src "issuer_ls180.v:176365.13-176365.36" + process $proc$issuer_ls180.v:176365$12952 + assign { } { } + assign $1\core_core_fasto1[2:0] 3'000 + sync always + sync init + update \core_core_fasto1 $1\core_core_fasto1[2:0] + end + attribute \src "issuer_ls180.v:176369.13-176369.36" + process $proc$issuer_ls180.v:176369$12953 + assign { } { } + assign $1\core_core_fasto2[2:0] 3'000 + sync always + sync init + update \core_core_fasto2 $1\core_core_fasto2[2:0] + end + attribute \src "issuer_ls180.v:176373.7-176373.26" + process $proc$issuer_ls180.v:176373$12954 + assign { } { } + assign $1\core_core_lk[0:0] 1'0 + sync always + sync init + update \core_core_lk $1\core_core_lk[0:0] + end + attribute \src "issuer_ls180.v:176377.14-176377.49" + process $proc$issuer_ls180.v:176377$12955 + assign { } { } + assign $1\core_core_pc[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \core_core_pc $1\core_core_pc[63:0] + end + attribute \src "issuer_ls180.v:176381.13-176381.35" + process $proc$issuer_ls180.v:176381$12956 + assign { } { } + assign $1\core_core_reg1[4:0] 5'00000 + sync always + sync init + update \core_core_reg1 $1\core_core_reg1[4:0] + end + attribute \src "issuer_ls180.v:176385.7-176385.31" + process $proc$issuer_ls180.v:176385$12957 + assign { } { } + assign $1\core_core_reg1_ok[0:0] 1'0 + sync always + sync init + update \core_core_reg1_ok $1\core_core_reg1_ok[0:0] + end + attribute \src "issuer_ls180.v:176389.13-176389.35" + process $proc$issuer_ls180.v:176389$12958 + assign { } { } + assign $1\core_core_reg2[4:0] 5'00000 + sync always + sync init + update \core_core_reg2 $1\core_core_reg2[4:0] + end + attribute \src "issuer_ls180.v:176393.7-176393.31" + process $proc$issuer_ls180.v:176393$12959 + assign { } { } + assign $1\core_core_reg2_ok[0:0] 1'0 + sync always + sync init + update \core_core_reg2_ok $1\core_core_reg2_ok[0:0] + end + attribute \src "issuer_ls180.v:176397.13-176397.35" + process $proc$issuer_ls180.v:176397$12960 + assign { } { } + assign $1\core_core_reg3[4:0] 5'00000 + sync always + sync init + update \core_core_reg3 $1\core_core_reg3[4:0] + end + attribute \src "issuer_ls180.v:176401.7-176401.31" + process $proc$issuer_ls180.v:176401$12961 + assign { } { } + assign $1\core_core_reg3_ok[0:0] 1'0 + sync always + sync init + update \core_core_reg3_ok $1\core_core_reg3_ok[0:0] + end + attribute \src "issuer_ls180.v:176405.13-176405.35" + process $proc$issuer_ls180.v:176405$12962 + assign { } { } + assign $1\core_core_rego[4:0] 5'00000 + sync always + sync init + update \core_core_rego $1\core_core_rego[4:0] + end + attribute \src "issuer_ls180.v:176522.13-176522.37" + process $proc$issuer_ls180.v:176522$12963 + assign { } { } + assign $1\core_core_spr1[9:0] 10'0000000000 + sync always + sync init + update \core_core_spr1 $1\core_core_spr1[9:0] + end + attribute \src "issuer_ls180.v:176526.7-176526.31" + process $proc$issuer_ls180.v:176526$12964 + assign { } { } + assign $1\core_core_spr1_ok[0:0] 1'0 + sync always + sync init + update \core_core_spr1_ok $1\core_core_spr1_ok[0:0] + end + attribute \src "issuer_ls180.v:176641.13-176641.37" + process $proc$issuer_ls180.v:176641$12965 + assign { } { } + assign $1\core_core_spro[9:0] 10'0000000000 + sync always + sync init + update \core_core_spro $1\core_core_spro[9:0] + end + attribute \src "issuer_ls180.v:176647.13-176647.36" + process $proc$issuer_ls180.v:176647$12966 + assign { } { } + assign $1\core_core_xer_in[2:0] 3'000 + sync always + sync init + update \core_core_xer_in $1\core_core_xer_in[2:0] + end + attribute \src "issuer_ls180.v:176655.7-176655.28" + process $proc$issuer_ls180.v:176655$12967 + assign { } { } + assign $1\core_cr_out_ok[0:0] 1'0 + sync always + sync init + update \core_cr_out_ok $1\core_cr_out_ok[0:0] + end + attribute \src "issuer_ls180.v:176669.14-176669.45" + process $proc$issuer_ls180.v:176669$12968 + assign { } { } + assign $1\core_dec[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \core_dec $1\core_dec[63:0] + end + attribute \src "issuer_ls180.v:176679.7-176679.24" + process $proc$issuer_ls180.v:176679$12969 + assign { } { } + assign $1\core_ea_ok[0:0] 1'0 + sync always + sync init + update \core_ea_ok $1\core_ea_ok[0:0] + end + attribute \src "issuer_ls180.v:176683.7-176683.23" + process $proc$issuer_ls180.v:176683$12970 + assign { } { } + assign $1\core_eint[0:0] 1'0 + sync always + sync init + update \core_eint $1\core_eint[0:0] + end + attribute \src "issuer_ls180.v:176687.7-176687.28" + process $proc$issuer_ls180.v:176687$12971 + assign { } { } + assign $1\core_fasto1_ok[0:0] 1'0 + sync always + sync init + update \core_fasto1_ok $1\core_fasto1_ok[0:0] + end + attribute \src "issuer_ls180.v:176691.7-176691.28" + process $proc$issuer_ls180.v:176691$12972 + assign { } { } + assign $1\core_fasto2_ok[0:0] 1'0 + sync always + sync init + update \core_fasto2_ok $1\core_fasto2_ok[0:0] + end + attribute \src "issuer_ls180.v:176719.14-176719.45" + process $proc$issuer_ls180.v:176719$12973 + assign { } { } + assign $1\core_msr[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \core_msr $1\core_msr[63:0] + end + attribute \src "issuer_ls180.v:176727.14-176727.37" + process $proc$issuer_ls180.v:176727$12974 + assign { } { } + assign $1\core_raw_insn_i[31:0] 0 + sync always + sync init + update \core_raw_insn_i $1\core_raw_insn_i[31:0] + end + attribute \src "issuer_ls180.v:176731.7-176731.26" + process $proc$issuer_ls180.v:176731$12975 + assign { } { } + assign $1\core_rego_ok[0:0] 1'0 + sync always + sync init + update \core_rego_ok $1\core_rego_ok[0:0] + end + attribute \src "issuer_ls180.v:176735.7-176735.26" + process $proc$issuer_ls180.v:176735$12976 + assign { } { } + assign $1\core_spro_ok[0:0] 1'0 + sync always + sync init + update \core_spro_ok $1\core_spro_ok[0:0] + end + attribute \src "issuer_ls180.v:176745.7-176745.26" + process $proc$issuer_ls180.v:176745$12977 + assign { } { } + assign $1\core_xer_out[0:0] 1'0 + sync always + sync init + update \core_xer_out $1\core_xer_out[0:0] + end + attribute \src "issuer_ls180.v:176749.7-176749.30" + process $proc$issuer_ls180.v:176749$12978 + assign { } { } + assign $1\cu_st__rel_o_dly[0:0] 1'0 + sync always + sync init + update \cu_st__rel_o_dly $1\cu_st__rel_o_dly[0:0] + end + attribute \src "issuer_ls180.v:176755.7-176755.24" + process $proc$issuer_ls180.v:176755$12979 + assign { } { } + assign $1\d_cr_delay[0:0] 1'0 + sync always + sync init + update \d_cr_delay $1\d_cr_delay[0:0] + end + attribute \src "issuer_ls180.v:176759.7-176759.25" + process $proc$issuer_ls180.v:176759$12980 + assign { } { } + assign $1\d_reg_delay[0:0] 1'0 + sync always + sync init + update \d_reg_delay $1\d_reg_delay[0:0] + end + attribute \src "issuer_ls180.v:176763.7-176763.25" + process $proc$issuer_ls180.v:176763$12981 + assign { } { } + assign $1\d_xer_delay[0:0] 1'0 + sync always + sync init + update \d_xer_delay $1\d_xer_delay[0:0] + end + attribute \src "issuer_ls180.v:176851.14-176851.49" + process $proc$issuer_ls180.v:176851$12982 + assign { } { } + assign $1\dec2_cur_dec[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \dec2_cur_dec $1\dec2_cur_dec[63:0] + end + attribute \src "issuer_ls180.v:176855.7-176855.27" + process $proc$issuer_ls180.v:176855$12983 + assign { } { } + assign $1\dec2_cur_eint[0:0] 1'0 + sync always + sync init + update \dec2_cur_eint $1\dec2_cur_eint[0:0] + end + attribute \src "issuer_ls180.v:176859.14-176859.49" + process $proc$issuer_ls180.v:176859$12984 + assign { } { } + assign $1\dec2_cur_msr[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \dec2_cur_msr $1\dec2_cur_msr[63:0] + end + attribute \src "issuer_ls180.v:176863.14-176863.48" + process $proc$issuer_ls180.v:176863$12985 + assign { } { } + assign $1\dec2_cur_pc[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \dec2_cur_pc $1\dec2_cur_pc[63:0] + end + attribute \src "issuer_ls180.v:177256.13-177256.25" + process $proc$issuer_ls180.v:177256$12986 + assign { } { } + assign $1\delay[1:0] 2'11 + sync always + sync init + update \delay $1\delay[1:0] + end + attribute \src "issuer_ls180.v:177272.13-177272.29" + process $proc$issuer_ls180.v:177272$12987 + assign { } { } + assign $1\fsm_state[1:0] 2'00 + sync always + sync init + update \fsm_state $1\fsm_state[1:0] + end + attribute \src "issuer_ls180.v:177274.13-177274.35" + process $proc$issuer_ls180.v:177274$12988 + assign { } { } + assign $0\fsm_state$117[1:0]$12989 2'00 + sync always + sync init + update \fsm_state$117 $0\fsm_state$117[1:0]$12989 + end + attribute \src "issuer_ls180.v:177346.14-177346.28" + process $proc$issuer_ls180.v:177346$12990 + assign { } { } + assign $1\ilatch[31:0] 0 + sync always + sync init + update \ilatch $1\ilatch[31:0] + end + attribute \src "issuer_ls180.v:177364.7-177364.22" + process $proc$issuer_ls180.v:177364$12991 + assign { } { } + assign $1\msr_read[0:0] 1'1 + sync always + sync init + update \msr_read $1\msr_read[0:0] + end + attribute \src "issuer_ls180.v:177376.7-177376.24" + process $proc$issuer_ls180.v:177376$12992 + assign { } { } + assign $1\pc_changed[0:0] 1'0 + sync always + sync init + update \pc_changed $1\pc_changed[0:0] + end + attribute \src "issuer_ls180.v:177386.7-177386.25" + process $proc$issuer_ls180.v:177386$12993 + assign { } { } + assign $1\pc_ok_delay[0:0] 1'0 + sync always + sync init + update \pc_ok_delay $1\pc_ok_delay[0:0] + end + attribute \src "issuer_ls180.v:177459.3-177460.41" + process $proc$issuer_ls180.v:177459$12497 + assign { } { } + assign $0\dec2_cur_dec[63:0] \dec2_cur_dec$next + sync posedge \clk + update \dec2_cur_dec $0\dec2_cur_dec[63:0] + end + attribute \src "issuer_ls180.v:177461.3-177462.33" + process $proc$issuer_ls180.v:177461$12498 + assign { } { } + assign $0\core_dec[63:0] \core_dec$next + sync posedge \clk + update \core_dec $0\core_dec[63:0] + end + attribute \src "issuer_ls180.v:177463.3-177464.41" + process $proc$issuer_ls180.v:177463$12499 + assign { } { } + assign $0\dec2_cur_msr[63:0] \dec2_cur_msr$next + sync posedge \clk + update \dec2_cur_msr $0\dec2_cur_msr[63:0] + end + attribute \src "issuer_ls180.v:177465.3-177466.35" + process $proc$issuer_ls180.v:177465$12500 + assign { } { } + assign $0\fsm_state[1:0] \fsm_state$next + sync posedge \clk + update \fsm_state $0\fsm_state[1:0] + end + attribute \src "issuer_ls180.v:177467.3-177468.33" + process $proc$issuer_ls180.v:177467$12501 + assign { } { } + assign $0\msr_read[0:0] \msr_read$next + sync posedge \clk + update \msr_read $0\msr_read[0:0] + end + attribute \src "issuer_ls180.v:177469.3-177470.39" + process $proc$issuer_ls180.v:177469$12502 + assign { } { } + assign $0\dec2_cur_pc[63:0] \dec2_cur_pc$next + sync posedge \clk + update \dec2_cur_pc $0\dec2_cur_pc[63:0] + end + attribute \src "issuer_ls180.v:177471.3-177472.55" + process $proc$issuer_ls180.v:177471$12503 + assign { } { } + assign $0\core_bigendian_i$3[0:0]$12504 \core_bigendian_i$3$next + sync posedge \clk + update \core_bigendian_i$3 $0\core_bigendian_i$3[0:0]$12504 + end + attribute \src "issuer_ls180.v:177473.3-177474.47" + process $proc$issuer_ls180.v:177473$12505 + assign { } { } + assign $0\core_raw_insn_i[31:0] \core_raw_insn_i$next + sync posedge \clk + update \core_raw_insn_i $0\core_raw_insn_i[31:0] + end + attribute \src "issuer_ls180.v:177475.3-177476.41" + process $proc$issuer_ls180.v:177475$12506 + assign { } { } + assign $0\core_asmcode[7:0] \core_asmcode$next + sync posedge \clk + update \core_asmcode $0\core_asmcode[7:0] + end + attribute \src "issuer_ls180.v:177477.3-177478.45" + process $proc$issuer_ls180.v:177477$12507 + assign { } { } + assign $0\core_core_rego[4:0] \core_core_rego$next + sync posedge \clk + update \core_core_rego $0\core_core_rego[4:0] + end + attribute \src "issuer_ls180.v:177479.3-177480.41" + process $proc$issuer_ls180.v:177479$12508 + assign { } { } + assign $0\core_rego_ok[0:0] \core_rego_ok$next + sync posedge \clk + update \core_rego_ok $0\core_rego_ok[0:0] + end + attribute \src "issuer_ls180.v:177481.3-177482.45" + process $proc$issuer_ls180.v:177481$12509 + assign { } { } + assign $0\fsm_state$117[1:0]$12510 \fsm_state$117$next + sync posedge \clk + update \fsm_state$117 $0\fsm_state$117[1:0]$12510 + end + attribute \src "issuer_ls180.v:177483.3-177484.41" + process $proc$issuer_ls180.v:177483$12511 + assign { } { } + assign $0\core_core_ea[4:0] \core_core_ea$next + sync posedge \clk + update \core_core_ea $0\core_core_ea[4:0] + end + attribute \src "issuer_ls180.v:177485.3-177486.37" + process $proc$issuer_ls180.v:177485$12512 + assign { } { } + assign $0\core_ea_ok[0:0] \core_ea_ok$next + sync posedge \clk + update \core_ea_ok $0\core_ea_ok[0:0] + end + attribute \src "issuer_ls180.v:177487.3-177488.45" + process $proc$issuer_ls180.v:177487$12513 + assign { } { } + assign $0\core_core_reg1[4:0] \core_core_reg1$next + sync posedge \clk + update \core_core_reg1 $0\core_core_reg1[4:0] + end + attribute \src "issuer_ls180.v:177489.3-177490.51" + process $proc$issuer_ls180.v:177489$12514 + assign { } { } + assign $0\core_core_reg1_ok[0:0] \core_core_reg1_ok$next + sync posedge \clk + update \core_core_reg1_ok $0\core_core_reg1_ok[0:0] + end + attribute \src "issuer_ls180.v:177491.3-177492.45" + process $proc$issuer_ls180.v:177491$12515 + assign { } { } + assign $0\core_core_reg2[4:0] \core_core_reg2$next + sync posedge \clk + update \core_core_reg2 $0\core_core_reg2[4:0] + end + attribute \src "issuer_ls180.v:177493.3-177494.51" + process $proc$issuer_ls180.v:177493$12516 + assign { } { } + assign $0\core_core_reg2_ok[0:0] \core_core_reg2_ok$next + sync posedge \clk + update \core_core_reg2_ok $0\core_core_reg2_ok[0:0] + end + attribute \src "issuer_ls180.v:177495.3-177496.45" + process $proc$issuer_ls180.v:177495$12517 + assign { } { } + assign $0\core_core_reg3[4:0] \core_core_reg3$next + sync posedge \clk + update \core_core_reg3 $0\core_core_reg3[4:0] + end + attribute \src "issuer_ls180.v:177497.3-177498.51" + process $proc$issuer_ls180.v:177497$12518 + assign { } { } + assign $0\core_core_reg3_ok[0:0] \core_core_reg3_ok$next + sync posedge \clk + update \core_core_reg3_ok $0\core_core_reg3_ok[0:0] + end + attribute \src "issuer_ls180.v:177499.3-177500.45" + process $proc$issuer_ls180.v:177499$12519 + assign { } { } + assign $0\core_core_spro[9:0] \core_core_spro$next + sync posedge \clk + update \core_core_spro $0\core_core_spro[9:0] + end + attribute \src "issuer_ls180.v:177501.3-177502.41" + process $proc$issuer_ls180.v:177501$12520 + assign { } { } + assign $0\core_spro_ok[0:0] \core_spro_ok$next + sync posedge \clk + update \core_spro_ok $0\core_spro_ok[0:0] + end + attribute \src "issuer_ls180.v:177503.3-177504.39" + process $proc$issuer_ls180.v:177503$12521 + assign { } { } + assign $0\d_xer_delay[0:0] \d_xer_delay$next + sync posedge \clk + update \d_xer_delay $0\d_xer_delay[0:0] + end + attribute \src "issuer_ls180.v:177505.3-177506.45" + process $proc$issuer_ls180.v:177505$12522 + assign { } { } + assign $0\core_core_spr1[9:0] \core_core_spr1$next + sync posedge \clk + update \core_core_spr1 $0\core_core_spr1[9:0] + end + attribute \src "issuer_ls180.v:177507.3-177508.51" + process $proc$issuer_ls180.v:177507$12523 + assign { } { } + assign $0\core_core_spr1_ok[0:0] \core_core_spr1_ok$next + sync posedge \clk + update \core_core_spr1_ok $0\core_core_spr1_ok[0:0] + end + attribute \src "issuer_ls180.v:177509.3-177510.49" + process $proc$issuer_ls180.v:177509$12524 + assign { } { } + assign $0\core_core_xer_in[2:0] \core_core_xer_in$next + sync posedge \clk + update \core_core_xer_in $0\core_core_xer_in[2:0] + end + attribute \src "issuer_ls180.v:177511.3-177512.41" + process $proc$issuer_ls180.v:177511$12525 + assign { } { } + assign $0\core_xer_out[0:0] \core_xer_out$next + sync posedge \clk + update \core_xer_out $0\core_xer_out[0:0] + end + attribute \src "issuer_ls180.v:177513.3-177514.47" + process $proc$issuer_ls180.v:177513$12526 + assign { } { } + assign $0\core_core_fast1[2:0] \core_core_fast1$next + sync posedge \clk + update \core_core_fast1 $0\core_core_fast1[2:0] + end + attribute \src "issuer_ls180.v:177515.3-177516.53" + process $proc$issuer_ls180.v:177515$12527 + assign { } { } + assign $0\core_core_fast1_ok[0:0] \core_core_fast1_ok$next + sync posedge \clk + update \core_core_fast1_ok $0\core_core_fast1_ok[0:0] + end + attribute \src "issuer_ls180.v:177517.3-177518.47" + process $proc$issuer_ls180.v:177517$12528 + assign { } { } + assign $0\core_core_fast2[2:0] \core_core_fast2$next + sync posedge \clk + update \core_core_fast2 $0\core_core_fast2[2:0] + end + attribute \src "issuer_ls180.v:177519.3-177520.53" + process $proc$issuer_ls180.v:177519$12529 + assign { } { } + assign $0\core_core_fast2_ok[0:0] \core_core_fast2_ok$next + sync posedge \clk + update \core_core_fast2_ok $0\core_core_fast2_ok[0:0] + end + attribute \src "issuer_ls180.v:177521.3-177522.49" + process $proc$issuer_ls180.v:177521$12530 + assign { } { } + assign $0\core_core_fasto1[2:0] \core_core_fasto1$next + sync posedge \clk + update \core_core_fasto1 $0\core_core_fasto1[2:0] + end + attribute \src "issuer_ls180.v:177523.3-177524.45" + process $proc$issuer_ls180.v:177523$12531 + assign { } { } + assign $0\core_fasto1_ok[0:0] \core_fasto1_ok$next + sync posedge \clk + update \core_fasto1_ok $0\core_fasto1_ok[0:0] + end + attribute \src "issuer_ls180.v:177525.3-177526.37" + process $proc$issuer_ls180.v:177525$12532 + assign { } { } + assign $0\d_cr_delay[0:0] \d_cr_delay$next + sync posedge \clk + update \d_cr_delay $0\d_cr_delay[0:0] + end + attribute \src "issuer_ls180.v:177527.3-177528.49" + process $proc$issuer_ls180.v:177527$12533 + assign { } { } + assign $0\core_core_fasto2[2:0] \core_core_fasto2$next + sync posedge \clk + update \core_core_fasto2 $0\core_core_fasto2[2:0] + end + attribute \src "issuer_ls180.v:177529.3-177530.45" + process $proc$issuer_ls180.v:177529$12534 + assign { } { } + assign $0\core_fasto2_ok[0:0] \core_fasto2_ok$next + sync posedge \clk + update \core_fasto2_ok $0\core_fasto2_ok[0:0] + end + attribute \src "issuer_ls180.v:177531.3-177532.49" + process $proc$issuer_ls180.v:177531$12535 + assign { } { } + assign $0\core_core_cr_in1[2:0] \core_core_cr_in1$next + sync posedge \clk + update \core_core_cr_in1 $0\core_core_cr_in1[2:0] + end + attribute \src "issuer_ls180.v:177533.3-177534.55" + process $proc$issuer_ls180.v:177533$12536 + assign { } { } + assign $0\core_core_cr_in1_ok[0:0] \core_core_cr_in1_ok$next + sync posedge \clk + update \core_core_cr_in1_ok $0\core_core_cr_in1_ok[0:0] + end + attribute \src "issuer_ls180.v:177535.3-177536.49" + process $proc$issuer_ls180.v:177535$12537 + assign { } { } + assign $0\core_core_cr_in2[2:0] \core_core_cr_in2$next + sync posedge \clk + update \core_core_cr_in2 $0\core_core_cr_in2[2:0] + end + attribute \src "issuer_ls180.v:177537.3-177538.55" + process $proc$issuer_ls180.v:177537$12538 + assign { } { } + assign $0\core_core_cr_in2_ok[0:0] \core_core_cr_in2_ok$next + sync posedge \clk + update \core_core_cr_in2_ok $0\core_core_cr_in2_ok[0:0] + end + attribute \src "issuer_ls180.v:177539.3-177540.55" + process $proc$issuer_ls180.v:177539$12539 + assign { } { } + assign $0\core_core_cr_in2$1[2:0]$12540 \core_core_cr_in2$1$next + sync posedge \clk + update \core_core_cr_in2$1 $0\core_core_cr_in2$1[2:0]$12540 + end + attribute \src "issuer_ls180.v:177541.3-177542.61" + process $proc$issuer_ls180.v:177541$12541 + assign { } { } + assign $0\core_core_cr_in2_ok$2[0:0]$12542 \core_core_cr_in2_ok$2$next + sync posedge \clk + update \core_core_cr_in2_ok$2 $0\core_core_cr_in2_ok$2[0:0]$12542 + end + attribute \src "issuer_ls180.v:177543.3-177544.49" + process $proc$issuer_ls180.v:177543$12543 + assign { } { } + assign $0\core_core_cr_out[2:0] \core_core_cr_out$next + sync posedge \clk + update \core_core_cr_out $0\core_core_cr_out[2:0] + end + attribute \src "issuer_ls180.v:177545.3-177546.45" + process $proc$issuer_ls180.v:177545$12544 + assign { } { } + assign $0\core_cr_out_ok[0:0] \core_cr_out_ok$next + sync posedge \clk + update \core_cr_out_ok $0\core_cr_out_ok[0:0] + end + attribute \src "issuer_ls180.v:177547.3-177548.39" + process $proc$issuer_ls180.v:177547$12545 + assign { } { } + assign $0\d_reg_delay[0:0] \d_reg_delay$next + sync posedge \clk + update \d_reg_delay $0\d_reg_delay[0:0] + end + attribute \src "issuer_ls180.v:177549.3-177550.53" + process $proc$issuer_ls180.v:177549$12546 + assign { } { } + assign $0\core_core_core_msr[63:0] \core_core_core_msr$next + sync posedge \clk + update \core_core_core_msr $0\core_core_core_msr[63:0] + end + attribute \src "issuer_ls180.v:177551.3-177552.53" + process $proc$issuer_ls180.v:177551$12547 + assign { } { } + assign $0\core_core_core_cia[63:0] \core_core_core_cia$next + sync posedge \clk + update \core_core_core_cia $0\core_core_core_cia[63:0] + end + attribute \src "issuer_ls180.v:177553.3-177554.55" + process $proc$issuer_ls180.v:177553$12548 + assign { } { } + assign $0\core_core_core_insn[31:0] \core_core_core_insn$next + sync posedge \clk + update \core_core_core_insn $0\core_core_core_insn[31:0] + end + attribute \src "issuer_ls180.v:177555.3-177556.65" + process $proc$issuer_ls180.v:177555$12549 + assign { } { } + assign $0\core_core_core_insn_type[6:0] \core_core_core_insn_type$next + sync posedge \clk + update \core_core_core_insn_type $0\core_core_core_insn_type[6:0] + end + attribute \src "issuer_ls180.v:177557.3-177558.61" + process $proc$issuer_ls180.v:177557$12550 + assign { } { } + assign $0\core_core_core_fn_unit[11:0] \core_core_core_fn_unit$next + sync posedge \clk + update \core_core_core_fn_unit $0\core_core_core_fn_unit[11:0] + end + attribute \src "issuer_ls180.v:177559.3-177560.41" + process $proc$issuer_ls180.v:177559$12551 + assign { } { } + assign $0\core_core_lk[0:0] \core_core_lk$next + sync posedge \clk + update \core_core_lk $0\core_core_lk[0:0] + end + attribute \src "issuer_ls180.v:177561.3-177562.51" + process $proc$issuer_ls180.v:177561$12552 + assign { } { } + assign $0\core_core_core_rc[0:0] \core_core_core_rc$next + sync posedge \clk + update \core_core_core_rc $0\core_core_core_rc[0:0] + end + attribute \src "issuer_ls180.v:177563.3-177564.57" + process $proc$issuer_ls180.v:177563$12553 + assign { } { } + assign $0\core_core_core_rc_ok[0:0] \core_core_core_rc_ok$next + sync posedge \clk + update \core_core_core_rc_ok $0\core_core_core_rc_ok[0:0] + end + attribute \src "issuer_ls180.v:177565.3-177566.51" + process $proc$issuer_ls180.v:177565$12554 + assign { } { } + assign $0\core_core_core_oe[0:0] \core_core_core_oe$next + sync posedge \clk + update \core_core_core_oe $0\core_core_core_oe[0:0] + end + attribute \src "issuer_ls180.v:177567.3-177568.57" + process $proc$issuer_ls180.v:177567$12555 + assign { } { } + assign $0\core_core_core_oe_ok[0:0] \core_core_core_oe_ok$next + sync posedge \clk + update \core_core_core_oe_ok $0\core_core_core_oe_ok[0:0] + end + attribute \src "issuer_ls180.v:177569.3-177570.29" + process $proc$issuer_ls180.v:177569$12556 + assign { } { } + assign $0\ilatch[31:0] \ilatch$next + sync posedge \clk + update \ilatch $0\ilatch[31:0] + end + attribute \src "issuer_ls180.v:177571.3-177572.69" + process $proc$issuer_ls180.v:177571$12557 + assign { } { } + assign $0\core_core_core_input_carry[1:0] \core_core_core_input_carry$next + sync posedge \clk + update \core_core_core_input_carry $0\core_core_core_input_carry[1:0] + end + attribute \src "issuer_ls180.v:177573.3-177574.63" + process $proc$issuer_ls180.v:177573$12558 + assign { } { } + assign $0\core_core_core_traptype[6:0] \core_core_core_traptype$next + sync posedge \clk + update \core_core_core_traptype $0\core_core_core_traptype[6:0] + end + attribute \src "issuer_ls180.v:177575.3-177576.63" + process $proc$issuer_ls180.v:177575$12559 + assign { } { } + assign $0\core_core_core_trapaddr[12:0] \core_core_core_trapaddr$next + sync posedge \clk + update \core_core_core_trapaddr $0\core_core_core_trapaddr[12:0] + end + attribute \src "issuer_ls180.v:177577.3-177578.57" + process $proc$issuer_ls180.v:177577$12560 + assign { } { } + assign $0\core_core_core_cr_rd[7:0] \core_core_core_cr_rd$next + sync posedge \clk + update \core_core_core_cr_rd $0\core_core_core_cr_rd[7:0] + end + attribute \src "issuer_ls180.v:177579.3-177580.63" + process $proc$issuer_ls180.v:177579$12561 + assign { } { } + assign $0\core_core_core_cr_rd_ok[0:0] \core_core_core_cr_rd_ok$next + sync posedge \clk + update \core_core_core_cr_rd_ok $0\core_core_core_cr_rd_ok[0:0] + end + attribute \src "issuer_ls180.v:177581.3-177582.57" + process $proc$issuer_ls180.v:177581$12562 + assign { } { } + assign $0\core_core_core_cr_wr[7:0] \core_core_core_cr_wr$next + sync posedge \clk + update \core_core_core_cr_wr $0\core_core_core_cr_wr[7:0] + end + attribute \src "issuer_ls180.v:177583.3-177584.53" + process $proc$issuer_ls180.v:177583$12563 + assign { } { } + assign $0\core_core_cr_wr_ok[0:0] \core_core_cr_wr_ok$next + sync posedge \clk + update \core_core_cr_wr_ok $0\core_core_cr_wr_ok[0:0] + end + attribute \src "issuer_ls180.v:177585.3-177586.63" + process $proc$issuer_ls180.v:177585$12564 + assign { } { } + assign $0\core_core_core_is_32bit[0:0] \core_core_core_is_32bit$next + sync posedge \clk + update \core_core_core_is_32bit $0\core_core_core_is_32bit[0:0] + end + attribute \src "issuer_ls180.v:177587.3-177588.37" + process $proc$issuer_ls180.v:177587$12565 + assign { } { } + assign $0\pc_changed[0:0] \pc_changed$next + sync posedge \clk + update \pc_changed $0\pc_changed[0:0] + end + attribute \src "issuer_ls180.v:177589.3-177590.39" + process $proc$issuer_ls180.v:177589$12566 + assign { } { } + assign $0\pc_ok_delay[0:0] \pc_ok_delay$next + sync posedge \clk + update \pc_ok_delay $0\pc_ok_delay[0:0] + end + attribute \src "issuer_ls180.v:177591.3-177592.41" + process $proc$issuer_ls180.v:177591$12567 + assign { } { } + assign $0\core_core_pc[63:0] \core_core_pc$next + sync posedge \clk + update \core_core_pc $0\core_core_pc[63:0] + end + attribute \src "issuer_ls180.v:177593.3-177594.43" + process $proc$issuer_ls180.v:177593$12568 + assign { } { } + assign $0\cu_st__rel_o_dly[0:0] \core_cu_st__rel_o + sync posedge \clk + update \cu_st__rel_o_dly $0\cu_st__rel_o_dly[0:0] + end + attribute \src "issuer_ls180.v:177595.3-177596.27" + process $proc$issuer_ls180.v:177595$12569 + assign { } { } + assign $0\delay[1:0] \delay$next + sync posedge \por_clk + update \delay $0\delay[1:0] + end + attribute \src "issuer_ls180.v:177597.3-177598.43" + process $proc$issuer_ls180.v:177597$12570 + assign { } { } + assign $0\dec2_cur_eint[0:0] \dec2_cur_eint$next + sync posedge \clk + update \dec2_cur_eint $0\dec2_cur_eint[0:0] + end + attribute \src "issuer_ls180.v:177599.3-177600.33" + process $proc$issuer_ls180.v:177599$12571 + assign { } { } + assign $0\core_msr[63:0] \core_msr$next + sync posedge \clk + update \core_msr $0\core_msr[63:0] + end + attribute \src "issuer_ls180.v:177601.3-177602.35" + process $proc$issuer_ls180.v:177601$12572 + assign { } { } + assign $0\core_eint[0:0] \core_eint$next + sync posedge \clk + update \core_eint $0\core_eint[0:0] + end + attribute \src "issuer_ls180.v:177818.3-177827.6" + process $proc$issuer_ls180.v:177818$12573 + assign { } { } + assign { } { } + assign $0\core_full_rd2__ren[7:0] $1\core_full_rd2__ren[7:0] + attribute \src "issuer_ls180.v:177819.5-177819.29" + switch \initial + attribute \src "issuer_ls180.v:177819.9-177819.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:310" + switch \dbg_d_cr_req + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\core_full_rd2__ren[7:0] 8'11111111 + case + assign $1\core_full_rd2__ren[7:0] 8'00000000 + end + sync always + update \core_full_rd2__ren $0\core_full_rd2__ren[7:0] + end + attribute \src "issuer_ls180.v:177828.3-177836.6" + process $proc$issuer_ls180.v:177828$12574 + assign { } { } + assign { } { } + assign $0\d_cr_delay$next[0:0]$12575 $1\d_cr_delay$next[0:0]$12576 + attribute \src "issuer_ls180.v:177829.5-177829.29" + switch \initial + attribute \src "issuer_ls180.v:177829.9-177829.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\d_cr_delay$next[0:0]$12576 1'0 + case + assign $1\d_cr_delay$next[0:0]$12576 \dbg_d_cr_req + end + sync always + update \d_cr_delay$next $0\d_cr_delay$next[0:0]$12575 + end + attribute \src "issuer_ls180.v:177837.3-177846.6" + process $proc$issuer_ls180.v:177837$12577 + assign { } { } + assign { } { } + assign $0\dbg_d_cr_data[63:0] $1\dbg_d_cr_data[63:0] + attribute \src "issuer_ls180.v:177838.5-177838.29" + switch \initial + attribute \src "issuer_ls180.v:177838.9-177838.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:314" + switch \d_cr_delay + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dbg_d_cr_data[63:0] \$113 + case + assign $1\dbg_d_cr_data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \dbg_d_cr_data $0\dbg_d_cr_data[63:0] + end + attribute \src "issuer_ls180.v:177847.3-177856.6" + process $proc$issuer_ls180.v:177847$12578 + assign { } { } + assign { } { } + assign $0\dbg_d_cr_ack[0:0] $1\dbg_d_cr_ack[0:0] + attribute \src "issuer_ls180.v:177848.5-177848.29" + switch \initial + attribute \src "issuer_ls180.v:177848.9-177848.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:314" + switch \d_cr_delay + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dbg_d_cr_ack[0:0] 1'1 + case + assign $1\dbg_d_cr_ack[0:0] 1'0 + end + sync always + update \dbg_d_cr_ack $0\dbg_d_cr_ack[0:0] + end + attribute \src "issuer_ls180.v:177857.3-177866.6" + process $proc$issuer_ls180.v:177857$12579 + assign { } { } + assign { } { } + assign $0\core_full_rd__ren[2:0] $1\core_full_rd__ren[2:0] + attribute \src "issuer_ls180.v:177858.5-177858.29" + switch \initial + attribute \src "issuer_ls180.v:177858.9-177858.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:320" + switch \dbg_d_xer_req + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\core_full_rd__ren[2:0] 3'111 + case + assign $1\core_full_rd__ren[2:0] 3'000 + end + sync always + update \core_full_rd__ren $0\core_full_rd__ren[2:0] + end + attribute \src "issuer_ls180.v:177867.3-177875.6" + process $proc$issuer_ls180.v:177867$12580 + assign { } { } + assign { } { } + assign $0\d_xer_delay$next[0:0]$12581 $1\d_xer_delay$next[0:0]$12582 + attribute \src "issuer_ls180.v:177868.5-177868.29" + switch \initial + attribute \src "issuer_ls180.v:177868.9-177868.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\d_xer_delay$next[0:0]$12582 1'0 + case + assign $1\d_xer_delay$next[0:0]$12582 \dbg_d_xer_req + end + sync always + update \d_xer_delay$next $0\d_xer_delay$next[0:0]$12581 + end + attribute \src "issuer_ls180.v:177876.3-177885.6" + process $proc$issuer_ls180.v:177876$12583 + assign { } { } + assign { } { } + assign $0\dbg_d_xer_data[63:0] $1\dbg_d_xer_data[63:0] + attribute \src "issuer_ls180.v:177877.5-177877.29" + switch \initial + attribute \src "issuer_ls180.v:177877.9-177877.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:324" + switch \d_xer_delay + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dbg_d_xer_data[63:0] \$115 + case + assign $1\dbg_d_xer_data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \dbg_d_xer_data $0\dbg_d_xer_data[63:0] + end + attribute \src "issuer_ls180.v:177886.3-177895.6" + process $proc$issuer_ls180.v:177886$12584 + assign { } { } + assign { } { } + assign $0\dbg_d_xer_ack[0:0] $1\dbg_d_xer_ack[0:0] + attribute \src "issuer_ls180.v:177887.5-177887.29" + switch \initial + attribute \src "issuer_ls180.v:177887.9-177887.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:324" + switch \d_xer_delay + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dbg_d_xer_ack[0:0] 1'1 + case + assign $1\dbg_d_xer_ack[0:0] 1'0 + end + sync always + update \dbg_d_xer_ack $0\dbg_d_xer_ack[0:0] + end + attribute \src "issuer_ls180.v:177896.3-177910.6" + process $proc$issuer_ls180.v:177896$12585 + assign { } { } + assign { } { } + assign $0\core_issue__addr[2:0] $1\core_issue__addr[2:0] + attribute \src "issuer_ls180.v:177897.5-177897.29" + switch \initial + attribute \src "issuer_ls180.v:177897.9-177897.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:350" + switch \fsm_state$117 + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\core_issue__addr[2:0] 3'110 + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\core_issue__addr[2:0] 3'111 + case + assign $1\core_issue__addr[2:0] 3'000 + end + sync always + update \core_issue__addr $0\core_issue__addr[2:0] + end + attribute \src "issuer_ls180.v:177911.3-177925.6" + process $proc$issuer_ls180.v:177911$12586 + assign { } { } + assign { } { } + assign $0\core_issue__ren[0:0] $1\core_issue__ren[0:0] + attribute \src "issuer_ls180.v:177912.5-177912.29" + switch \initial + attribute \src "issuer_ls180.v:177912.9-177912.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:350" + switch \fsm_state$117 + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\core_issue__ren[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\core_issue__ren[0:0] 1'1 + case + assign $1\core_issue__ren[0:0] 1'0 + end + sync always + update \core_issue__ren $0\core_issue__ren[0:0] + end + attribute \src "issuer_ls180.v:177926.3-177953.6" + process $proc$issuer_ls180.v:177926$12587 + assign { } { } + assign { } { } + assign { } { } + assign $0\fsm_state$117$next[1:0]$12588 $2\fsm_state$117$next[1:0]$12590 + attribute \src "issuer_ls180.v:177927.5-177927.29" + switch \initial + attribute \src "issuer_ls180.v:177927.9-177927.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:350" + switch \fsm_state$117 + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\fsm_state$117$next[1:0]$12589 2'01 + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\fsm_state$117$next[1:0]$12589 2'10 + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\fsm_state$117$next[1:0]$12589 2'11 + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'11 + assign { } { } + assign $1\fsm_state$117$next[1:0]$12589 2'00 + case + assign $1\fsm_state$117$next[1:0]$12589 \fsm_state$117 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\fsm_state$117$next[1:0]$12590 2'00 + case + assign $2\fsm_state$117$next[1:0]$12590 $1\fsm_state$117$next[1:0]$12589 + end + sync always + update \fsm_state$117$next $0\fsm_state$117$next[1:0]$12588 + end + attribute \src "issuer_ls180.v:177954.3-177964.6" + process $proc$issuer_ls180.v:177954$12591 + assign { } { } + assign { } { } + assign $0\new_dec[63:0] $1\new_dec[63:0] + attribute \src "issuer_ls180.v:177955.5-177955.29" + switch \initial + attribute \src "issuer_ls180.v:177955.9-177955.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:350" + switch \fsm_state$117 + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\new_dec[63:0] \$118 [63:0] + case + assign $1\new_dec[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \new_dec $0\new_dec[63:0] + end + attribute \src "issuer_ls180.v:177965.3-177979.6" + process $proc$issuer_ls180.v:177965$12592 + assign { } { } + assign { } { } + assign $0\core_issue__addr$4[2:0]$12593 $1\core_issue__addr$4[2:0]$12594 + attribute \src "issuer_ls180.v:177966.5-177966.29" + switch \initial + attribute \src "issuer_ls180.v:177966.9-177966.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:350" + switch \fsm_state$117 + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\core_issue__addr$4[2:0]$12594 3'110 + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'11 + assign { } { } + assign $1\core_issue__addr$4[2:0]$12594 3'111 + case + assign $1\core_issue__addr$4[2:0]$12594 3'000 + end + sync always + update \core_issue__addr$4 $0\core_issue__addr$4[2:0]$12593 + end + attribute \src "issuer_ls180.v:177980.3-177994.6" + process $proc$issuer_ls180.v:177980$12595 + assign { } { } + assign { } { } + assign $0\core_issue__wen[0:0] $1\core_issue__wen[0:0] + attribute \src "issuer_ls180.v:177981.5-177981.29" + switch \initial + attribute \src "issuer_ls180.v:177981.9-177981.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:350" + switch \fsm_state$117 + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\core_issue__wen[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'11 + assign { } { } + assign $1\core_issue__wen[0:0] 1'1 + case + assign $1\core_issue__wen[0:0] 1'0 + end + sync always + update \core_issue__wen $0\core_issue__wen[0:0] + end + attribute \src "issuer_ls180.v:177995.3-178009.6" + process $proc$issuer_ls180.v:177995$12596 + assign { } { } + assign { } { } + assign $0\core_issue__data_i[63:0] $1\core_issue__data_i[63:0] + attribute \src "issuer_ls180.v:177996.5-177996.29" + switch \initial + attribute \src "issuer_ls180.v:177996.9-177996.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:350" + switch \fsm_state$117 + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\core_issue__data_i[63:0] \new_dec + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'11 + assign { } { } + assign $1\core_issue__data_i[63:0] \new_tb + case + assign $1\core_issue__data_i[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \core_issue__data_i $0\core_issue__data_i[63:0] + end + attribute \src "issuer_ls180.v:178010.3-178025.6" + process $proc$issuer_ls180.v:178010$12597 + assign { } { } + assign { } { } + assign { } { } + assign $0\dec2_cur_dec$next[63:0]$12598 $2\dec2_cur_dec$next[63:0]$12600 + attribute \src "issuer_ls180.v:178011.5-178011.29" + switch \initial + attribute \src "issuer_ls180.v:178011.9-178011.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:350" + switch \fsm_state$117 + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec2_cur_dec$next[63:0]$12599 \new_dec + case + assign $1\dec2_cur_dec$next[63:0]$12599 \dec2_cur_dec + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\dec2_cur_dec$next[63:0]$12600 64'0000000000000000000000000000000000000000000000000000000000000000 + case + assign $2\dec2_cur_dec$next[63:0]$12600 $1\dec2_cur_dec$next[63:0]$12599 + end + sync always + update \dec2_cur_dec$next $0\dec2_cur_dec$next[63:0]$12598 + end + attribute \src "issuer_ls180.v:178026.3-178036.6" + process $proc$issuer_ls180.v:178026$12601 + assign { } { } + assign { } { } + assign $0\new_tb[63:0] $1\new_tb[63:0] + attribute \src "issuer_ls180.v:178027.5-178027.29" + switch \initial + attribute \src "issuer_ls180.v:178027.9-178027.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:350" + switch \fsm_state$117 + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'11 + assign { } { } + assign $1\new_tb[63:0] \$121 [63:0] + case + assign $1\new_tb[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \new_tb $0\new_tb[63:0] + end + attribute \src "issuer_ls180.v:178037.3-178045.6" + process $proc$issuer_ls180.v:178037$12602 + assign { } { } + assign { } { } + assign $0\pc_ok_delay$next[0:0]$12603 $1\pc_ok_delay$next[0:0]$12604 + attribute \src "issuer_ls180.v:178038.5-178038.29" + switch \initial + attribute \src "issuer_ls180.v:178038.9-178038.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\pc_ok_delay$next[0:0]$12604 1'0 + case + assign $1\pc_ok_delay$next[0:0]$12604 \$23 + end + sync always + update \pc_ok_delay$next $0\pc_ok_delay$next[0:0]$12603 + end + attribute \src "issuer_ls180.v:178046.3-178061.6" + process $proc$issuer_ls180.v:178046$12605 + assign { } { } + assign { } { } + assign { } { } + assign $0\pc[63:0] $2\pc[63:0] + attribute \src "issuer_ls180.v:178047.5-178047.29" + switch \initial + attribute \src "issuer_ls180.v:178047.9-178047.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:176" + switch \pc_i_ok + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\pc[63:0] \pc_i + case + assign $1\pc[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:183" + switch \pc_ok_delay + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\pc[63:0] \core_cia__data_o + case + assign $2\pc[63:0] $1\pc[63:0] + end + sync always + update \pc $0\pc[63:0] + end + attribute \src "issuer_ls180.v:178062.3-178074.6" + process $proc$issuer_ls180.v:178062$12606 + assign { } { } + assign { } { } + assign $0\core_cia__ren[3:0] $1\core_cia__ren[3:0] + attribute \src "issuer_ls180.v:178063.5-178063.29" + switch \initial + attribute \src "issuer_ls180.v:178063.9-178063.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:176" + switch \pc_i_ok + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign $1\core_cia__ren[3:0] 4'0000 + attribute \src "issuer_ls180.v:0.0-0.0" + case + assign { } { } + assign $1\core_cia__ren[3:0] 4'0001 + end + sync always + update \core_cia__ren $0\core_cia__ren[3:0] + end + attribute \src "issuer_ls180.v:178075.3-178095.6" + process $proc$issuer_ls180.v:178075$12607 + assign { } { } + assign { } { } + assign $0\core_wen[3:0] $1\core_wen[3:0] + attribute \src "issuer_ls180.v:178076.5-178076.29" + switch \initial + attribute \src "issuer_ls180.v:178076.9-178076.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:214" + switch \fsm_state + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'11 + assign { } { } + assign $1\core_wen[3:0] $2\core_wen[3:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:280" + switch \$25 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\core_wen[3:0] $3\core_wen[3:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:284" + switch \$27 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\core_wen[3:0] 4'0001 + case + assign $3\core_wen[3:0] 4'0000 + end + case + assign $2\core_wen[3:0] 4'0000 + end + case + assign $1\core_wen[3:0] 4'0000 + end + sync always + update \core_wen $0\core_wen[3:0] + end + attribute \src "issuer_ls180.v:178096.3-178116.6" + process $proc$issuer_ls180.v:178096$12608 + assign { } { } + assign { } { } + assign $0\core_data_i[63:0] $1\core_data_i[63:0] + attribute \src "issuer_ls180.v:178097.5-178097.29" + switch \initial + attribute \src "issuer_ls180.v:178097.9-178097.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:214" + switch \fsm_state + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'11 + assign { } { } + assign $1\core_data_i[63:0] $2\core_data_i[63:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:280" + switch \$29 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\core_data_i[63:0] $3\core_data_i[63:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:284" + switch \$31 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\core_data_i[63:0] \nia + case + assign $3\core_data_i[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + case + assign $2\core_data_i[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + case + assign $1\core_data_i[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \core_data_i $0\core_data_i[63:0] + end + attribute \src "issuer_ls180.v:178117.3-178125.6" + process $proc$issuer_ls180.v:178117$12609 + assign { } { } + assign { } { } + assign $0\dec2_cur_eint$next[0:0]$12610 $1\dec2_cur_eint$next[0:0]$12611 + attribute \src "issuer_ls180.v:178118.5-178118.29" + switch \initial + attribute \src "issuer_ls180.v:178118.9-178118.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dec2_cur_eint$next[0:0]$12611 1'0 + case + assign $1\dec2_cur_eint$next[0:0]$12611 \xics_icp_core_irq_o + end + sync always + update \dec2_cur_eint$next $0\dec2_cur_eint$next[0:0]$12610 + end + attribute \src "issuer_ls180.v:178126.3-178141.6" + process $proc$issuer_ls180.v:178126$12612 + assign { } { } + assign { } { } + assign $0\core_msr__ren[3:0] $1\core_msr__ren[3:0] + attribute \src "issuer_ls180.v:178127.5-178127.29" + switch \initial + attribute \src "issuer_ls180.v:178127.9-178127.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:214" + switch \fsm_state + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\core_msr__ren[3:0] $2\core_msr__ren[3:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:222" + switch \$37 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\core_msr__ren[3:0] 4'0010 + case + assign $2\core_msr__ren[3:0] 4'0000 + end + case + assign $1\core_msr__ren[3:0] 4'0000 + end + sync always + update \core_msr__ren $0\core_msr__ren[3:0] + end + attribute \src "issuer_ls180.v:178142.3-178166.6" + process $proc$issuer_ls180.v:178142$12613 + assign { } { } + assign { } { } + assign { } { } + assign $0\pc_changed$next[0:0]$12614 $3\pc_changed$next[0:0]$12617 + attribute \src "issuer_ls180.v:178143.5-178143.29" + switch \initial + attribute \src "issuer_ls180.v:178143.9-178143.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:214" + switch \fsm_state + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\pc_changed$next[0:0]$12615 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'11 + assign { } { } + assign $1\pc_changed$next[0:0]$12615 $2\pc_changed$next[0:0]$12616 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:278" + switch \$39 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\pc_changed$next[0:0]$12616 1'1 + case + assign $2\pc_changed$next[0:0]$12616 \pc_changed + end + case + assign $1\pc_changed$next[0:0]$12615 \pc_changed + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\pc_changed$next[0:0]$12617 1'0 + case + assign $3\pc_changed$next[0:0]$12617 $1\pc_changed$next[0:0]$12615 + end + sync always + update \pc_changed$next $0\pc_changed$next[0:0]$12614 + end + attribute \src "issuer_ls180.v:178167.3-178273.6" + process $proc$issuer_ls180.v:178167$12618 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\core_asmcode$next[7:0]$12619 $1\core_asmcode$next[7:0]$12670 + assign $0\core_core_core_cia$next[63:0]$12620 $1\core_core_core_cia$next[63:0]$12671 + assign $0\core_core_core_cr_rd$next[7:0]$12621 $1\core_core_core_cr_rd$next[7:0]$12672 + assign { } { } + assign $0\core_core_core_cr_wr$next[7:0]$12623 $1\core_core_core_cr_wr$next[7:0]$12674 + assign $0\core_core_core_fn_unit$next[11:0]$12624 $1\core_core_core_fn_unit$next[11:0]$12675 + assign $0\core_core_core_input_carry$next[1:0]$12625 $1\core_core_core_input_carry$next[1:0]$12676 + assign $0\core_core_core_insn$next[31:0]$12626 $1\core_core_core_insn$next[31:0]$12677 + assign $0\core_core_core_insn_type$next[6:0]$12627 $1\core_core_core_insn_type$next[6:0]$12678 + assign $0\core_core_core_is_32bit$next[0:0]$12628 $1\core_core_core_is_32bit$next[0:0]$12679 + assign $0\core_core_core_msr$next[63:0]$12629 $1\core_core_core_msr$next[63:0]$12680 + assign $0\core_core_core_oe$next[0:0]$12630 $1\core_core_core_oe$next[0:0]$12681 + assign { } { } + assign $0\core_core_core_rc$next[0:0]$12632 $1\core_core_core_rc$next[0:0]$12683 + assign { } { } + assign $0\core_core_core_trapaddr$next[12:0]$12634 $1\core_core_core_trapaddr$next[12:0]$12685 + assign $0\core_core_core_traptype$next[6:0]$12635 $1\core_core_core_traptype$next[6:0]$12686 + assign $0\core_core_cr_in1$next[2:0]$12636 $1\core_core_cr_in1$next[2:0]$12687 + assign { } { } + assign $0\core_core_cr_in2$1$next[2:0]$12638 $1\core_core_cr_in2$1$next[2:0]$12689 + assign $0\core_core_cr_in2$next[2:0]$12639 $1\core_core_cr_in2$next[2:0]$12690 + assign { } { } + assign { } { } + assign $0\core_core_cr_out$next[2:0]$12642 $1\core_core_cr_out$next[2:0]$12693 + assign { } { } + assign $0\core_core_ea$next[4:0]$12644 $1\core_core_ea$next[4:0]$12695 + assign $0\core_core_fast1$next[2:0]$12645 $1\core_core_fast1$next[2:0]$12696 + assign { } { } + assign $0\core_core_fast2$next[2:0]$12647 $1\core_core_fast2$next[2:0]$12698 + assign { } { } + assign $0\core_core_fasto1$next[2:0]$12649 $1\core_core_fasto1$next[2:0]$12700 + assign $0\core_core_fasto2$next[2:0]$12650 $1\core_core_fasto2$next[2:0]$12701 + assign $0\core_core_lk$next[0:0]$12651 $1\core_core_lk$next[0:0]$12702 + assign $0\core_core_reg1$next[4:0]$12652 $1\core_core_reg1$next[4:0]$12703 + assign { } { } + assign $0\core_core_reg2$next[4:0]$12654 $1\core_core_reg2$next[4:0]$12705 + assign { } { } + assign $0\core_core_reg3$next[4:0]$12656 $1\core_core_reg3$next[4:0]$12707 + assign { } { } + assign $0\core_core_rego$next[4:0]$12658 $1\core_core_rego$next[4:0]$12709 + assign $0\core_core_spr1$next[9:0]$12659 $1\core_core_spr1$next[9:0]$12710 + assign { } { } + assign $0\core_core_spro$next[9:0]$12661 $1\core_core_spro$next[9:0]$12712 + assign $0\core_core_xer_in$next[2:0]$12662 $1\core_core_xer_in$next[2:0]$12713 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\core_xer_out$next[0:0]$12669 $1\core_xer_out$next[0:0]$12720 + assign $0\core_core_core_cr_rd_ok$next[0:0]$12622 $4\core_core_core_cr_rd_ok$next[0:0]$12823 + assign $0\core_core_core_oe_ok$next[0:0]$12631 $4\core_core_core_oe_ok$next[0:0]$12824 + assign $0\core_core_core_rc_ok$next[0:0]$12633 $4\core_core_core_rc_ok$next[0:0]$12825 + assign $0\core_core_cr_in1_ok$next[0:0]$12637 $4\core_core_cr_in1_ok$next[0:0]$12826 + assign $0\core_core_cr_in2_ok$2$next[0:0]$12640 $4\core_core_cr_in2_ok$2$next[0:0]$12827 + assign $0\core_core_cr_in2_ok$next[0:0]$12641 $4\core_core_cr_in2_ok$next[0:0]$12828 + assign $0\core_core_cr_wr_ok$next[0:0]$12643 $4\core_core_cr_wr_ok$next[0:0]$12829 + assign $0\core_core_fast1_ok$next[0:0]$12646 $4\core_core_fast1_ok$next[0:0]$12830 + assign $0\core_core_fast2_ok$next[0:0]$12648 $4\core_core_fast2_ok$next[0:0]$12831 + assign $0\core_core_reg1_ok$next[0:0]$12653 $4\core_core_reg1_ok$next[0:0]$12832 + assign $0\core_core_reg2_ok$next[0:0]$12655 $4\core_core_reg2_ok$next[0:0]$12833 + assign $0\core_core_reg3_ok$next[0:0]$12657 $4\core_core_reg3_ok$next[0:0]$12834 + assign $0\core_core_spr1_ok$next[0:0]$12660 $4\core_core_spr1_ok$next[0:0]$12835 + assign $0\core_cr_out_ok$next[0:0]$12663 $4\core_cr_out_ok$next[0:0]$12836 + assign $0\core_ea_ok$next[0:0]$12664 $4\core_ea_ok$next[0:0]$12837 + assign $0\core_fasto1_ok$next[0:0]$12665 $4\core_fasto1_ok$next[0:0]$12838 + assign $0\core_fasto2_ok$next[0:0]$12666 $4\core_fasto2_ok$next[0:0]$12839 + assign $0\core_rego_ok$next[0:0]$12667 $4\core_rego_ok$next[0:0]$12840 + assign $0\core_spro_ok$next[0:0]$12668 $4\core_spro_ok$next[0:0]$12841 + attribute \src "issuer_ls180.v:178168.5-178168.29" + switch \initial + attribute \src "issuer_ls180.v:178168.9-178168.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:214" + switch \fsm_state + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'00 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { $1\core_core_core_is_32bit$next[0:0]$12679 $1\core_core_cr_wr_ok$next[0:0]$12694 $1\core_core_core_cr_wr$next[7:0]$12674 $1\core_core_core_cr_rd_ok$next[0:0]$12673 $1\core_core_core_cr_rd$next[7:0]$12672 $1\core_core_core_trapaddr$next[12:0]$12685 $1\core_core_core_traptype$next[6:0]$12686 $1\core_core_core_input_carry$next[1:0]$12676 $1\core_core_core_oe_ok$next[0:0]$12682 $1\core_core_core_oe$next[0:0]$12681 $1\core_core_core_rc_ok$next[0:0]$12684 $1\core_core_core_rc$next[0:0]$12683 $1\core_core_lk$next[0:0]$12702 $1\core_core_core_fn_unit$next[11:0]$12675 $1\core_core_core_insn_type$next[6:0]$12678 $1\core_core_core_insn$next[31:0]$12677 $1\core_core_core_cia$next[63:0]$12671 $1\core_core_core_msr$next[63:0]$12680 $1\core_cr_out_ok$next[0:0]$12714 $1\core_core_cr_out$next[2:0]$12693 $1\core_core_cr_in2_ok$2$next[0:0]$12691 $1\core_core_cr_in2$1$next[2:0]$12689 $1\core_core_cr_in2_ok$next[0:0]$12692 $1\core_core_cr_in2$next[2:0]$12690 $1\core_core_cr_in1_ok$next[0:0]$12688 $1\core_core_cr_in1$next[2:0]$12687 $1\core_fasto2_ok$next[0:0]$12717 $1\core_core_fasto2$next[2:0]$12701 $1\core_fasto1_ok$next[0:0]$12716 $1\core_core_fasto1$next[2:0]$12700 $1\core_core_fast2_ok$next[0:0]$12699 $1\core_core_fast2$next[2:0]$12698 $1\core_core_fast1_ok$next[0:0]$12697 $1\core_core_fast1$next[2:0]$12696 $1\core_xer_out$next[0:0]$12720 $1\core_core_xer_in$next[2:0]$12713 $1\core_core_spr1_ok$next[0:0]$12711 $1\core_core_spr1$next[9:0]$12710 $1\core_spro_ok$next[0:0]$12719 $1\core_core_spro$next[9:0]$12712 $1\core_core_reg3_ok$next[0:0]$12708 $1\core_core_reg3$next[4:0]$12707 $1\core_core_reg2_ok$next[0:0]$12706 $1\core_core_reg2$next[4:0]$12705 $1\core_core_reg1_ok$next[0:0]$12704 $1\core_core_reg1$next[4:0]$12703 $1\core_ea_ok$next[0:0]$12715 $1\core_core_ea$next[4:0]$12695 $1\core_rego_ok$next[0:0]$12718 $1\core_core_rego$next[4:0]$12709 $1\core_asmcode$next[7:0]$12670 } 321'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'01 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\core_asmcode$next[7:0]$12670 $2\core_asmcode$next[7:0]$12721 + assign $1\core_core_core_cia$next[63:0]$12671 $2\core_core_core_cia$next[63:0]$12722 + assign $1\core_core_core_cr_rd$next[7:0]$12672 $2\core_core_core_cr_rd$next[7:0]$12723 + assign $1\core_core_core_cr_rd_ok$next[0:0]$12673 $2\core_core_core_cr_rd_ok$next[0:0]$12724 + assign $1\core_core_core_cr_wr$next[7:0]$12674 $2\core_core_core_cr_wr$next[7:0]$12725 + assign $1\core_core_core_fn_unit$next[11:0]$12675 $2\core_core_core_fn_unit$next[11:0]$12726 + assign $1\core_core_core_input_carry$next[1:0]$12676 $2\core_core_core_input_carry$next[1:0]$12727 + assign $1\core_core_core_insn$next[31:0]$12677 $2\core_core_core_insn$next[31:0]$12728 + assign $1\core_core_core_insn_type$next[6:0]$12678 $2\core_core_core_insn_type$next[6:0]$12729 + assign $1\core_core_core_is_32bit$next[0:0]$12679 $2\core_core_core_is_32bit$next[0:0]$12730 + assign $1\core_core_core_msr$next[63:0]$12680 $2\core_core_core_msr$next[63:0]$12731 + assign $1\core_core_core_oe$next[0:0]$12681 $2\core_core_core_oe$next[0:0]$12732 + assign $1\core_core_core_oe_ok$next[0:0]$12682 $2\core_core_core_oe_ok$next[0:0]$12733 + assign $1\core_core_core_rc$next[0:0]$12683 $2\core_core_core_rc$next[0:0]$12734 + assign $1\core_core_core_rc_ok$next[0:0]$12684 $2\core_core_core_rc_ok$next[0:0]$12735 + assign $1\core_core_core_trapaddr$next[12:0]$12685 $2\core_core_core_trapaddr$next[12:0]$12736 + assign $1\core_core_core_traptype$next[6:0]$12686 $2\core_core_core_traptype$next[6:0]$12737 + assign $1\core_core_cr_in1$next[2:0]$12687 $2\core_core_cr_in1$next[2:0]$12738 + assign $1\core_core_cr_in1_ok$next[0:0]$12688 $2\core_core_cr_in1_ok$next[0:0]$12739 + assign $1\core_core_cr_in2$1$next[2:0]$12689 $2\core_core_cr_in2$1$next[2:0]$12740 + assign $1\core_core_cr_in2$next[2:0]$12690 $2\core_core_cr_in2$next[2:0]$12741 + assign $1\core_core_cr_in2_ok$2$next[0:0]$12691 $2\core_core_cr_in2_ok$2$next[0:0]$12742 + assign $1\core_core_cr_in2_ok$next[0:0]$12692 $2\core_core_cr_in2_ok$next[0:0]$12743 + assign $1\core_core_cr_out$next[2:0]$12693 $2\core_core_cr_out$next[2:0]$12744 + assign $1\core_core_cr_wr_ok$next[0:0]$12694 $2\core_core_cr_wr_ok$next[0:0]$12745 + assign $1\core_core_ea$next[4:0]$12695 $2\core_core_ea$next[4:0]$12746 + assign $1\core_core_fast1$next[2:0]$12696 $2\core_core_fast1$next[2:0]$12747 + assign $1\core_core_fast1_ok$next[0:0]$12697 $2\core_core_fast1_ok$next[0:0]$12748 + assign $1\core_core_fast2$next[2:0]$12698 $2\core_core_fast2$next[2:0]$12749 + assign $1\core_core_fast2_ok$next[0:0]$12699 $2\core_core_fast2_ok$next[0:0]$12750 + assign $1\core_core_fasto1$next[2:0]$12700 $2\core_core_fasto1$next[2:0]$12751 + assign $1\core_core_fasto2$next[2:0]$12701 $2\core_core_fasto2$next[2:0]$12752 + assign $1\core_core_lk$next[0:0]$12702 $2\core_core_lk$next[0:0]$12753 + assign $1\core_core_reg1$next[4:0]$12703 $2\core_core_reg1$next[4:0]$12754 + assign $1\core_core_reg1_ok$next[0:0]$12704 $2\core_core_reg1_ok$next[0:0]$12755 + assign $1\core_core_reg2$next[4:0]$12705 $2\core_core_reg2$next[4:0]$12756 + assign $1\core_core_reg2_ok$next[0:0]$12706 $2\core_core_reg2_ok$next[0:0]$12757 + assign $1\core_core_reg3$next[4:0]$12707 $2\core_core_reg3$next[4:0]$12758 + assign $1\core_core_reg3_ok$next[0:0]$12708 $2\core_core_reg3_ok$next[0:0]$12759 + assign $1\core_core_rego$next[4:0]$12709 $2\core_core_rego$next[4:0]$12760 + assign $1\core_core_spr1$next[9:0]$12710 $2\core_core_spr1$next[9:0]$12761 + assign $1\core_core_spr1_ok$next[0:0]$12711 $2\core_core_spr1_ok$next[0:0]$12762 + assign $1\core_core_spro$next[9:0]$12712 $2\core_core_spro$next[9:0]$12763 + assign $1\core_core_xer_in$next[2:0]$12713 $2\core_core_xer_in$next[2:0]$12764 + assign $1\core_cr_out_ok$next[0:0]$12714 $2\core_cr_out_ok$next[0:0]$12765 + assign $1\core_ea_ok$next[0:0]$12715 $2\core_ea_ok$next[0:0]$12766 + assign $1\core_fasto1_ok$next[0:0]$12716 $2\core_fasto1_ok$next[0:0]$12767 + assign $1\core_fasto2_ok$next[0:0]$12717 $2\core_fasto2_ok$next[0:0]$12768 + assign $1\core_rego_ok$next[0:0]$12718 $2\core_rego_ok$next[0:0]$12769 + assign $1\core_spro_ok$next[0:0]$12719 $2\core_spro_ok$next[0:0]$12770 + assign $1\core_xer_out$next[0:0]$12720 $2\core_xer_out$next[0:0]$12771 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:247" + switch \imem_f_busy_o + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign $2\core_asmcode$next[7:0]$12721 \core_asmcode + assign $2\core_core_core_cia$next[63:0]$12722 \core_core_core_cia + assign $2\core_core_core_cr_rd$next[7:0]$12723 \core_core_core_cr_rd + assign $2\core_core_core_cr_rd_ok$next[0:0]$12724 \core_core_core_cr_rd_ok + assign $2\core_core_core_cr_wr$next[7:0]$12725 \core_core_core_cr_wr + assign $2\core_core_core_fn_unit$next[11:0]$12726 \core_core_core_fn_unit + assign $2\core_core_core_input_carry$next[1:0]$12727 \core_core_core_input_carry + assign $2\core_core_core_insn$next[31:0]$12728 \core_core_core_insn + assign $2\core_core_core_insn_type$next[6:0]$12729 \core_core_core_insn_type + assign $2\core_core_core_is_32bit$next[0:0]$12730 \core_core_core_is_32bit + assign $2\core_core_core_msr$next[63:0]$12731 \core_core_core_msr + assign $2\core_core_core_oe$next[0:0]$12732 \core_core_core_oe + assign $2\core_core_core_oe_ok$next[0:0]$12733 \core_core_core_oe_ok + assign $2\core_core_core_rc$next[0:0]$12734 \core_core_core_rc + assign $2\core_core_core_rc_ok$next[0:0]$12735 \core_core_core_rc_ok + assign $2\core_core_core_trapaddr$next[12:0]$12736 \core_core_core_trapaddr + assign $2\core_core_core_traptype$next[6:0]$12737 \core_core_core_traptype + assign $2\core_core_cr_in1$next[2:0]$12738 \core_core_cr_in1 + assign $2\core_core_cr_in1_ok$next[0:0]$12739 \core_core_cr_in1_ok + assign $2\core_core_cr_in2$1$next[2:0]$12740 \core_core_cr_in2$1 + assign $2\core_core_cr_in2$next[2:0]$12741 \core_core_cr_in2 + assign $2\core_core_cr_in2_ok$2$next[0:0]$12742 \core_core_cr_in2_ok$2 + assign $2\core_core_cr_in2_ok$next[0:0]$12743 \core_core_cr_in2_ok + assign $2\core_core_cr_out$next[2:0]$12744 \core_core_cr_out + assign $2\core_core_cr_wr_ok$next[0:0]$12745 \core_core_cr_wr_ok + assign $2\core_core_ea$next[4:0]$12746 \core_core_ea + assign $2\core_core_fast1$next[2:0]$12747 \core_core_fast1 + assign $2\core_core_fast1_ok$next[0:0]$12748 \core_core_fast1_ok + assign $2\core_core_fast2$next[2:0]$12749 \core_core_fast2 + assign $2\core_core_fast2_ok$next[0:0]$12750 \core_core_fast2_ok + assign $2\core_core_fasto1$next[2:0]$12751 \core_core_fasto1 + assign $2\core_core_fasto2$next[2:0]$12752 \core_core_fasto2 + assign $2\core_core_lk$next[0:0]$12753 \core_core_lk + assign $2\core_core_reg1$next[4:0]$12754 \core_core_reg1 + assign $2\core_core_reg1_ok$next[0:0]$12755 \core_core_reg1_ok + assign $2\core_core_reg2$next[4:0]$12756 \core_core_reg2 + assign $2\core_core_reg2_ok$next[0:0]$12757 \core_core_reg2_ok + assign $2\core_core_reg3$next[4:0]$12758 \core_core_reg3 + assign $2\core_core_reg3_ok$next[0:0]$12759 \core_core_reg3_ok + assign $2\core_core_rego$next[4:0]$12760 \core_core_rego + assign $2\core_core_spr1$next[9:0]$12761 \core_core_spr1 + assign $2\core_core_spr1_ok$next[0:0]$12762 \core_core_spr1_ok + assign $2\core_core_spro$next[9:0]$12763 \core_core_spro + assign $2\core_core_xer_in$next[2:0]$12764 \core_core_xer_in + assign $2\core_cr_out_ok$next[0:0]$12765 \core_cr_out_ok + assign $2\core_ea_ok$next[0:0]$12766 \core_ea_ok + assign $2\core_fasto1_ok$next[0:0]$12767 \core_fasto1_ok + assign $2\core_fasto2_ok$next[0:0]$12768 \core_fasto2_ok + assign $2\core_rego_ok$next[0:0]$12769 \core_rego_ok + assign $2\core_spro_ok$next[0:0]$12770 \core_spro_ok + assign $2\core_xer_out$next[0:0]$12771 \core_xer_out + attribute \src "issuer_ls180.v:0.0-0.0" + case + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { $2\core_core_core_is_32bit$next[0:0]$12730 $2\core_core_cr_wr_ok$next[0:0]$12745 $2\core_core_core_cr_wr$next[7:0]$12725 $2\core_core_core_cr_rd_ok$next[0:0]$12724 $2\core_core_core_cr_rd$next[7:0]$12723 $2\core_core_core_trapaddr$next[12:0]$12736 $2\core_core_core_traptype$next[6:0]$12737 $2\core_core_core_input_carry$next[1:0]$12727 $2\core_core_core_oe_ok$next[0:0]$12733 $2\core_core_core_oe$next[0:0]$12732 $2\core_core_core_rc_ok$next[0:0]$12735 $2\core_core_core_rc$next[0:0]$12734 $2\core_core_lk$next[0:0]$12753 $2\core_core_core_fn_unit$next[11:0]$12726 $2\core_core_core_insn_type$next[6:0]$12729 $2\core_core_core_insn$next[31:0]$12728 $2\core_core_core_cia$next[63:0]$12722 $2\core_core_core_msr$next[63:0]$12731 $2\core_cr_out_ok$next[0:0]$12765 $2\core_core_cr_out$next[2:0]$12744 $2\core_core_cr_in2_ok$2$next[0:0]$12742 $2\core_core_cr_in2$1$next[2:0]$12740 $2\core_core_cr_in2_ok$next[0:0]$12743 $2\core_core_cr_in2$next[2:0]$12741 $2\core_core_cr_in1_ok$next[0:0]$12739 $2\core_core_cr_in1$next[2:0]$12738 $2\core_fasto2_ok$next[0:0]$12768 $2\core_core_fasto2$next[2:0]$12752 $2\core_fasto1_ok$next[0:0]$12767 $2\core_core_fasto1$next[2:0]$12751 $2\core_core_fast2_ok$next[0:0]$12750 $2\core_core_fast2$next[2:0]$12749 $2\core_core_fast1_ok$next[0:0]$12748 $2\core_core_fast1$next[2:0]$12747 $2\core_xer_out$next[0:0]$12771 $2\core_core_xer_in$next[2:0]$12764 $2\core_core_spr1_ok$next[0:0]$12762 $2\core_core_spr1$next[9:0]$12761 $2\core_spro_ok$next[0:0]$12770 $2\core_core_spro$next[9:0]$12763 $2\core_core_reg3_ok$next[0:0]$12759 $2\core_core_reg3$next[4:0]$12758 $2\core_core_reg2_ok$next[0:0]$12757 $2\core_core_reg2$next[4:0]$12756 $2\core_core_reg1_ok$next[0:0]$12755 $2\core_core_reg1$next[4:0]$12754 $2\core_ea_ok$next[0:0]$12766 $2\core_core_ea$next[4:0]$12746 $2\core_rego_ok$next[0:0]$12769 $2\core_core_rego$next[4:0]$12760 $2\core_asmcode$next[7:0]$12721 } { \dec2_is_32bit \dec2_cr_wr_ok \dec2_cr_wr \dec2_cr_rd_ok \dec2_cr_rd \dec2_trapaddr \dec2_traptype \dec2_input_carry \dec2_oe_ok \dec2_oe \dec2_rc_ok \dec2_rc \dec2_lk \dec2_fn_unit \dec2_insn_type \dec2_insn \dec2_cia \dec2_msr \dec2_cr_out_ok \dec2_cr_out \dec2_cr_in2_ok$6 \dec2_cr_in2$5 \dec2_cr_in2_ok \dec2_cr_in2 \dec2_cr_in1_ok \dec2_cr_in1 \dec2_fasto2_ok \dec2_fasto2 \dec2_fasto1_ok \dec2_fasto1 \dec2_fast2_ok \dec2_fast2 \dec2_fast1_ok \dec2_fast1 \dec2_xer_out \dec2_xer_in \dec2_spr1_ok \dec2_spr1 \dec2_spro_ok \dec2_spro \dec2_reg3_ok \dec2_reg3 \dec2_reg2_ok \dec2_reg2 \dec2_reg1_ok \dec2_reg1 \dec2_ea_ok \dec2_ea \dec2_rego_ok \dec2_rego \dec2_asmcode } + end + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'11 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\core_asmcode$next[7:0]$12670 $3\core_asmcode$next[7:0]$12772 + assign $1\core_core_core_cia$next[63:0]$12671 $3\core_core_core_cia$next[63:0]$12773 + assign $1\core_core_core_cr_rd$next[7:0]$12672 $3\core_core_core_cr_rd$next[7:0]$12774 + assign $1\core_core_core_cr_rd_ok$next[0:0]$12673 $3\core_core_core_cr_rd_ok$next[0:0]$12775 + assign $1\core_core_core_cr_wr$next[7:0]$12674 $3\core_core_core_cr_wr$next[7:0]$12776 + assign $1\core_core_core_fn_unit$next[11:0]$12675 $3\core_core_core_fn_unit$next[11:0]$12777 + assign $1\core_core_core_input_carry$next[1:0]$12676 $3\core_core_core_input_carry$next[1:0]$12778 + assign $1\core_core_core_insn$next[31:0]$12677 $3\core_core_core_insn$next[31:0]$12779 + assign $1\core_core_core_insn_type$next[6:0]$12678 $3\core_core_core_insn_type$next[6:0]$12780 + assign $1\core_core_core_is_32bit$next[0:0]$12679 $3\core_core_core_is_32bit$next[0:0]$12781 + assign $1\core_core_core_msr$next[63:0]$12680 $3\core_core_core_msr$next[63:0]$12782 + assign $1\core_core_core_oe$next[0:0]$12681 $3\core_core_core_oe$next[0:0]$12783 + assign $1\core_core_core_oe_ok$next[0:0]$12682 $3\core_core_core_oe_ok$next[0:0]$12784 + assign $1\core_core_core_rc$next[0:0]$12683 $3\core_core_core_rc$next[0:0]$12785 + assign $1\core_core_core_rc_ok$next[0:0]$12684 $3\core_core_core_rc_ok$next[0:0]$12786 + assign $1\core_core_core_trapaddr$next[12:0]$12685 $3\core_core_core_trapaddr$next[12:0]$12787 + assign $1\core_core_core_traptype$next[6:0]$12686 $3\core_core_core_traptype$next[6:0]$12788 + assign $1\core_core_cr_in1$next[2:0]$12687 $3\core_core_cr_in1$next[2:0]$12789 + assign $1\core_core_cr_in1_ok$next[0:0]$12688 $3\core_core_cr_in1_ok$next[0:0]$12790 + assign $1\core_core_cr_in2$1$next[2:0]$12689 $3\core_core_cr_in2$1$next[2:0]$12791 + assign $1\core_core_cr_in2$next[2:0]$12690 $3\core_core_cr_in2$next[2:0]$12792 + assign $1\core_core_cr_in2_ok$2$next[0:0]$12691 $3\core_core_cr_in2_ok$2$next[0:0]$12793 + assign $1\core_core_cr_in2_ok$next[0:0]$12692 $3\core_core_cr_in2_ok$next[0:0]$12794 + assign $1\core_core_cr_out$next[2:0]$12693 $3\core_core_cr_out$next[2:0]$12795 + assign $1\core_core_cr_wr_ok$next[0:0]$12694 $3\core_core_cr_wr_ok$next[0:0]$12796 + assign $1\core_core_ea$next[4:0]$12695 $3\core_core_ea$next[4:0]$12797 + assign $1\core_core_fast1$next[2:0]$12696 $3\core_core_fast1$next[2:0]$12798 + assign $1\core_core_fast1_ok$next[0:0]$12697 $3\core_core_fast1_ok$next[0:0]$12799 + assign $1\core_core_fast2$next[2:0]$12698 $3\core_core_fast2$next[2:0]$12800 + assign $1\core_core_fast2_ok$next[0:0]$12699 $3\core_core_fast2_ok$next[0:0]$12801 + assign $1\core_core_fasto1$next[2:0]$12700 $3\core_core_fasto1$next[2:0]$12802 + assign $1\core_core_fasto2$next[2:0]$12701 $3\core_core_fasto2$next[2:0]$12803 + assign $1\core_core_lk$next[0:0]$12702 $3\core_core_lk$next[0:0]$12804 + assign $1\core_core_reg1$next[4:0]$12703 $3\core_core_reg1$next[4:0]$12805 + assign $1\core_core_reg1_ok$next[0:0]$12704 $3\core_core_reg1_ok$next[0:0]$12806 + assign $1\core_core_reg2$next[4:0]$12705 $3\core_core_reg2$next[4:0]$12807 + assign $1\core_core_reg2_ok$next[0:0]$12706 $3\core_core_reg2_ok$next[0:0]$12808 + assign $1\core_core_reg3$next[4:0]$12707 $3\core_core_reg3$next[4:0]$12809 + assign $1\core_core_reg3_ok$next[0:0]$12708 $3\core_core_reg3_ok$next[0:0]$12810 + assign $1\core_core_rego$next[4:0]$12709 $3\core_core_rego$next[4:0]$12811 + assign $1\core_core_spr1$next[9:0]$12710 $3\core_core_spr1$next[9:0]$12812 + assign $1\core_core_spr1_ok$next[0:0]$12711 $3\core_core_spr1_ok$next[0:0]$12813 + assign $1\core_core_spro$next[9:0]$12712 $3\core_core_spro$next[9:0]$12814 + assign $1\core_core_xer_in$next[2:0]$12713 $3\core_core_xer_in$next[2:0]$12815 + assign $1\core_cr_out_ok$next[0:0]$12714 $3\core_cr_out_ok$next[0:0]$12816 + assign $1\core_ea_ok$next[0:0]$12715 $3\core_ea_ok$next[0:0]$12817 + assign $1\core_fasto1_ok$next[0:0]$12716 $3\core_fasto1_ok$next[0:0]$12818 + assign $1\core_fasto2_ok$next[0:0]$12717 $3\core_fasto2_ok$next[0:0]$12819 + assign $1\core_rego_ok$next[0:0]$12718 $3\core_rego_ok$next[0:0]$12820 + assign $1\core_spro_ok$next[0:0]$12719 $3\core_spro_ok$next[0:0]$12821 + assign $1\core_xer_out$next[0:0]$12720 $3\core_xer_out$next[0:0]$12822 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:280" + switch \$43 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { $3\core_core_core_is_32bit$next[0:0]$12781 $3\core_core_cr_wr_ok$next[0:0]$12796 $3\core_core_core_cr_wr$next[7:0]$12776 $3\core_core_core_cr_rd_ok$next[0:0]$12775 $3\core_core_core_cr_rd$next[7:0]$12774 $3\core_core_core_trapaddr$next[12:0]$12787 $3\core_core_core_traptype$next[6:0]$12788 $3\core_core_core_input_carry$next[1:0]$12778 $3\core_core_core_oe_ok$next[0:0]$12784 $3\core_core_core_oe$next[0:0]$12783 $3\core_core_core_rc_ok$next[0:0]$12786 $3\core_core_core_rc$next[0:0]$12785 $3\core_core_lk$next[0:0]$12804 $3\core_core_core_fn_unit$next[11:0]$12777 $3\core_core_core_insn_type$next[6:0]$12780 $3\core_core_core_insn$next[31:0]$12779 $3\core_core_core_cia$next[63:0]$12773 $3\core_core_core_msr$next[63:0]$12782 $3\core_cr_out_ok$next[0:0]$12816 $3\core_core_cr_out$next[2:0]$12795 $3\core_core_cr_in2_ok$2$next[0:0]$12793 $3\core_core_cr_in2$1$next[2:0]$12791 $3\core_core_cr_in2_ok$next[0:0]$12794 $3\core_core_cr_in2$next[2:0]$12792 $3\core_core_cr_in1_ok$next[0:0]$12790 $3\core_core_cr_in1$next[2:0]$12789 $3\core_fasto2_ok$next[0:0]$12819 $3\core_core_fasto2$next[2:0]$12803 $3\core_fasto1_ok$next[0:0]$12818 $3\core_core_fasto1$next[2:0]$12802 $3\core_core_fast2_ok$next[0:0]$12801 $3\core_core_fast2$next[2:0]$12800 $3\core_core_fast1_ok$next[0:0]$12799 $3\core_core_fast1$next[2:0]$12798 $3\core_xer_out$next[0:0]$12822 $3\core_core_xer_in$next[2:0]$12815 $3\core_core_spr1_ok$next[0:0]$12813 $3\core_core_spr1$next[9:0]$12812 $3\core_spro_ok$next[0:0]$12821 $3\core_core_spro$next[9:0]$12814 $3\core_core_reg3_ok$next[0:0]$12810 $3\core_core_reg3$next[4:0]$12809 $3\core_core_reg2_ok$next[0:0]$12808 $3\core_core_reg2$next[4:0]$12807 $3\core_core_reg1_ok$next[0:0]$12806 $3\core_core_reg1$next[4:0]$12805 $3\core_ea_ok$next[0:0]$12817 $3\core_core_ea$next[4:0]$12797 $3\core_rego_ok$next[0:0]$12820 $3\core_core_rego$next[4:0]$12811 $3\core_asmcode$next[7:0]$12772 } 321'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 + case + assign $3\core_asmcode$next[7:0]$12772 \core_asmcode + assign $3\core_core_core_cia$next[63:0]$12773 \core_core_core_cia + assign $3\core_core_core_cr_rd$next[7:0]$12774 \core_core_core_cr_rd + assign $3\core_core_core_cr_rd_ok$next[0:0]$12775 \core_core_core_cr_rd_ok + assign $3\core_core_core_cr_wr$next[7:0]$12776 \core_core_core_cr_wr + assign $3\core_core_core_fn_unit$next[11:0]$12777 \core_core_core_fn_unit + assign $3\core_core_core_input_carry$next[1:0]$12778 \core_core_core_input_carry + assign $3\core_core_core_insn$next[31:0]$12779 \core_core_core_insn + assign $3\core_core_core_insn_type$next[6:0]$12780 \core_core_core_insn_type + assign $3\core_core_core_is_32bit$next[0:0]$12781 \core_core_core_is_32bit + assign $3\core_core_core_msr$next[63:0]$12782 \core_core_core_msr + assign $3\core_core_core_oe$next[0:0]$12783 \core_core_core_oe + assign $3\core_core_core_oe_ok$next[0:0]$12784 \core_core_core_oe_ok + assign $3\core_core_core_rc$next[0:0]$12785 \core_core_core_rc + assign $3\core_core_core_rc_ok$next[0:0]$12786 \core_core_core_rc_ok + assign $3\core_core_core_trapaddr$next[12:0]$12787 \core_core_core_trapaddr + assign $3\core_core_core_traptype$next[6:0]$12788 \core_core_core_traptype + assign $3\core_core_cr_in1$next[2:0]$12789 \core_core_cr_in1 + assign $3\core_core_cr_in1_ok$next[0:0]$12790 \core_core_cr_in1_ok + assign $3\core_core_cr_in2$1$next[2:0]$12791 \core_core_cr_in2$1 + assign $3\core_core_cr_in2$next[2:0]$12792 \core_core_cr_in2 + assign $3\core_core_cr_in2_ok$2$next[0:0]$12793 \core_core_cr_in2_ok$2 + assign $3\core_core_cr_in2_ok$next[0:0]$12794 \core_core_cr_in2_ok + assign $3\core_core_cr_out$next[2:0]$12795 \core_core_cr_out + assign $3\core_core_cr_wr_ok$next[0:0]$12796 \core_core_cr_wr_ok + assign $3\core_core_ea$next[4:0]$12797 \core_core_ea + assign $3\core_core_fast1$next[2:0]$12798 \core_core_fast1 + assign $3\core_core_fast1_ok$next[0:0]$12799 \core_core_fast1_ok + assign $3\core_core_fast2$next[2:0]$12800 \core_core_fast2 + assign $3\core_core_fast2_ok$next[0:0]$12801 \core_core_fast2_ok + assign $3\core_core_fasto1$next[2:0]$12802 \core_core_fasto1 + assign $3\core_core_fasto2$next[2:0]$12803 \core_core_fasto2 + assign $3\core_core_lk$next[0:0]$12804 \core_core_lk + assign $3\core_core_reg1$next[4:0]$12805 \core_core_reg1 + assign $3\core_core_reg1_ok$next[0:0]$12806 \core_core_reg1_ok + assign $3\core_core_reg2$next[4:0]$12807 \core_core_reg2 + assign $3\core_core_reg2_ok$next[0:0]$12808 \core_core_reg2_ok + assign $3\core_core_reg3$next[4:0]$12809 \core_core_reg3 + assign $3\core_core_reg3_ok$next[0:0]$12810 \core_core_reg3_ok + assign $3\core_core_rego$next[4:0]$12811 \core_core_rego + assign $3\core_core_spr1$next[9:0]$12812 \core_core_spr1 + assign $3\core_core_spr1_ok$next[0:0]$12813 \core_core_spr1_ok + assign $3\core_core_spro$next[9:0]$12814 \core_core_spro + assign $3\core_core_xer_in$next[2:0]$12815 \core_core_xer_in + assign $3\core_cr_out_ok$next[0:0]$12816 \core_cr_out_ok + assign $3\core_ea_ok$next[0:0]$12817 \core_ea_ok + assign $3\core_fasto1_ok$next[0:0]$12818 \core_fasto1_ok + assign $3\core_fasto2_ok$next[0:0]$12819 \core_fasto2_ok + assign $3\core_rego_ok$next[0:0]$12820 \core_rego_ok + assign $3\core_spro_ok$next[0:0]$12821 \core_spro_ok + assign $3\core_xer_out$next[0:0]$12822 \core_xer_out + end + case + assign $1\core_asmcode$next[7:0]$12670 \core_asmcode + assign $1\core_core_core_cia$next[63:0]$12671 \core_core_core_cia + assign $1\core_core_core_cr_rd$next[7:0]$12672 \core_core_core_cr_rd + assign $1\core_core_core_cr_rd_ok$next[0:0]$12673 \core_core_core_cr_rd_ok + assign $1\core_core_core_cr_wr$next[7:0]$12674 \core_core_core_cr_wr + assign $1\core_core_core_fn_unit$next[11:0]$12675 \core_core_core_fn_unit + assign $1\core_core_core_input_carry$next[1:0]$12676 \core_core_core_input_carry + assign $1\core_core_core_insn$next[31:0]$12677 \core_core_core_insn + assign $1\core_core_core_insn_type$next[6:0]$12678 \core_core_core_insn_type + assign $1\core_core_core_is_32bit$next[0:0]$12679 \core_core_core_is_32bit + assign $1\core_core_core_msr$next[63:0]$12680 \core_core_core_msr + assign $1\core_core_core_oe$next[0:0]$12681 \core_core_core_oe + assign $1\core_core_core_oe_ok$next[0:0]$12682 \core_core_core_oe_ok + assign $1\core_core_core_rc$next[0:0]$12683 \core_core_core_rc + assign $1\core_core_core_rc_ok$next[0:0]$12684 \core_core_core_rc_ok + assign $1\core_core_core_trapaddr$next[12:0]$12685 \core_core_core_trapaddr + assign $1\core_core_core_traptype$next[6:0]$12686 \core_core_core_traptype + assign $1\core_core_cr_in1$next[2:0]$12687 \core_core_cr_in1 + assign $1\core_core_cr_in1_ok$next[0:0]$12688 \core_core_cr_in1_ok + assign $1\core_core_cr_in2$1$next[2:0]$12689 \core_core_cr_in2$1 + assign $1\core_core_cr_in2$next[2:0]$12690 \core_core_cr_in2 + assign $1\core_core_cr_in2_ok$2$next[0:0]$12691 \core_core_cr_in2_ok$2 + assign $1\core_core_cr_in2_ok$next[0:0]$12692 \core_core_cr_in2_ok + assign $1\core_core_cr_out$next[2:0]$12693 \core_core_cr_out + assign $1\core_core_cr_wr_ok$next[0:0]$12694 \core_core_cr_wr_ok + assign $1\core_core_ea$next[4:0]$12695 \core_core_ea + assign $1\core_core_fast1$next[2:0]$12696 \core_core_fast1 + assign $1\core_core_fast1_ok$next[0:0]$12697 \core_core_fast1_ok + assign $1\core_core_fast2$next[2:0]$12698 \core_core_fast2 + assign $1\core_core_fast2_ok$next[0:0]$12699 \core_core_fast2_ok + assign $1\core_core_fasto1$next[2:0]$12700 \core_core_fasto1 + assign $1\core_core_fasto2$next[2:0]$12701 \core_core_fasto2 + assign $1\core_core_lk$next[0:0]$12702 \core_core_lk + assign $1\core_core_reg1$next[4:0]$12703 \core_core_reg1 + assign $1\core_core_reg1_ok$next[0:0]$12704 \core_core_reg1_ok + assign $1\core_core_reg2$next[4:0]$12705 \core_core_reg2 + assign $1\core_core_reg2_ok$next[0:0]$12706 \core_core_reg2_ok + assign $1\core_core_reg3$next[4:0]$12707 \core_core_reg3 + assign $1\core_core_reg3_ok$next[0:0]$12708 \core_core_reg3_ok + assign $1\core_core_rego$next[4:0]$12709 \core_core_rego + assign $1\core_core_spr1$next[9:0]$12710 \core_core_spr1 + assign $1\core_core_spr1_ok$next[0:0]$12711 \core_core_spr1_ok + assign $1\core_core_spro$next[9:0]$12712 \core_core_spro + assign $1\core_core_xer_in$next[2:0]$12713 \core_core_xer_in + assign $1\core_cr_out_ok$next[0:0]$12714 \core_cr_out_ok + assign $1\core_ea_ok$next[0:0]$12715 \core_ea_ok + assign $1\core_fasto1_ok$next[0:0]$12716 \core_fasto1_ok + assign $1\core_fasto2_ok$next[0:0]$12717 \core_fasto2_ok + assign $1\core_rego_ok$next[0:0]$12718 \core_rego_ok + assign $1\core_spro_ok$next[0:0]$12719 \core_spro_ok + assign $1\core_xer_out$next[0:0]$12720 \core_xer_out + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $4\core_rego_ok$next[0:0]$12840 1'0 + assign $4\core_ea_ok$next[0:0]$12837 1'0 + assign $4\core_core_reg1_ok$next[0:0]$12832 1'0 + assign $4\core_core_reg2_ok$next[0:0]$12833 1'0 + assign $4\core_core_reg3_ok$next[0:0]$12834 1'0 + assign $4\core_spro_ok$next[0:0]$12841 1'0 + assign $4\core_core_spr1_ok$next[0:0]$12835 1'0 + assign $4\core_core_fast1_ok$next[0:0]$12830 1'0 + assign $4\core_core_fast2_ok$next[0:0]$12831 1'0 + assign $4\core_fasto1_ok$next[0:0]$12838 1'0 + assign $4\core_fasto2_ok$next[0:0]$12839 1'0 + assign $4\core_core_cr_in1_ok$next[0:0]$12826 1'0 + assign $4\core_core_cr_in2_ok$next[0:0]$12828 1'0 + assign $4\core_core_cr_in2_ok$2$next[0:0]$12827 1'0 + assign $4\core_cr_out_ok$next[0:0]$12836 1'0 + assign $4\core_core_core_rc_ok$next[0:0]$12825 1'0 + assign $4\core_core_core_oe_ok$next[0:0]$12824 1'0 + assign $4\core_core_core_cr_rd_ok$next[0:0]$12823 1'0 + assign $4\core_core_cr_wr_ok$next[0:0]$12829 1'0 + case + assign $4\core_core_core_cr_rd_ok$next[0:0]$12823 $1\core_core_core_cr_rd_ok$next[0:0]$12673 + assign $4\core_core_core_oe_ok$next[0:0]$12824 $1\core_core_core_oe_ok$next[0:0]$12682 + assign $4\core_core_core_rc_ok$next[0:0]$12825 $1\core_core_core_rc_ok$next[0:0]$12684 + assign $4\core_core_cr_in1_ok$next[0:0]$12826 $1\core_core_cr_in1_ok$next[0:0]$12688 + assign $4\core_core_cr_in2_ok$2$next[0:0]$12827 $1\core_core_cr_in2_ok$2$next[0:0]$12691 + assign $4\core_core_cr_in2_ok$next[0:0]$12828 $1\core_core_cr_in2_ok$next[0:0]$12692 + assign $4\core_core_cr_wr_ok$next[0:0]$12829 $1\core_core_cr_wr_ok$next[0:0]$12694 + assign $4\core_core_fast1_ok$next[0:0]$12830 $1\core_core_fast1_ok$next[0:0]$12697 + assign $4\core_core_fast2_ok$next[0:0]$12831 $1\core_core_fast2_ok$next[0:0]$12699 + assign $4\core_core_reg1_ok$next[0:0]$12832 $1\core_core_reg1_ok$next[0:0]$12704 + assign $4\core_core_reg2_ok$next[0:0]$12833 $1\core_core_reg2_ok$next[0:0]$12706 + assign $4\core_core_reg3_ok$next[0:0]$12834 $1\core_core_reg3_ok$next[0:0]$12708 + assign $4\core_core_spr1_ok$next[0:0]$12835 $1\core_core_spr1_ok$next[0:0]$12711 + assign $4\core_cr_out_ok$next[0:0]$12836 $1\core_cr_out_ok$next[0:0]$12714 + assign $4\core_ea_ok$next[0:0]$12837 $1\core_ea_ok$next[0:0]$12715 + assign $4\core_fasto1_ok$next[0:0]$12838 $1\core_fasto1_ok$next[0:0]$12716 + assign $4\core_fasto2_ok$next[0:0]$12839 $1\core_fasto2_ok$next[0:0]$12717 + assign $4\core_rego_ok$next[0:0]$12840 $1\core_rego_ok$next[0:0]$12718 + assign $4\core_spro_ok$next[0:0]$12841 $1\core_spro_ok$next[0:0]$12719 + end + sync always + update \core_asmcode$next $0\core_asmcode$next[7:0]$12619 + update \core_core_core_cia$next $0\core_core_core_cia$next[63:0]$12620 + update \core_core_core_cr_rd$next $0\core_core_core_cr_rd$next[7:0]$12621 + update \core_core_core_cr_rd_ok$next $0\core_core_core_cr_rd_ok$next[0:0]$12622 + update \core_core_core_cr_wr$next $0\core_core_core_cr_wr$next[7:0]$12623 + update \core_core_core_fn_unit$next $0\core_core_core_fn_unit$next[11:0]$12624 + update \core_core_core_input_carry$next $0\core_core_core_input_carry$next[1:0]$12625 + update \core_core_core_insn$next $0\core_core_core_insn$next[31:0]$12626 + update \core_core_core_insn_type$next $0\core_core_core_insn_type$next[6:0]$12627 + update \core_core_core_is_32bit$next $0\core_core_core_is_32bit$next[0:0]$12628 + update \core_core_core_msr$next $0\core_core_core_msr$next[63:0]$12629 + update \core_core_core_oe$next $0\core_core_core_oe$next[0:0]$12630 + update \core_core_core_oe_ok$next $0\core_core_core_oe_ok$next[0:0]$12631 + update \core_core_core_rc$next $0\core_core_core_rc$next[0:0]$12632 + update \core_core_core_rc_ok$next $0\core_core_core_rc_ok$next[0:0]$12633 + update \core_core_core_trapaddr$next $0\core_core_core_trapaddr$next[12:0]$12634 + update \core_core_core_traptype$next $0\core_core_core_traptype$next[6:0]$12635 + update \core_core_cr_in1$next $0\core_core_cr_in1$next[2:0]$12636 + update \core_core_cr_in1_ok$next $0\core_core_cr_in1_ok$next[0:0]$12637 + update \core_core_cr_in2$1$next $0\core_core_cr_in2$1$next[2:0]$12638 + update \core_core_cr_in2$next $0\core_core_cr_in2$next[2:0]$12639 + update \core_core_cr_in2_ok$2$next $0\core_core_cr_in2_ok$2$next[0:0]$12640 + update \core_core_cr_in2_ok$next $0\core_core_cr_in2_ok$next[0:0]$12641 + update \core_core_cr_out$next $0\core_core_cr_out$next[2:0]$12642 + update \core_core_cr_wr_ok$next $0\core_core_cr_wr_ok$next[0:0]$12643 + update \core_core_ea$next $0\core_core_ea$next[4:0]$12644 + update \core_core_fast1$next $0\core_core_fast1$next[2:0]$12645 + update \core_core_fast1_ok$next $0\core_core_fast1_ok$next[0:0]$12646 + update \core_core_fast2$next $0\core_core_fast2$next[2:0]$12647 + update \core_core_fast2_ok$next $0\core_core_fast2_ok$next[0:0]$12648 + update \core_core_fasto1$next $0\core_core_fasto1$next[2:0]$12649 + update \core_core_fasto2$next $0\core_core_fasto2$next[2:0]$12650 + update \core_core_lk$next $0\core_core_lk$next[0:0]$12651 + update \core_core_reg1$next $0\core_core_reg1$next[4:0]$12652 + update \core_core_reg1_ok$next $0\core_core_reg1_ok$next[0:0]$12653 + update \core_core_reg2$next $0\core_core_reg2$next[4:0]$12654 + update \core_core_reg2_ok$next $0\core_core_reg2_ok$next[0:0]$12655 + update \core_core_reg3$next $0\core_core_reg3$next[4:0]$12656 + update \core_core_reg3_ok$next $0\core_core_reg3_ok$next[0:0]$12657 + update \core_core_rego$next $0\core_core_rego$next[4:0]$12658 + update \core_core_spr1$next $0\core_core_spr1$next[9:0]$12659 + update \core_core_spr1_ok$next $0\core_core_spr1_ok$next[0:0]$12660 + update \core_core_spro$next $0\core_core_spro$next[9:0]$12661 + update \core_core_xer_in$next $0\core_core_xer_in$next[2:0]$12662 + update \core_cr_out_ok$next $0\core_cr_out_ok$next[0:0]$12663 + update \core_ea_ok$next $0\core_ea_ok$next[0:0]$12664 + update \core_fasto1_ok$next $0\core_fasto1_ok$next[0:0]$12665 + update \core_fasto2_ok$next $0\core_fasto2_ok$next[0:0]$12666 + update \core_rego_ok$next $0\core_rego_ok$next[0:0]$12667 + update \core_spro_ok$next $0\core_spro_ok$next[0:0]$12668 + update \core_xer_out$next $0\core_xer_out$next[0:0]$12669 + end + attribute \src "issuer_ls180.v:178274.3-178283.6" + process $proc$issuer_ls180.v:178274$12842 + assign { } { } + assign { } { } + assign $0\delay$next[1:0]$12843 $1\delay$next[1:0]$12844 + attribute \src "issuer_ls180.v:178275.5-178275.29" + switch \initial + attribute \src "issuer_ls180.v:178275.9-178275.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:145" + switch \$7 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\delay$next[1:0]$12844 \$9 [1:0] + case + assign $1\delay$next[1:0]$12844 \delay + end + sync always + update \delay$next $0\delay$next[1:0]$12843 + end + attribute \src "issuer_ls180.v:178284.3-178320.6" + process $proc$issuer_ls180.v:178284$12845 + assign { } { } + assign { } { } + assign { } { } + assign $0\core_raw_insn_i$next[31:0]$12846 $4\core_raw_insn_i$next[31:0]$12850 + attribute \src "issuer_ls180.v:178285.5-178285.29" + switch \initial + attribute \src "issuer_ls180.v:178285.9-178285.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:214" + switch \fsm_state + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\core_raw_insn_i$next[31:0]$12847 0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\core_raw_insn_i$next[31:0]$12847 $2\core_raw_insn_i$next[31:0]$12848 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:247" + switch \imem_f_busy_o + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign $2\core_raw_insn_i$next[31:0]$12848 \core_raw_insn_i + attribute \src "issuer_ls180.v:0.0-0.0" + case + assign { } { } + assign $2\core_raw_insn_i$next[31:0]$12848 \dec2_raw_opcode_in + end + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'11 + assign { } { } + assign $1\core_raw_insn_i$next[31:0]$12847 $3\core_raw_insn_i$next[31:0]$12849 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:280" + switch \$45 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\core_raw_insn_i$next[31:0]$12849 0 + case + assign $3\core_raw_insn_i$next[31:0]$12849 \core_raw_insn_i + end + case + assign $1\core_raw_insn_i$next[31:0]$12847 \core_raw_insn_i + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\core_raw_insn_i$next[31:0]$12850 0 + case + assign $4\core_raw_insn_i$next[31:0]$12850 $1\core_raw_insn_i$next[31:0]$12847 + end + sync always + update \core_raw_insn_i$next $0\core_raw_insn_i$next[31:0]$12846 + end + attribute \src "issuer_ls180.v:178321.3-178357.6" + process $proc$issuer_ls180.v:178321$12851 + assign { } { } + assign { } { } + assign { } { } + assign $0\core_bigendian_i$3$next[0:0]$12852 $4\core_bigendian_i$3$next[0:0]$12856 + attribute \src "issuer_ls180.v:178322.5-178322.29" + switch \initial + attribute \src "issuer_ls180.v:178322.9-178322.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:214" + switch \fsm_state + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\core_bigendian_i$3$next[0:0]$12853 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\core_bigendian_i$3$next[0:0]$12853 $2\core_bigendian_i$3$next[0:0]$12854 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:247" + switch \imem_f_busy_o + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign $2\core_bigendian_i$3$next[0:0]$12854 \core_bigendian_i$3 + attribute \src "issuer_ls180.v:0.0-0.0" + case + assign { } { } + assign $2\core_bigendian_i$3$next[0:0]$12854 \core_bigendian_i + end + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'11 + assign { } { } + assign $1\core_bigendian_i$3$next[0:0]$12853 $3\core_bigendian_i$3$next[0:0]$12855 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:280" + switch \$47 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\core_bigendian_i$3$next[0:0]$12855 1'0 + case + assign $3\core_bigendian_i$3$next[0:0]$12855 \core_bigendian_i$3 + end + case + assign $1\core_bigendian_i$3$next[0:0]$12853 \core_bigendian_i$3 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\core_bigendian_i$3$next[0:0]$12856 1'0 + case + assign $4\core_bigendian_i$3$next[0:0]$12856 $1\core_bigendian_i$3$next[0:0]$12853 + end + sync always + update \core_bigendian_i$3$next $0\core_bigendian_i$3$next[0:0]$12852 + end + attribute \src "issuer_ls180.v:178358.3-178373.6" + process $proc$issuer_ls180.v:178358$12857 + assign { } { } + assign { } { } + assign $0\imem_a_pc_i[47:0] $1\imem_a_pc_i[47:0] + attribute \src "issuer_ls180.v:178359.5-178359.29" + switch \initial + attribute \src "issuer_ls180.v:178359.9-178359.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:214" + switch \fsm_state + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\imem_a_pc_i[47:0] $2\imem_a_pc_i[47:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:222" + switch \$53 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\imem_a_pc_i[47:0] \pc [47:0] + case + assign $2\imem_a_pc_i[47:0] 48'000000000000000000000000000000000000000000000000 + end + case + assign $1\imem_a_pc_i[47:0] 48'000000000000000000000000000000000000000000000000 + end + sync always + update \imem_a_pc_i $0\imem_a_pc_i[47:0] + end + attribute \src "issuer_ls180.v:178374.3-178398.6" + process $proc$issuer_ls180.v:178374$12858 + assign { } { } + assign { } { } + assign $0\imem_a_valid_i[0:0] $1\imem_a_valid_i[0:0] + attribute \src "issuer_ls180.v:178375.5-178375.29" + switch \initial + attribute \src "issuer_ls180.v:178375.9-178375.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:214" + switch \fsm_state + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\imem_a_valid_i[0:0] $2\imem_a_valid_i[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:222" + switch \$59 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\imem_a_valid_i[0:0] 1'1 + case + assign $2\imem_a_valid_i[0:0] 1'0 + end + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\imem_a_valid_i[0:0] $3\imem_a_valid_i[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:247" + switch \imem_f_busy_o + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\imem_a_valid_i[0:0] 1'1 + case + assign $3\imem_a_valid_i[0:0] 1'0 + end + case + assign $1\imem_a_valid_i[0:0] 1'0 + end + sync always + update \imem_a_valid_i $0\imem_a_valid_i[0:0] + end + attribute \src "issuer_ls180.v:178399.3-178423.6" + process $proc$issuer_ls180.v:178399$12859 + assign { } { } + assign { } { } + assign $0\imem_f_valid_i[0:0] $1\imem_f_valid_i[0:0] + attribute \src "issuer_ls180.v:178400.5-178400.29" + switch \initial + attribute \src "issuer_ls180.v:178400.9-178400.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:214" + switch \fsm_state + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\imem_f_valid_i[0:0] $2\imem_f_valid_i[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:222" + switch \$65 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\imem_f_valid_i[0:0] 1'1 + case + assign $2\imem_f_valid_i[0:0] 1'0 + end + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\imem_f_valid_i[0:0] $3\imem_f_valid_i[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:247" + switch \imem_f_busy_o + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\imem_f_valid_i[0:0] 1'1 + case + assign $3\imem_f_valid_i[0:0] 1'0 + end + case + assign $1\imem_f_valid_i[0:0] 1'0 + end + sync always + update \imem_f_valid_i $0\imem_f_valid_i[0:0] + end + attribute \src "issuer_ls180.v:178424.3-178444.6" + process $proc$issuer_ls180.v:178424$12860 + assign { } { } + assign { } { } + assign { } { } + assign $0\dec2_cur_pc$next[63:0]$12861 $3\dec2_cur_pc$next[63:0]$12864 + attribute \src "issuer_ls180.v:178425.5-178425.29" + switch \initial + attribute \src "issuer_ls180.v:178425.9-178425.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:214" + switch \fsm_state + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dec2_cur_pc$next[63:0]$12862 $2\dec2_cur_pc$next[63:0]$12863 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:222" + switch \$71 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\dec2_cur_pc$next[63:0]$12863 \pc + case + assign $2\dec2_cur_pc$next[63:0]$12863 \dec2_cur_pc + end + case + assign $1\dec2_cur_pc$next[63:0]$12862 \dec2_cur_pc + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\dec2_cur_pc$next[63:0]$12864 64'0000000000000000000000000000000000000000000000000000000000000000 + case + assign $3\dec2_cur_pc$next[63:0]$12864 $1\dec2_cur_pc$next[63:0]$12862 + end + sync always + update \dec2_cur_pc$next $0\dec2_cur_pc$next[63:0]$12861 + end + attribute \src "issuer_ls180.v:178445.3-178474.6" + process $proc$issuer_ls180.v:178445$12865 + assign { } { } + assign { } { } + assign { } { } + assign $0\msr_read$next[0:0]$12866 $4\msr_read$next[0:0]$12870 + attribute \src "issuer_ls180.v:178446.5-178446.29" + switch \initial + attribute \src "issuer_ls180.v:178446.9-178446.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:214" + switch \fsm_state + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\msr_read$next[0:0]$12867 $2\msr_read$next[0:0]$12868 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:222" + switch \$77 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\msr_read$next[0:0]$12868 1'0 + case + assign $2\msr_read$next[0:0]$12868 \msr_read + end + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\msr_read$next[0:0]$12867 $3\msr_read$next[0:0]$12869 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:244" + switch \$79 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\msr_read$next[0:0]$12869 1'1 + case + assign $3\msr_read$next[0:0]$12869 \msr_read + end + case + assign $1\msr_read$next[0:0]$12867 \msr_read + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\msr_read$next[0:0]$12870 1'1 + case + assign $4\msr_read$next[0:0]$12870 $1\msr_read$next[0:0]$12867 + end + sync always + update \msr_read$next $0\msr_read$next[0:0]$12866 + end + attribute \src "issuer_ls180.v:178475.3-178520.6" + process $proc$issuer_ls180.v:178475$12871 + assign { } { } + assign { } { } + assign { } { } + assign $0\fsm_state$next[1:0]$12872 $5\fsm_state$next[1:0]$12877 + attribute \src "issuer_ls180.v:178476.5-178476.29" + switch \initial + attribute \src "issuer_ls180.v:178476.9-178476.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:214" + switch \fsm_state + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\fsm_state$next[1:0]$12873 $2\fsm_state$next[1:0]$12874 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:222" + switch \$85 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\fsm_state$next[1:0]$12874 2'01 + case + assign $2\fsm_state$next[1:0]$12874 \fsm_state + end + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\fsm_state$next[1:0]$12873 $3\fsm_state$next[1:0]$12875 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:247" + switch \imem_f_busy_o + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign $3\fsm_state$next[1:0]$12875 \fsm_state + attribute \src "issuer_ls180.v:0.0-0.0" + case + assign { } { } + assign $3\fsm_state$next[1:0]$12875 2'10 + end + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\fsm_state$next[1:0]$12873 2'11 + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'11 + assign { } { } + assign $1\fsm_state$next[1:0]$12873 $4\fsm_state$next[1:0]$12876 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:280" + switch \$87 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\fsm_state$next[1:0]$12876 2'00 + case + assign $4\fsm_state$next[1:0]$12876 \fsm_state + end + case + assign $1\fsm_state$next[1:0]$12873 \fsm_state + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $5\fsm_state$next[1:0]$12877 2'00 + case + assign $5\fsm_state$next[1:0]$12877 $1\fsm_state$next[1:0]$12873 + end + sync always + update \fsm_state$next $0\fsm_state$next[1:0]$12872 + end + attribute \src "issuer_ls180.v:178521.3-178539.6" + process $proc$issuer_ls180.v:178521$12878 + assign { } { } + assign { } { } + assign $0\core_stopped_i[0:0] $1\core_stopped_i[0:0] + attribute \src "issuer_ls180.v:178522.5-178522.29" + switch \initial + attribute \src "issuer_ls180.v:178522.9-178522.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:214" + switch \fsm_state + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\core_stopped_i[0:0] $2\core_stopped_i[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:222" + switch \$93 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign $2\core_stopped_i[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case + assign { } { } + assign $2\core_stopped_i[0:0] 1'1 + end + case + assign $1\core_stopped_i[0:0] 1'0 + end + sync always + update \core_stopped_i $0\core_stopped_i[0:0] + end + attribute \src "issuer_ls180.v:178540.3-178558.6" + process $proc$issuer_ls180.v:178540$12879 + assign { } { } + assign { } { } + assign $0\dbg_core_stopped_i[0:0] $1\dbg_core_stopped_i[0:0] + attribute \src "issuer_ls180.v:178541.5-178541.29" + switch \initial + attribute \src "issuer_ls180.v:178541.9-178541.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:214" + switch \fsm_state + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'00 + assign { } { } + assign $1\dbg_core_stopped_i[0:0] $2\dbg_core_stopped_i[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:222" + switch \$99 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign $2\dbg_core_stopped_i[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case + assign { } { } + assign $2\dbg_core_stopped_i[0:0] 1'1 + end + case + assign $1\dbg_core_stopped_i[0:0] 1'0 + end + sync always + update \dbg_core_stopped_i $0\dbg_core_stopped_i[0:0] + end + attribute \src "issuer_ls180.v:178559.3-178579.6" + process $proc$issuer_ls180.v:178559$12880 + assign { } { } + assign { } { } + assign { } { } + assign $0\dec2_cur_msr$next[63:0]$12881 $3\dec2_cur_msr$next[63:0]$12884 + attribute \src "issuer_ls180.v:178560.5-178560.29" + switch \initial + attribute \src "issuer_ls180.v:178560.9-178560.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:214" + switch \fsm_state + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec2_cur_msr$next[63:0]$12882 $2\dec2_cur_msr$next[63:0]$12883 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:244" + switch \$101 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\dec2_cur_msr$next[63:0]$12883 \core_msr__data_o + case + assign $2\dec2_cur_msr$next[63:0]$12883 \dec2_cur_msr + end + case + assign $1\dec2_cur_msr$next[63:0]$12882 \dec2_cur_msr + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\dec2_cur_msr$next[63:0]$12884 64'0000000000000000000000000000000000000000000000000000000000000000 + case + assign $3\dec2_cur_msr$next[63:0]$12884 $1\dec2_cur_msr$next[63:0]$12882 + end + sync always + update \dec2_cur_msr$next $0\dec2_cur_msr$next[63:0]$12881 + end + attribute \src "issuer_ls180.v:178580.3-178598.6" + process $proc$issuer_ls180.v:178580$12885 + assign { } { } + assign { } { } + assign $0\dec2_raw_opcode_in[31:0] $1\dec2_raw_opcode_in[31:0] + attribute \src "issuer_ls180.v:178581.5-178581.29" + switch \initial + attribute \src "issuer_ls180.v:178581.9-178581.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:214" + switch \fsm_state + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\dec2_raw_opcode_in[31:0] $2\dec2_raw_opcode_in[31:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:247" + switch \imem_f_busy_o + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign $2\dec2_raw_opcode_in[31:0] 0 + attribute \src "issuer_ls180.v:0.0-0.0" + case + assign { } { } + assign $2\dec2_raw_opcode_in[31:0] \$103 + end + case + assign $1\dec2_raw_opcode_in[31:0] 0 + end + sync always + update \dec2_raw_opcode_in $0\dec2_raw_opcode_in[31:0] + end + attribute \src "issuer_ls180.v:178599.3-178630.6" + process $proc$issuer_ls180.v:178599$12886 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\core_core_pc$next[63:0]$12887 $3\core_core_pc$next[63:0]$12899 + assign $0\core_dec$next[63:0]$12888 $3\core_dec$next[63:0]$12900 + assign $0\core_eint$next[0:0]$12889 $3\core_eint$next[0:0]$12901 + assign $0\core_msr$next[63:0]$12890 $3\core_msr$next[63:0]$12902 + attribute \src "issuer_ls180.v:178600.5-178600.29" + switch \initial + attribute \src "issuer_ls180.v:178600.9-178600.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:214" + switch \fsm_state + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'01 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\core_core_pc$next[63:0]$12891 $2\core_core_pc$next[63:0]$12895 + assign $1\core_dec$next[63:0]$12892 $2\core_dec$next[63:0]$12896 + assign $1\core_eint$next[0:0]$12893 $2\core_eint$next[0:0]$12897 + assign $1\core_msr$next[63:0]$12894 $2\core_msr$next[63:0]$12898 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:247" + switch \imem_f_busy_o + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign $2\core_core_pc$next[63:0]$12895 \core_core_pc + assign $2\core_dec$next[63:0]$12896 \core_dec + assign $2\core_eint$next[0:0]$12897 \core_eint + assign $2\core_msr$next[63:0]$12898 \core_msr + attribute \src "issuer_ls180.v:0.0-0.0" + case + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { $2\core_dec$next[63:0]$12896 $2\core_eint$next[0:0]$12897 $2\core_msr$next[63:0]$12898 $2\core_core_pc$next[63:0]$12895 } { \dec2_cur_dec \dec2_cur_eint \dec2_cur_msr \dec2_cur_pc } + end + case + assign $1\core_core_pc$next[63:0]$12891 \core_core_pc + assign $1\core_dec$next[63:0]$12892 \core_dec + assign $1\core_eint$next[0:0]$12893 \core_eint + assign $1\core_msr$next[63:0]$12894 \core_msr + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $3\core_core_pc$next[63:0]$12899 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $3\core_msr$next[63:0]$12902 64'0000000000000000000000000000000000000000000000000000000000000000 + assign $3\core_eint$next[0:0]$12901 1'0 + assign $3\core_dec$next[63:0]$12900 64'0000000000000000000000000000000000000000000000000000000000000000 + case + assign $3\core_core_pc$next[63:0]$12899 $1\core_core_pc$next[63:0]$12891 + assign $3\core_dec$next[63:0]$12900 $1\core_dec$next[63:0]$12892 + assign $3\core_eint$next[0:0]$12901 $1\core_eint$next[0:0]$12893 + assign $3\core_msr$next[63:0]$12902 $1\core_msr$next[63:0]$12894 + end + sync always + update \core_core_pc$next $0\core_core_pc$next[63:0]$12887 + update \core_dec$next $0\core_dec$next[63:0]$12888 + update \core_eint$next $0\core_eint$next[0:0]$12889 + update \core_msr$next $0\core_msr$next[63:0]$12890 + end + attribute \src "issuer_ls180.v:178631.3-178654.6" + process $proc$issuer_ls180.v:178631$12903 + assign { } { } + assign { } { } + assign { } { } + assign $0\ilatch$next[31:0]$12904 $3\ilatch$next[31:0]$12907 + attribute \src "issuer_ls180.v:178632.5-178632.29" + switch \initial + attribute \src "issuer_ls180.v:178632.9-178632.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:214" + switch \fsm_state + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'01 + assign { } { } + assign $1\ilatch$next[31:0]$12905 $2\ilatch$next[31:0]$12906 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:247" + switch \imem_f_busy_o + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign $2\ilatch$next[31:0]$12906 \ilatch + attribute \src "issuer_ls180.v:0.0-0.0" + case + assign { } { } + assign $2\ilatch$next[31:0]$12906 \$107 + end + case + assign $1\ilatch$next[31:0]$12905 \ilatch + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\ilatch$next[31:0]$12907 0 + case + assign $3\ilatch$next[31:0]$12907 $1\ilatch$next[31:0]$12905 + end + sync always + update \ilatch$next $0\ilatch$next[31:0]$12904 + end + attribute \src "issuer_ls180.v:178655.3-178674.6" + process $proc$issuer_ls180.v:178655$12908 + assign { } { } + assign { } { } + assign $0\core_ivalid_i[0:0] $1\core_ivalid_i[0:0] + attribute \src "issuer_ls180.v:178656.5-178656.29" + switch \initial + attribute \src "issuer_ls180.v:178656.9-178656.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:214" + switch \fsm_state + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\core_ivalid_i[0:0] 1'1 + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'11 + assign { } { } + assign $1\core_ivalid_i[0:0] $2\core_ivalid_i[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:276" + switch \$111 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\core_ivalid_i[0:0] 1'1 + case + assign $2\core_ivalid_i[0:0] 1'0 + end + case + assign $1\core_ivalid_i[0:0] 1'0 + end + sync always + update \core_ivalid_i $0\core_ivalid_i[0:0] + end + attribute \src "issuer_ls180.v:178675.3-178685.6" + process $proc$issuer_ls180.v:178675$12909 + assign { } { } + assign { } { } + assign $0\core_issue_i[0:0] $1\core_issue_i[0:0] + attribute \src "issuer_ls180.v:178676.5-178676.29" + switch \initial + attribute \src "issuer_ls180.v:178676.9-178676.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:214" + switch \fsm_state + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'10 + assign { } { } + assign $1\core_issue_i[0:0] 1'1 + case + assign $1\core_issue_i[0:0] 1'0 + end + sync always + update \core_issue_i $0\core_issue_i[0:0] + end + attribute \src "issuer_ls180.v:178686.3-178695.6" + process $proc$issuer_ls180.v:178686$12910 + assign { } { } + assign { } { } + assign $0\core_dmi__addr[4:0] $1\core_dmi__addr[4:0] + attribute \src "issuer_ls180.v:178687.5-178687.29" + switch \initial + attribute \src "issuer_ls180.v:178687.9-178687.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:294" + switch \dbg_d_gpr_req + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\core_dmi__addr[4:0] \dbg_d_gpr_addr [4:0] + case + assign $1\core_dmi__addr[4:0] 5'00000 + end + sync always + update \core_dmi__addr $0\core_dmi__addr[4:0] + end + attribute \src "issuer_ls180.v:178696.3-178705.6" + process $proc$issuer_ls180.v:178696$12911 + assign { } { } + assign { } { } + assign $0\core_dmi__ren[0:0] $1\core_dmi__ren[0:0] + attribute \src "issuer_ls180.v:178697.5-178697.29" + switch \initial + attribute \src "issuer_ls180.v:178697.9-178697.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:294" + switch \dbg_d_gpr_req + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\core_dmi__ren[0:0] 1'1 + case + assign $1\core_dmi__ren[0:0] 1'0 + end + sync always + update \core_dmi__ren $0\core_dmi__ren[0:0] + end + attribute \src "issuer_ls180.v:178706.3-178714.6" + process $proc$issuer_ls180.v:178706$12912 + assign { } { } + assign { } { } + assign $0\d_reg_delay$next[0:0]$12913 $1\d_reg_delay$next[0:0]$12914 + attribute \src "issuer_ls180.v:178707.5-178707.29" + switch \initial + attribute \src "issuer_ls180.v:178707.9-178707.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\d_reg_delay$next[0:0]$12914 1'0 + case + assign $1\d_reg_delay$next[0:0]$12914 \dbg_d_gpr_req + end + sync always + update \d_reg_delay$next $0\d_reg_delay$next[0:0]$12913 + end + attribute \src "issuer_ls180.v:178715.3-178724.6" + process $proc$issuer_ls180.v:178715$12915 + assign { } { } + assign { } { } + assign $0\dbg_d_gpr_data[63:0] $1\dbg_d_gpr_data[63:0] + attribute \src "issuer_ls180.v:178716.5-178716.29" + switch \initial + attribute \src "issuer_ls180.v:178716.9-178716.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:304" + switch \d_reg_delay + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dbg_d_gpr_data[63:0] \core_dmi__data_o + case + assign $1\dbg_d_gpr_data[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \dbg_d_gpr_data $0\dbg_d_gpr_data[63:0] + end + attribute \src "issuer_ls180.v:178725.3-178734.6" + process $proc$issuer_ls180.v:178725$12916 + assign { } { } + assign { } { } + assign $0\dbg_d_gpr_ack[0:0] $1\dbg_d_gpr_ack[0:0] + attribute \src "issuer_ls180.v:178726.5-178726.29" + switch \initial + attribute \src "issuer_ls180.v:178726.9-178726.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:304" + switch \d_reg_delay + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dbg_d_gpr_ack[0:0] 1'1 + case + assign $1\dbg_d_gpr_ack[0:0] 1'0 + end + sync always + update \dbg_d_gpr_ack $0\dbg_d_gpr_ack[0:0] + end + connect \$99 $and$issuer_ls180.v:177403$12439_Y + connect \$101 $not$issuer_ls180.v:177404$12440_Y + connect \$104 $mul$issuer_ls180.v:177405$12441_Y + connect \$103 $shr$issuer_ls180.v:177406$12442_Y [31:0] + connect \$108 $mul$issuer_ls180.v:177407$12443_Y + connect \$10 $sub$issuer_ls180.v:177408$12444_Y + connect \$107 $shr$issuer_ls180.v:177409$12445_Y [31:0] + connect \$111 $ne$issuer_ls180.v:177410$12446_Y + connect \$113 $pos$issuer_ls180.v:177411$12448_Y + connect \$115 $pos$issuer_ls180.v:177412$12450_Y + connect \$119 $sub$issuer_ls180.v:177413$12451_Y + connect \$122 $add$issuer_ls180.v:177414$12452_Y + connect \$12 $or$issuer_ls180.v:177415$12453_Y + connect \$14 $ne$issuer_ls180.v:177416$12454_Y + connect \$16 $not$issuer_ls180.v:177417$12455_Y + connect \$18 $and$issuer_ls180.v:177418$12456_Y + connect \$21 $add$issuer_ls180.v:177419$12457_Y + connect \$23 $not$issuer_ls180.v:177420$12458_Y + connect \$25 $not$issuer_ls180.v:177421$12459_Y + connect \$27 $not$issuer_ls180.v:177422$12460_Y + connect \$29 $not$issuer_ls180.v:177423$12461_Y + connect \$31 $not$issuer_ls180.v:177424$12462_Y + connect \$33 $not$issuer_ls180.v:177425$12463_Y + connect \$35 $not$issuer_ls180.v:177426$12464_Y + connect \$37 $and$issuer_ls180.v:177427$12465_Y + connect \$40 $and$issuer_ls180.v:177428$12466_Y + connect \$39 $reduce_or$issuer_ls180.v:177429$12467_Y + connect \$43 $not$issuer_ls180.v:177430$12468_Y + connect \$45 $not$issuer_ls180.v:177431$12469_Y + connect \$47 $not$issuer_ls180.v:177432$12470_Y + connect \$49 $not$issuer_ls180.v:177433$12471_Y + connect \$51 $not$issuer_ls180.v:177434$12472_Y + connect \$53 $and$issuer_ls180.v:177435$12473_Y + connect \$55 $not$issuer_ls180.v:177436$12474_Y + connect \$57 $not$issuer_ls180.v:177437$12475_Y + connect \$59 $and$issuer_ls180.v:177438$12476_Y + connect \$61 $not$issuer_ls180.v:177439$12477_Y + connect \$63 $not$issuer_ls180.v:177440$12478_Y + connect \$65 $and$issuer_ls180.v:177441$12479_Y + connect \$67 $not$issuer_ls180.v:177442$12480_Y + connect \$69 $not$issuer_ls180.v:177443$12481_Y + connect \$71 $and$issuer_ls180.v:177444$12482_Y + connect \$73 $not$issuer_ls180.v:177445$12483_Y + connect \$75 $not$issuer_ls180.v:177446$12484_Y + connect \$77 $and$issuer_ls180.v:177447$12485_Y + connect \$7 $ne$issuer_ls180.v:177448$12486_Y + connect \$79 $not$issuer_ls180.v:177449$12487_Y + connect \$81 $not$issuer_ls180.v:177450$12488_Y + connect \$83 $not$issuer_ls180.v:177451$12489_Y + connect \$85 $and$issuer_ls180.v:177452$12490_Y + connect \$87 $not$issuer_ls180.v:177453$12491_Y + connect \$89 $not$issuer_ls180.v:177454$12492_Y + connect \$91 $not$issuer_ls180.v:177455$12493_Y + connect \$93 $and$issuer_ls180.v:177456$12494_Y + connect \$95 $not$issuer_ls180.v:177457$12495_Y + connect \$97 $not$issuer_ls180.v:177458$12496_Y + connect \$9 \$10 + connect \$20 \$21 + connect \$118 \$119 + connect \$121 \$122 + connect \dbg_core_dbg_msr \dec2_cur_msr + connect \dbg_core_dbg_pc \pc + connect \dbg_terminate_i \core_core_terminate_o + connect \nia \$21 [63:0] + connect \pc_o \dec2_cur_pc + connect \core_cu_st__go_i \cu_st__rel_o_rise + connect \core_cu_ad__go_i \core_cu_ad__rel_o + connect \cu_st__rel_o_rise \$18 + connect \cu_st__rel_o_dly$next \core_cu_st__rel_o + connect \dec2_bigendian \core_bigendian_i + connect \busy_o \core_corebusy_o + connect \core_core_reset_i \$14 + connect \core_coresync_clk \clk + connect \por_clk \clk + connect { \xics_icp_ics_i_pri \xics_icp_ics_i_src } { \xics_ics_icp_o_pri \xics_ics_icp_o_src } +end +attribute \src "issuer_ls180.v:178758.1-179933.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.fus.trap0" +attribute \generator "nMigen" +module \trap0 + attribute \src "issuer_ls180.v:179480.3-179481.25" + wire $0\all_rd_dly[0:0] + attribute \src "issuer_ls180.v:179478.3-179479.41" + wire $0\alu_done_dly[0:0] + attribute \src "issuer_ls180.v:179836.3-179844.6" + wire $0\alu_l_r_alu$next[0:0]$13196 + attribute \src "issuer_ls180.v:179408.3-179409.39" + wire $0\alu_l_r_alu[0:0] + attribute \src "issuer_ls180.v:179660.3-179676.6" + wire width 64 $0\alu_trap0_trap_op__cia$next[63:0]$13124 + attribute \src "issuer_ls180.v:179448.3-179449.61" + wire width 64 $0\alu_trap0_trap_op__cia[63:0] + attribute \src "issuer_ls180.v:179660.3-179676.6" + wire width 12 $0\alu_trap0_trap_op__fn_unit$next[11:0]$13125 + attribute \src "issuer_ls180.v:179442.3-179443.69" + wire width 12 $0\alu_trap0_trap_op__fn_unit[11:0] + attribute \src "issuer_ls180.v:179660.3-179676.6" + wire width 32 $0\alu_trap0_trap_op__insn$next[31:0]$13126 + attribute \src "issuer_ls180.v:179444.3-179445.63" + wire width 32 $0\alu_trap0_trap_op__insn[31:0] + attribute \src "issuer_ls180.v:179660.3-179676.6" + wire width 7 $0\alu_trap0_trap_op__insn_type$next[6:0]$13127 + attribute \src "issuer_ls180.v:179440.3-179441.73" + wire width 7 $0\alu_trap0_trap_op__insn_type[6:0] + attribute \src "issuer_ls180.v:179660.3-179676.6" + wire $0\alu_trap0_trap_op__is_32bit$next[0:0]$13128 + attribute \src "issuer_ls180.v:179450.3-179451.71" + wire $0\alu_trap0_trap_op__is_32bit[0:0] + attribute \src "issuer_ls180.v:179660.3-179676.6" + wire width 64 $0\alu_trap0_trap_op__msr$next[63:0]$13129 + attribute \src "issuer_ls180.v:179446.3-179447.61" + wire width 64 $0\alu_trap0_trap_op__msr[63:0] + attribute \src "issuer_ls180.v:179660.3-179676.6" + wire width 13 $0\alu_trap0_trap_op__trapaddr$next[12:0]$13130 + attribute \src "issuer_ls180.v:179454.3-179455.71" + wire width 13 $0\alu_trap0_trap_op__trapaddr[12:0] + attribute \src "issuer_ls180.v:179660.3-179676.6" + wire width 7 $0\alu_trap0_trap_op__traptype$next[6:0]$13131 + attribute \src "issuer_ls180.v:179452.3-179453.71" + wire width 7 $0\alu_trap0_trap_op__traptype[6:0] + attribute \src "issuer_ls180.v:179827.3-179835.6" + wire $0\alui_l_r_alui$next[0:0]$13193 + attribute \src "issuer_ls180.v:179410.3-179411.43" + wire $0\alui_l_r_alui[0:0] + attribute \src "issuer_ls180.v:179677.3-179698.6" + wire width 64 $0\data_r0__o$next[63:0]$13141 + attribute \src "issuer_ls180.v:179436.3-179437.37" + wire width 64 $0\data_r0__o[63:0] + attribute \src "issuer_ls180.v:179677.3-179698.6" + wire $0\data_r0__o_ok$next[0:0]$13142 + attribute \src "issuer_ls180.v:179438.3-179439.43" + wire $0\data_r0__o_ok[0:0] + attribute \src "issuer_ls180.v:179699.3-179720.6" + wire width 64 $0\data_r1__fast1$next[63:0]$13149 + attribute \src "issuer_ls180.v:179432.3-179433.45" + wire width 64 $0\data_r1__fast1[63:0] + attribute \src "issuer_ls180.v:179699.3-179720.6" + wire $0\data_r1__fast1_ok$next[0:0]$13150 + attribute \src "issuer_ls180.v:179434.3-179435.51" + wire $0\data_r1__fast1_ok[0:0] + attribute \src "issuer_ls180.v:179721.3-179742.6" + wire width 64 $0\data_r2__fast2$next[63:0]$13157 + attribute \src "issuer_ls180.v:179428.3-179429.45" + wire width 64 $0\data_r2__fast2[63:0] + attribute \src "issuer_ls180.v:179721.3-179742.6" + wire $0\data_r2__fast2_ok$next[0:0]$13158 + attribute \src "issuer_ls180.v:179430.3-179431.51" + wire $0\data_r2__fast2_ok[0:0] + attribute \src "issuer_ls180.v:179743.3-179764.6" + wire width 64 $0\data_r3__nia$next[63:0]$13165 + attribute \src "issuer_ls180.v:179424.3-179425.41" + wire width 64 $0\data_r3__nia[63:0] + attribute \src "issuer_ls180.v:179743.3-179764.6" + wire $0\data_r3__nia_ok$next[0:0]$13166 + attribute \src "issuer_ls180.v:179426.3-179427.47" + wire $0\data_r3__nia_ok[0:0] + attribute \src "issuer_ls180.v:179765.3-179786.6" + wire width 64 $0\data_r4__msr$next[63:0]$13173 + attribute \src "issuer_ls180.v:179420.3-179421.41" + wire width 64 $0\data_r4__msr[63:0] + attribute \src "issuer_ls180.v:179765.3-179786.6" + wire $0\data_r4__msr_ok$next[0:0]$13174 + attribute \src "issuer_ls180.v:179422.3-179423.47" + wire $0\data_r4__msr_ok[0:0] + attribute \src "issuer_ls180.v:179845.3-179854.6" + wire width 64 $0\dest1_o[63:0] + attribute \src "issuer_ls180.v:179855.3-179864.6" + wire width 64 $0\dest2_o[63:0] + attribute \src "issuer_ls180.v:179865.3-179874.6" + wire width 64 $0\dest3_o[63:0] + attribute \src "issuer_ls180.v:179875.3-179884.6" + wire width 64 $0\dest4_o[63:0] + attribute \src "issuer_ls180.v:179885.3-179894.6" + wire width 64 $0\dest5_o[63:0] + attribute \src "issuer_ls180.v:178759.7-178759.20" + wire $0\initial[0:0] + attribute \src "issuer_ls180.v:179615.3-179623.6" + wire $0\opc_l_r_opc$next[0:0]$13109 + attribute \src "issuer_ls180.v:179464.3-179465.39" + wire $0\opc_l_r_opc[0:0] + attribute \src "issuer_ls180.v:179606.3-179614.6" + wire $0\opc_l_s_opc$next[0:0]$13106 + attribute \src "issuer_ls180.v:179466.3-179467.39" + wire $0\opc_l_s_opc[0:0] + attribute \src "issuer_ls180.v:179895.3-179903.6" + wire width 5 $0\prev_wr_go$next[4:0]$13204 + attribute \src "issuer_ls180.v:179476.3-179477.37" + wire width 5 $0\prev_wr_go[4:0] + attribute \src "issuer_ls180.v:179560.3-179569.6" + wire $0\req_done[0:0] + attribute \src "issuer_ls180.v:179651.3-179659.6" + wire width 5 $0\req_l_r_req$next[4:0]$13121 + attribute \src "issuer_ls180.v:179456.3-179457.39" + wire width 5 $0\req_l_r_req[4:0] + attribute \src "issuer_ls180.v:179642.3-179650.6" + wire width 5 $0\req_l_s_req$next[4:0]$13118 + attribute \src "issuer_ls180.v:179458.3-179459.39" + wire width 5 $0\req_l_s_req[4:0] + attribute \src "issuer_ls180.v:179579.3-179587.6" + wire $0\rok_l_r_rdok$next[0:0]$13097 + attribute \src "issuer_ls180.v:179472.3-179473.41" + wire $0\rok_l_r_rdok[0:0] + attribute \src "issuer_ls180.v:179570.3-179578.6" + wire $0\rok_l_s_rdok$next[0:0]$13094 + attribute \src "issuer_ls180.v:179474.3-179475.41" + wire $0\rok_l_s_rdok[0:0] + attribute \src "issuer_ls180.v:179597.3-179605.6" + wire $0\rst_l_r_rst$next[0:0]$13103 + attribute \src "issuer_ls180.v:179468.3-179469.39" + wire $0\rst_l_r_rst[0:0] + attribute \src "issuer_ls180.v:179588.3-179596.6" + wire $0\rst_l_s_rst$next[0:0]$13100 + attribute \src "issuer_ls180.v:179470.3-179471.39" + wire $0\rst_l_s_rst[0:0] + attribute \src "issuer_ls180.v:179633.3-179641.6" + wire width 4 $0\src_l_r_src$next[3:0]$13115 + attribute \src "issuer_ls180.v:179460.3-179461.39" + wire width 4 $0\src_l_r_src[3:0] + attribute \src "issuer_ls180.v:179624.3-179632.6" + wire width 4 $0\src_l_s_src$next[3:0]$13112 + attribute \src "issuer_ls180.v:179462.3-179463.39" + wire width 4 $0\src_l_s_src[3:0] + attribute \src "issuer_ls180.v:179787.3-179796.6" + wire width 64 $0\src_r0$next[63:0]$13181 + attribute \src "issuer_ls180.v:179418.3-179419.29" + wire width 64 $0\src_r0[63:0] + attribute \src "issuer_ls180.v:179797.3-179806.6" + wire width 64 $0\src_r1$next[63:0]$13184 + attribute \src "issuer_ls180.v:179416.3-179417.29" + wire width 64 $0\src_r1[63:0] + attribute \src "issuer_ls180.v:179807.3-179816.6" + wire width 64 $0\src_r2$next[63:0]$13187 + attribute \src "issuer_ls180.v:179414.3-179415.29" + wire width 64 $0\src_r2[63:0] + attribute \src "issuer_ls180.v:179817.3-179826.6" + wire width 64 $0\src_r3$next[63:0]$13190 + attribute \src "issuer_ls180.v:179412.3-179413.29" + wire width 64 $0\src_r3[63:0] + attribute \src "issuer_ls180.v:178885.7-178885.24" + wire $1\all_rd_dly[0:0] + attribute \src "issuer_ls180.v:178895.7-178895.26" + wire $1\alu_done_dly[0:0] + attribute \src "issuer_ls180.v:179836.3-179844.6" + wire $1\alu_l_r_alu$next[0:0]$13197 + attribute \src "issuer_ls180.v:178903.7-178903.25" + wire $1\alu_l_r_alu[0:0] + attribute \src "issuer_ls180.v:179660.3-179676.6" + wire width 64 $1\alu_trap0_trap_op__cia$next[63:0]$13132 + attribute \src "issuer_ls180.v:178939.14-178939.59" + wire width 64 $1\alu_trap0_trap_op__cia[63:0] + attribute \src "issuer_ls180.v:179660.3-179676.6" + wire width 12 $1\alu_trap0_trap_op__fn_unit$next[11:0]$13133 + attribute \src "issuer_ls180.v:178956.14-178956.50" + wire width 12 $1\alu_trap0_trap_op__fn_unit[11:0] + attribute \src "issuer_ls180.v:179660.3-179676.6" + wire width 32 $1\alu_trap0_trap_op__insn$next[31:0]$13134 + attribute \src "issuer_ls180.v:178960.14-178960.45" + wire width 32 $1\alu_trap0_trap_op__insn[31:0] + attribute \src "issuer_ls180.v:179660.3-179676.6" + wire width 7 $1\alu_trap0_trap_op__insn_type$next[6:0]$13135 + attribute \src "issuer_ls180.v:179038.13-179038.49" + wire width 7 $1\alu_trap0_trap_op__insn_type[6:0] + attribute \src "issuer_ls180.v:179660.3-179676.6" + wire $1\alu_trap0_trap_op__is_32bit$next[0:0]$13136 + attribute \src "issuer_ls180.v:179042.7-179042.41" + wire $1\alu_trap0_trap_op__is_32bit[0:0] + attribute \src "issuer_ls180.v:179660.3-179676.6" + wire width 64 $1\alu_trap0_trap_op__msr$next[63:0]$13137 + attribute \src "issuer_ls180.v:179046.14-179046.59" + wire width 64 $1\alu_trap0_trap_op__msr[63:0] + attribute \src "issuer_ls180.v:179660.3-179676.6" + wire width 13 $1\alu_trap0_trap_op__trapaddr$next[12:0]$13138 + attribute \src "issuer_ls180.v:179050.14-179050.52" + wire width 13 $1\alu_trap0_trap_op__trapaddr[12:0] + attribute \src "issuer_ls180.v:179660.3-179676.6" + wire width 7 $1\alu_trap0_trap_op__traptype$next[6:0]$13139 + attribute \src "issuer_ls180.v:179054.13-179054.48" + wire width 7 $1\alu_trap0_trap_op__traptype[6:0] + attribute \src "issuer_ls180.v:179827.3-179835.6" + wire $1\alui_l_r_alui$next[0:0]$13194 + attribute \src "issuer_ls180.v:179060.7-179060.27" + wire $1\alui_l_r_alui[0:0] + attribute \src "issuer_ls180.v:179677.3-179698.6" + wire width 64 $1\data_r0__o$next[63:0]$13143 + attribute \src "issuer_ls180.v:179092.14-179092.47" + wire width 64 $1\data_r0__o[63:0] + attribute \src "issuer_ls180.v:179677.3-179698.6" + wire $1\data_r0__o_ok$next[0:0]$13144 + attribute \src "issuer_ls180.v:179096.7-179096.27" + wire $1\data_r0__o_ok[0:0] + attribute \src "issuer_ls180.v:179699.3-179720.6" + wire width 64 $1\data_r1__fast1$next[63:0]$13151 + attribute \src "issuer_ls180.v:179100.14-179100.51" + wire width 64 $1\data_r1__fast1[63:0] + attribute \src "issuer_ls180.v:179699.3-179720.6" + wire $1\data_r1__fast1_ok$next[0:0]$13152 + attribute \src "issuer_ls180.v:179104.7-179104.31" + wire $1\data_r1__fast1_ok[0:0] + attribute \src "issuer_ls180.v:179721.3-179742.6" + wire width 64 $1\data_r2__fast2$next[63:0]$13159 + attribute \src "issuer_ls180.v:179108.14-179108.51" + wire width 64 $1\data_r2__fast2[63:0] + attribute \src "issuer_ls180.v:179721.3-179742.6" + wire $1\data_r2__fast2_ok$next[0:0]$13160 + attribute \src "issuer_ls180.v:179112.7-179112.31" + wire $1\data_r2__fast2_ok[0:0] + attribute \src "issuer_ls180.v:179743.3-179764.6" + wire width 64 $1\data_r3__nia$next[63:0]$13167 + attribute \src "issuer_ls180.v:179116.14-179116.49" + wire width 64 $1\data_r3__nia[63:0] + attribute \src "issuer_ls180.v:179743.3-179764.6" + wire $1\data_r3__nia_ok$next[0:0]$13168 + attribute \src "issuer_ls180.v:179120.7-179120.29" + wire $1\data_r3__nia_ok[0:0] + attribute \src "issuer_ls180.v:179765.3-179786.6" + wire width 64 $1\data_r4__msr$next[63:0]$13175 + attribute \src "issuer_ls180.v:179124.14-179124.49" + wire width 64 $1\data_r4__msr[63:0] + attribute \src "issuer_ls180.v:179765.3-179786.6" + wire $1\data_r4__msr_ok$next[0:0]$13176 + attribute \src "issuer_ls180.v:179128.7-179128.29" + wire $1\data_r4__msr_ok[0:0] + attribute \src "issuer_ls180.v:179845.3-179854.6" + wire width 64 $1\dest1_o[63:0] + attribute \src "issuer_ls180.v:179855.3-179864.6" + wire width 64 $1\dest2_o[63:0] + attribute \src "issuer_ls180.v:179865.3-179874.6" + wire width 64 $1\dest3_o[63:0] + attribute \src "issuer_ls180.v:179875.3-179884.6" + wire width 64 $1\dest4_o[63:0] + attribute \src "issuer_ls180.v:179885.3-179894.6" + wire width 64 $1\dest5_o[63:0] + attribute \src "issuer_ls180.v:179615.3-179623.6" + wire $1\opc_l_r_opc$next[0:0]$13110 + attribute \src "issuer_ls180.v:179159.7-179159.25" + wire $1\opc_l_r_opc[0:0] + attribute \src "issuer_ls180.v:179606.3-179614.6" + wire $1\opc_l_s_opc$next[0:0]$13107 + attribute \src "issuer_ls180.v:179163.7-179163.25" + wire $1\opc_l_s_opc[0:0] + attribute \src "issuer_ls180.v:179895.3-179903.6" + wire width 5 $1\prev_wr_go$next[4:0]$13205 + attribute \src "issuer_ls180.v:179270.13-179270.31" + wire width 5 $1\prev_wr_go[4:0] + attribute \src "issuer_ls180.v:179560.3-179569.6" + wire $1\req_done[0:0] + attribute \src "issuer_ls180.v:179651.3-179659.6" + wire width 5 $1\req_l_r_req$next[4:0]$13122 + attribute \src "issuer_ls180.v:179278.13-179278.32" + wire width 5 $1\req_l_r_req[4:0] + attribute \src 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$and$issuer_ls180.v:179396$13043_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" + cell $and $and$issuer_ls180.v:179397$13044 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \msr_ok + connect \B \cu_busy_o + connect \Y $and$issuer_ls180.v:179397$13044_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:327" + cell $and $and$issuer_ls180.v:179403$13050 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \alu_trap0_p_ready_o + connect \B \alui_l_q_alui + connect \Y $and$issuer_ls180.v:179403$13050_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:334" + cell $and $and$issuer_ls180.v:179404$13051 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \alu_trap0_n_valid_o + connect \B \alu_l_q_alu + connect \Y $and$issuer_ls180.v:179404$13051_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" + cell $and $and$issuer_ls180.v:179405$13052 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \src_l_q_src + connect \B { \cu_busy_o \cu_busy_o \cu_busy_o \cu_busy_o } + connect \Y $and$issuer_ls180.v:179405$13052_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" + cell $and $and$issuer_ls180.v:179406$13053 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \$93 + connect \B 4'1111 + connect \Y $and$issuer_ls180.v:179406$13053_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" + cell $eq $eq$issuer_ls180.v:179379$13026 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$43 + connect \B 1'0 + connect \Y $eq$issuer_ls180.v:179379$13026_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" + cell $eq $eq$issuer_ls180.v:179381$13028 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cu_wrmask_o + connect \B 1'0 + connect \Y $eq$issuer_ls180.v:179381$13028_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + cell $not $not$issuer_ls180.v:179362$13009 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \all_rd_dly + connect \Y $not$issuer_ls180.v:179362$13009_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" + cell $not $not$issuer_ls180.v:179364$13011 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \alu_done_dly + connect \Y $not$issuer_ls180.v:179364$13011_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" + cell $not $not$issuer_ls180.v:179367$13014 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \Y_WIDTH 5 + connect \A \cu_wrmask_o + connect \Y $not$issuer_ls180.v:179367$13014_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" + cell $not $not$issuer_ls180.v:179370$13017 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$24 + connect \Y $not$issuer_ls180.v:179370$13017_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" + cell $not $not$issuer_ls180.v:179376$13023 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \alu_trap0_n_ready_i + connect \Y $not$issuer_ls180.v:179376$13023_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" + cell $not $not$issuer_ls180.v:179391$13038 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \cu_rd__rel_o + connect \Y $not$issuer_ls180.v:179391$13038_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" + cell $not $not$issuer_ls180.v:179407$13054 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \cu_rdmaskn_i + connect \Y $not$issuer_ls180.v:179407$13054_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" + cell $or $or$issuer_ls180.v:179374$13021 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$33 + connect \B \$35 + connect \Y $or$issuer_ls180.v:179374$13021_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:230" + cell $or $or$issuer_ls180.v:179385$13032 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \req_done + connect \B \cu_go_die_i + connect \Y $or$issuer_ls180.v:179385$13032_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:231" + cell $or $or$issuer_ls180.v:179386$13033 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \cu_issue_i + connect \B \cu_go_die_i + connect \Y $or$issuer_ls180.v:179386$13033_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:232" + cell $or $or$issuer_ls180.v:179387$13034 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 5 + connect \A \cu_wr__go_i + connect \B { \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i } + connect \Y $or$issuer_ls180.v:179387$13034_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:233" + cell $or $or$issuer_ls180.v:179388$13035 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \cu_rd__go_i + connect \B { \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i } + connect \Y $or$issuer_ls180.v:179388$13035_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:253" + cell $or $or$issuer_ls180.v:179392$13039 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \B_SIGNED 0 + parameter \B_WIDTH 5 + parameter \Y_WIDTH 5 + connect \A \reset_w + connect \B \prev_wr_go + connect \Y $or$issuer_ls180.v:179392$13039_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" + cell $or $or$issuer_ls180.v:179402$13049 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \$6 + connect \B \cu_rd__go_i + connect \Y $or$issuer_ls180.v:179402$13049_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" + cell $reduce_and $reduce_and$issuer_ls180.v:179347$12994 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \$8 + connect \Y $reduce_and$issuer_ls180.v:179347$12994_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" + cell $reduce_or $reduce_or$issuer_ls180.v:179369$13016 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \$27 + connect \Y $reduce_or$issuer_ls180.v:179369$13016_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" + cell $reduce_or $reduce_or$issuer_ls180.v:179372$13019 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \cu_wr__go_i + connect \Y $reduce_or$issuer_ls180.v:179372$13019_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" + cell $reduce_or $reduce_or$issuer_ls180.v:179373$13020 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \prev_wr_go + connect \Y $reduce_or$issuer_ls180.v:179373$13020_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + cell $mux $ternary$issuer_ls180.v:179398$13045 + parameter \WIDTH 64 + connect \A \src_r0 + connect \B \src1_i + connect \S \src_l_q_src [0] + connect \Y $ternary$issuer_ls180.v:179398$13045_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + cell $mux $ternary$issuer_ls180.v:179399$13046 + parameter \WIDTH 64 + connect \A \src_r1 + connect \B \src2_i + connect \S \src_l_q_src [1] + connect \Y $ternary$issuer_ls180.v:179399$13046_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + cell $mux $ternary$issuer_ls180.v:179400$13047 + parameter \WIDTH 64 + connect \A \src_r2 + connect \B \src3_i + connect \S \src_l_q_src [2] + connect \Y $ternary$issuer_ls180.v:179400$13047_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" + cell $mux $ternary$issuer_ls180.v:179401$13048 + parameter \WIDTH 64 + connect \A \src_r3 + connect \B \src4_i + connect \S \src_l_q_src [3] + connect \Y $ternary$issuer_ls180.v:179401$13048_Y + end + attribute \module_not_derived 1 + attribute \src "issuer_ls180.v:179482.14-179488.4" + cell \alu_l$42 \alu_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_alu \alu_l_q_alu + connect \r_alu \alu_l_r_alu + connect \s_alu \alu_l_s_alu + end + attribute \module_not_derived 1 + attribute \src "issuer_ls180.v:179489.13-179518.4" + cell \alu_trap0 \alu_trap0 + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \fast1 \alu_trap0_fast1 + connect \fast1$1 \alu_trap0_fast1$1 + connect \fast1_ok \fast1_ok + connect \fast2 \alu_trap0_fast2 + connect \fast2$2 \alu_trap0_fast2$2 + connect \fast2_ok \fast2_ok + connect \msr \alu_trap0_msr + connect \msr_ok \msr_ok + connect \n_ready_i \alu_trap0_n_ready_i + connect \n_valid_o \alu_trap0_n_valid_o + connect \nia \alu_trap0_nia + connect \nia_ok \nia_ok + connect \o \alu_trap0_o + connect \o_ok \o_ok + connect \p_ready_o \alu_trap0_p_ready_o + connect \p_valid_i \alu_trap0_p_valid_i + connect \ra \alu_trap0_ra + connect \rb \alu_trap0_rb + connect \trap_op__cia \alu_trap0_trap_op__cia + connect \trap_op__fn_unit \alu_trap0_trap_op__fn_unit + connect \trap_op__insn \alu_trap0_trap_op__insn + connect \trap_op__insn_type \alu_trap0_trap_op__insn_type + connect \trap_op__is_32bit \alu_trap0_trap_op__is_32bit + connect \trap_op__msr \alu_trap0_trap_op__msr + connect \trap_op__trapaddr \alu_trap0_trap_op__trapaddr + connect \trap_op__traptype \alu_trap0_trap_op__traptype + end + attribute \module_not_derived 1 + attribute \src "issuer_ls180.v:179519.15-179525.4" + cell \alui_l$41 \alui_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_alui \alui_l_q_alui + connect \r_alui \alui_l_r_alui + connect \s_alui \alui_l_s_alui + end + attribute \module_not_derived 1 + attribute \src "issuer_ls180.v:179526.14-179532.4" + cell \opc_l$37 \opc_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_opc \opc_l_q_opc + connect \r_opc \opc_l_r_opc + connect \s_opc \opc_l_s_opc + end + attribute \module_not_derived 1 + attribute \src "issuer_ls180.v:179533.14-179539.4" + cell \req_l$38 \req_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_req \req_l_q_req + connect \r_req \req_l_r_req + connect \s_req \req_l_s_req + end + attribute \module_not_derived 1 + attribute \src "issuer_ls180.v:179540.14-179546.4" + cell \rok_l$40 \rok_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_rdok \rok_l_q_rdok + connect \r_rdok \rok_l_r_rdok + connect \s_rdok \rok_l_s_rdok + end + attribute \module_not_derived 1 + attribute \src "issuer_ls180.v:179547.14-179552.4" + cell \rst_l$39 \rst_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \r_rst \rst_l_r_rst + connect \s_rst \rst_l_s_rst + end + attribute \module_not_derived 1 + attribute \src "issuer_ls180.v:179553.14-179559.4" + cell \src_l$36 \src_l + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \q_src \src_l_q_src + connect \r_src \src_l_r_src + connect \s_src \src_l_s_src + end + attribute \src "issuer_ls180.v:178759.7-178759.20" + process $proc$issuer_ls180.v:178759$13206 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "issuer_ls180.v:178885.7-178885.24" + process $proc$issuer_ls180.v:178885$13207 + assign { } { } + assign $1\all_rd_dly[0:0] 1'0 + sync always + sync init + update \all_rd_dly $1\all_rd_dly[0:0] + end + attribute \src "issuer_ls180.v:178895.7-178895.26" + process $proc$issuer_ls180.v:178895$13208 + assign { } { } + assign $1\alu_done_dly[0:0] 1'0 + sync always + sync init + update \alu_done_dly $1\alu_done_dly[0:0] + end + attribute \src "issuer_ls180.v:178903.7-178903.25" + process $proc$issuer_ls180.v:178903$13209 + assign { } { } + assign $1\alu_l_r_alu[0:0] 1'1 + sync always + sync init + update \alu_l_r_alu $1\alu_l_r_alu[0:0] + end + attribute \src "issuer_ls180.v:178939.14-178939.59" + process $proc$issuer_ls180.v:178939$13210 + assign { } { } + assign $1\alu_trap0_trap_op__cia[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \alu_trap0_trap_op__cia $1\alu_trap0_trap_op__cia[63:0] + end + attribute \src "issuer_ls180.v:178956.14-178956.50" + process $proc$issuer_ls180.v:178956$13211 + assign { } { } + assign $1\alu_trap0_trap_op__fn_unit[11:0] 12'000000000000 + sync always + sync init + update \alu_trap0_trap_op__fn_unit $1\alu_trap0_trap_op__fn_unit[11:0] + end + attribute \src "issuer_ls180.v:178960.14-178960.45" + process $proc$issuer_ls180.v:178960$13212 + assign { } { } + assign $1\alu_trap0_trap_op__insn[31:0] 0 + sync always + sync init + update \alu_trap0_trap_op__insn $1\alu_trap0_trap_op__insn[31:0] + end + attribute \src "issuer_ls180.v:179038.13-179038.49" + process $proc$issuer_ls180.v:179038$13213 + assign { } { } + assign $1\alu_trap0_trap_op__insn_type[6:0] 7'0000000 + sync always + sync init + update \alu_trap0_trap_op__insn_type $1\alu_trap0_trap_op__insn_type[6:0] + end + attribute \src "issuer_ls180.v:179042.7-179042.41" + process $proc$issuer_ls180.v:179042$13214 + assign { } { } + assign $1\alu_trap0_trap_op__is_32bit[0:0] 1'0 + sync always + sync init + update \alu_trap0_trap_op__is_32bit $1\alu_trap0_trap_op__is_32bit[0:0] + end + attribute \src "issuer_ls180.v:179046.14-179046.59" + process $proc$issuer_ls180.v:179046$13215 + assign { } { } + assign $1\alu_trap0_trap_op__msr[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \alu_trap0_trap_op__msr $1\alu_trap0_trap_op__msr[63:0] + end + attribute \src "issuer_ls180.v:179050.14-179050.52" + process $proc$issuer_ls180.v:179050$13216 + assign { } { } + assign $1\alu_trap0_trap_op__trapaddr[12:0] 13'0000000000000 + sync always + sync init + update \alu_trap0_trap_op__trapaddr $1\alu_trap0_trap_op__trapaddr[12:0] + end + attribute \src "issuer_ls180.v:179054.13-179054.48" + process $proc$issuer_ls180.v:179054$13217 + assign { } { } + assign $1\alu_trap0_trap_op__traptype[6:0] 7'0000000 + sync always + sync init + update \alu_trap0_trap_op__traptype $1\alu_trap0_trap_op__traptype[6:0] + end + attribute \src "issuer_ls180.v:179060.7-179060.27" + process $proc$issuer_ls180.v:179060$13218 + assign { } { } + assign $1\alui_l_r_alui[0:0] 1'1 + sync always + sync init + update \alui_l_r_alui $1\alui_l_r_alui[0:0] + end + attribute \src "issuer_ls180.v:179092.14-179092.47" + process $proc$issuer_ls180.v:179092$13219 + assign { } { } + assign $1\data_r0__o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \data_r0__o $1\data_r0__o[63:0] + end + attribute \src "issuer_ls180.v:179096.7-179096.27" + process $proc$issuer_ls180.v:179096$13220 + assign { } { } + assign $1\data_r0__o_ok[0:0] 1'0 + sync always + sync init + update \data_r0__o_ok $1\data_r0__o_ok[0:0] + end + attribute \src "issuer_ls180.v:179100.14-179100.51" + process $proc$issuer_ls180.v:179100$13221 + assign { } { } + assign $1\data_r1__fast1[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \data_r1__fast1 $1\data_r1__fast1[63:0] + end + attribute \src "issuer_ls180.v:179104.7-179104.31" + process $proc$issuer_ls180.v:179104$13222 + assign { } { } + assign $1\data_r1__fast1_ok[0:0] 1'0 + sync always + sync init + update \data_r1__fast1_ok $1\data_r1__fast1_ok[0:0] + end + attribute \src "issuer_ls180.v:179108.14-179108.51" + process $proc$issuer_ls180.v:179108$13223 + assign { } { } + assign $1\data_r2__fast2[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \data_r2__fast2 $1\data_r2__fast2[63:0] + end + attribute \src "issuer_ls180.v:179112.7-179112.31" + process $proc$issuer_ls180.v:179112$13224 + assign { } { } + assign $1\data_r2__fast2_ok[0:0] 1'0 + sync always + sync init + update \data_r2__fast2_ok $1\data_r2__fast2_ok[0:0] + end + attribute \src "issuer_ls180.v:179116.14-179116.49" + process $proc$issuer_ls180.v:179116$13225 + assign { } { } + assign $1\data_r3__nia[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \data_r3__nia $1\data_r3__nia[63:0] + end + attribute \src "issuer_ls180.v:179120.7-179120.29" + process $proc$issuer_ls180.v:179120$13226 + assign { } { } + assign $1\data_r3__nia_ok[0:0] 1'0 + sync always + sync init + update \data_r3__nia_ok $1\data_r3__nia_ok[0:0] + end + attribute \src "issuer_ls180.v:179124.14-179124.49" + process $proc$issuer_ls180.v:179124$13227 + assign { } { } + assign $1\data_r4__msr[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \data_r4__msr $1\data_r4__msr[63:0] + end + attribute \src "issuer_ls180.v:179128.7-179128.29" + process $proc$issuer_ls180.v:179128$13228 + assign { } { } + assign $1\data_r4__msr_ok[0:0] 1'0 + sync always + sync init + update \data_r4__msr_ok $1\data_r4__msr_ok[0:0] + end + attribute \src "issuer_ls180.v:179159.7-179159.25" + process $proc$issuer_ls180.v:179159$13229 + assign { } { } + assign $1\opc_l_r_opc[0:0] 1'1 + sync always + sync init + update \opc_l_r_opc $1\opc_l_r_opc[0:0] + end + attribute \src "issuer_ls180.v:179163.7-179163.25" + process $proc$issuer_ls180.v:179163$13230 + assign { } { } + assign $1\opc_l_s_opc[0:0] 1'0 + sync always + sync init + update \opc_l_s_opc $1\opc_l_s_opc[0:0] + end + attribute \src "issuer_ls180.v:179270.13-179270.31" + process $proc$issuer_ls180.v:179270$13231 + assign { } { } + assign $1\prev_wr_go[4:0] 5'00000 + sync always + sync init + update \prev_wr_go $1\prev_wr_go[4:0] + end + attribute \src "issuer_ls180.v:179278.13-179278.32" + process $proc$issuer_ls180.v:179278$13232 + assign { } { } + assign $1\req_l_r_req[4:0] 5'11111 + sync always + sync init + update \req_l_r_req $1\req_l_r_req[4:0] + end + attribute \src "issuer_ls180.v:179282.13-179282.32" + process $proc$issuer_ls180.v:179282$13233 + assign { } { } + assign $1\req_l_s_req[4:0] 5'00000 + sync always + sync init + update \req_l_s_req $1\req_l_s_req[4:0] + end + attribute \src "issuer_ls180.v:179294.7-179294.26" + process $proc$issuer_ls180.v:179294$13234 + assign { } { } + assign $1\rok_l_r_rdok[0:0] 1'1 + sync always + sync init + update \rok_l_r_rdok $1\rok_l_r_rdok[0:0] + end + attribute \src "issuer_ls180.v:179298.7-179298.26" + process $proc$issuer_ls180.v:179298$13235 + assign { } { } + assign $1\rok_l_s_rdok[0:0] 1'0 + sync always + sync init + update \rok_l_s_rdok $1\rok_l_s_rdok[0:0] + end + attribute \src "issuer_ls180.v:179302.7-179302.25" + process $proc$issuer_ls180.v:179302$13236 + assign { } { } + assign $1\rst_l_r_rst[0:0] 1'1 + sync always + sync init + update \rst_l_r_rst $1\rst_l_r_rst[0:0] + end + attribute \src "issuer_ls180.v:179306.7-179306.25" + process $proc$issuer_ls180.v:179306$13237 + assign { } { } + assign $1\rst_l_s_rst[0:0] 1'0 + sync always + sync init + update \rst_l_s_rst $1\rst_l_s_rst[0:0] + end + attribute \src "issuer_ls180.v:179322.13-179322.31" + process $proc$issuer_ls180.v:179322$13238 + assign { } { } + assign $1\src_l_r_src[3:0] 4'1111 + sync always + sync init + update \src_l_r_src $1\src_l_r_src[3:0] + end + attribute \src "issuer_ls180.v:179326.13-179326.31" + process $proc$issuer_ls180.v:179326$13239 + assign { } { } + assign $1\src_l_s_src[3:0] 4'0000 + sync always + sync init + update \src_l_s_src $1\src_l_s_src[3:0] + end + attribute \src "issuer_ls180.v:179330.14-179330.43" + process $proc$issuer_ls180.v:179330$13240 + assign { } { } + assign $1\src_r0[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \src_r0 $1\src_r0[63:0] + end + attribute \src "issuer_ls180.v:179334.14-179334.43" + process $proc$issuer_ls180.v:179334$13241 + assign { } { } + assign $1\src_r1[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \src_r1 $1\src_r1[63:0] + end + attribute \src "issuer_ls180.v:179338.14-179338.43" + process $proc$issuer_ls180.v:179338$13242 + assign { } { } + assign $1\src_r2[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \src_r2 $1\src_r2[63:0] + end + attribute \src "issuer_ls180.v:179342.14-179342.43" + process $proc$issuer_ls180.v:179342$13243 + assign { } { } + assign $1\src_r3[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + sync always + sync init + update \src_r3 $1\src_r3[63:0] + end + attribute \src "issuer_ls180.v:179408.3-179409.39" + process $proc$issuer_ls180.v:179408$13055 + assign { } { } + assign $0\alu_l_r_alu[0:0] \alu_l_r_alu$next + sync posedge \coresync_clk + update \alu_l_r_alu $0\alu_l_r_alu[0:0] + end + attribute \src "issuer_ls180.v:179410.3-179411.43" + process $proc$issuer_ls180.v:179410$13056 + assign { } { } + assign $0\alui_l_r_alui[0:0] \alui_l_r_alui$next + sync posedge \coresync_clk + update \alui_l_r_alui $0\alui_l_r_alui[0:0] + end + attribute \src "issuer_ls180.v:179412.3-179413.29" + process $proc$issuer_ls180.v:179412$13057 + assign { } { } + assign $0\src_r3[63:0] \src_r3$next + sync posedge \coresync_clk + update \src_r3 $0\src_r3[63:0] + end + attribute \src "issuer_ls180.v:179414.3-179415.29" + process $proc$issuer_ls180.v:179414$13058 + assign { } { } + assign $0\src_r2[63:0] \src_r2$next + sync posedge \coresync_clk + update \src_r2 $0\src_r2[63:0] + end + attribute \src "issuer_ls180.v:179416.3-179417.29" + process $proc$issuer_ls180.v:179416$13059 + assign { } { } + assign $0\src_r1[63:0] \src_r1$next + sync posedge \coresync_clk + update \src_r1 $0\src_r1[63:0] + end + attribute \src "issuer_ls180.v:179418.3-179419.29" + process $proc$issuer_ls180.v:179418$13060 + assign { } { } + assign $0\src_r0[63:0] \src_r0$next + sync posedge \coresync_clk + update \src_r0 $0\src_r0[63:0] + end + attribute \src "issuer_ls180.v:179420.3-179421.41" + process $proc$issuer_ls180.v:179420$13061 + assign { } { } + assign $0\data_r4__msr[63:0] \data_r4__msr$next + sync posedge \coresync_clk + update \data_r4__msr $0\data_r4__msr[63:0] + end + attribute \src "issuer_ls180.v:179422.3-179423.47" + process $proc$issuer_ls180.v:179422$13062 + assign { } { } + assign $0\data_r4__msr_ok[0:0] \data_r4__msr_ok$next + sync posedge \coresync_clk + update \data_r4__msr_ok $0\data_r4__msr_ok[0:0] + end + attribute \src "issuer_ls180.v:179424.3-179425.41" + process $proc$issuer_ls180.v:179424$13063 + assign { } { } + assign $0\data_r3__nia[63:0] \data_r3__nia$next + sync posedge \coresync_clk + update \data_r3__nia $0\data_r3__nia[63:0] + end + attribute \src "issuer_ls180.v:179426.3-179427.47" + process $proc$issuer_ls180.v:179426$13064 + assign { } { } + assign $0\data_r3__nia_ok[0:0] \data_r3__nia_ok$next + sync posedge \coresync_clk + update \data_r3__nia_ok $0\data_r3__nia_ok[0:0] + end + attribute \src "issuer_ls180.v:179428.3-179429.45" + process $proc$issuer_ls180.v:179428$13065 + assign { } { } + assign $0\data_r2__fast2[63:0] \data_r2__fast2$next + sync posedge \coresync_clk + update \data_r2__fast2 $0\data_r2__fast2[63:0] + end + attribute \src "issuer_ls180.v:179430.3-179431.51" + process $proc$issuer_ls180.v:179430$13066 + assign { } { } + assign $0\data_r2__fast2_ok[0:0] \data_r2__fast2_ok$next + sync posedge \coresync_clk + update \data_r2__fast2_ok $0\data_r2__fast2_ok[0:0] + end + attribute \src "issuer_ls180.v:179432.3-179433.45" + process $proc$issuer_ls180.v:179432$13067 + assign { } { } + assign $0\data_r1__fast1[63:0] \data_r1__fast1$next + sync posedge \coresync_clk + update \data_r1__fast1 $0\data_r1__fast1[63:0] + end + attribute \src "issuer_ls180.v:179434.3-179435.51" + process $proc$issuer_ls180.v:179434$13068 + assign { } { } + assign $0\data_r1__fast1_ok[0:0] \data_r1__fast1_ok$next + sync posedge \coresync_clk + update \data_r1__fast1_ok $0\data_r1__fast1_ok[0:0] + end + attribute \src "issuer_ls180.v:179436.3-179437.37" + process $proc$issuer_ls180.v:179436$13069 + assign { } { } + assign $0\data_r0__o[63:0] \data_r0__o$next + sync posedge \coresync_clk + update \data_r0__o $0\data_r0__o[63:0] + end + attribute \src "issuer_ls180.v:179438.3-179439.43" + process $proc$issuer_ls180.v:179438$13070 + assign { } { } + assign $0\data_r0__o_ok[0:0] \data_r0__o_ok$next + sync posedge \coresync_clk + update \data_r0__o_ok $0\data_r0__o_ok[0:0] + end + attribute \src "issuer_ls180.v:179440.3-179441.73" + process $proc$issuer_ls180.v:179440$13071 + assign { } { } + assign $0\alu_trap0_trap_op__insn_type[6:0] \alu_trap0_trap_op__insn_type$next + sync posedge \coresync_clk + update \alu_trap0_trap_op__insn_type $0\alu_trap0_trap_op__insn_type[6:0] + end + attribute \src "issuer_ls180.v:179442.3-179443.69" + process $proc$issuer_ls180.v:179442$13072 + assign { } { } + assign $0\alu_trap0_trap_op__fn_unit[11:0] \alu_trap0_trap_op__fn_unit$next + sync posedge \coresync_clk + update \alu_trap0_trap_op__fn_unit $0\alu_trap0_trap_op__fn_unit[11:0] + end + attribute \src "issuer_ls180.v:179444.3-179445.63" + process $proc$issuer_ls180.v:179444$13073 + assign { } { } + assign $0\alu_trap0_trap_op__insn[31:0] \alu_trap0_trap_op__insn$next + sync posedge \coresync_clk + update \alu_trap0_trap_op__insn $0\alu_trap0_trap_op__insn[31:0] + end + attribute \src "issuer_ls180.v:179446.3-179447.61" + process $proc$issuer_ls180.v:179446$13074 + assign { } { } + assign $0\alu_trap0_trap_op__msr[63:0] \alu_trap0_trap_op__msr$next + sync posedge \coresync_clk + update \alu_trap0_trap_op__msr $0\alu_trap0_trap_op__msr[63:0] + end + attribute \src "issuer_ls180.v:179448.3-179449.61" + process $proc$issuer_ls180.v:179448$13075 + assign { } { } + assign $0\alu_trap0_trap_op__cia[63:0] \alu_trap0_trap_op__cia$next + sync posedge \coresync_clk + update \alu_trap0_trap_op__cia $0\alu_trap0_trap_op__cia[63:0] + end + attribute \src "issuer_ls180.v:179450.3-179451.71" + process $proc$issuer_ls180.v:179450$13076 + assign { } { } + assign $0\alu_trap0_trap_op__is_32bit[0:0] \alu_trap0_trap_op__is_32bit$next + sync posedge \coresync_clk + update \alu_trap0_trap_op__is_32bit $0\alu_trap0_trap_op__is_32bit[0:0] + end + attribute \src "issuer_ls180.v:179452.3-179453.71" + process $proc$issuer_ls180.v:179452$13077 + assign { } { } + assign $0\alu_trap0_trap_op__traptype[6:0] \alu_trap0_trap_op__traptype$next + sync posedge \coresync_clk + update \alu_trap0_trap_op__traptype $0\alu_trap0_trap_op__traptype[6:0] + end + attribute \src "issuer_ls180.v:179454.3-179455.71" + process $proc$issuer_ls180.v:179454$13078 + assign { } { } + assign $0\alu_trap0_trap_op__trapaddr[12:0] \alu_trap0_trap_op__trapaddr$next + sync posedge \coresync_clk + update \alu_trap0_trap_op__trapaddr $0\alu_trap0_trap_op__trapaddr[12:0] + end + attribute \src "issuer_ls180.v:179456.3-179457.39" + process $proc$issuer_ls180.v:179456$13079 + assign { } { } + assign $0\req_l_r_req[4:0] \req_l_r_req$next + sync posedge \coresync_clk + update \req_l_r_req $0\req_l_r_req[4:0] + end + attribute \src "issuer_ls180.v:179458.3-179459.39" + process $proc$issuer_ls180.v:179458$13080 + assign { } { } + assign $0\req_l_s_req[4:0] \req_l_s_req$next + sync posedge \coresync_clk + update \req_l_s_req $0\req_l_s_req[4:0] + end + attribute \src "issuer_ls180.v:179460.3-179461.39" + process $proc$issuer_ls180.v:179460$13081 + assign { } { } + assign $0\src_l_r_src[3:0] \src_l_r_src$next + sync posedge \coresync_clk + update \src_l_r_src $0\src_l_r_src[3:0] + end + attribute \src "issuer_ls180.v:179462.3-179463.39" + process $proc$issuer_ls180.v:179462$13082 + assign { } { } + assign $0\src_l_s_src[3:0] \src_l_s_src$next + sync posedge \coresync_clk + update \src_l_s_src $0\src_l_s_src[3:0] + end + attribute \src "issuer_ls180.v:179464.3-179465.39" + process $proc$issuer_ls180.v:179464$13083 + assign { } { } + assign $0\opc_l_r_opc[0:0] \opc_l_r_opc$next + sync posedge \coresync_clk + update \opc_l_r_opc $0\opc_l_r_opc[0:0] + end + attribute \src "issuer_ls180.v:179466.3-179467.39" + process $proc$issuer_ls180.v:179466$13084 + assign { } { } + assign $0\opc_l_s_opc[0:0] \opc_l_s_opc$next + sync posedge \coresync_clk + update \opc_l_s_opc $0\opc_l_s_opc[0:0] + end + attribute \src "issuer_ls180.v:179468.3-179469.39" + process $proc$issuer_ls180.v:179468$13085 + assign { } { } + assign $0\rst_l_r_rst[0:0] \rst_l_r_rst$next + sync posedge \coresync_clk + update \rst_l_r_rst $0\rst_l_r_rst[0:0] + end + attribute \src "issuer_ls180.v:179470.3-179471.39" + process $proc$issuer_ls180.v:179470$13086 + assign { } { } + assign $0\rst_l_s_rst[0:0] \rst_l_s_rst$next + sync posedge \coresync_clk + update \rst_l_s_rst $0\rst_l_s_rst[0:0] + end + attribute \src "issuer_ls180.v:179472.3-179473.41" + process $proc$issuer_ls180.v:179472$13087 + assign { } { } + assign $0\rok_l_r_rdok[0:0] \rok_l_r_rdok$next + sync posedge \coresync_clk + update \rok_l_r_rdok $0\rok_l_r_rdok[0:0] + end + attribute \src "issuer_ls180.v:179474.3-179475.41" + process $proc$issuer_ls180.v:179474$13088 + assign { } { } + assign $0\rok_l_s_rdok[0:0] \rok_l_s_rdok$next + sync posedge \coresync_clk + update \rok_l_s_rdok $0\rok_l_s_rdok[0:0] + end + attribute \src "issuer_ls180.v:179476.3-179477.37" + process $proc$issuer_ls180.v:179476$13089 + assign { } { } + assign $0\prev_wr_go[4:0] \prev_wr_go$next + sync posedge \coresync_clk + update \prev_wr_go $0\prev_wr_go[4:0] + end + attribute \src "issuer_ls180.v:179478.3-179479.41" + process $proc$issuer_ls180.v:179478$13090 + assign { } { } + assign $0\alu_done_dly[0:0] \alu_trap0_n_valid_o + sync posedge \coresync_clk + update \alu_done_dly $0\alu_done_dly[0:0] + end + attribute \src "issuer_ls180.v:179480.3-179481.25" + process $proc$issuer_ls180.v:179480$13091 + assign { } { } + assign $0\all_rd_dly[0:0] \$11 + sync posedge \coresync_clk + update \all_rd_dly $0\all_rd_dly[0:0] + end + attribute \src "issuer_ls180.v:179560.3-179569.6" + process $proc$issuer_ls180.v:179560$13092 + assign { } { } + assign { } { } + assign $0\req_done[0:0] $1\req_done[0:0] + attribute \src "issuer_ls180.v:179561.5-179561.29" + switch \initial + attribute \src "issuer_ls180.v:179561.9-179561.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" + switch \$55 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\req_done[0:0] 1'1 + case + assign $1\req_done[0:0] \$47 + end + sync always + update \req_done $0\req_done[0:0] + end + attribute \src "issuer_ls180.v:179570.3-179578.6" + process $proc$issuer_ls180.v:179570$13093 + assign { } { } + assign { } { } + assign $0\rok_l_s_rdok$next[0:0]$13094 $1\rok_l_s_rdok$next[0:0]$13095 + attribute \src "issuer_ls180.v:179571.5-179571.29" + switch \initial + attribute \src "issuer_ls180.v:179571.9-179571.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\rok_l_s_rdok$next[0:0]$13095 1'0 + case + assign $1\rok_l_s_rdok$next[0:0]$13095 \cu_issue_i + end + sync always + update \rok_l_s_rdok$next $0\rok_l_s_rdok$next[0:0]$13094 + end + attribute \src "issuer_ls180.v:179579.3-179587.6" + process $proc$issuer_ls180.v:179579$13096 + assign { } { } + assign { } { } + assign $0\rok_l_r_rdok$next[0:0]$13097 $1\rok_l_r_rdok$next[0:0]$13098 + attribute \src "issuer_ls180.v:179580.5-179580.29" + switch \initial + attribute \src "issuer_ls180.v:179580.9-179580.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\rok_l_r_rdok$next[0:0]$13098 1'1 + case + assign $1\rok_l_r_rdok$next[0:0]$13098 \$65 + end + sync always + update \rok_l_r_rdok$next $0\rok_l_r_rdok$next[0:0]$13097 + end + attribute \src "issuer_ls180.v:179588.3-179596.6" + process $proc$issuer_ls180.v:179588$13099 + assign { } { } + assign { } { } + assign $0\rst_l_s_rst$next[0:0]$13100 $1\rst_l_s_rst$next[0:0]$13101 + attribute \src "issuer_ls180.v:179589.5-179589.29" + switch \initial + attribute \src "issuer_ls180.v:179589.9-179589.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\rst_l_s_rst$next[0:0]$13101 1'0 + case + assign $1\rst_l_s_rst$next[0:0]$13101 \all_rd + end + sync always + update \rst_l_s_rst$next $0\rst_l_s_rst$next[0:0]$13100 + end + attribute \src "issuer_ls180.v:179597.3-179605.6" + process $proc$issuer_ls180.v:179597$13102 + assign { } { } + assign { } { } + assign $0\rst_l_r_rst$next[0:0]$13103 $1\rst_l_r_rst$next[0:0]$13104 + attribute \src "issuer_ls180.v:179598.5-179598.29" + switch \initial + attribute \src "issuer_ls180.v:179598.9-179598.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\rst_l_r_rst$next[0:0]$13104 1'1 + case + assign $1\rst_l_r_rst$next[0:0]$13104 \rst_r + end + sync always + update \rst_l_r_rst$next $0\rst_l_r_rst$next[0:0]$13103 + end + attribute \src "issuer_ls180.v:179606.3-179614.6" + process $proc$issuer_ls180.v:179606$13105 + assign { } { } + assign { } { } + assign $0\opc_l_s_opc$next[0:0]$13106 $1\opc_l_s_opc$next[0:0]$13107 + attribute \src "issuer_ls180.v:179607.5-179607.29" + switch \initial + attribute \src "issuer_ls180.v:179607.9-179607.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\opc_l_s_opc$next[0:0]$13107 1'0 + case + assign $1\opc_l_s_opc$next[0:0]$13107 \cu_issue_i + end + sync always + update \opc_l_s_opc$next $0\opc_l_s_opc$next[0:0]$13106 + end + attribute \src "issuer_ls180.v:179615.3-179623.6" + process $proc$issuer_ls180.v:179615$13108 + assign { } { } + assign { } { } + assign $0\opc_l_r_opc$next[0:0]$13109 $1\opc_l_r_opc$next[0:0]$13110 + attribute \src "issuer_ls180.v:179616.5-179616.29" + switch \initial + attribute \src "issuer_ls180.v:179616.9-179616.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\opc_l_r_opc$next[0:0]$13110 1'1 + case + assign $1\opc_l_r_opc$next[0:0]$13110 \req_done + end + sync always + update \opc_l_r_opc$next $0\opc_l_r_opc$next[0:0]$13109 + end + attribute \src "issuer_ls180.v:179624.3-179632.6" + process $proc$issuer_ls180.v:179624$13111 + assign { } { } + assign { } { } + assign $0\src_l_s_src$next[3:0]$13112 $1\src_l_s_src$next[3:0]$13113 + attribute \src "issuer_ls180.v:179625.5-179625.29" + switch \initial + attribute \src "issuer_ls180.v:179625.9-179625.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\src_l_s_src$next[3:0]$13113 4'0000 + case + assign $1\src_l_s_src$next[3:0]$13113 { \cu_issue_i \cu_issue_i \cu_issue_i \cu_issue_i } + end + sync always + update \src_l_s_src$next $0\src_l_s_src$next[3:0]$13112 + end + attribute \src "issuer_ls180.v:179633.3-179641.6" + process $proc$issuer_ls180.v:179633$13114 + assign { } { } + assign { } { } + assign $0\src_l_r_src$next[3:0]$13115 $1\src_l_r_src$next[3:0]$13116 + attribute \src "issuer_ls180.v:179634.5-179634.29" + switch \initial + attribute \src "issuer_ls180.v:179634.9-179634.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\src_l_r_src$next[3:0]$13116 4'1111 + case + assign $1\src_l_r_src$next[3:0]$13116 \reset_r + end + sync always + update \src_l_r_src$next $0\src_l_r_src$next[3:0]$13115 + end + attribute \src "issuer_ls180.v:179642.3-179650.6" + process $proc$issuer_ls180.v:179642$13117 + assign { } { } + assign { } { } + assign $0\req_l_s_req$next[4:0]$13118 $1\req_l_s_req$next[4:0]$13119 + attribute \src "issuer_ls180.v:179643.5-179643.29" + switch \initial + attribute \src "issuer_ls180.v:179643.9-179643.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\req_l_s_req$next[4:0]$13119 5'00000 + case + assign $1\req_l_s_req$next[4:0]$13119 \$67 + end + sync always + update \req_l_s_req$next $0\req_l_s_req$next[4:0]$13118 + end + attribute \src "issuer_ls180.v:179651.3-179659.6" + process $proc$issuer_ls180.v:179651$13120 + assign { } { } + assign { } { } + assign $0\req_l_r_req$next[4:0]$13121 $1\req_l_r_req$next[4:0]$13122 + attribute \src "issuer_ls180.v:179652.5-179652.29" + switch \initial + attribute \src "issuer_ls180.v:179652.9-179652.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\req_l_r_req$next[4:0]$13122 5'11111 + case + assign $1\req_l_r_req$next[4:0]$13122 \$69 + end + sync always + update \req_l_r_req$next $0\req_l_r_req$next[4:0]$13121 + end + attribute \src "issuer_ls180.v:179660.3-179676.6" + process $proc$issuer_ls180.v:179660$13123 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\alu_trap0_trap_op__cia$next[63:0]$13124 $1\alu_trap0_trap_op__cia$next[63:0]$13132 + assign $0\alu_trap0_trap_op__fn_unit$next[11:0]$13125 $1\alu_trap0_trap_op__fn_unit$next[11:0]$13133 + assign $0\alu_trap0_trap_op__insn$next[31:0]$13126 $1\alu_trap0_trap_op__insn$next[31:0]$13134 + assign $0\alu_trap0_trap_op__insn_type$next[6:0]$13127 $1\alu_trap0_trap_op__insn_type$next[6:0]$13135 + assign $0\alu_trap0_trap_op__is_32bit$next[0:0]$13128 $1\alu_trap0_trap_op__is_32bit$next[0:0]$13136 + assign $0\alu_trap0_trap_op__msr$next[63:0]$13129 $1\alu_trap0_trap_op__msr$next[63:0]$13137 + assign $0\alu_trap0_trap_op__trapaddr$next[12:0]$13130 $1\alu_trap0_trap_op__trapaddr$next[12:0]$13138 + assign $0\alu_trap0_trap_op__traptype$next[6:0]$13131 $1\alu_trap0_trap_op__traptype$next[6:0]$13139 + attribute \src "issuer_ls180.v:179661.5-179661.29" + switch \initial + attribute \src "issuer_ls180.v:179661.9-179661.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:257" + switch \cu_issue_i + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { $1\alu_trap0_trap_op__trapaddr$next[12:0]$13138 $1\alu_trap0_trap_op__traptype$next[6:0]$13139 $1\alu_trap0_trap_op__is_32bit$next[0:0]$13136 $1\alu_trap0_trap_op__cia$next[63:0]$13132 $1\alu_trap0_trap_op__msr$next[63:0]$13137 $1\alu_trap0_trap_op__insn$next[31:0]$13134 $1\alu_trap0_trap_op__fn_unit$next[11:0]$13133 $1\alu_trap0_trap_op__insn_type$next[6:0]$13135 } { \oper_i_alu_trap0__trapaddr \oper_i_alu_trap0__traptype \oper_i_alu_trap0__is_32bit \oper_i_alu_trap0__cia \oper_i_alu_trap0__msr \oper_i_alu_trap0__insn \oper_i_alu_trap0__fn_unit \oper_i_alu_trap0__insn_type } + case + assign $1\alu_trap0_trap_op__cia$next[63:0]$13132 \alu_trap0_trap_op__cia + assign $1\alu_trap0_trap_op__fn_unit$next[11:0]$13133 \alu_trap0_trap_op__fn_unit + assign $1\alu_trap0_trap_op__insn$next[31:0]$13134 \alu_trap0_trap_op__insn + assign $1\alu_trap0_trap_op__insn_type$next[6:0]$13135 \alu_trap0_trap_op__insn_type + assign $1\alu_trap0_trap_op__is_32bit$next[0:0]$13136 \alu_trap0_trap_op__is_32bit + assign $1\alu_trap0_trap_op__msr$next[63:0]$13137 \alu_trap0_trap_op__msr + assign $1\alu_trap0_trap_op__trapaddr$next[12:0]$13138 \alu_trap0_trap_op__trapaddr + assign $1\alu_trap0_trap_op__traptype$next[6:0]$13139 \alu_trap0_trap_op__traptype + end + sync always + update \alu_trap0_trap_op__cia$next $0\alu_trap0_trap_op__cia$next[63:0]$13124 + update \alu_trap0_trap_op__fn_unit$next $0\alu_trap0_trap_op__fn_unit$next[11:0]$13125 + update \alu_trap0_trap_op__insn$next $0\alu_trap0_trap_op__insn$next[31:0]$13126 + update \alu_trap0_trap_op__insn_type$next $0\alu_trap0_trap_op__insn_type$next[6:0]$13127 + update \alu_trap0_trap_op__is_32bit$next $0\alu_trap0_trap_op__is_32bit$next[0:0]$13128 + update \alu_trap0_trap_op__msr$next $0\alu_trap0_trap_op__msr$next[63:0]$13129 + update \alu_trap0_trap_op__trapaddr$next $0\alu_trap0_trap_op__trapaddr$next[12:0]$13130 + update \alu_trap0_trap_op__traptype$next $0\alu_trap0_trap_op__traptype$next[6:0]$13131 + end + attribute \src "issuer_ls180.v:179677.3-179698.6" + process $proc$issuer_ls180.v:179677$13140 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\data_r0__o$next[63:0]$13141 $2\data_r0__o$next[63:0]$13145 + assign { } { } + assign $0\data_r0__o_ok$next[0:0]$13142 $3\data_r0__o_ok$next[0:0]$13147 + attribute \src "issuer_ls180.v:179678.5-179678.29" + switch \initial + attribute \src "issuer_ls180.v:179678.9-179678.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" + switch \alu_pulse + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $1\data_r0__o_ok$next[0:0]$13144 $1\data_r0__o$next[63:0]$13143 } { \o_ok \alu_trap0_o } + case + assign $1\data_r0__o$next[63:0]$13143 \data_r0__o + assign $1\data_r0__o_ok$next[0:0]$13144 \data_r0__o_ok + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" + switch \cu_issue_i + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $2\data_r0__o_ok$next[0:0]$13146 $2\data_r0__o$next[63:0]$13145 } 65'00000000000000000000000000000000000000000000000000000000000000000 + case + assign $2\data_r0__o$next[63:0]$13145 $1\data_r0__o$next[63:0]$13143 + assign $2\data_r0__o_ok$next[0:0]$13146 $1\data_r0__o_ok$next[0:0]$13144 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\data_r0__o_ok$next[0:0]$13147 1'0 + case + assign $3\data_r0__o_ok$next[0:0]$13147 $2\data_r0__o_ok$next[0:0]$13146 + end + sync always + update \data_r0__o$next $0\data_r0__o$next[63:0]$13141 + update \data_r0__o_ok$next $0\data_r0__o_ok$next[0:0]$13142 + end + attribute \src "issuer_ls180.v:179699.3-179720.6" + process $proc$issuer_ls180.v:179699$13148 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\data_r1__fast1$next[63:0]$13149 $2\data_r1__fast1$next[63:0]$13153 + assign { } { } + assign $0\data_r1__fast1_ok$next[0:0]$13150 $3\data_r1__fast1_ok$next[0:0]$13155 + attribute \src "issuer_ls180.v:179700.5-179700.29" + switch \initial + attribute \src "issuer_ls180.v:179700.9-179700.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" + switch \alu_pulse + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $1\data_r1__fast1_ok$next[0:0]$13152 $1\data_r1__fast1$next[63:0]$13151 } { \fast1_ok \alu_trap0_fast1 } + case + assign $1\data_r1__fast1$next[63:0]$13151 \data_r1__fast1 + assign $1\data_r1__fast1_ok$next[0:0]$13152 \data_r1__fast1_ok + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" + switch \cu_issue_i + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $2\data_r1__fast1_ok$next[0:0]$13154 $2\data_r1__fast1$next[63:0]$13153 } 65'00000000000000000000000000000000000000000000000000000000000000000 + case + assign $2\data_r1__fast1$next[63:0]$13153 $1\data_r1__fast1$next[63:0]$13151 + assign $2\data_r1__fast1_ok$next[0:0]$13154 $1\data_r1__fast1_ok$next[0:0]$13152 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\data_r1__fast1_ok$next[0:0]$13155 1'0 + case + assign $3\data_r1__fast1_ok$next[0:0]$13155 $2\data_r1__fast1_ok$next[0:0]$13154 + end + sync always + update \data_r1__fast1$next $0\data_r1__fast1$next[63:0]$13149 + update \data_r1__fast1_ok$next $0\data_r1__fast1_ok$next[0:0]$13150 + end + attribute \src "issuer_ls180.v:179721.3-179742.6" + process $proc$issuer_ls180.v:179721$13156 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\data_r2__fast2$next[63:0]$13157 $2\data_r2__fast2$next[63:0]$13161 + assign { } { } + assign $0\data_r2__fast2_ok$next[0:0]$13158 $3\data_r2__fast2_ok$next[0:0]$13163 + attribute \src "issuer_ls180.v:179722.5-179722.29" + switch \initial + attribute \src "issuer_ls180.v:179722.9-179722.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" + switch \alu_pulse + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $1\data_r2__fast2_ok$next[0:0]$13160 $1\data_r2__fast2$next[63:0]$13159 } { \fast2_ok \alu_trap0_fast2 } + case + assign $1\data_r2__fast2$next[63:0]$13159 \data_r2__fast2 + assign $1\data_r2__fast2_ok$next[0:0]$13160 \data_r2__fast2_ok + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" + switch \cu_issue_i + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $2\data_r2__fast2_ok$next[0:0]$13162 $2\data_r2__fast2$next[63:0]$13161 } 65'00000000000000000000000000000000000000000000000000000000000000000 + case + assign $2\data_r2__fast2$next[63:0]$13161 $1\data_r2__fast2$next[63:0]$13159 + assign $2\data_r2__fast2_ok$next[0:0]$13162 $1\data_r2__fast2_ok$next[0:0]$13160 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\data_r2__fast2_ok$next[0:0]$13163 1'0 + case + assign $3\data_r2__fast2_ok$next[0:0]$13163 $2\data_r2__fast2_ok$next[0:0]$13162 + end + sync always + update \data_r2__fast2$next $0\data_r2__fast2$next[63:0]$13157 + update \data_r2__fast2_ok$next $0\data_r2__fast2_ok$next[0:0]$13158 + end + attribute \src "issuer_ls180.v:179743.3-179764.6" + process $proc$issuer_ls180.v:179743$13164 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\data_r3__nia$next[63:0]$13165 $2\data_r3__nia$next[63:0]$13169 + assign { } { } + assign $0\data_r3__nia_ok$next[0:0]$13166 $3\data_r3__nia_ok$next[0:0]$13171 + attribute \src "issuer_ls180.v:179744.5-179744.29" + switch \initial + attribute \src "issuer_ls180.v:179744.9-179744.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" + switch \alu_pulse + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $1\data_r3__nia_ok$next[0:0]$13168 $1\data_r3__nia$next[63:0]$13167 } { \nia_ok \alu_trap0_nia } + case + assign $1\data_r3__nia$next[63:0]$13167 \data_r3__nia + assign $1\data_r3__nia_ok$next[0:0]$13168 \data_r3__nia_ok + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" + switch \cu_issue_i + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $2\data_r3__nia_ok$next[0:0]$13170 $2\data_r3__nia$next[63:0]$13169 } 65'00000000000000000000000000000000000000000000000000000000000000000 + case + assign $2\data_r3__nia$next[63:0]$13169 $1\data_r3__nia$next[63:0]$13167 + assign $2\data_r3__nia_ok$next[0:0]$13170 $1\data_r3__nia_ok$next[0:0]$13168 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\data_r3__nia_ok$next[0:0]$13171 1'0 + case + assign $3\data_r3__nia_ok$next[0:0]$13171 $2\data_r3__nia_ok$next[0:0]$13170 + end + sync always + update \data_r3__nia$next $0\data_r3__nia$next[63:0]$13165 + update \data_r3__nia_ok$next $0\data_r3__nia_ok$next[0:0]$13166 + end + attribute \src "issuer_ls180.v:179765.3-179786.6" + process $proc$issuer_ls180.v:179765$13172 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\data_r4__msr$next[63:0]$13173 $2\data_r4__msr$next[63:0]$13177 + assign { } { } + assign $0\data_r4__msr_ok$next[0:0]$13174 $3\data_r4__msr_ok$next[0:0]$13179 + attribute \src "issuer_ls180.v:179766.5-179766.29" + switch \initial + attribute \src "issuer_ls180.v:179766.9-179766.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" + switch \alu_pulse + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $1\data_r4__msr_ok$next[0:0]$13176 $1\data_r4__msr$next[63:0]$13175 } { \msr_ok \alu_trap0_msr } + case + assign $1\data_r4__msr$next[63:0]$13175 \data_r4__msr + assign $1\data_r4__msr_ok$next[0:0]$13176 \data_r4__msr_ok + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" + switch \cu_issue_i + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { $2\data_r4__msr_ok$next[0:0]$13178 $2\data_r4__msr$next[63:0]$13177 } 65'00000000000000000000000000000000000000000000000000000000000000000 + case + assign $2\data_r4__msr$next[63:0]$13177 $1\data_r4__msr$next[63:0]$13175 + assign $2\data_r4__msr_ok$next[0:0]$13178 $1\data_r4__msr_ok$next[0:0]$13176 + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $3\data_r4__msr_ok$next[0:0]$13179 1'0 + case + assign $3\data_r4__msr_ok$next[0:0]$13179 $2\data_r4__msr_ok$next[0:0]$13178 + end + sync always + update \data_r4__msr$next $0\data_r4__msr$next[63:0]$13173 + update \data_r4__msr_ok$next $0\data_r4__msr_ok$next[0:0]$13174 + end + attribute \src "issuer_ls180.v:179787.3-179796.6" + process $proc$issuer_ls180.v:179787$13180 + assign { } { } + assign { } { } + assign $0\src_r0$next[63:0]$13181 $1\src_r0$next[63:0]$13182 + attribute \src "issuer_ls180.v:179788.5-179788.29" + switch \initial + attribute \src "issuer_ls180.v:179788.9-179788.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" + switch \src_l_q_src [0] + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\src_r0$next[63:0]$13182 \src1_i + case + assign $1\src_r0$next[63:0]$13182 \src_r0 + end + sync always + update \src_r0$next $0\src_r0$next[63:0]$13181 + end + attribute \src "issuer_ls180.v:179797.3-179806.6" + process $proc$issuer_ls180.v:179797$13183 + assign { } { } + assign { } { } + assign $0\src_r1$next[63:0]$13184 $1\src_r1$next[63:0]$13185 + attribute \src "issuer_ls180.v:179798.5-179798.29" + switch \initial + attribute \src "issuer_ls180.v:179798.9-179798.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" + switch \src_l_q_src [1] + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\src_r1$next[63:0]$13185 \src2_i + case + assign $1\src_r1$next[63:0]$13185 \src_r1 + end + sync always + update \src_r1$next $0\src_r1$next[63:0]$13184 + end + attribute \src "issuer_ls180.v:179807.3-179816.6" + process $proc$issuer_ls180.v:179807$13186 + assign { } { } + assign { } { } + assign $0\src_r2$next[63:0]$13187 $1\src_r2$next[63:0]$13188 + attribute \src "issuer_ls180.v:179808.5-179808.29" + switch \initial + attribute \src "issuer_ls180.v:179808.9-179808.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" + switch \src_l_q_src [2] + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\src_r2$next[63:0]$13188 \src3_i + case + assign $1\src_r2$next[63:0]$13188 \src_r2 + end + sync always + update \src_r2$next $0\src_r2$next[63:0]$13187 + end + attribute \src "issuer_ls180.v:179817.3-179826.6" + process $proc$issuer_ls180.v:179817$13189 + assign { } { } + assign { } { } + assign $0\src_r3$next[63:0]$13190 $1\src_r3$next[63:0]$13191 + attribute \src "issuer_ls180.v:179818.5-179818.29" + switch \initial + attribute \src "issuer_ls180.v:179818.9-179818.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" + switch \src_l_q_src [3] + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\src_r3$next[63:0]$13191 \src4_i + case + assign $1\src_r3$next[63:0]$13191 \src_r3 + end + sync always + update \src_r3$next $0\src_r3$next[63:0]$13190 + end + attribute \src "issuer_ls180.v:179827.3-179835.6" + process $proc$issuer_ls180.v:179827$13192 + assign { } { } + assign { } { } + assign $0\alui_l_r_alui$next[0:0]$13193 $1\alui_l_r_alui$next[0:0]$13194 + attribute \src "issuer_ls180.v:179828.5-179828.29" + switch \initial + attribute \src "issuer_ls180.v:179828.9-179828.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\alui_l_r_alui$next[0:0]$13194 1'1 + case + assign $1\alui_l_r_alui$next[0:0]$13194 \$89 + end + sync always + update \alui_l_r_alui$next $0\alui_l_r_alui$next[0:0]$13193 + end + attribute \src "issuer_ls180.v:179836.3-179844.6" + process $proc$issuer_ls180.v:179836$13195 + assign { } { } + assign { } { } + assign $0\alu_l_r_alu$next[0:0]$13196 $1\alu_l_r_alu$next[0:0]$13197 + attribute \src "issuer_ls180.v:179837.5-179837.29" + switch \initial + attribute \src "issuer_ls180.v:179837.9-179837.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\alu_l_r_alu$next[0:0]$13197 1'1 + case + assign $1\alu_l_r_alu$next[0:0]$13197 \$91 + end + sync always + update \alu_l_r_alu$next $0\alu_l_r_alu$next[0:0]$13196 + end + attribute \src "issuer_ls180.v:179845.3-179854.6" + process $proc$issuer_ls180.v:179845$13198 + assign { } { } + assign { } { } + assign $0\dest1_o[63:0] $1\dest1_o[63:0] + attribute \src "issuer_ls180.v:179846.5-179846.29" + switch \initial + attribute \src "issuer_ls180.v:179846.9-179846.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" + switch \$115 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dest1_o[63:0] \data_r0__o + case + assign $1\dest1_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \dest1_o $0\dest1_o[63:0] + end + attribute \src "issuer_ls180.v:179855.3-179864.6" + process $proc$issuer_ls180.v:179855$13199 + assign { } { } + assign { } { } + assign $0\dest2_o[63:0] $1\dest2_o[63:0] + attribute \src "issuer_ls180.v:179856.5-179856.29" + switch \initial + attribute \src "issuer_ls180.v:179856.9-179856.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" + switch \$117 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dest2_o[63:0] \data_r1__fast1 + case + assign $1\dest2_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \dest2_o $0\dest2_o[63:0] + end + attribute \src "issuer_ls180.v:179865.3-179874.6" + process $proc$issuer_ls180.v:179865$13200 + assign { } { } + assign { } { } + assign $0\dest3_o[63:0] $1\dest3_o[63:0] + attribute \src "issuer_ls180.v:179866.5-179866.29" + switch \initial + attribute \src "issuer_ls180.v:179866.9-179866.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" + switch \$119 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dest3_o[63:0] \data_r2__fast2 + case + assign $1\dest3_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \dest3_o $0\dest3_o[63:0] + end + attribute \src "issuer_ls180.v:179875.3-179884.6" + process $proc$issuer_ls180.v:179875$13201 + assign { } { } + assign { } { } + assign $0\dest4_o[63:0] $1\dest4_o[63:0] + attribute \src "issuer_ls180.v:179876.5-179876.29" + switch \initial + attribute \src "issuer_ls180.v:179876.9-179876.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" + switch \$121 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dest4_o[63:0] \data_r3__nia + case + assign $1\dest4_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \dest4_o $0\dest4_o[63:0] + end + attribute \src "issuer_ls180.v:179885.3-179894.6" + process $proc$issuer_ls180.v:179885$13202 + assign { } { } + assign { } { } + assign $0\dest5_o[63:0] $1\dest5_o[63:0] + attribute \src "issuer_ls180.v:179886.5-179886.29" + switch \initial + attribute \src "issuer_ls180.v:179886.9-179886.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" + switch \$123 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\dest5_o[63:0] \data_r4__msr + case + assign $1\dest5_o[63:0] 64'0000000000000000000000000000000000000000000000000000000000000000 + end + sync always + update \dest5_o $0\dest5_o[63:0] + end + attribute \src "issuer_ls180.v:179895.3-179903.6" + process $proc$issuer_ls180.v:179895$13203 + assign { } { } + assign { } { } + assign $0\prev_wr_go$next[4:0]$13204 $1\prev_wr_go$next[4:0]$13205 + attribute \src "issuer_ls180.v:179896.5-179896.29" + switch \initial + attribute \src "issuer_ls180.v:179896.9-179896.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\prev_wr_go$next[4:0]$13205 5'00000 + case + assign $1\prev_wr_go$next[4:0]$13205 \$21 + end + sync always + update \prev_wr_go$next $0\prev_wr_go$next[4:0]$13204 + end + connect \$5 $reduce_and$issuer_ls180.v:179347$12994_Y + connect \$99 $and$issuer_ls180.v:179348$12995_Y + connect \$101 $and$issuer_ls180.v:179349$12996_Y + connect \$103 $and$issuer_ls180.v:179350$12997_Y + connect \$105 $and$issuer_ls180.v:179351$12998_Y + connect \$107 $and$issuer_ls180.v:179352$12999_Y + connect \$109 $and$issuer_ls180.v:179353$13000_Y + connect \$111 $and$issuer_ls180.v:179354$13001_Y + connect \$113 $and$issuer_ls180.v:179355$13002_Y + connect \$115 $and$issuer_ls180.v:179356$13003_Y + connect \$117 $and$issuer_ls180.v:179357$13004_Y + connect \$11 $and$issuer_ls180.v:179358$13005_Y + connect \$119 $and$issuer_ls180.v:179359$13006_Y + connect \$121 $and$issuer_ls180.v:179360$13007_Y + connect \$123 $and$issuer_ls180.v:179361$13008_Y + connect \$13 $not$issuer_ls180.v:179362$13009_Y + connect \$15 $and$issuer_ls180.v:179363$13010_Y + connect \$17 $not$issuer_ls180.v:179364$13011_Y + connect \$19 $and$issuer_ls180.v:179365$13012_Y + connect \$21 $and$issuer_ls180.v:179366$13013_Y + connect \$25 $not$issuer_ls180.v:179367$13014_Y + connect \$27 $and$issuer_ls180.v:179368$13015_Y + connect \$24 $reduce_or$issuer_ls180.v:179369$13016_Y + connect \$23 $not$issuer_ls180.v:179370$13017_Y + connect \$31 $and$issuer_ls180.v:179371$13018_Y + connect \$33 $reduce_or$issuer_ls180.v:179372$13019_Y + connect \$35 $reduce_or$issuer_ls180.v:179373$13020_Y + connect \$37 $or$issuer_ls180.v:179374$13021_Y + connect \$3 $and$issuer_ls180.v:179375$13022_Y + connect \$39 $not$issuer_ls180.v:179376$13023_Y + connect \$41 $and$issuer_ls180.v:179377$13024_Y + connect \$43 $and$issuer_ls180.v:179378$13025_Y + connect \$45 $eq$issuer_ls180.v:179379$13026_Y + connect \$47 $and$issuer_ls180.v:179380$13027_Y + connect \$49 $eq$issuer_ls180.v:179381$13028_Y + connect \$51 $and$issuer_ls180.v:179382$13029_Y + connect \$53 $and$issuer_ls180.v:179383$13030_Y + connect \$55 $and$issuer_ls180.v:179384$13031_Y + connect \$57 $or$issuer_ls180.v:179385$13032_Y + connect \$59 $or$issuer_ls180.v:179386$13033_Y + connect \$61 $or$issuer_ls180.v:179387$13034_Y + connect \$63 $or$issuer_ls180.v:179388$13035_Y + connect \$65 $and$issuer_ls180.v:179389$13036_Y + connect \$67 $and$issuer_ls180.v:179390$13037_Y + connect \$6 $not$issuer_ls180.v:179391$13038_Y + connect \$69 $or$issuer_ls180.v:179392$13039_Y + connect \$71 $and$issuer_ls180.v:179393$13040_Y + connect \$73 $and$issuer_ls180.v:179394$13041_Y + connect \$75 $and$issuer_ls180.v:179395$13042_Y + connect \$77 $and$issuer_ls180.v:179396$13043_Y + connect \$79 $and$issuer_ls180.v:179397$13044_Y + connect \$81 $ternary$issuer_ls180.v:179398$13045_Y + connect \$83 $ternary$issuer_ls180.v:179399$13046_Y + connect \$85 $ternary$issuer_ls180.v:179400$13047_Y + connect \$87 $ternary$issuer_ls180.v:179401$13048_Y + connect \$8 $or$issuer_ls180.v:179402$13049_Y + connect \$89 $and$issuer_ls180.v:179403$13050_Y + connect \$91 $and$issuer_ls180.v:179404$13051_Y + connect \$93 $and$issuer_ls180.v:179405$13052_Y + connect \$95 $and$issuer_ls180.v:179406$13053_Y + connect \$97 $not$issuer_ls180.v:179407$13054_Y + connect \cu_go_die_i 1'0 + connect \cu_shadown_i 1'1 + connect \cu_wr__rel_o \$113 + connect \cu_rd__rel_o \$99 + connect \cu_busy_o \opc_l_q_opc + connect \alu_l_s_alu \all_rd_pulse + connect \alu_trap0_n_ready_i \alu_l_q_alu + connect \alui_l_s_alui \all_rd_pulse + connect \alu_trap0_p_valid_i \alui_l_q_alui + connect \alu_trap0_fast2$2 \$87 + connect \alu_trap0_fast1$1 \$85 + connect \alu_trap0_rb \$83 + connect \alu_trap0_ra \$81 + connect \cu_wrmask_o { \$79 \$77 \$75 \$73 \$71 } + connect \reset_r \$63 + connect \reset_w \$61 + connect \rst_r \$59 + connect \reset \$57 + connect \wr_any \$37 + connect \cu_done_o \$31 + connect \alu_pulsem { \alu_pulse \alu_pulse \alu_pulse \alu_pulse \alu_pulse } + connect \alu_pulse \alu_done_rise + connect \alu_done_rise \$19 + connect \alu_done_dly$next \alu_done + connect \alu_done \alu_trap0_n_valid_o + connect \all_rd_pulse \all_rd_rise + connect \all_rd_rise \$15 + connect \all_rd_dly$next \all_rd + connect \all_rd \$11 +end +attribute \src "issuer_ls180.v:179937.1-179995.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.fus.ldst0.upd_l" +attribute \generator "nMigen" +module \upd_l + attribute \src "issuer_ls180.v:179938.7-179938.20" + wire $0\initial[0:0] + attribute \src "issuer_ls180.v:179983.3-179991.6" + wire $0\q_int$next[0:0]$13254 + attribute \src "issuer_ls180.v:179981.3-179982.27" + wire $0\q_int[0:0] + attribute \src "issuer_ls180.v:179983.3-179991.6" + wire $1\q_int$next[0:0]$13255 + attribute \src "issuer_ls180.v:179960.7-179960.19" + wire $1\q_int[0:0] + attribute \src "issuer_ls180.v:179973.17-179973.96" + wire $and$issuer_ls180.v:179973$13244_Y + attribute \src "issuer_ls180.v:179978.17-179978.96" + wire $and$issuer_ls180.v:179978$13249_Y + attribute \src "issuer_ls180.v:179975.18-179975.93" + wire $not$issuer_ls180.v:179975$13246_Y + attribute \src "issuer_ls180.v:179977.17-179977.92" + wire $not$issuer_ls180.v:179977$13248_Y + attribute \src "issuer_ls180.v:179980.17-179980.92" + wire $not$issuer_ls180.v:179980$13251_Y + attribute \src "issuer_ls180.v:179974.18-179974.98" + wire $or$issuer_ls180.v:179974$13245_Y + attribute \src "issuer_ls180.v:179976.18-179976.99" + wire $or$issuer_ls180.v:179976$13247_Y + attribute \src "issuer_ls180.v:179979.17-179979.97" + wire $or$issuer_ls180.v:179979$13250_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire \$13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" + wire input 5 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" + wire input 1 \coresync_rst + attribute \src "issuer_ls180.v:179938.7-179938.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire output 4 \q_upd + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" + wire \qlq_upd + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + wire \qn_upd + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire input 3 \r_upd + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire input 2 \s_upd + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $and $and$issuer_ls180.v:179973$13244 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$7 + connect \Y $and$issuer_ls180.v:179973$13244_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $and $and$issuer_ls180.v:179978$13249 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$1 + connect \Y $and$issuer_ls180.v:179978$13249_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + cell $not $not$issuer_ls180.v:179975$13246 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_upd + connect \Y $not$issuer_ls180.v:179975$13246_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $not $not$issuer_ls180.v:179977$13248 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_upd + connect \Y $not$issuer_ls180.v:179977$13248_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $not $not$issuer_ls180.v:179980$13251 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_upd + connect \Y $not$issuer_ls180.v:179980$13251_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $or $or$issuer_ls180.v:179974$13245 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$9 + connect \B \s_upd + connect \Y $or$issuer_ls180.v:179974$13245_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + cell $or $or$issuer_ls180.v:179976$13247 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_upd + connect \B \q_int + connect \Y $or$issuer_ls180.v:179976$13247_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $or $or$issuer_ls180.v:179979$13250 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$3 + connect \B \s_upd + connect \Y $or$issuer_ls180.v:179979$13250_Y + end + attribute \src "issuer_ls180.v:179938.7-179938.20" + process $proc$issuer_ls180.v:179938$13256 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "issuer_ls180.v:179960.7-179960.19" + process $proc$issuer_ls180.v:179960$13257 + assign { } { } + assign $1\q_int[0:0] 1'0 + sync always + sync init + update \q_int $1\q_int[0:0] + end + attribute \src "issuer_ls180.v:179981.3-179982.27" + process $proc$issuer_ls180.v:179981$13252 + assign { } { } + assign $0\q_int[0:0] \q_int$next + sync posedge \coresync_clk + update \q_int $0\q_int[0:0] + end + attribute \src "issuer_ls180.v:179983.3-179991.6" + process $proc$issuer_ls180.v:179983$13253 + assign { } { } + assign { } { } + assign $0\q_int$next[0:0]$13254 $1\q_int$next[0:0]$13255 + attribute \src "issuer_ls180.v:179984.5-179984.29" + switch \initial + attribute \src "issuer_ls180.v:179984.9-179984.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\q_int$next[0:0]$13255 1'0 + case + assign $1\q_int$next[0:0]$13255 \$5 + end + sync always + update \q_int$next $0\q_int$next[0:0]$13254 + end + connect \$9 $and$issuer_ls180.v:179973$13244_Y + connect \$11 $or$issuer_ls180.v:179974$13245_Y + connect \$13 $not$issuer_ls180.v:179975$13246_Y + connect \$15 $or$issuer_ls180.v:179976$13247_Y + connect \$1 $not$issuer_ls180.v:179977$13248_Y + connect \$3 $and$issuer_ls180.v:179978$13249_Y + connect \$5 $or$issuer_ls180.v:179979$13250_Y + connect \$7 $not$issuer_ls180.v:179980$13251_Y + connect \qlq_upd \$15 + connect \qn_upd \$13 + connect \q_upd \$11 +end +attribute \src "issuer_ls180.v:179999.1-180057.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.l0.pimem.valid_l" +attribute \generator "nMigen" +module \valid_l + attribute \src "issuer_ls180.v:180000.7-180000.20" + wire $0\initial[0:0] + attribute \src "issuer_ls180.v:180045.3-180053.6" + wire $0\q_int$next[0:0]$13268 + attribute \src "issuer_ls180.v:180043.3-180044.27" + wire $0\q_int[0:0] + attribute \src "issuer_ls180.v:180045.3-180053.6" + wire $1\q_int$next[0:0]$13269 + attribute \src "issuer_ls180.v:180022.7-180022.19" + wire $1\q_int[0:0] + attribute \src "issuer_ls180.v:180035.17-180035.96" + wire $and$issuer_ls180.v:180035$13258_Y + attribute \src "issuer_ls180.v:180040.17-180040.96" + wire $and$issuer_ls180.v:180040$13263_Y + attribute \src "issuer_ls180.v:180037.18-180037.95" + wire $not$issuer_ls180.v:180037$13260_Y + attribute \src "issuer_ls180.v:180039.17-180039.94" + wire $not$issuer_ls180.v:180039$13262_Y + attribute \src "issuer_ls180.v:180042.17-180042.94" + wire $not$issuer_ls180.v:180042$13265_Y + attribute \src "issuer_ls180.v:180036.18-180036.100" + wire $or$issuer_ls180.v:180036$13259_Y + attribute \src "issuer_ls180.v:180038.18-180038.101" + wire $or$issuer_ls180.v:180038$13261_Y + attribute \src "issuer_ls180.v:180041.17-180041.99" + wire $or$issuer_ls180.v:180041$13264_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire \$13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" + wire input 5 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" + wire input 1 \coresync_rst + attribute \src "issuer_ls180.v:180000.7-180000.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire output 3 \q_valid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" + wire \qlq_valid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + wire \qn_valid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire input 4 \r_valid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire input 2 \s_valid + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $and $and$issuer_ls180.v:180035$13258 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$7 + connect \Y $and$issuer_ls180.v:180035$13258_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $and $and$issuer_ls180.v:180040$13263 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$1 + connect \Y $and$issuer_ls180.v:180040$13263_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + cell $not $not$issuer_ls180.v:180037$13260 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_valid + connect \Y $not$issuer_ls180.v:180037$13260_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $not $not$issuer_ls180.v:180039$13262 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_valid + connect \Y $not$issuer_ls180.v:180039$13262_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $not $not$issuer_ls180.v:180042$13265 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_valid + connect \Y $not$issuer_ls180.v:180042$13265_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $or $or$issuer_ls180.v:180036$13259 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$9 + connect \B \s_valid + connect \Y $or$issuer_ls180.v:180036$13259_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + cell $or $or$issuer_ls180.v:180038$13261 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_valid + connect \B \q_int + connect \Y $or$issuer_ls180.v:180038$13261_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $or $or$issuer_ls180.v:180041$13264 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$3 + connect \B \s_valid + connect \Y $or$issuer_ls180.v:180041$13264_Y + end + attribute \src "issuer_ls180.v:180000.7-180000.20" + process $proc$issuer_ls180.v:180000$13270 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "issuer_ls180.v:180022.7-180022.19" + process $proc$issuer_ls180.v:180022$13271 + assign { } { } + assign $1\q_int[0:0] 1'0 + sync always + sync init + update \q_int $1\q_int[0:0] + end + attribute \src "issuer_ls180.v:180043.3-180044.27" + process $proc$issuer_ls180.v:180043$13266 + assign { } { } + assign $0\q_int[0:0] \q_int$next + sync posedge \coresync_clk + update \q_int $0\q_int[0:0] + end + attribute \src "issuer_ls180.v:180045.3-180053.6" + process $proc$issuer_ls180.v:180045$13267 + assign { } { } + assign { } { } + assign $0\q_int$next[0:0]$13268 $1\q_int$next[0:0]$13269 + attribute \src "issuer_ls180.v:180046.5-180046.29" + switch \initial + attribute \src "issuer_ls180.v:180046.9-180046.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\q_int$next[0:0]$13269 1'0 + case + assign $1\q_int$next[0:0]$13269 \$5 + end + sync always + update \q_int$next $0\q_int$next[0:0]$13268 + end + connect \$9 $and$issuer_ls180.v:180035$13258_Y + connect \$11 $or$issuer_ls180.v:180036$13259_Y + connect \$13 $not$issuer_ls180.v:180037$13260_Y + connect \$15 $or$issuer_ls180.v:180038$13261_Y + connect \$1 $not$issuer_ls180.v:180039$13262_Y + connect \$3 $and$issuer_ls180.v:180040$13263_Y + connect \$5 $or$issuer_ls180.v:180041$13264_Y + connect \$7 $not$issuer_ls180.v:180042$13265_Y + connect \qlq_valid \$15 + connect \qn_valid \$13 + connect \q_valid \$11 +end +attribute \src "issuer_ls180.v:180061.1-180119.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.fus.ldst0.wri_l" +attribute \generator "nMigen" +module \wri_l + attribute \src "issuer_ls180.v:180062.7-180062.20" + wire $0\initial[0:0] + attribute \src "issuer_ls180.v:180107.3-180115.6" + wire $0\q_int$next[0:0]$13282 + attribute \src "issuer_ls180.v:180105.3-180106.27" + wire $0\q_int[0:0] + attribute \src "issuer_ls180.v:180107.3-180115.6" + wire $1\q_int$next[0:0]$13283 + attribute \src "issuer_ls180.v:180084.7-180084.19" + wire $1\q_int[0:0] + attribute \src "issuer_ls180.v:180097.17-180097.96" + wire $and$issuer_ls180.v:180097$13272_Y + attribute \src "issuer_ls180.v:180102.17-180102.96" + wire $and$issuer_ls180.v:180102$13277_Y + attribute \src "issuer_ls180.v:180099.18-180099.93" + wire $not$issuer_ls180.v:180099$13274_Y + attribute \src "issuer_ls180.v:180101.17-180101.92" + wire $not$issuer_ls180.v:180101$13276_Y + attribute \src "issuer_ls180.v:180104.17-180104.92" + wire $not$issuer_ls180.v:180104$13279_Y + attribute \src "issuer_ls180.v:180098.18-180098.98" + wire $or$issuer_ls180.v:180098$13273_Y + attribute \src "issuer_ls180.v:180100.18-180100.99" + wire $or$issuer_ls180.v:180100$13275_Y + attribute \src "issuer_ls180.v:180103.17-180103.97" + wire $or$issuer_ls180.v:180103$13278_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + wire \$13 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + wire \$5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + wire \$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" + wire input 5 \coresync_clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:141" + wire input 1 \coresync_rst + attribute \src "issuer_ls180.v:180062.7-180062.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \q_int + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" + wire \q_int$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" + wire output 4 \q_wri + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" + wire \qlq_wri + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" + wire \qn_wri + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" + wire input 3 \r_wri + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" + wire input 2 \s_wri + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $and $and$issuer_ls180.v:180097$13272 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$7 + connect \Y $and$issuer_ls180.v:180097$13272_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $and $and$issuer_ls180.v:180102$13277 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_int + connect \B \$1 + connect \Y $and$issuer_ls180.v:180102$13277_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" + cell $not $not$issuer_ls180.v:180099$13274 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_wri + connect \Y $not$issuer_ls180.v:180099$13274_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $not $not$issuer_ls180.v:180101$13276 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_wri + connect \Y $not$issuer_ls180.v:180101$13276_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $not $not$issuer_ls180.v:180104$13279 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \r_wri + connect \Y $not$issuer_ls180.v:180104$13279_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" + cell $or $or$issuer_ls180.v:180098$13273 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$9 + connect \B \s_wri + connect \Y $or$issuer_ls180.v:180098$13273_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" + cell $or $or$issuer_ls180.v:180100$13275 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \q_wri + connect \B \q_int + connect \Y $or$issuer_ls180.v:180100$13275_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" + cell $or $or$issuer_ls180.v:180103$13278 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$3 + connect \B \s_wri + connect \Y $or$issuer_ls180.v:180103$13278_Y + end + attribute \src "issuer_ls180.v:180062.7-180062.20" + process $proc$issuer_ls180.v:180062$13284 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "issuer_ls180.v:180084.7-180084.19" + process $proc$issuer_ls180.v:180084$13285 + assign { } { } + assign $1\q_int[0:0] 1'0 + sync always + sync init + update \q_int $1\q_int[0:0] + end + attribute \src "issuer_ls180.v:180105.3-180106.27" + process $proc$issuer_ls180.v:180105$13280 + assign { } { } + assign $0\q_int[0:0] \q_int$next + sync posedge \coresync_clk + update \q_int $0\q_int[0:0] + end + attribute \src "issuer_ls180.v:180107.3-180115.6" + process $proc$issuer_ls180.v:180107$13281 + assign { } { } + assign { } { } + assign $0\q_int$next[0:0]$13282 $1\q_int$next[0:0]$13283 + attribute \src "issuer_ls180.v:180108.5-180108.29" + switch \initial + attribute \src "issuer_ls180.v:180108.9-180108.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\q_int$next[0:0]$13283 1'0 + case + assign $1\q_int$next[0:0]$13283 \$5 + end + sync always + update \q_int$next $0\q_int$next[0:0]$13282 + end + connect \$9 $and$issuer_ls180.v:180097$13272_Y + connect \$11 $or$issuer_ls180.v:180098$13273_Y + connect \$13 $not$issuer_ls180.v:180099$13274_Y + connect \$15 $or$issuer_ls180.v:180100$13275_Y + connect \$1 $not$issuer_ls180.v:180101$13276_Y + connect \$3 $and$issuer_ls180.v:180102$13277_Y + connect \$5 $or$issuer_ls180.v:180103$13278_Y + connect \$7 $not$issuer_ls180.v:180104$13279_Y + connect \qlq_wri \$15 + connect \qn_wri \$13 + connect \q_wri \$11 +end +attribute \src "issuer_ls180.v:180123.1-180189.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.wrpick_CR_cr_a" +attribute \generator "nMigen" +module \wrpick_CR_cr_a + attribute \src "issuer_ls180.v:180168.17-180168.91" + wire $not$issuer_ls180.v:180168$13286_Y + attribute \src "issuer_ls180.v:180170.18-180170.93" + wire $not$issuer_ls180.v:180170$13288_Y + attribute \src "issuer_ls180.v:180172.18-180172.93" + wire $not$issuer_ls180.v:180172$13290_Y + attribute \src "issuer_ls180.v:180173.17-180173.89" + wire width 6 $not$issuer_ls180.v:180173$13291_Y + attribute \src "issuer_ls180.v:180175.18-180175.93" + wire $not$issuer_ls180.v:180175$13293_Y + attribute \src "issuer_ls180.v:180178.17-180178.91" + wire $not$issuer_ls180.v:180178$13296_Y + attribute \src "issuer_ls180.v:180169.18-180169.106" + wire $reduce_or$issuer_ls180.v:180169$13287_Y + attribute \src "issuer_ls180.v:180171.18-180171.106" + wire $reduce_or$issuer_ls180.v:180171$13289_Y + attribute \src "issuer_ls180.v:180174.18-180174.106" + wire $reduce_or$issuer_ls180.v:180174$13292_Y + attribute \src "issuer_ls180.v:180176.18-180176.90" + wire $reduce_or$issuer_ls180.v:180176$13294_Y + attribute \src "issuer_ls180.v:180177.17-180177.103" + wire $reduce_or$issuer_ls180.v:180177$13295_Y + attribute \src "issuer_ls180.v:180179.17-180179.105" + wire $reduce_or$issuer_ls180.v:180179$13297_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" + wire width 6 \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$12 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$16 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$19 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$20 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" + wire \$23 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$4 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$8 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" + wire output 2 \en_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" + wire width 6 input 3 \i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:49" + wire width 6 \ni + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" + wire width 6 output 1 \o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t0 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t2 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t4 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$issuer_ls180.v:180168$13286 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$8 + connect \Y $not$issuer_ls180.v:180168$13286_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$issuer_ls180.v:180170$13288 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$12 + connect \Y $not$issuer_ls180.v:180170$13288_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$issuer_ls180.v:180172$13290 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$16 + connect \Y $not$issuer_ls180.v:180172$13290_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" + cell $not $not$issuer_ls180.v:180173$13291 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \Y_WIDTH 6 + connect \A \i + connect \Y $not$issuer_ls180.v:180173$13291_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$issuer_ls180.v:180175$13293 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$20 + connect \Y $not$issuer_ls180.v:180175$13293_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$issuer_ls180.v:180178$13296 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$4 + connect \Y $not$issuer_ls180.v:180178$13296_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$issuer_ls180.v:180169$13287 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A { \i [2:0] \ni [3] } + connect \Y $reduce_or$issuer_ls180.v:180169$13287_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$issuer_ls180.v:180171$13289 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A { \i [3:0] \ni [4] } + connect \Y $reduce_or$issuer_ls180.v:180171$13289_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$issuer_ls180.v:180174$13292 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A { \i [4:0] \ni [5] } + connect \Y $reduce_or$issuer_ls180.v:180174$13292_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" + cell $reduce_or $reduce_or$issuer_ls180.v:180176$13294 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A \o + connect \Y $reduce_or$issuer_ls180.v:180176$13294_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$issuer_ls180.v:180177$13295 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A { \i [0] \ni [1] } + connect \Y $reduce_or$issuer_ls180.v:180177$13295_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$issuer_ls180.v:180179$13297 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A { \i [1:0] \ni [2] } + connect \Y $reduce_or$issuer_ls180.v:180179$13297_Y + end + connect \$7 $not$issuer_ls180.v:180168$13286_Y + connect \$12 $reduce_or$issuer_ls180.v:180169$13287_Y + connect \$11 $not$issuer_ls180.v:180170$13288_Y + connect \$16 $reduce_or$issuer_ls180.v:180171$13289_Y + connect \$15 $not$issuer_ls180.v:180172$13290_Y + connect \$1 $not$issuer_ls180.v:180173$13291_Y + connect \$20 $reduce_or$issuer_ls180.v:180174$13292_Y + connect \$19 $not$issuer_ls180.v:180175$13293_Y + connect \$23 $reduce_or$issuer_ls180.v:180176$13294_Y + connect \$4 $reduce_or$issuer_ls180.v:180177$13295_Y + connect \$3 $not$issuer_ls180.v:180178$13296_Y + connect \$8 $reduce_or$issuer_ls180.v:180179$13297_Y + connect \en_o \$23 + connect \o { \t5 \t4 \t3 \t2 \t1 \t0 } + connect \t5 \$19 + connect \t4 \$15 + connect \t3 \$11 + connect \t2 \$7 + connect \t1 \$3 + connect \t0 \i [0] + connect \ni \$1 +end +attribute \src "issuer_ls180.v:180193.1-180214.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.wrpick_CR_full_cr" +attribute \generator "nMigen" +module \wrpick_CR_full_cr + attribute \src "issuer_ls180.v:180208.17-180208.89" + wire $not$issuer_ls180.v:180208$13298_Y + attribute \src "issuer_ls180.v:180209.17-180209.89" + wire $reduce_or$issuer_ls180.v:180209$13299_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" + wire output 2 \en_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" + wire input 3 \i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:49" + wire \ni + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" + wire output 1 \o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t0 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" + cell $not $not$issuer_ls180.v:180208$13298 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \i + connect \Y $not$issuer_ls180.v:180208$13298_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" + cell $reduce_or $reduce_or$issuer_ls180.v:180209$13299 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \o + connect \Y $reduce_or$issuer_ls180.v:180209$13299_Y + end + connect \$1 $not$issuer_ls180.v:180208$13298_Y + connect \$3 $reduce_or$issuer_ls180.v:180209$13299_Y + connect \en_o \$3 + connect \o \t0 + connect \t0 \i + connect \ni \$1 +end +attribute \src "issuer_ls180.v:180218.1-180275.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.wrpick_FAST_fast1" +attribute \generator "nMigen" +module \wrpick_FAST_fast1 + attribute \src "issuer_ls180.v:180257.17-180257.91" + wire $not$issuer_ls180.v:180257$13300_Y + attribute \src "issuer_ls180.v:180259.18-180259.93" + wire $not$issuer_ls180.v:180259$13302_Y + attribute \src "issuer_ls180.v:180261.18-180261.93" + wire $not$issuer_ls180.v:180261$13304_Y + attribute \src "issuer_ls180.v:180262.17-180262.89" + wire width 5 $not$issuer_ls180.v:180262$13305_Y + attribute \src "issuer_ls180.v:180265.17-180265.91" + wire $not$issuer_ls180.v:180265$13308_Y + attribute \src "issuer_ls180.v:180258.18-180258.106" + wire $reduce_or$issuer_ls180.v:180258$13301_Y + attribute \src "issuer_ls180.v:180260.18-180260.106" + wire $reduce_or$issuer_ls180.v:180260$13303_Y + attribute \src "issuer_ls180.v:180263.18-180263.90" + wire $reduce_or$issuer_ls180.v:180263$13306_Y + attribute \src "issuer_ls180.v:180264.17-180264.103" + wire $reduce_or$issuer_ls180.v:180264$13307_Y + attribute \src "issuer_ls180.v:180266.17-180266.105" + wire $reduce_or$issuer_ls180.v:180266$13309_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" + wire width 5 \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$12 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$16 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" + wire \$19 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$4 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$8 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" + wire output 2 \en_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" + wire width 5 input 3 \i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:49" + wire width 5 \ni + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" + wire width 5 output 1 \o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t0 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t2 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t4 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$issuer_ls180.v:180257$13300 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$8 + connect \Y $not$issuer_ls180.v:180257$13300_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$issuer_ls180.v:180259$13302 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$12 + connect \Y $not$issuer_ls180.v:180259$13302_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$issuer_ls180.v:180261$13304 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$16 + connect \Y $not$issuer_ls180.v:180261$13304_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" + cell $not $not$issuer_ls180.v:180262$13305 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \Y_WIDTH 5 + connect \A \i + connect \Y $not$issuer_ls180.v:180262$13305_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$issuer_ls180.v:180265$13308 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$4 + connect \Y $not$issuer_ls180.v:180265$13308_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$issuer_ls180.v:180258$13301 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A { \i [2:0] \ni [3] } + connect \Y $reduce_or$issuer_ls180.v:180258$13301_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$issuer_ls180.v:180260$13303 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A { \i [3:0] \ni [4] } + connect \Y $reduce_or$issuer_ls180.v:180260$13303_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" + cell $reduce_or $reduce_or$issuer_ls180.v:180263$13306 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A \o + connect \Y $reduce_or$issuer_ls180.v:180263$13306_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$issuer_ls180.v:180264$13307 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A { \i [0] \ni [1] } + connect \Y $reduce_or$issuer_ls180.v:180264$13307_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$issuer_ls180.v:180266$13309 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A { \i [1:0] \ni [2] } + connect \Y $reduce_or$issuer_ls180.v:180266$13309_Y + end + connect \$7 $not$issuer_ls180.v:180257$13300_Y + connect \$12 $reduce_or$issuer_ls180.v:180258$13301_Y + connect \$11 $not$issuer_ls180.v:180259$13302_Y + connect \$16 $reduce_or$issuer_ls180.v:180260$13303_Y + connect \$15 $not$issuer_ls180.v:180261$13304_Y + connect \$1 $not$issuer_ls180.v:180262$13305_Y + connect \$19 $reduce_or$issuer_ls180.v:180263$13306_Y + connect \$4 $reduce_or$issuer_ls180.v:180264$13307_Y + connect \$3 $not$issuer_ls180.v:180265$13308_Y + connect \$8 $reduce_or$issuer_ls180.v:180266$13309_Y + connect \en_o \$19 + connect \o { \t4 \t3 \t2 \t1 \t0 } + connect \t4 \$15 + connect \t3 \$11 + connect \t2 \$7 + connect \t1 \$3 + connect \t0 \i [0] + connect \ni \$1 +end +attribute \src "issuer_ls180.v:180279.1-180381.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.wrpick_INT_o" +attribute \generator "nMigen" +module \wrpick_INT_o + attribute \src "issuer_ls180.v:180348.17-180348.91" + wire $not$issuer_ls180.v:180348$13310_Y + attribute \src "issuer_ls180.v:180350.18-180350.93" + wire $not$issuer_ls180.v:180350$13312_Y + attribute \src "issuer_ls180.v:180352.18-180352.93" + wire $not$issuer_ls180.v:180352$13314_Y + attribute \src "issuer_ls180.v:180353.17-180353.89" + wire width 10 $not$issuer_ls180.v:180353$13315_Y + attribute \src "issuer_ls180.v:180355.18-180355.93" + wire $not$issuer_ls180.v:180355$13317_Y + attribute \src "issuer_ls180.v:180357.18-180357.93" + wire $not$issuer_ls180.v:180357$13319_Y + attribute \src "issuer_ls180.v:180359.18-180359.93" + wire $not$issuer_ls180.v:180359$13321_Y + attribute \src "issuer_ls180.v:180361.18-180361.93" + wire $not$issuer_ls180.v:180361$13323_Y + attribute \src "issuer_ls180.v:180363.18-180363.93" + wire $not$issuer_ls180.v:180363$13325_Y + attribute \src "issuer_ls180.v:180366.17-180366.91" + wire $not$issuer_ls180.v:180366$13328_Y + attribute \src "issuer_ls180.v:180349.18-180349.106" + wire $reduce_or$issuer_ls180.v:180349$13311_Y + attribute \src "issuer_ls180.v:180351.18-180351.106" + wire $reduce_or$issuer_ls180.v:180351$13313_Y + attribute \src "issuer_ls180.v:180354.18-180354.106" + wire $reduce_or$issuer_ls180.v:180354$13316_Y + attribute \src "issuer_ls180.v:180356.18-180356.106" + wire $reduce_or$issuer_ls180.v:180356$13318_Y + attribute \src "issuer_ls180.v:180358.18-180358.106" + wire $reduce_or$issuer_ls180.v:180358$13320_Y + attribute \src "issuer_ls180.v:180360.18-180360.106" + wire $reduce_or$issuer_ls180.v:180360$13322_Y + attribute \src "issuer_ls180.v:180362.18-180362.106" + wire $reduce_or$issuer_ls180.v:180362$13324_Y + attribute \src "issuer_ls180.v:180364.18-180364.90" + wire $reduce_or$issuer_ls180.v:180364$13326_Y + attribute \src "issuer_ls180.v:180365.17-180365.103" + wire $reduce_or$issuer_ls180.v:180365$13327_Y + attribute \src "issuer_ls180.v:180367.17-180367.105" + wire $reduce_or$issuer_ls180.v:180367$13329_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" + wire width 10 \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$12 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$16 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$19 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$20 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$23 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$24 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$27 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$28 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$31 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$32 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$35 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$36 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" + wire \$39 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$4 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$8 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" + wire output 2 \en_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" + wire width 10 input 3 \i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:49" + wire width 10 \ni + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" + wire width 10 output 1 \o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t0 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t2 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t4 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t5 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t6 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t8 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t9 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$issuer_ls180.v:180348$13310 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$8 + connect \Y $not$issuer_ls180.v:180348$13310_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$issuer_ls180.v:180350$13312 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$12 + connect \Y $not$issuer_ls180.v:180350$13312_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$issuer_ls180.v:180352$13314 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$16 + connect \Y $not$issuer_ls180.v:180352$13314_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" + cell $not $not$issuer_ls180.v:180353$13315 + parameter \A_SIGNED 0 + parameter \A_WIDTH 10 + parameter \Y_WIDTH 10 + connect \A \i + connect \Y $not$issuer_ls180.v:180353$13315_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$issuer_ls180.v:180355$13317 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$20 + connect \Y $not$issuer_ls180.v:180355$13317_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$issuer_ls180.v:180357$13319 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$24 + connect \Y $not$issuer_ls180.v:180357$13319_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$issuer_ls180.v:180359$13321 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$28 + connect \Y $not$issuer_ls180.v:180359$13321_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$issuer_ls180.v:180361$13323 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$32 + connect \Y $not$issuer_ls180.v:180361$13323_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$issuer_ls180.v:180363$13325 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$36 + connect \Y $not$issuer_ls180.v:180363$13325_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$issuer_ls180.v:180366$13328 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$4 + connect \Y $not$issuer_ls180.v:180366$13328_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$issuer_ls180.v:180349$13311 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A { \i [2:0] \ni [3] } + connect \Y $reduce_or$issuer_ls180.v:180349$13311_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$issuer_ls180.v:180351$13313 + parameter \A_SIGNED 0 + parameter \A_WIDTH 5 + parameter \Y_WIDTH 1 + connect \A { \i [3:0] \ni [4] } + connect \Y $reduce_or$issuer_ls180.v:180351$13313_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$issuer_ls180.v:180354$13316 + parameter \A_SIGNED 0 + parameter \A_WIDTH 6 + parameter \Y_WIDTH 1 + connect \A { \i [4:0] \ni [5] } + connect \Y $reduce_or$issuer_ls180.v:180354$13316_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$issuer_ls180.v:180356$13318 + parameter \A_SIGNED 0 + parameter \A_WIDTH 7 + parameter \Y_WIDTH 1 + connect \A { \i [5:0] \ni [6] } + connect \Y $reduce_or$issuer_ls180.v:180356$13318_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$issuer_ls180.v:180358$13320 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A { \i [6:0] \ni [7] } + connect \Y $reduce_or$issuer_ls180.v:180358$13320_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$issuer_ls180.v:180360$13322 + parameter \A_SIGNED 0 + parameter \A_WIDTH 9 + parameter \Y_WIDTH 1 + connect \A { \i [7:0] \ni [8] } + connect \Y $reduce_or$issuer_ls180.v:180360$13322_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$issuer_ls180.v:180362$13324 + parameter \A_SIGNED 0 + parameter \A_WIDTH 10 + parameter \Y_WIDTH 1 + connect \A { \i [8:0] \ni [9] } + connect \Y $reduce_or$issuer_ls180.v:180362$13324_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" + cell $reduce_or $reduce_or$issuer_ls180.v:180364$13326 + parameter \A_SIGNED 0 + parameter \A_WIDTH 10 + parameter \Y_WIDTH 1 + connect \A \o + connect \Y $reduce_or$issuer_ls180.v:180364$13326_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$issuer_ls180.v:180365$13327 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A { \i [0] \ni [1] } + connect \Y $reduce_or$issuer_ls180.v:180365$13327_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$issuer_ls180.v:180367$13329 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A { \i [1:0] \ni [2] } + connect \Y $reduce_or$issuer_ls180.v:180367$13329_Y + end + connect \$7 $not$issuer_ls180.v:180348$13310_Y + connect \$12 $reduce_or$issuer_ls180.v:180349$13311_Y + connect \$11 $not$issuer_ls180.v:180350$13312_Y + connect \$16 $reduce_or$issuer_ls180.v:180351$13313_Y + connect \$15 $not$issuer_ls180.v:180352$13314_Y + connect \$1 $not$issuer_ls180.v:180353$13315_Y + connect \$20 $reduce_or$issuer_ls180.v:180354$13316_Y + connect \$19 $not$issuer_ls180.v:180355$13317_Y + connect \$24 $reduce_or$issuer_ls180.v:180356$13318_Y + connect \$23 $not$issuer_ls180.v:180357$13319_Y + connect \$28 $reduce_or$issuer_ls180.v:180358$13320_Y + connect \$27 $not$issuer_ls180.v:180359$13321_Y + connect \$32 $reduce_or$issuer_ls180.v:180360$13322_Y + connect \$31 $not$issuer_ls180.v:180361$13323_Y + connect \$36 $reduce_or$issuer_ls180.v:180362$13324_Y + connect \$35 $not$issuer_ls180.v:180363$13325_Y + connect \$39 $reduce_or$issuer_ls180.v:180364$13326_Y + connect \$4 $reduce_or$issuer_ls180.v:180365$13327_Y + connect \$3 $not$issuer_ls180.v:180366$13328_Y + connect \$8 $reduce_or$issuer_ls180.v:180367$13329_Y + connect \en_o \$39 + connect \o { \t9 \t8 \t7 \t6 \t5 \t4 \t3 \t2 \t1 \t0 } + connect \t9 \$35 + connect \t8 \$31 + connect \t7 \$27 + connect \t6 \$23 + connect \t5 \$19 + connect \t4 \$15 + connect \t3 \$11 + connect \t2 \$7 + connect \t1 \$3 + connect \t0 \i [0] + connect \ni \$1 +end +attribute \src "issuer_ls180.v:180385.1-180406.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.wrpick_SPR_spr1" +attribute \generator "nMigen" +module \wrpick_SPR_spr1 + attribute \src "issuer_ls180.v:180400.17-180400.89" + wire $not$issuer_ls180.v:180400$13330_Y + attribute \src "issuer_ls180.v:180401.17-180401.89" + wire $reduce_or$issuer_ls180.v:180401$13331_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" + wire output 2 \en_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" + wire input 3 \i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:49" + wire \ni + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" + wire output 1 \o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t0 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" + cell $not $not$issuer_ls180.v:180400$13330 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \i + connect \Y $not$issuer_ls180.v:180400$13330_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" + cell $reduce_or $reduce_or$issuer_ls180.v:180401$13331 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \o + connect \Y $reduce_or$issuer_ls180.v:180401$13331_Y + end + connect \$1 $not$issuer_ls180.v:180400$13330_Y + connect \$3 $reduce_or$issuer_ls180.v:180401$13331_Y + connect \en_o \$3 + connect \o \t0 + connect \t0 \i + connect \ni \$1 +end +attribute \src "issuer_ls180.v:180410.1-180431.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.wrpick_STATE_msr" +attribute \generator "nMigen" +module \wrpick_STATE_msr + attribute \src "issuer_ls180.v:180425.17-180425.89" + wire $not$issuer_ls180.v:180425$13332_Y + attribute \src "issuer_ls180.v:180426.17-180426.89" + wire $reduce_or$issuer_ls180.v:180426$13333_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" + wire \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" + wire output 2 \en_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" + wire input 3 \i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:49" + wire \ni + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" + wire output 1 \o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t0 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" + cell $not $not$issuer_ls180.v:180425$13332 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \i + connect \Y $not$issuer_ls180.v:180425$13332_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" + cell $reduce_or $reduce_or$issuer_ls180.v:180426$13333 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \o + connect \Y $reduce_or$issuer_ls180.v:180426$13333_Y + end + connect \$1 $not$issuer_ls180.v:180425$13332_Y + connect \$3 $reduce_or$issuer_ls180.v:180426$13333_Y + connect \en_o \$3 + connect \o \t0 + connect \t0 \i + connect \ni \$1 +end +attribute \src "issuer_ls180.v:180435.1-180465.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.wrpick_STATE_nia" +attribute \generator "nMigen" +module \wrpick_STATE_nia + attribute \src "issuer_ls180.v:180456.17-180456.89" + wire width 2 $not$issuer_ls180.v:180456$13334_Y + attribute \src "issuer_ls180.v:180458.17-180458.91" + wire $not$issuer_ls180.v:180458$13336_Y + attribute \src "issuer_ls180.v:180457.17-180457.103" + wire $reduce_or$issuer_ls180.v:180457$13335_Y + attribute \src "issuer_ls180.v:180459.17-180459.89" + wire $reduce_or$issuer_ls180.v:180459$13337_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" + wire width 2 \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$4 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" + wire output 2 \en_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" + wire width 2 input 3 \i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:49" + wire width 2 \ni + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" + wire width 2 output 1 \o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t0 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" + cell $not $not$issuer_ls180.v:180456$13334 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 2 + connect \A \i + connect \Y $not$issuer_ls180.v:180456$13334_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$issuer_ls180.v:180458$13336 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$4 + connect \Y $not$issuer_ls180.v:180458$13336_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$issuer_ls180.v:180457$13335 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A { \i [0] \ni [1] } + connect \Y $reduce_or$issuer_ls180.v:180457$13335_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" + cell $reduce_or $reduce_or$issuer_ls180.v:180459$13337 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A \o + connect \Y $reduce_or$issuer_ls180.v:180459$13337_Y + end + connect \$1 $not$issuer_ls180.v:180456$13334_Y + connect \$4 $reduce_or$issuer_ls180.v:180457$13335_Y + connect \$3 $not$issuer_ls180.v:180458$13336_Y + connect \$7 $reduce_or$issuer_ls180.v:180459$13337_Y + connect \en_o \$7 + connect \o { \t1 \t0 } + connect \t1 \$3 + connect \t0 \i [0] + connect \ni \$1 +end +attribute \src "issuer_ls180.v:180469.1-180508.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.wrpick_XER_xer_ca" +attribute \generator "nMigen" +module \wrpick_XER_xer_ca + attribute \src "issuer_ls180.v:180496.17-180496.91" + wire $not$issuer_ls180.v:180496$13338_Y + attribute \src "issuer_ls180.v:180498.17-180498.89" + wire width 3 $not$issuer_ls180.v:180498$13340_Y + attribute \src "issuer_ls180.v:180500.17-180500.91" + wire $not$issuer_ls180.v:180500$13342_Y + attribute \src "issuer_ls180.v:180497.18-180497.90" + wire $reduce_or$issuer_ls180.v:180497$13339_Y + attribute \src "issuer_ls180.v:180499.17-180499.103" + wire $reduce_or$issuer_ls180.v:180499$13341_Y + attribute \src "issuer_ls180.v:180501.17-180501.105" + wire $reduce_or$issuer_ls180.v:180501$13343_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" + wire width 3 \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$4 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$8 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" + wire output 2 \en_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" + wire width 3 input 3 \i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:49" + wire width 3 \ni + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" + wire width 3 output 1 \o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t0 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t2 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$issuer_ls180.v:180496$13338 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$8 + connect \Y $not$issuer_ls180.v:180496$13338_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" + cell $not $not$issuer_ls180.v:180498$13340 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 3 + connect \A \i + connect \Y $not$issuer_ls180.v:180498$13340_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$issuer_ls180.v:180500$13342 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$4 + connect \Y $not$issuer_ls180.v:180500$13342_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" + cell $reduce_or $reduce_or$issuer_ls180.v:180497$13339 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \o + connect \Y $reduce_or$issuer_ls180.v:180497$13339_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$issuer_ls180.v:180499$13341 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A { \i [0] \ni [1] } + connect \Y $reduce_or$issuer_ls180.v:180499$13341_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$issuer_ls180.v:180501$13343 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A { \i [1:0] \ni [2] } + connect \Y $reduce_or$issuer_ls180.v:180501$13343_Y + end + connect \$7 $not$issuer_ls180.v:180496$13338_Y + connect \$11 $reduce_or$issuer_ls180.v:180497$13339_Y + connect \$1 $not$issuer_ls180.v:180498$13340_Y + connect \$4 $reduce_or$issuer_ls180.v:180499$13341_Y + connect \$3 $not$issuer_ls180.v:180500$13342_Y + connect \$8 $reduce_or$issuer_ls180.v:180501$13343_Y + connect \en_o \$11 + connect \o { \t2 \t1 \t0 } + connect \t2 \$7 + connect \t1 \$3 + connect \t0 \i [0] + connect \ni \$1 +end +attribute \src "issuer_ls180.v:180512.1-180560.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.wrpick_XER_xer_ov" +attribute \generator "nMigen" +module \wrpick_XER_xer_ov + attribute \src "issuer_ls180.v:180545.17-180545.91" + wire $not$issuer_ls180.v:180545$13344_Y + attribute \src "issuer_ls180.v:180547.18-180547.93" + wire $not$issuer_ls180.v:180547$13346_Y + attribute \src "issuer_ls180.v:180549.17-180549.89" + wire width 4 $not$issuer_ls180.v:180549$13348_Y + attribute \src "issuer_ls180.v:180551.17-180551.91" + wire $not$issuer_ls180.v:180551$13350_Y + attribute \src "issuer_ls180.v:180546.18-180546.106" + wire $reduce_or$issuer_ls180.v:180546$13345_Y + attribute \src "issuer_ls180.v:180548.18-180548.90" + wire $reduce_or$issuer_ls180.v:180548$13347_Y + attribute \src "issuer_ls180.v:180550.17-180550.103" + wire $reduce_or$issuer_ls180.v:180550$13349_Y + attribute \src "issuer_ls180.v:180552.17-180552.105" + wire $reduce_or$issuer_ls180.v:180552$13351_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" + wire width 4 \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$12 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$4 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$8 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" + wire output 2 \en_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" + wire width 4 input 3 \i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:49" + wire width 4 \ni + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" + wire width 4 output 1 \o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t0 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t2 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$issuer_ls180.v:180545$13344 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$8 + connect \Y $not$issuer_ls180.v:180545$13344_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$issuer_ls180.v:180547$13346 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$12 + connect \Y $not$issuer_ls180.v:180547$13346_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" + cell $not $not$issuer_ls180.v:180549$13348 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \i + connect \Y $not$issuer_ls180.v:180549$13348_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$issuer_ls180.v:180551$13350 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$4 + connect \Y $not$issuer_ls180.v:180551$13350_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$issuer_ls180.v:180546$13345 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A { \i [2:0] \ni [3] } + connect \Y $reduce_or$issuer_ls180.v:180546$13345_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" + cell $reduce_or $reduce_or$issuer_ls180.v:180548$13347 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \o + connect \Y $reduce_or$issuer_ls180.v:180548$13347_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$issuer_ls180.v:180550$13349 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A { \i [0] \ni [1] } + connect \Y $reduce_or$issuer_ls180.v:180550$13349_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$issuer_ls180.v:180552$13351 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A { \i [1:0] \ni [2] } + connect \Y $reduce_or$issuer_ls180.v:180552$13351_Y + end + connect \$7 $not$issuer_ls180.v:180545$13344_Y + connect \$12 $reduce_or$issuer_ls180.v:180546$13345_Y + connect \$11 $not$issuer_ls180.v:180547$13346_Y + connect \$15 $reduce_or$issuer_ls180.v:180548$13347_Y + connect \$1 $not$issuer_ls180.v:180549$13348_Y + connect \$4 $reduce_or$issuer_ls180.v:180550$13349_Y + connect \$3 $not$issuer_ls180.v:180551$13350_Y + connect \$8 $reduce_or$issuer_ls180.v:180552$13351_Y + connect \en_o \$15 + connect \o { \t3 \t2 \t1 \t0 } + connect \t3 \$11 + connect \t2 \$7 + connect \t1 \$3 + connect \t0 \i [0] + connect \ni \$1 +end +attribute \src "issuer_ls180.v:180564.1-180612.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.core.wrpick_XER_xer_so" +attribute \generator "nMigen" +module \wrpick_XER_xer_so + attribute \src "issuer_ls180.v:180597.17-180597.91" + wire $not$issuer_ls180.v:180597$13352_Y + attribute \src "issuer_ls180.v:180599.18-180599.93" + wire $not$issuer_ls180.v:180599$13354_Y + attribute \src "issuer_ls180.v:180601.17-180601.89" + wire width 4 $not$issuer_ls180.v:180601$13356_Y + attribute \src "issuer_ls180.v:180603.17-180603.91" + wire $not$issuer_ls180.v:180603$13358_Y + attribute \src "issuer_ls180.v:180598.18-180598.106" + wire $reduce_or$issuer_ls180.v:180598$13353_Y + attribute \src "issuer_ls180.v:180600.18-180600.90" + wire $reduce_or$issuer_ls180.v:180600$13355_Y + attribute \src "issuer_ls180.v:180602.17-180602.103" + wire $reduce_or$issuer_ls180.v:180602$13357_Y + attribute \src "issuer_ls180.v:180604.17-180604.105" + wire $reduce_or$issuer_ls180.v:180604$13359_Y + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" + wire width 4 \$1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$11 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$12 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$4 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + wire \$8 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" + wire output 2 \en_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" + wire width 4 input 3 \i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:49" + wire width 4 \ni + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" + wire width 4 output 1 \o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t0 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t1 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t2 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" + wire \t3 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$issuer_ls180.v:180597$13352 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$8 + connect \Y $not$issuer_ls180.v:180597$13352_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$issuer_ls180.v:180599$13354 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$12 + connect \Y $not$issuer_ls180.v:180599$13354_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" + cell $not $not$issuer_ls180.v:180601$13356 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 4 + connect \A \i + connect \Y $not$issuer_ls180.v:180601$13356_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $not $not$issuer_ls180.v:180603$13358 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \$4 + connect \Y $not$issuer_ls180.v:180603$13358_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$issuer_ls180.v:180598$13353 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A { \i [2:0] \ni [3] } + connect \Y $reduce_or$issuer_ls180.v:180598$13353_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" + cell $reduce_or $reduce_or$issuer_ls180.v:180600$13355 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \o + connect \Y $reduce_or$issuer_ls180.v:180600$13355_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$issuer_ls180.v:180602$13357 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \Y_WIDTH 1 + connect \A { \i [0] \ni [1] } + connect \Y $reduce_or$issuer_ls180.v:180602$13357_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" + cell $reduce_or $reduce_or$issuer_ls180.v:180604$13359 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A { \i [1:0] \ni [2] } + connect \Y $reduce_or$issuer_ls180.v:180604$13359_Y + end + connect \$7 $not$issuer_ls180.v:180597$13352_Y + connect \$12 $reduce_or$issuer_ls180.v:180598$13353_Y + connect \$11 $not$issuer_ls180.v:180599$13354_Y + connect \$15 $reduce_or$issuer_ls180.v:180600$13355_Y + connect \$1 $not$issuer_ls180.v:180601$13356_Y + connect \$4 $reduce_or$issuer_ls180.v:180602$13357_Y + connect \$3 $not$issuer_ls180.v:180603$13358_Y + connect \$8 $reduce_or$issuer_ls180.v:180604$13359_Y + connect \en_o \$15 + connect \o { \t3 \t2 \t1 \t0 } + connect \t3 \$11 + connect \t2 \$7 + connect \t1 \$3 + connect \t0 \i [0] + connect \ni \$1 +end +attribute \src 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"/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire \reg_1_src31__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 2 \reg_1_w1__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire \reg_1_w1__wen + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 2 \reg_2_dest12__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire \reg_2_dest12__wen + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 2 \reg_2_dest22__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire \reg_2_dest22__wen + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 2 \reg_2_dest32__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire \reg_2_dest32__wen + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 2 \reg_2_r2__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire \reg_2_r2__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 2 \reg_2_src12__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire \reg_2_src12__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 2 \reg_2_src22__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire \reg_2_src22__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 2 \reg_2_src32__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire \reg_2_src32__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 2 \reg_2_w2__data_i + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire \reg_2_w2__wen + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:170" + wire width 3 \ren_delay + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:170" + wire width 3 \ren_delay$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:170" + wire width 3 \ren_delay$11$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:170" + wire width 3 \ren_delay$18 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:170" + wire width 3 \ren_delay$18$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:170" + wire width 3 \ren_delay$next + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 2 output 3 \src1__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 3 input 4 \src1__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 2 output 5 \src2__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 3 input 6 \src2__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 2 output 7 \src3__data_o + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 3 input 8 \src3__ren + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 3 input 10 \wen + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 3 input 12 \wen$2 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" + wire width 3 input 14 \wen$4 + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" + cell $or $or$issuer_ls180.v:180783$13360 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 2 + connect \A \reg_0_src10__data_o + connect \B \$7 + connect \Y $or$issuer_ls180.v:180783$13360_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + cell $or $or$issuer_ls180.v:180785$13362 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 2 + connect \A \reg_1_src21__data_o + connect \B \reg_2_src22__data_o + connect \Y $or$issuer_ls180.v:180785$13362_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" + cell $or $or$issuer_ls180.v:180786$13363 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 2 + connect \A \reg_0_src20__data_o + connect \B \$14 + connect \Y $or$issuer_ls180.v:180786$13363_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + cell $or $or$issuer_ls180.v:180788$13365 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 2 + connect \A \reg_1_src31__data_o + connect \B \reg_2_src32__data_o + connect \Y $or$issuer_ls180.v:180788$13365_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" + cell $or $or$issuer_ls180.v:180789$13366 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 2 + connect \A \reg_0_src30__data_o + connect \B \$21 + connect \Y $or$issuer_ls180.v:180789$13366_Y + end + attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" + cell $or $or$issuer_ls180.v:180791$13368 + parameter \A_SIGNED 0 + parameter \A_WIDTH 2 + parameter \B_SIGNED 0 + parameter \B_WIDTH 2 + parameter \Y_WIDTH 2 + connect \A \reg_1_src11__data_o + connect \B \reg_2_src12__data_o + connect \Y $or$issuer_ls180.v:180791$13368_Y + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" + cell $reduce_or $reduce_or$issuer_ls180.v:180784$13361 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \ren_delay$11 + connect \Y $reduce_or$issuer_ls180.v:180784$13361_Y + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" + cell $reduce_or $reduce_or$issuer_ls180.v:180787$13364 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \ren_delay$18 + connect \Y $reduce_or$issuer_ls180.v:180787$13364_Y + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" + cell $reduce_or $reduce_or$issuer_ls180.v:180790$13367 + parameter \A_SIGNED 0 + parameter \A_WIDTH 3 + parameter \Y_WIDTH 1 + connect \A \ren_delay + connect \Y $reduce_or$issuer_ls180.v:180790$13367_Y + end + attribute \module_not_derived 1 + attribute \src "issuer_ls180.v:180798.15-180817.4" + cell \reg_0$129 \reg_0 + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \dest10__data_i \reg_0_dest10__data_i + connect \dest10__wen \reg_0_dest10__wen + connect \dest20__data_i \reg_0_dest20__data_i + connect \dest20__wen \reg_0_dest20__wen + connect \dest30__data_i \reg_0_dest30__data_i + connect \dest30__wen \reg_0_dest30__wen + connect \r0__data_o \reg_0_r0__data_o + connect \r0__ren \reg_0_r0__ren + connect \src10__data_o \reg_0_src10__data_o + connect \src10__ren \reg_0_src10__ren + connect \src20__data_o \reg_0_src20__data_o + connect \src20__ren \reg_0_src20__ren + connect \src30__data_o \reg_0_src30__data_o + connect \src30__ren \reg_0_src30__ren + connect \w0__data_i \reg_0_w0__data_i + connect \w0__wen \reg_0_w0__wen + end + attribute \module_not_derived 1 + attribute \src "issuer_ls180.v:180818.15-180837.4" + cell \reg_1$130 \reg_1 + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \dest11__data_i \reg_1_dest11__data_i + connect \dest11__wen \reg_1_dest11__wen + connect \dest21__data_i \reg_1_dest21__data_i + connect \dest21__wen \reg_1_dest21__wen + connect \dest31__data_i \reg_1_dest31__data_i + connect \dest31__wen \reg_1_dest31__wen + connect \r1__data_o \reg_1_r1__data_o + connect \r1__ren \reg_1_r1__ren + connect \src11__data_o \reg_1_src11__data_o + connect \src11__ren \reg_1_src11__ren + connect \src21__data_o \reg_1_src21__data_o + connect \src21__ren \reg_1_src21__ren + connect \src31__data_o \reg_1_src31__data_o + connect \src31__ren \reg_1_src31__ren + connect \w1__data_i \reg_1_w1__data_i + connect \w1__wen \reg_1_w1__wen + end + attribute \module_not_derived 1 + attribute \src "issuer_ls180.v:180838.15-180857.4" + cell \reg_2$131 \reg_2 + connect \coresync_clk \coresync_clk + connect \coresync_rst \coresync_rst + connect \dest12__data_i \reg_2_dest12__data_i + connect \dest12__wen \reg_2_dest12__wen + connect \dest22__data_i \reg_2_dest22__data_i + connect \dest22__wen \reg_2_dest22__wen + connect \dest32__data_i \reg_2_dest32__data_i + connect \dest32__wen \reg_2_dest32__wen + connect \r2__data_o \reg_2_r2__data_o + connect \r2__ren \reg_2_r2__ren + connect \src12__data_o \reg_2_src12__data_o + connect \src12__ren \reg_2_src12__ren + connect \src22__data_o \reg_2_src22__data_o + connect \src22__ren \reg_2_src22__ren + connect \src32__data_o \reg_2_src32__data_o + connect \src32__ren \reg_2_src32__ren + connect \w2__data_i \reg_2_w2__data_i + connect \w2__wen \reg_2_w2__wen + end + attribute \src "issuer_ls180.v:180617.7-180617.20" + process $proc$issuer_ls180.v:180617$13386 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "issuer_ls180.v:180751.13-180751.29" + process $proc$issuer_ls180.v:180751$13387 + assign { } { } + assign $1\ren_delay[2:0] 3'000 + sync always + sync init + update \ren_delay $1\ren_delay[2:0] + end + attribute \src "issuer_ls180.v:180753.13-180753.34" + process $proc$issuer_ls180.v:180753$13388 + assign { } { } + assign $0\ren_delay$11[2:0]$13389 3'000 + sync always + sync init + update \ren_delay$11 $0\ren_delay$11[2:0]$13389 + end + attribute \src "issuer_ls180.v:180757.13-180757.34" + process $proc$issuer_ls180.v:180757$13390 + assign { } { } + assign $0\ren_delay$18[2:0]$13391 3'000 + sync always + sync init + update \ren_delay$18 $0\ren_delay$18[2:0]$13391 + end + attribute \src "issuer_ls180.v:180792.3-180793.43" + process $proc$issuer_ls180.v:180792$13369 + assign { } { } + assign $0\ren_delay$18[2:0]$13370 \ren_delay$18$next + sync posedge \coresync_clk + update \ren_delay$18 $0\ren_delay$18[2:0]$13370 + end + attribute \src "issuer_ls180.v:180794.3-180795.43" + process $proc$issuer_ls180.v:180794$13371 + assign { } { } + assign $0\ren_delay$11[2:0]$13372 \ren_delay$11$next + sync posedge \coresync_clk + update \ren_delay$11 $0\ren_delay$11[2:0]$13372 + end + attribute \src "issuer_ls180.v:180796.3-180797.35" + process $proc$issuer_ls180.v:180796$13373 + assign { } { } + assign $0\ren_delay[2:0] \ren_delay$next + sync posedge \coresync_clk + update \ren_delay $0\ren_delay[2:0] + end + attribute \src "issuer_ls180.v:180858.3-180866.6" + process $proc$issuer_ls180.v:180858$13374 + assign { } { } + assign { } { } + assign $0\ren_delay$18$next[2:0]$13375 $1\ren_delay$18$next[2:0]$13376 + attribute \src "issuer_ls180.v:180859.5-180859.29" + switch \initial + attribute \src "issuer_ls180.v:180859.9-180859.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\ren_delay$18$next[2:0]$13376 3'000 + case + assign $1\ren_delay$18$next[2:0]$13376 \src3__ren + end + sync always + update \ren_delay$18$next $0\ren_delay$18$next[2:0]$13375 + end + attribute \src "issuer_ls180.v:180867.3-180876.6" + process $proc$issuer_ls180.v:180867$13377 + assign { } { } + assign { } { } + assign $0\src3__data_o[1:0] $1\src3__data_o[1:0] + attribute \src "issuer_ls180.v:180868.5-180868.29" + switch \initial + attribute \src "issuer_ls180.v:180868.9-180868.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:172" + switch \$19 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\src3__data_o[1:0] \$23 + case + assign $1\src3__data_o[1:0] 2'00 + end + sync always + update \src3__data_o $0\src3__data_o[1:0] + end + attribute \src "issuer_ls180.v:180877.3-180885.6" + process $proc$issuer_ls180.v:180877$13378 + assign { } { } + assign { } { } + assign $0\ren_delay$next[2:0]$13379 $1\ren_delay$next[2:0]$13380 + attribute \src "issuer_ls180.v:180878.5-180878.29" + switch \initial + attribute \src "issuer_ls180.v:180878.9-180878.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\ren_delay$next[2:0]$13380 3'000 + case + assign $1\ren_delay$next[2:0]$13380 \src1__ren + end + sync always + update \ren_delay$next $0\ren_delay$next[2:0]$13379 + end + attribute \src "issuer_ls180.v:180886.3-180895.6" + process $proc$issuer_ls180.v:180886$13381 + assign { } { } + assign { } { } + assign $0\src1__data_o[1:0] $1\src1__data_o[1:0] + attribute \src "issuer_ls180.v:180887.5-180887.29" + switch \initial + attribute \src "issuer_ls180.v:180887.9-180887.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:172" + switch \$5 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\src1__data_o[1:0] \$9 + case + assign $1\src1__data_o[1:0] 2'00 + end + sync always + update \src1__data_o $0\src1__data_o[1:0] + end + attribute \src "issuer_ls180.v:180896.3-180904.6" + process $proc$issuer_ls180.v:180896$13382 + assign { } { } + assign { } { } + assign $0\ren_delay$11$next[2:0]$13383 $1\ren_delay$11$next[2:0]$13384 + attribute \src "issuer_ls180.v:180897.5-180897.29" + switch \initial + attribute \src "issuer_ls180.v:180897.9-180897.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \coresync_rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\ren_delay$11$next[2:0]$13384 3'000 + case + assign $1\ren_delay$11$next[2:0]$13384 \src2__ren + end + sync always + update \ren_delay$11$next $0\ren_delay$11$next[2:0]$13383 + end + attribute \src "issuer_ls180.v:180905.3-180914.6" + process $proc$issuer_ls180.v:180905$13385 + assign { } { } + assign { } { } + assign $0\src2__data_o[1:0] $1\src2__data_o[1:0] + attribute \src "issuer_ls180.v:180906.5-180906.29" + switch \initial + attribute \src "issuer_ls180.v:180906.9-180906.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:172" + switch \$12 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\src2__data_o[1:0] \$16 + case + assign $1\src2__data_o[1:0] 2'00 + end + sync always + update \src2__data_o $0\src2__data_o[1:0] + end + connect \$9 $or$issuer_ls180.v:180783$13360_Y + connect \$12 $reduce_or$issuer_ls180.v:180784$13361_Y + connect \$14 $or$issuer_ls180.v:180785$13362_Y + connect \$16 $or$issuer_ls180.v:180786$13363_Y + connect \$19 $reduce_or$issuer_ls180.v:180787$13364_Y + connect \$21 $or$issuer_ls180.v:180788$13365_Y + connect \$23 $or$issuer_ls180.v:180789$13366_Y + connect \$5 $reduce_or$issuer_ls180.v:180790$13367_Y + connect \$7 $or$issuer_ls180.v:180791$13368_Y + connect \full_wr__data_i 6'000000 + connect \full_wr__wen 3'000 + connect { \reg_2_w2__wen \reg_1_w1__wen \reg_0_w0__wen } 3'000 + connect { \reg_2_w2__data_i \reg_1_w1__data_i \reg_0_w0__data_i } 6'000000 + connect { \reg_2_r2__ren \reg_1_r1__ren \reg_0_r0__ren } \full_rd__ren + connect \full_rd__data_o { \reg_2_r2__data_o \reg_1_r1__data_o \reg_0_r0__data_o } + connect \reg_2_dest32__data_i \data_i$1 + connect \reg_1_dest31__data_i \data_i$1 + connect \reg_0_dest30__data_i \data_i$1 + connect { \reg_2_dest32__wen \reg_1_dest31__wen \reg_0_dest30__wen } \wen$2 + connect \reg_2_dest22__data_i \data_i + connect \reg_1_dest21__data_i \data_i + connect \reg_0_dest20__data_i \data_i + connect { \reg_2_dest22__wen \reg_1_dest21__wen \reg_0_dest20__wen } \wen + connect \reg_2_dest12__data_i \data_i$3 + connect \reg_1_dest11__data_i \data_i$3 + connect \reg_0_dest10__data_i \data_i$3 + connect { \reg_2_dest12__wen \reg_1_dest11__wen \reg_0_dest10__wen } \wen$4 + connect { \reg_2_src32__ren \reg_1_src31__ren \reg_0_src30__ren } \src3__ren + connect { \reg_2_src22__ren \reg_1_src21__ren \reg_0_src20__ren } \src2__ren + connect { \reg_2_src12__ren \reg_1_src11__ren \reg_0_src10__ren } \src1__ren +end +attribute \src "issuer_ls180.v:180940.1-181254.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.xics_icp" +attribute \generator "nMigen" +module \xics_icp + attribute \src "issuer_ls180.v:181118.3-181146.6" + wire width 32 $0\be_out[31:0] + attribute \src "issuer_ls180.v:181169.3-181177.6" + wire $0\core_irq_o$next[0:0]$13427 + attribute \src "issuer_ls180.v:181062.3-181063.37" + wire $0\core_irq_o[0:0] + attribute \src "issuer_ls180.v:181188.3-181250.6" + wire width 8 $0\cppr$10[7:0]$13431 + attribute \src "issuer_ls180.v:181074.3-181089.6" + wire width 8 $0\cppr$next[7:0]$13410 + attribute \src "issuer_ls180.v:181066.3-181067.25" + wire width 8 $0\cppr[7:0] + attribute \src "issuer_ls180.v:181178.3-181187.6" + wire width 32 $0\icp_wb__dat_r[31:0] + attribute \src "issuer_ls180.v:180941.7-180941.20" + wire $0\initial[0:0] + attribute \src "issuer_ls180.v:181188.3-181250.6" + wire $0\irq$12[0:0]$13432 + attribute \src "issuer_ls180.v:181074.3-181089.6" + wire $0\irq$next[0:0]$13411 + attribute \src "issuer_ls180.v:181070.3-181071.23" + wire $0\irq[0:0] + attribute \src "issuer_ls180.v:181188.3-181250.6" + wire width 8 $0\mfrr$11[7:0]$13433 + attribute \src "issuer_ls180.v:181074.3-181089.6" + wire width 8 $0\mfrr$next[7:0]$13412 + attribute \src "issuer_ls180.v:181068.3-181069.25" + wire width 8 $0\mfrr[7:0] + attribute \src "issuer_ls180.v:181157.3-181168.6" + wire width 8 $0\min_pri[7:0] + attribute \src "issuer_ls180.v:181147.3-181156.6" + wire width 8 $0\pending_priority[7:0] + attribute \src "issuer_ls180.v:181188.3-181250.6" + wire $0\wb_ack$14[0:0]$13434 + attribute \src "issuer_ls180.v:181074.3-181089.6" + wire $0\wb_ack$next[0:0]$13413 + attribute \src "issuer_ls180.v:181060.3-181061.29" + wire $0\wb_ack[0:0] + attribute \src "issuer_ls180.v:181188.3-181250.6" + wire width 32 $0\wb_rd_data$13[31:0]$13435 + attribute \src "issuer_ls180.v:181074.3-181089.6" + wire width 32 $0\wb_rd_data$next[31:0]$13414 + attribute \src "issuer_ls180.v:181072.3-181073.37" + wire width 32 $0\wb_rd_data[31:0] + attribute \src "issuer_ls180.v:181090.3-181117.6" + wire $0\xirr_accept_rd[0:0] + attribute \src "issuer_ls180.v:181188.3-181250.6" + wire width 24 $0\xisr$9[23:0]$13436 + attribute \src "issuer_ls180.v:181074.3-181089.6" + wire width 24 $0\xisr$next[23:0]$13415 + attribute \src "issuer_ls180.v:181064.3-181065.25" + wire width 24 $0\xisr[23:0] + attribute \src "issuer_ls180.v:181118.3-181146.6" + wire width 32 $1\be_out[31:0] + attribute \src "issuer_ls180.v:181169.3-181177.6" + wire $1\core_irq_o$next[0:0]$13428 + attribute \src "issuer_ls180.v:180970.7-180970.24" + wire $1\core_irq_o[0:0] + attribute \src "issuer_ls180.v:181188.3-181250.6" + wire width 8 $1\cppr$10[7:0]$13437 + attribute \src "issuer_ls180.v:181074.3-181089.6" + wire width 8 $1\cppr$next[7:0]$13416 + attribute \src "issuer_ls180.v:180974.13-180974.25" + wire width 8 $1\cppr[7:0] + attribute \src "issuer_ls180.v:181178.3-181187.6" + wire width 32 $1\icp_wb__dat_r[31:0] + attribute \src "issuer_ls180.v:181188.3-181250.6" + wire $1\irq$12[0:0]$13447 + attribute \src "issuer_ls180.v:181074.3-181089.6" + wire $1\irq$next[0:0]$13417 + attribute \src "issuer_ls180.v:181003.7-181003.17" + wire $1\irq[0:0] + attribute \src "issuer_ls180.v:181188.3-181250.6" + wire width 8 $1\mfrr$11[7:0]$13438 + attribute \src "issuer_ls180.v:181074.3-181089.6" + wire width 8 $1\mfrr$next[7:0]$13418 + attribute \src "issuer_ls180.v:181011.13-181011.25" + wire width 8 $1\mfrr[7:0] + attribute \src "issuer_ls180.v:181157.3-181168.6" + wire width 8 $1\min_pri[7:0] + attribute \src "issuer_ls180.v:181147.3-181156.6" + wire width 8 $1\pending_priority[7:0] + attribute \src "issuer_ls180.v:181188.3-181250.6" + wire $1\wb_ack$14[0:0]$13439 + attribute \src "issuer_ls180.v:181074.3-181089.6" + wire $1\wb_ack$next[0:0]$13419 + attribute \src "issuer_ls180.v:181025.7-181025.20" + wire $1\wb_ack[0:0] + attribute \src "issuer_ls180.v:181074.3-181089.6" + wire width 32 $1\wb_rd_data$next[31:0]$13420 + attribute \src "issuer_ls180.v:181033.14-181033.32" + wire width 32 $1\wb_rd_data[31:0] + attribute \src "issuer_ls180.v:181090.3-181117.6" + wire $1\xirr_accept_rd[0:0] + attribute \src "issuer_ls180.v:181188.3-181250.6" + wire width 24 $1\xisr$9[23:0]$13444 + attribute \src "issuer_ls180.v:181074.3-181089.6" + wire width 24 $1\xisr$next[23:0]$13421 + attribute \src "issuer_ls180.v:181043.14-181043.31" + wire width 24 $1\xisr[23:0] + attribute \src "issuer_ls180.v:181118.3-181146.6" + wire width 32 $2\be_out[31:0] + attribute \src "issuer_ls180.v:181188.3-181250.6" + wire width 8 $2\cppr$10[7:0]$13440 + attribute \src "issuer_ls180.v:181188.3-181250.6" + wire width 8 $2\mfrr$11[7:0]$13441 + attribute \src "issuer_ls180.v:181090.3-181117.6" + wire $2\xirr_accept_rd[0:0] + attribute \src "issuer_ls180.v:181188.3-181250.6" + wire width 24 $2\xisr$9[23:0]$13445 + attribute \src "issuer_ls180.v:181118.3-181146.6" + wire width 32 $3\be_out[31:0] + attribute \src "issuer_ls180.v:181188.3-181250.6" + wire width 8 $3\cppr$10[7:0]$13442 + attribute \src "issuer_ls180.v:181188.3-181250.6" + wire width 8 $3\mfrr$11[7:0]$13443 + attribute \src "issuer_ls180.v:181090.3-181117.6" + wire $3\xirr_accept_rd[0:0] + attribute \src "issuer_ls180.v:181188.3-181250.6" + wire width 8 $4\cppr$10[7:0]$13446 + attribute \src "issuer_ls180.v:181090.3-181117.6" + wire $4\xirr_accept_rd[0:0] + attribute \src "issuer_ls180.v:181050.18-181050.116" + wire $and$issuer_ls180.v:181050$13392_Y + attribute \src "issuer_ls180.v:181054.18-181054.116" + wire $and$issuer_ls180.v:181054$13396_Y + attribute \src "issuer_ls180.v:181056.18-181056.116" + wire $and$issuer_ls180.v:181056$13398_Y + attribute \src "issuer_ls180.v:181059.17-181059.109" + wire $and$issuer_ls180.v:181059$13401_Y + attribute \src "issuer_ls180.v:181055.18-181055.110" + wire $eq$issuer_ls180.v:181055$13397_Y + attribute \src "issuer_ls180.v:181052.18-181052.114" + wire $lt$issuer_ls180.v:181052$13394_Y + attribute \src "issuer_ls180.v:181053.18-181053.109" + wire $lt$issuer_ls180.v:181053$13395_Y + attribute \src "issuer_ls180.v:181058.18-181058.114" + wire $lt$issuer_ls180.v:181058$13400_Y + attribute \src "issuer_ls180.v:181051.18-181051.109" + wire $ne$issuer_ls180.v:181051$13393_Y + attribute \src "issuer_ls180.v:181057.18-181057.109" + wire $ne$issuer_ls180.v:181057$13399_Y + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:117" + wire \$15 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:173" + wire \$17 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:178" + wire \$19 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:195" + wire \$21 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:117" + wire \$23 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:162" + wire \$25 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:117" + wire \$27 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:173" + wire \$29 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:178" + wire \$31 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:96" + wire \$7 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:103" + wire width 32 \be_in + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:104" + wire width 32 \be_out + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:140" + wire input 3 \clk + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:83" + wire output 2 \core_irq_o + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:83" + wire \core_irq_o$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:62" + wire width 8 \cppr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:62" + wire width 8 \cppr$10 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:62" + wire width 8 \cppr$2 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:62" + wire width 8 \cppr$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" + wire output 5 \icp_wb__ack + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" + wire width 28 input 11 \icp_wb__adr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" + wire input 6 \icp_wb__cyc + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" + wire width 32 output 7 \icp_wb__dat_r + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" + wire width 32 input 8 \icp_wb__dat_w + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" + wire width 4 input 12 \icp_wb__sel + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" + wire input 9 \icp_wb__stb + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:81" + wire input 10 \icp_wb__we + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:46" + wire width 8 input 1 \ics_i_pri + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:45" + wire width 4 input 13 \ics_i_src + attribute \src "issuer_ls180.v:180941.7-180941.15" + wire \initial + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:64" + wire \irq + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:64" + wire \irq$12 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:64" + wire \irq$4 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:64" + wire \irq$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:63" + wire width 8 \mfrr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:63" + wire width 8 \mfrr$11 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:63" + wire width 8 \mfrr$3 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:63" + wire width 8 \mfrr$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:107" + wire width 8 \min_pri + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:106" + wire width 8 \pending_priority + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/issuer.py:140" + wire input 4 \rst + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:66" + wire \wb_ack + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:66" + wire \wb_ack$14 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:66" + wire \wb_ack$6 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:66" + wire \wb_ack$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:65" + wire width 32 \wb_rd_data + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:65" + wire width 32 \wb_rd_data$13 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:65" + wire width 32 \wb_rd_data$5 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:65" + wire width 32 \wb_rd_data$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:101" + wire \xirr_accept_rd + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:61" + wire width 24 \xisr + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:61" + wire width 24 \xisr$1 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:61" + wire width 24 \xisr$9 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:61" + wire width 24 \xisr$next + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:117" + cell $and $and$issuer_ls180.v:181050$13392 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \icp_wb__cyc + connect \B \icp_wb__stb + connect \Y $and$issuer_ls180.v:181050$13392_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:117" + cell $and $and$issuer_ls180.v:181054$13396 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \icp_wb__cyc + connect \B \icp_wb__stb + connect \Y $and$issuer_ls180.v:181054$13396_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:117" + cell $and $and$issuer_ls180.v:181056$13398 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \icp_wb__cyc + connect \B \icp_wb__stb + connect \Y $and$issuer_ls180.v:181056$13398_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:96" + cell $and $and$issuer_ls180.v:181059$13401 + parameter \A_SIGNED 0 + parameter \A_WIDTH 1 + parameter \B_SIGNED 0 + parameter \B_WIDTH 1 + parameter \Y_WIDTH 1 + connect \A \wb_ack + connect \B \icp_wb__cyc + connect \Y $and$issuer_ls180.v:181059$13401_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:162" + cell $eq $eq$issuer_ls180.v:181055$13397 + parameter \A_SIGNED 0 + parameter \A_WIDTH 4 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 1 + connect \A \icp_wb__sel + connect \B 4'1111 + connect \Y $eq$issuer_ls180.v:181055$13397_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:178" + cell $lt $lt$issuer_ls180.v:181052$13394 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \mfrr + connect \B \pending_priority + connect \Y $lt$issuer_ls180.v:181052$13394_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:195" + cell $lt $lt$issuer_ls180.v:181053$13395 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \min_pri + connect \B \cppr$10 + connect \Y $lt$issuer_ls180.v:181053$13395_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:178" + cell $lt $lt$issuer_ls180.v:181058$13400 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \mfrr + connect \B \pending_priority + connect \Y $lt$issuer_ls180.v:181058$13400_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:173" + cell $ne $ne$issuer_ls180.v:181051$13393 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \ics_i_pri + connect \B 8'11111111 + connect \Y $ne$issuer_ls180.v:181051$13393_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:173" + cell $ne $ne$issuer_ls180.v:181057$13399 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \ics_i_pri + connect \B 8'11111111 + connect \Y $ne$issuer_ls180.v:181057$13399_Y + end + attribute \src "issuer_ls180.v:180941.7-180941.20" + process $proc$issuer_ls180.v:180941$13448 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "issuer_ls180.v:180970.7-180970.24" + process $proc$issuer_ls180.v:180970$13449 + assign { } { } + assign $1\core_irq_o[0:0] 1'0 + sync always + sync init + update \core_irq_o $1\core_irq_o[0:0] + end + attribute \src "issuer_ls180.v:180974.13-180974.25" + process $proc$issuer_ls180.v:180974$13450 + assign { } { } + assign $1\cppr[7:0] 8'00000000 + sync always + sync init + update \cppr $1\cppr[7:0] + end + attribute \src "issuer_ls180.v:181003.7-181003.17" + process $proc$issuer_ls180.v:181003$13451 + assign { } { } + assign $1\irq[0:0] 1'0 + sync always + sync init + update \irq $1\irq[0:0] + end + attribute \src "issuer_ls180.v:181011.13-181011.25" + process $proc$issuer_ls180.v:181011$13452 + assign { } { } + assign $1\mfrr[7:0] 8'11111111 + sync always + sync init + update \mfrr $1\mfrr[7:0] + end + attribute \src "issuer_ls180.v:181025.7-181025.20" + process $proc$issuer_ls180.v:181025$13453 + assign { } { } + assign $1\wb_ack[0:0] 1'0 + sync always + sync init + update \wb_ack $1\wb_ack[0:0] + end + attribute \src "issuer_ls180.v:181033.14-181033.32" + process $proc$issuer_ls180.v:181033$13454 + assign { } { } + assign $1\wb_rd_data[31:0] 0 + sync always + sync init + update \wb_rd_data $1\wb_rd_data[31:0] + end + attribute \src "issuer_ls180.v:181043.14-181043.31" + process $proc$issuer_ls180.v:181043$13455 + assign { } { } + assign $1\xisr[23:0] 24'000000000000000000000000 + sync always + sync init + update \xisr $1\xisr[23:0] + end + attribute \src "issuer_ls180.v:181060.3-181061.29" + process $proc$issuer_ls180.v:181060$13402 + assign { } { } + assign $0\wb_ack[0:0] \wb_ack$next + sync posedge \clk + update \wb_ack $0\wb_ack[0:0] + end + attribute \src "issuer_ls180.v:181062.3-181063.37" + process $proc$issuer_ls180.v:181062$13403 + assign { } { } + assign $0\core_irq_o[0:0] \core_irq_o$next + sync posedge \clk + update \core_irq_o $0\core_irq_o[0:0] + end + attribute \src "issuer_ls180.v:181064.3-181065.25" + process $proc$issuer_ls180.v:181064$13404 + assign { } { } + assign $0\xisr[23:0] \xisr$next + sync posedge \clk + update \xisr $0\xisr[23:0] + end + attribute \src "issuer_ls180.v:181066.3-181067.25" + process $proc$issuer_ls180.v:181066$13405 + assign { } { } + assign $0\cppr[7:0] \cppr$next + sync posedge \clk + update \cppr $0\cppr[7:0] + end + attribute \src "issuer_ls180.v:181068.3-181069.25" + process $proc$issuer_ls180.v:181068$13406 + assign { } { } + assign $0\mfrr[7:0] \mfrr$next + sync posedge \clk + update \mfrr $0\mfrr[7:0] + end + attribute \src "issuer_ls180.v:181070.3-181071.23" + process $proc$issuer_ls180.v:181070$13407 + assign { } { } + assign $0\irq[0:0] \irq$next + sync posedge \clk + update \irq $0\irq[0:0] + end + attribute \src "issuer_ls180.v:181072.3-181073.37" + process $proc$issuer_ls180.v:181072$13408 + assign { } { } + assign $0\wb_rd_data[31:0] \wb_rd_data$next + sync posedge \clk + update \wb_rd_data $0\wb_rd_data[31:0] + end + attribute \src "issuer_ls180.v:181074.3-181089.6" + process $proc$issuer_ls180.v:181074$13409 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\cppr$next[7:0]$13410 $1\cppr$next[7:0]$13416 + assign $0\irq$next[0:0]$13411 $1\irq$next[0:0]$13417 + assign $0\mfrr$next[7:0]$13412 $1\mfrr$next[7:0]$13418 + assign $0\wb_ack$next[0:0]$13413 $1\wb_ack$next[0:0]$13419 + assign $0\wb_rd_data$next[31:0]$13414 $1\wb_rd_data$next[31:0]$13420 + assign $0\xisr$next[23:0]$13415 $1\xisr$next[23:0]$13421 + attribute \src "issuer_ls180.v:181075.5-181075.29" + switch \initial + attribute \src "issuer_ls180.v:181075.9-181075.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\xisr$next[23:0]$13421 24'000000000000000000000000 + assign $1\cppr$next[7:0]$13416 8'00000000 + assign $1\mfrr$next[7:0]$13418 8'11111111 + assign $1\irq$next[0:0]$13417 1'0 + assign $1\wb_rd_data$next[31:0]$13420 0 + assign $1\wb_ack$next[0:0]$13419 1'0 + case + assign $1\cppr$next[7:0]$13416 \cppr$2 + assign $1\irq$next[0:0]$13417 \irq$4 + assign $1\mfrr$next[7:0]$13418 \mfrr$3 + assign $1\wb_ack$next[0:0]$13419 \wb_ack$6 + assign $1\wb_rd_data$next[31:0]$13420 \wb_rd_data$5 + assign $1\xisr$next[23:0]$13421 \xisr$1 + end + sync always + update \cppr$next $0\cppr$next[7:0]$13410 + update \irq$next $0\irq$next[0:0]$13411 + update \mfrr$next $0\mfrr$next[7:0]$13412 + update \wb_ack$next $0\wb_ack$next[0:0]$13413 + update \wb_rd_data$next $0\wb_rd_data$next[31:0]$13414 + update \xisr$next $0\xisr$next[23:0]$13415 + end + attribute \src "issuer_ls180.v:181090.3-181117.6" + process $proc$issuer_ls180.v:181090$13422 + assign { } { } + assign { } { } + assign $0\xirr_accept_rd[0:0] $1\xirr_accept_rd[0:0] + attribute \src "issuer_ls180.v:181091.5-181091.29" + switch \initial + attribute \src "issuer_ls180.v:181091.9-181091.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:117" + switch \$23 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\xirr_accept_rd[0:0] $2\xirr_accept_rd[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:119" + switch \icp_wb__we + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign $2\xirr_accept_rd[0:0] 1'0 + attribute \src "issuer_ls180.v:0.0-0.0" + case + assign { } { } + assign $2\xirr_accept_rd[0:0] $3\xirr_accept_rd[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:155" + switch \icp_wb__adr [5:0] + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'000001 + assign { } { } + assign $3\xirr_accept_rd[0:0] $4\xirr_accept_rd[0:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:162" + switch \$25 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\xirr_accept_rd[0:0] 1'1 + case + assign $4\xirr_accept_rd[0:0] 1'0 + end + case + assign $3\xirr_accept_rd[0:0] 1'0 + end + end + case + assign $1\xirr_accept_rd[0:0] 1'0 + end + sync always + update \xirr_accept_rd $0\xirr_accept_rd[0:0] + end + attribute \src "issuer_ls180.v:181118.3-181146.6" + process $proc$issuer_ls180.v:181118$13423 + assign { } { } + assign { } { } + assign $0\be_out[31:0] $1\be_out[31:0] + attribute \src "issuer_ls180.v:181119.5-181119.29" + switch \initial + attribute \src "issuer_ls180.v:181119.9-181119.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:117" + switch \$27 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\be_out[31:0] $2\be_out[31:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:119" + switch \icp_wb__we + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign $2\be_out[31:0] 0 + attribute \src "issuer_ls180.v:0.0-0.0" + case + assign { } { } + assign $2\be_out[31:0] $3\be_out[31:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:155" + switch \icp_wb__adr [5:0] + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'000000 + assign { } { } + assign $3\be_out[31:0] { \cppr \xisr } + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'000001 + assign { } { } + assign $3\be_out[31:0] { \cppr \xisr } + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'000011 + assign $3\be_out[31:0] [23:0] 24'000000000000000000000000 + assign $3\be_out[31:0] [31:24] \mfrr + case + assign $3\be_out[31:0] 0 + end + end + case + assign $1\be_out[31:0] 0 + end + sync always + update \be_out $0\be_out[31:0] + end + attribute \src "issuer_ls180.v:181147.3-181156.6" + process $proc$issuer_ls180.v:181147$13424 + assign { } { } + assign { } { } + assign $0\pending_priority[7:0] $1\pending_priority[7:0] + attribute \src "issuer_ls180.v:181148.5-181148.29" + switch \initial + attribute \src "issuer_ls180.v:181148.9-181148.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:173" + switch \$29 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\pending_priority[7:0] \ics_i_pri + case + assign $1\pending_priority[7:0] 8'11111111 + end + sync always + update \pending_priority $0\pending_priority[7:0] + end + attribute \src "issuer_ls180.v:181157.3-181168.6" + process $proc$issuer_ls180.v:181157$13425 + assign { } { } + assign $0\min_pri[7:0] $1\min_pri[7:0] + attribute \src "issuer_ls180.v:181158.5-181158.29" + switch \initial + attribute \src "issuer_ls180.v:181158.9-181158.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:178" + switch \$31 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\min_pri[7:0] \mfrr + attribute \src "issuer_ls180.v:0.0-0.0" + case + assign { } { } + assign $1\min_pri[7:0] \pending_priority + end + sync always + update \min_pri $0\min_pri[7:0] + end + attribute \src "issuer_ls180.v:181169.3-181177.6" + process $proc$issuer_ls180.v:181169$13426 + assign { } { } + assign { } { } + assign $0\core_irq_o$next[0:0]$13427 $1\core_irq_o$next[0:0]$13428 + attribute \src "issuer_ls180.v:181170.5-181170.29" + switch \initial + attribute \src "issuer_ls180.v:181170.9-181170.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\core_irq_o$next[0:0]$13428 1'0 + case + assign $1\core_irq_o$next[0:0]$13428 \irq + end + sync always + update \core_irq_o$next $0\core_irq_o$next[0:0]$13427 + end + attribute \src "issuer_ls180.v:181178.3-181187.6" + process $proc$issuer_ls180.v:181178$13429 + assign { } { } + assign { } { } + assign $0\icp_wb__dat_r[31:0] $1\icp_wb__dat_r[31:0] + attribute \src "issuer_ls180.v:181179.5-181179.29" + switch \initial + attribute \src "issuer_ls180.v:181179.9-181179.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:97" + switch \icp_wb__ack + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\icp_wb__dat_r[31:0] \wb_rd_data + case + assign $1\icp_wb__dat_r[31:0] 0 + end + sync always + update \icp_wb__dat_r $0\icp_wb__dat_r[31:0] + end + attribute \src "issuer_ls180.v:181188.3-181250.6" + process $proc$issuer_ls180.v:181188$13430 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\mfrr$11[7:0]$13433 $1\mfrr$11[7:0]$13438 + assign $0\wb_ack$14[0:0]$13434 $1\wb_ack$14[0:0]$13439 + assign { } { } + assign { } { } + assign { } { } + assign $0\xisr$9[23:0]$13436 $2\xisr$9[23:0]$13445 + assign $0\cppr$10[7:0]$13431 $4\cppr$10[7:0]$13446 + assign $0\wb_rd_data$13[31:0]$13435 { \be_out [7:0] \be_out [15:8] \be_out [23:16] \be_out [31:24] } + assign $0\irq$12[0:0]$13432 $1\irq$12[0:0]$13447 + attribute \src "issuer_ls180.v:181189.5-181189.29" + switch \initial + attribute \src "issuer_ls180.v:181189.9-181189.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:117" + switch \$15 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign $1\wb_ack$14[0:0]$13439 1'1 + assign $1\cppr$10[7:0]$13437 $2\cppr$10[7:0]$13440 + assign $1\mfrr$11[7:0]$13438 $2\mfrr$11[7:0]$13441 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:119" + switch \icp_wb__we + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign $2\cppr$10[7:0]$13440 $3\cppr$10[7:0]$13442 + assign $2\mfrr$11[7:0]$13441 $3\mfrr$11[7:0]$13443 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:121" + switch \icp_wb__adr [5:0] + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'000000 + assign { } { } + assign $3\mfrr$11[7:0]$13443 \mfrr + assign $3\cppr$10[7:0]$13442 \be_in [31:24] + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'000001 + assign { } { } + assign $3\mfrr$11[7:0]$13443 \mfrr + assign $3\cppr$10[7:0]$13442 \be_in [31:24] + attribute \src "issuer_ls180.v:0.0-0.0" + case 6'000011 + assign $3\cppr$10[7:0]$13442 \cppr + assign { } { } + assign $3\mfrr$11[7:0]$13443 \be_in [31:24] + case + assign $3\cppr$10[7:0]$13442 \cppr + assign $3\mfrr$11[7:0]$13443 \mfrr + end + case + assign $2\cppr$10[7:0]$13440 \cppr + assign $2\mfrr$11[7:0]$13441 \mfrr + end + case + assign $1\cppr$10[7:0]$13437 \cppr + assign $1\mfrr$11[7:0]$13438 \mfrr + assign $1\wb_ack$14[0:0]$13439 1'0 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:173" + switch \$17 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\xisr$9[23:0]$13444 { 20'00000000000000000001 \ics_i_src } + case + assign $1\xisr$9[23:0]$13444 24'000000000000000000000000 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:178" + switch \$19 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $2\xisr$9[23:0]$13445 24'000000000000000000000010 + case + assign $2\xisr$9[23:0]$13445 $1\xisr$9[23:0]$13444 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:185" + switch \xirr_accept_rd + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $4\cppr$10[7:0]$13446 \min_pri + case + assign $4\cppr$10[7:0]$13446 $1\cppr$10[7:0]$13437 + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:195" + switch { \irq \$21 } + attribute \src "issuer_ls180.v:0.0-0.0" + case 2'-1 + assign { } { } + assign $1\irq$12[0:0]$13447 1'1 + case + assign $1\irq$12[0:0]$13447 1'0 + end + sync always + update \cppr$10 $0\cppr$10[7:0]$13431 + update \irq$12 $0\irq$12[0:0]$13432 + update \mfrr$11 $0\mfrr$11[7:0]$13433 + update \wb_ack$14 $0\wb_ack$14[0:0]$13434 + update \wb_rd_data$13 $0\wb_rd_data$13[31:0]$13435 + update \xisr$9 $0\xisr$9[23:0]$13436 + end + connect \$15 $and$issuer_ls180.v:181050$13392_Y + connect \$17 $ne$issuer_ls180.v:181051$13393_Y + connect \$19 $lt$issuer_ls180.v:181052$13394_Y + connect \$21 $lt$issuer_ls180.v:181053$13395_Y + connect \$23 $and$issuer_ls180.v:181054$13396_Y + connect \$25 $eq$issuer_ls180.v:181055$13397_Y + connect \$27 $and$issuer_ls180.v:181056$13398_Y + connect \$29 $ne$issuer_ls180.v:181057$13399_Y + connect \$31 $lt$issuer_ls180.v:181058$13400_Y + connect \$7 $and$issuer_ls180.v:181059$13401_Y + connect { \wb_ack$6 \wb_rd_data$5 \irq$4 \mfrr$3 \cppr$2 \xisr$1 } { \wb_ack$14 \wb_rd_data$13 \irq$12 \mfrr$11 \cppr$10 \xisr$9 } + connect \be_in { \icp_wb__dat_w [7:0] \icp_wb__dat_w [15:8] \icp_wb__dat_w [23:16] \icp_wb__dat_w [31:24] } + connect \icp_wb__ack \$7 +end +attribute \src "issuer_ls180.v:181258.1-182307.10" +attribute \cells_not_processed 1 +attribute \nmigen.hierarchy "test_issuer.xics_ics" +attribute \generator "nMigen" +module \xics_ics + attribute \src "issuer_ls180.v:182188.3-182237.6" + wire width 32 $0\be_out[31:0] + attribute \src "issuer_ls180.v:181899.3-181908.6" + wire width 4 $0\cur_idx0[3:0] + attribute \src "issuer_ls180.v:182108.3-182117.6" + wire width 4 $0\cur_idx10[3:0] + attribute \src "issuer_ls180.v:182128.3-182137.6" + wire width 4 $0\cur_idx11[3:0] + attribute \src "issuer_ls180.v:182148.3-182157.6" + wire width 4 $0\cur_idx12[3:0] + attribute \src "issuer_ls180.v:182168.3-182177.6" + wire width 4 $0\cur_idx13[3:0] + attribute \src "issuer_ls180.v:182238.3-182247.6" + wire width 4 $0\cur_idx14[3:0] + attribute \src "issuer_ls180.v:182258.3-182267.6" + wire width 4 $0\cur_idx15[3:0] + attribute \src "issuer_ls180.v:181919.3-181928.6" + wire width 4 $0\cur_idx1[3:0] + attribute \src "issuer_ls180.v:181939.3-181948.6" + wire width 4 $0\cur_idx2[3:0] + attribute \src "issuer_ls180.v:181959.3-181968.6" + wire width 4 $0\cur_idx3[3:0] + attribute \src "issuer_ls180.v:181988.3-181997.6" + wire width 4 $0\cur_idx4[3:0] + attribute \src "issuer_ls180.v:182008.3-182017.6" + wire width 4 $0\cur_idx5[3:0] + attribute \src "issuer_ls180.v:182028.3-182037.6" + wire width 4 $0\cur_idx6[3:0] + attribute \src "issuer_ls180.v:182048.3-182057.6" + wire width 4 $0\cur_idx7[3:0] + attribute \src "issuer_ls180.v:182068.3-182077.6" + wire width 4 $0\cur_idx8[3:0] + attribute \src "issuer_ls180.v:182088.3-182097.6" + wire width 4 $0\cur_idx9[3:0] + attribute \src "issuer_ls180.v:181889.3-181898.6" + wire width 8 $0\cur_pri0[7:0] + attribute \src "issuer_ls180.v:182098.3-182107.6" + wire width 8 $0\cur_pri10[7:0] + attribute \src "issuer_ls180.v:182118.3-182127.6" + wire width 8 $0\cur_pri11[7:0] + attribute \src "issuer_ls180.v:182138.3-182147.6" + wire width 8 $0\cur_pri12[7:0] + attribute \src "issuer_ls180.v:182158.3-182167.6" + wire width 8 $0\cur_pri13[7:0] + attribute \src "issuer_ls180.v:182178.3-182187.6" + wire width 8 $0\cur_pri14[7:0] + attribute \src "issuer_ls180.v:182248.3-182257.6" + wire width 8 $0\cur_pri15[7:0] + attribute \src "issuer_ls180.v:181909.3-181918.6" + wire width 8 $0\cur_pri1[7:0] + attribute \src "issuer_ls180.v:181929.3-181938.6" + wire width 8 $0\cur_pri2[7:0] + attribute \src "issuer_ls180.v:181949.3-181958.6" + wire width 8 $0\cur_pri3[7:0] + attribute \src "issuer_ls180.v:181969.3-181978.6" + wire width 8 $0\cur_pri4[7:0] + attribute \src "issuer_ls180.v:181998.3-182007.6" + wire width 8 $0\cur_pri5[7:0] + attribute \src "issuer_ls180.v:182018.3-182027.6" + wire width 8 $0\cur_pri6[7:0] + attribute \src "issuer_ls180.v:182038.3-182047.6" + wire width 8 $0\cur_pri7[7:0] + attribute \src "issuer_ls180.v:182058.3-182067.6" + wire width 8 $0\cur_pri8[7:0] + attribute \src "issuer_ls180.v:182078.3-182087.6" + wire width 8 $0\cur_pri9[7:0] + attribute \src "issuer_ls180.v:182268.3-182277.6" + wire $0\ibit[0:0] + attribute \src "issuer_ls180.v:181763.3-181764.25" + wire width 8 $0\icp_o_pri[7:0] + attribute \src "issuer_ls180.v:181761.3-181762.28" + wire width 4 $0\icp_o_src[3:0] + attribute \src "issuer_ls180.v:182287.3-182295.6" + wire $0\ics_wb__ack$next[0:0]$13702 + attribute \src "issuer_ls180.v:181797.3-181798.39" + wire $0\ics_wb__ack[0:0] + attribute \src "issuer_ls180.v:182278.3-182286.6" + wire width 32 $0\ics_wb__dat_r$next[31:0]$13699 + attribute \src "issuer_ls180.v:181799.3-181800.43" + wire width 32 $0\ics_wb__dat_r[31:0] + attribute \src "issuer_ls180.v:181259.7-181259.20" + wire $0\initial[0:0] + attribute \src "issuer_ls180.v:181979.3-181987.6" + wire width 16 $0\int_level_l$next[15:0]$13671 + attribute \src "issuer_ls180.v:181801.3-181802.39" + wire width 16 $0\int_level_l[15:0] + attribute \src "issuer_ls180.v:181803.3-181888.6" + wire width 8 $0\xive0_pri$next[7:0]$13581 + attribute \src "issuer_ls180.v:181765.3-181766.35" + wire width 8 $0\xive0_pri[7:0] + attribute \src "issuer_ls180.v:181803.3-181888.6" + wire width 8 $0\xive10_pri$next[7:0]$13582 + attribute \src "issuer_ls180.v:181785.3-181786.37" + wire width 8 $0\xive10_pri[7:0] + attribute \src "issuer_ls180.v:181803.3-181888.6" + wire width 8 $0\xive11_pri$next[7:0]$13583 + attribute \src "issuer_ls180.v:181787.3-181788.37" + wire width 8 $0\xive11_pri[7:0] + attribute \src "issuer_ls180.v:181803.3-181888.6" + wire width 8 $0\xive12_pri$next[7:0]$13584 + attribute \src "issuer_ls180.v:181789.3-181790.37" + wire width 8 $0\xive12_pri[7:0] + attribute \src "issuer_ls180.v:181803.3-181888.6" + wire width 8 $0\xive13_pri$next[7:0]$13585 + attribute \src "issuer_ls180.v:181791.3-181792.37" + wire width 8 $0\xive13_pri[7:0] + attribute \src "issuer_ls180.v:181803.3-181888.6" + wire width 8 $0\xive14_pri$next[7:0]$13586 + attribute \src "issuer_ls180.v:181793.3-181794.37" + wire width 8 $0\xive14_pri[7:0] + attribute \src "issuer_ls180.v:181803.3-181888.6" + wire width 8 $0\xive15_pri$next[7:0]$13587 + attribute \src "issuer_ls180.v:181795.3-181796.37" + wire width 8 $0\xive15_pri[7:0] + attribute \src "issuer_ls180.v:181803.3-181888.6" + wire width 8 $0\xive1_pri$next[7:0]$13588 + attribute \src "issuer_ls180.v:181767.3-181768.35" + wire width 8 $0\xive1_pri[7:0] + attribute \src "issuer_ls180.v:181803.3-181888.6" + wire width 8 $0\xive2_pri$next[7:0]$13589 + attribute \src "issuer_ls180.v:181769.3-181770.35" + wire width 8 $0\xive2_pri[7:0] + attribute \src "issuer_ls180.v:181803.3-181888.6" + wire width 8 $0\xive3_pri$next[7:0]$13590 + attribute \src "issuer_ls180.v:181771.3-181772.35" + wire width 8 $0\xive3_pri[7:0] + attribute \src "issuer_ls180.v:181803.3-181888.6" + wire width 8 $0\xive4_pri$next[7:0]$13591 + attribute \src "issuer_ls180.v:181773.3-181774.35" + wire width 8 $0\xive4_pri[7:0] + attribute \src "issuer_ls180.v:181803.3-181888.6" + wire width 8 $0\xive5_pri$next[7:0]$13592 + attribute \src "issuer_ls180.v:181775.3-181776.35" + wire width 8 $0\xive5_pri[7:0] + attribute \src "issuer_ls180.v:181803.3-181888.6" + wire width 8 $0\xive6_pri$next[7:0]$13593 + attribute \src "issuer_ls180.v:181777.3-181778.35" + wire width 8 $0\xive6_pri[7:0] + attribute \src "issuer_ls180.v:181803.3-181888.6" + wire width 8 $0\xive7_pri$next[7:0]$13594 + attribute \src "issuer_ls180.v:181779.3-181780.35" + wire width 8 $0\xive7_pri[7:0] + attribute \src "issuer_ls180.v:181803.3-181888.6" + wire width 8 $0\xive8_pri$next[7:0]$13595 + attribute \src "issuer_ls180.v:181781.3-181782.35" + wire width 8 $0\xive8_pri[7:0] + attribute \src "issuer_ls180.v:181803.3-181888.6" + wire width 8 $0\xive9_pri$next[7:0]$13596 + attribute \src "issuer_ls180.v:181783.3-181784.35" + wire width 8 $0\xive9_pri[7:0] + attribute \src "issuer_ls180.v:182188.3-182237.6" + wire width 32 $1\be_out[31:0] + attribute \src "issuer_ls180.v:181899.3-181908.6" + wire width 4 $1\cur_idx0[3:0] + attribute \src "issuer_ls180.v:182108.3-182117.6" + wire width 4 $1\cur_idx10[3:0] + attribute \src "issuer_ls180.v:182128.3-182137.6" + wire width 4 $1\cur_idx11[3:0] + attribute \src "issuer_ls180.v:182148.3-182157.6" + wire width 4 $1\cur_idx12[3:0] + attribute \src "issuer_ls180.v:182168.3-182177.6" + wire width 4 $1\cur_idx13[3:0] + attribute \src "issuer_ls180.v:182238.3-182247.6" + wire width 4 $1\cur_idx14[3:0] + attribute \src "issuer_ls180.v:182258.3-182267.6" + wire width 4 $1\cur_idx15[3:0] + attribute \src "issuer_ls180.v:181919.3-181928.6" + wire width 4 $1\cur_idx1[3:0] + attribute \src "issuer_ls180.v:181939.3-181948.6" + wire width 4 $1\cur_idx2[3:0] + attribute \src "issuer_ls180.v:181959.3-181968.6" + wire width 4 $1\cur_idx3[3:0] + attribute \src "issuer_ls180.v:181988.3-181997.6" + wire width 4 $1\cur_idx4[3:0] + attribute \src "issuer_ls180.v:182008.3-182017.6" + wire width 4 $1\cur_idx5[3:0] + attribute \src "issuer_ls180.v:182028.3-182037.6" + wire width 4 $1\cur_idx6[3:0] + attribute \src "issuer_ls180.v:182048.3-182057.6" + wire width 4 $1\cur_idx7[3:0] + attribute \src "issuer_ls180.v:182068.3-182077.6" + wire width 4 $1\cur_idx8[3:0] + attribute \src "issuer_ls180.v:182088.3-182097.6" + wire width 4 $1\cur_idx9[3:0] + attribute \src "issuer_ls180.v:181889.3-181898.6" + wire width 8 $1\cur_pri0[7:0] + attribute \src "issuer_ls180.v:182098.3-182107.6" + wire width 8 $1\cur_pri10[7:0] + attribute \src "issuer_ls180.v:182118.3-182127.6" + wire width 8 $1\cur_pri11[7:0] + attribute \src "issuer_ls180.v:182138.3-182147.6" + wire width 8 $1\cur_pri12[7:0] + attribute \src "issuer_ls180.v:182158.3-182167.6" + wire width 8 $1\cur_pri13[7:0] + attribute \src "issuer_ls180.v:182178.3-182187.6" + wire width 8 $1\cur_pri14[7:0] + attribute \src "issuer_ls180.v:182248.3-182257.6" + wire width 8 $1\cur_pri15[7:0] + attribute \src "issuer_ls180.v:181909.3-181918.6" + wire width 8 $1\cur_pri1[7:0] + attribute \src "issuer_ls180.v:181929.3-181938.6" + wire width 8 $1\cur_pri2[7:0] + attribute \src "issuer_ls180.v:181949.3-181958.6" + wire width 8 $1\cur_pri3[7:0] + attribute \src "issuer_ls180.v:181969.3-181978.6" + wire width 8 $1\cur_pri4[7:0] + attribute \src "issuer_ls180.v:181998.3-182007.6" + wire width 8 $1\cur_pri5[7:0] + attribute \src "issuer_ls180.v:182018.3-182027.6" + wire width 8 $1\cur_pri6[7:0] + attribute \src "issuer_ls180.v:182038.3-182047.6" + wire width 8 $1\cur_pri7[7:0] + attribute \src "issuer_ls180.v:182058.3-182067.6" + wire width 8 $1\cur_pri8[7:0] + attribute \src "issuer_ls180.v:182078.3-182087.6" + wire width 8 $1\cur_pri9[7:0] + attribute \src "issuer_ls180.v:182268.3-182277.6" + wire $1\ibit[0:0] + attribute \src "issuer_ls180.v:181540.13-181540.30" + wire width 8 $1\icp_o_pri[7:0] + attribute \src "issuer_ls180.v:181545.13-181545.29" + wire width 4 $1\icp_o_src[3:0] + attribute \src "issuer_ls180.v:182287.3-182295.6" + wire $1\ics_wb__ack$next[0:0]$13703 + attribute \src "issuer_ls180.v:181554.7-181554.25" + wire $1\ics_wb__ack[0:0] + attribute \src "issuer_ls180.v:182278.3-182286.6" + wire width 32 $1\ics_wb__dat_r$next[31:0]$13700 + attribute \src "issuer_ls180.v:181563.14-181563.35" + wire width 32 $1\ics_wb__dat_r[31:0] + attribute \src "issuer_ls180.v:181979.3-181987.6" + wire width 16 $1\int_level_l$next[15:0]$13672 + attribute \src "issuer_ls180.v:181575.14-181575.36" + wire width 16 $1\int_level_l[15:0] + attribute \src "issuer_ls180.v:181803.3-181888.6" + wire width 8 $1\xive0_pri$next[7:0]$13597 + attribute \src "issuer_ls180.v:181595.13-181595.30" + wire width 8 $1\xive0_pri[7:0] + attribute \src "issuer_ls180.v:181803.3-181888.6" + wire width 8 $1\xive10_pri$next[7:0]$13598 + attribute \src "issuer_ls180.v:181599.13-181599.31" + wire width 8 $1\xive10_pri[7:0] + attribute \src "issuer_ls180.v:181803.3-181888.6" + wire width 8 $1\xive11_pri$next[7:0]$13599 + attribute \src "issuer_ls180.v:181603.13-181603.31" + wire width 8 $1\xive11_pri[7:0] + attribute \src "issuer_ls180.v:181803.3-181888.6" + wire width 8 $1\xive12_pri$next[7:0]$13600 + attribute \src "issuer_ls180.v:181607.13-181607.31" + wire width 8 $1\xive12_pri[7:0] + attribute \src "issuer_ls180.v:181803.3-181888.6" + wire width 8 $1\xive13_pri$next[7:0]$13601 + attribute \src "issuer_ls180.v:181611.13-181611.31" + wire width 8 $1\xive13_pri[7:0] + attribute \src "issuer_ls180.v:181803.3-181888.6" + wire width 8 $1\xive14_pri$next[7:0]$13602 + attribute \src "issuer_ls180.v:181615.13-181615.31" + wire width 8 $1\xive14_pri[7:0] + attribute \src "issuer_ls180.v:181803.3-181888.6" + wire width 8 $1\xive15_pri$next[7:0]$13603 + attribute \src "issuer_ls180.v:181619.13-181619.31" + wire width 8 $1\xive15_pri[7:0] + attribute \src "issuer_ls180.v:181803.3-181888.6" + wire width 8 $1\xive1_pri$next[7:0]$13604 + attribute \src "issuer_ls180.v:181623.13-181623.30" + wire width 8 $1\xive1_pri[7:0] + attribute \src "issuer_ls180.v:181803.3-181888.6" + wire width 8 $1\xive2_pri$next[7:0]$13605 + attribute \src "issuer_ls180.v:181627.13-181627.30" + wire width 8 $1\xive2_pri[7:0] + attribute \src "issuer_ls180.v:181803.3-181888.6" + wire width 8 $1\xive3_pri$next[7:0]$13606 + attribute \src "issuer_ls180.v:181631.13-181631.30" + wire width 8 $1\xive3_pri[7:0] + attribute \src "issuer_ls180.v:181803.3-181888.6" + wire width 8 $1\xive4_pri$next[7:0]$13607 + attribute \src "issuer_ls180.v:181635.13-181635.30" + wire width 8 $1\xive4_pri[7:0] + attribute \src "issuer_ls180.v:181803.3-181888.6" + wire width 8 $1\xive5_pri$next[7:0]$13608 + attribute \src "issuer_ls180.v:181639.13-181639.30" + wire width 8 $1\xive5_pri[7:0] + attribute \src "issuer_ls180.v:181803.3-181888.6" + wire width 8 $1\xive6_pri$next[7:0]$13609 + attribute \src "issuer_ls180.v:181643.13-181643.30" + wire width 8 $1\xive6_pri[7:0] + attribute \src "issuer_ls180.v:181803.3-181888.6" + wire width 8 $1\xive7_pri$next[7:0]$13610 + attribute \src "issuer_ls180.v:181647.13-181647.30" + wire width 8 $1\xive7_pri[7:0] + attribute \src "issuer_ls180.v:181803.3-181888.6" + wire width 8 $1\xive8_pri$next[7:0]$13611 + attribute \src "issuer_ls180.v:181651.13-181651.30" + wire width 8 $1\xive8_pri[7:0] + attribute \src "issuer_ls180.v:181803.3-181888.6" + wire width 8 $1\xive9_pri$next[7:0]$13612 + attribute \src "issuer_ls180.v:181655.13-181655.30" + wire width 8 $1\xive9_pri[7:0] + attribute \src "issuer_ls180.v:182188.3-182237.6" + wire width 32 $2\be_out[31:0] + attribute \src "issuer_ls180.v:181803.3-181888.6" + wire width 8 $2\xive0_pri$next[7:0]$13613 + attribute \src "issuer_ls180.v:181803.3-181888.6" + wire width 8 $2\xive10_pri$next[7:0]$13614 + attribute \src "issuer_ls180.v:181803.3-181888.6" + wire width 8 $2\xive11_pri$next[7:0]$13615 + attribute \src "issuer_ls180.v:181803.3-181888.6" + wire width 8 $2\xive12_pri$next[7:0]$13616 + attribute \src "issuer_ls180.v:181803.3-181888.6" + wire width 8 $2\xive13_pri$next[7:0]$13617 + attribute \src "issuer_ls180.v:181803.3-181888.6" + wire width 8 $2\xive14_pri$next[7:0]$13618 + attribute \src "issuer_ls180.v:181803.3-181888.6" + wire width 8 $2\xive15_pri$next[7:0]$13619 + attribute \src "issuer_ls180.v:181803.3-181888.6" + wire width 8 $2\xive1_pri$next[7:0]$13620 + attribute \src "issuer_ls180.v:181803.3-181888.6" + wire width 8 $2\xive2_pri$next[7:0]$13621 + attribute \src "issuer_ls180.v:181803.3-181888.6" + wire width 8 $2\xive3_pri$next[7:0]$13622 + attribute \src "issuer_ls180.v:181803.3-181888.6" + wire width 8 $2\xive4_pri$next[7:0]$13623 + attribute \src "issuer_ls180.v:181803.3-181888.6" + wire width 8 $2\xive5_pri$next[7:0]$13624 + attribute \src "issuer_ls180.v:181803.3-181888.6" + wire width 8 $2\xive6_pri$next[7:0]$13625 + attribute \src "issuer_ls180.v:181803.3-181888.6" + wire width 8 $2\xive7_pri$next[7:0]$13626 + attribute \src "issuer_ls180.v:181803.3-181888.6" + wire width 8 $2\xive8_pri$next[7:0]$13627 + attribute \src "issuer_ls180.v:181803.3-181888.6" + wire width 8 $2\xive9_pri$next[7:0]$13628 + attribute \src "issuer_ls180.v:181803.3-181888.6" + wire width 8 $3\xive0_pri$next[7:0]$13629 + attribute \src "issuer_ls180.v:181803.3-181888.6" + wire width 8 $3\xive10_pri$next[7:0]$13630 + attribute \src "issuer_ls180.v:181803.3-181888.6" + wire width 8 $3\xive11_pri$next[7:0]$13631 + attribute \src "issuer_ls180.v:181803.3-181888.6" + wire width 8 $3\xive12_pri$next[7:0]$13632 + attribute \src "issuer_ls180.v:181803.3-181888.6" + wire width 8 $3\xive13_pri$next[7:0]$13633 + attribute \src "issuer_ls180.v:181803.3-181888.6" + wire width 8 $3\xive14_pri$next[7:0]$13634 + attribute \src "issuer_ls180.v:181803.3-181888.6" + wire width 8 $3\xive15_pri$next[7:0]$13635 + attribute \src "issuer_ls180.v:181803.3-181888.6" + wire width 8 $3\xive1_pri$next[7:0]$13636 + attribute \src "issuer_ls180.v:181803.3-181888.6" + wire width 8 $3\xive2_pri$next[7:0]$13637 + attribute \src "issuer_ls180.v:181803.3-181888.6" + wire width 8 $3\xive3_pri$next[7:0]$13638 + attribute \src "issuer_ls180.v:181803.3-181888.6" + wire width 8 $3\xive4_pri$next[7:0]$13639 + attribute \src "issuer_ls180.v:181803.3-181888.6" + wire width 8 $3\xive5_pri$next[7:0]$13640 + attribute \src "issuer_ls180.v:181803.3-181888.6" + wire width 8 $3\xive6_pri$next[7:0]$13641 + attribute \src "issuer_ls180.v:181803.3-181888.6" + wire width 8 $3\xive7_pri$next[7:0]$13642 + attribute \src "issuer_ls180.v:181803.3-181888.6" + wire width 8 $3\xive8_pri$next[7:0]$13643 + attribute \src "issuer_ls180.v:181803.3-181888.6" + wire width 8 $3\xive9_pri$next[7:0]$13644 + attribute \src "issuer_ls180.v:181803.3-181888.6" + wire width 8 $4\xive0_pri$next[7:0]$13645 + attribute \src "issuer_ls180.v:181803.3-181888.6" + wire width 8 $4\xive10_pri$next[7:0]$13646 + attribute \src "issuer_ls180.v:181803.3-181888.6" + wire width 8 $4\xive11_pri$next[7:0]$13647 + attribute \src "issuer_ls180.v:181803.3-181888.6" + wire width 8 $4\xive12_pri$next[7:0]$13648 + attribute \src "issuer_ls180.v:181803.3-181888.6" + wire width 8 $4\xive13_pri$next[7:0]$13649 + attribute \src "issuer_ls180.v:181803.3-181888.6" + wire width 8 $4\xive14_pri$next[7:0]$13650 + attribute \src "issuer_ls180.v:181803.3-181888.6" + wire width 8 $4\xive15_pri$next[7:0]$13651 + attribute \src "issuer_ls180.v:181803.3-181888.6" + wire width 8 $4\xive1_pri$next[7:0]$13652 + attribute \src "issuer_ls180.v:181803.3-181888.6" + wire width 8 $4\xive2_pri$next[7:0]$13653 + attribute \src "issuer_ls180.v:181803.3-181888.6" + wire width 8 $4\xive3_pri$next[7:0]$13654 + attribute \src "issuer_ls180.v:181803.3-181888.6" + wire width 8 $4\xive4_pri$next[7:0]$13655 + attribute \src "issuer_ls180.v:181803.3-181888.6" + wire width 8 $4\xive5_pri$next[7:0]$13656 + attribute \src "issuer_ls180.v:181803.3-181888.6" + wire width 8 $4\xive6_pri$next[7:0]$13657 + attribute \src "issuer_ls180.v:181803.3-181888.6" + wire width 8 $4\xive7_pri$next[7:0]$13658 + attribute \src "issuer_ls180.v:181803.3-181888.6" + wire width 8 $4\xive8_pri$next[7:0]$13659 + attribute \src "issuer_ls180.v:181803.3-181888.6" + wire width 8 $4\xive9_pri$next[7:0]$13660 + attribute \src "issuer_ls180.v:181660.19-181660.113" + wire $and$issuer_ls180.v:181660$13458_Y + attribute \src "issuer_ls180.v:181662.19-181662.114" + wire $and$issuer_ls180.v:181662$13460_Y + attribute \src "issuer_ls180.v:181664.19-181664.114" + wire $and$issuer_ls180.v:181664$13462_Y + attribute \src "issuer_ls180.v:181666.19-181666.114" + wire $and$issuer_ls180.v:181666$13464_Y + attribute \src "issuer_ls180.v:181668.19-181668.114" + wire $and$issuer_ls180.v:181668$13466_Y + attribute \src "issuer_ls180.v:181670.19-181670.114" + wire $and$issuer_ls180.v:181670$13468_Y + attribute \src "issuer_ls180.v:181672.19-181672.114" + wire $and$issuer_ls180.v:181672$13470_Y + attribute \src "issuer_ls180.v:181675.19-181675.114" + wire $and$issuer_ls180.v:181675$13473_Y + attribute \src "issuer_ls180.v:181677.19-181677.114" + wire $and$issuer_ls180.v:181677$13475_Y + attribute \src "issuer_ls180.v:181679.19-181679.114" + wire $and$issuer_ls180.v:181679$13477_Y + attribute \src "issuer_ls180.v:181682.19-181682.114" + wire $and$issuer_ls180.v:181682$13480_Y + attribute \src "issuer_ls180.v:181684.19-181684.114" + wire $and$issuer_ls180.v:181684$13482_Y + attribute \src "issuer_ls180.v:181686.19-181686.114" + wire $and$issuer_ls180.v:181686$13484_Y + attribute \src "issuer_ls180.v:181688.19-181688.114" + wire $and$issuer_ls180.v:181688$13486_Y + attribute \src "issuer_ls180.v:181690.19-181690.115" + wire $and$issuer_ls180.v:181690$13488_Y + attribute \src "issuer_ls180.v:181692.19-181692.115" + wire $and$issuer_ls180.v:181692$13490_Y + attribute \src "issuer_ls180.v:181694.19-181694.115" + wire $and$issuer_ls180.v:181694$13492_Y + attribute \src "issuer_ls180.v:181697.19-181697.115" + wire $and$issuer_ls180.v:181697$13495_Y + attribute \src "issuer_ls180.v:181699.19-181699.115" + wire $and$issuer_ls180.v:181699$13497_Y + attribute \src "issuer_ls180.v:181701.19-181701.115" + wire $and$issuer_ls180.v:181701$13499_Y + attribute \src "issuer_ls180.v:181704.19-181704.115" + wire $and$issuer_ls180.v:181704$13502_Y + attribute \src "issuer_ls180.v:181706.19-181706.115" + wire $and$issuer_ls180.v:181706$13504_Y + attribute \src "issuer_ls180.v:181708.19-181708.115" + wire $and$issuer_ls180.v:181708$13506_Y + attribute \src "issuer_ls180.v:181710.19-181710.115" + wire $and$issuer_ls180.v:181710$13508_Y + attribute \src "issuer_ls180.v:181712.19-181712.115" + wire $and$issuer_ls180.v:181712$13510_Y + attribute \src "issuer_ls180.v:181715.19-181715.115" + wire $and$issuer_ls180.v:181715$13513_Y + attribute \src "issuer_ls180.v:181739.17-181739.115" + wire $and$issuer_ls180.v:181739$13537_Y + attribute \src "issuer_ls180.v:181747.18-181747.112" + wire $and$issuer_ls180.v:181747$13545_Y + attribute \src "issuer_ls180.v:181749.18-181749.112" + wire $and$issuer_ls180.v:181749$13547_Y + attribute \src "issuer_ls180.v:181751.18-181751.112" + wire $and$issuer_ls180.v:181751$13549_Y + attribute \src "issuer_ls180.v:181753.18-181753.112" + wire $and$issuer_ls180.v:181753$13551_Y + attribute \src "issuer_ls180.v:181756.18-181756.112" + wire $and$issuer_ls180.v:181756$13554_Y + attribute \src "issuer_ls180.v:181758.18-181758.112" + wire $and$issuer_ls180.v:181758$13556_Y + attribute \src "issuer_ls180.v:181760.18-181760.112" + wire $and$issuer_ls180.v:181760$13558_Y + attribute \src "issuer_ls180.v:181674.18-181674.109" + wire $eq$issuer_ls180.v:181674$13472_Y + attribute \src "issuer_ls180.v:181696.18-181696.109" + wire $eq$issuer_ls180.v:181696$13494_Y + attribute \src "issuer_ls180.v:181713.17-181713.114" + wire $eq$issuer_ls180.v:181713$13511_Y + attribute \src "issuer_ls180.v:181716.19-181716.110" + wire $eq$issuer_ls180.v:181716$13514_Y + attribute \src "issuer_ls180.v:181718.18-181718.109" + wire $eq$issuer_ls180.v:181718$13516_Y + attribute \src "issuer_ls180.v:181720.18-181720.109" + wire $eq$issuer_ls180.v:181720$13518_Y + attribute \src "issuer_ls180.v:181722.18-181722.109" + wire $eq$issuer_ls180.v:181722$13520_Y + attribute \src "issuer_ls180.v:181724.18-181724.109" + wire $eq$issuer_ls180.v:181724$13522_Y + attribute \src "issuer_ls180.v:181726.18-181726.109" + wire $eq$issuer_ls180.v:181726$13524_Y + attribute \src "issuer_ls180.v:181728.17-181728.114" + wire $eq$issuer_ls180.v:181728$13526_Y + attribute \src "issuer_ls180.v:181729.18-181729.109" + wire $eq$issuer_ls180.v:181729$13527_Y + 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\A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \xive0_pri + connect \B \max_pri + connect \Y $lt$issuer_ls180.v:181748$13546_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" + cell $lt $lt$issuer_ls180.v:181750$13548 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \xive0_pri + connect \B \max_pri + connect \Y $lt$issuer_ls180.v:181750$13548_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" + cell $lt $lt$issuer_ls180.v:181752$13550 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \xive1_pri + connect \B \cur_pri0 + connect \Y $lt$issuer_ls180.v:181752$13550_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" + cell $lt $lt$issuer_ls180.v:181754$13552 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \xive1_pri + connect \B \cur_pri0 + connect \Y $lt$issuer_ls180.v:181754$13552_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" + cell $lt $lt$issuer_ls180.v:181757$13555 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \xive2_pri + connect \B \cur_pri1 + connect \Y $lt$issuer_ls180.v:181757$13555_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:251" + cell $lt $lt$issuer_ls180.v:181759$13557 + parameter \A_SIGNED 0 + parameter \A_WIDTH 8 + parameter \B_SIGNED 0 + parameter \B_WIDTH 8 + parameter \Y_WIDTH 1 + connect \A \xive2_pri + connect \B \cur_pri1 + connect \Y $lt$issuer_ls180.v:181759$13557_Y + end + attribute \src "issuer_ls180.v:181746.18-181746.40" + cell $shr $shr$issuer_ls180.v:181746$13544 + parameter \A_SIGNED 0 + parameter \A_WIDTH 16 + parameter \B_SIGNED 0 + parameter \B_WIDTH 4 + parameter \Y_WIDTH 16 + connect \A \int_level_l + connect \B \reg_idx + connect \Y $shr$issuer_ls180.v:181746$13544_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" + cell $mux $ternary$issuer_ls180.v:181658$13456 + parameter \WIDTH 8 + connect \A \xive0_pri + connect \B 8'11111111 + connect \S \$8 + connect \Y $ternary$issuer_ls180.v:181658$13456_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" + cell $mux $ternary$issuer_ls180.v:181680$13478 + parameter \WIDTH 8 + connect \A \xive1_pri + connect \B 8'11111111 + connect \S \$12 + connect \Y $ternary$issuer_ls180.v:181680$13478_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" + cell $mux $ternary$issuer_ls180.v:181702$13500 + parameter \WIDTH 8 + connect \A \xive2_pri + connect \B 8'11111111 + connect \S \$16 + connect \Y $ternary$issuer_ls180.v:181702$13500_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" + cell $mux $ternary$issuer_ls180.v:181717$13515 + parameter \WIDTH 8 + connect \A \cur_pri15 + connect \B 8'11111111 + connect \S \$204 + connect \Y $ternary$issuer_ls180.v:181717$13515_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" + cell $mux $ternary$issuer_ls180.v:181719$13517 + parameter \WIDTH 8 + connect \A \xive3_pri + connect \B 8'11111111 + connect \S \$20 + connect \Y $ternary$issuer_ls180.v:181719$13517_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" + cell $mux $ternary$issuer_ls180.v:181721$13519 + parameter \WIDTH 8 + connect \A \xive4_pri + connect \B 8'11111111 + connect \S \$24 + connect \Y $ternary$issuer_ls180.v:181721$13519_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" + cell $mux $ternary$issuer_ls180.v:181723$13521 + parameter \WIDTH 8 + connect \A \xive5_pri + connect \B 8'11111111 + connect \S \$28 + connect \Y $ternary$issuer_ls180.v:181723$13521_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" + cell $mux $ternary$issuer_ls180.v:181725$13523 + parameter \WIDTH 8 + connect \A \xive6_pri + connect \B 8'11111111 + connect \S \$32 + connect \Y $ternary$issuer_ls180.v:181725$13523_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" + cell $mux $ternary$issuer_ls180.v:181727$13525 + parameter \WIDTH 8 + connect \A \xive7_pri + connect \B 8'11111111 + connect \S \$36 + connect \Y $ternary$issuer_ls180.v:181727$13525_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" + cell $mux $ternary$issuer_ls180.v:181730$13528 + parameter \WIDTH 8 + connect \A \xive8_pri + connect \B 8'11111111 + connect \S \$40 + connect \Y $ternary$issuer_ls180.v:181730$13528_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" + cell $mux $ternary$issuer_ls180.v:181732$13530 + parameter \WIDTH 8 + connect \A \xive9_pri + connect \B 8'11111111 + connect \S \$44 + connect \Y $ternary$issuer_ls180.v:181732$13530_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" + cell $mux $ternary$issuer_ls180.v:181734$13532 + parameter \WIDTH 8 + connect \A \xive10_pri + connect \B 8'11111111 + connect \S \$48 + connect \Y $ternary$issuer_ls180.v:181734$13532_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" + cell $mux $ternary$issuer_ls180.v:181736$13534 + parameter \WIDTH 8 + connect \A \xive11_pri + connect \B 8'11111111 + connect \S \$52 + connect \Y $ternary$issuer_ls180.v:181736$13534_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" + cell $mux $ternary$issuer_ls180.v:181738$13536 + parameter \WIDTH 8 + connect \A \xive12_pri + connect \B 8'11111111 + connect \S \$56 + connect \Y $ternary$issuer_ls180.v:181738$13536_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" + cell $mux $ternary$issuer_ls180.v:181741$13539 + parameter \WIDTH 8 + connect \A \xive13_pri + connect \B 8'11111111 + connect \S \$60 + connect \Y $ternary$issuer_ls180.v:181741$13539_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" + cell $mux $ternary$issuer_ls180.v:181743$13541 + parameter \WIDTH 8 + connect \A \xive14_pri + connect \B 8'11111111 + connect \S \$64 + connect \Y $ternary$issuer_ls180.v:181743$13541_Y + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" + cell $mux $ternary$issuer_ls180.v:181745$13543 + parameter \WIDTH 8 + connect \A \xive15_pri + connect \B 8'11111111 + connect \S \$68 + connect \Y $ternary$issuer_ls180.v:181745$13543_Y + end + attribute \src "issuer_ls180.v:181259.7-181259.20" + process $proc$issuer_ls180.v:181259$13704 + assign { } { } + assign $0\initial[0:0] 1'0 + sync always + update \initial $0\initial[0:0] + sync init + end + attribute \src "issuer_ls180.v:181540.13-181540.30" + process $proc$issuer_ls180.v:181540$13705 + assign { } { } + assign $1\icp_o_pri[7:0] 8'00000000 + sync always + sync init + update \icp_o_pri $1\icp_o_pri[7:0] + end + attribute \src "issuer_ls180.v:181545.13-181545.29" + process $proc$issuer_ls180.v:181545$13706 + assign { } { } + assign $1\icp_o_src[3:0] 4'0000 + sync always + sync init + update \icp_o_src $1\icp_o_src[3:0] + end + attribute \src "issuer_ls180.v:181554.7-181554.25" + process $proc$issuer_ls180.v:181554$13707 + assign { } { } + assign $1\ics_wb__ack[0:0] 1'0 + sync always + sync init + update \ics_wb__ack $1\ics_wb__ack[0:0] + end + attribute \src "issuer_ls180.v:181563.14-181563.35" + process $proc$issuer_ls180.v:181563$13708 + assign { } { } + assign $1\ics_wb__dat_r[31:0] 0 + sync always + sync init + update \ics_wb__dat_r $1\ics_wb__dat_r[31:0] + end + attribute \src "issuer_ls180.v:181575.14-181575.36" + process $proc$issuer_ls180.v:181575$13709 + assign { } { } + assign $1\int_level_l[15:0] 16'0000000000000000 + sync always + sync init + update \int_level_l $1\int_level_l[15:0] + end + attribute \src "issuer_ls180.v:181595.13-181595.30" + process $proc$issuer_ls180.v:181595$13710 + assign { } { } + assign $1\xive0_pri[7:0] 8'11111111 + sync always + sync init + update \xive0_pri $1\xive0_pri[7:0] + end + attribute \src "issuer_ls180.v:181599.13-181599.31" + process $proc$issuer_ls180.v:181599$13711 + assign { } { } + assign $1\xive10_pri[7:0] 8'11111111 + sync always + sync init + update \xive10_pri $1\xive10_pri[7:0] + end + attribute \src "issuer_ls180.v:181603.13-181603.31" + process $proc$issuer_ls180.v:181603$13712 + assign { } { } + assign $1\xive11_pri[7:0] 8'11111111 + sync always + sync init + update \xive11_pri $1\xive11_pri[7:0] + end + attribute \src "issuer_ls180.v:181607.13-181607.31" + process $proc$issuer_ls180.v:181607$13713 + assign { } { } + assign $1\xive12_pri[7:0] 8'11111111 + sync always + sync init + update \xive12_pri $1\xive12_pri[7:0] + end + attribute \src "issuer_ls180.v:181611.13-181611.31" + process $proc$issuer_ls180.v:181611$13714 + assign { } { } + assign $1\xive13_pri[7:0] 8'11111111 + sync always + sync init + update \xive13_pri $1\xive13_pri[7:0] + end + attribute \src "issuer_ls180.v:181615.13-181615.31" + process $proc$issuer_ls180.v:181615$13715 + assign { } { } + assign $1\xive14_pri[7:0] 8'11111111 + sync always + sync init + update \xive14_pri $1\xive14_pri[7:0] + end + attribute \src "issuer_ls180.v:181619.13-181619.31" + process $proc$issuer_ls180.v:181619$13716 + assign { } { } + assign $1\xive15_pri[7:0] 8'11111111 + sync always + sync init + update \xive15_pri $1\xive15_pri[7:0] + end + attribute \src "issuer_ls180.v:181623.13-181623.30" + process $proc$issuer_ls180.v:181623$13717 + assign { } { } + assign $1\xive1_pri[7:0] 8'11111111 + sync always + sync init + update \xive1_pri $1\xive1_pri[7:0] + end + attribute \src "issuer_ls180.v:181627.13-181627.30" + process $proc$issuer_ls180.v:181627$13718 + assign { } { } + assign $1\xive2_pri[7:0] 8'11111111 + sync always + sync init + update \xive2_pri $1\xive2_pri[7:0] + end + attribute \src "issuer_ls180.v:181631.13-181631.30" + process $proc$issuer_ls180.v:181631$13719 + assign { } { } + assign $1\xive3_pri[7:0] 8'11111111 + sync always + sync init + update \xive3_pri $1\xive3_pri[7:0] + end + attribute \src "issuer_ls180.v:181635.13-181635.30" + process $proc$issuer_ls180.v:181635$13720 + assign { } { } + assign $1\xive4_pri[7:0] 8'11111111 + sync always + sync init + update \xive4_pri $1\xive4_pri[7:0] + end + attribute \src "issuer_ls180.v:181639.13-181639.30" + process $proc$issuer_ls180.v:181639$13721 + assign { } { } + assign $1\xive5_pri[7:0] 8'11111111 + sync always + sync init + update \xive5_pri $1\xive5_pri[7:0] + end + attribute \src "issuer_ls180.v:181643.13-181643.30" + process $proc$issuer_ls180.v:181643$13722 + assign { } { } + assign $1\xive6_pri[7:0] 8'11111111 + sync always + sync init + update \xive6_pri $1\xive6_pri[7:0] + end + attribute \src "issuer_ls180.v:181647.13-181647.30" + process $proc$issuer_ls180.v:181647$13723 + assign { } { } + assign $1\xive7_pri[7:0] 8'11111111 + sync always + sync init + update \xive7_pri $1\xive7_pri[7:0] + end + attribute \src "issuer_ls180.v:181651.13-181651.30" + process $proc$issuer_ls180.v:181651$13724 + assign { } { } + assign $1\xive8_pri[7:0] 8'11111111 + sync always + sync init + update \xive8_pri $1\xive8_pri[7:0] + end + attribute \src "issuer_ls180.v:181655.13-181655.30" + process $proc$issuer_ls180.v:181655$13725 + assign { } { } + assign $1\xive9_pri[7:0] 8'11111111 + sync always + sync init + update \xive9_pri $1\xive9_pri[7:0] + end + attribute \src "issuer_ls180.v:181761.3-181762.28" + process $proc$issuer_ls180.v:181761$13559 + assign { } { } + assign $0\icp_o_src[3:0] \cur_idx15 + sync posedge \clk + update \icp_o_src $0\icp_o_src[3:0] + end + attribute \src "issuer_ls180.v:181763.3-181764.25" + process $proc$issuer_ls180.v:181763$13560 + assign { } { } + assign $0\icp_o_pri[7:0] \$203 + sync posedge \clk + update \icp_o_pri $0\icp_o_pri[7:0] + end + attribute \src "issuer_ls180.v:181765.3-181766.35" + process $proc$issuer_ls180.v:181765$13561 + assign { } { } + assign $0\xive0_pri[7:0] \xive0_pri$next + sync posedge \clk + update \xive0_pri $0\xive0_pri[7:0] + end + attribute \src "issuer_ls180.v:181767.3-181768.35" + process $proc$issuer_ls180.v:181767$13562 + assign { } { } + assign $0\xive1_pri[7:0] \xive1_pri$next + sync posedge \clk + update \xive1_pri $0\xive1_pri[7:0] + end + attribute \src "issuer_ls180.v:181769.3-181770.35" + process $proc$issuer_ls180.v:181769$13563 + assign { } { } + assign $0\xive2_pri[7:0] \xive2_pri$next + sync posedge \clk + update \xive2_pri $0\xive2_pri[7:0] + end + attribute \src "issuer_ls180.v:181771.3-181772.35" + process $proc$issuer_ls180.v:181771$13564 + assign { } { } + assign $0\xive3_pri[7:0] \xive3_pri$next + sync posedge \clk + update \xive3_pri $0\xive3_pri[7:0] + end + attribute \src "issuer_ls180.v:181773.3-181774.35" + process $proc$issuer_ls180.v:181773$13565 + assign { } { } + assign $0\xive4_pri[7:0] \xive4_pri$next + sync posedge \clk + update \xive4_pri $0\xive4_pri[7:0] + end + attribute \src "issuer_ls180.v:181775.3-181776.35" + process $proc$issuer_ls180.v:181775$13566 + assign { } { } + assign $0\xive5_pri[7:0] \xive5_pri$next + sync posedge \clk + update \xive5_pri $0\xive5_pri[7:0] + end + attribute \src "issuer_ls180.v:181777.3-181778.35" + process $proc$issuer_ls180.v:181777$13567 + assign { } { } + assign $0\xive6_pri[7:0] \xive6_pri$next + sync posedge \clk + update \xive6_pri $0\xive6_pri[7:0] + end + attribute \src "issuer_ls180.v:181779.3-181780.35" + process $proc$issuer_ls180.v:181779$13568 + assign { } { } + assign $0\xive7_pri[7:0] \xive7_pri$next + sync posedge \clk + update \xive7_pri $0\xive7_pri[7:0] + end + attribute \src "issuer_ls180.v:181781.3-181782.35" + process $proc$issuer_ls180.v:181781$13569 + assign { } { } + assign $0\xive8_pri[7:0] \xive8_pri$next + sync posedge \clk + update \xive8_pri $0\xive8_pri[7:0] + end + attribute \src "issuer_ls180.v:181783.3-181784.35" + process $proc$issuer_ls180.v:181783$13570 + assign { } { } + assign $0\xive9_pri[7:0] \xive9_pri$next + sync posedge \clk + update \xive9_pri $0\xive9_pri[7:0] + end + attribute \src "issuer_ls180.v:181785.3-181786.37" + process $proc$issuer_ls180.v:181785$13571 + assign { } { } + assign $0\xive10_pri[7:0] \xive10_pri$next + sync posedge \clk + update \xive10_pri $0\xive10_pri[7:0] + end + attribute \src "issuer_ls180.v:181787.3-181788.37" + process $proc$issuer_ls180.v:181787$13572 + assign { } { } + assign $0\xive11_pri[7:0] \xive11_pri$next + sync posedge \clk + update \xive11_pri $0\xive11_pri[7:0] + end + attribute \src "issuer_ls180.v:181789.3-181790.37" + process $proc$issuer_ls180.v:181789$13573 + assign { } { } + assign $0\xive12_pri[7:0] \xive12_pri$next + sync posedge \clk + update \xive12_pri $0\xive12_pri[7:0] + end + attribute \src "issuer_ls180.v:181791.3-181792.37" + process $proc$issuer_ls180.v:181791$13574 + assign { } { } + assign $0\xive13_pri[7:0] \xive13_pri$next + sync posedge \clk + update \xive13_pri $0\xive13_pri[7:0] + end + attribute \src "issuer_ls180.v:181793.3-181794.37" + process $proc$issuer_ls180.v:181793$13575 + assign { } { } + assign $0\xive14_pri[7:0] \xive14_pri$next + sync posedge \clk + update \xive14_pri $0\xive14_pri[7:0] + end + attribute \src "issuer_ls180.v:181795.3-181796.37" + process $proc$issuer_ls180.v:181795$13576 + assign { } { } + assign $0\xive15_pri[7:0] \xive15_pri$next + sync posedge \clk + update \xive15_pri $0\xive15_pri[7:0] + end + attribute \src "issuer_ls180.v:181797.3-181798.39" + process $proc$issuer_ls180.v:181797$13577 + assign { } { } + assign $0\ics_wb__ack[0:0] \ics_wb__ack$next + sync posedge \clk + update \ics_wb__ack $0\ics_wb__ack[0:0] + end + attribute \src "issuer_ls180.v:181799.3-181800.43" + process $proc$issuer_ls180.v:181799$13578 + assign { } { } + assign $0\ics_wb__dat_r[31:0] \ics_wb__dat_r$next + sync posedge \clk + update \ics_wb__dat_r $0\ics_wb__dat_r[31:0] + end + attribute \src "issuer_ls180.v:181801.3-181802.39" + process $proc$issuer_ls180.v:181801$13579 + assign { } { } + assign $0\int_level_l[15:0] \int_level_l$next + sync posedge \clk + update \int_level_l $0\int_level_l[15:0] + end + attribute \src "issuer_ls180.v:181803.3-181888.6" + process $proc$issuer_ls180.v:181803$13580 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $0\xive0_pri$next[7:0]$13581 $4\xive0_pri$next[7:0]$13645 + assign $0\xive10_pri$next[7:0]$13582 $4\xive10_pri$next[7:0]$13646 + assign $0\xive11_pri$next[7:0]$13583 $4\xive11_pri$next[7:0]$13647 + assign $0\xive12_pri$next[7:0]$13584 $4\xive12_pri$next[7:0]$13648 + assign $0\xive13_pri$next[7:0]$13585 $4\xive13_pri$next[7:0]$13649 + assign $0\xive14_pri$next[7:0]$13586 $4\xive14_pri$next[7:0]$13650 + assign $0\xive15_pri$next[7:0]$13587 $4\xive15_pri$next[7:0]$13651 + assign $0\xive1_pri$next[7:0]$13588 $4\xive1_pri$next[7:0]$13652 + assign $0\xive2_pri$next[7:0]$13589 $4\xive2_pri$next[7:0]$13653 + assign $0\xive3_pri$next[7:0]$13590 $4\xive3_pri$next[7:0]$13654 + assign $0\xive4_pri$next[7:0]$13591 $4\xive4_pri$next[7:0]$13655 + assign $0\xive5_pri$next[7:0]$13592 $4\xive5_pri$next[7:0]$13656 + assign $0\xive6_pri$next[7:0]$13593 $4\xive6_pri$next[7:0]$13657 + assign $0\xive7_pri$next[7:0]$13594 $4\xive7_pri$next[7:0]$13658 + assign $0\xive8_pri$next[7:0]$13595 $4\xive8_pri$next[7:0]$13659 + assign $0\xive9_pri$next[7:0]$13596 $4\xive9_pri$next[7:0]$13660 + attribute \src "issuer_ls180.v:181804.5-181804.29" + switch \initial + attribute \src "issuer_ls180.v:181804.9-181804.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:341" + switch \$73 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $1\xive0_pri$next[7:0]$13597 $2\xive0_pri$next[7:0]$13613 + assign $1\xive10_pri$next[7:0]$13598 $2\xive10_pri$next[7:0]$13614 + assign $1\xive11_pri$next[7:0]$13599 $2\xive11_pri$next[7:0]$13615 + assign $1\xive12_pri$next[7:0]$13600 $2\xive12_pri$next[7:0]$13616 + assign $1\xive13_pri$next[7:0]$13601 $2\xive13_pri$next[7:0]$13617 + assign $1\xive14_pri$next[7:0]$13602 $2\xive14_pri$next[7:0]$13618 + assign $1\xive15_pri$next[7:0]$13603 $2\xive15_pri$next[7:0]$13619 + assign $1\xive1_pri$next[7:0]$13604 $2\xive1_pri$next[7:0]$13620 + assign $1\xive2_pri$next[7:0]$13605 $2\xive2_pri$next[7:0]$13621 + assign $1\xive3_pri$next[7:0]$13606 $2\xive3_pri$next[7:0]$13622 + assign $1\xive4_pri$next[7:0]$13607 $2\xive4_pri$next[7:0]$13623 + assign $1\xive5_pri$next[7:0]$13608 $2\xive5_pri$next[7:0]$13624 + assign $1\xive6_pri$next[7:0]$13609 $2\xive6_pri$next[7:0]$13625 + assign $1\xive7_pri$next[7:0]$13610 $2\xive7_pri$next[7:0]$13626 + assign $1\xive8_pri$next[7:0]$13611 $2\xive8_pri$next[7:0]$13627 + assign $1\xive9_pri$next[7:0]$13612 $2\xive9_pri$next[7:0]$13628 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:342" + switch \reg_is_xive + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $2\xive0_pri$next[7:0]$13613 $3\xive0_pri$next[7:0]$13629 + assign $2\xive10_pri$next[7:0]$13614 $3\xive10_pri$next[7:0]$13630 + assign $2\xive11_pri$next[7:0]$13615 $3\xive11_pri$next[7:0]$13631 + assign $2\xive12_pri$next[7:0]$13616 $3\xive12_pri$next[7:0]$13632 + assign $2\xive13_pri$next[7:0]$13617 $3\xive13_pri$next[7:0]$13633 + assign $2\xive14_pri$next[7:0]$13618 $3\xive14_pri$next[7:0]$13634 + assign $2\xive15_pri$next[7:0]$13619 $3\xive15_pri$next[7:0]$13635 + assign $2\xive1_pri$next[7:0]$13620 $3\xive1_pri$next[7:0]$13636 + assign $2\xive2_pri$next[7:0]$13621 $3\xive2_pri$next[7:0]$13637 + assign $2\xive3_pri$next[7:0]$13622 $3\xive3_pri$next[7:0]$13638 + assign $2\xive4_pri$next[7:0]$13623 $3\xive4_pri$next[7:0]$13639 + assign $2\xive5_pri$next[7:0]$13624 $3\xive5_pri$next[7:0]$13640 + assign $2\xive6_pri$next[7:0]$13625 $3\xive6_pri$next[7:0]$13641 + assign $2\xive7_pri$next[7:0]$13626 $3\xive7_pri$next[7:0]$13642 + assign $2\xive8_pri$next[7:0]$13627 $3\xive8_pri$next[7:0]$13643 + assign $2\xive9_pri$next[7:0]$13628 $3\xive9_pri$next[7:0]$13644 + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:345" + switch \reg_idx + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $3\xive10_pri$next[7:0]$13630 \xive10_pri + assign $3\xive11_pri$next[7:0]$13631 \xive11_pri + assign $3\xive12_pri$next[7:0]$13632 \xive12_pri + assign $3\xive13_pri$next[7:0]$13633 \xive13_pri + assign $3\xive14_pri$next[7:0]$13634 \xive14_pri + assign $3\xive15_pri$next[7:0]$13635 \xive15_pri + assign $3\xive1_pri$next[7:0]$13636 \xive1_pri + assign $3\xive2_pri$next[7:0]$13637 \xive2_pri + assign $3\xive3_pri$next[7:0]$13638 \xive3_pri + assign $3\xive4_pri$next[7:0]$13639 \xive4_pri + assign $3\xive5_pri$next[7:0]$13640 \xive5_pri + assign $3\xive6_pri$next[7:0]$13641 \xive6_pri + assign $3\xive7_pri$next[7:0]$13642 \xive7_pri + assign $3\xive8_pri$next[7:0]$13643 \xive8_pri + assign $3\xive9_pri$next[7:0]$13644 \xive9_pri + assign $3\xive0_pri$next[7:0]$13629 \be_in [7:0] + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0001 + assign $3\xive0_pri$next[7:0]$13629 \xive0_pri + assign $3\xive10_pri$next[7:0]$13630 \xive10_pri + assign $3\xive11_pri$next[7:0]$13631 \xive11_pri + assign $3\xive12_pri$next[7:0]$13632 \xive12_pri + assign $3\xive13_pri$next[7:0]$13633 \xive13_pri + assign $3\xive14_pri$next[7:0]$13634 \xive14_pri + assign $3\xive15_pri$next[7:0]$13635 \xive15_pri + assign { } { } + assign $3\xive2_pri$next[7:0]$13637 \xive2_pri + assign $3\xive3_pri$next[7:0]$13638 \xive3_pri + assign $3\xive4_pri$next[7:0]$13639 \xive4_pri + assign $3\xive5_pri$next[7:0]$13640 \xive5_pri + assign $3\xive6_pri$next[7:0]$13641 \xive6_pri + assign $3\xive7_pri$next[7:0]$13642 \xive7_pri + assign $3\xive8_pri$next[7:0]$13643 \xive8_pri + assign $3\xive9_pri$next[7:0]$13644 \xive9_pri + assign $3\xive1_pri$next[7:0]$13636 \be_in [7:0] + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0010 + assign $3\xive0_pri$next[7:0]$13629 \xive0_pri + assign $3\xive10_pri$next[7:0]$13630 \xive10_pri + assign $3\xive11_pri$next[7:0]$13631 \xive11_pri + assign $3\xive12_pri$next[7:0]$13632 \xive12_pri + assign $3\xive13_pri$next[7:0]$13633 \xive13_pri + assign $3\xive14_pri$next[7:0]$13634 \xive14_pri + assign $3\xive15_pri$next[7:0]$13635 \xive15_pri + assign $3\xive1_pri$next[7:0]$13636 \xive1_pri + assign { } { } + assign $3\xive3_pri$next[7:0]$13638 \xive3_pri + assign $3\xive4_pri$next[7:0]$13639 \xive4_pri + assign $3\xive5_pri$next[7:0]$13640 \xive5_pri + assign $3\xive6_pri$next[7:0]$13641 \xive6_pri + assign $3\xive7_pri$next[7:0]$13642 \xive7_pri + assign $3\xive8_pri$next[7:0]$13643 \xive8_pri + assign $3\xive9_pri$next[7:0]$13644 \xive9_pri + assign $3\xive2_pri$next[7:0]$13637 \be_in [7:0] + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0011 + assign $3\xive0_pri$next[7:0]$13629 \xive0_pri + assign $3\xive10_pri$next[7:0]$13630 \xive10_pri + assign $3\xive11_pri$next[7:0]$13631 \xive11_pri + assign $3\xive12_pri$next[7:0]$13632 \xive12_pri + assign $3\xive13_pri$next[7:0]$13633 \xive13_pri + assign $3\xive14_pri$next[7:0]$13634 \xive14_pri + assign $3\xive15_pri$next[7:0]$13635 \xive15_pri + assign $3\xive1_pri$next[7:0]$13636 \xive1_pri + assign $3\xive2_pri$next[7:0]$13637 \xive2_pri + assign { } { } + assign $3\xive4_pri$next[7:0]$13639 \xive4_pri + assign $3\xive5_pri$next[7:0]$13640 \xive5_pri + assign $3\xive6_pri$next[7:0]$13641 \xive6_pri + assign $3\xive7_pri$next[7:0]$13642 \xive7_pri + assign $3\xive8_pri$next[7:0]$13643 \xive8_pri + assign $3\xive9_pri$next[7:0]$13644 \xive9_pri + assign $3\xive3_pri$next[7:0]$13638 \be_in [7:0] + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0100 + assign $3\xive0_pri$next[7:0]$13629 \xive0_pri + assign $3\xive10_pri$next[7:0]$13630 \xive10_pri + assign $3\xive11_pri$next[7:0]$13631 \xive11_pri + assign $3\xive12_pri$next[7:0]$13632 \xive12_pri + assign $3\xive13_pri$next[7:0]$13633 \xive13_pri + assign $3\xive14_pri$next[7:0]$13634 \xive14_pri + assign $3\xive15_pri$next[7:0]$13635 \xive15_pri + assign $3\xive1_pri$next[7:0]$13636 \xive1_pri + assign $3\xive2_pri$next[7:0]$13637 \xive2_pri + assign $3\xive3_pri$next[7:0]$13638 \xive3_pri + assign { } { } + assign $3\xive5_pri$next[7:0]$13640 \xive5_pri + assign $3\xive6_pri$next[7:0]$13641 \xive6_pri + assign $3\xive7_pri$next[7:0]$13642 \xive7_pri + assign $3\xive8_pri$next[7:0]$13643 \xive8_pri + assign $3\xive9_pri$next[7:0]$13644 \xive9_pri + assign $3\xive4_pri$next[7:0]$13639 \be_in [7:0] + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0101 + assign $3\xive0_pri$next[7:0]$13629 \xive0_pri + assign $3\xive10_pri$next[7:0]$13630 \xive10_pri + assign $3\xive11_pri$next[7:0]$13631 \xive11_pri + assign $3\xive12_pri$next[7:0]$13632 \xive12_pri + assign $3\xive13_pri$next[7:0]$13633 \xive13_pri + assign $3\xive14_pri$next[7:0]$13634 \xive14_pri + assign $3\xive15_pri$next[7:0]$13635 \xive15_pri + assign $3\xive1_pri$next[7:0]$13636 \xive1_pri + assign $3\xive2_pri$next[7:0]$13637 \xive2_pri + assign $3\xive3_pri$next[7:0]$13638 \xive3_pri + assign $3\xive4_pri$next[7:0]$13639 \xive4_pri + assign { } { } + assign $3\xive6_pri$next[7:0]$13641 \xive6_pri + assign $3\xive7_pri$next[7:0]$13642 \xive7_pri + assign $3\xive8_pri$next[7:0]$13643 \xive8_pri + assign $3\xive9_pri$next[7:0]$13644 \xive9_pri + assign $3\xive5_pri$next[7:0]$13640 \be_in [7:0] + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0110 + assign $3\xive0_pri$next[7:0]$13629 \xive0_pri + assign $3\xive10_pri$next[7:0]$13630 \xive10_pri + assign $3\xive11_pri$next[7:0]$13631 \xive11_pri + assign $3\xive12_pri$next[7:0]$13632 \xive12_pri + assign $3\xive13_pri$next[7:0]$13633 \xive13_pri + assign $3\xive14_pri$next[7:0]$13634 \xive14_pri + assign $3\xive15_pri$next[7:0]$13635 \xive15_pri + assign $3\xive1_pri$next[7:0]$13636 \xive1_pri + assign $3\xive2_pri$next[7:0]$13637 \xive2_pri + assign $3\xive3_pri$next[7:0]$13638 \xive3_pri + assign $3\xive4_pri$next[7:0]$13639 \xive4_pri + assign $3\xive5_pri$next[7:0]$13640 \xive5_pri + assign { } { } + assign $3\xive7_pri$next[7:0]$13642 \xive7_pri + assign $3\xive8_pri$next[7:0]$13643 \xive8_pri + assign $3\xive9_pri$next[7:0]$13644 \xive9_pri + assign $3\xive6_pri$next[7:0]$13641 \be_in [7:0] + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0111 + assign $3\xive0_pri$next[7:0]$13629 \xive0_pri + assign $3\xive10_pri$next[7:0]$13630 \xive10_pri + assign $3\xive11_pri$next[7:0]$13631 \xive11_pri + assign $3\xive12_pri$next[7:0]$13632 \xive12_pri + assign $3\xive13_pri$next[7:0]$13633 \xive13_pri + assign $3\xive14_pri$next[7:0]$13634 \xive14_pri + assign $3\xive15_pri$next[7:0]$13635 \xive15_pri + assign $3\xive1_pri$next[7:0]$13636 \xive1_pri + assign $3\xive2_pri$next[7:0]$13637 \xive2_pri + assign $3\xive3_pri$next[7:0]$13638 \xive3_pri + assign $3\xive4_pri$next[7:0]$13639 \xive4_pri + assign $3\xive5_pri$next[7:0]$13640 \xive5_pri + assign $3\xive6_pri$next[7:0]$13641 \xive6_pri + assign { } { } + assign $3\xive8_pri$next[7:0]$13643 \xive8_pri + assign $3\xive9_pri$next[7:0]$13644 \xive9_pri + assign $3\xive7_pri$next[7:0]$13642 \be_in [7:0] + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'1000 + assign $3\xive0_pri$next[7:0]$13629 \xive0_pri + assign $3\xive10_pri$next[7:0]$13630 \xive10_pri + assign $3\xive11_pri$next[7:0]$13631 \xive11_pri + assign $3\xive12_pri$next[7:0]$13632 \xive12_pri + assign $3\xive13_pri$next[7:0]$13633 \xive13_pri + assign $3\xive14_pri$next[7:0]$13634 \xive14_pri + assign $3\xive15_pri$next[7:0]$13635 \xive15_pri + assign $3\xive1_pri$next[7:0]$13636 \xive1_pri + assign $3\xive2_pri$next[7:0]$13637 \xive2_pri + assign $3\xive3_pri$next[7:0]$13638 \xive3_pri + assign $3\xive4_pri$next[7:0]$13639 \xive4_pri + assign $3\xive5_pri$next[7:0]$13640 \xive5_pri + assign $3\xive6_pri$next[7:0]$13641 \xive6_pri + assign $3\xive7_pri$next[7:0]$13642 \xive7_pri + assign { } { } + assign $3\xive9_pri$next[7:0]$13644 \xive9_pri + assign $3\xive8_pri$next[7:0]$13643 \be_in [7:0] + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'1001 + assign $3\xive0_pri$next[7:0]$13629 \xive0_pri + assign $3\xive10_pri$next[7:0]$13630 \xive10_pri + assign $3\xive11_pri$next[7:0]$13631 \xive11_pri + assign $3\xive12_pri$next[7:0]$13632 \xive12_pri + assign $3\xive13_pri$next[7:0]$13633 \xive13_pri + assign $3\xive14_pri$next[7:0]$13634 \xive14_pri + assign $3\xive15_pri$next[7:0]$13635 \xive15_pri + assign $3\xive1_pri$next[7:0]$13636 \xive1_pri + assign $3\xive2_pri$next[7:0]$13637 \xive2_pri + assign $3\xive3_pri$next[7:0]$13638 \xive3_pri + assign $3\xive4_pri$next[7:0]$13639 \xive4_pri + assign $3\xive5_pri$next[7:0]$13640 \xive5_pri + assign $3\xive6_pri$next[7:0]$13641 \xive6_pri + assign $3\xive7_pri$next[7:0]$13642 \xive7_pri + assign $3\xive8_pri$next[7:0]$13643 \xive8_pri + assign { } { } + assign $3\xive9_pri$next[7:0]$13644 \be_in [7:0] + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'1010 + assign $3\xive0_pri$next[7:0]$13629 \xive0_pri + assign { } { } + assign $3\xive11_pri$next[7:0]$13631 \xive11_pri + assign $3\xive12_pri$next[7:0]$13632 \xive12_pri + assign $3\xive13_pri$next[7:0]$13633 \xive13_pri + assign $3\xive14_pri$next[7:0]$13634 \xive14_pri + assign $3\xive15_pri$next[7:0]$13635 \xive15_pri + assign $3\xive1_pri$next[7:0]$13636 \xive1_pri + assign $3\xive2_pri$next[7:0]$13637 \xive2_pri + assign $3\xive3_pri$next[7:0]$13638 \xive3_pri + assign $3\xive4_pri$next[7:0]$13639 \xive4_pri + assign $3\xive5_pri$next[7:0]$13640 \xive5_pri + assign $3\xive6_pri$next[7:0]$13641 \xive6_pri + assign $3\xive7_pri$next[7:0]$13642 \xive7_pri + assign $3\xive8_pri$next[7:0]$13643 \xive8_pri + assign $3\xive9_pri$next[7:0]$13644 \xive9_pri + assign $3\xive10_pri$next[7:0]$13630 \be_in [7:0] + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'1011 + assign $3\xive0_pri$next[7:0]$13629 \xive0_pri + assign $3\xive10_pri$next[7:0]$13630 \xive10_pri + assign { } { } + assign $3\xive12_pri$next[7:0]$13632 \xive12_pri + assign $3\xive13_pri$next[7:0]$13633 \xive13_pri + assign $3\xive14_pri$next[7:0]$13634 \xive14_pri + assign $3\xive15_pri$next[7:0]$13635 \xive15_pri + assign $3\xive1_pri$next[7:0]$13636 \xive1_pri + assign $3\xive2_pri$next[7:0]$13637 \xive2_pri + assign $3\xive3_pri$next[7:0]$13638 \xive3_pri + assign $3\xive4_pri$next[7:0]$13639 \xive4_pri + assign $3\xive5_pri$next[7:0]$13640 \xive5_pri + assign $3\xive6_pri$next[7:0]$13641 \xive6_pri + assign $3\xive7_pri$next[7:0]$13642 \xive7_pri + assign $3\xive8_pri$next[7:0]$13643 \xive8_pri + assign $3\xive9_pri$next[7:0]$13644 \xive9_pri + assign $3\xive11_pri$next[7:0]$13631 \be_in [7:0] + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'1100 + assign $3\xive0_pri$next[7:0]$13629 \xive0_pri + assign $3\xive10_pri$next[7:0]$13630 \xive10_pri + assign $3\xive11_pri$next[7:0]$13631 \xive11_pri + assign { } { } + assign $3\xive13_pri$next[7:0]$13633 \xive13_pri + assign $3\xive14_pri$next[7:0]$13634 \xive14_pri + assign $3\xive15_pri$next[7:0]$13635 \xive15_pri + assign $3\xive1_pri$next[7:0]$13636 \xive1_pri + assign $3\xive2_pri$next[7:0]$13637 \xive2_pri + assign $3\xive3_pri$next[7:0]$13638 \xive3_pri + assign $3\xive4_pri$next[7:0]$13639 \xive4_pri + assign $3\xive5_pri$next[7:0]$13640 \xive5_pri + assign $3\xive6_pri$next[7:0]$13641 \xive6_pri + assign $3\xive7_pri$next[7:0]$13642 \xive7_pri + assign $3\xive8_pri$next[7:0]$13643 \xive8_pri + assign $3\xive9_pri$next[7:0]$13644 \xive9_pri + assign $3\xive12_pri$next[7:0]$13632 \be_in [7:0] + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'1101 + assign $3\xive0_pri$next[7:0]$13629 \xive0_pri + assign $3\xive10_pri$next[7:0]$13630 \xive10_pri + assign $3\xive11_pri$next[7:0]$13631 \xive11_pri + assign $3\xive12_pri$next[7:0]$13632 \xive12_pri + assign { } { } + assign $3\xive14_pri$next[7:0]$13634 \xive14_pri + assign $3\xive15_pri$next[7:0]$13635 \xive15_pri + assign $3\xive1_pri$next[7:0]$13636 \xive1_pri + assign $3\xive2_pri$next[7:0]$13637 \xive2_pri + assign $3\xive3_pri$next[7:0]$13638 \xive3_pri + assign $3\xive4_pri$next[7:0]$13639 \xive4_pri + assign $3\xive5_pri$next[7:0]$13640 \xive5_pri + assign $3\xive6_pri$next[7:0]$13641 \xive6_pri + assign $3\xive7_pri$next[7:0]$13642 \xive7_pri + assign $3\xive8_pri$next[7:0]$13643 \xive8_pri + assign $3\xive9_pri$next[7:0]$13644 \xive9_pri + assign $3\xive13_pri$next[7:0]$13633 \be_in [7:0] + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'1110 + assign $3\xive0_pri$next[7:0]$13629 \xive0_pri + assign $3\xive10_pri$next[7:0]$13630 \xive10_pri + assign $3\xive11_pri$next[7:0]$13631 \xive11_pri + assign $3\xive12_pri$next[7:0]$13632 \xive12_pri + assign $3\xive13_pri$next[7:0]$13633 \xive13_pri + assign { } { } + assign $3\xive15_pri$next[7:0]$13635 \xive15_pri + assign $3\xive1_pri$next[7:0]$13636 \xive1_pri + assign $3\xive2_pri$next[7:0]$13637 \xive2_pri + assign $3\xive3_pri$next[7:0]$13638 \xive3_pri + assign $3\xive4_pri$next[7:0]$13639 \xive4_pri + assign $3\xive5_pri$next[7:0]$13640 \xive5_pri + assign $3\xive6_pri$next[7:0]$13641 \xive6_pri + assign $3\xive7_pri$next[7:0]$13642 \xive7_pri + assign $3\xive8_pri$next[7:0]$13643 \xive8_pri + assign $3\xive9_pri$next[7:0]$13644 \xive9_pri + assign $3\xive14_pri$next[7:0]$13634 \be_in [7:0] + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'---- + assign $3\xive0_pri$next[7:0]$13629 \xive0_pri + assign $3\xive10_pri$next[7:0]$13630 \xive10_pri + assign $3\xive11_pri$next[7:0]$13631 \xive11_pri + assign $3\xive12_pri$next[7:0]$13632 \xive12_pri + assign $3\xive13_pri$next[7:0]$13633 \xive13_pri + assign $3\xive14_pri$next[7:0]$13634 \xive14_pri + assign { } { } + assign $3\xive1_pri$next[7:0]$13636 \xive1_pri + assign $3\xive2_pri$next[7:0]$13637 \xive2_pri + assign $3\xive3_pri$next[7:0]$13638 \xive3_pri + assign $3\xive4_pri$next[7:0]$13639 \xive4_pri + assign $3\xive5_pri$next[7:0]$13640 \xive5_pri + assign $3\xive6_pri$next[7:0]$13641 \xive6_pri + assign $3\xive7_pri$next[7:0]$13642 \xive7_pri + assign $3\xive8_pri$next[7:0]$13643 \xive8_pri + assign $3\xive9_pri$next[7:0]$13644 \xive9_pri + assign $3\xive15_pri$next[7:0]$13635 \be_in [7:0] + case + assign $3\xive0_pri$next[7:0]$13629 \xive0_pri + assign $3\xive10_pri$next[7:0]$13630 \xive10_pri + assign $3\xive11_pri$next[7:0]$13631 \xive11_pri + assign $3\xive12_pri$next[7:0]$13632 \xive12_pri + assign $3\xive13_pri$next[7:0]$13633 \xive13_pri + assign $3\xive14_pri$next[7:0]$13634 \xive14_pri + assign $3\xive15_pri$next[7:0]$13635 \xive15_pri + assign $3\xive1_pri$next[7:0]$13636 \xive1_pri + assign $3\xive2_pri$next[7:0]$13637 \xive2_pri + assign $3\xive3_pri$next[7:0]$13638 \xive3_pri + assign $3\xive4_pri$next[7:0]$13639 \xive4_pri + assign $3\xive5_pri$next[7:0]$13640 \xive5_pri + assign $3\xive6_pri$next[7:0]$13641 \xive6_pri + assign $3\xive7_pri$next[7:0]$13642 \xive7_pri + assign $3\xive8_pri$next[7:0]$13643 \xive8_pri + assign $3\xive9_pri$next[7:0]$13644 \xive9_pri + end + case + assign $2\xive0_pri$next[7:0]$13613 \xive0_pri + assign $2\xive10_pri$next[7:0]$13614 \xive10_pri + assign $2\xive11_pri$next[7:0]$13615 \xive11_pri + assign $2\xive12_pri$next[7:0]$13616 \xive12_pri + assign $2\xive13_pri$next[7:0]$13617 \xive13_pri + assign $2\xive14_pri$next[7:0]$13618 \xive14_pri + assign $2\xive15_pri$next[7:0]$13619 \xive15_pri + assign $2\xive1_pri$next[7:0]$13620 \xive1_pri + assign $2\xive2_pri$next[7:0]$13621 \xive2_pri + assign $2\xive3_pri$next[7:0]$13622 \xive3_pri + assign $2\xive4_pri$next[7:0]$13623 \xive4_pri + assign $2\xive5_pri$next[7:0]$13624 \xive5_pri + assign $2\xive6_pri$next[7:0]$13625 \xive6_pri + assign $2\xive7_pri$next[7:0]$13626 \xive7_pri + assign $2\xive8_pri$next[7:0]$13627 \xive8_pri + assign $2\xive9_pri$next[7:0]$13628 \xive9_pri + end + case + assign $1\xive0_pri$next[7:0]$13597 \xive0_pri + assign $1\xive10_pri$next[7:0]$13598 \xive10_pri + assign $1\xive11_pri$next[7:0]$13599 \xive11_pri + assign $1\xive12_pri$next[7:0]$13600 \xive12_pri + assign $1\xive13_pri$next[7:0]$13601 \xive13_pri + assign $1\xive14_pri$next[7:0]$13602 \xive14_pri + assign $1\xive15_pri$next[7:0]$13603 \xive15_pri + assign $1\xive1_pri$next[7:0]$13604 \xive1_pri + assign $1\xive2_pri$next[7:0]$13605 \xive2_pri + assign $1\xive3_pri$next[7:0]$13606 \xive3_pri + assign $1\xive4_pri$next[7:0]$13607 \xive4_pri + assign $1\xive5_pri$next[7:0]$13608 \xive5_pri + assign $1\xive6_pri$next[7:0]$13609 \xive6_pri + assign $1\xive7_pri$next[7:0]$13610 \xive7_pri + assign $1\xive8_pri$next[7:0]$13611 \xive8_pri + assign $1\xive9_pri$next[7:0]$13612 \xive9_pri + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign { } { } + assign $4\xive0_pri$next[7:0]$13645 8'11111111 + assign $4\xive1_pri$next[7:0]$13652 8'11111111 + assign $4\xive2_pri$next[7:0]$13653 8'11111111 + assign $4\xive3_pri$next[7:0]$13654 8'11111111 + assign $4\xive4_pri$next[7:0]$13655 8'11111111 + assign $4\xive5_pri$next[7:0]$13656 8'11111111 + assign $4\xive6_pri$next[7:0]$13657 8'11111111 + assign $4\xive7_pri$next[7:0]$13658 8'11111111 + assign $4\xive8_pri$next[7:0]$13659 8'11111111 + assign $4\xive9_pri$next[7:0]$13660 8'11111111 + assign $4\xive10_pri$next[7:0]$13646 8'11111111 + assign $4\xive11_pri$next[7:0]$13647 8'11111111 + assign $4\xive12_pri$next[7:0]$13648 8'11111111 + assign $4\xive13_pri$next[7:0]$13649 8'11111111 + assign $4\xive14_pri$next[7:0]$13650 8'11111111 + assign $4\xive15_pri$next[7:0]$13651 8'11111111 + case + assign $4\xive0_pri$next[7:0]$13645 $1\xive0_pri$next[7:0]$13597 + assign $4\xive10_pri$next[7:0]$13646 $1\xive10_pri$next[7:0]$13598 + assign $4\xive11_pri$next[7:0]$13647 $1\xive11_pri$next[7:0]$13599 + assign $4\xive12_pri$next[7:0]$13648 $1\xive12_pri$next[7:0]$13600 + assign $4\xive13_pri$next[7:0]$13649 $1\xive13_pri$next[7:0]$13601 + assign $4\xive14_pri$next[7:0]$13650 $1\xive14_pri$next[7:0]$13602 + assign $4\xive15_pri$next[7:0]$13651 $1\xive15_pri$next[7:0]$13603 + assign $4\xive1_pri$next[7:0]$13652 $1\xive1_pri$next[7:0]$13604 + assign $4\xive2_pri$next[7:0]$13653 $1\xive2_pri$next[7:0]$13605 + assign $4\xive3_pri$next[7:0]$13654 $1\xive3_pri$next[7:0]$13606 + assign $4\xive4_pri$next[7:0]$13655 $1\xive4_pri$next[7:0]$13607 + assign $4\xive5_pri$next[7:0]$13656 $1\xive5_pri$next[7:0]$13608 + assign $4\xive6_pri$next[7:0]$13657 $1\xive6_pri$next[7:0]$13609 + assign $4\xive7_pri$next[7:0]$13658 $1\xive7_pri$next[7:0]$13610 + assign $4\xive8_pri$next[7:0]$13659 $1\xive8_pri$next[7:0]$13611 + assign $4\xive9_pri$next[7:0]$13660 $1\xive9_pri$next[7:0]$13612 + end + sync always + update \xive0_pri$next $0\xive0_pri$next[7:0]$13581 + update \xive10_pri$next $0\xive10_pri$next[7:0]$13582 + update \xive11_pri$next $0\xive11_pri$next[7:0]$13583 + update \xive12_pri$next $0\xive12_pri$next[7:0]$13584 + update \xive13_pri$next $0\xive13_pri$next[7:0]$13585 + update \xive14_pri$next $0\xive14_pri$next[7:0]$13586 + update \xive15_pri$next $0\xive15_pri$next[7:0]$13587 + update \xive1_pri$next $0\xive1_pri$next[7:0]$13588 + update \xive2_pri$next $0\xive2_pri$next[7:0]$13589 + update \xive3_pri$next $0\xive3_pri$next[7:0]$13590 + update \xive4_pri$next $0\xive4_pri$next[7:0]$13591 + update \xive5_pri$next $0\xive5_pri$next[7:0]$13592 + update \xive6_pri$next $0\xive6_pri$next[7:0]$13593 + update \xive7_pri$next $0\xive7_pri$next[7:0]$13594 + update \xive8_pri$next $0\xive8_pri$next[7:0]$13595 + update \xive9_pri$next $0\xive9_pri$next[7:0]$13596 + end + attribute \src "issuer_ls180.v:181889.3-181898.6" + process $proc$issuer_ls180.v:181889$13661 + assign { } { } + assign { } { } + assign $0\cur_pri0[7:0] $1\cur_pri0[7:0] + attribute \src "issuer_ls180.v:181890.5-181890.29" + switch \initial + attribute \src "issuer_ls180.v:181890.9-181890.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" + switch \$77 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\cur_pri0[7:0] \xive0_pri + case + assign $1\cur_pri0[7:0] \max_pri + end + sync always + update \cur_pri0 $0\cur_pri0[7:0] + end + attribute \src "issuer_ls180.v:181899.3-181908.6" + process $proc$issuer_ls180.v:181899$13662 + assign { } { } + assign { } { } + assign $0\cur_idx0[3:0] $1\cur_idx0[3:0] + attribute \src "issuer_ls180.v:181900.5-181900.29" + switch \initial + attribute \src "issuer_ls180.v:181900.9-181900.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" + switch \$81 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\cur_idx0[3:0] 4'0000 + case + assign $1\cur_idx0[3:0] \max_idx + end + sync always + update \cur_idx0 $0\cur_idx0[3:0] + end + attribute \src "issuer_ls180.v:181909.3-181918.6" + process $proc$issuer_ls180.v:181909$13663 + assign { } { } + assign { } { } + assign $0\cur_pri1[7:0] $1\cur_pri1[7:0] + attribute \src "issuer_ls180.v:181910.5-181910.29" + switch \initial + attribute \src "issuer_ls180.v:181910.9-181910.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" + switch \$85 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\cur_pri1[7:0] \xive1_pri + case + assign $1\cur_pri1[7:0] \cur_pri0 + end + sync always + update \cur_pri1 $0\cur_pri1[7:0] + end + attribute \src "issuer_ls180.v:181919.3-181928.6" + process $proc$issuer_ls180.v:181919$13664 + assign { } { } + assign { } { } + assign $0\cur_idx1[3:0] $1\cur_idx1[3:0] + attribute \src "issuer_ls180.v:181920.5-181920.29" + switch \initial + attribute \src "issuer_ls180.v:181920.9-181920.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" + switch \$89 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\cur_idx1[3:0] 4'0001 + case + assign $1\cur_idx1[3:0] \cur_idx0 + end + sync always + update \cur_idx1 $0\cur_idx1[3:0] + end + attribute \src "issuer_ls180.v:181929.3-181938.6" + process $proc$issuer_ls180.v:181929$13665 + assign { } { } + assign { } { } + assign $0\cur_pri2[7:0] $1\cur_pri2[7:0] + attribute \src "issuer_ls180.v:181930.5-181930.29" + switch \initial + attribute \src "issuer_ls180.v:181930.9-181930.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" + switch \$93 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\cur_pri2[7:0] \xive2_pri + case + assign $1\cur_pri2[7:0] \cur_pri1 + end + sync always + update \cur_pri2 $0\cur_pri2[7:0] + end + attribute \src "issuer_ls180.v:181939.3-181948.6" + process $proc$issuer_ls180.v:181939$13666 + assign { } { } + assign { } { } + assign $0\cur_idx2[3:0] $1\cur_idx2[3:0] + attribute \src "issuer_ls180.v:181940.5-181940.29" + switch \initial + attribute \src "issuer_ls180.v:181940.9-181940.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" + switch \$97 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\cur_idx2[3:0] 4'0010 + case + assign $1\cur_idx2[3:0] \cur_idx1 + end + sync always + update \cur_idx2 $0\cur_idx2[3:0] + end + attribute \src "issuer_ls180.v:181949.3-181958.6" + process $proc$issuer_ls180.v:181949$13667 + assign { } { } + assign { } { } + assign $0\cur_pri3[7:0] $1\cur_pri3[7:0] + attribute \src "issuer_ls180.v:181950.5-181950.29" + switch \initial + attribute \src "issuer_ls180.v:181950.9-181950.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" + switch \$101 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\cur_pri3[7:0] \xive3_pri + case + assign $1\cur_pri3[7:0] \cur_pri2 + end + sync always + update \cur_pri3 $0\cur_pri3[7:0] + end + attribute \src "issuer_ls180.v:181959.3-181968.6" + process $proc$issuer_ls180.v:181959$13668 + assign { } { } + assign { } { } + assign $0\cur_idx3[3:0] $1\cur_idx3[3:0] + attribute \src "issuer_ls180.v:181960.5-181960.29" + switch \initial + attribute \src "issuer_ls180.v:181960.9-181960.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" + switch \$105 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\cur_idx3[3:0] 4'0011 + case + assign $1\cur_idx3[3:0] \cur_idx2 + end + sync always + update \cur_idx3 $0\cur_idx3[3:0] + end + attribute \src "issuer_ls180.v:181969.3-181978.6" + process $proc$issuer_ls180.v:181969$13669 + assign { } { } + assign { } { } + assign $0\cur_pri4[7:0] $1\cur_pri4[7:0] + attribute \src "issuer_ls180.v:181970.5-181970.29" + switch \initial + attribute \src "issuer_ls180.v:181970.9-181970.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" + switch \$109 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\cur_pri4[7:0] \xive4_pri + case + assign $1\cur_pri4[7:0] \cur_pri3 + end + sync always + update \cur_pri4 $0\cur_pri4[7:0] + end + attribute \src "issuer_ls180.v:181979.3-181987.6" + process $proc$issuer_ls180.v:181979$13670 + assign { } { } + assign { } { } + assign $0\int_level_l$next[15:0]$13671 $1\int_level_l$next[15:0]$13672 + attribute \src "issuer_ls180.v:181980.5-181980.29" + switch \initial + attribute \src "issuer_ls180.v:181980.9-181980.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\int_level_l$next[15:0]$13672 16'0000000000000000 + case + assign $1\int_level_l$next[15:0]$13672 \int_level_i + end + sync always + update \int_level_l$next $0\int_level_l$next[15:0]$13671 + end + attribute \src "issuer_ls180.v:181988.3-181997.6" + process $proc$issuer_ls180.v:181988$13673 + assign { } { } + assign { } { } + assign $0\cur_idx4[3:0] $1\cur_idx4[3:0] + attribute \src "issuer_ls180.v:181989.5-181989.29" + switch \initial + attribute \src "issuer_ls180.v:181989.9-181989.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" + switch \$113 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\cur_idx4[3:0] 4'0100 + case + assign $1\cur_idx4[3:0] \cur_idx3 + end + sync always + update \cur_idx4 $0\cur_idx4[3:0] + end + attribute \src "issuer_ls180.v:181998.3-182007.6" + process $proc$issuer_ls180.v:181998$13674 + assign { } { } + assign { } { } + assign $0\cur_pri5[7:0] $1\cur_pri5[7:0] + attribute \src "issuer_ls180.v:181999.5-181999.29" + switch \initial + attribute \src "issuer_ls180.v:181999.9-181999.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" + switch \$117 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\cur_pri5[7:0] \xive5_pri + case + assign $1\cur_pri5[7:0] \cur_pri4 + end + sync always + update \cur_pri5 $0\cur_pri5[7:0] + end + attribute \src "issuer_ls180.v:182008.3-182017.6" + process $proc$issuer_ls180.v:182008$13675 + assign { } { } + assign { } { } + assign $0\cur_idx5[3:0] $1\cur_idx5[3:0] + attribute \src "issuer_ls180.v:182009.5-182009.29" + switch \initial + attribute \src "issuer_ls180.v:182009.9-182009.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" + switch \$121 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\cur_idx5[3:0] 4'0101 + case + assign $1\cur_idx5[3:0] \cur_idx4 + end + sync always + update \cur_idx5 $0\cur_idx5[3:0] + end + attribute \src "issuer_ls180.v:182018.3-182027.6" + process $proc$issuer_ls180.v:182018$13676 + assign { } { } + assign { } { } + assign $0\cur_pri6[7:0] $1\cur_pri6[7:0] + attribute \src "issuer_ls180.v:182019.5-182019.29" + switch \initial + attribute \src "issuer_ls180.v:182019.9-182019.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" + switch \$125 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\cur_pri6[7:0] \xive6_pri + case + assign $1\cur_pri6[7:0] \cur_pri5 + end + sync always + update \cur_pri6 $0\cur_pri6[7:0] + end + attribute \src "issuer_ls180.v:182028.3-182037.6" + process $proc$issuer_ls180.v:182028$13677 + assign { } { } + assign { } { } + assign $0\cur_idx6[3:0] $1\cur_idx6[3:0] + attribute \src "issuer_ls180.v:182029.5-182029.29" + switch \initial + attribute \src "issuer_ls180.v:182029.9-182029.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" + switch \$129 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\cur_idx6[3:0] 4'0110 + case + assign $1\cur_idx6[3:0] \cur_idx5 + end + sync always + update \cur_idx6 $0\cur_idx6[3:0] + end + attribute \src "issuer_ls180.v:182038.3-182047.6" + process $proc$issuer_ls180.v:182038$13678 + assign { } { } + assign { } { } + assign $0\cur_pri7[7:0] $1\cur_pri7[7:0] + attribute \src "issuer_ls180.v:182039.5-182039.29" + switch \initial + attribute \src "issuer_ls180.v:182039.9-182039.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" + switch \$133 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\cur_pri7[7:0] \xive7_pri + case + assign $1\cur_pri7[7:0] \cur_pri6 + end + sync always + update \cur_pri7 $0\cur_pri7[7:0] + end + attribute \src "issuer_ls180.v:182048.3-182057.6" + process $proc$issuer_ls180.v:182048$13679 + assign { } { } + assign { } { } + assign $0\cur_idx7[3:0] $1\cur_idx7[3:0] + attribute \src "issuer_ls180.v:182049.5-182049.29" + switch \initial + attribute \src "issuer_ls180.v:182049.9-182049.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" + switch \$137 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\cur_idx7[3:0] 4'0111 + case + assign $1\cur_idx7[3:0] \cur_idx6 + end + sync always + update \cur_idx7 $0\cur_idx7[3:0] + end + attribute \src "issuer_ls180.v:182058.3-182067.6" + process $proc$issuer_ls180.v:182058$13680 + assign { } { } + assign { } { } + assign $0\cur_pri8[7:0] $1\cur_pri8[7:0] + attribute \src "issuer_ls180.v:182059.5-182059.29" + switch \initial + attribute \src "issuer_ls180.v:182059.9-182059.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" + switch \$141 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\cur_pri8[7:0] \xive8_pri + case + assign $1\cur_pri8[7:0] \cur_pri7 + end + sync always + update \cur_pri8 $0\cur_pri8[7:0] + end + attribute \src "issuer_ls180.v:182068.3-182077.6" + process $proc$issuer_ls180.v:182068$13681 + assign { } { } + assign { } { } + assign $0\cur_idx8[3:0] $1\cur_idx8[3:0] + attribute \src "issuer_ls180.v:182069.5-182069.29" + switch \initial + attribute \src "issuer_ls180.v:182069.9-182069.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" + switch \$145 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\cur_idx8[3:0] 4'1000 + case + assign $1\cur_idx8[3:0] \cur_idx7 + end + sync always + update \cur_idx8 $0\cur_idx8[3:0] + end + attribute \src "issuer_ls180.v:182078.3-182087.6" + process $proc$issuer_ls180.v:182078$13682 + assign { } { } + assign { } { } + assign $0\cur_pri9[7:0] $1\cur_pri9[7:0] + attribute \src "issuer_ls180.v:182079.5-182079.29" + switch \initial + attribute \src "issuer_ls180.v:182079.9-182079.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" + switch \$149 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\cur_pri9[7:0] \xive9_pri + case + assign $1\cur_pri9[7:0] \cur_pri8 + end + sync always + update \cur_pri9 $0\cur_pri9[7:0] + end + attribute \src "issuer_ls180.v:182088.3-182097.6" + process $proc$issuer_ls180.v:182088$13683 + assign { } { } + assign { } { } + assign $0\cur_idx9[3:0] $1\cur_idx9[3:0] + attribute \src "issuer_ls180.v:182089.5-182089.29" + switch \initial + attribute \src "issuer_ls180.v:182089.9-182089.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" + switch \$153 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\cur_idx9[3:0] 4'1001 + case + assign $1\cur_idx9[3:0] \cur_idx8 + end + sync always + update \cur_idx9 $0\cur_idx9[3:0] + end + attribute \src "issuer_ls180.v:182098.3-182107.6" + process $proc$issuer_ls180.v:182098$13684 + assign { } { } + assign { } { } + assign $0\cur_pri10[7:0] $1\cur_pri10[7:0] + attribute \src "issuer_ls180.v:182099.5-182099.29" + switch \initial + attribute \src "issuer_ls180.v:182099.9-182099.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" + switch \$157 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\cur_pri10[7:0] \xive10_pri + case + assign $1\cur_pri10[7:0] \cur_pri9 + end + sync always + update \cur_pri10 $0\cur_pri10[7:0] + end + attribute \src "issuer_ls180.v:182108.3-182117.6" + process $proc$issuer_ls180.v:182108$13685 + assign { } { } + assign { } { } + assign $0\cur_idx10[3:0] $1\cur_idx10[3:0] + attribute \src "issuer_ls180.v:182109.5-182109.29" + switch \initial + attribute \src "issuer_ls180.v:182109.9-182109.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" + switch \$161 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\cur_idx10[3:0] 4'1010 + case + assign $1\cur_idx10[3:0] \cur_idx9 + end + sync always + update \cur_idx10 $0\cur_idx10[3:0] + end + attribute \src "issuer_ls180.v:182118.3-182127.6" + process $proc$issuer_ls180.v:182118$13686 + assign { } { } + assign { } { } + assign $0\cur_pri11[7:0] $1\cur_pri11[7:0] + attribute \src "issuer_ls180.v:182119.5-182119.29" + switch \initial + attribute \src "issuer_ls180.v:182119.9-182119.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" + switch \$165 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\cur_pri11[7:0] \xive11_pri + case + assign $1\cur_pri11[7:0] \cur_pri10 + end + sync always + update \cur_pri11 $0\cur_pri11[7:0] + end + attribute \src "issuer_ls180.v:182128.3-182137.6" + process $proc$issuer_ls180.v:182128$13687 + assign { } { } + assign { } { } + assign $0\cur_idx11[3:0] $1\cur_idx11[3:0] + attribute \src "issuer_ls180.v:182129.5-182129.29" + switch \initial + attribute \src "issuer_ls180.v:182129.9-182129.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" + switch \$169 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\cur_idx11[3:0] 4'1011 + case + assign $1\cur_idx11[3:0] \cur_idx10 + end + sync always + update \cur_idx11 $0\cur_idx11[3:0] + end + attribute \src "issuer_ls180.v:182138.3-182147.6" + process $proc$issuer_ls180.v:182138$13688 + assign { } { } + assign { } { } + assign $0\cur_pri12[7:0] $1\cur_pri12[7:0] + attribute \src "issuer_ls180.v:182139.5-182139.29" + switch \initial + attribute \src "issuer_ls180.v:182139.9-182139.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" + switch \$173 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\cur_pri12[7:0] \xive12_pri + case + assign $1\cur_pri12[7:0] \cur_pri11 + end + sync always + update \cur_pri12 $0\cur_pri12[7:0] + end + attribute \src "issuer_ls180.v:182148.3-182157.6" + process $proc$issuer_ls180.v:182148$13689 + assign { } { } + assign { } { } + assign $0\cur_idx12[3:0] $1\cur_idx12[3:0] + attribute \src "issuer_ls180.v:182149.5-182149.29" + switch \initial + attribute \src "issuer_ls180.v:182149.9-182149.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" + switch \$177 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\cur_idx12[3:0] 4'1100 + case + assign $1\cur_idx12[3:0] \cur_idx11 + end + sync always + update \cur_idx12 $0\cur_idx12[3:0] + end + attribute \src "issuer_ls180.v:182158.3-182167.6" + process $proc$issuer_ls180.v:182158$13690 + assign { } { } + assign { } { } + assign $0\cur_pri13[7:0] $1\cur_pri13[7:0] + attribute \src "issuer_ls180.v:182159.5-182159.29" + switch \initial + attribute \src "issuer_ls180.v:182159.9-182159.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" + switch \$181 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\cur_pri13[7:0] \xive13_pri + case + assign $1\cur_pri13[7:0] \cur_pri12 + end + sync always + update \cur_pri13 $0\cur_pri13[7:0] + end + attribute \src "issuer_ls180.v:182168.3-182177.6" + process $proc$issuer_ls180.v:182168$13691 + assign { } { } + assign { } { } + assign $0\cur_idx13[3:0] $1\cur_idx13[3:0] + attribute \src "issuer_ls180.v:182169.5-182169.29" + switch \initial + attribute \src "issuer_ls180.v:182169.9-182169.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" + switch \$185 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\cur_idx13[3:0] 4'1101 + case + assign $1\cur_idx13[3:0] \cur_idx12 + end + sync always + update \cur_idx13 $0\cur_idx13[3:0] + end + attribute \src "issuer_ls180.v:182178.3-182187.6" + process $proc$issuer_ls180.v:182178$13692 + assign { } { } + assign { } { } + assign $0\cur_pri14[7:0] $1\cur_pri14[7:0] + attribute \src "issuer_ls180.v:182179.5-182179.29" + switch \initial + attribute \src "issuer_ls180.v:182179.9-182179.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" + switch \$189 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\cur_pri14[7:0] \xive14_pri + case + assign $1\cur_pri14[7:0] \cur_pri13 + end + sync always + update \cur_pri14 $0\cur_pri14[7:0] + end + attribute \src "issuer_ls180.v:182188.3-182237.6" + process $proc$issuer_ls180.v:182188$13693 + assign { } { } + assign { } { } + assign $0\be_out[31:0] $1\be_out[31:0] + attribute \src "issuer_ls180.v:182189.5-182189.29" + switch \initial + attribute \src "issuer_ls180.v:182189.9-182189.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:312" + switch { \reg_is_debug \reg_is_config \reg_is_xive } + attribute \src "issuer_ls180.v:0.0-0.0" + case 3'--1 + assign { } { } + assign $1\be_out[31:0] $2\be_out[31:0] + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:244" + switch \reg_idx + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0000 + assign { } { } + assign $2\be_out[31:0] { \ibit 1'0 \ibit 21'000000000000000000000 \$7 } + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0001 + assign { } { } + assign $2\be_out[31:0] { \ibit 1'0 \ibit 21'000000000000000000000 \$11 } + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0010 + assign { } { } + assign $2\be_out[31:0] { \ibit 1'0 \ibit 21'000000000000000000000 \$15 } + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0011 + assign { } { } + assign $2\be_out[31:0] { \ibit 1'0 \ibit 21'000000000000000000000 \$19 } + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0100 + assign { } { } + assign $2\be_out[31:0] { \ibit 1'0 \ibit 21'000000000000000000000 \$23 } + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0101 + assign { } { } + assign $2\be_out[31:0] { \ibit 1'0 \ibit 21'000000000000000000000 \$27 } + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0110 + assign { } { } + assign $2\be_out[31:0] { \ibit 1'0 \ibit 21'000000000000000000000 \$31 } + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'0111 + assign { } { } + assign $2\be_out[31:0] { \ibit 1'0 \ibit 21'000000000000000000000 \$35 } + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'1000 + assign { } { } + assign $2\be_out[31:0] { \ibit 1'0 \ibit 21'000000000000000000000 \$39 } + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'1001 + assign { } { } + assign $2\be_out[31:0] { \ibit 1'0 \ibit 21'000000000000000000000 \$43 } + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'1010 + assign { } { } + assign $2\be_out[31:0] { \ibit 1'0 \ibit 21'000000000000000000000 \$47 } + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'1011 + assign { } { } + assign $2\be_out[31:0] { \ibit 1'0 \ibit 21'000000000000000000000 \$51 } + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'1100 + assign { } { } + assign $2\be_out[31:0] { \ibit 1'0 \ibit 21'000000000000000000000 \$55 } + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'1101 + assign { } { } + assign $2\be_out[31:0] { \ibit 1'0 \ibit 21'000000000000000000000 \$59 } + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'1110 + assign { } { } + assign $2\be_out[31:0] { \ibit 1'0 \ibit 21'000000000000000000000 \$63 } + attribute \src "issuer_ls180.v:0.0-0.0" + case 4'---- + assign { } { } + assign $2\be_out[31:0] { \ibit 1'0 \ibit 21'000000000000000000000 \$67 } + case + assign $2\be_out[31:0] 0 + end + attribute \src "issuer_ls180.v:0.0-0.0" + case 3'-1- + assign { } { } + assign $1\be_out[31:0] 134217744 + attribute \src "issuer_ls180.v:0.0-0.0" + case 3'1-- + assign { } { } + assign $1\be_out[31:0] { \icp_r_src 20'00000000000000000000 \icp_r_pri } + case + assign $1\be_out[31:0] 0 + end + sync always + update \be_out $0\be_out[31:0] + end + attribute \src "issuer_ls180.v:182238.3-182247.6" + process $proc$issuer_ls180.v:182238$13694 + assign { } { } + assign { } { } + assign $0\cur_idx14[3:0] $1\cur_idx14[3:0] + attribute \src "issuer_ls180.v:182239.5-182239.29" + switch \initial + attribute \src "issuer_ls180.v:182239.9-182239.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" + switch \$193 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\cur_idx14[3:0] 4'1110 + case + assign $1\cur_idx14[3:0] \cur_idx13 + end + sync always + update \cur_idx14 $0\cur_idx14[3:0] + end + attribute \src "issuer_ls180.v:182248.3-182257.6" + process $proc$issuer_ls180.v:182248$13695 + assign { } { } + assign { } { } + assign $0\cur_pri15[7:0] $1\cur_pri15[7:0] + attribute \src "issuer_ls180.v:182249.5-182249.29" + switch \initial + attribute \src "issuer_ls180.v:182249.9-182249.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" + switch \$197 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\cur_pri15[7:0] \xive15_pri + case + assign $1\cur_pri15[7:0] \cur_pri14 + end + sync always + update \cur_pri15 $0\cur_pri15[7:0] + end + attribute \src "issuer_ls180.v:182258.3-182267.6" + process $proc$issuer_ls180.v:182258$13696 + assign { } { } + assign { } { } + assign $0\cur_idx15[3:0] $1\cur_idx15[3:0] + attribute \src "issuer_ls180.v:182259.5-182259.29" + switch \initial + attribute \src "issuer_ls180.v:182259.9-182259.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:369" + switch \$201 + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\cur_idx15[3:0] 4'1111 + case + assign $1\cur_idx15[3:0] \cur_idx14 + end + sync always + update \cur_idx15 $0\cur_idx15[3:0] + end + attribute \src "issuer_ls180.v:182268.3-182277.6" + process $proc$issuer_ls180.v:182268$13697 + assign { } { } + assign { } { } + assign $0\ibit[0:0] $1\ibit[0:0] + attribute \src "issuer_ls180.v:182269.5-182269.29" + switch \initial + attribute \src "issuer_ls180.v:182269.9-182269.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/soc/src/soc/interrupts/xics.py:312" + switch { \reg_is_debug \reg_is_config \reg_is_xive } + attribute \src "issuer_ls180.v:0.0-0.0" + case 3'--1 + assign { } { } + assign $1\ibit[0:0] \$71 + case + assign $1\ibit[0:0] 1'0 + end + sync always + update \ibit $0\ibit[0:0] + end + attribute \src "issuer_ls180.v:182278.3-182286.6" + process $proc$issuer_ls180.v:182278$13698 + assign { } { } + assign { } { } + assign $0\ics_wb__dat_r$next[31:0]$13699 $1\ics_wb__dat_r$next[31:0]$13700 + attribute \src "issuer_ls180.v:182279.5-182279.29" + switch \initial + attribute \src "issuer_ls180.v:182279.9-182279.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\ics_wb__dat_r$next[31:0]$13700 0 + case + assign $1\ics_wb__dat_r$next[31:0]$13700 { \be_out [7:0] \be_out [15:8] \be_out [23:16] \be_out [31:24] } + end + sync always + update \ics_wb__dat_r$next $0\ics_wb__dat_r$next[31:0]$13699 + end + attribute \src "issuer_ls180.v:182287.3-182295.6" + process $proc$issuer_ls180.v:182287$13701 + assign { } { } + assign { } { } + assign $0\ics_wb__ack$next[0:0]$13702 $1\ics_wb__ack$next[0:0]$13703 + attribute \src "issuer_ls180.v:182288.5-182288.29" + switch \initial + attribute \src "issuer_ls180.v:182288.9-182288.17" + case 1'1 + case + end + attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:532" + switch \rst + attribute \src "issuer_ls180.v:0.0-0.0" + case 1'1 + assign { } { } + assign $1\ics_wb__ack$next[0:0]$13703 1'0 + case + assign $1\ics_wb__ack$next[0:0]$13703 \wb_valid + end + sync always + update \ics_wb__ack$next $0\ics_wb__ack$next[0:0]$13702 + end + connect \$7 $ternary$issuer_ls180.v:181658$13456_Y + connect \$99 $lt$issuer_ls180.v:181659$13457_Y + connect \$101 $and$issuer_ls180.v:181660$13458_Y + connect \$103 $lt$issuer_ls180.v:181661$13459_Y + connect \$105 $and$issuer_ls180.v:181662$13460_Y + connect \$107 $lt$issuer_ls180.v:181663$13461_Y + connect \$109 $and$issuer_ls180.v:181664$13462_Y + connect \$111 $lt$issuer_ls180.v:181665$13463_Y + connect \$113 $and$issuer_ls180.v:181666$13464_Y + connect \$115 $lt$issuer_ls180.v:181667$13465_Y + connect \$117 $and$issuer_ls180.v:181668$13466_Y + connect \$119 $lt$issuer_ls180.v:181669$13467_Y + connect \$121 $and$issuer_ls180.v:181670$13468_Y + connect \$123 $lt$issuer_ls180.v:181671$13469_Y + connect \$125 $and$issuer_ls180.v:181672$13470_Y + connect \$127 $lt$issuer_ls180.v:181673$13471_Y + connect \$12 $eq$issuer_ls180.v:181674$13472_Y + connect \$129 $and$issuer_ls180.v:181675$13473_Y + connect \$131 $lt$issuer_ls180.v:181676$13474_Y + connect \$133 $and$issuer_ls180.v:181677$13475_Y + connect \$135 $lt$issuer_ls180.v:181678$13476_Y + connect \$137 $and$issuer_ls180.v:181679$13477_Y + connect \$11 $ternary$issuer_ls180.v:181680$13478_Y + connect \$139 $lt$issuer_ls180.v:181681$13479_Y + connect \$141 $and$issuer_ls180.v:181682$13480_Y + connect \$143 $lt$issuer_ls180.v:181683$13481_Y + connect \$145 $and$issuer_ls180.v:181684$13482_Y + connect \$147 $lt$issuer_ls180.v:181685$13483_Y + connect \$149 $and$issuer_ls180.v:181686$13484_Y + connect \$151 $lt$issuer_ls180.v:181687$13485_Y + connect \$153 $and$issuer_ls180.v:181688$13486_Y + connect \$155 $lt$issuer_ls180.v:181689$13487_Y + connect \$157 $and$issuer_ls180.v:181690$13488_Y + connect \$159 $lt$issuer_ls180.v:181691$13489_Y + connect \$161 $and$issuer_ls180.v:181692$13490_Y + connect \$163 $lt$issuer_ls180.v:181693$13491_Y + connect \$165 $and$issuer_ls180.v:181694$13492_Y + connect \$167 $lt$issuer_ls180.v:181695$13493_Y + connect \$16 $eq$issuer_ls180.v:181696$13494_Y + connect \$169 $and$issuer_ls180.v:181697$13495_Y + connect \$171 $lt$issuer_ls180.v:181698$13496_Y + connect \$173 $and$issuer_ls180.v:181699$13497_Y + connect \$175 $lt$issuer_ls180.v:181700$13498_Y + connect \$177 $and$issuer_ls180.v:181701$13499_Y + connect \$15 $ternary$issuer_ls180.v:181702$13500_Y + connect \$179 $lt$issuer_ls180.v:181703$13501_Y + connect \$181 $and$issuer_ls180.v:181704$13502_Y + connect \$183 $lt$issuer_ls180.v:181705$13503_Y + connect \$185 $and$issuer_ls180.v:181706$13504_Y + connect \$187 $lt$issuer_ls180.v:181707$13505_Y + connect \$189 $and$issuer_ls180.v:181708$13506_Y + connect \$191 $lt$issuer_ls180.v:181709$13507_Y + connect \$193 $and$issuer_ls180.v:181710$13508_Y + connect \$195 $lt$issuer_ls180.v:181711$13509_Y + connect \$197 $and$issuer_ls180.v:181712$13510_Y + connect \$1 $eq$issuer_ls180.v:181713$13511_Y + connect \$199 $lt$issuer_ls180.v:181714$13512_Y + connect \$201 $and$issuer_ls180.v:181715$13513_Y + connect \$204 $eq$issuer_ls180.v:181716$13514_Y + connect \$203 $ternary$issuer_ls180.v:181717$13515_Y + connect \$20 $eq$issuer_ls180.v:181718$13516_Y + connect \$19 $ternary$issuer_ls180.v:181719$13517_Y + connect \$24 $eq$issuer_ls180.v:181720$13518_Y + connect \$23 $ternary$issuer_ls180.v:181721$13519_Y + connect \$28 $eq$issuer_ls180.v:181722$13520_Y + connect \$27 $ternary$issuer_ls180.v:181723$13521_Y + connect \$32 $eq$issuer_ls180.v:181724$13522_Y + connect \$31 $ternary$issuer_ls180.v:181725$13523_Y + connect \$36 $eq$issuer_ls180.v:181726$13524_Y + connect \$35 $ternary$issuer_ls180.v:181727$13525_Y + connect \$3 $eq$issuer_ls180.v:181728$13526_Y + connect \$40 $eq$issuer_ls180.v:181729$13527_Y + connect \$39 $ternary$issuer_ls180.v:181730$13528_Y + connect \$44 $eq$issuer_ls180.v:181731$13529_Y + connect \$43 $ternary$issuer_ls180.v:181732$13530_Y + connect \$48 $eq$issuer_ls180.v:181733$13531_Y + connect \$47 $ternary$issuer_ls180.v:181734$13532_Y + connect \$52 $eq$issuer_ls180.v:181735$13533_Y + connect \$51 $ternary$issuer_ls180.v:181736$13534_Y + connect \$56 $eq$issuer_ls180.v:181737$13535_Y + connect \$55 $ternary$issuer_ls180.v:181738$13536_Y + connect \$5 $and$issuer_ls180.v:181739$13537_Y + connect \$60 $eq$issuer_ls180.v:181740$13538_Y + connect \$59 $ternary$issuer_ls180.v:181741$13539_Y + connect \$64 $eq$issuer_ls180.v:181742$13540_Y + connect \$63 $ternary$issuer_ls180.v:181743$13541_Y + connect \$68 $eq$issuer_ls180.v:181744$13542_Y + connect \$67 $ternary$issuer_ls180.v:181745$13543_Y + connect \$71 $shr$issuer_ls180.v:181746$13544_Y [0] + connect \$73 $and$issuer_ls180.v:181747$13545_Y + connect \$75 $lt$issuer_ls180.v:181748$13546_Y + connect \$77 $and$issuer_ls180.v:181749$13547_Y + connect \$79 $lt$issuer_ls180.v:181750$13548_Y + connect \$81 $and$issuer_ls180.v:181751$13549_Y + connect \$83 $lt$issuer_ls180.v:181752$13550_Y + connect \$85 $and$issuer_ls180.v:181753$13551_Y + connect \$87 $lt$issuer_ls180.v:181754$13552_Y + connect \$8 $eq$issuer_ls180.v:181755$13553_Y + connect \$89 $and$issuer_ls180.v:181756$13554_Y + connect \$91 $lt$issuer_ls180.v:181757$13555_Y + connect \$93 $and$issuer_ls180.v:181758$13556_Y + connect \$95 $lt$issuer_ls180.v:181759$13557_Y + connect \$97 $and$issuer_ls180.v:181760$13558_Y + connect \icp_r_pri \$203 + connect \icp_r_src \cur_idx15 + connect \max_idx 4'0000 + connect \max_pri 8'11111111 + connect { \icp_o_pri$next \icp_o_src$next } { \icp_r_pri \icp_r_src } + connect \be_in { \ics_wb__dat_w [7:0] \ics_wb__dat_w [15:8] \ics_wb__dat_w [23:16] \ics_wb__dat_w [31:24] } + connect \wb_valid \$5 + connect \reg_idx \ics_wb__adr [3:0] + connect \reg_is_debug \$3 + connect \reg_is_config \$1 + connect \reg_is_xive \ics_wb__adr [9] +end diff --git a/experiments9/non_generated/test_issuer.il b/experiments9/non_generated/test_issuer.il deleted file mode 100644 index 42b446a..0000000 --- a/experiments9/non_generated/test_issuer.il +++ /dev/null @@ -1,278106 +0,0 @@ -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.alu0.alu_alu0.p" -module \p - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" - wire width 1 input 0 \p_valid_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" - wire width 1 input 1 \p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:158" - wire width 1 \trigger - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" - cell $and $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \p_valid_i - connect \B \p_ready_o - connect \Y $1 - end - process $group_0 - assign \trigger 1'0 - assign \trigger $1 - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.alu0.alu_alu0.n" -module \n - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" - wire width 1 input 0 \n_valid_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" - wire width 1 input 1 \n_ready_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:251" - wire width 1 \trigger - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" - cell $and $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \n_ready_i - connect \B \n_valid_o - connect \Y $1 - end - process $group_0 - assign \trigger 1'0 - assign \trigger $1 - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.alu0.alu_alu0.pipe1.p" -module \p$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" - wire width 1 input 0 \p_valid_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" - wire width 1 input 1 \p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:158" - wire width 1 \trigger - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" - cell $and $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \p_valid_i - connect \B \p_ready_o - connect \Y $1 - end - process $group_0 - assign \trigger 1'0 - assign \trigger $1 - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.alu0.alu_alu0.pipe1.n" -module \n$2 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" - wire width 1 input 0 \n_valid_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" - wire width 1 input 1 \n_ready_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:251" - wire width 1 \trigger - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" - cell $and $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \n_ready_i - connect \B \n_valid_o - connect \Y $1 - end - process $group_0 - assign \trigger 1'0 - assign \trigger $1 - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.alu0.alu_alu0.pipe1.input" -module \input - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 input 0 \muxid - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute 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\enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 input 1 \alu_op__insn_type - attribute \enum_base_type "Function" - attribute \enum_value_00000000000 "NONE" - attribute \enum_value_00000000010 "ALU" - attribute \enum_value_00000000100 "LDST" - attribute \enum_value_00000001000 "SHIFT_ROT" - attribute \enum_value_00000010000 "LOGICAL" - attribute \enum_value_00000100000 "BRANCH" - attribute \enum_value_00001000000 "CR" - attribute \enum_value_00010000000 "TRAP" - attribute \enum_value_00100000000 "MUL" - attribute \enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 input 2 \alu_op__fn_unit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 input 3 \alu_op__imm_data__data - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 4 \alu_op__imm_data__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 5 \alu_op__rc__rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 6 \alu_op__rc__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 7 \alu_op__oe__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 8 \alu_op__oe__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 9 \alu_op__invert_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 10 \alu_op__zero_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 11 \alu_op__invert_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 12 \alu_op__write_cr0 - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 input 13 \alu_op__input_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 14 \alu_op__output_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 15 \alu_op__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 16 \alu_op__is_signed - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 input 17 \alu_op__data_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 input 18 \alu_op__insn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 19 \ra - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 20 \rb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 1 input 21 \xer_so - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 2 input 22 \xer_ca - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 output 23 \muxid$1 - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 output 24 \alu_op__insn_type$2 - attribute \enum_base_type "Function" - attribute \enum_value_00000000000 "NONE" - attribute \enum_value_00000000010 "ALU" - attribute \enum_value_00000000100 "LDST" - attribute \enum_value_00000001000 "SHIFT_ROT" - attribute \enum_value_00000010000 "LOGICAL" - attribute \enum_value_00000100000 "BRANCH" - attribute \enum_value_00001000000 "CR" - attribute \enum_value_00010000000 "TRAP" - attribute \enum_value_00100000000 "MUL" - attribute \enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 output 25 \alu_op__fn_unit$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 output 26 \alu_op__imm_data__data$4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 27 \alu_op__imm_data__ok$5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 28 \alu_op__rc__rc$6 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 29 \alu_op__rc__ok$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 30 \alu_op__oe__oe$8 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 31 \alu_op__oe__ok$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 32 \alu_op__invert_in$10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 33 \alu_op__zero_a$11 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 34 \alu_op__invert_out$12 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 35 \alu_op__write_cr0$13 - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 output 36 \alu_op__input_carry$14 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 37 \alu_op__output_carry$15 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 38 \alu_op__is_32bit$16 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 39 \alu_op__is_signed$17 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 output 40 \alu_op__data_len$18 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 output 41 \alu_op__insn$19 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 output 42 \o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 43 \o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 4 output 44 \cr_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 45 \cr_a_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 2 output 46 \xer_ca$20 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 47 \xer_ca_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 2 output 48 \xer_ov - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 49 \xer_ov_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 50 \xer_so$21 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:50" - wire width 1 \is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:52" - wire width 1 $22 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:52" - cell $eq $23 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A \alu_op__insn_type - connect \B 7'0001010 - connect \Y $22 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:53" - wire width 1 $24 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:53" - cell $not $25 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \alu_op__insn [21] - connect \Y $24 - end - process $group_0 - assign \is_32bit 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:52" - switch { $22 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:52" - case 1'1 - assign \is_32bit $24 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:61" - wire width 64 \a_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:63" - wire width 1 $26 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:63" - cell $eq $27 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A \alu_op__insn_type - connect \B 7'0001010 - connect \Y $26 - end - process $group_1 - assign \a_i 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:63" - switch { \is_32bit $26 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:63" - case 2'-1 - assign \a_i \ra - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:66" - case 2'1- - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:67" - switch { \alu_op__is_signed } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:67" - case 1'1 - assign \a_i { { \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] } \ra [31:0] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:70" - case - assign \a_i { { 1'0 1'0 1'0 1'0 1'0 1'0 1'0 1'0 1'0 1'0 1'0 1'0 1'0 1'0 1'0 1'0 1'0 1'0 1'0 1'0 1'0 1'0 1'0 1'0 1'0 1'0 1'0 1'0 1'0 1'0 1'0 1'0 } \ra [31:0] } - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:73" - case - assign \a_i \ra - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:62" - wire width 64 \b_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:63" - wire width 1 $28 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:63" - cell $eq $29 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A \alu_op__insn_type - connect \B 7'0001010 - connect \Y $28 - end - process $group_2 - assign \b_i 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:63" - switch { \is_32bit $28 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:63" - case 2'-1 - assign \b_i \rb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:66" - case 2'1- - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:67" - switch { \alu_op__is_signed } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:67" - case 1'1 - assign \b_i { { \rb [31:0] [31] \rb [31:0] [31] \rb [31:0] [31] \rb [31:0] [31] \rb [31:0] [31] \rb [31:0] [31] \rb [31:0] [31] \rb [31:0] [31] \rb [31:0] [31] \rb [31:0] [31] \rb [31:0] [31] \rb [31:0] [31] \rb [31:0] [31] \rb [31:0] [31] \rb [31:0] [31] \rb [31:0] [31] \rb [31:0] [31] \rb [31:0] [31] \rb [31:0] [31] \rb [31:0] [31] \rb [31:0] [31] \rb [31:0] [31] \rb [31:0] [31] \rb [31:0] [31] \rb [31:0] [31] \rb [31:0] [31] \rb [31:0] [31] \rb [31:0] [31] \rb [31:0] [31] \rb [31:0] [31] \rb [31:0] [31] \rb [31:0] [31] } \rb [31:0] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:70" - case - assign \b_i { { 1'0 1'0 1'0 1'0 1'0 1'0 1'0 1'0 1'0 1'0 1'0 1'0 1'0 1'0 1'0 1'0 1'0 1'0 1'0 1'0 1'0 1'0 1'0 1'0 1'0 1'0 1'0 1'0 1'0 1'0 1'0 1'0 } \rb [31:0] } - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:73" - case - assign \b_i \rb - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:57" - wire width 66 \add_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:77" - wire width 1 $30 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:77" - cell $eq $31 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A \alu_op__insn_type - connect \B 7'0000010 - connect \Y $30 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:78" - wire width 1 $32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:78" - cell $eq $33 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A \alu_op__insn_type - connect \B 7'0001010 - connect \Y $32 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:78" - wire width 1 $34 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:78" - cell $or $35 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $30 - connect \B $32 - connect \Y $34 - end - process $group_3 - assign \add_a 66'000000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:78" - switch { $34 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:78" - case 1'1 - assign \add_a { 1'0 \a_i \xer_ca [0] } - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:58" - wire width 66 \add_b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:77" - wire width 1 $36 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:77" - cell $eq $37 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A \alu_op__insn_type - connect \B 7'0000010 - connect \Y $36 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:78" - wire width 1 $38 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:78" - cell $eq $39 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A \alu_op__insn_type - connect \B 7'0001010 - connect \Y $38 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:78" - wire width 1 $40 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:78" - cell $or $41 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $36 - connect \B $38 - connect \Y $40 - end - process $group_4 - assign \add_b 66'000000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:78" - switch { $40 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:78" - case 1'1 - assign \add_b { 1'0 \b_i 1'1 } - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:59" - wire width 66 \add_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:77" - wire width 1 $42 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:77" - cell $eq $43 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A \alu_op__insn_type - connect \B 7'0000010 - connect \Y $42 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:78" - wire width 1 $44 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:78" - cell $eq $45 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A \alu_op__insn_type - connect \B 7'0001010 - connect \Y $44 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:78" - wire width 1 $46 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:78" - cell $or $47 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $42 - connect \B $44 - connect \Y $46 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:82" - wire width 67 $48 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:82" - wire width 67 $49 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:82" - cell $add $50 - parameter \A_SIGNED 0 - parameter \A_WIDTH 66 - parameter \B_SIGNED 0 - parameter \B_WIDTH 66 - parameter \Y_WIDTH 67 - connect \A \add_a - connect \B \add_b - connect \Y $49 - end - connect $48 $49 - process $group_5 - assign \add_o 66'000000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:78" - switch { $46 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:78" - case 1'1 - assign \add_o $48 [65:0] - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:93" - wire width 64 \a_n - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:105" - wire width 64 $51 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:105" - cell $not $52 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \Y_WIDTH 64 - connect \A \ra - connect \Y $51 - end - process $group_6 - assign \a_n 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:87" - switch \alu_op__insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:92" - attribute \nmigen.decoding "OP_CMP/10" - case 7'0001010 - assign \a_n $51 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:139" - attribute \nmigen.decoding "OP_ADD/2" - case 7'0000010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:161" - attribute \nmigen.decoding "OP_EXTS/31" - case 7'0011111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:173" - attribute \nmigen.decoding "OP_CMPEQB/12" - case 7'0001100 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:96" - wire width 1 \carry_32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:106" - wire width 1 $53 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:106" - cell $xor $54 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \add_o [33] - connect \B \ra [32] - connect \Y $53 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:106" - wire width 1 $55 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:106" - cell $xor $56 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $53 - connect \B \rb [32] - connect \Y $55 - end - process $group_7 - assign \carry_32 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:87" - switch \alu_op__insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:92" - attribute \nmigen.decoding "OP_CMP/10" - case 7'0001010 - assign \carry_32 $55 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:139" - attribute \nmigen.decoding "OP_ADD/2" - case 7'0000010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:161" - attribute \nmigen.decoding "OP_EXTS/31" - case 7'0011111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:173" - attribute \nmigen.decoding "OP_CMPEQB/12" - case 7'0001100 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:97" - wire width 1 \carry_64 - process $group_8 - assign \carry_64 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:87" - switch \alu_op__insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:92" - attribute \nmigen.decoding "OP_CMP/10" - case 7'0001010 - assign \carry_64 \add_o [65] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:139" - attribute \nmigen.decoding "OP_ADD/2" - case 7'0000010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:161" - attribute \nmigen.decoding "OP_EXTS/31" - case 7'0011111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:173" - attribute \nmigen.decoding "OP_CMPEQB/12" - case 7'0001100 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:98" - wire width 1 \zerolo - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:109" - wire width 1 $57 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:109" - wire width 1 $58 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:109" - wire width 32 $59 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:109" - cell $xor $60 - parameter \A_SIGNED 0 - parameter \A_WIDTH 32 - parameter \B_SIGNED 0 - parameter \B_WIDTH 32 - parameter \Y_WIDTH 32 - connect \A \a_n [31:0] - connect \B \rb [31:0] - connect \Y $59 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:109" - cell $reduce_bool $61 - parameter \A_SIGNED 0 - parameter \A_WIDTH 32 - parameter \Y_WIDTH 1 - connect \A $59 - connect \Y $58 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:109" - cell $not $62 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $58 - connect \Y $57 - end - process $group_9 - assign \zerolo 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:87" - switch \alu_op__insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:92" - attribute \nmigen.decoding "OP_CMP/10" - case 7'0001010 - assign \zerolo $57 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:139" - attribute \nmigen.decoding "OP_ADD/2" - case 7'0000010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:161" - attribute \nmigen.decoding "OP_EXTS/31" - case 7'0011111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:173" - attribute \nmigen.decoding "OP_CMPEQB/12" - case 7'0001100 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:99" - wire width 1 \zerohi - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:110" - wire width 1 $63 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:110" - wire width 1 $64 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:110" - wire width 32 $65 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:110" - cell $xor $66 - parameter \A_SIGNED 0 - parameter \A_WIDTH 32 - parameter \B_SIGNED 0 - parameter \B_WIDTH 32 - parameter \Y_WIDTH 32 - connect \A \a_n [63:32] - connect \B \rb [63:32] - connect \Y $65 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:110" - cell $reduce_bool $67 - parameter \A_SIGNED 0 - parameter \A_WIDTH 32 - parameter \Y_WIDTH 1 - connect \A $65 - connect \Y $64 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:110" - cell $not $68 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $64 - connect \Y $63 - end - process $group_10 - assign \zerohi 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:87" - switch \alu_op__insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:92" - attribute \nmigen.decoding "OP_CMP/10" - case 7'0001010 - assign \zerohi $63 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:139" - attribute \nmigen.decoding "OP_ADD/2" - case 7'0000010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:161" - attribute \nmigen.decoding "OP_EXTS/31" - case 7'0011111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:173" - attribute \nmigen.decoding "OP_CMPEQB/12" - case 7'0001100 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:94" - wire width 5 \tval - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:112" - wire width 1 $69 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:112" - cell $or $70 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \is_32bit - connect \B \zerohi - connect \Y $69 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:112" - wire width 1 $71 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:112" - cell $and $72 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \zerolo - connect \B $69 - connect \Y $71 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:100" - wire width 1 \msb_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:101" - wire width 1 \msb_b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:119" - wire width 1 $73 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:119" - cell $ne $74 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \msb_a - connect \B \msb_b - connect \Y $73 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:128" - wire width 1 $75 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:95" - wire width 1 \a_lt - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:128" - cell $not $76 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \a_lt - connect \Y $75 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:128" - wire width 1 $77 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:128" - cell $not $78 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \a_lt - connect \Y $77 - end - process $group_11 - assign \tval 5'00000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:87" - switch \alu_op__insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:92" - attribute \nmigen.decoding "OP_CMP/10" - case 7'0001010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:112" - switch { $71 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:112" - case 1'1 - assign \tval [2] 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:115" - case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:119" - switch { $73 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:119" - case 1'1 - assign \tval { \msb_a \msb_b 1'0 \msb_b \msb_a } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:124" - case - assign \tval { \a_lt $77 1'0 \a_lt $75 } - end - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:139" - attribute \nmigen.decoding "OP_ADD/2" - case 7'0000010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:161" - attribute \nmigen.decoding "OP_EXTS/31" - case 7'0011111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:173" - attribute \nmigen.decoding "OP_CMPEQB/12" - case 7'0001100 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:112" - wire width 1 $79 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:112" - cell $or $80 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \is_32bit - connect \B \zerohi - connect \Y $79 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:112" - wire width 1 $81 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:112" - cell $and $82 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \zerolo - connect \B $79 - connect \Y $81 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:116" - wire width 1 $83 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:116" - cell $mux $84 - parameter \WIDTH 1 - connect \A \a_n [63] - connect \B \a_n [31] - connect \S \is_32bit - connect \Y $83 - end - process $group_12 - assign \msb_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:87" - switch \alu_op__insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:92" - attribute \nmigen.decoding "OP_CMP/10" - case 7'0001010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:112" - switch { $81 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:112" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:115" - case - assign \msb_a $83 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:139" - attribute \nmigen.decoding "OP_ADD/2" - case 7'0000010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:161" - attribute \nmigen.decoding "OP_EXTS/31" - case 7'0011111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:173" - attribute \nmigen.decoding "OP_CMPEQB/12" - case 7'0001100 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:112" - wire width 1 $85 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:112" - cell $or $86 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \is_32bit - connect \B \zerohi - connect \Y $85 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:112" - wire width 1 $87 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:112" - cell $and $88 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \zerolo - connect \B $85 - connect \Y $87 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:117" - wire width 1 $89 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:117" - cell $mux $90 - parameter \WIDTH 1 - connect \A \rb [63] - connect \B \rb [31] - connect \S \is_32bit - connect \Y $89 - end - process $group_13 - assign \msb_b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:87" - switch \alu_op__insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:92" - attribute \nmigen.decoding "OP_CMP/10" - case 7'0001010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:112" - switch { $87 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:112" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:115" - case - assign \msb_b $89 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:139" - attribute \nmigen.decoding "OP_ADD/2" - case 7'0000010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:161" - attribute \nmigen.decoding "OP_EXTS/31" - case 7'0011111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:173" - attribute \nmigen.decoding "OP_CMPEQB/12" - case 7'0001100 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:112" - wire width 1 $91 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:112" - cell $or $92 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \is_32bit - connect \B \zerohi - connect \Y $91 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:112" - wire width 1 $93 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:112" - cell $and $94 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \zerolo - connect \B $91 - connect \Y $93 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:119" - wire width 1 $95 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:119" - cell $ne $96 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \msb_a - connect \B \msb_b - connect \Y $95 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:127" - wire width 1 $97 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:127" - cell $mux $98 - parameter \WIDTH 1 - connect \A \carry_64 - connect \B \carry_32 - connect \S \is_32bit - connect \Y $97 - end - process $group_14 - assign \a_lt 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:87" - switch \alu_op__insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:92" - attribute \nmigen.decoding "OP_CMP/10" - case 7'0001010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:112" - switch { $93 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:112" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:115" - case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:119" - switch { $95 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:119" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:124" - case - assign \a_lt $97 - end - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:139" - attribute \nmigen.decoding "OP_ADD/2" - case 7'0000010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:161" - attribute \nmigen.decoding "OP_EXTS/31" - case 7'0011111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:173" - attribute \nmigen.decoding "OP_CMPEQB/12" - case 7'0001100 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:181" - wire width 1 $99 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:174" - wire width 8 \eqs - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:181" - cell $reduce_or $100 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \eqs - connect \Y $99 - end - process $group_15 - assign \cr_a 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:87" - switch \alu_op__insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:92" - attribute \nmigen.decoding "OP_CMP/10" - case 7'0001010 - assign \cr_a [1:0] { \tval [2] \xer_so } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:130" - switch { \alu_op__is_signed } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:130" - case 1'1 - assign \cr_a [3:2] \tval [4:3] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:132" - case - assign \cr_a [3:2] \tval [1:0] - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:139" - attribute \nmigen.decoding "OP_ADD/2" - case 7'0000010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:161" - attribute \nmigen.decoding "OP_EXTS/31" - case 7'0011111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:173" - attribute \nmigen.decoding "OP_CMPEQB/12" - case 7'0001100 - assign \cr_a { 1'0 $99 2'00 } - end - sync init - end - process $group_16 - assign \cr_a_ok 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:87" - switch \alu_op__insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:92" - attribute \nmigen.decoding "OP_CMP/10" - case 7'0001010 - assign \cr_a_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:139" - attribute \nmigen.decoding "OP_ADD/2" - case 7'0000010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:161" - attribute \nmigen.decoding "OP_EXTS/31" - case 7'0011111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:173" - attribute \nmigen.decoding "OP_CMPEQB/12" - case 7'0001100 - assign \cr_a_ok 1'1 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:162" - wire width 1 $101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:162" - cell $eq $102 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \alu_op__data_len - connect \B 1'1 - connect \Y $101 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:164" - wire width 1 $103 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:164" - cell $eq $104 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \alu_op__data_len - connect \B 2'10 - connect \Y $103 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:166" - wire width 1 $105 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:166" - cell $eq $106 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \alu_op__data_len - connect \B 3'100 - connect \Y $105 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:179" - wire width 1 $107 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:179" - cell $reduce_or $108 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \eqs - connect \Y $107 - end - process $group_17 - assign \o 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:87" - switch \alu_op__insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:92" - attribute \nmigen.decoding "OP_CMP/10" - case 7'0001010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:139" - attribute \nmigen.decoding "OP_ADD/2" - case 7'0000010 - assign \o \add_o [64:1] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:161" - attribute \nmigen.decoding "OP_EXTS/31" - case 7'0011111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:162" - switch { $101 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:162" - case 1'1 - assign \o { { \ra [7:0] [7] \ra [7:0] [7] \ra [7:0] [7] \ra [7:0] [7] \ra [7:0] [7] \ra [7:0] [7] \ra [7:0] [7] \ra [7:0] [7] \ra [7:0] [7] \ra [7:0] [7] \ra [7:0] [7] \ra [7:0] [7] \ra [7:0] [7] \ra [7:0] [7] \ra [7:0] [7] \ra [7:0] [7] \ra [7:0] [7] \ra [7:0] [7] \ra [7:0] [7] \ra [7:0] [7] \ra [7:0] [7] \ra [7:0] [7] \ra [7:0] [7] \ra [7:0] [7] \ra [7:0] [7] \ra [7:0] [7] \ra [7:0] [7] \ra [7:0] [7] \ra [7:0] [7] \ra [7:0] [7] \ra [7:0] [7] \ra [7:0] [7] \ra [7:0] [7] \ra [7:0] [7] \ra [7:0] [7] \ra [7:0] [7] \ra [7:0] [7] \ra [7:0] [7] \ra [7:0] [7] \ra [7:0] [7] \ra [7:0] [7] \ra [7:0] [7] \ra [7:0] [7] \ra [7:0] [7] \ra [7:0] [7] \ra [7:0] [7] \ra [7:0] [7] \ra [7:0] [7] \ra [7:0] [7] \ra [7:0] [7] \ra [7:0] [7] \ra [7:0] [7] \ra [7:0] [7] \ra [7:0] [7] \ra [7:0] [7] \ra [7:0] [7] } \ra [7:0] } - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:164" - switch { $103 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:164" - case 1'1 - assign \o { { \ra [15:0] [15] \ra [15:0] [15] \ra [15:0] [15] \ra [15:0] [15] \ra [15:0] [15] \ra [15:0] [15] \ra [15:0] [15] \ra [15:0] [15] \ra [15:0] [15] \ra [15:0] [15] \ra [15:0] [15] \ra [15:0] [15] \ra [15:0] [15] \ra [15:0] [15] \ra [15:0] [15] \ra [15:0] [15] \ra [15:0] [15] \ra [15:0] [15] \ra [15:0] [15] \ra [15:0] [15] \ra [15:0] [15] \ra [15:0] [15] \ra [15:0] [15] \ra [15:0] [15] \ra [15:0] [15] \ra [15:0] [15] \ra [15:0] [15] \ra [15:0] [15] \ra [15:0] [15] \ra [15:0] [15] \ra [15:0] [15] \ra [15:0] [15] \ra [15:0] [15] \ra [15:0] [15] \ra [15:0] [15] \ra [15:0] [15] \ra [15:0] [15] \ra [15:0] [15] \ra [15:0] [15] \ra [15:0] [15] \ra [15:0] [15] \ra [15:0] [15] \ra [15:0] [15] \ra [15:0] [15] \ra [15:0] [15] \ra [15:0] [15] \ra [15:0] [15] \ra [15:0] [15] } \ra [15:0] } - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:166" - switch { $105 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:166" - case 1'1 - assign \o { { \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] } \ra [31:0] } - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:173" - attribute \nmigen.decoding "OP_CMPEQB/12" - case 7'0001100 - assign \o [0] $107 - end - sync init - end - process $group_18 - assign \o_ok 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:87" - switch \alu_op__insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:92" - attribute \nmigen.decoding "OP_CMP/10" - case 7'0001010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:139" - attribute \nmigen.decoding "OP_ADD/2" - case 7'0000010 - assign \o_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:161" - attribute \nmigen.decoding "OP_EXTS/31" - case 7'0011111 - assign \o_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:173" - attribute \nmigen.decoding "OP_CMPEQB/12" - case 7'0001100 - assign \o_ok 1'0 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:146" - wire width 2 \ca - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:148" - wire width 1 $109 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:148" - cell $xor $110 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \a_i [32] - connect \B \b_i [32] - connect \Y $109 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:148" - wire width 1 $111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:148" - cell $xor $112 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \add_o [33] - connect \B $109 - connect \Y $111 - end - process $group_19 - assign \ca 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:87" - switch \alu_op__insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:92" - attribute \nmigen.decoding "OP_CMP/10" - case 7'0001010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:139" - attribute \nmigen.decoding "OP_ADD/2" - case 7'0000010 - assign \ca [0] \add_o [65] - assign \ca [1] $111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:161" - attribute \nmigen.decoding "OP_EXTS/31" - case 7'0011111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:173" - attribute \nmigen.decoding "OP_CMPEQB/12" - case 7'0001100 - end - sync init - end - process $group_20 - assign \xer_ca$20 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:87" - switch \alu_op__insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:92" - attribute \nmigen.decoding "OP_CMP/10" - case 7'0001010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:139" - attribute \nmigen.decoding "OP_ADD/2" - case 7'0000010 - assign \xer_ca$20 \ca - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:161" - attribute \nmigen.decoding "OP_EXTS/31" - case 7'0011111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:173" - attribute \nmigen.decoding "OP_CMPEQB/12" - case 7'0001100 - end - sync init - end - process $group_21 - assign \xer_ca_ok 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:87" - switch \alu_op__insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:92" - attribute \nmigen.decoding "OP_CMP/10" - case 7'0001010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:139" - attribute \nmigen.decoding "OP_ADD/2" - case 7'0000010 - assign \xer_ca_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:161" - attribute \nmigen.decoding "OP_EXTS/31" - case 7'0011111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:173" - attribute \nmigen.decoding "OP_CMPEQB/12" - case 7'0001100 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:152" - wire width 2 \ov - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:21" - wire width 1 $113 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:21" - cell $xor $114 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \ca [0] - connect \B \add_o [64] - connect \Y $113 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:21" - wire width 1 $115 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:21" - wire width 1 $116 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:21" - cell $xor $117 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \a_i [63] - connect \B \b_i [63] - connect \Y $116 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:21" - cell $not $118 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $116 - connect \Y $115 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:21" - wire width 1 $119 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:21" - cell $and $120 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $113 - connect \B $115 - connect \Y $119 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:21" - wire width 1 $121 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:21" - cell $xor $122 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \ca [1] - connect \B \add_o [32] - connect \Y $121 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:21" - wire width 1 $123 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:21" - wire width 1 $124 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:21" - cell $xor $125 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \a_i [31] - connect \B \b_i [31] - connect \Y $124 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:21" - cell $not $126 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $124 - connect \Y $123 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:21" - wire width 1 $127 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:21" - cell $and $128 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $121 - connect \B $123 - connect \Y $127 - end - process $group_22 - assign \ov 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:87" - switch \alu_op__insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:92" - attribute \nmigen.decoding "OP_CMP/10" - case 7'0001010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:139" - attribute \nmigen.decoding "OP_ADD/2" - case 7'0000010 - assign \ov [0] $119 - assign \ov [1] $127 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:161" - attribute \nmigen.decoding "OP_EXTS/31" - case 7'0011111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:173" - attribute \nmigen.decoding "OP_CMPEQB/12" - case 7'0001100 - end - sync init - end - process $group_23 - assign \xer_ov 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:87" - switch \alu_op__insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:92" - attribute \nmigen.decoding "OP_CMP/10" - case 7'0001010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:139" - attribute \nmigen.decoding "OP_ADD/2" - case 7'0000010 - assign \xer_ov \ov - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:161" - attribute \nmigen.decoding "OP_EXTS/31" - case 7'0011111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:173" - attribute \nmigen.decoding "OP_CMPEQB/12" - case 7'0001100 - end - sync init - end - process $group_24 - assign \xer_ov_ok 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:87" - switch \alu_op__insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:92" - attribute \nmigen.decoding "OP_CMP/10" - case 7'0001010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:139" - attribute \nmigen.decoding "OP_ADD/2" - case 7'0000010 - assign \xer_ov_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:161" - attribute \nmigen.decoding "OP_EXTS/31" - case 7'0011111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:173" - attribute \nmigen.decoding "OP_CMPEQB/12" - case 7'0001100 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:175" - wire width 8 \src1 - process $group_25 - assign \src1 8'00000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:87" - switch \alu_op__insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:92" - attribute \nmigen.decoding "OP_CMP/10" - case 7'0001010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:139" - attribute \nmigen.decoding "OP_ADD/2" - case 7'0000010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:161" - attribute \nmigen.decoding "OP_EXTS/31" - case 7'0011111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:173" - attribute \nmigen.decoding "OP_CMPEQB/12" - case 7'0001100 - assign \src1 \ra [7:0] - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:178" - wire width 1 $129 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:178" - cell $eq $130 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \src1 - connect \B \rb [7:0] - connect \Y $129 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:178" - wire width 1 $131 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:178" - cell $eq $132 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \src1 - connect \B \rb [15:8] - connect \Y $131 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:178" - wire width 1 $133 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:178" - cell $eq $134 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \src1 - connect \B \rb [23:16] - connect \Y $133 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:178" - wire width 1 $135 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:178" - cell $eq $136 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \src1 - connect \B \rb [31:24] - connect \Y $135 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:178" - wire width 1 $137 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:178" - cell $eq $138 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \src1 - connect \B \rb [39:32] - connect \Y $137 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:178" - wire width 1 $139 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:178" - cell $eq $140 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \src1 - connect \B \rb [47:40] - connect \Y $139 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:178" - wire width 1 $141 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:178" - cell $eq $142 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \src1 - connect \B \rb [55:48] - connect \Y $141 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:178" - wire width 1 $143 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:178" - cell $eq $144 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \src1 - connect \B \rb [63:56] - connect \Y $143 - end - process $group_26 - assign \eqs 8'00000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:87" - switch \alu_op__insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:92" - attribute \nmigen.decoding "OP_CMP/10" - case 7'0001010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:139" - attribute \nmigen.decoding "OP_ADD/2" - case 7'0000010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:161" - attribute \nmigen.decoding "OP_EXTS/31" - case 7'0011111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/main_stage.py:173" - attribute \nmigen.decoding "OP_CMPEQB/12" - case 7'0001100 - assign \eqs [0] $129 - assign \eqs [1] $131 - assign \eqs [2] $133 - assign \eqs [3] $135 - assign \eqs [4] $137 - assign \eqs [5] $139 - assign \eqs [6] $141 - assign \eqs [7] $143 - end - sync init - end - process $group_27 - assign \xer_so$21 1'0 - assign \xer_so$21 \xer_so - sync init - end - process $group_28 - assign \muxid$1 2'00 - assign \muxid$1 \muxid - sync init - end - process $group_29 - assign \alu_op__insn_type$2 7'0000000 - assign \alu_op__fn_unit$3 11'00000000000 - assign \alu_op__imm_data__data$4 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \alu_op__imm_data__ok$5 1'0 - assign \alu_op__rc__rc$6 1'0 - assign \alu_op__rc__ok$7 1'0 - assign \alu_op__oe__oe$8 1'0 - assign \alu_op__oe__ok$9 1'0 - assign \alu_op__invert_in$10 1'0 - assign \alu_op__zero_a$11 1'0 - assign \alu_op__invert_out$12 1'0 - assign \alu_op__write_cr0$13 1'0 - assign \alu_op__input_carry$14 2'00 - assign \alu_op__output_carry$15 1'0 - assign \alu_op__is_32bit$16 1'0 - assign \alu_op__is_signed$17 1'0 - assign \alu_op__data_len$18 4'0000 - assign \alu_op__insn$19 32'00000000000000000000000000000000 - assign { \alu_op__insn$19 \alu_op__data_len$18 \alu_op__is_signed$17 \alu_op__is_32bit$16 \alu_op__output_carry$15 \alu_op__input_carry$14 \alu_op__write_cr0$13 \alu_op__invert_out$12 \alu_op__zero_a$11 \alu_op__invert_in$10 { \alu_op__oe__ok$9 \alu_op__oe__oe$8 } { \alu_op__rc__ok$7 \alu_op__rc__rc$6 } { \alu_op__imm_data__ok$5 \alu_op__imm_data__data$4 } \alu_op__fn_unit$3 \alu_op__insn_type$2 } { \alu_op__insn \alu_op__data_len \alu_op__is_signed \alu_op__is_32bit \alu_op__output_carry \alu_op__input_carry \alu_op__write_cr0 \alu_op__invert_out \alu_op__zero_a \alu_op__invert_in { \alu_op__oe__ok \alu_op__oe__oe } { \alu_op__rc__ok \alu_op__rc__rc } { \alu_op__imm_data__ok \alu_op__imm_data__data } \alu_op__fn_unit \alu_op__insn_type } - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.alu0.alu_alu0.pipe1" -module \pipe1 - attribute \src "simple/issuer.py:141" - wire width 1 input 0 \coresync_clk - attribute \src "simple/issuer.py:141" - wire width 1 input 1 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" - wire width 1 output 2 \n_valid_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" - wire width 1 input 3 \n_ready_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 output 4 \muxid - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \muxid$next - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 output 5 \alu_op__insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \alu_op__insn_type$next - attribute \enum_base_type "Function" - attribute \enum_value_00000000000 "NONE" - attribute \enum_value_00000000010 "ALU" - attribute \enum_value_00000000100 "LDST" - attribute \enum_value_00000001000 "SHIFT_ROT" - attribute \enum_value_00000010000 "LOGICAL" - attribute \enum_value_00000100000 "BRANCH" - attribute \enum_value_00001000000 "CR" - attribute \enum_value_00010000000 "TRAP" - attribute \enum_value_00100000000 "MUL" - attribute \enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 output 6 \alu_op__fn_unit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 \alu_op__fn_unit$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 output 7 \alu_op__imm_data__data - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \alu_op__imm_data__data$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 8 \alu_op__imm_data__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \alu_op__imm_data__ok$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 9 \alu_op__rc__rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \alu_op__rc__rc$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 10 \alu_op__rc__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \alu_op__rc__ok$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 11 \alu_op__oe__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \alu_op__oe__oe$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 12 \alu_op__oe__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \alu_op__oe__ok$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 13 \alu_op__invert_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \alu_op__invert_in$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 14 \alu_op__zero_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \alu_op__zero_a$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 15 \alu_op__invert_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \alu_op__invert_out$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 16 \alu_op__write_cr0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \alu_op__write_cr0$next - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 output 17 \alu_op__input_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \alu_op__input_carry$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 18 \alu_op__output_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \alu_op__output_carry$next - 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wire width 32 \input_alu_op__insn$40 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \input_ra$41 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \input_rb$42 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 1 \input_xer_so$43 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 2 \input_xer_ca$44 - cell \input \input - connect \muxid \input_muxid - connect \alu_op__insn_type \input_alu_op__insn_type - connect \alu_op__fn_unit \input_alu_op__fn_unit - connect \alu_op__imm_data__data \input_alu_op__imm_data__data - connect \alu_op__imm_data__ok \input_alu_op__imm_data__ok - connect \alu_op__rc__rc \input_alu_op__rc__rc - connect \alu_op__rc__ok \input_alu_op__rc__ok - connect \alu_op__oe__oe \input_alu_op__oe__oe - connect \alu_op__oe__ok \input_alu_op__oe__ok - connect \alu_op__invert_in \input_alu_op__invert_in - connect \alu_op__zero_a \input_alu_op__zero_a - connect \alu_op__invert_out \input_alu_op__invert_out - connect \alu_op__write_cr0 \input_alu_op__write_cr0 - connect \alu_op__input_carry \input_alu_op__input_carry - connect \alu_op__output_carry \input_alu_op__output_carry - connect \alu_op__is_32bit \input_alu_op__is_32bit - connect \alu_op__is_signed \input_alu_op__is_signed - connect \alu_op__data_len \input_alu_op__data_len - connect \alu_op__insn \input_alu_op__insn - connect \ra \input_ra - connect \rb \input_rb - connect \xer_so \input_xer_so - connect \xer_ca \input_xer_ca - connect \muxid$1 \input_muxid$22 - connect \alu_op__insn_type$2 \input_alu_op__insn_type$23 - connect \alu_op__fn_unit$3 \input_alu_op__fn_unit$24 - connect \alu_op__imm_data__data$4 \input_alu_op__imm_data__data$25 - connect \alu_op__imm_data__ok$5 \input_alu_op__imm_data__ok$26 - connect \alu_op__rc__rc$6 \input_alu_op__rc__rc$27 - connect \alu_op__rc__ok$7 \input_alu_op__rc__ok$28 - connect \alu_op__oe__oe$8 \input_alu_op__oe__oe$29 - connect \alu_op__oe__ok$9 \input_alu_op__oe__ok$30 - connect \alu_op__invert_in$10 \input_alu_op__invert_in$31 - connect \alu_op__zero_a$11 \input_alu_op__zero_a$32 - connect \alu_op__invert_out$12 \input_alu_op__invert_out$33 - connect \alu_op__write_cr0$13 \input_alu_op__write_cr0$34 - connect \alu_op__input_carry$14 \input_alu_op__input_carry$35 - connect \alu_op__output_carry$15 \input_alu_op__output_carry$36 - connect \alu_op__is_32bit$16 \input_alu_op__is_32bit$37 - connect \alu_op__is_signed$17 \input_alu_op__is_signed$38 - connect \alu_op__data_len$18 \input_alu_op__data_len$39 - connect \alu_op__insn$19 \input_alu_op__insn$40 - connect \ra$20 \input_ra$41 - connect \rb$21 \input_rb$42 - connect \xer_so$22 \input_xer_so$43 - connect \xer_ca$23 \input_xer_ca$44 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \main_muxid - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute 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"OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \main_alu_op__insn_type - attribute \enum_base_type "Function" - attribute \enum_value_00000000000 "NONE" - attribute \enum_value_00000000010 "ALU" - attribute \enum_value_00000000100 "LDST" - attribute \enum_value_00000001000 "SHIFT_ROT" - attribute \enum_value_00000010000 "LOGICAL" - attribute \enum_value_00000100000 "BRANCH" - attribute \enum_value_00001000000 "CR" - attribute \enum_value_00010000000 "TRAP" - attribute \enum_value_00100000000 "MUL" - attribute \enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 \main_alu_op__fn_unit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \main_alu_op__imm_data__data - attribute \src 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"/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \main_alu_op__write_cr0 - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \main_alu_op__input_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \main_alu_op__output_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \main_alu_op__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \main_alu_op__is_signed - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \main_alu_op__data_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \main_alu_op__insn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \main_ra - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \main_rb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 1 \main_xer_so - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 2 \main_xer_ca - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \main_muxid$45 - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute 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"/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 2 \main_xer_ca$64 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \main_xer_ca_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 2 \main_xer_ov - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \main_xer_ov_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \main_xer_so$65 - cell \main \main - connect \muxid \main_muxid - connect \alu_op__insn_type \main_alu_op__insn_type - connect \alu_op__fn_unit \main_alu_op__fn_unit - connect \alu_op__imm_data__data \main_alu_op__imm_data__data - connect \alu_op__imm_data__ok \main_alu_op__imm_data__ok - connect \alu_op__rc__rc \main_alu_op__rc__rc - connect \alu_op__rc__ok \main_alu_op__rc__ok - connect \alu_op__oe__oe \main_alu_op__oe__oe - connect \alu_op__oe__ok \main_alu_op__oe__ok - connect \alu_op__invert_in \main_alu_op__invert_in - connect \alu_op__zero_a \main_alu_op__zero_a - connect \alu_op__invert_out \main_alu_op__invert_out - connect \alu_op__write_cr0 \main_alu_op__write_cr0 - connect \alu_op__input_carry \main_alu_op__input_carry - connect \alu_op__output_carry \main_alu_op__output_carry - connect \alu_op__is_32bit \main_alu_op__is_32bit - connect \alu_op__is_signed \main_alu_op__is_signed - connect \alu_op__data_len \main_alu_op__data_len - connect \alu_op__insn \main_alu_op__insn - connect \ra \main_ra - connect \rb \main_rb - connect \xer_so \main_xer_so - connect \xer_ca \main_xer_ca - connect \muxid$1 \main_muxid$45 - connect \alu_op__insn_type$2 \main_alu_op__insn_type$46 - connect \alu_op__fn_unit$3 \main_alu_op__fn_unit$47 - connect \alu_op__imm_data__data$4 \main_alu_op__imm_data__data$48 - connect \alu_op__imm_data__ok$5 \main_alu_op__imm_data__ok$49 - connect \alu_op__rc__rc$6 \main_alu_op__rc__rc$50 - connect \alu_op__rc__ok$7 \main_alu_op__rc__ok$51 - connect \alu_op__oe__oe$8 \main_alu_op__oe__oe$52 - connect \alu_op__oe__ok$9 \main_alu_op__oe__ok$53 - connect \alu_op__invert_in$10 \main_alu_op__invert_in$54 - connect \alu_op__zero_a$11 \main_alu_op__zero_a$55 - connect \alu_op__invert_out$12 \main_alu_op__invert_out$56 - connect \alu_op__write_cr0$13 \main_alu_op__write_cr0$57 - connect \alu_op__input_carry$14 \main_alu_op__input_carry$58 - connect \alu_op__output_carry$15 \main_alu_op__output_carry$59 - connect \alu_op__is_32bit$16 \main_alu_op__is_32bit$60 - connect \alu_op__is_signed$17 \main_alu_op__is_signed$61 - connect \alu_op__data_len$18 \main_alu_op__data_len$62 - connect \alu_op__insn$19 \main_alu_op__insn$63 - connect \o \main_o - connect \o_ok \main_o_ok - connect \cr_a \main_cr_a - connect \cr_a_ok \main_cr_a_ok - connect \xer_ca$20 \main_xer_ca$64 - connect \xer_ca_ok \main_xer_ca_ok - connect \xer_ov \main_xer_ov - connect \xer_ov_ok \main_xer_ov_ok - connect \xer_so$21 \main_xer_so$65 - end - process $group_0 - assign \input_muxid 2'00 - assign \input_muxid \muxid$1 - sync init - end - process $group_1 - assign \input_alu_op__insn_type 7'0000000 - assign \input_alu_op__fn_unit 11'00000000000 - assign \input_alu_op__imm_data__data 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \input_alu_op__imm_data__ok 1'0 - assign \input_alu_op__rc__rc 1'0 - assign \input_alu_op__rc__ok 1'0 - assign \input_alu_op__oe__oe 1'0 - assign \input_alu_op__oe__ok 1'0 - assign \input_alu_op__invert_in 1'0 - assign \input_alu_op__zero_a 1'0 - assign \input_alu_op__invert_out 1'0 - assign \input_alu_op__write_cr0 1'0 - assign \input_alu_op__input_carry 2'00 - assign \input_alu_op__output_carry 1'0 - assign \input_alu_op__is_32bit 1'0 - assign \input_alu_op__is_signed 1'0 - assign \input_alu_op__data_len 4'0000 - assign \input_alu_op__insn 32'00000000000000000000000000000000 - assign { \input_alu_op__insn \input_alu_op__data_len \input_alu_op__is_signed \input_alu_op__is_32bit \input_alu_op__output_carry \input_alu_op__input_carry \input_alu_op__write_cr0 \input_alu_op__invert_out \input_alu_op__zero_a \input_alu_op__invert_in { \input_alu_op__oe__ok \input_alu_op__oe__oe } { \input_alu_op__rc__ok \input_alu_op__rc__rc } { \input_alu_op__imm_data__ok \input_alu_op__imm_data__data } \input_alu_op__fn_unit \input_alu_op__insn_type } { \alu_op__insn$19 \alu_op__data_len$18 \alu_op__is_signed$17 \alu_op__is_32bit$16 \alu_op__output_carry$15 \alu_op__input_carry$14 \alu_op__write_cr0$13 \alu_op__invert_out$12 \alu_op__zero_a$11 \alu_op__invert_in$10 { \alu_op__oe__ok$9 \alu_op__oe__oe$8 } { \alu_op__rc__ok$7 \alu_op__rc__rc$6 } { \alu_op__imm_data__ok$5 \alu_op__imm_data__data$4 } \alu_op__fn_unit$3 \alu_op__insn_type$2 } - sync init - end - process $group_19 - assign \input_ra 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \input_ra \ra - sync init - end - process $group_20 - assign \input_rb 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \input_rb \rb - sync init - end - process $group_21 - assign \input_xer_so 1'0 - assign \input_xer_so \xer_so$20 - sync init - end - process $group_22 - assign \input_xer_ca 2'00 - assign \input_xer_ca \xer_ca$21 - sync init - end - process $group_23 - assign \main_muxid 2'00 - assign \main_muxid \input_muxid$22 - sync init - end - process $group_24 - assign \main_alu_op__insn_type 7'0000000 - assign \main_alu_op__fn_unit 11'00000000000 - assign \main_alu_op__imm_data__data 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \main_alu_op__imm_data__ok 1'0 - assign \main_alu_op__rc__rc 1'0 - assign \main_alu_op__rc__ok 1'0 - assign \main_alu_op__oe__oe 1'0 - assign \main_alu_op__oe__ok 1'0 - assign \main_alu_op__invert_in 1'0 - assign \main_alu_op__zero_a 1'0 - assign \main_alu_op__invert_out 1'0 - assign \main_alu_op__write_cr0 1'0 - assign \main_alu_op__input_carry 2'00 - assign \main_alu_op__output_carry 1'0 - assign \main_alu_op__is_32bit 1'0 - assign \main_alu_op__is_signed 1'0 - assign \main_alu_op__data_len 4'0000 - assign \main_alu_op__insn 32'00000000000000000000000000000000 - assign { \main_alu_op__insn \main_alu_op__data_len \main_alu_op__is_signed \main_alu_op__is_32bit \main_alu_op__output_carry \main_alu_op__input_carry \main_alu_op__write_cr0 \main_alu_op__invert_out \main_alu_op__zero_a \main_alu_op__invert_in { \main_alu_op__oe__ok \main_alu_op__oe__oe } { \main_alu_op__rc__ok \main_alu_op__rc__rc } { \main_alu_op__imm_data__ok \main_alu_op__imm_data__data } \main_alu_op__fn_unit \main_alu_op__insn_type } { \input_alu_op__insn$40 \input_alu_op__data_len$39 \input_alu_op__is_signed$38 \input_alu_op__is_32bit$37 \input_alu_op__output_carry$36 \input_alu_op__input_carry$35 \input_alu_op__write_cr0$34 \input_alu_op__invert_out$33 \input_alu_op__zero_a$32 \input_alu_op__invert_in$31 { \input_alu_op__oe__ok$30 \input_alu_op__oe__oe$29 } { \input_alu_op__rc__ok$28 \input_alu_op__rc__rc$27 } { \input_alu_op__imm_data__ok$26 \input_alu_op__imm_data__data$25 } \input_alu_op__fn_unit$24 \input_alu_op__insn_type$23 } - sync init - end - process $group_42 - assign \main_ra 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \main_ra \input_ra$41 - sync init - end - process $group_43 - assign \main_rb 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \main_rb \input_rb$42 - sync init - end - process $group_44 - assign \main_xer_so 1'0 - assign \main_xer_so \input_xer_so$43 - sync init - end - process $group_45 - assign \main_xer_ca 2'00 - assign \main_xer_ca \input_xer_ca$44 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:621" - wire width 1 \p_valid_i$66 - process $group_46 - assign \p_valid_i$66 1'0 - assign \p_valid_i$66 \p_valid_i - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:619" - wire width 1 \n_i_rdy_data - process $group_47 - assign \n_i_rdy_data 1'0 - assign \n_i_rdy_data \n_ready_i - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" - wire width 1 \p_valid_i_p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" - wire width 1 $67 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" - cell $and $68 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \p_valid_i$66 - connect \B \p_ready_o - connect \Y $67 - end - process $group_48 - assign \p_valid_i_p_ready_o 1'0 - assign \p_valid_i_p_ready_o $67 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \muxid$69 - process $group_49 - assign \muxid$69 2'00 - assign \muxid$69 \main_muxid$45 - sync init - end - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \alu_op__insn_type$70 - attribute \enum_base_type "Function" - attribute \enum_value_00000000000 "NONE" - attribute \enum_value_00000000010 "ALU" - attribute \enum_value_00000000100 "LDST" - attribute \enum_value_00000001000 "SHIFT_ROT" - attribute \enum_value_00000010000 "LOGICAL" - attribute \enum_value_00000100000 "BRANCH" - attribute \enum_value_00001000000 "CR" - attribute \enum_value_00010000000 "TRAP" - attribute \enum_value_00100000000 "MUL" - attribute \enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 \alu_op__fn_unit$71 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \alu_op__imm_data__data$72 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \alu_op__imm_data__ok$73 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \alu_op__rc__rc$74 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \alu_op__rc__ok$75 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \alu_op__oe__oe$76 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \alu_op__oe__ok$77 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \alu_op__invert_in$78 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \alu_op__zero_a$79 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \alu_op__invert_out$80 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \alu_op__write_cr0$81 - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \alu_op__input_carry$82 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \alu_op__output_carry$83 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \alu_op__is_32bit$84 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \alu_op__is_signed$85 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \alu_op__data_len$86 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \alu_op__insn$87 - process $group_50 - assign \alu_op__insn_type$70 7'0000000 - assign \alu_op__fn_unit$71 11'00000000000 - assign \alu_op__imm_data__data$72 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \alu_op__imm_data__ok$73 1'0 - assign \alu_op__rc__rc$74 1'0 - assign \alu_op__rc__ok$75 1'0 - assign \alu_op__oe__oe$76 1'0 - assign \alu_op__oe__ok$77 1'0 - assign \alu_op__invert_in$78 1'0 - assign \alu_op__zero_a$79 1'0 - assign \alu_op__invert_out$80 1'0 - assign \alu_op__write_cr0$81 1'0 - assign \alu_op__input_carry$82 2'00 - assign \alu_op__output_carry$83 1'0 - assign \alu_op__is_32bit$84 1'0 - assign \alu_op__is_signed$85 1'0 - assign \alu_op__data_len$86 4'0000 - assign \alu_op__insn$87 32'00000000000000000000000000000000 - assign { \alu_op__insn$87 \alu_op__data_len$86 \alu_op__is_signed$85 \alu_op__is_32bit$84 \alu_op__output_carry$83 \alu_op__input_carry$82 \alu_op__write_cr0$81 \alu_op__invert_out$80 \alu_op__zero_a$79 \alu_op__invert_in$78 { \alu_op__oe__ok$77 \alu_op__oe__oe$76 } { \alu_op__rc__ok$75 \alu_op__rc__rc$74 } { \alu_op__imm_data__ok$73 \alu_op__imm_data__data$72 } \alu_op__fn_unit$71 \alu_op__insn_type$70 } { \main_alu_op__insn$63 \main_alu_op__data_len$62 \main_alu_op__is_signed$61 \main_alu_op__is_32bit$60 \main_alu_op__output_carry$59 \main_alu_op__input_carry$58 \main_alu_op__write_cr0$57 \main_alu_op__invert_out$56 \main_alu_op__zero_a$55 \main_alu_op__invert_in$54 { \main_alu_op__oe__ok$53 \main_alu_op__oe__oe$52 } { \main_alu_op__rc__ok$51 \main_alu_op__rc__rc$50 } { \main_alu_op__imm_data__ok$49 \main_alu_op__imm_data__data$48 } \main_alu_op__fn_unit$47 \main_alu_op__insn_type$46 } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 \o$88 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \o_ok$89 - process $group_68 - assign \o$88 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \o_ok$89 1'0 - assign { \o_ok$89 \o$88 } { \main_o_ok \main_o } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 4 \cr_a$90 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \cr_a_ok$91 - process $group_70 - assign \cr_a$90 4'0000 - assign \cr_a_ok$91 1'0 - assign { \cr_a_ok$91 \cr_a$90 } { \main_cr_a_ok \main_cr_a } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 2 \xer_ca$92 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \xer_ca_ok$93 - process $group_72 - assign \xer_ca$92 2'00 - assign \xer_ca_ok$93 1'0 - assign { \xer_ca_ok$93 \xer_ca$92 } { \main_xer_ca_ok \main_xer_ca$64 } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 2 \xer_ov$94 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \xer_ov_ok$95 - process $group_74 - assign \xer_ov$94 2'00 - assign \xer_ov_ok$95 1'0 - assign { \xer_ov_ok$95 \xer_ov$94 } { \main_xer_ov_ok \main_xer_ov } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \xer_so$96 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \xer_so_ok$97 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \xer_so_ok$98 - process $group_76 - assign \xer_so$96 1'0 - assign \xer_so_ok$97 1'0 - assign { \xer_so_ok$97 \xer_so$96 } { \xer_so_ok$98 \main_xer_so$65 } - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615" - wire width 1 \r_busy - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615" - wire width 1 \r_busy$next - process $group_78 - assign \r_busy$next \r_busy - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign \r_busy$next 1'1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign \r_busy$next 1'0 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \r_busy$next 1'0 - end - sync init - update \r_busy 1'0 - sync posedge \coresync_clk - update \r_busy \r_busy$next - end - process $group_79 - assign \muxid$next \muxid - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign \muxid$next \muxid$69 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign \muxid$next \muxid$69 - end - sync init - update \muxid 2'00 - sync posedge \coresync_clk - update \muxid \muxid$next - end - process $group_80 - assign \alu_op__insn_type$next \alu_op__insn_type - assign \alu_op__fn_unit$next \alu_op__fn_unit - assign \alu_op__imm_data__data$next \alu_op__imm_data__data - assign \alu_op__imm_data__ok$next \alu_op__imm_data__ok - assign \alu_op__rc__rc$next \alu_op__rc__rc - assign \alu_op__rc__ok$next \alu_op__rc__ok - assign \alu_op__oe__oe$next \alu_op__oe__oe - assign \alu_op__oe__ok$next \alu_op__oe__ok - assign \alu_op__invert_in$next \alu_op__invert_in - assign \alu_op__zero_a$next \alu_op__zero_a - assign \alu_op__invert_out$next \alu_op__invert_out - assign \alu_op__write_cr0$next \alu_op__write_cr0 - assign \alu_op__input_carry$next \alu_op__input_carry - assign \alu_op__output_carry$next \alu_op__output_carry - assign \alu_op__is_32bit$next \alu_op__is_32bit - assign \alu_op__is_signed$next \alu_op__is_signed - assign \alu_op__data_len$next \alu_op__data_len - assign \alu_op__insn$next \alu_op__insn - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign { \alu_op__insn$next \alu_op__data_len$next \alu_op__is_signed$next \alu_op__is_32bit$next \alu_op__output_carry$next \alu_op__input_carry$next \alu_op__write_cr0$next \alu_op__invert_out$next \alu_op__zero_a$next \alu_op__invert_in$next { \alu_op__oe__ok$next \alu_op__oe__oe$next } { \alu_op__rc__ok$next \alu_op__rc__rc$next } { \alu_op__imm_data__ok$next \alu_op__imm_data__data$next } \alu_op__fn_unit$next \alu_op__insn_type$next } { \alu_op__insn$87 \alu_op__data_len$86 \alu_op__is_signed$85 \alu_op__is_32bit$84 \alu_op__output_carry$83 \alu_op__input_carry$82 \alu_op__write_cr0$81 \alu_op__invert_out$80 \alu_op__zero_a$79 \alu_op__invert_in$78 { \alu_op__oe__ok$77 \alu_op__oe__oe$76 } { \alu_op__rc__ok$75 \alu_op__rc__rc$74 } { \alu_op__imm_data__ok$73 \alu_op__imm_data__data$72 } \alu_op__fn_unit$71 \alu_op__insn_type$70 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign { \alu_op__insn$next \alu_op__data_len$next \alu_op__is_signed$next \alu_op__is_32bit$next \alu_op__output_carry$next \alu_op__input_carry$next \alu_op__write_cr0$next \alu_op__invert_out$next \alu_op__zero_a$next \alu_op__invert_in$next { \alu_op__oe__ok$next \alu_op__oe__oe$next } { \alu_op__rc__ok$next \alu_op__rc__rc$next } { \alu_op__imm_data__ok$next \alu_op__imm_data__data$next } \alu_op__fn_unit$next \alu_op__insn_type$next } { \alu_op__insn$87 \alu_op__data_len$86 \alu_op__is_signed$85 \alu_op__is_32bit$84 \alu_op__output_carry$83 \alu_op__input_carry$82 \alu_op__write_cr0$81 \alu_op__invert_out$80 \alu_op__zero_a$79 \alu_op__invert_in$78 { \alu_op__oe__ok$77 \alu_op__oe__oe$76 } { \alu_op__rc__ok$75 \alu_op__rc__rc$74 } { \alu_op__imm_data__ok$73 \alu_op__imm_data__data$72 } \alu_op__fn_unit$71 \alu_op__insn_type$70 } - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \alu_op__imm_data__data$next 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \alu_op__imm_data__ok$next 1'0 - assign \alu_op__rc__rc$next 1'0 - assign \alu_op__rc__ok$next 1'0 - assign \alu_op__oe__oe$next 1'0 - assign \alu_op__oe__ok$next 1'0 - end - sync init - update \alu_op__insn_type 7'0000000 - update \alu_op__fn_unit 11'00000000000 - update \alu_op__imm_data__data 64'0000000000000000000000000000000000000000000000000000000000000000 - update \alu_op__imm_data__ok 1'0 - update \alu_op__rc__rc 1'0 - update \alu_op__rc__ok 1'0 - update \alu_op__oe__oe 1'0 - update \alu_op__oe__ok 1'0 - update \alu_op__invert_in 1'0 - update \alu_op__zero_a 1'0 - update \alu_op__invert_out 1'0 - update \alu_op__write_cr0 1'0 - update \alu_op__input_carry 2'00 - update \alu_op__output_carry 1'0 - update \alu_op__is_32bit 1'0 - update \alu_op__is_signed 1'0 - update \alu_op__data_len 4'0000 - update \alu_op__insn 32'00000000000000000000000000000000 - sync posedge \coresync_clk - update \alu_op__insn_type \alu_op__insn_type$next - update \alu_op__fn_unit \alu_op__fn_unit$next - update \alu_op__imm_data__data \alu_op__imm_data__data$next - update \alu_op__imm_data__ok \alu_op__imm_data__ok$next - update \alu_op__rc__rc \alu_op__rc__rc$next - update \alu_op__rc__ok \alu_op__rc__ok$next - update \alu_op__oe__oe \alu_op__oe__oe$next - update \alu_op__oe__ok \alu_op__oe__ok$next - update \alu_op__invert_in \alu_op__invert_in$next - update \alu_op__zero_a \alu_op__zero_a$next - update \alu_op__invert_out \alu_op__invert_out$next - update \alu_op__write_cr0 \alu_op__write_cr0$next - update \alu_op__input_carry \alu_op__input_carry$next - update \alu_op__output_carry \alu_op__output_carry$next - update \alu_op__is_32bit \alu_op__is_32bit$next - update \alu_op__is_signed \alu_op__is_signed$next - update \alu_op__data_len \alu_op__data_len$next - update \alu_op__insn \alu_op__insn$next - end - process $group_98 - assign \o$next \o - assign \o_ok$next \o_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign { \o_ok$next \o$next } { \o_ok$89 \o$88 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign { \o_ok$next \o$next } { \o_ok$89 \o$88 } - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \o_ok$next 1'0 - end - sync init - update \o 64'0000000000000000000000000000000000000000000000000000000000000000 - update \o_ok 1'0 - sync posedge \coresync_clk - update \o \o$next - update \o_ok \o_ok$next - end - process $group_100 - assign \cr_a$next \cr_a - assign \cr_a_ok$next \cr_a_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign { \cr_a_ok$next \cr_a$next } { \cr_a_ok$91 \cr_a$90 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign { \cr_a_ok$next \cr_a$next } { \cr_a_ok$91 \cr_a$90 } - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \cr_a_ok$next 1'0 - end - sync init - update \cr_a 4'0000 - update \cr_a_ok 1'0 - sync posedge \coresync_clk - update \cr_a \cr_a$next - update \cr_a_ok \cr_a_ok$next - end - process $group_102 - assign \xer_ca$next \xer_ca - assign \xer_ca_ok$next \xer_ca_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign { \xer_ca_ok$next \xer_ca$next } { \xer_ca_ok$93 \xer_ca$92 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign { \xer_ca_ok$next \xer_ca$next } { \xer_ca_ok$93 \xer_ca$92 } - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \xer_ca_ok$next 1'0 - end - sync init - update \xer_ca 2'00 - update \xer_ca_ok 1'0 - sync posedge \coresync_clk - update \xer_ca \xer_ca$next - update \xer_ca_ok \xer_ca_ok$next - end - process $group_104 - assign \xer_ov$next \xer_ov - assign \xer_ov_ok$next \xer_ov_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign { \xer_ov_ok$next \xer_ov$next } { \xer_ov_ok$95 \xer_ov$94 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign { \xer_ov_ok$next \xer_ov$next } { \xer_ov_ok$95 \xer_ov$94 } - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \xer_ov_ok$next 1'0 - end - sync init - update \xer_ov 2'00 - update \xer_ov_ok 1'0 - sync posedge \coresync_clk - update \xer_ov \xer_ov$next - update \xer_ov_ok \xer_ov_ok$next - end - process $group_106 - assign \xer_so$next \xer_so - assign \xer_so_ok$next \xer_so_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign { \xer_so_ok$next \xer_so$next } { \xer_so_ok$97 \xer_so$96 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign { \xer_so_ok$next \xer_so$next } { \xer_so_ok$97 \xer_so$96 } - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \xer_so_ok$next 1'0 - end - sync init - update \xer_so 1'0 - update \xer_so_ok 1'0 - sync posedge \coresync_clk - update \xer_so \xer_so$next - update \xer_so_ok \xer_so_ok$next - end - process $group_108 - assign \n_valid_o 1'0 - assign \n_valid_o \r_busy - sync init - end - process $group_109 - assign \p_ready_o 1'0 - assign \p_ready_o \n_i_rdy_data - sync init - end - connect \xer_so_ok$98 1'0 -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.alu0.alu_alu0.pipe2.p" -module \p$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" - wire width 1 input 0 \p_valid_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" - wire width 1 input 1 \p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:158" - wire width 1 \trigger - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" - cell $and $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \p_valid_i - connect \B \p_ready_o - connect \Y $1 - end - process $group_0 - assign \trigger 1'0 - assign \trigger $1 - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.alu0.alu_alu0.pipe2.n" -module \n$4 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" - wire width 1 input 0 \n_valid_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" - wire width 1 input 1 \n_ready_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:251" - wire width 1 \trigger - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" - cell $and $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \n_ready_i - connect \B \n_valid_o - connect \Y $1 - end - process $group_0 - assign \trigger 1'0 - assign \trigger $1 - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.alu0.alu_alu0.pipe2.output" -module \output - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 input 0 \muxid - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 input 1 \alu_op__insn_type - attribute \enum_base_type "Function" - attribute \enum_value_00000000000 "NONE" - attribute \enum_value_00000000010 "ALU" - attribute \enum_value_00000000100 "LDST" - attribute \enum_value_00000001000 "SHIFT_ROT" - attribute \enum_value_00000010000 "LOGICAL" - attribute \enum_value_00000100000 "BRANCH" - attribute \enum_value_00001000000 "CR" - attribute \enum_value_00010000000 "TRAP" - attribute \enum_value_00100000000 "MUL" - attribute \enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 input 2 \alu_op__fn_unit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 input 3 \alu_op__imm_data__data - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 4 \alu_op__imm_data__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 5 \alu_op__rc__rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 6 \alu_op__rc__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 7 \alu_op__oe__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 8 \alu_op__oe__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 9 \alu_op__invert_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 10 \alu_op__zero_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 11 \alu_op__invert_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 12 \alu_op__write_cr0 - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 input 13 \alu_op__input_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 14 \alu_op__output_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 15 \alu_op__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 16 \alu_op__is_signed - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 input 17 \alu_op__data_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 input 18 \alu_op__insn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 input 19 \o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 input 20 \o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 4 input 21 \cr_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 2 input 22 \xer_ca - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 2 input 23 \xer_ov - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 input 24 \xer_so - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 output 25 \muxid$1 - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute 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\enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 output 26 \alu_op__insn_type$2 - attribute \enum_base_type "Function" - attribute \enum_value_00000000000 "NONE" - attribute \enum_value_00000000010 "ALU" - attribute \enum_value_00000000100 "LDST" - attribute \enum_value_00000001000 "SHIFT_ROT" - attribute \enum_value_00000010000 "LOGICAL" - attribute \enum_value_00000100000 "BRANCH" - attribute \enum_value_00001000000 "CR" - attribute \enum_value_00010000000 "TRAP" - attribute \enum_value_00100000000 "MUL" - attribute \enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 output 27 \alu_op__fn_unit$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 output 28 \alu_op__imm_data__data$4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 29 \alu_op__imm_data__ok$5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 30 \alu_op__rc__rc$6 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 31 \alu_op__rc__ok$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 32 \alu_op__oe__oe$8 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 33 \alu_op__oe__ok$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 34 \alu_op__invert_in$10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 35 \alu_op__zero_a$11 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 36 \alu_op__invert_out$12 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 37 \alu_op__write_cr0$13 - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 output 38 \alu_op__input_carry$14 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 39 \alu_op__output_carry$15 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 40 \alu_op__is_32bit$16 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 41 \alu_op__is_signed$17 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 output 42 \alu_op__data_len$18 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 output 43 \alu_op__insn$19 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 output 44 \o$20 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 45 \o_ok$21 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 4 output 46 \cr_a$22 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 47 \cr_a_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 2 output 48 \xer_ca$23 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 49 \xer_ca_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 2 output 50 \xer_ov$24 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 51 \xer_ov_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 52 \xer_so$25 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 53 \xer_so_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:28" - wire width 1 \oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:29" - wire width 1 $26 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:29" - cell $and $27 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \alu_op__oe__oe - connect \B \alu_op__oe__ok - connect \Y $26 - end - process $group_0 - assign \oe 1'0 - assign \oe $26 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:27" - wire width 1 \so - process $group_1 - assign \so 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:30" - switch { \oe } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:30" - case 1'1 - assign \so \xer_so$25 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:32" - case - assign \so \xer_so - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:38" - wire width 65 \o$28 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:41" - wire width 65 $29 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:41" - wire width 64 $30 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:41" - cell $not $31 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \Y_WIDTH 64 - connect \A \o - connect \Y $30 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:41" - cell $pos $32 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \Y_WIDTH 65 - connect \A $30 - connect \Y $29 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 65 $33 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - cell $pos $34 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \Y_WIDTH 65 - connect \A \o - connect \Y $33 - end - process $group_2 - assign \o$28 65'00000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:40" - switch { \alu_op__invert_out } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:40" - case 1'1 - assign \o$28 $29 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:42" - case - assign \o$28 $33 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:50" - wire width 64 \target - process $group_3 - assign \target 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \target \o$28 [63:0] - sync init - end - process $group_4 - assign \xer_ca$23 2'00 - assign \xer_ca$23 \xer_ca - sync init - end - process $group_5 - assign \xer_ca_ok 1'0 - assign \xer_ca_ok \alu_op__output_carry - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:69" - wire width 1 \is_cmp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:77" - wire width 1 $35 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:77" - cell $eq $36 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A \alu_op__insn_type - connect \B 7'0001010 - connect \Y $35 - end - process $group_6 - assign \is_cmp 1'0 - assign \is_cmp $35 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:70" - wire width 1 \is_cmpeqb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:78" - wire width 1 $37 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:78" - cell $eq $38 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A \alu_op__insn_type - connect \B 7'0001100 - connect \Y $37 - end - process $group_7 - assign \is_cmpeqb 1'0 - assign \is_cmpeqb $37 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:68" - wire width 1 \msb_test - process $group_8 - assign \msb_test 1'0 - assign \msb_test \target [63] - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:65" - wire width 1 \is_nzero - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:81" - wire width 1 $39 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:81" - cell $reduce_bool $40 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \Y_WIDTH 1 - connect \A \target - connect \Y $39 - end - process $group_9 - assign \is_nzero 1'0 - assign \is_nzero $39 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:67" - wire width 1 \is_negative - process $group_10 - assign \is_negative 1'0 - assign \is_negative \msb_test - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:66" - wire width 1 \is_positive - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:83" - wire width 1 $41 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:83" - cell $not $42 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \msb_test - connect \Y $41 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:83" - wire width 1 $43 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:83" - cell $and $44 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \is_nzero - connect \B $41 - connect \Y $43 - end - process $group_11 - assign \is_positive 1'0 - assign \is_positive $43 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:71" - wire width 4 \cr0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:85" - wire width 1 $45 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:85" - cell $or $46 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \is_cmpeqb - connect \B \is_cmp - connect \Y $45 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:88" - wire width 1 $47 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:88" - cell $not $48 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \is_nzero - connect \Y $47 - end - process $group_12 - assign \cr0 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:85" - switch { $45 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:85" - case 1'1 - assign \cr0 \cr_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:87" - case - assign \cr0 { \is_negative \is_positive $47 \so } - end - sync init - end - process $group_13 - assign \o$20 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \o$20 \o$28 [63:0] - sync init - end - process $group_14 - assign \o_ok$21 1'0 - assign \o_ok$21 \o_ok - sync init - end - process $group_15 - assign \cr_a$22 4'0000 - assign \cr_a$22 \cr0 - sync init - end - process $group_16 - assign \cr_a_ok 1'0 - assign \cr_a_ok \alu_op__write_cr0 - sync init - end - process $group_17 - assign \muxid$1 2'00 - assign \muxid$1 \muxid - sync init - end - process $group_18 - assign \alu_op__insn_type$2 7'0000000 - assign \alu_op__fn_unit$3 11'00000000000 - assign \alu_op__imm_data__data$4 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \alu_op__imm_data__ok$5 1'0 - assign \alu_op__rc__rc$6 1'0 - assign \alu_op__rc__ok$7 1'0 - assign \alu_op__oe__oe$8 1'0 - assign \alu_op__oe__ok$9 1'0 - assign \alu_op__invert_in$10 1'0 - assign \alu_op__zero_a$11 1'0 - assign \alu_op__invert_out$12 1'0 - assign \alu_op__write_cr0$13 1'0 - assign \alu_op__input_carry$14 2'00 - assign \alu_op__output_carry$15 1'0 - assign \alu_op__is_32bit$16 1'0 - assign \alu_op__is_signed$17 1'0 - assign \alu_op__data_len$18 4'0000 - assign \alu_op__insn$19 32'00000000000000000000000000000000 - assign { \alu_op__insn$19 \alu_op__data_len$18 \alu_op__is_signed$17 \alu_op__is_32bit$16 \alu_op__output_carry$15 \alu_op__input_carry$14 \alu_op__write_cr0$13 \alu_op__invert_out$12 \alu_op__zero_a$11 \alu_op__invert_in$10 { \alu_op__oe__ok$9 \alu_op__oe__oe$8 } { \alu_op__rc__ok$7 \alu_op__rc__rc$6 } { \alu_op__imm_data__ok$5 \alu_op__imm_data__data$4 } \alu_op__fn_unit$3 \alu_op__insn_type$2 } { \alu_op__insn \alu_op__data_len \alu_op__is_signed \alu_op__is_32bit \alu_op__output_carry \alu_op__input_carry \alu_op__write_cr0 \alu_op__invert_out \alu_op__zero_a \alu_op__invert_in { \alu_op__oe__ok \alu_op__oe__oe } { \alu_op__rc__ok \alu_op__rc__rc } { \alu_op__imm_data__ok \alu_op__imm_data__data } \alu_op__fn_unit \alu_op__insn_type } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:29" - wire width 1 \oe$49 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:30" - wire width 1 $50 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:30" - cell $and $51 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \alu_op__oe__oe - connect \B \alu_op__oe__ok - connect \Y $50 - end - process $group_36 - assign \oe$49 1'0 - assign \oe$49 $50 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:33" - wire width 1 $52 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:33" - cell $or $53 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \xer_so - connect \B \xer_ov [0] - connect \Y $52 - end - process $group_37 - assign \xer_so$25 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:31" - switch { \oe$49 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:31" - case 1'1 - assign \xer_so$25 $52 - end - sync init - end - process $group_38 - assign \xer_so_ok 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:31" - switch { \oe$49 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:31" - case 1'1 - assign \xer_so_ok 1'1 - end - sync init - end - process $group_39 - assign \xer_ov$24 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:31" - switch { \oe$49 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:31" - case 1'1 - assign \xer_ov$24 \xer_ov - end - sync init - end - process $group_40 - assign \xer_ov_ok 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:31" - switch { \oe$49 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:31" - case 1'1 - assign \xer_ov_ok 1'1 - end - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.alu0.alu_alu0.pipe2" -module \pipe2 - attribute \src "simple/issuer.py:141" - wire width 1 input 0 \coresync_clk - attribute \src "simple/issuer.py:141" - wire width 1 input 1 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" - wire width 1 input 2 \p_valid_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" - wire width 1 output 3 \p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" 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- attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute 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input 7 \alu_op__imm_data__data - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 8 \alu_op__imm_data__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 9 \alu_op__rc__rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 10 \alu_op__rc__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 11 \alu_op__oe__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 12 \alu_op__oe__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 13 \alu_op__invert_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 14 \alu_op__zero_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 15 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width 32 input 22 \alu_op__insn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 input 23 \o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 input 24 \o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 4 input 25 \cr_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 input 26 \cr_a_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 2 input 27 \xer_ca - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 input 28 \xer_ca_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 2 input 29 \xer_ov - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 input 30 \xer_ov_ok - attribute \src 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\alu_op__output_carry$15$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 50 \alu_op__is_32bit$16 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \alu_op__is_32bit$16$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 51 \alu_op__is_signed$17 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \alu_op__is_signed$17$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 output 52 \alu_op__data_len$18 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \alu_op__data_len$18$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 output 53 \alu_op__insn$19 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire 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attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute 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attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \output_alu_op__output_carry$44 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \output_alu_op__is_32bit$45 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \output_alu_op__is_signed$46 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \output_alu_op__data_len$47 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \output_alu_op__insn$48 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 \output_o$49 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \output_o_ok$50 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 4 \output_cr_a$51 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \output_cr_a_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 2 \output_xer_ca$52 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \output_xer_ca_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 2 \output_xer_ov$53 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \output_xer_ov_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \output_xer_so$54 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \output_xer_so_ok - cell \output \output - connect \muxid \output_muxid - connect \alu_op__insn_type \output_alu_op__insn_type - connect \alu_op__fn_unit \output_alu_op__fn_unit - connect \alu_op__imm_data__data \output_alu_op__imm_data__data - connect \alu_op__imm_data__ok \output_alu_op__imm_data__ok - connect \alu_op__rc__rc \output_alu_op__rc__rc - connect \alu_op__rc__ok \output_alu_op__rc__ok - connect \alu_op__oe__oe \output_alu_op__oe__oe - connect \alu_op__oe__ok \output_alu_op__oe__ok - connect \alu_op__invert_in \output_alu_op__invert_in - connect \alu_op__zero_a \output_alu_op__zero_a - connect \alu_op__invert_out \output_alu_op__invert_out - connect \alu_op__write_cr0 \output_alu_op__write_cr0 - connect \alu_op__input_carry \output_alu_op__input_carry - connect \alu_op__output_carry \output_alu_op__output_carry - connect \alu_op__is_32bit \output_alu_op__is_32bit - connect \alu_op__is_signed \output_alu_op__is_signed - connect \alu_op__data_len \output_alu_op__data_len - connect \alu_op__insn \output_alu_op__insn - connect \o \output_o - connect \o_ok \output_o_ok - connect \cr_a \output_cr_a - connect \xer_ca \output_xer_ca - connect \xer_ov \output_xer_ov - connect \xer_so \output_xer_so - connect \muxid$1 \output_muxid$30 - connect \alu_op__insn_type$2 \output_alu_op__insn_type$31 - connect \alu_op__fn_unit$3 \output_alu_op__fn_unit$32 - connect \alu_op__imm_data__data$4 \output_alu_op__imm_data__data$33 - connect \alu_op__imm_data__ok$5 \output_alu_op__imm_data__ok$34 - connect \alu_op__rc__rc$6 \output_alu_op__rc__rc$35 - connect \alu_op__rc__ok$7 \output_alu_op__rc__ok$36 - connect \alu_op__oe__oe$8 \output_alu_op__oe__oe$37 - connect \alu_op__oe__ok$9 \output_alu_op__oe__ok$38 - connect \alu_op__invert_in$10 \output_alu_op__invert_in$39 - connect \alu_op__zero_a$11 \output_alu_op__zero_a$40 - connect \alu_op__invert_out$12 \output_alu_op__invert_out$41 - connect \alu_op__write_cr0$13 \output_alu_op__write_cr0$42 - connect \alu_op__input_carry$14 \output_alu_op__input_carry$43 - connect \alu_op__output_carry$15 \output_alu_op__output_carry$44 - connect \alu_op__is_32bit$16 \output_alu_op__is_32bit$45 - connect \alu_op__is_signed$17 \output_alu_op__is_signed$46 - connect \alu_op__data_len$18 \output_alu_op__data_len$47 - connect \alu_op__insn$19 \output_alu_op__insn$48 - connect \o$20 \output_o$49 - connect \o_ok$21 \output_o_ok$50 - connect \cr_a$22 \output_cr_a$51 - connect \cr_a_ok \output_cr_a_ok - connect \xer_ca$23 \output_xer_ca$52 - connect \xer_ca_ok \output_xer_ca_ok - connect \xer_ov$24 \output_xer_ov$53 - connect \xer_ov_ok \output_xer_ov_ok - connect \xer_so$25 \output_xer_so$54 - connect \xer_so_ok \output_xer_so_ok - end - process $group_0 - assign \output_muxid 2'00 - assign \output_muxid \muxid - sync init - end - process $group_1 - assign \output_alu_op__insn_type 7'0000000 - assign \output_alu_op__fn_unit 11'00000000000 - assign \output_alu_op__imm_data__data 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \output_alu_op__imm_data__ok 1'0 - assign \output_alu_op__rc__rc 1'0 - assign \output_alu_op__rc__ok 1'0 - assign \output_alu_op__oe__oe 1'0 - assign \output_alu_op__oe__ok 1'0 - assign \output_alu_op__invert_in 1'0 - assign \output_alu_op__zero_a 1'0 - assign \output_alu_op__invert_out 1'0 - assign \output_alu_op__write_cr0 1'0 - assign \output_alu_op__input_carry 2'00 - assign \output_alu_op__output_carry 1'0 - assign \output_alu_op__is_32bit 1'0 - assign \output_alu_op__is_signed 1'0 - assign \output_alu_op__data_len 4'0000 - assign \output_alu_op__insn 32'00000000000000000000000000000000 - assign { \output_alu_op__insn \output_alu_op__data_len \output_alu_op__is_signed \output_alu_op__is_32bit \output_alu_op__output_carry \output_alu_op__input_carry \output_alu_op__write_cr0 \output_alu_op__invert_out \output_alu_op__zero_a \output_alu_op__invert_in { \output_alu_op__oe__ok \output_alu_op__oe__oe } { \output_alu_op__rc__ok \output_alu_op__rc__rc } { \output_alu_op__imm_data__ok \output_alu_op__imm_data__data } \output_alu_op__fn_unit \output_alu_op__insn_type } { \alu_op__insn \alu_op__data_len \alu_op__is_signed \alu_op__is_32bit \alu_op__output_carry \alu_op__input_carry \alu_op__write_cr0 \alu_op__invert_out \alu_op__zero_a \alu_op__invert_in { \alu_op__oe__ok \alu_op__oe__oe } { \alu_op__rc__ok \alu_op__rc__rc } { \alu_op__imm_data__ok \alu_op__imm_data__data } \alu_op__fn_unit \alu_op__insn_type } - sync init - end - process $group_19 - assign \output_o 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \output_o_ok 1'0 - assign { \output_o_ok \output_o } { \o_ok \o } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \cr_a_ok$55 - process $group_21 - assign \output_cr_a 4'0000 - assign \cr_a_ok$55 1'0 - assign { \cr_a_ok$55 \output_cr_a } { \cr_a_ok \cr_a } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \xer_ca_ok$56 - process $group_23 - assign \output_xer_ca 2'00 - assign \xer_ca_ok$56 1'0 - assign { \xer_ca_ok$56 \output_xer_ca } { \xer_ca_ok \xer_ca } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \xer_ov_ok$57 - process $group_25 - assign \output_xer_ov 2'00 - assign \xer_ov_ok$57 1'0 - assign { \xer_ov_ok$57 \output_xer_ov } { \xer_ov_ok \xer_ov } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \xer_so_ok$58 - process $group_27 - assign \output_xer_so 1'0 - assign \xer_so_ok$58 1'0 - assign { \xer_so_ok$58 \output_xer_so } { \xer_so_ok \xer_so } - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:621" - wire width 1 \p_valid_i$59 - process $group_29 - assign \p_valid_i$59 1'0 - assign \p_valid_i$59 \p_valid_i - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:619" - wire width 1 \n_i_rdy_data - process $group_30 - assign \n_i_rdy_data 1'0 - assign \n_i_rdy_data \n_ready_i - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" - wire width 1 \p_valid_i_p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" - wire width 1 $60 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" - cell $and $61 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \p_valid_i$59 - connect \B \p_ready_o - connect \Y $60 - end - process $group_31 - assign \p_valid_i_p_ready_o 1'0 - assign \p_valid_i_p_ready_o $60 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \muxid$62 - process $group_32 - assign \muxid$62 2'00 - assign \muxid$62 \output_muxid$30 - sync init - end - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \alu_op__insn_type$63 - attribute \enum_base_type "Function" - attribute \enum_value_00000000000 "NONE" - attribute \enum_value_00000000010 "ALU" - attribute \enum_value_00000000100 "LDST" - attribute \enum_value_00000001000 "SHIFT_ROT" - attribute \enum_value_00000010000 "LOGICAL" - attribute \enum_value_00000100000 "BRANCH" - attribute \enum_value_00001000000 "CR" - attribute \enum_value_00010000000 "TRAP" - attribute \enum_value_00100000000 "MUL" - attribute \enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 \alu_op__fn_unit$64 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \alu_op__imm_data__data$65 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \alu_op__imm_data__ok$66 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \alu_op__rc__rc$67 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \alu_op__rc__ok$68 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \alu_op__oe__oe$69 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \alu_op__oe__ok$70 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \alu_op__invert_in$71 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \alu_op__zero_a$72 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \alu_op__invert_out$73 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \alu_op__write_cr0$74 - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \alu_op__input_carry$75 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \alu_op__output_carry$76 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \alu_op__is_32bit$77 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \alu_op__is_signed$78 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \alu_op__data_len$79 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \alu_op__insn$80 - process $group_33 - assign \alu_op__insn_type$63 7'0000000 - assign \alu_op__fn_unit$64 11'00000000000 - assign \alu_op__imm_data__data$65 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \alu_op__imm_data__ok$66 1'0 - assign \alu_op__rc__rc$67 1'0 - assign \alu_op__rc__ok$68 1'0 - assign \alu_op__oe__oe$69 1'0 - assign \alu_op__oe__ok$70 1'0 - assign \alu_op__invert_in$71 1'0 - assign \alu_op__zero_a$72 1'0 - assign \alu_op__invert_out$73 1'0 - assign \alu_op__write_cr0$74 1'0 - assign \alu_op__input_carry$75 2'00 - assign \alu_op__output_carry$76 1'0 - assign \alu_op__is_32bit$77 1'0 - assign \alu_op__is_signed$78 1'0 - assign \alu_op__data_len$79 4'0000 - assign \alu_op__insn$80 32'00000000000000000000000000000000 - assign { \alu_op__insn$80 \alu_op__data_len$79 \alu_op__is_signed$78 \alu_op__is_32bit$77 \alu_op__output_carry$76 \alu_op__input_carry$75 \alu_op__write_cr0$74 \alu_op__invert_out$73 \alu_op__zero_a$72 \alu_op__invert_in$71 { \alu_op__oe__ok$70 \alu_op__oe__oe$69 } { \alu_op__rc__ok$68 \alu_op__rc__rc$67 } { \alu_op__imm_data__ok$66 \alu_op__imm_data__data$65 } \alu_op__fn_unit$64 \alu_op__insn_type$63 } { \output_alu_op__insn$48 \output_alu_op__data_len$47 \output_alu_op__is_signed$46 \output_alu_op__is_32bit$45 \output_alu_op__output_carry$44 \output_alu_op__input_carry$43 \output_alu_op__write_cr0$42 \output_alu_op__invert_out$41 \output_alu_op__zero_a$40 \output_alu_op__invert_in$39 { \output_alu_op__oe__ok$38 \output_alu_op__oe__oe$37 } { \output_alu_op__rc__ok$36 \output_alu_op__rc__rc$35 } { \output_alu_op__imm_data__ok$34 \output_alu_op__imm_data__data$33 } \output_alu_op__fn_unit$32 \output_alu_op__insn_type$31 } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 \o$81 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \o_ok$82 - process $group_51 - assign \o$81 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \o_ok$82 1'0 - assign { \o_ok$82 \o$81 } { \output_o_ok$50 \output_o$49 } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 4 \cr_a$83 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \cr_a_ok$84 - process $group_53 - assign \cr_a$83 4'0000 - assign \cr_a_ok$84 1'0 - assign { \cr_a_ok$84 \cr_a$83 } { \output_cr_a_ok \output_cr_a$51 } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 2 \xer_ca$85 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \xer_ca_ok$86 - process $group_55 - assign \xer_ca$85 2'00 - assign \xer_ca_ok$86 1'0 - assign { \xer_ca_ok$86 \xer_ca$85 } { \output_xer_ca_ok \output_xer_ca$52 } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 2 \xer_ov$87 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \xer_ov_ok$88 - process $group_57 - assign \xer_ov$87 2'00 - assign \xer_ov_ok$88 1'0 - assign { \xer_ov_ok$88 \xer_ov$87 } { \output_xer_ov_ok \output_xer_ov$53 } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \xer_so$89 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \xer_so_ok$90 - process $group_59 - assign \xer_so$89 1'0 - assign \xer_so_ok$90 1'0 - assign { \xer_so_ok$90 \xer_so$89 } { \output_xer_so_ok \output_xer_so$54 } - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615" - wire width 1 \r_busy - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615" - wire width 1 \r_busy$next - process $group_61 - assign \r_busy$next \r_busy - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign \r_busy$next 1'1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign \r_busy$next 1'0 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \r_busy$next 1'0 - end - sync init - update \r_busy 1'0 - sync posedge \coresync_clk - update \r_busy \r_busy$next - end - process $group_62 - assign \muxid$1$next \muxid$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign \muxid$1$next \muxid$62 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign \muxid$1$next \muxid$62 - end - sync init - update \muxid$1 2'00 - sync posedge \coresync_clk - update \muxid$1 \muxid$1$next - end - process $group_63 - assign \alu_op__insn_type$2$next \alu_op__insn_type$2 - assign \alu_op__fn_unit$3$next \alu_op__fn_unit$3 - assign \alu_op__imm_data__data$4$next \alu_op__imm_data__data$4 - assign \alu_op__imm_data__ok$5$next \alu_op__imm_data__ok$5 - assign \alu_op__rc__rc$6$next \alu_op__rc__rc$6 - assign \alu_op__rc__ok$7$next \alu_op__rc__ok$7 - assign \alu_op__oe__oe$8$next \alu_op__oe__oe$8 - assign \alu_op__oe__ok$9$next \alu_op__oe__ok$9 - assign \alu_op__invert_in$10$next \alu_op__invert_in$10 - assign \alu_op__zero_a$11$next \alu_op__zero_a$11 - assign \alu_op__invert_out$12$next \alu_op__invert_out$12 - assign \alu_op__write_cr0$13$next \alu_op__write_cr0$13 - assign \alu_op__input_carry$14$next \alu_op__input_carry$14 - assign \alu_op__output_carry$15$next \alu_op__output_carry$15 - assign \alu_op__is_32bit$16$next \alu_op__is_32bit$16 - assign \alu_op__is_signed$17$next \alu_op__is_signed$17 - assign \alu_op__data_len$18$next \alu_op__data_len$18 - assign \alu_op__insn$19$next \alu_op__insn$19 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign { \alu_op__insn$19$next \alu_op__data_len$18$next \alu_op__is_signed$17$next \alu_op__is_32bit$16$next \alu_op__output_carry$15$next \alu_op__input_carry$14$next \alu_op__write_cr0$13$next \alu_op__invert_out$12$next \alu_op__zero_a$11$next \alu_op__invert_in$10$next { \alu_op__oe__ok$9$next \alu_op__oe__oe$8$next } { \alu_op__rc__ok$7$next \alu_op__rc__rc$6$next } { \alu_op__imm_data__ok$5$next \alu_op__imm_data__data$4$next } \alu_op__fn_unit$3$next \alu_op__insn_type$2$next } { \alu_op__insn$80 \alu_op__data_len$79 \alu_op__is_signed$78 \alu_op__is_32bit$77 \alu_op__output_carry$76 \alu_op__input_carry$75 \alu_op__write_cr0$74 \alu_op__invert_out$73 \alu_op__zero_a$72 \alu_op__invert_in$71 { \alu_op__oe__ok$70 \alu_op__oe__oe$69 } { \alu_op__rc__ok$68 \alu_op__rc__rc$67 } { \alu_op__imm_data__ok$66 \alu_op__imm_data__data$65 } \alu_op__fn_unit$64 \alu_op__insn_type$63 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign { \alu_op__insn$19$next \alu_op__data_len$18$next \alu_op__is_signed$17$next \alu_op__is_32bit$16$next \alu_op__output_carry$15$next \alu_op__input_carry$14$next \alu_op__write_cr0$13$next \alu_op__invert_out$12$next \alu_op__zero_a$11$next \alu_op__invert_in$10$next { \alu_op__oe__ok$9$next \alu_op__oe__oe$8$next } { \alu_op__rc__ok$7$next \alu_op__rc__rc$6$next } { \alu_op__imm_data__ok$5$next \alu_op__imm_data__data$4$next } \alu_op__fn_unit$3$next \alu_op__insn_type$2$next } { \alu_op__insn$80 \alu_op__data_len$79 \alu_op__is_signed$78 \alu_op__is_32bit$77 \alu_op__output_carry$76 \alu_op__input_carry$75 \alu_op__write_cr0$74 \alu_op__invert_out$73 \alu_op__zero_a$72 \alu_op__invert_in$71 { \alu_op__oe__ok$70 \alu_op__oe__oe$69 } { \alu_op__rc__ok$68 \alu_op__rc__rc$67 } { \alu_op__imm_data__ok$66 \alu_op__imm_data__data$65 } \alu_op__fn_unit$64 \alu_op__insn_type$63 } - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \alu_op__imm_data__data$4$next 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \alu_op__imm_data__ok$5$next 1'0 - assign \alu_op__rc__rc$6$next 1'0 - assign \alu_op__rc__ok$7$next 1'0 - assign \alu_op__oe__oe$8$next 1'0 - assign \alu_op__oe__ok$9$next 1'0 - end - sync init - update \alu_op__insn_type$2 7'0000000 - update \alu_op__fn_unit$3 11'00000000000 - update \alu_op__imm_data__data$4 64'0000000000000000000000000000000000000000000000000000000000000000 - update \alu_op__imm_data__ok$5 1'0 - update \alu_op__rc__rc$6 1'0 - update \alu_op__rc__ok$7 1'0 - update \alu_op__oe__oe$8 1'0 - update \alu_op__oe__ok$9 1'0 - update \alu_op__invert_in$10 1'0 - update \alu_op__zero_a$11 1'0 - update \alu_op__invert_out$12 1'0 - update \alu_op__write_cr0$13 1'0 - update \alu_op__input_carry$14 2'00 - update \alu_op__output_carry$15 1'0 - update \alu_op__is_32bit$16 1'0 - update \alu_op__is_signed$17 1'0 - update \alu_op__data_len$18 4'0000 - update \alu_op__insn$19 32'00000000000000000000000000000000 - sync posedge \coresync_clk - update \alu_op__insn_type$2 \alu_op__insn_type$2$next - update \alu_op__fn_unit$3 \alu_op__fn_unit$3$next - update \alu_op__imm_data__data$4 \alu_op__imm_data__data$4$next - update \alu_op__imm_data__ok$5 \alu_op__imm_data__ok$5$next - update \alu_op__rc__rc$6 \alu_op__rc__rc$6$next - update \alu_op__rc__ok$7 \alu_op__rc__ok$7$next - update \alu_op__oe__oe$8 \alu_op__oe__oe$8$next - update \alu_op__oe__ok$9 \alu_op__oe__ok$9$next - update \alu_op__invert_in$10 \alu_op__invert_in$10$next - update \alu_op__zero_a$11 \alu_op__zero_a$11$next - update \alu_op__invert_out$12 \alu_op__invert_out$12$next - update \alu_op__write_cr0$13 \alu_op__write_cr0$13$next - update \alu_op__input_carry$14 \alu_op__input_carry$14$next - update \alu_op__output_carry$15 \alu_op__output_carry$15$next - update \alu_op__is_32bit$16 \alu_op__is_32bit$16$next - update \alu_op__is_signed$17 \alu_op__is_signed$17$next - update \alu_op__data_len$18 \alu_op__data_len$18$next - update \alu_op__insn$19 \alu_op__insn$19$next - end - process $group_81 - assign \o$20$next \o$20 - assign \o_ok$21$next \o_ok$21 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign { \o_ok$21$next \o$20$next } { \o_ok$82 \o$81 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign { \o_ok$21$next \o$20$next } { \o_ok$82 \o$81 } - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \o_ok$21$next 1'0 - end - sync init - update \o$20 64'0000000000000000000000000000000000000000000000000000000000000000 - update \o_ok$21 1'0 - sync posedge \coresync_clk - update \o$20 \o$20$next - update \o_ok$21 \o_ok$21$next - end - process $group_83 - assign \cr_a$22$next \cr_a$22 - assign \cr_a_ok$23$next \cr_a_ok$23 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign { \cr_a_ok$23$next \cr_a$22$next } { \cr_a_ok$84 \cr_a$83 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign { \cr_a_ok$23$next \cr_a$22$next } { \cr_a_ok$84 \cr_a$83 } - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \cr_a_ok$23$next 1'0 - end - sync init - update \cr_a$22 4'0000 - update \cr_a_ok$23 1'0 - sync posedge \coresync_clk - update \cr_a$22 \cr_a$22$next - update \cr_a_ok$23 \cr_a_ok$23$next - end - process $group_85 - assign \xer_ca$24$next \xer_ca$24 - assign \xer_ca_ok$25$next \xer_ca_ok$25 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign { \xer_ca_ok$25$next \xer_ca$24$next } { \xer_ca_ok$86 \xer_ca$85 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign { \xer_ca_ok$25$next \xer_ca$24$next } { \xer_ca_ok$86 \xer_ca$85 } - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \xer_ca_ok$25$next 1'0 - end - sync init - update \xer_ca$24 2'00 - update \xer_ca_ok$25 1'0 - sync posedge \coresync_clk - update \xer_ca$24 \xer_ca$24$next - update \xer_ca_ok$25 \xer_ca_ok$25$next - end - process $group_87 - assign \xer_ov$26$next \xer_ov$26 - assign \xer_ov_ok$27$next \xer_ov_ok$27 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign { \xer_ov_ok$27$next \xer_ov$26$next } { \xer_ov_ok$88 \xer_ov$87 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign { \xer_ov_ok$27$next \xer_ov$26$next } { \xer_ov_ok$88 \xer_ov$87 } - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \xer_ov_ok$27$next 1'0 - end - sync init - update \xer_ov$26 2'00 - update \xer_ov_ok$27 1'0 - sync posedge \coresync_clk - update \xer_ov$26 \xer_ov$26$next - update \xer_ov_ok$27 \xer_ov_ok$27$next - end - process $group_89 - assign \xer_so$28$next \xer_so$28 - assign \xer_so_ok$29$next \xer_so_ok$29 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign { \xer_so_ok$29$next \xer_so$28$next } { \xer_so_ok$90 \xer_so$89 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign { \xer_so_ok$29$next \xer_so$28$next } { \xer_so_ok$90 \xer_so$89 } - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \xer_so_ok$29$next 1'0 - end - sync init - update \xer_so$28 1'0 - update \xer_so_ok$29 1'0 - sync posedge \coresync_clk - update \xer_so$28 \xer_so$28$next - update \xer_so_ok$29 \xer_so_ok$29$next - end - process $group_91 - assign \n_valid_o 1'0 - assign \n_valid_o \r_busy - sync init - end - process $group_92 - assign \p_ready_o 1'0 - assign \p_ready_o \n_i_rdy_data - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.alu0.alu_alu0" -module \alu_alu0 - attribute \src "simple/issuer.py:141" - wire width 1 input 0 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 1 \o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 2 \cr_a_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 3 \xer_ca_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 4 \xer_ov_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 5 \xer_so_ok - attribute \src "simple/issuer.py:141" - wire width 1 input 6 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" - wire width 1 output 7 \n_valid_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" - wire width 1 input 8 \n_ready_i - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 input 9 \alu_op__insn_type - attribute \enum_base_type "Function" - attribute \enum_value_00000000000 "NONE" - attribute \enum_value_00000000010 "ALU" - attribute \enum_value_00000000100 "LDST" - attribute \enum_value_00000001000 "SHIFT_ROT" - attribute \enum_value_00000010000 "LOGICAL" - attribute \enum_value_00000100000 "BRANCH" - attribute \enum_value_00001000000 "CR" - attribute \enum_value_00010000000 "TRAP" - attribute \enum_value_00100000000 "MUL" - attribute \enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 input 10 \alu_op__fn_unit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 input 11 \alu_op__imm_data__data - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 12 \alu_op__imm_data__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 13 \alu_op__rc__rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 14 \alu_op__rc__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 15 \alu_op__oe__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 16 \alu_op__oe__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 17 \alu_op__invert_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 18 \alu_op__zero_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 19 \alu_op__invert_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 20 \alu_op__write_cr0 - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 input 21 \alu_op__input_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 22 \alu_op__output_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 23 \alu_op__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 24 \alu_op__is_signed - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 input 25 \alu_op__data_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 input 26 \alu_op__insn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 output 27 \o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 4 output 28 \cr_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 2 output 29 \xer_ca - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 2 output 30 \xer_ov - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 31 \xer_so - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 32 \ra - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 33 \rb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 1 input 34 \xer_so$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 2 input 35 \xer_ca$2 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" - wire width 1 input 36 \p_valid_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" - wire width 1 output 37 \p_ready_o - cell \p \p - connect \p_valid_i \p_valid_i - connect \p_ready_o \p_ready_o - end - cell \n \n - connect \n_valid_o \n_valid_o - connect \n_ready_i \n_ready_i - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" - wire width 1 \pipe1_n_valid_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" - wire width 1 \pipe1_n_ready_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \pipe1_muxid - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \pipe1_alu_op__insn_type - attribute \enum_base_type "Function" - attribute \enum_value_00000000000 "NONE" - attribute \enum_value_00000000010 "ALU" - attribute \enum_value_00000000100 "LDST" - attribute \enum_value_00000001000 "SHIFT_ROT" - attribute \enum_value_00000010000 "LOGICAL" - attribute \enum_value_00000100000 "BRANCH" - attribute \enum_value_00001000000 "CR" - attribute \enum_value_00010000000 "TRAP" - attribute \enum_value_00100000000 "MUL" - attribute \enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 \pipe1_alu_op__fn_unit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \pipe1_alu_op__imm_data__data - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe1_alu_op__imm_data__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe1_alu_op__rc__rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe1_alu_op__rc__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe1_alu_op__oe__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe1_alu_op__oe__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe1_alu_op__invert_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe1_alu_op__zero_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe1_alu_op__invert_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe1_alu_op__write_cr0 - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \pipe1_alu_op__input_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe1_alu_op__output_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe1_alu_op__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe1_alu_op__is_signed - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \pipe1_alu_op__data_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \pipe1_alu_op__insn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 \pipe1_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \pipe1_o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 4 \pipe1_cr_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \pipe1_cr_a_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 2 \pipe1_xer_ca - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \pipe1_xer_ca_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 2 \pipe1_xer_ov - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \pipe1_xer_ov_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \pipe1_xer_so - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \pipe1_xer_so_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" - wire width 1 \pipe1_p_valid_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" - wire width 1 \pipe1_p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \pipe1_muxid$3 - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \pipe1_alu_op__insn_type$4 - attribute \enum_base_type "Function" - attribute \enum_value_00000000000 "NONE" - attribute \enum_value_00000000010 "ALU" - attribute \enum_value_00000000100 "LDST" - attribute \enum_value_00000001000 "SHIFT_ROT" - attribute \enum_value_00000010000 "LOGICAL" - attribute \enum_value_00000100000 "BRANCH" - attribute \enum_value_00001000000 "CR" - attribute \enum_value_00010000000 "TRAP" - attribute \enum_value_00100000000 "MUL" - attribute \enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 \pipe1_alu_op__fn_unit$5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \pipe1_alu_op__imm_data__data$6 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe1_alu_op__imm_data__ok$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe1_alu_op__rc__rc$8 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe1_alu_op__rc__ok$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe1_alu_op__oe__oe$10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe1_alu_op__oe__ok$11 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe1_alu_op__invert_in$12 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe1_alu_op__zero_a$13 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe1_alu_op__invert_out$14 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe1_alu_op__write_cr0$15 - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \pipe1_alu_op__input_carry$16 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe1_alu_op__output_carry$17 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe1_alu_op__is_32bit$18 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe1_alu_op__is_signed$19 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \pipe1_alu_op__data_len$20 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \pipe1_alu_op__insn$21 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \pipe1_ra - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \pipe1_rb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 1 \pipe1_xer_so$22 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 2 \pipe1_xer_ca$23 - cell \pipe1 \pipe1 - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \n_valid_o \pipe1_n_valid_o - connect \n_ready_i \pipe1_n_ready_i - connect \muxid \pipe1_muxid - connect \alu_op__insn_type \pipe1_alu_op__insn_type - connect \alu_op__fn_unit \pipe1_alu_op__fn_unit - connect \alu_op__imm_data__data \pipe1_alu_op__imm_data__data - connect \alu_op__imm_data__ok \pipe1_alu_op__imm_data__ok - connect \alu_op__rc__rc \pipe1_alu_op__rc__rc - connect \alu_op__rc__ok \pipe1_alu_op__rc__ok - connect \alu_op__oe__oe \pipe1_alu_op__oe__oe - connect \alu_op__oe__ok \pipe1_alu_op__oe__ok - connect \alu_op__invert_in \pipe1_alu_op__invert_in - connect \alu_op__zero_a \pipe1_alu_op__zero_a - connect \alu_op__invert_out \pipe1_alu_op__invert_out - connect \alu_op__write_cr0 \pipe1_alu_op__write_cr0 - connect \alu_op__input_carry \pipe1_alu_op__input_carry - connect \alu_op__output_carry \pipe1_alu_op__output_carry - connect \alu_op__is_32bit \pipe1_alu_op__is_32bit - connect \alu_op__is_signed \pipe1_alu_op__is_signed - connect \alu_op__data_len \pipe1_alu_op__data_len - connect \alu_op__insn \pipe1_alu_op__insn - connect \o \pipe1_o - connect \o_ok \pipe1_o_ok - connect \cr_a \pipe1_cr_a - connect \cr_a_ok \pipe1_cr_a_ok - connect \xer_ca \pipe1_xer_ca - connect \xer_ca_ok \pipe1_xer_ca_ok - connect \xer_ov \pipe1_xer_ov - connect \xer_ov_ok \pipe1_xer_ov_ok - connect \xer_so \pipe1_xer_so - connect \xer_so_ok \pipe1_xer_so_ok - connect \p_valid_i \pipe1_p_valid_i - connect \p_ready_o \pipe1_p_ready_o - connect \muxid$1 \pipe1_muxid$3 - connect \alu_op__insn_type$2 \pipe1_alu_op__insn_type$4 - connect \alu_op__fn_unit$3 \pipe1_alu_op__fn_unit$5 - connect \alu_op__imm_data__data$4 \pipe1_alu_op__imm_data__data$6 - connect \alu_op__imm_data__ok$5 \pipe1_alu_op__imm_data__ok$7 - connect \alu_op__rc__rc$6 \pipe1_alu_op__rc__rc$8 - connect \alu_op__rc__ok$7 \pipe1_alu_op__rc__ok$9 - connect \alu_op__oe__oe$8 \pipe1_alu_op__oe__oe$10 - connect \alu_op__oe__ok$9 \pipe1_alu_op__oe__ok$11 - connect \alu_op__invert_in$10 \pipe1_alu_op__invert_in$12 - connect \alu_op__zero_a$11 \pipe1_alu_op__zero_a$13 - connect \alu_op__invert_out$12 \pipe1_alu_op__invert_out$14 - connect \alu_op__write_cr0$13 \pipe1_alu_op__write_cr0$15 - connect \alu_op__input_carry$14 \pipe1_alu_op__input_carry$16 - connect \alu_op__output_carry$15 \pipe1_alu_op__output_carry$17 - connect \alu_op__is_32bit$16 \pipe1_alu_op__is_32bit$18 - connect \alu_op__is_signed$17 \pipe1_alu_op__is_signed$19 - connect \alu_op__data_len$18 \pipe1_alu_op__data_len$20 - connect \alu_op__insn$19 \pipe1_alu_op__insn$21 - connect \ra \pipe1_ra - connect \rb \pipe1_rb - connect \xer_so$20 \pipe1_xer_so$22 - connect \xer_ca$21 \pipe1_xer_ca$23 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" - wire width 1 \pipe2_p_valid_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" - wire width 1 \pipe2_p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \pipe2_muxid - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \pipe2_alu_op__insn_type - attribute \enum_base_type "Function" - attribute \enum_value_00000000000 "NONE" - attribute \enum_value_00000000010 "ALU" - attribute \enum_value_00000000100 "LDST" - attribute \enum_value_00000001000 "SHIFT_ROT" - attribute \enum_value_00000010000 "LOGICAL" - attribute \enum_value_00000100000 "BRANCH" - attribute \enum_value_00001000000 "CR" - attribute \enum_value_00010000000 "TRAP" - attribute \enum_value_00100000000 "MUL" - attribute \enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 \pipe2_alu_op__fn_unit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \pipe2_alu_op__imm_data__data - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe2_alu_op__imm_data__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe2_alu_op__rc__rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe2_alu_op__rc__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe2_alu_op__oe__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe2_alu_op__oe__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe2_alu_op__invert_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe2_alu_op__zero_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe2_alu_op__invert_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe2_alu_op__write_cr0 - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \pipe2_alu_op__input_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe2_alu_op__output_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe2_alu_op__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe2_alu_op__is_signed - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \pipe2_alu_op__data_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \pipe2_alu_op__insn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 \pipe2_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \pipe2_o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 4 \pipe2_cr_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \pipe2_cr_a_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 2 \pipe2_xer_ca - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \pipe2_xer_ca_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 2 \pipe2_xer_ov - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \pipe2_xer_ov_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \pipe2_xer_so - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \pipe2_xer_so_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" - wire width 1 \pipe2_n_valid_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" - wire width 1 \pipe2_n_ready_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \pipe2_muxid$24 - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \pipe2_alu_op__insn_type$25 - attribute \enum_base_type "Function" - attribute \enum_value_00000000000 "NONE" - attribute \enum_value_00000000010 "ALU" - attribute \enum_value_00000000100 "LDST" - attribute \enum_value_00000001000 "SHIFT_ROT" - attribute \enum_value_00000010000 "LOGICAL" - attribute \enum_value_00000100000 "BRANCH" - attribute \enum_value_00001000000 "CR" - attribute \enum_value_00010000000 "TRAP" - attribute \enum_value_00100000000 "MUL" - attribute \enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 \pipe2_alu_op__fn_unit$26 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \pipe2_alu_op__imm_data__data$27 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe2_alu_op__imm_data__ok$28 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe2_alu_op__rc__rc$29 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe2_alu_op__rc__ok$30 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe2_alu_op__oe__oe$31 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe2_alu_op__oe__ok$32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe2_alu_op__invert_in$33 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe2_alu_op__zero_a$34 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe2_alu_op__invert_out$35 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe2_alu_op__write_cr0$36 - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \pipe2_alu_op__input_carry$37 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe2_alu_op__output_carry$38 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe2_alu_op__is_32bit$39 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe2_alu_op__is_signed$40 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \pipe2_alu_op__data_len$41 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \pipe2_alu_op__insn$42 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 \pipe2_o$43 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \pipe2_o_ok$44 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 4 \pipe2_cr_a$45 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \pipe2_cr_a_ok$46 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 2 \pipe2_xer_ca$47 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \pipe2_xer_ca_ok$48 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 2 \pipe2_xer_ov$49 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \pipe2_xer_ov_ok$50 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \pipe2_xer_so$51 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \pipe2_xer_so_ok$52 - cell \pipe2 \pipe2 - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \p_valid_i \pipe2_p_valid_i - connect \p_ready_o \pipe2_p_ready_o - connect \muxid \pipe2_muxid - connect \alu_op__insn_type \pipe2_alu_op__insn_type - connect \alu_op__fn_unit \pipe2_alu_op__fn_unit - connect \alu_op__imm_data__data \pipe2_alu_op__imm_data__data - connect \alu_op__imm_data__ok \pipe2_alu_op__imm_data__ok - connect \alu_op__rc__rc \pipe2_alu_op__rc__rc - connect \alu_op__rc__ok \pipe2_alu_op__rc__ok - connect \alu_op__oe__oe \pipe2_alu_op__oe__oe - connect \alu_op__oe__ok \pipe2_alu_op__oe__ok - connect \alu_op__invert_in \pipe2_alu_op__invert_in - connect \alu_op__zero_a \pipe2_alu_op__zero_a - connect \alu_op__invert_out \pipe2_alu_op__invert_out - connect \alu_op__write_cr0 \pipe2_alu_op__write_cr0 - connect \alu_op__input_carry \pipe2_alu_op__input_carry - connect \alu_op__output_carry \pipe2_alu_op__output_carry - connect \alu_op__is_32bit \pipe2_alu_op__is_32bit - connect \alu_op__is_signed \pipe2_alu_op__is_signed - connect \alu_op__data_len \pipe2_alu_op__data_len - connect \alu_op__insn \pipe2_alu_op__insn - connect \o \pipe2_o - connect \o_ok \pipe2_o_ok - connect \cr_a \pipe2_cr_a - connect \cr_a_ok \pipe2_cr_a_ok - connect \xer_ca \pipe2_xer_ca - connect \xer_ca_ok \pipe2_xer_ca_ok - connect \xer_ov \pipe2_xer_ov - connect \xer_ov_ok \pipe2_xer_ov_ok - connect \xer_so \pipe2_xer_so - connect \xer_so_ok \pipe2_xer_so_ok - connect \n_valid_o \pipe2_n_valid_o - connect \n_ready_i \pipe2_n_ready_i - connect \muxid$1 \pipe2_muxid$24 - connect \alu_op__insn_type$2 \pipe2_alu_op__insn_type$25 - connect \alu_op__fn_unit$3 \pipe2_alu_op__fn_unit$26 - connect \alu_op__imm_data__data$4 \pipe2_alu_op__imm_data__data$27 - connect \alu_op__imm_data__ok$5 \pipe2_alu_op__imm_data__ok$28 - connect \alu_op__rc__rc$6 \pipe2_alu_op__rc__rc$29 - connect \alu_op__rc__ok$7 \pipe2_alu_op__rc__ok$30 - connect \alu_op__oe__oe$8 \pipe2_alu_op__oe__oe$31 - connect \alu_op__oe__ok$9 \pipe2_alu_op__oe__ok$32 - connect \alu_op__invert_in$10 \pipe2_alu_op__invert_in$33 - connect \alu_op__zero_a$11 \pipe2_alu_op__zero_a$34 - connect \alu_op__invert_out$12 \pipe2_alu_op__invert_out$35 - connect \alu_op__write_cr0$13 \pipe2_alu_op__write_cr0$36 - connect \alu_op__input_carry$14 \pipe2_alu_op__input_carry$37 - connect \alu_op__output_carry$15 \pipe2_alu_op__output_carry$38 - connect \alu_op__is_32bit$16 \pipe2_alu_op__is_32bit$39 - connect \alu_op__is_signed$17 \pipe2_alu_op__is_signed$40 - connect \alu_op__data_len$18 \pipe2_alu_op__data_len$41 - connect \alu_op__insn$19 \pipe2_alu_op__insn$42 - connect \o$20 \pipe2_o$43 - connect \o_ok$21 \pipe2_o_ok$44 - connect \cr_a$22 \pipe2_cr_a$45 - connect \cr_a_ok$23 \pipe2_cr_a_ok$46 - connect \xer_ca$24 \pipe2_xer_ca$47 - connect \xer_ca_ok$25 \pipe2_xer_ca_ok$48 - connect \xer_ov$26 \pipe2_xer_ov$49 - connect \xer_ov_ok$27 \pipe2_xer_ov_ok$50 - connect \xer_so$28 \pipe2_xer_so$51 - connect \xer_so_ok$29 \pipe2_xer_so_ok$52 - end - process $group_0 - assign \pipe2_p_valid_i 1'0 - assign \pipe2_p_valid_i \pipe1_n_valid_o - sync init - end - process $group_1 - assign \pipe1_n_ready_i 1'0 - assign \pipe1_n_ready_i \pipe2_p_ready_o - sync init - end - process $group_2 - assign \pipe2_muxid 2'00 - assign \pipe2_muxid \pipe1_muxid - sync init - end - process $group_3 - assign \pipe2_alu_op__insn_type 7'0000000 - assign \pipe2_alu_op__fn_unit 11'00000000000 - assign \pipe2_alu_op__imm_data__data 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \pipe2_alu_op__imm_data__ok 1'0 - assign \pipe2_alu_op__rc__rc 1'0 - assign \pipe2_alu_op__rc__ok 1'0 - assign \pipe2_alu_op__oe__oe 1'0 - assign \pipe2_alu_op__oe__ok 1'0 - assign \pipe2_alu_op__invert_in 1'0 - assign \pipe2_alu_op__zero_a 1'0 - assign \pipe2_alu_op__invert_out 1'0 - assign \pipe2_alu_op__write_cr0 1'0 - assign \pipe2_alu_op__input_carry 2'00 - assign \pipe2_alu_op__output_carry 1'0 - assign \pipe2_alu_op__is_32bit 1'0 - assign \pipe2_alu_op__is_signed 1'0 - assign \pipe2_alu_op__data_len 4'0000 - assign \pipe2_alu_op__insn 32'00000000000000000000000000000000 - assign { \pipe2_alu_op__insn \pipe2_alu_op__data_len \pipe2_alu_op__is_signed \pipe2_alu_op__is_32bit \pipe2_alu_op__output_carry \pipe2_alu_op__input_carry \pipe2_alu_op__write_cr0 \pipe2_alu_op__invert_out \pipe2_alu_op__zero_a \pipe2_alu_op__invert_in { \pipe2_alu_op__oe__ok \pipe2_alu_op__oe__oe } { \pipe2_alu_op__rc__ok \pipe2_alu_op__rc__rc } { \pipe2_alu_op__imm_data__ok \pipe2_alu_op__imm_data__data } \pipe2_alu_op__fn_unit \pipe2_alu_op__insn_type } { \pipe1_alu_op__insn \pipe1_alu_op__data_len \pipe1_alu_op__is_signed \pipe1_alu_op__is_32bit \pipe1_alu_op__output_carry \pipe1_alu_op__input_carry \pipe1_alu_op__write_cr0 \pipe1_alu_op__invert_out \pipe1_alu_op__zero_a \pipe1_alu_op__invert_in { \pipe1_alu_op__oe__ok \pipe1_alu_op__oe__oe } { \pipe1_alu_op__rc__ok \pipe1_alu_op__rc__rc } { \pipe1_alu_op__imm_data__ok \pipe1_alu_op__imm_data__data } \pipe1_alu_op__fn_unit \pipe1_alu_op__insn_type } - sync init - end - process $group_21 - assign \pipe2_o 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \pipe2_o_ok 1'0 - assign { \pipe2_o_ok \pipe2_o } { \pipe1_o_ok \pipe1_o } - sync init - end - process $group_23 - assign \pipe2_cr_a 4'0000 - assign \pipe2_cr_a_ok 1'0 - assign { \pipe2_cr_a_ok \pipe2_cr_a } { \pipe1_cr_a_ok \pipe1_cr_a } - sync init - end - process $group_25 - assign \pipe2_xer_ca 2'00 - assign \pipe2_xer_ca_ok 1'0 - assign { \pipe2_xer_ca_ok \pipe2_xer_ca } { \pipe1_xer_ca_ok \pipe1_xer_ca } - sync init - end - process $group_27 - assign \pipe2_xer_ov 2'00 - assign \pipe2_xer_ov_ok 1'0 - assign { \pipe2_xer_ov_ok \pipe2_xer_ov } { \pipe1_xer_ov_ok \pipe1_xer_ov } - sync init - end - process $group_29 - assign \pipe2_xer_so 1'0 - assign \pipe2_xer_so_ok 1'0 - assign { \pipe2_xer_so_ok \pipe2_xer_so } { \pipe1_xer_so_ok \pipe1_xer_so } - sync init - end - process $group_31 - assign \pipe1_p_valid_i 1'0 - assign \pipe1_p_valid_i \p_valid_i - sync init - end - process $group_32 - assign \p_ready_o 1'0 - assign \p_ready_o \pipe1_p_ready_o - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \muxid - process $group_33 - assign \pipe1_muxid$3 2'00 - assign \pipe1_muxid$3 \muxid - sync init - end - process $group_34 - assign \pipe1_alu_op__insn_type$4 7'0000000 - assign \pipe1_alu_op__fn_unit$5 11'00000000000 - assign \pipe1_alu_op__imm_data__data$6 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \pipe1_alu_op__imm_data__ok$7 1'0 - assign \pipe1_alu_op__rc__rc$8 1'0 - assign \pipe1_alu_op__rc__ok$9 1'0 - assign \pipe1_alu_op__oe__oe$10 1'0 - assign \pipe1_alu_op__oe__ok$11 1'0 - assign \pipe1_alu_op__invert_in$12 1'0 - assign \pipe1_alu_op__zero_a$13 1'0 - assign \pipe1_alu_op__invert_out$14 1'0 - assign \pipe1_alu_op__write_cr0$15 1'0 - assign \pipe1_alu_op__input_carry$16 2'00 - assign \pipe1_alu_op__output_carry$17 1'0 - assign \pipe1_alu_op__is_32bit$18 1'0 - assign \pipe1_alu_op__is_signed$19 1'0 - assign \pipe1_alu_op__data_len$20 4'0000 - assign \pipe1_alu_op__insn$21 32'00000000000000000000000000000000 - assign { \pipe1_alu_op__insn$21 \pipe1_alu_op__data_len$20 \pipe1_alu_op__is_signed$19 \pipe1_alu_op__is_32bit$18 \pipe1_alu_op__output_carry$17 \pipe1_alu_op__input_carry$16 \pipe1_alu_op__write_cr0$15 \pipe1_alu_op__invert_out$14 \pipe1_alu_op__zero_a$13 \pipe1_alu_op__invert_in$12 { \pipe1_alu_op__oe__ok$11 \pipe1_alu_op__oe__oe$10 } { \pipe1_alu_op__rc__ok$9 \pipe1_alu_op__rc__rc$8 } { \pipe1_alu_op__imm_data__ok$7 \pipe1_alu_op__imm_data__data$6 } \pipe1_alu_op__fn_unit$5 \pipe1_alu_op__insn_type$4 } { \alu_op__insn \alu_op__data_len \alu_op__is_signed \alu_op__is_32bit \alu_op__output_carry \alu_op__input_carry \alu_op__write_cr0 \alu_op__invert_out \alu_op__zero_a \alu_op__invert_in { \alu_op__oe__ok \alu_op__oe__oe } { \alu_op__rc__ok \alu_op__rc__rc } { \alu_op__imm_data__ok \alu_op__imm_data__data } \alu_op__fn_unit \alu_op__insn_type } - sync init - end - process $group_52 - assign \pipe1_ra 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \pipe1_ra \ra - sync init - end - process $group_53 - assign \pipe1_rb 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \pipe1_rb \rb - sync init - end - process $group_54 - assign \pipe1_xer_so$22 1'0 - assign \pipe1_xer_so$22 \xer_so$1 - sync init - end - process $group_55 - assign \pipe1_xer_ca$23 2'00 - assign \pipe1_xer_ca$23 \xer_ca$2 - sync init - end - process $group_56 - assign \n_valid_o 1'0 - assign \n_valid_o \pipe2_n_valid_o - sync init - end - process $group_57 - assign \pipe2_n_ready_i 1'0 - assign \pipe2_n_ready_i \n_ready_i - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \muxid$53 - process $group_58 - assign \muxid$53 2'00 - assign \muxid$53 \pipe2_muxid$24 - sync init - end - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \alu_op__insn_type$54 - attribute \enum_base_type "Function" - attribute \enum_value_00000000000 "NONE" - attribute \enum_value_00000000010 "ALU" - attribute \enum_value_00000000100 "LDST" - attribute \enum_value_00000001000 "SHIFT_ROT" - attribute \enum_value_00000010000 "LOGICAL" - attribute \enum_value_00000100000 "BRANCH" - attribute \enum_value_00001000000 "CR" - attribute \enum_value_00010000000 "TRAP" - attribute \enum_value_00100000000 "MUL" - attribute \enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 \alu_op__fn_unit$55 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \alu_op__imm_data__data$56 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \alu_op__imm_data__ok$57 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \alu_op__rc__rc$58 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \alu_op__rc__ok$59 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \alu_op__oe__oe$60 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \alu_op__oe__ok$61 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \alu_op__invert_in$62 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \alu_op__zero_a$63 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \alu_op__invert_out$64 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \alu_op__write_cr0$65 - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \alu_op__input_carry$66 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \alu_op__output_carry$67 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \alu_op__is_32bit$68 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \alu_op__is_signed$69 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \alu_op__data_len$70 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \alu_op__insn$71 - process $group_59 - assign \alu_op__insn_type$54 7'0000000 - assign \alu_op__fn_unit$55 11'00000000000 - assign \alu_op__imm_data__data$56 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \alu_op__imm_data__ok$57 1'0 - assign \alu_op__rc__rc$58 1'0 - assign \alu_op__rc__ok$59 1'0 - assign \alu_op__oe__oe$60 1'0 - assign \alu_op__oe__ok$61 1'0 - assign \alu_op__invert_in$62 1'0 - assign \alu_op__zero_a$63 1'0 - assign \alu_op__invert_out$64 1'0 - assign \alu_op__write_cr0$65 1'0 - assign \alu_op__input_carry$66 2'00 - assign \alu_op__output_carry$67 1'0 - assign \alu_op__is_32bit$68 1'0 - assign \alu_op__is_signed$69 1'0 - assign \alu_op__data_len$70 4'0000 - assign \alu_op__insn$71 32'00000000000000000000000000000000 - assign { \alu_op__insn$71 \alu_op__data_len$70 \alu_op__is_signed$69 \alu_op__is_32bit$68 \alu_op__output_carry$67 \alu_op__input_carry$66 \alu_op__write_cr0$65 \alu_op__invert_out$64 \alu_op__zero_a$63 \alu_op__invert_in$62 { \alu_op__oe__ok$61 \alu_op__oe__oe$60 } { \alu_op__rc__ok$59 \alu_op__rc__rc$58 } { \alu_op__imm_data__ok$57 \alu_op__imm_data__data$56 } \alu_op__fn_unit$55 \alu_op__insn_type$54 } { \pipe2_alu_op__insn$42 \pipe2_alu_op__data_len$41 \pipe2_alu_op__is_signed$40 \pipe2_alu_op__is_32bit$39 \pipe2_alu_op__output_carry$38 \pipe2_alu_op__input_carry$37 \pipe2_alu_op__write_cr0$36 \pipe2_alu_op__invert_out$35 \pipe2_alu_op__zero_a$34 \pipe2_alu_op__invert_in$33 { \pipe2_alu_op__oe__ok$32 \pipe2_alu_op__oe__oe$31 } { \pipe2_alu_op__rc__ok$30 \pipe2_alu_op__rc__rc$29 } { \pipe2_alu_op__imm_data__ok$28 \pipe2_alu_op__imm_data__data$27 } \pipe2_alu_op__fn_unit$26 \pipe2_alu_op__insn_type$25 } - sync init - end - process $group_77 - assign \o 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \o_ok 1'0 - assign { \o_ok \o } { \pipe2_o_ok$44 \pipe2_o$43 } - sync init - end - process $group_79 - assign \cr_a 4'0000 - assign \cr_a_ok 1'0 - assign { \cr_a_ok \cr_a } { \pipe2_cr_a_ok$46 \pipe2_cr_a$45 } - sync init - end - process $group_81 - assign \xer_ca 2'00 - assign \xer_ca_ok 1'0 - assign { \xer_ca_ok \xer_ca } { \pipe2_xer_ca_ok$48 \pipe2_xer_ca$47 } - sync init - end - process $group_83 - assign \xer_ov 2'00 - assign \xer_ov_ok 1'0 - assign { \xer_ov_ok \xer_ov } { \pipe2_xer_ov_ok$50 \pipe2_xer_ov$49 } - sync init - end - process $group_85 - assign \xer_so 1'0 - assign \xer_so_ok 1'0 - assign { \xer_so_ok \xer_so } { \pipe2_xer_so_ok$52 \pipe2_xer_so$51 } - sync init - end - connect \muxid 2'00 -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.alu0.src_l" -module \src_l - attribute \src "simple/issuer.py:141" - wire width 1 input 0 \coresync_clk - attribute \src "simple/issuer.py:141" - wire width 1 input 1 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 4 input 2 \s_src - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 4 input 3 \r_src - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire width 4 output 4 \q_src - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire width 4 \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire width 4 \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 4 $1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A \r_src - connect \Y $1 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 4 $3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $4 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A \q_int - connect \B $1 - connect \Y $3 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 4 $5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $6 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A $3 - connect \B \s_src - connect \Y $5 - end - process $group_0 - assign \q_int$next \q_int - assign \q_int$next $5 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \q_int$next 4'0000 - end - sync init - update \q_int 4'0000 - sync posedge \coresync_clk - update \q_int \q_int$next - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 4 $7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $8 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A \r_src - connect \Y $7 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 4 $9 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $10 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A \q_int - connect \B $7 - connect \Y $9 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 4 $11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $12 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A $9 - connect \B \s_src - connect \Y $11 - end - process $group_1 - assign \q_src 4'0000 - assign \q_src $11 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" - wire width 4 \qn_src - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - wire width 4 $13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $14 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A \q_src - connect \Y $13 - end - process $group_2 - assign \qn_src 4'0000 - assign \qn_src $13 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" - wire width 4 \qlq_src - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - wire width 4 $15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $16 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A \q_src - connect \B \q_int - connect \Y $15 - end - process $group_3 - assign \qlq_src 4'0000 - assign \qlq_src $15 - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.alu0.opc_l" -module \opc_l - attribute \src "simple/issuer.py:141" - wire width 1 input 0 \coresync_clk - attribute \src "simple/issuer.py:141" - wire width 1 input 1 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 1 input 2 \s_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 1 input 3 \r_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire width 1 output 4 \q_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire width 1 \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire width 1 \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_opc - connect \Y $1 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 1 $3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $4 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B $1 - connect \Y $3 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 1 $5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $6 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $3 - connect \B \s_opc - connect \Y $5 - end - process $group_0 - assign \q_int$next \q_int - assign \q_int$next $5 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \q_int$next 1'0 - end - sync init - update \q_int 1'0 - sync posedge \coresync_clk - update \q_int \q_int$next - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 1 $7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $8 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_opc - connect \Y $7 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 1 $9 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $10 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B $7 - connect \Y $9 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 1 $11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $12 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $9 - connect \B \s_opc - connect \Y $11 - end - process $group_1 - assign \q_opc 1'0 - assign \q_opc $11 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" - wire width 1 \qn_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - wire width 1 $13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $14 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_opc - connect \Y $13 - end - process $group_2 - assign \qn_opc 1'0 - assign \qn_opc $13 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" - wire width 1 \qlq_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - wire width 1 $15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $16 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_opc - connect \B \q_int - connect \Y $15 - end - process $group_3 - assign \qlq_opc 1'0 - assign \qlq_opc $15 - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.alu0.req_l" -module \req_l - attribute \src "simple/issuer.py:141" - wire width 1 input 0 \coresync_clk - attribute \src "simple/issuer.py:141" - wire width 1 input 1 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire width 5 output 2 \q_req - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 5 input 3 \s_req - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 5 input 4 \r_req - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire width 5 \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire width 5 \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 5 $1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \Y_WIDTH 5 - connect \A \r_req - connect \Y $1 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 5 $3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $4 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 5 - connect \A \q_int - connect \B $1 - connect \Y $3 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 5 $5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $6 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 5 - connect \A $3 - connect \B \s_req - connect \Y $5 - end - process $group_0 - assign \q_int$next \q_int - assign \q_int$next $5 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \q_int$next 5'00000 - end - sync init - update \q_int 5'00000 - sync posedge \coresync_clk - update \q_int \q_int$next - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 5 $7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $8 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \Y_WIDTH 5 - connect \A \r_req - connect \Y $7 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 5 $9 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $10 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 5 - connect \A \q_int - connect \B $7 - connect \Y $9 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 5 $11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $12 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 5 - connect \A $9 - connect \B \s_req - connect \Y $11 - end - process $group_1 - assign \q_req 5'00000 - assign \q_req $11 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" - wire width 5 \qn_req - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - wire width 5 $13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $14 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \Y_WIDTH 5 - connect \A \q_req - connect \Y $13 - end - process $group_2 - assign \qn_req 5'00000 - assign \qn_req $13 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" - wire width 5 \qlq_req - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - wire width 5 $15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $16 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 5 - connect \A \q_req - connect \B \q_int - connect \Y $15 - end - process $group_3 - assign \qlq_req 5'00000 - assign \qlq_req $15 - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.alu0.rst_l" -module \rst_l - attribute \src "simple/issuer.py:141" - wire width 1 input 0 \coresync_clk - attribute \src "simple/issuer.py:141" - wire width 1 input 1 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 1 input 2 \s_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 1 input 3 \r_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire width 1 \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire width 1 \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_rst - connect \Y $1 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 1 $3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $4 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B $1 - connect \Y $3 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 1 $5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $6 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $3 - connect \B \s_rst - connect \Y $5 - end - process $group_0 - assign \q_int$next \q_int - assign \q_int$next $5 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \q_int$next 1'0 - end - sync init - update \q_int 1'0 - sync posedge \coresync_clk - update \q_int \q_int$next - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire width 1 \q_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 1 $7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $8 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_rst - connect \Y $7 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 1 $9 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $10 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B $7 - connect \Y $9 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 1 $11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $12 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $9 - connect \B \s_rst - connect \Y $11 - end - process $group_1 - assign \q_rst 1'0 - assign \q_rst $11 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" - wire width 1 \qn_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - wire width 1 $13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $14 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_rst - connect \Y $13 - end - process $group_2 - assign \qn_rst 1'0 - assign \qn_rst $13 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" - wire width 1 \qlq_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - wire width 1 $15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $16 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_rst - connect \B \q_int - connect \Y $15 - end - process $group_3 - assign \qlq_rst 1'0 - assign \qlq_rst $15 - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.alu0.rok_l" -module \rok_l - attribute \src "simple/issuer.py:141" - wire width 1 input 0 \coresync_clk - attribute \src "simple/issuer.py:141" - wire width 1 input 1 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire width 1 output 2 \q_rdok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 1 input 3 \s_rdok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 1 input 4 \r_rdok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire width 1 \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire width 1 \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_rdok - connect \Y $1 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 1 $3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $4 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B $1 - connect \Y $3 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 1 $5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $6 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $3 - connect \B \s_rdok - connect \Y $5 - end - process $group_0 - assign \q_int$next \q_int - assign \q_int$next $5 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \q_int$next 1'0 - end - sync init - update \q_int 1'0 - sync posedge \coresync_clk - update \q_int \q_int$next - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 1 $7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $8 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_rdok - connect \Y $7 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 1 $9 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $10 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B $7 - connect \Y $9 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 1 $11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $12 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $9 - connect \B \s_rdok - connect \Y $11 - end - process $group_1 - assign \q_rdok 1'0 - assign \q_rdok $11 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" - wire width 1 \qn_rdok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - wire width 1 $13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $14 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_rdok - connect \Y $13 - end - process $group_2 - assign \qn_rdok 1'0 - assign \qn_rdok $13 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" - wire width 1 \qlq_rdok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - wire width 1 $15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $16 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_rdok - connect \B \q_int - connect \Y $15 - end - process $group_3 - assign \qlq_rdok 1'0 - assign \qlq_rdok $15 - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.alu0.alui_l" -module \alui_l - attribute \src "simple/issuer.py:141" - wire width 1 input 0 \coresync_clk - attribute \src "simple/issuer.py:141" - wire width 1 input 1 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire width 1 output 2 \q_alui - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 1 input 3 \r_alui - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire 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\alu_alu0_n_valid_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" - wire width 1 \alu_alu0_n_ready_i - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \alu_alu0_alu_op__insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \alu_alu0_alu_op__insn_type$next - attribute \enum_base_type "Function" - attribute \enum_value_00000000000 "NONE" - attribute \enum_value_00000000010 "ALU" - attribute \enum_value_00000000100 "LDST" - attribute \enum_value_00000001000 "SHIFT_ROT" - attribute \enum_value_00000010000 "LOGICAL" - attribute \enum_value_00000100000 "BRANCH" - attribute \enum_value_00001000000 "CR" - attribute \enum_value_00010000000 "TRAP" - attribute \enum_value_00100000000 "MUL" - attribute \enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 \alu_alu0_alu_op__fn_unit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 \alu_alu0_alu_op__fn_unit$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \alu_alu0_alu_op__imm_data__data - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \alu_alu0_alu_op__imm_data__data$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \alu_alu0_alu_op__imm_data__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \alu_alu0_alu_op__imm_data__ok$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \alu_alu0_alu_op__rc__rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \alu_alu0_alu_op__rc__rc$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \alu_alu0_alu_op__rc__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \alu_alu0_alu_op__rc__ok$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \alu_alu0_alu_op__oe__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \alu_alu0_alu_op__oe__oe$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \alu_alu0_alu_op__oe__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \alu_alu0_alu_op__oe__ok$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \alu_alu0_alu_op__invert_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \alu_alu0_alu_op__invert_in$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \alu_alu0_alu_op__zero_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \alu_alu0_alu_op__zero_a$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \alu_alu0_alu_op__invert_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \alu_alu0_alu_op__invert_out$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \alu_alu0_alu_op__write_cr0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \alu_alu0_alu_op__write_cr0$next - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \alu_alu0_alu_op__input_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \alu_alu0_alu_op__input_carry$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \alu_alu0_alu_op__output_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \alu_alu0_alu_op__output_carry$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \alu_alu0_alu_op__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \alu_alu0_alu_op__is_32bit$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \alu_alu0_alu_op__is_signed - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \alu_alu0_alu_op__is_signed$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \alu_alu0_alu_op__data_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \alu_alu0_alu_op__data_len$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \alu_alu0_alu_op__insn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \alu_alu0_alu_op__insn$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 \alu_alu0_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 4 \alu_alu0_cr_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 2 \alu_alu0_xer_ca - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 2 \alu_alu0_xer_ov - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \alu_alu0_xer_so - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \alu_alu0_ra - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \alu_alu0_rb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 1 \alu_alu0_xer_so$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 2 \alu_alu0_xer_ca$2 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" - wire width 1 \alu_alu0_p_valid_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" - wire width 1 \alu_alu0_p_ready_o - cell \alu_alu0 \alu_alu0 - connect \coresync_clk \coresync_clk - connect \o_ok \o_ok - connect \cr_a_ok \cr_a_ok - connect \xer_ca_ok \xer_ca_ok - connect \xer_ov_ok \xer_ov_ok - connect \xer_so_ok \xer_so_ok - connect \coresync_rst \coresync_rst - connect \n_valid_o \alu_alu0_n_valid_o - connect \n_ready_i \alu_alu0_n_ready_i - connect \alu_op__insn_type \alu_alu0_alu_op__insn_type - connect \alu_op__fn_unit \alu_alu0_alu_op__fn_unit - connect \alu_op__imm_data__data \alu_alu0_alu_op__imm_data__data - connect \alu_op__imm_data__ok \alu_alu0_alu_op__imm_data__ok - connect \alu_op__rc__rc \alu_alu0_alu_op__rc__rc - connect \alu_op__rc__ok \alu_alu0_alu_op__rc__ok - connect \alu_op__oe__oe \alu_alu0_alu_op__oe__oe - connect \alu_op__oe__ok \alu_alu0_alu_op__oe__ok - connect \alu_op__invert_in \alu_alu0_alu_op__invert_in - connect \alu_op__zero_a \alu_alu0_alu_op__zero_a - connect \alu_op__invert_out \alu_alu0_alu_op__invert_out - connect \alu_op__write_cr0 \alu_alu0_alu_op__write_cr0 - connect \alu_op__input_carry \alu_alu0_alu_op__input_carry - connect \alu_op__output_carry \alu_alu0_alu_op__output_carry - connect \alu_op__is_32bit \alu_alu0_alu_op__is_32bit - connect \alu_op__is_signed \alu_alu0_alu_op__is_signed - connect \alu_op__data_len \alu_alu0_alu_op__data_len - connect \alu_op__insn \alu_alu0_alu_op__insn - connect \o \alu_alu0_o - connect \cr_a \alu_alu0_cr_a - connect \xer_ca \alu_alu0_xer_ca - connect \xer_ov \alu_alu0_xer_ov - connect \xer_so \alu_alu0_xer_so - connect \ra \alu_alu0_ra - connect \rb \alu_alu0_rb - connect \xer_so$1 \alu_alu0_xer_so$1 - connect \xer_ca$2 \alu_alu0_xer_ca$2 - connect \p_valid_i \alu_alu0_p_valid_i - connect \p_ready_o \alu_alu0_p_ready_o - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 4 \src_l_s_src - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 4 \src_l_s_src$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 4 \src_l_r_src - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 4 \src_l_r_src$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire width 4 \src_l_q_src - cell \src_l \src_l - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \s_src \src_l_s_src - connect \r_src \src_l_r_src - connect \q_src \src_l_q_src - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 1 \opc_l_s_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 1 \opc_l_s_opc$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 1 \opc_l_r_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 1 \opc_l_r_opc$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire width 1 \opc_l_q_opc - cell \opc_l \opc_l - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \s_opc \opc_l_s_opc - connect \r_opc \opc_l_r_opc - connect \q_opc \opc_l_q_opc - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire width 5 \req_l_q_req - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 5 \req_l_s_req - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 5 \req_l_s_req$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 5 \req_l_r_req - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 5 \req_l_r_req$next - cell \req_l \req_l - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \q_req \req_l_q_req - connect \s_req \req_l_s_req - connect \r_req \req_l_r_req - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 1 \rst_l_s_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 1 \rst_l_s_rst$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 1 \rst_l_r_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 1 \rst_l_r_rst$next - cell \rst_l \rst_l - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \s_rst \rst_l_s_rst - connect \r_rst \rst_l_r_rst - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire width 1 \rok_l_q_rdok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 1 \rok_l_s_rdok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 1 \rok_l_s_rdok$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 1 \rok_l_r_rdok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 1 \rok_l_r_rdok$next - cell \rok_l \rok_l - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \q_rdok \rok_l_q_rdok - connect \s_rdok \rok_l_s_rdok - connect \r_rdok \rok_l_r_rdok - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire width 1 \alui_l_q_alui - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 1 \alui_l_r_alui - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 1 \alui_l_r_alui$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 1 \alui_l_s_alui - cell \alui_l \alui_l - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \q_alui \alui_l_q_alui - connect \r_alui \alui_l_r_alui - connect \s_alui \alui_l_s_alui - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire width 1 \alu_l_q_alu - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 1 \alu_l_r_alu - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 1 \alu_l_r_alu$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 1 \alu_l_s_alu - cell \alu_l \alu_l - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \q_alu \alu_l_q_alu - connect \r_alu \alu_l_r_alu - connect \s_alu \alu_l_s_alu - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:187" - wire width 1 \all_rd - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:188" - wire width 1 $3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:188" - cell $and $4 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cu_busy_o - connect \B \rok_l_q_rdok - connect \Y $3 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - wire width 1 $5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - wire width 4 $6 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - cell $not $7 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A \cu_rd__rel_o - connect \Y $6 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - wire width 4 $8 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - cell $or $9 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A $6 - connect \B \cu_rd__go_i - connect \Y $8 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - cell $reduce_and $10 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A $8 - connect \Y $5 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - wire width 1 $11 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - cell $and $12 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $3 - connect \B $5 - connect \Y $11 - end - process $group_0 - assign \all_rd 1'0 - assign \all_rd $11 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire width 1 \all_rd_dly - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire width 1 \all_rd_dly$next - process $group_1 - assign \all_rd_dly$next \all_rd_dly - assign \all_rd_dly$next \all_rd - sync init - update \all_rd_dly 1'0 - sync posedge \coresync_clk - update \all_rd_dly \all_rd_dly$next - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" - wire width 1 \all_rd_rise - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - wire width 1 $13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $not $14 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \all_rd_dly - connect \Y $13 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - wire width 1 $15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $and $16 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \all_rd - connect \B $13 - connect \Y $15 - end - process $group_2 - assign \all_rd_rise 1'0 - assign \all_rd_rise $15 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:192" - wire width 1 \all_rd_pulse - process $group_3 - assign \all_rd_pulse 1'0 - assign \all_rd_pulse \all_rd_rise - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:196" - wire width 1 \alu_done - process $group_4 - assign \alu_done 1'0 - assign \alu_done \alu_alu0_n_valid_o - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire width 1 \alu_done_dly - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire width 1 \alu_done_dly$next - process $group_5 - assign \alu_done_dly$next \alu_done_dly - assign \alu_done_dly$next \alu_done - sync init - update \alu_done_dly 1'0 - sync posedge \coresync_clk - update \alu_done_dly \alu_done_dly$next - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" - wire width 1 \alu_done_rise - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - wire width 1 $17 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $not $18 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \alu_done_dly - connect \Y $17 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - wire width 1 $19 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $and $20 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \alu_done - connect \B $17 - connect \Y $19 - end - process $group_6 - assign \alu_done_rise 1'0 - assign \alu_done_rise $19 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:197" - wire width 1 \alu_pulse - process $group_7 - assign \alu_pulse 1'0 - assign \alu_pulse \alu_done_rise - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:198" - wire width 5 \alu_pulsem - process $group_8 - assign \alu_pulsem 5'00000 - assign \alu_pulsem { \alu_pulse \alu_pulse \alu_pulse \alu_pulse \alu_pulse } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:204" - wire width 5 \prev_wr_go - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:204" - wire width 5 \prev_wr_go$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:206" - wire width 5 $21 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:206" - cell $and $22 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 5 - connect \A \cu_wr__go_i - connect \B { \cu_busy_o \cu_busy_o \cu_busy_o \cu_busy_o \cu_busy_o } - connect \Y $21 - end - process $group_9 - assign \prev_wr_go$next \prev_wr_go - assign \prev_wr_go$next $21 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \prev_wr_go$next 5'00000 - end - sync init - update \prev_wr_go 5'00000 - sync posedge \coresync_clk - update \prev_wr_go \prev_wr_go$next - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:108" - wire width 1 \cu_done_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - wire width 1 $23 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - wire width 1 $24 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - wire width 5 $25 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:97" - wire width 5 \cu_wrmask_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $not $26 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \Y_WIDTH 5 - connect \A \cu_wrmask_o - connect \Y $25 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - wire width 5 $27 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $and $28 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 5 - connect \A \cu_wr__rel_o - connect \B $25 - connect \Y $27 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $reduce_bool $29 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A $27 - connect \Y $24 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $not $30 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $24 - connect \Y $23 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - wire width 1 $31 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $and $32 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cu_busy_o - connect \B $23 - connect \Y $31 - end - process $group_10 - assign \cu_done_o 1'0 - assign \cu_done_o $31 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:211" - wire width 1 \wr_any - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" - wire width 1 $33 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" - cell $reduce_bool $34 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \cu_wr__go_i - connect \Y $33 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" - wire width 1 $35 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" - cell $reduce_bool $36 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \prev_wr_go - connect \Y $35 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" - wire width 1 $37 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" - cell $or $38 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $33 - connect \B $35 - connect \Y $37 - end - process $group_11 - assign \wr_any 1'0 - assign \wr_any $37 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:212" - wire width 1 \req_done - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" - wire width 1 $39 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" - cell $not $40 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \alu_alu0_n_ready_i - connect \Y $39 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" - wire width 1 $41 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" - cell $and $42 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_any - connect \B $39 - connect \Y $41 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" - wire width 5 $43 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" - cell $and $44 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 5 - connect \A \req_l_q_req - connect \B \cu_wrmask_o - connect \Y $43 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" - wire width 1 $45 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" - cell $eq $46 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $43 - connect \B 1'0 - connect \Y $45 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" - wire width 1 $47 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" - cell $and $48 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $41 - connect \B $45 - connect \Y $47 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - wire width 1 $49 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - cell $eq $50 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cu_wrmask_o - connect \B 1'0 - connect \Y $49 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - wire width 1 $51 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - cell $and $52 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $49 - connect \B \alu_alu0_n_ready_i - connect \Y $51 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - wire width 1 $53 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - cell $and $54 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $51 - connect \B \alu_alu0_n_valid_o - connect \Y $53 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - wire width 1 $55 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - cell $and $56 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $53 - connect \B \cu_busy_o - connect \Y $55 - end - process $group_12 - assign \req_done 1'0 - assign \req_done $47 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - switch { $55 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - case 1'1 - assign \req_done 1'1 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:226" - wire width 1 \reset - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:104" - wire width 1 \cu_go_die_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:230" - wire width 1 $57 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:230" - cell $or $58 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \req_done - connect \B \cu_go_die_i - connect \Y $57 - end - process $group_13 - assign \reset 1'0 - assign \reset $57 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:227" - wire width 1 \rst_r - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:231" - wire width 1 $59 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:231" - cell $or $60 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cu_issue_i - connect \B \cu_go_die_i - connect \Y $59 - end - process $group_14 - assign \rst_r 1'0 - assign \rst_r $59 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:228" - wire width 5 \reset_w - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:232" - wire width 5 $61 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:232" - cell $or $62 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 5 - connect \A \cu_wr__go_i - connect \B { \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i } - connect \Y $61 - end - process $group_15 - assign \reset_w 5'00000 - assign \reset_w $61 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:229" - wire width 4 \reset_r - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:233" - wire width 4 $63 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:233" - cell $or $64 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A \cu_rd__go_i - connect \B { \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i } - connect \Y $63 - end - process $group_16 - assign \reset_r 4'0000 - assign \reset_r $63 - sync init - end - process $group_17 - assign \rok_l_s_rdok$next \rok_l_s_rdok - assign \rok_l_s_rdok$next \cu_issue_i - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \rok_l_s_rdok$next 1'0 - end - sync init - update \rok_l_s_rdok 1'0 - sync posedge \coresync_clk - update \rok_l_s_rdok \rok_l_s_rdok$next - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:237" - wire width 1 $65 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:237" - cell $and $66 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \alu_alu0_n_valid_o - connect \B \cu_busy_o - connect \Y $65 - end - process $group_18 - assign \rok_l_r_rdok$next \rok_l_r_rdok - assign \rok_l_r_rdok$next $65 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \rok_l_r_rdok$next 1'1 - end - sync init - update \rok_l_r_rdok 1'1 - sync posedge \coresync_clk - update \rok_l_r_rdok \rok_l_r_rdok$next - end - process $group_19 - assign \rst_l_s_rst$next \rst_l_s_rst - assign \rst_l_s_rst$next \all_rd - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \rst_l_s_rst$next 1'0 - end - sync init - update \rst_l_s_rst 1'0 - sync posedge \coresync_clk - update \rst_l_s_rst \rst_l_s_rst$next - end - process $group_20 - assign \rst_l_r_rst$next \rst_l_r_rst - assign \rst_l_r_rst$next \rst_r - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \rst_l_r_rst$next 1'1 - end - sync init - update \rst_l_r_rst 1'1 - sync posedge \coresync_clk - update \rst_l_r_rst \rst_l_r_rst$next - end - process $group_21 - assign \opc_l_s_opc$next \opc_l_s_opc - assign \opc_l_s_opc$next \cu_issue_i - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \opc_l_s_opc$next 1'0 - end - sync init - update \opc_l_s_opc 1'0 - sync posedge \coresync_clk - update \opc_l_s_opc \opc_l_s_opc$next - end - process $group_22 - assign \opc_l_r_opc$next \opc_l_r_opc - assign \opc_l_r_opc$next \req_done - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \opc_l_r_opc$next 1'1 - end - sync init - update \opc_l_r_opc 1'1 - sync posedge \coresync_clk - update \opc_l_r_opc \opc_l_r_opc$next - end - process $group_23 - assign \src_l_s_src$next \src_l_s_src - assign \src_l_s_src$next { \cu_issue_i \cu_issue_i \cu_issue_i \cu_issue_i } - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \src_l_s_src$next 4'0000 - end - sync init - update \src_l_s_src 4'0000 - sync posedge \coresync_clk - update \src_l_s_src \src_l_s_src$next - end - process $group_24 - assign \src_l_r_src$next \src_l_r_src - assign \src_l_r_src$next \reset_r - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \src_l_r_src$next 4'1111 - end - sync init - update \src_l_r_src 4'1111 - sync posedge \coresync_clk - update \src_l_r_src \src_l_r_src$next - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:252" - wire width 5 $67 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:252" - cell $and $68 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 5 - connect \A \alu_pulsem - connect \B \cu_wrmask_o - connect \Y $67 - end - process $group_25 - assign \req_l_s_req$next \req_l_s_req - assign \req_l_s_req$next $67 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \req_l_s_req$next 5'00000 - end - sync init - update \req_l_s_req 5'00000 - sync posedge \coresync_clk - update \req_l_s_req \req_l_s_req$next - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:253" - wire width 5 $69 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:253" - cell $or $70 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 5 - connect \A \reset_w - connect \B \prev_wr_go - connect \Y $69 - end - process $group_26 - assign \req_l_r_req$next \req_l_r_req - assign \req_l_r_req$next $69 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \req_l_r_req$next 5'11111 - end - sync init - update \req_l_r_req 5'11111 - sync posedge \coresync_clk - update \req_l_r_req \req_l_r_req$next - end - process $group_27 - assign \alu_alu0_alu_op__insn_type$next \alu_alu0_alu_op__insn_type - assign \alu_alu0_alu_op__fn_unit$next \alu_alu0_alu_op__fn_unit - assign \alu_alu0_alu_op__imm_data__data$next \alu_alu0_alu_op__imm_data__data - assign \alu_alu0_alu_op__imm_data__ok$next \alu_alu0_alu_op__imm_data__ok - assign \alu_alu0_alu_op__rc__rc$next \alu_alu0_alu_op__rc__rc - assign \alu_alu0_alu_op__rc__ok$next \alu_alu0_alu_op__rc__ok - assign \alu_alu0_alu_op__oe__oe$next \alu_alu0_alu_op__oe__oe - assign \alu_alu0_alu_op__oe__ok$next \alu_alu0_alu_op__oe__ok - assign \alu_alu0_alu_op__invert_in$next \alu_alu0_alu_op__invert_in - assign \alu_alu0_alu_op__zero_a$next \alu_alu0_alu_op__zero_a - assign \alu_alu0_alu_op__invert_out$next \alu_alu0_alu_op__invert_out - assign \alu_alu0_alu_op__write_cr0$next \alu_alu0_alu_op__write_cr0 - assign \alu_alu0_alu_op__input_carry$next \alu_alu0_alu_op__input_carry - assign \alu_alu0_alu_op__output_carry$next \alu_alu0_alu_op__output_carry - assign \alu_alu0_alu_op__is_32bit$next \alu_alu0_alu_op__is_32bit - assign \alu_alu0_alu_op__is_signed$next \alu_alu0_alu_op__is_signed - assign \alu_alu0_alu_op__data_len$next \alu_alu0_alu_op__data_len - assign \alu_alu0_alu_op__insn$next \alu_alu0_alu_op__insn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:257" - switch { \cu_issue_i } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:257" - case 1'1 - assign { \alu_alu0_alu_op__insn$next \alu_alu0_alu_op__data_len$next \alu_alu0_alu_op__is_signed$next \alu_alu0_alu_op__is_32bit$next \alu_alu0_alu_op__output_carry$next \alu_alu0_alu_op__input_carry$next \alu_alu0_alu_op__write_cr0$next \alu_alu0_alu_op__invert_out$next \alu_alu0_alu_op__zero_a$next \alu_alu0_alu_op__invert_in$next { \alu_alu0_alu_op__oe__ok$next \alu_alu0_alu_op__oe__oe$next } { \alu_alu0_alu_op__rc__ok$next \alu_alu0_alu_op__rc__rc$next } { \alu_alu0_alu_op__imm_data__ok$next \alu_alu0_alu_op__imm_data__data$next } \alu_alu0_alu_op__fn_unit$next \alu_alu0_alu_op__insn_type$next } { \oper_i_alu_alu0__insn \oper_i_alu_alu0__data_len \oper_i_alu_alu0__is_signed \oper_i_alu_alu0__is_32bit \oper_i_alu_alu0__output_carry \oper_i_alu_alu0__input_carry \oper_i_alu_alu0__write_cr0 \oper_i_alu_alu0__invert_out \oper_i_alu_alu0__zero_a \oper_i_alu_alu0__invert_in { \oper_i_alu_alu0__oe__ok \oper_i_alu_alu0__oe__oe } { \oper_i_alu_alu0__rc__ok \oper_i_alu_alu0__rc__rc } { \oper_i_alu_alu0__imm_data__ok \oper_i_alu_alu0__imm_data__data } \oper_i_alu_alu0__fn_unit \oper_i_alu_alu0__insn_type } - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \alu_alu0_alu_op__imm_data__data$next 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \alu_alu0_alu_op__imm_data__ok$next 1'0 - assign \alu_alu0_alu_op__rc__rc$next 1'0 - assign \alu_alu0_alu_op__rc__ok$next 1'0 - assign \alu_alu0_alu_op__oe__oe$next 1'0 - assign \alu_alu0_alu_op__oe__ok$next 1'0 - end - sync init - update \alu_alu0_alu_op__insn_type 7'0000000 - update \alu_alu0_alu_op__fn_unit 11'00000000000 - update \alu_alu0_alu_op__imm_data__data 64'0000000000000000000000000000000000000000000000000000000000000000 - update \alu_alu0_alu_op__imm_data__ok 1'0 - update \alu_alu0_alu_op__rc__rc 1'0 - update \alu_alu0_alu_op__rc__ok 1'0 - update \alu_alu0_alu_op__oe__oe 1'0 - update \alu_alu0_alu_op__oe__ok 1'0 - update \alu_alu0_alu_op__invert_in 1'0 - update \alu_alu0_alu_op__zero_a 1'0 - update \alu_alu0_alu_op__invert_out 1'0 - update \alu_alu0_alu_op__write_cr0 1'0 - update \alu_alu0_alu_op__input_carry 2'00 - update \alu_alu0_alu_op__output_carry 1'0 - update \alu_alu0_alu_op__is_32bit 1'0 - update \alu_alu0_alu_op__is_signed 1'0 - update \alu_alu0_alu_op__data_len 4'0000 - update \alu_alu0_alu_op__insn 32'00000000000000000000000000000000 - sync posedge \coresync_clk - update \alu_alu0_alu_op__insn_type \alu_alu0_alu_op__insn_type$next - update \alu_alu0_alu_op__fn_unit \alu_alu0_alu_op__fn_unit$next - update \alu_alu0_alu_op__imm_data__data \alu_alu0_alu_op__imm_data__data$next - update \alu_alu0_alu_op__imm_data__ok \alu_alu0_alu_op__imm_data__ok$next - update \alu_alu0_alu_op__rc__rc \alu_alu0_alu_op__rc__rc$next - update \alu_alu0_alu_op__rc__ok \alu_alu0_alu_op__rc__ok$next - update \alu_alu0_alu_op__oe__oe \alu_alu0_alu_op__oe__oe$next - update \alu_alu0_alu_op__oe__ok \alu_alu0_alu_op__oe__ok$next - update \alu_alu0_alu_op__invert_in \alu_alu0_alu_op__invert_in$next - update \alu_alu0_alu_op__zero_a \alu_alu0_alu_op__zero_a$next - update \alu_alu0_alu_op__invert_out \alu_alu0_alu_op__invert_out$next - update \alu_alu0_alu_op__write_cr0 \alu_alu0_alu_op__write_cr0$next - update \alu_alu0_alu_op__input_carry \alu_alu0_alu_op__input_carry$next - update \alu_alu0_alu_op__output_carry \alu_alu0_alu_op__output_carry$next - update \alu_alu0_alu_op__is_32bit \alu_alu0_alu_op__is_32bit$next - update \alu_alu0_alu_op__is_signed \alu_alu0_alu_op__is_signed$next - update \alu_alu0_alu_op__data_len \alu_alu0_alu_op__data_len$next - update \alu_alu0_alu_op__insn \alu_alu0_alu_op__insn$next - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" - wire width 64 \data_r0__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" - wire width 64 \data_r0__o$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" - wire width 1 \data_r0__o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" - wire width 1 \data_r0__o_ok$next - process $group_45 - assign \data_r0__o$next \data_r0__o - assign \data_r0__o_ok$next \data_r0__o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" - switch { \alu_pulse } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" - case 1'1 - assign { \data_r0__o_ok$next \data_r0__o$next } { \o_ok \alu_alu0_o } - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" - switch { \cu_issue_i } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" - case 1'1 - assign { \data_r0__o_ok$next \data_r0__o$next } 65'00000000000000000000000000000000000000000000000000000000000000000 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \data_r0__o_ok$next 1'0 - end - sync init - update \data_r0__o 64'0000000000000000000000000000000000000000000000000000000000000000 - update \data_r0__o_ok 1'0 - sync posedge \coresync_clk - update \data_r0__o \data_r0__o$next - update \data_r0__o_ok \data_r0__o_ok$next - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" - wire width 4 \data_r1__cr_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" - wire width 4 \data_r1__cr_a$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" - wire width 1 \data_r1__cr_a_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" - wire width 1 \data_r1__cr_a_ok$next - process $group_47 - assign \data_r1__cr_a$next \data_r1__cr_a - assign \data_r1__cr_a_ok$next \data_r1__cr_a_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" - switch { \alu_pulse } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" - case 1'1 - assign { \data_r1__cr_a_ok$next \data_r1__cr_a$next } { \cr_a_ok \alu_alu0_cr_a } - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" - switch { \cu_issue_i } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" - case 1'1 - assign { \data_r1__cr_a_ok$next \data_r1__cr_a$next } 5'00000 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \data_r1__cr_a_ok$next 1'0 - end - sync init - update \data_r1__cr_a 4'0000 - update \data_r1__cr_a_ok 1'0 - sync posedge \coresync_clk - update \data_r1__cr_a \data_r1__cr_a$next - update \data_r1__cr_a_ok \data_r1__cr_a_ok$next - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" - wire width 2 \data_r2__xer_ca - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" - wire width 2 \data_r2__xer_ca$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" - wire width 1 \data_r2__xer_ca_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" - wire width 1 \data_r2__xer_ca_ok$next - process $group_49 - assign \data_r2__xer_ca$next \data_r2__xer_ca - assign \data_r2__xer_ca_ok$next \data_r2__xer_ca_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" - switch { \alu_pulse } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" - case 1'1 - assign { \data_r2__xer_ca_ok$next \data_r2__xer_ca$next } { \xer_ca_ok \alu_alu0_xer_ca } - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" - switch { \cu_issue_i } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" - case 1'1 - assign { \data_r2__xer_ca_ok$next \data_r2__xer_ca$next } 3'000 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \data_r2__xer_ca_ok$next 1'0 - end - sync init - update \data_r2__xer_ca 2'00 - update \data_r2__xer_ca_ok 1'0 - sync posedge \coresync_clk - update \data_r2__xer_ca \data_r2__xer_ca$next - update \data_r2__xer_ca_ok \data_r2__xer_ca_ok$next - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" - wire width 2 \data_r3__xer_ov - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" - wire width 2 \data_r3__xer_ov$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" - wire width 1 \data_r3__xer_ov_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" - wire width 1 \data_r3__xer_ov_ok$next - process $group_51 - assign \data_r3__xer_ov$next \data_r3__xer_ov - assign \data_r3__xer_ov_ok$next \data_r3__xer_ov_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" - switch { \alu_pulse } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" - case 1'1 - assign { \data_r3__xer_ov_ok$next \data_r3__xer_ov$next } { \xer_ov_ok \alu_alu0_xer_ov } - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" - switch { \cu_issue_i } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" - case 1'1 - assign { \data_r3__xer_ov_ok$next \data_r3__xer_ov$next } 3'000 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \data_r3__xer_ov_ok$next 1'0 - end - sync init - update \data_r3__xer_ov 2'00 - update \data_r3__xer_ov_ok 1'0 - sync posedge \coresync_clk - update \data_r3__xer_ov \data_r3__xer_ov$next - update \data_r3__xer_ov_ok \data_r3__xer_ov_ok$next - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" - wire width 1 \data_r4__xer_so - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" - wire width 1 \data_r4__xer_so$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" - wire width 1 \data_r4__xer_so_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" - wire width 1 \data_r4__xer_so_ok$next - process $group_53 - assign \data_r4__xer_so$next \data_r4__xer_so - assign \data_r4__xer_so_ok$next \data_r4__xer_so_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" - switch { \alu_pulse } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" - case 1'1 - assign { \data_r4__xer_so_ok$next \data_r4__xer_so$next } { \xer_so_ok \alu_alu0_xer_so } - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" - switch { \cu_issue_i } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" - case 1'1 - assign { \data_r4__xer_so_ok$next \data_r4__xer_so$next } 2'00 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \data_r4__xer_so_ok$next 1'0 - end - sync init - update \data_r4__xer_so 1'0 - update \data_r4__xer_so_ok 1'0 - sync posedge \coresync_clk - update \data_r4__xer_so \data_r4__xer_so$next - update \data_r4__xer_so_ok \data_r4__xer_so_ok$next - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" - wire width 1 $71 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" - cell $and $72 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \o_ok - connect \B \cu_busy_o - connect \Y $71 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" - wire width 1 $73 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" - cell $and $74 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cr_a_ok - connect \B \cu_busy_o - connect \Y $73 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" - wire width 1 $75 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" - cell $and $76 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \xer_ca_ok - connect \B \cu_busy_o - connect \Y $75 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" - wire width 1 $77 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" - cell $and $78 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \xer_ov_ok - connect \B \cu_busy_o - connect \Y $77 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" - wire width 1 $79 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" - cell $and $80 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \xer_so_ok - connect \B \cu_busy_o - connect \Y $79 - end - process $group_55 - assign \cu_wrmask_o 5'00000 - assign \cu_wrmask_o { $79 $77 $75 $73 $71 } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:167" - wire width 1 \src_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:168" - wire width 1 $81 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:168" - cell $mux $82 - parameter \WIDTH 1 - connect \A \src_l_q_src [0] - connect \B \opc_l_q_opc - connect \S \alu_alu0_alu_op__zero_a - connect \Y $81 - end - process $group_56 - assign \src_sel 1'0 - assign \src_sel $81 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:166" - wire width 64 \src_or_imm - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:169" - wire width 64 $83 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:169" - cell $mux $84 - parameter \WIDTH 64 - connect \A \src1_i - connect \B 64'0000000000000000000000000000000000000000000000000000000000000000 - connect \S \alu_alu0_alu_op__zero_a - connect \Y $83 - end - process $group_57 - assign \src_or_imm 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \src_or_imm $83 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:167" - wire width 1 \src_sel$85 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:168" - wire width 1 $86 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:168" - cell $mux $87 - parameter \WIDTH 1 - connect \A \src_l_q_src [1] - connect \B \opc_l_q_opc - connect \S \alu_alu0_alu_op__imm_data__ok - connect \Y $86 - end - process $group_58 - assign \src_sel$85 1'0 - assign \src_sel$85 $86 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:166" - wire width 64 \src_or_imm$88 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:169" - wire width 64 $89 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:169" - cell $mux $90 - parameter \WIDTH 64 - connect \A \src2_i - connect \B \alu_alu0_alu_op__imm_data__data - connect \S \alu_alu0_alu_op__imm_data__ok - connect \Y $89 - end - process $group_59 - assign \src_or_imm$88 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \src_or_imm$88 $89 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" - wire width 64 \src_r0 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" - wire width 64 \src_r0$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - wire width 64 $91 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - cell $mux $92 - parameter \WIDTH 64 - connect \A \src_r0 - connect \B \src_or_imm - connect \S \src_sel - connect \Y $91 - end - process $group_60 - assign \alu_alu0_ra 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \alu_alu0_ra $91 - sync init - end - process $group_61 - assign \src_r0$next \src_r0 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" - switch { \src_sel } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" - case 1'1 - assign \src_r0$next \src_or_imm - end - sync init - update \src_r0 64'0000000000000000000000000000000000000000000000000000000000000000 - sync posedge \coresync_clk - update \src_r0 \src_r0$next - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" - wire width 64 \src_r1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" - wire width 64 \src_r1$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - wire width 64 $93 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - cell $mux $94 - parameter \WIDTH 64 - connect \A \src_r1 - connect \B \src_or_imm$88 - connect \S \src_sel$85 - connect \Y $93 - end - process $group_62 - assign \alu_alu0_rb 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \alu_alu0_rb $93 - sync init - end - process $group_63 - assign \src_r1$next \src_r1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" - switch { \src_sel$85 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" - case 1'1 - assign \src_r1$next \src_or_imm$88 - end - sync init - update \src_r1 64'0000000000000000000000000000000000000000000000000000000000000000 - sync posedge \coresync_clk - update \src_r1 \src_r1$next - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" - wire width 1 \src_r2 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" - wire width 1 \src_r2$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - wire width 1 $95 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - cell $mux $96 - parameter \WIDTH 1 - connect \A \src_r2 - connect \B \src3_i - connect \S \src_l_q_src [2] - connect \Y $95 - end - process $group_64 - assign \alu_alu0_xer_so$1 1'0 - assign \alu_alu0_xer_so$1 $95 - sync init - end - process $group_65 - assign \src_r2$next \src_r2 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" - switch { \src_l_q_src [2] } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" - case 1'1 - assign \src_r2$next \src3_i - end - sync init - update \src_r2 1'0 - sync posedge \coresync_clk - update \src_r2 \src_r2$next - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" - wire width 2 \src_r3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" - wire width 2 \src_r3$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - wire width 2 $97 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - cell $mux $98 - parameter \WIDTH 2 - connect \A \src_r3 - connect \B \src4_i - connect \S \src_l_q_src [3] - connect \Y $97 - end - process $group_66 - assign \alu_alu0_xer_ca$2 2'00 - assign \alu_alu0_xer_ca$2 $97 - sync init - end - process $group_67 - assign \src_r3$next \src_r3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" - switch { \src_l_q_src [3] } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" - case 1'1 - assign \src_r3$next \src4_i - end - sync init - update \src_r3 2'00 - sync posedge \coresync_clk - update \src_r3 \src_r3$next - end - process $group_68 - assign \alu_alu0_p_valid_i 1'0 - assign \alu_alu0_p_valid_i \alui_l_q_alui - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:327" - wire width 1 $99 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:327" - cell $and $100 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \alu_alu0_p_ready_o - connect \B \alui_l_q_alui - connect \Y $99 - end - process $group_69 - assign \alui_l_r_alui$next \alui_l_r_alui - assign \alui_l_r_alui$next $99 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \alui_l_r_alui$next 1'1 - end - sync init - update \alui_l_r_alui 1'1 - sync posedge \coresync_clk - update \alui_l_r_alui \alui_l_r_alui$next - end - process $group_70 - assign \alui_l_s_alui 1'0 - assign \alui_l_s_alui \all_rd_pulse - sync init - end - process $group_71 - assign \alu_alu0_n_ready_i 1'0 - assign \alu_alu0_n_ready_i \alu_l_q_alu - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:334" - wire width 1 $101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:334" - cell $and $102 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \alu_alu0_n_valid_o - connect \B \alu_l_q_alu - connect \Y $101 - end - process $group_72 - assign \alu_l_r_alu$next \alu_l_r_alu - assign \alu_l_r_alu$next $101 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \alu_l_r_alu$next 1'1 - end - sync init - update \alu_l_r_alu 1'1 - sync posedge \coresync_clk - update \alu_l_r_alu \alu_l_r_alu$next - end - process $group_73 - assign \alu_l_s_alu 1'0 - assign \alu_l_s_alu \all_rd_pulse - sync init - end - process $group_74 - assign \cu_busy_o 1'0 - assign \cu_busy_o \opc_l_q_opc - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - wire width 4 $103 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - cell $and $104 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A \src_l_q_src - connect \B { \cu_busy_o \cu_busy_o \cu_busy_o \cu_busy_o } - connect \Y $103 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:173" - wire width 1 $105 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:173" - cell $not $106 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \alu_alu0_alu_op__zero_a - connect \Y $105 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:173" - wire width 1 $107 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:173" - cell $not $108 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \alu_alu0_alu_op__imm_data__ok - connect \Y $107 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - wire width 4 $109 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - cell $and $110 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A $103 - connect \B { 1'1 1'1 $107 $105 } - connect \Y $109 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - wire width 4 $111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - cell $not $112 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A \cu_rdmaskn_i - connect \Y $111 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - wire width 4 $113 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - cell $and $114 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A $109 - connect \B $111 - connect \Y $113 - end - process $group_75 - assign \cu_rd__rel_o 4'0000 - assign \cu_rd__rel_o $113 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:102" - wire width 1 \cu_shadown_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" - wire width 1 $115 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" - cell $and $116 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cu_busy_o - connect \B \cu_shadown_i - connect \Y $115 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" - wire width 1 $117 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" - cell $and $118 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cu_busy_o - connect \B \cu_shadown_i - connect \Y $117 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" - wire width 1 $119 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" - cell $and $120 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cu_busy_o - connect \B \cu_shadown_i - connect \Y $119 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" - wire width 1 $121 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" - cell $and $122 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cu_busy_o - connect \B \cu_shadown_i - connect \Y $121 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" - wire width 1 $123 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" - cell $and $124 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cu_busy_o - connect \B \cu_shadown_i - connect \Y $123 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351" - wire width 5 $125 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351" - cell $and $126 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 5 - connect \A \req_l_q_req - connect \B { $115 $117 $119 $121 $123 } - connect \Y $125 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351" - wire width 5 $127 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351" - cell $and $128 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 5 - connect \A $125 - connect \B \cu_wrmask_o - connect \Y $127 - end - process $group_76 - assign \cu_wr__rel_o 5'00000 - assign \cu_wr__rel_o $127 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - wire width 1 $129 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - cell $and $130 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cu_wr__go_i [0] - connect \B \cu_busy_o - connect \Y $129 - end - process $group_77 - assign \dest1_o 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - switch { $129 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - case 1'1 - assign \dest1_o { \data_r0__o_ok \data_r0__o } [63:0] - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - wire width 1 $131 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - cell $and $132 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cu_wr__go_i [1] - connect \B \cu_busy_o - connect \Y $131 - end - process $group_78 - assign \dest2_o 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - switch { $131 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - case 1'1 - assign \dest2_o { \data_r1__cr_a_ok \data_r1__cr_a } [3:0] - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - wire width 1 $133 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - cell $and $134 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cu_wr__go_i [2] - connect \B \cu_busy_o - connect \Y $133 - end - process $group_79 - assign \dest3_o 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - switch { $133 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - case 1'1 - assign \dest3_o { \data_r2__xer_ca_ok \data_r2__xer_ca } [1:0] - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - wire width 1 $135 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - cell $and $136 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cu_wr__go_i [3] - connect \B \cu_busy_o - connect \Y $135 - end - process $group_80 - assign \dest4_o 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - switch { $135 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - case 1'1 - assign \dest4_o { \data_r3__xer_ov_ok \data_r3__xer_ov } [1:0] - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - wire width 1 $137 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - cell $and $138 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cu_wr__go_i [4] - connect \B \cu_busy_o - connect \Y $137 - end - process $group_81 - assign \dest5_o 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - switch { $137 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - case 1'1 - assign \dest5_o { \data_r4__xer_so_ok \data_r4__xer_so } [0] - end - sync init - end - connect \cu_go_die_i 1'0 - connect \cu_shadown_i 1'1 -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.cr0.alu_cr0.p" -module \p$5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" - wire width 1 input 0 \p_valid_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" - wire width 1 input 1 \p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:158" - wire width 1 \trigger - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" - cell $and $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \p_valid_i - connect \B \p_ready_o - connect \Y $1 - end - process $group_0 - assign \trigger 1'0 - assign \trigger $1 - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.cr0.alu_cr0.n" -module \n$6 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" - wire width 1 input 0 \n_valid_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" - wire width 1 input 1 \n_ready_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:251" - wire width 1 \trigger - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" - cell $and $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \n_ready_i - connect \B \n_valid_o - connect \Y $1 - end - process $group_0 - assign \trigger 1'0 - assign \trigger $1 - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.cr0.alu_cr0.pipe.p" -module \p$7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" - wire width 1 input 0 \p_valid_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" - wire width 1 input 1 \p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:158" - wire width 1 \trigger - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" - cell $and $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \p_valid_i - connect \B \p_ready_o - connect \Y $1 - end - process $group_0 - assign \trigger 1'0 - assign \trigger $1 - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.cr0.alu_cr0.pipe.n" -module \n$8 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" - wire width 1 input 0 \n_valid_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" - wire width 1 input 1 \n_ready_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:251" - wire width 1 \trigger - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" - cell $and $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \n_ready_i - connect \B \n_valid_o - connect \Y $1 - end - process $group_0 - assign \trigger 1'0 - assign \trigger $1 - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.cr0.alu_cr0.pipe.main" -module \main$9 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 input 0 \muxid - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute 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"OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 input 1 \cr_op__insn_type - attribute \enum_base_type "Function" - attribute \enum_value_00000000000 "NONE" - attribute \enum_value_00000000010 "ALU" - attribute \enum_value_00000000100 "LDST" - attribute \enum_value_00000001000 "SHIFT_ROT" - attribute \enum_value_00000010000 "LOGICAL" - attribute \enum_value_00000100000 "BRANCH" - attribute \enum_value_00001000000 "CR" - attribute \enum_value_00010000000 "TRAP" - attribute \enum_value_00100000000 "MUL" - attribute \enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 input 2 \cr_op__fn_unit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 input 3 \cr_op__insn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 4 \ra - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 5 \rb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 32 input 6 \full_cr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 4 input 7 \cr_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 4 input 8 \cr_b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 4 input 9 \cr_c - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 output 10 \muxid$1 - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 output 11 \cr_op__insn_type$2 - attribute \enum_base_type "Function" - attribute \enum_value_00000000000 "NONE" - attribute \enum_value_00000000010 "ALU" - attribute \enum_value_00000000100 "LDST" - attribute \enum_value_00000001000 "SHIFT_ROT" - attribute \enum_value_00000010000 "LOGICAL" - attribute \enum_value_00000100000 "BRANCH" - attribute \enum_value_00001000000 "CR" - attribute \enum_value_00010000000 "TRAP" - attribute \enum_value_00100000000 "MUL" - attribute \enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 output 12 \cr_op__fn_unit$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 output 13 \cr_op__insn$4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 output 14 \o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 15 \o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 32 output 16 \full_cr$5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 17 \full_cr_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 4 output 18 \cr_a$6 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 19 \cr_a_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 5 $7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - cell $pos $8 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \Y_WIDTH 5 - connect \A \cr_a - connect \Y $7 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:97" - wire width 1 \bit_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:81" - wire width 2 \bt - process $group_0 - assign \cr_a$6 4'0000 - assign \cr_a_ok 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:52" - switch \cr_op__insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:54" - attribute \nmigen.decoding "OP_MCRF/42" - case 7'0101010 - assign { \cr_a_ok \cr_a$6 } $7 - assign \cr_a_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:63" - attribute \nmigen.decoding "OP_CROP/69" - case 7'1000101 - assign \cr_a$6 \cr_c - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:105" - switch \bt - case 2'00 - assign { \cr_a_ok \cr_a$6 } [0] \bit_o - case 2'01 - assign { \cr_a_ok \cr_a$6 } [1] \bit_o - case 2'10 - assign { \cr_a_ok \cr_a$6 } [2] \bit_o - case 2'-- - assign { \cr_a_ok \cr_a$6 } [3] \bit_o - end - switch { } - case - assign \cr_a_ok 1'1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:109" - attribute \nmigen.decoding "OP_MTCRF/48" - case 7'0110000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:118" - attribute \nmigen.decoding "OP_MFCR/45" - case 7'0101101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:127" - attribute \nmigen.decoding "OP_ISEL/35" - case 7'0100011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:143" - attribute \nmigen.decoding "OP_SETB/59" - case 7'0111011 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:70" - wire width 4 \lut - process $group_2 - assign \lut 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:52" - switch \cr_op__insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:54" - attribute \nmigen.decoding "OP_MCRF/42" - case 7'0101010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:63" - attribute \nmigen.decoding "OP_CROP/69" - case 7'1000101 - assign \lut \cr_op__insn [9:6] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:109" - attribute \nmigen.decoding "OP_MTCRF/48" - case 7'0110000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:118" - attribute \nmigen.decoding "OP_MFCR/45" - case 7'0101101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:127" - attribute \nmigen.decoding "OP_ISEL/35" - case 7'0100011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:143" - attribute \nmigen.decoding "OP_SETB/59" - case 7'0111011 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:86" - wire width 3 $9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:86" - wire width 3 $10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:86" - cell $sub $11 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 3 - connect \A 2'11 - connect \B { \cr_op__insn [22] \cr_op__insn [21] } - connect \Y $10 - end - connect $9 $10 - process $group_3 - assign \bt 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:52" - switch \cr_op__insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:54" - attribute \nmigen.decoding "OP_MCRF/42" - case 7'0101010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:63" - attribute \nmigen.decoding "OP_CROP/69" - case 7'1000101 - assign \bt $9 [1:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:109" - attribute \nmigen.decoding "OP_MTCRF/48" - case 7'0110000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:118" - attribute \nmigen.decoding "OP_MFCR/45" - case 7'0101101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:127" - attribute \nmigen.decoding "OP_ISEL/35" - case 7'0100011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:143" - attribute \nmigen.decoding "OP_SETB/59" - case 7'0111011 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:82" - wire width 2 \ba - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:87" - wire width 3 $12 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:87" - wire width 3 $13 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:87" - cell $sub $14 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 3 - connect \A 2'11 - connect \B { \cr_op__insn [17] \cr_op__insn [16] } - connect \Y $13 - end - connect $12 $13 - process $group_4 - assign \ba 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:52" - switch \cr_op__insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:54" - attribute \nmigen.decoding "OP_MCRF/42" - case 7'0101010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:63" - attribute \nmigen.decoding "OP_CROP/69" - case 7'1000101 - assign \ba $12 [1:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:109" - attribute \nmigen.decoding "OP_MTCRF/48" - case 7'0110000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:118" - attribute \nmigen.decoding "OP_MFCR/45" - case 7'0101101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:127" - attribute \nmigen.decoding "OP_ISEL/35" - case 7'0100011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:143" - attribute \nmigen.decoding "OP_SETB/59" - case 7'0111011 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:83" - wire width 2 \bb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:88" - wire width 3 $15 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:88" - wire width 3 $16 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:88" - cell $sub $17 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 3 - connect \A 2'11 - connect \B { \cr_op__insn [12] \cr_op__insn [11] } - connect \Y $16 - end - connect $15 $16 - process $group_5 - assign \bb 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:52" - switch \cr_op__insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:54" - attribute \nmigen.decoding "OP_MCRF/42" - case 7'0101010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:63" - attribute \nmigen.decoding "OP_CROP/69" - case 7'1000101 - assign \bb $15 [1:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:109" - attribute \nmigen.decoding "OP_MTCRF/48" - case 7'0110000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:118" - attribute \nmigen.decoding "OP_MFCR/45" - case 7'0101101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:127" - attribute \nmigen.decoding "OP_ISEL/35" - case 7'0100011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:143" - attribute \nmigen.decoding "OP_SETB/59" - case 7'0111011 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:91" - wire width 1 \bit_a - process $group_6 - assign \bit_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:52" - switch \cr_op__insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:54" - attribute \nmigen.decoding "OP_MCRF/42" - case 7'0101010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:63" - attribute \nmigen.decoding "OP_CROP/69" - case 7'1000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:93" - switch \ba - case 2'00 - assign \bit_a \cr_a [0] - case 2'01 - assign \bit_a \cr_a [1] - case 2'10 - assign \bit_a \cr_a [2] - case 2'-- - assign \bit_a \cr_a [3] - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:109" - attribute \nmigen.decoding "OP_MTCRF/48" - case 7'0110000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:118" - attribute \nmigen.decoding "OP_MFCR/45" - case 7'0101101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:127" - attribute \nmigen.decoding "OP_ISEL/35" - case 7'0100011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:143" - attribute \nmigen.decoding "OP_SETB/59" - case 7'0111011 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:92" - wire width 1 \bit_b - process $group_7 - assign \bit_b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:52" - switch \cr_op__insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:54" - attribute \nmigen.decoding "OP_MCRF/42" - case 7'0101010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:63" - attribute \nmigen.decoding "OP_CROP/69" - case 7'1000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:94" - switch \bb - case 2'00 - assign \bit_b \cr_b [0] - case 2'01 - assign \bit_b \cr_b [1] - case 2'10 - assign \bit_b \cr_b [2] - case 2'-- - assign \bit_b \cr_b [3] - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:109" - attribute \nmigen.decoding "OP_MTCRF/48" - case 7'0110000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:118" - attribute \nmigen.decoding "OP_MFCR/45" - case 7'0101101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:127" - attribute \nmigen.decoding "OP_ISEL/35" - case 7'0100011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:143" - attribute \nmigen.decoding "OP_SETB/59" - case 7'0111011 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:99" - wire width 1 $18 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:99" - cell $mux $19 - parameter \WIDTH 1 - connect \A \lut [1] - connect \B \lut [3] - connect \S \bit_a - connect \Y $18 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:100" - wire width 1 $20 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:100" - cell $mux $21 - parameter \WIDTH 1 - connect \A \lut [0] - connect \B \lut [2] - connect \S \bit_a - connect \Y $20 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:100" - wire width 1 $22 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:100" - cell $mux $23 - parameter \WIDTH 1 - connect \A $20 - connect \B $18 - connect \S \bit_b - connect \Y $22 - end - process $group_8 - assign \bit_o 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:52" - switch \cr_op__insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:54" - attribute \nmigen.decoding "OP_MCRF/42" - case 7'0101010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:63" - attribute \nmigen.decoding "OP_CROP/69" - case 7'1000101 - assign \bit_o $22 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:109" - attribute \nmigen.decoding "OP_MTCRF/48" - case 7'0110000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:118" - attribute \nmigen.decoding "OP_MFCR/45" - case 7'0101101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:127" - attribute \nmigen.decoding "OP_ISEL/35" - case 7'0100011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:143" - attribute \nmigen.decoding "OP_SETB/59" - case 7'0111011 - end - sync init - end - process $group_9 - assign \full_cr$5 32'00000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:52" - switch \cr_op__insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:54" - attribute \nmigen.decoding "OP_MCRF/42" - case 7'0101010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:63" - attribute \nmigen.decoding "OP_CROP/69" - case 7'1000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:109" - attribute \nmigen.decoding "OP_MTCRF/48" - case 7'0110000 - assign \full_cr$5 \ra [31:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:118" - attribute \nmigen.decoding "OP_MFCR/45" - case 7'0101101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:127" - attribute \nmigen.decoding "OP_ISEL/35" - case 7'0100011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:143" - attribute \nmigen.decoding "OP_SETB/59" - case 7'0111011 - end - sync init - end - process $group_10 - assign \full_cr_ok 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:52" - switch \cr_op__insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:54" - attribute \nmigen.decoding "OP_MCRF/42" - case 7'0101010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:63" - attribute \nmigen.decoding "OP_CROP/69" - case 7'1000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:109" - attribute \nmigen.decoding "OP_MTCRF/48" - case 7'0110000 - assign \full_cr_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:118" - attribute \nmigen.decoding "OP_MFCR/45" - case 7'0101101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:127" - attribute \nmigen.decoding "OP_ISEL/35" - case 7'0100011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:143" - attribute \nmigen.decoding "OP_SETB/59" - case 7'0111011 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 $24 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - cell $pos $25 - parameter \A_SIGNED 0 - parameter \A_WIDTH 32 - parameter \Y_WIDTH 64 - connect \A \full_cr - connect \Y $24 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:140" - wire width 65 $26 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:140" - wire width 64 $27 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:136" - wire width 1 \cr_bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:140" - cell $mux $28 - parameter \WIDTH 64 - connect \A \rb - connect \B \ra - connect \S \cr_bit - connect \Y $27 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:140" - cell $pos $29 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \Y_WIDTH 65 - connect \A $27 - connect \Y $26 - end - process $group_11 - assign \o 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \o_ok 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:52" - switch \cr_op__insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:54" - attribute \nmigen.decoding "OP_MCRF/42" - case 7'0101010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:63" - attribute \nmigen.decoding "OP_CROP/69" - case 7'1000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:109" - attribute \nmigen.decoding "OP_MTCRF/48" - case 7'0110000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:118" - attribute \nmigen.decoding "OP_MFCR/45" - case 7'0101101 - assign \o $24 - assign \o_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:127" - attribute \nmigen.decoding "OP_ISEL/35" - case 7'0100011 - assign { \o_ok \o } $26 - assign \o_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:143" - attribute \nmigen.decoding "OP_SETB/59" - case 7'0111011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:144" - switch { \cr_a [2] \cr_a [3] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:144" - case 2'-1 - assign \o 64'1111111111111111111111111111111111111111111111111111111111111111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:146" - case 2'1- - assign \o 64'0000000000000000000000000000000000000000000000000000000000000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:148" - case - assign \o 64'0000000000000000000000000000000000000000000000000000000000000000 - end - switch { } - case - assign \o_ok 1'1 - end - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:131" - wire width 2 \BC - process $group_13 - assign \BC 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:52" - switch \cr_op__insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:54" - attribute \nmigen.decoding "OP_MCRF/42" - case 7'0101010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:63" - attribute \nmigen.decoding "OP_CROP/69" - case 7'1000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:109" - attribute \nmigen.decoding "OP_MTCRF/48" - case 7'0110000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:118" - attribute \nmigen.decoding "OP_MFCR/45" - case 7'0101101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:127" - attribute \nmigen.decoding "OP_ISEL/35" - case 7'0100011 - assign \BC { \cr_op__insn [7] \cr_op__insn [6] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:143" - attribute \nmigen.decoding "OP_SETB/59" - case 7'0111011 - end - sync init - end - process $group_14 - assign \cr_bit 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:52" - switch \cr_op__insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:54" - attribute \nmigen.decoding "OP_MCRF/42" - case 7'0101010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:63" - attribute \nmigen.decoding "OP_CROP/69" - case 7'1000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:109" - attribute \nmigen.decoding "OP_MTCRF/48" - case 7'0110000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:118" - attribute \nmigen.decoding "OP_MFCR/45" - case 7'0101101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:127" - attribute \nmigen.decoding "OP_ISEL/35" - case 7'0100011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:137" - switch \BC - case 2'00 - assign \cr_bit \cr_a [3] - case 2'01 - assign \cr_bit \cr_a [2] - case 2'10 - assign \cr_bit \cr_a [1] - case 2'-- - assign \cr_bit \cr_a [0] - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/cr/main_stage.py:143" - attribute \nmigen.decoding "OP_SETB/59" - case 7'0111011 - end - sync init - end - process $group_15 - assign \muxid$1 2'00 - assign \muxid$1 \muxid - sync init - end - process $group_16 - assign \cr_op__insn_type$2 7'0000000 - assign \cr_op__fn_unit$3 11'00000000000 - assign \cr_op__insn$4 32'00000000000000000000000000000000 - assign { \cr_op__insn$4 \cr_op__fn_unit$3 \cr_op__insn_type$2 } { \cr_op__insn \cr_op__fn_unit \cr_op__insn_type } - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.cr0.alu_cr0.pipe" -module \pipe - attribute \src "simple/issuer.py:141" - wire width 1 input 0 \coresync_clk - attribute \src "simple/issuer.py:141" - wire width 1 input 1 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" - wire width 1 input 2 \p_valid_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" - wire width 1 output 3 \p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 input 4 \muxid - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 input 5 \cr_op__insn_type - attribute \enum_base_type "Function" - attribute \enum_value_00000000000 "NONE" - attribute \enum_value_00000000010 "ALU" - attribute \enum_value_00000000100 "LDST" - attribute \enum_value_00000001000 "SHIFT_ROT" - attribute \enum_value_00000010000 "LOGICAL" - attribute \enum_value_00000100000 "BRANCH" - attribute \enum_value_00001000000 "CR" - attribute \enum_value_00010000000 "TRAP" - attribute \enum_value_00100000000 "MUL" - attribute \enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 input 6 \cr_op__fn_unit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 input 7 \cr_op__insn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 8 \ra - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 9 \rb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 32 input 10 \full_cr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 4 input 11 \cr_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 4 input 12 \cr_b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 4 input 13 \cr_c - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" - wire width 1 output 14 \n_valid_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" - wire width 1 input 15 \n_ready_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 output 16 \muxid$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \muxid$1$next - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute 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"OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \cr_op__insn_type$17 - attribute \enum_base_type "Function" - attribute \enum_value_00000000000 "NONE" - attribute \enum_value_00000000010 "ALU" - attribute \enum_value_00000000100 "LDST" - attribute \enum_value_00000001000 "SHIFT_ROT" - attribute \enum_value_00000010000 "LOGICAL" - attribute \enum_value_00000100000 "BRANCH" - attribute \enum_value_00001000000 "CR" - attribute \enum_value_00010000000 "TRAP" - attribute \enum_value_00100000000 "MUL" - attribute \enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 \cr_op__fn_unit$18 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \cr_op__insn$19 - process $group_14 - assign \cr_op__insn_type$17 7'0000000 - assign \cr_op__fn_unit$18 11'00000000000 - assign \cr_op__insn$19 32'00000000000000000000000000000000 - assign { \cr_op__insn$19 \cr_op__fn_unit$18 \cr_op__insn_type$17 } { \main_cr_op__insn$10 \main_cr_op__fn_unit$9 \main_cr_op__insn_type$8 } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 \o$20 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \o_ok$21 - process $group_17 - assign \o$20 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \o_ok$21 1'0 - assign { \o_ok$21 \o$20 } { \main_o_ok \main_o } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 32 \full_cr$22 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \full_cr_ok$23 - process $group_19 - assign \full_cr$22 32'00000000000000000000000000000000 - assign \full_cr_ok$23 1'0 - assign { \full_cr_ok$23 \full_cr$22 } { \main_full_cr_ok \main_full_cr$11 } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 4 \cr_a$24 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \cr_a_ok$25 - process $group_21 - assign \cr_a$24 4'0000 - assign \cr_a_ok$25 1'0 - assign { \cr_a_ok$25 \cr_a$24 } { \main_cr_a_ok \main_cr_a$12 } - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615" - wire width 1 \r_busy - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615" - wire width 1 \r_busy$next - process $group_23 - assign \r_busy$next \r_busy - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign \r_busy$next 1'1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign \r_busy$next 1'0 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \r_busy$next 1'0 - end - sync init - update \r_busy 1'0 - sync posedge \coresync_clk - update \r_busy \r_busy$next - end - process $group_24 - assign \muxid$1$next \muxid$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign \muxid$1$next \muxid$16 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign \muxid$1$next \muxid$16 - end - sync init - update \muxid$1 2'00 - sync posedge \coresync_clk - update \muxid$1 \muxid$1$next - end - process $group_25 - assign \cr_op__insn_type$2$next \cr_op__insn_type$2 - assign \cr_op__fn_unit$3$next \cr_op__fn_unit$3 - assign \cr_op__insn$4$next \cr_op__insn$4 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign { \cr_op__insn$4$next \cr_op__fn_unit$3$next \cr_op__insn_type$2$next } { \cr_op__insn$19 \cr_op__fn_unit$18 \cr_op__insn_type$17 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign { \cr_op__insn$4$next \cr_op__fn_unit$3$next \cr_op__insn_type$2$next } { \cr_op__insn$19 \cr_op__fn_unit$18 \cr_op__insn_type$17 } - end - sync init - update \cr_op__insn_type$2 7'0000000 - update \cr_op__fn_unit$3 11'00000000000 - update \cr_op__insn$4 32'00000000000000000000000000000000 - sync posedge \coresync_clk - update \cr_op__insn_type$2 \cr_op__insn_type$2$next - update \cr_op__fn_unit$3 \cr_op__fn_unit$3$next - update \cr_op__insn$4 \cr_op__insn$4$next - end - process $group_28 - assign \o$next \o - assign \o_ok$next \o_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign { \o_ok$next \o$next } { \o_ok$21 \o$20 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign { \o_ok$next \o$next } { \o_ok$21 \o$20 } - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \o_ok$next 1'0 - end - sync init - update \o 64'0000000000000000000000000000000000000000000000000000000000000000 - update \o_ok 1'0 - sync posedge \coresync_clk - update \o \o$next - update \o_ok \o_ok$next - end - process $group_30 - assign \full_cr$5$next \full_cr$5 - assign \full_cr_ok$next \full_cr_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign { \full_cr_ok$next \full_cr$5$next } { \full_cr_ok$23 \full_cr$22 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign { \full_cr_ok$next \full_cr$5$next } { \full_cr_ok$23 \full_cr$22 } - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \full_cr_ok$next 1'0 - end - sync init - update \full_cr$5 32'00000000000000000000000000000000 - update \full_cr_ok 1'0 - sync posedge \coresync_clk - update \full_cr$5 \full_cr$5$next - update \full_cr_ok \full_cr_ok$next - end - process $group_32 - assign \cr_a$6$next \cr_a$6 - assign \cr_a_ok$next \cr_a_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign { \cr_a_ok$next \cr_a$6$next } { \cr_a_ok$25 \cr_a$24 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign { \cr_a_ok$next \cr_a$6$next } { \cr_a_ok$25 \cr_a$24 } - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \cr_a_ok$next 1'0 - end - sync init - update \cr_a$6 4'0000 - update \cr_a_ok 1'0 - sync posedge \coresync_clk - update \cr_a$6 \cr_a$6$next - update \cr_a_ok \cr_a_ok$next - end - process $group_34 - assign \n_valid_o 1'0 - assign \n_valid_o \r_busy - sync init - end - process $group_35 - assign \p_ready_o 1'0 - assign \p_ready_o \n_i_rdy_data - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.cr0.alu_cr0" -module \alu_cr0 - attribute \src "simple/issuer.py:141" - wire width 1 input 0 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 1 \o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 2 \full_cr_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 3 \cr_a_ok - attribute \src "simple/issuer.py:141" - wire width 1 input 4 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" - wire width 1 output 5 \n_valid_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" - wire width 1 input 6 \n_ready_i - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 input 7 \cr_op__insn_type - attribute \enum_base_type "Function" - attribute \enum_value_00000000000 "NONE" - attribute \enum_value_00000000010 "ALU" - attribute \enum_value_00000000100 "LDST" - attribute \enum_value_00000001000 "SHIFT_ROT" - attribute \enum_value_00000010000 "LOGICAL" - attribute \enum_value_00000100000 "BRANCH" - attribute \enum_value_00001000000 "CR" - attribute \enum_value_00010000000 "TRAP" - attribute \enum_value_00100000000 "MUL" - attribute \enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 input 8 \cr_op__fn_unit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 input 9 \cr_op__insn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 output 10 \o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 32 output 11 \full_cr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 4 output 12 \cr_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 13 \ra - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 14 \rb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 32 input 15 \full_cr$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 4 input 16 \cr_a$2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 4 input 17 \cr_b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 4 input 18 \cr_c - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" - wire width 1 input 19 \p_valid_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" - wire width 1 output 20 \p_ready_o - cell \p$5 \p - connect \p_valid_i \p_valid_i - connect \p_ready_o \p_ready_o - end - cell \n$6 \n - connect \n_valid_o \n_valid_o - connect \n_ready_i \n_ready_i - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" - wire width 1 \pipe_p_valid_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" - wire width 1 \pipe_p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \pipe_muxid - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \pipe_cr_op__insn_type - attribute \enum_base_type "Function" - attribute \enum_value_00000000000 "NONE" - attribute \enum_value_00000000010 "ALU" - attribute \enum_value_00000000100 "LDST" - attribute \enum_value_00000001000 "SHIFT_ROT" - attribute \enum_value_00000010000 "LOGICAL" - attribute \enum_value_00000100000 "BRANCH" - attribute \enum_value_00001000000 "CR" - attribute \enum_value_00010000000 "TRAP" - attribute \enum_value_00100000000 "MUL" - attribute \enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 \pipe_cr_op__fn_unit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \pipe_cr_op__insn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \pipe_ra - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \pipe_rb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 32 \pipe_full_cr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 4 \pipe_cr_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 4 \pipe_cr_b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 4 \pipe_cr_c - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" - wire width 1 \pipe_n_valid_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" - wire width 1 \pipe_n_ready_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \pipe_muxid$3 - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \pipe_cr_op__insn_type$4 - attribute \enum_base_type "Function" - attribute \enum_value_00000000000 "NONE" - attribute \enum_value_00000000010 "ALU" - attribute \enum_value_00000000100 "LDST" - attribute \enum_value_00000001000 "SHIFT_ROT" - attribute \enum_value_00000010000 "LOGICAL" - attribute \enum_value_00000100000 "BRANCH" - attribute \enum_value_00001000000 "CR" - attribute \enum_value_00010000000 "TRAP" - attribute \enum_value_00100000000 "MUL" - attribute \enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 \pipe_cr_op__fn_unit$5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \pipe_cr_op__insn$6 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 \pipe_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \pipe_o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 32 \pipe_full_cr$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \pipe_full_cr_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 4 \pipe_cr_a$8 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \pipe_cr_a_ok - cell \pipe \pipe - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \p_valid_i \pipe_p_valid_i - connect \p_ready_o \pipe_p_ready_o - connect \muxid \pipe_muxid - connect \cr_op__insn_type \pipe_cr_op__insn_type - connect \cr_op__fn_unit \pipe_cr_op__fn_unit - connect \cr_op__insn \pipe_cr_op__insn - connect \ra \pipe_ra - connect \rb \pipe_rb - connect \full_cr \pipe_full_cr - connect \cr_a \pipe_cr_a - connect \cr_b \pipe_cr_b - connect \cr_c \pipe_cr_c - connect \n_valid_o \pipe_n_valid_o - connect \n_ready_i \pipe_n_ready_i - connect \muxid$1 \pipe_muxid$3 - connect \cr_op__insn_type$2 \pipe_cr_op__insn_type$4 - connect \cr_op__fn_unit$3 \pipe_cr_op__fn_unit$5 - connect \cr_op__insn$4 \pipe_cr_op__insn$6 - connect \o \pipe_o - connect \o_ok \pipe_o_ok - connect \full_cr$5 \pipe_full_cr$7 - connect \full_cr_ok \pipe_full_cr_ok - connect \cr_a$6 \pipe_cr_a$8 - connect \cr_a_ok \pipe_cr_a_ok - end - process $group_0 - assign \pipe_p_valid_i 1'0 - assign \pipe_p_valid_i \p_valid_i - sync init - end - process $group_1 - assign \p_ready_o 1'0 - assign \p_ready_o \pipe_p_ready_o - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \muxid - process $group_2 - assign \pipe_muxid 2'00 - assign \pipe_muxid \muxid - sync init - end - process $group_3 - assign \pipe_cr_op__insn_type 7'0000000 - assign \pipe_cr_op__fn_unit 11'00000000000 - assign \pipe_cr_op__insn 32'00000000000000000000000000000000 - assign { \pipe_cr_op__insn \pipe_cr_op__fn_unit \pipe_cr_op__insn_type } { \cr_op__insn \cr_op__fn_unit \cr_op__insn_type } - sync init - end - process $group_6 - assign \pipe_ra 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \pipe_ra \ra - sync init - end - process $group_7 - assign \pipe_rb 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \pipe_rb \rb - sync init - end - process $group_8 - assign \pipe_full_cr 32'00000000000000000000000000000000 - assign \pipe_full_cr \full_cr$1 - sync init - end - process $group_9 - assign \pipe_cr_a 4'0000 - assign \pipe_cr_a \cr_a$2 - sync init - end - process $group_10 - assign \pipe_cr_b 4'0000 - assign \pipe_cr_b \cr_b - sync init - end - process $group_11 - assign \pipe_cr_c 4'0000 - assign \pipe_cr_c \cr_c - sync init - end - process $group_12 - assign \n_valid_o 1'0 - assign \n_valid_o \pipe_n_valid_o - sync init - end - process $group_13 - assign \pipe_n_ready_i 1'0 - assign \pipe_n_ready_i \n_ready_i - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \muxid$9 - process $group_14 - assign \muxid$9 2'00 - assign \muxid$9 \pipe_muxid$3 - sync init - end - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \cr_op__insn_type$10 - attribute \enum_base_type "Function" - attribute \enum_value_00000000000 "NONE" - attribute \enum_value_00000000010 "ALU" - attribute \enum_value_00000000100 "LDST" - attribute \enum_value_00000001000 "SHIFT_ROT" - attribute \enum_value_00000010000 "LOGICAL" - attribute \enum_value_00000100000 "BRANCH" - attribute \enum_value_00001000000 "CR" - attribute \enum_value_00010000000 "TRAP" - attribute \enum_value_00100000000 "MUL" - attribute \enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 \cr_op__fn_unit$11 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \cr_op__insn$12 - process $group_15 - assign \cr_op__insn_type$10 7'0000000 - assign \cr_op__fn_unit$11 11'00000000000 - assign \cr_op__insn$12 32'00000000000000000000000000000000 - assign { \cr_op__insn$12 \cr_op__fn_unit$11 \cr_op__insn_type$10 } { \pipe_cr_op__insn$6 \pipe_cr_op__fn_unit$5 \pipe_cr_op__insn_type$4 } - sync init - end - process $group_18 - assign \o 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \o_ok 1'0 - assign { \o_ok \o } { \pipe_o_ok \pipe_o } - sync init - end - process $group_20 - assign \full_cr 32'00000000000000000000000000000000 - assign \full_cr_ok 1'0 - assign { \full_cr_ok \full_cr } { \pipe_full_cr_ok \pipe_full_cr$7 } - sync init - end - process $group_22 - assign \cr_a 4'0000 - assign \cr_a_ok 1'0 - assign { \cr_a_ok \cr_a } { \pipe_cr_a_ok \pipe_cr_a$8 } - sync init - end - connect \muxid 2'00 -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.cr0.src_l" -module \src_l$10 - attribute \src "simple/issuer.py:141" - wire width 1 input 0 \coresync_clk - attribute \src "simple/issuer.py:141" - wire width 1 input 1 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 6 input 2 \s_src - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 6 input 3 \r_src - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire width 6 output 4 \q_src - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire width 6 \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire width 6 \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 6 $1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \Y_WIDTH 6 - connect \A \r_src - connect \Y $1 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 6 $3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $4 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 6 - connect \A \q_int - connect \B $1 - connect \Y $3 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 6 $5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $6 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 6 - connect \A $3 - connect \B \s_src - connect \Y $5 - end - process $group_0 - assign \q_int$next \q_int - assign \q_int$next $5 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \q_int$next 6'000000 - end - sync init - update \q_int 6'000000 - sync posedge \coresync_clk - update \q_int \q_int$next - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 6 $7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $8 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \Y_WIDTH 6 - connect \A \r_src - connect \Y $7 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 6 $9 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $10 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 6 - connect \A \q_int - connect \B $7 - connect \Y $9 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 6 $11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $12 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 6 - connect \A $9 - connect \B \s_src - connect \Y $11 - end - process $group_1 - assign \q_src 6'000000 - assign \q_src $11 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" - wire width 6 \qn_src - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - wire width 6 $13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $14 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \Y_WIDTH 6 - connect \A \q_src - connect \Y $13 - end - process $group_2 - assign \qn_src 6'000000 - assign \qn_src $13 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" - wire width 6 \qlq_src - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - wire width 6 $15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $16 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 6 - connect \A \q_src - connect \B \q_int - connect \Y $15 - end - process $group_3 - assign \qlq_src 6'000000 - assign \qlq_src $15 - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.cr0.opc_l" -module \opc_l$11 - attribute \src "simple/issuer.py:141" - wire width 1 input 0 \coresync_clk - attribute \src "simple/issuer.py:141" - wire width 1 input 1 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 1 input 2 \s_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 1 input 3 \r_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire width 1 output 4 \q_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire width 1 \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire width 1 \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_opc - connect \Y $1 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 1 $3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $4 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B $1 - connect \Y $3 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 1 $5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $6 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $3 - connect \B \s_opc - connect \Y $5 - end - process $group_0 - assign \q_int$next \q_int - assign \q_int$next $5 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \q_int$next 1'0 - end - sync init - update \q_int 1'0 - sync posedge \coresync_clk - update \q_int \q_int$next - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 1 $7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $8 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_opc - connect \Y $7 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 1 $9 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $10 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B $7 - connect \Y $9 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 1 $11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $12 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $9 - connect \B \s_opc - connect \Y $11 - end - process $group_1 - assign \q_opc 1'0 - assign \q_opc $11 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" - wire width 1 \qn_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - wire width 1 $13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $14 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_opc - connect \Y $13 - end - process $group_2 - assign \qn_opc 1'0 - assign \qn_opc $13 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" - wire width 1 \qlq_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - wire width 1 $15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $16 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_opc - connect \B \q_int - connect \Y $15 - end - process $group_3 - assign \qlq_opc 1'0 - assign \qlq_opc $15 - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.cr0.req_l" -module \req_l$12 - attribute \src "simple/issuer.py:141" - wire width 1 input 0 \coresync_clk - attribute \src "simple/issuer.py:141" - wire width 1 input 1 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire width 3 output 2 \q_req - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 3 input 3 \s_req - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 3 input 4 \r_req - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire width 3 \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire width 3 \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 3 $1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A \r_req - connect \Y $1 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 3 $3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $4 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A \q_int - connect \B $1 - connect \Y $3 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 3 $5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $6 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A $3 - connect \B \s_req - connect \Y $5 - end - process $group_0 - assign \q_int$next \q_int - assign \q_int$next $5 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \q_int$next 3'000 - end - sync init - update \q_int 3'000 - sync posedge \coresync_clk - update \q_int \q_int$next - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 3 $7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $8 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A \r_req - connect \Y $7 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 3 $9 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $10 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A \q_int - connect \B $7 - connect \Y $9 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 3 $11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $12 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A $9 - connect \B \s_req - connect \Y $11 - end - process $group_1 - assign \q_req 3'000 - assign \q_req $11 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" - wire width 3 \qn_req - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - wire width 3 $13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $14 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A \q_req - connect \Y $13 - end - process $group_2 - assign \qn_req 3'000 - assign \qn_req $13 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" - wire width 3 \qlq_req - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - wire width 3 $15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $16 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A \q_req - connect \B \q_int - connect \Y $15 - end - process $group_3 - assign \qlq_req 3'000 - assign \qlq_req $15 - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.cr0.rst_l" -module \rst_l$13 - attribute \src "simple/issuer.py:141" - wire width 1 input 0 \coresync_clk - attribute \src "simple/issuer.py:141" - wire width 1 input 1 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 1 input 2 \s_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 1 input 3 \r_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire width 1 \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire width 1 \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_rst - connect \Y $1 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 1 $3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $4 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B $1 - connect \Y $3 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 1 $5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $6 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $3 - connect \B \s_rst - connect \Y $5 - end - process $group_0 - assign \q_int$next \q_int - assign \q_int$next $5 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \q_int$next 1'0 - end - sync init - update \q_int 1'0 - sync posedge \coresync_clk - update \q_int \q_int$next - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire width 1 \q_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 1 $7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $8 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_rst - connect \Y $7 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 1 $9 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $10 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B $7 - connect \Y $9 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 1 $11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $12 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $9 - connect \B \s_rst - connect \Y $11 - end - process $group_1 - assign \q_rst 1'0 - assign \q_rst $11 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" - wire width 1 \qn_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - wire width 1 $13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $14 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_rst - connect \Y $13 - end - process $group_2 - assign \qn_rst 1'0 - assign \qn_rst $13 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" - wire width 1 \qlq_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - wire width 1 $15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $16 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_rst - connect \B \q_int - connect \Y $15 - end - process $group_3 - assign \qlq_rst 1'0 - assign \qlq_rst $15 - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.cr0.rok_l" -module \rok_l$14 - attribute \src "simple/issuer.py:141" - wire width 1 input 0 \coresync_clk - attribute \src "simple/issuer.py:141" - wire width 1 input 1 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire width 1 output 2 \q_rdok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 1 input 3 \s_rdok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 1 input 4 \r_rdok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire width 1 \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire width 1 \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_rdok - connect \Y $1 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 1 $3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $4 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B $1 - connect \Y $3 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 1 $5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $6 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $3 - connect \B \s_rdok - connect \Y $5 - end - process $group_0 - assign \q_int$next \q_int - assign \q_int$next $5 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \q_int$next 1'0 - end - sync init - update \q_int 1'0 - sync posedge \coresync_clk - update \q_int \q_int$next - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 1 $7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $8 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_rdok - connect \Y $7 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 1 $9 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $10 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B $7 - connect \Y $9 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 1 $11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $12 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $9 - connect \B \s_rdok - connect \Y $11 - end - process $group_1 - assign \q_rdok 1'0 - assign \q_rdok $11 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" - wire width 1 \qn_rdok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - wire width 1 $13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $14 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_rdok - connect \Y $13 - end - process $group_2 - assign \qn_rdok 1'0 - assign \qn_rdok $13 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" - wire width 1 \qlq_rdok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - wire width 1 $15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $16 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_rdok - connect \B \q_int - connect \Y $15 - end - process $group_3 - assign \qlq_rdok 1'0 - assign \qlq_rdok $15 - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.cr0.alui_l" -module \alui_l$15 - attribute \src "simple/issuer.py:141" - wire width 1 input 0 \coresync_clk - attribute \src "simple/issuer.py:141" - wire width 1 input 1 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire width 1 output 2 \q_alui - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 1 input 3 \r_alui - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 1 input 4 \s_alui - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire width 1 \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire width 1 \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_alui - connect \Y $1 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 1 $3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $4 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B $1 - connect \Y $3 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 1 $5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $6 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $3 - connect \B \s_alui - connect \Y $5 - end - process $group_0 - assign \q_int$next \q_int - assign \q_int$next $5 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \q_int$next 1'0 - end - sync init - update \q_int 1'0 - sync posedge \coresync_clk - update \q_int \q_int$next - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 1 $7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $8 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_alui - connect \Y $7 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 1 $9 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $10 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B $7 - connect \Y $9 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 1 $11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $12 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $9 - connect \B \s_alui - connect \Y $11 - end - process $group_1 - assign \q_alui 1'0 - assign \q_alui $11 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" - wire width 1 \qn_alui - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - wire width 1 $13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $14 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_alui - connect \Y $13 - end - process $group_2 - assign \qn_alui 1'0 - assign \qn_alui $13 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" - wire width 1 \qlq_alui - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - wire width 1 $15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $16 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_alui - connect \B \q_int - connect \Y $15 - end - process $group_3 - assign \qlq_alui 1'0 - assign \qlq_alui $15 - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.cr0.alu_l" -module \alu_l$16 - attribute \src "simple/issuer.py:141" - wire width 1 input 0 \coresync_clk - attribute \src "simple/issuer.py:141" - wire width 1 input 1 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire width 1 output 2 \q_alu - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 1 input 3 \r_alu - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 1 input 4 \s_alu - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire width 1 \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire width 1 \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_alu - connect \Y $1 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 1 $3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $4 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B $1 - connect \Y $3 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 1 $5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $6 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $3 - connect \B \s_alu - connect \Y $5 - end - process $group_0 - assign \q_int$next \q_int - assign \q_int$next $5 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \q_int$next 1'0 - end - sync init - update \q_int 1'0 - sync posedge \coresync_clk - update \q_int \q_int$next - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 1 $7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $8 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_alu - connect \Y $7 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 1 $9 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $10 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B $7 - connect \Y $9 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 1 $11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $12 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $9 - connect \B \s_alu - connect \Y $11 - end - process $group_1 - assign \q_alu 1'0 - assign \q_alu $11 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" - wire width 1 \qn_alu - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - wire width 1 $13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $14 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_alu - connect \Y $13 - end - process $group_2 - assign \qn_alu 1'0 - assign \qn_alu $13 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" - wire width 1 \qlq_alu - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - wire width 1 $15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $16 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_alu - connect \B \q_int - connect \Y $15 - end - process $group_3 - assign \qlq_alu 1'0 - assign \qlq_alu $15 - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.cr0" -module \cr0 - attribute \src "simple/issuer.py:141" - wire width 1 input 0 \coresync_clk - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 input 1 \oper_i_alu_cr0__insn_type - attribute \enum_base_type "Function" - attribute \enum_value_00000000000 "NONE" - attribute \enum_value_00000000010 "ALU" - attribute \enum_value_00000000100 "LDST" - attribute \enum_value_00000001000 "SHIFT_ROT" - attribute \enum_value_00000010000 "LOGICAL" - attribute \enum_value_00000100000 "BRANCH" - attribute \enum_value_00001000000 "CR" - attribute \enum_value_00010000000 "TRAP" - attribute \enum_value_00100000000 "MUL" - attribute \enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 input 2 \oper_i_alu_cr0__fn_unit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 input 3 \oper_i_alu_cr0__insn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:100" - wire width 1 input 4 \cu_issue_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107" - wire width 1 output 5 \cu_busy_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96" - wire width 6 input 6 \cu_rdmaskn_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 6 output 7 \cu_rd__rel_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 6 input 8 \cu_rd__go_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 64 input 9 \src1_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 64 input 10 \src2_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 32 input 11 \src3_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 4 input 12 \src4_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 4 input 13 \src5_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 4 input 14 \src6_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 15 \o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 3 output 16 \cu_wr__rel_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 3 input 17 \cu_wr__go_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" - wire width 64 output 18 \dest1_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 19 \full_cr_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" - wire width 32 output 20 \dest2_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 21 \cr_a_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" - wire width 4 output 22 \dest3_o - attribute \src "simple/issuer.py:141" - wire width 1 input 23 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" - wire width 1 \alu_cr0_n_valid_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" - wire width 1 \alu_cr0_n_ready_i - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \alu_cr0_cr_op__insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \alu_cr0_cr_op__insn_type$next - attribute \enum_base_type "Function" - attribute \enum_value_00000000000 "NONE" - attribute \enum_value_00000000010 "ALU" - attribute \enum_value_00000000100 "LDST" - attribute \enum_value_00000001000 "SHIFT_ROT" - attribute \enum_value_00000010000 "LOGICAL" - attribute \enum_value_00000100000 "BRANCH" - attribute \enum_value_00001000000 "CR" - attribute \enum_value_00010000000 "TRAP" - attribute \enum_value_00100000000 "MUL" - attribute \enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 \alu_cr0_cr_op__fn_unit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 \alu_cr0_cr_op__fn_unit$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \alu_cr0_cr_op__insn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \alu_cr0_cr_op__insn$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 \alu_cr0_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 32 \alu_cr0_full_cr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 4 \alu_cr0_cr_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \alu_cr0_ra - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \alu_cr0_rb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 32 \alu_cr0_full_cr$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 4 \alu_cr0_cr_a$2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 4 \alu_cr0_cr_b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 4 \alu_cr0_cr_c - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" - wire width 1 \alu_cr0_p_valid_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" - wire width 1 \alu_cr0_p_ready_o - cell \alu_cr0 \alu_cr0 - connect \coresync_clk \coresync_clk - connect \o_ok \o_ok - connect \full_cr_ok \full_cr_ok - connect \cr_a_ok \cr_a_ok - connect \coresync_rst \coresync_rst - connect \n_valid_o \alu_cr0_n_valid_o - connect \n_ready_i \alu_cr0_n_ready_i - connect \cr_op__insn_type \alu_cr0_cr_op__insn_type - connect \cr_op__fn_unit \alu_cr0_cr_op__fn_unit - connect \cr_op__insn \alu_cr0_cr_op__insn - connect \o \alu_cr0_o - connect \full_cr \alu_cr0_full_cr - connect \cr_a \alu_cr0_cr_a - connect \ra \alu_cr0_ra - connect \rb \alu_cr0_rb - connect \full_cr$1 \alu_cr0_full_cr$1 - connect \cr_a$2 \alu_cr0_cr_a$2 - connect \cr_b \alu_cr0_cr_b - connect \cr_c \alu_cr0_cr_c - connect \p_valid_i \alu_cr0_p_valid_i - connect \p_ready_o \alu_cr0_p_ready_o - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 6 \src_l_s_src - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 6 \src_l_s_src$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 6 \src_l_r_src - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 6 \src_l_r_src$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire width 6 \src_l_q_src - cell \src_l$10 \src_l - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \s_src \src_l_s_src - connect \r_src \src_l_r_src - connect \q_src \src_l_q_src - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 1 \opc_l_s_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 1 \opc_l_s_opc$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 1 \opc_l_r_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 1 \opc_l_r_opc$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire width 1 \opc_l_q_opc - cell \opc_l$11 \opc_l - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \s_opc \opc_l_s_opc - connect \r_opc \opc_l_r_opc - connect \q_opc \opc_l_q_opc - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire width 3 \req_l_q_req - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 3 \req_l_s_req - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 3 \req_l_s_req$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 3 \req_l_r_req - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 3 \req_l_r_req$next - cell \req_l$12 \req_l - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \q_req \req_l_q_req - connect \s_req \req_l_s_req - connect \r_req \req_l_r_req - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 1 \rst_l_s_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 1 \rst_l_s_rst$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 1 \rst_l_r_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 1 \rst_l_r_rst$next - cell \rst_l$13 \rst_l - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \s_rst \rst_l_s_rst - connect \r_rst \rst_l_r_rst - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire width 1 \rok_l_q_rdok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 1 \rok_l_s_rdok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 1 \rok_l_s_rdok$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 1 \rok_l_r_rdok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 1 \rok_l_r_rdok$next - cell \rok_l$14 \rok_l - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \q_rdok \rok_l_q_rdok - connect \s_rdok \rok_l_s_rdok - connect \r_rdok \rok_l_r_rdok - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire width 1 \alui_l_q_alui - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 1 \alui_l_r_alui - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 1 \alui_l_r_alui$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 1 \alui_l_s_alui - cell \alui_l$15 \alui_l - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \q_alui \alui_l_q_alui - connect \r_alui \alui_l_r_alui - connect \s_alui \alui_l_s_alui - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire width 1 \alu_l_q_alu - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 1 \alu_l_r_alu - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 1 \alu_l_r_alu$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 1 \alu_l_s_alu - cell \alu_l$16 \alu_l - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \q_alu \alu_l_q_alu - connect \r_alu \alu_l_r_alu - connect \s_alu \alu_l_s_alu - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:187" - wire width 1 \all_rd - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:188" - wire width 1 $3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:188" - cell $and $4 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cu_busy_o - connect \B \rok_l_q_rdok - connect \Y $3 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - wire width 1 $5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - wire width 6 $6 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - cell $not $7 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \Y_WIDTH 6 - connect \A \cu_rd__rel_o - connect \Y $6 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - wire width 6 $8 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - cell $or $9 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 6 - connect \A $6 - connect \B \cu_rd__go_i - connect \Y $8 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - cell $reduce_and $10 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \Y_WIDTH 1 - connect \A $8 - connect \Y $5 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - wire width 1 $11 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - cell $and $12 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $3 - connect \B $5 - connect \Y $11 - end - process $group_0 - assign \all_rd 1'0 - assign \all_rd $11 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire width 1 \all_rd_dly - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire width 1 \all_rd_dly$next - process $group_1 - assign \all_rd_dly$next \all_rd_dly - assign \all_rd_dly$next \all_rd - sync init - update \all_rd_dly 1'0 - sync posedge \coresync_clk - update \all_rd_dly \all_rd_dly$next - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" - wire width 1 \all_rd_rise - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - wire width 1 $13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $not $14 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \all_rd_dly - connect \Y $13 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - wire width 1 $15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $and $16 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \all_rd - connect \B $13 - connect \Y $15 - end - process $group_2 - assign \all_rd_rise 1'0 - assign \all_rd_rise $15 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:192" - wire width 1 \all_rd_pulse - process $group_3 - assign \all_rd_pulse 1'0 - assign \all_rd_pulse \all_rd_rise - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:196" - wire width 1 \alu_done - process $group_4 - assign \alu_done 1'0 - assign \alu_done \alu_cr0_n_valid_o - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire width 1 \alu_done_dly - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire width 1 \alu_done_dly$next - process $group_5 - assign \alu_done_dly$next \alu_done_dly - assign \alu_done_dly$next \alu_done - sync init - update \alu_done_dly 1'0 - sync posedge \coresync_clk - update \alu_done_dly \alu_done_dly$next - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" - wire width 1 \alu_done_rise - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - wire width 1 $17 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $not $18 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \alu_done_dly - connect \Y $17 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - wire width 1 $19 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $and $20 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \alu_done - connect \B $17 - connect \Y $19 - end - process $group_6 - assign \alu_done_rise 1'0 - assign \alu_done_rise $19 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:197" - wire width 1 \alu_pulse - process $group_7 - assign \alu_pulse 1'0 - assign \alu_pulse \alu_done_rise - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:198" - wire width 3 \alu_pulsem - process $group_8 - assign \alu_pulsem 3'000 - assign \alu_pulsem { \alu_pulse \alu_pulse \alu_pulse } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:204" - wire width 3 \prev_wr_go - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:204" - wire width 3 \prev_wr_go$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:206" - wire width 3 $21 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:206" - cell $and $22 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A \cu_wr__go_i - connect \B { \cu_busy_o \cu_busy_o \cu_busy_o } - connect \Y $21 - end - process $group_9 - assign \prev_wr_go$next \prev_wr_go - assign \prev_wr_go$next $21 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \prev_wr_go$next 3'000 - end - sync init - update \prev_wr_go 3'000 - sync posedge \coresync_clk - update \prev_wr_go \prev_wr_go$next - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:108" - wire width 1 \cu_done_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - wire width 1 $23 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - wire width 1 $24 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - wire width 3 $25 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:97" - wire width 3 \cu_wrmask_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $not $26 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A \cu_wrmask_o - connect \Y $25 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - wire width 3 $27 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $and $28 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A \cu_wr__rel_o - connect \B $25 - connect \Y $27 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $reduce_bool $29 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A $27 - connect \Y $24 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $not $30 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $24 - connect \Y $23 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - wire width 1 $31 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $and $32 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cu_busy_o - connect \B $23 - connect \Y $31 - end - process $group_10 - assign \cu_done_o 1'0 - assign \cu_done_o $31 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:211" - wire width 1 \wr_any - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" - wire width 1 $33 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" - cell $reduce_bool $34 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \cu_wr__go_i - connect \Y $33 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" - wire width 1 $35 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" - cell $reduce_bool $36 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \prev_wr_go - connect \Y $35 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" - wire width 1 $37 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" - cell $or $38 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $33 - connect \B $35 - connect \Y $37 - end - process $group_11 - assign \wr_any 1'0 - assign \wr_any $37 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:212" - wire width 1 \req_done - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" - wire width 1 $39 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" - cell $not $40 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \alu_cr0_n_ready_i - connect \Y $39 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" - wire width 1 $41 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" - cell $and $42 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_any - connect \B $39 - connect \Y $41 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" - wire width 3 $43 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" - cell $and $44 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A \req_l_q_req - connect \B \cu_wrmask_o - connect \Y $43 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" - wire width 1 $45 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" - cell $eq $46 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $43 - connect \B 1'0 - connect \Y $45 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" - wire width 1 $47 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" - cell $and $48 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $41 - connect \B $45 - connect \Y $47 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - wire width 1 $49 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - cell $eq $50 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cu_wrmask_o - connect \B 1'0 - connect \Y $49 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - wire width 1 $51 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - cell $and $52 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $49 - connect \B \alu_cr0_n_ready_i - connect \Y $51 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - wire width 1 $53 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - cell $and $54 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $51 - connect \B \alu_cr0_n_valid_o - connect \Y $53 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - wire width 1 $55 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - cell $and $56 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $53 - connect \B \cu_busy_o - connect \Y $55 - end - process $group_12 - assign \req_done 1'0 - assign \req_done $47 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - switch { $55 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - case 1'1 - assign \req_done 1'1 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:226" - wire width 1 \reset - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:104" - wire width 1 \cu_go_die_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:230" - wire width 1 $57 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:230" - cell $or $58 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \req_done - connect \B \cu_go_die_i - connect \Y $57 - end - process $group_13 - assign \reset 1'0 - assign \reset $57 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:227" - wire width 1 \rst_r - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:231" - wire width 1 $59 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:231" - cell $or $60 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cu_issue_i - connect \B \cu_go_die_i - connect \Y $59 - end - process $group_14 - assign \rst_r 1'0 - assign \rst_r $59 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:228" - wire width 3 \reset_w - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:232" - wire width 3 $61 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:232" - cell $or $62 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A \cu_wr__go_i - connect \B { \cu_go_die_i \cu_go_die_i \cu_go_die_i } - connect \Y $61 - end - process $group_15 - assign \reset_w 3'000 - assign \reset_w $61 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:229" - wire width 6 \reset_r - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:233" - wire width 6 $63 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:233" - cell $or $64 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 6 - connect \A \cu_rd__go_i - connect \B { \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i } - connect \Y $63 - end - process $group_16 - assign \reset_r 6'000000 - assign \reset_r $63 - sync init - end - process $group_17 - assign \rok_l_s_rdok$next \rok_l_s_rdok - assign \rok_l_s_rdok$next \cu_issue_i - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \rok_l_s_rdok$next 1'0 - end - sync init - update \rok_l_s_rdok 1'0 - sync posedge \coresync_clk - update \rok_l_s_rdok \rok_l_s_rdok$next - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:237" - wire width 1 $65 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:237" - cell $and $66 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \alu_cr0_n_valid_o - connect \B \cu_busy_o - connect \Y $65 - end - process $group_18 - assign \rok_l_r_rdok$next \rok_l_r_rdok - assign \rok_l_r_rdok$next $65 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \rok_l_r_rdok$next 1'1 - end - sync init - update \rok_l_r_rdok 1'1 - sync posedge \coresync_clk - update \rok_l_r_rdok \rok_l_r_rdok$next - end - process $group_19 - assign \rst_l_s_rst$next \rst_l_s_rst - assign \rst_l_s_rst$next \all_rd - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \rst_l_s_rst$next 1'0 - end - sync init - update \rst_l_s_rst 1'0 - sync posedge \coresync_clk - update \rst_l_s_rst \rst_l_s_rst$next - end - process $group_20 - assign \rst_l_r_rst$next \rst_l_r_rst - assign \rst_l_r_rst$next \rst_r - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \rst_l_r_rst$next 1'1 - end - sync init - update \rst_l_r_rst 1'1 - sync posedge \coresync_clk - update \rst_l_r_rst \rst_l_r_rst$next - end - process $group_21 - assign \opc_l_s_opc$next \opc_l_s_opc - assign \opc_l_s_opc$next \cu_issue_i - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \opc_l_s_opc$next 1'0 - end - sync init - update \opc_l_s_opc 1'0 - sync posedge \coresync_clk - update \opc_l_s_opc \opc_l_s_opc$next - end - process $group_22 - assign \opc_l_r_opc$next \opc_l_r_opc - assign \opc_l_r_opc$next \req_done - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \opc_l_r_opc$next 1'1 - end - sync init - update \opc_l_r_opc 1'1 - sync posedge \coresync_clk - update \opc_l_r_opc \opc_l_r_opc$next - end - process $group_23 - assign \src_l_s_src$next \src_l_s_src - assign \src_l_s_src$next { \cu_issue_i \cu_issue_i \cu_issue_i \cu_issue_i \cu_issue_i \cu_issue_i } - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \src_l_s_src$next 6'000000 - end - sync init - update \src_l_s_src 6'000000 - sync posedge \coresync_clk - update \src_l_s_src \src_l_s_src$next - end - process $group_24 - assign \src_l_r_src$next \src_l_r_src - assign \src_l_r_src$next \reset_r - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \src_l_r_src$next 6'111111 - end - sync init - update \src_l_r_src 6'111111 - sync posedge \coresync_clk - update \src_l_r_src \src_l_r_src$next - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:252" - wire width 3 $67 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:252" - cell $and $68 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A \alu_pulsem - connect \B \cu_wrmask_o - connect \Y $67 - end - process $group_25 - assign \req_l_s_req$next \req_l_s_req - assign \req_l_s_req$next $67 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \req_l_s_req$next 3'000 - end - sync init - update \req_l_s_req 3'000 - sync posedge \coresync_clk - update \req_l_s_req \req_l_s_req$next - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:253" - wire width 3 $69 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:253" - cell $or $70 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A \reset_w - connect \B \prev_wr_go - connect \Y $69 - end - process $group_26 - assign \req_l_r_req$next \req_l_r_req - assign \req_l_r_req$next $69 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \req_l_r_req$next 3'111 - end - sync init - update \req_l_r_req 3'111 - sync posedge \coresync_clk - update \req_l_r_req \req_l_r_req$next - end - process $group_27 - assign \alu_cr0_cr_op__insn_type$next \alu_cr0_cr_op__insn_type - assign \alu_cr0_cr_op__fn_unit$next \alu_cr0_cr_op__fn_unit - assign \alu_cr0_cr_op__insn$next \alu_cr0_cr_op__insn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:257" - switch { \cu_issue_i } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:257" - case 1'1 - assign { \alu_cr0_cr_op__insn$next \alu_cr0_cr_op__fn_unit$next \alu_cr0_cr_op__insn_type$next } { \oper_i_alu_cr0__insn \oper_i_alu_cr0__fn_unit \oper_i_alu_cr0__insn_type } - end - sync init - update \alu_cr0_cr_op__insn_type 7'0000000 - update \alu_cr0_cr_op__fn_unit 11'00000000000 - update \alu_cr0_cr_op__insn 32'00000000000000000000000000000000 - sync posedge \coresync_clk - update \alu_cr0_cr_op__insn_type \alu_cr0_cr_op__insn_type$next - update \alu_cr0_cr_op__fn_unit \alu_cr0_cr_op__fn_unit$next - update \alu_cr0_cr_op__insn \alu_cr0_cr_op__insn$next - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" - wire width 64 \data_r0__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" - wire width 64 \data_r0__o$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" - wire width 1 \data_r0__o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" - wire width 1 \data_r0__o_ok$next - process $group_30 - assign \data_r0__o$next \data_r0__o - assign \data_r0__o_ok$next \data_r0__o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" - switch { \alu_pulse } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" - case 1'1 - assign { \data_r0__o_ok$next \data_r0__o$next } { \o_ok \alu_cr0_o } - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" - switch { \cu_issue_i } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" - case 1'1 - assign { \data_r0__o_ok$next \data_r0__o$next } 65'00000000000000000000000000000000000000000000000000000000000000000 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \data_r0__o_ok$next 1'0 - end - sync init - update \data_r0__o 64'0000000000000000000000000000000000000000000000000000000000000000 - update \data_r0__o_ok 1'0 - sync posedge \coresync_clk - update \data_r0__o \data_r0__o$next - update \data_r0__o_ok \data_r0__o_ok$next - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" - wire width 32 \data_r1__full_cr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" - wire width 32 \data_r1__full_cr$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" - wire width 1 \data_r1__full_cr_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" - wire width 1 \data_r1__full_cr_ok$next - process $group_32 - assign \data_r1__full_cr$next \data_r1__full_cr - assign \data_r1__full_cr_ok$next \data_r1__full_cr_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" - switch { \alu_pulse } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" - case 1'1 - assign { \data_r1__full_cr_ok$next \data_r1__full_cr$next } { \full_cr_ok \alu_cr0_full_cr } - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" - switch { \cu_issue_i } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" - case 1'1 - assign { \data_r1__full_cr_ok$next \data_r1__full_cr$next } 33'000000000000000000000000000000000 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \data_r1__full_cr_ok$next 1'0 - end - sync init - update \data_r1__full_cr 32'00000000000000000000000000000000 - update \data_r1__full_cr_ok 1'0 - sync posedge \coresync_clk - update \data_r1__full_cr \data_r1__full_cr$next - update \data_r1__full_cr_ok \data_r1__full_cr_ok$next - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" - wire width 4 \data_r2__cr_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" - wire width 4 \data_r2__cr_a$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" - wire width 1 \data_r2__cr_a_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" - wire width 1 \data_r2__cr_a_ok$next - process $group_34 - assign \data_r2__cr_a$next \data_r2__cr_a - assign \data_r2__cr_a_ok$next \data_r2__cr_a_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" - switch { \alu_pulse } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" - case 1'1 - assign { \data_r2__cr_a_ok$next \data_r2__cr_a$next } { \cr_a_ok \alu_cr0_cr_a } - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" - switch { \cu_issue_i } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" - case 1'1 - assign { \data_r2__cr_a_ok$next \data_r2__cr_a$next } 5'00000 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \data_r2__cr_a_ok$next 1'0 - end - sync init - update \data_r2__cr_a 4'0000 - update \data_r2__cr_a_ok 1'0 - sync posedge \coresync_clk - update \data_r2__cr_a \data_r2__cr_a$next - update \data_r2__cr_a_ok \data_r2__cr_a_ok$next - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" - wire width 1 $71 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" - cell $and $72 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \o_ok - connect \B \cu_busy_o - connect \Y $71 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" - wire width 1 $73 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" - cell $and $74 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \full_cr_ok - connect \B \cu_busy_o - connect \Y $73 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" - wire width 1 $75 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" - cell $and $76 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cr_a_ok - connect \B \cu_busy_o - connect \Y $75 - end - process $group_36 - assign \cu_wrmask_o 3'000 - assign \cu_wrmask_o { $75 $73 $71 } - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" - wire width 64 \src_r0 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" - wire width 64 \src_r0$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - wire width 64 $77 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - cell $mux $78 - parameter \WIDTH 64 - connect \A \src_r0 - connect \B \src1_i - connect \S \src_l_q_src [0] - connect \Y $77 - end - process $group_37 - assign \alu_cr0_ra 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \alu_cr0_ra $77 - sync init - end - process $group_38 - assign \src_r0$next \src_r0 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" - switch { \src_l_q_src [0] } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" - case 1'1 - assign \src_r0$next \src1_i - end - sync init - update \src_r0 64'0000000000000000000000000000000000000000000000000000000000000000 - sync posedge \coresync_clk - update \src_r0 \src_r0$next - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" - wire width 64 \src_r1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" - wire width 64 \src_r1$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - wire width 64 $79 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - cell $mux $80 - parameter \WIDTH 64 - connect \A \src_r1 - connect \B \src2_i - connect \S \src_l_q_src [1] - connect \Y $79 - end - process $group_39 - assign \alu_cr0_rb 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \alu_cr0_rb $79 - sync init - end - process $group_40 - assign \src_r1$next \src_r1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" - switch { \src_l_q_src [1] } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" - case 1'1 - assign \src_r1$next \src2_i - end - sync init - update \src_r1 64'0000000000000000000000000000000000000000000000000000000000000000 - sync posedge \coresync_clk - update \src_r1 \src_r1$next - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" - wire width 32 \src_r2 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" - wire width 32 \src_r2$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - wire width 32 $81 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - cell $mux $82 - parameter \WIDTH 32 - connect \A \src_r2 - connect \B \src3_i - connect \S \src_l_q_src [2] - connect \Y $81 - end - process $group_41 - assign \alu_cr0_full_cr$1 32'00000000000000000000000000000000 - assign \alu_cr0_full_cr$1 $81 - sync init - end - process $group_42 - assign \src_r2$next \src_r2 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" - switch { \src_l_q_src [2] } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" - case 1'1 - assign \src_r2$next \src3_i - end - sync init - update \src_r2 32'00000000000000000000000000000000 - sync posedge \coresync_clk - update \src_r2 \src_r2$next - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" - wire width 4 \src_r3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" - wire width 4 \src_r3$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - wire width 4 $83 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - cell $mux $84 - parameter \WIDTH 4 - connect \A \src_r3 - connect \B \src4_i - connect \S \src_l_q_src [3] - connect \Y $83 - end - process $group_43 - assign \alu_cr0_cr_a$2 4'0000 - assign \alu_cr0_cr_a$2 $83 - sync init - end - process $group_44 - assign \src_r3$next \src_r3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" - switch { \src_l_q_src [3] } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" - case 1'1 - assign \src_r3$next \src4_i - end - sync init - update \src_r3 4'0000 - sync posedge \coresync_clk - update \src_r3 \src_r3$next - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" - wire width 4 \src_r4 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" - wire width 4 \src_r4$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - wire width 4 $85 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - cell $mux $86 - parameter \WIDTH 4 - connect \A \src_r4 - connect \B \src5_i - connect \S \src_l_q_src [4] - connect \Y $85 - end - process $group_45 - assign \alu_cr0_cr_b 4'0000 - assign \alu_cr0_cr_b $85 - sync init - end - process $group_46 - assign \src_r4$next \src_r4 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" - switch { \src_l_q_src [4] } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" - case 1'1 - assign \src_r4$next \src5_i - end - sync init - update \src_r4 4'0000 - sync posedge \coresync_clk - update \src_r4 \src_r4$next - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" - wire width 4 \src_r5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" - wire width 4 \src_r5$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - wire width 4 $87 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - cell $mux $88 - parameter \WIDTH 4 - connect \A \src_r5 - connect \B \src6_i - connect \S \src_l_q_src [5] - connect \Y $87 - end - process $group_47 - assign \alu_cr0_cr_c 4'0000 - assign \alu_cr0_cr_c $87 - sync init - end - process $group_48 - assign \src_r5$next \src_r5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" - switch { \src_l_q_src [5] } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" - case 1'1 - assign \src_r5$next \src6_i - end - sync init - update \src_r5 4'0000 - sync posedge \coresync_clk - update \src_r5 \src_r5$next - end - process $group_49 - assign \alu_cr0_p_valid_i 1'0 - assign \alu_cr0_p_valid_i \alui_l_q_alui - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:327" - wire width 1 $89 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:327" - cell $and $90 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \alu_cr0_p_ready_o - connect \B \alui_l_q_alui - connect \Y $89 - end - process $group_50 - assign \alui_l_r_alui$next \alui_l_r_alui - assign \alui_l_r_alui$next $89 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \alui_l_r_alui$next 1'1 - end - sync init - update \alui_l_r_alui 1'1 - sync posedge \coresync_clk - update \alui_l_r_alui \alui_l_r_alui$next - end - process $group_51 - assign \alui_l_s_alui 1'0 - assign \alui_l_s_alui \all_rd_pulse - sync init - end - process $group_52 - assign \alu_cr0_n_ready_i 1'0 - assign \alu_cr0_n_ready_i \alu_l_q_alu - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:334" - wire width 1 $91 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:334" - cell $and $92 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \alu_cr0_n_valid_o - connect \B \alu_l_q_alu - connect \Y $91 - end - process $group_53 - assign \alu_l_r_alu$next \alu_l_r_alu - assign \alu_l_r_alu$next $91 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \alu_l_r_alu$next 1'1 - end - sync init - update \alu_l_r_alu 1'1 - sync posedge \coresync_clk - update \alu_l_r_alu \alu_l_r_alu$next - end - process $group_54 - assign \alu_l_s_alu 1'0 - assign \alu_l_s_alu \all_rd_pulse - sync init - end - process $group_55 - assign \cu_busy_o 1'0 - assign \cu_busy_o \opc_l_q_opc - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - wire width 6 $93 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - cell $and $94 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 6 - connect \A \src_l_q_src - connect \B { \cu_busy_o \cu_busy_o \cu_busy_o \cu_busy_o \cu_busy_o \cu_busy_o } - connect \Y $93 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - wire width 6 $95 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - cell $and $96 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 6 - connect \A $93 - connect \B { 1'1 1'1 1'1 1'1 1'1 1'1 } - connect \Y $95 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - wire width 6 $97 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - cell $not $98 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \Y_WIDTH 6 - connect \A \cu_rdmaskn_i - connect \Y $97 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - wire width 6 $99 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - cell $and $100 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 6 - connect \A $95 - connect \B $97 - connect \Y $99 - end - process $group_56 - assign \cu_rd__rel_o 6'000000 - assign \cu_rd__rel_o $99 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:102" - wire width 1 \cu_shadown_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" - wire width 1 $101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" - cell $and $102 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cu_busy_o - connect \B \cu_shadown_i - connect \Y $101 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" - wire width 1 $103 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" - cell $and $104 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cu_busy_o - connect \B \cu_shadown_i - connect \Y $103 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" - wire width 1 $105 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" - cell $and $106 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cu_busy_o - connect \B \cu_shadown_i - connect \Y $105 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351" - wire width 3 $107 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351" - cell $and $108 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A \req_l_q_req - connect \B { $101 $103 $105 } - connect \Y $107 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351" - wire width 3 $109 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351" - cell $and $110 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A $107 - connect \B \cu_wrmask_o - connect \Y $109 - end - process $group_57 - assign \cu_wr__rel_o 3'000 - assign \cu_wr__rel_o $109 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - wire width 1 $111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - cell $and $112 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cu_wr__go_i [0] - connect \B \cu_busy_o - connect \Y $111 - end - process $group_58 - assign \dest1_o 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - switch { $111 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - case 1'1 - assign \dest1_o { \data_r0__o_ok \data_r0__o } [63:0] - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - wire width 1 $113 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - cell $and $114 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cu_wr__go_i [1] - connect \B \cu_busy_o - connect \Y $113 - end - process $group_59 - assign \dest2_o 32'00000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - switch { $113 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - case 1'1 - assign \dest2_o { \data_r1__full_cr_ok \data_r1__full_cr } [31:0] - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - wire width 1 $115 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - cell $and $116 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cu_wr__go_i [2] - connect \B \cu_busy_o - connect \Y $115 - end - process $group_60 - assign \dest3_o 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - switch { $115 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - case 1'1 - assign \dest3_o { \data_r2__cr_a_ok \data_r2__cr_a } [3:0] - end - sync init - end - connect \cu_go_die_i 1'0 - connect \cu_shadown_i 1'1 -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.branch0.alu_branch0.p" -module \p$17 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" - wire width 1 input 0 \p_valid_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" - wire width 1 input 1 \p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:158" - wire width 1 \trigger - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" - cell $and $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \p_valid_i - connect \B \p_ready_o - connect \Y $1 - end - process $group_0 - assign \trigger 1'0 - assign \trigger $1 - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.branch0.alu_branch0.n" -module \n$18 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" - wire width 1 input 0 \n_valid_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" - wire width 1 input 1 \n_ready_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:251" - wire width 1 \trigger - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" - cell $and $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \n_ready_i - connect \B \n_valid_o - connect \Y $1 - end - process $group_0 - assign \trigger 1'0 - assign \trigger $1 - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.branch0.alu_branch0.pipe.p" -module \p$20 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" - wire width 1 input 0 \p_valid_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" - wire width 1 input 1 \p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:158" - wire width 1 \trigger - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" - cell $and $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \p_valid_i - connect \B \p_ready_o - connect \Y $1 - end - process $group_0 - assign \trigger 1'0 - assign \trigger $1 - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.branch0.alu_branch0.pipe.n" -module \n$21 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" - wire width 1 input 0 \n_valid_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" - wire width 1 input 1 \n_ready_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:251" - wire width 1 \trigger - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" - cell $and $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \n_ready_i - connect \B \n_valid_o - connect \Y $1 - end - process $group_0 - assign \trigger 1'0 - assign \trigger $1 - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.branch0.alu_branch0.pipe.main" -module \main$22 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 input 0 \muxid - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 input 1 \br_op__cia - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 input 2 \br_op__insn_type - attribute \enum_base_type "Function" - attribute \enum_value_00000000000 "NONE" - attribute \enum_value_00000000010 "ALU" - attribute \enum_value_00000000100 "LDST" - attribute \enum_value_00000001000 "SHIFT_ROT" - attribute \enum_value_00000010000 "LOGICAL" - attribute \enum_value_00000100000 "BRANCH" - attribute \enum_value_00001000000 "CR" - attribute \enum_value_00010000000 "TRAP" - attribute \enum_value_00100000000 "MUL" - attribute \enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 input 3 \br_op__fn_unit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 input 4 \br_op__insn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 input 5 \br_op__imm_data__data - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 6 \br_op__imm_data__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 7 \br_op__lk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 8 \br_op__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 9 \fast1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 10 \fast2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 4 input 11 \cr_a - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 output 12 \muxid$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 output 13 \br_op__cia$2 - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 output 14 \br_op__insn_type$3 - attribute \enum_base_type "Function" - attribute \enum_value_00000000000 "NONE" - attribute \enum_value_00000000010 "ALU" - attribute \enum_value_00000000100 "LDST" - attribute \enum_value_00000001000 "SHIFT_ROT" - attribute \enum_value_00000010000 "LOGICAL" - attribute \enum_value_00000100000 "BRANCH" - attribute \enum_value_00001000000 "CR" - attribute \enum_value_00010000000 "TRAP" - attribute \enum_value_00100000000 "MUL" - attribute \enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 output 15 \br_op__fn_unit$4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 output 16 \br_op__insn$5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 output 17 \br_op__imm_data__data$6 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 18 \br_op__imm_data__ok$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 19 \br_op__lk$8 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 20 \br_op__is_32bit$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 output 21 \fast1$10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 22 \fast1_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 output 23 \fast2$11 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 24 \fast2_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 output 25 \nia - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 26 \nia_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:88" - wire width 64 \br_addr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:92" - wire width 1 $12 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:92" - cell $eq $13 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A \br_op__insn_type - connect \B 7'0001000 - connect \Y $12 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:92" - wire width 1 $14 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:92" - cell $or $15 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A { \br_op__insn [1] } - connect \B $12 - connect \Y $14 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:87" - wire width 64 \br_imm_addr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:95" - wire width 65 $16 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:95" - wire width 65 $17 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:95" - cell $add $18 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \B_SIGNED 0 - parameter \B_WIDTH 64 - parameter \Y_WIDTH 65 - connect \A \br_imm_addr - connect \B \br_op__cia - connect \Y $17 - end - connect $16 $17 - process $group_0 - assign \br_addr 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:92" - switch { $14 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:92" - case 1'1 - assign \br_addr \br_imm_addr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:94" - case - assign \br_addr $16 [63:0] - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:105" - wire width 5 \bo - process $group_1 - assign \bo 5'00000 - assign \bo { \br_op__insn [25] \br_op__insn [24] \br_op__insn [23] \br_op__insn [22] \br_op__insn [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:109" - wire width 2 \bi - process $group_2 - assign \bi 2'00 - assign \bi { \br_op__insn [17] \br_op__insn [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:110" - wire width 1 \cr_bit - process $group_3 - assign \cr_bit 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:112" - switch \bi - case 2'00 - assign \cr_bit \cr_a [3] - case 2'01 - assign \cr_bit \cr_a [2] - case 2'10 - assign \cr_bit \cr_a [1] - case 2'-- - assign \cr_bit \cr_a [0] - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:115" - wire width 1 \ctr_write - process $group_4 - assign \ctr_write 1'0 - assign \ctr_write 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:120" - switch { \bo [2] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:120" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:122" - case - assign \ctr_write 1'1 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:119" - wire width 1 \bc_taken - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:121" - wire width 1 $19 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:121" - cell $eq $20 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cr_bit - connect \B \bo [3] - connect \Y $19 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:121" - wire width 1 $21 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:121" - cell $or $22 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $19 - connect \B \bo [4] - connect \Y $21 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:137" - wire width 1 $23 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:137" - cell $eq $24 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \bo [4:3] - connect \B 1'0 - connect \Y $23 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:139" - wire width 1 $25 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:139" - cell $eq $26 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \bo [4:3] - connect \B 1'1 - connect \Y $25 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:141" - wire width 1 $27 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:141" - cell $eq $28 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \bo [4] - connect \B 1'1 - connect \Y $27 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:135" - wire width 1 \ctr_zero_bo1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:138" - wire width 1 $29 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:138" - cell $not $30 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cr_bit - connect \Y $29 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:138" - wire width 1 $31 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:138" - cell $and $32 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \ctr_zero_bo1 - connect \B $29 - connect \Y $31 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:140" - wire width 1 $33 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:140" - cell $and $34 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \ctr_zero_bo1 - connect \B \cr_bit - connect \Y $33 - end - process $group_5 - assign \bc_taken 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:120" - switch { \bo [2] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:120" - case 1'1 - assign \bc_taken $21 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:122" - case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:137" - switch { $27 $25 $23 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:137" - case 3'--1 - assign \bc_taken $31 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:139" - case 3'-1- - assign \bc_taken $33 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:141" - case 3'1-- - assign \bc_taken \ctr_zero_bo1 - end - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:124" - wire width 64 \ctr_n - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:125" - wire width 65 $35 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:125" - wire width 65 $36 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:125" - cell $sub $37 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 65 - connect \A \fast1 - connect \B 1'1 - connect \Y $36 - end - connect $35 $36 - process $group_6 - assign \ctr_n 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:120" - switch { \bo [2] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:120" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:122" - case - assign \ctr_n $35 [63:0] - end - sync init - end - process $group_7 - assign \fast1$10 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:120" - switch { \bo [2] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:120" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:122" - case - assign \fast1$10 \ctr_n - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:129" - wire width 64 \ctr_m - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:265" - wire width 64 $38 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:265" - cell $pos $39 - parameter \A_SIGNED 0 - parameter \A_WIDTH 32 - parameter \Y_WIDTH 64 - connect \A \fast1 [31:0] - connect \Y $38 - end - process $group_8 - assign \ctr_m 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:120" - switch { \bo [2] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:120" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:122" - case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:130" - switch { \br_op__is_32bit } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:130" - case 1'1 - assign \ctr_m $38 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:132" - case - assign \ctr_m \fast1 - end - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:136" - wire width 1 $40 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:136" - cell $reduce_or $41 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \Y_WIDTH 1 - connect \A \ctr_n - connect \Y $40 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:136" - wire width 1 $42 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:136" - cell $xor $43 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \bo [1] - connect \B $40 - connect \Y $42 - end - process $group_9 - assign \ctr_zero_bo1 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:120" - switch { \bo [2] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:120" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:122" - case - assign \ctr_zero_bo1 $42 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:160" - wire width 1 $44 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:160" - cell $not $45 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A { \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] \br_op__insn [1] } [5] - connect \Y $44 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:160" - wire width 1 $46 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:160" - cell $and $47 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A { \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] \br_op__insn [1] } [9] - connect \B $44 - connect \Y $46 - end - process $group_10 - assign \br_imm_addr 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:145" - switch \br_op__insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:147" - attribute \nmigen.decoding "OP_B/6" - case 7'0000110 - assign \br_imm_addr { { { { \br_op__insn [25] \br_op__insn [24] \br_op__insn [23] \br_op__insn [22] \br_op__insn [21] \br_op__insn [20] \br_op__insn [19] \br_op__insn [18] \br_op__insn [17] \br_op__insn [16] \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [23] { \br_op__insn [25] \br_op__insn [24] \br_op__insn [23] \br_op__insn [22] \br_op__insn [21] \br_op__insn [20] \br_op__insn [19] \br_op__insn [18] \br_op__insn [17] \br_op__insn [16] \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [23] { \br_op__insn [25] \br_op__insn [24] \br_op__insn [23] \br_op__insn [22] \br_op__insn [21] \br_op__insn [20] \br_op__insn [19] \br_op__insn [18] \br_op__insn [17] \br_op__insn [16] \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [23] { \br_op__insn [25] \br_op__insn [24] \br_op__insn [23] \br_op__insn [22] \br_op__insn [21] \br_op__insn [20] \br_op__insn [19] \br_op__insn [18] \br_op__insn [17] \br_op__insn [16] \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [23] { \br_op__insn [25] \br_op__insn [24] \br_op__insn [23] \br_op__insn [22] \br_op__insn [21] \br_op__insn [20] \br_op__insn [19] \br_op__insn [18] \br_op__insn [17] \br_op__insn [16] \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [23] { \br_op__insn [25] \br_op__insn [24] \br_op__insn [23] \br_op__insn [22] \br_op__insn [21] \br_op__insn [20] \br_op__insn [19] \br_op__insn [18] \br_op__insn [17] \br_op__insn [16] \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [23] { \br_op__insn [25] \br_op__insn [24] \br_op__insn [23] \br_op__insn [22] \br_op__insn [21] \br_op__insn [20] \br_op__insn [19] \br_op__insn [18] \br_op__insn [17] \br_op__insn [16] \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [23] { \br_op__insn [25] \br_op__insn [24] \br_op__insn [23] \br_op__insn [22] \br_op__insn [21] \br_op__insn [20] \br_op__insn [19] \br_op__insn [18] \br_op__insn [17] \br_op__insn [16] \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [23] { \br_op__insn [25] \br_op__insn [24] \br_op__insn [23] \br_op__insn [22] \br_op__insn [21] \br_op__insn [20] \br_op__insn [19] \br_op__insn [18] \br_op__insn [17] \br_op__insn [16] \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [23] { \br_op__insn [25] \br_op__insn [24] \br_op__insn [23] \br_op__insn [22] \br_op__insn [21] \br_op__insn [20] \br_op__insn [19] \br_op__insn [18] \br_op__insn [17] \br_op__insn [16] \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [23] { \br_op__insn [25] \br_op__insn [24] \br_op__insn [23] \br_op__insn [22] \br_op__insn [21] \br_op__insn [20] \br_op__insn [19] \br_op__insn [18] \br_op__insn [17] \br_op__insn [16] \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [23] { \br_op__insn [25] \br_op__insn [24] \br_op__insn [23] \br_op__insn [22] \br_op__insn [21] \br_op__insn [20] \br_op__insn [19] \br_op__insn [18] \br_op__insn [17] \br_op__insn [16] \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [23] { \br_op__insn [25] \br_op__insn [24] \br_op__insn [23] \br_op__insn [22] \br_op__insn [21] \br_op__insn [20] \br_op__insn [19] \br_op__insn [18] \br_op__insn [17] \br_op__insn [16] \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [23] { \br_op__insn [25] \br_op__insn [24] \br_op__insn [23] \br_op__insn [22] \br_op__insn [21] \br_op__insn [20] \br_op__insn [19] \br_op__insn [18] \br_op__insn [17] \br_op__insn [16] \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [23] { \br_op__insn [25] \br_op__insn [24] \br_op__insn [23] \br_op__insn [22] \br_op__insn [21] \br_op__insn [20] \br_op__insn [19] \br_op__insn [18] \br_op__insn [17] \br_op__insn [16] \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [23] { \br_op__insn [25] \br_op__insn [24] \br_op__insn [23] \br_op__insn [22] \br_op__insn [21] \br_op__insn [20] \br_op__insn [19] \br_op__insn [18] \br_op__insn [17] \br_op__insn [16] \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [23] { \br_op__insn [25] \br_op__insn [24] \br_op__insn [23] \br_op__insn [22] \br_op__insn [21] \br_op__insn [20] \br_op__insn [19] \br_op__insn [18] \br_op__insn [17] \br_op__insn [16] \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [23] { \br_op__insn [25] \br_op__insn [24] \br_op__insn [23] \br_op__insn [22] \br_op__insn [21] \br_op__insn [20] \br_op__insn [19] \br_op__insn [18] \br_op__insn [17] \br_op__insn [16] \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [23] { \br_op__insn [25] \br_op__insn [24] \br_op__insn [23] \br_op__insn [22] \br_op__insn [21] \br_op__insn [20] \br_op__insn [19] \br_op__insn [18] \br_op__insn [17] \br_op__insn [16] \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [23] { \br_op__insn [25] \br_op__insn [24] \br_op__insn [23] \br_op__insn [22] \br_op__insn [21] \br_op__insn [20] \br_op__insn [19] \br_op__insn [18] \br_op__insn [17] \br_op__insn [16] \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [23] { \br_op__insn [25] \br_op__insn [24] \br_op__insn [23] \br_op__insn [22] \br_op__insn [21] \br_op__insn [20] \br_op__insn [19] \br_op__insn [18] \br_op__insn [17] \br_op__insn [16] \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [23] { \br_op__insn [25] \br_op__insn [24] \br_op__insn [23] \br_op__insn [22] \br_op__insn [21] \br_op__insn [20] \br_op__insn [19] \br_op__insn [18] \br_op__insn [17] \br_op__insn [16] \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [23] { \br_op__insn [25] \br_op__insn [24] \br_op__insn [23] \br_op__insn [22] \br_op__insn [21] \br_op__insn [20] \br_op__insn [19] \br_op__insn [18] \br_op__insn [17] \br_op__insn [16] \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [23] { \br_op__insn [25] \br_op__insn [24] \br_op__insn [23] \br_op__insn [22] \br_op__insn [21] \br_op__insn [20] \br_op__insn [19] \br_op__insn [18] \br_op__insn [17] \br_op__insn [16] \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [23] { \br_op__insn [25] \br_op__insn [24] \br_op__insn [23] \br_op__insn [22] \br_op__insn [21] \br_op__insn [20] \br_op__insn [19] \br_op__insn [18] \br_op__insn [17] \br_op__insn [16] \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [23] { \br_op__insn [25] \br_op__insn [24] \br_op__insn [23] \br_op__insn [22] \br_op__insn [21] \br_op__insn [20] \br_op__insn [19] \br_op__insn [18] \br_op__insn [17] \br_op__insn [16] \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [23] { \br_op__insn [25] \br_op__insn [24] \br_op__insn [23] \br_op__insn [22] \br_op__insn [21] \br_op__insn [20] \br_op__insn [19] \br_op__insn [18] \br_op__insn [17] \br_op__insn [16] \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [23] { \br_op__insn [25] \br_op__insn [24] \br_op__insn [23] \br_op__insn [22] \br_op__insn [21] \br_op__insn [20] \br_op__insn [19] \br_op__insn [18] \br_op__insn [17] \br_op__insn [16] \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [23] { \br_op__insn [25] \br_op__insn [24] \br_op__insn [23] \br_op__insn [22] \br_op__insn [21] \br_op__insn [20] \br_op__insn [19] \br_op__insn [18] \br_op__insn [17] \br_op__insn [16] \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [23] { \br_op__insn [25] \br_op__insn [24] \br_op__insn [23] \br_op__insn [22] \br_op__insn [21] \br_op__insn [20] \br_op__insn [19] \br_op__insn [18] \br_op__insn [17] \br_op__insn [16] \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [23] { \br_op__insn [25] \br_op__insn [24] \br_op__insn [23] \br_op__insn [22] \br_op__insn [21] \br_op__insn [20] \br_op__insn [19] \br_op__insn [18] \br_op__insn [17] \br_op__insn [16] \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [23] { \br_op__insn [25] \br_op__insn [24] \br_op__insn [23] \br_op__insn [22] \br_op__insn [21] \br_op__insn [20] \br_op__insn [19] \br_op__insn [18] \br_op__insn [17] \br_op__insn [16] \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [23] { \br_op__insn [25] \br_op__insn [24] \br_op__insn [23] \br_op__insn [22] \br_op__insn [21] \br_op__insn [20] \br_op__insn [19] \br_op__insn [18] \br_op__insn [17] \br_op__insn [16] \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [23] { \br_op__insn [25] \br_op__insn [24] \br_op__insn [23] \br_op__insn [22] \br_op__insn [21] \br_op__insn [20] \br_op__insn [19] \br_op__insn [18] \br_op__insn [17] \br_op__insn [16] \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [23] { \br_op__insn [25] \br_op__insn [24] \br_op__insn [23] \br_op__insn [22] \br_op__insn [21] \br_op__insn [20] \br_op__insn [19] \br_op__insn [18] \br_op__insn [17] \br_op__insn [16] \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [23] { \br_op__insn [25] \br_op__insn [24] \br_op__insn [23] \br_op__insn [22] \br_op__insn [21] \br_op__insn [20] \br_op__insn [19] \br_op__insn [18] \br_op__insn [17] \br_op__insn [16] \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [23] { \br_op__insn [25] \br_op__insn [24] \br_op__insn [23] \br_op__insn [22] \br_op__insn [21] \br_op__insn [20] \br_op__insn [19] \br_op__insn [18] \br_op__insn [17] \br_op__insn [16] \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [23] { \br_op__insn [25] \br_op__insn [24] \br_op__insn [23] \br_op__insn [22] \br_op__insn [21] \br_op__insn [20] \br_op__insn [19] \br_op__insn [18] \br_op__insn [17] \br_op__insn [16] \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [23] } { \br_op__insn [25] \br_op__insn [24] \br_op__insn [23] \br_op__insn [22] \br_op__insn [21] \br_op__insn [20] \br_op__insn [19] \br_op__insn [18] \br_op__insn [17] \br_op__insn [16] \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } } 2'00 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:152" - attribute \nmigen.decoding "OP_BC/7" - case 7'0000111 - assign \br_imm_addr { { { { \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [13] { \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [13] { \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [13] { \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [13] { \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [13] { \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [13] { \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [13] { \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [13] { \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [13] { \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [13] { \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [13] { \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [13] { \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [13] { \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [13] { \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [13] { \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [13] { \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [13] { \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [13] { \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [13] { \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [13] { \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [13] { \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [13] { \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [13] { \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [13] { \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [13] { \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [13] { \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [13] { \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [13] { \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [13] { \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [13] { \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [13] { \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [13] { \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [13] { \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [13] { \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [13] { \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [13] { \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [13] { \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] 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\br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [13] { \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [13] { \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [13] { \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [13] { \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [13] { \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [13] { \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } [13] } { \br_op__insn [15] \br_op__insn [14] \br_op__insn [13] \br_op__insn [12] \br_op__insn [11] \br_op__insn [10] \br_op__insn [9] \br_op__insn [8] \br_op__insn [7] \br_op__insn [6] \br_op__insn [5] \br_op__insn [4] \br_op__insn [3] \br_op__insn [2] } } 2'00 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:158" - attribute \nmigen.decoding "OP_BCREG/8" - case 7'0001000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:160" - switch { $46 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:160" - case 1'1 - assign \br_imm_addr { \fast1 [63:2] 2'00 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:162" - case - assign \br_imm_addr { \fast2 [63:2] 2'00 } - end - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:89" - wire width 1 \br_taken - process $group_11 - assign \br_taken 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:145" - switch \br_op__insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:147" - attribute \nmigen.decoding "OP_B/6" - case 7'0000110 - assign \br_taken 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:152" - attribute \nmigen.decoding "OP_BC/7" - case 7'0000111 - assign \br_taken \bc_taken - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:158" - attribute \nmigen.decoding "OP_BCREG/8" - case 7'0001000 - assign \br_taken \bc_taken - end - sync init - end - process $group_12 - assign \fast1_ok 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:145" - switch \br_op__insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:147" - attribute \nmigen.decoding "OP_B/6" - case 7'0000110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:152" - attribute \nmigen.decoding "OP_BC/7" - case 7'0000111 - assign \fast1_ok \ctr_write - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:158" - attribute \nmigen.decoding "OP_BCREG/8" - case 7'0001000 - assign \fast1_ok \ctr_write - end - sync init - end - process $group_13 - assign \nia 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \nia \br_addr - sync init - end - process $group_14 - assign \nia_ok 1'0 - assign \nia_ok \br_taken - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:175" - wire width 65 $48 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:175" - wire width 65 $49 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:175" - cell $add $50 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 65 - connect \A \br_op__cia - connect \B 3'100 - connect \Y $49 - end - connect $48 $49 - process $group_15 - assign \fast2$11 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:172" - switch { \br_op__lk } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:172" - case 1'1 - assign \fast2$11 $48 [63:0] - end - sync init - end - process $group_16 - assign \fast2_ok 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:172" - switch { \br_op__lk } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/branch/main_stage.py:172" - case 1'1 - assign \fast2_ok 1'1 - end - sync init - end - process $group_17 - assign \muxid$1 2'00 - assign \muxid$1 \muxid - sync init - end - process $group_18 - assign \br_op__cia$2 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \br_op__insn_type$3 7'0000000 - assign \br_op__fn_unit$4 11'00000000000 - assign \br_op__insn$5 32'00000000000000000000000000000000 - assign \br_op__imm_data__data$6 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \br_op__imm_data__ok$7 1'0 - assign \br_op__lk$8 1'0 - assign \br_op__is_32bit$9 1'0 - assign { \br_op__is_32bit$9 \br_op__lk$8 { \br_op__imm_data__ok$7 \br_op__imm_data__data$6 } \br_op__insn$5 \br_op__fn_unit$4 \br_op__insn_type$3 \br_op__cia$2 } { \br_op__is_32bit \br_op__lk { \br_op__imm_data__ok \br_op__imm_data__data } \br_op__insn \br_op__fn_unit \br_op__insn_type \br_op__cia } - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.branch0.alu_branch0.pipe" -module \pipe$19 - attribute \src "simple/issuer.py:141" - wire width 1 input 0 \coresync_clk - attribute \src "simple/issuer.py:141" - wire width 1 input 1 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" - wire width 1 input 2 \p_valid_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" - wire width 1 output 3 \p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 input 4 \muxid - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 input 5 \br_op__cia - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 input 6 \br_op__insn_type - attribute \enum_base_type "Function" - attribute \enum_value_00000000000 "NONE" - attribute \enum_value_00000000010 "ALU" - attribute \enum_value_00000000100 "LDST" - attribute \enum_value_00000001000 "SHIFT_ROT" - attribute \enum_value_00000010000 "LOGICAL" - attribute \enum_value_00000100000 "BRANCH" - attribute \enum_value_00001000000 "CR" - attribute \enum_value_00010000000 "TRAP" - attribute \enum_value_00100000000 "MUL" - attribute \enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 input 7 \br_op__fn_unit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 input 8 \br_op__insn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 input 9 \br_op__imm_data__data - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 10 \br_op__imm_data__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 11 \br_op__lk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 12 \br_op__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 13 \fast1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 14 \fast2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 4 input 15 \cr_a - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" - wire width 1 output 16 \n_valid_o - attribute \src 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\main_br_op__lk$19 - connect \br_op__is_32bit$9 \main_br_op__is_32bit$20 - connect \fast1$10 \main_fast1$21 - connect \fast1_ok \main_fast1_ok - connect \fast2$11 \main_fast2$22 - connect \fast2_ok \main_fast2_ok - connect \nia \main_nia - connect \nia_ok \main_nia_ok - end - process $group_0 - assign \main_muxid 2'00 - assign \main_muxid \muxid - sync init - end - process $group_1 - assign \main_br_op__cia 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \main_br_op__insn_type 7'0000000 - assign \main_br_op__fn_unit 11'00000000000 - assign \main_br_op__insn 32'00000000000000000000000000000000 - assign \main_br_op__imm_data__data 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \main_br_op__imm_data__ok 1'0 - assign \main_br_op__lk 1'0 - assign \main_br_op__is_32bit 1'0 - assign { \main_br_op__is_32bit \main_br_op__lk { \main_br_op__imm_data__ok \main_br_op__imm_data__data } \main_br_op__insn \main_br_op__fn_unit \main_br_op__insn_type \main_br_op__cia } { \br_op__is_32bit \br_op__lk { \br_op__imm_data__ok \br_op__imm_data__data } \br_op__insn \br_op__fn_unit \br_op__insn_type \br_op__cia } - sync init - end - process $group_9 - assign \main_fast1 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \main_fast1 \fast1 - sync init - end - process $group_10 - assign \main_fast2 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \main_fast2 \fast2 - sync init - end - process $group_11 - assign \main_cr_a 4'0000 - assign \main_cr_a \cr_a - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:621" - wire width 1 \p_valid_i$23 - process $group_12 - assign \p_valid_i$23 1'0 - assign \p_valid_i$23 \p_valid_i - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:619" - wire width 1 \n_i_rdy_data - process $group_13 - assign \n_i_rdy_data 1'0 - assign \n_i_rdy_data \n_ready_i - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" - wire width 1 \p_valid_i_p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" - wire width 1 $24 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" - cell $and $25 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \p_valid_i$23 - connect \B \p_ready_o - connect \Y $24 - end - process $group_14 - assign \p_valid_i_p_ready_o 1'0 - assign \p_valid_i_p_ready_o $24 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \muxid$26 - process $group_15 - assign \muxid$26 2'00 - assign \muxid$26 \main_muxid$12 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \br_op__cia$27 - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \br_op__insn_type$28 - attribute \enum_base_type "Function" - attribute \enum_value_00000000000 "NONE" - attribute \enum_value_00000000010 "ALU" - attribute \enum_value_00000000100 "LDST" - attribute \enum_value_00000001000 "SHIFT_ROT" - attribute \enum_value_00000010000 "LOGICAL" - attribute \enum_value_00000100000 "BRANCH" - attribute \enum_value_00001000000 "CR" - attribute \enum_value_00010000000 "TRAP" - attribute \enum_value_00100000000 "MUL" - attribute \enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 \br_op__fn_unit$29 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \br_op__insn$30 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \br_op__imm_data__data$31 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \br_op__imm_data__ok$32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \br_op__lk$33 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \br_op__is_32bit$34 - process $group_16 - assign \br_op__cia$27 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \br_op__insn_type$28 7'0000000 - assign \br_op__fn_unit$29 11'00000000000 - assign \br_op__insn$30 32'00000000000000000000000000000000 - assign \br_op__imm_data__data$31 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \br_op__imm_data__ok$32 1'0 - assign \br_op__lk$33 1'0 - assign \br_op__is_32bit$34 1'0 - assign { \br_op__is_32bit$34 \br_op__lk$33 { \br_op__imm_data__ok$32 \br_op__imm_data__data$31 } \br_op__insn$30 \br_op__fn_unit$29 \br_op__insn_type$28 \br_op__cia$27 } { \main_br_op__is_32bit$20 \main_br_op__lk$19 { \main_br_op__imm_data__ok$18 \main_br_op__imm_data__data$17 } \main_br_op__insn$16 \main_br_op__fn_unit$15 \main_br_op__insn_type$14 \main_br_op__cia$13 } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 \fast1$35 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \fast1_ok$36 - process $group_24 - assign \fast1$35 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \fast1_ok$36 1'0 - assign { \fast1_ok$36 \fast1$35 } { \main_fast1_ok \main_fast1$21 } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 \fast2$37 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \fast2_ok$38 - process $group_26 - assign \fast2$37 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \fast2_ok$38 1'0 - assign { \fast2_ok$38 \fast2$37 } { \main_fast2_ok \main_fast2$22 } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 \nia$39 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \nia_ok$40 - process $group_28 - assign \nia$39 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \nia_ok$40 1'0 - assign { \nia_ok$40 \nia$39 } { \main_nia_ok \main_nia } - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615" - wire width 1 \r_busy - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615" - wire width 1 \r_busy$next - process $group_30 - assign \r_busy$next \r_busy - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign \r_busy$next 1'1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign \r_busy$next 1'0 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \r_busy$next 1'0 - end - sync init - update \r_busy 1'0 - sync posedge \coresync_clk - update \r_busy \r_busy$next - end - process $group_31 - assign \muxid$1$next \muxid$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign \muxid$1$next \muxid$26 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign \muxid$1$next \muxid$26 - end - sync init - update \muxid$1 2'00 - sync posedge \coresync_clk - update \muxid$1 \muxid$1$next - end - process $group_32 - assign \br_op__cia$2$next \br_op__cia$2 - assign \br_op__insn_type$3$next \br_op__insn_type$3 - assign \br_op__fn_unit$4$next \br_op__fn_unit$4 - assign \br_op__insn$5$next \br_op__insn$5 - assign \br_op__imm_data__data$6$next \br_op__imm_data__data$6 - assign \br_op__imm_data__ok$7$next \br_op__imm_data__ok$7 - assign \br_op__lk$8$next \br_op__lk$8 - assign \br_op__is_32bit$9$next \br_op__is_32bit$9 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign { \br_op__is_32bit$9$next \br_op__lk$8$next { \br_op__imm_data__ok$7$next \br_op__imm_data__data$6$next } \br_op__insn$5$next \br_op__fn_unit$4$next \br_op__insn_type$3$next \br_op__cia$2$next } { \br_op__is_32bit$34 \br_op__lk$33 { \br_op__imm_data__ok$32 \br_op__imm_data__data$31 } \br_op__insn$30 \br_op__fn_unit$29 \br_op__insn_type$28 \br_op__cia$27 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign { \br_op__is_32bit$9$next \br_op__lk$8$next { \br_op__imm_data__ok$7$next \br_op__imm_data__data$6$next } \br_op__insn$5$next \br_op__fn_unit$4$next \br_op__insn_type$3$next \br_op__cia$2$next } { \br_op__is_32bit$34 \br_op__lk$33 { \br_op__imm_data__ok$32 \br_op__imm_data__data$31 } \br_op__insn$30 \br_op__fn_unit$29 \br_op__insn_type$28 \br_op__cia$27 } - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \br_op__imm_data__data$6$next 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \br_op__imm_data__ok$7$next 1'0 - end - sync init - update \br_op__cia$2 64'0000000000000000000000000000000000000000000000000000000000000000 - update \br_op__insn_type$3 7'0000000 - update \br_op__fn_unit$4 11'00000000000 - update \br_op__insn$5 32'00000000000000000000000000000000 - update \br_op__imm_data__data$6 64'0000000000000000000000000000000000000000000000000000000000000000 - update \br_op__imm_data__ok$7 1'0 - update \br_op__lk$8 1'0 - update \br_op__is_32bit$9 1'0 - sync posedge \coresync_clk - update \br_op__cia$2 \br_op__cia$2$next - update \br_op__insn_type$3 \br_op__insn_type$3$next - update \br_op__fn_unit$4 \br_op__fn_unit$4$next - update \br_op__insn$5 \br_op__insn$5$next - update \br_op__imm_data__data$6 \br_op__imm_data__data$6$next - update \br_op__imm_data__ok$7 \br_op__imm_data__ok$7$next - update \br_op__lk$8 \br_op__lk$8$next - update \br_op__is_32bit$9 \br_op__is_32bit$9$next - end - process $group_40 - assign \fast1$10$next \fast1$10 - assign \fast1_ok$next \fast1_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign { \fast1_ok$next \fast1$10$next } { \fast1_ok$36 \fast1$35 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign { \fast1_ok$next \fast1$10$next } { \fast1_ok$36 \fast1$35 } - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \fast1_ok$next 1'0 - end - sync init - update \fast1$10 64'0000000000000000000000000000000000000000000000000000000000000000 - update \fast1_ok 1'0 - sync posedge \coresync_clk - update \fast1$10 \fast1$10$next - update \fast1_ok \fast1_ok$next - end - process $group_42 - assign \fast2$11$next \fast2$11 - assign \fast2_ok$next \fast2_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign { \fast2_ok$next \fast2$11$next } { \fast2_ok$38 \fast2$37 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign { \fast2_ok$next \fast2$11$next } { \fast2_ok$38 \fast2$37 } - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \fast2_ok$next 1'0 - end - sync init - update \fast2$11 64'0000000000000000000000000000000000000000000000000000000000000000 - update \fast2_ok 1'0 - sync posedge \coresync_clk - update \fast2$11 \fast2$11$next - update \fast2_ok \fast2_ok$next - end - process $group_44 - assign \nia$next \nia - assign \nia_ok$next \nia_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign { \nia_ok$next \nia$next } { \nia_ok$40 \nia$39 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign { \nia_ok$next \nia$next } { \nia_ok$40 \nia$39 } - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \nia_ok$next 1'0 - end - sync init - update \nia 64'0000000000000000000000000000000000000000000000000000000000000000 - update \nia_ok 1'0 - sync posedge \coresync_clk - update \nia \nia$next - update \nia_ok \nia_ok$next - end - process $group_46 - assign \n_valid_o 1'0 - assign \n_valid_o \r_busy - sync init - end - process $group_47 - assign \p_ready_o 1'0 - assign \p_ready_o \n_i_rdy_data - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.branch0.alu_branch0" -module \alu_branch0 - attribute \src "simple/issuer.py:141" - wire width 1 input 0 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 1 \fast1_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 2 \fast2_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 3 \nia_ok - attribute \src "simple/issuer.py:141" - wire width 1 input 4 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" - wire width 1 output 5 \n_valid_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" - wire width 1 input 6 \n_ready_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 input 7 \br_op__cia - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 input 8 \br_op__insn_type - attribute \enum_base_type "Function" - attribute \enum_value_00000000000 "NONE" - attribute \enum_value_00000000010 "ALU" - attribute \enum_value_00000000100 "LDST" - attribute \enum_value_00000001000 "SHIFT_ROT" - attribute \enum_value_00000010000 "LOGICAL" - attribute \enum_value_00000100000 "BRANCH" - attribute \enum_value_00001000000 "CR" - attribute \enum_value_00010000000 "TRAP" - attribute \enum_value_00100000000 "MUL" - attribute \enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 input 9 \br_op__fn_unit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 input 10 \br_op__insn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 input 11 \br_op__imm_data__data - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 12 \br_op__imm_data__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 13 \br_op__lk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 14 \br_op__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 output 15 \fast1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 output 16 \fast2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 output 17 \nia - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 18 \fast1$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 19 \fast2$2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 4 input 20 \cr_a - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" - wire width 1 input 21 \p_valid_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" - wire width 1 output 22 \p_ready_o - cell \p$17 \p - connect \p_valid_i \p_valid_i - connect \p_ready_o \p_ready_o - end - cell \n$18 \n - connect \n_valid_o \n_valid_o - connect \n_ready_i \n_ready_i - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" - wire width 1 \pipe_p_valid_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" - wire width 1 \pipe_p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \pipe_muxid - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \pipe_br_op__cia - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \pipe_br_op__insn_type - attribute \enum_base_type "Function" - attribute \enum_value_00000000000 "NONE" - attribute \enum_value_00000000010 "ALU" - attribute \enum_value_00000000100 "LDST" - attribute \enum_value_00000001000 "SHIFT_ROT" - attribute \enum_value_00000010000 "LOGICAL" - attribute \enum_value_00000100000 "BRANCH" - attribute \enum_value_00001000000 "CR" - attribute \enum_value_00010000000 "TRAP" - attribute \enum_value_00100000000 "MUL" - attribute \enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 \pipe_br_op__fn_unit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \pipe_br_op__insn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \pipe_br_op__imm_data__data - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_br_op__imm_data__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_br_op__lk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_br_op__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \pipe_fast1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \pipe_fast2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 4 \pipe_cr_a - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" - wire width 1 \pipe_n_valid_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" - wire width 1 \pipe_n_ready_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \pipe_muxid$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \pipe_br_op__cia$4 - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \pipe_br_op__insn_type$5 - attribute \enum_base_type "Function" - attribute \enum_value_00000000000 "NONE" - attribute \enum_value_00000000010 "ALU" - attribute \enum_value_00000000100 "LDST" - attribute \enum_value_00000001000 "SHIFT_ROT" - attribute \enum_value_00000010000 "LOGICAL" - attribute \enum_value_00000100000 "BRANCH" - attribute \enum_value_00001000000 "CR" - attribute \enum_value_00010000000 "TRAP" - attribute \enum_value_00100000000 "MUL" - attribute \enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 \pipe_br_op__fn_unit$6 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \pipe_br_op__insn$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \pipe_br_op__imm_data__data$8 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_br_op__imm_data__ok$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_br_op__lk$10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_br_op__is_32bit$11 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 \pipe_fast1$12 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \pipe_fast1_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 \pipe_fast2$13 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \pipe_fast2_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 \pipe_nia - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \pipe_nia_ok - cell \pipe$19 \pipe - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \p_valid_i \pipe_p_valid_i - connect \p_ready_o \pipe_p_ready_o - connect \muxid \pipe_muxid - connect \br_op__cia \pipe_br_op__cia - connect \br_op__insn_type \pipe_br_op__insn_type - connect \br_op__fn_unit \pipe_br_op__fn_unit - connect \br_op__insn \pipe_br_op__insn - connect \br_op__imm_data__data \pipe_br_op__imm_data__data - connect \br_op__imm_data__ok \pipe_br_op__imm_data__ok - connect \br_op__lk \pipe_br_op__lk - connect \br_op__is_32bit \pipe_br_op__is_32bit - connect \fast1 \pipe_fast1 - connect \fast2 \pipe_fast2 - connect \cr_a \pipe_cr_a - connect \n_valid_o \pipe_n_valid_o - connect \n_ready_i \pipe_n_ready_i - connect \muxid$1 \pipe_muxid$3 - connect \br_op__cia$2 \pipe_br_op__cia$4 - connect \br_op__insn_type$3 \pipe_br_op__insn_type$5 - connect \br_op__fn_unit$4 \pipe_br_op__fn_unit$6 - connect \br_op__insn$5 \pipe_br_op__insn$7 - connect \br_op__imm_data__data$6 \pipe_br_op__imm_data__data$8 - connect \br_op__imm_data__ok$7 \pipe_br_op__imm_data__ok$9 - connect \br_op__lk$8 \pipe_br_op__lk$10 - connect \br_op__is_32bit$9 \pipe_br_op__is_32bit$11 - connect \fast1$10 \pipe_fast1$12 - connect \fast1_ok \pipe_fast1_ok - connect \fast2$11 \pipe_fast2$13 - connect \fast2_ok \pipe_fast2_ok - connect \nia \pipe_nia - connect \nia_ok \pipe_nia_ok - end - process $group_0 - assign \pipe_p_valid_i 1'0 - assign \pipe_p_valid_i \p_valid_i - sync init - end - process $group_1 - assign \p_ready_o 1'0 - assign \p_ready_o \pipe_p_ready_o - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \muxid - process $group_2 - assign \pipe_muxid 2'00 - assign \pipe_muxid \muxid - sync init - end - process $group_3 - assign \pipe_br_op__cia 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \pipe_br_op__insn_type 7'0000000 - assign \pipe_br_op__fn_unit 11'00000000000 - assign \pipe_br_op__insn 32'00000000000000000000000000000000 - assign \pipe_br_op__imm_data__data 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \pipe_br_op__imm_data__ok 1'0 - assign \pipe_br_op__lk 1'0 - assign \pipe_br_op__is_32bit 1'0 - assign { \pipe_br_op__is_32bit \pipe_br_op__lk { \pipe_br_op__imm_data__ok \pipe_br_op__imm_data__data } \pipe_br_op__insn \pipe_br_op__fn_unit \pipe_br_op__insn_type \pipe_br_op__cia } { \br_op__is_32bit \br_op__lk { \br_op__imm_data__ok \br_op__imm_data__data } \br_op__insn \br_op__fn_unit \br_op__insn_type \br_op__cia } - sync init - end - process $group_11 - assign \pipe_fast1 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \pipe_fast1 \fast1$1 - sync init - end - process $group_12 - assign \pipe_fast2 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \pipe_fast2 \fast2$2 - sync init - end - process $group_13 - assign \pipe_cr_a 4'0000 - assign \pipe_cr_a \cr_a - sync init - end - process $group_14 - assign \n_valid_o 1'0 - assign \n_valid_o \pipe_n_valid_o - sync init - end - process $group_15 - assign \pipe_n_ready_i 1'0 - assign \pipe_n_ready_i \n_ready_i - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \muxid$14 - process $group_16 - assign \muxid$14 2'00 - assign \muxid$14 \pipe_muxid$3 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \br_op__cia$15 - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute 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attribute \enum_value_00000000100 "LDST" - attribute \enum_value_00000001000 "SHIFT_ROT" - attribute \enum_value_00000010000 "LOGICAL" - attribute \enum_value_00000100000 "BRANCH" - attribute \enum_value_00001000000 "CR" - attribute \enum_value_00010000000 "TRAP" - attribute \enum_value_00100000000 "MUL" - attribute \enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 \br_op__fn_unit$17 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \br_op__insn$18 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \br_op__imm_data__data$19 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \br_op__imm_data__ok$20 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \br_op__lk$21 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \br_op__is_32bit$22 - process $group_17 - assign \br_op__cia$15 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \br_op__insn_type$16 7'0000000 - assign \br_op__fn_unit$17 11'00000000000 - assign \br_op__insn$18 32'00000000000000000000000000000000 - assign \br_op__imm_data__data$19 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \br_op__imm_data__ok$20 1'0 - assign \br_op__lk$21 1'0 - assign \br_op__is_32bit$22 1'0 - assign { \br_op__is_32bit$22 \br_op__lk$21 { \br_op__imm_data__ok$20 \br_op__imm_data__data$19 } \br_op__insn$18 \br_op__fn_unit$17 \br_op__insn_type$16 \br_op__cia$15 } { \pipe_br_op__is_32bit$11 \pipe_br_op__lk$10 { \pipe_br_op__imm_data__ok$9 \pipe_br_op__imm_data__data$8 } \pipe_br_op__insn$7 \pipe_br_op__fn_unit$6 \pipe_br_op__insn_type$5 \pipe_br_op__cia$4 } - sync init - end - process $group_25 - assign \fast1 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \fast1_ok 1'0 - assign { \fast1_ok \fast1 } { \pipe_fast1_ok \pipe_fast1$12 } - sync init - end - process $group_27 - assign \fast2 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \fast2_ok 1'0 - assign { \fast2_ok \fast2 } { \pipe_fast2_ok \pipe_fast2$13 } - sync init - end - process $group_29 - assign \nia 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \nia_ok 1'0 - assign { \nia_ok \nia } { \pipe_nia_ok \pipe_nia } - sync init - end - connect \muxid 2'00 -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.branch0.src_l" -module \src_l$23 - attribute \src "simple/issuer.py:141" - wire width 1 input 0 \coresync_clk - attribute \src "simple/issuer.py:141" - wire width 1 input 1 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 3 input 2 \s_src - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 3 input 3 \r_src - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire width 3 output 4 \q_src - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire width 3 \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire width 3 \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 3 $1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A \r_src - connect \Y $1 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 3 $3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $4 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A \q_int - connect \B $1 - connect \Y $3 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 3 $5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $6 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A $3 - connect \B \s_src - connect \Y $5 - end - process $group_0 - assign \q_int$next \q_int - assign \q_int$next $5 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \q_int$next 3'000 - end - sync init - update \q_int 3'000 - sync posedge \coresync_clk - update \q_int \q_int$next - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 3 $7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $8 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A \r_src - connect \Y $7 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 3 $9 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $10 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A \q_int - connect \B $7 - connect \Y $9 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 3 $11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $12 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A $9 - connect \B \s_src - connect \Y $11 - end - process $group_1 - assign \q_src 3'000 - assign \q_src $11 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" - wire width 3 \qn_src - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - wire width 3 $13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $14 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A \q_src - connect \Y $13 - end - process $group_2 - assign \qn_src 3'000 - assign \qn_src $13 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" - wire width 3 \qlq_src - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - wire width 3 $15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $16 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A \q_src - connect \B \q_int - connect \Y $15 - end - process $group_3 - assign \qlq_src 3'000 - assign \qlq_src $15 - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.branch0.opc_l" -module \opc_l$24 - attribute \src "simple/issuer.py:141" - wire width 1 input 0 \coresync_clk - attribute \src "simple/issuer.py:141" - wire width 1 input 1 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 1 input 2 \s_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 1 input 3 \r_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire width 1 output 4 \q_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire width 1 \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire width 1 \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_opc - connect \Y $1 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 1 $3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $4 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B $1 - connect \Y $3 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 1 $5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $6 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $3 - connect \B \s_opc - connect \Y $5 - end - process $group_0 - assign \q_int$next \q_int - assign \q_int$next $5 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \q_int$next 1'0 - end - sync init - update \q_int 1'0 - sync posedge \coresync_clk - update \q_int \q_int$next - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 1 $7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $8 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_opc - connect \Y $7 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 1 $9 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $10 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B $7 - connect \Y $9 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 1 $11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $12 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $9 - connect \B \s_opc - connect \Y $11 - end - process $group_1 - assign \q_opc 1'0 - assign \q_opc $11 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" - wire width 1 \qn_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - wire width 1 $13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $14 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_opc - connect \Y $13 - end - process $group_2 - assign \qn_opc 1'0 - assign \qn_opc $13 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" - wire width 1 \qlq_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - wire width 1 $15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $16 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_opc - connect \B \q_int - connect \Y $15 - end - process $group_3 - assign \qlq_opc 1'0 - assign \qlq_opc $15 - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.branch0.req_l" -module \req_l$25 - attribute \src "simple/issuer.py:141" - wire width 1 input 0 \coresync_clk - attribute \src "simple/issuer.py:141" - wire width 1 input 1 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire width 3 output 2 \q_req - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 3 input 3 \s_req - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 3 input 4 \r_req - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire width 3 \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire width 3 \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 3 $1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A \r_req - connect \Y $1 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 3 $3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $4 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A \q_int - connect \B $1 - connect \Y $3 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 3 $5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $6 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A $3 - connect \B \s_req - connect \Y $5 - end - process $group_0 - assign \q_int$next \q_int - assign \q_int$next $5 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \q_int$next 3'000 - end - sync init - update \q_int 3'000 - sync posedge \coresync_clk - update \q_int \q_int$next - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 3 $7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $8 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A \r_req - connect \Y $7 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 3 $9 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $10 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A \q_int - connect \B $7 - connect \Y $9 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 3 $11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $12 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A $9 - connect \B \s_req - connect \Y $11 - end - process $group_1 - assign \q_req 3'000 - assign \q_req $11 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" - wire width 3 \qn_req - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - wire width 3 $13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $14 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A \q_req - connect \Y $13 - end - process $group_2 - assign \qn_req 3'000 - assign \qn_req $13 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" - wire width 3 \qlq_req - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - wire width 3 $15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $16 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A \q_req - connect \B \q_int - connect \Y $15 - end - process $group_3 - assign \qlq_req 3'000 - assign \qlq_req $15 - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.branch0.rst_l" -module \rst_l$26 - attribute \src "simple/issuer.py:141" - wire width 1 input 0 \coresync_clk - attribute \src "simple/issuer.py:141" - wire width 1 input 1 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 1 input 2 \s_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 1 input 3 \r_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire width 1 \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire width 1 \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 1 $1 - attribute \src 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\oper_i_alu_branch0__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:100" - wire width 1 input 9 \cu_issue_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107" - wire width 1 output 10 \cu_busy_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96" - wire width 3 input 11 \cu_rdmaskn_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 3 output 12 \cu_rd__rel_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 3 input 13 \cu_rd__go_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 4 input 14 \src3_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 64 input 15 \src1_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 64 input 16 \src2_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 17 \fast1_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 3 output 18 \cu_wr__rel_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 3 input 19 \cu_wr__go_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 20 \fast2_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" - wire width 64 output 21 \dest1_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" - wire width 64 output 22 \dest2_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 23 \nia_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" - wire width 64 output 24 \dest3_o - attribute \src "simple/issuer.py:141" - wire width 1 input 25 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" - wire width 1 \alu_branch0_n_valid_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" - wire width 1 \alu_branch0_n_ready_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \alu_branch0_br_op__cia - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \alu_branch0_br_op__cia$next - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \alu_branch0_br_op__insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \alu_branch0_br_op__insn_type$next - attribute \enum_base_type "Function" - attribute \enum_value_00000000000 "NONE" - attribute \enum_value_00000000010 "ALU" - attribute \enum_value_00000000100 "LDST" - attribute \enum_value_00000001000 "SHIFT_ROT" - attribute \enum_value_00000010000 "LOGICAL" - attribute \enum_value_00000100000 "BRANCH" - attribute \enum_value_00001000000 "CR" - attribute \enum_value_00010000000 "TRAP" - attribute \enum_value_00100000000 "MUL" - attribute \enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 \alu_branch0_br_op__fn_unit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 \alu_branch0_br_op__fn_unit$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \alu_branch0_br_op__insn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \alu_branch0_br_op__insn$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \alu_branch0_br_op__imm_data__data - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \alu_branch0_br_op__imm_data__data$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \alu_branch0_br_op__imm_data__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \alu_branch0_br_op__imm_data__ok$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \alu_branch0_br_op__lk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \alu_branch0_br_op__lk$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \alu_branch0_br_op__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \alu_branch0_br_op__is_32bit$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 \alu_branch0_fast1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 \alu_branch0_fast2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 \alu_branch0_nia - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \alu_branch0_fast1$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \alu_branch0_fast2$2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 4 \alu_branch0_cr_a - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" - wire width 1 \alu_branch0_p_valid_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" - wire width 1 \alu_branch0_p_ready_o - cell \alu_branch0 \alu_branch0 - connect \coresync_clk \coresync_clk - connect \fast1_ok \fast1_ok - connect \fast2_ok \fast2_ok - connect \nia_ok \nia_ok - connect \coresync_rst \coresync_rst - connect \n_valid_o \alu_branch0_n_valid_o - connect \n_ready_i \alu_branch0_n_ready_i - connect \br_op__cia \alu_branch0_br_op__cia - connect \br_op__insn_type \alu_branch0_br_op__insn_type - connect \br_op__fn_unit \alu_branch0_br_op__fn_unit - connect \br_op__insn \alu_branch0_br_op__insn - connect \br_op__imm_data__data \alu_branch0_br_op__imm_data__data - connect \br_op__imm_data__ok \alu_branch0_br_op__imm_data__ok - connect \br_op__lk \alu_branch0_br_op__lk - connect \br_op__is_32bit \alu_branch0_br_op__is_32bit - connect \fast1 \alu_branch0_fast1 - connect \fast2 \alu_branch0_fast2 - connect \nia \alu_branch0_nia - connect \fast1$1 \alu_branch0_fast1$1 - connect \fast2$2 \alu_branch0_fast2$2 - connect \cr_a \alu_branch0_cr_a - connect \p_valid_i \alu_branch0_p_valid_i - connect \p_ready_o \alu_branch0_p_ready_o - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 3 \src_l_s_src - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 3 \src_l_s_src$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 3 \src_l_r_src - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 3 \src_l_r_src$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire width 3 \src_l_q_src - cell \src_l$23 \src_l - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \s_src \src_l_s_src - connect \r_src \src_l_r_src - connect \q_src \src_l_q_src - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 1 \opc_l_s_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 1 \opc_l_s_opc$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 1 \opc_l_r_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 1 \opc_l_r_opc$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire width 1 \opc_l_q_opc - cell \opc_l$24 \opc_l - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \s_opc \opc_l_s_opc - connect \r_opc \opc_l_r_opc - connect \q_opc \opc_l_q_opc - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire width 3 \req_l_q_req - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 3 \req_l_s_req - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 3 \req_l_s_req$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 3 \req_l_r_req - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 3 \req_l_r_req$next - cell \req_l$25 \req_l - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \q_req \req_l_q_req - connect \s_req \req_l_s_req - connect \r_req \req_l_r_req - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 1 \rst_l_s_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 1 \rst_l_s_rst$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 1 \rst_l_r_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 1 \rst_l_r_rst$next - cell \rst_l$26 \rst_l - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \s_rst \rst_l_s_rst - connect \r_rst \rst_l_r_rst - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire width 1 \rok_l_q_rdok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 1 \rok_l_s_rdok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 1 \rok_l_s_rdok$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 1 \rok_l_r_rdok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 1 \rok_l_r_rdok$next - cell \rok_l$27 \rok_l - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \q_rdok \rok_l_q_rdok - connect \s_rdok \rok_l_s_rdok - connect \r_rdok \rok_l_r_rdok - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire width 1 \alui_l_q_alui - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 1 \alui_l_r_alui - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 1 \alui_l_r_alui$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 1 \alui_l_s_alui - cell \alui_l$28 \alui_l - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \q_alui \alui_l_q_alui - connect \r_alui \alui_l_r_alui - connect \s_alui \alui_l_s_alui - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire width 1 \alu_l_q_alu - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 1 \alu_l_r_alu - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 1 \alu_l_r_alu$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 1 \alu_l_s_alu - cell \alu_l$29 \alu_l - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \q_alu \alu_l_q_alu - connect \r_alu \alu_l_r_alu - connect \s_alu \alu_l_s_alu - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:187" - wire width 1 \all_rd - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:188" - wire width 1 $3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:188" - cell $and $4 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cu_busy_o - connect \B \rok_l_q_rdok - connect \Y $3 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - wire width 1 $5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - wire width 3 $6 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - cell $not $7 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A \cu_rd__rel_o - connect \Y $6 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - wire width 3 $8 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - cell $or $9 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A $6 - connect \B \cu_rd__go_i - connect \Y $8 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - cell $reduce_and $10 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A $8 - connect \Y $5 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - wire width 1 $11 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - cell $and $12 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $3 - connect \B $5 - connect \Y $11 - end - process $group_0 - assign \all_rd 1'0 - assign \all_rd $11 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire width 1 \all_rd_dly - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire width 1 \all_rd_dly$next - process $group_1 - assign \all_rd_dly$next \all_rd_dly - assign \all_rd_dly$next \all_rd - sync init - update \all_rd_dly 1'0 - sync posedge \coresync_clk - update \all_rd_dly \all_rd_dly$next - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" - wire width 1 \all_rd_rise - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - wire width 1 $13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $not $14 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \all_rd_dly - connect \Y $13 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - wire width 1 $15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $and $16 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \all_rd - connect \B $13 - connect \Y $15 - end - process $group_2 - assign \all_rd_rise 1'0 - assign \all_rd_rise $15 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:192" - wire width 1 \all_rd_pulse - process $group_3 - assign \all_rd_pulse 1'0 - assign \all_rd_pulse \all_rd_rise - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:196" - wire width 1 \alu_done - process $group_4 - assign \alu_done 1'0 - assign \alu_done \alu_branch0_n_valid_o - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire width 1 \alu_done_dly - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire width 1 \alu_done_dly$next - process $group_5 - assign \alu_done_dly$next \alu_done_dly - assign \alu_done_dly$next \alu_done - sync init - update \alu_done_dly 1'0 - sync posedge \coresync_clk - update \alu_done_dly \alu_done_dly$next - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" - wire width 1 \alu_done_rise - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - wire width 1 $17 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $not $18 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \alu_done_dly - connect \Y $17 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - wire width 1 $19 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $and $20 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \alu_done - connect \B $17 - connect \Y $19 - end - process $group_6 - assign \alu_done_rise 1'0 - assign \alu_done_rise $19 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:197" - wire width 1 \alu_pulse - process $group_7 - assign \alu_pulse 1'0 - assign \alu_pulse \alu_done_rise - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:198" - wire width 3 \alu_pulsem - process $group_8 - assign \alu_pulsem 3'000 - assign \alu_pulsem { \alu_pulse \alu_pulse \alu_pulse } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:204" - wire width 3 \prev_wr_go - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:204" - wire width 3 \prev_wr_go$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:206" - wire width 3 $21 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:206" - cell $and $22 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A \cu_wr__go_i - connect \B { \cu_busy_o \cu_busy_o \cu_busy_o } - connect \Y $21 - end - process $group_9 - assign \prev_wr_go$next \prev_wr_go - assign \prev_wr_go$next $21 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \prev_wr_go$next 3'000 - end - sync init - update \prev_wr_go 3'000 - sync posedge \coresync_clk - update \prev_wr_go \prev_wr_go$next - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:108" - wire width 1 \cu_done_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - wire width 1 $23 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - wire width 1 $24 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - wire width 3 $25 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:97" - wire width 3 \cu_wrmask_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $not $26 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A \cu_wrmask_o - connect \Y $25 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - wire width 3 $27 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $and $28 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A \cu_wr__rel_o - connect \B $25 - connect \Y $27 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $reduce_bool $29 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A $27 - connect \Y $24 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $not $30 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $24 - connect \Y $23 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - wire width 1 $31 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $and $32 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cu_busy_o - connect \B $23 - connect \Y $31 - end - process $group_10 - assign \cu_done_o 1'0 - assign \cu_done_o $31 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:211" - wire width 1 \wr_any - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" - wire width 1 $33 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" - cell $reduce_bool $34 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \cu_wr__go_i - connect \Y $33 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" - wire width 1 $35 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" - cell $reduce_bool $36 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \prev_wr_go - connect \Y $35 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" - wire width 1 $37 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" - cell $or $38 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $33 - connect \B $35 - connect \Y $37 - end - process $group_11 - assign \wr_any 1'0 - assign \wr_any $37 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:212" - wire width 1 \req_done - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" - wire width 1 $39 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" - cell $not $40 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \alu_branch0_n_ready_i - connect \Y $39 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" - wire width 1 $41 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" - cell $and $42 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_any - connect \B $39 - connect \Y $41 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" - wire width 3 $43 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" - cell $and $44 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A \req_l_q_req - connect \B \cu_wrmask_o - connect \Y $43 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" - wire width 1 $45 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" - cell $eq $46 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $43 - connect \B 1'0 - connect \Y $45 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" - wire width 1 $47 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" - cell $and $48 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $41 - connect \B $45 - connect \Y $47 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - wire width 1 $49 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - cell $eq $50 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cu_wrmask_o - connect \B 1'0 - connect \Y $49 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - wire width 1 $51 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - cell $and $52 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $49 - connect \B \alu_branch0_n_ready_i - connect \Y $51 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - wire width 1 $53 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - cell $and $54 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $51 - connect \B \alu_branch0_n_valid_o - connect \Y $53 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - wire width 1 $55 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - cell $and $56 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $53 - connect \B \cu_busy_o - connect \Y $55 - end - process $group_12 - assign \req_done 1'0 - assign \req_done $47 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - switch { $55 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - case 1'1 - assign \req_done 1'1 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:226" - wire width 1 \reset - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:104" - wire width 1 \cu_go_die_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:230" - wire width 1 $57 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:230" - cell $or $58 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \req_done - connect \B \cu_go_die_i - connect \Y $57 - end - process $group_13 - assign \reset 1'0 - assign \reset $57 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:227" - wire width 1 \rst_r - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:231" - wire width 1 $59 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:231" - cell $or $60 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cu_issue_i - connect \B \cu_go_die_i - connect \Y $59 - end - process $group_14 - assign \rst_r 1'0 - assign \rst_r $59 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:228" - wire width 3 \reset_w - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:232" - wire width 3 $61 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:232" - cell $or $62 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A \cu_wr__go_i - connect \B { \cu_go_die_i \cu_go_die_i \cu_go_die_i } - connect \Y $61 - end - process $group_15 - assign \reset_w 3'000 - assign \reset_w $61 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:229" - wire width 3 \reset_r - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:233" - wire width 3 $63 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:233" - cell $or $64 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A \cu_rd__go_i - connect \B { \cu_go_die_i \cu_go_die_i \cu_go_die_i } - connect \Y $63 - end - process $group_16 - assign \reset_r 3'000 - assign \reset_r $63 - sync init - end - process $group_17 - assign \rok_l_s_rdok$next \rok_l_s_rdok - assign \rok_l_s_rdok$next \cu_issue_i - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \rok_l_s_rdok$next 1'0 - end - sync init - update \rok_l_s_rdok 1'0 - sync posedge \coresync_clk - update \rok_l_s_rdok \rok_l_s_rdok$next - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:237" - wire width 1 $65 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:237" - cell $and $66 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \alu_branch0_n_valid_o - connect \B \cu_busy_o - connect \Y $65 - end - process $group_18 - assign \rok_l_r_rdok$next \rok_l_r_rdok - assign \rok_l_r_rdok$next $65 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \rok_l_r_rdok$next 1'1 - end - sync init - update \rok_l_r_rdok 1'1 - sync posedge \coresync_clk - update \rok_l_r_rdok \rok_l_r_rdok$next - end - process $group_19 - assign \rst_l_s_rst$next \rst_l_s_rst - assign \rst_l_s_rst$next \all_rd - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \rst_l_s_rst$next 1'0 - end - sync init - update \rst_l_s_rst 1'0 - sync posedge \coresync_clk - update \rst_l_s_rst \rst_l_s_rst$next - end - process $group_20 - assign \rst_l_r_rst$next \rst_l_r_rst - assign \rst_l_r_rst$next \rst_r - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \rst_l_r_rst$next 1'1 - end - sync init - update \rst_l_r_rst 1'1 - sync posedge \coresync_clk - update \rst_l_r_rst \rst_l_r_rst$next - end - process $group_21 - assign \opc_l_s_opc$next \opc_l_s_opc - assign \opc_l_s_opc$next \cu_issue_i - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \opc_l_s_opc$next 1'0 - end - sync init - update \opc_l_s_opc 1'0 - sync posedge \coresync_clk - update \opc_l_s_opc \opc_l_s_opc$next - end - process $group_22 - assign \opc_l_r_opc$next \opc_l_r_opc - assign \opc_l_r_opc$next \req_done - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \opc_l_r_opc$next 1'1 - end - sync init - update \opc_l_r_opc 1'1 - sync posedge \coresync_clk - update \opc_l_r_opc \opc_l_r_opc$next - end - process $group_23 - assign \src_l_s_src$next \src_l_s_src - assign \src_l_s_src$next { \cu_issue_i \cu_issue_i \cu_issue_i } - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \src_l_s_src$next 3'000 - end - sync init - update \src_l_s_src 3'000 - sync posedge \coresync_clk - update \src_l_s_src \src_l_s_src$next - end - process $group_24 - assign \src_l_r_src$next \src_l_r_src - assign \src_l_r_src$next \reset_r - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \src_l_r_src$next 3'111 - end - sync init - update \src_l_r_src 3'111 - sync posedge \coresync_clk - update \src_l_r_src \src_l_r_src$next - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:252" - wire width 3 $67 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:252" - cell $and $68 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A \alu_pulsem - connect \B \cu_wrmask_o - connect \Y $67 - end - process $group_25 - assign \req_l_s_req$next \req_l_s_req - assign \req_l_s_req$next $67 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \req_l_s_req$next 3'000 - end - sync init - update \req_l_s_req 3'000 - sync posedge \coresync_clk - update \req_l_s_req \req_l_s_req$next - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:253" - wire width 3 $69 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:253" - cell $or $70 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A \reset_w - connect \B \prev_wr_go - connect \Y $69 - end - process $group_26 - assign \req_l_r_req$next \req_l_r_req - assign \req_l_r_req$next $69 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \req_l_r_req$next 3'111 - end - sync init - update \req_l_r_req 3'111 - sync posedge \coresync_clk - update \req_l_r_req \req_l_r_req$next - end - process $group_27 - assign \alu_branch0_br_op__cia$next \alu_branch0_br_op__cia - assign \alu_branch0_br_op__insn_type$next \alu_branch0_br_op__insn_type - assign \alu_branch0_br_op__fn_unit$next \alu_branch0_br_op__fn_unit - assign \alu_branch0_br_op__insn$next \alu_branch0_br_op__insn - assign \alu_branch0_br_op__imm_data__data$next \alu_branch0_br_op__imm_data__data - assign \alu_branch0_br_op__imm_data__ok$next \alu_branch0_br_op__imm_data__ok - assign \alu_branch0_br_op__lk$next \alu_branch0_br_op__lk - assign \alu_branch0_br_op__is_32bit$next \alu_branch0_br_op__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:257" - switch { \cu_issue_i } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:257" - case 1'1 - assign { \alu_branch0_br_op__is_32bit$next \alu_branch0_br_op__lk$next { \alu_branch0_br_op__imm_data__ok$next \alu_branch0_br_op__imm_data__data$next } \alu_branch0_br_op__insn$next \alu_branch0_br_op__fn_unit$next \alu_branch0_br_op__insn_type$next \alu_branch0_br_op__cia$next } { \oper_i_alu_branch0__is_32bit \oper_i_alu_branch0__lk { \oper_i_alu_branch0__imm_data__ok \oper_i_alu_branch0__imm_data__data } \oper_i_alu_branch0__insn \oper_i_alu_branch0__fn_unit \oper_i_alu_branch0__insn_type \oper_i_alu_branch0__cia } - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \alu_branch0_br_op__imm_data__data$next 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \alu_branch0_br_op__imm_data__ok$next 1'0 - end - sync init - update \alu_branch0_br_op__cia 64'0000000000000000000000000000000000000000000000000000000000000000 - update \alu_branch0_br_op__insn_type 7'0000000 - update \alu_branch0_br_op__fn_unit 11'00000000000 - update \alu_branch0_br_op__insn 32'00000000000000000000000000000000 - update \alu_branch0_br_op__imm_data__data 64'0000000000000000000000000000000000000000000000000000000000000000 - update \alu_branch0_br_op__imm_data__ok 1'0 - update \alu_branch0_br_op__lk 1'0 - update \alu_branch0_br_op__is_32bit 1'0 - sync posedge \coresync_clk - update \alu_branch0_br_op__cia \alu_branch0_br_op__cia$next - update \alu_branch0_br_op__insn_type \alu_branch0_br_op__insn_type$next - update \alu_branch0_br_op__fn_unit \alu_branch0_br_op__fn_unit$next - update \alu_branch0_br_op__insn \alu_branch0_br_op__insn$next - update \alu_branch0_br_op__imm_data__data \alu_branch0_br_op__imm_data__data$next - update \alu_branch0_br_op__imm_data__ok \alu_branch0_br_op__imm_data__ok$next - update \alu_branch0_br_op__lk \alu_branch0_br_op__lk$next - update \alu_branch0_br_op__is_32bit \alu_branch0_br_op__is_32bit$next - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" - wire width 64 \data_r0__fast1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" - wire width 64 \data_r0__fast1$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" - wire width 1 \data_r0__fast1_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" - wire width 1 \data_r0__fast1_ok$next - process $group_35 - assign \data_r0__fast1$next \data_r0__fast1 - assign \data_r0__fast1_ok$next \data_r0__fast1_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" - switch { \alu_pulse } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" - case 1'1 - assign { \data_r0__fast1_ok$next \data_r0__fast1$next } { \fast1_ok \alu_branch0_fast1 } - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" - switch { \cu_issue_i } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" - case 1'1 - assign { \data_r0__fast1_ok$next \data_r0__fast1$next } 65'00000000000000000000000000000000000000000000000000000000000000000 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \data_r0__fast1_ok$next 1'0 - end - sync init - update \data_r0__fast1 64'0000000000000000000000000000000000000000000000000000000000000000 - update \data_r0__fast1_ok 1'0 - sync posedge \coresync_clk - update \data_r0__fast1 \data_r0__fast1$next - update \data_r0__fast1_ok \data_r0__fast1_ok$next - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" - wire width 64 \data_r1__fast2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" - wire width 64 \data_r1__fast2$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" - wire width 1 \data_r1__fast2_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" - wire width 1 \data_r1__fast2_ok$next - process $group_37 - assign \data_r1__fast2$next \data_r1__fast2 - assign \data_r1__fast2_ok$next \data_r1__fast2_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" - switch { \alu_pulse } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" - case 1'1 - assign { \data_r1__fast2_ok$next \data_r1__fast2$next } { \fast2_ok \alu_branch0_fast2 } - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" - switch { \cu_issue_i } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" - case 1'1 - assign { \data_r1__fast2_ok$next \data_r1__fast2$next } 65'00000000000000000000000000000000000000000000000000000000000000000 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \data_r1__fast2_ok$next 1'0 - end - sync init - update \data_r1__fast2 64'0000000000000000000000000000000000000000000000000000000000000000 - update \data_r1__fast2_ok 1'0 - sync posedge \coresync_clk - update \data_r1__fast2 \data_r1__fast2$next - update \data_r1__fast2_ok \data_r1__fast2_ok$next - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" - wire width 64 \data_r2__nia - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" - wire width 64 \data_r2__nia$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" - wire width 1 \data_r2__nia_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" - wire width 1 \data_r2__nia_ok$next - process $group_39 - assign \data_r2__nia$next \data_r2__nia - assign \data_r2__nia_ok$next \data_r2__nia_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" - switch { \alu_pulse } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" - case 1'1 - assign { \data_r2__nia_ok$next \data_r2__nia$next } { \nia_ok \alu_branch0_nia } - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" - switch { \cu_issue_i } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" - case 1'1 - assign { \data_r2__nia_ok$next \data_r2__nia$next } 65'00000000000000000000000000000000000000000000000000000000000000000 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \data_r2__nia_ok$next 1'0 - end - sync init - update \data_r2__nia 64'0000000000000000000000000000000000000000000000000000000000000000 - update \data_r2__nia_ok 1'0 - sync posedge \coresync_clk - update \data_r2__nia \data_r2__nia$next - update \data_r2__nia_ok \data_r2__nia_ok$next - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" - wire width 1 $71 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" - cell $and $72 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \fast1_ok - connect \B \cu_busy_o - connect \Y $71 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" - wire width 1 $73 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" - cell $and $74 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \fast2_ok - connect \B \cu_busy_o - connect \Y $73 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" - wire width 1 $75 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" - cell $and $76 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \nia_ok - connect \B \cu_busy_o - connect \Y $75 - end - process $group_41 - assign \cu_wrmask_o 3'000 - assign \cu_wrmask_o { $75 $73 $71 } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:167" - wire width 1 \src_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:168" - wire width 1 $77 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:168" - cell $mux $78 - parameter \WIDTH 1 - connect \A \src_l_q_src [1] - connect \B \opc_l_q_opc - connect \S \alu_branch0_br_op__imm_data__ok - connect \Y $77 - end - process $group_42 - assign \src_sel 1'0 - assign \src_sel $77 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:166" - wire width 64 \src_or_imm - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:169" - wire width 64 $79 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:169" - cell $mux $80 - parameter \WIDTH 64 - connect \A \src2_i - connect \B \alu_branch0_br_op__imm_data__data - connect \S \alu_branch0_br_op__imm_data__ok - connect \Y $79 - end - process $group_43 - assign \src_or_imm 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \src_or_imm $79 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" - wire width 64 \src_r0 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" - wire width 64 \src_r0$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - wire width 64 $81 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - cell $mux $82 - parameter \WIDTH 64 - connect \A \src_r0 - connect \B \src1_i - connect \S \src_l_q_src [0] - connect \Y $81 - end - process $group_44 - assign \alu_branch0_fast1$1 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \alu_branch0_fast1$1 $81 - sync init - end - process $group_45 - assign \src_r0$next \src_r0 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" - switch { \src_l_q_src [0] } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" - case 1'1 - assign \src_r0$next \src1_i - end - sync init - update \src_r0 64'0000000000000000000000000000000000000000000000000000000000000000 - sync posedge \coresync_clk - update \src_r0 \src_r0$next - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" - wire width 64 \src_r1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" - wire width 64 \src_r1$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - wire width 64 $83 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - cell $mux $84 - parameter \WIDTH 64 - connect \A \src_r1 - connect \B \src_or_imm - connect \S \src_sel - connect \Y $83 - end - process $group_46 - assign \alu_branch0_fast2$2 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \alu_branch0_fast2$2 $83 - sync init - end - process $group_47 - assign \src_r1$next \src_r1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" - switch { \src_sel } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" - case 1'1 - assign \src_r1$next \src_or_imm - end - sync init - update \src_r1 64'0000000000000000000000000000000000000000000000000000000000000000 - sync posedge \coresync_clk - update \src_r1 \src_r1$next - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" - wire width 4 \src_r2 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" - wire width 4 \src_r2$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - wire width 4 $85 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - cell $mux $86 - parameter \WIDTH 4 - connect \A \src_r2 - connect \B \src3_i - connect \S \src_l_q_src [2] - connect \Y $85 - end - process $group_48 - assign \alu_branch0_cr_a 4'0000 - assign \alu_branch0_cr_a $85 - sync init - end - process $group_49 - assign \src_r2$next \src_r2 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" - switch { \src_l_q_src [2] } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" - case 1'1 - assign \src_r2$next \src3_i - end - sync init - update \src_r2 4'0000 - sync posedge \coresync_clk - update \src_r2 \src_r2$next - end - process $group_50 - assign \alu_branch0_p_valid_i 1'0 - assign \alu_branch0_p_valid_i \alui_l_q_alui - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:327" - wire width 1 $87 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:327" - cell $and $88 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \alu_branch0_p_ready_o - connect \B \alui_l_q_alui - connect \Y $87 - end - process $group_51 - assign \alui_l_r_alui$next \alui_l_r_alui - assign \alui_l_r_alui$next $87 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \alui_l_r_alui$next 1'1 - end - sync init - update \alui_l_r_alui 1'1 - sync posedge \coresync_clk - update \alui_l_r_alui \alui_l_r_alui$next - end - process $group_52 - assign \alui_l_s_alui 1'0 - assign \alui_l_s_alui \all_rd_pulse - sync init - end - process $group_53 - assign \alu_branch0_n_ready_i 1'0 - assign \alu_branch0_n_ready_i \alu_l_q_alu - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:334" - wire width 1 $89 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:334" - cell $and $90 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \alu_branch0_n_valid_o - connect \B \alu_l_q_alu - connect \Y $89 - end - process $group_54 - assign \alu_l_r_alu$next \alu_l_r_alu - assign \alu_l_r_alu$next $89 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \alu_l_r_alu$next 1'1 - end - sync init - update \alu_l_r_alu 1'1 - sync posedge \coresync_clk - update \alu_l_r_alu \alu_l_r_alu$next - end - process $group_55 - assign \alu_l_s_alu 1'0 - assign \alu_l_s_alu \all_rd_pulse - sync init - end - process $group_56 - assign \cu_busy_o 1'0 - assign \cu_busy_o \opc_l_q_opc - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - wire width 3 $91 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - cell $and $92 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A \src_l_q_src - connect \B { \cu_busy_o \cu_busy_o \cu_busy_o } - connect \Y $91 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:173" - wire width 1 $93 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:173" - cell $not $94 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \alu_branch0_br_op__imm_data__ok - connect \Y $93 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - wire width 3 $95 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - cell $and $96 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A $91 - connect \B { 1'1 $93 1'1 } - connect \Y $95 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - wire width 3 $97 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - cell $not $98 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A \cu_rdmaskn_i - connect \Y $97 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - wire width 3 $99 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - cell $and $100 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A $95 - connect \B $97 - connect \Y $99 - end - process $group_57 - assign \cu_rd__rel_o 3'000 - assign \cu_rd__rel_o $99 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:102" - wire width 1 \cu_shadown_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" - wire width 1 $101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" - cell $and $102 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cu_busy_o - connect \B \cu_shadown_i - connect \Y $101 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" - wire width 1 $103 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" - cell $and $104 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cu_busy_o - connect \B \cu_shadown_i - connect \Y $103 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" - wire width 1 $105 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" - cell $and $106 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cu_busy_o - connect \B \cu_shadown_i - connect \Y $105 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351" - wire width 3 $107 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351" - cell $and $108 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A \req_l_q_req - connect \B { $101 $103 $105 } - connect \Y $107 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351" - wire width 3 $109 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351" - cell $and $110 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A $107 - connect \B \cu_wrmask_o - connect \Y $109 - end - process $group_58 - assign \cu_wr__rel_o 3'000 - assign \cu_wr__rel_o $109 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - wire width 1 $111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - cell $and $112 - parameter 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- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 output 22 \o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 23 \o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 output 24 \fast1$10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 25 \fast1_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 output 26 \fast2$11 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 27 \fast2_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 output 28 \nia - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 29 \nia_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 output 30 \msr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 31 \msr_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:133" - wire width 5 \to - process $group_0 - assign \to 5'00000 - assign \to { \trap_op__insn [25] \trap_op__insn [24] \trap_op__insn [23] \trap_op__insn [22] \trap_op__insn [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:137" - wire width 64 \a_s - process $group_1 - assign \a_s 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:144" - switch { \trap_op__is_32bit } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:144" - case 1'1 - assign \a_s { { \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] \ra [31:0] [31] } \ra [31:0] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:149" - case - assign \a_s \ra - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:138" - wire width 64 \b_s - process $group_2 - assign \b_s 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:144" - switch { \trap_op__is_32bit } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:144" - case 1'1 - assign \b_s { { \rb [31:0] [31] \rb [31:0] [31] \rb [31:0] [31] \rb [31:0] [31] \rb [31:0] [31] \rb [31:0] [31] \rb [31:0] [31] \rb [31:0] [31] \rb [31:0] [31] \rb [31:0] [31] \rb [31:0] [31] \rb [31:0] [31] \rb [31:0] [31] \rb [31:0] [31] \rb [31:0] [31] \rb [31:0] [31] \rb [31:0] [31] \rb [31:0] [31] \rb [31:0] [31] \rb [31:0] [31] \rb [31:0] [31] \rb [31:0] [31] \rb [31:0] [31] \rb [31:0] [31] \rb [31:0] [31] \rb [31:0] [31] \rb [31:0] [31] \rb [31:0] [31] \rb [31:0] [31] \rb [31:0] [31] \rb [31:0] [31] \rb [31:0] [31] } \rb [31:0] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:149" - case - assign \b_s \rb - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:140" - wire width 64 \a - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:265" - wire width 64 $12 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:265" - cell $pos $13 - parameter \A_SIGNED 0 - parameter \A_WIDTH 32 - parameter \Y_WIDTH 64 - connect \A \ra [31:0] - connect \Y $12 - end - process $group_3 - assign \a 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:144" - switch { \trap_op__is_32bit } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:144" - case 1'1 - assign \a $12 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:149" - case - assign \a \ra - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:141" - wire width 64 \b - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:265" - wire width 64 $14 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:265" - cell $pos $15 - parameter \A_SIGNED 0 - parameter \A_WIDTH 32 - parameter \Y_WIDTH 64 - connect \A \rb [31:0] - connect \Y $14 - end - process $group_4 - assign \b 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:144" - switch { \trap_op__is_32bit } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:144" - case 1'1 - assign \b $14 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:149" - case - assign \b \rb - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:156" - wire width 1 \lt_s - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:162" - wire width 1 $16 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:162" - cell $lt $17 - parameter \A_SIGNED 1 - parameter \A_WIDTH 64 - parameter \B_SIGNED 1 - parameter \B_WIDTH 64 - parameter \Y_WIDTH 1 - connect \A \a_s - connect \B \b_s - connect \Y $16 - end - process $group_5 - assign \lt_s 1'0 - assign \lt_s $16 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:157" - wire width 1 \gt_s - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:163" - wire width 1 $18 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:163" - cell $gt $19 - parameter \A_SIGNED 1 - parameter \A_WIDTH 64 - parameter \B_SIGNED 1 - parameter \B_WIDTH 64 - parameter \Y_WIDTH 1 - connect \A \a_s - connect \B \b_s - connect \Y $18 - end - process $group_6 - assign \gt_s 1'0 - assign \gt_s $18 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:158" - wire width 1 \lt_u - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:164" - wire width 1 $20 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:164" - cell $lt $21 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \B_SIGNED 0 - parameter \B_WIDTH 64 - parameter \Y_WIDTH 1 - connect \A \a - connect \B \b - connect \Y $20 - end - process $group_7 - assign \lt_u 1'0 - assign \lt_u $20 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:159" - wire width 1 \gt_u - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:165" - wire width 1 $22 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:165" - cell $gt $23 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \B_SIGNED 0 - parameter \B_WIDTH 64 - parameter \Y_WIDTH 1 - connect \A \a - connect \B \b - connect \Y $22 - end - process $group_8 - assign \gt_u 1'0 - assign \gt_u $22 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:160" - wire width 1 \equal - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:166" - wire width 1 $24 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:166" - cell $eq $25 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \B_SIGNED 0 - parameter \B_WIDTH 64 - parameter \Y_WIDTH 1 - connect \A \a - connect \B \b - connect \Y $24 - end - process $group_9 - assign \equal 1'0 - assign \equal $24 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:170" - wire width 5 \trap_bits - process $group_10 - assign \trap_bits 5'00000 - assign \trap_bits { \lt_s \gt_s \equal \lt_u \gt_u } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:175" - wire width 1 \should_trap - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:176" - wire width 1 $26 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:176" - wire width 5 $27 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:176" - cell $and $28 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 5 - connect \A \trap_bits - connect \B \to - connect \Y $27 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:176" - cell $reduce_or $29 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A $27 - connect \Y $26 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:176" - wire width 1 $30 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:176" - cell $reduce_or $31 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A \trap_op__traptype - connect \Y $30 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:176" - wire width 1 $32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:176" - cell $or $33 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $26 - connect \B $30 - connect \Y $32 - end - process $group_11 - assign \should_trap 1'0 - assign \should_trap $32 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:188" - wire width 64 $34 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:188" - wire width 20 $35 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:188" - cell $sshl $36 - parameter \A_SIGNED 0 - parameter \A_WIDTH 13 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 20 - connect \A \trap_op__trapaddr - connect \B 3'100 - connect \Y $35 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:188" - cell $pos $37 - parameter \A_SIGNED 0 - parameter \A_WIDTH 20 - parameter \Y_WIDTH 64 - connect \A $35 - connect \Y $34 - end - process $group_12 - assign \nia 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:179" - switch \trap_op__insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:184" - attribute \nmigen.decoding "OP_TRAP/63" - case 7'0111111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:186" - switch { \should_trap } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:186" - case 1'1 - assign \nia $34 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:214" - attribute \nmigen.decoding "OP_MTMSRD/72|OP_MTMSR/74" - case 7'1001000, 7'1001010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:256" - attribute \nmigen.decoding "OP_MFMSR/71" - case 7'1000111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:264" - attribute \nmigen.decoding "OP_RFID/70" - case 7'1000110 - assign \nia { { { } \fast1 [63:2] } 2'00 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:295" - attribute \nmigen.decoding "OP_SC/73" - case 7'1001001 - assign \nia 64'0000000000000000000000000000000000000000000000000000110000000000 - end - sync init - end - process $group_13 - assign \nia_ok 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:179" - switch \trap_op__insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:184" - attribute \nmigen.decoding "OP_TRAP/63" - case 7'0111111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:186" - switch { \should_trap } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:186" - case 1'1 - assign \nia_ok 1'1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:214" - attribute \nmigen.decoding "OP_MTMSRD/72|OP_MTMSR/74" - case 7'1001000, 7'1001010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:256" - attribute \nmigen.decoding "OP_MFMSR/71" - case 7'1000111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:264" - attribute \nmigen.decoding "OP_RFID/70" - case 7'1000110 - assign \nia_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:295" - attribute \nmigen.decoding "OP_SC/73" - case 7'1001001 - assign \nia_ok 1'1 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:306" - wire width 65 $38 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:306" - wire width 65 $39 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:306" - cell $add $40 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 65 - connect \A \trap_op__cia - connect \B 3'100 - connect \Y $39 - end - connect $38 $39 - process $group_14 - assign \fast1$10 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:179" - switch \trap_op__insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:184" - attribute \nmigen.decoding "OP_TRAP/63" - case 7'0111111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:186" - switch { \should_trap } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:186" - case 1'1 - assign \fast1$10 \trap_op__cia - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:214" - attribute \nmigen.decoding "OP_MTMSRD/72|OP_MTMSR/74" - case 7'1001000, 7'1001010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:256" - attribute \nmigen.decoding "OP_MFMSR/71" - case 7'1000111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:264" - attribute \nmigen.decoding "OP_RFID/70" - case 7'1000110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:295" - attribute \nmigen.decoding "OP_SC/73" - case 7'1001001 - assign \fast1$10 $38 [63:0] - end - sync init - end - process $group_15 - assign \fast1_ok 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:179" - switch \trap_op__insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:184" - attribute \nmigen.decoding "OP_TRAP/63" - case 7'0111111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:186" - switch { \should_trap } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:186" - case 1'1 - assign \fast1_ok 1'1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:214" - attribute \nmigen.decoding "OP_MTMSRD/72|OP_MTMSR/74" - case 7'1001000, 7'1001010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:256" - attribute \nmigen.decoding "OP_MFMSR/71" - case 7'1000111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:264" - attribute \nmigen.decoding "OP_RFID/70" - case 7'1000110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:295" - attribute \nmigen.decoding "OP_SC/73" - case 7'1001001 - assign \fast1_ok 1'1 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:189" - wire width 1 $41 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:189" - cell $eq $42 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \trap_op__traptype - connect \B 1'0 - connect \Y $41 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" - wire width 1 $43 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:192" - wire width 7 $44 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:192" - cell $and $45 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 7 - connect \A \trap_op__traptype - connect \B 2'10 - connect \Y $44 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" - cell $reduce_bool $46 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A $44 - connect \Y $43 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" - wire width 1 $47 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:194" - wire width 7 $48 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:194" - cell $and $49 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 7 - connect \A \trap_op__traptype - connect \B 1'1 - connect \Y $48 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" - cell $reduce_bool $50 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A $48 - connect \Y $47 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" - wire width 1 $51 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:196" - wire width 7 $52 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:196" - cell $and $53 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 7 - connect \A \trap_op__traptype - connect \B 4'1000 - connect \Y $52 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" - cell $reduce_bool $54 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A $52 - connect \Y $51 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" - wire width 1 $55 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:204" - wire width 7 $56 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:204" - cell $and $57 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 7 - connect \A \trap_op__traptype - connect \B 7'1000000 - connect \Y $56 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" - cell $reduce_bool $58 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A $56 - connect \Y $55 - end - process $group_16 - assign \fast2$11 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:179" - switch \trap_op__insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:184" - attribute \nmigen.decoding "OP_TRAP/63" - case 7'0111111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:186" - switch { \should_trap } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:186" - case 1'1 - assign \fast2$11 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \fast2$11 [15:0] \trap_op__msr [15:0] - assign \fast2$11 [26:22] \trap_op__msr [26:22] - assign \fast2$11 [63:31] \trap_op__msr [63:31] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:189" - switch { $41 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:189" - case 1'1 - assign \fast2$11 [17] 1'1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:192" - switch { $43 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:192" - case 1'1 - assign \fast2$11 [18] 1'1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:194" - switch { $47 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:194" - case 1'1 - assign \fast2$11 [20] 1'1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:196" - switch { $51 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:196" - case 1'1 - assign \fast2$11 [16] 1'1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:204" - switch { $55 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:204" - case 1'1 - assign \fast2$11 [19] 1'1 - end - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:214" - attribute \nmigen.decoding "OP_MTMSRD/72|OP_MTMSR/74" - case 7'1001000, 7'1001010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:256" - attribute \nmigen.decoding "OP_MFMSR/71" - case 7'1000111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:264" - attribute \nmigen.decoding "OP_RFID/70" - case 7'1000110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:295" - attribute \nmigen.decoding "OP_SC/73" - case 7'1001001 - assign \fast2$11 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \fast2$11 [15:0] \trap_op__msr [15:0] - assign \fast2$11 [26:22] \trap_op__msr [26:22] - assign \fast2$11 [63:31] \trap_op__msr [63:31] - end - sync init - end - process $group_17 - assign \fast2_ok 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:179" - switch \trap_op__insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:184" - attribute \nmigen.decoding "OP_TRAP/63" - case 7'0111111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:186" - switch { \should_trap } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:186" - case 1'1 - assign \fast2_ok 1'1 - assign \fast2_ok 1'1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:214" - attribute \nmigen.decoding "OP_MTMSRD/72|OP_MTMSR/74" - case 7'1001000, 7'1001010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:256" - attribute \nmigen.decoding "OP_MFMSR/71" - case 7'1000111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:264" - attribute \nmigen.decoding "OP_RFID/70" - case 7'1000110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:295" - attribute \nmigen.decoding "OP_SC/73" - case 7'1001001 - assign \fast2_ok 1'1 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 65 $59 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - cell $pos $60 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \Y_WIDTH 65 - connect \A \trap_op__msr - connect \Y $59 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:225" - wire width 1 $61 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:225" - cell $eq $62 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A \trap_op__insn_type - connect \B 7'1001000 - connect \Y $61 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:231" - wire width 1 $63 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:231" - cell $eq $64 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \trap_op__msr [34:32] - connect \B 3'010 - connect \Y $63 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:232" - wire width 1 $65 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:232" - cell $eq $66 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \ra [34:32] - connect \B 3'000 - connect \Y $65 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:232" - wire width 1 $67 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:232" - cell $and $68 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $63 - connect \B $65 - connect \Y $67 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:247" - wire width 1 $69 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:247" - cell $not $70 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \trap_op__msr [60] - connect \Y $69 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:273" - wire width 1 $71 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:273" - cell $not $72 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \trap_op__insn [9] - connect \Y $71 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:286" - wire width 1 $73 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:286" - cell $eq $74 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \trap_op__msr [34:32] - connect \B 3'010 - connect \Y $73 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:287" - wire width 1 $75 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:287" - cell $eq $76 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \fast2 [34:32] - connect \B 3'000 - connect \Y $75 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:287" - wire width 1 $77 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:287" - cell $and $78 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $73 - connect \B $75 - connect \Y $77 - end - process $group_18 - assign \msr 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \msr_ok 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:179" - switch \trap_op__insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:184" - attribute \nmigen.decoding "OP_TRAP/63" - case 7'0111111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:186" - switch { \should_trap } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:186" - case 1'1 - assign \msr \trap_op__msr - assign \msr [63] 1'1 - assign \msr [15] 1'0 - assign \msr [14] 1'0 - assign \msr [5] 1'0 - assign \msr [4] 1'0 - assign \msr [1] 1'0 - assign \msr [0] 1'1 - assign \msr [11] 1'0 - assign \msr [8] 1'0 - assign \msr [23] 1'0 - assign \msr [32] 1'0 - assign \msr [25] 1'0 - assign \msr [13] 1'0 - assign \msr [3] 1'0 - assign \msr [10] 1'0 - assign \msr [9] 1'0 - assign \msr [58] 1'0 - assign \msr_ok 1'1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:214" - attribute \nmigen.decoding "OP_MTMSRD/72|OP_MTMSR/74" - case 7'1001000, 7'1001010 - assign { \msr_ok \msr } $59 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:218" - switch { { \trap_op__insn [21] } } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:218" - case 1'1 - assign \msr [1] \ra [1] - assign \msr [15] \ra [15] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:222" - case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:225" - switch { $61 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:225" - case 1'1 - assign \msr [11:1] \ra [11:1] - assign \msr [59:13] \ra [59:13] - assign \msr [63:61] \ra [63:61] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:232" - switch { $67 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:232" - case 1'1 - assign \msr [34:32] \trap_op__msr [34:32] - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:235" - case - assign \msr [11:1] \ra [11:1] - assign \msr [31:13] \ra [31:13] - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:48" - switch { \msr [14] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:48" - case 1'1 - assign \msr [15] 1'1 - assign \msr [5] 1'1 - assign \msr [4] 1'1 - end - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:247" - switch { $69 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:247" - case 1'1 - assign \msr [60] \trap_op__msr [60] - assign \msr [12] \trap_op__msr [12] - end - switch { } - case - assign \msr_ok 1'1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:256" - attribute \nmigen.decoding "OP_MFMSR/71" - case 7'1000111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:264" - attribute \nmigen.decoding "OP_RFID/70" - case 7'1000110 - assign \msr [15:0] \fast2 [15:0] - assign \msr [26:22] \fast2 [26:22] - assign \msr [63:31] \fast2 [63:31] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:273" - switch { $71 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:273" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:274" - switch { \trap_op__msr [60] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:274" - case 1'1 - assign { \msr_ok \msr } [12] \fast2 [12] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:276" - case - assign { \msr_ok \msr } [12] \trap_op__msr [12] - end - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:48" - switch { \msr [14] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:48" - case 1'1 - assign \msr [15] 1'1 - assign \msr [5] 1'1 - assign \msr [4] 1'1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:287" - switch { $77 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:287" - case 1'1 - assign \msr [34:32] \trap_op__msr [34:32] - end - switch { } - case - assign \msr_ok 1'1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:295" - attribute \nmigen.decoding "OP_SC/73" - case 7'1001001 - assign \msr \trap_op__msr - assign \msr [63] 1'1 - assign \msr [15] 1'0 - assign \msr [14] 1'0 - assign \msr [5] 1'0 - assign \msr [4] 1'0 - assign \msr [1] 1'0 - assign \msr [0] 1'1 - assign \msr [11] 1'0 - assign \msr [8] 1'0 - assign \msr [23] 1'0 - assign \msr [32] 1'0 - assign \msr [25] 1'0 - assign \msr [13] 1'0 - assign \msr [3] 1'0 - assign \msr [10] 1'0 - assign \msr [9] 1'0 - assign \msr [58] 1'0 - assign \msr_ok 1'1 - end - sync init - end - process $group_20 - assign \o 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:179" - switch \trap_op__insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:184" - attribute \nmigen.decoding "OP_TRAP/63" - case 7'0111111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:214" - attribute \nmigen.decoding "OP_MTMSRD/72|OP_MTMSR/74" - case 7'1001000, 7'1001010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:256" - attribute \nmigen.decoding "OP_MFMSR/71" - case 7'1000111 - assign \o \trap_op__msr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:264" - attribute \nmigen.decoding "OP_RFID/70" - case 7'1000110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:295" - attribute \nmigen.decoding "OP_SC/73" - case 7'1001001 - end - sync init - end - process $group_21 - assign \o_ok 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:179" - switch \trap_op__insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:184" - attribute \nmigen.decoding "OP_TRAP/63" - case 7'0111111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:214" - attribute \nmigen.decoding "OP_MTMSRD/72|OP_MTMSR/74" - case 7'1001000, 7'1001010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:256" - attribute \nmigen.decoding "OP_MFMSR/71" - case 7'1000111 - assign \o_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:264" - attribute \nmigen.decoding "OP_RFID/70" - case 7'1000110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/trap/main_stage.py:295" - attribute \nmigen.decoding "OP_SC/73" - case 7'1001001 - end - sync init - end - process $group_22 - assign \muxid$1 2'00 - assign \muxid$1 \muxid - sync init - end - process $group_23 - assign \trap_op__insn_type$2 7'0000000 - assign \trap_op__fn_unit$3 11'00000000000 - assign \trap_op__insn$4 32'00000000000000000000000000000000 - assign \trap_op__msr$5 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \trap_op__cia$6 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \trap_op__is_32bit$7 1'0 - assign \trap_op__traptype$8 7'0000000 - assign \trap_op__trapaddr$9 13'0000000000000 - assign { \trap_op__trapaddr$9 \trap_op__traptype$8 \trap_op__is_32bit$7 \trap_op__cia$6 \trap_op__msr$5 \trap_op__insn$4 \trap_op__fn_unit$3 \trap_op__insn_type$2 } { \trap_op__trapaddr \trap_op__traptype \trap_op__is_32bit \trap_op__cia \trap_op__msr \trap_op__insn \trap_op__fn_unit \trap_op__insn_type } - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.trap0.alu_trap0.pipe" -module \pipe$32 - attribute \src "simple/issuer.py:141" - wire width 1 input 0 \coresync_clk - attribute \src "simple/issuer.py:141" - wire width 1 input 1 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" - wire width 1 input 2 \p_valid_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" - wire width 1 output 3 \p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 input 4 \muxid - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute 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\enum_value_00001000000 "CR" - attribute \enum_value_00010000000 "TRAP" - attribute \enum_value_00100000000 "MUL" - attribute \enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 \main_trap_op__fn_unit$14 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \main_trap_op__insn$15 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \main_trap_op__msr$16 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \main_trap_op__cia$17 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \main_trap_op__is_32bit$18 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \main_trap_op__traptype$19 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 \main_trap_op__trapaddr$20 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 \main_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \main_o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 \main_fast1$21 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \main_fast1_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 \main_fast2$22 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \main_fast2_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 \main_nia - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \main_nia_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 \main_msr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \main_msr_ok - cell \main$35 \main - connect \muxid \main_muxid - connect \trap_op__insn_type \main_trap_op__insn_type - connect \trap_op__fn_unit \main_trap_op__fn_unit - connect \trap_op__insn \main_trap_op__insn - connect \trap_op__msr \main_trap_op__msr - connect \trap_op__cia \main_trap_op__cia - connect \trap_op__is_32bit \main_trap_op__is_32bit - connect \trap_op__traptype \main_trap_op__traptype - connect \trap_op__trapaddr \main_trap_op__trapaddr - connect \ra \main_ra - connect \rb \main_rb - connect \fast1 \main_fast1 - connect \fast2 \main_fast2 - connect \muxid$1 \main_muxid$12 - connect \trap_op__insn_type$2 \main_trap_op__insn_type$13 - connect \trap_op__fn_unit$3 \main_trap_op__fn_unit$14 - connect \trap_op__insn$4 \main_trap_op__insn$15 - connect \trap_op__msr$5 \main_trap_op__msr$16 - connect \trap_op__cia$6 \main_trap_op__cia$17 - connect \trap_op__is_32bit$7 \main_trap_op__is_32bit$18 - connect \trap_op__traptype$8 \main_trap_op__traptype$19 - connect \trap_op__trapaddr$9 \main_trap_op__trapaddr$20 - connect \o \main_o - connect \o_ok \main_o_ok - connect \fast1$10 \main_fast1$21 - connect \fast1_ok \main_fast1_ok - connect \fast2$11 \main_fast2$22 - connect \fast2_ok \main_fast2_ok - connect \nia \main_nia - connect \nia_ok \main_nia_ok - connect \msr \main_msr - connect \msr_ok \main_msr_ok - end - process $group_0 - assign \main_muxid 2'00 - assign \main_muxid \muxid - sync init - end - process $group_1 - assign \main_trap_op__insn_type 7'0000000 - assign \main_trap_op__fn_unit 11'00000000000 - assign \main_trap_op__insn 32'00000000000000000000000000000000 - assign \main_trap_op__msr 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \main_trap_op__cia 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \main_trap_op__is_32bit 1'0 - assign \main_trap_op__traptype 7'0000000 - assign \main_trap_op__trapaddr 13'0000000000000 - assign { \main_trap_op__trapaddr \main_trap_op__traptype \main_trap_op__is_32bit \main_trap_op__cia \main_trap_op__msr \main_trap_op__insn \main_trap_op__fn_unit \main_trap_op__insn_type } { \trap_op__trapaddr \trap_op__traptype \trap_op__is_32bit \trap_op__cia \trap_op__msr \trap_op__insn \trap_op__fn_unit \trap_op__insn_type } - sync init - end - process $group_9 - assign \main_ra 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \main_ra \ra - sync init - end - process $group_10 - assign \main_rb 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \main_rb \rb - sync init - end - process $group_11 - assign \main_fast1 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \main_fast1 \fast1 - sync init - end - process $group_12 - assign \main_fast2 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \main_fast2 \fast2 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:621" - wire width 1 \p_valid_i$23 - process $group_13 - assign \p_valid_i$23 1'0 - assign \p_valid_i$23 \p_valid_i - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:619" - wire width 1 \n_i_rdy_data - process $group_14 - assign \n_i_rdy_data 1'0 - assign \n_i_rdy_data \n_ready_i - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" - wire width 1 \p_valid_i_p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" - wire width 1 $24 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" - cell $and $25 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \p_valid_i$23 - connect \B \p_ready_o - connect \Y $24 - end - process $group_15 - assign \p_valid_i_p_ready_o 1'0 - assign \p_valid_i_p_ready_o $24 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \muxid$26 - process $group_16 - assign \muxid$26 2'00 - assign \muxid$26 \main_muxid$12 - sync init - end - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \trap_op__insn_type$27 - attribute \enum_base_type "Function" - attribute \enum_value_00000000000 "NONE" - attribute \enum_value_00000000010 "ALU" - attribute \enum_value_00000000100 "LDST" - attribute \enum_value_00000001000 "SHIFT_ROT" - attribute \enum_value_00000010000 "LOGICAL" - attribute \enum_value_00000100000 "BRANCH" - attribute \enum_value_00001000000 "CR" - attribute \enum_value_00010000000 "TRAP" - attribute \enum_value_00100000000 "MUL" - attribute \enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 \trap_op__fn_unit$28 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \trap_op__insn$29 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \trap_op__msr$30 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \trap_op__cia$31 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \trap_op__is_32bit$32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \trap_op__traptype$33 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 \trap_op__trapaddr$34 - process $group_17 - assign \trap_op__insn_type$27 7'0000000 - assign \trap_op__fn_unit$28 11'00000000000 - assign \trap_op__insn$29 32'00000000000000000000000000000000 - assign \trap_op__msr$30 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \trap_op__cia$31 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \trap_op__is_32bit$32 1'0 - assign \trap_op__traptype$33 7'0000000 - assign \trap_op__trapaddr$34 13'0000000000000 - assign { \trap_op__trapaddr$34 \trap_op__traptype$33 \trap_op__is_32bit$32 \trap_op__cia$31 \trap_op__msr$30 \trap_op__insn$29 \trap_op__fn_unit$28 \trap_op__insn_type$27 } { \main_trap_op__trapaddr$20 \main_trap_op__traptype$19 \main_trap_op__is_32bit$18 \main_trap_op__cia$17 \main_trap_op__msr$16 \main_trap_op__insn$15 \main_trap_op__fn_unit$14 \main_trap_op__insn_type$13 } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 \o$35 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \o_ok$36 - process $group_25 - assign \o$35 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \o_ok$36 1'0 - assign { \o_ok$36 \o$35 } { \main_o_ok \main_o } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 \fast1$37 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \fast1_ok$38 - process $group_27 - assign \fast1$37 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \fast1_ok$38 1'0 - assign { \fast1_ok$38 \fast1$37 } { \main_fast1_ok \main_fast1$21 } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 \fast2$39 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \fast2_ok$40 - process $group_29 - assign \fast2$39 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \fast2_ok$40 1'0 - assign { \fast2_ok$40 \fast2$39 } { \main_fast2_ok \main_fast2$22 } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 \nia$41 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \nia_ok$42 - process $group_31 - assign \nia$41 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \nia_ok$42 1'0 - assign { \nia_ok$42 \nia$41 } { \main_nia_ok \main_nia } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 \msr$43 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \msr_ok$44 - process $group_33 - assign \msr$43 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \msr_ok$44 1'0 - assign { \msr_ok$44 \msr$43 } { \main_msr_ok \main_msr } - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615" - wire width 1 \r_busy - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615" - wire width 1 \r_busy$next - process $group_35 - assign \r_busy$next \r_busy - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign \r_busy$next 1'1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign \r_busy$next 1'0 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \r_busy$next 1'0 - end - sync init - update \r_busy 1'0 - sync posedge \coresync_clk - update \r_busy \r_busy$next - end - process $group_36 - assign \muxid$1$next \muxid$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign \muxid$1$next \muxid$26 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign \muxid$1$next \muxid$26 - end - sync init - update \muxid$1 2'00 - sync posedge \coresync_clk - update \muxid$1 \muxid$1$next - end - process $group_37 - assign \trap_op__insn_type$2$next \trap_op__insn_type$2 - assign \trap_op__fn_unit$3$next \trap_op__fn_unit$3 - assign \trap_op__insn$4$next \trap_op__insn$4 - assign \trap_op__msr$5$next \trap_op__msr$5 - assign \trap_op__cia$6$next \trap_op__cia$6 - assign \trap_op__is_32bit$7$next \trap_op__is_32bit$7 - assign \trap_op__traptype$8$next \trap_op__traptype$8 - assign \trap_op__trapaddr$9$next \trap_op__trapaddr$9 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign { \trap_op__trapaddr$9$next \trap_op__traptype$8$next \trap_op__is_32bit$7$next \trap_op__cia$6$next \trap_op__msr$5$next \trap_op__insn$4$next \trap_op__fn_unit$3$next \trap_op__insn_type$2$next } { \trap_op__trapaddr$34 \trap_op__traptype$33 \trap_op__is_32bit$32 \trap_op__cia$31 \trap_op__msr$30 \trap_op__insn$29 \trap_op__fn_unit$28 \trap_op__insn_type$27 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign { \trap_op__trapaddr$9$next \trap_op__traptype$8$next \trap_op__is_32bit$7$next \trap_op__cia$6$next \trap_op__msr$5$next \trap_op__insn$4$next \trap_op__fn_unit$3$next \trap_op__insn_type$2$next } { \trap_op__trapaddr$34 \trap_op__traptype$33 \trap_op__is_32bit$32 \trap_op__cia$31 \trap_op__msr$30 \trap_op__insn$29 \trap_op__fn_unit$28 \trap_op__insn_type$27 } - end - sync init - update \trap_op__insn_type$2 7'0000000 - update \trap_op__fn_unit$3 11'00000000000 - update \trap_op__insn$4 32'00000000000000000000000000000000 - update \trap_op__msr$5 64'0000000000000000000000000000000000000000000000000000000000000000 - update \trap_op__cia$6 64'0000000000000000000000000000000000000000000000000000000000000000 - update \trap_op__is_32bit$7 1'0 - update \trap_op__traptype$8 7'0000000 - update \trap_op__trapaddr$9 13'0000000000000 - sync posedge \coresync_clk - update \trap_op__insn_type$2 \trap_op__insn_type$2$next - update \trap_op__fn_unit$3 \trap_op__fn_unit$3$next - update \trap_op__insn$4 \trap_op__insn$4$next - update \trap_op__msr$5 \trap_op__msr$5$next - update \trap_op__cia$6 \trap_op__cia$6$next - update \trap_op__is_32bit$7 \trap_op__is_32bit$7$next - update \trap_op__traptype$8 \trap_op__traptype$8$next - update \trap_op__trapaddr$9 \trap_op__trapaddr$9$next - end - process $group_45 - assign \o$next \o - assign \o_ok$next \o_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign { \o_ok$next \o$next } { \o_ok$36 \o$35 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign { \o_ok$next \o$next } { \o_ok$36 \o$35 } - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \o_ok$next 1'0 - end - sync init - update \o 64'0000000000000000000000000000000000000000000000000000000000000000 - update \o_ok 1'0 - sync posedge \coresync_clk - update \o \o$next - update \o_ok \o_ok$next - end - process $group_47 - assign \fast1$10$next \fast1$10 - assign \fast1_ok$next \fast1_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign { \fast1_ok$next \fast1$10$next } { \fast1_ok$38 \fast1$37 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign { \fast1_ok$next \fast1$10$next } { \fast1_ok$38 \fast1$37 } - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \fast1_ok$next 1'0 - end - sync init - update \fast1$10 64'0000000000000000000000000000000000000000000000000000000000000000 - update \fast1_ok 1'0 - sync posedge \coresync_clk - update \fast1$10 \fast1$10$next - update \fast1_ok \fast1_ok$next - end - process $group_49 - assign \fast2$11$next \fast2$11 - assign \fast2_ok$next \fast2_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign { \fast2_ok$next \fast2$11$next } { \fast2_ok$40 \fast2$39 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign { \fast2_ok$next \fast2$11$next } { \fast2_ok$40 \fast2$39 } - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \fast2_ok$next 1'0 - end - sync init - update \fast2$11 64'0000000000000000000000000000000000000000000000000000000000000000 - update \fast2_ok 1'0 - sync posedge \coresync_clk - update \fast2$11 \fast2$11$next - update \fast2_ok \fast2_ok$next - end - process $group_51 - assign \nia$next \nia - assign \nia_ok$next \nia_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign { \nia_ok$next \nia$next } { \nia_ok$42 \nia$41 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign { \nia_ok$next \nia$next } { \nia_ok$42 \nia$41 } - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \nia_ok$next 1'0 - end - sync init - update \nia 64'0000000000000000000000000000000000000000000000000000000000000000 - update \nia_ok 1'0 - sync posedge \coresync_clk - update \nia \nia$next - update \nia_ok \nia_ok$next - end - process $group_53 - assign \msr$next \msr - assign \msr_ok$next \msr_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign { \msr_ok$next \msr$next } { \msr_ok$44 \msr$43 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign { \msr_ok$next \msr$next } { \msr_ok$44 \msr$43 } - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \msr_ok$next 1'0 - end - sync init - update \msr 64'0000000000000000000000000000000000000000000000000000000000000000 - update \msr_ok 1'0 - sync posedge \coresync_clk - update \msr \msr$next - update \msr_ok \msr_ok$next - end - process $group_55 - assign \n_valid_o 1'0 - assign \n_valid_o \r_busy - sync init - end - process $group_56 - assign \p_ready_o 1'0 - assign \p_ready_o \n_i_rdy_data - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.trap0.alu_trap0" -module \alu_trap0 - attribute \src "simple/issuer.py:141" - wire width 1 input 0 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 1 \o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 2 \fast1_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 3 \fast2_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 4 \nia_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 5 \msr_ok - attribute \src "simple/issuer.py:141" - wire width 1 input 6 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" - wire width 1 output 7 \n_valid_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" - wire width 1 input 8 \n_ready_i - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 input 9 \trap_op__insn_type - attribute \enum_base_type "Function" - attribute \enum_value_00000000000 "NONE" - attribute \enum_value_00000000010 "ALU" - attribute \enum_value_00000000100 "LDST" - attribute \enum_value_00000001000 "SHIFT_ROT" - attribute \enum_value_00000010000 "LOGICAL" - attribute \enum_value_00000100000 "BRANCH" - attribute \enum_value_00001000000 "CR" - attribute \enum_value_00010000000 "TRAP" - attribute \enum_value_00100000000 "MUL" - attribute \enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 input 10 \trap_op__fn_unit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 input 11 \trap_op__insn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 input 12 \trap_op__msr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 input 13 \trap_op__cia - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 14 \trap_op__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 input 15 \trap_op__traptype - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 input 16 \trap_op__trapaddr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 output 17 \o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 output 18 \fast1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 output 19 \fast2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 output 20 \nia - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 output 21 \msr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 22 \ra - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 23 \rb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 24 \fast1$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 25 \fast2$2 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" - wire width 1 input 26 \p_valid_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" - wire width 1 output 27 \p_ready_o - cell \p$30 \p - connect \p_valid_i \p_valid_i - connect \p_ready_o \p_ready_o - end - cell \n$31 \n - connect \n_valid_o \n_valid_o - connect \n_ready_i \n_ready_i - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" - wire width 1 \pipe_p_valid_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" - wire width 1 \pipe_p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \pipe_muxid - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \pipe_trap_op__insn_type - attribute \enum_base_type "Function" - attribute \enum_value_00000000000 "NONE" - attribute \enum_value_00000000010 "ALU" - attribute \enum_value_00000000100 "LDST" - attribute \enum_value_00000001000 "SHIFT_ROT" - attribute \enum_value_00000010000 "LOGICAL" - attribute \enum_value_00000100000 "BRANCH" - attribute \enum_value_00001000000 "CR" - attribute \enum_value_00010000000 "TRAP" - attribute \enum_value_00100000000 "MUL" - attribute \enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 \pipe_trap_op__fn_unit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \pipe_trap_op__insn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \pipe_trap_op__msr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \pipe_trap_op__cia - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_trap_op__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \pipe_trap_op__traptype - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 \pipe_trap_op__trapaddr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \pipe_ra - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \pipe_rb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \pipe_fast1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \pipe_fast2 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" - wire width 1 \pipe_n_valid_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" - wire width 1 \pipe_n_ready_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \pipe_muxid$3 - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \pipe_trap_op__insn_type$4 - attribute \enum_base_type "Function" - attribute \enum_value_00000000000 "NONE" - attribute \enum_value_00000000010 "ALU" - attribute \enum_value_00000000100 "LDST" - attribute \enum_value_00000001000 "SHIFT_ROT" - attribute \enum_value_00000010000 "LOGICAL" - attribute \enum_value_00000100000 "BRANCH" - attribute \enum_value_00001000000 "CR" - attribute \enum_value_00010000000 "TRAP" - attribute \enum_value_00100000000 "MUL" - attribute \enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 \pipe_trap_op__fn_unit$5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \pipe_trap_op__insn$6 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \pipe_trap_op__msr$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \pipe_trap_op__cia$8 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_trap_op__is_32bit$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \pipe_trap_op__traptype$10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 \pipe_trap_op__trapaddr$11 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 \pipe_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \pipe_o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 \pipe_fast1$12 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \pipe_fast1_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 \pipe_fast2$13 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \pipe_fast2_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 \pipe_nia - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \pipe_nia_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 \pipe_msr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \pipe_msr_ok - cell \pipe$32 \pipe - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \p_valid_i \pipe_p_valid_i - connect \p_ready_o \pipe_p_ready_o - connect \muxid \pipe_muxid - connect \trap_op__insn_type \pipe_trap_op__insn_type - connect \trap_op__fn_unit \pipe_trap_op__fn_unit - connect \trap_op__insn \pipe_trap_op__insn - connect \trap_op__msr \pipe_trap_op__msr - connect \trap_op__cia \pipe_trap_op__cia - connect \trap_op__is_32bit \pipe_trap_op__is_32bit - connect \trap_op__traptype \pipe_trap_op__traptype - connect \trap_op__trapaddr \pipe_trap_op__trapaddr - connect \ra \pipe_ra - connect \rb \pipe_rb - connect \fast1 \pipe_fast1 - connect \fast2 \pipe_fast2 - connect \n_valid_o \pipe_n_valid_o - connect \n_ready_i \pipe_n_ready_i - connect \muxid$1 \pipe_muxid$3 - connect \trap_op__insn_type$2 \pipe_trap_op__insn_type$4 - connect \trap_op__fn_unit$3 \pipe_trap_op__fn_unit$5 - connect \trap_op__insn$4 \pipe_trap_op__insn$6 - connect \trap_op__msr$5 \pipe_trap_op__msr$7 - connect \trap_op__cia$6 \pipe_trap_op__cia$8 - connect \trap_op__is_32bit$7 \pipe_trap_op__is_32bit$9 - connect \trap_op__traptype$8 \pipe_trap_op__traptype$10 - connect \trap_op__trapaddr$9 \pipe_trap_op__trapaddr$11 - connect \o \pipe_o - connect \o_ok \pipe_o_ok - connect \fast1$10 \pipe_fast1$12 - connect \fast1_ok \pipe_fast1_ok - connect \fast2$11 \pipe_fast2$13 - connect \fast2_ok \pipe_fast2_ok - connect \nia \pipe_nia - connect \nia_ok \pipe_nia_ok - connect \msr \pipe_msr - connect \msr_ok \pipe_msr_ok - end - process $group_0 - assign \pipe_p_valid_i 1'0 - assign \pipe_p_valid_i \p_valid_i - sync init - end - process $group_1 - assign \p_ready_o 1'0 - assign \p_ready_o \pipe_p_ready_o - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \muxid - process $group_2 - assign \pipe_muxid 2'00 - assign \pipe_muxid \muxid - sync init - end - process $group_3 - assign \pipe_trap_op__insn_type 7'0000000 - assign \pipe_trap_op__fn_unit 11'00000000000 - assign \pipe_trap_op__insn 32'00000000000000000000000000000000 - assign \pipe_trap_op__msr 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \pipe_trap_op__cia 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \pipe_trap_op__is_32bit 1'0 - assign \pipe_trap_op__traptype 7'0000000 - assign \pipe_trap_op__trapaddr 13'0000000000000 - assign { \pipe_trap_op__trapaddr \pipe_trap_op__traptype \pipe_trap_op__is_32bit \pipe_trap_op__cia \pipe_trap_op__msr \pipe_trap_op__insn \pipe_trap_op__fn_unit \pipe_trap_op__insn_type } { \trap_op__trapaddr \trap_op__traptype \trap_op__is_32bit \trap_op__cia \trap_op__msr \trap_op__insn \trap_op__fn_unit \trap_op__insn_type } - sync init - end - process $group_11 - assign \pipe_ra 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \pipe_ra \ra - sync init - end - process $group_12 - assign \pipe_rb 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \pipe_rb \rb - sync init - end - process $group_13 - assign \pipe_fast1 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \pipe_fast1 \fast1$1 - sync init - end - process $group_14 - assign \pipe_fast2 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \pipe_fast2 \fast2$2 - sync init - end - process $group_15 - assign \n_valid_o 1'0 - assign \n_valid_o \pipe_n_valid_o - sync init - end - process $group_16 - assign \pipe_n_ready_i 1'0 - assign \pipe_n_ready_i \n_ready_i - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \muxid$14 - process $group_17 - assign \muxid$14 2'00 - assign \muxid$14 \pipe_muxid$3 - sync init - end - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \trap_op__insn_type$15 - attribute \enum_base_type "Function" - attribute \enum_value_00000000000 "NONE" - attribute \enum_value_00000000010 "ALU" - attribute \enum_value_00000000100 "LDST" - attribute \enum_value_00000001000 "SHIFT_ROT" - attribute \enum_value_00000010000 "LOGICAL" - attribute \enum_value_00000100000 "BRANCH" - attribute \enum_value_00001000000 "CR" - attribute \enum_value_00010000000 "TRAP" - attribute \enum_value_00100000000 "MUL" - attribute \enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 \trap_op__fn_unit$16 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \trap_op__insn$17 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \trap_op__msr$18 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \trap_op__cia$19 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \trap_op__is_32bit$20 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \trap_op__traptype$21 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 \trap_op__trapaddr$22 - process $group_18 - assign \trap_op__insn_type$15 7'0000000 - assign \trap_op__fn_unit$16 11'00000000000 - assign \trap_op__insn$17 32'00000000000000000000000000000000 - assign \trap_op__msr$18 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \trap_op__cia$19 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \trap_op__is_32bit$20 1'0 - assign \trap_op__traptype$21 7'0000000 - assign \trap_op__trapaddr$22 13'0000000000000 - assign { \trap_op__trapaddr$22 \trap_op__traptype$21 \trap_op__is_32bit$20 \trap_op__cia$19 \trap_op__msr$18 \trap_op__insn$17 \trap_op__fn_unit$16 \trap_op__insn_type$15 } { \pipe_trap_op__trapaddr$11 \pipe_trap_op__traptype$10 \pipe_trap_op__is_32bit$9 \pipe_trap_op__cia$8 \pipe_trap_op__msr$7 \pipe_trap_op__insn$6 \pipe_trap_op__fn_unit$5 \pipe_trap_op__insn_type$4 } - sync init - end - process $group_26 - assign \o 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \o_ok 1'0 - assign { \o_ok \o } { \pipe_o_ok \pipe_o } - sync init - end - process $group_28 - assign \fast1 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \fast1_ok 1'0 - assign { \fast1_ok \fast1 } { \pipe_fast1_ok \pipe_fast1$12 } - sync init - end - process $group_30 - assign \fast2 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \fast2_ok 1'0 - assign { \fast2_ok \fast2 } { \pipe_fast2_ok \pipe_fast2$13 } - sync init - end - process $group_32 - assign \nia 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \nia_ok 1'0 - assign { \nia_ok \nia } { \pipe_nia_ok \pipe_nia } - sync init - end - process $group_34 - assign \msr 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \msr_ok 1'0 - assign { \msr_ok \msr } { \pipe_msr_ok \pipe_msr } - sync init - end - connect \muxid 2'00 -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.trap0.src_l" -module \src_l$36 - attribute \src "simple/issuer.py:141" - wire width 1 input 0 \coresync_clk - attribute \src "simple/issuer.py:141" - wire width 1 input 1 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 4 input 2 \s_src - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 4 input 3 \r_src - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire width 4 output 4 \q_src - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire width 4 \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire width 4 \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 4 $1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A \r_src - connect \Y $1 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 4 $3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $4 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A \q_int - connect \B $1 - connect \Y $3 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 4 $5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $6 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A $3 - connect \B \s_src - connect \Y $5 - end - process $group_0 - assign \q_int$next \q_int - assign \q_int$next $5 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \q_int$next 4'0000 - end - sync init - update \q_int 4'0000 - sync posedge \coresync_clk - update \q_int \q_int$next - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 4 $7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $8 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A \r_src - connect \Y $7 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 4 $9 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $10 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A \q_int - connect \B $7 - connect \Y $9 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 4 $11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $12 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A $9 - connect \B \s_src - connect \Y $11 - end - process $group_1 - assign \q_src 4'0000 - assign \q_src $11 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" - wire width 4 \qn_src - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - wire width 4 $13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $14 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A \q_src - connect \Y $13 - end - process $group_2 - assign \qn_src 4'0000 - assign \qn_src $13 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" - wire width 4 \qlq_src - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - wire width 4 $15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $16 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A \q_src - connect \B \q_int - connect \Y $15 - end - process $group_3 - assign \qlq_src 4'0000 - assign \qlq_src $15 - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.trap0.opc_l" -module \opc_l$37 - attribute \src "simple/issuer.py:141" - wire width 1 input 0 \coresync_clk - attribute \src "simple/issuer.py:141" - wire width 1 input 1 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 1 input 2 \s_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 1 input 3 \r_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire width 1 output 4 \q_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire width 1 \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire width 1 \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_opc - connect \Y $1 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 1 $3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $4 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B $1 - connect \Y $3 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 1 $5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $6 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $3 - connect \B \s_opc - connect \Y $5 - end - process $group_0 - assign \q_int$next \q_int - assign \q_int$next $5 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \q_int$next 1'0 - end - sync init - update \q_int 1'0 - sync posedge \coresync_clk - update \q_int \q_int$next - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 1 $7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $8 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_opc - connect \Y $7 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 1 $9 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $10 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B $7 - connect \Y $9 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 1 $11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $12 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $9 - connect \B \s_opc - connect \Y $11 - end - process $group_1 - assign \q_opc 1'0 - assign \q_opc $11 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" - wire width 1 \qn_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - wire width 1 $13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $14 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_opc - connect \Y $13 - end - process $group_2 - assign \qn_opc 1'0 - assign \qn_opc $13 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" - wire width 1 \qlq_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - wire width 1 $15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $16 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_opc - connect \B \q_int - connect \Y $15 - end - process $group_3 - assign \qlq_opc 1'0 - assign \qlq_opc $15 - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.trap0.req_l" -module \req_l$38 - attribute \src "simple/issuer.py:141" - wire width 1 input 0 \coresync_clk - attribute \src "simple/issuer.py:141" - wire width 1 input 1 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire width 5 output 2 \q_req - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 5 input 3 \s_req - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 5 input 4 \r_req - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire width 5 \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire width 5 \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 5 $1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \Y_WIDTH 5 - connect \A \r_req - connect \Y $1 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 5 $3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $4 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 5 - connect \A \q_int - connect \B $1 - connect \Y $3 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 5 $5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $6 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 5 - connect \A $3 - connect \B \s_req - connect \Y $5 - end - process $group_0 - assign \q_int$next \q_int - assign \q_int$next $5 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \q_int$next 5'00000 - end - sync init - update \q_int 5'00000 - sync posedge \coresync_clk - update \q_int \q_int$next - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 5 $7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $8 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \Y_WIDTH 5 - connect \A \r_req - connect \Y $7 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 5 $9 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $10 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 5 - connect \A \q_int - connect \B $7 - connect \Y $9 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 5 $11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $12 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 5 - connect \A $9 - connect \B \s_req - connect \Y $11 - end - process $group_1 - assign \q_req 5'00000 - assign \q_req $11 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" - wire width 5 \qn_req - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - wire width 5 $13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $14 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \Y_WIDTH 5 - connect \A \q_req - connect \Y $13 - end - process $group_2 - assign \qn_req 5'00000 - assign \qn_req $13 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" - wire width 5 \qlq_req - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - wire width 5 $15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $16 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 5 - connect \A \q_req - connect \B \q_int - connect \Y $15 - end - process $group_3 - assign \qlq_req 5'00000 - assign \qlq_req $15 - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.trap0.rst_l" -module \rst_l$39 - attribute \src "simple/issuer.py:141" - wire width 1 input 0 \coresync_clk - attribute \src "simple/issuer.py:141" - wire width 1 input 1 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 1 input 2 \s_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 1 input 3 \r_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire width 1 \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire width 1 \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_rst - connect \Y $1 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 1 $3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $4 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B $1 - connect \Y $3 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 1 $5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $6 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $3 - connect \B \s_rst - connect \Y $5 - end - process $group_0 - assign \q_int$next \q_int - assign \q_int$next $5 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \q_int$next 1'0 - end - sync init - update \q_int 1'0 - sync posedge \coresync_clk - update \q_int \q_int$next - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire width 1 \q_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 1 $7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $8 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_rst - connect \Y $7 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 1 $9 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $10 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B $7 - connect \Y $9 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 1 $11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $12 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $9 - connect \B \s_rst - connect \Y $11 - end - process $group_1 - assign \q_rst 1'0 - assign \q_rst $11 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" - wire width 1 \qn_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - wire width 1 $13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $14 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_rst - connect \Y $13 - end - process $group_2 - assign \qn_rst 1'0 - assign \qn_rst $13 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" - wire width 1 \qlq_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - wire width 1 $15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $16 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_rst - connect \B \q_int - connect \Y $15 - end - process $group_3 - assign \qlq_rst 1'0 - assign \qlq_rst $15 - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.trap0.rok_l" -module \rok_l$40 - attribute \src "simple/issuer.py:141" - wire width 1 input 0 \coresync_clk - attribute \src "simple/issuer.py:141" - wire width 1 input 1 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire width 1 output 2 \q_rdok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 1 input 3 \s_rdok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 1 input 4 \r_rdok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire width 1 \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire width 1 \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_rdok - connect \Y $1 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 1 $3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $4 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B $1 - connect \Y $3 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 1 $5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $6 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $3 - connect \B \s_rdok - connect \Y $5 - end - process $group_0 - assign \q_int$next \q_int - assign \q_int$next $5 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \q_int$next 1'0 - end - sync init - update \q_int 1'0 - sync posedge \coresync_clk - update \q_int \q_int$next - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 1 $7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $8 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_rdok - connect \Y $7 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 1 $9 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $10 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B $7 - connect \Y $9 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 1 $11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $12 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $9 - connect \B \s_rdok - connect \Y $11 - end - process $group_1 - assign \q_rdok 1'0 - assign \q_rdok $11 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" - wire width 1 \qn_rdok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - wire width 1 $13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $14 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_rdok - connect \Y $13 - end - process $group_2 - assign \qn_rdok 1'0 - assign \qn_rdok $13 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" - wire width 1 \qlq_rdok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - wire width 1 $15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $16 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_rdok - connect \B \q_int - connect \Y $15 - end - process $group_3 - assign \qlq_rdok 1'0 - assign \qlq_rdok $15 - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.trap0.alui_l" -module \alui_l$41 - attribute \src "simple/issuer.py:141" - wire width 1 input 0 \coresync_clk - attribute \src "simple/issuer.py:141" - wire width 1 input 1 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire width 1 output 2 \q_alui - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 1 input 3 \r_alui - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 1 input 4 \s_alui - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire width 1 \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire width 1 \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_alui - connect \Y $1 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 1 $3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $4 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B $1 - connect \Y $3 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 1 $5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $6 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $3 - connect \B \s_alui - connect \Y $5 - end - process $group_0 - assign \q_int$next \q_int - assign \q_int$next $5 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \q_int$next 1'0 - end - sync init - update \q_int 1'0 - sync posedge \coresync_clk - update \q_int \q_int$next - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 1 $7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $8 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_alui - connect \Y $7 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 1 $9 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $10 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B $7 - connect \Y $9 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 1 $11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $12 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $9 - connect \B \s_alui - connect \Y $11 - end - process $group_1 - assign \q_alui 1'0 - assign \q_alui $11 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" - wire width 1 \qn_alui - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - wire width 1 $13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $14 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_alui - connect \Y $13 - end - process $group_2 - assign \qn_alui 1'0 - assign \qn_alui $13 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" - wire width 1 \qlq_alui - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - wire width 1 $15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $16 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_alui - connect \B \q_int - connect \Y $15 - end - process $group_3 - assign \qlq_alui 1'0 - assign \qlq_alui $15 - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.trap0.alu_l" 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"/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 1 $3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $4 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B $1 - connect \Y $3 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 1 $5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $6 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $3 - connect \B \s_alu - connect \Y $5 - end - process $group_0 - assign \q_int$next \q_int - assign \q_int$next $5 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \q_int$next 1'0 - end - sync init - update \q_int 1'0 - sync posedge \coresync_clk - update \q_int \q_int$next - end - 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end - process $group_3 - assign \qlq_alu 1'0 - assign \qlq_alu $15 - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.trap0" -module \trap0 - attribute \src "simple/issuer.py:141" - wire width 1 input 0 \coresync_clk - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute 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attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:100" - wire width 1 input 9 \cu_issue_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107" - wire width 1 output 10 \cu_busy_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96" - wire width 4 input 11 \cu_rdmaskn_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 4 output 12 \cu_rd__rel_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 4 input 13 \cu_rd__go_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 64 input 14 \src1_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 64 input 15 \src2_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 64 input 16 \src3_i - attribute \src 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\src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \alu_trap0_trap_op__is_32bit$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \alu_trap0_trap_op__traptype - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \alu_trap0_trap_op__traptype$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 \alu_trap0_trap_op__trapaddr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 13 \alu_trap0_trap_op__trapaddr$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 \alu_trap0_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 \alu_trap0_fast1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 \alu_trap0_fast2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 \alu_trap0_nia - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 \alu_trap0_msr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \alu_trap0_ra - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \alu_trap0_rb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \alu_trap0_fast1$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \alu_trap0_fast2$2 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" - wire width 1 \alu_trap0_p_valid_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" - wire width 1 \alu_trap0_p_ready_o - cell \alu_trap0 \alu_trap0 - connect \coresync_clk \coresync_clk - connect \o_ok \o_ok - connect \fast1_ok \fast1_ok - connect \fast2_ok \fast2_ok - connect \nia_ok \nia_ok - connect \msr_ok \msr_ok - connect \coresync_rst \coresync_rst - connect \n_valid_o \alu_trap0_n_valid_o - connect \n_ready_i \alu_trap0_n_ready_i - connect \trap_op__insn_type \alu_trap0_trap_op__insn_type - connect \trap_op__fn_unit \alu_trap0_trap_op__fn_unit - connect \trap_op__insn \alu_trap0_trap_op__insn - connect \trap_op__msr \alu_trap0_trap_op__msr - connect \trap_op__cia \alu_trap0_trap_op__cia - connect \trap_op__is_32bit \alu_trap0_trap_op__is_32bit - connect \trap_op__traptype \alu_trap0_trap_op__traptype - connect \trap_op__trapaddr \alu_trap0_trap_op__trapaddr - connect \o \alu_trap0_o - connect \fast1 \alu_trap0_fast1 - connect \fast2 \alu_trap0_fast2 - connect \nia \alu_trap0_nia - connect \msr \alu_trap0_msr - connect \ra \alu_trap0_ra - connect \rb \alu_trap0_rb - connect \fast1$1 \alu_trap0_fast1$1 - connect \fast2$2 \alu_trap0_fast2$2 - connect \p_valid_i \alu_trap0_p_valid_i - connect \p_ready_o \alu_trap0_p_ready_o - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 4 \src_l_s_src - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 4 \src_l_s_src$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 4 \src_l_r_src - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 4 \src_l_r_src$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire width 4 \src_l_q_src - cell \src_l$36 \src_l - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \s_src \src_l_s_src - connect \r_src \src_l_r_src - connect \q_src \src_l_q_src - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 1 \opc_l_s_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 1 \opc_l_s_opc$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 1 \opc_l_r_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 1 \opc_l_r_opc$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire width 1 \opc_l_q_opc - cell \opc_l$37 \opc_l - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \s_opc \opc_l_s_opc - connect \r_opc \opc_l_r_opc - connect \q_opc \opc_l_q_opc - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire width 5 \req_l_q_req - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 5 \req_l_s_req - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 5 \req_l_s_req$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 5 \req_l_r_req - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 5 \req_l_r_req$next - cell \req_l$38 \req_l - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \q_req \req_l_q_req - connect \s_req \req_l_s_req - connect \r_req \req_l_r_req - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 1 \rst_l_s_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 1 \rst_l_s_rst$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 1 \rst_l_r_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 1 \rst_l_r_rst$next - cell \rst_l$39 \rst_l - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \s_rst \rst_l_s_rst - connect \r_rst \rst_l_r_rst - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire width 1 \rok_l_q_rdok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 1 \rok_l_s_rdok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 1 \rok_l_s_rdok$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 1 \rok_l_r_rdok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 1 \rok_l_r_rdok$next - cell \rok_l$40 \rok_l - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \q_rdok \rok_l_q_rdok - connect \s_rdok \rok_l_s_rdok - connect \r_rdok \rok_l_r_rdok - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire width 1 \alui_l_q_alui - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 1 \alui_l_r_alui - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 1 \alui_l_r_alui$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 1 \alui_l_s_alui - cell \alui_l$41 \alui_l - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \q_alui \alui_l_q_alui - connect \r_alui \alui_l_r_alui - connect \s_alui \alui_l_s_alui - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire width 1 \alu_l_q_alu - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 1 \alu_l_r_alu - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 1 \alu_l_r_alu$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 1 \alu_l_s_alu - cell \alu_l$42 \alu_l - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \q_alu \alu_l_q_alu - connect \r_alu \alu_l_r_alu - connect \s_alu \alu_l_s_alu - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:187" - wire width 1 \all_rd - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:188" - wire width 1 $3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:188" - cell $and $4 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cu_busy_o - connect \B \rok_l_q_rdok - connect \Y $3 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - wire width 1 $5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - wire width 4 $6 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - cell $not $7 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A \cu_rd__rel_o - connect \Y $6 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - wire width 4 $8 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - cell $or $9 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A $6 - connect \B \cu_rd__go_i - connect \Y $8 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - cell $reduce_and $10 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A $8 - connect \Y $5 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - wire width 1 $11 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - cell $and $12 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $3 - connect \B $5 - connect \Y $11 - end - process $group_0 - assign \all_rd 1'0 - assign \all_rd $11 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire width 1 \all_rd_dly - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire width 1 \all_rd_dly$next - process $group_1 - assign \all_rd_dly$next \all_rd_dly - assign \all_rd_dly$next \all_rd - sync init - update \all_rd_dly 1'0 - sync posedge \coresync_clk - update \all_rd_dly \all_rd_dly$next - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" - wire width 1 \all_rd_rise - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - wire width 1 $13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $not $14 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \all_rd_dly - connect \Y $13 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - wire width 1 $15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $and $16 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \all_rd - connect \B $13 - connect \Y $15 - end - process $group_2 - assign \all_rd_rise 1'0 - assign \all_rd_rise $15 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:192" - wire width 1 \all_rd_pulse - process $group_3 - assign \all_rd_pulse 1'0 - assign \all_rd_pulse \all_rd_rise - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:196" - wire width 1 \alu_done - process $group_4 - assign \alu_done 1'0 - assign \alu_done \alu_trap0_n_valid_o - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire width 1 \alu_done_dly - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire width 1 \alu_done_dly$next - process $group_5 - assign \alu_done_dly$next \alu_done_dly - assign \alu_done_dly$next \alu_done - sync init - update \alu_done_dly 1'0 - sync posedge \coresync_clk - update \alu_done_dly \alu_done_dly$next - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" - wire width 1 \alu_done_rise - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - wire width 1 $17 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $not $18 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \alu_done_dly - connect \Y $17 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - wire width 1 $19 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $and $20 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \alu_done - connect \B $17 - connect \Y $19 - end - process $group_6 - assign \alu_done_rise 1'0 - assign \alu_done_rise $19 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:197" - wire width 1 \alu_pulse - process $group_7 - assign \alu_pulse 1'0 - assign \alu_pulse \alu_done_rise - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:198" - wire width 5 \alu_pulsem - process $group_8 - assign \alu_pulsem 5'00000 - assign \alu_pulsem { \alu_pulse \alu_pulse \alu_pulse \alu_pulse \alu_pulse } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:204" - wire width 5 \prev_wr_go - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:204" - wire width 5 \prev_wr_go$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:206" - wire width 5 $21 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:206" - cell $and $22 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 5 - connect \A \cu_wr__go_i - connect \B { \cu_busy_o \cu_busy_o \cu_busy_o \cu_busy_o \cu_busy_o } - connect \Y $21 - end - process $group_9 - assign \prev_wr_go$next \prev_wr_go - assign \prev_wr_go$next $21 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \prev_wr_go$next 5'00000 - end - sync init - update \prev_wr_go 5'00000 - sync posedge \coresync_clk - update \prev_wr_go \prev_wr_go$next - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:108" - wire width 1 \cu_done_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - wire width 1 $23 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - wire width 1 $24 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - wire width 5 $25 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:97" - wire width 5 \cu_wrmask_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $not $26 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \Y_WIDTH 5 - connect \A \cu_wrmask_o - connect \Y $25 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - wire width 5 $27 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $and $28 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 5 - connect \A \cu_wr__rel_o - connect \B $25 - connect \Y $27 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $reduce_bool $29 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A $27 - connect \Y $24 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $not $30 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $24 - connect \Y $23 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - wire width 1 $31 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $and $32 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cu_busy_o - connect \B $23 - connect \Y $31 - end - process $group_10 - assign \cu_done_o 1'0 - assign \cu_done_o $31 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:211" - wire width 1 \wr_any - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" - wire width 1 $33 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" - cell $reduce_bool $34 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \cu_wr__go_i - connect \Y $33 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" - wire width 1 $35 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" - cell $reduce_bool $36 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \prev_wr_go - connect \Y $35 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" - wire width 1 $37 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" - cell $or $38 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $33 - connect \B $35 - connect \Y $37 - end - process $group_11 - assign \wr_any 1'0 - assign \wr_any $37 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:212" - wire width 1 \req_done - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" - wire width 1 $39 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" - cell $not $40 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \alu_trap0_n_ready_i - connect \Y $39 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" - wire width 1 $41 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" - cell $and $42 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_any - connect \B $39 - connect \Y $41 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" - wire width 5 $43 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" - cell $and $44 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 5 - connect \A \req_l_q_req - connect \B \cu_wrmask_o - connect \Y $43 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" - wire width 1 $45 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" - cell $eq $46 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $43 - connect \B 1'0 - connect \Y $45 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" - wire width 1 $47 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" - cell $and $48 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $41 - connect \B $45 - connect \Y $47 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - wire width 1 $49 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - cell $eq $50 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cu_wrmask_o - connect \B 1'0 - connect \Y $49 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - wire width 1 $51 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - cell $and $52 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $49 - connect \B \alu_trap0_n_ready_i - connect \Y $51 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - wire width 1 $53 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - cell $and $54 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $51 - connect \B \alu_trap0_n_valid_o - connect \Y $53 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - wire width 1 $55 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - cell $and $56 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $53 - connect \B \cu_busy_o - connect \Y $55 - end - process $group_12 - assign \req_done 1'0 - assign \req_done $47 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - switch { $55 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - case 1'1 - assign \req_done 1'1 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:226" - wire width 1 \reset - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:104" - wire width 1 \cu_go_die_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:230" - wire width 1 $57 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:230" - cell $or $58 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \req_done - connect \B \cu_go_die_i - connect \Y $57 - end - process $group_13 - assign \reset 1'0 - assign \reset $57 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:227" - wire width 1 \rst_r - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:231" - wire width 1 $59 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:231" - cell $or $60 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cu_issue_i - connect \B \cu_go_die_i - connect \Y $59 - end - process $group_14 - assign \rst_r 1'0 - assign \rst_r $59 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:228" - wire width 5 \reset_w - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:232" - wire width 5 $61 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:232" - cell $or $62 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 5 - connect \A \cu_wr__go_i - connect \B { \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i } - connect \Y $61 - end - process $group_15 - assign \reset_w 5'00000 - assign \reset_w $61 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:229" - wire width 4 \reset_r - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:233" - wire width 4 $63 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:233" - cell $or $64 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A \cu_rd__go_i - connect \B { \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i } - connect \Y $63 - end - process $group_16 - assign \reset_r 4'0000 - assign \reset_r $63 - sync init - end - process $group_17 - assign \rok_l_s_rdok$next \rok_l_s_rdok - assign \rok_l_s_rdok$next \cu_issue_i - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \rok_l_s_rdok$next 1'0 - end - sync init - update \rok_l_s_rdok 1'0 - sync posedge \coresync_clk - update \rok_l_s_rdok \rok_l_s_rdok$next - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:237" - wire width 1 $65 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:237" - cell $and $66 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \alu_trap0_n_valid_o - connect \B \cu_busy_o - connect \Y $65 - end - process $group_18 - assign \rok_l_r_rdok$next \rok_l_r_rdok - assign \rok_l_r_rdok$next $65 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \rok_l_r_rdok$next 1'1 - end - sync init - update \rok_l_r_rdok 1'1 - sync posedge \coresync_clk - update \rok_l_r_rdok \rok_l_r_rdok$next - end - process $group_19 - assign \rst_l_s_rst$next \rst_l_s_rst - assign \rst_l_s_rst$next \all_rd - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \rst_l_s_rst$next 1'0 - end - sync init - update \rst_l_s_rst 1'0 - sync posedge \coresync_clk - update \rst_l_s_rst \rst_l_s_rst$next - end - process $group_20 - assign \rst_l_r_rst$next \rst_l_r_rst - assign \rst_l_r_rst$next \rst_r - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \rst_l_r_rst$next 1'1 - end - sync init - update \rst_l_r_rst 1'1 - sync posedge \coresync_clk - update \rst_l_r_rst \rst_l_r_rst$next - end - process $group_21 - assign \opc_l_s_opc$next \opc_l_s_opc - assign \opc_l_s_opc$next \cu_issue_i - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \opc_l_s_opc$next 1'0 - end - sync init - update \opc_l_s_opc 1'0 - sync posedge \coresync_clk - update \opc_l_s_opc \opc_l_s_opc$next - end - process $group_22 - assign \opc_l_r_opc$next \opc_l_r_opc - assign \opc_l_r_opc$next \req_done - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \opc_l_r_opc$next 1'1 - end - sync init - update \opc_l_r_opc 1'1 - sync posedge \coresync_clk - update \opc_l_r_opc \opc_l_r_opc$next - end - process $group_23 - assign \src_l_s_src$next \src_l_s_src - assign \src_l_s_src$next { \cu_issue_i \cu_issue_i \cu_issue_i \cu_issue_i } - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \src_l_s_src$next 4'0000 - end - sync init - update \src_l_s_src 4'0000 - sync posedge \coresync_clk - update \src_l_s_src \src_l_s_src$next - end - process $group_24 - assign \src_l_r_src$next \src_l_r_src - assign \src_l_r_src$next \reset_r - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \src_l_r_src$next 4'1111 - end - sync init - update \src_l_r_src 4'1111 - sync posedge \coresync_clk - update \src_l_r_src \src_l_r_src$next - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:252" - wire width 5 $67 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:252" - cell $and $68 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 5 - connect \A \alu_pulsem - connect \B \cu_wrmask_o - connect \Y $67 - end - process $group_25 - assign \req_l_s_req$next \req_l_s_req - assign \req_l_s_req$next $67 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \req_l_s_req$next 5'00000 - end - sync init - update \req_l_s_req 5'00000 - sync posedge \coresync_clk - update \req_l_s_req \req_l_s_req$next - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:253" - wire width 5 $69 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:253" - cell $or $70 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 5 - connect \A \reset_w - connect \B \prev_wr_go - connect \Y $69 - end - process $group_26 - assign \req_l_r_req$next \req_l_r_req - assign \req_l_r_req$next $69 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \req_l_r_req$next 5'11111 - end - sync init - update \req_l_r_req 5'11111 - sync posedge \coresync_clk - update \req_l_r_req \req_l_r_req$next - end - process $group_27 - assign \alu_trap0_trap_op__insn_type$next \alu_trap0_trap_op__insn_type - assign \alu_trap0_trap_op__fn_unit$next \alu_trap0_trap_op__fn_unit - assign \alu_trap0_trap_op__insn$next \alu_trap0_trap_op__insn - assign \alu_trap0_trap_op__msr$next \alu_trap0_trap_op__msr - assign \alu_trap0_trap_op__cia$next \alu_trap0_trap_op__cia - assign \alu_trap0_trap_op__is_32bit$next \alu_trap0_trap_op__is_32bit - assign \alu_trap0_trap_op__traptype$next \alu_trap0_trap_op__traptype - assign \alu_trap0_trap_op__trapaddr$next \alu_trap0_trap_op__trapaddr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:257" - switch { \cu_issue_i } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:257" - case 1'1 - assign { \alu_trap0_trap_op__trapaddr$next \alu_trap0_trap_op__traptype$next \alu_trap0_trap_op__is_32bit$next \alu_trap0_trap_op__cia$next \alu_trap0_trap_op__msr$next \alu_trap0_trap_op__insn$next \alu_trap0_trap_op__fn_unit$next \alu_trap0_trap_op__insn_type$next } { \oper_i_alu_trap0__trapaddr \oper_i_alu_trap0__traptype \oper_i_alu_trap0__is_32bit \oper_i_alu_trap0__cia \oper_i_alu_trap0__msr \oper_i_alu_trap0__insn \oper_i_alu_trap0__fn_unit \oper_i_alu_trap0__insn_type } - end - sync init - update \alu_trap0_trap_op__insn_type 7'0000000 - update \alu_trap0_trap_op__fn_unit 11'00000000000 - update \alu_trap0_trap_op__insn 32'00000000000000000000000000000000 - update \alu_trap0_trap_op__msr 64'0000000000000000000000000000000000000000000000000000000000000000 - update \alu_trap0_trap_op__cia 64'0000000000000000000000000000000000000000000000000000000000000000 - update \alu_trap0_trap_op__is_32bit 1'0 - update \alu_trap0_trap_op__traptype 7'0000000 - update \alu_trap0_trap_op__trapaddr 13'0000000000000 - sync posedge \coresync_clk - update \alu_trap0_trap_op__insn_type \alu_trap0_trap_op__insn_type$next - update \alu_trap0_trap_op__fn_unit \alu_trap0_trap_op__fn_unit$next - update \alu_trap0_trap_op__insn \alu_trap0_trap_op__insn$next - update \alu_trap0_trap_op__msr \alu_trap0_trap_op__msr$next - update \alu_trap0_trap_op__cia \alu_trap0_trap_op__cia$next - update \alu_trap0_trap_op__is_32bit \alu_trap0_trap_op__is_32bit$next - update \alu_trap0_trap_op__traptype \alu_trap0_trap_op__traptype$next - update \alu_trap0_trap_op__trapaddr \alu_trap0_trap_op__trapaddr$next - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" - wire width 64 \data_r0__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" - wire width 64 \data_r0__o$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" - wire width 1 \data_r0__o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" - wire width 1 \data_r0__o_ok$next - process $group_35 - assign \data_r0__o$next \data_r0__o - assign \data_r0__o_ok$next \data_r0__o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" - switch { \alu_pulse } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" - case 1'1 - assign { \data_r0__o_ok$next \data_r0__o$next } { \o_ok \alu_trap0_o } - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" - switch { \cu_issue_i } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" - case 1'1 - assign { \data_r0__o_ok$next \data_r0__o$next } 65'00000000000000000000000000000000000000000000000000000000000000000 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \data_r0__o_ok$next 1'0 - end - sync init - update \data_r0__o 64'0000000000000000000000000000000000000000000000000000000000000000 - update \data_r0__o_ok 1'0 - sync posedge \coresync_clk - update \data_r0__o \data_r0__o$next - update \data_r0__o_ok \data_r0__o_ok$next - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" - wire width 64 \data_r1__fast1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" - wire width 64 \data_r1__fast1$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" - wire width 1 \data_r1__fast1_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" - wire width 1 \data_r1__fast1_ok$next - process $group_37 - assign \data_r1__fast1$next \data_r1__fast1 - assign \data_r1__fast1_ok$next \data_r1__fast1_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" - switch { \alu_pulse } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" - case 1'1 - assign { \data_r1__fast1_ok$next \data_r1__fast1$next } { \fast1_ok \alu_trap0_fast1 } - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" - switch { \cu_issue_i } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" - case 1'1 - assign { \data_r1__fast1_ok$next \data_r1__fast1$next } 65'00000000000000000000000000000000000000000000000000000000000000000 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \data_r1__fast1_ok$next 1'0 - end - sync init - update \data_r1__fast1 64'0000000000000000000000000000000000000000000000000000000000000000 - update \data_r1__fast1_ok 1'0 - sync posedge \coresync_clk - update \data_r1__fast1 \data_r1__fast1$next - update \data_r1__fast1_ok \data_r1__fast1_ok$next - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" - wire width 64 \data_r2__fast2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" - wire width 64 \data_r2__fast2$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" - wire width 1 \data_r2__fast2_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" - wire width 1 \data_r2__fast2_ok$next - process $group_39 - assign \data_r2__fast2$next \data_r2__fast2 - assign \data_r2__fast2_ok$next \data_r2__fast2_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" - switch { \alu_pulse } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" - case 1'1 - assign { \data_r2__fast2_ok$next \data_r2__fast2$next } { \fast2_ok \alu_trap0_fast2 } - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" - switch { \cu_issue_i } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" - case 1'1 - assign { \data_r2__fast2_ok$next \data_r2__fast2$next } 65'00000000000000000000000000000000000000000000000000000000000000000 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \data_r2__fast2_ok$next 1'0 - end - sync init - update \data_r2__fast2 64'0000000000000000000000000000000000000000000000000000000000000000 - update \data_r2__fast2_ok 1'0 - sync posedge \coresync_clk - update \data_r2__fast2 \data_r2__fast2$next - update \data_r2__fast2_ok \data_r2__fast2_ok$next - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" - wire width 64 \data_r3__nia - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" - wire width 64 \data_r3__nia$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" - wire width 1 \data_r3__nia_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" - wire width 1 \data_r3__nia_ok$next - process $group_41 - assign \data_r3__nia$next \data_r3__nia - assign \data_r3__nia_ok$next \data_r3__nia_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" - switch { \alu_pulse } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" - case 1'1 - assign { \data_r3__nia_ok$next \data_r3__nia$next } { \nia_ok \alu_trap0_nia } - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" - switch { \cu_issue_i } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" - case 1'1 - assign { \data_r3__nia_ok$next \data_r3__nia$next } 65'00000000000000000000000000000000000000000000000000000000000000000 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \data_r3__nia_ok$next 1'0 - end - sync init - update \data_r3__nia 64'0000000000000000000000000000000000000000000000000000000000000000 - update \data_r3__nia_ok 1'0 - sync posedge \coresync_clk - update \data_r3__nia \data_r3__nia$next - update \data_r3__nia_ok \data_r3__nia_ok$next - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" - wire width 64 \data_r4__msr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" - wire width 64 \data_r4__msr$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" - wire width 1 \data_r4__msr_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" - wire width 1 \data_r4__msr_ok$next - process $group_43 - assign \data_r4__msr$next \data_r4__msr - assign \data_r4__msr_ok$next \data_r4__msr_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" - switch { \alu_pulse } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" - case 1'1 - assign { \data_r4__msr_ok$next \data_r4__msr$next } { \msr_ok \alu_trap0_msr } - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" - switch { \cu_issue_i } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" - case 1'1 - assign { \data_r4__msr_ok$next \data_r4__msr$next } 65'00000000000000000000000000000000000000000000000000000000000000000 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \data_r4__msr_ok$next 1'0 - end - sync init - update \data_r4__msr 64'0000000000000000000000000000000000000000000000000000000000000000 - update \data_r4__msr_ok 1'0 - sync posedge \coresync_clk - update \data_r4__msr \data_r4__msr$next - update \data_r4__msr_ok \data_r4__msr_ok$next - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" - wire width 1 $71 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" - cell $and $72 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \o_ok - connect \B \cu_busy_o - connect \Y $71 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" - wire width 1 $73 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" - cell $and $74 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \fast1_ok - connect \B \cu_busy_o - connect \Y $73 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" - wire width 1 $75 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" - cell $and $76 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \fast2_ok - connect \B \cu_busy_o - connect \Y $75 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" - wire width 1 $77 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" - cell $and $78 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \nia_ok - connect \B \cu_busy_o - connect \Y $77 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" - wire width 1 $79 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" - cell $and $80 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \msr_ok - connect \B \cu_busy_o - connect \Y $79 - end - process $group_45 - assign \cu_wrmask_o 5'00000 - assign \cu_wrmask_o { $79 $77 $75 $73 $71 } - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" - wire width 64 \src_r0 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" - wire width 64 \src_r0$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - wire width 64 $81 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - cell $mux $82 - parameter \WIDTH 64 - connect \A \src_r0 - connect \B \src1_i - connect \S \src_l_q_src [0] - connect \Y $81 - end - process $group_46 - assign \alu_trap0_ra 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \alu_trap0_ra $81 - sync init - end - process $group_47 - assign \src_r0$next \src_r0 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" - switch { \src_l_q_src [0] } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" - case 1'1 - assign \src_r0$next \src1_i - end - sync init - update \src_r0 64'0000000000000000000000000000000000000000000000000000000000000000 - sync posedge \coresync_clk - update \src_r0 \src_r0$next - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" - wire width 64 \src_r1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" - wire width 64 \src_r1$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - wire width 64 $83 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - cell $mux $84 - parameter \WIDTH 64 - connect \A \src_r1 - connect \B \src2_i - connect \S \src_l_q_src [1] - connect \Y $83 - end - process $group_48 - assign \alu_trap0_rb 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \alu_trap0_rb $83 - sync init - end - process $group_49 - assign \src_r1$next \src_r1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" - switch { \src_l_q_src [1] } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" - case 1'1 - assign \src_r1$next \src2_i - end - sync init - update \src_r1 64'0000000000000000000000000000000000000000000000000000000000000000 - sync posedge \coresync_clk - update \src_r1 \src_r1$next - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" - wire width 64 \src_r2 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" - wire width 64 \src_r2$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - wire width 64 $85 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - cell $mux $86 - parameter \WIDTH 64 - connect \A \src_r2 - connect \B \src3_i - connect \S \src_l_q_src [2] - connect \Y $85 - end - process $group_50 - assign \alu_trap0_fast1$1 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \alu_trap0_fast1$1 $85 - sync init - end - process $group_51 - assign \src_r2$next \src_r2 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" - switch { \src_l_q_src [2] } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" - case 1'1 - assign \src_r2$next \src3_i - end - sync init - update \src_r2 64'0000000000000000000000000000000000000000000000000000000000000000 - sync posedge \coresync_clk - update \src_r2 \src_r2$next - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" - wire width 64 \src_r3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" - wire width 64 \src_r3$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - wire width 64 $87 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - cell $mux $88 - parameter \WIDTH 64 - connect \A \src_r3 - connect \B \src4_i - connect \S \src_l_q_src [3] - connect \Y $87 - end - process $group_52 - assign \alu_trap0_fast2$2 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \alu_trap0_fast2$2 $87 - sync init - end - process $group_53 - assign \src_r3$next \src_r3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" - switch { \src_l_q_src [3] } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" - case 1'1 - assign \src_r3$next \src4_i - end - sync init - update \src_r3 64'0000000000000000000000000000000000000000000000000000000000000000 - sync posedge \coresync_clk - update \src_r3 \src_r3$next - end - process $group_54 - assign \alu_trap0_p_valid_i 1'0 - assign \alu_trap0_p_valid_i \alui_l_q_alui - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:327" - wire width 1 $89 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:327" - cell $and $90 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \alu_trap0_p_ready_o - connect \B \alui_l_q_alui - connect \Y $89 - end - process $group_55 - assign \alui_l_r_alui$next \alui_l_r_alui - assign \alui_l_r_alui$next $89 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \alui_l_r_alui$next 1'1 - end - sync init - update \alui_l_r_alui 1'1 - sync posedge \coresync_clk - update \alui_l_r_alui \alui_l_r_alui$next - end - process $group_56 - assign \alui_l_s_alui 1'0 - assign \alui_l_s_alui \all_rd_pulse - sync init - end - process $group_57 - assign \alu_trap0_n_ready_i 1'0 - assign \alu_trap0_n_ready_i \alu_l_q_alu - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:334" - wire width 1 $91 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:334" - cell $and $92 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \alu_trap0_n_valid_o - connect \B \alu_l_q_alu - connect \Y $91 - end - process $group_58 - assign \alu_l_r_alu$next \alu_l_r_alu - assign \alu_l_r_alu$next $91 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \alu_l_r_alu$next 1'1 - end - sync init - update \alu_l_r_alu 1'1 - sync posedge \coresync_clk - update \alu_l_r_alu \alu_l_r_alu$next - end - process $group_59 - assign \alu_l_s_alu 1'0 - assign \alu_l_s_alu \all_rd_pulse - sync init - end - process $group_60 - assign \cu_busy_o 1'0 - assign \cu_busy_o \opc_l_q_opc - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - wire width 4 $93 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - cell $and $94 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A \src_l_q_src - connect \B { \cu_busy_o \cu_busy_o \cu_busy_o \cu_busy_o } - connect \Y $93 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - wire width 4 $95 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - cell $and $96 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A $93 - connect \B { 1'1 1'1 1'1 1'1 } - connect \Y $95 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - wire width 4 $97 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - cell $not $98 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A \cu_rdmaskn_i - connect \Y $97 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - wire width 4 $99 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - cell $and $100 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A $95 - connect \B $97 - connect \Y $99 - end - process $group_61 - assign \cu_rd__rel_o 4'0000 - assign \cu_rd__rel_o $99 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:102" - wire width 1 \cu_shadown_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" - wire width 1 $101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" - cell $and $102 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cu_busy_o - connect \B \cu_shadown_i - connect \Y $101 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" - wire width 1 $103 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" - cell $and $104 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cu_busy_o - connect \B \cu_shadown_i - connect \Y $103 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" - wire width 1 $105 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" - cell $and $106 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cu_busy_o - connect \B \cu_shadown_i - connect \Y $105 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" - wire width 1 $107 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" - cell $and $108 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cu_busy_o - connect \B \cu_shadown_i - connect \Y $107 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" - wire width 1 $109 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" - cell $and $110 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cu_busy_o - connect \B \cu_shadown_i - connect \Y $109 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351" - wire width 5 $111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351" - cell $and $112 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 5 - connect \A \req_l_q_req - connect \B { $101 $103 $105 $107 $109 } - connect \Y $111 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351" - wire width 5 $113 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351" - cell $and $114 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 5 - connect \A $111 - connect \B \cu_wrmask_o - connect \Y $113 - end - process $group_62 - assign \cu_wr__rel_o 5'00000 - assign \cu_wr__rel_o $113 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - wire width 1 $115 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - cell $and $116 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cu_wr__go_i [0] - connect \B \cu_busy_o - connect \Y $115 - end - process $group_63 - assign \dest1_o 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - switch { $115 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - case 1'1 - assign \dest1_o { \data_r0__o_ok \data_r0__o } [63:0] - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - wire width 1 $117 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - cell $and $118 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cu_wr__go_i [1] - connect \B \cu_busy_o - connect \Y $117 - end - process $group_64 - assign \dest2_o 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - switch { $117 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - case 1'1 - assign \dest2_o { \data_r1__fast1_ok \data_r1__fast1 } [63:0] - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - wire width 1 $119 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - cell $and $120 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cu_wr__go_i [2] - connect \B \cu_busy_o - connect \Y $119 - end - process $group_65 - assign \dest3_o 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - switch { $119 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - case 1'1 - assign \dest3_o { \data_r2__fast2_ok \data_r2__fast2 } [63:0] - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - wire width 1 $121 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - cell $and $122 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cu_wr__go_i [3] - connect \B \cu_busy_o - connect \Y $121 - end - process $group_66 - assign \dest4_o 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - switch { $121 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - case 1'1 - assign \dest4_o { \data_r3__nia_ok \data_r3__nia } [63:0] - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - wire width 1 $123 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - cell $and $124 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cu_wr__go_i [4] - connect \B \cu_busy_o - connect \Y $123 - end - process $group_67 - assign \dest5_o 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src 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- wire width 32 output 40 \logical_op__insn$19 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 output 41 \ra$20 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 output 42 \rb$21 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 1 output 43 \xer_so$22 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:20" - wire width 64 \a - process $group_0 - assign \a 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \a \ra - sync init - end - process $group_1 - assign \ra$20 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \ra$20 \a - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:39" - wire width 64 \b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:43" - wire width 64 $23 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:43" - cell $not $24 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \Y_WIDTH 64 - connect \A \rb - connect \Y $23 - end - process $group_2 - assign \b 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:42" - switch { \logical_op__invert_in } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:42" - case 1'1 - assign \b $23 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:44" - case - assign \b \rb - end - sync init - end - process $group_3 - assign \rb$21 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \rb$21 \b - sync init - end - process $group_4 - assign \xer_so$22 1'0 - assign \xer_so$22 \xer_so - sync init - end - process $group_5 - assign \muxid$1 2'00 - assign \muxid$1 \muxid - sync init - end - process $group_6 - assign \logical_op__insn_type$2 7'0000000 - assign \logical_op__fn_unit$3 11'00000000000 - assign \logical_op__imm_data__data$4 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \logical_op__imm_data__ok$5 1'0 - assign \logical_op__rc__rc$6 1'0 - assign \logical_op__rc__ok$7 1'0 - assign \logical_op__oe__oe$8 1'0 - assign \logical_op__oe__ok$9 1'0 - assign \logical_op__invert_in$10 1'0 - assign \logical_op__zero_a$11 1'0 - assign \logical_op__input_carry$12 2'00 - assign \logical_op__invert_out$13 1'0 - assign \logical_op__write_cr0$14 1'0 - assign \logical_op__output_carry$15 1'0 - assign \logical_op__is_32bit$16 1'0 - assign \logical_op__is_signed$17 1'0 - assign \logical_op__data_len$18 4'0000 - assign \logical_op__insn$19 32'00000000000000000000000000000000 - assign { \logical_op__insn$19 \logical_op__data_len$18 \logical_op__is_signed$17 \logical_op__is_32bit$16 \logical_op__output_carry$15 \logical_op__write_cr0$14 \logical_op__invert_out$13 \logical_op__input_carry$12 \logical_op__zero_a$11 \logical_op__invert_in$10 { \logical_op__oe__ok$9 \logical_op__oe__oe$8 } { \logical_op__rc__ok$7 \logical_op__rc__rc$6 } { \logical_op__imm_data__ok$5 \logical_op__imm_data__data$4 } \logical_op__fn_unit$3 \logical_op__insn_type$2 } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in { \logical_op__oe__ok \logical_op__oe__oe } { \logical_op__rc__ok \logical_op__rc__rc } { \logical_op__imm_data__ok \logical_op__imm_data__data } \logical_op__fn_unit \logical_op__insn_type } - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.logical0.alu_logical0.logical_pipe1.main.bpermd" -module \bpermd - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:54" - wire width 64 input 0 \rs - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:56" - wire width 64 input 1 \rb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:55" - wire width 64 output 2 \ra - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" - wire width 1 \rb64_0 - process $group_0 - assign \rb64_0 1'0 - assign \rb64_0 \rb [63] - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" - wire width 1 \rb64_1 - process $group_1 - assign \rb64_1 1'0 - assign \rb64_1 \rb [62] - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" - wire width 1 \rb64_2 - process $group_2 - assign \rb64_2 1'0 - assign \rb64_2 \rb [61] - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" - wire width 1 \rb64_3 - process $group_3 - assign \rb64_3 1'0 - assign \rb64_3 \rb [60] - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" - wire width 1 \rb64_4 - process $group_4 - assign \rb64_4 1'0 - assign \rb64_4 \rb [59] - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" - wire width 1 \rb64_5 - process $group_5 - assign \rb64_5 1'0 - assign \rb64_5 \rb [58] - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" - wire width 1 \rb64_6 - process $group_6 - assign \rb64_6 1'0 - assign \rb64_6 \rb [57] - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" - wire width 1 \rb64_7 - process $group_7 - assign \rb64_7 1'0 - assign \rb64_7 \rb [56] - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" - wire width 1 \rb64_8 - process $group_8 - assign \rb64_8 1'0 - assign \rb64_8 \rb [55] - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" - wire width 1 \rb64_9 - process $group_9 - assign \rb64_9 1'0 - assign \rb64_9 \rb [54] - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" - wire width 1 \rb64_10 - process $group_10 - assign \rb64_10 1'0 - assign \rb64_10 \rb [53] - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" - wire width 1 \rb64_11 - process $group_11 - assign \rb64_11 1'0 - assign \rb64_11 \rb [52] - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" - wire width 1 \rb64_12 - process $group_12 - assign \rb64_12 1'0 - assign \rb64_12 \rb [51] - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" - wire width 1 \rb64_13 - process $group_13 - assign \rb64_13 1'0 - assign \rb64_13 \rb [50] - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" - wire width 1 \rb64_14 - process $group_14 - assign \rb64_14 1'0 - assign \rb64_14 \rb [49] - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" - wire width 1 \rb64_15 - process $group_15 - assign \rb64_15 1'0 - assign \rb64_15 \rb [48] - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" - wire width 1 \rb64_16 - process $group_16 - assign \rb64_16 1'0 - assign \rb64_16 \rb [47] - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" - wire width 1 \rb64_17 - process $group_17 - assign \rb64_17 1'0 - assign \rb64_17 \rb [46] - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" - wire width 1 \rb64_18 - process $group_18 - assign \rb64_18 1'0 - assign \rb64_18 \rb [45] - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" - wire width 1 \rb64_19 - process $group_19 - assign \rb64_19 1'0 - assign \rb64_19 \rb [44] - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" - wire width 1 \rb64_20 - process $group_20 - assign \rb64_20 1'0 - assign \rb64_20 \rb [43] - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" - wire width 1 \rb64_21 - process $group_21 - assign \rb64_21 1'0 - assign \rb64_21 \rb [42] - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" - wire width 1 \rb64_22 - process $group_22 - assign \rb64_22 1'0 - assign \rb64_22 \rb [41] - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" - wire width 1 \rb64_23 - process $group_23 - assign \rb64_23 1'0 - assign \rb64_23 \rb [40] - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" - wire width 1 \rb64_24 - process $group_24 - assign \rb64_24 1'0 - assign \rb64_24 \rb [39] - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" - wire width 1 \rb64_25 - process $group_25 - assign \rb64_25 1'0 - assign \rb64_25 \rb [38] - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" - wire width 1 \rb64_26 - process $group_26 - assign \rb64_26 1'0 - assign \rb64_26 \rb [37] - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" - wire width 1 \rb64_27 - process $group_27 - assign \rb64_27 1'0 - assign \rb64_27 \rb [36] - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" - wire width 1 \rb64_28 - process $group_28 - assign \rb64_28 1'0 - assign \rb64_28 \rb [35] - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" - wire width 1 \rb64_29 - process $group_29 - assign \rb64_29 1'0 - assign \rb64_29 \rb [34] - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" - wire width 1 \rb64_30 - process $group_30 - assign \rb64_30 1'0 - assign \rb64_30 \rb [33] - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" - wire width 1 \rb64_31 - process $group_31 - assign \rb64_31 1'0 - assign \rb64_31 \rb [32] - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" - wire width 1 \rb64_32 - process $group_32 - assign \rb64_32 1'0 - assign \rb64_32 \rb [31] - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" - wire width 1 \rb64_33 - process $group_33 - assign \rb64_33 1'0 - assign \rb64_33 \rb [30] - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" - wire width 1 \rb64_34 - process $group_34 - assign \rb64_34 1'0 - assign \rb64_34 \rb [29] - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" - wire width 1 \rb64_35 - process $group_35 - assign \rb64_35 1'0 - assign \rb64_35 \rb [28] - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" - wire width 1 \rb64_36 - process $group_36 - assign \rb64_36 1'0 - assign \rb64_36 \rb [27] - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" - wire width 1 \rb64_37 - process $group_37 - assign \rb64_37 1'0 - assign \rb64_37 \rb [26] - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" - wire width 1 \rb64_38 - process $group_38 - assign \rb64_38 1'0 - assign \rb64_38 \rb [25] - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" - wire width 1 \rb64_39 - process $group_39 - assign \rb64_39 1'0 - assign \rb64_39 \rb [24] - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" - wire width 1 \rb64_40 - process $group_40 - assign \rb64_40 1'0 - assign \rb64_40 \rb [23] - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" - wire width 1 \rb64_41 - process $group_41 - assign \rb64_41 1'0 - assign \rb64_41 \rb [22] - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" - wire width 1 \rb64_42 - process $group_42 - assign \rb64_42 1'0 - assign \rb64_42 \rb [21] - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" - wire width 1 \rb64_43 - process $group_43 - assign \rb64_43 1'0 - assign \rb64_43 \rb [20] - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" - wire width 1 \rb64_44 - process $group_44 - assign \rb64_44 1'0 - assign \rb64_44 \rb [19] - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" - wire width 1 \rb64_45 - process $group_45 - assign \rb64_45 1'0 - assign \rb64_45 \rb [18] - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" - wire width 1 \rb64_46 - process $group_46 - assign \rb64_46 1'0 - assign \rb64_46 \rb [17] - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" - wire width 1 \rb64_47 - process $group_47 - assign \rb64_47 1'0 - assign \rb64_47 \rb [16] - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" - wire width 1 \rb64_48 - process $group_48 - assign \rb64_48 1'0 - assign \rb64_48 \rb [15] - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" - wire width 1 \rb64_49 - process $group_49 - assign \rb64_49 1'0 - assign \rb64_49 \rb [14] - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" - wire width 1 \rb64_50 - process $group_50 - assign \rb64_50 1'0 - assign \rb64_50 \rb [13] - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" - wire width 1 \rb64_51 - process $group_51 - assign \rb64_51 1'0 - assign \rb64_51 \rb [12] - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" - wire width 1 \rb64_52 - process $group_52 - assign \rb64_52 1'0 - assign \rb64_52 \rb [11] - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" - wire width 1 \rb64_53 - process $group_53 - assign \rb64_53 1'0 - assign \rb64_53 \rb [10] - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" - wire width 1 \rb64_54 - process $group_54 - assign \rb64_54 1'0 - assign \rb64_54 \rb [9] - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" - wire width 1 \rb64_55 - process $group_55 - assign \rb64_55 1'0 - assign \rb64_55 \rb [8] - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" - wire width 1 \rb64_56 - process $group_56 - assign \rb64_56 1'0 - assign \rb64_56 \rb [7] - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" - wire width 1 \rb64_57 - process $group_57 - assign \rb64_57 1'0 - assign \rb64_57 \rb [6] - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" - wire width 1 \rb64_58 - process $group_58 - assign \rb64_58 1'0 - assign \rb64_58 \rb [5] - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" - wire width 1 \rb64_59 - process $group_59 - assign \rb64_59 1'0 - assign \rb64_59 \rb [4] - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" - wire width 1 \rb64_60 - process $group_60 - assign \rb64_60 1'0 - assign \rb64_60 \rb [3] - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" - wire width 1 \rb64_61 - process $group_61 - assign \rb64_61 1'0 - assign \rb64_61 \rb [2] - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" - wire width 1 \rb64_62 - process $group_62 - assign \rb64_62 1'0 - assign \rb64_62 \rb [1] - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:61" - wire width 1 \rb64_63 - process $group_63 - assign \rb64_63 1'0 - assign \rb64_63 \rb [0] - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:67" - wire width 8 \idx_0 - process $group_64 - assign \idx_0 8'00000000 - assign \idx_0 \rs [7:0] - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:60" - wire width 64 \perm - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69" - cell $lt $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A \idx_0 - connect \B 7'1000000 - connect \Y $1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:67" - wire width 8 \idx_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69" - wire width 1 $3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69" - cell $lt $4 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A \idx_1 - connect \B 7'1000000 - connect \Y $3 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:67" - wire width 8 \idx_2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69" - wire width 1 $5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69" - cell $lt $6 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A \idx_2 - connect \B 7'1000000 - connect \Y $5 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:67" - wire width 8 \idx_3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69" - wire width 1 $7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69" - cell $lt $8 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A \idx_3 - connect \B 7'1000000 - connect \Y $7 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:67" - wire width 8 \idx_4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69" - wire width 1 $9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69" - cell $lt $10 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A \idx_4 - connect \B 7'1000000 - connect \Y $9 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:67" - wire width 8 \idx_5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69" - wire width 1 $11 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69" - cell $lt $12 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A \idx_5 - connect \B 7'1000000 - connect \Y $11 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:67" - wire width 8 \idx_6 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69" - wire width 1 $13 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69" - cell $lt $14 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A \idx_6 - connect \B 7'1000000 - connect \Y $13 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:67" - wire width 8 \idx_7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69" - wire width 1 $15 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69" - cell $lt $16 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A \idx_7 - connect \B 7'1000000 - connect \Y $15 - end - process $group_65 - assign \perm 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69" - switch { $1 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:70" - switch \idx_0 - case 8'00000000 - assign \perm [0] \rb64_0 - case 8'00000001 - assign \perm [0] \rb64_1 - case 8'00000010 - assign \perm [0] \rb64_2 - case 8'00000011 - assign \perm [0] \rb64_3 - case 8'00000100 - assign \perm [0] \rb64_4 - case 8'00000101 - assign \perm [0] \rb64_5 - case 8'00000110 - assign \perm [0] \rb64_6 - case 8'00000111 - assign \perm [0] \rb64_7 - case 8'00001000 - assign \perm [0] \rb64_8 - case 8'00001001 - assign \perm [0] \rb64_9 - case 8'00001010 - assign \perm [0] \rb64_10 - case 8'00001011 - assign \perm [0] \rb64_11 - case 8'00001100 - assign \perm [0] \rb64_12 - case 8'00001101 - assign \perm [0] \rb64_13 - case 8'00001110 - assign \perm [0] \rb64_14 - case 8'00001111 - assign \perm [0] \rb64_15 - case 8'00010000 - assign \perm [0] \rb64_16 - case 8'00010001 - assign \perm [0] \rb64_17 - case 8'00010010 - assign \perm [0] \rb64_18 - case 8'00010011 - assign \perm [0] \rb64_19 - case 8'00010100 - assign \perm [0] \rb64_20 - case 8'00010101 - assign \perm [0] \rb64_21 - case 8'00010110 - assign \perm [0] \rb64_22 - case 8'00010111 - assign \perm [0] \rb64_23 - case 8'00011000 - assign \perm [0] \rb64_24 - case 8'00011001 - assign \perm [0] \rb64_25 - case 8'00011010 - assign \perm [0] \rb64_26 - case 8'00011011 - assign \perm [0] \rb64_27 - case 8'00011100 - assign \perm [0] \rb64_28 - case 8'00011101 - assign \perm [0] \rb64_29 - case 8'00011110 - assign \perm [0] \rb64_30 - case 8'00011111 - assign \perm [0] \rb64_31 - case 8'00100000 - assign \perm [0] \rb64_32 - case 8'00100001 - assign \perm [0] \rb64_33 - case 8'00100010 - assign \perm [0] \rb64_34 - case 8'00100011 - assign \perm [0] \rb64_35 - case 8'00100100 - assign \perm [0] \rb64_36 - case 8'00100101 - assign \perm [0] \rb64_37 - case 8'00100110 - assign \perm [0] \rb64_38 - case 8'00100111 - assign \perm [0] \rb64_39 - case 8'00101000 - assign \perm [0] \rb64_40 - case 8'00101001 - assign \perm [0] \rb64_41 - case 8'00101010 - assign \perm [0] \rb64_42 - case 8'00101011 - assign \perm [0] \rb64_43 - case 8'00101100 - assign \perm [0] \rb64_44 - case 8'00101101 - assign \perm [0] \rb64_45 - case 8'00101110 - assign \perm [0] \rb64_46 - case 8'00101111 - assign \perm [0] \rb64_47 - case 8'00110000 - assign \perm [0] \rb64_48 - case 8'00110001 - assign \perm [0] \rb64_49 - case 8'00110010 - assign \perm [0] \rb64_50 - case 8'00110011 - assign \perm [0] \rb64_51 - case 8'00110100 - assign \perm [0] \rb64_52 - case 8'00110101 - assign \perm [0] \rb64_53 - case 8'00110110 - assign \perm [0] \rb64_54 - case 8'00110111 - assign \perm [0] \rb64_55 - case 8'00111000 - assign \perm [0] \rb64_56 - case 8'00111001 - assign \perm [0] \rb64_57 - case 8'00111010 - assign \perm [0] \rb64_58 - case 8'00111011 - assign \perm [0] \rb64_59 - case 8'00111100 - assign \perm [0] \rb64_60 - case 8'00111101 - assign \perm [0] \rb64_61 - case 8'00111110 - assign \perm [0] \rb64_62 - case 8'-------- - assign \perm [0] \rb64_63 - end - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69" - switch { $3 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:70" - switch \idx_1 - case 8'00000000 - assign \perm [1] \rb64_0 - case 8'00000001 - assign \perm [1] \rb64_1 - case 8'00000010 - assign \perm [1] \rb64_2 - case 8'00000011 - assign \perm [1] \rb64_3 - case 8'00000100 - assign \perm [1] \rb64_4 - case 8'00000101 - assign \perm [1] \rb64_5 - case 8'00000110 - assign \perm [1] \rb64_6 - case 8'00000111 - assign \perm [1] \rb64_7 - case 8'00001000 - assign \perm [1] \rb64_8 - case 8'00001001 - assign \perm [1] \rb64_9 - case 8'00001010 - assign \perm [1] \rb64_10 - case 8'00001011 - assign \perm [1] \rb64_11 - case 8'00001100 - assign \perm [1] \rb64_12 - case 8'00001101 - assign \perm [1] \rb64_13 - case 8'00001110 - assign \perm [1] \rb64_14 - case 8'00001111 - assign \perm [1] \rb64_15 - case 8'00010000 - assign \perm [1] \rb64_16 - case 8'00010001 - assign \perm [1] \rb64_17 - case 8'00010010 - assign \perm [1] \rb64_18 - case 8'00010011 - assign \perm [1] \rb64_19 - case 8'00010100 - assign \perm [1] \rb64_20 - case 8'00010101 - assign \perm [1] \rb64_21 - case 8'00010110 - assign \perm [1] \rb64_22 - case 8'00010111 - assign \perm [1] \rb64_23 - case 8'00011000 - assign \perm [1] \rb64_24 - case 8'00011001 - assign \perm [1] \rb64_25 - case 8'00011010 - assign \perm [1] \rb64_26 - case 8'00011011 - assign \perm [1] \rb64_27 - case 8'00011100 - assign \perm [1] \rb64_28 - case 8'00011101 - assign \perm [1] \rb64_29 - case 8'00011110 - assign \perm [1] \rb64_30 - case 8'00011111 - assign \perm [1] \rb64_31 - case 8'00100000 - assign \perm [1] \rb64_32 - case 8'00100001 - assign \perm [1] \rb64_33 - case 8'00100010 - assign \perm [1] \rb64_34 - case 8'00100011 - assign \perm [1] \rb64_35 - case 8'00100100 - assign \perm [1] \rb64_36 - case 8'00100101 - assign \perm [1] \rb64_37 - case 8'00100110 - assign \perm [1] \rb64_38 - case 8'00100111 - assign \perm [1] \rb64_39 - case 8'00101000 - assign \perm [1] \rb64_40 - case 8'00101001 - assign \perm [1] \rb64_41 - case 8'00101010 - assign \perm [1] \rb64_42 - case 8'00101011 - assign \perm [1] \rb64_43 - case 8'00101100 - assign \perm [1] \rb64_44 - case 8'00101101 - assign \perm [1] \rb64_45 - case 8'00101110 - assign \perm [1] \rb64_46 - case 8'00101111 - assign \perm [1] \rb64_47 - case 8'00110000 - assign \perm [1] \rb64_48 - case 8'00110001 - assign \perm [1] \rb64_49 - case 8'00110010 - assign \perm [1] \rb64_50 - case 8'00110011 - assign \perm [1] \rb64_51 - case 8'00110100 - assign \perm [1] \rb64_52 - case 8'00110101 - assign \perm [1] \rb64_53 - case 8'00110110 - assign \perm [1] \rb64_54 - case 8'00110111 - assign \perm [1] \rb64_55 - case 8'00111000 - assign \perm [1] \rb64_56 - case 8'00111001 - assign \perm [1] \rb64_57 - case 8'00111010 - assign \perm [1] \rb64_58 - case 8'00111011 - assign \perm [1] \rb64_59 - case 8'00111100 - assign \perm [1] \rb64_60 - case 8'00111101 - assign \perm [1] \rb64_61 - case 8'00111110 - assign \perm [1] \rb64_62 - case 8'-------- - assign \perm [1] \rb64_63 - end - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69" - switch { $5 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:70" - switch \idx_2 - case 8'00000000 - assign \perm [2] \rb64_0 - case 8'00000001 - assign \perm [2] \rb64_1 - case 8'00000010 - assign \perm [2] \rb64_2 - case 8'00000011 - assign \perm [2] \rb64_3 - case 8'00000100 - assign \perm [2] \rb64_4 - case 8'00000101 - assign \perm [2] \rb64_5 - case 8'00000110 - assign \perm [2] \rb64_6 - case 8'00000111 - assign \perm [2] \rb64_7 - case 8'00001000 - assign \perm [2] \rb64_8 - case 8'00001001 - assign \perm [2] \rb64_9 - case 8'00001010 - assign \perm [2] \rb64_10 - case 8'00001011 - assign \perm [2] \rb64_11 - case 8'00001100 - assign \perm [2] \rb64_12 - case 8'00001101 - assign \perm [2] \rb64_13 - case 8'00001110 - assign \perm [2] \rb64_14 - case 8'00001111 - assign \perm [2] \rb64_15 - case 8'00010000 - assign \perm [2] \rb64_16 - case 8'00010001 - assign \perm [2] \rb64_17 - case 8'00010010 - assign \perm [2] \rb64_18 - case 8'00010011 - assign \perm [2] \rb64_19 - case 8'00010100 - assign \perm [2] \rb64_20 - case 8'00010101 - assign \perm [2] \rb64_21 - case 8'00010110 - assign \perm [2] \rb64_22 - case 8'00010111 - assign \perm [2] \rb64_23 - case 8'00011000 - assign \perm [2] \rb64_24 - case 8'00011001 - assign \perm [2] \rb64_25 - case 8'00011010 - assign \perm [2] \rb64_26 - case 8'00011011 - assign \perm [2] \rb64_27 - case 8'00011100 - assign \perm [2] \rb64_28 - case 8'00011101 - assign \perm [2] \rb64_29 - case 8'00011110 - assign \perm [2] \rb64_30 - case 8'00011111 - assign \perm [2] \rb64_31 - case 8'00100000 - assign \perm [2] \rb64_32 - case 8'00100001 - assign \perm [2] \rb64_33 - case 8'00100010 - assign \perm [2] \rb64_34 - case 8'00100011 - assign \perm [2] \rb64_35 - case 8'00100100 - assign \perm [2] \rb64_36 - case 8'00100101 - assign \perm [2] \rb64_37 - case 8'00100110 - assign \perm [2] \rb64_38 - case 8'00100111 - assign \perm [2] \rb64_39 - case 8'00101000 - assign \perm [2] \rb64_40 - case 8'00101001 - assign \perm [2] \rb64_41 - case 8'00101010 - assign \perm [2] \rb64_42 - case 8'00101011 - assign \perm [2] \rb64_43 - case 8'00101100 - assign \perm [2] \rb64_44 - case 8'00101101 - assign \perm [2] \rb64_45 - case 8'00101110 - assign \perm [2] \rb64_46 - case 8'00101111 - assign \perm [2] \rb64_47 - case 8'00110000 - assign \perm [2] \rb64_48 - case 8'00110001 - assign \perm [2] \rb64_49 - case 8'00110010 - assign \perm [2] \rb64_50 - case 8'00110011 - assign \perm [2] \rb64_51 - case 8'00110100 - assign \perm [2] \rb64_52 - case 8'00110101 - assign \perm [2] \rb64_53 - case 8'00110110 - assign \perm [2] \rb64_54 - case 8'00110111 - assign \perm [2] \rb64_55 - case 8'00111000 - assign \perm [2] \rb64_56 - case 8'00111001 - assign \perm [2] \rb64_57 - case 8'00111010 - assign \perm [2] \rb64_58 - case 8'00111011 - assign \perm [2] \rb64_59 - case 8'00111100 - assign \perm [2] \rb64_60 - case 8'00111101 - assign \perm [2] \rb64_61 - case 8'00111110 - assign \perm [2] \rb64_62 - case 8'-------- - assign \perm [2] \rb64_63 - end - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69" - switch { $7 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:70" - switch \idx_3 - case 8'00000000 - assign \perm [3] \rb64_0 - case 8'00000001 - assign \perm [3] \rb64_1 - case 8'00000010 - assign \perm [3] \rb64_2 - case 8'00000011 - assign \perm [3] \rb64_3 - case 8'00000100 - assign \perm [3] \rb64_4 - case 8'00000101 - assign \perm [3] \rb64_5 - case 8'00000110 - assign \perm [3] \rb64_6 - case 8'00000111 - assign \perm [3] \rb64_7 - case 8'00001000 - assign \perm [3] \rb64_8 - case 8'00001001 - assign \perm [3] \rb64_9 - case 8'00001010 - assign \perm [3] \rb64_10 - case 8'00001011 - assign \perm [3] \rb64_11 - case 8'00001100 - assign \perm [3] \rb64_12 - case 8'00001101 - assign \perm [3] \rb64_13 - case 8'00001110 - assign \perm [3] \rb64_14 - case 8'00001111 - assign \perm [3] \rb64_15 - case 8'00010000 - assign \perm [3] \rb64_16 - case 8'00010001 - assign \perm [3] \rb64_17 - case 8'00010010 - assign \perm [3] \rb64_18 - case 8'00010011 - assign \perm [3] \rb64_19 - case 8'00010100 - assign \perm [3] \rb64_20 - case 8'00010101 - assign \perm [3] \rb64_21 - case 8'00010110 - assign \perm [3] \rb64_22 - case 8'00010111 - assign \perm [3] \rb64_23 - case 8'00011000 - assign \perm [3] \rb64_24 - case 8'00011001 - assign \perm [3] \rb64_25 - case 8'00011010 - assign \perm [3] \rb64_26 - case 8'00011011 - assign \perm [3] \rb64_27 - case 8'00011100 - assign \perm [3] \rb64_28 - case 8'00011101 - assign \perm [3] \rb64_29 - case 8'00011110 - assign \perm [3] \rb64_30 - case 8'00011111 - assign \perm [3] \rb64_31 - case 8'00100000 - assign \perm [3] \rb64_32 - case 8'00100001 - assign \perm [3] \rb64_33 - case 8'00100010 - assign \perm [3] \rb64_34 - case 8'00100011 - assign \perm [3] \rb64_35 - case 8'00100100 - assign \perm [3] \rb64_36 - case 8'00100101 - assign \perm [3] \rb64_37 - case 8'00100110 - assign \perm [3] \rb64_38 - case 8'00100111 - assign \perm [3] \rb64_39 - case 8'00101000 - assign \perm [3] \rb64_40 - case 8'00101001 - assign \perm [3] \rb64_41 - case 8'00101010 - assign \perm [3] \rb64_42 - case 8'00101011 - assign \perm [3] \rb64_43 - case 8'00101100 - assign \perm [3] \rb64_44 - case 8'00101101 - assign \perm [3] \rb64_45 - case 8'00101110 - assign \perm [3] \rb64_46 - case 8'00101111 - assign \perm [3] \rb64_47 - case 8'00110000 - assign \perm [3] \rb64_48 - case 8'00110001 - assign \perm [3] \rb64_49 - case 8'00110010 - assign \perm [3] \rb64_50 - case 8'00110011 - assign \perm [3] \rb64_51 - case 8'00110100 - assign \perm [3] \rb64_52 - case 8'00110101 - assign \perm [3] \rb64_53 - case 8'00110110 - assign \perm [3] \rb64_54 - case 8'00110111 - assign \perm [3] \rb64_55 - case 8'00111000 - assign \perm [3] \rb64_56 - case 8'00111001 - assign \perm [3] \rb64_57 - case 8'00111010 - assign \perm [3] \rb64_58 - case 8'00111011 - assign \perm [3] \rb64_59 - case 8'00111100 - assign \perm [3] \rb64_60 - case 8'00111101 - assign \perm [3] \rb64_61 - case 8'00111110 - assign \perm [3] \rb64_62 - case 8'-------- - assign \perm [3] \rb64_63 - end - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69" - switch { $9 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:70" - switch \idx_4 - case 8'00000000 - assign \perm [4] \rb64_0 - case 8'00000001 - assign \perm [4] \rb64_1 - case 8'00000010 - assign \perm [4] \rb64_2 - case 8'00000011 - assign \perm [4] \rb64_3 - case 8'00000100 - assign \perm [4] \rb64_4 - case 8'00000101 - assign \perm [4] \rb64_5 - case 8'00000110 - assign \perm [4] \rb64_6 - case 8'00000111 - assign \perm [4] \rb64_7 - case 8'00001000 - assign \perm [4] \rb64_8 - case 8'00001001 - assign \perm [4] \rb64_9 - case 8'00001010 - assign \perm [4] \rb64_10 - case 8'00001011 - assign \perm [4] \rb64_11 - case 8'00001100 - assign \perm [4] \rb64_12 - case 8'00001101 - assign \perm [4] \rb64_13 - case 8'00001110 - assign \perm [4] \rb64_14 - case 8'00001111 - assign \perm [4] \rb64_15 - case 8'00010000 - assign \perm [4] \rb64_16 - case 8'00010001 - assign \perm [4] \rb64_17 - case 8'00010010 - assign \perm [4] \rb64_18 - case 8'00010011 - assign \perm [4] \rb64_19 - case 8'00010100 - assign \perm [4] \rb64_20 - case 8'00010101 - assign \perm [4] \rb64_21 - case 8'00010110 - assign \perm [4] \rb64_22 - case 8'00010111 - assign \perm [4] \rb64_23 - case 8'00011000 - assign \perm [4] \rb64_24 - case 8'00011001 - assign \perm [4] \rb64_25 - case 8'00011010 - assign \perm [4] \rb64_26 - case 8'00011011 - assign \perm [4] \rb64_27 - case 8'00011100 - assign \perm [4] \rb64_28 - case 8'00011101 - assign \perm [4] \rb64_29 - case 8'00011110 - assign \perm [4] \rb64_30 - case 8'00011111 - assign \perm [4] \rb64_31 - case 8'00100000 - assign \perm [4] \rb64_32 - case 8'00100001 - assign \perm [4] \rb64_33 - case 8'00100010 - assign \perm [4] \rb64_34 - case 8'00100011 - assign \perm [4] \rb64_35 - case 8'00100100 - assign \perm [4] \rb64_36 - case 8'00100101 - assign \perm [4] \rb64_37 - case 8'00100110 - assign \perm [4] \rb64_38 - case 8'00100111 - assign \perm [4] \rb64_39 - case 8'00101000 - assign \perm [4] \rb64_40 - case 8'00101001 - assign \perm [4] \rb64_41 - case 8'00101010 - assign \perm [4] \rb64_42 - case 8'00101011 - assign \perm [4] \rb64_43 - case 8'00101100 - assign \perm [4] \rb64_44 - case 8'00101101 - assign \perm [4] \rb64_45 - case 8'00101110 - assign \perm [4] \rb64_46 - case 8'00101111 - assign \perm [4] \rb64_47 - case 8'00110000 - assign \perm [4] \rb64_48 - case 8'00110001 - assign \perm [4] \rb64_49 - case 8'00110010 - assign \perm [4] \rb64_50 - case 8'00110011 - assign \perm [4] \rb64_51 - case 8'00110100 - assign \perm [4] \rb64_52 - case 8'00110101 - assign \perm [4] \rb64_53 - case 8'00110110 - assign \perm [4] \rb64_54 - case 8'00110111 - assign \perm [4] \rb64_55 - case 8'00111000 - assign \perm [4] \rb64_56 - case 8'00111001 - assign \perm [4] \rb64_57 - case 8'00111010 - assign \perm [4] \rb64_58 - case 8'00111011 - assign \perm [4] \rb64_59 - case 8'00111100 - assign \perm [4] \rb64_60 - case 8'00111101 - assign \perm [4] \rb64_61 - case 8'00111110 - assign \perm [4] \rb64_62 - case 8'-------- - assign \perm [4] \rb64_63 - end - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69" - switch { $11 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:70" - switch \idx_5 - case 8'00000000 - assign \perm [5] \rb64_0 - case 8'00000001 - assign \perm [5] \rb64_1 - case 8'00000010 - assign \perm [5] \rb64_2 - case 8'00000011 - assign \perm [5] \rb64_3 - case 8'00000100 - assign \perm [5] \rb64_4 - case 8'00000101 - assign \perm [5] \rb64_5 - case 8'00000110 - assign \perm [5] \rb64_6 - case 8'00000111 - assign \perm [5] \rb64_7 - case 8'00001000 - assign \perm [5] \rb64_8 - case 8'00001001 - assign \perm [5] \rb64_9 - case 8'00001010 - assign \perm [5] \rb64_10 - case 8'00001011 - assign \perm [5] \rb64_11 - case 8'00001100 - assign \perm [5] \rb64_12 - case 8'00001101 - assign \perm [5] \rb64_13 - case 8'00001110 - assign \perm [5] \rb64_14 - case 8'00001111 - assign \perm [5] \rb64_15 - case 8'00010000 - assign \perm [5] \rb64_16 - case 8'00010001 - assign \perm [5] \rb64_17 - case 8'00010010 - assign \perm [5] \rb64_18 - case 8'00010011 - assign \perm [5] \rb64_19 - case 8'00010100 - assign \perm [5] \rb64_20 - case 8'00010101 - assign \perm [5] \rb64_21 - case 8'00010110 - assign \perm [5] \rb64_22 - case 8'00010111 - assign \perm [5] \rb64_23 - case 8'00011000 - assign \perm [5] \rb64_24 - case 8'00011001 - assign \perm [5] \rb64_25 - case 8'00011010 - assign \perm [5] \rb64_26 - case 8'00011011 - assign \perm [5] \rb64_27 - case 8'00011100 - assign \perm [5] \rb64_28 - case 8'00011101 - assign \perm [5] \rb64_29 - case 8'00011110 - assign \perm [5] \rb64_30 - case 8'00011111 - assign \perm [5] \rb64_31 - case 8'00100000 - assign \perm [5] \rb64_32 - case 8'00100001 - assign \perm [5] \rb64_33 - case 8'00100010 - assign \perm [5] \rb64_34 - case 8'00100011 - assign \perm [5] \rb64_35 - case 8'00100100 - assign \perm [5] \rb64_36 - case 8'00100101 - assign \perm [5] \rb64_37 - case 8'00100110 - assign \perm [5] \rb64_38 - case 8'00100111 - assign \perm [5] \rb64_39 - case 8'00101000 - assign \perm [5] \rb64_40 - case 8'00101001 - assign \perm [5] \rb64_41 - case 8'00101010 - assign \perm [5] \rb64_42 - case 8'00101011 - assign \perm [5] \rb64_43 - case 8'00101100 - assign \perm [5] \rb64_44 - case 8'00101101 - assign \perm [5] \rb64_45 - case 8'00101110 - assign \perm [5] \rb64_46 - case 8'00101111 - assign \perm [5] \rb64_47 - case 8'00110000 - assign \perm [5] \rb64_48 - case 8'00110001 - assign \perm [5] \rb64_49 - case 8'00110010 - assign \perm [5] \rb64_50 - case 8'00110011 - assign \perm [5] \rb64_51 - case 8'00110100 - assign \perm [5] \rb64_52 - case 8'00110101 - assign \perm [5] \rb64_53 - case 8'00110110 - assign \perm [5] \rb64_54 - case 8'00110111 - assign \perm [5] \rb64_55 - case 8'00111000 - assign \perm [5] \rb64_56 - case 8'00111001 - assign \perm [5] \rb64_57 - case 8'00111010 - assign \perm [5] \rb64_58 - case 8'00111011 - assign \perm [5] \rb64_59 - case 8'00111100 - assign \perm [5] \rb64_60 - case 8'00111101 - assign \perm [5] \rb64_61 - case 8'00111110 - assign \perm [5] \rb64_62 - case 8'-------- - assign \perm [5] \rb64_63 - end - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69" - switch { $13 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:70" - switch \idx_6 - case 8'00000000 - assign \perm [6] \rb64_0 - case 8'00000001 - assign \perm [6] \rb64_1 - case 8'00000010 - assign \perm [6] \rb64_2 - case 8'00000011 - assign \perm [6] \rb64_3 - case 8'00000100 - assign \perm [6] \rb64_4 - case 8'00000101 - assign \perm [6] \rb64_5 - case 8'00000110 - assign \perm [6] \rb64_6 - case 8'00000111 - assign \perm [6] \rb64_7 - case 8'00001000 - assign \perm [6] \rb64_8 - case 8'00001001 - assign \perm [6] \rb64_9 - case 8'00001010 - assign \perm [6] \rb64_10 - case 8'00001011 - assign \perm [6] \rb64_11 - case 8'00001100 - assign \perm [6] \rb64_12 - case 8'00001101 - assign \perm [6] \rb64_13 - case 8'00001110 - assign \perm [6] \rb64_14 - case 8'00001111 - assign \perm [6] \rb64_15 - case 8'00010000 - assign \perm [6] \rb64_16 - case 8'00010001 - assign \perm [6] \rb64_17 - case 8'00010010 - assign \perm [6] \rb64_18 - case 8'00010011 - assign \perm [6] \rb64_19 - case 8'00010100 - assign \perm [6] \rb64_20 - case 8'00010101 - assign \perm [6] \rb64_21 - case 8'00010110 - assign \perm [6] \rb64_22 - case 8'00010111 - assign \perm [6] \rb64_23 - case 8'00011000 - assign \perm [6] \rb64_24 - case 8'00011001 - assign \perm [6] \rb64_25 - case 8'00011010 - assign \perm [6] \rb64_26 - case 8'00011011 - assign \perm [6] \rb64_27 - case 8'00011100 - assign \perm [6] \rb64_28 - case 8'00011101 - assign \perm [6] \rb64_29 - case 8'00011110 - assign \perm [6] \rb64_30 - case 8'00011111 - assign \perm [6] \rb64_31 - case 8'00100000 - assign \perm [6] \rb64_32 - case 8'00100001 - assign \perm [6] \rb64_33 - case 8'00100010 - assign \perm [6] \rb64_34 - case 8'00100011 - assign \perm [6] \rb64_35 - case 8'00100100 - assign \perm [6] \rb64_36 - case 8'00100101 - assign \perm [6] \rb64_37 - case 8'00100110 - assign \perm [6] \rb64_38 - case 8'00100111 - assign \perm [6] \rb64_39 - case 8'00101000 - assign \perm [6] \rb64_40 - case 8'00101001 - assign \perm [6] \rb64_41 - case 8'00101010 - assign \perm [6] \rb64_42 - case 8'00101011 - assign \perm [6] \rb64_43 - case 8'00101100 - assign \perm [6] \rb64_44 - case 8'00101101 - assign \perm [6] \rb64_45 - case 8'00101110 - assign \perm [6] \rb64_46 - case 8'00101111 - assign \perm [6] \rb64_47 - case 8'00110000 - assign \perm [6] \rb64_48 - case 8'00110001 - assign \perm [6] \rb64_49 - case 8'00110010 - assign \perm [6] \rb64_50 - case 8'00110011 - assign \perm [6] \rb64_51 - case 8'00110100 - assign \perm [6] \rb64_52 - case 8'00110101 - assign \perm [6] \rb64_53 - case 8'00110110 - assign \perm [6] \rb64_54 - case 8'00110111 - assign \perm [6] \rb64_55 - case 8'00111000 - assign \perm [6] \rb64_56 - case 8'00111001 - assign \perm [6] \rb64_57 - case 8'00111010 - assign \perm [6] \rb64_58 - case 8'00111011 - assign \perm [6] \rb64_59 - case 8'00111100 - assign \perm [6] \rb64_60 - case 8'00111101 - assign \perm [6] \rb64_61 - case 8'00111110 - assign \perm [6] \rb64_62 - case 8'-------- - assign \perm [6] \rb64_63 - end - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69" - switch { $15 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:69" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:70" - switch \idx_7 - case 8'00000000 - assign \perm [7] \rb64_0 - case 8'00000001 - assign \perm [7] \rb64_1 - case 8'00000010 - assign \perm [7] \rb64_2 - case 8'00000011 - assign \perm [7] \rb64_3 - case 8'00000100 - assign \perm [7] \rb64_4 - case 8'00000101 - assign \perm [7] \rb64_5 - case 8'00000110 - assign \perm [7] \rb64_6 - case 8'00000111 - assign \perm [7] \rb64_7 - case 8'00001000 - assign \perm [7] \rb64_8 - case 8'00001001 - assign \perm [7] \rb64_9 - case 8'00001010 - assign \perm [7] \rb64_10 - case 8'00001011 - assign \perm [7] \rb64_11 - case 8'00001100 - assign \perm [7] \rb64_12 - case 8'00001101 - assign \perm [7] \rb64_13 - case 8'00001110 - assign \perm [7] \rb64_14 - case 8'00001111 - assign \perm [7] \rb64_15 - case 8'00010000 - assign \perm [7] \rb64_16 - case 8'00010001 - assign \perm [7] \rb64_17 - case 8'00010010 - assign \perm [7] \rb64_18 - case 8'00010011 - assign \perm [7] \rb64_19 - case 8'00010100 - assign \perm [7] \rb64_20 - case 8'00010101 - assign \perm [7] \rb64_21 - case 8'00010110 - assign \perm [7] \rb64_22 - case 8'00010111 - assign \perm [7] \rb64_23 - case 8'00011000 - assign \perm [7] \rb64_24 - case 8'00011001 - assign \perm [7] \rb64_25 - case 8'00011010 - assign \perm [7] \rb64_26 - case 8'00011011 - assign \perm [7] \rb64_27 - case 8'00011100 - assign \perm [7] \rb64_28 - case 8'00011101 - assign \perm [7] \rb64_29 - case 8'00011110 - assign \perm [7] \rb64_30 - case 8'00011111 - assign \perm [7] \rb64_31 - case 8'00100000 - assign \perm [7] \rb64_32 - case 8'00100001 - assign \perm [7] \rb64_33 - case 8'00100010 - assign \perm [7] \rb64_34 - case 8'00100011 - assign \perm [7] \rb64_35 - case 8'00100100 - assign \perm [7] \rb64_36 - case 8'00100101 - assign \perm [7] \rb64_37 - case 8'00100110 - assign \perm [7] \rb64_38 - case 8'00100111 - assign \perm [7] \rb64_39 - case 8'00101000 - assign \perm [7] \rb64_40 - case 8'00101001 - assign \perm [7] \rb64_41 - case 8'00101010 - assign \perm [7] \rb64_42 - case 8'00101011 - assign \perm [7] \rb64_43 - case 8'00101100 - assign \perm [7] \rb64_44 - case 8'00101101 - assign \perm [7] \rb64_45 - case 8'00101110 - assign \perm [7] \rb64_46 - case 8'00101111 - assign \perm [7] \rb64_47 - case 8'00110000 - assign \perm [7] \rb64_48 - case 8'00110001 - assign \perm [7] \rb64_49 - case 8'00110010 - assign \perm [7] \rb64_50 - case 8'00110011 - assign \perm [7] \rb64_51 - case 8'00110100 - assign \perm [7] \rb64_52 - case 8'00110101 - assign \perm [7] \rb64_53 - case 8'00110110 - assign \perm [7] \rb64_54 - case 8'00110111 - assign \perm [7] \rb64_55 - case 8'00111000 - assign \perm [7] \rb64_56 - case 8'00111001 - assign \perm [7] \rb64_57 - case 8'00111010 - assign \perm [7] \rb64_58 - case 8'00111011 - assign \perm [7] \rb64_59 - case 8'00111100 - assign \perm [7] \rb64_60 - case 8'00111101 - assign \perm [7] \rb64_61 - case 8'00111110 - assign \perm [7] \rb64_62 - case 8'-------- - assign \perm [7] \rb64_63 - end - end - sync init - end - process $group_66 - assign \idx_1 8'00000000 - assign \idx_1 \rs [15:8] - sync init - end - process $group_67 - assign \idx_2 8'00000000 - assign \idx_2 \rs [23:16] - sync init - end - process $group_68 - assign \idx_3 8'00000000 - assign \idx_3 \rs [31:24] - sync init - end - process $group_69 - assign \idx_4 8'00000000 - assign \idx_4 \rs [39:32] - sync init - end - process $group_70 - assign \idx_5 8'00000000 - assign \idx_5 \rs [47:40] - sync init - end - process $group_71 - assign \idx_6 8'00000000 - assign \idx_6 \rs [55:48] - sync init - end - process $group_72 - assign \idx_7 8'00000000 - assign \idx_7 \rs [63:56] - sync init - end - process $group_73 - assign \ra 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \ra [7:0] \perm [7:0] - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.logical0.alu_logical0.logical_pipe1.main.popcount" -module \popcount - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:27" - wire width 64 input 0 \a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:29" - wire width 64 input 1 \data_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:30" - wire width 64 output 2 \o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - wire width 2 \pop_2_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - wire width 3 $1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - wire width 3 $2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $3 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 3 - connect \A { 1'0 \a [0] } - connect \B { 1'0 \a [1] } - connect \Y $2 - end - connect $1 $2 - process $group_0 - assign \pop_2_0 2'00 - assign \pop_2_0 $1 [1:0] - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - wire width 2 \pop_2_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - wire width 3 $4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - wire width 3 $5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $6 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 3 - connect \A { 1'0 \a [2] } - connect \B { 1'0 \a [3] } - connect \Y $5 - end - connect $4 $5 - process $group_1 - assign \pop_2_1 2'00 - assign \pop_2_1 $4 [1:0] - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - wire width 2 \pop_2_2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - wire width 3 $7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - wire width 3 $8 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $9 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 3 - connect \A { 1'0 \a [4] } - connect \B { 1'0 \a [5] } - connect \Y $8 - end - connect $7 $8 - process $group_2 - assign \pop_2_2 2'00 - assign \pop_2_2 $7 [1:0] - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - wire width 2 \pop_2_3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - wire width 3 $10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - wire width 3 $11 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $12 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 3 - connect \A { 1'0 \a [6] } - connect \B { 1'0 \a [7] } - connect \Y $11 - end - connect $10 $11 - process $group_3 - assign \pop_2_3 2'00 - assign \pop_2_3 $10 [1:0] - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - wire width 2 \pop_2_4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - wire width 3 $13 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - wire width 3 $14 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $15 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 3 - connect \A { 1'0 \a [8] } - connect \B { 1'0 \a [9] } - connect \Y $14 - end - connect $13 $14 - process $group_4 - assign \pop_2_4 2'00 - assign \pop_2_4 $13 [1:0] - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - wire width 2 \pop_2_5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - wire width 3 $16 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - wire width 3 $17 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $18 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 3 - connect \A { 1'0 \a [10] } - connect \B { 1'0 \a [11] } - connect \Y $17 - end - connect $16 $17 - process $group_5 - assign \pop_2_5 2'00 - assign \pop_2_5 $16 [1:0] - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - wire width 2 \pop_2_6 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - wire width 3 $19 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - wire width 3 $20 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $21 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 3 - connect \A { 1'0 \a [12] } - connect \B { 1'0 \a [13] } - connect \Y $20 - end - connect $19 $20 - process $group_6 - assign \pop_2_6 2'00 - assign \pop_2_6 $19 [1:0] - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - wire width 2 \pop_2_7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - wire width 3 $22 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - wire width 3 $23 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $24 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 3 - connect \A { 1'0 \a [14] } - connect \B { 1'0 \a [15] } - connect \Y $23 - end - connect $22 $23 - process $group_7 - assign \pop_2_7 2'00 - assign \pop_2_7 $22 [1:0] - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - wire width 2 \pop_2_8 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - wire width 3 $25 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - wire width 3 $26 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $27 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 3 - connect \A { 1'0 \a [16] } - connect \B { 1'0 \a [17] } - connect \Y $26 - end - connect $25 $26 - process $group_8 - assign \pop_2_8 2'00 - assign \pop_2_8 $25 [1:0] - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - wire width 2 \pop_2_9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - wire width 3 $28 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - wire width 3 $29 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $30 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 3 - connect \A { 1'0 \a [18] } - connect \B { 1'0 \a [19] } - connect \Y $29 - end - connect $28 $29 - process $group_9 - assign \pop_2_9 2'00 - assign \pop_2_9 $28 [1:0] - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - wire width 2 \pop_2_10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - wire width 3 $31 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - wire width 3 $32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $33 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 3 - connect \A { 1'0 \a [20] } - connect \B { 1'0 \a [21] } - connect \Y $32 - end - connect $31 $32 - process $group_10 - assign \pop_2_10 2'00 - assign \pop_2_10 $31 [1:0] - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - wire width 2 \pop_2_11 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - wire width 3 $34 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - wire width 3 $35 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $36 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 3 - connect \A { 1'0 \a [22] } - connect \B { 1'0 \a [23] } - connect \Y $35 - end - connect $34 $35 - process $group_11 - assign \pop_2_11 2'00 - assign \pop_2_11 $34 [1:0] - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - wire width 2 \pop_2_12 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - wire width 3 $37 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - wire width 3 $38 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $39 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 3 - connect \A { 1'0 \a [24] } - connect \B { 1'0 \a [25] } - connect \Y $38 - end - connect $37 $38 - process $group_12 - assign \pop_2_12 2'00 - assign \pop_2_12 $37 [1:0] - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - wire width 2 \pop_2_13 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - wire width 3 $40 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - wire width 3 $41 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $42 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 3 - connect \A { 1'0 \a [26] } - connect \B { 1'0 \a [27] } - connect \Y $41 - end - connect $40 $41 - process $group_13 - assign \pop_2_13 2'00 - assign \pop_2_13 $40 [1:0] - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - wire width 2 \pop_2_14 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - wire width 3 $43 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - wire width 3 $44 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $45 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 3 - connect \A { 1'0 \a [28] } - connect \B { 1'0 \a [29] } - connect \Y $44 - end - connect $43 $44 - process $group_14 - assign \pop_2_14 2'00 - assign \pop_2_14 $43 [1:0] - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - wire width 2 \pop_2_15 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - wire width 3 $46 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - wire width 3 $47 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $48 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 3 - connect \A { 1'0 \a [30] } - connect \B { 1'0 \a [31] } - connect \Y $47 - end - connect $46 $47 - process $group_15 - assign \pop_2_15 2'00 - assign \pop_2_15 $46 [1:0] - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - wire width 2 \pop_2_16 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - wire width 3 $49 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - wire width 3 $50 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $51 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 3 - connect \A { 1'0 \a [32] } - connect \B { 1'0 \a [33] } - connect \Y $50 - end - connect $49 $50 - process $group_16 - assign \pop_2_16 2'00 - assign \pop_2_16 $49 [1:0] - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - wire width 2 \pop_2_17 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - wire width 3 $52 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - wire width 3 $53 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $54 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 3 - connect \A { 1'0 \a [34] } - connect \B { 1'0 \a [35] } - connect \Y $53 - end - connect $52 $53 - process $group_17 - assign \pop_2_17 2'00 - assign \pop_2_17 $52 [1:0] - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - wire width 2 \pop_2_18 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - wire width 3 $55 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - wire width 3 $56 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $57 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 3 - connect \A { 1'0 \a [36] } - connect \B { 1'0 \a [37] } - connect \Y $56 - end - connect $55 $56 - process $group_18 - assign \pop_2_18 2'00 - assign \pop_2_18 $55 [1:0] - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - wire width 2 \pop_2_19 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - wire width 3 $58 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - wire width 3 $59 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $60 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 3 - connect \A { 1'0 \a [38] } - connect \B { 1'0 \a [39] } - connect \Y $59 - end - connect $58 $59 - process $group_19 - assign \pop_2_19 2'00 - assign \pop_2_19 $58 [1:0] - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - wire width 2 \pop_2_20 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - wire width 3 $61 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - wire width 3 $62 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $63 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 3 - connect \A { 1'0 \a [40] } - connect \B { 1'0 \a [41] } - connect \Y $62 - end - connect $61 $62 - process $group_20 - assign \pop_2_20 2'00 - assign \pop_2_20 $61 [1:0] - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - wire width 2 \pop_2_21 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - wire width 3 $64 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - wire width 3 $65 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $66 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 3 - connect \A { 1'0 \a [42] } - connect \B { 1'0 \a [43] } - connect \Y $65 - end - connect $64 $65 - process $group_21 - assign \pop_2_21 2'00 - assign \pop_2_21 $64 [1:0] - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - wire width 2 \pop_2_22 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - wire width 3 $67 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - wire width 3 $68 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $69 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 3 - connect \A { 1'0 \a [44] } - connect \B { 1'0 \a [45] } - connect \Y $68 - end - connect $67 $68 - process $group_22 - assign \pop_2_22 2'00 - assign \pop_2_22 $67 [1:0] - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - wire width 2 \pop_2_23 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - wire width 3 $70 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - wire width 3 $71 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $72 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 3 - connect \A { 1'0 \a [46] } - connect \B { 1'0 \a [47] } - connect \Y $71 - end - connect $70 $71 - process $group_23 - assign \pop_2_23 2'00 - assign \pop_2_23 $70 [1:0] - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - wire width 2 \pop_2_24 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - wire width 3 $73 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - wire width 3 $74 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $75 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 3 - connect \A { 1'0 \a [48] } - connect \B { 1'0 \a [49] } - connect \Y $74 - end - connect $73 $74 - process $group_24 - assign \pop_2_24 2'00 - assign \pop_2_24 $73 [1:0] - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - wire width 2 \pop_2_25 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - wire width 3 $76 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - wire width 3 $77 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $78 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 3 - connect \A { 1'0 \a [50] } - connect \B { 1'0 \a [51] } - connect \Y $77 - end - connect $76 $77 - process $group_25 - assign \pop_2_25 2'00 - assign \pop_2_25 $76 [1:0] - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - wire width 2 \pop_2_26 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - wire width 3 $79 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - wire width 3 $80 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $81 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 3 - connect \A { 1'0 \a [52] } - connect \B { 1'0 \a [53] } - connect \Y $80 - end - connect $79 $80 - process $group_26 - assign \pop_2_26 2'00 - assign \pop_2_26 $79 [1:0] - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - wire width 2 \pop_2_27 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - wire width 3 $82 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - wire width 3 $83 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $84 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 3 - connect \A { 1'0 \a [54] } - connect \B { 1'0 \a [55] } - connect \Y $83 - end - connect $82 $83 - process $group_27 - assign \pop_2_27 2'00 - assign \pop_2_27 $82 [1:0] - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - wire width 2 \pop_2_28 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - wire width 3 $85 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - wire width 3 $86 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $87 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 3 - connect \A { 1'0 \a [56] } - connect \B { 1'0 \a [57] } - connect \Y $86 - end - connect $85 $86 - process $group_28 - assign \pop_2_28 2'00 - assign \pop_2_28 $85 [1:0] - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - wire width 2 \pop_2_29 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - wire width 3 $88 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - wire width 3 $89 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $90 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 3 - connect \A { 1'0 \a [58] } - connect \B { 1'0 \a [59] } - connect \Y $89 - end - connect $88 $89 - process $group_29 - assign \pop_2_29 2'00 - assign \pop_2_29 $88 [1:0] - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - wire width 2 \pop_2_30 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - wire width 3 $91 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - wire width 3 $92 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $93 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 3 - connect \A { 1'0 \a [60] } - connect \B { 1'0 \a [61] } - connect \Y $92 - end - connect $91 $92 - process $group_30 - assign \pop_2_30 2'00 - assign \pop_2_30 $91 [1:0] - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - wire width 2 \pop_2_31 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - wire width 3 $94 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - wire width 3 $95 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $96 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 3 - connect \A { 1'0 \a [62] } - connect \B { 1'0 \a [63] } - connect \Y $95 - end - connect $94 $95 - process $group_31 - assign \pop_2_31 2'00 - assign \pop_2_31 $94 [1:0] - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - wire width 3 \pop_3_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - wire width 4 $97 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - wire width 4 $98 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $99 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 4 - connect \A { 1'0 \pop_2_0 } - connect \B { 1'0 \pop_2_1 } - connect \Y $98 - end - connect $97 $98 - process $group_32 - assign \pop_3_0 3'000 - assign \pop_3_0 $97 [2:0] - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - wire width 3 \pop_3_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - wire width 4 $100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - wire width 4 $101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $102 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 4 - connect \A { 1'0 \pop_2_2 } - connect \B { 1'0 \pop_2_3 } - connect \Y $101 - end - connect $100 $101 - process $group_33 - assign \pop_3_1 3'000 - assign \pop_3_1 $100 [2:0] - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - wire width 3 \pop_3_2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - wire width 4 $103 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - wire width 4 $104 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $105 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 4 - connect \A { 1'0 \pop_2_4 } - connect \B { 1'0 \pop_2_5 } - connect \Y $104 - end - connect $103 $104 - process $group_34 - assign \pop_3_2 3'000 - assign \pop_3_2 $103 [2:0] - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - wire width 3 \pop_3_3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - wire width 4 $106 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - wire width 4 $107 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $108 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 4 - connect \A { 1'0 \pop_2_6 } - connect \B { 1'0 \pop_2_7 } - connect \Y $107 - end - connect $106 $107 - process $group_35 - assign \pop_3_3 3'000 - assign \pop_3_3 $106 [2:0] - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - wire width 3 \pop_3_4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - wire width 4 $109 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - wire width 4 $110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $111 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 4 - connect \A { 1'0 \pop_2_8 } - connect \B { 1'0 \pop_2_9 } - connect \Y $110 - end - connect $109 $110 - process $group_36 - assign \pop_3_4 3'000 - assign \pop_3_4 $109 [2:0] - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - wire width 3 \pop_3_5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - wire width 4 $112 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - wire width 4 $113 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $114 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 4 - connect \A { 1'0 \pop_2_10 } - connect \B { 1'0 \pop_2_11 } - connect \Y $113 - end - connect $112 $113 - process $group_37 - assign \pop_3_5 3'000 - assign \pop_3_5 $112 [2:0] - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - wire width 3 \pop_3_6 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - wire width 4 $115 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - wire width 4 $116 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $117 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 4 - connect \A { 1'0 \pop_2_12 } - connect \B { 1'0 \pop_2_13 } - connect \Y $116 - end - connect $115 $116 - process $group_38 - assign \pop_3_6 3'000 - assign \pop_3_6 $115 [2:0] - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - wire width 3 \pop_3_7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - wire width 4 $118 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - wire width 4 $119 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $120 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 4 - connect \A { 1'0 \pop_2_14 } - connect \B { 1'0 \pop_2_15 } - connect \Y $119 - end - connect $118 $119 - process $group_39 - assign \pop_3_7 3'000 - assign \pop_3_7 $118 [2:0] - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - wire width 3 \pop_3_8 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - wire width 4 $121 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - wire width 4 $122 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $123 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 4 - connect \A { 1'0 \pop_2_16 } - connect \B { 1'0 \pop_2_17 } - connect \Y $122 - end - connect $121 $122 - process $group_40 - assign \pop_3_8 3'000 - assign \pop_3_8 $121 [2:0] - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - wire width 3 \pop_3_9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - wire width 4 $124 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - wire width 4 $125 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $126 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 4 - connect \A { 1'0 \pop_2_18 } - connect \B { 1'0 \pop_2_19 } - connect \Y $125 - end - connect $124 $125 - process $group_41 - assign \pop_3_9 3'000 - assign \pop_3_9 $124 [2:0] - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - wire width 3 \pop_3_10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - wire width 4 $127 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - wire width 4 $128 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $129 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 4 - connect \A { 1'0 \pop_2_20 } - connect \B { 1'0 \pop_2_21 } - connect \Y $128 - end - connect $127 $128 - process $group_42 - assign \pop_3_10 3'000 - assign \pop_3_10 $127 [2:0] - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - wire width 3 \pop_3_11 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - wire width 4 $130 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - wire width 4 $131 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $132 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 4 - connect \A { 1'0 \pop_2_22 } - connect \B { 1'0 \pop_2_23 } - connect \Y $131 - end - connect $130 $131 - process $group_43 - assign \pop_3_11 3'000 - assign \pop_3_11 $130 [2:0] - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - wire width 3 \pop_3_12 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - wire width 4 $133 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - wire width 4 $134 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $135 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 4 - connect \A { 1'0 \pop_2_24 } - connect \B { 1'0 \pop_2_25 } - connect \Y $134 - end - connect $133 $134 - process $group_44 - assign \pop_3_12 3'000 - assign \pop_3_12 $133 [2:0] - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - wire width 3 \pop_3_13 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - wire width 4 $136 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - wire width 4 $137 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $138 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 4 - connect \A { 1'0 \pop_2_26 } - connect \B { 1'0 \pop_2_27 } - connect \Y $137 - end - connect $136 $137 - process $group_45 - assign \pop_3_13 3'000 - assign \pop_3_13 $136 [2:0] - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - wire width 3 \pop_3_14 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - wire width 4 $139 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - wire width 4 $140 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $141 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 4 - connect \A { 1'0 \pop_2_28 } - connect \B { 1'0 \pop_2_29 } - connect \Y $140 - end - connect $139 $140 - process $group_46 - assign \pop_3_14 3'000 - assign \pop_3_14 $139 [2:0] - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - wire width 3 \pop_3_15 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - wire width 4 $142 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - wire width 4 $143 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $144 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 4 - connect \A { 1'0 \pop_2_30 } - connect \B { 1'0 \pop_2_31 } - connect \Y $143 - end - connect $142 $143 - process $group_47 - assign \pop_3_15 3'000 - assign \pop_3_15 $142 [2:0] - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - wire width 4 \pop_4_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - wire width 5 $145 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - wire width 5 $146 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $147 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 5 - connect \A { 1'0 \pop_3_0 } - connect \B { 1'0 \pop_3_1 } - connect \Y $146 - end - connect $145 $146 - process $group_48 - assign \pop_4_0 4'0000 - assign \pop_4_0 $145 [3:0] - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - wire width 4 \pop_4_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - wire width 5 $148 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - wire width 5 $149 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $150 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 5 - connect \A { 1'0 \pop_3_2 } - connect \B { 1'0 \pop_3_3 } - connect \Y $149 - end - connect $148 $149 - process $group_49 - assign \pop_4_1 4'0000 - assign \pop_4_1 $148 [3:0] - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - wire width 4 \pop_4_2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - wire width 5 $151 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - wire width 5 $152 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $153 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 5 - connect \A { 1'0 \pop_3_4 } - connect \B { 1'0 \pop_3_5 } - connect \Y $152 - end - connect $151 $152 - process $group_50 - assign \pop_4_2 4'0000 - assign \pop_4_2 $151 [3:0] - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - wire width 4 \pop_4_3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - wire width 5 $154 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - wire width 5 $155 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $156 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 5 - connect \A { 1'0 \pop_3_6 } - connect \B { 1'0 \pop_3_7 } - connect \Y $155 - end - connect $154 $155 - process $group_51 - assign \pop_4_3 4'0000 - assign \pop_4_3 $154 [3:0] - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - wire width 4 \pop_4_4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - wire width 5 $157 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - wire width 5 $158 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $159 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 5 - connect \A { 1'0 \pop_3_8 } - connect \B { 1'0 \pop_3_9 } - connect \Y $158 - end - connect $157 $158 - process $group_52 - assign \pop_4_4 4'0000 - assign \pop_4_4 $157 [3:0] - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - wire width 4 \pop_4_5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - wire width 5 $160 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - wire width 5 $161 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $162 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 5 - connect \A { 1'0 \pop_3_10 } - connect \B { 1'0 \pop_3_11 } - connect \Y $161 - end - connect $160 $161 - process $group_53 - assign \pop_4_5 4'0000 - assign \pop_4_5 $160 [3:0] - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - wire width 4 \pop_4_6 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - wire width 5 $163 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - wire width 5 $164 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $165 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 5 - connect \A { 1'0 \pop_3_12 } - connect \B { 1'0 \pop_3_13 } - connect \Y $164 - end - connect $163 $164 - process $group_54 - assign \pop_4_6 4'0000 - assign \pop_4_6 $163 [3:0] - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - wire width 4 \pop_4_7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - wire width 5 $166 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - wire width 5 $167 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $168 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 5 - connect \A { 1'0 \pop_3_14 } - connect \B { 1'0 \pop_3_15 } - connect \Y $167 - end - connect $166 $167 - process $group_55 - assign \pop_4_7 4'0000 - assign \pop_4_7 $166 [3:0] - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - wire width 5 \pop_5_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - wire width 6 $169 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - wire width 6 $170 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $171 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 6 - connect \A { 1'0 \pop_4_0 } - connect \B { 1'0 \pop_4_1 } - connect \Y $170 - end - connect $169 $170 - process $group_56 - assign \pop_5_0 5'00000 - assign \pop_5_0 $169 [4:0] - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - wire width 5 \pop_5_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - wire width 6 $172 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - wire width 6 $173 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $174 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 6 - connect \A { 1'0 \pop_4_2 } - connect \B { 1'0 \pop_4_3 } - connect \Y $173 - end - connect $172 $173 - process $group_57 - assign \pop_5_1 5'00000 - assign \pop_5_1 $172 [4:0] - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - wire width 5 \pop_5_2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - wire width 6 $175 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - wire width 6 $176 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $177 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 6 - connect \A { 1'0 \pop_4_4 } - connect \B { 1'0 \pop_4_5 } - connect \Y $176 - end - connect $175 $176 - process $group_58 - assign \pop_5_2 5'00000 - assign \pop_5_2 $175 [4:0] - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - wire width 5 \pop_5_3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - wire width 6 $178 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - wire width 6 $179 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $180 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 6 - connect \A { 1'0 \pop_4_6 } - connect \B { 1'0 \pop_4_7 } - connect \Y $179 - end - connect $178 $179 - process $group_59 - assign \pop_5_3 5'00000 - assign \pop_5_3 $178 [4:0] - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - wire width 6 \pop_6_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - wire width 7 $181 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - wire width 7 $182 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $183 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 7 - connect \A { 1'0 \pop_5_0 } - connect \B { 1'0 \pop_5_1 } - connect \Y $182 - end - connect $181 $182 - process $group_60 - assign \pop_6_0 6'000000 - assign \pop_6_0 $181 [5:0] - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - wire width 6 \pop_6_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - wire width 7 $184 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - wire width 7 $185 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $186 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 7 - connect \A { 1'0 \pop_5_2 } - connect \B { 1'0 \pop_5_3 } - connect \Y $185 - end - connect $184 $185 - process $group_61 - assign \pop_6_1 6'000000 - assign \pop_6_1 $184 [5:0] - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - wire width 7 \pop_7_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - wire width 8 $187 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - wire width 8 $188 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:53" - cell $add $189 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 8 - connect \A { 1'0 \pop_6_0 } - connect \B { 1'0 \pop_6_1 } - connect \Y $188 - end - connect $187 $188 - process $group_62 - assign \pop_7_0 7'0000000 - assign \pop_7_0 $187 [6:0] - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:55" - wire width 1 $190 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:55" - cell $eq $191 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \data_len - connect \B 1'1 - connect \Y $190 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:59" - wire width 1 $192 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:59" - cell $eq $193 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \data_len - connect \B 3'100 - connect \Y $192 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - wire width 8 $194 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - cell $pos $195 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \Y_WIDTH 8 - connect \A \pop_4_0 - connect \Y $194 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - wire width 8 $196 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - cell $pos $197 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \Y_WIDTH 8 - connect \A \pop_4_1 - connect \Y $196 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - wire width 8 $198 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - cell $pos $199 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \Y_WIDTH 8 - connect \A \pop_4_2 - connect \Y $198 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - wire width 8 $200 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - cell $pos $201 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \Y_WIDTH 8 - connect \A \pop_4_3 - connect \Y $200 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - wire width 8 $202 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - cell $pos $203 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \Y_WIDTH 8 - connect \A \pop_4_4 - connect \Y $202 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - wire width 8 $204 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - cell $pos $205 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \Y_WIDTH 8 - connect \A \pop_4_5 - connect \Y $204 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - wire width 8 $206 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - cell $pos $207 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \Y_WIDTH 8 - connect \A \pop_4_6 - connect \Y $206 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - wire width 8 $208 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - cell $pos $209 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \Y_WIDTH 8 - connect \A \pop_4_7 - connect \Y $208 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - wire width 32 $210 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - cell $pos $211 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \Y_WIDTH 32 - connect \A \pop_6_0 - connect \Y $210 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - wire width 32 $212 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - cell $pos $213 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \Y_WIDTH 32 - connect \A \pop_6_1 - connect \Y $212 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - wire width 64 $214 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:21" - cell $pos $215 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \Y_WIDTH 64 - connect \A \pop_7_0 - connect \Y $214 - end - process $group_63 - assign \o 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:55" - switch { $192 $190 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:55" - case 2'-1 - assign \o [7:0] $194 - assign \o [15:8] $196 - assign \o [23:16] $198 - assign \o [31:24] $200 - assign \o [39:32] $202 - assign \o [47:40] $204 - assign \o [55:48] $206 - assign \o [63:56] $208 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:59" - case 2'1- - assign \o [31:0] $210 - assign \o [63:32] $212 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:63" - case - assign \o $214 - end - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.logical0.alu_logical0.logical_pipe1.main.clz" -module \clz - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:11" - wire width 64 input 0 \sig_in - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:13" - wire width 7 output 1 \lz - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:24" - wire width 2 \pair0 - process $group_0 - assign \pair0 2'00 - assign \pair0 \sig_in [1:0] - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:27" - wire width 2 \cnt_1_0 - process $group_1 - assign \cnt_1_0 2'00 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:28" - switch \pair0 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:29" - case 2'00 - assign \cnt_1_0 2'10 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:31" - case 2'01 - assign \cnt_1_0 2'01 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:33" - case - assign \cnt_1_0 2'00 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:24" - wire width 2 \pair2 - process $group_2 - assign \pair2 2'00 - assign \pair2 \sig_in [3:2] - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:27" - wire width 2 \cnt_1_1 - process $group_3 - assign \cnt_1_1 2'00 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:28" - switch \pair2 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:29" - case 2'00 - assign \cnt_1_1 2'10 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:31" - case 2'01 - assign \cnt_1_1 2'01 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:33" - case - assign \cnt_1_1 2'00 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:24" - wire width 2 \pair4 - process $group_4 - assign \pair4 2'00 - assign \pair4 \sig_in [5:4] - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:27" - wire width 2 \cnt_1_2 - process $group_5 - assign \cnt_1_2 2'00 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:28" - switch \pair4 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:29" - case 2'00 - assign \cnt_1_2 2'10 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:31" - case 2'01 - assign \cnt_1_2 2'01 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:33" - case - assign \cnt_1_2 2'00 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:24" - wire width 2 \pair6 - process $group_6 - assign \pair6 2'00 - assign \pair6 \sig_in [7:6] - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:27" - wire width 2 \cnt_1_3 - process $group_7 - assign \cnt_1_3 2'00 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:28" - switch \pair6 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:29" - case 2'00 - assign \cnt_1_3 2'10 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:31" - case 2'01 - assign \cnt_1_3 2'01 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:33" - case - assign \cnt_1_3 2'00 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:24" - wire width 2 \pair8 - process $group_8 - assign \pair8 2'00 - assign \pair8 \sig_in [9:8] - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:27" - wire width 2 \cnt_1_4 - process $group_9 - assign \cnt_1_4 2'00 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:28" - switch \pair8 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:29" - case 2'00 - assign \cnt_1_4 2'10 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:31" - case 2'01 - assign \cnt_1_4 2'01 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:33" - case - assign \cnt_1_4 2'00 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:24" - wire width 2 \pair10 - process $group_10 - assign \pair10 2'00 - assign \pair10 \sig_in [11:10] - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:27" - wire width 2 \cnt_1_5 - process $group_11 - assign \cnt_1_5 2'00 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:28" - switch \pair10 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:29" - case 2'00 - assign \cnt_1_5 2'10 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:31" - case 2'01 - assign \cnt_1_5 2'01 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:33" - case - assign \cnt_1_5 2'00 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:24" - wire width 2 \pair12 - process $group_12 - assign \pair12 2'00 - assign \pair12 \sig_in [13:12] - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:27" - wire width 2 \cnt_1_6 - process $group_13 - assign \cnt_1_6 2'00 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:28" - switch \pair12 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:29" - case 2'00 - assign \cnt_1_6 2'10 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:31" - case 2'01 - assign \cnt_1_6 2'01 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:33" - case - assign \cnt_1_6 2'00 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:24" - wire width 2 \pair14 - process $group_14 - assign \pair14 2'00 - assign \pair14 \sig_in [15:14] - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:27" - wire width 2 \cnt_1_7 - process $group_15 - assign \cnt_1_7 2'00 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:28" - switch \pair14 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:29" - case 2'00 - assign \cnt_1_7 2'10 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:31" - case 2'01 - assign \cnt_1_7 2'01 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:33" - case - assign \cnt_1_7 2'00 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:24" - wire width 2 \pair16 - process $group_16 - assign \pair16 2'00 - assign \pair16 \sig_in [17:16] - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:27" - wire width 2 \cnt_1_8 - process $group_17 - assign \cnt_1_8 2'00 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:28" - switch \pair16 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:29" - case 2'00 - assign \cnt_1_8 2'10 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:31" - case 2'01 - assign \cnt_1_8 2'01 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:33" - case - assign \cnt_1_8 2'00 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:24" - wire width 2 \pair18 - process $group_18 - assign \pair18 2'00 - assign \pair18 \sig_in [19:18] - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:27" - wire width 2 \cnt_1_9 - process $group_19 - assign \cnt_1_9 2'00 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:28" - switch \pair18 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:29" - case 2'00 - assign \cnt_1_9 2'10 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:31" - case 2'01 - assign \cnt_1_9 2'01 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:33" - case - assign \cnt_1_9 2'00 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:24" - wire width 2 \pair20 - process $group_20 - assign \pair20 2'00 - assign \pair20 \sig_in [21:20] - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:27" - wire width 2 \cnt_1_10 - process $group_21 - assign \cnt_1_10 2'00 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:28" - switch \pair20 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:29" - case 2'00 - assign \cnt_1_10 2'10 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:31" - case 2'01 - assign \cnt_1_10 2'01 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:33" - case - assign \cnt_1_10 2'00 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:24" - wire width 2 \pair22 - process $group_22 - assign \pair22 2'00 - assign \pair22 \sig_in [23:22] - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:27" - wire width 2 \cnt_1_11 - process $group_23 - assign \cnt_1_11 2'00 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:28" - switch \pair22 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:29" - case 2'00 - assign \cnt_1_11 2'10 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:31" - case 2'01 - assign \cnt_1_11 2'01 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:33" - case - assign \cnt_1_11 2'00 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:24" - wire width 2 \pair24 - process $group_24 - assign \pair24 2'00 - assign \pair24 \sig_in [25:24] - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:27" - wire width 2 \cnt_1_12 - process $group_25 - assign \cnt_1_12 2'00 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:28" - switch \pair24 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:29" - case 2'00 - assign \cnt_1_12 2'10 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:31" - case 2'01 - assign \cnt_1_12 2'01 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:33" - case - assign \cnt_1_12 2'00 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:24" - wire width 2 \pair26 - process $group_26 - assign \pair26 2'00 - assign \pair26 \sig_in [27:26] - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:27" - wire width 2 \cnt_1_13 - process $group_27 - assign \cnt_1_13 2'00 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:28" - switch \pair26 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:29" - case 2'00 - assign \cnt_1_13 2'10 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:31" - case 2'01 - assign \cnt_1_13 2'01 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:33" - case - assign \cnt_1_13 2'00 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:24" - wire width 2 \pair28 - process $group_28 - assign \pair28 2'00 - assign \pair28 \sig_in [29:28] - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:27" - wire width 2 \cnt_1_14 - process $group_29 - assign \cnt_1_14 2'00 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:28" - switch \pair28 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:29" - case 2'00 - assign \cnt_1_14 2'10 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:31" - case 2'01 - assign \cnt_1_14 2'01 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:33" - case - assign \cnt_1_14 2'00 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:24" - wire width 2 \pair30 - process $group_30 - assign \pair30 2'00 - assign \pair30 \sig_in [31:30] - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:27" - wire width 2 \cnt_1_15 - process $group_31 - assign \cnt_1_15 2'00 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:28" - switch \pair30 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:29" - case 2'00 - assign \cnt_1_15 2'10 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:31" - case 2'01 - assign \cnt_1_15 2'01 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:33" - case - assign \cnt_1_15 2'00 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:24" - wire width 2 \pair32 - process $group_32 - assign \pair32 2'00 - assign \pair32 \sig_in [33:32] - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:27" - wire width 2 \cnt_1_16 - process $group_33 - assign \cnt_1_16 2'00 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:28" - switch \pair32 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:29" - case 2'00 - assign \cnt_1_16 2'10 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:31" - case 2'01 - assign \cnt_1_16 2'01 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:33" - case - assign \cnt_1_16 2'00 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:24" - wire width 2 \pair34 - process $group_34 - assign \pair34 2'00 - assign \pair34 \sig_in [35:34] - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:27" - wire width 2 \cnt_1_17 - process $group_35 - assign \cnt_1_17 2'00 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:28" - switch \pair34 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:29" - case 2'00 - assign \cnt_1_17 2'10 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:31" - case 2'01 - assign \cnt_1_17 2'01 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:33" - case - assign \cnt_1_17 2'00 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:24" - wire width 2 \pair36 - process $group_36 - assign \pair36 2'00 - assign \pair36 \sig_in [37:36] - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:27" - wire width 2 \cnt_1_18 - process $group_37 - assign \cnt_1_18 2'00 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:28" - switch \pair36 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:29" - case 2'00 - assign \cnt_1_18 2'10 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:31" - case 2'01 - assign \cnt_1_18 2'01 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:33" - case - assign \cnt_1_18 2'00 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:24" - wire width 2 \pair38 - process $group_38 - assign \pair38 2'00 - assign \pair38 \sig_in [39:38] - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:27" - wire width 2 \cnt_1_19 - process $group_39 - assign \cnt_1_19 2'00 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:28" - switch \pair38 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:29" - case 2'00 - assign \cnt_1_19 2'10 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:31" - case 2'01 - assign \cnt_1_19 2'01 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:33" - case - assign \cnt_1_19 2'00 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:24" - wire width 2 \pair40 - process $group_40 - assign \pair40 2'00 - assign \pair40 \sig_in [41:40] - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:27" - wire width 2 \cnt_1_20 - process $group_41 - assign \cnt_1_20 2'00 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:28" - switch \pair40 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:29" - case 2'00 - assign \cnt_1_20 2'10 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:31" - case 2'01 - assign \cnt_1_20 2'01 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:33" - case - assign \cnt_1_20 2'00 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:24" - wire width 2 \pair42 - process $group_42 - assign \pair42 2'00 - assign \pair42 \sig_in [43:42] - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:27" - wire width 2 \cnt_1_21 - process $group_43 - assign \cnt_1_21 2'00 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:28" - switch \pair42 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:29" - case 2'00 - assign \cnt_1_21 2'10 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:31" - case 2'01 - assign \cnt_1_21 2'01 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:33" - case - assign \cnt_1_21 2'00 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:24" - wire width 2 \pair44 - process $group_44 - assign \pair44 2'00 - assign \pair44 \sig_in [45:44] - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:27" - wire width 2 \cnt_1_22 - process $group_45 - assign \cnt_1_22 2'00 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:28" - switch \pair44 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:29" - case 2'00 - assign \cnt_1_22 2'10 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:31" - case 2'01 - assign \cnt_1_22 2'01 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:33" - case - assign \cnt_1_22 2'00 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:24" - wire width 2 \pair46 - process $group_46 - assign \pair46 2'00 - assign \pair46 \sig_in [47:46] - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:27" - wire width 2 \cnt_1_23 - process $group_47 - assign \cnt_1_23 2'00 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:28" - switch \pair46 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:29" - case 2'00 - assign \cnt_1_23 2'10 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:31" - case 2'01 - assign \cnt_1_23 2'01 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:33" - case - assign \cnt_1_23 2'00 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:24" - wire width 2 \pair48 - process $group_48 - assign \pair48 2'00 - assign \pair48 \sig_in [49:48] - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:27" - wire width 2 \cnt_1_24 - process $group_49 - assign \cnt_1_24 2'00 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:28" - switch \pair48 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:29" - case 2'00 - assign \cnt_1_24 2'10 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:31" - case 2'01 - assign \cnt_1_24 2'01 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:33" - case - assign \cnt_1_24 2'00 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:24" - wire width 2 \pair50 - process $group_50 - assign \pair50 2'00 - assign \pair50 \sig_in [51:50] - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:27" - wire width 2 \cnt_1_25 - process $group_51 - assign \cnt_1_25 2'00 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:28" - switch \pair50 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:29" - case 2'00 - assign \cnt_1_25 2'10 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:31" - case 2'01 - assign \cnt_1_25 2'01 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:33" - case - assign \cnt_1_25 2'00 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:24" - wire width 2 \pair52 - process $group_52 - assign \pair52 2'00 - assign \pair52 \sig_in [53:52] - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:27" - wire width 2 \cnt_1_26 - process $group_53 - assign \cnt_1_26 2'00 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:28" - switch \pair52 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:29" - case 2'00 - assign \cnt_1_26 2'10 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:31" - case 2'01 - assign \cnt_1_26 2'01 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:33" - case - assign \cnt_1_26 2'00 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:24" - wire width 2 \pair54 - process $group_54 - assign \pair54 2'00 - assign \pair54 \sig_in [55:54] - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:27" - wire width 2 \cnt_1_27 - process $group_55 - assign \cnt_1_27 2'00 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:28" - switch \pair54 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:29" - case 2'00 - assign \cnt_1_27 2'10 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:31" - case 2'01 - assign \cnt_1_27 2'01 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:33" - case - assign \cnt_1_27 2'00 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:24" - wire width 2 \pair56 - process $group_56 - assign \pair56 2'00 - assign \pair56 \sig_in [57:56] - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:27" - wire width 2 \cnt_1_28 - process $group_57 - assign \cnt_1_28 2'00 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:28" - switch \pair56 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:29" - case 2'00 - assign \cnt_1_28 2'10 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:31" - case 2'01 - assign \cnt_1_28 2'01 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:33" - case - assign \cnt_1_28 2'00 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:24" - wire width 2 \pair58 - process $group_58 - assign \pair58 2'00 - assign \pair58 \sig_in [59:58] - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:27" - wire width 2 \cnt_1_29 - process $group_59 - assign \cnt_1_29 2'00 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:28" - switch \pair58 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:29" - case 2'00 - assign \cnt_1_29 2'10 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:31" - case 2'01 - assign \cnt_1_29 2'01 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:33" - case - assign \cnt_1_29 2'00 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:24" - wire width 2 \pair60 - process $group_60 - assign \pair60 2'00 - assign \pair60 \sig_in [61:60] - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:27" - wire width 2 \cnt_1_30 - process $group_61 - assign \cnt_1_30 2'00 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:28" - switch \pair60 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:29" - case 2'00 - assign \cnt_1_30 2'10 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:31" - case 2'01 - assign \cnt_1_30 2'01 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:33" - case - assign \cnt_1_30 2'00 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:24" - wire width 2 \pair62 - process $group_62 - assign \pair62 2'00 - assign \pair62 \sig_in [63:62] - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:27" - wire width 2 \cnt_1_31 - process $group_63 - assign \cnt_1_31 2'00 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:28" - switch \pair62 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:29" - case 2'00 - assign \cnt_1_31 2'10 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:31" - case 2'01 - assign \cnt_1_31 2'01 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:33" - case - assign \cnt_1_31 2'00 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:53" - wire width 3 \cnt_2_0 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - cell $eq $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cnt_1_1 [1] - connect \B 1'1 - connect \Y $1 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - wire width 1 $3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - cell $eq $4 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cnt_1_0 [1] - connect \B 1'1 - connect \Y $3 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" - wire width 3 $5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" - cell $pos $6 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \Y_WIDTH 3 - connect \A { 1'1 \cnt_1_0 [0] } - connect \Y $5 - end - process $group_64 - assign \cnt_2_0 3'000 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - switch { $1 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - switch { $3 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - case 1'1 - assign \cnt_2_0 { 1'1 { 1'0 1'0 } } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:58" - case - assign \cnt_2_0 $5 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" - case - assign \cnt_2_0 { 1'0 \cnt_1_1 } - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:53" - wire width 3 \cnt_2_2 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - wire width 1 $7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - cell $eq $8 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cnt_1_3 [1] - connect \B 1'1 - connect \Y $7 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - wire width 1 $9 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - cell $eq $10 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cnt_1_2 [1] - connect \B 1'1 - connect \Y $9 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" - wire width 3 $11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" - cell $pos $12 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \Y_WIDTH 3 - connect \A { 1'1 \cnt_1_2 [0] } - connect \Y $11 - end - process $group_65 - assign \cnt_2_2 3'000 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - switch { $7 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - switch { $9 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - case 1'1 - assign \cnt_2_2 { 1'1 { 1'0 1'0 } } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:58" - case - assign \cnt_2_2 $11 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" - case - assign \cnt_2_2 { 1'0 \cnt_1_3 } - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:53" - wire width 3 \cnt_2_4 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - wire width 1 $13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - cell $eq $14 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cnt_1_5 [1] - connect \B 1'1 - connect \Y $13 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - wire width 1 $15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - cell $eq $16 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cnt_1_4 [1] - connect \B 1'1 - connect \Y $15 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" - wire width 3 $17 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" - cell $pos $18 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \Y_WIDTH 3 - connect \A { 1'1 \cnt_1_4 [0] } - connect \Y $17 - end - process $group_66 - assign \cnt_2_4 3'000 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - switch { $13 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - switch { $15 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - case 1'1 - assign \cnt_2_4 { 1'1 { 1'0 1'0 } } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:58" - case - assign \cnt_2_4 $17 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" - case - assign \cnt_2_4 { 1'0 \cnt_1_5 } - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:53" - wire width 3 \cnt_2_6 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - wire width 1 $19 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - cell $eq $20 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cnt_1_7 [1] - connect \B 1'1 - connect \Y $19 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - wire width 1 $21 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - cell $eq $22 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cnt_1_6 [1] - connect \B 1'1 - connect \Y $21 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" - wire width 3 $23 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" - cell $pos $24 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \Y_WIDTH 3 - connect \A { 1'1 \cnt_1_6 [0] } - connect \Y $23 - end - process $group_67 - assign \cnt_2_6 3'000 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - switch { $19 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - switch { $21 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - case 1'1 - assign \cnt_2_6 { 1'1 { 1'0 1'0 } } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:58" - case - assign \cnt_2_6 $23 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" - case - assign \cnt_2_6 { 1'0 \cnt_1_7 } - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:53" - wire width 3 \cnt_2_8 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - wire width 1 $25 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - cell $eq $26 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cnt_1_9 [1] - connect \B 1'1 - connect \Y $25 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - wire width 1 $27 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - cell $eq $28 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cnt_1_8 [1] - connect \B 1'1 - connect \Y $27 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" - wire width 3 $29 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" - cell $pos $30 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \Y_WIDTH 3 - connect \A { 1'1 \cnt_1_8 [0] } - connect \Y $29 - end - process $group_68 - assign \cnt_2_8 3'000 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - switch { $25 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - switch { $27 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - case 1'1 - assign \cnt_2_8 { 1'1 { 1'0 1'0 } } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:58" - case - assign \cnt_2_8 $29 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" - case - assign \cnt_2_8 { 1'0 \cnt_1_9 } - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:53" - wire width 3 \cnt_2_10 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - wire width 1 $31 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - cell $eq $32 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cnt_1_11 [1] - connect \B 1'1 - connect \Y $31 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - wire width 1 $33 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - cell $eq $34 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cnt_1_10 [1] - connect \B 1'1 - connect \Y $33 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" - wire width 3 $35 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" - cell $pos $36 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \Y_WIDTH 3 - connect \A { 1'1 \cnt_1_10 [0] } - connect \Y $35 - end - process $group_69 - assign \cnt_2_10 3'000 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - switch { $31 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - switch { $33 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - case 1'1 - assign \cnt_2_10 { 1'1 { 1'0 1'0 } } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:58" - case - assign \cnt_2_10 $35 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" - case - assign \cnt_2_10 { 1'0 \cnt_1_11 } - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:53" - wire width 3 \cnt_2_12 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - wire width 1 $37 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - cell $eq $38 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cnt_1_13 [1] - connect \B 1'1 - connect \Y $37 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - wire width 1 $39 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - cell $eq $40 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cnt_1_12 [1] - connect \B 1'1 - connect \Y $39 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" - wire width 3 $41 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" - cell $pos $42 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \Y_WIDTH 3 - connect \A { 1'1 \cnt_1_12 [0] } - connect \Y $41 - end - process $group_70 - assign \cnt_2_12 3'000 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - switch { $37 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - switch { $39 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - case 1'1 - assign \cnt_2_12 { 1'1 { 1'0 1'0 } } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:58" - case - assign \cnt_2_12 $41 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" - case - assign \cnt_2_12 { 1'0 \cnt_1_13 } - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:53" - wire width 3 \cnt_2_14 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - wire width 1 $43 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - cell $eq $44 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cnt_1_15 [1] - connect \B 1'1 - connect \Y $43 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - wire width 1 $45 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - cell $eq $46 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cnt_1_14 [1] - connect \B 1'1 - connect \Y $45 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" - wire width 3 $47 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" - cell $pos $48 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \Y_WIDTH 3 - connect \A { 1'1 \cnt_1_14 [0] } - connect \Y $47 - end - process $group_71 - assign \cnt_2_14 3'000 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - switch { $43 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - switch { $45 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - case 1'1 - assign \cnt_2_14 { 1'1 { 1'0 1'0 } } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:58" - case - assign \cnt_2_14 $47 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" - case - assign \cnt_2_14 { 1'0 \cnt_1_15 } - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:53" - wire width 3 \cnt_2_16 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - wire width 1 $49 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - cell $eq $50 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cnt_1_17 [1] - connect \B 1'1 - connect \Y $49 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - wire width 1 $51 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - cell $eq $52 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cnt_1_16 [1] - connect \B 1'1 - connect \Y $51 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" - wire width 3 $53 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" - cell $pos $54 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \Y_WIDTH 3 - connect \A { 1'1 \cnt_1_16 [0] } - connect \Y $53 - end - process $group_72 - assign \cnt_2_16 3'000 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - switch { $49 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - switch { $51 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - case 1'1 - assign \cnt_2_16 { 1'1 { 1'0 1'0 } } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:58" - case - assign \cnt_2_16 $53 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" - case - assign \cnt_2_16 { 1'0 \cnt_1_17 } - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:53" - wire width 3 \cnt_2_18 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - wire width 1 $55 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - cell $eq $56 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cnt_1_19 [1] - connect \B 1'1 - connect \Y $55 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - wire width 1 $57 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - cell $eq $58 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cnt_1_18 [1] - connect \B 1'1 - connect \Y $57 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" - wire width 3 $59 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" - cell $pos $60 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \Y_WIDTH 3 - connect \A { 1'1 \cnt_1_18 [0] } - connect \Y $59 - end - process $group_73 - assign \cnt_2_18 3'000 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - switch { $55 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - switch { $57 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - case 1'1 - assign \cnt_2_18 { 1'1 { 1'0 1'0 } } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:58" - case - assign \cnt_2_18 $59 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" - case - assign \cnt_2_18 { 1'0 \cnt_1_19 } - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:53" - wire width 3 \cnt_2_20 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - wire width 1 $61 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - cell $eq $62 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cnt_1_21 [1] - connect \B 1'1 - connect \Y $61 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - wire width 1 $63 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - cell $eq $64 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cnt_1_20 [1] - connect \B 1'1 - connect \Y $63 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" - wire width 3 $65 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" - cell $pos $66 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \Y_WIDTH 3 - connect \A { 1'1 \cnt_1_20 [0] } - connect \Y $65 - end - process $group_74 - assign \cnt_2_20 3'000 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - switch { $61 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - switch { $63 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - case 1'1 - assign \cnt_2_20 { 1'1 { 1'0 1'0 } } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:58" - case - assign \cnt_2_20 $65 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" - case - assign \cnt_2_20 { 1'0 \cnt_1_21 } - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:53" - wire width 3 \cnt_2_22 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - wire width 1 $67 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - cell $eq $68 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cnt_1_23 [1] - connect \B 1'1 - connect \Y $67 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - wire width 1 $69 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - cell $eq $70 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cnt_1_22 [1] - connect \B 1'1 - connect \Y $69 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" - wire width 3 $71 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" - cell $pos $72 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \Y_WIDTH 3 - connect \A { 1'1 \cnt_1_22 [0] } - connect \Y $71 - end - process $group_75 - assign \cnt_2_22 3'000 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - switch { $67 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - switch { $69 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - case 1'1 - assign \cnt_2_22 { 1'1 { 1'0 1'0 } } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:58" - case - assign \cnt_2_22 $71 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" - case - assign \cnt_2_22 { 1'0 \cnt_1_23 } - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:53" - wire width 3 \cnt_2_24 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - wire width 1 $73 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - cell $eq $74 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cnt_1_25 [1] - connect \B 1'1 - connect \Y $73 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - wire width 1 $75 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - cell $eq $76 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cnt_1_24 [1] - connect \B 1'1 - connect \Y $75 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" - wire width 3 $77 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" - cell $pos $78 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \Y_WIDTH 3 - connect \A { 1'1 \cnt_1_24 [0] } - connect \Y $77 - end - process $group_76 - assign \cnt_2_24 3'000 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - switch { $73 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - switch { $75 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - case 1'1 - assign \cnt_2_24 { 1'1 { 1'0 1'0 } } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:58" - case - assign \cnt_2_24 $77 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" - case - assign \cnt_2_24 { 1'0 \cnt_1_25 } - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:53" - wire width 3 \cnt_2_26 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - wire width 1 $79 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - cell $eq $80 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cnt_1_27 [1] - connect \B 1'1 - connect \Y $79 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - wire width 1 $81 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - cell $eq $82 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cnt_1_26 [1] - connect \B 1'1 - connect \Y $81 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" - wire width 3 $83 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" - cell $pos $84 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \Y_WIDTH 3 - connect \A { 1'1 \cnt_1_26 [0] } - connect \Y $83 - end - process $group_77 - assign \cnt_2_26 3'000 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - switch { $79 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - switch { $81 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - case 1'1 - assign \cnt_2_26 { 1'1 { 1'0 1'0 } } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:58" - case - assign \cnt_2_26 $83 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" - case - assign \cnt_2_26 { 1'0 \cnt_1_27 } - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:53" - wire width 3 \cnt_2_28 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - wire width 1 $85 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - cell $eq $86 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cnt_1_29 [1] - connect \B 1'1 - connect \Y $85 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - wire width 1 $87 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - cell $eq $88 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cnt_1_28 [1] - connect \B 1'1 - connect \Y $87 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" - wire width 3 $89 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" - cell $pos $90 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \Y_WIDTH 3 - connect \A { 1'1 \cnt_1_28 [0] } - connect \Y $89 - end - process $group_78 - assign \cnt_2_28 3'000 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - switch { $85 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - switch { $87 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - case 1'1 - assign \cnt_2_28 { 1'1 { 1'0 1'0 } } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:58" - case - assign \cnt_2_28 $89 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" - case - assign \cnt_2_28 { 1'0 \cnt_1_29 } - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:53" - wire width 3 \cnt_2_30 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - wire width 1 $91 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - cell $eq $92 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cnt_1_31 [1] - connect \B 1'1 - connect \Y $91 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - wire width 1 $93 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - cell $eq $94 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cnt_1_30 [1] - connect \B 1'1 - connect \Y $93 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" - wire width 3 $95 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" - cell $pos $96 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \Y_WIDTH 3 - connect \A { 1'1 \cnt_1_30 [0] } - connect \Y $95 - end - process $group_79 - assign \cnt_2_30 3'000 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - switch { $91 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - switch { $93 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - case 1'1 - assign \cnt_2_30 { 1'1 { 1'0 1'0 } } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:58" - case - assign \cnt_2_30 $95 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" - case - assign \cnt_2_30 { 1'0 \cnt_1_31 } - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:53" - wire width 4 \cnt_3_0 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - wire width 1 $97 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - cell $eq $98 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cnt_2_2 [2] - connect \B 1'1 - connect \Y $97 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - wire width 1 $99 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - cell $eq $100 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cnt_2_0 [2] - connect \B 1'1 - connect \Y $99 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" - wire width 4 $101 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" - cell $pos $102 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 4 - connect \A { 1'1 \cnt_2_0 [1:0] } - connect \Y $101 - end - process $group_80 - assign \cnt_3_0 4'0000 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - switch { $97 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - switch { $99 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - case 1'1 - assign \cnt_3_0 { 1'1 { 1'0 1'0 1'0 } } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:58" - case - assign \cnt_3_0 $101 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" - case - assign \cnt_3_0 { 1'0 \cnt_2_2 } - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:53" - wire width 4 \cnt_3_2 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - wire width 1 $103 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - cell $eq $104 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cnt_2_6 [2] - connect \B 1'1 - connect \Y $103 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - wire width 1 $105 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - cell $eq $106 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cnt_2_4 [2] - connect \B 1'1 - connect \Y $105 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" - wire width 4 $107 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" - cell $pos $108 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 4 - connect \A { 1'1 \cnt_2_4 [1:0] } - connect \Y $107 - end - process $group_81 - assign \cnt_3_2 4'0000 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - switch { $103 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - switch { $105 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - case 1'1 - assign \cnt_3_2 { 1'1 { 1'0 1'0 1'0 } } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:58" - case - assign \cnt_3_2 $107 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" - case - assign \cnt_3_2 { 1'0 \cnt_2_6 } - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:53" - wire width 4 \cnt_3_4 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - wire width 1 $109 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - cell $eq $110 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cnt_2_10 [2] - connect \B 1'1 - connect \Y $109 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - wire width 1 $111 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - cell $eq $112 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cnt_2_8 [2] - connect \B 1'1 - connect \Y $111 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" - wire width 4 $113 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" - cell $pos $114 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 4 - connect \A { 1'1 \cnt_2_8 [1:0] } - connect \Y $113 - end - process $group_82 - assign \cnt_3_4 4'0000 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - switch { $109 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - switch { $111 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - case 1'1 - assign \cnt_3_4 { 1'1 { 1'0 1'0 1'0 } } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:58" - case - assign \cnt_3_4 $113 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" - case - assign \cnt_3_4 { 1'0 \cnt_2_10 } - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:53" - wire width 4 \cnt_3_6 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - wire width 1 $115 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - cell $eq $116 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cnt_2_14 [2] - connect \B 1'1 - connect \Y $115 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - wire width 1 $117 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - cell $eq $118 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cnt_2_12 [2] - connect \B 1'1 - connect \Y $117 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" - wire width 4 $119 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" - cell $pos $120 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 4 - connect \A { 1'1 \cnt_2_12 [1:0] } - connect \Y $119 - end - process $group_83 - assign \cnt_3_6 4'0000 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - switch { $115 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - switch { $117 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - case 1'1 - assign \cnt_3_6 { 1'1 { 1'0 1'0 1'0 } } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:58" - case - assign \cnt_3_6 $119 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" - case - assign \cnt_3_6 { 1'0 \cnt_2_14 } - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:53" - wire width 4 \cnt_3_8 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - wire width 1 $121 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - cell $eq $122 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cnt_2_18 [2] - connect \B 1'1 - connect \Y $121 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - wire width 1 $123 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - cell $eq $124 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cnt_2_16 [2] - connect \B 1'1 - connect \Y $123 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" - wire width 4 $125 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" - cell $pos $126 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 4 - connect \A { 1'1 \cnt_2_16 [1:0] } - connect \Y $125 - end - process $group_84 - assign \cnt_3_8 4'0000 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - switch { $121 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - switch { $123 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - case 1'1 - assign \cnt_3_8 { 1'1 { 1'0 1'0 1'0 } } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:58" - case - assign \cnt_3_8 $125 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" - case - assign \cnt_3_8 { 1'0 \cnt_2_18 } - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:53" - wire width 4 \cnt_3_10 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - wire width 1 $127 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - cell $eq $128 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cnt_2_22 [2] - connect \B 1'1 - connect \Y $127 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - wire width 1 $129 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - cell $eq $130 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cnt_2_20 [2] - connect \B 1'1 - connect \Y $129 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" - wire width 4 $131 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" - cell $pos $132 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 4 - connect \A { 1'1 \cnt_2_20 [1:0] } - connect \Y $131 - end - process $group_85 - assign \cnt_3_10 4'0000 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - switch { $127 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - switch { $129 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - case 1'1 - assign \cnt_3_10 { 1'1 { 1'0 1'0 1'0 } } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:58" - case - assign \cnt_3_10 $131 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" - case - assign \cnt_3_10 { 1'0 \cnt_2_22 } - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:53" - wire width 4 \cnt_3_12 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - wire width 1 $133 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - cell $eq $134 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cnt_2_26 [2] - connect \B 1'1 - connect \Y $133 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - wire width 1 $135 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - cell $eq $136 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cnt_2_24 [2] - connect \B 1'1 - connect \Y $135 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" - wire width 4 $137 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" - cell $pos $138 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 4 - connect \A { 1'1 \cnt_2_24 [1:0] } - connect \Y $137 - end - process $group_86 - assign \cnt_3_12 4'0000 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - switch { $133 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - switch { $135 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - case 1'1 - assign \cnt_3_12 { 1'1 { 1'0 1'0 1'0 } } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:58" - case - assign \cnt_3_12 $137 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" - case - assign \cnt_3_12 { 1'0 \cnt_2_26 } - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:53" - wire width 4 \cnt_3_14 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - wire width 1 $139 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - cell $eq $140 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cnt_2_30 [2] - connect \B 1'1 - connect \Y $139 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - wire width 1 $141 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - cell $eq $142 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cnt_2_28 [2] - connect \B 1'1 - connect \Y $141 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" - wire width 4 $143 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" - cell $pos $144 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 4 - connect \A { 1'1 \cnt_2_28 [1:0] } - connect \Y $143 - end - process $group_87 - assign \cnt_3_14 4'0000 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - switch { $139 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - switch { $141 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - case 1'1 - assign \cnt_3_14 { 1'1 { 1'0 1'0 1'0 } } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:58" - case - assign \cnt_3_14 $143 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" - case - assign \cnt_3_14 { 1'0 \cnt_2_30 } - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:53" - wire width 5 \cnt_4_0 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - wire width 1 $145 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - cell $eq $146 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cnt_3_2 [3] - connect \B 1'1 - connect \Y $145 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - wire width 1 $147 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - cell $eq $148 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cnt_3_0 [3] - connect \B 1'1 - connect \Y $147 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" - wire width 5 $149 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" - cell $pos $150 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \Y_WIDTH 5 - connect \A { 1'1 \cnt_3_0 [2:0] } - connect \Y $149 - end - process $group_88 - assign \cnt_4_0 5'00000 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - switch { $145 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - switch { $147 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - case 1'1 - assign \cnt_4_0 { 1'1 { 1'0 1'0 1'0 1'0 } } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:58" - case - assign \cnt_4_0 $149 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" - case - assign \cnt_4_0 { 1'0 \cnt_3_2 } - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:53" - wire width 5 \cnt_4_2 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - wire width 1 $151 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - cell $eq $152 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cnt_3_6 [3] - connect \B 1'1 - connect \Y $151 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - wire width 1 $153 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - cell $eq $154 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cnt_3_4 [3] - connect \B 1'1 - connect \Y $153 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" - wire width 5 $155 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" - cell $pos $156 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \Y_WIDTH 5 - connect \A { 1'1 \cnt_3_4 [2:0] } - connect \Y $155 - end - process $group_89 - assign \cnt_4_2 5'00000 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - switch { $151 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - switch { $153 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - case 1'1 - assign \cnt_4_2 { 1'1 { 1'0 1'0 1'0 1'0 } } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:58" - case - assign \cnt_4_2 $155 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" - case - assign \cnt_4_2 { 1'0 \cnt_3_6 } - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:53" - wire width 5 \cnt_4_4 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - wire width 1 $157 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - cell $eq $158 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cnt_3_10 [3] - connect \B 1'1 - connect \Y $157 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - wire width 1 $159 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - cell $eq $160 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cnt_3_8 [3] - connect \B 1'1 - connect \Y $159 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" - wire width 5 $161 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" - cell $pos $162 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \Y_WIDTH 5 - connect \A { 1'1 \cnt_3_8 [2:0] } - connect \Y $161 - end - process $group_90 - assign \cnt_4_4 5'00000 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - switch { $157 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - switch { $159 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - case 1'1 - assign \cnt_4_4 { 1'1 { 1'0 1'0 1'0 1'0 } } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:58" - case - assign \cnt_4_4 $161 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" - case - assign \cnt_4_4 { 1'0 \cnt_3_10 } - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:53" - wire width 5 \cnt_4_6 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - wire width 1 $163 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - cell $eq $164 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cnt_3_14 [3] - connect \B 1'1 - connect \Y $163 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - wire width 1 $165 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - cell $eq $166 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cnt_3_12 [3] - connect \B 1'1 - connect \Y $165 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" - wire width 5 $167 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" - cell $pos $168 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \Y_WIDTH 5 - connect \A { 1'1 \cnt_3_12 [2:0] } - connect \Y $167 - end - process $group_91 - assign \cnt_4_6 5'00000 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - switch { $163 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - switch { $165 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - case 1'1 - assign \cnt_4_6 { 1'1 { 1'0 1'0 1'0 1'0 } } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:58" - case - assign \cnt_4_6 $167 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" - case - assign \cnt_4_6 { 1'0 \cnt_3_14 } - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:53" - wire width 6 \cnt_5_0 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - wire width 1 $169 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - cell $eq $170 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cnt_4_2 [4] - connect \B 1'1 - connect \Y $169 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - wire width 1 $171 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - cell $eq $172 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cnt_4_0 [4] - connect \B 1'1 - connect \Y $171 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" - wire width 6 $173 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" - cell $pos $174 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \Y_WIDTH 6 - connect \A { 1'1 \cnt_4_0 [3:0] } - connect \Y $173 - end - process $group_92 - assign \cnt_5_0 6'000000 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - switch { $169 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - switch { $171 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - case 1'1 - assign \cnt_5_0 { 1'1 { 1'0 1'0 1'0 1'0 1'0 } } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:58" - case - assign \cnt_5_0 $173 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" - case - assign \cnt_5_0 { 1'0 \cnt_4_2 } - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:53" - wire width 6 \cnt_5_2 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - wire width 1 $175 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - cell $eq $176 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cnt_4_6 [4] - connect \B 1'1 - connect \Y $175 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - wire width 1 $177 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - cell $eq $178 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cnt_4_4 [4] - connect \B 1'1 - connect \Y $177 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" - wire width 6 $179 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" - cell $pos $180 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \Y_WIDTH 6 - connect \A { 1'1 \cnt_4_4 [3:0] } - connect \Y $179 - end - process $group_93 - assign \cnt_5_2 6'000000 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - switch { $175 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - switch { $177 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - case 1'1 - assign \cnt_5_2 { 1'1 { 1'0 1'0 1'0 1'0 1'0 } } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:58" - case - assign \cnt_5_2 $179 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" - case - assign \cnt_5_2 { 1'0 \cnt_4_6 } - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:53" - wire width 7 \cnt_6_0 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - wire width 1 $181 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - cell $eq $182 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cnt_5_2 [5] - connect \B 1'1 - connect \Y $181 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - wire width 1 $183 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - cell $eq $184 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cnt_5_0 [5] - connect \B 1'1 - connect \Y $183 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" - wire width 7 $185 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:59" - cell $pos $186 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \Y_WIDTH 7 - connect \A { 1'1 \cnt_5_0 [4:0] } - connect \Y $185 - end - process $group_94 - assign \cnt_6_0 7'0000000 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - switch { $181 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:55" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - switch { $183 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:56" - case 1'1 - assign \cnt_6_0 { 1'1 { 1'0 1'0 1'0 1'0 1'0 1'0 } } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:58" - case - assign \cnt_6_0 $185 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:60" - case - assign \cnt_6_0 { 1'0 \cnt_5_2 } - end - sync init - end - process $group_95 - assign \lz 7'0000000 - assign \lz \cnt_6_0 - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.logical0.alu_logical0.logical_pipe1.main" -module \main$48 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 input 0 \muxid - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 input 1 \logical_op__insn_type - attribute \enum_base_type "Function" - attribute \enum_value_00000000000 "NONE" - attribute \enum_value_00000000010 "ALU" - attribute \enum_value_00000000100 "LDST" - attribute \enum_value_00000001000 "SHIFT_ROT" - attribute \enum_value_00000010000 "LOGICAL" - attribute \enum_value_00000100000 "BRANCH" - attribute \enum_value_00001000000 "CR" - attribute \enum_value_00010000000 "TRAP" - attribute \enum_value_00100000000 "MUL" - attribute \enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 input 2 \logical_op__fn_unit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 input 3 \logical_op__imm_data__data - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 4 \logical_op__imm_data__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 5 \logical_op__rc__rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 6 \logical_op__rc__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 7 \logical_op__oe__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 8 \logical_op__oe__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 9 \logical_op__invert_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 10 \logical_op__zero_a - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 input 11 \logical_op__input_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 12 \logical_op__invert_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 13 \logical_op__write_cr0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 14 \logical_op__output_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 15 \logical_op__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 16 \logical_op__is_signed - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 input 17 \logical_op__data_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 input 18 \logical_op__insn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 19 \ra - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 20 \rb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 1 input 21 \xer_so - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 output 22 \muxid$1 - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 output 23 \logical_op__insn_type$2 - attribute \enum_base_type "Function" - attribute \enum_value_00000000000 "NONE" - attribute \enum_value_00000000010 "ALU" - attribute \enum_value_00000000100 "LDST" - attribute \enum_value_00000001000 "SHIFT_ROT" - attribute \enum_value_00000010000 "LOGICAL" - attribute \enum_value_00000100000 "BRANCH" - attribute \enum_value_00001000000 "CR" - attribute \enum_value_00010000000 "TRAP" - attribute \enum_value_00100000000 "MUL" - attribute \enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 output 24 \logical_op__fn_unit$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 output 25 \logical_op__imm_data__data$4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 26 \logical_op__imm_data__ok$5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 27 \logical_op__rc__rc$6 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 28 \logical_op__rc__ok$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 29 \logical_op__oe__oe$8 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 30 \logical_op__oe__ok$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 31 \logical_op__invert_in$10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 32 \logical_op__zero_a$11 - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 output 33 \logical_op__input_carry$12 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 34 \logical_op__invert_out$13 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 35 \logical_op__write_cr0$14 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 36 \logical_op__output_carry$15 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 37 \logical_op__is_32bit$16 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 38 \logical_op__is_signed$17 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 output 39 \logical_op__data_len$18 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 output 40 \logical_op__insn$19 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 output 41 \o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 42 \o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 43 \xer_so$20 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:54" - wire width 64 \bpermd_rs - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:56" - wire width 64 \bpermd_rb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/bpermd.py:55" - wire width 64 \bpermd_ra - cell \bpermd \bpermd - connect \rs \bpermd_rs - connect \rb \bpermd_rb - connect \ra \bpermd_ra - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:27" - wire width 64 \popcount_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:29" - wire width 64 \popcount_data_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:30" - wire width 64 \popcount_o - cell \popcount \popcount - connect \a \popcount_a - connect \data_len \popcount_data_len - connect \o \popcount_o - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:11" - wire width 64 \clz_sig_in - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:13" - wire width 7 \clz_lz - cell \clz \clz - connect \sig_in \clz_sig_in - connect \lz \clz_lz - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:54" - wire width 64 $21 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:54" - cell $and $22 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \B_SIGNED 0 - parameter \B_WIDTH 64 - parameter \Y_WIDTH 64 - connect \A \ra - connect \B \rb - connect \Y $21 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:56" - wire width 64 $23 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:56" - cell $or $24 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \B_SIGNED 0 - parameter \B_WIDTH 64 - parameter \Y_WIDTH 64 - connect \A \ra - connect \B \rb - connect \Y $23 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:58" - wire width 64 $25 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:58" - cell $xor $26 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \B_SIGNED 0 - parameter \B_WIDTH 64 - parameter \Y_WIDTH 64 - connect \A \ra - connect \B \rb - connect \Y $25 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - wire width 1 $27 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $28 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \ra [7:0] - connect \B \rb [7:0] - connect \Y $27 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - wire width 1 $29 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $30 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \ra [7:0] - connect \B \rb [7:0] - connect \Y $29 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - wire width 1 $31 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $32 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \ra [7:0] - connect \B \rb [7:0] - connect \Y $31 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - wire width 1 $33 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $34 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \ra [7:0] - connect \B \rb [7:0] - connect \Y $33 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - wire width 1 $35 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $36 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \ra [7:0] - connect \B \rb [7:0] - connect \Y $35 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - wire width 1 $37 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $38 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \ra [7:0] - connect \B \rb [7:0] - connect \Y $37 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - wire width 1 $39 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $40 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \ra [7:0] - connect \B \rb [7:0] - connect \Y $39 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - wire width 1 $41 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $42 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \ra [7:0] - connect \B \rb [7:0] - connect \Y $41 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - wire width 1 $43 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $44 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \ra [15:8] - connect \B \rb [15:8] - connect \Y $43 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - wire width 1 $45 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $46 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \ra [15:8] - connect \B \rb [15:8] - connect \Y $45 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - wire width 1 $47 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $48 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \ra [15:8] - connect \B \rb [15:8] - connect \Y $47 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - wire width 1 $49 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $50 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \ra [15:8] - connect \B \rb [15:8] - connect \Y $49 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - wire width 1 $51 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $52 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \ra [15:8] - connect \B \rb [15:8] - connect \Y $51 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - wire width 1 $53 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $54 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \ra [15:8] - connect \B \rb [15:8] - connect \Y $53 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - wire width 1 $55 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $56 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \ra [15:8] - connect \B \rb [15:8] - connect \Y $55 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - wire width 1 $57 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $58 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \ra [15:8] - connect \B \rb [15:8] - connect \Y $57 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - wire width 1 $59 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $60 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \ra [23:16] - connect \B \rb [23:16] - connect \Y $59 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - wire width 1 $61 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $62 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \ra [23:16] - connect \B \rb [23:16] - connect \Y $61 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - wire width 1 $63 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $64 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \ra [23:16] - connect \B \rb [23:16] - connect \Y $63 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - wire width 1 $65 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $66 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \ra [23:16] - connect \B \rb [23:16] - connect \Y $65 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - wire width 1 $67 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $68 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \ra [23:16] - connect \B \rb [23:16] - connect \Y $67 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - wire width 1 $69 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $70 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \ra [23:16] - connect \B \rb [23:16] - connect \Y $69 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - wire width 1 $71 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $72 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \ra [23:16] - connect \B \rb [23:16] - connect \Y $71 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - wire width 1 $73 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $74 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \ra [23:16] - connect \B \rb [23:16] - connect \Y $73 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - wire width 1 $75 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $76 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \ra [31:24] - connect \B \rb [31:24] - connect \Y $75 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - wire width 1 $77 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $78 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \ra [31:24] - connect \B \rb [31:24] - connect \Y $77 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - wire width 1 $79 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $80 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \ra [31:24] - connect \B \rb [31:24] - connect \Y $79 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - wire width 1 $81 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $82 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \ra [31:24] - connect \B \rb [31:24] - connect \Y $81 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - wire width 1 $83 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $84 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \ra [31:24] - connect \B \rb [31:24] - connect \Y $83 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - wire width 1 $85 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $86 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \ra [31:24] - connect \B \rb [31:24] - connect \Y $85 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - wire width 1 $87 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $88 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \ra [31:24] - connect \B \rb [31:24] - connect \Y $87 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - wire width 1 $89 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $90 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \ra [31:24] - connect \B \rb [31:24] - connect \Y $89 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - wire width 1 $91 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $92 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \ra [39:32] - connect \B \rb [39:32] - connect \Y $91 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - wire width 1 $93 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $94 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \ra [39:32] - connect \B \rb [39:32] - connect \Y $93 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - wire width 1 $95 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $96 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \ra [39:32] - connect \B \rb [39:32] - connect \Y $95 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - wire width 1 $97 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $98 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \ra [39:32] - connect \B \rb [39:32] - connect \Y $97 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - wire width 1 $99 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $100 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \ra [39:32] - connect \B \rb [39:32] - connect \Y $99 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - wire width 1 $101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $102 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \ra [39:32] - connect \B \rb [39:32] - connect \Y $101 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - wire width 1 $103 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $104 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \ra [39:32] - connect \B \rb [39:32] - connect \Y $103 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - wire width 1 $105 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $106 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \ra [39:32] - connect \B \rb [39:32] - connect \Y $105 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - wire width 1 $107 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $108 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \ra [47:40] - connect \B \rb [47:40] - connect \Y $107 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - wire width 1 $109 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $110 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \ra [47:40] - connect \B \rb [47:40] - connect \Y $109 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - wire width 1 $111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $112 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \ra [47:40] - connect \B \rb [47:40] - connect \Y $111 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - wire width 1 $113 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $114 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \ra [47:40] - connect \B \rb [47:40] - connect \Y $113 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - wire width 1 $115 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $116 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \ra [47:40] - connect \B \rb [47:40] - connect \Y $115 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - wire width 1 $117 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $118 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \ra [47:40] - connect \B \rb [47:40] - connect \Y $117 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - wire width 1 $119 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $120 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \ra [47:40] - connect \B \rb [47:40] - connect \Y $119 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - wire width 1 $121 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $122 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \ra [47:40] - connect \B \rb [47:40] - connect \Y $121 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - wire width 1 $123 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $124 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \ra [55:48] - connect \B \rb [55:48] - connect \Y $123 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - wire width 1 $125 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $126 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \ra [55:48] - connect \B \rb [55:48] - connect \Y $125 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - wire width 1 $127 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $128 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \ra [55:48] - connect \B \rb [55:48] - connect \Y $127 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - wire width 1 $129 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $130 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \ra [55:48] - connect \B \rb [55:48] - connect \Y $129 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - wire width 1 $131 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $132 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \ra [55:48] - connect \B \rb [55:48] - connect \Y $131 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - wire width 1 $133 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $134 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \ra [55:48] - connect \B \rb [55:48] - connect \Y $133 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - wire width 1 $135 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $136 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \ra [55:48] - connect \B \rb [55:48] - connect \Y $135 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - wire width 1 $137 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $138 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \ra [55:48] - connect \B \rb [55:48] - connect \Y $137 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - wire width 1 $139 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $140 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \ra [63:56] - connect \B \rb [63:56] - connect \Y $139 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - wire width 1 $141 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $142 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \ra [63:56] - connect \B \rb [63:56] - connect \Y $141 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - wire width 1 $143 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $144 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \ra [63:56] - connect \B \rb [63:56] - connect \Y $143 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - wire width 1 $145 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $146 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \ra [63:56] - connect \B \rb [63:56] - connect \Y $145 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - wire width 1 $147 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $148 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \ra [63:56] - connect \B \rb [63:56] - connect \Y $147 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - wire width 1 $149 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $150 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \ra [63:56] - connect \B \rb [63:56] - connect \Y $149 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - wire width 1 $151 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $152 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \ra [63:56] - connect \B \rb [63:56] - connect \Y $151 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - wire width 1 $153 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:67" - cell $eq $154 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \ra [63:56] - connect \B \rb [63:56] - connect \Y $153 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:88" - wire width 1 $155 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:88" - cell $eq $156 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \logical_op__data_len [3] - connect \B 1'1 - connect \Y $155 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:89" - wire width 64 $157 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:84" - wire width 1 \par0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:85" - wire width 1 \par1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:89" - wire width 1 $158 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:89" - cell $xor $159 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \par0 - connect \B \par1 - connect \Y $158 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:89" - cell $pos $160 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 64 - connect \A $158 - connect \Y $157 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:113" - wire width 64 $161 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:113" - wire width 8 $162 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:113" - cell $sub $163 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 8 - connect \A \clz_lz - connect \B 6'100000 - connect \Y $162 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:13" - wire width 8 $164 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/clz.py:13" - cell $pos $165 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \Y_WIDTH 8 - connect \A \clz_lz - connect \Y $164 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:113" - wire width 8 $166 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:113" - cell $mux $167 - parameter \WIDTH 8 - connect \A $164 - connect \B $162 - connect \S \logical_op__is_32bit - connect \Y $166 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:113" - cell $pos $168 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \Y_WIDTH 64 - connect \A $166 - connect \Y $161 - end - process $group_1 - assign \o_ok 1'0 - assign \o 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \o_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:48" - switch \logical_op__insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:53" - attribute \nmigen.decoding "OP_AND/4" - case 7'0000100 - assign \o $21 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:55" - attribute \nmigen.decoding "OP_OR/53" - case 7'0110101 - assign \o $23 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:57" - attribute \nmigen.decoding "OP_XOR/67" - case 7'1000011 - assign \o $25 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:63" - attribute \nmigen.decoding "OP_CMPB/11" - case 7'0001011 - assign \o { { $139 $141 $143 $145 $147 $149 $151 $153 } { $123 $125 $127 $129 $131 $133 $135 $137 } { $107 $109 $111 $113 $115 $117 $119 $121 } { $91 $93 $95 $97 $99 $101 $103 $105 } { $75 $77 $79 $81 $83 $85 $87 $89 } { $59 $61 $63 $65 $67 $69 $71 $73 } { $43 $45 $47 $49 $51 $53 $55 $57 } { $27 $29 $31 $33 $35 $37 $39 $41 } } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:73" - attribute \nmigen.decoding "OP_POPCNT/54" - case 7'0110110 - assign \o \popcount_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:82" - attribute \nmigen.decoding "OP_PRTY/55" - case 7'0110111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:88" - switch { $155 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:88" - case 1'1 - assign \o $157 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:90" - case - assign { \o_ok \o } [0] \par0 - assign { \o_ok \o } [32] \par1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:97" - attribute \nmigen.decoding "OP_CNTZ/14" - case 7'0001110 - assign \o $161 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:118" - attribute \nmigen.decoding "OP_BPERM/9" - case 7'0001001 - assign \o \bpermd_ra - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:123" - attribute \nmigen.decoding "" - case - assign \o_ok 1'0 - end - sync init - end - process $group_2 - assign \popcount_a 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:48" - switch \logical_op__insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:53" - attribute \nmigen.decoding "OP_AND/4" - case 7'0000100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:55" - attribute \nmigen.decoding "OP_OR/53" - case 7'0110101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:57" - attribute \nmigen.decoding "OP_XOR/67" - case 7'1000011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:63" - attribute \nmigen.decoding "OP_CMPB/11" - case 7'0001011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:73" - attribute \nmigen.decoding "OP_POPCNT/54" - case 7'0110110 - assign \popcount_a \ra - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:82" - attribute \nmigen.decoding "OP_PRTY/55" - case 7'0110111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:97" - attribute \nmigen.decoding "OP_CNTZ/14" - case 7'0001110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:118" - attribute \nmigen.decoding "OP_BPERM/9" - case 7'0001001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:123" - attribute \nmigen.decoding "" - case - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/popcount.py:28" - wire width 64 \b - process $group_3 - assign \b 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:48" - switch \logical_op__insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:53" - attribute \nmigen.decoding "OP_AND/4" - case 7'0000100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:55" - attribute \nmigen.decoding "OP_OR/53" - case 7'0110101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:57" - attribute \nmigen.decoding "OP_XOR/67" - case 7'1000011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:63" - attribute \nmigen.decoding "OP_CMPB/11" - case 7'0001011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:73" - attribute \nmigen.decoding "OP_POPCNT/54" - case 7'0110110 - assign \b \rb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:82" - attribute \nmigen.decoding "OP_PRTY/55" - case 7'0110111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:97" - attribute \nmigen.decoding "OP_CNTZ/14" - case 7'0001110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:118" - attribute \nmigen.decoding "OP_BPERM/9" - case 7'0001001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:123" - attribute \nmigen.decoding "" - case - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 $169 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - cell $pos $170 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \Y_WIDTH 64 - connect \A \logical_op__data_len - connect \Y $169 - end - process $group_4 - assign \popcount_data_len 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:48" - switch \logical_op__insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:53" - attribute \nmigen.decoding "OP_AND/4" - case 7'0000100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:55" - attribute \nmigen.decoding "OP_OR/53" - case 7'0110101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:57" - attribute \nmigen.decoding "OP_XOR/67" - case 7'1000011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:63" - attribute \nmigen.decoding "OP_CMPB/11" - case 7'0001011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:73" - attribute \nmigen.decoding "OP_POPCNT/54" - case 7'0110110 - assign \popcount_data_len $169 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:82" - attribute \nmigen.decoding "OP_PRTY/55" - case 7'0110111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:97" - attribute \nmigen.decoding "OP_CNTZ/14" - case 7'0001110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:118" - attribute \nmigen.decoding "OP_BPERM/9" - case 7'0001001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:123" - attribute \nmigen.decoding "" - case - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:86" - wire width 1 $171 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:86" - cell $reduce_xor $172 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A { \ra [24] \ra [16] \ra [8] \ra [0] } - connect \Y $171 - end - process $group_5 - assign \par0 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:48" - switch \logical_op__insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:53" - attribute \nmigen.decoding "OP_AND/4" - case 7'0000100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:55" - attribute \nmigen.decoding "OP_OR/53" - case 7'0110101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:57" - attribute \nmigen.decoding "OP_XOR/67" - case 7'1000011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:63" - attribute \nmigen.decoding "OP_CMPB/11" - case 7'0001011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:73" - attribute \nmigen.decoding "OP_POPCNT/54" - case 7'0110110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:82" - attribute \nmigen.decoding "OP_PRTY/55" - case 7'0110111 - assign \par0 $171 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:97" - attribute \nmigen.decoding "OP_CNTZ/14" - case 7'0001110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:118" - attribute \nmigen.decoding "OP_BPERM/9" - case 7'0001001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:123" - attribute \nmigen.decoding "" - case - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:87" - wire width 1 $173 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:87" - cell $reduce_xor $174 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A { \ra [56] \ra [48] \ra [40] \ra [32] } - connect \Y $173 - end - process $group_6 - assign \par1 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:48" - switch \logical_op__insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:53" - attribute \nmigen.decoding "OP_AND/4" - case 7'0000100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:55" - attribute \nmigen.decoding "OP_OR/53" - case 7'0110101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:57" - attribute \nmigen.decoding "OP_XOR/67" - case 7'1000011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:63" - attribute \nmigen.decoding "OP_CMPB/11" - case 7'0001011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:73" - attribute \nmigen.decoding "OP_POPCNT/54" - case 7'0110110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:82" - attribute \nmigen.decoding "OP_PRTY/55" - case 7'0110111 - assign \par1 $173 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:97" - attribute \nmigen.decoding "OP_CNTZ/14" - case 7'0001110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:118" - attribute \nmigen.decoding "OP_BPERM/9" - case 7'0001001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:123" - attribute \nmigen.decoding "" - case - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:99" - wire width 1 \count_right - process $group_7 - assign \count_right 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:48" - switch \logical_op__insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:53" - attribute \nmigen.decoding "OP_AND/4" - case 7'0000100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:55" - attribute \nmigen.decoding "OP_OR/53" - case 7'0110101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:57" - attribute \nmigen.decoding "OP_XOR/67" - case 7'1000011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:63" - attribute \nmigen.decoding "OP_CMPB/11" - case 7'0001011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:73" - attribute \nmigen.decoding "OP_POPCNT/54" - case 7'0110110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:82" - attribute \nmigen.decoding "OP_PRTY/55" - case 7'0110111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:97" - attribute \nmigen.decoding "OP_CNTZ/14" - case 7'0001110 - assign \count_right { \logical_op__insn [10] \logical_op__insn [9] \logical_op__insn [8] \logical_op__insn [7] \logical_op__insn [6] \logical_op__insn [5] \logical_op__insn [4] \logical_op__insn [3] \logical_op__insn [2] \logical_op__insn [1] } [9] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:118" - attribute \nmigen.decoding "OP_BPERM/9" - case 7'0001001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:123" - attribute \nmigen.decoding "" - case - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:103" - wire width 32 \a32 - process $group_8 - assign \a32 32'00000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:48" - switch \logical_op__insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:53" - attribute \nmigen.decoding "OP_AND/4" - case 7'0000100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:55" - attribute \nmigen.decoding "OP_OR/53" - case 7'0110101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:57" - attribute \nmigen.decoding "OP_XOR/67" - case 7'1000011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:63" - attribute \nmigen.decoding "OP_CMPB/11" - case 7'0001011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:73" - attribute \nmigen.decoding "OP_POPCNT/54" - case 7'0110110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:82" - attribute \nmigen.decoding "OP_PRTY/55" - case 7'0110111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:97" - attribute \nmigen.decoding "OP_CNTZ/14" - case 7'0001110 - assign \a32 \ra [31:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:118" - attribute \nmigen.decoding "OP_BPERM/9" - case 7'0001001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:123" - attribute \nmigen.decoding "" - case - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:102" - wire width 64 \cntz_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:107" - wire width 64 $175 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:107" - wire width 32 $176 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:107" - cell $mux $177 - parameter \WIDTH 32 - connect \A \a32 - connect \B { \a32 [0] \a32 [1] \a32 [2] \a32 [3] \a32 [4] \a32 [5] \a32 [6] \a32 [7] \a32 [8] \a32 [9] \a32 [10] \a32 [11] \a32 [12] \a32 [13] \a32 [14] \a32 [15] \a32 [16] \a32 [17] \a32 [18] \a32 [19] \a32 [20] \a32 [21] \a32 [22] \a32 [23] \a32 [24] \a32 [25] \a32 [26] \a32 [27] \a32 [28] \a32 [29] \a32 [30] \a32 [31] } - connect \S \count_right - connect \Y $176 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:107" - cell $pos $178 - parameter \A_SIGNED 0 - parameter \A_WIDTH 32 - parameter \Y_WIDTH 64 - connect \A $176 - connect \Y $175 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:109" - wire width 64 $179 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:109" - cell $mux $180 - parameter \WIDTH 64 - connect \A \ra - connect \B { \ra [0] \ra [1] \ra [2] \ra [3] \ra [4] \ra [5] \ra [6] \ra [7] \ra [8] \ra [9] \ra [10] \ra [11] \ra [12] \ra [13] \ra [14] \ra [15] \ra [16] \ra [17] \ra [18] \ra [19] \ra [20] \ra [21] \ra [22] \ra [23] \ra [24] \ra [25] \ra [26] \ra [27] \ra [28] \ra [29] \ra [30] \ra [31] \ra [32] \ra [33] \ra [34] \ra [35] \ra [36] \ra [37] \ra [38] \ra [39] \ra [40] \ra [41] \ra [42] \ra [43] \ra [44] \ra [45] \ra [46] \ra [47] \ra [48] \ra [49] \ra [50] \ra [51] \ra [52] \ra [53] \ra [54] \ra [55] \ra [56] \ra [57] \ra [58] \ra [59] \ra [60] \ra [61] \ra [62] \ra [63] } - connect \S \count_right - connect \Y $179 - end - process $group_9 - assign \cntz_i 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:48" - switch \logical_op__insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:53" - attribute \nmigen.decoding "OP_AND/4" - case 7'0000100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:55" - attribute \nmigen.decoding "OP_OR/53" - case 7'0110101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:57" - attribute \nmigen.decoding "OP_XOR/67" - case 7'1000011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:63" - attribute \nmigen.decoding "OP_CMPB/11" - case 7'0001011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:73" - attribute \nmigen.decoding "OP_POPCNT/54" - case 7'0110110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:82" - attribute \nmigen.decoding "OP_PRTY/55" - case 7'0110111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:97" - attribute \nmigen.decoding "OP_CNTZ/14" - case 7'0001110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:106" - switch { \logical_op__is_32bit } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:106" - case 1'1 - assign \cntz_i $175 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:108" - case - assign \cntz_i $179 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:118" - attribute \nmigen.decoding "OP_BPERM/9" - case 7'0001001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:123" - attribute \nmigen.decoding "" - case - end - sync init - end - process $group_10 - assign \clz_sig_in 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:48" - switch \logical_op__insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:53" - attribute \nmigen.decoding "OP_AND/4" - case 7'0000100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:55" - attribute \nmigen.decoding "OP_OR/53" - case 7'0110101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:57" - attribute \nmigen.decoding "OP_XOR/67" - case 7'1000011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:63" - attribute \nmigen.decoding "OP_CMPB/11" - case 7'0001011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:73" - attribute \nmigen.decoding "OP_POPCNT/54" - case 7'0110110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:82" - attribute \nmigen.decoding "OP_PRTY/55" - case 7'0110111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:97" - attribute \nmigen.decoding "OP_CNTZ/14" - case 7'0001110 - assign \clz_sig_in \cntz_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:118" - attribute \nmigen.decoding "OP_BPERM/9" - case 7'0001001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:123" - attribute \nmigen.decoding "" - case - end - sync init - end - process $group_11 - assign \bpermd_rs 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:48" - switch \logical_op__insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:53" - attribute \nmigen.decoding "OP_AND/4" - case 7'0000100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:55" - attribute \nmigen.decoding "OP_OR/53" - case 7'0110101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:57" - attribute \nmigen.decoding "OP_XOR/67" - case 7'1000011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:63" - attribute \nmigen.decoding "OP_CMPB/11" - case 7'0001011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:73" - attribute \nmigen.decoding "OP_POPCNT/54" - case 7'0110110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:82" - attribute \nmigen.decoding "OP_PRTY/55" - case 7'0110111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:97" - attribute \nmigen.decoding "OP_CNTZ/14" - case 7'0001110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:118" - attribute \nmigen.decoding "OP_BPERM/9" - case 7'0001001 - assign \bpermd_rs \ra - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:123" - attribute \nmigen.decoding "" - case - end - sync init - end - process $group_12 - assign \bpermd_rb 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:48" - switch \logical_op__insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:53" - attribute \nmigen.decoding "OP_AND/4" - case 7'0000100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:55" - attribute \nmigen.decoding "OP_OR/53" - case 7'0110101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:57" - attribute \nmigen.decoding "OP_XOR/67" - case 7'1000011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:63" - attribute \nmigen.decoding "OP_CMPB/11" - case 7'0001011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:73" - attribute \nmigen.decoding "OP_POPCNT/54" - case 7'0110110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:82" - attribute \nmigen.decoding "OP_PRTY/55" - case 7'0110111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:97" - attribute \nmigen.decoding "OP_CNTZ/14" - case 7'0001110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:118" - attribute \nmigen.decoding "OP_BPERM/9" - case 7'0001001 - assign \bpermd_rb \rb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/logical/main_stage.py:123" - attribute \nmigen.decoding "" - case - end - sync init - end - process $group_13 - assign \xer_so$20 1'0 - assign \xer_so$20 \xer_so - sync init - end - process $group_14 - assign \muxid$1 2'00 - assign \muxid$1 \muxid - sync init - end - process $group_15 - assign \logical_op__insn_type$2 7'0000000 - assign \logical_op__fn_unit$3 11'00000000000 - assign \logical_op__imm_data__data$4 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \logical_op__imm_data__ok$5 1'0 - assign \logical_op__rc__rc$6 1'0 - assign \logical_op__rc__ok$7 1'0 - assign \logical_op__oe__oe$8 1'0 - assign \logical_op__oe__ok$9 1'0 - assign \logical_op__invert_in$10 1'0 - assign \logical_op__zero_a$11 1'0 - assign \logical_op__input_carry$12 2'00 - assign \logical_op__invert_out$13 1'0 - assign \logical_op__write_cr0$14 1'0 - assign \logical_op__output_carry$15 1'0 - assign \logical_op__is_32bit$16 1'0 - assign \logical_op__is_signed$17 1'0 - assign \logical_op__data_len$18 4'0000 - assign \logical_op__insn$19 32'00000000000000000000000000000000 - assign { \logical_op__insn$19 \logical_op__data_len$18 \logical_op__is_signed$17 \logical_op__is_32bit$16 \logical_op__output_carry$15 \logical_op__write_cr0$14 \logical_op__invert_out$13 \logical_op__input_carry$12 \logical_op__zero_a$11 \logical_op__invert_in$10 { \logical_op__oe__ok$9 \logical_op__oe__oe$8 } { \logical_op__rc__ok$7 \logical_op__rc__rc$6 } { \logical_op__imm_data__ok$5 \logical_op__imm_data__data$4 } \logical_op__fn_unit$3 \logical_op__insn_type$2 } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in { \logical_op__oe__ok \logical_op__oe__oe } { \logical_op__rc__ok \logical_op__rc__rc } { \logical_op__imm_data__ok \logical_op__imm_data__data } \logical_op__fn_unit \logical_op__insn_type } - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.logical0.alu_logical0.logical_pipe1" -module \logical_pipe1 - attribute \src "simple/issuer.py:141" - wire width 1 input 0 \coresync_clk - attribute \src "simple/issuer.py:141" - wire width 1 input 1 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" - wire width 1 output 2 \n_valid_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" - wire width 1 input 3 \n_ready_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 output 4 \muxid - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \muxid$next - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 output 5 \logical_op__insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \logical_op__insn_type$next - attribute \enum_base_type "Function" - attribute \enum_value_00000000000 "NONE" - attribute \enum_value_00000000010 "ALU" - attribute \enum_value_00000000100 "LDST" - attribute \enum_value_00000001000 "SHIFT_ROT" - attribute \enum_value_00000010000 "LOGICAL" - attribute \enum_value_00000100000 "BRANCH" - attribute \enum_value_00001000000 "CR" - attribute \enum_value_00010000000 "TRAP" - attribute \enum_value_00100000000 "MUL" - attribute \enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 output 6 \logical_op__fn_unit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 \logical_op__fn_unit$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 output 7 \logical_op__imm_data__data - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \logical_op__imm_data__data$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 8 \logical_op__imm_data__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__imm_data__ok$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 9 \logical_op__rc__rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__rc__rc$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 10 \logical_op__rc__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__rc__ok$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 11 \logical_op__oe__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__oe__oe$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 12 \logical_op__oe__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__oe__ok$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 13 \logical_op__invert_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__invert_in$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 14 \logical_op__zero_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__zero_a$next - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 output 15 \logical_op__input_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \logical_op__input_carry$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 16 \logical_op__invert_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__invert_out$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 17 \logical_op__write_cr0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__write_cr0$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 18 \logical_op__output_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__output_carry$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 19 \logical_op__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__is_32bit$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 20 \logical_op__is_signed - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__is_signed$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 output 21 \logical_op__data_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \logical_op__data_len$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 output 22 \logical_op__insn - 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\main_logical_op__zero_a - connect \logical_op__input_carry \main_logical_op__input_carry - connect \logical_op__invert_out \main_logical_op__invert_out - connect \logical_op__write_cr0 \main_logical_op__write_cr0 - connect \logical_op__output_carry \main_logical_op__output_carry - connect \logical_op__is_32bit \main_logical_op__is_32bit - connect \logical_op__is_signed \main_logical_op__is_signed - connect \logical_op__data_len \main_logical_op__data_len - connect \logical_op__insn \main_logical_op__insn - connect \ra \main_ra - connect \rb \main_rb - connect \xer_so \main_xer_so - connect \muxid$1 \main_muxid$43 - connect \logical_op__insn_type$2 \main_logical_op__insn_type$44 - connect \logical_op__fn_unit$3 \main_logical_op__fn_unit$45 - connect \logical_op__imm_data__data$4 \main_logical_op__imm_data__data$46 - connect \logical_op__imm_data__ok$5 \main_logical_op__imm_data__ok$47 - connect \logical_op__rc__rc$6 \main_logical_op__rc__rc$48 - connect \logical_op__rc__ok$7 \main_logical_op__rc__ok$49 - connect \logical_op__oe__oe$8 \main_logical_op__oe__oe$50 - connect \logical_op__oe__ok$9 \main_logical_op__oe__ok$51 - connect \logical_op__invert_in$10 \main_logical_op__invert_in$52 - connect \logical_op__zero_a$11 \main_logical_op__zero_a$53 - connect \logical_op__input_carry$12 \main_logical_op__input_carry$54 - connect \logical_op__invert_out$13 \main_logical_op__invert_out$55 - connect \logical_op__write_cr0$14 \main_logical_op__write_cr0$56 - connect \logical_op__output_carry$15 \main_logical_op__output_carry$57 - connect \logical_op__is_32bit$16 \main_logical_op__is_32bit$58 - connect \logical_op__is_signed$17 \main_logical_op__is_signed$59 - connect \logical_op__data_len$18 \main_logical_op__data_len$60 - connect \logical_op__insn$19 \main_logical_op__insn$61 - connect \o \main_o - connect \o_ok \main_o_ok - connect \xer_so$20 \main_xer_so$62 - end - process $group_0 - assign \input_muxid 2'00 - assign \input_muxid \muxid$1 - sync init - end - process $group_1 - assign \input_logical_op__insn_type 7'0000000 - assign \input_logical_op__fn_unit 11'00000000000 - assign \input_logical_op__imm_data__data 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \input_logical_op__imm_data__ok 1'0 - assign \input_logical_op__rc__rc 1'0 - assign \input_logical_op__rc__ok 1'0 - assign \input_logical_op__oe__oe 1'0 - assign \input_logical_op__oe__ok 1'0 - assign \input_logical_op__invert_in 1'0 - assign \input_logical_op__zero_a 1'0 - assign \input_logical_op__input_carry 2'00 - assign \input_logical_op__invert_out 1'0 - assign \input_logical_op__write_cr0 1'0 - assign \input_logical_op__output_carry 1'0 - assign \input_logical_op__is_32bit 1'0 - assign \input_logical_op__is_signed 1'0 - assign \input_logical_op__data_len 4'0000 - assign \input_logical_op__insn 32'00000000000000000000000000000000 - assign { \input_logical_op__insn \input_logical_op__data_len \input_logical_op__is_signed \input_logical_op__is_32bit \input_logical_op__output_carry \input_logical_op__write_cr0 \input_logical_op__invert_out \input_logical_op__input_carry \input_logical_op__zero_a \input_logical_op__invert_in { \input_logical_op__oe__ok \input_logical_op__oe__oe } { \input_logical_op__rc__ok \input_logical_op__rc__rc } { \input_logical_op__imm_data__ok \input_logical_op__imm_data__data } \input_logical_op__fn_unit \input_logical_op__insn_type } { \logical_op__insn$19 \logical_op__data_len$18 \logical_op__is_signed$17 \logical_op__is_32bit$16 \logical_op__output_carry$15 \logical_op__write_cr0$14 \logical_op__invert_out$13 \logical_op__input_carry$12 \logical_op__zero_a$11 \logical_op__invert_in$10 { \logical_op__oe__ok$9 \logical_op__oe__oe$8 } { \logical_op__rc__ok$7 \logical_op__rc__rc$6 } { \logical_op__imm_data__ok$5 \logical_op__imm_data__data$4 } \logical_op__fn_unit$3 \logical_op__insn_type$2 } - sync init - end - process $group_19 - assign \input_ra 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \input_ra \ra - sync init - end - process $group_20 - assign \input_rb 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \input_rb \rb - sync init - end - process $group_21 - assign \input_xer_so 1'0 - assign \input_xer_so \xer_so$20 - sync init - end - process $group_22 - assign \main_muxid 2'00 - assign \main_muxid \input_muxid$21 - sync init - end - process $group_23 - assign \main_logical_op__insn_type 7'0000000 - assign \main_logical_op__fn_unit 11'00000000000 - assign \main_logical_op__imm_data__data 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \main_logical_op__imm_data__ok 1'0 - assign \main_logical_op__rc__rc 1'0 - assign \main_logical_op__rc__ok 1'0 - assign \main_logical_op__oe__oe 1'0 - assign \main_logical_op__oe__ok 1'0 - assign \main_logical_op__invert_in 1'0 - assign \main_logical_op__zero_a 1'0 - assign \main_logical_op__input_carry 2'00 - assign \main_logical_op__invert_out 1'0 - assign \main_logical_op__write_cr0 1'0 - assign \main_logical_op__output_carry 1'0 - assign \main_logical_op__is_32bit 1'0 - assign \main_logical_op__is_signed 1'0 - assign \main_logical_op__data_len 4'0000 - assign \main_logical_op__insn 32'00000000000000000000000000000000 - assign { \main_logical_op__insn \main_logical_op__data_len \main_logical_op__is_signed \main_logical_op__is_32bit \main_logical_op__output_carry \main_logical_op__write_cr0 \main_logical_op__invert_out \main_logical_op__input_carry \main_logical_op__zero_a \main_logical_op__invert_in { \main_logical_op__oe__ok \main_logical_op__oe__oe } { \main_logical_op__rc__ok \main_logical_op__rc__rc } { \main_logical_op__imm_data__ok \main_logical_op__imm_data__data } \main_logical_op__fn_unit \main_logical_op__insn_type } { \input_logical_op__insn$39 \input_logical_op__data_len$38 \input_logical_op__is_signed$37 \input_logical_op__is_32bit$36 \input_logical_op__output_carry$35 \input_logical_op__write_cr0$34 \input_logical_op__invert_out$33 \input_logical_op__input_carry$32 \input_logical_op__zero_a$31 \input_logical_op__invert_in$30 { \input_logical_op__oe__ok$29 \input_logical_op__oe__oe$28 } { \input_logical_op__rc__ok$27 \input_logical_op__rc__rc$26 } { \input_logical_op__imm_data__ok$25 \input_logical_op__imm_data__data$24 } \input_logical_op__fn_unit$23 \input_logical_op__insn_type$22 } - sync init - end - process $group_41 - assign \main_ra 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \main_ra \input_ra$40 - sync init - end - process $group_42 - assign \main_rb 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \main_rb \input_rb$41 - sync init - end - process $group_43 - assign \main_xer_so 1'0 - assign \main_xer_so \input_xer_so$42 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:621" - wire width 1 \p_valid_i$63 - process $group_44 - assign \p_valid_i$63 1'0 - assign \p_valid_i$63 \p_valid_i - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:619" - wire width 1 \n_i_rdy_data - process $group_45 - assign \n_i_rdy_data 1'0 - assign \n_i_rdy_data \n_ready_i - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" - wire width 1 \p_valid_i_p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" - wire width 1 $64 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" - cell $and $65 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \p_valid_i$63 - connect \B \p_ready_o - connect \Y $64 - end - process $group_46 - assign \p_valid_i_p_ready_o 1'0 - assign \p_valid_i_p_ready_o $64 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \muxid$66 - process $group_47 - assign \muxid$66 2'00 - assign \muxid$66 \main_muxid$43 - sync init - end - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \logical_op__insn_type$67 - attribute \enum_base_type "Function" - attribute \enum_value_00000000000 "NONE" - attribute \enum_value_00000000010 "ALU" - attribute \enum_value_00000000100 "LDST" - attribute \enum_value_00000001000 "SHIFT_ROT" - attribute \enum_value_00000010000 "LOGICAL" - attribute \enum_value_00000100000 "BRANCH" - attribute \enum_value_00001000000 "CR" - attribute \enum_value_00010000000 "TRAP" - attribute \enum_value_00100000000 "MUL" - attribute \enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 \logical_op__fn_unit$68 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \logical_op__imm_data__data$69 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__imm_data__ok$70 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__rc__rc$71 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__rc__ok$72 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__oe__oe$73 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__oe__ok$74 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__invert_in$75 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__zero_a$76 - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \logical_op__input_carry$77 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__invert_out$78 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__write_cr0$79 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__output_carry$80 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__is_32bit$81 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__is_signed$82 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \logical_op__data_len$83 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \logical_op__insn$84 - process $group_48 - assign \logical_op__insn_type$67 7'0000000 - assign \logical_op__fn_unit$68 11'00000000000 - assign \logical_op__imm_data__data$69 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \logical_op__imm_data__ok$70 1'0 - assign \logical_op__rc__rc$71 1'0 - assign \logical_op__rc__ok$72 1'0 - assign \logical_op__oe__oe$73 1'0 - assign \logical_op__oe__ok$74 1'0 - assign \logical_op__invert_in$75 1'0 - assign \logical_op__zero_a$76 1'0 - assign \logical_op__input_carry$77 2'00 - assign \logical_op__invert_out$78 1'0 - assign \logical_op__write_cr0$79 1'0 - assign \logical_op__output_carry$80 1'0 - assign \logical_op__is_32bit$81 1'0 - assign \logical_op__is_signed$82 1'0 - assign \logical_op__data_len$83 4'0000 - assign \logical_op__insn$84 32'00000000000000000000000000000000 - assign { \logical_op__insn$84 \logical_op__data_len$83 \logical_op__is_signed$82 \logical_op__is_32bit$81 \logical_op__output_carry$80 \logical_op__write_cr0$79 \logical_op__invert_out$78 \logical_op__input_carry$77 \logical_op__zero_a$76 \logical_op__invert_in$75 { \logical_op__oe__ok$74 \logical_op__oe__oe$73 } { \logical_op__rc__ok$72 \logical_op__rc__rc$71 } { \logical_op__imm_data__ok$70 \logical_op__imm_data__data$69 } \logical_op__fn_unit$68 \logical_op__insn_type$67 } { \main_logical_op__insn$61 \main_logical_op__data_len$60 \main_logical_op__is_signed$59 \main_logical_op__is_32bit$58 \main_logical_op__output_carry$57 \main_logical_op__write_cr0$56 \main_logical_op__invert_out$55 \main_logical_op__input_carry$54 \main_logical_op__zero_a$53 \main_logical_op__invert_in$52 { \main_logical_op__oe__ok$51 \main_logical_op__oe__oe$50 } { \main_logical_op__rc__ok$49 \main_logical_op__rc__rc$48 } { \main_logical_op__imm_data__ok$47 \main_logical_op__imm_data__data$46 } \main_logical_op__fn_unit$45 \main_logical_op__insn_type$44 } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 \o$85 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \o_ok$86 - process $group_66 - assign \o$85 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \o_ok$86 1'0 - assign { \o_ok$86 \o$85 } { \main_o_ok \main_o } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 4 \cr_a$87 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \cr_a_ok$88 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 4 \cr_a$89 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \cr_a_ok$90 - process $group_68 - assign \cr_a$87 4'0000 - assign \cr_a_ok$88 1'0 - assign { \cr_a_ok$88 \cr_a$87 } { \cr_a_ok$90 \cr_a$89 } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \xer_so$91 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \xer_so_ok$92 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \xer_so_ok$93 - process $group_70 - assign \xer_so$91 1'0 - assign \xer_so_ok$92 1'0 - assign { \xer_so_ok$92 \xer_so$91 } { \xer_so_ok$93 \main_xer_so$62 } - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615" - wire width 1 \r_busy - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615" - wire width 1 \r_busy$next - process $group_72 - assign \r_busy$next \r_busy - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign \r_busy$next 1'1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign \r_busy$next 1'0 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \r_busy$next 1'0 - end - sync init - update \r_busy 1'0 - sync posedge \coresync_clk - update \r_busy \r_busy$next - end - process $group_73 - assign \muxid$next \muxid - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign \muxid$next \muxid$66 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign \muxid$next \muxid$66 - end - sync init - update \muxid 2'00 - sync posedge \coresync_clk - update \muxid \muxid$next - end - process $group_74 - assign \logical_op__insn_type$next \logical_op__insn_type - assign \logical_op__fn_unit$next \logical_op__fn_unit - assign \logical_op__imm_data__data$next \logical_op__imm_data__data - assign \logical_op__imm_data__ok$next \logical_op__imm_data__ok - assign \logical_op__rc__rc$next \logical_op__rc__rc - assign \logical_op__rc__ok$next \logical_op__rc__ok - assign \logical_op__oe__oe$next \logical_op__oe__oe - assign \logical_op__oe__ok$next \logical_op__oe__ok - assign \logical_op__invert_in$next \logical_op__invert_in - assign \logical_op__zero_a$next \logical_op__zero_a - assign \logical_op__input_carry$next \logical_op__input_carry - assign \logical_op__invert_out$next \logical_op__invert_out - assign \logical_op__write_cr0$next \logical_op__write_cr0 - assign \logical_op__output_carry$next \logical_op__output_carry - assign \logical_op__is_32bit$next \logical_op__is_32bit - assign \logical_op__is_signed$next \logical_op__is_signed - assign \logical_op__data_len$next \logical_op__data_len - assign \logical_op__insn$next \logical_op__insn - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign { \logical_op__insn$next \logical_op__data_len$next \logical_op__is_signed$next \logical_op__is_32bit$next \logical_op__output_carry$next \logical_op__write_cr0$next \logical_op__invert_out$next \logical_op__input_carry$next \logical_op__zero_a$next \logical_op__invert_in$next { \logical_op__oe__ok$next \logical_op__oe__oe$next } { \logical_op__rc__ok$next \logical_op__rc__rc$next } { \logical_op__imm_data__ok$next \logical_op__imm_data__data$next } \logical_op__fn_unit$next \logical_op__insn_type$next } { \logical_op__insn$84 \logical_op__data_len$83 \logical_op__is_signed$82 \logical_op__is_32bit$81 \logical_op__output_carry$80 \logical_op__write_cr0$79 \logical_op__invert_out$78 \logical_op__input_carry$77 \logical_op__zero_a$76 \logical_op__invert_in$75 { \logical_op__oe__ok$74 \logical_op__oe__oe$73 } { \logical_op__rc__ok$72 \logical_op__rc__rc$71 } { \logical_op__imm_data__ok$70 \logical_op__imm_data__data$69 } \logical_op__fn_unit$68 \logical_op__insn_type$67 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign { \logical_op__insn$next \logical_op__data_len$next \logical_op__is_signed$next \logical_op__is_32bit$next \logical_op__output_carry$next \logical_op__write_cr0$next \logical_op__invert_out$next \logical_op__input_carry$next \logical_op__zero_a$next \logical_op__invert_in$next { \logical_op__oe__ok$next \logical_op__oe__oe$next } { \logical_op__rc__ok$next \logical_op__rc__rc$next } { \logical_op__imm_data__ok$next \logical_op__imm_data__data$next } \logical_op__fn_unit$next \logical_op__insn_type$next } { \logical_op__insn$84 \logical_op__data_len$83 \logical_op__is_signed$82 \logical_op__is_32bit$81 \logical_op__output_carry$80 \logical_op__write_cr0$79 \logical_op__invert_out$78 \logical_op__input_carry$77 \logical_op__zero_a$76 \logical_op__invert_in$75 { \logical_op__oe__ok$74 \logical_op__oe__oe$73 } { \logical_op__rc__ok$72 \logical_op__rc__rc$71 } { \logical_op__imm_data__ok$70 \logical_op__imm_data__data$69 } \logical_op__fn_unit$68 \logical_op__insn_type$67 } - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \logical_op__imm_data__data$next 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \logical_op__imm_data__ok$next 1'0 - assign \logical_op__rc__rc$next 1'0 - assign \logical_op__rc__ok$next 1'0 - assign \logical_op__oe__oe$next 1'0 - assign \logical_op__oe__ok$next 1'0 - end - sync init - update \logical_op__insn_type 7'0000000 - update \logical_op__fn_unit 11'00000000000 - update \logical_op__imm_data__data 64'0000000000000000000000000000000000000000000000000000000000000000 - update \logical_op__imm_data__ok 1'0 - update \logical_op__rc__rc 1'0 - update \logical_op__rc__ok 1'0 - update \logical_op__oe__oe 1'0 - update \logical_op__oe__ok 1'0 - update \logical_op__invert_in 1'0 - update \logical_op__zero_a 1'0 - update \logical_op__input_carry 2'00 - update \logical_op__invert_out 1'0 - update \logical_op__write_cr0 1'0 - update \logical_op__output_carry 1'0 - update \logical_op__is_32bit 1'0 - update \logical_op__is_signed 1'0 - update \logical_op__data_len 4'0000 - update \logical_op__insn 32'00000000000000000000000000000000 - sync posedge \coresync_clk - update \logical_op__insn_type \logical_op__insn_type$next - update \logical_op__fn_unit \logical_op__fn_unit$next - update \logical_op__imm_data__data \logical_op__imm_data__data$next - update \logical_op__imm_data__ok \logical_op__imm_data__ok$next - update \logical_op__rc__rc \logical_op__rc__rc$next - update \logical_op__rc__ok \logical_op__rc__ok$next - update \logical_op__oe__oe \logical_op__oe__oe$next - update \logical_op__oe__ok \logical_op__oe__ok$next - update \logical_op__invert_in \logical_op__invert_in$next - update \logical_op__zero_a \logical_op__zero_a$next - update \logical_op__input_carry \logical_op__input_carry$next - update \logical_op__invert_out \logical_op__invert_out$next - update \logical_op__write_cr0 \logical_op__write_cr0$next - update \logical_op__output_carry \logical_op__output_carry$next - update \logical_op__is_32bit \logical_op__is_32bit$next - update \logical_op__is_signed \logical_op__is_signed$next - update \logical_op__data_len \logical_op__data_len$next - update \logical_op__insn \logical_op__insn$next - end - process $group_92 - assign \o$next \o - assign \o_ok$next \o_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign { \o_ok$next \o$next } { \o_ok$86 \o$85 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign { \o_ok$next \o$next } { \o_ok$86 \o$85 } - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \o_ok$next 1'0 - end - sync init - update \o 64'0000000000000000000000000000000000000000000000000000000000000000 - update \o_ok 1'0 - sync posedge \coresync_clk - update \o \o$next - update \o_ok \o_ok$next - end - process $group_94 - assign \cr_a$next \cr_a - assign \cr_a_ok$next \cr_a_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign { \cr_a_ok$next \cr_a$next } { \cr_a_ok$88 \cr_a$87 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign { \cr_a_ok$next \cr_a$next } { \cr_a_ok$88 \cr_a$87 } - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \cr_a_ok$next 1'0 - end - sync init - update \cr_a 4'0000 - update \cr_a_ok 1'0 - sync posedge \coresync_clk - update \cr_a \cr_a$next - update \cr_a_ok \cr_a_ok$next - end - process $group_96 - assign \xer_so$next \xer_so - assign \xer_so_ok$next \xer_so_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign { \xer_so_ok$next \xer_so$next } { \xer_so_ok$92 \xer_so$91 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign { \xer_so_ok$next \xer_so$next } { \xer_so_ok$92 \xer_so$91 } - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \xer_so_ok$next 1'0 - end - sync init - update \xer_so 1'0 - update \xer_so_ok 1'0 - sync posedge \coresync_clk - update \xer_so \xer_so$next - update \xer_so_ok \xer_so_ok$next - end - process $group_98 - assign \n_valid_o 1'0 - assign \n_valid_o \r_busy - sync init - end - process $group_99 - assign \p_ready_o 1'0 - assign \p_ready_o \n_i_rdy_data - sync init - end - connect \cr_a$89 4'0000 - connect \cr_a_ok$90 1'0 - connect \xer_so_ok$93 1'0 -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.logical0.alu_logical0.logical_pipe2.p" -module \p$49 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" - wire width 1 input 0 \p_valid_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" - wire width 1 input 1 \p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:158" - wire width 1 \trigger - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" - cell $and $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \p_valid_i - connect \B \p_ready_o - connect \Y $1 - end - process $group_0 - assign \trigger 1'0 - assign \trigger $1 - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.logical0.alu_logical0.logical_pipe2.n" -module \n$50 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" - wire width 1 input 0 \n_valid_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" - wire width 1 input 1 \n_ready_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:251" - wire width 1 \trigger - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" - cell $and $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \n_ready_i - connect \B \n_valid_o - connect \Y $1 - end - process $group_0 - assign \trigger 1'0 - assign \trigger $1 - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.logical0.alu_logical0.logical_pipe2.output" -module \output$51 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 input 0 \muxid - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 input 1 \logical_op__insn_type - attribute \enum_base_type "Function" - attribute \enum_value_00000000000 "NONE" - attribute \enum_value_00000000010 "ALU" - attribute \enum_value_00000000100 "LDST" - attribute \enum_value_00000001000 "SHIFT_ROT" - attribute \enum_value_00000010000 "LOGICAL" - attribute \enum_value_00000100000 "BRANCH" - attribute \enum_value_00001000000 "CR" - attribute \enum_value_00010000000 "TRAP" - attribute \enum_value_00100000000 "MUL" - attribute \enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 input 2 \logical_op__fn_unit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 input 3 \logical_op__imm_data__data - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 4 \logical_op__imm_data__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 5 \logical_op__rc__rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 6 \logical_op__rc__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 7 \logical_op__oe__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 8 \logical_op__oe__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 9 \logical_op__invert_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 10 \logical_op__zero_a - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 input 11 \logical_op__input_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 12 \logical_op__invert_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 13 \logical_op__write_cr0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 14 \logical_op__output_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 15 \logical_op__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 16 \logical_op__is_signed - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 input 17 \logical_op__data_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 input 18 \logical_op__insn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 input 19 \o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 input 20 \o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 4 input 21 \cr_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 input 22 \xer_so - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 output 23 \muxid$1 - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute 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\enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 output 24 \logical_op__insn_type$2 - attribute \enum_base_type "Function" - attribute \enum_value_00000000000 "NONE" - attribute \enum_value_00000000010 "ALU" - attribute \enum_value_00000000100 "LDST" - attribute \enum_value_00000001000 "SHIFT_ROT" - attribute \enum_value_00000010000 "LOGICAL" - attribute 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\logical_op__output_carry$15 \output_logical_op__output_carry$38 - connect \logical_op__is_32bit$16 \output_logical_op__is_32bit$39 - connect \logical_op__is_signed$17 \output_logical_op__is_signed$40 - connect \logical_op__data_len$18 \output_logical_op__data_len$41 - connect \logical_op__insn$19 \output_logical_op__insn$42 - connect \o$20 \output_o$43 - connect \o_ok$21 \output_o_ok$44 - connect \cr_a$22 \output_cr_a$45 - connect \cr_a_ok \output_cr_a_ok - end - process $group_0 - assign \output_muxid 2'00 - assign \output_muxid \muxid - sync init - end - process $group_1 - assign \output_logical_op__insn_type 7'0000000 - assign \output_logical_op__fn_unit 11'00000000000 - assign \output_logical_op__imm_data__data 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \output_logical_op__imm_data__ok 1'0 - assign \output_logical_op__rc__rc 1'0 - assign \output_logical_op__rc__ok 1'0 - assign \output_logical_op__oe__oe 1'0 - assign \output_logical_op__oe__ok 1'0 - assign \output_logical_op__invert_in 1'0 - assign \output_logical_op__zero_a 1'0 - assign \output_logical_op__input_carry 2'00 - assign \output_logical_op__invert_out 1'0 - assign \output_logical_op__write_cr0 1'0 - assign \output_logical_op__output_carry 1'0 - assign \output_logical_op__is_32bit 1'0 - assign \output_logical_op__is_signed 1'0 - assign \output_logical_op__data_len 4'0000 - assign \output_logical_op__insn 32'00000000000000000000000000000000 - assign { \output_logical_op__insn \output_logical_op__data_len \output_logical_op__is_signed \output_logical_op__is_32bit \output_logical_op__output_carry \output_logical_op__write_cr0 \output_logical_op__invert_out \output_logical_op__input_carry \output_logical_op__zero_a \output_logical_op__invert_in { \output_logical_op__oe__ok \output_logical_op__oe__oe } { \output_logical_op__rc__ok \output_logical_op__rc__rc } { \output_logical_op__imm_data__ok \output_logical_op__imm_data__data } \output_logical_op__fn_unit \output_logical_op__insn_type } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in { \logical_op__oe__ok \logical_op__oe__oe } { \logical_op__rc__ok \logical_op__rc__rc } { \logical_op__imm_data__ok \logical_op__imm_data__data } \logical_op__fn_unit \logical_op__insn_type } - sync init - end - process $group_19 - assign \output_o 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \output_o_ok 1'0 - assign { \output_o_ok \output_o } { \o_ok \o } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \cr_a_ok$46 - process $group_21 - assign \output_cr_a 4'0000 - assign \cr_a_ok$46 1'0 - assign { \cr_a_ok$46 \output_cr_a } { \cr_a_ok \cr_a } - sync init - end - attribute \src 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\enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \logical_op__insn_type$52 - attribute \enum_base_type "Function" - attribute \enum_value_00000000000 "NONE" - attribute \enum_value_00000000010 "ALU" - attribute \enum_value_00000000100 "LDST" - attribute \enum_value_00000001000 "SHIFT_ROT" - attribute \enum_value_00000010000 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\logical_op__oe__oe$58 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__oe__ok$59 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__invert_in$60 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__zero_a$61 - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \logical_op__input_carry$62 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__invert_out$63 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__write_cr0$64 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__output_carry$65 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__is_32bit$66 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__is_signed$67 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \logical_op__data_len$68 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \logical_op__insn$69 - process $group_29 - assign \logical_op__insn_type$52 7'0000000 - assign \logical_op__fn_unit$53 11'00000000000 - assign \logical_op__imm_data__data$54 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \logical_op__imm_data__ok$55 1'0 - assign \logical_op__rc__rc$56 1'0 - assign \logical_op__rc__ok$57 1'0 - assign \logical_op__oe__oe$58 1'0 - assign \logical_op__oe__ok$59 1'0 - assign \logical_op__invert_in$60 1'0 - assign \logical_op__zero_a$61 1'0 - assign \logical_op__input_carry$62 2'00 - assign \logical_op__invert_out$63 1'0 - assign \logical_op__write_cr0$64 1'0 - assign \logical_op__output_carry$65 1'0 - assign \logical_op__is_32bit$66 1'0 - assign \logical_op__is_signed$67 1'0 - assign \logical_op__data_len$68 4'0000 - assign \logical_op__insn$69 32'00000000000000000000000000000000 - assign { \logical_op__insn$69 \logical_op__data_len$68 \logical_op__is_signed$67 \logical_op__is_32bit$66 \logical_op__output_carry$65 \logical_op__write_cr0$64 \logical_op__invert_out$63 \logical_op__input_carry$62 \logical_op__zero_a$61 \logical_op__invert_in$60 { \logical_op__oe__ok$59 \logical_op__oe__oe$58 } { \logical_op__rc__ok$57 \logical_op__rc__rc$56 } { \logical_op__imm_data__ok$55 \logical_op__imm_data__data$54 } \logical_op__fn_unit$53 \logical_op__insn_type$52 } { \output_logical_op__insn$42 \output_logical_op__data_len$41 \output_logical_op__is_signed$40 \output_logical_op__is_32bit$39 \output_logical_op__output_carry$38 \output_logical_op__write_cr0$37 \output_logical_op__invert_out$36 \output_logical_op__input_carry$35 \output_logical_op__zero_a$34 \output_logical_op__invert_in$33 { \output_logical_op__oe__ok$32 \output_logical_op__oe__oe$31 } { \output_logical_op__rc__ok$30 \output_logical_op__rc__rc$29 } { \output_logical_op__imm_data__ok$28 \output_logical_op__imm_data__data$27 } \output_logical_op__fn_unit$26 \output_logical_op__insn_type$25 } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 \o$70 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \o_ok$71 - process $group_47 - assign \o$70 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \o_ok$71 1'0 - assign { \o_ok$71 \o$70 } { \output_o_ok$44 \output_o$43 } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 4 \cr_a$72 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \cr_a_ok$73 - process $group_49 - assign \cr_a$72 4'0000 - assign \cr_a_ok$73 1'0 - assign { \cr_a_ok$73 \cr_a$72 } { \output_cr_a_ok \output_cr_a$45 } - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615" - wire width 1 \r_busy - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615" - wire width 1 \r_busy$next - process $group_51 - assign \r_busy$next \r_busy - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign \r_busy$next 1'1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign \r_busy$next 1'0 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \r_busy$next 1'0 - end - sync init - update \r_busy 1'0 - sync posedge \coresync_clk - update \r_busy \r_busy$next - end - process $group_52 - assign \muxid$1$next \muxid$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign \muxid$1$next \muxid$51 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign \muxid$1$next \muxid$51 - end - sync init - update \muxid$1 2'00 - sync posedge \coresync_clk - update \muxid$1 \muxid$1$next - end - process $group_53 - assign \logical_op__insn_type$2$next \logical_op__insn_type$2 - assign \logical_op__fn_unit$3$next \logical_op__fn_unit$3 - assign \logical_op__imm_data__data$4$next \logical_op__imm_data__data$4 - assign \logical_op__imm_data__ok$5$next \logical_op__imm_data__ok$5 - assign \logical_op__rc__rc$6$next \logical_op__rc__rc$6 - assign \logical_op__rc__ok$7$next \logical_op__rc__ok$7 - assign \logical_op__oe__oe$8$next \logical_op__oe__oe$8 - assign \logical_op__oe__ok$9$next \logical_op__oe__ok$9 - assign \logical_op__invert_in$10$next \logical_op__invert_in$10 - assign \logical_op__zero_a$11$next \logical_op__zero_a$11 - assign \logical_op__input_carry$12$next \logical_op__input_carry$12 - assign \logical_op__invert_out$13$next \logical_op__invert_out$13 - assign \logical_op__write_cr0$14$next \logical_op__write_cr0$14 - assign \logical_op__output_carry$15$next \logical_op__output_carry$15 - assign \logical_op__is_32bit$16$next \logical_op__is_32bit$16 - assign \logical_op__is_signed$17$next \logical_op__is_signed$17 - assign \logical_op__data_len$18$next \logical_op__data_len$18 - assign \logical_op__insn$19$next \logical_op__insn$19 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign { \logical_op__insn$19$next \logical_op__data_len$18$next \logical_op__is_signed$17$next \logical_op__is_32bit$16$next \logical_op__output_carry$15$next \logical_op__write_cr0$14$next \logical_op__invert_out$13$next \logical_op__input_carry$12$next \logical_op__zero_a$11$next \logical_op__invert_in$10$next { \logical_op__oe__ok$9$next \logical_op__oe__oe$8$next } { \logical_op__rc__ok$7$next \logical_op__rc__rc$6$next } { \logical_op__imm_data__ok$5$next \logical_op__imm_data__data$4$next } \logical_op__fn_unit$3$next \logical_op__insn_type$2$next } { \logical_op__insn$69 \logical_op__data_len$68 \logical_op__is_signed$67 \logical_op__is_32bit$66 \logical_op__output_carry$65 \logical_op__write_cr0$64 \logical_op__invert_out$63 \logical_op__input_carry$62 \logical_op__zero_a$61 \logical_op__invert_in$60 { \logical_op__oe__ok$59 \logical_op__oe__oe$58 } { \logical_op__rc__ok$57 \logical_op__rc__rc$56 } { \logical_op__imm_data__ok$55 \logical_op__imm_data__data$54 } \logical_op__fn_unit$53 \logical_op__insn_type$52 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign { \logical_op__insn$19$next \logical_op__data_len$18$next \logical_op__is_signed$17$next \logical_op__is_32bit$16$next \logical_op__output_carry$15$next \logical_op__write_cr0$14$next \logical_op__invert_out$13$next \logical_op__input_carry$12$next \logical_op__zero_a$11$next \logical_op__invert_in$10$next { \logical_op__oe__ok$9$next \logical_op__oe__oe$8$next } { \logical_op__rc__ok$7$next \logical_op__rc__rc$6$next } { \logical_op__imm_data__ok$5$next \logical_op__imm_data__data$4$next } \logical_op__fn_unit$3$next \logical_op__insn_type$2$next } { \logical_op__insn$69 \logical_op__data_len$68 \logical_op__is_signed$67 \logical_op__is_32bit$66 \logical_op__output_carry$65 \logical_op__write_cr0$64 \logical_op__invert_out$63 \logical_op__input_carry$62 \logical_op__zero_a$61 \logical_op__invert_in$60 { \logical_op__oe__ok$59 \logical_op__oe__oe$58 } { \logical_op__rc__ok$57 \logical_op__rc__rc$56 } { \logical_op__imm_data__ok$55 \logical_op__imm_data__data$54 } \logical_op__fn_unit$53 \logical_op__insn_type$52 } - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \logical_op__imm_data__data$4$next 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \logical_op__imm_data__ok$5$next 1'0 - assign \logical_op__rc__rc$6$next 1'0 - assign \logical_op__rc__ok$7$next 1'0 - assign \logical_op__oe__oe$8$next 1'0 - assign \logical_op__oe__ok$9$next 1'0 - end - sync init - update \logical_op__insn_type$2 7'0000000 - update \logical_op__fn_unit$3 11'00000000000 - update \logical_op__imm_data__data$4 64'0000000000000000000000000000000000000000000000000000000000000000 - update \logical_op__imm_data__ok$5 1'0 - update \logical_op__rc__rc$6 1'0 - update \logical_op__rc__ok$7 1'0 - update \logical_op__oe__oe$8 1'0 - update \logical_op__oe__ok$9 1'0 - update \logical_op__invert_in$10 1'0 - update \logical_op__zero_a$11 1'0 - update \logical_op__input_carry$12 2'00 - update \logical_op__invert_out$13 1'0 - update \logical_op__write_cr0$14 1'0 - update \logical_op__output_carry$15 1'0 - update \logical_op__is_32bit$16 1'0 - update \logical_op__is_signed$17 1'0 - update \logical_op__data_len$18 4'0000 - update \logical_op__insn$19 32'00000000000000000000000000000000 - sync posedge \coresync_clk - update \logical_op__insn_type$2 \logical_op__insn_type$2$next - update \logical_op__fn_unit$3 \logical_op__fn_unit$3$next - update \logical_op__imm_data__data$4 \logical_op__imm_data__data$4$next - update \logical_op__imm_data__ok$5 \logical_op__imm_data__ok$5$next - update \logical_op__rc__rc$6 \logical_op__rc__rc$6$next - update \logical_op__rc__ok$7 \logical_op__rc__ok$7$next - update \logical_op__oe__oe$8 \logical_op__oe__oe$8$next - update \logical_op__oe__ok$9 \logical_op__oe__ok$9$next - update \logical_op__invert_in$10 \logical_op__invert_in$10$next - update \logical_op__zero_a$11 \logical_op__zero_a$11$next - update \logical_op__input_carry$12 \logical_op__input_carry$12$next - update \logical_op__invert_out$13 \logical_op__invert_out$13$next - update \logical_op__write_cr0$14 \logical_op__write_cr0$14$next - update \logical_op__output_carry$15 \logical_op__output_carry$15$next - update \logical_op__is_32bit$16 \logical_op__is_32bit$16$next - update \logical_op__is_signed$17 \logical_op__is_signed$17$next - update \logical_op__data_len$18 \logical_op__data_len$18$next - update \logical_op__insn$19 \logical_op__insn$19$next - end - process $group_71 - assign \o$20$next \o$20 - assign \o_ok$21$next \o_ok$21 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign { \o_ok$21$next \o$20$next } { \o_ok$71 \o$70 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign { \o_ok$21$next \o$20$next } { \o_ok$71 \o$70 } - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \o_ok$21$next 1'0 - end - sync init - update \o$20 64'0000000000000000000000000000000000000000000000000000000000000000 - update \o_ok$21 1'0 - sync posedge \coresync_clk - update \o$20 \o$20$next - update \o_ok$21 \o_ok$21$next - end - process $group_73 - assign \cr_a$22$next \cr_a$22 - assign \cr_a_ok$23$next \cr_a_ok$23 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign { \cr_a_ok$23$next \cr_a$22$next } { \cr_a_ok$73 \cr_a$72 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign { \cr_a_ok$23$next \cr_a$22$next } { \cr_a_ok$73 \cr_a$72 } - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \cr_a_ok$23$next 1'0 - end - sync init - update \cr_a$22 4'0000 - update \cr_a_ok$23 1'0 - sync posedge \coresync_clk - update \cr_a$22 \cr_a$22$next - update \cr_a_ok$23 \cr_a_ok$23$next - end - process $group_75 - assign \n_valid_o 1'0 - assign \n_valid_o \r_busy - sync init - end - process $group_76 - assign \p_ready_o 1'0 - assign \p_ready_o \n_i_rdy_data - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.logical0.alu_logical0" -module \alu_logical0 - attribute \src "simple/issuer.py:141" - wire width 1 input 0 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 1 \o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 2 \cr_a_ok - attribute \src "simple/issuer.py:141" - wire width 1 input 3 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" - wire width 1 output 4 \n_valid_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" - wire width 1 input 5 \n_ready_i - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 input 6 \logical_op__insn_type - attribute \enum_base_type "Function" - attribute \enum_value_00000000000 "NONE" - attribute \enum_value_00000000010 "ALU" - attribute \enum_value_00000000100 "LDST" - attribute \enum_value_00000001000 "SHIFT_ROT" - attribute \enum_value_00000010000 "LOGICAL" - attribute \enum_value_00000100000 "BRANCH" - attribute \enum_value_00001000000 "CR" - attribute \enum_value_00010000000 "TRAP" - attribute \enum_value_00100000000 "MUL" - attribute \enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 input 7 \logical_op__fn_unit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 input 8 \logical_op__imm_data__data - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 9 \logical_op__imm_data__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 10 \logical_op__rc__rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 11 \logical_op__rc__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 12 \logical_op__oe__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 13 \logical_op__oe__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 14 \logical_op__invert_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 15 \logical_op__zero_a - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 input 16 \logical_op__input_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 17 \logical_op__invert_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 18 \logical_op__write_cr0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 19 \logical_op__output_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 20 \logical_op__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 21 \logical_op__is_signed - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 input 22 \logical_op__data_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 input 23 \logical_op__insn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 output 24 \o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 4 output 25 \cr_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 26 \ra - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 27 \rb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 1 input 28 \xer_so - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" - wire width 1 input 29 \p_valid_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" - wire width 1 output 30 \p_ready_o - cell \p$43 \p - connect \p_valid_i \p_valid_i - connect \p_ready_o \p_ready_o - end - cell \n$44 \n - connect \n_valid_o \n_valid_o - connect \n_ready_i \n_ready_i - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" - wire width 1 \logical_pipe1_n_valid_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" - wire width 1 \logical_pipe1_n_ready_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \logical_pipe1_muxid - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute 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\logical_op__imm_data__ok$5 \logical_pipe1_logical_op__imm_data__ok$5 - connect \logical_op__rc__rc$6 \logical_pipe1_logical_op__rc__rc$6 - connect \logical_op__rc__ok$7 \logical_pipe1_logical_op__rc__ok$7 - connect \logical_op__oe__oe$8 \logical_pipe1_logical_op__oe__oe$8 - connect \logical_op__oe__ok$9 \logical_pipe1_logical_op__oe__ok$9 - connect \logical_op__invert_in$10 \logical_pipe1_logical_op__invert_in$10 - connect \logical_op__zero_a$11 \logical_pipe1_logical_op__zero_a$11 - connect \logical_op__input_carry$12 \logical_pipe1_logical_op__input_carry$12 - connect \logical_op__invert_out$13 \logical_pipe1_logical_op__invert_out$13 - connect \logical_op__write_cr0$14 \logical_pipe1_logical_op__write_cr0$14 - connect \logical_op__output_carry$15 \logical_pipe1_logical_op__output_carry$15 - connect \logical_op__is_32bit$16 \logical_pipe1_logical_op__is_32bit$16 - connect \logical_op__is_signed$17 \logical_pipe1_logical_op__is_signed$17 - connect \logical_op__data_len$18 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\enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \logical_pipe2_logical_op__insn_type - attribute \enum_base_type "Function" - attribute \enum_value_00000000000 "NONE" - attribute \enum_value_00000000010 "ALU" - attribute \enum_value_00000000100 "LDST" - attribute \enum_value_00000001000 "SHIFT_ROT" - attribute \enum_value_00000010000 "LOGICAL" - attribute \enum_value_00000100000 "BRANCH" - attribute \enum_value_00001000000 "CR" - attribute \enum_value_00010000000 "TRAP" - attribute \enum_value_00100000000 "MUL" - attribute \enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 \logical_pipe2_logical_op__fn_unit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \logical_pipe2_logical_op__imm_data__data - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_pipe2_logical_op__imm_data__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_pipe2_logical_op__rc__rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_pipe2_logical_op__rc__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_pipe2_logical_op__oe__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_pipe2_logical_op__oe__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_pipe2_logical_op__invert_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_pipe2_logical_op__zero_a - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \logical_pipe2_logical_op__input_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_pipe2_logical_op__invert_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_pipe2_logical_op__write_cr0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_pipe2_logical_op__output_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_pipe2_logical_op__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_pipe2_logical_op__is_signed - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \logical_pipe2_logical_op__data_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \logical_pipe2_logical_op__insn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 \logical_pipe2_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \logical_pipe2_o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 4 \logical_pipe2_cr_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \logical_pipe2_cr_a_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \logical_pipe2_xer_so - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \logical_pipe2_xer_so_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" - wire width 1 \logical_pipe2_n_valid_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" - wire width 1 \logical_pipe2_n_ready_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \logical_pipe2_muxid$21 - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \logical_pipe2_logical_op__insn_type$22 - attribute \enum_base_type "Function" - attribute \enum_value_00000000000 "NONE" - attribute \enum_value_00000000010 "ALU" - attribute \enum_value_00000000100 "LDST" - attribute \enum_value_00000001000 "SHIFT_ROT" - attribute \enum_value_00000010000 "LOGICAL" - attribute \enum_value_00000100000 "BRANCH" - attribute \enum_value_00001000000 "CR" - attribute \enum_value_00010000000 "TRAP" - attribute \enum_value_00100000000 "MUL" - attribute \enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 \logical_pipe2_logical_op__fn_unit$23 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \logical_pipe2_logical_op__imm_data__data$24 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_pipe2_logical_op__imm_data__ok$25 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_pipe2_logical_op__rc__rc$26 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_pipe2_logical_op__rc__ok$27 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_pipe2_logical_op__oe__oe$28 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_pipe2_logical_op__oe__ok$29 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_pipe2_logical_op__invert_in$30 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_pipe2_logical_op__zero_a$31 - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \logical_pipe2_logical_op__input_carry$32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_pipe2_logical_op__invert_out$33 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_pipe2_logical_op__write_cr0$34 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_pipe2_logical_op__output_carry$35 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_pipe2_logical_op__is_32bit$36 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_pipe2_logical_op__is_signed$37 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \logical_pipe2_logical_op__data_len$38 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \logical_pipe2_logical_op__insn$39 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 \logical_pipe2_o$40 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \logical_pipe2_o_ok$41 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 4 \logical_pipe2_cr_a$42 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \logical_pipe2_cr_a_ok$43 - cell \logical_pipe2 \logical_pipe2 - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \p_valid_i \logical_pipe2_p_valid_i - connect \p_ready_o \logical_pipe2_p_ready_o - connect \muxid \logical_pipe2_muxid - connect \logical_op__insn_type \logical_pipe2_logical_op__insn_type - connect \logical_op__fn_unit \logical_pipe2_logical_op__fn_unit - connect \logical_op__imm_data__data \logical_pipe2_logical_op__imm_data__data - connect \logical_op__imm_data__ok \logical_pipe2_logical_op__imm_data__ok - connect \logical_op__rc__rc \logical_pipe2_logical_op__rc__rc - connect \logical_op__rc__ok \logical_pipe2_logical_op__rc__ok - connect \logical_op__oe__oe \logical_pipe2_logical_op__oe__oe - connect \logical_op__oe__ok \logical_pipe2_logical_op__oe__ok - connect \logical_op__invert_in \logical_pipe2_logical_op__invert_in - connect \logical_op__zero_a \logical_pipe2_logical_op__zero_a - connect \logical_op__input_carry \logical_pipe2_logical_op__input_carry - connect \logical_op__invert_out \logical_pipe2_logical_op__invert_out - connect \logical_op__write_cr0 \logical_pipe2_logical_op__write_cr0 - connect \logical_op__output_carry \logical_pipe2_logical_op__output_carry - connect \logical_op__is_32bit \logical_pipe2_logical_op__is_32bit - connect \logical_op__is_signed \logical_pipe2_logical_op__is_signed - connect \logical_op__data_len \logical_pipe2_logical_op__data_len - connect \logical_op__insn \logical_pipe2_logical_op__insn - connect \o \logical_pipe2_o - connect \o_ok \logical_pipe2_o_ok - connect \cr_a \logical_pipe2_cr_a - connect \cr_a_ok \logical_pipe2_cr_a_ok - connect \xer_so \logical_pipe2_xer_so - connect \xer_so_ok \logical_pipe2_xer_so_ok - connect \n_valid_o \logical_pipe2_n_valid_o - connect \n_ready_i \logical_pipe2_n_ready_i - connect \muxid$1 \logical_pipe2_muxid$21 - connect \logical_op__insn_type$2 \logical_pipe2_logical_op__insn_type$22 - connect \logical_op__fn_unit$3 \logical_pipe2_logical_op__fn_unit$23 - connect \logical_op__imm_data__data$4 \logical_pipe2_logical_op__imm_data__data$24 - connect \logical_op__imm_data__ok$5 \logical_pipe2_logical_op__imm_data__ok$25 - connect \logical_op__rc__rc$6 \logical_pipe2_logical_op__rc__rc$26 - connect \logical_op__rc__ok$7 \logical_pipe2_logical_op__rc__ok$27 - connect \logical_op__oe__oe$8 \logical_pipe2_logical_op__oe__oe$28 - connect \logical_op__oe__ok$9 \logical_pipe2_logical_op__oe__ok$29 - connect \logical_op__invert_in$10 \logical_pipe2_logical_op__invert_in$30 - connect \logical_op__zero_a$11 \logical_pipe2_logical_op__zero_a$31 - connect \logical_op__input_carry$12 \logical_pipe2_logical_op__input_carry$32 - connect \logical_op__invert_out$13 \logical_pipe2_logical_op__invert_out$33 - connect \logical_op__write_cr0$14 \logical_pipe2_logical_op__write_cr0$34 - connect \logical_op__output_carry$15 \logical_pipe2_logical_op__output_carry$35 - connect \logical_op__is_32bit$16 \logical_pipe2_logical_op__is_32bit$36 - connect \logical_op__is_signed$17 \logical_pipe2_logical_op__is_signed$37 - connect \logical_op__data_len$18 \logical_pipe2_logical_op__data_len$38 - connect \logical_op__insn$19 \logical_pipe2_logical_op__insn$39 - connect \o$20 \logical_pipe2_o$40 - connect \o_ok$21 \logical_pipe2_o_ok$41 - connect \cr_a$22 \logical_pipe2_cr_a$42 - connect \cr_a_ok$23 \logical_pipe2_cr_a_ok$43 - end - process $group_0 - assign \logical_pipe2_p_valid_i 1'0 - assign \logical_pipe2_p_valid_i \logical_pipe1_n_valid_o - sync init - end - process $group_1 - assign \logical_pipe1_n_ready_i 1'0 - assign \logical_pipe1_n_ready_i \logical_pipe2_p_ready_o - sync init - end - process $group_2 - assign \logical_pipe2_muxid 2'00 - assign \logical_pipe2_muxid \logical_pipe1_muxid - sync init - end - process $group_3 - assign \logical_pipe2_logical_op__insn_type 7'0000000 - assign \logical_pipe2_logical_op__fn_unit 11'00000000000 - assign \logical_pipe2_logical_op__imm_data__data 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \logical_pipe2_logical_op__imm_data__ok 1'0 - assign \logical_pipe2_logical_op__rc__rc 1'0 - assign \logical_pipe2_logical_op__rc__ok 1'0 - assign \logical_pipe2_logical_op__oe__oe 1'0 - assign \logical_pipe2_logical_op__oe__ok 1'0 - assign \logical_pipe2_logical_op__invert_in 1'0 - assign \logical_pipe2_logical_op__zero_a 1'0 - assign \logical_pipe2_logical_op__input_carry 2'00 - assign \logical_pipe2_logical_op__invert_out 1'0 - assign \logical_pipe2_logical_op__write_cr0 1'0 - assign \logical_pipe2_logical_op__output_carry 1'0 - assign \logical_pipe2_logical_op__is_32bit 1'0 - assign \logical_pipe2_logical_op__is_signed 1'0 - assign \logical_pipe2_logical_op__data_len 4'0000 - assign \logical_pipe2_logical_op__insn 32'00000000000000000000000000000000 - assign { \logical_pipe2_logical_op__insn \logical_pipe2_logical_op__data_len \logical_pipe2_logical_op__is_signed \logical_pipe2_logical_op__is_32bit \logical_pipe2_logical_op__output_carry \logical_pipe2_logical_op__write_cr0 \logical_pipe2_logical_op__invert_out \logical_pipe2_logical_op__input_carry \logical_pipe2_logical_op__zero_a \logical_pipe2_logical_op__invert_in { \logical_pipe2_logical_op__oe__ok \logical_pipe2_logical_op__oe__oe } { \logical_pipe2_logical_op__rc__ok \logical_pipe2_logical_op__rc__rc } { \logical_pipe2_logical_op__imm_data__ok \logical_pipe2_logical_op__imm_data__data } \logical_pipe2_logical_op__fn_unit \logical_pipe2_logical_op__insn_type } { \logical_pipe1_logical_op__insn \logical_pipe1_logical_op__data_len \logical_pipe1_logical_op__is_signed \logical_pipe1_logical_op__is_32bit \logical_pipe1_logical_op__output_carry \logical_pipe1_logical_op__write_cr0 \logical_pipe1_logical_op__invert_out \logical_pipe1_logical_op__input_carry \logical_pipe1_logical_op__zero_a \logical_pipe1_logical_op__invert_in { \logical_pipe1_logical_op__oe__ok \logical_pipe1_logical_op__oe__oe } { \logical_pipe1_logical_op__rc__ok \logical_pipe1_logical_op__rc__rc } { \logical_pipe1_logical_op__imm_data__ok \logical_pipe1_logical_op__imm_data__data } \logical_pipe1_logical_op__fn_unit \logical_pipe1_logical_op__insn_type } - sync init - end - process $group_21 - assign \logical_pipe2_o 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \logical_pipe2_o_ok 1'0 - assign { \logical_pipe2_o_ok \logical_pipe2_o } { \logical_pipe1_o_ok \logical_pipe1_o } - sync init - end - process $group_23 - assign \logical_pipe2_cr_a 4'0000 - assign \logical_pipe2_cr_a_ok 1'0 - assign { \logical_pipe2_cr_a_ok \logical_pipe2_cr_a } { \logical_pipe1_cr_a_ok \logical_pipe1_cr_a } - sync init - end - process $group_25 - assign \logical_pipe2_xer_so 1'0 - assign \logical_pipe2_xer_so_ok 1'0 - assign { \logical_pipe2_xer_so_ok \logical_pipe2_xer_so } { \logical_pipe1_xer_so_ok \logical_pipe1_xer_so } - sync init - end - process $group_27 - assign \logical_pipe1_p_valid_i 1'0 - assign \logical_pipe1_p_valid_i \p_valid_i - sync init - end - process $group_28 - assign \p_ready_o 1'0 - assign \p_ready_o \logical_pipe1_p_ready_o - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \muxid - process $group_29 - assign \logical_pipe1_muxid$1 2'00 - assign \logical_pipe1_muxid$1 \muxid - sync init - end - process $group_30 - assign \logical_pipe1_logical_op__insn_type$2 7'0000000 - assign \logical_pipe1_logical_op__fn_unit$3 11'00000000000 - assign \logical_pipe1_logical_op__imm_data__data$4 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \logical_pipe1_logical_op__imm_data__ok$5 1'0 - assign \logical_pipe1_logical_op__rc__rc$6 1'0 - assign \logical_pipe1_logical_op__rc__ok$7 1'0 - assign \logical_pipe1_logical_op__oe__oe$8 1'0 - assign \logical_pipe1_logical_op__oe__ok$9 1'0 - assign \logical_pipe1_logical_op__invert_in$10 1'0 - assign \logical_pipe1_logical_op__zero_a$11 1'0 - assign \logical_pipe1_logical_op__input_carry$12 2'00 - assign \logical_pipe1_logical_op__invert_out$13 1'0 - assign \logical_pipe1_logical_op__write_cr0$14 1'0 - assign \logical_pipe1_logical_op__output_carry$15 1'0 - assign \logical_pipe1_logical_op__is_32bit$16 1'0 - assign \logical_pipe1_logical_op__is_signed$17 1'0 - assign \logical_pipe1_logical_op__data_len$18 4'0000 - assign \logical_pipe1_logical_op__insn$19 32'00000000000000000000000000000000 - assign { \logical_pipe1_logical_op__insn$19 \logical_pipe1_logical_op__data_len$18 \logical_pipe1_logical_op__is_signed$17 \logical_pipe1_logical_op__is_32bit$16 \logical_pipe1_logical_op__output_carry$15 \logical_pipe1_logical_op__write_cr0$14 \logical_pipe1_logical_op__invert_out$13 \logical_pipe1_logical_op__input_carry$12 \logical_pipe1_logical_op__zero_a$11 \logical_pipe1_logical_op__invert_in$10 { \logical_pipe1_logical_op__oe__ok$9 \logical_pipe1_logical_op__oe__oe$8 } { \logical_pipe1_logical_op__rc__ok$7 \logical_pipe1_logical_op__rc__rc$6 } { \logical_pipe1_logical_op__imm_data__ok$5 \logical_pipe1_logical_op__imm_data__data$4 } \logical_pipe1_logical_op__fn_unit$3 \logical_pipe1_logical_op__insn_type$2 } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in { \logical_op__oe__ok \logical_op__oe__oe } { \logical_op__rc__ok \logical_op__rc__rc } { \logical_op__imm_data__ok \logical_op__imm_data__data } \logical_op__fn_unit \logical_op__insn_type } - sync init - end - process $group_48 - assign \logical_pipe1_ra 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \logical_pipe1_ra \ra - sync init - end - process $group_49 - assign \logical_pipe1_rb 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \logical_pipe1_rb \rb - sync init - end - process $group_50 - assign \logical_pipe1_xer_so$20 1'0 - assign \logical_pipe1_xer_so$20 \xer_so - sync init - end - process $group_51 - assign \n_valid_o 1'0 - assign \n_valid_o \logical_pipe2_n_valid_o - sync init - end - process $group_52 - assign \logical_pipe2_n_ready_i 1'0 - assign \logical_pipe2_n_ready_i \n_ready_i - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \muxid$44 - process $group_53 - assign \muxid$44 2'00 - assign \muxid$44 \logical_pipe2_muxid$21 - sync init - end - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \logical_op__insn_type$45 - attribute \enum_base_type "Function" - attribute \enum_value_00000000000 "NONE" - attribute \enum_value_00000000010 "ALU" - attribute \enum_value_00000000100 "LDST" - attribute \enum_value_00000001000 "SHIFT_ROT" - attribute \enum_value_00000010000 "LOGICAL" - attribute \enum_value_00000100000 "BRANCH" - attribute \enum_value_00001000000 "CR" - attribute \enum_value_00010000000 "TRAP" - attribute \enum_value_00100000000 "MUL" - attribute \enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 \logical_op__fn_unit$46 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \logical_op__imm_data__data$47 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__imm_data__ok$48 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__rc__rc$49 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__rc__ok$50 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__oe__oe$51 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__oe__ok$52 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__invert_in$53 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__zero_a$54 - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \logical_op__input_carry$55 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__invert_out$56 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__write_cr0$57 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__output_carry$58 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__is_32bit$59 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__is_signed$60 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \logical_op__data_len$61 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \logical_op__insn$62 - process $group_54 - assign \logical_op__insn_type$45 7'0000000 - assign \logical_op__fn_unit$46 11'00000000000 - assign \logical_op__imm_data__data$47 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \logical_op__imm_data__ok$48 1'0 - assign \logical_op__rc__rc$49 1'0 - assign \logical_op__rc__ok$50 1'0 - assign \logical_op__oe__oe$51 1'0 - assign \logical_op__oe__ok$52 1'0 - assign \logical_op__invert_in$53 1'0 - assign \logical_op__zero_a$54 1'0 - assign \logical_op__input_carry$55 2'00 - assign \logical_op__invert_out$56 1'0 - assign \logical_op__write_cr0$57 1'0 - assign \logical_op__output_carry$58 1'0 - assign \logical_op__is_32bit$59 1'0 - assign \logical_op__is_signed$60 1'0 - assign \logical_op__data_len$61 4'0000 - assign \logical_op__insn$62 32'00000000000000000000000000000000 - assign { \logical_op__insn$62 \logical_op__data_len$61 \logical_op__is_signed$60 \logical_op__is_32bit$59 \logical_op__output_carry$58 \logical_op__write_cr0$57 \logical_op__invert_out$56 \logical_op__input_carry$55 \logical_op__zero_a$54 \logical_op__invert_in$53 { \logical_op__oe__ok$52 \logical_op__oe__oe$51 } { \logical_op__rc__ok$50 \logical_op__rc__rc$49 } { \logical_op__imm_data__ok$48 \logical_op__imm_data__data$47 } \logical_op__fn_unit$46 \logical_op__insn_type$45 } { \logical_pipe2_logical_op__insn$39 \logical_pipe2_logical_op__data_len$38 \logical_pipe2_logical_op__is_signed$37 \logical_pipe2_logical_op__is_32bit$36 \logical_pipe2_logical_op__output_carry$35 \logical_pipe2_logical_op__write_cr0$34 \logical_pipe2_logical_op__invert_out$33 \logical_pipe2_logical_op__input_carry$32 \logical_pipe2_logical_op__zero_a$31 \logical_pipe2_logical_op__invert_in$30 { \logical_pipe2_logical_op__oe__ok$29 \logical_pipe2_logical_op__oe__oe$28 } { \logical_pipe2_logical_op__rc__ok$27 \logical_pipe2_logical_op__rc__rc$26 } { \logical_pipe2_logical_op__imm_data__ok$25 \logical_pipe2_logical_op__imm_data__data$24 } \logical_pipe2_logical_op__fn_unit$23 \logical_pipe2_logical_op__insn_type$22 } - sync init - end - process $group_72 - assign \o 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \o_ok 1'0 - assign { \o_ok \o } { \logical_pipe2_o_ok$41 \logical_pipe2_o$40 } - sync init - end - process $group_74 - assign \cr_a 4'0000 - assign \cr_a_ok 1'0 - assign { \cr_a_ok \cr_a } { \logical_pipe2_cr_a_ok$43 \logical_pipe2_cr_a$42 } - sync init - end - connect \muxid 2'00 -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.logical0.src_l" -module \src_l$52 - attribute \src "simple/issuer.py:141" - wire width 1 input 0 \coresync_clk - attribute \src "simple/issuer.py:141" - wire width 1 input 1 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 3 input 2 \s_src - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 3 input 3 \r_src - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire width 3 output 4 \q_src - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire width 3 \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire width 3 \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 3 $1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A \r_src - connect \Y $1 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 3 $3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $4 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A \q_int - connect \B $1 - connect \Y $3 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 3 $5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $6 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A $3 - connect \B \s_src - connect \Y $5 - end - process $group_0 - assign \q_int$next \q_int - assign \q_int$next $5 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \q_int$next 3'000 - end - sync init - update \q_int 3'000 - sync posedge \coresync_clk - update \q_int \q_int$next - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 3 $7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $8 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A \r_src - connect \Y $7 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 3 $9 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $10 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A \q_int - connect \B $7 - connect \Y $9 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 3 $11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $12 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A $9 - connect \B \s_src - connect \Y $11 - end - process $group_1 - assign \q_src 3'000 - assign \q_src $11 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" - wire width 3 \qn_src - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - wire width 3 $13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $14 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A \q_src - connect \Y $13 - end - process $group_2 - assign \qn_src 3'000 - assign \qn_src $13 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" - wire width 3 \qlq_src - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - wire width 3 $15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $16 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A \q_src - connect \B \q_int - connect \Y $15 - end - process $group_3 - assign \qlq_src 3'000 - assign \qlq_src $15 - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.logical0.opc_l" -module \opc_l$53 - attribute \src "simple/issuer.py:141" - wire width 1 input 0 \coresync_clk - attribute \src "simple/issuer.py:141" - wire width 1 input 1 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 1 input 2 \s_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 1 input 3 \r_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire width 1 output 4 \q_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire width 1 \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire width 1 \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_opc - connect \Y $1 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 1 $3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $4 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B $1 - connect \Y $3 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 1 $5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $6 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $3 - connect \B \s_opc - connect \Y $5 - end - process $group_0 - assign \q_int$next \q_int - assign \q_int$next $5 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \q_int$next 1'0 - end - sync init - update \q_int 1'0 - sync posedge \coresync_clk - update \q_int \q_int$next - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 1 $7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $8 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_opc - connect \Y $7 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 1 $9 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $10 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B $7 - connect \Y $9 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 1 $11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $12 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $9 - connect \B \s_opc - connect \Y $11 - end - process $group_1 - assign \q_opc 1'0 - assign \q_opc $11 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" - wire width 1 \qn_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - wire width 1 $13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $14 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_opc - connect \Y $13 - end - process $group_2 - assign \qn_opc 1'0 - assign \qn_opc $13 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" - wire width 1 \qlq_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - wire width 1 $15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $16 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_opc - connect \B \q_int - connect \Y $15 - end - process $group_3 - assign \qlq_opc 1'0 - assign \qlq_opc $15 - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.logical0.req_l" -module \req_l$54 - attribute \src "simple/issuer.py:141" - wire width 1 input 0 \coresync_clk - attribute \src "simple/issuer.py:141" - wire width 1 input 1 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire width 2 output 2 \q_req - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 2 input 3 \s_req - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 2 input 4 \r_req - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire width 2 \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire width 2 \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 2 $1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \Y_WIDTH 2 - connect \A \r_req - connect \Y $1 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 2 $3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $4 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 2 - connect \A \q_int - connect \B $1 - connect \Y $3 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 2 $5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $6 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 2 - connect \A $3 - connect \B \s_req - connect \Y $5 - end - process $group_0 - assign \q_int$next \q_int - assign \q_int$next $5 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \q_int$next 2'00 - end - sync init - update \q_int 2'00 - sync posedge \coresync_clk - update \q_int \q_int$next - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 2 $7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $8 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \Y_WIDTH 2 - connect \A \r_req - connect \Y $7 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 2 $9 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $10 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 2 - connect \A \q_int - connect \B $7 - connect \Y $9 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 2 $11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $12 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 2 - connect \A $9 - connect \B \s_req - connect \Y $11 - end - process $group_1 - assign \q_req 2'00 - assign \q_req $11 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" - wire width 2 \qn_req - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - wire width 2 $13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $14 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \Y_WIDTH 2 - connect \A \q_req - connect \Y $13 - end - process $group_2 - assign \qn_req 2'00 - assign \qn_req $13 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" - wire width 2 \qlq_req - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - wire width 2 $15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $16 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 2 - connect \A \q_req - connect \B \q_int - connect \Y $15 - end - process $group_3 - assign \qlq_req 2'00 - assign \qlq_req $15 - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.logical0.rst_l" -module \rst_l$55 - attribute \src "simple/issuer.py:141" - wire width 1 input 0 \coresync_clk - attribute \src "simple/issuer.py:141" - wire width 1 input 1 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 1 input 2 \s_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 1 input 3 \r_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire width 1 \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire width 1 \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_rst - connect \Y $1 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 1 $3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $4 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B $1 - connect \Y $3 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 1 $5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $6 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $3 - connect \B \s_rst - connect \Y $5 - end - process $group_0 - assign \q_int$next \q_int - assign \q_int$next $5 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \q_int$next 1'0 - end - sync init - update \q_int 1'0 - sync posedge \coresync_clk - update \q_int \q_int$next - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire width 1 \q_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 1 $7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $8 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_rst - connect \Y $7 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 1 $9 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $10 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B $7 - connect \Y $9 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 1 $11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $12 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $9 - connect \B \s_rst - connect \Y $11 - end - process $group_1 - assign \q_rst 1'0 - assign \q_rst $11 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" - wire width 1 \qn_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - wire width 1 $13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $14 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_rst - connect \Y $13 - end - process $group_2 - assign \qn_rst 1'0 - assign \qn_rst $13 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" - wire width 1 \qlq_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - wire width 1 $15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $16 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_rst - connect \B \q_int - connect \Y $15 - end - process $group_3 - assign \qlq_rst 1'0 - assign \qlq_rst $15 - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.logical0.rok_l" -module \rok_l$56 - attribute \src "simple/issuer.py:141" - wire width 1 input 0 \coresync_clk - attribute \src "simple/issuer.py:141" - wire width 1 input 1 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire width 1 output 2 \q_rdok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 1 input 3 \s_rdok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 1 input 4 \r_rdok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire width 1 \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire width 1 \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_rdok - connect \Y $1 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 1 $3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $4 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B $1 - connect \Y $3 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 1 $5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $6 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $3 - connect \B \s_rdok - connect \Y $5 - end - process $group_0 - assign \q_int$next \q_int - assign \q_int$next $5 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \q_int$next 1'0 - end - sync init - update \q_int 1'0 - sync posedge \coresync_clk - update \q_int \q_int$next - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 1 $7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $8 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_rdok - connect \Y $7 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 1 $9 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $10 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B $7 - connect \Y $9 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 1 $11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $12 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $9 - connect \B \s_rdok - connect \Y $11 - end - process $group_1 - assign \q_rdok 1'0 - assign \q_rdok $11 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" - wire width 1 \qn_rdok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - wire width 1 $13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $14 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_rdok - connect \Y $13 - end - process $group_2 - assign \qn_rdok 1'0 - assign \qn_rdok $13 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" - wire width 1 \qlq_rdok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - wire width 1 $15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $16 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_rdok - connect \B \q_int - connect \Y $15 - end - process $group_3 - assign \qlq_rdok 1'0 - assign \qlq_rdok $15 - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.logical0.alui_l" -module \alui_l$57 - attribute \src "simple/issuer.py:141" - wire width 1 input 0 \coresync_clk - attribute \src "simple/issuer.py:141" - wire width 1 input 1 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire width 1 output 2 \q_alui - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 1 input 3 \r_alui - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 1 input 4 \s_alui - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire width 1 \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire width 1 \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_alui - connect \Y $1 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 1 $3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $4 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B $1 - connect \Y $3 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 1 $5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $6 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $3 - connect \B \s_alui - connect \Y $5 - end - process $group_0 - assign \q_int$next \q_int - assign \q_int$next $5 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \q_int$next 1'0 - end - sync init - update \q_int 1'0 - sync posedge \coresync_clk - update \q_int \q_int$next - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 1 $7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $8 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_alui - connect \Y $7 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 1 $9 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $10 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B $7 - connect \Y $9 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 1 $11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $12 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $9 - connect \B \s_alui - connect \Y $11 - end - process $group_1 - assign \q_alui 1'0 - assign \q_alui $11 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" - wire width 1 \qn_alui - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - wire width 1 $13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $14 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_alui - connect \Y $13 - end - process $group_2 - assign \qn_alui 1'0 - assign \qn_alui $13 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" - wire width 1 \qlq_alui - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - wire width 1 $15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $16 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_alui - connect \B \q_int - connect \Y $15 - end - process $group_3 - assign \qlq_alui 1'0 - assign \qlq_alui $15 - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.logical0.alu_l" -module \alu_l$58 - attribute \src "simple/issuer.py:141" - wire width 1 input 0 \coresync_clk - attribute \src "simple/issuer.py:141" - wire width 1 input 1 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire width 1 output 2 \q_alu - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 1 input 3 \r_alu - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 1 input 4 \s_alu - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire width 1 \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire width 1 \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $2 - parameter \A_SIGNED 0 - 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"/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \alu_logical0_logical_op__rc__ok$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \alu_logical0_logical_op__oe__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \alu_logical0_logical_op__oe__oe$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \alu_logical0_logical_op__oe__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \alu_logical0_logical_op__oe__ok$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \alu_logical0_logical_op__invert_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \alu_logical0_logical_op__invert_in$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \alu_logical0_logical_op__zero_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \alu_logical0_logical_op__zero_a$next - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \alu_logical0_logical_op__input_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \alu_logical0_logical_op__input_carry$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \alu_logical0_logical_op__invert_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \alu_logical0_logical_op__invert_out$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \alu_logical0_logical_op__write_cr0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \alu_logical0_logical_op__write_cr0$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \alu_logical0_logical_op__output_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \alu_logical0_logical_op__output_carry$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \alu_logical0_logical_op__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \alu_logical0_logical_op__is_32bit$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \alu_logical0_logical_op__is_signed - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \alu_logical0_logical_op__is_signed$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \alu_logical0_logical_op__data_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \alu_logical0_logical_op__data_len$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \alu_logical0_logical_op__insn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \alu_logical0_logical_op__insn$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 \alu_logical0_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 4 \alu_logical0_cr_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \alu_logical0_ra - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \alu_logical0_rb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 1 \alu_logical0_xer_so - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" - wire width 1 \alu_logical0_p_valid_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" - wire width 1 \alu_logical0_p_ready_o - cell \alu_logical0 \alu_logical0 - connect \coresync_clk \coresync_clk - connect \o_ok \o_ok - connect \cr_a_ok \cr_a_ok - connect \coresync_rst \coresync_rst - connect \n_valid_o \alu_logical0_n_valid_o - connect \n_ready_i \alu_logical0_n_ready_i - connect \logical_op__insn_type \alu_logical0_logical_op__insn_type - connect \logical_op__fn_unit \alu_logical0_logical_op__fn_unit - connect \logical_op__imm_data__data \alu_logical0_logical_op__imm_data__data - connect \logical_op__imm_data__ok \alu_logical0_logical_op__imm_data__ok - connect \logical_op__rc__rc \alu_logical0_logical_op__rc__rc - connect \logical_op__rc__ok \alu_logical0_logical_op__rc__ok - connect \logical_op__oe__oe \alu_logical0_logical_op__oe__oe - connect \logical_op__oe__ok \alu_logical0_logical_op__oe__ok - connect \logical_op__invert_in \alu_logical0_logical_op__invert_in - connect \logical_op__zero_a \alu_logical0_logical_op__zero_a - connect \logical_op__input_carry \alu_logical0_logical_op__input_carry - connect \logical_op__invert_out \alu_logical0_logical_op__invert_out - connect \logical_op__write_cr0 \alu_logical0_logical_op__write_cr0 - connect \logical_op__output_carry \alu_logical0_logical_op__output_carry - connect \logical_op__is_32bit \alu_logical0_logical_op__is_32bit - connect \logical_op__is_signed \alu_logical0_logical_op__is_signed - connect \logical_op__data_len \alu_logical0_logical_op__data_len - connect \logical_op__insn \alu_logical0_logical_op__insn - connect \o \alu_logical0_o - connect \cr_a \alu_logical0_cr_a - connect \ra \alu_logical0_ra - connect \rb \alu_logical0_rb - connect \xer_so \alu_logical0_xer_so - connect \p_valid_i \alu_logical0_p_valid_i - connect \p_ready_o \alu_logical0_p_ready_o - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 3 \src_l_s_src - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 3 \src_l_s_src$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 3 \src_l_r_src - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 3 \src_l_r_src$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire width 3 \src_l_q_src - cell \src_l$52 \src_l - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \s_src \src_l_s_src - connect \r_src \src_l_r_src - connect \q_src \src_l_q_src - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 1 \opc_l_s_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 1 \opc_l_s_opc$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 1 \opc_l_r_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 1 \opc_l_r_opc$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire width 1 \opc_l_q_opc - cell \opc_l$53 \opc_l - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \s_opc \opc_l_s_opc - connect \r_opc \opc_l_r_opc - connect \q_opc \opc_l_q_opc - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire width 2 \req_l_q_req - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 2 \req_l_s_req - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 2 \req_l_s_req$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 2 \req_l_r_req - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 2 \req_l_r_req$next - cell \req_l$54 \req_l - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \q_req \req_l_q_req - connect \s_req \req_l_s_req - connect \r_req \req_l_r_req - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 1 \rst_l_s_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 1 \rst_l_s_rst$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 1 \rst_l_r_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 1 \rst_l_r_rst$next - cell \rst_l$55 \rst_l - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \s_rst \rst_l_s_rst - connect \r_rst \rst_l_r_rst - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire width 1 \rok_l_q_rdok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 1 \rok_l_s_rdok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 1 \rok_l_s_rdok$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 1 \rok_l_r_rdok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 1 \rok_l_r_rdok$next - cell \rok_l$56 \rok_l - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \q_rdok \rok_l_q_rdok - connect \s_rdok \rok_l_s_rdok - connect \r_rdok \rok_l_r_rdok - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire width 1 \alui_l_q_alui - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 1 \alui_l_r_alui - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 1 \alui_l_r_alui$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 1 \alui_l_s_alui - cell \alui_l$57 \alui_l - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \q_alui \alui_l_q_alui - connect \r_alui \alui_l_r_alui - connect \s_alui \alui_l_s_alui - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire width 1 \alu_l_q_alu - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 1 \alu_l_r_alu - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 1 \alu_l_r_alu$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 1 \alu_l_s_alu - cell \alu_l$58 \alu_l - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \q_alu \alu_l_q_alu - connect \r_alu \alu_l_r_alu - connect \s_alu \alu_l_s_alu - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:187" - wire width 1 \all_rd - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:188" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:188" - cell $and $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cu_busy_o - connect \B \rok_l_q_rdok - connect \Y $1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - wire width 1 $3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - wire width 3 $4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - cell $not $5 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A \cu_rd__rel_o - connect \Y $4 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - wire width 3 $6 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - cell $or $7 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A $4 - connect \B \cu_rd__go_i - connect \Y $6 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - cell $reduce_and $8 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A $6 - connect \Y $3 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - wire width 1 $9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - cell $and $10 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $1 - connect \B $3 - connect \Y $9 - end - process $group_0 - assign \all_rd 1'0 - assign \all_rd $9 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire width 1 \all_rd_dly - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire width 1 \all_rd_dly$next - process $group_1 - assign \all_rd_dly$next \all_rd_dly - assign \all_rd_dly$next \all_rd - sync init - update \all_rd_dly 1'0 - sync posedge \coresync_clk - update \all_rd_dly \all_rd_dly$next - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" - wire width 1 \all_rd_rise - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - wire width 1 $11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $not $12 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \all_rd_dly - connect \Y $11 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - wire width 1 $13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $and $14 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \all_rd - connect \B $11 - connect \Y $13 - end - process $group_2 - assign \all_rd_rise 1'0 - assign \all_rd_rise $13 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:192" - wire width 1 \all_rd_pulse - process $group_3 - assign \all_rd_pulse 1'0 - assign \all_rd_pulse \all_rd_rise - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:196" - wire width 1 \alu_done - process $group_4 - assign \alu_done 1'0 - assign \alu_done \alu_logical0_n_valid_o - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire width 1 \alu_done_dly - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire width 1 \alu_done_dly$next - process $group_5 - assign \alu_done_dly$next \alu_done_dly - assign \alu_done_dly$next \alu_done - sync init - update \alu_done_dly 1'0 - sync posedge \coresync_clk - update \alu_done_dly \alu_done_dly$next - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" - wire width 1 \alu_done_rise - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - wire width 1 $15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $not $16 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \alu_done_dly - connect \Y $15 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - wire width 1 $17 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $and $18 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \alu_done - connect \B $15 - connect \Y $17 - end - process $group_6 - assign \alu_done_rise 1'0 - assign \alu_done_rise $17 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:197" - wire width 1 \alu_pulse - process $group_7 - assign \alu_pulse 1'0 - assign \alu_pulse \alu_done_rise - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:198" - wire width 2 \alu_pulsem - process $group_8 - assign \alu_pulsem 2'00 - assign \alu_pulsem { \alu_pulse \alu_pulse } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:204" - wire width 2 \prev_wr_go - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:204" - wire width 2 \prev_wr_go$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:206" - wire width 2 $19 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:206" - cell $and $20 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 2 - connect \A \cu_wr__go_i - connect \B { \cu_busy_o \cu_busy_o } - connect \Y $19 - end - process $group_9 - assign \prev_wr_go$next \prev_wr_go - assign \prev_wr_go$next $19 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \prev_wr_go$next 2'00 - end - sync init - update \prev_wr_go 2'00 - sync posedge \coresync_clk - update \prev_wr_go \prev_wr_go$next - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:108" - wire width 1 \cu_done_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - wire width 1 $21 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - wire width 1 $22 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - wire width 2 $23 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:97" - wire width 2 \cu_wrmask_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $not $24 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \Y_WIDTH 2 - connect \A \cu_wrmask_o - connect \Y $23 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - wire width 2 $25 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $and $26 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 2 - connect \A \cu_wr__rel_o - connect \B $23 - connect \Y $25 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $reduce_bool $27 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A $25 - connect \Y $22 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $not $28 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $22 - connect \Y $21 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - wire width 1 $29 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $and $30 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cu_busy_o - connect \B $21 - connect \Y $29 - end - process $group_10 - assign \cu_done_o 1'0 - assign \cu_done_o $29 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:211" - wire width 1 \wr_any - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" - wire width 1 $31 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" - cell $reduce_bool $32 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \cu_wr__go_i - connect \Y $31 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" - wire width 1 $33 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" - cell $reduce_bool $34 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \prev_wr_go - connect \Y $33 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" - wire width 1 $35 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" - cell $or $36 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $31 - connect \B $33 - connect \Y $35 - end - process $group_11 - assign \wr_any 1'0 - assign \wr_any $35 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:212" - wire width 1 \req_done - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" - wire width 1 $37 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" - cell $not $38 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \alu_logical0_n_ready_i - connect \Y $37 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" - wire width 1 $39 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" - cell $and $40 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_any - connect \B $37 - connect \Y $39 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" - wire width 2 $41 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" - cell $and $42 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 2 - connect \A \req_l_q_req - connect \B \cu_wrmask_o - connect \Y $41 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" - wire width 1 $43 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" - cell $eq $44 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $41 - connect \B 1'0 - connect \Y $43 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" - wire width 1 $45 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" - cell $and $46 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $39 - connect \B $43 - connect \Y $45 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - wire width 1 $47 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - cell $eq $48 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cu_wrmask_o - connect \B 1'0 - connect \Y $47 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - wire width 1 $49 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - cell $and $50 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $47 - connect \B \alu_logical0_n_ready_i - connect \Y $49 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - wire width 1 $51 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - cell $and $52 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $49 - connect \B \alu_logical0_n_valid_o - connect \Y $51 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - wire width 1 $53 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - cell $and $54 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $51 - connect \B \cu_busy_o - connect \Y $53 - end - process $group_12 - assign \req_done 1'0 - assign \req_done $45 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - switch { $53 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - case 1'1 - assign \req_done 1'1 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:226" - wire width 1 \reset - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:104" - wire width 1 \cu_go_die_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:230" - wire width 1 $55 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:230" - cell $or $56 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \req_done - connect \B \cu_go_die_i - connect \Y $55 - end - process $group_13 - assign \reset 1'0 - assign \reset $55 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:227" - wire width 1 \rst_r - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:231" - wire width 1 $57 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:231" - cell $or $58 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cu_issue_i - connect \B \cu_go_die_i - connect \Y $57 - end - process $group_14 - assign \rst_r 1'0 - assign \rst_r $57 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:228" - wire width 2 \reset_w - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:232" - wire width 2 $59 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:232" - cell $or $60 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 2 - connect \A \cu_wr__go_i - connect \B { \cu_go_die_i \cu_go_die_i } - connect \Y $59 - end - process $group_15 - assign \reset_w 2'00 - assign \reset_w $59 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:229" - wire width 3 \reset_r - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:233" - wire width 3 $61 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:233" - cell $or $62 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A \cu_rd__go_i - connect \B { \cu_go_die_i \cu_go_die_i \cu_go_die_i } - connect \Y $61 - end - process $group_16 - assign \reset_r 3'000 - assign \reset_r $61 - sync init - end - process $group_17 - assign \rok_l_s_rdok$next \rok_l_s_rdok - assign \rok_l_s_rdok$next \cu_issue_i - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \rok_l_s_rdok$next 1'0 - end - sync init - update \rok_l_s_rdok 1'0 - sync posedge \coresync_clk - update \rok_l_s_rdok \rok_l_s_rdok$next - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:237" - wire width 1 $63 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:237" - cell $and $64 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \alu_logical0_n_valid_o - connect \B \cu_busy_o - connect \Y $63 - end - process $group_18 - assign \rok_l_r_rdok$next \rok_l_r_rdok - assign \rok_l_r_rdok$next $63 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \rok_l_r_rdok$next 1'1 - end - sync init - update \rok_l_r_rdok 1'1 - sync posedge \coresync_clk - update \rok_l_r_rdok \rok_l_r_rdok$next - end - process $group_19 - assign \rst_l_s_rst$next \rst_l_s_rst - assign \rst_l_s_rst$next \all_rd - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \rst_l_s_rst$next 1'0 - end - sync init - update \rst_l_s_rst 1'0 - sync posedge \coresync_clk - update \rst_l_s_rst \rst_l_s_rst$next - end - process $group_20 - assign \rst_l_r_rst$next \rst_l_r_rst - assign \rst_l_r_rst$next \rst_r - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \rst_l_r_rst$next 1'1 - end - sync init - update \rst_l_r_rst 1'1 - sync posedge \coresync_clk - update \rst_l_r_rst \rst_l_r_rst$next - end - process $group_21 - assign \opc_l_s_opc$next \opc_l_s_opc - assign \opc_l_s_opc$next \cu_issue_i - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \opc_l_s_opc$next 1'0 - end - sync init - update \opc_l_s_opc 1'0 - sync posedge \coresync_clk - update \opc_l_s_opc \opc_l_s_opc$next - end - process $group_22 - assign \opc_l_r_opc$next \opc_l_r_opc - assign \opc_l_r_opc$next \req_done - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \opc_l_r_opc$next 1'1 - end - sync init - update \opc_l_r_opc 1'1 - sync posedge \coresync_clk - update \opc_l_r_opc \opc_l_r_opc$next - end - process $group_23 - assign \src_l_s_src$next \src_l_s_src - assign \src_l_s_src$next { \cu_issue_i \cu_issue_i \cu_issue_i } - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \src_l_s_src$next 3'000 - end - sync init - update \src_l_s_src 3'000 - sync posedge \coresync_clk - update \src_l_s_src \src_l_s_src$next - end - process $group_24 - assign \src_l_r_src$next \src_l_r_src - assign \src_l_r_src$next \reset_r - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \src_l_r_src$next 3'111 - end - sync init - update \src_l_r_src 3'111 - sync posedge \coresync_clk - update \src_l_r_src \src_l_r_src$next - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:252" - wire width 2 $65 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:252" - cell $and $66 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 2 - connect \A \alu_pulsem - connect \B \cu_wrmask_o - connect \Y $65 - end - process $group_25 - assign \req_l_s_req$next \req_l_s_req - assign \req_l_s_req$next $65 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \req_l_s_req$next 2'00 - end - sync init - update \req_l_s_req 2'00 - sync posedge \coresync_clk - update \req_l_s_req \req_l_s_req$next - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:253" - wire width 2 $67 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:253" - cell $or $68 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 2 - connect \A \reset_w - connect \B \prev_wr_go - connect \Y $67 - end - process $group_26 - assign \req_l_r_req$next \req_l_r_req - assign \req_l_r_req$next $67 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \req_l_r_req$next 2'11 - end - sync init - update \req_l_r_req 2'11 - sync posedge \coresync_clk - update \req_l_r_req \req_l_r_req$next - end - process $group_27 - assign \alu_logical0_logical_op__insn_type$next \alu_logical0_logical_op__insn_type - assign \alu_logical0_logical_op__fn_unit$next \alu_logical0_logical_op__fn_unit - assign \alu_logical0_logical_op__imm_data__data$next \alu_logical0_logical_op__imm_data__data - assign \alu_logical0_logical_op__imm_data__ok$next \alu_logical0_logical_op__imm_data__ok - assign \alu_logical0_logical_op__rc__rc$next \alu_logical0_logical_op__rc__rc - assign \alu_logical0_logical_op__rc__ok$next \alu_logical0_logical_op__rc__ok - assign \alu_logical0_logical_op__oe__oe$next \alu_logical0_logical_op__oe__oe - assign \alu_logical0_logical_op__oe__ok$next \alu_logical0_logical_op__oe__ok - assign \alu_logical0_logical_op__invert_in$next \alu_logical0_logical_op__invert_in - assign \alu_logical0_logical_op__zero_a$next \alu_logical0_logical_op__zero_a - assign \alu_logical0_logical_op__input_carry$next \alu_logical0_logical_op__input_carry - assign \alu_logical0_logical_op__invert_out$next \alu_logical0_logical_op__invert_out - assign \alu_logical0_logical_op__write_cr0$next \alu_logical0_logical_op__write_cr0 - assign \alu_logical0_logical_op__output_carry$next \alu_logical0_logical_op__output_carry - assign \alu_logical0_logical_op__is_32bit$next \alu_logical0_logical_op__is_32bit - assign \alu_logical0_logical_op__is_signed$next \alu_logical0_logical_op__is_signed - assign \alu_logical0_logical_op__data_len$next \alu_logical0_logical_op__data_len - assign \alu_logical0_logical_op__insn$next \alu_logical0_logical_op__insn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:257" - switch { \cu_issue_i } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:257" - case 1'1 - assign { \alu_logical0_logical_op__insn$next \alu_logical0_logical_op__data_len$next \alu_logical0_logical_op__is_signed$next \alu_logical0_logical_op__is_32bit$next \alu_logical0_logical_op__output_carry$next \alu_logical0_logical_op__write_cr0$next \alu_logical0_logical_op__invert_out$next \alu_logical0_logical_op__input_carry$next \alu_logical0_logical_op__zero_a$next \alu_logical0_logical_op__invert_in$next { \alu_logical0_logical_op__oe__ok$next \alu_logical0_logical_op__oe__oe$next } { \alu_logical0_logical_op__rc__ok$next \alu_logical0_logical_op__rc__rc$next } { \alu_logical0_logical_op__imm_data__ok$next \alu_logical0_logical_op__imm_data__data$next } \alu_logical0_logical_op__fn_unit$next \alu_logical0_logical_op__insn_type$next } { \oper_i_alu_logical0__insn \oper_i_alu_logical0__data_len \oper_i_alu_logical0__is_signed \oper_i_alu_logical0__is_32bit \oper_i_alu_logical0__output_carry \oper_i_alu_logical0__write_cr0 \oper_i_alu_logical0__invert_out \oper_i_alu_logical0__input_carry \oper_i_alu_logical0__zero_a \oper_i_alu_logical0__invert_in { \oper_i_alu_logical0__oe__ok \oper_i_alu_logical0__oe__oe } { \oper_i_alu_logical0__rc__ok \oper_i_alu_logical0__rc__rc } { \oper_i_alu_logical0__imm_data__ok \oper_i_alu_logical0__imm_data__data } \oper_i_alu_logical0__fn_unit \oper_i_alu_logical0__insn_type } - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \alu_logical0_logical_op__imm_data__data$next 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \alu_logical0_logical_op__imm_data__ok$next 1'0 - assign \alu_logical0_logical_op__rc__rc$next 1'0 - assign \alu_logical0_logical_op__rc__ok$next 1'0 - assign \alu_logical0_logical_op__oe__oe$next 1'0 - assign \alu_logical0_logical_op__oe__ok$next 1'0 - end - sync init - update \alu_logical0_logical_op__insn_type 7'0000000 - update \alu_logical0_logical_op__fn_unit 11'00000000000 - update \alu_logical0_logical_op__imm_data__data 64'0000000000000000000000000000000000000000000000000000000000000000 - update \alu_logical0_logical_op__imm_data__ok 1'0 - update \alu_logical0_logical_op__rc__rc 1'0 - update \alu_logical0_logical_op__rc__ok 1'0 - update \alu_logical0_logical_op__oe__oe 1'0 - update \alu_logical0_logical_op__oe__ok 1'0 - update \alu_logical0_logical_op__invert_in 1'0 - update \alu_logical0_logical_op__zero_a 1'0 - update \alu_logical0_logical_op__input_carry 2'00 - update \alu_logical0_logical_op__invert_out 1'0 - update \alu_logical0_logical_op__write_cr0 1'0 - update \alu_logical0_logical_op__output_carry 1'0 - update \alu_logical0_logical_op__is_32bit 1'0 - update \alu_logical0_logical_op__is_signed 1'0 - update \alu_logical0_logical_op__data_len 4'0000 - update \alu_logical0_logical_op__insn 32'00000000000000000000000000000000 - sync posedge \coresync_clk - update \alu_logical0_logical_op__insn_type \alu_logical0_logical_op__insn_type$next - update \alu_logical0_logical_op__fn_unit \alu_logical0_logical_op__fn_unit$next - update \alu_logical0_logical_op__imm_data__data \alu_logical0_logical_op__imm_data__data$next - update \alu_logical0_logical_op__imm_data__ok \alu_logical0_logical_op__imm_data__ok$next - update \alu_logical0_logical_op__rc__rc \alu_logical0_logical_op__rc__rc$next - update \alu_logical0_logical_op__rc__ok \alu_logical0_logical_op__rc__ok$next - update \alu_logical0_logical_op__oe__oe \alu_logical0_logical_op__oe__oe$next - update \alu_logical0_logical_op__oe__ok \alu_logical0_logical_op__oe__ok$next - update \alu_logical0_logical_op__invert_in \alu_logical0_logical_op__invert_in$next - update \alu_logical0_logical_op__zero_a \alu_logical0_logical_op__zero_a$next - update \alu_logical0_logical_op__input_carry \alu_logical0_logical_op__input_carry$next - update \alu_logical0_logical_op__invert_out \alu_logical0_logical_op__invert_out$next - update \alu_logical0_logical_op__write_cr0 \alu_logical0_logical_op__write_cr0$next - update \alu_logical0_logical_op__output_carry \alu_logical0_logical_op__output_carry$next - update \alu_logical0_logical_op__is_32bit \alu_logical0_logical_op__is_32bit$next - update \alu_logical0_logical_op__is_signed \alu_logical0_logical_op__is_signed$next - update \alu_logical0_logical_op__data_len \alu_logical0_logical_op__data_len$next - update \alu_logical0_logical_op__insn \alu_logical0_logical_op__insn$next - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" - wire width 64 \data_r0__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" - wire width 64 \data_r0__o$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" - wire width 1 \data_r0__o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" - wire width 1 \data_r0__o_ok$next - process $group_45 - assign \data_r0__o$next \data_r0__o - assign \data_r0__o_ok$next \data_r0__o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" - switch { \alu_pulse } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" - case 1'1 - assign { \data_r0__o_ok$next \data_r0__o$next } { \o_ok \alu_logical0_o } - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" - switch { \cu_issue_i } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" - case 1'1 - assign { \data_r0__o_ok$next \data_r0__o$next } 65'00000000000000000000000000000000000000000000000000000000000000000 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \data_r0__o_ok$next 1'0 - end - sync init - update \data_r0__o 64'0000000000000000000000000000000000000000000000000000000000000000 - update \data_r0__o_ok 1'0 - sync posedge \coresync_clk - update \data_r0__o \data_r0__o$next - update \data_r0__o_ok \data_r0__o_ok$next - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" - wire width 4 \data_r1__cr_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" - wire width 4 \data_r1__cr_a$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" - wire width 1 \data_r1__cr_a_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" - wire width 1 \data_r1__cr_a_ok$next - process $group_47 - assign \data_r1__cr_a$next \data_r1__cr_a - assign \data_r1__cr_a_ok$next \data_r1__cr_a_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" - switch { \alu_pulse } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" - case 1'1 - assign { \data_r1__cr_a_ok$next \data_r1__cr_a$next } { \cr_a_ok \alu_logical0_cr_a } - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" - switch { \cu_issue_i } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" - case 1'1 - assign { \data_r1__cr_a_ok$next \data_r1__cr_a$next } 5'00000 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \data_r1__cr_a_ok$next 1'0 - end - sync init - update \data_r1__cr_a 4'0000 - update \data_r1__cr_a_ok 1'0 - sync posedge \coresync_clk - update \data_r1__cr_a \data_r1__cr_a$next - update \data_r1__cr_a_ok \data_r1__cr_a_ok$next - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" - wire width 1 $69 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" - cell $and $70 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \o_ok - connect \B \cu_busy_o - connect \Y $69 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" - wire width 1 $71 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" - cell $and $72 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cr_a_ok - connect \B \cu_busy_o - connect \Y $71 - end - process $group_49 - assign \cu_wrmask_o 2'00 - assign \cu_wrmask_o { $71 $69 } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:167" - wire width 1 \src_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:168" - wire width 1 $73 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:168" - cell $mux $74 - parameter \WIDTH 1 - connect \A \src_l_q_src [0] - connect \B \opc_l_q_opc - connect \S \alu_logical0_logical_op__zero_a - connect \Y $73 - end - process $group_50 - assign \src_sel 1'0 - assign \src_sel $73 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:166" - wire width 64 \src_or_imm - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:169" - wire width 64 $75 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:169" - cell $mux $76 - parameter \WIDTH 64 - connect \A \src1_i - connect \B 64'0000000000000000000000000000000000000000000000000000000000000000 - connect \S \alu_logical0_logical_op__zero_a - connect \Y $75 - end - process $group_51 - assign \src_or_imm 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \src_or_imm $75 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:167" - wire width 1 \src_sel$77 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:168" - wire width 1 $78 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:168" - cell $mux $79 - parameter \WIDTH 1 - connect \A \src_l_q_src [1] - connect \B \opc_l_q_opc - connect \S \alu_logical0_logical_op__imm_data__ok - connect \Y $78 - end - process $group_52 - assign \src_sel$77 1'0 - assign \src_sel$77 $78 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:166" - wire width 64 \src_or_imm$80 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:169" - wire width 64 $81 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:169" - cell $mux $82 - parameter \WIDTH 64 - connect \A \src2_i - connect \B \alu_logical0_logical_op__imm_data__data - connect \S \alu_logical0_logical_op__imm_data__ok - connect \Y $81 - end - process $group_53 - assign \src_or_imm$80 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \src_or_imm$80 $81 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" - wire width 64 \src_r0 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" - wire width 64 \src_r0$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - wire width 64 $83 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - cell $mux $84 - parameter \WIDTH 64 - connect \A \src_r0 - connect \B \src_or_imm - connect \S \src_sel - connect \Y $83 - end - process $group_54 - assign \alu_logical0_ra 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \alu_logical0_ra $83 - sync init - end - process $group_55 - assign \src_r0$next \src_r0 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" - switch { \src_sel } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" - case 1'1 - assign \src_r0$next \src_or_imm - end - sync init - update \src_r0 64'0000000000000000000000000000000000000000000000000000000000000000 - sync posedge \coresync_clk - update \src_r0 \src_r0$next - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" - wire width 64 \src_r1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" - wire width 64 \src_r1$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - wire width 64 $85 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - cell $mux $86 - parameter \WIDTH 64 - connect \A \src_r1 - connect \B \src_or_imm$80 - connect \S \src_sel$77 - connect \Y $85 - end - process $group_56 - assign \alu_logical0_rb 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \alu_logical0_rb $85 - sync init - end - process $group_57 - assign \src_r1$next \src_r1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" - switch { \src_sel$77 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" - case 1'1 - assign \src_r1$next \src_or_imm$80 - end - sync init - update \src_r1 64'0000000000000000000000000000000000000000000000000000000000000000 - sync posedge \coresync_clk - update \src_r1 \src_r1$next - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" - wire width 1 \src_r2 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" - wire width 1 \src_r2$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - wire width 1 $87 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - cell $mux $88 - parameter \WIDTH 1 - connect \A \src_r2 - connect \B \src3_i - connect \S \src_l_q_src [2] - connect \Y $87 - end - process $group_58 - assign \alu_logical0_xer_so 1'0 - assign \alu_logical0_xer_so $87 - sync init - end - process $group_59 - assign \src_r2$next \src_r2 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" - switch { \src_l_q_src [2] } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" - case 1'1 - assign \src_r2$next \src3_i - end - sync init - update \src_r2 1'0 - sync posedge \coresync_clk - update \src_r2 \src_r2$next - end - process $group_60 - assign \alu_logical0_p_valid_i 1'0 - assign \alu_logical0_p_valid_i \alui_l_q_alui - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:327" - wire width 1 $89 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:327" - cell $and $90 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \alu_logical0_p_ready_o - connect \B \alui_l_q_alui - connect \Y $89 - end - process $group_61 - assign \alui_l_r_alui$next \alui_l_r_alui - assign \alui_l_r_alui$next $89 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \alui_l_r_alui$next 1'1 - end - sync init - update \alui_l_r_alui 1'1 - sync posedge \coresync_clk - update \alui_l_r_alui \alui_l_r_alui$next - end - process $group_62 - assign \alui_l_s_alui 1'0 - assign \alui_l_s_alui \all_rd_pulse - sync init - end - process $group_63 - assign \alu_logical0_n_ready_i 1'0 - assign \alu_logical0_n_ready_i \alu_l_q_alu - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:334" - wire width 1 $91 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:334" - cell $and $92 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \alu_logical0_n_valid_o - connect \B \alu_l_q_alu - connect \Y $91 - end - process $group_64 - assign \alu_l_r_alu$next \alu_l_r_alu - assign \alu_l_r_alu$next $91 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \alu_l_r_alu$next 1'1 - end - sync init - update \alu_l_r_alu 1'1 - sync posedge \coresync_clk - update \alu_l_r_alu \alu_l_r_alu$next - end - process $group_65 - assign \alu_l_s_alu 1'0 - assign \alu_l_s_alu \all_rd_pulse - sync init - end - process $group_66 - assign \cu_busy_o 1'0 - assign \cu_busy_o \opc_l_q_opc - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - wire width 3 $93 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - cell $and $94 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A \src_l_q_src - connect \B { \cu_busy_o \cu_busy_o \cu_busy_o } - connect \Y $93 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:173" - wire width 1 $95 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:173" - cell $not $96 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \alu_logical0_logical_op__zero_a - connect \Y $95 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:173" - wire width 1 $97 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:173" - cell $not $98 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \alu_logical0_logical_op__imm_data__ok - connect \Y $97 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - wire width 3 $99 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - cell $and $100 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A $93 - connect \B { 1'1 $97 $95 } - connect \Y $99 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - wire width 3 $101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - cell $not $102 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A \cu_rdmaskn_i - connect \Y $101 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - wire width 3 $103 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - cell $and $104 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A $99 - connect \B $101 - connect \Y $103 - end - process $group_67 - assign \cu_rd__rel_o 3'000 - assign \cu_rd__rel_o $103 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:102" - wire width 1 \cu_shadown_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" - wire width 1 $105 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" - cell $and $106 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cu_busy_o - connect \B \cu_shadown_i - connect \Y $105 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" - wire width 1 $107 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" - cell $and $108 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cu_busy_o - connect \B \cu_shadown_i - connect \Y $107 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351" - wire width 2 $109 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351" - cell $and $110 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 2 - connect \A \req_l_q_req - connect \B { $105 $107 } - connect \Y $109 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351" - wire width 2 $111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351" - cell $and $112 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 2 - connect \A $109 - connect \B \cu_wrmask_o - connect \Y $111 - end - process $group_68 - assign \cu_wr__rel_o 2'00 - assign \cu_wr__rel_o $111 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - wire width 1 $113 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - cell $and $114 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cu_wr__go_i [0] - connect \B \cu_busy_o - connect \Y $113 - end - process $group_69 - assign \dest1_o 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - switch { $113 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - case 1'1 - assign \dest1_o { \data_r0__o_ok \data_r0__o } [63:0] - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - wire width 1 $115 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - cell $and $116 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cu_wr__go_i [1] - connect \B \cu_busy_o - connect \Y $115 - end - process $group_70 - assign \dest2_o 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - switch { $115 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - case 1'1 - assign \dest2_o { \data_r1__cr_a_ok \data_r1__cr_a } [3:0] - end - sync init - end - connect \cu_go_die_i 1'0 - connect \cu_shadown_i 1'1 -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.spr0.alu_spr0.p" -module \p$59 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" - wire width 1 input 0 \p_valid_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" - wire width 1 input 1 \p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:158" - wire width 1 \trigger - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" - cell $and $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \p_valid_i - connect \B \p_ready_o - connect \Y $1 - end - process $group_0 - assign \trigger 1'0 - assign \trigger $1 - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.spr0.alu_spr0.n" -module \n$60 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" - wire width 1 input 0 \n_valid_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" - wire width 1 input 1 \n_ready_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:251" - wire width 1 \trigger - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" - cell $and $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \n_ready_i - connect \B \n_valid_o - connect \Y $1 - end - process $group_0 - assign \trigger 1'0 - assign \trigger $1 - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.spr0.alu_spr0.pipe.p" -module \p$62 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" - wire width 1 input 0 \p_valid_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" - wire width 1 input 1 \p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:158" - wire width 1 \trigger - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" - cell $and $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \p_valid_i - connect \B \p_ready_o - connect \Y $1 - end - process $group_0 - assign \trigger 1'0 - assign \trigger $1 - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.spr0.alu_spr0.pipe.n" -module \n$63 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" - wire width 1 input 0 \n_valid_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" - wire width 1 input 1 \n_ready_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:251" - wire width 1 \trigger - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" - cell $and $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \n_ready_i - connect \B \n_valid_o - connect \Y $1 - end - process $group_0 - assign \trigger 1'0 - assign \trigger $1 - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.spr0.alu_spr0.pipe.spr_main" -module \spr_main - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 input 0 \muxid - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 input 1 \spr_op__insn_type - attribute \enum_base_type "Function" - attribute \enum_value_00000000000 "NONE" - attribute \enum_value_00000000010 "ALU" - attribute \enum_value_00000000100 "LDST" - attribute \enum_value_00000001000 "SHIFT_ROT" - attribute \enum_value_00000010000 "LOGICAL" - attribute \enum_value_00000100000 "BRANCH" - attribute \enum_value_00001000000 "CR" - attribute \enum_value_00010000000 "TRAP" - attribute \enum_value_00100000000 "MUL" - attribute \enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 input 2 \spr_op__fn_unit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 input 3 \spr_op__insn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 4 \spr_op__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 5 \ra - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 6 \spr1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 7 \fast1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 1 input 8 \xer_so - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 2 input 9 \xer_ov - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 2 input 10 \xer_ca - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 output 11 \muxid$1 - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 output 12 \spr_op__insn_type$2 - attribute \enum_base_type "Function" - attribute \enum_value_00000000000 "NONE" - attribute \enum_value_00000000010 "ALU" - attribute \enum_value_00000000100 "LDST" - attribute \enum_value_00000001000 "SHIFT_ROT" - attribute \enum_value_00000010000 "LOGICAL" - attribute \enum_value_00000100000 "BRANCH" - attribute \enum_value_00001000000 "CR" - attribute \enum_value_00010000000 "TRAP" - attribute \enum_value_00100000000 "MUL" - attribute \enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 output 13 \spr_op__fn_unit$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 output 14 \spr_op__insn$4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 15 \spr_op__is_32bit$5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 output 16 \o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 17 \o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 output 18 \spr1$6 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 19 \spr1_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 output 20 \fast1$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 21 \fast1_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 22 \xer_so$8 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 23 \xer_so_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 2 output 24 \xer_ov$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 25 \xer_ov_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 2 output 26 \xer_ca$10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 27 \xer_ca_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:42" - wire width 10 \spr - process $group_0 - assign \spr 10'0000000000 - assign \spr { { \spr_op__insn [15] \spr_op__insn [14] \spr_op__insn [13] \spr_op__insn [12] \spr_op__insn [11] } { \spr_op__insn [20] \spr_op__insn [19] \spr_op__insn [18] \spr_op__insn [17] \spr_op__insn [16] } } - sync init - end - process $group_1 - assign \fast1$7 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:46" - switch \spr_op__insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:48" - attribute \nmigen.decoding "OP_MTSPR/49" - case 7'0110001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:49" - switch \spr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:52" - case 10'0000001001, 10'0000001000, 10'1100101111, 10'0000011010, 10'0000011011, 10'0000000001, 10'0000010110 - assign \fast1$7 \ra - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:70" - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:75" - attribute \nmigen.decoding "OP_MFSPR/46" - case 7'0101110 - end - sync init - end - process $group_2 - assign \fast1_ok 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:46" - switch \spr_op__insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:48" - attribute \nmigen.decoding "OP_MTSPR/49" - case 7'0110001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:49" - switch \spr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:52" - case 10'0000001001, 10'0000001000, 10'1100101111, 10'0000011010, 10'0000011011, 10'0000000001, 10'0000010110 - assign \fast1_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:70" - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:75" - attribute \nmigen.decoding "OP_MFSPR/46" - case 7'0101110 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:56" - wire width 1 $11 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:56" - cell $eq $12 - parameter \A_SIGNED 0 - parameter \A_WIDTH 10 - parameter \B_SIGNED 0 - parameter \B_WIDTH 10 - parameter \Y_WIDTH 1 - connect \A \spr - connect \B 10'0000000001 - connect \Y $11 - end - process $group_3 - assign \xer_so$8 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:46" - switch \spr_op__insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:48" - attribute \nmigen.decoding "OP_MTSPR/49" - case 7'0110001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:49" - switch \spr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:52" - case 10'0000001001, 10'0000001000, 10'1100101111, 10'0000011010, 10'0000011011, 10'0000000001, 10'0000010110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:56" - switch { $11 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:56" - case 1'1 - assign \xer_so$8 \ra [31] - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:70" - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:75" - attribute \nmigen.decoding "OP_MFSPR/46" - case 7'0101110 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:56" - wire width 1 $13 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:56" - cell $eq $14 - parameter \A_SIGNED 0 - parameter \A_WIDTH 10 - parameter \B_SIGNED 0 - parameter \B_WIDTH 10 - parameter \Y_WIDTH 1 - connect \A \spr - connect \B 10'0000000001 - connect \Y $13 - end - process $group_4 - assign \xer_so_ok 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:46" - switch \spr_op__insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:48" - attribute \nmigen.decoding "OP_MTSPR/49" - case 7'0110001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:49" - switch \spr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:52" - case 10'0000001001, 10'0000001000, 10'1100101111, 10'0000011010, 10'0000011011, 10'0000000001, 10'0000010110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:56" - switch { $13 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:56" - case 1'1 - assign \xer_so_ok 1'1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:70" - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:75" - attribute \nmigen.decoding "OP_MFSPR/46" - case 7'0101110 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:56" - wire width 1 $15 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:56" - cell $eq $16 - parameter \A_SIGNED 0 - parameter \A_WIDTH 10 - parameter \B_SIGNED 0 - parameter \B_WIDTH 10 - parameter \Y_WIDTH 1 - connect \A \spr - connect \B 10'0000000001 - connect \Y $15 - end - process $group_5 - assign \xer_ov$9 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:46" - switch \spr_op__insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:48" - attribute \nmigen.decoding "OP_MTSPR/49" - case 7'0110001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:49" - switch \spr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:52" - case 10'0000001001, 10'0000001000, 10'1100101111, 10'0000011010, 10'0000011011, 10'0000000001, 10'0000010110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:56" - switch { $15 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:56" - case 1'1 - assign \xer_ov$9 [0] \ra [30] - assign \xer_ov$9 [1] \ra [19] - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:70" - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:75" - attribute \nmigen.decoding "OP_MFSPR/46" - case 7'0101110 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:56" - wire width 1 $17 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:56" - cell $eq $18 - parameter \A_SIGNED 0 - parameter \A_WIDTH 10 - parameter \B_SIGNED 0 - parameter \B_WIDTH 10 - parameter \Y_WIDTH 1 - connect \A \spr - connect \B 10'0000000001 - connect \Y $17 - end - process $group_6 - assign \xer_ov_ok 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:46" - switch \spr_op__insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:48" - attribute \nmigen.decoding "OP_MTSPR/49" - case 7'0110001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:49" - switch \spr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:52" - case 10'0000001001, 10'0000001000, 10'1100101111, 10'0000011010, 10'0000011011, 10'0000000001, 10'0000010110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:56" - switch { $17 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:56" - case 1'1 - assign \xer_ov_ok 1'1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:70" - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:75" - attribute \nmigen.decoding "OP_MFSPR/46" - case 7'0101110 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:56" - wire width 1 $19 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:56" - cell $eq $20 - parameter \A_SIGNED 0 - parameter \A_WIDTH 10 - parameter \B_SIGNED 0 - parameter \B_WIDTH 10 - parameter \Y_WIDTH 1 - connect \A \spr - connect \B 10'0000000001 - connect \Y $19 - end - process $group_7 - assign \xer_ca$10 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:46" - switch \spr_op__insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:48" - attribute \nmigen.decoding "OP_MTSPR/49" - case 7'0110001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:49" - switch \spr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:52" - case 10'0000001001, 10'0000001000, 10'1100101111, 10'0000011010, 10'0000011011, 10'0000000001, 10'0000010110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:56" - switch { $19 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:56" - case 1'1 - assign \xer_ca$10 [0] \ra [29] - assign \xer_ca$10 [1] \ra [18] - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:70" - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:75" - attribute \nmigen.decoding "OP_MFSPR/46" - case 7'0101110 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:56" - wire width 1 $21 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:56" - cell $eq $22 - parameter \A_SIGNED 0 - parameter \A_WIDTH 10 - parameter \B_SIGNED 0 - parameter \B_WIDTH 10 - parameter \Y_WIDTH 1 - connect \A \spr - connect \B 10'0000000001 - connect \Y $21 - end - process $group_8 - assign \xer_ca_ok 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:46" - switch \spr_op__insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:48" - attribute \nmigen.decoding "OP_MTSPR/49" - case 7'0110001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:49" - switch \spr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:52" - case 10'0000001001, 10'0000001000, 10'1100101111, 10'0000011010, 10'0000011011, 10'0000000001, 10'0000010110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:56" - switch { $21 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:56" - case 1'1 - assign \xer_ca_ok 1'1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:70" - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:75" - attribute \nmigen.decoding "OP_MFSPR/46" - case 7'0101110 - end - sync init - end - process $group_9 - assign \spr1$6 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:46" - switch \spr_op__insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:48" - attribute \nmigen.decoding "OP_MTSPR/49" - case 7'0110001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:49" - switch \spr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:52" - case 10'0000001001, 10'0000001000, 10'1100101111, 10'0000011010, 10'0000011011, 10'0000000001, 10'0000010110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:70" - case - assign \spr1$6 \ra - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:75" - attribute \nmigen.decoding "OP_MFSPR/46" - case 7'0101110 - end - sync init - end - process $group_10 - assign \spr1_ok 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:46" - switch \spr_op__insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:48" - attribute \nmigen.decoding "OP_MTSPR/49" - case 7'0110001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:49" - switch \spr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:52" - case 10'0000001001, 10'0000001000, 10'1100101111, 10'0000011010, 10'0000011011, 10'0000000001, 10'0000010110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:70" - case - assign \spr1_ok 1'1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:75" - attribute \nmigen.decoding "OP_MFSPR/46" - case 7'0101110 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:82" - wire width 1 $23 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:82" - cell $eq $24 - parameter \A_SIGNED 0 - parameter \A_WIDTH 10 - parameter \B_SIGNED 0 - parameter \B_WIDTH 10 - parameter \Y_WIDTH 1 - connect \A \spr - connect \B 10'0000000001 - connect \Y $23 - end - process $group_12 - assign \o_ok 1'0 - assign \o 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:46" - switch \spr_op__insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:48" - attribute \nmigen.decoding "OP_MTSPR/49" - case 7'0110001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:75" - attribute \nmigen.decoding "OP_MFSPR/46" - case 7'0101110 - assign \o_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:77" - switch \spr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:80" - case 10'0000001001, 10'0000001000, 10'1100101111, 10'0000011010, 10'0000011011, 10'0000000001, 10'0000010110, 10'0100001100 - assign \o \fast1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:82" - switch { $23 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:82" - case 1'1 - assign { \o_ok \o } [63:32] 32'00000000000000000000000000000000 - assign { \o_ok \o } [28:20] 9'000000000 - assign { \o_ok \o } [31] \xer_so - assign { \o_ok \o } [30] \xer_ov [0] - assign { \o_ok \o } [19] \xer_ov [1] - assign { \o_ok \o } [29] \xer_ca [0] - assign { \o_ok \o } [18] \xer_ca [1] - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:95" - case 10'0100001101 - assign \o [31:0] \fast1 [63:32] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/spr/main_stage.py:99" - case - assign \o \spr1 - end - end - sync init - end - process $group_13 - assign \muxid$1 2'00 - assign \muxid$1 \muxid - sync init - end - process $group_14 - assign \spr_op__insn_type$2 7'0000000 - assign \spr_op__fn_unit$3 11'00000000000 - assign \spr_op__insn$4 32'00000000000000000000000000000000 - assign \spr_op__is_32bit$5 1'0 - assign { \spr_op__is_32bit$5 \spr_op__insn$4 \spr_op__fn_unit$3 \spr_op__insn_type$2 } { \spr_op__is_32bit \spr_op__insn \spr_op__fn_unit \spr_op__insn_type } - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.spr0.alu_spr0.pipe" -module \pipe$61 - attribute \src "simple/issuer.py:141" - wire width 1 input 0 \coresync_clk - attribute \src "simple/issuer.py:141" - wire width 1 input 1 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" - wire width 1 input 2 \p_valid_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" - wire width 1 output 3 \p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 input 4 \muxid - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 input 5 \spr_op__insn_type - attribute \enum_base_type "Function" - attribute \enum_value_00000000000 "NONE" - attribute \enum_value_00000000010 "ALU" - attribute \enum_value_00000000100 "LDST" - attribute \enum_value_00000001000 "SHIFT_ROT" - attribute \enum_value_00000010000 "LOGICAL" - attribute \enum_value_00000100000 "BRANCH" - attribute \enum_value_00001000000 "CR" - attribute \enum_value_00010000000 "TRAP" - attribute \enum_value_00100000000 "MUL" - attribute \enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 input 6 \spr_op__fn_unit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 input 7 \spr_op__insn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 8 \spr_op__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 9 \ra - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 10 \spr1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 11 \fast1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 1 input 12 \xer_so - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 2 input 13 \xer_ov - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 2 input 14 \xer_ca - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" - wire width 1 output 15 \n_valid_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" - wire width 1 input 16 \n_ready_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 output 17 \muxid$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \muxid$1$next - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 output 18 \spr_op__insn_type$2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \spr_op__insn_type$2$next - attribute \enum_base_type "Function" - attribute \enum_value_00000000000 "NONE" - attribute \enum_value_00000000010 "ALU" - attribute \enum_value_00000000100 "LDST" - attribute \enum_value_00000001000 "SHIFT_ROT" - attribute \enum_value_00000010000 "LOGICAL" - attribute \enum_value_00000100000 "BRANCH" - attribute \enum_value_00001000000 "CR" - attribute \enum_value_00010000000 "TRAP" - attribute \enum_value_00100000000 "MUL" - attribute \enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 output 19 \spr_op__fn_unit$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 \spr_op__fn_unit$3$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 output 20 \spr_op__insn$4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \spr_op__insn$4$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 21 \spr_op__is_32bit$5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \spr_op__is_32bit$5$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 output 22 \o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 \o$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 23 \o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \o_ok$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 output 24 \spr1$6 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 \spr1$6$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 25 \spr1_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \spr1_ok$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 output 26 \fast1$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 \fast1$7$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 27 \fast1_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \fast1_ok$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 28 \xer_so$8 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \xer_so$8$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 29 \xer_so_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \xer_so_ok$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 2 output 30 \xer_ov$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 2 \xer_ov$9$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 31 \xer_ov_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \xer_ov_ok$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 2 output 32 \xer_ca$10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 2 \xer_ca$10$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 33 \xer_ca_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \xer_ca_ok$next - cell \p$62 \p - connect \p_valid_i \p_valid_i - connect \p_ready_o \p_ready_o - end - cell \n$63 \n - connect \n_valid_o \n_valid_o - connect \n_ready_i \n_ready_i - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \spr_main_muxid - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \spr_main_spr_op__insn_type - attribute \enum_base_type "Function" - attribute \enum_value_00000000000 "NONE" - attribute \enum_value_00000000010 "ALU" - attribute \enum_value_00000000100 "LDST" - attribute \enum_value_00000001000 "SHIFT_ROT" - attribute \enum_value_00000010000 "LOGICAL" - attribute \enum_value_00000100000 "BRANCH" - attribute \enum_value_00001000000 "CR" - attribute \enum_value_00010000000 "TRAP" - attribute \enum_value_00100000000 "MUL" - attribute \enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 \spr_main_spr_op__fn_unit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \spr_main_spr_op__insn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \spr_main_spr_op__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \spr_main_ra - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \spr_main_spr1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \spr_main_fast1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 1 \spr_main_xer_so - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 2 \spr_main_xer_ov - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 2 \spr_main_xer_ca - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \spr_main_muxid$11 - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \spr_main_spr_op__insn_type$12 - attribute \enum_base_type "Function" - attribute \enum_value_00000000000 "NONE" - attribute \enum_value_00000000010 "ALU" - attribute \enum_value_00000000100 "LDST" - attribute \enum_value_00000001000 "SHIFT_ROT" - attribute \enum_value_00000010000 "LOGICAL" - attribute \enum_value_00000100000 "BRANCH" - attribute \enum_value_00001000000 "CR" - attribute \enum_value_00010000000 "TRAP" - attribute \enum_value_00100000000 "MUL" - attribute \enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 \spr_main_spr_op__fn_unit$13 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \spr_main_spr_op__insn$14 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \spr_main_spr_op__is_32bit$15 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 \spr_main_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \spr_main_o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 \spr_main_spr1$16 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \spr_main_spr1_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 \spr_main_fast1$17 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \spr_main_fast1_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \spr_main_xer_so$18 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \spr_main_xer_so_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 2 \spr_main_xer_ov$19 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \spr_main_xer_ov_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 2 \spr_main_xer_ca$20 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \spr_main_xer_ca_ok - cell \spr_main \spr_main - connect \muxid \spr_main_muxid - connect \spr_op__insn_type \spr_main_spr_op__insn_type - connect \spr_op__fn_unit \spr_main_spr_op__fn_unit - connect \spr_op__insn \spr_main_spr_op__insn - connect \spr_op__is_32bit \spr_main_spr_op__is_32bit - connect \ra \spr_main_ra - connect \spr1 \spr_main_spr1 - connect \fast1 \spr_main_fast1 - connect \xer_so \spr_main_xer_so - connect \xer_ov \spr_main_xer_ov - connect \xer_ca \spr_main_xer_ca - connect \muxid$1 \spr_main_muxid$11 - connect \spr_op__insn_type$2 \spr_main_spr_op__insn_type$12 - connect \spr_op__fn_unit$3 \spr_main_spr_op__fn_unit$13 - connect \spr_op__insn$4 \spr_main_spr_op__insn$14 - connect \spr_op__is_32bit$5 \spr_main_spr_op__is_32bit$15 - connect \o \spr_main_o - connect \o_ok \spr_main_o_ok - connect \spr1$6 \spr_main_spr1$16 - connect \spr1_ok \spr_main_spr1_ok - connect \fast1$7 \spr_main_fast1$17 - connect \fast1_ok \spr_main_fast1_ok - connect \xer_so$8 \spr_main_xer_so$18 - connect \xer_so_ok \spr_main_xer_so_ok - connect \xer_ov$9 \spr_main_xer_ov$19 - connect \xer_ov_ok \spr_main_xer_ov_ok - connect \xer_ca$10 \spr_main_xer_ca$20 - connect \xer_ca_ok \spr_main_xer_ca_ok - end - process $group_0 - assign \spr_main_muxid 2'00 - assign \spr_main_muxid \muxid - sync init - end - process $group_1 - assign \spr_main_spr_op__insn_type 7'0000000 - assign \spr_main_spr_op__fn_unit 11'00000000000 - assign \spr_main_spr_op__insn 32'00000000000000000000000000000000 - assign \spr_main_spr_op__is_32bit 1'0 - assign { \spr_main_spr_op__is_32bit \spr_main_spr_op__insn \spr_main_spr_op__fn_unit \spr_main_spr_op__insn_type } { \spr_op__is_32bit \spr_op__insn \spr_op__fn_unit \spr_op__insn_type } - sync init - end - process $group_5 - assign \spr_main_ra 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \spr_main_ra \ra - sync init - end - process $group_6 - assign \spr_main_spr1 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \spr_main_spr1 \spr1 - sync init - end - process $group_7 - assign \spr_main_fast1 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \spr_main_fast1 \fast1 - sync init - end - process $group_8 - assign \spr_main_xer_so 1'0 - assign \spr_main_xer_so \xer_so - sync init - end - process $group_9 - assign \spr_main_xer_ov 2'00 - assign \spr_main_xer_ov \xer_ov - sync init - end - process $group_10 - assign \spr_main_xer_ca 2'00 - assign \spr_main_xer_ca \xer_ca - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:621" - wire width 1 \p_valid_i$21 - process $group_11 - assign \p_valid_i$21 1'0 - assign \p_valid_i$21 \p_valid_i - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:619" - wire width 1 \n_i_rdy_data - process $group_12 - assign \n_i_rdy_data 1'0 - assign \n_i_rdy_data \n_ready_i - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" - wire width 1 \p_valid_i_p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" - wire width 1 $22 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" - cell $and $23 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \p_valid_i$21 - connect \B \p_ready_o - connect \Y $22 - end - process $group_13 - assign \p_valid_i_p_ready_o 1'0 - assign \p_valid_i_p_ready_o $22 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \muxid$24 - process $group_14 - assign \muxid$24 2'00 - assign \muxid$24 \spr_main_muxid$11 - sync init - end - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \spr_op__insn_type$25 - attribute \enum_base_type "Function" - attribute \enum_value_00000000000 "NONE" - attribute \enum_value_00000000010 "ALU" - attribute \enum_value_00000000100 "LDST" - attribute \enum_value_00000001000 "SHIFT_ROT" - attribute \enum_value_00000010000 "LOGICAL" - attribute \enum_value_00000100000 "BRANCH" - attribute \enum_value_00001000000 "CR" - attribute \enum_value_00010000000 "TRAP" - attribute \enum_value_00100000000 "MUL" - attribute \enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 \spr_op__fn_unit$26 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \spr_op__insn$27 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \spr_op__is_32bit$28 - process $group_15 - assign \spr_op__insn_type$25 7'0000000 - assign \spr_op__fn_unit$26 11'00000000000 - assign \spr_op__insn$27 32'00000000000000000000000000000000 - assign \spr_op__is_32bit$28 1'0 - assign { \spr_op__is_32bit$28 \spr_op__insn$27 \spr_op__fn_unit$26 \spr_op__insn_type$25 } { \spr_main_spr_op__is_32bit$15 \spr_main_spr_op__insn$14 \spr_main_spr_op__fn_unit$13 \spr_main_spr_op__insn_type$12 } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 \o$29 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \o_ok$30 - process $group_19 - assign \o$29 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \o_ok$30 1'0 - assign { \o_ok$30 \o$29 } { \spr_main_o_ok \spr_main_o } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 \spr1$31 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \spr1_ok$32 - process $group_21 - assign \spr1$31 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \spr1_ok$32 1'0 - assign { \spr1_ok$32 \spr1$31 } { \spr_main_spr1_ok \spr_main_spr1$16 } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 \fast1$33 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \fast1_ok$34 - process $group_23 - assign \fast1$33 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \fast1_ok$34 1'0 - assign { \fast1_ok$34 \fast1$33 } { \spr_main_fast1_ok \spr_main_fast1$17 } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \xer_so$35 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \xer_so_ok$36 - process $group_25 - assign \xer_so$35 1'0 - assign \xer_so_ok$36 1'0 - assign { \xer_so_ok$36 \xer_so$35 } { \spr_main_xer_so_ok \spr_main_xer_so$18 } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 2 \xer_ov$37 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \xer_ov_ok$38 - process $group_27 - assign \xer_ov$37 2'00 - assign \xer_ov_ok$38 1'0 - assign { \xer_ov_ok$38 \xer_ov$37 } { \spr_main_xer_ov_ok \spr_main_xer_ov$19 } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 2 \xer_ca$39 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \xer_ca_ok$40 - process $group_29 - assign \xer_ca$39 2'00 - assign \xer_ca_ok$40 1'0 - assign { \xer_ca_ok$40 \xer_ca$39 } { \spr_main_xer_ca_ok \spr_main_xer_ca$20 } - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615" - wire width 1 \r_busy - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615" - wire width 1 \r_busy$next - process $group_31 - assign \r_busy$next \r_busy - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign \r_busy$next 1'1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign \r_busy$next 1'0 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \r_busy$next 1'0 - end - sync init - update \r_busy 1'0 - sync posedge \coresync_clk - update \r_busy \r_busy$next - end - process $group_32 - assign \muxid$1$next \muxid$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign \muxid$1$next \muxid$24 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign \muxid$1$next \muxid$24 - end - sync init - update \muxid$1 2'00 - sync posedge \coresync_clk - update \muxid$1 \muxid$1$next - end - process $group_33 - assign \spr_op__insn_type$2$next \spr_op__insn_type$2 - assign \spr_op__fn_unit$3$next \spr_op__fn_unit$3 - assign \spr_op__insn$4$next \spr_op__insn$4 - assign \spr_op__is_32bit$5$next \spr_op__is_32bit$5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign { \spr_op__is_32bit$5$next \spr_op__insn$4$next \spr_op__fn_unit$3$next \spr_op__insn_type$2$next } { \spr_op__is_32bit$28 \spr_op__insn$27 \spr_op__fn_unit$26 \spr_op__insn_type$25 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign { \spr_op__is_32bit$5$next \spr_op__insn$4$next \spr_op__fn_unit$3$next \spr_op__insn_type$2$next } { \spr_op__is_32bit$28 \spr_op__insn$27 \spr_op__fn_unit$26 \spr_op__insn_type$25 } - end - sync init - update \spr_op__insn_type$2 7'0000000 - update \spr_op__fn_unit$3 11'00000000000 - update \spr_op__insn$4 32'00000000000000000000000000000000 - update \spr_op__is_32bit$5 1'0 - sync posedge \coresync_clk - update \spr_op__insn_type$2 \spr_op__insn_type$2$next - update \spr_op__fn_unit$3 \spr_op__fn_unit$3$next - update \spr_op__insn$4 \spr_op__insn$4$next - update \spr_op__is_32bit$5 \spr_op__is_32bit$5$next - end - process $group_37 - assign \o$next \o - assign \o_ok$next \o_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign { \o_ok$next \o$next } { \o_ok$30 \o$29 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign { \o_ok$next \o$next } { \o_ok$30 \o$29 } - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \o_ok$next 1'0 - end - sync init - update \o 64'0000000000000000000000000000000000000000000000000000000000000000 - update \o_ok 1'0 - sync posedge \coresync_clk - update \o \o$next - update \o_ok \o_ok$next - end - process $group_39 - assign \spr1$6$next \spr1$6 - assign \spr1_ok$next \spr1_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign { \spr1_ok$next \spr1$6$next } { \spr1_ok$32 \spr1$31 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign { \spr1_ok$next \spr1$6$next } { \spr1_ok$32 \spr1$31 } - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \spr1_ok$next 1'0 - end - sync init - update \spr1$6 64'0000000000000000000000000000000000000000000000000000000000000000 - update \spr1_ok 1'0 - sync posedge \coresync_clk - update \spr1$6 \spr1$6$next - update \spr1_ok \spr1_ok$next - end - process $group_41 - assign \fast1$7$next \fast1$7 - assign \fast1_ok$next \fast1_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign { \fast1_ok$next \fast1$7$next } { \fast1_ok$34 \fast1$33 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign { \fast1_ok$next \fast1$7$next } { \fast1_ok$34 \fast1$33 } - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \fast1_ok$next 1'0 - end - sync init - update \fast1$7 64'0000000000000000000000000000000000000000000000000000000000000000 - update \fast1_ok 1'0 - sync posedge \coresync_clk - update \fast1$7 \fast1$7$next - update \fast1_ok \fast1_ok$next - end - process $group_43 - assign \xer_so$8$next \xer_so$8 - assign \xer_so_ok$next \xer_so_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign { \xer_so_ok$next \xer_so$8$next } { \xer_so_ok$36 \xer_so$35 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign { \xer_so_ok$next \xer_so$8$next } { \xer_so_ok$36 \xer_so$35 } - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \xer_so_ok$next 1'0 - end - sync init - update \xer_so$8 1'0 - update \xer_so_ok 1'0 - sync posedge \coresync_clk - update \xer_so$8 \xer_so$8$next - update \xer_so_ok \xer_so_ok$next - end - process $group_45 - assign \xer_ov$9$next \xer_ov$9 - assign \xer_ov_ok$next \xer_ov_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign { \xer_ov_ok$next \xer_ov$9$next } { \xer_ov_ok$38 \xer_ov$37 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign { \xer_ov_ok$next \xer_ov$9$next } { \xer_ov_ok$38 \xer_ov$37 } - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \xer_ov_ok$next 1'0 - end - sync init - update \xer_ov$9 2'00 - update \xer_ov_ok 1'0 - sync posedge \coresync_clk - update \xer_ov$9 \xer_ov$9$next - update \xer_ov_ok \xer_ov_ok$next - end - process $group_47 - assign \xer_ca$10$next \xer_ca$10 - assign \xer_ca_ok$next \xer_ca_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign { \xer_ca_ok$next \xer_ca$10$next } { \xer_ca_ok$40 \xer_ca$39 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign { \xer_ca_ok$next \xer_ca$10$next } { \xer_ca_ok$40 \xer_ca$39 } - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \xer_ca_ok$next 1'0 - end - sync init - update \xer_ca$10 2'00 - update \xer_ca_ok 1'0 - sync posedge \coresync_clk - update \xer_ca$10 \xer_ca$10$next - update \xer_ca_ok \xer_ca_ok$next - end - process $group_49 - assign \n_valid_o 1'0 - assign \n_valid_o \r_busy - sync init - end - process $group_50 - assign \p_ready_o 1'0 - assign \p_ready_o \n_i_rdy_data - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.spr0.alu_spr0" -module \alu_spr0 - attribute \src "simple/issuer.py:141" - wire width 1 input 0 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 1 \o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 2 \xer_ca_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 3 \xer_ov_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 4 \xer_so_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 5 \fast1_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 6 \spr1_ok - attribute \src "simple/issuer.py:141" - wire width 1 input 7 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" - wire width 1 output 8 \n_valid_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" - wire width 1 input 9 \n_ready_i - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 input 10 \spr_op__insn_type - attribute \enum_base_type "Function" - attribute \enum_value_00000000000 "NONE" - attribute \enum_value_00000000010 "ALU" - attribute \enum_value_00000000100 "LDST" - attribute \enum_value_00000001000 "SHIFT_ROT" - attribute \enum_value_00000010000 "LOGICAL" - attribute \enum_value_00000100000 "BRANCH" - attribute \enum_value_00001000000 "CR" - attribute \enum_value_00010000000 "TRAP" - attribute \enum_value_00100000000 "MUL" - attribute \enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 input 11 \spr_op__fn_unit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 input 12 \spr_op__insn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 13 \spr_op__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 output 14 \o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 output 15 \spr1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 output 16 \fast1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 17 \xer_so - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 2 output 18 \xer_ov - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 2 output 19 \xer_ca - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 20 \ra - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 21 \spr1$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 22 \fast1$2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 1 input 23 \xer_so$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 2 input 24 \xer_ov$4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 2 input 25 \xer_ca$5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" - wire width 1 input 26 \p_valid_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" - wire width 1 output 27 \p_ready_o - cell \p$59 \p - connect \p_valid_i \p_valid_i - connect \p_ready_o \p_ready_o - end - cell \n$60 \n - connect \n_valid_o \n_valid_o - connect \n_ready_i \n_ready_i - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" - wire width 1 \pipe_p_valid_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" - wire width 1 \pipe_p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \pipe_muxid - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute 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"OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \pipe_spr_op__insn_type - attribute \enum_base_type "Function" - attribute \enum_value_00000000000 "NONE" - attribute \enum_value_00000000010 "ALU" - attribute \enum_value_00000000100 "LDST" - attribute \enum_value_00000001000 "SHIFT_ROT" - attribute \enum_value_00000010000 "LOGICAL" - attribute \enum_value_00000100000 "BRANCH" - attribute \enum_value_00001000000 "CR" - attribute \enum_value_00010000000 "TRAP" - attribute \enum_value_00100000000 "MUL" - attribute \enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 \pipe_spr_op__fn_unit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \pipe_spr_op__insn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_spr_op__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \pipe_ra - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \pipe_spr1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \pipe_fast1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 1 \pipe_xer_so - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 2 \pipe_xer_ov - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 2 \pipe_xer_ca - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" - wire width 1 \pipe_n_valid_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" - wire width 1 \pipe_n_ready_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \pipe_muxid$6 - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \pipe_spr_op__insn_type$7 - attribute \enum_base_type "Function" - attribute \enum_value_00000000000 "NONE" - attribute \enum_value_00000000010 "ALU" - attribute \enum_value_00000000100 "LDST" - attribute \enum_value_00000001000 "SHIFT_ROT" - attribute \enum_value_00000010000 "LOGICAL" - attribute \enum_value_00000100000 "BRANCH" - attribute \enum_value_00001000000 "CR" - attribute \enum_value_00010000000 "TRAP" - attribute \enum_value_00100000000 "MUL" - attribute \enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 \pipe_spr_op__fn_unit$8 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \pipe_spr_op__insn$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_spr_op__is_32bit$10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 \pipe_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \pipe_o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 \pipe_spr1$11 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \pipe_spr1_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 \pipe_fast1$12 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \pipe_fast1_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \pipe_xer_so$13 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \pipe_xer_so_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 2 \pipe_xer_ov$14 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \pipe_xer_ov_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 2 \pipe_xer_ca$15 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \pipe_xer_ca_ok - cell \pipe$61 \pipe - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \p_valid_i \pipe_p_valid_i - connect \p_ready_o \pipe_p_ready_o - connect \muxid \pipe_muxid - connect \spr_op__insn_type \pipe_spr_op__insn_type - connect \spr_op__fn_unit \pipe_spr_op__fn_unit - connect \spr_op__insn \pipe_spr_op__insn - connect \spr_op__is_32bit \pipe_spr_op__is_32bit - connect \ra \pipe_ra - connect \spr1 \pipe_spr1 - connect \fast1 \pipe_fast1 - connect \xer_so \pipe_xer_so - connect \xer_ov \pipe_xer_ov - connect \xer_ca \pipe_xer_ca - connect \n_valid_o \pipe_n_valid_o - connect \n_ready_i \pipe_n_ready_i - connect \muxid$1 \pipe_muxid$6 - connect \spr_op__insn_type$2 \pipe_spr_op__insn_type$7 - connect \spr_op__fn_unit$3 \pipe_spr_op__fn_unit$8 - connect \spr_op__insn$4 \pipe_spr_op__insn$9 - connect \spr_op__is_32bit$5 \pipe_spr_op__is_32bit$10 - connect \o \pipe_o - connect \o_ok \pipe_o_ok - connect \spr1$6 \pipe_spr1$11 - connect \spr1_ok \pipe_spr1_ok - connect \fast1$7 \pipe_fast1$12 - connect \fast1_ok \pipe_fast1_ok - connect \xer_so$8 \pipe_xer_so$13 - connect \xer_so_ok \pipe_xer_so_ok - connect \xer_ov$9 \pipe_xer_ov$14 - connect \xer_ov_ok \pipe_xer_ov_ok - connect \xer_ca$10 \pipe_xer_ca$15 - connect \xer_ca_ok \pipe_xer_ca_ok - end - process $group_0 - assign \pipe_p_valid_i 1'0 - assign \pipe_p_valid_i \p_valid_i - sync init - end - process $group_1 - assign \p_ready_o 1'0 - assign \p_ready_o \pipe_p_ready_o - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \muxid - process $group_2 - assign \pipe_muxid 2'00 - assign \pipe_muxid \muxid - sync init - end - process $group_3 - assign \pipe_spr_op__insn_type 7'0000000 - assign \pipe_spr_op__fn_unit 11'00000000000 - assign \pipe_spr_op__insn 32'00000000000000000000000000000000 - assign \pipe_spr_op__is_32bit 1'0 - assign { \pipe_spr_op__is_32bit \pipe_spr_op__insn \pipe_spr_op__fn_unit \pipe_spr_op__insn_type } { \spr_op__is_32bit \spr_op__insn \spr_op__fn_unit \spr_op__insn_type } - sync init - end - process $group_7 - assign \pipe_ra 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \pipe_ra \ra - sync init - end - process $group_8 - assign \pipe_spr1 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \pipe_spr1 \spr1$1 - sync init - end - process $group_9 - assign \pipe_fast1 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \pipe_fast1 \fast1$2 - sync init - end - process $group_10 - assign \pipe_xer_so 1'0 - assign \pipe_xer_so \xer_so$3 - sync init - end - process $group_11 - assign \pipe_xer_ov 2'00 - assign \pipe_xer_ov \xer_ov$4 - sync init - end - process $group_12 - assign \pipe_xer_ca 2'00 - assign \pipe_xer_ca \xer_ca$5 - sync init - end - process $group_13 - assign \n_valid_o 1'0 - assign \n_valid_o \pipe_n_valid_o - sync init - end - process $group_14 - assign \pipe_n_ready_i 1'0 - assign \pipe_n_ready_i \n_ready_i - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \muxid$16 - process $group_15 - assign \muxid$16 2'00 - assign \muxid$16 \pipe_muxid$6 - sync init - end - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \spr_op__insn_type$17 - attribute \enum_base_type "Function" - attribute \enum_value_00000000000 "NONE" - attribute \enum_value_00000000010 "ALU" - attribute \enum_value_00000000100 "LDST" - attribute \enum_value_00000001000 "SHIFT_ROT" - attribute \enum_value_00000010000 "LOGICAL" - attribute \enum_value_00000100000 "BRANCH" - attribute \enum_value_00001000000 "CR" - attribute \enum_value_00010000000 "TRAP" - attribute \enum_value_00100000000 "MUL" - attribute \enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 \spr_op__fn_unit$18 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \spr_op__insn$19 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \spr_op__is_32bit$20 - process $group_16 - assign \spr_op__insn_type$17 7'0000000 - assign \spr_op__fn_unit$18 11'00000000000 - assign \spr_op__insn$19 32'00000000000000000000000000000000 - assign \spr_op__is_32bit$20 1'0 - assign { \spr_op__is_32bit$20 \spr_op__insn$19 \spr_op__fn_unit$18 \spr_op__insn_type$17 } { \pipe_spr_op__is_32bit$10 \pipe_spr_op__insn$9 \pipe_spr_op__fn_unit$8 \pipe_spr_op__insn_type$7 } - sync init - end - process $group_20 - assign \o 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \o_ok 1'0 - assign { \o_ok \o } { \pipe_o_ok \pipe_o } - sync init - end - process $group_22 - assign \spr1 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \spr1_ok 1'0 - assign { \spr1_ok \spr1 } { \pipe_spr1_ok \pipe_spr1$11 } - sync init - end - process $group_24 - assign \fast1 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \fast1_ok 1'0 - assign { \fast1_ok \fast1 } { \pipe_fast1_ok \pipe_fast1$12 } - sync init - end - process $group_26 - assign \xer_so 1'0 - assign \xer_so_ok 1'0 - assign { \xer_so_ok \xer_so } { \pipe_xer_so_ok \pipe_xer_so$13 } - sync init - end - process $group_28 - assign \xer_ov 2'00 - assign \xer_ov_ok 1'0 - assign { \xer_ov_ok \xer_ov } { \pipe_xer_ov_ok \pipe_xer_ov$14 } - sync init - end - process $group_30 - assign \xer_ca 2'00 - assign \xer_ca_ok 1'0 - assign { \xer_ca_ok \xer_ca } { \pipe_xer_ca_ok \pipe_xer_ca$15 } - sync init - end - connect \muxid 2'00 -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.spr0.src_l" -module \src_l$64 - attribute \src "simple/issuer.py:141" - wire width 1 input 0 \coresync_clk - attribute \src "simple/issuer.py:141" - wire width 1 input 1 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 6 input 2 \s_src - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 6 input 3 \r_src - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire width 6 output 4 \q_src - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire width 6 \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire width 6 \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 6 $1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \Y_WIDTH 6 - connect \A \r_src - connect \Y $1 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 6 $3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $4 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 6 - connect \A \q_int - connect \B $1 - connect \Y $3 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 6 $5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $6 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 6 - connect \A $3 - connect \B \s_src - connect \Y $5 - end - process $group_0 - assign \q_int$next \q_int - assign \q_int$next $5 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \q_int$next 6'000000 - end - sync init - update \q_int 6'000000 - sync posedge \coresync_clk - update \q_int \q_int$next - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 6 $7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $8 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \Y_WIDTH 6 - connect \A \r_src - connect \Y $7 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 6 $9 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $10 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 6 - connect \A \q_int - connect \B $7 - connect \Y $9 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 6 $11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $12 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 6 - connect \A $9 - connect \B \s_src - connect \Y $11 - end - process $group_1 - assign \q_src 6'000000 - assign \q_src $11 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" - wire width 6 \qn_src - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - wire width 6 $13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $14 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \Y_WIDTH 6 - connect \A \q_src - connect \Y $13 - end - process $group_2 - assign \qn_src 6'000000 - assign \qn_src $13 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" - wire width 6 \qlq_src - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - wire width 6 $15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $16 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 6 - connect \A \q_src - connect \B \q_int - connect \Y $15 - end - process $group_3 - assign \qlq_src 6'000000 - assign \qlq_src $15 - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.spr0.opc_l" -module \opc_l$65 - attribute \src "simple/issuer.py:141" - wire width 1 input 0 \coresync_clk - attribute \src "simple/issuer.py:141" - wire width 1 input 1 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 1 input 2 \s_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 1 input 3 \r_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire width 1 output 4 \q_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire width 1 \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire width 1 \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_opc - connect \Y $1 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 1 $3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $4 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B $1 - connect \Y $3 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 1 $5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $6 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $3 - connect \B \s_opc - connect \Y $5 - end - process $group_0 - assign \q_int$next \q_int - assign \q_int$next $5 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \q_int$next 1'0 - end - sync init - update \q_int 1'0 - sync posedge \coresync_clk - update \q_int \q_int$next - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 1 $7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $8 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_opc - connect \Y $7 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 1 $9 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $10 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B $7 - connect \Y $9 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 1 $11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $12 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $9 - connect \B \s_opc - connect \Y $11 - end - process $group_1 - assign \q_opc 1'0 - assign \q_opc $11 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" - wire width 1 \qn_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - wire width 1 $13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $14 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_opc - connect \Y $13 - end - process $group_2 - assign \qn_opc 1'0 - assign \qn_opc $13 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" - wire width 1 \qlq_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - wire width 1 $15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $16 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_opc - connect \B \q_int - connect \Y $15 - end - process $group_3 - assign \qlq_opc 1'0 - assign \qlq_opc $15 - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.spr0.req_l" -module \req_l$66 - attribute \src "simple/issuer.py:141" - wire width 1 input 0 \coresync_clk - attribute \src "simple/issuer.py:141" - wire width 1 input 1 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire width 6 output 2 \q_req - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 6 input 3 \s_req - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 6 input 4 \r_req - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire width 6 \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire width 6 \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 6 $1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \Y_WIDTH 6 - connect \A \r_req - connect \Y $1 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 6 $3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $4 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 6 - connect \A \q_int - connect \B $1 - connect \Y $3 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 6 $5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $6 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 6 - connect \A $3 - connect \B \s_req - connect \Y $5 - end - process $group_0 - assign \q_int$next \q_int - assign \q_int$next $5 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \q_int$next 6'000000 - end - sync init - update \q_int 6'000000 - sync posedge \coresync_clk - update \q_int \q_int$next - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 6 $7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $8 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \Y_WIDTH 6 - connect \A \r_req - connect \Y $7 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 6 $9 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $10 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 6 - connect \A \q_int - connect \B $7 - connect \Y $9 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 6 $11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $12 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 6 - connect \A $9 - connect \B \s_req - connect \Y $11 - end - process $group_1 - assign \q_req 6'000000 - assign \q_req $11 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" - wire width 6 \qn_req - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - wire width 6 $13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $14 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \Y_WIDTH 6 - connect \A \q_req - connect \Y $13 - end - process $group_2 - assign \qn_req 6'000000 - assign \qn_req $13 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" - wire width 6 \qlq_req - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - wire width 6 $15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $16 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 6 - connect \A \q_req - connect \B \q_int - connect \Y $15 - end - process $group_3 - assign \qlq_req 6'000000 - assign \qlq_req $15 - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.spr0.rst_l" -module \rst_l$67 - attribute \src "simple/issuer.py:141" - wire width 1 input 0 \coresync_clk - attribute \src "simple/issuer.py:141" - wire width 1 input 1 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 1 input 2 \s_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 1 input 3 \r_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire width 1 \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire width 1 \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_rst - connect \Y $1 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 1 $3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $4 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B $1 - connect \Y $3 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 1 $5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $6 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $3 - connect \B \s_rst - connect \Y $5 - end - process $group_0 - assign \q_int$next \q_int - assign \q_int$next $5 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \q_int$next 1'0 - end - sync init - update \q_int 1'0 - sync posedge \coresync_clk - update \q_int \q_int$next - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire width 1 \q_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 1 $7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $8 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_rst - connect \Y $7 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 1 $9 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $10 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B $7 - connect \Y $9 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 1 $11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $12 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $9 - connect \B \s_rst - connect \Y $11 - end - process $group_1 - assign \q_rst 1'0 - assign \q_rst $11 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" - wire width 1 \qn_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - wire width 1 $13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $14 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_rst - connect \Y $13 - end - process $group_2 - assign \qn_rst 1'0 - assign \qn_rst $13 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" - wire width 1 \qlq_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - wire width 1 $15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $16 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_rst - connect \B \q_int - connect \Y $15 - end - process $group_3 - assign \qlq_rst 1'0 - assign \qlq_rst $15 - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.spr0.rok_l" -module \rok_l$68 - attribute \src "simple/issuer.py:141" - wire width 1 input 0 \coresync_clk - attribute \src "simple/issuer.py:141" - wire width 1 input 1 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire width 1 output 2 \q_rdok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 1 input 3 \s_rdok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 1 input 4 \r_rdok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire width 1 \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire width 1 \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_rdok - connect \Y $1 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 1 $3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $4 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B $1 - connect \Y $3 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 1 $5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $6 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $3 - connect \B \s_rdok - connect \Y $5 - end - process $group_0 - assign \q_int$next \q_int - assign \q_int$next $5 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \q_int$next 1'0 - end - sync init - update \q_int 1'0 - sync posedge \coresync_clk - update \q_int \q_int$next - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 1 $7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $8 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_rdok - connect \Y $7 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 1 $9 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $10 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B $7 - connect \Y $9 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 1 $11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $12 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $9 - connect \B \s_rdok - connect \Y $11 - end - process $group_1 - assign \q_rdok 1'0 - assign \q_rdok $11 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" - wire width 1 \qn_rdok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - wire width 1 $13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $14 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_rdok - connect \Y $13 - end - process $group_2 - assign \qn_rdok 1'0 - assign \qn_rdok $13 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" - wire width 1 \qlq_rdok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - wire width 1 $15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $16 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_rdok - connect \B \q_int - connect \Y $15 - end - process $group_3 - assign \qlq_rdok 1'0 - assign \qlq_rdok $15 - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.spr0.alui_l" -module \alui_l$69 - attribute \src "simple/issuer.py:141" - wire width 1 input 0 \coresync_clk - attribute \src "simple/issuer.py:141" - wire width 1 input 1 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire width 1 output 2 \q_alui - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 1 input 3 \r_alui - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 1 input 4 \s_alui - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire width 1 \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire width 1 \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_alui - connect \Y $1 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 1 $3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $4 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B $1 - connect \Y $3 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 1 $5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $6 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $3 - connect \B \s_alui - connect \Y $5 - end - process $group_0 - assign \q_int$next \q_int - assign \q_int$next $5 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \q_int$next 1'0 - end - sync init - update \q_int 1'0 - sync posedge \coresync_clk - update \q_int \q_int$next - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 1 $7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $8 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_alui - connect \Y $7 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 1 $9 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $10 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B $7 - connect \Y $9 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 1 $11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $12 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $9 - connect \B \s_alui - connect \Y $11 - end - process $group_1 - assign \q_alui 1'0 - assign \q_alui $11 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" - wire width 1 \qn_alui - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - wire width 1 $13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $14 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_alui - connect \Y $13 - end - process $group_2 - assign \qn_alui 1'0 - assign \qn_alui $13 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" - wire width 1 \qlq_alui - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - wire width 1 $15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $16 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_alui - connect \B \q_int - connect \Y $15 - end - process $group_3 - assign \qlq_alui 1'0 - assign \qlq_alui $15 - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.spr0.alu_l" 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"/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 1 $3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $4 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B $1 - connect \Y $3 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 1 $5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $6 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $3 - connect \B \s_alu - connect \Y $5 - end - process $group_0 - assign \q_int$next \q_int - assign \q_int$next $5 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \q_int$next 1'0 - end - sync init - update \q_int 1'0 - sync posedge \coresync_clk - update \q_int \q_int$next - end - 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\enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 input 2 \oper_i_alu_spr0__fn_unit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 input 3 \oper_i_alu_spr0__insn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 4 \oper_i_alu_spr0__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:100" - wire width 1 input 5 \cu_issue_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107" - wire width 1 output 6 \cu_busy_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96" - wire width 6 input 7 \cu_rdmaskn_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 6 output 8 \cu_rd__rel_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 6 input 9 \cu_rd__go_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 64 input 10 \src1_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 1 input 11 \src4_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 2 input 12 \src6_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 2 input 13 \src5_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 64 input 14 \src3_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 64 input 15 \src2_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 16 \o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 6 output 17 \cu_wr__rel_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 6 input 18 \cu_wr__go_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" - wire width 64 output 19 \dest1_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 20 \xer_ca_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" - wire width 2 output 21 \dest6_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 22 \xer_ov_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" - wire width 2 output 23 \dest5_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 24 \xer_so_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" - wire width 1 output 25 \dest4_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 26 \fast1_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" - wire width 64 output 27 \dest3_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 28 \spr1_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" - wire width 64 output 29 \dest2_o - attribute \src "simple/issuer.py:141" - wire width 1 input 30 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" - wire width 1 \alu_spr0_n_valid_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" - wire width 1 \alu_spr0_n_ready_i - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \alu_spr0_spr_op__insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \alu_spr0_spr_op__insn_type$next - attribute \enum_base_type "Function" - attribute \enum_value_00000000000 "NONE" - attribute \enum_value_00000000010 "ALU" - attribute \enum_value_00000000100 "LDST" - attribute \enum_value_00000001000 "SHIFT_ROT" - attribute \enum_value_00000010000 "LOGICAL" - attribute \enum_value_00000100000 "BRANCH" - attribute \enum_value_00001000000 "CR" - attribute \enum_value_00010000000 "TRAP" - attribute \enum_value_00100000000 "MUL" - attribute \enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 \alu_spr0_spr_op__fn_unit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 \alu_spr0_spr_op__fn_unit$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \alu_spr0_spr_op__insn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \alu_spr0_spr_op__insn$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \alu_spr0_spr_op__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \alu_spr0_spr_op__is_32bit$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 \alu_spr0_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 \alu_spr0_spr1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 \alu_spr0_fast1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \alu_spr0_xer_so - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 2 \alu_spr0_xer_ov - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 2 \alu_spr0_xer_ca - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \alu_spr0_ra - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \alu_spr0_spr1$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \alu_spr0_fast1$2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 1 \alu_spr0_xer_so$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 2 \alu_spr0_xer_ov$4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 2 \alu_spr0_xer_ca$5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" - wire width 1 \alu_spr0_p_valid_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" - wire width 1 \alu_spr0_p_ready_o - cell \alu_spr0 \alu_spr0 - connect \coresync_clk \coresync_clk - connect \o_ok \o_ok - connect \xer_ca_ok \xer_ca_ok - connect \xer_ov_ok \xer_ov_ok - connect \xer_so_ok \xer_so_ok - connect \fast1_ok \fast1_ok - connect \spr1_ok \spr1_ok - connect \coresync_rst \coresync_rst - connect \n_valid_o \alu_spr0_n_valid_o - connect \n_ready_i \alu_spr0_n_ready_i - connect \spr_op__insn_type \alu_spr0_spr_op__insn_type - connect \spr_op__fn_unit \alu_spr0_spr_op__fn_unit - connect \spr_op__insn \alu_spr0_spr_op__insn - connect \spr_op__is_32bit \alu_spr0_spr_op__is_32bit - connect \o \alu_spr0_o - connect \spr1 \alu_spr0_spr1 - connect \fast1 \alu_spr0_fast1 - connect \xer_so \alu_spr0_xer_so - connect \xer_ov \alu_spr0_xer_ov - connect \xer_ca \alu_spr0_xer_ca - connect \ra \alu_spr0_ra - connect \spr1$1 \alu_spr0_spr1$1 - connect \fast1$2 \alu_spr0_fast1$2 - connect \xer_so$3 \alu_spr0_xer_so$3 - connect \xer_ov$4 \alu_spr0_xer_ov$4 - connect \xer_ca$5 \alu_spr0_xer_ca$5 - connect \p_valid_i \alu_spr0_p_valid_i - connect \p_ready_o \alu_spr0_p_ready_o - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 6 \src_l_s_src - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 6 \src_l_s_src$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 6 \src_l_r_src - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 6 \src_l_r_src$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire width 6 \src_l_q_src - cell \src_l$64 \src_l - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \s_src \src_l_s_src - connect \r_src \src_l_r_src - connect \q_src \src_l_q_src - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 1 \opc_l_s_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 1 \opc_l_s_opc$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 1 \opc_l_r_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 1 \opc_l_r_opc$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire width 1 \opc_l_q_opc - cell \opc_l$65 \opc_l - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \s_opc \opc_l_s_opc - connect \r_opc \opc_l_r_opc - connect \q_opc \opc_l_q_opc - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire width 6 \req_l_q_req - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 6 \req_l_s_req - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 6 \req_l_s_req$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 6 \req_l_r_req - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 6 \req_l_r_req$next - cell \req_l$66 \req_l - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \q_req \req_l_q_req - connect \s_req \req_l_s_req - connect \r_req \req_l_r_req - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 1 \rst_l_s_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 1 \rst_l_s_rst$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 1 \rst_l_r_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 1 \rst_l_r_rst$next - cell \rst_l$67 \rst_l - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \s_rst \rst_l_s_rst - connect \r_rst \rst_l_r_rst - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire width 1 \rok_l_q_rdok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 1 \rok_l_s_rdok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 1 \rok_l_s_rdok$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 1 \rok_l_r_rdok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 1 \rok_l_r_rdok$next - cell \rok_l$68 \rok_l - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \q_rdok \rok_l_q_rdok - connect \s_rdok \rok_l_s_rdok - connect \r_rdok \rok_l_r_rdok - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire width 1 \alui_l_q_alui - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 1 \alui_l_r_alui - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 1 \alui_l_r_alui$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 1 \alui_l_s_alui - cell \alui_l$69 \alui_l - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \q_alui \alui_l_q_alui - connect \r_alui \alui_l_r_alui - connect \s_alui \alui_l_s_alui - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire width 1 \alu_l_q_alu - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 1 \alu_l_r_alu - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 1 \alu_l_r_alu$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 1 \alu_l_s_alu - cell \alu_l$70 \alu_l - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \q_alu \alu_l_q_alu - connect \r_alu \alu_l_r_alu - connect \s_alu \alu_l_s_alu - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:187" - wire width 1 \all_rd - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:188" - wire width 1 $6 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:188" - cell $and $7 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cu_busy_o - connect \B \rok_l_q_rdok - connect \Y $6 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - wire width 1 $8 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - wire width 6 $9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - cell $not $10 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \Y_WIDTH 6 - connect \A \cu_rd__rel_o - connect \Y $9 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - wire width 6 $11 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - cell $or $12 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 6 - connect \A $9 - connect \B \cu_rd__go_i - connect \Y $11 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - cell $reduce_and $13 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \Y_WIDTH 1 - connect \A $11 - connect \Y $8 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - wire width 1 $14 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - cell $and $15 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $6 - connect \B $8 - connect \Y $14 - end - process $group_0 - assign \all_rd 1'0 - assign \all_rd $14 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire width 1 \all_rd_dly - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire width 1 \all_rd_dly$next - process $group_1 - assign \all_rd_dly$next \all_rd_dly - assign \all_rd_dly$next \all_rd - sync init - update \all_rd_dly 1'0 - sync posedge \coresync_clk - update \all_rd_dly \all_rd_dly$next - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" - wire width 1 \all_rd_rise - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - wire width 1 $16 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $not $17 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \all_rd_dly - connect \Y $16 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - wire width 1 $18 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $and $19 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \all_rd - connect \B $16 - connect \Y $18 - end - process $group_2 - assign \all_rd_rise 1'0 - assign \all_rd_rise $18 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:192" - wire width 1 \all_rd_pulse - process $group_3 - assign \all_rd_pulse 1'0 - assign \all_rd_pulse \all_rd_rise - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:196" - wire width 1 \alu_done - process $group_4 - assign \alu_done 1'0 - assign \alu_done \alu_spr0_n_valid_o - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire width 1 \alu_done_dly - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire width 1 \alu_done_dly$next - process $group_5 - assign \alu_done_dly$next \alu_done_dly - assign \alu_done_dly$next \alu_done - sync init - update \alu_done_dly 1'0 - sync posedge \coresync_clk - update \alu_done_dly \alu_done_dly$next - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" - wire width 1 \alu_done_rise - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - wire width 1 $20 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $not $21 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \alu_done_dly - connect \Y $20 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - wire width 1 $22 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $and $23 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \alu_done - connect \B $20 - connect \Y $22 - end - process $group_6 - assign \alu_done_rise 1'0 - assign \alu_done_rise $22 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:197" - wire width 1 \alu_pulse - process $group_7 - assign \alu_pulse 1'0 - assign \alu_pulse \alu_done_rise - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:198" - wire width 6 \alu_pulsem - process $group_8 - assign \alu_pulsem 6'000000 - assign \alu_pulsem { \alu_pulse \alu_pulse \alu_pulse \alu_pulse \alu_pulse \alu_pulse } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:204" - wire width 6 \prev_wr_go - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:204" - wire width 6 \prev_wr_go$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:206" - wire width 6 $24 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:206" - cell $and $25 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 6 - connect \A \cu_wr__go_i - connect \B { \cu_busy_o \cu_busy_o \cu_busy_o \cu_busy_o \cu_busy_o \cu_busy_o } - connect \Y $24 - end - process $group_9 - assign \prev_wr_go$next \prev_wr_go - assign \prev_wr_go$next $24 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \prev_wr_go$next 6'000000 - end - sync init - update \prev_wr_go 6'000000 - sync posedge \coresync_clk - update \prev_wr_go \prev_wr_go$next - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:108" - wire width 1 \cu_done_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - wire width 1 $26 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - wire width 1 $27 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - wire width 6 $28 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:97" - wire width 6 \cu_wrmask_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $not $29 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \Y_WIDTH 6 - connect \A \cu_wrmask_o - connect \Y $28 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - wire width 6 $30 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $and $31 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 6 - connect \A \cu_wr__rel_o - connect \B $28 - connect \Y $30 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $reduce_bool $32 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \Y_WIDTH 1 - connect \A $30 - connect \Y $27 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $not $33 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $27 - connect \Y $26 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - wire width 1 $34 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $and $35 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cu_busy_o - connect \B $26 - connect \Y $34 - end - process $group_10 - assign \cu_done_o 1'0 - assign \cu_done_o $34 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:211" - wire width 1 \wr_any - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" - wire width 1 $36 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" - cell $reduce_bool $37 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \Y_WIDTH 1 - connect \A \cu_wr__go_i - connect \Y $36 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" - wire width 1 $38 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" - cell $reduce_bool $39 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \Y_WIDTH 1 - connect \A \prev_wr_go - connect \Y $38 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" - wire width 1 $40 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" - cell $or $41 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $36 - connect \B $38 - connect \Y $40 - end - process $group_11 - assign \wr_any 1'0 - assign \wr_any $40 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:212" - wire width 1 \req_done - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" - wire width 1 $42 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" - cell $not $43 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \alu_spr0_n_ready_i - connect \Y $42 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" - wire width 1 $44 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" - cell $and $45 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_any - connect \B $42 - connect \Y $44 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" - wire width 6 $46 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" - cell $and $47 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 6 - connect \A \req_l_q_req - connect \B \cu_wrmask_o - connect \Y $46 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" - wire width 1 $48 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" - cell $eq $49 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $46 - connect \B 1'0 - connect \Y $48 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" - wire width 1 $50 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" - cell $and $51 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $44 - connect \B $48 - connect \Y $50 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - wire width 1 $52 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - cell $eq $53 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cu_wrmask_o - connect \B 1'0 - connect \Y $52 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - wire width 1 $54 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - cell $and $55 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $52 - connect \B \alu_spr0_n_ready_i - connect \Y $54 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - wire width 1 $56 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - cell $and $57 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $54 - connect \B \alu_spr0_n_valid_o - connect \Y $56 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - wire width 1 $58 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - cell $and $59 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $56 - connect \B \cu_busy_o - connect \Y $58 - end - process $group_12 - assign \req_done 1'0 - assign \req_done $50 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - switch { $58 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - case 1'1 - assign \req_done 1'1 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:226" - wire width 1 \reset - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:104" - wire width 1 \cu_go_die_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:230" - wire width 1 $60 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:230" - cell $or $61 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \req_done - connect \B \cu_go_die_i - connect \Y $60 - end - process $group_13 - assign \reset 1'0 - assign \reset $60 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:227" - wire width 1 \rst_r - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:231" - wire width 1 $62 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:231" - cell $or $63 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cu_issue_i - connect \B \cu_go_die_i - connect \Y $62 - end - process $group_14 - assign \rst_r 1'0 - assign \rst_r $62 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:228" - wire width 6 \reset_w - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:232" - wire width 6 $64 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:232" - cell $or $65 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 6 - connect \A \cu_wr__go_i - connect \B { \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i } - connect \Y $64 - end - process $group_15 - assign \reset_w 6'000000 - assign \reset_w $64 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:229" - wire width 6 \reset_r - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:233" - wire width 6 $66 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:233" - cell $or $67 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 6 - connect \A \cu_rd__go_i - connect \B { \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i } - connect \Y $66 - end - process $group_16 - assign \reset_r 6'000000 - assign \reset_r $66 - sync init - end - process $group_17 - assign \rok_l_s_rdok$next \rok_l_s_rdok - assign \rok_l_s_rdok$next \cu_issue_i - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \rok_l_s_rdok$next 1'0 - end - sync init - update \rok_l_s_rdok 1'0 - sync posedge \coresync_clk - update \rok_l_s_rdok \rok_l_s_rdok$next - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:237" - wire width 1 $68 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:237" - cell $and $69 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \alu_spr0_n_valid_o - connect \B \cu_busy_o - connect \Y $68 - end - process $group_18 - assign \rok_l_r_rdok$next \rok_l_r_rdok - assign \rok_l_r_rdok$next $68 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \rok_l_r_rdok$next 1'1 - end - sync init - update \rok_l_r_rdok 1'1 - sync posedge \coresync_clk - update \rok_l_r_rdok \rok_l_r_rdok$next - end - process $group_19 - assign \rst_l_s_rst$next \rst_l_s_rst - assign \rst_l_s_rst$next \all_rd - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \rst_l_s_rst$next 1'0 - end - sync init - update \rst_l_s_rst 1'0 - sync posedge \coresync_clk - update \rst_l_s_rst \rst_l_s_rst$next - end - process $group_20 - assign \rst_l_r_rst$next \rst_l_r_rst - assign \rst_l_r_rst$next \rst_r - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \rst_l_r_rst$next 1'1 - end - sync init - update \rst_l_r_rst 1'1 - sync posedge \coresync_clk - update \rst_l_r_rst \rst_l_r_rst$next - end - process $group_21 - assign \opc_l_s_opc$next \opc_l_s_opc - assign \opc_l_s_opc$next \cu_issue_i - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \opc_l_s_opc$next 1'0 - end - sync init - update \opc_l_s_opc 1'0 - sync posedge \coresync_clk - update \opc_l_s_opc \opc_l_s_opc$next - end - process $group_22 - assign \opc_l_r_opc$next \opc_l_r_opc - assign \opc_l_r_opc$next \req_done - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \opc_l_r_opc$next 1'1 - end - sync init - update \opc_l_r_opc 1'1 - sync posedge \coresync_clk - update \opc_l_r_opc \opc_l_r_opc$next - end - process $group_23 - assign \src_l_s_src$next \src_l_s_src - assign \src_l_s_src$next { \cu_issue_i \cu_issue_i \cu_issue_i \cu_issue_i \cu_issue_i \cu_issue_i } - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \src_l_s_src$next 6'000000 - end - sync init - update \src_l_s_src 6'000000 - sync posedge \coresync_clk - update \src_l_s_src \src_l_s_src$next - end - process $group_24 - assign \src_l_r_src$next \src_l_r_src - assign \src_l_r_src$next \reset_r - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \src_l_r_src$next 6'111111 - end - sync init - update \src_l_r_src 6'111111 - sync posedge \coresync_clk - update \src_l_r_src \src_l_r_src$next - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:252" - wire width 6 $70 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:252" - cell $and $71 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 6 - connect \A \alu_pulsem - connect \B \cu_wrmask_o - connect \Y $70 - end - process $group_25 - assign \req_l_s_req$next \req_l_s_req - assign \req_l_s_req$next $70 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \req_l_s_req$next 6'000000 - end - sync init - update \req_l_s_req 6'000000 - sync posedge \coresync_clk - update \req_l_s_req \req_l_s_req$next - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:253" - wire width 6 $72 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:253" - cell $or $73 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 6 - connect \A \reset_w - connect \B \prev_wr_go - connect \Y $72 - end - process $group_26 - assign \req_l_r_req$next \req_l_r_req - assign \req_l_r_req$next $72 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \req_l_r_req$next 6'111111 - end - sync init - update \req_l_r_req 6'111111 - sync posedge \coresync_clk - update \req_l_r_req \req_l_r_req$next - end - process $group_27 - assign \alu_spr0_spr_op__insn_type$next \alu_spr0_spr_op__insn_type - assign \alu_spr0_spr_op__fn_unit$next \alu_spr0_spr_op__fn_unit - assign \alu_spr0_spr_op__insn$next \alu_spr0_spr_op__insn - assign \alu_spr0_spr_op__is_32bit$next \alu_spr0_spr_op__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:257" - switch { \cu_issue_i } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:257" - case 1'1 - assign { \alu_spr0_spr_op__is_32bit$next \alu_spr0_spr_op__insn$next \alu_spr0_spr_op__fn_unit$next \alu_spr0_spr_op__insn_type$next } { \oper_i_alu_spr0__is_32bit \oper_i_alu_spr0__insn \oper_i_alu_spr0__fn_unit \oper_i_alu_spr0__insn_type } - end - sync init - update \alu_spr0_spr_op__insn_type 7'0000000 - update \alu_spr0_spr_op__fn_unit 11'00000000000 - update \alu_spr0_spr_op__insn 32'00000000000000000000000000000000 - update \alu_spr0_spr_op__is_32bit 1'0 - sync posedge \coresync_clk - update \alu_spr0_spr_op__insn_type \alu_spr0_spr_op__insn_type$next - update \alu_spr0_spr_op__fn_unit \alu_spr0_spr_op__fn_unit$next - update \alu_spr0_spr_op__insn \alu_spr0_spr_op__insn$next - update \alu_spr0_spr_op__is_32bit \alu_spr0_spr_op__is_32bit$next - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" - wire width 64 \data_r0__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" - wire width 64 \data_r0__o$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" - wire width 1 \data_r0__o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" - wire width 1 \data_r0__o_ok$next - process $group_31 - assign \data_r0__o$next \data_r0__o - assign \data_r0__o_ok$next \data_r0__o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" - switch { \alu_pulse } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" - case 1'1 - assign { \data_r0__o_ok$next \data_r0__o$next } { \o_ok \alu_spr0_o } - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" - switch { \cu_issue_i } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" - case 1'1 - assign { \data_r0__o_ok$next \data_r0__o$next } 65'00000000000000000000000000000000000000000000000000000000000000000 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \data_r0__o_ok$next 1'0 - end - sync init - update \data_r0__o 64'0000000000000000000000000000000000000000000000000000000000000000 - update \data_r0__o_ok 1'0 - sync posedge \coresync_clk - update \data_r0__o \data_r0__o$next - update \data_r0__o_ok \data_r0__o_ok$next - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" - wire width 64 \data_r1__spr1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" - wire width 64 \data_r1__spr1$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" - wire width 1 \data_r1__spr1_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" - wire width 1 \data_r1__spr1_ok$next - process $group_33 - assign \data_r1__spr1$next \data_r1__spr1 - assign \data_r1__spr1_ok$next \data_r1__spr1_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" - switch { \alu_pulse } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" - case 1'1 - assign { \data_r1__spr1_ok$next \data_r1__spr1$next } { \spr1_ok \alu_spr0_spr1 } - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" - switch { \cu_issue_i } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" - case 1'1 - assign { \data_r1__spr1_ok$next \data_r1__spr1$next } 65'00000000000000000000000000000000000000000000000000000000000000000 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \data_r1__spr1_ok$next 1'0 - end - sync init - update \data_r1__spr1 64'0000000000000000000000000000000000000000000000000000000000000000 - update \data_r1__spr1_ok 1'0 - sync posedge \coresync_clk - update \data_r1__spr1 \data_r1__spr1$next - update \data_r1__spr1_ok \data_r1__spr1_ok$next - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" - wire width 64 \data_r2__fast1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" - wire width 64 \data_r2__fast1$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" - wire width 1 \data_r2__fast1_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" - wire width 1 \data_r2__fast1_ok$next - process $group_35 - assign \data_r2__fast1$next \data_r2__fast1 - assign \data_r2__fast1_ok$next \data_r2__fast1_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" - switch { \alu_pulse } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" - case 1'1 - assign { \data_r2__fast1_ok$next \data_r2__fast1$next } { \fast1_ok \alu_spr0_fast1 } - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" - switch { \cu_issue_i } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" - case 1'1 - assign { \data_r2__fast1_ok$next \data_r2__fast1$next } 65'00000000000000000000000000000000000000000000000000000000000000000 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \data_r2__fast1_ok$next 1'0 - end - sync init - update \data_r2__fast1 64'0000000000000000000000000000000000000000000000000000000000000000 - update \data_r2__fast1_ok 1'0 - sync posedge \coresync_clk - update \data_r2__fast1 \data_r2__fast1$next - update \data_r2__fast1_ok \data_r2__fast1_ok$next - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" - wire width 1 \data_r3__xer_so - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" - wire width 1 \data_r3__xer_so$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" - wire width 1 \data_r3__xer_so_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" - wire width 1 \data_r3__xer_so_ok$next - process $group_37 - assign \data_r3__xer_so$next \data_r3__xer_so - assign \data_r3__xer_so_ok$next \data_r3__xer_so_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" - switch { \alu_pulse } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" - case 1'1 - assign { \data_r3__xer_so_ok$next \data_r3__xer_so$next } { \xer_so_ok \alu_spr0_xer_so } - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" - switch { \cu_issue_i } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" - case 1'1 - assign { \data_r3__xer_so_ok$next \data_r3__xer_so$next } 2'00 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \data_r3__xer_so_ok$next 1'0 - end - sync init - update \data_r3__xer_so 1'0 - update \data_r3__xer_so_ok 1'0 - sync posedge \coresync_clk - update \data_r3__xer_so \data_r3__xer_so$next - update \data_r3__xer_so_ok \data_r3__xer_so_ok$next - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" - wire width 2 \data_r4__xer_ov - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" - wire width 2 \data_r4__xer_ov$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" - wire width 1 \data_r4__xer_ov_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" - wire width 1 \data_r4__xer_ov_ok$next - process $group_39 - assign \data_r4__xer_ov$next \data_r4__xer_ov - assign \data_r4__xer_ov_ok$next \data_r4__xer_ov_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" - switch { \alu_pulse } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" - case 1'1 - assign { \data_r4__xer_ov_ok$next \data_r4__xer_ov$next } { \xer_ov_ok \alu_spr0_xer_ov } - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" - switch { \cu_issue_i } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" - case 1'1 - assign { \data_r4__xer_ov_ok$next \data_r4__xer_ov$next } 3'000 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \data_r4__xer_ov_ok$next 1'0 - end - sync init - update \data_r4__xer_ov 2'00 - update \data_r4__xer_ov_ok 1'0 - sync posedge \coresync_clk - update \data_r4__xer_ov \data_r4__xer_ov$next - update \data_r4__xer_ov_ok \data_r4__xer_ov_ok$next - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" - wire width 2 \data_r5__xer_ca - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" - wire width 2 \data_r5__xer_ca$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" - wire width 1 \data_r5__xer_ca_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" - wire width 1 \data_r5__xer_ca_ok$next - process $group_41 - assign \data_r5__xer_ca$next \data_r5__xer_ca - assign \data_r5__xer_ca_ok$next \data_r5__xer_ca_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" - switch { \alu_pulse } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" - case 1'1 - assign { \data_r5__xer_ca_ok$next \data_r5__xer_ca$next } { \xer_ca_ok \alu_spr0_xer_ca } - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" - switch { \cu_issue_i } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" - case 1'1 - assign { \data_r5__xer_ca_ok$next \data_r5__xer_ca$next } 3'000 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \data_r5__xer_ca_ok$next 1'0 - end - sync init - update \data_r5__xer_ca 2'00 - update \data_r5__xer_ca_ok 1'0 - sync posedge \coresync_clk - update \data_r5__xer_ca \data_r5__xer_ca$next - update \data_r5__xer_ca_ok \data_r5__xer_ca_ok$next - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" - wire width 1 $74 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" - cell $and $75 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \o_ok - connect \B \cu_busy_o - connect \Y $74 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" - wire width 1 $76 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" - cell $and $77 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \spr1_ok - connect \B \cu_busy_o - connect \Y $76 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" - wire width 1 $78 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" - cell $and $79 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \fast1_ok - connect \B \cu_busy_o - connect \Y $78 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" - wire width 1 $80 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" - cell $and $81 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \xer_so_ok - connect \B \cu_busy_o - connect \Y $80 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" - wire width 1 $82 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" - cell $and $83 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \xer_ov_ok - connect \B \cu_busy_o - connect \Y $82 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" - wire width 1 $84 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" - cell $and $85 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \xer_ca_ok - connect \B \cu_busy_o - connect \Y $84 - end - process $group_43 - assign \cu_wrmask_o 6'000000 - assign \cu_wrmask_o { $84 $82 $80 $78 $76 $74 } - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" - wire width 64 \src_r0 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" - wire width 64 \src_r0$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - wire width 64 $86 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - cell $mux $87 - parameter \WIDTH 64 - connect \A \src_r0 - connect \B \src1_i - connect \S \src_l_q_src [0] - connect \Y $86 - end - process $group_44 - assign \alu_spr0_ra 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \alu_spr0_ra $86 - sync init - end - process $group_45 - assign \src_r0$next \src_r0 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" - switch { \src_l_q_src [0] } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" - case 1'1 - assign \src_r0$next \src1_i - end - sync init - update \src_r0 64'0000000000000000000000000000000000000000000000000000000000000000 - sync posedge \coresync_clk - update \src_r0 \src_r0$next - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" - wire width 64 \src_r1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" - wire width 64 \src_r1$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - wire width 64 $88 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - cell $mux $89 - parameter \WIDTH 64 - connect \A \src_r1 - connect \B \src2_i - connect \S \src_l_q_src [1] - connect \Y $88 - end - process $group_46 - assign \alu_spr0_spr1$1 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \alu_spr0_spr1$1 $88 - sync init - end - process $group_47 - assign \src_r1$next \src_r1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" - switch { \src_l_q_src [1] } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" - case 1'1 - assign \src_r1$next \src2_i - end - sync init - update \src_r1 64'0000000000000000000000000000000000000000000000000000000000000000 - sync posedge \coresync_clk - update \src_r1 \src_r1$next - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" - wire width 64 \src_r2 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" - wire width 64 \src_r2$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - wire width 64 $90 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - cell $mux $91 - parameter \WIDTH 64 - connect \A \src_r2 - connect \B \src3_i - connect \S \src_l_q_src [2] - connect \Y $90 - end - process $group_48 - assign \alu_spr0_fast1$2 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \alu_spr0_fast1$2 $90 - sync init - end - process $group_49 - assign \src_r2$next \src_r2 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" - switch { \src_l_q_src [2] } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" - case 1'1 - assign \src_r2$next \src3_i - end - sync init - update \src_r2 64'0000000000000000000000000000000000000000000000000000000000000000 - sync posedge \coresync_clk - update \src_r2 \src_r2$next - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" - wire width 1 \src_r3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" - wire width 1 \src_r3$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - wire width 1 $92 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - cell $mux $93 - parameter \WIDTH 1 - connect \A \src_r3 - connect \B \src4_i - connect \S \src_l_q_src [3] - connect \Y $92 - end - process $group_50 - assign \alu_spr0_xer_so$3 1'0 - assign \alu_spr0_xer_so$3 $92 - sync init - end - process $group_51 - assign \src_r3$next \src_r3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" - switch { \src_l_q_src [3] } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" - case 1'1 - assign \src_r3$next \src4_i - end - sync init - update \src_r3 1'0 - sync posedge \coresync_clk - update \src_r3 \src_r3$next - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" - wire width 2 \src_r4 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" - wire width 2 \src_r4$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - wire width 2 $94 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - cell $mux $95 - parameter \WIDTH 2 - connect \A \src_r4 - connect \B \src5_i - connect \S \src_l_q_src [4] - connect \Y $94 - end - process $group_52 - assign \alu_spr0_xer_ov$4 2'00 - assign \alu_spr0_xer_ov$4 $94 - sync init - end - process $group_53 - assign \src_r4$next \src_r4 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" - switch { \src_l_q_src [4] } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" - case 1'1 - assign \src_r4$next \src5_i - end - sync init - update \src_r4 2'00 - sync posedge \coresync_clk - update \src_r4 \src_r4$next - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" - wire width 2 \src_r5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" - wire width 2 \src_r5$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - wire width 2 $96 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - cell $mux $97 - parameter \WIDTH 2 - connect \A \src_r5 - connect \B \src6_i - connect \S \src_l_q_src [5] - connect \Y $96 - end - process $group_54 - assign \alu_spr0_xer_ca$5 2'00 - assign \alu_spr0_xer_ca$5 $96 - sync init - end - process $group_55 - assign \src_r5$next \src_r5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" - switch { \src_l_q_src [5] } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" - case 1'1 - assign \src_r5$next \src6_i - end - sync init - update \src_r5 2'00 - sync posedge \coresync_clk - update \src_r5 \src_r5$next - end - process $group_56 - assign \alu_spr0_p_valid_i 1'0 - assign \alu_spr0_p_valid_i \alui_l_q_alui - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:327" - wire width 1 $98 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:327" - cell $and $99 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \alu_spr0_p_ready_o - connect \B \alui_l_q_alui - connect \Y $98 - end - process $group_57 - assign \alui_l_r_alui$next \alui_l_r_alui - assign \alui_l_r_alui$next $98 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \alui_l_r_alui$next 1'1 - end - sync init - update \alui_l_r_alui 1'1 - sync posedge \coresync_clk - update \alui_l_r_alui \alui_l_r_alui$next - end - process $group_58 - assign \alui_l_s_alui 1'0 - assign \alui_l_s_alui \all_rd_pulse - sync init - end - process $group_59 - assign \alu_spr0_n_ready_i 1'0 - assign \alu_spr0_n_ready_i \alu_l_q_alu - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:334" - wire width 1 $100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:334" - cell $and $101 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \alu_spr0_n_valid_o - connect \B \alu_l_q_alu - connect \Y $100 - end - process $group_60 - assign \alu_l_r_alu$next \alu_l_r_alu - assign \alu_l_r_alu$next $100 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \alu_l_r_alu$next 1'1 - end - sync init - update \alu_l_r_alu 1'1 - sync posedge \coresync_clk - update \alu_l_r_alu \alu_l_r_alu$next - end - process $group_61 - assign \alu_l_s_alu 1'0 - assign \alu_l_s_alu \all_rd_pulse - sync init - end - process $group_62 - assign \cu_busy_o 1'0 - assign \cu_busy_o \opc_l_q_opc - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - wire width 6 $102 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - cell $and $103 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 6 - connect \A \src_l_q_src - connect \B { \cu_busy_o \cu_busy_o \cu_busy_o \cu_busy_o \cu_busy_o \cu_busy_o } - connect \Y $102 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - wire width 6 $104 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - cell $and $105 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 6 - connect \A $102 - connect \B { 1'1 1'1 1'1 1'1 1'1 1'1 } - connect \Y $104 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - wire width 6 $106 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - cell $not $107 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \Y_WIDTH 6 - connect \A \cu_rdmaskn_i - connect \Y $106 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - wire width 6 $108 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - cell $and $109 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 6 - connect \A $104 - connect \B $106 - connect \Y $108 - end - process $group_63 - assign \cu_rd__rel_o 6'000000 - assign \cu_rd__rel_o $108 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:102" - wire width 1 \cu_shadown_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" - wire width 1 $110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" - cell $and $111 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cu_busy_o - connect \B \cu_shadown_i - connect \Y $110 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" - wire width 1 $112 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" - cell $and $113 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cu_busy_o - connect \B \cu_shadown_i - connect \Y $112 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" - wire width 1 $114 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" - cell $and $115 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cu_busy_o - connect \B \cu_shadown_i - connect \Y $114 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" - wire width 1 $116 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" - cell $and $117 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cu_busy_o - connect \B \cu_shadown_i - connect \Y $116 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" - wire width 1 $118 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" - cell $and $119 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cu_busy_o - connect \B \cu_shadown_i - connect \Y $118 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" - wire width 1 $120 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" - cell $and $121 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cu_busy_o - connect \B \cu_shadown_i - connect \Y $120 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351" - wire width 6 $122 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351" - cell $and $123 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 6 - connect \A \req_l_q_req - connect \B { $110 $112 $114 $116 $118 $120 } - connect \Y $122 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351" - wire width 6 $124 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351" - cell $and $125 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 6 - connect \A $122 - connect \B \cu_wrmask_o - connect \Y $124 - end - process $group_64 - assign \cu_wr__rel_o 6'000000 - assign \cu_wr__rel_o $124 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - wire width 1 $126 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - cell $and $127 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cu_wr__go_i [0] - connect \B \cu_busy_o - connect \Y $126 - end - process $group_65 - assign \dest1_o 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - switch { $126 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - case 1'1 - assign \dest1_o { \data_r0__o_ok \data_r0__o } [63:0] - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - wire width 1 $128 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - cell $and $129 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cu_wr__go_i [1] - connect \B \cu_busy_o - connect \Y $128 - end - process $group_66 - assign \dest2_o 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - switch { $128 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - case 1'1 - assign \dest2_o { \data_r1__spr1_ok \data_r1__spr1 } [63:0] - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - wire width 1 $130 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - cell $and $131 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cu_wr__go_i [2] - connect \B \cu_busy_o - connect \Y $130 - end - process $group_67 - assign \dest3_o 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - switch { $130 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - case 1'1 - assign \dest3_o { \data_r2__fast1_ok \data_r2__fast1 } [63:0] - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - wire width 1 $132 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - cell $and $133 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cu_wr__go_i [3] - connect \B \cu_busy_o - connect \Y $132 - end - process $group_68 - assign \dest4_o 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - switch { $132 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - case 1'1 - assign \dest4_o { \data_r3__xer_so_ok \data_r3__xer_so } [0] - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - wire width 1 $134 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - cell $and $135 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cu_wr__go_i [4] - connect \B \cu_busy_o - connect \Y $134 - end - process $group_69 - assign \dest5_o 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - switch { $134 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - case 1'1 - assign \dest5_o { \data_r4__xer_ov_ok \data_r4__xer_ov } [1:0] - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - wire width 1 $136 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - cell $and $137 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cu_wr__go_i [5] - connect \B \cu_busy_o - connect \Y $136 - end - process $group_70 - assign \dest6_o 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - switch { $136 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - case 1'1 - assign \dest6_o { \data_r5__xer_ca_ok \data_r5__xer_ca } [1:0] - end - sync init - end - connect \cu_go_die_i 1'0 - connect \cu_shadown_i 1'1 -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.p" -module \p$71 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" - wire width 1 input 0 \p_valid_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" - wire width 1 input 1 \p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:158" - wire width 1 \trigger - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" - cell $and $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \p_valid_i - connect \B \p_ready_o - connect \Y $1 - end - process $group_0 - assign \trigger 1'0 - assign \trigger $1 - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.n" -module \n$72 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" - wire width 1 input 0 \n_valid_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" - wire width 1 input 1 \n_ready_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:251" - wire width 1 \trigger - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" - cell $and $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \n_ready_i - connect \B \n_valid_o - connect \Y $1 - end - process $group_0 - assign \trigger 1'0 - assign \trigger $1 - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_start.p" -module \p$73 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" - wire width 1 input 0 \p_valid_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" - wire width 1 input 1 \p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:158" - wire width 1 \trigger - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" - cell $and $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \p_valid_i - connect \B \p_ready_o - connect \Y $1 - end - process $group_0 - assign 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\logical_op__imm_data__data - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 4 \logical_op__imm_data__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 5 \logical_op__rc__rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 6 \logical_op__rc__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 7 \logical_op__oe__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 8 \logical_op__oe__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 9 \logical_op__invert_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 10 \logical_op__zero_a - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 input 11 \logical_op__input_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 12 \logical_op__invert_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 13 \logical_op__write_cr0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 14 \logical_op__output_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 15 \logical_op__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 16 \logical_op__is_signed - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 input 17 \logical_op__data_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 input 18 \logical_op__insn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 19 \ra - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 20 \rb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 1 input 21 \xer_so - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 output 22 \muxid$1 - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 output 23 \logical_op__insn_type$2 - attribute \enum_base_type "Function" - attribute \enum_value_00000000000 "NONE" - attribute \enum_value_00000000010 "ALU" - attribute \enum_value_00000000100 "LDST" - attribute \enum_value_00000001000 "SHIFT_ROT" - attribute \enum_value_00000010000 "LOGICAL" - attribute \enum_value_00000100000 "BRANCH" - attribute \enum_value_00001000000 "CR" - attribute \enum_value_00010000000 "TRAP" - attribute \enum_value_00100000000 "MUL" - attribute \enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 output 24 \logical_op__fn_unit$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 output 25 \logical_op__imm_data__data$4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 26 \logical_op__imm_data__ok$5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 27 \logical_op__rc__rc$6 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 28 \logical_op__rc__ok$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 29 \logical_op__oe__oe$8 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 30 \logical_op__oe__ok$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 31 \logical_op__invert_in$10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 32 \logical_op__zero_a$11 - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 output 33 \logical_op__input_carry$12 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 34 \logical_op__invert_out$13 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 35 \logical_op__write_cr0$14 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 36 \logical_op__output_carry$15 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 37 \logical_op__is_32bit$16 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 38 \logical_op__is_signed$17 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 output 39 \logical_op__data_len$18 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 output 40 \logical_op__insn$19 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 1 output 41 \xer_so$20 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" - wire width 1 output 42 \divisor_neg - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" - wire width 1 output 43 \dividend_neg - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" - wire width 1 output 44 \dive_abs_ov32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" - wire width 1 output 45 \dive_abs_ov64 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" - wire width 1 output 46 \div_by_zero - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:18" - wire width 128 output 47 \dividend - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:19" - wire width 64 output 48 \divisor_radicand - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:21" - wire width 2 output 49 \operation - wire width 1 $verilog_initial_trigger - process $group_0 - assign \operation 2'00 - assign \operation 2'01 - assign $verilog_initial_trigger $verilog_initial_trigger - sync init - update $verilog_initial_trigger 1'0 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:45" - wire width 1 $21 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:45" - cell $mux $22 - parameter \WIDTH 1 - connect \A \ra [63] - connect \B \ra [31] - connect \S \logical_op__is_32bit - connect \Y $21 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:45" - wire width 1 $23 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:45" - cell $and $24 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $21 - connect \B \logical_op__is_signed - connect \Y $23 - end - process $group_1 - assign \dividend_neg 1'0 - assign \dividend_neg $23 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:46" - wire width 1 $25 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:46" - cell $mux $26 - parameter \WIDTH 1 - connect \A \rb [63] - connect \B \rb [31] - connect \S \logical_op__is_32bit - connect \Y $25 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:46" - wire width 1 $27 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:46" - cell $and $28 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $25 - connect \B \logical_op__is_signed - connect \Y $27 - end - process $group_2 - assign \divisor_neg 1'0 - assign \divisor_neg $27 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:51" - wire width 64 \abs_dor - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:53" - wire width 65 $29 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:53" - wire width 65 $30 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:53" - cell $neg $31 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \Y_WIDTH 65 - connect \A \rb - connect \Y $30 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 65 $32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - cell $pos $33 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \Y_WIDTH 65 - connect \A \rb - connect \Y $32 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:53" - wire width 65 $34 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:53" - cell $mux $35 - parameter \WIDTH 65 - connect \A $32 - connect \B $30 - connect \S \divisor_neg - connect \Y $34 - end - connect $29 $34 - process $group_3 - assign \abs_dor 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \abs_dor $29 [63:0] - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:52" - wire width 64 \abs_dend - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:54" - wire width 65 $36 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:54" - wire width 65 $37 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:54" - cell $neg $38 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \Y_WIDTH 65 - connect \A \ra - connect \Y $37 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 65 $39 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - cell $pos $40 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \Y_WIDTH 65 - connect \A \ra - connect \Y $39 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:54" - wire width 65 $41 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:54" - cell $mux $42 - parameter \WIDTH 65 - connect \A $39 - connect \B $37 - connect \S \dividend_neg - connect \Y $41 - end - connect $36 $41 - process $group_4 - assign \abs_dend 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \abs_dend $36 [63:0] - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:57" - wire width 1 $43 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:57" - cell $ge $44 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \B_SIGNED 0 - parameter \B_WIDTH 64 - parameter \Y_WIDTH 1 - connect \A \abs_dend - connect \B \abs_dor - connect \Y $43 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:58" - wire width 1 $45 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:58" - cell $eq $46 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A \logical_op__insn_type - connect \B 7'0011110 - connect \Y $45 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:58" - wire width 1 $47 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:58" - cell $and $48 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $43 - connect \B $45 - connect \Y $47 - end - process $group_5 - assign \dive_abs_ov64 1'0 - assign \dive_abs_ov64 $47 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:60" - wire width 1 $49 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:60" - cell $ge $50 - parameter \A_SIGNED 0 - parameter \A_WIDTH 32 - parameter \B_SIGNED 0 - parameter \B_WIDTH 32 - parameter \Y_WIDTH 1 - connect \A \abs_dend [31:0] - connect \B \abs_dor [31:0] - connect \Y $49 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:61" - wire width 1 $51 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:61" - cell $eq $52 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A \logical_op__insn_type - connect \B 7'0011110 - connect \Y $51 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:61" - wire width 1 $53 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:61" - cell $and $54 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $49 - connect \B $51 - connect \Y $53 - end - process $group_6 - assign \dive_abs_ov32 1'0 - assign \dive_abs_ov32 $53 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:34" - wire width 32 $55 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:34" - cell $mux $56 - parameter \WIDTH 32 - connect \A \abs_dor [63:32] - connect \B 32'00000000000000000000000000000000 - connect \S \logical_op__is_32bit - connect \Y $55 - end - process $group_7 - assign \divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \divisor_radicand [31:0] \abs_dor [31:0] - assign \divisor_radicand [63:32] $55 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:67" - wire width 1 $57 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:67" - cell $eq $58 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \divisor_radicand - connect \B 1'0 - connect \Y $57 - end - process $group_8 - assign \div_by_zero 1'0 - assign \div_by_zero $57 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:34" - wire width 32 $59 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:34" - cell $mux $60 - parameter \WIDTH 32 - connect \A \abs_dend [63:32] - connect \B 32'00000000000000000000000000000000 - connect \S \logical_op__is_32bit - connect \Y $59 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:79" - wire width 128 $61 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:79" - wire width 95 $62 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:79" - cell $sshl $63 - parameter \A_SIGNED 0 - parameter \A_WIDTH 32 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 95 - connect \A \abs_dend [31:0] - connect \B 6'100000 - connect \Y $62 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:79" - cell $pos $64 - parameter \A_SIGNED 0 - parameter \A_WIDTH 95 - parameter \Y_WIDTH 128 - connect \A $62 - connect \Y $61 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:81" - wire width 191 $65 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:81" - wire width 191 $66 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:81" - cell $sshl $67 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 191 - connect \A \abs_dend - connect \B 7'1000000 - connect \Y $66 - end - connect $65 $66 - process $group_9 - assign \dividend 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:72" - switch \logical_op__insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:74" - attribute \nmigen.decoding "OP_DIV/29|OP_MOD/47" - case 7'0011101, 7'0101111 - assign \dividend [31:0] \abs_dend [31:0] - assign \dividend [63:32] $59 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/setup_stage.py:77" - attribute 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"OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \setup_stage_logical_op__insn_type - attribute \enum_base_type "Function" - attribute \enum_value_00000000000 "NONE" - attribute \enum_value_00000000010 "ALU" - attribute \enum_value_00000000100 "LDST" - attribute \enum_value_00000001000 "SHIFT_ROT" - attribute \enum_value_00000010000 "LOGICAL" - attribute \enum_value_00000100000 "BRANCH" - attribute \enum_value_00001000000 "CR" - attribute \enum_value_00010000000 "TRAP" - attribute \enum_value_00100000000 "MUL" - attribute \enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 \setup_stage_logical_op__fn_unit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \setup_stage_logical_op__imm_data__data - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \setup_stage_logical_op__imm_data__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \setup_stage_logical_op__rc__rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \setup_stage_logical_op__rc__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \setup_stage_logical_op__oe__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \setup_stage_logical_op__oe__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \setup_stage_logical_op__invert_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \setup_stage_logical_op__zero_a - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \setup_stage_logical_op__input_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \setup_stage_logical_op__invert_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \setup_stage_logical_op__write_cr0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \setup_stage_logical_op__output_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \setup_stage_logical_op__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \setup_stage_logical_op__is_signed - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \setup_stage_logical_op__data_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \setup_stage_logical_op__insn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \setup_stage_ra - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \setup_stage_rb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 1 \setup_stage_xer_so - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \setup_stage_muxid$45 - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \setup_stage_logical_op__insn_type$46 - attribute \enum_base_type "Function" - attribute \enum_value_00000000000 "NONE" - attribute \enum_value_00000000010 "ALU" - attribute \enum_value_00000000100 "LDST" - attribute \enum_value_00000001000 "SHIFT_ROT" - attribute \enum_value_00000010000 "LOGICAL" - attribute \enum_value_00000100000 "BRANCH" - attribute \enum_value_00001000000 "CR" - attribute \enum_value_00010000000 "TRAP" - attribute \enum_value_00100000000 "MUL" - attribute \enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 \setup_stage_logical_op__fn_unit$47 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \setup_stage_logical_op__imm_data__data$48 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \setup_stage_logical_op__imm_data__ok$49 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \setup_stage_logical_op__rc__rc$50 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \setup_stage_logical_op__rc__ok$51 - attribute \src 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"/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \setup_stage_logical_op__write_cr0$58 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \setup_stage_logical_op__output_carry$59 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \setup_stage_logical_op__is_32bit$60 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \setup_stage_logical_op__is_signed$61 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \setup_stage_logical_op__data_len$62 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \setup_stage_logical_op__insn$63 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 1 \setup_stage_xer_so$64 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" - wire width 1 \setup_stage_divisor_neg - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" - wire width 1 \setup_stage_dividend_neg - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" - wire width 1 \setup_stage_dive_abs_ov32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" - wire width 1 \setup_stage_dive_abs_ov64 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" - wire width 1 \setup_stage_div_by_zero - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:18" - wire width 128 \setup_stage_dividend - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:19" - wire width 64 \setup_stage_divisor_radicand - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:21" - wire width 2 \setup_stage_operation - cell \setup_stage \setup_stage - connect \muxid \setup_stage_muxid - connect \logical_op__insn_type \setup_stage_logical_op__insn_type - connect \logical_op__fn_unit \setup_stage_logical_op__fn_unit - connect \logical_op__imm_data__data \setup_stage_logical_op__imm_data__data - connect \logical_op__imm_data__ok \setup_stage_logical_op__imm_data__ok - connect \logical_op__rc__rc \setup_stage_logical_op__rc__rc - connect \logical_op__rc__ok \setup_stage_logical_op__rc__ok - connect \logical_op__oe__oe \setup_stage_logical_op__oe__oe - connect \logical_op__oe__ok \setup_stage_logical_op__oe__ok - connect \logical_op__invert_in \setup_stage_logical_op__invert_in - connect \logical_op__zero_a \setup_stage_logical_op__zero_a - connect \logical_op__input_carry \setup_stage_logical_op__input_carry - connect \logical_op__invert_out \setup_stage_logical_op__invert_out - connect \logical_op__write_cr0 \setup_stage_logical_op__write_cr0 - connect \logical_op__output_carry \setup_stage_logical_op__output_carry - connect \logical_op__is_32bit \setup_stage_logical_op__is_32bit - connect \logical_op__is_signed \setup_stage_logical_op__is_signed - connect \logical_op__data_len \setup_stage_logical_op__data_len - connect \logical_op__insn \setup_stage_logical_op__insn - connect \ra \setup_stage_ra - connect \rb \setup_stage_rb - connect \xer_so \setup_stage_xer_so - connect \muxid$1 \setup_stage_muxid$45 - connect \logical_op__insn_type$2 \setup_stage_logical_op__insn_type$46 - connect \logical_op__fn_unit$3 \setup_stage_logical_op__fn_unit$47 - connect \logical_op__imm_data__data$4 \setup_stage_logical_op__imm_data__data$48 - connect \logical_op__imm_data__ok$5 \setup_stage_logical_op__imm_data__ok$49 - connect \logical_op__rc__rc$6 \setup_stage_logical_op__rc__rc$50 - connect \logical_op__rc__ok$7 \setup_stage_logical_op__rc__ok$51 - connect \logical_op__oe__oe$8 \setup_stage_logical_op__oe__oe$52 - connect \logical_op__oe__ok$9 \setup_stage_logical_op__oe__ok$53 - connect \logical_op__invert_in$10 \setup_stage_logical_op__invert_in$54 - connect \logical_op__zero_a$11 \setup_stage_logical_op__zero_a$55 - connect \logical_op__input_carry$12 \setup_stage_logical_op__input_carry$56 - connect \logical_op__invert_out$13 \setup_stage_logical_op__invert_out$57 - connect \logical_op__write_cr0$14 \setup_stage_logical_op__write_cr0$58 - connect \logical_op__output_carry$15 \setup_stage_logical_op__output_carry$59 - connect \logical_op__is_32bit$16 \setup_stage_logical_op__is_32bit$60 - connect \logical_op__is_signed$17 \setup_stage_logical_op__is_signed$61 - connect \logical_op__data_len$18 \setup_stage_logical_op__data_len$62 - connect \logical_op__insn$19 \setup_stage_logical_op__insn$63 - connect \xer_so$20 \setup_stage_xer_so$64 - connect \divisor_neg \setup_stage_divisor_neg - connect \dividend_neg \setup_stage_dividend_neg - connect \dive_abs_ov32 \setup_stage_dive_abs_ov32 - connect \dive_abs_ov64 \setup_stage_dive_abs_ov64 - connect \div_by_zero \setup_stage_div_by_zero - connect \dividend \setup_stage_dividend - connect \divisor_radicand \setup_stage_divisor_radicand - connect \operation \setup_stage_operation - end - process $group_0 - assign \input_muxid 2'00 - assign \input_muxid \muxid$1 - sync init - end - process $group_1 - assign \input_logical_op__insn_type 7'0000000 - assign \input_logical_op__fn_unit 11'00000000000 - assign \input_logical_op__imm_data__data 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \input_logical_op__imm_data__ok 1'0 - assign \input_logical_op__rc__rc 1'0 - assign \input_logical_op__rc__ok 1'0 - assign \input_logical_op__oe__oe 1'0 - assign \input_logical_op__oe__ok 1'0 - assign \input_logical_op__invert_in 1'0 - assign \input_logical_op__zero_a 1'0 - assign \input_logical_op__input_carry 2'00 - assign \input_logical_op__invert_out 1'0 - assign \input_logical_op__write_cr0 1'0 - assign \input_logical_op__output_carry 1'0 - assign \input_logical_op__is_32bit 1'0 - assign \input_logical_op__is_signed 1'0 - assign \input_logical_op__data_len 4'0000 - assign \input_logical_op__insn 32'00000000000000000000000000000000 - assign { \input_logical_op__insn \input_logical_op__data_len \input_logical_op__is_signed \input_logical_op__is_32bit \input_logical_op__output_carry \input_logical_op__write_cr0 \input_logical_op__invert_out \input_logical_op__input_carry \input_logical_op__zero_a \input_logical_op__invert_in { \input_logical_op__oe__ok \input_logical_op__oe__oe } { \input_logical_op__rc__ok \input_logical_op__rc__rc } { \input_logical_op__imm_data__ok \input_logical_op__imm_data__data } \input_logical_op__fn_unit \input_logical_op__insn_type } { \logical_op__insn$19 \logical_op__data_len$18 \logical_op__is_signed$17 \logical_op__is_32bit$16 \logical_op__output_carry$15 \logical_op__write_cr0$14 \logical_op__invert_out$13 \logical_op__input_carry$12 \logical_op__zero_a$11 \logical_op__invert_in$10 { \logical_op__oe__ok$9 \logical_op__oe__oe$8 } { \logical_op__rc__ok$7 \logical_op__rc__rc$6 } { \logical_op__imm_data__ok$5 \logical_op__imm_data__data$4 } \logical_op__fn_unit$3 \logical_op__insn_type$2 } - sync init - end - process $group_19 - assign \input_ra 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \input_ra \ra$20 - sync init - end - process $group_20 - assign \input_rb 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \input_rb \rb$21 - sync init - end - process $group_21 - assign \input_xer_so 1'0 - assign \input_xer_so \xer_so$22 - sync init - end - process $group_22 - assign \setup_stage_muxid 2'00 - assign \setup_stage_muxid \input_muxid$23 - sync init - end - process $group_23 - assign \setup_stage_logical_op__insn_type 7'0000000 - assign \setup_stage_logical_op__fn_unit 11'00000000000 - assign \setup_stage_logical_op__imm_data__data 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \setup_stage_logical_op__imm_data__ok 1'0 - assign \setup_stage_logical_op__rc__rc 1'0 - assign \setup_stage_logical_op__rc__ok 1'0 - assign \setup_stage_logical_op__oe__oe 1'0 - assign \setup_stage_logical_op__oe__ok 1'0 - assign \setup_stage_logical_op__invert_in 1'0 - assign \setup_stage_logical_op__zero_a 1'0 - assign \setup_stage_logical_op__input_carry 2'00 - assign \setup_stage_logical_op__invert_out 1'0 - assign \setup_stage_logical_op__write_cr0 1'0 - assign \setup_stage_logical_op__output_carry 1'0 - assign \setup_stage_logical_op__is_32bit 1'0 - assign \setup_stage_logical_op__is_signed 1'0 - assign \setup_stage_logical_op__data_len 4'0000 - assign \setup_stage_logical_op__insn 32'00000000000000000000000000000000 - assign { \setup_stage_logical_op__insn \setup_stage_logical_op__data_len \setup_stage_logical_op__is_signed \setup_stage_logical_op__is_32bit \setup_stage_logical_op__output_carry \setup_stage_logical_op__write_cr0 \setup_stage_logical_op__invert_out \setup_stage_logical_op__input_carry \setup_stage_logical_op__zero_a \setup_stage_logical_op__invert_in { \setup_stage_logical_op__oe__ok \setup_stage_logical_op__oe__oe } { \setup_stage_logical_op__rc__ok \setup_stage_logical_op__rc__rc } { \setup_stage_logical_op__imm_data__ok \setup_stage_logical_op__imm_data__data } \setup_stage_logical_op__fn_unit \setup_stage_logical_op__insn_type } { \input_logical_op__insn$41 \input_logical_op__data_len$40 \input_logical_op__is_signed$39 \input_logical_op__is_32bit$38 \input_logical_op__output_carry$37 \input_logical_op__write_cr0$36 \input_logical_op__invert_out$35 \input_logical_op__input_carry$34 \input_logical_op__zero_a$33 \input_logical_op__invert_in$32 { \input_logical_op__oe__ok$31 \input_logical_op__oe__oe$30 } { \input_logical_op__rc__ok$29 \input_logical_op__rc__rc$28 } { \input_logical_op__imm_data__ok$27 \input_logical_op__imm_data__data$26 } \input_logical_op__fn_unit$25 \input_logical_op__insn_type$24 } - sync init - end - process $group_41 - assign \setup_stage_ra 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \setup_stage_ra \input_ra$42 - sync init - end - process $group_42 - assign \setup_stage_rb 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \setup_stage_rb \input_rb$43 - sync init - end - process $group_43 - assign \setup_stage_xer_so 1'0 - assign \setup_stage_xer_so \input_xer_so$44 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:621" - wire width 1 \p_valid_i$65 - process $group_44 - assign \p_valid_i$65 1'0 - assign \p_valid_i$65 \p_valid_i - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:619" - wire width 1 \n_i_rdy_data - process $group_45 - assign \n_i_rdy_data 1'0 - assign \n_i_rdy_data \n_ready_i - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" - wire width 1 \p_valid_i_p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" - wire width 1 $66 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" - cell $and $67 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \p_valid_i$65 - connect \B \p_ready_o - connect \Y $66 - end - process $group_46 - assign \p_valid_i_p_ready_o 1'0 - assign \p_valid_i_p_ready_o $66 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \muxid$68 - process $group_47 - assign \muxid$68 2'00 - assign \muxid$68 \setup_stage_muxid$45 - sync init - end - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \logical_op__insn_type$69 - attribute \enum_base_type "Function" - attribute \enum_value_00000000000 "NONE" - attribute \enum_value_00000000010 "ALU" - attribute \enum_value_00000000100 "LDST" - attribute \enum_value_00000001000 "SHIFT_ROT" - attribute \enum_value_00000010000 "LOGICAL" - attribute \enum_value_00000100000 "BRANCH" - attribute \enum_value_00001000000 "CR" - attribute \enum_value_00010000000 "TRAP" - attribute \enum_value_00100000000 "MUL" - attribute \enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 \logical_op__fn_unit$70 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \logical_op__imm_data__data$71 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__imm_data__ok$72 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__rc__rc$73 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__rc__ok$74 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__oe__oe$75 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__oe__ok$76 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__invert_in$77 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__zero_a$78 - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \logical_op__input_carry$79 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__invert_out$80 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__write_cr0$81 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__output_carry$82 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__is_32bit$83 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__is_signed$84 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \logical_op__data_len$85 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \logical_op__insn$86 - process $group_48 - assign \logical_op__insn_type$69 7'0000000 - assign \logical_op__fn_unit$70 11'00000000000 - assign \logical_op__imm_data__data$71 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \logical_op__imm_data__ok$72 1'0 - assign \logical_op__rc__rc$73 1'0 - assign \logical_op__rc__ok$74 1'0 - assign \logical_op__oe__oe$75 1'0 - assign \logical_op__oe__ok$76 1'0 - assign \logical_op__invert_in$77 1'0 - assign \logical_op__zero_a$78 1'0 - assign \logical_op__input_carry$79 2'00 - assign \logical_op__invert_out$80 1'0 - assign \logical_op__write_cr0$81 1'0 - assign \logical_op__output_carry$82 1'0 - assign \logical_op__is_32bit$83 1'0 - assign \logical_op__is_signed$84 1'0 - assign \logical_op__data_len$85 4'0000 - assign \logical_op__insn$86 32'00000000000000000000000000000000 - assign { \logical_op__insn$86 \logical_op__data_len$85 \logical_op__is_signed$84 \logical_op__is_32bit$83 \logical_op__output_carry$82 \logical_op__write_cr0$81 \logical_op__invert_out$80 \logical_op__input_carry$79 \logical_op__zero_a$78 \logical_op__invert_in$77 { \logical_op__oe__ok$76 \logical_op__oe__oe$75 } { \logical_op__rc__ok$74 \logical_op__rc__rc$73 } { \logical_op__imm_data__ok$72 \logical_op__imm_data__data$71 } \logical_op__fn_unit$70 \logical_op__insn_type$69 } { \setup_stage_logical_op__insn$63 \setup_stage_logical_op__data_len$62 \setup_stage_logical_op__is_signed$61 \setup_stage_logical_op__is_32bit$60 \setup_stage_logical_op__output_carry$59 \setup_stage_logical_op__write_cr0$58 \setup_stage_logical_op__invert_out$57 \setup_stage_logical_op__input_carry$56 \setup_stage_logical_op__zero_a$55 \setup_stage_logical_op__invert_in$54 { \setup_stage_logical_op__oe__ok$53 \setup_stage_logical_op__oe__oe$52 } { \setup_stage_logical_op__rc__ok$51 \setup_stage_logical_op__rc__rc$50 } { \setup_stage_logical_op__imm_data__ok$49 \setup_stage_logical_op__imm_data__data$48 } \setup_stage_logical_op__fn_unit$47 \setup_stage_logical_op__insn_type$46 } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \ra$87 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \ra$88 - process $group_66 - assign \ra$87 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \ra$87 \ra$88 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \rb$89 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \rb$90 - process $group_67 - assign \rb$89 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \rb$89 \rb$90 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 1 \xer_so$91 - process $group_68 - assign \xer_so$91 1'0 - assign \xer_so$91 \setup_stage_xer_so$64 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" - wire width 1 \divisor_neg$92 - process $group_69 - assign \divisor_neg$92 1'0 - assign \divisor_neg$92 \setup_stage_divisor_neg - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" - wire width 1 \dividend_neg$93 - process $group_70 - assign \dividend_neg$93 1'0 - assign \dividend_neg$93 \setup_stage_dividend_neg - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" - wire width 1 \dive_abs_ov32$94 - process $group_71 - assign \dive_abs_ov32$94 1'0 - assign \dive_abs_ov32$94 \setup_stage_dive_abs_ov32 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" - wire width 1 \dive_abs_ov64$95 - process $group_72 - assign \dive_abs_ov64$95 1'0 - assign \dive_abs_ov64$95 \setup_stage_dive_abs_ov64 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" - wire width 1 \div_by_zero$96 - process $group_73 - assign \div_by_zero$96 1'0 - assign \div_by_zero$96 \setup_stage_div_by_zero - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:18" - wire width 128 \dividend$97 - process $group_74 - assign \dividend$97 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \dividend$97 \setup_stage_dividend - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:19" - wire width 64 \divisor_radicand$98 - process $group_75 - assign \divisor_radicand$98 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \divisor_radicand$98 \setup_stage_divisor_radicand - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:21" - wire width 2 \operation$99 - process $group_76 - assign \operation$99 2'00 - assign \operation$99 \setup_stage_operation - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615" - wire width 1 \r_busy - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615" - wire width 1 \r_busy$next - process $group_77 - assign \r_busy$next \r_busy - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign \r_busy$next 1'1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign \r_busy$next 1'0 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \r_busy$next 1'0 - end - sync init - update \r_busy 1'0 - sync posedge \coresync_clk - update \r_busy \r_busy$next - end - process $group_78 - assign \muxid$next \muxid - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign \muxid$next \muxid$68 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign \muxid$next \muxid$68 - end - sync init - update \muxid 2'00 - sync posedge \coresync_clk - update \muxid \muxid$next - end - process $group_79 - assign \logical_op__insn_type$next \logical_op__insn_type - assign \logical_op__fn_unit$next \logical_op__fn_unit - assign \logical_op__imm_data__data$next \logical_op__imm_data__data - assign \logical_op__imm_data__ok$next \logical_op__imm_data__ok - assign \logical_op__rc__rc$next \logical_op__rc__rc - assign \logical_op__rc__ok$next \logical_op__rc__ok - assign \logical_op__oe__oe$next \logical_op__oe__oe - assign \logical_op__oe__ok$next \logical_op__oe__ok - assign \logical_op__invert_in$next \logical_op__invert_in - assign \logical_op__zero_a$next \logical_op__zero_a - assign \logical_op__input_carry$next \logical_op__input_carry - assign \logical_op__invert_out$next \logical_op__invert_out - assign \logical_op__write_cr0$next \logical_op__write_cr0 - assign \logical_op__output_carry$next \logical_op__output_carry - assign \logical_op__is_32bit$next \logical_op__is_32bit - assign \logical_op__is_signed$next \logical_op__is_signed - assign \logical_op__data_len$next \logical_op__data_len - assign \logical_op__insn$next \logical_op__insn - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign { \logical_op__insn$next \logical_op__data_len$next \logical_op__is_signed$next \logical_op__is_32bit$next \logical_op__output_carry$next \logical_op__write_cr0$next \logical_op__invert_out$next \logical_op__input_carry$next \logical_op__zero_a$next \logical_op__invert_in$next { \logical_op__oe__ok$next \logical_op__oe__oe$next } { \logical_op__rc__ok$next \logical_op__rc__rc$next } { \logical_op__imm_data__ok$next \logical_op__imm_data__data$next } \logical_op__fn_unit$next \logical_op__insn_type$next } { \logical_op__insn$86 \logical_op__data_len$85 \logical_op__is_signed$84 \logical_op__is_32bit$83 \logical_op__output_carry$82 \logical_op__write_cr0$81 \logical_op__invert_out$80 \logical_op__input_carry$79 \logical_op__zero_a$78 \logical_op__invert_in$77 { \logical_op__oe__ok$76 \logical_op__oe__oe$75 } { \logical_op__rc__ok$74 \logical_op__rc__rc$73 } { \logical_op__imm_data__ok$72 \logical_op__imm_data__data$71 } \logical_op__fn_unit$70 \logical_op__insn_type$69 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign { \logical_op__insn$next \logical_op__data_len$next \logical_op__is_signed$next \logical_op__is_32bit$next \logical_op__output_carry$next \logical_op__write_cr0$next \logical_op__invert_out$next \logical_op__input_carry$next \logical_op__zero_a$next \logical_op__invert_in$next { \logical_op__oe__ok$next \logical_op__oe__oe$next } { \logical_op__rc__ok$next \logical_op__rc__rc$next } { \logical_op__imm_data__ok$next \logical_op__imm_data__data$next } \logical_op__fn_unit$next \logical_op__insn_type$next } { \logical_op__insn$86 \logical_op__data_len$85 \logical_op__is_signed$84 \logical_op__is_32bit$83 \logical_op__output_carry$82 \logical_op__write_cr0$81 \logical_op__invert_out$80 \logical_op__input_carry$79 \logical_op__zero_a$78 \logical_op__invert_in$77 { \logical_op__oe__ok$76 \logical_op__oe__oe$75 } { \logical_op__rc__ok$74 \logical_op__rc__rc$73 } { \logical_op__imm_data__ok$72 \logical_op__imm_data__data$71 } \logical_op__fn_unit$70 \logical_op__insn_type$69 } - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \logical_op__imm_data__data$next 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \logical_op__imm_data__ok$next 1'0 - assign \logical_op__rc__rc$next 1'0 - assign \logical_op__rc__ok$next 1'0 - assign \logical_op__oe__oe$next 1'0 - assign \logical_op__oe__ok$next 1'0 - end - sync init - update \logical_op__insn_type 7'0000000 - update \logical_op__fn_unit 11'00000000000 - update \logical_op__imm_data__data 64'0000000000000000000000000000000000000000000000000000000000000000 - update \logical_op__imm_data__ok 1'0 - update \logical_op__rc__rc 1'0 - update \logical_op__rc__ok 1'0 - update \logical_op__oe__oe 1'0 - update \logical_op__oe__ok 1'0 - update \logical_op__invert_in 1'0 - update \logical_op__zero_a 1'0 - update \logical_op__input_carry 2'00 - update \logical_op__invert_out 1'0 - update \logical_op__write_cr0 1'0 - update \logical_op__output_carry 1'0 - update \logical_op__is_32bit 1'0 - update \logical_op__is_signed 1'0 - update \logical_op__data_len 4'0000 - update \logical_op__insn 32'00000000000000000000000000000000 - sync posedge \coresync_clk - update \logical_op__insn_type \logical_op__insn_type$next - update \logical_op__fn_unit \logical_op__fn_unit$next - update \logical_op__imm_data__data \logical_op__imm_data__data$next - update \logical_op__imm_data__ok \logical_op__imm_data__ok$next - update \logical_op__rc__rc \logical_op__rc__rc$next - update \logical_op__rc__ok \logical_op__rc__ok$next - update \logical_op__oe__oe \logical_op__oe__oe$next - update \logical_op__oe__ok \logical_op__oe__ok$next - update \logical_op__invert_in \logical_op__invert_in$next - update \logical_op__zero_a \logical_op__zero_a$next - update \logical_op__input_carry \logical_op__input_carry$next - update \logical_op__invert_out \logical_op__invert_out$next - update \logical_op__write_cr0 \logical_op__write_cr0$next - update \logical_op__output_carry \logical_op__output_carry$next - update \logical_op__is_32bit \logical_op__is_32bit$next - update \logical_op__is_signed \logical_op__is_signed$next - update \logical_op__data_len \logical_op__data_len$next - update \logical_op__insn \logical_op__insn$next - end - process $group_97 - assign \ra$next \ra - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign \ra$next \ra$87 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign \ra$next \ra$87 - end - sync init - update \ra 64'0000000000000000000000000000000000000000000000000000000000000000 - sync posedge \coresync_clk - update \ra \ra$next - end - process $group_98 - assign \rb$next \rb - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign \rb$next \rb$89 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign \rb$next \rb$89 - end - sync init - update \rb 64'0000000000000000000000000000000000000000000000000000000000000000 - sync posedge \coresync_clk - update \rb \rb$next - end - process $group_99 - assign \xer_so$next \xer_so - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign \xer_so$next \xer_so$91 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign \xer_so$next \xer_so$91 - end - sync init - update \xer_so 1'0 - sync posedge \coresync_clk - update \xer_so \xer_so$next - end - process $group_100 - assign \divisor_neg$next \divisor_neg - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign \divisor_neg$next \divisor_neg$92 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign \divisor_neg$next \divisor_neg$92 - end - sync init - update \divisor_neg 1'0 - sync posedge \coresync_clk - update \divisor_neg \divisor_neg$next - end - process $group_101 - assign \dividend_neg$next \dividend_neg - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign \dividend_neg$next \dividend_neg$93 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign \dividend_neg$next \dividend_neg$93 - end - sync init - update \dividend_neg 1'0 - sync posedge \coresync_clk - update \dividend_neg \dividend_neg$next - end - process $group_102 - assign \dive_abs_ov32$next \dive_abs_ov32 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign \dive_abs_ov32$next \dive_abs_ov32$94 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign \dive_abs_ov32$next \dive_abs_ov32$94 - end - sync init - update \dive_abs_ov32 1'0 - sync posedge \coresync_clk - update \dive_abs_ov32 \dive_abs_ov32$next - end - process $group_103 - assign \dive_abs_ov64$next \dive_abs_ov64 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign \dive_abs_ov64$next \dive_abs_ov64$95 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign \dive_abs_ov64$next \dive_abs_ov64$95 - end - sync init - update \dive_abs_ov64 1'0 - sync posedge \coresync_clk - update \dive_abs_ov64 \dive_abs_ov64$next - end - process $group_104 - assign \div_by_zero$next \div_by_zero - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign \div_by_zero$next \div_by_zero$96 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign \div_by_zero$next \div_by_zero$96 - end - sync init - update \div_by_zero 1'0 - sync posedge \coresync_clk - update \div_by_zero \div_by_zero$next - end - process $group_105 - assign \dividend$next \dividend - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign \dividend$next \dividend$97 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign \dividend$next \dividend$97 - end - sync init - update \dividend 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - sync posedge \coresync_clk - update \dividend \dividend$next - end - process $group_106 - assign \divisor_radicand$next \divisor_radicand - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign \divisor_radicand$next \divisor_radicand$98 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign \divisor_radicand$next \divisor_radicand$98 - end - sync init - update \divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 - sync posedge \coresync_clk - update \divisor_radicand \divisor_radicand$next - end - process $group_107 - assign \operation$next \operation - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign \operation$next \operation$99 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign \operation$next \operation$99 - end - sync init - update \operation 2'00 - sync posedge \coresync_clk - update \operation \operation$next - end - process $group_108 - assign \n_valid_o 1'0 - assign \n_valid_o \r_busy - sync init - end - process $group_109 - assign \p_ready_o 1'0 - assign \p_ready_o \n_i_rdy_data - sync init - end - connect \ra$88 64'0000000000000000000000000000000000000000000000000000000000000000 - connect \rb$90 64'0000000000000000000000000000000000000000000000000000000000000000 -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_0.p" -module \p$76 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" - wire width 1 input 0 \p_valid_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" - wire width 1 input 1 \p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:158" - wire width 1 \trigger - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" - cell $and $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \p_valid_i - connect \B \p_ready_o - connect \Y $1 - end - process $group_0 - assign \trigger 1'0 - assign \trigger $1 - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_0.n" -module \n$77 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" - wire width 1 input 0 \n_valid_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" - wire width 1 input 1 \n_ready_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:251" - wire width 1 \trigger - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" - cell $and $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \n_ready_i - connect \B \n_valid_o - connect \Y $1 - end - process $group_0 - assign \trigger 1'0 - assign \trigger $1 - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_0.div_state_next" -module \div_state_next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:123" - wire width 128 output 0 \o_dividend_quotient - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:121" - wire width 7 output 1 \o_q_bits_known - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:121" - wire width 7 input 2 \i_q_bits_known - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:123" - wire width 128 input 3 \i_dividend_quotient - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:77" - wire width 64 input 4 \divisor - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:82" - wire width 128 \difference - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:85" - wire width 129 $1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:85" - wire width 127 $2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:85" - cell $sshl $3 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 127 - connect \A \divisor - connect \B 6'111111 - connect \Y $2 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:85" - wire width 129 $4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:85" - cell $sub $5 - parameter \A_SIGNED 0 - parameter \A_WIDTH 128 - parameter \B_SIGNED 0 - parameter \B_WIDTH 127 - parameter \Y_WIDTH 129 - connect \A \i_dividend_quotient - connect \B $2 - connect \Y $4 - end - connect $1 $4 - process $group_0 - assign \difference 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \difference $1 [127:0] - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:86" - wire width 1 \next_quotient_bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:88" - wire width 1 $6 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:88" - cell $not $7 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \difference [127] - connect \Y $6 - end - process $group_1 - assign \next_quotient_bit 1'0 - assign \next_quotient_bit $6 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:89" - wire width 128 \value - process $group_2 - assign \value 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:90" - switch { \next_quotient_bit } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:90" - case 1'1 - assign \value \difference - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:92" - case - assign \value \i_dividend_quotient - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:127" - wire width 1 $8 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:127" - cell $eq $9 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A \i_q_bits_known - connect \B 7'1000000 - connect \Y $8 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:99" - wire width 8 $10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:99" - wire width 8 $11 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:99" - cell $add $12 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 8 - connect \A \i_q_bits_known - connect \B 1'1 - connect \Y $11 - end - connect $10 $11 - process $group_3 - assign \o_q_bits_known 7'0000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:95" - switch { $8 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:95" - case 1'1 - assign \o_q_bits_known \i_q_bits_known - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:97" - case - assign \o_q_bits_known $10 [6:0] - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:127" - wire width 1 $13 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:127" - cell $eq $14 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A \i_q_bits_known - connect \B 7'1000000 - connect \Y $13 - end - process $group_4 - assign \o_dividend_quotient 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:95" - switch { $13 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:95" - case 1'1 - assign \o_dividend_quotient \i_dividend_quotient - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:97" - case - assign \o_dividend_quotient { \value \next_quotient_bit } [127:0] - end - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_0.div_state_init" -module \div_state_init - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:107" - wire width 128 input 0 \dividend - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:121" - wire width 7 output 1 \o_q_bits_known - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:123" - wire width 128 output 2 \o_dividend_quotient - wire width 1 $verilog_initial_trigger - process $group_0 - assign \o_q_bits_known 7'0000000 - assign \o_q_bits_known 7'0000000 - assign $verilog_initial_trigger $verilog_initial_trigger - sync init - update $verilog_initial_trigger 1'0 - end - process $group_1 - assign \o_dividend_quotient 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \o_dividend_quotient \dividend - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_middle_0" -module \pipe_middle_0 - attribute \src "simple/issuer.py:141" - wire width 1 input 0 \coresync_clk - attribute \src "simple/issuer.py:141" - wire width 1 input 1 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" - wire width 1 input 2 \p_valid_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" - wire width 1 output 3 \p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 input 4 \muxid - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute 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"OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \logical_op__insn_type$29 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \logical_op__insn_type$29$next - attribute \enum_base_type "Function" - attribute \enum_value_00000000000 "NONE" - attribute \enum_value_00000000010 "ALU" - attribute \enum_value_00000000100 "LDST" - attribute \enum_value_00000001000 "SHIFT_ROT" - attribute \enum_value_00000010000 "LOGICAL" - attribute \enum_value_00000100000 "BRANCH" - attribute \enum_value_00001000000 "CR" - attribute \enum_value_00010000000 "TRAP" - attribute \enum_value_00100000000 "MUL" - attribute \enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 \logical_op__fn_unit$30 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 \logical_op__fn_unit$30$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \logical_op__imm_data__data$31 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \logical_op__imm_data__data$31$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__imm_data__ok$32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__imm_data__ok$32$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__rc__rc$33 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__rc__rc$33$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__rc__ok$34 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__rc__ok$34$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__oe__oe$35 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__oe__oe$35$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__oe__ok$36 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__oe__ok$36$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__invert_in$37 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__invert_in$37$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__zero_a$38 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__zero_a$38$next - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \logical_op__input_carry$39 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \logical_op__input_carry$39$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__invert_out$40 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__invert_out$40$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__write_cr0$41 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__write_cr0$41$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__output_carry$42 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__output_carry$42$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__is_32bit$43 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__is_32bit$43$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__is_signed$44 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__is_signed$44$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \logical_op__data_len$45 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \logical_op__data_len$45$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \logical_op__insn$46 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \logical_op__insn$46$next - process $group_2 - assign \logical_op__insn_type$2 7'0000000 - assign \logical_op__fn_unit$3 11'00000000000 - assign \logical_op__imm_data__data$4 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \logical_op__imm_data__ok$5 1'0 - assign \logical_op__rc__rc$6 1'0 - assign \logical_op__rc__ok$7 1'0 - assign \logical_op__oe__oe$8 1'0 - assign \logical_op__oe__ok$9 1'0 - assign \logical_op__invert_in$10 1'0 - assign \logical_op__zero_a$11 1'0 - assign \logical_op__input_carry$12 2'00 - assign \logical_op__invert_out$13 1'0 - assign \logical_op__write_cr0$14 1'0 - assign \logical_op__output_carry$15 1'0 - assign \logical_op__is_32bit$16 1'0 - assign \logical_op__is_signed$17 1'0 - assign \logical_op__data_len$18 4'0000 - assign \logical_op__insn$19 32'00000000000000000000000000000000 - assign { \logical_op__insn$19 \logical_op__data_len$18 \logical_op__is_signed$17 \logical_op__is_32bit$16 \logical_op__output_carry$15 \logical_op__write_cr0$14 \logical_op__invert_out$13 \logical_op__input_carry$12 \logical_op__zero_a$11 \logical_op__invert_in$10 { \logical_op__oe__ok$9 \logical_op__oe__oe$8 } { \logical_op__rc__ok$7 \logical_op__rc__rc$6 } { \logical_op__imm_data__ok$5 \logical_op__imm_data__data$4 } \logical_op__fn_unit$3 \logical_op__insn_type$2 } { \logical_op__insn$46 \logical_op__data_len$45 \logical_op__is_signed$44 \logical_op__is_32bit$43 \logical_op__output_carry$42 \logical_op__write_cr0$41 \logical_op__invert_out$40 \logical_op__input_carry$39 \logical_op__zero_a$38 \logical_op__invert_in$37 { \logical_op__oe__ok$36 \logical_op__oe__oe$35 } { \logical_op__rc__ok$34 \logical_op__rc__rc$33 } { \logical_op__imm_data__ok$32 \logical_op__imm_data__data$31 } \logical_op__fn_unit$30 \logical_op__insn_type$29 } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \ra$47 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \ra$47$next - process $group_20 - assign \ra$20 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \ra$20 \ra$47 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \rb$48 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \rb$48$next - process $group_21 - assign \rb$21 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \rb$21 \rb$48 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 1 \xer_so$49 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 1 \xer_so$49$next - process $group_22 - assign \xer_so$22 1'0 - assign \xer_so$22 \xer_so$49 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" - wire width 1 \divisor_neg$50 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" - wire width 1 \divisor_neg$50$next - process $group_23 - assign \divisor_neg$23 1'0 - assign \divisor_neg$23 \divisor_neg$50 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" - wire width 1 \dividend_neg$51 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" - wire width 1 \dividend_neg$51$next - process $group_24 - assign \dividend_neg$24 1'0 - assign \dividend_neg$24 \dividend_neg$51 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" - wire width 1 \dive_abs_ov32$52 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" - wire width 1 \dive_abs_ov32$52$next - process $group_25 - assign \dive_abs_ov32$25 1'0 - assign \dive_abs_ov32$25 \dive_abs_ov32$52 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" - wire width 1 \dive_abs_ov64$53 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" - wire width 1 \dive_abs_ov64$53$next - process $group_26 - assign \dive_abs_ov64$26 1'0 - assign \dive_abs_ov64$26 \dive_abs_ov64$53 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" - wire width 1 \div_by_zero$54 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" - wire width 1 \div_by_zero$54$next - process $group_27 - assign \div_by_zero$27 1'0 - assign \div_by_zero$27 \div_by_zero$54 - sync init - end - process $group_28 - assign \quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \quotient_root \div_state_next_o_dividend_quotient [63:0] - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:180" - wire width 192 $55 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:180" - wire width 191 $56 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:180" - cell $sshl $57 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 191 - connect \A \div_state_next_o_dividend_quotient [127:64] - connect \B 7'1000000 - connect \Y $56 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:180" - cell $pos $58 - parameter \A_SIGNED 0 - parameter \A_WIDTH 191 - parameter \Y_WIDTH 192 - connect \A $56 - connect \Y $55 - end - process $group_29 - assign \remainder 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \remainder $55 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:181" - wire width 1 $59 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:152" - wire width 1 \empty - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:152" - wire width 1 \empty$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:181" - cell $not $60 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \empty - connect \Y $59 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:127" - wire width 1 $61 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:127" - cell $eq $62 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A \div_state_next_o_q_bits_known - connect \B 7'1000000 - connect \Y $61 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:181" - wire width 1 $63 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:181" - cell $and $64 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $59 - connect \B $61 - connect \Y $63 - end - process $group_30 - assign \n_valid_o 1'0 - assign \n_valid_o $63 - sync init - end - process $group_31 - assign \p_ready_o 1'0 - assign \p_ready_o \empty - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:121" - wire width 7 \saved_state_q_bits_known - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:121" - wire width 7 \saved_state_q_bits_known$next - process $group_32 - assign \saved_state_q_bits_known$next \saved_state_q_bits_known - assign \saved_state_q_bits_known$next \div_state_next_o_q_bits_known - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \saved_state_q_bits_known$next 7'0000000 - end - sync init - update \saved_state_q_bits_known 7'0000000 - sync posedge \coresync_clk - update \saved_state_q_bits_known \saved_state_q_bits_known$next - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:123" - wire width 128 \saved_state_dividend_quotient - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:123" - wire width 128 \saved_state_dividend_quotient$next - process $group_33 - assign \saved_state_dividend_quotient$next \saved_state_dividend_quotient - assign \saved_state_dividend_quotient$next \div_state_next_o_dividend_quotient - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \saved_state_dividend_quotient$next 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - end - sync init - update \saved_state_dividend_quotient 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - sync posedge \coresync_clk - update \saved_state_dividend_quotient \saved_state_dividend_quotient$next - end - process $group_34 - assign \div_state_next_i_q_bits_known 7'0000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:185" - switch { \empty } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:185" - case 1'1 - assign \div_state_next_i_q_bits_known \div_state_init_o_q_bits_known - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:191" - case - assign \div_state_next_i_q_bits_known \saved_state_q_bits_known - end - sync init - end - process $group_35 - assign \div_state_next_i_dividend_quotient 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:185" - switch { \empty } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:185" - case 1'1 - assign \div_state_next_i_dividend_quotient \div_state_init_o_dividend_quotient - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:191" - case - assign \div_state_next_i_dividend_quotient \saved_state_dividend_quotient - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:19" - wire width 64 \divisor_radicand$65 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:19" - wire width 64 \divisor_radicand$65$next - process $group_36 - assign \div_state_next_divisor 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:185" - switch { \empty } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:185" - case 1'1 - assign \div_state_next_divisor \divisor_radicand - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:191" - case - assign \div_state_next_divisor \divisor_radicand$65 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:195" - wire width 1 $66 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:195" - cell $and $67 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \n_ready_i - connect \B \n_valid_o - connect \Y $66 - end - process $group_37 - assign \empty$next \empty - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:185" - switch { \empty } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:185" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:188" - switch { \p_valid_i } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:188" - case 1'1 - assign \empty$next 1'0 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:191" - case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:195" - switch { $66 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:195" - case 1'1 - assign \empty$next 1'1 - end - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \empty$next 1'1 - end - sync init - update \empty 1'1 - sync posedge \coresync_clk - update \empty \empty$next - end - process $group_38 - assign \muxid$28$next \muxid$28 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:185" - switch { \empty } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:185" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:188" - switch { \p_valid_i } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:188" - case 1'1 - assign \muxid$28$next \muxid - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:191" - case - end - sync init - update \muxid$28 2'00 - sync posedge \coresync_clk - update \muxid$28 \muxid$28$next - end - process $group_39 - assign \logical_op__insn_type$29$next \logical_op__insn_type$29 - assign \logical_op__fn_unit$30$next \logical_op__fn_unit$30 - assign \logical_op__imm_data__data$31$next \logical_op__imm_data__data$31 - assign \logical_op__imm_data__ok$32$next \logical_op__imm_data__ok$32 - assign \logical_op__rc__rc$33$next \logical_op__rc__rc$33 - assign \logical_op__rc__ok$34$next \logical_op__rc__ok$34 - assign \logical_op__oe__oe$35$next \logical_op__oe__oe$35 - assign \logical_op__oe__ok$36$next \logical_op__oe__ok$36 - assign \logical_op__invert_in$37$next \logical_op__invert_in$37 - assign \logical_op__zero_a$38$next \logical_op__zero_a$38 - assign \logical_op__input_carry$39$next \logical_op__input_carry$39 - assign \logical_op__invert_out$40$next \logical_op__invert_out$40 - assign \logical_op__write_cr0$41$next \logical_op__write_cr0$41 - assign \logical_op__output_carry$42$next \logical_op__output_carry$42 - assign \logical_op__is_32bit$43$next \logical_op__is_32bit$43 - assign \logical_op__is_signed$44$next \logical_op__is_signed$44 - assign \logical_op__data_len$45$next \logical_op__data_len$45 - assign \logical_op__insn$46$next \logical_op__insn$46 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:185" - switch { \empty } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:185" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:188" - switch { \p_valid_i } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:188" - case 1'1 - assign { \logical_op__insn$46$next \logical_op__data_len$45$next \logical_op__is_signed$44$next \logical_op__is_32bit$43$next \logical_op__output_carry$42$next \logical_op__write_cr0$41$next \logical_op__invert_out$40$next \logical_op__input_carry$39$next \logical_op__zero_a$38$next \logical_op__invert_in$37$next { \logical_op__oe__ok$36$next \logical_op__oe__oe$35$next } { \logical_op__rc__ok$34$next \logical_op__rc__rc$33$next } { \logical_op__imm_data__ok$32$next \logical_op__imm_data__data$31$next } \logical_op__fn_unit$30$next \logical_op__insn_type$29$next } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in { \logical_op__oe__ok \logical_op__oe__oe } { \logical_op__rc__ok \logical_op__rc__rc } { \logical_op__imm_data__ok \logical_op__imm_data__data } \logical_op__fn_unit \logical_op__insn_type } - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:191" - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \logical_op__imm_data__data$31$next 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \logical_op__imm_data__ok$32$next 1'0 - assign \logical_op__rc__rc$33$next 1'0 - assign \logical_op__rc__ok$34$next 1'0 - assign \logical_op__oe__oe$35$next 1'0 - assign \logical_op__oe__ok$36$next 1'0 - end - sync init - update \logical_op__insn_type$29 7'0000000 - update \logical_op__fn_unit$30 11'00000000000 - update \logical_op__imm_data__data$31 64'0000000000000000000000000000000000000000000000000000000000000000 - update \logical_op__imm_data__ok$32 1'0 - update \logical_op__rc__rc$33 1'0 - update \logical_op__rc__ok$34 1'0 - update \logical_op__oe__oe$35 1'0 - update \logical_op__oe__ok$36 1'0 - update \logical_op__invert_in$37 1'0 - update \logical_op__zero_a$38 1'0 - update \logical_op__input_carry$39 2'00 - update \logical_op__invert_out$40 1'0 - update \logical_op__write_cr0$41 1'0 - update \logical_op__output_carry$42 1'0 - update \logical_op__is_32bit$43 1'0 - update \logical_op__is_signed$44 1'0 - update \logical_op__data_len$45 4'0000 - update \logical_op__insn$46 32'00000000000000000000000000000000 - sync posedge \coresync_clk - update \logical_op__insn_type$29 \logical_op__insn_type$29$next - update \logical_op__fn_unit$30 \logical_op__fn_unit$30$next - update \logical_op__imm_data__data$31 \logical_op__imm_data__data$31$next - update \logical_op__imm_data__ok$32 \logical_op__imm_data__ok$32$next - update \logical_op__rc__rc$33 \logical_op__rc__rc$33$next - update \logical_op__rc__ok$34 \logical_op__rc__ok$34$next - update \logical_op__oe__oe$35 \logical_op__oe__oe$35$next - update \logical_op__oe__ok$36 \logical_op__oe__ok$36$next - update \logical_op__invert_in$37 \logical_op__invert_in$37$next - update \logical_op__zero_a$38 \logical_op__zero_a$38$next - update \logical_op__input_carry$39 \logical_op__input_carry$39$next - update \logical_op__invert_out$40 \logical_op__invert_out$40$next - update \logical_op__write_cr0$41 \logical_op__write_cr0$41$next - update \logical_op__output_carry$42 \logical_op__output_carry$42$next - update \logical_op__is_32bit$43 \logical_op__is_32bit$43$next - update \logical_op__is_signed$44 \logical_op__is_signed$44$next - update \logical_op__data_len$45 \logical_op__data_len$45$next - update \logical_op__insn$46 \logical_op__insn$46$next - end - process $group_57 - assign \ra$47$next \ra$47 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:185" - switch { \empty } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:185" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:188" - switch { \p_valid_i } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:188" - case 1'1 - assign \ra$47$next \ra - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:191" - case - end - sync init - update \ra$47 64'0000000000000000000000000000000000000000000000000000000000000000 - sync posedge \coresync_clk - update \ra$47 \ra$47$next - end - process $group_58 - assign \rb$48$next \rb$48 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:185" - switch { \empty } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:185" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:188" - switch { \p_valid_i } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:188" - case 1'1 - assign \rb$48$next \rb - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:191" - case - end - sync init - update \rb$48 64'0000000000000000000000000000000000000000000000000000000000000000 - sync posedge \coresync_clk - update \rb$48 \rb$48$next - end - process $group_59 - assign \xer_so$49$next \xer_so$49 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:185" - switch { \empty } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:185" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:188" - switch { \p_valid_i } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:188" - case 1'1 - assign \xer_so$49$next \xer_so - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:191" - case - end - sync init - update \xer_so$49 1'0 - sync posedge \coresync_clk - update \xer_so$49 \xer_so$49$next - end - process $group_60 - assign \divisor_neg$50$next \divisor_neg$50 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:185" - switch { \empty } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:185" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:188" - switch { \p_valid_i } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:188" - case 1'1 - assign \divisor_neg$50$next \divisor_neg - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:191" - case - end - sync init - update \divisor_neg$50 1'0 - sync posedge \coresync_clk - update \divisor_neg$50 \divisor_neg$50$next - end - process $group_61 - assign \dividend_neg$51$next \dividend_neg$51 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:185" - switch { \empty } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:185" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:188" - switch { \p_valid_i } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:188" - case 1'1 - assign \dividend_neg$51$next \dividend_neg - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:191" - case - end - sync init - update \dividend_neg$51 1'0 - sync posedge \coresync_clk - update \dividend_neg$51 \dividend_neg$51$next - end - process $group_62 - assign \dive_abs_ov32$52$next \dive_abs_ov32$52 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:185" - switch { \empty } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:185" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:188" - switch { \p_valid_i } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:188" - case 1'1 - assign \dive_abs_ov32$52$next \dive_abs_ov32 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:191" - case - end - sync init - update \dive_abs_ov32$52 1'0 - sync posedge \coresync_clk - update \dive_abs_ov32$52 \dive_abs_ov32$52$next - end - process $group_63 - assign \dive_abs_ov64$53$next \dive_abs_ov64$53 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:185" - switch { \empty } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:185" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:188" - switch { \p_valid_i } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:188" - case 1'1 - assign \dive_abs_ov64$53$next \dive_abs_ov64 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:191" - case - end - sync init - update \dive_abs_ov64$53 1'0 - sync posedge \coresync_clk - update \dive_abs_ov64$53 \dive_abs_ov64$53$next - end - process $group_64 - assign \div_by_zero$54$next \div_by_zero$54 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:185" - switch { \empty } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:185" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:188" - switch { \p_valid_i } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:188" - case 1'1 - assign \div_by_zero$54$next \div_by_zero - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:191" - case - end - sync init - update \div_by_zero$54 1'0 - sync posedge \coresync_clk - update \div_by_zero$54 \div_by_zero$54$next - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:18" - wire width 128 \dividend$68 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:18" - wire width 128 \dividend$68$next - process $group_65 - assign \dividend$68$next \dividend$68 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:185" - switch { \empty } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:185" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:188" - switch { \p_valid_i } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:188" - case 1'1 - assign \dividend$68$next \dividend - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:191" - case - end - sync init - update \dividend$68 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - sync posedge \coresync_clk - update \dividend$68 \dividend$68$next - end - process $group_66 - assign \divisor_radicand$65$next \divisor_radicand$65 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:185" - switch { \empty } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:185" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:188" - switch { \p_valid_i } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:188" - case 1'1 - assign \divisor_radicand$65$next \divisor_radicand - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:191" - case - end - sync init - update \divisor_radicand$65 64'0000000000000000000000000000000000000000000000000000000000000000 - sync posedge \coresync_clk - update \divisor_radicand$65 \divisor_radicand$65$next - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:21" - wire width 2 \operation$69 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:21" - wire width 2 \operation$69$next - process $group_67 - assign \operation$69$next \operation$69 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:185" - switch { \empty } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:185" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:188" - switch { \p_valid_i } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:188" - case 1'1 - assign \operation$69$next \operation - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:191" - case - end - sync init - update \operation$69 2'00 - sync posedge \coresync_clk - update \operation$69 \operation$69$next - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_end.p" -module \p$78 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" - wire width 1 input 0 \p_valid_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" - wire width 1 input 1 \p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:158" - wire width 1 \trigger - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" - cell $and $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \p_valid_i - connect \B \p_ready_o - connect \Y $1 - end - process $group_0 - assign \trigger 1'0 - assign \trigger $1 - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_end.n" -module \n$79 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" - wire width 1 input 0 \n_valid_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" - wire width 1 input 1 \n_ready_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:251" - wire width 1 \trigger - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" - cell $and $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \n_ready_i - connect \B \n_valid_o - connect \Y $1 - end - process $group_0 - assign \trigger 1'0 - assign \trigger $1 - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_end.output_stage" -module \output_stage - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 input 0 \muxid - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 input 1 \logical_op__insn_type - attribute \enum_base_type "Function" - attribute \enum_value_00000000000 "NONE" - attribute \enum_value_00000000010 "ALU" - attribute \enum_value_00000000100 "LDST" - attribute \enum_value_00000001000 "SHIFT_ROT" - attribute \enum_value_00000010000 "LOGICAL" - attribute \enum_value_00000100000 "BRANCH" - attribute \enum_value_00001000000 "CR" - attribute \enum_value_00010000000 "TRAP" - attribute \enum_value_00100000000 "MUL" - attribute \enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 input 2 \logical_op__fn_unit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 input 3 \logical_op__imm_data__data - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 4 \logical_op__imm_data__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 5 \logical_op__rc__rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 6 \logical_op__rc__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 7 \logical_op__oe__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 8 \logical_op__oe__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 9 \logical_op__invert_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 10 \logical_op__zero_a - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 input 11 \logical_op__input_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 12 \logical_op__invert_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 13 \logical_op__write_cr0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 14 \logical_op__output_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 15 \logical_op__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 16 \logical_op__is_signed - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 input 17 \logical_op__data_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 input 18 \logical_op__insn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 1 input 19 \xer_so - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" - wire width 1 input 20 \divisor_neg - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" - wire width 1 input 21 \dividend_neg - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" - wire width 1 input 22 \dive_abs_ov32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" - wire width 1 input 23 \dive_abs_ov64 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" - wire width 1 input 24 \div_by_zero - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:40" - wire width 64 input 25 \quotient_root - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:41" - wire width 192 input 26 \remainder - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 output 27 \muxid$1 - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 output 28 \logical_op__insn_type$2 - attribute \enum_base_type "Function" - attribute \enum_value_00000000000 "NONE" - attribute \enum_value_00000000010 "ALU" - attribute \enum_value_00000000100 "LDST" - attribute \enum_value_00000001000 "SHIFT_ROT" - attribute \enum_value_00000010000 "LOGICAL" - attribute \enum_value_00000100000 "BRANCH" - attribute \enum_value_00001000000 "CR" - attribute \enum_value_00010000000 "TRAP" - attribute \enum_value_00100000000 "MUL" - attribute \enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 output 29 \logical_op__fn_unit$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 output 30 \logical_op__imm_data__data$4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 31 \logical_op__imm_data__ok$5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 32 \logical_op__rc__rc$6 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 33 \logical_op__rc__ok$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 34 \logical_op__oe__oe$8 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 35 \logical_op__oe__ok$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 36 \logical_op__invert_in$10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 37 \logical_op__zero_a$11 - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 output 38 \logical_op__input_carry$12 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 39 \logical_op__invert_out$13 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 40 \logical_op__write_cr0$14 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 41 \logical_op__output_carry$15 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 42 \logical_op__is_32bit$16 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 43 \logical_op__is_signed$17 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 output 44 \logical_op__data_len$18 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 output 45 \logical_op__insn$19 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 output 46 \o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 47 \o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 2 output 48 \xer_ov - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 49 \xer_ov_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 50 \xer_so$20 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:24" - wire width 1 \quotient_neg - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:55" - wire width 1 $21 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:55" - cell $xor $22 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \dividend_neg - connect \B \divisor_neg - connect \Y $21 - end - process $group_0 - assign \quotient_neg 1'0 - assign \quotient_neg $21 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:25" - wire width 1 \remainder_neg - process $group_1 - assign \remainder_neg 1'0 - assign \remainder_neg \dividend_neg - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:26" - wire width 65 \quotient_65 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:65" - wire width 65 $23 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:65" - cell $neg $24 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \Y_WIDTH 65 - connect \A \quotient_root - connect \Y $23 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:40" - wire width 65 $25 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:40" - cell $pos $26 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \Y_WIDTH 65 - connect \A \quotient_root - connect \Y $25 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:65" - wire width 65 $27 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:65" - cell $mux $28 - parameter \WIDTH 65 - connect \A $25 - connect \B $23 - connect \S \quotient_neg - connect \Y $27 - end - process $group_2 - assign \quotient_65 65'00000000000000000000000000000000000000000000000000000000000000000 - assign \quotient_65 $27 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:27" - wire width 64 \remainder_64 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:67" - wire width 65 $29 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:67" - wire width 65 $30 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:67" - cell $neg $31 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \Y_WIDTH 65 - connect \A \remainder [127:64] - connect \Y $30 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:265" - wire width 65 $32 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:265" - cell $pos $33 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \Y_WIDTH 65 - connect \A \remainder [127:64] - connect \Y $32 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:67" - wire width 65 $34 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:67" - cell $mux $35 - parameter \WIDTH 65 - connect \A $32 - connect \B $30 - connect \S \remainder_neg - connect \Y $34 - end - connect $29 $34 - process $group_3 - assign \remainder_64 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \remainder_64 $29 [63:0] - sync init - end - wire width 1 $verilog_initial_trigger - process $group_4 - assign \xer_ov_ok 1'0 - assign \xer_ov_ok 1'1 - assign $verilog_initial_trigger $verilog_initial_trigger - sync init - update $verilog_initial_trigger 1'0 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:75" - wire width 1 \ov - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:78" - wire width 1 $36 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:78" - cell $not $37 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \logical_op__is_32bit - connect \Y $36 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:80" - wire width 1 $38 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:80" - cell $xor $39 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \quotient_65 [64] - connect \B \quotient_65 [63] - connect \Y $38 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:80" - wire width 1 $40 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:80" - cell $and $41 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \logical_op__is_signed - connect \B $38 - connect \Y $40 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:84" - wire width 1 $42 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:84" - cell $ne $43 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \quotient_65 [32] - connect \B \quotient_65 [31] - connect \Y $42 - end - process $group_5 - assign \ov 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:76" - switch { \logical_op__is_signed $36 \div_by_zero } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:76" - case 3'--1 - assign \ov 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:78" - case 3'-1- - assign \ov \dive_abs_ov64 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:80" - switch { $40 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:80" - case 1'1 - assign \ov 1'1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:82" - case 3'1-- - assign \ov \dive_abs_ov32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:84" - switch { $42 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:84" - case 1'1 - assign \ov 1'1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:86" - case - assign \ov \dive_abs_ov32 - end - sync init - end - process $group_6 - assign \xer_ov 2'00 - assign \xer_ov { \ov \ov } - sync init - end - process $group_7 - assign \o_ok 1'0 - assign \o_ok 1'1 - assign $verilog_initial_trigger $verilog_initial_trigger - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:96" - wire width 1 $44 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:96" - cell $not $45 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \ov - connect \Y $44 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:102" - wire width 64 $46 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:102" - cell $pos $47 - parameter \A_SIGNED 0 - parameter \A_WIDTH 32 - parameter \Y_WIDTH 64 - connect \A \quotient_65 [31:0] - connect \Y $46 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:104" - wire width 64 $48 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:104" - cell $pos $49 - parameter \A_SIGNED 0 - parameter \A_WIDTH 32 - parameter \Y_WIDTH 64 - connect \A \quotient_65 [31:0] - connect \Y $48 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:111" - wire width 64 $50 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:111" - cell $pos $51 - parameter \A_SIGNED 0 - parameter \A_WIDTH 32 - parameter \Y_WIDTH 64 - connect \A \quotient_65 [31:0] - connect \Y $50 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:113" - wire width 64 $52 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:113" - cell $pos $53 - parameter \A_SIGNED 0 - parameter \A_WIDTH 32 - parameter \Y_WIDTH 64 - connect \A \quotient_65 [31:0] - connect \Y $52 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:120" - wire width 64 $54 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:120" - cell $pos $55 - parameter \A_SIGNED 1 - parameter \A_WIDTH 32 - parameter \Y_WIDTH 64 - connect \A \remainder_64 [31:0] - connect \Y $54 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:122" - wire width 64 $56 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:122" - cell $pos $57 - parameter \A_SIGNED 0 - parameter \A_WIDTH 32 - parameter \Y_WIDTH 64 - connect \A \remainder_64 [31:0] - connect \Y $56 - end - process $group_8 - assign \o 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:96" - switch { $44 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:96" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:97" - switch \logical_op__insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:98" - attribute \nmigen.decoding "OP_DIVE/30" - case 7'0011110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:99" - switch { \logical_op__is_32bit } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:99" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:100" - switch { \logical_op__is_signed } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:100" - case 1'1 - assign \o $46 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:103" - case - assign \o $48 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:105" - case - assign \o \quotient_65 [63:0] - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:107" - attribute \nmigen.decoding "OP_DIV/29" - case 7'0011101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:108" - switch { \logical_op__is_32bit } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:108" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:109" - switch { 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"/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:121" - case - assign \o $56 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/output_stage.py:123" - case - assign \o \remainder_64 - end - end - end - sync init - end - process $group_9 - assign \xer_so$20 1'0 - assign \xer_so$20 \xer_so - sync init - end - process $group_10 - assign \muxid$1 2'00 - assign \muxid$1 \muxid - sync init - end - process $group_11 - assign \logical_op__insn_type$2 7'0000000 - assign \logical_op__fn_unit$3 11'00000000000 - assign \logical_op__imm_data__data$4 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \logical_op__imm_data__ok$5 1'0 - assign \logical_op__rc__rc$6 1'0 - assign \logical_op__rc__ok$7 1'0 - assign \logical_op__oe__oe$8 1'0 - assign \logical_op__oe__ok$9 1'0 - assign \logical_op__invert_in$10 1'0 - assign \logical_op__zero_a$11 1'0 - assign \logical_op__input_carry$12 2'00 - assign \logical_op__invert_out$13 1'0 - assign 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} { \logical_op__rc__ok \logical_op__rc__rc } { \logical_op__imm_data__ok \logical_op__imm_data__data } \logical_op__fn_unit \logical_op__insn_type } - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_end.output" -module \output$80 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 input 0 \muxid - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" 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- wire width 1 output 39 \logical_op__is_32bit$16 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 40 \logical_op__is_signed$17 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 output 41 \logical_op__data_len$18 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 output 42 \logical_op__insn$19 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 output 43 \o$20 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 44 \o_ok$21 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 4 output 45 \cr_a$22 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 46 \cr_a_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 2 output 47 \xer_ov$23 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 48 \xer_ov_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 49 \xer_so$24 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 50 \xer_so_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:28" - wire width 1 \oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:29" - wire width 1 $25 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:29" - cell $and $26 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \logical_op__oe__oe - connect \B \logical_op__oe__ok - connect \Y $25 - end - process $group_0 - assign \oe 1'0 - assign \oe $25 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:27" - wire width 1 \so - process $group_1 - assign \so 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:30" - switch { \oe } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:30" - case 1'1 - assign \so \xer_so$24 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:32" - case - assign \so \xer_so - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:38" - wire width 65 \o$27 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:41" - wire width 65 $28 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:41" - wire width 64 $29 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:41" - cell $not $30 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \Y_WIDTH 64 - connect \A \o - connect \Y $29 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:41" - cell $pos $31 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \Y_WIDTH 65 - connect \A $29 - connect \Y $28 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 65 $32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - cell $pos $33 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \Y_WIDTH 65 - connect \A \o - connect \Y $32 - end - process $group_2 - assign \o$27 65'00000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:40" - switch { \logical_op__invert_out } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:40" - case 1'1 - assign \o$27 $28 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:42" - case - assign \o$27 $32 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:50" - wire width 64 \target - process $group_3 - assign \target 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \target \o$27 [63:0] - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:69" - wire width 1 \is_cmp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:77" - wire width 1 $34 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:77" - cell $eq $35 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A \logical_op__insn_type - connect \B 7'0001010 - connect \Y $34 - end - process $group_4 - assign \is_cmp 1'0 - assign \is_cmp $34 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:70" - wire width 1 \is_cmpeqb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:78" - wire width 1 $36 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:78" - cell $eq $37 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A \logical_op__insn_type - connect \B 7'0001100 - connect \Y $36 - end - process $group_5 - assign \is_cmpeqb 1'0 - assign \is_cmpeqb $36 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:68" - wire width 1 \msb_test - process $group_6 - assign \msb_test 1'0 - assign \msb_test \target [63] - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:65" - wire width 1 \is_nzero - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:81" - wire width 1 $38 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:81" - cell $reduce_bool $39 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \Y_WIDTH 1 - connect \A \target - connect \Y $38 - end - process $group_7 - assign \is_nzero 1'0 - assign \is_nzero $38 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:67" - wire width 1 \is_negative - process $group_8 - assign \is_negative 1'0 - assign \is_negative \msb_test - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:66" - wire width 1 \is_positive - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:83" - wire width 1 $40 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:83" - cell $not $41 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \msb_test - connect \Y $40 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:83" - wire width 1 $42 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:83" - cell $and $43 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \is_nzero - connect \B $40 - connect \Y $42 - end - process $group_9 - assign \is_positive 1'0 - assign \is_positive $42 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:71" - wire width 4 \cr0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:85" - wire width 1 $44 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:85" - cell $or $45 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \is_cmpeqb - connect \B \is_cmp - connect \Y $44 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:88" - wire width 1 $46 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:88" - cell $not $47 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \is_nzero - connect \Y $46 - end - process $group_10 - assign \cr0 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:85" - switch { $44 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:85" - case 1'1 - assign \cr0 \cr_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:87" - case - assign \cr0 { \is_negative \is_positive $46 \so } - end - sync init - end - process $group_11 - assign \o$20 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \o$20 \o$27 [63:0] - sync init - end - process $group_12 - assign \o_ok$21 1'0 - assign \o_ok$21 \o_ok - sync init - end - process $group_13 - assign \cr_a$22 4'0000 - assign \cr_a$22 \cr0 - sync init - end - process $group_14 - assign \cr_a_ok 1'0 - assign \cr_a_ok \logical_op__write_cr0 - sync init - end - process $group_15 - assign \muxid$1 2'00 - assign \muxid$1 \muxid - sync init - end - process $group_16 - assign \logical_op__insn_type$2 7'0000000 - assign \logical_op__fn_unit$3 11'00000000000 - assign \logical_op__imm_data__data$4 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \logical_op__imm_data__ok$5 1'0 - assign \logical_op__rc__rc$6 1'0 - assign \logical_op__rc__ok$7 1'0 - assign \logical_op__oe__oe$8 1'0 - assign \logical_op__oe__ok$9 1'0 - assign \logical_op__invert_in$10 1'0 - assign \logical_op__zero_a$11 1'0 - assign \logical_op__input_carry$12 2'00 - assign \logical_op__invert_out$13 1'0 - assign \logical_op__write_cr0$14 1'0 - assign \logical_op__output_carry$15 1'0 - assign \logical_op__is_32bit$16 1'0 - assign \logical_op__is_signed$17 1'0 - assign \logical_op__data_len$18 4'0000 - assign \logical_op__insn$19 32'00000000000000000000000000000000 - assign { \logical_op__insn$19 \logical_op__data_len$18 \logical_op__is_signed$17 \logical_op__is_32bit$16 \logical_op__output_carry$15 \logical_op__write_cr0$14 \logical_op__invert_out$13 \logical_op__input_carry$12 \logical_op__zero_a$11 \logical_op__invert_in$10 { \logical_op__oe__ok$9 \logical_op__oe__oe$8 } { \logical_op__rc__ok$7 \logical_op__rc__rc$6 } { \logical_op__imm_data__ok$5 \logical_op__imm_data__data$4 } \logical_op__fn_unit$3 \logical_op__insn_type$2 } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in { \logical_op__oe__ok \logical_op__oe__oe } { \logical_op__rc__ok \logical_op__rc__rc } { \logical_op__imm_data__ok \logical_op__imm_data__data } \logical_op__fn_unit \logical_op__insn_type } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:29" - wire width 1 \oe$48 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:30" - wire width 1 $49 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:30" - cell $and $50 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \logical_op__oe__oe - connect \B \logical_op__oe__ok - connect \Y $49 - end - process $group_34 - assign \oe$48 1'0 - assign \oe$48 $49 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:33" - wire width 1 $51 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:33" - cell $or $52 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \xer_so - connect \B \xer_ov [0] - connect \Y $51 - end - process $group_35 - assign \xer_so$24 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:31" - switch { \oe$48 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:31" - case 1'1 - assign \xer_so$24 $51 - end - sync init - end - process $group_36 - assign \xer_so_ok 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:31" - switch { \oe$48 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:31" - case 1'1 - assign \xer_so_ok 1'1 - end - sync init - end - process $group_37 - assign \xer_ov$23 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:31" - switch { \oe$48 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:31" - case 1'1 - assign \xer_ov$23 \xer_ov - end - sync init - end - process $group_38 - assign \xer_ov_ok 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:31" - switch { \oe$48 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:31" - case 1'1 - assign \xer_ov_ok 1'1 - end - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0.pipe_end" -module \pipe_end - attribute \src "simple/issuer.py:141" - wire width 1 input 0 \coresync_clk - attribute \src "simple/issuer.py:141" - wire width 1 input 1 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" - wire width 1 input 2 \p_valid_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" - wire width 1 output 3 \p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 input 4 \muxid - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - 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\logical_op__insn_type - attribute \enum_base_type "Function" - attribute \enum_value_00000000000 "NONE" - attribute \enum_value_00000000010 "ALU" - attribute \enum_value_00000000100 "LDST" - attribute \enum_value_00000001000 "SHIFT_ROT" - attribute \enum_value_00000010000 "LOGICAL" - attribute \enum_value_00000100000 "BRANCH" - attribute \enum_value_00001000000 "CR" - attribute \enum_value_00010000000 "TRAP" - attribute \enum_value_00100000000 "MUL" - attribute \enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 input 6 \logical_op__fn_unit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 input 7 \logical_op__imm_data__data - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 8 \logical_op__imm_data__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 9 \logical_op__rc__rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 10 \logical_op__rc__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 11 \logical_op__oe__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 12 \logical_op__oe__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 13 \logical_op__invert_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 14 \logical_op__zero_a - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 input 15 \logical_op__input_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 16 \logical_op__invert_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 17 \logical_op__write_cr0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 18 \logical_op__output_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 19 \logical_op__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 20 \logical_op__is_signed - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 input 21 \logical_op__data_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 input 22 \logical_op__insn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" 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1 \cr_a_ok$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 2 output 58 \xer_ov - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 2 \xer_ov$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 59 \xer_ov_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \xer_ov_ok$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 60 \xer_so$20 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \xer_so$20$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 61 \xer_so_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \xer_so_ok$next - cell \p$78 \p - connect \p_valid_i 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attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__rc__rc$81 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__rc__ok$82 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__oe__oe$83 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__oe__ok$84 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__invert_in$85 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__zero_a$86 - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \logical_op__input_carry$87 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__invert_out$88 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__write_cr0$89 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__output_carry$90 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__is_32bit$91 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__is_signed$92 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \logical_op__data_len$93 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \logical_op__insn$94 - process $group_60 - assign \logical_op__insn_type$77 7'0000000 - assign \logical_op__fn_unit$78 11'00000000000 - assign \logical_op__imm_data__data$79 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \logical_op__imm_data__ok$80 1'0 - assign \logical_op__rc__rc$81 1'0 - assign \logical_op__rc__ok$82 1'0 - assign \logical_op__oe__oe$83 1'0 - assign \logical_op__oe__ok$84 1'0 - assign \logical_op__invert_in$85 1'0 - assign \logical_op__zero_a$86 1'0 - assign \logical_op__input_carry$87 2'00 - assign \logical_op__invert_out$88 1'0 - assign \logical_op__write_cr0$89 1'0 - assign \logical_op__output_carry$90 1'0 - assign \logical_op__is_32bit$91 1'0 - assign \logical_op__is_signed$92 1'0 - assign \logical_op__data_len$93 4'0000 - assign \logical_op__insn$94 32'00000000000000000000000000000000 - assign { \logical_op__insn$94 \logical_op__data_len$93 \logical_op__is_signed$92 \logical_op__is_32bit$91 \logical_op__output_carry$90 \logical_op__write_cr0$89 \logical_op__invert_out$88 \logical_op__input_carry$87 \logical_op__zero_a$86 \logical_op__invert_in$85 { \logical_op__oe__ok$84 \logical_op__oe__oe$83 } { \logical_op__rc__ok$82 \logical_op__rc__rc$81 } { \logical_op__imm_data__ok$80 \logical_op__imm_data__data$79 } \logical_op__fn_unit$78 \logical_op__insn_type$77 } { \output_logical_op__insn$59 \output_logical_op__data_len$58 \output_logical_op__is_signed$57 \output_logical_op__is_32bit$56 \output_logical_op__output_carry$55 \output_logical_op__write_cr0$54 \output_logical_op__invert_out$53 \output_logical_op__input_carry$52 \output_logical_op__zero_a$51 \output_logical_op__invert_in$50 { \output_logical_op__oe__ok$49 \output_logical_op__oe__oe$48 } { \output_logical_op__rc__ok$47 \output_logical_op__rc__rc$46 } { \output_logical_op__imm_data__ok$45 \output_logical_op__imm_data__data$44 } \output_logical_op__fn_unit$43 \output_logical_op__insn_type$42 } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 \o$95 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \o_ok$96 - process $group_78 - assign \o$95 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \o_ok$96 1'0 - assign { \o_ok$96 \o$95 } { \output_o_ok$61 \output_o$60 } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 4 \cr_a$97 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \cr_a_ok$98 - process $group_80 - assign \cr_a$97 4'0000 - assign \cr_a_ok$98 1'0 - assign { \cr_a_ok$98 \cr_a$97 } { \output_cr_a_ok \output_cr_a$62 } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 2 \xer_ov$99 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \xer_ov_ok$100 - process $group_82 - assign \xer_ov$99 2'00 - assign \xer_ov_ok$100 1'0 - assign { \xer_ov_ok$100 \xer_ov$99 } { \output_xer_ov_ok \output_xer_ov$63 } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \xer_so$101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \xer_so_ok$102 - process $group_84 - assign \xer_so$101 1'0 - assign \xer_so_ok$102 1'0 - assign { \xer_so_ok$102 \xer_so$101 } { \output_xer_so_ok \output_xer_so$64 } - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615" - wire width 1 \r_busy - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615" - wire width 1 \r_busy$next - process $group_86 - assign \r_busy$next \r_busy - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign \r_busy$next 1'1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign \r_busy$next 1'0 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \r_busy$next 1'0 - end - sync init - update \r_busy 1'0 - sync posedge \coresync_clk - update \r_busy \r_busy$next - end - process $group_87 - assign \muxid$1$next \muxid$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign \muxid$1$next \muxid$76 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign \muxid$1$next \muxid$76 - end - sync init - update \muxid$1 2'00 - sync posedge \coresync_clk - update \muxid$1 \muxid$1$next - end - process $group_88 - assign \logical_op__insn_type$2$next \logical_op__insn_type$2 - assign \logical_op__fn_unit$3$next \logical_op__fn_unit$3 - assign \logical_op__imm_data__data$4$next \logical_op__imm_data__data$4 - assign \logical_op__imm_data__ok$5$next \logical_op__imm_data__ok$5 - assign \logical_op__rc__rc$6$next \logical_op__rc__rc$6 - assign \logical_op__rc__ok$7$next \logical_op__rc__ok$7 - assign \logical_op__oe__oe$8$next \logical_op__oe__oe$8 - assign \logical_op__oe__ok$9$next \logical_op__oe__ok$9 - assign \logical_op__invert_in$10$next \logical_op__invert_in$10 - assign \logical_op__zero_a$11$next \logical_op__zero_a$11 - assign \logical_op__input_carry$12$next \logical_op__input_carry$12 - assign \logical_op__invert_out$13$next \logical_op__invert_out$13 - assign \logical_op__write_cr0$14$next \logical_op__write_cr0$14 - assign \logical_op__output_carry$15$next \logical_op__output_carry$15 - assign \logical_op__is_32bit$16$next \logical_op__is_32bit$16 - assign \logical_op__is_signed$17$next \logical_op__is_signed$17 - assign \logical_op__data_len$18$next \logical_op__data_len$18 - assign \logical_op__insn$19$next \logical_op__insn$19 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign { \logical_op__insn$19$next \logical_op__data_len$18$next \logical_op__is_signed$17$next \logical_op__is_32bit$16$next \logical_op__output_carry$15$next \logical_op__write_cr0$14$next \logical_op__invert_out$13$next \logical_op__input_carry$12$next \logical_op__zero_a$11$next \logical_op__invert_in$10$next { \logical_op__oe__ok$9$next \logical_op__oe__oe$8$next } { \logical_op__rc__ok$7$next \logical_op__rc__rc$6$next } { \logical_op__imm_data__ok$5$next \logical_op__imm_data__data$4$next } \logical_op__fn_unit$3$next \logical_op__insn_type$2$next } { \logical_op__insn$94 \logical_op__data_len$93 \logical_op__is_signed$92 \logical_op__is_32bit$91 \logical_op__output_carry$90 \logical_op__write_cr0$89 \logical_op__invert_out$88 \logical_op__input_carry$87 \logical_op__zero_a$86 \logical_op__invert_in$85 { \logical_op__oe__ok$84 \logical_op__oe__oe$83 } { \logical_op__rc__ok$82 \logical_op__rc__rc$81 } { \logical_op__imm_data__ok$80 \logical_op__imm_data__data$79 } \logical_op__fn_unit$78 \logical_op__insn_type$77 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign { \logical_op__insn$19$next \logical_op__data_len$18$next \logical_op__is_signed$17$next \logical_op__is_32bit$16$next \logical_op__output_carry$15$next \logical_op__write_cr0$14$next \logical_op__invert_out$13$next \logical_op__input_carry$12$next \logical_op__zero_a$11$next \logical_op__invert_in$10$next { \logical_op__oe__ok$9$next \logical_op__oe__oe$8$next } { \logical_op__rc__ok$7$next \logical_op__rc__rc$6$next } { \logical_op__imm_data__ok$5$next \logical_op__imm_data__data$4$next } \logical_op__fn_unit$3$next \logical_op__insn_type$2$next } { \logical_op__insn$94 \logical_op__data_len$93 \logical_op__is_signed$92 \logical_op__is_32bit$91 \logical_op__output_carry$90 \logical_op__write_cr0$89 \logical_op__invert_out$88 \logical_op__input_carry$87 \logical_op__zero_a$86 \logical_op__invert_in$85 { \logical_op__oe__ok$84 \logical_op__oe__oe$83 } { \logical_op__rc__ok$82 \logical_op__rc__rc$81 } { \logical_op__imm_data__ok$80 \logical_op__imm_data__data$79 } \logical_op__fn_unit$78 \logical_op__insn_type$77 } - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \logical_op__imm_data__data$4$next 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \logical_op__imm_data__ok$5$next 1'0 - assign \logical_op__rc__rc$6$next 1'0 - assign \logical_op__rc__ok$7$next 1'0 - assign \logical_op__oe__oe$8$next 1'0 - assign \logical_op__oe__ok$9$next 1'0 - end - sync init - update \logical_op__insn_type$2 7'0000000 - update \logical_op__fn_unit$3 11'00000000000 - update \logical_op__imm_data__data$4 64'0000000000000000000000000000000000000000000000000000000000000000 - update \logical_op__imm_data__ok$5 1'0 - update \logical_op__rc__rc$6 1'0 - update \logical_op__rc__ok$7 1'0 - update \logical_op__oe__oe$8 1'0 - update \logical_op__oe__ok$9 1'0 - update \logical_op__invert_in$10 1'0 - update \logical_op__zero_a$11 1'0 - update \logical_op__input_carry$12 2'00 - update \logical_op__invert_out$13 1'0 - update \logical_op__write_cr0$14 1'0 - update \logical_op__output_carry$15 1'0 - update \logical_op__is_32bit$16 1'0 - update \logical_op__is_signed$17 1'0 - update \logical_op__data_len$18 4'0000 - update \logical_op__insn$19 32'00000000000000000000000000000000 - sync posedge \coresync_clk - update \logical_op__insn_type$2 \logical_op__insn_type$2$next - update \logical_op__fn_unit$3 \logical_op__fn_unit$3$next - update \logical_op__imm_data__data$4 \logical_op__imm_data__data$4$next - update \logical_op__imm_data__ok$5 \logical_op__imm_data__ok$5$next - update \logical_op__rc__rc$6 \logical_op__rc__rc$6$next - update \logical_op__rc__ok$7 \logical_op__rc__ok$7$next - update \logical_op__oe__oe$8 \logical_op__oe__oe$8$next - update \logical_op__oe__ok$9 \logical_op__oe__ok$9$next - update \logical_op__invert_in$10 \logical_op__invert_in$10$next - update \logical_op__zero_a$11 \logical_op__zero_a$11$next - update \logical_op__input_carry$12 \logical_op__input_carry$12$next - update \logical_op__invert_out$13 \logical_op__invert_out$13$next - update \logical_op__write_cr0$14 \logical_op__write_cr0$14$next - update \logical_op__output_carry$15 \logical_op__output_carry$15$next - update \logical_op__is_32bit$16 \logical_op__is_32bit$16$next - update \logical_op__is_signed$17 \logical_op__is_signed$17$next - update \logical_op__data_len$18 \logical_op__data_len$18$next - update \logical_op__insn$19 \logical_op__insn$19$next - end - process $group_106 - assign \o$next \o - assign \o_ok$next \o_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign { \o_ok$next \o$next } { \o_ok$96 \o$95 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign { \o_ok$next \o$next } { \o_ok$96 \o$95 } - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \o_ok$next 1'0 - end - sync init - update \o 64'0000000000000000000000000000000000000000000000000000000000000000 - update \o_ok 1'0 - sync posedge \coresync_clk - update \o \o$next - update \o_ok \o_ok$next - end - process $group_108 - assign \cr_a$next \cr_a - assign \cr_a_ok$next \cr_a_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign { \cr_a_ok$next \cr_a$next } { \cr_a_ok$98 \cr_a$97 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign { \cr_a_ok$next \cr_a$next } { \cr_a_ok$98 \cr_a$97 } - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \cr_a_ok$next 1'0 - end - sync init - update \cr_a 4'0000 - update \cr_a_ok 1'0 - sync posedge \coresync_clk - update \cr_a \cr_a$next - update \cr_a_ok \cr_a_ok$next - end - process $group_110 - assign \xer_ov$next \xer_ov - assign \xer_ov_ok$next \xer_ov_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign { \xer_ov_ok$next \xer_ov$next } { \xer_ov_ok$100 \xer_ov$99 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign { \xer_ov_ok$next \xer_ov$next } { \xer_ov_ok$100 \xer_ov$99 } - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \xer_ov_ok$next 1'0 - end - sync init - update \xer_ov 2'00 - update \xer_ov_ok 1'0 - sync posedge \coresync_clk - update \xer_ov \xer_ov$next - update \xer_ov_ok \xer_ov_ok$next - end - process $group_112 - assign \xer_so$20$next \xer_so$20 - assign \xer_so_ok$next \xer_so_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign { \xer_so_ok$next \xer_so$20$next } { \xer_so_ok$102 \xer_so$101 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign { \xer_so_ok$next \xer_so$20$next } { \xer_so_ok$102 \xer_so$101 } - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \xer_so_ok$next 1'0 - end - sync init - update \xer_so$20 1'0 - update \xer_so_ok 1'0 - sync posedge \coresync_clk - update \xer_so$20 \xer_so$20$next - update \xer_so_ok \xer_so_ok$next - end - process $group_114 - assign \n_valid_o 1'0 - assign \n_valid_o \r_busy - sync init - end - process $group_115 - assign \p_ready_o 1'0 - assign \p_ready_o \n_i_rdy_data - sync init - end - connect \cr_a$68 4'0000 - connect \cr_a_ok$69 1'0 - connect \xer_so_ok$72 1'0 -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_div0" -module \alu_div0 - attribute \src "simple/issuer.py:141" - wire width 1 input 0 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 1 \o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire 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\enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \pipe_start_logical_op__input_carry$13 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_start_logical_op__invert_out$14 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_start_logical_op__write_cr0$15 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_start_logical_op__output_carry$16 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_start_logical_op__is_32bit$17 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_start_logical_op__is_signed$18 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \pipe_start_logical_op__data_len$19 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \pipe_start_logical_op__insn$20 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \pipe_start_ra$21 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \pipe_start_rb$22 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 1 \pipe_start_xer_so$23 - cell \pipe_start \pipe_start - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \n_valid_o \pipe_start_n_valid_o - connect \n_ready_i \pipe_start_n_ready_i - connect \muxid \pipe_start_muxid - connect \logical_op__insn_type \pipe_start_logical_op__insn_type - connect \logical_op__fn_unit \pipe_start_logical_op__fn_unit - connect \logical_op__imm_data__data \pipe_start_logical_op__imm_data__data - connect \logical_op__imm_data__ok \pipe_start_logical_op__imm_data__ok - connect \logical_op__rc__rc \pipe_start_logical_op__rc__rc - connect \logical_op__rc__ok \pipe_start_logical_op__rc__ok - connect \logical_op__oe__oe \pipe_start_logical_op__oe__oe - connect \logical_op__oe__ok \pipe_start_logical_op__oe__ok - connect \logical_op__invert_in \pipe_start_logical_op__invert_in - connect \logical_op__zero_a \pipe_start_logical_op__zero_a - connect \logical_op__input_carry \pipe_start_logical_op__input_carry - connect \logical_op__invert_out \pipe_start_logical_op__invert_out - connect \logical_op__write_cr0 \pipe_start_logical_op__write_cr0 - connect \logical_op__output_carry \pipe_start_logical_op__output_carry - connect \logical_op__is_32bit \pipe_start_logical_op__is_32bit - connect \logical_op__is_signed \pipe_start_logical_op__is_signed - connect \logical_op__data_len \pipe_start_logical_op__data_len - connect \logical_op__insn \pipe_start_logical_op__insn - connect \ra \pipe_start_ra - connect \rb \pipe_start_rb - connect \xer_so \pipe_start_xer_so - connect \divisor_neg \pipe_start_divisor_neg - connect \dividend_neg \pipe_start_dividend_neg - connect \dive_abs_ov32 \pipe_start_dive_abs_ov32 - connect \dive_abs_ov64 \pipe_start_dive_abs_ov64 - connect \div_by_zero \pipe_start_div_by_zero - connect \dividend \pipe_start_dividend - connect \divisor_radicand \pipe_start_divisor_radicand - connect \operation \pipe_start_operation - connect \p_valid_i \pipe_start_p_valid_i - connect \p_ready_o \pipe_start_p_ready_o - connect \muxid$1 \pipe_start_muxid$2 - connect \logical_op__insn_type$2 \pipe_start_logical_op__insn_type$3 - connect \logical_op__fn_unit$3 \pipe_start_logical_op__fn_unit$4 - connect \logical_op__imm_data__data$4 \pipe_start_logical_op__imm_data__data$5 - connect \logical_op__imm_data__ok$5 \pipe_start_logical_op__imm_data__ok$6 - connect \logical_op__rc__rc$6 \pipe_start_logical_op__rc__rc$7 - connect \logical_op__rc__ok$7 \pipe_start_logical_op__rc__ok$8 - connect \logical_op__oe__oe$8 \pipe_start_logical_op__oe__oe$9 - connect \logical_op__oe__ok$9 \pipe_start_logical_op__oe__ok$10 - connect \logical_op__invert_in$10 \pipe_start_logical_op__invert_in$11 - connect \logical_op__zero_a$11 \pipe_start_logical_op__zero_a$12 - connect \logical_op__input_carry$12 \pipe_start_logical_op__input_carry$13 - connect \logical_op__invert_out$13 \pipe_start_logical_op__invert_out$14 - connect \logical_op__write_cr0$14 \pipe_start_logical_op__write_cr0$15 - connect \logical_op__output_carry$15 \pipe_start_logical_op__output_carry$16 - connect \logical_op__is_32bit$16 \pipe_start_logical_op__is_32bit$17 - connect \logical_op__is_signed$17 \pipe_start_logical_op__is_signed$18 - connect \logical_op__data_len$18 \pipe_start_logical_op__data_len$19 - connect \logical_op__insn$19 \pipe_start_logical_op__insn$20 - connect \ra$20 \pipe_start_ra$21 - connect \rb$21 \pipe_start_rb$22 - connect \xer_so$22 \pipe_start_xer_so$23 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" - wire width 1 \pipe_middle_0_p_valid_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" - wire width 1 \pipe_middle_0_p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \pipe_middle_0_muxid - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \pipe_middle_0_logical_op__insn_type - attribute \enum_base_type "Function" - attribute \enum_value_00000000000 "NONE" - attribute \enum_value_00000000010 "ALU" - attribute \enum_value_00000000100 "LDST" - attribute \enum_value_00000001000 "SHIFT_ROT" - attribute \enum_value_00000010000 "LOGICAL" - attribute \enum_value_00000100000 "BRANCH" - attribute \enum_value_00001000000 "CR" - attribute \enum_value_00010000000 "TRAP" - attribute \enum_value_00100000000 "MUL" - attribute \enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 \pipe_middle_0_logical_op__fn_unit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \pipe_middle_0_logical_op__imm_data__data - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_0_logical_op__imm_data__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_0_logical_op__rc__rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_0_logical_op__rc__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_0_logical_op__oe__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_0_logical_op__oe__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_0_logical_op__invert_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_0_logical_op__zero_a - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \pipe_middle_0_logical_op__input_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_0_logical_op__invert_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_0_logical_op__write_cr0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_0_logical_op__output_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_0_logical_op__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_0_logical_op__is_signed - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \pipe_middle_0_logical_op__data_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \pipe_middle_0_logical_op__insn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \pipe_middle_0_ra - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \pipe_middle_0_rb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 1 \pipe_middle_0_xer_so - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" - wire width 1 \pipe_middle_0_divisor_neg - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" - wire width 1 \pipe_middle_0_dividend_neg - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" - wire width 1 \pipe_middle_0_dive_abs_ov32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" - wire width 1 \pipe_middle_0_dive_abs_ov64 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" - wire width 1 \pipe_middle_0_div_by_zero - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:18" - wire width 128 \pipe_middle_0_dividend - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:19" - wire width 64 \pipe_middle_0_divisor_radicand - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:21" - wire width 2 \pipe_middle_0_operation - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" - wire width 1 \pipe_middle_0_n_valid_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" - wire width 1 \pipe_middle_0_n_ready_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \pipe_middle_0_muxid$24 - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute 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"/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_0_logical_op__oe__ok$32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_0_logical_op__invert_in$33 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_0_logical_op__zero_a$34 - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \pipe_middle_0_logical_op__input_carry$35 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_0_logical_op__invert_out$36 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_0_logical_op__write_cr0$37 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_0_logical_op__output_carry$38 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_0_logical_op__is_32bit$39 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_middle_0_logical_op__is_signed$40 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \pipe_middle_0_logical_op__data_len$41 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \pipe_middle_0_logical_op__insn$42 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \pipe_middle_0_ra$43 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \pipe_middle_0_rb$44 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 1 \pipe_middle_0_xer_so$45 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" - wire width 1 \pipe_middle_0_divisor_neg$46 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" - wire width 1 \pipe_middle_0_dividend_neg$47 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" - wire width 1 \pipe_middle_0_dive_abs_ov32$48 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" - wire width 1 \pipe_middle_0_dive_abs_ov64$49 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" - wire width 1 \pipe_middle_0_div_by_zero$50 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:40" - wire width 64 \pipe_middle_0_quotient_root - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:41" - wire width 192 \pipe_middle_0_remainder - cell \pipe_middle_0 \pipe_middle_0 - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \p_valid_i \pipe_middle_0_p_valid_i - connect \p_ready_o \pipe_middle_0_p_ready_o - connect \muxid \pipe_middle_0_muxid - connect \logical_op__insn_type \pipe_middle_0_logical_op__insn_type - connect \logical_op__fn_unit \pipe_middle_0_logical_op__fn_unit - connect \logical_op__imm_data__data \pipe_middle_0_logical_op__imm_data__data - connect \logical_op__imm_data__ok \pipe_middle_0_logical_op__imm_data__ok - connect \logical_op__rc__rc \pipe_middle_0_logical_op__rc__rc - connect \logical_op__rc__ok \pipe_middle_0_logical_op__rc__ok - connect \logical_op__oe__oe \pipe_middle_0_logical_op__oe__oe - connect \logical_op__oe__ok \pipe_middle_0_logical_op__oe__ok - connect \logical_op__invert_in \pipe_middle_0_logical_op__invert_in - connect \logical_op__zero_a \pipe_middle_0_logical_op__zero_a - connect \logical_op__input_carry \pipe_middle_0_logical_op__input_carry - connect \logical_op__invert_out \pipe_middle_0_logical_op__invert_out - connect \logical_op__write_cr0 \pipe_middle_0_logical_op__write_cr0 - connect \logical_op__output_carry \pipe_middle_0_logical_op__output_carry - connect \logical_op__is_32bit \pipe_middle_0_logical_op__is_32bit - connect \logical_op__is_signed \pipe_middle_0_logical_op__is_signed - connect \logical_op__data_len \pipe_middle_0_logical_op__data_len - connect \logical_op__insn \pipe_middle_0_logical_op__insn - connect \ra \pipe_middle_0_ra - connect \rb \pipe_middle_0_rb - connect \xer_so \pipe_middle_0_xer_so - connect \divisor_neg \pipe_middle_0_divisor_neg - connect \dividend_neg \pipe_middle_0_dividend_neg - connect \dive_abs_ov32 \pipe_middle_0_dive_abs_ov32 - connect \dive_abs_ov64 \pipe_middle_0_dive_abs_ov64 - connect \div_by_zero \pipe_middle_0_div_by_zero - connect \dividend \pipe_middle_0_dividend - connect \divisor_radicand \pipe_middle_0_divisor_radicand - connect \operation \pipe_middle_0_operation - connect \n_valid_o \pipe_middle_0_n_valid_o - connect \n_ready_i \pipe_middle_0_n_ready_i - connect \muxid$1 \pipe_middle_0_muxid$24 - connect \logical_op__insn_type$2 \pipe_middle_0_logical_op__insn_type$25 - connect \logical_op__fn_unit$3 \pipe_middle_0_logical_op__fn_unit$26 - connect \logical_op__imm_data__data$4 \pipe_middle_0_logical_op__imm_data__data$27 - connect \logical_op__imm_data__ok$5 \pipe_middle_0_logical_op__imm_data__ok$28 - connect \logical_op__rc__rc$6 \pipe_middle_0_logical_op__rc__rc$29 - connect \logical_op__rc__ok$7 \pipe_middle_0_logical_op__rc__ok$30 - connect \logical_op__oe__oe$8 \pipe_middle_0_logical_op__oe__oe$31 - connect \logical_op__oe__ok$9 \pipe_middle_0_logical_op__oe__ok$32 - connect \logical_op__invert_in$10 \pipe_middle_0_logical_op__invert_in$33 - connect \logical_op__zero_a$11 \pipe_middle_0_logical_op__zero_a$34 - connect \logical_op__input_carry$12 \pipe_middle_0_logical_op__input_carry$35 - connect \logical_op__invert_out$13 \pipe_middle_0_logical_op__invert_out$36 - connect \logical_op__write_cr0$14 \pipe_middle_0_logical_op__write_cr0$37 - connect \logical_op__output_carry$15 \pipe_middle_0_logical_op__output_carry$38 - connect \logical_op__is_32bit$16 \pipe_middle_0_logical_op__is_32bit$39 - connect \logical_op__is_signed$17 \pipe_middle_0_logical_op__is_signed$40 - connect \logical_op__data_len$18 \pipe_middle_0_logical_op__data_len$41 - connect \logical_op__insn$19 \pipe_middle_0_logical_op__insn$42 - connect \ra$20 \pipe_middle_0_ra$43 - connect \rb$21 \pipe_middle_0_rb$44 - connect \xer_so$22 \pipe_middle_0_xer_so$45 - connect \divisor_neg$23 \pipe_middle_0_divisor_neg$46 - connect \dividend_neg$24 \pipe_middle_0_dividend_neg$47 - connect \dive_abs_ov32$25 \pipe_middle_0_dive_abs_ov32$48 - connect \dive_abs_ov64$26 \pipe_middle_0_dive_abs_ov64$49 - connect \div_by_zero$27 \pipe_middle_0_div_by_zero$50 - connect \quotient_root \pipe_middle_0_quotient_root - connect \remainder \pipe_middle_0_remainder - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" - wire width 1 \pipe_end_p_valid_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" - wire width 1 \pipe_end_p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \pipe_end_muxid - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \pipe_end_logical_op__insn_type - attribute \enum_base_type "Function" - attribute \enum_value_00000000000 "NONE" - attribute \enum_value_00000000010 "ALU" - attribute \enum_value_00000000100 "LDST" - attribute \enum_value_00000001000 "SHIFT_ROT" - attribute \enum_value_00000010000 "LOGICAL" - attribute \enum_value_00000100000 "BRANCH" - attribute \enum_value_00001000000 "CR" - attribute \enum_value_00010000000 "TRAP" - attribute \enum_value_00100000000 "MUL" - attribute \enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 \pipe_end_logical_op__fn_unit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \pipe_end_logical_op__imm_data__data - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_end_logical_op__imm_data__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_end_logical_op__rc__rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_end_logical_op__rc__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_end_logical_op__oe__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_end_logical_op__oe__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_end_logical_op__invert_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_end_logical_op__zero_a - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \pipe_end_logical_op__input_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_end_logical_op__invert_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_end_logical_op__write_cr0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_end_logical_op__output_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_end_logical_op__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_end_logical_op__is_signed - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \pipe_end_logical_op__data_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \pipe_end_logical_op__insn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \pipe_end_ra - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \pipe_end_rb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 1 \pipe_end_xer_so - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:160" - wire width 1 \pipe_end_divisor_neg - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:161" - wire width 1 \pipe_end_dividend_neg - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:167" - wire width 1 \pipe_end_dive_abs_ov32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:168" - wire width 1 \pipe_end_dive_abs_ov64 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/pipe_data.py:162" - wire width 1 \pipe_end_div_by_zero - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:40" - wire width 64 \pipe_end_quotient_root - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/div/fsm.py:41" - wire width 192 \pipe_end_remainder - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" - wire width 1 \pipe_end_n_valid_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" - wire width 1 \pipe_end_n_ready_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \pipe_end_muxid$51 - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute 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attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \pipe_end_logical_op__insn_type$52 - attribute \enum_base_type "Function" - attribute \enum_value_00000000000 "NONE" - attribute \enum_value_00000000010 "ALU" - attribute \enum_value_00000000100 "LDST" - attribute \enum_value_00000001000 "SHIFT_ROT" - attribute \enum_value_00000010000 "LOGICAL" - attribute \enum_value_00000100000 "BRANCH" - attribute \enum_value_00001000000 "CR" - attribute \enum_value_00010000000 "TRAP" - attribute \enum_value_00100000000 "MUL" - attribute \enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 \pipe_end_logical_op__fn_unit$53 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \pipe_end_logical_op__imm_data__data$54 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_end_logical_op__imm_data__ok$55 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_end_logical_op__rc__rc$56 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_end_logical_op__rc__ok$57 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_end_logical_op__oe__oe$58 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_end_logical_op__oe__ok$59 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_end_logical_op__invert_in$60 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_end_logical_op__zero_a$61 - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \pipe_end_logical_op__input_carry$62 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_end_logical_op__invert_out$63 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_end_logical_op__write_cr0$64 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_end_logical_op__output_carry$65 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_end_logical_op__is_32bit$66 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe_end_logical_op__is_signed$67 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \pipe_end_logical_op__data_len$68 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \pipe_end_logical_op__insn$69 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 \pipe_end_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \pipe_end_o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 4 \pipe_end_cr_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \pipe_end_cr_a_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 2 \pipe_end_xer_ov - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \pipe_end_xer_ov_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \pipe_end_xer_so$70 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \pipe_end_xer_so_ok - cell \pipe_end \pipe_end - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \p_valid_i \pipe_end_p_valid_i - connect \p_ready_o \pipe_end_p_ready_o - connect \muxid \pipe_end_muxid - connect \logical_op__insn_type \pipe_end_logical_op__insn_type - connect \logical_op__fn_unit \pipe_end_logical_op__fn_unit - connect \logical_op__imm_data__data \pipe_end_logical_op__imm_data__data - connect \logical_op__imm_data__ok \pipe_end_logical_op__imm_data__ok - connect \logical_op__rc__rc \pipe_end_logical_op__rc__rc - connect \logical_op__rc__ok \pipe_end_logical_op__rc__ok - connect \logical_op__oe__oe \pipe_end_logical_op__oe__oe - connect \logical_op__oe__ok \pipe_end_logical_op__oe__ok - connect \logical_op__invert_in \pipe_end_logical_op__invert_in - connect \logical_op__zero_a \pipe_end_logical_op__zero_a - connect \logical_op__input_carry \pipe_end_logical_op__input_carry - connect \logical_op__invert_out \pipe_end_logical_op__invert_out - connect \logical_op__write_cr0 \pipe_end_logical_op__write_cr0 - connect \logical_op__output_carry \pipe_end_logical_op__output_carry - connect \logical_op__is_32bit \pipe_end_logical_op__is_32bit - connect \logical_op__is_signed \pipe_end_logical_op__is_signed - connect \logical_op__data_len \pipe_end_logical_op__data_len - connect \logical_op__insn \pipe_end_logical_op__insn - connect \ra \pipe_end_ra - connect \rb \pipe_end_rb - connect \xer_so \pipe_end_xer_so - connect \divisor_neg \pipe_end_divisor_neg - connect \dividend_neg \pipe_end_dividend_neg - connect \dive_abs_ov32 \pipe_end_dive_abs_ov32 - connect \dive_abs_ov64 \pipe_end_dive_abs_ov64 - connect \div_by_zero \pipe_end_div_by_zero - connect \quotient_root \pipe_end_quotient_root - connect \remainder \pipe_end_remainder - connect \n_valid_o \pipe_end_n_valid_o - connect \n_ready_i \pipe_end_n_ready_i - connect \muxid$1 \pipe_end_muxid$51 - connect \logical_op__insn_type$2 \pipe_end_logical_op__insn_type$52 - connect \logical_op__fn_unit$3 \pipe_end_logical_op__fn_unit$53 - connect \logical_op__imm_data__data$4 \pipe_end_logical_op__imm_data__data$54 - connect \logical_op__imm_data__ok$5 \pipe_end_logical_op__imm_data__ok$55 - connect \logical_op__rc__rc$6 \pipe_end_logical_op__rc__rc$56 - connect \logical_op__rc__ok$7 \pipe_end_logical_op__rc__ok$57 - connect \logical_op__oe__oe$8 \pipe_end_logical_op__oe__oe$58 - connect \logical_op__oe__ok$9 \pipe_end_logical_op__oe__ok$59 - connect \logical_op__invert_in$10 \pipe_end_logical_op__invert_in$60 - connect \logical_op__zero_a$11 \pipe_end_logical_op__zero_a$61 - connect \logical_op__input_carry$12 \pipe_end_logical_op__input_carry$62 - connect \logical_op__invert_out$13 \pipe_end_logical_op__invert_out$63 - connect \logical_op__write_cr0$14 \pipe_end_logical_op__write_cr0$64 - connect \logical_op__output_carry$15 \pipe_end_logical_op__output_carry$65 - connect \logical_op__is_32bit$16 \pipe_end_logical_op__is_32bit$66 - connect \logical_op__is_signed$17 \pipe_end_logical_op__is_signed$67 - connect \logical_op__data_len$18 \pipe_end_logical_op__data_len$68 - connect \logical_op__insn$19 \pipe_end_logical_op__insn$69 - connect \o \pipe_end_o - connect \o_ok \pipe_end_o_ok - connect \cr_a \pipe_end_cr_a - connect \cr_a_ok \pipe_end_cr_a_ok - connect \xer_ov \pipe_end_xer_ov - connect \xer_ov_ok \pipe_end_xer_ov_ok - connect \xer_so$20 \pipe_end_xer_so$70 - connect \xer_so_ok \pipe_end_xer_so_ok - end - process $group_0 - assign \pipe_middle_0_p_valid_i 1'0 - assign \pipe_middle_0_p_valid_i \pipe_start_n_valid_o - sync init - end - process $group_1 - assign \pipe_start_n_ready_i 1'0 - assign \pipe_start_n_ready_i \pipe_middle_0_p_ready_o - sync init - end - process $group_2 - assign \pipe_middle_0_muxid 2'00 - assign \pipe_middle_0_muxid \pipe_start_muxid - sync init - end - process $group_3 - assign \pipe_middle_0_logical_op__insn_type 7'0000000 - assign \pipe_middle_0_logical_op__fn_unit 11'00000000000 - assign \pipe_middle_0_logical_op__imm_data__data 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \pipe_middle_0_logical_op__imm_data__ok 1'0 - assign \pipe_middle_0_logical_op__rc__rc 1'0 - assign \pipe_middle_0_logical_op__rc__ok 1'0 - assign \pipe_middle_0_logical_op__oe__oe 1'0 - assign \pipe_middle_0_logical_op__oe__ok 1'0 - assign \pipe_middle_0_logical_op__invert_in 1'0 - assign \pipe_middle_0_logical_op__zero_a 1'0 - assign \pipe_middle_0_logical_op__input_carry 2'00 - assign \pipe_middle_0_logical_op__invert_out 1'0 - assign \pipe_middle_0_logical_op__write_cr0 1'0 - assign \pipe_middle_0_logical_op__output_carry 1'0 - assign \pipe_middle_0_logical_op__is_32bit 1'0 - assign \pipe_middle_0_logical_op__is_signed 1'0 - assign \pipe_middle_0_logical_op__data_len 4'0000 - assign \pipe_middle_0_logical_op__insn 32'00000000000000000000000000000000 - assign { \pipe_middle_0_logical_op__insn \pipe_middle_0_logical_op__data_len \pipe_middle_0_logical_op__is_signed \pipe_middle_0_logical_op__is_32bit \pipe_middle_0_logical_op__output_carry \pipe_middle_0_logical_op__write_cr0 \pipe_middle_0_logical_op__invert_out \pipe_middle_0_logical_op__input_carry \pipe_middle_0_logical_op__zero_a \pipe_middle_0_logical_op__invert_in { \pipe_middle_0_logical_op__oe__ok \pipe_middle_0_logical_op__oe__oe } { \pipe_middle_0_logical_op__rc__ok \pipe_middle_0_logical_op__rc__rc } { \pipe_middle_0_logical_op__imm_data__ok \pipe_middle_0_logical_op__imm_data__data } \pipe_middle_0_logical_op__fn_unit \pipe_middle_0_logical_op__insn_type } { \pipe_start_logical_op__insn \pipe_start_logical_op__data_len \pipe_start_logical_op__is_signed \pipe_start_logical_op__is_32bit \pipe_start_logical_op__output_carry \pipe_start_logical_op__write_cr0 \pipe_start_logical_op__invert_out \pipe_start_logical_op__input_carry \pipe_start_logical_op__zero_a \pipe_start_logical_op__invert_in { \pipe_start_logical_op__oe__ok \pipe_start_logical_op__oe__oe } { \pipe_start_logical_op__rc__ok \pipe_start_logical_op__rc__rc } { \pipe_start_logical_op__imm_data__ok \pipe_start_logical_op__imm_data__data } \pipe_start_logical_op__fn_unit \pipe_start_logical_op__insn_type } - sync init - end - process $group_21 - assign \pipe_middle_0_ra 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \pipe_middle_0_ra \pipe_start_ra - sync init - end - process $group_22 - assign \pipe_middle_0_rb 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \pipe_middle_0_rb \pipe_start_rb - sync init - end - process $group_23 - assign \pipe_middle_0_xer_so 1'0 - assign \pipe_middle_0_xer_so \pipe_start_xer_so - sync init - end - process $group_24 - assign \pipe_middle_0_divisor_neg 1'0 - assign \pipe_middle_0_divisor_neg \pipe_start_divisor_neg - sync init - end - process $group_25 - assign \pipe_middle_0_dividend_neg 1'0 - assign \pipe_middle_0_dividend_neg \pipe_start_dividend_neg - sync init - end - process $group_26 - assign \pipe_middle_0_dive_abs_ov32 1'0 - assign \pipe_middle_0_dive_abs_ov32 \pipe_start_dive_abs_ov32 - sync init - end - process $group_27 - assign \pipe_middle_0_dive_abs_ov64 1'0 - assign \pipe_middle_0_dive_abs_ov64 \pipe_start_dive_abs_ov64 - sync init - end - process $group_28 - assign \pipe_middle_0_div_by_zero 1'0 - assign \pipe_middle_0_div_by_zero \pipe_start_div_by_zero - sync init - end - process $group_29 - assign \pipe_middle_0_dividend 128'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \pipe_middle_0_dividend \pipe_start_dividend - sync init - end - process $group_30 - assign \pipe_middle_0_divisor_radicand 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \pipe_middle_0_divisor_radicand \pipe_start_divisor_radicand - sync init - end - process $group_31 - assign \pipe_middle_0_operation 2'00 - assign \pipe_middle_0_operation \pipe_start_operation - sync init - end - process $group_32 - assign \pipe_end_p_valid_i 1'0 - assign \pipe_end_p_valid_i \pipe_middle_0_n_valid_o - sync init - end - process $group_33 - assign \pipe_middle_0_n_ready_i 1'0 - assign \pipe_middle_0_n_ready_i \pipe_end_p_ready_o - sync init - end - process $group_34 - assign \pipe_end_muxid 2'00 - assign \pipe_end_muxid \pipe_middle_0_muxid$24 - sync init - end - process $group_35 - assign \pipe_end_logical_op__insn_type 7'0000000 - assign \pipe_end_logical_op__fn_unit 11'00000000000 - assign \pipe_end_logical_op__imm_data__data 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \pipe_end_logical_op__imm_data__ok 1'0 - assign \pipe_end_logical_op__rc__rc 1'0 - assign \pipe_end_logical_op__rc__ok 1'0 - assign \pipe_end_logical_op__oe__oe 1'0 - assign \pipe_end_logical_op__oe__ok 1'0 - assign \pipe_end_logical_op__invert_in 1'0 - assign \pipe_end_logical_op__zero_a 1'0 - assign \pipe_end_logical_op__input_carry 2'00 - assign \pipe_end_logical_op__invert_out 1'0 - assign \pipe_end_logical_op__write_cr0 1'0 - assign \pipe_end_logical_op__output_carry 1'0 - assign \pipe_end_logical_op__is_32bit 1'0 - assign \pipe_end_logical_op__is_signed 1'0 - assign \pipe_end_logical_op__data_len 4'0000 - assign \pipe_end_logical_op__insn 32'00000000000000000000000000000000 - assign { \pipe_end_logical_op__insn \pipe_end_logical_op__data_len \pipe_end_logical_op__is_signed \pipe_end_logical_op__is_32bit \pipe_end_logical_op__output_carry \pipe_end_logical_op__write_cr0 \pipe_end_logical_op__invert_out \pipe_end_logical_op__input_carry \pipe_end_logical_op__zero_a \pipe_end_logical_op__invert_in { \pipe_end_logical_op__oe__ok \pipe_end_logical_op__oe__oe } { \pipe_end_logical_op__rc__ok \pipe_end_logical_op__rc__rc } { \pipe_end_logical_op__imm_data__ok \pipe_end_logical_op__imm_data__data } \pipe_end_logical_op__fn_unit \pipe_end_logical_op__insn_type } { \pipe_middle_0_logical_op__insn$42 \pipe_middle_0_logical_op__data_len$41 \pipe_middle_0_logical_op__is_signed$40 \pipe_middle_0_logical_op__is_32bit$39 \pipe_middle_0_logical_op__output_carry$38 \pipe_middle_0_logical_op__write_cr0$37 \pipe_middle_0_logical_op__invert_out$36 \pipe_middle_0_logical_op__input_carry$35 \pipe_middle_0_logical_op__zero_a$34 \pipe_middle_0_logical_op__invert_in$33 { \pipe_middle_0_logical_op__oe__ok$32 \pipe_middle_0_logical_op__oe__oe$31 } { \pipe_middle_0_logical_op__rc__ok$30 \pipe_middle_0_logical_op__rc__rc$29 } { \pipe_middle_0_logical_op__imm_data__ok$28 \pipe_middle_0_logical_op__imm_data__data$27 } \pipe_middle_0_logical_op__fn_unit$26 \pipe_middle_0_logical_op__insn_type$25 } - sync init - end - process $group_53 - assign \pipe_end_ra 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \pipe_end_ra \pipe_middle_0_ra$43 - sync init - end - process $group_54 - assign \pipe_end_rb 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \pipe_end_rb \pipe_middle_0_rb$44 - sync init - end - process $group_55 - assign \pipe_end_xer_so 1'0 - assign \pipe_end_xer_so \pipe_middle_0_xer_so$45 - sync init - end - process $group_56 - assign \pipe_end_divisor_neg 1'0 - assign \pipe_end_divisor_neg \pipe_middle_0_divisor_neg$46 - sync init - end - process $group_57 - assign \pipe_end_dividend_neg 1'0 - assign \pipe_end_dividend_neg \pipe_middle_0_dividend_neg$47 - sync init - end - process $group_58 - assign \pipe_end_dive_abs_ov32 1'0 - assign \pipe_end_dive_abs_ov32 \pipe_middle_0_dive_abs_ov32$48 - sync init - end - process $group_59 - assign \pipe_end_dive_abs_ov64 1'0 - assign \pipe_end_dive_abs_ov64 \pipe_middle_0_dive_abs_ov64$49 - sync init - end - process $group_60 - assign \pipe_end_div_by_zero 1'0 - assign \pipe_end_div_by_zero \pipe_middle_0_div_by_zero$50 - sync init - end - process $group_61 - assign \pipe_end_quotient_root 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \pipe_end_quotient_root \pipe_middle_0_quotient_root - sync init - end - process $group_62 - assign \pipe_end_remainder 192'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \pipe_end_remainder \pipe_middle_0_remainder - sync init - end - process $group_63 - assign \pipe_start_p_valid_i 1'0 - assign \pipe_start_p_valid_i \p_valid_i - sync init - end - process $group_64 - assign \p_ready_o 1'0 - assign \p_ready_o \pipe_start_p_ready_o - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \muxid - process $group_65 - assign \pipe_start_muxid$2 2'00 - assign \pipe_start_muxid$2 \muxid - sync init - end - process $group_66 - assign \pipe_start_logical_op__insn_type$3 7'0000000 - assign \pipe_start_logical_op__fn_unit$4 11'00000000000 - assign \pipe_start_logical_op__imm_data__data$5 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \pipe_start_logical_op__imm_data__ok$6 1'0 - assign \pipe_start_logical_op__rc__rc$7 1'0 - assign \pipe_start_logical_op__rc__ok$8 1'0 - assign \pipe_start_logical_op__oe__oe$9 1'0 - assign \pipe_start_logical_op__oe__ok$10 1'0 - assign \pipe_start_logical_op__invert_in$11 1'0 - assign \pipe_start_logical_op__zero_a$12 1'0 - assign \pipe_start_logical_op__input_carry$13 2'00 - assign \pipe_start_logical_op__invert_out$14 1'0 - assign \pipe_start_logical_op__write_cr0$15 1'0 - assign \pipe_start_logical_op__output_carry$16 1'0 - assign \pipe_start_logical_op__is_32bit$17 1'0 - assign \pipe_start_logical_op__is_signed$18 1'0 - assign \pipe_start_logical_op__data_len$19 4'0000 - assign \pipe_start_logical_op__insn$20 32'00000000000000000000000000000000 - assign { \pipe_start_logical_op__insn$20 \pipe_start_logical_op__data_len$19 \pipe_start_logical_op__is_signed$18 \pipe_start_logical_op__is_32bit$17 \pipe_start_logical_op__output_carry$16 \pipe_start_logical_op__write_cr0$15 \pipe_start_logical_op__invert_out$14 \pipe_start_logical_op__input_carry$13 \pipe_start_logical_op__zero_a$12 \pipe_start_logical_op__invert_in$11 { \pipe_start_logical_op__oe__ok$10 \pipe_start_logical_op__oe__oe$9 } { \pipe_start_logical_op__rc__ok$8 \pipe_start_logical_op__rc__rc$7 } { \pipe_start_logical_op__imm_data__ok$6 \pipe_start_logical_op__imm_data__data$5 } \pipe_start_logical_op__fn_unit$4 \pipe_start_logical_op__insn_type$3 } { \logical_op__insn \logical_op__data_len \logical_op__is_signed \logical_op__is_32bit \logical_op__output_carry \logical_op__write_cr0 \logical_op__invert_out \logical_op__input_carry \logical_op__zero_a \logical_op__invert_in { \logical_op__oe__ok \logical_op__oe__oe } { \logical_op__rc__ok \logical_op__rc__rc } { \logical_op__imm_data__ok \logical_op__imm_data__data } \logical_op__fn_unit \logical_op__insn_type } - sync init - end - process $group_84 - assign \pipe_start_ra$21 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \pipe_start_ra$21 \ra - sync init - end - process $group_85 - assign \pipe_start_rb$22 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \pipe_start_rb$22 \rb - sync init - end - process $group_86 - assign \pipe_start_xer_so$23 1'0 - assign \pipe_start_xer_so$23 \xer_so$1 - sync init - end - process $group_87 - assign \n_valid_o 1'0 - assign \n_valid_o \pipe_end_n_valid_o - sync init - end - process $group_88 - assign \pipe_end_n_ready_i 1'0 - assign \pipe_end_n_ready_i \n_ready_i - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \muxid$71 - process $group_89 - assign \muxid$71 2'00 - assign \muxid$71 \pipe_end_muxid$51 - sync init - end - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \logical_op__insn_type$72 - attribute \enum_base_type "Function" - attribute \enum_value_00000000000 "NONE" - attribute \enum_value_00000000010 "ALU" - attribute \enum_value_00000000100 "LDST" - attribute \enum_value_00000001000 "SHIFT_ROT" - attribute \enum_value_00000010000 "LOGICAL" - attribute \enum_value_00000100000 "BRANCH" - attribute \enum_value_00001000000 "CR" - attribute \enum_value_00010000000 "TRAP" - attribute \enum_value_00100000000 "MUL" - attribute \enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 \logical_op__fn_unit$73 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \logical_op__imm_data__data$74 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__imm_data__ok$75 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__rc__rc$76 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__rc__ok$77 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__oe__oe$78 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__oe__ok$79 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__invert_in$80 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__zero_a$81 - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \logical_op__input_carry$82 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__invert_out$83 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__write_cr0$84 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__output_carry$85 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__is_32bit$86 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \logical_op__is_signed$87 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \logical_op__data_len$88 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \logical_op__insn$89 - process $group_90 - assign \logical_op__insn_type$72 7'0000000 - assign \logical_op__fn_unit$73 11'00000000000 - assign \logical_op__imm_data__data$74 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \logical_op__imm_data__ok$75 1'0 - assign \logical_op__rc__rc$76 1'0 - assign \logical_op__rc__ok$77 1'0 - assign \logical_op__oe__oe$78 1'0 - assign \logical_op__oe__ok$79 1'0 - assign \logical_op__invert_in$80 1'0 - assign \logical_op__zero_a$81 1'0 - assign \logical_op__input_carry$82 2'00 - assign \logical_op__invert_out$83 1'0 - assign \logical_op__write_cr0$84 1'0 - assign \logical_op__output_carry$85 1'0 - assign \logical_op__is_32bit$86 1'0 - assign \logical_op__is_signed$87 1'0 - assign \logical_op__data_len$88 4'0000 - assign \logical_op__insn$89 32'00000000000000000000000000000000 - assign { \logical_op__insn$89 \logical_op__data_len$88 \logical_op__is_signed$87 \logical_op__is_32bit$86 \logical_op__output_carry$85 \logical_op__write_cr0$84 \logical_op__invert_out$83 \logical_op__input_carry$82 \logical_op__zero_a$81 \logical_op__invert_in$80 { \logical_op__oe__ok$79 \logical_op__oe__oe$78 } { \logical_op__rc__ok$77 \logical_op__rc__rc$76 } { \logical_op__imm_data__ok$75 \logical_op__imm_data__data$74 } \logical_op__fn_unit$73 \logical_op__insn_type$72 } { \pipe_end_logical_op__insn$69 \pipe_end_logical_op__data_len$68 \pipe_end_logical_op__is_signed$67 \pipe_end_logical_op__is_32bit$66 \pipe_end_logical_op__output_carry$65 \pipe_end_logical_op__write_cr0$64 \pipe_end_logical_op__invert_out$63 \pipe_end_logical_op__input_carry$62 \pipe_end_logical_op__zero_a$61 \pipe_end_logical_op__invert_in$60 { \pipe_end_logical_op__oe__ok$59 \pipe_end_logical_op__oe__oe$58 } { \pipe_end_logical_op__rc__ok$57 \pipe_end_logical_op__rc__rc$56 } { \pipe_end_logical_op__imm_data__ok$55 \pipe_end_logical_op__imm_data__data$54 } \pipe_end_logical_op__fn_unit$53 \pipe_end_logical_op__insn_type$52 } - sync init - end - process $group_108 - assign \o 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \o_ok 1'0 - assign { \o_ok \o } { \pipe_end_o_ok \pipe_end_o } - sync init - end - process $group_110 - assign \cr_a 4'0000 - assign \cr_a_ok 1'0 - assign { \cr_a_ok \cr_a } { \pipe_end_cr_a_ok \pipe_end_cr_a } - sync init - end - process $group_112 - assign \xer_ov 2'00 - assign \xer_ov_ok 1'0 - assign { \xer_ov_ok \xer_ov } { \pipe_end_xer_ov_ok \pipe_end_xer_ov } - sync init - end - process $group_114 - assign \xer_so 1'0 - assign \xer_so_ok 1'0 - assign { \xer_so_ok \xer_so } { \pipe_end_xer_so_ok \pipe_end_xer_so$70 } - sync init - end - connect \muxid 2'00 -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.div0.src_l" -module \src_l$81 - attribute \src "simple/issuer.py:141" - wire width 1 input 0 \coresync_clk - attribute \src "simple/issuer.py:141" - wire width 1 input 1 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 3 input 2 \s_src - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 3 input 3 \r_src - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire width 3 output 4 \q_src - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire width 3 \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire width 3 \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 3 $1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A \r_src - connect \Y $1 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 3 $3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $4 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A \q_int - connect \B $1 - connect \Y $3 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 3 $5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $6 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A $3 - connect \B \s_src - connect \Y $5 - end - process $group_0 - assign \q_int$next \q_int - assign \q_int$next $5 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \q_int$next 3'000 - end - sync init - update \q_int 3'000 - sync posedge \coresync_clk - update \q_int \q_int$next - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 3 $7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $8 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A \r_src - connect \Y $7 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 3 $9 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $10 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A \q_int - connect \B $7 - connect \Y $9 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 3 $11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $12 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A $9 - connect \B \s_src - connect \Y $11 - end - process $group_1 - assign \q_src 3'000 - assign \q_src $11 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" - wire width 3 \qn_src - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - wire width 3 $13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $14 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A \q_src - connect \Y $13 - end - process $group_2 - assign \qn_src 3'000 - assign \qn_src $13 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" - wire width 3 \qlq_src - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - wire width 3 $15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $16 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A \q_src - connect \B \q_int - connect \Y $15 - end - process $group_3 - assign \qlq_src 3'000 - assign \qlq_src $15 - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.div0.opc_l" -module \opc_l$82 - attribute \src "simple/issuer.py:141" - wire width 1 input 0 \coresync_clk - attribute \src "simple/issuer.py:141" - wire width 1 input 1 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 1 input 2 \s_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 1 input 3 \r_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire width 1 output 4 \q_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire width 1 \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire width 1 \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_opc - connect \Y $1 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 1 $3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $4 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B $1 - connect \Y $3 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 1 $5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $6 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $3 - connect \B \s_opc - connect \Y $5 - end - process $group_0 - assign \q_int$next \q_int - assign \q_int$next $5 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \q_int$next 1'0 - end - sync init - update \q_int 1'0 - sync posedge \coresync_clk - update \q_int \q_int$next - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 1 $7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $8 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_opc - connect \Y $7 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 1 $9 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $10 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B $7 - connect \Y $9 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 1 $11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $12 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $9 - connect \B \s_opc - connect \Y $11 - end - process $group_1 - assign \q_opc 1'0 - assign \q_opc $11 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" - wire width 1 \qn_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - wire width 1 $13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $14 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_opc - connect \Y $13 - end - process $group_2 - assign \qn_opc 1'0 - assign \qn_opc $13 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" - wire width 1 \qlq_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - wire width 1 $15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $16 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_opc - connect \B \q_int - connect \Y $15 - end - process $group_3 - assign \qlq_opc 1'0 - assign \qlq_opc $15 - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.div0.req_l" -module \req_l$83 - attribute \src "simple/issuer.py:141" - wire width 1 input 0 \coresync_clk - attribute \src "simple/issuer.py:141" - wire width 1 input 1 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire width 4 output 2 \q_req - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 4 input 3 \s_req - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 4 input 4 \r_req - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire width 4 \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire width 4 \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 4 $1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A \r_req - connect \Y $1 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 4 $3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $4 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A \q_int - connect \B $1 - connect \Y $3 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 4 $5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $6 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A $3 - connect \B \s_req - connect \Y $5 - end - process $group_0 - assign \q_int$next \q_int - assign \q_int$next $5 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \q_int$next 4'0000 - end - sync init - update \q_int 4'0000 - sync posedge \coresync_clk - update \q_int \q_int$next - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 4 $7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $8 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A \r_req - connect \Y $7 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 4 $9 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $10 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A \q_int - connect \B $7 - connect \Y $9 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 4 $11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $12 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A $9 - connect \B \s_req - connect \Y $11 - end - process $group_1 - assign \q_req 4'0000 - assign \q_req $11 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" - wire width 4 \qn_req - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - wire width 4 $13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $14 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A \q_req - connect \Y $13 - end - process $group_2 - assign \qn_req 4'0000 - assign \qn_req $13 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" - wire width 4 \qlq_req - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - wire width 4 $15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $16 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A \q_req - connect \B \q_int - connect \Y $15 - end - process $group_3 - assign \qlq_req 4'0000 - assign \qlq_req $15 - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.div0.rst_l" -module \rst_l$84 - attribute \src "simple/issuer.py:141" - wire width 1 input 0 \coresync_clk - attribute \src "simple/issuer.py:141" - wire width 1 input 1 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 1 input 2 \s_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 1 input 3 \r_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire width 1 \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire width 1 \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_rst - connect \Y $1 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 1 $3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $4 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B $1 - connect \Y $3 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 1 $5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $6 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $3 - connect \B \s_rst - connect \Y $5 - end - process $group_0 - assign \q_int$next \q_int - assign \q_int$next $5 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \q_int$next 1'0 - end - sync init - update \q_int 1'0 - sync posedge \coresync_clk - update \q_int \q_int$next - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire width 1 \q_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 1 $7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $8 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_rst - connect \Y $7 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 1 $9 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $10 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B $7 - connect \Y $9 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 1 $11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $12 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $9 - connect \B \s_rst - connect \Y $11 - end - process $group_1 - assign \q_rst 1'0 - assign \q_rst $11 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" - wire width 1 \qn_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - wire width 1 $13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $14 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_rst - connect \Y $13 - end - process $group_2 - assign \qn_rst 1'0 - assign \qn_rst $13 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" - wire width 1 \qlq_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - wire width 1 $15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $16 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_rst - connect \B \q_int - connect \Y $15 - end - process $group_3 - assign \qlq_rst 1'0 - assign \qlq_rst $15 - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.div0.rok_l" -module \rok_l$85 - attribute \src "simple/issuer.py:141" - wire width 1 input 0 \coresync_clk - attribute \src "simple/issuer.py:141" - wire width 1 input 1 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire width 1 output 2 \q_rdok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 1 input 3 \s_rdok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 1 input 4 \r_rdok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire width 1 \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire width 1 \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_rdok - connect \Y $1 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 1 $3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $4 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B $1 - connect \Y $3 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 1 $5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $6 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $3 - connect \B \s_rdok - connect \Y $5 - end - process $group_0 - assign \q_int$next \q_int - assign \q_int$next $5 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \q_int$next 1'0 - end - sync init - update \q_int 1'0 - sync posedge \coresync_clk - update \q_int \q_int$next - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 1 $7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $8 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_rdok - connect \Y $7 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 1 $9 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $10 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B $7 - connect \Y $9 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 1 $11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $12 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $9 - connect \B \s_rdok - connect \Y $11 - end - process $group_1 - assign \q_rdok 1'0 - assign \q_rdok $11 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" - wire width 1 \qn_rdok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - wire width 1 $13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $14 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_rdok - connect \Y $13 - end - process $group_2 - assign \qn_rdok 1'0 - assign \qn_rdok $13 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" - wire width 1 \qlq_rdok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - wire width 1 $15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $16 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_rdok - connect \B \q_int - connect \Y $15 - end - process $group_3 - assign \qlq_rdok 1'0 - assign \qlq_rdok $15 - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alui_l" -module \alui_l$86 - attribute \src "simple/issuer.py:141" - wire width 1 input 0 \coresync_clk - attribute \src "simple/issuer.py:141" - wire width 1 input 1 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire width 1 output 2 \q_alui - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 1 input 3 \r_alui - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 1 input 4 \s_alui - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire width 1 \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire width 1 \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_alui - connect \Y $1 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 1 $3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $4 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B $1 - connect \Y $3 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 1 $5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $6 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $3 - connect \B \s_alui - connect \Y $5 - end - process $group_0 - assign \q_int$next \q_int - assign \q_int$next $5 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \q_int$next 1'0 - end - sync init - update \q_int 1'0 - sync posedge \coresync_clk - update \q_int \q_int$next - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 1 $7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $8 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_alui - connect \Y $7 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 1 $9 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $10 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B $7 - connect \Y $9 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 1 $11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $12 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $9 - connect \B \s_alui - connect \Y $11 - end - process $group_1 - assign \q_alui 1'0 - assign \q_alui $11 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" - wire width 1 \qn_alui - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - wire width 1 $13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $14 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_alui - connect \Y $13 - end - process $group_2 - assign \qn_alui 1'0 - assign \qn_alui $13 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" - wire width 1 \qlq_alui - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - wire width 1 $15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $16 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_alui - connect \B \q_int - connect \Y $15 - end - process $group_3 - assign \qlq_alui 1'0 - assign \qlq_alui $15 - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.div0.alu_l" -module \alu_l$87 - attribute \src "simple/issuer.py:141" - wire width 1 input 0 \coresync_clk - attribute \src "simple/issuer.py:141" - wire width 1 input 1 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire width 1 output 2 \q_alu - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 1 input 3 \r_alu - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 1 input 4 \s_alu - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire width 1 \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire width 1 \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_alu - connect \Y $1 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 1 $3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $4 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B $1 - connect \Y $3 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 1 $5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $6 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $3 - connect \B \s_alu - connect \Y $5 - end - process $group_0 - assign \q_int$next \q_int - assign \q_int$next $5 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \q_int$next 1'0 - end - sync init - update \q_int 1'0 - sync posedge \coresync_clk - update \q_int \q_int$next - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 1 $7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $8 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_alu - connect \Y $7 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 1 $9 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $10 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B $7 - connect \Y $9 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 1 $11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $12 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $9 - connect \B \s_alu - connect \Y $11 - end - process $group_1 - assign \q_alu 1'0 - assign \q_alu $11 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" - wire width 1 \qn_alu - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - wire width 1 $13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $14 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_alu - connect \Y $13 - end - process $group_2 - assign \qn_alu 1'0 - assign \qn_alu $13 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" - wire width 1 \qlq_alu - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - wire width 1 $15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $16 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_alu - connect \B \q_int - connect \Y $15 - end - process $group_3 - assign \qlq_alu 1'0 - assign \qlq_alu $15 - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.div0" -module \div0 - attribute \src "simple/issuer.py:141" - wire width 1 input 0 \coresync_clk - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute 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\enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 input 2 \oper_i_alu_div0__fn_unit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 input 3 \oper_i_alu_div0__imm_data__data - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 4 \oper_i_alu_div0__imm_data__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 5 \oper_i_alu_div0__rc__rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 6 \oper_i_alu_div0__rc__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 7 \oper_i_alu_div0__oe__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 8 \oper_i_alu_div0__oe__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 9 \oper_i_alu_div0__invert_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 10 \oper_i_alu_div0__zero_a - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 input 11 \oper_i_alu_div0__input_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 12 \oper_i_alu_div0__invert_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 13 \oper_i_alu_div0__write_cr0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 14 \oper_i_alu_div0__output_carry - attribute \src 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"/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 31 \cr_a_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" - wire width 4 output 32 \dest2_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 33 \xer_ov_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" - wire width 2 output 34 \dest3_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 35 \xer_so_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" - wire width 1 output 36 \dest4_o - attribute \src "simple/issuer.py:141" - wire width 1 input 37 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" - wire width 1 \alu_div0_n_valid_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" - wire width 1 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"OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \alu_div0_logical_op__insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \alu_div0_logical_op__insn_type$next - attribute \enum_base_type "Function" - attribute \enum_value_00000000000 "NONE" - attribute \enum_value_00000000010 "ALU" - attribute \enum_value_00000000100 "LDST" - attribute \enum_value_00000001000 "SHIFT_ROT" - attribute \enum_value_00000010000 "LOGICAL" - attribute \enum_value_00000100000 "BRANCH" - attribute \enum_value_00001000000 "CR" - attribute \enum_value_00010000000 "TRAP" - attribute \enum_value_00100000000 "MUL" - attribute \enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 \alu_div0_logical_op__fn_unit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 \alu_div0_logical_op__fn_unit$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \alu_div0_logical_op__imm_data__data - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \alu_div0_logical_op__imm_data__data$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \alu_div0_logical_op__imm_data__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \alu_div0_logical_op__imm_data__ok$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \alu_div0_logical_op__rc__rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \alu_div0_logical_op__rc__rc$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \alu_div0_logical_op__rc__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \alu_div0_logical_op__rc__ok$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \alu_div0_logical_op__oe__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \alu_div0_logical_op__oe__oe$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \alu_div0_logical_op__oe__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \alu_div0_logical_op__oe__ok$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \alu_div0_logical_op__invert_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 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"/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \alu_div0_logical_op__write_cr0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \alu_div0_logical_op__write_cr0$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \alu_div0_logical_op__output_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \alu_div0_logical_op__output_carry$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \alu_div0_logical_op__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \alu_div0_logical_op__is_32bit$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \alu_div0_logical_op__is_signed - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \alu_div0_logical_op__is_signed$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \alu_div0_logical_op__data_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \alu_div0_logical_op__data_len$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \alu_div0_logical_op__insn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \alu_div0_logical_op__insn$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 \alu_div0_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 4 \alu_div0_cr_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 2 \alu_div0_xer_ov - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \alu_div0_xer_so - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \alu_div0_ra - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \alu_div0_rb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 1 \alu_div0_xer_so$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" - wire width 1 \alu_div0_p_valid_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" - wire width 1 \alu_div0_p_ready_o - cell \alu_div0 \alu_div0 - connect \coresync_clk \coresync_clk - connect \o_ok \o_ok - connect \cr_a_ok \cr_a_ok - connect \xer_ov_ok \xer_ov_ok - connect \xer_so_ok \xer_so_ok - connect \coresync_rst \coresync_rst - connect \n_valid_o \alu_div0_n_valid_o - connect \n_ready_i \alu_div0_n_ready_i - connect \logical_op__insn_type \alu_div0_logical_op__insn_type - connect \logical_op__fn_unit \alu_div0_logical_op__fn_unit - connect \logical_op__imm_data__data \alu_div0_logical_op__imm_data__data - connect \logical_op__imm_data__ok \alu_div0_logical_op__imm_data__ok - connect \logical_op__rc__rc \alu_div0_logical_op__rc__rc - connect \logical_op__rc__ok \alu_div0_logical_op__rc__ok - connect \logical_op__oe__oe \alu_div0_logical_op__oe__oe - connect \logical_op__oe__ok \alu_div0_logical_op__oe__ok - connect \logical_op__invert_in \alu_div0_logical_op__invert_in - connect \logical_op__zero_a \alu_div0_logical_op__zero_a - connect \logical_op__input_carry \alu_div0_logical_op__input_carry - connect \logical_op__invert_out \alu_div0_logical_op__invert_out - connect \logical_op__write_cr0 \alu_div0_logical_op__write_cr0 - connect \logical_op__output_carry \alu_div0_logical_op__output_carry - connect \logical_op__is_32bit \alu_div0_logical_op__is_32bit - connect \logical_op__is_signed \alu_div0_logical_op__is_signed - connect \logical_op__data_len \alu_div0_logical_op__data_len - connect \logical_op__insn \alu_div0_logical_op__insn - connect \o \alu_div0_o - connect \cr_a \alu_div0_cr_a - connect \xer_ov \alu_div0_xer_ov - connect \xer_so \alu_div0_xer_so - connect \ra \alu_div0_ra - connect \rb \alu_div0_rb - connect \xer_so$1 \alu_div0_xer_so$1 - connect \p_valid_i \alu_div0_p_valid_i - connect \p_ready_o \alu_div0_p_ready_o - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 3 \src_l_s_src - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 3 \src_l_s_src$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 3 \src_l_r_src - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 3 \src_l_r_src$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire width 3 \src_l_q_src - cell \src_l$81 \src_l - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \s_src \src_l_s_src - connect \r_src \src_l_r_src - connect \q_src \src_l_q_src - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 1 \opc_l_s_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 1 \opc_l_s_opc$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 1 \opc_l_r_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 1 \opc_l_r_opc$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire width 1 \opc_l_q_opc - cell \opc_l$82 \opc_l - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \s_opc \opc_l_s_opc - connect \r_opc \opc_l_r_opc - connect \q_opc \opc_l_q_opc - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire width 4 \req_l_q_req - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 4 \req_l_s_req - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 4 \req_l_s_req$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 4 \req_l_r_req - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 4 \req_l_r_req$next - cell \req_l$83 \req_l - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \q_req \req_l_q_req - connect \s_req \req_l_s_req - connect \r_req \req_l_r_req - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 1 \rst_l_s_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 1 \rst_l_s_rst$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 1 \rst_l_r_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 1 \rst_l_r_rst$next - cell \rst_l$84 \rst_l - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \s_rst \rst_l_s_rst - connect \r_rst \rst_l_r_rst - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire width 1 \rok_l_q_rdok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 1 \rok_l_s_rdok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 1 \rok_l_s_rdok$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 1 \rok_l_r_rdok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 1 \rok_l_r_rdok$next - cell \rok_l$85 \rok_l - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \q_rdok \rok_l_q_rdok - connect \s_rdok \rok_l_s_rdok - connect \r_rdok \rok_l_r_rdok - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire width 1 \alui_l_q_alui - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 1 \alui_l_r_alui - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 1 \alui_l_r_alui$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 1 \alui_l_s_alui - cell \alui_l$86 \alui_l - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \q_alui \alui_l_q_alui - connect \r_alui \alui_l_r_alui - connect \s_alui \alui_l_s_alui - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire width 1 \alu_l_q_alu - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 1 \alu_l_r_alu - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 1 \alu_l_r_alu$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 1 \alu_l_s_alu - cell \alu_l$87 \alu_l - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \q_alu \alu_l_q_alu - connect \r_alu \alu_l_r_alu - connect \s_alu \alu_l_s_alu - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:187" - wire width 1 \all_rd - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:188" - wire width 1 $2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:188" - cell $and $3 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cu_busy_o - connect \B \rok_l_q_rdok - connect \Y $2 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - wire width 1 $4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - wire width 3 $5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - cell $not $6 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A \cu_rd__rel_o - connect \Y $5 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - wire width 3 $7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - cell $or $8 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A $5 - connect \B \cu_rd__go_i - connect \Y $7 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - cell $reduce_and $9 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A $7 - connect \Y $4 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - wire width 1 $10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - cell $and $11 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $2 - connect \B $4 - connect \Y $10 - end - process $group_0 - assign \all_rd 1'0 - assign \all_rd $10 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire width 1 \all_rd_dly - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire width 1 \all_rd_dly$next - process $group_1 - assign \all_rd_dly$next \all_rd_dly - assign \all_rd_dly$next \all_rd - sync init - update \all_rd_dly 1'0 - sync posedge \coresync_clk - update \all_rd_dly \all_rd_dly$next - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" - wire width 1 \all_rd_rise - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - wire width 1 $12 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $not $13 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \all_rd_dly - connect \Y $12 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - wire width 1 $14 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $and $15 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \all_rd - connect \B $12 - connect \Y $14 - end - process $group_2 - assign \all_rd_rise 1'0 - assign \all_rd_rise $14 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:192" - wire width 1 \all_rd_pulse - process $group_3 - assign \all_rd_pulse 1'0 - assign \all_rd_pulse \all_rd_rise - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:196" - wire width 1 \alu_done - process $group_4 - assign \alu_done 1'0 - assign \alu_done \alu_div0_n_valid_o - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire width 1 \alu_done_dly - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire width 1 \alu_done_dly$next - process $group_5 - assign \alu_done_dly$next \alu_done_dly - assign \alu_done_dly$next \alu_done - sync init - update \alu_done_dly 1'0 - sync posedge \coresync_clk - update \alu_done_dly \alu_done_dly$next - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" - wire width 1 \alu_done_rise - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - wire width 1 $16 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $not $17 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \alu_done_dly - connect \Y $16 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - wire width 1 $18 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $and $19 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \alu_done - connect \B $16 - connect \Y $18 - end - process $group_6 - assign \alu_done_rise 1'0 - assign \alu_done_rise $18 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:197" - wire width 1 \alu_pulse - process $group_7 - assign \alu_pulse 1'0 - assign \alu_pulse \alu_done_rise - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:198" - wire width 4 \alu_pulsem - process $group_8 - assign \alu_pulsem 4'0000 - assign \alu_pulsem { \alu_pulse \alu_pulse \alu_pulse \alu_pulse } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:204" - wire width 4 \prev_wr_go - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:204" - wire width 4 \prev_wr_go$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:206" - wire width 4 $20 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:206" - cell $and $21 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A \cu_wr__go_i - connect \B { \cu_busy_o \cu_busy_o \cu_busy_o \cu_busy_o } - connect \Y $20 - end - process $group_9 - assign \prev_wr_go$next \prev_wr_go - assign \prev_wr_go$next $20 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \prev_wr_go$next 4'0000 - end - sync init - update \prev_wr_go 4'0000 - sync posedge \coresync_clk - update \prev_wr_go \prev_wr_go$next - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:108" - wire width 1 \cu_done_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - wire width 1 $22 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - wire width 1 $23 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - wire width 4 $24 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:97" - wire width 4 \cu_wrmask_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $not $25 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A \cu_wrmask_o - connect \Y $24 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - wire width 4 $26 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $and $27 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A \cu_wr__rel_o - connect \B $24 - connect \Y $26 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $reduce_bool $28 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A $26 - connect \Y $23 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $not $29 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $23 - connect \Y $22 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - wire width 1 $30 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $and $31 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cu_busy_o - connect \B $22 - connect \Y $30 - end - process $group_10 - assign \cu_done_o 1'0 - assign \cu_done_o $30 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:211" - wire width 1 \wr_any - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" - wire width 1 $32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" - cell $reduce_bool $33 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \cu_wr__go_i - connect \Y $32 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" - wire width 1 $34 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" - cell $reduce_bool $35 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \prev_wr_go - connect \Y $34 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" - wire width 1 $36 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" - cell $or $37 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $32 - connect \B $34 - connect \Y $36 - end - process $group_11 - assign \wr_any 1'0 - assign \wr_any $36 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:212" - wire width 1 \req_done - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" - wire width 1 $38 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" - cell $not $39 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \alu_div0_n_ready_i - connect \Y $38 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" - wire width 1 $40 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" - cell $and $41 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_any - connect \B $38 - connect \Y $40 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" - wire width 4 $42 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" - cell $and $43 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A \req_l_q_req - connect \B \cu_wrmask_o - connect \Y $42 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" - wire width 1 $44 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" - cell $eq $45 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $42 - connect \B 1'0 - connect \Y $44 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" - wire width 1 $46 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" - cell $and $47 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $40 - connect \B $44 - connect \Y $46 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - wire width 1 $48 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - cell $eq $49 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cu_wrmask_o - connect \B 1'0 - connect \Y $48 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - wire width 1 $50 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - cell $and $51 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $48 - connect \B \alu_div0_n_ready_i - connect \Y $50 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - wire width 1 $52 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - cell $and $53 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $50 - connect \B \alu_div0_n_valid_o - connect \Y $52 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - wire width 1 $54 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - cell $and $55 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $52 - connect \B \cu_busy_o - connect \Y $54 - end - process $group_12 - assign \req_done 1'0 - assign \req_done $46 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - switch { $54 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - case 1'1 - assign \req_done 1'1 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:226" - wire width 1 \reset - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:104" - wire width 1 \cu_go_die_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:230" - wire width 1 $56 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:230" - cell $or $57 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \req_done - connect \B \cu_go_die_i - connect \Y $56 - end - process $group_13 - assign \reset 1'0 - assign \reset $56 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:227" - wire width 1 \rst_r - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:231" - wire width 1 $58 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:231" - cell $or $59 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cu_issue_i - connect \B \cu_go_die_i - connect \Y $58 - end - process $group_14 - assign \rst_r 1'0 - assign \rst_r $58 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:228" - wire width 4 \reset_w - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:232" - wire width 4 $60 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:232" - cell $or $61 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A \cu_wr__go_i - connect \B { \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i } - connect \Y $60 - end - process $group_15 - assign \reset_w 4'0000 - assign \reset_w $60 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:229" - wire width 3 \reset_r - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:233" - wire width 3 $62 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:233" - cell $or $63 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A \cu_rd__go_i - connect \B { \cu_go_die_i \cu_go_die_i \cu_go_die_i } - connect \Y $62 - end - process $group_16 - assign \reset_r 3'000 - assign \reset_r $62 - sync init - end - process $group_17 - assign \rok_l_s_rdok$next \rok_l_s_rdok - assign \rok_l_s_rdok$next \cu_issue_i - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \rok_l_s_rdok$next 1'0 - end - sync init - update \rok_l_s_rdok 1'0 - sync posedge \coresync_clk - update \rok_l_s_rdok \rok_l_s_rdok$next - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:237" - wire width 1 $64 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:237" - cell $and $65 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \alu_div0_n_valid_o - connect \B \cu_busy_o - connect \Y $64 - end - process $group_18 - assign \rok_l_r_rdok$next \rok_l_r_rdok - assign \rok_l_r_rdok$next $64 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \rok_l_r_rdok$next 1'1 - end - sync init - update \rok_l_r_rdok 1'1 - sync posedge \coresync_clk - update \rok_l_r_rdok \rok_l_r_rdok$next - end - process $group_19 - assign \rst_l_s_rst$next \rst_l_s_rst - assign \rst_l_s_rst$next \all_rd - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \rst_l_s_rst$next 1'0 - end - sync init - update \rst_l_s_rst 1'0 - sync posedge \coresync_clk - update \rst_l_s_rst \rst_l_s_rst$next - end - process $group_20 - assign \rst_l_r_rst$next \rst_l_r_rst - assign \rst_l_r_rst$next \rst_r - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \rst_l_r_rst$next 1'1 - end - sync init - update \rst_l_r_rst 1'1 - sync posedge \coresync_clk - update \rst_l_r_rst \rst_l_r_rst$next - end - process $group_21 - assign \opc_l_s_opc$next \opc_l_s_opc - assign \opc_l_s_opc$next \cu_issue_i - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \opc_l_s_opc$next 1'0 - end - sync init - update \opc_l_s_opc 1'0 - sync posedge \coresync_clk - update \opc_l_s_opc \opc_l_s_opc$next - end - process $group_22 - assign \opc_l_r_opc$next \opc_l_r_opc - assign \opc_l_r_opc$next \req_done - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \opc_l_r_opc$next 1'1 - end - sync init - update \opc_l_r_opc 1'1 - sync posedge \coresync_clk - update \opc_l_r_opc \opc_l_r_opc$next - end - process $group_23 - assign \src_l_s_src$next \src_l_s_src - assign \src_l_s_src$next { \cu_issue_i \cu_issue_i \cu_issue_i } - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \src_l_s_src$next 3'000 - end - sync init - update \src_l_s_src 3'000 - sync posedge \coresync_clk - update \src_l_s_src \src_l_s_src$next - end - process $group_24 - assign \src_l_r_src$next \src_l_r_src - assign \src_l_r_src$next \reset_r - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \src_l_r_src$next 3'111 - end - sync init - update \src_l_r_src 3'111 - sync posedge \coresync_clk - update \src_l_r_src \src_l_r_src$next - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:252" - wire width 4 $66 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:252" - cell $and $67 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A \alu_pulsem - connect \B \cu_wrmask_o - connect \Y $66 - end - process $group_25 - assign \req_l_s_req$next \req_l_s_req - assign \req_l_s_req$next $66 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \req_l_s_req$next 4'0000 - end - sync init - update \req_l_s_req 4'0000 - sync posedge \coresync_clk - update \req_l_s_req \req_l_s_req$next - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:253" - wire width 4 $68 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:253" - cell $or $69 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A \reset_w - connect \B \prev_wr_go - connect \Y $68 - end - process $group_26 - assign \req_l_r_req$next \req_l_r_req - assign \req_l_r_req$next $68 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \req_l_r_req$next 4'1111 - end - sync init - update \req_l_r_req 4'1111 - sync posedge \coresync_clk - update \req_l_r_req \req_l_r_req$next - end - process $group_27 - assign \alu_div0_logical_op__insn_type$next \alu_div0_logical_op__insn_type - assign \alu_div0_logical_op__fn_unit$next \alu_div0_logical_op__fn_unit - assign \alu_div0_logical_op__imm_data__data$next \alu_div0_logical_op__imm_data__data - assign \alu_div0_logical_op__imm_data__ok$next \alu_div0_logical_op__imm_data__ok - assign \alu_div0_logical_op__rc__rc$next \alu_div0_logical_op__rc__rc - assign \alu_div0_logical_op__rc__ok$next \alu_div0_logical_op__rc__ok - assign \alu_div0_logical_op__oe__oe$next \alu_div0_logical_op__oe__oe - assign \alu_div0_logical_op__oe__ok$next \alu_div0_logical_op__oe__ok - assign \alu_div0_logical_op__invert_in$next \alu_div0_logical_op__invert_in - assign \alu_div0_logical_op__zero_a$next \alu_div0_logical_op__zero_a - assign \alu_div0_logical_op__input_carry$next \alu_div0_logical_op__input_carry - assign \alu_div0_logical_op__invert_out$next \alu_div0_logical_op__invert_out - assign \alu_div0_logical_op__write_cr0$next \alu_div0_logical_op__write_cr0 - assign \alu_div0_logical_op__output_carry$next \alu_div0_logical_op__output_carry - assign \alu_div0_logical_op__is_32bit$next \alu_div0_logical_op__is_32bit - assign \alu_div0_logical_op__is_signed$next \alu_div0_logical_op__is_signed - assign \alu_div0_logical_op__data_len$next \alu_div0_logical_op__data_len - assign \alu_div0_logical_op__insn$next \alu_div0_logical_op__insn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:257" - switch { \cu_issue_i } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:257" - case 1'1 - assign { \alu_div0_logical_op__insn$next \alu_div0_logical_op__data_len$next \alu_div0_logical_op__is_signed$next \alu_div0_logical_op__is_32bit$next \alu_div0_logical_op__output_carry$next \alu_div0_logical_op__write_cr0$next \alu_div0_logical_op__invert_out$next \alu_div0_logical_op__input_carry$next \alu_div0_logical_op__zero_a$next \alu_div0_logical_op__invert_in$next { \alu_div0_logical_op__oe__ok$next \alu_div0_logical_op__oe__oe$next } { \alu_div0_logical_op__rc__ok$next \alu_div0_logical_op__rc__rc$next } { \alu_div0_logical_op__imm_data__ok$next \alu_div0_logical_op__imm_data__data$next } \alu_div0_logical_op__fn_unit$next \alu_div0_logical_op__insn_type$next } { \oper_i_alu_div0__insn \oper_i_alu_div0__data_len \oper_i_alu_div0__is_signed \oper_i_alu_div0__is_32bit \oper_i_alu_div0__output_carry \oper_i_alu_div0__write_cr0 \oper_i_alu_div0__invert_out \oper_i_alu_div0__input_carry \oper_i_alu_div0__zero_a \oper_i_alu_div0__invert_in { \oper_i_alu_div0__oe__ok \oper_i_alu_div0__oe__oe } { \oper_i_alu_div0__rc__ok \oper_i_alu_div0__rc__rc } { \oper_i_alu_div0__imm_data__ok \oper_i_alu_div0__imm_data__data } \oper_i_alu_div0__fn_unit \oper_i_alu_div0__insn_type } - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \alu_div0_logical_op__imm_data__data$next 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \alu_div0_logical_op__imm_data__ok$next 1'0 - assign \alu_div0_logical_op__rc__rc$next 1'0 - assign \alu_div0_logical_op__rc__ok$next 1'0 - assign \alu_div0_logical_op__oe__oe$next 1'0 - assign \alu_div0_logical_op__oe__ok$next 1'0 - end - sync init - update \alu_div0_logical_op__insn_type 7'0000000 - update \alu_div0_logical_op__fn_unit 11'00000000000 - update \alu_div0_logical_op__imm_data__data 64'0000000000000000000000000000000000000000000000000000000000000000 - update \alu_div0_logical_op__imm_data__ok 1'0 - update \alu_div0_logical_op__rc__rc 1'0 - update \alu_div0_logical_op__rc__ok 1'0 - update \alu_div0_logical_op__oe__oe 1'0 - update \alu_div0_logical_op__oe__ok 1'0 - update \alu_div0_logical_op__invert_in 1'0 - update \alu_div0_logical_op__zero_a 1'0 - update \alu_div0_logical_op__input_carry 2'00 - update \alu_div0_logical_op__invert_out 1'0 - update \alu_div0_logical_op__write_cr0 1'0 - update \alu_div0_logical_op__output_carry 1'0 - update \alu_div0_logical_op__is_32bit 1'0 - update \alu_div0_logical_op__is_signed 1'0 - update \alu_div0_logical_op__data_len 4'0000 - update \alu_div0_logical_op__insn 32'00000000000000000000000000000000 - sync posedge \coresync_clk - update \alu_div0_logical_op__insn_type \alu_div0_logical_op__insn_type$next - update \alu_div0_logical_op__fn_unit \alu_div0_logical_op__fn_unit$next - update \alu_div0_logical_op__imm_data__data \alu_div0_logical_op__imm_data__data$next - update \alu_div0_logical_op__imm_data__ok \alu_div0_logical_op__imm_data__ok$next - update \alu_div0_logical_op__rc__rc \alu_div0_logical_op__rc__rc$next - update \alu_div0_logical_op__rc__ok \alu_div0_logical_op__rc__ok$next - update \alu_div0_logical_op__oe__oe \alu_div0_logical_op__oe__oe$next - update \alu_div0_logical_op__oe__ok \alu_div0_logical_op__oe__ok$next - update \alu_div0_logical_op__invert_in \alu_div0_logical_op__invert_in$next - update \alu_div0_logical_op__zero_a \alu_div0_logical_op__zero_a$next - update \alu_div0_logical_op__input_carry \alu_div0_logical_op__input_carry$next - update \alu_div0_logical_op__invert_out \alu_div0_logical_op__invert_out$next - update \alu_div0_logical_op__write_cr0 \alu_div0_logical_op__write_cr0$next - update \alu_div0_logical_op__output_carry \alu_div0_logical_op__output_carry$next - update \alu_div0_logical_op__is_32bit \alu_div0_logical_op__is_32bit$next - update \alu_div0_logical_op__is_signed \alu_div0_logical_op__is_signed$next - update \alu_div0_logical_op__data_len \alu_div0_logical_op__data_len$next - update \alu_div0_logical_op__insn \alu_div0_logical_op__insn$next - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" - wire width 64 \data_r0__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" - wire width 64 \data_r0__o$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" - wire width 1 \data_r0__o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" - wire width 1 \data_r0__o_ok$next - process $group_45 - assign \data_r0__o$next \data_r0__o - assign \data_r0__o_ok$next \data_r0__o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" - switch { \alu_pulse } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" - case 1'1 - assign { \data_r0__o_ok$next \data_r0__o$next } { \o_ok \alu_div0_o } - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" - switch { \cu_issue_i } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" - case 1'1 - assign { \data_r0__o_ok$next \data_r0__o$next } 65'00000000000000000000000000000000000000000000000000000000000000000 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \data_r0__o_ok$next 1'0 - end - sync init - update \data_r0__o 64'0000000000000000000000000000000000000000000000000000000000000000 - update \data_r0__o_ok 1'0 - sync posedge \coresync_clk - update \data_r0__o \data_r0__o$next - update \data_r0__o_ok \data_r0__o_ok$next - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" - wire width 4 \data_r1__cr_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" - wire width 4 \data_r1__cr_a$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" - wire width 1 \data_r1__cr_a_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" - wire width 1 \data_r1__cr_a_ok$next - process $group_47 - assign \data_r1__cr_a$next \data_r1__cr_a - assign \data_r1__cr_a_ok$next \data_r1__cr_a_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" - switch { \alu_pulse } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" - case 1'1 - assign { \data_r1__cr_a_ok$next \data_r1__cr_a$next } { \cr_a_ok \alu_div0_cr_a } - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" - switch { \cu_issue_i } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" - case 1'1 - assign { \data_r1__cr_a_ok$next \data_r1__cr_a$next } 5'00000 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \data_r1__cr_a_ok$next 1'0 - end - sync init - update \data_r1__cr_a 4'0000 - update \data_r1__cr_a_ok 1'0 - sync posedge \coresync_clk - update \data_r1__cr_a \data_r1__cr_a$next - update \data_r1__cr_a_ok \data_r1__cr_a_ok$next - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" - wire width 2 \data_r2__xer_ov - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" - wire width 2 \data_r2__xer_ov$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" - wire width 1 \data_r2__xer_ov_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" - wire width 1 \data_r2__xer_ov_ok$next - process $group_49 - assign \data_r2__xer_ov$next \data_r2__xer_ov - assign \data_r2__xer_ov_ok$next \data_r2__xer_ov_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" - switch { \alu_pulse } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" - case 1'1 - assign { \data_r2__xer_ov_ok$next \data_r2__xer_ov$next } { \xer_ov_ok \alu_div0_xer_ov } - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" - switch { \cu_issue_i } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" - case 1'1 - assign { \data_r2__xer_ov_ok$next \data_r2__xer_ov$next } 3'000 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \data_r2__xer_ov_ok$next 1'0 - end - sync init - update \data_r2__xer_ov 2'00 - update \data_r2__xer_ov_ok 1'0 - sync posedge \coresync_clk - update \data_r2__xer_ov \data_r2__xer_ov$next - update \data_r2__xer_ov_ok \data_r2__xer_ov_ok$next - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" - wire width 1 \data_r3__xer_so - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" - wire width 1 \data_r3__xer_so$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" - wire width 1 \data_r3__xer_so_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" - wire width 1 \data_r3__xer_so_ok$next - process $group_51 - assign \data_r3__xer_so$next \data_r3__xer_so - assign \data_r3__xer_so_ok$next \data_r3__xer_so_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" - switch { \alu_pulse } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" - case 1'1 - assign { \data_r3__xer_so_ok$next \data_r3__xer_so$next } { \xer_so_ok \alu_div0_xer_so } - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" - switch { \cu_issue_i } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" - case 1'1 - assign { \data_r3__xer_so_ok$next \data_r3__xer_so$next } 2'00 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \data_r3__xer_so_ok$next 1'0 - end - sync init - update \data_r3__xer_so 1'0 - update \data_r3__xer_so_ok 1'0 - sync posedge \coresync_clk - update \data_r3__xer_so \data_r3__xer_so$next - update \data_r3__xer_so_ok \data_r3__xer_so_ok$next - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" - wire width 1 $70 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" - cell $and $71 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \o_ok - connect \B \cu_busy_o - connect \Y $70 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" - wire width 1 $72 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" - cell $and $73 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cr_a_ok - connect \B \cu_busy_o - connect \Y $72 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" - wire width 1 $74 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" - cell $and $75 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \xer_ov_ok - connect \B \cu_busy_o - connect \Y $74 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" - wire width 1 $76 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" - cell $and $77 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \xer_so_ok - connect \B \cu_busy_o - connect \Y $76 - end - process $group_53 - assign \cu_wrmask_o 4'0000 - assign \cu_wrmask_o { $76 $74 $72 $70 } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:167" - wire width 1 \src_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:168" - wire width 1 $78 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:168" - cell $mux $79 - parameter \WIDTH 1 - connect \A \src_l_q_src [0] - connect \B \opc_l_q_opc - connect \S \alu_div0_logical_op__zero_a - connect \Y $78 - end - process $group_54 - assign \src_sel 1'0 - assign \src_sel $78 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:166" - wire width 64 \src_or_imm - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:169" - wire width 64 $80 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:169" - cell $mux $81 - parameter \WIDTH 64 - connect \A \src1_i - connect \B 64'0000000000000000000000000000000000000000000000000000000000000000 - connect \S \alu_div0_logical_op__zero_a - connect \Y $80 - end - process $group_55 - assign \src_or_imm 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \src_or_imm $80 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:167" - wire width 1 \src_sel$82 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:168" - wire width 1 $83 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:168" - cell $mux $84 - parameter \WIDTH 1 - connect \A \src_l_q_src [1] - connect \B \opc_l_q_opc - connect \S \alu_div0_logical_op__imm_data__ok - connect \Y $83 - end - process $group_56 - assign \src_sel$82 1'0 - assign \src_sel$82 $83 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:166" - wire width 64 \src_or_imm$85 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:169" - wire width 64 $86 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:169" - cell $mux $87 - parameter \WIDTH 64 - connect \A \src2_i - connect \B \alu_div0_logical_op__imm_data__data - connect \S \alu_div0_logical_op__imm_data__ok - connect \Y $86 - end - process $group_57 - assign \src_or_imm$85 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \src_or_imm$85 $86 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" - wire width 64 \src_r0 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" - wire width 64 \src_r0$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - wire width 64 $88 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - cell $mux $89 - parameter \WIDTH 64 - connect \A \src_r0 - connect \B \src_or_imm - connect \S \src_sel - connect \Y $88 - end - process $group_58 - assign \alu_div0_ra 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \alu_div0_ra $88 - sync init - end - process $group_59 - assign \src_r0$next \src_r0 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" - switch { \src_sel } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" - case 1'1 - assign \src_r0$next \src_or_imm - end - sync init - update \src_r0 64'0000000000000000000000000000000000000000000000000000000000000000 - sync posedge \coresync_clk - update \src_r0 \src_r0$next - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" - wire width 64 \src_r1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" - wire width 64 \src_r1$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - wire width 64 $90 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - cell $mux $91 - parameter \WIDTH 64 - connect \A \src_r1 - connect \B \src_or_imm$85 - connect \S \src_sel$82 - connect \Y $90 - end - process $group_60 - assign \alu_div0_rb 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \alu_div0_rb $90 - sync init - end - process $group_61 - assign \src_r1$next \src_r1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" - switch { \src_sel$82 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" - case 1'1 - assign \src_r1$next \src_or_imm$85 - end - sync init - update \src_r1 64'0000000000000000000000000000000000000000000000000000000000000000 - sync posedge \coresync_clk - update \src_r1 \src_r1$next - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" - wire width 1 \src_r2 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" - wire width 1 \src_r2$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - wire width 1 $92 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - cell $mux $93 - parameter \WIDTH 1 - connect \A \src_r2 - connect \B \src3_i - connect \S \src_l_q_src [2] - connect \Y $92 - end - process $group_62 - assign \alu_div0_xer_so$1 1'0 - assign \alu_div0_xer_so$1 $92 - sync init - end - process $group_63 - assign \src_r2$next \src_r2 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" - switch { \src_l_q_src [2] } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" - case 1'1 - assign \src_r2$next \src3_i - end - sync init - update \src_r2 1'0 - sync posedge \coresync_clk - update \src_r2 \src_r2$next - end - process $group_64 - assign \alu_div0_p_valid_i 1'0 - assign \alu_div0_p_valid_i \alui_l_q_alui - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:327" - wire width 1 $94 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:327" - cell $and $95 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \alu_div0_p_ready_o - connect \B \alui_l_q_alui - connect \Y $94 - end - process $group_65 - assign \alui_l_r_alui$next \alui_l_r_alui - assign \alui_l_r_alui$next $94 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \alui_l_r_alui$next 1'1 - end - sync init - update \alui_l_r_alui 1'1 - sync posedge \coresync_clk - update \alui_l_r_alui \alui_l_r_alui$next - end - process $group_66 - assign \alui_l_s_alui 1'0 - assign \alui_l_s_alui \all_rd_pulse - sync init - end - process $group_67 - assign \alu_div0_n_ready_i 1'0 - assign \alu_div0_n_ready_i \alu_l_q_alu - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:334" - wire width 1 $96 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:334" - cell $and $97 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \alu_div0_n_valid_o - connect \B \alu_l_q_alu - connect \Y $96 - end - process $group_68 - assign \alu_l_r_alu$next \alu_l_r_alu - assign \alu_l_r_alu$next $96 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \alu_l_r_alu$next 1'1 - end - sync init - update \alu_l_r_alu 1'1 - sync posedge \coresync_clk - update \alu_l_r_alu \alu_l_r_alu$next - end - process $group_69 - assign \alu_l_s_alu 1'0 - assign \alu_l_s_alu \all_rd_pulse - sync init - end - process $group_70 - assign \cu_busy_o 1'0 - assign \cu_busy_o \opc_l_q_opc - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - wire width 3 $98 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - cell $and $99 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A \src_l_q_src - connect \B { \cu_busy_o \cu_busy_o \cu_busy_o } - connect \Y $98 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:173" - wire width 1 $100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:173" - cell $not $101 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \alu_div0_logical_op__zero_a - connect \Y $100 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:173" - wire width 1 $102 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:173" - cell $not $103 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \alu_div0_logical_op__imm_data__ok - connect \Y $102 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - wire width 3 $104 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - cell $and $105 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A $98 - connect \B { 1'1 $102 $100 } - connect \Y $104 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - wire width 3 $106 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - cell $not $107 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A \cu_rdmaskn_i - connect \Y $106 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - wire width 3 $108 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - cell $and $109 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A $104 - connect \B $106 - connect \Y $108 - end - process $group_71 - assign \cu_rd__rel_o 3'000 - assign \cu_rd__rel_o $108 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:102" - wire width 1 \cu_shadown_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" - wire width 1 $110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" - cell $and $111 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cu_busy_o - connect \B \cu_shadown_i - connect \Y $110 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" - wire width 1 $112 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" - cell $and $113 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cu_busy_o - connect \B \cu_shadown_i - connect \Y $112 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" - wire width 1 $114 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" - cell $and $115 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cu_busy_o - connect \B \cu_shadown_i - connect \Y $114 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" - wire width 1 $116 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" - cell $and $117 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cu_busy_o - connect \B \cu_shadown_i - connect \Y $116 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351" - wire width 4 $118 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351" - cell $and $119 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A \req_l_q_req - connect \B { $110 $112 $114 $116 } - connect \Y $118 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351" - wire width 4 $120 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351" - cell $and $121 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A $118 - connect \B \cu_wrmask_o - connect \Y $120 - end - process $group_72 - assign \cu_wr__rel_o 4'0000 - assign \cu_wr__rel_o $120 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - wire width 1 $122 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - cell $and $123 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cu_wr__go_i [0] - connect \B \cu_busy_o - connect \Y $122 - end - process $group_73 - assign \dest1_o 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - switch { $122 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - case 1'1 - assign \dest1_o { \data_r0__o_ok \data_r0__o } [63:0] - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - wire width 1 $124 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - cell $and $125 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cu_wr__go_i [1] - connect \B \cu_busy_o - connect \Y $124 - end - process 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width 32 output 28 \mul_op__insn$13 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 output 29 \ra$14 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 output 30 \rb$15 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 1 output 31 \xer_so$16 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:11" - wire width 1 output 32 \neg_res - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:12" - wire width 1 output 33 \neg_res32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:30" - wire width 1 \is_32bit - process $group_0 - assign \is_32bit 1'0 - assign \is_32bit \mul_op__is_32bit - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:31" - wire width 1 \sign_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:38" - wire width 1 $17 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:38" - cell $mux $18 - parameter \WIDTH 1 - connect \A \ra [63] - connect \B \ra [31] - connect \S \mul_op__is_32bit - connect \Y $17 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:38" - wire width 1 $19 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:38" - cell $and $20 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $17 - connect \B \mul_op__is_signed - connect \Y $19 - end - process $group_1 - assign \sign_a 1'0 - assign \sign_a $19 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:32" - wire width 1 \sign_b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:39" - wire width 1 $21 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:39" - cell $mux $22 - parameter \WIDTH 1 - connect \A \rb [63] - connect \B \rb [31] - connect \S \mul_op__is_32bit - connect \Y $21 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:39" - wire width 1 $23 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:39" - cell $and $24 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $21 - connect \B \mul_op__is_signed - connect \Y $23 - end - process $group_2 - assign \sign_b 1'0 - assign \sign_b $23 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:33" - wire width 1 \sign32_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:40" - wire width 1 $25 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:40" - cell $and $26 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \ra [31] - connect \B \mul_op__is_signed - connect \Y $25 - end - process $group_3 - assign \sign32_a 1'0 - assign \sign32_a $25 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:34" - wire width 1 \sign32_b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:41" - wire width 1 $27 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:41" - cell $and $28 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \rb [31] - connect \B \mul_op__is_signed - connect \Y $27 - end - process $group_4 - assign \sign32_b 1'0 - assign \sign32_b $27 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:44" - wire width 1 $29 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:44" - cell $xor $30 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \sign_a - connect \B \sign_b - connect \Y $29 - end - process $group_5 - assign \neg_res 1'0 - assign \neg_res $29 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:45" - wire width 1 $31 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:45" - cell $xor $32 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \sign32_a - connect \B \sign32_b - connect \Y $31 - end - process $group_6 - assign \neg_res32 1'0 - assign \neg_res32 $31 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:50" - wire width 64 \abs_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:52" - wire width 65 $33 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:52" - wire width 65 $34 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pre_stage.py:52" - cell $neg $35 - parameter \A_SIGNED 0 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"/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \mul1_mul_op__oe__ok$41 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \mul1_mul_op__write_cr0$42 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \mul1_mul_op__is_32bit$43 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \mul1_mul_op__is_signed$44 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \mul1_mul_op__insn$45 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \mul1_ra$46 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \mul1_rb$47 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 1 \mul1_xer_so$48 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:11" - wire width 1 \mul1_neg_res - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:12" - wire width 1 \mul1_neg_res32 - cell \mul1 \mul1 - connect \muxid \mul1_muxid - connect \mul_op__insn_type \mul1_mul_op__insn_type - connect \mul_op__fn_unit \mul1_mul_op__fn_unit - connect \mul_op__imm_data__data \mul1_mul_op__imm_data__data - connect \mul_op__imm_data__ok \mul1_mul_op__imm_data__ok - connect \mul_op__rc__rc \mul1_mul_op__rc__rc - connect \mul_op__rc__ok \mul1_mul_op__rc__ok - connect \mul_op__oe__oe \mul1_mul_op__oe__oe - connect \mul_op__oe__ok \mul1_mul_op__oe__ok - connect \mul_op__write_cr0 \mul1_mul_op__write_cr0 - connect \mul_op__is_32bit \mul1_mul_op__is_32bit - connect \mul_op__is_signed \mul1_mul_op__is_signed - connect \mul_op__insn \mul1_mul_op__insn - connect \ra \mul1_ra - connect \rb \mul1_rb - connect \xer_so \mul1_xer_so - connect \muxid$1 \mul1_muxid$33 - connect \mul_op__insn_type$2 \mul1_mul_op__insn_type$34 - connect \mul_op__fn_unit$3 \mul1_mul_op__fn_unit$35 - connect \mul_op__imm_data__data$4 \mul1_mul_op__imm_data__data$36 - connect \mul_op__imm_data__ok$5 \mul1_mul_op__imm_data__ok$37 - connect \mul_op__rc__rc$6 \mul1_mul_op__rc__rc$38 - connect \mul_op__rc__ok$7 \mul1_mul_op__rc__ok$39 - connect \mul_op__oe__oe$8 \mul1_mul_op__oe__oe$40 - connect \mul_op__oe__ok$9 \mul1_mul_op__oe__ok$41 - connect \mul_op__write_cr0$10 \mul1_mul_op__write_cr0$42 - connect \mul_op__is_32bit$11 \mul1_mul_op__is_32bit$43 - connect \mul_op__is_signed$12 \mul1_mul_op__is_signed$44 - connect \mul_op__insn$13 \mul1_mul_op__insn$45 - connect \ra$14 \mul1_ra$46 - connect \rb$15 \mul1_rb$47 - connect \xer_so$16 \mul1_xer_so$48 - connect \neg_res \mul1_neg_res - connect \neg_res32 \mul1_neg_res32 - end - process $group_0 - assign \input_muxid 2'00 - assign \input_muxid \muxid$1 - sync init - end - process $group_1 - assign \input_mul_op__insn_type 7'0000000 - assign \input_mul_op__fn_unit 11'00000000000 - assign \input_mul_op__imm_data__data 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \input_mul_op__imm_data__ok 1'0 - assign \input_mul_op__rc__rc 1'0 - assign \input_mul_op__rc__ok 1'0 - assign \input_mul_op__oe__oe 1'0 - assign \input_mul_op__oe__ok 1'0 - assign \input_mul_op__write_cr0 1'0 - assign \input_mul_op__is_32bit 1'0 - assign \input_mul_op__is_signed 1'0 - assign \input_mul_op__insn 32'00000000000000000000000000000000 - assign { \input_mul_op__insn \input_mul_op__is_signed \input_mul_op__is_32bit \input_mul_op__write_cr0 { \input_mul_op__oe__ok \input_mul_op__oe__oe } { \input_mul_op__rc__ok \input_mul_op__rc__rc } { \input_mul_op__imm_data__ok \input_mul_op__imm_data__data } \input_mul_op__fn_unit \input_mul_op__insn_type } { \mul_op__insn$13 \mul_op__is_signed$12 \mul_op__is_32bit$11 \mul_op__write_cr0$10 { \mul_op__oe__ok$9 \mul_op__oe__oe$8 } { \mul_op__rc__ok$7 \mul_op__rc__rc$6 } { \mul_op__imm_data__ok$5 \mul_op__imm_data__data$4 } \mul_op__fn_unit$3 \mul_op__insn_type$2 } - sync init - end - process $group_13 - assign \input_ra 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \input_ra \ra$14 - sync init - end - process $group_14 - assign \input_rb 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \input_rb \rb$15 - sync init - end - process $group_15 - assign \input_xer_so 1'0 - assign \input_xer_so \xer_so$16 - sync init - end - process $group_16 - assign \mul1_muxid 2'00 - assign \mul1_muxid \input_muxid$17 - sync init - end - process $group_17 - assign \mul1_mul_op__insn_type 7'0000000 - assign \mul1_mul_op__fn_unit 11'00000000000 - assign \mul1_mul_op__imm_data__data 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \mul1_mul_op__imm_data__ok 1'0 - assign \mul1_mul_op__rc__rc 1'0 - assign \mul1_mul_op__rc__ok 1'0 - assign \mul1_mul_op__oe__oe 1'0 - assign \mul1_mul_op__oe__ok 1'0 - assign \mul1_mul_op__write_cr0 1'0 - assign \mul1_mul_op__is_32bit 1'0 - assign \mul1_mul_op__is_signed 1'0 - assign \mul1_mul_op__insn 32'00000000000000000000000000000000 - assign { \mul1_mul_op__insn \mul1_mul_op__is_signed \mul1_mul_op__is_32bit \mul1_mul_op__write_cr0 { \mul1_mul_op__oe__ok \mul1_mul_op__oe__oe } { \mul1_mul_op__rc__ok \mul1_mul_op__rc__rc } { \mul1_mul_op__imm_data__ok \mul1_mul_op__imm_data__data } \mul1_mul_op__fn_unit \mul1_mul_op__insn_type } { \input_mul_op__insn$29 \input_mul_op__is_signed$28 \input_mul_op__is_32bit$27 \input_mul_op__write_cr0$26 { \input_mul_op__oe__ok$25 \input_mul_op__oe__oe$24 } { \input_mul_op__rc__ok$23 \input_mul_op__rc__rc$22 } { \input_mul_op__imm_data__ok$21 \input_mul_op__imm_data__data$20 } \input_mul_op__fn_unit$19 \input_mul_op__insn_type$18 } - sync init - end - process $group_29 - assign \mul1_ra 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \mul1_ra \input_ra$30 - sync init - end - process $group_30 - assign \mul1_rb 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \mul1_rb \input_rb$31 - sync init - end - process $group_31 - assign \mul1_xer_so 1'0 - assign \mul1_xer_so \input_xer_so$32 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:621" - wire width 1 \p_valid_i$49 - process $group_32 - assign \p_valid_i$49 1'0 - assign \p_valid_i$49 \p_valid_i - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:619" - wire width 1 \n_i_rdy_data - process $group_33 - assign \n_i_rdy_data 1'0 - assign \n_i_rdy_data \n_ready_i - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" - wire width 1 \p_valid_i_p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" - wire width 1 $50 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" - cell $and $51 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \p_valid_i$49 - connect \B \p_ready_o - connect \Y $50 - end - process $group_34 - assign \p_valid_i_p_ready_o 1'0 - assign \p_valid_i_p_ready_o $50 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \muxid$52 - process $group_35 - assign \muxid$52 2'00 - assign \muxid$52 \mul1_muxid$33 - sync init - end - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \mul_op__insn_type$53 - attribute \enum_base_type "Function" - attribute \enum_value_00000000000 "NONE" - attribute \enum_value_00000000010 "ALU" - attribute \enum_value_00000000100 "LDST" - attribute \enum_value_00000001000 "SHIFT_ROT" - attribute \enum_value_00000010000 "LOGICAL" - attribute \enum_value_00000100000 "BRANCH" - attribute \enum_value_00001000000 "CR" - attribute \enum_value_00010000000 "TRAP" - attribute \enum_value_00100000000 "MUL" - attribute \enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 \mul_op__fn_unit$54 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \mul_op__imm_data__data$55 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \mul_op__imm_data__ok$56 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \mul_op__rc__rc$57 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \mul_op__rc__ok$58 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \mul_op__oe__oe$59 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \mul_op__oe__ok$60 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \mul_op__write_cr0$61 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \mul_op__is_32bit$62 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \mul_op__is_signed$63 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \mul_op__insn$64 - process $group_36 - assign \mul_op__insn_type$53 7'0000000 - assign \mul_op__fn_unit$54 11'00000000000 - assign \mul_op__imm_data__data$55 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \mul_op__imm_data__ok$56 1'0 - assign \mul_op__rc__rc$57 1'0 - assign \mul_op__rc__ok$58 1'0 - assign \mul_op__oe__oe$59 1'0 - assign \mul_op__oe__ok$60 1'0 - assign \mul_op__write_cr0$61 1'0 - assign \mul_op__is_32bit$62 1'0 - assign \mul_op__is_signed$63 1'0 - assign \mul_op__insn$64 32'00000000000000000000000000000000 - assign { \mul_op__insn$64 \mul_op__is_signed$63 \mul_op__is_32bit$62 \mul_op__write_cr0$61 { \mul_op__oe__ok$60 \mul_op__oe__oe$59 } { \mul_op__rc__ok$58 \mul_op__rc__rc$57 } { \mul_op__imm_data__ok$56 \mul_op__imm_data__data$55 } \mul_op__fn_unit$54 \mul_op__insn_type$53 } { \mul1_mul_op__insn$45 \mul1_mul_op__is_signed$44 \mul1_mul_op__is_32bit$43 \mul1_mul_op__write_cr0$42 { \mul1_mul_op__oe__ok$41 \mul1_mul_op__oe__oe$40 } { \mul1_mul_op__rc__ok$39 \mul1_mul_op__rc__rc$38 } { \mul1_mul_op__imm_data__ok$37 \mul1_mul_op__imm_data__data$36 } \mul1_mul_op__fn_unit$35 \mul1_mul_op__insn_type$34 } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \ra$65 - process $group_48 - assign \ra$65 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \ra$65 \mul1_ra$46 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \rb$66 - process $group_49 - assign \rb$66 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \rb$66 \mul1_rb$47 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 1 \xer_so$67 - process $group_50 - assign \xer_so$67 1'0 - assign \xer_so$67 \mul1_xer_so$48 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:11" - wire width 1 \neg_res$68 - process $group_51 - assign \neg_res$68 1'0 - assign \neg_res$68 \mul1_neg_res - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:12" - wire width 1 \neg_res32$69 - process $group_52 - assign \neg_res32$69 1'0 - assign \neg_res32$69 \mul1_neg_res32 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615" - wire width 1 \r_busy - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615" - wire width 1 \r_busy$next - process $group_53 - assign \r_busy$next \r_busy - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign \r_busy$next 1'1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign \r_busy$next 1'0 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \r_busy$next 1'0 - end - sync init - update \r_busy 1'0 - sync posedge \coresync_clk - update \r_busy \r_busy$next - end - process $group_54 - assign \muxid$next \muxid - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign \muxid$next \muxid$52 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign \muxid$next \muxid$52 - end - sync init - update \muxid 2'00 - sync posedge \coresync_clk - update \muxid \muxid$next - end - process $group_55 - assign \mul_op__insn_type$next \mul_op__insn_type - assign \mul_op__fn_unit$next \mul_op__fn_unit - assign \mul_op__imm_data__data$next \mul_op__imm_data__data - assign \mul_op__imm_data__ok$next \mul_op__imm_data__ok - assign \mul_op__rc__rc$next \mul_op__rc__rc - assign \mul_op__rc__ok$next \mul_op__rc__ok - assign \mul_op__oe__oe$next \mul_op__oe__oe - assign \mul_op__oe__ok$next \mul_op__oe__ok - assign \mul_op__write_cr0$next \mul_op__write_cr0 - assign \mul_op__is_32bit$next \mul_op__is_32bit - assign \mul_op__is_signed$next \mul_op__is_signed - assign \mul_op__insn$next \mul_op__insn - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign { \mul_op__insn$next \mul_op__is_signed$next \mul_op__is_32bit$next \mul_op__write_cr0$next { \mul_op__oe__ok$next \mul_op__oe__oe$next } { \mul_op__rc__ok$next \mul_op__rc__rc$next } { \mul_op__imm_data__ok$next \mul_op__imm_data__data$next } \mul_op__fn_unit$next \mul_op__insn_type$next } { \mul_op__insn$64 \mul_op__is_signed$63 \mul_op__is_32bit$62 \mul_op__write_cr0$61 { \mul_op__oe__ok$60 \mul_op__oe__oe$59 } { \mul_op__rc__ok$58 \mul_op__rc__rc$57 } { \mul_op__imm_data__ok$56 \mul_op__imm_data__data$55 } \mul_op__fn_unit$54 \mul_op__insn_type$53 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign { \mul_op__insn$next \mul_op__is_signed$next \mul_op__is_32bit$next \mul_op__write_cr0$next { \mul_op__oe__ok$next \mul_op__oe__oe$next } { \mul_op__rc__ok$next \mul_op__rc__rc$next } { \mul_op__imm_data__ok$next \mul_op__imm_data__data$next } \mul_op__fn_unit$next \mul_op__insn_type$next } { \mul_op__insn$64 \mul_op__is_signed$63 \mul_op__is_32bit$62 \mul_op__write_cr0$61 { \mul_op__oe__ok$60 \mul_op__oe__oe$59 } { \mul_op__rc__ok$58 \mul_op__rc__rc$57 } { \mul_op__imm_data__ok$56 \mul_op__imm_data__data$55 } \mul_op__fn_unit$54 \mul_op__insn_type$53 } - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \mul_op__imm_data__data$next 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \mul_op__imm_data__ok$next 1'0 - assign \mul_op__rc__rc$next 1'0 - assign \mul_op__rc__ok$next 1'0 - assign \mul_op__oe__oe$next 1'0 - assign \mul_op__oe__ok$next 1'0 - end - sync init - update \mul_op__insn_type 7'0000000 - update \mul_op__fn_unit 11'00000000000 - update \mul_op__imm_data__data 64'0000000000000000000000000000000000000000000000000000000000000000 - update \mul_op__imm_data__ok 1'0 - update \mul_op__rc__rc 1'0 - update \mul_op__rc__ok 1'0 - update \mul_op__oe__oe 1'0 - update \mul_op__oe__ok 1'0 - update \mul_op__write_cr0 1'0 - update \mul_op__is_32bit 1'0 - update \mul_op__is_signed 1'0 - update \mul_op__insn 32'00000000000000000000000000000000 - sync posedge \coresync_clk - update \mul_op__insn_type \mul_op__insn_type$next - update \mul_op__fn_unit \mul_op__fn_unit$next - update \mul_op__imm_data__data \mul_op__imm_data__data$next - update \mul_op__imm_data__ok \mul_op__imm_data__ok$next - update \mul_op__rc__rc \mul_op__rc__rc$next - update \mul_op__rc__ok \mul_op__rc__ok$next - update \mul_op__oe__oe \mul_op__oe__oe$next - update \mul_op__oe__ok \mul_op__oe__ok$next - update \mul_op__write_cr0 \mul_op__write_cr0$next - update \mul_op__is_32bit \mul_op__is_32bit$next - update \mul_op__is_signed \mul_op__is_signed$next - update \mul_op__insn \mul_op__insn$next - end - process $group_67 - assign \ra$next \ra - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign \ra$next \ra$65 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign \ra$next \ra$65 - end - sync init - update \ra 64'0000000000000000000000000000000000000000000000000000000000000000 - sync posedge \coresync_clk - update \ra \ra$next - end - process $group_68 - assign \rb$next \rb - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign \rb$next \rb$66 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign \rb$next \rb$66 - end - sync init - update \rb 64'0000000000000000000000000000000000000000000000000000000000000000 - sync posedge \coresync_clk - update \rb \rb$next - end - process $group_69 - assign \xer_so$next \xer_so - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign \xer_so$next \xer_so$67 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign \xer_so$next \xer_so$67 - end - sync init - update \xer_so 1'0 - sync posedge \coresync_clk - update \xer_so \xer_so$next - end - process $group_70 - assign \neg_res$next \neg_res - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign \neg_res$next \neg_res$68 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign \neg_res$next \neg_res$68 - end - sync init - update \neg_res 1'0 - sync posedge \coresync_clk - update \neg_res \neg_res$next - end - process $group_71 - assign \neg_res32$next \neg_res32 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign \neg_res32$next \neg_res32$69 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign \neg_res32$next \neg_res32$69 - end - sync init - update \neg_res32 1'0 - sync posedge \coresync_clk - update \neg_res32 \neg_res32$next - end - process $group_72 - assign \n_valid_o 1'0 - assign \n_valid_o \r_busy - sync init - end - process $group_73 - assign \p_ready_o 1'0 - assign \p_ready_o \n_i_rdy_data - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.mul0.alu_mul0.mul_pipe2.p" -module \p$93 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" - wire width 1 input 0 \p_valid_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" - wire width 1 input 1 \p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:158" - wire width 1 \trigger - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" - cell $and $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \p_valid_i - connect \B \p_ready_o - connect \Y $1 - end - process $group_0 - assign \trigger 1'0 - assign \trigger $1 - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.mul0.alu_mul0.mul_pipe2.n" -module \n$94 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" - wire width 1 input 0 \n_valid_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" - wire width 1 input 1 \n_ready_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:251" - wire width 1 \trigger - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" - cell $and $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \n_ready_i - connect \B \n_valid_o - connect \Y $1 - end - process $group_0 - assign \trigger 1'0 - assign \trigger $1 - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.mul0.alu_mul0.mul_pipe2.mul2" -module \mul2 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 input 0 \muxid - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 input 1 \mul_op__insn_type - attribute \enum_base_type "Function" - attribute \enum_value_00000000000 "NONE" - attribute \enum_value_00000000010 "ALU" - attribute \enum_value_00000000100 "LDST" - attribute \enum_value_00000001000 "SHIFT_ROT" - attribute \enum_value_00000010000 "LOGICAL" - attribute \enum_value_00000100000 "BRANCH" - attribute \enum_value_00001000000 "CR" - attribute \enum_value_00010000000 "TRAP" - attribute \enum_value_00100000000 "MUL" - attribute \enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 input 2 \mul_op__fn_unit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 input 3 \mul_op__imm_data__data - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 4 \mul_op__imm_data__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 5 \mul_op__rc__rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 6 \mul_op__rc__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 7 \mul_op__oe__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 8 \mul_op__oe__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 9 \mul_op__write_cr0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 10 \mul_op__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 11 \mul_op__is_signed - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 input 12 \mul_op__insn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 13 \ra - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 14 \rb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 1 input 15 \xer_so - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:11" - wire width 1 input 16 \neg_res - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:12" - wire width 1 input 17 \neg_res32 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 output 18 \muxid$1 - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 output 19 \mul_op__insn_type$2 - attribute \enum_base_type "Function" - attribute \enum_value_00000000000 "NONE" - attribute \enum_value_00000000010 "ALU" - attribute \enum_value_00000000100 "LDST" - attribute \enum_value_00000001000 "SHIFT_ROT" - attribute \enum_value_00000010000 "LOGICAL" - attribute \enum_value_00000100000 "BRANCH" - attribute \enum_value_00001000000 "CR" - attribute \enum_value_00010000000 "TRAP" - attribute \enum_value_00100000000 "MUL" - attribute \enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 output 20 \mul_op__fn_unit$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 output 21 \mul_op__imm_data__data$4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 22 \mul_op__imm_data__ok$5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 23 \mul_op__rc__rc$6 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 24 \mul_op__rc__ok$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 25 \mul_op__oe__oe$8 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 26 \mul_op__oe__ok$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 27 \mul_op__write_cr0$10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 28 \mul_op__is_32bit$11 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 29 \mul_op__is_signed$12 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 output 30 \mul_op__insn$13 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 129 output 31 \o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 1 output 32 \xer_so$14 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:23" - wire width 1 output 33 \neg_res$15 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:24" - wire width 1 output 34 \neg_res32$16 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/main_stage.py:28" - wire width 129 $17 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/main_stage.py:28" - wire width 128 $18 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/main_stage.py:28" - cell $mul $19 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \B_SIGNED 0 - parameter \B_WIDTH 64 - parameter \Y_WIDTH 128 - connect \A \ra - connect \B \rb - connect \Y $18 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/main_stage.py:28" - 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\enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \mul2_mul_op__insn_type - attribute \enum_base_type "Function" - attribute \enum_value_00000000000 "NONE" - attribute \enum_value_00000000010 "ALU" - attribute \enum_value_00000000100 "LDST" - attribute \enum_value_00000001000 "SHIFT_ROT" - attribute \enum_value_00000010000 "LOGICAL" - attribute \enum_value_00000100000 "BRANCH" - attribute \enum_value_00001000000 "CR" - attribute \enum_value_00010000000 "TRAP" - attribute \enum_value_00100000000 "MUL" - attribute \enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 \mul2_mul_op__fn_unit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \mul2_mul_op__imm_data__data - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \mul2_mul_op__imm_data__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \mul2_mul_op__rc__rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \mul2_mul_op__rc__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \mul2_mul_op__oe__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \mul2_mul_op__oe__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \mul2_mul_op__write_cr0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \mul2_mul_op__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \mul2_mul_op__is_signed - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \mul2_mul_op__insn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \mul2_ra - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \mul2_rb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 1 \mul2_xer_so - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:11" - wire width 1 \mul2_neg_res - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:12" - wire width 1 \mul2_neg_res32 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \mul2_muxid$17 - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \mul2_mul_op__insn_type$18 - attribute \enum_base_type "Function" - attribute \enum_value_00000000000 "NONE" - attribute \enum_value_00000000010 "ALU" - attribute \enum_value_00000000100 "LDST" - attribute \enum_value_00000001000 "SHIFT_ROT" - attribute \enum_value_00000010000 "LOGICAL" - attribute \enum_value_00000100000 "BRANCH" - attribute \enum_value_00001000000 "CR" - attribute \enum_value_00010000000 "TRAP" - attribute \enum_value_00100000000 "MUL" - attribute \enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 \mul2_mul_op__fn_unit$19 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \mul2_mul_op__imm_data__data$20 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \mul2_mul_op__imm_data__ok$21 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \mul2_mul_op__rc__rc$22 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \mul2_mul_op__rc__ok$23 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \mul2_mul_op__oe__oe$24 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \mul2_mul_op__oe__ok$25 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \mul2_mul_op__write_cr0$26 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \mul2_mul_op__is_32bit$27 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \mul2_mul_op__is_signed$28 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \mul2_mul_op__insn$29 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 129 \mul2_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 1 \mul2_xer_so$30 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:23" - wire width 1 \mul2_neg_res$31 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:24" - wire width 1 \mul2_neg_res32$32 - cell \mul2 \mul2 - connect \muxid \mul2_muxid - connect \mul_op__insn_type \mul2_mul_op__insn_type - connect \mul_op__fn_unit \mul2_mul_op__fn_unit - connect \mul_op__imm_data__data \mul2_mul_op__imm_data__data - connect \mul_op__imm_data__ok \mul2_mul_op__imm_data__ok - connect \mul_op__rc__rc \mul2_mul_op__rc__rc - connect \mul_op__rc__ok \mul2_mul_op__rc__ok - connect \mul_op__oe__oe \mul2_mul_op__oe__oe - connect \mul_op__oe__ok \mul2_mul_op__oe__ok - connect \mul_op__write_cr0 \mul2_mul_op__write_cr0 - connect \mul_op__is_32bit \mul2_mul_op__is_32bit - connect \mul_op__is_signed \mul2_mul_op__is_signed - connect \mul_op__insn \mul2_mul_op__insn - connect \ra \mul2_ra - connect \rb \mul2_rb - connect \xer_so \mul2_xer_so - connect \neg_res \mul2_neg_res - connect \neg_res32 \mul2_neg_res32 - connect \muxid$1 \mul2_muxid$17 - connect \mul_op__insn_type$2 \mul2_mul_op__insn_type$18 - connect \mul_op__fn_unit$3 \mul2_mul_op__fn_unit$19 - connect \mul_op__imm_data__data$4 \mul2_mul_op__imm_data__data$20 - connect \mul_op__imm_data__ok$5 \mul2_mul_op__imm_data__ok$21 - connect \mul_op__rc__rc$6 \mul2_mul_op__rc__rc$22 - connect \mul_op__rc__ok$7 \mul2_mul_op__rc__ok$23 - connect \mul_op__oe__oe$8 \mul2_mul_op__oe__oe$24 - connect \mul_op__oe__ok$9 \mul2_mul_op__oe__ok$25 - connect \mul_op__write_cr0$10 \mul2_mul_op__write_cr0$26 - connect \mul_op__is_32bit$11 \mul2_mul_op__is_32bit$27 - connect \mul_op__is_signed$12 \mul2_mul_op__is_signed$28 - connect \mul_op__insn$13 \mul2_mul_op__insn$29 - connect \o \mul2_o - connect \xer_so$14 \mul2_xer_so$30 - connect \neg_res$15 \mul2_neg_res$31 - connect \neg_res32$16 \mul2_neg_res32$32 - end - process $group_0 - assign \mul2_muxid 2'00 - assign \mul2_muxid \muxid - sync init - end - process $group_1 - assign \mul2_mul_op__insn_type 7'0000000 - assign \mul2_mul_op__fn_unit 11'00000000000 - assign \mul2_mul_op__imm_data__data 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \mul2_mul_op__imm_data__ok 1'0 - assign \mul2_mul_op__rc__rc 1'0 - assign \mul2_mul_op__rc__ok 1'0 - assign \mul2_mul_op__oe__oe 1'0 - assign \mul2_mul_op__oe__ok 1'0 - assign \mul2_mul_op__write_cr0 1'0 - assign \mul2_mul_op__is_32bit 1'0 - assign \mul2_mul_op__is_signed 1'0 - assign \mul2_mul_op__insn 32'00000000000000000000000000000000 - assign { \mul2_mul_op__insn \mul2_mul_op__is_signed \mul2_mul_op__is_32bit \mul2_mul_op__write_cr0 { \mul2_mul_op__oe__ok \mul2_mul_op__oe__oe } { \mul2_mul_op__rc__ok \mul2_mul_op__rc__rc } { \mul2_mul_op__imm_data__ok \mul2_mul_op__imm_data__data } \mul2_mul_op__fn_unit \mul2_mul_op__insn_type } { \mul_op__insn \mul_op__is_signed \mul_op__is_32bit \mul_op__write_cr0 { \mul_op__oe__ok \mul_op__oe__oe } { \mul_op__rc__ok \mul_op__rc__rc } { \mul_op__imm_data__ok \mul_op__imm_data__data } \mul_op__fn_unit \mul_op__insn_type } - sync init - end - process $group_13 - assign \mul2_ra 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \mul2_ra \ra - sync init - end - process $group_14 - assign \mul2_rb 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \mul2_rb \rb - sync init - end - process $group_15 - assign \mul2_xer_so 1'0 - assign \mul2_xer_so \xer_so - sync init - end - process $group_16 - assign \mul2_neg_res 1'0 - assign \mul2_neg_res \neg_res - sync init - end - process $group_17 - assign \mul2_neg_res32 1'0 - assign \mul2_neg_res32 \neg_res32 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:621" - wire width 1 \p_valid_i$33 - process $group_18 - assign \p_valid_i$33 1'0 - assign \p_valid_i$33 \p_valid_i - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:619" - wire width 1 \n_i_rdy_data - process $group_19 - assign \n_i_rdy_data 1'0 - assign \n_i_rdy_data \n_ready_i - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" - wire width 1 \p_valid_i_p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" - wire width 1 $34 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" - cell $and $35 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \p_valid_i$33 - connect \B \p_ready_o - connect \Y $34 - end - process $group_20 - assign \p_valid_i_p_ready_o 1'0 - assign \p_valid_i_p_ready_o $34 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \muxid$36 - process $group_21 - assign \muxid$36 2'00 - assign \muxid$36 \mul2_muxid$17 - sync init - end - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \mul_op__insn_type$37 - attribute \enum_base_type "Function" - attribute \enum_value_00000000000 "NONE" - attribute \enum_value_00000000010 "ALU" - attribute \enum_value_00000000100 "LDST" - attribute \enum_value_00000001000 "SHIFT_ROT" - attribute \enum_value_00000010000 "LOGICAL" - attribute \enum_value_00000100000 "BRANCH" - attribute \enum_value_00001000000 "CR" - attribute \enum_value_00010000000 "TRAP" - attribute \enum_value_00100000000 "MUL" - attribute \enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 \mul_op__fn_unit$38 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \mul_op__imm_data__data$39 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \mul_op__imm_data__ok$40 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \mul_op__rc__rc$41 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \mul_op__rc__ok$42 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \mul_op__oe__oe$43 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \mul_op__oe__ok$44 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \mul_op__write_cr0$45 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \mul_op__is_32bit$46 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \mul_op__is_signed$47 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \mul_op__insn$48 - process $group_22 - assign \mul_op__insn_type$37 7'0000000 - assign \mul_op__fn_unit$38 11'00000000000 - assign \mul_op__imm_data__data$39 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \mul_op__imm_data__ok$40 1'0 - assign \mul_op__rc__rc$41 1'0 - assign \mul_op__rc__ok$42 1'0 - assign \mul_op__oe__oe$43 1'0 - assign \mul_op__oe__ok$44 1'0 - assign \mul_op__write_cr0$45 1'0 - assign \mul_op__is_32bit$46 1'0 - assign \mul_op__is_signed$47 1'0 - assign \mul_op__insn$48 32'00000000000000000000000000000000 - assign { \mul_op__insn$48 \mul_op__is_signed$47 \mul_op__is_32bit$46 \mul_op__write_cr0$45 { \mul_op__oe__ok$44 \mul_op__oe__oe$43 } { \mul_op__rc__ok$42 \mul_op__rc__rc$41 } { \mul_op__imm_data__ok$40 \mul_op__imm_data__data$39 } \mul_op__fn_unit$38 \mul_op__insn_type$37 } { \mul2_mul_op__insn$29 \mul2_mul_op__is_signed$28 \mul2_mul_op__is_32bit$27 \mul2_mul_op__write_cr0$26 { \mul2_mul_op__oe__ok$25 \mul2_mul_op__oe__oe$24 } { \mul2_mul_op__rc__ok$23 \mul2_mul_op__rc__rc$22 } { \mul2_mul_op__imm_data__ok$21 \mul2_mul_op__imm_data__data$20 } \mul2_mul_op__fn_unit$19 \mul2_mul_op__insn_type$18 } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 129 \o$49 - process $group_34 - assign \o$49 129'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \o$49 \mul2_o - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 1 \xer_so$50 - process $group_35 - assign \xer_so$50 1'0 - assign \xer_so$50 \mul2_xer_so$30 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:23" - wire width 1 \neg_res$51 - process $group_36 - assign \neg_res$51 1'0 - assign \neg_res$51 \mul2_neg_res$31 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:24" - wire width 1 \neg_res32$52 - process $group_37 - assign \neg_res32$52 1'0 - assign \neg_res32$52 \mul2_neg_res32$32 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615" - wire width 1 \r_busy - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615" - wire width 1 \r_busy$next - process $group_38 - assign \r_busy$next \r_busy - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign \r_busy$next 1'1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign \r_busy$next 1'0 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \r_busy$next 1'0 - end - sync init - update \r_busy 1'0 - sync posedge \coresync_clk - update \r_busy \r_busy$next - end - process $group_39 - assign \muxid$1$next \muxid$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign \muxid$1$next \muxid$36 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign \muxid$1$next \muxid$36 - end - sync init - update \muxid$1 2'00 - sync posedge \coresync_clk - update \muxid$1 \muxid$1$next - end - process $group_40 - assign \mul_op__insn_type$2$next \mul_op__insn_type$2 - assign \mul_op__fn_unit$3$next \mul_op__fn_unit$3 - assign \mul_op__imm_data__data$4$next \mul_op__imm_data__data$4 - assign \mul_op__imm_data__ok$5$next \mul_op__imm_data__ok$5 - assign \mul_op__rc__rc$6$next \mul_op__rc__rc$6 - assign \mul_op__rc__ok$7$next \mul_op__rc__ok$7 - assign \mul_op__oe__oe$8$next \mul_op__oe__oe$8 - assign \mul_op__oe__ok$9$next \mul_op__oe__ok$9 - assign \mul_op__write_cr0$10$next \mul_op__write_cr0$10 - assign \mul_op__is_32bit$11$next \mul_op__is_32bit$11 - assign \mul_op__is_signed$12$next \mul_op__is_signed$12 - assign \mul_op__insn$13$next \mul_op__insn$13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign { \mul_op__insn$13$next \mul_op__is_signed$12$next \mul_op__is_32bit$11$next \mul_op__write_cr0$10$next { \mul_op__oe__ok$9$next \mul_op__oe__oe$8$next } { \mul_op__rc__ok$7$next \mul_op__rc__rc$6$next } { \mul_op__imm_data__ok$5$next \mul_op__imm_data__data$4$next } \mul_op__fn_unit$3$next \mul_op__insn_type$2$next } { \mul_op__insn$48 \mul_op__is_signed$47 \mul_op__is_32bit$46 \mul_op__write_cr0$45 { \mul_op__oe__ok$44 \mul_op__oe__oe$43 } { \mul_op__rc__ok$42 \mul_op__rc__rc$41 } { \mul_op__imm_data__ok$40 \mul_op__imm_data__data$39 } \mul_op__fn_unit$38 \mul_op__insn_type$37 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign { \mul_op__insn$13$next \mul_op__is_signed$12$next \mul_op__is_32bit$11$next \mul_op__write_cr0$10$next { \mul_op__oe__ok$9$next \mul_op__oe__oe$8$next } { \mul_op__rc__ok$7$next \mul_op__rc__rc$6$next } { \mul_op__imm_data__ok$5$next \mul_op__imm_data__data$4$next } \mul_op__fn_unit$3$next \mul_op__insn_type$2$next } { \mul_op__insn$48 \mul_op__is_signed$47 \mul_op__is_32bit$46 \mul_op__write_cr0$45 { \mul_op__oe__ok$44 \mul_op__oe__oe$43 } { \mul_op__rc__ok$42 \mul_op__rc__rc$41 } { \mul_op__imm_data__ok$40 \mul_op__imm_data__data$39 } \mul_op__fn_unit$38 \mul_op__insn_type$37 } - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \mul_op__imm_data__data$4$next 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \mul_op__imm_data__ok$5$next 1'0 - assign \mul_op__rc__rc$6$next 1'0 - assign \mul_op__rc__ok$7$next 1'0 - assign \mul_op__oe__oe$8$next 1'0 - assign \mul_op__oe__ok$9$next 1'0 - end - sync init - update \mul_op__insn_type$2 7'0000000 - update \mul_op__fn_unit$3 11'00000000000 - update \mul_op__imm_data__data$4 64'0000000000000000000000000000000000000000000000000000000000000000 - update \mul_op__imm_data__ok$5 1'0 - update \mul_op__rc__rc$6 1'0 - update \mul_op__rc__ok$7 1'0 - update \mul_op__oe__oe$8 1'0 - update \mul_op__oe__ok$9 1'0 - update \mul_op__write_cr0$10 1'0 - update \mul_op__is_32bit$11 1'0 - update \mul_op__is_signed$12 1'0 - update \mul_op__insn$13 32'00000000000000000000000000000000 - sync posedge \coresync_clk - update \mul_op__insn_type$2 \mul_op__insn_type$2$next - update \mul_op__fn_unit$3 \mul_op__fn_unit$3$next - update \mul_op__imm_data__data$4 \mul_op__imm_data__data$4$next - update \mul_op__imm_data__ok$5 \mul_op__imm_data__ok$5$next - update \mul_op__rc__rc$6 \mul_op__rc__rc$6$next - update \mul_op__rc__ok$7 \mul_op__rc__ok$7$next - update \mul_op__oe__oe$8 \mul_op__oe__oe$8$next - update \mul_op__oe__ok$9 \mul_op__oe__ok$9$next - update \mul_op__write_cr0$10 \mul_op__write_cr0$10$next - update \mul_op__is_32bit$11 \mul_op__is_32bit$11$next - update \mul_op__is_signed$12 \mul_op__is_signed$12$next - update \mul_op__insn$13 \mul_op__insn$13$next - end - process $group_52 - assign \o$next \o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign \o$next \o$49 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign \o$next \o$49 - end - sync init - update \o 129'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - sync posedge \coresync_clk - update \o \o$next - end - process $group_53 - assign \xer_so$14$next \xer_so$14 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign \xer_so$14$next \xer_so$50 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign \xer_so$14$next \xer_so$50 - end - sync init - update \xer_so$14 1'0 - sync posedge \coresync_clk - update \xer_so$14 \xer_so$14$next - end - process $group_54 - assign \neg_res$15$next \neg_res$15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign \neg_res$15$next \neg_res$51 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign \neg_res$15$next \neg_res$51 - end - sync init - update \neg_res$15 1'0 - sync posedge \coresync_clk - update \neg_res$15 \neg_res$15$next - end - process $group_55 - assign \neg_res32$16$next \neg_res32$16 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign \neg_res32$16$next \neg_res32$52 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign \neg_res32$16$next \neg_res32$52 - end - sync init - update \neg_res32$16 1'0 - sync posedge \coresync_clk - update \neg_res32$16 \neg_res32$16$next - end - process $group_56 - assign \n_valid_o 1'0 - assign \n_valid_o \r_busy - sync init - end - process $group_57 - assign \p_ready_o 1'0 - assign \p_ready_o \n_i_rdy_data - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.mul0.alu_mul0.mul_pipe3.p" -module \p$95 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" - wire width 1 input 0 \p_valid_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" - wire width 1 input 1 \p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:158" - wire width 1 \trigger - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" - cell $and $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \p_valid_i - connect \B \p_ready_o - connect \Y $1 - end - process $group_0 - assign \trigger 1'0 - assign \trigger $1 - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.mul0.alu_mul0.mul_pipe3.n" -module \n$96 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" - wire width 1 input 0 \n_valid_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" - wire width 1 input 1 \n_ready_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:251" - wire width 1 \trigger - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" - cell $and $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \n_ready_i - connect \B \n_valid_o - connect \Y $1 - end - process $group_0 - assign \trigger 1'0 - assign \trigger $1 - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.mul0.alu_mul0.mul_pipe3.mul3" -module \mul3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 input 0 \muxid - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 input 1 \mul_op__insn_type - attribute \enum_base_type "Function" - attribute \enum_value_00000000000 "NONE" - attribute \enum_value_00000000010 "ALU" - attribute \enum_value_00000000100 "LDST" - attribute \enum_value_00000001000 "SHIFT_ROT" - attribute \enum_value_00000010000 "LOGICAL" - attribute \enum_value_00000100000 "BRANCH" - attribute \enum_value_00001000000 "CR" - attribute \enum_value_00010000000 "TRAP" - attribute \enum_value_00100000000 "MUL" - attribute \enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 input 2 \mul_op__fn_unit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 input 3 \mul_op__imm_data__data - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 4 \mul_op__imm_data__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 5 \mul_op__rc__rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 6 \mul_op__rc__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 7 \mul_op__oe__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 8 \mul_op__oe__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 9 \mul_op__write_cr0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 10 \mul_op__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 11 \mul_op__is_signed - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 input 12 \mul_op__insn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 129 input 13 \o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 1 input 14 \xer_so - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:23" - wire width 1 input 15 \neg_res - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 output 16 \muxid$1 - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 output 17 \mul_op__insn_type$2 - attribute \enum_base_type "Function" - attribute \enum_value_00000000000 "NONE" - attribute \enum_value_00000000010 "ALU" - attribute \enum_value_00000000100 "LDST" - attribute \enum_value_00000001000 "SHIFT_ROT" - attribute \enum_value_00000010000 "LOGICAL" - attribute \enum_value_00000100000 "BRANCH" - attribute \enum_value_00001000000 "CR" - attribute \enum_value_00010000000 "TRAP" - attribute \enum_value_00100000000 "MUL" - attribute \enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 output 18 \mul_op__fn_unit$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 output 19 \mul_op__imm_data__data$4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 20 \mul_op__imm_data__ok$5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 21 \mul_op__rc__rc$6 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 22 \mul_op__rc__ok$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 23 \mul_op__oe__oe$8 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 24 \mul_op__oe__ok$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 25 \mul_op__write_cr0$10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 26 \mul_op__is_32bit$11 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 27 \mul_op__is_signed$12 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 output 28 \mul_op__insn$13 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 output 29 \o$14 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 30 \o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 2 output 31 \xer_ov - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 32 \xer_ov_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 33 \xer_so$15 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 34 \xer_so_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:36" - wire width 1 \is_32bit - process $group_0 - assign \is_32bit 1'0 - assign \is_32bit \mul_op__is_32bit - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:40" - wire width 129 \mul_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:41" - wire width 130 $16 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:41" - wire width 130 $17 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:41" - cell $neg $18 - parameter \A_SIGNED 0 - parameter \A_WIDTH 129 - parameter \Y_WIDTH 130 - connect \A \o - connect \Y $17 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 130 $19 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - cell $pos $20 - parameter \A_SIGNED 0 - parameter \A_WIDTH 129 - parameter \Y_WIDTH 130 - connect \A \o - connect \Y $19 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:41" - wire width 130 $21 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:41" - cell $mux $22 - parameter \WIDTH 130 - connect \A $19 - connect \B $17 - connect \S \neg_res - connect \Y $21 - end - connect $16 $21 - process $group_1 - assign \mul_o 129'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \mul_o $16 [128:0] - sync init - end - process $group_2 - assign \o$14 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:44" - switch \mul_op__insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:46" - attribute \nmigen.decoding "OP_MUL_H32/52" - case 7'0110100 - assign \o$14 { \mul_o [63:32] \mul_o [63:32] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:50" - attribute \nmigen.decoding "OP_MUL_H64/51" - case 7'0110011 - assign \o$14 \mul_o [127:64] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:54" - attribute \nmigen.decoding "OP_MUL_L64/50" - case 7'0110010 - assign \o$14 \mul_o [63:0] - end - sync init - end - process $group_3 - assign \o_ok 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:44" - switch \mul_op__insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:46" - attribute \nmigen.decoding "OP_MUL_H32/52" - case 7'0110100 - assign \o_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:50" - attribute \nmigen.decoding "OP_MUL_H64/51" - case 7'0110011 - assign \o_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:54" - attribute \nmigen.decoding "OP_MUL_L64/50" - case 7'0110010 - assign \o_ok 1'1 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:60" - wire width 1 \mul_ov - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:65" - wire width 1 $23 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:65" - cell $reduce_bool $24 - parameter \A_SIGNED 0 - parameter \A_WIDTH 33 - parameter \Y_WIDTH 1 - connect \A \mul_o [63:31] - connect \Y $23 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:65" - wire width 1 $25 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:65" - wire width 1 $26 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:65" - cell $reduce_and $27 - parameter \A_SIGNED 0 - parameter \A_WIDTH 33 - parameter \Y_WIDTH 1 - connect \A \mul_o [63:31] - connect \Y $26 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:65" - cell $not $28 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $26 - connect \Y $25 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:65" - wire width 1 $29 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:65" - cell $and $30 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $23 - connect \B $25 - connect \Y $29 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:70" - wire width 1 $31 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:70" - cell $reduce_bool $32 - parameter \A_SIGNED 0 - parameter \A_WIDTH 65 - parameter \Y_WIDTH 1 - connect \A \mul_o [127:63] - connect \Y $31 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:70" - wire width 1 $33 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:70" - wire width 1 $34 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:70" - cell $reduce_and $35 - parameter \A_SIGNED 0 - parameter \A_WIDTH 65 - parameter \Y_WIDTH 1 - connect \A \mul_o [127:63] - connect \Y $34 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:70" - cell $not $36 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $34 - connect \Y $33 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:70" - wire width 1 $37 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:70" - cell $and $38 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $31 - connect \B $33 - connect \Y $37 - end - process $group_4 - assign \mul_ov 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:44" - switch \mul_op__insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:46" - attribute \nmigen.decoding "OP_MUL_H32/52" - case 7'0110100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:50" - attribute \nmigen.decoding "OP_MUL_H64/51" - case 7'0110011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:54" - attribute \nmigen.decoding "OP_MUL_L64/50" - case 7'0110010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:61" - switch { \is_32bit } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:61" - case 1'1 - assign \mul_ov $29 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:66" - case - assign \mul_ov $37 - end - end - sync init - end - process $group_5 - assign \xer_ov 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:44" - switch \mul_op__insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:46" - attribute \nmigen.decoding "OP_MUL_H32/52" - case 7'0110100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:50" - attribute \nmigen.decoding "OP_MUL_H64/51" - case 7'0110011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:54" - attribute \nmigen.decoding "OP_MUL_L64/50" - case 7'0110010 - assign \xer_ov { \mul_ov \mul_ov } - end - sync init - end - process $group_6 - assign \xer_ov_ok 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:44" - switch \mul_op__insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:46" - attribute \nmigen.decoding "OP_MUL_H32/52" - case 7'0110100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:50" - attribute \nmigen.decoding "OP_MUL_H64/51" - case 7'0110011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/post_stage.py:54" - attribute \nmigen.decoding "OP_MUL_L64/50" - case 7'0110010 - assign \xer_ov_ok 1'1 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 2 $39 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - cell $pos $40 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 2 - connect \A \xer_so - connect \Y $39 - end - process $group_7 - assign \xer_so$15 1'0 - assign \xer_so_ok 1'0 - assign { \xer_so_ok \xer_so$15 } $39 - sync init - end - process $group_9 - assign \muxid$1 2'00 - assign \muxid$1 \muxid - sync init - end - process $group_10 - assign \mul_op__insn_type$2 7'0000000 - assign \mul_op__fn_unit$3 11'00000000000 - assign \mul_op__imm_data__data$4 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \mul_op__imm_data__ok$5 1'0 - assign \mul_op__rc__rc$6 1'0 - assign \mul_op__rc__ok$7 1'0 - assign \mul_op__oe__oe$8 1'0 - assign \mul_op__oe__ok$9 1'0 - assign \mul_op__write_cr0$10 1'0 - assign \mul_op__is_32bit$11 1'0 - assign \mul_op__is_signed$12 1'0 - assign \mul_op__insn$13 32'00000000000000000000000000000000 - assign { \mul_op__insn$13 \mul_op__is_signed$12 \mul_op__is_32bit$11 \mul_op__write_cr0$10 { \mul_op__oe__ok$9 \mul_op__oe__oe$8 } { \mul_op__rc__ok$7 \mul_op__rc__rc$6 } { \mul_op__imm_data__ok$5 \mul_op__imm_data__data$4 } \mul_op__fn_unit$3 \mul_op__insn_type$2 } { \mul_op__insn \mul_op__is_signed \mul_op__is_32bit \mul_op__write_cr0 { \mul_op__oe__ok \mul_op__oe__oe } { \mul_op__rc__ok \mul_op__rc__rc } { \mul_op__imm_data__ok \mul_op__imm_data__data } \mul_op__fn_unit \mul_op__insn_type } - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.mul0.alu_mul0.mul_pipe3.output" -module \output$97 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire 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attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute 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input 3 \mul_op__imm_data__data - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 4 \mul_op__imm_data__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 5 \mul_op__rc__rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 6 \mul_op__rc__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 7 \mul_op__oe__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 8 \mul_op__oe__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 9 \mul_op__write_cr0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 10 \mul_op__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 11 \mul_op__is_signed - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 input 12 \mul_op__insn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 input 13 \o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 input 14 \o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 4 input 15 \cr_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 2 input 16 \xer_ov - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 input 17 \xer_so - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 output 18 \muxid$1 - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 output 19 \mul_op__insn_type$2 - attribute \enum_base_type "Function" - attribute \enum_value_00000000000 "NONE" - attribute \enum_value_00000000010 "ALU" - attribute \enum_value_00000000100 "LDST" - attribute \enum_value_00000001000 "SHIFT_ROT" - attribute \enum_value_00000010000 "LOGICAL" - attribute \enum_value_00000100000 "BRANCH" - attribute \enum_value_00001000000 "CR" - attribute \enum_value_00010000000 "TRAP" - attribute \enum_value_00100000000 "MUL" - attribute \enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 output 20 \mul_op__fn_unit$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 output 21 \mul_op__imm_data__data$4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 22 \mul_op__imm_data__ok$5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 23 \mul_op__rc__rc$6 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 24 \mul_op__rc__ok$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 25 \mul_op__oe__oe$8 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 26 \mul_op__oe__ok$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 27 \mul_op__write_cr0$10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 28 \mul_op__is_32bit$11 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 29 \mul_op__is_signed$12 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 output 30 \mul_op__insn$13 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 output 31 \o$14 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 32 \o_ok$15 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 4 output 33 \cr_a$16 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 34 \cr_a_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 2 output 35 \xer_ov$17 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 36 \xer_ov_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 37 \xer_so$18 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 38 \xer_so_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:28" - wire width 1 \oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:29" - wire width 1 $19 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:29" - cell $and $20 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \mul_op__oe__oe - connect \B \mul_op__oe__ok - connect \Y $19 - end - process $group_0 - assign \oe 1'0 - assign \oe $19 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:27" - wire width 1 \so - process $group_1 - assign \so 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:30" - switch { \oe } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:30" - case 1'1 - assign \so \xer_so$18 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:32" - case - assign \so \xer_so - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:38" - wire width 65 \o$21 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 65 $22 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - cell $pos $23 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \Y_WIDTH 65 - connect \A \o - connect \Y $22 - end - process $group_2 - assign \o$21 65'00000000000000000000000000000000000000000000000000000000000000000 - assign \o$21 $22 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:50" - wire width 64 \target - process $group_3 - assign \target 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \target \o$21 [63:0] - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:69" - wire width 1 \is_cmp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:77" - wire width 1 $24 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:77" - cell $eq $25 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A \mul_op__insn_type - connect \B 7'0001010 - connect \Y $24 - end - process $group_4 - assign \is_cmp 1'0 - assign \is_cmp $24 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:70" - wire width 1 \is_cmpeqb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:78" - wire width 1 $26 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:78" - cell $eq $27 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A \mul_op__insn_type - connect \B 7'0001100 - connect \Y $26 - end - process $group_5 - assign \is_cmpeqb 1'0 - assign \is_cmpeqb $26 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:68" - wire width 1 \msb_test - process $group_6 - assign \msb_test 1'0 - assign \msb_test \target [63] - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:65" - wire width 1 \is_nzero - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:81" - wire width 1 $28 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:81" - cell $reduce_bool $29 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \Y_WIDTH 1 - connect \A \target - connect \Y $28 - end - process $group_7 - assign \is_nzero 1'0 - assign \is_nzero $28 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:67" - wire width 1 \is_negative - process $group_8 - assign \is_negative 1'0 - assign \is_negative \msb_test - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:66" - wire width 1 \is_positive - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:83" - wire width 1 $30 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:83" - cell $not $31 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \msb_test - connect \Y $30 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:83" - wire width 1 $32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:83" - cell $and $33 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \is_nzero - connect \B $30 - connect \Y $32 - end - process $group_9 - assign \is_positive 1'0 - assign \is_positive $32 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:71" - wire width 4 \cr0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:85" - wire width 1 $34 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:85" - cell $or $35 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \is_cmpeqb - connect \B \is_cmp - connect \Y $34 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:88" - wire width 1 $36 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:88" - cell $not $37 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \is_nzero - connect \Y $36 - end - process $group_10 - assign \cr0 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:85" - switch { $34 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:85" - case 1'1 - assign \cr0 \cr_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_output_stage.py:87" - case - assign \cr0 { \is_negative \is_positive $36 \so } - end - sync init - end - process $group_11 - assign \o$14 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \o$14 \o$21 [63:0] - sync init - end - process $group_12 - assign \o_ok$15 1'0 - assign \o_ok$15 \o_ok - sync init - end - process $group_13 - assign \cr_a$16 4'0000 - assign \cr_a$16 \cr0 - sync init - end - process $group_14 - assign \cr_a_ok 1'0 - assign \cr_a_ok \mul_op__write_cr0 - sync init - end - process $group_15 - assign \muxid$1 2'00 - assign \muxid$1 \muxid - sync init - end - process $group_16 - assign \mul_op__insn_type$2 7'0000000 - assign \mul_op__fn_unit$3 11'00000000000 - assign \mul_op__imm_data__data$4 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \mul_op__imm_data__ok$5 1'0 - assign \mul_op__rc__rc$6 1'0 - assign \mul_op__rc__ok$7 1'0 - assign \mul_op__oe__oe$8 1'0 - assign \mul_op__oe__ok$9 1'0 - assign \mul_op__write_cr0$10 1'0 - assign \mul_op__is_32bit$11 1'0 - assign \mul_op__is_signed$12 1'0 - assign \mul_op__insn$13 32'00000000000000000000000000000000 - assign { \mul_op__insn$13 \mul_op__is_signed$12 \mul_op__is_32bit$11 \mul_op__write_cr0$10 { \mul_op__oe__ok$9 \mul_op__oe__oe$8 } { \mul_op__rc__ok$7 \mul_op__rc__rc$6 } { \mul_op__imm_data__ok$5 \mul_op__imm_data__data$4 } \mul_op__fn_unit$3 \mul_op__insn_type$2 } { \mul_op__insn \mul_op__is_signed \mul_op__is_32bit \mul_op__write_cr0 { \mul_op__oe__ok \mul_op__oe__oe } { \mul_op__rc__ok \mul_op__rc__rc } { \mul_op__imm_data__ok \mul_op__imm_data__data } \mul_op__fn_unit \mul_op__insn_type } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:29" - wire width 1 \oe$38 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:30" - wire width 1 $39 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:30" - cell $and $40 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \mul_op__oe__oe - connect \B \mul_op__oe__ok - connect \Y $39 - end - process $group_28 - assign \oe$38 1'0 - assign \oe$38 $39 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:33" - wire width 1 $41 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:33" - cell $or $42 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \xer_so - connect \B \xer_ov [0] - connect \Y $41 - end - process $group_29 - assign \xer_so$18 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:31" - switch { \oe$38 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:31" - case 1'1 - assign \xer_so$18 $41 - end - sync init - end - process $group_30 - assign \xer_so_ok 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:31" - switch { \oe$38 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:31" - case 1'1 - assign \xer_so_ok 1'1 - end - sync init - end - process $group_31 - assign \xer_ov$17 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:31" - switch { \oe$38 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:31" - case 1'1 - assign \xer_ov$17 \xer_ov - end - sync init - end - process $group_32 - assign \xer_ov_ok 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:31" - switch { \oe$38 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/alu/output_stage.py:31" - case 1'1 - assign \xer_ov_ok 1'1 - end - sync init - end -end -attribute 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"/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 4 \output_cr_a$46 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \output_cr_a_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 2 \output_xer_ov$47 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \output_xer_ov_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \output_xer_so$48 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \output_xer_so_ok - cell \output$97 \output - connect \muxid \output_muxid - connect \mul_op__insn_type \output_mul_op__insn_type - connect \mul_op__fn_unit \output_mul_op__fn_unit - connect \mul_op__imm_data__data \output_mul_op__imm_data__data - connect \mul_op__imm_data__ok \output_mul_op__imm_data__ok - connect \mul_op__rc__rc \output_mul_op__rc__rc - connect \mul_op__rc__ok \output_mul_op__rc__ok - connect \mul_op__oe__oe \output_mul_op__oe__oe - connect \mul_op__oe__ok \output_mul_op__oe__ok - connect \mul_op__write_cr0 \output_mul_op__write_cr0 - connect \mul_op__is_32bit \output_mul_op__is_32bit - connect \mul_op__is_signed \output_mul_op__is_signed - connect \mul_op__insn \output_mul_op__insn - connect \o \output_o - connect \o_ok \output_o_ok - connect \cr_a \output_cr_a - connect \xer_ov \output_xer_ov - connect \xer_so \output_xer_so - connect \muxid$1 \output_muxid$31 - connect \mul_op__insn_type$2 \output_mul_op__insn_type$32 - connect \mul_op__fn_unit$3 \output_mul_op__fn_unit$33 - connect \mul_op__imm_data__data$4 \output_mul_op__imm_data__data$34 - connect \mul_op__imm_data__ok$5 \output_mul_op__imm_data__ok$35 - connect \mul_op__rc__rc$6 \output_mul_op__rc__rc$36 - connect \mul_op__rc__ok$7 \output_mul_op__rc__ok$37 - connect \mul_op__oe__oe$8 \output_mul_op__oe__oe$38 - connect \mul_op__oe__ok$9 \output_mul_op__oe__ok$39 - connect \mul_op__write_cr0$10 \output_mul_op__write_cr0$40 - connect \mul_op__is_32bit$11 \output_mul_op__is_32bit$41 - connect \mul_op__is_signed$12 \output_mul_op__is_signed$42 - connect \mul_op__insn$13 \output_mul_op__insn$43 - connect \o$14 \output_o$44 - connect \o_ok$15 \output_o_ok$45 - connect \cr_a$16 \output_cr_a$46 - connect \cr_a_ok \output_cr_a_ok - connect \xer_ov$17 \output_xer_ov$47 - connect \xer_ov_ok \output_xer_ov_ok - connect \xer_so$18 \output_xer_so$48 - connect \xer_so_ok \output_xer_so_ok - end - process $group_0 - assign \mul3_muxid 2'00 - assign \mul3_muxid \muxid - sync init - end - process $group_1 - assign \mul3_mul_op__insn_type 7'0000000 - assign \mul3_mul_op__fn_unit 11'00000000000 - assign \mul3_mul_op__imm_data__data 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \mul3_mul_op__imm_data__ok 1'0 - assign \mul3_mul_op__rc__rc 1'0 - assign \mul3_mul_op__rc__ok 1'0 - assign \mul3_mul_op__oe__oe 1'0 - assign \mul3_mul_op__oe__ok 1'0 - assign \mul3_mul_op__write_cr0 1'0 - assign \mul3_mul_op__is_32bit 1'0 - assign \mul3_mul_op__is_signed 1'0 - assign \mul3_mul_op__insn 32'00000000000000000000000000000000 - assign { \mul3_mul_op__insn \mul3_mul_op__is_signed \mul3_mul_op__is_32bit \mul3_mul_op__write_cr0 { \mul3_mul_op__oe__ok \mul3_mul_op__oe__oe } { \mul3_mul_op__rc__ok \mul3_mul_op__rc__rc } { \mul3_mul_op__imm_data__ok \mul3_mul_op__imm_data__data } \mul3_mul_op__fn_unit \mul3_mul_op__insn_type } { \mul_op__insn \mul_op__is_signed \mul_op__is_32bit \mul_op__write_cr0 { \mul_op__oe__ok \mul_op__oe__oe } { \mul_op__rc__ok \mul_op__rc__rc } { \mul_op__imm_data__ok \mul_op__imm_data__data } \mul_op__fn_unit \mul_op__insn_type } - sync init - end - process $group_13 - assign \mul3_o 129'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \mul3_o \o - sync init - end - process $group_14 - assign \mul3_xer_so 1'0 - assign \mul3_xer_so \xer_so - sync init - end - process $group_15 - assign \mul3_neg_res 1'0 - assign \mul3_neg_res \neg_res - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:24" - wire width 1 \neg_res32$49 - process $group_16 - assign \neg_res32$49 1'0 - assign \neg_res32$49 \neg_res32 - sync init - end - process $group_17 - assign \output_muxid 2'00 - assign \output_muxid \mul3_muxid$16 - sync init - end - process $group_18 - assign \output_mul_op__insn_type 7'0000000 - assign \output_mul_op__fn_unit 11'00000000000 - assign \output_mul_op__imm_data__data 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \output_mul_op__imm_data__ok 1'0 - assign \output_mul_op__rc__rc 1'0 - assign \output_mul_op__rc__ok 1'0 - assign \output_mul_op__oe__oe 1'0 - assign \output_mul_op__oe__ok 1'0 - assign \output_mul_op__write_cr0 1'0 - assign \output_mul_op__is_32bit 1'0 - assign \output_mul_op__is_signed 1'0 - assign \output_mul_op__insn 32'00000000000000000000000000000000 - assign { \output_mul_op__insn \output_mul_op__is_signed \output_mul_op__is_32bit \output_mul_op__write_cr0 { \output_mul_op__oe__ok \output_mul_op__oe__oe } { \output_mul_op__rc__ok \output_mul_op__rc__rc } { \output_mul_op__imm_data__ok \output_mul_op__imm_data__data } \output_mul_op__fn_unit \output_mul_op__insn_type } { \mul3_mul_op__insn$28 \mul3_mul_op__is_signed$27 \mul3_mul_op__is_32bit$26 \mul3_mul_op__write_cr0$25 { \mul3_mul_op__oe__ok$24 \mul3_mul_op__oe__oe$23 } { \mul3_mul_op__rc__ok$22 \mul3_mul_op__rc__rc$21 } { \mul3_mul_op__imm_data__ok$20 \mul3_mul_op__imm_data__data$19 } \mul3_mul_op__fn_unit$18 \mul3_mul_op__insn_type$17 } - sync init - end - process $group_30 - assign \output_o 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \output_o_ok 1'0 - assign { \output_o_ok \output_o } { \mul3_o_ok \mul3_o$29 } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \cr_a_ok$50 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 4 \cr_a$51 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \cr_a_ok$52 - process $group_32 - assign \output_cr_a 4'0000 - assign \cr_a_ok$50 1'0 - assign { \cr_a_ok$50 \output_cr_a } { \cr_a_ok$52 \cr_a$51 } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \xer_ov_ok$53 - process $group_34 - assign \output_xer_ov 2'00 - assign \xer_ov_ok$53 1'0 - assign { \xer_ov_ok$53 \output_xer_ov } { \mul3_xer_ov_ok \mul3_xer_ov } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \xer_so_ok$54 - process $group_36 - assign \output_xer_so 1'0 - assign \xer_so_ok$54 1'0 - assign { \xer_so_ok$54 \output_xer_so } { \mul3_xer_so_ok \mul3_xer_so$30 } - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:621" - wire width 1 \p_valid_i$55 - process $group_38 - assign \p_valid_i$55 1'0 - assign \p_valid_i$55 \p_valid_i - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:619" - wire width 1 \n_i_rdy_data - process $group_39 - assign \n_i_rdy_data 1'0 - assign \n_i_rdy_data \n_ready_i - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" - wire width 1 \p_valid_i_p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" - wire width 1 $56 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" - cell $and $57 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \p_valid_i$55 - connect \B \p_ready_o - connect \Y $56 - end - process $group_40 - assign \p_valid_i_p_ready_o 1'0 - assign \p_valid_i_p_ready_o $56 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \muxid$58 - process $group_41 - assign \muxid$58 2'00 - assign \muxid$58 \output_muxid$31 - sync init - end - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \mul_op__insn_type$59 - attribute \enum_base_type "Function" - attribute \enum_value_00000000000 "NONE" - attribute \enum_value_00000000010 "ALU" - attribute \enum_value_00000000100 "LDST" - attribute \enum_value_00000001000 "SHIFT_ROT" - attribute \enum_value_00000010000 "LOGICAL" - attribute \enum_value_00000100000 "BRANCH" - attribute \enum_value_00001000000 "CR" - attribute \enum_value_00010000000 "TRAP" - attribute \enum_value_00100000000 "MUL" - attribute \enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 \mul_op__fn_unit$60 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \mul_op__imm_data__data$61 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \mul_op__imm_data__ok$62 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \mul_op__rc__rc$63 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \mul_op__rc__ok$64 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \mul_op__oe__oe$65 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \mul_op__oe__ok$66 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \mul_op__write_cr0$67 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \mul_op__is_32bit$68 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \mul_op__is_signed$69 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \mul_op__insn$70 - process $group_42 - assign \mul_op__insn_type$59 7'0000000 - assign \mul_op__fn_unit$60 11'00000000000 - assign \mul_op__imm_data__data$61 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \mul_op__imm_data__ok$62 1'0 - assign \mul_op__rc__rc$63 1'0 - assign \mul_op__rc__ok$64 1'0 - assign \mul_op__oe__oe$65 1'0 - assign \mul_op__oe__ok$66 1'0 - assign \mul_op__write_cr0$67 1'0 - assign \mul_op__is_32bit$68 1'0 - assign \mul_op__is_signed$69 1'0 - assign \mul_op__insn$70 32'00000000000000000000000000000000 - assign { \mul_op__insn$70 \mul_op__is_signed$69 \mul_op__is_32bit$68 \mul_op__write_cr0$67 { \mul_op__oe__ok$66 \mul_op__oe__oe$65 } { \mul_op__rc__ok$64 \mul_op__rc__rc$63 } { \mul_op__imm_data__ok$62 \mul_op__imm_data__data$61 } \mul_op__fn_unit$60 \mul_op__insn_type$59 } { \output_mul_op__insn$43 \output_mul_op__is_signed$42 \output_mul_op__is_32bit$41 \output_mul_op__write_cr0$40 { \output_mul_op__oe__ok$39 \output_mul_op__oe__oe$38 } { \output_mul_op__rc__ok$37 \output_mul_op__rc__rc$36 } { \output_mul_op__imm_data__ok$35 \output_mul_op__imm_data__data$34 } \output_mul_op__fn_unit$33 \output_mul_op__insn_type$32 } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 \o$71 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \o_ok$72 - process $group_54 - assign \o$71 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \o_ok$72 1'0 - assign { \o_ok$72 \o$71 } { \output_o_ok$45 \output_o$44 } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 4 \cr_a$73 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \cr_a_ok$74 - process $group_56 - assign \cr_a$73 4'0000 - assign \cr_a_ok$74 1'0 - assign { \cr_a_ok$74 \cr_a$73 } { \output_cr_a_ok \output_cr_a$46 } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 2 \xer_ov$75 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \xer_ov_ok$76 - process $group_58 - assign \xer_ov$75 2'00 - assign \xer_ov_ok$76 1'0 - assign { \xer_ov_ok$76 \xer_ov$75 } { \output_xer_ov_ok \output_xer_ov$47 } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \xer_so$77 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \xer_so_ok$78 - process $group_60 - assign \xer_so$77 1'0 - assign \xer_so_ok$78 1'0 - assign { \xer_so_ok$78 \xer_so$77 } { \output_xer_so_ok \output_xer_so$48 } - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615" - wire width 1 \r_busy - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615" - wire width 1 \r_busy$next - process $group_62 - assign \r_busy$next \r_busy - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign \r_busy$next 1'1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign \r_busy$next 1'0 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \r_busy$next 1'0 - end - sync init - update \r_busy 1'0 - sync posedge \coresync_clk - update \r_busy \r_busy$next - end - process $group_63 - assign \muxid$1$next \muxid$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign \muxid$1$next \muxid$58 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign \muxid$1$next \muxid$58 - end - sync init - update \muxid$1 2'00 - sync posedge \coresync_clk - update \muxid$1 \muxid$1$next - end - process $group_64 - assign \mul_op__insn_type$2$next \mul_op__insn_type$2 - assign \mul_op__fn_unit$3$next \mul_op__fn_unit$3 - assign \mul_op__imm_data__data$4$next \mul_op__imm_data__data$4 - assign \mul_op__imm_data__ok$5$next \mul_op__imm_data__ok$5 - assign \mul_op__rc__rc$6$next \mul_op__rc__rc$6 - assign \mul_op__rc__ok$7$next \mul_op__rc__ok$7 - assign \mul_op__oe__oe$8$next \mul_op__oe__oe$8 - assign \mul_op__oe__ok$9$next \mul_op__oe__ok$9 - assign \mul_op__write_cr0$10$next \mul_op__write_cr0$10 - assign \mul_op__is_32bit$11$next \mul_op__is_32bit$11 - assign \mul_op__is_signed$12$next \mul_op__is_signed$12 - assign \mul_op__insn$13$next \mul_op__insn$13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign { \mul_op__insn$13$next \mul_op__is_signed$12$next \mul_op__is_32bit$11$next \mul_op__write_cr0$10$next { \mul_op__oe__ok$9$next \mul_op__oe__oe$8$next } { \mul_op__rc__ok$7$next \mul_op__rc__rc$6$next } { \mul_op__imm_data__ok$5$next \mul_op__imm_data__data$4$next } \mul_op__fn_unit$3$next \mul_op__insn_type$2$next } { \mul_op__insn$70 \mul_op__is_signed$69 \mul_op__is_32bit$68 \mul_op__write_cr0$67 { \mul_op__oe__ok$66 \mul_op__oe__oe$65 } { \mul_op__rc__ok$64 \mul_op__rc__rc$63 } { \mul_op__imm_data__ok$62 \mul_op__imm_data__data$61 } \mul_op__fn_unit$60 \mul_op__insn_type$59 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign { \mul_op__insn$13$next \mul_op__is_signed$12$next \mul_op__is_32bit$11$next \mul_op__write_cr0$10$next { \mul_op__oe__ok$9$next \mul_op__oe__oe$8$next } { \mul_op__rc__ok$7$next \mul_op__rc__rc$6$next } { \mul_op__imm_data__ok$5$next \mul_op__imm_data__data$4$next } \mul_op__fn_unit$3$next \mul_op__insn_type$2$next } { \mul_op__insn$70 \mul_op__is_signed$69 \mul_op__is_32bit$68 \mul_op__write_cr0$67 { \mul_op__oe__ok$66 \mul_op__oe__oe$65 } { \mul_op__rc__ok$64 \mul_op__rc__rc$63 } { \mul_op__imm_data__ok$62 \mul_op__imm_data__data$61 } \mul_op__fn_unit$60 \mul_op__insn_type$59 } - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \mul_op__imm_data__data$4$next 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \mul_op__imm_data__ok$5$next 1'0 - assign \mul_op__rc__rc$6$next 1'0 - assign \mul_op__rc__ok$7$next 1'0 - assign \mul_op__oe__oe$8$next 1'0 - assign \mul_op__oe__ok$9$next 1'0 - end - sync init - update \mul_op__insn_type$2 7'0000000 - update \mul_op__fn_unit$3 11'00000000000 - update \mul_op__imm_data__data$4 64'0000000000000000000000000000000000000000000000000000000000000000 - update \mul_op__imm_data__ok$5 1'0 - update \mul_op__rc__rc$6 1'0 - update \mul_op__rc__ok$7 1'0 - update \mul_op__oe__oe$8 1'0 - update \mul_op__oe__ok$9 1'0 - update \mul_op__write_cr0$10 1'0 - update \mul_op__is_32bit$11 1'0 - update \mul_op__is_signed$12 1'0 - update \mul_op__insn$13 32'00000000000000000000000000000000 - sync posedge \coresync_clk - update \mul_op__insn_type$2 \mul_op__insn_type$2$next - update \mul_op__fn_unit$3 \mul_op__fn_unit$3$next - update \mul_op__imm_data__data$4 \mul_op__imm_data__data$4$next - update \mul_op__imm_data__ok$5 \mul_op__imm_data__ok$5$next - update \mul_op__rc__rc$6 \mul_op__rc__rc$6$next - update \mul_op__rc__ok$7 \mul_op__rc__ok$7$next - update \mul_op__oe__oe$8 \mul_op__oe__oe$8$next - update \mul_op__oe__ok$9 \mul_op__oe__ok$9$next - update \mul_op__write_cr0$10 \mul_op__write_cr0$10$next - update \mul_op__is_32bit$11 \mul_op__is_32bit$11$next - update \mul_op__is_signed$12 \mul_op__is_signed$12$next - update \mul_op__insn$13 \mul_op__insn$13$next - end - process $group_76 - assign \o$14$next \o$14 - assign \o_ok$next \o_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign { \o_ok$next \o$14$next } { \o_ok$72 \o$71 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign { \o_ok$next \o$14$next } { \o_ok$72 \o$71 } - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \o_ok$next 1'0 - end - sync init - update \o$14 64'0000000000000000000000000000000000000000000000000000000000000000 - update \o_ok 1'0 - sync posedge \coresync_clk - update \o$14 \o$14$next - update \o_ok \o_ok$next - end - process $group_78 - assign \cr_a$next \cr_a - assign \cr_a_ok$next \cr_a_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign { \cr_a_ok$next \cr_a$next } { \cr_a_ok$74 \cr_a$73 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign { \cr_a_ok$next \cr_a$next } { \cr_a_ok$74 \cr_a$73 } - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \cr_a_ok$next 1'0 - end - sync init - update \cr_a 4'0000 - update \cr_a_ok 1'0 - sync posedge \coresync_clk - update \cr_a \cr_a$next - update \cr_a_ok \cr_a_ok$next - end - process $group_80 - assign \xer_ov$next \xer_ov - assign \xer_ov_ok$next \xer_ov_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign { \xer_ov_ok$next \xer_ov$next } { \xer_ov_ok$76 \xer_ov$75 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign { \xer_ov_ok$next \xer_ov$next } { \xer_ov_ok$76 \xer_ov$75 } - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \xer_ov_ok$next 1'0 - end - sync init - update \xer_ov 2'00 - update \xer_ov_ok 1'0 - sync posedge \coresync_clk - update \xer_ov \xer_ov$next - update \xer_ov_ok \xer_ov_ok$next - end - process $group_82 - assign \xer_so$15$next \xer_so$15 - assign \xer_so_ok$next \xer_so_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign { \xer_so_ok$next \xer_so$15$next } { \xer_so_ok$78 \xer_so$77 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign { \xer_so_ok$next \xer_so$15$next } { \xer_so_ok$78 \xer_so$77 } - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \xer_so_ok$next 1'0 - end - sync init - update \xer_so$15 1'0 - update \xer_so_ok 1'0 - sync posedge \coresync_clk - update \xer_so$15 \xer_so$15$next - update \xer_so_ok \xer_so_ok$next - end - process $group_84 - assign \n_valid_o 1'0 - assign \n_valid_o \r_busy - sync init - end - process $group_85 - assign \p_ready_o 1'0 - assign \p_ready_o \n_i_rdy_data - sync init - end - connect \cr_a$51 4'0000 - connect \cr_a_ok$52 1'0 -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.mul0.alu_mul0" -module \alu_mul0 - attribute \src "simple/issuer.py:141" - wire width 1 input 0 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 1 \o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 2 \cr_a_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 3 \xer_ov_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 4 \xer_so_ok - attribute \src "simple/issuer.py:141" - wire width 1 input 5 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" - wire width 1 output 6 \n_valid_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" - wire width 1 input 7 \n_ready_i - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 input 8 \mul_op__insn_type - attribute \enum_base_type "Function" - attribute \enum_value_00000000000 "NONE" - attribute \enum_value_00000000010 "ALU" - attribute \enum_value_00000000100 "LDST" - attribute \enum_value_00000001000 "SHIFT_ROT" - attribute \enum_value_00000010000 "LOGICAL" - attribute \enum_value_00000100000 "BRANCH" - attribute \enum_value_00001000000 "CR" - attribute \enum_value_00010000000 "TRAP" - attribute \enum_value_00100000000 "MUL" - attribute \enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 input 9 \mul_op__fn_unit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 input 10 \mul_op__imm_data__data - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 11 \mul_op__imm_data__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 12 \mul_op__rc__rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 13 \mul_op__rc__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 14 \mul_op__oe__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 15 \mul_op__oe__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 16 \mul_op__write_cr0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 17 \mul_op__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 18 \mul_op__is_signed - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 input 19 \mul_op__insn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 output 20 \o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 4 output 21 \cr_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 2 output 22 \xer_ov - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 23 \xer_so - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 24 \ra - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 25 \rb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 1 input 26 \xer_so$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" - wire width 1 input 27 \p_valid_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" - wire width 1 output 28 \p_ready_o - cell \p$88 \p - connect \p_valid_i \p_valid_i - connect \p_ready_o \p_ready_o - end - cell \n$89 \n - connect \n_valid_o \n_valid_o - connect \n_ready_i \n_ready_i - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" - wire width 1 \mul_pipe1_n_valid_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" - wire width 1 \mul_pipe1_n_ready_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \mul_pipe1_muxid - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \mul_pipe1_mul_op__insn_type - attribute \enum_base_type "Function" - attribute \enum_value_00000000000 "NONE" - attribute \enum_value_00000000010 "ALU" - attribute \enum_value_00000000100 "LDST" - attribute \enum_value_00000001000 "SHIFT_ROT" - attribute \enum_value_00000010000 "LOGICAL" - attribute \enum_value_00000100000 "BRANCH" - attribute \enum_value_00001000000 "CR" - attribute \enum_value_00010000000 "TRAP" - attribute \enum_value_00100000000 "MUL" - attribute \enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 \mul_pipe1_mul_op__fn_unit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \mul_pipe1_mul_op__imm_data__data - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \mul_pipe1_mul_op__imm_data__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \mul_pipe1_mul_op__rc__rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \mul_pipe1_mul_op__rc__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \mul_pipe1_mul_op__oe__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \mul_pipe1_mul_op__oe__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \mul_pipe1_mul_op__write_cr0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \mul_pipe1_mul_op__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \mul_pipe1_mul_op__is_signed - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \mul_pipe1_mul_op__insn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \mul_pipe1_ra - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \mul_pipe1_rb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 1 \mul_pipe1_xer_so - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:11" - wire width 1 \mul_pipe1_neg_res - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:12" - wire width 1 \mul_pipe1_neg_res32 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" - wire width 1 \mul_pipe1_p_valid_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" - wire width 1 \mul_pipe1_p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \mul_pipe1_muxid$2 - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \mul_pipe1_mul_op__insn_type$3 - attribute \enum_base_type "Function" - attribute \enum_value_00000000000 "NONE" - attribute \enum_value_00000000010 "ALU" - attribute \enum_value_00000000100 "LDST" - attribute \enum_value_00000001000 "SHIFT_ROT" - attribute \enum_value_00000010000 "LOGICAL" - attribute \enum_value_00000100000 "BRANCH" - attribute \enum_value_00001000000 "CR" - attribute \enum_value_00010000000 "TRAP" - attribute \enum_value_00100000000 "MUL" - attribute \enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 \mul_pipe1_mul_op__fn_unit$4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \mul_pipe1_mul_op__imm_data__data$5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \mul_pipe1_mul_op__imm_data__ok$6 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \mul_pipe1_mul_op__rc__rc$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \mul_pipe1_mul_op__rc__ok$8 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \mul_pipe1_mul_op__oe__oe$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \mul_pipe1_mul_op__oe__ok$10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \mul_pipe1_mul_op__write_cr0$11 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \mul_pipe1_mul_op__is_32bit$12 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \mul_pipe1_mul_op__is_signed$13 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \mul_pipe1_mul_op__insn$14 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \mul_pipe1_ra$15 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \mul_pipe1_rb$16 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 1 \mul_pipe1_xer_so$17 - cell \mul_pipe1 \mul_pipe1 - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \n_valid_o \mul_pipe1_n_valid_o - connect \n_ready_i \mul_pipe1_n_ready_i - connect \muxid \mul_pipe1_muxid - connect \mul_op__insn_type \mul_pipe1_mul_op__insn_type - connect \mul_op__fn_unit \mul_pipe1_mul_op__fn_unit - connect \mul_op__imm_data__data \mul_pipe1_mul_op__imm_data__data - connect \mul_op__imm_data__ok \mul_pipe1_mul_op__imm_data__ok - connect \mul_op__rc__rc \mul_pipe1_mul_op__rc__rc - connect \mul_op__rc__ok \mul_pipe1_mul_op__rc__ok - connect \mul_op__oe__oe \mul_pipe1_mul_op__oe__oe - connect \mul_op__oe__ok \mul_pipe1_mul_op__oe__ok - connect \mul_op__write_cr0 \mul_pipe1_mul_op__write_cr0 - connect \mul_op__is_32bit \mul_pipe1_mul_op__is_32bit - connect \mul_op__is_signed \mul_pipe1_mul_op__is_signed - connect \mul_op__insn \mul_pipe1_mul_op__insn - connect \ra \mul_pipe1_ra - connect \rb \mul_pipe1_rb - connect \xer_so \mul_pipe1_xer_so - connect \neg_res \mul_pipe1_neg_res - connect \neg_res32 \mul_pipe1_neg_res32 - connect \p_valid_i \mul_pipe1_p_valid_i - connect \p_ready_o \mul_pipe1_p_ready_o - connect \muxid$1 \mul_pipe1_muxid$2 - connect \mul_op__insn_type$2 \mul_pipe1_mul_op__insn_type$3 - connect \mul_op__fn_unit$3 \mul_pipe1_mul_op__fn_unit$4 - connect \mul_op__imm_data__data$4 \mul_pipe1_mul_op__imm_data__data$5 - connect \mul_op__imm_data__ok$5 \mul_pipe1_mul_op__imm_data__ok$6 - connect \mul_op__rc__rc$6 \mul_pipe1_mul_op__rc__rc$7 - connect \mul_op__rc__ok$7 \mul_pipe1_mul_op__rc__ok$8 - connect \mul_op__oe__oe$8 \mul_pipe1_mul_op__oe__oe$9 - connect \mul_op__oe__ok$9 \mul_pipe1_mul_op__oe__ok$10 - connect \mul_op__write_cr0$10 \mul_pipe1_mul_op__write_cr0$11 - connect \mul_op__is_32bit$11 \mul_pipe1_mul_op__is_32bit$12 - connect \mul_op__is_signed$12 \mul_pipe1_mul_op__is_signed$13 - connect \mul_op__insn$13 \mul_pipe1_mul_op__insn$14 - connect \ra$14 \mul_pipe1_ra$15 - connect \rb$15 \mul_pipe1_rb$16 - connect \xer_so$16 \mul_pipe1_xer_so$17 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" - wire width 1 \mul_pipe2_p_valid_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" - wire width 1 \mul_pipe2_p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \mul_pipe2_muxid - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \mul_pipe2_mul_op__insn_type - attribute \enum_base_type "Function" - attribute \enum_value_00000000000 "NONE" - attribute \enum_value_00000000010 "ALU" - attribute \enum_value_00000000100 "LDST" - attribute \enum_value_00000001000 "SHIFT_ROT" - attribute \enum_value_00000010000 "LOGICAL" - attribute \enum_value_00000100000 "BRANCH" - attribute \enum_value_00001000000 "CR" - attribute \enum_value_00010000000 "TRAP" - attribute \enum_value_00100000000 "MUL" - attribute \enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 \mul_pipe2_mul_op__fn_unit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \mul_pipe2_mul_op__imm_data__data - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \mul_pipe2_mul_op__imm_data__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \mul_pipe2_mul_op__rc__rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \mul_pipe2_mul_op__rc__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \mul_pipe2_mul_op__oe__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \mul_pipe2_mul_op__oe__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \mul_pipe2_mul_op__write_cr0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \mul_pipe2_mul_op__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \mul_pipe2_mul_op__is_signed - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \mul_pipe2_mul_op__insn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \mul_pipe2_ra - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \mul_pipe2_rb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 1 \mul_pipe2_xer_so - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:11" - wire width 1 \mul_pipe2_neg_res - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:12" - wire width 1 \mul_pipe2_neg_res32 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" - wire width 1 \mul_pipe2_n_valid_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" - wire width 1 \mul_pipe2_n_ready_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \mul_pipe2_muxid$18 - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \mul_pipe2_mul_op__insn_type$19 - attribute \enum_base_type "Function" - attribute \enum_value_00000000000 "NONE" - attribute \enum_value_00000000010 "ALU" - attribute \enum_value_00000000100 "LDST" - attribute \enum_value_00000001000 "SHIFT_ROT" - attribute \enum_value_00000010000 "LOGICAL" - attribute \enum_value_00000100000 "BRANCH" - attribute \enum_value_00001000000 "CR" - attribute \enum_value_00010000000 "TRAP" - attribute \enum_value_00100000000 "MUL" - attribute \enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 \mul_pipe2_mul_op__fn_unit$20 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \mul_pipe2_mul_op__imm_data__data$21 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \mul_pipe2_mul_op__imm_data__ok$22 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \mul_pipe2_mul_op__rc__rc$23 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \mul_pipe2_mul_op__rc__ok$24 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \mul_pipe2_mul_op__oe__oe$25 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \mul_pipe2_mul_op__oe__ok$26 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \mul_pipe2_mul_op__write_cr0$27 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \mul_pipe2_mul_op__is_32bit$28 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \mul_pipe2_mul_op__is_signed$29 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \mul_pipe2_mul_op__insn$30 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 129 \mul_pipe2_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 1 \mul_pipe2_xer_so$31 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:23" - wire width 1 \mul_pipe2_neg_res$32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:24" - wire width 1 \mul_pipe2_neg_res32$33 - cell \mul_pipe2 \mul_pipe2 - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \p_valid_i \mul_pipe2_p_valid_i - connect \p_ready_o \mul_pipe2_p_ready_o - connect \muxid \mul_pipe2_muxid - connect \mul_op__insn_type \mul_pipe2_mul_op__insn_type - connect \mul_op__fn_unit \mul_pipe2_mul_op__fn_unit - connect \mul_op__imm_data__data \mul_pipe2_mul_op__imm_data__data - connect \mul_op__imm_data__ok \mul_pipe2_mul_op__imm_data__ok - connect \mul_op__rc__rc \mul_pipe2_mul_op__rc__rc - connect \mul_op__rc__ok \mul_pipe2_mul_op__rc__ok - connect \mul_op__oe__oe \mul_pipe2_mul_op__oe__oe - connect \mul_op__oe__ok \mul_pipe2_mul_op__oe__ok - connect \mul_op__write_cr0 \mul_pipe2_mul_op__write_cr0 - connect \mul_op__is_32bit \mul_pipe2_mul_op__is_32bit - connect \mul_op__is_signed \mul_pipe2_mul_op__is_signed - connect \mul_op__insn \mul_pipe2_mul_op__insn - connect \ra \mul_pipe2_ra - connect \rb \mul_pipe2_rb - connect \xer_so \mul_pipe2_xer_so - connect \neg_res \mul_pipe2_neg_res - connect \neg_res32 \mul_pipe2_neg_res32 - connect \n_valid_o \mul_pipe2_n_valid_o - connect \n_ready_i \mul_pipe2_n_ready_i - connect \muxid$1 \mul_pipe2_muxid$18 - connect \mul_op__insn_type$2 \mul_pipe2_mul_op__insn_type$19 - connect \mul_op__fn_unit$3 \mul_pipe2_mul_op__fn_unit$20 - connect \mul_op__imm_data__data$4 \mul_pipe2_mul_op__imm_data__data$21 - connect \mul_op__imm_data__ok$5 \mul_pipe2_mul_op__imm_data__ok$22 - connect \mul_op__rc__rc$6 \mul_pipe2_mul_op__rc__rc$23 - connect \mul_op__rc__ok$7 \mul_pipe2_mul_op__rc__ok$24 - connect \mul_op__oe__oe$8 \mul_pipe2_mul_op__oe__oe$25 - connect \mul_op__oe__ok$9 \mul_pipe2_mul_op__oe__ok$26 - connect \mul_op__write_cr0$10 \mul_pipe2_mul_op__write_cr0$27 - connect \mul_op__is_32bit$11 \mul_pipe2_mul_op__is_32bit$28 - connect \mul_op__is_signed$12 \mul_pipe2_mul_op__is_signed$29 - connect \mul_op__insn$13 \mul_pipe2_mul_op__insn$30 - connect \o \mul_pipe2_o - connect \xer_so$14 \mul_pipe2_xer_so$31 - connect \neg_res$15 \mul_pipe2_neg_res$32 - connect \neg_res32$16 \mul_pipe2_neg_res32$33 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" - wire width 1 \mul_pipe3_p_valid_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" - wire width 1 \mul_pipe3_p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \mul_pipe3_muxid - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \mul_pipe3_mul_op__insn_type - attribute \enum_base_type "Function" - attribute \enum_value_00000000000 "NONE" - attribute \enum_value_00000000010 "ALU" - attribute \enum_value_00000000100 "LDST" - attribute \enum_value_00000001000 "SHIFT_ROT" - attribute \enum_value_00000010000 "LOGICAL" - attribute \enum_value_00000100000 "BRANCH" - attribute \enum_value_00001000000 "CR" - attribute \enum_value_00010000000 "TRAP" - attribute \enum_value_00100000000 "MUL" - attribute \enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 \mul_pipe3_mul_op__fn_unit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \mul_pipe3_mul_op__imm_data__data - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \mul_pipe3_mul_op__imm_data__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \mul_pipe3_mul_op__rc__rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \mul_pipe3_mul_op__rc__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \mul_pipe3_mul_op__oe__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \mul_pipe3_mul_op__oe__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \mul_pipe3_mul_op__write_cr0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \mul_pipe3_mul_op__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \mul_pipe3_mul_op__is_signed - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \mul_pipe3_mul_op__insn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 129 \mul_pipe3_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 1 \mul_pipe3_xer_so - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:23" - wire width 1 \mul_pipe3_neg_res - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/mul/pipe_data.py:24" - wire width 1 \mul_pipe3_neg_res32 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" - wire width 1 \mul_pipe3_n_valid_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" - wire width 1 \mul_pipe3_n_ready_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \mul_pipe3_muxid$34 - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \mul_pipe3_mul_op__insn_type$35 - attribute \enum_base_type "Function" - attribute \enum_value_00000000000 "NONE" - attribute \enum_value_00000000010 "ALU" - attribute \enum_value_00000000100 "LDST" - attribute \enum_value_00000001000 "SHIFT_ROT" - attribute \enum_value_00000010000 "LOGICAL" - attribute \enum_value_00000100000 "BRANCH" - attribute \enum_value_00001000000 "CR" - attribute \enum_value_00010000000 "TRAP" - attribute \enum_value_00100000000 "MUL" - attribute \enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 \mul_pipe3_mul_op__fn_unit$36 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \mul_pipe3_mul_op__imm_data__data$37 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \mul_pipe3_mul_op__imm_data__ok$38 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \mul_pipe3_mul_op__rc__rc$39 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \mul_pipe3_mul_op__rc__ok$40 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \mul_pipe3_mul_op__oe__oe$41 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \mul_pipe3_mul_op__oe__ok$42 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \mul_pipe3_mul_op__write_cr0$43 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \mul_pipe3_mul_op__is_32bit$44 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \mul_pipe3_mul_op__is_signed$45 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \mul_pipe3_mul_op__insn$46 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 \mul_pipe3_o$47 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \mul_pipe3_o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 4 \mul_pipe3_cr_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \mul_pipe3_cr_a_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 2 \mul_pipe3_xer_ov - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \mul_pipe3_xer_ov_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \mul_pipe3_xer_so$48 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \mul_pipe3_xer_so_ok - cell \mul_pipe3 \mul_pipe3 - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \p_valid_i \mul_pipe3_p_valid_i - connect \p_ready_o \mul_pipe3_p_ready_o - connect \muxid \mul_pipe3_muxid - connect \mul_op__insn_type \mul_pipe3_mul_op__insn_type - connect \mul_op__fn_unit \mul_pipe3_mul_op__fn_unit - connect \mul_op__imm_data__data \mul_pipe3_mul_op__imm_data__data - connect \mul_op__imm_data__ok \mul_pipe3_mul_op__imm_data__ok - connect \mul_op__rc__rc \mul_pipe3_mul_op__rc__rc - connect \mul_op__rc__ok \mul_pipe3_mul_op__rc__ok - connect \mul_op__oe__oe \mul_pipe3_mul_op__oe__oe - connect \mul_op__oe__ok \mul_pipe3_mul_op__oe__ok - connect \mul_op__write_cr0 \mul_pipe3_mul_op__write_cr0 - connect \mul_op__is_32bit \mul_pipe3_mul_op__is_32bit - connect \mul_op__is_signed \mul_pipe3_mul_op__is_signed - connect \mul_op__insn \mul_pipe3_mul_op__insn - connect \o \mul_pipe3_o - connect \xer_so \mul_pipe3_xer_so - connect \neg_res \mul_pipe3_neg_res - connect \neg_res32 \mul_pipe3_neg_res32 - connect \n_valid_o \mul_pipe3_n_valid_o - connect \n_ready_i \mul_pipe3_n_ready_i - connect \muxid$1 \mul_pipe3_muxid$34 - connect \mul_op__insn_type$2 \mul_pipe3_mul_op__insn_type$35 - connect \mul_op__fn_unit$3 \mul_pipe3_mul_op__fn_unit$36 - connect \mul_op__imm_data__data$4 \mul_pipe3_mul_op__imm_data__data$37 - connect \mul_op__imm_data__ok$5 \mul_pipe3_mul_op__imm_data__ok$38 - connect \mul_op__rc__rc$6 \mul_pipe3_mul_op__rc__rc$39 - connect \mul_op__rc__ok$7 \mul_pipe3_mul_op__rc__ok$40 - connect \mul_op__oe__oe$8 \mul_pipe3_mul_op__oe__oe$41 - connect \mul_op__oe__ok$9 \mul_pipe3_mul_op__oe__ok$42 - connect \mul_op__write_cr0$10 \mul_pipe3_mul_op__write_cr0$43 - connect \mul_op__is_32bit$11 \mul_pipe3_mul_op__is_32bit$44 - connect \mul_op__is_signed$12 \mul_pipe3_mul_op__is_signed$45 - connect \mul_op__insn$13 \mul_pipe3_mul_op__insn$46 - connect \o$14 \mul_pipe3_o$47 - connect \o_ok \mul_pipe3_o_ok - connect \cr_a \mul_pipe3_cr_a - connect \cr_a_ok \mul_pipe3_cr_a_ok - connect \xer_ov \mul_pipe3_xer_ov - connect \xer_ov_ok \mul_pipe3_xer_ov_ok - connect \xer_so$15 \mul_pipe3_xer_so$48 - connect \xer_so_ok \mul_pipe3_xer_so_ok - end - process $group_0 - assign \mul_pipe2_p_valid_i 1'0 - assign \mul_pipe2_p_valid_i \mul_pipe1_n_valid_o - sync init - end - process $group_1 - assign \mul_pipe1_n_ready_i 1'0 - assign \mul_pipe1_n_ready_i \mul_pipe2_p_ready_o - sync init - end - process $group_2 - assign \mul_pipe2_muxid 2'00 - assign \mul_pipe2_muxid \mul_pipe1_muxid - sync init - end - process $group_3 - assign \mul_pipe2_mul_op__insn_type 7'0000000 - assign \mul_pipe2_mul_op__fn_unit 11'00000000000 - assign \mul_pipe2_mul_op__imm_data__data 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \mul_pipe2_mul_op__imm_data__ok 1'0 - assign \mul_pipe2_mul_op__rc__rc 1'0 - assign \mul_pipe2_mul_op__rc__ok 1'0 - assign \mul_pipe2_mul_op__oe__oe 1'0 - assign \mul_pipe2_mul_op__oe__ok 1'0 - assign \mul_pipe2_mul_op__write_cr0 1'0 - assign \mul_pipe2_mul_op__is_32bit 1'0 - assign \mul_pipe2_mul_op__is_signed 1'0 - assign \mul_pipe2_mul_op__insn 32'00000000000000000000000000000000 - assign { \mul_pipe2_mul_op__insn \mul_pipe2_mul_op__is_signed \mul_pipe2_mul_op__is_32bit \mul_pipe2_mul_op__write_cr0 { \mul_pipe2_mul_op__oe__ok \mul_pipe2_mul_op__oe__oe } { \mul_pipe2_mul_op__rc__ok \mul_pipe2_mul_op__rc__rc } { \mul_pipe2_mul_op__imm_data__ok \mul_pipe2_mul_op__imm_data__data } \mul_pipe2_mul_op__fn_unit \mul_pipe2_mul_op__insn_type } { \mul_pipe1_mul_op__insn \mul_pipe1_mul_op__is_signed \mul_pipe1_mul_op__is_32bit \mul_pipe1_mul_op__write_cr0 { \mul_pipe1_mul_op__oe__ok \mul_pipe1_mul_op__oe__oe } { \mul_pipe1_mul_op__rc__ok \mul_pipe1_mul_op__rc__rc } { \mul_pipe1_mul_op__imm_data__ok \mul_pipe1_mul_op__imm_data__data } \mul_pipe1_mul_op__fn_unit \mul_pipe1_mul_op__insn_type } - sync init - end - process $group_15 - assign \mul_pipe2_ra 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \mul_pipe2_ra \mul_pipe1_ra - sync init - end - process $group_16 - assign \mul_pipe2_rb 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \mul_pipe2_rb \mul_pipe1_rb - sync init - end - process $group_17 - assign \mul_pipe2_xer_so 1'0 - assign \mul_pipe2_xer_so \mul_pipe1_xer_so - sync init - end - process $group_18 - assign \mul_pipe2_neg_res 1'0 - assign \mul_pipe2_neg_res \mul_pipe1_neg_res - sync init - end - process $group_19 - assign \mul_pipe2_neg_res32 1'0 - assign \mul_pipe2_neg_res32 \mul_pipe1_neg_res32 - sync init - end - process $group_20 - assign \mul_pipe3_p_valid_i 1'0 - assign \mul_pipe3_p_valid_i \mul_pipe2_n_valid_o - sync init - end - process $group_21 - assign \mul_pipe2_n_ready_i 1'0 - assign \mul_pipe2_n_ready_i \mul_pipe3_p_ready_o - sync init - end - process $group_22 - assign \mul_pipe3_muxid 2'00 - assign \mul_pipe3_muxid \mul_pipe2_muxid$18 - sync init - end - process $group_23 - assign \mul_pipe3_mul_op__insn_type 7'0000000 - assign \mul_pipe3_mul_op__fn_unit 11'00000000000 - assign \mul_pipe3_mul_op__imm_data__data 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \mul_pipe3_mul_op__imm_data__ok 1'0 - assign \mul_pipe3_mul_op__rc__rc 1'0 - assign \mul_pipe3_mul_op__rc__ok 1'0 - assign \mul_pipe3_mul_op__oe__oe 1'0 - assign \mul_pipe3_mul_op__oe__ok 1'0 - assign \mul_pipe3_mul_op__write_cr0 1'0 - assign \mul_pipe3_mul_op__is_32bit 1'0 - assign \mul_pipe3_mul_op__is_signed 1'0 - assign \mul_pipe3_mul_op__insn 32'00000000000000000000000000000000 - assign { \mul_pipe3_mul_op__insn \mul_pipe3_mul_op__is_signed \mul_pipe3_mul_op__is_32bit \mul_pipe3_mul_op__write_cr0 { \mul_pipe3_mul_op__oe__ok \mul_pipe3_mul_op__oe__oe } { \mul_pipe3_mul_op__rc__ok \mul_pipe3_mul_op__rc__rc } { \mul_pipe3_mul_op__imm_data__ok \mul_pipe3_mul_op__imm_data__data } \mul_pipe3_mul_op__fn_unit \mul_pipe3_mul_op__insn_type } { \mul_pipe2_mul_op__insn$30 \mul_pipe2_mul_op__is_signed$29 \mul_pipe2_mul_op__is_32bit$28 \mul_pipe2_mul_op__write_cr0$27 { \mul_pipe2_mul_op__oe__ok$26 \mul_pipe2_mul_op__oe__oe$25 } { \mul_pipe2_mul_op__rc__ok$24 \mul_pipe2_mul_op__rc__rc$23 } { \mul_pipe2_mul_op__imm_data__ok$22 \mul_pipe2_mul_op__imm_data__data$21 } \mul_pipe2_mul_op__fn_unit$20 \mul_pipe2_mul_op__insn_type$19 } - sync init - end - process $group_35 - assign \mul_pipe3_o 129'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \mul_pipe3_o \mul_pipe2_o - sync init - end - process $group_36 - assign \mul_pipe3_xer_so 1'0 - assign \mul_pipe3_xer_so \mul_pipe2_xer_so$31 - sync init - end - process $group_37 - assign \mul_pipe3_neg_res 1'0 - assign \mul_pipe3_neg_res \mul_pipe2_neg_res$32 - sync init - end - process $group_38 - assign \mul_pipe3_neg_res32 1'0 - assign \mul_pipe3_neg_res32 \mul_pipe2_neg_res32$33 - sync init - end - process $group_39 - assign \mul_pipe1_p_valid_i 1'0 - assign \mul_pipe1_p_valid_i \p_valid_i - sync init - end - process $group_40 - assign \p_ready_o 1'0 - assign \p_ready_o \mul_pipe1_p_ready_o - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \muxid - process $group_41 - assign \mul_pipe1_muxid$2 2'00 - assign \mul_pipe1_muxid$2 \muxid - sync init - end - process $group_42 - assign \mul_pipe1_mul_op__insn_type$3 7'0000000 - assign \mul_pipe1_mul_op__fn_unit$4 11'00000000000 - assign \mul_pipe1_mul_op__imm_data__data$5 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \mul_pipe1_mul_op__imm_data__ok$6 1'0 - assign \mul_pipe1_mul_op__rc__rc$7 1'0 - assign \mul_pipe1_mul_op__rc__ok$8 1'0 - assign \mul_pipe1_mul_op__oe__oe$9 1'0 - assign \mul_pipe1_mul_op__oe__ok$10 1'0 - assign \mul_pipe1_mul_op__write_cr0$11 1'0 - assign \mul_pipe1_mul_op__is_32bit$12 1'0 - assign \mul_pipe1_mul_op__is_signed$13 1'0 - assign \mul_pipe1_mul_op__insn$14 32'00000000000000000000000000000000 - assign { \mul_pipe1_mul_op__insn$14 \mul_pipe1_mul_op__is_signed$13 \mul_pipe1_mul_op__is_32bit$12 \mul_pipe1_mul_op__write_cr0$11 { \mul_pipe1_mul_op__oe__ok$10 \mul_pipe1_mul_op__oe__oe$9 } { \mul_pipe1_mul_op__rc__ok$8 \mul_pipe1_mul_op__rc__rc$7 } { \mul_pipe1_mul_op__imm_data__ok$6 \mul_pipe1_mul_op__imm_data__data$5 } \mul_pipe1_mul_op__fn_unit$4 \mul_pipe1_mul_op__insn_type$3 } { \mul_op__insn \mul_op__is_signed \mul_op__is_32bit \mul_op__write_cr0 { \mul_op__oe__ok \mul_op__oe__oe } { \mul_op__rc__ok \mul_op__rc__rc } { \mul_op__imm_data__ok \mul_op__imm_data__data } \mul_op__fn_unit \mul_op__insn_type } - sync init - end - process $group_54 - assign \mul_pipe1_ra$15 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \mul_pipe1_ra$15 \ra - sync init - end - process $group_55 - assign \mul_pipe1_rb$16 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \mul_pipe1_rb$16 \rb - sync init - end - process $group_56 - assign \mul_pipe1_xer_so$17 1'0 - assign \mul_pipe1_xer_so$17 \xer_so$1 - sync init - end - process $group_57 - assign \n_valid_o 1'0 - assign \n_valid_o \mul_pipe3_n_valid_o - sync init - end - process $group_58 - assign \mul_pipe3_n_ready_i 1'0 - assign \mul_pipe3_n_ready_i \n_ready_i - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \muxid$49 - process $group_59 - assign \muxid$49 2'00 - assign \muxid$49 \mul_pipe3_muxid$34 - sync init - end - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \mul_op__insn_type$50 - attribute \enum_base_type "Function" - attribute \enum_value_00000000000 "NONE" - attribute \enum_value_00000000010 "ALU" - attribute \enum_value_00000000100 "LDST" - attribute \enum_value_00000001000 "SHIFT_ROT" - attribute \enum_value_00000010000 "LOGICAL" - attribute \enum_value_00000100000 "BRANCH" - attribute \enum_value_00001000000 "CR" - attribute \enum_value_00010000000 "TRAP" - attribute \enum_value_00100000000 "MUL" - attribute \enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 \mul_op__fn_unit$51 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \mul_op__imm_data__data$52 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \mul_op__imm_data__ok$53 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \mul_op__rc__rc$54 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \mul_op__rc__ok$55 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \mul_op__oe__oe$56 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \mul_op__oe__ok$57 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \mul_op__write_cr0$58 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \mul_op__is_32bit$59 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \mul_op__is_signed$60 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \mul_op__insn$61 - process $group_60 - assign \mul_op__insn_type$50 7'0000000 - assign \mul_op__fn_unit$51 11'00000000000 - assign \mul_op__imm_data__data$52 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \mul_op__imm_data__ok$53 1'0 - assign \mul_op__rc__rc$54 1'0 - assign \mul_op__rc__ok$55 1'0 - assign \mul_op__oe__oe$56 1'0 - assign \mul_op__oe__ok$57 1'0 - assign \mul_op__write_cr0$58 1'0 - assign \mul_op__is_32bit$59 1'0 - assign \mul_op__is_signed$60 1'0 - assign \mul_op__insn$61 32'00000000000000000000000000000000 - assign { \mul_op__insn$61 \mul_op__is_signed$60 \mul_op__is_32bit$59 \mul_op__write_cr0$58 { \mul_op__oe__ok$57 \mul_op__oe__oe$56 } { \mul_op__rc__ok$55 \mul_op__rc__rc$54 } { \mul_op__imm_data__ok$53 \mul_op__imm_data__data$52 } \mul_op__fn_unit$51 \mul_op__insn_type$50 } { \mul_pipe3_mul_op__insn$46 \mul_pipe3_mul_op__is_signed$45 \mul_pipe3_mul_op__is_32bit$44 \mul_pipe3_mul_op__write_cr0$43 { \mul_pipe3_mul_op__oe__ok$42 \mul_pipe3_mul_op__oe__oe$41 } { \mul_pipe3_mul_op__rc__ok$40 \mul_pipe3_mul_op__rc__rc$39 } { \mul_pipe3_mul_op__imm_data__ok$38 \mul_pipe3_mul_op__imm_data__data$37 } \mul_pipe3_mul_op__fn_unit$36 \mul_pipe3_mul_op__insn_type$35 } - sync init - end - process $group_72 - assign \o 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \o_ok 1'0 - assign { \o_ok \o } { \mul_pipe3_o_ok \mul_pipe3_o$47 } - sync init - end - process $group_74 - assign \cr_a 4'0000 - assign \cr_a_ok 1'0 - assign { \cr_a_ok \cr_a } { \mul_pipe3_cr_a_ok \mul_pipe3_cr_a } - sync init - end - process $group_76 - assign \xer_ov 2'00 - assign \xer_ov_ok 1'0 - assign { \xer_ov_ok \xer_ov } { \mul_pipe3_xer_ov_ok \mul_pipe3_xer_ov } - sync init - end - process $group_78 - assign \xer_so 1'0 - assign \xer_so_ok 1'0 - assign { \xer_so_ok \xer_so } { \mul_pipe3_xer_so_ok \mul_pipe3_xer_so$48 } - sync init - end - connect \muxid 2'00 -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.mul0.src_l" -module \src_l$98 - attribute \src "simple/issuer.py:141" - wire width 1 input 0 \coresync_clk - attribute \src "simple/issuer.py:141" - wire width 1 input 1 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 3 input 2 \s_src - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 3 input 3 \r_src - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire width 3 output 4 \q_src - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire width 3 \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire width 3 \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 3 $1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A \r_src - connect \Y $1 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 3 $3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $4 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A \q_int - connect \B $1 - connect \Y $3 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 3 $5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $6 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A $3 - connect \B \s_src - connect \Y $5 - end - process $group_0 - assign \q_int$next \q_int - assign \q_int$next $5 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \q_int$next 3'000 - end - sync init - update \q_int 3'000 - sync posedge \coresync_clk - update \q_int \q_int$next - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 3 $7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $8 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A \r_src - connect \Y $7 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 3 $9 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $10 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A \q_int - connect \B $7 - connect \Y $9 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 3 $11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $12 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A $9 - connect \B \s_src - connect \Y $11 - end - process $group_1 - assign \q_src 3'000 - assign \q_src $11 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" - wire width 3 \qn_src - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - wire width 3 $13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $14 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A \q_src - connect \Y $13 - end - process $group_2 - assign \qn_src 3'000 - assign \qn_src $13 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" - wire width 3 \qlq_src - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - wire width 3 $15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $16 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A \q_src - connect \B \q_int - connect \Y $15 - end - process $group_3 - assign \qlq_src 3'000 - assign \qlq_src $15 - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.mul0.opc_l" -module \opc_l$99 - attribute \src "simple/issuer.py:141" - wire width 1 input 0 \coresync_clk - attribute \src "simple/issuer.py:141" - wire width 1 input 1 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 1 input 2 \s_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 1 input 3 \r_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire width 1 output 4 \q_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire width 1 \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire width 1 \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_opc - connect \Y $1 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 1 $3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $4 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B $1 - connect \Y $3 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 1 $5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $6 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $3 - connect \B \s_opc - connect \Y $5 - end - process $group_0 - assign \q_int$next \q_int - assign \q_int$next $5 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \q_int$next 1'0 - end - sync init - update \q_int 1'0 - sync posedge \coresync_clk - update \q_int \q_int$next - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 1 $7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $8 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_opc - connect \Y $7 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 1 $9 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $10 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B $7 - connect \Y $9 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 1 $11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $12 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $9 - connect \B \s_opc - connect \Y $11 - end - process $group_1 - assign \q_opc 1'0 - assign \q_opc $11 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" - wire width 1 \qn_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - wire width 1 $13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $14 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_opc - connect \Y $13 - end - process $group_2 - assign \qn_opc 1'0 - assign \qn_opc $13 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" - wire width 1 \qlq_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - wire width 1 $15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $16 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_opc - connect \B \q_int - connect \Y $15 - end - process $group_3 - assign \qlq_opc 1'0 - assign \qlq_opc $15 - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.mul0.req_l" -module \req_l$100 - attribute \src "simple/issuer.py:141" - wire width 1 input 0 \coresync_clk - attribute \src "simple/issuer.py:141" - wire width 1 input 1 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire width 4 output 2 \q_req - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 4 input 3 \s_req - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 4 input 4 \r_req - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire width 4 \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire width 4 \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 4 $1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A \r_req - connect \Y $1 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 4 $3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $4 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A \q_int - connect \B $1 - connect \Y $3 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 4 $5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $6 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A $3 - connect \B \s_req - connect \Y $5 - end - process $group_0 - assign \q_int$next \q_int - assign \q_int$next $5 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \q_int$next 4'0000 - end - sync init - update \q_int 4'0000 - sync posedge \coresync_clk - update \q_int \q_int$next - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 4 $7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $8 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A \r_req - connect \Y $7 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 4 $9 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $10 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A \q_int - connect \B $7 - connect \Y $9 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 4 $11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $12 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A $9 - connect \B \s_req - connect \Y $11 - end - process $group_1 - assign \q_req 4'0000 - assign \q_req $11 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" - wire width 4 \qn_req - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - wire width 4 $13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $14 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A \q_req - connect \Y $13 - end - process $group_2 - assign \qn_req 4'0000 - assign \qn_req $13 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" - wire width 4 \qlq_req - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - wire width 4 $15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $16 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A \q_req - connect \B \q_int - connect \Y $15 - end - process $group_3 - assign \qlq_req 4'0000 - assign \qlq_req $15 - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.mul0.rst_l" -module \rst_l$101 - attribute \src "simple/issuer.py:141" - wire width 1 input 0 \coresync_clk - attribute \src "simple/issuer.py:141" - wire width 1 input 1 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 1 input 2 \s_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 1 input 3 \r_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire width 1 \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire width 1 \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_rst - connect \Y $1 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 1 $3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $4 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B $1 - connect \Y $3 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 1 $5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $6 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $3 - connect \B \s_rst - connect \Y $5 - end - process $group_0 - assign \q_int$next \q_int - assign \q_int$next $5 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \q_int$next 1'0 - end - sync init - update \q_int 1'0 - sync posedge \coresync_clk - update \q_int \q_int$next - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire width 1 \q_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 1 $7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $8 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_rst - connect \Y $7 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 1 $9 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $10 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B $7 - connect \Y $9 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 1 $11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $12 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $9 - connect \B \s_rst - connect \Y $11 - end - process $group_1 - assign \q_rst 1'0 - assign \q_rst $11 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" - wire width 1 \qn_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - wire width 1 $13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $14 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_rst - connect \Y $13 - end - process $group_2 - assign \qn_rst 1'0 - assign \qn_rst $13 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" - wire width 1 \qlq_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - wire width 1 $15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $16 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_rst - connect \B \q_int - connect \Y $15 - end - process $group_3 - assign \qlq_rst 1'0 - assign \qlq_rst $15 - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.mul0.rok_l" -module \rok_l$102 - attribute \src "simple/issuer.py:141" - wire width 1 input 0 \coresync_clk - attribute \src "simple/issuer.py:141" - wire width 1 input 1 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire width 1 output 2 \q_rdok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 1 input 3 \s_rdok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 1 input 4 \r_rdok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire width 1 \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire width 1 \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_rdok - connect \Y $1 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 1 $3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $4 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B $1 - connect \Y $3 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 1 $5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $6 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $3 - connect \B \s_rdok - connect \Y $5 - end - process $group_0 - assign \q_int$next \q_int - assign \q_int$next $5 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \q_int$next 1'0 - end - sync init - update \q_int 1'0 - sync posedge \coresync_clk - update \q_int \q_int$next - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 1 $7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $8 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_rdok - connect \Y $7 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 1 $9 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $10 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B $7 - connect \Y $9 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 1 $11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $12 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $9 - connect \B \s_rdok - connect \Y $11 - end - process $group_1 - assign \q_rdok 1'0 - assign \q_rdok $11 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" - wire width 1 \qn_rdok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - wire width 1 $13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $14 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_rdok - connect \Y $13 - end - process $group_2 - assign \qn_rdok 1'0 - assign \qn_rdok $13 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" - wire width 1 \qlq_rdok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - wire width 1 $15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $16 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_rdok - connect \B \q_int - connect \Y $15 - end - process $group_3 - assign \qlq_rdok 1'0 - assign \qlq_rdok $15 - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.mul0.alui_l" -module \alui_l$103 - attribute \src "simple/issuer.py:141" - wire width 1 input 0 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"OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \alu_mul0_mul_op__insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \alu_mul0_mul_op__insn_type$next - attribute \enum_base_type "Function" - attribute \enum_value_00000000000 "NONE" - attribute \enum_value_00000000010 "ALU" - attribute \enum_value_00000000100 "LDST" - attribute \enum_value_00000001000 "SHIFT_ROT" - attribute \enum_value_00000010000 "LOGICAL" - attribute \enum_value_00000100000 "BRANCH" - attribute \enum_value_00001000000 "CR" - attribute \enum_value_00010000000 "TRAP" - attribute \enum_value_00100000000 "MUL" - attribute \enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 \alu_mul0_mul_op__fn_unit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 \alu_mul0_mul_op__fn_unit$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \alu_mul0_mul_op__imm_data__data - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \alu_mul0_mul_op__imm_data__data$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \alu_mul0_mul_op__imm_data__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \alu_mul0_mul_op__imm_data__ok$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \alu_mul0_mul_op__rc__rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \alu_mul0_mul_op__rc__rc$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \alu_mul0_mul_op__rc__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \alu_mul0_mul_op__rc__ok$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \alu_mul0_mul_op__oe__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \alu_mul0_mul_op__oe__oe$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \alu_mul0_mul_op__oe__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \alu_mul0_mul_op__oe__ok$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \alu_mul0_mul_op__write_cr0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \alu_mul0_mul_op__write_cr0$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \alu_mul0_mul_op__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \alu_mul0_mul_op__is_32bit$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \alu_mul0_mul_op__is_signed - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \alu_mul0_mul_op__is_signed$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \alu_mul0_mul_op__insn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \alu_mul0_mul_op__insn$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 \alu_mul0_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 4 \alu_mul0_cr_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 2 \alu_mul0_xer_ov - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \alu_mul0_xer_so - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \alu_mul0_ra - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \alu_mul0_rb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 1 \alu_mul0_xer_so$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" - wire width 1 \alu_mul0_p_valid_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" - wire width 1 \alu_mul0_p_ready_o - cell \alu_mul0 \alu_mul0 - connect \coresync_clk \coresync_clk - connect \o_ok \o_ok - connect \cr_a_ok \cr_a_ok - connect \xer_ov_ok \xer_ov_ok - connect \xer_so_ok \xer_so_ok - connect \coresync_rst \coresync_rst - connect \n_valid_o \alu_mul0_n_valid_o - connect \n_ready_i \alu_mul0_n_ready_i - connect \mul_op__insn_type \alu_mul0_mul_op__insn_type - connect \mul_op__fn_unit \alu_mul0_mul_op__fn_unit - connect \mul_op__imm_data__data \alu_mul0_mul_op__imm_data__data - connect \mul_op__imm_data__ok \alu_mul0_mul_op__imm_data__ok - connect \mul_op__rc__rc \alu_mul0_mul_op__rc__rc - connect \mul_op__rc__ok \alu_mul0_mul_op__rc__ok - connect \mul_op__oe__oe \alu_mul0_mul_op__oe__oe - connect \mul_op__oe__ok \alu_mul0_mul_op__oe__ok - connect \mul_op__write_cr0 \alu_mul0_mul_op__write_cr0 - connect \mul_op__is_32bit \alu_mul0_mul_op__is_32bit - connect \mul_op__is_signed \alu_mul0_mul_op__is_signed - connect \mul_op__insn \alu_mul0_mul_op__insn - connect \o \alu_mul0_o - connect \cr_a \alu_mul0_cr_a - connect \xer_ov \alu_mul0_xer_ov - connect \xer_so \alu_mul0_xer_so - connect \ra \alu_mul0_ra - connect \rb \alu_mul0_rb - connect \xer_so$1 \alu_mul0_xer_so$1 - connect \p_valid_i \alu_mul0_p_valid_i - connect \p_ready_o \alu_mul0_p_ready_o - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 3 \src_l_s_src - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 3 \src_l_s_src$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 3 \src_l_r_src - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 3 \src_l_r_src$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire width 3 \src_l_q_src - cell \src_l$98 \src_l - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \s_src \src_l_s_src - connect \r_src \src_l_r_src - connect \q_src \src_l_q_src - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 1 \opc_l_s_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 1 \opc_l_s_opc$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 1 \opc_l_r_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 1 \opc_l_r_opc$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire width 1 \opc_l_q_opc - cell \opc_l$99 \opc_l - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \s_opc \opc_l_s_opc - connect \r_opc \opc_l_r_opc - connect \q_opc \opc_l_q_opc - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire width 4 \req_l_q_req - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 4 \req_l_s_req - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 4 \req_l_s_req$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 4 \req_l_r_req - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 4 \req_l_r_req$next - cell \req_l$100 \req_l - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \q_req \req_l_q_req - connect \s_req \req_l_s_req - connect \r_req \req_l_r_req - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 1 \rst_l_s_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 1 \rst_l_s_rst$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 1 \rst_l_r_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 1 \rst_l_r_rst$next - cell \rst_l$101 \rst_l - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \s_rst \rst_l_s_rst - connect \r_rst \rst_l_r_rst - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire width 1 \rok_l_q_rdok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 1 \rok_l_s_rdok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 1 \rok_l_s_rdok$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 1 \rok_l_r_rdok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 1 \rok_l_r_rdok$next - cell \rok_l$102 \rok_l - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \q_rdok \rok_l_q_rdok - connect \s_rdok \rok_l_s_rdok - connect \r_rdok \rok_l_r_rdok - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire width 1 \alui_l_q_alui - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 1 \alui_l_r_alui - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 1 \alui_l_r_alui$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 1 \alui_l_s_alui - cell \alui_l$103 \alui_l - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \q_alui \alui_l_q_alui - connect \r_alui \alui_l_r_alui - connect \s_alui \alui_l_s_alui - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire width 1 \alu_l_q_alu - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 1 \alu_l_r_alu - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 1 \alu_l_r_alu$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 1 \alu_l_s_alu - cell \alu_l$104 \alu_l - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \q_alu \alu_l_q_alu - connect \r_alu \alu_l_r_alu - connect \s_alu \alu_l_s_alu - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:187" - wire width 1 \all_rd - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:188" - wire width 1 $2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:188" - cell $and $3 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cu_busy_o - connect \B \rok_l_q_rdok - connect \Y $2 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - wire width 1 $4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - wire width 3 $5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - cell $not $6 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A \cu_rd__rel_o - connect \Y $5 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - wire width 3 $7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - cell $or $8 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A $5 - connect \B \cu_rd__go_i - connect \Y $7 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - cell $reduce_and $9 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A $7 - connect \Y $4 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - wire width 1 $10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - cell $and $11 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $2 - connect \B $4 - connect \Y $10 - end - process $group_0 - assign \all_rd 1'0 - assign \all_rd $10 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire width 1 \all_rd_dly - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire width 1 \all_rd_dly$next - process $group_1 - assign \all_rd_dly$next \all_rd_dly - assign \all_rd_dly$next \all_rd - sync init - update \all_rd_dly 1'0 - sync posedge \coresync_clk - update \all_rd_dly \all_rd_dly$next - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" - wire width 1 \all_rd_rise - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - wire width 1 $12 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $not $13 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \all_rd_dly - connect \Y $12 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - wire width 1 $14 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $and $15 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \all_rd - connect \B $12 - connect \Y $14 - end - process $group_2 - assign \all_rd_rise 1'0 - assign \all_rd_rise $14 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:192" - wire width 1 \all_rd_pulse - process $group_3 - assign \all_rd_pulse 1'0 - assign \all_rd_pulse \all_rd_rise - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:196" - wire width 1 \alu_done - process $group_4 - assign \alu_done 1'0 - assign \alu_done \alu_mul0_n_valid_o - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire width 1 \alu_done_dly - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire width 1 \alu_done_dly$next - process $group_5 - assign \alu_done_dly$next \alu_done_dly - assign \alu_done_dly$next \alu_done - sync init - update \alu_done_dly 1'0 - sync posedge \coresync_clk - update \alu_done_dly \alu_done_dly$next - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" - wire width 1 \alu_done_rise - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - wire width 1 $16 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $not $17 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \alu_done_dly - connect \Y $16 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - wire width 1 $18 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $and $19 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \alu_done - connect \B $16 - connect \Y $18 - end - process $group_6 - assign \alu_done_rise 1'0 - assign \alu_done_rise $18 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:197" - wire width 1 \alu_pulse - process $group_7 - assign \alu_pulse 1'0 - assign \alu_pulse \alu_done_rise - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:198" - wire width 4 \alu_pulsem - process $group_8 - assign \alu_pulsem 4'0000 - assign \alu_pulsem { \alu_pulse \alu_pulse \alu_pulse \alu_pulse } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:204" - wire width 4 \prev_wr_go - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:204" - wire width 4 \prev_wr_go$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:206" - wire width 4 $20 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:206" - cell $and $21 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A \cu_wr__go_i - connect \B { \cu_busy_o \cu_busy_o \cu_busy_o \cu_busy_o } - connect \Y $20 - end - process $group_9 - assign \prev_wr_go$next \prev_wr_go - assign \prev_wr_go$next $20 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \prev_wr_go$next 4'0000 - end - sync init - update \prev_wr_go 4'0000 - sync posedge \coresync_clk - update \prev_wr_go \prev_wr_go$next - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:108" - wire width 1 \cu_done_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - wire width 1 $22 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - wire width 1 $23 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - wire width 4 $24 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:97" - wire width 4 \cu_wrmask_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $not $25 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A \cu_wrmask_o - connect \Y $24 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - wire width 4 $26 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $and $27 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A \cu_wr__rel_o - connect \B $24 - connect \Y $26 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $reduce_bool $28 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A $26 - connect \Y $23 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $not $29 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $23 - connect \Y $22 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - wire width 1 $30 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $and $31 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cu_busy_o - connect \B $22 - connect \Y $30 - end - process $group_10 - assign \cu_done_o 1'0 - assign \cu_done_o $30 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:211" - wire width 1 \wr_any - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" - wire width 1 $32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" - cell $reduce_bool $33 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \cu_wr__go_i - connect \Y $32 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" - wire width 1 $34 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" - cell $reduce_bool $35 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \prev_wr_go - connect \Y $34 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" - wire width 1 $36 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" - cell $or $37 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $32 - connect \B $34 - connect \Y $36 - end - process $group_11 - assign \wr_any 1'0 - assign \wr_any $36 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:212" - wire width 1 \req_done - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" - wire width 1 $38 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" - cell $not $39 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \alu_mul0_n_ready_i - connect \Y $38 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" - wire width 1 $40 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" - cell $and $41 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_any - connect \B $38 - connect \Y $40 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" - wire width 4 $42 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" - cell $and $43 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A \req_l_q_req - connect \B \cu_wrmask_o - connect \Y $42 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" - wire width 1 $44 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" - cell $eq $45 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $42 - connect \B 1'0 - connect \Y $44 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" - wire width 1 $46 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" - cell $and $47 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $40 - connect \B $44 - connect \Y $46 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - wire width 1 $48 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - cell $eq $49 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cu_wrmask_o - connect \B 1'0 - connect \Y $48 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - wire width 1 $50 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - cell $and $51 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $48 - connect \B \alu_mul0_n_ready_i - connect \Y $50 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - wire width 1 $52 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - cell $and $53 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $50 - connect \B \alu_mul0_n_valid_o - connect \Y $52 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - wire width 1 $54 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - cell $and $55 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $52 - connect \B \cu_busy_o - connect \Y $54 - end - process $group_12 - assign \req_done 1'0 - assign \req_done $46 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - switch { $54 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - case 1'1 - assign \req_done 1'1 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:226" - wire width 1 \reset - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:104" - wire width 1 \cu_go_die_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:230" - wire width 1 $56 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:230" - cell $or $57 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \req_done - connect \B \cu_go_die_i - connect \Y $56 - end - process $group_13 - assign \reset 1'0 - assign \reset $56 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:227" - wire width 1 \rst_r - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:231" - wire width 1 $58 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:231" - cell $or $59 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cu_issue_i - connect \B \cu_go_die_i - connect \Y $58 - end - process $group_14 - assign \rst_r 1'0 - assign \rst_r $58 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:228" - wire width 4 \reset_w - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:232" - wire width 4 $60 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:232" - cell $or $61 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A \cu_wr__go_i - connect \B { \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i } - connect \Y $60 - end - process $group_15 - assign \reset_w 4'0000 - assign \reset_w $60 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:229" - wire width 3 \reset_r - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:233" - wire width 3 $62 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:233" - cell $or $63 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A \cu_rd__go_i - connect \B { \cu_go_die_i \cu_go_die_i \cu_go_die_i } - connect \Y $62 - end - process $group_16 - assign \reset_r 3'000 - assign \reset_r $62 - sync init - end - process $group_17 - assign \rok_l_s_rdok$next \rok_l_s_rdok - assign \rok_l_s_rdok$next \cu_issue_i - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \rok_l_s_rdok$next 1'0 - end - sync init - update \rok_l_s_rdok 1'0 - sync posedge \coresync_clk - update \rok_l_s_rdok \rok_l_s_rdok$next - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:237" - wire width 1 $64 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:237" - cell $and $65 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \alu_mul0_n_valid_o - connect \B \cu_busy_o - connect \Y $64 - end - process $group_18 - assign \rok_l_r_rdok$next \rok_l_r_rdok - assign \rok_l_r_rdok$next $64 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \rok_l_r_rdok$next 1'1 - end - sync init - update \rok_l_r_rdok 1'1 - sync posedge \coresync_clk - update \rok_l_r_rdok \rok_l_r_rdok$next - end - process $group_19 - assign \rst_l_s_rst$next \rst_l_s_rst - assign \rst_l_s_rst$next \all_rd - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \rst_l_s_rst$next 1'0 - end - sync init - update \rst_l_s_rst 1'0 - sync posedge \coresync_clk - update \rst_l_s_rst \rst_l_s_rst$next - end - process $group_20 - assign \rst_l_r_rst$next \rst_l_r_rst - assign \rst_l_r_rst$next \rst_r - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \rst_l_r_rst$next 1'1 - end - sync init - update \rst_l_r_rst 1'1 - sync posedge \coresync_clk - update \rst_l_r_rst \rst_l_r_rst$next - end - process $group_21 - assign \opc_l_s_opc$next \opc_l_s_opc - assign \opc_l_s_opc$next \cu_issue_i - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \opc_l_s_opc$next 1'0 - end - sync init - update \opc_l_s_opc 1'0 - sync posedge \coresync_clk - update \opc_l_s_opc \opc_l_s_opc$next - end - process $group_22 - assign \opc_l_r_opc$next \opc_l_r_opc - assign \opc_l_r_opc$next \req_done - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \opc_l_r_opc$next 1'1 - end - sync init - update \opc_l_r_opc 1'1 - sync posedge \coresync_clk - update \opc_l_r_opc \opc_l_r_opc$next - end - process $group_23 - assign \src_l_s_src$next \src_l_s_src - assign \src_l_s_src$next { \cu_issue_i \cu_issue_i \cu_issue_i } - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \src_l_s_src$next 3'000 - end - sync init - update \src_l_s_src 3'000 - sync posedge \coresync_clk - update \src_l_s_src \src_l_s_src$next - end - process $group_24 - assign \src_l_r_src$next \src_l_r_src - assign \src_l_r_src$next \reset_r - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \src_l_r_src$next 3'111 - end - sync init - update \src_l_r_src 3'111 - sync posedge \coresync_clk - update \src_l_r_src \src_l_r_src$next - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:252" - wire width 4 $66 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:252" - cell $and $67 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A \alu_pulsem - connect \B \cu_wrmask_o - connect \Y $66 - end - process $group_25 - assign \req_l_s_req$next \req_l_s_req - assign \req_l_s_req$next $66 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \req_l_s_req$next 4'0000 - end - sync init - update \req_l_s_req 4'0000 - sync posedge \coresync_clk - update \req_l_s_req \req_l_s_req$next - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:253" - wire width 4 $68 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:253" - cell $or $69 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A \reset_w - connect \B \prev_wr_go - connect \Y $68 - end - process $group_26 - assign \req_l_r_req$next \req_l_r_req - assign \req_l_r_req$next $68 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \req_l_r_req$next 4'1111 - end - sync init - update \req_l_r_req 4'1111 - sync posedge \coresync_clk - update \req_l_r_req \req_l_r_req$next - end - process $group_27 - assign \alu_mul0_mul_op__insn_type$next \alu_mul0_mul_op__insn_type - assign \alu_mul0_mul_op__fn_unit$next \alu_mul0_mul_op__fn_unit - assign \alu_mul0_mul_op__imm_data__data$next \alu_mul0_mul_op__imm_data__data - assign \alu_mul0_mul_op__imm_data__ok$next \alu_mul0_mul_op__imm_data__ok - assign \alu_mul0_mul_op__rc__rc$next \alu_mul0_mul_op__rc__rc - assign \alu_mul0_mul_op__rc__ok$next \alu_mul0_mul_op__rc__ok - assign \alu_mul0_mul_op__oe__oe$next \alu_mul0_mul_op__oe__oe - assign \alu_mul0_mul_op__oe__ok$next \alu_mul0_mul_op__oe__ok - assign \alu_mul0_mul_op__write_cr0$next \alu_mul0_mul_op__write_cr0 - assign \alu_mul0_mul_op__is_32bit$next \alu_mul0_mul_op__is_32bit - assign \alu_mul0_mul_op__is_signed$next \alu_mul0_mul_op__is_signed - assign \alu_mul0_mul_op__insn$next \alu_mul0_mul_op__insn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:257" - switch { \cu_issue_i } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:257" - case 1'1 - assign { \alu_mul0_mul_op__insn$next \alu_mul0_mul_op__is_signed$next \alu_mul0_mul_op__is_32bit$next \alu_mul0_mul_op__write_cr0$next { \alu_mul0_mul_op__oe__ok$next \alu_mul0_mul_op__oe__oe$next } { \alu_mul0_mul_op__rc__ok$next \alu_mul0_mul_op__rc__rc$next } { \alu_mul0_mul_op__imm_data__ok$next \alu_mul0_mul_op__imm_data__data$next } \alu_mul0_mul_op__fn_unit$next \alu_mul0_mul_op__insn_type$next } { \oper_i_alu_mul0__insn \oper_i_alu_mul0__is_signed \oper_i_alu_mul0__is_32bit \oper_i_alu_mul0__write_cr0 { \oper_i_alu_mul0__oe__ok \oper_i_alu_mul0__oe__oe } { \oper_i_alu_mul0__rc__ok \oper_i_alu_mul0__rc__rc } { \oper_i_alu_mul0__imm_data__ok \oper_i_alu_mul0__imm_data__data } \oper_i_alu_mul0__fn_unit \oper_i_alu_mul0__insn_type } - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \alu_mul0_mul_op__imm_data__data$next 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \alu_mul0_mul_op__imm_data__ok$next 1'0 - assign \alu_mul0_mul_op__rc__rc$next 1'0 - assign \alu_mul0_mul_op__rc__ok$next 1'0 - assign \alu_mul0_mul_op__oe__oe$next 1'0 - assign \alu_mul0_mul_op__oe__ok$next 1'0 - end - sync init - update \alu_mul0_mul_op__insn_type 7'0000000 - update \alu_mul0_mul_op__fn_unit 11'00000000000 - update \alu_mul0_mul_op__imm_data__data 64'0000000000000000000000000000000000000000000000000000000000000000 - update \alu_mul0_mul_op__imm_data__ok 1'0 - update \alu_mul0_mul_op__rc__rc 1'0 - update \alu_mul0_mul_op__rc__ok 1'0 - update \alu_mul0_mul_op__oe__oe 1'0 - update \alu_mul0_mul_op__oe__ok 1'0 - update \alu_mul0_mul_op__write_cr0 1'0 - update \alu_mul0_mul_op__is_32bit 1'0 - update \alu_mul0_mul_op__is_signed 1'0 - update \alu_mul0_mul_op__insn 32'00000000000000000000000000000000 - sync posedge \coresync_clk - update \alu_mul0_mul_op__insn_type \alu_mul0_mul_op__insn_type$next - update \alu_mul0_mul_op__fn_unit \alu_mul0_mul_op__fn_unit$next - update \alu_mul0_mul_op__imm_data__data \alu_mul0_mul_op__imm_data__data$next - update \alu_mul0_mul_op__imm_data__ok \alu_mul0_mul_op__imm_data__ok$next - update \alu_mul0_mul_op__rc__rc \alu_mul0_mul_op__rc__rc$next - update \alu_mul0_mul_op__rc__ok \alu_mul0_mul_op__rc__ok$next - update \alu_mul0_mul_op__oe__oe \alu_mul0_mul_op__oe__oe$next - update \alu_mul0_mul_op__oe__ok \alu_mul0_mul_op__oe__ok$next - update \alu_mul0_mul_op__write_cr0 \alu_mul0_mul_op__write_cr0$next - update \alu_mul0_mul_op__is_32bit \alu_mul0_mul_op__is_32bit$next - update \alu_mul0_mul_op__is_signed \alu_mul0_mul_op__is_signed$next - update \alu_mul0_mul_op__insn \alu_mul0_mul_op__insn$next - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" - wire width 64 \data_r0__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" - wire width 64 \data_r0__o$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" - wire width 1 \data_r0__o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" - wire width 1 \data_r0__o_ok$next - process $group_39 - assign \data_r0__o$next \data_r0__o - assign \data_r0__o_ok$next \data_r0__o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" - switch { \alu_pulse } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" - case 1'1 - assign { \data_r0__o_ok$next \data_r0__o$next } { \o_ok \alu_mul0_o } - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" - switch { \cu_issue_i } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" - case 1'1 - assign { \data_r0__o_ok$next \data_r0__o$next } 65'00000000000000000000000000000000000000000000000000000000000000000 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \data_r0__o_ok$next 1'0 - end - sync init - update \data_r0__o 64'0000000000000000000000000000000000000000000000000000000000000000 - update \data_r0__o_ok 1'0 - sync posedge \coresync_clk - update \data_r0__o \data_r0__o$next - update \data_r0__o_ok \data_r0__o_ok$next - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" - wire width 4 \data_r1__cr_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" - wire width 4 \data_r1__cr_a$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" - wire width 1 \data_r1__cr_a_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" - wire width 1 \data_r1__cr_a_ok$next - process $group_41 - assign \data_r1__cr_a$next \data_r1__cr_a - assign \data_r1__cr_a_ok$next \data_r1__cr_a_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" - switch { \alu_pulse } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" - case 1'1 - assign { \data_r1__cr_a_ok$next \data_r1__cr_a$next } { \cr_a_ok \alu_mul0_cr_a } - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" - switch { \cu_issue_i } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" - case 1'1 - assign { \data_r1__cr_a_ok$next \data_r1__cr_a$next } 5'00000 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \data_r1__cr_a_ok$next 1'0 - end - sync init - update \data_r1__cr_a 4'0000 - update \data_r1__cr_a_ok 1'0 - sync posedge \coresync_clk - update \data_r1__cr_a \data_r1__cr_a$next - update \data_r1__cr_a_ok \data_r1__cr_a_ok$next - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" - wire width 2 \data_r2__xer_ov - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" - wire width 2 \data_r2__xer_ov$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" - wire width 1 \data_r2__xer_ov_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" - wire width 1 \data_r2__xer_ov_ok$next - process $group_43 - assign \data_r2__xer_ov$next \data_r2__xer_ov - assign \data_r2__xer_ov_ok$next \data_r2__xer_ov_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" - switch { \alu_pulse } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" - case 1'1 - assign { \data_r2__xer_ov_ok$next \data_r2__xer_ov$next } { \xer_ov_ok \alu_mul0_xer_ov } - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" - switch { \cu_issue_i } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" - case 1'1 - assign { \data_r2__xer_ov_ok$next \data_r2__xer_ov$next } 3'000 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \data_r2__xer_ov_ok$next 1'0 - end - sync init - update \data_r2__xer_ov 2'00 - update \data_r2__xer_ov_ok 1'0 - sync posedge \coresync_clk - update \data_r2__xer_ov \data_r2__xer_ov$next - update \data_r2__xer_ov_ok \data_r2__xer_ov_ok$next - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" - wire width 1 \data_r3__xer_so - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" - wire width 1 \data_r3__xer_so$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" - wire width 1 \data_r3__xer_so_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" - wire width 1 \data_r3__xer_so_ok$next - process $group_45 - assign \data_r3__xer_so$next \data_r3__xer_so - assign \data_r3__xer_so_ok$next \data_r3__xer_so_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" - switch { \alu_pulse } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" - case 1'1 - assign { \data_r3__xer_so_ok$next \data_r3__xer_so$next } { \xer_so_ok \alu_mul0_xer_so } - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" - switch { \cu_issue_i } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" - case 1'1 - assign { \data_r3__xer_so_ok$next \data_r3__xer_so$next } 2'00 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \data_r3__xer_so_ok$next 1'0 - end - sync init - update \data_r3__xer_so 1'0 - update \data_r3__xer_so_ok 1'0 - sync posedge \coresync_clk - update \data_r3__xer_so \data_r3__xer_so$next - update \data_r3__xer_so_ok \data_r3__xer_so_ok$next - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" - wire width 1 $70 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" - cell $and $71 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \o_ok - connect \B \cu_busy_o - connect \Y $70 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" - wire width 1 $72 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" - cell $and $73 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cr_a_ok - connect \B \cu_busy_o - connect \Y $72 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" - wire width 1 $74 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" - cell $and $75 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \xer_ov_ok - connect \B \cu_busy_o - connect \Y $74 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" - wire width 1 $76 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" - cell $and $77 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \xer_so_ok - connect \B \cu_busy_o - connect \Y $76 - end - process $group_47 - assign \cu_wrmask_o 4'0000 - assign \cu_wrmask_o { $76 $74 $72 $70 } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:167" - wire width 1 \src_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:168" - wire width 1 $78 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:168" - cell $mux $79 - parameter \WIDTH 1 - connect \A \src_l_q_src [1] - connect \B \opc_l_q_opc - connect \S \alu_mul0_mul_op__imm_data__ok - connect \Y $78 - end - process $group_48 - assign \src_sel 1'0 - assign \src_sel $78 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:166" - wire width 64 \src_or_imm - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:169" - wire width 64 $80 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:169" - cell $mux $81 - parameter \WIDTH 64 - connect \A \src2_i - connect \B \alu_mul0_mul_op__imm_data__data - connect \S \alu_mul0_mul_op__imm_data__ok - connect \Y $80 - end - process $group_49 - assign \src_or_imm 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \src_or_imm $80 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" - wire width 64 \src_r0 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" - wire width 64 \src_r0$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - wire width 64 $82 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - cell $mux $83 - parameter \WIDTH 64 - connect \A \src_r0 - connect \B \src1_i - connect \S \src_l_q_src [0] - connect \Y $82 - end - process $group_50 - assign \alu_mul0_ra 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \alu_mul0_ra $82 - sync init - end - process $group_51 - assign \src_r0$next \src_r0 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" - switch { \src_l_q_src [0] } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" - case 1'1 - assign \src_r0$next \src1_i - end - sync init - update \src_r0 64'0000000000000000000000000000000000000000000000000000000000000000 - sync posedge \coresync_clk - update \src_r0 \src_r0$next - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" - wire width 64 \src_r1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" - wire width 64 \src_r1$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - wire width 64 $84 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - cell $mux $85 - parameter \WIDTH 64 - connect \A \src_r1 - connect \B \src_or_imm - connect \S \src_sel - connect \Y $84 - end - process $group_52 - assign \alu_mul0_rb 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \alu_mul0_rb $84 - sync init - end - process $group_53 - assign \src_r1$next \src_r1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" - switch { \src_sel } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" - case 1'1 - assign \src_r1$next \src_or_imm - end - sync init - update \src_r1 64'0000000000000000000000000000000000000000000000000000000000000000 - sync posedge \coresync_clk - update \src_r1 \src_r1$next - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" - wire width 1 \src_r2 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" - wire width 1 \src_r2$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - wire width 1 $86 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - cell $mux $87 - parameter \WIDTH 1 - connect \A \src_r2 - connect \B \src3_i - connect \S \src_l_q_src [2] - connect \Y $86 - end - process $group_54 - assign \alu_mul0_xer_so$1 1'0 - assign \alu_mul0_xer_so$1 $86 - sync init - end - process $group_55 - assign \src_r2$next \src_r2 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" - switch { \src_l_q_src [2] } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" - case 1'1 - assign \src_r2$next \src3_i - end - sync init - update \src_r2 1'0 - sync posedge \coresync_clk - update \src_r2 \src_r2$next - end - process $group_56 - assign \alu_mul0_p_valid_i 1'0 - assign \alu_mul0_p_valid_i \alui_l_q_alui - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:327" - wire width 1 $88 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:327" - cell $and $89 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \alu_mul0_p_ready_o - connect \B \alui_l_q_alui - connect \Y $88 - end - process $group_57 - assign \alui_l_r_alui$next \alui_l_r_alui - assign \alui_l_r_alui$next $88 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \alui_l_r_alui$next 1'1 - end - sync init - update \alui_l_r_alui 1'1 - sync posedge \coresync_clk - update \alui_l_r_alui \alui_l_r_alui$next - end - process $group_58 - assign \alui_l_s_alui 1'0 - assign \alui_l_s_alui \all_rd_pulse - sync init - end - process $group_59 - assign \alu_mul0_n_ready_i 1'0 - assign \alu_mul0_n_ready_i \alu_l_q_alu - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:334" - wire width 1 $90 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:334" - cell $and $91 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \alu_mul0_n_valid_o - connect \B \alu_l_q_alu - connect \Y $90 - end - process $group_60 - assign \alu_l_r_alu$next \alu_l_r_alu - assign \alu_l_r_alu$next $90 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \alu_l_r_alu$next 1'1 - end - sync init - update \alu_l_r_alu 1'1 - sync posedge \coresync_clk - update \alu_l_r_alu \alu_l_r_alu$next - end - process $group_61 - assign \alu_l_s_alu 1'0 - assign \alu_l_s_alu \all_rd_pulse - sync init - end - process $group_62 - assign \cu_busy_o 1'0 - assign \cu_busy_o \opc_l_q_opc - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - wire width 3 $92 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - cell $and $93 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A \src_l_q_src - connect \B { \cu_busy_o \cu_busy_o \cu_busy_o } - connect \Y $92 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:173" - wire width 1 $94 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:173" - cell $not $95 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \alu_mul0_mul_op__imm_data__ok - connect \Y $94 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - wire width 3 $96 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - cell $and $97 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A $92 - connect \B { 1'1 $94 1'1 } - connect \Y $96 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - wire width 3 $98 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - cell $not $99 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A \cu_rdmaskn_i - connect \Y $98 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - wire width 3 $100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - cell $and $101 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A $96 - connect \B $98 - connect \Y $100 - end - process $group_63 - assign \cu_rd__rel_o 3'000 - assign \cu_rd__rel_o $100 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:102" - wire width 1 \cu_shadown_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" - wire width 1 $102 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" - cell $and $103 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cu_busy_o - connect \B \cu_shadown_i - connect \Y $102 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" - wire width 1 $104 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" - cell $and $105 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cu_busy_o - connect \B \cu_shadown_i - connect \Y $104 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" - wire width 1 $106 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" - cell $and $107 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cu_busy_o - connect \B \cu_shadown_i - connect \Y $106 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" - wire width 1 $108 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" - cell $and $109 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter 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64'0000000000000000000000000000000000000000000000000000000000000000 - assign \a \ra - sync init - end - process $group_1 - assign \ra$18 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \ra$18 \a - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:39" - wire width 64 \b - process $group_2 - assign \b 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \b \rb - sync init - end - process $group_3 - assign \rb$19 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \rb$19 \b - sync init - end - process $group_4 - assign \xer_ca$22 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:55" - switch \sr_op__input_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/common_input_stage.py:56" - attribute \nmigen.decoding "ZERO/0" - case 2'00 - assign \xer_ca$22 2'00 - attribute \src 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assign \sr_op__output_cr$14 1'0 - assign \sr_op__is_32bit$15 1'0 - assign \sr_op__is_signed$16 1'0 - assign \sr_op__insn$17 32'00000000000000000000000000000000 - assign { \sr_op__insn$17 \sr_op__is_signed$16 \sr_op__is_32bit$15 \sr_op__output_cr$14 \sr_op__input_cr$13 \sr_op__output_carry$12 \sr_op__input_carry$11 \sr_op__write_cr0$10 { \sr_op__oe__ok$9 \sr_op__oe__oe$8 } { \sr_op__rc__ok$7 \sr_op__rc__rc$6 } { \sr_op__imm_data__ok$5 \sr_op__imm_data__data$4 } \sr_op__fn_unit$3 \sr_op__insn_type$2 } { \sr_op__insn \sr_op__is_signed \sr_op__is_32bit \sr_op__output_cr \sr_op__input_cr \sr_op__output_carry \sr_op__input_carry \sr_op__write_cr0 { \sr_op__oe__ok \sr_op__oe__oe } { \sr_op__rc__ok \sr_op__rc__rc } { \sr_op__imm_data__ok \sr_op__imm_data__data } \sr_op__fn_unit \sr_op__insn_type } - sync init - end - process $group_23 - assign \rc$20 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \rc$20 \rc - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.shiftrot0.alu_shift_rot0.pipe1.main.rotator.rotl" -module \rotl - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotl.py:8" - wire width 64 input 0 \a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotl.py:9" - wire width 6 input 1 \b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotl.py:11" - wire width 64 output 2 \o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotl.py:19" - wire width 64 $1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotl.py:18" - wire width 8 $2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotl.py:18" - cell $sub $3 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 8 - connect \A 7'1000000 - connect \B \b - connect \Y $2 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotl.py:19" - cell $shift $4 - parameter \A_SIGNED 0 - parameter \A_WIDTH 128 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 64 - connect \A { \a \a } - connect \B $2 - connect \Y $1 - end - process $group_0 - assign \o 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \o $1 - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.shiftrot0.alu_shift_rot0.pipe1.main.rotator.right_mask" -module \right_mask - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:8" - wire width 7 input 0 \shift - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:9" - wire width 64 output 1 \mask - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - cell $gt $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 1'0 - connect \Y $1 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - wire width 1 $3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - cell $gt $4 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 1'1 - connect \Y $3 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - wire width 1 $5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - cell $gt $6 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 2'10 - connect \Y $5 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - wire width 1 $7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - cell $gt $8 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter 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connect \A \shift - connect \B 4'1110 - connect \Y $29 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - wire width 1 $31 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - cell $gt $32 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 4'1111 - connect \Y $31 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - wire width 1 $33 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - cell $gt $34 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 5'10000 - connect \Y $33 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - wire width 1 $35 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - cell $gt $36 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 5'10001 - connect \Y $35 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - wire width 1 $37 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - cell $gt $38 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 5'10010 - connect \Y $37 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - wire width 1 $39 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - cell $gt $40 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 5'10011 - connect \Y $39 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - wire width 1 $41 - attribute \src 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"/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - cell $gt $64 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 5'11111 - connect \Y $63 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - wire width 1 $65 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - cell $gt $66 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 6'100000 - connect \Y $65 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - wire width 1 $67 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - cell $gt $68 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 6'100001 - connect \Y $67 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - wire width 1 $69 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - cell $gt $70 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 6'100010 - connect \Y $69 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - wire width 1 $71 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - cell $gt $72 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 6'100011 - connect \Y $71 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - wire width 1 $73 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - cell $gt $74 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 6'100100 - connect \Y $73 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - wire width 1 $75 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - cell $gt $76 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 6'100101 - connect \Y $75 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - wire width 1 $77 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - cell $gt $78 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 6'100110 - connect \Y $77 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - wire width 1 $79 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - cell $gt $80 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 6'100111 - connect \Y $79 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - wire width 1 $81 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - cell $gt $82 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 6'101000 - connect \Y $81 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - wire width 1 $83 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - cell $gt $84 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 6'101001 - connect \Y $83 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - wire width 1 $85 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - cell $gt $86 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 6'101010 - connect \Y $85 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - wire width 1 $87 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - cell $gt $88 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 6'101011 - connect \Y $87 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - wire width 1 $89 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - cell $gt $90 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 6'101100 - connect \Y $89 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - wire width 1 $91 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - cell $gt $92 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 6'101101 - connect \Y $91 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - wire width 1 $93 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - cell $gt $94 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 6'101110 - connect \Y $93 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - wire width 1 $95 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - cell $gt $96 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 6'101111 - connect \Y $95 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - wire width 1 $97 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - cell $gt $98 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 6'110000 - connect \Y $97 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - wire width 1 $99 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - cell $gt $100 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 6'110001 - connect \Y $99 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - wire width 1 $101 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - cell $gt $102 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 6'110010 - connect \Y $101 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - wire width 1 $103 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - cell $gt $104 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 6'110011 - connect \Y $103 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - wire width 1 $105 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - cell $gt $106 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 6'110100 - connect \Y $105 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - wire width 1 $107 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - cell $gt $108 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 6'110101 - connect \Y $107 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - wire width 1 $109 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - cell $gt $110 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 6'110110 - connect \Y $109 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - wire width 1 $111 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - cell $gt $112 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 6'110111 - connect \Y $111 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - wire width 1 $113 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - cell $gt $114 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 6'111000 - connect \Y $113 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - wire width 1 $115 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - cell $gt $116 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 6'111001 - connect \Y $115 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - wire width 1 $117 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - cell $gt $118 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 6'111010 - connect \Y $117 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - wire width 1 $119 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - cell $gt $120 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 6'111011 - connect \Y $119 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - wire width 1 $121 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - cell $gt $122 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 6'111100 - connect \Y $121 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - wire width 1 $123 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - cell $gt $124 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 6'111101 - connect \Y $123 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - wire width 1 $125 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - cell $gt $126 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 6'111110 - connect \Y $125 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - wire width 1 $127 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - cell $gt $128 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 6'111111 - connect \Y $127 - end - process $group_0 - assign \mask 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - switch { $1 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - case 1'1 - assign \mask [0] 1'1 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - switch { $3 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - case 1'1 - assign \mask [1] 1'1 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - switch { $5 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - case 1'1 - assign \mask [2] 1'1 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - switch { $7 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - case 1'1 - assign \mask [3] 1'1 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - switch { $9 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - case 1'1 - assign \mask [4] 1'1 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - switch { $11 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - case 1'1 - assign \mask [5] 1'1 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - switch { $13 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - case 1'1 - assign \mask [6] 1'1 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - switch { $15 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - case 1'1 - assign \mask [7] 1'1 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - switch { $17 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - case 1'1 - assign \mask [8] 1'1 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - switch { $19 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - case 1'1 - assign \mask [9] 1'1 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - switch { $21 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - case 1'1 - assign \mask [10] 1'1 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - switch { $23 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - case 1'1 - assign \mask [11] 1'1 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - switch { $25 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - case 1'1 - assign \mask [12] 1'1 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - switch { $27 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - case 1'1 - assign \mask [13] 1'1 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - switch { $29 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - case 1'1 - assign \mask [14] 1'1 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - switch { $31 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - case 1'1 - assign \mask [15] 1'1 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - switch { $33 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - case 1'1 - assign \mask [16] 1'1 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - switch { $35 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - case 1'1 - assign \mask [17] 1'1 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - switch { $37 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - case 1'1 - assign \mask [18] 1'1 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - switch { $39 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - case 1'1 - assign \mask [19] 1'1 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - switch { $41 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - case 1'1 - assign \mask [20] 1'1 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - switch { $43 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - case 1'1 - assign \mask [21] 1'1 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - switch { $45 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - case 1'1 - assign \mask [22] 1'1 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - switch { $47 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - case 1'1 - assign \mask [23] 1'1 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - switch { $49 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - case 1'1 - assign \mask [24] 1'1 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - switch { $51 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - case 1'1 - assign \mask [25] 1'1 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - switch { $53 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - case 1'1 - assign \mask [26] 1'1 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - switch { $55 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - case 1'1 - assign \mask [27] 1'1 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - switch { $57 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - case 1'1 - assign \mask [28] 1'1 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - switch { $59 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - case 1'1 - assign \mask [29] 1'1 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - switch { $61 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - case 1'1 - assign \mask [30] 1'1 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - switch { $63 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - case 1'1 - assign \mask [31] 1'1 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - switch { $65 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - case 1'1 - assign \mask [32] 1'1 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - switch { $67 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - case 1'1 - assign \mask [33] 1'1 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - switch { $69 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - case 1'1 - assign \mask [34] 1'1 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - switch { $71 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - case 1'1 - assign \mask [35] 1'1 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - switch { $73 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - case 1'1 - assign \mask [36] 1'1 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - switch { $75 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - case 1'1 - assign \mask [37] 1'1 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - switch { $77 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - case 1'1 - assign \mask [38] 1'1 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - switch { $79 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - case 1'1 - assign \mask [39] 1'1 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - switch { $81 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - case 1'1 - assign \mask [40] 1'1 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - switch { $83 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - case 1'1 - assign \mask [41] 1'1 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - switch { $85 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - case 1'1 - assign \mask [42] 1'1 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - switch { $87 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - case 1'1 - assign \mask [43] 1'1 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - switch { $89 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - case 1'1 - assign \mask [44] 1'1 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - switch { $91 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - case 1'1 - assign \mask [45] 1'1 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - switch { $93 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - case 1'1 - assign \mask [46] 1'1 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - switch { $95 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - case 1'1 - assign \mask [47] 1'1 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - switch { $97 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - case 1'1 - assign \mask [48] 1'1 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - switch { $99 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - case 1'1 - assign \mask [49] 1'1 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - switch { $101 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - case 1'1 - assign \mask [50] 1'1 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - switch { $103 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - case 1'1 - assign \mask [51] 1'1 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - switch { $105 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - case 1'1 - assign \mask [52] 1'1 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - switch { $107 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - case 1'1 - assign \mask [53] 1'1 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - switch { $109 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - case 1'1 - assign \mask [54] 1'1 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - switch { $111 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - case 1'1 - assign \mask [55] 1'1 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - switch { $113 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - case 1'1 - assign \mask [56] 1'1 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - switch { $115 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - case 1'1 - assign \mask [57] 1'1 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - switch { $117 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - case 1'1 - assign \mask [58] 1'1 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - switch { $119 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - case 1'1 - assign \mask [59] 1'1 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - switch { $121 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - case 1'1 - assign \mask [60] 1'1 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - switch { $123 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - case 1'1 - assign \mask [61] 1'1 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - switch { $125 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - case 1'1 - assign \mask [62] 1'1 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - switch { $127 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - case 1'1 - assign \mask [63] 1'1 - end - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.shiftrot0.alu_shift_rot0.pipe1.main.rotator.left_mask" -module \left_mask - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:8" - wire width 7 input 0 \shift - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:9" - wire width 64 output 1 \mask - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - cell $gt $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 1'0 - connect \Y $1 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - wire width 1 $3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - cell $gt $4 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 1'1 - connect \Y $3 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - wire width 1 $5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - cell $gt $6 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 2'10 - connect \Y $5 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - wire width 1 $7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - cell $gt $8 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 2'11 - connect \Y $7 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - wire width 1 $9 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - cell $gt $10 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 3'100 - connect \Y $9 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - wire width 1 $11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - cell $gt $12 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 3'101 - connect \Y $11 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - wire width 1 $13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - cell $gt $14 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 3'110 - connect \Y $13 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - wire width 1 $15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - cell $gt $16 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 3'111 - connect \Y $15 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - wire width 1 $17 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - cell $gt $18 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 4'1000 - connect \Y $17 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - wire width 1 $19 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - cell $gt $20 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 4'1001 - connect \Y $19 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - wire width 1 $21 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - cell $gt $22 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 4'1010 - connect \Y $21 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - wire width 1 $23 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - cell $gt $24 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 4'1011 - connect \Y $23 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - wire width 1 $25 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - cell $gt $26 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 4'1100 - connect \Y $25 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - wire width 1 $27 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - cell $gt $28 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 4'1101 - connect \Y $27 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - wire width 1 $29 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - cell $gt $30 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 4'1110 - connect \Y $29 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - wire width 1 $31 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - cell $gt $32 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 4'1111 - connect \Y $31 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - wire width 1 $33 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - cell $gt $34 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 5'10000 - connect \Y $33 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - wire width 1 $35 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - cell $gt $36 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 5'10001 - connect \Y $35 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - wire width 1 $37 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - cell $gt $38 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 5'10010 - connect \Y $37 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - wire width 1 $39 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - cell $gt $40 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 5'10011 - connect \Y $39 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - wire width 1 $41 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - cell $gt $42 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 5'10100 - connect \Y $41 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - wire width 1 $43 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - cell $gt $44 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 5'10101 - connect \Y $43 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - wire width 1 $45 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - cell $gt $46 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 5'10110 - connect \Y $45 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - wire width 1 $47 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - cell $gt $48 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 5'10111 - connect \Y $47 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - wire width 1 $49 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - cell $gt $50 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 5'11000 - connect \Y $49 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - wire width 1 $51 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - cell $gt $52 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 5'11001 - connect \Y $51 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - wire width 1 $53 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - cell $gt $54 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 5'11010 - connect \Y $53 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - wire width 1 $55 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - cell $gt $56 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 5'11011 - connect \Y $55 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - wire width 1 $57 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - cell $gt $58 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 5'11100 - connect \Y $57 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - wire width 1 $59 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - cell $gt $60 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 5'11101 - connect \Y $59 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - wire width 1 $61 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - cell $gt $62 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 5'11110 - connect \Y $61 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - wire width 1 $63 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - cell $gt $64 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 5'11111 - connect \Y $63 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - wire width 1 $65 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - cell $gt $66 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 6'100000 - connect \Y $65 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - wire width 1 $67 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - cell $gt $68 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 6'100001 - connect \Y $67 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - wire width 1 $69 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - cell $gt $70 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 6'100010 - connect \Y $69 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - wire width 1 $71 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - cell $gt $72 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 6'100011 - connect \Y $71 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - wire width 1 $73 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - cell $gt $74 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 6'100100 - connect \Y $73 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - wire width 1 $75 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - cell $gt $76 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 6'100101 - connect \Y $75 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - wire width 1 $77 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - cell $gt $78 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 6'100110 - connect \Y $77 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - wire width 1 $79 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - cell $gt $80 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 6'100111 - connect \Y $79 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - wire width 1 $81 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - cell $gt $82 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 6'101000 - connect \Y $81 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - wire width 1 $83 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - cell $gt $84 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 6'101001 - connect \Y $83 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - wire width 1 $85 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - cell $gt $86 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 6'101010 - connect \Y $85 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - wire width 1 $87 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - cell $gt $88 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 6'101011 - connect \Y $87 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - wire width 1 $89 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - cell $gt $90 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 6'101100 - connect \Y $89 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - wire width 1 $91 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - cell $gt $92 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 6'101101 - connect \Y $91 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - wire width 1 $93 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - cell $gt $94 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 6'101110 - connect \Y $93 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - wire width 1 $95 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - cell $gt $96 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 6'101111 - connect \Y $95 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - wire width 1 $97 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - cell $gt $98 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 6'110000 - connect \Y $97 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - wire width 1 $99 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - cell $gt $100 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 6'110001 - connect \Y $99 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - wire width 1 $101 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - cell $gt $102 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 6'110010 - connect \Y $101 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - wire width 1 $103 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - cell $gt $104 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 6'110011 - connect \Y $103 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - wire width 1 $105 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - cell $gt $106 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 6'110100 - connect \Y $105 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - wire width 1 $107 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - cell $gt $108 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 6'110101 - connect \Y $107 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - wire width 1 $109 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - cell $gt $110 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 6'110110 - connect \Y $109 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - wire width 1 $111 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - cell $gt $112 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 6'110111 - connect \Y $111 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - wire width 1 $113 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - cell $gt $114 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 6'111000 - connect \Y $113 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - wire width 1 $115 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - cell $gt $116 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 6'111001 - connect \Y $115 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - wire width 1 $117 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - cell $gt $118 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 6'111010 - connect \Y $117 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - wire width 1 $119 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - cell $gt $120 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 6'111011 - connect \Y $119 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - wire width 1 $121 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - cell $gt $122 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 6'111100 - connect \Y $121 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - wire width 1 $123 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - cell $gt $124 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 6'111101 - connect \Y $123 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - wire width 1 $125 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - cell $gt $126 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 6'111110 - connect \Y $125 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - wire width 1 $127 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - cell $gt $128 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 1 - connect \A \shift - connect \B 6'111111 - connect \Y $127 - end - process $group_0 - assign \mask 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - switch { $1 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - case 1'1 - assign \mask [0] 1'1 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - switch { $3 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - case 1'1 - assign \mask [1] 1'1 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - switch { $5 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - case 1'1 - assign \mask [2] 1'1 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - switch { $7 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - case 1'1 - assign \mask [3] 1'1 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - switch { $9 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - case 1'1 - assign \mask [4] 1'1 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - switch { $11 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - case 1'1 - assign \mask [5] 1'1 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - switch { $13 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - case 1'1 - assign \mask [6] 1'1 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - switch { $15 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - case 1'1 - assign \mask [7] 1'1 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - switch { $17 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - case 1'1 - assign \mask [8] 1'1 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - switch { $19 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - case 1'1 - assign \mask [9] 1'1 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - switch { $21 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - case 1'1 - assign \mask [10] 1'1 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - switch { $23 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - case 1'1 - assign \mask [11] 1'1 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - switch { $25 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - case 1'1 - assign \mask [12] 1'1 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - switch { $27 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - case 1'1 - assign \mask [13] 1'1 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - switch { $29 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - case 1'1 - assign \mask [14] 1'1 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - switch { $31 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - case 1'1 - assign \mask [15] 1'1 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - switch { $33 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - case 1'1 - assign \mask [16] 1'1 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - switch { $35 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - case 1'1 - assign \mask [17] 1'1 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - switch { $37 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - case 1'1 - assign \mask [18] 1'1 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - switch { $39 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - case 1'1 - assign \mask [19] 1'1 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - switch { $41 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - case 1'1 - assign \mask [20] 1'1 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - switch { $43 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - case 1'1 - assign \mask [21] 1'1 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - switch { $45 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - case 1'1 - assign \mask [22] 1'1 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - switch { $47 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - case 1'1 - assign \mask [23] 1'1 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - switch { $49 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - case 1'1 - assign \mask [24] 1'1 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - switch { $51 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - case 1'1 - assign \mask [25] 1'1 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - switch { $53 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - case 1'1 - assign \mask [26] 1'1 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - switch { $55 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - case 1'1 - assign \mask [27] 1'1 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - switch { $57 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - case 1'1 - assign \mask [28] 1'1 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - switch { $59 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - case 1'1 - assign \mask [29] 1'1 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - switch { $61 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - case 1'1 - assign \mask [30] 1'1 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - switch { $63 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - case 1'1 - assign \mask [31] 1'1 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - switch { $65 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - case 1'1 - assign \mask [32] 1'1 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - switch { $67 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - case 1'1 - assign \mask [33] 1'1 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - switch { $69 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - case 1'1 - assign \mask [34] 1'1 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - switch { $71 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - case 1'1 - assign \mask [35] 1'1 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - switch { $73 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - case 1'1 - assign \mask [36] 1'1 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - switch { $75 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - case 1'1 - assign \mask [37] 1'1 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - switch { $77 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - case 1'1 - assign \mask [38] 1'1 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - switch { $79 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - case 1'1 - assign \mask [39] 1'1 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - switch { $81 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - case 1'1 - assign \mask [40] 1'1 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - switch { $83 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - case 1'1 - assign \mask [41] 1'1 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - switch { $85 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - case 1'1 - assign \mask [42] 1'1 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - switch { $87 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - case 1'1 - assign \mask [43] 1'1 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - switch { $89 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - case 1'1 - assign \mask [44] 1'1 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - switch { $91 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - case 1'1 - assign \mask [45] 1'1 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - switch { $93 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - case 1'1 - assign \mask [46] 1'1 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - switch { $95 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - case 1'1 - assign \mask [47] 1'1 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - switch { $97 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - case 1'1 - assign \mask [48] 1'1 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - switch { $99 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - case 1'1 - assign \mask [49] 1'1 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - switch { $101 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - case 1'1 - assign \mask [50] 1'1 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - switch { $103 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - case 1'1 - assign \mask [51] 1'1 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - switch { $105 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - case 1'1 - assign \mask [52] 1'1 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - switch { $107 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - case 1'1 - assign \mask [53] 1'1 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - switch { $109 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - case 1'1 - assign \mask [54] 1'1 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - switch { $111 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - case 1'1 - assign \mask [55] 1'1 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - switch { $113 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - case 1'1 - assign \mask [56] 1'1 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - switch { $115 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - case 1'1 - assign \mask [57] 1'1 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - switch { $117 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - case 1'1 - assign \mask [58] 1'1 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - switch { $119 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - case 1'1 - assign \mask [59] 1'1 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - switch { $121 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - case 1'1 - assign \mask [60] 1'1 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - switch { $123 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - case 1'1 - assign \mask [61] 1'1 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - switch { $125 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - case 1'1 - assign \mask [62] 1'1 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - switch { $127 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:15" - case 1'1 - assign \mask [63] 1'1 - end - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.shiftrot0.alu_shift_rot0.pipe1.main.rotator" -module \rotator - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:50" - wire width 5 input 0 \me - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:51" - wire width 5 input 1 \mb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:53" - wire width 1 input 2 \mb_extra - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:55" - wire width 64 input 3 \rs - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:54" - wire width 64 input 4 \ra - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:56" - wire width 7 input 5 \shift - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:57" - wire width 1 input 6 \is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:59" - wire width 1 input 7 \arith - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:58" - wire width 1 input 8 \right_shift - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:60" - wire width 1 input 9 \clear_left - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:61" - wire width 1 input 10 \clear_right - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:62" - wire width 1 input 11 \sign_ext_rs - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:64" - wire width 64 output 12 \result_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:65" - wire width 1 output 13 \carry_out_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotl.py:8" - wire width 64 \rotl_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotl.py:9" - wire width 6 \rotl_b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotl.py:11" - wire width 64 \rotl_o - cell \rotl \rotl - connect \a \rotl_a - connect \b \rotl_b - connect \o \rotl_o - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:8" - wire width 7 \right_mask_shift - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:9" - wire width 64 \right_mask_mask - cell \right_mask \right_mask - connect \shift \right_mask_shift - connect \mask \right_mask_mask - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:8" - wire width 7 \left_mask_shift - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/mask.py:9" - wire width 64 \left_mask_mask - cell \left_mask \left_mask - connect \shift \left_mask_shift - connect \mask \left_mask_mask - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:81" - wire width 32 \hi32 - process $group_0 - assign \hi32 32'00000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:85" - switch { \sign_ext_rs \is_32bit } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:85" - case 2'-1 - assign \hi32 \rs [31:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:87" - case 2'1- - assign \hi32 { \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] \rs [31] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:90" - case - assign \hi32 \rs [63:32] - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:82" - wire width 64 \repl32 - process $group_1 - assign \repl32 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \repl32 { \hi32 \rs [31:0] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:94" - wire width 6 \shift_signed - process $group_2 - assign \shift_signed 6'000000 - assign \shift_signed \shift [5:0] - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:73" - wire width 6 \rot_count - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:99" - wire width 7 $1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:99" - wire width 7 $2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:99" - cell $neg $3 - parameter \A_SIGNED 1 - parameter \A_WIDTH 6 - parameter \Y_WIDTH 7 - connect \A \shift_signed - connect \Y $2 - end - connect $1 $2 - process $group_3 - assign \rot_count 6'000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:98" - switch { \right_shift } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:98" - case 1'1 - assign \rot_count $1 [5:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:100" - case - assign \rot_count \shift [5:0] - end - sync init - end - process $group_4 - assign \rotl_a 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \rotl_a \repl32 - sync init - end - process $group_5 - assign \rotl_b 6'000000 - assign \rotl_b \rot_count - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:74" - wire width 64 \rot - process $group_6 - assign \rot 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \rot \rotl_o - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:75" - wire width 7 \sh - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:110" - wire width 1 $4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:110" - cell $not $5 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \is_32bit - connect \Y $4 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:110" - wire width 1 $6 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:110" - cell $and $7 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \shift [6] - connect \B $4 - connect \Y $6 - end - process $group_7 - assign \sh 7'0000000 - assign \sh { $6 \shift [5:0] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:76" - wire width 7 \mb$8 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:51" - wire width 7 $9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:51" - cell $pos $10 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \Y_WIDTH 7 - connect \A \mb - connect \Y $9 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:126" - wire width 1 $11 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:126" - cell $not $12 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \sh [5] - connect \Y $11 - end - process $group_8 - assign \mb$8 7'0000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:116" - switch { \right_shift \clear_left } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:116" - case 2'-1 - assign \mb$8 $9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:118" - switch { \is_32bit } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:118" - case 1'1 - assign \mb$8 [6:5] 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:120" - case - assign \mb$8 [6:5] { 1'0 \mb_extra } - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:122" - case 2'1- - assign \mb$8 \sh - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:125" - switch { \is_32bit } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:125" - case 1'1 - assign \mb$8 [6:5] { \sh [5] $11 } - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:127" - case - assign \mb$8 { 1'0 \is_32bit 5'00000 } - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:77" - wire width 7 \me$13 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:131" - wire width 1 $14 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:131" - cell $and $15 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \clear_right - connect \B \is_32bit - connect \Y $14 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:134" - wire width 1 $16 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:134" - cell $not $17 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \clear_left - connect \Y $16 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:134" - wire width 1 $18 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:134" - cell $and $19 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \clear_right - connect \B $16 - connect \Y $18 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:139" - wire width 6 $20 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:139" - cell $not $21 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \Y_WIDTH 6 - connect \A \sh [5:0] - connect \Y $20 - end - process $group_9 - assign \me$13 7'0000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:131" - switch { $18 $14 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:131" - case 2'-1 - assign \me$13 { 2'01 \me } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:134" - case 2'1- - assign \me$13 { 1'0 \mb_extra \mb } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:137" - case - assign \me$13 { \sh [6] $20 } - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:143" - wire width 1 $22 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:143" - cell $le $23 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A \mb$8 - connect \B 7'1000000 - connect \Y $22 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:144" - wire width 8 $24 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:144" - wire width 8 $25 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:144" - cell $sub $26 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 8 - connect \A 7'1000000 - connect \B \mb$8 - connect \Y $25 - end - connect $24 $25 - process $group_10 - assign \right_mask_shift 7'0000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:143" - switch { $22 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:143" - case 1'1 - assign \right_mask_shift $24 [6:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:146" - case - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:78" - wire width 64 \mr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:143" - wire width 1 $27 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:143" - cell $le $28 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A \mb$8 - connect \B 7'1000000 - connect \Y $27 - end - process $group_11 - assign \mr 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:143" - switch { $27 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:143" - case 1'1 - assign \mr \right_mask_mask - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:146" - case - assign \mr 64'0000000000000000000000000000000000000000000000000000000000000000 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:151" - wire width 8 $29 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:151" - wire width 8 $30 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:151" - cell $sub $31 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 8 - connect \A 6'111111 - connect \B \me$13 - connect \Y $30 - end - connect $29 $30 - process $group_12 - assign \left_mask_shift 7'0000000 - assign \left_mask_shift $29 [6:0] - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:79" - wire width 64 \ml - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:152" - wire width 64 $32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:152" - cell $not $33 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \Y_WIDTH 64 - connect \A \left_mask_mask - connect \Y $32 - end - process $group_13 - assign \ml 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \ml $32 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:80" - wire width 2 \output_mode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:161" - wire width 1 $34 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:161" - cell $not $35 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \clear_right - connect \Y $34 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:161" - wire width 1 $36 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:161" - cell $and $37 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \clear_left - connect \B $34 - connect \Y $36 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:161" - wire width 1 $38 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:161" - cell $or $39 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $36 - connect \B \right_shift - connect \Y $38 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:162" - wire width 1 $40 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:162" - cell $and $41 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \arith - connect \B \repl32 [63] - connect \Y $40 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:164" - wire width 1 $42 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:164" - cell $gt $43 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 1 - connect \A \mb$8 [5:0] - connect \B \me$13 [5:0] - connect \Y $42 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:164" - wire width 1 $44 - attribute \src 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"/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 29 \sr_op__oe__ok$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 30 \sr_op__write_cr0$10 - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 output 31 \sr_op__input_carry$11 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 32 \sr_op__output_carry$12 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 33 \sr_op__input_cr$13 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 34 \sr_op__output_cr$14 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 35 \sr_op__is_32bit$15 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 36 \sr_op__is_signed$16 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 output 37 \sr_op__insn$17 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 output 38 \o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 39 \o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 40 \xer_so$18 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 2 output 41 \xer_ca - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:50" - wire width 5 \rotator_me - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:51" - wire width 5 \rotator_mb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:53" - wire width 1 \rotator_mb_extra - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:55" - wire width 64 \rotator_rs - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:54" - wire width 64 \rotator_ra - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:56" - wire width 7 \rotator_shift - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:57" - wire width 1 \rotator_is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:59" - wire width 1 \rotator_arith - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:58" - wire width 1 \rotator_right_shift - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:60" - wire width 1 \rotator_clear_left - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:61" - wire width 1 \rotator_clear_right - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:62" - wire width 1 \rotator_sign_ext_rs - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:64" - wire width 64 \rotator_result_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/rotator.py:65" - wire width 1 \rotator_carry_out_o - cell \rotator \rotator - connect \me \rotator_me - connect \mb \rotator_mb - connect \mb_extra \rotator_mb_extra - connect \rs \rotator_rs - connect \ra \rotator_ra - connect \shift \rotator_shift - connect \is_32bit \rotator_is_32bit - connect \arith \rotator_arith - connect \right_shift \rotator_right_shift - connect \clear_left \rotator_clear_left - connect \clear_right \rotator_clear_right - connect \sign_ext_rs \rotator_sign_ext_rs - connect \result_o \rotator_result_o - connect \carry_out_o \rotator_carry_out_o - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/main_stage.py:46" - wire width 5 \mb - process $group_0 - assign \mb 5'00000 - assign \mb { \sr_op__insn [10] \sr_op__insn [9] \sr_op__insn [8] \sr_op__insn [7] \sr_op__insn [6] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/main_stage.py:47" - wire width 5 \me - process $group_1 - assign \me 5'00000 - assign \me { \sr_op__insn [5] \sr_op__insn [4] \sr_op__insn [3] \sr_op__insn [2] \sr_op__insn [1] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/main_stage.py:48" - wire width 1 \mb_extra - process $group_2 - assign \mb_extra 1'0 - assign \mb_extra { \sr_op__insn [10] \sr_op__insn [9] \sr_op__insn [8] \sr_op__insn [7] \sr_op__insn [6] \sr_op__insn [5] } [0] - sync init - end - process $group_3 - assign \rotator_me 5'00000 - assign \rotator_me \me - sync init - end - process $group_4 - assign \rotator_mb 5'00000 - assign \rotator_mb \mb - sync init - end - process $group_5 - assign \rotator_mb_extra 1'0 - assign \rotator_mb_extra \mb_extra - sync init - end - process $group_6 - assign \rotator_rs 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \rotator_rs \rc - sync init - end - process $group_7 - assign \rotator_ra 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \rotator_ra \ra - sync init - end - process $group_8 - assign \rotator_shift 7'0000000 - assign \rotator_shift \rb [6:0] - sync init - end - process $group_9 - assign \rotator_is_32bit 1'0 - assign \rotator_is_32bit \sr_op__is_32bit - sync init - end - process $group_10 - assign \rotator_arith 1'0 - assign \rotator_arith \sr_op__is_signed - sync init - end - process $group_11 - assign \o_ok 1'0 - assign \o_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/main_stage.py:70" - switch \sr_op__insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/main_stage.py:71" - attribute \nmigen.decoding "OP_SHL/60" - case 7'0111100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/main_stage.py:72" - attribute \nmigen.decoding "OP_SHR/61" - case 7'0111101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/main_stage.py:73" - attribute \nmigen.decoding "OP_RLC/56" - case 7'0111000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/main_stage.py:74" - attribute \nmigen.decoding "OP_RLCL/57" - case 7'0111001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/main_stage.py:75" - attribute \nmigen.decoding "OP_RLCR/58" - case 7'0111010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/main_stage.py:76" - attribute \nmigen.decoding "OP_EXTSWSLI/32" - case 7'0100000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/main_stage.py:77" - attribute \nmigen.decoding "" - case - assign \o_ok 1'0 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/main_stage.py:69" - wire width 4 \mode - process $group_12 - assign \mode 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/main_stage.py:70" - switch \sr_op__insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/main_stage.py:71" - attribute \nmigen.decoding "OP_SHL/60" - case 7'0111100 - assign \mode 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/main_stage.py:72" - attribute \nmigen.decoding "OP_SHR/61" - case 7'0111101 - assign \mode 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/main_stage.py:73" - attribute \nmigen.decoding "OP_RLC/56" - case 7'0111000 - assign \mode 4'0110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/main_stage.py:74" - attribute \nmigen.decoding "OP_RLCL/57" - case 7'0111001 - assign \mode 4'0010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/main_stage.py:75" - attribute \nmigen.decoding "OP_RLCR/58" - case 7'0111010 - assign \mode 4'0100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/main_stage.py:76" - attribute \nmigen.decoding "OP_EXTSWSLI/32" - case 7'0100000 - assign \mode 4'1000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/shift_rot/main_stage.py:77" - attribute \nmigen.decoding "" - case - end - sync init - end - process $group_13 - assign \rotator_right_shift 1'0 - assign \rotator_clear_left 1'0 - assign \rotator_clear_right 1'0 - assign \rotator_sign_ext_rs 1'0 - assign { \rotator_sign_ext_rs \rotator_clear_right \rotator_clear_left \rotator_right_shift } \mode - sync init - end - process $group_17 - assign \o 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \o \rotator_result_o - sync init - end - process $group_18 - assign \xer_ca 2'00 - assign \xer_ca { \rotator_carry_out_o \rotator_carry_out_o } - sync init - end - process $group_19 - assign \xer_so$18 1'0 - assign \xer_so$18 \xer_so - sync init - end - process $group_20 - assign \muxid$1 2'00 - assign \muxid$1 \muxid - sync init - end - process $group_21 - assign \sr_op__insn_type$2 7'0000000 - assign \sr_op__fn_unit$3 11'00000000000 - assign \sr_op__imm_data__data$4 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \sr_op__imm_data__ok$5 1'0 - assign \sr_op__rc__rc$6 1'0 - assign \sr_op__rc__ok$7 1'0 - assign \sr_op__oe__oe$8 1'0 - assign \sr_op__oe__ok$9 1'0 - assign \sr_op__write_cr0$10 1'0 - assign \sr_op__input_carry$11 2'00 - assign \sr_op__output_carry$12 1'0 - assign \sr_op__input_cr$13 1'0 - assign \sr_op__output_cr$14 1'0 - assign \sr_op__is_32bit$15 1'0 - assign \sr_op__is_signed$16 1'0 - assign \sr_op__insn$17 32'00000000000000000000000000000000 - assign { \sr_op__insn$17 \sr_op__is_signed$16 \sr_op__is_32bit$15 \sr_op__output_cr$14 \sr_op__input_cr$13 \sr_op__output_carry$12 \sr_op__input_carry$11 \sr_op__write_cr0$10 { \sr_op__oe__ok$9 \sr_op__oe__oe$8 } { \sr_op__rc__ok$7 \sr_op__rc__rc$6 } { \sr_op__imm_data__ok$5 \sr_op__imm_data__data$4 } \sr_op__fn_unit$3 \sr_op__insn_type$2 } { \sr_op__insn \sr_op__is_signed \sr_op__is_32bit \sr_op__output_cr \sr_op__input_cr \sr_op__output_carry \sr_op__input_carry \sr_op__write_cr0 { \sr_op__oe__ok \sr_op__oe__oe } { \sr_op__rc__ok \sr_op__rc__rc } { \sr_op__imm_data__ok \sr_op__imm_data__data } \sr_op__fn_unit \sr_op__insn_type } - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.shiftrot0.alu_shift_rot0.pipe1" -module \pipe1$107 - attribute \src "simple/issuer.py:141" - wire width 1 input 0 \coresync_clk - attribute \src "simple/issuer.py:141" - wire width 1 input 1 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" - wire width 1 output 2 \n_valid_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" - wire width 1 input 3 \n_ready_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 output 4 \muxid - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \muxid$next - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 output 5 \sr_op__insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \sr_op__insn_type$next - attribute \enum_base_type "Function" - attribute \enum_value_00000000000 "NONE" - attribute \enum_value_00000000010 "ALU" - attribute \enum_value_00000000100 "LDST" - attribute \enum_value_00000001000 "SHIFT_ROT" - attribute \enum_value_00000010000 "LOGICAL" - attribute \enum_value_00000100000 "BRANCH" - attribute \enum_value_00001000000 "CR" - attribute \enum_value_00010000000 "TRAP" - attribute \enum_value_00100000000 "MUL" - attribute \enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 output 6 \sr_op__fn_unit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 \sr_op__fn_unit$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 output 7 \sr_op__imm_data__data - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \sr_op__imm_data__data$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 8 \sr_op__imm_data__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \sr_op__imm_data__ok$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 9 \sr_op__rc__rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \sr_op__rc__rc$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 10 \sr_op__rc__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \sr_op__rc__ok$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 11 \sr_op__oe__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \sr_op__oe__oe$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 12 \sr_op__oe__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \sr_op__oe__ok$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 13 \sr_op__write_cr0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \sr_op__write_cr0$next - attribute \enum_base_type "CryIn" - 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connect \o_ok \main_o_ok - connect \xer_so$18 \main_xer_so$59 - connect \xer_ca \main_xer_ca - end - process $group_0 - assign \input_muxid 2'00 - assign \input_muxid \muxid$1 - sync init - end - process $group_1 - assign \input_sr_op__insn_type 7'0000000 - assign \input_sr_op__fn_unit 11'00000000000 - assign \input_sr_op__imm_data__data 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \input_sr_op__imm_data__ok 1'0 - assign \input_sr_op__rc__rc 1'0 - assign \input_sr_op__rc__ok 1'0 - assign \input_sr_op__oe__oe 1'0 - assign \input_sr_op__oe__ok 1'0 - assign \input_sr_op__write_cr0 1'0 - assign \input_sr_op__input_carry 2'00 - assign \input_sr_op__output_carry 1'0 - assign \input_sr_op__input_cr 1'0 - assign \input_sr_op__output_cr 1'0 - assign \input_sr_op__is_32bit 1'0 - assign \input_sr_op__is_signed 1'0 - assign \input_sr_op__insn 32'00000000000000000000000000000000 - assign { \input_sr_op__insn \input_sr_op__is_signed \input_sr_op__is_32bit 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assign \main_ra 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \main_ra \input_ra$37 - sync init - end - process $group_40 - assign \main_rb 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \main_rb \input_rb$38 - sync init - end - process $group_41 - assign \main_rc 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \main_rc \input_rc$39 - sync init - end - process $group_42 - assign \main_xer_so 1'0 - assign \main_xer_so \input_xer_so$40 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 2 \xer_ca$60 - process $group_43 - assign \xer_ca$60 2'00 - assign \xer_ca$60 \input_xer_ca$41 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:621" - wire width 1 \p_valid_i$61 - process $group_44 - assign \p_valid_i$61 1'0 - assign \p_valid_i$61 \p_valid_i - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:619" - wire width 1 \n_i_rdy_data - process $group_45 - assign \n_i_rdy_data 1'0 - assign \n_i_rdy_data \n_ready_i - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:620" - wire width 1 \p_valid_i_p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" - wire width 1 $62 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:624" - cell $and $63 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \p_valid_i$61 - connect \B \p_ready_o - connect \Y $62 - end - process $group_46 - assign \p_valid_i_p_ready_o 1'0 - assign \p_valid_i_p_ready_o $62 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \muxid$64 - process $group_47 - assign \muxid$64 2'00 - assign \muxid$64 \main_muxid$42 - sync init - end - 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attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \sr_op__imm_data__ok$68 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \sr_op__rc__rc$69 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \sr_op__rc__ok$70 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \sr_op__oe__oe$71 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \sr_op__oe__ok$72 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \sr_op__write_cr0$73 - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \sr_op__input_carry$74 - attribute \src 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\main_sr_op__rc__rc$47 } { \main_sr_op__imm_data__ok$46 \main_sr_op__imm_data__data$45 } \main_sr_op__fn_unit$44 \main_sr_op__insn_type$43 } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 \o$81 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \o_ok$82 - process $group_64 - assign \o$81 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \o_ok$82 1'0 - assign { \o_ok$82 \o$81 } { \main_o_ok \main_o } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 4 \cr_a$83 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \cr_a_ok$84 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 4 \cr_a$85 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \cr_a_ok$86 - process $group_66 - assign \cr_a$83 4'0000 - assign \cr_a_ok$84 1'0 - assign { \cr_a_ok$84 \cr_a$83 } { \cr_a_ok$86 \cr_a$85 } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \xer_so$87 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \xer_so_ok$88 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \xer_so_ok$89 - process $group_68 - assign \xer_so$87 1'0 - assign \xer_so_ok$88 1'0 - assign { \xer_so_ok$88 \xer_so$87 } { \xer_so_ok$89 \main_xer_so$59 } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 2 \xer_ca$90 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \xer_ca_ok$91 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \xer_ca_ok$92 - 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\r_busy$next - end - process $group_73 - assign \muxid$next \muxid - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign \muxid$next \muxid$64 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign \muxid$next \muxid$64 - end - sync init - update \muxid 2'00 - sync posedge \coresync_clk - update \muxid \muxid$next - end - process $group_74 - assign \sr_op__insn_type$next \sr_op__insn_type - assign \sr_op__fn_unit$next \sr_op__fn_unit - assign \sr_op__imm_data__data$next \sr_op__imm_data__data - assign \sr_op__imm_data__ok$next \sr_op__imm_data__ok - assign \sr_op__rc__rc$next \sr_op__rc__rc - assign \sr_op__rc__ok$next \sr_op__rc__ok - assign \sr_op__oe__oe$next \sr_op__oe__oe - assign \sr_op__oe__ok$next \sr_op__oe__ok - assign \sr_op__write_cr0$next \sr_op__write_cr0 - assign \sr_op__input_carry$next \sr_op__input_carry - assign \sr_op__output_carry$next \sr_op__output_carry - assign \sr_op__input_cr$next \sr_op__input_cr - assign \sr_op__output_cr$next \sr_op__output_cr - assign \sr_op__is_32bit$next \sr_op__is_32bit - assign \sr_op__is_signed$next \sr_op__is_signed - assign \sr_op__insn$next \sr_op__insn - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign { \sr_op__insn$next \sr_op__is_signed$next \sr_op__is_32bit$next \sr_op__output_cr$next \sr_op__input_cr$next \sr_op__output_carry$next \sr_op__input_carry$next \sr_op__write_cr0$next { \sr_op__oe__ok$next \sr_op__oe__oe$next } { \sr_op__rc__ok$next \sr_op__rc__rc$next } { \sr_op__imm_data__ok$next \sr_op__imm_data__data$next } \sr_op__fn_unit$next \sr_op__insn_type$next } { \sr_op__insn$80 \sr_op__is_signed$79 \sr_op__is_32bit$78 \sr_op__output_cr$77 \sr_op__input_cr$76 \sr_op__output_carry$75 \sr_op__input_carry$74 \sr_op__write_cr0$73 { \sr_op__oe__ok$72 \sr_op__oe__oe$71 } { \sr_op__rc__ok$70 \sr_op__rc__rc$69 } { \sr_op__imm_data__ok$68 \sr_op__imm_data__data$67 } \sr_op__fn_unit$66 \sr_op__insn_type$65 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign { \sr_op__insn$next \sr_op__is_signed$next \sr_op__is_32bit$next \sr_op__output_cr$next \sr_op__input_cr$next \sr_op__output_carry$next \sr_op__input_carry$next \sr_op__write_cr0$next { \sr_op__oe__ok$next \sr_op__oe__oe$next } { \sr_op__rc__ok$next \sr_op__rc__rc$next } { \sr_op__imm_data__ok$next \sr_op__imm_data__data$next } \sr_op__fn_unit$next \sr_op__insn_type$next } { \sr_op__insn$80 \sr_op__is_signed$79 \sr_op__is_32bit$78 \sr_op__output_cr$77 \sr_op__input_cr$76 \sr_op__output_carry$75 \sr_op__input_carry$74 \sr_op__write_cr0$73 { \sr_op__oe__ok$72 \sr_op__oe__oe$71 } { \sr_op__rc__ok$70 \sr_op__rc__rc$69 } { \sr_op__imm_data__ok$68 \sr_op__imm_data__data$67 } \sr_op__fn_unit$66 \sr_op__insn_type$65 } - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \sr_op__imm_data__data$next 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \sr_op__imm_data__ok$next 1'0 - assign \sr_op__rc__rc$next 1'0 - assign \sr_op__rc__ok$next 1'0 - assign \sr_op__oe__oe$next 1'0 - assign \sr_op__oe__ok$next 1'0 - end - sync init - update \sr_op__insn_type 7'0000000 - update \sr_op__fn_unit 11'00000000000 - update \sr_op__imm_data__data 64'0000000000000000000000000000000000000000000000000000000000000000 - update \sr_op__imm_data__ok 1'0 - update \sr_op__rc__rc 1'0 - update \sr_op__rc__ok 1'0 - update \sr_op__oe__oe 1'0 - update \sr_op__oe__ok 1'0 - update \sr_op__write_cr0 1'0 - update \sr_op__input_carry 2'00 - update \sr_op__output_carry 1'0 - update \sr_op__input_cr 1'0 - update \sr_op__output_cr 1'0 - update \sr_op__is_32bit 1'0 - update \sr_op__is_signed 1'0 - update \sr_op__insn 32'00000000000000000000000000000000 - sync posedge \coresync_clk - update \sr_op__insn_type \sr_op__insn_type$next - update \sr_op__fn_unit \sr_op__fn_unit$next - update \sr_op__imm_data__data \sr_op__imm_data__data$next - update \sr_op__imm_data__ok \sr_op__imm_data__ok$next - update \sr_op__rc__rc \sr_op__rc__rc$next - update \sr_op__rc__ok \sr_op__rc__ok$next - update \sr_op__oe__oe \sr_op__oe__oe$next - update \sr_op__oe__ok \sr_op__oe__ok$next - update \sr_op__write_cr0 \sr_op__write_cr0$next - update \sr_op__input_carry \sr_op__input_carry$next - update \sr_op__output_carry \sr_op__output_carry$next - update \sr_op__input_cr \sr_op__input_cr$next - update \sr_op__output_cr \sr_op__output_cr$next - update \sr_op__is_32bit \sr_op__is_32bit$next - update \sr_op__is_signed \sr_op__is_signed$next - update \sr_op__insn \sr_op__insn$next - end - process $group_90 - assign \o$next \o - assign \o_ok$next \o_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign { \o_ok$next \o$next } { \o_ok$82 \o$81 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign { \o_ok$next \o$next } { \o_ok$82 \o$81 } - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \o_ok$next 1'0 - end - sync init - update \o 64'0000000000000000000000000000000000000000000000000000000000000000 - update \o_ok 1'0 - sync posedge \coresync_clk - update \o \o$next - update \o_ok \o_ok$next - end - process $group_92 - assign \cr_a$next \cr_a - assign \cr_a_ok$next \cr_a_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign { \cr_a_ok$next \cr_a$next } { \cr_a_ok$84 \cr_a$83 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign { \cr_a_ok$next \cr_a$next } { \cr_a_ok$84 \cr_a$83 } - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \cr_a_ok$next 1'0 - end - sync init - update \cr_a 4'0000 - update \cr_a_ok 1'0 - sync posedge \coresync_clk - update \cr_a \cr_a$next - update \cr_a_ok \cr_a_ok$next - end - process $group_94 - assign \xer_so$next \xer_so - assign \xer_so_ok$next \xer_so_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign { \xer_so_ok$next \xer_so$next } { \xer_so_ok$88 \xer_so$87 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign { \xer_so_ok$next \xer_so$next } { \xer_so_ok$88 \xer_so$87 } - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \xer_so_ok$next 1'0 - end - sync init - update \xer_so 1'0 - update \xer_so_ok 1'0 - sync posedge \coresync_clk - update \xer_so \xer_so$next - update \xer_so_ok \xer_so_ok$next - end - process $group_96 - assign \xer_ca$next \xer_ca - assign \xer_ca_ok$next \xer_ca_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign { \xer_ca_ok$next \xer_ca$next } { \xer_ca_ok$91 \xer_ca$90 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign { \xer_ca_ok$next \xer_ca$next } { \xer_ca_ok$91 \xer_ca$90 } - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \xer_ca_ok$next 1'0 - end - sync init - update \xer_ca 2'00 - update \xer_ca_ok 1'0 - sync posedge \coresync_clk - update \xer_ca \xer_ca$next - update \xer_ca_ok \xer_ca_ok$next - end - process $group_98 - assign \n_valid_o 1'0 - assign \n_valid_o \r_busy - sync init - end - process $group_99 - assign \p_ready_o 1'0 - assign \p_ready_o \n_i_rdy_data - sync init - end - connect \cr_a$85 4'0000 - connect \cr_a_ok$86 1'0 - connect \xer_so_ok$89 1'0 - connect \xer_ca_ok$92 1'0 -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.shiftrot0.alu_shift_rot0.pipe2.p" -module \p$113 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" - wire width 1 input 0 \p_valid_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" - wire width 1 input 1 \p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:158" - wire width 1 \trigger - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:205" - cell $and $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \p_valid_i - connect \B \p_ready_o - connect \Y $1 - end - process $group_0 - assign \trigger 1'0 - assign \trigger $1 - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.shiftrot0.alu_shift_rot0.pipe2.n" -module \n$114 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" - wire width 1 input 0 \n_valid_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" - wire width 1 input 1 \n_ready_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:251" - wire width 1 \trigger - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:298" - cell $and $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \n_ready_i - connect \B \n_valid_o - connect \Y $1 - end - process $group_0 - assign \trigger 1'0 - assign \trigger $1 - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.shiftrot0.alu_shift_rot0.pipe2.output" -module \output$115 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 input 0 \muxid - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 input 1 \sr_op__insn_type - attribute \enum_base_type "Function" - attribute \enum_value_00000000000 "NONE" - attribute \enum_value_00000000010 "ALU" - attribute \enum_value_00000000100 "LDST" - attribute \enum_value_00000001000 "SHIFT_ROT" - attribute \enum_value_00000010000 "LOGICAL" - attribute \enum_value_00000100000 "BRANCH" - attribute \enum_value_00001000000 "CR" - attribute \enum_value_00010000000 "TRAP" - attribute \enum_value_00100000000 "MUL" - attribute \enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 input 2 \sr_op__fn_unit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 input 3 \sr_op__imm_data__data - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 4 \sr_op__imm_data__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 5 \sr_op__rc__rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 6 \sr_op__rc__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 7 \sr_op__oe__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 8 \sr_op__oe__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 9 \sr_op__write_cr0 - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 input 10 \sr_op__input_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 11 \sr_op__output_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 12 \sr_op__input_cr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 13 \sr_op__output_cr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 14 \sr_op__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 15 \sr_op__is_signed - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 input 16 \sr_op__insn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 input 17 \o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 input 18 \o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 4 input 19 \cr_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 input 20 \xer_so - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 2 input 21 \xer_ca - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 output 22 \muxid$1 - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute 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"/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \sr_op__is_signed$66 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \sr_op__insn$67 - process $group_29 - assign \sr_op__insn_type$52 7'0000000 - assign \sr_op__fn_unit$53 11'00000000000 - assign \sr_op__imm_data__data$54 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \sr_op__imm_data__ok$55 1'0 - assign \sr_op__rc__rc$56 1'0 - assign \sr_op__rc__ok$57 1'0 - assign \sr_op__oe__oe$58 1'0 - assign \sr_op__oe__ok$59 1'0 - assign \sr_op__write_cr0$60 1'0 - assign \sr_op__input_carry$61 2'00 - assign \sr_op__output_carry$62 1'0 - assign \sr_op__input_cr$63 1'0 - assign \sr_op__output_cr$64 1'0 - assign \sr_op__is_32bit$65 1'0 - assign \sr_op__is_signed$66 1'0 - assign \sr_op__insn$67 32'00000000000000000000000000000000 - assign { \sr_op__insn$67 \sr_op__is_signed$66 \sr_op__is_32bit$65 \sr_op__output_cr$64 \sr_op__input_cr$63 \sr_op__output_carry$62 \sr_op__input_carry$61 \sr_op__write_cr0$60 { \sr_op__oe__ok$59 \sr_op__oe__oe$58 } { \sr_op__rc__ok$57 \sr_op__rc__rc$56 } { \sr_op__imm_data__ok$55 \sr_op__imm_data__data$54 } \sr_op__fn_unit$53 \sr_op__insn_type$52 } { \output_sr_op__insn$40 \output_sr_op__is_signed$39 \output_sr_op__is_32bit$38 \output_sr_op__output_cr$37 \output_sr_op__input_cr$36 \output_sr_op__output_carry$35 \output_sr_op__input_carry$34 \output_sr_op__write_cr0$33 { \output_sr_op__oe__ok$32 \output_sr_op__oe__oe$31 } { \output_sr_op__rc__ok$30 \output_sr_op__rc__rc$29 } { \output_sr_op__imm_data__ok$28 \output_sr_op__imm_data__data$27 } \output_sr_op__fn_unit$26 \output_sr_op__insn_type$25 } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 \o$68 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \o_ok$69 - process $group_45 - assign \o$68 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \o_ok$69 1'0 - assign { \o_ok$69 \o$68 } { \output_o_ok$42 \output_o$41 } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 4 \cr_a$70 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \cr_a_ok$71 - process $group_47 - assign \cr_a$70 4'0000 - assign \cr_a_ok$71 1'0 - assign { \cr_a_ok$71 \cr_a$70 } { \output_cr_a_ok \output_cr_a$43 } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 2 \xer_ca$72 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \xer_ca_ok$73 - process $group_49 - assign \xer_ca$72 2'00 - assign \xer_ca_ok$73 1'0 - assign { \xer_ca_ok$73 \xer_ca$72 } { \output_xer_ca_ok \output_xer_ca$44 } - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615" - wire width 1 \r_busy - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:615" - wire width 1 \r_busy$next - process $group_51 - assign \r_busy$next \r_busy - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign \r_busy$next 1'1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign \r_busy$next 1'0 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \r_busy$next 1'0 - end - sync init - update \r_busy 1'0 - sync posedge \coresync_clk - update \r_busy \r_busy$next - end - process $group_52 - assign \muxid$1$next \muxid$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign \muxid$1$next \muxid$51 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign \muxid$1$next \muxid$51 - end - sync init - update \muxid$1 2'00 - sync posedge \coresync_clk - update \muxid$1 \muxid$1$next - end - process $group_53 - assign \sr_op__insn_type$2$next \sr_op__insn_type$2 - assign \sr_op__fn_unit$3$next \sr_op__fn_unit$3 - assign \sr_op__imm_data__data$4$next \sr_op__imm_data__data$4 - assign \sr_op__imm_data__ok$5$next \sr_op__imm_data__ok$5 - assign \sr_op__rc__rc$6$next \sr_op__rc__rc$6 - assign \sr_op__rc__ok$7$next \sr_op__rc__ok$7 - assign \sr_op__oe__oe$8$next \sr_op__oe__oe$8 - assign \sr_op__oe__ok$9$next \sr_op__oe__ok$9 - assign \sr_op__write_cr0$10$next \sr_op__write_cr0$10 - assign \sr_op__input_carry$11$next \sr_op__input_carry$11 - assign \sr_op__output_carry$12$next \sr_op__output_carry$12 - assign \sr_op__input_cr$13$next \sr_op__input_cr$13 - assign \sr_op__output_cr$14$next \sr_op__output_cr$14 - assign \sr_op__is_32bit$15$next \sr_op__is_32bit$15 - assign \sr_op__is_signed$16$next \sr_op__is_signed$16 - assign \sr_op__insn$17$next \sr_op__insn$17 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign { \sr_op__insn$17$next \sr_op__is_signed$16$next \sr_op__is_32bit$15$next \sr_op__output_cr$14$next \sr_op__input_cr$13$next \sr_op__output_carry$12$next \sr_op__input_carry$11$next \sr_op__write_cr0$10$next { \sr_op__oe__ok$9$next \sr_op__oe__oe$8$next } { \sr_op__rc__ok$7$next \sr_op__rc__rc$6$next } { \sr_op__imm_data__ok$5$next \sr_op__imm_data__data$4$next } \sr_op__fn_unit$3$next \sr_op__insn_type$2$next } { \sr_op__insn$67 \sr_op__is_signed$66 \sr_op__is_32bit$65 \sr_op__output_cr$64 \sr_op__input_cr$63 \sr_op__output_carry$62 \sr_op__input_carry$61 \sr_op__write_cr0$60 { \sr_op__oe__ok$59 \sr_op__oe__oe$58 } { \sr_op__rc__ok$57 \sr_op__rc__rc$56 } { \sr_op__imm_data__ok$55 \sr_op__imm_data__data$54 } \sr_op__fn_unit$53 \sr_op__insn_type$52 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign { \sr_op__insn$17$next \sr_op__is_signed$16$next \sr_op__is_32bit$15$next \sr_op__output_cr$14$next \sr_op__input_cr$13$next \sr_op__output_carry$12$next \sr_op__input_carry$11$next \sr_op__write_cr0$10$next { \sr_op__oe__ok$9$next \sr_op__oe__oe$8$next } { \sr_op__rc__ok$7$next \sr_op__rc__rc$6$next } { \sr_op__imm_data__ok$5$next \sr_op__imm_data__data$4$next } \sr_op__fn_unit$3$next \sr_op__insn_type$2$next } { \sr_op__insn$67 \sr_op__is_signed$66 \sr_op__is_32bit$65 \sr_op__output_cr$64 \sr_op__input_cr$63 \sr_op__output_carry$62 \sr_op__input_carry$61 \sr_op__write_cr0$60 { \sr_op__oe__ok$59 \sr_op__oe__oe$58 } { \sr_op__rc__ok$57 \sr_op__rc__rc$56 } { \sr_op__imm_data__ok$55 \sr_op__imm_data__data$54 } \sr_op__fn_unit$53 \sr_op__insn_type$52 } - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \sr_op__imm_data__data$4$next 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \sr_op__imm_data__ok$5$next 1'0 - assign \sr_op__rc__rc$6$next 1'0 - assign \sr_op__rc__ok$7$next 1'0 - assign \sr_op__oe__oe$8$next 1'0 - assign \sr_op__oe__ok$9$next 1'0 - end - sync init - update \sr_op__insn_type$2 7'0000000 - update \sr_op__fn_unit$3 11'00000000000 - update \sr_op__imm_data__data$4 64'0000000000000000000000000000000000000000000000000000000000000000 - update \sr_op__imm_data__ok$5 1'0 - update \sr_op__rc__rc$6 1'0 - update \sr_op__rc__ok$7 1'0 - update \sr_op__oe__oe$8 1'0 - update \sr_op__oe__ok$9 1'0 - update \sr_op__write_cr0$10 1'0 - update \sr_op__input_carry$11 2'00 - update \sr_op__output_carry$12 1'0 - update \sr_op__input_cr$13 1'0 - update \sr_op__output_cr$14 1'0 - update \sr_op__is_32bit$15 1'0 - update \sr_op__is_signed$16 1'0 - update \sr_op__insn$17 32'00000000000000000000000000000000 - sync posedge \coresync_clk - update \sr_op__insn_type$2 \sr_op__insn_type$2$next - update \sr_op__fn_unit$3 \sr_op__fn_unit$3$next - update \sr_op__imm_data__data$4 \sr_op__imm_data__data$4$next - update \sr_op__imm_data__ok$5 \sr_op__imm_data__ok$5$next - update \sr_op__rc__rc$6 \sr_op__rc__rc$6$next - update \sr_op__rc__ok$7 \sr_op__rc__ok$7$next - update \sr_op__oe__oe$8 \sr_op__oe__oe$8$next - update \sr_op__oe__ok$9 \sr_op__oe__ok$9$next - update \sr_op__write_cr0$10 \sr_op__write_cr0$10$next - update \sr_op__input_carry$11 \sr_op__input_carry$11$next - update \sr_op__output_carry$12 \sr_op__output_carry$12$next - update \sr_op__input_cr$13 \sr_op__input_cr$13$next - update \sr_op__output_cr$14 \sr_op__output_cr$14$next - update \sr_op__is_32bit$15 \sr_op__is_32bit$15$next - update \sr_op__is_signed$16 \sr_op__is_signed$16$next - update \sr_op__insn$17 \sr_op__insn$17$next - end - process $group_69 - assign \o$18$next \o$18 - assign \o_ok$19$next \o_ok$19 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign { \o_ok$19$next \o$18$next } { \o_ok$69 \o$68 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign { \o_ok$19$next \o$18$next } { \o_ok$69 \o$68 } - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \o_ok$19$next 1'0 - end - sync init - update \o$18 64'0000000000000000000000000000000000000000000000000000000000000000 - update \o_ok$19 1'0 - sync posedge \coresync_clk - update \o$18 \o$18$next - update \o_ok$19 \o_ok$19$next - end - process $group_71 - assign \cr_a$20$next \cr_a$20 - assign \cr_a_ok$21$next \cr_a_ok$21 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign { \cr_a_ok$21$next \cr_a$20$next } { \cr_a_ok$71 \cr_a$70 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign { \cr_a_ok$21$next \cr_a$20$next } { \cr_a_ok$71 \cr_a$70 } - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \cr_a_ok$21$next 1'0 - end - sync init - update \cr_a$20 4'0000 - update \cr_a_ok$21 1'0 - sync posedge \coresync_clk - update \cr_a$20 \cr_a$20$next - update \cr_a_ok$21 \cr_a_ok$21$next - end - process $group_73 - assign \xer_ca$22$next \xer_ca$22 - assign \xer_ca_ok$23$next \xer_ca_ok$23 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - switch { \n_i_rdy_data \p_valid_i_p_ready_o } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:631" - case 2'-1 - assign { \xer_ca_ok$23$next \xer_ca$22$next } { \xer_ca_ok$73 \xer_ca$72 } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/singlepipe.py:637" - case 2'1- - assign { \xer_ca_ok$23$next \xer_ca$22$next } { \xer_ca_ok$73 \xer_ca$72 } - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \xer_ca_ok$23$next 1'0 - end - sync init - update \xer_ca$22 2'00 - update \xer_ca_ok$23 1'0 - sync posedge \coresync_clk - update \xer_ca$22 \xer_ca$22$next - update \xer_ca_ok$23 \xer_ca_ok$23$next - end - process $group_75 - assign \n_valid_o 1'0 - assign \n_valid_o \r_busy - sync init - end - process $group_76 - assign \p_ready_o 1'0 - assign \p_ready_o \n_i_rdy_data - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.shiftrot0.alu_shift_rot0" -module \alu_shift_rot0 - attribute \src "simple/issuer.py:141" - wire width 1 input 0 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 1 \o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 2 \cr_a_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 3 \xer_ca_ok - attribute \src "simple/issuer.py:141" - wire width 1 input 4 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" - wire width 1 output 5 \n_valid_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" - wire width 1 input 6 \n_ready_i - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 input 7 \sr_op__insn_type - attribute \enum_base_type "Function" - attribute \enum_value_00000000000 "NONE" - attribute \enum_value_00000000010 "ALU" - attribute \enum_value_00000000100 "LDST" - attribute \enum_value_00000001000 "SHIFT_ROT" - attribute \enum_value_00000010000 "LOGICAL" - attribute \enum_value_00000100000 "BRANCH" - attribute \enum_value_00001000000 "CR" - attribute \enum_value_00010000000 "TRAP" - attribute \enum_value_00100000000 "MUL" - attribute \enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 input 8 \sr_op__fn_unit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 input 9 \sr_op__imm_data__data - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 10 \sr_op__imm_data__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 11 \sr_op__rc__rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 12 \sr_op__rc__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 13 \sr_op__oe__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 14 \sr_op__oe__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 15 \sr_op__write_cr0 - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 input 16 \sr_op__input_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 17 \sr_op__output_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 18 \sr_op__input_cr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 19 \sr_op__output_cr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 20 \sr_op__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 21 \sr_op__is_signed - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 input 22 \sr_op__insn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 output 23 \o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 4 output 24 \cr_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 2 output 25 \xer_ca - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 26 \ra - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 27 \rb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 input 28 \rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 1 input 29 \xer_so - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 2 input 30 \xer_ca$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" - wire width 1 input 31 \p_valid_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" - wire width 1 output 32 \p_ready_o - cell \p$105 \p - connect \p_valid_i \p_valid_i - connect \p_ready_o \p_ready_o - end - cell \n$106 \n - connect \n_valid_o \n_valid_o - connect \n_ready_i \n_ready_i - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" - wire width 1 \pipe1_n_valid_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" - wire width 1 \pipe1_n_ready_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \pipe1_muxid - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \pipe1_sr_op__insn_type - attribute \enum_base_type "Function" - attribute \enum_value_00000000000 "NONE" - attribute \enum_value_00000000010 "ALU" - attribute \enum_value_00000000100 "LDST" - attribute \enum_value_00000001000 "SHIFT_ROT" - attribute \enum_value_00000010000 "LOGICAL" - attribute \enum_value_00000100000 "BRANCH" - attribute \enum_value_00001000000 "CR" - attribute \enum_value_00010000000 "TRAP" - attribute \enum_value_00100000000 "MUL" - attribute \enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 \pipe1_sr_op__fn_unit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \pipe1_sr_op__imm_data__data - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe1_sr_op__imm_data__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe1_sr_op__rc__rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe1_sr_op__rc__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe1_sr_op__oe__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe1_sr_op__oe__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe1_sr_op__write_cr0 - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \pipe1_sr_op__input_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe1_sr_op__output_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe1_sr_op__input_cr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe1_sr_op__output_cr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe1_sr_op__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe1_sr_op__is_signed - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \pipe1_sr_op__insn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 \pipe1_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \pipe1_o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 4 \pipe1_cr_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \pipe1_cr_a_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \pipe1_xer_so - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \pipe1_xer_so_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 2 \pipe1_xer_ca - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \pipe1_xer_ca_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" - wire width 1 \pipe1_p_valid_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" - wire width 1 \pipe1_p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \pipe1_muxid$2 - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \pipe1_sr_op__insn_type$3 - attribute \enum_base_type "Function" - attribute \enum_value_00000000000 "NONE" - attribute \enum_value_00000000010 "ALU" - attribute \enum_value_00000000100 "LDST" - attribute \enum_value_00000001000 "SHIFT_ROT" - attribute \enum_value_00000010000 "LOGICAL" - attribute \enum_value_00000100000 "BRANCH" - attribute \enum_value_00001000000 "CR" - attribute \enum_value_00010000000 "TRAP" - attribute \enum_value_00100000000 "MUL" - attribute \enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 \pipe1_sr_op__fn_unit$4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \pipe1_sr_op__imm_data__data$5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe1_sr_op__imm_data__ok$6 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe1_sr_op__rc__rc$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe1_sr_op__rc__ok$8 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe1_sr_op__oe__oe$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe1_sr_op__oe__ok$10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe1_sr_op__write_cr0$11 - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \pipe1_sr_op__input_carry$12 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe1_sr_op__output_carry$13 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe1_sr_op__input_cr$14 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe1_sr_op__output_cr$15 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe1_sr_op__is_32bit$16 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe1_sr_op__is_signed$17 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \pipe1_sr_op__insn$18 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \pipe1_ra - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \pipe1_rb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \pipe1_rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 1 \pipe1_xer_so$19 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 2 \pipe1_xer_ca$20 - cell \pipe1$107 \pipe1 - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \n_valid_o \pipe1_n_valid_o - connect \n_ready_i \pipe1_n_ready_i - connect \muxid \pipe1_muxid - connect \sr_op__insn_type \pipe1_sr_op__insn_type - connect \sr_op__fn_unit \pipe1_sr_op__fn_unit - connect \sr_op__imm_data__data \pipe1_sr_op__imm_data__data - connect \sr_op__imm_data__ok \pipe1_sr_op__imm_data__ok - connect \sr_op__rc__rc \pipe1_sr_op__rc__rc - connect \sr_op__rc__ok \pipe1_sr_op__rc__ok - connect \sr_op__oe__oe \pipe1_sr_op__oe__oe - connect \sr_op__oe__ok \pipe1_sr_op__oe__ok - connect \sr_op__write_cr0 \pipe1_sr_op__write_cr0 - connect \sr_op__input_carry \pipe1_sr_op__input_carry - connect \sr_op__output_carry \pipe1_sr_op__output_carry - connect \sr_op__input_cr \pipe1_sr_op__input_cr - connect \sr_op__output_cr \pipe1_sr_op__output_cr - connect \sr_op__is_32bit \pipe1_sr_op__is_32bit - connect \sr_op__is_signed \pipe1_sr_op__is_signed - connect \sr_op__insn \pipe1_sr_op__insn - connect \o \pipe1_o - connect \o_ok \pipe1_o_ok - connect \cr_a \pipe1_cr_a - connect \cr_a_ok \pipe1_cr_a_ok - connect \xer_so \pipe1_xer_so - connect \xer_so_ok \pipe1_xer_so_ok - connect \xer_ca \pipe1_xer_ca - connect \xer_ca_ok \pipe1_xer_ca_ok - connect \p_valid_i \pipe1_p_valid_i - connect \p_ready_o \pipe1_p_ready_o - connect \muxid$1 \pipe1_muxid$2 - connect \sr_op__insn_type$2 \pipe1_sr_op__insn_type$3 - connect \sr_op__fn_unit$3 \pipe1_sr_op__fn_unit$4 - connect \sr_op__imm_data__data$4 \pipe1_sr_op__imm_data__data$5 - connect \sr_op__imm_data__ok$5 \pipe1_sr_op__imm_data__ok$6 - connect \sr_op__rc__rc$6 \pipe1_sr_op__rc__rc$7 - connect \sr_op__rc__ok$7 \pipe1_sr_op__rc__ok$8 - connect \sr_op__oe__oe$8 \pipe1_sr_op__oe__oe$9 - connect \sr_op__oe__ok$9 \pipe1_sr_op__oe__ok$10 - connect \sr_op__write_cr0$10 \pipe1_sr_op__write_cr0$11 - connect \sr_op__input_carry$11 \pipe1_sr_op__input_carry$12 - connect \sr_op__output_carry$12 \pipe1_sr_op__output_carry$13 - connect \sr_op__input_cr$13 \pipe1_sr_op__input_cr$14 - connect \sr_op__output_cr$14 \pipe1_sr_op__output_cr$15 - connect \sr_op__is_32bit$15 \pipe1_sr_op__is_32bit$16 - connect \sr_op__is_signed$16 \pipe1_sr_op__is_signed$17 - connect \sr_op__insn$17 \pipe1_sr_op__insn$18 - connect \ra \pipe1_ra - connect \rb \pipe1_rb - connect \rc \pipe1_rc - connect \xer_so$18 \pipe1_xer_so$19 - connect \xer_ca$19 \pipe1_xer_ca$20 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" - wire width 1 \pipe2_p_valid_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" - wire width 1 \pipe2_p_ready_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \pipe2_muxid - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \pipe2_sr_op__insn_type - attribute \enum_base_type "Function" - attribute \enum_value_00000000000 "NONE" - attribute \enum_value_00000000010 "ALU" - attribute \enum_value_00000000100 "LDST" - attribute \enum_value_00000001000 "SHIFT_ROT" - attribute \enum_value_00000010000 "LOGICAL" - attribute \enum_value_00000100000 "BRANCH" - attribute \enum_value_00001000000 "CR" - attribute \enum_value_00010000000 "TRAP" - attribute \enum_value_00100000000 "MUL" - attribute \enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 \pipe2_sr_op__fn_unit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \pipe2_sr_op__imm_data__data - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe2_sr_op__imm_data__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe2_sr_op__rc__rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe2_sr_op__rc__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe2_sr_op__oe__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe2_sr_op__oe__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe2_sr_op__write_cr0 - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \pipe2_sr_op__input_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe2_sr_op__output_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe2_sr_op__input_cr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe2_sr_op__output_cr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe2_sr_op__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe2_sr_op__is_signed - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \pipe2_sr_op__insn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 \pipe2_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \pipe2_o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 4 \pipe2_cr_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \pipe2_cr_a_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \pipe2_xer_so - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \pipe2_xer_so_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 2 \pipe2_xer_ca - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \pipe2_xer_ca_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" - wire width 1 \pipe2_n_valid_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" - wire width 1 \pipe2_n_ready_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \pipe2_muxid$21 - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \pipe2_sr_op__insn_type$22 - attribute \enum_base_type "Function" - attribute \enum_value_00000000000 "NONE" - attribute \enum_value_00000000010 "ALU" - attribute \enum_value_00000000100 "LDST" - attribute \enum_value_00000001000 "SHIFT_ROT" - attribute \enum_value_00000010000 "LOGICAL" - attribute \enum_value_00000100000 "BRANCH" - attribute \enum_value_00001000000 "CR" - attribute \enum_value_00010000000 "TRAP" - attribute \enum_value_00100000000 "MUL" - attribute \enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 \pipe2_sr_op__fn_unit$23 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \pipe2_sr_op__imm_data__data$24 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe2_sr_op__imm_data__ok$25 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe2_sr_op__rc__rc$26 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe2_sr_op__rc__ok$27 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe2_sr_op__oe__oe$28 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe2_sr_op__oe__ok$29 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe2_sr_op__write_cr0$30 - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \pipe2_sr_op__input_carry$31 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe2_sr_op__output_carry$32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe2_sr_op__input_cr$33 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe2_sr_op__output_cr$34 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe2_sr_op__is_32bit$35 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \pipe2_sr_op__is_signed$36 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \pipe2_sr_op__insn$37 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 \pipe2_o$38 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \pipe2_o_ok$39 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 4 \pipe2_cr_a$40 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \pipe2_cr_a_ok$41 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 2 \pipe2_xer_ca$42 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \pipe2_xer_ca_ok$43 - cell \pipe2$112 \pipe2 - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \p_valid_i \pipe2_p_valid_i - connect \p_ready_o \pipe2_p_ready_o - connect \muxid \pipe2_muxid - connect \sr_op__insn_type \pipe2_sr_op__insn_type - connect \sr_op__fn_unit \pipe2_sr_op__fn_unit - connect \sr_op__imm_data__data \pipe2_sr_op__imm_data__data - connect \sr_op__imm_data__ok \pipe2_sr_op__imm_data__ok - connect \sr_op__rc__rc \pipe2_sr_op__rc__rc - connect \sr_op__rc__ok \pipe2_sr_op__rc__ok - connect \sr_op__oe__oe \pipe2_sr_op__oe__oe - connect \sr_op__oe__ok \pipe2_sr_op__oe__ok - connect \sr_op__write_cr0 \pipe2_sr_op__write_cr0 - connect \sr_op__input_carry \pipe2_sr_op__input_carry - connect \sr_op__output_carry \pipe2_sr_op__output_carry - connect \sr_op__input_cr \pipe2_sr_op__input_cr - connect \sr_op__output_cr \pipe2_sr_op__output_cr - connect \sr_op__is_32bit \pipe2_sr_op__is_32bit - connect \sr_op__is_signed \pipe2_sr_op__is_signed - connect \sr_op__insn \pipe2_sr_op__insn - connect \o \pipe2_o - connect \o_ok \pipe2_o_ok - connect \cr_a \pipe2_cr_a - connect \cr_a_ok \pipe2_cr_a_ok - connect \xer_so \pipe2_xer_so - connect \xer_so_ok \pipe2_xer_so_ok - connect \xer_ca \pipe2_xer_ca - connect \xer_ca_ok \pipe2_xer_ca_ok - connect \n_valid_o \pipe2_n_valid_o - connect \n_ready_i \pipe2_n_ready_i - connect \muxid$1 \pipe2_muxid$21 - connect \sr_op__insn_type$2 \pipe2_sr_op__insn_type$22 - connect \sr_op__fn_unit$3 \pipe2_sr_op__fn_unit$23 - connect \sr_op__imm_data__data$4 \pipe2_sr_op__imm_data__data$24 - connect \sr_op__imm_data__ok$5 \pipe2_sr_op__imm_data__ok$25 - connect \sr_op__rc__rc$6 \pipe2_sr_op__rc__rc$26 - connect \sr_op__rc__ok$7 \pipe2_sr_op__rc__ok$27 - connect \sr_op__oe__oe$8 \pipe2_sr_op__oe__oe$28 - connect \sr_op__oe__ok$9 \pipe2_sr_op__oe__ok$29 - connect \sr_op__write_cr0$10 \pipe2_sr_op__write_cr0$30 - connect \sr_op__input_carry$11 \pipe2_sr_op__input_carry$31 - connect \sr_op__output_carry$12 \pipe2_sr_op__output_carry$32 - connect \sr_op__input_cr$13 \pipe2_sr_op__input_cr$33 - connect \sr_op__output_cr$14 \pipe2_sr_op__output_cr$34 - connect \sr_op__is_32bit$15 \pipe2_sr_op__is_32bit$35 - connect \sr_op__is_signed$16 \pipe2_sr_op__is_signed$36 - connect \sr_op__insn$17 \pipe2_sr_op__insn$37 - connect \o$18 \pipe2_o$38 - connect \o_ok$19 \pipe2_o_ok$39 - connect \cr_a$20 \pipe2_cr_a$40 - connect \cr_a_ok$21 \pipe2_cr_a_ok$41 - connect \xer_ca$22 \pipe2_xer_ca$42 - connect \xer_ca_ok$23 \pipe2_xer_ca_ok$43 - end - process $group_0 - assign \pipe2_p_valid_i 1'0 - assign \pipe2_p_valid_i \pipe1_n_valid_o - sync init - end - process $group_1 - assign \pipe1_n_ready_i 1'0 - assign \pipe1_n_ready_i \pipe2_p_ready_o - sync init - end - process $group_2 - assign \pipe2_muxid 2'00 - assign \pipe2_muxid \pipe1_muxid - sync init - end - process $group_3 - assign \pipe2_sr_op__insn_type 7'0000000 - assign \pipe2_sr_op__fn_unit 11'00000000000 - assign \pipe2_sr_op__imm_data__data 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \pipe2_sr_op__imm_data__ok 1'0 - assign \pipe2_sr_op__rc__rc 1'0 - assign \pipe2_sr_op__rc__ok 1'0 - assign \pipe2_sr_op__oe__oe 1'0 - assign \pipe2_sr_op__oe__ok 1'0 - assign \pipe2_sr_op__write_cr0 1'0 - assign \pipe2_sr_op__input_carry 2'00 - assign \pipe2_sr_op__output_carry 1'0 - assign \pipe2_sr_op__input_cr 1'0 - assign \pipe2_sr_op__output_cr 1'0 - assign \pipe2_sr_op__is_32bit 1'0 - assign \pipe2_sr_op__is_signed 1'0 - assign \pipe2_sr_op__insn 32'00000000000000000000000000000000 - assign { \pipe2_sr_op__insn \pipe2_sr_op__is_signed \pipe2_sr_op__is_32bit \pipe2_sr_op__output_cr \pipe2_sr_op__input_cr \pipe2_sr_op__output_carry \pipe2_sr_op__input_carry \pipe2_sr_op__write_cr0 { \pipe2_sr_op__oe__ok \pipe2_sr_op__oe__oe } { \pipe2_sr_op__rc__ok \pipe2_sr_op__rc__rc } { \pipe2_sr_op__imm_data__ok \pipe2_sr_op__imm_data__data } \pipe2_sr_op__fn_unit \pipe2_sr_op__insn_type } { \pipe1_sr_op__insn \pipe1_sr_op__is_signed \pipe1_sr_op__is_32bit \pipe1_sr_op__output_cr \pipe1_sr_op__input_cr \pipe1_sr_op__output_carry \pipe1_sr_op__input_carry \pipe1_sr_op__write_cr0 { \pipe1_sr_op__oe__ok \pipe1_sr_op__oe__oe } { \pipe1_sr_op__rc__ok \pipe1_sr_op__rc__rc } { \pipe1_sr_op__imm_data__ok \pipe1_sr_op__imm_data__data } \pipe1_sr_op__fn_unit \pipe1_sr_op__insn_type } - sync init - end - process $group_19 - assign \pipe2_o 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \pipe2_o_ok 1'0 - assign { \pipe2_o_ok \pipe2_o } { \pipe1_o_ok \pipe1_o } - sync init - end - process $group_21 - assign \pipe2_cr_a 4'0000 - assign \pipe2_cr_a_ok 1'0 - assign { \pipe2_cr_a_ok \pipe2_cr_a } { \pipe1_cr_a_ok \pipe1_cr_a } - sync init - end - process $group_23 - assign \pipe2_xer_so 1'0 - assign \pipe2_xer_so_ok 1'0 - assign { \pipe2_xer_so_ok \pipe2_xer_so } { \pipe1_xer_so_ok \pipe1_xer_so } - sync init - end - process $group_25 - assign \pipe2_xer_ca 2'00 - assign \pipe2_xer_ca_ok 1'0 - assign { \pipe2_xer_ca_ok \pipe2_xer_ca } { \pipe1_xer_ca_ok \pipe1_xer_ca } - sync init - end - process $group_27 - assign \pipe1_p_valid_i 1'0 - assign \pipe1_p_valid_i \p_valid_i - sync init - end - process $group_28 - assign \p_ready_o 1'0 - assign \p_ready_o \pipe1_p_ready_o - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \muxid - process $group_29 - assign \pipe1_muxid$2 2'00 - assign \pipe1_muxid$2 \muxid - sync init - end - process $group_30 - assign \pipe1_sr_op__insn_type$3 7'0000000 - assign \pipe1_sr_op__fn_unit$4 11'00000000000 - assign \pipe1_sr_op__imm_data__data$5 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \pipe1_sr_op__imm_data__ok$6 1'0 - assign \pipe1_sr_op__rc__rc$7 1'0 - assign \pipe1_sr_op__rc__ok$8 1'0 - assign \pipe1_sr_op__oe__oe$9 1'0 - assign \pipe1_sr_op__oe__ok$10 1'0 - assign \pipe1_sr_op__write_cr0$11 1'0 - assign \pipe1_sr_op__input_carry$12 2'00 - assign \pipe1_sr_op__output_carry$13 1'0 - assign \pipe1_sr_op__input_cr$14 1'0 - assign \pipe1_sr_op__output_cr$15 1'0 - assign \pipe1_sr_op__is_32bit$16 1'0 - assign \pipe1_sr_op__is_signed$17 1'0 - assign \pipe1_sr_op__insn$18 32'00000000000000000000000000000000 - assign { \pipe1_sr_op__insn$18 \pipe1_sr_op__is_signed$17 \pipe1_sr_op__is_32bit$16 \pipe1_sr_op__output_cr$15 \pipe1_sr_op__input_cr$14 \pipe1_sr_op__output_carry$13 \pipe1_sr_op__input_carry$12 \pipe1_sr_op__write_cr0$11 { \pipe1_sr_op__oe__ok$10 \pipe1_sr_op__oe__oe$9 } { \pipe1_sr_op__rc__ok$8 \pipe1_sr_op__rc__rc$7 } { \pipe1_sr_op__imm_data__ok$6 \pipe1_sr_op__imm_data__data$5 } \pipe1_sr_op__fn_unit$4 \pipe1_sr_op__insn_type$3 } { \sr_op__insn \sr_op__is_signed \sr_op__is_32bit \sr_op__output_cr \sr_op__input_cr \sr_op__output_carry \sr_op__input_carry \sr_op__write_cr0 { \sr_op__oe__ok \sr_op__oe__oe } { \sr_op__rc__ok \sr_op__rc__rc } { \sr_op__imm_data__ok \sr_op__imm_data__data } \sr_op__fn_unit \sr_op__insn_type } - sync init - end - process $group_46 - assign \pipe1_ra 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \pipe1_ra \ra - sync init - end - process $group_47 - assign \pipe1_rb 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \pipe1_rb \rb - sync init - end - process $group_48 - assign \pipe1_rc 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \pipe1_rc \rc - sync init - end - process $group_49 - assign \pipe1_xer_so$19 1'0 - assign \pipe1_xer_so$19 \xer_so - sync init - end - process $group_50 - assign \pipe1_xer_ca$20 2'00 - assign \pipe1_xer_ca$20 \xer_ca$1 - sync init - end - process $group_51 - assign \n_valid_o 1'0 - assign \n_valid_o \pipe2_n_valid_o - sync init - end - process $group_52 - assign \pipe2_n_ready_i 1'0 - assign \pipe2_n_ready_i \n_ready_i - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/concurrentunit.py:35" - wire width 2 \muxid$44 - process $group_53 - assign \muxid$44 2'00 - assign \muxid$44 \pipe2_muxid$21 - sync init - end - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \sr_op__insn_type$45 - attribute \enum_base_type "Function" - attribute \enum_value_00000000000 "NONE" - attribute \enum_value_00000000010 "ALU" - attribute \enum_value_00000000100 "LDST" - attribute \enum_value_00000001000 "SHIFT_ROT" - attribute \enum_value_00000010000 "LOGICAL" - attribute \enum_value_00000100000 "BRANCH" - attribute \enum_value_00001000000 "CR" - attribute \enum_value_00010000000 "TRAP" - attribute \enum_value_00100000000 "MUL" - attribute \enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 \sr_op__fn_unit$46 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \sr_op__imm_data__data$47 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \sr_op__imm_data__ok$48 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \sr_op__rc__rc$49 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \sr_op__rc__ok$50 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \sr_op__oe__oe$51 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \sr_op__oe__ok$52 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \sr_op__write_cr0$53 - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \sr_op__input_carry$54 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \sr_op__output_carry$55 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \sr_op__input_cr$56 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \sr_op__output_cr$57 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \sr_op__is_32bit$58 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \sr_op__is_signed$59 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \sr_op__insn$60 - process $group_54 - assign \sr_op__insn_type$45 7'0000000 - assign \sr_op__fn_unit$46 11'00000000000 - assign \sr_op__imm_data__data$47 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \sr_op__imm_data__ok$48 1'0 - assign \sr_op__rc__rc$49 1'0 - assign \sr_op__rc__ok$50 1'0 - assign \sr_op__oe__oe$51 1'0 - assign \sr_op__oe__ok$52 1'0 - assign \sr_op__write_cr0$53 1'0 - assign \sr_op__input_carry$54 2'00 - assign \sr_op__output_carry$55 1'0 - assign \sr_op__input_cr$56 1'0 - assign \sr_op__output_cr$57 1'0 - assign \sr_op__is_32bit$58 1'0 - assign \sr_op__is_signed$59 1'0 - assign \sr_op__insn$60 32'00000000000000000000000000000000 - assign { \sr_op__insn$60 \sr_op__is_signed$59 \sr_op__is_32bit$58 \sr_op__output_cr$57 \sr_op__input_cr$56 \sr_op__output_carry$55 \sr_op__input_carry$54 \sr_op__write_cr0$53 { \sr_op__oe__ok$52 \sr_op__oe__oe$51 } { \sr_op__rc__ok$50 \sr_op__rc__rc$49 } { \sr_op__imm_data__ok$48 \sr_op__imm_data__data$47 } \sr_op__fn_unit$46 \sr_op__insn_type$45 } { \pipe2_sr_op__insn$37 \pipe2_sr_op__is_signed$36 \pipe2_sr_op__is_32bit$35 \pipe2_sr_op__output_cr$34 \pipe2_sr_op__input_cr$33 \pipe2_sr_op__output_carry$32 \pipe2_sr_op__input_carry$31 \pipe2_sr_op__write_cr0$30 { \pipe2_sr_op__oe__ok$29 \pipe2_sr_op__oe__oe$28 } { \pipe2_sr_op__rc__ok$27 \pipe2_sr_op__rc__rc$26 } { \pipe2_sr_op__imm_data__ok$25 \pipe2_sr_op__imm_data__data$24 } \pipe2_sr_op__fn_unit$23 \pipe2_sr_op__insn_type$22 } - sync init - end - process $group_70 - assign \o 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \o_ok 1'0 - assign { \o_ok \o } { \pipe2_o_ok$39 \pipe2_o$38 } - sync init - end - process $group_72 - assign \cr_a 4'0000 - assign \cr_a_ok 1'0 - assign { \cr_a_ok \cr_a } { \pipe2_cr_a_ok$41 \pipe2_cr_a$40 } - sync init - end - process $group_74 - assign \xer_ca 2'00 - assign \xer_ca_ok 1'0 - assign { \xer_ca_ok \xer_ca } { \pipe2_xer_ca_ok$43 \pipe2_xer_ca$42 } - sync init - end - connect \muxid 2'00 -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.shiftrot0.src_l" -module \src_l$116 - attribute \src "simple/issuer.py:141" - wire width 1 input 0 \coresync_clk - attribute \src "simple/issuer.py:141" - wire width 1 input 1 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 5 input 2 \s_src - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 5 input 3 \r_src - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire width 5 output 4 \q_src - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire width 5 \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire width 5 \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 5 $1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \Y_WIDTH 5 - connect \A \r_src - connect \Y $1 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 5 $3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $4 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 5 - connect \A \q_int - connect \B $1 - connect \Y $3 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 5 $5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $6 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 5 - connect \A $3 - connect \B \s_src - connect \Y $5 - end - process $group_0 - assign \q_int$next \q_int - assign \q_int$next $5 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \q_int$next 5'00000 - end - sync init - update \q_int 5'00000 - sync posedge \coresync_clk - update \q_int \q_int$next - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 5 $7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $8 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \Y_WIDTH 5 - connect \A \r_src - connect \Y $7 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 5 $9 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $10 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 5 - connect \A \q_int - connect \B $7 - connect \Y $9 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 5 $11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $12 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 5 - connect \A $9 - connect \B \s_src - connect \Y $11 - end - process $group_1 - assign \q_src 5'00000 - assign \q_src $11 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" - wire width 5 \qn_src - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - wire width 5 $13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $14 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \Y_WIDTH 5 - connect \A \q_src - connect \Y $13 - end - process $group_2 - assign \qn_src 5'00000 - assign \qn_src $13 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" - wire width 5 \qlq_src - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - wire width 5 $15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $16 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 5 - connect \A \q_src - connect \B \q_int - connect \Y $15 - end - process $group_3 - assign \qlq_src 5'00000 - assign \qlq_src $15 - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.shiftrot0.opc_l" -module \opc_l$117 - attribute \src "simple/issuer.py:141" - wire width 1 input 0 \coresync_clk - attribute \src "simple/issuer.py:141" - wire width 1 input 1 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 1 input 2 \s_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 1 input 3 \r_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire width 1 output 4 \q_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire width 1 \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire width 1 \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_opc - connect \Y $1 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 1 $3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $4 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B $1 - connect \Y $3 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 1 $5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $6 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $3 - connect \B \s_opc - connect \Y $5 - end - process $group_0 - assign \q_int$next \q_int - assign \q_int$next $5 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \q_int$next 1'0 - end - sync init - update \q_int 1'0 - sync posedge \coresync_clk - update \q_int \q_int$next - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 1 $7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $8 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_opc - connect \Y $7 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 1 $9 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $10 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B $7 - connect \Y $9 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 1 $11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $12 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $9 - connect \B \s_opc - connect \Y $11 - end - process $group_1 - assign \q_opc 1'0 - assign \q_opc $11 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" - wire width 1 \qn_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - wire width 1 $13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $14 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_opc - connect \Y $13 - end - process $group_2 - assign \qn_opc 1'0 - assign \qn_opc $13 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" - wire width 1 \qlq_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - wire width 1 $15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $16 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_opc - connect \B \q_int - connect \Y $15 - end - process $group_3 - assign \qlq_opc 1'0 - assign \qlq_opc $15 - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.shiftrot0.req_l" -module \req_l$118 - attribute \src "simple/issuer.py:141" - wire width 1 input 0 \coresync_clk - attribute \src "simple/issuer.py:141" - wire width 1 input 1 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire width 3 output 2 \q_req - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 3 input 3 \s_req - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 3 input 4 \r_req - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire width 3 \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire width 3 \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 3 $1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A \r_req - connect \Y $1 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 3 $3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $4 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A \q_int - connect \B $1 - connect \Y $3 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 3 $5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $6 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A $3 - connect \B \s_req - connect \Y $5 - end - process $group_0 - assign \q_int$next \q_int - assign \q_int$next $5 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \q_int$next 3'000 - end - sync init - update \q_int 3'000 - sync posedge \coresync_clk - update \q_int \q_int$next - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 3 $7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $8 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A \r_req - connect \Y $7 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 3 $9 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $10 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A \q_int - connect \B $7 - connect \Y $9 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 3 $11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $12 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A $9 - connect \B \s_req - connect \Y $11 - end - process $group_1 - assign \q_req 3'000 - assign \q_req $11 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" - wire width 3 \qn_req - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - wire width 3 $13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $14 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A \q_req - connect \Y $13 - end - process $group_2 - assign \qn_req 3'000 - assign \qn_req $13 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" - wire width 3 \qlq_req - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - wire width 3 $15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $16 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A \q_req - connect \B \q_int - connect \Y $15 - end - process $group_3 - assign \qlq_req 3'000 - assign \qlq_req $15 - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.shiftrot0.rst_l" -module \rst_l$119 - attribute \src "simple/issuer.py:141" - wire width 1 input 0 \coresync_clk - attribute \src "simple/issuer.py:141" - wire width 1 input 1 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 1 input 2 \s_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 1 input 3 \r_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire width 1 \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire width 1 \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_rst - connect \Y $1 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 1 $3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $4 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B $1 - connect \Y $3 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 1 $5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $6 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $3 - connect \B \s_rst - connect \Y $5 - end - process $group_0 - assign \q_int$next \q_int - assign \q_int$next $5 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \q_int$next 1'0 - end - sync init - update \q_int 1'0 - sync posedge \coresync_clk - update \q_int \q_int$next - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire width 1 \q_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 1 $7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $8 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_rst - connect \Y $7 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 1 $9 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $10 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B $7 - connect \Y $9 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 1 $11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $12 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $9 - connect \B \s_rst - connect \Y $11 - end - process $group_1 - assign \q_rst 1'0 - assign \q_rst $11 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" - wire width 1 \qn_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - wire width 1 $13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $14 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_rst - connect \Y $13 - end - process $group_2 - assign \qn_rst 1'0 - assign \qn_rst $13 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" - wire width 1 \qlq_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - wire width 1 $15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $16 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_rst - connect \B \q_int - connect \Y $15 - end - process $group_3 - assign \qlq_rst 1'0 - assign \qlq_rst $15 - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.shiftrot0.rok_l" -module \rok_l$120 - attribute \src "simple/issuer.py:141" - wire width 1 input 0 \coresync_clk - attribute \src "simple/issuer.py:141" - wire width 1 input 1 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire width 1 output 2 \q_rdok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 1 input 3 \s_rdok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 1 input 4 \r_rdok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire width 1 \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire width 1 \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_rdok - connect \Y $1 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 1 $3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $4 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B $1 - connect \Y $3 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 1 $5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $6 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $3 - connect \B \s_rdok - connect \Y $5 - end - process $group_0 - assign \q_int$next \q_int - assign \q_int$next $5 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \q_int$next 1'0 - end - sync init - update \q_int 1'0 - sync posedge \coresync_clk - update \q_int \q_int$next - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 1 $7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $8 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_rdok - connect \Y $7 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 1 $9 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $10 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B $7 - connect \Y $9 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 1 $11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $12 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $9 - connect \B \s_rdok - connect \Y $11 - end - process $group_1 - assign \q_rdok 1'0 - assign \q_rdok $11 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" - wire width 1 \qn_rdok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - wire width 1 $13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $14 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_rdok - connect \Y $13 - end - process $group_2 - assign \qn_rdok 1'0 - assign \qn_rdok $13 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" - wire width 1 \qlq_rdok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - wire width 1 $15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $16 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_rdok - connect \B \q_int - connect \Y $15 - end - process $group_3 - assign \qlq_rdok 1'0 - assign \qlq_rdok $15 - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.shiftrot0.alui_l" -module \alui_l$121 - attribute \src "simple/issuer.py:141" - wire width 1 input 0 \coresync_clk - attribute \src "simple/issuer.py:141" - wire width 1 input 1 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire width 1 output 2 \q_alui - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 1 input 3 \r_alui - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 1 input 4 \s_alui - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire width 1 \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire width 1 \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_alui - connect \Y $1 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 1 $3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $4 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B $1 - connect \Y $3 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 1 $5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $6 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $3 - connect \B \s_alui - connect \Y $5 - end - process $group_0 - assign \q_int$next \q_int - assign \q_int$next $5 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \q_int$next 1'0 - end - sync init - update \q_int 1'0 - sync posedge \coresync_clk - update \q_int \q_int$next - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 1 $7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $8 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_alui - connect \Y $7 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 1 $9 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $10 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B $7 - connect \Y $9 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 1 $11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $12 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $9 - connect \B \s_alui - connect \Y $11 - end - process $group_1 - assign \q_alui 1'0 - assign \q_alui $11 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" - wire width 1 \qn_alui - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - wire width 1 $13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $14 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_alui - connect \Y $13 - end - process $group_2 - assign \qn_alui 1'0 - assign \qn_alui $13 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" - wire width 1 \qlq_alui - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - wire width 1 $15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $16 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_alui - connect \B \q_int - connect \Y $15 - end - process $group_3 - assign \qlq_alui 1'0 - assign \qlq_alui $15 - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.shiftrot0.alu_l" -module \alu_l$122 - attribute \src "simple/issuer.py:141" - wire width 1 input 0 \coresync_clk - attribute \src "simple/issuer.py:141" - wire width 1 input 1 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire width 1 output 2 \q_alu - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 1 input 3 \r_alu - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 1 input 4 \s_alu - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire width 1 \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire width 1 \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_alu - connect \Y $1 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 1 $3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $4 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B $1 - connect \Y $3 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 1 $5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $6 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $3 - connect \B \s_alu - connect \Y $5 - end - process $group_0 - assign \q_int$next \q_int - assign \q_int$next $5 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \q_int$next 1'0 - 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parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $9 - connect \B \s_alu - connect \Y $11 - end - process $group_1 - assign \q_alu 1'0 - assign \q_alu $11 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" - wire width 1 \qn_alu - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - wire width 1 $13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $14 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_alu - connect \Y $13 - end - process $group_2 - assign \qn_alu 1'0 - assign \qn_alu $13 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" - wire width 1 \qlq_alu - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - wire width 1 $15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $16 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_alu - connect \B \q_int - connect \Y $15 - end - process $group_3 - assign \qlq_alu 1'0 - assign \qlq_alu $15 - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.shiftrot0" -module \shiftrot0 - attribute \src "simple/issuer.py:141" - wire width 1 input 0 \coresync_clk - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 input 1 \oper_i_alu_shift_rot0__insn_type - attribute \enum_base_type "Function" - attribute \enum_value_00000000000 "NONE" - attribute \enum_value_00000000010 "ALU" - attribute \enum_value_00000000100 "LDST" - attribute \enum_value_00000001000 "SHIFT_ROT" - attribute \enum_value_00000010000 "LOGICAL" - attribute \enum_value_00000100000 "BRANCH" - attribute \enum_value_00001000000 "CR" - attribute \enum_value_00010000000 "TRAP" - attribute \enum_value_00100000000 "MUL" - attribute \enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 input 2 \oper_i_alu_shift_rot0__fn_unit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 input 3 \oper_i_alu_shift_rot0__imm_data__data - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 4 \oper_i_alu_shift_rot0__imm_data__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 5 \oper_i_alu_shift_rot0__rc__rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 6 \oper_i_alu_shift_rot0__rc__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 7 \oper_i_alu_shift_rot0__oe__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 8 \oper_i_alu_shift_rot0__oe__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 9 \oper_i_alu_shift_rot0__write_cr0 - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 input 10 \oper_i_alu_shift_rot0__input_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 11 \oper_i_alu_shift_rot0__output_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 12 \oper_i_alu_shift_rot0__input_cr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 13 \oper_i_alu_shift_rot0__output_cr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 14 \oper_i_alu_shift_rot0__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 15 \oper_i_alu_shift_rot0__is_signed - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 input 16 \oper_i_alu_shift_rot0__insn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:100" - wire width 1 input 17 \cu_issue_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107" - wire width 1 output 18 \cu_busy_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96" - wire width 5 input 19 \cu_rdmaskn_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 5 output 20 \cu_rd__rel_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 5 input 21 \cu_rd__go_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 64 input 22 \src1_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 64 input 23 \src2_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 64 input 24 \src3_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 1 input 25 \src4_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 2 input 26 \src5_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 27 \o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 3 output 28 \cu_wr__rel_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 3 input 29 \cu_wr__go_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" - wire width 64 output 30 \dest1_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 31 \cr_a_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" - wire width 4 output 32 \dest2_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 33 \xer_ca_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" - wire width 2 output 34 \dest3_o - attribute \src "simple/issuer.py:141" - wire width 1 input 35 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:246" - wire width 1 \alu_shift_rot0_n_valid_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:247" - wire width 1 \alu_shift_rot0_n_ready_i - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \alu_shift_rot0_sr_op__insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \alu_shift_rot0_sr_op__insn_type$next - attribute \enum_base_type "Function" - attribute \enum_value_00000000000 "NONE" - attribute \enum_value_00000000010 "ALU" - attribute \enum_value_00000000100 "LDST" - attribute \enum_value_00000001000 "SHIFT_ROT" - attribute \enum_value_00000010000 "LOGICAL" - attribute \enum_value_00000100000 "BRANCH" - attribute \enum_value_00001000000 "CR" - attribute \enum_value_00010000000 "TRAP" - attribute \enum_value_00100000000 "MUL" - attribute \enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 \alu_shift_rot0_sr_op__fn_unit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 \alu_shift_rot0_sr_op__fn_unit$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \alu_shift_rot0_sr_op__imm_data__data - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \alu_shift_rot0_sr_op__imm_data__data$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \alu_shift_rot0_sr_op__imm_data__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \alu_shift_rot0_sr_op__imm_data__ok$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \alu_shift_rot0_sr_op__rc__rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \alu_shift_rot0_sr_op__rc__rc$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \alu_shift_rot0_sr_op__rc__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \alu_shift_rot0_sr_op__rc__ok$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \alu_shift_rot0_sr_op__oe__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \alu_shift_rot0_sr_op__oe__oe$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \alu_shift_rot0_sr_op__oe__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \alu_shift_rot0_sr_op__oe__ok$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \alu_shift_rot0_sr_op__write_cr0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \alu_shift_rot0_sr_op__write_cr0$next - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \alu_shift_rot0_sr_op__input_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \alu_shift_rot0_sr_op__input_carry$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \alu_shift_rot0_sr_op__output_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \alu_shift_rot0_sr_op__output_carry$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \alu_shift_rot0_sr_op__input_cr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \alu_shift_rot0_sr_op__input_cr$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \alu_shift_rot0_sr_op__output_cr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \alu_shift_rot0_sr_op__output_cr$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \alu_shift_rot0_sr_op__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \alu_shift_rot0_sr_op__is_32bit$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \alu_shift_rot0_sr_op__is_signed - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \alu_shift_rot0_sr_op__is_signed$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \alu_shift_rot0_sr_op__insn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \alu_shift_rot0_sr_op__insn$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 \alu_shift_rot0_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 4 \alu_shift_rot0_cr_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 2 \alu_shift_rot0_xer_ca - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \alu_shift_rot0_ra - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \alu_shift_rot0_rb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 64 \alu_shift_rot0_rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 1 \alu_shift_rot0_xer_so - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/pipe_data.py:29" - wire width 2 \alu_shift_rot0_xer_ca$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:153" - wire width 1 \alu_shift_rot0_p_valid_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:154" - wire width 1 \alu_shift_rot0_p_ready_o - cell \alu_shift_rot0 \alu_shift_rot0 - connect \coresync_clk \coresync_clk - connect \o_ok \o_ok - connect \cr_a_ok \cr_a_ok - connect \xer_ca_ok \xer_ca_ok - connect \coresync_rst \coresync_rst - connect \n_valid_o \alu_shift_rot0_n_valid_o - connect \n_ready_i \alu_shift_rot0_n_ready_i - connect \sr_op__insn_type \alu_shift_rot0_sr_op__insn_type - connect \sr_op__fn_unit \alu_shift_rot0_sr_op__fn_unit - connect \sr_op__imm_data__data \alu_shift_rot0_sr_op__imm_data__data - connect \sr_op__imm_data__ok \alu_shift_rot0_sr_op__imm_data__ok - connect \sr_op__rc__rc \alu_shift_rot0_sr_op__rc__rc - connect \sr_op__rc__ok \alu_shift_rot0_sr_op__rc__ok - connect \sr_op__oe__oe \alu_shift_rot0_sr_op__oe__oe - connect \sr_op__oe__ok \alu_shift_rot0_sr_op__oe__ok - connect \sr_op__write_cr0 \alu_shift_rot0_sr_op__write_cr0 - connect \sr_op__input_carry \alu_shift_rot0_sr_op__input_carry - connect \sr_op__output_carry \alu_shift_rot0_sr_op__output_carry - connect \sr_op__input_cr \alu_shift_rot0_sr_op__input_cr - connect \sr_op__output_cr \alu_shift_rot0_sr_op__output_cr - connect \sr_op__is_32bit \alu_shift_rot0_sr_op__is_32bit - connect \sr_op__is_signed \alu_shift_rot0_sr_op__is_signed - connect \sr_op__insn \alu_shift_rot0_sr_op__insn - connect \o \alu_shift_rot0_o - connect \cr_a \alu_shift_rot0_cr_a - connect \xer_ca \alu_shift_rot0_xer_ca - connect \ra \alu_shift_rot0_ra - connect \rb \alu_shift_rot0_rb - connect \rc \alu_shift_rot0_rc - connect \xer_so \alu_shift_rot0_xer_so - connect \xer_ca$1 \alu_shift_rot0_xer_ca$1 - connect \p_valid_i \alu_shift_rot0_p_valid_i - connect \p_ready_o \alu_shift_rot0_p_ready_o - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 5 \src_l_s_src - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 5 \src_l_s_src$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 5 \src_l_r_src - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 5 \src_l_r_src$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire width 5 \src_l_q_src - cell \src_l$116 \src_l - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \s_src \src_l_s_src - connect \r_src \src_l_r_src - connect \q_src \src_l_q_src - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 1 \opc_l_s_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 1 \opc_l_s_opc$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 1 \opc_l_r_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 1 \opc_l_r_opc$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire width 1 \opc_l_q_opc - cell \opc_l$117 \opc_l - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \s_opc \opc_l_s_opc - connect \r_opc \opc_l_r_opc - connect \q_opc \opc_l_q_opc - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire width 3 \req_l_q_req - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 3 \req_l_s_req - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 3 \req_l_s_req$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 3 \req_l_r_req - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 3 \req_l_r_req$next - cell \req_l$118 \req_l - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \q_req \req_l_q_req - connect \s_req \req_l_s_req - connect \r_req \req_l_r_req - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 1 \rst_l_s_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 1 \rst_l_s_rst$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 1 \rst_l_r_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 1 \rst_l_r_rst$next - cell \rst_l$119 \rst_l - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \s_rst \rst_l_s_rst - connect \r_rst \rst_l_r_rst - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire width 1 \rok_l_q_rdok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 1 \rok_l_s_rdok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 1 \rok_l_s_rdok$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 1 \rok_l_r_rdok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 1 \rok_l_r_rdok$next - cell \rok_l$120 \rok_l - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \q_rdok \rok_l_q_rdok - connect \s_rdok \rok_l_s_rdok - connect \r_rdok \rok_l_r_rdok - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire width 1 \alui_l_q_alui - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 1 \alui_l_r_alui - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 1 \alui_l_r_alui$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 1 \alui_l_s_alui - cell \alui_l$121 \alui_l - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \q_alui \alui_l_q_alui - connect \r_alui \alui_l_r_alui - connect \s_alui \alui_l_s_alui - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire width 1 \alu_l_q_alu - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 1 \alu_l_r_alu - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 1 \alu_l_r_alu$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 1 \alu_l_s_alu - cell \alu_l$122 \alu_l - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \q_alu \alu_l_q_alu - connect \r_alu \alu_l_r_alu - connect \s_alu \alu_l_s_alu - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:187" - wire width 1 \all_rd - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:188" - wire width 1 $2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:188" - cell $and $3 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cu_busy_o - connect \B \rok_l_q_rdok - connect \Y $2 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - wire width 1 $4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - wire width 5 $5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - cell $not $6 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \Y_WIDTH 5 - connect \A \cu_rd__rel_o - connect \Y $5 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - wire width 5 $7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - cell $or $8 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 5 - connect \A $5 - connect \B \cu_rd__go_i - connect \Y $7 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - cell $reduce_and $9 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A $7 - connect \Y $4 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - wire width 1 $10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:189" - cell $and $11 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $2 - connect \B $4 - connect \Y $10 - end - process $group_0 - assign \all_rd 1'0 - assign \all_rd $10 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire width 1 \all_rd_dly - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire width 1 \all_rd_dly$next - process $group_1 - assign \all_rd_dly$next \all_rd_dly - assign \all_rd_dly$next \all_rd - sync init - update \all_rd_dly 1'0 - sync posedge \coresync_clk - update \all_rd_dly \all_rd_dly$next - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" - wire width 1 \all_rd_rise - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - wire width 1 $12 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $not $13 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \all_rd_dly - connect \Y $12 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - wire width 1 $14 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $and $15 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \all_rd - connect \B $12 - connect \Y $14 - end - process $group_2 - assign \all_rd_rise 1'0 - assign \all_rd_rise $14 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:192" - wire width 1 \all_rd_pulse - process $group_3 - assign \all_rd_pulse 1'0 - assign \all_rd_pulse \all_rd_rise - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:196" - wire width 1 \alu_done - process $group_4 - assign \alu_done 1'0 - assign \alu_done \alu_shift_rot0_n_valid_o - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire width 1 \alu_done_dly - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire width 1 \alu_done_dly$next - process $group_5 - assign \alu_done_dly$next \alu_done_dly - assign \alu_done_dly$next \alu_done - sync init - update \alu_done_dly 1'0 - sync posedge \coresync_clk - update \alu_done_dly \alu_done_dly$next - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" - wire width 1 \alu_done_rise - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - wire width 1 $16 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $not $17 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \alu_done_dly - connect \Y $16 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - wire width 1 $18 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $and $19 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \alu_done - connect \B $16 - connect \Y $18 - end - process $group_6 - assign \alu_done_rise 1'0 - assign \alu_done_rise $18 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:197" - wire width 1 \alu_pulse - process $group_7 - assign \alu_pulse 1'0 - assign \alu_pulse \alu_done_rise - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:198" - wire width 3 \alu_pulsem - process $group_8 - assign \alu_pulsem 3'000 - assign \alu_pulsem { \alu_pulse \alu_pulse \alu_pulse } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:204" - wire width 3 \prev_wr_go - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:204" - wire width 3 \prev_wr_go$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:206" - wire width 3 $20 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:206" - cell $and $21 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A \cu_wr__go_i - connect \B { \cu_busy_o \cu_busy_o \cu_busy_o } - connect \Y $20 - end - process $group_9 - assign \prev_wr_go$next \prev_wr_go - assign \prev_wr_go$next $20 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \prev_wr_go$next 3'000 - end - sync init - update \prev_wr_go 3'000 - sync posedge \coresync_clk - update \prev_wr_go \prev_wr_go$next - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:108" - wire width 1 \cu_done_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - wire width 1 $22 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - wire width 1 $23 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - wire width 3 $24 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:97" - wire width 3 \cu_wrmask_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $not $25 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A \cu_wrmask_o - connect \Y $24 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - wire width 3 $26 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $and $27 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A \cu_wr__rel_o - connect \B $24 - connect \Y $26 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $reduce_bool $28 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A $26 - connect \Y $23 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $not $29 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $23 - connect \Y $22 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - wire width 1 $30 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:214" - cell $and $31 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cu_busy_o - connect \B $22 - connect \Y $30 - end - process $group_10 - assign \cu_done_o 1'0 - assign \cu_done_o $30 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:211" - wire width 1 \wr_any - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" - wire width 1 $32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" - cell $reduce_bool $33 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \cu_wr__go_i - connect \Y $32 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" - wire width 1 $34 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" - cell $reduce_bool $35 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \prev_wr_go - connect \Y $34 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" - wire width 1 $36 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:215" - cell $or $37 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $32 - connect \B $34 - connect \Y $36 - end - process $group_11 - assign \wr_any 1'0 - assign \wr_any $36 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:212" - wire width 1 \req_done - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" - wire width 1 $38 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" - cell $not $39 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \alu_shift_rot0_n_ready_i - connect \Y $38 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" - wire width 1 $40 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:216" - cell $and $41 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_any - connect \B $38 - connect \Y $40 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" - wire width 3 $42 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" - cell $and $43 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A \req_l_q_req - connect \B \cu_wrmask_o - connect \Y $42 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" - wire width 1 $44 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" - cell $eq $45 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $42 - connect \B 1'0 - connect \Y $44 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" - wire width 1 $46 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:217" - cell $and $47 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $40 - connect \B $44 - connect \Y $46 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - wire width 1 $48 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - cell $eq $49 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cu_wrmask_o - connect \B 1'0 - connect \Y $48 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - wire width 1 $50 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - cell $and $51 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $48 - connect \B \alu_shift_rot0_n_ready_i - connect \Y $50 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - wire width 1 $52 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - cell $and $53 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $50 - connect \B \alu_shift_rot0_n_valid_o - connect \Y $52 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - wire width 1 $54 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - cell $and $55 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $52 - connect \B \cu_busy_o - connect \Y $54 - end - process $group_12 - assign \req_done 1'0 - assign \req_done $46 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - switch { $54 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:222" - case 1'1 - assign \req_done 1'1 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:226" - wire width 1 \reset - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:104" - wire width 1 \cu_go_die_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:230" - wire width 1 $56 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:230" - cell $or $57 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \req_done - connect \B \cu_go_die_i - connect \Y $56 - end - process $group_13 - assign \reset 1'0 - assign \reset $56 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:227" - wire width 1 \rst_r - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:231" - wire width 1 $58 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:231" - cell $or $59 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cu_issue_i - connect \B \cu_go_die_i - connect \Y $58 - end - process $group_14 - assign \rst_r 1'0 - assign \rst_r $58 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:228" - wire width 3 \reset_w - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:232" - wire width 3 $60 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:232" - cell $or $61 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A \cu_wr__go_i - connect \B { \cu_go_die_i \cu_go_die_i \cu_go_die_i } - connect \Y $60 - end - process $group_15 - assign \reset_w 3'000 - assign \reset_w $60 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:229" - wire width 5 \reset_r - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:233" - wire width 5 $62 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:233" - cell $or $63 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 5 - connect \A \cu_rd__go_i - connect \B { \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i \cu_go_die_i } - connect \Y $62 - end - process $group_16 - assign \reset_r 5'00000 - assign \reset_r $62 - sync init - end - process $group_17 - assign \rok_l_s_rdok$next \rok_l_s_rdok - assign \rok_l_s_rdok$next \cu_issue_i - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \rok_l_s_rdok$next 1'0 - end - sync init - update \rok_l_s_rdok 1'0 - sync posedge \coresync_clk - update \rok_l_s_rdok \rok_l_s_rdok$next - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:237" - wire width 1 $64 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:237" - cell $and $65 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \alu_shift_rot0_n_valid_o - connect \B \cu_busy_o - connect \Y $64 - end - process $group_18 - assign \rok_l_r_rdok$next \rok_l_r_rdok - assign \rok_l_r_rdok$next $64 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \rok_l_r_rdok$next 1'1 - end - sync init - update \rok_l_r_rdok 1'1 - sync posedge \coresync_clk - update \rok_l_r_rdok \rok_l_r_rdok$next - end - process $group_19 - assign \rst_l_s_rst$next \rst_l_s_rst - assign \rst_l_s_rst$next \all_rd - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \rst_l_s_rst$next 1'0 - end - sync init - update \rst_l_s_rst 1'0 - sync posedge \coresync_clk - update \rst_l_s_rst \rst_l_s_rst$next - end - process $group_20 - assign \rst_l_r_rst$next \rst_l_r_rst - assign \rst_l_r_rst$next \rst_r - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \rst_l_r_rst$next 1'1 - end - sync init - update \rst_l_r_rst 1'1 - sync posedge \coresync_clk - update \rst_l_r_rst \rst_l_r_rst$next - end - process $group_21 - assign \opc_l_s_opc$next \opc_l_s_opc - assign \opc_l_s_opc$next \cu_issue_i - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \opc_l_s_opc$next 1'0 - end - sync init - update \opc_l_s_opc 1'0 - sync posedge \coresync_clk - update \opc_l_s_opc \opc_l_s_opc$next - end - process $group_22 - assign \opc_l_r_opc$next \opc_l_r_opc - assign \opc_l_r_opc$next \req_done - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \opc_l_r_opc$next 1'1 - end - sync init - update \opc_l_r_opc 1'1 - sync posedge \coresync_clk - update \opc_l_r_opc \opc_l_r_opc$next - end - process $group_23 - assign \src_l_s_src$next \src_l_s_src - assign \src_l_s_src$next { \cu_issue_i \cu_issue_i \cu_issue_i \cu_issue_i \cu_issue_i } - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \src_l_s_src$next 5'00000 - end - sync init - update \src_l_s_src 5'00000 - sync posedge \coresync_clk - update \src_l_s_src \src_l_s_src$next - end - process $group_24 - assign \src_l_r_src$next \src_l_r_src - assign \src_l_r_src$next \reset_r - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \src_l_r_src$next 5'11111 - end - sync init - update \src_l_r_src 5'11111 - sync posedge \coresync_clk - update \src_l_r_src \src_l_r_src$next - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:252" - wire width 3 $66 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:252" - cell $and $67 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A \alu_pulsem - connect \B \cu_wrmask_o - connect \Y $66 - end - process $group_25 - assign \req_l_s_req$next \req_l_s_req - assign \req_l_s_req$next $66 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \req_l_s_req$next 3'000 - end - sync init - update \req_l_s_req 3'000 - sync posedge \coresync_clk - update \req_l_s_req \req_l_s_req$next - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:253" - wire width 3 $68 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:253" - cell $or $69 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A \reset_w - connect \B \prev_wr_go - connect \Y $68 - end - process $group_26 - assign \req_l_r_req$next \req_l_r_req - assign \req_l_r_req$next $68 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \req_l_r_req$next 3'111 - end - sync init - update \req_l_r_req 3'111 - sync posedge \coresync_clk - update \req_l_r_req \req_l_r_req$next - end - process $group_27 - assign \alu_shift_rot0_sr_op__insn_type$next \alu_shift_rot0_sr_op__insn_type - assign \alu_shift_rot0_sr_op__fn_unit$next \alu_shift_rot0_sr_op__fn_unit - assign \alu_shift_rot0_sr_op__imm_data__data$next \alu_shift_rot0_sr_op__imm_data__data - assign \alu_shift_rot0_sr_op__imm_data__ok$next \alu_shift_rot0_sr_op__imm_data__ok - assign \alu_shift_rot0_sr_op__rc__rc$next \alu_shift_rot0_sr_op__rc__rc - assign \alu_shift_rot0_sr_op__rc__ok$next \alu_shift_rot0_sr_op__rc__ok - assign \alu_shift_rot0_sr_op__oe__oe$next \alu_shift_rot0_sr_op__oe__oe - assign \alu_shift_rot0_sr_op__oe__ok$next \alu_shift_rot0_sr_op__oe__ok - assign \alu_shift_rot0_sr_op__write_cr0$next \alu_shift_rot0_sr_op__write_cr0 - assign \alu_shift_rot0_sr_op__input_carry$next \alu_shift_rot0_sr_op__input_carry - assign \alu_shift_rot0_sr_op__output_carry$next \alu_shift_rot0_sr_op__output_carry - assign \alu_shift_rot0_sr_op__input_cr$next \alu_shift_rot0_sr_op__input_cr - assign \alu_shift_rot0_sr_op__output_cr$next \alu_shift_rot0_sr_op__output_cr - assign \alu_shift_rot0_sr_op__is_32bit$next \alu_shift_rot0_sr_op__is_32bit - assign \alu_shift_rot0_sr_op__is_signed$next \alu_shift_rot0_sr_op__is_signed - assign \alu_shift_rot0_sr_op__insn$next \alu_shift_rot0_sr_op__insn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:257" - switch { \cu_issue_i } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:257" - case 1'1 - assign { \alu_shift_rot0_sr_op__insn$next \alu_shift_rot0_sr_op__is_signed$next \alu_shift_rot0_sr_op__is_32bit$next \alu_shift_rot0_sr_op__output_cr$next \alu_shift_rot0_sr_op__input_cr$next \alu_shift_rot0_sr_op__output_carry$next \alu_shift_rot0_sr_op__input_carry$next \alu_shift_rot0_sr_op__write_cr0$next { \alu_shift_rot0_sr_op__oe__ok$next \alu_shift_rot0_sr_op__oe__oe$next } { \alu_shift_rot0_sr_op__rc__ok$next \alu_shift_rot0_sr_op__rc__rc$next } { \alu_shift_rot0_sr_op__imm_data__ok$next \alu_shift_rot0_sr_op__imm_data__data$next } \alu_shift_rot0_sr_op__fn_unit$next \alu_shift_rot0_sr_op__insn_type$next } { \oper_i_alu_shift_rot0__insn \oper_i_alu_shift_rot0__is_signed \oper_i_alu_shift_rot0__is_32bit \oper_i_alu_shift_rot0__output_cr \oper_i_alu_shift_rot0__input_cr \oper_i_alu_shift_rot0__output_carry \oper_i_alu_shift_rot0__input_carry \oper_i_alu_shift_rot0__write_cr0 { \oper_i_alu_shift_rot0__oe__ok \oper_i_alu_shift_rot0__oe__oe } { \oper_i_alu_shift_rot0__rc__ok \oper_i_alu_shift_rot0__rc__rc } { \oper_i_alu_shift_rot0__imm_data__ok \oper_i_alu_shift_rot0__imm_data__data } \oper_i_alu_shift_rot0__fn_unit \oper_i_alu_shift_rot0__insn_type } - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \alu_shift_rot0_sr_op__imm_data__data$next 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \alu_shift_rot0_sr_op__imm_data__ok$next 1'0 - assign \alu_shift_rot0_sr_op__rc__rc$next 1'0 - assign \alu_shift_rot0_sr_op__rc__ok$next 1'0 - assign \alu_shift_rot0_sr_op__oe__oe$next 1'0 - assign \alu_shift_rot0_sr_op__oe__ok$next 1'0 - end - sync init - update \alu_shift_rot0_sr_op__insn_type 7'0000000 - update \alu_shift_rot0_sr_op__fn_unit 11'00000000000 - update \alu_shift_rot0_sr_op__imm_data__data 64'0000000000000000000000000000000000000000000000000000000000000000 - update \alu_shift_rot0_sr_op__imm_data__ok 1'0 - update \alu_shift_rot0_sr_op__rc__rc 1'0 - update \alu_shift_rot0_sr_op__rc__ok 1'0 - update \alu_shift_rot0_sr_op__oe__oe 1'0 - update \alu_shift_rot0_sr_op__oe__ok 1'0 - update \alu_shift_rot0_sr_op__write_cr0 1'0 - update \alu_shift_rot0_sr_op__input_carry 2'00 - update \alu_shift_rot0_sr_op__output_carry 1'0 - update \alu_shift_rot0_sr_op__input_cr 1'0 - update \alu_shift_rot0_sr_op__output_cr 1'0 - update \alu_shift_rot0_sr_op__is_32bit 1'0 - update \alu_shift_rot0_sr_op__is_signed 1'0 - update \alu_shift_rot0_sr_op__insn 32'00000000000000000000000000000000 - sync posedge \coresync_clk - update \alu_shift_rot0_sr_op__insn_type \alu_shift_rot0_sr_op__insn_type$next - update \alu_shift_rot0_sr_op__fn_unit \alu_shift_rot0_sr_op__fn_unit$next - update \alu_shift_rot0_sr_op__imm_data__data \alu_shift_rot0_sr_op__imm_data__data$next - update \alu_shift_rot0_sr_op__imm_data__ok \alu_shift_rot0_sr_op__imm_data__ok$next - update \alu_shift_rot0_sr_op__rc__rc \alu_shift_rot0_sr_op__rc__rc$next - update \alu_shift_rot0_sr_op__rc__ok \alu_shift_rot0_sr_op__rc__ok$next - update \alu_shift_rot0_sr_op__oe__oe \alu_shift_rot0_sr_op__oe__oe$next - update \alu_shift_rot0_sr_op__oe__ok \alu_shift_rot0_sr_op__oe__ok$next - update \alu_shift_rot0_sr_op__write_cr0 \alu_shift_rot0_sr_op__write_cr0$next - update \alu_shift_rot0_sr_op__input_carry \alu_shift_rot0_sr_op__input_carry$next - update \alu_shift_rot0_sr_op__output_carry \alu_shift_rot0_sr_op__output_carry$next - update \alu_shift_rot0_sr_op__input_cr \alu_shift_rot0_sr_op__input_cr$next - update \alu_shift_rot0_sr_op__output_cr \alu_shift_rot0_sr_op__output_cr$next - update \alu_shift_rot0_sr_op__is_32bit \alu_shift_rot0_sr_op__is_32bit$next - update \alu_shift_rot0_sr_op__is_signed \alu_shift_rot0_sr_op__is_signed$next - update \alu_shift_rot0_sr_op__insn \alu_shift_rot0_sr_op__insn$next - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" - wire width 64 \data_r0__o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" - wire width 64 \data_r0__o$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" - wire width 1 \data_r0__o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" - wire width 1 \data_r0__o_ok$next - process $group_43 - assign \data_r0__o$next \data_r0__o - assign \data_r0__o_ok$next \data_r0__o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" - switch { \alu_pulse } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" - case 1'1 - assign { \data_r0__o_ok$next \data_r0__o$next } { \o_ok \alu_shift_rot0_o } - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" - switch { \cu_issue_i } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" - case 1'1 - assign { \data_r0__o_ok$next \data_r0__o$next } 65'00000000000000000000000000000000000000000000000000000000000000000 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \data_r0__o_ok$next 1'0 - end - sync init - update \data_r0__o 64'0000000000000000000000000000000000000000000000000000000000000000 - update \data_r0__o_ok 1'0 - sync posedge \coresync_clk - update \data_r0__o \data_r0__o$next - update \data_r0__o_ok \data_r0__o_ok$next - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" - wire width 4 \data_r1__cr_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" - wire width 4 \data_r1__cr_a$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" - wire width 1 \data_r1__cr_a_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" - wire width 1 \data_r1__cr_a_ok$next - process $group_45 - assign \data_r1__cr_a$next \data_r1__cr_a - assign \data_r1__cr_a_ok$next \data_r1__cr_a_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" - switch { \alu_pulse } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" - case 1'1 - assign { \data_r1__cr_a_ok$next \data_r1__cr_a$next } { \cr_a_ok \alu_shift_rot0_cr_a } - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" - switch { \cu_issue_i } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" - case 1'1 - assign { \data_r1__cr_a_ok$next \data_r1__cr_a$next } 5'00000 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \data_r1__cr_a_ok$next 1'0 - end - sync init - update \data_r1__cr_a 4'0000 - update \data_r1__cr_a_ok 1'0 - sync posedge \coresync_clk - update \data_r1__cr_a \data_r1__cr_a$next - update \data_r1__cr_a_ok \data_r1__cr_a_ok$next - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" - wire width 2 \data_r2__xer_ca - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" - wire width 2 \data_r2__xer_ca$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" - wire width 1 \data_r2__xer_ca_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:268" - wire width 1 \data_r2__xer_ca_ok$next - process $group_47 - assign \data_r2__xer_ca$next \data_r2__xer_ca - assign \data_r2__xer_ca_ok$next \data_r2__xer_ca_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" - switch { \alu_pulse } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:277" - case 1'1 - assign { \data_r2__xer_ca_ok$next \data_r2__xer_ca$next } { \xer_ca_ok \alu_shift_rot0_xer_ca } - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" - switch { \cu_issue_i } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:279" - case 1'1 - assign { \data_r2__xer_ca_ok$next \data_r2__xer_ca$next } 3'000 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \data_r2__xer_ca_ok$next 1'0 - end - sync init - update \data_r2__xer_ca 2'00 - update \data_r2__xer_ca_ok 1'0 - sync posedge \coresync_clk - update \data_r2__xer_ca \data_r2__xer_ca$next - update \data_r2__xer_ca_ok \data_r2__xer_ca_ok$next - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" - wire width 1 $70 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" - cell $and $71 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \o_ok - connect \B \cu_busy_o - connect \Y $70 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" - wire width 1 $72 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" - cell $and $73 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cr_a_ok - connect \B \cu_busy_o - connect \Y $72 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" - wire width 1 $74 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:276" - cell $and $75 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \xer_ca_ok - connect \B \cu_busy_o - connect \Y $74 - end - process $group_49 - assign \cu_wrmask_o 3'000 - assign \cu_wrmask_o { $74 $72 $70 } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:167" - wire width 1 \src_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:168" - wire width 1 $76 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:168" - cell $mux $77 - parameter \WIDTH 1 - connect \A \src_l_q_src [1] - connect \B \opc_l_q_opc - connect \S \alu_shift_rot0_sr_op__imm_data__ok - connect \Y $76 - end - process $group_50 - assign \src_sel 1'0 - assign \src_sel $76 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:166" - wire width 64 \src_or_imm - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:169" - wire width 64 $78 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:169" - cell $mux $79 - parameter \WIDTH 64 - connect \A \src2_i - connect \B \alu_shift_rot0_sr_op__imm_data__data - connect \S \alu_shift_rot0_sr_op__imm_data__ok - connect \Y $78 - end - process $group_51 - assign \src_or_imm 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \src_or_imm $78 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" - wire width 64 \src_r0 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" - wire width 64 \src_r0$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - wire width 64 $80 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - cell $mux $81 - parameter \WIDTH 64 - connect \A \src_r0 - connect \B \src1_i - connect \S \src_l_q_src [0] - connect \Y $80 - end - process $group_52 - assign \alu_shift_rot0_ra 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \alu_shift_rot0_ra $80 - sync init - end - process $group_53 - assign \src_r0$next \src_r0 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" - switch { \src_l_q_src [0] } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" - case 1'1 - assign \src_r0$next \src1_i - end - sync init - update \src_r0 64'0000000000000000000000000000000000000000000000000000000000000000 - sync posedge \coresync_clk - update \src_r0 \src_r0$next - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" - wire width 64 \src_r1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" - wire width 64 \src_r1$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - wire width 64 $82 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - cell $mux $83 - parameter \WIDTH 64 - connect \A \src_r1 - connect \B \src_or_imm - connect \S \src_sel - connect \Y $82 - end - process $group_54 - assign \alu_shift_rot0_rb 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \alu_shift_rot0_rb $82 - sync init - end - process $group_55 - assign \src_r1$next \src_r1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" - switch { \src_sel } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" - case 1'1 - assign \src_r1$next \src_or_imm - end - sync init - update \src_r1 64'0000000000000000000000000000000000000000000000000000000000000000 - sync posedge \coresync_clk - update \src_r1 \src_r1$next - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" - wire width 64 \src_r2 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" - wire width 64 \src_r2$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - wire width 64 $84 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - cell $mux $85 - parameter \WIDTH 64 - connect \A \src_r2 - connect \B \src3_i - connect \S \src_l_q_src [2] - connect \Y $84 - end - process $group_56 - assign \alu_shift_rot0_rc 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \alu_shift_rot0_rc $84 - sync init - end - process $group_57 - assign \src_r2$next \src_r2 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" - switch { \src_l_q_src [2] } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" - case 1'1 - assign \src_r2$next \src3_i - end - sync init - update \src_r2 64'0000000000000000000000000000000000000000000000000000000000000000 - sync posedge \coresync_clk - update \src_r2 \src_r2$next - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" - wire width 1 \src_r3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" - wire width 1 \src_r3$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - wire width 1 $86 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - cell $mux $87 - parameter \WIDTH 1 - connect \A \src_r3 - connect \B \src4_i - connect \S \src_l_q_src [3] - connect \Y $86 - end - process $group_58 - assign \alu_shift_rot0_xer_so 1'0 - assign \alu_shift_rot0_xer_so $86 - sync init - end - process $group_59 - assign \src_r3$next \src_r3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" - switch { \src_l_q_src [3] } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" - case 1'1 - assign \src_r3$next \src4_i - end - sync init - update \src_r3 1'0 - sync posedge \coresync_clk - update \src_r3 \src_r3$next - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" - wire width 2 \src_r4 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" - wire width 2 \src_r4$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - wire width 2 $88 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - cell $mux $89 - parameter \WIDTH 2 - connect \A \src_r4 - connect \B \src5_i - connect \S \src_l_q_src [4] - connect \Y $88 - end - process $group_60 - assign \alu_shift_rot0_xer_ca$1 2'00 - assign \alu_shift_rot0_xer_ca$1 $88 - sync init - end - process $group_61 - assign \src_r4$next \src_r4 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" - switch { \src_l_q_src [4] } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" - case 1'1 - assign \src_r4$next \src5_i - end - sync init - update \src_r4 2'00 - sync posedge \coresync_clk - update \src_r4 \src_r4$next - end - process $group_62 - assign \alu_shift_rot0_p_valid_i 1'0 - assign \alu_shift_rot0_p_valid_i \alui_l_q_alui - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:327" - wire width 1 $90 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:327" - cell $and $91 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \alu_shift_rot0_p_ready_o - connect \B \alui_l_q_alui - connect \Y $90 - end - process $group_63 - assign \alui_l_r_alui$next \alui_l_r_alui - assign \alui_l_r_alui$next $90 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \alui_l_r_alui$next 1'1 - end - sync init - update \alui_l_r_alui 1'1 - sync posedge \coresync_clk - update \alui_l_r_alui \alui_l_r_alui$next - end - process $group_64 - assign \alui_l_s_alui 1'0 - assign \alui_l_s_alui \all_rd_pulse - sync init - end - process $group_65 - assign \alu_shift_rot0_n_ready_i 1'0 - assign \alu_shift_rot0_n_ready_i \alu_l_q_alu - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:334" - wire width 1 $92 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:334" - cell $and $93 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \alu_shift_rot0_n_valid_o - connect \B \alu_l_q_alu - connect \Y $92 - end - process $group_66 - assign \alu_l_r_alu$next \alu_l_r_alu - assign \alu_l_r_alu$next $92 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \alu_l_r_alu$next 1'1 - end - sync init - update \alu_l_r_alu 1'1 - sync posedge \coresync_clk - update \alu_l_r_alu \alu_l_r_alu$next - end - process $group_67 - assign \alu_l_s_alu 1'0 - assign \alu_l_s_alu \all_rd_pulse - sync init - end - process $group_68 - assign \cu_busy_o 1'0 - assign \cu_busy_o \opc_l_q_opc - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - wire width 5 $94 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - cell $and $95 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 5 - connect \A \src_l_q_src - connect \B { \cu_busy_o \cu_busy_o \cu_busy_o \cu_busy_o \cu_busy_o } - connect \Y $94 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:173" - wire width 1 $96 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:173" - cell $not $97 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \alu_shift_rot0_sr_op__imm_data__ok - connect \Y $96 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - wire width 5 $98 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - cell $and $99 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 5 - connect \A $94 - connect \B { 1'1 1'1 1'1 $96 1'1 } - connect \Y $98 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - wire width 5 $100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - cell $not $101 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \Y_WIDTH 5 - connect \A \cu_rdmaskn_i - connect \Y $100 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - wire width 5 $102 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:347" - cell $and $103 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 5 - connect \A $98 - connect \B $100 - connect \Y $102 - end - process $group_69 - assign \cu_rd__rel_o 5'00000 - assign \cu_rd__rel_o $102 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:102" - wire width 1 \cu_shadown_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" - wire width 1 $104 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" - cell $and $105 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cu_busy_o - connect \B \cu_shadown_i - connect \Y $104 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" - wire width 1 $106 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" - cell $and $107 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cu_busy_o - connect \B \cu_shadown_i - connect \Y $106 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" - wire width 1 $108 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:350" - cell $and $109 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cu_busy_o - connect \B \cu_shadown_i - connect \Y $108 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351" - wire width 3 $110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351" - cell $and $111 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A \req_l_q_req - connect \B { $104 $106 $108 } - connect \Y $110 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351" - wire width 3 $112 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:351" - cell $and $113 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A $110 - connect \B \cu_wrmask_o - connect \Y $112 - end - process $group_70 - assign \cu_wr__rel_o 3'000 - assign \cu_wr__rel_o $112 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - wire width 1 $114 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - cell $and $115 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cu_wr__go_i [0] - connect \B \cu_busy_o - connect \Y $114 - end - process $group_71 - assign \dest1_o 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - switch { $114 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - case 1'1 - assign \dest1_o { \data_r0__o_ok \data_r0__o } [63:0] - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - wire width 1 $116 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - cell $and $117 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cu_wr__go_i [1] - connect \B \cu_busy_o - connect \Y $116 - end - process $group_72 - assign \dest2_o 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - switch { $116 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - case 1'1 - assign \dest2_o { \data_r1__cr_a_ok \data_r1__cr_a } [3:0] - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - wire width 1 $118 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - cell $and $119 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cu_wr__go_i [2] - connect \B \cu_busy_o - connect \Y $118 - end - process $group_73 - assign \dest3_o 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - switch { $118 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:355" - case 1'1 - assign \dest3_o { \data_r2__xer_ca_ok \data_r2__xer_ca } [1:0] - end - sync init - end - connect \cu_go_die_i 1'0 - connect \cu_shadown_i 1'1 -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.ldst0.opc_l" -module \opc_l$123 - attribute \src "simple/issuer.py:141" - wire width 1 input 0 \coresync_clk - attribute \src "simple/issuer.py:141" - wire width 1 input 1 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 1 input 2 \s_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 1 input 3 \r_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire width 1 output 4 \q_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire width 1 \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire width 1 \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_opc - connect \Y $1 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 1 $3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $4 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B $1 - connect \Y $3 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 1 $5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $6 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $3 - connect \B \s_opc - connect \Y $5 - end - process $group_0 - assign \q_int$next \q_int - assign \q_int$next $5 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \q_int$next 1'0 - end - sync init - update \q_int 1'0 - sync posedge \coresync_clk - update \q_int \q_int$next - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 1 $7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $8 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_opc - connect \Y $7 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 1 $9 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $10 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B $7 - connect \Y $9 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 1 $11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $12 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $9 - connect \B \s_opc - connect \Y $11 - end - process $group_1 - assign \q_opc 1'0 - assign \q_opc $11 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" - wire width 1 \qn_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - wire width 1 $13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $14 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_opc - connect \Y $13 - end - process $group_2 - assign \qn_opc 1'0 - assign \qn_opc $13 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" - wire width 1 \qlq_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - wire width 1 $15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $16 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_opc - connect \B \q_int - connect \Y $15 - end - process $group_3 - assign \qlq_opc 1'0 - assign \qlq_opc $15 - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.ldst0.src_l" -module \src_l$124 - attribute \src "simple/issuer.py:141" - wire width 1 input 0 \coresync_clk - attribute \src "simple/issuer.py:141" - wire width 1 input 1 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 3 input 2 \s_src - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 3 input 3 \r_src - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire width 3 output 4 \q_src - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire width 3 \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire width 3 \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 3 $1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A \r_src - connect \Y $1 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 3 $3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $4 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A \q_int - connect \B $1 - connect \Y $3 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 3 $5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $6 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A $3 - connect \B \s_src - connect \Y $5 - end - process $group_0 - assign \q_int$next \q_int - assign \q_int$next $5 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \q_int$next 3'000 - end - sync init - update \q_int 3'000 - sync posedge \coresync_clk - update \q_int \q_int$next - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 3 $7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $8 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A \r_src - connect \Y $7 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 3 $9 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $10 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A \q_int - connect \B $7 - connect \Y $9 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 3 $11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $12 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A $9 - connect \B \s_src - connect \Y $11 - end - process $group_1 - assign \q_src 3'000 - assign \q_src $11 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" - wire width 3 \qn_src - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - wire width 3 $13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $14 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A \q_src - connect \Y $13 - end - process $group_2 - assign \qn_src 3'000 - assign \qn_src $13 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" - wire width 3 \qlq_src - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - wire width 3 $15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $16 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A \q_src - connect \B \q_int - connect \Y $15 - end - process $group_3 - assign \qlq_src 3'000 - assign \qlq_src $15 - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.ldst0.alu_l" -module \alu_l$125 - attribute \src "simple/issuer.py:141" - wire width 1 input 0 \coresync_clk - attribute \src "simple/issuer.py:141" - wire width 1 input 1 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 1 input 2 \s_alu - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 1 input 3 \r_alu - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire width 1 output 4 \q_alu - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire width 1 \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire width 1 \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_alu - connect \Y $1 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 1 $3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $4 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B $1 - connect \Y $3 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 1 $5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $6 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $3 - connect \B \s_alu - connect \Y $5 - end - process $group_0 - assign \q_int$next \q_int - assign \q_int$next $5 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \q_int$next 1'0 - end - sync init - update \q_int 1'0 - sync posedge \coresync_clk - update \q_int \q_int$next - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 1 $7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $8 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_alu - connect \Y $7 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 1 $9 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $10 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B $7 - connect \Y $9 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 1 $11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $12 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $9 - connect \B \s_alu - connect \Y $11 - end - process $group_1 - assign \q_alu 1'0 - assign \q_alu $11 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" - wire width 1 \qn_alu - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - wire width 1 $13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $14 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_alu - connect \Y $13 - end - process $group_2 - assign \qn_alu 1'0 - assign \qn_alu $13 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" - wire width 1 \qlq_alu - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - wire width 1 $15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $16 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_alu - connect \B \q_int - connect \Y $15 - end - process $group_3 - assign \qlq_alu 1'0 - assign \qlq_alu $15 - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.ldst0.adr_l" -module \adr_l - attribute \src "simple/issuer.py:141" - wire width 1 input 0 \coresync_clk - attribute \src "simple/issuer.py:141" - wire width 1 input 1 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 1 input 2 \s_adr - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 1 input 3 \r_adr - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire width 1 output 4 \q_adr - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire width 1 \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire width 1 \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_adr - connect \Y $1 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 1 $3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $4 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B $1 - connect \Y $3 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 1 $5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $6 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $3 - connect \B \s_adr - connect \Y $5 - end - process $group_0 - assign \q_int$next \q_int - assign \q_int$next $5 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \q_int$next 1'0 - end - sync init - update \q_int 1'0 - sync posedge \coresync_clk - update \q_int \q_int$next - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 1 $7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $8 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_adr - connect \Y $7 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 1 $9 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $10 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B $7 - connect \Y $9 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 1 $11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $12 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $9 - connect \B \s_adr - connect \Y $11 - end - process $group_1 - assign \q_adr 1'0 - assign \q_adr $11 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" - wire width 1 \qn_adr - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - wire width 1 $13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $14 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_adr - connect \Y $13 - end - process $group_2 - assign \qn_adr 1'0 - assign \qn_adr $13 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" - wire width 1 \qlq_adr - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - wire width 1 $15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $16 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_adr - connect \B \q_int - connect \Y $15 - end - process $group_3 - assign \qlq_adr 1'0 - assign \qlq_adr $15 - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.ldst0.lod_l" -module \lod_l - attribute \src "simple/issuer.py:141" - wire width 1 input 0 \coresync_clk - attribute \src "simple/issuer.py:141" - wire width 1 input 1 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 1 input 2 \s_lod - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 1 input 3 \r_lod - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" - wire width 1 output 4 \qn_lod - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire width 1 \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire width 1 \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_lod - connect \Y $1 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 1 $3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $4 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B $1 - connect \Y $3 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 1 $5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $6 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $3 - connect \B \s_lod - connect \Y $5 - end - process $group_0 - assign \q_int$next \q_int - assign \q_int$next $5 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \q_int$next 1'0 - end - sync init - update \q_int 1'0 - sync posedge \coresync_clk - update \q_int \q_int$next - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire width 1 \q_lod - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 1 $7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $8 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_lod - connect \Y $7 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 1 $9 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $10 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B $7 - connect \Y $9 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 1 $11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $12 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $9 - connect \B \s_lod - connect \Y $11 - end - process $group_1 - assign \q_lod 1'0 - assign \q_lod $11 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - wire width 1 $13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $14 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_lod - connect \Y $13 - end - process $group_2 - assign \qn_lod 1'0 - assign \qn_lod $13 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" - wire width 1 \qlq_lod - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - wire width 1 $15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $16 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_lod - connect \B \q_int - connect \Y $15 - end - process $group_3 - assign \qlq_lod 1'0 - assign \qlq_lod $15 - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.ldst0.sto_l" -module \sto_l - attribute \src "simple/issuer.py:141" - wire width 1 input 0 \coresync_clk - attribute \src "simple/issuer.py:141" - wire width 1 input 1 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 1 input 2 \s_sto - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 1 input 3 \r_sto - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire width 1 output 4 \q_sto - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire width 1 \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire width 1 \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_sto - connect \Y $1 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 1 $3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $4 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B $1 - connect \Y $3 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 1 $5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $6 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $3 - connect \B \s_sto - connect \Y $5 - end - process $group_0 - assign \q_int$next \q_int - assign \q_int$next $5 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \q_int$next 1'0 - end - sync init - update \q_int 1'0 - sync posedge \coresync_clk - update \q_int \q_int$next - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 1 $7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $8 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_sto - connect \Y $7 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 1 $9 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $10 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B $7 - connect \Y $9 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 1 $11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $12 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $9 - connect \B \s_sto - connect \Y $11 - end - process $group_1 - assign \q_sto 1'0 - assign \q_sto $11 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" - wire width 1 \qn_sto - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - wire width 1 $13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $14 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_sto - connect \Y $13 - end - process $group_2 - assign \qn_sto 1'0 - assign \qn_sto $13 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" - wire width 1 \qlq_sto - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - wire width 1 $15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $16 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_sto - connect \B \q_int - connect \Y $15 - end - process $group_3 - assign \qlq_sto 1'0 - assign \qlq_sto $15 - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.ldst0.wri_l" -module \wri_l - attribute \src "simple/issuer.py:141" - wire width 1 input 0 \coresync_clk - attribute \src "simple/issuer.py:141" - wire width 1 input 1 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 1 input 2 \s_wri - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 1 input 3 \r_wri - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire width 1 output 4 \q_wri - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire width 1 \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire width 1 \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_wri - connect \Y $1 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 1 $3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $4 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B $1 - connect \Y $3 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 1 $5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $6 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $3 - connect \B \s_wri - connect \Y $5 - end - process $group_0 - assign \q_int$next \q_int - assign \q_int$next $5 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \q_int$next 1'0 - end - sync init - update \q_int 1'0 - sync posedge \coresync_clk - update \q_int \q_int$next - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 1 $7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $8 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_wri - connect \Y $7 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 1 $9 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $10 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B $7 - connect \Y $9 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 1 $11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $12 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $9 - connect \B \s_wri - connect \Y $11 - end - process $group_1 - assign \q_wri 1'0 - assign \q_wri $11 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" - wire width 1 \qn_wri - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - wire width 1 $13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $14 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_wri - connect \Y $13 - end - process $group_2 - assign \qn_wri 1'0 - assign \qn_wri $13 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" - wire width 1 \qlq_wri - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - wire width 1 $15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $16 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_wri - connect \B \q_int - connect \Y $15 - end - process $group_3 - assign \qlq_wri 1'0 - assign \qlq_wri $15 - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.ldst0.upd_l" -module \upd_l - attribute \src "simple/issuer.py:141" - wire width 1 input 0 \coresync_clk - attribute \src "simple/issuer.py:141" - wire width 1 input 1 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 1 input 2 \s_upd - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 1 input 3 \r_upd - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire width 1 output 4 \q_upd - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire width 1 \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire width 1 \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_upd - connect \Y $1 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 1 $3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $4 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B $1 - connect \Y $3 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 1 $5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $6 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $3 - connect \B \s_upd - connect \Y $5 - end - process $group_0 - assign \q_int$next \q_int - assign \q_int$next $5 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \q_int$next 1'0 - end - sync init - update \q_int 1'0 - sync posedge \coresync_clk - update \q_int \q_int$next - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 1 $7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $8 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_upd - connect \Y $7 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 1 $9 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $10 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B $7 - connect \Y $9 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 1 $11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $12 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $9 - connect \B \s_upd - connect \Y $11 - end - process $group_1 - assign \q_upd 1'0 - assign \q_upd $11 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" - wire width 1 \qn_upd - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - wire width 1 $13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $14 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_upd - connect \Y $13 - end - process $group_2 - assign \qn_upd 1'0 - assign \qn_upd $13 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" - wire width 1 \qlq_upd - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - wire width 1 $15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $16 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_upd - connect \B \q_int - connect \Y $15 - end - process $group_3 - assign \qlq_upd 1'0 - assign \qlq_upd $15 - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.ldst0.rst_l" -module \rst_l$126 - attribute \src "simple/issuer.py:141" - wire width 1 input 0 \coresync_clk - attribute \src "simple/issuer.py:141" - wire width 1 input 1 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 1 input 2 \s_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 1 input 3 \r_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire width 1 output 4 \q_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire width 1 \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire width 1 \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_rst - connect \Y $1 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 1 $3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $4 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B $1 - connect \Y $3 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 1 $5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $6 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $3 - connect \B \s_rst - connect \Y $5 - end - process $group_0 - assign \q_int$next \q_int - assign \q_int$next $5 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \q_int$next 1'0 - end - sync init - update \q_int 1'0 - sync posedge \coresync_clk - update \q_int \q_int$next - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 1 $7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $8 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_rst - connect \Y $7 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 1 $9 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $10 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B $7 - connect \Y $9 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 1 $11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $12 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $9 - connect \B \s_rst - connect \Y $11 - end - process $group_1 - assign \q_rst 1'0 - assign \q_rst $11 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" - wire width 1 \qn_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - wire width 1 $13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $14 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_rst - connect \Y $13 - end - process $group_2 - assign \qn_rst 1'0 - assign \qn_rst $13 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" - wire width 1 \qlq_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - wire width 1 $15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $16 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_rst - connect \B \q_int - connect \Y $15 - end - process $group_3 - assign \qlq_rst 1'0 - assign \qlq_rst $15 - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.ldst0.lsd_l" -module \lsd_l - attribute \src "simple/issuer.py:141" - wire width 1 input 0 \coresync_clk - attribute \src "simple/issuer.py:141" - wire width 1 input 1 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 1 input 2 \s_lsd - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 1 input 3 \r_lsd - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire width 1 output 4 \q_lsd - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire width 1 \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire width 1 \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_lsd - connect \Y $1 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 1 $3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $4 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B $1 - connect \Y $3 - end - attribute \src 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"/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 1 $9 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $10 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B $7 - connect \Y $9 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 1 $11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $12 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $9 - connect \B \s_lsd - connect \Y $11 - end - process $group_1 - assign \q_lsd 1'0 - assign \q_lsd $11 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" - wire width 1 \qn_lsd - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - wire width 1 $13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $14 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_lsd - connect \Y $13 - end - process $group_2 - assign \qn_lsd 1'0 - assign \qn_lsd $13 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" - wire width 1 \qlq_lsd - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - wire width 1 $15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $16 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_lsd - connect \B \q_int - connect \Y $15 - end - process $group_3 - assign \qlq_lsd 1'0 - assign \qlq_lsd $15 - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus.ldst0" -module \ldst0 - attribute \src "simple/issuer.py:141" - wire width 1 input 0 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 1 output 1 \cu_st__rel_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 1 input 2 \cu_ad__go_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 1 output 3 \cu_ad__rel_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 1 input 4 \cu_st__go_i - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute 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\enum_value_00000010000 "LOGICAL" - attribute \enum_value_00000100000 "BRANCH" - attribute \enum_value_00001000000 "CR" - attribute \enum_value_00010000000 "TRAP" - attribute \enum_value_00100000000 "MUL" - attribute \enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 input 6 \oper_i_ldst_ldst0__fn_unit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 input 7 \oper_i_ldst_ldst0__imm_data__data - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 8 \oper_i_ldst_ldst0__imm_data__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 9 \oper_i_ldst_ldst0__zero_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 10 \oper_i_ldst_ldst0__rc__rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 11 \oper_i_ldst_ldst0__rc__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 12 \oper_i_ldst_ldst0__oe__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 13 \oper_i_ldst_ldst0__oe__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 14 \oper_i_ldst_ldst0__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 15 \oper_i_ldst_ldst0__is_signed - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 input 16 \oper_i_ldst_ldst0__data_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 17 \oper_i_ldst_ldst0__byte_reverse - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 input 18 \oper_i_ldst_ldst0__sign_extend - attribute \enum_base_type "LDSTMode" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "update" - attribute \enum_value_10 "cix" - attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 input 19 \oper_i_ldst_ldst0__ldst_mode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 input 20 \oper_i_ldst_ldst0__insn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:100" - wire width 1 input 21 \cu_issue_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:107" - wire width 1 output 22 \cu_busy_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:96" - wire width 3 input 23 \cu_rdmaskn_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 3 output 24 \cu_rd__rel_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 3 input 25 \cu_rd__go_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 64 input 26 \src1_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 64 input 27 \src2_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 64 input 28 \src3_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 2 output 29 \cu_wr__rel_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 2 input 30 \cu_wr__go_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 output 31 \o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 output 32 \ea - attribute \src "simple/issuer.py:141" - wire width 1 input 33 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:105" - wire width 1 input 34 \ldst_port0_busy_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:98" - wire width 1 output 35 \ldst_port0_is_ld_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:99" - wire width 1 output 36 \ldst_port0_is_st_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:102" - wire width 4 output 37 \ldst_port0_data_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 96 output 38 \ldst_port0_addr_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 96 \ldst_port0_addr_i$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 39 \ldst_port0_addr_i_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \ldst_port0_addr_i_ok$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:110" - wire width 1 input 40 \ldst_port0_addr_exc_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:109" - wire width 1 input 41 \ldst_port0_addr_ok_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 input 42 \ldst_port0_ld_data_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 input 43 \ldst_port0_ld_data_o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 output 44 \ldst_port0_st_data_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 45 \ldst_port0_st_data_i_ok - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 1 \opc_l_s_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 1 \opc_l_s_opc$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 1 \opc_l_r_opc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 1 \opc_l_r_opc$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire width 1 \opc_l_q_opc - cell \opc_l$123 \opc_l - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \s_opc \opc_l_s_opc - connect \r_opc \opc_l_r_opc - connect \q_opc \opc_l_q_opc - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 3 \src_l_s_src - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 3 \src_l_s_src$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 3 \src_l_r_src - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 3 \src_l_r_src$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire width 3 \src_l_q_src - cell \src_l$124 \src_l - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \s_src \src_l_s_src - connect \r_src \src_l_r_src - connect \q_src \src_l_q_src - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 1 \alu_l_s_alu - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 1 \alu_l_r_alu - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire width 1 \alu_l_q_alu - cell \alu_l$125 \alu_l - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \s_alu \alu_l_s_alu - connect \r_alu \alu_l_r_alu - connect \q_alu \alu_l_q_alu - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 1 \adr_l_s_adr - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 1 \adr_l_r_adr - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 1 \adr_l_r_adr$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire width 1 \adr_l_q_adr - cell \adr_l \adr_l - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \s_adr \adr_l_s_adr - connect \r_adr \adr_l_r_adr - connect \q_adr \adr_l_q_adr - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 1 \lod_l_s_lod - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 1 \lod_l_r_lod - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" - wire width 1 \lod_l_qn_lod - cell \lod_l \lod_l - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \s_lod \lod_l_s_lod - connect \r_lod \lod_l_r_lod - connect \qn_lod \lod_l_qn_lod - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 1 \sto_l_s_sto - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 1 \sto_l_r_sto - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 1 \sto_l_r_sto$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire width 1 \sto_l_q_sto - cell \sto_l \sto_l - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \s_sto \sto_l_s_sto - connect \r_sto \sto_l_r_sto - connect \q_sto \sto_l_q_sto - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 1 \wri_l_s_wri - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 1 \wri_l_r_wri - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 1 \wri_l_r_wri$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire width 1 \wri_l_q_wri - cell \wri_l \wri_l - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \s_wri \wri_l_s_wri - connect \r_wri \wri_l_r_wri - connect \q_wri \wri_l_q_wri - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 1 \upd_l_s_upd - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 1 \upd_l_s_upd$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 1 \upd_l_r_upd - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 1 \upd_l_r_upd$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire width 1 \upd_l_q_upd - cell \upd_l \upd_l - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \s_upd \upd_l_s_upd - connect \r_upd \upd_l_r_upd - connect \q_upd \upd_l_q_upd - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 1 \rst_l_s_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 1 \rst_l_r_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire width 1 \rst_l_q_rst - cell \rst_l$126 \rst_l - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \s_rst \rst_l_s_rst - connect \r_rst \rst_l_r_rst - connect \q_rst \rst_l_q_rst - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 1 \lsd_l_s_lsd - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 1 \lsd_l_r_lsd - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 1 \lsd_l_r_lsd$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire width 1 \lsd_l_q_lsd - cell \lsd_l \lsd_l - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \s_lsd \lsd_l_s_lsd - connect \r_lsd \lsd_l_r_lsd - connect \q_lsd \lsd_l_q_lsd - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:290" - wire width 1 \reset_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:104" - wire width 1 \cu_go_die_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:294" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:294" - cell $or $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cu_issue_i - connect \B \cu_go_die_i - connect \Y $1 - end - process $group_0 - assign \reset_i 1'0 - assign \reset_i $1 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:286" - wire width 1 \reset_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:108" - wire width 1 \cu_done_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:295" - wire width 1 $3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:295" - cell $or $4 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cu_done_o - connect \B \cu_go_die_i - connect \Y $3 - end - process $group_1 - assign \reset_o 1'0 - assign \reset_o $3 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:287" - wire width 1 \reset_w - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:296" - wire width 1 $5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:296" - cell $or $6 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cu_wr__go_i [0] - connect \B \cu_go_die_i - connect \Y $5 - end - process $group_2 - assign \reset_w 1'0 - assign \reset_w $5 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:288" - wire width 1 \reset_u - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:297" - wire width 1 $7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:297" - cell $or $8 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cu_wr__go_i [1] - connect \B \cu_go_die_i - connect \Y $7 - end - process $group_3 - assign \reset_u 1'0 - assign \reset_u $7 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:292" - wire width 1 \reset_s - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:298" - wire width 1 $9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:298" - cell $or $10 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cu_st__go_i - connect \B \cu_go_die_i - connect \Y $9 - end - process $group_4 - assign \reset_s 1'0 - assign \reset_s $9 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:291" - wire width 3 \reset_r - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:299" - wire width 3 $11 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:299" - cell $or $12 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A \cu_rd__go_i - connect \B { \cu_go_die_i \cu_go_die_i \cu_go_die_i } - connect \Y $11 - end - process $group_5 - assign \reset_r 3'000 - assign \reset_r $11 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:289" - wire width 1 \reset_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:300" - wire width 1 $13 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:300" - cell $or $14 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cu_ad__go_i - connect \B \cu_go_die_i - connect \Y $13 - end - process $group_6 - assign \reset_a 1'0 - assign \reset_a $13 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:302" - wire width 1 \p_st_go - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:302" - wire width 1 \p_st_go$next - process $group_7 - assign \p_st_go$next \p_st_go - assign \p_st_go$next \cu_st__go_i - sync init - update \p_st_go 1'0 - sync posedge \coresync_clk - update \p_st_go \p_st_go$next - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:266" - wire width 1 \op_is_st - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \oper_r__insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \oper_r__insn_type$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:307" - wire width 1 $15 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:307" - cell $eq $16 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A \oper_r__insn_type - connect \B 7'0100110 - connect \Y $15 - end - process $group_8 - assign \op_is_st 1'0 - assign \op_is_st $15 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:265" - wire width 1 \op_is_ld - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:308" - wire width 1 $17 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:308" - cell $eq $18 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A \oper_r__insn_type - connect \B 7'0100101 - connect \Y $17 - end - process $group_9 - assign \op_is_ld 1'0 - assign \op_is_ld $17 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:113" - wire width 1 \load_mem_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:311" - wire width 1 $19 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:311" - cell $and $20 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \op_is_ld - connect \B \cu_ad__go_i - connect \Y $19 - end - process $group_10 - assign \load_mem_o 1'0 - assign \load_mem_o $19 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:114" - wire width 1 \stwd_mem_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:312" - wire width 1 $21 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:312" - cell $and $22 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \op_is_st - connect \B \cu_st__go_i - connect \Y $21 - end - process $group_11 - assign \stwd_mem_o 1'0 - assign \stwd_mem_o $21 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:109" - wire width 1 \ld_o - process $group_12 - assign \ld_o 1'0 - assign \ld_o \op_is_ld - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:110" - wire width 1 \st_o - process $group_13 - assign \st_o 1'0 - assign \st_o \op_is_st - sync init - end - process $group_14 - assign \opc_l_s_opc$next \opc_l_s_opc - assign \opc_l_s_opc$next \cu_issue_i - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \opc_l_s_opc$next 1'0 - end - sync init - update \opc_l_s_opc 1'0 - sync posedge \coresync_clk - update \opc_l_s_opc \opc_l_s_opc$next - end - process $group_15 - assign \opc_l_r_opc$next \opc_l_r_opc - assign \opc_l_r_opc$next \reset_o - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \opc_l_r_opc$next 1'1 - end - sync init - update \opc_l_r_opc 1'1 - sync posedge \coresync_clk - update \opc_l_r_opc \opc_l_r_opc$next - end - process $group_16 - assign \src_l_s_src$next \src_l_s_src - assign \src_l_s_src$next { \cu_issue_i \cu_issue_i \cu_issue_i } - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \src_l_s_src$next 3'000 - end - sync init - update \src_l_s_src 3'000 - sync posedge \coresync_clk - update \src_l_s_src \src_l_s_src$next - end - process $group_17 - assign \src_l_r_src$next \src_l_r_src - assign \src_l_r_src$next \reset_r - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \src_l_r_src$next 3'111 - end - sync init - update \src_l_r_src 3'111 - sync posedge \coresync_clk - update \src_l_r_src \src_l_r_src$next - end - process $group_18 - assign \alu_l_s_alu 1'0 - assign \alu_l_s_alu \reset_i - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:270" - wire width 1 \alu_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:270" - wire width 1 \alu_ok$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:343" - wire width 1 $23 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:269" - wire width 1 \alu_valid - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:343" - cell $not $24 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \alu_valid - connect \Y $23 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:343" - wire width 1 $25 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:343" - cell $and $26 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \alu_ok - connect \B $23 - connect \Y $25 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:343" - wire width 1 $27 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:274" - wire width 1 \rda_any - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:343" - cell $not $28 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \rda_any - connect \Y $27 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:343" - wire width 1 $29 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:343" - cell $and $30 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $25 - connect \B $27 - connect \Y $29 - end - process $group_19 - assign \alu_l_r_alu 1'1 - assign \alu_l_r_alu $29 - sync init - end - process $group_20 - assign \adr_l_s_adr 1'0 - assign \adr_l_s_adr \reset_i - sync init - end - process $group_21 - assign \adr_l_r_adr$next \adr_l_r_adr - assign \adr_l_r_adr$next \reset_a - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \adr_l_r_adr$next 1'1 - end - sync init - update \adr_l_r_adr 1'1 - sync posedge \coresync_clk - update \adr_l_r_adr \adr_l_r_adr$next - end - process $group_22 - assign \lod_l_s_lod 1'0 - assign \lod_l_s_lod \reset_i - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:272" - wire width 1 \ld_ok - process $group_23 - assign \lod_l_r_lod 1'1 - assign \lod_l_r_lod \ld_ok - sync init - end - process $group_24 - assign \wri_l_s_wri 1'0 - assign \wri_l_s_wri \cu_issue_i - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:359" - wire width 2 $31 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:276" - wire width 1 \wr_reset - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:356" - wire width 1 $32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:356" - cell $not $33 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \ldst_port0_busy_o - connect \Y $32 - end - attribute \enum_base_type "LDSTMode" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "update" - attribute \enum_value_10 "cix" - attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \oper_r__ldst_mode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \oper_r__ldst_mode$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:309" - wire width 1 $34 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:309" - cell $eq $35 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \oper_r__ldst_mode - connect \B 2'01 - connect \Y $34 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:356" - wire width 1 $36 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:356" - cell $and $37 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $32 - connect \B $34 - connect \Y $36 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:356" - wire width 1 $38 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:356" - cell $or $39 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_reset - connect \B $36 - connect \Y $38 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:356" - wire width 1 $40 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:356" - cell $not $41 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \ldst_port0_busy_o - connect \Y $40 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:309" - wire width 1 $42 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:309" - cell $eq $43 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \oper_r__ldst_mode - connect \B 2'01 - connect \Y $42 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:356" - wire width 1 $44 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:356" - cell $and $45 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $40 - connect \B $42 - connect \Y $44 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:356" - wire width 1 $46 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:356" - cell $or $47 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_reset - connect \B $44 - connect \Y $46 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:359" - wire width 2 $48 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:359" - cell $or $49 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 2 - connect \A \reset_w - connect \B { $38 $46 } - connect \Y $48 - end - connect $31 $48 - process $group_25 - assign \wri_l_r_wri$next \wri_l_r_wri - assign \wri_l_r_wri$next $31 [0] - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \wri_l_r_wri$next 1'1 - end - sync init - update \wri_l_r_wri 1'1 - sync posedge \coresync_clk - update \wri_l_r_wri \wri_l_r_wri$next - end - process $group_26 - assign \upd_l_s_upd$next \upd_l_s_upd - assign \upd_l_s_upd$next \reset_i - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \upd_l_s_upd$next 1'0 - end - sync init - update \upd_l_s_upd 1'0 - sync posedge \coresync_clk - update \upd_l_s_upd \upd_l_s_upd$next - end - process $group_27 - assign \upd_l_r_upd$next \upd_l_r_upd - assign \upd_l_r_upd$next \reset_u - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \upd_l_r_upd$next 1'1 - end - sync init - update \upd_l_r_upd 1'1 - sync posedge \coresync_clk - update \upd_l_r_upd \upd_l_r_upd$next - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:271" - wire width 1 \addr_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:366" - wire width 1 $50 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:366" - cell $and $51 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \addr_ok - connect \B \op_is_st - connect \Y $50 - end - process $group_28 - assign \sto_l_s_sto 1'0 - assign \sto_l_s_sto $50 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:367" - wire width 1 $52 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:367" - cell $or $53 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \reset_s - connect \B \p_st_go - connect \Y $52 - end - process $group_29 - assign \sto_l_r_sto$next \sto_l_r_sto - assign \sto_l_r_sto$next $52 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \sto_l_r_sto$next 1'1 - end - sync init - update \sto_l_r_sto 1'1 - sync posedge \coresync_clk - update \sto_l_r_sto \sto_l_r_sto$next - end - process $group_30 - assign \lsd_l_s_lsd 1'0 - assign \lsd_l_s_lsd \cu_issue_i - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:371" - wire width 1 $54 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:371" - cell $or $55 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \reset_s - connect \B \p_st_go - connect \Y $54 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:371" - wire width 1 $56 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:371" - cell $or $57 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $54 - connect \B \ld_ok - connect \Y $56 - end - process $group_31 - assign \lsd_l_r_lsd$next \lsd_l_r_lsd - assign \lsd_l_r_lsd$next $56 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \lsd_l_r_lsd$next 1'1 - end - sync init - update \lsd_l_r_lsd 1'1 - sync posedge \coresync_clk - update \lsd_l_r_lsd \lsd_l_r_lsd$next - end - process $group_32 - assign \rst_l_s_rst 1'0 - assign \rst_l_s_rst \addr_ok - sync init - end - process $group_33 - assign \rst_l_r_rst 1'1 - assign \rst_l_r_rst \cu_issue_i - sync init - end - attribute \enum_base_type "Function" - attribute \enum_value_00000000000 "NONE" - attribute \enum_value_00000000010 "ALU" - attribute \enum_value_00000000100 "LDST" - attribute \enum_value_00000001000 "SHIFT_ROT" - attribute \enum_value_00000010000 "LOGICAL" - attribute \enum_value_00000100000 "BRANCH" - attribute \enum_value_00001000000 "CR" - attribute \enum_value_00010000000 "TRAP" - attribute \enum_value_00100000000 "MUL" - attribute \enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 \oper_r__fn_unit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 \oper_r__fn_unit$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \oper_r__imm_data__data - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \oper_r__imm_data__data$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \oper_r__imm_data__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \oper_r__imm_data__ok$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \oper_r__zero_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \oper_r__zero_a$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \oper_r__rc__rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \oper_r__rc__rc$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \oper_r__rc__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \oper_r__rc__ok$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \oper_r__oe__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \oper_r__oe__oe$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \oper_r__oe__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \oper_r__oe__ok$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \oper_r__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \oper_r__is_32bit$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \oper_r__is_signed - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \oper_r__is_signed$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \oper_r__data_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \oper_r__data_len$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \oper_r__byte_reverse - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \oper_r__byte_reverse$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \oper_r__sign_extend - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \oper_r__sign_extend$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \oper_r__insn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \oper_r__insn$next - process $group_34 - assign \oper_r__insn_type$next \oper_r__insn_type - assign \oper_r__fn_unit$next \oper_r__fn_unit - assign \oper_r__imm_data__data$next \oper_r__imm_data__data - assign \oper_r__imm_data__ok$next \oper_r__imm_data__ok - assign \oper_r__zero_a$next \oper_r__zero_a - assign \oper_r__rc__rc$next \oper_r__rc__rc - assign \oper_r__rc__ok$next \oper_r__rc__ok - assign \oper_r__oe__oe$next \oper_r__oe__oe - assign \oper_r__oe__ok$next \oper_r__oe__ok - assign \oper_r__is_32bit$next \oper_r__is_32bit - assign \oper_r__is_signed$next \oper_r__is_signed - assign \oper_r__data_len$next \oper_r__data_len - assign \oper_r__byte_reverse$next \oper_r__byte_reverse - assign \oper_r__sign_extend$next \oper_r__sign_extend - assign \oper_r__ldst_mode$next \oper_r__ldst_mode - assign \oper_r__insn$next \oper_r__insn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:378" - switch { \cu_issue_i } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:378" - case 1'1 - assign { \oper_r__insn$next \oper_r__ldst_mode$next \oper_r__sign_extend$next \oper_r__byte_reverse$next \oper_r__data_len$next \oper_r__is_signed$next \oper_r__is_32bit$next { \oper_r__oe__ok$next \oper_r__oe__oe$next } { \oper_r__rc__ok$next \oper_r__rc__rc$next } \oper_r__zero_a$next { \oper_r__imm_data__ok$next \oper_r__imm_data__data$next } \oper_r__fn_unit$next \oper_r__insn_type$next } { \oper_i_ldst_ldst0__insn \oper_i_ldst_ldst0__ldst_mode \oper_i_ldst_ldst0__sign_extend \oper_i_ldst_ldst0__byte_reverse \oper_i_ldst_ldst0__data_len \oper_i_ldst_ldst0__is_signed \oper_i_ldst_ldst0__is_32bit { \oper_i_ldst_ldst0__oe__ok \oper_i_ldst_ldst0__oe__oe } { \oper_i_ldst_ldst0__rc__ok \oper_i_ldst_ldst0__rc__rc } \oper_i_ldst_ldst0__zero_a { \oper_i_ldst_ldst0__imm_data__ok \oper_i_ldst_ldst0__imm_data__data } \oper_i_ldst_ldst0__fn_unit \oper_i_ldst_ldst0__insn_type } - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:380" - switch { \cu_done_o } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:380" - case 1'1 - assign { \oper_r__insn$next \oper_r__ldst_mode$next \oper_r__sign_extend$next \oper_r__byte_reverse$next \oper_r__data_len$next \oper_r__is_signed$next \oper_r__is_32bit$next { \oper_r__oe__ok$next \oper_r__oe__oe$next } { \oper_r__rc__ok$next \oper_r__rc__rc$next } \oper_r__zero_a$next { \oper_r__imm_data__ok$next \oper_r__imm_data__data$next } \oper_r__fn_unit$next \oper_r__insn_type$next } 130'0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \oper_r__imm_data__data$next 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \oper_r__imm_data__ok$next 1'0 - assign \oper_r__rc__rc$next 1'0 - assign \oper_r__rc__ok$next 1'0 - assign \oper_r__oe__oe$next 1'0 - assign \oper_r__oe__ok$next 1'0 - end - sync init - update \oper_r__insn_type 7'0000000 - update \oper_r__fn_unit 11'00000000000 - update \oper_r__imm_data__data 64'0000000000000000000000000000000000000000000000000000000000000000 - update \oper_r__imm_data__ok 1'0 - update \oper_r__zero_a 1'0 - update \oper_r__rc__rc 1'0 - update \oper_r__rc__ok 1'0 - update \oper_r__oe__oe 1'0 - update \oper_r__oe__ok 1'0 - update \oper_r__is_32bit 1'0 - update \oper_r__is_signed 1'0 - update \oper_r__data_len 4'0000 - update \oper_r__byte_reverse 1'0 - update \oper_r__sign_extend 1'0 - update \oper_r__ldst_mode 2'00 - update \oper_r__insn 32'00000000000000000000000000000000 - sync posedge \coresync_clk - update \oper_r__insn_type \oper_r__insn_type$next - update \oper_r__fn_unit \oper_r__fn_unit$next - update \oper_r__imm_data__data \oper_r__imm_data__data$next - update \oper_r__imm_data__ok \oper_r__imm_data__ok$next - update \oper_r__zero_a \oper_r__zero_a$next - update \oper_r__rc__rc \oper_r__rc__rc$next - update \oper_r__rc__ok \oper_r__rc__ok$next - update \oper_r__oe__oe \oper_r__oe__oe$next - update \oper_r__oe__ok \oper_r__oe__ok$next - update \oper_r__is_32bit \oper_r__is_32bit$next - update \oper_r__is_signed \oper_r__is_signed$next - update \oper_r__data_len \oper_r__data_len$next - update \oper_r__byte_reverse \oper_r__byte_reverse$next - update \oper_r__sign_extend \oper_r__sign_extend$next - update \oper_r__ldst_mode \oper_r__ldst_mode$next - update \oper_r__insn \oper_r__insn$next - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:384" - wire width 64 \ldd_r - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:280" - wire width 64 \ldd_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" - wire width 64 \ldo_r - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" - wire width 64 \ldo_r$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - wire width 64 $58 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - cell $mux $59 - parameter \WIDTH 64 - connect \A \ldo_r - connect \B \ldd_o - connect \S \ld_ok - connect \Y $58 - end - process $group_50 - assign \ldd_r 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \ldd_r $58 - sync init - end - process $group_51 - assign \ldo_r$next \ldo_r - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" - switch { \ld_ok } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" - case 1'1 - assign \ldo_r$next \ldd_o - end - sync init - update \ldo_r 64'0000000000000000000000000000000000000000000000000000000000000000 - sync posedge \coresync_clk - update \ldo_r \ldo_r$next - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:391" - wire width 64 \src_r0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:391" - wire width 64 \src_r0$next - process $group_52 - assign \src_r0$next \src_r0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:392" - switch { \cu_rd__go_i [0] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:392" - case 1'1 - assign \src_r0$next \src1_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:394" - switch { \cu_issue_i } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:394" - case 1'1 - assign \src_r0$next 64'0000000000000000000000000000000000000000000000000000000000000000 - end - sync init - update \src_r0 64'0000000000000000000000000000000000000000000000000000000000000000 - sync posedge \coresync_clk - update \src_r0 \src_r0$next - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:391" - wire width 64 \src_r1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:391" - wire width 64 \src_r1$next - process $group_53 - assign \src_r1$next \src_r1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:392" - switch { \cu_rd__go_i [1] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:392" - case 1'1 - assign \src_r1$next \src2_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:394" - switch { \cu_issue_i } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:394" - case 1'1 - assign \src_r1$next 64'0000000000000000000000000000000000000000000000000000000000000000 - end - sync init - update \src_r1 64'0000000000000000000000000000000000000000000000000000000000000000 - sync posedge \coresync_clk - update \src_r1 \src_r1$next - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:391" - wire width 64 \src_r2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:391" - wire width 64 \src_r2$next - process $group_54 - assign \src_r2$next \src_r2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:392" - switch { \cu_rd__go_i [2] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:392" - case 1'1 - assign \src_r2$next \src3_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:394" - switch { \cu_issue_i } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:394" - case 1'1 - assign \src_r2$next 64'0000000000000000000000000000000000000000000000000000000000000000 - end - sync init - update \src_r2 64'0000000000000000000000000000000000000000000000000000000000000000 - sync posedge \coresync_clk - update \src_r2 \src_r2$next - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:399" - wire width 64 \addr_r - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:279" - wire width 64 \alu_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" - wire width 64 \ea_r - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" - wire width 64 \ea_r$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - wire width 64 $60 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - cell $mux $61 - parameter \WIDTH 64 - connect \A \ea_r - connect \B \alu_o - connect \S \alu_l_q_alu - connect \Y $60 - end - process $group_55 - assign \addr_r 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \addr_r $60 - sync init - end - process $group_56 - assign \ea_r$next \ea_r - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" - switch { \alu_l_q_alu } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" - case 1'1 - assign \ea_r$next \alu_o - end - sync init - update \ea_r 64'0000000000000000000000000000000000000000000000000000000000000000 - sync posedge \coresync_clk - update \ea_r \ea_r$next - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:404" - wire width 64 \src1_or_z - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:405" - wire width 64 $62 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:405" - cell $mux $63 - parameter \WIDTH 64 - connect \A \src_r0 - connect \B 64'0000000000000000000000000000000000000000000000000000000000000000 - connect \S \oper_r__zero_a - connect \Y $62 - end - process $group_57 - assign \src1_or_z 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \src1_or_z $62 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:409" - wire width 64 \src2_or_imm - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:410" - wire width 64 $64 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:410" - cell $mux $65 - parameter \WIDTH 64 - connect \A \src_r1 - connect \B \oper_r__imm_data__data - connect \S \oper_r__imm_data__ok - connect \Y $64 - end - process $group_58 - assign \src2_or_imm 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \src2_or_imm $64 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:413" - wire width 65 $66 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:413" - wire width 65 $67 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:413" - cell $add $68 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \B_SIGNED 0 - parameter \B_WIDTH 64 - parameter \Y_WIDTH 65 - connect \A \src1_or_z - connect \B \src2_or_imm - connect \Y $67 - end - connect $66 $67 - process $group_59 - assign \alu_o 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \alu_o $66 [63:0] - sync init - end - process $group_60 - assign \alu_ok$next \alu_ok - assign \alu_ok$next \alu_valid - sync init - update \alu_ok 1'0 - sync posedge \coresync_clk - update \alu_ok \alu_ok$next - end - process $group_61 - assign \cu_busy_o 1'0 - assign \cu_busy_o \opc_l_q_opc - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:427" - wire width 3 $69 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:427" - cell $and $70 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A \src_l_q_src - connect \B { \cu_busy_o \cu_busy_o \cu_busy_o } - connect \Y $69 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:427" - wire width 2 $71 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:427" - cell $not $72 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \Y_WIDTH 2 - connect \A { \oper_r__imm_data__ok \oper_r__zero_a } - connect \Y $71 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:427" - wire width 3 $73 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:427" - cell $and $74 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 3 - connect \A $69 - connect \B $71 - connect \Y $73 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:427" - wire width 3 $75 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:427" - cell $not $76 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A \cu_rdmaskn_i - connect \Y $75 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:427" - wire width 3 $77 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:427" - cell $and $78 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A $73 - connect \B $75 - connect \Y $77 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:436" - wire width 1 $79 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:436" - cell $and $80 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \src_l_q_src [2] - connect \B \cu_busy_o - connect \Y $79 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:436" - wire width 1 $81 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:436" - cell $and $82 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $79 - connect \B \op_is_st - connect \Y $81 - end - process $group_62 - assign \cu_rd__rel_o 3'000 - assign \cu_rd__rel_o $77 - assign \cu_rd__rel_o [2] $81 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:430" - wire width 1 $83 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:430" - cell $or $84 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cu_rd__go_i [0] - connect \B \cu_rd__go_i [1] - connect \Y $83 - end - process $group_63 - assign \rda_any 1'0 - assign \rda_any $83 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:433" - wire width 1 $85 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:433" - wire width 1 $86 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:433" - cell $or $87 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cu_rd__rel_o [0] - connect \B \cu_rd__rel_o [1] - connect \Y $86 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:433" - cell $not $88 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $86 - connect \Y $85 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:433" - wire width 1 $89 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:433" - cell $and $90 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cu_busy_o - connect \B $85 - connect \Y $89 - end - process $group_64 - assign \alu_valid 1'0 - assign \alu_valid $89 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:275" - wire width 1 \rd_done - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:439" - wire width 1 $91 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:439" - cell $not $92 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cu_rd__rel_o [2] - connect \Y $91 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:439" - wire width 1 $93 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:439" - cell $and $94 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \alu_valid - connect \B $91 - connect \Y $93 - end - process $group_65 - assign \rd_done 1'0 - assign \rd_done $93 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:442" - wire width 1 $95 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:442" - cell $and $96 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \alu_valid - connect \B \adr_l_q_adr - connect \Y $95 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:442" - wire width 1 $97 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:442" - cell $and $98 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $95 - connect \B \cu_busy_o - connect \Y $97 - end - process $group_66 - assign \cu_ad__rel_o 1'0 - assign \cu_ad__rel_o $97 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:445" - wire width 1 $99 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:445" - cell $and $100 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \sto_l_q_sto - connect \B \cu_busy_o - connect \Y $99 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:445" - wire width 1 $101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:445" - cell $and $102 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $99 - connect \B \rd_done - connect \Y $101 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:445" - wire width 1 $103 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:445" - cell $and $104 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $101 - connect \B \op_is_st - connect \Y $103 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:102" - wire width 1 \cu_shadown_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:446" - wire width 1 $105 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:446" - cell $and $106 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $103 - connect \B \cu_shadown_i - connect \Y $105 - end - process $group_67 - assign \cu_st__rel_o 1'0 - assign \cu_st__rel_o $105 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:450" - wire width 1 $107 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:450" - cell $and $108 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \rd_done - connect \B \wri_l_q_wri - connect \Y $107 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:450" - wire width 1 $109 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:450" - cell $and $110 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $107 - connect \B \cu_busy_o - connect \Y $109 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:450" - wire width 1 $111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:450" - cell $and $112 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $109 - connect \B \lod_l_qn_lod - connect \Y $111 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:450" - wire width 1 $113 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:450" - cell $and $114 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $111 - connect \B \op_is_ld - connect \Y $113 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:450" - wire width 1 $115 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:450" - cell $and $116 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $113 - connect \B \cu_shadown_i - connect \Y $115 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:454" - wire width 1 $117 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:454" - cell $and $118 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \upd_l_q_upd - connect \B \cu_busy_o - connect \Y $117 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:309" - wire width 1 $119 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:309" - cell $eq $120 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \oper_r__ldst_mode - connect \B 2'01 - connect \Y $119 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:454" - wire width 1 $121 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:454" - cell $and $122 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $117 - connect \B $119 - connect \Y $121 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:454" - wire width 1 $123 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:454" - cell $and $124 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $121 - connect \B \alu_valid - connect \Y $123 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:454" - wire width 1 $125 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:454" - cell $and $126 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $123 - connect \B \cu_shadown_i - connect \Y $125 - end - process $group_68 - assign \cu_wr__rel_o 2'00 - assign \cu_wr__rel_o [0] $115 - assign \cu_wr__rel_o [1] $125 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:273" - wire width 1 \wr_any - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:458" - wire width 1 $127 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:458" - cell $or $128 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cu_st__go_i - connect \B \p_st_go - connect \Y $127 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:458" - wire width 1 $129 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:458" - cell $or $130 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $127 - connect \B \cu_wr__go_i [0] - connect \Y $129 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:458" - wire width 1 $131 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:458" - cell $or $132 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $129 - connect \B \cu_wr__go_i [1] - connect \Y $131 - end - process $group_69 - assign \wr_any 1'0 - assign \wr_any $131 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:461" - wire width 1 $133 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:461" - cell $and $134 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \rst_l_q_rst - connect \B \cu_busy_o - connect \Y $133 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:461" - wire width 1 $135 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:461" - cell $and $136 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $133 - connect \B \cu_shadown_i - connect \Y $135 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:461" - wire width 1 $137 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:461" - wire width 1 $138 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:461" - cell $or $139 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cu_st__rel_o - connect \B \cu_wr__rel_o [0] - connect \Y $138 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:461" - wire width 1 $140 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:461" - cell $or $141 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $138 - connect \B \cu_wr__rel_o [1] - connect \Y $140 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:461" - cell $not $142 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $140 - connect \Y $137 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:461" - wire width 1 $143 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:461" - cell $and $144 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $135 - connect \B $137 - connect \Y $143 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:462" - wire width 1 $145 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:462" - cell $or $146 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \lod_l_qn_lod - connect \B \op_is_st - connect \Y $145 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:462" - wire width 1 $147 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:462" - cell $and $148 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $143 - connect \B $145 - connect \Y $147 - end - process $group_70 - assign \wr_reset 1'0 - assign \wr_reset $147 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:464" - wire width 1 $149 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:464" - cell $not $150 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \ldst_port0_busy_o - connect \Y $149 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:464" - wire width 1 $151 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:464" - cell $or $152 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $149 - connect \B \op_is_ld - connect \Y $151 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:464" - wire width 1 $153 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:464" - cell $and $154 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_reset - connect \B $151 - connect \Y $153 - end - process $group_71 - assign \cu_done_o 1'0 - assign \cu_done_o $153 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" - wire width 64 \dest1_o - process $group_72 - assign \o 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \o \dest1_o - sync init - end - process $group_73 - assign \dest1_o 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:471" - switch { \cu_wr__go_i [0] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:471" - case 1'1 - assign \dest1_o \ldd_r - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" - wire width 64 \dest2_o - process $group_74 - assign \ea 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \ea \dest2_o - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:309" - wire width 1 $155 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:309" - cell $eq $156 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \oper_r__ldst_mode - connect \B 2'01 - connect \Y $155 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:476" - wire width 1 $157 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:476" - cell $and $158 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $155 - connect \B \cu_wr__go_i [1] - connect \Y $157 - end - process $group_75 - assign \dest2_o 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:476" - switch { $157 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:476" - case 1'1 - assign \dest2_o \addr_r - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:97" - wire width 2 \cu_wrmask_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:481" - wire width 3 $159 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:309" - wire width 1 $160 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:309" - cell $eq $161 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \oper_r__ldst_mode - connect \B 2'01 - connect \Y $160 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:481" - wire width 3 $162 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:481" - cell $and $163 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 3 - connect \A { \cu_busy_o \cu_busy_o \cu_busy_o } - connect \B { $160 \op_is_ld } - connect \Y $162 - end - connect $159 $162 - process $group_76 - assign \cu_wrmask_o 2'00 - assign \cu_wrmask_o $159 [1:0] - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:488" - wire width 1 $164 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:488" - cell $and $165 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \op_is_ld - connect \B \cu_busy_o - connect \Y $164 - end - process $group_77 - assign \ldst_port0_is_ld_i 1'0 - assign \ldst_port0_is_ld_i $164 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:489" - wire width 1 $166 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:489" - cell $and $167 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \op_is_st - connect \B \cu_busy_o - connect \Y $166 - end - process $group_78 - assign \ldst_port0_is_st_i 1'0 - assign \ldst_port0_is_st_i $166 - sync init - end - process $group_79 - assign \ldst_port0_data_len 4'0000 - assign \ldst_port0_data_len \oper_r__data_len - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:399" - wire width 96 $168 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:399" - cell $pos $169 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \Y_WIDTH 96 - connect \A \addr_r - connect \Y $168 - end - process $group_80 - assign \ldst_port0_addr_i$next \ldst_port0_addr_i - assign \ldst_port0_addr_i$next $168 - sync init - update \ldst_port0_addr_i 96'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - sync posedge \coresync_clk - update \ldst_port0_addr_i \ldst_port0_addr_i$next - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:493" - wire width 1 $170 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:493" - cell $and $171 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \alu_ok - connect \B \lsd_l_q_lsd - connect \Y $170 - end - process $group_81 - assign \ldst_port0_addr_i_ok$next \ldst_port0_addr_i_ok - assign \ldst_port0_addr_i_ok$next $170 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \ldst_port0_addr_i_ok$next 1'0 - end - sync init - update \ldst_port0_addr_i_ok 1'0 - sync posedge \coresync_clk - update \ldst_port0_addr_i_ok \ldst_port0_addr_i_ok$next - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:107" - wire width 1 \addr_exc_o - process $group_82 - assign \addr_exc_o 1'0 - assign \addr_exc_o \ldst_port0_addr_exc_o - sync init - end - process $group_83 - assign \addr_ok 1'0 - assign \addr_ok \ldst_port0_addr_ok_o - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:11" - wire width 64 \lddata_r - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:28" - wire width 64 $172 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:28" - cell $pos $173 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \Y_WIDTH 64 - connect \A { \ldst_port0_ld_data_o [7:0] } - connect \Y $172 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:28" - wire width 64 $174 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:28" - cell $pos $175 - parameter \A_SIGNED 0 - parameter \A_WIDTH 16 - parameter \Y_WIDTH 64 - connect \A { \ldst_port0_ld_data_o [7:0] \ldst_port0_ld_data_o [15:8] } - connect \Y $174 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:28" - wire width 64 $176 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:28" - cell $pos $177 - parameter \A_SIGNED 0 - parameter \A_WIDTH 32 - parameter \Y_WIDTH 64 - connect \A { \ldst_port0_ld_data_o [7:0] \ldst_port0_ld_data_o [15:8] \ldst_port0_ld_data_o [23:16] \ldst_port0_ld_data_o [31:24] } - connect \Y $176 - end - process $group_84 - assign \lddata_r 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:499" - switch { \oper_r__byte_reverse } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:499" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:22" - switch \oper_r__data_len - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:24" - case 4'0001 - assign \lddata_r $172 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:24" - case 4'0010 - assign \lddata_r $174 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:24" - case 4'0100 - assign \lddata_r $176 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:24" - case 4'1000 - assign \lddata_r { \ldst_port0_ld_data_o [7:0] \ldst_port0_ld_data_o [15:8] \ldst_port0_ld_data_o [23:16] \ldst_port0_ld_data_o [31:24] \ldst_port0_ld_data_o [39:32] \ldst_port0_ld_data_o [47:40] \ldst_port0_ld_data_o [55:48] \ldst_port0_ld_data_o [63:56] } - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:504" - case - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:498" - wire width 64 \revnorev - process $group_85 - assign \revnorev 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:499" - switch { \oper_r__byte_reverse } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:499" - case 1'1 - assign \revnorev \lddata_r - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:504" - case - assign \revnorev \ldst_port0_ld_data_o - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:510" - wire width 1 $178 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:510" - cell $eq $179 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \oper_r__data_len - connect \B 2'10 - connect \Y $178 - end - process $group_86 - assign \ldd_o 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:508" - switch { \oper_r__sign_extend } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:508" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:510" - switch { $178 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:510" - case 1'1 - assign \ldd_o { { \revnorev [15:0] [15] \revnorev [15:0] [15] \revnorev [15:0] [15] \revnorev [15:0] [15] \revnorev [15:0] [15] \revnorev [15:0] [15] \revnorev [15:0] [15] \revnorev [15:0] [15] \revnorev [15:0] [15] \revnorev [15:0] [15] \revnorev [15:0] [15] \revnorev [15:0] [15] \revnorev [15:0] [15] \revnorev [15:0] [15] \revnorev [15:0] [15] \revnorev [15:0] [15] \revnorev [15:0] [15] \revnorev [15:0] [15] \revnorev [15:0] [15] \revnorev [15:0] [15] \revnorev [15:0] [15] \revnorev [15:0] [15] \revnorev [15:0] [15] \revnorev [15:0] [15] \revnorev [15:0] [15] \revnorev [15:0] [15] \revnorev [15:0] [15] \revnorev [15:0] [15] \revnorev [15:0] [15] \revnorev [15:0] [15] \revnorev [15:0] [15] \revnorev [15:0] [15] \revnorev [15:0] [15] \revnorev [15:0] [15] \revnorev [15:0] [15] \revnorev [15:0] [15] \revnorev [15:0] [15] \revnorev [15:0] [15] \revnorev [15:0] [15] \revnorev [15:0] [15] \revnorev [15:0] [15] \revnorev [15:0] [15] \revnorev [15:0] [15] \revnorev [15:0] [15] \revnorev [15:0] [15] \revnorev [15:0] [15] \revnorev [15:0] [15] \revnorev [15:0] [15] } \revnorev [15:0] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:512" - case - assign \ldd_o { { \revnorev [31:0] [31] \revnorev [31:0] [31] \revnorev [31:0] [31] \revnorev [31:0] [31] \revnorev [31:0] [31] \revnorev [31:0] [31] \revnorev [31:0] [31] \revnorev [31:0] [31] \revnorev [31:0] [31] \revnorev [31:0] [31] \revnorev [31:0] [31] \revnorev [31:0] [31] \revnorev [31:0] [31] \revnorev [31:0] [31] \revnorev [31:0] [31] \revnorev [31:0] [31] \revnorev [31:0] [31] \revnorev [31:0] [31] \revnorev [31:0] [31] \revnorev [31:0] [31] \revnorev [31:0] [31] \revnorev [31:0] [31] \revnorev [31:0] [31] \revnorev [31:0] [31] \revnorev [31:0] [31] \revnorev [31:0] [31] \revnorev [31:0] [31] \revnorev [31:0] [31] \revnorev [31:0] [31] \revnorev [31:0] [31] \revnorev [31:0] [31] \revnorev [31:0] [31] } \revnorev [31:0] } - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:514" - case - assign \ldd_o \revnorev - end - sync init - end - process $group_87 - assign \ld_ok 1'0 - assign \ld_ok \ldst_port0_ld_data_o_ok - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:11" - wire width 64 \stdata_r - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:28" - wire width 64 $180 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:28" - cell $pos $181 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \Y_WIDTH 64 - connect \A { \src_r2 [7:0] } - connect \Y $180 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:28" - wire width 64 $182 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:28" - cell $pos $183 - parameter \A_SIGNED 0 - parameter \A_WIDTH 16 - parameter \Y_WIDTH 64 - connect \A { \src_r2 [7:0] \src_r2 [15:8] } - connect \Y $182 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:28" - wire width 64 $184 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:28" - cell $pos $185 - parameter \A_SIGNED 0 - parameter \A_WIDTH 32 - parameter \Y_WIDTH 64 - connect \A { \src_r2 [7:0] \src_r2 [15:8] \src_r2 [23:16] \src_r2 [31:24] } - connect \Y $184 - end - process $group_88 - assign \stdata_r 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:522" - switch { \oper_r__byte_reverse } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:522" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:22" - switch \oper_r__data_len - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:24" - case 4'0001 - assign \stdata_r $180 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:24" - case 4'0010 - assign \stdata_r $182 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:24" - case 4'0100 - assign \stdata_r $184 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/byterev.py:24" - case 4'1000 - assign \stdata_r { \src_r2 [7:0] \src_r2 [15:8] \src_r2 [23:16] \src_r2 [31:24] \src_r2 [39:32] \src_r2 [47:40] \src_r2 [55:48] \src_r2 [63:56] } - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:527" - case - end - sync init - end - process $group_89 - assign \ldst_port0_st_data_i 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:522" - switch { \oper_r__byte_reverse } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:522" - case 1'1 - assign \ldst_port0_st_data_i \stdata_r - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compldst_multi.py:527" - case - assign \ldst_port0_st_data_i \src_r2 - end - sync init - end - process $group_90 - assign \ldst_port0_st_data_i_ok 1'0 - assign \ldst_port0_st_data_i_ok \cu_st__go_i - sync init - end - connect \cu_go_die_i 1'0 - connect \cu_shadown_i 1'1 -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fus" -module \fus - attribute \src "simple/issuer.py:141" - wire width 1 input 0 \coresync_clk - attribute \src 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attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 258 \cr_a_ok$113 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 259 \cr_a_ok$114 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" - wire width 4 output 260 \dest2_o$115 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" - wire width 4 output 261 \dest3_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" - wire width 4 output 262 \dest2_o$116 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" - wire width 4 output 263 \dest2_o$117 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" - wire width 4 output 264 \dest2_o$118 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" - wire width 4 output 265 \dest2_o$119 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 266 \xer_ca_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 267 \xer_ca_ok$120 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 268 \xer_ca_ok$121 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" - wire width 2 output 269 \dest3_o$122 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" - wire width 2 output 270 \dest6_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" - wire width 2 output 271 \dest3_o$123 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 272 \xer_ov_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 273 \xer_ov_ok$124 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 274 \xer_ov_ok$125 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 275 \xer_ov_ok$126 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" - wire width 2 output 276 \dest4_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" - wire width 2 output 277 \dest5_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" - wire width 2 output 278 \dest3_o$127 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" - wire width 2 output 279 \dest3_o$128 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 280 \xer_so_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 281 \xer_so_ok$129 - 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- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 3 input 290 \cu_wr__go_i$137 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 291 \fast1_ok$138 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 292 \fast1_ok$139 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 293 \fast2_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 294 \fast2_ok$140 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" - wire width 64 output 295 \dest1_o$141 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" - wire width 64 output 296 \dest2_o$142 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" - wire width 64 output 297 \dest3_o$143 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" - wire width 64 output 298 \dest2_o$144 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" - wire width 64 output 299 \dest3_o$145 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 300 \nia_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 301 \nia_ok$146 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" - wire width 64 output 302 \dest3_o$147 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" - wire width 64 output 303 \dest4_o$148 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 304 \msr_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" - wire width 64 output 305 \dest5_o$149 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 306 \spr1_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" - wire width 64 output 307 \dest2_o$150 - attribute \src "simple/issuer.py:141" - wire width 1 input 308 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:105" - wire width 1 input 309 \ldst_port0_busy_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:98" - wire width 1 output 310 \ldst_port0_is_ld_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:99" - wire width 1 output 311 \ldst_port0_is_st_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:102" - wire width 4 output 312 \ldst_port0_data_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 96 output 313 \ldst_port0_addr_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 314 \ldst_port0_addr_i_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:110" - wire width 1 input 315 \ldst_port0_addr_exc_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:109" - wire width 1 input 316 \ldst_port0_addr_ok_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 input 317 \ldst_port0_ld_data_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 input 318 \ldst_port0_ld_data_o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 output 319 \ldst_port0_st_data_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 320 \ldst_port0_st_data_i_ok - cell \alu0 \alu0 - connect \coresync_clk \coresync_clk - connect \oper_i_alu_alu0__insn_type \oper_i_alu_alu0__insn_type - connect \oper_i_alu_alu0__fn_unit \oper_i_alu_alu0__fn_unit - connect \oper_i_alu_alu0__imm_data__data \oper_i_alu_alu0__imm_data__data - connect \oper_i_alu_alu0__imm_data__ok \oper_i_alu_alu0__imm_data__ok - connect \oper_i_alu_alu0__rc__rc \oper_i_alu_alu0__rc__rc - connect \oper_i_alu_alu0__rc__ok \oper_i_alu_alu0__rc__ok - connect \oper_i_alu_alu0__oe__oe \oper_i_alu_alu0__oe__oe - connect \oper_i_alu_alu0__oe__ok \oper_i_alu_alu0__oe__ok - connect \oper_i_alu_alu0__invert_in \oper_i_alu_alu0__invert_in - connect \oper_i_alu_alu0__zero_a \oper_i_alu_alu0__zero_a - connect \oper_i_alu_alu0__invert_out \oper_i_alu_alu0__invert_out - connect \oper_i_alu_alu0__write_cr0 \oper_i_alu_alu0__write_cr0 - connect \oper_i_alu_alu0__input_carry \oper_i_alu_alu0__input_carry - connect \oper_i_alu_alu0__output_carry \oper_i_alu_alu0__output_carry - connect \oper_i_alu_alu0__is_32bit \oper_i_alu_alu0__is_32bit - connect \oper_i_alu_alu0__is_signed \oper_i_alu_alu0__is_signed - connect \oper_i_alu_alu0__data_len \oper_i_alu_alu0__data_len - connect \oper_i_alu_alu0__insn \oper_i_alu_alu0__insn - connect \cu_issue_i \cu_issue_i - connect \cu_busy_o \cu_busy_o - connect \cu_rdmaskn_i \cu_rdmaskn_i - connect \cu_rd__rel_o \cu_rd__rel_o - connect \cu_rd__go_i \cu_rd__go_i - connect \src1_i \src1_i - connect \src2_i \src2_i - connect \src3_i \src3_i$60 - connect \src4_i \src4_i$65 - connect \o_ok \o_ok - connect \cu_wr__rel_o \cu_wr__rel_o - connect \cu_wr__go_i \cu_wr__go_i - connect \dest1_o \dest1_o - connect \cr_a_ok \cr_a_ok - connect \dest2_o \dest2_o$115 - connect \xer_ca_ok \xer_ca_ok - connect \dest3_o \dest3_o$122 - connect \xer_ov_ok \xer_ov_ok - connect \dest4_o \dest4_o - connect \xer_so_ok \xer_so_ok - connect \dest5_o \dest5_o$132 - connect \coresync_rst \coresync_rst - end - cell \cr0 \cr0 - connect \coresync_clk \coresync_clk - connect \oper_i_alu_cr0__insn_type \oper_i_alu_cr0__insn_type - connect \oper_i_alu_cr0__fn_unit \oper_i_alu_cr0__fn_unit - connect \oper_i_alu_cr0__insn \oper_i_alu_cr0__insn - connect \cu_issue_i \cu_issue_i$1 - connect \cu_busy_o \cu_busy_o$2 - connect \cu_rdmaskn_i \cu_rdmaskn_i$3 - connect \cu_rd__rel_o \cu_rd__rel_o$28 - connect \cu_rd__go_i \cu_rd__go_i$29 - connect \src1_i \src1_i$30 - connect \src2_i \src2_i$52 - connect \src3_i \src3_i$67 - connect \src4_i \src4_i$68 - connect \src5_i \src5_i$72 - connect \src6_i \src6_i$73 - connect \o_ok \o_ok$80 - connect \cu_wr__rel_o \cu_wr__rel_o$81 - connect \cu_wr__go_i \cu_wr__go_i$82 - connect \dest1_o \dest1_o$103 - connect \full_cr_ok \full_cr_ok - connect \dest2_o \dest2_o - connect \cr_a_ok \cr_a_ok$110 - connect \dest3_o \dest3_o - connect \coresync_rst \coresync_rst - end - cell \branch0 \branch0 - connect \coresync_clk \coresync_clk - connect \oper_i_alu_branch0__cia \oper_i_alu_branch0__cia - connect \oper_i_alu_branch0__insn_type \oper_i_alu_branch0__insn_type - connect \oper_i_alu_branch0__fn_unit \oper_i_alu_branch0__fn_unit - connect \oper_i_alu_branch0__insn \oper_i_alu_branch0__insn - connect \oper_i_alu_branch0__imm_data__data \oper_i_alu_branch0__imm_data__data - connect \oper_i_alu_branch0__imm_data__ok \oper_i_alu_branch0__imm_data__ok - connect \oper_i_alu_branch0__lk \oper_i_alu_branch0__lk - connect \oper_i_alu_branch0__is_32bit \oper_i_alu_branch0__is_32bit - connect \cu_issue_i \cu_issue_i$4 - connect \cu_busy_o \cu_busy_o$5 - connect \cu_rdmaskn_i \cu_rdmaskn_i$6 - connect \cu_rd__rel_o \cu_rd__rel_o$69 - connect \cu_rd__go_i \cu_rd__go_i$70 - connect \src3_i \src3_i$71 - connect \src1_i \src1_i$74 - connect \src2_i \src2_i$77 - connect \fast1_ok \fast1_ok - connect \cu_wr__rel_o \cu_wr__rel_o$136 - connect \cu_wr__go_i \cu_wr__go_i$137 - connect \fast2_ok \fast2_ok - connect \dest1_o \dest1_o$141 - connect \dest2_o \dest2_o$144 - connect \nia_ok \nia_ok - connect \dest3_o \dest3_o$147 - connect \coresync_rst \coresync_rst - end - cell \trap0 \trap0 - connect \coresync_clk \coresync_clk - connect \oper_i_alu_trap0__insn_type \oper_i_alu_trap0__insn_type - connect \oper_i_alu_trap0__fn_unit \oper_i_alu_trap0__fn_unit - connect \oper_i_alu_trap0__insn \oper_i_alu_trap0__insn - connect \oper_i_alu_trap0__msr \oper_i_alu_trap0__msr - connect \oper_i_alu_trap0__cia \oper_i_alu_trap0__cia - connect \oper_i_alu_trap0__is_32bit \oper_i_alu_trap0__is_32bit - connect \oper_i_alu_trap0__traptype \oper_i_alu_trap0__traptype - connect \oper_i_alu_trap0__trapaddr \oper_i_alu_trap0__trapaddr - connect \cu_issue_i \cu_issue_i$7 - connect \cu_busy_o \cu_busy_o$8 - connect \cu_rdmaskn_i \cu_rdmaskn_i$9 - connect \cu_rd__rel_o \cu_rd__rel_o$31 - connect \cu_rd__go_i \cu_rd__go_i$32 - connect \src1_i \src1_i$33 - connect \src2_i \src2_i$53 - connect \src3_i \src3_i$75 - connect \src4_i \src4_i$78 - connect \o_ok \o_ok$83 - connect \cu_wr__rel_o \cu_wr__rel_o$84 - connect \cu_wr__go_i \cu_wr__go_i$85 - connect \dest1_o \dest1_o$104 - connect \fast1_ok \fast1_ok$138 - connect \fast2_ok \fast2_ok$140 - connect \dest2_o \dest2_o$142 - connect \dest3_o \dest3_o$145 - connect \nia_ok \nia_ok$146 - connect \dest4_o \dest4_o$148 - connect \msr_ok \msr_ok - connect \dest5_o \dest5_o$149 - connect \coresync_rst \coresync_rst - end - cell \logical0 \logical0 - connect \coresync_clk \coresync_clk - connect \oper_i_alu_logical0__insn_type \oper_i_alu_logical0__insn_type - connect \oper_i_alu_logical0__fn_unit \oper_i_alu_logical0__fn_unit - connect \oper_i_alu_logical0__imm_data__data \oper_i_alu_logical0__imm_data__data - connect \oper_i_alu_logical0__imm_data__ok \oper_i_alu_logical0__imm_data__ok - connect \oper_i_alu_logical0__rc__rc \oper_i_alu_logical0__rc__rc - connect \oper_i_alu_logical0__rc__ok \oper_i_alu_logical0__rc__ok - connect \oper_i_alu_logical0__oe__oe \oper_i_alu_logical0__oe__oe - connect \oper_i_alu_logical0__oe__ok \oper_i_alu_logical0__oe__ok - connect \oper_i_alu_logical0__invert_in \oper_i_alu_logical0__invert_in - connect \oper_i_alu_logical0__zero_a \oper_i_alu_logical0__zero_a - connect \oper_i_alu_logical0__input_carry \oper_i_alu_logical0__input_carry - connect \oper_i_alu_logical0__invert_out \oper_i_alu_logical0__invert_out - connect \oper_i_alu_logical0__write_cr0 \oper_i_alu_logical0__write_cr0 - connect \oper_i_alu_logical0__output_carry \oper_i_alu_logical0__output_carry - connect \oper_i_alu_logical0__is_32bit \oper_i_alu_logical0__is_32bit - connect \oper_i_alu_logical0__is_signed \oper_i_alu_logical0__is_signed - connect \oper_i_alu_logical0__data_len \oper_i_alu_logical0__data_len - connect \oper_i_alu_logical0__insn \oper_i_alu_logical0__insn - connect \cu_issue_i \cu_issue_i$10 - connect \cu_busy_o \cu_busy_o$11 - connect \cu_rdmaskn_i \cu_rdmaskn_i$12 - connect \cu_rd__rel_o \cu_rd__rel_o$34 - connect \cu_rd__go_i \cu_rd__go_i$35 - connect \src1_i \src1_i$36 - connect \src2_i \src2_i$54 - connect \src3_i \src3_i$61 - connect \o_ok \o_ok$86 - connect \cu_wr__rel_o \cu_wr__rel_o$87 - connect \cu_wr__go_i \cu_wr__go_i$88 - connect \dest1_o \dest1_o$105 - connect \cr_a_ok \cr_a_ok$111 - connect \dest2_o \dest2_o$116 - connect \coresync_rst \coresync_rst - end - cell \spr0 \spr0 - connect \coresync_clk \coresync_clk - connect \oper_i_alu_spr0__insn_type \oper_i_alu_spr0__insn_type - connect \oper_i_alu_spr0__fn_unit \oper_i_alu_spr0__fn_unit - connect \oper_i_alu_spr0__insn \oper_i_alu_spr0__insn - connect \oper_i_alu_spr0__is_32bit \oper_i_alu_spr0__is_32bit - connect \cu_issue_i \cu_issue_i$13 - connect \cu_busy_o \cu_busy_o$14 - connect \cu_rdmaskn_i \cu_rdmaskn_i$15 - connect \cu_rd__rel_o \cu_rd__rel_o$37 - connect \cu_rd__go_i \cu_rd__go_i$38 - connect \src1_i \src1_i$39 - connect \src4_i \src4_i - connect \src6_i \src6_i - connect \src5_i \src5_i$66 - connect \src3_i \src3_i$76 - connect \src2_i \src2_i$79 - connect \o_ok \o_ok$89 - connect \cu_wr__rel_o \cu_wr__rel_o$90 - connect \cu_wr__go_i \cu_wr__go_i$91 - connect \dest1_o \dest1_o$106 - connect \xer_ca_ok \xer_ca_ok$120 - connect \dest6_o \dest6_o - connect \xer_ov_ok \xer_ov_ok$124 - connect \dest5_o \dest5_o - connect \xer_so_ok \xer_so_ok$129 - connect \dest4_o \dest4_o$133 - connect \fast1_ok \fast1_ok$139 - connect \dest3_o \dest3_o$143 - connect \spr1_ok \spr1_ok - connect \dest2_o \dest2_o$150 - connect \coresync_rst \coresync_rst - end - cell \div0 \div0 - connect \coresync_clk \coresync_clk - connect \oper_i_alu_div0__insn_type \oper_i_alu_div0__insn_type - connect \oper_i_alu_div0__fn_unit \oper_i_alu_div0__fn_unit - connect \oper_i_alu_div0__imm_data__data \oper_i_alu_div0__imm_data__data - connect \oper_i_alu_div0__imm_data__ok \oper_i_alu_div0__imm_data__ok - connect \oper_i_alu_div0__rc__rc \oper_i_alu_div0__rc__rc - connect \oper_i_alu_div0__rc__ok \oper_i_alu_div0__rc__ok - connect \oper_i_alu_div0__oe__oe \oper_i_alu_div0__oe__oe - connect \oper_i_alu_div0__oe__ok \oper_i_alu_div0__oe__ok - connect \oper_i_alu_div0__invert_in \oper_i_alu_div0__invert_in - connect \oper_i_alu_div0__zero_a \oper_i_alu_div0__zero_a - connect \oper_i_alu_div0__input_carry \oper_i_alu_div0__input_carry - connect \oper_i_alu_div0__invert_out \oper_i_alu_div0__invert_out - connect \oper_i_alu_div0__write_cr0 \oper_i_alu_div0__write_cr0 - connect \oper_i_alu_div0__output_carry \oper_i_alu_div0__output_carry - connect \oper_i_alu_div0__is_32bit \oper_i_alu_div0__is_32bit - connect \oper_i_alu_div0__is_signed \oper_i_alu_div0__is_signed - connect \oper_i_alu_div0__data_len \oper_i_alu_div0__data_len - connect \oper_i_alu_div0__insn \oper_i_alu_div0__insn - connect \cu_issue_i \cu_issue_i$16 - connect \cu_busy_o \cu_busy_o$17 - connect \cu_rdmaskn_i \cu_rdmaskn_i$18 - connect \cu_rd__rel_o \cu_rd__rel_o$40 - connect \cu_rd__go_i \cu_rd__go_i$41 - connect \src1_i \src1_i$42 - connect \src2_i \src2_i$55 - connect \src3_i \src3_i$62 - connect \o_ok \o_ok$92 - connect \cu_wr__rel_o \cu_wr__rel_o$93 - connect \cu_wr__go_i \cu_wr__go_i$94 - connect \dest1_o \dest1_o$107 - connect \cr_a_ok \cr_a_ok$112 - connect \dest2_o \dest2_o$117 - connect \xer_ov_ok \xer_ov_ok$125 - connect \dest3_o \dest3_o$127 - connect \xer_so_ok \xer_so_ok$130 - connect \dest4_o \dest4_o$134 - connect \coresync_rst \coresync_rst - end - cell \mul0 \mul0 - connect \coresync_clk \coresync_clk - connect \oper_i_alu_mul0__insn_type \oper_i_alu_mul0__insn_type - connect \oper_i_alu_mul0__fn_unit \oper_i_alu_mul0__fn_unit - connect \oper_i_alu_mul0__imm_data__data \oper_i_alu_mul0__imm_data__data - connect \oper_i_alu_mul0__imm_data__ok \oper_i_alu_mul0__imm_data__ok - connect \oper_i_alu_mul0__rc__rc \oper_i_alu_mul0__rc__rc - connect \oper_i_alu_mul0__rc__ok \oper_i_alu_mul0__rc__ok - connect \oper_i_alu_mul0__oe__oe \oper_i_alu_mul0__oe__oe - connect \oper_i_alu_mul0__oe__ok \oper_i_alu_mul0__oe__ok - connect \oper_i_alu_mul0__write_cr0 \oper_i_alu_mul0__write_cr0 - connect \oper_i_alu_mul0__is_32bit \oper_i_alu_mul0__is_32bit - connect \oper_i_alu_mul0__is_signed \oper_i_alu_mul0__is_signed - connect \oper_i_alu_mul0__insn \oper_i_alu_mul0__insn - connect \cu_issue_i \cu_issue_i$19 - connect \cu_busy_o \cu_busy_o$20 - connect \cu_rdmaskn_i \cu_rdmaskn_i$21 - connect \cu_rd__rel_o \cu_rd__rel_o$43 - connect \cu_rd__go_i \cu_rd__go_i$44 - connect \src1_i \src1_i$45 - connect \src2_i \src2_i$56 - connect \src3_i \src3_i$63 - connect \o_ok \o_ok$95 - connect \cu_wr__rel_o \cu_wr__rel_o$96 - connect \cu_wr__go_i \cu_wr__go_i$97 - connect \dest1_o \dest1_o$108 - connect \cr_a_ok \cr_a_ok$113 - connect \dest2_o \dest2_o$118 - connect \xer_ov_ok \xer_ov_ok$126 - connect \dest3_o \dest3_o$128 - connect \xer_so_ok \xer_so_ok$131 - connect \dest4_o \dest4_o$135 - connect \coresync_rst \coresync_rst - end - cell \shiftrot0 \shiftrot0 - connect \coresync_clk \coresync_clk - connect \oper_i_alu_shift_rot0__insn_type \oper_i_alu_shift_rot0__insn_type - connect \oper_i_alu_shift_rot0__fn_unit \oper_i_alu_shift_rot0__fn_unit - connect \oper_i_alu_shift_rot0__imm_data__data \oper_i_alu_shift_rot0__imm_data__data - connect \oper_i_alu_shift_rot0__imm_data__ok \oper_i_alu_shift_rot0__imm_data__ok - connect \oper_i_alu_shift_rot0__rc__rc \oper_i_alu_shift_rot0__rc__rc - connect \oper_i_alu_shift_rot0__rc__ok \oper_i_alu_shift_rot0__rc__ok - connect \oper_i_alu_shift_rot0__oe__oe \oper_i_alu_shift_rot0__oe__oe - connect \oper_i_alu_shift_rot0__oe__ok \oper_i_alu_shift_rot0__oe__ok - connect \oper_i_alu_shift_rot0__write_cr0 \oper_i_alu_shift_rot0__write_cr0 - connect \oper_i_alu_shift_rot0__input_carry \oper_i_alu_shift_rot0__input_carry - connect \oper_i_alu_shift_rot0__output_carry \oper_i_alu_shift_rot0__output_carry - connect \oper_i_alu_shift_rot0__input_cr \oper_i_alu_shift_rot0__input_cr - connect \oper_i_alu_shift_rot0__output_cr \oper_i_alu_shift_rot0__output_cr - connect \oper_i_alu_shift_rot0__is_32bit \oper_i_alu_shift_rot0__is_32bit - connect \oper_i_alu_shift_rot0__is_signed \oper_i_alu_shift_rot0__is_signed - connect \oper_i_alu_shift_rot0__insn \oper_i_alu_shift_rot0__insn - connect \cu_issue_i \cu_issue_i$22 - connect \cu_busy_o \cu_busy_o$23 - connect \cu_rdmaskn_i \cu_rdmaskn_i$24 - connect \cu_rd__rel_o \cu_rd__rel_o$46 - connect \cu_rd__go_i \cu_rd__go_i$47 - connect \src1_i \src1_i$48 - connect \src2_i \src2_i$57 - connect \src3_i \src3_i - connect \src4_i \src4_i$64 - connect \src5_i \src5_i - connect \o_ok \o_ok$98 - connect \cu_wr__rel_o \cu_wr__rel_o$99 - connect \cu_wr__go_i \cu_wr__go_i$100 - connect \dest1_o \dest1_o$109 - connect \cr_a_ok \cr_a_ok$114 - connect \dest2_o \dest2_o$119 - connect \xer_ca_ok \xer_ca_ok$121 - connect \dest3_o \dest3_o$123 - connect \coresync_rst \coresync_rst - end - cell \ldst0 \ldst0 - connect \coresync_clk \coresync_clk - connect \cu_st__rel_o \cu_st__rel_o - connect \cu_ad__go_i \cu_ad__go_i - connect \cu_ad__rel_o \cu_ad__rel_o - connect \cu_st__go_i \cu_st__go_i - connect \oper_i_ldst_ldst0__insn_type \oper_i_ldst_ldst0__insn_type - connect \oper_i_ldst_ldst0__fn_unit \oper_i_ldst_ldst0__fn_unit - connect \oper_i_ldst_ldst0__imm_data__data \oper_i_ldst_ldst0__imm_data__data - connect \oper_i_ldst_ldst0__imm_data__ok \oper_i_ldst_ldst0__imm_data__ok - connect \oper_i_ldst_ldst0__zero_a \oper_i_ldst_ldst0__zero_a - connect \oper_i_ldst_ldst0__rc__rc \oper_i_ldst_ldst0__rc__rc - connect \oper_i_ldst_ldst0__rc__ok \oper_i_ldst_ldst0__rc__ok - connect \oper_i_ldst_ldst0__oe__oe \oper_i_ldst_ldst0__oe__oe - connect \oper_i_ldst_ldst0__oe__ok \oper_i_ldst_ldst0__oe__ok - connect \oper_i_ldst_ldst0__is_32bit \oper_i_ldst_ldst0__is_32bit - connect \oper_i_ldst_ldst0__is_signed \oper_i_ldst_ldst0__is_signed - connect \oper_i_ldst_ldst0__data_len \oper_i_ldst_ldst0__data_len - connect \oper_i_ldst_ldst0__byte_reverse \oper_i_ldst_ldst0__byte_reverse - connect \oper_i_ldst_ldst0__sign_extend \oper_i_ldst_ldst0__sign_extend - connect \oper_i_ldst_ldst0__ldst_mode \oper_i_ldst_ldst0__ldst_mode - connect \oper_i_ldst_ldst0__insn \oper_i_ldst_ldst0__insn - connect \cu_issue_i \cu_issue_i$25 - connect \cu_busy_o \cu_busy_o$26 - connect \cu_rdmaskn_i \cu_rdmaskn_i$27 - connect \cu_rd__rel_o \cu_rd__rel_o$49 - connect \cu_rd__go_i \cu_rd__go_i$50 - connect \src1_i \src1_i$51 - connect \src2_i \src2_i$58 - connect \src3_i \src3_i$59 - connect \cu_wr__rel_o \cu_wr__rel_o$101 - connect \cu_wr__go_i \cu_wr__go_i$102 - connect \o \o - connect \ea \ea - connect \coresync_rst \coresync_rst - connect \ldst_port0_busy_o \ldst_port0_busy_o - connect \ldst_port0_is_ld_i \ldst_port0_is_ld_i - connect \ldst_port0_is_st_i \ldst_port0_is_st_i - connect \ldst_port0_data_len \ldst_port0_data_len - connect \ldst_port0_addr_i \ldst_port0_addr_i - connect \ldst_port0_addr_i_ok \ldst_port0_addr_i_ok - connect \ldst_port0_addr_exc_o \ldst_port0_addr_exc_o - connect \ldst_port0_addr_ok_o \ldst_port0_addr_ok_o - connect \ldst_port0_ld_data_o \ldst_port0_ld_data_o - connect \ldst_port0_ld_data_o_ok \ldst_port0_ld_data_o_ok - connect \ldst_port0_st_data_i \ldst_port0_st_data_i - connect \ldst_port0_st_data_i_ok \ldst_port0_st_data_i_ok - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.l0.pimem.st_active" -module \st_active - attribute \src "simple/issuer.py:141" - wire width 1 input 0 \coresync_clk - attribute \src "simple/issuer.py:141" - wire width 1 input 1 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 1 input 2 \r_st_active - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 1 input 3 \s_st_active - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire width 1 output 4 \q_st_active - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire width 1 \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire width 1 \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_st_active - connect \Y $1 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 1 $3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $4 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B $1 - connect \Y $3 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 1 $5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $6 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $3 - connect \B \s_st_active - connect \Y $5 - end - process $group_0 - assign \q_int$next \q_int - assign \q_int$next $5 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \q_int$next 1'0 - end - sync init - update \q_int 1'0 - sync posedge \coresync_clk - update \q_int \q_int$next - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 1 $7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $8 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_st_active - connect \Y $7 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 1 $9 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $10 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B $7 - connect \Y $9 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 1 $11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $12 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $9 - connect \B \s_st_active - connect \Y $11 - end - process $group_1 - assign \q_st_active 1'0 - assign \q_st_active $11 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" - wire width 1 \qn_st_active - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - wire width 1 $13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $14 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_st_active - connect \Y $13 - end - process $group_2 - assign \qn_st_active 1'0 - assign \qn_st_active $13 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" - wire width 1 \qlq_st_active - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - wire width 1 $15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $16 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_st_active - connect \B \q_int - connect \Y $15 - end - process $group_3 - assign \qlq_st_active 1'0 - assign \qlq_st_active $15 - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.l0.pimem.st_done" -module \st_done - attribute \src "simple/issuer.py:141" - wire width 1 input 0 \coresync_clk - attribute \src "simple/issuer.py:141" - wire width 1 input 1 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 1 input 2 \s_st_done - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 1 input 3 \r_st_done - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire width 1 output 4 \q_st_done - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire width 1 \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire width 1 \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_st_done - connect \Y $1 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 1 $3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $4 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B $1 - connect \Y $3 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 1 $5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $6 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $3 - connect \B \s_st_done - connect \Y $5 - end - process $group_0 - assign \q_int$next \q_int - assign \q_int$next $5 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \q_int$next 1'0 - end - sync init - update \q_int 1'0 - sync posedge \coresync_clk - update \q_int \q_int$next - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 1 $7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $8 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_st_done - connect \Y $7 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 1 $9 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $10 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B $7 - connect \Y $9 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 1 $11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $12 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $9 - connect \B \s_st_done - connect \Y $11 - end - process $group_1 - assign \q_st_done 1'0 - assign \q_st_done $11 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" - wire width 1 \qn_st_done - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - wire width 1 $13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $14 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_st_done - connect \Y $13 - end - process $group_2 - assign \qn_st_done 1'0 - assign \qn_st_done $13 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" - wire width 1 \qlq_st_done - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - wire width 1 $15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $16 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_st_done - connect \B \q_int - connect \Y $15 - end - process $group_3 - assign \qlq_st_done 1'0 - assign \qlq_st_done $15 - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.l0.pimem.ld_active" -module \ld_active - attribute \src "simple/issuer.py:141" - wire width 1 input 0 \coresync_clk - attribute \src "simple/issuer.py:141" - wire width 1 input 1 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 1 input 2 \r_ld_active - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 1 input 3 \s_ld_active - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire width 1 output 4 \q_ld_active - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire width 1 \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire width 1 \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_ld_active - connect \Y $1 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 1 $3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $4 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B $1 - connect \Y $3 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 1 $5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $6 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $3 - connect \B \s_ld_active - connect \Y $5 - end - process $group_0 - assign \q_int$next \q_int - assign \q_int$next $5 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \q_int$next 1'0 - end - sync init - update \q_int 1'0 - sync posedge \coresync_clk - update \q_int \q_int$next - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 1 $7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $8 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_ld_active - connect \Y $7 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 1 $9 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $10 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B $7 - connect \Y $9 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 1 $11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $12 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $9 - connect \B \s_ld_active - connect \Y $11 - end - process $group_1 - assign \q_ld_active 1'0 - assign \q_ld_active $11 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" - wire width 1 \qn_ld_active - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - wire width 1 $13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $14 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_ld_active - connect \Y $13 - end - process $group_2 - assign \qn_ld_active 1'0 - assign \qn_ld_active $13 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" - wire width 1 \qlq_ld_active - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - wire width 1 $15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $16 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_ld_active - connect \B \q_int - connect \Y $15 - end - process $group_3 - assign \qlq_ld_active 1'0 - assign \qlq_ld_active $15 - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.l0.pimem.reset_l" -module \reset_l - attribute \src "simple/issuer.py:141" - wire width 1 input 0 \coresync_clk - attribute \src "simple/issuer.py:141" - wire width 1 input 1 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 1 input 2 \s_reset - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 1 input 3 \r_reset - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire width 1 output 4 \q_reset - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire width 1 \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire width 1 \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_reset - connect \Y $1 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 1 $3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $4 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B $1 - connect \Y $3 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 1 $5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $6 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $3 - connect \B \s_reset - connect \Y $5 - end - process $group_0 - assign \q_int$next \q_int - assign \q_int$next $5 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \q_int$next 1'0 - end - sync init - update \q_int 1'0 - sync posedge \coresync_clk - update \q_int \q_int$next - end - process $group_1 - assign \q_reset 1'0 - assign \q_reset \q_int - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" - wire width 1 \qn_reset - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - wire width 1 $7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $8 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_reset - connect \Y $7 - end - process $group_2 - assign \qn_reset 1'0 - assign \qn_reset $7 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" - wire width 1 \qlq_reset - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - wire width 1 $9 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $10 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_reset - connect \B \q_int - connect \Y $9 - end - process $group_3 - assign \qlq_reset 1'0 - assign \qlq_reset $9 - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.l0.pimem.adrok_l" -module \adrok_l - attribute \src "simple/issuer.py:141" - wire width 1 input 0 \coresync_clk - attribute \src "simple/issuer.py:141" - wire width 1 input 1 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 1 input 2 \s_addr_acked - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 1 input 3 \r_addr_acked - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" - wire width 1 output 4 \qn_addr_acked - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire width 1 output 5 \q_addr_acked - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire width 1 \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire width 1 \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_addr_acked - connect \Y $1 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 1 $3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $4 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B $1 - connect \Y $3 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 1 $5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $6 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $3 - connect \B \s_addr_acked - connect \Y $5 - end - process $group_0 - assign \q_int$next \q_int - assign \q_int$next $5 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \q_int$next 1'0 - end - sync init - update \q_int 1'0 - sync posedge \coresync_clk - update \q_int \q_int$next - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 1 $7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $8 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_addr_acked - connect \Y $7 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 1 $9 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $10 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B $7 - connect \Y $9 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 1 $11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $12 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $9 - connect \B \s_addr_acked - connect \Y $11 - end - process $group_1 - assign \q_addr_acked 1'0 - assign \q_addr_acked $11 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - wire width 1 $13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $14 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_addr_acked - connect \Y $13 - end - process $group_2 - assign \qn_addr_acked 1'0 - assign \qn_addr_acked $13 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" - wire width 1 \qlq_addr_acked - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - wire width 1 $15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $16 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_addr_acked - connect \B \q_int - connect \Y $15 - end - process $group_3 - assign \qlq_addr_acked 1'0 - assign \qlq_addr_acked $15 - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.l0.pimem.busy_l" -module \busy_l - attribute \src "simple/issuer.py:141" - wire width 1 input 0 \coresync_clk - attribute \src "simple/issuer.py:141" - wire width 1 input 1 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 1 input 2 \s_busy - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 1 input 3 \r_busy - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire width 1 output 4 \q_busy - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire width 1 \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire width 1 \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_busy - connect \Y $1 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 1 $3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $4 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B $1 - connect \Y $3 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 1 $5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $6 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $3 - connect \B \s_busy - connect \Y $5 - end - process $group_0 - assign \q_int$next \q_int - assign \q_int$next $5 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \q_int$next 1'0 - end - sync init - update \q_int 1'0 - sync posedge \coresync_clk - update \q_int \q_int$next - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 1 $7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $8 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_busy - connect \Y $7 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 1 $9 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $10 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B $7 - connect \Y $9 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 1 $11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $12 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $9 - connect \B \s_busy - connect \Y $11 - end - process $group_1 - assign \q_busy 1'0 - assign \q_busy $11 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" - wire width 1 \qn_busy - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - wire width 1 $13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $14 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_busy - connect \Y $13 - end - process $group_2 - assign \qn_busy 1'0 - assign \qn_busy $13 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" - wire width 1 \qlq_busy - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - wire width 1 $15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $16 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_busy - connect \B \q_int - connect \Y $15 - end - process $group_3 - assign \qlq_busy 1'0 - assign \qlq_busy $15 - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.l0.pimem.cyc_l" -module \cyc_l - attribute \src "simple/issuer.py:141" - wire width 1 input 0 \coresync_clk - attribute \src "simple/issuer.py:141" - wire width 1 input 1 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 1 input 2 \s_cyc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 1 input 3 \r_cyc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire width 1 output 4 \q_cyc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire width 1 \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire width 1 \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_cyc - connect \Y $1 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 1 $3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $4 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B $1 - connect \Y $3 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 1 $5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $6 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $3 - connect \B \s_cyc - connect \Y $5 - end - process $group_0 - assign \q_int$next \q_int - assign \q_int$next $5 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \q_int$next 1'0 - end - sync init - update \q_int 1'0 - sync posedge \coresync_clk - update \q_int \q_int$next - end - process $group_1 - assign \q_cyc 1'0 - assign \q_cyc \q_int - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" - wire width 1 \qn_cyc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - wire width 1 $7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $8 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_cyc - connect \Y $7 - end - process $group_2 - assign \qn_cyc 1'0 - assign \qn_cyc $7 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" - wire width 1 \qlq_cyc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - wire width 1 $9 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $10 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_cyc - connect \B \q_int - connect \Y $9 - end - process $group_3 - assign \qlq_cyc 1'0 - assign \qlq_cyc $9 - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.l0.pimem.lenexp" -module \lenexp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:130" - wire width 4 input 0 \len_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:131" - wire width 4 input 1 \addr_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:132" - wire width 64 output 2 \lexp_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:134" - wire width 176 output 3 \rexp_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:148" - wire width 17 \binlen - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:150" - wire width 21 $1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:150" - wire width 20 $2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:150" - cell $sshl $3 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 20 - connect \A 5'00001 - connect \B \len_i - connect \Y $2 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:150" - wire width 21 $4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:150" - cell $sub $5 - parameter \A_SIGNED 0 - parameter \A_WIDTH 20 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 21 - connect \A $2 - connect \B 1'1 - connect \Y $4 - end - connect $1 $4 - process $group_0 - assign \binlen 17'00000000000000000 - assign \binlen $1 [16:0] - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:151" - wire width 64 $6 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:151" - wire width 32 $7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:151" - cell $sshl $8 - parameter \A_SIGNED 0 - parameter \A_WIDTH 17 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 32 - connect \A \binlen - connect \B \addr_i - connect \Y $7 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:151" - cell $pos $9 - parameter \A_SIGNED 0 - parameter \A_WIDTH 32 - parameter \Y_WIDTH 64 - connect \A $7 - connect \Y $6 - end - process $group_1 - assign \lexp_o 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \lexp_o $6 - sync init - end - process $group_2 - assign \rexp_o 176'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \rexp_o { { \lexp_o [63] \lexp_o [63] \lexp_o [63] \lexp_o [63] \lexp_o [63] \lexp_o [63] \lexp_o [63] \lexp_o [63] } { \lexp_o [62] \lexp_o [62] \lexp_o [62] \lexp_o [62] \lexp_o [62] \lexp_o [62] \lexp_o [62] \lexp_o [62] } { \lexp_o [61] \lexp_o [61] \lexp_o [61] \lexp_o [61] \lexp_o [61] \lexp_o [61] \lexp_o [61] \lexp_o [61] } { \lexp_o [60] \lexp_o [60] \lexp_o [60] \lexp_o [60] \lexp_o [60] \lexp_o [60] \lexp_o [60] \lexp_o [60] } { \lexp_o [59] \lexp_o [59] \lexp_o [59] \lexp_o [59] \lexp_o [59] \lexp_o [59] \lexp_o [59] \lexp_o [59] } { \lexp_o [58] \lexp_o [58] \lexp_o [58] \lexp_o [58] \lexp_o [58] \lexp_o [58] \lexp_o [58] \lexp_o [58] } { \lexp_o [57] \lexp_o [57] \lexp_o [57] \lexp_o [57] \lexp_o [57] \lexp_o [57] \lexp_o [57] \lexp_o [57] } { \lexp_o [56] \lexp_o [56] \lexp_o [56] \lexp_o [56] \lexp_o [56] \lexp_o [56] \lexp_o [56] \lexp_o [56] } { \lexp_o [55] \lexp_o [55] \lexp_o [55] \lexp_o [55] \lexp_o [55] \lexp_o [55] \lexp_o [55] \lexp_o [55] } { \lexp_o [54] \lexp_o [54] \lexp_o [54] \lexp_o [54] \lexp_o [54] \lexp_o [54] \lexp_o [54] \lexp_o [54] } { \lexp_o [53] \lexp_o [53] \lexp_o [53] \lexp_o [53] \lexp_o [53] \lexp_o [53] \lexp_o [53] \lexp_o [53] } { \lexp_o [52] \lexp_o [52] \lexp_o [52] \lexp_o [52] \lexp_o [52] \lexp_o [52] \lexp_o [52] \lexp_o [52] } { \lexp_o [51] \lexp_o [51] \lexp_o [51] \lexp_o [51] \lexp_o [51] \lexp_o [51] \lexp_o [51] \lexp_o [51] } { \lexp_o [50] \lexp_o [50] \lexp_o [50] \lexp_o [50] \lexp_o [50] \lexp_o [50] \lexp_o [50] \lexp_o [50] } { \lexp_o [49] \lexp_o [49] \lexp_o [49] \lexp_o [49] \lexp_o [49] \lexp_o [49] \lexp_o [49] \lexp_o [49] } { \lexp_o [48] \lexp_o [48] \lexp_o [48] \lexp_o [48] \lexp_o [48] \lexp_o [48] \lexp_o [48] \lexp_o [48] } { \lexp_o [47] \lexp_o [47] \lexp_o [47] \lexp_o [47] \lexp_o [47] \lexp_o [47] \lexp_o [47] \lexp_o [47] } { \lexp_o [46] \lexp_o [46] \lexp_o [46] \lexp_o [46] \lexp_o [46] \lexp_o [46] \lexp_o [46] \lexp_o [46] } { \lexp_o [45] \lexp_o [45] \lexp_o [45] \lexp_o [45] \lexp_o [45] \lexp_o [45] \lexp_o [45] \lexp_o [45] } { \lexp_o [44] \lexp_o [44] \lexp_o [44] \lexp_o [44] \lexp_o [44] \lexp_o [44] \lexp_o [44] \lexp_o [44] } { \lexp_o [43] \lexp_o [43] \lexp_o [43] \lexp_o [43] \lexp_o [43] \lexp_o [43] \lexp_o [43] \lexp_o [43] } { \lexp_o [42] \lexp_o [42] \lexp_o [42] \lexp_o [42] \lexp_o [42] \lexp_o [42] \lexp_o [42] \lexp_o [42] } { \lexp_o [41] \lexp_o [41] \lexp_o [41] \lexp_o [41] \lexp_o [41] \lexp_o [41] \lexp_o [41] \lexp_o [41] } { \lexp_o [40] \lexp_o [40] \lexp_o [40] \lexp_o [40] \lexp_o [40] \lexp_o [40] \lexp_o [40] \lexp_o [40] } { \lexp_o [39] \lexp_o [39] \lexp_o [39] \lexp_o [39] \lexp_o [39] \lexp_o [39] \lexp_o [39] \lexp_o [39] } { \lexp_o [38] \lexp_o [38] \lexp_o [38] \lexp_o [38] \lexp_o [38] \lexp_o [38] \lexp_o [38] \lexp_o [38] } { \lexp_o [37] \lexp_o [37] \lexp_o [37] \lexp_o [37] \lexp_o [37] \lexp_o [37] \lexp_o [37] \lexp_o [37] } { \lexp_o [36] \lexp_o [36] \lexp_o [36] \lexp_o [36] \lexp_o [36] \lexp_o [36] \lexp_o [36] \lexp_o [36] } { \lexp_o [35] \lexp_o [35] \lexp_o [35] \lexp_o [35] \lexp_o [35] \lexp_o [35] \lexp_o [35] \lexp_o [35] } { \lexp_o [34] \lexp_o [34] \lexp_o [34] \lexp_o [34] \lexp_o [34] \lexp_o [34] \lexp_o [34] \lexp_o [34] } { \lexp_o [33] \lexp_o [33] \lexp_o [33] \lexp_o [33] \lexp_o [33] \lexp_o [33] \lexp_o [33] \lexp_o [33] } { \lexp_o [32] \lexp_o [32] \lexp_o [32] \lexp_o [32] \lexp_o [32] \lexp_o [32] \lexp_o [32] \lexp_o [32] } { \lexp_o [31] \lexp_o [31] \lexp_o [31] \lexp_o [31] \lexp_o [31] \lexp_o [31] \lexp_o [31] \lexp_o [31] } { \lexp_o [30] \lexp_o [30] \lexp_o [30] \lexp_o [30] \lexp_o [30] \lexp_o [30] \lexp_o [30] \lexp_o [30] } { \lexp_o [29] \lexp_o [29] \lexp_o [29] \lexp_o [29] \lexp_o [29] \lexp_o [29] \lexp_o [29] \lexp_o [29] } { \lexp_o [28] \lexp_o [28] \lexp_o [28] \lexp_o [28] \lexp_o [28] \lexp_o [28] \lexp_o [28] \lexp_o [28] } { \lexp_o [27] \lexp_o [27] \lexp_o [27] \lexp_o [27] \lexp_o [27] \lexp_o [27] \lexp_o [27] \lexp_o [27] } { \lexp_o [26] \lexp_o [26] \lexp_o [26] \lexp_o [26] \lexp_o [26] \lexp_o [26] \lexp_o [26] \lexp_o [26] } { \lexp_o [25] \lexp_o [25] \lexp_o [25] \lexp_o [25] \lexp_o [25] \lexp_o [25] \lexp_o [25] \lexp_o [25] } { \lexp_o [24] \lexp_o [24] \lexp_o [24] \lexp_o [24] \lexp_o [24] \lexp_o [24] \lexp_o [24] \lexp_o [24] } { \lexp_o [23] \lexp_o [23] \lexp_o [23] \lexp_o [23] \lexp_o [23] \lexp_o [23] \lexp_o [23] \lexp_o [23] } { \lexp_o [22] \lexp_o [22] \lexp_o [22] \lexp_o [22] \lexp_o [22] \lexp_o [22] \lexp_o [22] \lexp_o [22] } { \lexp_o [21] \lexp_o [21] \lexp_o [21] \lexp_o [21] \lexp_o [21] \lexp_o [21] \lexp_o [21] \lexp_o [21] } { \lexp_o [20] \lexp_o [20] \lexp_o [20] \lexp_o [20] \lexp_o [20] \lexp_o [20] \lexp_o [20] \lexp_o [20] } { \lexp_o [19] \lexp_o [19] \lexp_o [19] \lexp_o [19] \lexp_o [19] \lexp_o [19] \lexp_o [19] \lexp_o [19] } { \lexp_o [18] \lexp_o [18] \lexp_o [18] \lexp_o [18] \lexp_o [18] \lexp_o [18] \lexp_o [18] \lexp_o [18] } { \lexp_o [17] \lexp_o [17] \lexp_o [17] \lexp_o [17] \lexp_o [17] \lexp_o [17] \lexp_o [17] \lexp_o [17] } { \lexp_o [16] \lexp_o [16] \lexp_o [16] \lexp_o [16] \lexp_o [16] \lexp_o [16] \lexp_o [16] \lexp_o [16] } { \lexp_o [15] \lexp_o [15] \lexp_o [15] \lexp_o [15] \lexp_o [15] \lexp_o [15] \lexp_o [15] \lexp_o [15] } { \lexp_o [14] \lexp_o [14] \lexp_o [14] \lexp_o [14] \lexp_o [14] \lexp_o [14] \lexp_o [14] \lexp_o [14] } { \lexp_o [13] \lexp_o [13] \lexp_o [13] \lexp_o [13] \lexp_o [13] \lexp_o [13] \lexp_o [13] \lexp_o [13] } { \lexp_o [12] \lexp_o [12] \lexp_o [12] \lexp_o [12] \lexp_o [12] \lexp_o [12] \lexp_o [12] \lexp_o [12] } { \lexp_o [11] \lexp_o [11] \lexp_o [11] \lexp_o [11] \lexp_o [11] \lexp_o [11] \lexp_o [11] \lexp_o [11] } { \lexp_o [10] \lexp_o [10] \lexp_o [10] \lexp_o [10] \lexp_o [10] \lexp_o [10] \lexp_o [10] \lexp_o [10] } { \lexp_o [9] \lexp_o [9] \lexp_o [9] \lexp_o [9] \lexp_o [9] \lexp_o [9] \lexp_o [9] \lexp_o [9] } { \lexp_o [8] \lexp_o [8] \lexp_o [8] \lexp_o [8] \lexp_o [8] \lexp_o [8] \lexp_o [8] \lexp_o [8] } { \lexp_o [7] \lexp_o [7] \lexp_o [7] \lexp_o [7] \lexp_o [7] \lexp_o [7] \lexp_o [7] \lexp_o [7] } { \lexp_o [6] \lexp_o [6] \lexp_o [6] \lexp_o [6] \lexp_o [6] \lexp_o [6] \lexp_o [6] \lexp_o [6] } { \lexp_o [5] \lexp_o [5] \lexp_o [5] \lexp_o [5] \lexp_o [5] \lexp_o [5] \lexp_o [5] \lexp_o [5] } { \lexp_o [4] \lexp_o [4] \lexp_o [4] \lexp_o [4] \lexp_o [4] \lexp_o [4] \lexp_o [4] \lexp_o [4] } { \lexp_o [3] \lexp_o [3] \lexp_o [3] \lexp_o [3] \lexp_o [3] \lexp_o [3] \lexp_o [3] \lexp_o [3] } { \lexp_o [2] \lexp_o [2] \lexp_o [2] \lexp_o [2] \lexp_o [2] \lexp_o [2] \lexp_o [2] \lexp_o [2] } { \lexp_o [1] \lexp_o [1] \lexp_o [1] \lexp_o [1] \lexp_o [1] \lexp_o [1] \lexp_o [1] \lexp_o [1] } { \lexp_o [0] \lexp_o [0] \lexp_o [0] \lexp_o [0] \lexp_o [0] \lexp_o [0] \lexp_o [0] \lexp_o [0] } } [175:0] - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.l0.pimem.valid_l" -module \valid_l - attribute \src "simple/issuer.py:141" - wire width 1 input 0 \coresync_clk - attribute \src "simple/issuer.py:141" - wire width 1 input 1 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 1 input 2 \s_valid - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire width 1 output 3 \q_valid - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 1 input 4 \r_valid - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire width 1 \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire width 1 \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_valid - connect \Y $1 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 1 $3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $4 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B $1 - connect \Y $3 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 1 $5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $6 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $3 - connect \B \s_valid - connect \Y $5 - end - process $group_0 - assign \q_int$next \q_int - assign \q_int$next $5 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \q_int$next 1'0 - end - sync init - update \q_int 1'0 - sync posedge \coresync_clk - update \q_int \q_int$next - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 1 $7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $8 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_valid - connect \Y $7 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 1 $9 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $10 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B $7 - connect \Y $9 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 1 $11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $12 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $9 - connect \B \s_valid - connect \Y $11 - end - process $group_1 - assign \q_valid 1'0 - assign \q_valid $11 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" - wire width 1 \qn_valid - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - wire width 1 $13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $14 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_valid - connect \Y $13 - end - process $group_2 - assign \qn_valid 1'0 - assign \qn_valid $13 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" - wire width 1 \qlq_valid - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - wire width 1 $15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $16 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_valid - connect \B \q_int - connect \Y $15 - end - process $group_3 - assign \qlq_valid 1'0 - assign \qlq_valid $15 - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.l0.pimem" -module \pimem - attribute \src "simple/issuer.py:141" - wire width 1 input 0 \coresync_clk - attribute \src "simple/issuer.py:141" - wire width 1 input 1 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:98" - wire width 1 input 2 \ldst_port0_is_ld_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:99" - wire width 1 input 3 \ldst_port0_is_st_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:105" - wire width 1 output 4 \ldst_port0_busy_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:102" - wire width 4 input 5 \ldst_port0_data_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 48 input 6 \ldst_port0_addr_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 input 7 \ldst_port0_addr_i_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:44" - wire width 8 output 8 \x_mask_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:43" - wire width 48 output 9 \x_addr_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:109" - wire width 1 output 10 \ldst_port0_addr_ok_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:62" - wire width 64 input 11 \m_ld_data_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 output 12 \ldst_port0_ld_data_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 13 \ldst_port0_ld_data_o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 input 14 \ldst_port0_st_data_i_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 input 15 \ldst_port0_st_data_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:47" - wire width 64 output 16 \x_st_data_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:59" - wire width 1 input 17 \x_busy_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:110" - wire width 1 input 18 \ldst_port0_addr_exc_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:45" - wire width 1 output 19 \x_ld_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:46" - wire width 1 output 20 \x_st_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:54" - wire width 1 output 21 \m_valid_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:50" - wire width 1 output 22 \x_valid_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 1 \st_active_r_st_active - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 1 \st_active_s_st_active - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire width 1 \st_active_q_st_active - cell \st_active \st_active - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \r_st_active \st_active_r_st_active - connect \s_st_active \st_active_s_st_active - connect \q_st_active \st_active_q_st_active - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 1 \st_done_s_st_done - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 1 \st_done_s_st_done$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 1 \st_done_r_st_done - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire width 1 \st_done_q_st_done - cell \st_done \st_done - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \s_st_done \st_done_s_st_done - connect \r_st_done \st_done_r_st_done - connect \q_st_done \st_done_q_st_done - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 1 \ld_active_r_ld_active - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 1 \ld_active_s_ld_active - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire width 1 \ld_active_q_ld_active - cell \ld_active \ld_active - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \r_ld_active \ld_active_r_ld_active - connect \s_ld_active \ld_active_s_ld_active - connect \q_ld_active \ld_active_q_ld_active - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 1 \reset_l_s_reset - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 1 \reset_l_r_reset - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire width 1 \reset_l_q_reset - cell \reset_l \reset_l - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \s_reset \reset_l_s_reset - connect \r_reset \reset_l_r_reset - connect \q_reset \reset_l_q_reset - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 1 \adrok_l_s_addr_acked - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 1 \adrok_l_s_addr_acked$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 1 \adrok_l_r_addr_acked - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" - wire width 1 \adrok_l_qn_addr_acked - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire width 1 \adrok_l_q_addr_acked - cell \adrok_l \adrok_l - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \s_addr_acked \adrok_l_s_addr_acked - connect \r_addr_acked \adrok_l_r_addr_acked - connect \qn_addr_acked \adrok_l_qn_addr_acked - connect \q_addr_acked \adrok_l_q_addr_acked - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 1 \busy_l_s_busy - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 1 \busy_l_r_busy - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire width 1 \busy_l_q_busy - cell \busy_l \busy_l - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \s_busy \busy_l_s_busy - connect \r_busy \busy_l_r_busy - connect \q_busy \busy_l_q_busy - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 1 \cyc_l_s_cyc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 1 \cyc_l_r_cyc - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire width 1 \cyc_l_q_cyc - cell \cyc_l \cyc_l - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \s_cyc \cyc_l_s_cyc - connect \r_cyc \cyc_l_r_cyc - connect \q_cyc \cyc_l_q_cyc - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:130" - wire width 4 \lenexp_len_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:131" - wire width 4 \lenexp_addr_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:132" - wire width 64 \lenexp_lexp_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/scoreboard/addr_match.py:134" - wire width 176 \lenexp_rexp_o - cell \lenexp \lenexp - connect \len_i \lenexp_len_i - connect \addr_i \lenexp_addr_i - connect \lexp_o \lenexp_lexp_o - connect \rexp_o \lenexp_rexp_o - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 1 \valid_l_s_valid - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire width 1 \valid_l_q_valid - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 1 \valid_l_r_valid - cell \valid_l \valid_l - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \s_valid \valid_l_s_valid - connect \q_valid \valid_l_q_valid - connect \r_valid \valid_l_r_valid - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:250" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:250" - cell $and $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \st_active_q_st_active - connect \B \ldst_port0_st_data_i_ok - connect \Y $1 - end - process $group_0 - assign \st_done_s_st_done$next \st_done_s_st_done - assign \st_done_s_st_done$next 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:250" - switch { $1 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:250" - case 1'1 - assign \st_done_s_st_done$next 1'1 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \st_done_s_st_done$next 1'0 - end - sync init - update \st_done_s_st_done 1'0 - sync posedge \coresync_clk - update \st_done_s_st_done \st_done_s_st_done$next - end - process $group_1 - assign \st_done_r_st_done 1'1 - assign \st_done_r_st_done 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:269" - switch { \reset_l_q_reset } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:269" - case 1'1 - assign \st_done_r_st_done 1'1 - end - sync init - end - process $group_2 - assign \st_active_r_st_active 1'1 - assign \st_active_r_st_active 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:269" - switch { \reset_l_q_reset } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:269" - case 1'1 - assign \st_active_r_st_active 1'1 - end - sync init - end - process $group_3 - assign \ld_active_r_ld_active 1'1 - assign \ld_active_r_ld_active 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:269" - switch { \reset_l_q_reset } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:269" - case 1'1 - assign \ld_active_r_ld_active 1'1 - end - sync init - end - process $group_4 - assign \cyc_l_s_cyc 1'0 - assign \cyc_l_s_cyc 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:282" - switch { \reset_l_s_reset } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:282" - case 1'1 - assign \cyc_l_s_cyc 1'1 - end - sync init - end - process $group_5 - assign \cyc_l_r_cyc 1'1 - assign \cyc_l_r_cyc 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:285" - switch { \cyc_l_q_cyc } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:285" - case 1'1 - assign \cyc_l_r_cyc 1'1 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:206" - wire width 1 $3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:206" - cell $or $4 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \ldst_port0_is_ld_i - connect \B \ldst_port0_is_st_i - connect \Y $3 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:207" - wire width 1 $5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:196" - wire width 1 \busy_delay - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:196" - wire width 1 \busy_delay$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:207" - cell $not $6 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \busy_delay - connect \Y $5 - end - process $group_6 - assign \busy_l_s_busy 1'0 - assign \busy_l_s_busy 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:206" - switch { $3 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:206" - case 1'1 - assign \busy_l_s_busy $5 - end - sync init - end - process $group_7 - assign \busy_l_r_busy 1'1 - assign \busy_l_r_busy 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:277" - switch { \ldst_port0_addr_exc_o } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:277" - case 1'1 - assign \busy_l_r_busy 1'1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:285" - switch { \cyc_l_q_cyc } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:285" - case 1'1 - assign \busy_l_r_busy 1'1 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:216" - wire width 1 $7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:216" - cell $and $8 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \ldst_port0_addr_i_ok - connect \B \adrok_l_qn_addr_acked - connect \Y $7 - end - process $group_8 - assign \adrok_l_s_addr_acked$next \adrok_l_s_addr_acked - assign \adrok_l_s_addr_acked$next 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:211" - switch { \ld_active_q_ld_active } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:211" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:216" - switch { $7 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:216" - case 1'1 - assign \adrok_l_s_addr_acked$next 1'1 - end - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:223" - switch { \st_active_q_st_active } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:223" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:228" - switch { \ldst_port0_addr_i_ok } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:228" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:230" - switch { \adrok_l_qn_addr_acked } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:230" - case 1'1 - assign \adrok_l_s_addr_acked$next 1'1 - end - end - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \adrok_l_s_addr_acked$next 1'0 - end - sync init - update \adrok_l_s_addr_acked 1'0 - sync posedge \coresync_clk - update \adrok_l_s_addr_acked \adrok_l_s_addr_acked$next - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:263" - wire width 1 \reset_delay - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:263" - wire width 1 \reset_delay$next - process $group_9 - assign \adrok_l_r_addr_acked 1'1 - assign \adrok_l_r_addr_acked 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:265" - switch { \reset_delay } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:265" - case 1'1 - assign \adrok_l_r_addr_acked 1'1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:269" - switch { \reset_l_q_reset } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:269" - case 1'1 - assign \adrok_l_r_addr_acked 1'1 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:189" - wire width 1 \lds - process $group_10 - assign \lds 1'0 - assign \lds \ldst_port0_is_ld_i - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:190" - wire width 1 \sts - process $group_11 - assign \sts 1'0 - assign \sts \ldst_port0_is_st_i - sync init - end - process $group_12 - assign \busy_delay$next \busy_delay - assign \busy_delay$next \ldst_port0_busy_o - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \busy_delay$next 1'0 - end - sync init - update \busy_delay 1'0 - sync posedge \coresync_clk - update \busy_delay \busy_delay$next - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:197" - wire width 1 \busy_edge - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:199" - wire width 1 $9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:199" - cell $not $10 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \busy_delay - connect \Y $9 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:199" - wire width 1 $11 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:199" - cell $and $12 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \ldst_port0_busy_o - connect \B $9 - connect \Y $11 - end - process $group_13 - assign \busy_edge 1'0 - assign \busy_edge $11 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire width 1 \lds_dly - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire width 1 \lds_dly$next - process $group_14 - assign \lds_dly$next \lds_dly - assign \lds_dly$next \lds - sync init - update \lds_dly 1'0 - sync posedge \coresync_clk - update \lds_dly \lds_dly$next - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" - wire width 1 \lds_rise - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - wire width 1 $13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $not $14 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \lds_dly - connect \Y $13 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - wire width 1 $15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $and $16 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \lds - connect \B $13 - connect \Y $15 - end - process $group_15 - assign \lds_rise 1'0 - assign \lds_rise $15 - sync init - end - process $group_16 - assign \ld_active_s_ld_active 1'0 - assign \ld_active_s_ld_active \lds_rise - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire width 1 \sts_dly - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire width 1 \sts_dly$next - process $group_17 - assign \sts_dly$next \sts_dly - assign \sts_dly$next \sts - sync init - update \sts_dly 1'0 - sync posedge \coresync_clk - update \sts_dly \sts_dly$next - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" - wire width 1 \sts_rise - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - wire width 1 $17 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $not $18 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \sts_dly - connect \Y $17 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - wire width 1 $19 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $and $20 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \sts - connect \B $17 - connect \Y $19 - end - process $group_18 - assign \sts_rise 1'0 - assign \sts_rise $19 - sync init - end - process $group_19 - assign \st_active_s_st_active 1'0 - assign \st_active_s_st_active \sts_rise - sync init - end - process $group_20 - assign \lenexp_len_i 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:211" - switch { \ld_active_q_ld_active } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:211" - case 1'1 - assign \lenexp_len_i \ldst_port0_data_len - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:223" - switch { \st_active_q_st_active } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:223" - case 1'1 - assign \lenexp_len_i \ldst_port0_data_len - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:265" - wire width 4 $21 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:265" - cell $pos $22 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 4 - connect \A \ldst_port0_addr_i [2:0] - connect \Y $21 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:265" - wire width 4 $23 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/ast.py:265" - cell $pos $24 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 4 - connect \A \ldst_port0_addr_i [2:0] - connect \Y $23 - end - process $group_21 - assign \lenexp_addr_i 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:211" - switch { \ld_active_q_ld_active } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:211" - case 1'1 - assign \lenexp_addr_i $21 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:223" - switch { \st_active_q_st_active } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:223" - case 1'1 - assign \lenexp_addr_i $23 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:216" - wire width 1 $25 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:216" - cell $and $26 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \ldst_port0_addr_i_ok - connect \B \adrok_l_qn_addr_acked - connect \Y $25 - end - process $group_22 - assign \valid_l_s_valid 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:211" - switch { \ld_active_q_ld_active } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:211" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:216" - switch { $25 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:216" - case 1'1 - assign \valid_l_s_valid 1'1 - end - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:223" - switch { \st_active_q_st_active } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:223" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:228" - switch { \ldst_port0_addr_i_ok } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:228" - case 1'1 - assign \valid_l_s_valid 1'1 - end - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:216" - wire width 1 $27 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:216" - cell $and $28 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \ldst_port0_addr_i_ok - connect \B \adrok_l_qn_addr_acked - connect \Y $27 - end - process $group_23 - assign \x_mask_i 8'00000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:211" - switch { \ld_active_q_ld_active } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:211" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:216" - switch { $27 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:216" - case 1'1 - assign \x_mask_i \lenexp_lexp_o [7:0] - end - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:223" - switch { \st_active_q_st_active } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:223" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:228" - switch { \ldst_port0_addr_i_ok } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:228" - case 1'1 - assign \x_mask_i \lenexp_lexp_o [7:0] - end - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:216" - wire width 1 $29 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:216" - cell $and $30 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \ldst_port0_addr_i_ok - connect \B \adrok_l_qn_addr_acked - connect \Y $29 - end - process $group_24 - assign \x_addr_i 48'000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:211" - switch { \ld_active_q_ld_active } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:211" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:216" - switch { $29 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:216" - case 1'1 - assign \x_addr_i \ldst_port0_addr_i - end - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:223" - switch { \st_active_q_st_active } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:223" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:228" - switch { \ldst_port0_addr_i_ok } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:228" - case 1'1 - assign \x_addr_i \ldst_port0_addr_i - end - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:216" - wire width 1 $31 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:216" - cell $and $32 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \ldst_port0_addr_i_ok - connect \B \adrok_l_qn_addr_acked - connect \Y $31 - end - process $group_25 - assign \ldst_port0_addr_ok_o 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:211" - switch { \ld_active_q_ld_active } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:211" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:216" - switch { $31 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:216" - case 1'1 - assign \ldst_port0_addr_ok_o 1'1 - end - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:223" - switch { \st_active_q_st_active } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:223" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:228" - switch { \ldst_port0_addr_i_ok } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:228" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:230" - switch { \adrok_l_qn_addr_acked } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:230" - case 1'1 - assign \ldst_port0_addr_ok_o 1'1 - end - end - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:242" - wire width 1 $33 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:242" - cell $and $34 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \ld_active_q_ld_active - connect \B \adrok_l_q_addr_acked - connect \Y $33 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:64" - wire width 1 $35 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:46" - wire width 1 \lsui_busy - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:64" - cell $not $36 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \lsui_busy - connect \Y $35 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:61" - wire width 1 $37 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:61" - wire width 1 $38 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:61" - cell $or $39 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \x_busy_o - connect \B \lsui_busy - connect \Y $38 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:61" - cell $not $40 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $38 - connect \Y $37 - end - process $group_26 - assign \reset_l_s_reset 1'0 - assign \reset_l_s_reset 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:242" - switch { $33 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:242" - case 1'1 - assign \reset_l_s_reset $35 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:259" - switch { \st_done_q_st_done } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:259" - case 1'1 - assign \reset_l_s_reset $37 - end - sync init - end - process $group_27 - assign \reset_l_r_reset 1'1 - assign \reset_l_r_reset 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:269" - switch { \reset_l_q_reset } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:269" - case 1'1 - assign \reset_l_r_reset 1'1 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:238" - wire width 64 \lddata - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:241" - wire width 176 $41 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:240" - wire width 176 $42 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:240" - cell $and $43 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \B_SIGNED 0 - parameter \B_WIDTH 176 - parameter \Y_WIDTH 176 - connect \A \m_ld_data_o - connect \B \lenexp_rexp_o - connect \Y $42 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:241" - wire width 8 $44 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:241" - cell $mul $45 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 8 - connect \A \lenexp_addr_i - connect \B 4'1000 - connect \Y $44 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:241" - wire width 176 $46 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:241" - cell $sshr $47 - parameter \A_SIGNED 0 - parameter \A_WIDTH 176 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 176 - connect \A $42 - connect \B $44 - connect \Y $46 - end - connect $41 $46 - process $group_28 - assign \lddata 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \lddata $41 [63:0] - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:242" - wire width 1 $48 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:242" - cell $and $49 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \ld_active_q_ld_active - connect \B \adrok_l_q_addr_acked - connect \Y $48 - end - process $group_29 - assign \ldst_port0_ld_data_o 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:242" - switch { $48 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:242" - case 1'1 - assign \ldst_port0_ld_data_o \lddata - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:242" - wire width 1 $50 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:242" - cell $and $51 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \ld_active_q_ld_active - connect \B \adrok_l_q_addr_acked - connect \Y $50 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:64" - wire width 1 $52 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:64" - cell $not $53 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \lsui_busy - connect \Y $52 - end - process $group_30 - assign \ldst_port0_ld_data_o_ok 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:242" - switch { $50 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:242" - case 1'1 - assign \ldst_port0_ld_data_o_ok $52 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:253" - wire width 64 \stdata - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:250" - wire width 1 $54 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:250" - cell $and $55 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \st_active_q_st_active - connect \B \ldst_port0_st_data_i_ok - connect \Y $54 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:254" - wire width 319 $56 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:254" - wire width 8 $57 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:254" - cell $mul $58 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 8 - connect \A \lenexp_addr_i - connect \B 4'1000 - connect \Y $57 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:254" - wire width 319 $59 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:254" - cell $sshl $60 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 319 - connect \A \ldst_port0_st_data_i - connect \B $57 - connect \Y $59 - end - connect $56 $59 - process $group_31 - assign \stdata 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:250" - switch { $54 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:250" - case 1'1 - assign \stdata $56 [63:0] - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:250" - wire width 1 $61 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:250" - cell $and $62 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \st_active_q_st_active - connect \B \ldst_port0_st_data_i_ok - connect \Y $61 - end - process $group_32 - assign \x_st_data_i 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:250" - switch { $61 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:250" - case 1'1 - assign \x_st_data_i \stdata - end - sync init - end - process $group_33 - assign \reset_delay$next \reset_delay - assign \reset_delay$next \reset_l_q_reset - sync init - update \reset_delay 1'0 - sync posedge \coresync_clk - update \reset_delay \reset_delay$next - end - process $group_34 - assign \ldst_port0_busy_o 1'0 - assign \ldst_port0_busy_o \busy_l_q_busy - sync init - end - process $group_35 - assign \x_ld_i 1'0 - assign \x_ld_i \ldst_port0_is_ld_i - sync init - end - process $group_36 - assign \x_st_i 1'0 - assign \x_st_i \ldst_port0_is_st_i - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:85" - wire width 2 \fsm_state - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:85" - wire width 2 \fsm_state$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:88" - wire width 1 $63 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:88" - cell $or $64 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \ldst_port0_is_ld_i - connect \B \ldst_port0_is_st_i - connect \Y $63 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:88" - wire width 1 $65 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:88" - cell $and $66 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $63 - connect \B \valid_l_q_valid - connect \Y $65 - end - process $group_37 - assign \lsui_busy 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:85" - switch \fsm_state - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:86" - attribute \nmigen.decoding "IDLE/0" - case 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:88" - switch { $65 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:88" - case 1'1 - assign \lsui_busy 1'1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:91" - attribute \nmigen.decoding "BUSY/1" - case 2'01 - assign \lsui_busy 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:97" - attribute \nmigen.decoding "WAITDEASSERT/2" - case 2'10 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:88" - wire width 1 $67 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:88" - cell $or $68 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \ldst_port0_is_ld_i - connect \B \ldst_port0_is_st_i - connect \Y $67 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:88" - wire width 1 $69 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:88" - cell $and $70 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $67 - connect \B \valid_l_q_valid - connect \Y $69 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:95" - wire width 1 $71 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:95" - cell $not $72 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \x_busy_o - connect \Y $71 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:99" - wire width 1 $73 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:99" - cell $not $74 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \ldst_port0_is_st_i - connect \Y $73 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:99" - wire width 1 $75 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:99" - cell $not $76 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \ldst_port0_busy_o - connect \Y $75 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:99" - wire width 1 $77 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:99" - cell $and $78 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $73 - connect \B $75 - connect \Y $77 - end - process $group_38 - assign \fsm_state$next \fsm_state - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:85" - switch \fsm_state - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:86" - attribute \nmigen.decoding "IDLE/0" - case 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:88" - switch { $69 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:88" - case 1'1 - assign \fsm_state$next 2'01 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:91" - attribute \nmigen.decoding "BUSY/1" - case 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:95" - switch { $71 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:95" - case 1'1 - assign \fsm_state$next 2'10 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:97" - attribute \nmigen.decoding "WAITDEASSERT/2" - case 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:99" - switch { $77 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:99" - case 1'1 - assign \fsm_state$next 2'00 - end - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \fsm_state$next 2'00 - end - sync init - update \fsm_state 2'00 - sync posedge \coresync_clk - update \fsm_state \fsm_state$next - end - process $group_39 - assign \m_valid_i 1'0 - assign \m_valid_i \valid_l_q_valid - sync init - end - process $group_40 - assign \x_valid_i 1'0 - assign \x_valid_i \valid_l_q_valid - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:107" - wire width 1 \lsui_active - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:108" - wire width 1 $79 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pi2ls.py:108" - cell $not $80 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \x_busy_o - connect \Y $79 - end - process $group_41 - assign \lsui_active 1'0 - assign \lsui_active $79 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire width 1 \lsui_active_dly - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire width 1 \lsui_active_dly$next - process $group_42 - assign \lsui_active_dly$next \lsui_active_dly - assign \lsui_active_dly$next \lsui_active - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \lsui_active_dly$next 1'0 - end - sync init - update \lsui_active_dly 1'0 - sync posedge \coresync_clk - update \lsui_active_dly \lsui_active_dly$next - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" - wire width 1 \lsui_active_rise - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - wire width 1 $81 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $not $82 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \lsui_active_dly - connect \Y $81 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - wire width 1 $83 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $and $84 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \lsui_active - connect \B $81 - connect \Y $83 - end - process $group_43 - assign \lsui_active_rise 1'0 - assign \lsui_active_rise $83 - sync init - end - process $group_44 - assign \valid_l_r_valid 1'1 - assign \valid_l_r_valid \lsui_active_rise - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.l0.l0.idx_l" -module \idx_l - attribute \src "simple/issuer.py:141" - wire width 1 input 0 \coresync_clk - attribute \src "simple/issuer.py:141" - wire width 1 input 1 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire width 1 output 2 \q_idx_l - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 1 input 3 \s_idx_l - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 1 input 4 \r_idx_l - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire width 1 \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire width 1 \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_idx_l - connect \Y $1 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 1 $3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $4 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B $1 - connect \Y $3 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 1 $5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $6 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $3 - connect \B \s_idx_l - connect \Y $5 - end - process $group_0 - assign \q_int$next \q_int - assign \q_int$next $5 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \q_int$next 1'0 - end - sync init - update \q_int 1'0 - sync posedge \coresync_clk - update \q_int \q_int$next - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 1 $7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $not $8 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_idx_l - connect \Y $7 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 1 $9 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $and $10 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B $7 - connect \Y $9 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - wire width 1 $11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:72" - cell $or $12 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $9 - connect \B \s_idx_l - connect \Y $11 - end - process $group_1 - assign \q_idx_l 1'0 - assign \q_idx_l $11 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" - wire width 1 \qn_idx_l - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - wire width 1 $13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $14 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_idx_l - connect \Y $13 - end - process $group_2 - assign \qn_idx_l 1'0 - assign \qn_idx_l $13 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" - wire width 1 \qlq_idx_l - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - wire width 1 $15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $16 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_idx_l - connect \B \q_int - connect \Y $15 - end - process $group_3 - assign \qlq_idx_l 1'0 - assign \qlq_idx_l $15 - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.l0.l0.reset_l" -module \reset_l$128 - attribute \src "simple/issuer.py:141" - wire width 1 input 0 \coresync_clk - attribute \src "simple/issuer.py:141" - wire width 1 input 1 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 1 input 2 \s_reset - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 1 input 3 \r_reset - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire width 1 output 4 \q_reset - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire width 1 \q_int - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:66" - wire width 1 \q_int$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $not $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \r_reset - connect \Y $1 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 1 $3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $and $4 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_int - connect \B $1 - connect \Y $3 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - wire width 1 $5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:68" - cell $or $6 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $3 - connect \B \s_reset - connect \Y $5 - end - process $group_0 - assign \q_int$next \q_int - assign \q_int$next $5 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \q_int$next 1'0 - end - sync init - update \q_int 1'0 - sync posedge \coresync_clk - update \q_int \q_int$next - end - process $group_1 - assign \q_reset 1'0 - assign \q_reset \q_int - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:61" - wire width 1 \qn_reset - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - wire width 1 $7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:73" - cell $not $8 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_reset - connect \Y $7 - end - process $group_2 - assign \qn_reset 1'0 - assign \qn_reset $7 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:62" - wire width 1 \qlq_reset - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - wire width 1 $9 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:74" - cell $or $10 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \q_reset - connect \B \q_int - connect \Y $9 - end - process $group_3 - assign \qlq_reset 1'0 - assign \qlq_reset $9 - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.l0.l0.pick" -module \pick - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:75" - wire width 1 input 0 \i - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:76" - wire width 1 output 1 \o - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:77" - wire width 1 output 2 \n - process $group_0 - assign \o 1'0 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" - switch { \i } - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:82" - case 1'1 - assign \o 1'0 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:84" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:84" - cell $eq $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \i - connect \B 1'0 - connect \Y $1 - end - process $group_1 - assign \n 1'0 - assign \n $1 - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.l0.l0" -module \l0$127 - attribute \src "simple/issuer.py:141" - wire width 1 input 0 \coresync_clk - attribute \src "simple/issuer.py:141" - wire width 1 input 1 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:105" - wire width 1 output 2 \ldst_port0_busy_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:98" - wire width 1 input 3 \ldst_port0_is_ld_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:99" - wire width 1 input 4 \ldst_port0_is_st_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:102" - wire width 4 input 5 \ldst_port0_data_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 96 input 6 \ldst_port0_addr_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 input 7 \ldst_port0_addr_i_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:110" - wire width 1 output 8 \ldst_port0_addr_exc_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:109" - wire width 1 output 9 \ldst_port0_addr_ok_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 output 10 \ldst_port0_ld_data_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 11 \ldst_port0_ld_data_o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 input 12 \ldst_port0_st_data_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 input 13 \ldst_port0_st_data_i_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:98" - wire width 1 output 14 \ldst_port0_is_ld_i$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:99" - wire width 1 output 15 \ldst_port0_is_st_i$2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:105" - wire width 1 input 16 \ldst_port0_busy_o$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:102" - wire width 4 output 17 \ldst_port0_data_len$4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 48 output 18 \ldst_port0_addr_i$5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 19 \ldst_port0_addr_i_ok$6 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:109" - wire width 1 input 20 \ldst_port0_addr_ok_o$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 input 21 \ldst_port0_ld_data_o$8 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 input 22 \ldst_port0_ld_data_o_ok$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 23 \ldst_port0_st_data_i_ok$10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 output 24 \ldst_port0_st_data_i$11 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:110" - wire width 1 input 25 \ldst_port0_addr_exc_o$12 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire width 1 \idx_l_q_idx_l - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 1 \idx_l_s_idx_l - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 1 \idx_l_r_idx_l - cell \idx_l \idx_l - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \q_idx_l \idx_l_q_idx_l - connect \s_idx_l \idx_l_s_idx_l - connect \r_idx_l \idx_l_r_idx_l - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:58" - wire width 1 \reset_l_s_reset - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:59" - wire width 1 \reset_l_r_reset - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:60" - wire width 1 \reset_l_q_reset - cell \reset_l$128 \reset_l - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \s_reset \reset_l_s_reset - connect \r_reset \reset_l_r_reset - connect \q_reset \reset_l_q_reset - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:75" - wire width 1 \pick_i - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:76" - wire width 1 \pick_o - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/lib/coding.py:77" - wire width 1 \pick_n - cell \pick \pick - connect \i \pick_i - connect \o \pick_o - connect \n \pick_n - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:262" - wire width 1 $13 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:262" - cell $or $14 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \ldst_port0_is_ld_i - connect \B \ldst_port0_is_st_i - connect \Y $13 - end - process $group_0 - assign \pick_i 1'0 - assign \pick_i { $13 } - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - wire width 1 $15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" - wire width 1 \idx_l$16 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:39" - wire width 1 \idx_l$16$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - wire width 1 $17 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:40" - cell $mux $18 - parameter \WIDTH 1 - connect \A \idx_l$16 - connect \B \pick_o - connect \S \idx_l_q_idx_l - connect \Y $17 - end - connect $15 $17 - process $group_1 - assign { } 0'0 - assign { } {} - sync init - end - process $group_2 - assign \idx_l$16$next \idx_l$16 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" - switch { \idx_l_q_idx_l } - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/latch.py:41" - case 1'1 - assign \idx_l$16$next \pick_o - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \idx_l$16$next 1'0 - end - sync init - update \idx_l$16 1'0 - sync posedge \coresync_clk - update \idx_l$16 \idx_l$16$next - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:278" - wire width 1 $19 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:278" - cell $not $20 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \pick_n - connect \Y $19 - end - process $group_3 - assign \idx_l_s_idx_l 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:278" - switch { $19 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:278" - case 1'1 - assign \idx_l_s_idx_l 1'1 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:288" - wire width 1 $21 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:288" - cell $not $22 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \ldst_port0_busy_o$3 - connect \Y $21 - end - process $group_4 - assign \reset_l_s_reset 1'0 - assign \reset_l_s_reset 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:286" - switch { \idx_l_q_idx_l } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:286" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:288" - switch { $21 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:288" - case 1'1 - assign \reset_l_s_reset 1'1 - end - end - sync init - end - process $group_5 - assign \reset_l_r_reset 1'1 - assign \reset_l_r_reset 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:296" - switch { \reset_l_q_reset } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:296" - case 1'1 - assign \reset_l_r_reset 1'1 - end - sync init - end - process $group_6 - assign \ldst_port0_is_ld_i$1 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:286" - switch { \idx_l_q_idx_l } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:286" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:118" - switch { } - case 0' - assign \ldst_port0_is_ld_i$1 \ldst_port0_is_ld_i - end - end - sync init - end - process $group_7 - assign \ldst_port0_is_st_i$2 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:286" - switch { \idx_l_q_idx_l } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:286" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:119" - switch { } - case 0' - assign \ldst_port0_is_st_i$2 \ldst_port0_is_st_i - end - end - sync init - end - process $group_8 - assign \ldst_port0_data_len$4 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:286" - switch { \idx_l_q_idx_l } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:286" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:120" - switch { } - case 0' - assign \ldst_port0_data_len$4 \ldst_port0_data_len - end - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:106" - wire width 1 \ldst_port0_go_die_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:106" - wire width 1 \ldst_port0_go_die_i$23 - process $group_9 - assign \ldst_port0_go_die_i 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:286" - switch { \idx_l_q_idx_l } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:286" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:121" - switch { } - case 0' - assign \ldst_port0_go_die_i \ldst_port0_go_die_i$23 - end - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:122" - wire width 96 $24 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:122" - wire width 96 $25 - connect $25 \ldst_port0_addr_i - process $group_10 - assign \ldst_port0_addr_i$5 48'000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:286" - switch { \idx_l_q_idx_l } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:286" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:122" - switch { } - case 0' - assign \ldst_port0_addr_i$5 $25 [47:0] - end - end - sync init - end - process $group_11 - assign \ldst_port0_addr_i_ok$6 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:286" - switch { \idx_l_q_idx_l } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:286" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:123" - switch { } - case 0' - assign \ldst_port0_addr_i_ok$6 \ldst_port0_addr_i_ok - end - end - sync init - end - process $group_12 - assign \ldst_port0_st_data_i$11 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \ldst_port0_st_data_i_ok$10 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:286" - switch { \idx_l_q_idx_l } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:286" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:124" - switch { } - case 0' - assign { \ldst_port0_st_data_i_ok$10 \ldst_port0_st_data_i$11 } { \ldst_port0_st_data_i_ok \ldst_port0_st_data_i } - end - end - sync init - end - process $group_14 - assign \ldst_port0_ld_data_o 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \ldst_port0_ld_data_o_ok 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:286" - switch { \idx_l_q_idx_l } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:286" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:125" - switch { } - case 0' - assign { \ldst_port0_ld_data_o_ok \ldst_port0_ld_data_o } { \ldst_port0_ld_data_o_ok$9 \ldst_port0_ld_data_o$8 } - end - end - sync init - end - process $group_16 - assign \ldst_port0_busy_o 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:286" - switch { \idx_l_q_idx_l } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:286" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:126" - switch { } - case 0' - assign \ldst_port0_busy_o \ldst_port0_busy_o$3 - end - end - sync init - end - process $group_17 - assign \ldst_port0_addr_ok_o 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:286" - switch { \idx_l_q_idx_l } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:286" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:127" - switch { } - case 0' - assign \ldst_port0_addr_ok_o \ldst_port0_addr_ok_o$7 - end - end - sync init - end - process $group_18 - assign \ldst_port0_addr_exc_o 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:286" - switch { \idx_l_q_idx_l } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:286" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:128" - switch { } - case 0' - assign \ldst_port0_addr_exc_o \ldst_port0_addr_exc_o$12 - end - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:292" - wire width 1 \reset_delay - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:292" - wire width 1 \reset_delay$next - process $group_19 - assign \reset_delay$next \reset_delay - assign \reset_delay$next \reset_l_q_reset - sync init - update \reset_delay 1'0 - sync posedge \coresync_clk - update \reset_delay \reset_delay$next - end - process $group_20 - assign \idx_l_r_idx_l 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:296" - switch { \reset_l_q_reset } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/l0_cache.py:296" - case 1'1 - assign \idx_l_r_idx_l 1'1 - end - sync init - end - connect \ldst_port0_go_die_i$23 1'0 -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.l0.lsmem" -module \lsmem - attribute \src "simple/issuer.py:141" - wire width 1 input 0 \coresync_clk - attribute \src "simple/issuer.py:141" - wire width 1 input 1 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:44" - wire width 8 input 2 \x_mask_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:43" - wire width 48 input 3 \x_addr_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:62" - wire width 64 output 4 \m_ld_data_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:62" - wire width 64 \m_ld_data_o$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:47" - wire width 64 input 5 \x_st_data_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:59" - wire width 1 output 6 \x_busy_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:45" - wire width 1 input 7 \x_ld_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:46" - wire width 1 input 8 \x_st_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:54" - wire width 1 input 9 \m_valid_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:50" - wire width 1 input 10 \x_valid_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" - wire width 1 output 11 \dbus__cyc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" - wire width 1 \dbus__cyc$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" - wire width 1 input 12 \dbus__ack - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" - wire width 1 input 13 \dbus__err - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" - wire width 1 output 14 \dbus__stb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" - wire width 1 \dbus__stb$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" - wire width 8 output 15 \dbus__sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" - wire width 8 \dbus__sel$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" - wire width 64 input 16 \dbus__dat_r - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" - wire width 45 output 17 \dbus__adr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" - wire width 45 \dbus__adr$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" - wire width 1 output 18 \dbus__we - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" - wire width 1 \dbus__we$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" - wire width 64 output 19 \dbus__dat_w - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" - wire width 64 \dbus__dat_w$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113" - cell $or $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \x_ld_i - connect \B \x_st_i - connect \Y $1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113" - wire width 1 $3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113" - cell $and $4 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $1 - connect \B \x_valid_i - connect \Y $3 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113" - wire width 1 $5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:49" - wire width 1 \x_stall_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113" - cell $not $6 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \x_stall_i - connect \Y $5 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113" - wire width 1 $7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113" - cell $and $8 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $3 - connect \B $5 - connect \Y $7 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:105" - wire width 1 $9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:105" - cell $or $10 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \dbus__ack - connect \B \dbus__err - connect \Y $9 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:105" - wire width 1 $11 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:105" - cell $not $12 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \m_valid_i - connect \Y $11 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:105" - wire width 1 $13 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:105" - cell $or $14 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $9 - connect \B $11 - connect \Y $13 - end - process $group_0 - assign \dbus__cyc$next \dbus__cyc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:104" - switch { $7 \dbus__cyc } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:104" - case 2'-1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:105" - switch { $13 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:105" - case 1'1 - assign \dbus__cyc$next 1'0 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113" - case 2'1- - assign \dbus__cyc$next 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \dbus__cyc$next 1'0 - end - sync init - update \dbus__cyc 1'0 - sync posedge \coresync_clk - update \dbus__cyc \dbus__cyc$next - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113" - wire width 1 $15 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113" - cell $or $16 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \x_ld_i - connect \B \x_st_i - connect \Y $15 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113" - wire width 1 $17 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113" - cell $and $18 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $15 - connect \B \x_valid_i - connect \Y $17 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113" - wire width 1 $19 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113" - cell $not $20 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \x_stall_i - connect \Y $19 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113" - wire width 1 $21 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113" - cell $and $22 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $17 - connect \B $19 - connect \Y $21 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:105" - wire width 1 $23 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:105" - cell $or $24 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \dbus__ack - connect \B \dbus__err - connect \Y $23 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:105" - wire width 1 $25 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:105" - cell $not $26 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \m_valid_i - connect \Y $25 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:105" - wire width 1 $27 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:105" - cell $or $28 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $23 - connect \B $25 - connect \Y $27 - end - process $group_1 - assign \dbus__stb$next \dbus__stb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:104" - switch { $21 \dbus__cyc } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:104" - case 2'-1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:105" - switch { $27 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:105" - case 1'1 - assign \dbus__stb$next 1'0 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113" - case 2'1- - assign \dbus__stb$next 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \dbus__stb$next 1'0 - end - sync init - update \dbus__stb 1'0 - sync posedge \coresync_clk - update \dbus__stb \dbus__stb$next - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113" - wire width 1 $29 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113" - cell $or $30 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \x_ld_i - connect \B \x_st_i - connect \Y $29 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113" - wire width 1 $31 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113" - cell $and $32 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $29 - connect \B \x_valid_i - connect \Y $31 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113" - wire width 1 $33 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113" - cell $not $34 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \x_stall_i - connect \Y $33 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113" - wire width 1 $35 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113" - cell $and $36 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $31 - connect \B $33 - connect \Y $35 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:105" - wire width 1 $37 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:105" - cell $or $38 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \dbus__ack - connect \B \dbus__err - connect \Y $37 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:105" - wire width 1 $39 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:105" - cell $not $40 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \m_valid_i - connect \Y $39 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:105" - wire width 1 $41 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:105" - cell $or $42 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $37 - connect \B $39 - connect \Y $41 - end - process $group_2 - assign \dbus__sel$next \dbus__sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:104" - switch { $35 \dbus__cyc } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:104" - case 2'-1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:105" - switch { $41 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:105" - case 1'1 - assign \dbus__sel$next 8'00000000 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113" - case 2'1- - assign \dbus__sel$next \x_mask_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" - case - assign \dbus__sel$next 8'00000000 - assign \dbus__sel$next 8'00000000 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \dbus__sel$next 8'00000000 - end - sync init - update \dbus__sel 8'00000000 - sync posedge \coresync_clk - update \dbus__sel \dbus__sel$next - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113" - wire width 1 $43 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113" - cell $or $44 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \x_ld_i - connect \B \x_st_i - connect \Y $43 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113" - wire width 1 $45 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113" - cell $and $46 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $43 - connect \B \x_valid_i - connect \Y $45 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113" - wire width 1 $47 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113" - cell $not $48 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \x_stall_i - connect \Y $47 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113" - wire width 1 $49 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113" - cell $and $50 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $45 - connect \B $47 - connect \Y $49 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:105" - wire width 1 $51 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:105" - cell $or $52 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \dbus__ack - connect \B \dbus__err - connect \Y $51 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:105" - wire width 1 $53 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:105" - cell $not $54 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \m_valid_i - connect \Y $53 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:105" - wire width 1 $55 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:105" - cell $or $56 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $51 - connect \B $53 - connect \Y $55 - end - process $group_3 - assign \m_ld_data_o$next \m_ld_data_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:104" - switch { $49 \dbus__cyc } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:104" - case 2'-1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:105" - switch { $55 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:105" - case 1'1 - assign \m_ld_data_o$next \dbus__dat_r - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113" - case 2'1- - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" - case - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \m_ld_data_o$next 64'0000000000000000000000000000000000000000000000000000000000000000 - end - sync init - update \m_ld_data_o 64'0000000000000000000000000000000000000000000000000000000000000000 - sync posedge \coresync_clk - update \m_ld_data_o \m_ld_data_o$next - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113" - wire width 1 $57 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113" - cell $or $58 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \x_ld_i - connect \B \x_st_i - connect \Y $57 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113" - wire width 1 $59 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113" - cell $and $60 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $57 - connect \B \x_valid_i - connect \Y $59 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113" - wire width 1 $61 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113" - cell $not $62 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \x_stall_i - connect \Y $61 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113" - wire width 1 $63 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113" - cell $and $64 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $59 - connect \B $61 - connect \Y $63 - end - process $group_4 - assign \dbus__adr$next \dbus__adr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:104" - switch { $63 \dbus__cyc } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:104" - case 2'-1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113" - case 2'1- - assign \dbus__adr$next \x_addr_i [47:3] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" - case - assign \dbus__adr$next 45'000000000000000000000000000000000000000000000 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \dbus__adr$next 45'000000000000000000000000000000000000000000000 - end - sync init - update \dbus__adr 45'000000000000000000000000000000000000000000000 - sync posedge \coresync_clk - update \dbus__adr \dbus__adr$next - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113" - wire width 1 $65 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113" - cell $or $66 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \x_ld_i - connect \B \x_st_i - connect \Y $65 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113" - wire width 1 $67 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113" - cell $and $68 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $65 - connect \B \x_valid_i - connect \Y $67 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113" - wire width 1 $69 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113" - cell $not $70 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \x_stall_i - connect \Y $69 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113" - wire width 1 $71 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113" - cell $and $72 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $67 - connect \B $69 - connect \Y $71 - end - process $group_5 - assign \dbus__we$next \dbus__we - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:104" - switch { $71 \dbus__cyc } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:104" - case 2'-1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113" - case 2'1- - assign \dbus__we$next \x_st_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" - case - assign \dbus__we$next 1'0 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \dbus__we$next 1'0 - end - sync init - update \dbus__we 1'0 - sync posedge \coresync_clk - update \dbus__we \dbus__we$next - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113" - wire width 1 $73 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113" - cell $or $74 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \x_ld_i - connect \B \x_st_i - connect \Y $73 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113" - wire width 1 $75 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113" - cell $and $76 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $73 - connect \B \x_valid_i - connect \Y $75 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113" - wire width 1 $77 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113" - cell $not $78 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \x_stall_i - connect \Y $77 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113" - wire width 1 $79 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113" - cell $and $80 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $75 - connect \B $77 - connect \Y $79 - end - process $group_6 - assign \dbus__dat_w$next \dbus__dat_w - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:104" - switch { $79 \dbus__cyc } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:104" - case 2'-1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:113" - case 2'1- - assign \dbus__dat_w$next \x_st_data_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:122" - case - assign \dbus__dat_w$next 64'0000000000000000000000000000000000000000000000000000000000000000 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \dbus__dat_w$next 64'0000000000000000000000000000000000000000000000000000000000000000 - end - sync init - update \dbus__dat_w 64'0000000000000000000000000000000000000000000000000000000000000000 - sync posedge \coresync_clk - update \dbus__dat_w \dbus__dat_w$next - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:67" - wire width 1 \m_load_err_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:67" - wire width 1 \m_load_err_o$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:131" - wire width 1 $81 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:131" - cell $and $82 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \dbus__cyc - connect \B \dbus__err - connect \Y $81 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:137" - wire width 1 $83 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:53" - wire width 1 \m_stall_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:137" - cell $not $84 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \m_stall_i - connect \Y $83 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:133" - wire width 1 $85 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:133" - cell $not $86 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \dbus__we - connect \Y $85 - end - process $group_7 - assign \m_load_err_o$next \m_load_err_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:131" - switch { $83 $81 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:131" - case 2'-1 - assign \m_load_err_o$next $85 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:137" - case 2'1- - assign \m_load_err_o$next 1'0 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \m_load_err_o$next 1'0 - end - sync init - update \m_load_err_o 1'0 - sync posedge \coresync_clk - update \m_load_err_o \m_load_err_o$next - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:68" - wire width 1 \m_store_err_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:68" - wire width 1 \m_store_err_o$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:131" - wire width 1 $87 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:131" - cell $and $88 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \dbus__cyc - connect \B \dbus__err - connect \Y $87 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:137" - wire width 1 $89 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:137" - cell $not $90 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \m_stall_i - connect \Y $89 - end - process $group_8 - assign \m_store_err_o$next \m_store_err_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:131" - switch { $89 $87 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:131" - case 2'-1 - assign \m_store_err_o$next \dbus__we - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:137" - case 2'1- - assign \m_store_err_o$next 1'0 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \m_store_err_o$next 1'0 - end - sync init - update \m_store_err_o 1'0 - sync posedge \coresync_clk - update \m_store_err_o \m_store_err_o$next - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:70" - wire width 45 \m_badaddr_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:70" - wire width 45 \m_badaddr_o$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:131" - wire width 1 $91 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:131" - cell $and $92 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \dbus__cyc - connect \B \dbus__err - connect \Y $91 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:137" - wire width 1 $93 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:137" - cell $not $94 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \m_stall_i - connect \Y $93 - end - process $group_9 - assign \m_badaddr_o$next \m_badaddr_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:131" - switch { $93 $91 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:131" - case 2'-1 - assign \m_badaddr_o$next \dbus__adr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:137" - case 2'1- - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \m_badaddr_o$next 45'000000000000000000000000000000000000000000000 - end - sync init - update \m_badaddr_o 45'000000000000000000000000000000000000000000000 - sync posedge \coresync_clk - update \m_badaddr_o \m_badaddr_o$next - end - process $group_10 - assign \x_busy_o 1'0 - assign \x_busy_o \dbus__cyc - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:60" - wire width 1 \m_busy_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:145" - wire width 1 $95 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:145" - cell $or $96 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \m_load_err_o - connect \B \m_store_err_o - connect \Y $95 - end - process $group_11 - assign \m_busy_o 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:145" - switch { $95 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:145" - case 1'1 - assign \m_busy_o 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:147" - case - assign \m_busy_o \dbus__cyc - end - sync init - end - connect \x_stall_i 1'0 - connect \m_stall_i 1'0 -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.l0" -module \l0 - attribute \src "simple/issuer.py:141" - wire width 1 input 0 \coresync_clk - attribute \src "simple/issuer.py:141" - wire width 1 input 1 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:105" - wire width 1 output 2 \ldst_port0_busy_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:98" - wire width 1 input 3 \ldst_port0_is_ld_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:99" - wire width 1 input 4 \ldst_port0_is_st_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:102" - wire width 4 input 5 \ldst_port0_data_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 96 input 6 \ldst_port0_addr_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 input 7 \ldst_port0_addr_i_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:110" - wire width 1 output 8 \ldst_port0_addr_exc_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:109" - wire width 1 output 9 \ldst_port0_addr_ok_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 output 10 \ldst_port0_ld_data_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 11 \ldst_port0_ld_data_o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 input 12 \ldst_port0_st_data_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 input 13 \ldst_port0_st_data_i_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" - wire width 1 output 14 \dbus__cyc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" - wire width 1 input 15 \dbus__ack - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" - wire width 1 input 16 \dbus__err - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" - wire width 1 output 17 \dbus__stb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" - wire width 8 output 18 \dbus__sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" - wire width 64 input 19 \dbus__dat_r - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" - wire width 45 output 20 \dbus__adr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" - wire width 1 output 21 \dbus__we - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:32" - wire width 64 output 22 \dbus__dat_w - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:98" - wire width 1 \pimem_ldst_port0_is_ld_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:99" - wire width 1 \pimem_ldst_port0_is_st_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:105" - wire width 1 \pimem_ldst_port0_busy_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:102" - wire width 4 \pimem_ldst_port0_data_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 48 \pimem_ldst_port0_addr_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \pimem_ldst_port0_addr_i_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:44" - wire width 8 \pimem_x_mask_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:43" - wire width 48 \pimem_x_addr_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:109" - wire width 1 \pimem_ldst_port0_addr_ok_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:62" - wire width 64 \pimem_m_ld_data_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 \pimem_ldst_port0_ld_data_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \pimem_ldst_port0_ld_data_o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \pimem_ldst_port0_st_data_i_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 \pimem_ldst_port0_st_data_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:47" - wire width 64 \pimem_x_st_data_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:59" - wire width 1 \pimem_x_busy_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:110" - wire width 1 \pimem_ldst_port0_addr_exc_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:45" - wire width 1 \pimem_x_ld_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:46" - wire width 1 \pimem_x_st_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:54" - wire width 1 \pimem_m_valid_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/loadstore.py:50" - wire width 1 \pimem_x_valid_i - cell \pimem \pimem - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \ldst_port0_is_ld_i \pimem_ldst_port0_is_ld_i - connect \ldst_port0_is_st_i \pimem_ldst_port0_is_st_i - connect \ldst_port0_busy_o \pimem_ldst_port0_busy_o - connect \ldst_port0_data_len \pimem_ldst_port0_data_len - connect \ldst_port0_addr_i \pimem_ldst_port0_addr_i - connect \ldst_port0_addr_i_ok \pimem_ldst_port0_addr_i_ok - connect \x_mask_i \pimem_x_mask_i - connect \x_addr_i \pimem_x_addr_i - connect \ldst_port0_addr_ok_o \pimem_ldst_port0_addr_ok_o - connect \m_ld_data_o \pimem_m_ld_data_o - connect \ldst_port0_ld_data_o \pimem_ldst_port0_ld_data_o - connect \ldst_port0_ld_data_o_ok \pimem_ldst_port0_ld_data_o_ok - connect \ldst_port0_st_data_i_ok \pimem_ldst_port0_st_data_i_ok - connect \ldst_port0_st_data_i \pimem_ldst_port0_st_data_i - connect \x_st_data_i \pimem_x_st_data_i - connect \x_busy_o \pimem_x_busy_o - connect \ldst_port0_addr_exc_o \pimem_ldst_port0_addr_exc_o - connect \x_ld_i \pimem_x_ld_i - connect \x_st_i \pimem_x_st_i - connect \m_valid_i \pimem_m_valid_i - connect \x_valid_i \pimem_x_valid_i - end - cell \l0$127 \l0 - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \ldst_port0_busy_o \ldst_port0_busy_o - connect \ldst_port0_is_ld_i \ldst_port0_is_ld_i - connect \ldst_port0_is_st_i \ldst_port0_is_st_i - connect \ldst_port0_data_len \ldst_port0_data_len - connect \ldst_port0_addr_i \ldst_port0_addr_i - connect \ldst_port0_addr_i_ok \ldst_port0_addr_i_ok - connect \ldst_port0_addr_exc_o \ldst_port0_addr_exc_o - connect \ldst_port0_addr_ok_o \ldst_port0_addr_ok_o - connect \ldst_port0_ld_data_o \ldst_port0_ld_data_o - connect \ldst_port0_ld_data_o_ok \ldst_port0_ld_data_o_ok - connect \ldst_port0_st_data_i \ldst_port0_st_data_i - connect \ldst_port0_st_data_i_ok \ldst_port0_st_data_i_ok - connect \ldst_port0_is_ld_i$1 \pimem_ldst_port0_is_ld_i - connect \ldst_port0_is_st_i$2 \pimem_ldst_port0_is_st_i - connect \ldst_port0_busy_o$3 \pimem_ldst_port0_busy_o - connect \ldst_port0_data_len$4 \pimem_ldst_port0_data_len - connect \ldst_port0_addr_i$5 \pimem_ldst_port0_addr_i - connect \ldst_port0_addr_i_ok$6 \pimem_ldst_port0_addr_i_ok - connect \ldst_port0_addr_ok_o$7 \pimem_ldst_port0_addr_ok_o - connect \ldst_port0_ld_data_o$8 \pimem_ldst_port0_ld_data_o - connect \ldst_port0_ld_data_o_ok$9 \pimem_ldst_port0_ld_data_o_ok - connect \ldst_port0_st_data_i_ok$10 \pimem_ldst_port0_st_data_i_ok - connect \ldst_port0_st_data_i$11 \pimem_ldst_port0_st_data_i - connect \ldst_port0_addr_exc_o$12 \pimem_ldst_port0_addr_exc_o - end - cell \lsmem \lsmem - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \x_mask_i \pimem_x_mask_i - connect \x_addr_i \pimem_x_addr_i - connect \m_ld_data_o \pimem_m_ld_data_o - connect \x_st_data_i \pimem_x_st_data_i - connect \x_busy_o \pimem_x_busy_o - connect \x_ld_i \pimem_x_ld_i - connect \x_st_i \pimem_x_st_i - connect \m_valid_i \pimem_m_valid_i - connect \x_valid_i \pimem_x_valid_i - connect \dbus__cyc \dbus__cyc - connect \dbus__ack \dbus__ack - connect \dbus__err \dbus__err - connect \dbus__stb \dbus__stb - connect \dbus__sel \dbus__sel - connect \dbus__dat_r \dbus__dat_r - connect \dbus__adr \dbus__adr - connect \dbus__we \dbus__we - connect \dbus__dat_w \dbus__dat_w - end - connect \pimem_ldst_port0_addr_exc_o 1'0 -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.int" -module \int - attribute \src "simple/issuer.py:141" - wire width 1 input 0 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 5 input 1 \dmi__addr - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 input 2 \dmi__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 output 3 \dmi__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 output 4 \src1__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 5 input 5 \src1__addr - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 input 6 \src1__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 output 7 \src2__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 5 input 8 \src2__addr - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 input 9 \src2__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 output 10 \src3__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 5 input 11 \src3__addr - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 input 12 \src3__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 input 13 \dest1__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 5 input 14 \dest1__addr - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 input 15 \dest1__wen - attribute \src "simple/issuer.py:141" - wire width 1 input 16 \coresync_rst - memory width 64 size 32 \memory - cell $meminit $1 - parameter \MEMID "\\memory" - parameter \ABITS 6 - parameter \WIDTH 64 - parameter \WORDS 32 - parameter \PRIORITY 0 - connect \ADDR 6'000000 - connect \DATA 2048'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:210" - wire width 5 \memory_r_addr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:210" - wire width 64 \memory_r_data - cell $memrd \rp_src1 - parameter \MEMID "\\memory" - parameter \ABITS 5 - parameter \WIDTH 64 - parameter \CLK_ENABLE 1 - parameter \CLK_POLARITY 1 - parameter \TRANSPARENT 1 - connect \CLK \coresync_clk - connect \EN 1'1 - connect \ADDR \memory_r_addr - connect \DATA \memory_r_data - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:210" - wire width 5 \memory_r_addr$2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:210" - wire width 64 \memory_r_data$3 - cell $memrd \rp_src2 - parameter \MEMID "\\memory" - parameter \ABITS 5 - parameter \WIDTH 64 - parameter \CLK_ENABLE 1 - parameter \CLK_POLARITY 1 - parameter \TRANSPARENT 1 - connect \CLK \coresync_clk - connect \EN 1'1 - connect \ADDR \memory_r_addr$2 - connect \DATA \memory_r_data$3 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:210" - wire width 5 \memory_r_addr$4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:210" - wire width 64 \memory_r_data$5 - cell $memrd \rp_src3 - parameter \MEMID "\\memory" - parameter \ABITS 5 - parameter \WIDTH 64 - parameter \CLK_ENABLE 1 - parameter \CLK_POLARITY 1 - parameter \TRANSPARENT 1 - connect \CLK \coresync_clk - connect \EN 1'1 - connect \ADDR \memory_r_addr$4 - connect \DATA \memory_r_data$5 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:210" - wire width 5 \memory_r_addr$6 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:210" - wire width 64 \memory_r_data$7 - cell $memrd \rp_dmi - parameter \MEMID "\\memory" - parameter \ABITS 5 - parameter \WIDTH 64 - parameter \CLK_ENABLE 1 - parameter \CLK_POLARITY 1 - parameter \TRANSPARENT 1 - connect \CLK \coresync_clk - connect \EN 1'1 - connect \ADDR \memory_r_addr$6 - connect \DATA \memory_r_data$7 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:218" - wire width 1 \memory_w_en - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:218" - wire width 5 \memory_w_addr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:218" - wire width 64 \memory_w_data - cell $memwr \wp_dest1 - parameter \MEMID "\\memory" - parameter \ABITS 5 - parameter \WIDTH 64 - parameter \CLK_ENABLE 1 - parameter \CLK_POLARITY 1 - parameter \PRIORITY 0 - connect \CLK \coresync_clk - connect \EN { { \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en } } - connect \ADDR \memory_w_addr - connect \DATA \memory_w_data - end - process $group_0 - assign \memory_r_addr 5'00000 - assign \memory_r_addr \src1__addr - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:243" - wire width 1 \ren_delay - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:243" - wire width 1 \ren_delay$next - process $group_1 - assign \ren_delay$next \ren_delay - assign \ren_delay$next \src1__ren - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \ren_delay$next 1'0 - end - sync init - update \ren_delay 1'0 - sync posedge \coresync_clk - update \ren_delay \ren_delay$next - end - process $group_2 - assign \src1__data_o 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:245" - switch { \ren_delay } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:245" - case 1'1 - assign \src1__data_o \memory_r_data - end - sync init - end - process $group_3 - assign \memory_r_addr$2 5'00000 - assign \memory_r_addr$2 \src2__addr - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:243" - wire width 1 \ren_delay$8 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:243" - wire width 1 \ren_delay$8$next - process $group_4 - assign \ren_delay$8$next \ren_delay$8 - assign \ren_delay$8$next \src2__ren - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \ren_delay$8$next 1'0 - end - sync init - update \ren_delay$8 1'0 - sync posedge \coresync_clk - update \ren_delay$8 \ren_delay$8$next - end - process $group_5 - assign \src2__data_o 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:245" - switch { \ren_delay$8 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:245" - case 1'1 - assign \src2__data_o \memory_r_data$3 - end - sync init - end - process $group_6 - assign \memory_r_addr$4 5'00000 - assign \memory_r_addr$4 \src3__addr - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:243" - wire width 1 \ren_delay$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:243" - wire width 1 \ren_delay$9$next - process $group_7 - assign \ren_delay$9$next \ren_delay$9 - assign \ren_delay$9$next \src3__ren - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \ren_delay$9$next 1'0 - end - sync init - update \ren_delay$9 1'0 - sync posedge \coresync_clk - update \ren_delay$9 \ren_delay$9$next - end - process $group_8 - assign \src3__data_o 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:245" - switch { \ren_delay$9 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:245" - case 1'1 - assign \src3__data_o \memory_r_data$5 - end - sync init - end - process $group_9 - assign \memory_r_addr$6 5'00000 - assign \memory_r_addr$6 \dmi__addr - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:243" - wire width 1 \ren_delay$10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:243" - wire width 1 \ren_delay$10$next - process $group_10 - assign \ren_delay$10$next \ren_delay$10 - assign \ren_delay$10$next \dmi__ren - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \ren_delay$10$next 1'0 - end - sync init - update \ren_delay$10 1'0 - sync posedge \coresync_clk - update \ren_delay$10 \ren_delay$10$next - end - process $group_11 - assign \dmi__data_o 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:245" - switch { \ren_delay$10 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:245" - case 1'1 - assign \dmi__data_o \memory_r_data$7 - end - sync init - end - process $group_12 - assign \memory_w_addr 5'00000 - assign \memory_w_addr \dest1__addr - sync init - end - process $group_13 - assign \memory_w_en 1'0 - assign \memory_w_en \dest1__wen - sync init - end - process $group_14 - assign \memory_w_data 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \memory_w_data \dest1__data_i - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.cr.reg_0" -module \reg_0 - attribute \src "simple/issuer.py:141" - wire width 1 input 0 \coresync_clk - attribute \src "simple/issuer.py:141" - wire width 1 input 1 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 input 2 \src10__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 output 3 \src10__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 \src10__data_o$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 input 4 \src20__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 output 5 \src20__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 \src20__data_o$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 input 6 \src30__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 output 7 \src30__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 \src30__data_o$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 input 8 \dest10__wen - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 input 9 \dest10__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 input 10 \dest20__wen - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 input 11 \dest20__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 output 12 \r0__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 \r0__data_o$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 input 13 \r0__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 output 14 \r20__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 \r20__data_o$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 input 15 \r20__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 input 16 \w0__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 input 17 \w0__wen - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" - wire width 1 \wr_detect - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_detect - connect \Y $1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" - wire width 4 \reg - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" - wire width 4 \reg$next - process $group_0 - assign \src10__data_o$next \src10__data_o - assign \src10__data_o$next 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch { \src10__ren } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch { \dest10__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - case 1'1 - assign \src10__data_o$next \dest10__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch { \dest20__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - case 1'1 - assign \src10__data_o$next \dest20__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch { \w0__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - case 1'1 - assign \src10__data_o$next \w0__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - switch { $1 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - case 1'1 - assign \src10__data_o$next \reg - end - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \src10__data_o$next 4'0000 - end - sync init - update \src10__data_o 4'0000 - sync posedge \coresync_clk - update \src10__data_o \src10__data_o$next - end - process $group_1 - assign \wr_detect 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch { \src10__ren } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - case 1'1 - assign \wr_detect 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch { \dest10__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - case 1'1 - assign \wr_detect 1'1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch { \dest20__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - case 1'1 - assign \wr_detect 1'1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch { \w0__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - case 1'1 - assign \wr_detect 1'1 - end - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - wire width 1 $3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" - wire width 1 \wr_detect$4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $5 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_detect$4 - connect \Y $3 - end - process $group_2 - assign \src20__data_o$next \src20__data_o - assign \src20__data_o$next 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch { \src20__ren } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch { \dest10__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - case 1'1 - assign \src20__data_o$next \dest10__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch { \dest20__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - case 1'1 - assign \src20__data_o$next \dest20__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch { \w0__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - case 1'1 - assign \src20__data_o$next \w0__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - switch { $3 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - case 1'1 - assign \src20__data_o$next \reg - end - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \src20__data_o$next 4'0000 - end - sync init - update \src20__data_o 4'0000 - sync posedge \coresync_clk - update \src20__data_o \src20__data_o$next - end - process $group_3 - assign \wr_detect$4 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch { \src20__ren } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - case 1'1 - assign \wr_detect$4 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch { \dest10__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - case 1'1 - assign \wr_detect$4 1'1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch { \dest20__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - case 1'1 - assign \wr_detect$4 1'1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch { \w0__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - case 1'1 - assign \wr_detect$4 1'1 - end - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - wire width 1 $6 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" - wire width 1 \wr_detect$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $8 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_detect$7 - connect \Y $6 - end - process $group_4 - assign \src30__data_o$next \src30__data_o - assign \src30__data_o$next 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch { \src30__ren } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch { \dest10__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - case 1'1 - assign \src30__data_o$next \dest10__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch { \dest20__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - case 1'1 - assign \src30__data_o$next \dest20__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch { \w0__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - case 1'1 - assign \src30__data_o$next \w0__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - switch { $6 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - case 1'1 - assign \src30__data_o$next \reg - end - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \src30__data_o$next 4'0000 - end - sync init - update \src30__data_o 4'0000 - sync posedge \coresync_clk - update \src30__data_o \src30__data_o$next - end - process $group_5 - assign \wr_detect$7 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch { \src30__ren } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - case 1'1 - assign \wr_detect$7 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch { \dest10__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - case 1'1 - assign \wr_detect$7 1'1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch { \dest20__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - case 1'1 - assign \wr_detect$7 1'1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch { \w0__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - case 1'1 - assign \wr_detect$7 1'1 - end - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - wire width 1 $9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" - wire width 1 \wr_detect$10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $11 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_detect$10 - connect \Y $9 - end - process $group_6 - assign \r0__data_o$next \r0__data_o - assign \r0__data_o$next 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch { \r0__ren } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch { \dest10__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - case 1'1 - assign \r0__data_o$next \dest10__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch { \dest20__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - case 1'1 - assign \r0__data_o$next \dest20__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch { \w0__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - case 1'1 - assign \r0__data_o$next \w0__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - switch { $9 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - case 1'1 - assign \r0__data_o$next \reg - end - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \r0__data_o$next 4'0000 - end - sync init - update \r0__data_o 4'0000 - sync posedge \coresync_clk - update \r0__data_o \r0__data_o$next - end - process $group_7 - assign \wr_detect$10 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch { \r0__ren } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - case 1'1 - assign \wr_detect$10 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch { \dest10__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - case 1'1 - assign \wr_detect$10 1'1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch { \dest20__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - case 1'1 - assign \wr_detect$10 1'1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch { \w0__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - case 1'1 - assign \wr_detect$10 1'1 - end - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - wire width 1 $12 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" - wire width 1 \wr_detect$13 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $14 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_detect$13 - connect \Y $12 - end - process $group_8 - assign \r20__data_o$next \r20__data_o - assign \r20__data_o$next 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch { \r20__ren } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch { \dest10__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - case 1'1 - assign \r20__data_o$next \dest10__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch { \dest20__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - case 1'1 - assign \r20__data_o$next \dest20__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch { \w0__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - case 1'1 - assign \r20__data_o$next \w0__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - switch { $12 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - case 1'1 - assign \r20__data_o$next \reg - end - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \r20__data_o$next 4'0000 - end - sync init - update \r20__data_o 4'0000 - sync posedge \coresync_clk - update \r20__data_o \r20__data_o$next - end - process $group_9 - assign \wr_detect$13 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch { \r20__ren } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - case 1'1 - assign \wr_detect$13 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch { \dest10__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - case 1'1 - assign \wr_detect$13 1'1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch { \dest20__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - case 1'1 - assign \wr_detect$13 1'1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch { \w0__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - case 1'1 - assign \wr_detect$13 1'1 - end - end - sync init - end - process $group_10 - assign \reg$next \reg - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" - switch { \dest10__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" - case 1'1 - assign \reg$next \dest10__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" - switch { \dest20__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" - case 1'1 - assign \reg$next \dest20__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" - switch { \w0__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" - case 1'1 - assign \reg$next \w0__data_i - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \reg$next 4'0000 - end - sync init - update \reg 4'0000 - sync posedge \coresync_clk - update \reg \reg$next - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.cr.reg_1" -module \reg_1 - attribute \src "simple/issuer.py:141" - wire width 1 input 0 \coresync_clk - attribute \src "simple/issuer.py:141" - wire width 1 input 1 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 input 2 \src11__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 output 3 \src11__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 \src11__data_o$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 input 4 \src21__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 output 5 \src21__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 \src21__data_o$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 input 6 \src31__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 output 7 \src31__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 \src31__data_o$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 input 8 \dest11__wen - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 input 9 \dest11__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 input 10 \dest21__wen - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 input 11 \dest21__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 output 12 \r1__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 \r1__data_o$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 input 13 \r1__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 output 14 \r21__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 \r21__data_o$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 input 15 \r21__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 input 16 \w1__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 input 17 \w1__wen - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" - wire width 1 \wr_detect - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_detect - connect \Y $1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" - wire width 4 \reg - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" - wire width 4 \reg$next - process $group_0 - assign \src11__data_o$next \src11__data_o - assign \src11__data_o$next 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch { \src11__ren } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch { \dest11__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - case 1'1 - assign \src11__data_o$next \dest11__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch { \dest21__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - case 1'1 - assign \src11__data_o$next \dest21__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch { \w1__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - case 1'1 - assign \src11__data_o$next \w1__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - switch { $1 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - case 1'1 - assign \src11__data_o$next \reg - end - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \src11__data_o$next 4'0000 - end - sync init - update \src11__data_o 4'0000 - sync posedge \coresync_clk - update \src11__data_o \src11__data_o$next - end - process $group_1 - assign \wr_detect 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch { \src11__ren } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - case 1'1 - assign \wr_detect 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch { \dest11__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - case 1'1 - assign \wr_detect 1'1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch { \dest21__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - case 1'1 - assign \wr_detect 1'1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch { \w1__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - case 1'1 - assign \wr_detect 1'1 - end - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - wire width 1 $3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" - wire width 1 \wr_detect$4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $5 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_detect$4 - connect \Y $3 - end - process $group_2 - assign \src21__data_o$next \src21__data_o - assign \src21__data_o$next 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch { \src21__ren } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch { \dest11__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - case 1'1 - assign \src21__data_o$next \dest11__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch { \dest21__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - case 1'1 - assign \src21__data_o$next \dest21__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch { \w1__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - case 1'1 - assign \src21__data_o$next \w1__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - switch { $3 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - case 1'1 - assign \src21__data_o$next \reg - end - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \src21__data_o$next 4'0000 - end - sync init - update \src21__data_o 4'0000 - sync posedge \coresync_clk - update \src21__data_o \src21__data_o$next - end - process $group_3 - assign \wr_detect$4 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch { \src21__ren } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - case 1'1 - assign \wr_detect$4 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch { \dest11__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - case 1'1 - assign \wr_detect$4 1'1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch { \dest21__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - case 1'1 - assign \wr_detect$4 1'1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch { \w1__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - case 1'1 - assign \wr_detect$4 1'1 - end - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - wire width 1 $6 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" - wire width 1 \wr_detect$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $8 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_detect$7 - connect \Y $6 - end - process $group_4 - assign \src31__data_o$next \src31__data_o - assign \src31__data_o$next 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch { \src31__ren } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch { \dest11__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - case 1'1 - assign \src31__data_o$next \dest11__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch { \dest21__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - case 1'1 - assign \src31__data_o$next \dest21__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch { \w1__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - case 1'1 - assign \src31__data_o$next \w1__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - switch { $6 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - case 1'1 - assign \src31__data_o$next \reg - end - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \src31__data_o$next 4'0000 - end - sync init - update \src31__data_o 4'0000 - sync posedge \coresync_clk - update \src31__data_o \src31__data_o$next - end - process $group_5 - assign \wr_detect$7 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch { \src31__ren } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - case 1'1 - assign \wr_detect$7 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch { \dest11__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - case 1'1 - assign \wr_detect$7 1'1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch { \dest21__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - case 1'1 - assign \wr_detect$7 1'1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch { \w1__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - case 1'1 - assign \wr_detect$7 1'1 - end - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - wire width 1 $9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" - wire width 1 \wr_detect$10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $11 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_detect$10 - connect \Y $9 - end - process $group_6 - assign \r1__data_o$next \r1__data_o - assign \r1__data_o$next 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch { \r1__ren } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch { \dest11__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - case 1'1 - assign \r1__data_o$next \dest11__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch { \dest21__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - case 1'1 - assign \r1__data_o$next \dest21__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch { \w1__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - case 1'1 - assign \r1__data_o$next \w1__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - switch { $9 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - case 1'1 - assign \r1__data_o$next \reg - end - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \r1__data_o$next 4'0000 - end - sync init - update \r1__data_o 4'0000 - sync posedge \coresync_clk - update \r1__data_o \r1__data_o$next - end - process $group_7 - assign \wr_detect$10 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch { \r1__ren } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - case 1'1 - assign \wr_detect$10 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch { \dest11__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - case 1'1 - assign \wr_detect$10 1'1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch { \dest21__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - case 1'1 - assign \wr_detect$10 1'1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch { \w1__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - case 1'1 - assign \wr_detect$10 1'1 - end - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - wire width 1 $12 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" - wire width 1 \wr_detect$13 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $14 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_detect$13 - connect \Y $12 - end - process $group_8 - assign \r21__data_o$next \r21__data_o - assign \r21__data_o$next 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch { \r21__ren } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch { \dest11__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - case 1'1 - assign \r21__data_o$next \dest11__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch { \dest21__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - case 1'1 - assign \r21__data_o$next \dest21__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch { \w1__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - case 1'1 - assign \r21__data_o$next \w1__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - switch { $12 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - case 1'1 - assign \r21__data_o$next \reg - end - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \r21__data_o$next 4'0000 - end - sync init - update \r21__data_o 4'0000 - sync posedge \coresync_clk - update \r21__data_o \r21__data_o$next - end - process $group_9 - assign \wr_detect$13 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch { \r21__ren } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - case 1'1 - assign \wr_detect$13 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch { \dest11__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - case 1'1 - assign \wr_detect$13 1'1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch { \dest21__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - case 1'1 - assign \wr_detect$13 1'1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch { \w1__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - case 1'1 - assign \wr_detect$13 1'1 - end - end - sync init - end - process $group_10 - assign \reg$next \reg - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" - switch { \dest11__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" - case 1'1 - assign \reg$next \dest11__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" - switch { \dest21__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" - case 1'1 - assign \reg$next \dest21__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" - switch { \w1__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" - case 1'1 - assign \reg$next \w1__data_i - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \reg$next 4'0000 - end - sync init - update \reg 4'0000 - sync posedge \coresync_clk - update \reg \reg$next - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.cr.reg_2" -module \reg_2 - attribute \src "simple/issuer.py:141" - wire width 1 input 0 \coresync_clk - attribute \src "simple/issuer.py:141" - wire width 1 input 1 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 input 2 \src12__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 output 3 \src12__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 \src12__data_o$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 input 4 \src22__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 output 5 \src22__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 \src22__data_o$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 input 6 \src32__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 output 7 \src32__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 \src32__data_o$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 input 8 \dest12__wen - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 input 9 \dest12__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 input 10 \dest22__wen - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 input 11 \dest22__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 output 12 \r2__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 \r2__data_o$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 input 13 \r2__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 output 14 \r22__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 \r22__data_o$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 input 15 \r22__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 input 16 \w2__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 input 17 \w2__wen - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" - wire width 1 \wr_detect - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_detect - connect \Y $1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" - wire width 4 \reg - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" - wire width 4 \reg$next - process $group_0 - assign \src12__data_o$next \src12__data_o - assign \src12__data_o$next 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch { \src12__ren } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch { \dest12__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - case 1'1 - assign \src12__data_o$next \dest12__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch { \dest22__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - case 1'1 - assign \src12__data_o$next \dest22__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch { \w2__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - case 1'1 - assign \src12__data_o$next \w2__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - switch { $1 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - case 1'1 - assign \src12__data_o$next \reg - end - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \src12__data_o$next 4'0000 - end - sync init - update \src12__data_o 4'0000 - sync posedge \coresync_clk - update \src12__data_o \src12__data_o$next - end - process $group_1 - assign \wr_detect 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch { \src12__ren } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - case 1'1 - assign \wr_detect 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch { \dest12__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - case 1'1 - assign \wr_detect 1'1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch { \dest22__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - case 1'1 - assign \wr_detect 1'1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch { \w2__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - case 1'1 - assign \wr_detect 1'1 - end - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - wire width 1 $3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" - wire width 1 \wr_detect$4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $5 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_detect$4 - connect \Y $3 - end - process $group_2 - assign \src22__data_o$next \src22__data_o - assign \src22__data_o$next 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch { \src22__ren } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch { \dest12__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - case 1'1 - assign \src22__data_o$next \dest12__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch { \dest22__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - case 1'1 - assign \src22__data_o$next \dest22__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch { \w2__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - case 1'1 - assign \src22__data_o$next \w2__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - switch { $3 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - case 1'1 - assign \src22__data_o$next \reg - end - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \src22__data_o$next 4'0000 - end - sync init - update \src22__data_o 4'0000 - sync posedge \coresync_clk - update \src22__data_o \src22__data_o$next - end - process $group_3 - assign \wr_detect$4 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch { \src22__ren } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - case 1'1 - assign \wr_detect$4 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch { \dest12__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - case 1'1 - assign \wr_detect$4 1'1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch { \dest22__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - case 1'1 - assign \wr_detect$4 1'1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch { \w2__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - case 1'1 - assign \wr_detect$4 1'1 - end - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - wire width 1 $6 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" - wire width 1 \wr_detect$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $8 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_detect$7 - connect \Y $6 - end - process $group_4 - assign \src32__data_o$next \src32__data_o - assign \src32__data_o$next 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch { \src32__ren } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch { \dest12__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - case 1'1 - assign \src32__data_o$next \dest12__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch { \dest22__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - case 1'1 - assign \src32__data_o$next \dest22__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch { \w2__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - case 1'1 - assign \src32__data_o$next \w2__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - switch { $6 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - case 1'1 - assign \src32__data_o$next \reg - end - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \src32__data_o$next 4'0000 - end - sync init - update \src32__data_o 4'0000 - sync posedge \coresync_clk - update \src32__data_o \src32__data_o$next - end - process $group_5 - assign \wr_detect$7 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch { \src32__ren } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - case 1'1 - assign \wr_detect$7 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch { \dest12__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - case 1'1 - assign \wr_detect$7 1'1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch { \dest22__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - case 1'1 - assign \wr_detect$7 1'1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch { \w2__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - case 1'1 - assign \wr_detect$7 1'1 - end - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - wire width 1 $9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" - wire width 1 \wr_detect$10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $11 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_detect$10 - connect \Y $9 - end - process $group_6 - assign \r2__data_o$next \r2__data_o - assign \r2__data_o$next 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch { \r2__ren } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch { \dest12__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - case 1'1 - assign \r2__data_o$next \dest12__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch { \dest22__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - case 1'1 - assign \r2__data_o$next \dest22__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch { \w2__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - case 1'1 - assign \r2__data_o$next \w2__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - switch { $9 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - case 1'1 - assign \r2__data_o$next \reg - end - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \r2__data_o$next 4'0000 - end - sync init - update \r2__data_o 4'0000 - sync posedge \coresync_clk - update \r2__data_o \r2__data_o$next - end - process $group_7 - assign \wr_detect$10 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch { \r2__ren } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - case 1'1 - assign \wr_detect$10 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch { \dest12__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - case 1'1 - assign \wr_detect$10 1'1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch { \dest22__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - case 1'1 - assign \wr_detect$10 1'1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch { \w2__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - case 1'1 - assign \wr_detect$10 1'1 - end - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - wire width 1 $12 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" - wire width 1 \wr_detect$13 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $14 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_detect$13 - connect \Y $12 - end - process $group_8 - assign \r22__data_o$next \r22__data_o - assign \r22__data_o$next 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch { \r22__ren } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch { \dest12__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - case 1'1 - assign \r22__data_o$next \dest12__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch { \dest22__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - case 1'1 - assign \r22__data_o$next \dest22__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch { \w2__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - case 1'1 - assign \r22__data_o$next \w2__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - switch { $12 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - case 1'1 - assign \r22__data_o$next \reg - end - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \r22__data_o$next 4'0000 - end - sync init - update \r22__data_o 4'0000 - sync posedge \coresync_clk - update \r22__data_o \r22__data_o$next - end - process $group_9 - assign \wr_detect$13 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch { \r22__ren } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - case 1'1 - assign \wr_detect$13 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch { \dest12__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - case 1'1 - assign \wr_detect$13 1'1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch { \dest22__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - case 1'1 - assign \wr_detect$13 1'1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch { \w2__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - case 1'1 - assign \wr_detect$13 1'1 - end - end - sync init - end - process $group_10 - assign \reg$next \reg - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" - switch { \dest12__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" - case 1'1 - assign \reg$next \dest12__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" - switch { \dest22__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" - case 1'1 - assign \reg$next \dest22__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" - switch { \w2__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" - case 1'1 - assign \reg$next \w2__data_i - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \reg$next 4'0000 - end - sync init - update \reg 4'0000 - sync posedge \coresync_clk - update \reg \reg$next - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.cr.reg_3" -module \reg_3 - attribute \src "simple/issuer.py:141" - wire width 1 input 0 \coresync_clk - attribute \src "simple/issuer.py:141" - wire width 1 input 1 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 input 2 \src13__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 output 3 \src13__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 \src13__data_o$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 input 4 \src23__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 output 5 \src23__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 \src23__data_o$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 input 6 \src33__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 output 7 \src33__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 \src33__data_o$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 input 8 \dest13__wen - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 input 9 \dest13__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 input 10 \dest23__wen - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 input 11 \dest23__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 output 12 \r3__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 \r3__data_o$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 input 13 \r3__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 output 14 \r23__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 \r23__data_o$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 input 15 \r23__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 input 16 \w3__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 input 17 \w3__wen - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" - wire width 1 \wr_detect - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_detect - connect \Y $1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" - wire width 4 \reg - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" - wire width 4 \reg$next - process $group_0 - assign \src13__data_o$next \src13__data_o - assign \src13__data_o$next 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch { \src13__ren } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch { \dest13__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - case 1'1 - assign \src13__data_o$next \dest13__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch { \dest23__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - case 1'1 - assign \src13__data_o$next \dest23__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch { \w3__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - case 1'1 - assign \src13__data_o$next \w3__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - switch { $1 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - case 1'1 - assign \src13__data_o$next \reg - end - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \src13__data_o$next 4'0000 - end - sync init - update \src13__data_o 4'0000 - sync posedge \coresync_clk - update \src13__data_o \src13__data_o$next - end - process $group_1 - assign \wr_detect 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch { \src13__ren } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - case 1'1 - assign \wr_detect 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch { \dest13__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - case 1'1 - assign \wr_detect 1'1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch { \dest23__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - case 1'1 - assign \wr_detect 1'1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch { \w3__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - case 1'1 - assign \wr_detect 1'1 - end - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - wire width 1 $3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" - wire width 1 \wr_detect$4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $5 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_detect$4 - connect \Y $3 - end - process $group_2 - assign \src23__data_o$next \src23__data_o - assign \src23__data_o$next 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch { \src23__ren } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch { \dest13__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - case 1'1 - assign \src23__data_o$next \dest13__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch { \dest23__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - case 1'1 - assign \src23__data_o$next \dest23__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch { \w3__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - case 1'1 - assign \src23__data_o$next \w3__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - switch { $3 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - case 1'1 - assign \src23__data_o$next \reg - end - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \src23__data_o$next 4'0000 - end - sync init - update \src23__data_o 4'0000 - sync posedge \coresync_clk - update \src23__data_o \src23__data_o$next - end - process $group_3 - assign \wr_detect$4 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch { \src23__ren } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - case 1'1 - assign \wr_detect$4 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch { \dest13__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - case 1'1 - assign \wr_detect$4 1'1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch { \dest23__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - case 1'1 - assign \wr_detect$4 1'1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch { \w3__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - case 1'1 - assign \wr_detect$4 1'1 - end - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - wire width 1 $6 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" - wire width 1 \wr_detect$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $8 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_detect$7 - connect \Y $6 - end - process $group_4 - assign \src33__data_o$next \src33__data_o - assign \src33__data_o$next 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch { \src33__ren } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch { \dest13__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - case 1'1 - assign \src33__data_o$next \dest13__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch { \dest23__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - case 1'1 - assign \src33__data_o$next \dest23__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch { \w3__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - case 1'1 - assign \src33__data_o$next \w3__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - switch { $6 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - case 1'1 - assign \src33__data_o$next \reg - end - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \src33__data_o$next 4'0000 - end - sync init - update \src33__data_o 4'0000 - sync posedge \coresync_clk - update \src33__data_o \src33__data_o$next - end - process $group_5 - assign \wr_detect$7 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch { \src33__ren } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - case 1'1 - assign \wr_detect$7 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch { \dest13__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - case 1'1 - assign \wr_detect$7 1'1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch { \dest23__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - case 1'1 - assign \wr_detect$7 1'1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch { \w3__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - case 1'1 - assign \wr_detect$7 1'1 - end - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - wire width 1 $9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" - wire width 1 \wr_detect$10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $11 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_detect$10 - connect \Y $9 - end - process $group_6 - assign \r3__data_o$next \r3__data_o - assign \r3__data_o$next 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch { \r3__ren } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch { \dest13__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - case 1'1 - assign \r3__data_o$next \dest13__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch { \dest23__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - case 1'1 - assign \r3__data_o$next \dest23__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch { \w3__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - case 1'1 - assign \r3__data_o$next \w3__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - switch { $9 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - case 1'1 - assign \r3__data_o$next \reg - end - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \r3__data_o$next 4'0000 - end - sync init - update \r3__data_o 4'0000 - sync posedge \coresync_clk - update \r3__data_o \r3__data_o$next - end - process $group_7 - assign \wr_detect$10 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch { \r3__ren } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - case 1'1 - assign \wr_detect$10 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch { \dest13__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - case 1'1 - assign \wr_detect$10 1'1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch { \dest23__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - case 1'1 - assign \wr_detect$10 1'1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch { \w3__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - case 1'1 - assign \wr_detect$10 1'1 - end - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - wire width 1 $12 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" - wire width 1 \wr_detect$13 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $14 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_detect$13 - connect \Y $12 - end - process $group_8 - assign \r23__data_o$next \r23__data_o - assign \r23__data_o$next 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch { \r23__ren } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch { \dest13__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - case 1'1 - assign \r23__data_o$next \dest13__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch { \dest23__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - case 1'1 - assign \r23__data_o$next \dest23__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch { \w3__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - case 1'1 - assign \r23__data_o$next \w3__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - switch { $12 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - case 1'1 - assign \r23__data_o$next \reg - end - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \r23__data_o$next 4'0000 - end - sync init - update \r23__data_o 4'0000 - sync posedge \coresync_clk - update \r23__data_o \r23__data_o$next - end - process $group_9 - assign \wr_detect$13 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch { \r23__ren } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - case 1'1 - assign \wr_detect$13 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch { \dest13__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - case 1'1 - assign \wr_detect$13 1'1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch { \dest23__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - case 1'1 - assign \wr_detect$13 1'1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch { \w3__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - case 1'1 - assign \wr_detect$13 1'1 - end - end - sync init - end - process $group_10 - assign \reg$next \reg - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" - switch { \dest13__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" - case 1'1 - assign \reg$next \dest13__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" - switch { \dest23__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" - case 1'1 - assign \reg$next \dest23__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" - switch { \w3__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" - case 1'1 - assign \reg$next \w3__data_i - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \reg$next 4'0000 - end - sync init - update \reg 4'0000 - sync posedge \coresync_clk - update \reg \reg$next - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.cr.reg_4" -module \reg_4 - attribute \src "simple/issuer.py:141" - wire width 1 input 0 \coresync_clk - attribute \src "simple/issuer.py:141" - wire width 1 input 1 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 input 2 \src14__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 output 3 \src14__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 \src14__data_o$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 input 4 \src24__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 output 5 \src24__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 \src24__data_o$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 input 6 \src34__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 output 7 \src34__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 \src34__data_o$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 input 8 \dest14__wen - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 input 9 \dest14__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 input 10 \dest24__wen - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 input 11 \dest24__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 output 12 \r4__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 \r4__data_o$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 input 13 \r4__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 output 14 \r24__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 \r24__data_o$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 input 15 \r24__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 input 16 \w4__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 input 17 \w4__wen - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" - wire width 1 \wr_detect - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_detect - connect \Y $1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" - wire width 4 \reg - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" - wire width 4 \reg$next - process $group_0 - assign \src14__data_o$next \src14__data_o - assign \src14__data_o$next 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch { \src14__ren } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch { \dest14__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - case 1'1 - assign \src14__data_o$next \dest14__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch { \dest24__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - case 1'1 - assign \src14__data_o$next \dest24__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch { \w4__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - case 1'1 - assign \src14__data_o$next \w4__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - switch { $1 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - case 1'1 - assign \src14__data_o$next \reg - end - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \src14__data_o$next 4'0000 - end - sync init - update \src14__data_o 4'0000 - sync posedge \coresync_clk - update \src14__data_o \src14__data_o$next - end - process $group_1 - assign \wr_detect 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch { \src14__ren } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - case 1'1 - assign \wr_detect 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch { \dest14__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - case 1'1 - assign \wr_detect 1'1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch { \dest24__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - case 1'1 - assign \wr_detect 1'1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch { \w4__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - case 1'1 - assign \wr_detect 1'1 - end - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - wire width 1 $3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" - wire width 1 \wr_detect$4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $5 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_detect$4 - connect \Y $3 - end - process $group_2 - assign \src24__data_o$next \src24__data_o - assign \src24__data_o$next 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch { \src24__ren } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch { \dest14__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - case 1'1 - assign \src24__data_o$next \dest14__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch { \dest24__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - case 1'1 - assign \src24__data_o$next \dest24__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch { \w4__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - case 1'1 - assign \src24__data_o$next \w4__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - switch { $3 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - case 1'1 - assign \src24__data_o$next \reg - end - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \src24__data_o$next 4'0000 - end - sync init - update \src24__data_o 4'0000 - sync posedge \coresync_clk - update \src24__data_o \src24__data_o$next - end - process $group_3 - assign \wr_detect$4 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch { \src24__ren } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - case 1'1 - assign \wr_detect$4 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch { \dest14__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - case 1'1 - assign \wr_detect$4 1'1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch { \dest24__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - case 1'1 - assign \wr_detect$4 1'1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch { \w4__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - case 1'1 - assign \wr_detect$4 1'1 - end - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - wire width 1 $6 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" - wire width 1 \wr_detect$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $8 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_detect$7 - connect \Y $6 - end - process $group_4 - assign \src34__data_o$next \src34__data_o - assign \src34__data_o$next 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch { \src34__ren } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch { \dest14__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - case 1'1 - assign \src34__data_o$next \dest14__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch { \dest24__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - case 1'1 - assign \src34__data_o$next \dest24__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch { \w4__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - case 1'1 - assign \src34__data_o$next \w4__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - switch { $6 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - case 1'1 - assign \src34__data_o$next \reg - end - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \src34__data_o$next 4'0000 - end - sync init - update \src34__data_o 4'0000 - sync posedge \coresync_clk - update \src34__data_o \src34__data_o$next - end - process $group_5 - assign \wr_detect$7 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch { \src34__ren } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - case 1'1 - assign \wr_detect$7 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch { \dest14__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - case 1'1 - assign \wr_detect$7 1'1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch { \dest24__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - case 1'1 - assign \wr_detect$7 1'1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch { \w4__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - case 1'1 - assign \wr_detect$7 1'1 - end - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - wire width 1 $9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" - wire width 1 \wr_detect$10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $11 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_detect$10 - connect \Y $9 - end - process $group_6 - assign \r4__data_o$next \r4__data_o - assign \r4__data_o$next 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch { \r4__ren } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch { \dest14__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - case 1'1 - assign \r4__data_o$next \dest14__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch { \dest24__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - case 1'1 - assign \r4__data_o$next \dest24__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch { \w4__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - case 1'1 - assign \r4__data_o$next \w4__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - switch { $9 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - case 1'1 - assign \r4__data_o$next \reg - end - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \r4__data_o$next 4'0000 - end - sync init - update \r4__data_o 4'0000 - sync posedge \coresync_clk - update \r4__data_o \r4__data_o$next - end - process $group_7 - assign \wr_detect$10 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch { \r4__ren } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - case 1'1 - assign \wr_detect$10 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch { \dest14__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - case 1'1 - assign \wr_detect$10 1'1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch { \dest24__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - case 1'1 - assign \wr_detect$10 1'1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch { \w4__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - case 1'1 - assign \wr_detect$10 1'1 - end - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - wire width 1 $12 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" - wire width 1 \wr_detect$13 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $14 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_detect$13 - connect \Y $12 - end - process $group_8 - assign \r24__data_o$next \r24__data_o - assign \r24__data_o$next 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch { \r24__ren } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch { \dest14__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - case 1'1 - assign \r24__data_o$next \dest14__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch { \dest24__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - case 1'1 - assign \r24__data_o$next \dest24__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch { \w4__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - case 1'1 - assign \r24__data_o$next \w4__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - switch { $12 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - case 1'1 - assign \r24__data_o$next \reg - end - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \r24__data_o$next 4'0000 - end - sync init - update \r24__data_o 4'0000 - sync posedge \coresync_clk - update \r24__data_o \r24__data_o$next - end - process $group_9 - assign \wr_detect$13 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch { \r24__ren } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - case 1'1 - assign \wr_detect$13 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch { \dest14__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - case 1'1 - assign \wr_detect$13 1'1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch { \dest24__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - case 1'1 - assign \wr_detect$13 1'1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch { \w4__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - case 1'1 - assign \wr_detect$13 1'1 - end - end - sync init - end - process $group_10 - assign \reg$next \reg - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" - switch { \dest14__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" - case 1'1 - assign \reg$next \dest14__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" - switch { \dest24__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" - case 1'1 - assign \reg$next \dest24__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" - switch { \w4__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" - case 1'1 - assign \reg$next \w4__data_i - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \reg$next 4'0000 - end - sync init - update \reg 4'0000 - sync posedge \coresync_clk - update \reg \reg$next - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.cr.reg_5" -module \reg_5 - attribute \src "simple/issuer.py:141" - wire width 1 input 0 \coresync_clk - attribute \src "simple/issuer.py:141" - wire width 1 input 1 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 input 2 \src15__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 output 3 \src15__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 \src15__data_o$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 input 4 \src25__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 output 5 \src25__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 \src25__data_o$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 input 6 \src35__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 output 7 \src35__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 \src35__data_o$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 input 8 \dest15__wen - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 input 9 \dest15__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 input 10 \dest25__wen - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 input 11 \dest25__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 output 12 \r5__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 \r5__data_o$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 input 13 \r5__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 output 14 \r25__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 \r25__data_o$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 input 15 \r25__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 input 16 \w5__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 input 17 \w5__wen - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" - wire width 1 \wr_detect - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_detect - connect \Y $1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" - wire width 4 \reg - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" - wire width 4 \reg$next - process $group_0 - assign \src15__data_o$next \src15__data_o - assign \src15__data_o$next 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch { \src15__ren } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch { \dest15__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - case 1'1 - assign \src15__data_o$next \dest15__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch { \dest25__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - case 1'1 - assign \src15__data_o$next \dest25__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch { \w5__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - case 1'1 - assign \src15__data_o$next \w5__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - switch { $1 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - case 1'1 - assign \src15__data_o$next \reg - end - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \src15__data_o$next 4'0000 - end - sync init - update \src15__data_o 4'0000 - sync posedge \coresync_clk - update \src15__data_o \src15__data_o$next - end - process $group_1 - assign \wr_detect 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch { \src15__ren } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - case 1'1 - assign \wr_detect 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch { \dest15__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - case 1'1 - assign \wr_detect 1'1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch { \dest25__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - case 1'1 - assign \wr_detect 1'1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch { \w5__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - case 1'1 - assign \wr_detect 1'1 - end - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - wire width 1 $3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" - wire width 1 \wr_detect$4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $5 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_detect$4 - connect \Y $3 - end - process $group_2 - assign \src25__data_o$next \src25__data_o - assign \src25__data_o$next 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch { \src25__ren } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch { \dest15__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - case 1'1 - assign \src25__data_o$next \dest15__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch { \dest25__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - case 1'1 - assign \src25__data_o$next \dest25__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch { \w5__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - case 1'1 - assign \src25__data_o$next \w5__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - switch { $3 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - case 1'1 - assign \src25__data_o$next \reg - end - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \src25__data_o$next 4'0000 - end - sync init - update \src25__data_o 4'0000 - sync posedge \coresync_clk - update \src25__data_o \src25__data_o$next - end - process $group_3 - assign \wr_detect$4 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch { \src25__ren } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - case 1'1 - assign \wr_detect$4 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch { \dest15__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - case 1'1 - assign \wr_detect$4 1'1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch { \dest25__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - case 1'1 - assign \wr_detect$4 1'1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch { \w5__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - case 1'1 - assign \wr_detect$4 1'1 - end - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - wire width 1 $6 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" - wire width 1 \wr_detect$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $8 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_detect$7 - connect \Y $6 - end - process $group_4 - assign \src35__data_o$next \src35__data_o - assign \src35__data_o$next 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch { \src35__ren } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch { \dest15__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - case 1'1 - assign \src35__data_o$next \dest15__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch { \dest25__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - case 1'1 - assign \src35__data_o$next \dest25__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch { \w5__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - case 1'1 - assign \src35__data_o$next \w5__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - switch { $6 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - case 1'1 - assign \src35__data_o$next \reg - end - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \src35__data_o$next 4'0000 - end - sync init - update \src35__data_o 4'0000 - sync posedge \coresync_clk - update \src35__data_o \src35__data_o$next - end - process $group_5 - assign \wr_detect$7 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch { \src35__ren } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - case 1'1 - assign \wr_detect$7 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch { \dest15__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - case 1'1 - assign \wr_detect$7 1'1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch { \dest25__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - case 1'1 - assign \wr_detect$7 1'1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch { \w5__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - case 1'1 - assign \wr_detect$7 1'1 - end - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - wire width 1 $9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" - wire width 1 \wr_detect$10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $11 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_detect$10 - connect \Y $9 - end - process $group_6 - assign \r5__data_o$next \r5__data_o - assign \r5__data_o$next 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch { \r5__ren } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch { \dest15__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - case 1'1 - assign \r5__data_o$next \dest15__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch { \dest25__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - case 1'1 - assign \r5__data_o$next \dest25__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch { \w5__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - case 1'1 - assign \r5__data_o$next \w5__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - switch { $9 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - case 1'1 - assign \r5__data_o$next \reg - end - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \r5__data_o$next 4'0000 - end - sync init - update \r5__data_o 4'0000 - sync posedge \coresync_clk - update \r5__data_o \r5__data_o$next - end - process $group_7 - assign \wr_detect$10 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch { \r5__ren } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - case 1'1 - assign \wr_detect$10 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch { \dest15__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - case 1'1 - assign \wr_detect$10 1'1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch { \dest25__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - case 1'1 - assign \wr_detect$10 1'1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch { \w5__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - case 1'1 - assign \wr_detect$10 1'1 - end - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - wire width 1 $12 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" - wire width 1 \wr_detect$13 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $14 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_detect$13 - connect \Y $12 - end - process $group_8 - assign \r25__data_o$next \r25__data_o - assign \r25__data_o$next 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch { \r25__ren } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch { \dest15__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - case 1'1 - assign \r25__data_o$next \dest15__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch { \dest25__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - case 1'1 - assign \r25__data_o$next \dest25__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch { \w5__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - case 1'1 - assign \r25__data_o$next \w5__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - switch { $12 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - case 1'1 - assign \r25__data_o$next \reg - end - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \r25__data_o$next 4'0000 - end - sync init - update \r25__data_o 4'0000 - sync posedge \coresync_clk - update \r25__data_o \r25__data_o$next - end - process $group_9 - assign \wr_detect$13 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch { \r25__ren } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - case 1'1 - assign \wr_detect$13 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch { \dest15__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - case 1'1 - assign \wr_detect$13 1'1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch { \dest25__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - case 1'1 - assign \wr_detect$13 1'1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch { \w5__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - case 1'1 - assign \wr_detect$13 1'1 - end - end - sync init - end - process $group_10 - assign \reg$next \reg - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" - switch { \dest15__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" - case 1'1 - assign \reg$next \dest15__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" - switch { \dest25__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" - case 1'1 - assign \reg$next \dest25__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" - switch { \w5__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" - case 1'1 - assign \reg$next \w5__data_i - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \reg$next 4'0000 - end - sync init - update \reg 4'0000 - sync posedge \coresync_clk - update \reg \reg$next - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.cr.reg_6" -module \reg_6 - attribute \src "simple/issuer.py:141" - wire width 1 input 0 \coresync_clk - attribute \src "simple/issuer.py:141" - wire width 1 input 1 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 input 2 \src16__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 output 3 \src16__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 \src16__data_o$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 input 4 \src26__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 output 5 \src26__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 \src26__data_o$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 input 6 \src36__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 output 7 \src36__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 \src36__data_o$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 input 8 \dest16__wen - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 input 9 \dest16__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 input 10 \dest26__wen - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 input 11 \dest26__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 output 12 \r6__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 \r6__data_o$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 input 13 \r6__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 output 14 \r26__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 \r26__data_o$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 input 15 \r26__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 input 16 \w6__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 input 17 \w6__wen - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" - wire width 1 \wr_detect - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_detect - connect \Y $1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" - wire width 4 \reg - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" - wire width 4 \reg$next - process $group_0 - assign \src16__data_o$next \src16__data_o - assign \src16__data_o$next 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch { \src16__ren } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch { \dest16__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - case 1'1 - assign \src16__data_o$next \dest16__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch { \dest26__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - case 1'1 - assign \src16__data_o$next \dest26__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch { \w6__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - case 1'1 - assign \src16__data_o$next \w6__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - switch { $1 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - case 1'1 - assign \src16__data_o$next \reg - end - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \src16__data_o$next 4'0000 - end - sync init - update \src16__data_o 4'0000 - sync posedge \coresync_clk - update \src16__data_o \src16__data_o$next - end - process $group_1 - assign \wr_detect 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch { \src16__ren } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - case 1'1 - assign \wr_detect 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch { \dest16__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - case 1'1 - assign \wr_detect 1'1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch { \dest26__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - case 1'1 - assign \wr_detect 1'1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch { \w6__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - case 1'1 - assign \wr_detect 1'1 - end - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - wire width 1 $3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" - wire width 1 \wr_detect$4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $5 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_detect$4 - connect \Y $3 - end - process $group_2 - assign \src26__data_o$next \src26__data_o - assign \src26__data_o$next 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch { \src26__ren } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch { \dest16__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - case 1'1 - assign \src26__data_o$next \dest16__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch { \dest26__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - case 1'1 - assign \src26__data_o$next \dest26__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch { \w6__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - case 1'1 - assign \src26__data_o$next \w6__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - switch { $3 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - case 1'1 - assign \src26__data_o$next \reg - end - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \src26__data_o$next 4'0000 - end - sync init - update \src26__data_o 4'0000 - sync posedge \coresync_clk - update \src26__data_o \src26__data_o$next - end - process $group_3 - assign \wr_detect$4 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch { \src26__ren } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - case 1'1 - assign \wr_detect$4 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch { \dest16__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - case 1'1 - assign \wr_detect$4 1'1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch { \dest26__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - case 1'1 - assign \wr_detect$4 1'1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch { \w6__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - case 1'1 - assign \wr_detect$4 1'1 - end - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - wire width 1 $6 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" - wire width 1 \wr_detect$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $8 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_detect$7 - connect \Y $6 - end - process $group_4 - assign \src36__data_o$next \src36__data_o - assign \src36__data_o$next 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch { \src36__ren } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch { \dest16__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - case 1'1 - assign \src36__data_o$next \dest16__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch { \dest26__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - case 1'1 - assign \src36__data_o$next \dest26__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch { \w6__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - case 1'1 - assign \src36__data_o$next \w6__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - switch { $6 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - case 1'1 - assign \src36__data_o$next \reg - end - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \src36__data_o$next 4'0000 - end - sync init - update \src36__data_o 4'0000 - sync posedge \coresync_clk - update \src36__data_o \src36__data_o$next - end - process $group_5 - assign \wr_detect$7 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch { \src36__ren } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - case 1'1 - assign \wr_detect$7 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch { \dest16__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - case 1'1 - assign \wr_detect$7 1'1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch { \dest26__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - case 1'1 - assign \wr_detect$7 1'1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch { \w6__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - case 1'1 - assign \wr_detect$7 1'1 - end - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - wire width 1 $9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" - wire width 1 \wr_detect$10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $11 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_detect$10 - connect \Y $9 - end - process $group_6 - assign \r6__data_o$next \r6__data_o - assign \r6__data_o$next 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch { \r6__ren } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch { \dest16__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - case 1'1 - assign \r6__data_o$next \dest16__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch { \dest26__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - case 1'1 - assign \r6__data_o$next \dest26__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch { \w6__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - case 1'1 - assign \r6__data_o$next \w6__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - switch { $9 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - case 1'1 - assign \r6__data_o$next \reg - end - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \r6__data_o$next 4'0000 - end - sync init - update \r6__data_o 4'0000 - sync posedge \coresync_clk - update \r6__data_o \r6__data_o$next - end - process $group_7 - assign \wr_detect$10 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch { \r6__ren } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - case 1'1 - assign \wr_detect$10 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch { \dest16__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - case 1'1 - assign \wr_detect$10 1'1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch { \dest26__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - case 1'1 - assign \wr_detect$10 1'1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch { \w6__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - case 1'1 - assign \wr_detect$10 1'1 - end - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - wire width 1 $12 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" - wire width 1 \wr_detect$13 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $14 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_detect$13 - connect \Y $12 - end - process $group_8 - assign \r26__data_o$next \r26__data_o - assign \r26__data_o$next 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch { \r26__ren } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch { \dest16__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - case 1'1 - assign \r26__data_o$next \dest16__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch { \dest26__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - case 1'1 - assign \r26__data_o$next \dest26__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch { \w6__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - case 1'1 - assign \r26__data_o$next \w6__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - switch { $12 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - case 1'1 - assign \r26__data_o$next \reg - end - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \r26__data_o$next 4'0000 - end - sync init - update \r26__data_o 4'0000 - sync posedge \coresync_clk - update \r26__data_o \r26__data_o$next - end - process $group_9 - assign \wr_detect$13 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch { \r26__ren } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - case 1'1 - assign \wr_detect$13 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch { \dest16__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - case 1'1 - assign \wr_detect$13 1'1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch { \dest26__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - case 1'1 - assign \wr_detect$13 1'1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch { \w6__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - case 1'1 - assign \wr_detect$13 1'1 - end - end - sync init - end - process $group_10 - assign \reg$next \reg - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" - switch { \dest16__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" - case 1'1 - assign \reg$next \dest16__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" - switch { \dest26__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" - case 1'1 - assign \reg$next \dest26__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" - switch { \w6__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" - case 1'1 - assign \reg$next \w6__data_i - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \reg$next 4'0000 - end - sync init - update \reg 4'0000 - sync posedge \coresync_clk - update \reg \reg$next - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.cr.reg_7" -module \reg_7 - attribute \src "simple/issuer.py:141" - wire width 1 input 0 \coresync_clk - attribute \src "simple/issuer.py:141" - wire width 1 input 1 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 input 2 \src17__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 output 3 \src17__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 \src17__data_o$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 input 4 \src27__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 output 5 \src27__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 \src27__data_o$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 input 6 \src37__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 output 7 \src37__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 \src37__data_o$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 input 8 \dest17__wen - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 input 9 \dest17__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 input 10 \dest27__wen - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 input 11 \dest27__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 output 12 \r7__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 \r7__data_o$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 input 13 \r7__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 output 14 \r27__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 \r27__data_o$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 input 15 \r27__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 input 16 \w7__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 input 17 \w7__wen - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" - wire width 1 \wr_detect - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_detect - connect \Y $1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" - wire width 4 \reg - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" - wire width 4 \reg$next - process $group_0 - assign \src17__data_o$next \src17__data_o - assign \src17__data_o$next 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch { \src17__ren } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch { \dest17__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - case 1'1 - assign \src17__data_o$next \dest17__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch { \dest27__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - case 1'1 - assign \src17__data_o$next \dest27__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch { \w7__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - case 1'1 - assign \src17__data_o$next \w7__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - switch { $1 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - case 1'1 - assign \src17__data_o$next \reg - end - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \src17__data_o$next 4'0000 - end - sync init - update \src17__data_o 4'0000 - sync posedge \coresync_clk - update \src17__data_o \src17__data_o$next - end - process $group_1 - assign \wr_detect 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch { \src17__ren } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - case 1'1 - assign \wr_detect 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch { \dest17__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - case 1'1 - assign \wr_detect 1'1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch { \dest27__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - case 1'1 - assign \wr_detect 1'1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch { \w7__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - case 1'1 - assign \wr_detect 1'1 - end - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - wire width 1 $3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" - wire width 1 \wr_detect$4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $5 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_detect$4 - connect \Y $3 - end - process $group_2 - assign \src27__data_o$next \src27__data_o - assign \src27__data_o$next 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch { \src27__ren } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch { \dest17__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - case 1'1 - assign \src27__data_o$next \dest17__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch { \dest27__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - case 1'1 - assign \src27__data_o$next \dest27__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch { \w7__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - case 1'1 - assign \src27__data_o$next \w7__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - switch { $3 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - case 1'1 - assign \src27__data_o$next \reg - end - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \src27__data_o$next 4'0000 - end - sync init - update \src27__data_o 4'0000 - sync posedge \coresync_clk - update \src27__data_o \src27__data_o$next - end - process $group_3 - assign \wr_detect$4 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch { \src27__ren } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - case 1'1 - assign \wr_detect$4 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch { \dest17__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - case 1'1 - assign \wr_detect$4 1'1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch { \dest27__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - case 1'1 - assign \wr_detect$4 1'1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch { \w7__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - case 1'1 - assign \wr_detect$4 1'1 - end - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - wire width 1 $6 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" - wire width 1 \wr_detect$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $8 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_detect$7 - connect \Y $6 - end - process $group_4 - assign \src37__data_o$next \src37__data_o - assign \src37__data_o$next 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch { \src37__ren } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch { \dest17__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - case 1'1 - assign \src37__data_o$next \dest17__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch { \dest27__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - case 1'1 - assign \src37__data_o$next \dest27__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch { \w7__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - case 1'1 - assign \src37__data_o$next \w7__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - switch { $6 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - case 1'1 - assign \src37__data_o$next \reg - end - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \src37__data_o$next 4'0000 - end - sync init - update \src37__data_o 4'0000 - sync posedge \coresync_clk - update \src37__data_o \src37__data_o$next - end - process $group_5 - assign \wr_detect$7 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch { \src37__ren } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - case 1'1 - assign \wr_detect$7 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch { \dest17__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - case 1'1 - assign \wr_detect$7 1'1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch { \dest27__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - case 1'1 - assign \wr_detect$7 1'1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch { \w7__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - case 1'1 - assign \wr_detect$7 1'1 - end - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - wire width 1 $9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" - wire width 1 \wr_detect$10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $11 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_detect$10 - connect \Y $9 - end - process $group_6 - assign \r7__data_o$next \r7__data_o - assign \r7__data_o$next 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch { \r7__ren } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch { \dest17__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - case 1'1 - assign \r7__data_o$next \dest17__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch { \dest27__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - case 1'1 - assign \r7__data_o$next \dest27__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch { \w7__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - case 1'1 - assign \r7__data_o$next \w7__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - switch { $9 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - case 1'1 - assign \r7__data_o$next \reg - end - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \r7__data_o$next 4'0000 - end - sync init - update \r7__data_o 4'0000 - sync posedge \coresync_clk - update \r7__data_o \r7__data_o$next - end - process $group_7 - assign \wr_detect$10 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch { \r7__ren } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - case 1'1 - assign \wr_detect$10 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch { \dest17__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - case 1'1 - assign \wr_detect$10 1'1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch { \dest27__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - case 1'1 - assign \wr_detect$10 1'1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch { \w7__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - case 1'1 - assign \wr_detect$10 1'1 - end - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - wire width 1 $12 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" - wire width 1 \wr_detect$13 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $14 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_detect$13 - connect \Y $12 - end - process $group_8 - assign \r27__data_o$next \r27__data_o - assign \r27__data_o$next 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch { \r27__ren } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch { \dest17__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - case 1'1 - assign \r27__data_o$next \dest17__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch { \dest27__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - case 1'1 - assign \r27__data_o$next \dest27__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch { \w7__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - case 1'1 - assign \r27__data_o$next \w7__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - switch { $12 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - case 1'1 - assign \r27__data_o$next \reg - end - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \r27__data_o$next 4'0000 - end - sync init - update \r27__data_o 4'0000 - sync posedge \coresync_clk - update \r27__data_o \r27__data_o$next - end - process $group_9 - assign \wr_detect$13 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch { \r27__ren } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - case 1'1 - assign \wr_detect$13 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch { \dest17__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - case 1'1 - assign \wr_detect$13 1'1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch { \dest27__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - case 1'1 - assign \wr_detect$13 1'1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch { \w7__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - case 1'1 - assign \wr_detect$13 1'1 - end - end - sync init - end - process $group_10 - assign \reg$next \reg - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" - switch { \dest17__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" - case 1'1 - assign \reg$next \dest17__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" - switch { \dest27__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" - case 1'1 - assign \reg$next \dest27__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" - switch { \w7__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" - case 1'1 - assign \reg$next \w7__data_i - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \reg$next 4'0000 - end - sync init - update \reg 4'0000 - sync posedge \coresync_clk - update \reg \reg$next - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.cr" -module \cr - attribute \src "simple/issuer.py:141" - wire width 1 input 0 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 8 input 1 \full_rd2__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 32 output 2 \full_rd2__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 32 output 3 \full_rd__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 8 input 4 \full_rd__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 output 5 \src1__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 8 input 6 \src1__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 output 7 \src2__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 8 input 8 \src2__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 output 9 \src3__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 8 input 10 \src3__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 32 input 11 \full_wr__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 8 input 12 \full_wr__wen - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 input 13 \data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 8 input 14 \wen - attribute \src "simple/issuer.py:141" - wire width 1 input 15 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 \reg_0_src10__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 \reg_0_src10__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 \reg_0_src20__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 \reg_0_src20__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 \reg_0_src30__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 \reg_0_src30__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 \reg_0_dest10__wen - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 \reg_0_dest10__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 \reg_0_dest20__wen - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 \reg_0_dest20__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 \reg_0_r0__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 \reg_0_r0__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 \reg_0_r20__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 \reg_0_r20__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 \reg_0_w0__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 \reg_0_w0__wen - cell \reg_0 \reg_0 - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \src10__ren \reg_0_src10__ren - connect \src10__data_o \reg_0_src10__data_o - connect \src20__ren \reg_0_src20__ren - connect \src20__data_o \reg_0_src20__data_o - connect \src30__ren \reg_0_src30__ren - connect \src30__data_o \reg_0_src30__data_o - connect \dest10__wen \reg_0_dest10__wen - connect \dest10__data_i \reg_0_dest10__data_i - connect \dest20__wen \reg_0_dest20__wen - connect \dest20__data_i \reg_0_dest20__data_i - connect \r0__data_o \reg_0_r0__data_o - connect \r0__ren \reg_0_r0__ren - connect \r20__data_o \reg_0_r20__data_o - connect \r20__ren \reg_0_r20__ren - connect \w0__data_i \reg_0_w0__data_i - connect \w0__wen \reg_0_w0__wen - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 \reg_1_src11__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 \reg_1_src11__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 \reg_1_src21__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 \reg_1_src21__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 \reg_1_src31__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 \reg_1_src31__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 \reg_1_dest11__wen - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 \reg_1_dest11__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 \reg_1_dest21__wen - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 \reg_1_dest21__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 \reg_1_r1__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 \reg_1_r1__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 \reg_1_r21__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 \reg_1_r21__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 \reg_1_w1__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 \reg_1_w1__wen - cell \reg_1 \reg_1 - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \src11__ren \reg_1_src11__ren - connect \src11__data_o \reg_1_src11__data_o - connect \src21__ren \reg_1_src21__ren - connect \src21__data_o \reg_1_src21__data_o - connect \src31__ren \reg_1_src31__ren - connect \src31__data_o \reg_1_src31__data_o - connect \dest11__wen \reg_1_dest11__wen - connect \dest11__data_i \reg_1_dest11__data_i - connect \dest21__wen \reg_1_dest21__wen - connect \dest21__data_i \reg_1_dest21__data_i - connect \r1__data_o \reg_1_r1__data_o - connect \r1__ren \reg_1_r1__ren - connect \r21__data_o \reg_1_r21__data_o - connect \r21__ren \reg_1_r21__ren - connect \w1__data_i \reg_1_w1__data_i - connect \w1__wen \reg_1_w1__wen - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 \reg_2_src12__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 \reg_2_src12__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 \reg_2_src22__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 \reg_2_src22__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 \reg_2_src32__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 \reg_2_src32__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 \reg_2_dest12__wen - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 \reg_2_dest12__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 \reg_2_dest22__wen - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 \reg_2_dest22__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 \reg_2_r2__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 \reg_2_r2__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 \reg_2_r22__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 \reg_2_r22__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 \reg_2_w2__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 \reg_2_w2__wen - cell \reg_2 \reg_2 - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \src12__ren \reg_2_src12__ren - connect \src12__data_o \reg_2_src12__data_o - connect \src22__ren \reg_2_src22__ren - connect \src22__data_o \reg_2_src22__data_o - connect \src32__ren \reg_2_src32__ren - connect \src32__data_o \reg_2_src32__data_o - connect \dest12__wen \reg_2_dest12__wen - connect \dest12__data_i \reg_2_dest12__data_i - connect \dest22__wen \reg_2_dest22__wen - connect \dest22__data_i \reg_2_dest22__data_i - connect \r2__data_o \reg_2_r2__data_o - connect \r2__ren \reg_2_r2__ren - connect \r22__data_o \reg_2_r22__data_o - connect \r22__ren \reg_2_r22__ren - connect \w2__data_i \reg_2_w2__data_i - connect \w2__wen \reg_2_w2__wen - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 \reg_3_src13__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 \reg_3_src13__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 \reg_3_src23__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 \reg_3_src23__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 \reg_3_src33__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 \reg_3_src33__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 \reg_3_dest13__wen - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 \reg_3_dest13__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 \reg_3_dest23__wen - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 \reg_3_dest23__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 \reg_3_r3__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 \reg_3_r3__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 \reg_3_r23__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 \reg_3_r23__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 \reg_3_w3__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 \reg_3_w3__wen - cell \reg_3 \reg_3 - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \src13__ren \reg_3_src13__ren - connect \src13__data_o \reg_3_src13__data_o - connect \src23__ren \reg_3_src23__ren - connect \src23__data_o \reg_3_src23__data_o - connect \src33__ren \reg_3_src33__ren - connect \src33__data_o \reg_3_src33__data_o - connect \dest13__wen \reg_3_dest13__wen - connect \dest13__data_i \reg_3_dest13__data_i - connect \dest23__wen \reg_3_dest23__wen - connect \dest23__data_i \reg_3_dest23__data_i - connect \r3__data_o \reg_3_r3__data_o - connect \r3__ren \reg_3_r3__ren - connect \r23__data_o \reg_3_r23__data_o - connect \r23__ren \reg_3_r23__ren - connect \w3__data_i \reg_3_w3__data_i - connect \w3__wen \reg_3_w3__wen - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 \reg_4_src14__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 \reg_4_src14__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 \reg_4_src24__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 \reg_4_src24__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 \reg_4_src34__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 \reg_4_src34__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 \reg_4_dest14__wen - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 \reg_4_dest14__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 \reg_4_dest24__wen - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 \reg_4_dest24__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 \reg_4_r4__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 \reg_4_r4__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 \reg_4_r24__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 \reg_4_r24__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 \reg_4_w4__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 \reg_4_w4__wen - cell \reg_4 \reg_4 - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \src14__ren \reg_4_src14__ren - connect \src14__data_o \reg_4_src14__data_o - connect \src24__ren \reg_4_src24__ren - connect \src24__data_o \reg_4_src24__data_o - connect \src34__ren \reg_4_src34__ren - connect \src34__data_o \reg_4_src34__data_o - connect \dest14__wen \reg_4_dest14__wen - connect \dest14__data_i \reg_4_dest14__data_i - connect \dest24__wen \reg_4_dest24__wen - connect \dest24__data_i \reg_4_dest24__data_i - connect \r4__data_o \reg_4_r4__data_o - connect \r4__ren \reg_4_r4__ren - connect \r24__data_o \reg_4_r24__data_o - connect \r24__ren \reg_4_r24__ren - connect \w4__data_i \reg_4_w4__data_i - connect \w4__wen \reg_4_w4__wen - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 \reg_5_src15__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 \reg_5_src15__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 \reg_5_src25__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 \reg_5_src25__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 \reg_5_src35__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 \reg_5_src35__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 \reg_5_dest15__wen - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 \reg_5_dest15__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 \reg_5_dest25__wen - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 \reg_5_dest25__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 \reg_5_r5__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 \reg_5_r5__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 \reg_5_r25__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 \reg_5_r25__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 \reg_5_w5__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 \reg_5_w5__wen - cell \reg_5 \reg_5 - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \src15__ren \reg_5_src15__ren - connect \src15__data_o \reg_5_src15__data_o - connect \src25__ren \reg_5_src25__ren - connect \src25__data_o \reg_5_src25__data_o - connect \src35__ren \reg_5_src35__ren - connect \src35__data_o \reg_5_src35__data_o - connect \dest15__wen \reg_5_dest15__wen - connect \dest15__data_i \reg_5_dest15__data_i - connect \dest25__wen \reg_5_dest25__wen - connect \dest25__data_i \reg_5_dest25__data_i - connect \r5__data_o \reg_5_r5__data_o - connect \r5__ren \reg_5_r5__ren - connect \r25__data_o \reg_5_r25__data_o - connect \r25__ren \reg_5_r25__ren - connect \w5__data_i \reg_5_w5__data_i - connect \w5__wen \reg_5_w5__wen - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 \reg_6_src16__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 \reg_6_src16__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 \reg_6_src26__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 \reg_6_src26__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 \reg_6_src36__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 \reg_6_src36__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 \reg_6_dest16__wen - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 \reg_6_dest16__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 \reg_6_dest26__wen - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 \reg_6_dest26__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 \reg_6_r6__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 \reg_6_r6__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 \reg_6_r26__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 \reg_6_r26__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 \reg_6_w6__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 \reg_6_w6__wen - cell \reg_6 \reg_6 - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \src16__ren \reg_6_src16__ren - connect \src16__data_o \reg_6_src16__data_o - connect \src26__ren \reg_6_src26__ren - connect \src26__data_o \reg_6_src26__data_o - connect \src36__ren \reg_6_src36__ren - connect \src36__data_o \reg_6_src36__data_o - connect \dest16__wen \reg_6_dest16__wen - connect \dest16__data_i \reg_6_dest16__data_i - connect \dest26__wen \reg_6_dest26__wen - connect \dest26__data_i \reg_6_dest26__data_i - connect \r6__data_o \reg_6_r6__data_o - connect \r6__ren \reg_6_r6__ren - connect \r26__data_o \reg_6_r26__data_o - connect \r26__ren \reg_6_r26__ren - connect \w6__data_i \reg_6_w6__data_i - connect \w6__wen \reg_6_w6__wen - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 \reg_7_src17__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 \reg_7_src17__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 \reg_7_src27__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 \reg_7_src27__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 \reg_7_src37__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 \reg_7_src37__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 \reg_7_dest17__wen - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 \reg_7_dest17__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 \reg_7_dest27__wen - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 \reg_7_dest27__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 \reg_7_r7__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 \reg_7_r7__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 \reg_7_r27__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 \reg_7_r27__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 \reg_7_w7__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 \reg_7_w7__wen - cell \reg_7 \reg_7 - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \src17__ren \reg_7_src17__ren - connect \src17__data_o \reg_7_src17__data_o - connect \src27__ren \reg_7_src27__ren - connect \src27__data_o \reg_7_src27__data_o - connect \src37__ren \reg_7_src37__ren - connect \src37__data_o \reg_7_src37__data_o - connect \dest17__wen \reg_7_dest17__wen - connect \dest17__data_i \reg_7_dest17__data_i - connect \dest27__wen \reg_7_dest27__wen - connect \dest27__data_i \reg_7_dest27__data_i - connect \r7__data_o \reg_7_r7__data_o - connect \r7__ren \reg_7_r7__ren - connect \r27__data_o \reg_7_r27__data_o - connect \r27__ren \reg_7_r27__ren - connect \w7__data_i \reg_7_w7__data_i - connect \w7__wen \reg_7_w7__wen - end - process $group_0 - assign \reg_0_src10__ren 1'0 - assign \reg_1_src11__ren 1'0 - assign \reg_2_src12__ren 1'0 - assign \reg_3_src13__ren 1'0 - assign \reg_4_src14__ren 1'0 - assign \reg_5_src15__ren 1'0 - assign \reg_6_src16__ren 1'0 - assign \reg_7_src17__ren 1'0 - assign { \reg_7_src17__ren \reg_6_src16__ren \reg_5_src15__ren \reg_4_src14__ren \reg_3_src13__ren \reg_2_src12__ren \reg_1_src11__ren \reg_0_src10__ren } \src1__ren - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:170" - wire width 8 \ren_delay - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:170" - wire width 8 \ren_delay$next - process $group_8 - assign \ren_delay$next \ren_delay - assign \ren_delay$next \src1__ren - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \ren_delay$next 8'00000000 - end - sync init - update \ren_delay 8'00000000 - sync posedge \coresync_clk - update \ren_delay \ren_delay$next - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" - cell $reduce_bool $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \ren_delay - connect \Y $1 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - wire width 4 $3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $or $4 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A \reg_0_src10__data_o - connect \B \reg_1_src11__data_o - connect \Y $3 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - wire width 4 $5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $or $6 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A \reg_2_src12__data_o - connect \B \reg_3_src13__data_o - connect \Y $5 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - wire width 4 $7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - cell $or $8 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A $3 - connect \B $5 - connect \Y $7 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - wire width 4 $9 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $or $10 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A \reg_4_src14__data_o - connect \B \reg_5_src15__data_o - connect \Y $9 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - wire width 4 $11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $or $12 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A \reg_6_src16__data_o - connect \B \reg_7_src17__data_o - connect \Y $11 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - wire width 4 $13 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - cell $or $14 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A $9 - connect \B $11 - connect \Y $13 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - wire width 4 $15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - cell $or $16 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A $7 - connect \B $13 - connect \Y $15 - end - process $group_9 - assign \src1__data_o 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:172" - switch { $1 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:172" - case 1'1 - assign \src1__data_o $15 - end - sync init - end - process $group_10 - assign \reg_0_src20__ren 1'0 - assign \reg_1_src21__ren 1'0 - assign \reg_2_src22__ren 1'0 - assign \reg_3_src23__ren 1'0 - assign \reg_4_src24__ren 1'0 - assign \reg_5_src25__ren 1'0 - assign \reg_6_src26__ren 1'0 - assign \reg_7_src27__ren 1'0 - assign { \reg_7_src27__ren \reg_6_src26__ren \reg_5_src25__ren \reg_4_src24__ren \reg_3_src23__ren \reg_2_src22__ren \reg_1_src21__ren \reg_0_src20__ren } \src2__ren - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:170" - wire width 8 \ren_delay$17 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:170" - wire width 8 \ren_delay$17$next - process $group_18 - assign \ren_delay$17$next \ren_delay$17 - assign \ren_delay$17$next \src2__ren - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \ren_delay$17$next 8'00000000 - end - sync init - update \ren_delay$17 8'00000000 - sync posedge \coresync_clk - update \ren_delay$17 \ren_delay$17$next - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" - wire width 1 $18 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" - cell $reduce_bool $19 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \ren_delay$17 - connect \Y $18 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - wire width 4 $20 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $or $21 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A \reg_0_src20__data_o - connect \B \reg_1_src21__data_o - connect \Y $20 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - wire width 4 $22 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $or $23 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A \reg_2_src22__data_o - connect \B \reg_3_src23__data_o - connect \Y $22 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - wire width 4 $24 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - cell $or $25 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A $20 - connect \B $22 - connect \Y $24 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - wire width 4 $26 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $or $27 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A \reg_4_src24__data_o - connect \B \reg_5_src25__data_o - connect \Y $26 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - wire width 4 $28 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $or $29 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A \reg_6_src26__data_o - connect \B \reg_7_src27__data_o - connect \Y $28 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - wire width 4 $30 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - cell $or $31 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A $26 - connect \B $28 - connect \Y $30 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - wire width 4 $32 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - cell $or $33 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A $24 - connect \B $30 - connect \Y $32 - end - process $group_19 - assign \src2__data_o 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:172" - switch { $18 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:172" - case 1'1 - assign \src2__data_o $32 - end - sync init - end - process $group_20 - assign \reg_0_src30__ren 1'0 - assign \reg_1_src31__ren 1'0 - assign \reg_2_src32__ren 1'0 - assign \reg_3_src33__ren 1'0 - assign \reg_4_src34__ren 1'0 - assign \reg_5_src35__ren 1'0 - assign \reg_6_src36__ren 1'0 - assign \reg_7_src37__ren 1'0 - assign { \reg_7_src37__ren \reg_6_src36__ren \reg_5_src35__ren \reg_4_src34__ren \reg_3_src33__ren \reg_2_src32__ren \reg_1_src31__ren \reg_0_src30__ren } \src3__ren - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:170" - wire width 8 \ren_delay$34 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:170" - wire width 8 \ren_delay$34$next - process $group_28 - assign \ren_delay$34$next \ren_delay$34 - assign \ren_delay$34$next \src3__ren - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \ren_delay$34$next 8'00000000 - end - sync init - update \ren_delay$34 8'00000000 - sync posedge \coresync_clk - update \ren_delay$34 \ren_delay$34$next - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" - wire width 1 $35 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" - cell $reduce_bool $36 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \ren_delay$34 - connect \Y $35 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - wire width 4 $37 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $or $38 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A \reg_0_src30__data_o - connect \B \reg_1_src31__data_o - connect \Y $37 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - wire width 4 $39 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $or $40 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A \reg_2_src32__data_o - connect \B \reg_3_src33__data_o - connect \Y $39 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - wire width 4 $41 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - cell $or $42 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A $37 - connect \B $39 - connect \Y $41 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - wire width 4 $43 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $or $44 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A \reg_4_src34__data_o - connect \B \reg_5_src35__data_o - connect \Y $43 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - wire width 4 $45 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $or $46 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A \reg_6_src36__data_o - connect \B \reg_7_src37__data_o - connect \Y $45 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - wire width 4 $47 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - cell $or $48 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A $43 - connect \B $45 - connect \Y $47 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - wire width 4 $49 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - cell $or $50 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A $41 - connect \B $47 - connect \Y $49 - end - process $group_29 - assign \src3__data_o 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:172" - switch { $35 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:172" - case 1'1 - assign \src3__data_o $49 - end - sync init - end - process $group_30 - assign \reg_0_dest10__wen 1'0 - assign \reg_1_dest11__wen 1'0 - assign \reg_2_dest12__wen 1'0 - assign \reg_3_dest13__wen 1'0 - assign \reg_4_dest14__wen 1'0 - assign \reg_5_dest15__wen 1'0 - assign \reg_6_dest16__wen 1'0 - assign \reg_7_dest17__wen 1'0 - assign { \reg_7_dest17__wen \reg_6_dest16__wen \reg_5_dest15__wen \reg_4_dest14__wen \reg_3_dest13__wen \reg_2_dest12__wen \reg_1_dest11__wen \reg_0_dest10__wen } \wen - sync init - end - process $group_38 - assign \reg_0_dest10__data_i 4'0000 - assign \reg_0_dest10__data_i \data_i - sync init - end - process $group_39 - assign \reg_1_dest11__data_i 4'0000 - assign \reg_1_dest11__data_i \data_i - sync init - end - process $group_40 - assign \reg_2_dest12__data_i 4'0000 - assign \reg_2_dest12__data_i \data_i - sync init - end - process $group_41 - assign \reg_3_dest13__data_i 4'0000 - assign \reg_3_dest13__data_i \data_i - sync init - end - process $group_42 - assign \reg_4_dest14__data_i 4'0000 - assign \reg_4_dest14__data_i \data_i - sync init - end - process $group_43 - assign \reg_5_dest15__data_i 4'0000 - assign \reg_5_dest15__data_i \data_i - sync init - end - process $group_44 - assign \reg_6_dest16__data_i 4'0000 - assign \reg_6_dest16__data_i \data_i - sync init - end - process $group_45 - assign \reg_7_dest17__data_i 4'0000 - assign \reg_7_dest17__data_i \data_i - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 8 \wen$51 - process $group_46 - assign \reg_0_dest20__wen 1'0 - assign \reg_1_dest21__wen 1'0 - assign \reg_2_dest22__wen 1'0 - assign \reg_3_dest23__wen 1'0 - assign \reg_4_dest24__wen 1'0 - assign \reg_5_dest25__wen 1'0 - assign \reg_6_dest26__wen 1'0 - assign \reg_7_dest27__wen 1'0 - assign { \reg_7_dest27__wen \reg_6_dest26__wen \reg_5_dest25__wen \reg_4_dest24__wen \reg_3_dest23__wen \reg_2_dest22__wen \reg_1_dest21__wen \reg_0_dest20__wen } \wen$51 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 \data_i$52 - process $group_54 - assign \reg_0_dest20__data_i 4'0000 - assign \reg_0_dest20__data_i \data_i$52 - sync init - end - process $group_55 - assign \reg_1_dest21__data_i 4'0000 - assign \reg_1_dest21__data_i \data_i$52 - sync init - end - process $group_56 - assign \reg_2_dest22__data_i 4'0000 - assign \reg_2_dest22__data_i \data_i$52 - sync init - end - process $group_57 - assign \reg_3_dest23__data_i 4'0000 - assign \reg_3_dest23__data_i \data_i$52 - sync init - end - process $group_58 - assign \reg_4_dest24__data_i 4'0000 - assign \reg_4_dest24__data_i \data_i$52 - sync init - end - process $group_59 - assign \reg_5_dest25__data_i 4'0000 - assign \reg_5_dest25__data_i \data_i$52 - sync init - end - process $group_60 - assign \reg_6_dest26__data_i 4'0000 - assign \reg_6_dest26__data_i \data_i$52 - sync init - end - process $group_61 - assign \reg_7_dest27__data_i 4'0000 - assign \reg_7_dest27__data_i \data_i$52 - sync init - end - process $group_62 - assign \full_rd__data_o 32'00000000000000000000000000000000 - assign \full_rd__data_o { \reg_7_r7__data_o \reg_6_r6__data_o \reg_5_r5__data_o \reg_4_r4__data_o \reg_3_r3__data_o \reg_2_r2__data_o \reg_1_r1__data_o \reg_0_r0__data_o } - sync init - end - process $group_63 - assign \reg_0_r0__ren 1'0 - assign \reg_1_r1__ren 1'0 - assign \reg_2_r2__ren 1'0 - assign \reg_3_r3__ren 1'0 - assign \reg_4_r4__ren 1'0 - assign \reg_5_r5__ren 1'0 - assign \reg_6_r6__ren 1'0 - assign \reg_7_r7__ren 1'0 - assign { \reg_7_r7__ren \reg_6_r6__ren \reg_5_r5__ren \reg_4_r4__ren \reg_3_r3__ren \reg_2_r2__ren \reg_1_r1__ren \reg_0_r0__ren } \full_rd__ren - sync init - end - process $group_71 - assign \full_rd2__data_o 32'00000000000000000000000000000000 - assign \full_rd2__data_o { \reg_7_r27__data_o \reg_6_r26__data_o \reg_5_r25__data_o \reg_4_r24__data_o \reg_3_r23__data_o \reg_2_r22__data_o \reg_1_r21__data_o \reg_0_r20__data_o } - sync init - end - process $group_72 - assign \reg_0_r20__ren 1'0 - assign \reg_1_r21__ren 1'0 - assign \reg_2_r22__ren 1'0 - assign \reg_3_r23__ren 1'0 - assign \reg_4_r24__ren 1'0 - assign \reg_5_r25__ren 1'0 - assign \reg_6_r26__ren 1'0 - assign \reg_7_r27__ren 1'0 - assign { \reg_7_r27__ren \reg_6_r26__ren \reg_5_r25__ren \reg_4_r24__ren \reg_3_r23__ren \reg_2_r22__ren \reg_1_r21__ren \reg_0_r20__ren } \full_rd2__ren - sync init - end - process $group_80 - assign \reg_0_w0__data_i 4'0000 - assign \reg_1_w1__data_i 4'0000 - assign \reg_2_w2__data_i 4'0000 - assign \reg_3_w3__data_i 4'0000 - assign \reg_4_w4__data_i 4'0000 - assign \reg_5_w5__data_i 4'0000 - assign \reg_6_w6__data_i 4'0000 - assign \reg_7_w7__data_i 4'0000 - assign { \reg_7_w7__data_i \reg_6_w6__data_i \reg_5_w5__data_i \reg_4_w4__data_i \reg_3_w3__data_i \reg_2_w2__data_i \reg_1_w1__data_i \reg_0_w0__data_i } \full_wr__data_i - sync init - end - process $group_88 - assign \reg_0_w0__wen 1'0 - assign \reg_1_w1__wen 1'0 - assign \reg_2_w2__wen 1'0 - assign \reg_3_w3__wen 1'0 - assign \reg_4_w4__wen 1'0 - assign \reg_5_w5__wen 1'0 - assign \reg_6_w6__wen 1'0 - assign \reg_7_w7__wen 1'0 - assign { \reg_7_w7__wen \reg_6_w6__wen \reg_5_w5__wen \reg_4_w4__wen \reg_3_w3__wen \reg_2_w2__wen \reg_1_w1__wen \reg_0_w0__wen } \full_wr__wen - sync init - end - connect \wen$51 8'00000000 - connect \data_i$52 4'0000 -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.xer.reg_0" -module \reg_0$129 - attribute \src "simple/issuer.py:141" - wire width 1 input 0 \coresync_clk - attribute \src "simple/issuer.py:141" - wire width 1 input 1 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 input 2 \src10__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 2 output 3 \src10__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 2 \src10__data_o$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 input 4 \src20__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 2 output 5 \src20__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 2 \src20__data_o$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 input 6 \src30__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 2 output 7 \src30__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 2 \src30__data_o$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 input 8 \dest10__wen - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 2 input 9 \dest10__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 input 10 \dest20__wen - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 2 input 11 \dest20__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 input 12 \dest30__wen - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 2 input 13 \dest30__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 2 output 14 \r0__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 2 \r0__data_o$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 input 15 \r0__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 2 input 16 \w0__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 input 17 \w0__wen - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" - wire width 1 \wr_detect - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_detect - connect \Y $1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" - wire width 2 \reg - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" - wire width 2 \reg$next - process $group_0 - assign \src10__data_o$next \src10__data_o - assign \src10__data_o$next 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch { \src10__ren } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch { \dest10__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - case 1'1 - assign \src10__data_o$next \dest10__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch { \dest20__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - case 1'1 - assign \src10__data_o$next \dest20__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch { \dest30__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - case 1'1 - assign \src10__data_o$next \dest30__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch { \w0__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - case 1'1 - assign \src10__data_o$next \w0__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - switch { $1 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - case 1'1 - assign \src10__data_o$next \reg - end - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \src10__data_o$next 2'00 - end - sync init - update \src10__data_o 2'00 - sync posedge \coresync_clk - update \src10__data_o \src10__data_o$next - end - process $group_1 - assign \wr_detect 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch { \src10__ren } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - case 1'1 - assign \wr_detect 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch { \dest10__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - case 1'1 - assign \wr_detect 1'1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch { \dest20__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - case 1'1 - assign \wr_detect 1'1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch { \dest30__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - case 1'1 - assign \wr_detect 1'1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch { \w0__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - case 1'1 - assign \wr_detect 1'1 - end - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - wire width 1 $3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" - wire width 1 \wr_detect$4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $5 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_detect$4 - connect \Y $3 - end - process $group_2 - assign \src20__data_o$next \src20__data_o - assign \src20__data_o$next 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch { \src20__ren } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch { \dest10__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - case 1'1 - assign \src20__data_o$next \dest10__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch { \dest20__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - case 1'1 - assign \src20__data_o$next \dest20__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch { \dest30__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - case 1'1 - assign \src20__data_o$next \dest30__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch { \w0__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - case 1'1 - assign \src20__data_o$next \w0__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - switch { $3 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - case 1'1 - assign \src20__data_o$next \reg - end - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \src20__data_o$next 2'00 - end - sync init - update \src20__data_o 2'00 - sync posedge \coresync_clk - update \src20__data_o \src20__data_o$next - end - process $group_3 - assign \wr_detect$4 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch { \src20__ren } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - case 1'1 - assign \wr_detect$4 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch { \dest10__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - case 1'1 - assign \wr_detect$4 1'1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch { \dest20__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - case 1'1 - assign \wr_detect$4 1'1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch { \dest30__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - case 1'1 - assign \wr_detect$4 1'1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch { \w0__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - case 1'1 - assign \wr_detect$4 1'1 - end - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - wire width 1 $6 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" - wire width 1 \wr_detect$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $8 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_detect$7 - connect \Y $6 - end - process $group_4 - assign \src30__data_o$next \src30__data_o - assign \src30__data_o$next 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch { \src30__ren } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch { \dest10__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - case 1'1 - assign \src30__data_o$next \dest10__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch { \dest20__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - case 1'1 - assign \src30__data_o$next \dest20__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch { \dest30__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - case 1'1 - assign \src30__data_o$next \dest30__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch { \w0__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - case 1'1 - assign \src30__data_o$next \w0__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - switch { $6 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - case 1'1 - assign \src30__data_o$next \reg - end - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \src30__data_o$next 2'00 - end - sync init - update \src30__data_o 2'00 - sync posedge \coresync_clk - update \src30__data_o \src30__data_o$next - end - process $group_5 - assign \wr_detect$7 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch { \src30__ren } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - case 1'1 - assign \wr_detect$7 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch { \dest10__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - case 1'1 - assign \wr_detect$7 1'1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch { \dest20__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - case 1'1 - assign \wr_detect$7 1'1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch { \dest30__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - case 1'1 - assign \wr_detect$7 1'1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch { \w0__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - case 1'1 - assign \wr_detect$7 1'1 - end - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - wire width 1 $9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" - wire width 1 \wr_detect$10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $11 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_detect$10 - connect \Y $9 - end - process $group_6 - assign \r0__data_o$next \r0__data_o - assign \r0__data_o$next 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch { \r0__ren } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch { \dest10__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - case 1'1 - assign \r0__data_o$next \dest10__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch { \dest20__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - case 1'1 - assign \r0__data_o$next \dest20__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch { \dest30__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - case 1'1 - assign \r0__data_o$next \dest30__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch { \w0__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - case 1'1 - assign \r0__data_o$next \w0__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - switch { $9 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - case 1'1 - assign \r0__data_o$next \reg - end - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \r0__data_o$next 2'00 - end - sync init - update \r0__data_o 2'00 - sync posedge \coresync_clk - update \r0__data_o \r0__data_o$next - end - process $group_7 - assign \wr_detect$10 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch { \r0__ren } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - case 1'1 - assign \wr_detect$10 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch { \dest10__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - case 1'1 - assign \wr_detect$10 1'1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch { \dest20__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - case 1'1 - assign \wr_detect$10 1'1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch { \dest30__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - case 1'1 - assign \wr_detect$10 1'1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch { \w0__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - case 1'1 - assign \wr_detect$10 1'1 - end - end - sync init - end - process $group_8 - assign \reg$next \reg - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" - switch { \dest10__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" - case 1'1 - assign \reg$next \dest10__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" - switch { \dest20__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" - case 1'1 - assign \reg$next \dest20__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" - switch { \dest30__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" - case 1'1 - assign \reg$next \dest30__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" - switch { \w0__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" - case 1'1 - assign \reg$next \w0__data_i - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \reg$next 2'00 - end - sync init - update \reg 2'00 - sync posedge \coresync_clk - update \reg \reg$next - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.xer.reg_1" -module \reg_1$130 - attribute \src "simple/issuer.py:141" - wire width 1 input 0 \coresync_clk - attribute \src "simple/issuer.py:141" - wire width 1 input 1 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 input 2 \src11__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 2 output 3 \src11__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 2 \src11__data_o$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 input 4 \src21__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 2 output 5 \src21__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 2 \src21__data_o$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 input 6 \src31__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 2 output 7 \src31__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 2 \src31__data_o$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 input 8 \dest11__wen - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 2 input 9 \dest11__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 input 10 \dest21__wen - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 2 input 11 \dest21__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 input 12 \dest31__wen - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 2 input 13 \dest31__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 2 output 14 \r1__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 2 \r1__data_o$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 input 15 \r1__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 2 input 16 \w1__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 input 17 \w1__wen - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" - wire width 1 \wr_detect - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_detect - connect \Y $1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" - wire width 2 \reg - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" - wire width 2 \reg$next - process $group_0 - assign \src11__data_o$next \src11__data_o - assign \src11__data_o$next 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch { \src11__ren } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch { \dest11__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - case 1'1 - assign \src11__data_o$next \dest11__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch { \dest21__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - case 1'1 - assign \src11__data_o$next \dest21__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch { \dest31__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - case 1'1 - assign \src11__data_o$next \dest31__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch { \w1__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - case 1'1 - assign \src11__data_o$next \w1__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - switch { $1 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - case 1'1 - assign \src11__data_o$next \reg - end - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \src11__data_o$next 2'00 - end - sync init - update \src11__data_o 2'00 - sync posedge \coresync_clk - update \src11__data_o \src11__data_o$next - end - process $group_1 - assign \wr_detect 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch { \src11__ren } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - case 1'1 - assign \wr_detect 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch { \dest11__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - case 1'1 - assign \wr_detect 1'1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch { \dest21__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - case 1'1 - assign \wr_detect 1'1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch { \dest31__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - case 1'1 - assign \wr_detect 1'1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch { \w1__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - case 1'1 - assign \wr_detect 1'1 - end - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - wire width 1 $3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" - wire width 1 \wr_detect$4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $5 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_detect$4 - connect \Y $3 - end - process $group_2 - assign \src21__data_o$next \src21__data_o - assign \src21__data_o$next 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch { \src21__ren } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch { \dest11__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - case 1'1 - assign \src21__data_o$next \dest11__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch { \dest21__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - case 1'1 - assign \src21__data_o$next \dest21__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch { \dest31__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - case 1'1 - assign \src21__data_o$next \dest31__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch { \w1__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - case 1'1 - assign \src21__data_o$next \w1__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - switch { $3 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - case 1'1 - assign \src21__data_o$next \reg - end - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \src21__data_o$next 2'00 - end - sync init - update \src21__data_o 2'00 - sync posedge \coresync_clk - update \src21__data_o \src21__data_o$next - end - process $group_3 - assign \wr_detect$4 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch { \src21__ren } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - case 1'1 - assign \wr_detect$4 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch { \dest11__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - case 1'1 - assign \wr_detect$4 1'1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch { \dest21__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - case 1'1 - assign \wr_detect$4 1'1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch { \dest31__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - case 1'1 - assign \wr_detect$4 1'1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch { \w1__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - case 1'1 - assign \wr_detect$4 1'1 - end - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - wire width 1 $6 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" - wire width 1 \wr_detect$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $8 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_detect$7 - connect \Y $6 - end - process $group_4 - assign \src31__data_o$next \src31__data_o - assign \src31__data_o$next 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch { \src31__ren } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch { \dest11__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - case 1'1 - assign \src31__data_o$next \dest11__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch { \dest21__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - case 1'1 - assign \src31__data_o$next \dest21__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch { \dest31__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - case 1'1 - assign \src31__data_o$next \dest31__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch { \w1__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - case 1'1 - assign \src31__data_o$next \w1__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - switch { $6 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - case 1'1 - assign \src31__data_o$next \reg - end - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \src31__data_o$next 2'00 - end - sync init - update \src31__data_o 2'00 - sync posedge \coresync_clk - update \src31__data_o \src31__data_o$next - end - process $group_5 - assign \wr_detect$7 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch { \src31__ren } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - case 1'1 - assign \wr_detect$7 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch { \dest11__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - case 1'1 - assign \wr_detect$7 1'1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch { \dest21__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - case 1'1 - assign \wr_detect$7 1'1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch { \dest31__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - case 1'1 - assign \wr_detect$7 1'1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch { \w1__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - case 1'1 - assign \wr_detect$7 1'1 - end - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - wire width 1 $9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" - wire width 1 \wr_detect$10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $11 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_detect$10 - connect \Y $9 - end - process $group_6 - assign \r1__data_o$next \r1__data_o - assign \r1__data_o$next 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch { \r1__ren } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch { \dest11__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - case 1'1 - assign \r1__data_o$next \dest11__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch { \dest21__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - case 1'1 - assign \r1__data_o$next \dest21__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch { \dest31__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - case 1'1 - assign \r1__data_o$next \dest31__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch { \w1__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - case 1'1 - assign \r1__data_o$next \w1__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - switch { $9 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - case 1'1 - assign \r1__data_o$next \reg - end - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \r1__data_o$next 2'00 - end - sync init - update \r1__data_o 2'00 - sync posedge \coresync_clk - update \r1__data_o \r1__data_o$next - end - process $group_7 - assign \wr_detect$10 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch { \r1__ren } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - case 1'1 - assign \wr_detect$10 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch { \dest11__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - case 1'1 - assign \wr_detect$10 1'1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch { \dest21__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - case 1'1 - assign \wr_detect$10 1'1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch { \dest31__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - case 1'1 - assign \wr_detect$10 1'1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch { \w1__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - case 1'1 - assign \wr_detect$10 1'1 - end - end - sync init - end - process $group_8 - assign \reg$next \reg - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" - switch { \dest11__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" - case 1'1 - assign \reg$next \dest11__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" - switch { \dest21__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" - case 1'1 - assign \reg$next \dest21__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" - switch { \dest31__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" - case 1'1 - assign \reg$next \dest31__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" - switch { \w1__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" - case 1'1 - assign \reg$next \w1__data_i - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \reg$next 2'00 - end - sync init - update \reg 2'00 - sync posedge \coresync_clk - update \reg \reg$next - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.xer.reg_2" -module \reg_2$131 - attribute \src "simple/issuer.py:141" - wire width 1 input 0 \coresync_clk - attribute \src "simple/issuer.py:141" - wire width 1 input 1 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 input 2 \src12__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 2 output 3 \src12__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 2 \src12__data_o$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 input 4 \src22__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 2 output 5 \src22__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 2 \src22__data_o$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 input 6 \src32__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 2 output 7 \src32__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 2 \src32__data_o$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 input 8 \dest12__wen - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 2 input 9 \dest12__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 input 10 \dest22__wen - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 2 input 11 \dest22__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 input 12 \dest32__wen - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 2 input 13 \dest32__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 2 output 14 \r2__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 2 \r2__data_o$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 input 15 \r2__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 2 input 16 \w2__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 input 17 \w2__wen - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" - wire width 1 \wr_detect - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_detect - connect \Y $1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" - wire width 2 \reg - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" - wire width 2 \reg$next - process $group_0 - assign \src12__data_o$next \src12__data_o - assign \src12__data_o$next 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch { \src12__ren } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch { \dest12__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - case 1'1 - assign \src12__data_o$next \dest12__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch { \dest22__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - case 1'1 - assign \src12__data_o$next \dest22__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch { \dest32__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - case 1'1 - assign \src12__data_o$next \dest32__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch { \w2__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - case 1'1 - assign \src12__data_o$next \w2__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - switch { $1 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - case 1'1 - assign \src12__data_o$next \reg - end - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \src12__data_o$next 2'00 - end - sync init - update \src12__data_o 2'00 - sync posedge \coresync_clk - update \src12__data_o \src12__data_o$next - end - process $group_1 - assign \wr_detect 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch { \src12__ren } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - case 1'1 - assign \wr_detect 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch { \dest12__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - case 1'1 - assign \wr_detect 1'1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch { \dest22__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - case 1'1 - assign \wr_detect 1'1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch { \dest32__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - case 1'1 - assign \wr_detect 1'1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch { \w2__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - case 1'1 - assign \wr_detect 1'1 - end - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - wire width 1 $3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" - wire width 1 \wr_detect$4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $5 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_detect$4 - connect \Y $3 - end - process $group_2 - assign \src22__data_o$next \src22__data_o - assign \src22__data_o$next 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch { \src22__ren } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch { \dest12__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - case 1'1 - assign \src22__data_o$next \dest12__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch { \dest22__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - case 1'1 - assign \src22__data_o$next \dest22__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch { \dest32__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - case 1'1 - assign \src22__data_o$next \dest32__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch { \w2__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - case 1'1 - assign \src22__data_o$next \w2__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - switch { $3 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - case 1'1 - assign \src22__data_o$next \reg - end - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \src22__data_o$next 2'00 - end - sync init - update \src22__data_o 2'00 - sync posedge \coresync_clk - update \src22__data_o \src22__data_o$next - end - process $group_3 - assign \wr_detect$4 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch { \src22__ren } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - case 1'1 - assign \wr_detect$4 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch { \dest12__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - case 1'1 - assign \wr_detect$4 1'1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch { \dest22__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - case 1'1 - assign \wr_detect$4 1'1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch { \dest32__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - case 1'1 - assign \wr_detect$4 1'1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch { \w2__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - case 1'1 - assign \wr_detect$4 1'1 - end - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - wire width 1 $6 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" - wire width 1 \wr_detect$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $8 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_detect$7 - connect \Y $6 - end - process $group_4 - assign \src32__data_o$next \src32__data_o - assign \src32__data_o$next 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch { \src32__ren } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch { \dest12__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - case 1'1 - assign \src32__data_o$next \dest12__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch { \dest22__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - case 1'1 - assign \src32__data_o$next \dest22__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch { \dest32__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - case 1'1 - assign \src32__data_o$next \dest32__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch { \w2__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - case 1'1 - assign \src32__data_o$next \w2__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - switch { $6 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - case 1'1 - assign \src32__data_o$next \reg - end - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \src32__data_o$next 2'00 - end - sync init - update \src32__data_o 2'00 - sync posedge \coresync_clk - update \src32__data_o \src32__data_o$next - end - process $group_5 - assign \wr_detect$7 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch { \src32__ren } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - case 1'1 - assign \wr_detect$7 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch { \dest12__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - case 1'1 - assign \wr_detect$7 1'1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch { \dest22__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - case 1'1 - assign \wr_detect$7 1'1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch { \dest32__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - case 1'1 - assign \wr_detect$7 1'1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch { \w2__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - case 1'1 - assign \wr_detect$7 1'1 - end - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - wire width 1 $9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" - wire width 1 \wr_detect$10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $11 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_detect$10 - connect \Y $9 - end - process $group_6 - assign \r2__data_o$next \r2__data_o - assign \r2__data_o$next 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch { \r2__ren } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch { \dest12__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - case 1'1 - assign \r2__data_o$next \dest12__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch { \dest22__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - case 1'1 - assign \r2__data_o$next \dest22__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch { \dest32__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - case 1'1 - assign \r2__data_o$next \dest32__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch { \w2__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - case 1'1 - assign \r2__data_o$next \w2__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - switch { $9 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - case 1'1 - assign \r2__data_o$next \reg - end - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \r2__data_o$next 2'00 - end - sync init - update \r2__data_o 2'00 - sync posedge \coresync_clk - update \r2__data_o \r2__data_o$next - end - process $group_7 - assign \wr_detect$10 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch { \r2__ren } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - case 1'1 - assign \wr_detect$10 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch { \dest12__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - case 1'1 - assign \wr_detect$10 1'1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch { \dest22__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - case 1'1 - assign \wr_detect$10 1'1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch { \dest32__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - case 1'1 - assign \wr_detect$10 1'1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch { \w2__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - case 1'1 - assign \wr_detect$10 1'1 - end - end - sync init - end - process $group_8 - assign \reg$next \reg - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" - switch { \dest12__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" - case 1'1 - assign \reg$next \dest12__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" - switch { \dest22__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" - case 1'1 - assign \reg$next \dest22__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" - switch { \dest32__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" - case 1'1 - assign \reg$next \dest32__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" - switch { \w2__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" - case 1'1 - assign \reg$next \w2__data_i - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \reg$next 2'00 - end - sync init - update \reg 2'00 - sync posedge \coresync_clk - update \reg \reg$next - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.xer" -module \xer - attribute \src "simple/issuer.py:141" - wire width 1 input 0 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 3 input 1 \full_rd__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 6 output 2 \full_rd__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 2 output 3 \src1__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 3 input 4 \src1__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 2 output 5 \src2__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 3 input 6 \src2__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 2 output 7 \src3__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 3 input 8 \src3__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 2 input 9 \data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 3 input 10 \wen - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 2 input 11 \data_i$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 3 input 12 \wen$2 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 2 input 13 \data_i$3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 3 input 14 \wen$4 - attribute \src "simple/issuer.py:141" - wire width 1 input 15 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 \reg_0_src10__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 2 \reg_0_src10__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 \reg_0_src20__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 2 \reg_0_src20__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 \reg_0_src30__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 2 \reg_0_src30__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 \reg_0_dest10__wen - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 2 \reg_0_dest10__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 \reg_0_dest20__wen - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 2 \reg_0_dest20__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 \reg_0_dest30__wen - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 2 \reg_0_dest30__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 2 \reg_0_r0__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 \reg_0_r0__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 2 \reg_0_w0__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 \reg_0_w0__wen - cell \reg_0$129 \reg_0 - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \src10__ren \reg_0_src10__ren - connect \src10__data_o \reg_0_src10__data_o - connect \src20__ren \reg_0_src20__ren - connect \src20__data_o \reg_0_src20__data_o - connect \src30__ren \reg_0_src30__ren - connect \src30__data_o \reg_0_src30__data_o - connect \dest10__wen \reg_0_dest10__wen - connect \dest10__data_i \reg_0_dest10__data_i - connect \dest20__wen \reg_0_dest20__wen - connect \dest20__data_i \reg_0_dest20__data_i - connect \dest30__wen \reg_0_dest30__wen - connect \dest30__data_i \reg_0_dest30__data_i - connect \r0__data_o \reg_0_r0__data_o - connect \r0__ren \reg_0_r0__ren - connect \w0__data_i \reg_0_w0__data_i - connect \w0__wen \reg_0_w0__wen - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 \reg_1_src11__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 2 \reg_1_src11__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 \reg_1_src21__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 2 \reg_1_src21__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 \reg_1_src31__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 2 \reg_1_src31__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 \reg_1_dest11__wen - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 2 \reg_1_dest11__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 \reg_1_dest21__wen - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 2 \reg_1_dest21__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 \reg_1_dest31__wen - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 2 \reg_1_dest31__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 2 \reg_1_r1__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 \reg_1_r1__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 2 \reg_1_w1__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 \reg_1_w1__wen - cell \reg_1$130 \reg_1 - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \src11__ren \reg_1_src11__ren - connect \src11__data_o \reg_1_src11__data_o - connect \src21__ren \reg_1_src21__ren - connect \src21__data_o \reg_1_src21__data_o - connect \src31__ren \reg_1_src31__ren - connect \src31__data_o \reg_1_src31__data_o - connect \dest11__wen \reg_1_dest11__wen - connect \dest11__data_i \reg_1_dest11__data_i - connect \dest21__wen \reg_1_dest21__wen - connect \dest21__data_i \reg_1_dest21__data_i - connect \dest31__wen \reg_1_dest31__wen - connect \dest31__data_i \reg_1_dest31__data_i - connect \r1__data_o \reg_1_r1__data_o - connect \r1__ren \reg_1_r1__ren - connect \w1__data_i \reg_1_w1__data_i - connect \w1__wen \reg_1_w1__wen - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 \reg_2_src12__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 2 \reg_2_src12__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 \reg_2_src22__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 2 \reg_2_src22__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 \reg_2_src32__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 2 \reg_2_src32__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 \reg_2_dest12__wen - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 2 \reg_2_dest12__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 \reg_2_dest22__wen - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 2 \reg_2_dest22__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 \reg_2_dest32__wen - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 2 \reg_2_dest32__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 2 \reg_2_r2__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 \reg_2_r2__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 2 \reg_2_w2__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 \reg_2_w2__wen - cell \reg_2$131 \reg_2 - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \src12__ren \reg_2_src12__ren - connect \src12__data_o \reg_2_src12__data_o - connect \src22__ren \reg_2_src22__ren - connect \src22__data_o \reg_2_src22__data_o - connect \src32__ren \reg_2_src32__ren - connect \src32__data_o \reg_2_src32__data_o - connect \dest12__wen \reg_2_dest12__wen - connect \dest12__data_i \reg_2_dest12__data_i - connect \dest22__wen \reg_2_dest22__wen - connect \dest22__data_i \reg_2_dest22__data_i - connect \dest32__wen \reg_2_dest32__wen - connect \dest32__data_i \reg_2_dest32__data_i - connect \r2__data_o \reg_2_r2__data_o - connect \r2__ren \reg_2_r2__ren - connect \w2__data_i \reg_2_w2__data_i - connect \w2__wen \reg_2_w2__wen - end - process $group_0 - assign \reg_0_src10__ren 1'0 - assign \reg_1_src11__ren 1'0 - assign \reg_2_src12__ren 1'0 - assign { \reg_2_src12__ren \reg_1_src11__ren \reg_0_src10__ren } \src1__ren - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:170" - wire width 3 \ren_delay - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:170" - wire width 3 \ren_delay$next - process $group_3 - assign \ren_delay$next \ren_delay - assign \ren_delay$next \src1__ren - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \ren_delay$next 3'000 - end - sync init - update \ren_delay 3'000 - sync posedge \coresync_clk - update \ren_delay \ren_delay$next - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" - wire width 1 $5 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" - cell $reduce_bool $6 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \ren_delay - connect \Y $5 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - wire width 2 $7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $or $8 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 2 - connect \A \reg_1_src11__data_o - connect \B \reg_2_src12__data_o - connect \Y $7 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - wire width 2 $9 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - cell $or $10 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 2 - connect \A \reg_0_src10__data_o - connect \B $7 - connect \Y $9 - end - process $group_4 - assign \src1__data_o 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:172" - switch { $5 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:172" - case 1'1 - assign \src1__data_o $9 - end - sync init - end - process $group_5 - assign \reg_0_src20__ren 1'0 - assign \reg_1_src21__ren 1'0 - assign \reg_2_src22__ren 1'0 - assign { \reg_2_src22__ren \reg_1_src21__ren \reg_0_src20__ren } \src2__ren - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:170" - wire width 3 \ren_delay$11 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:170" - wire width 3 \ren_delay$11$next - process $group_8 - assign \ren_delay$11$next \ren_delay$11 - assign \ren_delay$11$next \src2__ren - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \ren_delay$11$next 3'000 - end - sync init - update \ren_delay$11 3'000 - sync posedge \coresync_clk - update \ren_delay$11 \ren_delay$11$next - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" - wire width 1 $12 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" - cell $reduce_bool $13 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \ren_delay$11 - connect \Y $12 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - wire width 2 $14 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $or $15 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 2 - connect \A \reg_1_src21__data_o - connect \B \reg_2_src22__data_o - connect \Y $14 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - wire width 2 $16 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - cell $or $17 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 2 - connect \A \reg_0_src20__data_o - connect \B $14 - connect \Y $16 - end - process $group_9 - assign \src2__data_o 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:172" - switch { $12 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:172" - case 1'1 - assign \src2__data_o $16 - end - sync init - end - process $group_10 - assign \reg_0_src30__ren 1'0 - assign \reg_1_src31__ren 1'0 - assign \reg_2_src32__ren 1'0 - assign { \reg_2_src32__ren \reg_1_src31__ren \reg_0_src30__ren } \src3__ren - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:170" - wire width 3 \ren_delay$18 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:170" - wire width 3 \ren_delay$18$next - process $group_13 - assign \ren_delay$18$next \ren_delay$18 - assign \ren_delay$18$next \src3__ren - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \ren_delay$18$next 3'000 - end - sync init - update \ren_delay$18 3'000 - sync posedge \coresync_clk - update \ren_delay$18 \ren_delay$18$next - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" - wire width 1 $19 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" - cell $reduce_bool $20 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \ren_delay$18 - connect \Y $19 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - wire width 2 $21 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $or $22 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 2 - connect \A \reg_1_src31__data_o - connect \B \reg_2_src32__data_o - connect \Y $21 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - wire width 2 $23 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - cell $or $24 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 2 - connect \A \reg_0_src30__data_o - connect \B $21 - connect \Y $23 - end - process $group_14 - assign \src3__data_o 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:172" - switch { $19 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:172" - case 1'1 - assign \src3__data_o $23 - end - sync init - end - process $group_15 - assign \reg_0_dest10__wen 1'0 - assign \reg_1_dest11__wen 1'0 - assign \reg_2_dest12__wen 1'0 - assign { \reg_2_dest12__wen \reg_1_dest11__wen \reg_0_dest10__wen } \wen$4 - sync init - end - process $group_18 - assign \reg_0_dest10__data_i 2'00 - assign \reg_0_dest10__data_i \data_i$3 - sync init - end - process $group_19 - assign \reg_1_dest11__data_i 2'00 - assign \reg_1_dest11__data_i \data_i$3 - sync init - end - process $group_20 - assign \reg_2_dest12__data_i 2'00 - assign \reg_2_dest12__data_i \data_i$3 - sync init - end - process $group_21 - assign \reg_0_dest20__wen 1'0 - assign \reg_1_dest21__wen 1'0 - assign \reg_2_dest22__wen 1'0 - assign { \reg_2_dest22__wen \reg_1_dest21__wen \reg_0_dest20__wen } \wen - sync init - end - process $group_24 - assign \reg_0_dest20__data_i 2'00 - assign \reg_0_dest20__data_i \data_i - sync init - end - process $group_25 - assign \reg_1_dest21__data_i 2'00 - assign \reg_1_dest21__data_i \data_i - sync init - end - process $group_26 - assign \reg_2_dest22__data_i 2'00 - assign \reg_2_dest22__data_i \data_i - sync init - end - process $group_27 - assign \reg_0_dest30__wen 1'0 - assign \reg_1_dest31__wen 1'0 - assign \reg_2_dest32__wen 1'0 - assign { \reg_2_dest32__wen \reg_1_dest31__wen \reg_0_dest30__wen } \wen$2 - sync init - end - process $group_30 - assign \reg_0_dest30__data_i 2'00 - assign \reg_0_dest30__data_i \data_i$1 - sync init - end - process $group_31 - assign \reg_1_dest31__data_i 2'00 - assign \reg_1_dest31__data_i \data_i$1 - sync init - end - process $group_32 - assign \reg_2_dest32__data_i 2'00 - assign \reg_2_dest32__data_i \data_i$1 - sync init - end - process $group_33 - assign \full_rd__data_o 6'000000 - assign \full_rd__data_o { \reg_2_r2__data_o \reg_1_r1__data_o \reg_0_r0__data_o } - sync init - end - process $group_34 - assign \reg_0_r0__ren 1'0 - assign \reg_1_r1__ren 1'0 - assign \reg_2_r2__ren 1'0 - assign { \reg_2_r2__ren \reg_1_r1__ren \reg_0_r0__ren } \full_rd__ren - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 6 \full_wr__data_i - process $group_37 - assign \reg_0_w0__data_i 2'00 - assign \reg_1_w1__data_i 2'00 - assign \reg_2_w2__data_i 2'00 - assign { \reg_2_w2__data_i \reg_1_w1__data_i \reg_0_w0__data_i } \full_wr__data_i - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 3 \full_wr__wen - process $group_40 - assign \reg_0_w0__wen 1'0 - assign \reg_1_w1__wen 1'0 - assign \reg_2_w2__wen 1'0 - assign { \reg_2_w2__wen \reg_1_w1__wen \reg_0_w0__wen } \full_wr__wen - sync init - end - connect \full_wr__data_i 6'000000 - connect \full_wr__wen 3'000 -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.fast" -module \fast - attribute \src "simple/issuer.py:141" - wire width 1 input 0 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 3 input 1 \issue__addr - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 input 2 \issue__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 output 3 \issue__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 3 input 4 \issue__addr$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 input 5 \issue__wen - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 input 6 \issue__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 output 7 \src1__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 3 input 8 \src1__addr - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 input 9 \src1__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 output 10 \src2__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 3 input 11 \src2__addr - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 input 12 \src2__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 input 13 \dest1__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 3 input 14 \dest1__addr - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 input 15 \dest1__wen - attribute \src "simple/issuer.py:141" - wire width 1 input 16 \coresync_rst - memory width 64 size 8 \memory - cell $meminit $2 - parameter \MEMID "\\memory" - parameter \ABITS 4 - parameter \WIDTH 64 - parameter \WORDS 8 - parameter \PRIORITY 0 - connect \ADDR 4'0000 - connect \DATA 512'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:210" - wire width 3 \memory_r_addr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:210" - wire width 64 \memory_r_data - cell $memrd \rp_src1 - parameter \MEMID "\\memory" - parameter \ABITS 3 - parameter \WIDTH 64 - parameter \CLK_ENABLE 1 - parameter \CLK_POLARITY 1 - parameter \TRANSPARENT 1 - connect \CLK \coresync_clk - connect \EN 1'1 - connect \ADDR \memory_r_addr - connect \DATA \memory_r_data - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:210" - wire width 3 \memory_r_addr$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:210" - wire width 64 \memory_r_data$4 - cell $memrd \rp_src2 - parameter \MEMID "\\memory" - parameter \ABITS 3 - parameter \WIDTH 64 - parameter \CLK_ENABLE 1 - parameter \CLK_POLARITY 1 - parameter \TRANSPARENT 1 - connect \CLK \coresync_clk - connect \EN 1'1 - connect \ADDR \memory_r_addr$3 - connect \DATA \memory_r_data$4 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:210" - wire width 3 \memory_r_addr$5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:210" - wire width 64 \memory_r_data$6 - cell $memrd \rp_issue - parameter \MEMID "\\memory" - parameter \ABITS 3 - parameter \WIDTH 64 - parameter \CLK_ENABLE 1 - parameter \CLK_POLARITY 1 - parameter \TRANSPARENT 1 - connect \CLK \coresync_clk - connect \EN 1'1 - connect \ADDR \memory_r_addr$5 - connect \DATA \memory_r_data$6 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:218" - wire width 1 \memory_w_en - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:218" - wire width 3 \memory_w_addr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:218" - wire width 64 \memory_w_data - cell $memwr \wp_dest1 - parameter \MEMID "\\memory" - parameter \ABITS 3 - parameter \WIDTH 64 - parameter \CLK_ENABLE 1 - parameter \CLK_POLARITY 1 - parameter \PRIORITY 0 - connect \CLK \coresync_clk - connect \EN { { \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en } } - connect \ADDR \memory_w_addr - connect \DATA \memory_w_data - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:218" - wire width 1 \memory_w_en$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:218" - wire width 3 \memory_w_addr$8 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:218" - wire width 64 \memory_w_data$9 - cell $memwr \wp_issue - parameter \MEMID "\\memory" - parameter \ABITS 3 - parameter \WIDTH 64 - parameter \CLK_ENABLE 1 - parameter \CLK_POLARITY 1 - parameter \PRIORITY 0 - connect \CLK \coresync_clk - connect \EN { { \memory_w_en$7 \memory_w_en$7 \memory_w_en$7 \memory_w_en$7 \memory_w_en$7 \memory_w_en$7 \memory_w_en$7 \memory_w_en$7 \memory_w_en$7 \memory_w_en$7 \memory_w_en$7 \memory_w_en$7 \memory_w_en$7 \memory_w_en$7 \memory_w_en$7 \memory_w_en$7 \memory_w_en$7 \memory_w_en$7 \memory_w_en$7 \memory_w_en$7 \memory_w_en$7 \memory_w_en$7 \memory_w_en$7 \memory_w_en$7 \memory_w_en$7 \memory_w_en$7 \memory_w_en$7 \memory_w_en$7 \memory_w_en$7 \memory_w_en$7 \memory_w_en$7 \memory_w_en$7 \memory_w_en$7 \memory_w_en$7 \memory_w_en$7 \memory_w_en$7 \memory_w_en$7 \memory_w_en$7 \memory_w_en$7 \memory_w_en$7 \memory_w_en$7 \memory_w_en$7 \memory_w_en$7 \memory_w_en$7 \memory_w_en$7 \memory_w_en$7 \memory_w_en$7 \memory_w_en$7 \memory_w_en$7 \memory_w_en$7 \memory_w_en$7 \memory_w_en$7 \memory_w_en$7 \memory_w_en$7 \memory_w_en$7 \memory_w_en$7 \memory_w_en$7 \memory_w_en$7 \memory_w_en$7 \memory_w_en$7 \memory_w_en$7 \memory_w_en$7 \memory_w_en$7 \memory_w_en$7 } } - connect \ADDR \memory_w_addr$8 - connect \DATA \memory_w_data$9 - end - process $group_0 - assign \memory_r_addr 3'000 - assign \memory_r_addr \src1__addr - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:243" - wire width 1 \ren_delay - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:243" - wire width 1 \ren_delay$next - process $group_1 - assign \ren_delay$next \ren_delay - assign \ren_delay$next \src1__ren - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \ren_delay$next 1'0 - end - sync init - update \ren_delay 1'0 - sync posedge \coresync_clk - update \ren_delay \ren_delay$next - end - process $group_2 - assign \src1__data_o 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:245" - switch { \ren_delay } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:245" - case 1'1 - assign \src1__data_o \memory_r_data - end - sync init - end - process $group_3 - assign \memory_r_addr$3 3'000 - assign \memory_r_addr$3 \src2__addr - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:243" - wire width 1 \ren_delay$10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:243" - wire width 1 \ren_delay$10$next - process $group_4 - assign \ren_delay$10$next \ren_delay$10 - assign \ren_delay$10$next \src2__ren - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \ren_delay$10$next 1'0 - end - sync init - update \ren_delay$10 1'0 - sync posedge \coresync_clk - update \ren_delay$10 \ren_delay$10$next - end - process $group_5 - assign \src2__data_o 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:245" - switch { \ren_delay$10 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:245" - case 1'1 - assign \src2__data_o \memory_r_data$4 - end - sync init - end - process $group_6 - assign \memory_r_addr$5 3'000 - assign \memory_r_addr$5 \issue__addr - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:243" - wire width 1 \ren_delay$11 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:243" - wire width 1 \ren_delay$11$next - process $group_7 - assign \ren_delay$11$next \ren_delay$11 - assign \ren_delay$11$next \issue__ren - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \ren_delay$11$next 1'0 - end - sync init - update \ren_delay$11 1'0 - sync posedge \coresync_clk - update \ren_delay$11 \ren_delay$11$next - end - process $group_8 - assign \issue__data_o 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:245" - switch { \ren_delay$11 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:245" - case 1'1 - assign \issue__data_o \memory_r_data$6 - end - sync init - end - process $group_9 - assign \memory_w_addr 3'000 - assign \memory_w_addr \dest1__addr - sync init - end - process $group_10 - assign \memory_w_en 1'0 - assign \memory_w_en \dest1__wen - sync init - end - process $group_11 - assign \memory_w_data 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \memory_w_data \dest1__data_i - sync init - end - process $group_12 - assign \memory_w_addr$8 3'000 - assign \memory_w_addr$8 \issue__addr$1 - sync init - end - process $group_13 - assign \memory_w_en$7 1'0 - assign \memory_w_en$7 \issue__wen - sync init - end - process $group_14 - assign \memory_w_data$9 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \memory_w_data$9 \issue__data_i - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.state.reg_0" -module \reg_0$132 - attribute \src "simple/issuer.py:141" - wire width 1 input 0 \coresync_clk - attribute \src "simple/issuer.py:141" - wire width 1 input 1 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 input 2 \cia0__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 output 3 \cia0__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 \cia0__data_o$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 input 4 \msr0__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 output 5 \msr0__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 \msr0__data_o$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 input 6 \nia0__wen - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 input 7 \nia0__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 input 8 \msr0__wen - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 input 9 \msr0__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 input 10 \d_wr10__wen - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 input 11 \d_wr10__data_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" - wire width 1 \wr_detect - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_detect - connect \Y $1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" - wire width 64 \reg - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" - wire width 64 \reg$next - process $group_0 - assign \cia0__data_o$next \cia0__data_o - assign \cia0__data_o$next 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch { \cia0__ren } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch { \nia0__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - case 1'1 - assign \cia0__data_o$next \nia0__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch { \msr0__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - case 1'1 - assign \cia0__data_o$next \msr0__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch { \d_wr10__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - case 1'1 - assign \cia0__data_o$next \d_wr10__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - switch { $1 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - case 1'1 - assign \cia0__data_o$next \reg - end - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \cia0__data_o$next 64'0000000000000000000000000000000000000000000000000000000000000000 - end - sync init - update \cia0__data_o 64'0000000000000000000000000000000000000000000000000000000000000000 - sync posedge \coresync_clk - update \cia0__data_o \cia0__data_o$next - end - process $group_1 - assign \wr_detect 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch { \cia0__ren } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - case 1'1 - assign \wr_detect 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch { \nia0__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - case 1'1 - assign \wr_detect 1'1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch { \msr0__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - case 1'1 - assign \wr_detect 1'1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch { \d_wr10__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - case 1'1 - assign \wr_detect 1'1 - end - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - wire width 1 $3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" - wire width 1 \wr_detect$4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $5 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_detect$4 - connect \Y $3 - end - process $group_2 - assign \msr0__data_o$next \msr0__data_o - assign \msr0__data_o$next 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch { \msr0__ren } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch { \nia0__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - case 1'1 - assign \msr0__data_o$next \nia0__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch { \msr0__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - case 1'1 - assign \msr0__data_o$next \msr0__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch { \d_wr10__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - case 1'1 - assign \msr0__data_o$next \d_wr10__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - switch { $3 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - case 1'1 - assign \msr0__data_o$next \reg - end - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \msr0__data_o$next 64'0000000000000000000000000000000000000000000000000000000000000000 - end - sync init - update \msr0__data_o 64'0000000000000000000000000000000000000000000000000000000000000000 - sync posedge \coresync_clk - update \msr0__data_o \msr0__data_o$next - end - process $group_3 - assign \wr_detect$4 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch { \msr0__ren } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - case 1'1 - assign \wr_detect$4 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch { \nia0__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - case 1'1 - assign \wr_detect$4 1'1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch { \msr0__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - case 1'1 - assign \wr_detect$4 1'1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch { \d_wr10__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - case 1'1 - assign \wr_detect$4 1'1 - end - end - sync init - end - process $group_4 - assign \reg$next \reg - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" - switch { \nia0__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" - case 1'1 - assign \reg$next \nia0__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" - switch { \msr0__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" - case 1'1 - assign \reg$next \msr0__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" - switch { \d_wr10__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" - case 1'1 - assign \reg$next \d_wr10__data_i - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \reg$next 64'0000000000000000000000000000000000000000000000000000000000000000 - end - sync init - update \reg 64'0000000000000000000000000000000000000000000000000000000000000000 - sync posedge \coresync_clk - update \reg \reg$next - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.state.reg_1" -module \reg_1$133 - attribute \src "simple/issuer.py:141" - wire width 1 input 0 \coresync_clk - attribute \src "simple/issuer.py:141" - wire width 1 input 1 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 input 2 \cia1__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 output 3 \cia1__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 \cia1__data_o$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 input 4 \msr1__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 output 5 \msr1__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 \msr1__data_o$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 input 6 \nia1__wen - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 input 7 \nia1__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 input 8 \msr1__wen - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 input 9 \msr1__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 input 10 \d_wr11__wen - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 input 11 \d_wr11__data_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" - wire width 1 \wr_detect - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_detect - connect \Y $1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" - wire width 64 \reg - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" - wire width 64 \reg$next - process $group_0 - assign \cia1__data_o$next \cia1__data_o - assign \cia1__data_o$next 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch { \cia1__ren } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch { \nia1__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - case 1'1 - assign \cia1__data_o$next \nia1__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch { \msr1__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - case 1'1 - assign \cia1__data_o$next \msr1__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch { \d_wr11__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - case 1'1 - assign \cia1__data_o$next \d_wr11__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - switch { $1 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - case 1'1 - assign \cia1__data_o$next \reg - end - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \cia1__data_o$next 64'0000000000000000000000000000000000000000000000000000000000000000 - end - sync init - update \cia1__data_o 64'0000000000000000000000000000000000000000000000000000000000000000 - sync posedge \coresync_clk - update \cia1__data_o \cia1__data_o$next - end - process $group_1 - assign \wr_detect 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch { \cia1__ren } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - case 1'1 - assign \wr_detect 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch { \nia1__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - case 1'1 - assign \wr_detect 1'1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch { \msr1__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - case 1'1 - assign \wr_detect 1'1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch { \d_wr11__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - case 1'1 - assign \wr_detect 1'1 - end - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - wire width 1 $3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" - wire width 1 \wr_detect$4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $5 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_detect$4 - connect \Y $3 - end - process $group_2 - assign \msr1__data_o$next \msr1__data_o - assign \msr1__data_o$next 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch { \msr1__ren } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch { \nia1__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - case 1'1 - assign \msr1__data_o$next \nia1__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch { \msr1__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - case 1'1 - assign \msr1__data_o$next \msr1__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch { \d_wr11__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - case 1'1 - assign \msr1__data_o$next \d_wr11__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - switch { $3 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - case 1'1 - assign \msr1__data_o$next \reg - end - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \msr1__data_o$next 64'0000000000000000000000000000000000000000000000000000000000000000 - end - sync init - update \msr1__data_o 64'0000000000000000000000000000000000000000000000000000000000000000 - sync posedge \coresync_clk - update \msr1__data_o \msr1__data_o$next - end - process $group_3 - assign \wr_detect$4 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch { \msr1__ren } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - case 1'1 - assign \wr_detect$4 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch { \nia1__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - case 1'1 - assign \wr_detect$4 1'1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch { \msr1__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - case 1'1 - assign \wr_detect$4 1'1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch { \d_wr11__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - case 1'1 - assign \wr_detect$4 1'1 - end - end - sync init - end - process $group_4 - assign \reg$next \reg - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" - switch { \nia1__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" - case 1'1 - assign \reg$next \nia1__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" - switch { \msr1__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" - case 1'1 - assign \reg$next \msr1__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" - switch { \d_wr11__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" - case 1'1 - assign \reg$next \d_wr11__data_i - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \reg$next 64'0000000000000000000000000000000000000000000000000000000000000000 - end - sync init - update \reg 64'0000000000000000000000000000000000000000000000000000000000000000 - sync posedge \coresync_clk - update \reg \reg$next - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.state.reg_2" -module \reg_2$134 - attribute \src "simple/issuer.py:141" - wire width 1 input 0 \coresync_clk - attribute \src "simple/issuer.py:141" - wire width 1 input 1 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 input 2 \cia2__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 output 3 \cia2__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 \cia2__data_o$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 input 4 \msr2__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 output 5 \msr2__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 \msr2__data_o$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 input 6 \nia2__wen - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 input 7 \nia2__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 input 8 \msr2__wen - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 input 9 \msr2__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 input 10 \d_wr12__wen - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 input 11 \d_wr12__data_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" - wire width 1 \wr_detect - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_detect - connect \Y $1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" - wire width 64 \reg - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" - wire width 64 \reg$next - process $group_0 - assign \cia2__data_o$next \cia2__data_o - assign \cia2__data_o$next 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch { \cia2__ren } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch { \nia2__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - case 1'1 - assign \cia2__data_o$next \nia2__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch { \msr2__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - case 1'1 - assign \cia2__data_o$next \msr2__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch { \d_wr12__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - case 1'1 - assign \cia2__data_o$next \d_wr12__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - switch { $1 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - case 1'1 - assign \cia2__data_o$next \reg - end - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \cia2__data_o$next 64'0000000000000000000000000000000000000000000000000000000000000000 - end - sync init - update \cia2__data_o 64'0000000000000000000000000000000000000000000000000000000000000000 - sync posedge \coresync_clk - update \cia2__data_o \cia2__data_o$next - end - process $group_1 - assign \wr_detect 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch { \cia2__ren } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - case 1'1 - assign \wr_detect 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch { \nia2__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - case 1'1 - assign \wr_detect 1'1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch { \msr2__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - case 1'1 - assign \wr_detect 1'1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch { \d_wr12__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - case 1'1 - assign \wr_detect 1'1 - end - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - wire width 1 $3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" - wire width 1 \wr_detect$4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $5 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_detect$4 - connect \Y $3 - end - process $group_2 - assign \msr2__data_o$next \msr2__data_o - assign \msr2__data_o$next 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch { \msr2__ren } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch { \nia2__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - case 1'1 - assign \msr2__data_o$next \nia2__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch { \msr2__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - case 1'1 - assign \msr2__data_o$next \msr2__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch { \d_wr12__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - case 1'1 - assign \msr2__data_o$next \d_wr12__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - switch { $3 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - case 1'1 - assign \msr2__data_o$next \reg - end - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \msr2__data_o$next 64'0000000000000000000000000000000000000000000000000000000000000000 - end - sync init - update \msr2__data_o 64'0000000000000000000000000000000000000000000000000000000000000000 - sync posedge \coresync_clk - update \msr2__data_o \msr2__data_o$next - end - process $group_3 - assign \wr_detect$4 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch { \msr2__ren } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - case 1'1 - assign \wr_detect$4 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch { \nia2__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - case 1'1 - assign \wr_detect$4 1'1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch { \msr2__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - case 1'1 - assign \wr_detect$4 1'1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch { \d_wr12__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - case 1'1 - assign \wr_detect$4 1'1 - end - end - sync init - end - process $group_4 - assign \reg$next \reg - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" - switch { \nia2__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" - case 1'1 - assign \reg$next \nia2__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" - switch { \msr2__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" - case 1'1 - assign \reg$next \msr2__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" - switch { \d_wr12__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" - case 1'1 - assign \reg$next \d_wr12__data_i - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \reg$next 64'0000000000000000000000000000000000000000000000000000000000000000 - end - sync init - update \reg 64'0000000000000000000000000000000000000000000000000000000000000000 - sync posedge \coresync_clk - update \reg \reg$next - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.state.reg_3" -module \reg_3$135 - attribute \src "simple/issuer.py:141" - wire width 1 input 0 \coresync_clk - attribute \src "simple/issuer.py:141" - wire width 1 input 1 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 input 2 \cia3__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 output 3 \cia3__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 \cia3__data_o$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 input 4 \msr3__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 output 5 \msr3__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 \msr3__data_o$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 input 6 \nia3__wen - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 input 7 \nia3__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 input 8 \msr3__wen - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 input 9 \msr3__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 input 10 \d_wr13__wen - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 input 11 \d_wr13__data_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" - wire width 1 \wr_detect - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_detect - connect \Y $1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" - wire width 64 \reg - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:59" - wire width 64 \reg$next - process $group_0 - assign \cia3__data_o$next \cia3__data_o - assign \cia3__data_o$next 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch { \cia3__ren } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch { \nia3__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - case 1'1 - assign \cia3__data_o$next \nia3__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch { \msr3__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - case 1'1 - assign \cia3__data_o$next \msr3__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch { \d_wr13__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - case 1'1 - assign \cia3__data_o$next \d_wr13__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - switch { $1 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - case 1'1 - assign \cia3__data_o$next \reg - end - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \cia3__data_o$next 64'0000000000000000000000000000000000000000000000000000000000000000 - end - sync init - update \cia3__data_o 64'0000000000000000000000000000000000000000000000000000000000000000 - sync posedge \coresync_clk - update \cia3__data_o \cia3__data_o$next - end - process $group_1 - assign \wr_detect 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch { \cia3__ren } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - case 1'1 - assign \wr_detect 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch { \nia3__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - case 1'1 - assign \wr_detect 1'1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch { \msr3__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - case 1'1 - assign \wr_detect 1'1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch { \d_wr13__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - case 1'1 - assign \wr_detect 1'1 - end - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - wire width 1 $3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:71" - wire width 1 \wr_detect$4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - cell $not $5 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_detect$4 - connect \Y $3 - end - process $group_2 - assign \msr3__data_o$next \msr3__data_o - assign \msr3__data_o$next 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch { \msr3__ren } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch { \nia3__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - case 1'1 - assign \msr3__data_o$next \nia3__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch { \msr3__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - case 1'1 - assign \msr3__data_o$next \msr3__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch { \d_wr13__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - case 1'1 - assign \msr3__data_o$next \d_wr13__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - switch { $3 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:77" - case 1'1 - assign \msr3__data_o$next \reg - end - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \msr3__data_o$next 64'0000000000000000000000000000000000000000000000000000000000000000 - end - sync init - update \msr3__data_o 64'0000000000000000000000000000000000000000000000000000000000000000 - sync posedge \coresync_clk - update \msr3__data_o \msr3__data_o$next - end - process $group_3 - assign \wr_detect$4 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - switch { \msr3__ren } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:69" - case 1'1 - assign \wr_detect$4 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch { \nia3__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - case 1'1 - assign \wr_detect$4 1'1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch { \msr3__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - case 1'1 - assign \wr_detect$4 1'1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - switch { \d_wr13__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:74" - case 1'1 - assign \wr_detect$4 1'1 - end - end - sync init - end - process $group_4 - assign \reg$next \reg - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" - switch { \nia3__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" - case 1'1 - assign \reg$next \nia3__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" - switch { \msr3__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" - case 1'1 - assign \reg$next \msr3__data_i - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" - switch { \d_wr13__wen } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:84" - case 1'1 - assign \reg$next \d_wr13__data_i - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \reg$next 64'0000000000000000000000000000000000000000000000000000000000000000 - end - sync init - update \reg 64'0000000000000000000000000000000000000000000000000000000000000000 - sync posedge \coresync_clk - update \reg \reg$next - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.state" -module \state - attribute \src "simple/issuer.py:141" - wire width 1 input 0 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 input 1 \cia__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 output 2 \cia__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 input 3 \wen - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 input 4 \data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 input 5 \msr__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 output 6 \msr__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 input 7 \state_nia_wen - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 input 8 \data_i$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 input 9 \data_i$2 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 input 10 \wen$3 - attribute \src "simple/issuer.py:141" - wire width 1 input 11 \coresync_rst - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 \reg_0_cia0__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 \reg_0_cia0__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 \reg_0_msr0__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 \reg_0_msr0__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 \reg_0_nia0__wen - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 \reg_0_nia0__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 \reg_0_msr0__wen - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 \reg_0_msr0__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 \reg_0_d_wr10__wen - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 \reg_0_d_wr10__data_i - cell \reg_0$132 \reg_0 - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \cia0__ren \reg_0_cia0__ren - connect \cia0__data_o \reg_0_cia0__data_o - connect \msr0__ren \reg_0_msr0__ren - connect \msr0__data_o \reg_0_msr0__data_o - connect \nia0__wen \reg_0_nia0__wen - connect \nia0__data_i \reg_0_nia0__data_i - connect \msr0__wen \reg_0_msr0__wen - connect \msr0__data_i \reg_0_msr0__data_i - connect \d_wr10__wen \reg_0_d_wr10__wen - connect \d_wr10__data_i \reg_0_d_wr10__data_i - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 \reg_1_cia1__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 \reg_1_cia1__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 \reg_1_msr1__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 \reg_1_msr1__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 \reg_1_nia1__wen - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 \reg_1_nia1__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 \reg_1_msr1__wen - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 \reg_1_msr1__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 \reg_1_d_wr11__wen - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 \reg_1_d_wr11__data_i - cell \reg_1$133 \reg_1 - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \cia1__ren \reg_1_cia1__ren - connect \cia1__data_o \reg_1_cia1__data_o - connect \msr1__ren \reg_1_msr1__ren - connect \msr1__data_o \reg_1_msr1__data_o - connect \nia1__wen \reg_1_nia1__wen - connect \nia1__data_i \reg_1_nia1__data_i - connect \msr1__wen \reg_1_msr1__wen - connect \msr1__data_i \reg_1_msr1__data_i - connect \d_wr11__wen \reg_1_d_wr11__wen - connect \d_wr11__data_i \reg_1_d_wr11__data_i - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 \reg_2_cia2__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 \reg_2_cia2__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 \reg_2_msr2__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 \reg_2_msr2__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 \reg_2_nia2__wen - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 \reg_2_nia2__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 \reg_2_msr2__wen - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 \reg_2_msr2__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 \reg_2_d_wr12__wen - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 \reg_2_d_wr12__data_i - cell \reg_2$134 \reg_2 - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \cia2__ren \reg_2_cia2__ren - connect \cia2__data_o \reg_2_cia2__data_o - connect \msr2__ren \reg_2_msr2__ren - connect \msr2__data_o \reg_2_msr2__data_o - connect \nia2__wen \reg_2_nia2__wen - connect \nia2__data_i \reg_2_nia2__data_i - connect \msr2__wen \reg_2_msr2__wen - connect \msr2__data_i \reg_2_msr2__data_i - connect \d_wr12__wen \reg_2_d_wr12__wen - connect \d_wr12__data_i \reg_2_d_wr12__data_i - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 \reg_3_cia3__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 \reg_3_cia3__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 \reg_3_msr3__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 \reg_3_msr3__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 \reg_3_nia3__wen - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 \reg_3_nia3__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 \reg_3_msr3__wen - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 \reg_3_msr3__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 \reg_3_d_wr13__wen - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 \reg_3_d_wr13__data_i - cell \reg_3$135 \reg_3 - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \cia3__ren \reg_3_cia3__ren - connect \cia3__data_o \reg_3_cia3__data_o - connect \msr3__ren \reg_3_msr3__ren - connect \msr3__data_o \reg_3_msr3__data_o - connect \nia3__wen \reg_3_nia3__wen - connect \nia3__data_i \reg_3_nia3__data_i - connect \msr3__wen \reg_3_msr3__wen - connect \msr3__data_i \reg_3_msr3__data_i - connect \d_wr13__wen \reg_3_d_wr13__wen - connect \d_wr13__data_i \reg_3_d_wr13__data_i - end - process $group_0 - assign \reg_0_cia0__ren 1'0 - assign \reg_1_cia1__ren 1'0 - assign \reg_2_cia2__ren 1'0 - assign \reg_3_cia3__ren 1'0 - assign { \reg_3_cia3__ren \reg_2_cia2__ren \reg_1_cia1__ren \reg_0_cia0__ren } \cia__ren - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:170" - wire width 4 \ren_delay - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:170" - wire width 4 \ren_delay$next - process $group_4 - assign \ren_delay$next \ren_delay - assign \ren_delay$next \cia__ren - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \ren_delay$next 4'0000 - end - sync init - update \ren_delay 4'0000 - sync posedge \coresync_clk - update \ren_delay \ren_delay$next - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" - wire width 1 $4 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" - cell $reduce_bool $5 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \ren_delay - connect \Y $4 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - wire width 64 $6 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $or $7 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \B_SIGNED 0 - parameter \B_WIDTH 64 - parameter \Y_WIDTH 64 - connect \A \reg_0_cia0__data_o - connect \B \reg_1_cia1__data_o - connect \Y $6 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - wire width 64 $8 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $or $9 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \B_SIGNED 0 - parameter \B_WIDTH 64 - parameter \Y_WIDTH 64 - connect \A \reg_2_cia2__data_o - connect \B \reg_3_cia3__data_o - connect \Y $8 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - wire width 64 $10 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - cell $or $11 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \B_SIGNED 0 - parameter \B_WIDTH 64 - parameter \Y_WIDTH 64 - connect \A $6 - connect \B $8 - connect \Y $10 - end - process $group_5 - assign \cia__data_o 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:172" - switch { $4 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:172" - case 1'1 - assign \cia__data_o $10 - end - sync init - end - process $group_6 - assign \reg_0_msr0__ren 1'0 - assign \reg_1_msr1__ren 1'0 - assign \reg_2_msr2__ren 1'0 - assign \reg_3_msr3__ren 1'0 - assign { \reg_3_msr3__ren \reg_2_msr2__ren \reg_1_msr1__ren \reg_0_msr0__ren } \msr__ren - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:170" - wire width 4 \ren_delay$12 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:170" - wire width 4 \ren_delay$12$next - process $group_10 - assign \ren_delay$12$next \ren_delay$12 - assign \ren_delay$12$next \msr__ren - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \ren_delay$12$next 4'0000 - end - sync init - update \ren_delay$12 4'0000 - sync posedge \coresync_clk - update \ren_delay$12 \ren_delay$12$next - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" - wire width 1 $13 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" - cell $reduce_bool $14 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A \ren_delay$12 - connect \Y $13 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - wire width 64 $15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $or $16 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \B_SIGNED 0 - parameter \B_WIDTH 64 - parameter \Y_WIDTH 64 - connect \A \reg_0_msr0__data_o - connect \B \reg_1_msr1__data_o - connect \Y $15 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - wire width 64 $17 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $or $18 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \B_SIGNED 0 - parameter \B_WIDTH 64 - parameter \Y_WIDTH 64 - connect \A \reg_2_msr2__data_o - connect \B \reg_3_msr3__data_o - connect \Y $17 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - wire width 64 $19 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - cell $or $20 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \B_SIGNED 0 - parameter \B_WIDTH 64 - parameter \Y_WIDTH 64 - connect \A $15 - connect \B $17 - connect \Y $19 - end - process $group_11 - assign \msr__data_o 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:172" - switch { $13 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:172" - case 1'1 - assign \msr__data_o $19 - end - sync init - end - process $group_12 - assign \reg_0_nia0__wen 1'0 - assign \reg_1_nia1__wen 1'0 - assign \reg_2_nia2__wen 1'0 - assign \reg_3_nia3__wen 1'0 - assign { \reg_3_nia3__wen \reg_2_nia2__wen \reg_1_nia1__wen \reg_0_nia0__wen } \state_nia_wen - sync init - end - process $group_16 - assign \reg_0_nia0__data_i 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \reg_0_nia0__data_i \data_i$1 - sync init - end - process $group_17 - assign \reg_1_nia1__data_i 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \reg_1_nia1__data_i \data_i$1 - sync init - end - process $group_18 - assign \reg_2_nia2__data_i 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \reg_2_nia2__data_i \data_i$1 - sync init - end - process $group_19 - assign \reg_3_nia3__data_i 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \reg_3_nia3__data_i \data_i$1 - sync init - end - process $group_20 - assign \reg_0_msr0__wen 1'0 - assign \reg_1_msr1__wen 1'0 - assign \reg_2_msr2__wen 1'0 - assign \reg_3_msr3__wen 1'0 - assign { \reg_3_msr3__wen \reg_2_msr2__wen \reg_1_msr1__wen \reg_0_msr0__wen } \wen$3 - sync init - end - process $group_24 - assign \reg_0_msr0__data_i 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \reg_0_msr0__data_i \data_i$2 - sync init - end - process $group_25 - assign \reg_1_msr1__data_i 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \reg_1_msr1__data_i \data_i$2 - sync init - end - process $group_26 - assign \reg_2_msr2__data_i 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \reg_2_msr2__data_i \data_i$2 - sync init - end - process $group_27 - assign \reg_3_msr3__data_i 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \reg_3_msr3__data_i \data_i$2 - sync init - end - process $group_28 - assign \reg_0_d_wr10__wen 1'0 - assign \reg_1_d_wr11__wen 1'0 - assign \reg_2_d_wr12__wen 1'0 - assign \reg_3_d_wr13__wen 1'0 - assign { \reg_3_d_wr13__wen \reg_2_d_wr12__wen \reg_1_d_wr11__wen \reg_0_d_wr10__wen } \wen - sync init - end - process $group_32 - assign \reg_0_d_wr10__data_i 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \reg_0_d_wr10__data_i \data_i - sync init - end - process $group_33 - assign \reg_1_d_wr11__data_i 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \reg_1_d_wr11__data_i \data_i - sync init - end - process $group_34 - assign \reg_2_d_wr12__data_i 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \reg_2_d_wr12__data_i \data_i - sync init - end - process $group_35 - assign \reg_3_d_wr13__data_i 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \reg_3_d_wr13__data_i \data_i - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.spr" -module \spr - attribute \src "simple/issuer.py:141" - wire width 1 input 0 \coresync_clk - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 output 1 \spr1__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 7 input 2 \spr1__addr - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 input 3 \spr1__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 input 4 \spr1__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 7 input 5 \spr1__addr$1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 input 6 \spr1__wen - attribute \src "simple/issuer.py:141" - wire width 1 input 7 \coresync_rst - memory width 64 size 110 \memory - cell $meminit $2 - parameter \MEMID "\\memory" - parameter \ABITS 7 - parameter \WIDTH 64 - parameter \WORDS 110 - parameter \PRIORITY 0 - connect \ADDR 7'0000000 - connect \DATA 7040'000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000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- end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:210" - wire width 7 \memory_r_addr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:210" - wire width 64 \memory_r_data - cell $memrd \rp_spr1 - parameter \MEMID "\\memory" - parameter \ABITS 7 - parameter \WIDTH 64 - parameter \CLK_ENABLE 1 - parameter \CLK_POLARITY 1 - parameter \TRANSPARENT 1 - connect \CLK \coresync_clk - connect \EN 1'1 - connect \ADDR \memory_r_addr - connect \DATA \memory_r_data - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:218" - wire width 1 \memory_w_en - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:218" - wire width 7 \memory_w_addr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:218" - wire width 64 \memory_w_data - cell $memwr \wp_spr1 - parameter \MEMID "\\memory" - parameter \ABITS 7 - parameter \WIDTH 64 - parameter \CLK_ENABLE 1 - parameter \CLK_POLARITY 1 - parameter \PRIORITY 0 - connect \CLK \coresync_clk - connect \EN { { \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en \memory_w_en } } - connect \ADDR \memory_w_addr - connect \DATA \memory_w_data - end - process $group_0 - assign \memory_r_addr 7'0000000 - assign \memory_r_addr \spr1__addr - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:243" - wire width 1 \ren_delay - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:243" - wire width 1 \ren_delay$next - process $group_1 - assign \ren_delay$next \ren_delay - assign \ren_delay$next \spr1__ren - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \ren_delay$next 1'0 - end - sync init - update \ren_delay 1'0 - sync posedge \coresync_clk - update \ren_delay \ren_delay$next - end - process $group_2 - assign \spr1__data_o 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:245" - switch { \ren_delay } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/regfile/regfile.py:245" - case 1'1 - assign \spr1__data_o \memory_r_data - end - sync init - end - process $group_3 - assign \memory_w_addr 7'0000000 - assign \memory_w_addr \spr1__addr$1 - sync init - end - process $group_4 - assign \memory_w_en 1'0 - assign \memory_w_en \spr1__wen - sync init - end - process $group_5 - assign \memory_w_data 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \memory_w_data \spr1__data_i - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.dec_ALU.dec.ALU_dec19" -module \ALU_dec19 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" - wire width 32 input 0 \opcode_in - attribute \enum_base_type "Function" - attribute \enum_value_00000000000 "NONE" - attribute \enum_value_00000000010 "ALU" - attribute \enum_value_00000000100 "LDST" - attribute \enum_value_00000001000 "SHIFT_ROT" - attribute \enum_value_00000010000 "LOGICAL" - attribute \enum_value_00000100000 "BRANCH" - attribute \enum_value_00001000000 "CR" - attribute \enum_value_00010000000 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\enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 2 output 9 \ALU_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 output 10 \ALU_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 output 11 \ALU_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 output 12 \ALU_cry_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 output 13 \ALU_is_32b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 output 14 \ALU_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:308" - wire width 10 \opcode_switch - process $group_0 - assign \opcode_switch 10'0000000000 - assign \opcode_switch \opcode_in [10:1] - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:308" - wire width 5 \opcode_switch$1 - process $group_1 - assign \ALU_function_unit 11'00000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 10'0010010110 - assign \ALU_function_unit 11'00000000010 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00010 - assign \ALU_function_unit 11'00000000010 - end - sync init - end - process $group_2 - assign \ALU_internal_op 7'0000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 10'0010010110 - assign \ALU_internal_op 7'0100100 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00010 - assign \ALU_internal_op 7'0000000 - end - sync init - end - process $group_3 - assign \ALU_in1_sel 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 10'0010010110 - assign \ALU_in1_sel 3'000 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00010 - assign \ALU_in1_sel 3'000 - end - sync init - end - process $group_4 - assign \ALU_in2_sel 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 10'0010010110 - assign \ALU_in2_sel 4'0000 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00010 - assign \ALU_in2_sel 4'0000 - end - sync init - end - process $group_5 - assign \ALU_cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 10'0010010110 - assign \ALU_cr_in 3'000 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00010 - assign \ALU_cr_in 3'000 - end - sync init - end - process $group_6 - assign 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"/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00010 - assign \ALU_ldst_len 4'0000 - end - sync init - end - process $group_8 - assign \ALU_rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 10'0010010110 - assign \ALU_rc_sel 2'00 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00010 - assign \ALU_rc_sel 2'10 - end - sync init - end - process $group_9 - assign \ALU_cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 10'0010010110 - assign \ALU_cry_in 2'00 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00010 - assign \ALU_cry_in 2'00 - end - sync init - end - process $group_10 - assign \ALU_inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 10'0010010110 - assign \ALU_inv_a 1'0 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00010 - assign \ALU_inv_a 1'0 - end - sync init - end - process $group_11 - assign \ALU_inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 10'0010010110 - assign \ALU_inv_out 1'0 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00010 - assign \ALU_inv_out 1'0 - end - sync init - end - process $group_12 - assign \ALU_cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 10'0010010110 - assign \ALU_cry_out 1'0 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00010 - assign \ALU_cry_out 1'0 - end - sync init - end - process $group_13 - assign \ALU_is_32b 1'0 - attribute \src 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\enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 7 output 2 \ALU_internal_op - attribute \enum_base_type "In1Sel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "RA" - attribute \enum_value_010 "RA_OR_ZERO" - attribute \enum_value_011 "SPR" - attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 output 3 \ALU_in1_sel - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 4 output 4 \ALU_in2_sel - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 output 5 \ALU_cr_in - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 output 6 \ALU_cr_out - attribute \enum_base_type "LdstLen" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "is1B" - attribute \enum_value_0010 "is2B" - attribute \enum_value_0100 "is4B" - attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 4 output 7 \ALU_ldst_len - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 2 output 8 \ALU_rc_sel - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 2 output 9 \ALU_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 output 10 \ALU_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 output 11 \ALU_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 output 12 \ALU_cry_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 output 13 \ALU_is_32b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 output 14 \ALU_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:308" - wire width 5 \opcode_switch - process $group_0 - assign \opcode_switch 5'00000 - assign \opcode_switch \opcode_in [10:6] - sync init - end - process $group_1 - assign \ALU_function_unit 11'00000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01000 - assign \ALU_function_unit 11'00000000010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11000 - assign \ALU_function_unit 11'00000000010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \ALU_function_unit 11'00000000010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10000 - assign \ALU_function_unit 11'00000000010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00100 - assign \ALU_function_unit 11'00000000010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10100 - assign \ALU_function_unit 11'00000000010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00111 - assign \ALU_function_unit 11'00000000010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10111 - assign \ALU_function_unit 11'00000000010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00110 - assign \ALU_function_unit 11'00000000010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10110 - assign \ALU_function_unit 11'00000000010 - end - sync init - end - process $group_2 - assign \ALU_internal_op 7'0000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01000 - assign \ALU_internal_op 7'0000010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11000 - assign \ALU_internal_op 7'0000010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \ALU_internal_op 7'0000010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10000 - assign \ALU_internal_op 7'0000010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00100 - assign \ALU_internal_op 7'0000010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10100 - assign \ALU_internal_op 7'0000010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00111 - assign \ALU_internal_op 7'0000010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10111 - assign \ALU_internal_op 7'0000010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00110 - assign \ALU_internal_op 7'0000010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10110 - assign \ALU_internal_op 7'0000010 - end - sync init - end - process $group_3 - assign \ALU_in1_sel 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01000 - assign \ALU_in1_sel 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11000 - assign \ALU_in1_sel 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \ALU_in1_sel 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10000 - assign \ALU_in1_sel 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00100 - assign \ALU_in1_sel 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10100 - assign \ALU_in1_sel 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00111 - assign \ALU_in1_sel 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10111 - assign \ALU_in1_sel 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00110 - assign \ALU_in1_sel 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10110 - assign \ALU_in1_sel 3'001 - end - sync init - end - process $group_4 - assign \ALU_in2_sel 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01000 - assign \ALU_in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11000 - assign \ALU_in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \ALU_in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10000 - assign \ALU_in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00100 - assign \ALU_in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10100 - assign \ALU_in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00111 - assign \ALU_in2_sel 4'1001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10111 - assign \ALU_in2_sel 4'1001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00110 - assign \ALU_in2_sel 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10110 - assign \ALU_in2_sel 4'0000 - end - sync init - end - process $group_5 - assign \ALU_cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01000 - assign \ALU_cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11000 - assign \ALU_cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \ALU_cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10000 - assign \ALU_cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00100 - assign \ALU_cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10100 - assign \ALU_cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00111 - assign \ALU_cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10111 - assign \ALU_cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00110 - assign \ALU_cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10110 - assign \ALU_cr_in 3'000 - end - sync init - end - process $group_6 - assign \ALU_cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01000 - assign \ALU_cr_out 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11000 - assign \ALU_cr_out 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \ALU_cr_out 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10000 - assign \ALU_cr_out 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00100 - assign \ALU_cr_out 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10100 - assign \ALU_cr_out 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00111 - assign \ALU_cr_out 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10111 - assign \ALU_cr_out 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00110 - assign \ALU_cr_out 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10110 - assign \ALU_cr_out 3'001 - end - sync init - end - process $group_7 - assign \ALU_ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01000 - assign \ALU_ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11000 - assign \ALU_ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \ALU_ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10000 - assign \ALU_ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00100 - assign \ALU_ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10100 - assign \ALU_ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00111 - assign \ALU_ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10111 - assign \ALU_ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00110 - assign \ALU_ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10110 - assign \ALU_ldst_len 4'0000 - end - sync init - end - process $group_8 - assign \ALU_rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01000 - assign \ALU_rc_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11000 - assign \ALU_rc_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \ALU_rc_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10000 - assign \ALU_rc_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00100 - assign \ALU_rc_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10100 - assign \ALU_rc_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00111 - assign \ALU_rc_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10111 - assign \ALU_rc_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00110 - assign \ALU_rc_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10110 - assign \ALU_rc_sel 2'10 - end - sync init - end - process $group_9 - assign \ALU_cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01000 - assign \ALU_cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11000 - assign \ALU_cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \ALU_cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10000 - assign \ALU_cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00100 - assign \ALU_cry_in 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10100 - assign \ALU_cry_in 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00111 - assign \ALU_cry_in 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10111 - assign \ALU_cry_in 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00110 - assign \ALU_cry_in 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10110 - assign \ALU_cry_in 2'10 - end - sync init - end - process $group_10 - assign \ALU_inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01000 - assign \ALU_inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11000 - assign \ALU_inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \ALU_inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10000 - assign \ALU_inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00100 - assign \ALU_inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10100 - assign \ALU_inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00111 - assign \ALU_inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10111 - assign \ALU_inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00110 - assign \ALU_inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10110 - assign \ALU_inv_a 1'0 - end - sync init - end - process $group_11 - assign \ALU_inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01000 - assign \ALU_inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11000 - assign \ALU_inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \ALU_inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10000 - assign \ALU_inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00100 - assign \ALU_inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10100 - assign \ALU_inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00111 - assign \ALU_inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10111 - assign \ALU_inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00110 - assign \ALU_inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10110 - assign \ALU_inv_out 1'0 - end - sync init - end - process $group_12 - assign \ALU_cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01000 - assign \ALU_cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11000 - assign \ALU_cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \ALU_cry_out 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10000 - assign \ALU_cry_out 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00100 - assign \ALU_cry_out 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10100 - assign \ALU_cry_out 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00111 - assign \ALU_cry_out 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10111 - assign \ALU_cry_out 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00110 - assign \ALU_cry_out 1'1 - attribute \src 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5'10100 - assign \ALU_is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00111 - assign \ALU_is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10111 - assign \ALU_is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00110 - assign \ALU_is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10110 - assign \ALU_is_32b 1'0 - end - sync init - end - process $group_14 - assign \ALU_sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01000 - assign \ALU_sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11000 - assign \ALU_sgn 1'0 - attribute \src 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width 2 output 8 \ALU_rc_sel - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 2 output 9 \ALU_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 output 10 \ALU_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 output 11 \ALU_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 output 12 \ALU_cry_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 output 13 \ALU_is_32b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 output 14 \ALU_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:308" - wire width 5 \opcode_switch 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assign \ALU_internal_op 7'0001010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00111 - assign \ALU_internal_op 7'0001100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00001 - assign \ALU_internal_op 7'0001010 - end - sync init - end - process $group_3 - assign \ALU_in1_sel 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \ALU_in1_sel 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00111 - assign \ALU_in1_sel 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00001 - assign \ALU_in1_sel 3'001 - end - sync init - end - process $group_4 - assign \ALU_in2_sel 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \ALU_in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00111 - assign \ALU_in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00001 - assign \ALU_in2_sel 4'0001 - end - sync init - end - process $group_5 - assign \ALU_cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \ALU_cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00111 - assign \ALU_cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00001 - assign \ALU_cr_in 3'000 - end - sync init - end - process $group_6 - assign \ALU_cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \ALU_cr_out 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00111 - assign \ALU_cr_out 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00001 - assign \ALU_cr_out 3'010 - end - sync init - end - process $group_7 - assign \ALU_ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \ALU_ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00111 - assign \ALU_ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00001 - assign \ALU_ldst_len 4'0000 - end - sync init - end - process $group_8 - assign \ALU_rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \ALU_rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00111 - assign \ALU_rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00001 - assign \ALU_rc_sel 2'00 - end - sync init - end - process $group_9 - assign \ALU_cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \ALU_cry_in 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00111 - assign \ALU_cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00001 - assign \ALU_cry_in 2'01 - end - sync init - end - process $group_10 - assign \ALU_inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \ALU_inv_a 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00111 - assign \ALU_inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00001 - assign \ALU_inv_a 1'1 - end - sync init - end - process $group_11 - assign \ALU_inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \ALU_inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00111 - assign \ALU_inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00001 - assign \ALU_inv_out 1'0 - end - sync init - end - process $group_12 - assign \ALU_cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \ALU_cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00111 - assign \ALU_cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00001 - assign \ALU_cry_out 1'0 - end - sync init - end - process $group_13 - assign \ALU_is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \ALU_is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00111 - assign \ALU_is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00001 - assign \ALU_is_32b 1'0 - end - sync init - end - process $group_14 - assign \ALU_sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \ALU_sgn 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00111 - assign \ALU_sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00001 - assign \ALU_sgn 1'0 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"/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 output 11 \ALU_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 output 12 \ALU_cry_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 output 13 \ALU_is_32b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 output 14 \ALU_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:308" - wire width 5 \opcode_switch - process $group_0 - assign \opcode_switch 5'00000 - assign \opcode_switch \opcode_in [10:6] - sync init - end - process $group_1 - assign \ALU_function_unit 11'00000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11101 - assign \ALU_function_unit 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5'11110 - assign \ALU_in2_sel 4'0000 - end - sync init - end - process $group_5 - assign \ALU_cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11101 - assign \ALU_cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11100 - assign \ALU_cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11110 - assign \ALU_cr_in 3'000 - end - sync init - end - process $group_6 - assign \ALU_cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11101 - assign \ALU_cr_out 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11100 - assign 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attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11101 - assign \ALU_inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11100 - assign \ALU_inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11110 - assign \ALU_inv_a 1'0 - end - sync init - end - process $group_11 - assign \ALU_inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11101 - assign \ALU_inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11100 - assign \ALU_inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11110 - assign \ALU_inv_out 1'0 - end - sync init - end - process $group_12 - assign \ALU_cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11101 - assign \ALU_cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11100 - assign \ALU_cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11110 - assign \ALU_cry_out 1'0 - end - sync init - end - process $group_13 - assign \ALU_is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11101 - assign \ALU_is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11100 - assign \ALU_is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11110 - assign \ALU_is_32b 1'0 - end - sync init - end - process $group_14 - assign \ALU_sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11101 - assign \ALU_sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11100 - assign \ALU_sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11110 - assign \ALU_sgn 1'0 - end - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.dec_ALU.dec.ALU_dec31.ALU_dec_sub19" -module \ALU_dec_sub19 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" - wire width 32 input 0 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:308" - wire width 5 \opcode_switch - process $group_0 - assign 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\enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 7 output 2 \ALU_internal_op - attribute \enum_base_type "In1Sel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "RA" - attribute \enum_value_010 "RA_OR_ZERO" - attribute \enum_value_011 "SPR" - attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 output 3 \ALU_in1_sel - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 4 output 4 \ALU_in2_sel - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 output 5 \ALU_cr_in - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 output 6 \ALU_cr_out - attribute \enum_base_type "LdstLen" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "is1B" - attribute \enum_value_0010 "is2B" - attribute \enum_value_0100 "is4B" - attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 4 output 7 \ALU_ldst_len - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 2 output 8 \ALU_rc_sel - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 2 output 9 \ALU_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 output 10 \ALU_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 output 11 \ALU_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 output 12 \ALU_cry_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 output 13 \ALU_is_32b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 output 14 \ALU_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:308" - wire width 5 \opcode_switch - process $group_0 - assign \opcode_switch 5'00000 - assign \opcode_switch \opcode_in [10:6] - sync init - end - process $group_1 - assign \ALU_function_unit 11'00000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00010 - assign \ALU_function_unit 11'00000000010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00001 - assign \ALU_function_unit 11'00000000010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01000 - assign \ALU_function_unit 11'00000000010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00111 - assign \ALU_function_unit 11'00000000010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11110 - assign \ALU_function_unit 11'00000000010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \ALU_function_unit 11'00000000010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10010 - assign \ALU_function_unit 11'00000000010 - end - sync init - end - process $group_2 - assign \ALU_internal_op 7'0000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00010 - assign \ALU_internal_op 7'0000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00001 - assign \ALU_internal_op 7'0000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01000 - assign \ALU_internal_op 7'0000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00111 - assign \ALU_internal_op 7'0000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11110 - assign \ALU_internal_op 7'0100001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \ALU_internal_op 7'0000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10010 - assign \ALU_internal_op 7'0000001 - end - sync init - end - process $group_3 - assign \ALU_in1_sel 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00010 - assign \ALU_in1_sel 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00001 - assign \ALU_in1_sel 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01000 - assign \ALU_in1_sel 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00111 - assign \ALU_in1_sel 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11110 - assign \ALU_in1_sel 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \ALU_in1_sel 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10010 - assign \ALU_in1_sel 3'000 - end - sync init - end - process $group_4 - assign \ALU_in2_sel 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00010 - assign \ALU_in2_sel 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00001 - assign \ALU_in2_sel 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01000 - assign \ALU_in2_sel 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00111 - assign \ALU_in2_sel 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11110 - assign \ALU_in2_sel 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \ALU_in2_sel 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10010 - assign \ALU_in2_sel 4'0000 - end - sync init - end - process $group_5 - assign \ALU_cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00010 - assign \ALU_cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00001 - assign \ALU_cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01000 - assign \ALU_cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00111 - assign \ALU_cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11110 - assign \ALU_cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \ALU_cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10010 - assign \ALU_cr_in 3'000 - end - sync init - end - process $group_6 - assign \ALU_cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00010 - assign \ALU_cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00001 - assign \ALU_cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01000 - assign \ALU_cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00111 - assign \ALU_cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11110 - assign \ALU_cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \ALU_cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10010 - assign \ALU_cr_out 3'000 - end - sync init - end - process $group_7 - assign \ALU_ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00010 - assign \ALU_ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00001 - assign \ALU_ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01000 - assign \ALU_ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00111 - assign \ALU_ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11110 - assign \ALU_ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \ALU_ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10010 - assign \ALU_ldst_len 4'0000 - end - sync init - end - process $group_8 - assign \ALU_rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00010 - assign \ALU_rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00001 - assign \ALU_rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01000 - assign \ALU_rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00111 - assign \ALU_rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11110 - assign \ALU_rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \ALU_rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10010 - assign \ALU_rc_sel 2'00 - end - sync init - end - process $group_9 - assign \ALU_cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00010 - assign \ALU_cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00001 - assign \ALU_cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01000 - assign \ALU_cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00111 - assign \ALU_cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11110 - assign \ALU_cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \ALU_cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10010 - assign \ALU_cry_in 2'00 - end - sync init - end - process $group_10 - assign \ALU_inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00010 - assign \ALU_inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00001 - assign \ALU_inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01000 - assign \ALU_inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00111 - assign \ALU_inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11110 - assign \ALU_inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \ALU_inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10010 - assign \ALU_inv_a 1'0 - end - sync init - end - process $group_11 - assign \ALU_inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00010 - assign \ALU_inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00001 - assign \ALU_inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01000 - assign \ALU_inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00111 - assign \ALU_inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11110 - assign \ALU_inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \ALU_inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10010 - assign \ALU_inv_out 1'0 - end - sync init - end - process $group_12 - assign \ALU_cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00010 - assign \ALU_cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00001 - assign \ALU_cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01000 - assign \ALU_cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00111 - assign \ALU_cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11110 - assign \ALU_cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \ALU_cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10010 - assign \ALU_cry_out 1'0 - end - sync init - end - process $group_13 - assign \ALU_is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00010 - assign \ALU_is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00001 - assign \ALU_is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01000 - assign \ALU_is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00111 - assign \ALU_is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11110 - assign \ALU_is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \ALU_is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10010 - assign \ALU_is_32b 1'0 - end - sync init - end - process $group_14 - assign \ALU_sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00010 - assign \ALU_sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00001 - assign \ALU_sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01000 - assign \ALU_sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00111 - assign \ALU_sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11110 - assign \ALU_sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \ALU_sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10010 - assign \ALU_sgn 1'0 - end - sync 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\generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.dec_ALU.dec.ALU_dec31.ALU_dec_sub27" -module \ALU_dec_sub27 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" - wire width 32 input 0 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:308" - wire width 5 \opcode_switch - process $group_0 - assign \opcode_switch 5'00000 - assign \opcode_switch \opcode_in [10:6] - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.dec_ALU.dec.ALU_dec31.ALU_dec_sub15" -module \ALU_dec_sub15 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" - wire width 32 input 0 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:308" - wire width 5 \opcode_switch - process $group_0 - assign \opcode_switch 5'00000 - assign \opcode_switch \opcode_in [10:6] - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.dec_ALU.dec.ALU_dec31.ALU_dec_sub20" -module \ALU_dec_sub20 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" - wire width 32 input 0 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:308" - wire width 5 \opcode_switch - process $group_0 - assign \opcode_switch 5'00000 - assign \opcode_switch \opcode_in [10:6] - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.dec_ALU.dec.ALU_dec31.ALU_dec_sub21" -module \ALU_dec_sub21 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" - wire width 32 input 0 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:308" - wire width 5 \opcode_switch - process $group_0 - assign \opcode_switch 5'00000 - assign \opcode_switch \opcode_in [10:6] - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.dec_ALU.dec.ALU_dec31.ALU_dec_sub23" -module \ALU_dec_sub23 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" - wire width 32 input 0 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:308" - wire width 5 \opcode_switch - process $group_0 - assign \opcode_switch 5'00000 - assign \opcode_switch \opcode_in [10:6] - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.dec_ALU.dec.ALU_dec31.ALU_dec_sub16" -module \ALU_dec_sub16 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" - wire width 32 input 0 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:308" - wire width 5 \opcode_switch - process $group_0 - assign \opcode_switch 5'00000 - assign \opcode_switch \opcode_in [10:6] - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.dec_ALU.dec.ALU_dec31.ALU_dec_sub18" -module \ALU_dec_sub18 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" - wire width 32 input 0 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:308" - wire width 5 \opcode_switch - process $group_0 - assign \opcode_switch 5'00000 - assign \opcode_switch \opcode_in [10:6] - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.dec_ALU.dec.ALU_dec31.ALU_dec_sub8" -module \ALU_dec_sub8 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" - wire width 32 input 0 \opcode_in - attribute \enum_base_type "Function" - attribute \enum_value_00000000000 "NONE" - attribute \enum_value_00000000010 "ALU" - attribute \enum_value_00000000100 "LDST" - attribute \enum_value_00000001000 "SHIFT_ROT" - attribute \enum_value_00000010000 "LOGICAL" - attribute \enum_value_00000100000 "BRANCH" - attribute \enum_value_00001000000 "CR" - attribute \enum_value_00010000000 "TRAP" - attribute \enum_value_00100000000 "MUL" - attribute \enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 11 output 1 \ALU_function_unit - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 7 output 2 \ALU_internal_op - attribute \enum_base_type "In1Sel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "RA" - attribute \enum_value_010 "RA_OR_ZERO" - attribute \enum_value_011 "SPR" - attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 output 3 \ALU_in1_sel - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 4 output 4 \ALU_in2_sel - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 output 5 \ALU_cr_in - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 output 6 \ALU_cr_out - attribute \enum_base_type "LdstLen" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "is1B" - attribute \enum_value_0010 "is2B" - attribute \enum_value_0100 "is4B" - attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 4 output 7 \ALU_ldst_len - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 2 output 8 \ALU_rc_sel - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 2 output 9 \ALU_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 output 10 \ALU_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 output 11 \ALU_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 output 12 \ALU_cry_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 output 13 \ALU_is_32b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 output 14 \ALU_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:308" - wire width 5 \opcode_switch - process $group_0 - assign \opcode_switch 5'00000 - assign \opcode_switch \opcode_in [10:6] - sync init - end - process $group_1 - assign \ALU_function_unit 11'00000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00011 - assign \ALU_function_unit 11'00000000010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10011 - assign \ALU_function_unit 11'00000000010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00001 - assign \ALU_function_unit 11'00000000010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10001 - assign \ALU_function_unit 11'00000000010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \ALU_function_unit 11'00000000010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10000 - assign \ALU_function_unit 11'00000000010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00100 - assign \ALU_function_unit 11'00000000010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10100 - assign \ALU_function_unit 11'00000000010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00111 - assign \ALU_function_unit 11'00000000010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10111 - assign \ALU_function_unit 11'00000000010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00110 - assign \ALU_function_unit 11'00000000010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10110 - assign \ALU_function_unit 11'00000000010 - end - sync init - end - process $group_2 - assign \ALU_internal_op 7'0000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00011 - assign \ALU_internal_op 7'0000010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10011 - assign \ALU_internal_op 7'0000010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00001 - assign \ALU_internal_op 7'0000010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10001 - assign \ALU_internal_op 7'0000010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \ALU_internal_op 7'0000010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10000 - assign \ALU_internal_op 7'0000010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00100 - assign \ALU_internal_op 7'0000010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10100 - assign \ALU_internal_op 7'0000010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00111 - assign \ALU_internal_op 7'0000010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10111 - assign \ALU_internal_op 7'0000010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00110 - assign \ALU_internal_op 7'0000010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10110 - assign \ALU_internal_op 7'0000010 - end - sync init - end - process $group_3 - assign \ALU_in1_sel 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00011 - assign \ALU_in1_sel 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10011 - assign \ALU_in1_sel 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00001 - assign \ALU_in1_sel 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10001 - assign \ALU_in1_sel 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \ALU_in1_sel 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10000 - assign \ALU_in1_sel 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00100 - assign \ALU_in1_sel 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10100 - assign \ALU_in1_sel 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00111 - assign \ALU_in1_sel 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10111 - assign \ALU_in1_sel 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00110 - assign \ALU_in1_sel 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10110 - assign \ALU_in1_sel 3'001 - end - sync init - end - process $group_4 - assign \ALU_in2_sel 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00011 - assign \ALU_in2_sel 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10011 - assign \ALU_in2_sel 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00001 - assign \ALU_in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10001 - assign \ALU_in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \ALU_in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10000 - assign \ALU_in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00100 - assign \ALU_in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10100 - assign \ALU_in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00111 - assign \ALU_in2_sel 4'1001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10111 - assign \ALU_in2_sel 4'1001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00110 - assign \ALU_in2_sel 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10110 - assign \ALU_in2_sel 4'0000 - end - sync init - end - process $group_5 - assign \ALU_cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00011 - assign \ALU_cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10011 - assign \ALU_cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00001 - assign \ALU_cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10001 - assign \ALU_cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \ALU_cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10000 - assign \ALU_cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00100 - assign \ALU_cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10100 - assign \ALU_cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00111 - assign \ALU_cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10111 - assign \ALU_cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00110 - assign \ALU_cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10110 - assign \ALU_cr_in 3'000 - end - sync init - end - process $group_6 - assign \ALU_cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00011 - assign \ALU_cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10011 - assign \ALU_cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00001 - assign \ALU_cr_out 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10001 - assign \ALU_cr_out 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \ALU_cr_out 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10000 - assign \ALU_cr_out 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00100 - assign \ALU_cr_out 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10100 - assign \ALU_cr_out 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00111 - assign \ALU_cr_out 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10111 - assign \ALU_cr_out 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00110 - assign \ALU_cr_out 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10110 - assign \ALU_cr_out 3'001 - end - sync init - end - process $group_7 - assign \ALU_ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00011 - assign \ALU_ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10011 - assign \ALU_ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00001 - assign \ALU_ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10001 - assign \ALU_ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \ALU_ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10000 - assign \ALU_ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00100 - assign \ALU_ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10100 - assign \ALU_ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00111 - assign \ALU_ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10111 - assign \ALU_ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00110 - assign \ALU_ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10110 - assign \ALU_ldst_len 4'0000 - end - sync init - end - process $group_8 - assign \ALU_rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00011 - assign \ALU_rc_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10011 - assign \ALU_rc_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00001 - assign \ALU_rc_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10001 - assign \ALU_rc_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \ALU_rc_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10000 - assign \ALU_rc_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00100 - assign \ALU_rc_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10100 - assign \ALU_rc_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00111 - assign \ALU_rc_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10111 - assign \ALU_rc_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00110 - assign \ALU_rc_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10110 - assign \ALU_rc_sel 2'10 - end - sync init - end - process $group_9 - assign \ALU_cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00011 - assign \ALU_cry_in 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10011 - assign \ALU_cry_in 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00001 - assign \ALU_cry_in 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10001 - assign \ALU_cry_in 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \ALU_cry_in 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10000 - assign \ALU_cry_in 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00100 - assign \ALU_cry_in 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10100 - assign \ALU_cry_in 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00111 - assign \ALU_cry_in 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10111 - assign \ALU_cry_in 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00110 - assign \ALU_cry_in 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10110 - assign \ALU_cry_in 2'10 - end - sync init - end - process $group_10 - assign \ALU_inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00011 - assign \ALU_inv_a 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10011 - assign \ALU_inv_a 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00001 - assign \ALU_inv_a 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10001 - assign \ALU_inv_a 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \ALU_inv_a 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10000 - assign \ALU_inv_a 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00100 - assign \ALU_inv_a 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10100 - assign \ALU_inv_a 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00111 - assign \ALU_inv_a 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10111 - assign \ALU_inv_a 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00110 - assign \ALU_inv_a 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10110 - assign \ALU_inv_a 1'1 - end - sync init - end - process $group_11 - assign \ALU_inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00011 - assign \ALU_inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10011 - assign \ALU_inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00001 - assign \ALU_inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10001 - assign \ALU_inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \ALU_inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10000 - assign \ALU_inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00100 - assign \ALU_inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10100 - assign \ALU_inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00111 - assign \ALU_inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10111 - assign \ALU_inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00110 - assign \ALU_inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10110 - assign \ALU_inv_out 1'0 - end - sync init - end - process $group_12 - assign \ALU_cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00011 - assign \ALU_cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10011 - assign \ALU_cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00001 - assign \ALU_cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10001 - assign \ALU_cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \ALU_cry_out 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10000 - assign \ALU_cry_out 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00100 - assign \ALU_cry_out 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10100 - assign \ALU_cry_out 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00111 - assign \ALU_cry_out 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10111 - assign \ALU_cry_out 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00110 - assign \ALU_cry_out 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10110 - assign \ALU_cry_out 1'1 - end - sync init - end - process $group_13 - assign \ALU_is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00011 - assign \ALU_is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10011 - assign \ALU_is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00001 - assign \ALU_is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10001 - assign \ALU_is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \ALU_is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10000 - assign \ALU_is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00100 - assign \ALU_is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10100 - assign \ALU_is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00111 - assign \ALU_is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10111 - assign \ALU_is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00110 - assign \ALU_is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10110 - assign \ALU_is_32b 1'0 - end - sync init - end - process $group_14 - assign \ALU_sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00011 - assign \ALU_sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10011 - assign \ALU_sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00001 - assign \ALU_sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10001 - assign \ALU_sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \ALU_sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10000 - assign \ALU_sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00100 - assign \ALU_sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10100 - assign \ALU_sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00111 - assign \ALU_sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10111 - assign \ALU_sgn 1'0 - attribute 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\enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 7 \ALU_internal_op$25 - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute 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"OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 7 \ALU_internal_op$26 - process $group_21 - assign \ALU_internal_op 7'0000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:315" - switch \opc_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01010 - assign \ALU_internal_op \ALU_dec_sub10_ALU_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'11100 - assign \ALU_internal_op \ALU_internal_op$14 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'00000 - assign \ALU_internal_op \ALU_dec_sub0_ALU_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'11010 - assign \ALU_internal_op \ALU_dec_sub26_ALU_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10011 - assign \ALU_internal_op \ALU_internal_op$15 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10110 - assign \ALU_internal_op \ALU_dec_sub22_ALU_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01001 - assign \ALU_internal_op \ALU_internal_op$16 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01011 - assign \ALU_internal_op \ALU_internal_op$17 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'11011 - assign \ALU_internal_op \ALU_internal_op$18 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01111 - assign \ALU_internal_op \ALU_internal_op$19 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10100 - assign \ALU_internal_op \ALU_internal_op$20 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10101 - assign \ALU_internal_op \ALU_internal_op$21 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10111 - assign \ALU_internal_op \ALU_internal_op$22 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10000 - assign \ALU_internal_op \ALU_internal_op$23 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10010 - assign \ALU_internal_op \ALU_internal_op$24 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01000 - assign \ALU_internal_op \ALU_dec_sub8_ALU_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'11000 - assign \ALU_internal_op \ALU_internal_op$25 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'00100 - assign \ALU_internal_op \ALU_internal_op$26 - end - sync init - end - attribute \enum_base_type "In1Sel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "RA" - attribute \enum_value_010 "RA_OR_ZERO" - attribute \enum_value_011 "SPR" - attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \ALU_in1_sel$27 - attribute \enum_base_type "In1Sel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "RA" - attribute \enum_value_010 "RA_OR_ZERO" - attribute \enum_value_011 "SPR" - attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \ALU_in1_sel$28 - attribute \enum_base_type "In1Sel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "RA" - attribute \enum_value_010 "RA_OR_ZERO" - attribute \enum_value_011 "SPR" - attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \ALU_in1_sel$29 - attribute \enum_base_type "In1Sel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "RA" - attribute \enum_value_010 "RA_OR_ZERO" - attribute \enum_value_011 "SPR" - attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \ALU_in1_sel$30 - attribute \enum_base_type "In1Sel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "RA" - attribute \enum_value_010 "RA_OR_ZERO" - attribute \enum_value_011 "SPR" - attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \ALU_in1_sel$31 - attribute \enum_base_type "In1Sel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "RA" - attribute \enum_value_010 "RA_OR_ZERO" - attribute \enum_value_011 "SPR" - attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \ALU_in1_sel$32 - attribute \enum_base_type "In1Sel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "RA" - attribute \enum_value_010 "RA_OR_ZERO" - attribute \enum_value_011 "SPR" - attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \ALU_in1_sel$33 - attribute \enum_base_type "In1Sel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "RA" - attribute \enum_value_010 "RA_OR_ZERO" - attribute \enum_value_011 "SPR" - attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \ALU_in1_sel$34 - attribute \enum_base_type "In1Sel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "RA" - attribute \enum_value_010 "RA_OR_ZERO" - attribute \enum_value_011 "SPR" - attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \ALU_in1_sel$35 - attribute \enum_base_type "In1Sel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "RA" - attribute \enum_value_010 "RA_OR_ZERO" - attribute \enum_value_011 "SPR" - attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \ALU_in1_sel$36 - attribute \enum_base_type "In1Sel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "RA" - attribute \enum_value_010 "RA_OR_ZERO" - attribute \enum_value_011 "SPR" - attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \ALU_in1_sel$37 - attribute \enum_base_type "In1Sel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "RA" - attribute \enum_value_010 "RA_OR_ZERO" - attribute \enum_value_011 "SPR" - attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \ALU_in1_sel$38 - attribute \enum_base_type "In1Sel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "RA" - attribute \enum_value_010 "RA_OR_ZERO" - attribute \enum_value_011 "SPR" - attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \ALU_in1_sel$39 - process $group_22 - assign \ALU_in1_sel 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:315" - switch \opc_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01010 - assign \ALU_in1_sel \ALU_dec_sub10_ALU_in1_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'11100 - assign \ALU_in1_sel \ALU_in1_sel$27 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'00000 - assign \ALU_in1_sel \ALU_dec_sub0_ALU_in1_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'11010 - assign \ALU_in1_sel \ALU_dec_sub26_ALU_in1_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10011 - assign \ALU_in1_sel \ALU_in1_sel$28 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10110 - assign \ALU_in1_sel \ALU_dec_sub22_ALU_in1_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01001 - assign \ALU_in1_sel \ALU_in1_sel$29 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01011 - assign \ALU_in1_sel \ALU_in1_sel$30 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'11011 - assign \ALU_in1_sel \ALU_in1_sel$31 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01111 - assign \ALU_in1_sel \ALU_in1_sel$32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10100 - assign \ALU_in1_sel \ALU_in1_sel$33 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10101 - assign \ALU_in1_sel \ALU_in1_sel$34 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10111 - assign \ALU_in1_sel \ALU_in1_sel$35 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10000 - assign \ALU_in1_sel \ALU_in1_sel$36 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10010 - assign \ALU_in1_sel \ALU_in1_sel$37 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01000 - assign \ALU_in1_sel \ALU_dec_sub8_ALU_in1_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'11000 - assign \ALU_in1_sel \ALU_in1_sel$38 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'00100 - assign \ALU_in1_sel \ALU_in1_sel$39 - end - sync init - end - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 4 \ALU_in2_sel$40 - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 4 \ALU_in2_sel$41 - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 4 \ALU_in2_sel$42 - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 4 \ALU_in2_sel$43 - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 4 \ALU_in2_sel$44 - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 4 \ALU_in2_sel$45 - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 4 \ALU_in2_sel$46 - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 4 \ALU_in2_sel$47 - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 4 \ALU_in2_sel$48 - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 4 \ALU_in2_sel$49 - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 4 \ALU_in2_sel$50 - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 4 \ALU_in2_sel$51 - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 4 \ALU_in2_sel$52 - process $group_23 - assign \ALU_in2_sel 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:315" - switch \opc_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01010 - assign \ALU_in2_sel \ALU_dec_sub10_ALU_in2_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'11100 - assign \ALU_in2_sel \ALU_in2_sel$40 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'00000 - assign \ALU_in2_sel \ALU_dec_sub0_ALU_in2_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'11010 - assign \ALU_in2_sel \ALU_dec_sub26_ALU_in2_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10011 - assign \ALU_in2_sel \ALU_in2_sel$41 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10110 - assign \ALU_in2_sel \ALU_dec_sub22_ALU_in2_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01001 - assign \ALU_in2_sel \ALU_in2_sel$42 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01011 - assign \ALU_in2_sel \ALU_in2_sel$43 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'11011 - assign \ALU_in2_sel \ALU_in2_sel$44 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01111 - assign \ALU_in2_sel \ALU_in2_sel$45 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10100 - assign \ALU_in2_sel \ALU_in2_sel$46 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10101 - assign \ALU_in2_sel \ALU_in2_sel$47 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10111 - assign \ALU_in2_sel \ALU_in2_sel$48 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10000 - assign \ALU_in2_sel \ALU_in2_sel$49 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10010 - assign \ALU_in2_sel \ALU_in2_sel$50 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01000 - assign \ALU_in2_sel \ALU_dec_sub8_ALU_in2_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'11000 - assign \ALU_in2_sel \ALU_in2_sel$51 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'00100 - assign \ALU_in2_sel \ALU_in2_sel$52 - end - sync init - end - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \ALU_cr_in$53 - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \ALU_cr_in$54 - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \ALU_cr_in$55 - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \ALU_cr_in$56 - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \ALU_cr_in$57 - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \ALU_cr_in$58 - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \ALU_cr_in$59 - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \ALU_cr_in$60 - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \ALU_cr_in$61 - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \ALU_cr_in$62 - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \ALU_cr_in$63 - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \ALU_cr_in$64 - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \ALU_cr_in$65 - process $group_24 - assign \ALU_cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:315" - switch \opc_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01010 - assign \ALU_cr_in \ALU_dec_sub10_ALU_cr_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'11100 - assign \ALU_cr_in \ALU_cr_in$53 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'00000 - assign \ALU_cr_in \ALU_dec_sub0_ALU_cr_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'11010 - assign \ALU_cr_in \ALU_dec_sub26_ALU_cr_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10011 - assign \ALU_cr_in \ALU_cr_in$54 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10110 - assign \ALU_cr_in \ALU_dec_sub22_ALU_cr_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01001 - assign \ALU_cr_in \ALU_cr_in$55 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01011 - assign \ALU_cr_in \ALU_cr_in$56 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'11011 - assign \ALU_cr_in \ALU_cr_in$57 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01111 - assign \ALU_cr_in \ALU_cr_in$58 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10100 - assign \ALU_cr_in \ALU_cr_in$59 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10101 - assign \ALU_cr_in \ALU_cr_in$60 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10111 - assign \ALU_cr_in \ALU_cr_in$61 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10000 - assign \ALU_cr_in \ALU_cr_in$62 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10010 - assign \ALU_cr_in \ALU_cr_in$63 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01000 - assign \ALU_cr_in \ALU_dec_sub8_ALU_cr_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'11000 - assign \ALU_cr_in \ALU_cr_in$64 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'00100 - assign \ALU_cr_in \ALU_cr_in$65 - end - sync init - end - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \ALU_cr_out$66 - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \ALU_cr_out$67 - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \ALU_cr_out$68 - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \ALU_cr_out$69 - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \ALU_cr_out$70 - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \ALU_cr_out$71 - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \ALU_cr_out$72 - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \ALU_cr_out$73 - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \ALU_cr_out$74 - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \ALU_cr_out$75 - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \ALU_cr_out$76 - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \ALU_cr_out$77 - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \ALU_cr_out$78 - process $group_25 - assign \ALU_cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:315" - switch \opc_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01010 - assign \ALU_cr_out \ALU_dec_sub10_ALU_cr_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'11100 - assign \ALU_cr_out \ALU_cr_out$66 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'00000 - assign \ALU_cr_out \ALU_dec_sub0_ALU_cr_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'11010 - assign \ALU_cr_out \ALU_dec_sub26_ALU_cr_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10011 - assign \ALU_cr_out \ALU_cr_out$67 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10110 - assign \ALU_cr_out \ALU_dec_sub22_ALU_cr_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01001 - assign \ALU_cr_out \ALU_cr_out$68 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01011 - assign \ALU_cr_out \ALU_cr_out$69 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'11011 - assign \ALU_cr_out \ALU_cr_out$70 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01111 - assign \ALU_cr_out \ALU_cr_out$71 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10100 - assign \ALU_cr_out \ALU_cr_out$72 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10101 - assign \ALU_cr_out \ALU_cr_out$73 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10111 - assign \ALU_cr_out \ALU_cr_out$74 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10000 - assign \ALU_cr_out \ALU_cr_out$75 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10010 - assign \ALU_cr_out \ALU_cr_out$76 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01000 - assign \ALU_cr_out \ALU_dec_sub8_ALU_cr_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'11000 - assign \ALU_cr_out \ALU_cr_out$77 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'00100 - assign \ALU_cr_out \ALU_cr_out$78 - end - sync init - end - attribute \enum_base_type "LdstLen" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "is1B" - attribute \enum_value_0010 "is2B" - attribute \enum_value_0100 "is4B" - attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 4 \ALU_ldst_len$79 - attribute \enum_base_type "LdstLen" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "is1B" - attribute \enum_value_0010 "is2B" - attribute \enum_value_0100 "is4B" - attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 4 \ALU_ldst_len$80 - attribute \enum_base_type "LdstLen" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "is1B" - attribute \enum_value_0010 "is2B" - attribute \enum_value_0100 "is4B" - attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 4 \ALU_ldst_len$81 - attribute \enum_base_type "LdstLen" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "is1B" - attribute \enum_value_0010 "is2B" - attribute \enum_value_0100 "is4B" - attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 4 \ALU_ldst_len$82 - attribute \enum_base_type "LdstLen" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "is1B" - attribute \enum_value_0010 "is2B" - attribute \enum_value_0100 "is4B" - attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 4 \ALU_ldst_len$83 - attribute \enum_base_type "LdstLen" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "is1B" - attribute \enum_value_0010 "is2B" - attribute \enum_value_0100 "is4B" - attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 4 \ALU_ldst_len$84 - attribute \enum_base_type "LdstLen" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "is1B" - attribute \enum_value_0010 "is2B" - attribute \enum_value_0100 "is4B" - attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 4 \ALU_ldst_len$85 - attribute \enum_base_type "LdstLen" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "is1B" - attribute \enum_value_0010 "is2B" - attribute \enum_value_0100 "is4B" - attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 4 \ALU_ldst_len$86 - attribute \enum_base_type "LdstLen" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "is1B" - attribute \enum_value_0010 "is2B" - attribute \enum_value_0100 "is4B" - attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 4 \ALU_ldst_len$87 - attribute \enum_base_type "LdstLen" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "is1B" - attribute \enum_value_0010 "is2B" - attribute \enum_value_0100 "is4B" - attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 4 \ALU_ldst_len$88 - attribute \enum_base_type "LdstLen" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "is1B" - attribute \enum_value_0010 "is2B" - attribute \enum_value_0100 "is4B" - attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 4 \ALU_ldst_len$89 - attribute \enum_base_type "LdstLen" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "is1B" - attribute \enum_value_0010 "is2B" - attribute \enum_value_0100 "is4B" - attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 4 \ALU_ldst_len$90 - attribute \enum_base_type "LdstLen" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "is1B" - attribute \enum_value_0010 "is2B" - attribute \enum_value_0100 "is4B" - attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 4 \ALU_ldst_len$91 - process $group_26 - assign \ALU_ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:315" - switch \opc_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01010 - assign \ALU_ldst_len \ALU_dec_sub10_ALU_ldst_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'11100 - assign \ALU_ldst_len \ALU_ldst_len$79 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'00000 - assign \ALU_ldst_len \ALU_dec_sub0_ALU_ldst_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'11010 - assign \ALU_ldst_len \ALU_dec_sub26_ALU_ldst_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10011 - assign \ALU_ldst_len \ALU_ldst_len$80 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10110 - assign \ALU_ldst_len \ALU_dec_sub22_ALU_ldst_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01001 - assign \ALU_ldst_len \ALU_ldst_len$81 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01011 - assign \ALU_ldst_len \ALU_ldst_len$82 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'11011 - assign \ALU_ldst_len \ALU_ldst_len$83 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01111 - assign \ALU_ldst_len \ALU_ldst_len$84 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10100 - assign \ALU_ldst_len \ALU_ldst_len$85 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10101 - assign \ALU_ldst_len \ALU_ldst_len$86 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10111 - assign \ALU_ldst_len \ALU_ldst_len$87 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10000 - assign \ALU_ldst_len \ALU_ldst_len$88 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10010 - assign \ALU_ldst_len \ALU_ldst_len$89 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01000 - assign \ALU_ldst_len \ALU_dec_sub8_ALU_ldst_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'11000 - assign \ALU_ldst_len \ALU_ldst_len$90 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'00100 - assign \ALU_ldst_len \ALU_ldst_len$91 - end - sync init - end - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 2 \ALU_rc_sel$92 - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 2 \ALU_rc_sel$93 - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 2 \ALU_rc_sel$94 - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 2 \ALU_rc_sel$95 - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 2 \ALU_rc_sel$96 - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 2 \ALU_rc_sel$97 - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 2 \ALU_rc_sel$98 - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 2 \ALU_rc_sel$99 - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 2 \ALU_rc_sel$100 - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 2 \ALU_rc_sel$101 - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 2 \ALU_rc_sel$102 - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 2 \ALU_rc_sel$103 - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 2 \ALU_rc_sel$104 - process $group_27 - assign \ALU_rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:315" - switch \opc_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01010 - assign \ALU_rc_sel \ALU_dec_sub10_ALU_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'11100 - assign \ALU_rc_sel \ALU_rc_sel$92 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'00000 - assign \ALU_rc_sel \ALU_dec_sub0_ALU_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'11010 - assign \ALU_rc_sel \ALU_dec_sub26_ALU_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10011 - assign \ALU_rc_sel \ALU_rc_sel$93 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10110 - assign \ALU_rc_sel \ALU_dec_sub22_ALU_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01001 - assign \ALU_rc_sel \ALU_rc_sel$94 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01011 - assign \ALU_rc_sel \ALU_rc_sel$95 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'11011 - assign \ALU_rc_sel \ALU_rc_sel$96 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01111 - assign \ALU_rc_sel \ALU_rc_sel$97 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10100 - assign \ALU_rc_sel \ALU_rc_sel$98 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10101 - assign \ALU_rc_sel \ALU_rc_sel$99 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10111 - assign \ALU_rc_sel \ALU_rc_sel$100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10000 - assign \ALU_rc_sel \ALU_rc_sel$101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10010 - assign \ALU_rc_sel \ALU_rc_sel$102 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01000 - assign \ALU_rc_sel \ALU_dec_sub8_ALU_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'11000 - assign \ALU_rc_sel \ALU_rc_sel$103 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'00100 - assign \ALU_rc_sel \ALU_rc_sel$104 - end - sync init - end - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 2 \ALU_cry_in$105 - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 2 \ALU_cry_in$106 - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 2 \ALU_cry_in$107 - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 2 \ALU_cry_in$108 - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 2 \ALU_cry_in$109 - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 2 \ALU_cry_in$110 - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 2 \ALU_cry_in$111 - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 2 \ALU_cry_in$112 - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 2 \ALU_cry_in$113 - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 2 \ALU_cry_in$114 - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 2 \ALU_cry_in$115 - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 2 \ALU_cry_in$116 - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 2 \ALU_cry_in$117 - process $group_28 - assign \ALU_cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:315" - switch \opc_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01010 - assign \ALU_cry_in \ALU_dec_sub10_ALU_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'11100 - assign \ALU_cry_in \ALU_cry_in$105 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'00000 - assign \ALU_cry_in \ALU_dec_sub0_ALU_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'11010 - assign \ALU_cry_in \ALU_dec_sub26_ALU_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10011 - assign \ALU_cry_in \ALU_cry_in$106 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10110 - assign \ALU_cry_in \ALU_dec_sub22_ALU_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01001 - assign \ALU_cry_in \ALU_cry_in$107 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01011 - assign \ALU_cry_in \ALU_cry_in$108 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'11011 - assign \ALU_cry_in \ALU_cry_in$109 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01111 - assign \ALU_cry_in \ALU_cry_in$110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10100 - assign \ALU_cry_in \ALU_cry_in$111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10101 - assign \ALU_cry_in \ALU_cry_in$112 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10111 - assign \ALU_cry_in \ALU_cry_in$113 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10000 - assign \ALU_cry_in \ALU_cry_in$114 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10010 - assign \ALU_cry_in \ALU_cry_in$115 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01000 - assign \ALU_cry_in \ALU_dec_sub8_ALU_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'11000 - assign \ALU_cry_in \ALU_cry_in$116 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'00100 - assign \ALU_cry_in \ALU_cry_in$117 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \ALU_inv_a$118 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \ALU_inv_a$119 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \ALU_inv_a$120 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \ALU_inv_a$121 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \ALU_inv_a$122 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \ALU_inv_a$123 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \ALU_inv_a$124 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \ALU_inv_a$125 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \ALU_inv_a$126 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \ALU_inv_a$127 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \ALU_inv_a$128 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \ALU_inv_a$129 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \ALU_inv_a$130 - process $group_29 - assign \ALU_inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:315" - switch \opc_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01010 - assign \ALU_inv_a \ALU_dec_sub10_ALU_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'11100 - assign \ALU_inv_a \ALU_inv_a$118 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'00000 - assign \ALU_inv_a \ALU_dec_sub0_ALU_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'11010 - assign \ALU_inv_a \ALU_dec_sub26_ALU_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10011 - assign \ALU_inv_a \ALU_inv_a$119 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10110 - assign \ALU_inv_a \ALU_dec_sub22_ALU_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01001 - assign \ALU_inv_a \ALU_inv_a$120 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01011 - assign \ALU_inv_a \ALU_inv_a$121 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'11011 - assign \ALU_inv_a \ALU_inv_a$122 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01111 - assign \ALU_inv_a \ALU_inv_a$123 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10100 - assign \ALU_inv_a \ALU_inv_a$124 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10101 - assign \ALU_inv_a \ALU_inv_a$125 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10111 - assign \ALU_inv_a \ALU_inv_a$126 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10000 - assign \ALU_inv_a \ALU_inv_a$127 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10010 - assign \ALU_inv_a \ALU_inv_a$128 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01000 - assign \ALU_inv_a \ALU_dec_sub8_ALU_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'11000 - assign \ALU_inv_a \ALU_inv_a$129 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'00100 - assign \ALU_inv_a \ALU_inv_a$130 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \ALU_inv_out$131 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \ALU_inv_out$132 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \ALU_inv_out$133 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \ALU_inv_out$134 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \ALU_inv_out$135 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \ALU_inv_out$136 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \ALU_inv_out$137 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \ALU_inv_out$138 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \ALU_inv_out$139 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \ALU_inv_out$140 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \ALU_inv_out$141 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \ALU_inv_out$142 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \ALU_inv_out$143 - process $group_30 - assign \ALU_inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:315" - switch \opc_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01010 - assign \ALU_inv_out \ALU_dec_sub10_ALU_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'11100 - assign \ALU_inv_out \ALU_inv_out$131 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'00000 - assign \ALU_inv_out \ALU_dec_sub0_ALU_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'11010 - assign \ALU_inv_out \ALU_dec_sub26_ALU_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10011 - assign \ALU_inv_out \ALU_inv_out$132 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10110 - assign \ALU_inv_out \ALU_dec_sub22_ALU_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01001 - assign \ALU_inv_out \ALU_inv_out$133 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01011 - assign \ALU_inv_out \ALU_inv_out$134 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'11011 - assign \ALU_inv_out \ALU_inv_out$135 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01111 - assign \ALU_inv_out \ALU_inv_out$136 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10100 - assign \ALU_inv_out \ALU_inv_out$137 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10101 - assign \ALU_inv_out \ALU_inv_out$138 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10111 - assign \ALU_inv_out \ALU_inv_out$139 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10000 - assign \ALU_inv_out \ALU_inv_out$140 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10010 - assign \ALU_inv_out \ALU_inv_out$141 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01000 - assign \ALU_inv_out \ALU_dec_sub8_ALU_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'11000 - assign \ALU_inv_out \ALU_inv_out$142 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'00100 - assign \ALU_inv_out \ALU_inv_out$143 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \ALU_cry_out$144 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \ALU_cry_out$145 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \ALU_cry_out$146 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \ALU_cry_out$147 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \ALU_cry_out$148 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \ALU_cry_out$149 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \ALU_cry_out$150 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \ALU_cry_out$151 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \ALU_cry_out$152 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \ALU_cry_out$153 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \ALU_cry_out$154 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \ALU_cry_out$155 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \ALU_cry_out$156 - process $group_31 - assign \ALU_cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:315" - switch \opc_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01010 - assign \ALU_cry_out \ALU_dec_sub10_ALU_cry_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'11100 - assign \ALU_cry_out \ALU_cry_out$144 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'00000 - assign \ALU_cry_out \ALU_dec_sub0_ALU_cry_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'11010 - assign \ALU_cry_out \ALU_dec_sub26_ALU_cry_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10011 - assign \ALU_cry_out \ALU_cry_out$145 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10110 - assign \ALU_cry_out \ALU_dec_sub22_ALU_cry_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01001 - assign \ALU_cry_out \ALU_cry_out$146 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01011 - assign \ALU_cry_out \ALU_cry_out$147 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'11011 - assign \ALU_cry_out \ALU_cry_out$148 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01111 - assign \ALU_cry_out \ALU_cry_out$149 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10100 - assign \ALU_cry_out \ALU_cry_out$150 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10101 - assign \ALU_cry_out \ALU_cry_out$151 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10111 - assign \ALU_cry_out \ALU_cry_out$152 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10000 - assign \ALU_cry_out \ALU_cry_out$153 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10010 - assign \ALU_cry_out \ALU_cry_out$154 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01000 - assign \ALU_cry_out \ALU_dec_sub8_ALU_cry_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'11000 - assign \ALU_cry_out \ALU_cry_out$155 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'00100 - assign \ALU_cry_out \ALU_cry_out$156 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \ALU_is_32b$157 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \ALU_is_32b$158 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \ALU_is_32b$159 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \ALU_is_32b$160 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \ALU_is_32b$161 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \ALU_is_32b$162 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \ALU_is_32b$163 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \ALU_is_32b$164 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \ALU_is_32b$165 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \ALU_is_32b$166 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \ALU_is_32b$167 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \ALU_is_32b$168 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \ALU_is_32b$169 - process $group_32 - assign \ALU_is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:315" - switch \opc_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01010 - assign \ALU_is_32b \ALU_dec_sub10_ALU_is_32b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'11100 - assign \ALU_is_32b \ALU_is_32b$157 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'00000 - assign \ALU_is_32b \ALU_dec_sub0_ALU_is_32b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'11010 - assign \ALU_is_32b \ALU_dec_sub26_ALU_is_32b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10011 - assign \ALU_is_32b \ALU_is_32b$158 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10110 - assign \ALU_is_32b \ALU_dec_sub22_ALU_is_32b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01001 - assign \ALU_is_32b \ALU_is_32b$159 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01011 - assign \ALU_is_32b \ALU_is_32b$160 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'11011 - assign \ALU_is_32b \ALU_is_32b$161 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01111 - assign \ALU_is_32b \ALU_is_32b$162 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10100 - assign \ALU_is_32b \ALU_is_32b$163 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10101 - assign \ALU_is_32b \ALU_is_32b$164 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10111 - assign \ALU_is_32b \ALU_is_32b$165 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10000 - assign \ALU_is_32b \ALU_is_32b$166 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10010 - assign \ALU_is_32b \ALU_is_32b$167 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01000 - assign \ALU_is_32b \ALU_dec_sub8_ALU_is_32b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'11000 - assign \ALU_is_32b \ALU_is_32b$168 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'00100 - assign \ALU_is_32b \ALU_is_32b$169 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \ALU_sgn$170 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \ALU_sgn$171 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \ALU_sgn$172 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \ALU_sgn$173 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \ALU_sgn$174 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \ALU_sgn$175 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \ALU_sgn$176 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \ALU_sgn$177 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \ALU_sgn$178 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \ALU_sgn$179 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \ALU_sgn$180 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \ALU_sgn$181 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \ALU_sgn$182 - process $group_33 - assign \ALU_sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:315" - switch \opc_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01010 - assign \ALU_sgn \ALU_dec_sub10_ALU_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'11100 - assign \ALU_sgn \ALU_sgn$170 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'00000 - assign \ALU_sgn \ALU_dec_sub0_ALU_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'11010 - assign \ALU_sgn \ALU_dec_sub26_ALU_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10011 - assign \ALU_sgn \ALU_sgn$171 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10110 - assign \ALU_sgn \ALU_dec_sub22_ALU_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01001 - assign \ALU_sgn \ALU_sgn$172 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01011 - assign \ALU_sgn \ALU_sgn$173 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'11011 - assign \ALU_sgn \ALU_sgn$174 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01111 - assign \ALU_sgn \ALU_sgn$175 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10100 - assign \ALU_sgn \ALU_sgn$176 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10101 - assign \ALU_sgn \ALU_sgn$177 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10111 - assign \ALU_sgn \ALU_sgn$178 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10000 - assign \ALU_sgn \ALU_sgn$179 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10010 - assign \ALU_sgn \ALU_sgn$180 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01000 - assign \ALU_sgn \ALU_dec_sub8_ALU_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'11000 - assign \ALU_sgn \ALU_sgn$181 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'00100 - assign \ALU_sgn \ALU_sgn$182 - end - sync init - end - connect \ALU_function_unit$1 11'00000000000 - connect \ALU_function_unit$2 11'00000000000 - connect \ALU_function_unit$3 11'00000000000 - connect \ALU_function_unit$4 11'00000000000 - connect \ALU_function_unit$5 11'00000000000 - connect \ALU_function_unit$6 11'00000000000 - connect \ALU_function_unit$7 11'00000000000 - connect \ALU_function_unit$8 11'00000000000 - connect \ALU_function_unit$9 11'00000000000 - connect \ALU_function_unit$10 11'00000000000 - connect \ALU_function_unit$11 11'00000000000 - connect \ALU_function_unit$12 11'00000000000 - connect \ALU_function_unit$13 11'00000000000 - connect \ALU_internal_op$14 7'0000000 - connect \ALU_internal_op$15 7'0000000 - connect \ALU_internal_op$16 7'0000000 - connect \ALU_internal_op$17 7'0000000 - connect \ALU_internal_op$18 7'0000000 - connect \ALU_internal_op$19 7'0000000 - connect \ALU_internal_op$20 7'0000000 - connect \ALU_internal_op$21 7'0000000 - connect \ALU_internal_op$22 7'0000000 - connect \ALU_internal_op$23 7'0000000 - connect \ALU_internal_op$24 7'0000000 - connect \ALU_internal_op$25 7'0000000 - connect \ALU_internal_op$26 7'0000000 - connect \ALU_in1_sel$27 3'000 - connect \ALU_in1_sel$28 3'000 - connect \ALU_in1_sel$29 3'000 - connect \ALU_in1_sel$30 3'000 - connect \ALU_in1_sel$31 3'000 - connect \ALU_in1_sel$32 3'000 - connect \ALU_in1_sel$33 3'000 - connect \ALU_in1_sel$34 3'000 - connect \ALU_in1_sel$35 3'000 - connect \ALU_in1_sel$36 3'000 - connect \ALU_in1_sel$37 3'000 - connect \ALU_in1_sel$38 3'000 - connect \ALU_in1_sel$39 3'000 - connect \ALU_in2_sel$40 4'0000 - connect \ALU_in2_sel$41 4'0000 - connect \ALU_in2_sel$42 4'0000 - connect \ALU_in2_sel$43 4'0000 - connect \ALU_in2_sel$44 4'0000 - connect \ALU_in2_sel$45 4'0000 - connect \ALU_in2_sel$46 4'0000 - connect \ALU_in2_sel$47 4'0000 - connect \ALU_in2_sel$48 4'0000 - connect \ALU_in2_sel$49 4'0000 - connect \ALU_in2_sel$50 4'0000 - connect \ALU_in2_sel$51 4'0000 - connect \ALU_in2_sel$52 4'0000 - connect \ALU_cr_in$53 3'000 - connect \ALU_cr_in$54 3'000 - connect \ALU_cr_in$55 3'000 - connect \ALU_cr_in$56 3'000 - connect \ALU_cr_in$57 3'000 - connect \ALU_cr_in$58 3'000 - connect \ALU_cr_in$59 3'000 - connect \ALU_cr_in$60 3'000 - connect \ALU_cr_in$61 3'000 - connect \ALU_cr_in$62 3'000 - connect \ALU_cr_in$63 3'000 - connect \ALU_cr_in$64 3'000 - connect \ALU_cr_in$65 3'000 - connect \ALU_cr_out$66 3'000 - connect \ALU_cr_out$67 3'000 - connect \ALU_cr_out$68 3'000 - connect \ALU_cr_out$69 3'000 - connect \ALU_cr_out$70 3'000 - connect \ALU_cr_out$71 3'000 - connect \ALU_cr_out$72 3'000 - connect \ALU_cr_out$73 3'000 - connect \ALU_cr_out$74 3'000 - connect \ALU_cr_out$75 3'000 - connect \ALU_cr_out$76 3'000 - connect \ALU_cr_out$77 3'000 - connect \ALU_cr_out$78 3'000 - connect \ALU_ldst_len$79 4'0000 - connect \ALU_ldst_len$80 4'0000 - connect \ALU_ldst_len$81 4'0000 - connect \ALU_ldst_len$82 4'0000 - connect \ALU_ldst_len$83 4'0000 - connect \ALU_ldst_len$84 4'0000 - connect \ALU_ldst_len$85 4'0000 - connect \ALU_ldst_len$86 4'0000 - connect \ALU_ldst_len$87 4'0000 - connect \ALU_ldst_len$88 4'0000 - connect \ALU_ldst_len$89 4'0000 - connect \ALU_ldst_len$90 4'0000 - connect \ALU_ldst_len$91 4'0000 - connect \ALU_rc_sel$92 2'00 - connect \ALU_rc_sel$93 2'00 - connect \ALU_rc_sel$94 2'00 - connect \ALU_rc_sel$95 2'00 - connect \ALU_rc_sel$96 2'00 - connect \ALU_rc_sel$97 2'00 - connect \ALU_rc_sel$98 2'00 - connect \ALU_rc_sel$99 2'00 - connect \ALU_rc_sel$100 2'00 - connect \ALU_rc_sel$101 2'00 - connect \ALU_rc_sel$102 2'00 - connect \ALU_rc_sel$103 2'00 - connect \ALU_rc_sel$104 2'00 - connect \ALU_cry_in$105 2'00 - connect \ALU_cry_in$106 2'00 - connect \ALU_cry_in$107 2'00 - connect \ALU_cry_in$108 2'00 - connect \ALU_cry_in$109 2'00 - connect \ALU_cry_in$110 2'00 - connect \ALU_cry_in$111 2'00 - connect \ALU_cry_in$112 2'00 - connect \ALU_cry_in$113 2'00 - connect \ALU_cry_in$114 2'00 - connect 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"CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 4 \ALU_dec31_ALU_in2_sel - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \ALU_dec31_ALU_cr_in - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \ALU_dec31_ALU_cr_out - attribute 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attribute \enum_value_00000001000 "SHIFT_ROT" - attribute \enum_value_00000010000 "LOGICAL" - attribute \enum_value_00000100000 "BRANCH" - attribute \enum_value_00001000000 "CR" - attribute \enum_value_00010000000 "TRAP" - attribute \enum_value_00100000000 "MUL" - attribute \enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 11 \ALU_function_unit$3 - process $group_6 - assign \ALU_function_unit 11'00000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'010011 - assign \ALU_function_unit \ALU_dec19_ALU_function_unit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'011110 - assign \ALU_function_unit \ALU_function_unit$1 - attribute \src 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attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 7 \ALU_internal_op$6 - process $group_7 - assign \ALU_internal_op 7'0000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'010011 - assign \ALU_internal_op \ALU_dec19_ALU_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'011110 - assign \ALU_internal_op \ALU_internal_op$4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'011111 - assign \ALU_internal_op \ALU_dec31_ALU_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'111010 - assign \ALU_internal_op \ALU_internal_op$5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'111110 - assign \ALU_internal_op \ALU_internal_op$6 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'001100 - assign \ALU_internal_op 7'0000010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'001101 - assign \ALU_internal_op 7'0000010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'001110 - assign \ALU_internal_op 7'0000010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'001111 - assign \ALU_internal_op 7'0000010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'001011 - assign \ALU_internal_op 7'0001010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'001010 - assign \ALU_internal_op 7'0001010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'001000 - assign \ALU_internal_op 7'0000010 - end - sync init - end - attribute \enum_base_type "In1Sel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "RA" - attribute \enum_value_010 "RA_OR_ZERO" - attribute \enum_value_011 "SPR" - attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \ALU_in1_sel$7 - attribute \enum_base_type "In1Sel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "RA" - attribute \enum_value_010 "RA_OR_ZERO" - attribute \enum_value_011 "SPR" - attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \ALU_in1_sel$8 - attribute \enum_base_type "In1Sel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "RA" - attribute \enum_value_010 "RA_OR_ZERO" - attribute \enum_value_011 "SPR" - attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \ALU_in1_sel$9 - process $group_8 - assign \ALU_in1_sel 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'010011 - assign \ALU_in1_sel \ALU_dec19_ALU_in1_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'011110 - assign \ALU_in1_sel \ALU_in1_sel$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'011111 - assign \ALU_in1_sel \ALU_dec31_ALU_in1_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'111010 - assign \ALU_in1_sel \ALU_in1_sel$8 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'111110 - assign \ALU_in1_sel \ALU_in1_sel$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'001100 - assign \ALU_in1_sel 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'001101 - assign \ALU_in1_sel 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'001110 - assign \ALU_in1_sel 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'001111 - assign \ALU_in1_sel 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'001011 - assign \ALU_in1_sel 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'001010 - assign \ALU_in1_sel 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'001000 - assign \ALU_in1_sel 3'001 - end - sync init - end - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 4 \ALU_in2_sel$10 - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 4 \ALU_in2_sel$11 - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 4 \ALU_in2_sel$12 - process $group_9 - assign \ALU_in2_sel 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'010011 - assign \ALU_in2_sel \ALU_dec19_ALU_in2_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'011110 - assign \ALU_in2_sel \ALU_in2_sel$10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'011111 - assign \ALU_in2_sel \ALU_dec31_ALU_in2_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'111010 - assign \ALU_in2_sel \ALU_in2_sel$11 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'111110 - assign \ALU_in2_sel \ALU_in2_sel$12 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'001100 - assign \ALU_in2_sel 4'0011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'001101 - assign \ALU_in2_sel 4'0011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'001110 - assign \ALU_in2_sel 4'0011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'001111 - assign \ALU_in2_sel 4'0101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'001011 - assign \ALU_in2_sel 4'0011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'001010 - assign \ALU_in2_sel 4'0010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'001000 - assign \ALU_in2_sel 4'0011 - end - sync init - end - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \ALU_cr_in$13 - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \ALU_cr_in$14 - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \ALU_cr_in$15 - process $group_10 - assign \ALU_cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'010011 - assign \ALU_cr_in \ALU_dec19_ALU_cr_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'011110 - assign \ALU_cr_in \ALU_cr_in$13 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'011111 - assign \ALU_cr_in \ALU_dec31_ALU_cr_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'111010 - assign \ALU_cr_in \ALU_cr_in$14 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'111110 - assign \ALU_cr_in \ALU_cr_in$15 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'001100 - assign \ALU_cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'001101 - assign \ALU_cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'001110 - assign \ALU_cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'001111 - assign \ALU_cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'001011 - assign \ALU_cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'001010 - assign \ALU_cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'001000 - assign \ALU_cr_in 3'000 - end - sync init - end - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \ALU_cr_out$16 - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \ALU_cr_out$17 - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \ALU_cr_out$18 - process $group_11 - assign \ALU_cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'010011 - assign \ALU_cr_out \ALU_dec19_ALU_cr_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'011110 - assign \ALU_cr_out \ALU_cr_out$16 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'011111 - assign \ALU_cr_out \ALU_dec31_ALU_cr_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'111010 - assign \ALU_cr_out \ALU_cr_out$17 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'111110 - assign \ALU_cr_out \ALU_cr_out$18 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'001100 - assign \ALU_cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'001101 - assign \ALU_cr_out 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'001110 - assign \ALU_cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'001111 - assign \ALU_cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'001011 - assign \ALU_cr_out 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'001010 - assign \ALU_cr_out 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'001000 - assign \ALU_cr_out 3'000 - end - sync init - end - attribute \enum_base_type "LdstLen" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "is1B" - attribute \enum_value_0010 "is2B" - attribute \enum_value_0100 "is4B" - attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 4 \ALU_ldst_len$19 - attribute \enum_base_type "LdstLen" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "is1B" - attribute \enum_value_0010 "is2B" - attribute \enum_value_0100 "is4B" - attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 4 \ALU_ldst_len$20 - attribute \enum_base_type "LdstLen" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "is1B" - attribute \enum_value_0010 "is2B" - attribute \enum_value_0100 "is4B" - attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 4 \ALU_ldst_len$21 - process $group_12 - assign \ALU_ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'010011 - assign \ALU_ldst_len \ALU_dec19_ALU_ldst_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'011110 - assign \ALU_ldst_len \ALU_ldst_len$19 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'011111 - assign \ALU_ldst_len \ALU_dec31_ALU_ldst_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'111010 - assign \ALU_ldst_len \ALU_ldst_len$20 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'111110 - assign \ALU_ldst_len \ALU_ldst_len$21 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'001100 - assign \ALU_ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'001101 - assign \ALU_ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'001110 - assign \ALU_ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'001111 - assign \ALU_ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'001011 - assign \ALU_ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'001010 - assign \ALU_ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'001000 - assign \ALU_ldst_len 4'0000 - end - sync init - end - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 2 \ALU_rc_sel$22 - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 2 \ALU_rc_sel$23 - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 2 \ALU_rc_sel$24 - process $group_13 - assign \ALU_rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'010011 - assign \ALU_rc_sel \ALU_dec19_ALU_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'011110 - assign \ALU_rc_sel \ALU_rc_sel$22 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'011111 - assign \ALU_rc_sel \ALU_dec31_ALU_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'111010 - assign \ALU_rc_sel \ALU_rc_sel$23 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'111110 - assign \ALU_rc_sel \ALU_rc_sel$24 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'001100 - assign \ALU_rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'001101 - assign \ALU_rc_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'001110 - assign \ALU_rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'001111 - assign \ALU_rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'001011 - assign \ALU_rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'001010 - assign \ALU_rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'001000 - assign \ALU_rc_sel 2'00 - end - sync init - end - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 2 \ALU_cry_in$25 - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 2 \ALU_cry_in$26 - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 2 \ALU_cry_in$27 - process $group_14 - assign \ALU_cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'010011 - assign \ALU_cry_in \ALU_dec19_ALU_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'011110 - assign \ALU_cry_in \ALU_cry_in$25 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'011111 - assign \ALU_cry_in \ALU_dec31_ALU_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'111010 - assign \ALU_cry_in \ALU_cry_in$26 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'111110 - assign \ALU_cry_in \ALU_cry_in$27 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'001100 - assign \ALU_cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'001101 - assign \ALU_cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'001110 - assign \ALU_cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'001111 - assign \ALU_cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'001011 - assign \ALU_cry_in 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'001010 - assign \ALU_cry_in 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'001000 - assign \ALU_cry_in 2'01 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \ALU_inv_a$28 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \ALU_inv_a$29 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \ALU_inv_a$30 - process $group_15 - assign \ALU_inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'010011 - assign \ALU_inv_a \ALU_dec19_ALU_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'011110 - assign \ALU_inv_a \ALU_inv_a$28 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'011111 - assign \ALU_inv_a \ALU_dec31_ALU_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'111010 - assign \ALU_inv_a \ALU_inv_a$29 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'111110 - assign \ALU_inv_a \ALU_inv_a$30 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'001100 - assign \ALU_inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'001101 - assign \ALU_inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'001110 - assign \ALU_inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'001111 - assign \ALU_inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'001011 - assign \ALU_inv_a 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'001010 - assign \ALU_inv_a 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'001000 - assign \ALU_inv_a 1'1 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \ALU_inv_out$31 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \ALU_inv_out$32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \ALU_inv_out$33 - process $group_16 - assign \ALU_inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'010011 - assign \ALU_inv_out \ALU_dec19_ALU_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'011110 - assign \ALU_inv_out \ALU_inv_out$31 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'011111 - assign \ALU_inv_out \ALU_dec31_ALU_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'111010 - assign \ALU_inv_out \ALU_inv_out$32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'111110 - assign \ALU_inv_out \ALU_inv_out$33 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'001100 - assign \ALU_inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'001101 - assign \ALU_inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'001110 - assign \ALU_inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'001111 - assign \ALU_inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'001011 - assign \ALU_inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'001010 - assign \ALU_inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'001000 - assign \ALU_inv_out 1'0 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \ALU_cry_out$34 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \ALU_cry_out$35 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \ALU_cry_out$36 - process $group_17 - assign \ALU_cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'010011 - assign \ALU_cry_out \ALU_dec19_ALU_cry_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'011110 - assign \ALU_cry_out \ALU_cry_out$34 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'011111 - assign \ALU_cry_out \ALU_dec31_ALU_cry_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'111010 - assign \ALU_cry_out \ALU_cry_out$35 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'111110 - assign \ALU_cry_out \ALU_cry_out$36 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'001100 - assign \ALU_cry_out 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'001101 - assign \ALU_cry_out 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'001110 - assign \ALU_cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'001111 - assign \ALU_cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'001011 - assign \ALU_cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'001010 - assign \ALU_cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'001000 - assign \ALU_cry_out 1'1 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \ALU_is_32b$37 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \ALU_is_32b$38 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \ALU_is_32b$39 - process $group_18 - assign \ALU_is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'010011 - assign \ALU_is_32b \ALU_dec19_ALU_is_32b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'011110 - assign \ALU_is_32b \ALU_is_32b$37 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'011111 - assign \ALU_is_32b \ALU_dec31_ALU_is_32b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'111010 - assign \ALU_is_32b \ALU_is_32b$38 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'111110 - assign \ALU_is_32b \ALU_is_32b$39 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'001100 - assign \ALU_is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'001101 - assign \ALU_is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'001110 - assign \ALU_is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'001111 - assign \ALU_is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'001011 - assign \ALU_is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'001010 - assign \ALU_is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'001000 - assign \ALU_is_32b 1'0 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \ALU_sgn$40 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \ALU_sgn$41 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \ALU_sgn$42 - process $group_19 - assign \ALU_sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'010011 - assign \ALU_sgn \ALU_dec19_ALU_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'011110 - assign \ALU_sgn \ALU_sgn$40 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'011111 - assign \ALU_sgn \ALU_dec31_ALU_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'111010 - assign \ALU_sgn \ALU_sgn$41 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'111110 - assign \ALU_sgn \ALU_sgn$42 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'001100 - assign \ALU_sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'001101 - assign \ALU_sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'001110 - assign \ALU_sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'001111 - assign \ALU_sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'001011 - assign \ALU_sgn 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'001010 - assign \ALU_sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'001000 - assign \ALU_sgn 1'0 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:308" - wire width 32 \opcode_switch$43 - process $group_20 - assign \opcode_switch$43 32'00000000000000000000000000000000 - assign \opcode_switch$43 \opcode_in - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:418" - wire width 32 $44 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:418" - cell $mux $45 - parameter \WIDTH 32 - connect \A \raw_opcode_in - connect \B { \raw_opcode_in [7:0] \raw_opcode_in [15:8] \raw_opcode_in [23:16] \raw_opcode_in [31:24] } - connect \S \bigendian - connect \Y $44 - end - process $group_21 - assign \opcode_in 32'00000000000000000000000000000000 - assign \opcode_in $44 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 5 \ALU_RS - process $group_22 - assign \ALU_RS 5'00000 - assign \ALU_RS { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 5 \ALU_RT - process $group_23 - assign \ALU_RT 5'00000 - assign \ALU_RT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - process $group_24 - assign \ALU_RA 5'00000 - assign \ALU_RA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 5 \ALU_RB - process $group_25 - assign \ALU_RB 5'00000 - assign \ALU_RB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - process $group_26 - assign \ALU_SI 16'0000000000000000 - assign \ALU_SI { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] \opcode_in [0] } - sync init - end - process $group_27 - assign \ALU_UI 16'0000000000000000 - assign \ALU_UI { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] \opcode_in [0] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 1 \ALU_L - process $group_28 - assign \ALU_L 1'0 - assign \ALU_L { \opcode_in [21] } - sync init - end - process $group_29 - assign \ALU_SH32 5'00000 - assign \ALU_SH32 { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - process $group_30 - assign \ALU_sh 6'000000 - assign \ALU_sh { \opcode_in [1] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 5 \ALU_MB32 - process $group_31 - assign \ALU_MB32 5'00000 - assign \ALU_MB32 { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 5 \ALU_ME32 - process $group_32 - assign \ALU_ME32 5'00000 - assign \ALU_ME32 { \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] } - sync init - end - process $group_33 - assign \ALU_LI 24'000000000000000000000000 - assign \ALU_LI { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 1 \ALU_LK - process $group_34 - assign \ALU_LK 1'0 - assign \ALU_LK { \opcode_in [0] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 1 \ALU_AA - process $group_35 - assign \ALU_AA 1'0 - assign \ALU_AA { \opcode_in [1] } - sync init - end - process $group_36 - assign \ALU_Rc 1'0 - assign \ALU_Rc { \opcode_in [0] } - sync init - end - process $group_37 - assign \ALU_OE 1'0 - assign \ALU_OE { \opcode_in [10] } - sync init - end - process $group_38 - assign \ALU_BD 14'00000000000000 - assign \ALU_BD { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 3 \ALU_BF - process $group_39 - assign \ALU_BF 3'000 - assign \ALU_BF { \opcode_in [25] \opcode_in [24] \opcode_in [23] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 10 \ALU_CR - process $group_40 - assign \ALU_CR 10'0000000000 - assign \ALU_CR { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] } - sync init - end - process $group_41 - assign \ALU_BB 5'00000 - assign \ALU_BB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - process $group_42 - assign \ALU_BA 5'00000 - assign \ALU_BA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - process $group_43 - assign \ALU_BT 5'00000 - assign \ALU_BT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - process $group_44 - assign \ALU_FXM 8'00000000 - assign \ALU_FXM { \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 5 \ALU_BO - process $group_45 - assign \ALU_BO 5'00000 - assign \ALU_BO { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - process $group_46 - assign \ALU_BI 5'00000 - assign \ALU_BI { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 2 \ALU_BH - process $group_47 - assign \ALU_BH 2'00 - assign \ALU_BH { \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 16 \ALU_D - process $group_48 - assign \ALU_D 16'0000000000000000 - assign \ALU_D { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] \opcode_in [0] } - sync init - end - process $group_49 - assign \ALU_DS 14'00000000000000 - assign \ALU_DS { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 5 \ALU_TO - process $group_50 - assign \ALU_TO 5'00000 - assign \ALU_TO { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - process $group_51 - assign \ALU_BC 5'00000 - assign \ALU_BC { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 5 \ALU_SH - process $group_52 - assign \ALU_SH 5'00000 - assign \ALU_SH { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 5 \ALU_ME - process $group_53 - assign \ALU_ME 5'00000 - assign \ALU_ME { \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 5 \ALU_MB - process $group_54 - assign \ALU_MB 5'00000 - assign \ALU_MB { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 10 \ALU_SPR - process $group_55 - assign \ALU_SPR 10'0000000000 - assign \ALU_SPR { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \X_A - process $group_56 - assign \X_A 1'0 - assign \X_A { \opcode_in [25] } - sync init - end - process $group_57 - assign \X_BF 3'000 - assign \X_BF { \opcode_in [25] \opcode_in [24] \opcode_in [23] } - sync init - end - process $group_58 - assign \X_BFA 3'000 - assign \X_BFA { \opcode_in [20] \opcode_in [19] \opcode_in [18] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \X_BO - process $group_59 - assign \X_BO 5'00000 - assign \X_BO { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 4 \X_CT - process $group_60 - assign \X_CT 4'0000 - assign \X_CT { \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 7 \X_DCMX - process $group_61 - assign \X_DCMX 7'0000000 - assign \X_DCMX { \opcode_in [22] \opcode_in [21] \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 3 \X_DRM - process $group_62 - assign \X_DRM 3'000 - assign \X_DRM { \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \X_E - process $group_63 - assign \X_E 1'0 - assign \X_E { \opcode_in [15] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 4 \X_E_1 - process $group_64 - assign \X_E_1 4'0000 - assign \X_E_1 { \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 2 \X_EO - process $group_65 - assign \X_EO 2'00 - assign \X_EO { \opcode_in [20] \opcode_in [19] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \X_EO_1 - process $group_66 - assign \X_EO_1 5'00000 - assign \X_EO_1 { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \X_EX - process $group_67 - assign \X_EX 1'0 - assign \X_EX { \opcode_in [0] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \X_FC - process $group_68 - assign \X_FC 5'00000 - assign \X_FC { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \X_FRA - process $group_69 - assign \X_FRA 5'00000 - assign \X_FRA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \X_FRAp - process $group_70 - assign \X_FRAp 5'00000 - assign \X_FRAp { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \X_FRB - process $group_71 - assign \X_FRB 5'00000 - assign \X_FRB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \X_FRBp - process $group_72 - assign \X_FRBp 5'00000 - assign \X_FRBp { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \X_FRS - process $group_73 - assign \X_FRS 5'00000 - assign \X_FRS { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \X_FRSp - process $group_74 - assign \X_FRSp 5'00000 - assign \X_FRSp { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \X_FRT - process $group_75 - assign \X_FRT 5'00000 - assign \X_FRT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \X_FRTp - process $group_76 - assign \X_FRTp 5'00000 - assign \X_FRTp { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 3 \X_IH - process $group_77 - assign \X_IH 3'000 - assign \X_IH { \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 8 \X_IMM8 - process $group_78 - assign \X_IMM8 8'00000000 - assign \X_IMM8 { \opcode_in [18] \opcode_in [17] \opcode_in [16] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 2 \X_L2 - process $group_79 - assign \X_L2 2'00 - assign \X_L2 { \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \X_L - process $group_80 - assign \X_L 1'0 - assign \X_L { \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \X_L1 - process $group_81 - assign \X_L1 1'0 - assign \X_L1 { \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 2 \X_L3 - process $group_82 - assign \X_L3 2'00 - assign \X_L3 { \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \X_MO - process $group_83 - assign \X_MO 5'00000 - assign \X_MO { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \X_NB - process $group_84 - assign \X_NB 5'00000 - assign \X_NB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \X_PRS - process $group_85 - assign \X_PRS 1'0 - assign \X_PRS { \opcode_in [17] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \X_R - process $group_86 - assign \X_R 1'0 - assign \X_R { \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \X_R_1 - process $group_87 - assign \X_R_1 1'0 - assign \X_R_1 { \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \X_RA - process $group_88 - assign \X_RA 5'00000 - assign \X_RA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \X_RB - process $group_89 - assign \X_RB 5'00000 - assign \X_RB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \X_Rc - process $group_90 - assign \X_Rc 1'0 - assign \X_Rc { \opcode_in [0] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 2 \X_RIC - process $group_91 - assign \X_RIC 2'00 - assign \X_RIC { \opcode_in [19] \opcode_in [18] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 2 \X_RM - process $group_92 - assign \X_RM 2'00 - assign \X_RM { \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \X_RO - process $group_93 - assign \X_RO 1'0 - assign \X_RO { \opcode_in [0] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \X_RS - process $group_94 - assign \X_RS 5'00000 - assign \X_RS { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \X_RSp - process $group_95 - assign \X_RSp 5'00000 - assign \X_RSp { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \X_RT - process $group_96 - assign \X_RT 5'00000 - assign \X_RT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \X_RTp - process $group_97 - assign \X_RTp 5'00000 - assign \X_RTp { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \X_S - process $group_98 - assign \X_S 5'00000 - assign \X_S { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \X_SH - process $group_99 - assign \X_SH 5'00000 - assign \X_SH { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \X_SI - process $group_100 - assign \X_SI 5'00000 - assign \X_SI { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 2 \X_SP - process $group_101 - assign \X_SP 2'00 - assign \X_SP { \opcode_in [20] \opcode_in [19] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 4 \X_SR - process $group_102 - assign \X_SR 4'0000 - assign \X_SR { \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \X_SX - process $group_103 - assign \X_SX 1'0 - assign \X_SX { \opcode_in [0] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 6 \X_SX_S - process $group_104 - assign \X_SX_S 6'000000 - assign \X_SX_S { \opcode_in [0] \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \X_T - process $group_105 - assign \X_T 5'00000 - assign \X_T { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 10 \X_TBR - process $group_106 - assign \X_TBR 10'0000000000 - assign \X_TBR { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \X_TH - process $group_107 - assign \X_TH 5'00000 - assign \X_TH { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \X_TO - process $group_108 - assign \X_TO 5'00000 - assign \X_TO { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \X_TX - process $group_109 - assign \X_TX 1'0 - assign \X_TX { \opcode_in [0] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 6 \X_TX_T - process $group_110 - assign \X_TX_T 6'000000 - assign \X_TX_T { \opcode_in [0] \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 4 \X_U - process $group_111 - assign \X_U 4'0000 - assign \X_U { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \X_UIM - process $group_112 - assign \X_UIM 5'00000 - assign \X_UIM { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \X_VRS - process $group_113 - assign \X_VRS 5'00000 - assign \X_VRS { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \X_VRT - process $group_114 - assign \X_VRT 5'00000 - assign \X_VRT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \X_W - process $group_115 - assign \X_W 1'0 - assign \X_W { \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 2 \X_WC - process $group_116 - assign \X_WC 2'00 - assign \X_WC { \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 10 \X_XO - process $group_117 - assign \X_XO 10'0000000000 - assign \X_XO { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 8 \X_XO_1 - process $group_118 - assign \X_XO_1 8'00000000 - assign \X_XO_1 { \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \B_AA - process $group_119 - assign \B_AA 1'0 - assign \B_AA { \opcode_in [1] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 14 \B_BD - process $group_120 - assign \B_BD 14'00000000000000 - assign \B_BD { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \B_BI - process $group_121 - assign \B_BI 5'00000 - assign \B_BI { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \B_BO - process $group_122 - assign \B_BO 5'00000 - assign \B_BO { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \B_LK - process $group_123 - assign \B_LK 1'0 - assign \B_LK { \opcode_in [0] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \I_AA - process $group_124 - assign \I_AA 1'0 - assign \I_AA { \opcode_in [1] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 24 \I_LI - process $group_125 - assign \I_LI 24'000000000000000000000000 - assign \I_LI { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \I_LK - process $group_126 - assign \I_LK 1'0 - assign \I_LK { \opcode_in [0] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \XX3_AX - process $group_127 - assign \XX3_AX 1'0 - assign \XX3_AX { \opcode_in [2] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \XX3_A - process $group_128 - assign \XX3_A 5'00000 - assign \XX3_A { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 6 \XX3_AX_A - process $group_129 - assign \XX3_AX_A 6'000000 - assign \XX3_AX_A { \opcode_in [2] \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 3 \XX3_BF - process $group_130 - assign \XX3_BF 3'000 - assign \XX3_BF { \opcode_in [25] \opcode_in [24] \opcode_in [23] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \XX3_BX - process $group_131 - assign \XX3_BX 1'0 - assign \XX3_BX { \opcode_in [1] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \XX3_B - process $group_132 - assign \XX3_B 5'00000 - assign \XX3_B { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 6 \XX3_BX_B - process $group_133 - assign \XX3_BX_B 6'000000 - assign \XX3_BX_B { \opcode_in [1] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 2 \XX3_DM - process $group_134 - assign \XX3_DM 2'00 - assign \XX3_DM { \opcode_in [9] \opcode_in [8] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \XX3_Rc - process $group_135 - assign \XX3_Rc 1'0 - assign \XX3_Rc { \opcode_in [10] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 2 \XX3_SHW - process $group_136 - assign \XX3_SHW 2'00 - assign \XX3_SHW { \opcode_in [9] \opcode_in [8] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \XX3_TX - process $group_137 - assign \XX3_TX 1'0 - assign \XX3_TX { \opcode_in [0] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \XX3_T - process $group_138 - assign \XX3_T 5'00000 - assign \XX3_T { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 6 \XX3_TX_T - process $group_139 - assign \XX3_TX_T 6'000000 - assign \XX3_TX_T { \opcode_in [0] \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 4 \XX3_XO - process $group_140 - assign \XX3_XO 4'0000 - assign \XX3_XO { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 8 \XX3_XO_1 - process $group_141 - assign \XX3_XO_1 8'00000000 - assign \XX3_XO_1 { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 9 \XX3_XO_2 - process $group_142 - assign \XX3_XO_2 9'000000000 - assign \XX3_XO_2 { \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \XX4_AX - process $group_143 - assign \XX4_AX 1'0 - assign \XX4_AX { \opcode_in [2] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \XX4_A - process $group_144 - assign \XX4_A 5'00000 - assign \XX4_A { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 6 \XX4_AX_A - process $group_145 - assign \XX4_AX_A 6'000000 - assign \XX4_AX_A { \opcode_in [2] \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \XX4_BX - process $group_146 - assign \XX4_BX 1'0 - assign \XX4_BX { \opcode_in [1] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \XX4_B - process $group_147 - assign \XX4_B 5'00000 - assign \XX4_B { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 6 \XX4_BX_B - process $group_148 - assign \XX4_BX_B 6'000000 - assign \XX4_BX_B { \opcode_in [1] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \XX4_CX - process $group_149 - assign \XX4_CX 1'0 - assign \XX4_CX { \opcode_in [3] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \XX4_C - process $group_150 - assign \XX4_C 5'00000 - assign \XX4_C { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 6 \XX4_CX_C - process $group_151 - assign \XX4_CX_C 6'000000 - assign \XX4_CX_C { \opcode_in [3] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \XX4_TX - process $group_152 - assign \XX4_TX 1'0 - assign \XX4_TX { \opcode_in [0] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \XX4_T - process $group_153 - assign \XX4_T 5'00000 - assign \XX4_T { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 6 \XX4_TX_T - process $group_154 - assign \XX4_TX_T 6'000000 - assign \XX4_TX_T { \opcode_in [0] \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 2 \XX4_XO - process $group_155 - assign \XX4_XO 2'00 - assign \XX4_XO { \opcode_in [5] \opcode_in [4] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \XL_BA - process $group_156 - assign \XL_BA 5'00000 - assign \XL_BA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \XL_BB - process $group_157 - assign \XL_BB 5'00000 - assign \XL_BB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 3 \XL_BF - process $group_158 - assign \XL_BF 3'000 - assign \XL_BF { \opcode_in [25] \opcode_in [24] \opcode_in [23] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 3 \XL_BFA - process $group_159 - assign \XL_BFA 3'000 - assign \XL_BFA { \opcode_in [20] \opcode_in [19] \opcode_in [18] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 2 \XL_BH - process $group_160 - assign \XL_BH 2'00 - assign \XL_BH { \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \XL_BI - process $group_161 - assign \XL_BI 5'00000 - assign \XL_BI { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \XL_BO - process $group_162 - assign \XL_BO 5'00000 - assign \XL_BO { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \XL_BO_1 - process $group_163 - assign \XL_BO_1 5'00000 - assign \XL_BO_1 { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - process $group_164 - assign \XL_BT 5'00000 - assign \XL_BT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \XL_LK - process $group_165 - assign \XL_LK 1'0 - assign \XL_LK { \opcode_in [0] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 15 \XL_OC - process $group_166 - assign \XL_OC 15'000000000000000 - assign \XL_OC { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \XL_S - process $group_167 - assign \XL_S 1'0 - assign \XL_S { \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 10 \XL_XO - process $group_168 - assign \XL_XO 10'0000000000 - assign \XL_XO { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \A_BC - process $group_169 - assign \A_BC 5'00000 - assign \A_BC { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \A_FRA - process $group_170 - assign \A_FRA 5'00000 - assign \A_FRA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \A_FRB - process $group_171 - assign \A_FRB 5'00000 - assign \A_FRB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \A_FRC - process $group_172 - assign \A_FRC 5'00000 - assign \A_FRC { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \A_FRT - process $group_173 - assign \A_FRT 5'00000 - assign \A_FRT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \A_RA - process $group_174 - assign \A_RA 5'00000 - assign \A_RA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \A_RB - process $group_175 - assign \A_RB 5'00000 - assign \A_RB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \A_Rc - process $group_176 - assign \A_Rc 1'0 - assign \A_Rc { \opcode_in [0] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \A_RT - process $group_177 - assign \A_RT 5'00000 - assign \A_RT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \A_XO - process $group_178 - assign \A_XO 5'00000 - assign \A_XO { \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 3 \D_BF - process $group_179 - assign \D_BF 3'000 - assign \D_BF { \opcode_in [25] \opcode_in [24] \opcode_in [23] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 16 \D_D - process $group_180 - assign \D_D 16'0000000000000000 - assign \D_D { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] \opcode_in [0] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \D_FRS - process $group_181 - assign \D_FRS 5'00000 - assign \D_FRS { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \D_FRT - process $group_182 - assign \D_FRT 5'00000 - assign \D_FRT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \D_L - process $group_183 - assign \D_L 1'0 - assign \D_L { \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \D_RA - process $group_184 - assign \D_RA 5'00000 - assign \D_RA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \D_RS - process $group_185 - assign \D_RS 5'00000 - assign \D_RS { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \D_RT - process $group_186 - assign \D_RT 5'00000 - assign \D_RT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 16 \D_SI - process $group_187 - assign \D_SI 16'0000000000000000 - assign \D_SI { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] \opcode_in [0] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \D_TO - process $group_188 - assign \D_TO 5'00000 - assign \D_TO { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 16 \D_UI - process $group_189 - assign \D_UI 16'0000000000000000 - assign \D_UI { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] \opcode_in [0] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 3 \XX2_BF - process $group_190 - assign \XX2_BF 3'000 - assign \XX2_BF { \opcode_in [25] \opcode_in [24] \opcode_in [23] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \XX2_BX - process $group_191 - assign \XX2_BX 1'0 - assign \XX2_BX { \opcode_in [1] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \XX2_B - process $group_192 - assign \XX2_B 5'00000 - assign \XX2_B { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 6 \XX2_BX_B - process $group_193 - assign \XX2_BX_B 6'000000 - assign \XX2_BX_B { \opcode_in [1] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \XX2_dc - process $group_194 - assign \XX2_dc 1'0 - assign \XX2_dc { \opcode_in [6] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \XX2_dm - process $group_195 - assign \XX2_dm 1'0 - assign \XX2_dm { \opcode_in [2] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \XX2_dx - process $group_196 - assign \XX2_dx 5'00000 - assign \XX2_dx { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 7 \XX2_dc_dm_dx - process $group_197 - assign \XX2_dc_dm_dx 7'0000000 - assign \XX2_dc_dm_dx { \opcode_in [6] \opcode_in [2] \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 7 \XX2_DCMX - process $group_198 - assign \XX2_DCMX 7'0000000 - assign \XX2_DCMX { \opcode_in [22] \opcode_in [21] \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \XX2_EO - process $group_199 - assign \XX2_EO 5'00000 - assign \XX2_EO { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \XX2_RT - process $group_200 - assign \XX2_RT 5'00000 - assign \XX2_RT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \XX2_TX - process $group_201 - assign \XX2_TX 1'0 - assign \XX2_TX { \opcode_in [0] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \XX2_T - process $group_202 - assign \XX2_T 5'00000 - assign \XX2_T { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 6 \XX2_TX_T - process $group_203 - assign \XX2_TX_T 6'000000 - assign \XX2_TX_T { \opcode_in [0] \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 4 \XX2_UIM - process $group_204 - assign \XX2_UIM 4'0000 - assign \XX2_UIM { \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 2 \XX2_UIM_1 - process $group_205 - assign \XX2_UIM_1 2'00 - assign \XX2_UIM_1 { \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 7 \XX2_XO - process $group_206 - assign \XX2_XO 7'0000000 - assign \XX2_XO { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [5] \opcode_in [4] \opcode_in [3] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 9 \XX2_XO_1 - process $group_207 - assign \XX2_XO_1 9'000000000 - assign \XX2_XO_1 { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 3 \Z22_BF - process $group_208 - assign \Z22_BF 3'000 - assign \Z22_BF { \opcode_in [25] \opcode_in [24] \opcode_in [23] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 6 \Z22_DCM - process $group_209 - assign \Z22_DCM 6'000000 - assign \Z22_DCM { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 6 \Z22_DGM - process $group_210 - assign \Z22_DGM 6'000000 - assign \Z22_DGM { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \Z22_FRA - process $group_211 - assign \Z22_FRA 5'00000 - assign \Z22_FRA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \Z22_FRAp - process $group_212 - assign \Z22_FRAp 5'00000 - assign \Z22_FRAp { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \Z22_FRT - process $group_213 - assign \Z22_FRT 5'00000 - assign \Z22_FRT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \Z22_FRTp - process $group_214 - assign \Z22_FRTp 5'00000 - assign \Z22_FRTp { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \Z22_Rc - process $group_215 - assign \Z22_Rc 1'0 - assign \Z22_Rc { \opcode_in [0] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 6 \Z22_SH - process $group_216 - assign \Z22_SH 6'000000 - assign \Z22_SH { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 9 \Z22_XO - process $group_217 - assign \Z22_XO 9'000000000 - assign \Z22_XO { \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 3 \EVS_BFA - process $group_218 - assign \EVS_BFA 3'000 - assign \EVS_BFA { \opcode_in [2] \opcode_in [1] \opcode_in [0] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 10 \XFX_BHRBE - process $group_219 - assign \XFX_BHRBE 10'0000000000 - assign \XFX_BHRBE { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \XFX_DUI - process $group_220 - assign \XFX_DUI 5'00000 - assign \XFX_DUI { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 10 \XFX_DUIS - process $group_221 - assign \XFX_DUIS 10'0000000000 - assign \XFX_DUIS { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 8 \XFX_FXM - process $group_222 - assign \XFX_FXM 8'00000000 - assign \XFX_FXM { \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \XFX_RS - process $group_223 - assign \XFX_RS 5'00000 - assign \XFX_RS { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \XFX_RT - process $group_224 - assign \XFX_RT 5'00000 - assign \XFX_RT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 10 \XFX_SPR - process $group_225 - assign \XFX_SPR 10'0000000000 - assign \XFX_SPR { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 10 \XFX_XO - process $group_226 - assign \XFX_XO 10'0000000000 - assign \XFX_XO { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 10 \DX_d0 - process $group_227 - assign \DX_d0 10'0000000000 - assign \DX_d0 { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \DX_d1 - process $group_228 - assign \DX_d1 5'00000 - assign \DX_d1 { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \DX_d2 - process $group_229 - assign \DX_d2 1'0 - assign \DX_d2 { \opcode_in [0] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 16 \DX_d0_d1_d2 - process $group_230 - assign \DX_d0_d1_d2 16'0000000000000000 - assign \DX_d0_d1_d2 { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] \opcode_in [0] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \DX_RT - process $group_231 - assign \DX_RT 5'00000 - assign \DX_RT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \DX_XO - process $group_232 - assign \DX_XO 5'00000 - assign \DX_XO { \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 12 \DQ_DQ - process $group_233 - assign \DQ_DQ 12'000000000000 - assign \DQ_DQ { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 4 \DQ_PT - process $group_234 - assign \DQ_PT 4'0000 - assign \DQ_PT { \opcode_in [3] \opcode_in [2] \opcode_in [1] \opcode_in [0] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \DQ_RA - process $group_235 - assign \DQ_RA 5'00000 - assign \DQ_RA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \DQ_RTp - process $group_236 - assign \DQ_RTp 5'00000 - assign \DQ_RTp { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \DQ_SX - process $group_237 - assign \DQ_SX 1'0 - assign \DQ_SX { \opcode_in [3] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \DQ_S - process $group_238 - assign \DQ_S 5'00000 - assign \DQ_S { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 6 \DQ_SX_S - process $group_239 - assign \DQ_SX_S 6'000000 - assign \DQ_SX_S { \opcode_in [3] \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \DQ_TX - process $group_240 - assign \DQ_TX 1'0 - assign \DQ_TX { \opcode_in [3] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \DQ_T - process $group_241 - assign \DQ_T 5'00000 - assign \DQ_T { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 6 \DQ_TX_T - process $group_242 - assign \DQ_TX_T 6'000000 - assign \DQ_TX_T { \opcode_in [3] \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 3 \DQ_XO - process $group_243 - assign \DQ_XO 3'000 - assign \DQ_XO { \opcode_in [2] \opcode_in [1] \opcode_in [0] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 14 \DS_DS - process $group_244 - assign \DS_DS 14'00000000000000 - assign \DS_DS { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \DS_FRSp - process $group_245 - assign \DS_FRSp 5'00000 - assign \DS_FRSp { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \DS_FRTp - process $group_246 - assign \DS_FRTp 5'00000 - assign \DS_FRTp { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \DS_RA - process $group_247 - assign \DS_RA 5'00000 - assign \DS_RA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \DS_RS - process $group_248 - assign \DS_RS 5'00000 - assign \DS_RS { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \DS_RSp - process $group_249 - assign \DS_RSp 5'00000 - assign \DS_RSp { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \DS_RT - process $group_250 - assign \DS_RT 5'00000 - assign \DS_RT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \DS_VRS - process $group_251 - assign \DS_VRS 5'00000 - assign \DS_VRS { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \DS_VRT - process $group_252 - assign \DS_VRT 5'00000 - assign \DS_VRT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 2 \DS_XO - process $group_253 - assign \DS_XO 2'00 - assign \DS_XO { \opcode_in [1] \opcode_in [0] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \VX_EO - process $group_254 - assign \VX_EO 5'00000 - assign \VX_EO { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \VX_PS - process $group_255 - assign \VX_PS 1'0 - assign \VX_PS { \opcode_in [9] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \VX_RA - process $group_256 - assign \VX_RA 5'00000 - assign \VX_RA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \VX_RT - process $group_257 - assign \VX_RT 5'00000 - assign \VX_RT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \VX_SIM - process $group_258 - assign \VX_SIM 5'00000 - assign \VX_SIM { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \VX_UIM - process $group_259 - assign \VX_UIM 5'00000 - assign \VX_UIM { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 4 \VX_UIM_1 - process $group_260 - assign \VX_UIM_1 4'0000 - assign \VX_UIM_1 { \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 3 \VX_UIM_2 - process $group_261 - assign \VX_UIM_2 3'000 - assign \VX_UIM_2 { \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 2 \VX_UIM_3 - process $group_262 - assign \VX_UIM_3 2'00 - assign \VX_UIM_3 { \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \VX_VRA - process $group_263 - assign \VX_VRA 5'00000 - assign \VX_VRA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \VX_VRB - process $group_264 - assign \VX_VRB 5'00000 - assign \VX_VRB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \VX_VRT - process $group_265 - assign \VX_VRT 5'00000 - assign \VX_VRT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 10 \VX_XO - process $group_266 - assign \VX_XO 10'0000000000 - assign \VX_XO { \opcode_in [10] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] \opcode_in [0] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 11 \VX_XO_1 - process $group_267 - assign \VX_XO_1 11'00000000000 - assign \VX_XO_1 { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] \opcode_in [0] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 8 \XFL_FLM - process $group_268 - assign \XFL_FLM 8'00000000 - assign \XFL_FLM { \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \XFL_FRB - process $group_269 - assign \XFL_FRB 5'00000 - assign \XFL_FRB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \XFL_L - process $group_270 - assign \XFL_L 1'0 - assign \XFL_L { \opcode_in [25] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \XFL_Rc - process $group_271 - assign \XFL_Rc 1'0 - assign \XFL_Rc { \opcode_in [0] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \XFL_W - process $group_272 - assign \XFL_W 1'0 - assign \XFL_W { \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 10 \XFL_XO - process $group_273 - assign \XFL_XO 10'0000000000 - assign \XFL_XO { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \Z23_FRA - process $group_274 - assign \Z23_FRA 5'00000 - assign \Z23_FRA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \Z23_FRAp - process $group_275 - assign \Z23_FRAp 5'00000 - assign \Z23_FRAp { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \Z23_FRB - process $group_276 - assign \Z23_FRB 5'00000 - assign \Z23_FRB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \Z23_FRBp - process $group_277 - assign \Z23_FRBp 5'00000 - assign \Z23_FRBp { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \Z23_FRT - process $group_278 - assign \Z23_FRT 5'00000 - assign \Z23_FRT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \Z23_FRTp - process $group_279 - assign \Z23_FRTp 5'00000 - assign \Z23_FRTp { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \Z23_R - process $group_280 - assign \Z23_R 1'0 - assign \Z23_R { \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \Z23_Rc - process $group_281 - assign \Z23_Rc 1'0 - assign \Z23_Rc { \opcode_in [0] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 2 \Z23_RMC - process $group_282 - assign \Z23_RMC 2'00 - assign \Z23_RMC { \opcode_in [10] \opcode_in [9] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \Z23_TE - process $group_283 - assign \Z23_TE 5'00000 - assign \Z23_TE { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 8 \Z23_XO - process $group_284 - assign \Z23_XO 8'00000000 - assign \Z23_XO { \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \MDS_IB - process $group_285 - assign \MDS_IB 5'00000 - assign \MDS_IB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \MDS_IS - process $group_286 - assign \MDS_IS 5'00000 - assign \MDS_IS { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 6 \MDS_mb - process $group_287 - assign \MDS_mb 6'000000 - assign \MDS_mb { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 6 \MDS_me - process $group_288 - assign \MDS_me 6'000000 - assign \MDS_me { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \MDS_RA - process $group_289 - assign \MDS_RA 5'00000 - assign \MDS_RA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \MDS_RB - process $group_290 - assign \MDS_RB 5'00000 - assign \MDS_RB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \MDS_Rc - process $group_291 - assign \MDS_Rc 1'0 - assign \MDS_Rc { \opcode_in [0] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \MDS_RS - process $group_292 - assign \MDS_RS 5'00000 - assign \MDS_RS { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 4 \MDS_XBI - process $group_293 - assign \MDS_XBI 4'0000 - assign \MDS_XBI { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 4 \MDS_XBI_1 - process $group_294 - assign \MDS_XBI_1 4'0000 - assign \MDS_XBI_1 { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 4 \MDS_XO - process $group_295 - assign \MDS_XO 4'0000 - assign \MDS_XO { \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 7 \SC_LEV - process $group_296 - assign \SC_LEV 7'0000000 - assign \SC_LEV { \opcode_in [11] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \SC_XO - process $group_297 - assign \SC_XO 1'0 - assign \SC_XO { \opcode_in [1] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 2 \SC_XO_1 - process $group_298 - assign \SC_XO_1 2'00 - assign \SC_XO_1 { \opcode_in [1] \opcode_in [0] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \M_MB - process $group_299 - assign \M_MB 5'00000 - assign \M_MB { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \M_ME - process $group_300 - assign \M_ME 5'00000 - assign \M_ME { \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \M_RA - process $group_301 - assign \M_RA 5'00000 - assign \M_RA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \M_RB - process $group_302 - assign \M_RB 5'00000 - assign \M_RB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \M_Rc - process $group_303 - assign \M_Rc 1'0 - assign \M_Rc { \opcode_in [0] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \M_RS - process $group_304 - assign \M_RS 5'00000 - assign \M_RS { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \M_SH - process $group_305 - assign \M_SH 5'00000 - assign \M_SH { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 6 \MD_mb - process $group_306 - assign \MD_mb 6'000000 - assign \MD_mb { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 6 \MD_me - process $group_307 - assign \MD_me 6'000000 - assign \MD_me { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \MD_RA - process $group_308 - assign \MD_RA 5'00000 - assign \MD_RA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \MD_Rc - process $group_309 - assign \MD_Rc 1'0 - assign \MD_Rc { \opcode_in [0] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \MD_RS - process $group_310 - assign \MD_RS 5'00000 - assign \MD_RS { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 6 \MD_sh - process $group_311 - assign \MD_sh 6'000000 - assign \MD_sh { \opcode_in [1] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 3 \MD_XO - process $group_312 - assign \MD_XO 3'000 - assign \MD_XO { \opcode_in [4] \opcode_in [3] \opcode_in [2] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 6 \all_OPCD - process $group_313 - assign \all_OPCD 6'000000 - assign \all_OPCD { \opcode_in [31] \opcode_in [30] \opcode_in [29] \opcode_in [28] \opcode_in [27] \opcode_in [26] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 6 \all_PO - process $group_314 - assign \all_PO 6'000000 - assign \all_PO { \opcode_in [31] \opcode_in [30] \opcode_in [29] \opcode_in [28] \opcode_in [27] \opcode_in [26] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \XO_OE - process $group_315 - assign \XO_OE 1'0 - assign \XO_OE { \opcode_in [10] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \XO_RA - process $group_316 - assign \XO_RA 5'00000 - assign \XO_RA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \XO_RB - process $group_317 - assign \XO_RB 5'00000 - assign \XO_RB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \XO_Rc - process $group_318 - assign \XO_Rc 1'0 - assign \XO_Rc { \opcode_in [0] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \XO_RT - process $group_319 - assign \XO_RT 5'00000 - assign \XO_RT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 9 \XO_XO - process $group_320 - assign \XO_XO 9'000000000 - assign \XO_XO { \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \DQE_RA - process $group_321 - assign \DQE_RA 5'00000 - assign \DQE_RA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \DQE_RT - process $group_322 - assign \DQE_RT 5'00000 - assign \DQE_RT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 2 \DQE_XO - process $group_323 - assign \DQE_XO 2'00 - assign \DQE_XO { \opcode_in [1] \opcode_in [0] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \TX_RA - process $group_324 - assign \TX_RA 5'00000 - assign \TX_RA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \TX_UI - process $group_325 - assign \TX_UI 5'00000 - assign \TX_UI { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 4 \TX_XBI - process $group_326 - assign \TX_XBI 4'0000 - assign \TX_XBI { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 6 \TX_XO - process $group_327 - assign \TX_XO 6'000000 - assign \TX_XO { \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \VA_RA - process $group_328 - assign \VA_RA 5'00000 - assign \VA_RA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \VA_RB - process $group_329 - assign \VA_RB 5'00000 - assign \VA_RB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \VA_RC - process $group_330 - assign \VA_RC 5'00000 - assign \VA_RC { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \VA_RT - process $group_331 - assign \VA_RT 5'00000 - assign \VA_RT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 4 \VA_SHB - process $group_332 - assign \VA_SHB 4'0000 - assign \VA_SHB { \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \VA_VRA - process $group_333 - assign \VA_VRA 5'00000 - assign \VA_VRA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \VA_VRB - process $group_334 - assign \VA_VRB 5'00000 - assign \VA_VRB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \VA_VRC - process $group_335 - assign \VA_VRC 5'00000 - assign \VA_VRC { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \VA_VRT - process $group_336 - assign \VA_VRT 5'00000 - assign \VA_VRT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 6 \VA_XO - process $group_337 - assign \VA_XO 6'000000 - assign \VA_XO { \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] \opcode_in [0] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \XS_RA - process $group_338 - assign \XS_RA 5'00000 - assign \XS_RA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \XS_Rc - process $group_339 - assign \XS_Rc 1'0 - assign \XS_Rc { \opcode_in [0] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \XS_RS - process $group_340 - assign \XS_RS 5'00000 - assign \XS_RS { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 6 \XS_sh - process $group_341 - assign \XS_sh 6'000000 - assign \XS_sh { \opcode_in [1] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 9 \XS_XO - process $group_342 - assign \XS_XO 9'000000000 - assign \XS_XO { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \VC_Rc - process $group_343 - assign \VC_Rc 1'0 - assign \VC_Rc { \opcode_in [10] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \VC_VRA - process $group_344 - assign \VC_VRA 5'00000 - assign \VC_VRA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \VC_VRB - process $group_345 - assign \VC_VRB 5'00000 - assign \VC_VRB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \VC_VRT - process $group_346 - assign \VC_VRT 5'00000 - assign \VC_VRT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 10 \VC_XO - process $group_347 - assign \VC_XO 10'0000000000 - assign \VC_XO { \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] \opcode_in [0] } - sync init - end - connect \ALU_function_unit$1 11'00000000000 - connect \ALU_function_unit$2 11'00000000000 - connect \ALU_function_unit$3 11'00000000000 - connect \ALU_internal_op$4 7'0000000 - connect \ALU_internal_op$5 7'0000000 - connect \ALU_internal_op$6 7'0000000 - connect \ALU_in1_sel$7 3'000 - connect \ALU_in1_sel$8 3'000 - connect \ALU_in1_sel$9 3'000 - connect \ALU_in2_sel$10 4'0000 - connect \ALU_in2_sel$11 4'0000 - connect \ALU_in2_sel$12 4'0000 - connect \ALU_cr_in$13 3'000 - connect \ALU_cr_in$14 3'000 - connect \ALU_cr_in$15 3'000 - connect \ALU_cr_out$16 3'000 - connect \ALU_cr_out$17 3'000 - connect \ALU_cr_out$18 3'000 - connect \ALU_ldst_len$19 4'0000 - connect \ALU_ldst_len$20 4'0000 - connect \ALU_ldst_len$21 4'0000 - connect \ALU_rc_sel$22 2'00 - connect \ALU_rc_sel$23 2'00 - connect \ALU_rc_sel$24 2'00 - connect \ALU_cry_in$25 2'00 - connect \ALU_cry_in$26 2'00 - connect \ALU_cry_in$27 2'00 - connect \ALU_inv_a$28 1'0 - connect \ALU_inv_a$29 1'0 - connect \ALU_inv_a$30 1'0 - connect \ALU_inv_out$31 1'0 - connect \ALU_inv_out$32 1'0 - connect \ALU_inv_out$33 1'0 - connect \ALU_cry_out$34 1'0 - connect \ALU_cry_out$35 1'0 - connect \ALU_cry_out$36 1'0 - connect \ALU_is_32b$37 1'0 - connect \ALU_is_32b$38 1'0 - connect \ALU_is_32b$39 1'0 - connect \ALU_sgn$40 1'0 - connect \ALU_sgn$41 1'0 - connect \ALU_sgn$42 1'0 -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.dec_ALU.dec_rc" -module \dec_rc - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:404" - wire width 2 input 0 \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 1 \rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 2 \rc_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 1 input 3 \ALU_Rc - process $group_0 - assign \rc 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:413" - switch \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:414" - attribute \nmigen.decoding "RC/2" - case 2'10 - assign \rc \ALU_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:417" - attribute \nmigen.decoding "ONE/1" - case 2'01 - assign \rc 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:420" - attribute \nmigen.decoding "NONE/0" - case 2'00 - assign \rc 1'0 - end - sync init - end - process $group_1 - assign \rc_ok 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:413" - switch \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:414" - attribute \nmigen.decoding "RC/2" - case 2'10 - assign \rc_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:417" - attribute \nmigen.decoding "ONE/1" - case 2'01 - assign \rc_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:420" - attribute \nmigen.decoding "NONE/0" - case 2'00 - assign \rc_ok 1'1 - end - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.dec_ALU.dec_oe" -module \dec_oe - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:441" - wire width 2 input 0 \sel_in - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 7 input 1 \ALU_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 2 \oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 3 \oe_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 1 input 4 \ALU_OE - process $group_0 - assign \oe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:450" - switch \ALU_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:461" - attribute \nmigen.decoding "OP_MUL_H64/51|OP_MUL_H32/52|OP_EXTS/31|OP_CNTZ/14|OP_SHL/60|OP_SHR/61|OP_RLC/56|OP_LOAD/37|OP_STORE/38|OP_RLCL/57|OP_RLCR/58|OP_EXTSWSLI/32" - case 7'0110011, 7'0110100, 7'0011111, 7'0001110, 7'0111100, 7'0111101, 7'0111000, 7'0100101, 7'0100110, 7'0111001, 7'0111010, 7'0100000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:465" - attribute \nmigen.decoding "" - case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:467" - switch \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:468" - attribute \nmigen.decoding "RC/2" - case 2'10 - assign \oe \ALU_OE - end - end - sync init - end - process $group_1 - assign \oe_ok 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:450" - switch \ALU_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:461" - attribute \nmigen.decoding "OP_MUL_H64/51|OP_MUL_H32/52|OP_EXTS/31|OP_CNTZ/14|OP_SHL/60|OP_SHR/61|OP_RLC/56|OP_LOAD/37|OP_STORE/38|OP_RLCL/57|OP_RLCR/58|OP_EXTSWSLI/32" - case 7'0110011, 7'0110100, 7'0011111, 7'0001110, 7'0111100, 7'0111101, 7'0111000, 7'0100101, 7'0100110, 7'0111001, 7'0111010, 7'0100000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:465" - attribute \nmigen.decoding "" - case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:467" - switch \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:468" - attribute \nmigen.decoding "RC/2" - case 2'10 - assign \oe_ok 1'1 - end - end - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.dec_ALU.dec_cr_in.ppick" -module \ppick - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" - wire width 8 input 0 \i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" - wire width 8 output 1 \o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:49" - wire width 8 \ni - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" - wire width 8 $1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" - cell $not $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \Y_WIDTH 8 - connect \A { \i [0] \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] } - connect \Y $1 - end - process $group_0 - assign \ni 8'00000000 - assign \ni $1 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire width 1 \t0 - process $group_1 - assign \t0 1'0 - assign \t0 \i [7] - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire width 1 \t1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire width 1 $3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire width 1 $4 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_bool $5 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A { \i [7] \ni [1] } - connect \Y $4 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $6 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $4 - connect \Y $3 - end - process $group_2 - assign \t1 1'0 - assign \t1 $3 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire width 1 \t2 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire width 1 $7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire width 1 $8 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_bool $9 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A { \i [6] \i [7] \ni [2] } - connect \Y $8 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $10 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $8 - connect \Y $7 - end - process $group_3 - assign \t2 1'0 - assign \t2 $7 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire width 1 \t3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire width 1 $11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire width 1 $12 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_bool $13 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A { \i [5] \i [6] \i [7] \ni [3] } - connect \Y $12 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $14 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $12 - connect \Y $11 - end - process $group_4 - assign \t3 1'0 - assign \t3 $11 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire width 1 \t4 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire width 1 $15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire width 1 $16 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_bool $17 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A { \i [4] \i [5] \i [6] \i [7] \ni [4] } - connect \Y $16 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $18 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $16 - connect \Y $15 - end - process $group_5 - assign \t4 1'0 - assign \t4 $15 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire width 1 \t5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" 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$reduce_bool $25 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A { \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [6] } - connect \Y $24 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $26 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $24 - connect \Y $23 - end - process $group_7 - assign \t6 1'0 - assign \t6 $23 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire width 1 \t7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire width 1 $27 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire width 1 $28 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_bool $29 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A { \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [7] } - connect \Y $28 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $30 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $28 - connect \Y $27 - end - process $group_8 - assign \t7 1'0 - assign \t7 $27 - sync init - end - process $group_9 - assign \o 8'00000000 - assign \o { \t0 \t1 \t2 \t3 \t4 \t5 \t6 \t7 } - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" - wire width 1 \en_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" - wire width 1 $31 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" - cell $reduce_bool $32 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \o - connect \Y $31 - end - process $group_10 - assign \en_o 1'0 - assign \en_o $31 - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.dec_ALU.dec_cr_in" -module \dec_cr_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:485" - wire width 32 input 0 \insn_in - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:484" - wire width 3 input 1 \sel_in - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 7 input 2 \ALU_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 5 input 3 \ALU_BB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 5 input 4 \ALU_BA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 5 input 5 \ALU_BT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 8 input 6 \ALU_FXM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 5 input 7 \ALU_BI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 5 input 8 \ALU_BC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 3 input 9 \X_BFA - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" - wire width 8 \ppick_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" - wire width 8 \ppick_o - cell \ppick \ppick - connect \i \ppick_i - connect \o \ppick_o - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \cr_bitfield_ok - process $group_0 - assign \cr_bitfield_ok 1'0 - assign \cr_bitfield_ok 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" - switch \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" - attribute \nmigen.decoding "NONE/0" - case 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:505" - attribute \nmigen.decoding "CR0/1" - case 3'001 - assign \cr_bitfield_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:508" - attribute \nmigen.decoding "BI/2" - case 3'010 - assign \cr_bitfield_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:511" - attribute \nmigen.decoding "BFA/3" - case 3'011 - assign \cr_bitfield_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:514" - attribute \nmigen.decoding "BA_BB/4" - case 3'100 - assign \cr_bitfield_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:521" - attribute \nmigen.decoding "BC/5" - case 3'101 - assign \cr_bitfield_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:524" - attribute \nmigen.decoding "WHOLE_REG/6" - case 3'110 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \cr_bitfield_b_ok - process $group_1 - assign \cr_bitfield_b_ok 1'0 - assign \cr_bitfield_b_ok 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" - switch \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" - attribute \nmigen.decoding "NONE/0" - case 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:505" - attribute \nmigen.decoding "CR0/1" - case 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:508" - attribute \nmigen.decoding "BI/2" - case 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:511" - attribute \nmigen.decoding "BFA/3" - case 3'011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:514" - attribute \nmigen.decoding "BA_BB/4" - case 3'100 - assign \cr_bitfield_b_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:521" - attribute \nmigen.decoding "BC/5" - case 3'101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:524" - attribute \nmigen.decoding "WHOLE_REG/6" - case 3'110 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \cr_fxm_ok - process $group_2 - assign \cr_fxm_ok 1'0 - assign \cr_fxm_ok 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" - switch \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" - attribute \nmigen.decoding "NONE/0" - case 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:505" - attribute \nmigen.decoding "CR0/1" - case 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:508" - attribute \nmigen.decoding "BI/2" - case 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:511" - attribute \nmigen.decoding "BFA/3" - case 3'011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:514" - attribute \nmigen.decoding "BA_BB/4" - case 3'100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:521" - attribute \nmigen.decoding "BC/5" - case 3'101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:524" - attribute \nmigen.decoding "WHOLE_REG/6" - case 3'110 - assign \cr_fxm_ok 1'1 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 3 \cr_bitfield - process $group_3 - assign \cr_bitfield 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" - switch \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" - attribute \nmigen.decoding "NONE/0" - case 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:505" - attribute \nmigen.decoding "CR0/1" - case 3'001 - assign \cr_bitfield 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:508" - attribute \nmigen.decoding "BI/2" - case 3'010 - assign \cr_bitfield \ALU_BI [4:2] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:511" - attribute \nmigen.decoding "BFA/3" - case 3'011 - assign \cr_bitfield \X_BFA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:514" - attribute \nmigen.decoding "BA_BB/4" - case 3'100 - assign \cr_bitfield \ALU_BA [4:2] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:521" - attribute \nmigen.decoding "BC/5" - case 3'101 - assign \cr_bitfield \ALU_BC [4:2] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:524" - attribute \nmigen.decoding "WHOLE_REG/6" - case 3'110 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 3 \cr_bitfield_b - process $group_4 - assign \cr_bitfield_b 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" - switch \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" - attribute \nmigen.decoding "NONE/0" - case 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:505" - attribute \nmigen.decoding "CR0/1" - case 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:508" - attribute \nmigen.decoding "BI/2" - case 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:511" - attribute \nmigen.decoding "BFA/3" - case 3'011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:514" - attribute \nmigen.decoding "BA_BB/4" - case 3'100 - assign \cr_bitfield_b \ALU_BB [4:2] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:521" - attribute \nmigen.decoding "BC/5" - case 3'101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:524" - attribute \nmigen.decoding "WHOLE_REG/6" - case 3'110 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 3 \cr_bitfield_o - process $group_5 - assign \cr_bitfield_o 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" - switch \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" - attribute \nmigen.decoding "NONE/0" - case 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:505" - attribute \nmigen.decoding "CR0/1" - case 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:508" - attribute \nmigen.decoding "BI/2" - case 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:511" - attribute \nmigen.decoding "BFA/3" - case 3'011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:514" - attribute \nmigen.decoding "BA_BB/4" - case 3'100 - assign \cr_bitfield_o \ALU_BT [4:2] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:521" - attribute \nmigen.decoding "BC/5" - case 3'101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:524" - attribute \nmigen.decoding "WHOLE_REG/6" - case 3'110 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \cr_bitfield_o_ok - process $group_6 - assign \cr_bitfield_o_ok 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" - switch \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" - attribute \nmigen.decoding "NONE/0" - case 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:505" - attribute \nmigen.decoding "CR0/1" - case 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:508" - attribute \nmigen.decoding "BI/2" - case 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:511" - attribute \nmigen.decoding "BFA/3" - case 3'011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:514" - attribute \nmigen.decoding "BA_BB/4" - case 3'100 - assign \cr_bitfield_o_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:521" - attribute \nmigen.decoding "BC/5" - case 3'101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:524" - attribute \nmigen.decoding "WHOLE_REG/6" - case 3'110 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:526" - wire width 1 \move_one - process $group_7 - assign \move_one 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" - switch \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" - attribute \nmigen.decoding "NONE/0" - case 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:505" - attribute \nmigen.decoding "CR0/1" - case 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:508" - attribute \nmigen.decoding "BI/2" - case 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:511" - attribute \nmigen.decoding "BFA/3" - case 3'011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:514" - attribute \nmigen.decoding "BA_BB/4" - case 3'100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:521" - attribute \nmigen.decoding "BC/5" - case 3'101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:524" - attribute \nmigen.decoding "WHOLE_REG/6" - case 3'110 - assign \move_one \insn_in [20] - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" - cell $eq $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A \ALU_internal_op - connect \B 7'0101101 - connect \Y $1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" - wire width 1 $3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" - cell $and $4 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $1 - connect \B \move_one - connect \Y $3 - end - process $group_8 - assign \ppick_i 8'00000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" - switch \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" - attribute \nmigen.decoding "NONE/0" - case 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:505" - attribute \nmigen.decoding "CR0/1" - case 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:508" - attribute \nmigen.decoding "BI/2" - case 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:511" - attribute \nmigen.decoding "BFA/3" - case 3'011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:514" - attribute \nmigen.decoding "BA_BB/4" - case 3'100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:521" - attribute \nmigen.decoding "BC/5" - case 3'101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:524" - attribute \nmigen.decoding "WHOLE_REG/6" - case 3'110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" - switch { $3 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" - case 1'1 - assign \ppick_i \ALU_FXM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532" - case - end - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 8 \cr_fxm - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" - wire width 1 $5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" - cell $eq $6 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A \ALU_internal_op - connect \B 7'0101101 - connect \Y $5 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" - wire width 1 $7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" - cell $and $8 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $5 - connect \B \move_one - connect \Y $7 - end - process $group_9 - assign \cr_fxm 8'00000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" - switch \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" - attribute \nmigen.decoding "NONE/0" - case 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:505" - attribute \nmigen.decoding "CR0/1" - case 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:508" - attribute \nmigen.decoding "BI/2" - case 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:511" - attribute \nmigen.decoding "BFA/3" - case 3'011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:514" - attribute \nmigen.decoding "BA_BB/4" - case 3'100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:521" - attribute \nmigen.decoding "BC/5" - case 3'101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:524" - attribute \nmigen.decoding "WHOLE_REG/6" - case 3'110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" - switch { $7 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" - case 1'1 - assign \cr_fxm \ppick_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532" - case - assign \cr_fxm 8'11111111 - end - end - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.dec_ALU.dec_cr_out.ppick" -module \ppick$136 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" - wire width 8 input 0 \i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" - wire width 1 output 1 \en_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" - wire width 8 output 2 \o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:49" - wire width 8 \ni - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" - wire width 8 $1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" - cell $not $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \Y_WIDTH 8 - connect \A { \i [0] \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] } - connect \Y $1 - end - process $group_0 - assign \ni 8'00000000 - assign \ni $1 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire width 1 \t0 - process $group_1 - assign \t0 1'0 - assign \t0 \i [7] - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire width 1 \t1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire width 1 $3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire width 1 $4 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_bool $5 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A { \i [7] \ni [1] } - connect \Y $4 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $6 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $4 - connect \Y $3 - end - process $group_2 - assign \t1 1'0 - assign \t1 $3 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire width 1 \t2 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire width 1 $7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire width 1 $8 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_bool $9 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A { \i [6] \i [7] \ni [2] } - connect \Y $8 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $10 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $8 - connect \Y $7 - end - process $group_3 - assign \t2 1'0 - assign \t2 $7 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire width 1 \t3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire width 1 $11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire width 1 $12 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_bool $13 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A { \i [5] \i [6] \i [7] \ni [3] } - connect \Y $12 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $14 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $12 - connect \Y $11 - end - process $group_4 - assign \t3 1'0 - assign \t3 $11 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire width 1 \t4 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire width 1 $15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire width 1 $16 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_bool $17 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A { \i [4] \i [5] \i [6] \i [7] \ni [4] } - connect \Y $16 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $18 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $16 - connect \Y $15 - end - process $group_5 - assign \t4 1'0 - assign \t4 $15 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire width 1 \t5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire width 1 $19 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire width 1 $20 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_bool $21 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \Y_WIDTH 1 - connect \A { \i [3] \i [4] \i [5] \i [6] \i [7] \ni [5] } - connect \Y $20 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $22 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $20 - connect \Y $19 - end - process $group_6 - assign \t5 1'0 - assign \t5 $19 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire width 1 \t6 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire width 1 $23 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire width 1 $24 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_bool $25 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A { \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [6] } - connect \Y $24 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $26 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $24 - connect \Y $23 - end - process $group_7 - assign \t6 1'0 - assign \t6 $23 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire width 1 \t7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire width 1 $27 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire width 1 $28 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_bool $29 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A { \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [7] } - connect \Y $28 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $30 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $28 - connect \Y $27 - end - process $group_8 - assign \t7 1'0 - assign \t7 $27 - sync init - end - process $group_9 - assign \o 8'00000000 - assign \o { \t0 \t1 \t2 \t3 \t4 \t5 \t6 \t7 } - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" - wire width 1 $31 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" - cell $reduce_bool $32 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \o - connect \Y $31 - end - process $group_10 - assign \en_o 1'0 - assign \en_o $31 - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.dec_ALU.dec_cr_out" -module \dec_cr_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:550" - wire width 32 input 0 \insn_in - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:549" - wire width 3 input 1 \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:548" - wire width 1 input 2 \rc_in - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 7 input 3 \ALU_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 4 \cr_bitfield_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 8 input 5 \ALU_FXM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 3 input 6 \X_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 input 7 \XL_BT - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" - wire width 8 \ppick_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" - wire width 1 \ppick_en_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" - wire width 8 \ppick_o - cell \ppick$136 \ppick - connect \i \ppick_i - connect \en_o \ppick_en_o - connect \o \ppick_o - end - process $group_0 - assign \cr_bitfield_ok 1'0 - assign \cr_bitfield_ok 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:563" - switch \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:564" - attribute \nmigen.decoding "NONE/0" - case 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:566" - attribute \nmigen.decoding "CR0/1" - case 3'001 - assign \cr_bitfield_ok \rc_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:569" - attribute \nmigen.decoding "BF/2" - case 3'010 - assign \cr_bitfield_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:572" - attribute \nmigen.decoding "BT/3" - case 3'011 - assign \cr_bitfield_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:575" - attribute \nmigen.decoding "WHOLE_REG/4" - case 3'100 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \cr_fxm_ok - process $group_1 - assign \cr_fxm_ok 1'0 - assign \cr_fxm_ok 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:563" - switch \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:564" - attribute \nmigen.decoding "NONE/0" - case 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:566" - attribute \nmigen.decoding "CR0/1" - case 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:569" - attribute \nmigen.decoding "BF/2" - case 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:572" - attribute \nmigen.decoding "BT/3" - case 3'011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:575" - attribute \nmigen.decoding "WHOLE_REG/4" - case 3'100 - assign \cr_fxm_ok 1'1 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 3 \cr_bitfield - process $group_2 - assign \cr_bitfield 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:563" - switch \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:564" - attribute \nmigen.decoding "NONE/0" - case 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:566" - attribute \nmigen.decoding "CR0/1" - case 3'001 - assign \cr_bitfield 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:569" - attribute \nmigen.decoding "BF/2" - case 3'010 - assign \cr_bitfield \X_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:572" - attribute \nmigen.decoding "BT/3" - case 3'011 - assign \cr_bitfield \XL_BT [4:2] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:575" - attribute \nmigen.decoding "WHOLE_REG/4" - case 3'100 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:577" - wire width 1 \move_one - process $group_3 - assign \move_one 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:563" - switch \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:564" - attribute \nmigen.decoding "NONE/0" - case 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:566" - attribute \nmigen.decoding "CR0/1" - case 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:569" - attribute \nmigen.decoding "BF/2" - case 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:572" - attribute \nmigen.decoding "BT/3" - case 3'011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:575" - attribute \nmigen.decoding "WHOLE_REG/4" - case 3'100 - assign \move_one \insn_in [20] - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:579" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:579" - cell $eq $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A \ALU_internal_op - connect \B 7'0110000 - connect \Y $1 - end - process $group_4 - assign \ppick_i 8'00000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:563" - switch \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:564" - attribute \nmigen.decoding "NONE/0" - case 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:566" - attribute \nmigen.decoding "CR0/1" - case 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:569" - attribute \nmigen.decoding "BF/2" - case 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:572" - attribute \nmigen.decoding "BT/3" - case 3'011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:575" - attribute \nmigen.decoding "WHOLE_REG/4" - case 3'100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:579" - switch { $1 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:579" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:580" - switch { \move_one } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:580" - case 1'1 - assign \ppick_i \ALU_FXM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:587" - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:589" - case - end - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 8 \cr_fxm - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:579" - wire width 1 $3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:579" - cell $eq $4 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A \ALU_internal_op - connect \B 7'0110000 - connect \Y $3 - end - process $group_5 - assign \cr_fxm 8'00000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:563" - switch \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:564" - attribute \nmigen.decoding "NONE/0" - case 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:566" - attribute \nmigen.decoding "CR0/1" - case 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:569" - attribute \nmigen.decoding "BF/2" - case 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:572" - attribute \nmigen.decoding "BT/3" - case 3'011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:575" - attribute \nmigen.decoding "WHOLE_REG/4" - case 3'100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:579" - switch { $3 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:579" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:580" - switch { \move_one } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:580" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:583" - switch { \ppick_en_o } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:583" - case 1'1 - assign \cr_fxm \ppick_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:585" - case - assign \cr_fxm 8'00000001 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:587" - case - assign \cr_fxm \ALU_FXM - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:589" - case - assign \cr_fxm 8'11111111 - end - end - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.dec_ALU.dec_ai" -module \dec_ai - attribute \enum_base_type "In1Sel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "RA" - attribute \enum_value_010 "RA_OR_ZERO" - attribute \enum_value_011 "SPR" - attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:148" - wire width 3 input 0 \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:149" - wire width 1 output 1 \immz_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 5 input 2 \ALU_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:156" - wire width 5 \ra - process $group_0 - assign \ra 5'00000 - assign \ra \ALU_RA - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:158" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:158" - cell $eq $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \sel_in - connect \B 3'010 - connect \Y $1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:158" - wire width 1 $3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:158" - cell $eq $4 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \ra - connect \B 5'00000 - connect \Y $3 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:158" - wire width 1 $5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:158" - cell $and $6 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $1 - connect \B $3 - connect \Y $5 - end - process $group_1 - assign \immz_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:158" - switch { $5 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:158" - case 1'1 - assign \immz_out 1'1 - end - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.dec_ALU.dec_bi" -module \dec_bi - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:216" - wire width 4 input 0 \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 output 1 \imm_b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 2 \imm_b_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 16 input 3 \ALU_SI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 16 input 4 \ALU_UI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 5 input 5 \ALU_SH32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 6 input 6 \ALU_sh - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 24 input 7 \ALU_LI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 14 input 8 \ALU_BD - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 14 input 9 \ALU_DS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 64 $1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - cell $pos $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 16 - parameter \Y_WIDTH 64 - connect \A \ALU_UI - connect \Y $1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:229" - wire width 16 \si - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:234" - wire width 32 \si_hi - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:241" - wire width 64 $3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:239" - wire width 16 \ui - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:241" - wire width 47 $4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:241" - cell $sshl $5 - parameter \A_SIGNED 0 - parameter \A_WIDTH 16 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 47 - connect \A \ui - connect \B 5'10000 - connect \Y $4 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:241" - cell $pos $6 - parameter \A_SIGNED 0 - parameter \A_WIDTH 47 - parameter \Y_WIDTH 64 - connect \A $4 - connect \Y $3 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" - wire width 26 \li - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:249" - wire width 16 \bd - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:254" - wire width 16 \ds - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:259" - wire width 64 $7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:259" - cell $not $8 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \Y_WIDTH 64 - connect \A 64'0000000000000000000000000000000000000000000000000000000000000000 - connect \Y $7 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 64 $9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - cell $pos $10 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \Y_WIDTH 64 - connect \A \ALU_sh - connect \Y $9 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 64 $11 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - cell $pos $12 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \Y_WIDTH 64 - connect \A \ALU_SH32 - connect \Y $11 - end - process $group_0 - assign \imm_b 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:224" - switch \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:225" - attribute \nmigen.decoding "CONST_UI/2" - case 4'0010 - assign \imm_b $1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:228" - attribute \nmigen.decoding "CONST_SI/3" - case 4'0011 - assign \imm_b { { \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] } \si } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:233" - attribute \nmigen.decoding "CONST_SI_HI/5" - case 4'0101 - assign \imm_b { { \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] } \si_hi } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:238" - attribute \nmigen.decoding "CONST_UI_HI/4" - case 4'0100 - assign \imm_b $3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:243" - attribute \nmigen.decoding "CONST_LI/6" - case 4'0110 - assign \imm_b { { \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] } \li } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:248" - attribute \nmigen.decoding "CONST_BD/7" - case 4'0111 - assign \imm_b { { \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] } \bd } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:253" - attribute \nmigen.decoding "CONST_DS/8" - case 4'1000 - assign \imm_b { { \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] } \ds } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:258" - attribute \nmigen.decoding "CONST_M1/9" - case 4'1001 - assign \imm_b $7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" - attribute \nmigen.decoding "CONST_SH/10" - case 4'1010 - assign \imm_b $9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:264" - attribute \nmigen.decoding "CONST_SH32/11" - case 4'1011 - assign \imm_b $11 - end - sync init - end - process $group_1 - assign \imm_b_ok 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:224" - switch \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:225" - attribute \nmigen.decoding "CONST_UI/2" - case 4'0010 - assign \imm_b_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:228" - attribute \nmigen.decoding "CONST_SI/3" - case 4'0011 - assign \imm_b_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:233" - attribute \nmigen.decoding "CONST_SI_HI/5" - case 4'0101 - assign \imm_b_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:238" - attribute \nmigen.decoding "CONST_UI_HI/4" - case 4'0100 - assign \imm_b_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:243" - attribute \nmigen.decoding "CONST_LI/6" - case 4'0110 - assign \imm_b_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:248" - attribute \nmigen.decoding "CONST_BD/7" - case 4'0111 - assign \imm_b_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:253" - attribute \nmigen.decoding "CONST_DS/8" - case 4'1000 - assign \imm_b_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:258" - attribute \nmigen.decoding "CONST_M1/9" - case 4'1001 - assign \imm_b_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" - attribute \nmigen.decoding "CONST_SH/10" - case 4'1010 - assign \imm_b_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:264" - attribute \nmigen.decoding "CONST_SH32/11" - case 4'1011 - assign \imm_b_ok 1'1 - end - sync init - end - process $group_2 - assign \si 16'0000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:224" - switch \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:225" - attribute \nmigen.decoding "CONST_UI/2" - case 4'0010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:228" - attribute \nmigen.decoding "CONST_SI/3" - case 4'0011 - assign \si \ALU_SI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:233" - attribute \nmigen.decoding "CONST_SI_HI/5" - case 4'0101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:238" - attribute \nmigen.decoding "CONST_UI_HI/4" - case 4'0100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:243" - attribute \nmigen.decoding "CONST_LI/6" - case 4'0110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:248" - attribute \nmigen.decoding "CONST_BD/7" - case 4'0111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:253" - attribute \nmigen.decoding "CONST_DS/8" - case 4'1000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:258" - attribute \nmigen.decoding "CONST_M1/9" - case 4'1001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" - attribute \nmigen.decoding "CONST_SH/10" - case 4'1010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:264" - attribute \nmigen.decoding "CONST_SH32/11" - case 4'1011 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:235" - wire width 47 $13 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:235" - wire width 47 $14 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:235" - cell $sshl $15 - parameter \A_SIGNED 0 - parameter \A_WIDTH 16 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 47 - connect \A \ALU_SI - connect \B 5'10000 - connect \Y $14 - end - connect $13 $14 - process $group_3 - assign \si_hi 32'00000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:224" - switch \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:225" - attribute \nmigen.decoding "CONST_UI/2" - case 4'0010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:228" - attribute \nmigen.decoding "CONST_SI/3" - case 4'0011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:233" - attribute \nmigen.decoding "CONST_SI_HI/5" - case 4'0101 - assign \si_hi $13 [31:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:238" - attribute \nmigen.decoding "CONST_UI_HI/4" - case 4'0100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:243" - attribute \nmigen.decoding "CONST_LI/6" - case 4'0110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:248" - attribute \nmigen.decoding "CONST_BD/7" - case 4'0111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:253" - attribute \nmigen.decoding "CONST_DS/8" - case 4'1000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:258" - attribute \nmigen.decoding "CONST_M1/9" - case 4'1001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" - attribute \nmigen.decoding "CONST_SH/10" - case 4'1010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:264" - attribute \nmigen.decoding "CONST_SH32/11" - case 4'1011 - end - sync init - end - process $group_4 - assign \ui 16'0000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:224" - switch \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:225" - attribute \nmigen.decoding "CONST_UI/2" - case 4'0010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:228" - attribute \nmigen.decoding "CONST_SI/3" - case 4'0011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:233" - attribute \nmigen.decoding "CONST_SI_HI/5" - case 4'0101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:238" - attribute \nmigen.decoding "CONST_UI_HI/4" - case 4'0100 - assign \ui \ALU_UI - attribute \src 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\enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 4 \dec_ALU_ldst_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \dec_ALU_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \dec_ALU_inv_out - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 2 \dec_ALU_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \dec_ALU_cry_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \dec_ALU_is_32b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \dec_ALU_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 5 \dec_ALU_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 16 \dec_ALU_SI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 16 \dec_ALU_UI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 5 \dec_ALU_SH32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 6 \dec_ALU_sh - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 24 \dec_ALU_LI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 1 \dec_ALU_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 1 \dec_ALU_OE - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 14 \dec_ALU_BD - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 5 \dec_ALU_BB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 5 \dec_ALU_BA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 5 \dec_ALU_BT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 8 \dec_ALU_FXM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 5 \dec_ALU_BI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 14 \dec_ALU_DS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 5 \dec_ALU_BC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 3 \dec_X_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 3 \dec_X_BFA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \dec_XL_BT - cell \dec \dec - connect \raw_opcode_in \raw_opcode_in - connect \bigendian \bigendian - connect \opcode_in \dec_opcode_in - connect \ALU_rc_sel \dec_ALU_rc_sel - connect \ALU_cr_in \dec_ALU_cr_in - connect \ALU_cr_out \dec_ALU_cr_out - connect \ALU_internal_op \dec_ALU_internal_op - connect \ALU_function_unit \dec_ALU_function_unit - connect \ALU_in1_sel \dec_ALU_in1_sel - connect \ALU_in2_sel \dec_ALU_in2_sel - connect \ALU_ldst_len \dec_ALU_ldst_len - connect \ALU_inv_a \dec_ALU_inv_a - connect \ALU_inv_out \dec_ALU_inv_out - connect \ALU_cry_in \dec_ALU_cry_in - connect \ALU_cry_out \dec_ALU_cry_out - connect \ALU_is_32b \dec_ALU_is_32b - connect \ALU_sgn \dec_ALU_sgn - connect \ALU_RA \dec_ALU_RA - connect \ALU_SI \dec_ALU_SI - connect \ALU_UI \dec_ALU_UI - connect \ALU_SH32 \dec_ALU_SH32 - connect \ALU_sh \dec_ALU_sh - connect \ALU_LI \dec_ALU_LI - connect \ALU_Rc \dec_ALU_Rc - connect \ALU_OE \dec_ALU_OE - connect \ALU_BD \dec_ALU_BD - connect \ALU_BB \dec_ALU_BB - connect \ALU_BA \dec_ALU_BA - connect \ALU_BT \dec_ALU_BT - connect \ALU_FXM \dec_ALU_FXM - connect \ALU_BI \dec_ALU_BI - connect \ALU_DS \dec_ALU_DS - connect \ALU_BC \dec_ALU_BC - connect \X_BF \dec_X_BF - connect \X_BFA \dec_X_BFA - connect \XL_BT \dec_XL_BT - end - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:404" - wire width 2 \dec_rc_sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \dec_rc_rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \dec_rc_rc_ok - cell \dec_rc \dec_rc - connect \sel_in \dec_rc_sel_in - connect \rc \dec_rc_rc - connect \rc_ok \dec_rc_rc_ok - connect \ALU_Rc \dec_ALU_Rc - end - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:441" - wire width 2 \dec_oe_sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \dec_oe_oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \dec_oe_oe_ok - cell \dec_oe \dec_oe - connect \sel_in \dec_oe_sel_in - connect \ALU_internal_op \dec_ALU_internal_op - connect \oe \dec_oe_oe - connect \oe_ok \dec_oe_oe_ok - connect \ALU_OE \dec_ALU_OE - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:485" - wire width 32 \dec_cr_in_insn_in - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:484" - wire width 3 \dec_cr_in_sel_in - cell \dec_cr_in \dec_cr_in - connect \insn_in \dec_cr_in_insn_in - connect \sel_in \dec_cr_in_sel_in - connect \ALU_internal_op \dec_ALU_internal_op - connect \ALU_BB \dec_ALU_BB - connect \ALU_BA \dec_ALU_BA - connect \ALU_BT \dec_ALU_BT - connect \ALU_FXM \dec_ALU_FXM - connect \ALU_BI \dec_ALU_BI - connect \ALU_BC \dec_ALU_BC - connect \X_BFA \dec_X_BFA - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:550" - wire width 32 \dec_cr_out_insn_in - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:549" - wire width 3 \dec_cr_out_sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:548" - wire width 1 \dec_cr_out_rc_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \dec_cr_out_cr_bitfield_ok - cell \dec_cr_out \dec_cr_out - connect \insn_in \dec_cr_out_insn_in - connect \sel_in \dec_cr_out_sel_in - connect \rc_in \dec_cr_out_rc_in - connect \ALU_internal_op \dec_ALU_internal_op - connect \cr_bitfield_ok \dec_cr_out_cr_bitfield_ok - connect \ALU_FXM \dec_ALU_FXM - connect \X_BF \dec_X_BF - connect \XL_BT \dec_XL_BT - end - attribute \enum_base_type "In1Sel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "RA" - attribute \enum_value_010 "RA_OR_ZERO" - attribute \enum_value_011 "SPR" - attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:148" - wire width 3 \dec_ai_sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:149" - wire width 1 \dec_ai_immz_out - cell \dec_ai \dec_ai - connect \sel_in \dec_ai_sel_in - connect \immz_out \dec_ai_immz_out - connect \ALU_RA \dec_ALU_RA - end - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:216" - wire width 4 \dec_bi_sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 \dec_bi_imm_b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \dec_bi_imm_b_ok - cell \dec_bi \dec_bi - connect \sel_in \dec_bi_sel_in - connect \imm_b \dec_bi_imm_b - connect \imm_b_ok \dec_bi_imm_b_ok - connect \ALU_SI \dec_ALU_SI - connect \ALU_UI \dec_ALU_UI - connect \ALU_SH32 \dec_ALU_SH32 - connect \ALU_sh \dec_ALU_sh - connect \ALU_LI \dec_ALU_LI - connect \ALU_BD \dec_ALU_BD - connect \ALU_DS \dec_ALU_DS - end - process $group_0 - assign \ALU_ALU__insn 32'00000000000000000000000000000000 - assign \ALU_ALU__insn \dec_opcode_in - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:405" - wire width 32 \insn_in - process $group_1 - assign \insn_in 32'00000000000000000000000000000000 - assign \insn_in \dec_opcode_in - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:442" - wire width 32 \insn_in$1 - process $group_2 - assign \insn_in$1 32'00000000000000000000000000000000 - assign \insn_in$1 \dec_opcode_in - sync init - end - process $group_3 - assign \dec_cr_in_insn_in 32'00000000000000000000000000000000 - assign \dec_cr_in_insn_in \dec_opcode_in - sync init - end - process $group_4 - assign \dec_cr_out_insn_in 32'00000000000000000000000000000000 - assign \dec_cr_out_insn_in \dec_opcode_in - sync init - end - process $group_5 - assign \dec_rc_sel_in 2'00 - assign \dec_rc_sel_in \dec_ALU_rc_sel - sync init - end - process $group_6 - assign \dec_oe_sel_in 2'00 - assign \dec_oe_sel_in \dec_ALU_rc_sel - sync init - end - process $group_7 - assign \dec_cr_in_sel_in 3'000 - assign \dec_cr_in_sel_in \dec_ALU_cr_in - sync init - end - process $group_8 - assign \dec_cr_out_sel_in 3'000 - assign \dec_cr_out_sel_in \dec_ALU_cr_out - sync init - end - process $group_9 - assign \dec_cr_out_rc_in 1'0 - assign \dec_cr_out_rc_in \dec_rc_rc - sync init - end - process $group_10 - assign \ALU_ALU__insn_type 7'0000000 - assign \ALU_ALU__insn_type \dec_ALU_internal_op - sync init - end - process $group_11 - assign \ALU_ALU__fn_unit 11'00000000000 - assign \ALU_ALU__fn_unit \dec_ALU_function_unit - sync init - end - process $group_12 - assign \dec_ai_sel_in 3'000 - assign \dec_ai_sel_in \dec_ALU_in1_sel - sync init - end - process $group_13 - assign \ALU_ALU__zero_a 1'0 - assign \ALU_ALU__zero_a \dec_ai_immz_out - sync init - end - process $group_14 - assign \dec_bi_sel_in 4'0000 - assign \dec_bi_sel_in \dec_ALU_in2_sel - sync init - end - process $group_15 - assign \ALU_ALU__imm_data__data 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \ALU_ALU__imm_data__ok 1'0 - assign { \ALU_ALU__imm_data__ok \ALU_ALU__imm_data__data } { \dec_bi_imm_b_ok \dec_bi_imm_b } - sync init - end - process $group_17 - assign \ALU_ALU__rc__rc 1'0 - assign \ALU_ALU__rc__ok 1'0 - assign { \ALU_ALU__rc__ok \ALU_ALU__rc__rc } { \dec_rc_rc_ok \dec_rc_rc } - sync init - end - process $group_19 - assign \ALU_ALU__oe__oe 1'0 - assign \ALU_ALU__oe__ok 1'0 - assign { \ALU_ALU__oe__ok \ALU_ALU__oe__oe } { \dec_oe_oe_ok \dec_oe_oe } - sync init - end - process $group_21 - assign \ALU_ALU__write_cr0 1'0 - assign \ALU_ALU__write_cr0 \dec_cr_out_cr_bitfield_ok - sync init - end - process $group_22 - assign \ALU_ALU__data_len 4'0000 - assign \ALU_ALU__data_len \dec_ALU_ldst_len - sync init - end - process $group_23 - assign \ALU_ALU__invert_in 1'0 - assign \ALU_ALU__invert_in \dec_ALU_inv_a - sync init - end - process $group_24 - assign \ALU_ALU__invert_out 1'0 - assign \ALU_ALU__invert_out \dec_ALU_inv_out - sync init - end - process $group_25 - assign \ALU_ALU__input_carry 2'00 - assign \ALU_ALU__input_carry \dec_ALU_cry_in - sync init - end - process $group_26 - assign \ALU_ALU__output_carry 1'0 - assign \ALU_ALU__output_carry \dec_ALU_cry_out - sync init - end - process $group_27 - assign \ALU_ALU__is_32bit 1'0 - assign \ALU_ALU__is_32bit \dec_ALU_is_32b - sync init - end - process $group_28 - assign \ALU_ALU__is_signed 1'0 - assign \ALU_ALU__is_signed \dec_ALU_sgn - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.dec_CR.dec.CR_dec19" -module \CR_dec19 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" - wire width 32 input 0 \opcode_in - attribute \enum_base_type "Function" - attribute \enum_value_00000000000 "NONE" - attribute \enum_value_00000000010 "ALU" - attribute \enum_value_00000000100 "LDST" - attribute \enum_value_00000001000 "SHIFT_ROT" - attribute \enum_value_00000010000 "LOGICAL" - attribute \enum_value_00000100000 "BRANCH" - attribute \enum_value_00001000000 "CR" - attribute \enum_value_00010000000 "TRAP" - attribute \enum_value_00100000000 "MUL" - attribute \enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 11 output 1 \CR_function_unit - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 7 output 2 \CR_internal_op - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 output 3 \CR_cr_in - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 output 4 \CR_cr_out - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 2 output 5 \CR_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:308" - wire width 10 \opcode_switch - process $group_0 - assign \opcode_switch 10'0000000000 - assign \opcode_switch \opcode_in [10:1] - sync init - end - process $group_1 - assign \CR_function_unit 11'00000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 10'0000000000 - assign \CR_function_unit 11'00001000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 10'0100000001 - assign \CR_function_unit 11'00001000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 10'0010000001 - assign \CR_function_unit 11'00001000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 10'0100100001 - assign \CR_function_unit 11'00001000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 10'0011100001 - assign \CR_function_unit 11'00001000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 10'0000100001 - assign \CR_function_unit 11'00001000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 10'0111000001 - assign \CR_function_unit 11'00001000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 10'0110100001 - assign \CR_function_unit 11'00001000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 10'0011000001 - assign \CR_function_unit 11'00001000000 - end - sync init - end - process $group_2 - assign \CR_internal_op 7'0000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 10'0000000000 - assign \CR_internal_op 7'0101010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 10'0100000001 - assign \CR_internal_op 7'1000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 10'0010000001 - assign \CR_internal_op 7'1000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 10'0100100001 - assign \CR_internal_op 7'1000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 10'0011100001 - assign \CR_internal_op 7'1000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 10'0000100001 - assign \CR_internal_op 7'1000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 10'0111000001 - assign \CR_internal_op 7'1000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 10'0110100001 - assign \CR_internal_op 7'1000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 10'0011000001 - assign \CR_internal_op 7'1000101 - end - sync init - end - process $group_3 - assign \CR_cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 10'0000000000 - assign \CR_cr_in 3'011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 10'0100000001 - assign \CR_cr_in 3'100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 10'0010000001 - assign \CR_cr_in 3'100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 10'0100100001 - assign \CR_cr_in 3'100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 10'0011100001 - assign \CR_cr_in 3'100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 10'0000100001 - assign \CR_cr_in 3'100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 10'0111000001 - assign \CR_cr_in 3'100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 10'0110100001 - assign \CR_cr_in 3'100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 10'0011000001 - assign \CR_cr_in 3'100 - end - sync init - end - process $group_4 - assign \CR_cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 10'0000000000 - assign \CR_cr_out 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 10'0100000001 - assign \CR_cr_out 3'011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 10'0010000001 - assign \CR_cr_out 3'011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 10'0100100001 - assign \CR_cr_out 3'011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 10'0011100001 - assign \CR_cr_out 3'011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 10'0000100001 - assign \CR_cr_out 3'011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 10'0111000001 - assign \CR_cr_out 3'011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 10'0110100001 - assign \CR_cr_out 3'011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 10'0011000001 - assign \CR_cr_out 3'011 - end - sync init - end - process $group_5 - assign \CR_rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 10'0000000000 - assign \CR_rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 10'0100000001 - assign \CR_rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 10'0010000001 - assign \CR_rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 10'0100100001 - assign \CR_rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 10'0011100001 - assign \CR_rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 10'0000100001 - assign \CR_rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 10'0111000001 - assign \CR_rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 10'0110100001 - assign \CR_rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 10'0011000001 - assign \CR_rc_sel 2'00 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:308" - wire width 5 \opcode_switch$1 - process $group_6 - assign \opcode_switch$1 5'00000 - assign \opcode_switch$1 \opcode_in [5:1] - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.dec_CR.dec.CR_dec30" -module \CR_dec30 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" - wire width 32 input 0 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:308" - wire width 4 \opcode_switch - process $group_0 - assign \opcode_switch 4'0000 - assign \opcode_switch \opcode_in [4:1] - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.dec_CR.dec.CR_dec31.CR_dec_sub10" -module \CR_dec_sub10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" - wire width 32 input 0 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:308" - wire width 5 \opcode_switch - process $group_0 - assign \opcode_switch 5'00000 - assign \opcode_switch \opcode_in [10:6] - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.dec_CR.dec.CR_dec31.CR_dec_sub28" -module \CR_dec_sub28 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" - wire width 32 input 0 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:308" - wire width 5 \opcode_switch - process $group_0 - assign \opcode_switch 5'00000 - assign \opcode_switch \opcode_in [10:6] - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.dec_CR.dec.CR_dec31.CR_dec_sub0" -module \CR_dec_sub0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" - wire width 32 input 0 \opcode_in - attribute \enum_base_type "Function" - attribute \enum_value_00000000000 "NONE" - attribute \enum_value_00000000010 "ALU" - attribute \enum_value_00000000100 "LDST" - attribute \enum_value_00000001000 "SHIFT_ROT" - attribute \enum_value_00000010000 "LOGICAL" - attribute \enum_value_00000100000 "BRANCH" - attribute \enum_value_00001000000 "CR" - attribute \enum_value_00010000000 "TRAP" - attribute \enum_value_00100000000 "MUL" - attribute \enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" - attribute \src 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attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute 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\enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 7 output 2 \CR_internal_op - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 output 3 \CR_cr_in - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 output 4 \CR_cr_out - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 2 output 5 \CR_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:308" - wire width 5 \opcode_switch - process $group_0 - assign \opcode_switch 5'00000 - assign \opcode_switch \opcode_in [10:6] - sync init - end - process $group_1 - assign \CR_function_unit 11'00000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00100 - assign \CR_function_unit 11'00001000000 - end - sync init - end - process $group_2 - assign \CR_internal_op 7'0000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00100 - assign \CR_internal_op 7'0111011 - end - sync init - end - process $group_3 - assign \CR_cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00100 - assign \CR_cr_in 3'011 - end - sync init - end - process $group_4 - assign \CR_cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00100 - assign \CR_cr_out 3'000 - end - sync init - end - process $group_5 - assign \CR_rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00100 - assign \CR_rc_sel 2'00 - end - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.dec_CR.dec.CR_dec31.CR_dec_sub26" -module \CR_dec_sub26 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" - wire width 32 input 0 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:308" - wire width 5 \opcode_switch - process $group_0 - assign \opcode_switch 5'00000 - assign \opcode_switch \opcode_in [10:6] - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.dec_CR.dec.CR_dec31.CR_dec_sub19" -module \CR_dec_sub19 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" - wire width 32 input 0 \opcode_in - attribute \enum_base_type "Function" - attribute \enum_value_00000000000 "NONE" - attribute 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process $group_1 - assign \CR_function_unit 11'00000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \CR_function_unit 11'00001000000 - end - sync init - end - process $group_2 - assign \CR_internal_op 7'0000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \CR_internal_op 7'0101101 - end - sync init - end - process $group_3 - assign \CR_cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \CR_cr_in 3'110 - end - sync init - end - process $group_4 - assign \CR_cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \CR_cr_out 3'000 - end - sync init - end - process $group_5 - assign \CR_rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \CR_rc_sel 2'00 - end - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.dec_CR.dec.CR_dec31.CR_dec_sub22" -module \CR_dec_sub22 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" - wire width 32 input 0 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:308" - wire width 5 \opcode_switch - process $group_0 - assign \opcode_switch 5'00000 - assign \opcode_switch \opcode_in [10:6] - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.dec_CR.dec.CR_dec31.CR_dec_sub9" -module \CR_dec_sub9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" - wire width 32 input 0 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:308" - wire width 5 \opcode_switch - process $group_0 - assign \opcode_switch 5'00000 - assign \opcode_switch \opcode_in [10:6] - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.dec_CR.dec.CR_dec31.CR_dec_sub11" -module \CR_dec_sub11 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" - wire width 32 input 0 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:308" - wire width 5 \opcode_switch - process $group_0 - assign \opcode_switch 5'00000 - assign \opcode_switch \opcode_in [10:6] - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.dec_CR.dec.CR_dec31.CR_dec_sub27" -module \CR_dec_sub27 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" - wire width 32 input 0 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:308" - wire width 5 \opcode_switch - process $group_0 - assign \opcode_switch 5'00000 - assign \opcode_switch \opcode_in [10:6] - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.dec_CR.dec.CR_dec31.CR_dec_sub15" -module \CR_dec_sub15 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" - wire width 32 input 0 \opcode_in - attribute \enum_base_type "Function" - attribute \enum_value_00000000000 "NONE" - attribute \enum_value_00000000010 "ALU" - attribute \enum_value_00000000100 "LDST" - attribute \enum_value_00000001000 "SHIFT_ROT" - attribute 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- attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 7 output 2 \CR_internal_op - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 output 3 \CR_cr_in - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 output 4 \CR_cr_out - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 2 output 5 \CR_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:308" - wire width 5 \opcode_switch - process $group_0 - assign \opcode_switch 5'00000 - assign \opcode_switch \opcode_in [10:6] - sync init - end - process $group_1 - assign \CR_function_unit 11'00000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \CR_function_unit 11'00001000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00001 - assign \CR_function_unit 11'00001000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00010 - assign \CR_function_unit 11'00001000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00011 - assign \CR_function_unit 11'00001000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00100 - assign \CR_function_unit 11'00001000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00101 - assign \CR_function_unit 11'00001000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00110 - assign \CR_function_unit 11'00001000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00111 - assign \CR_function_unit 11'00001000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01000 - assign \CR_function_unit 11'00001000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01001 - assign \CR_function_unit 11'00001000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01010 - assign \CR_function_unit 11'00001000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01011 - assign \CR_function_unit 11'00001000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01100 - assign \CR_function_unit 11'00001000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01101 - assign \CR_function_unit 11'00001000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01110 - assign \CR_function_unit 11'00001000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01111 - assign \CR_function_unit 11'00001000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10000 - assign \CR_function_unit 11'00001000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10001 - assign \CR_function_unit 11'00001000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10010 - assign \CR_function_unit 11'00001000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10011 - assign \CR_function_unit 11'00001000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10100 - assign \CR_function_unit 11'00001000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10101 - assign \CR_function_unit 11'00001000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10110 - assign \CR_function_unit 11'00001000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10111 - assign \CR_function_unit 11'00001000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11000 - assign \CR_function_unit 11'00001000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11001 - assign \CR_function_unit 11'00001000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11010 - assign \CR_function_unit 11'00001000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11011 - assign \CR_function_unit 11'00001000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11100 - assign \CR_function_unit 11'00001000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11101 - assign \CR_function_unit 11'00001000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11110 - assign \CR_function_unit 11'00001000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11111 - assign \CR_function_unit 11'00001000000 - end - sync init - end - process $group_2 - assign \CR_internal_op 7'0000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \CR_internal_op 7'0100011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00001 - assign \CR_internal_op 7'0100011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00010 - assign \CR_internal_op 7'0100011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00011 - assign \CR_internal_op 7'0100011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00100 - assign \CR_internal_op 7'0100011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00101 - assign \CR_internal_op 7'0100011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00110 - assign \CR_internal_op 7'0100011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00111 - assign \CR_internal_op 7'0100011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01000 - assign \CR_internal_op 7'0100011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01001 - assign \CR_internal_op 7'0100011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01010 - assign \CR_internal_op 7'0100011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01011 - assign \CR_internal_op 7'0100011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01100 - assign \CR_internal_op 7'0100011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01101 - assign \CR_internal_op 7'0100011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01110 - assign \CR_internal_op 7'0100011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01111 - assign \CR_internal_op 7'0100011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10000 - assign \CR_internal_op 7'0100011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10001 - assign \CR_internal_op 7'0100011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10010 - assign \CR_internal_op 7'0100011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10011 - assign \CR_internal_op 7'0100011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10100 - assign \CR_internal_op 7'0100011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10101 - assign \CR_internal_op 7'0100011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10110 - assign \CR_internal_op 7'0100011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10111 - assign \CR_internal_op 7'0100011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11000 - assign \CR_internal_op 7'0100011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11001 - assign \CR_internal_op 7'0100011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11010 - assign \CR_internal_op 7'0100011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11011 - assign \CR_internal_op 7'0100011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11100 - assign \CR_internal_op 7'0100011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11101 - assign \CR_internal_op 7'0100011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11110 - assign \CR_internal_op 7'0100011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11111 - assign \CR_internal_op 7'0100011 - end - sync init - end - process $group_3 - assign \CR_cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \CR_cr_in 3'101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00001 - assign \CR_cr_in 3'101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00010 - assign \CR_cr_in 3'101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00011 - assign \CR_cr_in 3'101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00100 - assign \CR_cr_in 3'101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00101 - assign \CR_cr_in 3'101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00110 - assign \CR_cr_in 3'101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00111 - assign \CR_cr_in 3'101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01000 - assign \CR_cr_in 3'101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01001 - assign \CR_cr_in 3'101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01010 - assign \CR_cr_in 3'101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01011 - assign \CR_cr_in 3'101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01100 - assign \CR_cr_in 3'101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01101 - assign \CR_cr_in 3'101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01110 - assign \CR_cr_in 3'101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01111 - assign \CR_cr_in 3'101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10000 - assign \CR_cr_in 3'101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10001 - assign \CR_cr_in 3'101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10010 - assign \CR_cr_in 3'101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10011 - assign \CR_cr_in 3'101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10100 - assign \CR_cr_in 3'101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10101 - assign \CR_cr_in 3'101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10110 - assign \CR_cr_in 3'101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10111 - assign \CR_cr_in 3'101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11000 - assign \CR_cr_in 3'101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11001 - assign \CR_cr_in 3'101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11010 - assign \CR_cr_in 3'101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11011 - assign \CR_cr_in 3'101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11100 - assign \CR_cr_in 3'101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11101 - assign \CR_cr_in 3'101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11110 - assign \CR_cr_in 3'101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11111 - assign \CR_cr_in 3'101 - end - sync init - end - process $group_4 - assign \CR_cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \CR_cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00001 - assign \CR_cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00010 - assign \CR_cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00011 - assign \CR_cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00100 - assign \CR_cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00101 - assign \CR_cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00110 - assign \CR_cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00111 - assign \CR_cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01000 - assign \CR_cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01001 - assign \CR_cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01010 - assign \CR_cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01011 - assign \CR_cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01100 - assign \CR_cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01101 - assign \CR_cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01110 - assign \CR_cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01111 - assign \CR_cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10000 - assign \CR_cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10001 - assign \CR_cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10010 - assign \CR_cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10011 - assign \CR_cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10100 - assign \CR_cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10101 - assign \CR_cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10110 - assign \CR_cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10111 - assign \CR_cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11000 - assign \CR_cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11001 - assign \CR_cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11010 - assign \CR_cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11011 - assign \CR_cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11100 - assign \CR_cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11101 - assign \CR_cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11110 - assign \CR_cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11111 - assign \CR_cr_out 3'000 - end - sync init - end - process $group_5 - assign \CR_rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \CR_rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00001 - assign \CR_rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00010 - assign \CR_rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00011 - assign \CR_rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00100 - assign \CR_rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00101 - assign \CR_rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00110 - assign \CR_rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00111 - assign \CR_rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01000 - assign \CR_rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01001 - assign \CR_rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01010 - assign \CR_rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01011 - assign \CR_rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01100 - assign \CR_rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01101 - assign \CR_rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01110 - assign \CR_rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01111 - assign \CR_rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10000 - assign \CR_rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10001 - assign \CR_rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10010 - assign \CR_rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10011 - assign \CR_rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10100 - assign \CR_rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10101 - assign \CR_rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10110 - assign \CR_rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10111 - assign \CR_rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11000 - assign \CR_rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11001 - assign \CR_rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11010 - assign \CR_rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11011 - assign \CR_rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11100 - assign \CR_rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11101 - assign \CR_rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11110 - assign \CR_rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11111 - assign \CR_rc_sel 2'00 - end - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.dec_CR.dec.CR_dec31.CR_dec_sub20" -module \CR_dec_sub20 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" - wire width 32 input 0 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:308" - wire width 5 \opcode_switch - process $group_0 - assign \opcode_switch 5'00000 - assign \opcode_switch \opcode_in [10:6] - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.dec_CR.dec.CR_dec31.CR_dec_sub21" -module \CR_dec_sub21 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" - wire width 32 input 0 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:308" - wire width 5 \opcode_switch - process $group_0 - assign \opcode_switch 5'00000 - assign \opcode_switch \opcode_in [10:6] - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.dec_CR.dec.CR_dec31.CR_dec_sub23" -module \CR_dec_sub23 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" - wire width 32 input 0 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:308" - wire width 5 \opcode_switch - process $group_0 - assign \opcode_switch 5'00000 - assign \opcode_switch \opcode_in [10:6] - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.dec_CR.dec.CR_dec31.CR_dec_sub16" -module \CR_dec_sub16 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" - wire width 32 input 0 \opcode_in - attribute \enum_base_type "Function" - attribute \enum_value_00000000000 "NONE" - attribute \enum_value_00000000010 "ALU" - attribute \enum_value_00000000100 "LDST" - attribute \enum_value_00000001000 "SHIFT_ROT" - attribute \enum_value_00000010000 "LOGICAL" - attribute \enum_value_00000100000 "BRANCH" - attribute \enum_value_00001000000 "CR" - attribute \enum_value_00010000000 "TRAP" - attribute \enum_value_00100000000 "MUL" - attribute \enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 11 output 1 \CR_function_unit - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute 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case 5'11100 - assign \CR_internal_op \CR_internal_op$16 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'00000 - assign \CR_internal_op \CR_dec_sub0_CR_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'11010 - assign \CR_internal_op \CR_internal_op$17 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10011 - assign \CR_internal_op \CR_dec_sub19_CR_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10110 - assign \CR_internal_op \CR_internal_op$18 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01001 - assign \CR_internal_op \CR_internal_op$19 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01011 - assign \CR_internal_op \CR_internal_op$20 - attribute \src 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"/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \CR_cr_in$42 - process $group_22 - assign \CR_cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:315" - switch \opc_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01010 - assign \CR_cr_in \CR_cr_in$29 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'11100 - assign \CR_cr_in \CR_cr_in$30 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'00000 - assign \CR_cr_in \CR_dec_sub0_CR_cr_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'11010 - assign \CR_cr_in \CR_cr_in$31 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10011 - assign \CR_cr_in \CR_dec_sub19_CR_cr_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10110 - assign \CR_cr_in \CR_cr_in$32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01001 - assign \CR_cr_in \CR_cr_in$33 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01011 - assign \CR_cr_in \CR_cr_in$34 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'11011 - assign \CR_cr_in \CR_cr_in$35 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01111 - assign \CR_cr_in \CR_dec_sub15_CR_cr_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10100 - assign \CR_cr_in \CR_cr_in$36 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10101 - assign \CR_cr_in \CR_cr_in$37 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10111 - assign \CR_cr_in \CR_cr_in$38 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10000 - assign \CR_cr_in \CR_dec_sub16_CR_cr_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10010 - assign \CR_cr_in \CR_cr_in$39 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01000 - assign \CR_cr_in \CR_cr_in$40 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'11000 - assign \CR_cr_in \CR_cr_in$41 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'00100 - assign \CR_cr_in \CR_cr_in$42 - end - sync init - end - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \CR_cr_out$43 - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \CR_cr_out$44 - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \CR_cr_out$45 - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \CR_cr_out$46 - attribute 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attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \CR_cr_out$53 - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \CR_cr_out$54 - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \CR_cr_out$55 - attribute \enum_base_type "CROutSel" - attribute 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\enum_value_00000000000 "NONE" - attribute \enum_value_00000000010 "ALU" - attribute \enum_value_00000000100 "LDST" - attribute \enum_value_00000001000 "SHIFT_ROT" - attribute \enum_value_00000010000 "LOGICAL" - attribute \enum_value_00000100000 "BRANCH" - attribute \enum_value_00001000000 "CR" - attribute \enum_value_00010000000 "TRAP" - attribute \enum_value_00100000000 "MUL" - attribute \enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 11 \CR_function_unit$2 - attribute \enum_base_type "Function" - attribute \enum_value_00000000000 "NONE" - attribute \enum_value_00000000010 "ALU" - attribute \enum_value_00000000100 "LDST" - attribute \enum_value_00000001000 "SHIFT_ROT" - attribute \enum_value_00000010000 "LOGICAL" - attribute \enum_value_00000100000 "BRANCH" - attribute \enum_value_00001000000 "CR" - attribute \enum_value_00010000000 "TRAP" - attribute \enum_value_00100000000 "MUL" - attribute \enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 11 \CR_function_unit$3 - process $group_6 - assign \CR_function_unit 11'00000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'010011 - assign \CR_function_unit \CR_dec19_CR_function_unit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'011110 - assign \CR_function_unit \CR_function_unit$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'011111 - assign \CR_function_unit \CR_dec31_CR_function_unit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'111010 - assign \CR_function_unit \CR_function_unit$2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'111110 - assign \CR_function_unit \CR_function_unit$3 - end - sync init - end - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 7 \CR_internal_op$4 - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 7 \CR_internal_op$5 - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 7 \CR_internal_op$6 - process $group_7 - assign \CR_internal_op 7'0000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'010011 - assign \CR_internal_op \CR_dec19_CR_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'011110 - assign \CR_internal_op \CR_internal_op$4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'011111 - assign \CR_internal_op \CR_dec31_CR_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'111010 - assign \CR_internal_op \CR_internal_op$5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'111110 - assign \CR_internal_op \CR_internal_op$6 - end - sync init - end - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \CR_cr_in$7 - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \CR_cr_in$8 - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \CR_cr_in$9 - process $group_8 - assign \CR_cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'010011 - assign \CR_cr_in \CR_dec19_CR_cr_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'011110 - assign \CR_cr_in \CR_cr_in$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'011111 - assign \CR_cr_in \CR_dec31_CR_cr_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'111010 - assign \CR_cr_in \CR_cr_in$8 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'111110 - assign \CR_cr_in \CR_cr_in$9 - end - sync init - end - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \CR_cr_out$10 - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \CR_cr_out$11 - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \CR_cr_out$12 - process $group_9 - assign \CR_cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'010011 - assign \CR_cr_out \CR_dec19_CR_cr_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'011110 - assign \CR_cr_out \CR_cr_out$10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'011111 - assign \CR_cr_out \CR_dec31_CR_cr_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'111010 - assign \CR_cr_out \CR_cr_out$11 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'111110 - assign \CR_cr_out \CR_cr_out$12 - end - sync init - end - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 2 \CR_rc_sel$13 - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 2 \CR_rc_sel$14 - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 2 \CR_rc_sel$15 - process $group_10 - assign \CR_rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'010011 - assign \CR_rc_sel \CR_dec19_CR_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'011110 - assign \CR_rc_sel \CR_rc_sel$13 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'011111 - assign \CR_rc_sel \CR_dec31_CR_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'111010 - assign \CR_rc_sel \CR_rc_sel$14 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'111110 - assign \CR_rc_sel \CR_rc_sel$15 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:308" - wire width 32 \opcode_switch$16 - process $group_11 - assign \opcode_switch$16 32'00000000000000000000000000000000 - assign \opcode_switch$16 \opcode_in - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:418" - wire width 32 $17 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:418" - cell $mux $18 - parameter \WIDTH 32 - connect \A \raw_opcode_in - connect \B { \raw_opcode_in [7:0] \raw_opcode_in [15:8] \raw_opcode_in [23:16] \raw_opcode_in [31:24] } - connect \S \bigendian - connect \Y $17 - end - process $group_12 - assign \opcode_in 32'00000000000000000000000000000000 - assign \opcode_in $17 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 5 \CR_RS - process $group_13 - assign \CR_RS 5'00000 - assign \CR_RS { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 5 \CR_RT - process $group_14 - assign \CR_RT 5'00000 - assign \CR_RT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 5 \CR_RA - process $group_15 - assign \CR_RA 5'00000 - assign \CR_RA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 5 \CR_RB - process $group_16 - assign \CR_RB 5'00000 - assign \CR_RB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 16 \CR_SI - process $group_17 - assign \CR_SI 16'0000000000000000 - assign \CR_SI { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] \opcode_in [0] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 16 \CR_UI - process $group_18 - assign \CR_UI 16'0000000000000000 - assign \CR_UI { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] \opcode_in [0] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 1 \CR_L - process $group_19 - assign \CR_L 1'0 - assign \CR_L { \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 5 \CR_SH32 - process $group_20 - assign \CR_SH32 5'00000 - assign \CR_SH32 { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 6 \CR_sh - process $group_21 - assign \CR_sh 6'000000 - assign \CR_sh { \opcode_in [1] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 5 \CR_MB32 - process $group_22 - assign \CR_MB32 5'00000 - assign \CR_MB32 { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 5 \CR_ME32 - process $group_23 - assign \CR_ME32 5'00000 - assign \CR_ME32 { \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 24 \CR_LI - process $group_24 - assign \CR_LI 24'000000000000000000000000 - assign \CR_LI { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 1 \CR_LK - process $group_25 - assign \CR_LK 1'0 - assign \CR_LK { \opcode_in [0] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 1 \CR_AA - process $group_26 - assign \CR_AA 1'0 - assign \CR_AA { \opcode_in [1] } - sync init - end - process $group_27 - assign \CR_Rc 1'0 - assign \CR_Rc { \opcode_in [0] } - sync init - end - process $group_28 - assign \CR_OE 1'0 - assign \CR_OE { \opcode_in [10] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 14 \CR_BD - process $group_29 - assign \CR_BD 14'00000000000000 - assign \CR_BD { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 3 \CR_BF - process $group_30 - assign \CR_BF 3'000 - assign \CR_BF { \opcode_in [25] \opcode_in [24] \opcode_in [23] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 10 \CR_CR - process $group_31 - assign \CR_CR 10'0000000000 - assign \CR_CR { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] } - sync init - end - process $group_32 - assign \CR_BB 5'00000 - assign \CR_BB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - process $group_33 - assign \CR_BA 5'00000 - assign \CR_BA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - process $group_34 - assign \CR_BT 5'00000 - assign \CR_BT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - process $group_35 - assign \CR_FXM 8'00000000 - assign \CR_FXM { \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 5 \CR_BO - process $group_36 - assign \CR_BO 5'00000 - assign \CR_BO { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - process $group_37 - assign \CR_BI 5'00000 - assign \CR_BI { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 2 \CR_BH - process $group_38 - assign \CR_BH 2'00 - assign \CR_BH { \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 16 \CR_D - process $group_39 - assign \CR_D 16'0000000000000000 - assign \CR_D { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] \opcode_in [0] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 14 \CR_DS - process $group_40 - assign \CR_DS 14'00000000000000 - assign \CR_DS { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 5 \CR_TO - process $group_41 - assign \CR_TO 5'00000 - assign \CR_TO { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - process $group_42 - assign \CR_BC 5'00000 - assign \CR_BC { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 5 \CR_SH - process $group_43 - assign \CR_SH 5'00000 - assign \CR_SH { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 5 \CR_ME - process $group_44 - assign \CR_ME 5'00000 - assign \CR_ME { \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 5 \CR_MB - process $group_45 - assign \CR_MB 5'00000 - assign \CR_MB { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 10 \CR_SPR - process $group_46 - assign \CR_SPR 10'0000000000 - assign \CR_SPR { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \X_A - process $group_47 - assign \X_A 1'0 - assign \X_A { \opcode_in [25] } - sync init - end - process $group_48 - assign \X_BF 3'000 - assign \X_BF { \opcode_in [25] \opcode_in [24] \opcode_in [23] } - sync init - end - process $group_49 - assign \X_BFA 3'000 - assign \X_BFA { \opcode_in [20] \opcode_in [19] \opcode_in [18] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \X_BO - process $group_50 - assign \X_BO 5'00000 - assign \X_BO { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 4 \X_CT - process $group_51 - assign \X_CT 4'0000 - assign \X_CT { \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 7 \X_DCMX - process $group_52 - assign \X_DCMX 7'0000000 - assign \X_DCMX { \opcode_in [22] \opcode_in [21] \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 3 \X_DRM - process $group_53 - assign \X_DRM 3'000 - assign \X_DRM { \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \X_E - process $group_54 - assign \X_E 1'0 - assign \X_E { \opcode_in [15] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 4 \X_E_1 - process $group_55 - assign \X_E_1 4'0000 - assign \X_E_1 { \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 2 \X_EO - process $group_56 - assign \X_EO 2'00 - assign \X_EO { \opcode_in [20] \opcode_in [19] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \X_EO_1 - process $group_57 - assign \X_EO_1 5'00000 - assign \X_EO_1 { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \X_EX - process $group_58 - assign \X_EX 1'0 - assign \X_EX { \opcode_in [0] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \X_FC - process $group_59 - assign \X_FC 5'00000 - assign \X_FC { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \X_FRA - process $group_60 - assign \X_FRA 5'00000 - assign \X_FRA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \X_FRAp - process $group_61 - assign \X_FRAp 5'00000 - assign \X_FRAp { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \X_FRB - process $group_62 - assign \X_FRB 5'00000 - assign \X_FRB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \X_FRBp - process $group_63 - assign \X_FRBp 5'00000 - assign \X_FRBp { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \X_FRS - process $group_64 - assign \X_FRS 5'00000 - assign \X_FRS { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \X_FRSp - process $group_65 - assign \X_FRSp 5'00000 - assign \X_FRSp { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \X_FRT - process $group_66 - assign \X_FRT 5'00000 - assign \X_FRT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \X_FRTp - process $group_67 - assign \X_FRTp 5'00000 - assign \X_FRTp { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 3 \X_IH - process $group_68 - assign \X_IH 3'000 - assign \X_IH { \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 8 \X_IMM8 - process $group_69 - assign \X_IMM8 8'00000000 - assign \X_IMM8 { \opcode_in [18] \opcode_in [17] \opcode_in [16] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 2 \X_L2 - process $group_70 - assign \X_L2 2'00 - assign \X_L2 { \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \X_L - process $group_71 - assign \X_L 1'0 - assign \X_L { \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \X_L1 - process $group_72 - assign \X_L1 1'0 - assign \X_L1 { \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 2 \X_L3 - process $group_73 - assign \X_L3 2'00 - assign \X_L3 { \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \X_MO - process $group_74 - assign \X_MO 5'00000 - assign \X_MO { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \X_NB - process $group_75 - assign \X_NB 5'00000 - assign \X_NB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \X_PRS - process $group_76 - assign \X_PRS 1'0 - assign \X_PRS { \opcode_in [17] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \X_R - process $group_77 - assign \X_R 1'0 - assign \X_R { \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \X_R_1 - process $group_78 - assign \X_R_1 1'0 - assign \X_R_1 { \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \X_RA - process $group_79 - assign \X_RA 5'00000 - assign \X_RA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \X_RB - process $group_80 - assign \X_RB 5'00000 - assign \X_RB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \X_Rc - process $group_81 - assign \X_Rc 1'0 - assign \X_Rc { \opcode_in [0] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 2 \X_RIC - process $group_82 - assign \X_RIC 2'00 - assign \X_RIC { \opcode_in [19] \opcode_in [18] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 2 \X_RM - process $group_83 - assign \X_RM 2'00 - assign \X_RM { \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \X_RO - process $group_84 - assign \X_RO 1'0 - assign \X_RO { \opcode_in [0] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \X_RS - process $group_85 - assign \X_RS 5'00000 - assign \X_RS { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \X_RSp - process $group_86 - assign \X_RSp 5'00000 - assign \X_RSp { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \X_RT - process $group_87 - assign \X_RT 5'00000 - assign \X_RT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \X_RTp - process $group_88 - assign \X_RTp 5'00000 - assign \X_RTp { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \X_S - process $group_89 - assign \X_S 5'00000 - assign \X_S { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \X_SH - process $group_90 - assign \X_SH 5'00000 - assign \X_SH { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \X_SI - process $group_91 - assign \X_SI 5'00000 - assign \X_SI { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 2 \X_SP - process $group_92 - assign \X_SP 2'00 - assign \X_SP { \opcode_in [20] \opcode_in [19] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 4 \X_SR - process $group_93 - assign \X_SR 4'0000 - assign \X_SR { \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \X_SX - process $group_94 - assign \X_SX 1'0 - assign \X_SX { \opcode_in [0] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 6 \X_SX_S - process $group_95 - assign \X_SX_S 6'000000 - assign \X_SX_S { \opcode_in [0] \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \X_T - process $group_96 - assign \X_T 5'00000 - assign \X_T { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 10 \X_TBR - process $group_97 - assign \X_TBR 10'0000000000 - assign \X_TBR { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \X_TH - process $group_98 - assign \X_TH 5'00000 - assign \X_TH { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \X_TO - process $group_99 - assign \X_TO 5'00000 - assign \X_TO { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \X_TX - process $group_100 - assign \X_TX 1'0 - assign \X_TX { \opcode_in [0] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 6 \X_TX_T - process $group_101 - assign \X_TX_T 6'000000 - assign \X_TX_T { \opcode_in [0] \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 4 \X_U - process $group_102 - assign \X_U 4'0000 - assign \X_U { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \X_UIM - process $group_103 - assign \X_UIM 5'00000 - assign \X_UIM { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \X_VRS - process $group_104 - assign \X_VRS 5'00000 - assign \X_VRS { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \X_VRT - process $group_105 - assign \X_VRT 5'00000 - assign \X_VRT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \X_W - process $group_106 - assign \X_W 1'0 - assign \X_W { \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 2 \X_WC - process $group_107 - assign \X_WC 2'00 - assign \X_WC { \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 10 \X_XO - process $group_108 - assign \X_XO 10'0000000000 - assign \X_XO { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 8 \X_XO_1 - process $group_109 - assign \X_XO_1 8'00000000 - assign \X_XO_1 { \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \B_AA - process $group_110 - assign \B_AA 1'0 - assign \B_AA { \opcode_in [1] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 14 \B_BD - process $group_111 - assign \B_BD 14'00000000000000 - assign \B_BD { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \B_BI - process $group_112 - assign \B_BI 5'00000 - assign \B_BI { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \B_BO - process $group_113 - assign \B_BO 5'00000 - assign \B_BO { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \B_LK - process $group_114 - assign \B_LK 1'0 - assign \B_LK { \opcode_in [0] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \I_AA - process $group_115 - assign \I_AA 1'0 - assign \I_AA { \opcode_in [1] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 24 \I_LI - process $group_116 - assign \I_LI 24'000000000000000000000000 - assign \I_LI { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \I_LK - process $group_117 - assign \I_LK 1'0 - assign \I_LK { \opcode_in [0] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \XX3_AX - process $group_118 - assign \XX3_AX 1'0 - assign \XX3_AX { \opcode_in [2] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \XX3_A - process $group_119 - assign \XX3_A 5'00000 - assign \XX3_A { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 6 \XX3_AX_A - process $group_120 - assign \XX3_AX_A 6'000000 - assign \XX3_AX_A { \opcode_in [2] \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 3 \XX3_BF - process $group_121 - assign \XX3_BF 3'000 - assign \XX3_BF { \opcode_in [25] \opcode_in [24] \opcode_in [23] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \XX3_BX - process $group_122 - assign \XX3_BX 1'0 - assign \XX3_BX { \opcode_in [1] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \XX3_B - process $group_123 - assign \XX3_B 5'00000 - assign \XX3_B { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 6 \XX3_BX_B - process $group_124 - assign \XX3_BX_B 6'000000 - assign \XX3_BX_B { \opcode_in [1] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 2 \XX3_DM - process $group_125 - assign \XX3_DM 2'00 - assign \XX3_DM { \opcode_in [9] \opcode_in [8] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \XX3_Rc - process $group_126 - assign \XX3_Rc 1'0 - assign \XX3_Rc { \opcode_in [10] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 2 \XX3_SHW - process $group_127 - assign \XX3_SHW 2'00 - assign \XX3_SHW { \opcode_in [9] \opcode_in [8] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \XX3_TX - process $group_128 - assign \XX3_TX 1'0 - assign \XX3_TX { \opcode_in [0] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \XX3_T - process $group_129 - assign \XX3_T 5'00000 - assign \XX3_T { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 6 \XX3_TX_T - process $group_130 - assign \XX3_TX_T 6'000000 - assign \XX3_TX_T { \opcode_in [0] \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 4 \XX3_XO - process $group_131 - assign \XX3_XO 4'0000 - assign \XX3_XO { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 8 \XX3_XO_1 - process $group_132 - assign \XX3_XO_1 8'00000000 - assign \XX3_XO_1 { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 9 \XX3_XO_2 - process $group_133 - assign \XX3_XO_2 9'000000000 - assign \XX3_XO_2 { \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \XX4_AX - process $group_134 - assign \XX4_AX 1'0 - assign \XX4_AX { \opcode_in [2] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \XX4_A - process $group_135 - assign \XX4_A 5'00000 - assign \XX4_A { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 6 \XX4_AX_A - process $group_136 - assign \XX4_AX_A 6'000000 - assign \XX4_AX_A { \opcode_in [2] \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \XX4_BX - process $group_137 - assign \XX4_BX 1'0 - assign \XX4_BX { \opcode_in [1] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \XX4_B - process $group_138 - assign \XX4_B 5'00000 - assign \XX4_B { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 6 \XX4_BX_B - process $group_139 - assign \XX4_BX_B 6'000000 - assign \XX4_BX_B { \opcode_in [1] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \XX4_CX - process $group_140 - assign \XX4_CX 1'0 - assign \XX4_CX { \opcode_in [3] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \XX4_C - process $group_141 - assign \XX4_C 5'00000 - assign \XX4_C { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 6 \XX4_CX_C - process $group_142 - assign \XX4_CX_C 6'000000 - assign \XX4_CX_C { \opcode_in [3] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \XX4_TX - process $group_143 - assign \XX4_TX 1'0 - assign \XX4_TX { \opcode_in [0] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \XX4_T - process $group_144 - assign \XX4_T 5'00000 - assign \XX4_T { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 6 \XX4_TX_T - process $group_145 - assign \XX4_TX_T 6'000000 - assign \XX4_TX_T { \opcode_in [0] \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 2 \XX4_XO - process $group_146 - assign \XX4_XO 2'00 - assign \XX4_XO { \opcode_in [5] \opcode_in [4] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \XL_BA - process $group_147 - assign \XL_BA 5'00000 - assign \XL_BA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \XL_BB - process $group_148 - assign \XL_BB 5'00000 - assign \XL_BB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 3 \XL_BF - process $group_149 - assign \XL_BF 3'000 - assign \XL_BF { \opcode_in [25] \opcode_in [24] \opcode_in [23] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 3 \XL_BFA - process $group_150 - assign \XL_BFA 3'000 - assign \XL_BFA { \opcode_in [20] \opcode_in [19] \opcode_in [18] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 2 \XL_BH - process $group_151 - assign \XL_BH 2'00 - assign \XL_BH { \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \XL_BI - process $group_152 - assign \XL_BI 5'00000 - assign \XL_BI { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \XL_BO - process $group_153 - assign \XL_BO 5'00000 - assign \XL_BO { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \XL_BO_1 - process $group_154 - assign \XL_BO_1 5'00000 - assign \XL_BO_1 { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - process $group_155 - assign \XL_BT 5'00000 - assign \XL_BT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \XL_LK - process $group_156 - assign \XL_LK 1'0 - assign \XL_LK { \opcode_in [0] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 15 \XL_OC - process $group_157 - assign \XL_OC 15'000000000000000 - assign \XL_OC { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \XL_S - process $group_158 - assign \XL_S 1'0 - assign \XL_S { \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 10 \XL_XO - process $group_159 - assign \XL_XO 10'0000000000 - assign \XL_XO { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \A_BC - process $group_160 - assign \A_BC 5'00000 - assign \A_BC { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \A_FRA - process $group_161 - assign \A_FRA 5'00000 - assign \A_FRA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \A_FRB - process $group_162 - assign \A_FRB 5'00000 - assign \A_FRB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \A_FRC - process $group_163 - assign \A_FRC 5'00000 - assign \A_FRC { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \A_FRT - process $group_164 - assign \A_FRT 5'00000 - assign \A_FRT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \A_RA - process $group_165 - assign \A_RA 5'00000 - assign \A_RA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \A_RB - process $group_166 - assign \A_RB 5'00000 - assign \A_RB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \A_Rc - process $group_167 - assign \A_Rc 1'0 - assign \A_Rc { \opcode_in [0] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \A_RT - process $group_168 - assign \A_RT 5'00000 - assign \A_RT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \A_XO - process $group_169 - assign \A_XO 5'00000 - assign \A_XO { \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 3 \D_BF - process $group_170 - assign \D_BF 3'000 - assign \D_BF { \opcode_in [25] \opcode_in [24] \opcode_in [23] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 16 \D_D - process $group_171 - assign \D_D 16'0000000000000000 - assign \D_D { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] \opcode_in [0] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \D_FRS - process $group_172 - assign \D_FRS 5'00000 - assign \D_FRS { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \D_FRT - process $group_173 - assign \D_FRT 5'00000 - assign \D_FRT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \D_L - process $group_174 - assign \D_L 1'0 - assign \D_L { \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \D_RA - process $group_175 - assign \D_RA 5'00000 - assign \D_RA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \D_RS - process $group_176 - assign \D_RS 5'00000 - assign \D_RS { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \D_RT - process $group_177 - assign \D_RT 5'00000 - assign \D_RT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 16 \D_SI - process $group_178 - assign \D_SI 16'0000000000000000 - assign \D_SI { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] \opcode_in [0] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \D_TO - process $group_179 - assign \D_TO 5'00000 - assign \D_TO { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 16 \D_UI - process $group_180 - assign \D_UI 16'0000000000000000 - assign \D_UI { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] \opcode_in [0] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 3 \XX2_BF - process $group_181 - assign \XX2_BF 3'000 - assign \XX2_BF { \opcode_in [25] \opcode_in [24] \opcode_in [23] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \XX2_BX - process $group_182 - assign \XX2_BX 1'0 - assign \XX2_BX { \opcode_in [1] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \XX2_B - process $group_183 - assign \XX2_B 5'00000 - assign \XX2_B { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 6 \XX2_BX_B - process $group_184 - assign \XX2_BX_B 6'000000 - assign \XX2_BX_B { \opcode_in [1] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \XX2_dc - process $group_185 - assign \XX2_dc 1'0 - assign \XX2_dc { \opcode_in [6] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \XX2_dm - process $group_186 - assign \XX2_dm 1'0 - assign \XX2_dm { \opcode_in [2] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \XX2_dx - process $group_187 - assign \XX2_dx 5'00000 - assign \XX2_dx { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 7 \XX2_dc_dm_dx - process $group_188 - assign \XX2_dc_dm_dx 7'0000000 - assign \XX2_dc_dm_dx { \opcode_in [6] \opcode_in [2] \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 7 \XX2_DCMX - process $group_189 - assign \XX2_DCMX 7'0000000 - assign \XX2_DCMX { \opcode_in [22] \opcode_in [21] \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \XX2_EO - process $group_190 - assign \XX2_EO 5'00000 - assign \XX2_EO { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \XX2_RT - process $group_191 - assign \XX2_RT 5'00000 - assign \XX2_RT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \XX2_TX - process $group_192 - assign \XX2_TX 1'0 - assign \XX2_TX { \opcode_in [0] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \XX2_T - process $group_193 - assign \XX2_T 5'00000 - assign \XX2_T { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 6 \XX2_TX_T - process $group_194 - assign \XX2_TX_T 6'000000 - assign \XX2_TX_T { \opcode_in [0] \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 4 \XX2_UIM - process $group_195 - assign \XX2_UIM 4'0000 - assign \XX2_UIM { \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 2 \XX2_UIM_1 - process $group_196 - assign \XX2_UIM_1 2'00 - assign \XX2_UIM_1 { \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 7 \XX2_XO - process $group_197 - assign \XX2_XO 7'0000000 - assign \XX2_XO { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [5] \opcode_in [4] \opcode_in [3] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 9 \XX2_XO_1 - process $group_198 - assign \XX2_XO_1 9'000000000 - assign \XX2_XO_1 { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 3 \Z22_BF - process $group_199 - assign \Z22_BF 3'000 - assign \Z22_BF { \opcode_in [25] \opcode_in [24] \opcode_in [23] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 6 \Z22_DCM - process $group_200 - assign \Z22_DCM 6'000000 - assign \Z22_DCM { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 6 \Z22_DGM - process $group_201 - assign \Z22_DGM 6'000000 - assign \Z22_DGM { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \Z22_FRA - process $group_202 - assign \Z22_FRA 5'00000 - assign \Z22_FRA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \Z22_FRAp - process $group_203 - assign \Z22_FRAp 5'00000 - assign \Z22_FRAp { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \Z22_FRT - process $group_204 - assign \Z22_FRT 5'00000 - assign \Z22_FRT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \Z22_FRTp - process $group_205 - assign \Z22_FRTp 5'00000 - assign \Z22_FRTp { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \Z22_Rc - process $group_206 - assign \Z22_Rc 1'0 - assign \Z22_Rc { \opcode_in [0] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 6 \Z22_SH - process $group_207 - assign \Z22_SH 6'000000 - assign \Z22_SH { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 9 \Z22_XO - process $group_208 - assign \Z22_XO 9'000000000 - assign \Z22_XO { \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 3 \EVS_BFA - process $group_209 - assign \EVS_BFA 3'000 - assign \EVS_BFA { \opcode_in [2] \opcode_in [1] \opcode_in [0] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 10 \XFX_BHRBE - process $group_210 - assign \XFX_BHRBE 10'0000000000 - assign \XFX_BHRBE { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \XFX_DUI - process $group_211 - assign \XFX_DUI 5'00000 - assign \XFX_DUI { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 10 \XFX_DUIS - process $group_212 - assign \XFX_DUIS 10'0000000000 - assign \XFX_DUIS { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 8 \XFX_FXM - process $group_213 - assign \XFX_FXM 8'00000000 - assign \XFX_FXM { \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \XFX_RS - process $group_214 - assign \XFX_RS 5'00000 - assign \XFX_RS { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \XFX_RT - process $group_215 - assign \XFX_RT 5'00000 - assign \XFX_RT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 10 \XFX_SPR - process $group_216 - assign \XFX_SPR 10'0000000000 - assign \XFX_SPR { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 10 \XFX_XO - process $group_217 - assign \XFX_XO 10'0000000000 - assign \XFX_XO { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 10 \DX_d0 - process $group_218 - assign \DX_d0 10'0000000000 - assign \DX_d0 { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \DX_d1 - process $group_219 - assign \DX_d1 5'00000 - assign \DX_d1 { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \DX_d2 - process $group_220 - assign \DX_d2 1'0 - assign \DX_d2 { \opcode_in [0] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 16 \DX_d0_d1_d2 - process $group_221 - assign \DX_d0_d1_d2 16'0000000000000000 - assign \DX_d0_d1_d2 { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] \opcode_in [0] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \DX_RT - process $group_222 - assign \DX_RT 5'00000 - assign \DX_RT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \DX_XO - process $group_223 - assign \DX_XO 5'00000 - assign \DX_XO { \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 12 \DQ_DQ - process $group_224 - assign \DQ_DQ 12'000000000000 - assign \DQ_DQ { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 4 \DQ_PT - process $group_225 - assign \DQ_PT 4'0000 - assign \DQ_PT { \opcode_in [3] \opcode_in [2] \opcode_in [1] \opcode_in [0] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \DQ_RA - process $group_226 - assign \DQ_RA 5'00000 - assign \DQ_RA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \DQ_RTp - process $group_227 - assign \DQ_RTp 5'00000 - assign \DQ_RTp { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \DQ_SX - process $group_228 - assign \DQ_SX 1'0 - assign \DQ_SX { \opcode_in [3] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \DQ_S - process $group_229 - assign \DQ_S 5'00000 - assign \DQ_S { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 6 \DQ_SX_S - process $group_230 - assign \DQ_SX_S 6'000000 - assign \DQ_SX_S { \opcode_in [3] \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \DQ_TX - process $group_231 - assign \DQ_TX 1'0 - assign \DQ_TX { \opcode_in [3] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \DQ_T - process $group_232 - assign \DQ_T 5'00000 - assign \DQ_T { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 6 \DQ_TX_T - process $group_233 - assign \DQ_TX_T 6'000000 - assign \DQ_TX_T { \opcode_in [3] \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 3 \DQ_XO - process $group_234 - assign \DQ_XO 3'000 - assign \DQ_XO { \opcode_in [2] \opcode_in [1] \opcode_in [0] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 14 \DS_DS - process $group_235 - assign \DS_DS 14'00000000000000 - assign \DS_DS { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \DS_FRSp - process $group_236 - assign \DS_FRSp 5'00000 - assign \DS_FRSp { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \DS_FRTp - process $group_237 - assign \DS_FRTp 5'00000 - assign \DS_FRTp { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \DS_RA - process $group_238 - assign \DS_RA 5'00000 - assign \DS_RA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \DS_RS - process $group_239 - assign \DS_RS 5'00000 - assign \DS_RS { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \DS_RSp - process $group_240 - assign \DS_RSp 5'00000 - assign \DS_RSp { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \DS_RT - process $group_241 - assign \DS_RT 5'00000 - assign \DS_RT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \DS_VRS - process $group_242 - assign \DS_VRS 5'00000 - assign \DS_VRS { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \DS_VRT - process $group_243 - assign \DS_VRT 5'00000 - assign \DS_VRT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 2 \DS_XO - process $group_244 - assign \DS_XO 2'00 - assign \DS_XO { \opcode_in [1] \opcode_in [0] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \VX_EO - process $group_245 - assign \VX_EO 5'00000 - assign \VX_EO { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \VX_PS - process $group_246 - assign \VX_PS 1'0 - assign \VX_PS { \opcode_in [9] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \VX_RA - process $group_247 - assign \VX_RA 5'00000 - assign \VX_RA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \VX_RT - process $group_248 - assign \VX_RT 5'00000 - assign \VX_RT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \VX_SIM - process $group_249 - assign \VX_SIM 5'00000 - assign \VX_SIM { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \VX_UIM - process $group_250 - assign \VX_UIM 5'00000 - assign \VX_UIM { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 4 \VX_UIM_1 - process $group_251 - assign \VX_UIM_1 4'0000 - assign \VX_UIM_1 { \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 3 \VX_UIM_2 - process $group_252 - assign \VX_UIM_2 3'000 - assign \VX_UIM_2 { \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 2 \VX_UIM_3 - process $group_253 - assign \VX_UIM_3 2'00 - assign \VX_UIM_3 { \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \VX_VRA - process $group_254 - assign \VX_VRA 5'00000 - assign \VX_VRA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \VX_VRB - process $group_255 - assign \VX_VRB 5'00000 - assign \VX_VRB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \VX_VRT - process $group_256 - assign \VX_VRT 5'00000 - assign \VX_VRT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 10 \VX_XO - process $group_257 - assign \VX_XO 10'0000000000 - assign \VX_XO { \opcode_in [10] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] \opcode_in [0] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 11 \VX_XO_1 - process $group_258 - assign \VX_XO_1 11'00000000000 - assign \VX_XO_1 { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] \opcode_in [0] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 8 \XFL_FLM - process $group_259 - assign \XFL_FLM 8'00000000 - assign \XFL_FLM { \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \XFL_FRB - process $group_260 - assign \XFL_FRB 5'00000 - assign \XFL_FRB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \XFL_L - process $group_261 - assign \XFL_L 1'0 - assign \XFL_L { \opcode_in [25] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \XFL_Rc - process $group_262 - assign \XFL_Rc 1'0 - assign \XFL_Rc { \opcode_in [0] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \XFL_W - process $group_263 - assign \XFL_W 1'0 - assign \XFL_W { \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 10 \XFL_XO - process $group_264 - assign \XFL_XO 10'0000000000 - assign \XFL_XO { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \Z23_FRA - process $group_265 - assign \Z23_FRA 5'00000 - assign \Z23_FRA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \Z23_FRAp - process $group_266 - assign \Z23_FRAp 5'00000 - assign \Z23_FRAp { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \Z23_FRB - process $group_267 - assign \Z23_FRB 5'00000 - assign \Z23_FRB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \Z23_FRBp - process $group_268 - assign \Z23_FRBp 5'00000 - assign \Z23_FRBp { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \Z23_FRT - process $group_269 - assign \Z23_FRT 5'00000 - assign \Z23_FRT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \Z23_FRTp - process $group_270 - assign \Z23_FRTp 5'00000 - assign \Z23_FRTp { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \Z23_R - process $group_271 - assign \Z23_R 1'0 - assign \Z23_R { \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \Z23_Rc - process $group_272 - assign \Z23_Rc 1'0 - assign \Z23_Rc { \opcode_in [0] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 2 \Z23_RMC - process $group_273 - assign \Z23_RMC 2'00 - assign \Z23_RMC { \opcode_in [10] \opcode_in [9] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \Z23_TE - process $group_274 - assign \Z23_TE 5'00000 - assign \Z23_TE { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 8 \Z23_XO - process $group_275 - assign \Z23_XO 8'00000000 - assign \Z23_XO { \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \MDS_IB - process $group_276 - assign \MDS_IB 5'00000 - assign \MDS_IB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \MDS_IS - process $group_277 - assign \MDS_IS 5'00000 - assign \MDS_IS { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 6 \MDS_mb - process $group_278 - assign \MDS_mb 6'000000 - assign \MDS_mb { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 6 \MDS_me - process $group_279 - assign \MDS_me 6'000000 - assign \MDS_me { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \MDS_RA - process $group_280 - assign \MDS_RA 5'00000 - assign \MDS_RA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \MDS_RB - process $group_281 - assign \MDS_RB 5'00000 - assign \MDS_RB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \MDS_Rc - process $group_282 - assign \MDS_Rc 1'0 - assign \MDS_Rc { \opcode_in [0] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \MDS_RS - process $group_283 - assign \MDS_RS 5'00000 - assign \MDS_RS { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 4 \MDS_XBI - process $group_284 - assign \MDS_XBI 4'0000 - assign \MDS_XBI { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 4 \MDS_XBI_1 - process $group_285 - assign \MDS_XBI_1 4'0000 - assign \MDS_XBI_1 { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 4 \MDS_XO - process $group_286 - assign \MDS_XO 4'0000 - assign \MDS_XO { \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 7 \SC_LEV - process $group_287 - assign \SC_LEV 7'0000000 - assign \SC_LEV { \opcode_in [11] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \SC_XO - process $group_288 - assign \SC_XO 1'0 - assign \SC_XO { \opcode_in [1] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 2 \SC_XO_1 - process $group_289 - assign \SC_XO_1 2'00 - assign \SC_XO_1 { \opcode_in [1] \opcode_in [0] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \M_MB - process $group_290 - assign \M_MB 5'00000 - assign \M_MB { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \M_ME - process $group_291 - assign \M_ME 5'00000 - assign \M_ME { \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \M_RA - process $group_292 - assign \M_RA 5'00000 - assign \M_RA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \M_RB - process $group_293 - assign \M_RB 5'00000 - assign \M_RB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \M_Rc - process $group_294 - assign \M_Rc 1'0 - assign \M_Rc { \opcode_in [0] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \M_RS - process $group_295 - assign \M_RS 5'00000 - assign \M_RS { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \M_SH - process $group_296 - assign \M_SH 5'00000 - assign \M_SH { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 6 \MD_mb - process $group_297 - assign \MD_mb 6'000000 - assign \MD_mb { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 6 \MD_me - process $group_298 - assign \MD_me 6'000000 - assign \MD_me { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \MD_RA - process $group_299 - assign \MD_RA 5'00000 - assign \MD_RA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \MD_Rc - process $group_300 - assign \MD_Rc 1'0 - assign \MD_Rc { \opcode_in [0] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \MD_RS - process $group_301 - assign \MD_RS 5'00000 - assign \MD_RS { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 6 \MD_sh - process $group_302 - assign \MD_sh 6'000000 - assign \MD_sh { \opcode_in [1] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 3 \MD_XO - process $group_303 - assign \MD_XO 3'000 - assign \MD_XO { \opcode_in [4] \opcode_in [3] \opcode_in [2] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 6 \all_OPCD - process $group_304 - assign \all_OPCD 6'000000 - assign \all_OPCD { \opcode_in [31] \opcode_in [30] \opcode_in [29] \opcode_in [28] \opcode_in [27] \opcode_in [26] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 6 \all_PO - process $group_305 - assign \all_PO 6'000000 - assign \all_PO { \opcode_in [31] \opcode_in [30] \opcode_in [29] \opcode_in [28] \opcode_in [27] \opcode_in [26] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \XO_OE - process $group_306 - assign \XO_OE 1'0 - assign \XO_OE { \opcode_in [10] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \XO_RA - process $group_307 - assign \XO_RA 5'00000 - assign \XO_RA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \XO_RB - process $group_308 - assign \XO_RB 5'00000 - assign \XO_RB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \XO_Rc - process $group_309 - assign \XO_Rc 1'0 - assign \XO_Rc { \opcode_in [0] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \XO_RT - process $group_310 - assign \XO_RT 5'00000 - assign \XO_RT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 9 \XO_XO - process $group_311 - assign \XO_XO 9'000000000 - assign \XO_XO { \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \DQE_RA - process $group_312 - assign \DQE_RA 5'00000 - assign \DQE_RA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \DQE_RT - process $group_313 - assign \DQE_RT 5'00000 - assign \DQE_RT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 2 \DQE_XO - process $group_314 - assign \DQE_XO 2'00 - assign \DQE_XO { \opcode_in [1] \opcode_in [0] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \TX_RA - process $group_315 - assign \TX_RA 5'00000 - assign \TX_RA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \TX_UI - process $group_316 - assign \TX_UI 5'00000 - assign \TX_UI { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 4 \TX_XBI - process $group_317 - assign \TX_XBI 4'0000 - assign \TX_XBI { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 6 \TX_XO - process $group_318 - assign \TX_XO 6'000000 - assign \TX_XO { \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \VA_RA - process $group_319 - assign \VA_RA 5'00000 - assign \VA_RA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \VA_RB - process $group_320 - assign \VA_RB 5'00000 - assign \VA_RB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \VA_RC - process $group_321 - assign \VA_RC 5'00000 - assign \VA_RC { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \VA_RT - process $group_322 - assign \VA_RT 5'00000 - assign \VA_RT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 4 \VA_SHB - process $group_323 - assign \VA_SHB 4'0000 - assign \VA_SHB { \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \VA_VRA - process $group_324 - assign \VA_VRA 5'00000 - assign \VA_VRA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \VA_VRB - process $group_325 - assign \VA_VRB 5'00000 - assign \VA_VRB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \VA_VRC - process $group_326 - assign \VA_VRC 5'00000 - assign \VA_VRC { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \VA_VRT - process $group_327 - assign \VA_VRT 5'00000 - assign \VA_VRT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 6 \VA_XO - process $group_328 - assign \VA_XO 6'000000 - assign \VA_XO { \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] \opcode_in [0] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \XS_RA - process $group_329 - assign \XS_RA 5'00000 - assign \XS_RA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \XS_Rc - process $group_330 - assign \XS_Rc 1'0 - assign \XS_Rc { \opcode_in [0] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \XS_RS - process $group_331 - assign \XS_RS 5'00000 - assign \XS_RS { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 6 \XS_sh - process $group_332 - assign \XS_sh 6'000000 - assign \XS_sh { \opcode_in [1] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 9 \XS_XO - process $group_333 - assign \XS_XO 9'000000000 - assign \XS_XO { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \VC_Rc - process $group_334 - assign \VC_Rc 1'0 - assign \VC_Rc { \opcode_in [10] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \VC_VRA - process $group_335 - assign \VC_VRA 5'00000 - assign \VC_VRA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \VC_VRB - process $group_336 - assign \VC_VRB 5'00000 - assign \VC_VRB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \VC_VRT - process $group_337 - assign \VC_VRT 5'00000 - assign \VC_VRT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 10 \VC_XO - process $group_338 - assign \VC_XO 10'0000000000 - assign \VC_XO { \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] \opcode_in [0] } - sync init - end - connect \CR_function_unit$1 11'00000000000 - connect \CR_function_unit$2 11'00000000000 - connect \CR_function_unit$3 11'00000000000 - connect \CR_internal_op$4 7'0000000 - connect \CR_internal_op$5 7'0000000 - connect \CR_internal_op$6 7'0000000 - connect \CR_cr_in$7 3'000 - connect \CR_cr_in$8 3'000 - connect \CR_cr_in$9 3'000 - connect \CR_cr_out$10 3'000 - connect \CR_cr_out$11 3'000 - connect \CR_cr_out$12 3'000 - connect \CR_rc_sel$13 2'00 - connect \CR_rc_sel$14 2'00 - connect \CR_rc_sel$15 2'00 -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.dec_CR.dec_rc" -module \dec_rc$138 - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:404" - wire width 2 input 0 \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 1 \rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 1 input 2 \CR_Rc - process $group_0 - assign \rc 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:413" - switch \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:414" - attribute \nmigen.decoding "RC/2" - case 2'10 - assign \rc \CR_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:417" - attribute \nmigen.decoding "ONE/1" - case 2'01 - assign \rc 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:420" - attribute \nmigen.decoding "NONE/0" - case 2'00 - assign \rc 1'0 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \rc_ok - process $group_1 - assign \rc_ok 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:413" - switch \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:414" - attribute \nmigen.decoding "RC/2" - case 2'10 - assign \rc_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:417" - attribute \nmigen.decoding "ONE/1" - case 2'01 - assign \rc_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:420" - attribute \nmigen.decoding "NONE/0" - case 2'00 - assign \rc_ok 1'1 - end - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.dec_CR.dec_oe" -module \dec_oe$139 - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:441" - wire width 2 input 0 \sel_in - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 7 input 1 \CR_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 1 input 2 \CR_OE - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \oe - process $group_0 - assign \oe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:450" - switch \CR_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:461" - attribute \nmigen.decoding "OP_MUL_H64/51|OP_MUL_H32/52|OP_EXTS/31|OP_CNTZ/14|OP_SHL/60|OP_SHR/61|OP_RLC/56|OP_LOAD/37|OP_STORE/38|OP_RLCL/57|OP_RLCR/58|OP_EXTSWSLI/32" - case 7'0110011, 7'0110100, 7'0011111, 7'0001110, 7'0111100, 7'0111101, 7'0111000, 7'0100101, 7'0100110, 7'0111001, 7'0111010, 7'0100000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:465" - attribute \nmigen.decoding "" - case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:467" - switch \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:468" - attribute \nmigen.decoding "RC/2" - case 2'10 - assign \oe \CR_OE - end - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \oe_ok - process $group_1 - assign \oe_ok 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:450" - switch \CR_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:461" - attribute \nmigen.decoding "OP_MUL_H64/51|OP_MUL_H32/52|OP_EXTS/31|OP_CNTZ/14|OP_SHL/60|OP_SHR/61|OP_RLC/56|OP_LOAD/37|OP_STORE/38|OP_RLCL/57|OP_RLCR/58|OP_EXTSWSLI/32" - case 7'0110011, 7'0110100, 7'0011111, 7'0001110, 7'0111100, 7'0111101, 7'0111000, 7'0100101, 7'0100110, 7'0111001, 7'0111010, 7'0100000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:465" - attribute \nmigen.decoding "" - case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:467" - switch \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:468" - attribute \nmigen.decoding "RC/2" - case 2'10 - assign \oe_ok 1'1 - end - end - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.dec_CR.dec_cr_in.ppick" -module \ppick$141 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" - wire width 8 input 0 \i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" - wire 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"/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_bool $5 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A { \i [7] \ni [1] } - connect \Y $4 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $6 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $4 - connect \Y $3 - end - process $group_2 - assign \t1 1'0 - assign \t1 $3 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire width 1 \t2 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire width 1 $7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire width 1 $8 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_bool $9 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A { \i [6] \i [7] \ni [2] } - connect \Y $8 - end - attribute \src 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"/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:485" - wire width 32 input 0 \insn_in - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:484" - wire width 3 input 1 \sel_in - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 7 input 2 \CR_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 5 input 3 \CR_BB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 5 input 4 \CR_BA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 5 input 5 \CR_BT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 8 input 6 \CR_FXM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 5 input 7 \CR_BI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 5 input 8 \CR_BC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 3 input 9 \X_BFA - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" - wire width 8 \ppick_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" - wire width 8 \ppick_o - cell \ppick$141 \ppick - connect \i \ppick_i - connect \o \ppick_o - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \cr_bitfield_ok - process $group_0 - assign \cr_bitfield_ok 1'0 - assign \cr_bitfield_ok 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" - switch \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" - attribute \nmigen.decoding "NONE/0" - case 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:505" - attribute \nmigen.decoding "CR0/1" - case 3'001 - assign \cr_bitfield_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:508" - attribute \nmigen.decoding "BI/2" - case 3'010 - assign \cr_bitfield_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:511" - attribute \nmigen.decoding "BFA/3" - case 3'011 - assign \cr_bitfield_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:514" - attribute \nmigen.decoding "BA_BB/4" - case 3'100 - assign \cr_bitfield_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:521" - attribute \nmigen.decoding "BC/5" - case 3'101 - assign \cr_bitfield_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:524" - attribute \nmigen.decoding "WHOLE_REG/6" - case 3'110 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \cr_bitfield_b_ok - process $group_1 - assign \cr_bitfield_b_ok 1'0 - assign \cr_bitfield_b_ok 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" - switch \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" - attribute \nmigen.decoding "NONE/0" - case 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:505" - attribute \nmigen.decoding "CR0/1" - case 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:508" - attribute \nmigen.decoding "BI/2" - case 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:511" - attribute \nmigen.decoding "BFA/3" - case 3'011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:514" - attribute \nmigen.decoding "BA_BB/4" - case 3'100 - assign \cr_bitfield_b_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:521" - attribute \nmigen.decoding "BC/5" - case 3'101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:524" - attribute \nmigen.decoding "WHOLE_REG/6" - case 3'110 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \cr_fxm_ok - process $group_2 - assign \cr_fxm_ok 1'0 - assign \cr_fxm_ok 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" - switch \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" - attribute \nmigen.decoding "NONE/0" - case 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:505" - attribute \nmigen.decoding "CR0/1" - case 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:508" - attribute \nmigen.decoding "BI/2" - case 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:511" - attribute \nmigen.decoding "BFA/3" - case 3'011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:514" - attribute \nmigen.decoding "BA_BB/4" - case 3'100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:521" - attribute \nmigen.decoding "BC/5" - case 3'101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:524" - attribute \nmigen.decoding "WHOLE_REG/6" - case 3'110 - assign \cr_fxm_ok 1'1 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 3 \cr_bitfield - process $group_3 - assign \cr_bitfield 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" - switch \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" - attribute \nmigen.decoding "NONE/0" - case 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:505" - attribute \nmigen.decoding "CR0/1" - case 3'001 - assign \cr_bitfield 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:508" - attribute \nmigen.decoding "BI/2" - case 3'010 - assign \cr_bitfield \CR_BI [4:2] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:511" - attribute \nmigen.decoding "BFA/3" - case 3'011 - assign \cr_bitfield \X_BFA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:514" - attribute \nmigen.decoding "BA_BB/4" - case 3'100 - assign \cr_bitfield \CR_BA [4:2] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:521" - attribute \nmigen.decoding "BC/5" - case 3'101 - assign \cr_bitfield \CR_BC [4:2] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:524" - attribute \nmigen.decoding "WHOLE_REG/6" - case 3'110 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 3 \cr_bitfield_b - process $group_4 - assign \cr_bitfield_b 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" - switch \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" - attribute \nmigen.decoding "NONE/0" - case 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:505" - attribute \nmigen.decoding "CR0/1" - case 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:508" - attribute \nmigen.decoding "BI/2" - case 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:511" - attribute \nmigen.decoding "BFA/3" - case 3'011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:514" - attribute \nmigen.decoding "BA_BB/4" - case 3'100 - assign \cr_bitfield_b \CR_BB [4:2] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:521" - attribute \nmigen.decoding "BC/5" - case 3'101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:524" - attribute \nmigen.decoding "WHOLE_REG/6" - case 3'110 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 3 \cr_bitfield_o - process $group_5 - assign \cr_bitfield_o 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" - switch \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" - attribute \nmigen.decoding "NONE/0" - case 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:505" - attribute \nmigen.decoding "CR0/1" - case 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:508" - attribute \nmigen.decoding "BI/2" - case 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:511" - attribute \nmigen.decoding "BFA/3" - case 3'011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:514" - attribute \nmigen.decoding "BA_BB/4" - case 3'100 - assign \cr_bitfield_o \CR_BT [4:2] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:521" - attribute \nmigen.decoding "BC/5" - case 3'101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:524" - attribute \nmigen.decoding "WHOLE_REG/6" - case 3'110 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \cr_bitfield_o_ok - process $group_6 - assign \cr_bitfield_o_ok 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" - switch \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" - attribute \nmigen.decoding "NONE/0" - case 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:505" - attribute \nmigen.decoding "CR0/1" - case 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:508" - attribute \nmigen.decoding "BI/2" - case 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:511" - attribute \nmigen.decoding "BFA/3" - case 3'011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:514" - attribute \nmigen.decoding "BA_BB/4" - case 3'100 - assign \cr_bitfield_o_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:521" - attribute \nmigen.decoding "BC/5" - case 3'101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:524" - attribute \nmigen.decoding "WHOLE_REG/6" - case 3'110 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:526" - wire width 1 \move_one - process $group_7 - assign \move_one 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" - switch \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" - attribute \nmigen.decoding "NONE/0" - case 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:505" - attribute \nmigen.decoding "CR0/1" - case 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:508" - attribute \nmigen.decoding "BI/2" - case 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:511" - attribute \nmigen.decoding "BFA/3" - case 3'011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:514" - attribute \nmigen.decoding "BA_BB/4" - case 3'100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:521" - attribute \nmigen.decoding "BC/5" - case 3'101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:524" - attribute \nmigen.decoding "WHOLE_REG/6" - case 3'110 - assign \move_one \insn_in [20] - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" - cell $eq $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A \CR_internal_op - connect \B 7'0101101 - connect \Y $1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" - wire width 1 $3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" - cell $and $4 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $1 - connect \B \move_one - connect \Y $3 - end - process $group_8 - assign \ppick_i 8'00000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" - switch \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" - attribute \nmigen.decoding "NONE/0" - case 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:505" - attribute \nmigen.decoding "CR0/1" - case 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:508" - attribute \nmigen.decoding "BI/2" - case 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:511" - attribute \nmigen.decoding "BFA/3" - case 3'011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:514" - attribute \nmigen.decoding "BA_BB/4" - case 3'100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:521" - attribute \nmigen.decoding "BC/5" - case 3'101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:524" - attribute \nmigen.decoding "WHOLE_REG/6" - case 3'110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" - switch { $3 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" - case 1'1 - assign \ppick_i \CR_FXM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532" - case - end - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 8 \cr_fxm - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" - wire width 1 $5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" - cell $eq $6 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A \CR_internal_op - connect \B 7'0101101 - connect \Y $5 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" - wire width 1 $7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" - cell $and $8 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $5 - connect \B \move_one - connect \Y $7 - end - process $group_9 - assign \cr_fxm 8'00000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" - switch \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" - attribute \nmigen.decoding "NONE/0" - case 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:505" - attribute \nmigen.decoding "CR0/1" - case 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:508" - attribute \nmigen.decoding "BI/2" - case 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:511" - attribute \nmigen.decoding "BFA/3" - case 3'011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:514" - attribute \nmigen.decoding "BA_BB/4" - case 3'100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:521" - attribute \nmigen.decoding "BC/5" - case 3'101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:524" - attribute \nmigen.decoding "WHOLE_REG/6" - case 3'110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" - switch { $7 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" - case 1'1 - assign \cr_fxm \ppick_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532" - case - assign \cr_fxm 8'11111111 - end - end - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.dec_CR.dec_cr_out.ppick" -module \ppick$143 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" - wire width 8 input 0 \i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" - wire width 1 output 1 \en_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" - wire width 8 output 2 \o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:49" - wire width 8 \ni - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" - wire width 8 $1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" - cell $not $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \Y_WIDTH 8 - connect \A { \i [0] \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] } - connect \Y $1 - end - process $group_0 - assign \ni 8'00000000 - assign \ni $1 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire width 1 \t0 - process $group_1 - assign \t0 1'0 - assign \t0 \i [7] - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire width 1 \t1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire width 1 $3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire width 1 $4 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_bool $5 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A { \i [7] \ni [1] } - connect \Y $4 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $6 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $4 - connect \Y $3 - end - process $group_2 - assign \t1 1'0 - assign \t1 $3 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire width 1 \t2 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire width 1 $7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire width 1 $8 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_bool $9 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A { \i [6] \i [7] \ni [2] } - connect \Y $8 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $10 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $8 - connect \Y $7 - end - process $group_3 - assign \t2 1'0 - assign \t2 $7 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire width 1 \t3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire width 1 $11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire width 1 $12 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_bool $13 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A { \i [5] \i [6] \i [7] \ni [3] } - connect \Y $12 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $14 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $12 - connect \Y $11 - end - process $group_4 - assign \t3 1'0 - assign \t3 $11 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire width 1 \t4 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire width 1 $15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire width 1 $16 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_bool $17 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A { \i [4] \i [5] \i [6] \i [7] \ni [4] } - connect \Y $16 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $18 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $16 - connect \Y $15 - end - process $group_5 - assign \t4 1'0 - assign \t4 $15 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire width 1 \t5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire width 1 $19 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire width 1 $20 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_bool $21 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \Y_WIDTH 1 - connect \A { \i [3] \i [4] \i [5] \i [6] \i [7] \ni [5] } - connect \Y $20 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $22 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $20 - connect \Y $19 - end - process $group_6 - assign \t5 1'0 - assign \t5 $19 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire width 1 \t6 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire width 1 $23 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire width 1 $24 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_bool $25 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A { \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [6] } - connect \Y $24 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $26 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $24 - connect \Y $23 - end - process $group_7 - assign \t6 1'0 - assign \t6 $23 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire width 1 \t7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire width 1 $27 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire width 1 $28 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_bool $29 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A { \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [7] } - connect \Y $28 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $30 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $28 - connect \Y $27 - end - process $group_8 - assign \t7 1'0 - assign \t7 $27 - sync init - end - process $group_9 - assign \o 8'00000000 - assign \o { \t0 \t1 \t2 \t3 \t4 \t5 \t6 \t7 } - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" - wire width 1 $31 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" - cell $reduce_bool $32 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \o - connect \Y $31 - end - process $group_10 - assign \en_o 1'0 - assign \en_o $31 - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.dec_CR.dec_cr_out" -module \dec_cr_out$142 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:550" - wire width 32 input 0 \insn_in - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:549" - wire width 3 input 1 \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:548" - wire width 1 input 2 \rc_in - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 7 input 3 \CR_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 8 input 4 \CR_FXM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 3 input 5 \X_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 input 6 \XL_BT - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" - wire width 8 \ppick_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" - wire width 1 \ppick_en_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" - wire width 8 \ppick_o - cell \ppick$143 \ppick - connect \i \ppick_i - connect \en_o \ppick_en_o - connect \o \ppick_o - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \cr_bitfield_ok - process $group_0 - assign \cr_bitfield_ok 1'0 - assign \cr_bitfield_ok 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:563" - switch \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:564" - attribute \nmigen.decoding "NONE/0" - case 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:566" - attribute \nmigen.decoding "CR0/1" - case 3'001 - assign \cr_bitfield_ok \rc_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:569" - attribute \nmigen.decoding "BF/2" - case 3'010 - assign \cr_bitfield_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:572" - attribute \nmigen.decoding "BT/3" - case 3'011 - assign \cr_bitfield_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:575" - attribute \nmigen.decoding "WHOLE_REG/4" - case 3'100 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \cr_fxm_ok - process $group_1 - assign \cr_fxm_ok 1'0 - assign \cr_fxm_ok 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:563" - switch \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:564" - attribute \nmigen.decoding "NONE/0" - case 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:566" - attribute \nmigen.decoding "CR0/1" - case 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:569" - attribute \nmigen.decoding "BF/2" - case 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:572" - attribute \nmigen.decoding "BT/3" - case 3'011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:575" - attribute \nmigen.decoding "WHOLE_REG/4" - case 3'100 - assign \cr_fxm_ok 1'1 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 3 \cr_bitfield - process $group_2 - assign \cr_bitfield 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:563" - switch \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:564" - attribute \nmigen.decoding "NONE/0" - case 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:566" - attribute \nmigen.decoding "CR0/1" - case 3'001 - assign \cr_bitfield 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:569" - attribute \nmigen.decoding "BF/2" - case 3'010 - assign \cr_bitfield \X_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:572" - attribute \nmigen.decoding "BT/3" - case 3'011 - assign \cr_bitfield \XL_BT [4:2] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:575" - attribute \nmigen.decoding "WHOLE_REG/4" - case 3'100 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:577" - wire width 1 \move_one - process $group_3 - assign \move_one 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:563" - switch \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:564" - attribute \nmigen.decoding "NONE/0" - case 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:566" - attribute \nmigen.decoding "CR0/1" - case 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:569" - attribute \nmigen.decoding "BF/2" - case 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:572" - attribute \nmigen.decoding "BT/3" - case 3'011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:575" - attribute \nmigen.decoding "WHOLE_REG/4" - case 3'100 - assign \move_one \insn_in [20] - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:579" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:579" - cell $eq $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A \CR_internal_op - connect \B 7'0110000 - connect \Y $1 - end - process $group_4 - assign \ppick_i 8'00000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:563" - switch \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:564" - attribute \nmigen.decoding "NONE/0" - case 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:566" - attribute \nmigen.decoding "CR0/1" - case 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:569" - attribute \nmigen.decoding "BF/2" - case 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:572" - attribute \nmigen.decoding "BT/3" - case 3'011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:575" - attribute \nmigen.decoding "WHOLE_REG/4" - case 3'100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:579" - switch { $1 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:579" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:580" - switch { \move_one } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:580" - case 1'1 - assign \ppick_i \CR_FXM - attribute \src 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attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 7 output 2 \BRANCH_internal_op - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 4 output 3 \BRANCH_in2_sel - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 output 4 \BRANCH_cr_in - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 output 5 \BRANCH_cr_out - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 2 output 6 \BRANCH_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 output 7 \BRANCH_is_32b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 output 8 \BRANCH_lk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" - wire width 32 \BRANCH_dec_sub10_opcode_in - cell \BRANCH_dec_sub10 \BRANCH_dec_sub10 - connect \opcode_in \BRANCH_dec_sub10_opcode_in - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" - wire width 32 \BRANCH_dec_sub28_opcode_in - cell \BRANCH_dec_sub28 \BRANCH_dec_sub28 - connect \opcode_in \BRANCH_dec_sub28_opcode_in - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" - wire width 32 \BRANCH_dec_sub0_opcode_in - cell \BRANCH_dec_sub0 \BRANCH_dec_sub0 - connect \opcode_in \BRANCH_dec_sub0_opcode_in - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" - wire width 32 \BRANCH_dec_sub26_opcode_in - cell \BRANCH_dec_sub26 \BRANCH_dec_sub26 - connect \opcode_in \BRANCH_dec_sub26_opcode_in - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" - wire width 32 \BRANCH_dec_sub19_opcode_in - cell \BRANCH_dec_sub19 \BRANCH_dec_sub19 - connect \opcode_in \BRANCH_dec_sub19_opcode_in - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" - wire width 32 \BRANCH_dec_sub22_opcode_in - cell \BRANCH_dec_sub22 \BRANCH_dec_sub22 - connect \opcode_in \BRANCH_dec_sub22_opcode_in - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" - wire width 32 \BRANCH_dec_sub9_opcode_in - cell \BRANCH_dec_sub9 \BRANCH_dec_sub9 - connect \opcode_in \BRANCH_dec_sub9_opcode_in - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" - wire width 32 \BRANCH_dec_sub11_opcode_in - cell \BRANCH_dec_sub11 \BRANCH_dec_sub11 - connect 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"/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" - wire width 32 \BRANCH_dec_sub23_opcode_in - cell \BRANCH_dec_sub23 \BRANCH_dec_sub23 - connect \opcode_in \BRANCH_dec_sub23_opcode_in - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" - wire width 32 \BRANCH_dec_sub16_opcode_in - cell \BRANCH_dec_sub16 \BRANCH_dec_sub16 - connect \opcode_in \BRANCH_dec_sub16_opcode_in - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" - wire width 32 \BRANCH_dec_sub18_opcode_in - cell \BRANCH_dec_sub18 \BRANCH_dec_sub18 - connect \opcode_in \BRANCH_dec_sub18_opcode_in - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" - wire width 32 \BRANCH_dec_sub8_opcode_in - cell \BRANCH_dec_sub8 \BRANCH_dec_sub8 - connect \opcode_in \BRANCH_dec_sub8_opcode_in - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" - wire width 32 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4 \BRANCH_in2_sel$39 - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 4 \BRANCH_in2_sel$40 - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - 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attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 4 \BRANCH_in2_sel$47 - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 4 \BRANCH_in2_sel$48 - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 4 \BRANCH_in2_sel$49 - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 4 \BRANCH_in2_sel$50 - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 4 \BRANCH_in2_sel$51 - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 4 \BRANCH_in2_sel$52 - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 4 \BRANCH_in2_sel$53 - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 4 \BRANCH_in2_sel$54 - process $group_22 - assign \BRANCH_in2_sel 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:315" - switch \opc_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01010 - assign \BRANCH_in2_sel \BRANCH_in2_sel$37 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'11100 - assign \BRANCH_in2_sel \BRANCH_in2_sel$38 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'00000 - assign \BRANCH_in2_sel \BRANCH_in2_sel$39 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'11010 - assign \BRANCH_in2_sel \BRANCH_in2_sel$40 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10011 - assign \BRANCH_in2_sel \BRANCH_in2_sel$41 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10110 - assign \BRANCH_in2_sel \BRANCH_in2_sel$42 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01001 - assign \BRANCH_in2_sel \BRANCH_in2_sel$43 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01011 - assign \BRANCH_in2_sel \BRANCH_in2_sel$44 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'11011 - assign \BRANCH_in2_sel \BRANCH_in2_sel$45 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01111 - assign \BRANCH_in2_sel \BRANCH_in2_sel$46 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10100 - assign \BRANCH_in2_sel \BRANCH_in2_sel$47 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10101 - assign \BRANCH_in2_sel \BRANCH_in2_sel$48 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10111 - assign \BRANCH_in2_sel \BRANCH_in2_sel$49 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10000 - assign \BRANCH_in2_sel \BRANCH_in2_sel$50 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10010 - assign \BRANCH_in2_sel \BRANCH_in2_sel$51 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01000 - assign \BRANCH_in2_sel \BRANCH_in2_sel$52 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'11000 - assign \BRANCH_in2_sel \BRANCH_in2_sel$53 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'00100 - assign \BRANCH_in2_sel \BRANCH_in2_sel$54 - end - sync init - end - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \BRANCH_cr_in$55 - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \BRANCH_cr_in$56 - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \BRANCH_cr_in$57 - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \BRANCH_cr_in$58 - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \BRANCH_cr_in$59 - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \BRANCH_cr_in$60 - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \BRANCH_cr_in$61 - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \BRANCH_cr_in$62 - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \BRANCH_cr_in$63 - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \BRANCH_cr_in$64 - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \BRANCH_cr_in$65 - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \BRANCH_cr_in$66 - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \BRANCH_cr_in$67 - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \BRANCH_cr_in$68 - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \BRANCH_cr_in$69 - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \BRANCH_cr_in$70 - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \BRANCH_cr_in$71 - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \BRANCH_cr_in$72 - process $group_23 - assign \BRANCH_cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:315" - switch \opc_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01010 - assign \BRANCH_cr_in \BRANCH_cr_in$55 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'11100 - assign \BRANCH_cr_in \BRANCH_cr_in$56 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'00000 - assign \BRANCH_cr_in \BRANCH_cr_in$57 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'11010 - assign \BRANCH_cr_in \BRANCH_cr_in$58 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10011 - assign \BRANCH_cr_in \BRANCH_cr_in$59 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10110 - assign \BRANCH_cr_in \BRANCH_cr_in$60 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01001 - assign \BRANCH_cr_in \BRANCH_cr_in$61 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01011 - assign \BRANCH_cr_in \BRANCH_cr_in$62 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'11011 - assign \BRANCH_cr_in \BRANCH_cr_in$63 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01111 - assign \BRANCH_cr_in \BRANCH_cr_in$64 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10100 - assign \BRANCH_cr_in \BRANCH_cr_in$65 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10101 - assign \BRANCH_cr_in \BRANCH_cr_in$66 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10111 - assign \BRANCH_cr_in \BRANCH_cr_in$67 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10000 - assign \BRANCH_cr_in \BRANCH_cr_in$68 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10010 - assign \BRANCH_cr_in \BRANCH_cr_in$69 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01000 - assign \BRANCH_cr_in \BRANCH_cr_in$70 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'11000 - assign \BRANCH_cr_in \BRANCH_cr_in$71 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'00100 - assign \BRANCH_cr_in \BRANCH_cr_in$72 - end - sync init - end - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \BRANCH_cr_out$73 - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \BRANCH_cr_out$74 - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \BRANCH_cr_out$75 - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \BRANCH_cr_out$76 - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \BRANCH_cr_out$77 - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \BRANCH_cr_out$78 - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \BRANCH_cr_out$79 - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \BRANCH_cr_out$80 - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \BRANCH_cr_out$81 - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \BRANCH_cr_out$82 - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \BRANCH_cr_out$83 - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \BRANCH_cr_out$84 - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \BRANCH_cr_out$85 - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \BRANCH_cr_out$86 - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \BRANCH_cr_out$87 - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \BRANCH_cr_out$88 - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \BRANCH_cr_out$89 - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \BRANCH_cr_out$90 - process $group_24 - assign \BRANCH_cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:315" - switch \opc_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01010 - assign \BRANCH_cr_out \BRANCH_cr_out$73 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'11100 - assign \BRANCH_cr_out \BRANCH_cr_out$74 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'00000 - assign \BRANCH_cr_out \BRANCH_cr_out$75 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'11010 - assign \BRANCH_cr_out \BRANCH_cr_out$76 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10011 - assign \BRANCH_cr_out \BRANCH_cr_out$77 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10110 - assign \BRANCH_cr_out \BRANCH_cr_out$78 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01001 - assign \BRANCH_cr_out \BRANCH_cr_out$79 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01011 - assign \BRANCH_cr_out \BRANCH_cr_out$80 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'11011 - assign \BRANCH_cr_out \BRANCH_cr_out$81 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01111 - assign \BRANCH_cr_out \BRANCH_cr_out$82 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10100 - assign \BRANCH_cr_out \BRANCH_cr_out$83 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10101 - assign \BRANCH_cr_out \BRANCH_cr_out$84 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10111 - assign \BRANCH_cr_out \BRANCH_cr_out$85 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10000 - assign \BRANCH_cr_out \BRANCH_cr_out$86 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10010 - assign \BRANCH_cr_out \BRANCH_cr_out$87 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01000 - assign \BRANCH_cr_out \BRANCH_cr_out$88 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'11000 - assign \BRANCH_cr_out \BRANCH_cr_out$89 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'00100 - assign \BRANCH_cr_out \BRANCH_cr_out$90 - end - sync init - end - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 2 \BRANCH_rc_sel$91 - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 2 \BRANCH_rc_sel$92 - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 2 \BRANCH_rc_sel$93 - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 2 \BRANCH_rc_sel$94 - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 2 \BRANCH_rc_sel$95 - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 2 \BRANCH_rc_sel$96 - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 2 \BRANCH_rc_sel$97 - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 2 \BRANCH_rc_sel$98 - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 2 \BRANCH_rc_sel$99 - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 2 \BRANCH_rc_sel$100 - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 2 \BRANCH_rc_sel$101 - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 2 \BRANCH_rc_sel$102 - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 2 \BRANCH_rc_sel$103 - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 2 \BRANCH_rc_sel$104 - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 2 \BRANCH_rc_sel$105 - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 2 \BRANCH_rc_sel$106 - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 2 \BRANCH_rc_sel$107 - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 2 \BRANCH_rc_sel$108 - process $group_25 - assign \BRANCH_rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:315" - switch \opc_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01010 - assign \BRANCH_rc_sel \BRANCH_rc_sel$91 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'11100 - assign \BRANCH_rc_sel \BRANCH_rc_sel$92 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'00000 - assign \BRANCH_rc_sel \BRANCH_rc_sel$93 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'11010 - assign \BRANCH_rc_sel \BRANCH_rc_sel$94 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10011 - assign \BRANCH_rc_sel \BRANCH_rc_sel$95 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10110 - assign \BRANCH_rc_sel \BRANCH_rc_sel$96 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01001 - assign \BRANCH_rc_sel \BRANCH_rc_sel$97 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01011 - assign \BRANCH_rc_sel \BRANCH_rc_sel$98 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'11011 - assign \BRANCH_rc_sel \BRANCH_rc_sel$99 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01111 - assign \BRANCH_rc_sel \BRANCH_rc_sel$100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10100 - assign \BRANCH_rc_sel \BRANCH_rc_sel$101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10101 - assign \BRANCH_rc_sel \BRANCH_rc_sel$102 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10111 - assign \BRANCH_rc_sel \BRANCH_rc_sel$103 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10000 - assign \BRANCH_rc_sel \BRANCH_rc_sel$104 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10010 - assign \BRANCH_rc_sel \BRANCH_rc_sel$105 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01000 - assign \BRANCH_rc_sel \BRANCH_rc_sel$106 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'11000 - assign \BRANCH_rc_sel \BRANCH_rc_sel$107 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'00100 - assign \BRANCH_rc_sel \BRANCH_rc_sel$108 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \BRANCH_is_32b$109 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \BRANCH_is_32b$110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \BRANCH_is_32b$111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \BRANCH_is_32b$112 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \BRANCH_is_32b$113 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \BRANCH_is_32b$114 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \BRANCH_is_32b$115 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \BRANCH_is_32b$116 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \BRANCH_is_32b$117 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \BRANCH_is_32b$118 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \BRANCH_is_32b$119 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \BRANCH_is_32b$120 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \BRANCH_is_32b$121 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \BRANCH_is_32b$122 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \BRANCH_is_32b$123 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \BRANCH_is_32b$124 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \BRANCH_is_32b$125 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \BRANCH_is_32b$126 - process $group_26 - assign \BRANCH_is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:315" - switch \opc_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01010 - assign \BRANCH_is_32b \BRANCH_is_32b$109 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'11100 - assign \BRANCH_is_32b \BRANCH_is_32b$110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'00000 - assign \BRANCH_is_32b \BRANCH_is_32b$111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'11010 - assign \BRANCH_is_32b \BRANCH_is_32b$112 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10011 - assign \BRANCH_is_32b \BRANCH_is_32b$113 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10110 - assign \BRANCH_is_32b \BRANCH_is_32b$114 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01001 - assign \BRANCH_is_32b \BRANCH_is_32b$115 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01011 - assign \BRANCH_is_32b \BRANCH_is_32b$116 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'11011 - assign \BRANCH_is_32b \BRANCH_is_32b$117 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01111 - assign \BRANCH_is_32b \BRANCH_is_32b$118 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10100 - assign \BRANCH_is_32b \BRANCH_is_32b$119 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10101 - assign \BRANCH_is_32b \BRANCH_is_32b$120 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10111 - assign \BRANCH_is_32b \BRANCH_is_32b$121 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10000 - assign \BRANCH_is_32b \BRANCH_is_32b$122 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10010 - assign \BRANCH_is_32b \BRANCH_is_32b$123 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01000 - assign \BRANCH_is_32b \BRANCH_is_32b$124 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'11000 - assign \BRANCH_is_32b \BRANCH_is_32b$125 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'00100 - assign \BRANCH_is_32b \BRANCH_is_32b$126 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \BRANCH_lk$127 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \BRANCH_lk$128 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \BRANCH_lk$129 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \BRANCH_lk$130 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \BRANCH_lk$131 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \BRANCH_lk$132 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \BRANCH_lk$133 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \BRANCH_lk$134 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \BRANCH_lk$135 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \BRANCH_lk$136 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \BRANCH_lk$137 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \BRANCH_lk$138 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \BRANCH_lk$139 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \BRANCH_lk$140 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \BRANCH_lk$141 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \BRANCH_lk$142 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \BRANCH_lk$143 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \BRANCH_lk$144 - process $group_27 - assign \BRANCH_lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:315" - switch \opc_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01010 - assign \BRANCH_lk \BRANCH_lk$127 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'11100 - assign \BRANCH_lk \BRANCH_lk$128 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'00000 - assign \BRANCH_lk \BRANCH_lk$129 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'11010 - assign \BRANCH_lk \BRANCH_lk$130 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10011 - assign \BRANCH_lk \BRANCH_lk$131 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10110 - assign \BRANCH_lk \BRANCH_lk$132 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01001 - assign \BRANCH_lk \BRANCH_lk$133 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01011 - assign \BRANCH_lk \BRANCH_lk$134 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'11011 - assign \BRANCH_lk \BRANCH_lk$135 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01111 - assign \BRANCH_lk \BRANCH_lk$136 - attribute \src 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attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 7 \BRANCH_internal_op$6 - process $group_7 - assign \BRANCH_internal_op 7'0000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'010011 - assign \BRANCH_internal_op \BRANCH_dec19_BRANCH_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'011110 - assign \BRANCH_internal_op \BRANCH_internal_op$4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'011111 - assign \BRANCH_internal_op \BRANCH_dec31_BRANCH_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'111010 - assign \BRANCH_internal_op \BRANCH_internal_op$5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'111110 - assign \BRANCH_internal_op \BRANCH_internal_op$6 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'010010 - assign \BRANCH_internal_op 7'0000110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'010000 - assign \BRANCH_internal_op 7'0000111 - end - sync init - end - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 4 \BRANCH_in2_sel$7 - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 4 \BRANCH_in2_sel$8 - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 4 \BRANCH_in2_sel$9 - process $group_8 - assign \BRANCH_in2_sel 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'010011 - assign \BRANCH_in2_sel \BRANCH_dec19_BRANCH_in2_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'011110 - assign \BRANCH_in2_sel \BRANCH_in2_sel$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'011111 - assign \BRANCH_in2_sel \BRANCH_dec31_BRANCH_in2_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'111010 - assign \BRANCH_in2_sel \BRANCH_in2_sel$8 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'111110 - assign \BRANCH_in2_sel \BRANCH_in2_sel$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'010010 - assign \BRANCH_in2_sel 4'0110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'010000 - assign \BRANCH_in2_sel 4'0111 - end - sync init - end - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \BRANCH_cr_in$10 - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \BRANCH_cr_in$11 - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \BRANCH_cr_in$12 - process $group_9 - assign \BRANCH_cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'010011 - assign \BRANCH_cr_in \BRANCH_dec19_BRANCH_cr_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'011110 - assign \BRANCH_cr_in \BRANCH_cr_in$10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'011111 - assign \BRANCH_cr_in \BRANCH_dec31_BRANCH_cr_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'111010 - assign \BRANCH_cr_in \BRANCH_cr_in$11 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'111110 - assign \BRANCH_cr_in \BRANCH_cr_in$12 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'010010 - assign \BRANCH_cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'010000 - assign \BRANCH_cr_in 3'010 - end - sync init - end - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \BRANCH_cr_out$13 - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \BRANCH_cr_out$14 - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \BRANCH_cr_out$15 - process $group_10 - assign \BRANCH_cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'010011 - assign \BRANCH_cr_out \BRANCH_dec19_BRANCH_cr_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'011110 - assign \BRANCH_cr_out \BRANCH_cr_out$13 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'011111 - assign \BRANCH_cr_out \BRANCH_dec31_BRANCH_cr_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'111010 - assign \BRANCH_cr_out \BRANCH_cr_out$14 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'111110 - assign \BRANCH_cr_out \BRANCH_cr_out$15 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'010010 - assign \BRANCH_cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'010000 - assign \BRANCH_cr_out 3'000 - end - sync init - end - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 2 \BRANCH_rc_sel$16 - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 2 \BRANCH_rc_sel$17 - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 2 \BRANCH_rc_sel$18 - process $group_11 - assign \BRANCH_rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'010011 - assign \BRANCH_rc_sel \BRANCH_dec19_BRANCH_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'011110 - assign \BRANCH_rc_sel \BRANCH_rc_sel$16 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'011111 - assign \BRANCH_rc_sel \BRANCH_dec31_BRANCH_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'111010 - assign \BRANCH_rc_sel \BRANCH_rc_sel$17 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'111110 - assign \BRANCH_rc_sel \BRANCH_rc_sel$18 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'010010 - assign \BRANCH_rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'010000 - assign \BRANCH_rc_sel 2'00 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \BRANCH_is_32b$19 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \BRANCH_is_32b$20 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \BRANCH_is_32b$21 - process $group_12 - assign \BRANCH_is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'010011 - assign \BRANCH_is_32b \BRANCH_dec19_BRANCH_is_32b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'011110 - assign \BRANCH_is_32b \BRANCH_is_32b$19 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'011111 - assign \BRANCH_is_32b \BRANCH_dec31_BRANCH_is_32b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'111010 - assign \BRANCH_is_32b \BRANCH_is_32b$20 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'111110 - assign \BRANCH_is_32b \BRANCH_is_32b$21 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'010010 - assign \BRANCH_is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'010000 - assign \BRANCH_is_32b 1'0 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \BRANCH_lk$22 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \BRANCH_lk$23 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \BRANCH_lk$24 - process $group_13 - assign \BRANCH_lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'010011 - assign \BRANCH_lk \BRANCH_dec19_BRANCH_lk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'011110 - assign \BRANCH_lk \BRANCH_lk$22 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'011111 - assign \BRANCH_lk \BRANCH_dec31_BRANCH_lk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'111010 - assign \BRANCH_lk \BRANCH_lk$23 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'111110 - assign \BRANCH_lk \BRANCH_lk$24 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'010010 - assign \BRANCH_lk 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'010000 - assign \BRANCH_lk 1'1 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:308" - wire width 32 \opcode_switch$25 - process $group_14 - assign \opcode_switch$25 32'00000000000000000000000000000000 - assign \opcode_switch$25 \opcode_in - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:418" - wire width 32 $26 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:418" - cell $mux $27 - parameter \WIDTH 32 - connect \A \raw_opcode_in - connect \B { \raw_opcode_in [7:0] \raw_opcode_in [15:8] \raw_opcode_in [23:16] \raw_opcode_in [31:24] } - connect \S \bigendian - connect \Y $26 - end - process $group_15 - assign \opcode_in 32'00000000000000000000000000000000 - assign \opcode_in $26 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 5 \BRANCH_RS - process $group_16 - assign \BRANCH_RS 5'00000 - assign \BRANCH_RS { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 5 \BRANCH_RT - process $group_17 - assign \BRANCH_RT 5'00000 - assign \BRANCH_RT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 5 \BRANCH_RA - process $group_18 - assign \BRANCH_RA 5'00000 - assign \BRANCH_RA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 5 \BRANCH_RB - process $group_19 - assign \BRANCH_RB 5'00000 - assign \BRANCH_RB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - process $group_20 - assign \BRANCH_SI 16'0000000000000000 - assign \BRANCH_SI { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] \opcode_in [0] } - sync init - end - process $group_21 - assign \BRANCH_UI 16'0000000000000000 - assign \BRANCH_UI { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] \opcode_in [0] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 1 \BRANCH_L - process $group_22 - assign \BRANCH_L 1'0 - assign \BRANCH_L { \opcode_in [21] } - sync init - end - process $group_23 - assign \BRANCH_SH32 5'00000 - assign \BRANCH_SH32 { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - process $group_24 - assign \BRANCH_sh 6'000000 - assign \BRANCH_sh { \opcode_in [1] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 5 \BRANCH_MB32 - process $group_25 - assign \BRANCH_MB32 5'00000 - assign \BRANCH_MB32 { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 5 \BRANCH_ME32 - process $group_26 - assign \BRANCH_ME32 5'00000 - assign \BRANCH_ME32 { \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] } - sync init - end - process $group_27 - assign \BRANCH_LI 24'000000000000000000000000 - assign \BRANCH_LI { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] } - sync init - end - process $group_28 - assign \BRANCH_LK 1'0 - assign \BRANCH_LK { \opcode_in [0] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 1 \BRANCH_AA - process $group_29 - assign \BRANCH_AA 1'0 - assign \BRANCH_AA { \opcode_in [1] } - sync init - end - process $group_30 - assign \BRANCH_Rc 1'0 - assign \BRANCH_Rc { \opcode_in [0] } - sync init - end - process $group_31 - assign \BRANCH_OE 1'0 - assign \BRANCH_OE { \opcode_in [10] } - sync init - end - process $group_32 - assign \BRANCH_BD 14'00000000000000 - assign \BRANCH_BD { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 3 \BRANCH_BF - process $group_33 - assign \BRANCH_BF 3'000 - assign \BRANCH_BF { \opcode_in [25] \opcode_in [24] \opcode_in [23] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 10 \BRANCH_CR - process $group_34 - assign \BRANCH_CR 10'0000000000 - assign \BRANCH_CR { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] } - sync init - end - process $group_35 - assign \BRANCH_BB 5'00000 - assign \BRANCH_BB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - process $group_36 - assign \BRANCH_BA 5'00000 - assign \BRANCH_BA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - process $group_37 - assign \BRANCH_BT 5'00000 - assign \BRANCH_BT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - process $group_38 - assign \BRANCH_FXM 8'00000000 - assign \BRANCH_FXM { \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 5 \BRANCH_BO - process $group_39 - assign \BRANCH_BO 5'00000 - assign \BRANCH_BO { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - process $group_40 - assign \BRANCH_BI 5'00000 - assign \BRANCH_BI { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 2 \BRANCH_BH - process $group_41 - assign \BRANCH_BH 2'00 - assign \BRANCH_BH { \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 16 \BRANCH_D - process $group_42 - assign \BRANCH_D 16'0000000000000000 - assign \BRANCH_D { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] \opcode_in [0] } - sync init - end - process $group_43 - assign \BRANCH_DS 14'00000000000000 - assign \BRANCH_DS { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 5 \BRANCH_TO - process $group_44 - assign \BRANCH_TO 5'00000 - assign \BRANCH_TO { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - process $group_45 - assign \BRANCH_BC 5'00000 - assign \BRANCH_BC { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 5 \BRANCH_SH - process $group_46 - assign \BRANCH_SH 5'00000 - assign \BRANCH_SH { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 5 \BRANCH_ME - process $group_47 - assign \BRANCH_ME 5'00000 - assign \BRANCH_ME { \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 5 \BRANCH_MB - process $group_48 - assign \BRANCH_MB 5'00000 - assign \BRANCH_MB { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 10 \BRANCH_SPR - process $group_49 - assign \BRANCH_SPR 10'0000000000 - assign \BRANCH_SPR { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \X_A - process $group_50 - assign \X_A 1'0 - assign \X_A { \opcode_in [25] } - sync init - end - process $group_51 - assign \X_BF 3'000 - assign \X_BF { \opcode_in [25] \opcode_in [24] \opcode_in [23] } - sync init - end - process $group_52 - assign \X_BFA 3'000 - assign \X_BFA { \opcode_in [20] \opcode_in [19] \opcode_in [18] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \X_BO - process $group_53 - assign \X_BO 5'00000 - assign \X_BO { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 4 \X_CT - process $group_54 - assign \X_CT 4'0000 - assign \X_CT { \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 7 \X_DCMX - process $group_55 - assign \X_DCMX 7'0000000 - assign \X_DCMX { \opcode_in [22] \opcode_in [21] \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 3 \X_DRM - process $group_56 - assign \X_DRM 3'000 - assign \X_DRM { \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \X_E - process $group_57 - assign \X_E 1'0 - assign \X_E { \opcode_in [15] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 4 \X_E_1 - process $group_58 - assign \X_E_1 4'0000 - assign \X_E_1 { \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 2 \X_EO - process $group_59 - assign \X_EO 2'00 - assign \X_EO { \opcode_in [20] \opcode_in [19] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \X_EO_1 - process $group_60 - assign \X_EO_1 5'00000 - assign \X_EO_1 { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \X_EX - process $group_61 - assign \X_EX 1'0 - assign \X_EX { \opcode_in [0] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \X_FC - process $group_62 - assign \X_FC 5'00000 - assign \X_FC { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \X_FRA - process $group_63 - assign \X_FRA 5'00000 - assign \X_FRA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \X_FRAp - process $group_64 - assign \X_FRAp 5'00000 - assign \X_FRAp { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \X_FRB - process $group_65 - assign \X_FRB 5'00000 - assign \X_FRB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \X_FRBp - process $group_66 - assign \X_FRBp 5'00000 - assign \X_FRBp { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \X_FRS - process $group_67 - assign \X_FRS 5'00000 - assign \X_FRS { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \X_FRSp - process $group_68 - assign \X_FRSp 5'00000 - assign \X_FRSp { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \X_FRT - process $group_69 - assign \X_FRT 5'00000 - assign \X_FRT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \X_FRTp - process $group_70 - assign \X_FRTp 5'00000 - assign \X_FRTp { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 3 \X_IH - process $group_71 - assign \X_IH 3'000 - assign \X_IH { \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 8 \X_IMM8 - process $group_72 - assign \X_IMM8 8'00000000 - assign \X_IMM8 { \opcode_in [18] \opcode_in [17] \opcode_in [16] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 2 \X_L2 - process $group_73 - assign \X_L2 2'00 - assign \X_L2 { \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \X_L - process $group_74 - assign \X_L 1'0 - assign \X_L { \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \X_L1 - process $group_75 - assign \X_L1 1'0 - assign \X_L1 { \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 2 \X_L3 - process $group_76 - assign \X_L3 2'00 - assign \X_L3 { \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \X_MO - process $group_77 - assign \X_MO 5'00000 - assign \X_MO { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \X_NB - process $group_78 - assign \X_NB 5'00000 - assign \X_NB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \X_PRS - process $group_79 - assign \X_PRS 1'0 - assign \X_PRS { \opcode_in [17] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \X_R - process $group_80 - assign \X_R 1'0 - assign \X_R { \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \X_R_1 - process $group_81 - assign \X_R_1 1'0 - assign \X_R_1 { \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \X_RA - process $group_82 - assign \X_RA 5'00000 - assign \X_RA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \X_RB - process $group_83 - assign \X_RB 5'00000 - assign \X_RB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \X_Rc - process $group_84 - assign \X_Rc 1'0 - assign \X_Rc { \opcode_in [0] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 2 \X_RIC - process $group_85 - assign \X_RIC 2'00 - assign \X_RIC { \opcode_in [19] \opcode_in [18] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 2 \X_RM - process $group_86 - assign \X_RM 2'00 - assign \X_RM { \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \X_RO - process $group_87 - assign \X_RO 1'0 - assign \X_RO { \opcode_in [0] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \X_RS - process $group_88 - assign \X_RS 5'00000 - assign \X_RS { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \X_RSp - process $group_89 - assign \X_RSp 5'00000 - assign \X_RSp { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \X_RT - process $group_90 - assign \X_RT 5'00000 - assign \X_RT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \X_RTp - process $group_91 - assign \X_RTp 5'00000 - assign \X_RTp { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \X_S - process $group_92 - assign \X_S 5'00000 - assign \X_S { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \X_SH - process $group_93 - assign \X_SH 5'00000 - assign \X_SH { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \X_SI - process $group_94 - assign \X_SI 5'00000 - assign \X_SI { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 2 \X_SP - process $group_95 - assign \X_SP 2'00 - assign \X_SP { \opcode_in [20] \opcode_in [19] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 4 \X_SR - process $group_96 - assign \X_SR 4'0000 - assign \X_SR { \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \X_SX - process $group_97 - assign \X_SX 1'0 - assign \X_SX { \opcode_in [0] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 6 \X_SX_S - process $group_98 - assign \X_SX_S 6'000000 - assign \X_SX_S { \opcode_in [0] \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \X_T - process $group_99 - assign \X_T 5'00000 - assign \X_T { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 10 \X_TBR - process $group_100 - assign \X_TBR 10'0000000000 - assign \X_TBR { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \X_TH - process $group_101 - assign \X_TH 5'00000 - assign \X_TH { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \X_TO - process $group_102 - assign \X_TO 5'00000 - assign \X_TO { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \X_TX - process $group_103 - assign \X_TX 1'0 - assign \X_TX { \opcode_in [0] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 6 \X_TX_T - process $group_104 - assign \X_TX_T 6'000000 - assign \X_TX_T { \opcode_in [0] \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 4 \X_U - process $group_105 - assign \X_U 4'0000 - assign \X_U { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \X_UIM - process $group_106 - assign \X_UIM 5'00000 - assign \X_UIM { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \X_VRS - process $group_107 - assign \X_VRS 5'00000 - assign \X_VRS { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \X_VRT - process $group_108 - assign \X_VRT 5'00000 - assign \X_VRT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \X_W - process $group_109 - assign \X_W 1'0 - assign \X_W { \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 2 \X_WC - process $group_110 - assign \X_WC 2'00 - assign \X_WC { \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 10 \X_XO - process $group_111 - assign \X_XO 10'0000000000 - assign \X_XO { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 8 \X_XO_1 - process $group_112 - assign \X_XO_1 8'00000000 - assign \X_XO_1 { \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \B_AA - process $group_113 - assign \B_AA 1'0 - assign \B_AA { \opcode_in [1] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 14 \B_BD - process $group_114 - assign \B_BD 14'00000000000000 - assign \B_BD { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \B_BI - process $group_115 - assign \B_BI 5'00000 - assign \B_BI { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \B_BO - process $group_116 - assign \B_BO 5'00000 - assign \B_BO { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \B_LK - process $group_117 - assign \B_LK 1'0 - assign \B_LK { \opcode_in [0] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \I_AA - process $group_118 - assign \I_AA 1'0 - assign \I_AA { \opcode_in [1] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 24 \I_LI - process $group_119 - assign \I_LI 24'000000000000000000000000 - assign \I_LI { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \I_LK - process $group_120 - assign \I_LK 1'0 - assign \I_LK { \opcode_in [0] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \XX3_AX - process $group_121 - assign \XX3_AX 1'0 - assign \XX3_AX { \opcode_in [2] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \XX3_A - process $group_122 - assign \XX3_A 5'00000 - assign \XX3_A { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 6 \XX3_AX_A - process $group_123 - assign \XX3_AX_A 6'000000 - assign \XX3_AX_A { \opcode_in [2] \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 3 \XX3_BF - process $group_124 - assign \XX3_BF 3'000 - assign \XX3_BF { \opcode_in [25] \opcode_in [24] \opcode_in [23] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \XX3_BX - process $group_125 - assign \XX3_BX 1'0 - assign \XX3_BX { \opcode_in [1] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \XX3_B - process $group_126 - assign \XX3_B 5'00000 - assign \XX3_B { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 6 \XX3_BX_B - process $group_127 - assign \XX3_BX_B 6'000000 - assign \XX3_BX_B { \opcode_in [1] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 2 \XX3_DM - process $group_128 - assign \XX3_DM 2'00 - assign \XX3_DM { \opcode_in [9] \opcode_in [8] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \XX3_Rc - process $group_129 - assign \XX3_Rc 1'0 - assign \XX3_Rc { \opcode_in [10] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 2 \XX3_SHW - process $group_130 - assign \XX3_SHW 2'00 - assign \XX3_SHW { \opcode_in [9] \opcode_in [8] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \XX3_TX - process $group_131 - assign \XX3_TX 1'0 - assign \XX3_TX { \opcode_in [0] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \XX3_T - process $group_132 - assign \XX3_T 5'00000 - assign \XX3_T { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 6 \XX3_TX_T - process $group_133 - assign \XX3_TX_T 6'000000 - assign \XX3_TX_T { \opcode_in [0] \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 4 \XX3_XO - process $group_134 - assign \XX3_XO 4'0000 - assign \XX3_XO { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 8 \XX3_XO_1 - process $group_135 - assign \XX3_XO_1 8'00000000 - assign \XX3_XO_1 { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 9 \XX3_XO_2 - process $group_136 - assign \XX3_XO_2 9'000000000 - assign \XX3_XO_2 { \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \XX4_AX - process $group_137 - assign \XX4_AX 1'0 - assign \XX4_AX { \opcode_in [2] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \XX4_A - process $group_138 - assign \XX4_A 5'00000 - assign \XX4_A { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 6 \XX4_AX_A - process $group_139 - assign \XX4_AX_A 6'000000 - assign \XX4_AX_A { \opcode_in [2] \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \XX4_BX - process $group_140 - assign \XX4_BX 1'0 - assign \XX4_BX { \opcode_in [1] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \XX4_B - process $group_141 - assign \XX4_B 5'00000 - assign \XX4_B { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 6 \XX4_BX_B - process $group_142 - assign \XX4_BX_B 6'000000 - assign \XX4_BX_B { \opcode_in [1] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \XX4_CX - process $group_143 - assign \XX4_CX 1'0 - assign \XX4_CX { \opcode_in [3] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \XX4_C - process $group_144 - assign \XX4_C 5'00000 - assign \XX4_C { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 6 \XX4_CX_C - process $group_145 - assign \XX4_CX_C 6'000000 - assign \XX4_CX_C { \opcode_in [3] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \XX4_TX - process $group_146 - assign \XX4_TX 1'0 - assign \XX4_TX { \opcode_in [0] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \XX4_T - process $group_147 - assign \XX4_T 5'00000 - assign \XX4_T { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 6 \XX4_TX_T - process $group_148 - assign \XX4_TX_T 6'000000 - assign \XX4_TX_T { \opcode_in [0] \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 2 \XX4_XO - process $group_149 - assign \XX4_XO 2'00 - assign \XX4_XO { \opcode_in [5] \opcode_in [4] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \XL_BA - process $group_150 - assign \XL_BA 5'00000 - assign \XL_BA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \XL_BB - process $group_151 - assign \XL_BB 5'00000 - assign \XL_BB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 3 \XL_BF - process $group_152 - assign \XL_BF 3'000 - assign \XL_BF { \opcode_in [25] \opcode_in [24] \opcode_in [23] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 3 \XL_BFA - process $group_153 - assign \XL_BFA 3'000 - assign \XL_BFA { \opcode_in [20] \opcode_in [19] \opcode_in [18] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 2 \XL_BH - process $group_154 - assign \XL_BH 2'00 - assign \XL_BH { \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \XL_BI - process $group_155 - assign \XL_BI 5'00000 - assign \XL_BI { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \XL_BO - process $group_156 - assign \XL_BO 5'00000 - assign \XL_BO { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \XL_BO_1 - process $group_157 - assign \XL_BO_1 5'00000 - assign \XL_BO_1 { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - process $group_158 - assign \XL_BT 5'00000 - assign \XL_BT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \XL_LK - process $group_159 - assign \XL_LK 1'0 - assign \XL_LK { \opcode_in [0] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 15 \XL_OC - process $group_160 - assign \XL_OC 15'000000000000000 - assign \XL_OC { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \XL_S - process $group_161 - assign \XL_S 1'0 - assign \XL_S { \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 10 \XL_XO - process $group_162 - assign \XL_XO 10'0000000000 - assign \XL_XO { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \A_BC - process $group_163 - assign \A_BC 5'00000 - assign \A_BC { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \A_FRA - process $group_164 - assign \A_FRA 5'00000 - assign \A_FRA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \A_FRB - process $group_165 - assign \A_FRB 5'00000 - assign \A_FRB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \A_FRC - process $group_166 - assign \A_FRC 5'00000 - assign \A_FRC { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \A_FRT - process $group_167 - assign \A_FRT 5'00000 - assign \A_FRT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \A_RA - process $group_168 - assign \A_RA 5'00000 - assign \A_RA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \A_RB - process $group_169 - assign \A_RB 5'00000 - assign \A_RB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \A_Rc - process $group_170 - assign \A_Rc 1'0 - assign \A_Rc { \opcode_in [0] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \A_RT - process $group_171 - assign \A_RT 5'00000 - assign \A_RT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \A_XO - process $group_172 - assign \A_XO 5'00000 - assign \A_XO { \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 3 \D_BF - process $group_173 - assign \D_BF 3'000 - assign \D_BF { \opcode_in [25] \opcode_in [24] \opcode_in [23] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 16 \D_D - process $group_174 - assign \D_D 16'0000000000000000 - assign \D_D { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] \opcode_in [0] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \D_FRS - process $group_175 - assign \D_FRS 5'00000 - assign \D_FRS { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \D_FRT - process $group_176 - assign \D_FRT 5'00000 - assign \D_FRT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \D_L - process $group_177 - assign \D_L 1'0 - assign \D_L { \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \D_RA - process $group_178 - assign \D_RA 5'00000 - assign \D_RA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \D_RS - process $group_179 - assign \D_RS 5'00000 - assign \D_RS { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \D_RT - process $group_180 - assign \D_RT 5'00000 - assign \D_RT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 16 \D_SI - process $group_181 - assign \D_SI 16'0000000000000000 - assign \D_SI { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] \opcode_in [0] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \D_TO - process $group_182 - assign \D_TO 5'00000 - assign \D_TO { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 16 \D_UI - process $group_183 - assign \D_UI 16'0000000000000000 - assign \D_UI { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] \opcode_in [0] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 3 \XX2_BF - process $group_184 - assign \XX2_BF 3'000 - assign \XX2_BF { \opcode_in [25] \opcode_in [24] \opcode_in [23] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \XX2_BX - process $group_185 - assign \XX2_BX 1'0 - assign \XX2_BX { \opcode_in [1] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \XX2_B - process $group_186 - assign \XX2_B 5'00000 - assign \XX2_B { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 6 \XX2_BX_B - process $group_187 - assign \XX2_BX_B 6'000000 - assign \XX2_BX_B { \opcode_in [1] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \XX2_dc - process $group_188 - assign \XX2_dc 1'0 - assign \XX2_dc { \opcode_in [6] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \XX2_dm - process $group_189 - assign \XX2_dm 1'0 - assign \XX2_dm { \opcode_in [2] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \XX2_dx - process $group_190 - assign \XX2_dx 5'00000 - assign \XX2_dx { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 7 \XX2_dc_dm_dx - process $group_191 - assign \XX2_dc_dm_dx 7'0000000 - assign \XX2_dc_dm_dx { \opcode_in [6] \opcode_in [2] \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 7 \XX2_DCMX - process $group_192 - assign \XX2_DCMX 7'0000000 - assign \XX2_DCMX { \opcode_in [22] \opcode_in [21] \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \XX2_EO - process $group_193 - assign \XX2_EO 5'00000 - assign \XX2_EO { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \XX2_RT - process $group_194 - assign \XX2_RT 5'00000 - assign \XX2_RT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \XX2_TX - process $group_195 - assign \XX2_TX 1'0 - assign \XX2_TX { \opcode_in [0] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \XX2_T - process $group_196 - assign \XX2_T 5'00000 - assign \XX2_T { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 6 \XX2_TX_T - process $group_197 - assign \XX2_TX_T 6'000000 - assign \XX2_TX_T { \opcode_in [0] \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 4 \XX2_UIM - process $group_198 - assign \XX2_UIM 4'0000 - assign \XX2_UIM { \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 2 \XX2_UIM_1 - process $group_199 - assign \XX2_UIM_1 2'00 - assign \XX2_UIM_1 { \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 7 \XX2_XO - process $group_200 - assign \XX2_XO 7'0000000 - assign \XX2_XO { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [5] \opcode_in [4] \opcode_in [3] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 9 \XX2_XO_1 - process $group_201 - assign \XX2_XO_1 9'000000000 - assign \XX2_XO_1 { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 3 \Z22_BF - process $group_202 - assign \Z22_BF 3'000 - assign \Z22_BF { \opcode_in [25] \opcode_in [24] \opcode_in [23] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 6 \Z22_DCM - process $group_203 - assign \Z22_DCM 6'000000 - assign \Z22_DCM { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 6 \Z22_DGM - process $group_204 - assign \Z22_DGM 6'000000 - assign \Z22_DGM { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \Z22_FRA - process $group_205 - assign \Z22_FRA 5'00000 - assign \Z22_FRA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \Z22_FRAp - process $group_206 - assign \Z22_FRAp 5'00000 - assign \Z22_FRAp { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \Z22_FRT - process $group_207 - assign \Z22_FRT 5'00000 - assign \Z22_FRT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \Z22_FRTp - process $group_208 - assign \Z22_FRTp 5'00000 - assign \Z22_FRTp { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \Z22_Rc - process $group_209 - assign \Z22_Rc 1'0 - assign \Z22_Rc { \opcode_in [0] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 6 \Z22_SH - process $group_210 - assign \Z22_SH 6'000000 - assign \Z22_SH { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 9 \Z22_XO - process $group_211 - assign \Z22_XO 9'000000000 - assign \Z22_XO { \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 3 \EVS_BFA - process $group_212 - assign \EVS_BFA 3'000 - assign \EVS_BFA { \opcode_in [2] \opcode_in [1] \opcode_in [0] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 10 \XFX_BHRBE - process $group_213 - assign \XFX_BHRBE 10'0000000000 - assign \XFX_BHRBE { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \XFX_DUI - process $group_214 - assign \XFX_DUI 5'00000 - assign \XFX_DUI { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 10 \XFX_DUIS - process $group_215 - assign \XFX_DUIS 10'0000000000 - assign \XFX_DUIS { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 8 \XFX_FXM - process $group_216 - assign \XFX_FXM 8'00000000 - assign \XFX_FXM { \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \XFX_RS - process $group_217 - assign \XFX_RS 5'00000 - assign \XFX_RS { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \XFX_RT - process $group_218 - assign \XFX_RT 5'00000 - assign \XFX_RT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 10 \XFX_SPR - process $group_219 - assign \XFX_SPR 10'0000000000 - assign \XFX_SPR { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 10 \XFX_XO - process $group_220 - assign \XFX_XO 10'0000000000 - assign \XFX_XO { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 10 \DX_d0 - process $group_221 - assign \DX_d0 10'0000000000 - assign \DX_d0 { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \DX_d1 - process $group_222 - assign \DX_d1 5'00000 - assign \DX_d1 { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \DX_d2 - process $group_223 - assign \DX_d2 1'0 - assign \DX_d2 { \opcode_in [0] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 16 \DX_d0_d1_d2 - process $group_224 - assign \DX_d0_d1_d2 16'0000000000000000 - assign \DX_d0_d1_d2 { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] \opcode_in [0] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \DX_RT - process $group_225 - assign \DX_RT 5'00000 - assign \DX_RT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \DX_XO - process $group_226 - assign \DX_XO 5'00000 - assign \DX_XO { \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 12 \DQ_DQ - process $group_227 - assign \DQ_DQ 12'000000000000 - assign \DQ_DQ { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 4 \DQ_PT - process $group_228 - assign \DQ_PT 4'0000 - assign \DQ_PT { \opcode_in [3] \opcode_in [2] \opcode_in [1] \opcode_in [0] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \DQ_RA - process $group_229 - assign \DQ_RA 5'00000 - assign \DQ_RA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \DQ_RTp - process $group_230 - assign \DQ_RTp 5'00000 - assign \DQ_RTp { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \DQ_SX - process $group_231 - assign \DQ_SX 1'0 - assign \DQ_SX { \opcode_in [3] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \DQ_S - process $group_232 - assign \DQ_S 5'00000 - assign \DQ_S { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 6 \DQ_SX_S - process $group_233 - assign \DQ_SX_S 6'000000 - assign \DQ_SX_S { \opcode_in [3] \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \DQ_TX - process $group_234 - assign \DQ_TX 1'0 - assign \DQ_TX { \opcode_in [3] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \DQ_T - process $group_235 - assign \DQ_T 5'00000 - assign \DQ_T { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 6 \DQ_TX_T - process $group_236 - assign \DQ_TX_T 6'000000 - assign \DQ_TX_T { \opcode_in [3] \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 3 \DQ_XO - process $group_237 - assign \DQ_XO 3'000 - assign \DQ_XO { \opcode_in [2] \opcode_in [1] \opcode_in [0] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 14 \DS_DS - process $group_238 - assign \DS_DS 14'00000000000000 - assign \DS_DS { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \DS_FRSp - process $group_239 - assign \DS_FRSp 5'00000 - assign \DS_FRSp { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \DS_FRTp - process $group_240 - assign \DS_FRTp 5'00000 - assign \DS_FRTp { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \DS_RA - process $group_241 - assign \DS_RA 5'00000 - assign \DS_RA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \DS_RS - process $group_242 - assign \DS_RS 5'00000 - assign \DS_RS { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \DS_RSp - process $group_243 - assign \DS_RSp 5'00000 - assign \DS_RSp { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \DS_RT - process $group_244 - assign \DS_RT 5'00000 - assign \DS_RT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \DS_VRS - process $group_245 - assign \DS_VRS 5'00000 - assign \DS_VRS { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \DS_VRT - process $group_246 - assign \DS_VRT 5'00000 - assign \DS_VRT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 2 \DS_XO - process $group_247 - assign \DS_XO 2'00 - assign \DS_XO { \opcode_in [1] \opcode_in [0] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \VX_EO - process $group_248 - assign \VX_EO 5'00000 - assign \VX_EO { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \VX_PS - process $group_249 - assign \VX_PS 1'0 - assign \VX_PS { \opcode_in [9] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \VX_RA - process $group_250 - assign \VX_RA 5'00000 - assign \VX_RA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \VX_RT - process $group_251 - assign \VX_RT 5'00000 - assign \VX_RT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \VX_SIM - process $group_252 - assign \VX_SIM 5'00000 - assign \VX_SIM { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \VX_UIM - process $group_253 - assign \VX_UIM 5'00000 - assign \VX_UIM { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 4 \VX_UIM_1 - process $group_254 - assign \VX_UIM_1 4'0000 - assign \VX_UIM_1 { \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 3 \VX_UIM_2 - process $group_255 - assign \VX_UIM_2 3'000 - assign \VX_UIM_2 { \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 2 \VX_UIM_3 - process $group_256 - assign \VX_UIM_3 2'00 - assign \VX_UIM_3 { \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \VX_VRA - process $group_257 - assign \VX_VRA 5'00000 - assign \VX_VRA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \VX_VRB - process $group_258 - assign \VX_VRB 5'00000 - assign \VX_VRB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \VX_VRT - process $group_259 - assign \VX_VRT 5'00000 - assign \VX_VRT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 10 \VX_XO - process $group_260 - assign \VX_XO 10'0000000000 - assign \VX_XO { \opcode_in [10] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] \opcode_in [0] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 11 \VX_XO_1 - process $group_261 - assign \VX_XO_1 11'00000000000 - assign \VX_XO_1 { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] \opcode_in [0] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 8 \XFL_FLM - process $group_262 - assign \XFL_FLM 8'00000000 - assign \XFL_FLM { \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \XFL_FRB - process $group_263 - assign \XFL_FRB 5'00000 - assign \XFL_FRB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \XFL_L - process $group_264 - assign \XFL_L 1'0 - assign \XFL_L { \opcode_in [25] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \XFL_Rc - process $group_265 - assign \XFL_Rc 1'0 - assign \XFL_Rc { \opcode_in [0] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \XFL_W - process $group_266 - assign \XFL_W 1'0 - assign \XFL_W { \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 10 \XFL_XO - process $group_267 - assign \XFL_XO 10'0000000000 - assign \XFL_XO { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \Z23_FRA - process $group_268 - assign \Z23_FRA 5'00000 - assign \Z23_FRA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \Z23_FRAp - process $group_269 - assign \Z23_FRAp 5'00000 - assign \Z23_FRAp { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \Z23_FRB - process $group_270 - assign \Z23_FRB 5'00000 - assign \Z23_FRB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \Z23_FRBp - process $group_271 - assign \Z23_FRBp 5'00000 - assign \Z23_FRBp { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \Z23_FRT - process $group_272 - assign \Z23_FRT 5'00000 - assign \Z23_FRT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \Z23_FRTp - process $group_273 - assign \Z23_FRTp 5'00000 - assign \Z23_FRTp { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \Z23_R - process $group_274 - assign \Z23_R 1'0 - assign \Z23_R { \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \Z23_Rc - process $group_275 - assign \Z23_Rc 1'0 - assign \Z23_Rc { \opcode_in [0] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 2 \Z23_RMC - process $group_276 - assign \Z23_RMC 2'00 - assign \Z23_RMC { \opcode_in [10] \opcode_in [9] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \Z23_TE - process $group_277 - assign \Z23_TE 5'00000 - assign \Z23_TE { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 8 \Z23_XO - process $group_278 - assign \Z23_XO 8'00000000 - assign \Z23_XO { \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \MDS_IB - process $group_279 - assign \MDS_IB 5'00000 - assign \MDS_IB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \MDS_IS - process $group_280 - assign \MDS_IS 5'00000 - assign \MDS_IS { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 6 \MDS_mb - process $group_281 - assign \MDS_mb 6'000000 - assign \MDS_mb { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 6 \MDS_me - process $group_282 - assign \MDS_me 6'000000 - assign \MDS_me { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \MDS_RA - process $group_283 - assign \MDS_RA 5'00000 - assign \MDS_RA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \MDS_RB - process $group_284 - assign \MDS_RB 5'00000 - assign \MDS_RB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \MDS_Rc - process $group_285 - assign \MDS_Rc 1'0 - assign \MDS_Rc { \opcode_in [0] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \MDS_RS - process $group_286 - assign \MDS_RS 5'00000 - assign \MDS_RS { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 4 \MDS_XBI - process $group_287 - assign \MDS_XBI 4'0000 - assign \MDS_XBI { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 4 \MDS_XBI_1 - process $group_288 - assign \MDS_XBI_1 4'0000 - assign \MDS_XBI_1 { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 4 \MDS_XO - process $group_289 - assign \MDS_XO 4'0000 - assign \MDS_XO { \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 7 \SC_LEV - process $group_290 - assign \SC_LEV 7'0000000 - assign \SC_LEV { \opcode_in [11] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \SC_XO - process $group_291 - assign \SC_XO 1'0 - assign \SC_XO { \opcode_in [1] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 2 \SC_XO_1 - process $group_292 - assign \SC_XO_1 2'00 - assign \SC_XO_1 { \opcode_in [1] \opcode_in [0] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \M_MB - process $group_293 - assign \M_MB 5'00000 - assign \M_MB { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \M_ME - process $group_294 - assign \M_ME 5'00000 - assign \M_ME { \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \M_RA - process $group_295 - assign \M_RA 5'00000 - assign \M_RA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \M_RB - process $group_296 - assign \M_RB 5'00000 - assign \M_RB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \M_Rc - process $group_297 - assign \M_Rc 1'0 - assign \M_Rc { \opcode_in [0] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \M_RS - process $group_298 - assign \M_RS 5'00000 - assign \M_RS { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \M_SH - process $group_299 - assign \M_SH 5'00000 - assign \M_SH { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 6 \MD_mb - process $group_300 - assign \MD_mb 6'000000 - assign \MD_mb { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 6 \MD_me - process $group_301 - assign \MD_me 6'000000 - assign \MD_me { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \MD_RA - process $group_302 - assign \MD_RA 5'00000 - assign \MD_RA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \MD_Rc - process $group_303 - assign \MD_Rc 1'0 - assign \MD_Rc { \opcode_in [0] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \MD_RS - process $group_304 - assign \MD_RS 5'00000 - assign \MD_RS { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 6 \MD_sh - process $group_305 - assign \MD_sh 6'000000 - assign \MD_sh { \opcode_in [1] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 3 \MD_XO - process $group_306 - assign \MD_XO 3'000 - assign \MD_XO { \opcode_in [4] \opcode_in [3] \opcode_in [2] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 6 \all_OPCD - process $group_307 - assign \all_OPCD 6'000000 - assign \all_OPCD { \opcode_in [31] \opcode_in [30] \opcode_in [29] \opcode_in [28] \opcode_in [27] \opcode_in [26] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 6 \all_PO - process $group_308 - assign \all_PO 6'000000 - assign \all_PO { \opcode_in [31] \opcode_in [30] \opcode_in [29] \opcode_in [28] \opcode_in [27] \opcode_in [26] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \XO_OE - process $group_309 - assign \XO_OE 1'0 - assign \XO_OE { \opcode_in [10] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \XO_RA - process $group_310 - assign \XO_RA 5'00000 - assign \XO_RA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \XO_RB - process $group_311 - assign \XO_RB 5'00000 - assign \XO_RB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \XO_Rc - process $group_312 - assign \XO_Rc 1'0 - assign \XO_Rc { \opcode_in [0] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \XO_RT - process $group_313 - assign \XO_RT 5'00000 - assign \XO_RT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 9 \XO_XO - process $group_314 - assign \XO_XO 9'000000000 - assign \XO_XO { \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \DQE_RA - process $group_315 - assign \DQE_RA 5'00000 - assign \DQE_RA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \DQE_RT - process $group_316 - assign \DQE_RT 5'00000 - assign \DQE_RT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 2 \DQE_XO - process $group_317 - assign \DQE_XO 2'00 - assign \DQE_XO { \opcode_in [1] \opcode_in [0] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \TX_RA - process $group_318 - assign \TX_RA 5'00000 - assign \TX_RA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \TX_UI - process $group_319 - assign \TX_UI 5'00000 - assign \TX_UI { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 4 \TX_XBI - process $group_320 - assign \TX_XBI 4'0000 - assign \TX_XBI { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 6 \TX_XO - process $group_321 - assign \TX_XO 6'000000 - assign \TX_XO { \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \VA_RA - process $group_322 - assign \VA_RA 5'00000 - assign \VA_RA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \VA_RB - process $group_323 - assign \VA_RB 5'00000 - assign \VA_RB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \VA_RC - process $group_324 - assign \VA_RC 5'00000 - assign \VA_RC { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \VA_RT - process $group_325 - assign \VA_RT 5'00000 - assign \VA_RT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 4 \VA_SHB - process $group_326 - assign \VA_SHB 4'0000 - assign \VA_SHB { \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \VA_VRA - process $group_327 - assign \VA_VRA 5'00000 - assign \VA_VRA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \VA_VRB - process $group_328 - assign \VA_VRB 5'00000 - assign \VA_VRB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \VA_VRC - process $group_329 - assign \VA_VRC 5'00000 - assign \VA_VRC { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \VA_VRT - process $group_330 - assign \VA_VRT 5'00000 - assign \VA_VRT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 6 \VA_XO - process $group_331 - assign \VA_XO 6'000000 - assign \VA_XO { \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] \opcode_in [0] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \XS_RA - process $group_332 - assign \XS_RA 5'00000 - assign \XS_RA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \XS_Rc - process $group_333 - assign \XS_Rc 1'0 - assign \XS_Rc { \opcode_in [0] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \XS_RS - process $group_334 - assign \XS_RS 5'00000 - assign \XS_RS { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 6 \XS_sh - process $group_335 - assign \XS_sh 6'000000 - assign \XS_sh { \opcode_in [1] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 9 \XS_XO - process $group_336 - assign \XS_XO 9'000000000 - assign \XS_XO { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \VC_Rc - process $group_337 - assign \VC_Rc 1'0 - assign \VC_Rc { \opcode_in [10] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \VC_VRA - process $group_338 - assign \VC_VRA 5'00000 - assign \VC_VRA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \VC_VRB - process $group_339 - assign \VC_VRB 5'00000 - assign \VC_VRB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \VC_VRT - process $group_340 - assign \VC_VRT 5'00000 - assign \VC_VRT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 10 \VC_XO - process $group_341 - assign \VC_XO 10'0000000000 - assign \VC_XO { \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] \opcode_in [0] } - sync init - end - connect \BRANCH_function_unit$1 11'00000000000 - connect \BRANCH_function_unit$2 11'00000000000 - connect \BRANCH_function_unit$3 11'00000000000 - connect \BRANCH_internal_op$4 7'0000000 - connect \BRANCH_internal_op$5 7'0000000 - connect \BRANCH_internal_op$6 7'0000000 - connect \BRANCH_in2_sel$7 4'0000 - connect \BRANCH_in2_sel$8 4'0000 - connect \BRANCH_in2_sel$9 4'0000 - connect \BRANCH_cr_in$10 3'000 - connect \BRANCH_cr_in$11 3'000 - connect \BRANCH_cr_in$12 3'000 - connect \BRANCH_cr_out$13 3'000 - connect \BRANCH_cr_out$14 3'000 - connect \BRANCH_cr_out$15 3'000 - connect \BRANCH_rc_sel$16 2'00 - connect \BRANCH_rc_sel$17 2'00 - connect \BRANCH_rc_sel$18 2'00 - connect \BRANCH_is_32b$19 1'0 - connect \BRANCH_is_32b$20 1'0 - connect \BRANCH_is_32b$21 1'0 - connect \BRANCH_lk$22 1'0 - connect \BRANCH_lk$23 1'0 - connect \BRANCH_lk$24 1'0 -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.dec_BRANCH.dec_rc" -module \dec_rc$145 - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:404" - wire width 2 input 0 \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 1 \rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 1 input 2 \BRANCH_Rc - process $group_0 - assign \rc 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:413" - switch \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:414" - attribute \nmigen.decoding "RC/2" - case 2'10 - assign \rc \BRANCH_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:417" - attribute \nmigen.decoding "ONE/1" - case 2'01 - assign \rc 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:420" - attribute \nmigen.decoding "NONE/0" - case 2'00 - assign \rc 1'0 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \rc_ok - process $group_1 - assign \rc_ok 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:413" - switch \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:414" - attribute \nmigen.decoding "RC/2" - case 2'10 - assign \rc_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:417" - attribute \nmigen.decoding "ONE/1" - case 2'01 - assign \rc_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:420" - attribute \nmigen.decoding "NONE/0" - case 2'00 - assign \rc_ok 1'1 - end - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.dec_BRANCH.dec_oe" -module \dec_oe$146 - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:441" - wire width 2 input 0 \sel_in - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 7 input 1 \BRANCH_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 1 input 2 \BRANCH_OE - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \oe - process $group_0 - assign \oe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:450" - switch \BRANCH_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:461" - attribute \nmigen.decoding "OP_MUL_H64/51|OP_MUL_H32/52|OP_EXTS/31|OP_CNTZ/14|OP_SHL/60|OP_SHR/61|OP_RLC/56|OP_LOAD/37|OP_STORE/38|OP_RLCL/57|OP_RLCR/58|OP_EXTSWSLI/32" - case 7'0110011, 7'0110100, 7'0011111, 7'0001110, 7'0111100, 7'0111101, 7'0111000, 7'0100101, 7'0100110, 7'0111001, 7'0111010, 7'0100000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:465" - attribute \nmigen.decoding "" - case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:467" - switch \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:468" - attribute \nmigen.decoding "RC/2" - case 2'10 - assign \oe \BRANCH_OE - end - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \oe_ok - process $group_1 - assign \oe_ok 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:450" - switch \BRANCH_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:461" - attribute \nmigen.decoding "OP_MUL_H64/51|OP_MUL_H32/52|OP_EXTS/31|OP_CNTZ/14|OP_SHL/60|OP_SHR/61|OP_RLC/56|OP_LOAD/37|OP_STORE/38|OP_RLCL/57|OP_RLCR/58|OP_EXTSWSLI/32" - case 7'0110011, 7'0110100, 7'0011111, 7'0001110, 7'0111100, 7'0111101, 7'0111000, 7'0100101, 7'0100110, 7'0111001, 7'0111010, 7'0100000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:465" - attribute \nmigen.decoding "" - case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:467" - switch \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:468" - attribute \nmigen.decoding "RC/2" - case 2'10 - assign \oe_ok 1'1 - end - end - sync init - end -end -attribute \generator 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"OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 7 input 2 \BRANCH_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 5 input 3 \BRANCH_BB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 5 input 4 \BRANCH_BA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 5 input 5 \BRANCH_BT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 8 input 6 \BRANCH_FXM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 5 input 7 \BRANCH_BI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 5 input 8 \BRANCH_BC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 3 input 9 \X_BFA - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" - wire width 8 \ppick_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" - wire width 8 \ppick_o - cell \ppick$148 \ppick - connect \i \ppick_i - connect \o \ppick_o - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \cr_bitfield_ok - process $group_0 - assign \cr_bitfield_ok 1'0 - assign \cr_bitfield_ok 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" - switch \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" - attribute \nmigen.decoding "NONE/0" - case 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:505" - attribute \nmigen.decoding "CR0/1" - case 3'001 - assign \cr_bitfield_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:508" - attribute \nmigen.decoding "BI/2" - case 3'010 - assign \cr_bitfield_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:511" - attribute \nmigen.decoding "BFA/3" - case 3'011 - assign \cr_bitfield_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:514" - attribute \nmigen.decoding "BA_BB/4" - case 3'100 - assign \cr_bitfield_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:521" - attribute \nmigen.decoding "BC/5" - case 3'101 - assign \cr_bitfield_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:524" - attribute \nmigen.decoding "WHOLE_REG/6" - case 3'110 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \cr_bitfield_b_ok - process $group_1 - assign \cr_bitfield_b_ok 1'0 - assign \cr_bitfield_b_ok 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" - switch \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" - attribute \nmigen.decoding "NONE/0" - case 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:505" - attribute \nmigen.decoding "CR0/1" - case 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:508" - attribute \nmigen.decoding "BI/2" - case 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:511" - attribute \nmigen.decoding "BFA/3" - case 3'011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:514" - attribute \nmigen.decoding "BA_BB/4" - case 3'100 - assign \cr_bitfield_b_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:521" - attribute \nmigen.decoding "BC/5" - case 3'101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:524" - attribute \nmigen.decoding "WHOLE_REG/6" - case 3'110 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \cr_fxm_ok - process $group_2 - assign \cr_fxm_ok 1'0 - assign \cr_fxm_ok 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" - switch \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" - attribute \nmigen.decoding "NONE/0" - case 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:505" - attribute \nmigen.decoding "CR0/1" - case 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:508" - attribute \nmigen.decoding "BI/2" - case 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:511" - attribute \nmigen.decoding "BFA/3" - case 3'011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:514" - attribute \nmigen.decoding "BA_BB/4" - case 3'100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:521" - attribute \nmigen.decoding "BC/5" - case 3'101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:524" - attribute \nmigen.decoding "WHOLE_REG/6" - case 3'110 - assign \cr_fxm_ok 1'1 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 3 \cr_bitfield - process $group_3 - assign \cr_bitfield 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" - switch \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" - attribute \nmigen.decoding "NONE/0" - case 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:505" - attribute \nmigen.decoding "CR0/1" - case 3'001 - assign \cr_bitfield 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:508" - attribute \nmigen.decoding "BI/2" - case 3'010 - assign \cr_bitfield \BRANCH_BI [4:2] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:511" - attribute \nmigen.decoding "BFA/3" - case 3'011 - assign \cr_bitfield \X_BFA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:514" - attribute \nmigen.decoding "BA_BB/4" - case 3'100 - assign \cr_bitfield \BRANCH_BA [4:2] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:521" - attribute \nmigen.decoding "BC/5" - case 3'101 - assign \cr_bitfield \BRANCH_BC [4:2] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:524" - attribute \nmigen.decoding "WHOLE_REG/6" - case 3'110 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 3 \cr_bitfield_b - process $group_4 - assign \cr_bitfield_b 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" - switch \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" - attribute \nmigen.decoding "NONE/0" - case 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:505" - attribute \nmigen.decoding "CR0/1" - case 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:508" - attribute \nmigen.decoding "BI/2" - case 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:511" - attribute \nmigen.decoding "BFA/3" - case 3'011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:514" - attribute \nmigen.decoding "BA_BB/4" - case 3'100 - assign \cr_bitfield_b \BRANCH_BB [4:2] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:521" - attribute \nmigen.decoding "BC/5" - case 3'101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:524" - attribute \nmigen.decoding "WHOLE_REG/6" - case 3'110 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 3 \cr_bitfield_o - process $group_5 - assign \cr_bitfield_o 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" - switch \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" - attribute \nmigen.decoding "NONE/0" - case 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:505" - attribute \nmigen.decoding "CR0/1" - case 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:508" - attribute \nmigen.decoding "BI/2" - case 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:511" - attribute \nmigen.decoding "BFA/3" - case 3'011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:514" - attribute \nmigen.decoding "BA_BB/4" - case 3'100 - assign \cr_bitfield_o \BRANCH_BT [4:2] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:521" - attribute \nmigen.decoding "BC/5" - case 3'101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:524" - attribute \nmigen.decoding "WHOLE_REG/6" - case 3'110 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \cr_bitfield_o_ok - process $group_6 - assign \cr_bitfield_o_ok 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" - switch \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" - attribute \nmigen.decoding "NONE/0" - case 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:505" - attribute \nmigen.decoding "CR0/1" - case 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:508" - attribute \nmigen.decoding "BI/2" - case 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:511" - attribute \nmigen.decoding "BFA/3" - case 3'011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:514" - attribute \nmigen.decoding "BA_BB/4" - case 3'100 - assign \cr_bitfield_o_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:521" - attribute \nmigen.decoding "BC/5" - case 3'101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:524" - attribute \nmigen.decoding "WHOLE_REG/6" - case 3'110 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:526" - wire width 1 \move_one - process $group_7 - assign \move_one 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" - switch \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" - attribute \nmigen.decoding "NONE/0" - case 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:505" - attribute \nmigen.decoding "CR0/1" - case 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:508" - attribute \nmigen.decoding "BI/2" - case 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:511" - attribute \nmigen.decoding "BFA/3" - case 3'011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:514" - attribute \nmigen.decoding "BA_BB/4" - case 3'100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:521" - attribute \nmigen.decoding "BC/5" - case 3'101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:524" - attribute \nmigen.decoding "WHOLE_REG/6" - case 3'110 - assign \move_one \insn_in [20] - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" - cell $eq $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A \BRANCH_internal_op - connect \B 7'0101101 - connect \Y $1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" - wire width 1 $3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" - cell $and $4 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $1 - connect \B \move_one - connect \Y $3 - end - process $group_8 - assign \ppick_i 8'00000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" - switch \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" - attribute \nmigen.decoding "NONE/0" - case 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:505" - attribute \nmigen.decoding "CR0/1" - case 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:508" - attribute \nmigen.decoding "BI/2" - case 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:511" - attribute \nmigen.decoding "BFA/3" - case 3'011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:514" - attribute \nmigen.decoding "BA_BB/4" - case 3'100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:521" - attribute \nmigen.decoding "BC/5" - case 3'101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:524" - attribute \nmigen.decoding "WHOLE_REG/6" - case 3'110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" - switch { $3 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" - case 1'1 - assign \ppick_i \BRANCH_FXM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532" - case - end - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 8 \cr_fxm - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" - wire width 1 $5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" - cell $eq $6 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A \BRANCH_internal_op - connect \B 7'0101101 - connect \Y $5 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" - wire width 1 $7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" - cell $and $8 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $5 - connect \B \move_one - connect \Y $7 - end - process $group_9 - assign \cr_fxm 8'00000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" - switch \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" - attribute \nmigen.decoding "NONE/0" - case 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:505" - attribute \nmigen.decoding "CR0/1" - case 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:508" - attribute \nmigen.decoding "BI/2" - case 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:511" - attribute \nmigen.decoding "BFA/3" - case 3'011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:514" - attribute \nmigen.decoding "BA_BB/4" - case 3'100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:521" - attribute \nmigen.decoding "BC/5" - case 3'101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:524" - attribute \nmigen.decoding "WHOLE_REG/6" - case 3'110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" - switch { $7 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" - case 1'1 - assign \cr_fxm \ppick_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532" - case - assign \cr_fxm 8'11111111 - end - end - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.dec_BRANCH.dec_cr_out.ppick" -module \ppick$150 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" - wire width 8 input 0 \i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" - wire width 1 output 1 \en_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" - wire width 8 output 2 \o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:49" - wire width 8 \ni - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" - wire width 8 $1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" - cell $not $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \Y_WIDTH 8 - connect \A { \i [0] \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] } - connect \Y $1 - end - process $group_0 - assign \ni 8'00000000 - assign \ni $1 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire width 1 \t0 - process $group_1 - assign \t0 1'0 - assign \t0 \i [7] - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire width 1 \t1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire width 1 $3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire width 1 $4 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_bool $5 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A { \i [7] \ni [1] } - connect \Y $4 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $6 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $4 - connect \Y $3 - end - process $group_2 - assign \t1 1'0 - assign \t1 $3 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire width 1 \t2 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire width 1 $7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire width 1 $8 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_bool $9 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A { \i [6] \i [7] \ni [2] } - connect \Y $8 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $10 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $8 - connect \Y $7 - end - process $group_3 - assign \t2 1'0 - assign \t2 $7 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire width 1 \t3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire width 1 $11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire width 1 $12 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_bool $13 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A { \i [5] \i [6] \i [7] \ni [3] } - connect \Y $12 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $14 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $12 - connect \Y $11 - end - process $group_4 - assign \t3 1'0 - assign \t3 $11 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire width 1 \t4 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire width 1 $15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire width 1 $16 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_bool $17 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A { \i [4] \i [5] \i [6] \i [7] \ni [4] } - connect \Y $16 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $18 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $16 - connect \Y $15 - end - process $group_5 - assign \t4 1'0 - assign \t4 $15 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire width 1 \t5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire width 1 $19 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire width 1 $20 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_bool $21 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \Y_WIDTH 1 - connect \A { \i [3] \i [4] \i [5] \i [6] \i [7] \ni [5] } - connect \Y $20 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $22 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $20 - connect \Y $19 - end - process $group_6 - assign \t5 1'0 - assign \t5 $19 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire width 1 \t6 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire width 1 $23 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire width 1 $24 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_bool $25 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A { \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [6] } - connect \Y $24 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $26 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $24 - connect \Y $23 - end - process $group_7 - assign \t6 1'0 - assign \t6 $23 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire width 1 \t7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire width 1 $27 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire width 1 $28 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_bool $29 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A { \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [7] } - connect \Y $28 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $30 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $28 - connect \Y $27 - end - process $group_8 - assign \t7 1'0 - assign \t7 $27 - sync init - end - process $group_9 - assign \o 8'00000000 - assign \o { \t0 \t1 \t2 \t3 \t4 \t5 \t6 \t7 } - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" - wire width 1 $31 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" - cell $reduce_bool $32 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \o - connect \Y $31 - end - process $group_10 - assign \en_o 1'0 - assign \en_o $31 - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.dec_BRANCH.dec_cr_out" -module \dec_cr_out$149 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:550" - wire width 32 input 0 \insn_in - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:549" - wire width 3 input 1 \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:548" - wire width 1 input 2 \rc_in - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 7 input 3 \BRANCH_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 8 input 4 \BRANCH_FXM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 3 input 5 \X_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 input 6 \XL_BT - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" - wire width 8 \ppick_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" - wire width 1 \ppick_en_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" - wire width 8 \ppick_o - cell \ppick$150 \ppick - connect \i \ppick_i - connect \en_o \ppick_en_o - connect \o \ppick_o - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \cr_bitfield_ok - process $group_0 - assign \cr_bitfield_ok 1'0 - assign \cr_bitfield_ok 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:563" - switch \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:564" - attribute \nmigen.decoding "NONE/0" - case 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:566" - attribute \nmigen.decoding "CR0/1" - case 3'001 - assign \cr_bitfield_ok \rc_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:569" - attribute \nmigen.decoding "BF/2" - case 3'010 - assign \cr_bitfield_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:572" - attribute \nmigen.decoding "BT/3" - case 3'011 - assign \cr_bitfield_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:575" - attribute \nmigen.decoding "WHOLE_REG/4" - case 3'100 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \cr_fxm_ok - process $group_1 - assign \cr_fxm_ok 1'0 - assign \cr_fxm_ok 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:563" - switch \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:564" - attribute \nmigen.decoding "NONE/0" - case 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:566" - attribute \nmigen.decoding "CR0/1" - case 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:569" - attribute \nmigen.decoding "BF/2" - case 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:572" - attribute \nmigen.decoding "BT/3" - case 3'011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:575" - attribute \nmigen.decoding "WHOLE_REG/4" - case 3'100 - assign \cr_fxm_ok 1'1 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 3 \cr_bitfield - process $group_2 - assign \cr_bitfield 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:563" - switch \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:564" - attribute \nmigen.decoding "NONE/0" - case 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:566" - attribute \nmigen.decoding "CR0/1" - case 3'001 - assign \cr_bitfield 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:569" - attribute \nmigen.decoding "BF/2" - case 3'010 - assign \cr_bitfield \X_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:572" - attribute \nmigen.decoding "BT/3" - case 3'011 - assign \cr_bitfield \XL_BT [4:2] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:575" - attribute \nmigen.decoding "WHOLE_REG/4" - case 3'100 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:577" - wire width 1 \move_one - process $group_3 - assign \move_one 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:563" - switch \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:564" - attribute \nmigen.decoding "NONE/0" - case 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:566" - attribute \nmigen.decoding "CR0/1" - case 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:569" - attribute \nmigen.decoding "BF/2" - case 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:572" - attribute \nmigen.decoding "BT/3" - case 3'011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:575" - attribute \nmigen.decoding "WHOLE_REG/4" - case 3'100 - assign \move_one \insn_in [20] - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:579" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:579" - cell $eq $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A \BRANCH_internal_op - connect \B 7'0110000 - connect \Y $1 - end - process $group_4 - assign \ppick_i 8'00000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:563" - switch \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:564" - attribute \nmigen.decoding "NONE/0" - case 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:566" - attribute \nmigen.decoding "CR0/1" - case 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:569" - attribute \nmigen.decoding "BF/2" - case 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:572" - attribute \nmigen.decoding "BT/3" - case 3'011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:575" - attribute \nmigen.decoding "WHOLE_REG/4" - case 3'100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:579" - switch { $1 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:579" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:580" - switch { \move_one } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:580" - case 1'1 - assign \ppick_i \BRANCH_FXM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:587" - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:589" - case - end - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 8 \cr_fxm - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:579" - wire width 1 $3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:579" - cell $eq $4 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A \BRANCH_internal_op - connect \B 7'0110000 - connect \Y $3 - end - process $group_5 - assign \cr_fxm 8'00000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:563" - switch \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:564" - attribute \nmigen.decoding "NONE/0" - case 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:566" - attribute \nmigen.decoding "CR0/1" - case 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:569" - attribute \nmigen.decoding "BF/2" - case 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:572" - attribute \nmigen.decoding "BT/3" - case 3'011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:575" - attribute \nmigen.decoding "WHOLE_REG/4" - case 3'100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:579" - switch { $3 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:579" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:580" - switch { \move_one } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:580" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:583" - switch { \ppick_en_o } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:583" - case 1'1 - assign \cr_fxm \ppick_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:585" - case - assign \cr_fxm 8'00000001 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:587" - case - assign \cr_fxm \BRANCH_FXM - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:589" - case - assign \cr_fxm 8'11111111 - end - end - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.dec_BRANCH.dec_bi" -module \dec_bi$151 - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:216" - wire width 4 input 0 \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 output 1 \imm_b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 2 \imm_b_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 16 input 3 \BRANCH_SI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 16 input 4 \BRANCH_UI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 5 input 5 \BRANCH_SH32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 6 input 6 \BRANCH_sh - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 24 input 7 \BRANCH_LI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 14 input 8 \BRANCH_BD - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 14 input 9 \BRANCH_DS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 64 $1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - cell $pos $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 16 - parameter \Y_WIDTH 64 - connect \A \BRANCH_UI - connect \Y $1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:229" - wire width 16 \si - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:234" - wire width 32 \si_hi - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:241" - wire width 64 $3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:239" - wire width 16 \ui - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:241" - wire width 47 $4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:241" - cell $sshl $5 - parameter \A_SIGNED 0 - parameter \A_WIDTH 16 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 47 - connect \A \ui - connect \B 5'10000 - connect \Y $4 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:241" - cell $pos $6 - parameter \A_SIGNED 0 - parameter \A_WIDTH 47 - parameter \Y_WIDTH 64 - connect \A $4 - connect \Y $3 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" - wire width 26 \li - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:249" - wire width 16 \bd - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:254" - wire width 16 \ds - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:259" - wire width 64 $7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:259" - cell $not $8 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \Y_WIDTH 64 - connect \A 64'0000000000000000000000000000000000000000000000000000000000000000 - connect \Y $7 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 64 $9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - cell $pos $10 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \Y_WIDTH 64 - connect \A \BRANCH_sh - connect \Y $9 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 64 $11 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - cell $pos $12 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \Y_WIDTH 64 - connect \A \BRANCH_SH32 - connect \Y $11 - end - process $group_0 - assign \imm_b 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:224" - switch \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:225" - attribute \nmigen.decoding "CONST_UI/2" - case 4'0010 - assign \imm_b $1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:228" - attribute \nmigen.decoding "CONST_SI/3" - case 4'0011 - assign \imm_b { { \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] } \si } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:233" - attribute \nmigen.decoding "CONST_SI_HI/5" - case 4'0101 - assign \imm_b { { \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] } \si_hi } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:238" - attribute \nmigen.decoding "CONST_UI_HI/4" - case 4'0100 - assign \imm_b $3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:243" - attribute \nmigen.decoding "CONST_LI/6" - case 4'0110 - assign \imm_b { { \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] } \li } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:248" - attribute \nmigen.decoding "CONST_BD/7" - case 4'0111 - assign \imm_b { { \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] } \bd } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:253" - attribute \nmigen.decoding "CONST_DS/8" - case 4'1000 - assign \imm_b { { \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] } \ds } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:258" - attribute \nmigen.decoding "CONST_M1/9" - case 4'1001 - assign \imm_b $7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" - attribute \nmigen.decoding "CONST_SH/10" - case 4'1010 - assign \imm_b $9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:264" - attribute \nmigen.decoding "CONST_SH32/11" - case 4'1011 - assign \imm_b $11 - end - sync init - end - process $group_1 - assign \imm_b_ok 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:224" - switch \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:225" - attribute \nmigen.decoding "CONST_UI/2" - case 4'0010 - assign \imm_b_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:228" - attribute \nmigen.decoding "CONST_SI/3" - case 4'0011 - assign \imm_b_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:233" - attribute \nmigen.decoding "CONST_SI_HI/5" - case 4'0101 - assign \imm_b_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:238" - attribute \nmigen.decoding "CONST_UI_HI/4" - case 4'0100 - assign \imm_b_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:243" - attribute \nmigen.decoding "CONST_LI/6" - case 4'0110 - assign \imm_b_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:248" - attribute \nmigen.decoding "CONST_BD/7" - case 4'0111 - assign \imm_b_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:253" - attribute \nmigen.decoding "CONST_DS/8" - case 4'1000 - assign \imm_b_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:258" - attribute \nmigen.decoding "CONST_M1/9" - case 4'1001 - assign \imm_b_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" - attribute \nmigen.decoding "CONST_SH/10" - case 4'1010 - assign \imm_b_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:264" - attribute \nmigen.decoding "CONST_SH32/11" - case 4'1011 - assign \imm_b_ok 1'1 - end - sync init - end - process $group_2 - assign \si 16'0000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:224" - switch \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:225" - attribute \nmigen.decoding "CONST_UI/2" - case 4'0010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:228" - attribute \nmigen.decoding "CONST_SI/3" - case 4'0011 - assign \si \BRANCH_SI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:233" - attribute \nmigen.decoding "CONST_SI_HI/5" - case 4'0101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:238" - attribute \nmigen.decoding "CONST_UI_HI/4" - case 4'0100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:243" - attribute \nmigen.decoding "CONST_LI/6" - case 4'0110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:248" - attribute \nmigen.decoding "CONST_BD/7" - case 4'0111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:253" - attribute \nmigen.decoding "CONST_DS/8" - case 4'1000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:258" - attribute \nmigen.decoding "CONST_M1/9" - case 4'1001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" - attribute \nmigen.decoding "CONST_SH/10" - case 4'1010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:264" - attribute \nmigen.decoding "CONST_SH32/11" - case 4'1011 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:235" - wire width 47 $13 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:235" - wire width 47 $14 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:235" - cell $sshl $15 - parameter \A_SIGNED 0 - parameter \A_WIDTH 16 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 47 - connect \A \BRANCH_SI - connect \B 5'10000 - connect \Y $14 - end - connect $13 $14 - process $group_3 - assign \si_hi 32'00000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:224" - switch \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:225" - attribute \nmigen.decoding "CONST_UI/2" - case 4'0010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:228" - attribute \nmigen.decoding "CONST_SI/3" - case 4'0011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:233" - attribute \nmigen.decoding "CONST_SI_HI/5" - case 4'0101 - assign \si_hi $13 [31:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:238" - attribute \nmigen.decoding "CONST_UI_HI/4" - case 4'0100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:243" - attribute \nmigen.decoding "CONST_LI/6" - case 4'0110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:248" - attribute \nmigen.decoding "CONST_BD/7" - case 4'0111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:253" - attribute \nmigen.decoding "CONST_DS/8" - case 4'1000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:258" - attribute \nmigen.decoding "CONST_M1/9" - case 4'1001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" - attribute \nmigen.decoding "CONST_SH/10" - case 4'1010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:264" - attribute \nmigen.decoding "CONST_SH32/11" - case 4'1011 - end - sync init - end - process $group_4 - assign \ui 16'0000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:224" - switch \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:225" - attribute \nmigen.decoding "CONST_UI/2" - case 4'0010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:228" - attribute \nmigen.decoding "CONST_SI/3" - case 4'0011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:233" - attribute \nmigen.decoding "CONST_SI_HI/5" - case 4'0101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:238" - attribute \nmigen.decoding "CONST_UI_HI/4" - case 4'0100 - assign \ui \BRANCH_UI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:243" - attribute \nmigen.decoding "CONST_LI/6" - case 4'0110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:248" - attribute \nmigen.decoding "CONST_BD/7" - case 4'0111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:253" - attribute \nmigen.decoding "CONST_DS/8" - case 4'1000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:258" - attribute \nmigen.decoding "CONST_M1/9" - case 4'1001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" - attribute \nmigen.decoding "CONST_SH/10" - case 4'1010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:264" - attribute \nmigen.decoding "CONST_SH32/11" - case 4'1011 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:245" - wire width 27 $16 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:245" - wire width 27 $17 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:245" - cell $sshl $18 - parameter \A_SIGNED 0 - parameter \A_WIDTH 24 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 27 - connect \A \BRANCH_LI - connect \B 2'10 - connect \Y $17 - end - connect $16 $17 - process $group_5 - assign \li 26'00000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:224" - switch \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:225" - attribute \nmigen.decoding "CONST_UI/2" - case 4'0010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:228" - attribute \nmigen.decoding "CONST_SI/3" - case 4'0011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:233" - attribute \nmigen.decoding "CONST_SI_HI/5" - case 4'0101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:238" - attribute \nmigen.decoding "CONST_UI_HI/4" - case 4'0100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:243" - attribute \nmigen.decoding "CONST_LI/6" - case 4'0110 - assign \li $16 [25:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:248" - attribute \nmigen.decoding "CONST_BD/7" - case 4'0111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:253" - attribute \nmigen.decoding "CONST_DS/8" - case 4'1000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:258" - attribute \nmigen.decoding "CONST_M1/9" - case 4'1001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" - attribute \nmigen.decoding "CONST_SH/10" - case 4'1010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:264" - attribute \nmigen.decoding "CONST_SH32/11" - case 4'1011 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:250" - wire width 17 $19 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:250" - wire width 17 $20 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:250" - cell $sshl $21 - parameter \A_SIGNED 0 - parameter \A_WIDTH 14 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 17 - connect \A \BRANCH_BD - connect \B 2'10 - connect \Y $20 - end - connect $19 $20 - process $group_6 - assign \bd 16'0000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:224" - switch \sel_in - attribute \src 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attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:485" - wire width 32 \dec_cr_in_insn_in - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:484" - wire width 3 \dec_cr_in_sel_in - cell \dec_cr_in$147 \dec_cr_in - connect \insn_in \dec_cr_in_insn_in - connect \sel_in \dec_cr_in_sel_in - connect \BRANCH_internal_op \dec_BRANCH_internal_op - connect \BRANCH_BB \dec_BRANCH_BB - connect \BRANCH_BA \dec_BRANCH_BA - connect \BRANCH_BT \dec_BRANCH_BT - connect \BRANCH_FXM \dec_BRANCH_FXM - connect \BRANCH_BI \dec_BRANCH_BI - connect \BRANCH_BC \dec_BRANCH_BC - connect \X_BFA \dec_X_BFA - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:550" - wire width 32 \dec_cr_out_insn_in - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:549" - wire width 3 \dec_cr_out_sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:548" - wire width 1 \dec_cr_out_rc_in - cell \dec_cr_out$149 \dec_cr_out - connect \insn_in \dec_cr_out_insn_in - connect \sel_in \dec_cr_out_sel_in - connect \rc_in \dec_cr_out_rc_in - connect \BRANCH_internal_op \dec_BRANCH_internal_op - connect \BRANCH_FXM \dec_BRANCH_FXM - connect \X_BF \dec_X_BF - connect \XL_BT \dec_XL_BT - end - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:216" - wire width 4 \dec_bi_sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 \dec_bi_imm_b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \dec_bi_imm_b_ok - cell \dec_bi$151 \dec_bi - connect \sel_in \dec_bi_sel_in - connect \imm_b \dec_bi_imm_b - connect \imm_b_ok \dec_bi_imm_b_ok - connect \BRANCH_SI \dec_BRANCH_SI - connect \BRANCH_UI \dec_BRANCH_UI - connect \BRANCH_SH32 \dec_BRANCH_SH32 - connect \BRANCH_sh \dec_BRANCH_sh - connect \BRANCH_LI \dec_BRANCH_LI - connect \BRANCH_BD \dec_BRANCH_BD - connect \BRANCH_DS \dec_BRANCH_DS - end - process $group_0 - assign \BRANCH_BRANCH__insn 32'00000000000000000000000000000000 - assign \BRANCH_BRANCH__insn \dec_opcode_in - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:405" - wire width 32 \insn_in - process $group_1 - assign \insn_in 32'00000000000000000000000000000000 - assign \insn_in \dec_opcode_in - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:442" - wire width 32 \insn_in$1 - process $group_2 - assign \insn_in$1 32'00000000000000000000000000000000 - assign \insn_in$1 \dec_opcode_in - sync init - end - process $group_3 - assign \dec_cr_in_insn_in 32'00000000000000000000000000000000 - assign \dec_cr_in_insn_in \dec_opcode_in - sync init - end - process $group_4 - assign \dec_cr_out_insn_in 32'00000000000000000000000000000000 - assign \dec_cr_out_insn_in \dec_opcode_in - sync init - end - process $group_5 - assign \dec_rc_sel_in 2'00 - assign \dec_rc_sel_in \dec_BRANCH_rc_sel - sync init - end - process $group_6 - assign \dec_oe_sel_in 2'00 - assign \dec_oe_sel_in \dec_BRANCH_rc_sel - sync init - end - process $group_7 - assign \dec_cr_in_sel_in 3'000 - assign \dec_cr_in_sel_in \dec_BRANCH_cr_in - sync init - end - process $group_8 - assign \dec_cr_out_sel_in 3'000 - assign \dec_cr_out_sel_in \dec_BRANCH_cr_out - sync init - end - process $group_9 - assign \dec_cr_out_rc_in 1'0 - assign \dec_cr_out_rc_in \dec_rc_rc - sync init - end - process $group_10 - assign \BRANCH_BRANCH__cia 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \BRANCH_BRANCH__cia \core_pc - sync init - end - process $group_11 - assign \BRANCH_BRANCH__insn_type 7'0000000 - assign \BRANCH_BRANCH__insn_type \dec_BRANCH_internal_op - sync init - end - process $group_12 - assign \BRANCH_BRANCH__fn_unit 11'00000000000 - assign \BRANCH_BRANCH__fn_unit \dec_BRANCH_function_unit - sync init - end - process $group_13 - assign \dec_bi_sel_in 4'0000 - assign \dec_bi_sel_in \dec_BRANCH_in2_sel - sync init - end - process $group_14 - assign \BRANCH_BRANCH__imm_data__data 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \BRANCH_BRANCH__imm_data__ok 1'0 - assign { \BRANCH_BRANCH__imm_data__ok \BRANCH_BRANCH__imm_data__data } { \dec_bi_imm_b_ok \dec_bi_imm_b } - sync init - end - process $group_16 - assign \BRANCH_BRANCH__is_32bit 1'0 - assign \BRANCH_BRANCH__is_32bit \dec_BRANCH_is_32b - sync init - end - process $group_17 - assign \BRANCH_BRANCH__lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:756" - switch { \dec_BRANCH_lk } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:756" - case 1'1 - assign \BRANCH_BRANCH__lk \dec_BRANCH_LK - end - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.dec_LOGICAL.dec.LOGICAL_dec19" -module \LOGICAL_dec19 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" - wire width 32 input 0 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:308" - wire width 10 \opcode_switch - process $group_0 - assign \opcode_switch 10'0000000000 - assign \opcode_switch \opcode_in [10:1] - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:308" - wire width 5 \opcode_switch$1 - process $group_1 - assign \opcode_switch$1 5'00000 - assign \opcode_switch$1 \opcode_in [5:1] - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.dec_LOGICAL.dec.LOGICAL_dec30" -module \LOGICAL_dec30 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" - wire width 32 input 0 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:308" - wire width 4 \opcode_switch - process $group_0 - assign \opcode_switch 4'0000 - assign \opcode_switch \opcode_in [4:1] - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.dec_LOGICAL.dec.LOGICAL_dec31.LOGICAL_dec_sub10" -module \LOGICAL_dec_sub10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" - wire width 32 input 0 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:308" - wire width 5 \opcode_switch - process $group_0 - assign \opcode_switch 5'00000 - assign \opcode_switch \opcode_in [10:6] - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.dec_LOGICAL.dec.LOGICAL_dec31.LOGICAL_dec_sub28" -module \LOGICAL_dec_sub28 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" - wire width 32 input 0 \opcode_in - attribute \enum_base_type "Function" - attribute \enum_value_00000000000 "NONE" - attribute \enum_value_00000000010 "ALU" - attribute \enum_value_00000000100 "LDST" - attribute \enum_value_00000001000 "SHIFT_ROT" - attribute \enum_value_00000010000 "LOGICAL" - attribute \enum_value_00000100000 "BRANCH" - attribute \enum_value_00001000000 "CR" - attribute \enum_value_00010000000 "TRAP" - attribute \enum_value_00100000000 "MUL" - attribute \enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 11 output 1 \LOGICAL_function_unit - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 7 output 2 \LOGICAL_internal_op - attribute \enum_base_type "In1Sel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "RA" - attribute \enum_value_010 "RA_OR_ZERO" - attribute \enum_value_011 "SPR" - attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 output 3 \LOGICAL_in1_sel - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 4 output 4 \LOGICAL_in2_sel - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 output 5 \LOGICAL_cr_in - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 output 6 \LOGICAL_cr_out - attribute \enum_base_type "LdstLen" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "is1B" - attribute \enum_value_0010 "is2B" - attribute \enum_value_0100 "is4B" - attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 4 output 7 \LOGICAL_ldst_len - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 2 output 8 \LOGICAL_rc_sel - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 2 output 9 \LOGICAL_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 output 10 \LOGICAL_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 output 11 \LOGICAL_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 output 12 \LOGICAL_cry_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 output 13 \LOGICAL_is_32b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 output 14 \LOGICAL_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:308" - wire width 5 \opcode_switch - process $group_0 - assign \opcode_switch 5'00000 - assign \opcode_switch \opcode_in [10:6] - sync init - end - process $group_1 - assign \LOGICAL_function_unit 11'00000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \LOGICAL_function_unit 11'00000010000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00001 - assign \LOGICAL_function_unit 11'00000010000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00111 - assign \LOGICAL_function_unit 11'00000010000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01111 - assign \LOGICAL_function_unit 11'00000010000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01000 - assign \LOGICAL_function_unit 11'00000010000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01110 - assign \LOGICAL_function_unit 11'00000010000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00011 - assign \LOGICAL_function_unit 11'00000010000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01101 - assign \LOGICAL_function_unit 11'00000010000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01100 - assign \LOGICAL_function_unit 11'00000010000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01001 - assign \LOGICAL_function_unit 11'00000010000 - end - sync init - end - process $group_2 - assign \LOGICAL_internal_op 7'0000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \LOGICAL_internal_op 7'0000100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00001 - assign \LOGICAL_internal_op 7'0000100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00111 - assign \LOGICAL_internal_op 7'0001001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01111 - assign \LOGICAL_internal_op 7'0001011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01000 - assign \LOGICAL_internal_op 7'1000011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01110 - assign \LOGICAL_internal_op 7'0000100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00011 - assign \LOGICAL_internal_op 7'0110101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01101 - assign \LOGICAL_internal_op 7'0110101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01100 - assign \LOGICAL_internal_op 7'0110101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01001 - assign \LOGICAL_internal_op 7'1000011 - end - sync init - end - process $group_3 - assign \LOGICAL_in1_sel 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \LOGICAL_in1_sel 3'100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00001 - assign \LOGICAL_in1_sel 3'100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00111 - assign \LOGICAL_in1_sel 3'100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01111 - assign \LOGICAL_in1_sel 3'100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01000 - assign \LOGICAL_in1_sel 3'100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01110 - assign \LOGICAL_in1_sel 3'100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00011 - assign \LOGICAL_in1_sel 3'100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01101 - assign \LOGICAL_in1_sel 3'100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01100 - assign \LOGICAL_in1_sel 3'100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01001 - assign \LOGICAL_in1_sel 3'100 - end - sync init - end - process $group_4 - assign \LOGICAL_in2_sel 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \LOGICAL_in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00001 - assign \LOGICAL_in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00111 - assign \LOGICAL_in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01111 - assign \LOGICAL_in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01000 - assign \LOGICAL_in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01110 - assign \LOGICAL_in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00011 - assign \LOGICAL_in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01101 - assign \LOGICAL_in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01100 - assign \LOGICAL_in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01001 - assign \LOGICAL_in2_sel 4'0001 - end - sync init - end - process $group_5 - assign \LOGICAL_cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \LOGICAL_cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00001 - assign \LOGICAL_cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00111 - assign \LOGICAL_cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01111 - assign \LOGICAL_cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01000 - assign \LOGICAL_cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01110 - assign \LOGICAL_cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00011 - assign \LOGICAL_cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01101 - assign \LOGICAL_cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01100 - assign \LOGICAL_cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01001 - assign \LOGICAL_cr_in 3'000 - end - sync init - end - process $group_6 - assign \LOGICAL_cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \LOGICAL_cr_out 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00001 - assign \LOGICAL_cr_out 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00111 - assign \LOGICAL_cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01111 - assign \LOGICAL_cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01000 - assign \LOGICAL_cr_out 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01110 - assign \LOGICAL_cr_out 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00011 - assign \LOGICAL_cr_out 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01101 - assign \LOGICAL_cr_out 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01100 - assign \LOGICAL_cr_out 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01001 - assign \LOGICAL_cr_out 3'001 - end - sync init - end - process $group_7 - assign \LOGICAL_ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \LOGICAL_ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00001 - assign \LOGICAL_ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00111 - assign \LOGICAL_ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01111 - assign \LOGICAL_ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01000 - assign \LOGICAL_ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01110 - assign \LOGICAL_ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00011 - assign \LOGICAL_ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01101 - assign \LOGICAL_ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01100 - assign \LOGICAL_ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01001 - assign \LOGICAL_ldst_len 4'0000 - end - sync init - end - process $group_8 - assign \LOGICAL_rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \LOGICAL_rc_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00001 - assign \LOGICAL_rc_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00111 - assign \LOGICAL_rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01111 - assign \LOGICAL_rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01000 - assign \LOGICAL_rc_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01110 - assign \LOGICAL_rc_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00011 - assign \LOGICAL_rc_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01101 - assign \LOGICAL_rc_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01100 - assign \LOGICAL_rc_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01001 - assign \LOGICAL_rc_sel 2'10 - end - sync init - end - process $group_9 - assign \LOGICAL_cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \LOGICAL_cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00001 - assign \LOGICAL_cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00111 - assign \LOGICAL_cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01111 - assign \LOGICAL_cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01000 - assign \LOGICAL_cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01110 - assign \LOGICAL_cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00011 - assign \LOGICAL_cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01101 - assign \LOGICAL_cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01100 - assign \LOGICAL_cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01001 - assign \LOGICAL_cry_in 2'00 - end - sync init - end - process $group_10 - assign \LOGICAL_inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \LOGICAL_inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00001 - assign \LOGICAL_inv_a 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00111 - assign \LOGICAL_inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01111 - assign \LOGICAL_inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01000 - assign \LOGICAL_inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01110 - assign \LOGICAL_inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00011 - assign \LOGICAL_inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01101 - assign \LOGICAL_inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01100 - assign \LOGICAL_inv_a 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01001 - assign \LOGICAL_inv_a 1'0 - end - sync init - end - process $group_11 - assign \LOGICAL_inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \LOGICAL_inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00001 - assign \LOGICAL_inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00111 - assign \LOGICAL_inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01111 - assign \LOGICAL_inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01000 - assign \LOGICAL_inv_out 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01110 - assign \LOGICAL_inv_out 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00011 - assign \LOGICAL_inv_out 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01101 - assign \LOGICAL_inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01100 - assign \LOGICAL_inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01001 - assign \LOGICAL_inv_out 1'0 - end - sync init - end - process $group_12 - assign \LOGICAL_cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \LOGICAL_cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00001 - assign \LOGICAL_cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00111 - assign \LOGICAL_cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01111 - assign \LOGICAL_cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01000 - assign \LOGICAL_cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01110 - assign \LOGICAL_cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00011 - assign \LOGICAL_cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01101 - assign \LOGICAL_cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01100 - assign \LOGICAL_cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01001 - assign \LOGICAL_cry_out 1'0 - end - sync init - end - process $group_13 - assign \LOGICAL_is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \LOGICAL_is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00001 - assign \LOGICAL_is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00111 - assign \LOGICAL_is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01111 - assign \LOGICAL_is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01000 - assign \LOGICAL_is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01110 - assign \LOGICAL_is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00011 - assign \LOGICAL_is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01101 - assign \LOGICAL_is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01100 - assign \LOGICAL_is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01001 - assign \LOGICAL_is_32b 1'0 - end - sync init - end - process $group_14 - assign \LOGICAL_sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \LOGICAL_sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00001 - assign \LOGICAL_sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00111 - assign \LOGICAL_sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01111 - assign \LOGICAL_sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01000 - assign \LOGICAL_sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01110 - assign \LOGICAL_sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00011 - assign \LOGICAL_sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01101 - assign \LOGICAL_sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01100 - assign \LOGICAL_sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01001 - assign \LOGICAL_sgn 1'0 - end - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.dec_LOGICAL.dec.LOGICAL_dec31.LOGICAL_dec_sub0" -module \LOGICAL_dec_sub0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" - wire width 32 input 0 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:308" - wire width 5 \opcode_switch - process $group_0 - assign \opcode_switch 5'00000 - assign \opcode_switch \opcode_in [10:6] - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.dec_LOGICAL.dec.LOGICAL_dec31.LOGICAL_dec_sub26" -module \LOGICAL_dec_sub26 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" - wire width 32 input 0 \opcode_in - attribute \enum_base_type "Function" - attribute \enum_value_00000000000 "NONE" - attribute \enum_value_00000000010 "ALU" - attribute \enum_value_00000000100 "LDST" - attribute \enum_value_00000001000 "SHIFT_ROT" - attribute \enum_value_00000010000 "LOGICAL" - attribute \enum_value_00000100000 "BRANCH" - attribute \enum_value_00001000000 "CR" - attribute \enum_value_00010000000 "TRAP" - attribute \enum_value_00100000000 "MUL" - attribute \enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 11 output 1 \LOGICAL_function_unit - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 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attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 7 output 2 \LOGICAL_internal_op - attribute \enum_base_type "In1Sel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "RA" - attribute \enum_value_010 "RA_OR_ZERO" - attribute \enum_value_011 "SPR" - attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 output 3 \LOGICAL_in1_sel - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute 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attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 output 6 \LOGICAL_cr_out - attribute \enum_base_type "LdstLen" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "is1B" - attribute \enum_value_0010 "is2B" - attribute \enum_value_0100 "is4B" - attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 4 output 7 \LOGICAL_ldst_len - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 2 output 8 \LOGICAL_rc_sel - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 2 output 9 \LOGICAL_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 output 10 \LOGICAL_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 output 11 \LOGICAL_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 output 12 \LOGICAL_cry_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 output 13 \LOGICAL_is_32b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 output 14 \LOGICAL_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:308" - wire width 5 \opcode_switch - process $group_0 - assign \opcode_switch 5'00000 - assign \opcode_switch \opcode_in [10:6] - sync init - end - process $group_1 - assign \LOGICAL_function_unit 11'00000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00001 - assign \LOGICAL_function_unit 11'00000010000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \LOGICAL_function_unit 11'00000010000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10001 - assign \LOGICAL_function_unit 11'00000010000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10000 - assign \LOGICAL_function_unit 11'00000010000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00011 - assign \LOGICAL_function_unit 11'00000010000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01111 - assign \LOGICAL_function_unit 11'00000010000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01011 - assign \LOGICAL_function_unit 11'00000010000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00101 - assign \LOGICAL_function_unit 11'00000010000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00100 - assign \LOGICAL_function_unit 11'00000010000 - end - sync init - end - process $group_2 - assign \LOGICAL_internal_op 7'0000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00001 - assign \LOGICAL_internal_op 7'0001110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \LOGICAL_internal_op 7'0001110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10001 - assign \LOGICAL_internal_op 7'0001110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10000 - assign \LOGICAL_internal_op 7'0001110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00011 - assign \LOGICAL_internal_op 7'0110110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01111 - assign \LOGICAL_internal_op 7'0110110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01011 - assign \LOGICAL_internal_op 7'0110110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00101 - assign \LOGICAL_internal_op 7'0110111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00100 - assign \LOGICAL_internal_op 7'0110111 - end - sync init - end - process $group_3 - assign \LOGICAL_in1_sel 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00001 - assign \LOGICAL_in1_sel 3'100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \LOGICAL_in1_sel 3'100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10001 - assign \LOGICAL_in1_sel 3'100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10000 - assign \LOGICAL_in1_sel 3'100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00011 - assign \LOGICAL_in1_sel 3'100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01111 - assign \LOGICAL_in1_sel 3'100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01011 - assign \LOGICAL_in1_sel 3'100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00101 - assign \LOGICAL_in1_sel 3'100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00100 - assign \LOGICAL_in1_sel 3'100 - end - sync init - end - process $group_4 - assign \LOGICAL_in2_sel 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00001 - assign \LOGICAL_in2_sel 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \LOGICAL_in2_sel 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10001 - assign \LOGICAL_in2_sel 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10000 - assign \LOGICAL_in2_sel 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00011 - assign \LOGICAL_in2_sel 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01111 - assign \LOGICAL_in2_sel 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01011 - assign \LOGICAL_in2_sel 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00101 - assign \LOGICAL_in2_sel 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00100 - assign \LOGICAL_in2_sel 4'0000 - end - sync init - end - process $group_5 - assign \LOGICAL_cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00001 - assign \LOGICAL_cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \LOGICAL_cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10001 - assign \LOGICAL_cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10000 - assign \LOGICAL_cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00011 - assign \LOGICAL_cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01111 - assign \LOGICAL_cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01011 - assign \LOGICAL_cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00101 - assign \LOGICAL_cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00100 - assign \LOGICAL_cr_in 3'000 - end - sync init - end - process $group_6 - assign \LOGICAL_cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00001 - assign \LOGICAL_cr_out 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \LOGICAL_cr_out 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10001 - assign \LOGICAL_cr_out 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10000 - assign \LOGICAL_cr_out 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00011 - assign \LOGICAL_cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01111 - assign \LOGICAL_cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01011 - assign \LOGICAL_cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00101 - assign \LOGICAL_cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00100 - assign \LOGICAL_cr_out 3'000 - end - sync init - end - process $group_7 - assign \LOGICAL_ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00001 - assign \LOGICAL_ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \LOGICAL_ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10001 - assign \LOGICAL_ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10000 - assign \LOGICAL_ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00011 - assign \LOGICAL_ldst_len 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01111 - assign \LOGICAL_ldst_len 4'1000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01011 - assign \LOGICAL_ldst_len 4'0100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00101 - assign \LOGICAL_ldst_len 4'1000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00100 - assign \LOGICAL_ldst_len 4'0100 - end - sync init - end - process $group_8 - assign \LOGICAL_rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00001 - assign \LOGICAL_rc_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \LOGICAL_rc_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10001 - assign \LOGICAL_rc_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10000 - assign \LOGICAL_rc_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00011 - assign \LOGICAL_rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01111 - assign \LOGICAL_rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01011 - assign \LOGICAL_rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00101 - assign \LOGICAL_rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00100 - assign \LOGICAL_rc_sel 2'00 - end - sync init - end - process $group_9 - assign \LOGICAL_cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00001 - assign \LOGICAL_cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \LOGICAL_cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10001 - assign \LOGICAL_cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10000 - assign \LOGICAL_cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00011 - assign \LOGICAL_cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01111 - assign \LOGICAL_cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01011 - assign \LOGICAL_cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00101 - assign \LOGICAL_cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00100 - assign \LOGICAL_cry_in 2'00 - end - sync init - end - process $group_10 - assign \LOGICAL_inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00001 - assign \LOGICAL_inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \LOGICAL_inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10001 - assign \LOGICAL_inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10000 - assign \LOGICAL_inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00011 - assign \LOGICAL_inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01111 - assign \LOGICAL_inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01011 - assign \LOGICAL_inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00101 - assign \LOGICAL_inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00100 - assign \LOGICAL_inv_a 1'0 - end - sync init - end - process $group_11 - assign \LOGICAL_inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00001 - assign \LOGICAL_inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \LOGICAL_inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10001 - assign \LOGICAL_inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10000 - assign \LOGICAL_inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00011 - assign \LOGICAL_inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01111 - assign \LOGICAL_inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01011 - assign \LOGICAL_inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00101 - assign \LOGICAL_inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00100 - assign \LOGICAL_inv_out 1'0 - end - sync init - end - process $group_12 - assign \LOGICAL_cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00001 - assign \LOGICAL_cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \LOGICAL_cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10001 - assign \LOGICAL_cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10000 - assign \LOGICAL_cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00011 - assign \LOGICAL_cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01111 - assign \LOGICAL_cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01011 - assign \LOGICAL_cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00101 - assign \LOGICAL_cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00100 - assign \LOGICAL_cry_out 1'0 - end - sync init - end - process $group_13 - assign \LOGICAL_is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00001 - assign \LOGICAL_is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \LOGICAL_is_32b 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10001 - assign \LOGICAL_is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10000 - assign \LOGICAL_is_32b 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00011 - assign \LOGICAL_is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01111 - assign \LOGICAL_is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01011 - assign \LOGICAL_is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00101 - assign \LOGICAL_is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00100 - assign \LOGICAL_is_32b 1'0 - end - sync init - end - process $group_14 - assign \LOGICAL_sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00001 - assign \LOGICAL_sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \LOGICAL_sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10001 - assign \LOGICAL_sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10000 - assign \LOGICAL_sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00011 - assign \LOGICAL_sgn 1'0 - attribute \src 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\enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 7 \LOGICAL_internal_op$32 - process $group_21 - assign \LOGICAL_internal_op 7'0000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:315" - switch \opc_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01010 - assign \LOGICAL_internal_op \LOGICAL_internal_op$17 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'11100 - assign \LOGICAL_internal_op \LOGICAL_dec_sub28_LOGICAL_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'00000 - assign \LOGICAL_internal_op \LOGICAL_internal_op$18 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'11010 - assign \LOGICAL_internal_op \LOGICAL_dec_sub26_LOGICAL_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10011 - assign \LOGICAL_internal_op \LOGICAL_internal_op$19 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10110 - assign \LOGICAL_internal_op \LOGICAL_internal_op$20 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01001 - assign \LOGICAL_internal_op \LOGICAL_internal_op$21 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01011 - assign \LOGICAL_internal_op \LOGICAL_internal_op$22 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'11011 - assign \LOGICAL_internal_op \LOGICAL_internal_op$23 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01111 - assign \LOGICAL_internal_op \LOGICAL_internal_op$24 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10100 - assign \LOGICAL_internal_op \LOGICAL_internal_op$25 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10101 - assign \LOGICAL_internal_op \LOGICAL_internal_op$26 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10111 - assign \LOGICAL_internal_op \LOGICAL_internal_op$27 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10000 - assign \LOGICAL_internal_op \LOGICAL_internal_op$28 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10010 - assign \LOGICAL_internal_op \LOGICAL_internal_op$29 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01000 - assign \LOGICAL_internal_op \LOGICAL_internal_op$30 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'11000 - assign \LOGICAL_internal_op \LOGICAL_internal_op$31 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'00100 - assign \LOGICAL_internal_op \LOGICAL_internal_op$32 - end - sync init - end - attribute \enum_base_type "In1Sel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "RA" - attribute \enum_value_010 "RA_OR_ZERO" - attribute \enum_value_011 "SPR" - attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \LOGICAL_in1_sel$33 - attribute \enum_base_type "In1Sel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "RA" - attribute \enum_value_010 "RA_OR_ZERO" - attribute \enum_value_011 "SPR" - attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \LOGICAL_in1_sel$34 - attribute \enum_base_type "In1Sel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "RA" - attribute \enum_value_010 "RA_OR_ZERO" - attribute \enum_value_011 "SPR" - attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \LOGICAL_in1_sel$35 - attribute \enum_base_type "In1Sel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "RA" - attribute \enum_value_010 "RA_OR_ZERO" - attribute \enum_value_011 "SPR" - attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \LOGICAL_in1_sel$36 - attribute \enum_base_type "In1Sel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "RA" - attribute \enum_value_010 "RA_OR_ZERO" - attribute \enum_value_011 "SPR" - attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \LOGICAL_in1_sel$37 - attribute \enum_base_type "In1Sel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "RA" - attribute \enum_value_010 "RA_OR_ZERO" - attribute \enum_value_011 "SPR" - attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \LOGICAL_in1_sel$38 - attribute \enum_base_type "In1Sel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "RA" - attribute \enum_value_010 "RA_OR_ZERO" - attribute \enum_value_011 "SPR" - attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \LOGICAL_in1_sel$39 - attribute \enum_base_type "In1Sel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "RA" - attribute \enum_value_010 "RA_OR_ZERO" - attribute \enum_value_011 "SPR" - attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \LOGICAL_in1_sel$40 - attribute \enum_base_type "In1Sel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "RA" - attribute \enum_value_010 "RA_OR_ZERO" - attribute \enum_value_011 "SPR" - attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \LOGICAL_in1_sel$41 - attribute \enum_base_type "In1Sel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "RA" - attribute \enum_value_010 "RA_OR_ZERO" - attribute \enum_value_011 "SPR" - attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \LOGICAL_in1_sel$42 - attribute \enum_base_type "In1Sel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "RA" - attribute \enum_value_010 "RA_OR_ZERO" - attribute \enum_value_011 "SPR" - attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \LOGICAL_in1_sel$43 - attribute \enum_base_type "In1Sel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "RA" - attribute \enum_value_010 "RA_OR_ZERO" - attribute \enum_value_011 "SPR" - attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \LOGICAL_in1_sel$44 - attribute \enum_base_type "In1Sel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "RA" - attribute \enum_value_010 "RA_OR_ZERO" - attribute \enum_value_011 "SPR" - attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \LOGICAL_in1_sel$45 - attribute \enum_base_type "In1Sel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "RA" - attribute \enum_value_010 "RA_OR_ZERO" - attribute \enum_value_011 "SPR" - attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \LOGICAL_in1_sel$46 - attribute \enum_base_type "In1Sel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "RA" - attribute \enum_value_010 "RA_OR_ZERO" - attribute \enum_value_011 "SPR" - attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \LOGICAL_in1_sel$47 - attribute \enum_base_type "In1Sel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "RA" - attribute \enum_value_010 "RA_OR_ZERO" - attribute \enum_value_011 "SPR" - attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \LOGICAL_in1_sel$48 - process $group_22 - assign \LOGICAL_in1_sel 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:315" - switch \opc_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01010 - assign \LOGICAL_in1_sel \LOGICAL_in1_sel$33 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'11100 - assign \LOGICAL_in1_sel \LOGICAL_dec_sub28_LOGICAL_in1_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'00000 - assign \LOGICAL_in1_sel \LOGICAL_in1_sel$34 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'11010 - assign \LOGICAL_in1_sel \LOGICAL_dec_sub26_LOGICAL_in1_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10011 - assign \LOGICAL_in1_sel \LOGICAL_in1_sel$35 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10110 - assign \LOGICAL_in1_sel \LOGICAL_in1_sel$36 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01001 - assign \LOGICAL_in1_sel \LOGICAL_in1_sel$37 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01011 - assign \LOGICAL_in1_sel \LOGICAL_in1_sel$38 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'11011 - assign \LOGICAL_in1_sel \LOGICAL_in1_sel$39 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01111 - assign \LOGICAL_in1_sel \LOGICAL_in1_sel$40 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10100 - assign \LOGICAL_in1_sel \LOGICAL_in1_sel$41 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10101 - assign \LOGICAL_in1_sel \LOGICAL_in1_sel$42 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10111 - assign \LOGICAL_in1_sel \LOGICAL_in1_sel$43 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10000 - assign \LOGICAL_in1_sel \LOGICAL_in1_sel$44 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10010 - assign \LOGICAL_in1_sel \LOGICAL_in1_sel$45 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01000 - assign \LOGICAL_in1_sel \LOGICAL_in1_sel$46 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'11000 - assign \LOGICAL_in1_sel \LOGICAL_in1_sel$47 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'00100 - assign \LOGICAL_in1_sel \LOGICAL_in1_sel$48 - end - sync init - end - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 4 \LOGICAL_in2_sel$49 - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 4 \LOGICAL_in2_sel$50 - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 4 \LOGICAL_in2_sel$51 - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 4 \LOGICAL_in2_sel$52 - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 4 \LOGICAL_in2_sel$53 - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 4 \LOGICAL_in2_sel$54 - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 4 \LOGICAL_in2_sel$55 - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 4 \LOGICAL_in2_sel$56 - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 4 \LOGICAL_in2_sel$57 - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 4 \LOGICAL_in2_sel$58 - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 4 \LOGICAL_in2_sel$59 - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 4 \LOGICAL_in2_sel$60 - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 4 \LOGICAL_in2_sel$61 - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 4 \LOGICAL_in2_sel$62 - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 4 \LOGICAL_in2_sel$63 - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 4 \LOGICAL_in2_sel$64 - process $group_23 - assign \LOGICAL_in2_sel 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:315" - switch \opc_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01010 - assign \LOGICAL_in2_sel \LOGICAL_in2_sel$49 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'11100 - assign \LOGICAL_in2_sel \LOGICAL_dec_sub28_LOGICAL_in2_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'00000 - assign \LOGICAL_in2_sel \LOGICAL_in2_sel$50 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'11010 - assign \LOGICAL_in2_sel \LOGICAL_dec_sub26_LOGICAL_in2_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10011 - assign \LOGICAL_in2_sel \LOGICAL_in2_sel$51 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10110 - assign \LOGICAL_in2_sel \LOGICAL_in2_sel$52 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01001 - assign \LOGICAL_in2_sel \LOGICAL_in2_sel$53 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01011 - assign \LOGICAL_in2_sel \LOGICAL_in2_sel$54 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'11011 - assign \LOGICAL_in2_sel \LOGICAL_in2_sel$55 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01111 - assign \LOGICAL_in2_sel \LOGICAL_in2_sel$56 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10100 - assign \LOGICAL_in2_sel \LOGICAL_in2_sel$57 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10101 - assign \LOGICAL_in2_sel \LOGICAL_in2_sel$58 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10111 - assign \LOGICAL_in2_sel \LOGICAL_in2_sel$59 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10000 - assign \LOGICAL_in2_sel \LOGICAL_in2_sel$60 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10010 - assign \LOGICAL_in2_sel \LOGICAL_in2_sel$61 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01000 - assign \LOGICAL_in2_sel \LOGICAL_in2_sel$62 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'11000 - assign \LOGICAL_in2_sel \LOGICAL_in2_sel$63 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'00100 - assign \LOGICAL_in2_sel \LOGICAL_in2_sel$64 - end - sync init - end - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \LOGICAL_cr_in$65 - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \LOGICAL_cr_in$66 - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \LOGICAL_cr_in$67 - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \LOGICAL_cr_in$68 - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \LOGICAL_cr_in$69 - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \LOGICAL_cr_in$70 - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \LOGICAL_cr_in$71 - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \LOGICAL_cr_in$72 - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \LOGICAL_cr_in$73 - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \LOGICAL_cr_in$74 - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \LOGICAL_cr_in$75 - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \LOGICAL_cr_in$76 - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \LOGICAL_cr_in$77 - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \LOGICAL_cr_in$78 - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \LOGICAL_cr_in$79 - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \LOGICAL_cr_in$80 - process $group_24 - assign \LOGICAL_cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:315" - switch \opc_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01010 - assign \LOGICAL_cr_in \LOGICAL_cr_in$65 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'11100 - assign \LOGICAL_cr_in \LOGICAL_dec_sub28_LOGICAL_cr_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'00000 - assign \LOGICAL_cr_in \LOGICAL_cr_in$66 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'11010 - assign \LOGICAL_cr_in \LOGICAL_dec_sub26_LOGICAL_cr_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10011 - assign \LOGICAL_cr_in \LOGICAL_cr_in$67 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10110 - assign \LOGICAL_cr_in \LOGICAL_cr_in$68 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01001 - assign \LOGICAL_cr_in \LOGICAL_cr_in$69 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01011 - assign \LOGICAL_cr_in \LOGICAL_cr_in$70 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'11011 - assign \LOGICAL_cr_in \LOGICAL_cr_in$71 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01111 - assign \LOGICAL_cr_in \LOGICAL_cr_in$72 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10100 - assign \LOGICAL_cr_in \LOGICAL_cr_in$73 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10101 - assign \LOGICAL_cr_in \LOGICAL_cr_in$74 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10111 - assign \LOGICAL_cr_in \LOGICAL_cr_in$75 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10000 - assign \LOGICAL_cr_in \LOGICAL_cr_in$76 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10010 - assign \LOGICAL_cr_in \LOGICAL_cr_in$77 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01000 - assign \LOGICAL_cr_in \LOGICAL_cr_in$78 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'11000 - assign \LOGICAL_cr_in \LOGICAL_cr_in$79 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'00100 - assign \LOGICAL_cr_in \LOGICAL_cr_in$80 - end - sync init - end - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \LOGICAL_cr_out$81 - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \LOGICAL_cr_out$82 - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \LOGICAL_cr_out$83 - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \LOGICAL_cr_out$84 - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \LOGICAL_cr_out$85 - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \LOGICAL_cr_out$86 - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \LOGICAL_cr_out$87 - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \LOGICAL_cr_out$88 - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \LOGICAL_cr_out$89 - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \LOGICAL_cr_out$90 - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \LOGICAL_cr_out$91 - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \LOGICAL_cr_out$92 - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \LOGICAL_cr_out$93 - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \LOGICAL_cr_out$94 - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \LOGICAL_cr_out$95 - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \LOGICAL_cr_out$96 - process $group_25 - assign \LOGICAL_cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:315" - switch \opc_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01010 - assign \LOGICAL_cr_out \LOGICAL_cr_out$81 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'11100 - assign \LOGICAL_cr_out \LOGICAL_dec_sub28_LOGICAL_cr_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'00000 - assign \LOGICAL_cr_out \LOGICAL_cr_out$82 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'11010 - assign \LOGICAL_cr_out \LOGICAL_dec_sub26_LOGICAL_cr_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10011 - assign \LOGICAL_cr_out \LOGICAL_cr_out$83 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10110 - assign \LOGICAL_cr_out \LOGICAL_cr_out$84 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01001 - assign \LOGICAL_cr_out \LOGICAL_cr_out$85 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01011 - assign \LOGICAL_cr_out \LOGICAL_cr_out$86 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'11011 - assign \LOGICAL_cr_out \LOGICAL_cr_out$87 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01111 - assign \LOGICAL_cr_out \LOGICAL_cr_out$88 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10100 - assign \LOGICAL_cr_out \LOGICAL_cr_out$89 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10101 - assign \LOGICAL_cr_out \LOGICAL_cr_out$90 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10111 - assign \LOGICAL_cr_out \LOGICAL_cr_out$91 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10000 - assign \LOGICAL_cr_out \LOGICAL_cr_out$92 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10010 - assign \LOGICAL_cr_out \LOGICAL_cr_out$93 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01000 - assign \LOGICAL_cr_out \LOGICAL_cr_out$94 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'11000 - assign \LOGICAL_cr_out \LOGICAL_cr_out$95 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'00100 - assign \LOGICAL_cr_out \LOGICAL_cr_out$96 - end - sync init - end - attribute \enum_base_type "LdstLen" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "is1B" - attribute \enum_value_0010 "is2B" - attribute \enum_value_0100 "is4B" - attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 4 \LOGICAL_ldst_len$97 - attribute \enum_base_type "LdstLen" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "is1B" - attribute \enum_value_0010 "is2B" - attribute \enum_value_0100 "is4B" - attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 4 \LOGICAL_ldst_len$98 - attribute \enum_base_type "LdstLen" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "is1B" - attribute \enum_value_0010 "is2B" - attribute \enum_value_0100 "is4B" - attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 4 \LOGICAL_ldst_len$99 - attribute \enum_base_type "LdstLen" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "is1B" - attribute \enum_value_0010 "is2B" - attribute \enum_value_0100 "is4B" - attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 4 \LOGICAL_ldst_len$100 - attribute \enum_base_type "LdstLen" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "is1B" - attribute \enum_value_0010 "is2B" - attribute \enum_value_0100 "is4B" - attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 4 \LOGICAL_ldst_len$101 - attribute \enum_base_type "LdstLen" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "is1B" - attribute \enum_value_0010 "is2B" - attribute \enum_value_0100 "is4B" - attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 4 \LOGICAL_ldst_len$102 - attribute \enum_base_type "LdstLen" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "is1B" - attribute \enum_value_0010 "is2B" - attribute \enum_value_0100 "is4B" - attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 4 \LOGICAL_ldst_len$103 - attribute \enum_base_type "LdstLen" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "is1B" - attribute \enum_value_0010 "is2B" - attribute \enum_value_0100 "is4B" - attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 4 \LOGICAL_ldst_len$104 - attribute \enum_base_type "LdstLen" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "is1B" - attribute \enum_value_0010 "is2B" - attribute \enum_value_0100 "is4B" - attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 4 \LOGICAL_ldst_len$105 - attribute \enum_base_type "LdstLen" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "is1B" - attribute \enum_value_0010 "is2B" - attribute \enum_value_0100 "is4B" - attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 4 \LOGICAL_ldst_len$106 - attribute \enum_base_type "LdstLen" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "is1B" - attribute \enum_value_0010 "is2B" - attribute \enum_value_0100 "is4B" - attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 4 \LOGICAL_ldst_len$107 - attribute \enum_base_type "LdstLen" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "is1B" - attribute \enum_value_0010 "is2B" - attribute \enum_value_0100 "is4B" - attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 4 \LOGICAL_ldst_len$108 - attribute \enum_base_type "LdstLen" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "is1B" - attribute \enum_value_0010 "is2B" - attribute \enum_value_0100 "is4B" - attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 4 \LOGICAL_ldst_len$109 - attribute \enum_base_type "LdstLen" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "is1B" - attribute \enum_value_0010 "is2B" - attribute \enum_value_0100 "is4B" - attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 4 \LOGICAL_ldst_len$110 - attribute \enum_base_type "LdstLen" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "is1B" - attribute \enum_value_0010 "is2B" - attribute \enum_value_0100 "is4B" - attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 4 \LOGICAL_ldst_len$111 - attribute \enum_base_type "LdstLen" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "is1B" - attribute \enum_value_0010 "is2B" - attribute \enum_value_0100 "is4B" - attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 4 \LOGICAL_ldst_len$112 - process $group_26 - assign \LOGICAL_ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:315" - switch \opc_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01010 - assign \LOGICAL_ldst_len \LOGICAL_ldst_len$97 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'11100 - assign \LOGICAL_ldst_len \LOGICAL_dec_sub28_LOGICAL_ldst_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'00000 - assign \LOGICAL_ldst_len \LOGICAL_ldst_len$98 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'11010 - assign \LOGICAL_ldst_len \LOGICAL_dec_sub26_LOGICAL_ldst_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10011 - assign \LOGICAL_ldst_len \LOGICAL_ldst_len$99 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10110 - assign \LOGICAL_ldst_len \LOGICAL_ldst_len$100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01001 - assign \LOGICAL_ldst_len \LOGICAL_ldst_len$101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01011 - assign \LOGICAL_ldst_len \LOGICAL_ldst_len$102 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'11011 - assign \LOGICAL_ldst_len \LOGICAL_ldst_len$103 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01111 - assign \LOGICAL_ldst_len \LOGICAL_ldst_len$104 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10100 - assign \LOGICAL_ldst_len \LOGICAL_ldst_len$105 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10101 - assign \LOGICAL_ldst_len \LOGICAL_ldst_len$106 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10111 - assign \LOGICAL_ldst_len \LOGICAL_ldst_len$107 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10000 - assign \LOGICAL_ldst_len \LOGICAL_ldst_len$108 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10010 - assign \LOGICAL_ldst_len \LOGICAL_ldst_len$109 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01000 - assign \LOGICAL_ldst_len \LOGICAL_ldst_len$110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'11000 - assign \LOGICAL_ldst_len \LOGICAL_ldst_len$111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'00100 - assign \LOGICAL_ldst_len \LOGICAL_ldst_len$112 - end - sync init - end - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 2 \LOGICAL_rc_sel$113 - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 2 \LOGICAL_rc_sel$114 - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 2 \LOGICAL_rc_sel$115 - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 2 \LOGICAL_rc_sel$116 - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 2 \LOGICAL_rc_sel$117 - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 2 \LOGICAL_rc_sel$118 - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 2 \LOGICAL_rc_sel$119 - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 2 \LOGICAL_rc_sel$120 - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 2 \LOGICAL_rc_sel$121 - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 2 \LOGICAL_rc_sel$122 - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 2 \LOGICAL_rc_sel$123 - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 2 \LOGICAL_rc_sel$124 - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 2 \LOGICAL_rc_sel$125 - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 2 \LOGICAL_rc_sel$126 - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 2 \LOGICAL_rc_sel$127 - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 2 \LOGICAL_rc_sel$128 - process $group_27 - assign \LOGICAL_rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:315" - switch \opc_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01010 - assign \LOGICAL_rc_sel \LOGICAL_rc_sel$113 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'11100 - assign \LOGICAL_rc_sel \LOGICAL_dec_sub28_LOGICAL_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'00000 - assign \LOGICAL_rc_sel \LOGICAL_rc_sel$114 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'11010 - assign \LOGICAL_rc_sel \LOGICAL_dec_sub26_LOGICAL_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10011 - assign \LOGICAL_rc_sel \LOGICAL_rc_sel$115 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10110 - assign \LOGICAL_rc_sel \LOGICAL_rc_sel$116 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01001 - assign \LOGICAL_rc_sel \LOGICAL_rc_sel$117 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01011 - assign \LOGICAL_rc_sel \LOGICAL_rc_sel$118 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'11011 - assign \LOGICAL_rc_sel \LOGICAL_rc_sel$119 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01111 - assign \LOGICAL_rc_sel \LOGICAL_rc_sel$120 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10100 - assign \LOGICAL_rc_sel \LOGICAL_rc_sel$121 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10101 - assign \LOGICAL_rc_sel \LOGICAL_rc_sel$122 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10111 - assign \LOGICAL_rc_sel \LOGICAL_rc_sel$123 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10000 - assign \LOGICAL_rc_sel \LOGICAL_rc_sel$124 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10010 - assign \LOGICAL_rc_sel \LOGICAL_rc_sel$125 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01000 - assign \LOGICAL_rc_sel \LOGICAL_rc_sel$126 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'11000 - assign \LOGICAL_rc_sel \LOGICAL_rc_sel$127 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'00100 - assign \LOGICAL_rc_sel \LOGICAL_rc_sel$128 - end - sync init - end - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 2 \LOGICAL_cry_in$129 - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 2 \LOGICAL_cry_in$130 - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 2 \LOGICAL_cry_in$131 - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 2 \LOGICAL_cry_in$132 - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 2 \LOGICAL_cry_in$133 - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 2 \LOGICAL_cry_in$134 - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 2 \LOGICAL_cry_in$135 - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 2 \LOGICAL_cry_in$136 - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 2 \LOGICAL_cry_in$137 - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 2 \LOGICAL_cry_in$138 - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 2 \LOGICAL_cry_in$139 - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 2 \LOGICAL_cry_in$140 - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 2 \LOGICAL_cry_in$141 - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 2 \LOGICAL_cry_in$142 - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 2 \LOGICAL_cry_in$143 - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 2 \LOGICAL_cry_in$144 - process $group_28 - assign \LOGICAL_cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:315" - switch \opc_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01010 - assign \LOGICAL_cry_in \LOGICAL_cry_in$129 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'11100 - assign \LOGICAL_cry_in \LOGICAL_dec_sub28_LOGICAL_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'00000 - assign \LOGICAL_cry_in \LOGICAL_cry_in$130 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'11010 - assign \LOGICAL_cry_in \LOGICAL_dec_sub26_LOGICAL_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10011 - assign \LOGICAL_cry_in \LOGICAL_cry_in$131 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10110 - assign \LOGICAL_cry_in \LOGICAL_cry_in$132 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01001 - assign \LOGICAL_cry_in \LOGICAL_cry_in$133 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01011 - assign \LOGICAL_cry_in \LOGICAL_cry_in$134 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'11011 - assign \LOGICAL_cry_in \LOGICAL_cry_in$135 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01111 - assign \LOGICAL_cry_in \LOGICAL_cry_in$136 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10100 - assign \LOGICAL_cry_in \LOGICAL_cry_in$137 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10101 - assign \LOGICAL_cry_in \LOGICAL_cry_in$138 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10111 - assign \LOGICAL_cry_in \LOGICAL_cry_in$139 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10000 - assign \LOGICAL_cry_in \LOGICAL_cry_in$140 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10010 - assign \LOGICAL_cry_in \LOGICAL_cry_in$141 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01000 - assign \LOGICAL_cry_in \LOGICAL_cry_in$142 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'11000 - assign \LOGICAL_cry_in \LOGICAL_cry_in$143 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'00100 - assign \LOGICAL_cry_in \LOGICAL_cry_in$144 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \LOGICAL_inv_a$145 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \LOGICAL_inv_a$146 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \LOGICAL_inv_a$147 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \LOGICAL_inv_a$148 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \LOGICAL_inv_a$149 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \LOGICAL_inv_a$150 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \LOGICAL_inv_a$151 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \LOGICAL_inv_a$152 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \LOGICAL_inv_a$153 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \LOGICAL_inv_a$154 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \LOGICAL_inv_a$155 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \LOGICAL_inv_a$156 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \LOGICAL_inv_a$157 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \LOGICAL_inv_a$158 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \LOGICAL_inv_a$159 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \LOGICAL_inv_a$160 - process $group_29 - assign \LOGICAL_inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:315" - switch \opc_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01010 - assign \LOGICAL_inv_a \LOGICAL_inv_a$145 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'11100 - assign \LOGICAL_inv_a \LOGICAL_dec_sub28_LOGICAL_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'00000 - assign \LOGICAL_inv_a \LOGICAL_inv_a$146 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'11010 - assign \LOGICAL_inv_a \LOGICAL_dec_sub26_LOGICAL_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10011 - assign \LOGICAL_inv_a \LOGICAL_inv_a$147 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10110 - assign \LOGICAL_inv_a \LOGICAL_inv_a$148 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01001 - assign \LOGICAL_inv_a \LOGICAL_inv_a$149 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01011 - assign \LOGICAL_inv_a \LOGICAL_inv_a$150 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'11011 - assign \LOGICAL_inv_a \LOGICAL_inv_a$151 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01111 - assign \LOGICAL_inv_a \LOGICAL_inv_a$152 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10100 - assign \LOGICAL_inv_a \LOGICAL_inv_a$153 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10101 - assign \LOGICAL_inv_a \LOGICAL_inv_a$154 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10111 - assign \LOGICAL_inv_a \LOGICAL_inv_a$155 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10000 - assign \LOGICAL_inv_a \LOGICAL_inv_a$156 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10010 - assign \LOGICAL_inv_a \LOGICAL_inv_a$157 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01000 - assign \LOGICAL_inv_a \LOGICAL_inv_a$158 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'11000 - assign \LOGICAL_inv_a \LOGICAL_inv_a$159 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'00100 - assign \LOGICAL_inv_a \LOGICAL_inv_a$160 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \LOGICAL_inv_out$161 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \LOGICAL_inv_out$162 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \LOGICAL_inv_out$163 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \LOGICAL_inv_out$164 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \LOGICAL_inv_out$165 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \LOGICAL_inv_out$166 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \LOGICAL_inv_out$167 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \LOGICAL_inv_out$168 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \LOGICAL_inv_out$169 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \LOGICAL_inv_out$170 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \LOGICAL_inv_out$171 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \LOGICAL_inv_out$172 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \LOGICAL_inv_out$173 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \LOGICAL_inv_out$174 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \LOGICAL_inv_out$175 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \LOGICAL_inv_out$176 - process $group_30 - assign \LOGICAL_inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:315" - switch \opc_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01010 - assign \LOGICAL_inv_out \LOGICAL_inv_out$161 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'11100 - assign \LOGICAL_inv_out \LOGICAL_dec_sub28_LOGICAL_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'00000 - assign \LOGICAL_inv_out \LOGICAL_inv_out$162 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'11010 - assign \LOGICAL_inv_out \LOGICAL_dec_sub26_LOGICAL_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10011 - assign \LOGICAL_inv_out \LOGICAL_inv_out$163 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10110 - assign \LOGICAL_inv_out \LOGICAL_inv_out$164 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01001 - assign \LOGICAL_inv_out \LOGICAL_inv_out$165 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01011 - assign \LOGICAL_inv_out \LOGICAL_inv_out$166 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'11011 - assign \LOGICAL_inv_out \LOGICAL_inv_out$167 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01111 - assign \LOGICAL_inv_out \LOGICAL_inv_out$168 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10100 - assign \LOGICAL_inv_out \LOGICAL_inv_out$169 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10101 - assign \LOGICAL_inv_out \LOGICAL_inv_out$170 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10111 - assign \LOGICAL_inv_out \LOGICAL_inv_out$171 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10000 - assign \LOGICAL_inv_out \LOGICAL_inv_out$172 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10010 - assign \LOGICAL_inv_out \LOGICAL_inv_out$173 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01000 - assign \LOGICAL_inv_out \LOGICAL_inv_out$174 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'11000 - assign \LOGICAL_inv_out \LOGICAL_inv_out$175 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'00100 - assign \LOGICAL_inv_out \LOGICAL_inv_out$176 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \LOGICAL_cry_out$177 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \LOGICAL_cry_out$178 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \LOGICAL_cry_out$179 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \LOGICAL_cry_out$180 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \LOGICAL_cry_out$181 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \LOGICAL_cry_out$182 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \LOGICAL_cry_out$183 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \LOGICAL_cry_out$184 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \LOGICAL_cry_out$185 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \LOGICAL_cry_out$186 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \LOGICAL_cry_out$187 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \LOGICAL_cry_out$188 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \LOGICAL_cry_out$189 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \LOGICAL_cry_out$190 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \LOGICAL_cry_out$191 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \LOGICAL_cry_out$192 - process $group_31 - assign \LOGICAL_cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:315" - switch \opc_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01010 - assign \LOGICAL_cry_out \LOGICAL_cry_out$177 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'11100 - assign \LOGICAL_cry_out \LOGICAL_dec_sub28_LOGICAL_cry_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'00000 - assign \LOGICAL_cry_out \LOGICAL_cry_out$178 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'11010 - assign \LOGICAL_cry_out \LOGICAL_dec_sub26_LOGICAL_cry_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10011 - assign \LOGICAL_cry_out \LOGICAL_cry_out$179 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10110 - assign \LOGICAL_cry_out \LOGICAL_cry_out$180 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01001 - assign \LOGICAL_cry_out \LOGICAL_cry_out$181 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01011 - assign \LOGICAL_cry_out \LOGICAL_cry_out$182 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'11011 - assign \LOGICAL_cry_out \LOGICAL_cry_out$183 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01111 - assign \LOGICAL_cry_out \LOGICAL_cry_out$184 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10100 - assign \LOGICAL_cry_out \LOGICAL_cry_out$185 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10101 - assign \LOGICAL_cry_out \LOGICAL_cry_out$186 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10111 - assign \LOGICAL_cry_out \LOGICAL_cry_out$187 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10000 - assign \LOGICAL_cry_out \LOGICAL_cry_out$188 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10010 - assign \LOGICAL_cry_out \LOGICAL_cry_out$189 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01000 - assign \LOGICAL_cry_out \LOGICAL_cry_out$190 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'11000 - assign \LOGICAL_cry_out \LOGICAL_cry_out$191 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'00100 - assign \LOGICAL_cry_out \LOGICAL_cry_out$192 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \LOGICAL_is_32b$193 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \LOGICAL_is_32b$194 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \LOGICAL_is_32b$195 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \LOGICAL_is_32b$196 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \LOGICAL_is_32b$197 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \LOGICAL_is_32b$198 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \LOGICAL_is_32b$199 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \LOGICAL_is_32b$200 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \LOGICAL_is_32b$201 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \LOGICAL_is_32b$202 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \LOGICAL_is_32b$203 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \LOGICAL_is_32b$204 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \LOGICAL_is_32b$205 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \LOGICAL_is_32b$206 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \LOGICAL_is_32b$207 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \LOGICAL_is_32b$208 - process $group_32 - assign \LOGICAL_is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:315" - switch \opc_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01010 - assign \LOGICAL_is_32b \LOGICAL_is_32b$193 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'11100 - assign \LOGICAL_is_32b \LOGICAL_dec_sub28_LOGICAL_is_32b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'00000 - assign \LOGICAL_is_32b \LOGICAL_is_32b$194 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'11010 - assign \LOGICAL_is_32b \LOGICAL_dec_sub26_LOGICAL_is_32b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10011 - assign \LOGICAL_is_32b \LOGICAL_is_32b$195 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10110 - assign \LOGICAL_is_32b \LOGICAL_is_32b$196 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01001 - assign \LOGICAL_is_32b \LOGICAL_is_32b$197 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01011 - assign \LOGICAL_is_32b \LOGICAL_is_32b$198 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'11011 - assign \LOGICAL_is_32b \LOGICAL_is_32b$199 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01111 - assign \LOGICAL_is_32b \LOGICAL_is_32b$200 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10100 - assign \LOGICAL_is_32b \LOGICAL_is_32b$201 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10101 - assign \LOGICAL_is_32b \LOGICAL_is_32b$202 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10111 - assign \LOGICAL_is_32b \LOGICAL_is_32b$203 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10000 - assign \LOGICAL_is_32b \LOGICAL_is_32b$204 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10010 - assign \LOGICAL_is_32b \LOGICAL_is_32b$205 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01000 - assign \LOGICAL_is_32b \LOGICAL_is_32b$206 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'11000 - assign \LOGICAL_is_32b \LOGICAL_is_32b$207 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'00100 - assign \LOGICAL_is_32b \LOGICAL_is_32b$208 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \LOGICAL_sgn$209 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \LOGICAL_sgn$210 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \LOGICAL_sgn$211 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \LOGICAL_sgn$212 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \LOGICAL_sgn$213 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \LOGICAL_sgn$214 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \LOGICAL_sgn$215 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \LOGICAL_sgn$216 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \LOGICAL_sgn$217 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \LOGICAL_sgn$218 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \LOGICAL_sgn$219 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \LOGICAL_sgn$220 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \LOGICAL_sgn$221 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \LOGICAL_sgn$222 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \LOGICAL_sgn$223 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \LOGICAL_sgn$224 - process $group_33 - assign \LOGICAL_sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:315" - switch \opc_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01010 - assign \LOGICAL_sgn \LOGICAL_sgn$209 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'11100 - assign \LOGICAL_sgn \LOGICAL_dec_sub28_LOGICAL_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'00000 - assign \LOGICAL_sgn \LOGICAL_sgn$210 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'11010 - assign \LOGICAL_sgn \LOGICAL_dec_sub26_LOGICAL_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10011 - assign \LOGICAL_sgn \LOGICAL_sgn$211 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10110 - assign \LOGICAL_sgn \LOGICAL_sgn$212 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01001 - assign \LOGICAL_sgn \LOGICAL_sgn$213 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01011 - assign \LOGICAL_sgn \LOGICAL_sgn$214 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'11011 - assign \LOGICAL_sgn \LOGICAL_sgn$215 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01111 - assign \LOGICAL_sgn \LOGICAL_sgn$216 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10100 - assign \LOGICAL_sgn \LOGICAL_sgn$217 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10101 - assign \LOGICAL_sgn \LOGICAL_sgn$218 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10111 - assign \LOGICAL_sgn \LOGICAL_sgn$219 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10000 - assign \LOGICAL_sgn \LOGICAL_sgn$220 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10010 - assign \LOGICAL_sgn \LOGICAL_sgn$221 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01000 - assign \LOGICAL_sgn \LOGICAL_sgn$222 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'11000 - assign \LOGICAL_sgn \LOGICAL_sgn$223 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'00100 - assign \LOGICAL_sgn \LOGICAL_sgn$224 - end - sync init - end - connect \LOGICAL_function_unit$1 11'00000000000 - connect \LOGICAL_function_unit$2 11'00000000000 - connect \LOGICAL_function_unit$3 11'00000000000 - connect \LOGICAL_function_unit$4 11'00000000000 - connect \LOGICAL_function_unit$5 11'00000000000 - connect \LOGICAL_function_unit$6 11'00000000000 - connect \LOGICAL_function_unit$7 11'00000000000 - connect \LOGICAL_function_unit$8 11'00000000000 - connect \LOGICAL_function_unit$9 11'00000000000 - connect \LOGICAL_function_unit$10 11'00000000000 - connect \LOGICAL_function_unit$11 11'00000000000 - connect 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\enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 7 \LOGICAL_internal_op$7 - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 7 \LOGICAL_internal_op$8 - process $group_7 - assign \LOGICAL_internal_op 7'0000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'010011 - assign \LOGICAL_internal_op \LOGICAL_internal_op$5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'011110 - assign \LOGICAL_internal_op \LOGICAL_internal_op$6 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'011111 - assign \LOGICAL_internal_op \LOGICAL_dec31_LOGICAL_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'111010 - assign \LOGICAL_internal_op \LOGICAL_internal_op$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'111110 - assign \LOGICAL_internal_op \LOGICAL_internal_op$8 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'011100 - assign \LOGICAL_internal_op 7'0000100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'011101 - assign \LOGICAL_internal_op 7'0000100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'011000 - assign \LOGICAL_internal_op 7'0110101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'011001 - assign \LOGICAL_internal_op 7'0110101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'011010 - assign \LOGICAL_internal_op 7'1000011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'011011 - assign \LOGICAL_internal_op 7'1000011 - end - sync init - end - attribute \enum_base_type "In1Sel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "RA" - attribute \enum_value_010 "RA_OR_ZERO" - attribute \enum_value_011 "SPR" - attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \LOGICAL_in1_sel$9 - attribute \enum_base_type "In1Sel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "RA" - attribute \enum_value_010 "RA_OR_ZERO" - attribute \enum_value_011 "SPR" - attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \LOGICAL_in1_sel$10 - attribute \enum_base_type "In1Sel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "RA" - attribute \enum_value_010 "RA_OR_ZERO" - attribute \enum_value_011 "SPR" - attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \LOGICAL_in1_sel$11 - attribute \enum_base_type "In1Sel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "RA" - attribute \enum_value_010 "RA_OR_ZERO" - attribute \enum_value_011 "SPR" - attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \LOGICAL_in1_sel$12 - process $group_8 - assign \LOGICAL_in1_sel 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'010011 - assign \LOGICAL_in1_sel \LOGICAL_in1_sel$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'011110 - assign \LOGICAL_in1_sel \LOGICAL_in1_sel$10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'011111 - assign \LOGICAL_in1_sel \LOGICAL_dec31_LOGICAL_in1_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'111010 - assign \LOGICAL_in1_sel \LOGICAL_in1_sel$11 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'111110 - assign \LOGICAL_in1_sel \LOGICAL_in1_sel$12 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'011100 - assign \LOGICAL_in1_sel 3'100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'011101 - assign \LOGICAL_in1_sel 3'100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'011000 - assign \LOGICAL_in1_sel 3'100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'011001 - assign \LOGICAL_in1_sel 3'100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'011010 - assign \LOGICAL_in1_sel 3'100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'011011 - assign \LOGICAL_in1_sel 3'100 - end - sync init - end - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 4 \LOGICAL_in2_sel$13 - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 4 \LOGICAL_in2_sel$14 - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 4 \LOGICAL_in2_sel$15 - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 4 \LOGICAL_in2_sel$16 - process $group_9 - assign \LOGICAL_in2_sel 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'010011 - assign \LOGICAL_in2_sel \LOGICAL_in2_sel$13 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'011110 - assign \LOGICAL_in2_sel \LOGICAL_in2_sel$14 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'011111 - assign \LOGICAL_in2_sel \LOGICAL_dec31_LOGICAL_in2_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'111010 - assign \LOGICAL_in2_sel \LOGICAL_in2_sel$15 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'111110 - assign \LOGICAL_in2_sel \LOGICAL_in2_sel$16 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'011100 - assign \LOGICAL_in2_sel 4'0010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'011101 - assign \LOGICAL_in2_sel 4'0100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'011000 - assign \LOGICAL_in2_sel 4'0010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'011001 - assign \LOGICAL_in2_sel 4'0100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'011010 - assign \LOGICAL_in2_sel 4'0010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'011011 - assign \LOGICAL_in2_sel 4'0100 - end - sync init - end - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \LOGICAL_cr_in$17 - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \LOGICAL_cr_in$18 - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \LOGICAL_cr_in$19 - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \LOGICAL_cr_in$20 - process $group_10 - assign \LOGICAL_cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'010011 - assign \LOGICAL_cr_in \LOGICAL_cr_in$17 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'011110 - assign \LOGICAL_cr_in \LOGICAL_cr_in$18 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'011111 - assign \LOGICAL_cr_in \LOGICAL_dec31_LOGICAL_cr_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'111010 - assign \LOGICAL_cr_in \LOGICAL_cr_in$19 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'111110 - assign \LOGICAL_cr_in \LOGICAL_cr_in$20 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'011100 - assign \LOGICAL_cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'011101 - assign \LOGICAL_cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'011000 - assign \LOGICAL_cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'011001 - assign \LOGICAL_cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'011010 - assign \LOGICAL_cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'011011 - assign \LOGICAL_cr_in 3'000 - end - sync init - end - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \LOGICAL_cr_out$21 - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \LOGICAL_cr_out$22 - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \LOGICAL_cr_out$23 - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \LOGICAL_cr_out$24 - process $group_11 - assign \LOGICAL_cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'010011 - assign \LOGICAL_cr_out \LOGICAL_cr_out$21 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'011110 - assign \LOGICAL_cr_out \LOGICAL_cr_out$22 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'011111 - assign \LOGICAL_cr_out \LOGICAL_dec31_LOGICAL_cr_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'111010 - assign \LOGICAL_cr_out \LOGICAL_cr_out$23 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'111110 - assign \LOGICAL_cr_out \LOGICAL_cr_out$24 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'011100 - assign \LOGICAL_cr_out 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'011101 - assign \LOGICAL_cr_out 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'011000 - assign \LOGICAL_cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'011001 - assign \LOGICAL_cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'011010 - assign \LOGICAL_cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'011011 - assign \LOGICAL_cr_out 3'000 - end - sync init - end - attribute \enum_base_type "LdstLen" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "is1B" - attribute \enum_value_0010 "is2B" - attribute \enum_value_0100 "is4B" - attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 4 \LOGICAL_ldst_len$25 - attribute \enum_base_type "LdstLen" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "is1B" - attribute \enum_value_0010 "is2B" - attribute \enum_value_0100 "is4B" - attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 4 \LOGICAL_ldst_len$26 - attribute \enum_base_type "LdstLen" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "is1B" - attribute \enum_value_0010 "is2B" - attribute \enum_value_0100 "is4B" - attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 4 \LOGICAL_ldst_len$27 - attribute \enum_base_type "LdstLen" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "is1B" - attribute \enum_value_0010 "is2B" - attribute \enum_value_0100 "is4B" - attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 4 \LOGICAL_ldst_len$28 - process $group_12 - assign \LOGICAL_ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'010011 - assign \LOGICAL_ldst_len \LOGICAL_ldst_len$25 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'011110 - assign \LOGICAL_ldst_len \LOGICAL_ldst_len$26 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'011111 - assign \LOGICAL_ldst_len \LOGICAL_dec31_LOGICAL_ldst_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'111010 - assign \LOGICAL_ldst_len \LOGICAL_ldst_len$27 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'111110 - assign \LOGICAL_ldst_len \LOGICAL_ldst_len$28 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'011100 - assign \LOGICAL_ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'011101 - assign \LOGICAL_ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'011000 - assign \LOGICAL_ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'011001 - assign \LOGICAL_ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'011010 - assign \LOGICAL_ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'011011 - assign \LOGICAL_ldst_len 4'0000 - end - sync init - end - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 2 \LOGICAL_rc_sel$29 - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 2 \LOGICAL_rc_sel$30 - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 2 \LOGICAL_rc_sel$31 - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 2 \LOGICAL_rc_sel$32 - process $group_13 - assign \LOGICAL_rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'010011 - assign \LOGICAL_rc_sel \LOGICAL_rc_sel$29 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'011110 - assign \LOGICAL_rc_sel \LOGICAL_rc_sel$30 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'011111 - assign \LOGICAL_rc_sel \LOGICAL_dec31_LOGICAL_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'111010 - assign \LOGICAL_rc_sel \LOGICAL_rc_sel$31 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'111110 - assign \LOGICAL_rc_sel \LOGICAL_rc_sel$32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'011100 - assign \LOGICAL_rc_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'011101 - assign \LOGICAL_rc_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'011000 - assign \LOGICAL_rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'011001 - assign \LOGICAL_rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'011010 - assign \LOGICAL_rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'011011 - assign \LOGICAL_rc_sel 2'00 - end - sync init - end - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 2 \LOGICAL_cry_in$33 - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 2 \LOGICAL_cry_in$34 - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 2 \LOGICAL_cry_in$35 - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 2 \LOGICAL_cry_in$36 - process $group_14 - assign \LOGICAL_cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'010011 - assign \LOGICAL_cry_in \LOGICAL_cry_in$33 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'011110 - assign \LOGICAL_cry_in \LOGICAL_cry_in$34 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'011111 - assign \LOGICAL_cry_in \LOGICAL_dec31_LOGICAL_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'111010 - assign \LOGICAL_cry_in \LOGICAL_cry_in$35 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'111110 - assign \LOGICAL_cry_in \LOGICAL_cry_in$36 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'011100 - assign \LOGICAL_cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'011101 - assign \LOGICAL_cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'011000 - assign \LOGICAL_cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'011001 - assign \LOGICAL_cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'011010 - assign \LOGICAL_cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'011011 - assign \LOGICAL_cry_in 2'00 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \LOGICAL_inv_a$37 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \LOGICAL_inv_a$38 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \LOGICAL_inv_a$39 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \LOGICAL_inv_a$40 - process $group_15 - assign \LOGICAL_inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'010011 - assign \LOGICAL_inv_a \LOGICAL_inv_a$37 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'011110 - assign \LOGICAL_inv_a \LOGICAL_inv_a$38 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'011111 - assign \LOGICAL_inv_a \LOGICAL_dec31_LOGICAL_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'111010 - assign \LOGICAL_inv_a \LOGICAL_inv_a$39 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'111110 - assign \LOGICAL_inv_a \LOGICAL_inv_a$40 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'011100 - assign \LOGICAL_inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'011101 - assign \LOGICAL_inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'011000 - assign \LOGICAL_inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'011001 - assign \LOGICAL_inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'011010 - assign \LOGICAL_inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'011011 - assign \LOGICAL_inv_a 1'0 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \LOGICAL_inv_out$41 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \LOGICAL_inv_out$42 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \LOGICAL_inv_out$43 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \LOGICAL_inv_out$44 - process $group_16 - assign \LOGICAL_inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'010011 - assign \LOGICAL_inv_out \LOGICAL_inv_out$41 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'011110 - assign \LOGICAL_inv_out \LOGICAL_inv_out$42 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'011111 - assign \LOGICAL_inv_out \LOGICAL_dec31_LOGICAL_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'111010 - assign \LOGICAL_inv_out \LOGICAL_inv_out$43 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'111110 - assign \LOGICAL_inv_out \LOGICAL_inv_out$44 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'011100 - assign \LOGICAL_inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'011101 - assign \LOGICAL_inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'011000 - assign \LOGICAL_inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'011001 - assign \LOGICAL_inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'011010 - assign \LOGICAL_inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'011011 - assign \LOGICAL_inv_out 1'0 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \LOGICAL_cry_out$45 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \LOGICAL_cry_out$46 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \LOGICAL_cry_out$47 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \LOGICAL_cry_out$48 - process $group_17 - assign \LOGICAL_cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'010011 - assign \LOGICAL_cry_out \LOGICAL_cry_out$45 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'011110 - assign \LOGICAL_cry_out \LOGICAL_cry_out$46 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'011111 - assign \LOGICAL_cry_out \LOGICAL_dec31_LOGICAL_cry_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'111010 - assign \LOGICAL_cry_out \LOGICAL_cry_out$47 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'111110 - assign \LOGICAL_cry_out \LOGICAL_cry_out$48 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'011100 - assign \LOGICAL_cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'011101 - assign \LOGICAL_cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'011000 - assign \LOGICAL_cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'011001 - assign \LOGICAL_cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'011010 - assign \LOGICAL_cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'011011 - assign \LOGICAL_cry_out 1'0 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \LOGICAL_is_32b$49 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \LOGICAL_is_32b$50 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \LOGICAL_is_32b$51 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \LOGICAL_is_32b$52 - process $group_18 - assign \LOGICAL_is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'010011 - assign \LOGICAL_is_32b \LOGICAL_is_32b$49 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'011110 - assign \LOGICAL_is_32b \LOGICAL_is_32b$50 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'011111 - assign \LOGICAL_is_32b \LOGICAL_dec31_LOGICAL_is_32b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'111010 - assign \LOGICAL_is_32b \LOGICAL_is_32b$51 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'111110 - assign \LOGICAL_is_32b \LOGICAL_is_32b$52 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'011100 - assign \LOGICAL_is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'011101 - assign \LOGICAL_is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'011000 - assign \LOGICAL_is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'011001 - assign \LOGICAL_is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'011010 - assign \LOGICAL_is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'011011 - assign \LOGICAL_is_32b 1'0 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \LOGICAL_sgn$53 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \LOGICAL_sgn$54 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \LOGICAL_sgn$55 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \LOGICAL_sgn$56 - process $group_19 - assign \LOGICAL_sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'010011 - assign \LOGICAL_sgn \LOGICAL_sgn$53 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'011110 - assign \LOGICAL_sgn \LOGICAL_sgn$54 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'011111 - assign \LOGICAL_sgn \LOGICAL_dec31_LOGICAL_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'111010 - assign \LOGICAL_sgn \LOGICAL_sgn$55 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'111110 - assign \LOGICAL_sgn \LOGICAL_sgn$56 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'011100 - assign \LOGICAL_sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'011101 - assign \LOGICAL_sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'011000 - assign \LOGICAL_sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'011001 - assign \LOGICAL_sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'011010 - assign \LOGICAL_sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'011011 - assign \LOGICAL_sgn 1'0 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:308" - wire width 32 \opcode_switch$57 - process $group_20 - assign \opcode_switch$57 32'00000000000000000000000000000000 - assign \opcode_switch$57 \opcode_in - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:418" - wire width 32 $58 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:418" - cell $mux $59 - parameter \WIDTH 32 - connect \A \raw_opcode_in - connect \B { \raw_opcode_in [7:0] \raw_opcode_in [15:8] \raw_opcode_in [23:16] \raw_opcode_in [31:24] } - connect \S \bigendian - connect \Y $58 - end - process $group_21 - assign \opcode_in 32'00000000000000000000000000000000 - assign \opcode_in $58 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 5 \LOGICAL_RS - process $group_22 - assign \LOGICAL_RS 5'00000 - assign \LOGICAL_RS { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 5 \LOGICAL_RT - process $group_23 - assign \LOGICAL_RT 5'00000 - assign \LOGICAL_RT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - process $group_24 - assign \LOGICAL_RA 5'00000 - assign \LOGICAL_RA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 5 \LOGICAL_RB - process $group_25 - assign \LOGICAL_RB 5'00000 - assign \LOGICAL_RB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - process $group_26 - assign \LOGICAL_SI 16'0000000000000000 - assign \LOGICAL_SI { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] \opcode_in [0] } - sync init - end - process $group_27 - assign \LOGICAL_UI 16'0000000000000000 - assign \LOGICAL_UI { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] \opcode_in [0] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 1 \LOGICAL_L - process $group_28 - assign \LOGICAL_L 1'0 - assign \LOGICAL_L { \opcode_in [21] } - sync init - end - process $group_29 - assign \LOGICAL_SH32 5'00000 - assign \LOGICAL_SH32 { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - process $group_30 - assign \LOGICAL_sh 6'000000 - assign \LOGICAL_sh { \opcode_in [1] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 5 \LOGICAL_MB32 - process $group_31 - assign \LOGICAL_MB32 5'00000 - assign \LOGICAL_MB32 { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 5 \LOGICAL_ME32 - process $group_32 - assign \LOGICAL_ME32 5'00000 - assign \LOGICAL_ME32 { \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] } - sync init - end - process $group_33 - assign \LOGICAL_LI 24'000000000000000000000000 - assign \LOGICAL_LI { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 1 \LOGICAL_LK - process $group_34 - assign \LOGICAL_LK 1'0 - assign \LOGICAL_LK { \opcode_in [0] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 1 \LOGICAL_AA - process $group_35 - assign \LOGICAL_AA 1'0 - assign \LOGICAL_AA { \opcode_in [1] } - sync init - end - process $group_36 - assign \LOGICAL_Rc 1'0 - assign \LOGICAL_Rc { \opcode_in [0] } - sync init - end - process $group_37 - assign \LOGICAL_OE 1'0 - assign \LOGICAL_OE { \opcode_in [10] } - sync init - end - process $group_38 - assign \LOGICAL_BD 14'00000000000000 - assign \LOGICAL_BD { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 3 \LOGICAL_BF - process $group_39 - assign \LOGICAL_BF 3'000 - assign \LOGICAL_BF { \opcode_in [25] \opcode_in [24] \opcode_in [23] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 10 \LOGICAL_CR - process $group_40 - assign \LOGICAL_CR 10'0000000000 - assign \LOGICAL_CR { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] } - sync init - end - process $group_41 - assign \LOGICAL_BB 5'00000 - assign \LOGICAL_BB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - process $group_42 - assign \LOGICAL_BA 5'00000 - assign \LOGICAL_BA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - process $group_43 - assign \LOGICAL_BT 5'00000 - assign \LOGICAL_BT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - process $group_44 - assign \LOGICAL_FXM 8'00000000 - assign \LOGICAL_FXM { \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 5 \LOGICAL_BO - process $group_45 - assign \LOGICAL_BO 5'00000 - assign \LOGICAL_BO { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - process $group_46 - assign \LOGICAL_BI 5'00000 - assign \LOGICAL_BI { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 2 \LOGICAL_BH - process $group_47 - assign \LOGICAL_BH 2'00 - assign \LOGICAL_BH { \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 16 \LOGICAL_D - process $group_48 - assign \LOGICAL_D 16'0000000000000000 - assign \LOGICAL_D { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] \opcode_in [0] } - sync init - end - process $group_49 - assign \LOGICAL_DS 14'00000000000000 - assign \LOGICAL_DS { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 5 \LOGICAL_TO - process $group_50 - assign \LOGICAL_TO 5'00000 - assign \LOGICAL_TO { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - process $group_51 - assign \LOGICAL_BC 5'00000 - assign \LOGICAL_BC { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 5 \LOGICAL_SH - process $group_52 - assign \LOGICAL_SH 5'00000 - assign \LOGICAL_SH { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 5 \LOGICAL_ME - process $group_53 - assign \LOGICAL_ME 5'00000 - assign \LOGICAL_ME { \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 5 \LOGICAL_MB - process $group_54 - assign \LOGICAL_MB 5'00000 - assign \LOGICAL_MB { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 10 \LOGICAL_SPR - process $group_55 - assign \LOGICAL_SPR 10'0000000000 - assign \LOGICAL_SPR { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \X_A - process $group_56 - assign \X_A 1'0 - assign \X_A { \opcode_in [25] } - sync init - end - process $group_57 - assign \X_BF 3'000 - assign \X_BF { \opcode_in [25] \opcode_in [24] \opcode_in [23] } - sync init - end - process $group_58 - assign \X_BFA 3'000 - assign \X_BFA { \opcode_in [20] \opcode_in [19] \opcode_in [18] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \X_BO - process $group_59 - assign \X_BO 5'00000 - assign \X_BO { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 4 \X_CT - process $group_60 - assign \X_CT 4'0000 - assign \X_CT { \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 7 \X_DCMX - process $group_61 - assign \X_DCMX 7'0000000 - assign \X_DCMX { \opcode_in [22] \opcode_in [21] \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 3 \X_DRM - process $group_62 - assign \X_DRM 3'000 - assign \X_DRM { \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \X_E - process $group_63 - assign \X_E 1'0 - assign \X_E { \opcode_in [15] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 4 \X_E_1 - process $group_64 - assign \X_E_1 4'0000 - assign \X_E_1 { \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 2 \X_EO - process $group_65 - assign \X_EO 2'00 - assign \X_EO { \opcode_in [20] \opcode_in [19] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \X_EO_1 - process $group_66 - assign \X_EO_1 5'00000 - assign \X_EO_1 { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \X_EX - process $group_67 - assign \X_EX 1'0 - assign \X_EX { \opcode_in [0] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \X_FC - process $group_68 - assign \X_FC 5'00000 - assign \X_FC { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \X_FRA - process $group_69 - assign \X_FRA 5'00000 - assign \X_FRA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \X_FRAp - process $group_70 - assign \X_FRAp 5'00000 - assign \X_FRAp { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \X_FRB - process $group_71 - assign \X_FRB 5'00000 - assign \X_FRB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \X_FRBp - process $group_72 - assign \X_FRBp 5'00000 - assign \X_FRBp { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \X_FRS - process $group_73 - assign \X_FRS 5'00000 - assign \X_FRS { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \X_FRSp - process $group_74 - assign \X_FRSp 5'00000 - assign \X_FRSp { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \X_FRT - process $group_75 - assign \X_FRT 5'00000 - assign \X_FRT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \X_FRTp - process $group_76 - assign \X_FRTp 5'00000 - assign \X_FRTp { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 3 \X_IH - process $group_77 - assign \X_IH 3'000 - assign \X_IH { \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 8 \X_IMM8 - process $group_78 - assign \X_IMM8 8'00000000 - assign \X_IMM8 { \opcode_in [18] \opcode_in [17] \opcode_in [16] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 2 \X_L2 - process $group_79 - assign \X_L2 2'00 - assign \X_L2 { \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \X_L - process $group_80 - assign \X_L 1'0 - assign \X_L { \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \X_L1 - process $group_81 - assign \X_L1 1'0 - assign \X_L1 { \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 2 \X_L3 - process $group_82 - assign \X_L3 2'00 - assign \X_L3 { \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \X_MO - process $group_83 - assign \X_MO 5'00000 - assign \X_MO { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \X_NB - process $group_84 - assign \X_NB 5'00000 - assign \X_NB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \X_PRS - process $group_85 - assign \X_PRS 1'0 - assign \X_PRS { \opcode_in [17] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \X_R - process $group_86 - assign \X_R 1'0 - assign \X_R { \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \X_R_1 - process $group_87 - assign \X_R_1 1'0 - assign \X_R_1 { \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \X_RA - process $group_88 - assign \X_RA 5'00000 - assign \X_RA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \X_RB - process $group_89 - assign \X_RB 5'00000 - assign \X_RB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \X_Rc - process $group_90 - assign \X_Rc 1'0 - assign \X_Rc { \opcode_in [0] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 2 \X_RIC - process $group_91 - assign \X_RIC 2'00 - assign \X_RIC { \opcode_in [19] \opcode_in [18] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 2 \X_RM - process $group_92 - assign \X_RM 2'00 - assign \X_RM { \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \X_RO - process $group_93 - assign \X_RO 1'0 - assign \X_RO { \opcode_in [0] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \X_RS - process $group_94 - assign \X_RS 5'00000 - assign \X_RS { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \X_RSp - process $group_95 - assign \X_RSp 5'00000 - assign \X_RSp { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \X_RT - process $group_96 - assign \X_RT 5'00000 - assign \X_RT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \X_RTp - process $group_97 - assign \X_RTp 5'00000 - assign \X_RTp { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \X_S - process $group_98 - assign \X_S 5'00000 - assign \X_S { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \X_SH - process $group_99 - assign \X_SH 5'00000 - assign \X_SH { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \X_SI - process $group_100 - assign \X_SI 5'00000 - assign \X_SI { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 2 \X_SP - process $group_101 - assign \X_SP 2'00 - assign \X_SP { \opcode_in [20] \opcode_in [19] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 4 \X_SR - process $group_102 - assign \X_SR 4'0000 - assign \X_SR { \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \X_SX - process $group_103 - assign \X_SX 1'0 - assign \X_SX { \opcode_in [0] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 6 \X_SX_S - process $group_104 - assign \X_SX_S 6'000000 - assign \X_SX_S { \opcode_in [0] \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \X_T - process $group_105 - assign \X_T 5'00000 - assign \X_T { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 10 \X_TBR - process $group_106 - assign \X_TBR 10'0000000000 - assign \X_TBR { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \X_TH - process $group_107 - assign \X_TH 5'00000 - assign \X_TH { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \X_TO - process $group_108 - assign \X_TO 5'00000 - assign \X_TO { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \X_TX - process $group_109 - assign \X_TX 1'0 - assign \X_TX { \opcode_in [0] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 6 \X_TX_T - process $group_110 - assign \X_TX_T 6'000000 - assign \X_TX_T { \opcode_in [0] \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 4 \X_U - process $group_111 - assign \X_U 4'0000 - assign \X_U { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \X_UIM - process $group_112 - assign \X_UIM 5'00000 - assign \X_UIM { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \X_VRS - process $group_113 - assign \X_VRS 5'00000 - assign \X_VRS { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \X_VRT - process $group_114 - assign \X_VRT 5'00000 - assign \X_VRT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \X_W - process $group_115 - assign \X_W 1'0 - assign \X_W { \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 2 \X_WC - process $group_116 - assign \X_WC 2'00 - assign \X_WC { \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 10 \X_XO - process $group_117 - assign \X_XO 10'0000000000 - assign \X_XO { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 8 \X_XO_1 - process $group_118 - assign \X_XO_1 8'00000000 - assign \X_XO_1 { \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \B_AA - process $group_119 - assign \B_AA 1'0 - assign \B_AA { \opcode_in [1] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 14 \B_BD - process $group_120 - assign \B_BD 14'00000000000000 - assign \B_BD { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \B_BI - process $group_121 - assign \B_BI 5'00000 - assign \B_BI { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \B_BO - process $group_122 - assign \B_BO 5'00000 - assign \B_BO { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \B_LK - process $group_123 - assign \B_LK 1'0 - assign \B_LK { \opcode_in [0] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \I_AA - process $group_124 - assign \I_AA 1'0 - assign \I_AA { \opcode_in [1] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 24 \I_LI - process $group_125 - assign \I_LI 24'000000000000000000000000 - assign \I_LI { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \I_LK - process $group_126 - assign \I_LK 1'0 - assign \I_LK { \opcode_in [0] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \XX3_AX - process $group_127 - assign \XX3_AX 1'0 - assign \XX3_AX { \opcode_in [2] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \XX3_A - process $group_128 - assign \XX3_A 5'00000 - assign \XX3_A { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 6 \XX3_AX_A - process $group_129 - assign \XX3_AX_A 6'000000 - assign \XX3_AX_A { \opcode_in [2] \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 3 \XX3_BF - process $group_130 - assign \XX3_BF 3'000 - assign \XX3_BF { \opcode_in [25] \opcode_in [24] \opcode_in [23] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \XX3_BX - process $group_131 - assign \XX3_BX 1'0 - assign \XX3_BX { \opcode_in [1] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \XX3_B - process $group_132 - assign \XX3_B 5'00000 - assign \XX3_B { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 6 \XX3_BX_B - process $group_133 - assign \XX3_BX_B 6'000000 - assign \XX3_BX_B { \opcode_in [1] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 2 \XX3_DM - process $group_134 - assign \XX3_DM 2'00 - assign \XX3_DM { \opcode_in [9] \opcode_in [8] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \XX3_Rc - process $group_135 - assign \XX3_Rc 1'0 - assign \XX3_Rc { \opcode_in [10] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 2 \XX3_SHW - process $group_136 - assign \XX3_SHW 2'00 - assign \XX3_SHW { \opcode_in [9] \opcode_in [8] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \XX3_TX - process $group_137 - assign \XX3_TX 1'0 - assign \XX3_TX { \opcode_in [0] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \XX3_T - process $group_138 - assign \XX3_T 5'00000 - assign \XX3_T { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 6 \XX3_TX_T - process $group_139 - assign \XX3_TX_T 6'000000 - assign \XX3_TX_T { \opcode_in [0] \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 4 \XX3_XO - process $group_140 - assign \XX3_XO 4'0000 - assign \XX3_XO { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 8 \XX3_XO_1 - process $group_141 - assign \XX3_XO_1 8'00000000 - assign \XX3_XO_1 { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 9 \XX3_XO_2 - process $group_142 - assign \XX3_XO_2 9'000000000 - assign \XX3_XO_2 { \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \XX4_AX - process $group_143 - assign \XX4_AX 1'0 - assign \XX4_AX { \opcode_in [2] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \XX4_A - process $group_144 - assign \XX4_A 5'00000 - assign \XX4_A { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 6 \XX4_AX_A - process $group_145 - assign \XX4_AX_A 6'000000 - assign \XX4_AX_A { \opcode_in [2] \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \XX4_BX - process $group_146 - assign \XX4_BX 1'0 - assign \XX4_BX { \opcode_in [1] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \XX4_B - process $group_147 - assign \XX4_B 5'00000 - assign \XX4_B { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 6 \XX4_BX_B - process $group_148 - assign \XX4_BX_B 6'000000 - assign \XX4_BX_B { \opcode_in [1] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \XX4_CX - process $group_149 - assign \XX4_CX 1'0 - assign \XX4_CX { \opcode_in [3] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \XX4_C - process $group_150 - assign \XX4_C 5'00000 - assign \XX4_C { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 6 \XX4_CX_C - process $group_151 - assign \XX4_CX_C 6'000000 - assign \XX4_CX_C { \opcode_in [3] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \XX4_TX - process $group_152 - assign \XX4_TX 1'0 - assign \XX4_TX { \opcode_in [0] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \XX4_T - process $group_153 - assign \XX4_T 5'00000 - assign \XX4_T { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 6 \XX4_TX_T - process $group_154 - assign \XX4_TX_T 6'000000 - assign \XX4_TX_T { \opcode_in [0] \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 2 \XX4_XO - process $group_155 - assign \XX4_XO 2'00 - assign \XX4_XO { \opcode_in [5] \opcode_in [4] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \XL_BA - process $group_156 - assign \XL_BA 5'00000 - assign \XL_BA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \XL_BB - process $group_157 - assign \XL_BB 5'00000 - assign \XL_BB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 3 \XL_BF - process $group_158 - assign \XL_BF 3'000 - assign \XL_BF { \opcode_in [25] \opcode_in [24] \opcode_in [23] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 3 \XL_BFA - process $group_159 - assign \XL_BFA 3'000 - assign \XL_BFA { \opcode_in [20] \opcode_in [19] \opcode_in [18] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 2 \XL_BH - process $group_160 - assign \XL_BH 2'00 - assign \XL_BH { \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \XL_BI - process $group_161 - assign \XL_BI 5'00000 - assign \XL_BI { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \XL_BO - process $group_162 - assign \XL_BO 5'00000 - assign \XL_BO { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \XL_BO_1 - process $group_163 - assign \XL_BO_1 5'00000 - assign \XL_BO_1 { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - process $group_164 - assign \XL_BT 5'00000 - assign \XL_BT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \XL_LK - process $group_165 - assign \XL_LK 1'0 - assign \XL_LK { \opcode_in [0] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 15 \XL_OC - process $group_166 - assign \XL_OC 15'000000000000000 - assign \XL_OC { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \XL_S - process $group_167 - assign \XL_S 1'0 - assign \XL_S { \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 10 \XL_XO - process $group_168 - assign \XL_XO 10'0000000000 - assign \XL_XO { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \A_BC - process $group_169 - assign \A_BC 5'00000 - assign \A_BC { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \A_FRA - process $group_170 - assign \A_FRA 5'00000 - assign \A_FRA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \A_FRB - process $group_171 - assign \A_FRB 5'00000 - assign \A_FRB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \A_FRC - process $group_172 - assign \A_FRC 5'00000 - assign \A_FRC { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \A_FRT - process $group_173 - assign \A_FRT 5'00000 - assign \A_FRT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \A_RA - process $group_174 - assign \A_RA 5'00000 - assign \A_RA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \A_RB - process $group_175 - assign \A_RB 5'00000 - assign \A_RB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \A_Rc - process $group_176 - assign \A_Rc 1'0 - assign \A_Rc { \opcode_in [0] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \A_RT - process $group_177 - assign \A_RT 5'00000 - assign \A_RT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \A_XO - process $group_178 - assign \A_XO 5'00000 - assign \A_XO { \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 3 \D_BF - process $group_179 - assign \D_BF 3'000 - assign \D_BF { \opcode_in [25] \opcode_in [24] \opcode_in [23] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 16 \D_D - process $group_180 - assign \D_D 16'0000000000000000 - assign \D_D { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] \opcode_in [0] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \D_FRS - process $group_181 - assign \D_FRS 5'00000 - assign \D_FRS { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \D_FRT - process $group_182 - assign \D_FRT 5'00000 - assign \D_FRT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \D_L - process $group_183 - assign \D_L 1'0 - assign \D_L { \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \D_RA - process $group_184 - assign \D_RA 5'00000 - assign \D_RA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \D_RS - process $group_185 - assign \D_RS 5'00000 - assign \D_RS { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \D_RT - process $group_186 - assign \D_RT 5'00000 - assign \D_RT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 16 \D_SI - process $group_187 - assign \D_SI 16'0000000000000000 - assign \D_SI { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] \opcode_in [0] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \D_TO - process $group_188 - assign \D_TO 5'00000 - assign \D_TO { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 16 \D_UI - process $group_189 - assign \D_UI 16'0000000000000000 - assign \D_UI { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] \opcode_in [0] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 3 \XX2_BF - process $group_190 - assign \XX2_BF 3'000 - assign \XX2_BF { \opcode_in [25] \opcode_in [24] \opcode_in [23] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \XX2_BX - process $group_191 - assign \XX2_BX 1'0 - assign \XX2_BX { \opcode_in [1] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \XX2_B - process $group_192 - assign \XX2_B 5'00000 - assign \XX2_B { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 6 \XX2_BX_B - process $group_193 - assign \XX2_BX_B 6'000000 - assign \XX2_BX_B { \opcode_in [1] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \XX2_dc - process $group_194 - assign \XX2_dc 1'0 - assign \XX2_dc { \opcode_in [6] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \XX2_dm - process $group_195 - assign \XX2_dm 1'0 - assign \XX2_dm { \opcode_in [2] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \XX2_dx - process $group_196 - assign \XX2_dx 5'00000 - assign \XX2_dx { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 7 \XX2_dc_dm_dx - process $group_197 - assign \XX2_dc_dm_dx 7'0000000 - assign \XX2_dc_dm_dx { \opcode_in [6] \opcode_in [2] \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 7 \XX2_DCMX - process $group_198 - assign \XX2_DCMX 7'0000000 - assign \XX2_DCMX { \opcode_in [22] \opcode_in [21] \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \XX2_EO - process $group_199 - assign \XX2_EO 5'00000 - assign \XX2_EO { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \XX2_RT - process $group_200 - assign \XX2_RT 5'00000 - assign \XX2_RT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \XX2_TX - process $group_201 - assign \XX2_TX 1'0 - assign \XX2_TX { \opcode_in [0] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \XX2_T - process $group_202 - assign \XX2_T 5'00000 - assign \XX2_T { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 6 \XX2_TX_T - process $group_203 - assign \XX2_TX_T 6'000000 - assign \XX2_TX_T { \opcode_in [0] \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 4 \XX2_UIM - process $group_204 - assign \XX2_UIM 4'0000 - assign \XX2_UIM { \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 2 \XX2_UIM_1 - process $group_205 - assign \XX2_UIM_1 2'00 - assign \XX2_UIM_1 { \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 7 \XX2_XO - process $group_206 - assign \XX2_XO 7'0000000 - assign \XX2_XO { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [5] \opcode_in [4] \opcode_in [3] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 9 \XX2_XO_1 - process $group_207 - assign \XX2_XO_1 9'000000000 - assign \XX2_XO_1 { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 3 \Z22_BF - process $group_208 - assign \Z22_BF 3'000 - assign \Z22_BF { \opcode_in [25] \opcode_in [24] \opcode_in [23] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 6 \Z22_DCM - process $group_209 - assign \Z22_DCM 6'000000 - assign \Z22_DCM { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 6 \Z22_DGM - process $group_210 - assign \Z22_DGM 6'000000 - assign \Z22_DGM { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \Z22_FRA - process $group_211 - assign \Z22_FRA 5'00000 - assign \Z22_FRA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \Z22_FRAp - process $group_212 - assign \Z22_FRAp 5'00000 - assign \Z22_FRAp { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \Z22_FRT - process $group_213 - assign \Z22_FRT 5'00000 - assign \Z22_FRT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \Z22_FRTp - process $group_214 - assign \Z22_FRTp 5'00000 - assign \Z22_FRTp { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \Z22_Rc - process $group_215 - assign \Z22_Rc 1'0 - assign \Z22_Rc { \opcode_in [0] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 6 \Z22_SH - process $group_216 - assign \Z22_SH 6'000000 - assign \Z22_SH { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 9 \Z22_XO - process $group_217 - assign \Z22_XO 9'000000000 - assign \Z22_XO { \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 3 \EVS_BFA - process $group_218 - assign \EVS_BFA 3'000 - assign \EVS_BFA { \opcode_in [2] \opcode_in [1] \opcode_in [0] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 10 \XFX_BHRBE - process $group_219 - assign \XFX_BHRBE 10'0000000000 - assign \XFX_BHRBE { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \XFX_DUI - process $group_220 - assign \XFX_DUI 5'00000 - assign \XFX_DUI { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 10 \XFX_DUIS - process $group_221 - assign \XFX_DUIS 10'0000000000 - assign \XFX_DUIS { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 8 \XFX_FXM - process $group_222 - assign \XFX_FXM 8'00000000 - assign \XFX_FXM { \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \XFX_RS - process $group_223 - assign \XFX_RS 5'00000 - assign \XFX_RS { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \XFX_RT - process $group_224 - assign \XFX_RT 5'00000 - assign \XFX_RT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 10 \XFX_SPR - process $group_225 - assign \XFX_SPR 10'0000000000 - assign \XFX_SPR { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 10 \XFX_XO - process $group_226 - assign \XFX_XO 10'0000000000 - assign \XFX_XO { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 10 \DX_d0 - process $group_227 - assign \DX_d0 10'0000000000 - assign \DX_d0 { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \DX_d1 - process $group_228 - assign \DX_d1 5'00000 - assign \DX_d1 { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \DX_d2 - process $group_229 - assign \DX_d2 1'0 - assign \DX_d2 { \opcode_in [0] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 16 \DX_d0_d1_d2 - process $group_230 - assign \DX_d0_d1_d2 16'0000000000000000 - assign \DX_d0_d1_d2 { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] \opcode_in [0] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \DX_RT - process $group_231 - assign \DX_RT 5'00000 - assign \DX_RT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \DX_XO - process $group_232 - assign \DX_XO 5'00000 - assign \DX_XO { \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 12 \DQ_DQ - process $group_233 - assign \DQ_DQ 12'000000000000 - assign \DQ_DQ { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 4 \DQ_PT - process $group_234 - assign \DQ_PT 4'0000 - assign \DQ_PT { \opcode_in [3] \opcode_in [2] \opcode_in [1] \opcode_in [0] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \DQ_RA - process $group_235 - assign \DQ_RA 5'00000 - assign \DQ_RA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \DQ_RTp - process $group_236 - assign \DQ_RTp 5'00000 - assign \DQ_RTp { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \DQ_SX - process $group_237 - assign \DQ_SX 1'0 - assign \DQ_SX { \opcode_in [3] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \DQ_S - process $group_238 - assign \DQ_S 5'00000 - assign \DQ_S { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 6 \DQ_SX_S - process $group_239 - assign \DQ_SX_S 6'000000 - assign \DQ_SX_S { \opcode_in [3] \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \DQ_TX - process $group_240 - assign \DQ_TX 1'0 - assign \DQ_TX { \opcode_in [3] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \DQ_T - process $group_241 - assign \DQ_T 5'00000 - assign \DQ_T { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 6 \DQ_TX_T - process $group_242 - assign \DQ_TX_T 6'000000 - assign \DQ_TX_T { \opcode_in [3] \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 3 \DQ_XO - process $group_243 - assign \DQ_XO 3'000 - assign \DQ_XO { \opcode_in [2] \opcode_in [1] \opcode_in [0] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 14 \DS_DS - process $group_244 - assign \DS_DS 14'00000000000000 - assign \DS_DS { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \DS_FRSp - process $group_245 - assign \DS_FRSp 5'00000 - assign \DS_FRSp { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \DS_FRTp - process $group_246 - assign \DS_FRTp 5'00000 - assign \DS_FRTp { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \DS_RA - process $group_247 - assign \DS_RA 5'00000 - assign \DS_RA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \DS_RS - process $group_248 - assign \DS_RS 5'00000 - assign \DS_RS { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \DS_RSp - process $group_249 - assign \DS_RSp 5'00000 - assign \DS_RSp { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \DS_RT - process $group_250 - assign \DS_RT 5'00000 - assign \DS_RT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \DS_VRS - process $group_251 - assign \DS_VRS 5'00000 - assign \DS_VRS { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \DS_VRT - process $group_252 - assign \DS_VRT 5'00000 - assign \DS_VRT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 2 \DS_XO - process $group_253 - assign \DS_XO 2'00 - assign \DS_XO { \opcode_in [1] \opcode_in [0] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \VX_EO - process $group_254 - assign \VX_EO 5'00000 - assign \VX_EO { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \VX_PS - process $group_255 - assign \VX_PS 1'0 - assign \VX_PS { \opcode_in [9] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \VX_RA - process $group_256 - assign \VX_RA 5'00000 - assign \VX_RA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \VX_RT - process $group_257 - assign \VX_RT 5'00000 - assign \VX_RT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \VX_SIM - process $group_258 - assign \VX_SIM 5'00000 - assign \VX_SIM { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \VX_UIM - process $group_259 - assign \VX_UIM 5'00000 - assign \VX_UIM { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 4 \VX_UIM_1 - process $group_260 - assign \VX_UIM_1 4'0000 - assign \VX_UIM_1 { \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 3 \VX_UIM_2 - process $group_261 - assign \VX_UIM_2 3'000 - assign \VX_UIM_2 { \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 2 \VX_UIM_3 - process $group_262 - assign \VX_UIM_3 2'00 - assign \VX_UIM_3 { \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \VX_VRA - process $group_263 - assign \VX_VRA 5'00000 - assign \VX_VRA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \VX_VRB - process $group_264 - assign \VX_VRB 5'00000 - assign \VX_VRB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \VX_VRT - process $group_265 - assign \VX_VRT 5'00000 - assign \VX_VRT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 10 \VX_XO - process $group_266 - assign \VX_XO 10'0000000000 - assign \VX_XO { \opcode_in [10] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] \opcode_in [0] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 11 \VX_XO_1 - process $group_267 - assign \VX_XO_1 11'00000000000 - assign \VX_XO_1 { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] \opcode_in [0] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 8 \XFL_FLM - process $group_268 - assign \XFL_FLM 8'00000000 - assign \XFL_FLM { \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \XFL_FRB - process $group_269 - assign \XFL_FRB 5'00000 - assign \XFL_FRB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \XFL_L - process $group_270 - assign \XFL_L 1'0 - assign \XFL_L { \opcode_in [25] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \XFL_Rc - process $group_271 - assign \XFL_Rc 1'0 - assign \XFL_Rc { \opcode_in [0] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \XFL_W - process $group_272 - assign \XFL_W 1'0 - assign \XFL_W { \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 10 \XFL_XO - process $group_273 - assign \XFL_XO 10'0000000000 - assign \XFL_XO { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \Z23_FRA - process $group_274 - assign \Z23_FRA 5'00000 - assign \Z23_FRA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \Z23_FRAp - process $group_275 - assign \Z23_FRAp 5'00000 - assign \Z23_FRAp { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \Z23_FRB - process $group_276 - assign \Z23_FRB 5'00000 - assign \Z23_FRB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \Z23_FRBp - process $group_277 - assign \Z23_FRBp 5'00000 - assign \Z23_FRBp { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \Z23_FRT - process $group_278 - assign \Z23_FRT 5'00000 - assign \Z23_FRT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \Z23_FRTp - process $group_279 - assign \Z23_FRTp 5'00000 - assign \Z23_FRTp { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \Z23_R - process $group_280 - assign \Z23_R 1'0 - assign \Z23_R { \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \Z23_Rc - process $group_281 - assign \Z23_Rc 1'0 - assign \Z23_Rc { \opcode_in [0] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 2 \Z23_RMC - process $group_282 - assign \Z23_RMC 2'00 - assign \Z23_RMC { \opcode_in [10] \opcode_in [9] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \Z23_TE - process $group_283 - assign \Z23_TE 5'00000 - assign \Z23_TE { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 8 \Z23_XO - process $group_284 - assign \Z23_XO 8'00000000 - assign \Z23_XO { \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \MDS_IB - process $group_285 - assign \MDS_IB 5'00000 - assign \MDS_IB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \MDS_IS - process $group_286 - assign \MDS_IS 5'00000 - assign \MDS_IS { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 6 \MDS_mb - process $group_287 - assign \MDS_mb 6'000000 - assign \MDS_mb { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 6 \MDS_me - process $group_288 - assign \MDS_me 6'000000 - assign \MDS_me { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \MDS_RA - process $group_289 - assign \MDS_RA 5'00000 - assign \MDS_RA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \MDS_RB - process $group_290 - assign \MDS_RB 5'00000 - assign \MDS_RB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \MDS_Rc - process $group_291 - assign \MDS_Rc 1'0 - assign \MDS_Rc { \opcode_in [0] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \MDS_RS - process $group_292 - assign \MDS_RS 5'00000 - assign \MDS_RS { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 4 \MDS_XBI - process $group_293 - assign \MDS_XBI 4'0000 - assign \MDS_XBI { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 4 \MDS_XBI_1 - process $group_294 - assign \MDS_XBI_1 4'0000 - assign \MDS_XBI_1 { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 4 \MDS_XO - process $group_295 - assign \MDS_XO 4'0000 - assign \MDS_XO { \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 7 \SC_LEV - process $group_296 - assign \SC_LEV 7'0000000 - assign \SC_LEV { \opcode_in [11] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \SC_XO - process $group_297 - assign \SC_XO 1'0 - assign \SC_XO { \opcode_in [1] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 2 \SC_XO_1 - process $group_298 - assign \SC_XO_1 2'00 - assign \SC_XO_1 { \opcode_in [1] \opcode_in [0] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \M_MB - process $group_299 - assign \M_MB 5'00000 - assign \M_MB { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \M_ME - process $group_300 - assign \M_ME 5'00000 - assign \M_ME { \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \M_RA - process $group_301 - assign \M_RA 5'00000 - assign \M_RA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \M_RB - process $group_302 - assign \M_RB 5'00000 - assign \M_RB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \M_Rc - process $group_303 - assign \M_Rc 1'0 - assign \M_Rc { \opcode_in [0] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \M_RS - process $group_304 - assign \M_RS 5'00000 - assign \M_RS { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \M_SH - process $group_305 - assign \M_SH 5'00000 - assign \M_SH { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 6 \MD_mb - process $group_306 - assign \MD_mb 6'000000 - assign \MD_mb { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 6 \MD_me - process $group_307 - assign \MD_me 6'000000 - assign \MD_me { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \MD_RA - process $group_308 - assign \MD_RA 5'00000 - assign \MD_RA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \MD_Rc - process $group_309 - assign \MD_Rc 1'0 - assign \MD_Rc { \opcode_in [0] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \MD_RS - process $group_310 - assign \MD_RS 5'00000 - assign \MD_RS { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 6 \MD_sh - process $group_311 - assign \MD_sh 6'000000 - assign \MD_sh { \opcode_in [1] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 3 \MD_XO - process $group_312 - assign \MD_XO 3'000 - assign \MD_XO { \opcode_in [4] \opcode_in [3] \opcode_in [2] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 6 \all_OPCD - process $group_313 - assign \all_OPCD 6'000000 - assign \all_OPCD { \opcode_in [31] \opcode_in [30] \opcode_in [29] \opcode_in [28] \opcode_in [27] \opcode_in [26] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 6 \all_PO - process $group_314 - assign \all_PO 6'000000 - assign \all_PO { \opcode_in [31] \opcode_in [30] \opcode_in [29] \opcode_in [28] \opcode_in [27] \opcode_in [26] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \XO_OE - process $group_315 - assign \XO_OE 1'0 - assign \XO_OE { \opcode_in [10] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \XO_RA - process $group_316 - assign \XO_RA 5'00000 - assign \XO_RA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \XO_RB - process $group_317 - assign \XO_RB 5'00000 - assign \XO_RB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \XO_Rc - process $group_318 - assign \XO_Rc 1'0 - assign \XO_Rc { \opcode_in [0] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \XO_RT - process $group_319 - assign \XO_RT 5'00000 - assign \XO_RT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 9 \XO_XO - process $group_320 - assign \XO_XO 9'000000000 - assign \XO_XO { \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \DQE_RA - process $group_321 - assign \DQE_RA 5'00000 - assign \DQE_RA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \DQE_RT - process $group_322 - assign \DQE_RT 5'00000 - assign \DQE_RT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 2 \DQE_XO - process $group_323 - assign \DQE_XO 2'00 - assign \DQE_XO { \opcode_in [1] \opcode_in [0] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \TX_RA - process $group_324 - assign \TX_RA 5'00000 - assign \TX_RA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \TX_UI - process $group_325 - assign \TX_UI 5'00000 - assign \TX_UI { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 4 \TX_XBI - process $group_326 - assign \TX_XBI 4'0000 - assign \TX_XBI { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 6 \TX_XO - process $group_327 - assign \TX_XO 6'000000 - assign \TX_XO { \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \VA_RA - process $group_328 - assign \VA_RA 5'00000 - assign \VA_RA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \VA_RB - process $group_329 - assign \VA_RB 5'00000 - assign \VA_RB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \VA_RC - process $group_330 - assign \VA_RC 5'00000 - assign \VA_RC { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \VA_RT - process $group_331 - assign \VA_RT 5'00000 - assign \VA_RT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 4 \VA_SHB - process $group_332 - assign \VA_SHB 4'0000 - assign \VA_SHB { \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \VA_VRA - process $group_333 - assign \VA_VRA 5'00000 - assign \VA_VRA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \VA_VRB - process $group_334 - assign \VA_VRB 5'00000 - assign \VA_VRB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \VA_VRC - process $group_335 - assign \VA_VRC 5'00000 - assign \VA_VRC { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \VA_VRT - process $group_336 - assign \VA_VRT 5'00000 - assign \VA_VRT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 6 \VA_XO - process $group_337 - assign \VA_XO 6'000000 - assign \VA_XO { \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] \opcode_in [0] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \XS_RA - process $group_338 - assign \XS_RA 5'00000 - assign \XS_RA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \XS_Rc - process $group_339 - assign \XS_Rc 1'0 - assign \XS_Rc { \opcode_in [0] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \XS_RS - process $group_340 - assign \XS_RS 5'00000 - assign \XS_RS { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 6 \XS_sh - process $group_341 - assign \XS_sh 6'000000 - assign \XS_sh { \opcode_in [1] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 9 \XS_XO - process $group_342 - assign \XS_XO 9'000000000 - assign \XS_XO { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \VC_Rc - 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- attribute \nmigen.decoding "ONE/1" - case 2'01 - assign \rc_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:420" - attribute \nmigen.decoding "NONE/0" - case 2'00 - assign \rc_ok 1'1 - end - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.dec_LOGICAL.dec_oe" -module \dec_oe$154 - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:441" - wire width 2 input 0 \sel_in - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - 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attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 3 \oe_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 1 input 4 \LOGICAL_OE - process $group_0 - assign \oe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:450" - switch \LOGICAL_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:461" - attribute \nmigen.decoding "OP_MUL_H64/51|OP_MUL_H32/52|OP_EXTS/31|OP_CNTZ/14|OP_SHL/60|OP_SHR/61|OP_RLC/56|OP_LOAD/37|OP_STORE/38|OP_RLCL/57|OP_RLCR/58|OP_EXTSWSLI/32" - case 7'0110011, 7'0110100, 7'0011111, 7'0001110, 7'0111100, 7'0111101, 7'0111000, 7'0100101, 7'0100110, 7'0111001, 7'0111010, 7'0100000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:465" - attribute \nmigen.decoding "" - case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:467" - switch 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\en_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" - wire width 1 $31 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" - cell $reduce_bool $32 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \o - connect \Y $31 - end - process $group_10 - assign \en_o 1'0 - assign \en_o $31 - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.dec_LOGICAL.dec_cr_in" -module \dec_cr_in$155 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:485" - wire width 32 input 0 \insn_in - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:484" - wire width 3 input 1 \sel_in - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 7 input 2 \LOGICAL_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 5 input 3 \LOGICAL_BB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 5 input 4 \LOGICAL_BA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 5 input 5 \LOGICAL_BT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 8 input 6 \LOGICAL_FXM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 5 input 7 \LOGICAL_BI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 5 input 8 \LOGICAL_BC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 3 input 9 \X_BFA - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" - wire width 8 \ppick_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" - wire width 8 \ppick_o - cell \ppick$156 \ppick - connect \i \ppick_i - connect \o \ppick_o - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \cr_bitfield_ok - process $group_0 - assign \cr_bitfield_ok 1'0 - assign \cr_bitfield_ok 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" - switch \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" - attribute \nmigen.decoding "NONE/0" - case 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:505" - attribute \nmigen.decoding "CR0/1" - case 3'001 - assign \cr_bitfield_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:508" - attribute \nmigen.decoding "BI/2" - case 3'010 - assign \cr_bitfield_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:511" - attribute \nmigen.decoding "BFA/3" - case 3'011 - assign \cr_bitfield_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:514" - attribute \nmigen.decoding "BA_BB/4" - case 3'100 - assign \cr_bitfield_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:521" - attribute \nmigen.decoding "BC/5" - case 3'101 - assign \cr_bitfield_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:524" - attribute \nmigen.decoding "WHOLE_REG/6" - case 3'110 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \cr_bitfield_b_ok - process $group_1 - assign \cr_bitfield_b_ok 1'0 - assign \cr_bitfield_b_ok 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" - switch \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" - attribute \nmigen.decoding "NONE/0" - case 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:505" - attribute \nmigen.decoding "CR0/1" - case 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:508" - attribute \nmigen.decoding "BI/2" - case 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:511" - attribute \nmigen.decoding "BFA/3" - case 3'011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:514" - attribute \nmigen.decoding "BA_BB/4" - case 3'100 - assign \cr_bitfield_b_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:521" - attribute \nmigen.decoding "BC/5" - case 3'101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:524" - attribute \nmigen.decoding "WHOLE_REG/6" - case 3'110 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \cr_fxm_ok - process $group_2 - assign \cr_fxm_ok 1'0 - assign \cr_fxm_ok 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" - switch \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" - attribute \nmigen.decoding "NONE/0" - case 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:505" - attribute \nmigen.decoding "CR0/1" - case 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:508" - attribute \nmigen.decoding "BI/2" - case 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:511" - attribute \nmigen.decoding "BFA/3" - case 3'011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:514" - attribute \nmigen.decoding "BA_BB/4" - case 3'100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:521" - attribute \nmigen.decoding "BC/5" - case 3'101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:524" - attribute \nmigen.decoding "WHOLE_REG/6" - case 3'110 - assign \cr_fxm_ok 1'1 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 3 \cr_bitfield - process $group_3 - assign \cr_bitfield 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" - switch \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" - attribute \nmigen.decoding "NONE/0" - case 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:505" - attribute \nmigen.decoding "CR0/1" - case 3'001 - assign \cr_bitfield 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:508" - attribute \nmigen.decoding "BI/2" - case 3'010 - assign \cr_bitfield \LOGICAL_BI [4:2] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:511" - attribute \nmigen.decoding "BFA/3" - case 3'011 - assign \cr_bitfield \X_BFA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:514" - attribute \nmigen.decoding "BA_BB/4" - case 3'100 - assign \cr_bitfield \LOGICAL_BA [4:2] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:521" - attribute \nmigen.decoding "BC/5" - case 3'101 - assign \cr_bitfield \LOGICAL_BC [4:2] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:524" - attribute \nmigen.decoding "WHOLE_REG/6" - case 3'110 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 3 \cr_bitfield_b - process $group_4 - assign \cr_bitfield_b 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" - switch \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" - attribute \nmigen.decoding "NONE/0" - case 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:505" - attribute \nmigen.decoding "CR0/1" - case 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:508" - attribute \nmigen.decoding "BI/2" - case 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:511" - attribute \nmigen.decoding "BFA/3" - case 3'011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:514" - attribute \nmigen.decoding "BA_BB/4" - case 3'100 - assign \cr_bitfield_b \LOGICAL_BB [4:2] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:521" - attribute \nmigen.decoding "BC/5" - case 3'101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:524" - attribute \nmigen.decoding "WHOLE_REG/6" - case 3'110 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 3 \cr_bitfield_o - process $group_5 - assign \cr_bitfield_o 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" - switch \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" - attribute \nmigen.decoding "NONE/0" - case 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:505" - attribute \nmigen.decoding "CR0/1" - case 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:508" - attribute \nmigen.decoding "BI/2" - case 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:511" - attribute \nmigen.decoding "BFA/3" - case 3'011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:514" - attribute \nmigen.decoding "BA_BB/4" - case 3'100 - assign \cr_bitfield_o \LOGICAL_BT [4:2] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:521" - attribute \nmigen.decoding "BC/5" - case 3'101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:524" - attribute \nmigen.decoding "WHOLE_REG/6" - case 3'110 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \cr_bitfield_o_ok - process $group_6 - assign \cr_bitfield_o_ok 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" - switch \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" - attribute \nmigen.decoding "NONE/0" - case 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:505" - attribute \nmigen.decoding "CR0/1" - case 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:508" - attribute \nmigen.decoding "BI/2" - case 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:511" - attribute \nmigen.decoding "BFA/3" - case 3'011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:514" - attribute \nmigen.decoding "BA_BB/4" - case 3'100 - assign \cr_bitfield_o_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:521" - attribute \nmigen.decoding "BC/5" - case 3'101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:524" - attribute \nmigen.decoding "WHOLE_REG/6" - case 3'110 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:526" - wire width 1 \move_one - process $group_7 - assign \move_one 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" - switch \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" - attribute \nmigen.decoding "NONE/0" - case 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:505" - attribute \nmigen.decoding "CR0/1" - case 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:508" - attribute \nmigen.decoding "BI/2" - case 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:511" - attribute \nmigen.decoding "BFA/3" - case 3'011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:514" - attribute \nmigen.decoding "BA_BB/4" - case 3'100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:521" - attribute \nmigen.decoding "BC/5" - case 3'101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:524" - attribute \nmigen.decoding "WHOLE_REG/6" - case 3'110 - assign \move_one \insn_in [20] - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" - cell $eq $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A \LOGICAL_internal_op - connect \B 7'0101101 - connect \Y $1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" - wire width 1 $3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" - cell $and $4 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $1 - connect \B \move_one - connect \Y $3 - end - process $group_8 - assign \ppick_i 8'00000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" - switch \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" - attribute \nmigen.decoding "NONE/0" - case 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:505" - attribute \nmigen.decoding "CR0/1" - case 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:508" - attribute \nmigen.decoding "BI/2" - case 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:511" - attribute \nmigen.decoding "BFA/3" - case 3'011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:514" - attribute \nmigen.decoding "BA_BB/4" - case 3'100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:521" - attribute \nmigen.decoding "BC/5" - case 3'101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:524" - attribute \nmigen.decoding "WHOLE_REG/6" - case 3'110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" - switch { $3 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" - case 1'1 - assign \ppick_i \LOGICAL_FXM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532" - case - end - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 8 \cr_fxm - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" - wire width 1 $5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" - cell $eq $6 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A \LOGICAL_internal_op - connect \B 7'0101101 - connect \Y $5 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" - wire width 1 $7 - attribute \src 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$group_1 - assign \cr_fxm_ok 1'0 - assign \cr_fxm_ok 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:563" - switch \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:564" - attribute \nmigen.decoding "NONE/0" - case 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:566" - attribute \nmigen.decoding "CR0/1" - case 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:569" - attribute \nmigen.decoding "BF/2" - case 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:572" - attribute \nmigen.decoding "BT/3" - case 3'011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:575" - attribute \nmigen.decoding "WHOLE_REG/4" - case 3'100 - assign \cr_fxm_ok 1'1 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 3 \cr_bitfield - process $group_2 - assign \cr_bitfield 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:563" - switch \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:564" - attribute \nmigen.decoding "NONE/0" - case 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:566" - attribute \nmigen.decoding "CR0/1" - case 3'001 - assign \cr_bitfield 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:569" - attribute \nmigen.decoding "BF/2" - case 3'010 - assign \cr_bitfield \X_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:572" - attribute \nmigen.decoding "BT/3" - case 3'011 - assign \cr_bitfield \XL_BT [4:2] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:575" - attribute \nmigen.decoding "WHOLE_REG/4" - case 3'100 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:577" - wire width 1 \move_one - process $group_3 - assign \move_one 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:563" - switch \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:564" - attribute \nmigen.decoding "NONE/0" - case 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:566" - attribute \nmigen.decoding "CR0/1" - case 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:569" - attribute \nmigen.decoding "BF/2" - case 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:572" - attribute \nmigen.decoding "BT/3" - case 3'011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:575" - attribute \nmigen.decoding "WHOLE_REG/4" - case 3'100 - assign \move_one \insn_in [20] - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:579" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:579" - cell $eq $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A \LOGICAL_internal_op - connect \B 7'0110000 - connect \Y $1 - end - process $group_4 - assign \ppick_i 8'00000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:563" - switch \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:564" - attribute \nmigen.decoding "NONE/0" - case 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:566" - attribute \nmigen.decoding "CR0/1" - case 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:569" - attribute \nmigen.decoding "BF/2" - case 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:572" - attribute \nmigen.decoding "BT/3" - case 3'011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:575" - attribute \nmigen.decoding "WHOLE_REG/4" - case 3'100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:579" - switch { $1 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:579" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:580" - switch { \move_one } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:580" - case 1'1 - assign \ppick_i \LOGICAL_FXM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:587" - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:589" - case - end - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 8 \cr_fxm - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:579" - wire width 1 $3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:579" - cell $eq $4 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A \LOGICAL_internal_op - connect \B 7'0110000 - connect \Y $3 - end - process $group_5 - assign \cr_fxm 8'00000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:563" - switch \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:564" - attribute \nmigen.decoding "NONE/0" - case 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:566" - attribute \nmigen.decoding "CR0/1" - case 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:569" - attribute \nmigen.decoding "BF/2" - case 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:572" - attribute \nmigen.decoding "BT/3" - case 3'011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:575" - attribute \nmigen.decoding "WHOLE_REG/4" - case 3'100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:579" - switch { $3 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:579" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:580" - switch { \move_one } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:580" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:583" - switch { \ppick_en_o } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:583" - case 1'1 - assign \cr_fxm \ppick_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:585" - case - assign \cr_fxm 8'00000001 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:587" - case - assign \cr_fxm \LOGICAL_FXM - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:589" - case - assign \cr_fxm 8'11111111 - end - end - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.dec_LOGICAL.dec_ai" -module \dec_ai$159 - attribute \enum_base_type "In1Sel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "RA" - attribute \enum_value_010 "RA_OR_ZERO" - attribute \enum_value_011 "SPR" - attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:148" - wire width 3 input 0 \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:149" - wire width 1 output 1 \immz_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 5 input 2 \LOGICAL_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:156" - wire width 5 \ra - process $group_0 - assign \ra 5'00000 - assign \ra \LOGICAL_RA - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:158" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:158" - cell $eq $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \sel_in - connect \B 3'010 - connect \Y $1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:158" - wire width 1 $3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:158" - cell $eq $4 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \ra - connect \B 5'00000 - connect \Y $3 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:158" - wire width 1 $5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:158" - cell $and $6 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $1 - connect \B $3 - connect \Y $5 - end - process $group_1 - assign \immz_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:158" - switch { $5 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:158" - case 1'1 - assign \immz_out 1'1 - end - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.dec_LOGICAL.dec_bi" -module \dec_bi$160 - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:216" - wire width 4 input 0 \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 output 1 \imm_b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 2 \imm_b_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 16 input 3 \LOGICAL_SI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 16 input 4 \LOGICAL_UI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 5 input 5 \LOGICAL_SH32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 6 input 6 \LOGICAL_sh - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 24 input 7 \LOGICAL_LI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 14 input 8 \LOGICAL_BD - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 14 input 9 \LOGICAL_DS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 64 $1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - cell $pos $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 16 - parameter \Y_WIDTH 64 - connect \A \LOGICAL_UI - connect \Y $1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:229" - wire width 16 \si - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:234" - wire width 32 \si_hi - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:241" - wire width 64 $3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:239" - wire width 16 \ui - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:241" - wire width 47 $4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:241" - cell $sshl $5 - parameter \A_SIGNED 0 - parameter \A_WIDTH 16 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 47 - connect \A \ui - connect \B 5'10000 - connect \Y $4 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:241" - cell $pos $6 - parameter \A_SIGNED 0 - parameter \A_WIDTH 47 - parameter \Y_WIDTH 64 - connect \A $4 - connect \Y $3 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" - wire width 26 \li - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:249" - wire width 16 \bd - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:254" - wire width 16 \ds - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:259" - wire width 64 $7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:259" - cell $not $8 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \Y_WIDTH 64 - connect \A 64'0000000000000000000000000000000000000000000000000000000000000000 - connect \Y $7 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 64 $9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - cell $pos $10 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \Y_WIDTH 64 - connect \A \LOGICAL_sh - connect \Y $9 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 64 $11 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - cell $pos $12 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \Y_WIDTH 64 - connect \A \LOGICAL_SH32 - connect \Y $11 - end - process $group_0 - assign \imm_b 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:224" - switch \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:225" - attribute \nmigen.decoding "CONST_UI/2" - case 4'0010 - assign \imm_b $1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:228" - attribute \nmigen.decoding "CONST_SI/3" - case 4'0011 - assign \imm_b { { \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] } \si } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:233" - attribute \nmigen.decoding "CONST_SI_HI/5" - case 4'0101 - assign \imm_b { { \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] } \si_hi } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:238" - attribute \nmigen.decoding "CONST_UI_HI/4" - case 4'0100 - assign \imm_b $3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:243" - attribute \nmigen.decoding "CONST_LI/6" - case 4'0110 - assign \imm_b { { \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] } \li } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:248" - attribute \nmigen.decoding "CONST_BD/7" - case 4'0111 - assign \imm_b { { \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] } \bd } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:253" - attribute \nmigen.decoding "CONST_DS/8" - case 4'1000 - assign \imm_b { { \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] } \ds } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:258" - attribute \nmigen.decoding "CONST_M1/9" - case 4'1001 - assign \imm_b $7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" - attribute \nmigen.decoding "CONST_SH/10" - case 4'1010 - assign \imm_b $9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:264" - attribute \nmigen.decoding "CONST_SH32/11" - case 4'1011 - assign \imm_b $11 - end - sync init - end - process $group_1 - assign \imm_b_ok 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:224" - switch \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:225" - attribute \nmigen.decoding "CONST_UI/2" - case 4'0010 - assign \imm_b_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:228" - attribute \nmigen.decoding "CONST_SI/3" - case 4'0011 - assign \imm_b_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:233" - attribute \nmigen.decoding "CONST_SI_HI/5" - case 4'0101 - assign \imm_b_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:238" - attribute \nmigen.decoding "CONST_UI_HI/4" - case 4'0100 - assign \imm_b_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:243" - attribute \nmigen.decoding "CONST_LI/6" - case 4'0110 - assign \imm_b_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:248" - attribute \nmigen.decoding "CONST_BD/7" - case 4'0111 - assign \imm_b_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:253" - attribute \nmigen.decoding "CONST_DS/8" - case 4'1000 - assign \imm_b_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:258" - attribute \nmigen.decoding "CONST_M1/9" - case 4'1001 - assign \imm_b_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" - attribute \nmigen.decoding "CONST_SH/10" - case 4'1010 - assign \imm_b_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:264" - attribute \nmigen.decoding "CONST_SH32/11" - case 4'1011 - assign \imm_b_ok 1'1 - end - sync init - end - process $group_2 - assign \si 16'0000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:224" - switch \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:225" - attribute \nmigen.decoding "CONST_UI/2" - case 4'0010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:228" - attribute \nmigen.decoding "CONST_SI/3" - case 4'0011 - assign \si \LOGICAL_SI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:233" - attribute \nmigen.decoding "CONST_SI_HI/5" - case 4'0101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:238" - attribute \nmigen.decoding "CONST_UI_HI/4" - case 4'0100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:243" - attribute \nmigen.decoding "CONST_LI/6" - case 4'0110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:248" - attribute \nmigen.decoding "CONST_BD/7" - case 4'0111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:253" - attribute \nmigen.decoding "CONST_DS/8" - case 4'1000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:258" - attribute \nmigen.decoding "CONST_M1/9" - case 4'1001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" - attribute \nmigen.decoding "CONST_SH/10" - case 4'1010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:264" - attribute \nmigen.decoding "CONST_SH32/11" - case 4'1011 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:235" - wire width 47 $13 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:235" - wire width 47 $14 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:235" - cell $sshl $15 - parameter \A_SIGNED 0 - parameter \A_WIDTH 16 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 47 - connect \A \LOGICAL_SI - connect \B 5'10000 - connect \Y $14 - end - connect $13 $14 - process $group_3 - assign \si_hi 32'00000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:224" - switch \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:225" - attribute \nmigen.decoding "CONST_UI/2" - case 4'0010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:228" - attribute \nmigen.decoding "CONST_SI/3" - case 4'0011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:233" - attribute \nmigen.decoding "CONST_SI_HI/5" - case 4'0101 - assign \si_hi $13 [31:0] - attribute \src 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attribute \enum_value_00000000000 "NONE" - attribute \enum_value_00000000010 "ALU" - attribute \enum_value_00000000100 "LDST" - attribute \enum_value_00000001000 "SHIFT_ROT" - attribute \enum_value_00000010000 "LOGICAL" - attribute \enum_value_00000100000 "BRANCH" - attribute \enum_value_00001000000 "CR" - attribute \enum_value_00010000000 "TRAP" - attribute \enum_value_00100000000 "MUL" - attribute \enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 11 \SPR_function_unit$17 - process $group_20 - assign \SPR_function_unit 11'00000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:315" - switch \opc_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01010 - assign \SPR_function_unit \SPR_function_unit$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 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assign \SPR_internal_op \SPR_internal_op$18 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'11100 - assign \SPR_internal_op \SPR_internal_op$19 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'00000 - assign \SPR_internal_op \SPR_internal_op$20 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'11010 - assign \SPR_internal_op \SPR_internal_op$21 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10011 - assign \SPR_internal_op \SPR_dec_sub19_SPR_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10110 - assign \SPR_internal_op \SPR_internal_op$22 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01001 - assign \SPR_internal_op \SPR_internal_op$23 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01011 - assign \SPR_internal_op \SPR_internal_op$24 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'11011 - assign \SPR_internal_op \SPR_internal_op$25 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01111 - assign \SPR_internal_op \SPR_internal_op$26 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10100 - assign \SPR_internal_op \SPR_internal_op$27 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10101 - assign \SPR_internal_op \SPR_internal_op$28 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10111 - assign \SPR_internal_op \SPR_internal_op$29 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10000 - assign \SPR_internal_op \SPR_internal_op$30 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10010 - assign \SPR_internal_op \SPR_internal_op$31 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01000 - assign \SPR_internal_op \SPR_internal_op$32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'11000 - assign \SPR_internal_op \SPR_internal_op$33 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'00100 - assign \SPR_internal_op \SPR_internal_op$34 - end - sync init - end - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \SPR_cr_in$35 - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \SPR_cr_in$36 - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \SPR_cr_in$37 - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \SPR_cr_in$38 - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \SPR_cr_in$39 - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \SPR_cr_in$40 - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \SPR_cr_in$41 - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \SPR_cr_in$42 - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \SPR_cr_in$43 - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \SPR_cr_in$44 - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \SPR_cr_in$45 - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \SPR_cr_in$46 - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \SPR_cr_in$47 - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \SPR_cr_in$48 - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \SPR_cr_in$49 - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \SPR_cr_in$50 - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \SPR_cr_in$51 - process $group_22 - assign \SPR_cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:315" - switch \opc_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01010 - assign \SPR_cr_in \SPR_cr_in$35 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'11100 - assign \SPR_cr_in \SPR_cr_in$36 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'00000 - assign \SPR_cr_in \SPR_cr_in$37 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'11010 - assign \SPR_cr_in \SPR_cr_in$38 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10011 - assign \SPR_cr_in \SPR_dec_sub19_SPR_cr_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10110 - assign \SPR_cr_in \SPR_cr_in$39 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01001 - assign \SPR_cr_in \SPR_cr_in$40 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01011 - assign \SPR_cr_in \SPR_cr_in$41 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'11011 - assign \SPR_cr_in \SPR_cr_in$42 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01111 - assign \SPR_cr_in \SPR_cr_in$43 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10100 - assign \SPR_cr_in \SPR_cr_in$44 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10101 - assign \SPR_cr_in \SPR_cr_in$45 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10111 - assign \SPR_cr_in \SPR_cr_in$46 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10000 - assign \SPR_cr_in \SPR_cr_in$47 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10010 - assign \SPR_cr_in \SPR_cr_in$48 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01000 - assign \SPR_cr_in \SPR_cr_in$49 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'11000 - assign \SPR_cr_in \SPR_cr_in$50 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'00100 - assign \SPR_cr_in \SPR_cr_in$51 - end - sync init - end - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \SPR_cr_out$52 - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \SPR_cr_out$53 - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \SPR_cr_out$54 - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \SPR_cr_out$55 - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \SPR_cr_out$56 - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \SPR_cr_out$57 - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \SPR_cr_out$58 - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \SPR_cr_out$59 - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \SPR_cr_out$60 - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \SPR_cr_out$61 - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \SPR_cr_out$62 - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \SPR_cr_out$63 - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \SPR_cr_out$64 - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \SPR_cr_out$65 - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \SPR_cr_out$66 - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \SPR_cr_out$67 - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \SPR_cr_out$68 - process $group_23 - assign \SPR_cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:315" - switch \opc_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01010 - assign \SPR_cr_out \SPR_cr_out$52 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'11100 - assign \SPR_cr_out \SPR_cr_out$53 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'00000 - assign \SPR_cr_out \SPR_cr_out$54 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'11010 - assign \SPR_cr_out \SPR_cr_out$55 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10011 - assign \SPR_cr_out \SPR_dec_sub19_SPR_cr_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10110 - assign \SPR_cr_out \SPR_cr_out$56 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01001 - assign \SPR_cr_out \SPR_cr_out$57 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01011 - assign \SPR_cr_out \SPR_cr_out$58 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'11011 - assign \SPR_cr_out \SPR_cr_out$59 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01111 - assign \SPR_cr_out \SPR_cr_out$60 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10100 - assign \SPR_cr_out \SPR_cr_out$61 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10101 - assign \SPR_cr_out \SPR_cr_out$62 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10111 - assign \SPR_cr_out \SPR_cr_out$63 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10000 - assign \SPR_cr_out \SPR_cr_out$64 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10010 - assign \SPR_cr_out \SPR_cr_out$65 - attribute \src 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\SPR_rc_sel \SPR_rc_sel$70 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'00000 - assign \SPR_rc_sel \SPR_rc_sel$71 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'11010 - assign \SPR_rc_sel \SPR_rc_sel$72 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10011 - assign \SPR_rc_sel \SPR_dec_sub19_SPR_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10110 - assign \SPR_rc_sel \SPR_rc_sel$73 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01001 - assign \SPR_rc_sel \SPR_rc_sel$74 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01011 - assign \SPR_rc_sel \SPR_rc_sel$75 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'11011 - assign \SPR_rc_sel \SPR_rc_sel$76 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01111 - assign \SPR_rc_sel \SPR_rc_sel$77 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10100 - assign \SPR_rc_sel \SPR_rc_sel$78 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10101 - assign \SPR_rc_sel \SPR_rc_sel$79 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10111 - assign \SPR_rc_sel \SPR_rc_sel$80 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10000 - assign \SPR_rc_sel \SPR_rc_sel$81 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10010 - assign \SPR_rc_sel \SPR_rc_sel$82 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01000 - assign \SPR_rc_sel \SPR_rc_sel$83 - attribute \src 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attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute 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\enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 7 \SPR_internal_op$7 - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 7 \SPR_internal_op$8 - process $group_7 - assign \SPR_internal_op 7'0000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'010011 - assign \SPR_internal_op \SPR_internal_op$5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'011110 - assign \SPR_internal_op \SPR_internal_op$6 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'011111 - assign \SPR_internal_op \SPR_dec31_SPR_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'111010 - assign \SPR_internal_op \SPR_internal_op$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'111110 - assign \SPR_internal_op \SPR_internal_op$8 - end - sync init - end - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \SPR_cr_in$9 - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \SPR_cr_in$10 - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \SPR_cr_in$11 - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \SPR_cr_in$12 - process $group_8 - assign \SPR_cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'010011 - assign \SPR_cr_in \SPR_cr_in$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'011110 - assign \SPR_cr_in \SPR_cr_in$10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'011111 - assign \SPR_cr_in \SPR_dec31_SPR_cr_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'111010 - assign \SPR_cr_in \SPR_cr_in$11 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'111110 - assign \SPR_cr_in \SPR_cr_in$12 - end - sync init - end - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \SPR_cr_out$13 - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \SPR_cr_out$14 - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \SPR_cr_out$15 - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \SPR_cr_out$16 - process $group_9 - assign \SPR_cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'010011 - assign \SPR_cr_out \SPR_cr_out$13 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'011110 - assign \SPR_cr_out \SPR_cr_out$14 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'011111 - assign \SPR_cr_out \SPR_dec31_SPR_cr_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'111010 - assign \SPR_cr_out \SPR_cr_out$15 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'111110 - assign \SPR_cr_out \SPR_cr_out$16 - end - sync init - end - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 2 \SPR_rc_sel$17 - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 2 \SPR_rc_sel$18 - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 2 \SPR_rc_sel$19 - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 2 \SPR_rc_sel$20 - process $group_10 - assign \SPR_rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'010011 - assign \SPR_rc_sel \SPR_rc_sel$17 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'011110 - assign \SPR_rc_sel \SPR_rc_sel$18 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'011111 - assign \SPR_rc_sel \SPR_dec31_SPR_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'111010 - assign \SPR_rc_sel \SPR_rc_sel$19 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'111110 - assign \SPR_rc_sel \SPR_rc_sel$20 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \SPR_is_32b$21 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \SPR_is_32b$22 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \SPR_is_32b$23 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \SPR_is_32b$24 - process $group_11 - assign \SPR_is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'010011 - assign \SPR_is_32b \SPR_is_32b$21 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'011110 - assign \SPR_is_32b \SPR_is_32b$22 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'011111 - assign \SPR_is_32b \SPR_dec31_SPR_is_32b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'111010 - assign \SPR_is_32b \SPR_is_32b$23 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'111110 - assign \SPR_is_32b \SPR_is_32b$24 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:308" - wire width 32 \opcode_switch$25 - process $group_12 - assign \opcode_switch$25 32'00000000000000000000000000000000 - assign \opcode_switch$25 \opcode_in - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:418" - wire width 32 $26 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:418" - cell $mux $27 - parameter \WIDTH 32 - connect \A \raw_opcode_in - connect \B { \raw_opcode_in [7:0] \raw_opcode_in [15:8] \raw_opcode_in [23:16] \raw_opcode_in [31:24] } - connect \S \bigendian - connect \Y $26 - end - process $group_13 - assign \opcode_in 32'00000000000000000000000000000000 - assign \opcode_in $26 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 5 \SPR_RS - process $group_14 - assign \SPR_RS 5'00000 - assign \SPR_RS { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 5 \SPR_RT - process $group_15 - assign \SPR_RT 5'00000 - assign \SPR_RT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 5 \SPR_RA - process $group_16 - assign \SPR_RA 5'00000 - assign \SPR_RA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 5 \SPR_RB - process $group_17 - assign \SPR_RB 5'00000 - assign \SPR_RB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 16 \SPR_SI - process $group_18 - assign \SPR_SI 16'0000000000000000 - assign \SPR_SI { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] \opcode_in [0] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 16 \SPR_UI - process $group_19 - assign \SPR_UI 16'0000000000000000 - assign \SPR_UI { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] \opcode_in [0] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 1 \SPR_L - process $group_20 - assign \SPR_L 1'0 - assign \SPR_L { \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 5 \SPR_SH32 - process $group_21 - assign \SPR_SH32 5'00000 - assign \SPR_SH32 { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 6 \SPR_sh - process $group_22 - assign \SPR_sh 6'000000 - assign \SPR_sh { \opcode_in [1] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 5 \SPR_MB32 - process $group_23 - assign \SPR_MB32 5'00000 - assign \SPR_MB32 { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 5 \SPR_ME32 - process $group_24 - assign \SPR_ME32 5'00000 - assign \SPR_ME32 { \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 24 \SPR_LI - process $group_25 - assign \SPR_LI 24'000000000000000000000000 - assign \SPR_LI { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 1 \SPR_LK - process $group_26 - assign \SPR_LK 1'0 - assign \SPR_LK { \opcode_in [0] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 1 \SPR_AA - process $group_27 - assign \SPR_AA 1'0 - assign \SPR_AA { \opcode_in [1] } - sync init - end - process $group_28 - assign \SPR_Rc 1'0 - assign \SPR_Rc { \opcode_in [0] } - sync init - end - process $group_29 - assign \SPR_OE 1'0 - assign \SPR_OE { \opcode_in [10] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 14 \SPR_BD - process $group_30 - assign \SPR_BD 14'00000000000000 - assign \SPR_BD { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 3 \SPR_BF - process $group_31 - assign \SPR_BF 3'000 - assign \SPR_BF { \opcode_in [25] \opcode_in [24] \opcode_in [23] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 10 \SPR_CR - process $group_32 - assign \SPR_CR 10'0000000000 - assign \SPR_CR { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] } - sync init - end - process $group_33 - assign \SPR_BB 5'00000 - assign \SPR_BB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - process $group_34 - assign \SPR_BA 5'00000 - assign \SPR_BA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - process $group_35 - assign \SPR_BT 5'00000 - assign \SPR_BT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - process $group_36 - assign \SPR_FXM 8'00000000 - assign \SPR_FXM { \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 5 \SPR_BO - process $group_37 - assign \SPR_BO 5'00000 - assign \SPR_BO { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - process $group_38 - assign \SPR_BI 5'00000 - assign \SPR_BI { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 2 \SPR_BH - process $group_39 - assign \SPR_BH 2'00 - assign \SPR_BH { \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 16 \SPR_D - process $group_40 - assign \SPR_D 16'0000000000000000 - assign \SPR_D { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] \opcode_in [0] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 14 \SPR_DS - process $group_41 - assign \SPR_DS 14'00000000000000 - assign \SPR_DS { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 5 \SPR_TO - process $group_42 - assign \SPR_TO 5'00000 - assign \SPR_TO { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - process $group_43 - assign \SPR_BC 5'00000 - assign \SPR_BC { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 5 \SPR_SH - process $group_44 - assign \SPR_SH 5'00000 - assign \SPR_SH { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 5 \SPR_ME - process $group_45 - assign \SPR_ME 5'00000 - assign \SPR_ME { \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 5 \SPR_MB - process $group_46 - assign \SPR_MB 5'00000 - assign \SPR_MB { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 10 \SPR_SPR - process $group_47 - assign \SPR_SPR 10'0000000000 - assign \SPR_SPR { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \X_A - process $group_48 - assign \X_A 1'0 - assign \X_A { \opcode_in [25] } - sync init - end - process $group_49 - assign \X_BF 3'000 - assign \X_BF { \opcode_in [25] \opcode_in [24] \opcode_in [23] } - sync init - end - process $group_50 - assign \X_BFA 3'000 - assign \X_BFA { \opcode_in [20] \opcode_in [19] \opcode_in [18] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \X_BO - process $group_51 - assign \X_BO 5'00000 - assign \X_BO { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 4 \X_CT - process $group_52 - assign \X_CT 4'0000 - assign \X_CT { \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 7 \X_DCMX - process $group_53 - assign \X_DCMX 7'0000000 - assign \X_DCMX { \opcode_in [22] \opcode_in [21] \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 3 \X_DRM - process $group_54 - assign \X_DRM 3'000 - assign \X_DRM { \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \X_E - process $group_55 - assign \X_E 1'0 - assign \X_E { \opcode_in [15] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 4 \X_E_1 - process $group_56 - assign \X_E_1 4'0000 - assign \X_E_1 { \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 2 \X_EO - process $group_57 - assign \X_EO 2'00 - assign \X_EO { \opcode_in [20] \opcode_in [19] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \X_EO_1 - process $group_58 - assign \X_EO_1 5'00000 - assign \X_EO_1 { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \X_EX - process $group_59 - assign \X_EX 1'0 - assign \X_EX { \opcode_in [0] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \X_FC - process $group_60 - assign \X_FC 5'00000 - assign \X_FC { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \X_FRA - process $group_61 - assign \X_FRA 5'00000 - assign \X_FRA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \X_FRAp - process $group_62 - assign \X_FRAp 5'00000 - assign \X_FRAp { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \X_FRB - process $group_63 - assign \X_FRB 5'00000 - assign \X_FRB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \X_FRBp - process $group_64 - assign \X_FRBp 5'00000 - assign \X_FRBp { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \X_FRS - process $group_65 - assign \X_FRS 5'00000 - assign \X_FRS { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \X_FRSp - process $group_66 - assign \X_FRSp 5'00000 - assign \X_FRSp { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \X_FRT - process $group_67 - assign \X_FRT 5'00000 - assign \X_FRT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \X_FRTp - process $group_68 - assign \X_FRTp 5'00000 - assign \X_FRTp { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 3 \X_IH - process $group_69 - assign \X_IH 3'000 - assign \X_IH { \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 8 \X_IMM8 - process $group_70 - assign \X_IMM8 8'00000000 - assign \X_IMM8 { \opcode_in [18] \opcode_in [17] \opcode_in [16] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 2 \X_L2 - process $group_71 - assign \X_L2 2'00 - assign \X_L2 { \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \X_L - process $group_72 - assign \X_L 1'0 - assign \X_L { \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \X_L1 - process $group_73 - assign \X_L1 1'0 - assign \X_L1 { \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 2 \X_L3 - process $group_74 - assign \X_L3 2'00 - assign \X_L3 { \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \X_MO - process $group_75 - assign \X_MO 5'00000 - assign \X_MO { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \X_NB - process $group_76 - assign \X_NB 5'00000 - assign \X_NB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \X_PRS - process $group_77 - assign \X_PRS 1'0 - assign \X_PRS { \opcode_in [17] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \X_R - process $group_78 - assign \X_R 1'0 - assign \X_R { \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \X_R_1 - process $group_79 - assign \X_R_1 1'0 - assign \X_R_1 { \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \X_RA - process $group_80 - assign \X_RA 5'00000 - assign \X_RA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \X_RB - process $group_81 - assign \X_RB 5'00000 - assign \X_RB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \X_Rc - process $group_82 - assign \X_Rc 1'0 - assign \X_Rc { \opcode_in [0] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 2 \X_RIC - process $group_83 - assign \X_RIC 2'00 - assign \X_RIC { \opcode_in [19] \opcode_in [18] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 2 \X_RM - process $group_84 - assign \X_RM 2'00 - assign \X_RM { \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \X_RO - process $group_85 - assign \X_RO 1'0 - assign \X_RO { \opcode_in [0] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \X_RS - process $group_86 - assign \X_RS 5'00000 - assign \X_RS { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \X_RSp - process $group_87 - assign \X_RSp 5'00000 - assign \X_RSp { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \X_RT - process $group_88 - assign \X_RT 5'00000 - assign \X_RT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \X_RTp - process $group_89 - assign \X_RTp 5'00000 - assign \X_RTp { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \X_S - process $group_90 - assign \X_S 5'00000 - assign \X_S { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \X_SH - process $group_91 - assign \X_SH 5'00000 - assign \X_SH { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \X_SI - process $group_92 - assign \X_SI 5'00000 - assign \X_SI { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 2 \X_SP - process $group_93 - assign \X_SP 2'00 - assign \X_SP { \opcode_in [20] \opcode_in [19] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 4 \X_SR - process $group_94 - assign \X_SR 4'0000 - assign \X_SR { \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \X_SX - process $group_95 - assign \X_SX 1'0 - assign \X_SX { \opcode_in [0] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 6 \X_SX_S - process $group_96 - assign \X_SX_S 6'000000 - assign \X_SX_S { \opcode_in [0] \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \X_T - process $group_97 - assign \X_T 5'00000 - assign \X_T { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 10 \X_TBR - process $group_98 - assign \X_TBR 10'0000000000 - assign \X_TBR { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \X_TH - process $group_99 - assign \X_TH 5'00000 - assign \X_TH { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \X_TO - process $group_100 - assign \X_TO 5'00000 - assign \X_TO { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \X_TX - process $group_101 - assign \X_TX 1'0 - assign \X_TX { \opcode_in [0] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 6 \X_TX_T - process $group_102 - assign \X_TX_T 6'000000 - assign \X_TX_T { \opcode_in [0] \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 4 \X_U - process $group_103 - assign \X_U 4'0000 - assign \X_U { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \X_UIM - process $group_104 - assign \X_UIM 5'00000 - assign \X_UIM { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \X_VRS - process $group_105 - assign \X_VRS 5'00000 - assign \X_VRS { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \X_VRT - process $group_106 - assign \X_VRT 5'00000 - assign \X_VRT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \X_W - process $group_107 - assign \X_W 1'0 - assign \X_W { \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 2 \X_WC - process $group_108 - assign \X_WC 2'00 - assign \X_WC { \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 10 \X_XO - process $group_109 - assign \X_XO 10'0000000000 - assign \X_XO { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 8 \X_XO_1 - process $group_110 - assign \X_XO_1 8'00000000 - assign \X_XO_1 { \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \B_AA - process $group_111 - assign \B_AA 1'0 - assign \B_AA { \opcode_in [1] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 14 \B_BD - process $group_112 - assign \B_BD 14'00000000000000 - assign \B_BD { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \B_BI - process $group_113 - assign \B_BI 5'00000 - assign \B_BI { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \B_BO - process $group_114 - assign \B_BO 5'00000 - assign \B_BO { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \B_LK - process $group_115 - assign \B_LK 1'0 - assign \B_LK { \opcode_in [0] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \I_AA - process $group_116 - assign \I_AA 1'0 - assign \I_AA { \opcode_in [1] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 24 \I_LI - process $group_117 - assign \I_LI 24'000000000000000000000000 - assign \I_LI { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \I_LK - process $group_118 - assign \I_LK 1'0 - assign \I_LK { \opcode_in [0] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \XX3_AX - process $group_119 - assign \XX3_AX 1'0 - assign \XX3_AX { \opcode_in [2] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \XX3_A - process $group_120 - assign \XX3_A 5'00000 - assign \XX3_A { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 6 \XX3_AX_A - process $group_121 - assign \XX3_AX_A 6'000000 - assign \XX3_AX_A { \opcode_in [2] \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 3 \XX3_BF - process $group_122 - assign \XX3_BF 3'000 - assign \XX3_BF { \opcode_in [25] \opcode_in [24] \opcode_in [23] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \XX3_BX - process $group_123 - assign \XX3_BX 1'0 - assign \XX3_BX { \opcode_in [1] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \XX3_B - process $group_124 - assign \XX3_B 5'00000 - assign \XX3_B { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 6 \XX3_BX_B - process $group_125 - assign \XX3_BX_B 6'000000 - assign \XX3_BX_B { \opcode_in [1] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 2 \XX3_DM - process $group_126 - assign \XX3_DM 2'00 - assign \XX3_DM { \opcode_in [9] \opcode_in [8] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \XX3_Rc - process $group_127 - assign \XX3_Rc 1'0 - assign \XX3_Rc { \opcode_in [10] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 2 \XX3_SHW - process $group_128 - assign \XX3_SHW 2'00 - assign \XX3_SHW { \opcode_in [9] \opcode_in [8] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \XX3_TX - process $group_129 - assign \XX3_TX 1'0 - assign \XX3_TX { \opcode_in [0] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \XX3_T - process $group_130 - assign \XX3_T 5'00000 - assign \XX3_T { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 6 \XX3_TX_T - process $group_131 - assign \XX3_TX_T 6'000000 - assign \XX3_TX_T { \opcode_in [0] \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 4 \XX3_XO - process $group_132 - assign \XX3_XO 4'0000 - assign \XX3_XO { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 8 \XX3_XO_1 - process $group_133 - assign \XX3_XO_1 8'00000000 - assign \XX3_XO_1 { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 9 \XX3_XO_2 - process $group_134 - assign \XX3_XO_2 9'000000000 - assign \XX3_XO_2 { \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \XX4_AX - process $group_135 - assign \XX4_AX 1'0 - assign \XX4_AX { \opcode_in [2] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \XX4_A - process $group_136 - assign \XX4_A 5'00000 - assign \XX4_A { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 6 \XX4_AX_A - process $group_137 - assign \XX4_AX_A 6'000000 - assign \XX4_AX_A { \opcode_in [2] \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \XX4_BX - process $group_138 - assign \XX4_BX 1'0 - assign \XX4_BX { \opcode_in [1] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \XX4_B - process $group_139 - assign \XX4_B 5'00000 - assign \XX4_B { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 6 \XX4_BX_B - process $group_140 - assign \XX4_BX_B 6'000000 - assign \XX4_BX_B { \opcode_in [1] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \XX4_CX - process $group_141 - assign \XX4_CX 1'0 - assign \XX4_CX { \opcode_in [3] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \XX4_C - process $group_142 - assign \XX4_C 5'00000 - assign \XX4_C { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 6 \XX4_CX_C - process $group_143 - assign \XX4_CX_C 6'000000 - assign \XX4_CX_C { \opcode_in [3] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \XX4_TX - process $group_144 - assign \XX4_TX 1'0 - assign \XX4_TX { \opcode_in [0] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \XX4_T - process $group_145 - assign \XX4_T 5'00000 - assign \XX4_T { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 6 \XX4_TX_T - process $group_146 - assign \XX4_TX_T 6'000000 - assign \XX4_TX_T { \opcode_in [0] \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 2 \XX4_XO - process $group_147 - assign \XX4_XO 2'00 - assign \XX4_XO { \opcode_in [5] \opcode_in [4] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \XL_BA - process $group_148 - assign \XL_BA 5'00000 - assign \XL_BA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \XL_BB - process $group_149 - assign \XL_BB 5'00000 - assign \XL_BB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 3 \XL_BF - process $group_150 - assign \XL_BF 3'000 - assign \XL_BF { \opcode_in [25] \opcode_in [24] \opcode_in [23] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 3 \XL_BFA - process $group_151 - assign \XL_BFA 3'000 - assign \XL_BFA { \opcode_in [20] \opcode_in [19] \opcode_in [18] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 2 \XL_BH - process $group_152 - assign \XL_BH 2'00 - assign \XL_BH { \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \XL_BI - process $group_153 - assign \XL_BI 5'00000 - assign \XL_BI { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \XL_BO - process $group_154 - assign \XL_BO 5'00000 - assign \XL_BO { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \XL_BO_1 - process $group_155 - assign \XL_BO_1 5'00000 - assign \XL_BO_1 { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - process $group_156 - assign \XL_BT 5'00000 - assign \XL_BT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \XL_LK - process $group_157 - assign \XL_LK 1'0 - assign \XL_LK { \opcode_in [0] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 15 \XL_OC - process $group_158 - assign \XL_OC 15'000000000000000 - assign \XL_OC { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \XL_S - process $group_159 - assign \XL_S 1'0 - assign \XL_S { \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 10 \XL_XO - process $group_160 - assign \XL_XO 10'0000000000 - assign \XL_XO { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \A_BC - process $group_161 - assign \A_BC 5'00000 - assign \A_BC { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \A_FRA - process $group_162 - assign \A_FRA 5'00000 - assign \A_FRA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \A_FRB - process $group_163 - assign \A_FRB 5'00000 - assign \A_FRB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \A_FRC - process $group_164 - assign \A_FRC 5'00000 - assign \A_FRC { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \A_FRT - process $group_165 - assign \A_FRT 5'00000 - assign \A_FRT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \A_RA - process $group_166 - assign \A_RA 5'00000 - assign \A_RA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \A_RB - process $group_167 - assign \A_RB 5'00000 - assign \A_RB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \A_Rc - process $group_168 - assign \A_Rc 1'0 - assign \A_Rc { \opcode_in [0] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \A_RT - process $group_169 - assign \A_RT 5'00000 - assign \A_RT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \A_XO - process $group_170 - assign \A_XO 5'00000 - assign \A_XO { \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 3 \D_BF - process $group_171 - assign \D_BF 3'000 - assign \D_BF { \opcode_in [25] \opcode_in [24] \opcode_in [23] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 16 \D_D - process $group_172 - assign \D_D 16'0000000000000000 - assign \D_D { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] \opcode_in [0] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \D_FRS - process $group_173 - assign \D_FRS 5'00000 - assign \D_FRS { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \D_FRT - process $group_174 - assign \D_FRT 5'00000 - assign \D_FRT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \D_L - process $group_175 - assign \D_L 1'0 - assign \D_L { \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \D_RA - process $group_176 - assign \D_RA 5'00000 - assign \D_RA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \D_RS - process $group_177 - assign \D_RS 5'00000 - assign \D_RS { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \D_RT - process $group_178 - assign \D_RT 5'00000 - assign \D_RT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 16 \D_SI - process $group_179 - assign \D_SI 16'0000000000000000 - assign \D_SI { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] \opcode_in [0] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \D_TO - process $group_180 - assign \D_TO 5'00000 - assign \D_TO { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 16 \D_UI - process $group_181 - assign \D_UI 16'0000000000000000 - assign \D_UI { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] \opcode_in [0] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 3 \XX2_BF - process $group_182 - assign \XX2_BF 3'000 - assign \XX2_BF { \opcode_in [25] \opcode_in [24] \opcode_in [23] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \XX2_BX - process $group_183 - assign \XX2_BX 1'0 - assign \XX2_BX { \opcode_in [1] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \XX2_B - process $group_184 - assign \XX2_B 5'00000 - assign \XX2_B { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 6 \XX2_BX_B - process $group_185 - assign \XX2_BX_B 6'000000 - assign \XX2_BX_B { \opcode_in [1] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \XX2_dc - process $group_186 - assign \XX2_dc 1'0 - assign \XX2_dc { \opcode_in [6] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \XX2_dm - process $group_187 - assign \XX2_dm 1'0 - assign \XX2_dm { \opcode_in [2] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \XX2_dx - process $group_188 - assign \XX2_dx 5'00000 - assign \XX2_dx { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 7 \XX2_dc_dm_dx - process $group_189 - assign \XX2_dc_dm_dx 7'0000000 - assign \XX2_dc_dm_dx { \opcode_in [6] \opcode_in [2] \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 7 \XX2_DCMX - process $group_190 - assign \XX2_DCMX 7'0000000 - assign \XX2_DCMX { \opcode_in [22] \opcode_in [21] \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \XX2_EO - process $group_191 - assign \XX2_EO 5'00000 - assign \XX2_EO { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \XX2_RT - process $group_192 - assign \XX2_RT 5'00000 - assign \XX2_RT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \XX2_TX - process $group_193 - assign \XX2_TX 1'0 - assign \XX2_TX { \opcode_in [0] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \XX2_T - process $group_194 - assign \XX2_T 5'00000 - assign \XX2_T { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 6 \XX2_TX_T - process $group_195 - assign \XX2_TX_T 6'000000 - assign \XX2_TX_T { \opcode_in [0] \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 4 \XX2_UIM - process $group_196 - assign \XX2_UIM 4'0000 - assign \XX2_UIM { \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 2 \XX2_UIM_1 - process $group_197 - assign \XX2_UIM_1 2'00 - assign \XX2_UIM_1 { \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 7 \XX2_XO - process $group_198 - assign \XX2_XO 7'0000000 - assign \XX2_XO { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [5] \opcode_in [4] \opcode_in [3] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 9 \XX2_XO_1 - process $group_199 - assign \XX2_XO_1 9'000000000 - assign \XX2_XO_1 { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 3 \Z22_BF - process $group_200 - assign \Z22_BF 3'000 - assign \Z22_BF { \opcode_in [25] \opcode_in [24] \opcode_in [23] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 6 \Z22_DCM - process $group_201 - assign \Z22_DCM 6'000000 - assign \Z22_DCM { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 6 \Z22_DGM - process $group_202 - assign \Z22_DGM 6'000000 - assign \Z22_DGM { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \Z22_FRA - process $group_203 - assign \Z22_FRA 5'00000 - assign \Z22_FRA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \Z22_FRAp - process $group_204 - assign \Z22_FRAp 5'00000 - assign \Z22_FRAp { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \Z22_FRT - process $group_205 - assign \Z22_FRT 5'00000 - assign \Z22_FRT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \Z22_FRTp - process $group_206 - assign \Z22_FRTp 5'00000 - assign \Z22_FRTp { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \Z22_Rc - process $group_207 - assign \Z22_Rc 1'0 - assign \Z22_Rc { \opcode_in [0] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 6 \Z22_SH - process $group_208 - assign \Z22_SH 6'000000 - assign \Z22_SH { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 9 \Z22_XO - process $group_209 - assign \Z22_XO 9'000000000 - assign \Z22_XO { \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 3 \EVS_BFA - process $group_210 - assign \EVS_BFA 3'000 - assign \EVS_BFA { \opcode_in [2] \opcode_in [1] \opcode_in [0] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 10 \XFX_BHRBE - process $group_211 - assign \XFX_BHRBE 10'0000000000 - assign \XFX_BHRBE { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \XFX_DUI - process $group_212 - assign \XFX_DUI 5'00000 - assign \XFX_DUI { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 10 \XFX_DUIS - process $group_213 - assign \XFX_DUIS 10'0000000000 - assign \XFX_DUIS { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 8 \XFX_FXM - process $group_214 - assign \XFX_FXM 8'00000000 - assign \XFX_FXM { \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \XFX_RS - process $group_215 - assign \XFX_RS 5'00000 - assign \XFX_RS { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \XFX_RT - process $group_216 - assign \XFX_RT 5'00000 - assign \XFX_RT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 10 \XFX_SPR - process $group_217 - assign \XFX_SPR 10'0000000000 - assign \XFX_SPR { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 10 \XFX_XO - process $group_218 - assign \XFX_XO 10'0000000000 - assign \XFX_XO { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 10 \DX_d0 - process $group_219 - assign \DX_d0 10'0000000000 - assign \DX_d0 { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \DX_d1 - process $group_220 - assign \DX_d1 5'00000 - assign \DX_d1 { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \DX_d2 - process $group_221 - assign \DX_d2 1'0 - assign \DX_d2 { \opcode_in [0] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 16 \DX_d0_d1_d2 - process $group_222 - assign \DX_d0_d1_d2 16'0000000000000000 - assign \DX_d0_d1_d2 { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] \opcode_in [0] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \DX_RT - process $group_223 - assign \DX_RT 5'00000 - assign \DX_RT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \DX_XO - process $group_224 - assign \DX_XO 5'00000 - assign \DX_XO { \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 12 \DQ_DQ - process $group_225 - assign \DQ_DQ 12'000000000000 - assign \DQ_DQ { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 4 \DQ_PT - process $group_226 - assign \DQ_PT 4'0000 - assign \DQ_PT { \opcode_in [3] \opcode_in [2] \opcode_in [1] \opcode_in [0] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \DQ_RA - process $group_227 - assign \DQ_RA 5'00000 - assign \DQ_RA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \DQ_RTp - process $group_228 - assign \DQ_RTp 5'00000 - assign \DQ_RTp { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \DQ_SX - process $group_229 - assign \DQ_SX 1'0 - assign \DQ_SX { \opcode_in [3] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \DQ_S - process $group_230 - assign \DQ_S 5'00000 - assign \DQ_S { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 6 \DQ_SX_S - process $group_231 - assign \DQ_SX_S 6'000000 - assign \DQ_SX_S { \opcode_in [3] \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \DQ_TX - process $group_232 - assign \DQ_TX 1'0 - assign \DQ_TX { \opcode_in [3] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \DQ_T - process $group_233 - assign \DQ_T 5'00000 - assign \DQ_T { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 6 \DQ_TX_T - process $group_234 - assign \DQ_TX_T 6'000000 - assign \DQ_TX_T { \opcode_in [3] \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 3 \DQ_XO - process $group_235 - assign \DQ_XO 3'000 - assign \DQ_XO { \opcode_in [2] \opcode_in [1] \opcode_in [0] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 14 \DS_DS - process $group_236 - assign \DS_DS 14'00000000000000 - assign \DS_DS { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \DS_FRSp - process $group_237 - assign \DS_FRSp 5'00000 - assign \DS_FRSp { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \DS_FRTp - process $group_238 - assign \DS_FRTp 5'00000 - assign \DS_FRTp { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \DS_RA - process $group_239 - assign \DS_RA 5'00000 - assign \DS_RA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \DS_RS - process $group_240 - assign \DS_RS 5'00000 - assign \DS_RS { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \DS_RSp - process $group_241 - assign \DS_RSp 5'00000 - assign \DS_RSp { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \DS_RT - process $group_242 - assign \DS_RT 5'00000 - assign \DS_RT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \DS_VRS - process $group_243 - assign \DS_VRS 5'00000 - assign \DS_VRS { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \DS_VRT - process $group_244 - assign \DS_VRT 5'00000 - assign \DS_VRT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 2 \DS_XO - process $group_245 - assign \DS_XO 2'00 - assign \DS_XO { \opcode_in [1] \opcode_in [0] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \VX_EO - process $group_246 - assign \VX_EO 5'00000 - assign \VX_EO { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \VX_PS - process $group_247 - assign \VX_PS 1'0 - assign \VX_PS { \opcode_in [9] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \VX_RA - process $group_248 - assign \VX_RA 5'00000 - assign \VX_RA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \VX_RT - process $group_249 - assign \VX_RT 5'00000 - assign \VX_RT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \VX_SIM - process $group_250 - assign \VX_SIM 5'00000 - assign \VX_SIM { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \VX_UIM - process $group_251 - assign \VX_UIM 5'00000 - assign \VX_UIM { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 4 \VX_UIM_1 - process $group_252 - assign \VX_UIM_1 4'0000 - assign \VX_UIM_1 { \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 3 \VX_UIM_2 - process $group_253 - assign \VX_UIM_2 3'000 - assign \VX_UIM_2 { \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 2 \VX_UIM_3 - process $group_254 - assign \VX_UIM_3 2'00 - assign \VX_UIM_3 { \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \VX_VRA - process $group_255 - assign \VX_VRA 5'00000 - assign \VX_VRA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \VX_VRB - process $group_256 - assign \VX_VRB 5'00000 - assign \VX_VRB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \VX_VRT - process $group_257 - assign \VX_VRT 5'00000 - assign \VX_VRT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 10 \VX_XO - process $group_258 - assign \VX_XO 10'0000000000 - assign \VX_XO { \opcode_in [10] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] \opcode_in [0] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 11 \VX_XO_1 - process $group_259 - assign \VX_XO_1 11'00000000000 - assign \VX_XO_1 { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] \opcode_in [0] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 8 \XFL_FLM - process $group_260 - assign \XFL_FLM 8'00000000 - assign \XFL_FLM { \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \XFL_FRB - process $group_261 - assign \XFL_FRB 5'00000 - assign \XFL_FRB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \XFL_L - process $group_262 - assign \XFL_L 1'0 - assign \XFL_L { \opcode_in [25] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \XFL_Rc - process $group_263 - assign \XFL_Rc 1'0 - assign \XFL_Rc { \opcode_in [0] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \XFL_W - process $group_264 - assign \XFL_W 1'0 - assign \XFL_W { \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 10 \XFL_XO - process $group_265 - assign \XFL_XO 10'0000000000 - assign \XFL_XO { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \Z23_FRA - process $group_266 - assign \Z23_FRA 5'00000 - assign \Z23_FRA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \Z23_FRAp - process $group_267 - assign \Z23_FRAp 5'00000 - assign \Z23_FRAp { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \Z23_FRB - process $group_268 - assign \Z23_FRB 5'00000 - assign \Z23_FRB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \Z23_FRBp - process $group_269 - assign \Z23_FRBp 5'00000 - assign \Z23_FRBp { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \Z23_FRT - process $group_270 - assign \Z23_FRT 5'00000 - assign \Z23_FRT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \Z23_FRTp - process $group_271 - assign \Z23_FRTp 5'00000 - assign \Z23_FRTp { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \Z23_R - process $group_272 - assign \Z23_R 1'0 - assign \Z23_R { \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \Z23_Rc - process $group_273 - assign \Z23_Rc 1'0 - assign \Z23_Rc { \opcode_in [0] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 2 \Z23_RMC - process $group_274 - assign \Z23_RMC 2'00 - assign \Z23_RMC { \opcode_in [10] \opcode_in [9] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \Z23_TE - process $group_275 - assign \Z23_TE 5'00000 - assign \Z23_TE { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 8 \Z23_XO - process $group_276 - assign \Z23_XO 8'00000000 - assign \Z23_XO { \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \MDS_IB - process $group_277 - assign \MDS_IB 5'00000 - assign \MDS_IB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \MDS_IS - process $group_278 - assign \MDS_IS 5'00000 - assign \MDS_IS { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 6 \MDS_mb - process $group_279 - assign \MDS_mb 6'000000 - assign \MDS_mb { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 6 \MDS_me - process $group_280 - assign \MDS_me 6'000000 - assign \MDS_me { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \MDS_RA - process $group_281 - assign \MDS_RA 5'00000 - assign \MDS_RA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \MDS_RB - process $group_282 - assign \MDS_RB 5'00000 - assign \MDS_RB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \MDS_Rc - process $group_283 - assign \MDS_Rc 1'0 - assign \MDS_Rc { \opcode_in [0] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \MDS_RS - process $group_284 - assign \MDS_RS 5'00000 - assign \MDS_RS { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 4 \MDS_XBI - process $group_285 - assign \MDS_XBI 4'0000 - assign \MDS_XBI { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 4 \MDS_XBI_1 - process $group_286 - assign \MDS_XBI_1 4'0000 - assign \MDS_XBI_1 { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 4 \MDS_XO - process $group_287 - assign \MDS_XO 4'0000 - assign \MDS_XO { \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 7 \SC_LEV - process $group_288 - assign \SC_LEV 7'0000000 - assign \SC_LEV { \opcode_in [11] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \SC_XO - process $group_289 - assign \SC_XO 1'0 - assign \SC_XO { \opcode_in [1] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 2 \SC_XO_1 - process $group_290 - assign \SC_XO_1 2'00 - assign \SC_XO_1 { \opcode_in [1] \opcode_in [0] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \M_MB - process $group_291 - assign \M_MB 5'00000 - assign \M_MB { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \M_ME - process $group_292 - assign \M_ME 5'00000 - assign \M_ME { \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \M_RA - process $group_293 - assign \M_RA 5'00000 - assign \M_RA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \M_RB - process $group_294 - assign \M_RB 5'00000 - assign \M_RB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \M_Rc - process $group_295 - assign \M_Rc 1'0 - assign \M_Rc { \opcode_in [0] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \M_RS - process $group_296 - assign \M_RS 5'00000 - assign \M_RS { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \M_SH - process $group_297 - assign \M_SH 5'00000 - assign \M_SH { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 6 \MD_mb - process $group_298 - assign \MD_mb 6'000000 - assign \MD_mb { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 6 \MD_me - process $group_299 - assign \MD_me 6'000000 - assign \MD_me { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \MD_RA - process $group_300 - assign \MD_RA 5'00000 - assign \MD_RA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \MD_Rc - process $group_301 - assign \MD_Rc 1'0 - assign \MD_Rc { \opcode_in [0] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \MD_RS - process $group_302 - assign \MD_RS 5'00000 - assign \MD_RS { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 6 \MD_sh - process $group_303 - assign \MD_sh 6'000000 - assign \MD_sh { \opcode_in [1] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 3 \MD_XO - process $group_304 - assign \MD_XO 3'000 - assign \MD_XO { \opcode_in [4] \opcode_in [3] \opcode_in [2] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 6 \all_OPCD - process $group_305 - assign \all_OPCD 6'000000 - assign \all_OPCD { \opcode_in [31] \opcode_in [30] \opcode_in [29] \opcode_in [28] \opcode_in [27] \opcode_in [26] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 6 \all_PO - process $group_306 - assign \all_PO 6'000000 - assign \all_PO { \opcode_in [31] \opcode_in [30] \opcode_in [29] \opcode_in [28] \opcode_in [27] \opcode_in [26] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \XO_OE - process $group_307 - assign \XO_OE 1'0 - assign \XO_OE { \opcode_in [10] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \XO_RA - process $group_308 - assign \XO_RA 5'00000 - assign \XO_RA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \XO_RB - process $group_309 - assign \XO_RB 5'00000 - assign \XO_RB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \XO_Rc - process $group_310 - assign \XO_Rc 1'0 - assign \XO_Rc { \opcode_in [0] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \XO_RT - process $group_311 - assign \XO_RT 5'00000 - assign \XO_RT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 9 \XO_XO - process $group_312 - assign \XO_XO 9'000000000 - assign \XO_XO { \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \DQE_RA - process $group_313 - assign \DQE_RA 5'00000 - assign \DQE_RA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \DQE_RT - process $group_314 - assign \DQE_RT 5'00000 - assign \DQE_RT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 2 \DQE_XO - process $group_315 - assign \DQE_XO 2'00 - assign \DQE_XO { \opcode_in [1] \opcode_in [0] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \TX_RA - process $group_316 - assign \TX_RA 5'00000 - assign \TX_RA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \TX_UI - process $group_317 - assign \TX_UI 5'00000 - assign \TX_UI { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 4 \TX_XBI - process $group_318 - assign \TX_XBI 4'0000 - assign \TX_XBI { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 6 \TX_XO - process $group_319 - assign \TX_XO 6'000000 - assign \TX_XO { \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \VA_RA - process $group_320 - assign \VA_RA 5'00000 - assign \VA_RA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \VA_RB - process $group_321 - assign \VA_RB 5'00000 - assign \VA_RB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \VA_RC - process $group_322 - assign \VA_RC 5'00000 - assign \VA_RC { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \VA_RT - process $group_323 - assign \VA_RT 5'00000 - assign \VA_RT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 4 \VA_SHB - process $group_324 - assign \VA_SHB 4'0000 - assign \VA_SHB { \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \VA_VRA - process $group_325 - assign \VA_VRA 5'00000 - assign \VA_VRA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \VA_VRB - process $group_326 - assign \VA_VRB 5'00000 - assign \VA_VRB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \VA_VRC - process $group_327 - assign \VA_VRC 5'00000 - assign \VA_VRC { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \VA_VRT - process $group_328 - assign \VA_VRT 5'00000 - assign \VA_VRT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 6 \VA_XO - process $group_329 - assign \VA_XO 6'000000 - assign \VA_XO { \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] \opcode_in [0] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \XS_RA - process $group_330 - assign \XS_RA 5'00000 - assign \XS_RA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \XS_Rc - process $group_331 - assign \XS_Rc 1'0 - assign \XS_Rc { \opcode_in [0] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \XS_RS - process $group_332 - assign \XS_RS 5'00000 - assign \XS_RS { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 6 \XS_sh - process $group_333 - assign \XS_sh 6'000000 - assign \XS_sh { \opcode_in [1] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 9 \XS_XO - process $group_334 - assign \XS_XO 9'000000000 - assign \XS_XO { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \VC_Rc - process $group_335 - assign \VC_Rc 1'0 - assign \VC_Rc { \opcode_in [10] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \VC_VRA - process $group_336 - assign \VC_VRA 5'00000 - assign \VC_VRA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \VC_VRB - process $group_337 - assign \VC_VRB 5'00000 - assign \VC_VRB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \VC_VRT - process $group_338 - assign \VC_VRT 5'00000 - assign \VC_VRT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 10 \VC_XO - process $group_339 - assign \VC_XO 10'0000000000 - assign \VC_XO { \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] \opcode_in [0] } - sync init - end - connect \SPR_function_unit$1 11'00000000000 - connect \SPR_function_unit$2 11'00000000000 - connect \SPR_function_unit$3 11'00000000000 - connect \SPR_function_unit$4 11'00000000000 - connect \SPR_internal_op$5 7'0000000 - connect \SPR_internal_op$6 7'0000000 - connect \SPR_internal_op$7 7'0000000 - connect \SPR_internal_op$8 7'0000000 - connect \SPR_cr_in$9 3'000 - connect \SPR_cr_in$10 3'000 - connect \SPR_cr_in$11 3'000 - connect \SPR_cr_in$12 3'000 - connect \SPR_cr_out$13 3'000 - connect \SPR_cr_out$14 3'000 - connect \SPR_cr_out$15 3'000 - connect \SPR_cr_out$16 3'000 - connect \SPR_rc_sel$17 2'00 - connect \SPR_rc_sel$18 2'00 - connect \SPR_rc_sel$19 2'00 - connect \SPR_rc_sel$20 2'00 - connect \SPR_is_32b$21 1'0 - connect \SPR_is_32b$22 1'0 - connect \SPR_is_32b$23 1'0 - connect \SPR_is_32b$24 1'0 -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.dec_SPR.dec_rc" -module \dec_rc$162 - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:404" - wire width 2 input 0 \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 1 \rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 1 input 2 \SPR_Rc - process $group_0 - assign \rc 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:413" - switch \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:414" - attribute \nmigen.decoding "RC/2" - case 2'10 - assign \rc \SPR_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:417" - attribute \nmigen.decoding "ONE/1" - case 2'01 - assign \rc 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:420" - attribute \nmigen.decoding "NONE/0" - case 2'00 - assign \rc 1'0 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \rc_ok - process $group_1 - assign \rc_ok 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:413" - switch \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:414" - attribute \nmigen.decoding "RC/2" - case 2'10 - assign \rc_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:417" - attribute \nmigen.decoding "ONE/1" - case 2'01 - assign \rc_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:420" - attribute \nmigen.decoding "NONE/0" - case 2'00 - assign \rc_ok 1'1 - end - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.dec_SPR.dec_oe" -module \dec_oe$163 - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:441" - wire width 2 input 0 \sel_in - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 7 input 1 \SPR_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 1 input 2 \SPR_OE - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \oe - process $group_0 - assign \oe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:450" - switch \SPR_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:461" - attribute \nmigen.decoding "OP_MUL_H64/51|OP_MUL_H32/52|OP_EXTS/31|OP_CNTZ/14|OP_SHL/60|OP_SHR/61|OP_RLC/56|OP_LOAD/37|OP_STORE/38|OP_RLCL/57|OP_RLCR/58|OP_EXTSWSLI/32" - case 7'0110011, 7'0110100, 7'0011111, 7'0001110, 7'0111100, 7'0111101, 7'0111000, 7'0100101, 7'0100110, 7'0111001, 7'0111010, 7'0100000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:465" - attribute \nmigen.decoding "" - case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:467" - switch \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:468" - attribute \nmigen.decoding "RC/2" - case 2'10 - assign \oe \SPR_OE - end - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \oe_ok - process $group_1 - assign \oe_ok 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:450" - switch \SPR_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:461" - attribute \nmigen.decoding "OP_MUL_H64/51|OP_MUL_H32/52|OP_EXTS/31|OP_CNTZ/14|OP_SHL/60|OP_SHR/61|OP_RLC/56|OP_LOAD/37|OP_STORE/38|OP_RLCL/57|OP_RLCR/58|OP_EXTSWSLI/32" - case 7'0110011, 7'0110100, 7'0011111, 7'0001110, 7'0111100, 7'0111101, 7'0111000, 7'0100101, 7'0100110, 7'0111001, 7'0111010, 7'0100000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:465" - attribute \nmigen.decoding "" - case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:467" - switch \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:468" - attribute \nmigen.decoding "RC/2" - case 2'10 - assign \oe_ok 1'1 - end - end - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.dec_SPR.dec_cr_in.ppick" -module \ppick$165 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" - wire width 8 input 0 \i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" - wire width 8 output 1 \o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:49" - wire width 8 \ni - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" - wire width 8 $1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" - cell $not $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \Y_WIDTH 8 - connect \A { \i [0] \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] } - connect \Y $1 - end - process $group_0 - assign \ni 8'00000000 - assign \ni $1 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire width 1 \t0 - process $group_1 - assign \t0 1'0 - assign \t0 \i [7] - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire width 1 \t1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire width 1 $3 - attribute \src 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[1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [7] } - connect \Y $28 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $30 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $28 - connect \Y $27 - end - process $group_8 - assign \t7 1'0 - assign \t7 $27 - sync init - end - process $group_9 - assign \o 8'00000000 - assign \o { \t0 \t1 \t2 \t3 \t4 \t5 \t6 \t7 } - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" - wire width 1 \en_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" - wire width 1 $31 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" - cell $reduce_bool $32 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \o - connect \Y $31 - end - process $group_10 - assign \en_o 1'0 - assign \en_o $31 - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.dec_SPR.dec_cr_in" -module \dec_cr_in$164 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:485" - wire width 32 input 0 \insn_in - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:484" - wire width 3 input 1 \sel_in - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 7 input 2 \SPR_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 5 input 3 \SPR_BB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 5 input 4 \SPR_BA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 5 input 5 \SPR_BT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 8 input 6 \SPR_FXM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 5 input 7 \SPR_BI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 5 input 8 \SPR_BC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 3 input 9 \X_BFA - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" - wire width 8 \ppick_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" - wire width 8 \ppick_o - cell \ppick$165 \ppick - connect \i \ppick_i - connect \o \ppick_o - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \cr_bitfield_ok - process $group_0 - assign \cr_bitfield_ok 1'0 - assign \cr_bitfield_ok 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" - switch \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" - attribute \nmigen.decoding "NONE/0" - case 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:505" - attribute \nmigen.decoding "CR0/1" - case 3'001 - assign \cr_bitfield_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:508" - attribute \nmigen.decoding "BI/2" - case 3'010 - assign \cr_bitfield_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:511" - attribute \nmigen.decoding "BFA/3" - case 3'011 - assign \cr_bitfield_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:514" - attribute \nmigen.decoding "BA_BB/4" - case 3'100 - assign \cr_bitfield_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:521" - attribute \nmigen.decoding "BC/5" - case 3'101 - assign \cr_bitfield_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:524" - attribute \nmigen.decoding "WHOLE_REG/6" - case 3'110 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \cr_bitfield_b_ok - process $group_1 - assign \cr_bitfield_b_ok 1'0 - assign \cr_bitfield_b_ok 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" - switch \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" - attribute \nmigen.decoding "NONE/0" - case 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:505" - attribute \nmigen.decoding "CR0/1" - case 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:508" - attribute \nmigen.decoding "BI/2" - case 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:511" - attribute \nmigen.decoding "BFA/3" - case 3'011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:514" - attribute \nmigen.decoding "BA_BB/4" - case 3'100 - assign \cr_bitfield_b_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:521" - attribute \nmigen.decoding "BC/5" - case 3'101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:524" - attribute \nmigen.decoding "WHOLE_REG/6" - case 3'110 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \cr_fxm_ok - process $group_2 - assign \cr_fxm_ok 1'0 - assign \cr_fxm_ok 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" - switch \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" - attribute \nmigen.decoding "NONE/0" - case 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:505" - attribute \nmigen.decoding "CR0/1" - case 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:508" - attribute \nmigen.decoding "BI/2" - case 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:511" - attribute \nmigen.decoding "BFA/3" - case 3'011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:514" - attribute \nmigen.decoding "BA_BB/4" - case 3'100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:521" - attribute \nmigen.decoding "BC/5" - case 3'101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:524" - attribute \nmigen.decoding "WHOLE_REG/6" - case 3'110 - assign \cr_fxm_ok 1'1 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 3 \cr_bitfield - process $group_3 - assign \cr_bitfield 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" - switch \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" - attribute \nmigen.decoding "NONE/0" - case 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:505" - attribute \nmigen.decoding "CR0/1" - case 3'001 - assign \cr_bitfield 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:508" - attribute \nmigen.decoding "BI/2" - case 3'010 - assign \cr_bitfield \SPR_BI [4:2] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:511" - attribute \nmigen.decoding "BFA/3" - case 3'011 - assign \cr_bitfield \X_BFA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:514" - attribute \nmigen.decoding "BA_BB/4" - case 3'100 - assign \cr_bitfield \SPR_BA [4:2] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:521" - attribute \nmigen.decoding "BC/5" - case 3'101 - assign \cr_bitfield \SPR_BC [4:2] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:524" - attribute \nmigen.decoding "WHOLE_REG/6" - case 3'110 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 3 \cr_bitfield_b - process $group_4 - assign \cr_bitfield_b 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" - switch \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" - attribute \nmigen.decoding "NONE/0" - case 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:505" - attribute \nmigen.decoding "CR0/1" - case 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:508" - attribute \nmigen.decoding "BI/2" - case 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:511" - attribute \nmigen.decoding "BFA/3" - case 3'011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:514" - attribute \nmigen.decoding "BA_BB/4" - case 3'100 - assign \cr_bitfield_b \SPR_BB [4:2] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:521" - attribute \nmigen.decoding "BC/5" - case 3'101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:524" - attribute \nmigen.decoding "WHOLE_REG/6" - case 3'110 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 3 \cr_bitfield_o - process $group_5 - assign \cr_bitfield_o 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" - switch \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" - attribute \nmigen.decoding "NONE/0" - case 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:505" - attribute \nmigen.decoding "CR0/1" - case 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:508" - attribute \nmigen.decoding "BI/2" - case 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:511" - attribute \nmigen.decoding "BFA/3" - case 3'011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:514" - attribute \nmigen.decoding "BA_BB/4" - case 3'100 - assign \cr_bitfield_o \SPR_BT [4:2] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:521" - attribute \nmigen.decoding "BC/5" - case 3'101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:524" - attribute \nmigen.decoding "WHOLE_REG/6" - case 3'110 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \cr_bitfield_o_ok - process $group_6 - assign \cr_bitfield_o_ok 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" - switch \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" - attribute \nmigen.decoding "NONE/0" - case 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:505" - attribute \nmigen.decoding "CR0/1" - case 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:508" - attribute \nmigen.decoding "BI/2" - case 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:511" - attribute \nmigen.decoding "BFA/3" - case 3'011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:514" - attribute \nmigen.decoding "BA_BB/4" - case 3'100 - assign \cr_bitfield_o_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:521" - attribute \nmigen.decoding "BC/5" - case 3'101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:524" - attribute \nmigen.decoding "WHOLE_REG/6" - case 3'110 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:526" - wire width 1 \move_one - process $group_7 - assign \move_one 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" - switch \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" - attribute \nmigen.decoding "NONE/0" - case 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:505" - attribute \nmigen.decoding "CR0/1" - case 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:508" - attribute \nmigen.decoding "BI/2" - case 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:511" - attribute \nmigen.decoding "BFA/3" - case 3'011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:514" - attribute \nmigen.decoding "BA_BB/4" - case 3'100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:521" - attribute \nmigen.decoding "BC/5" - case 3'101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:524" - attribute \nmigen.decoding "WHOLE_REG/6" - case 3'110 - assign \move_one \insn_in [20] - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" - cell $eq $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A \SPR_internal_op - connect \B 7'0101101 - connect \Y $1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" - wire width 1 $3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" - cell $and $4 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $1 - connect \B \move_one - connect \Y $3 - end - process $group_8 - assign \ppick_i 8'00000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" - switch \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" - attribute \nmigen.decoding "NONE/0" - case 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:505" - attribute \nmigen.decoding "CR0/1" - case 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:508" - attribute \nmigen.decoding "BI/2" - case 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:511" - attribute \nmigen.decoding "BFA/3" - case 3'011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:514" - attribute \nmigen.decoding "BA_BB/4" - case 3'100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:521" - attribute \nmigen.decoding "BC/5" - case 3'101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:524" - attribute \nmigen.decoding "WHOLE_REG/6" - case 3'110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" - switch { $3 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" - case 1'1 - assign \ppick_i \SPR_FXM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532" - case - end - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 8 \cr_fxm - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" - wire width 1 $5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" - cell $eq $6 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A \SPR_internal_op - connect \B 7'0101101 - connect \Y $5 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" - wire width 1 $7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" - cell $and $8 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $5 - connect \B \move_one - connect \Y $7 - end - process $group_9 - assign \cr_fxm 8'00000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" - switch \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" - attribute \nmigen.decoding "NONE/0" - case 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:505" - attribute \nmigen.decoding "CR0/1" - case 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:508" - attribute \nmigen.decoding "BI/2" - case 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:511" - attribute \nmigen.decoding "BFA/3" - case 3'011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:514" - attribute \nmigen.decoding "BA_BB/4" - case 3'100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:521" - attribute \nmigen.decoding "BC/5" - case 3'101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:524" - attribute \nmigen.decoding "WHOLE_REG/6" - case 3'110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" - switch { $7 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" - case 1'1 - assign \cr_fxm \ppick_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532" - case - assign \cr_fxm 8'11111111 - end - end - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.dec_SPR.dec_cr_out.ppick" -module \ppick$167 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" - wire width 8 input 0 \i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" - wire width 1 output 1 \en_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" - wire width 8 output 2 \o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:49" - wire width 8 \ni - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" - wire width 8 $1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" - cell $not $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \Y_WIDTH 8 - connect \A { \i [0] \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] } - connect \Y $1 - end - process $group_0 - assign \ni 8'00000000 - assign \ni $1 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire width 1 \t0 - process $group_1 - assign \t0 1'0 - assign \t0 \i [7] - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire width 1 \t1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire width 1 $3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire width 1 $4 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_bool $5 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A { \i [7] \ni [1] } - connect \Y $4 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $6 - parameter \A_SIGNED 0 - parameter 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width 1 \t3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire width 1 $11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire width 1 $12 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_bool $13 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A { \i [5] \i [6] \i [7] \ni [3] } - connect \Y $12 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $14 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $12 - connect \Y $11 - end - process $group_4 - assign \t3 1'0 - assign \t3 $11 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire width 1 \t4 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire width 1 $15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire width 1 $16 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_bool $17 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A { \i [4] \i [5] \i [6] \i [7] \ni [4] } - connect \Y $16 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $18 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $16 - connect \Y $15 - end - process $group_5 - assign \t4 1'0 - assign \t4 $15 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire width 1 \t5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire width 1 $19 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire width 1 $20 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_bool $21 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \Y_WIDTH 1 - connect \A { \i [3] \i [4] \i [5] \i [6] \i [7] \ni [5] } - connect \Y $20 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $22 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $20 - connect \Y $19 - end - process $group_6 - assign \t5 1'0 - assign \t5 $19 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire width 1 \t6 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire width 1 $23 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire width 1 $24 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_bool $25 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A { \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [6] } - connect \Y $24 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $26 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $24 - connect \Y $23 - end - process $group_7 - assign \t6 1'0 - assign \t6 $23 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire width 1 \t7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire width 1 $27 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire width 1 $28 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_bool $29 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A { \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [7] } - connect \Y $28 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $30 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $28 - connect \Y $27 - end - process $group_8 - assign \t7 1'0 - assign \t7 $27 - sync init - end - process $group_9 - assign \o 8'00000000 - assign \o { \t0 \t1 \t2 \t3 \t4 \t5 \t6 \t7 } - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" - wire width 1 $31 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" - cell $reduce_bool $32 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \o - connect \Y $31 - end - process $group_10 - assign \en_o 1'0 - assign \en_o $31 - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.dec_SPR.dec_cr_out" -module \dec_cr_out$166 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:550" - wire width 32 input 0 \insn_in - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:549" - wire width 3 input 1 \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:548" - wire width 1 input 2 \rc_in - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 7 input 3 \SPR_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 8 input 4 \SPR_FXM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 3 input 5 \X_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 input 6 \XL_BT - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" - wire width 8 \ppick_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" - wire width 1 \ppick_en_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" - wire width 8 \ppick_o - cell \ppick$167 \ppick - connect \i \ppick_i - connect \en_o \ppick_en_o - connect \o \ppick_o - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \cr_bitfield_ok - process $group_0 - assign \cr_bitfield_ok 1'0 - assign \cr_bitfield_ok 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:563" - switch \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:564" - attribute \nmigen.decoding "NONE/0" - case 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:566" - attribute \nmigen.decoding "CR0/1" - case 3'001 - assign \cr_bitfield_ok \rc_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:569" - attribute \nmigen.decoding "BF/2" - case 3'010 - assign \cr_bitfield_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:572" - attribute \nmigen.decoding "BT/3" - case 3'011 - assign \cr_bitfield_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:575" - attribute \nmigen.decoding "WHOLE_REG/4" - case 3'100 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \cr_fxm_ok - process $group_1 - assign \cr_fxm_ok 1'0 - assign \cr_fxm_ok 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:563" - switch \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:564" - attribute \nmigen.decoding "NONE/0" - case 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:566" - attribute \nmigen.decoding "CR0/1" - case 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:569" - attribute \nmigen.decoding "BF/2" - case 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:572" - attribute \nmigen.decoding "BT/3" - case 3'011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:575" - attribute \nmigen.decoding "WHOLE_REG/4" - case 3'100 - assign \cr_fxm_ok 1'1 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 3 \cr_bitfield - process $group_2 - assign \cr_bitfield 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:563" - switch \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:564" - attribute \nmigen.decoding "NONE/0" - case 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:566" - attribute \nmigen.decoding "CR0/1" - case 3'001 - assign \cr_bitfield 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:569" - attribute \nmigen.decoding "BF/2" - case 3'010 - assign \cr_bitfield \X_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:572" - attribute \nmigen.decoding "BT/3" - case 3'011 - assign \cr_bitfield \XL_BT [4:2] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:575" - attribute \nmigen.decoding "WHOLE_REG/4" - case 3'100 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:577" - wire width 1 \move_one - process $group_3 - assign \move_one 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:563" - switch \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:564" - attribute \nmigen.decoding "NONE/0" - case 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:566" - attribute \nmigen.decoding "CR0/1" - case 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:569" - attribute \nmigen.decoding "BF/2" - case 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:572" - attribute \nmigen.decoding "BT/3" - case 3'011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:575" - attribute \nmigen.decoding "WHOLE_REG/4" - case 3'100 - assign \move_one \insn_in [20] - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:579" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:579" - cell $eq $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A \SPR_internal_op - connect \B 7'0110000 - connect \Y $1 - end - process $group_4 - assign \ppick_i 8'00000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:563" - switch \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:564" - attribute \nmigen.decoding "NONE/0" - case 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:566" - attribute \nmigen.decoding "CR0/1" - case 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:569" - attribute \nmigen.decoding "BF/2" - case 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:572" - attribute \nmigen.decoding "BT/3" - case 3'011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:575" - attribute \nmigen.decoding "WHOLE_REG/4" - case 3'100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:579" - switch { $1 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:579" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:580" - switch { \move_one } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:580" - case 1'1 - assign \ppick_i \SPR_FXM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:587" - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:589" - case - end - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 8 \cr_fxm - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:579" - wire width 1 $3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:579" - cell $eq $4 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A \SPR_internal_op - connect \B 7'0110000 - connect \Y $3 - end - process $group_5 - assign \cr_fxm 8'00000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:563" - switch \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:564" - attribute \nmigen.decoding "NONE/0" - case 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:566" - attribute \nmigen.decoding "CR0/1" - case 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:569" - attribute \nmigen.decoding "BF/2" - case 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:572" - attribute \nmigen.decoding "BT/3" - case 3'011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:575" - attribute \nmigen.decoding "WHOLE_REG/4" - case 3'100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:579" - switch { $3 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:579" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:580" - switch { \move_one } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:580" - case 1'1 - attribute \src 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10'0000000000 - assign \opcode_switch \opcode_in [10:1] - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:308" - wire width 5 \opcode_switch$1 - process $group_1 - assign \opcode_switch$1 5'00000 - assign \opcode_switch$1 \opcode_in [5:1] - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.dec_DIV.dec.DIV_dec30" -module \DIV_dec30 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" - wire width 32 input 0 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:308" - wire width 4 \opcode_switch - process $group_0 - assign \opcode_switch 4'0000 - assign \opcode_switch \opcode_in [4:1] - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.dec_DIV.dec.DIV_dec31.DIV_dec_sub10" -module \DIV_dec_sub10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" - 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\opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:308" - wire width 5 \opcode_switch - process $group_0 - assign \opcode_switch 5'00000 - assign \opcode_switch \opcode_in [10:6] - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.dec_DIV.dec.DIV_dec31.DIV_dec_sub26" -module \DIV_dec_sub26 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" - wire width 32 input 0 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:308" - wire width 5 \opcode_switch - process $group_0 - assign \opcode_switch 5'00000 - assign \opcode_switch \opcode_in [10:6] - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.dec_DIV.dec.DIV_dec31.DIV_dec_sub19" -module \DIV_dec_sub19 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" - wire width 32 input 0 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:308" - wire width 5 \opcode_switch - process $group_0 - assign \opcode_switch 5'00000 - assign \opcode_switch \opcode_in [10:6] - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.dec_DIV.dec.DIV_dec31.DIV_dec_sub22" -module \DIV_dec_sub22 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" - wire width 32 input 0 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:308" - wire width 5 \opcode_switch - process $group_0 - assign \opcode_switch 5'00000 - assign \opcode_switch \opcode_in [10:6] - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.dec_DIV.dec.DIV_dec31.DIV_dec_sub9" -module \DIV_dec_sub9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" - wire width 32 input 0 \opcode_in - attribute \enum_base_type "Function" - attribute \enum_value_00000000000 "NONE" - attribute \enum_value_00000000010 "ALU" - attribute \enum_value_00000000100 "LDST" - attribute \enum_value_00000001000 "SHIFT_ROT" - attribute \enum_value_00000010000 "LOGICAL" - attribute \enum_value_00000100000 "BRANCH" - attribute \enum_value_00001000000 "CR" - attribute \enum_value_00010000000 "TRAP" - attribute \enum_value_00100000000 "MUL" - attribute \enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 11 output 1 \DIV_function_unit - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 7 output 2 \DIV_internal_op - attribute \enum_base_type "In1Sel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "RA" - attribute \enum_value_010 "RA_OR_ZERO" - attribute \enum_value_011 "SPR" - attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 output 3 \DIV_in1_sel - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 4 output 4 \DIV_in2_sel - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 output 5 \DIV_cr_in - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 output 6 \DIV_cr_out - attribute \enum_base_type "LdstLen" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "is1B" - attribute \enum_value_0010 "is2B" - attribute \enum_value_0100 "is4B" - attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 4 output 7 \DIV_ldst_len - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 2 output 8 \DIV_rc_sel - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 2 output 9 \DIV_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 output 10 \DIV_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 output 11 \DIV_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 output 12 \DIV_cry_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 output 13 \DIV_is_32b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 output 14 \DIV_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:308" - wire width 5 \opcode_switch - process $group_0 - assign \opcode_switch 5'00000 - assign \opcode_switch \opcode_in [10:6] - sync init - end - process $group_1 - assign \DIV_function_unit 11'00000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01100 - assign \DIV_function_unit 11'01000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11100 - assign \DIV_function_unit 11'01000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01101 - assign \DIV_function_unit 11'01000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11101 - assign \DIV_function_unit 11'01000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01110 - assign \DIV_function_unit 11'01000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11110 - assign \DIV_function_unit 11'01000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01111 - assign \DIV_function_unit 11'01000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11111 - assign \DIV_function_unit 11'01000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01000 - assign \DIV_function_unit 11'01000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11000 - assign \DIV_function_unit 11'01000000000 - end - sync init - end - process $group_2 - assign \DIV_internal_op 7'0000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01100 - assign \DIV_internal_op 7'0011110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11100 - assign \DIV_internal_op 7'0011110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01101 - assign \DIV_internal_op 7'0011110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11101 - assign \DIV_internal_op 7'0011110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01110 - assign \DIV_internal_op 7'0011101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11110 - assign \DIV_internal_op 7'0011101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01111 - assign \DIV_internal_op 7'0011101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11111 - assign \DIV_internal_op 7'0011101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01000 - assign \DIV_internal_op 7'0101111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11000 - assign \DIV_internal_op 7'0101111 - end - sync init - end - process $group_3 - assign \DIV_in1_sel 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01100 - assign \DIV_in1_sel 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11100 - assign \DIV_in1_sel 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01101 - assign \DIV_in1_sel 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11101 - assign \DIV_in1_sel 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01110 - assign \DIV_in1_sel 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11110 - assign \DIV_in1_sel 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01111 - assign \DIV_in1_sel 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11111 - assign \DIV_in1_sel 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01000 - assign \DIV_in1_sel 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11000 - assign \DIV_in1_sel 3'001 - end - sync init - end - process $group_4 - assign \DIV_in2_sel 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01100 - assign \DIV_in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11100 - assign \DIV_in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01101 - assign \DIV_in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11101 - assign \DIV_in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01110 - assign \DIV_in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11110 - assign \DIV_in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01111 - assign \DIV_in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11111 - assign \DIV_in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01000 - assign \DIV_in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11000 - assign \DIV_in2_sel 4'0001 - end - sync init - end - process $group_5 - assign \DIV_cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01100 - assign \DIV_cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11100 - assign \DIV_cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01101 - assign \DIV_cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11101 - assign \DIV_cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01110 - assign \DIV_cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11110 - assign \DIV_cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01111 - assign \DIV_cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11111 - assign \DIV_cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01000 - assign \DIV_cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11000 - assign \DIV_cr_in 3'000 - end - sync init - end - process $group_6 - assign \DIV_cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01100 - assign \DIV_cr_out 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11100 - assign \DIV_cr_out 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01101 - assign \DIV_cr_out 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11101 - assign \DIV_cr_out 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01110 - assign \DIV_cr_out 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11110 - assign \DIV_cr_out 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01111 - assign \DIV_cr_out 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11111 - assign \DIV_cr_out 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01000 - assign \DIV_cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11000 - assign \DIV_cr_out 3'000 - end - sync init - end - process $group_7 - assign \DIV_ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01100 - assign \DIV_ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11100 - assign \DIV_ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01101 - assign \DIV_ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11101 - assign \DIV_ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01110 - assign \DIV_ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11110 - assign \DIV_ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01111 - assign \DIV_ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11111 - assign \DIV_ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01000 - assign \DIV_ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11000 - assign \DIV_ldst_len 4'0000 - end - sync init - end - process $group_8 - assign \DIV_rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01100 - assign \DIV_rc_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11100 - assign \DIV_rc_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01101 - assign \DIV_rc_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11101 - assign \DIV_rc_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01110 - assign \DIV_rc_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11110 - assign \DIV_rc_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01111 - assign \DIV_rc_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11111 - assign \DIV_rc_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01000 - assign \DIV_rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11000 - assign \DIV_rc_sel 2'00 - end - sync init - end - process $group_9 - assign \DIV_cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01100 - assign \DIV_cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11100 - assign \DIV_cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01101 - assign \DIV_cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11101 - assign \DIV_cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01110 - assign \DIV_cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11110 - assign \DIV_cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01111 - assign \DIV_cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11111 - assign \DIV_cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01000 - assign \DIV_cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11000 - assign \DIV_cry_in 2'00 - end - sync init - end - process $group_10 - assign \DIV_inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01100 - assign \DIV_inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11100 - assign \DIV_inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01101 - assign \DIV_inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11101 - assign \DIV_inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01110 - assign \DIV_inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11110 - assign \DIV_inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01111 - assign \DIV_inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11111 - assign \DIV_inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01000 - assign \DIV_inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11000 - assign \DIV_inv_a 1'0 - end - sync init - end - process $group_11 - assign \DIV_inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01100 - assign \DIV_inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11100 - assign \DIV_inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01101 - assign \DIV_inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11101 - assign \DIV_inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01110 - assign \DIV_inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11110 - assign \DIV_inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01111 - assign \DIV_inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11111 - assign \DIV_inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01000 - assign \DIV_inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11000 - assign \DIV_inv_out 1'0 - end - sync init - end - process $group_12 - assign \DIV_cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01100 - assign \DIV_cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11100 - assign \DIV_cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01101 - assign \DIV_cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11101 - assign \DIV_cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01110 - assign \DIV_cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11110 - assign \DIV_cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01111 - assign \DIV_cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11111 - assign \DIV_cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01000 - assign \DIV_cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11000 - assign \DIV_cry_out 1'0 - end - sync init - end - process $group_13 - assign \DIV_is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01100 - assign \DIV_is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11100 - assign \DIV_is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01101 - assign \DIV_is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11101 - assign \DIV_is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01110 - assign \DIV_is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11110 - assign \DIV_is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01111 - assign \DIV_is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11111 - assign \DIV_is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01000 - assign \DIV_is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11000 - assign \DIV_is_32b 1'0 - end - sync init - end - process $group_14 - assign \DIV_sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01100 - assign \DIV_sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11100 - assign \DIV_sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01101 - assign \DIV_sgn 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11101 - assign \DIV_sgn 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01110 - assign \DIV_sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11110 - assign \DIV_sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01111 - assign \DIV_sgn 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11111 - assign \DIV_sgn 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01000 - assign \DIV_sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11000 - assign \DIV_sgn 1'1 - end - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.dec_DIV.dec.DIV_dec31.DIV_dec_sub11" -module \DIV_dec_sub11 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" - wire width 32 input 0 \opcode_in - attribute \enum_base_type "Function" - attribute \enum_value_00000000000 "NONE" - attribute \enum_value_00000000010 "ALU" - attribute \enum_value_00000000100 "LDST" - attribute \enum_value_00000001000 "SHIFT_ROT" - attribute \enum_value_00000010000 "LOGICAL" - attribute \enum_value_00000100000 "BRANCH" - attribute \enum_value_00001000000 "CR" - attribute \enum_value_00010000000 "TRAP" - attribute \enum_value_00100000000 "MUL" - attribute \enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 11 output 1 \DIV_function_unit - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 7 output 2 \DIV_internal_op - attribute \enum_base_type "In1Sel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "RA" - attribute \enum_value_010 "RA_OR_ZERO" - attribute \enum_value_011 "SPR" - attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 output 3 \DIV_in1_sel - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 4 output 4 \DIV_in2_sel - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 output 5 \DIV_cr_in - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 output 6 \DIV_cr_out - attribute \enum_base_type "LdstLen" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "is1B" - attribute \enum_value_0010 "is2B" - attribute \enum_value_0100 "is4B" - attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 4 output 7 \DIV_ldst_len - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 2 output 8 \DIV_rc_sel - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 2 output 9 \DIV_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 output 10 \DIV_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 output 11 \DIV_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 output 12 \DIV_cry_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 output 13 \DIV_is_32b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 output 14 \DIV_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:308" - wire width 5 \opcode_switch - process $group_0 - assign \opcode_switch 5'00000 - assign \opcode_switch \opcode_in [10:6] - sync init - end - process $group_1 - assign \DIV_function_unit 11'00000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01100 - assign \DIV_function_unit 11'01000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11100 - assign \DIV_function_unit 11'01000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01101 - assign \DIV_function_unit 11'01000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11101 - assign \DIV_function_unit 11'01000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01110 - assign \DIV_function_unit 11'01000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11110 - assign \DIV_function_unit 11'01000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01111 - assign \DIV_function_unit 11'01000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11111 - assign \DIV_function_unit 11'01000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01000 - assign \DIV_function_unit 11'01000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11000 - assign \DIV_function_unit 11'01000000000 - end - sync init - end - process $group_2 - assign \DIV_internal_op 7'0000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01100 - assign \DIV_internal_op 7'0011110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11100 - assign \DIV_internal_op 7'0011110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01101 - assign \DIV_internal_op 7'0011110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11101 - assign \DIV_internal_op 7'0011110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01110 - assign \DIV_internal_op 7'0011101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11110 - assign \DIV_internal_op 7'0011101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01111 - assign \DIV_internal_op 7'0011101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11111 - assign \DIV_internal_op 7'0011101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01000 - assign \DIV_internal_op 7'0101111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11000 - assign \DIV_internal_op 7'0101111 - end - sync init - end - process $group_3 - assign \DIV_in1_sel 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01100 - assign \DIV_in1_sel 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11100 - assign \DIV_in1_sel 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01101 - assign \DIV_in1_sel 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11101 - assign \DIV_in1_sel 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01110 - assign \DIV_in1_sel 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11110 - assign \DIV_in1_sel 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01111 - assign \DIV_in1_sel 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11111 - assign \DIV_in1_sel 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01000 - assign \DIV_in1_sel 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11000 - assign \DIV_in1_sel 3'001 - end - sync init - end - process $group_4 - assign \DIV_in2_sel 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01100 - assign \DIV_in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11100 - assign \DIV_in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01101 - assign \DIV_in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11101 - assign \DIV_in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01110 - assign \DIV_in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11110 - assign \DIV_in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01111 - assign \DIV_in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11111 - assign \DIV_in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01000 - assign \DIV_in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11000 - assign \DIV_in2_sel 4'0001 - end - sync init - end - process $group_5 - assign \DIV_cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01100 - assign \DIV_cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11100 - assign \DIV_cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01101 - assign \DIV_cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11101 - assign \DIV_cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01110 - assign \DIV_cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11110 - assign \DIV_cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01111 - assign \DIV_cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11111 - assign \DIV_cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01000 - assign \DIV_cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11000 - assign \DIV_cr_in 3'000 - end - sync init - end - process $group_6 - assign \DIV_cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01100 - assign \DIV_cr_out 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11100 - assign \DIV_cr_out 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01101 - assign \DIV_cr_out 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11101 - assign \DIV_cr_out 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01110 - assign \DIV_cr_out 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11110 - assign \DIV_cr_out 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01111 - assign \DIV_cr_out 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11111 - assign \DIV_cr_out 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01000 - assign \DIV_cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11000 - assign \DIV_cr_out 3'000 - end - sync init - end - process $group_7 - assign \DIV_ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01100 - assign \DIV_ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11100 - assign \DIV_ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01101 - assign \DIV_ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11101 - assign \DIV_ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01110 - assign \DIV_ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11110 - assign \DIV_ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01111 - assign \DIV_ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11111 - assign \DIV_ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01000 - assign \DIV_ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11000 - assign \DIV_ldst_len 4'0000 - end - sync init - end - process $group_8 - assign \DIV_rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01100 - assign \DIV_rc_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11100 - assign \DIV_rc_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01101 - assign \DIV_rc_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11101 - assign \DIV_rc_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01110 - assign \DIV_rc_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11110 - assign \DIV_rc_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01111 - assign \DIV_rc_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11111 - assign \DIV_rc_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01000 - assign \DIV_rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11000 - assign \DIV_rc_sel 2'00 - end - sync init - end - process $group_9 - assign \DIV_cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01100 - assign \DIV_cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11100 - assign \DIV_cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01101 - assign \DIV_cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11101 - assign \DIV_cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01110 - assign \DIV_cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11110 - assign \DIV_cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01111 - assign \DIV_cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11111 - assign \DIV_cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01000 - assign \DIV_cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11000 - assign \DIV_cry_in 2'00 - end - sync init - end - process $group_10 - assign \DIV_inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01100 - assign \DIV_inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11100 - assign \DIV_inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01101 - assign \DIV_inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11101 - assign \DIV_inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01110 - assign \DIV_inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11110 - assign \DIV_inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01111 - assign \DIV_inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11111 - assign \DIV_inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01000 - assign \DIV_inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11000 - assign \DIV_inv_a 1'0 - end - sync init - end - process $group_11 - assign \DIV_inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01100 - assign \DIV_inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11100 - assign \DIV_inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01101 - assign \DIV_inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11101 - assign \DIV_inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01110 - assign \DIV_inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11110 - assign \DIV_inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01111 - assign \DIV_inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11111 - assign \DIV_inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01000 - assign \DIV_inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11000 - assign \DIV_inv_out 1'0 - end - sync init - end - process $group_12 - assign \DIV_cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01100 - assign \DIV_cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11100 - assign \DIV_cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01101 - assign \DIV_cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11101 - assign \DIV_cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01110 - assign \DIV_cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11110 - assign \DIV_cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01111 - assign \DIV_cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11111 - assign \DIV_cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01000 - assign \DIV_cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11000 - assign \DIV_cry_out 1'0 - end - sync init - end - process $group_13 - assign \DIV_is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01100 - assign \DIV_is_32b 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11100 - assign \DIV_is_32b 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01101 - assign \DIV_is_32b 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11101 - assign \DIV_is_32b 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01110 - assign \DIV_is_32b 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11110 - assign \DIV_is_32b 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01111 - assign \DIV_is_32b 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11111 - assign \DIV_is_32b 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01000 - assign \DIV_is_32b 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11000 - assign \DIV_is_32b 1'1 - end - sync init - end - process $group_14 - assign \DIV_sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01100 - assign \DIV_sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11100 - assign \DIV_sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01101 - assign \DIV_sgn 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11101 - assign \DIV_sgn 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01110 - assign \DIV_sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11110 - assign \DIV_sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01111 - assign \DIV_sgn 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11111 - assign \DIV_sgn 1'1 - attribute \src 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assign \DIV_internal_op \DIV_internal_op$17 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'11100 - assign \DIV_internal_op \DIV_internal_op$18 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'00000 - assign \DIV_internal_op \DIV_internal_op$19 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'11010 - assign \DIV_internal_op \DIV_internal_op$20 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10011 - assign \DIV_internal_op \DIV_internal_op$21 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10110 - assign \DIV_internal_op \DIV_internal_op$22 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01001 - assign \DIV_internal_op \DIV_dec_sub9_DIV_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01011 - assign \DIV_internal_op \DIV_dec_sub11_DIV_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'11011 - assign \DIV_internal_op \DIV_internal_op$23 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01111 - assign \DIV_internal_op \DIV_internal_op$24 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10100 - assign \DIV_internal_op \DIV_internal_op$25 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10101 - assign \DIV_internal_op \DIV_internal_op$26 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10111 - assign \DIV_internal_op \DIV_internal_op$27 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10000 - assign \DIV_internal_op \DIV_internal_op$28 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10010 - assign \DIV_internal_op \DIV_internal_op$29 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01000 - assign \DIV_internal_op \DIV_internal_op$30 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'11000 - assign \DIV_internal_op \DIV_internal_op$31 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'00100 - assign \DIV_internal_op \DIV_internal_op$32 - end - sync init - end - attribute \enum_base_type "In1Sel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "RA" - attribute \enum_value_010 "RA_OR_ZERO" - attribute \enum_value_011 "SPR" - attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \DIV_in1_sel$33 - attribute \enum_base_type "In1Sel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "RA" - attribute \enum_value_010 "RA_OR_ZERO" - attribute \enum_value_011 "SPR" - attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \DIV_in1_sel$34 - attribute \enum_base_type "In1Sel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "RA" - attribute \enum_value_010 "RA_OR_ZERO" - attribute \enum_value_011 "SPR" - attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \DIV_in1_sel$35 - attribute \enum_base_type "In1Sel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "RA" - attribute \enum_value_010 "RA_OR_ZERO" - attribute \enum_value_011 "SPR" - attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \DIV_in1_sel$36 - attribute \enum_base_type "In1Sel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "RA" - attribute \enum_value_010 "RA_OR_ZERO" - attribute \enum_value_011 "SPR" - attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \DIV_in1_sel$37 - attribute \enum_base_type "In1Sel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "RA" - attribute \enum_value_010 "RA_OR_ZERO" - attribute \enum_value_011 "SPR" - attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \DIV_in1_sel$38 - attribute \enum_base_type "In1Sel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "RA" - attribute \enum_value_010 "RA_OR_ZERO" - attribute \enum_value_011 "SPR" - attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \DIV_in1_sel$39 - attribute \enum_base_type "In1Sel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "RA" - attribute \enum_value_010 "RA_OR_ZERO" - attribute \enum_value_011 "SPR" - attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \DIV_in1_sel$40 - attribute \enum_base_type "In1Sel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "RA" - attribute \enum_value_010 "RA_OR_ZERO" - attribute \enum_value_011 "SPR" - attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \DIV_in1_sel$41 - attribute \enum_base_type "In1Sel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "RA" - attribute \enum_value_010 "RA_OR_ZERO" - attribute \enum_value_011 "SPR" - attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \DIV_in1_sel$42 - attribute \enum_base_type "In1Sel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "RA" - attribute \enum_value_010 "RA_OR_ZERO" - attribute \enum_value_011 "SPR" - attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \DIV_in1_sel$43 - attribute \enum_base_type "In1Sel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "RA" - attribute \enum_value_010 "RA_OR_ZERO" - attribute \enum_value_011 "SPR" - attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \DIV_in1_sel$44 - attribute \enum_base_type "In1Sel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "RA" - attribute \enum_value_010 "RA_OR_ZERO" - attribute \enum_value_011 "SPR" - attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \DIV_in1_sel$45 - attribute \enum_base_type "In1Sel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "RA" - attribute \enum_value_010 "RA_OR_ZERO" - attribute \enum_value_011 "SPR" - attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \DIV_in1_sel$46 - attribute \enum_base_type "In1Sel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "RA" - attribute \enum_value_010 "RA_OR_ZERO" - attribute \enum_value_011 "SPR" - attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \DIV_in1_sel$47 - attribute \enum_base_type "In1Sel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "RA" - attribute \enum_value_010 "RA_OR_ZERO" - attribute \enum_value_011 "SPR" - attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \DIV_in1_sel$48 - process $group_22 - assign \DIV_in1_sel 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:315" - switch \opc_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01010 - assign \DIV_in1_sel \DIV_in1_sel$33 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'11100 - assign \DIV_in1_sel \DIV_in1_sel$34 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'00000 - assign \DIV_in1_sel \DIV_in1_sel$35 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'11010 - assign \DIV_in1_sel \DIV_in1_sel$36 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10011 - assign \DIV_in1_sel \DIV_in1_sel$37 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10110 - assign \DIV_in1_sel \DIV_in1_sel$38 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01001 - assign \DIV_in1_sel \DIV_dec_sub9_DIV_in1_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01011 - assign \DIV_in1_sel \DIV_dec_sub11_DIV_in1_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'11011 - assign \DIV_in1_sel \DIV_in1_sel$39 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01111 - assign \DIV_in1_sel \DIV_in1_sel$40 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10100 - assign \DIV_in1_sel \DIV_in1_sel$41 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10101 - assign \DIV_in1_sel \DIV_in1_sel$42 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10111 - assign \DIV_in1_sel \DIV_in1_sel$43 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10000 - assign \DIV_in1_sel \DIV_in1_sel$44 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10010 - assign \DIV_in1_sel \DIV_in1_sel$45 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01000 - assign \DIV_in1_sel \DIV_in1_sel$46 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'11000 - assign \DIV_in1_sel \DIV_in1_sel$47 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'00100 - assign \DIV_in1_sel \DIV_in1_sel$48 - end - sync init - end - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 4 \DIV_in2_sel$49 - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 4 \DIV_in2_sel$50 - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 4 \DIV_in2_sel$51 - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 4 \DIV_in2_sel$52 - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 4 \DIV_in2_sel$53 - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 4 \DIV_in2_sel$54 - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 4 \DIV_in2_sel$55 - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute 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\DIV_in2_sel$60 - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 4 \DIV_in2_sel$61 - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 4 \DIV_in2_sel$62 - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 4 \DIV_in2_sel$63 - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 4 \DIV_in2_sel$64 - process $group_23 - assign \DIV_in2_sel 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:315" - switch \opc_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01010 - assign \DIV_in2_sel \DIV_in2_sel$49 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'11100 - assign \DIV_in2_sel \DIV_in2_sel$50 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'00000 - assign \DIV_in2_sel \DIV_in2_sel$51 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'11010 - assign \DIV_in2_sel \DIV_in2_sel$52 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10011 - assign \DIV_in2_sel \DIV_in2_sel$53 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10110 - assign \DIV_in2_sel \DIV_in2_sel$54 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01001 - assign \DIV_in2_sel \DIV_dec_sub9_DIV_in2_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01011 - assign \DIV_in2_sel \DIV_dec_sub11_DIV_in2_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'11011 - assign \DIV_in2_sel \DIV_in2_sel$55 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01111 - assign \DIV_in2_sel \DIV_in2_sel$56 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10100 - assign \DIV_in2_sel \DIV_in2_sel$57 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10101 - assign \DIV_in2_sel \DIV_in2_sel$58 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10111 - assign \DIV_in2_sel \DIV_in2_sel$59 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10000 - assign \DIV_in2_sel \DIV_in2_sel$60 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10010 - assign \DIV_in2_sel \DIV_in2_sel$61 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01000 - assign \DIV_in2_sel \DIV_in2_sel$62 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'11000 - assign \DIV_in2_sel \DIV_in2_sel$63 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'00100 - assign \DIV_in2_sel \DIV_in2_sel$64 - end - sync init - end - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \DIV_cr_in$65 - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \DIV_cr_in$66 - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \DIV_cr_in$67 - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \DIV_cr_in$68 - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \DIV_cr_in$69 - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \DIV_cr_in$70 - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \DIV_cr_in$71 - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \DIV_cr_in$72 - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \DIV_cr_in$73 - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \DIV_cr_in$74 - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \DIV_cr_in$75 - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \DIV_cr_in$76 - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \DIV_cr_in$77 - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \DIV_cr_in$78 - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \DIV_cr_in$79 - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \DIV_cr_in$80 - process $group_24 - assign \DIV_cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:315" - switch \opc_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01010 - assign \DIV_cr_in \DIV_cr_in$65 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'11100 - assign \DIV_cr_in \DIV_cr_in$66 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'00000 - assign \DIV_cr_in \DIV_cr_in$67 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'11010 - assign \DIV_cr_in \DIV_cr_in$68 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10011 - assign \DIV_cr_in \DIV_cr_in$69 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10110 - assign \DIV_cr_in \DIV_cr_in$70 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01001 - assign \DIV_cr_in \DIV_dec_sub9_DIV_cr_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01011 - assign \DIV_cr_in \DIV_dec_sub11_DIV_cr_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'11011 - assign \DIV_cr_in \DIV_cr_in$71 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01111 - assign \DIV_cr_in \DIV_cr_in$72 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10100 - assign \DIV_cr_in \DIV_cr_in$73 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10101 - assign \DIV_cr_in \DIV_cr_in$74 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10111 - assign \DIV_cr_in \DIV_cr_in$75 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10000 - assign \DIV_cr_in \DIV_cr_in$76 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10010 - assign \DIV_cr_in \DIV_cr_in$77 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01000 - assign \DIV_cr_in \DIV_cr_in$78 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'11000 - assign \DIV_cr_in \DIV_cr_in$79 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'00100 - assign \DIV_cr_in \DIV_cr_in$80 - end - sync init - end - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \DIV_cr_out$81 - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \DIV_cr_out$82 - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \DIV_cr_out$83 - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \DIV_cr_out$84 - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \DIV_cr_out$85 - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \DIV_cr_out$86 - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \DIV_cr_out$87 - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \DIV_cr_out$88 - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \DIV_cr_out$89 - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \DIV_cr_out$90 - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \DIV_cr_out$91 - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \DIV_cr_out$92 - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \DIV_cr_out$93 - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \DIV_cr_out$94 - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \DIV_cr_out$95 - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \DIV_cr_out$96 - process $group_25 - assign \DIV_cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:315" - switch \opc_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01010 - assign \DIV_cr_out \DIV_cr_out$81 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'11100 - assign \DIV_cr_out \DIV_cr_out$82 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'00000 - assign \DIV_cr_out \DIV_cr_out$83 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'11010 - assign \DIV_cr_out \DIV_cr_out$84 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10011 - assign \DIV_cr_out \DIV_cr_out$85 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10110 - assign \DIV_cr_out \DIV_cr_out$86 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01001 - assign \DIV_cr_out \DIV_dec_sub9_DIV_cr_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01011 - assign \DIV_cr_out \DIV_dec_sub11_DIV_cr_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'11011 - assign \DIV_cr_out \DIV_cr_out$87 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01111 - assign \DIV_cr_out \DIV_cr_out$88 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10100 - assign \DIV_cr_out \DIV_cr_out$89 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10101 - assign \DIV_cr_out \DIV_cr_out$90 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10111 - assign \DIV_cr_out \DIV_cr_out$91 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10000 - assign \DIV_cr_out \DIV_cr_out$92 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10010 - assign \DIV_cr_out \DIV_cr_out$93 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01000 - assign \DIV_cr_out \DIV_cr_out$94 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'11000 - assign \DIV_cr_out \DIV_cr_out$95 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'00100 - assign \DIV_cr_out \DIV_cr_out$96 - end - sync init - end - attribute \enum_base_type "LdstLen" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "is1B" - attribute \enum_value_0010 "is2B" - attribute \enum_value_0100 "is4B" - attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 4 \DIV_ldst_len$97 - attribute \enum_base_type "LdstLen" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "is1B" - attribute \enum_value_0010 "is2B" - attribute \enum_value_0100 "is4B" - attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 4 \DIV_ldst_len$98 - attribute \enum_base_type "LdstLen" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "is1B" - attribute \enum_value_0010 "is2B" - attribute \enum_value_0100 "is4B" - attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 4 \DIV_ldst_len$99 - attribute \enum_base_type "LdstLen" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "is1B" - attribute \enum_value_0010 "is2B" - attribute \enum_value_0100 "is4B" - attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 4 \DIV_ldst_len$100 - attribute \enum_base_type "LdstLen" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "is1B" - attribute \enum_value_0010 "is2B" - attribute \enum_value_0100 "is4B" - attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 4 \DIV_ldst_len$101 - attribute \enum_base_type "LdstLen" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "is1B" - attribute \enum_value_0010 "is2B" - attribute \enum_value_0100 "is4B" - attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 4 \DIV_ldst_len$102 - attribute \enum_base_type "LdstLen" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "is1B" - attribute \enum_value_0010 "is2B" - attribute \enum_value_0100 "is4B" - attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 4 \DIV_ldst_len$103 - attribute \enum_base_type "LdstLen" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "is1B" - attribute \enum_value_0010 "is2B" - attribute \enum_value_0100 "is4B" - attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 4 \DIV_ldst_len$104 - attribute \enum_base_type "LdstLen" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "is1B" - attribute \enum_value_0010 "is2B" - attribute \enum_value_0100 "is4B" - attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 4 \DIV_ldst_len$105 - attribute \enum_base_type "LdstLen" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "is1B" - attribute \enum_value_0010 "is2B" - attribute \enum_value_0100 "is4B" - attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 4 \DIV_ldst_len$106 - attribute \enum_base_type "LdstLen" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "is1B" - attribute \enum_value_0010 "is2B" - attribute \enum_value_0100 "is4B" - attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 4 \DIV_ldst_len$107 - attribute \enum_base_type "LdstLen" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "is1B" - attribute \enum_value_0010 "is2B" - attribute \enum_value_0100 "is4B" - attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 4 \DIV_ldst_len$108 - attribute \enum_base_type "LdstLen" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "is1B" - attribute \enum_value_0010 "is2B" - attribute \enum_value_0100 "is4B" - attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 4 \DIV_ldst_len$109 - attribute \enum_base_type "LdstLen" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "is1B" - attribute \enum_value_0010 "is2B" - attribute \enum_value_0100 "is4B" - attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 4 \DIV_ldst_len$110 - attribute \enum_base_type "LdstLen" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "is1B" - attribute \enum_value_0010 "is2B" - attribute \enum_value_0100 "is4B" - attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 4 \DIV_ldst_len$111 - attribute \enum_base_type "LdstLen" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "is1B" - attribute \enum_value_0010 "is2B" - attribute \enum_value_0100 "is4B" - attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 4 \DIV_ldst_len$112 - process $group_26 - assign \DIV_ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:315" - switch \opc_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01010 - assign \DIV_ldst_len \DIV_ldst_len$97 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'11100 - assign \DIV_ldst_len \DIV_ldst_len$98 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'00000 - assign \DIV_ldst_len \DIV_ldst_len$99 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'11010 - assign \DIV_ldst_len \DIV_ldst_len$100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10011 - assign \DIV_ldst_len \DIV_ldst_len$101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10110 - assign \DIV_ldst_len \DIV_ldst_len$102 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01001 - assign \DIV_ldst_len \DIV_dec_sub9_DIV_ldst_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01011 - assign \DIV_ldst_len \DIV_dec_sub11_DIV_ldst_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'11011 - assign \DIV_ldst_len \DIV_ldst_len$103 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01111 - assign \DIV_ldst_len \DIV_ldst_len$104 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10100 - assign \DIV_ldst_len \DIV_ldst_len$105 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10101 - assign \DIV_ldst_len \DIV_ldst_len$106 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10111 - assign \DIV_ldst_len \DIV_ldst_len$107 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10000 - assign \DIV_ldst_len \DIV_ldst_len$108 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10010 - assign \DIV_ldst_len \DIV_ldst_len$109 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01000 - assign \DIV_ldst_len \DIV_ldst_len$110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'11000 - assign \DIV_ldst_len \DIV_ldst_len$111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'00100 - assign \DIV_ldst_len \DIV_ldst_len$112 - end - sync init - end - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 2 \DIV_rc_sel$113 - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 2 \DIV_rc_sel$114 - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 2 \DIV_rc_sel$115 - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 2 \DIV_rc_sel$116 - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 2 \DIV_rc_sel$117 - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 2 \DIV_rc_sel$118 - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 2 \DIV_rc_sel$119 - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 2 \DIV_rc_sel$120 - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 2 \DIV_rc_sel$121 - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 2 \DIV_rc_sel$122 - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 2 \DIV_rc_sel$123 - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 2 \DIV_rc_sel$124 - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 2 \DIV_rc_sel$125 - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 2 \DIV_rc_sel$126 - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 2 \DIV_rc_sel$127 - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 2 \DIV_rc_sel$128 - process $group_27 - assign \DIV_rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:315" - switch \opc_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01010 - assign \DIV_rc_sel \DIV_rc_sel$113 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'11100 - assign \DIV_rc_sel \DIV_rc_sel$114 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'00000 - assign \DIV_rc_sel \DIV_rc_sel$115 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'11010 - assign \DIV_rc_sel \DIV_rc_sel$116 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10011 - assign \DIV_rc_sel \DIV_rc_sel$117 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10110 - assign \DIV_rc_sel \DIV_rc_sel$118 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01001 - assign \DIV_rc_sel \DIV_dec_sub9_DIV_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01011 - assign \DIV_rc_sel \DIV_dec_sub11_DIV_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'11011 - assign \DIV_rc_sel \DIV_rc_sel$119 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01111 - assign \DIV_rc_sel \DIV_rc_sel$120 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10100 - assign \DIV_rc_sel \DIV_rc_sel$121 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10101 - assign \DIV_rc_sel \DIV_rc_sel$122 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10111 - assign \DIV_rc_sel \DIV_rc_sel$123 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10000 - assign \DIV_rc_sel \DIV_rc_sel$124 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10010 - assign \DIV_rc_sel \DIV_rc_sel$125 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01000 - assign \DIV_rc_sel \DIV_rc_sel$126 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'11000 - assign \DIV_rc_sel \DIV_rc_sel$127 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'00100 - assign \DIV_rc_sel \DIV_rc_sel$128 - end - sync init - end - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 2 \DIV_cry_in$129 - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 2 \DIV_cry_in$130 - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 2 \DIV_cry_in$131 - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 2 \DIV_cry_in$132 - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 2 \DIV_cry_in$133 - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 2 \DIV_cry_in$134 - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 2 \DIV_cry_in$135 - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 2 \DIV_cry_in$136 - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 2 \DIV_cry_in$137 - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 2 \DIV_cry_in$138 - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 2 \DIV_cry_in$139 - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 2 \DIV_cry_in$140 - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 2 \DIV_cry_in$141 - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 2 \DIV_cry_in$142 - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 2 \DIV_cry_in$143 - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 2 \DIV_cry_in$144 - process $group_28 - assign \DIV_cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:315" - switch \opc_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01010 - assign \DIV_cry_in \DIV_cry_in$129 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'11100 - assign \DIV_cry_in \DIV_cry_in$130 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'00000 - assign \DIV_cry_in \DIV_cry_in$131 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'11010 - assign \DIV_cry_in \DIV_cry_in$132 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10011 - assign \DIV_cry_in \DIV_cry_in$133 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10110 - assign \DIV_cry_in \DIV_cry_in$134 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01001 - assign \DIV_cry_in \DIV_dec_sub9_DIV_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01011 - assign \DIV_cry_in \DIV_dec_sub11_DIV_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'11011 - assign \DIV_cry_in \DIV_cry_in$135 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01111 - assign \DIV_cry_in \DIV_cry_in$136 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10100 - assign \DIV_cry_in \DIV_cry_in$137 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10101 - assign \DIV_cry_in \DIV_cry_in$138 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10111 - assign \DIV_cry_in \DIV_cry_in$139 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10000 - assign \DIV_cry_in \DIV_cry_in$140 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10010 - assign \DIV_cry_in \DIV_cry_in$141 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01000 - assign \DIV_cry_in \DIV_cry_in$142 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'11000 - assign \DIV_cry_in \DIV_cry_in$143 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'00100 - assign \DIV_cry_in \DIV_cry_in$144 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \DIV_inv_a$145 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \DIV_inv_a$146 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \DIV_inv_a$147 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \DIV_inv_a$148 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \DIV_inv_a$149 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \DIV_inv_a$150 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \DIV_inv_a$151 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \DIV_inv_a$152 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \DIV_inv_a$153 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \DIV_inv_a$154 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \DIV_inv_a$155 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \DIV_inv_a$156 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \DIV_inv_a$157 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \DIV_inv_a$158 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \DIV_inv_a$159 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \DIV_inv_a$160 - process $group_29 - assign \DIV_inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:315" - switch \opc_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01010 - assign \DIV_inv_a \DIV_inv_a$145 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'11100 - assign \DIV_inv_a \DIV_inv_a$146 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'00000 - assign \DIV_inv_a \DIV_inv_a$147 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'11010 - assign \DIV_inv_a \DIV_inv_a$148 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10011 - assign \DIV_inv_a \DIV_inv_a$149 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10110 - assign \DIV_inv_a \DIV_inv_a$150 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01001 - assign \DIV_inv_a \DIV_dec_sub9_DIV_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01011 - assign \DIV_inv_a \DIV_dec_sub11_DIV_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'11011 - assign \DIV_inv_a \DIV_inv_a$151 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01111 - assign \DIV_inv_a \DIV_inv_a$152 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10100 - assign \DIV_inv_a \DIV_inv_a$153 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10101 - assign \DIV_inv_a \DIV_inv_a$154 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10111 - assign \DIV_inv_a \DIV_inv_a$155 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10000 - assign \DIV_inv_a \DIV_inv_a$156 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10010 - assign \DIV_inv_a \DIV_inv_a$157 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01000 - assign \DIV_inv_a \DIV_inv_a$158 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'11000 - assign \DIV_inv_a \DIV_inv_a$159 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'00100 - assign \DIV_inv_a \DIV_inv_a$160 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \DIV_inv_out$161 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \DIV_inv_out$162 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \DIV_inv_out$163 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \DIV_inv_out$164 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \DIV_inv_out$165 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \DIV_inv_out$166 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \DIV_inv_out$167 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \DIV_inv_out$168 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \DIV_inv_out$169 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \DIV_inv_out$170 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \DIV_inv_out$171 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \DIV_inv_out$172 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \DIV_inv_out$173 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \DIV_inv_out$174 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \DIV_inv_out$175 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \DIV_inv_out$176 - process $group_30 - assign \DIV_inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:315" - switch \opc_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01010 - assign \DIV_inv_out \DIV_inv_out$161 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'11100 - assign \DIV_inv_out \DIV_inv_out$162 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'00000 - assign \DIV_inv_out \DIV_inv_out$163 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'11010 - assign \DIV_inv_out \DIV_inv_out$164 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10011 - assign \DIV_inv_out \DIV_inv_out$165 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10110 - assign \DIV_inv_out \DIV_inv_out$166 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01001 - assign \DIV_inv_out \DIV_dec_sub9_DIV_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01011 - assign \DIV_inv_out \DIV_dec_sub11_DIV_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'11011 - assign \DIV_inv_out \DIV_inv_out$167 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01111 - assign \DIV_inv_out \DIV_inv_out$168 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10100 - assign \DIV_inv_out \DIV_inv_out$169 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10101 - assign \DIV_inv_out \DIV_inv_out$170 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10111 - assign \DIV_inv_out \DIV_inv_out$171 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10000 - assign \DIV_inv_out \DIV_inv_out$172 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10010 - assign \DIV_inv_out \DIV_inv_out$173 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01000 - assign \DIV_inv_out \DIV_inv_out$174 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'11000 - assign \DIV_inv_out \DIV_inv_out$175 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'00100 - assign \DIV_inv_out \DIV_inv_out$176 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \DIV_cry_out$177 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \DIV_cry_out$178 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \DIV_cry_out$179 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \DIV_cry_out$180 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \DIV_cry_out$181 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \DIV_cry_out$182 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \DIV_cry_out$183 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \DIV_cry_out$184 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \DIV_cry_out$185 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \DIV_cry_out$186 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \DIV_cry_out$187 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \DIV_cry_out$188 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \DIV_cry_out$189 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \DIV_cry_out$190 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \DIV_cry_out$191 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \DIV_cry_out$192 - process $group_31 - assign \DIV_cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:315" - switch \opc_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01010 - assign \DIV_cry_out \DIV_cry_out$177 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'11100 - assign \DIV_cry_out \DIV_cry_out$178 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'00000 - assign \DIV_cry_out \DIV_cry_out$179 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'11010 - assign \DIV_cry_out \DIV_cry_out$180 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10011 - assign \DIV_cry_out \DIV_cry_out$181 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10110 - assign \DIV_cry_out \DIV_cry_out$182 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01001 - assign \DIV_cry_out \DIV_dec_sub9_DIV_cry_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01011 - assign \DIV_cry_out \DIV_dec_sub11_DIV_cry_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'11011 - assign \DIV_cry_out \DIV_cry_out$183 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01111 - assign \DIV_cry_out \DIV_cry_out$184 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10100 - assign \DIV_cry_out \DIV_cry_out$185 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10101 - assign \DIV_cry_out \DIV_cry_out$186 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10111 - assign \DIV_cry_out \DIV_cry_out$187 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10000 - assign \DIV_cry_out \DIV_cry_out$188 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10010 - assign \DIV_cry_out \DIV_cry_out$189 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01000 - assign \DIV_cry_out \DIV_cry_out$190 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'11000 - assign \DIV_cry_out \DIV_cry_out$191 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'00100 - assign \DIV_cry_out \DIV_cry_out$192 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \DIV_is_32b$193 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \DIV_is_32b$194 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \DIV_is_32b$195 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \DIV_is_32b$196 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \DIV_is_32b$197 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \DIV_is_32b$198 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \DIV_is_32b$199 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \DIV_is_32b$200 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \DIV_is_32b$201 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \DIV_is_32b$202 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \DIV_is_32b$203 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \DIV_is_32b$204 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \DIV_is_32b$205 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \DIV_is_32b$206 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \DIV_is_32b$207 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \DIV_is_32b$208 - process $group_32 - assign \DIV_is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:315" - switch \opc_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01010 - assign \DIV_is_32b \DIV_is_32b$193 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'11100 - assign \DIV_is_32b \DIV_is_32b$194 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'00000 - assign \DIV_is_32b \DIV_is_32b$195 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'11010 - assign \DIV_is_32b \DIV_is_32b$196 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10011 - assign \DIV_is_32b \DIV_is_32b$197 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10110 - assign \DIV_is_32b \DIV_is_32b$198 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01001 - assign \DIV_is_32b \DIV_dec_sub9_DIV_is_32b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01011 - assign \DIV_is_32b \DIV_dec_sub11_DIV_is_32b - attribute \src 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"TRAP" - attribute \enum_value_00100000000 "MUL" - attribute \enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 11 \DIV_dec31_DIV_function_unit - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute 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attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \DIV_dec31_DIV_cr_out - attribute \enum_base_type "LdstLen" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "is1B" - attribute \enum_value_0010 "is2B" - attribute \enum_value_0100 "is4B" - attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 4 \DIV_dec31_DIV_ldst_len - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 2 \DIV_dec31_DIV_rc_sel - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 2 \DIV_dec31_DIV_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \DIV_dec31_DIV_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \DIV_dec31_DIV_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \DIV_dec31_DIV_cry_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \DIV_dec31_DIV_is_32b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \DIV_dec31_DIV_sgn - cell \DIV_dec31 \DIV_dec31 - connect \opcode_in \DIV_dec31_opcode_in - connect \DIV_function_unit \DIV_dec31_DIV_function_unit - connect \DIV_internal_op \DIV_dec31_DIV_internal_op - connect \DIV_in1_sel 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attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'111010 - assign \DIV_internal_op \DIV_internal_op$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'111110 - assign \DIV_internal_op \DIV_internal_op$8 - end - sync init - end - attribute \enum_base_type "In1Sel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "RA" - attribute \enum_value_010 "RA_OR_ZERO" - attribute \enum_value_011 "SPR" - attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \DIV_in1_sel$9 - attribute \enum_base_type "In1Sel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "RA" - attribute \enum_value_010 "RA_OR_ZERO" - attribute \enum_value_011 "SPR" - attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \DIV_in1_sel$10 - attribute \enum_base_type "In1Sel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "RA" - attribute \enum_value_010 "RA_OR_ZERO" - attribute \enum_value_011 "SPR" - attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \DIV_in1_sel$11 - attribute \enum_base_type "In1Sel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "RA" - attribute \enum_value_010 "RA_OR_ZERO" - attribute \enum_value_011 "SPR" - attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \DIV_in1_sel$12 - process $group_8 - assign \DIV_in1_sel 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'010011 - assign \DIV_in1_sel \DIV_in1_sel$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'011110 - assign \DIV_in1_sel \DIV_in1_sel$10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'011111 - assign \DIV_in1_sel \DIV_dec31_DIV_in1_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'111010 - assign \DIV_in1_sel \DIV_in1_sel$11 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'111110 - assign \DIV_in1_sel \DIV_in1_sel$12 - end - sync init - end - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 4 \DIV_in2_sel$13 - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 4 \DIV_in2_sel$14 - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 4 \DIV_in2_sel$15 - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 4 \DIV_in2_sel$16 - process $group_9 - assign \DIV_in2_sel 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'010011 - assign \DIV_in2_sel \DIV_in2_sel$13 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'011110 - assign \DIV_in2_sel \DIV_in2_sel$14 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'011111 - assign \DIV_in2_sel \DIV_dec31_DIV_in2_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'111010 - assign \DIV_in2_sel \DIV_in2_sel$15 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'111110 - assign \DIV_in2_sel \DIV_in2_sel$16 - end - sync init - end - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \DIV_cr_in$17 - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \DIV_cr_in$18 - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \DIV_cr_in$19 - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \DIV_cr_in$20 - process $group_10 - assign \DIV_cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'010011 - assign \DIV_cr_in \DIV_cr_in$17 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'011110 - assign \DIV_cr_in \DIV_cr_in$18 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'011111 - assign \DIV_cr_in \DIV_dec31_DIV_cr_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'111010 - assign \DIV_cr_in \DIV_cr_in$19 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'111110 - assign \DIV_cr_in \DIV_cr_in$20 - end - sync init - end - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \DIV_cr_out$21 - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \DIV_cr_out$22 - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \DIV_cr_out$23 - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \DIV_cr_out$24 - process $group_11 - assign \DIV_cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'010011 - assign \DIV_cr_out \DIV_cr_out$21 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'011110 - assign \DIV_cr_out \DIV_cr_out$22 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'011111 - assign \DIV_cr_out \DIV_dec31_DIV_cr_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'111010 - assign \DIV_cr_out \DIV_cr_out$23 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'111110 - assign \DIV_cr_out \DIV_cr_out$24 - end - sync init - end - attribute \enum_base_type "LdstLen" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "is1B" - attribute \enum_value_0010 "is2B" - attribute \enum_value_0100 "is4B" - attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 4 \DIV_ldst_len$25 - attribute \enum_base_type "LdstLen" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "is1B" - attribute \enum_value_0010 "is2B" - attribute \enum_value_0100 "is4B" - attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 4 \DIV_ldst_len$26 - attribute \enum_base_type "LdstLen" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "is1B" - attribute \enum_value_0010 "is2B" - attribute \enum_value_0100 "is4B" - attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 4 \DIV_ldst_len$27 - attribute \enum_base_type "LdstLen" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "is1B" - attribute \enum_value_0010 "is2B" - attribute \enum_value_0100 "is4B" - attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 4 \DIV_ldst_len$28 - process $group_12 - assign \DIV_ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'010011 - assign \DIV_ldst_len \DIV_ldst_len$25 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'011110 - assign \DIV_ldst_len \DIV_ldst_len$26 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'011111 - assign \DIV_ldst_len \DIV_dec31_DIV_ldst_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'111010 - assign \DIV_ldst_len \DIV_ldst_len$27 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'111110 - assign \DIV_ldst_len \DIV_ldst_len$28 - end - sync init - end - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 2 \DIV_rc_sel$29 - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 2 \DIV_rc_sel$30 - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 2 \DIV_rc_sel$31 - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 2 \DIV_rc_sel$32 - process $group_13 - assign \DIV_rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'010011 - assign \DIV_rc_sel \DIV_rc_sel$29 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'011110 - assign \DIV_rc_sel \DIV_rc_sel$30 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'011111 - assign \DIV_rc_sel \DIV_dec31_DIV_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'111010 - assign \DIV_rc_sel \DIV_rc_sel$31 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'111110 - assign \DIV_rc_sel \DIV_rc_sel$32 - end - sync init - end - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 2 \DIV_cry_in$33 - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 2 \DIV_cry_in$34 - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 2 \DIV_cry_in$35 - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 2 \DIV_cry_in$36 - process $group_14 - assign \DIV_cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'010011 - assign \DIV_cry_in \DIV_cry_in$33 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'011110 - assign \DIV_cry_in \DIV_cry_in$34 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'011111 - assign \DIV_cry_in \DIV_dec31_DIV_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'111010 - assign \DIV_cry_in \DIV_cry_in$35 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'111110 - assign \DIV_cry_in \DIV_cry_in$36 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \DIV_inv_a$37 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \DIV_inv_a$38 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \DIV_inv_a$39 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \DIV_inv_a$40 - process $group_15 - assign \DIV_inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'010011 - assign \DIV_inv_a \DIV_inv_a$37 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'011110 - assign \DIV_inv_a \DIV_inv_a$38 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'011111 - assign \DIV_inv_a \DIV_dec31_DIV_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'111010 - assign \DIV_inv_a \DIV_inv_a$39 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'111110 - assign \DIV_inv_a \DIV_inv_a$40 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \DIV_inv_out$41 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \DIV_inv_out$42 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \DIV_inv_out$43 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \DIV_inv_out$44 - process $group_16 - assign \DIV_inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'010011 - assign \DIV_inv_out \DIV_inv_out$41 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'011110 - assign \DIV_inv_out \DIV_inv_out$42 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'011111 - assign \DIV_inv_out \DIV_dec31_DIV_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'111010 - assign \DIV_inv_out \DIV_inv_out$43 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'111110 - assign \DIV_inv_out \DIV_inv_out$44 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \DIV_cry_out$45 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \DIV_cry_out$46 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \DIV_cry_out$47 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \DIV_cry_out$48 - process $group_17 - assign \DIV_cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'010011 - assign \DIV_cry_out \DIV_cry_out$45 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'011110 - assign \DIV_cry_out \DIV_cry_out$46 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'011111 - assign \DIV_cry_out \DIV_dec31_DIV_cry_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'111010 - assign \DIV_cry_out \DIV_cry_out$47 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'111110 - assign \DIV_cry_out \DIV_cry_out$48 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \DIV_is_32b$49 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \DIV_is_32b$50 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \DIV_is_32b$51 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \DIV_is_32b$52 - process $group_18 - assign \DIV_is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'010011 - assign \DIV_is_32b \DIV_is_32b$49 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'011110 - assign \DIV_is_32b \DIV_is_32b$50 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'011111 - assign \DIV_is_32b \DIV_dec31_DIV_is_32b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'111010 - assign \DIV_is_32b \DIV_is_32b$51 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'111110 - assign \DIV_is_32b \DIV_is_32b$52 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \DIV_sgn$53 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \DIV_sgn$54 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \DIV_sgn$55 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \DIV_sgn$56 - process $group_19 - assign \DIV_sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'010011 - assign \DIV_sgn \DIV_sgn$53 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'011110 - assign \DIV_sgn \DIV_sgn$54 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'011111 - assign \DIV_sgn \DIV_dec31_DIV_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'111010 - assign \DIV_sgn \DIV_sgn$55 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'111110 - assign \DIV_sgn \DIV_sgn$56 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:308" - wire width 32 \opcode_switch$57 - process $group_20 - assign \opcode_switch$57 32'00000000000000000000000000000000 - assign \opcode_switch$57 \opcode_in - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:418" - wire width 32 $58 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:418" - cell $mux $59 - parameter \WIDTH 32 - connect \A \raw_opcode_in - connect \B { \raw_opcode_in [7:0] \raw_opcode_in [15:8] \raw_opcode_in [23:16] \raw_opcode_in [31:24] } - connect \S \bigendian - connect \Y $58 - end - process $group_21 - assign \opcode_in 32'00000000000000000000000000000000 - assign \opcode_in $58 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 5 \DIV_RS - process $group_22 - assign \DIV_RS 5'00000 - assign \DIV_RS { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 5 \DIV_RT - process $group_23 - assign \DIV_RT 5'00000 - assign \DIV_RT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - process $group_24 - assign \DIV_RA 5'00000 - assign \DIV_RA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 5 \DIV_RB - process $group_25 - assign \DIV_RB 5'00000 - assign \DIV_RB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - process $group_26 - assign \DIV_SI 16'0000000000000000 - assign \DIV_SI { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] \opcode_in [0] } - sync init - end - process $group_27 - assign \DIV_UI 16'0000000000000000 - assign \DIV_UI { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] \opcode_in [0] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 1 \DIV_L - process $group_28 - assign \DIV_L 1'0 - assign \DIV_L { \opcode_in [21] } - sync init - end - process $group_29 - assign \DIV_SH32 5'00000 - assign \DIV_SH32 { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - process $group_30 - assign \DIV_sh 6'000000 - assign \DIV_sh { \opcode_in [1] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 5 \DIV_MB32 - process $group_31 - assign \DIV_MB32 5'00000 - assign \DIV_MB32 { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 5 \DIV_ME32 - process $group_32 - assign \DIV_ME32 5'00000 - assign \DIV_ME32 { \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] } - sync init - end - process $group_33 - assign \DIV_LI 24'000000000000000000000000 - assign \DIV_LI { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 1 \DIV_LK - process $group_34 - assign \DIV_LK 1'0 - assign \DIV_LK { \opcode_in [0] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 1 \DIV_AA - process $group_35 - assign \DIV_AA 1'0 - assign \DIV_AA { \opcode_in [1] } - sync init - end - process $group_36 - assign \DIV_Rc 1'0 - assign \DIV_Rc { \opcode_in [0] } - sync init - end - process $group_37 - assign \DIV_OE 1'0 - assign \DIV_OE { \opcode_in [10] } - sync init - end - process $group_38 - assign \DIV_BD 14'00000000000000 - assign \DIV_BD { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 3 \DIV_BF - process $group_39 - assign \DIV_BF 3'000 - assign \DIV_BF { \opcode_in [25] \opcode_in [24] \opcode_in [23] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 10 \DIV_CR - process $group_40 - assign \DIV_CR 10'0000000000 - assign \DIV_CR { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] } - sync init - end - process $group_41 - assign \DIV_BB 5'00000 - assign \DIV_BB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - process $group_42 - assign \DIV_BA 5'00000 - assign \DIV_BA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - process $group_43 - assign \DIV_BT 5'00000 - assign \DIV_BT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - process $group_44 - assign \DIV_FXM 8'00000000 - assign \DIV_FXM { \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 5 \DIV_BO - process $group_45 - assign \DIV_BO 5'00000 - assign \DIV_BO { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - process $group_46 - assign \DIV_BI 5'00000 - assign \DIV_BI { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 2 \DIV_BH - process $group_47 - assign \DIV_BH 2'00 - assign \DIV_BH { \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 16 \DIV_D - process $group_48 - assign \DIV_D 16'0000000000000000 - assign \DIV_D { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] \opcode_in [0] } - sync init - end - process $group_49 - assign \DIV_DS 14'00000000000000 - assign \DIV_DS { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 5 \DIV_TO - process $group_50 - assign \DIV_TO 5'00000 - assign \DIV_TO { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - process $group_51 - assign \DIV_BC 5'00000 - assign \DIV_BC { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 5 \DIV_SH - process $group_52 - assign \DIV_SH 5'00000 - assign \DIV_SH { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 5 \DIV_ME - process $group_53 - assign \DIV_ME 5'00000 - assign \DIV_ME { \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 5 \DIV_MB - process $group_54 - assign \DIV_MB 5'00000 - assign \DIV_MB { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 10 \DIV_SPR - process $group_55 - assign \DIV_SPR 10'0000000000 - assign \DIV_SPR { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \X_A - process $group_56 - assign \X_A 1'0 - assign \X_A { \opcode_in [25] } - sync init - end - process $group_57 - assign \X_BF 3'000 - assign \X_BF { \opcode_in [25] \opcode_in [24] \opcode_in [23] } - sync init - end - process $group_58 - assign \X_BFA 3'000 - assign \X_BFA { \opcode_in [20] \opcode_in [19] \opcode_in [18] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \X_BO - process $group_59 - assign \X_BO 5'00000 - assign \X_BO { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 4 \X_CT - process $group_60 - assign \X_CT 4'0000 - assign \X_CT { \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 7 \X_DCMX - process $group_61 - assign \X_DCMX 7'0000000 - assign \X_DCMX { \opcode_in [22] \opcode_in [21] \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 3 \X_DRM - process $group_62 - assign \X_DRM 3'000 - assign \X_DRM { \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \X_E - process $group_63 - assign \X_E 1'0 - assign \X_E { \opcode_in [15] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 4 \X_E_1 - process $group_64 - assign \X_E_1 4'0000 - assign \X_E_1 { \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 2 \X_EO - process $group_65 - assign \X_EO 2'00 - assign \X_EO { \opcode_in [20] \opcode_in [19] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \X_EO_1 - process $group_66 - assign \X_EO_1 5'00000 - assign \X_EO_1 { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \X_EX - process $group_67 - assign \X_EX 1'0 - assign \X_EX { \opcode_in [0] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \X_FC - process $group_68 - assign \X_FC 5'00000 - assign \X_FC { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \X_FRA - process $group_69 - assign \X_FRA 5'00000 - assign \X_FRA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \X_FRAp - process $group_70 - assign \X_FRAp 5'00000 - assign \X_FRAp { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \X_FRB - process $group_71 - assign \X_FRB 5'00000 - assign \X_FRB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \X_FRBp - process $group_72 - assign \X_FRBp 5'00000 - assign \X_FRBp { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \X_FRS - process $group_73 - assign \X_FRS 5'00000 - assign \X_FRS { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \X_FRSp - process $group_74 - assign \X_FRSp 5'00000 - assign \X_FRSp { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \X_FRT - process $group_75 - assign \X_FRT 5'00000 - assign \X_FRT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \X_FRTp - process $group_76 - assign \X_FRTp 5'00000 - assign \X_FRTp { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 3 \X_IH - process $group_77 - assign \X_IH 3'000 - assign \X_IH { \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 8 \X_IMM8 - process $group_78 - assign \X_IMM8 8'00000000 - assign \X_IMM8 { \opcode_in [18] \opcode_in [17] \opcode_in [16] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 2 \X_L2 - process $group_79 - assign \X_L2 2'00 - assign \X_L2 { \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \X_L - process $group_80 - assign \X_L 1'0 - assign \X_L { \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \X_L1 - process $group_81 - assign \X_L1 1'0 - assign \X_L1 { \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 2 \X_L3 - process $group_82 - assign \X_L3 2'00 - assign \X_L3 { \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \X_MO - process $group_83 - assign \X_MO 5'00000 - assign \X_MO { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \X_NB - process $group_84 - assign \X_NB 5'00000 - assign \X_NB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \X_PRS - process $group_85 - assign \X_PRS 1'0 - assign \X_PRS { \opcode_in [17] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \X_R - process $group_86 - assign \X_R 1'0 - assign \X_R { \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \X_R_1 - process $group_87 - assign \X_R_1 1'0 - assign \X_R_1 { \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \X_RA - process $group_88 - assign \X_RA 5'00000 - assign \X_RA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \X_RB - process $group_89 - assign \X_RB 5'00000 - assign \X_RB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \X_Rc - process $group_90 - assign \X_Rc 1'0 - assign \X_Rc { \opcode_in [0] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 2 \X_RIC - process $group_91 - assign \X_RIC 2'00 - assign \X_RIC { \opcode_in [19] \opcode_in [18] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 2 \X_RM - process $group_92 - assign \X_RM 2'00 - assign \X_RM { \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \X_RO - process $group_93 - assign \X_RO 1'0 - assign \X_RO { \opcode_in [0] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \X_RS - process $group_94 - assign \X_RS 5'00000 - assign \X_RS { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \X_RSp - process $group_95 - assign \X_RSp 5'00000 - assign \X_RSp { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \X_RT - process $group_96 - assign \X_RT 5'00000 - assign \X_RT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \X_RTp - process $group_97 - assign \X_RTp 5'00000 - assign \X_RTp { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \X_S - process $group_98 - assign \X_S 5'00000 - assign \X_S { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \X_SH - process $group_99 - assign \X_SH 5'00000 - assign \X_SH { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \X_SI - process $group_100 - assign \X_SI 5'00000 - assign \X_SI { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 2 \X_SP - process $group_101 - assign \X_SP 2'00 - assign \X_SP { \opcode_in [20] \opcode_in [19] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 4 \X_SR - process $group_102 - assign \X_SR 4'0000 - assign \X_SR { \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \X_SX - process $group_103 - assign \X_SX 1'0 - assign \X_SX { \opcode_in [0] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 6 \X_SX_S - process $group_104 - assign \X_SX_S 6'000000 - assign \X_SX_S { \opcode_in [0] \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \X_T - process $group_105 - assign \X_T 5'00000 - assign \X_T { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 10 \X_TBR - process $group_106 - assign \X_TBR 10'0000000000 - assign \X_TBR { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \X_TH - process $group_107 - assign \X_TH 5'00000 - assign \X_TH { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \X_TO - process $group_108 - assign \X_TO 5'00000 - assign \X_TO { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \X_TX - process $group_109 - assign \X_TX 1'0 - assign \X_TX { \opcode_in [0] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 6 \X_TX_T - process $group_110 - assign \X_TX_T 6'000000 - assign \X_TX_T { \opcode_in [0] \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 4 \X_U - process $group_111 - assign \X_U 4'0000 - assign \X_U { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \X_UIM - process $group_112 - assign \X_UIM 5'00000 - assign \X_UIM { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \X_VRS - process $group_113 - assign \X_VRS 5'00000 - assign \X_VRS { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \X_VRT - process $group_114 - assign \X_VRT 5'00000 - assign \X_VRT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \X_W - process $group_115 - assign \X_W 1'0 - assign \X_W { \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 2 \X_WC - process $group_116 - assign \X_WC 2'00 - assign \X_WC { \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 10 \X_XO - process $group_117 - assign \X_XO 10'0000000000 - assign \X_XO { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 8 \X_XO_1 - process $group_118 - assign \X_XO_1 8'00000000 - assign \X_XO_1 { \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \B_AA - process $group_119 - assign \B_AA 1'0 - assign \B_AA { \opcode_in [1] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 14 \B_BD - process $group_120 - assign \B_BD 14'00000000000000 - assign \B_BD { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \B_BI - process $group_121 - assign \B_BI 5'00000 - assign \B_BI { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \B_BO - process $group_122 - assign \B_BO 5'00000 - assign \B_BO { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \B_LK - process $group_123 - assign \B_LK 1'0 - assign \B_LK { \opcode_in [0] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \I_AA - process $group_124 - assign \I_AA 1'0 - assign \I_AA { \opcode_in [1] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 24 \I_LI - process $group_125 - assign \I_LI 24'000000000000000000000000 - assign \I_LI { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \I_LK - process $group_126 - assign \I_LK 1'0 - assign \I_LK { \opcode_in [0] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \XX3_AX - process $group_127 - assign \XX3_AX 1'0 - assign \XX3_AX { \opcode_in [2] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \XX3_A - process $group_128 - assign \XX3_A 5'00000 - assign \XX3_A { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 6 \XX3_AX_A - process $group_129 - assign \XX3_AX_A 6'000000 - assign \XX3_AX_A { \opcode_in [2] \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 3 \XX3_BF - process $group_130 - assign \XX3_BF 3'000 - assign \XX3_BF { \opcode_in [25] \opcode_in [24] \opcode_in [23] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \XX3_BX - process $group_131 - assign \XX3_BX 1'0 - assign \XX3_BX { \opcode_in [1] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \XX3_B - process $group_132 - assign \XX3_B 5'00000 - assign \XX3_B { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 6 \XX3_BX_B - process $group_133 - assign \XX3_BX_B 6'000000 - assign \XX3_BX_B { \opcode_in [1] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 2 \XX3_DM - process $group_134 - assign \XX3_DM 2'00 - assign \XX3_DM { \opcode_in [9] \opcode_in [8] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \XX3_Rc - process $group_135 - assign \XX3_Rc 1'0 - assign \XX3_Rc { \opcode_in [10] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 2 \XX3_SHW - process $group_136 - assign \XX3_SHW 2'00 - assign \XX3_SHW { \opcode_in [9] \opcode_in [8] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \XX3_TX - process $group_137 - assign \XX3_TX 1'0 - assign \XX3_TX { \opcode_in [0] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \XX3_T - process $group_138 - assign \XX3_T 5'00000 - assign \XX3_T { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 6 \XX3_TX_T - process $group_139 - assign \XX3_TX_T 6'000000 - assign \XX3_TX_T { \opcode_in [0] \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 4 \XX3_XO - process $group_140 - assign \XX3_XO 4'0000 - assign \XX3_XO { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 8 \XX3_XO_1 - process $group_141 - assign \XX3_XO_1 8'00000000 - assign \XX3_XO_1 { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 9 \XX3_XO_2 - process $group_142 - assign \XX3_XO_2 9'000000000 - assign \XX3_XO_2 { \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \XX4_AX - process $group_143 - assign \XX4_AX 1'0 - assign \XX4_AX { \opcode_in [2] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \XX4_A - process $group_144 - assign \XX4_A 5'00000 - assign \XX4_A { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 6 \XX4_AX_A - process $group_145 - assign \XX4_AX_A 6'000000 - assign \XX4_AX_A { \opcode_in [2] \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \XX4_BX - process $group_146 - assign \XX4_BX 1'0 - assign \XX4_BX { \opcode_in [1] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \XX4_B - process $group_147 - assign \XX4_B 5'00000 - assign \XX4_B { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 6 \XX4_BX_B - process $group_148 - assign \XX4_BX_B 6'000000 - assign \XX4_BX_B { \opcode_in [1] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \XX4_CX - process $group_149 - assign \XX4_CX 1'0 - assign \XX4_CX { \opcode_in [3] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \XX4_C - process $group_150 - assign \XX4_C 5'00000 - assign \XX4_C { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 6 \XX4_CX_C - process $group_151 - assign \XX4_CX_C 6'000000 - assign \XX4_CX_C { \opcode_in [3] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \XX4_TX - process $group_152 - assign \XX4_TX 1'0 - assign \XX4_TX { \opcode_in [0] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \XX4_T - process $group_153 - assign \XX4_T 5'00000 - assign \XX4_T { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 6 \XX4_TX_T - process $group_154 - assign \XX4_TX_T 6'000000 - assign \XX4_TX_T { \opcode_in [0] \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 2 \XX4_XO - process $group_155 - assign \XX4_XO 2'00 - assign \XX4_XO { \opcode_in [5] \opcode_in [4] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \XL_BA - process $group_156 - assign \XL_BA 5'00000 - assign \XL_BA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \XL_BB - process $group_157 - assign \XL_BB 5'00000 - assign \XL_BB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 3 \XL_BF - process $group_158 - assign \XL_BF 3'000 - assign \XL_BF { \opcode_in [25] \opcode_in [24] \opcode_in [23] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 3 \XL_BFA - process $group_159 - assign \XL_BFA 3'000 - assign \XL_BFA { \opcode_in [20] \opcode_in [19] \opcode_in [18] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 2 \XL_BH - process $group_160 - assign \XL_BH 2'00 - assign \XL_BH { \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \XL_BI - process $group_161 - assign \XL_BI 5'00000 - assign \XL_BI { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \XL_BO - process $group_162 - assign \XL_BO 5'00000 - assign \XL_BO { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \XL_BO_1 - process $group_163 - assign \XL_BO_1 5'00000 - assign \XL_BO_1 { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - process $group_164 - assign \XL_BT 5'00000 - assign \XL_BT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \XL_LK - process $group_165 - assign \XL_LK 1'0 - assign \XL_LK { \opcode_in [0] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 15 \XL_OC - process $group_166 - assign \XL_OC 15'000000000000000 - assign \XL_OC { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \XL_S - process $group_167 - assign \XL_S 1'0 - assign \XL_S { \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 10 \XL_XO - process $group_168 - assign \XL_XO 10'0000000000 - assign \XL_XO { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \A_BC - process $group_169 - assign \A_BC 5'00000 - assign \A_BC { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \A_FRA - process $group_170 - assign \A_FRA 5'00000 - assign \A_FRA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \A_FRB - process $group_171 - assign \A_FRB 5'00000 - assign \A_FRB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \A_FRC - process $group_172 - assign \A_FRC 5'00000 - assign \A_FRC { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \A_FRT - process $group_173 - assign \A_FRT 5'00000 - assign \A_FRT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \A_RA - process $group_174 - assign \A_RA 5'00000 - assign \A_RA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \A_RB - process $group_175 - assign \A_RB 5'00000 - assign \A_RB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \A_Rc - process $group_176 - assign \A_Rc 1'0 - assign \A_Rc { \opcode_in [0] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \A_RT - process $group_177 - assign \A_RT 5'00000 - assign \A_RT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \A_XO - process $group_178 - assign \A_XO 5'00000 - assign \A_XO { \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 3 \D_BF - process $group_179 - assign \D_BF 3'000 - assign \D_BF { \opcode_in [25] \opcode_in [24] \opcode_in [23] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 16 \D_D - process $group_180 - assign \D_D 16'0000000000000000 - assign \D_D { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] \opcode_in [0] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \D_FRS - process $group_181 - assign \D_FRS 5'00000 - assign \D_FRS { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \D_FRT - process $group_182 - assign \D_FRT 5'00000 - assign \D_FRT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \D_L - process $group_183 - assign \D_L 1'0 - assign \D_L { \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \D_RA - process $group_184 - assign \D_RA 5'00000 - assign \D_RA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \D_RS - process $group_185 - assign \D_RS 5'00000 - assign \D_RS { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \D_RT - process $group_186 - assign \D_RT 5'00000 - assign \D_RT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 16 \D_SI - process $group_187 - assign \D_SI 16'0000000000000000 - assign \D_SI { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] \opcode_in [0] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \D_TO - process $group_188 - assign \D_TO 5'00000 - assign \D_TO { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 16 \D_UI - process $group_189 - assign \D_UI 16'0000000000000000 - assign \D_UI { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] \opcode_in [0] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 3 \XX2_BF - process $group_190 - assign \XX2_BF 3'000 - assign \XX2_BF { \opcode_in [25] \opcode_in [24] \opcode_in [23] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \XX2_BX - process $group_191 - assign \XX2_BX 1'0 - assign \XX2_BX { \opcode_in [1] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \XX2_B - process $group_192 - assign \XX2_B 5'00000 - assign \XX2_B { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 6 \XX2_BX_B - process $group_193 - assign \XX2_BX_B 6'000000 - assign \XX2_BX_B { \opcode_in [1] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \XX2_dc - process $group_194 - assign \XX2_dc 1'0 - assign \XX2_dc { \opcode_in [6] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \XX2_dm - process $group_195 - assign \XX2_dm 1'0 - assign \XX2_dm { \opcode_in [2] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \XX2_dx - process $group_196 - assign \XX2_dx 5'00000 - assign \XX2_dx { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 7 \XX2_dc_dm_dx - process $group_197 - assign \XX2_dc_dm_dx 7'0000000 - assign \XX2_dc_dm_dx { \opcode_in [6] \opcode_in [2] \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 7 \XX2_DCMX - process $group_198 - assign \XX2_DCMX 7'0000000 - assign \XX2_DCMX { \opcode_in [22] \opcode_in [21] \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \XX2_EO - process $group_199 - assign \XX2_EO 5'00000 - assign \XX2_EO { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \XX2_RT - process $group_200 - assign \XX2_RT 5'00000 - assign \XX2_RT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \XX2_TX - process $group_201 - assign \XX2_TX 1'0 - assign \XX2_TX { \opcode_in [0] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \XX2_T - process $group_202 - assign \XX2_T 5'00000 - assign \XX2_T { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 6 \XX2_TX_T - process $group_203 - assign \XX2_TX_T 6'000000 - assign \XX2_TX_T { \opcode_in [0] \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 4 \XX2_UIM - process $group_204 - assign \XX2_UIM 4'0000 - assign \XX2_UIM { \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 2 \XX2_UIM_1 - process $group_205 - assign \XX2_UIM_1 2'00 - assign \XX2_UIM_1 { \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 7 \XX2_XO - process $group_206 - assign \XX2_XO 7'0000000 - assign \XX2_XO { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [5] \opcode_in [4] \opcode_in [3] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 9 \XX2_XO_1 - process $group_207 - assign \XX2_XO_1 9'000000000 - assign \XX2_XO_1 { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 3 \Z22_BF - process $group_208 - assign \Z22_BF 3'000 - assign \Z22_BF { \opcode_in [25] \opcode_in [24] \opcode_in [23] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 6 \Z22_DCM - process $group_209 - assign \Z22_DCM 6'000000 - assign \Z22_DCM { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 6 \Z22_DGM - process $group_210 - assign \Z22_DGM 6'000000 - assign \Z22_DGM { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \Z22_FRA - process $group_211 - assign \Z22_FRA 5'00000 - assign \Z22_FRA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \Z22_FRAp - process $group_212 - assign \Z22_FRAp 5'00000 - assign \Z22_FRAp { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \Z22_FRT - process $group_213 - assign \Z22_FRT 5'00000 - assign \Z22_FRT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \Z22_FRTp - process $group_214 - assign \Z22_FRTp 5'00000 - assign \Z22_FRTp { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \Z22_Rc - process $group_215 - assign \Z22_Rc 1'0 - assign \Z22_Rc { \opcode_in [0] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 6 \Z22_SH - process $group_216 - assign \Z22_SH 6'000000 - assign \Z22_SH { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 9 \Z22_XO - process $group_217 - assign \Z22_XO 9'000000000 - assign \Z22_XO { \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 3 \EVS_BFA - process $group_218 - assign \EVS_BFA 3'000 - assign \EVS_BFA { \opcode_in [2] \opcode_in [1] \opcode_in [0] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 10 \XFX_BHRBE - process $group_219 - assign \XFX_BHRBE 10'0000000000 - assign \XFX_BHRBE { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \XFX_DUI - process $group_220 - assign \XFX_DUI 5'00000 - assign \XFX_DUI { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 10 \XFX_DUIS - process $group_221 - assign \XFX_DUIS 10'0000000000 - assign \XFX_DUIS { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 8 \XFX_FXM - process $group_222 - assign \XFX_FXM 8'00000000 - assign \XFX_FXM { \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \XFX_RS - process $group_223 - assign \XFX_RS 5'00000 - assign \XFX_RS { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \XFX_RT - process $group_224 - assign \XFX_RT 5'00000 - assign \XFX_RT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 10 \XFX_SPR - process $group_225 - assign \XFX_SPR 10'0000000000 - assign \XFX_SPR { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 10 \XFX_XO - process $group_226 - assign \XFX_XO 10'0000000000 - assign \XFX_XO { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 10 \DX_d0 - process $group_227 - assign \DX_d0 10'0000000000 - assign \DX_d0 { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \DX_d1 - process $group_228 - assign \DX_d1 5'00000 - assign \DX_d1 { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \DX_d2 - process $group_229 - assign \DX_d2 1'0 - assign \DX_d2 { \opcode_in [0] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 16 \DX_d0_d1_d2 - process $group_230 - assign \DX_d0_d1_d2 16'0000000000000000 - assign \DX_d0_d1_d2 { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] \opcode_in [0] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \DX_RT - process $group_231 - assign \DX_RT 5'00000 - assign \DX_RT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \DX_XO - process $group_232 - assign \DX_XO 5'00000 - assign \DX_XO { \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 12 \DQ_DQ - process $group_233 - assign \DQ_DQ 12'000000000000 - assign \DQ_DQ { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 4 \DQ_PT - process $group_234 - assign \DQ_PT 4'0000 - assign \DQ_PT { \opcode_in [3] \opcode_in [2] \opcode_in [1] \opcode_in [0] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \DQ_RA - process $group_235 - assign \DQ_RA 5'00000 - assign \DQ_RA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \DQ_RTp - process $group_236 - assign \DQ_RTp 5'00000 - assign \DQ_RTp { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \DQ_SX - process $group_237 - assign \DQ_SX 1'0 - assign \DQ_SX { \opcode_in [3] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \DQ_S - process $group_238 - assign \DQ_S 5'00000 - assign \DQ_S { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 6 \DQ_SX_S - process $group_239 - assign \DQ_SX_S 6'000000 - assign \DQ_SX_S { \opcode_in [3] \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \DQ_TX - process $group_240 - assign \DQ_TX 1'0 - assign \DQ_TX { \opcode_in [3] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \DQ_T - process $group_241 - assign \DQ_T 5'00000 - assign \DQ_T { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 6 \DQ_TX_T - process $group_242 - assign \DQ_TX_T 6'000000 - assign \DQ_TX_T { \opcode_in [3] \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 3 \DQ_XO - process $group_243 - assign \DQ_XO 3'000 - assign \DQ_XO { \opcode_in [2] \opcode_in [1] \opcode_in [0] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 14 \DS_DS - process $group_244 - assign \DS_DS 14'00000000000000 - assign \DS_DS { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \DS_FRSp - process $group_245 - assign \DS_FRSp 5'00000 - assign \DS_FRSp { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \DS_FRTp - process $group_246 - assign \DS_FRTp 5'00000 - assign \DS_FRTp { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \DS_RA - process $group_247 - assign \DS_RA 5'00000 - assign \DS_RA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \DS_RS - process $group_248 - assign \DS_RS 5'00000 - assign \DS_RS { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \DS_RSp - process $group_249 - assign \DS_RSp 5'00000 - assign \DS_RSp { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \DS_RT - process $group_250 - assign \DS_RT 5'00000 - assign \DS_RT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \DS_VRS - process $group_251 - assign \DS_VRS 5'00000 - assign \DS_VRS { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \DS_VRT - process $group_252 - assign \DS_VRT 5'00000 - assign \DS_VRT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 2 \DS_XO - process $group_253 - assign \DS_XO 2'00 - assign \DS_XO { \opcode_in [1] \opcode_in [0] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \VX_EO - process $group_254 - assign \VX_EO 5'00000 - assign \VX_EO { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \VX_PS - process $group_255 - assign \VX_PS 1'0 - assign \VX_PS { \opcode_in [9] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \VX_RA - process $group_256 - assign \VX_RA 5'00000 - assign \VX_RA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \VX_RT - process $group_257 - assign \VX_RT 5'00000 - assign \VX_RT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \VX_SIM - process $group_258 - assign \VX_SIM 5'00000 - assign \VX_SIM { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \VX_UIM - process $group_259 - assign \VX_UIM 5'00000 - assign \VX_UIM { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 4 \VX_UIM_1 - process $group_260 - assign \VX_UIM_1 4'0000 - assign \VX_UIM_1 { \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 3 \VX_UIM_2 - process $group_261 - assign \VX_UIM_2 3'000 - assign \VX_UIM_2 { \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 2 \VX_UIM_3 - process $group_262 - assign \VX_UIM_3 2'00 - assign \VX_UIM_3 { \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \VX_VRA - process $group_263 - assign \VX_VRA 5'00000 - assign \VX_VRA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \VX_VRB - process $group_264 - assign \VX_VRB 5'00000 - assign \VX_VRB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \VX_VRT - process $group_265 - assign \VX_VRT 5'00000 - assign \VX_VRT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 10 \VX_XO - process $group_266 - assign \VX_XO 10'0000000000 - assign \VX_XO { \opcode_in [10] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] \opcode_in [0] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 11 \VX_XO_1 - process $group_267 - assign \VX_XO_1 11'00000000000 - assign \VX_XO_1 { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] \opcode_in [0] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 8 \XFL_FLM - process $group_268 - assign \XFL_FLM 8'00000000 - assign \XFL_FLM { \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \XFL_FRB - process $group_269 - assign \XFL_FRB 5'00000 - assign \XFL_FRB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \XFL_L - process $group_270 - assign \XFL_L 1'0 - assign \XFL_L { \opcode_in [25] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \XFL_Rc - process $group_271 - assign \XFL_Rc 1'0 - assign \XFL_Rc { \opcode_in [0] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \XFL_W - process $group_272 - assign \XFL_W 1'0 - assign \XFL_W { \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 10 \XFL_XO - process $group_273 - assign \XFL_XO 10'0000000000 - assign \XFL_XO { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \Z23_FRA - process $group_274 - assign \Z23_FRA 5'00000 - assign \Z23_FRA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \Z23_FRAp - process $group_275 - assign \Z23_FRAp 5'00000 - assign \Z23_FRAp { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \Z23_FRB - process $group_276 - assign \Z23_FRB 5'00000 - assign \Z23_FRB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \Z23_FRBp - process $group_277 - assign \Z23_FRBp 5'00000 - assign \Z23_FRBp { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \Z23_FRT - process $group_278 - assign \Z23_FRT 5'00000 - assign \Z23_FRT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \Z23_FRTp - process $group_279 - assign \Z23_FRTp 5'00000 - assign \Z23_FRTp { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \Z23_R - process $group_280 - assign \Z23_R 1'0 - assign \Z23_R { \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \Z23_Rc - process $group_281 - assign \Z23_Rc 1'0 - assign \Z23_Rc { \opcode_in [0] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 2 \Z23_RMC - process $group_282 - assign \Z23_RMC 2'00 - assign \Z23_RMC { \opcode_in [10] \opcode_in [9] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \Z23_TE - process $group_283 - assign \Z23_TE 5'00000 - assign \Z23_TE { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 8 \Z23_XO - process $group_284 - assign \Z23_XO 8'00000000 - assign \Z23_XO { \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \MDS_IB - process $group_285 - assign \MDS_IB 5'00000 - assign \MDS_IB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \MDS_IS - process $group_286 - assign \MDS_IS 5'00000 - assign \MDS_IS { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 6 \MDS_mb - process $group_287 - assign \MDS_mb 6'000000 - assign \MDS_mb { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 6 \MDS_me - process $group_288 - assign \MDS_me 6'000000 - assign \MDS_me { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \MDS_RA - process $group_289 - assign \MDS_RA 5'00000 - assign \MDS_RA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \MDS_RB - process $group_290 - assign \MDS_RB 5'00000 - assign \MDS_RB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \MDS_Rc - process $group_291 - assign \MDS_Rc 1'0 - assign \MDS_Rc { \opcode_in [0] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \MDS_RS - process $group_292 - assign \MDS_RS 5'00000 - assign \MDS_RS { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 4 \MDS_XBI - process $group_293 - assign \MDS_XBI 4'0000 - assign \MDS_XBI { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 4 \MDS_XBI_1 - process $group_294 - assign \MDS_XBI_1 4'0000 - assign \MDS_XBI_1 { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 4 \MDS_XO - process $group_295 - assign \MDS_XO 4'0000 - assign \MDS_XO { \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 7 \SC_LEV - process $group_296 - assign \SC_LEV 7'0000000 - assign \SC_LEV { \opcode_in [11] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \SC_XO - process $group_297 - assign \SC_XO 1'0 - assign \SC_XO { \opcode_in [1] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 2 \SC_XO_1 - process $group_298 - assign \SC_XO_1 2'00 - assign \SC_XO_1 { \opcode_in [1] \opcode_in [0] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \M_MB - process $group_299 - assign \M_MB 5'00000 - assign \M_MB { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \M_ME - process $group_300 - assign \M_ME 5'00000 - assign \M_ME { \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \M_RA - process $group_301 - assign \M_RA 5'00000 - assign \M_RA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \M_RB - process $group_302 - assign \M_RB 5'00000 - assign \M_RB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \M_Rc - process $group_303 - assign \M_Rc 1'0 - assign \M_Rc { \opcode_in [0] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \M_RS - process $group_304 - assign \M_RS 5'00000 - assign \M_RS { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \M_SH - process $group_305 - assign \M_SH 5'00000 - assign \M_SH { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 6 \MD_mb - process $group_306 - assign \MD_mb 6'000000 - assign \MD_mb { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 6 \MD_me - process $group_307 - assign \MD_me 6'000000 - assign \MD_me { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \MD_RA - process $group_308 - assign \MD_RA 5'00000 - assign \MD_RA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \MD_Rc - process $group_309 - assign \MD_Rc 1'0 - assign \MD_Rc { \opcode_in [0] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \MD_RS - process $group_310 - assign \MD_RS 5'00000 - assign \MD_RS { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 6 \MD_sh - process $group_311 - assign \MD_sh 6'000000 - assign \MD_sh { \opcode_in [1] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 3 \MD_XO - process $group_312 - assign \MD_XO 3'000 - assign \MD_XO { \opcode_in [4] \opcode_in [3] \opcode_in [2] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 6 \all_OPCD - process $group_313 - assign \all_OPCD 6'000000 - assign \all_OPCD { \opcode_in [31] \opcode_in [30] \opcode_in [29] \opcode_in [28] \opcode_in [27] \opcode_in [26] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 6 \all_PO - process $group_314 - assign \all_PO 6'000000 - assign \all_PO { \opcode_in [31] \opcode_in [30] \opcode_in [29] \opcode_in [28] \opcode_in [27] \opcode_in [26] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \XO_OE - process $group_315 - assign \XO_OE 1'0 - assign \XO_OE { \opcode_in [10] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \XO_RA - process $group_316 - assign \XO_RA 5'00000 - assign \XO_RA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \XO_RB - process $group_317 - assign \XO_RB 5'00000 - assign \XO_RB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \XO_Rc - process $group_318 - assign \XO_Rc 1'0 - assign \XO_Rc { \opcode_in [0] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \XO_RT - process $group_319 - assign \XO_RT 5'00000 - assign \XO_RT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 9 \XO_XO - process $group_320 - assign \XO_XO 9'000000000 - assign \XO_XO { \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \DQE_RA - process $group_321 - assign \DQE_RA 5'00000 - assign \DQE_RA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \DQE_RT - process $group_322 - assign \DQE_RT 5'00000 - assign \DQE_RT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 2 \DQE_XO - process $group_323 - assign \DQE_XO 2'00 - assign \DQE_XO { \opcode_in [1] \opcode_in [0] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \TX_RA - process $group_324 - assign \TX_RA 5'00000 - assign \TX_RA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \TX_UI - process $group_325 - assign \TX_UI 5'00000 - assign \TX_UI { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 4 \TX_XBI - process $group_326 - assign \TX_XBI 4'0000 - assign \TX_XBI { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 6 \TX_XO - process $group_327 - assign \TX_XO 6'000000 - assign \TX_XO { \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \VA_RA - process $group_328 - assign \VA_RA 5'00000 - assign \VA_RA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \VA_RB - process $group_329 - assign \VA_RB 5'00000 - assign \VA_RB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \VA_RC - process $group_330 - assign \VA_RC 5'00000 - assign \VA_RC { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \VA_RT - process $group_331 - assign \VA_RT 5'00000 - assign \VA_RT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 4 \VA_SHB - process $group_332 - assign \VA_SHB 4'0000 - assign \VA_SHB { \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \VA_VRA - process $group_333 - assign \VA_VRA 5'00000 - assign \VA_VRA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \VA_VRB - process $group_334 - assign \VA_VRB 5'00000 - assign \VA_VRB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \VA_VRC - process $group_335 - assign \VA_VRC 5'00000 - assign \VA_VRC { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \VA_VRT - process $group_336 - assign \VA_VRT 5'00000 - assign \VA_VRT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 6 \VA_XO - process $group_337 - assign \VA_XO 6'000000 - assign \VA_XO { \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] \opcode_in [0] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \XS_RA - process $group_338 - assign \XS_RA 5'00000 - assign \XS_RA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \XS_Rc - process $group_339 - assign \XS_Rc 1'0 - assign \XS_Rc { \opcode_in [0] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \XS_RS - process $group_340 - assign \XS_RS 5'00000 - assign \XS_RS { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 6 \XS_sh - process $group_341 - assign \XS_sh 6'000000 - assign \XS_sh { \opcode_in [1] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 9 \XS_XO - process $group_342 - assign \XS_XO 9'000000000 - assign \XS_XO { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \VC_Rc - process $group_343 - assign \VC_Rc 1'0 - assign \VC_Rc { \opcode_in [10] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \VC_VRA - process $group_344 - assign \VC_VRA 5'00000 - assign \VC_VRA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \VC_VRB - process $group_345 - assign \VC_VRB 5'00000 - assign \VC_VRB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \VC_VRT - process $group_346 - assign \VC_VRT 5'00000 - assign \VC_VRT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 10 \VC_XO - process $group_347 - assign \VC_XO 10'0000000000 - assign \VC_XO { \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] \opcode_in [0] } - sync init - end - connect \DIV_function_unit$1 11'00000000000 - connect \DIV_function_unit$2 11'00000000000 - connect \DIV_function_unit$3 11'00000000000 - connect \DIV_function_unit$4 11'00000000000 - connect \DIV_internal_op$5 7'0000000 - connect \DIV_internal_op$6 7'0000000 - connect \DIV_internal_op$7 7'0000000 - connect \DIV_internal_op$8 7'0000000 - connect \DIV_in1_sel$9 3'000 - connect \DIV_in1_sel$10 3'000 - connect \DIV_in1_sel$11 3'000 - connect \DIV_in1_sel$12 3'000 - connect \DIV_in2_sel$13 4'0000 - connect \DIV_in2_sel$14 4'0000 - connect \DIV_in2_sel$15 4'0000 - connect \DIV_in2_sel$16 4'0000 - connect \DIV_cr_in$17 3'000 - connect \DIV_cr_in$18 3'000 - connect \DIV_cr_in$19 3'000 - connect \DIV_cr_in$20 3'000 - connect \DIV_cr_out$21 3'000 - connect \DIV_cr_out$22 3'000 - connect \DIV_cr_out$23 3'000 - connect \DIV_cr_out$24 3'000 - connect \DIV_ldst_len$25 4'0000 - connect \DIV_ldst_len$26 4'0000 - connect \DIV_ldst_len$27 4'0000 - connect \DIV_ldst_len$28 4'0000 - connect \DIV_rc_sel$29 2'00 - connect \DIV_rc_sel$30 2'00 - connect \DIV_rc_sel$31 2'00 - connect \DIV_rc_sel$32 2'00 - connect \DIV_cry_in$33 2'00 - connect \DIV_cry_in$34 2'00 - connect \DIV_cry_in$35 2'00 - connect \DIV_cry_in$36 2'00 - connect \DIV_inv_a$37 1'0 - connect \DIV_inv_a$38 1'0 - connect \DIV_inv_a$39 1'0 - connect \DIV_inv_a$40 1'0 - connect \DIV_inv_out$41 1'0 - connect \DIV_inv_out$42 1'0 - connect \DIV_inv_out$43 1'0 - connect \DIV_inv_out$44 1'0 - connect \DIV_cry_out$45 1'0 - connect \DIV_cry_out$46 1'0 - connect \DIV_cry_out$47 1'0 - connect \DIV_cry_out$48 1'0 - connect \DIV_is_32b$49 1'0 - connect \DIV_is_32b$50 1'0 - connect \DIV_is_32b$51 1'0 - connect \DIV_is_32b$52 1'0 - connect \DIV_sgn$53 1'0 - connect \DIV_sgn$54 1'0 - connect \DIV_sgn$55 1'0 - connect \DIV_sgn$56 1'0 -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.dec_DIV.dec_rc" -module \dec_rc$169 - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:404" - wire width 2 input 0 \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 1 \rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 2 \rc_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 1 input 3 \DIV_Rc - process $group_0 - assign \rc 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:413" - switch \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:414" - attribute \nmigen.decoding "RC/2" - case 2'10 - assign \rc \DIV_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:417" - attribute \nmigen.decoding "ONE/1" - case 2'01 - assign \rc 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:420" - attribute \nmigen.decoding "NONE/0" - case 2'00 - assign \rc 1'0 - end - sync init - end - process $group_1 - assign \rc_ok 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:413" - switch \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:414" - attribute \nmigen.decoding "RC/2" - case 2'10 - assign \rc_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:417" - attribute \nmigen.decoding "ONE/1" - case 2'01 - assign \rc_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:420" - attribute \nmigen.decoding "NONE/0" - case 2'00 - assign \rc_ok 1'1 - end - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.dec_DIV.dec_oe" -module \dec_oe$170 - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:441" - wire width 2 input 0 \sel_in - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 7 input 1 \DIV_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 2 \oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 3 \oe_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 1 input 4 \DIV_OE - process $group_0 - assign \oe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:450" - switch \DIV_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:461" - attribute \nmigen.decoding "OP_MUL_H64/51|OP_MUL_H32/52|OP_EXTS/31|OP_CNTZ/14|OP_SHL/60|OP_SHR/61|OP_RLC/56|OP_LOAD/37|OP_STORE/38|OP_RLCL/57|OP_RLCR/58|OP_EXTSWSLI/32" - case 7'0110011, 7'0110100, 7'0011111, 7'0001110, 7'0111100, 7'0111101, 7'0111000, 7'0100101, 7'0100110, 7'0111001, 7'0111010, 7'0100000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:465" - attribute \nmigen.decoding "" - case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:467" - switch \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:468" - attribute \nmigen.decoding "RC/2" - case 2'10 - assign \oe \DIV_OE - end - end - sync init - end - process $group_1 - assign \oe_ok 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:450" - switch \DIV_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:461" - attribute \nmigen.decoding "OP_MUL_H64/51|OP_MUL_H32/52|OP_EXTS/31|OP_CNTZ/14|OP_SHL/60|OP_SHR/61|OP_RLC/56|OP_LOAD/37|OP_STORE/38|OP_RLCL/57|OP_RLCR/58|OP_EXTSWSLI/32" - case 7'0110011, 7'0110100, 7'0011111, 7'0001110, 7'0111100, 7'0111101, 7'0111000, 7'0100101, 7'0100110, 7'0111001, 7'0111010, 7'0100000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:465" - attribute \nmigen.decoding "" - case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:467" - switch \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:468" - attribute \nmigen.decoding "RC/2" - case 2'10 - assign \oe_ok 1'1 - end - end - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.dec_DIV.dec_cr_in.ppick" -module \ppick$172 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" - wire width 8 input 0 \i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" - wire width 8 output 1 \o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:49" - wire width 8 \ni - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" - wire width 8 $1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" - cell $not $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \Y_WIDTH 8 - connect \A { \i [0] \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] } - connect \Y $1 - end - process $group_0 - assign \ni 8'00000000 - assign \ni $1 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire width 1 \t0 - process $group_1 - assign \t0 1'0 - assign \t0 \i [7] - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire width 1 \t1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire width 1 $3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire width 1 $4 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_bool $5 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A { \i [7] \ni [1] } - connect \Y $4 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $6 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $4 - connect \Y $3 - end - process $group_2 - assign \t1 1'0 - assign \t1 $3 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire width 1 \t2 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire width 1 $7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire width 1 $8 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_bool $9 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A { \i [6] \i [7] \ni [2] } - connect \Y $8 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $10 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $8 - connect \Y $7 - end - process $group_3 - assign \t2 1'0 - assign \t2 $7 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire width 1 \t3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire width 1 $11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire width 1 $12 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_bool $13 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A { \i [5] \i [6] \i [7] \ni [3] } - connect \Y $12 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $14 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $12 - connect \Y $11 - end - process $group_4 - assign \t3 1'0 - assign \t3 $11 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire width 1 \t4 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire width 1 $15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire width 1 $16 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_bool $17 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A { \i [4] \i [5] \i [6] \i [7] \ni [4] } - connect \Y $16 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $18 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $16 - connect \Y $15 - end - process $group_5 - assign \t4 1'0 - assign \t4 $15 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire width 1 \t5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire width 1 $19 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire width 1 $20 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_bool $21 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \Y_WIDTH 1 - connect \A { \i [3] \i [4] \i [5] \i [6] \i [7] \ni [5] } - connect \Y $20 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $22 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $20 - connect \Y $19 - end - process $group_6 - assign \t5 1'0 - assign \t5 $19 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire width 1 \t6 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire width 1 $23 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire width 1 $24 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_bool $25 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A { \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [6] } - connect \Y $24 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $26 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $24 - connect \Y $23 - end - process $group_7 - assign \t6 1'0 - assign \t6 $23 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire width 1 \t7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire width 1 $27 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire width 1 $28 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_bool $29 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A { \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [7] } - connect \Y $28 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $30 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $28 - connect \Y $27 - end - process $group_8 - assign \t7 1'0 - assign \t7 $27 - sync init - end - process $group_9 - assign \o 8'00000000 - assign \o { \t0 \t1 \t2 \t3 \t4 \t5 \t6 \t7 } - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" - wire width 1 \en_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" - wire width 1 $31 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" - cell $reduce_bool $32 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \o - connect \Y $31 - end - process $group_10 - assign \en_o 1'0 - assign \en_o $31 - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.dec_DIV.dec_cr_in" -module \dec_cr_in$171 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:485" - wire width 32 input 0 \insn_in - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:484" - wire width 3 input 1 \sel_in - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 7 input 2 \DIV_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 5 input 3 \DIV_BB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 5 input 4 \DIV_BA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 5 input 5 \DIV_BT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 8 input 6 \DIV_FXM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 5 input 7 \DIV_BI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 5 input 8 \DIV_BC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 3 input 9 \X_BFA - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" - wire width 8 \ppick_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" - wire width 8 \ppick_o - cell \ppick$172 \ppick - connect \i \ppick_i - connect \o \ppick_o - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \cr_bitfield_ok - process $group_0 - assign \cr_bitfield_ok 1'0 - assign \cr_bitfield_ok 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" - switch \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" - attribute \nmigen.decoding "NONE/0" - case 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:505" - attribute \nmigen.decoding "CR0/1" - case 3'001 - assign \cr_bitfield_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:508" - attribute \nmigen.decoding "BI/2" - case 3'010 - assign \cr_bitfield_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:511" - attribute \nmigen.decoding "BFA/3" - case 3'011 - assign \cr_bitfield_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:514" - attribute \nmigen.decoding "BA_BB/4" - case 3'100 - assign \cr_bitfield_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:521" - attribute \nmigen.decoding "BC/5" - case 3'101 - assign \cr_bitfield_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:524" - attribute \nmigen.decoding "WHOLE_REG/6" - case 3'110 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \cr_bitfield_b_ok - process $group_1 - assign \cr_bitfield_b_ok 1'0 - assign \cr_bitfield_b_ok 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" - switch \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" - attribute \nmigen.decoding "NONE/0" - case 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:505" - attribute \nmigen.decoding "CR0/1" - case 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:508" - attribute \nmigen.decoding "BI/2" - case 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:511" - attribute \nmigen.decoding "BFA/3" - case 3'011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:514" - attribute \nmigen.decoding "BA_BB/4" - case 3'100 - assign \cr_bitfield_b_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:521" - attribute \nmigen.decoding "BC/5" - case 3'101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:524" - attribute \nmigen.decoding "WHOLE_REG/6" - case 3'110 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \cr_fxm_ok - process $group_2 - assign \cr_fxm_ok 1'0 - assign \cr_fxm_ok 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" - switch \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" - attribute \nmigen.decoding "NONE/0" - case 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:505" - attribute \nmigen.decoding "CR0/1" - case 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:508" - attribute \nmigen.decoding "BI/2" - case 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:511" - attribute \nmigen.decoding "BFA/3" - case 3'011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:514" - attribute \nmigen.decoding "BA_BB/4" - case 3'100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:521" - attribute \nmigen.decoding "BC/5" - case 3'101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:524" - attribute \nmigen.decoding "WHOLE_REG/6" - case 3'110 - assign \cr_fxm_ok 1'1 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 3 \cr_bitfield - process $group_3 - assign \cr_bitfield 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" - switch \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" - attribute \nmigen.decoding "NONE/0" - case 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:505" - attribute \nmigen.decoding "CR0/1" - case 3'001 - assign \cr_bitfield 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:508" - attribute \nmigen.decoding "BI/2" - case 3'010 - assign \cr_bitfield \DIV_BI [4:2] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:511" - attribute \nmigen.decoding "BFA/3" - case 3'011 - assign \cr_bitfield \X_BFA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:514" - attribute \nmigen.decoding "BA_BB/4" - case 3'100 - assign \cr_bitfield \DIV_BA [4:2] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:521" - attribute \nmigen.decoding "BC/5" - case 3'101 - assign \cr_bitfield \DIV_BC [4:2] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:524" - attribute \nmigen.decoding "WHOLE_REG/6" - case 3'110 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 3 \cr_bitfield_b - process $group_4 - assign \cr_bitfield_b 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" - switch \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" - attribute \nmigen.decoding "NONE/0" - case 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:505" - attribute \nmigen.decoding "CR0/1" - case 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:508" - attribute \nmigen.decoding "BI/2" - case 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:511" - attribute \nmigen.decoding "BFA/3" - case 3'011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:514" - attribute \nmigen.decoding "BA_BB/4" - case 3'100 - assign \cr_bitfield_b \DIV_BB [4:2] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:521" - attribute \nmigen.decoding "BC/5" - case 3'101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:524" - attribute \nmigen.decoding "WHOLE_REG/6" - case 3'110 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 3 \cr_bitfield_o - process $group_5 - assign \cr_bitfield_o 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" - switch \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" - attribute \nmigen.decoding "NONE/0" - case 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:505" - attribute \nmigen.decoding "CR0/1" - case 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:508" - attribute \nmigen.decoding "BI/2" - case 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:511" - attribute \nmigen.decoding "BFA/3" - case 3'011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:514" - attribute \nmigen.decoding "BA_BB/4" - case 3'100 - assign \cr_bitfield_o \DIV_BT [4:2] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:521" - attribute \nmigen.decoding "BC/5" - case 3'101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:524" - attribute \nmigen.decoding "WHOLE_REG/6" - case 3'110 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \cr_bitfield_o_ok - process $group_6 - assign \cr_bitfield_o_ok 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" - switch \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" - attribute \nmigen.decoding "NONE/0" - case 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:505" - attribute \nmigen.decoding "CR0/1" - case 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:508" - attribute \nmigen.decoding "BI/2" - case 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:511" - attribute \nmigen.decoding "BFA/3" - case 3'011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:514" - attribute \nmigen.decoding "BA_BB/4" - case 3'100 - assign \cr_bitfield_o_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:521" - attribute \nmigen.decoding "BC/5" - case 3'101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:524" - attribute \nmigen.decoding "WHOLE_REG/6" - case 3'110 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:526" - wire width 1 \move_one - process $group_7 - assign \move_one 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" - switch \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" - attribute \nmigen.decoding "NONE/0" - case 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:505" - attribute \nmigen.decoding "CR0/1" - case 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:508" - attribute \nmigen.decoding "BI/2" - case 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:511" - attribute \nmigen.decoding "BFA/3" - case 3'011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:514" - attribute \nmigen.decoding "BA_BB/4" - case 3'100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:521" - attribute \nmigen.decoding "BC/5" - case 3'101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:524" - attribute \nmigen.decoding "WHOLE_REG/6" - case 3'110 - assign \move_one \insn_in [20] - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" - cell $eq $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A \DIV_internal_op - connect \B 7'0101101 - connect \Y $1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" - wire width 1 $3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" - cell $and $4 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $1 - connect \B \move_one - connect \Y $3 - end - process $group_8 - assign \ppick_i 8'00000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" - switch \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" - attribute \nmigen.decoding "NONE/0" - case 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:505" - attribute \nmigen.decoding "CR0/1" - case 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:508" - attribute \nmigen.decoding "BI/2" - case 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:511" - attribute \nmigen.decoding "BFA/3" - case 3'011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:514" - attribute \nmigen.decoding "BA_BB/4" - case 3'100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:521" - attribute \nmigen.decoding "BC/5" - case 3'101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:524" - attribute \nmigen.decoding "WHOLE_REG/6" - case 3'110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" - switch { $3 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" - case 1'1 - assign \ppick_i \DIV_FXM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532" - case - end - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 8 \cr_fxm - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" - wire width 1 $5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" - cell $eq $6 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A \DIV_internal_op - connect \B 7'0101101 - connect \Y $5 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" - wire width 1 $7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" - cell $and $8 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $5 - connect \B \move_one - connect \Y $7 - end - process $group_9 - assign \cr_fxm 8'00000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" - switch \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" - attribute \nmigen.decoding "NONE/0" - case 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:505" - attribute \nmigen.decoding "CR0/1" - case 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:508" - attribute \nmigen.decoding "BI/2" - case 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:511" - attribute \nmigen.decoding "BFA/3" - case 3'011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:514" - attribute \nmigen.decoding "BA_BB/4" - case 3'100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:521" - attribute \nmigen.decoding "BC/5" - case 3'101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:524" - attribute \nmigen.decoding "WHOLE_REG/6" - case 3'110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" - switch { $7 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" - case 1'1 - assign \cr_fxm \ppick_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532" - case - assign \cr_fxm 8'11111111 - end - end - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.dec_DIV.dec_cr_out.ppick" -module \ppick$174 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" - wire width 8 input 0 \i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" - wire width 1 output 1 \en_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" - wire width 8 output 2 \o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:49" - wire width 8 \ni - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" - wire width 8 $1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" - cell $not $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \Y_WIDTH 8 - connect \A { \i [0] \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] } - connect \Y $1 - end - process $group_0 - assign \ni 8'00000000 - assign \ni $1 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire width 1 \t0 - process $group_1 - assign \t0 1'0 - assign \t0 \i [7] - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire width 1 \t1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire width 1 $3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire width 1 $4 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_bool $5 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A { \i [7] \ni [1] } - connect \Y $4 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $6 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $4 - connect \Y $3 - end - process $group_2 - assign \t1 1'0 - assign \t1 $3 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire width 1 \t2 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire width 1 $7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire width 1 $8 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_bool $9 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A { \i [6] \i [7] \ni [2] } - connect \Y $8 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $10 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $8 - connect \Y $7 - end - process $group_3 - assign \t2 1'0 - assign \t2 $7 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire width 1 \t3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire width 1 $11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire width 1 $12 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_bool $13 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A { \i [5] \i [6] \i [7] \ni [3] } - connect \Y $12 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $14 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $12 - connect \Y $11 - end - process $group_4 - assign \t3 1'0 - assign \t3 $11 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire width 1 \t4 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire width 1 $15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire width 1 $16 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_bool $17 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A { \i [4] \i [5] \i [6] \i [7] \ni [4] } - connect \Y $16 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $18 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $16 - connect \Y $15 - end - process $group_5 - assign \t4 1'0 - assign \t4 $15 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire width 1 \t5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire width 1 $19 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire width 1 $20 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_bool $21 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \Y_WIDTH 1 - connect \A { \i [3] \i [4] \i [5] \i [6] \i [7] \ni [5] } - connect \Y $20 - end - attribute \src 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"/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" - wire width 1 $31 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" - cell $reduce_bool $32 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \o - connect \Y $31 - end - process $group_10 - assign \en_o 1'0 - assign \en_o $31 - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.dec_DIV.dec_cr_out" -module \dec_cr_out$173 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:550" - wire width 32 input 0 \insn_in - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:549" - wire width 3 input 1 \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:548" - wire width 1 input 2 \rc_in - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute 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\enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 7 input 3 \DIV_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 4 \cr_bitfield_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 8 input 5 \DIV_FXM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 3 input 6 \X_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 input 7 \XL_BT - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" - wire width 8 \ppick_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" - wire width 1 \ppick_en_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" - wire width 8 \ppick_o - cell \ppick$174 \ppick - connect \i \ppick_i - connect \en_o \ppick_en_o - connect \o \ppick_o - end - process $group_0 - assign \cr_bitfield_ok 1'0 - assign \cr_bitfield_ok 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:563" - switch \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:564" - attribute \nmigen.decoding "NONE/0" - case 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:566" - attribute \nmigen.decoding "CR0/1" - case 3'001 - assign \cr_bitfield_ok \rc_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:569" - attribute \nmigen.decoding "BF/2" - case 3'010 - assign \cr_bitfield_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:572" - attribute \nmigen.decoding "BT/3" - case 3'011 - assign \cr_bitfield_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:575" - attribute \nmigen.decoding "WHOLE_REG/4" - case 3'100 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \cr_fxm_ok - process $group_1 - assign \cr_fxm_ok 1'0 - assign \cr_fxm_ok 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:563" - switch \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:564" - attribute \nmigen.decoding "NONE/0" - case 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:566" - attribute \nmigen.decoding "CR0/1" - case 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:569" - attribute \nmigen.decoding "BF/2" - case 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:572" - attribute \nmigen.decoding "BT/3" - case 3'011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:575" - attribute \nmigen.decoding "WHOLE_REG/4" - case 3'100 - assign \cr_fxm_ok 1'1 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 3 \cr_bitfield - process $group_2 - assign \cr_bitfield 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:563" - switch \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:564" - attribute \nmigen.decoding "NONE/0" - case 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:566" - attribute \nmigen.decoding "CR0/1" - case 3'001 - assign \cr_bitfield 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:569" - attribute \nmigen.decoding "BF/2" - case 3'010 - assign \cr_bitfield \X_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:572" - attribute \nmigen.decoding "BT/3" - case 3'011 - assign \cr_bitfield \XL_BT [4:2] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:575" - attribute \nmigen.decoding "WHOLE_REG/4" - case 3'100 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:577" - wire width 1 \move_one - process $group_3 - assign \move_one 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:563" - switch \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:564" - attribute \nmigen.decoding "NONE/0" - case 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:566" - attribute \nmigen.decoding "CR0/1" - case 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:569" - attribute \nmigen.decoding "BF/2" - case 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:572" - attribute \nmigen.decoding "BT/3" - case 3'011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:575" - attribute \nmigen.decoding "WHOLE_REG/4" - case 3'100 - assign \move_one \insn_in [20] - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:579" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:579" - cell $eq $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A \DIV_internal_op - connect \B 7'0110000 - connect \Y $1 - end - process $group_4 - assign \ppick_i 8'00000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:563" - switch \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:564" - attribute \nmigen.decoding "NONE/0" - case 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:566" - attribute \nmigen.decoding "CR0/1" - case 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:569" - attribute \nmigen.decoding "BF/2" - case 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:572" - attribute \nmigen.decoding "BT/3" - case 3'011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:575" - attribute \nmigen.decoding "WHOLE_REG/4" - case 3'100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:579" - switch { $1 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:579" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:580" - switch { \move_one } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:580" - case 1'1 - assign \ppick_i \DIV_FXM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:587" - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:589" - case - end - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 8 \cr_fxm - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:579" - wire width 1 $3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:579" - cell $eq $4 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A \DIV_internal_op - connect \B 7'0110000 - connect \Y $3 - end - process $group_5 - assign \cr_fxm 8'00000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:563" - switch \sel_in - attribute \src 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"/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:580" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:583" - switch { \ppick_en_o } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:583" - case 1'1 - assign \cr_fxm \ppick_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:585" - case - assign \cr_fxm 8'00000001 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:587" - case - assign \cr_fxm \DIV_FXM - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:589" - case - assign \cr_fxm 8'11111111 - end - end - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.dec_DIV.dec_ai" -module \dec_ai$175 - attribute \enum_base_type "In1Sel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "RA" - attribute \enum_value_010 "RA_OR_ZERO" - attribute \enum_value_011 "SPR" - attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:148" - wire width 3 input 0 \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:149" - wire width 1 output 1 \immz_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 5 input 2 \DIV_RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:156" - wire width 5 \ra - process $group_0 - assign \ra 5'00000 - assign \ra \DIV_RA - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:158" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:158" - cell $eq $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \sel_in - connect \B 3'010 - connect \Y $1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:158" - wire width 1 $3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:158" - cell $eq $4 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \ra - connect \B 5'00000 - connect \Y $3 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:158" - wire width 1 $5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:158" - cell $and $6 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $1 - connect \B $3 - connect \Y $5 - end - process $group_1 - assign \immz_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:158" - switch { $5 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:158" - case 1'1 - assign \immz_out 1'1 - end - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.dec_DIV.dec_bi" -module \dec_bi$176 - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:216" - wire width 4 input 0 \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 output 1 \imm_b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 2 \imm_b_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 16 input 3 \DIV_SI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 16 input 4 \DIV_UI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 5 input 5 \DIV_SH32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 6 input 6 \DIV_sh - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 24 input 7 \DIV_LI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 14 input 8 \DIV_BD - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 14 input 9 \DIV_DS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 64 $1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - cell $pos $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 16 - parameter \Y_WIDTH 64 - connect \A \DIV_UI - connect \Y $1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:229" - wire width 16 \si - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:234" - wire width 32 \si_hi - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:241" - wire width 64 $3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:239" - wire width 16 \ui - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:241" - wire width 47 $4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:241" - cell $sshl $5 - parameter \A_SIGNED 0 - parameter \A_WIDTH 16 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 47 - connect \A \ui - connect \B 5'10000 - connect \Y $4 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:241" - cell $pos $6 - parameter \A_SIGNED 0 - parameter \A_WIDTH 47 - parameter \Y_WIDTH 64 - connect \A $4 - connect \Y $3 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" - wire width 26 \li - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:249" - wire width 16 \bd - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:254" - wire width 16 \ds - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:259" - wire width 64 $7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:259" - cell $not $8 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \Y_WIDTH 64 - connect \A 64'0000000000000000000000000000000000000000000000000000000000000000 - connect \Y $7 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 64 $9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - cell $pos $10 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \Y_WIDTH 64 - connect \A \DIV_sh - connect \Y $9 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 64 $11 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - cell $pos $12 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \Y_WIDTH 64 - connect \A \DIV_SH32 - connect \Y $11 - end - process $group_0 - assign \imm_b 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:224" - switch \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:225" - attribute \nmigen.decoding "CONST_UI/2" - case 4'0010 - assign \imm_b $1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:228" - attribute \nmigen.decoding "CONST_SI/3" - case 4'0011 - assign \imm_b { { \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] } \si } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:233" - attribute \nmigen.decoding "CONST_SI_HI/5" - case 4'0101 - assign \imm_b { { \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] } \si_hi } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:238" - attribute \nmigen.decoding "CONST_UI_HI/4" - case 4'0100 - assign \imm_b $3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:243" - attribute \nmigen.decoding "CONST_LI/6" - case 4'0110 - assign \imm_b { { \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] } \li } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:248" - attribute \nmigen.decoding "CONST_BD/7" - case 4'0111 - assign \imm_b { { \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] } \bd } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:253" - attribute \nmigen.decoding "CONST_DS/8" - case 4'1000 - assign \imm_b { { \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] } \ds } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:258" - attribute \nmigen.decoding "CONST_M1/9" - case 4'1001 - assign \imm_b $7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" - attribute \nmigen.decoding "CONST_SH/10" - case 4'1010 - assign \imm_b $9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:264" - attribute \nmigen.decoding "CONST_SH32/11" - case 4'1011 - assign \imm_b $11 - end - sync init - end - process $group_1 - assign \imm_b_ok 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:224" - switch \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:225" - attribute \nmigen.decoding "CONST_UI/2" - case 4'0010 - assign \imm_b_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:228" - attribute \nmigen.decoding "CONST_SI/3" - case 4'0011 - assign \imm_b_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:233" - attribute \nmigen.decoding "CONST_SI_HI/5" - case 4'0101 - assign \imm_b_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:238" - attribute \nmigen.decoding "CONST_UI_HI/4" - case 4'0100 - assign \imm_b_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:243" - attribute \nmigen.decoding "CONST_LI/6" - case 4'0110 - assign \imm_b_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:248" - attribute \nmigen.decoding "CONST_BD/7" - case 4'0111 - assign \imm_b_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:253" - attribute \nmigen.decoding "CONST_DS/8" - case 4'1000 - assign \imm_b_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:258" - attribute \nmigen.decoding "CONST_M1/9" - case 4'1001 - assign \imm_b_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" - attribute \nmigen.decoding "CONST_SH/10" - case 4'1010 - assign \imm_b_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:264" - attribute \nmigen.decoding "CONST_SH32/11" - case 4'1011 - assign \imm_b_ok 1'1 - end - sync init - end - process $group_2 - assign \si 16'0000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:224" - switch \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:225" - attribute \nmigen.decoding "CONST_UI/2" - case 4'0010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:228" - attribute \nmigen.decoding "CONST_SI/3" - case 4'0011 - assign \si \DIV_SI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:233" - attribute \nmigen.decoding "CONST_SI_HI/5" - case 4'0101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:238" - attribute \nmigen.decoding "CONST_UI_HI/4" - case 4'0100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:243" - attribute \nmigen.decoding "CONST_LI/6" - case 4'0110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:248" - attribute \nmigen.decoding "CONST_BD/7" - case 4'0111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:253" - attribute \nmigen.decoding "CONST_DS/8" - case 4'1000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:258" - attribute \nmigen.decoding "CONST_M1/9" - case 4'1001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" - attribute \nmigen.decoding "CONST_SH/10" - case 4'1010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:264" - attribute \nmigen.decoding "CONST_SH32/11" - case 4'1011 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:235" - wire width 47 $13 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:235" - wire width 47 $14 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:235" - cell $sshl $15 - parameter \A_SIGNED 0 - parameter \A_WIDTH 16 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 47 - connect \A \DIV_SI - connect \B 5'10000 - connect \Y $14 - end - connect $13 $14 - process $group_3 - assign \si_hi 32'00000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:224" - switch \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:225" - attribute \nmigen.decoding "CONST_UI/2" - case 4'0010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:228" - attribute \nmigen.decoding "CONST_SI/3" - case 4'0011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:233" - attribute \nmigen.decoding "CONST_SI_HI/5" - case 4'0101 - assign \si_hi $13 [31:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:238" - attribute \nmigen.decoding "CONST_UI_HI/4" - case 4'0100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:243" - attribute \nmigen.decoding "CONST_LI/6" - case 4'0110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:248" - attribute \nmigen.decoding "CONST_BD/7" - case 4'0111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:253" - attribute \nmigen.decoding "CONST_DS/8" - case 4'1000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:258" - attribute \nmigen.decoding "CONST_M1/9" - case 4'1001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" - attribute \nmigen.decoding "CONST_SH/10" - case 4'1010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:264" - attribute \nmigen.decoding "CONST_SH32/11" - case 4'1011 - end - sync init - end - process $group_4 - assign \ui 16'0000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:224" - switch \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:225" - attribute \nmigen.decoding "CONST_UI/2" - case 4'0010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:228" - attribute \nmigen.decoding "CONST_SI/3" - case 4'0011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:233" - attribute \nmigen.decoding "CONST_SI_HI/5" - case 4'0101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:238" - attribute \nmigen.decoding "CONST_UI_HI/4" - case 4'0100 - assign \ui \DIV_UI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:243" - attribute \nmigen.decoding "CONST_LI/6" - case 4'0110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:248" - attribute \nmigen.decoding "CONST_BD/7" - case 4'0111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:253" - attribute \nmigen.decoding "CONST_DS/8" - case 4'1000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:258" - attribute \nmigen.decoding "CONST_M1/9" - case 4'1001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" - attribute \nmigen.decoding "CONST_SH/10" - case 4'1010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:264" - attribute \nmigen.decoding "CONST_SH32/11" - case 4'1011 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:245" - wire width 27 $16 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:245" - wire width 27 $17 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:245" - cell $sshl $18 - parameter \A_SIGNED 0 - parameter \A_WIDTH 24 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 27 - connect \A \DIV_LI - connect \B 2'10 - connect \Y $17 - end - connect $16 $17 - process $group_5 - assign \li 26'00000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:224" - switch \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:225" - attribute \nmigen.decoding "CONST_UI/2" - case 4'0010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:228" - attribute \nmigen.decoding "CONST_SI/3" - case 4'0011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:233" - attribute \nmigen.decoding "CONST_SI_HI/5" - case 4'0101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:238" - attribute \nmigen.decoding "CONST_UI_HI/4" - case 4'0100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:243" - attribute \nmigen.decoding "CONST_LI/6" - case 4'0110 - assign \li $16 [25:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:248" - attribute \nmigen.decoding "CONST_BD/7" - case 4'0111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:253" - attribute \nmigen.decoding "CONST_DS/8" - case 4'1000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:258" - attribute \nmigen.decoding "CONST_M1/9" - case 4'1001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" - attribute \nmigen.decoding "CONST_SH/10" - case 4'1010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:264" - attribute \nmigen.decoding "CONST_SH32/11" - case 4'1011 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:250" - wire width 17 $19 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:250" - wire width 17 $20 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:250" - cell $sshl $21 - parameter \A_SIGNED 0 - parameter \A_WIDTH 14 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 17 - connect \A \DIV_BD - connect \B 2'10 - connect \Y $20 - end - connect $19 $20 - process $group_6 - assign \bd 16'0000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:224" - switch \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:225" - attribute \nmigen.decoding "CONST_UI/2" - case 4'0010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:228" - attribute \nmigen.decoding "CONST_SI/3" - case 4'0011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:233" - attribute \nmigen.decoding "CONST_SI_HI/5" - case 4'0101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:238" - attribute \nmigen.decoding "CONST_UI_HI/4" - case 4'0100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:243" - attribute \nmigen.decoding "CONST_LI/6" - case 4'0110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:248" - attribute \nmigen.decoding "CONST_BD/7" - case 4'0111 - assign \bd $19 [15:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:253" - attribute \nmigen.decoding "CONST_DS/8" - case 4'1000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:258" - attribute \nmigen.decoding "CONST_M1/9" - case 4'1001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" - attribute \nmigen.decoding "CONST_SH/10" - case 4'1010 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\src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \dec_XL_BT - cell \dec$168 \dec - connect \raw_opcode_in \raw_opcode_in - connect \bigendian \bigendian - connect \opcode_in \dec_opcode_in - connect \DIV_rc_sel \dec_DIV_rc_sel - connect \DIV_cr_in \dec_DIV_cr_in - connect \DIV_cr_out \dec_DIV_cr_out - connect \DIV_internal_op \dec_DIV_internal_op - connect \DIV_function_unit \dec_DIV_function_unit - connect \DIV_in1_sel \dec_DIV_in1_sel - connect \DIV_in2_sel \dec_DIV_in2_sel - connect \DIV_ldst_len \dec_DIV_ldst_len - connect \DIV_inv_a \dec_DIV_inv_a - connect \DIV_inv_out \dec_DIV_inv_out - connect \DIV_cry_in \dec_DIV_cry_in - connect \DIV_cry_out \dec_DIV_cry_out - connect \DIV_is_32b \dec_DIV_is_32b - connect \DIV_sgn \dec_DIV_sgn - connect \DIV_RA \dec_DIV_RA - connect \DIV_SI \dec_DIV_SI - connect \DIV_UI \dec_DIV_UI - connect \DIV_SH32 \dec_DIV_SH32 - connect \DIV_sh \dec_DIV_sh - connect \DIV_LI \dec_DIV_LI - connect \DIV_Rc \dec_DIV_Rc - connect \DIV_OE \dec_DIV_OE - connect \DIV_BD \dec_DIV_BD - connect \DIV_BB \dec_DIV_BB - connect \DIV_BA \dec_DIV_BA - connect \DIV_BT \dec_DIV_BT - connect \DIV_FXM \dec_DIV_FXM - connect \DIV_BI \dec_DIV_BI - connect \DIV_DS \dec_DIV_DS - connect \DIV_BC \dec_DIV_BC - connect \X_BF \dec_X_BF - connect \X_BFA \dec_X_BFA - connect \XL_BT \dec_XL_BT - end - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:404" - wire width 2 \dec_rc_sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \dec_rc_rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \dec_rc_rc_ok - cell \dec_rc$169 \dec_rc - connect \sel_in \dec_rc_sel_in - connect \rc \dec_rc_rc - connect \rc_ok \dec_rc_rc_ok - connect \DIV_Rc \dec_DIV_Rc - end - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:441" - wire width 2 \dec_oe_sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \dec_oe_oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \dec_oe_oe_ok - cell \dec_oe$170 \dec_oe - connect \sel_in \dec_oe_sel_in - connect \DIV_internal_op \dec_DIV_internal_op - connect \oe \dec_oe_oe - connect \oe_ok \dec_oe_oe_ok - connect \DIV_OE \dec_DIV_OE - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:485" - wire width 32 \dec_cr_in_insn_in - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:484" - wire width 3 \dec_cr_in_sel_in - cell \dec_cr_in$171 \dec_cr_in - connect \insn_in \dec_cr_in_insn_in - connect \sel_in \dec_cr_in_sel_in - connect \DIV_internal_op \dec_DIV_internal_op - connect \DIV_BB \dec_DIV_BB - connect \DIV_BA \dec_DIV_BA - connect \DIV_BT \dec_DIV_BT - connect \DIV_FXM \dec_DIV_FXM - connect \DIV_BI \dec_DIV_BI - connect \DIV_BC \dec_DIV_BC - connect \X_BFA \dec_X_BFA - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:550" - wire width 32 \dec_cr_out_insn_in - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:549" - wire width 3 \dec_cr_out_sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:548" - wire width 1 \dec_cr_out_rc_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \dec_cr_out_cr_bitfield_ok - cell \dec_cr_out$173 \dec_cr_out - connect \insn_in \dec_cr_out_insn_in - connect \sel_in \dec_cr_out_sel_in - connect \rc_in \dec_cr_out_rc_in - connect \DIV_internal_op \dec_DIV_internal_op - connect \cr_bitfield_ok \dec_cr_out_cr_bitfield_ok - connect \DIV_FXM \dec_DIV_FXM - connect \X_BF \dec_X_BF - connect \XL_BT \dec_XL_BT - end - attribute \enum_base_type "In1Sel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "RA" - attribute \enum_value_010 "RA_OR_ZERO" - attribute \enum_value_011 "SPR" - attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:148" - wire width 3 \dec_ai_sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:149" - wire width 1 \dec_ai_immz_out - cell \dec_ai$175 \dec_ai - connect \sel_in \dec_ai_sel_in - connect \immz_out \dec_ai_immz_out - connect \DIV_RA \dec_DIV_RA - end - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:216" - wire width 4 \dec_bi_sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 \dec_bi_imm_b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \dec_bi_imm_b_ok - cell \dec_bi$176 \dec_bi - connect \sel_in \dec_bi_sel_in - connect \imm_b \dec_bi_imm_b - connect \imm_b_ok \dec_bi_imm_b_ok - connect \DIV_SI \dec_DIV_SI - connect \DIV_UI \dec_DIV_UI - connect \DIV_SH32 \dec_DIV_SH32 - connect \DIV_sh \dec_DIV_sh - connect \DIV_LI \dec_DIV_LI - connect \DIV_BD \dec_DIV_BD - connect \DIV_DS \dec_DIV_DS - end - process $group_0 - assign \DIV_DIV__insn 32'00000000000000000000000000000000 - assign \DIV_DIV__insn \dec_opcode_in - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:405" - wire width 32 \insn_in - process $group_1 - assign \insn_in 32'00000000000000000000000000000000 - assign \insn_in \dec_opcode_in - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:442" - wire width 32 \insn_in$1 - process $group_2 - assign \insn_in$1 32'00000000000000000000000000000000 - assign \insn_in$1 \dec_opcode_in - sync init - end - process $group_3 - assign \dec_cr_in_insn_in 32'00000000000000000000000000000000 - assign \dec_cr_in_insn_in \dec_opcode_in - sync init - end - process $group_4 - assign \dec_cr_out_insn_in 32'00000000000000000000000000000000 - assign \dec_cr_out_insn_in \dec_opcode_in - sync init - end - process $group_5 - assign \dec_rc_sel_in 2'00 - assign \dec_rc_sel_in \dec_DIV_rc_sel - sync init - end - process $group_6 - assign \dec_oe_sel_in 2'00 - assign \dec_oe_sel_in \dec_DIV_rc_sel - sync init - end - process $group_7 - assign \dec_cr_in_sel_in 3'000 - assign \dec_cr_in_sel_in \dec_DIV_cr_in - sync init - end - process $group_8 - assign \dec_cr_out_sel_in 3'000 - assign \dec_cr_out_sel_in \dec_DIV_cr_out - sync init - end - process $group_9 - assign \dec_cr_out_rc_in 1'0 - assign \dec_cr_out_rc_in \dec_rc_rc - sync init - end - process $group_10 - assign \DIV_DIV__insn_type 7'0000000 - assign \DIV_DIV__insn_type \dec_DIV_internal_op - sync init - end - process $group_11 - assign \DIV_DIV__fn_unit 11'00000000000 - assign \DIV_DIV__fn_unit \dec_DIV_function_unit - sync init - end - process $group_12 - assign \dec_ai_sel_in 3'000 - assign \dec_ai_sel_in \dec_DIV_in1_sel - sync init - end - process $group_13 - assign \DIV_DIV__zero_a 1'0 - assign \DIV_DIV__zero_a \dec_ai_immz_out - sync init - end - process $group_14 - assign \dec_bi_sel_in 4'0000 - assign \dec_bi_sel_in \dec_DIV_in2_sel - sync init - end - process $group_15 - assign \DIV_DIV__imm_data__data 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \DIV_DIV__imm_data__ok 1'0 - assign { \DIV_DIV__imm_data__ok \DIV_DIV__imm_data__data } { \dec_bi_imm_b_ok \dec_bi_imm_b } - sync init - end - process $group_17 - assign \DIV_DIV__rc__rc 1'0 - assign \DIV_DIV__rc__ok 1'0 - assign { \DIV_DIV__rc__ok \DIV_DIV__rc__rc } { \dec_rc_rc_ok \dec_rc_rc } - sync init - end - process $group_19 - assign \DIV_DIV__oe__oe 1'0 - assign \DIV_DIV__oe__ok 1'0 - assign { \DIV_DIV__oe__ok \DIV_DIV__oe__oe } { \dec_oe_oe_ok \dec_oe_oe } - sync init - end - process $group_21 - assign \DIV_DIV__write_cr0 1'0 - assign \DIV_DIV__write_cr0 \dec_cr_out_cr_bitfield_ok - sync init - end - process $group_22 - assign \DIV_DIV__data_len 4'0000 - assign \DIV_DIV__data_len \dec_DIV_ldst_len - sync init - end - process $group_23 - assign \DIV_DIV__invert_in 1'0 - assign \DIV_DIV__invert_in \dec_DIV_inv_a - sync init - end - process $group_24 - assign \DIV_DIV__invert_out 1'0 - assign \DIV_DIV__invert_out \dec_DIV_inv_out - sync init - end - process $group_25 - assign \DIV_DIV__input_carry 2'00 - assign \DIV_DIV__input_carry \dec_DIV_cry_in - sync init - end - process $group_26 - assign \DIV_DIV__output_carry 1'0 - assign \DIV_DIV__output_carry \dec_DIV_cry_out - sync init - end - process $group_27 - assign \DIV_DIV__is_32bit 1'0 - assign \DIV_DIV__is_32bit \dec_DIV_is_32b - sync init - end - process $group_28 - assign \DIV_DIV__is_signed 1'0 - assign \DIV_DIV__is_signed \dec_DIV_sgn - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.dec_MUL.dec.MUL_dec19" -module \MUL_dec19 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" - wire width 32 input 0 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:308" - wire width 10 \opcode_switch - process $group_0 - assign \opcode_switch 10'0000000000 - assign \opcode_switch \opcode_in [10:1] - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:308" - wire width 5 \opcode_switch$1 - process $group_1 - assign \opcode_switch$1 5'00000 - assign \opcode_switch$1 \opcode_in [5:1] - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.dec_MUL.dec.MUL_dec30" -module \MUL_dec30 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" - wire width 32 input 0 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:308" - wire width 4 \opcode_switch - process $group_0 - assign \opcode_switch 4'0000 - assign \opcode_switch \opcode_in [4:1] - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.dec_MUL.dec.MUL_dec31.MUL_dec_sub10" -module \MUL_dec_sub10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" - wire width 32 input 0 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:308" - wire width 5 \opcode_switch - process $group_0 - assign \opcode_switch 5'00000 - assign \opcode_switch \opcode_in [10:6] - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.dec_MUL.dec.MUL_dec31.MUL_dec_sub28" -module \MUL_dec_sub28 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" - wire width 32 input 0 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:308" - wire width 5 \opcode_switch - process $group_0 - assign \opcode_switch 5'00000 - assign \opcode_switch \opcode_in [10:6] - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.dec_MUL.dec.MUL_dec31.MUL_dec_sub0" -module \MUL_dec_sub0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" - wire width 32 input 0 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:308" - wire width 5 \opcode_switch - process $group_0 - assign \opcode_switch 5'00000 - assign \opcode_switch \opcode_in [10:6] - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.dec_MUL.dec.MUL_dec31.MUL_dec_sub26" -module \MUL_dec_sub26 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" - wire width 32 input 0 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:308" - wire width 5 \opcode_switch - process $group_0 - assign \opcode_switch 5'00000 - assign \opcode_switch \opcode_in [10:6] - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.dec_MUL.dec.MUL_dec31.MUL_dec_sub19" -module \MUL_dec_sub19 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" - wire width 32 input 0 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:308" - wire width 5 \opcode_switch - process $group_0 - assign \opcode_switch 5'00000 - assign \opcode_switch \opcode_in [10:6] - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.dec_MUL.dec.MUL_dec31.MUL_dec_sub22" -module \MUL_dec_sub22 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" - wire width 32 input 0 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:308" - wire width 5 \opcode_switch - process $group_0 - assign \opcode_switch 5'00000 - assign \opcode_switch \opcode_in [10:6] - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.dec_MUL.dec.MUL_dec31.MUL_dec_sub9" -module \MUL_dec_sub9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" - wire width 32 input 0 \opcode_in - attribute \enum_base_type "Function" - attribute \enum_value_00000000000 "NONE" - attribute \enum_value_00000000010 "ALU" - attribute \enum_value_00000000100 "LDST" - attribute \enum_value_00000001000 "SHIFT_ROT" - attribute \enum_value_00000010000 "LOGICAL" - attribute \enum_value_00000100000 "BRANCH" - attribute \enum_value_00001000000 "CR" - attribute \enum_value_00010000000 "TRAP" - attribute \enum_value_00100000000 "MUL" - attribute \enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 11 output 1 \MUL_function_unit - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 7 output 2 \MUL_internal_op - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 4 output 3 \MUL_in2_sel - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 output 4 \MUL_cr_in - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 output 5 \MUL_cr_out - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 2 output 6 \MUL_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 output 7 \MUL_is_32b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 output 8 \MUL_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:308" - wire width 5 \opcode_switch - process $group_0 - assign \opcode_switch 5'00000 - assign \opcode_switch \opcode_in [10:6] - sync init - end - process $group_1 - assign \MUL_function_unit 11'00000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00010 - assign \MUL_function_unit 11'00100000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \MUL_function_unit 11'00100000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10010 - assign \MUL_function_unit 11'00100000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10000 - assign \MUL_function_unit 11'00100000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00111 - assign \MUL_function_unit 11'00100000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10111 - assign \MUL_function_unit 11'00100000000 - end - sync init - end - process $group_2 - assign \MUL_internal_op 7'0000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00010 - assign \MUL_internal_op 7'0110011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \MUL_internal_op 7'0110011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10010 - assign \MUL_internal_op 7'0110011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10000 - assign \MUL_internal_op 7'0110011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00111 - assign \MUL_internal_op 7'0110010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10111 - assign \MUL_internal_op 7'0110010 - end - sync init - end - process $group_3 - assign \MUL_in2_sel 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00010 - assign \MUL_in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \MUL_in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10010 - assign \MUL_in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10000 - assign \MUL_in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00111 - assign \MUL_in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10111 - assign \MUL_in2_sel 4'0001 - end - sync init - end - process $group_4 - assign \MUL_cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00010 - assign \MUL_cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \MUL_cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10010 - assign \MUL_cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10000 - assign \MUL_cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00111 - assign \MUL_cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10111 - assign \MUL_cr_in 3'000 - end - sync init - end - process $group_5 - assign \MUL_cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00010 - assign \MUL_cr_out 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \MUL_cr_out 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10010 - assign \MUL_cr_out 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10000 - assign \MUL_cr_out 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00111 - assign \MUL_cr_out 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10111 - assign \MUL_cr_out 3'001 - end - sync init - end - process $group_6 - assign \MUL_rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00010 - assign \MUL_rc_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \MUL_rc_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10010 - assign \MUL_rc_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10000 - assign \MUL_rc_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00111 - assign \MUL_rc_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10111 - assign \MUL_rc_sel 2'10 - end - sync init - end - process $group_7 - assign \MUL_is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00010 - assign \MUL_is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \MUL_is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10010 - assign \MUL_is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10000 - assign \MUL_is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00111 - assign \MUL_is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10111 - assign \MUL_is_32b 1'0 - end - sync init - end - process $group_8 - assign \MUL_sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00010 - assign \MUL_sgn 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \MUL_sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10010 - assign \MUL_sgn 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10000 - assign \MUL_sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00111 - assign \MUL_sgn 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10111 - assign \MUL_sgn 1'1 - end - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.dec_MUL.dec.MUL_dec31.MUL_dec_sub11" -module \MUL_dec_sub11 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" - wire width 32 input 0 \opcode_in - attribute \enum_base_type "Function" - attribute \enum_value_00000000000 "NONE" - attribute \enum_value_00000000010 "ALU" - attribute \enum_value_00000000100 "LDST" - attribute \enum_value_00000001000 "SHIFT_ROT" - attribute \enum_value_00000010000 "LOGICAL" - attribute \enum_value_00000100000 "BRANCH" - attribute \enum_value_00001000000 "CR" - attribute \enum_value_00010000000 "TRAP" - attribute \enum_value_00100000000 "MUL" - attribute \enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 11 output 1 \MUL_function_unit - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 7 output 2 \MUL_internal_op - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 4 output 3 \MUL_in2_sel - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 output 4 \MUL_cr_in - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 output 5 \MUL_cr_out - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 2 output 6 \MUL_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 output 7 \MUL_is_32b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 output 8 \MUL_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:308" - wire width 5 \opcode_switch - process $group_0 - assign \opcode_switch 5'00000 - assign \opcode_switch \opcode_in [10:6] - sync init - end - process $group_1 - assign \MUL_function_unit 11'00000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00010 - assign \MUL_function_unit 11'00100000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \MUL_function_unit 11'00100000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10010 - assign \MUL_function_unit 11'00100000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10000 - assign \MUL_function_unit 11'00100000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00111 - assign \MUL_function_unit 11'00100000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10111 - assign \MUL_function_unit 11'00100000000 - end - sync init - end - process $group_2 - assign \MUL_internal_op 7'0000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00010 - assign \MUL_internal_op 7'0110100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \MUL_internal_op 7'0110100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10010 - assign \MUL_internal_op 7'0110100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10000 - assign \MUL_internal_op 7'0110100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00111 - assign \MUL_internal_op 7'0110010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10111 - assign \MUL_internal_op 7'0110010 - end - sync init - end - process $group_3 - assign \MUL_in2_sel 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00010 - assign \MUL_in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \MUL_in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10010 - assign \MUL_in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10000 - assign \MUL_in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00111 - assign \MUL_in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10111 - assign \MUL_in2_sel 4'0001 - end - sync init - end - process $group_4 - assign \MUL_cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00010 - assign \MUL_cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \MUL_cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10010 - assign \MUL_cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10000 - assign \MUL_cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00111 - assign \MUL_cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10111 - assign \MUL_cr_in 3'000 - end - sync init - end - process $group_5 - assign \MUL_cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00010 - assign \MUL_cr_out 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \MUL_cr_out 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10010 - assign \MUL_cr_out 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10000 - assign \MUL_cr_out 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00111 - assign \MUL_cr_out 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10111 - assign \MUL_cr_out 3'001 - end - sync init - end - process $group_6 - assign \MUL_rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src 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\enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 4 \MUL_in2_sel$35 - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 4 \MUL_in2_sel$36 - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 4 \MUL_in2_sel$37 - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 4 \MUL_in2_sel$38 - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 4 \MUL_in2_sel$39 - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 4 \MUL_in2_sel$40 - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 4 \MUL_in2_sel$41 - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 4 \MUL_in2_sel$42 - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 4 \MUL_in2_sel$43 - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 4 \MUL_in2_sel$44 - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 4 \MUL_in2_sel$45 - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 4 \MUL_in2_sel$46 - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 4 \MUL_in2_sel$47 - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 4 \MUL_in2_sel$48 - process $group_22 - assign \MUL_in2_sel 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:315" - switch \opc_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01010 - assign \MUL_in2_sel \MUL_in2_sel$33 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'11100 - assign \MUL_in2_sel \MUL_in2_sel$34 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'00000 - assign \MUL_in2_sel \MUL_in2_sel$35 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'11010 - assign \MUL_in2_sel \MUL_in2_sel$36 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10011 - assign \MUL_in2_sel \MUL_in2_sel$37 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10110 - assign \MUL_in2_sel \MUL_in2_sel$38 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01001 - assign \MUL_in2_sel \MUL_dec_sub9_MUL_in2_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01011 - assign \MUL_in2_sel \MUL_dec_sub11_MUL_in2_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'11011 - assign \MUL_in2_sel \MUL_in2_sel$39 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01111 - assign \MUL_in2_sel \MUL_in2_sel$40 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10100 - assign \MUL_in2_sel \MUL_in2_sel$41 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10101 - assign \MUL_in2_sel \MUL_in2_sel$42 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10111 - assign \MUL_in2_sel \MUL_in2_sel$43 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10000 - assign \MUL_in2_sel \MUL_in2_sel$44 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10010 - assign \MUL_in2_sel \MUL_in2_sel$45 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01000 - assign \MUL_in2_sel \MUL_in2_sel$46 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'11000 - assign \MUL_in2_sel \MUL_in2_sel$47 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'00100 - assign \MUL_in2_sel \MUL_in2_sel$48 - end - sync init - end - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \MUL_cr_in$49 - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \MUL_cr_in$50 - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \MUL_cr_in$51 - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \MUL_cr_in$52 - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \MUL_cr_in$53 - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \MUL_cr_in$54 - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \MUL_cr_in$55 - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \MUL_cr_in$56 - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \MUL_cr_in$57 - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \MUL_cr_in$58 - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \MUL_cr_in$59 - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \MUL_cr_in$60 - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \MUL_cr_in$61 - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \MUL_cr_in$62 - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \MUL_cr_in$63 - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \MUL_cr_in$64 - process $group_23 - assign \MUL_cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:315" - switch \opc_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01010 - assign \MUL_cr_in \MUL_cr_in$49 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'11100 - assign \MUL_cr_in \MUL_cr_in$50 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'00000 - assign \MUL_cr_in \MUL_cr_in$51 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'11010 - assign \MUL_cr_in \MUL_cr_in$52 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10011 - assign \MUL_cr_in \MUL_cr_in$53 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10110 - assign \MUL_cr_in \MUL_cr_in$54 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01001 - assign \MUL_cr_in \MUL_dec_sub9_MUL_cr_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01011 - assign \MUL_cr_in \MUL_dec_sub11_MUL_cr_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'11011 - assign \MUL_cr_in \MUL_cr_in$55 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01111 - assign \MUL_cr_in \MUL_cr_in$56 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10100 - assign \MUL_cr_in \MUL_cr_in$57 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10101 - assign \MUL_cr_in \MUL_cr_in$58 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10111 - assign \MUL_cr_in \MUL_cr_in$59 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10000 - assign \MUL_cr_in \MUL_cr_in$60 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10010 - assign \MUL_cr_in \MUL_cr_in$61 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01000 - assign \MUL_cr_in \MUL_cr_in$62 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'11000 - assign \MUL_cr_in \MUL_cr_in$63 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'00100 - assign \MUL_cr_in \MUL_cr_in$64 - end - sync init - end - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \MUL_cr_out$65 - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \MUL_cr_out$66 - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \MUL_cr_out$67 - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \MUL_cr_out$68 - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \MUL_cr_out$69 - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \MUL_cr_out$70 - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \MUL_cr_out$71 - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \MUL_cr_out$72 - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \MUL_cr_out$73 - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \MUL_cr_out$74 - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \MUL_cr_out$75 - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \MUL_cr_out$76 - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \MUL_cr_out$77 - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \MUL_cr_out$78 - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \MUL_cr_out$79 - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \MUL_cr_out$80 - process $group_24 - assign \MUL_cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:315" - switch \opc_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01010 - assign \MUL_cr_out \MUL_cr_out$65 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'11100 - assign \MUL_cr_out \MUL_cr_out$66 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'00000 - assign \MUL_cr_out \MUL_cr_out$67 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'11010 - assign \MUL_cr_out \MUL_cr_out$68 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10011 - assign \MUL_cr_out \MUL_cr_out$69 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10110 - assign \MUL_cr_out \MUL_cr_out$70 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01001 - assign \MUL_cr_out \MUL_dec_sub9_MUL_cr_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01011 - assign \MUL_cr_out \MUL_dec_sub11_MUL_cr_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'11011 - assign \MUL_cr_out \MUL_cr_out$71 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01111 - assign \MUL_cr_out \MUL_cr_out$72 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10100 - assign \MUL_cr_out \MUL_cr_out$73 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10101 - assign \MUL_cr_out \MUL_cr_out$74 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10111 - assign \MUL_cr_out \MUL_cr_out$75 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10000 - assign \MUL_cr_out \MUL_cr_out$76 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10010 - assign \MUL_cr_out \MUL_cr_out$77 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01000 - assign \MUL_cr_out \MUL_cr_out$78 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'11000 - assign \MUL_cr_out \MUL_cr_out$79 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'00100 - assign \MUL_cr_out \MUL_cr_out$80 - end - sync init - end - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 2 \MUL_rc_sel$81 - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 2 \MUL_rc_sel$82 - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 2 \MUL_rc_sel$83 - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 2 \MUL_rc_sel$84 - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 2 \MUL_rc_sel$85 - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 2 \MUL_rc_sel$86 - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 2 \MUL_rc_sel$87 - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 2 \MUL_rc_sel$88 - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 2 \MUL_rc_sel$89 - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 2 \MUL_rc_sel$90 - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 2 \MUL_rc_sel$91 - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 2 \MUL_rc_sel$92 - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 2 \MUL_rc_sel$93 - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 2 \MUL_rc_sel$94 - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 2 \MUL_rc_sel$95 - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 2 \MUL_rc_sel$96 - process $group_25 - assign \MUL_rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:315" - switch \opc_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01010 - assign \MUL_rc_sel \MUL_rc_sel$81 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'11100 - assign \MUL_rc_sel \MUL_rc_sel$82 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'00000 - assign \MUL_rc_sel \MUL_rc_sel$83 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'11010 - assign \MUL_rc_sel \MUL_rc_sel$84 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10011 - assign \MUL_rc_sel \MUL_rc_sel$85 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10110 - assign \MUL_rc_sel \MUL_rc_sel$86 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01001 - assign \MUL_rc_sel \MUL_dec_sub9_MUL_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01011 - assign \MUL_rc_sel \MUL_dec_sub11_MUL_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'11011 - assign \MUL_rc_sel \MUL_rc_sel$87 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01111 - assign \MUL_rc_sel \MUL_rc_sel$88 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10100 - assign \MUL_rc_sel \MUL_rc_sel$89 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10101 - assign \MUL_rc_sel \MUL_rc_sel$90 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10111 - assign \MUL_rc_sel \MUL_rc_sel$91 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10000 - assign \MUL_rc_sel \MUL_rc_sel$92 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10010 - assign \MUL_rc_sel \MUL_rc_sel$93 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01000 - assign \MUL_rc_sel \MUL_rc_sel$94 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'11000 - assign \MUL_rc_sel \MUL_rc_sel$95 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'00100 - assign \MUL_rc_sel \MUL_rc_sel$96 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \MUL_is_32b$97 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \MUL_is_32b$98 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \MUL_is_32b$99 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \MUL_is_32b$100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \MUL_is_32b$101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \MUL_is_32b$102 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \MUL_is_32b$103 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \MUL_is_32b$104 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \MUL_is_32b$105 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \MUL_is_32b$106 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \MUL_is_32b$107 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \MUL_is_32b$108 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \MUL_is_32b$109 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \MUL_is_32b$110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \MUL_is_32b$111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \MUL_is_32b$112 - process $group_26 - assign \MUL_is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:315" - switch \opc_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01010 - assign \MUL_is_32b \MUL_is_32b$97 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'11100 - assign \MUL_is_32b \MUL_is_32b$98 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'00000 - assign \MUL_is_32b \MUL_is_32b$99 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'11010 - assign \MUL_is_32b \MUL_is_32b$100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10011 - assign \MUL_is_32b \MUL_is_32b$101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10110 - assign \MUL_is_32b \MUL_is_32b$102 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01001 - assign \MUL_is_32b \MUL_dec_sub9_MUL_is_32b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01011 - assign \MUL_is_32b \MUL_dec_sub11_MUL_is_32b - attribute \src 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attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 7 \MUL_internal_op$7 - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 7 \MUL_internal_op$8 - process $group_7 - assign \MUL_internal_op 7'0000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'010011 - assign \MUL_internal_op \MUL_internal_op$5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'011110 - assign \MUL_internal_op \MUL_internal_op$6 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'011111 - assign \MUL_internal_op \MUL_dec31_MUL_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'111010 - assign \MUL_internal_op \MUL_internal_op$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'111110 - assign \MUL_internal_op \MUL_internal_op$8 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'000111 - assign \MUL_internal_op 7'0110010 - end - sync init - end - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 4 \MUL_in2_sel$9 - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 4 \MUL_in2_sel$10 - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 4 \MUL_in2_sel$11 - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 4 \MUL_in2_sel$12 - process $group_8 - assign \MUL_in2_sel 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'010011 - assign \MUL_in2_sel \MUL_in2_sel$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'011110 - assign \MUL_in2_sel \MUL_in2_sel$10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'011111 - assign \MUL_in2_sel \MUL_dec31_MUL_in2_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'111010 - assign \MUL_in2_sel \MUL_in2_sel$11 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'111110 - assign \MUL_in2_sel \MUL_in2_sel$12 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'000111 - assign \MUL_in2_sel 4'0011 - end - sync init - end - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \MUL_cr_in$13 - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \MUL_cr_in$14 - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \MUL_cr_in$15 - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \MUL_cr_in$16 - process $group_9 - assign \MUL_cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'010011 - assign \MUL_cr_in \MUL_cr_in$13 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'011110 - assign \MUL_cr_in \MUL_cr_in$14 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'011111 - assign \MUL_cr_in \MUL_dec31_MUL_cr_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'111010 - assign \MUL_cr_in \MUL_cr_in$15 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'111110 - assign \MUL_cr_in \MUL_cr_in$16 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'000111 - assign \MUL_cr_in 3'000 - end - sync init - end - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \MUL_cr_out$17 - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \MUL_cr_out$18 - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \MUL_cr_out$19 - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \MUL_cr_out$20 - process $group_10 - assign \MUL_cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'010011 - assign \MUL_cr_out \MUL_cr_out$17 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'011110 - assign \MUL_cr_out \MUL_cr_out$18 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'011111 - assign \MUL_cr_out \MUL_dec31_MUL_cr_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'111010 - assign \MUL_cr_out \MUL_cr_out$19 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'111110 - assign \MUL_cr_out \MUL_cr_out$20 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'000111 - assign \MUL_cr_out 3'001 - end - sync init - end - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 2 \MUL_rc_sel$21 - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 2 \MUL_rc_sel$22 - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 2 \MUL_rc_sel$23 - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 2 \MUL_rc_sel$24 - process $group_11 - assign \MUL_rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'010011 - assign \MUL_rc_sel \MUL_rc_sel$21 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'011110 - assign \MUL_rc_sel \MUL_rc_sel$22 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'011111 - assign \MUL_rc_sel \MUL_dec31_MUL_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'111010 - assign \MUL_rc_sel \MUL_rc_sel$23 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'111110 - assign \MUL_rc_sel \MUL_rc_sel$24 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'000111 - assign \MUL_rc_sel 2'00 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \MUL_is_32b$25 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \MUL_is_32b$26 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \MUL_is_32b$27 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \MUL_is_32b$28 - process $group_12 - assign \MUL_is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'010011 - assign \MUL_is_32b \MUL_is_32b$25 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'011110 - assign \MUL_is_32b \MUL_is_32b$26 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'011111 - assign \MUL_is_32b \MUL_dec31_MUL_is_32b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'111010 - assign \MUL_is_32b \MUL_is_32b$27 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'111110 - assign \MUL_is_32b \MUL_is_32b$28 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'000111 - assign \MUL_is_32b 1'0 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \MUL_sgn$29 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \MUL_sgn$30 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \MUL_sgn$31 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \MUL_sgn$32 - process $group_13 - assign \MUL_sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'010011 - assign \MUL_sgn \MUL_sgn$29 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'011110 - assign \MUL_sgn \MUL_sgn$30 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'011111 - assign \MUL_sgn \MUL_dec31_MUL_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'111010 - assign \MUL_sgn \MUL_sgn$31 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'111110 - assign \MUL_sgn \MUL_sgn$32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'000111 - assign \MUL_sgn 1'1 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:308" - wire width 32 \opcode_switch$33 - process $group_14 - assign \opcode_switch$33 32'00000000000000000000000000000000 - assign \opcode_switch$33 \opcode_in - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:418" - wire width 32 $34 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:418" - cell $mux $35 - parameter \WIDTH 32 - connect \A \raw_opcode_in - connect \B { \raw_opcode_in [7:0] \raw_opcode_in [15:8] \raw_opcode_in [23:16] \raw_opcode_in [31:24] } - connect \S \bigendian - connect \Y $34 - end - process $group_15 - assign \opcode_in 32'00000000000000000000000000000000 - assign \opcode_in $34 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 5 \MUL_RS - process $group_16 - assign \MUL_RS 5'00000 - assign \MUL_RS { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 5 \MUL_RT - process $group_17 - assign \MUL_RT 5'00000 - assign \MUL_RT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 5 \MUL_RA - process $group_18 - assign \MUL_RA 5'00000 - assign \MUL_RA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 5 \MUL_RB - process $group_19 - assign \MUL_RB 5'00000 - assign \MUL_RB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - process $group_20 - assign \MUL_SI 16'0000000000000000 - assign \MUL_SI { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] \opcode_in [0] } - sync init - end - process $group_21 - assign \MUL_UI 16'0000000000000000 - assign \MUL_UI { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] \opcode_in [0] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 1 \MUL_L - process $group_22 - assign \MUL_L 1'0 - assign \MUL_L { \opcode_in [21] } - sync init - end - process $group_23 - assign \MUL_SH32 5'00000 - assign \MUL_SH32 { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - process $group_24 - assign \MUL_sh 6'000000 - assign \MUL_sh { \opcode_in [1] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 5 \MUL_MB32 - process $group_25 - assign \MUL_MB32 5'00000 - assign \MUL_MB32 { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 5 \MUL_ME32 - process $group_26 - assign \MUL_ME32 5'00000 - assign \MUL_ME32 { \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] } - sync init - end - process $group_27 - assign \MUL_LI 24'000000000000000000000000 - assign \MUL_LI { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 1 \MUL_LK - process $group_28 - assign \MUL_LK 1'0 - assign \MUL_LK { \opcode_in [0] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 1 \MUL_AA - process $group_29 - assign \MUL_AA 1'0 - assign \MUL_AA { \opcode_in [1] } - sync init - end - process $group_30 - assign \MUL_Rc 1'0 - assign \MUL_Rc { \opcode_in [0] } - sync init - end - process $group_31 - assign \MUL_OE 1'0 - assign \MUL_OE { \opcode_in [10] } - sync init - end - process $group_32 - assign \MUL_BD 14'00000000000000 - assign \MUL_BD { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 3 \MUL_BF - process $group_33 - assign \MUL_BF 3'000 - assign \MUL_BF { \opcode_in [25] \opcode_in [24] \opcode_in [23] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 10 \MUL_CR - process $group_34 - assign \MUL_CR 10'0000000000 - assign \MUL_CR { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] } - sync init - end - process $group_35 - assign \MUL_BB 5'00000 - assign \MUL_BB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - process $group_36 - assign \MUL_BA 5'00000 - assign \MUL_BA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - process $group_37 - assign \MUL_BT 5'00000 - assign \MUL_BT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - process $group_38 - assign \MUL_FXM 8'00000000 - assign \MUL_FXM { \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 5 \MUL_BO - process $group_39 - assign \MUL_BO 5'00000 - assign \MUL_BO { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - process $group_40 - assign \MUL_BI 5'00000 - assign \MUL_BI { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 2 \MUL_BH - process $group_41 - assign \MUL_BH 2'00 - assign \MUL_BH { \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 16 \MUL_D - process $group_42 - assign \MUL_D 16'0000000000000000 - assign \MUL_D { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] \opcode_in [0] } - sync init - end - process $group_43 - assign \MUL_DS 14'00000000000000 - assign \MUL_DS { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 5 \MUL_TO - process $group_44 - assign \MUL_TO 5'00000 - assign \MUL_TO { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - process $group_45 - assign \MUL_BC 5'00000 - assign \MUL_BC { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 5 \MUL_SH - process $group_46 - assign \MUL_SH 5'00000 - assign \MUL_SH { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 5 \MUL_ME - process $group_47 - assign \MUL_ME 5'00000 - assign \MUL_ME { \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 5 \MUL_MB - process $group_48 - assign \MUL_MB 5'00000 - assign \MUL_MB { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 10 \MUL_SPR - process $group_49 - assign \MUL_SPR 10'0000000000 - assign \MUL_SPR { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \X_A - process $group_50 - assign \X_A 1'0 - assign \X_A { \opcode_in [25] } - sync init - end - process $group_51 - assign \X_BF 3'000 - assign \X_BF { \opcode_in [25] \opcode_in [24] \opcode_in [23] } - sync init - end - process $group_52 - assign \X_BFA 3'000 - assign \X_BFA { \opcode_in [20] \opcode_in [19] \opcode_in [18] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \X_BO - process $group_53 - assign \X_BO 5'00000 - assign \X_BO { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 4 \X_CT - process $group_54 - assign \X_CT 4'0000 - assign \X_CT { \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 7 \X_DCMX - process $group_55 - assign \X_DCMX 7'0000000 - assign \X_DCMX { \opcode_in [22] \opcode_in [21] \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 3 \X_DRM - process $group_56 - assign \X_DRM 3'000 - assign \X_DRM { \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \X_E - process $group_57 - assign \X_E 1'0 - assign \X_E { \opcode_in [15] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 4 \X_E_1 - process $group_58 - assign \X_E_1 4'0000 - assign \X_E_1 { \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 2 \X_EO - process $group_59 - assign \X_EO 2'00 - assign \X_EO { \opcode_in [20] \opcode_in [19] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \X_EO_1 - process $group_60 - assign \X_EO_1 5'00000 - assign \X_EO_1 { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \X_EX - process $group_61 - assign \X_EX 1'0 - assign \X_EX { \opcode_in [0] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \X_FC - process $group_62 - assign \X_FC 5'00000 - assign \X_FC { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \X_FRA - process $group_63 - assign \X_FRA 5'00000 - assign \X_FRA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \X_FRAp - process $group_64 - assign \X_FRAp 5'00000 - assign \X_FRAp { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \X_FRB - process $group_65 - assign \X_FRB 5'00000 - assign \X_FRB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \X_FRBp - process $group_66 - assign \X_FRBp 5'00000 - assign \X_FRBp { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \X_FRS - process $group_67 - assign \X_FRS 5'00000 - assign \X_FRS { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \X_FRSp - process $group_68 - assign \X_FRSp 5'00000 - assign \X_FRSp { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \X_FRT - process $group_69 - assign \X_FRT 5'00000 - assign \X_FRT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \X_FRTp - process $group_70 - assign \X_FRTp 5'00000 - assign \X_FRTp { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 3 \X_IH - process $group_71 - assign \X_IH 3'000 - assign \X_IH { \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 8 \X_IMM8 - process $group_72 - assign \X_IMM8 8'00000000 - assign \X_IMM8 { \opcode_in [18] \opcode_in [17] \opcode_in [16] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 2 \X_L2 - process $group_73 - assign \X_L2 2'00 - assign \X_L2 { \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \X_L - process $group_74 - assign \X_L 1'0 - assign \X_L { \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \X_L1 - process $group_75 - assign \X_L1 1'0 - assign \X_L1 { \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 2 \X_L3 - process $group_76 - assign \X_L3 2'00 - assign \X_L3 { \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \X_MO - process $group_77 - assign \X_MO 5'00000 - assign \X_MO { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \X_NB - process $group_78 - assign \X_NB 5'00000 - assign \X_NB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \X_PRS - process $group_79 - assign \X_PRS 1'0 - assign \X_PRS { \opcode_in [17] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \X_R - process $group_80 - assign \X_R 1'0 - assign \X_R { \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \X_R_1 - process $group_81 - assign \X_R_1 1'0 - assign \X_R_1 { \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \X_RA - process $group_82 - assign \X_RA 5'00000 - assign \X_RA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \X_RB - process $group_83 - assign \X_RB 5'00000 - assign \X_RB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \X_Rc - process $group_84 - assign \X_Rc 1'0 - assign \X_Rc { \opcode_in [0] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 2 \X_RIC - process $group_85 - assign \X_RIC 2'00 - assign \X_RIC { \opcode_in [19] \opcode_in [18] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 2 \X_RM - process $group_86 - assign \X_RM 2'00 - assign \X_RM { \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \X_RO - process $group_87 - assign \X_RO 1'0 - assign \X_RO { \opcode_in [0] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \X_RS - process $group_88 - assign \X_RS 5'00000 - assign \X_RS { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \X_RSp - process $group_89 - assign \X_RSp 5'00000 - assign \X_RSp { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \X_RT - process $group_90 - assign \X_RT 5'00000 - assign \X_RT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \X_RTp - process $group_91 - assign \X_RTp 5'00000 - assign \X_RTp { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \X_S - process $group_92 - assign \X_S 5'00000 - assign \X_S { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \X_SH - process $group_93 - assign \X_SH 5'00000 - assign \X_SH { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \X_SI - process $group_94 - assign \X_SI 5'00000 - assign \X_SI { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 2 \X_SP - process $group_95 - assign \X_SP 2'00 - assign \X_SP { \opcode_in [20] \opcode_in [19] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 4 \X_SR - process $group_96 - assign \X_SR 4'0000 - assign \X_SR { \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \X_SX - process $group_97 - assign \X_SX 1'0 - assign \X_SX { \opcode_in [0] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 6 \X_SX_S - process $group_98 - assign \X_SX_S 6'000000 - assign \X_SX_S { \opcode_in [0] \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \X_T - process $group_99 - assign \X_T 5'00000 - assign \X_T { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 10 \X_TBR - process $group_100 - assign \X_TBR 10'0000000000 - assign \X_TBR { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \X_TH - process $group_101 - assign \X_TH 5'00000 - assign \X_TH { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \X_TO - process $group_102 - assign \X_TO 5'00000 - assign \X_TO { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \X_TX - process $group_103 - assign \X_TX 1'0 - assign \X_TX { \opcode_in [0] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 6 \X_TX_T - process $group_104 - assign \X_TX_T 6'000000 - assign \X_TX_T { \opcode_in [0] \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 4 \X_U - process $group_105 - assign \X_U 4'0000 - assign \X_U { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \X_UIM - process $group_106 - assign \X_UIM 5'00000 - assign \X_UIM { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \X_VRS - process $group_107 - assign \X_VRS 5'00000 - assign \X_VRS { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \X_VRT - process $group_108 - assign \X_VRT 5'00000 - assign \X_VRT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \X_W - process $group_109 - assign \X_W 1'0 - assign \X_W { \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 2 \X_WC - process $group_110 - assign \X_WC 2'00 - assign \X_WC { \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 10 \X_XO - process $group_111 - assign \X_XO 10'0000000000 - assign \X_XO { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 8 \X_XO_1 - process $group_112 - assign \X_XO_1 8'00000000 - assign \X_XO_1 { \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \B_AA - process $group_113 - assign \B_AA 1'0 - assign \B_AA { \opcode_in [1] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 14 \B_BD - process $group_114 - assign \B_BD 14'00000000000000 - assign \B_BD { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \B_BI - process $group_115 - assign \B_BI 5'00000 - assign \B_BI { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \B_BO - process $group_116 - assign \B_BO 5'00000 - assign \B_BO { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \B_LK - process $group_117 - assign \B_LK 1'0 - assign \B_LK { \opcode_in [0] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \I_AA - process $group_118 - assign \I_AA 1'0 - assign \I_AA { \opcode_in [1] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 24 \I_LI - process $group_119 - assign \I_LI 24'000000000000000000000000 - assign \I_LI { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \I_LK - process $group_120 - assign \I_LK 1'0 - assign \I_LK { \opcode_in [0] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \XX3_AX - process $group_121 - assign \XX3_AX 1'0 - assign \XX3_AX { \opcode_in [2] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \XX3_A - process $group_122 - assign \XX3_A 5'00000 - assign \XX3_A { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 6 \XX3_AX_A - process $group_123 - assign \XX3_AX_A 6'000000 - assign \XX3_AX_A { \opcode_in [2] \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 3 \XX3_BF - process $group_124 - assign \XX3_BF 3'000 - assign \XX3_BF { \opcode_in [25] \opcode_in [24] \opcode_in [23] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \XX3_BX - process $group_125 - assign \XX3_BX 1'0 - assign \XX3_BX { \opcode_in [1] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \XX3_B - process $group_126 - assign \XX3_B 5'00000 - assign \XX3_B { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 6 \XX3_BX_B - process $group_127 - assign \XX3_BX_B 6'000000 - assign \XX3_BX_B { \opcode_in [1] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 2 \XX3_DM - process $group_128 - assign \XX3_DM 2'00 - assign \XX3_DM { \opcode_in [9] \opcode_in [8] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \XX3_Rc - process $group_129 - assign \XX3_Rc 1'0 - assign \XX3_Rc { \opcode_in [10] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 2 \XX3_SHW - process $group_130 - assign \XX3_SHW 2'00 - assign \XX3_SHW { \opcode_in [9] \opcode_in [8] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \XX3_TX - process $group_131 - assign \XX3_TX 1'0 - assign \XX3_TX { \opcode_in [0] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \XX3_T - process $group_132 - assign \XX3_T 5'00000 - assign \XX3_T { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 6 \XX3_TX_T - process $group_133 - assign \XX3_TX_T 6'000000 - assign \XX3_TX_T { \opcode_in [0] \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 4 \XX3_XO - process $group_134 - assign \XX3_XO 4'0000 - assign \XX3_XO { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 8 \XX3_XO_1 - process $group_135 - assign \XX3_XO_1 8'00000000 - assign \XX3_XO_1 { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 9 \XX3_XO_2 - process $group_136 - assign \XX3_XO_2 9'000000000 - assign \XX3_XO_2 { \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \XX4_AX - process $group_137 - assign \XX4_AX 1'0 - assign \XX4_AX { \opcode_in [2] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \XX4_A - process $group_138 - assign \XX4_A 5'00000 - assign \XX4_A { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 6 \XX4_AX_A - process $group_139 - assign \XX4_AX_A 6'000000 - assign \XX4_AX_A { \opcode_in [2] \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \XX4_BX - process $group_140 - assign \XX4_BX 1'0 - assign \XX4_BX { \opcode_in [1] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \XX4_B - process $group_141 - assign \XX4_B 5'00000 - assign \XX4_B { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 6 \XX4_BX_B - process $group_142 - assign \XX4_BX_B 6'000000 - assign \XX4_BX_B { \opcode_in [1] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \XX4_CX - process $group_143 - assign \XX4_CX 1'0 - assign \XX4_CX { \opcode_in [3] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \XX4_C - process $group_144 - assign \XX4_C 5'00000 - assign \XX4_C { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 6 \XX4_CX_C - process $group_145 - assign \XX4_CX_C 6'000000 - assign \XX4_CX_C { \opcode_in [3] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \XX4_TX - process $group_146 - assign \XX4_TX 1'0 - assign \XX4_TX { \opcode_in [0] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \XX4_T - process $group_147 - assign \XX4_T 5'00000 - assign \XX4_T { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 6 \XX4_TX_T - process $group_148 - assign \XX4_TX_T 6'000000 - assign \XX4_TX_T { \opcode_in [0] \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 2 \XX4_XO - process $group_149 - assign \XX4_XO 2'00 - assign \XX4_XO { \opcode_in [5] \opcode_in [4] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \XL_BA - process $group_150 - assign \XL_BA 5'00000 - assign \XL_BA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \XL_BB - process $group_151 - assign \XL_BB 5'00000 - assign \XL_BB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 3 \XL_BF - process $group_152 - assign \XL_BF 3'000 - assign \XL_BF { \opcode_in [25] \opcode_in [24] \opcode_in [23] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 3 \XL_BFA - process $group_153 - assign \XL_BFA 3'000 - assign \XL_BFA { \opcode_in [20] \opcode_in [19] \opcode_in [18] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 2 \XL_BH - process $group_154 - assign \XL_BH 2'00 - assign \XL_BH { \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \XL_BI - process $group_155 - assign \XL_BI 5'00000 - assign \XL_BI { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \XL_BO - process $group_156 - assign \XL_BO 5'00000 - assign \XL_BO { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \XL_BO_1 - process $group_157 - assign \XL_BO_1 5'00000 - assign \XL_BO_1 { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - process $group_158 - assign \XL_BT 5'00000 - assign \XL_BT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \XL_LK - process $group_159 - assign \XL_LK 1'0 - assign \XL_LK { \opcode_in [0] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 15 \XL_OC - process $group_160 - assign \XL_OC 15'000000000000000 - assign \XL_OC { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \XL_S - process $group_161 - assign \XL_S 1'0 - assign \XL_S { \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 10 \XL_XO - process $group_162 - assign \XL_XO 10'0000000000 - assign \XL_XO { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \A_BC - process $group_163 - assign \A_BC 5'00000 - assign \A_BC { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \A_FRA - process $group_164 - assign \A_FRA 5'00000 - assign \A_FRA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \A_FRB - process $group_165 - assign \A_FRB 5'00000 - assign \A_FRB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \A_FRC - process $group_166 - assign \A_FRC 5'00000 - assign \A_FRC { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \A_FRT - process $group_167 - assign \A_FRT 5'00000 - assign \A_FRT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \A_RA - process $group_168 - assign \A_RA 5'00000 - assign \A_RA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \A_RB - process $group_169 - assign \A_RB 5'00000 - assign \A_RB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \A_Rc - process $group_170 - assign \A_Rc 1'0 - assign \A_Rc { \opcode_in [0] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \A_RT - process $group_171 - assign \A_RT 5'00000 - assign \A_RT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \A_XO - process $group_172 - assign \A_XO 5'00000 - assign \A_XO { \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 3 \D_BF - process $group_173 - assign \D_BF 3'000 - assign \D_BF { \opcode_in [25] \opcode_in [24] \opcode_in [23] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 16 \D_D - process $group_174 - assign \D_D 16'0000000000000000 - assign \D_D { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] \opcode_in [0] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \D_FRS - process $group_175 - assign \D_FRS 5'00000 - assign \D_FRS { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \D_FRT - process $group_176 - assign \D_FRT 5'00000 - assign \D_FRT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \D_L - process $group_177 - assign \D_L 1'0 - assign \D_L { \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \D_RA - process $group_178 - assign \D_RA 5'00000 - assign \D_RA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \D_RS - process $group_179 - assign \D_RS 5'00000 - assign \D_RS { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \D_RT - process $group_180 - assign \D_RT 5'00000 - assign \D_RT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 16 \D_SI - process $group_181 - assign \D_SI 16'0000000000000000 - assign \D_SI { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] \opcode_in [0] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \D_TO - process $group_182 - assign \D_TO 5'00000 - assign \D_TO { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 16 \D_UI - process $group_183 - assign \D_UI 16'0000000000000000 - assign \D_UI { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] \opcode_in [0] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 3 \XX2_BF - process $group_184 - assign \XX2_BF 3'000 - assign \XX2_BF { \opcode_in [25] \opcode_in [24] \opcode_in [23] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \XX2_BX - process $group_185 - assign \XX2_BX 1'0 - assign \XX2_BX { \opcode_in [1] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \XX2_B - process $group_186 - assign \XX2_B 5'00000 - assign \XX2_B { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 6 \XX2_BX_B - process $group_187 - assign \XX2_BX_B 6'000000 - assign \XX2_BX_B { \opcode_in [1] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \XX2_dc - process $group_188 - assign \XX2_dc 1'0 - assign \XX2_dc { \opcode_in [6] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \XX2_dm - process $group_189 - assign \XX2_dm 1'0 - assign \XX2_dm { \opcode_in [2] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \XX2_dx - process $group_190 - assign \XX2_dx 5'00000 - assign \XX2_dx { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 7 \XX2_dc_dm_dx - process $group_191 - assign \XX2_dc_dm_dx 7'0000000 - assign \XX2_dc_dm_dx { \opcode_in [6] \opcode_in [2] \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 7 \XX2_DCMX - process $group_192 - assign \XX2_DCMX 7'0000000 - assign \XX2_DCMX { \opcode_in [22] \opcode_in [21] \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \XX2_EO - process $group_193 - assign \XX2_EO 5'00000 - assign \XX2_EO { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \XX2_RT - process $group_194 - assign \XX2_RT 5'00000 - assign \XX2_RT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \XX2_TX - process $group_195 - assign \XX2_TX 1'0 - assign \XX2_TX { \opcode_in [0] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \XX2_T - process $group_196 - assign \XX2_T 5'00000 - assign \XX2_T { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 6 \XX2_TX_T - process $group_197 - assign \XX2_TX_T 6'000000 - assign \XX2_TX_T { \opcode_in [0] \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 4 \XX2_UIM - process $group_198 - assign \XX2_UIM 4'0000 - assign \XX2_UIM { \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 2 \XX2_UIM_1 - process $group_199 - assign \XX2_UIM_1 2'00 - assign \XX2_UIM_1 { \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 7 \XX2_XO - process $group_200 - assign \XX2_XO 7'0000000 - assign \XX2_XO { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [5] \opcode_in [4] \opcode_in [3] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 9 \XX2_XO_1 - process $group_201 - assign \XX2_XO_1 9'000000000 - assign \XX2_XO_1 { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 3 \Z22_BF - process $group_202 - assign \Z22_BF 3'000 - assign \Z22_BF { \opcode_in [25] \opcode_in [24] \opcode_in [23] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 6 \Z22_DCM - process $group_203 - assign \Z22_DCM 6'000000 - assign \Z22_DCM { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 6 \Z22_DGM - process $group_204 - assign \Z22_DGM 6'000000 - assign \Z22_DGM { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \Z22_FRA - process $group_205 - assign \Z22_FRA 5'00000 - assign \Z22_FRA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \Z22_FRAp - process $group_206 - assign \Z22_FRAp 5'00000 - assign \Z22_FRAp { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \Z22_FRT - process $group_207 - assign \Z22_FRT 5'00000 - assign \Z22_FRT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \Z22_FRTp - process $group_208 - assign \Z22_FRTp 5'00000 - assign \Z22_FRTp { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \Z22_Rc - process $group_209 - assign \Z22_Rc 1'0 - assign \Z22_Rc { \opcode_in [0] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 6 \Z22_SH - process $group_210 - assign \Z22_SH 6'000000 - assign \Z22_SH { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 9 \Z22_XO - process $group_211 - assign \Z22_XO 9'000000000 - assign \Z22_XO { \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 3 \EVS_BFA - process $group_212 - assign \EVS_BFA 3'000 - assign \EVS_BFA { \opcode_in [2] \opcode_in [1] \opcode_in [0] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 10 \XFX_BHRBE - process $group_213 - assign \XFX_BHRBE 10'0000000000 - assign \XFX_BHRBE { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \XFX_DUI - process $group_214 - assign \XFX_DUI 5'00000 - assign \XFX_DUI { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 10 \XFX_DUIS - process $group_215 - assign \XFX_DUIS 10'0000000000 - assign \XFX_DUIS { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 8 \XFX_FXM - process $group_216 - assign \XFX_FXM 8'00000000 - assign \XFX_FXM { \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \XFX_RS - process $group_217 - assign \XFX_RS 5'00000 - assign \XFX_RS { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \XFX_RT - process $group_218 - assign \XFX_RT 5'00000 - assign \XFX_RT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 10 \XFX_SPR - process $group_219 - assign \XFX_SPR 10'0000000000 - assign \XFX_SPR { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 10 \XFX_XO - process $group_220 - assign \XFX_XO 10'0000000000 - assign \XFX_XO { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 10 \DX_d0 - process $group_221 - assign \DX_d0 10'0000000000 - assign \DX_d0 { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \DX_d1 - process $group_222 - assign \DX_d1 5'00000 - assign \DX_d1 { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \DX_d2 - process $group_223 - assign \DX_d2 1'0 - assign \DX_d2 { \opcode_in [0] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 16 \DX_d0_d1_d2 - process $group_224 - assign \DX_d0_d1_d2 16'0000000000000000 - assign \DX_d0_d1_d2 { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] \opcode_in [0] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \DX_RT - process $group_225 - assign \DX_RT 5'00000 - assign \DX_RT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \DX_XO - process $group_226 - assign \DX_XO 5'00000 - assign \DX_XO { \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 12 \DQ_DQ - process $group_227 - assign \DQ_DQ 12'000000000000 - assign \DQ_DQ { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 4 \DQ_PT - process $group_228 - assign \DQ_PT 4'0000 - assign \DQ_PT { \opcode_in [3] \opcode_in [2] \opcode_in [1] \opcode_in [0] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \DQ_RA - process $group_229 - assign \DQ_RA 5'00000 - assign \DQ_RA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \DQ_RTp - process $group_230 - assign \DQ_RTp 5'00000 - assign \DQ_RTp { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \DQ_SX - process $group_231 - assign \DQ_SX 1'0 - assign \DQ_SX { \opcode_in [3] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \DQ_S - process $group_232 - assign \DQ_S 5'00000 - assign \DQ_S { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 6 \DQ_SX_S - process $group_233 - assign \DQ_SX_S 6'000000 - assign \DQ_SX_S { \opcode_in [3] \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \DQ_TX - process $group_234 - assign \DQ_TX 1'0 - assign \DQ_TX { \opcode_in [3] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \DQ_T - process $group_235 - assign \DQ_T 5'00000 - assign \DQ_T { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 6 \DQ_TX_T - process $group_236 - assign \DQ_TX_T 6'000000 - assign \DQ_TX_T { \opcode_in [3] \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 3 \DQ_XO - process $group_237 - assign \DQ_XO 3'000 - assign \DQ_XO { \opcode_in [2] \opcode_in [1] \opcode_in [0] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 14 \DS_DS - process $group_238 - assign \DS_DS 14'00000000000000 - assign \DS_DS { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \DS_FRSp - process $group_239 - assign \DS_FRSp 5'00000 - assign \DS_FRSp { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \DS_FRTp - process $group_240 - assign \DS_FRTp 5'00000 - assign \DS_FRTp { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \DS_RA - process $group_241 - assign \DS_RA 5'00000 - assign \DS_RA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \DS_RS - process $group_242 - assign \DS_RS 5'00000 - assign \DS_RS { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \DS_RSp - process $group_243 - assign \DS_RSp 5'00000 - assign \DS_RSp { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \DS_RT - process $group_244 - assign \DS_RT 5'00000 - assign \DS_RT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \DS_VRS - process $group_245 - assign \DS_VRS 5'00000 - assign \DS_VRS { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \DS_VRT - process $group_246 - assign \DS_VRT 5'00000 - assign \DS_VRT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 2 \DS_XO - process $group_247 - assign \DS_XO 2'00 - assign \DS_XO { \opcode_in [1] \opcode_in [0] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \VX_EO - process $group_248 - assign \VX_EO 5'00000 - assign \VX_EO { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \VX_PS - process $group_249 - assign \VX_PS 1'0 - assign \VX_PS { \opcode_in [9] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \VX_RA - process $group_250 - assign \VX_RA 5'00000 - assign \VX_RA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \VX_RT - process $group_251 - assign \VX_RT 5'00000 - assign \VX_RT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \VX_SIM - process $group_252 - assign \VX_SIM 5'00000 - assign \VX_SIM { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \VX_UIM - process $group_253 - assign \VX_UIM 5'00000 - assign \VX_UIM { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 4 \VX_UIM_1 - process $group_254 - assign \VX_UIM_1 4'0000 - assign \VX_UIM_1 { \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 3 \VX_UIM_2 - process $group_255 - assign \VX_UIM_2 3'000 - assign \VX_UIM_2 { \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 2 \VX_UIM_3 - process $group_256 - assign \VX_UIM_3 2'00 - assign \VX_UIM_3 { \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \VX_VRA - process $group_257 - assign \VX_VRA 5'00000 - assign \VX_VRA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \VX_VRB - process $group_258 - assign \VX_VRB 5'00000 - assign \VX_VRB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \VX_VRT - process $group_259 - assign \VX_VRT 5'00000 - assign \VX_VRT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 10 \VX_XO - process $group_260 - assign \VX_XO 10'0000000000 - assign \VX_XO { \opcode_in [10] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] \opcode_in [0] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 11 \VX_XO_1 - process $group_261 - assign \VX_XO_1 11'00000000000 - assign \VX_XO_1 { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] \opcode_in [0] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 8 \XFL_FLM - process $group_262 - assign \XFL_FLM 8'00000000 - assign \XFL_FLM { \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \XFL_FRB - process $group_263 - assign \XFL_FRB 5'00000 - assign \XFL_FRB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \XFL_L - process $group_264 - assign \XFL_L 1'0 - assign \XFL_L { \opcode_in [25] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \XFL_Rc - process $group_265 - assign \XFL_Rc 1'0 - assign \XFL_Rc { \opcode_in [0] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \XFL_W - process $group_266 - assign \XFL_W 1'0 - assign \XFL_W { \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 10 \XFL_XO - process $group_267 - assign \XFL_XO 10'0000000000 - assign \XFL_XO { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \Z23_FRA - process $group_268 - assign \Z23_FRA 5'00000 - assign \Z23_FRA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \Z23_FRAp - process $group_269 - assign \Z23_FRAp 5'00000 - assign \Z23_FRAp { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \Z23_FRB - process $group_270 - assign \Z23_FRB 5'00000 - assign \Z23_FRB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \Z23_FRBp - process $group_271 - assign \Z23_FRBp 5'00000 - assign \Z23_FRBp { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \Z23_FRT - process $group_272 - assign \Z23_FRT 5'00000 - assign \Z23_FRT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \Z23_FRTp - process $group_273 - assign \Z23_FRTp 5'00000 - assign \Z23_FRTp { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \Z23_R - process $group_274 - assign \Z23_R 1'0 - assign \Z23_R { \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \Z23_Rc - process $group_275 - assign \Z23_Rc 1'0 - assign \Z23_Rc { \opcode_in [0] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 2 \Z23_RMC - process $group_276 - assign \Z23_RMC 2'00 - assign \Z23_RMC { \opcode_in [10] \opcode_in [9] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \Z23_TE - process $group_277 - assign \Z23_TE 5'00000 - assign \Z23_TE { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 8 \Z23_XO - process $group_278 - assign \Z23_XO 8'00000000 - assign \Z23_XO { \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \MDS_IB - process $group_279 - assign \MDS_IB 5'00000 - assign \MDS_IB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \MDS_IS - process $group_280 - assign \MDS_IS 5'00000 - assign \MDS_IS { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 6 \MDS_mb - process $group_281 - assign \MDS_mb 6'000000 - assign \MDS_mb { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 6 \MDS_me - process $group_282 - assign \MDS_me 6'000000 - assign \MDS_me { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \MDS_RA - process $group_283 - assign \MDS_RA 5'00000 - assign \MDS_RA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \MDS_RB - process $group_284 - assign \MDS_RB 5'00000 - assign \MDS_RB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \MDS_Rc - process $group_285 - assign \MDS_Rc 1'0 - assign \MDS_Rc { \opcode_in [0] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \MDS_RS - process $group_286 - assign \MDS_RS 5'00000 - assign \MDS_RS { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 4 \MDS_XBI - process $group_287 - assign \MDS_XBI 4'0000 - assign \MDS_XBI { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 4 \MDS_XBI_1 - process $group_288 - assign \MDS_XBI_1 4'0000 - assign \MDS_XBI_1 { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 4 \MDS_XO - process $group_289 - assign \MDS_XO 4'0000 - assign \MDS_XO { \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 7 \SC_LEV - process $group_290 - assign \SC_LEV 7'0000000 - assign \SC_LEV { \opcode_in [11] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \SC_XO - process $group_291 - assign \SC_XO 1'0 - assign \SC_XO { \opcode_in [1] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 2 \SC_XO_1 - process $group_292 - assign \SC_XO_1 2'00 - assign \SC_XO_1 { \opcode_in [1] \opcode_in [0] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \M_MB - process $group_293 - assign \M_MB 5'00000 - assign \M_MB { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \M_ME - process $group_294 - assign \M_ME 5'00000 - assign \M_ME { \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \M_RA - process $group_295 - assign \M_RA 5'00000 - assign \M_RA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \M_RB - process $group_296 - assign \M_RB 5'00000 - assign \M_RB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \M_Rc - process $group_297 - assign \M_Rc 1'0 - assign \M_Rc { \opcode_in [0] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \M_RS - process $group_298 - assign \M_RS 5'00000 - assign \M_RS { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \M_SH - process $group_299 - assign \M_SH 5'00000 - assign \M_SH { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 6 \MD_mb - process $group_300 - assign \MD_mb 6'000000 - assign \MD_mb { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 6 \MD_me - process $group_301 - assign \MD_me 6'000000 - assign \MD_me { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \MD_RA - process $group_302 - assign \MD_RA 5'00000 - assign \MD_RA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \MD_Rc - process $group_303 - assign \MD_Rc 1'0 - assign \MD_Rc { \opcode_in [0] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \MD_RS - process $group_304 - assign \MD_RS 5'00000 - assign \MD_RS { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 6 \MD_sh - process $group_305 - assign \MD_sh 6'000000 - assign \MD_sh { \opcode_in [1] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 3 \MD_XO - process $group_306 - assign \MD_XO 3'000 - assign \MD_XO { \opcode_in [4] \opcode_in [3] \opcode_in [2] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 6 \all_OPCD - process $group_307 - assign \all_OPCD 6'000000 - assign \all_OPCD { \opcode_in [31] \opcode_in [30] \opcode_in [29] \opcode_in [28] \opcode_in [27] \opcode_in [26] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 6 \all_PO - process $group_308 - assign \all_PO 6'000000 - assign \all_PO { \opcode_in [31] \opcode_in [30] \opcode_in [29] \opcode_in [28] \opcode_in [27] \opcode_in [26] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \XO_OE - process $group_309 - assign \XO_OE 1'0 - assign \XO_OE { \opcode_in [10] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \XO_RA - process $group_310 - assign \XO_RA 5'00000 - assign \XO_RA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \XO_RB - process $group_311 - assign \XO_RB 5'00000 - assign \XO_RB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \XO_Rc - process $group_312 - assign \XO_Rc 1'0 - assign \XO_Rc { \opcode_in [0] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \XO_RT - process $group_313 - assign \XO_RT 5'00000 - assign \XO_RT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 9 \XO_XO - process $group_314 - assign \XO_XO 9'000000000 - assign \XO_XO { \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \DQE_RA - process $group_315 - assign \DQE_RA 5'00000 - assign \DQE_RA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \DQE_RT - process $group_316 - assign \DQE_RT 5'00000 - assign \DQE_RT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 2 \DQE_XO - process $group_317 - assign \DQE_XO 2'00 - assign \DQE_XO { \opcode_in [1] \opcode_in [0] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \TX_RA - process $group_318 - assign \TX_RA 5'00000 - assign \TX_RA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \TX_UI - process $group_319 - assign \TX_UI 5'00000 - assign \TX_UI { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 4 \TX_XBI - process $group_320 - assign \TX_XBI 4'0000 - assign \TX_XBI { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 6 \TX_XO - process $group_321 - assign \TX_XO 6'000000 - assign \TX_XO { \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \VA_RA - process $group_322 - assign \VA_RA 5'00000 - assign \VA_RA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \VA_RB - process $group_323 - assign \VA_RB 5'00000 - assign \VA_RB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \VA_RC - process $group_324 - assign \VA_RC 5'00000 - assign \VA_RC { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \VA_RT - process $group_325 - assign \VA_RT 5'00000 - assign \VA_RT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 4 \VA_SHB - process $group_326 - assign \VA_SHB 4'0000 - assign \VA_SHB { \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \VA_VRA - process $group_327 - assign \VA_VRA 5'00000 - assign \VA_VRA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \VA_VRB - process $group_328 - assign \VA_VRB 5'00000 - assign \VA_VRB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \VA_VRC - process $group_329 - assign \VA_VRC 5'00000 - assign \VA_VRC { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \VA_VRT - process $group_330 - assign \VA_VRT 5'00000 - assign \VA_VRT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 6 \VA_XO - process $group_331 - assign \VA_XO 6'000000 - assign \VA_XO { \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] \opcode_in [0] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \XS_RA - process $group_332 - assign \XS_RA 5'00000 - assign \XS_RA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \XS_Rc - process $group_333 - assign \XS_Rc 1'0 - assign \XS_Rc { \opcode_in [0] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \XS_RS - process $group_334 - assign \XS_RS 5'00000 - assign \XS_RS { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 6 \XS_sh - process $group_335 - assign \XS_sh 6'000000 - assign \XS_sh { \opcode_in [1] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 9 \XS_XO - process $group_336 - assign \XS_XO 9'000000000 - assign \XS_XO { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \VC_Rc - process $group_337 - assign \VC_Rc 1'0 - assign \VC_Rc { \opcode_in [10] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \VC_VRA - process $group_338 - assign \VC_VRA 5'00000 - assign \VC_VRA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \VC_VRB - process $group_339 - assign \VC_VRB 5'00000 - assign \VC_VRB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \VC_VRT - process $group_340 - assign \VC_VRT 5'00000 - assign \VC_VRT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 10 \VC_XO - process $group_341 - assign \VC_XO 10'0000000000 - assign \VC_XO { \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] \opcode_in [0] } - sync init - end - connect \MUL_function_unit$1 11'00000000000 - connect \MUL_function_unit$2 11'00000000000 - connect \MUL_function_unit$3 11'00000000000 - connect \MUL_function_unit$4 11'00000000000 - connect \MUL_internal_op$5 7'0000000 - connect \MUL_internal_op$6 7'0000000 - connect \MUL_internal_op$7 7'0000000 - connect \MUL_internal_op$8 7'0000000 - connect \MUL_in2_sel$9 4'0000 - connect \MUL_in2_sel$10 4'0000 - connect \MUL_in2_sel$11 4'0000 - connect \MUL_in2_sel$12 4'0000 - connect \MUL_cr_in$13 3'000 - connect \MUL_cr_in$14 3'000 - connect \MUL_cr_in$15 3'000 - connect \MUL_cr_in$16 3'000 - connect \MUL_cr_out$17 3'000 - connect \MUL_cr_out$18 3'000 - connect \MUL_cr_out$19 3'000 - connect \MUL_cr_out$20 3'000 - connect \MUL_rc_sel$21 2'00 - connect \MUL_rc_sel$22 2'00 - connect \MUL_rc_sel$23 2'00 - connect \MUL_rc_sel$24 2'00 - connect \MUL_is_32b$25 1'0 - connect \MUL_is_32b$26 1'0 - connect \MUL_is_32b$27 1'0 - connect \MUL_is_32b$28 1'0 - connect \MUL_sgn$29 1'0 - connect \MUL_sgn$30 1'0 - connect \MUL_sgn$31 1'0 - connect \MUL_sgn$32 1'0 -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.dec_MUL.dec_rc" -module \dec_rc$178 - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:404" - wire width 2 input 0 \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 1 \rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 2 \rc_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 1 input 3 \MUL_Rc - process $group_0 - assign \rc 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:413" - switch \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:414" - attribute \nmigen.decoding "RC/2" - case 2'10 - assign \rc \MUL_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:417" - attribute \nmigen.decoding "ONE/1" - case 2'01 - assign \rc 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:420" - attribute \nmigen.decoding "NONE/0" - case 2'00 - assign \rc 1'0 - end - sync init - end - process $group_1 - assign \rc_ok 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:413" - switch \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:414" - attribute \nmigen.decoding "RC/2" - case 2'10 - assign \rc_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:417" - attribute \nmigen.decoding "ONE/1" - case 2'01 - assign \rc_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:420" - attribute \nmigen.decoding "NONE/0" - case 2'00 - assign \rc_ok 1'1 - end - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.dec_MUL.dec_oe" -module \dec_oe$179 - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:441" - wire width 2 input 0 \sel_in - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 7 input 1 \MUL_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 2 \oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 3 \oe_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 1 input 4 \MUL_OE - process $group_0 - assign \oe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:450" - switch \MUL_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:461" - attribute \nmigen.decoding "OP_MUL_H64/51|OP_MUL_H32/52|OP_EXTS/31|OP_CNTZ/14|OP_SHL/60|OP_SHR/61|OP_RLC/56|OP_LOAD/37|OP_STORE/38|OP_RLCL/57|OP_RLCR/58|OP_EXTSWSLI/32" - case 7'0110011, 7'0110100, 7'0011111, 7'0001110, 7'0111100, 7'0111101, 7'0111000, 7'0100101, 7'0100110, 7'0111001, 7'0111010, 7'0100000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:465" - attribute \nmigen.decoding "" - case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:467" - switch \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:468" - attribute \nmigen.decoding "RC/2" - case 2'10 - assign \oe \MUL_OE - end - end - sync init - end - process $group_1 - assign \oe_ok 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:450" - switch \MUL_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:461" - attribute \nmigen.decoding "OP_MUL_H64/51|OP_MUL_H32/52|OP_EXTS/31|OP_CNTZ/14|OP_SHL/60|OP_SHR/61|OP_RLC/56|OP_LOAD/37|OP_STORE/38|OP_RLCL/57|OP_RLCR/58|OP_EXTSWSLI/32" - case 7'0110011, 7'0110100, 7'0011111, 7'0001110, 7'0111100, 7'0111101, 7'0111000, 7'0100101, 7'0100110, 7'0111001, 7'0111010, 7'0100000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:465" - attribute \nmigen.decoding "" - case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:467" - switch \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:468" - attribute \nmigen.decoding "RC/2" - case 2'10 - assign \oe_ok 1'1 - end - end - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.dec_MUL.dec_cr_in.ppick" -module \ppick$181 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" - wire width 8 input 0 \i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" - wire width 8 output 1 \o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:49" - wire width 8 \ni - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" - wire width 8 $1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" - cell $not $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \Y_WIDTH 8 - connect \A { \i [0] \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] } - connect \Y $1 - end - process $group_0 - assign \ni 8'00000000 - assign \ni $1 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire width 1 \t0 - process $group_1 - assign \t0 1'0 - assign \t0 \i [7] - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire width 1 \t1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire width 1 $3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire width 1 $4 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_bool $5 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A { \i [7] \ni [1] } - connect \Y $4 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $6 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $4 - connect \Y $3 - end - process $group_2 - assign \t1 1'0 - assign \t1 $3 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire width 1 \t2 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire width 1 $7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire width 1 $8 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_bool $9 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A { \i [6] \i [7] \ni [2] } - connect \Y $8 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $10 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $8 - connect \Y $7 - end - process $group_3 - assign \t2 1'0 - assign \t2 $7 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire width 1 \t3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire width 1 $11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire width 1 $12 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_bool $13 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A { \i [5] \i [6] \i [7] \ni [3] } - connect \Y $12 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $14 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $12 - connect \Y $11 - end - process $group_4 - assign \t3 1'0 - assign \t3 $11 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire width 1 \t4 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire width 1 $15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire width 1 $16 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_bool $17 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A { \i [4] \i [5] \i [6] \i [7] \ni [4] } - connect \Y $16 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $18 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $16 - connect \Y $15 - end - process $group_5 - assign \t4 1'0 - assign \t4 $15 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire width 1 \t5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire width 1 $19 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire width 1 $20 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_bool $21 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \Y_WIDTH 1 - connect \A { \i [3] \i [4] \i [5] \i [6] \i [7] \ni [5] } - connect \Y $20 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $22 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $20 - connect \Y $19 - end - process $group_6 - assign \t5 1'0 - assign \t5 $19 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire width 1 \t6 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire width 1 $23 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire width 1 $24 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_bool $25 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A { \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [6] } - connect \Y $24 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $26 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $24 - connect \Y $23 - end - process $group_7 - assign \t6 1'0 - assign \t6 $23 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire width 1 \t7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire width 1 $27 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire width 1 $28 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_bool $29 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A { \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [7] } - connect \Y $28 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $30 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $28 - connect \Y $27 - end - process $group_8 - assign \t7 1'0 - assign \t7 $27 - sync init - end - process $group_9 - assign \o 8'00000000 - assign \o { \t0 \t1 \t2 \t3 \t4 \t5 \t6 \t7 } - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" - wire width 1 \en_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" - wire width 1 $31 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" - cell $reduce_bool $32 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \o - connect \Y $31 - end - process $group_10 - assign \en_o 1'0 - assign \en_o $31 - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.dec_MUL.dec_cr_in" -module \dec_cr_in$180 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:485" - wire width 32 input 0 \insn_in - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:484" - wire width 3 input 1 \sel_in - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 7 input 2 \MUL_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 5 input 3 \MUL_BB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 5 input 4 \MUL_BA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 5 input 5 \MUL_BT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 8 input 6 \MUL_FXM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 5 input 7 \MUL_BI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 5 input 8 \MUL_BC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 3 input 9 \X_BFA - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" - wire width 8 \ppick_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" - wire width 8 \ppick_o - cell \ppick$181 \ppick - connect \i \ppick_i - connect \o \ppick_o - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \cr_bitfield_ok - process $group_0 - assign \cr_bitfield_ok 1'0 - assign \cr_bitfield_ok 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" - switch \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" - attribute \nmigen.decoding "NONE/0" - case 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:505" - attribute \nmigen.decoding "CR0/1" - case 3'001 - assign \cr_bitfield_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:508" - attribute \nmigen.decoding "BI/2" - case 3'010 - assign \cr_bitfield_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:511" - attribute \nmigen.decoding "BFA/3" - case 3'011 - assign \cr_bitfield_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:514" - attribute \nmigen.decoding "BA_BB/4" - case 3'100 - assign \cr_bitfield_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:521" - attribute \nmigen.decoding "BC/5" - case 3'101 - assign \cr_bitfield_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:524" - attribute \nmigen.decoding "WHOLE_REG/6" - case 3'110 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \cr_bitfield_b_ok - process $group_1 - assign \cr_bitfield_b_ok 1'0 - assign \cr_bitfield_b_ok 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" - switch \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" - attribute \nmigen.decoding "NONE/0" - case 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:505" - attribute \nmigen.decoding "CR0/1" - case 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:508" - attribute \nmigen.decoding "BI/2" - case 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:511" - attribute \nmigen.decoding "BFA/3" - case 3'011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:514" - attribute \nmigen.decoding "BA_BB/4" - case 3'100 - assign \cr_bitfield_b_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:521" - attribute \nmigen.decoding "BC/5" - case 3'101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:524" - attribute \nmigen.decoding "WHOLE_REG/6" - case 3'110 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \cr_fxm_ok - process $group_2 - assign \cr_fxm_ok 1'0 - assign \cr_fxm_ok 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" - switch \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" - attribute \nmigen.decoding "NONE/0" - case 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:505" - attribute \nmigen.decoding "CR0/1" - case 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:508" - attribute \nmigen.decoding "BI/2" - case 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:511" - attribute \nmigen.decoding "BFA/3" - case 3'011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:514" - attribute \nmigen.decoding "BA_BB/4" - case 3'100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:521" - attribute \nmigen.decoding "BC/5" - case 3'101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:524" - attribute \nmigen.decoding "WHOLE_REG/6" - case 3'110 - assign \cr_fxm_ok 1'1 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 3 \cr_bitfield - process $group_3 - assign \cr_bitfield 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" - switch \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" - attribute \nmigen.decoding "NONE/0" - case 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:505" - attribute \nmigen.decoding "CR0/1" - case 3'001 - assign \cr_bitfield 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:508" - attribute \nmigen.decoding "BI/2" - case 3'010 - assign \cr_bitfield \MUL_BI [4:2] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:511" - attribute \nmigen.decoding "BFA/3" - case 3'011 - assign \cr_bitfield \X_BFA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:514" - attribute \nmigen.decoding "BA_BB/4" - case 3'100 - assign \cr_bitfield \MUL_BA [4:2] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:521" - attribute \nmigen.decoding "BC/5" - case 3'101 - assign \cr_bitfield \MUL_BC [4:2] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:524" - attribute \nmigen.decoding "WHOLE_REG/6" - case 3'110 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 3 \cr_bitfield_b - process $group_4 - assign \cr_bitfield_b 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" - switch \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" - attribute \nmigen.decoding "NONE/0" - case 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:505" - attribute \nmigen.decoding "CR0/1" - case 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:508" - attribute \nmigen.decoding "BI/2" - case 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:511" - attribute \nmigen.decoding "BFA/3" - case 3'011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:514" - attribute \nmigen.decoding "BA_BB/4" - case 3'100 - assign \cr_bitfield_b \MUL_BB [4:2] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:521" - attribute \nmigen.decoding "BC/5" - case 3'101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:524" - attribute \nmigen.decoding "WHOLE_REG/6" - case 3'110 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 3 \cr_bitfield_o - process $group_5 - assign \cr_bitfield_o 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" - switch \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" - attribute \nmigen.decoding "NONE/0" - case 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:505" - attribute \nmigen.decoding "CR0/1" - case 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:508" - attribute \nmigen.decoding "BI/2" - case 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:511" - attribute \nmigen.decoding "BFA/3" - case 3'011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:514" - attribute \nmigen.decoding "BA_BB/4" - case 3'100 - assign \cr_bitfield_o \MUL_BT [4:2] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:521" - attribute \nmigen.decoding "BC/5" - case 3'101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:524" - attribute \nmigen.decoding "WHOLE_REG/6" - case 3'110 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \cr_bitfield_o_ok - process $group_6 - assign \cr_bitfield_o_ok 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" - switch \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" - attribute \nmigen.decoding "NONE/0" - case 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:505" - attribute \nmigen.decoding "CR0/1" - case 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:508" - attribute \nmigen.decoding "BI/2" - case 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:511" - attribute \nmigen.decoding "BFA/3" - case 3'011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:514" - attribute \nmigen.decoding "BA_BB/4" - case 3'100 - assign \cr_bitfield_o_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:521" - attribute \nmigen.decoding "BC/5" - case 3'101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:524" - attribute \nmigen.decoding "WHOLE_REG/6" - case 3'110 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:526" - wire width 1 \move_one - process $group_7 - assign \move_one 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" - switch \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" - attribute \nmigen.decoding "NONE/0" - case 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:505" - attribute \nmigen.decoding "CR0/1" - case 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:508" - attribute \nmigen.decoding "BI/2" - case 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:511" - attribute \nmigen.decoding "BFA/3" - case 3'011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:514" - attribute \nmigen.decoding "BA_BB/4" - case 3'100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:521" - attribute \nmigen.decoding "BC/5" - case 3'101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:524" - attribute \nmigen.decoding "WHOLE_REG/6" - case 3'110 - assign \move_one \insn_in [20] - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" - cell $eq $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A \MUL_internal_op - connect \B 7'0101101 - connect \Y $1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" - wire width 1 $3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" - cell $and $4 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $1 - connect \B \move_one - connect \Y $3 - end - process $group_8 - assign \ppick_i 8'00000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" - switch \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" - attribute \nmigen.decoding "NONE/0" - case 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:505" - attribute \nmigen.decoding "CR0/1" - case 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:508" - attribute \nmigen.decoding "BI/2" - case 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:511" - attribute \nmigen.decoding "BFA/3" - case 3'011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:514" - attribute \nmigen.decoding "BA_BB/4" - case 3'100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:521" - attribute \nmigen.decoding "BC/5" - case 3'101 - attribute \src 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attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 3 \cr_bitfield - process $group_2 - assign \cr_bitfield 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:563" - switch \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:564" - attribute \nmigen.decoding "NONE/0" - case 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:566" - attribute \nmigen.decoding "CR0/1" - case 3'001 - assign \cr_bitfield 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:569" - attribute \nmigen.decoding "BF/2" - case 3'010 - assign \cr_bitfield \X_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:572" - attribute \nmigen.decoding "BT/3" - case 3'011 - assign \cr_bitfield \XL_BT [4:2] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:575" - attribute \nmigen.decoding "WHOLE_REG/4" - case 3'100 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:577" - wire width 1 \move_one - process $group_3 - assign \move_one 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:563" - switch \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:564" - attribute \nmigen.decoding "NONE/0" - case 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:566" - attribute \nmigen.decoding "CR0/1" - case 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:569" - attribute \nmigen.decoding "BF/2" - case 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:572" - attribute \nmigen.decoding "BT/3" - case 3'011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:575" - attribute \nmigen.decoding "WHOLE_REG/4" - case 3'100 - assign \move_one \insn_in [20] - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:579" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:579" - cell $eq $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A \MUL_internal_op - connect \B 7'0110000 - connect \Y $1 - end - process $group_4 - assign \ppick_i 8'00000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:563" - switch \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:564" - attribute \nmigen.decoding "NONE/0" - case 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:566" - attribute \nmigen.decoding "CR0/1" - case 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:569" - attribute \nmigen.decoding "BF/2" - case 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:572" - attribute \nmigen.decoding "BT/3" - case 3'011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:575" - attribute \nmigen.decoding "WHOLE_REG/4" - case 3'100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:579" - switch { $1 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:579" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:580" - switch { \move_one } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:580" - case 1'1 - assign \ppick_i \MUL_FXM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:587" - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:589" - case - end - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 8 \cr_fxm - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:579" - wire width 1 $3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:579" - cell $eq $4 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A \MUL_internal_op - connect \B 7'0110000 - connect \Y $3 - end - process $group_5 - assign \cr_fxm 8'00000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:563" - switch \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:564" - attribute \nmigen.decoding "NONE/0" - case 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:566" - attribute \nmigen.decoding "CR0/1" - case 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:569" - attribute \nmigen.decoding "BF/2" - case 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:572" - attribute \nmigen.decoding "BT/3" - case 3'011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:575" - attribute \nmigen.decoding "WHOLE_REG/4" - case 3'100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:579" - switch { $3 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:579" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:580" - switch { \move_one } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:580" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:583" - switch { \ppick_en_o } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:583" - case 1'1 - assign \cr_fxm \ppick_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:585" - case - assign \cr_fxm 8'00000001 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:587" - case - assign \cr_fxm \MUL_FXM - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:589" - case - assign \cr_fxm 8'11111111 - end - end - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.dec_MUL.dec_bi" -module \dec_bi$184 - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:216" - wire width 4 input 0 \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 output 1 \imm_b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 2 \imm_b_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 16 input 3 \MUL_SI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 16 input 4 \MUL_UI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 5 input 5 \MUL_SH32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 6 input 6 \MUL_sh - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 24 input 7 \MUL_LI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 14 input 8 \MUL_BD - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 14 input 9 \MUL_DS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 64 $1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - cell $pos $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 16 - parameter \Y_WIDTH 64 - connect \A \MUL_UI - connect \Y $1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:229" - wire width 16 \si - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:234" - wire width 32 \si_hi - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:241" - wire width 64 $3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:239" - wire width 16 \ui - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:241" - wire width 47 $4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:241" - cell $sshl $5 - parameter \A_SIGNED 0 - parameter \A_WIDTH 16 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 47 - connect \A \ui - connect \B 5'10000 - connect \Y $4 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:241" - cell $pos $6 - parameter \A_SIGNED 0 - parameter \A_WIDTH 47 - parameter \Y_WIDTH 64 - connect \A $4 - connect \Y $3 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" - wire width 26 \li - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:249" - wire width 16 \bd - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:254" - wire width 16 \ds - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:259" - wire width 64 $7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:259" - cell $not $8 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \Y_WIDTH 64 - connect \A 64'0000000000000000000000000000000000000000000000000000000000000000 - connect \Y $7 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 64 $9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - cell $pos $10 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \Y_WIDTH 64 - connect \A \MUL_sh - connect \Y $9 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 64 $11 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - cell $pos $12 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \Y_WIDTH 64 - connect \A \MUL_SH32 - connect \Y $11 - end - process $group_0 - assign \imm_b 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:224" - switch \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:225" - attribute \nmigen.decoding "CONST_UI/2" - case 4'0010 - assign \imm_b $1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:228" - attribute \nmigen.decoding "CONST_SI/3" - case 4'0011 - assign \imm_b { { \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] } \si } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:233" - attribute \nmigen.decoding "CONST_SI_HI/5" - case 4'0101 - assign \imm_b { { \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] } \si_hi } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:238" - attribute \nmigen.decoding "CONST_UI_HI/4" - case 4'0100 - assign \imm_b $3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:243" - attribute \nmigen.decoding "CONST_LI/6" - case 4'0110 - assign \imm_b { { \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] } \li } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:248" - attribute \nmigen.decoding "CONST_BD/7" - case 4'0111 - assign \imm_b { { \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] } \bd } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:253" - attribute \nmigen.decoding "CONST_DS/8" - case 4'1000 - assign \imm_b { { \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] } \ds } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:258" - attribute \nmigen.decoding "CONST_M1/9" - case 4'1001 - assign \imm_b $7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" - attribute \nmigen.decoding "CONST_SH/10" - case 4'1010 - assign \imm_b $9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:264" - attribute \nmigen.decoding "CONST_SH32/11" - case 4'1011 - assign \imm_b $11 - end - sync init - end - process $group_1 - assign \imm_b_ok 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:224" - switch \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:225" - attribute \nmigen.decoding "CONST_UI/2" - case 4'0010 - assign \imm_b_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:228" - attribute \nmigen.decoding "CONST_SI/3" - case 4'0011 - assign \imm_b_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:233" - attribute \nmigen.decoding "CONST_SI_HI/5" - case 4'0101 - assign \imm_b_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:238" - attribute \nmigen.decoding "CONST_UI_HI/4" - case 4'0100 - assign \imm_b_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:243" - attribute \nmigen.decoding "CONST_LI/6" - case 4'0110 - assign \imm_b_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:248" - attribute \nmigen.decoding "CONST_BD/7" - case 4'0111 - assign \imm_b_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:253" - attribute \nmigen.decoding "CONST_DS/8" - case 4'1000 - assign \imm_b_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:258" - attribute \nmigen.decoding "CONST_M1/9" - case 4'1001 - assign \imm_b_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" - attribute \nmigen.decoding "CONST_SH/10" - case 4'1010 - assign \imm_b_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:264" - attribute \nmigen.decoding "CONST_SH32/11" - case 4'1011 - assign \imm_b_ok 1'1 - end - sync init - end - process $group_2 - assign \si 16'0000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:224" - switch \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:225" - attribute \nmigen.decoding "CONST_UI/2" - case 4'0010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:228" - attribute \nmigen.decoding "CONST_SI/3" - case 4'0011 - assign \si \MUL_SI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:233" - attribute \nmigen.decoding "CONST_SI_HI/5" - case 4'0101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:238" - attribute \nmigen.decoding "CONST_UI_HI/4" - case 4'0100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:243" - attribute \nmigen.decoding "CONST_LI/6" - case 4'0110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:248" - attribute \nmigen.decoding "CONST_BD/7" - case 4'0111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:253" - attribute \nmigen.decoding "CONST_DS/8" - case 4'1000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:258" - attribute \nmigen.decoding "CONST_M1/9" - case 4'1001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" - attribute \nmigen.decoding "CONST_SH/10" - case 4'1010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:264" - attribute \nmigen.decoding "CONST_SH32/11" - case 4'1011 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:235" - wire width 47 $13 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:235" - wire width 47 $14 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:235" - cell $sshl $15 - parameter \A_SIGNED 0 - parameter \A_WIDTH 16 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 47 - connect \A \MUL_SI - connect \B 5'10000 - connect \Y $14 - end - connect $13 $14 - process $group_3 - assign \si_hi 32'00000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:224" - switch \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:225" - attribute \nmigen.decoding "CONST_UI/2" - case 4'0010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:228" - attribute \nmigen.decoding "CONST_SI/3" - case 4'0011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:233" - attribute \nmigen.decoding "CONST_SI_HI/5" - case 4'0101 - assign \si_hi $13 [31:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:238" - attribute \nmigen.decoding "CONST_UI_HI/4" - case 4'0100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:243" - attribute \nmigen.decoding "CONST_LI/6" - case 4'0110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:248" - attribute \nmigen.decoding "CONST_BD/7" - case 4'0111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:253" - attribute \nmigen.decoding "CONST_DS/8" - case 4'1000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:258" - attribute \nmigen.decoding "CONST_M1/9" - case 4'1001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" - attribute \nmigen.decoding "CONST_SH/10" - case 4'1010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:264" - attribute \nmigen.decoding "CONST_SH32/11" - case 4'1011 - end - sync init - end - process $group_4 - assign \ui 16'0000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:224" - switch \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:225" - attribute \nmigen.decoding "CONST_UI/2" - case 4'0010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:228" - 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\dec_MUL_OE - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 14 \dec_MUL_BD - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 5 \dec_MUL_BB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 5 \dec_MUL_BA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 5 \dec_MUL_BT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 8 \dec_MUL_FXM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 5 \dec_MUL_BI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 14 \dec_MUL_DS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 5 \dec_MUL_BC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 3 \dec_X_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 3 \dec_X_BFA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \dec_XL_BT - cell \dec$177 \dec - connect \raw_opcode_in \raw_opcode_in - connect \bigendian \bigendian - connect \opcode_in \dec_opcode_in - connect \MUL_rc_sel \dec_MUL_rc_sel - connect \MUL_cr_in \dec_MUL_cr_in - connect \MUL_cr_out \dec_MUL_cr_out - connect \MUL_internal_op \dec_MUL_internal_op - connect \MUL_function_unit \dec_MUL_function_unit - connect \MUL_in2_sel \dec_MUL_in2_sel - connect \MUL_is_32b \dec_MUL_is_32b - connect \MUL_sgn \dec_MUL_sgn - connect \MUL_SI \dec_MUL_SI - connect \MUL_UI \dec_MUL_UI - connect \MUL_SH32 \dec_MUL_SH32 - connect \MUL_sh \dec_MUL_sh - connect \MUL_LI \dec_MUL_LI - connect \MUL_Rc \dec_MUL_Rc - connect \MUL_OE \dec_MUL_OE - connect \MUL_BD \dec_MUL_BD - connect \MUL_BB \dec_MUL_BB - connect \MUL_BA \dec_MUL_BA - connect \MUL_BT \dec_MUL_BT - connect \MUL_FXM \dec_MUL_FXM - connect \MUL_BI \dec_MUL_BI - connect \MUL_DS \dec_MUL_DS - connect \MUL_BC \dec_MUL_BC - connect \X_BF \dec_X_BF - connect \X_BFA \dec_X_BFA - connect \XL_BT \dec_XL_BT - end - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:404" - wire width 2 \dec_rc_sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \dec_rc_rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \dec_rc_rc_ok - cell \dec_rc$178 \dec_rc - connect \sel_in \dec_rc_sel_in - connect \rc \dec_rc_rc - connect \rc_ok \dec_rc_rc_ok - connect \MUL_Rc \dec_MUL_Rc - end - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:441" - wire width 2 \dec_oe_sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \dec_oe_oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \dec_oe_oe_ok - cell \dec_oe$179 \dec_oe - connect \sel_in \dec_oe_sel_in - connect \MUL_internal_op \dec_MUL_internal_op - connect \oe \dec_oe_oe - connect \oe_ok \dec_oe_oe_ok - connect \MUL_OE \dec_MUL_OE - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:485" - wire width 32 \dec_cr_in_insn_in - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:484" - wire width 3 \dec_cr_in_sel_in - cell \dec_cr_in$180 \dec_cr_in - connect \insn_in \dec_cr_in_insn_in - connect \sel_in \dec_cr_in_sel_in - connect \MUL_internal_op \dec_MUL_internal_op - connect \MUL_BB \dec_MUL_BB - connect \MUL_BA \dec_MUL_BA - connect \MUL_BT \dec_MUL_BT - connect \MUL_FXM \dec_MUL_FXM - connect \MUL_BI \dec_MUL_BI - connect \MUL_BC \dec_MUL_BC - connect \X_BFA \dec_X_BFA - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:550" - wire width 32 \dec_cr_out_insn_in - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:549" - wire width 3 \dec_cr_out_sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:548" - wire width 1 \dec_cr_out_rc_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \dec_cr_out_cr_bitfield_ok - cell \dec_cr_out$182 \dec_cr_out - connect \insn_in \dec_cr_out_insn_in - connect \sel_in \dec_cr_out_sel_in - connect \rc_in \dec_cr_out_rc_in - connect \MUL_internal_op \dec_MUL_internal_op - connect \cr_bitfield_ok \dec_cr_out_cr_bitfield_ok - connect \MUL_FXM \dec_MUL_FXM - connect \X_BF \dec_X_BF - connect \XL_BT \dec_XL_BT - end - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:216" - wire width 4 \dec_bi_sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 \dec_bi_imm_b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \dec_bi_imm_b_ok - cell \dec_bi$184 \dec_bi - connect \sel_in \dec_bi_sel_in - connect \imm_b \dec_bi_imm_b - connect \imm_b_ok \dec_bi_imm_b_ok - connect \MUL_SI \dec_MUL_SI - connect \MUL_UI \dec_MUL_UI - connect \MUL_SH32 \dec_MUL_SH32 - connect \MUL_sh \dec_MUL_sh - connect \MUL_LI \dec_MUL_LI - connect \MUL_BD \dec_MUL_BD - connect \MUL_DS \dec_MUL_DS - end - process $group_0 - assign \MUL_MUL__insn 32'00000000000000000000000000000000 - assign \MUL_MUL__insn \dec_opcode_in - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:405" - wire width 32 \insn_in - process $group_1 - assign \insn_in 32'00000000000000000000000000000000 - assign \insn_in \dec_opcode_in - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:442" - wire width 32 \insn_in$1 - process $group_2 - assign \insn_in$1 32'00000000000000000000000000000000 - assign \insn_in$1 \dec_opcode_in - sync init - end - process $group_3 - assign \dec_cr_in_insn_in 32'00000000000000000000000000000000 - assign \dec_cr_in_insn_in \dec_opcode_in - sync init - end - process $group_4 - assign \dec_cr_out_insn_in 32'00000000000000000000000000000000 - assign \dec_cr_out_insn_in \dec_opcode_in - sync init - end - process $group_5 - assign \dec_rc_sel_in 2'00 - assign \dec_rc_sel_in \dec_MUL_rc_sel - sync init - end - process $group_6 - assign \dec_oe_sel_in 2'00 - assign \dec_oe_sel_in \dec_MUL_rc_sel - sync init - end - process $group_7 - assign \dec_cr_in_sel_in 3'000 - assign \dec_cr_in_sel_in \dec_MUL_cr_in - sync init - end - process $group_8 - assign \dec_cr_out_sel_in 3'000 - assign \dec_cr_out_sel_in \dec_MUL_cr_out - sync init - end - process $group_9 - assign \dec_cr_out_rc_in 1'0 - assign \dec_cr_out_rc_in \dec_rc_rc - sync init - end - process $group_10 - assign \MUL_MUL__insn_type 7'0000000 - assign \MUL_MUL__insn_type \dec_MUL_internal_op - sync init - end - process $group_11 - assign \MUL_MUL__fn_unit 11'00000000000 - assign \MUL_MUL__fn_unit \dec_MUL_function_unit - sync init - end - process $group_12 - assign \dec_bi_sel_in 4'0000 - assign \dec_bi_sel_in \dec_MUL_in2_sel - sync init - end - process $group_13 - assign \MUL_MUL__imm_data__data 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \MUL_MUL__imm_data__ok 1'0 - assign { \MUL_MUL__imm_data__ok \MUL_MUL__imm_data__data } { \dec_bi_imm_b_ok \dec_bi_imm_b } - sync init - end - process $group_15 - assign \MUL_MUL__rc__rc 1'0 - assign \MUL_MUL__rc__ok 1'0 - assign { \MUL_MUL__rc__ok \MUL_MUL__rc__rc } { \dec_rc_rc_ok \dec_rc_rc } - sync init - end - process $group_17 - assign \MUL_MUL__oe__oe 1'0 - assign \MUL_MUL__oe__ok 1'0 - assign { \MUL_MUL__oe__ok \MUL_MUL__oe__oe } { \dec_oe_oe_ok \dec_oe_oe } - sync init - end - process $group_19 - assign \MUL_MUL__write_cr0 1'0 - assign \MUL_MUL__write_cr0 \dec_cr_out_cr_bitfield_ok - sync init - end - process $group_20 - assign \MUL_MUL__is_32bit 1'0 - assign \MUL_MUL__is_32bit \dec_MUL_is_32b - sync init - end - process $group_21 - assign \MUL_MUL__is_signed 1'0 - assign \MUL_MUL__is_signed \dec_MUL_sgn - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.dec_SHIFT_ROT.dec.SHIFT_ROT_dec19" -module \SHIFT_ROT_dec19 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" - wire width 32 input 0 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:308" - wire width 10 \opcode_switch - process $group_0 - assign \opcode_switch 10'0000000000 - assign \opcode_switch \opcode_in [10:1] - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:308" - wire width 5 \opcode_switch$1 - process $group_1 - assign \opcode_switch$1 5'00000 - assign \opcode_switch$1 \opcode_in [5:1] - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.dec_SHIFT_ROT.dec.SHIFT_ROT_dec30" -module \SHIFT_ROT_dec30 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" - wire width 32 input 0 \opcode_in - attribute \enum_base_type "Function" - attribute \enum_value_00000000000 "NONE" - attribute \enum_value_00000000010 "ALU" - attribute \enum_value_00000000100 "LDST" - attribute \enum_value_00000001000 "SHIFT_ROT" - attribute \enum_value_00000010000 "LOGICAL" - attribute \enum_value_00000100000 "BRANCH" - attribute \enum_value_00001000000 "CR" - attribute \enum_value_00010000000 "TRAP" - attribute \enum_value_00100000000 "MUL" - attribute \enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 11 output 1 \SHIFT_ROT_function_unit - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 7 output 2 \SHIFT_ROT_internal_op - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 4 output 3 \SHIFT_ROT_in2_sel - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 output 4 \SHIFT_ROT_cr_in - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 output 5 \SHIFT_ROT_cr_out - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 2 output 6 \SHIFT_ROT_rc_sel - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 2 output 7 \SHIFT_ROT_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 output 8 \SHIFT_ROT_cry_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 output 9 \SHIFT_ROT_is_32b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 output 10 \SHIFT_ROT_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:308" - wire width 4 \opcode_switch - process $group_0 - assign \opcode_switch 4'0000 - assign \opcode_switch \opcode_in [4:1] - sync init - end - process $group_1 - assign \SHIFT_ROT_function_unit 11'00000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 4'0100 - assign \SHIFT_ROT_function_unit 11'00000001000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 4'0101 - assign \SHIFT_ROT_function_unit 11'00000001000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 4'0000 - assign \SHIFT_ROT_function_unit 11'00000001000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 4'0001 - assign \SHIFT_ROT_function_unit 11'00000001000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 4'0010 - assign \SHIFT_ROT_function_unit 11'00000001000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 4'0011 - assign \SHIFT_ROT_function_unit 11'00000001000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 4'0110 - assign \SHIFT_ROT_function_unit 11'00000001000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 4'0111 - assign \SHIFT_ROT_function_unit 11'00000001000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 4'1000 - assign \SHIFT_ROT_function_unit 11'00000001000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 4'1001 - assign \SHIFT_ROT_function_unit 11'00000001000 - end - sync init - end - process $group_2 - assign \SHIFT_ROT_internal_op 7'0000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 4'0100 - assign \SHIFT_ROT_internal_op 7'0111000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 4'0101 - assign \SHIFT_ROT_internal_op 7'0111000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 4'0000 - assign \SHIFT_ROT_internal_op 7'0111001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 4'0001 - assign \SHIFT_ROT_internal_op 7'0111001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 4'0010 - assign \SHIFT_ROT_internal_op 7'0111010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 4'0011 - assign \SHIFT_ROT_internal_op 7'0111010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 4'0110 - assign \SHIFT_ROT_internal_op 7'0111000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 4'0111 - assign \SHIFT_ROT_internal_op 7'0111000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 4'1000 - assign \SHIFT_ROT_internal_op 7'0111001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 4'1001 - assign \SHIFT_ROT_internal_op 7'0111010 - end - sync init - end - process $group_3 - assign \SHIFT_ROT_in2_sel 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 4'0100 - assign \SHIFT_ROT_in2_sel 4'1010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 4'0101 - assign \SHIFT_ROT_in2_sel 4'1010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 4'0000 - assign \SHIFT_ROT_in2_sel 4'1010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 4'0001 - assign \SHIFT_ROT_in2_sel 4'1010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 4'0010 - assign \SHIFT_ROT_in2_sel 4'1010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 4'0011 - assign \SHIFT_ROT_in2_sel 4'1010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 4'0110 - assign \SHIFT_ROT_in2_sel 4'1010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 4'0111 - assign \SHIFT_ROT_in2_sel 4'1010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 4'1000 - assign \SHIFT_ROT_in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 4'1001 - assign \SHIFT_ROT_in2_sel 4'0001 - end - sync init - end - process $group_4 - assign \SHIFT_ROT_cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 4'0100 - assign \SHIFT_ROT_cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 4'0101 - assign \SHIFT_ROT_cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 4'0000 - assign \SHIFT_ROT_cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 4'0001 - assign \SHIFT_ROT_cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 4'0010 - assign \SHIFT_ROT_cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 4'0011 - assign \SHIFT_ROT_cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 4'0110 - assign \SHIFT_ROT_cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 4'0111 - assign \SHIFT_ROT_cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 4'1000 - assign \SHIFT_ROT_cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 4'1001 - assign \SHIFT_ROT_cr_in 3'000 - end - sync init - end - process $group_5 - assign \SHIFT_ROT_cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 4'0100 - assign \SHIFT_ROT_cr_out 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 4'0101 - assign \SHIFT_ROT_cr_out 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 4'0000 - assign \SHIFT_ROT_cr_out 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 4'0001 - assign \SHIFT_ROT_cr_out 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 4'0010 - assign \SHIFT_ROT_cr_out 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 4'0011 - assign \SHIFT_ROT_cr_out 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 4'0110 - assign \SHIFT_ROT_cr_out 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 4'0111 - assign \SHIFT_ROT_cr_out 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 4'1000 - assign \SHIFT_ROT_cr_out 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 4'1001 - assign \SHIFT_ROT_cr_out 3'001 - end - sync init - end - process $group_6 - assign \SHIFT_ROT_rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 4'0100 - assign \SHIFT_ROT_rc_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 4'0101 - assign \SHIFT_ROT_rc_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 4'0000 - assign \SHIFT_ROT_rc_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 4'0001 - assign \SHIFT_ROT_rc_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 4'0010 - assign \SHIFT_ROT_rc_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 4'0011 - assign \SHIFT_ROT_rc_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 4'0110 - assign \SHIFT_ROT_rc_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 4'0111 - assign \SHIFT_ROT_rc_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 4'1000 - assign \SHIFT_ROT_rc_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 4'1001 - assign \SHIFT_ROT_rc_sel 2'10 - end - sync init - end - process $group_7 - assign \SHIFT_ROT_cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 4'0100 - assign \SHIFT_ROT_cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 4'0101 - assign \SHIFT_ROT_cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 4'0000 - assign \SHIFT_ROT_cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 4'0001 - assign \SHIFT_ROT_cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 4'0010 - assign \SHIFT_ROT_cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 4'0011 - assign \SHIFT_ROT_cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 4'0110 - assign \SHIFT_ROT_cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 4'0111 - assign \SHIFT_ROT_cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 4'1000 - assign \SHIFT_ROT_cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 4'1001 - assign \SHIFT_ROT_cry_in 2'00 - end - sync init - end - process $group_8 - assign \SHIFT_ROT_cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 4'0100 - assign \SHIFT_ROT_cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 4'0101 - assign \SHIFT_ROT_cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 4'0000 - assign \SHIFT_ROT_cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 4'0001 - assign \SHIFT_ROT_cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 4'0010 - assign \SHIFT_ROT_cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 4'0011 - assign \SHIFT_ROT_cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 4'0110 - assign \SHIFT_ROT_cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 4'0111 - assign \SHIFT_ROT_cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 4'1000 - assign \SHIFT_ROT_cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 4'1001 - assign \SHIFT_ROT_cry_out 1'0 - end - sync init - end - process $group_9 - assign \SHIFT_ROT_is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 4'0100 - assign \SHIFT_ROT_is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 4'0101 - assign \SHIFT_ROT_is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 4'0000 - assign \SHIFT_ROT_is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 4'0001 - assign \SHIFT_ROT_is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 4'0010 - assign \SHIFT_ROT_is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 4'0011 - assign \SHIFT_ROT_is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 4'0110 - assign \SHIFT_ROT_is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 4'0111 - assign \SHIFT_ROT_is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 4'1000 - assign \SHIFT_ROT_is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 4'1001 - assign \SHIFT_ROT_is_32b 1'0 - end - sync init - end - process $group_10 - assign \SHIFT_ROT_sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 4'0100 - assign \SHIFT_ROT_sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 4'0101 - assign \SHIFT_ROT_sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 4'0000 - assign \SHIFT_ROT_sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 4'0001 - assign \SHIFT_ROT_sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 4'0010 - assign \SHIFT_ROT_sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 4'0011 - assign \SHIFT_ROT_sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 4'0110 - assign \SHIFT_ROT_sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 4'0111 - assign \SHIFT_ROT_sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 4'1000 - assign \SHIFT_ROT_sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 4'1001 - assign \SHIFT_ROT_sgn 1'0 - end - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.dec_SHIFT_ROT.dec.SHIFT_ROT_dec31.SHIFT_ROT_dec_sub10" -module \SHIFT_ROT_dec_sub10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" - wire width 32 input 0 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:308" - wire width 5 \opcode_switch - process $group_0 - assign \opcode_switch 5'00000 - assign \opcode_switch \opcode_in [10:6] - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.dec_SHIFT_ROT.dec.SHIFT_ROT_dec31.SHIFT_ROT_dec_sub28" -module \SHIFT_ROT_dec_sub28 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" - wire width 32 input 0 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:308" - wire width 5 \opcode_switch - process $group_0 - assign \opcode_switch 5'00000 - assign \opcode_switch \opcode_in [10:6] - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.dec_SHIFT_ROT.dec.SHIFT_ROT_dec31.SHIFT_ROT_dec_sub0" -module \SHIFT_ROT_dec_sub0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" - wire width 32 input 0 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:308" - wire width 5 \opcode_switch - process $group_0 - assign \opcode_switch 5'00000 - assign \opcode_switch \opcode_in [10:6] - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.dec_SHIFT_ROT.dec.SHIFT_ROT_dec31.SHIFT_ROT_dec_sub26" -module \SHIFT_ROT_dec_sub26 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" - wire width 32 input 0 \opcode_in - attribute \enum_base_type "Function" - attribute \enum_value_00000000000 "NONE" - attribute \enum_value_00000000010 "ALU" - attribute \enum_value_00000000100 "LDST" - attribute \enum_value_00000001000 "SHIFT_ROT" - attribute \enum_value_00000010000 "LOGICAL" - attribute \enum_value_00000100000 "BRANCH" - attribute \enum_value_00001000000 "CR" - attribute \enum_value_00010000000 "TRAP" - attribute \enum_value_00100000000 "MUL" - attribute \enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 11 output 1 \SHIFT_ROT_function_unit - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 7 output 2 \SHIFT_ROT_internal_op - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 4 output 3 \SHIFT_ROT_in2_sel - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 output 4 \SHIFT_ROT_cr_in - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 output 5 \SHIFT_ROT_cr_out - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 2 output 6 \SHIFT_ROT_rc_sel - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 2 output 7 \SHIFT_ROT_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 output 8 \SHIFT_ROT_cry_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 output 9 \SHIFT_ROT_is_32b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 output 10 \SHIFT_ROT_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:308" - wire width 5 \opcode_switch - process $group_0 - assign \opcode_switch 5'00000 - assign \opcode_switch \opcode_in [10:6] - sync init - end - process $group_1 - assign \SHIFT_ROT_function_unit 11'00000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11011 - assign \SHIFT_ROT_function_unit 11'00000001000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11000 - assign \SHIFT_ROT_function_unit 11'00000001000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11001 - assign \SHIFT_ROT_function_unit 11'00000001000 - end - sync init - end - process $group_2 - assign \SHIFT_ROT_internal_op 7'0000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11011 - assign \SHIFT_ROT_internal_op 7'0100000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11000 - assign \SHIFT_ROT_internal_op 7'0111101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11001 - assign \SHIFT_ROT_internal_op 7'0111101 - end - sync init - end - process $group_3 - assign \SHIFT_ROT_in2_sel 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11011 - assign \SHIFT_ROT_in2_sel 4'1010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11000 - assign \SHIFT_ROT_in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11001 - assign \SHIFT_ROT_in2_sel 4'1010 - end - sync init - end - process $group_4 - assign \SHIFT_ROT_cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11011 - assign \SHIFT_ROT_cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11000 - assign \SHIFT_ROT_cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11001 - assign \SHIFT_ROT_cr_in 3'000 - end - sync init - end - process $group_5 - assign \SHIFT_ROT_cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11011 - assign \SHIFT_ROT_cr_out 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11000 - assign \SHIFT_ROT_cr_out 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11001 - assign \SHIFT_ROT_cr_out 3'001 - end - sync init - end - process $group_6 - assign \SHIFT_ROT_rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11011 - assign \SHIFT_ROT_rc_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11000 - assign \SHIFT_ROT_rc_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11001 - assign \SHIFT_ROT_rc_sel 2'10 - end - sync init - end - process $group_7 - assign \SHIFT_ROT_cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11011 - assign \SHIFT_ROT_cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11000 - assign \SHIFT_ROT_cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11001 - assign \SHIFT_ROT_cry_in 2'00 - end - sync init - end - process $group_8 - assign \SHIFT_ROT_cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11011 - assign \SHIFT_ROT_cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11000 - assign \SHIFT_ROT_cry_out 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11001 - assign \SHIFT_ROT_cry_out 1'1 - end - sync init - end - process $group_9 - assign \SHIFT_ROT_is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11011 - assign \SHIFT_ROT_is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11000 - assign \SHIFT_ROT_is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11001 - assign \SHIFT_ROT_is_32b 1'0 - end - sync init - end - process $group_10 - assign \SHIFT_ROT_sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11011 - assign \SHIFT_ROT_sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11000 - assign \SHIFT_ROT_sgn 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11001 - assign \SHIFT_ROT_sgn 1'1 - end - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.dec_SHIFT_ROT.dec.SHIFT_ROT_dec31.SHIFT_ROT_dec_sub19" -module \SHIFT_ROT_dec_sub19 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" - wire width 32 input 0 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:308" - wire width 5 \opcode_switch - process $group_0 - assign \opcode_switch 5'00000 - assign \opcode_switch \opcode_in [10:6] - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.dec_SHIFT_ROT.dec.SHIFT_ROT_dec31.SHIFT_ROT_dec_sub22" -module \SHIFT_ROT_dec_sub22 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" - wire width 32 input 0 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:308" - wire width 5 \opcode_switch - process $group_0 - assign \opcode_switch 5'00000 - assign \opcode_switch \opcode_in [10:6] - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.dec_SHIFT_ROT.dec.SHIFT_ROT_dec31.SHIFT_ROT_dec_sub9" -module \SHIFT_ROT_dec_sub9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" - wire width 32 input 0 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:308" - wire width 5 \opcode_switch - process $group_0 - assign \opcode_switch 5'00000 - assign \opcode_switch \opcode_in [10:6] - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.dec_SHIFT_ROT.dec.SHIFT_ROT_dec31.SHIFT_ROT_dec_sub11" -module \SHIFT_ROT_dec_sub11 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" - wire width 32 input 0 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:308" - wire width 5 \opcode_switch - process $group_0 - assign \opcode_switch 5'00000 - assign \opcode_switch \opcode_in [10:6] - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.dec_SHIFT_ROT.dec.SHIFT_ROT_dec31.SHIFT_ROT_dec_sub27" -module \SHIFT_ROT_dec_sub27 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" - wire width 32 input 0 \opcode_in - attribute \enum_base_type "Function" - attribute \enum_value_00000000000 "NONE" - attribute \enum_value_00000000010 "ALU" - attribute \enum_value_00000000100 "LDST" - attribute \enum_value_00000001000 "SHIFT_ROT" - attribute \enum_value_00000010000 "LOGICAL" - attribute \enum_value_00000100000 "BRANCH" - attribute \enum_value_00001000000 "CR" - attribute \enum_value_00010000000 "TRAP" - attribute \enum_value_00100000000 "MUL" - attribute \enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 11 output 1 \SHIFT_ROT_function_unit - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 7 output 2 \SHIFT_ROT_internal_op - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 4 output 3 \SHIFT_ROT_in2_sel - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 output 4 \SHIFT_ROT_cr_in - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 output 5 \SHIFT_ROT_cr_out - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 2 output 6 \SHIFT_ROT_rc_sel - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 2 output 7 \SHIFT_ROT_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 output 8 \SHIFT_ROT_cry_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 output 9 \SHIFT_ROT_is_32b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 output 10 \SHIFT_ROT_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:308" - wire width 5 \opcode_switch - process $group_0 - assign \opcode_switch 5'00000 - assign \opcode_switch \opcode_in [10:6] - sync init - end - process $group_1 - assign \SHIFT_ROT_function_unit 11'00000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11011 - assign \SHIFT_ROT_function_unit 11'00000001000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \SHIFT_ROT_function_unit 11'00000001000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11001 - assign \SHIFT_ROT_function_unit 11'00000001000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10000 - assign \SHIFT_ROT_function_unit 11'00000001000 - end - sync init - end - process $group_2 - assign \SHIFT_ROT_internal_op 7'0000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11011 - assign \SHIFT_ROT_internal_op 7'0100000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \SHIFT_ROT_internal_op 7'0111100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11001 - assign \SHIFT_ROT_internal_op 7'0111101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10000 - assign \SHIFT_ROT_internal_op 7'0111101 - end - sync init - end - process $group_3 - assign \SHIFT_ROT_in2_sel 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11011 - assign \SHIFT_ROT_in2_sel 4'1010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \SHIFT_ROT_in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11001 - assign \SHIFT_ROT_in2_sel 4'1010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10000 - assign \SHIFT_ROT_in2_sel 4'0001 - end - sync init - end - process $group_4 - assign \SHIFT_ROT_cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11011 - assign \SHIFT_ROT_cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \SHIFT_ROT_cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11001 - assign \SHIFT_ROT_cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10000 - assign \SHIFT_ROT_cr_in 3'000 - end - sync init - end - process $group_5 - assign \SHIFT_ROT_cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11011 - assign \SHIFT_ROT_cr_out 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \SHIFT_ROT_cr_out 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11001 - assign \SHIFT_ROT_cr_out 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10000 - assign \SHIFT_ROT_cr_out 3'001 - end - sync init - end - process $group_6 - assign \SHIFT_ROT_rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11011 - assign \SHIFT_ROT_rc_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \SHIFT_ROT_rc_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11001 - assign \SHIFT_ROT_rc_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10000 - assign \SHIFT_ROT_rc_sel 2'10 - end - sync init - end - process $group_7 - assign \SHIFT_ROT_cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11011 - assign \SHIFT_ROT_cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \SHIFT_ROT_cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11001 - assign \SHIFT_ROT_cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10000 - assign \SHIFT_ROT_cry_in 2'00 - end - sync init - end - process $group_8 - assign \SHIFT_ROT_cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11011 - assign \SHIFT_ROT_cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \SHIFT_ROT_cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11001 - assign \SHIFT_ROT_cry_out 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10000 - assign \SHIFT_ROT_cry_out 1'0 - end - sync init - end - process $group_9 - assign \SHIFT_ROT_is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11011 - assign \SHIFT_ROT_is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \SHIFT_ROT_is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11001 - assign \SHIFT_ROT_is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10000 - assign \SHIFT_ROT_is_32b 1'0 - end - sync init - end - process $group_10 - assign \SHIFT_ROT_sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11011 - assign \SHIFT_ROT_sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \SHIFT_ROT_sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11001 - assign \SHIFT_ROT_sgn 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10000 - assign \SHIFT_ROT_sgn 1'0 - end - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.dec_SHIFT_ROT.dec.SHIFT_ROT_dec31.SHIFT_ROT_dec_sub15" -module \SHIFT_ROT_dec_sub15 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" - wire width 32 input 0 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:308" - wire width 5 \opcode_switch - process $group_0 - assign \opcode_switch 5'00000 - assign \opcode_switch \opcode_in [10:6] - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.dec_SHIFT_ROT.dec.SHIFT_ROT_dec31.SHIFT_ROT_dec_sub20" -module \SHIFT_ROT_dec_sub20 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" - wire width 32 input 0 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:308" - wire width 5 \opcode_switch - process $group_0 - assign \opcode_switch 5'00000 - assign \opcode_switch \opcode_in [10:6] - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.dec_SHIFT_ROT.dec.SHIFT_ROT_dec31.SHIFT_ROT_dec_sub21" -module \SHIFT_ROT_dec_sub21 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" - wire width 32 input 0 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:308" - wire width 5 \opcode_switch - process $group_0 - assign \opcode_switch 5'00000 - assign \opcode_switch \opcode_in [10:6] - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.dec_SHIFT_ROT.dec.SHIFT_ROT_dec31.SHIFT_ROT_dec_sub23" -module \SHIFT_ROT_dec_sub23 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" - wire width 32 input 0 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:308" - wire width 5 \opcode_switch - process $group_0 - assign \opcode_switch 5'00000 - assign \opcode_switch \opcode_in [10:6] - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.dec_SHIFT_ROT.dec.SHIFT_ROT_dec31.SHIFT_ROT_dec_sub16" -module \SHIFT_ROT_dec_sub16 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" - wire width 32 input 0 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:308" - wire width 5 \opcode_switch - process $group_0 - assign \opcode_switch 5'00000 - assign \opcode_switch \opcode_in [10:6] - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.dec_SHIFT_ROT.dec.SHIFT_ROT_dec31.SHIFT_ROT_dec_sub18" -module \SHIFT_ROT_dec_sub18 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" - wire width 32 input 0 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:308" - wire width 5 \opcode_switch - process $group_0 - assign \opcode_switch 5'00000 - assign \opcode_switch \opcode_in [10:6] - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.dec_SHIFT_ROT.dec.SHIFT_ROT_dec31.SHIFT_ROT_dec_sub8" -module \SHIFT_ROT_dec_sub8 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" - wire width 32 input 0 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:308" - wire width 5 \opcode_switch - process $group_0 - assign \opcode_switch 5'00000 - assign \opcode_switch \opcode_in [10:6] - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.dec_SHIFT_ROT.dec.SHIFT_ROT_dec31.SHIFT_ROT_dec_sub24" -module \SHIFT_ROT_dec_sub24 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" - wire width 32 input 0 \opcode_in - attribute \enum_base_type "Function" - attribute \enum_value_00000000000 "NONE" - attribute \enum_value_00000000010 "ALU" - attribute \enum_value_00000000100 "LDST" - attribute \enum_value_00000001000 "SHIFT_ROT" - attribute \enum_value_00000010000 "LOGICAL" - attribute \enum_value_00000100000 "BRANCH" - attribute \enum_value_00001000000 "CR" - attribute \enum_value_00010000000 "TRAP" - attribute \enum_value_00100000000 "MUL" - attribute \enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 11 output 1 \SHIFT_ROT_function_unit - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 7 output 2 \SHIFT_ROT_internal_op - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 4 output 3 \SHIFT_ROT_in2_sel - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 output 4 \SHIFT_ROT_cr_in - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 output 5 \SHIFT_ROT_cr_out - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 2 output 6 \SHIFT_ROT_rc_sel - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 2 output 7 \SHIFT_ROT_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 output 8 \SHIFT_ROT_cry_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 output 9 \SHIFT_ROT_is_32b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 output 10 \SHIFT_ROT_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:308" - wire width 5 \opcode_switch - process $group_0 - assign \opcode_switch 5'00000 - assign \opcode_switch \opcode_in [10:6] - sync init - end - process $group_1 - assign \SHIFT_ROT_function_unit 11'00000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \SHIFT_ROT_function_unit 11'00000001000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11000 - assign \SHIFT_ROT_function_unit 11'00000001000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11001 - assign \SHIFT_ROT_function_unit 11'00000001000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10000 - assign \SHIFT_ROT_function_unit 11'00000001000 - end - sync init - end - process $group_2 - assign \SHIFT_ROT_internal_op 7'0000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \SHIFT_ROT_internal_op 7'0111100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11000 - assign \SHIFT_ROT_internal_op 7'0111101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11001 - assign \SHIFT_ROT_internal_op 7'0111101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10000 - assign \SHIFT_ROT_internal_op 7'0111101 - end - sync init - end - process $group_3 - assign \SHIFT_ROT_in2_sel 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \SHIFT_ROT_in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11000 - assign \SHIFT_ROT_in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11001 - assign \SHIFT_ROT_in2_sel 4'1011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10000 - assign \SHIFT_ROT_in2_sel 4'0001 - end - sync init - end - process $group_4 - assign \SHIFT_ROT_cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \SHIFT_ROT_cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11000 - assign \SHIFT_ROT_cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11001 - assign \SHIFT_ROT_cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10000 - assign \SHIFT_ROT_cr_in 3'000 - end - sync init - end - process $group_5 - assign \SHIFT_ROT_cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \SHIFT_ROT_cr_out 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11000 - assign \SHIFT_ROT_cr_out 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11001 - assign \SHIFT_ROT_cr_out 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10000 - assign \SHIFT_ROT_cr_out 3'001 - end - sync init - end - process $group_6 - assign \SHIFT_ROT_rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \SHIFT_ROT_rc_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11000 - assign \SHIFT_ROT_rc_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11001 - assign \SHIFT_ROT_rc_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10000 - assign \SHIFT_ROT_rc_sel 2'10 - end - sync init - end - process $group_7 - assign \SHIFT_ROT_cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \SHIFT_ROT_cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11000 - assign \SHIFT_ROT_cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11001 - assign \SHIFT_ROT_cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10000 - assign \SHIFT_ROT_cry_in 2'00 - end - sync init - end - process $group_8 - assign \SHIFT_ROT_cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \SHIFT_ROT_cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11000 - assign \SHIFT_ROT_cry_out 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11001 - assign \SHIFT_ROT_cry_out 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10000 - assign \SHIFT_ROT_cry_out 1'0 - end - sync init - end - process $group_9 - assign \SHIFT_ROT_is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \SHIFT_ROT_is_32b 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11000 - assign \SHIFT_ROT_is_32b 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11001 - assign \SHIFT_ROT_is_32b 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10000 - assign \SHIFT_ROT_is_32b 1'1 - end - sync init - end - process $group_10 - assign \SHIFT_ROT_sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \SHIFT_ROT_sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11000 - assign \SHIFT_ROT_sgn 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11001 - assign \SHIFT_ROT_sgn 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10000 - assign \SHIFT_ROT_sgn 1'0 - end - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.dec_SHIFT_ROT.dec.SHIFT_ROT_dec31.SHIFT_ROT_dec_sub4" -module \SHIFT_ROT_dec_sub4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" - wire width 32 input 0 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:308" - wire width 5 \opcode_switch - process $group_0 - assign \opcode_switch 5'00000 - assign \opcode_switch \opcode_in [10:6] - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.dec_SHIFT_ROT.dec.SHIFT_ROT_dec31" -module \SHIFT_ROT_dec31 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" - wire width 32 input 0 \opcode_in - attribute \enum_base_type "Function" - attribute \enum_value_00000000000 "NONE" - attribute \enum_value_00000000010 "ALU" - attribute \enum_value_00000000100 "LDST" - attribute \enum_value_00000001000 "SHIFT_ROT" - attribute \enum_value_00000010000 "LOGICAL" - attribute \enum_value_00000100000 "BRANCH" - attribute \enum_value_00001000000 "CR" - attribute \enum_value_00010000000 "TRAP" - attribute \enum_value_00100000000 "MUL" - attribute \enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 11 output 1 \SHIFT_ROT_function_unit - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 7 output 2 \SHIFT_ROT_internal_op - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 4 output 3 \SHIFT_ROT_in2_sel - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 output 4 \SHIFT_ROT_cr_in - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 output 5 \SHIFT_ROT_cr_out - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 2 output 6 \SHIFT_ROT_rc_sel - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 2 output 7 \SHIFT_ROT_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 output 8 \SHIFT_ROT_cry_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 output 9 \SHIFT_ROT_is_32b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 output 10 \SHIFT_ROT_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" - wire width 32 \SHIFT_ROT_dec_sub10_opcode_in - cell \SHIFT_ROT_dec_sub10 \SHIFT_ROT_dec_sub10 - connect \opcode_in \SHIFT_ROT_dec_sub10_opcode_in - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" - wire width 32 \SHIFT_ROT_dec_sub28_opcode_in - cell \SHIFT_ROT_dec_sub28 \SHIFT_ROT_dec_sub28 - connect \opcode_in \SHIFT_ROT_dec_sub28_opcode_in - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" - wire width 32 \SHIFT_ROT_dec_sub0_opcode_in - cell \SHIFT_ROT_dec_sub0 \SHIFT_ROT_dec_sub0 - connect \opcode_in \SHIFT_ROT_dec_sub0_opcode_in - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" - wire width 32 \SHIFT_ROT_dec_sub26_opcode_in - attribute \enum_base_type "Function" - attribute \enum_value_00000000000 "NONE" - attribute \enum_value_00000000010 "ALU" - attribute \enum_value_00000000100 "LDST" - attribute \enum_value_00000001000 "SHIFT_ROT" - attribute \enum_value_00000010000 "LOGICAL" - attribute \enum_value_00000100000 "BRANCH" - attribute \enum_value_00001000000 "CR" - attribute \enum_value_00010000000 "TRAP" - attribute \enum_value_00100000000 "MUL" - attribute \enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 11 \SHIFT_ROT_dec_sub26_SHIFT_ROT_function_unit - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 7 \SHIFT_ROT_dec_sub26_SHIFT_ROT_internal_op - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 4 \SHIFT_ROT_dec_sub26_SHIFT_ROT_in2_sel - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \SHIFT_ROT_dec_sub26_SHIFT_ROT_cr_in - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \SHIFT_ROT_dec_sub26_SHIFT_ROT_cr_out - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 2 \SHIFT_ROT_dec_sub26_SHIFT_ROT_rc_sel - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 2 \SHIFT_ROT_dec_sub26_SHIFT_ROT_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \SHIFT_ROT_dec_sub26_SHIFT_ROT_cry_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \SHIFT_ROT_dec_sub26_SHIFT_ROT_is_32b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \SHIFT_ROT_dec_sub26_SHIFT_ROT_sgn - cell \SHIFT_ROT_dec_sub26 \SHIFT_ROT_dec_sub26 - connect \opcode_in \SHIFT_ROT_dec_sub26_opcode_in - connect \SHIFT_ROT_function_unit \SHIFT_ROT_dec_sub26_SHIFT_ROT_function_unit - connect \SHIFT_ROT_internal_op \SHIFT_ROT_dec_sub26_SHIFT_ROT_internal_op - connect \SHIFT_ROT_in2_sel \SHIFT_ROT_dec_sub26_SHIFT_ROT_in2_sel - connect \SHIFT_ROT_cr_in \SHIFT_ROT_dec_sub26_SHIFT_ROT_cr_in - connect \SHIFT_ROT_cr_out \SHIFT_ROT_dec_sub26_SHIFT_ROT_cr_out - connect \SHIFT_ROT_rc_sel \SHIFT_ROT_dec_sub26_SHIFT_ROT_rc_sel - connect \SHIFT_ROT_cry_in \SHIFT_ROT_dec_sub26_SHIFT_ROT_cry_in - connect \SHIFT_ROT_cry_out \SHIFT_ROT_dec_sub26_SHIFT_ROT_cry_out - connect \SHIFT_ROT_is_32b \SHIFT_ROT_dec_sub26_SHIFT_ROT_is_32b - connect \SHIFT_ROT_sgn \SHIFT_ROT_dec_sub26_SHIFT_ROT_sgn - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" - wire width 32 \SHIFT_ROT_dec_sub19_opcode_in - cell \SHIFT_ROT_dec_sub19 \SHIFT_ROT_dec_sub19 - connect \opcode_in \SHIFT_ROT_dec_sub19_opcode_in - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" - wire width 32 \SHIFT_ROT_dec_sub22_opcode_in - cell \SHIFT_ROT_dec_sub22 \SHIFT_ROT_dec_sub22 - connect \opcode_in \SHIFT_ROT_dec_sub22_opcode_in - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" - wire width 32 \SHIFT_ROT_dec_sub9_opcode_in - cell \SHIFT_ROT_dec_sub9 \SHIFT_ROT_dec_sub9 - connect \opcode_in \SHIFT_ROT_dec_sub9_opcode_in - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" - wire width 32 \SHIFT_ROT_dec_sub11_opcode_in - cell \SHIFT_ROT_dec_sub11 \SHIFT_ROT_dec_sub11 - connect \opcode_in \SHIFT_ROT_dec_sub11_opcode_in - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" - wire width 32 \SHIFT_ROT_dec_sub27_opcode_in - attribute \enum_base_type "Function" - attribute \enum_value_00000000000 "NONE" - attribute \enum_value_00000000010 "ALU" - attribute \enum_value_00000000100 "LDST" - attribute \enum_value_00000001000 "SHIFT_ROT" - attribute \enum_value_00000010000 "LOGICAL" - attribute \enum_value_00000100000 "BRANCH" - attribute \enum_value_00001000000 "CR" - attribute \enum_value_00010000000 "TRAP" - attribute \enum_value_00100000000 "MUL" - attribute \enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 11 \SHIFT_ROT_dec_sub27_SHIFT_ROT_function_unit - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 7 \SHIFT_ROT_dec_sub27_SHIFT_ROT_internal_op - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 4 \SHIFT_ROT_dec_sub27_SHIFT_ROT_in2_sel - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \SHIFT_ROT_dec_sub27_SHIFT_ROT_cr_in - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \SHIFT_ROT_dec_sub27_SHIFT_ROT_cr_out - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 2 \SHIFT_ROT_dec_sub27_SHIFT_ROT_rc_sel - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 2 \SHIFT_ROT_dec_sub27_SHIFT_ROT_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \SHIFT_ROT_dec_sub27_SHIFT_ROT_cry_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \SHIFT_ROT_dec_sub27_SHIFT_ROT_is_32b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \SHIFT_ROT_dec_sub27_SHIFT_ROT_sgn - cell \SHIFT_ROT_dec_sub27 \SHIFT_ROT_dec_sub27 - connect \opcode_in \SHIFT_ROT_dec_sub27_opcode_in - connect \SHIFT_ROT_function_unit \SHIFT_ROT_dec_sub27_SHIFT_ROT_function_unit - connect \SHIFT_ROT_internal_op \SHIFT_ROT_dec_sub27_SHIFT_ROT_internal_op - connect \SHIFT_ROT_in2_sel \SHIFT_ROT_dec_sub27_SHIFT_ROT_in2_sel - connect \SHIFT_ROT_cr_in \SHIFT_ROT_dec_sub27_SHIFT_ROT_cr_in - connect \SHIFT_ROT_cr_out \SHIFT_ROT_dec_sub27_SHIFT_ROT_cr_out - connect \SHIFT_ROT_rc_sel \SHIFT_ROT_dec_sub27_SHIFT_ROT_rc_sel - connect \SHIFT_ROT_cry_in \SHIFT_ROT_dec_sub27_SHIFT_ROT_cry_in - connect \SHIFT_ROT_cry_out \SHIFT_ROT_dec_sub27_SHIFT_ROT_cry_out - connect \SHIFT_ROT_is_32b \SHIFT_ROT_dec_sub27_SHIFT_ROT_is_32b - connect \SHIFT_ROT_sgn \SHIFT_ROT_dec_sub27_SHIFT_ROT_sgn - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" - wire width 32 \SHIFT_ROT_dec_sub15_opcode_in - cell \SHIFT_ROT_dec_sub15 \SHIFT_ROT_dec_sub15 - connect \opcode_in \SHIFT_ROT_dec_sub15_opcode_in - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" - wire width 32 \SHIFT_ROT_dec_sub20_opcode_in - cell \SHIFT_ROT_dec_sub20 \SHIFT_ROT_dec_sub20 - connect \opcode_in \SHIFT_ROT_dec_sub20_opcode_in - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" - wire width 32 \SHIFT_ROT_dec_sub21_opcode_in - cell \SHIFT_ROT_dec_sub21 \SHIFT_ROT_dec_sub21 - connect \opcode_in \SHIFT_ROT_dec_sub21_opcode_in - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" - wire width 32 \SHIFT_ROT_dec_sub23_opcode_in - cell \SHIFT_ROT_dec_sub23 \SHIFT_ROT_dec_sub23 - connect \opcode_in \SHIFT_ROT_dec_sub23_opcode_in - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" - wire width 32 \SHIFT_ROT_dec_sub16_opcode_in - cell \SHIFT_ROT_dec_sub16 \SHIFT_ROT_dec_sub16 - connect \opcode_in \SHIFT_ROT_dec_sub16_opcode_in - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" - wire width 32 \SHIFT_ROT_dec_sub18_opcode_in - cell \SHIFT_ROT_dec_sub18 \SHIFT_ROT_dec_sub18 - connect \opcode_in \SHIFT_ROT_dec_sub18_opcode_in - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" - wire width 32 \SHIFT_ROT_dec_sub8_opcode_in - cell \SHIFT_ROT_dec_sub8 \SHIFT_ROT_dec_sub8 - connect \opcode_in \SHIFT_ROT_dec_sub8_opcode_in - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" - wire width 32 \SHIFT_ROT_dec_sub24_opcode_in - attribute \enum_base_type "Function" - attribute \enum_value_00000000000 "NONE" - attribute \enum_value_00000000010 "ALU" - attribute \enum_value_00000000100 "LDST" - attribute \enum_value_00000001000 "SHIFT_ROT" - attribute \enum_value_00000010000 "LOGICAL" - attribute \enum_value_00000100000 "BRANCH" - attribute \enum_value_00001000000 "CR" - attribute \enum_value_00010000000 "TRAP" - attribute \enum_value_00100000000 "MUL" - attribute \enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 11 \SHIFT_ROT_dec_sub24_SHIFT_ROT_function_unit - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 7 \SHIFT_ROT_dec_sub24_SHIFT_ROT_internal_op - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 4 \SHIFT_ROT_dec_sub24_SHIFT_ROT_in2_sel - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \SHIFT_ROT_dec_sub24_SHIFT_ROT_cr_in - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \SHIFT_ROT_dec_sub24_SHIFT_ROT_cr_out - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 2 \SHIFT_ROT_dec_sub24_SHIFT_ROT_rc_sel - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 2 \SHIFT_ROT_dec_sub24_SHIFT_ROT_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \SHIFT_ROT_dec_sub24_SHIFT_ROT_cry_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \SHIFT_ROT_dec_sub24_SHIFT_ROT_is_32b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \SHIFT_ROT_dec_sub24_SHIFT_ROT_sgn - cell \SHIFT_ROT_dec_sub24 \SHIFT_ROT_dec_sub24 - connect \opcode_in \SHIFT_ROT_dec_sub24_opcode_in - connect \SHIFT_ROT_function_unit \SHIFT_ROT_dec_sub24_SHIFT_ROT_function_unit - connect \SHIFT_ROT_internal_op \SHIFT_ROT_dec_sub24_SHIFT_ROT_internal_op - connect \SHIFT_ROT_in2_sel \SHIFT_ROT_dec_sub24_SHIFT_ROT_in2_sel - connect \SHIFT_ROT_cr_in \SHIFT_ROT_dec_sub24_SHIFT_ROT_cr_in - connect \SHIFT_ROT_cr_out \SHIFT_ROT_dec_sub24_SHIFT_ROT_cr_out - connect \SHIFT_ROT_rc_sel \SHIFT_ROT_dec_sub24_SHIFT_ROT_rc_sel - connect \SHIFT_ROT_cry_in \SHIFT_ROT_dec_sub24_SHIFT_ROT_cry_in - connect \SHIFT_ROT_cry_out \SHIFT_ROT_dec_sub24_SHIFT_ROT_cry_out - connect \SHIFT_ROT_is_32b \SHIFT_ROT_dec_sub24_SHIFT_ROT_is_32b - connect \SHIFT_ROT_sgn \SHIFT_ROT_dec_sub24_SHIFT_ROT_sgn - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" - wire width 32 \SHIFT_ROT_dec_sub4_opcode_in - cell \SHIFT_ROT_dec_sub4 \SHIFT_ROT_dec_sub4 - connect \opcode_in \SHIFT_ROT_dec_sub4_opcode_in - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:308" - wire width 10 \opcode_switch - process $group_0 - assign \opcode_switch 10'0000000000 - assign \opcode_switch \opcode_in [10:1] - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:312" - wire width 5 \opc_in - process $group_1 - assign \opc_in 5'00000 - assign \opc_in \opcode_switch [4:0] - sync init - end - process $group_2 - assign \SHIFT_ROT_dec_sub10_opcode_in 32'00000000000000000000000000000000 - assign \SHIFT_ROT_dec_sub10_opcode_in \opcode_in - sync init - end - process $group_3 - assign \SHIFT_ROT_dec_sub28_opcode_in 32'00000000000000000000000000000000 - assign \SHIFT_ROT_dec_sub28_opcode_in \opcode_in - sync init - end - process $group_4 - assign \SHIFT_ROT_dec_sub0_opcode_in 32'00000000000000000000000000000000 - assign \SHIFT_ROT_dec_sub0_opcode_in \opcode_in - sync init - end - process $group_5 - assign \SHIFT_ROT_dec_sub26_opcode_in 32'00000000000000000000000000000000 - assign \SHIFT_ROT_dec_sub26_opcode_in \opcode_in - sync init - end - process $group_6 - assign \SHIFT_ROT_dec_sub19_opcode_in 32'00000000000000000000000000000000 - assign \SHIFT_ROT_dec_sub19_opcode_in \opcode_in - sync init - end - process $group_7 - assign \SHIFT_ROT_dec_sub22_opcode_in 32'00000000000000000000000000000000 - assign \SHIFT_ROT_dec_sub22_opcode_in \opcode_in - sync init - end - process $group_8 - assign \SHIFT_ROT_dec_sub9_opcode_in 32'00000000000000000000000000000000 - assign \SHIFT_ROT_dec_sub9_opcode_in \opcode_in - sync init - end - process $group_9 - assign \SHIFT_ROT_dec_sub11_opcode_in 32'00000000000000000000000000000000 - assign \SHIFT_ROT_dec_sub11_opcode_in \opcode_in - sync init - end - process $group_10 - assign \SHIFT_ROT_dec_sub27_opcode_in 32'00000000000000000000000000000000 - assign \SHIFT_ROT_dec_sub27_opcode_in \opcode_in - sync init - end - process $group_11 - assign \SHIFT_ROT_dec_sub15_opcode_in 32'00000000000000000000000000000000 - assign \SHIFT_ROT_dec_sub15_opcode_in \opcode_in - sync init - end - process $group_12 - assign \SHIFT_ROT_dec_sub20_opcode_in 32'00000000000000000000000000000000 - assign \SHIFT_ROT_dec_sub20_opcode_in \opcode_in - sync init - end - process $group_13 - assign \SHIFT_ROT_dec_sub21_opcode_in 32'00000000000000000000000000000000 - assign \SHIFT_ROT_dec_sub21_opcode_in \opcode_in - sync init - end - process $group_14 - assign \SHIFT_ROT_dec_sub23_opcode_in 32'00000000000000000000000000000000 - assign \SHIFT_ROT_dec_sub23_opcode_in \opcode_in - sync init - end - process $group_15 - assign \SHIFT_ROT_dec_sub16_opcode_in 32'00000000000000000000000000000000 - assign \SHIFT_ROT_dec_sub16_opcode_in \opcode_in - sync init - end - process $group_16 - assign \SHIFT_ROT_dec_sub18_opcode_in 32'00000000000000000000000000000000 - assign \SHIFT_ROT_dec_sub18_opcode_in \opcode_in - sync init - end - process $group_17 - assign \SHIFT_ROT_dec_sub8_opcode_in 32'00000000000000000000000000000000 - assign \SHIFT_ROT_dec_sub8_opcode_in \opcode_in - sync init - end - process $group_18 - assign \SHIFT_ROT_dec_sub24_opcode_in 32'00000000000000000000000000000000 - assign \SHIFT_ROT_dec_sub24_opcode_in \opcode_in - sync init - end - process $group_19 - assign \SHIFT_ROT_dec_sub4_opcode_in 32'00000000000000000000000000000000 - assign \SHIFT_ROT_dec_sub4_opcode_in \opcode_in - sync init - end - attribute \enum_base_type "Function" - attribute \enum_value_00000000000 "NONE" - attribute \enum_value_00000000010 "ALU" - attribute \enum_value_00000000100 "LDST" - attribute \enum_value_00000001000 "SHIFT_ROT" - attribute \enum_value_00000010000 "LOGICAL" - attribute \enum_value_00000100000 "BRANCH" - attribute \enum_value_00001000000 "CR" - attribute \enum_value_00010000000 "TRAP" - attribute \enum_value_00100000000 "MUL" - attribute \enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 11 \SHIFT_ROT_function_unit$1 - attribute \enum_base_type "Function" - attribute \enum_value_00000000000 "NONE" - attribute \enum_value_00000000010 "ALU" - attribute \enum_value_00000000100 "LDST" - attribute \enum_value_00000001000 "SHIFT_ROT" - attribute \enum_value_00000010000 "LOGICAL" - attribute \enum_value_00000100000 "BRANCH" - attribute \enum_value_00001000000 "CR" - attribute \enum_value_00010000000 "TRAP" - attribute \enum_value_00100000000 "MUL" - attribute \enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 11 \SHIFT_ROT_function_unit$2 - attribute \enum_base_type "Function" - attribute \enum_value_00000000000 "NONE" - attribute \enum_value_00000000010 "ALU" - attribute \enum_value_00000000100 "LDST" - attribute \enum_value_00000001000 "SHIFT_ROT" - attribute \enum_value_00000010000 "LOGICAL" - attribute \enum_value_00000100000 "BRANCH" - attribute \enum_value_00001000000 "CR" - attribute \enum_value_00010000000 "TRAP" - attribute \enum_value_00100000000 "MUL" - attribute \enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 11 \SHIFT_ROT_function_unit$3 - attribute \enum_base_type "Function" - attribute \enum_value_00000000000 "NONE" - attribute \enum_value_00000000010 "ALU" - attribute \enum_value_00000000100 "LDST" - attribute \enum_value_00000001000 "SHIFT_ROT" - attribute \enum_value_00000010000 "LOGICAL" - attribute \enum_value_00000100000 "BRANCH" - attribute \enum_value_00001000000 "CR" - attribute \enum_value_00010000000 "TRAP" - attribute \enum_value_00100000000 "MUL" - attribute \enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 11 \SHIFT_ROT_function_unit$4 - attribute \enum_base_type "Function" - attribute \enum_value_00000000000 "NONE" - attribute \enum_value_00000000010 "ALU" - attribute \enum_value_00000000100 "LDST" - attribute \enum_value_00000001000 "SHIFT_ROT" - attribute \enum_value_00000010000 "LOGICAL" - attribute \enum_value_00000100000 "BRANCH" - attribute \enum_value_00001000000 "CR" - attribute \enum_value_00010000000 "TRAP" - attribute \enum_value_00100000000 "MUL" - attribute \enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 11 \SHIFT_ROT_function_unit$5 - attribute \enum_base_type "Function" - attribute \enum_value_00000000000 "NONE" - attribute \enum_value_00000000010 "ALU" - attribute \enum_value_00000000100 "LDST" - attribute \enum_value_00000001000 "SHIFT_ROT" - attribute \enum_value_00000010000 "LOGICAL" - attribute \enum_value_00000100000 "BRANCH" - attribute \enum_value_00001000000 "CR" - attribute \enum_value_00010000000 "TRAP" - attribute \enum_value_00100000000 "MUL" - attribute \enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 11 \SHIFT_ROT_function_unit$6 - attribute \enum_base_type "Function" - attribute \enum_value_00000000000 "NONE" - attribute \enum_value_00000000010 "ALU" - attribute \enum_value_00000000100 "LDST" - attribute \enum_value_00000001000 "SHIFT_ROT" - attribute \enum_value_00000010000 "LOGICAL" - attribute \enum_value_00000100000 "BRANCH" - attribute \enum_value_00001000000 "CR" - attribute \enum_value_00010000000 "TRAP" - attribute \enum_value_00100000000 "MUL" - attribute \enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 11 \SHIFT_ROT_function_unit$7 - attribute \enum_base_type "Function" - attribute \enum_value_00000000000 "NONE" - attribute \enum_value_00000000010 "ALU" - attribute \enum_value_00000000100 "LDST" - attribute \enum_value_00000001000 "SHIFT_ROT" - attribute \enum_value_00000010000 "LOGICAL" - attribute \enum_value_00000100000 "BRANCH" - attribute \enum_value_00001000000 "CR" - attribute \enum_value_00010000000 "TRAP" - attribute \enum_value_00100000000 "MUL" - attribute \enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 11 \SHIFT_ROT_function_unit$8 - attribute \enum_base_type "Function" - attribute \enum_value_00000000000 "NONE" - attribute \enum_value_00000000010 "ALU" - attribute \enum_value_00000000100 "LDST" - attribute \enum_value_00000001000 "SHIFT_ROT" - attribute \enum_value_00000010000 "LOGICAL" - attribute \enum_value_00000100000 "BRANCH" - attribute \enum_value_00001000000 "CR" - attribute \enum_value_00010000000 "TRAP" - attribute \enum_value_00100000000 "MUL" - attribute \enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 11 \SHIFT_ROT_function_unit$9 - attribute \enum_base_type "Function" - attribute \enum_value_00000000000 "NONE" - attribute \enum_value_00000000010 "ALU" - attribute \enum_value_00000000100 "LDST" - attribute \enum_value_00000001000 "SHIFT_ROT" - attribute \enum_value_00000010000 "LOGICAL" - attribute \enum_value_00000100000 "BRANCH" - attribute \enum_value_00001000000 "CR" - attribute \enum_value_00010000000 "TRAP" - attribute \enum_value_00100000000 "MUL" - attribute \enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 11 \SHIFT_ROT_function_unit$10 - attribute \enum_base_type "Function" - attribute \enum_value_00000000000 "NONE" - attribute \enum_value_00000000010 "ALU" - attribute \enum_value_00000000100 "LDST" - attribute \enum_value_00000001000 "SHIFT_ROT" - attribute \enum_value_00000010000 "LOGICAL" - attribute \enum_value_00000100000 "BRANCH" - attribute \enum_value_00001000000 "CR" - attribute \enum_value_00010000000 "TRAP" - attribute \enum_value_00100000000 "MUL" - attribute \enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 11 \SHIFT_ROT_function_unit$11 - attribute \enum_base_type "Function" - attribute \enum_value_00000000000 "NONE" - attribute \enum_value_00000000010 "ALU" - attribute \enum_value_00000000100 "LDST" - attribute \enum_value_00000001000 "SHIFT_ROT" - attribute \enum_value_00000010000 "LOGICAL" - attribute \enum_value_00000100000 "BRANCH" - attribute \enum_value_00001000000 "CR" - attribute \enum_value_00010000000 "TRAP" - attribute \enum_value_00100000000 "MUL" - attribute \enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 11 \SHIFT_ROT_function_unit$12 - attribute \enum_base_type "Function" - attribute \enum_value_00000000000 "NONE" - attribute \enum_value_00000000010 "ALU" - attribute \enum_value_00000000100 "LDST" - attribute \enum_value_00000001000 "SHIFT_ROT" - attribute \enum_value_00000010000 "LOGICAL" - attribute \enum_value_00000100000 "BRANCH" - attribute \enum_value_00001000000 "CR" - attribute \enum_value_00010000000 "TRAP" - attribute \enum_value_00100000000 "MUL" - attribute \enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 11 \SHIFT_ROT_function_unit$13 - attribute \enum_base_type "Function" - attribute \enum_value_00000000000 "NONE" - attribute \enum_value_00000000010 "ALU" - attribute \enum_value_00000000100 "LDST" - attribute \enum_value_00000001000 "SHIFT_ROT" - attribute \enum_value_00000010000 "LOGICAL" - attribute \enum_value_00000100000 "BRANCH" - attribute \enum_value_00001000000 "CR" - attribute \enum_value_00010000000 "TRAP" - attribute \enum_value_00100000000 "MUL" - attribute \enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 11 \SHIFT_ROT_function_unit$14 - attribute \enum_base_type "Function" - attribute \enum_value_00000000000 "NONE" - attribute \enum_value_00000000010 "ALU" - attribute \enum_value_00000000100 "LDST" - attribute \enum_value_00000001000 "SHIFT_ROT" - attribute \enum_value_00000010000 "LOGICAL" - attribute \enum_value_00000100000 "BRANCH" - attribute \enum_value_00001000000 "CR" - attribute \enum_value_00010000000 "TRAP" - attribute \enum_value_00100000000 "MUL" - attribute \enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 11 \SHIFT_ROT_function_unit$15 - process $group_20 - assign \SHIFT_ROT_function_unit 11'00000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:315" - switch \opc_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01010 - assign \SHIFT_ROT_function_unit \SHIFT_ROT_function_unit$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'11100 - assign \SHIFT_ROT_function_unit \SHIFT_ROT_function_unit$2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'00000 - assign \SHIFT_ROT_function_unit \SHIFT_ROT_function_unit$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'11010 - assign \SHIFT_ROT_function_unit \SHIFT_ROT_dec_sub26_SHIFT_ROT_function_unit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10011 - assign \SHIFT_ROT_function_unit \SHIFT_ROT_function_unit$4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10110 - assign \SHIFT_ROT_function_unit \SHIFT_ROT_function_unit$5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01001 - assign \SHIFT_ROT_function_unit \SHIFT_ROT_function_unit$6 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01011 - assign \SHIFT_ROT_function_unit \SHIFT_ROT_function_unit$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'11011 - assign \SHIFT_ROT_function_unit \SHIFT_ROT_dec_sub27_SHIFT_ROT_function_unit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01111 - assign \SHIFT_ROT_function_unit \SHIFT_ROT_function_unit$8 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10100 - assign \SHIFT_ROT_function_unit \SHIFT_ROT_function_unit$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10101 - assign \SHIFT_ROT_function_unit \SHIFT_ROT_function_unit$10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10111 - assign \SHIFT_ROT_function_unit \SHIFT_ROT_function_unit$11 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10000 - assign \SHIFT_ROT_function_unit \SHIFT_ROT_function_unit$12 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10010 - assign \SHIFT_ROT_function_unit \SHIFT_ROT_function_unit$13 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01000 - assign \SHIFT_ROT_function_unit \SHIFT_ROT_function_unit$14 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'11000 - assign \SHIFT_ROT_function_unit \SHIFT_ROT_dec_sub24_SHIFT_ROT_function_unit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'00100 - assign \SHIFT_ROT_function_unit \SHIFT_ROT_function_unit$15 - end - sync init - end - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 7 \SHIFT_ROT_internal_op$16 - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 7 \SHIFT_ROT_internal_op$17 - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - 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"/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:315" - switch \opc_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01010 - assign \SHIFT_ROT_internal_op \SHIFT_ROT_internal_op$16 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'11100 - assign \SHIFT_ROT_internal_op \SHIFT_ROT_internal_op$17 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'00000 - assign \SHIFT_ROT_internal_op \SHIFT_ROT_internal_op$18 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'11010 - assign \SHIFT_ROT_internal_op \SHIFT_ROT_dec_sub26_SHIFT_ROT_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10011 - assign \SHIFT_ROT_internal_op \SHIFT_ROT_internal_op$19 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10110 - assign \SHIFT_ROT_internal_op \SHIFT_ROT_internal_op$20 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01001 - assign \SHIFT_ROT_internal_op \SHIFT_ROT_internal_op$21 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01011 - assign \SHIFT_ROT_internal_op \SHIFT_ROT_internal_op$22 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'11011 - assign \SHIFT_ROT_internal_op \SHIFT_ROT_dec_sub27_SHIFT_ROT_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01111 - assign \SHIFT_ROT_internal_op \SHIFT_ROT_internal_op$23 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10100 - assign \SHIFT_ROT_internal_op \SHIFT_ROT_internal_op$24 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10101 - assign \SHIFT_ROT_internal_op \SHIFT_ROT_internal_op$25 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10111 - assign \SHIFT_ROT_internal_op \SHIFT_ROT_internal_op$26 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10000 - assign \SHIFT_ROT_internal_op \SHIFT_ROT_internal_op$27 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10010 - assign \SHIFT_ROT_internal_op \SHIFT_ROT_internal_op$28 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01000 - assign \SHIFT_ROT_internal_op \SHIFT_ROT_internal_op$29 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'11000 - assign \SHIFT_ROT_internal_op \SHIFT_ROT_dec_sub24_SHIFT_ROT_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'00100 - assign \SHIFT_ROT_internal_op \SHIFT_ROT_internal_op$30 - end - sync init - end - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 4 \SHIFT_ROT_in2_sel$31 - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 4 \SHIFT_ROT_in2_sel$32 - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 4 \SHIFT_ROT_in2_sel$33 - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 4 \SHIFT_ROT_in2_sel$34 - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 4 \SHIFT_ROT_in2_sel$35 - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 4 \SHIFT_ROT_in2_sel$36 - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 4 \SHIFT_ROT_in2_sel$37 - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 4 \SHIFT_ROT_in2_sel$38 - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 4 \SHIFT_ROT_in2_sel$39 - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 4 \SHIFT_ROT_in2_sel$40 - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 4 \SHIFT_ROT_in2_sel$41 - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 4 \SHIFT_ROT_in2_sel$42 - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 4 \SHIFT_ROT_in2_sel$43 - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 4 \SHIFT_ROT_in2_sel$44 - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 4 \SHIFT_ROT_in2_sel$45 - process $group_22 - assign \SHIFT_ROT_in2_sel 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:315" - switch \opc_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01010 - assign \SHIFT_ROT_in2_sel \SHIFT_ROT_in2_sel$31 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'11100 - assign \SHIFT_ROT_in2_sel \SHIFT_ROT_in2_sel$32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'00000 - assign \SHIFT_ROT_in2_sel \SHIFT_ROT_in2_sel$33 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'11010 - assign \SHIFT_ROT_in2_sel \SHIFT_ROT_dec_sub26_SHIFT_ROT_in2_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10011 - assign \SHIFT_ROT_in2_sel \SHIFT_ROT_in2_sel$34 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10110 - assign \SHIFT_ROT_in2_sel \SHIFT_ROT_in2_sel$35 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01001 - assign \SHIFT_ROT_in2_sel \SHIFT_ROT_in2_sel$36 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01011 - assign \SHIFT_ROT_in2_sel \SHIFT_ROT_in2_sel$37 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'11011 - assign \SHIFT_ROT_in2_sel \SHIFT_ROT_dec_sub27_SHIFT_ROT_in2_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01111 - assign \SHIFT_ROT_in2_sel \SHIFT_ROT_in2_sel$38 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10100 - assign \SHIFT_ROT_in2_sel \SHIFT_ROT_in2_sel$39 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10101 - assign \SHIFT_ROT_in2_sel \SHIFT_ROT_in2_sel$40 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10111 - assign \SHIFT_ROT_in2_sel \SHIFT_ROT_in2_sel$41 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10000 - assign \SHIFT_ROT_in2_sel \SHIFT_ROT_in2_sel$42 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10010 - assign \SHIFT_ROT_in2_sel \SHIFT_ROT_in2_sel$43 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01000 - assign \SHIFT_ROT_in2_sel \SHIFT_ROT_in2_sel$44 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'11000 - assign \SHIFT_ROT_in2_sel \SHIFT_ROT_dec_sub24_SHIFT_ROT_in2_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'00100 - assign \SHIFT_ROT_in2_sel \SHIFT_ROT_in2_sel$45 - end - sync init - end - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \SHIFT_ROT_cr_in$46 - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \SHIFT_ROT_cr_in$47 - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \SHIFT_ROT_cr_in$48 - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \SHIFT_ROT_cr_in$49 - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \SHIFT_ROT_cr_in$50 - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \SHIFT_ROT_cr_in$51 - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \SHIFT_ROT_cr_in$52 - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \SHIFT_ROT_cr_in$53 - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \SHIFT_ROT_cr_in$54 - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \SHIFT_ROT_cr_in$55 - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \SHIFT_ROT_cr_in$56 - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \SHIFT_ROT_cr_in$57 - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \SHIFT_ROT_cr_in$58 - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \SHIFT_ROT_cr_in$59 - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \SHIFT_ROT_cr_in$60 - process $group_23 - assign \SHIFT_ROT_cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:315" - switch \opc_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01010 - assign \SHIFT_ROT_cr_in \SHIFT_ROT_cr_in$46 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'11100 - assign \SHIFT_ROT_cr_in \SHIFT_ROT_cr_in$47 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'00000 - assign \SHIFT_ROT_cr_in \SHIFT_ROT_cr_in$48 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'11010 - assign \SHIFT_ROT_cr_in \SHIFT_ROT_dec_sub26_SHIFT_ROT_cr_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10011 - assign \SHIFT_ROT_cr_in \SHIFT_ROT_cr_in$49 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10110 - assign \SHIFT_ROT_cr_in \SHIFT_ROT_cr_in$50 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01001 - assign \SHIFT_ROT_cr_in \SHIFT_ROT_cr_in$51 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01011 - assign \SHIFT_ROT_cr_in \SHIFT_ROT_cr_in$52 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'11011 - assign \SHIFT_ROT_cr_in \SHIFT_ROT_dec_sub27_SHIFT_ROT_cr_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01111 - assign \SHIFT_ROT_cr_in \SHIFT_ROT_cr_in$53 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10100 - assign \SHIFT_ROT_cr_in \SHIFT_ROT_cr_in$54 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10101 - assign \SHIFT_ROT_cr_in \SHIFT_ROT_cr_in$55 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10111 - assign \SHIFT_ROT_cr_in \SHIFT_ROT_cr_in$56 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10000 - assign \SHIFT_ROT_cr_in \SHIFT_ROT_cr_in$57 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10010 - assign \SHIFT_ROT_cr_in \SHIFT_ROT_cr_in$58 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01000 - assign \SHIFT_ROT_cr_in \SHIFT_ROT_cr_in$59 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'11000 - assign \SHIFT_ROT_cr_in \SHIFT_ROT_dec_sub24_SHIFT_ROT_cr_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'00100 - assign \SHIFT_ROT_cr_in \SHIFT_ROT_cr_in$60 - end - sync init - end - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \SHIFT_ROT_cr_out$61 - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \SHIFT_ROT_cr_out$62 - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \SHIFT_ROT_cr_out$63 - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \SHIFT_ROT_cr_out$64 - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \SHIFT_ROT_cr_out$65 - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \SHIFT_ROT_cr_out$66 - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \SHIFT_ROT_cr_out$67 - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \SHIFT_ROT_cr_out$68 - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \SHIFT_ROT_cr_out$69 - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \SHIFT_ROT_cr_out$70 - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \SHIFT_ROT_cr_out$71 - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \SHIFT_ROT_cr_out$72 - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \SHIFT_ROT_cr_out$73 - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \SHIFT_ROT_cr_out$74 - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \SHIFT_ROT_cr_out$75 - process $group_24 - assign \SHIFT_ROT_cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:315" - switch \opc_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01010 - assign \SHIFT_ROT_cr_out \SHIFT_ROT_cr_out$61 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'11100 - assign \SHIFT_ROT_cr_out \SHIFT_ROT_cr_out$62 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'00000 - assign \SHIFT_ROT_cr_out \SHIFT_ROT_cr_out$63 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'11010 - assign \SHIFT_ROT_cr_out \SHIFT_ROT_dec_sub26_SHIFT_ROT_cr_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10011 - assign \SHIFT_ROT_cr_out \SHIFT_ROT_cr_out$64 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10110 - assign \SHIFT_ROT_cr_out \SHIFT_ROT_cr_out$65 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01001 - assign \SHIFT_ROT_cr_out \SHIFT_ROT_cr_out$66 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01011 - assign \SHIFT_ROT_cr_out \SHIFT_ROT_cr_out$67 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'11011 - assign \SHIFT_ROT_cr_out \SHIFT_ROT_dec_sub27_SHIFT_ROT_cr_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01111 - assign \SHIFT_ROT_cr_out \SHIFT_ROT_cr_out$68 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10100 - assign \SHIFT_ROT_cr_out \SHIFT_ROT_cr_out$69 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10101 - assign \SHIFT_ROT_cr_out \SHIFT_ROT_cr_out$70 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10111 - assign \SHIFT_ROT_cr_out \SHIFT_ROT_cr_out$71 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10000 - assign \SHIFT_ROT_cr_out \SHIFT_ROT_cr_out$72 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10010 - assign \SHIFT_ROT_cr_out \SHIFT_ROT_cr_out$73 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01000 - assign \SHIFT_ROT_cr_out \SHIFT_ROT_cr_out$74 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'11000 - assign \SHIFT_ROT_cr_out \SHIFT_ROT_dec_sub24_SHIFT_ROT_cr_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'00100 - assign \SHIFT_ROT_cr_out \SHIFT_ROT_cr_out$75 - end - sync init - end - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 2 \SHIFT_ROT_rc_sel$76 - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 2 \SHIFT_ROT_rc_sel$77 - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 2 \SHIFT_ROT_rc_sel$78 - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 2 \SHIFT_ROT_rc_sel$79 - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 2 \SHIFT_ROT_rc_sel$80 - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 2 \SHIFT_ROT_rc_sel$81 - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 2 \SHIFT_ROT_rc_sel$82 - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 2 \SHIFT_ROT_rc_sel$83 - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 2 \SHIFT_ROT_rc_sel$84 - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 2 \SHIFT_ROT_rc_sel$85 - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 2 \SHIFT_ROT_rc_sel$86 - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 2 \SHIFT_ROT_rc_sel$87 - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 2 \SHIFT_ROT_rc_sel$88 - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 2 \SHIFT_ROT_rc_sel$89 - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 2 \SHIFT_ROT_rc_sel$90 - process $group_25 - assign \SHIFT_ROT_rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:315" - switch \opc_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01010 - assign \SHIFT_ROT_rc_sel \SHIFT_ROT_rc_sel$76 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'11100 - assign \SHIFT_ROT_rc_sel \SHIFT_ROT_rc_sel$77 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'00000 - assign \SHIFT_ROT_rc_sel \SHIFT_ROT_rc_sel$78 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'11010 - assign \SHIFT_ROT_rc_sel \SHIFT_ROT_dec_sub26_SHIFT_ROT_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10011 - assign \SHIFT_ROT_rc_sel \SHIFT_ROT_rc_sel$79 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10110 - assign \SHIFT_ROT_rc_sel \SHIFT_ROT_rc_sel$80 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01001 - assign \SHIFT_ROT_rc_sel \SHIFT_ROT_rc_sel$81 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01011 - assign \SHIFT_ROT_rc_sel \SHIFT_ROT_rc_sel$82 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'11011 - assign \SHIFT_ROT_rc_sel \SHIFT_ROT_dec_sub27_SHIFT_ROT_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01111 - assign \SHIFT_ROT_rc_sel \SHIFT_ROT_rc_sel$83 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10100 - assign \SHIFT_ROT_rc_sel \SHIFT_ROT_rc_sel$84 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10101 - assign \SHIFT_ROT_rc_sel \SHIFT_ROT_rc_sel$85 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10111 - assign \SHIFT_ROT_rc_sel \SHIFT_ROT_rc_sel$86 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10000 - assign \SHIFT_ROT_rc_sel \SHIFT_ROT_rc_sel$87 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10010 - assign \SHIFT_ROT_rc_sel \SHIFT_ROT_rc_sel$88 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01000 - assign \SHIFT_ROT_rc_sel \SHIFT_ROT_rc_sel$89 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'11000 - assign \SHIFT_ROT_rc_sel \SHIFT_ROT_dec_sub24_SHIFT_ROT_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'00100 - assign \SHIFT_ROT_rc_sel \SHIFT_ROT_rc_sel$90 - end - sync init - end - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 2 \SHIFT_ROT_cry_in$91 - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 2 \SHIFT_ROT_cry_in$92 - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 2 \SHIFT_ROT_cry_in$93 - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 2 \SHIFT_ROT_cry_in$94 - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 2 \SHIFT_ROT_cry_in$95 - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 2 \SHIFT_ROT_cry_in$96 - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 2 \SHIFT_ROT_cry_in$97 - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 2 \SHIFT_ROT_cry_in$98 - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 2 \SHIFT_ROT_cry_in$99 - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 2 \SHIFT_ROT_cry_in$100 - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 2 \SHIFT_ROT_cry_in$101 - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 2 \SHIFT_ROT_cry_in$102 - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 2 \SHIFT_ROT_cry_in$103 - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 2 \SHIFT_ROT_cry_in$104 - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 2 \SHIFT_ROT_cry_in$105 - process $group_26 - assign \SHIFT_ROT_cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:315" - switch \opc_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01010 - assign \SHIFT_ROT_cry_in \SHIFT_ROT_cry_in$91 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'11100 - assign \SHIFT_ROT_cry_in \SHIFT_ROT_cry_in$92 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'00000 - assign \SHIFT_ROT_cry_in \SHIFT_ROT_cry_in$93 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'11010 - assign \SHIFT_ROT_cry_in \SHIFT_ROT_dec_sub26_SHIFT_ROT_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10011 - assign \SHIFT_ROT_cry_in \SHIFT_ROT_cry_in$94 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10110 - assign \SHIFT_ROT_cry_in \SHIFT_ROT_cry_in$95 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01001 - assign \SHIFT_ROT_cry_in \SHIFT_ROT_cry_in$96 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01011 - assign \SHIFT_ROT_cry_in \SHIFT_ROT_cry_in$97 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'11011 - assign \SHIFT_ROT_cry_in \SHIFT_ROT_dec_sub27_SHIFT_ROT_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01111 - assign \SHIFT_ROT_cry_in \SHIFT_ROT_cry_in$98 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10100 - assign \SHIFT_ROT_cry_in \SHIFT_ROT_cry_in$99 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10101 - assign \SHIFT_ROT_cry_in \SHIFT_ROT_cry_in$100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10111 - assign \SHIFT_ROT_cry_in \SHIFT_ROT_cry_in$101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10000 - assign \SHIFT_ROT_cry_in \SHIFT_ROT_cry_in$102 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10010 - assign \SHIFT_ROT_cry_in \SHIFT_ROT_cry_in$103 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01000 - assign \SHIFT_ROT_cry_in \SHIFT_ROT_cry_in$104 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'11000 - assign \SHIFT_ROT_cry_in \SHIFT_ROT_dec_sub24_SHIFT_ROT_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'00100 - assign \SHIFT_ROT_cry_in \SHIFT_ROT_cry_in$105 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \SHIFT_ROT_cry_out$106 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \SHIFT_ROT_cry_out$107 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \SHIFT_ROT_cry_out$108 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \SHIFT_ROT_cry_out$109 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \SHIFT_ROT_cry_out$110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \SHIFT_ROT_cry_out$111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \SHIFT_ROT_cry_out$112 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \SHIFT_ROT_cry_out$113 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \SHIFT_ROT_cry_out$114 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \SHIFT_ROT_cry_out$115 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \SHIFT_ROT_cry_out$116 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \SHIFT_ROT_cry_out$117 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \SHIFT_ROT_cry_out$118 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \SHIFT_ROT_cry_out$119 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \SHIFT_ROT_cry_out$120 - process $group_27 - assign \SHIFT_ROT_cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:315" - switch \opc_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01010 - assign \SHIFT_ROT_cry_out \SHIFT_ROT_cry_out$106 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'11100 - assign \SHIFT_ROT_cry_out \SHIFT_ROT_cry_out$107 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'00000 - assign \SHIFT_ROT_cry_out \SHIFT_ROT_cry_out$108 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'11010 - assign \SHIFT_ROT_cry_out \SHIFT_ROT_dec_sub26_SHIFT_ROT_cry_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10011 - assign \SHIFT_ROT_cry_out \SHIFT_ROT_cry_out$109 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10110 - assign \SHIFT_ROT_cry_out \SHIFT_ROT_cry_out$110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01001 - assign \SHIFT_ROT_cry_out \SHIFT_ROT_cry_out$111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01011 - assign \SHIFT_ROT_cry_out \SHIFT_ROT_cry_out$112 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'11011 - assign \SHIFT_ROT_cry_out \SHIFT_ROT_dec_sub27_SHIFT_ROT_cry_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01111 - assign \SHIFT_ROT_cry_out \SHIFT_ROT_cry_out$113 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10100 - assign \SHIFT_ROT_cry_out \SHIFT_ROT_cry_out$114 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10101 - assign \SHIFT_ROT_cry_out \SHIFT_ROT_cry_out$115 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10111 - assign \SHIFT_ROT_cry_out \SHIFT_ROT_cry_out$116 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10000 - assign \SHIFT_ROT_cry_out \SHIFT_ROT_cry_out$117 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10010 - assign \SHIFT_ROT_cry_out \SHIFT_ROT_cry_out$118 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01000 - assign \SHIFT_ROT_cry_out \SHIFT_ROT_cry_out$119 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'11000 - assign \SHIFT_ROT_cry_out \SHIFT_ROT_dec_sub24_SHIFT_ROT_cry_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'00100 - assign \SHIFT_ROT_cry_out \SHIFT_ROT_cry_out$120 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \SHIFT_ROT_is_32b$121 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \SHIFT_ROT_is_32b$122 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \SHIFT_ROT_is_32b$123 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \SHIFT_ROT_is_32b$124 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \SHIFT_ROT_is_32b$125 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \SHIFT_ROT_is_32b$126 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \SHIFT_ROT_is_32b$127 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \SHIFT_ROT_is_32b$128 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \SHIFT_ROT_is_32b$129 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \SHIFT_ROT_is_32b$130 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \SHIFT_ROT_is_32b$131 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \SHIFT_ROT_is_32b$132 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \SHIFT_ROT_is_32b$133 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \SHIFT_ROT_is_32b$134 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \SHIFT_ROT_is_32b$135 - process $group_28 - assign \SHIFT_ROT_is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:315" - switch \opc_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01010 - assign \SHIFT_ROT_is_32b \SHIFT_ROT_is_32b$121 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'11100 - assign \SHIFT_ROT_is_32b \SHIFT_ROT_is_32b$122 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'00000 - assign \SHIFT_ROT_is_32b \SHIFT_ROT_is_32b$123 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'11010 - assign \SHIFT_ROT_is_32b \SHIFT_ROT_dec_sub26_SHIFT_ROT_is_32b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10011 - assign \SHIFT_ROT_is_32b \SHIFT_ROT_is_32b$124 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10110 - assign \SHIFT_ROT_is_32b \SHIFT_ROT_is_32b$125 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01001 - assign \SHIFT_ROT_is_32b \SHIFT_ROT_is_32b$126 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01011 - assign \SHIFT_ROT_is_32b \SHIFT_ROT_is_32b$127 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'11011 - assign \SHIFT_ROT_is_32b \SHIFT_ROT_dec_sub27_SHIFT_ROT_is_32b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01111 - assign \SHIFT_ROT_is_32b \SHIFT_ROT_is_32b$128 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10100 - assign \SHIFT_ROT_is_32b \SHIFT_ROT_is_32b$129 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10101 - assign \SHIFT_ROT_is_32b \SHIFT_ROT_is_32b$130 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10111 - assign \SHIFT_ROT_is_32b \SHIFT_ROT_is_32b$131 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10000 - assign \SHIFT_ROT_is_32b \SHIFT_ROT_is_32b$132 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10010 - assign \SHIFT_ROT_is_32b \SHIFT_ROT_is_32b$133 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01000 - assign \SHIFT_ROT_is_32b \SHIFT_ROT_is_32b$134 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'11000 - assign \SHIFT_ROT_is_32b \SHIFT_ROT_dec_sub24_SHIFT_ROT_is_32b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'00100 - assign \SHIFT_ROT_is_32b \SHIFT_ROT_is_32b$135 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \SHIFT_ROT_sgn$136 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \SHIFT_ROT_sgn$137 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \SHIFT_ROT_sgn$138 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \SHIFT_ROT_sgn$139 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \SHIFT_ROT_sgn$140 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \SHIFT_ROT_sgn$141 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \SHIFT_ROT_sgn$142 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \SHIFT_ROT_sgn$143 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \SHIFT_ROT_sgn$144 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \SHIFT_ROT_sgn$145 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \SHIFT_ROT_sgn$146 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \SHIFT_ROT_sgn$147 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \SHIFT_ROT_sgn$148 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \SHIFT_ROT_sgn$149 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \SHIFT_ROT_sgn$150 - process $group_29 - assign \SHIFT_ROT_sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:315" - switch \opc_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01010 - assign \SHIFT_ROT_sgn \SHIFT_ROT_sgn$136 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'11100 - assign \SHIFT_ROT_sgn \SHIFT_ROT_sgn$137 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'00000 - assign \SHIFT_ROT_sgn \SHIFT_ROT_sgn$138 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'11010 - assign \SHIFT_ROT_sgn \SHIFT_ROT_dec_sub26_SHIFT_ROT_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10011 - assign \SHIFT_ROT_sgn \SHIFT_ROT_sgn$139 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10110 - assign \SHIFT_ROT_sgn \SHIFT_ROT_sgn$140 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01001 - assign \SHIFT_ROT_sgn \SHIFT_ROT_sgn$141 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01011 - assign \SHIFT_ROT_sgn \SHIFT_ROT_sgn$142 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'11011 - assign \SHIFT_ROT_sgn \SHIFT_ROT_dec_sub27_SHIFT_ROT_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01111 - assign \SHIFT_ROT_sgn \SHIFT_ROT_sgn$143 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10100 - assign \SHIFT_ROT_sgn \SHIFT_ROT_sgn$144 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10101 - assign \SHIFT_ROT_sgn \SHIFT_ROT_sgn$145 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10111 - assign \SHIFT_ROT_sgn \SHIFT_ROT_sgn$146 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10000 - assign \SHIFT_ROT_sgn \SHIFT_ROT_sgn$147 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10010 - assign \SHIFT_ROT_sgn \SHIFT_ROT_sgn$148 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01000 - assign \SHIFT_ROT_sgn \SHIFT_ROT_sgn$149 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'11000 - assign \SHIFT_ROT_sgn \SHIFT_ROT_dec_sub24_SHIFT_ROT_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'00100 - assign \SHIFT_ROT_sgn \SHIFT_ROT_sgn$150 - end - sync init - end - connect \SHIFT_ROT_function_unit$1 11'00000000000 - connect \SHIFT_ROT_function_unit$2 11'00000000000 - connect \SHIFT_ROT_function_unit$3 11'00000000000 - connect \SHIFT_ROT_function_unit$4 11'00000000000 - connect \SHIFT_ROT_function_unit$5 11'00000000000 - connect \SHIFT_ROT_function_unit$6 11'00000000000 - connect \SHIFT_ROT_function_unit$7 11'00000000000 - connect \SHIFT_ROT_function_unit$8 11'00000000000 - connect \SHIFT_ROT_function_unit$9 11'00000000000 - connect \SHIFT_ROT_function_unit$10 11'00000000000 - connect \SHIFT_ROT_function_unit$11 11'00000000000 - connect \SHIFT_ROT_function_unit$12 11'00000000000 - connect \SHIFT_ROT_function_unit$13 11'00000000000 - connect \SHIFT_ROT_function_unit$14 11'00000000000 - connect \SHIFT_ROT_function_unit$15 11'00000000000 - connect \SHIFT_ROT_internal_op$16 7'0000000 - connect \SHIFT_ROT_internal_op$17 7'0000000 - connect \SHIFT_ROT_internal_op$18 7'0000000 - connect \SHIFT_ROT_internal_op$19 7'0000000 - connect \SHIFT_ROT_internal_op$20 7'0000000 - connect \SHIFT_ROT_internal_op$21 7'0000000 - connect \SHIFT_ROT_internal_op$22 7'0000000 - connect \SHIFT_ROT_internal_op$23 7'0000000 - connect \SHIFT_ROT_internal_op$24 7'0000000 - connect \SHIFT_ROT_internal_op$25 7'0000000 - connect \SHIFT_ROT_internal_op$26 7'0000000 - connect \SHIFT_ROT_internal_op$27 7'0000000 - connect \SHIFT_ROT_internal_op$28 7'0000000 - connect \SHIFT_ROT_internal_op$29 7'0000000 - connect \SHIFT_ROT_internal_op$30 7'0000000 - connect \SHIFT_ROT_in2_sel$31 4'0000 - connect \SHIFT_ROT_in2_sel$32 4'0000 - connect \SHIFT_ROT_in2_sel$33 4'0000 - connect \SHIFT_ROT_in2_sel$34 4'0000 - connect \SHIFT_ROT_in2_sel$35 4'0000 - connect \SHIFT_ROT_in2_sel$36 4'0000 - connect \SHIFT_ROT_in2_sel$37 4'0000 - connect \SHIFT_ROT_in2_sel$38 4'0000 - connect \SHIFT_ROT_in2_sel$39 4'0000 - connect \SHIFT_ROT_in2_sel$40 4'0000 - connect \SHIFT_ROT_in2_sel$41 4'0000 - connect \SHIFT_ROT_in2_sel$42 4'0000 - connect \SHIFT_ROT_in2_sel$43 4'0000 - connect \SHIFT_ROT_in2_sel$44 4'0000 - connect \SHIFT_ROT_in2_sel$45 4'0000 - connect \SHIFT_ROT_cr_in$46 3'000 - connect \SHIFT_ROT_cr_in$47 3'000 - connect \SHIFT_ROT_cr_in$48 3'000 - connect \SHIFT_ROT_cr_in$49 3'000 - connect \SHIFT_ROT_cr_in$50 3'000 - connect \SHIFT_ROT_cr_in$51 3'000 - connect \SHIFT_ROT_cr_in$52 3'000 - connect \SHIFT_ROT_cr_in$53 3'000 - connect \SHIFT_ROT_cr_in$54 3'000 - connect \SHIFT_ROT_cr_in$55 3'000 - connect \SHIFT_ROT_cr_in$56 3'000 - connect \SHIFT_ROT_cr_in$57 3'000 - connect \SHIFT_ROT_cr_in$58 3'000 - connect \SHIFT_ROT_cr_in$59 3'000 - connect \SHIFT_ROT_cr_in$60 3'000 - connect \SHIFT_ROT_cr_out$61 3'000 - connect \SHIFT_ROT_cr_out$62 3'000 - connect \SHIFT_ROT_cr_out$63 3'000 - connect \SHIFT_ROT_cr_out$64 3'000 - connect \SHIFT_ROT_cr_out$65 3'000 - connect \SHIFT_ROT_cr_out$66 3'000 - connect \SHIFT_ROT_cr_out$67 3'000 - connect \SHIFT_ROT_cr_out$68 3'000 - connect \SHIFT_ROT_cr_out$69 3'000 - connect \SHIFT_ROT_cr_out$70 3'000 - connect \SHIFT_ROT_cr_out$71 3'000 - connect \SHIFT_ROT_cr_out$72 3'000 - connect \SHIFT_ROT_cr_out$73 3'000 - connect \SHIFT_ROT_cr_out$74 3'000 - connect \SHIFT_ROT_cr_out$75 3'000 - connect \SHIFT_ROT_rc_sel$76 2'00 - connect \SHIFT_ROT_rc_sel$77 2'00 - connect \SHIFT_ROT_rc_sel$78 2'00 - connect \SHIFT_ROT_rc_sel$79 2'00 - connect \SHIFT_ROT_rc_sel$80 2'00 - connect \SHIFT_ROT_rc_sel$81 2'00 - connect \SHIFT_ROT_rc_sel$82 2'00 - connect \SHIFT_ROT_rc_sel$83 2'00 - connect \SHIFT_ROT_rc_sel$84 2'00 - connect \SHIFT_ROT_rc_sel$85 2'00 - connect \SHIFT_ROT_rc_sel$86 2'00 - connect \SHIFT_ROT_rc_sel$87 2'00 - connect \SHIFT_ROT_rc_sel$88 2'00 - connect \SHIFT_ROT_rc_sel$89 2'00 - connect \SHIFT_ROT_rc_sel$90 2'00 - connect \SHIFT_ROT_cry_in$91 2'00 - connect \SHIFT_ROT_cry_in$92 2'00 - connect \SHIFT_ROT_cry_in$93 2'00 - connect \SHIFT_ROT_cry_in$94 2'00 - connect \SHIFT_ROT_cry_in$95 2'00 - connect \SHIFT_ROT_cry_in$96 2'00 - connect \SHIFT_ROT_cry_in$97 2'00 - connect \SHIFT_ROT_cry_in$98 2'00 - connect \SHIFT_ROT_cry_in$99 2'00 - connect \SHIFT_ROT_cry_in$100 2'00 - connect \SHIFT_ROT_cry_in$101 2'00 - connect \SHIFT_ROT_cry_in$102 2'00 - connect \SHIFT_ROT_cry_in$103 2'00 - connect \SHIFT_ROT_cry_in$104 2'00 - connect \SHIFT_ROT_cry_in$105 2'00 - connect \SHIFT_ROT_cry_out$106 1'0 - connect \SHIFT_ROT_cry_out$107 1'0 - connect \SHIFT_ROT_cry_out$108 1'0 - connect \SHIFT_ROT_cry_out$109 1'0 - connect \SHIFT_ROT_cry_out$110 1'0 - connect \SHIFT_ROT_cry_out$111 1'0 - connect \SHIFT_ROT_cry_out$112 1'0 - connect \SHIFT_ROT_cry_out$113 1'0 - connect \SHIFT_ROT_cry_out$114 1'0 - connect \SHIFT_ROT_cry_out$115 1'0 - connect \SHIFT_ROT_cry_out$116 1'0 - connect \SHIFT_ROT_cry_out$117 1'0 - connect \SHIFT_ROT_cry_out$118 1'0 - connect \SHIFT_ROT_cry_out$119 1'0 - connect \SHIFT_ROT_cry_out$120 1'0 - connect \SHIFT_ROT_is_32b$121 1'0 - connect \SHIFT_ROT_is_32b$122 1'0 - connect \SHIFT_ROT_is_32b$123 1'0 - connect \SHIFT_ROT_is_32b$124 1'0 - connect \SHIFT_ROT_is_32b$125 1'0 - connect \SHIFT_ROT_is_32b$126 1'0 - connect \SHIFT_ROT_is_32b$127 1'0 - connect \SHIFT_ROT_is_32b$128 1'0 - connect \SHIFT_ROT_is_32b$129 1'0 - connect \SHIFT_ROT_is_32b$130 1'0 - connect \SHIFT_ROT_is_32b$131 1'0 - connect \SHIFT_ROT_is_32b$132 1'0 - connect \SHIFT_ROT_is_32b$133 1'0 - connect \SHIFT_ROT_is_32b$134 1'0 - connect \SHIFT_ROT_is_32b$135 1'0 - connect \SHIFT_ROT_sgn$136 1'0 - connect \SHIFT_ROT_sgn$137 1'0 - connect \SHIFT_ROT_sgn$138 1'0 - connect \SHIFT_ROT_sgn$139 1'0 - connect \SHIFT_ROT_sgn$140 1'0 - connect \SHIFT_ROT_sgn$141 1'0 - connect \SHIFT_ROT_sgn$142 1'0 - connect \SHIFT_ROT_sgn$143 1'0 - connect \SHIFT_ROT_sgn$144 1'0 - connect \SHIFT_ROT_sgn$145 1'0 - connect \SHIFT_ROT_sgn$146 1'0 - connect \SHIFT_ROT_sgn$147 1'0 - connect \SHIFT_ROT_sgn$148 1'0 - connect \SHIFT_ROT_sgn$149 1'0 - connect \SHIFT_ROT_sgn$150 1'0 -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.dec_SHIFT_ROT.dec.SHIFT_ROT_dec58" -module \SHIFT_ROT_dec58 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" - wire width 32 input 0 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:308" - wire width 2 \opcode_switch - process $group_0 - assign \opcode_switch 2'00 - assign \opcode_switch \opcode_in [1:0] - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.dec_SHIFT_ROT.dec.SHIFT_ROT_dec62" -module \SHIFT_ROT_dec62 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" - wire width 32 input 0 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:308" - wire width 2 \opcode_switch - process $group_0 - assign \opcode_switch 2'00 - assign \opcode_switch \opcode_in [1:0] - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.dec_SHIFT_ROT.dec" -module \dec$185 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:384" - wire width 32 input 0 \raw_opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:385" - wire width 1 input 1 \bigendian - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" - wire width 32 output 2 \opcode_in - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 2 output 3 \SHIFT_ROT_rc_sel - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 output 4 \SHIFT_ROT_cr_in - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 output 5 \SHIFT_ROT_cr_out - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 7 output 6 \SHIFT_ROT_internal_op - attribute \enum_base_type "Function" - attribute \enum_value_00000000000 "NONE" - attribute \enum_value_00000000010 "ALU" - attribute \enum_value_00000000100 "LDST" - attribute \enum_value_00000001000 "SHIFT_ROT" - attribute \enum_value_00000010000 "LOGICAL" - attribute \enum_value_00000100000 "BRANCH" - attribute \enum_value_00001000000 "CR" - attribute \enum_value_00010000000 "TRAP" - attribute \enum_value_00100000000 "MUL" - attribute \enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 11 output 7 \SHIFT_ROT_function_unit - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 4 output 8 \SHIFT_ROT_in2_sel - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 2 output 9 \SHIFT_ROT_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 output 10 \SHIFT_ROT_cry_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 output 11 \SHIFT_ROT_is_32b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 output 12 \SHIFT_ROT_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 16 output 13 \SHIFT_ROT_SI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 16 output 14 \SHIFT_ROT_UI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 5 output 15 \SHIFT_ROT_SH32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 6 output 16 \SHIFT_ROT_sh - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 24 output 17 \SHIFT_ROT_LI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 1 output 18 \SHIFT_ROT_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 1 output 19 \SHIFT_ROT_OE - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 14 output 20 \SHIFT_ROT_BD - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 5 output 21 \SHIFT_ROT_BB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 5 output 22 \SHIFT_ROT_BA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 5 output 23 \SHIFT_ROT_BT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 8 output 24 \SHIFT_ROT_FXM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 5 output 25 \SHIFT_ROT_BI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 14 output 26 \SHIFT_ROT_DS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 5 output 27 \SHIFT_ROT_BC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 3 output 28 \X_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 3 output 29 \X_BFA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 output 30 \XL_BT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" - wire width 32 \SHIFT_ROT_dec19_opcode_in - cell \SHIFT_ROT_dec19 \SHIFT_ROT_dec19 - connect \opcode_in \SHIFT_ROT_dec19_opcode_in - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" - wire width 32 \SHIFT_ROT_dec30_opcode_in - attribute \enum_base_type "Function" - attribute \enum_value_00000000000 "NONE" - attribute \enum_value_00000000010 "ALU" - attribute \enum_value_00000000100 "LDST" - attribute \enum_value_00000001000 "SHIFT_ROT" - attribute \enum_value_00000010000 "LOGICAL" - attribute \enum_value_00000100000 "BRANCH" - attribute \enum_value_00001000000 "CR" - attribute \enum_value_00010000000 "TRAP" - attribute \enum_value_00100000000 "MUL" - attribute \enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 11 \SHIFT_ROT_dec30_SHIFT_ROT_function_unit - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 7 \SHIFT_ROT_dec30_SHIFT_ROT_internal_op - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 4 \SHIFT_ROT_dec30_SHIFT_ROT_in2_sel - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \SHIFT_ROT_dec30_SHIFT_ROT_cr_in - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \SHIFT_ROT_dec30_SHIFT_ROT_cr_out - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 2 \SHIFT_ROT_dec30_SHIFT_ROT_rc_sel - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 2 \SHIFT_ROT_dec30_SHIFT_ROT_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \SHIFT_ROT_dec30_SHIFT_ROT_cry_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \SHIFT_ROT_dec30_SHIFT_ROT_is_32b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \SHIFT_ROT_dec30_SHIFT_ROT_sgn - cell \SHIFT_ROT_dec30 \SHIFT_ROT_dec30 - connect \opcode_in \SHIFT_ROT_dec30_opcode_in - connect \SHIFT_ROT_function_unit \SHIFT_ROT_dec30_SHIFT_ROT_function_unit - connect \SHIFT_ROT_internal_op \SHIFT_ROT_dec30_SHIFT_ROT_internal_op - connect \SHIFT_ROT_in2_sel \SHIFT_ROT_dec30_SHIFT_ROT_in2_sel - connect \SHIFT_ROT_cr_in \SHIFT_ROT_dec30_SHIFT_ROT_cr_in - connect \SHIFT_ROT_cr_out \SHIFT_ROT_dec30_SHIFT_ROT_cr_out - connect \SHIFT_ROT_rc_sel \SHIFT_ROT_dec30_SHIFT_ROT_rc_sel - connect \SHIFT_ROT_cry_in \SHIFT_ROT_dec30_SHIFT_ROT_cry_in - connect \SHIFT_ROT_cry_out \SHIFT_ROT_dec30_SHIFT_ROT_cry_out - connect \SHIFT_ROT_is_32b \SHIFT_ROT_dec30_SHIFT_ROT_is_32b - connect \SHIFT_ROT_sgn \SHIFT_ROT_dec30_SHIFT_ROT_sgn - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" - wire width 32 \SHIFT_ROT_dec31_opcode_in - attribute \enum_base_type "Function" - attribute \enum_value_00000000000 "NONE" - attribute \enum_value_00000000010 "ALU" - attribute \enum_value_00000000100 "LDST" - attribute \enum_value_00000001000 "SHIFT_ROT" - attribute \enum_value_00000010000 "LOGICAL" - attribute \enum_value_00000100000 "BRANCH" - attribute \enum_value_00001000000 "CR" - attribute \enum_value_00010000000 "TRAP" - attribute \enum_value_00100000000 "MUL" - attribute \enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 11 \SHIFT_ROT_dec31_SHIFT_ROT_function_unit - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 7 \SHIFT_ROT_dec31_SHIFT_ROT_internal_op - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 4 \SHIFT_ROT_dec31_SHIFT_ROT_in2_sel - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \SHIFT_ROT_dec31_SHIFT_ROT_cr_in - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \SHIFT_ROT_dec31_SHIFT_ROT_cr_out - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 2 \SHIFT_ROT_dec31_SHIFT_ROT_rc_sel - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 2 \SHIFT_ROT_dec31_SHIFT_ROT_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \SHIFT_ROT_dec31_SHIFT_ROT_cry_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \SHIFT_ROT_dec31_SHIFT_ROT_is_32b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \SHIFT_ROT_dec31_SHIFT_ROT_sgn - cell \SHIFT_ROT_dec31 \SHIFT_ROT_dec31 - connect \opcode_in \SHIFT_ROT_dec31_opcode_in - connect \SHIFT_ROT_function_unit \SHIFT_ROT_dec31_SHIFT_ROT_function_unit - connect \SHIFT_ROT_internal_op \SHIFT_ROT_dec31_SHIFT_ROT_internal_op - connect \SHIFT_ROT_in2_sel \SHIFT_ROT_dec31_SHIFT_ROT_in2_sel - connect \SHIFT_ROT_cr_in \SHIFT_ROT_dec31_SHIFT_ROT_cr_in - connect \SHIFT_ROT_cr_out \SHIFT_ROT_dec31_SHIFT_ROT_cr_out - connect \SHIFT_ROT_rc_sel \SHIFT_ROT_dec31_SHIFT_ROT_rc_sel - connect \SHIFT_ROT_cry_in \SHIFT_ROT_dec31_SHIFT_ROT_cry_in - connect \SHIFT_ROT_cry_out \SHIFT_ROT_dec31_SHIFT_ROT_cry_out - connect \SHIFT_ROT_is_32b \SHIFT_ROT_dec31_SHIFT_ROT_is_32b - connect \SHIFT_ROT_sgn \SHIFT_ROT_dec31_SHIFT_ROT_sgn - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" - wire width 32 \SHIFT_ROT_dec58_opcode_in - cell \SHIFT_ROT_dec58 \SHIFT_ROT_dec58 - connect \opcode_in \SHIFT_ROT_dec58_opcode_in - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" - wire width 32 \SHIFT_ROT_dec62_opcode_in - cell \SHIFT_ROT_dec62 \SHIFT_ROT_dec62 - connect \opcode_in \SHIFT_ROT_dec62_opcode_in - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:308" - wire width 6 \opcode_switch - process $group_0 - assign \opcode_switch 6'000000 - assign \opcode_switch \opcode_in [31:26] - sync init - end - process $group_1 - assign \SHIFT_ROT_dec19_opcode_in 32'00000000000000000000000000000000 - assign \SHIFT_ROT_dec19_opcode_in \opcode_in - sync init - end - process $group_2 - assign \SHIFT_ROT_dec30_opcode_in 32'00000000000000000000000000000000 - assign \SHIFT_ROT_dec30_opcode_in \opcode_in - sync init - end - process $group_3 - assign \SHIFT_ROT_dec31_opcode_in 32'00000000000000000000000000000000 - assign \SHIFT_ROT_dec31_opcode_in \opcode_in - sync init - end - process $group_4 - assign \SHIFT_ROT_dec58_opcode_in 32'00000000000000000000000000000000 - assign \SHIFT_ROT_dec58_opcode_in \opcode_in - sync init - end - process $group_5 - assign \SHIFT_ROT_dec62_opcode_in 32'00000000000000000000000000000000 - assign \SHIFT_ROT_dec62_opcode_in \opcode_in - sync init - end - attribute \enum_base_type "Function" - attribute \enum_value_00000000000 "NONE" - attribute \enum_value_00000000010 "ALU" - attribute \enum_value_00000000100 "LDST" - attribute \enum_value_00000001000 "SHIFT_ROT" - attribute \enum_value_00000010000 "LOGICAL" - attribute \enum_value_00000100000 "BRANCH" - attribute \enum_value_00001000000 "CR" - attribute \enum_value_00010000000 "TRAP" - attribute \enum_value_00100000000 "MUL" - attribute \enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 11 \SHIFT_ROT_function_unit$1 - attribute \enum_base_type "Function" - attribute \enum_value_00000000000 "NONE" - attribute \enum_value_00000000010 "ALU" - attribute \enum_value_00000000100 "LDST" - attribute \enum_value_00000001000 "SHIFT_ROT" - attribute \enum_value_00000010000 "LOGICAL" - attribute \enum_value_00000100000 "BRANCH" - attribute \enum_value_00001000000 "CR" - attribute \enum_value_00010000000 "TRAP" - attribute \enum_value_00100000000 "MUL" - attribute \enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 11 \SHIFT_ROT_function_unit$2 - attribute \enum_base_type "Function" - attribute \enum_value_00000000000 "NONE" - attribute \enum_value_00000000010 "ALU" - attribute \enum_value_00000000100 "LDST" - attribute \enum_value_00000001000 "SHIFT_ROT" - attribute \enum_value_00000010000 "LOGICAL" - attribute \enum_value_00000100000 "BRANCH" - attribute \enum_value_00001000000 "CR" - attribute \enum_value_00010000000 "TRAP" - attribute \enum_value_00100000000 "MUL" - attribute \enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 11 \SHIFT_ROT_function_unit$3 - process $group_6 - assign \SHIFT_ROT_function_unit 11'00000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'010011 - assign \SHIFT_ROT_function_unit \SHIFT_ROT_function_unit$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'011110 - assign \SHIFT_ROT_function_unit \SHIFT_ROT_dec30_SHIFT_ROT_function_unit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'011111 - assign \SHIFT_ROT_function_unit \SHIFT_ROT_dec31_SHIFT_ROT_function_unit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'111010 - assign \SHIFT_ROT_function_unit \SHIFT_ROT_function_unit$2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'111110 - assign \SHIFT_ROT_function_unit \SHIFT_ROT_function_unit$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'010100 - assign \SHIFT_ROT_function_unit 11'00000001000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'010101 - assign \SHIFT_ROT_function_unit 11'00000001000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'010111 - assign \SHIFT_ROT_function_unit 11'00000001000 - end - sync init - end - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 7 \SHIFT_ROT_internal_op$4 - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 7 \SHIFT_ROT_internal_op$5 - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 7 \SHIFT_ROT_internal_op$6 - process $group_7 - assign \SHIFT_ROT_internal_op 7'0000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'010011 - assign \SHIFT_ROT_internal_op \SHIFT_ROT_internal_op$4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'011110 - assign \SHIFT_ROT_internal_op \SHIFT_ROT_dec30_SHIFT_ROT_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'011111 - assign \SHIFT_ROT_internal_op \SHIFT_ROT_dec31_SHIFT_ROT_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'111010 - assign \SHIFT_ROT_internal_op \SHIFT_ROT_internal_op$5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'111110 - assign \SHIFT_ROT_internal_op \SHIFT_ROT_internal_op$6 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'010100 - assign \SHIFT_ROT_internal_op 7'0111000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'010101 - assign \SHIFT_ROT_internal_op 7'0111000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'010111 - assign \SHIFT_ROT_internal_op 7'0111000 - end - sync init - end - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 4 \SHIFT_ROT_in2_sel$7 - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 4 \SHIFT_ROT_in2_sel$8 - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 4 \SHIFT_ROT_in2_sel$9 - process $group_8 - assign \SHIFT_ROT_in2_sel 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'010011 - assign \SHIFT_ROT_in2_sel \SHIFT_ROT_in2_sel$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'011110 - assign \SHIFT_ROT_in2_sel \SHIFT_ROT_dec30_SHIFT_ROT_in2_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'011111 - assign \SHIFT_ROT_in2_sel \SHIFT_ROT_dec31_SHIFT_ROT_in2_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'111010 - assign \SHIFT_ROT_in2_sel \SHIFT_ROT_in2_sel$8 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'111110 - assign \SHIFT_ROT_in2_sel \SHIFT_ROT_in2_sel$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'010100 - assign \SHIFT_ROT_in2_sel 4'1011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'010101 - assign \SHIFT_ROT_in2_sel 4'1011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'010111 - assign \SHIFT_ROT_in2_sel 4'0001 - end - sync init - end - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \SHIFT_ROT_cr_in$10 - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \SHIFT_ROT_cr_in$11 - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \SHIFT_ROT_cr_in$12 - process $group_9 - assign \SHIFT_ROT_cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'010011 - assign \SHIFT_ROT_cr_in \SHIFT_ROT_cr_in$10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'011110 - assign \SHIFT_ROT_cr_in \SHIFT_ROT_dec30_SHIFT_ROT_cr_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'011111 - assign \SHIFT_ROT_cr_in \SHIFT_ROT_dec31_SHIFT_ROT_cr_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'111010 - assign \SHIFT_ROT_cr_in \SHIFT_ROT_cr_in$11 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'111110 - assign \SHIFT_ROT_cr_in \SHIFT_ROT_cr_in$12 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'010100 - assign \SHIFT_ROT_cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'010101 - assign \SHIFT_ROT_cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'010111 - assign \SHIFT_ROT_cr_in 3'000 - end - sync init - end - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \SHIFT_ROT_cr_out$13 - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \SHIFT_ROT_cr_out$14 - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \SHIFT_ROT_cr_out$15 - process $group_10 - assign \SHIFT_ROT_cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'010011 - assign \SHIFT_ROT_cr_out \SHIFT_ROT_cr_out$13 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'011110 - assign \SHIFT_ROT_cr_out \SHIFT_ROT_dec30_SHIFT_ROT_cr_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'011111 - assign \SHIFT_ROT_cr_out \SHIFT_ROT_dec31_SHIFT_ROT_cr_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'111010 - assign \SHIFT_ROT_cr_out \SHIFT_ROT_cr_out$14 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'111110 - assign \SHIFT_ROT_cr_out \SHIFT_ROT_cr_out$15 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'010100 - assign \SHIFT_ROT_cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'010101 - assign \SHIFT_ROT_cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'010111 - assign \SHIFT_ROT_cr_out 3'000 - end - sync init - end - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 2 \SHIFT_ROT_rc_sel$16 - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 2 \SHIFT_ROT_rc_sel$17 - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 2 \SHIFT_ROT_rc_sel$18 - process $group_11 - assign \SHIFT_ROT_rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'010011 - assign \SHIFT_ROT_rc_sel \SHIFT_ROT_rc_sel$16 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'011110 - assign \SHIFT_ROT_rc_sel \SHIFT_ROT_dec30_SHIFT_ROT_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'011111 - assign \SHIFT_ROT_rc_sel \SHIFT_ROT_dec31_SHIFT_ROT_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'111010 - assign \SHIFT_ROT_rc_sel \SHIFT_ROT_rc_sel$17 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'111110 - assign \SHIFT_ROT_rc_sel \SHIFT_ROT_rc_sel$18 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'010100 - assign \SHIFT_ROT_rc_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'010101 - assign \SHIFT_ROT_rc_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'010111 - assign \SHIFT_ROT_rc_sel 2'10 - end - sync init - end - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 2 \SHIFT_ROT_cry_in$19 - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 2 \SHIFT_ROT_cry_in$20 - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 2 \SHIFT_ROT_cry_in$21 - process $group_12 - assign \SHIFT_ROT_cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'010011 - assign \SHIFT_ROT_cry_in \SHIFT_ROT_cry_in$19 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'011110 - assign \SHIFT_ROT_cry_in \SHIFT_ROT_dec30_SHIFT_ROT_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'011111 - assign \SHIFT_ROT_cry_in \SHIFT_ROT_dec31_SHIFT_ROT_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'111010 - assign \SHIFT_ROT_cry_in \SHIFT_ROT_cry_in$20 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'111110 - assign \SHIFT_ROT_cry_in \SHIFT_ROT_cry_in$21 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'010100 - assign \SHIFT_ROT_cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'010101 - assign \SHIFT_ROT_cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'010111 - assign \SHIFT_ROT_cry_in 2'00 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \SHIFT_ROT_cry_out$22 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \SHIFT_ROT_cry_out$23 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \SHIFT_ROT_cry_out$24 - process $group_13 - assign \SHIFT_ROT_cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'010011 - assign \SHIFT_ROT_cry_out \SHIFT_ROT_cry_out$22 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'011110 - assign \SHIFT_ROT_cry_out \SHIFT_ROT_dec30_SHIFT_ROT_cry_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'011111 - assign \SHIFT_ROT_cry_out \SHIFT_ROT_dec31_SHIFT_ROT_cry_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'111010 - assign \SHIFT_ROT_cry_out \SHIFT_ROT_cry_out$23 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'111110 - assign \SHIFT_ROT_cry_out \SHIFT_ROT_cry_out$24 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'010100 - assign \SHIFT_ROT_cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'010101 - assign \SHIFT_ROT_cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'010111 - assign \SHIFT_ROT_cry_out 1'0 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \SHIFT_ROT_is_32b$25 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \SHIFT_ROT_is_32b$26 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \SHIFT_ROT_is_32b$27 - process $group_14 - assign \SHIFT_ROT_is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'010011 - assign \SHIFT_ROT_is_32b \SHIFT_ROT_is_32b$25 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'011110 - assign \SHIFT_ROT_is_32b \SHIFT_ROT_dec30_SHIFT_ROT_is_32b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'011111 - assign \SHIFT_ROT_is_32b \SHIFT_ROT_dec31_SHIFT_ROT_is_32b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'111010 - assign \SHIFT_ROT_is_32b \SHIFT_ROT_is_32b$26 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'111110 - assign \SHIFT_ROT_is_32b \SHIFT_ROT_is_32b$27 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'010100 - assign \SHIFT_ROT_is_32b 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'010101 - assign \SHIFT_ROT_is_32b 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'010111 - assign \SHIFT_ROT_is_32b 1'1 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \SHIFT_ROT_sgn$28 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \SHIFT_ROT_sgn$29 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \SHIFT_ROT_sgn$30 - process $group_15 - assign \SHIFT_ROT_sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'010011 - assign \SHIFT_ROT_sgn \SHIFT_ROT_sgn$28 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'011110 - assign \SHIFT_ROT_sgn \SHIFT_ROT_dec30_SHIFT_ROT_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'011111 - assign \SHIFT_ROT_sgn \SHIFT_ROT_dec31_SHIFT_ROT_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'111010 - assign \SHIFT_ROT_sgn \SHIFT_ROT_sgn$29 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'111110 - assign \SHIFT_ROT_sgn \SHIFT_ROT_sgn$30 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'010100 - assign \SHIFT_ROT_sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'010101 - assign \SHIFT_ROT_sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'010111 - assign \SHIFT_ROT_sgn 1'0 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:308" - wire width 32 \opcode_switch$31 - process $group_16 - assign \opcode_switch$31 32'00000000000000000000000000000000 - assign \opcode_switch$31 \opcode_in - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:418" - wire width 32 $32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:418" - cell $mux $33 - parameter \WIDTH 32 - connect \A \raw_opcode_in - connect \B { \raw_opcode_in [7:0] \raw_opcode_in [15:8] \raw_opcode_in [23:16] \raw_opcode_in [31:24] } - connect \S \bigendian - connect \Y $32 - end - process $group_17 - assign \opcode_in 32'00000000000000000000000000000000 - assign \opcode_in $32 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 5 \SHIFT_ROT_RS - process $group_18 - assign \SHIFT_ROT_RS 5'00000 - assign \SHIFT_ROT_RS { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 5 \SHIFT_ROT_RT - process $group_19 - assign \SHIFT_ROT_RT 5'00000 - assign \SHIFT_ROT_RT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 5 \SHIFT_ROT_RA - process $group_20 - assign \SHIFT_ROT_RA 5'00000 - assign \SHIFT_ROT_RA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 5 \SHIFT_ROT_RB - process $group_21 - assign \SHIFT_ROT_RB 5'00000 - assign \SHIFT_ROT_RB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - process $group_22 - assign \SHIFT_ROT_SI 16'0000000000000000 - assign \SHIFT_ROT_SI { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] \opcode_in [0] } - sync init - end - process $group_23 - assign \SHIFT_ROT_UI 16'0000000000000000 - assign \SHIFT_ROT_UI { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] \opcode_in [0] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 1 \SHIFT_ROT_L - process $group_24 - assign \SHIFT_ROT_L 1'0 - assign \SHIFT_ROT_L { \opcode_in [21] } - sync init - end - process $group_25 - assign \SHIFT_ROT_SH32 5'00000 - assign \SHIFT_ROT_SH32 { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - process $group_26 - assign \SHIFT_ROT_sh 6'000000 - assign \SHIFT_ROT_sh { \opcode_in [1] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 5 \SHIFT_ROT_MB32 - process $group_27 - assign \SHIFT_ROT_MB32 5'00000 - assign \SHIFT_ROT_MB32 { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 5 \SHIFT_ROT_ME32 - process $group_28 - assign \SHIFT_ROT_ME32 5'00000 - assign \SHIFT_ROT_ME32 { \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] } - sync init - end - process $group_29 - assign \SHIFT_ROT_LI 24'000000000000000000000000 - assign \SHIFT_ROT_LI { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 1 \SHIFT_ROT_LK - process $group_30 - assign \SHIFT_ROT_LK 1'0 - assign \SHIFT_ROT_LK { \opcode_in [0] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 1 \SHIFT_ROT_AA - process $group_31 - assign \SHIFT_ROT_AA 1'0 - assign \SHIFT_ROT_AA { \opcode_in [1] } - sync init - end - process $group_32 - assign \SHIFT_ROT_Rc 1'0 - assign \SHIFT_ROT_Rc { \opcode_in [0] } - sync init - end - process $group_33 - assign \SHIFT_ROT_OE 1'0 - assign \SHIFT_ROT_OE { \opcode_in [10] } - sync init - end - process $group_34 - assign \SHIFT_ROT_BD 14'00000000000000 - assign \SHIFT_ROT_BD { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 3 \SHIFT_ROT_BF - process $group_35 - assign \SHIFT_ROT_BF 3'000 - assign \SHIFT_ROT_BF { \opcode_in [25] \opcode_in [24] \opcode_in [23] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 10 \SHIFT_ROT_CR - process $group_36 - assign \SHIFT_ROT_CR 10'0000000000 - assign \SHIFT_ROT_CR { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] } - sync init - end - process $group_37 - assign \SHIFT_ROT_BB 5'00000 - assign \SHIFT_ROT_BB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - process $group_38 - assign \SHIFT_ROT_BA 5'00000 - assign \SHIFT_ROT_BA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - process $group_39 - assign \SHIFT_ROT_BT 5'00000 - assign \SHIFT_ROT_BT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - process $group_40 - assign \SHIFT_ROT_FXM 8'00000000 - assign \SHIFT_ROT_FXM { \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 5 \SHIFT_ROT_BO - process $group_41 - assign \SHIFT_ROT_BO 5'00000 - assign \SHIFT_ROT_BO { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - process $group_42 - assign \SHIFT_ROT_BI 5'00000 - assign \SHIFT_ROT_BI { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 2 \SHIFT_ROT_BH - process $group_43 - assign \SHIFT_ROT_BH 2'00 - assign \SHIFT_ROT_BH { \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 16 \SHIFT_ROT_D - process $group_44 - assign \SHIFT_ROT_D 16'0000000000000000 - assign \SHIFT_ROT_D { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] \opcode_in [0] } - sync init - end - process $group_45 - assign \SHIFT_ROT_DS 14'00000000000000 - assign \SHIFT_ROT_DS { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 5 \SHIFT_ROT_TO - process $group_46 - assign \SHIFT_ROT_TO 5'00000 - assign \SHIFT_ROT_TO { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - process $group_47 - assign \SHIFT_ROT_BC 5'00000 - assign \SHIFT_ROT_BC { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 5 \SHIFT_ROT_SH - process $group_48 - assign \SHIFT_ROT_SH 5'00000 - assign \SHIFT_ROT_SH { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 5 \SHIFT_ROT_ME - process $group_49 - assign \SHIFT_ROT_ME 5'00000 - assign \SHIFT_ROT_ME { \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 5 \SHIFT_ROT_MB - process $group_50 - assign \SHIFT_ROT_MB 5'00000 - assign \SHIFT_ROT_MB { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 10 \SHIFT_ROT_SPR - process $group_51 - assign \SHIFT_ROT_SPR 10'0000000000 - assign \SHIFT_ROT_SPR { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \X_A - process $group_52 - assign \X_A 1'0 - assign \X_A { \opcode_in [25] } - sync init - end - process $group_53 - assign \X_BF 3'000 - assign \X_BF { \opcode_in [25] \opcode_in [24] \opcode_in [23] } - sync init - end - process $group_54 - assign \X_BFA 3'000 - assign \X_BFA { \opcode_in [20] \opcode_in [19] \opcode_in [18] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \X_BO - process $group_55 - assign \X_BO 5'00000 - assign \X_BO { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 4 \X_CT - process $group_56 - assign \X_CT 4'0000 - assign \X_CT { \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 7 \X_DCMX - process $group_57 - assign \X_DCMX 7'0000000 - assign \X_DCMX { \opcode_in [22] \opcode_in [21] \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 3 \X_DRM - process $group_58 - assign \X_DRM 3'000 - assign \X_DRM { \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \X_E - process $group_59 - assign \X_E 1'0 - assign \X_E { \opcode_in [15] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 4 \X_E_1 - process $group_60 - assign \X_E_1 4'0000 - assign \X_E_1 { \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 2 \X_EO - process $group_61 - assign \X_EO 2'00 - assign \X_EO { \opcode_in [20] \opcode_in [19] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \X_EO_1 - process $group_62 - assign \X_EO_1 5'00000 - assign \X_EO_1 { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \X_EX - process $group_63 - assign \X_EX 1'0 - assign \X_EX { \opcode_in [0] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \X_FC - process $group_64 - assign \X_FC 5'00000 - assign \X_FC { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \X_FRA - process $group_65 - assign \X_FRA 5'00000 - assign \X_FRA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \X_FRAp - process $group_66 - assign \X_FRAp 5'00000 - assign \X_FRAp { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \X_FRB - process $group_67 - assign \X_FRB 5'00000 - assign \X_FRB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \X_FRBp - process $group_68 - assign \X_FRBp 5'00000 - assign \X_FRBp { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \X_FRS - process $group_69 - assign \X_FRS 5'00000 - assign \X_FRS { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \X_FRSp - process $group_70 - assign \X_FRSp 5'00000 - assign \X_FRSp { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \X_FRT - process $group_71 - assign \X_FRT 5'00000 - assign \X_FRT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \X_FRTp - process $group_72 - assign \X_FRTp 5'00000 - assign \X_FRTp { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 3 \X_IH - process $group_73 - assign \X_IH 3'000 - assign \X_IH { \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 8 \X_IMM8 - process $group_74 - assign \X_IMM8 8'00000000 - assign \X_IMM8 { \opcode_in [18] \opcode_in [17] \opcode_in [16] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 2 \X_L2 - process $group_75 - assign \X_L2 2'00 - assign \X_L2 { \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \X_L - process $group_76 - assign \X_L 1'0 - assign \X_L { \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \X_L1 - process $group_77 - assign \X_L1 1'0 - assign \X_L1 { \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 2 \X_L3 - process $group_78 - assign \X_L3 2'00 - assign \X_L3 { \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \X_MO - process $group_79 - assign \X_MO 5'00000 - assign \X_MO { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \X_NB - process $group_80 - assign \X_NB 5'00000 - assign \X_NB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \X_PRS - process $group_81 - assign \X_PRS 1'0 - assign \X_PRS { \opcode_in [17] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \X_R - process $group_82 - assign \X_R 1'0 - assign \X_R { \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \X_R_1 - process $group_83 - assign \X_R_1 1'0 - assign \X_R_1 { \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \X_RA - process $group_84 - assign \X_RA 5'00000 - assign \X_RA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \X_RB - process $group_85 - assign \X_RB 5'00000 - assign \X_RB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \X_Rc - process $group_86 - assign \X_Rc 1'0 - assign \X_Rc { \opcode_in [0] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 2 \X_RIC - process $group_87 - assign \X_RIC 2'00 - assign \X_RIC { \opcode_in [19] \opcode_in [18] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 2 \X_RM - process $group_88 - assign \X_RM 2'00 - assign \X_RM { \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \X_RO - process $group_89 - assign \X_RO 1'0 - assign \X_RO { \opcode_in [0] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \X_RS - process $group_90 - assign \X_RS 5'00000 - assign \X_RS { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \X_RSp - process $group_91 - assign \X_RSp 5'00000 - assign \X_RSp { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \X_RT - process $group_92 - assign \X_RT 5'00000 - assign \X_RT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \X_RTp - process $group_93 - assign \X_RTp 5'00000 - assign \X_RTp { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \X_S - process $group_94 - assign \X_S 5'00000 - assign \X_S { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \X_SH - process $group_95 - assign \X_SH 5'00000 - assign \X_SH { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \X_SI - process $group_96 - assign \X_SI 5'00000 - assign \X_SI { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 2 \X_SP - process $group_97 - assign \X_SP 2'00 - assign \X_SP { \opcode_in [20] \opcode_in [19] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 4 \X_SR - process $group_98 - assign \X_SR 4'0000 - assign \X_SR { \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \X_SX - process $group_99 - assign \X_SX 1'0 - assign \X_SX { \opcode_in [0] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 6 \X_SX_S - process $group_100 - assign \X_SX_S 6'000000 - assign \X_SX_S { \opcode_in [0] \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \X_T - process $group_101 - assign \X_T 5'00000 - assign \X_T { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 10 \X_TBR - process $group_102 - assign \X_TBR 10'0000000000 - assign \X_TBR { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \X_TH - process $group_103 - assign \X_TH 5'00000 - assign \X_TH { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \X_TO - process $group_104 - assign \X_TO 5'00000 - assign \X_TO { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \X_TX - process $group_105 - assign \X_TX 1'0 - assign \X_TX { \opcode_in [0] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 6 \X_TX_T - process $group_106 - assign \X_TX_T 6'000000 - assign \X_TX_T { \opcode_in [0] \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 4 \X_U - process $group_107 - assign \X_U 4'0000 - assign \X_U { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \X_UIM - process $group_108 - assign \X_UIM 5'00000 - assign \X_UIM { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \X_VRS - process $group_109 - assign \X_VRS 5'00000 - assign \X_VRS { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \X_VRT - process $group_110 - assign \X_VRT 5'00000 - assign \X_VRT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \X_W - process $group_111 - assign \X_W 1'0 - assign \X_W { \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 2 \X_WC - process $group_112 - assign \X_WC 2'00 - assign \X_WC { \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 10 \X_XO - process $group_113 - assign \X_XO 10'0000000000 - assign \X_XO { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 8 \X_XO_1 - process $group_114 - assign \X_XO_1 8'00000000 - assign \X_XO_1 { \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \B_AA - process $group_115 - assign \B_AA 1'0 - assign \B_AA { \opcode_in [1] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 14 \B_BD - process $group_116 - assign \B_BD 14'00000000000000 - assign \B_BD { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \B_BI - process $group_117 - assign \B_BI 5'00000 - assign \B_BI { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \B_BO - process $group_118 - assign \B_BO 5'00000 - assign \B_BO { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \B_LK - process $group_119 - assign \B_LK 1'0 - assign \B_LK { \opcode_in [0] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \I_AA - process $group_120 - assign \I_AA 1'0 - assign \I_AA { \opcode_in [1] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 24 \I_LI - process $group_121 - assign \I_LI 24'000000000000000000000000 - assign \I_LI { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \I_LK - process $group_122 - assign \I_LK 1'0 - assign \I_LK { \opcode_in [0] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \XX3_AX - process $group_123 - assign \XX3_AX 1'0 - assign \XX3_AX { \opcode_in [2] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \XX3_A - process $group_124 - assign \XX3_A 5'00000 - assign \XX3_A { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 6 \XX3_AX_A - process $group_125 - assign \XX3_AX_A 6'000000 - assign \XX3_AX_A { \opcode_in [2] \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 3 \XX3_BF - process $group_126 - assign \XX3_BF 3'000 - assign \XX3_BF { \opcode_in [25] \opcode_in [24] \opcode_in [23] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \XX3_BX - process $group_127 - assign \XX3_BX 1'0 - assign \XX3_BX { \opcode_in [1] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \XX3_B - process $group_128 - assign \XX3_B 5'00000 - assign \XX3_B { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 6 \XX3_BX_B - process $group_129 - assign \XX3_BX_B 6'000000 - assign \XX3_BX_B { \opcode_in [1] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 2 \XX3_DM - process $group_130 - assign \XX3_DM 2'00 - assign \XX3_DM { \opcode_in [9] \opcode_in [8] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \XX3_Rc - process $group_131 - assign \XX3_Rc 1'0 - assign \XX3_Rc { \opcode_in [10] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 2 \XX3_SHW - process $group_132 - assign \XX3_SHW 2'00 - assign \XX3_SHW { \opcode_in [9] \opcode_in [8] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \XX3_TX - process $group_133 - assign \XX3_TX 1'0 - assign \XX3_TX { \opcode_in [0] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \XX3_T - process $group_134 - assign \XX3_T 5'00000 - assign \XX3_T { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 6 \XX3_TX_T - process $group_135 - assign \XX3_TX_T 6'000000 - assign \XX3_TX_T { \opcode_in [0] \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 4 \XX3_XO - process $group_136 - assign \XX3_XO 4'0000 - assign \XX3_XO { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 8 \XX3_XO_1 - process $group_137 - assign \XX3_XO_1 8'00000000 - assign \XX3_XO_1 { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 9 \XX3_XO_2 - process $group_138 - assign \XX3_XO_2 9'000000000 - assign \XX3_XO_2 { \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \XX4_AX - process $group_139 - assign \XX4_AX 1'0 - assign \XX4_AX { \opcode_in [2] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \XX4_A - process $group_140 - assign \XX4_A 5'00000 - assign \XX4_A { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 6 \XX4_AX_A - process $group_141 - assign \XX4_AX_A 6'000000 - assign \XX4_AX_A { \opcode_in [2] \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \XX4_BX - process $group_142 - assign \XX4_BX 1'0 - assign \XX4_BX { \opcode_in [1] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \XX4_B - process $group_143 - assign \XX4_B 5'00000 - assign \XX4_B { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 6 \XX4_BX_B - process $group_144 - assign \XX4_BX_B 6'000000 - assign \XX4_BX_B { \opcode_in [1] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \XX4_CX - process $group_145 - assign \XX4_CX 1'0 - assign \XX4_CX { \opcode_in [3] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \XX4_C - process $group_146 - assign \XX4_C 5'00000 - assign \XX4_C { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 6 \XX4_CX_C - process $group_147 - assign \XX4_CX_C 6'000000 - assign \XX4_CX_C { \opcode_in [3] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \XX4_TX - process $group_148 - assign \XX4_TX 1'0 - assign \XX4_TX { \opcode_in [0] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \XX4_T - process $group_149 - assign \XX4_T 5'00000 - assign \XX4_T { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 6 \XX4_TX_T - process $group_150 - assign \XX4_TX_T 6'000000 - assign \XX4_TX_T { \opcode_in [0] \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 2 \XX4_XO - process $group_151 - assign \XX4_XO 2'00 - assign \XX4_XO { \opcode_in [5] \opcode_in [4] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \XL_BA - process $group_152 - assign \XL_BA 5'00000 - assign \XL_BA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \XL_BB - process $group_153 - assign \XL_BB 5'00000 - assign \XL_BB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 3 \XL_BF - process $group_154 - assign \XL_BF 3'000 - assign \XL_BF { \opcode_in [25] \opcode_in [24] \opcode_in [23] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 3 \XL_BFA - process $group_155 - assign \XL_BFA 3'000 - assign \XL_BFA { \opcode_in [20] \opcode_in [19] \opcode_in [18] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 2 \XL_BH - process $group_156 - assign \XL_BH 2'00 - assign \XL_BH { \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \XL_BI - process $group_157 - assign \XL_BI 5'00000 - assign \XL_BI { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \XL_BO - process $group_158 - assign \XL_BO 5'00000 - assign \XL_BO { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \XL_BO_1 - process $group_159 - assign \XL_BO_1 5'00000 - assign \XL_BO_1 { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - process $group_160 - assign \XL_BT 5'00000 - assign \XL_BT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \XL_LK - process $group_161 - assign \XL_LK 1'0 - assign \XL_LK { \opcode_in [0] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 15 \XL_OC - process $group_162 - assign \XL_OC 15'000000000000000 - assign \XL_OC { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \XL_S - process $group_163 - assign \XL_S 1'0 - assign \XL_S { \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 10 \XL_XO - process $group_164 - assign \XL_XO 10'0000000000 - assign \XL_XO { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \A_BC - process $group_165 - assign \A_BC 5'00000 - assign \A_BC { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \A_FRA - process $group_166 - assign \A_FRA 5'00000 - assign \A_FRA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \A_FRB - process $group_167 - assign \A_FRB 5'00000 - assign \A_FRB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \A_FRC - process $group_168 - assign \A_FRC 5'00000 - assign \A_FRC { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \A_FRT - process $group_169 - assign \A_FRT 5'00000 - assign \A_FRT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \A_RA - process $group_170 - assign \A_RA 5'00000 - assign \A_RA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \A_RB - process $group_171 - assign \A_RB 5'00000 - assign \A_RB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \A_Rc - process $group_172 - assign \A_Rc 1'0 - assign \A_Rc { \opcode_in [0] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \A_RT - process $group_173 - assign \A_RT 5'00000 - assign \A_RT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \A_XO - process $group_174 - assign \A_XO 5'00000 - assign \A_XO { \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 3 \D_BF - process $group_175 - assign \D_BF 3'000 - assign \D_BF { \opcode_in [25] \opcode_in [24] \opcode_in [23] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 16 \D_D - process $group_176 - assign \D_D 16'0000000000000000 - assign \D_D { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] \opcode_in [0] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \D_FRS - process $group_177 - assign \D_FRS 5'00000 - assign \D_FRS { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \D_FRT - process $group_178 - assign \D_FRT 5'00000 - assign \D_FRT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \D_L - process $group_179 - assign \D_L 1'0 - assign \D_L { \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \D_RA - process $group_180 - assign \D_RA 5'00000 - assign \D_RA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \D_RS - process $group_181 - assign \D_RS 5'00000 - assign \D_RS { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \D_RT - process $group_182 - assign \D_RT 5'00000 - assign \D_RT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 16 \D_SI - process $group_183 - assign \D_SI 16'0000000000000000 - assign \D_SI { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] \opcode_in [0] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \D_TO - process $group_184 - assign \D_TO 5'00000 - assign \D_TO { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 16 \D_UI - process $group_185 - assign \D_UI 16'0000000000000000 - assign \D_UI { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] \opcode_in [0] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 3 \XX2_BF - process $group_186 - assign \XX2_BF 3'000 - assign \XX2_BF { \opcode_in [25] \opcode_in [24] \opcode_in [23] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \XX2_BX - process $group_187 - assign \XX2_BX 1'0 - assign \XX2_BX { \opcode_in [1] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \XX2_B - process $group_188 - assign \XX2_B 5'00000 - assign \XX2_B { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 6 \XX2_BX_B - process $group_189 - assign \XX2_BX_B 6'000000 - assign \XX2_BX_B { \opcode_in [1] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \XX2_dc - process $group_190 - assign \XX2_dc 1'0 - assign \XX2_dc { \opcode_in [6] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \XX2_dm - process $group_191 - assign \XX2_dm 1'0 - assign \XX2_dm { \opcode_in [2] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \XX2_dx - process $group_192 - assign \XX2_dx 5'00000 - assign \XX2_dx { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 7 \XX2_dc_dm_dx - process $group_193 - assign \XX2_dc_dm_dx 7'0000000 - assign \XX2_dc_dm_dx { \opcode_in [6] \opcode_in [2] \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 7 \XX2_DCMX - process $group_194 - assign \XX2_DCMX 7'0000000 - assign \XX2_DCMX { \opcode_in [22] \opcode_in [21] \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \XX2_EO - process $group_195 - assign \XX2_EO 5'00000 - assign \XX2_EO { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \XX2_RT - process $group_196 - assign \XX2_RT 5'00000 - assign \XX2_RT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \XX2_TX - process $group_197 - assign \XX2_TX 1'0 - assign \XX2_TX { \opcode_in [0] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \XX2_T - process $group_198 - assign \XX2_T 5'00000 - assign \XX2_T { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 6 \XX2_TX_T - process $group_199 - assign \XX2_TX_T 6'000000 - assign \XX2_TX_T { \opcode_in [0] \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 4 \XX2_UIM - process $group_200 - assign \XX2_UIM 4'0000 - assign \XX2_UIM { \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 2 \XX2_UIM_1 - process $group_201 - assign \XX2_UIM_1 2'00 - assign \XX2_UIM_1 { \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 7 \XX2_XO - process $group_202 - assign \XX2_XO 7'0000000 - assign \XX2_XO { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [5] \opcode_in [4] \opcode_in [3] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 9 \XX2_XO_1 - process $group_203 - assign \XX2_XO_1 9'000000000 - assign \XX2_XO_1 { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 3 \Z22_BF - process $group_204 - assign \Z22_BF 3'000 - assign \Z22_BF { \opcode_in [25] \opcode_in [24] \opcode_in [23] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 6 \Z22_DCM - process $group_205 - assign \Z22_DCM 6'000000 - assign \Z22_DCM { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 6 \Z22_DGM - process $group_206 - assign \Z22_DGM 6'000000 - assign \Z22_DGM { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \Z22_FRA - process $group_207 - assign \Z22_FRA 5'00000 - assign \Z22_FRA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \Z22_FRAp - process $group_208 - assign \Z22_FRAp 5'00000 - assign \Z22_FRAp { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \Z22_FRT - process $group_209 - assign \Z22_FRT 5'00000 - assign \Z22_FRT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \Z22_FRTp - process $group_210 - assign \Z22_FRTp 5'00000 - assign \Z22_FRTp { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \Z22_Rc - process $group_211 - assign \Z22_Rc 1'0 - assign \Z22_Rc { \opcode_in [0] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 6 \Z22_SH - process $group_212 - assign \Z22_SH 6'000000 - assign \Z22_SH { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 9 \Z22_XO - process $group_213 - assign \Z22_XO 9'000000000 - assign \Z22_XO { \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 3 \EVS_BFA - process $group_214 - assign \EVS_BFA 3'000 - assign \EVS_BFA { \opcode_in [2] \opcode_in [1] \opcode_in [0] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 10 \XFX_BHRBE - process $group_215 - assign \XFX_BHRBE 10'0000000000 - assign \XFX_BHRBE { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \XFX_DUI - process $group_216 - assign \XFX_DUI 5'00000 - assign \XFX_DUI { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 10 \XFX_DUIS - process $group_217 - assign \XFX_DUIS 10'0000000000 - assign \XFX_DUIS { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 8 \XFX_FXM - process $group_218 - assign \XFX_FXM 8'00000000 - assign \XFX_FXM { \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \XFX_RS - process $group_219 - assign \XFX_RS 5'00000 - assign \XFX_RS { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \XFX_RT - process $group_220 - assign \XFX_RT 5'00000 - assign \XFX_RT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 10 \XFX_SPR - process $group_221 - assign \XFX_SPR 10'0000000000 - assign \XFX_SPR { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 10 \XFX_XO - process $group_222 - assign \XFX_XO 10'0000000000 - assign \XFX_XO { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 10 \DX_d0 - process $group_223 - assign \DX_d0 10'0000000000 - assign \DX_d0 { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \DX_d1 - process $group_224 - assign \DX_d1 5'00000 - assign \DX_d1 { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \DX_d2 - process $group_225 - assign \DX_d2 1'0 - assign \DX_d2 { \opcode_in [0] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 16 \DX_d0_d1_d2 - process $group_226 - assign \DX_d0_d1_d2 16'0000000000000000 - assign \DX_d0_d1_d2 { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] \opcode_in [0] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \DX_RT - process $group_227 - assign \DX_RT 5'00000 - assign \DX_RT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \DX_XO - process $group_228 - assign \DX_XO 5'00000 - assign \DX_XO { \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 12 \DQ_DQ - process $group_229 - assign \DQ_DQ 12'000000000000 - assign \DQ_DQ { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 4 \DQ_PT - process $group_230 - assign \DQ_PT 4'0000 - assign \DQ_PT { \opcode_in [3] \opcode_in [2] \opcode_in [1] \opcode_in [0] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \DQ_RA - process $group_231 - assign \DQ_RA 5'00000 - assign \DQ_RA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \DQ_RTp - process $group_232 - assign \DQ_RTp 5'00000 - assign \DQ_RTp { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \DQ_SX - process $group_233 - assign \DQ_SX 1'0 - assign \DQ_SX { \opcode_in [3] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \DQ_S - process $group_234 - assign \DQ_S 5'00000 - assign \DQ_S { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 6 \DQ_SX_S - process $group_235 - assign \DQ_SX_S 6'000000 - assign \DQ_SX_S { \opcode_in [3] \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \DQ_TX - process $group_236 - assign \DQ_TX 1'0 - assign \DQ_TX { \opcode_in [3] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \DQ_T - process $group_237 - assign \DQ_T 5'00000 - assign \DQ_T { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 6 \DQ_TX_T - process $group_238 - assign \DQ_TX_T 6'000000 - assign \DQ_TX_T { \opcode_in [3] \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 3 \DQ_XO - process $group_239 - assign \DQ_XO 3'000 - assign \DQ_XO { \opcode_in [2] \opcode_in [1] \opcode_in [0] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 14 \DS_DS - process $group_240 - assign \DS_DS 14'00000000000000 - assign \DS_DS { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \DS_FRSp - process $group_241 - assign \DS_FRSp 5'00000 - assign \DS_FRSp { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \DS_FRTp - process $group_242 - assign \DS_FRTp 5'00000 - assign \DS_FRTp { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \DS_RA - process $group_243 - assign \DS_RA 5'00000 - assign \DS_RA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \DS_RS - process $group_244 - assign \DS_RS 5'00000 - assign \DS_RS { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \DS_RSp - process $group_245 - assign \DS_RSp 5'00000 - assign \DS_RSp { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \DS_RT - process $group_246 - assign \DS_RT 5'00000 - assign \DS_RT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \DS_VRS - process $group_247 - assign \DS_VRS 5'00000 - assign \DS_VRS { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \DS_VRT - process $group_248 - assign \DS_VRT 5'00000 - assign \DS_VRT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 2 \DS_XO - process $group_249 - assign \DS_XO 2'00 - assign \DS_XO { \opcode_in [1] \opcode_in [0] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \VX_EO - process $group_250 - assign \VX_EO 5'00000 - assign \VX_EO { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \VX_PS - process $group_251 - assign \VX_PS 1'0 - assign \VX_PS { \opcode_in [9] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \VX_RA - process $group_252 - assign \VX_RA 5'00000 - assign \VX_RA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \VX_RT - process $group_253 - assign \VX_RT 5'00000 - assign \VX_RT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \VX_SIM - process $group_254 - assign \VX_SIM 5'00000 - assign \VX_SIM { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \VX_UIM - process $group_255 - assign \VX_UIM 5'00000 - assign \VX_UIM { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 4 \VX_UIM_1 - process $group_256 - assign \VX_UIM_1 4'0000 - assign \VX_UIM_1 { \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 3 \VX_UIM_2 - process $group_257 - assign \VX_UIM_2 3'000 - assign \VX_UIM_2 { \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 2 \VX_UIM_3 - process $group_258 - assign \VX_UIM_3 2'00 - assign \VX_UIM_3 { \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \VX_VRA - process $group_259 - assign \VX_VRA 5'00000 - assign \VX_VRA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \VX_VRB - process $group_260 - assign \VX_VRB 5'00000 - assign \VX_VRB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \VX_VRT - process $group_261 - assign \VX_VRT 5'00000 - assign \VX_VRT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 10 \VX_XO - process $group_262 - assign \VX_XO 10'0000000000 - assign \VX_XO { \opcode_in [10] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] \opcode_in [0] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 11 \VX_XO_1 - process $group_263 - assign \VX_XO_1 11'00000000000 - assign \VX_XO_1 { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] \opcode_in [0] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 8 \XFL_FLM - process $group_264 - assign \XFL_FLM 8'00000000 - assign \XFL_FLM { \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \XFL_FRB - process $group_265 - assign \XFL_FRB 5'00000 - assign \XFL_FRB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \XFL_L - process $group_266 - assign \XFL_L 1'0 - assign \XFL_L { \opcode_in [25] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \XFL_Rc - process $group_267 - assign \XFL_Rc 1'0 - assign \XFL_Rc { \opcode_in [0] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \XFL_W - process $group_268 - assign \XFL_W 1'0 - assign \XFL_W { \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 10 \XFL_XO - process $group_269 - assign \XFL_XO 10'0000000000 - assign \XFL_XO { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \Z23_FRA - process $group_270 - assign \Z23_FRA 5'00000 - assign \Z23_FRA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \Z23_FRAp - process $group_271 - assign \Z23_FRAp 5'00000 - assign \Z23_FRAp { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \Z23_FRB - process $group_272 - assign \Z23_FRB 5'00000 - assign \Z23_FRB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \Z23_FRBp - process $group_273 - assign \Z23_FRBp 5'00000 - assign \Z23_FRBp { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \Z23_FRT - process $group_274 - assign \Z23_FRT 5'00000 - assign \Z23_FRT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \Z23_FRTp - process $group_275 - assign \Z23_FRTp 5'00000 - assign \Z23_FRTp { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \Z23_R - process $group_276 - assign \Z23_R 1'0 - assign \Z23_R { \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \Z23_Rc - process $group_277 - assign \Z23_Rc 1'0 - assign \Z23_Rc { \opcode_in [0] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 2 \Z23_RMC - process $group_278 - assign \Z23_RMC 2'00 - assign \Z23_RMC { \opcode_in [10] \opcode_in [9] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \Z23_TE - process $group_279 - assign \Z23_TE 5'00000 - assign \Z23_TE { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 8 \Z23_XO - process $group_280 - assign \Z23_XO 8'00000000 - assign \Z23_XO { \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \MDS_IB - process $group_281 - assign \MDS_IB 5'00000 - assign \MDS_IB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \MDS_IS - process $group_282 - assign \MDS_IS 5'00000 - assign \MDS_IS { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 6 \MDS_mb - process $group_283 - assign \MDS_mb 6'000000 - assign \MDS_mb { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 6 \MDS_me - process $group_284 - assign \MDS_me 6'000000 - assign \MDS_me { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \MDS_RA - process $group_285 - assign \MDS_RA 5'00000 - assign \MDS_RA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \MDS_RB - process $group_286 - assign \MDS_RB 5'00000 - assign \MDS_RB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \MDS_Rc - process $group_287 - assign \MDS_Rc 1'0 - assign \MDS_Rc { \opcode_in [0] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \MDS_RS - process $group_288 - assign \MDS_RS 5'00000 - assign \MDS_RS { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 4 \MDS_XBI - process $group_289 - assign \MDS_XBI 4'0000 - assign \MDS_XBI { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 4 \MDS_XBI_1 - process $group_290 - assign \MDS_XBI_1 4'0000 - assign \MDS_XBI_1 { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 4 \MDS_XO - process $group_291 - assign \MDS_XO 4'0000 - assign \MDS_XO { \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 7 \SC_LEV - process $group_292 - assign \SC_LEV 7'0000000 - assign \SC_LEV { \opcode_in [11] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \SC_XO - process $group_293 - assign \SC_XO 1'0 - assign \SC_XO { \opcode_in [1] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 2 \SC_XO_1 - process $group_294 - assign \SC_XO_1 2'00 - assign \SC_XO_1 { \opcode_in [1] \opcode_in [0] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \M_MB - process $group_295 - assign \M_MB 5'00000 - assign \M_MB { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \M_ME - process $group_296 - assign \M_ME 5'00000 - assign \M_ME { \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \M_RA - process $group_297 - assign \M_RA 5'00000 - assign \M_RA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \M_RB - process $group_298 - assign \M_RB 5'00000 - assign \M_RB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \M_Rc - process $group_299 - assign \M_Rc 1'0 - assign \M_Rc { \opcode_in [0] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \M_RS - process $group_300 - assign \M_RS 5'00000 - assign \M_RS { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \M_SH - process $group_301 - assign \M_SH 5'00000 - assign \M_SH { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 6 \MD_mb - process $group_302 - assign \MD_mb 6'000000 - assign \MD_mb { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 6 \MD_me - process $group_303 - assign \MD_me 6'000000 - assign \MD_me { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \MD_RA - process $group_304 - assign \MD_RA 5'00000 - assign \MD_RA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \MD_Rc - process $group_305 - assign \MD_Rc 1'0 - assign \MD_Rc { \opcode_in [0] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \MD_RS - process $group_306 - assign \MD_RS 5'00000 - assign \MD_RS { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 6 \MD_sh - process $group_307 - assign \MD_sh 6'000000 - assign \MD_sh { \opcode_in [1] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 3 \MD_XO - process $group_308 - assign \MD_XO 3'000 - assign \MD_XO { \opcode_in [4] \opcode_in [3] \opcode_in [2] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 6 \all_OPCD - process $group_309 - assign \all_OPCD 6'000000 - assign \all_OPCD { \opcode_in [31] \opcode_in [30] \opcode_in [29] \opcode_in [28] \opcode_in [27] \opcode_in [26] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 6 \all_PO - process $group_310 - assign \all_PO 6'000000 - assign \all_PO { \opcode_in [31] \opcode_in [30] \opcode_in [29] \opcode_in [28] \opcode_in [27] \opcode_in [26] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \XO_OE - process $group_311 - assign \XO_OE 1'0 - assign \XO_OE { \opcode_in [10] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \XO_RA - process $group_312 - assign \XO_RA 5'00000 - assign \XO_RA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \XO_RB - process $group_313 - assign \XO_RB 5'00000 - assign \XO_RB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \XO_Rc - process $group_314 - assign \XO_Rc 1'0 - assign \XO_Rc { \opcode_in [0] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \XO_RT - process $group_315 - assign \XO_RT 5'00000 - assign \XO_RT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 9 \XO_XO - process $group_316 - assign \XO_XO 9'000000000 - assign \XO_XO { \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \DQE_RA - process $group_317 - assign \DQE_RA 5'00000 - assign \DQE_RA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \DQE_RT - process $group_318 - assign \DQE_RT 5'00000 - assign \DQE_RT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 2 \DQE_XO - process $group_319 - assign \DQE_XO 2'00 - assign \DQE_XO { \opcode_in [1] \opcode_in [0] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \TX_RA - process $group_320 - assign \TX_RA 5'00000 - assign \TX_RA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \TX_UI - process $group_321 - assign \TX_UI 5'00000 - assign \TX_UI { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 4 \TX_XBI - process $group_322 - assign \TX_XBI 4'0000 - assign \TX_XBI { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 6 \TX_XO - process $group_323 - assign \TX_XO 6'000000 - assign \TX_XO { \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \VA_RA - process $group_324 - assign \VA_RA 5'00000 - assign \VA_RA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \VA_RB - process $group_325 - assign \VA_RB 5'00000 - assign \VA_RB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \VA_RC - process $group_326 - assign \VA_RC 5'00000 - assign \VA_RC { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \VA_RT - process $group_327 - assign \VA_RT 5'00000 - assign \VA_RT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 4 \VA_SHB - process $group_328 - assign \VA_SHB 4'0000 - assign \VA_SHB { \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \VA_VRA - process $group_329 - assign \VA_VRA 5'00000 - assign \VA_VRA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \VA_VRB - process $group_330 - assign \VA_VRB 5'00000 - assign \VA_VRB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \VA_VRC - process $group_331 - assign \VA_VRC 5'00000 - assign \VA_VRC { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \VA_VRT - process $group_332 - assign \VA_VRT 5'00000 - assign \VA_VRT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 6 \VA_XO - process $group_333 - assign \VA_XO 6'000000 - assign \VA_XO { \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] \opcode_in [0] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \XS_RA - process $group_334 - assign \XS_RA 5'00000 - assign \XS_RA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \XS_Rc - process $group_335 - assign \XS_Rc 1'0 - assign \XS_Rc { \opcode_in [0] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \XS_RS - process $group_336 - assign \XS_RS 5'00000 - assign \XS_RS { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 6 \XS_sh - process $group_337 - assign \XS_sh 6'000000 - assign \XS_sh { \opcode_in [1] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 9 \XS_XO - process $group_338 - assign \XS_XO 9'000000000 - assign \XS_XO { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \VC_Rc - process $group_339 - assign \VC_Rc 1'0 - assign \VC_Rc { \opcode_in [10] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \VC_VRA - process $group_340 - assign \VC_VRA 5'00000 - assign \VC_VRA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \VC_VRB - process $group_341 - assign \VC_VRB 5'00000 - assign \VC_VRB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \VC_VRT - process $group_342 - assign \VC_VRT 5'00000 - assign \VC_VRT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 10 \VC_XO - process $group_343 - assign \VC_XO 10'0000000000 - assign \VC_XO { \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] \opcode_in [0] } - sync init - end - connect \SHIFT_ROT_function_unit$1 11'00000000000 - connect \SHIFT_ROT_function_unit$2 11'00000000000 - connect \SHIFT_ROT_function_unit$3 11'00000000000 - connect \SHIFT_ROT_internal_op$4 7'0000000 - connect \SHIFT_ROT_internal_op$5 7'0000000 - connect \SHIFT_ROT_internal_op$6 7'0000000 - connect \SHIFT_ROT_in2_sel$7 4'0000 - connect \SHIFT_ROT_in2_sel$8 4'0000 - connect \SHIFT_ROT_in2_sel$9 4'0000 - connect \SHIFT_ROT_cr_in$10 3'000 - connect \SHIFT_ROT_cr_in$11 3'000 - connect \SHIFT_ROT_cr_in$12 3'000 - connect \SHIFT_ROT_cr_out$13 3'000 - connect \SHIFT_ROT_cr_out$14 3'000 - connect \SHIFT_ROT_cr_out$15 3'000 - connect \SHIFT_ROT_rc_sel$16 2'00 - connect \SHIFT_ROT_rc_sel$17 2'00 - connect \SHIFT_ROT_rc_sel$18 2'00 - connect \SHIFT_ROT_cry_in$19 2'00 - connect \SHIFT_ROT_cry_in$20 2'00 - connect \SHIFT_ROT_cry_in$21 2'00 - connect \SHIFT_ROT_cry_out$22 1'0 - connect \SHIFT_ROT_cry_out$23 1'0 - connect \SHIFT_ROT_cry_out$24 1'0 - connect \SHIFT_ROT_is_32b$25 1'0 - connect \SHIFT_ROT_is_32b$26 1'0 - connect \SHIFT_ROT_is_32b$27 1'0 - connect \SHIFT_ROT_sgn$28 1'0 - connect \SHIFT_ROT_sgn$29 1'0 - connect \SHIFT_ROT_sgn$30 1'0 -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.dec_SHIFT_ROT.dec_rc" -module \dec_rc$186 - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:404" - wire width 2 input 0 \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 1 \rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 2 \rc_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 1 input 3 \SHIFT_ROT_Rc - process $group_0 - assign \rc 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:413" - switch \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:414" - attribute \nmigen.decoding "RC/2" - case 2'10 - assign \rc \SHIFT_ROT_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:417" - attribute \nmigen.decoding "ONE/1" - case 2'01 - assign \rc 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:420" - attribute \nmigen.decoding "NONE/0" - case 2'00 - assign \rc 1'0 - end - sync init - end - process $group_1 - assign \rc_ok 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:413" - switch \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:414" - attribute \nmigen.decoding "RC/2" - case 2'10 - assign \rc_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:417" - attribute \nmigen.decoding "ONE/1" - case 2'01 - assign \rc_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:420" - attribute \nmigen.decoding "NONE/0" - case 2'00 - assign \rc_ok 1'1 - end - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.dec_SHIFT_ROT.dec_oe" -module \dec_oe$187 - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:441" - wire width 2 input 0 \sel_in - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 7 input 1 \SHIFT_ROT_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 2 \oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 3 \oe_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 1 input 4 \SHIFT_ROT_OE - process $group_0 - assign \oe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:450" - switch \SHIFT_ROT_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:461" - attribute \nmigen.decoding "OP_MUL_H64/51|OP_MUL_H32/52|OP_EXTS/31|OP_CNTZ/14|OP_SHL/60|OP_SHR/61|OP_RLC/56|OP_LOAD/37|OP_STORE/38|OP_RLCL/57|OP_RLCR/58|OP_EXTSWSLI/32" - case 7'0110011, 7'0110100, 7'0011111, 7'0001110, 7'0111100, 7'0111101, 7'0111000, 7'0100101, 7'0100110, 7'0111001, 7'0111010, 7'0100000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:465" - attribute \nmigen.decoding "" - case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:467" - switch \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:468" - attribute \nmigen.decoding "RC/2" - case 2'10 - assign \oe \SHIFT_ROT_OE - end - end - sync init - end - process $group_1 - assign \oe_ok 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:450" - switch \SHIFT_ROT_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:461" - attribute \nmigen.decoding "OP_MUL_H64/51|OP_MUL_H32/52|OP_EXTS/31|OP_CNTZ/14|OP_SHL/60|OP_SHR/61|OP_RLC/56|OP_LOAD/37|OP_STORE/38|OP_RLCL/57|OP_RLCR/58|OP_EXTSWSLI/32" - case 7'0110011, 7'0110100, 7'0011111, 7'0001110, 7'0111100, 7'0111101, 7'0111000, 7'0100101, 7'0100110, 7'0111001, 7'0111010, 7'0100000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:465" - attribute \nmigen.decoding "" - case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:467" - switch \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:468" - attribute \nmigen.decoding "RC/2" - case 2'10 - assign \oe_ok 1'1 - end - end - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.dec_SHIFT_ROT.dec_cr_in.ppick" -module \ppick$189 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" - wire width 8 input 0 \i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" - wire width 8 output 1 \o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:49" - wire width 8 \ni - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" - wire width 8 $1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" - cell $not $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \Y_WIDTH 8 - connect \A { \i [0] \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] } - connect \Y $1 - end - process $group_0 - assign \ni 8'00000000 - assign \ni $1 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire width 1 \t0 - process $group_1 - assign \t0 1'0 - assign \t0 \i [7] - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire width 1 \t1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire width 1 $3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire width 1 $4 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_bool $5 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A { \i [7] \ni [1] } - connect \Y $4 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $6 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $4 - connect \Y $3 - end - process $group_2 - assign \t1 1'0 - assign \t1 $3 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire width 1 \t2 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire width 1 $7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire width 1 $8 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_bool $9 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A { \i [6] \i [7] \ni [2] } - connect \Y $8 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $10 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $8 - connect \Y $7 - end - process $group_3 - assign \t2 1'0 - assign \t2 $7 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire width 1 \t3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire width 1 $11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire width 1 $12 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_bool $13 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A { \i [5] \i [6] \i [7] \ni [3] } - connect \Y $12 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $14 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $12 - connect \Y $11 - end - process $group_4 - assign \t3 1'0 - assign \t3 $11 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire width 1 \t4 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire width 1 $15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire width 1 $16 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_bool $17 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A { \i [4] \i [5] \i [6] \i [7] \ni [4] } - connect \Y $16 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $18 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $16 - connect \Y $15 - end - process $group_5 - assign \t4 1'0 - assign \t4 $15 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire width 1 \t5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire width 1 $19 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire width 1 $20 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_bool $21 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \Y_WIDTH 1 - connect \A { \i [3] \i [4] \i [5] \i [6] \i [7] \ni [5] } - connect \Y $20 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $22 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $20 - connect \Y $19 - end - process $group_6 - assign \t5 1'0 - assign \t5 $19 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire width 1 \t6 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire width 1 $23 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire width 1 $24 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_bool $25 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A { \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [6] } - connect \Y $24 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $26 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $24 - connect \Y $23 - end - process $group_7 - assign \t6 1'0 - assign \t6 $23 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire width 1 \t7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire width 1 $27 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire width 1 $28 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_bool $29 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A { \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [7] } - connect \Y $28 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $30 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $28 - connect \Y $27 - end - process $group_8 - assign \t7 1'0 - assign \t7 $27 - sync init - end - process $group_9 - assign \o 8'00000000 - assign \o { \t0 \t1 \t2 \t3 \t4 \t5 \t6 \t7 } - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" - wire width 1 \en_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" - wire width 1 $31 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" - cell $reduce_bool $32 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \o - connect \Y $31 - end - process $group_10 - assign \en_o 1'0 - assign \en_o $31 - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.dec_SHIFT_ROT.dec_cr_in" -module \dec_cr_in$188 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:485" - wire width 32 input 0 \insn_in - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:484" - wire width 3 input 1 \sel_in - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 7 input 2 \SHIFT_ROT_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 5 input 3 \SHIFT_ROT_BB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 5 input 4 \SHIFT_ROT_BA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 5 input 5 \SHIFT_ROT_BT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 8 input 6 \SHIFT_ROT_FXM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 5 input 7 \SHIFT_ROT_BI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 5 input 8 \SHIFT_ROT_BC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 3 input 9 \X_BFA - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" - wire width 8 \ppick_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" - wire width 8 \ppick_o - cell \ppick$189 \ppick - connect \i \ppick_i - connect \o \ppick_o - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \cr_bitfield_ok - process $group_0 - assign \cr_bitfield_ok 1'0 - assign \cr_bitfield_ok 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" - switch \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" - attribute \nmigen.decoding "NONE/0" - case 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:505" - attribute \nmigen.decoding "CR0/1" - case 3'001 - assign \cr_bitfield_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:508" - attribute \nmigen.decoding "BI/2" - case 3'010 - assign \cr_bitfield_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:511" - attribute \nmigen.decoding "BFA/3" - case 3'011 - assign \cr_bitfield_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:514" - attribute \nmigen.decoding "BA_BB/4" - case 3'100 - assign \cr_bitfield_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:521" - attribute \nmigen.decoding "BC/5" - case 3'101 - assign \cr_bitfield_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:524" - attribute \nmigen.decoding "WHOLE_REG/6" - case 3'110 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \cr_bitfield_b_ok - process $group_1 - assign \cr_bitfield_b_ok 1'0 - assign \cr_bitfield_b_ok 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" - switch \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" - attribute \nmigen.decoding "NONE/0" - case 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:505" - attribute \nmigen.decoding "CR0/1" - case 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:508" - attribute \nmigen.decoding "BI/2" - case 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:511" - attribute \nmigen.decoding "BFA/3" - case 3'011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:514" - attribute \nmigen.decoding "BA_BB/4" - case 3'100 - assign \cr_bitfield_b_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:521" - attribute \nmigen.decoding "BC/5" - case 3'101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:524" - attribute \nmigen.decoding "WHOLE_REG/6" - case 3'110 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \cr_fxm_ok - process $group_2 - assign \cr_fxm_ok 1'0 - assign \cr_fxm_ok 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" - switch \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" - attribute \nmigen.decoding "NONE/0" - case 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:505" - attribute \nmigen.decoding "CR0/1" - case 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:508" - attribute \nmigen.decoding "BI/2" - case 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:511" - attribute \nmigen.decoding "BFA/3" - case 3'011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:514" - attribute \nmigen.decoding "BA_BB/4" - case 3'100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:521" - attribute \nmigen.decoding "BC/5" - case 3'101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:524" - attribute \nmigen.decoding "WHOLE_REG/6" - case 3'110 - assign \cr_fxm_ok 1'1 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 3 \cr_bitfield - process $group_3 - assign \cr_bitfield 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" - switch \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" - attribute \nmigen.decoding "NONE/0" - case 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:505" - attribute \nmigen.decoding "CR0/1" - case 3'001 - assign \cr_bitfield 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:508" - attribute \nmigen.decoding "BI/2" - case 3'010 - assign \cr_bitfield \SHIFT_ROT_BI [4:2] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:511" - attribute \nmigen.decoding "BFA/3" - case 3'011 - assign \cr_bitfield \X_BFA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:514" - attribute \nmigen.decoding "BA_BB/4" - case 3'100 - assign \cr_bitfield \SHIFT_ROT_BA [4:2] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:521" - attribute \nmigen.decoding "BC/5" - case 3'101 - assign \cr_bitfield \SHIFT_ROT_BC [4:2] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:524" - attribute \nmigen.decoding "WHOLE_REG/6" - case 3'110 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 3 \cr_bitfield_b - process $group_4 - assign \cr_bitfield_b 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" - switch \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" - attribute \nmigen.decoding "NONE/0" - case 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:505" - attribute \nmigen.decoding "CR0/1" - case 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:508" - attribute \nmigen.decoding "BI/2" - case 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:511" - attribute \nmigen.decoding "BFA/3" - case 3'011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:514" - attribute \nmigen.decoding "BA_BB/4" - case 3'100 - assign \cr_bitfield_b \SHIFT_ROT_BB [4:2] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:521" - attribute \nmigen.decoding "BC/5" - case 3'101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:524" - attribute \nmigen.decoding "WHOLE_REG/6" - case 3'110 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 3 \cr_bitfield_o - process $group_5 - assign \cr_bitfield_o 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" - switch \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" - attribute \nmigen.decoding "NONE/0" - case 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:505" - attribute \nmigen.decoding "CR0/1" - case 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:508" - attribute \nmigen.decoding "BI/2" - case 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:511" - attribute \nmigen.decoding "BFA/3" - case 3'011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:514" - attribute \nmigen.decoding "BA_BB/4" - case 3'100 - assign \cr_bitfield_o \SHIFT_ROT_BT [4:2] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:521" - attribute \nmigen.decoding "BC/5" - case 3'101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:524" - attribute \nmigen.decoding "WHOLE_REG/6" - case 3'110 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \cr_bitfield_o_ok - process $group_6 - assign \cr_bitfield_o_ok 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" - switch \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" - attribute \nmigen.decoding "NONE/0" - case 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:505" - attribute \nmigen.decoding "CR0/1" - case 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:508" - attribute \nmigen.decoding "BI/2" - case 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:511" - attribute \nmigen.decoding "BFA/3" - case 3'011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:514" - attribute \nmigen.decoding "BA_BB/4" - case 3'100 - assign \cr_bitfield_o_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:521" - attribute \nmigen.decoding "BC/5" - case 3'101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:524" - attribute \nmigen.decoding "WHOLE_REG/6" - case 3'110 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:526" - wire width 1 \move_one - process $group_7 - assign \move_one 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" - switch \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" - attribute \nmigen.decoding "NONE/0" - case 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:505" - attribute \nmigen.decoding "CR0/1" - case 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:508" - attribute \nmigen.decoding "BI/2" - case 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:511" - attribute \nmigen.decoding "BFA/3" - case 3'011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:514" - attribute \nmigen.decoding "BA_BB/4" - case 3'100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:521" - attribute \nmigen.decoding "BC/5" - case 3'101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:524" - attribute \nmigen.decoding "WHOLE_REG/6" - case 3'110 - assign \move_one \insn_in [20] - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" - cell $eq $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A \SHIFT_ROT_internal_op - connect \B 7'0101101 - connect \Y $1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" - wire width 1 $3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" - cell $and $4 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $1 - connect \B \move_one - connect \Y $3 - end - process $group_8 - assign \ppick_i 8'00000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" - switch \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" - attribute \nmigen.decoding "NONE/0" - case 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:505" - attribute \nmigen.decoding "CR0/1" - case 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:508" - attribute \nmigen.decoding "BI/2" - case 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:511" - attribute \nmigen.decoding "BFA/3" - case 3'011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:514" - attribute \nmigen.decoding "BA_BB/4" - case 3'100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:521" - attribute \nmigen.decoding "BC/5" - case 3'101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:524" - attribute \nmigen.decoding "WHOLE_REG/6" - case 3'110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" - switch { $3 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" - case 1'1 - assign \ppick_i \SHIFT_ROT_FXM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532" - case - end - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 8 \cr_fxm - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" - wire width 1 $5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" - cell $eq $6 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A \SHIFT_ROT_internal_op - connect \B 7'0101101 - connect \Y $5 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" - wire width 1 $7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" - cell $and $8 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $5 - connect \B \move_one - connect \Y $7 - end - process $group_9 - assign \cr_fxm 8'00000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" - switch \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" - attribute \nmigen.decoding "NONE/0" - case 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:505" - attribute \nmigen.decoding "CR0/1" - case 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:508" - attribute \nmigen.decoding "BI/2" - case 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:511" - attribute \nmigen.decoding "BFA/3" - case 3'011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:514" - attribute \nmigen.decoding "BA_BB/4" - case 3'100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:521" - attribute \nmigen.decoding "BC/5" - case 3'101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:524" - attribute \nmigen.decoding "WHOLE_REG/6" - case 3'110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" - switch { $7 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" - case 1'1 - assign \cr_fxm \ppick_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532" - case - assign \cr_fxm 8'11111111 - end - end - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.dec_SHIFT_ROT.dec_cr_out.ppick" -module \ppick$191 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" - wire width 8 input 0 \i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" - wire width 1 output 1 \en_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" - wire width 8 output 2 \o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:49" - wire width 8 \ni - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" - wire width 8 $1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" - cell $not $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \Y_WIDTH 8 - connect \A { \i [0] \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] } - connect \Y $1 - end - process $group_0 - assign \ni 8'00000000 - assign \ni $1 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire width 1 \t0 - process $group_1 - assign \t0 1'0 - assign \t0 \i [7] - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire width 1 \t1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire width 1 $3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire width 1 $4 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_bool $5 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A { \i [7] \ni [1] } - connect \Y $4 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $6 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $4 - connect \Y $3 - end - process $group_2 - assign \t1 1'0 - assign \t1 $3 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire width 1 \t2 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire width 1 $7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire width 1 $8 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_bool $9 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A { \i [6] \i [7] \ni [2] } - connect \Y $8 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $10 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $8 - connect \Y $7 - end - process $group_3 - assign \t2 1'0 - assign \t2 $7 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire width 1 \t3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire width 1 $11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire width 1 $12 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_bool $13 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A { \i [5] \i [6] \i [7] \ni [3] } - connect \Y $12 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $14 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $12 - connect \Y $11 - end - process $group_4 - assign \t3 1'0 - assign \t3 $11 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire width 1 \t4 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire width 1 $15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire width 1 $16 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_bool $17 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A { \i [4] \i [5] \i [6] \i [7] \ni [4] } - connect \Y $16 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $18 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $16 - connect \Y $15 - end - process $group_5 - assign \t4 1'0 - assign \t4 $15 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire width 1 \t5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire width 1 $19 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire width 1 $20 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_bool $21 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \Y_WIDTH 1 - connect \A { \i [3] \i [4] \i [5] \i [6] \i [7] \ni [5] } - connect \Y $20 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $22 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $20 - connect \Y $19 - end - process $group_6 - assign \t5 1'0 - assign \t5 $19 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire width 1 \t6 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire width 1 $23 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire width 1 $24 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_bool $25 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A { \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [6] } - connect \Y $24 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $26 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $24 - connect \Y $23 - end - process $group_7 - assign \t6 1'0 - assign \t6 $23 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire width 1 \t7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire width 1 $27 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire width 1 $28 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_bool $29 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A { \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [7] } - connect \Y $28 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $30 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $28 - connect \Y $27 - end - process $group_8 - assign \t7 1'0 - assign \t7 $27 - sync init - end - process $group_9 - assign \o 8'00000000 - assign \o { \t0 \t1 \t2 \t3 \t4 \t5 \t6 \t7 } - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" - wire width 1 $31 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" - cell $reduce_bool $32 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \o - connect \Y $31 - end - process $group_10 - assign \en_o 1'0 - assign \en_o $31 - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.dec_SHIFT_ROT.dec_cr_out" -module \dec_cr_out$190 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:550" - wire width 32 input 0 \insn_in - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:549" - wire width 3 input 1 \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:548" - wire width 1 input 2 \rc_in - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 7 input 3 \SHIFT_ROT_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 4 \cr_bitfield_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 8 input 5 \SHIFT_ROT_FXM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 3 input 6 \X_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 input 7 \XL_BT - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" - wire width 8 \ppick_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" - wire width 1 \ppick_en_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" - wire width 8 \ppick_o - cell \ppick$191 \ppick - connect \i \ppick_i - connect \en_o \ppick_en_o - connect \o \ppick_o - end - process $group_0 - assign \cr_bitfield_ok 1'0 - assign \cr_bitfield_ok 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:563" - switch \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:564" - attribute \nmigen.decoding "NONE/0" - case 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:566" - attribute \nmigen.decoding "CR0/1" - case 3'001 - assign \cr_bitfield_ok \rc_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:569" - attribute \nmigen.decoding "BF/2" - case 3'010 - assign \cr_bitfield_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:572" - attribute \nmigen.decoding "BT/3" - case 3'011 - assign \cr_bitfield_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:575" - attribute \nmigen.decoding "WHOLE_REG/4" - case 3'100 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \cr_fxm_ok - process $group_1 - assign \cr_fxm_ok 1'0 - assign \cr_fxm_ok 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:563" - switch \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:564" - attribute \nmigen.decoding "NONE/0" - case 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:566" - attribute \nmigen.decoding "CR0/1" - case 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:569" - attribute \nmigen.decoding "BF/2" - case 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:572" - attribute \nmigen.decoding "BT/3" - case 3'011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:575" - attribute \nmigen.decoding "WHOLE_REG/4" - case 3'100 - assign \cr_fxm_ok 1'1 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 3 \cr_bitfield - process $group_2 - assign \cr_bitfield 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:563" - switch \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:564" - attribute \nmigen.decoding "NONE/0" - case 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:566" - attribute \nmigen.decoding "CR0/1" - case 3'001 - assign \cr_bitfield 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:569" - attribute \nmigen.decoding "BF/2" - case 3'010 - assign \cr_bitfield \X_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:572" - attribute \nmigen.decoding "BT/3" - case 3'011 - assign \cr_bitfield \XL_BT [4:2] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:575" - attribute \nmigen.decoding "WHOLE_REG/4" - case 3'100 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:577" - wire width 1 \move_one - process $group_3 - assign \move_one 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:563" - switch \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:564" - attribute \nmigen.decoding "NONE/0" - case 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:566" - attribute \nmigen.decoding "CR0/1" - case 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:569" - attribute \nmigen.decoding "BF/2" - case 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:572" - attribute \nmigen.decoding "BT/3" - case 3'011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:575" - attribute \nmigen.decoding "WHOLE_REG/4" - case 3'100 - assign \move_one \insn_in [20] - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:579" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:579" - cell $eq $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A \SHIFT_ROT_internal_op - connect \B 7'0110000 - connect \Y $1 - end - process $group_4 - assign \ppick_i 8'00000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:563" - switch \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:564" - attribute \nmigen.decoding "NONE/0" - case 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:566" - attribute \nmigen.decoding "CR0/1" - case 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:569" - attribute \nmigen.decoding "BF/2" - case 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:572" - attribute \nmigen.decoding "BT/3" - case 3'011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:575" - attribute \nmigen.decoding "WHOLE_REG/4" - case 3'100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:579" - switch { $1 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:579" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:580" - switch { \move_one } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:580" - case 1'1 - assign \ppick_i \SHIFT_ROT_FXM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:587" - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:589" - case - end - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 8 \cr_fxm - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:579" - wire width 1 $3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:579" - cell $eq $4 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A \SHIFT_ROT_internal_op - connect \B 7'0110000 - connect \Y $3 - end - process $group_5 - assign \cr_fxm 8'00000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:563" - switch \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:564" - attribute \nmigen.decoding "NONE/0" - case 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:566" - attribute \nmigen.decoding "CR0/1" - case 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:569" - attribute \nmigen.decoding "BF/2" - case 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:572" - attribute \nmigen.decoding "BT/3" - case 3'011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:575" - attribute \nmigen.decoding "WHOLE_REG/4" - case 3'100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:579" - switch { $3 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:579" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:580" - switch { \move_one } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:580" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:583" - switch { \ppick_en_o } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:583" - case 1'1 - assign \cr_fxm \ppick_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:585" - case - assign \cr_fxm 8'00000001 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:587" - case - assign \cr_fxm \SHIFT_ROT_FXM - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:589" - case - assign \cr_fxm 8'11111111 - end - end - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.dec_SHIFT_ROT.dec_bi" -module \dec_bi$192 - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:216" - wire width 4 input 0 \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 output 1 \imm_b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 2 \imm_b_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 16 input 3 \SHIFT_ROT_SI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 16 input 4 \SHIFT_ROT_UI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 5 input 5 \SHIFT_ROT_SH32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 6 input 6 \SHIFT_ROT_sh - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 24 input 7 \SHIFT_ROT_LI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 14 input 8 \SHIFT_ROT_BD - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 14 input 9 \SHIFT_ROT_DS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 64 $1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - cell $pos $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 16 - parameter \Y_WIDTH 64 - connect \A \SHIFT_ROT_UI - connect \Y $1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:229" - wire width 16 \si - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:234" - wire width 32 \si_hi - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:241" - wire width 64 $3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:239" - wire width 16 \ui - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:241" - wire width 47 $4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:241" - cell $sshl $5 - parameter \A_SIGNED 0 - parameter \A_WIDTH 16 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 47 - connect \A \ui - connect \B 5'10000 - connect \Y $4 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:241" - cell $pos $6 - parameter \A_SIGNED 0 - parameter \A_WIDTH 47 - parameter \Y_WIDTH 64 - connect \A $4 - connect \Y $3 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" - wire width 26 \li - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:249" - wire width 16 \bd - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:254" - wire width 16 \ds - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:259" - wire width 64 $7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:259" - cell $not $8 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \Y_WIDTH 64 - connect \A 64'0000000000000000000000000000000000000000000000000000000000000000 - connect \Y $7 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 64 $9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - cell $pos $10 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \Y_WIDTH 64 - connect \A \SHIFT_ROT_sh - connect \Y $9 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 64 $11 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - cell $pos $12 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \Y_WIDTH 64 - connect \A \SHIFT_ROT_SH32 - connect \Y $11 - end - process $group_0 - assign \imm_b 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:224" - switch \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:225" - attribute \nmigen.decoding "CONST_UI/2" - case 4'0010 - assign \imm_b $1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:228" - attribute \nmigen.decoding "CONST_SI/3" - case 4'0011 - assign \imm_b { { \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] } \si } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:233" - attribute \nmigen.decoding "CONST_SI_HI/5" - case 4'0101 - assign \imm_b { { \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] } \si_hi } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:238" - attribute \nmigen.decoding "CONST_UI_HI/4" - case 4'0100 - assign \imm_b $3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:243" - attribute \nmigen.decoding "CONST_LI/6" - case 4'0110 - assign \imm_b { { \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] } \li } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:248" - attribute \nmigen.decoding "CONST_BD/7" - case 4'0111 - assign \imm_b { { \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] } \bd } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:253" - attribute \nmigen.decoding "CONST_DS/8" - case 4'1000 - assign \imm_b { { \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] } \ds } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:258" - attribute \nmigen.decoding "CONST_M1/9" - case 4'1001 - assign \imm_b $7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" - attribute \nmigen.decoding "CONST_SH/10" - case 4'1010 - assign \imm_b $9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:264" - attribute \nmigen.decoding "CONST_SH32/11" - case 4'1011 - assign \imm_b $11 - end - sync init - end - process $group_1 - assign \imm_b_ok 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:224" - switch \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:225" - attribute \nmigen.decoding "CONST_UI/2" - case 4'0010 - assign \imm_b_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:228" - attribute \nmigen.decoding "CONST_SI/3" - case 4'0011 - assign \imm_b_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:233" - attribute \nmigen.decoding "CONST_SI_HI/5" - case 4'0101 - assign \imm_b_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:238" - attribute \nmigen.decoding "CONST_UI_HI/4" - case 4'0100 - assign \imm_b_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:243" - attribute \nmigen.decoding "CONST_LI/6" - case 4'0110 - assign \imm_b_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:248" - attribute \nmigen.decoding "CONST_BD/7" - case 4'0111 - assign \imm_b_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:253" - attribute \nmigen.decoding "CONST_DS/8" - case 4'1000 - assign \imm_b_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:258" - attribute \nmigen.decoding "CONST_M1/9" - case 4'1001 - assign \imm_b_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" - attribute \nmigen.decoding "CONST_SH/10" - case 4'1010 - assign \imm_b_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:264" - attribute \nmigen.decoding "CONST_SH32/11" - case 4'1011 - assign \imm_b_ok 1'1 - end - sync init - end - process $group_2 - assign \si 16'0000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:224" - switch \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:225" - attribute \nmigen.decoding "CONST_UI/2" - case 4'0010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:228" - attribute \nmigen.decoding "CONST_SI/3" - case 4'0011 - assign \si \SHIFT_ROT_SI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:233" - attribute \nmigen.decoding "CONST_SI_HI/5" - case 4'0101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:238" - attribute \nmigen.decoding "CONST_UI_HI/4" - case 4'0100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:243" - attribute \nmigen.decoding "CONST_LI/6" - case 4'0110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:248" - attribute \nmigen.decoding "CONST_BD/7" - case 4'0111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:253" - attribute \nmigen.decoding "CONST_DS/8" - case 4'1000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:258" - attribute \nmigen.decoding "CONST_M1/9" - case 4'1001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" - attribute \nmigen.decoding "CONST_SH/10" - case 4'1010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:264" - attribute \nmigen.decoding "CONST_SH32/11" - case 4'1011 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:235" - wire width 47 $13 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:235" - wire width 47 $14 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:235" - cell $sshl $15 - parameter \A_SIGNED 0 - parameter \A_WIDTH 16 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 47 - connect \A \SHIFT_ROT_SI - connect \B 5'10000 - connect \Y $14 - end - connect $13 $14 - process $group_3 - assign \si_hi 32'00000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:224" - switch \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:225" - attribute \nmigen.decoding "CONST_UI/2" - case 4'0010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:228" - attribute \nmigen.decoding "CONST_SI/3" - case 4'0011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:233" - attribute \nmigen.decoding "CONST_SI_HI/5" - case 4'0101 - assign \si_hi $13 [31:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:238" - attribute \nmigen.decoding "CONST_UI_HI/4" - case 4'0100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:243" - attribute \nmigen.decoding "CONST_LI/6" - case 4'0110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:248" - attribute \nmigen.decoding "CONST_BD/7" - case 4'0111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:253" - attribute \nmigen.decoding "CONST_DS/8" - case 4'1000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:258" - attribute \nmigen.decoding "CONST_M1/9" - case 4'1001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" - attribute \nmigen.decoding "CONST_SH/10" - case 4'1010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:264" - attribute \nmigen.decoding "CONST_SH32/11" - case 4'1011 - end - sync init - end - process $group_4 - assign \ui 16'0000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:224" - switch \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:225" - attribute \nmigen.decoding "CONST_UI/2" - case 4'0010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:228" - attribute \nmigen.decoding "CONST_SI/3" - case 4'0011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:233" - attribute \nmigen.decoding "CONST_SI_HI/5" - case 4'0101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:238" - attribute \nmigen.decoding "CONST_UI_HI/4" - case 4'0100 - assign \ui \SHIFT_ROT_UI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:243" - attribute \nmigen.decoding "CONST_LI/6" - case 4'0110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:248" - attribute \nmigen.decoding "CONST_BD/7" - case 4'0111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:253" - attribute \nmigen.decoding "CONST_DS/8" - case 4'1000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:258" - attribute \nmigen.decoding "CONST_M1/9" - case 4'1001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" - attribute \nmigen.decoding "CONST_SH/10" - case 4'1010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:264" - attribute \nmigen.decoding "CONST_SH32/11" - case 4'1011 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:245" - wire width 27 $16 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:245" - wire width 27 $17 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:245" - cell $sshl $18 - parameter \A_SIGNED 0 - parameter \A_WIDTH 24 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 27 - connect \A \SHIFT_ROT_LI - connect \B 2'10 - connect \Y $17 - end - connect $16 $17 - process $group_5 - assign \li 26'00000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:224" - switch \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:225" - attribute \nmigen.decoding "CONST_UI/2" - case 4'0010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:228" - attribute \nmigen.decoding "CONST_SI/3" - case 4'0011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:233" - attribute \nmigen.decoding "CONST_SI_HI/5" - case 4'0101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:238" - attribute \nmigen.decoding "CONST_UI_HI/4" - case 4'0100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:243" - attribute \nmigen.decoding "CONST_LI/6" - case 4'0110 - assign \li $16 [25:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:248" - attribute \nmigen.decoding "CONST_BD/7" - case 4'0111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:253" - attribute \nmigen.decoding "CONST_DS/8" - case 4'1000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:258" - attribute \nmigen.decoding "CONST_M1/9" - case 4'1001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" - attribute \nmigen.decoding "CONST_SH/10" - case 4'1010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:264" - attribute \nmigen.decoding "CONST_SH32/11" - case 4'1011 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:250" - wire width 17 $19 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:250" - wire width 17 $20 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:250" - cell $sshl $21 - parameter \A_SIGNED 0 - parameter \A_WIDTH 14 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 17 - connect \A \SHIFT_ROT_BD - connect \B 2'10 - connect \Y $20 - end - connect $19 $20 - process $group_6 - assign \bd 16'0000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:224" - switch \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:225" - attribute \nmigen.decoding "CONST_UI/2" - case 4'0010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:228" - attribute \nmigen.decoding "CONST_SI/3" - case 4'0011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:233" - attribute \nmigen.decoding "CONST_SI_HI/5" - case 4'0101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:238" - attribute \nmigen.decoding "CONST_UI_HI/4" - case 4'0100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:243" - attribute \nmigen.decoding "CONST_LI/6" - case 4'0110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:248" - attribute \nmigen.decoding "CONST_BD/7" - case 4'0111 - assign \bd $19 [15:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:253" - attribute \nmigen.decoding "CONST_DS/8" - case 4'1000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:258" - attribute \nmigen.decoding "CONST_M1/9" - case 4'1001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" - attribute \nmigen.decoding "CONST_SH/10" - case 4'1010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:264" - attribute \nmigen.decoding "CONST_SH32/11" - case 4'1011 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:255" - wire width 17 $22 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:255" - wire width 17 $23 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:255" - cell $sshl $24 - parameter \A_SIGNED 0 - parameter \A_WIDTH 14 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 17 - connect \A \SHIFT_ROT_DS - connect \B 2'10 - connect \Y $23 - end - connect $22 $23 - process $group_7 - assign \ds 16'0000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:224" - switch \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:225" - attribute \nmigen.decoding "CONST_UI/2" - case 4'0010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:228" - attribute \nmigen.decoding "CONST_SI/3" - case 4'0011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:233" - attribute \nmigen.decoding "CONST_SI_HI/5" - case 4'0101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:238" - attribute \nmigen.decoding "CONST_UI_HI/4" - case 4'0100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:243" - attribute \nmigen.decoding "CONST_LI/6" - case 4'0110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:248" - attribute \nmigen.decoding "CONST_BD/7" - case 4'0111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:253" - attribute \nmigen.decoding "CONST_DS/8" - case 4'1000 - assign \ds $22 [15:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:258" - attribute \nmigen.decoding "CONST_M1/9" - case 4'1001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" - attribute \nmigen.decoding "CONST_SH/10" - case 4'1010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:264" - attribute \nmigen.decoding "CONST_SH32/11" - case 4'1011 - end - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.dec_SHIFT_ROT" -module \dec_SHIFT_ROT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:384" - wire width 32 input 0 \raw_opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:385" - wire width 1 input 1 \bigendian - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 output 2 \SHIFT_ROT_SHIFT_ROT__insn_type - attribute \enum_base_type "Function" - attribute \enum_value_00000000000 "NONE" - attribute \enum_value_00000000010 "ALU" - attribute \enum_value_00000000100 "LDST" - attribute \enum_value_00000001000 "SHIFT_ROT" - attribute \enum_value_00000010000 "LOGICAL" - attribute \enum_value_00000100000 "BRANCH" - attribute \enum_value_00001000000 "CR" - attribute \enum_value_00010000000 "TRAP" - attribute \enum_value_00100000000 "MUL" - attribute \enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 output 3 \SHIFT_ROT_SHIFT_ROT__fn_unit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 output 4 \SHIFT_ROT_SHIFT_ROT__imm_data__data - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 5 \SHIFT_ROT_SHIFT_ROT__imm_data__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 6 \SHIFT_ROT_SHIFT_ROT__rc__rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 7 \SHIFT_ROT_SHIFT_ROT__rc__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 8 \SHIFT_ROT_SHIFT_ROT__oe__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 9 \SHIFT_ROT_SHIFT_ROT__oe__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 10 \SHIFT_ROT_SHIFT_ROT__write_cr0 - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 output 11 \SHIFT_ROT_SHIFT_ROT__input_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 12 \SHIFT_ROT_SHIFT_ROT__output_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 13 \SHIFT_ROT_SHIFT_ROT__input_cr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 14 \SHIFT_ROT_SHIFT_ROT__output_cr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 15 \SHIFT_ROT_SHIFT_ROT__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 output 16 \SHIFT_ROT_SHIFT_ROT__is_signed - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 output 17 \SHIFT_ROT_SHIFT_ROT__insn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" - wire width 32 \dec_opcode_in - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 2 \dec_SHIFT_ROT_rc_sel - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \dec_SHIFT_ROT_cr_in - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \dec_SHIFT_ROT_cr_out - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 7 \dec_SHIFT_ROT_internal_op - attribute \enum_base_type "Function" - attribute \enum_value_00000000000 "NONE" - attribute \enum_value_00000000010 "ALU" - attribute \enum_value_00000000100 "LDST" - attribute \enum_value_00000001000 "SHIFT_ROT" - attribute \enum_value_00000010000 "LOGICAL" - attribute \enum_value_00000100000 "BRANCH" - attribute \enum_value_00001000000 "CR" - attribute \enum_value_00010000000 "TRAP" - attribute \enum_value_00100000000 "MUL" - attribute \enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 11 \dec_SHIFT_ROT_function_unit - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 4 \dec_SHIFT_ROT_in2_sel - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 2 \dec_SHIFT_ROT_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \dec_SHIFT_ROT_cry_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \dec_SHIFT_ROT_is_32b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \dec_SHIFT_ROT_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 16 \dec_SHIFT_ROT_SI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 16 \dec_SHIFT_ROT_UI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 5 \dec_SHIFT_ROT_SH32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 6 \dec_SHIFT_ROT_sh - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 24 \dec_SHIFT_ROT_LI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 1 \dec_SHIFT_ROT_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 1 \dec_SHIFT_ROT_OE - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 14 \dec_SHIFT_ROT_BD - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 5 \dec_SHIFT_ROT_BB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 5 \dec_SHIFT_ROT_BA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 5 \dec_SHIFT_ROT_BT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 8 \dec_SHIFT_ROT_FXM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 5 \dec_SHIFT_ROT_BI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 14 \dec_SHIFT_ROT_DS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 5 \dec_SHIFT_ROT_BC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 3 \dec_X_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 3 \dec_X_BFA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \dec_XL_BT - cell \dec$185 \dec - connect \raw_opcode_in \raw_opcode_in - connect \bigendian \bigendian - connect \opcode_in \dec_opcode_in - connect \SHIFT_ROT_rc_sel \dec_SHIFT_ROT_rc_sel - connect \SHIFT_ROT_cr_in \dec_SHIFT_ROT_cr_in - connect \SHIFT_ROT_cr_out \dec_SHIFT_ROT_cr_out - connect \SHIFT_ROT_internal_op \dec_SHIFT_ROT_internal_op - connect \SHIFT_ROT_function_unit \dec_SHIFT_ROT_function_unit - connect \SHIFT_ROT_in2_sel \dec_SHIFT_ROT_in2_sel - connect \SHIFT_ROT_cry_in \dec_SHIFT_ROT_cry_in - connect \SHIFT_ROT_cry_out \dec_SHIFT_ROT_cry_out - connect \SHIFT_ROT_is_32b \dec_SHIFT_ROT_is_32b - connect \SHIFT_ROT_sgn \dec_SHIFT_ROT_sgn - connect \SHIFT_ROT_SI \dec_SHIFT_ROT_SI - connect \SHIFT_ROT_UI \dec_SHIFT_ROT_UI - connect \SHIFT_ROT_SH32 \dec_SHIFT_ROT_SH32 - connect \SHIFT_ROT_sh \dec_SHIFT_ROT_sh - connect \SHIFT_ROT_LI \dec_SHIFT_ROT_LI - connect \SHIFT_ROT_Rc \dec_SHIFT_ROT_Rc - connect \SHIFT_ROT_OE \dec_SHIFT_ROT_OE - connect \SHIFT_ROT_BD \dec_SHIFT_ROT_BD - connect \SHIFT_ROT_BB \dec_SHIFT_ROT_BB - connect \SHIFT_ROT_BA \dec_SHIFT_ROT_BA - connect \SHIFT_ROT_BT \dec_SHIFT_ROT_BT - connect \SHIFT_ROT_FXM \dec_SHIFT_ROT_FXM - connect \SHIFT_ROT_BI \dec_SHIFT_ROT_BI - connect \SHIFT_ROT_DS \dec_SHIFT_ROT_DS - connect \SHIFT_ROT_BC \dec_SHIFT_ROT_BC - connect \X_BF \dec_X_BF - connect \X_BFA \dec_X_BFA - connect \XL_BT \dec_XL_BT - end - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:404" - wire width 2 \dec_rc_sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \dec_rc_rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \dec_rc_rc_ok - cell \dec_rc$186 \dec_rc - connect \sel_in \dec_rc_sel_in - connect \rc \dec_rc_rc - connect \rc_ok \dec_rc_rc_ok - connect \SHIFT_ROT_Rc \dec_SHIFT_ROT_Rc - end - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:441" - wire width 2 \dec_oe_sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \dec_oe_oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \dec_oe_oe_ok - cell \dec_oe$187 \dec_oe - connect \sel_in \dec_oe_sel_in - connect \SHIFT_ROT_internal_op \dec_SHIFT_ROT_internal_op - connect \oe \dec_oe_oe - connect \oe_ok \dec_oe_oe_ok - connect \SHIFT_ROT_OE \dec_SHIFT_ROT_OE - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:485" - wire width 32 \dec_cr_in_insn_in - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:484" - wire width 3 \dec_cr_in_sel_in - cell \dec_cr_in$188 \dec_cr_in - connect \insn_in \dec_cr_in_insn_in - connect \sel_in \dec_cr_in_sel_in - connect \SHIFT_ROT_internal_op \dec_SHIFT_ROT_internal_op - connect \SHIFT_ROT_BB \dec_SHIFT_ROT_BB - connect \SHIFT_ROT_BA \dec_SHIFT_ROT_BA - connect \SHIFT_ROT_BT \dec_SHIFT_ROT_BT - connect \SHIFT_ROT_FXM \dec_SHIFT_ROT_FXM - connect \SHIFT_ROT_BI \dec_SHIFT_ROT_BI - connect \SHIFT_ROT_BC \dec_SHIFT_ROT_BC - connect \X_BFA \dec_X_BFA - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:550" - wire width 32 \dec_cr_out_insn_in - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:549" - wire width 3 \dec_cr_out_sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:548" - wire width 1 \dec_cr_out_rc_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \dec_cr_out_cr_bitfield_ok - cell \dec_cr_out$190 \dec_cr_out - connect \insn_in \dec_cr_out_insn_in - connect \sel_in \dec_cr_out_sel_in - connect \rc_in \dec_cr_out_rc_in - connect \SHIFT_ROT_internal_op \dec_SHIFT_ROT_internal_op - connect \cr_bitfield_ok \dec_cr_out_cr_bitfield_ok - connect \SHIFT_ROT_FXM \dec_SHIFT_ROT_FXM - connect \X_BF \dec_X_BF - connect \XL_BT \dec_XL_BT - end - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:216" - wire width 4 \dec_bi_sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 \dec_bi_imm_b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \dec_bi_imm_b_ok - cell \dec_bi$192 \dec_bi - connect \sel_in \dec_bi_sel_in - connect \imm_b \dec_bi_imm_b - connect \imm_b_ok \dec_bi_imm_b_ok - connect \SHIFT_ROT_SI \dec_SHIFT_ROT_SI - connect \SHIFT_ROT_UI \dec_SHIFT_ROT_UI - connect \SHIFT_ROT_SH32 \dec_SHIFT_ROT_SH32 - connect \SHIFT_ROT_sh \dec_SHIFT_ROT_sh - connect \SHIFT_ROT_LI \dec_SHIFT_ROT_LI - connect \SHIFT_ROT_BD \dec_SHIFT_ROT_BD - connect \SHIFT_ROT_DS \dec_SHIFT_ROT_DS - end - process $group_0 - assign \SHIFT_ROT_SHIFT_ROT__insn 32'00000000000000000000000000000000 - assign \SHIFT_ROT_SHIFT_ROT__insn \dec_opcode_in - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:405" - wire width 32 \insn_in - process $group_1 - assign \insn_in 32'00000000000000000000000000000000 - assign \insn_in \dec_opcode_in - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:442" - wire width 32 \insn_in$1 - process $group_2 - assign \insn_in$1 32'00000000000000000000000000000000 - assign \insn_in$1 \dec_opcode_in - sync init - end - process $group_3 - assign \dec_cr_in_insn_in 32'00000000000000000000000000000000 - assign \dec_cr_in_insn_in \dec_opcode_in - sync init - end - process $group_4 - assign \dec_cr_out_insn_in 32'00000000000000000000000000000000 - assign \dec_cr_out_insn_in \dec_opcode_in - sync init - end - process $group_5 - assign \dec_rc_sel_in 2'00 - assign \dec_rc_sel_in \dec_SHIFT_ROT_rc_sel - sync init - end - process $group_6 - assign \dec_oe_sel_in 2'00 - assign \dec_oe_sel_in \dec_SHIFT_ROT_rc_sel - sync init - end - process $group_7 - assign \dec_cr_in_sel_in 3'000 - assign \dec_cr_in_sel_in \dec_SHIFT_ROT_cr_in - sync init - end - process $group_8 - assign \dec_cr_out_sel_in 3'000 - assign \dec_cr_out_sel_in \dec_SHIFT_ROT_cr_out - sync init - end - process $group_9 - assign \dec_cr_out_rc_in 1'0 - assign \dec_cr_out_rc_in \dec_rc_rc - sync init - end - process $group_10 - assign \SHIFT_ROT_SHIFT_ROT__insn_type 7'0000000 - assign \SHIFT_ROT_SHIFT_ROT__insn_type \dec_SHIFT_ROT_internal_op - sync init - end - process $group_11 - assign \SHIFT_ROT_SHIFT_ROT__fn_unit 11'00000000000 - assign \SHIFT_ROT_SHIFT_ROT__fn_unit \dec_SHIFT_ROT_function_unit - sync init - end - process $group_12 - assign \dec_bi_sel_in 4'0000 - assign \dec_bi_sel_in \dec_SHIFT_ROT_in2_sel - sync init - end - process $group_13 - assign \SHIFT_ROT_SHIFT_ROT__imm_data__data 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \SHIFT_ROT_SHIFT_ROT__imm_data__ok 1'0 - assign { \SHIFT_ROT_SHIFT_ROT__imm_data__ok \SHIFT_ROT_SHIFT_ROT__imm_data__data } { \dec_bi_imm_b_ok \dec_bi_imm_b } - sync init - end - process $group_15 - assign \SHIFT_ROT_SHIFT_ROT__rc__rc 1'0 - assign \SHIFT_ROT_SHIFT_ROT__rc__ok 1'0 - assign { \SHIFT_ROT_SHIFT_ROT__rc__ok \SHIFT_ROT_SHIFT_ROT__rc__rc } { \dec_rc_rc_ok \dec_rc_rc } - sync init - end - process $group_17 - assign \SHIFT_ROT_SHIFT_ROT__oe__oe 1'0 - assign \SHIFT_ROT_SHIFT_ROT__oe__ok 1'0 - assign { \SHIFT_ROT_SHIFT_ROT__oe__ok \SHIFT_ROT_SHIFT_ROT__oe__oe } { \dec_oe_oe_ok \dec_oe_oe } - sync init - end - process $group_19 - assign \SHIFT_ROT_SHIFT_ROT__write_cr0 1'0 - assign \SHIFT_ROT_SHIFT_ROT__write_cr0 \dec_cr_out_cr_bitfield_ok - sync init - end - process $group_20 - assign \SHIFT_ROT_SHIFT_ROT__input_cr 1'0 - assign \SHIFT_ROT_SHIFT_ROT__input_cr \dec_SHIFT_ROT_cr_in [0] - sync init - end - process $group_21 - assign \SHIFT_ROT_SHIFT_ROT__output_cr 1'0 - assign \SHIFT_ROT_SHIFT_ROT__output_cr \dec_SHIFT_ROT_cr_out [0] - sync init - end - process $group_22 - assign \SHIFT_ROT_SHIFT_ROT__input_carry 2'00 - assign \SHIFT_ROT_SHIFT_ROT__input_carry \dec_SHIFT_ROT_cry_in - sync init - end - process $group_23 - assign \SHIFT_ROT_SHIFT_ROT__output_carry 1'0 - assign \SHIFT_ROT_SHIFT_ROT__output_carry \dec_SHIFT_ROT_cry_out - sync init - end - process $group_24 - assign \SHIFT_ROT_SHIFT_ROT__is_32bit 1'0 - assign \SHIFT_ROT_SHIFT_ROT__is_32bit \dec_SHIFT_ROT_is_32b - sync init - end - process $group_25 - assign \SHIFT_ROT_SHIFT_ROT__is_signed 1'0 - assign \SHIFT_ROT_SHIFT_ROT__is_signed \dec_SHIFT_ROT_sgn - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.dec_LDST.dec.LDST_dec19" -module \LDST_dec19 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" - wire width 32 input 0 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:308" - wire width 10 \opcode_switch - process $group_0 - assign \opcode_switch 10'0000000000 - assign \opcode_switch \opcode_in [10:1] - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:308" - wire width 5 \opcode_switch$1 - process $group_1 - assign \opcode_switch$1 5'00000 - assign \opcode_switch$1 \opcode_in [5:1] - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.dec_LDST.dec.LDST_dec30" -module \LDST_dec30 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" - wire width 32 input 0 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:308" - wire width 4 \opcode_switch - process $group_0 - assign \opcode_switch 4'0000 - assign \opcode_switch \opcode_in [4:1] - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.dec_LDST.dec.LDST_dec31.LDST_dec_sub10" -module \LDST_dec_sub10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" - wire width 32 input 0 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:308" - wire width 5 \opcode_switch - process $group_0 - assign \opcode_switch 5'00000 - assign \opcode_switch \opcode_in [10:6] - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.dec_LDST.dec.LDST_dec31.LDST_dec_sub28" -module \LDST_dec_sub28 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" - wire width 32 input 0 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:308" - wire width 5 \opcode_switch - process $group_0 - assign \opcode_switch 5'00000 - assign \opcode_switch \opcode_in [10:6] - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.dec_LDST.dec.LDST_dec31.LDST_dec_sub0" -module \LDST_dec_sub0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" - wire width 32 input 0 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:308" - wire width 5 \opcode_switch - process $group_0 - assign \opcode_switch 5'00000 - assign \opcode_switch \opcode_in [10:6] - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.dec_LDST.dec.LDST_dec31.LDST_dec_sub26" -module \LDST_dec_sub26 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" - wire width 32 input 0 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:308" - wire width 5 \opcode_switch - process $group_0 - assign \opcode_switch 5'00000 - assign \opcode_switch \opcode_in [10:6] - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.dec_LDST.dec.LDST_dec31.LDST_dec_sub19" -module \LDST_dec_sub19 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" - wire width 32 input 0 \opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:308" - wire width 5 \opcode_switch - process $group_0 - assign \opcode_switch 5'00000 - assign \opcode_switch \opcode_in [10:6] - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.dec_LDST.dec.LDST_dec31.LDST_dec_sub22" -module \LDST_dec_sub22 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" - wire width 32 input 0 \opcode_in - attribute \enum_base_type "Function" - attribute \enum_value_00000000000 "NONE" - attribute \enum_value_00000000010 "ALU" - attribute \enum_value_00000000100 "LDST" - attribute \enum_value_00000001000 "SHIFT_ROT" - attribute \enum_value_00000010000 "LOGICAL" - attribute \enum_value_00000100000 "BRANCH" - attribute \enum_value_00001000000 "CR" - attribute \enum_value_00010000000 "TRAP" - attribute \enum_value_00100000000 "MUL" - attribute \enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 11 output 1 \LDST_function_unit - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 7 output 2 \LDST_internal_op - attribute \enum_base_type "In1Sel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "RA" - attribute \enum_value_010 "RA_OR_ZERO" - attribute \enum_value_011 "SPR" - attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 output 3 \LDST_in1_sel - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 4 output 4 \LDST_in2_sel - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 output 5 \LDST_cr_in - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 output 6 \LDST_cr_out - attribute \enum_base_type "LdstLen" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "is1B" - attribute \enum_value_0010 "is2B" - attribute \enum_value_0100 "is4B" - attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 4 output 7 \LDST_ldst_len - attribute \enum_base_type "LDSTMode" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "update" - attribute \enum_value_10 "cix" - attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 2 output 8 \LDST_upd - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 2 output 9 \LDST_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 output 10 \LDST_br - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 output 11 \LDST_sgn_ext - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 output 12 \LDST_is_32b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 output 13 \LDST_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:308" - wire width 5 \opcode_switch - process $group_0 - assign \opcode_switch 5'00000 - assign \opcode_switch \opcode_in [10:6] - sync init - end - process $group_1 - assign \LDST_function_unit 11'00000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11000 - assign \LDST_function_unit 11'00000000100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10000 - assign \LDST_function_unit 11'00000000100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10101 - assign \LDST_function_unit 11'00000000100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00110 - assign \LDST_function_unit 11'00000000100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11100 - assign \LDST_function_unit 11'00000000100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10110 - assign \LDST_function_unit 11'00000000100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10100 - assign \LDST_function_unit 11'00000000100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00100 - assign \LDST_function_unit 11'00000000100 - end - sync init - end - process $group_2 - assign \LDST_internal_op 7'0000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11000 - assign \LDST_internal_op 7'0100101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10000 - assign \LDST_internal_op 7'0100101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10101 - assign \LDST_internal_op 7'0100110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00110 - assign \LDST_internal_op 7'0100110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11100 - assign \LDST_internal_op 7'0100110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10110 - assign \LDST_internal_op 7'0100110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10100 - assign \LDST_internal_op 7'0100110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00100 - assign \LDST_internal_op 7'0100110 - end - sync init - end - process $group_3 - assign \LDST_in1_sel 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11000 - assign \LDST_in1_sel 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10000 - assign \LDST_in1_sel 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10101 - assign \LDST_in1_sel 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00110 - assign \LDST_in1_sel 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11100 - assign \LDST_in1_sel 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10110 - assign \LDST_in1_sel 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10100 - assign \LDST_in1_sel 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00100 - assign \LDST_in1_sel 3'010 - end - sync init - end - process $group_4 - assign \LDST_in2_sel 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11000 - assign \LDST_in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10000 - assign \LDST_in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10101 - assign \LDST_in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00110 - assign \LDST_in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11100 - assign \LDST_in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10110 - assign \LDST_in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10100 - assign \LDST_in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00100 - assign \LDST_in2_sel 4'0001 - end - sync init - end - process $group_5 - assign \LDST_cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11000 - assign \LDST_cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10000 - assign \LDST_cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10101 - assign \LDST_cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00110 - assign \LDST_cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11100 - assign \LDST_cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10110 - assign \LDST_cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10100 - assign \LDST_cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00100 - assign \LDST_cr_in 3'000 - end - sync init - end - process $group_6 - assign \LDST_cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11000 - assign \LDST_cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10000 - assign \LDST_cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10101 - assign \LDST_cr_out 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00110 - assign \LDST_cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11100 - assign \LDST_cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10110 - assign \LDST_cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10100 - assign \LDST_cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00100 - assign \LDST_cr_out 3'000 - end - sync init - end - process $group_7 - assign \LDST_ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11000 - assign \LDST_ldst_len 4'0010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10000 - assign \LDST_ldst_len 4'0100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10101 - assign \LDST_ldst_len 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00110 - assign \LDST_ldst_len 4'1000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11100 - assign \LDST_ldst_len 4'0010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10110 - assign \LDST_ldst_len 4'0010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10100 - assign \LDST_ldst_len 4'0100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00100 - assign \LDST_ldst_len 4'0100 - end - sync init - end - process $group_8 - assign \LDST_upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11000 - assign \LDST_upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10000 - assign \LDST_upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10101 - assign \LDST_upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00110 - assign \LDST_upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11100 - assign \LDST_upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10110 - assign \LDST_upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10100 - assign \LDST_upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00100 - assign \LDST_upd 2'00 - end - sync init - end - process $group_9 - assign \LDST_rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11000 - assign \LDST_rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10000 - assign \LDST_rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10101 - assign \LDST_rc_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00110 - assign \LDST_rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11100 - assign \LDST_rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10110 - assign \LDST_rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10100 - assign \LDST_rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00100 - assign \LDST_rc_sel 2'00 - end - sync init - end - process $group_10 - assign \LDST_br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11000 - assign \LDST_br 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10000 - assign \LDST_br 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10101 - assign \LDST_br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00110 - assign \LDST_br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11100 - assign \LDST_br 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10110 - assign \LDST_br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10100 - assign \LDST_br 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00100 - assign \LDST_br 1'0 - end - sync init - end - process $group_11 - assign \LDST_sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11000 - assign \LDST_sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10000 - assign \LDST_sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10101 - assign \LDST_sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00110 - assign \LDST_sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11100 - assign \LDST_sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10110 - assign \LDST_sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10100 - assign \LDST_sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00100 - assign \LDST_sgn_ext 1'0 - end - sync init - end - process $group_12 - assign \LDST_is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11000 - assign \LDST_is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10000 - assign \LDST_is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10101 - assign \LDST_is_32b 1'0 - attribute \src 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\LDST_internal_op - attribute \enum_base_type "In1Sel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "RA" - attribute \enum_value_010 "RA_OR_ZERO" - attribute \enum_value_011 "SPR" - attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 output 3 \LDST_in1_sel - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 4 output 4 \LDST_in2_sel - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 output 5 \LDST_cr_in - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 output 6 \LDST_cr_out - attribute \enum_base_type "LdstLen" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "is1B" - attribute \enum_value_0010 "is2B" - attribute \enum_value_0100 "is4B" - attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 4 output 7 \LDST_ldst_len - attribute \enum_base_type "LDSTMode" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "update" - attribute \enum_value_10 "cix" - attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 2 output 8 \LDST_upd - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 2 output 9 \LDST_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 output 10 \LDST_br - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 output 11 \LDST_sgn_ext - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 output 12 \LDST_is_32b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 output 13 \LDST_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:308" - wire width 5 \opcode_switch - process $group_0 - assign \opcode_switch 5'00000 - assign \opcode_switch \opcode_in [10:6] - sync init - end - process $group_1 - assign \LDST_function_unit 11'00000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00001 - assign \LDST_function_unit 11'00000000100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00010 - assign \LDST_function_unit 11'00000000100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10000 - assign \LDST_function_unit 11'00000000100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00011 - assign \LDST_function_unit 11'00000000100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \LDST_function_unit 11'00000000100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10100 - assign \LDST_function_unit 11'00000000100 - end - sync init - end - process $group_2 - assign \LDST_internal_op 7'0000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00001 - assign \LDST_internal_op 7'0100101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00010 - assign \LDST_internal_op 7'0100101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10000 - assign \LDST_internal_op 7'0100101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00011 - assign \LDST_internal_op 7'0100101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \LDST_internal_op 7'0100101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10100 - assign \LDST_internal_op 7'0100110 - end - sync init - end - process $group_3 - assign \LDST_in1_sel 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00001 - assign \LDST_in1_sel 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00010 - assign \LDST_in1_sel 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10000 - assign \LDST_in1_sel 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00011 - assign \LDST_in1_sel 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \LDST_in1_sel 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10100 - assign \LDST_in1_sel 3'010 - end - sync init - end - process $group_4 - assign \LDST_in2_sel 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00001 - assign \LDST_in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00010 - assign \LDST_in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10000 - assign \LDST_in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00011 - assign \LDST_in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \LDST_in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10100 - assign \LDST_in2_sel 4'0001 - end - sync init - end - process $group_5 - assign \LDST_cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00001 - assign \LDST_cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00010 - assign \LDST_cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10000 - assign \LDST_cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00011 - assign \LDST_cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \LDST_cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10100 - assign \LDST_cr_in 3'000 - end - sync init - end - process $group_6 - assign \LDST_cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00001 - assign \LDST_cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00010 - assign \LDST_cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10000 - assign \LDST_cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00011 - assign \LDST_cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \LDST_cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10100 - assign \LDST_cr_out 3'000 - end - sync init - end - process $group_7 - assign \LDST_ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00001 - assign \LDST_ldst_len 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00010 - assign \LDST_ldst_len 4'1000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10000 - assign \LDST_ldst_len 4'1000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00011 - assign \LDST_ldst_len 4'0010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \LDST_ldst_len 4'0100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10100 - assign \LDST_ldst_len 4'1000 - end - sync init - end - process $group_8 - assign \LDST_upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00001 - assign \LDST_upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00010 - assign \LDST_upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10000 - assign \LDST_upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00011 - assign \LDST_upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \LDST_upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10100 - assign \LDST_upd 2'00 - end - sync init - end - process $group_9 - assign \LDST_rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00001 - assign \LDST_rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00010 - assign \LDST_rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10000 - assign \LDST_rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00011 - assign \LDST_rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \LDST_rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10100 - assign \LDST_rc_sel 2'00 - end - sync init - end - process $group_10 - assign \LDST_br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00001 - assign \LDST_br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00010 - assign \LDST_br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10000 - assign \LDST_br 1'1 - attribute \src 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attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 output 6 \LDST_cr_out - attribute \enum_base_type "LdstLen" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "is1B" - attribute \enum_value_0010 "is2B" - attribute \enum_value_0100 "is4B" - attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 4 output 7 \LDST_ldst_len - attribute \enum_base_type "LDSTMode" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "update" - attribute \enum_value_10 "cix" - attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 2 output 8 \LDST_upd - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 2 output 9 \LDST_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 output 10 \LDST_br - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 output 11 \LDST_sgn_ext - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 output 12 \LDST_is_32b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 output 13 \LDST_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:308" - wire width 5 \opcode_switch - process $group_0 - assign \opcode_switch 5'00000 - assign \opcode_switch \opcode_in [10:6] - sync init - end - process $group_1 - assign \LDST_function_unit 11'00000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11010 - assign \LDST_function_unit 11'00000000100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11011 - assign \LDST_function_unit 11'00000000100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00001 - assign \LDST_function_unit 11'00000000100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \LDST_function_unit 11'00000000100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11001 - assign \LDST_function_unit 11'00000000100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01011 - assign \LDST_function_unit 11'00000000100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01010 - assign \LDST_function_unit 11'00000000100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11000 - assign \LDST_function_unit 11'00000000100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11110 - assign \LDST_function_unit 11'00000000100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11111 - assign \LDST_function_unit 11'00000000100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00101 - assign \LDST_function_unit 11'00000000100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00100 - assign \LDST_function_unit 11'00000000100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11101 - assign \LDST_function_unit 11'00000000100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11100 - assign \LDST_function_unit 11'00000000100 - end - sync init - end - process $group_2 - assign \LDST_internal_op 7'0000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11010 - assign \LDST_internal_op 7'0100101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11011 - assign \LDST_internal_op 7'0100101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00001 - assign \LDST_internal_op 7'0100101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \LDST_internal_op 7'0100101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11001 - assign \LDST_internal_op 7'0100101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01011 - assign \LDST_internal_op 7'0100101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01010 - assign \LDST_internal_op 7'0100101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11000 - assign \LDST_internal_op 7'0100101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11110 - assign \LDST_internal_op 7'0100110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11111 - assign \LDST_internal_op 7'0100110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00101 - assign \LDST_internal_op 7'0100110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00100 - assign \LDST_internal_op 7'0100110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11101 - assign \LDST_internal_op 7'0100110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11100 - assign \LDST_internal_op 7'0100110 - end - sync init - end - process $group_3 - assign \LDST_in1_sel 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11010 - assign \LDST_in1_sel 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11011 - assign \LDST_in1_sel 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00001 - assign \LDST_in1_sel 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \LDST_in1_sel 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11001 - assign \LDST_in1_sel 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01011 - assign \LDST_in1_sel 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01010 - assign \LDST_in1_sel 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11000 - assign \LDST_in1_sel 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11110 - assign \LDST_in1_sel 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11111 - assign \LDST_in1_sel 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00101 - assign \LDST_in1_sel 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00100 - assign \LDST_in1_sel 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11101 - assign \LDST_in1_sel 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11100 - assign \LDST_in1_sel 3'010 - end - sync init - end - process $group_4 - assign \LDST_in2_sel 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11010 - assign \LDST_in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11011 - assign \LDST_in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00001 - assign \LDST_in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \LDST_in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11001 - assign \LDST_in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01011 - assign \LDST_in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01010 - assign \LDST_in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11000 - assign \LDST_in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11110 - assign \LDST_in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11111 - assign \LDST_in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00101 - assign \LDST_in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00100 - assign \LDST_in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11101 - assign \LDST_in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11100 - assign \LDST_in2_sel 4'0001 - end - sync init - end - process $group_5 - assign \LDST_cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11010 - assign \LDST_cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11011 - assign \LDST_cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00001 - assign \LDST_cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \LDST_cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11001 - assign \LDST_cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01011 - assign \LDST_cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01010 - assign \LDST_cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11000 - assign \LDST_cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11110 - assign \LDST_cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11111 - assign \LDST_cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00101 - assign \LDST_cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00100 - assign \LDST_cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11101 - assign \LDST_cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11100 - assign \LDST_cr_in 3'000 - end - sync init - end - process $group_6 - assign \LDST_cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11010 - assign \LDST_cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11011 - assign \LDST_cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00001 - assign \LDST_cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \LDST_cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11001 - assign \LDST_cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01011 - assign \LDST_cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01010 - assign \LDST_cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11000 - assign \LDST_cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11110 - assign \LDST_cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11111 - assign \LDST_cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00101 - assign \LDST_cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00100 - assign \LDST_cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11101 - assign \LDST_cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11100 - assign \LDST_cr_out 3'000 - end - sync init - end - process $group_7 - assign \LDST_ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11010 - assign \LDST_ldst_len 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11011 - assign \LDST_ldst_len 4'1000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00001 - assign \LDST_ldst_len 4'1000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \LDST_ldst_len 4'1000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11001 - assign \LDST_ldst_len 4'0010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01011 - assign \LDST_ldst_len 4'0100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01010 - assign \LDST_ldst_len 4'0100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11000 - assign \LDST_ldst_len 4'0100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11110 - assign \LDST_ldst_len 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11111 - assign \LDST_ldst_len 4'1000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00101 - assign \LDST_ldst_len 4'1000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00100 - assign \LDST_ldst_len 4'1000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11101 - assign \LDST_ldst_len 4'0010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11100 - assign \LDST_ldst_len 4'0100 - end - sync init - end - process $group_8 - assign \LDST_upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11010 - assign \LDST_upd 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11011 - assign \LDST_upd 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00001 - assign \LDST_upd 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \LDST_upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11001 - assign \LDST_upd 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01011 - assign \LDST_upd 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01010 - assign \LDST_upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11000 - assign \LDST_upd 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11110 - assign \LDST_upd 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11111 - assign \LDST_upd 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00101 - assign \LDST_upd 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00100 - assign \LDST_upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11101 - assign \LDST_upd 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11100 - assign \LDST_upd 2'10 - end - sync init - end - process $group_9 - assign \LDST_rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11010 - assign \LDST_rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11011 - assign \LDST_rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00001 - assign \LDST_rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \LDST_rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11001 - assign \LDST_rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01011 - assign \LDST_rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01010 - assign \LDST_rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11000 - assign \LDST_rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11110 - assign \LDST_rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11111 - assign \LDST_rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00101 - assign \LDST_rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00100 - assign \LDST_rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11101 - assign \LDST_rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11100 - assign \LDST_rc_sel 2'00 - end - sync init - end - process $group_10 - assign \LDST_br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11010 - assign \LDST_br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11011 - assign \LDST_br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00001 - assign \LDST_br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \LDST_br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11001 - assign \LDST_br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01011 - assign \LDST_br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01010 - assign \LDST_br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11000 - assign \LDST_br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11110 - assign \LDST_br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11111 - assign \LDST_br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00101 - assign \LDST_br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00100 - assign \LDST_br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11101 - assign \LDST_br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11100 - assign \LDST_br 1'0 - end - sync init - end - process $group_11 - assign \LDST_sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11010 - assign \LDST_sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11011 - assign \LDST_sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00001 - assign \LDST_sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \LDST_sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11001 - assign \LDST_sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01011 - assign \LDST_sgn_ext 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01010 - assign \LDST_sgn_ext 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11000 - assign \LDST_sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11110 - assign \LDST_sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11111 - assign \LDST_sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00101 - assign \LDST_sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00100 - assign \LDST_sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11101 - assign \LDST_sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11100 - assign \LDST_sgn_ext 1'0 - end - sync init - end - process $group_12 - assign \LDST_is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11010 - assign \LDST_is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11011 - assign \LDST_is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00001 - assign \LDST_is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \LDST_is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11001 - assign \LDST_is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01011 - assign \LDST_is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01010 - assign \LDST_is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11000 - assign \LDST_is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11110 - assign \LDST_is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11111 - assign \LDST_is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00101 - assign \LDST_is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00100 - assign \LDST_is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11101 - assign \LDST_is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11100 - assign \LDST_is_32b 1'0 - end - sync init - end - process $group_13 - assign \LDST_sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11010 - assign \LDST_sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11011 - assign \LDST_sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00001 - assign \LDST_sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \LDST_sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11001 - assign \LDST_sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01011 - assign \LDST_sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01010 - assign \LDST_sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11000 - assign \LDST_sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11110 - assign \LDST_sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11111 - assign \LDST_sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00101 - assign \LDST_sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00100 - assign \LDST_sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11101 - assign \LDST_sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11100 - assign \LDST_sgn 1'0 - end - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.dec_LDST.dec.LDST_dec31.LDST_dec_sub23" -module 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\enum_value_0100 "is4B" - attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 4 output 7 \LDST_ldst_len - attribute \enum_base_type "LDSTMode" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "update" - attribute \enum_value_10 "cix" - attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 2 output 8 \LDST_upd - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 2 output 9 \LDST_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 output 10 \LDST_br - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 output 11 \LDST_sgn_ext - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 output 12 \LDST_is_32b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 output 13 \LDST_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:308" - wire width 5 \opcode_switch - process $group_0 - assign \opcode_switch 5'00000 - assign \opcode_switch \opcode_in [10:6] - sync init - end - process $group_1 - assign \LDST_function_unit 11'00000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00011 - assign \LDST_function_unit 11'00000000100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00010 - assign \LDST_function_unit 11'00000000100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01011 - assign \LDST_function_unit 11'00000000100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01010 - assign \LDST_function_unit 11'00000000100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01001 - assign \LDST_function_unit 11'00000000100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01000 - assign \LDST_function_unit 11'00000000100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00001 - assign \LDST_function_unit 11'00000000100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \LDST_function_unit 11'00000000100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00111 - assign \LDST_function_unit 11'00000000100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00110 - assign \LDST_function_unit 11'00000000100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01101 - assign \LDST_function_unit 11'00000000100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01100 - assign \LDST_function_unit 11'00000000100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00101 - assign \LDST_function_unit 11'00000000100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00100 - assign \LDST_function_unit 11'00000000100 - end - sync init - end - process $group_2 - assign \LDST_internal_op 7'0000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00011 - assign \LDST_internal_op 7'0100101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00010 - assign \LDST_internal_op 7'0100101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01011 - assign \LDST_internal_op 7'0100101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01010 - assign \LDST_internal_op 7'0100101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01001 - assign \LDST_internal_op 7'0100101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01000 - assign \LDST_internal_op 7'0100101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00001 - assign \LDST_internal_op 7'0100101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \LDST_internal_op 7'0100101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00111 - assign \LDST_internal_op 7'0100110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00110 - assign \LDST_internal_op 7'0100110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01101 - assign \LDST_internal_op 7'0100110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01100 - assign \LDST_internal_op 7'0100110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00101 - assign \LDST_internal_op 7'0100110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00100 - assign \LDST_internal_op 7'0100110 - end - sync init - end - process $group_3 - assign \LDST_in1_sel 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00011 - assign \LDST_in1_sel 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00010 - assign \LDST_in1_sel 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01011 - assign \LDST_in1_sel 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01010 - assign \LDST_in1_sel 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01001 - assign \LDST_in1_sel 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01000 - assign \LDST_in1_sel 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00001 - assign \LDST_in1_sel 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \LDST_in1_sel 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00111 - assign \LDST_in1_sel 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00110 - assign \LDST_in1_sel 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01101 - assign \LDST_in1_sel 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01100 - assign \LDST_in1_sel 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00101 - assign \LDST_in1_sel 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00100 - assign \LDST_in1_sel 3'010 - end - sync init - end - process $group_4 - assign \LDST_in2_sel 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00011 - assign \LDST_in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00010 - assign \LDST_in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01011 - assign \LDST_in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01010 - assign \LDST_in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01001 - assign \LDST_in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01000 - assign \LDST_in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00001 - assign \LDST_in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \LDST_in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00111 - assign \LDST_in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00110 - assign \LDST_in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01101 - assign \LDST_in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01100 - assign \LDST_in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00101 - assign \LDST_in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00100 - assign \LDST_in2_sel 4'0001 - end - sync init - end - process $group_5 - assign \LDST_cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00011 - assign \LDST_cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00010 - assign \LDST_cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01011 - assign \LDST_cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01010 - assign \LDST_cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01001 - assign \LDST_cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01000 - assign \LDST_cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00001 - assign \LDST_cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \LDST_cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00111 - assign \LDST_cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00110 - assign \LDST_cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01101 - assign \LDST_cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01100 - assign \LDST_cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00101 - assign \LDST_cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00100 - assign \LDST_cr_in 3'000 - end - sync init - end - process $group_6 - assign \LDST_cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00011 - assign \LDST_cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00010 - assign \LDST_cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01011 - assign \LDST_cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01010 - assign \LDST_cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01001 - assign \LDST_cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01000 - assign \LDST_cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00001 - assign \LDST_cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \LDST_cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00111 - assign \LDST_cr_out 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00110 - assign \LDST_cr_out 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01101 - assign \LDST_cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01100 - assign \LDST_cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00101 - assign \LDST_cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00100 - assign \LDST_cr_out 3'000 - end - sync init - end - process $group_7 - assign \LDST_ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00011 - assign \LDST_ldst_len 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00010 - assign \LDST_ldst_len 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01011 - assign \LDST_ldst_len 4'0010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01010 - assign \LDST_ldst_len 4'0010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01001 - assign \LDST_ldst_len 4'0010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01000 - assign \LDST_ldst_len 4'0010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00001 - assign \LDST_ldst_len 4'0100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \LDST_ldst_len 4'0100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00111 - assign \LDST_ldst_len 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00110 - assign \LDST_ldst_len 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01101 - assign \LDST_ldst_len 4'0010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01100 - assign \LDST_ldst_len 4'0010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00101 - assign \LDST_ldst_len 4'0100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00100 - assign \LDST_ldst_len 4'0100 - end - sync init - end - process $group_8 - assign \LDST_upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00011 - assign \LDST_upd 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00010 - assign \LDST_upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01011 - assign \LDST_upd 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01010 - assign \LDST_upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01001 - assign \LDST_upd 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01000 - assign \LDST_upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00001 - assign \LDST_upd 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \LDST_upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00111 - assign \LDST_upd 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00110 - assign \LDST_upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01101 - assign \LDST_upd 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01100 - assign \LDST_upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00101 - assign \LDST_upd 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00100 - assign \LDST_upd 2'00 - end - sync init - end - process $group_9 - assign \LDST_rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00011 - assign \LDST_rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00010 - assign \LDST_rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01011 - assign \LDST_rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01010 - assign \LDST_rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01001 - assign \LDST_rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01000 - assign \LDST_rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00001 - assign \LDST_rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \LDST_rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00111 - assign \LDST_rc_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00110 - assign \LDST_rc_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01101 - assign \LDST_rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01100 - assign \LDST_rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00101 - assign \LDST_rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00100 - assign \LDST_rc_sel 2'00 - end - sync init - end - process $group_10 - assign \LDST_br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00011 - assign \LDST_br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00010 - assign \LDST_br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01011 - assign \LDST_br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01010 - assign \LDST_br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01001 - assign \LDST_br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01000 - assign \LDST_br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00001 - assign \LDST_br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \LDST_br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00111 - assign \LDST_br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00110 - assign \LDST_br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01101 - assign \LDST_br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01100 - assign \LDST_br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00101 - assign \LDST_br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00100 - assign \LDST_br 1'0 - end - sync init - end - process $group_11 - assign \LDST_sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00011 - assign \LDST_sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00010 - assign \LDST_sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01011 - assign \LDST_sgn_ext 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01010 - assign \LDST_sgn_ext 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01001 - assign \LDST_sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01000 - assign \LDST_sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00001 - assign \LDST_sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \LDST_sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00111 - assign \LDST_sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00110 - assign \LDST_sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01101 - assign \LDST_sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01100 - assign \LDST_sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00101 - assign \LDST_sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00100 - assign \LDST_sgn_ext 1'0 - end - sync init - end - process $group_12 - assign \LDST_is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00011 - assign \LDST_is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00010 - assign \LDST_is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01011 - assign \LDST_is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01010 - assign \LDST_is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01001 - assign \LDST_is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01000 - assign \LDST_is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00001 - assign \LDST_is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \LDST_is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00111 - assign \LDST_is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00110 - assign \LDST_is_32b 1'0 - attribute \src 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attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src 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\enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 7 \LDST_internal_op$28 - process $group_21 - assign \LDST_internal_op 7'0000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:315" - switch \opc_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01010 - assign \LDST_internal_op \LDST_internal_op$15 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'11100 - assign \LDST_internal_op \LDST_internal_op$16 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'00000 - assign \LDST_internal_op \LDST_internal_op$17 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'11010 - assign \LDST_internal_op \LDST_internal_op$18 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10011 - assign \LDST_internal_op \LDST_internal_op$19 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10110 - assign \LDST_internal_op \LDST_dec_sub22_LDST_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01001 - assign \LDST_internal_op \LDST_internal_op$20 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01011 - assign \LDST_internal_op \LDST_internal_op$21 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'11011 - assign \LDST_internal_op \LDST_internal_op$22 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01111 - assign \LDST_internal_op \LDST_internal_op$23 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10100 - assign \LDST_internal_op \LDST_dec_sub20_LDST_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10101 - assign \LDST_internal_op \LDST_dec_sub21_LDST_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10111 - assign \LDST_internal_op \LDST_dec_sub23_LDST_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10000 - assign \LDST_internal_op \LDST_internal_op$24 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10010 - assign \LDST_internal_op \LDST_internal_op$25 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01000 - assign \LDST_internal_op \LDST_internal_op$26 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'11000 - assign \LDST_internal_op \LDST_internal_op$27 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'00100 - assign \LDST_internal_op \LDST_internal_op$28 - end - sync init - end - attribute \enum_base_type "In1Sel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "RA" - attribute \enum_value_010 "RA_OR_ZERO" - attribute \enum_value_011 "SPR" - attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \LDST_in1_sel$29 - attribute \enum_base_type "In1Sel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "RA" - attribute \enum_value_010 "RA_OR_ZERO" - attribute \enum_value_011 "SPR" - attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \LDST_in1_sel$30 - attribute \enum_base_type "In1Sel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "RA" - attribute \enum_value_010 "RA_OR_ZERO" - attribute \enum_value_011 "SPR" - attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \LDST_in1_sel$31 - attribute \enum_base_type "In1Sel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "RA" - attribute \enum_value_010 "RA_OR_ZERO" - attribute \enum_value_011 "SPR" - attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \LDST_in1_sel$32 - attribute \enum_base_type "In1Sel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "RA" - attribute \enum_value_010 "RA_OR_ZERO" - attribute \enum_value_011 "SPR" - attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \LDST_in1_sel$33 - attribute \enum_base_type "In1Sel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "RA" - attribute \enum_value_010 "RA_OR_ZERO" - attribute \enum_value_011 "SPR" - attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \LDST_in1_sel$34 - attribute \enum_base_type "In1Sel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "RA" - attribute \enum_value_010 "RA_OR_ZERO" - attribute \enum_value_011 "SPR" - attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \LDST_in1_sel$35 - attribute \enum_base_type "In1Sel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "RA" - attribute \enum_value_010 "RA_OR_ZERO" - attribute \enum_value_011 "SPR" - attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \LDST_in1_sel$36 - attribute \enum_base_type "In1Sel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "RA" - attribute \enum_value_010 "RA_OR_ZERO" - attribute \enum_value_011 "SPR" - attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \LDST_in1_sel$37 - attribute \enum_base_type "In1Sel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "RA" - attribute \enum_value_010 "RA_OR_ZERO" - attribute \enum_value_011 "SPR" - attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \LDST_in1_sel$38 - attribute \enum_base_type "In1Sel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "RA" - attribute \enum_value_010 "RA_OR_ZERO" - attribute \enum_value_011 "SPR" - attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \LDST_in1_sel$39 - attribute \enum_base_type "In1Sel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "RA" - attribute \enum_value_010 "RA_OR_ZERO" - attribute \enum_value_011 "SPR" - attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \LDST_in1_sel$40 - attribute \enum_base_type "In1Sel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "RA" - attribute \enum_value_010 "RA_OR_ZERO" - attribute \enum_value_011 "SPR" - attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \LDST_in1_sel$41 - attribute \enum_base_type "In1Sel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "RA" - attribute \enum_value_010 "RA_OR_ZERO" - attribute \enum_value_011 "SPR" - attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \LDST_in1_sel$42 - process $group_22 - assign \LDST_in1_sel 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:315" - switch \opc_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01010 - assign \LDST_in1_sel \LDST_in1_sel$29 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'11100 - assign \LDST_in1_sel \LDST_in1_sel$30 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'00000 - assign \LDST_in1_sel \LDST_in1_sel$31 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'11010 - assign \LDST_in1_sel \LDST_in1_sel$32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10011 - assign \LDST_in1_sel \LDST_in1_sel$33 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10110 - assign \LDST_in1_sel \LDST_dec_sub22_LDST_in1_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01001 - assign \LDST_in1_sel \LDST_in1_sel$34 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01011 - assign \LDST_in1_sel \LDST_in1_sel$35 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'11011 - assign \LDST_in1_sel \LDST_in1_sel$36 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01111 - assign \LDST_in1_sel \LDST_in1_sel$37 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10100 - assign \LDST_in1_sel \LDST_dec_sub20_LDST_in1_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10101 - assign \LDST_in1_sel \LDST_dec_sub21_LDST_in1_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10111 - assign \LDST_in1_sel \LDST_dec_sub23_LDST_in1_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10000 - assign \LDST_in1_sel \LDST_in1_sel$38 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10010 - assign \LDST_in1_sel \LDST_in1_sel$39 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01000 - assign \LDST_in1_sel \LDST_in1_sel$40 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'11000 - assign \LDST_in1_sel \LDST_in1_sel$41 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'00100 - assign \LDST_in1_sel \LDST_in1_sel$42 - end - sync init - end - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 4 \LDST_in2_sel$43 - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 4 \LDST_in2_sel$44 - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 4 \LDST_in2_sel$45 - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 4 \LDST_in2_sel$46 - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 4 \LDST_in2_sel$47 - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 4 \LDST_in2_sel$48 - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 4 \LDST_in2_sel$49 - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 4 \LDST_in2_sel$50 - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 4 \LDST_in2_sel$51 - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 4 \LDST_in2_sel$52 - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 4 \LDST_in2_sel$53 - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 4 \LDST_in2_sel$54 - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 4 \LDST_in2_sel$55 - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 4 \LDST_in2_sel$56 - process $group_23 - assign \LDST_in2_sel 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:315" - switch \opc_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01010 - assign \LDST_in2_sel \LDST_in2_sel$43 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'11100 - assign \LDST_in2_sel \LDST_in2_sel$44 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'00000 - assign \LDST_in2_sel \LDST_in2_sel$45 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'11010 - assign \LDST_in2_sel \LDST_in2_sel$46 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10011 - assign \LDST_in2_sel \LDST_in2_sel$47 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10110 - assign \LDST_in2_sel \LDST_dec_sub22_LDST_in2_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01001 - assign \LDST_in2_sel \LDST_in2_sel$48 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01011 - assign \LDST_in2_sel \LDST_in2_sel$49 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'11011 - assign \LDST_in2_sel \LDST_in2_sel$50 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01111 - assign \LDST_in2_sel \LDST_in2_sel$51 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10100 - assign \LDST_in2_sel \LDST_dec_sub20_LDST_in2_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10101 - assign \LDST_in2_sel \LDST_dec_sub21_LDST_in2_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10111 - assign \LDST_in2_sel \LDST_dec_sub23_LDST_in2_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10000 - assign \LDST_in2_sel \LDST_in2_sel$52 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10010 - assign \LDST_in2_sel \LDST_in2_sel$53 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01000 - assign \LDST_in2_sel \LDST_in2_sel$54 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'11000 - assign \LDST_in2_sel \LDST_in2_sel$55 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'00100 - assign \LDST_in2_sel \LDST_in2_sel$56 - end - sync init - end - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \LDST_cr_in$57 - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \LDST_cr_in$58 - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \LDST_cr_in$59 - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \LDST_cr_in$60 - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \LDST_cr_in$61 - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \LDST_cr_in$62 - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \LDST_cr_in$63 - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \LDST_cr_in$64 - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \LDST_cr_in$65 - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \LDST_cr_in$66 - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \LDST_cr_in$67 - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \LDST_cr_in$68 - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \LDST_cr_in$69 - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \LDST_cr_in$70 - process $group_24 - assign \LDST_cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:315" - switch \opc_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01010 - assign \LDST_cr_in \LDST_cr_in$57 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'11100 - assign \LDST_cr_in \LDST_cr_in$58 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'00000 - assign \LDST_cr_in \LDST_cr_in$59 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'11010 - assign \LDST_cr_in \LDST_cr_in$60 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10011 - assign \LDST_cr_in \LDST_cr_in$61 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10110 - assign \LDST_cr_in \LDST_dec_sub22_LDST_cr_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01001 - assign \LDST_cr_in \LDST_cr_in$62 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01011 - assign \LDST_cr_in \LDST_cr_in$63 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'11011 - assign \LDST_cr_in \LDST_cr_in$64 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01111 - assign \LDST_cr_in \LDST_cr_in$65 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10100 - assign \LDST_cr_in \LDST_dec_sub20_LDST_cr_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10101 - assign \LDST_cr_in \LDST_dec_sub21_LDST_cr_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10111 - assign \LDST_cr_in \LDST_dec_sub23_LDST_cr_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10000 - assign \LDST_cr_in \LDST_cr_in$66 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10010 - assign \LDST_cr_in \LDST_cr_in$67 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01000 - assign \LDST_cr_in \LDST_cr_in$68 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'11000 - assign \LDST_cr_in \LDST_cr_in$69 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'00100 - assign \LDST_cr_in \LDST_cr_in$70 - end - sync init - end - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \LDST_cr_out$71 - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \LDST_cr_out$72 - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \LDST_cr_out$73 - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \LDST_cr_out$74 - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \LDST_cr_out$75 - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \LDST_cr_out$76 - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \LDST_cr_out$77 - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \LDST_cr_out$78 - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \LDST_cr_out$79 - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \LDST_cr_out$80 - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \LDST_cr_out$81 - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \LDST_cr_out$82 - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \LDST_cr_out$83 - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \LDST_cr_out$84 - process $group_25 - assign \LDST_cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:315" - switch \opc_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01010 - assign \LDST_cr_out \LDST_cr_out$71 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'11100 - assign \LDST_cr_out \LDST_cr_out$72 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'00000 - assign \LDST_cr_out \LDST_cr_out$73 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'11010 - assign \LDST_cr_out \LDST_cr_out$74 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10011 - assign \LDST_cr_out \LDST_cr_out$75 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10110 - assign \LDST_cr_out \LDST_dec_sub22_LDST_cr_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01001 - assign \LDST_cr_out \LDST_cr_out$76 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01011 - assign \LDST_cr_out \LDST_cr_out$77 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'11011 - assign \LDST_cr_out \LDST_cr_out$78 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01111 - assign \LDST_cr_out \LDST_cr_out$79 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10100 - assign \LDST_cr_out \LDST_dec_sub20_LDST_cr_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10101 - assign \LDST_cr_out \LDST_dec_sub21_LDST_cr_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10111 - assign \LDST_cr_out \LDST_dec_sub23_LDST_cr_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10000 - assign \LDST_cr_out \LDST_cr_out$80 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10010 - assign \LDST_cr_out \LDST_cr_out$81 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01000 - assign \LDST_cr_out \LDST_cr_out$82 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'11000 - assign \LDST_cr_out \LDST_cr_out$83 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'00100 - assign \LDST_cr_out \LDST_cr_out$84 - end - sync init - end - attribute \enum_base_type "LdstLen" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "is1B" - attribute \enum_value_0010 "is2B" - attribute \enum_value_0100 "is4B" - attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 4 \LDST_ldst_len$85 - attribute \enum_base_type "LdstLen" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "is1B" - attribute \enum_value_0010 "is2B" - attribute \enum_value_0100 "is4B" - attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 4 \LDST_ldst_len$86 - attribute \enum_base_type "LdstLen" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "is1B" - attribute \enum_value_0010 "is2B" - attribute \enum_value_0100 "is4B" - attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 4 \LDST_ldst_len$87 - attribute \enum_base_type "LdstLen" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "is1B" - attribute \enum_value_0010 "is2B" - attribute \enum_value_0100 "is4B" - attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 4 \LDST_ldst_len$88 - attribute \enum_base_type "LdstLen" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "is1B" - attribute \enum_value_0010 "is2B" - attribute \enum_value_0100 "is4B" - attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 4 \LDST_ldst_len$89 - attribute \enum_base_type "LdstLen" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "is1B" - attribute \enum_value_0010 "is2B" - attribute \enum_value_0100 "is4B" - attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 4 \LDST_ldst_len$90 - attribute \enum_base_type "LdstLen" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "is1B" - attribute \enum_value_0010 "is2B" - attribute \enum_value_0100 "is4B" - attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 4 \LDST_ldst_len$91 - attribute \enum_base_type "LdstLen" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "is1B" - attribute \enum_value_0010 "is2B" - attribute \enum_value_0100 "is4B" - attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 4 \LDST_ldst_len$92 - attribute \enum_base_type "LdstLen" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "is1B" - attribute \enum_value_0010 "is2B" - attribute \enum_value_0100 "is4B" - attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 4 \LDST_ldst_len$93 - attribute \enum_base_type "LdstLen" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "is1B" - attribute \enum_value_0010 "is2B" - attribute \enum_value_0100 "is4B" - attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 4 \LDST_ldst_len$94 - attribute \enum_base_type "LdstLen" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "is1B" - attribute \enum_value_0010 "is2B" - attribute \enum_value_0100 "is4B" - attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 4 \LDST_ldst_len$95 - attribute \enum_base_type "LdstLen" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "is1B" - attribute \enum_value_0010 "is2B" - attribute \enum_value_0100 "is4B" - attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 4 \LDST_ldst_len$96 - attribute \enum_base_type "LdstLen" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "is1B" - attribute \enum_value_0010 "is2B" - attribute \enum_value_0100 "is4B" - attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 4 \LDST_ldst_len$97 - attribute \enum_base_type "LdstLen" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "is1B" - attribute \enum_value_0010 "is2B" - attribute \enum_value_0100 "is4B" - attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 4 \LDST_ldst_len$98 - process $group_26 - assign \LDST_ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:315" - switch \opc_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01010 - assign \LDST_ldst_len \LDST_ldst_len$85 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'11100 - assign \LDST_ldst_len \LDST_ldst_len$86 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'00000 - assign \LDST_ldst_len \LDST_ldst_len$87 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'11010 - assign \LDST_ldst_len \LDST_ldst_len$88 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10011 - assign \LDST_ldst_len \LDST_ldst_len$89 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10110 - assign \LDST_ldst_len \LDST_dec_sub22_LDST_ldst_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01001 - assign \LDST_ldst_len \LDST_ldst_len$90 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01011 - assign \LDST_ldst_len \LDST_ldst_len$91 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'11011 - assign \LDST_ldst_len \LDST_ldst_len$92 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01111 - assign \LDST_ldst_len \LDST_ldst_len$93 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10100 - assign \LDST_ldst_len \LDST_dec_sub20_LDST_ldst_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10101 - assign \LDST_ldst_len \LDST_dec_sub21_LDST_ldst_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10111 - assign \LDST_ldst_len \LDST_dec_sub23_LDST_ldst_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10000 - assign \LDST_ldst_len \LDST_ldst_len$94 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10010 - assign \LDST_ldst_len \LDST_ldst_len$95 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01000 - assign \LDST_ldst_len \LDST_ldst_len$96 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'11000 - assign \LDST_ldst_len \LDST_ldst_len$97 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'00100 - assign \LDST_ldst_len \LDST_ldst_len$98 - end - sync init - end - attribute \enum_base_type "LDSTMode" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "update" - attribute \enum_value_10 "cix" - attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 2 \LDST_upd$99 - attribute \enum_base_type "LDSTMode" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "update" - attribute \enum_value_10 "cix" - attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 2 \LDST_upd$100 - attribute \enum_base_type "LDSTMode" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "update" - attribute \enum_value_10 "cix" - attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 2 \LDST_upd$101 - attribute \enum_base_type "LDSTMode" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "update" - attribute \enum_value_10 "cix" - attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 2 \LDST_upd$102 - attribute \enum_base_type "LDSTMode" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "update" - attribute \enum_value_10 "cix" - attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 2 \LDST_upd$103 - attribute \enum_base_type "LDSTMode" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "update" - attribute \enum_value_10 "cix" - attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 2 \LDST_upd$104 - attribute \enum_base_type "LDSTMode" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "update" - attribute \enum_value_10 "cix" - attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 2 \LDST_upd$105 - attribute \enum_base_type "LDSTMode" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "update" - attribute \enum_value_10 "cix" - attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 2 \LDST_upd$106 - attribute \enum_base_type "LDSTMode" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "update" - attribute \enum_value_10 "cix" - attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 2 \LDST_upd$107 - attribute \enum_base_type "LDSTMode" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "update" - attribute \enum_value_10 "cix" - attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 2 \LDST_upd$108 - attribute \enum_base_type "LDSTMode" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "update" - attribute \enum_value_10 "cix" - attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 2 \LDST_upd$109 - attribute \enum_base_type "LDSTMode" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "update" - attribute \enum_value_10 "cix" - attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 2 \LDST_upd$110 - attribute \enum_base_type "LDSTMode" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "update" - attribute \enum_value_10 "cix" - attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 2 \LDST_upd$111 - attribute \enum_base_type "LDSTMode" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "update" - attribute \enum_value_10 "cix" - attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 2 \LDST_upd$112 - process $group_27 - assign \LDST_upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:315" - switch \opc_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01010 - assign \LDST_upd \LDST_upd$99 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'11100 - assign \LDST_upd \LDST_upd$100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'00000 - assign \LDST_upd \LDST_upd$101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'11010 - assign \LDST_upd \LDST_upd$102 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10011 - assign \LDST_upd \LDST_upd$103 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10110 - assign \LDST_upd \LDST_dec_sub22_LDST_upd - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01001 - assign \LDST_upd \LDST_upd$104 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01011 - assign \LDST_upd \LDST_upd$105 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'11011 - assign \LDST_upd \LDST_upd$106 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01111 - assign \LDST_upd \LDST_upd$107 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10100 - assign \LDST_upd \LDST_dec_sub20_LDST_upd - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10101 - assign \LDST_upd \LDST_dec_sub21_LDST_upd - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10111 - assign \LDST_upd \LDST_dec_sub23_LDST_upd - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10000 - assign \LDST_upd \LDST_upd$108 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10010 - assign \LDST_upd \LDST_upd$109 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01000 - assign \LDST_upd \LDST_upd$110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'11000 - assign \LDST_upd \LDST_upd$111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'00100 - assign \LDST_upd \LDST_upd$112 - end - sync init - end - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 2 \LDST_rc_sel$113 - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 2 \LDST_rc_sel$114 - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 2 \LDST_rc_sel$115 - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 2 \LDST_rc_sel$116 - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 2 \LDST_rc_sel$117 - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 2 \LDST_rc_sel$118 - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 2 \LDST_rc_sel$119 - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 2 \LDST_rc_sel$120 - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 2 \LDST_rc_sel$121 - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 2 \LDST_rc_sel$122 - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 2 \LDST_rc_sel$123 - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 2 \LDST_rc_sel$124 - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 2 \LDST_rc_sel$125 - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 2 \LDST_rc_sel$126 - process $group_28 - assign \LDST_rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:315" - switch \opc_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01010 - assign \LDST_rc_sel \LDST_rc_sel$113 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'11100 - assign \LDST_rc_sel \LDST_rc_sel$114 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'00000 - assign \LDST_rc_sel \LDST_rc_sel$115 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'11010 - assign \LDST_rc_sel \LDST_rc_sel$116 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10011 - assign \LDST_rc_sel \LDST_rc_sel$117 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10110 - assign \LDST_rc_sel \LDST_dec_sub22_LDST_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01001 - assign \LDST_rc_sel \LDST_rc_sel$118 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01011 - assign \LDST_rc_sel \LDST_rc_sel$119 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'11011 - assign \LDST_rc_sel \LDST_rc_sel$120 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01111 - assign \LDST_rc_sel \LDST_rc_sel$121 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10100 - assign \LDST_rc_sel \LDST_dec_sub20_LDST_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10101 - assign \LDST_rc_sel \LDST_dec_sub21_LDST_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10111 - assign \LDST_rc_sel \LDST_dec_sub23_LDST_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10000 - assign \LDST_rc_sel \LDST_rc_sel$122 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10010 - assign \LDST_rc_sel \LDST_rc_sel$123 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01000 - assign \LDST_rc_sel \LDST_rc_sel$124 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'11000 - assign \LDST_rc_sel \LDST_rc_sel$125 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'00100 - assign \LDST_rc_sel \LDST_rc_sel$126 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \LDST_br$127 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \LDST_br$128 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \LDST_br$129 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \LDST_br$130 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \LDST_br$131 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \LDST_br$132 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \LDST_br$133 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \LDST_br$134 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \LDST_br$135 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \LDST_br$136 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \LDST_br$137 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \LDST_br$138 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \LDST_br$139 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \LDST_br$140 - process $group_29 - assign \LDST_br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:315" - switch \opc_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01010 - assign \LDST_br \LDST_br$127 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'11100 - assign \LDST_br \LDST_br$128 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'00000 - assign \LDST_br \LDST_br$129 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'11010 - assign \LDST_br \LDST_br$130 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10011 - assign \LDST_br \LDST_br$131 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10110 - assign \LDST_br \LDST_dec_sub22_LDST_br - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01001 - assign \LDST_br \LDST_br$132 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01011 - assign \LDST_br \LDST_br$133 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'11011 - assign \LDST_br \LDST_br$134 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01111 - assign \LDST_br \LDST_br$135 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10100 - assign \LDST_br \LDST_dec_sub20_LDST_br - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10101 - assign \LDST_br \LDST_dec_sub21_LDST_br - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10111 - assign \LDST_br \LDST_dec_sub23_LDST_br - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10000 - assign \LDST_br \LDST_br$136 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10010 - assign \LDST_br \LDST_br$137 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01000 - assign \LDST_br \LDST_br$138 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'11000 - assign \LDST_br \LDST_br$139 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'00100 - assign \LDST_br \LDST_br$140 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \LDST_sgn_ext$141 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \LDST_sgn_ext$142 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \LDST_sgn_ext$143 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \LDST_sgn_ext$144 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \LDST_sgn_ext$145 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \LDST_sgn_ext$146 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \LDST_sgn_ext$147 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \LDST_sgn_ext$148 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \LDST_sgn_ext$149 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \LDST_sgn_ext$150 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \LDST_sgn_ext$151 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \LDST_sgn_ext$152 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \LDST_sgn_ext$153 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \LDST_sgn_ext$154 - process $group_30 - assign \LDST_sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:315" - switch \opc_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01010 - assign \LDST_sgn_ext \LDST_sgn_ext$141 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'11100 - assign \LDST_sgn_ext \LDST_sgn_ext$142 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'00000 - assign \LDST_sgn_ext \LDST_sgn_ext$143 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'11010 - assign \LDST_sgn_ext \LDST_sgn_ext$144 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10011 - assign \LDST_sgn_ext \LDST_sgn_ext$145 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10110 - assign \LDST_sgn_ext \LDST_dec_sub22_LDST_sgn_ext - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01001 - assign \LDST_sgn_ext \LDST_sgn_ext$146 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01011 - assign \LDST_sgn_ext \LDST_sgn_ext$147 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'11011 - assign \LDST_sgn_ext \LDST_sgn_ext$148 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01111 - assign \LDST_sgn_ext \LDST_sgn_ext$149 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10100 - assign \LDST_sgn_ext \LDST_dec_sub20_LDST_sgn_ext - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10101 - assign \LDST_sgn_ext \LDST_dec_sub21_LDST_sgn_ext - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10111 - assign \LDST_sgn_ext \LDST_dec_sub23_LDST_sgn_ext - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10000 - assign \LDST_sgn_ext \LDST_sgn_ext$150 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10010 - assign \LDST_sgn_ext \LDST_sgn_ext$151 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01000 - assign \LDST_sgn_ext \LDST_sgn_ext$152 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'11000 - assign \LDST_sgn_ext \LDST_sgn_ext$153 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'00100 - assign \LDST_sgn_ext \LDST_sgn_ext$154 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \LDST_is_32b$155 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \LDST_is_32b$156 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \LDST_is_32b$157 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \LDST_is_32b$158 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire 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"/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10110 - assign \LDST_is_32b \LDST_dec_sub22_LDST_is_32b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01001 - assign \LDST_is_32b \LDST_is_32b$160 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01011 - assign \LDST_is_32b \LDST_is_32b$161 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'11011 - assign \LDST_is_32b \LDST_is_32b$162 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01111 - assign \LDST_is_32b \LDST_is_32b$163 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10100 - assign \LDST_is_32b \LDST_dec_sub20_LDST_is_32b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10101 - assign \LDST_is_32b \LDST_dec_sub21_LDST_is_32b - attribute \src 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"/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 11 \LDST_function_unit$1 - attribute \enum_base_type "Function" - attribute \enum_value_00000000000 "NONE" - attribute \enum_value_00000000010 "ALU" - attribute \enum_value_00000000100 "LDST" - attribute \enum_value_00000001000 "SHIFT_ROT" - attribute \enum_value_00000010000 "LOGICAL" - attribute \enum_value_00000100000 "BRANCH" - attribute \enum_value_00001000000 "CR" - attribute \enum_value_00010000000 "TRAP" - attribute \enum_value_00100000000 "MUL" - attribute \enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 11 \LDST_function_unit$2 - process $group_6 - assign \LDST_function_unit 11'00000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'010011 - assign \LDST_function_unit \LDST_function_unit$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'011110 - assign \LDST_function_unit \LDST_function_unit$2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'011111 - assign \LDST_function_unit \LDST_dec31_LDST_function_unit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'111010 - assign \LDST_function_unit \LDST_dec58_LDST_function_unit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'111110 - assign \LDST_function_unit \LDST_dec62_LDST_function_unit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'100010 - assign \LDST_function_unit 11'00000000100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'100011 - assign \LDST_function_unit 11'00000000100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'101010 - assign \LDST_function_unit 11'00000000100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'101011 - assign \LDST_function_unit 11'00000000100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'101000 - assign \LDST_function_unit 11'00000000100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'101001 - assign \LDST_function_unit 11'00000000100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'100000 - assign \LDST_function_unit 11'00000000100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'100001 - assign \LDST_function_unit 11'00000000100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'100110 - assign \LDST_function_unit 11'00000000100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'100111 - assign \LDST_function_unit 11'00000000100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'101100 - assign \LDST_function_unit 11'00000000100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'101101 - assign \LDST_function_unit 11'00000000100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'100100 - assign \LDST_function_unit 11'00000000100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'100101 - assign \LDST_function_unit 11'00000000100 - end - sync init - end - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 7 \LDST_internal_op$3 - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 7 \LDST_internal_op$4 - process $group_7 - assign \LDST_internal_op 7'0000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'010011 - assign \LDST_internal_op \LDST_internal_op$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'011110 - assign \LDST_internal_op \LDST_internal_op$4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'011111 - assign \LDST_internal_op \LDST_dec31_LDST_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'111010 - assign \LDST_internal_op \LDST_dec58_LDST_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'111110 - assign \LDST_internal_op \LDST_dec62_LDST_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'100010 - assign \LDST_internal_op 7'0100101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'100011 - assign \LDST_internal_op 7'0100101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'101010 - assign \LDST_internal_op 7'0100101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'101011 - assign \LDST_internal_op 7'0100101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'101000 - assign \LDST_internal_op 7'0100101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'101001 - assign \LDST_internal_op 7'0100101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'100000 - assign \LDST_internal_op 7'0100101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'100001 - assign \LDST_internal_op 7'0100101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'100110 - assign \LDST_internal_op 7'0100110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'100111 - assign \LDST_internal_op 7'0100110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'101100 - assign \LDST_internal_op 7'0100110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'101101 - assign \LDST_internal_op 7'0100110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'100100 - assign \LDST_internal_op 7'0100110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'100101 - assign \LDST_internal_op 7'0100110 - end - sync init - end - attribute \enum_base_type "In1Sel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "RA" - attribute \enum_value_010 "RA_OR_ZERO" - attribute \enum_value_011 "SPR" - attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \LDST_in1_sel$5 - attribute \enum_base_type "In1Sel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "RA" - attribute \enum_value_010 "RA_OR_ZERO" - attribute \enum_value_011 "SPR" - attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \LDST_in1_sel$6 - process $group_8 - assign \LDST_in1_sel 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'010011 - assign \LDST_in1_sel \LDST_in1_sel$5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'011110 - assign \LDST_in1_sel \LDST_in1_sel$6 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'011111 - assign \LDST_in1_sel \LDST_dec31_LDST_in1_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'111010 - assign \LDST_in1_sel \LDST_dec58_LDST_in1_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'111110 - assign \LDST_in1_sel \LDST_dec62_LDST_in1_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'100010 - assign \LDST_in1_sel 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'100011 - assign \LDST_in1_sel 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'101010 - assign \LDST_in1_sel 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'101011 - assign \LDST_in1_sel 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'101000 - assign \LDST_in1_sel 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'101001 - assign \LDST_in1_sel 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'100000 - assign \LDST_in1_sel 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'100001 - assign \LDST_in1_sel 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'100110 - assign \LDST_in1_sel 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'100111 - assign \LDST_in1_sel 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'101100 - assign \LDST_in1_sel 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'101101 - assign \LDST_in1_sel 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'100100 - assign \LDST_in1_sel 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'100101 - assign \LDST_in1_sel 3'010 - end - sync init - end - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 4 \LDST_in2_sel$7 - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 4 \LDST_in2_sel$8 - process $group_9 - assign \LDST_in2_sel 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'010011 - assign \LDST_in2_sel \LDST_in2_sel$7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'011110 - assign \LDST_in2_sel \LDST_in2_sel$8 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'011111 - assign \LDST_in2_sel \LDST_dec31_LDST_in2_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'111010 - assign \LDST_in2_sel \LDST_dec58_LDST_in2_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'111110 - assign \LDST_in2_sel \LDST_dec62_LDST_in2_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'100010 - assign \LDST_in2_sel 4'0011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'100011 - assign \LDST_in2_sel 4'0011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'101010 - assign \LDST_in2_sel 4'0011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'101011 - assign \LDST_in2_sel 4'0011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'101000 - assign \LDST_in2_sel 4'0011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'101001 - assign \LDST_in2_sel 4'0011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'100000 - assign \LDST_in2_sel 4'0011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'100001 - assign \LDST_in2_sel 4'0011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'100110 - assign \LDST_in2_sel 4'0011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'100111 - assign \LDST_in2_sel 4'0011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'101100 - assign \LDST_in2_sel 4'0011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'101101 - assign \LDST_in2_sel 4'0011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'100100 - assign \LDST_in2_sel 4'0011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'100101 - assign \LDST_in2_sel 4'0011 - end - sync init - end - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \LDST_cr_in$9 - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \LDST_cr_in$10 - process $group_10 - assign \LDST_cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'010011 - assign \LDST_cr_in \LDST_cr_in$9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'011110 - assign \LDST_cr_in \LDST_cr_in$10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'011111 - assign \LDST_cr_in \LDST_dec31_LDST_cr_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'111010 - assign \LDST_cr_in \LDST_dec58_LDST_cr_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'111110 - assign \LDST_cr_in \LDST_dec62_LDST_cr_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'100010 - assign \LDST_cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'100011 - assign \LDST_cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'101010 - assign \LDST_cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'101011 - assign \LDST_cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'101000 - assign \LDST_cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'101001 - assign \LDST_cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'100000 - assign \LDST_cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'100001 - assign \LDST_cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'100110 - assign \LDST_cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'100111 - assign \LDST_cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'101100 - assign \LDST_cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'101101 - assign \LDST_cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'100100 - assign \LDST_cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'100101 - assign \LDST_cr_in 3'000 - end - sync init - end - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \LDST_cr_out$11 - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \LDST_cr_out$12 - process $group_11 - assign \LDST_cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'010011 - assign \LDST_cr_out \LDST_cr_out$11 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'011110 - assign \LDST_cr_out \LDST_cr_out$12 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'011111 - assign \LDST_cr_out \LDST_dec31_LDST_cr_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'111010 - assign \LDST_cr_out \LDST_dec58_LDST_cr_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'111110 - assign \LDST_cr_out \LDST_dec62_LDST_cr_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'100010 - assign \LDST_cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'100011 - assign \LDST_cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'101010 - assign \LDST_cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'101011 - assign \LDST_cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'101000 - assign \LDST_cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'101001 - assign \LDST_cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'100000 - assign \LDST_cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'100001 - assign \LDST_cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'100110 - assign \LDST_cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'100111 - assign \LDST_cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'101100 - assign \LDST_cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'101101 - assign \LDST_cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'100100 - assign \LDST_cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'100101 - assign \LDST_cr_out 3'000 - end - sync init - end - attribute \enum_base_type "LdstLen" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "is1B" - attribute \enum_value_0010 "is2B" - attribute \enum_value_0100 "is4B" - attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 4 \LDST_ldst_len$13 - attribute \enum_base_type "LdstLen" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "is1B" - attribute \enum_value_0010 "is2B" - attribute \enum_value_0100 "is4B" - attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 4 \LDST_ldst_len$14 - process $group_12 - assign \LDST_ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'010011 - assign \LDST_ldst_len \LDST_ldst_len$13 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'011110 - assign \LDST_ldst_len \LDST_ldst_len$14 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'011111 - assign \LDST_ldst_len \LDST_dec31_LDST_ldst_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'111010 - assign \LDST_ldst_len \LDST_dec58_LDST_ldst_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'111110 - assign \LDST_ldst_len \LDST_dec62_LDST_ldst_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'100010 - assign \LDST_ldst_len 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'100011 - assign \LDST_ldst_len 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'101010 - assign \LDST_ldst_len 4'0010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'101011 - assign \LDST_ldst_len 4'0010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'101000 - assign \LDST_ldst_len 4'0010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'101001 - assign \LDST_ldst_len 4'0010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'100000 - assign \LDST_ldst_len 4'0100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'100001 - assign \LDST_ldst_len 4'0100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'100110 - assign \LDST_ldst_len 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'100111 - assign \LDST_ldst_len 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'101100 - assign \LDST_ldst_len 4'0010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'101101 - assign \LDST_ldst_len 4'0010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'100100 - assign \LDST_ldst_len 4'0100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'100101 - assign \LDST_ldst_len 4'0100 - end - sync init - end - attribute \enum_base_type "LDSTMode" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "update" - attribute \enum_value_10 "cix" - attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 2 \LDST_upd$15 - attribute \enum_base_type "LDSTMode" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "update" - attribute \enum_value_10 "cix" - attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 2 \LDST_upd$16 - process $group_13 - assign \LDST_upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'010011 - assign \LDST_upd \LDST_upd$15 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'011110 - assign \LDST_upd \LDST_upd$16 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'011111 - assign \LDST_upd \LDST_dec31_LDST_upd - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'111010 - assign \LDST_upd \LDST_dec58_LDST_upd - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'111110 - assign \LDST_upd \LDST_dec62_LDST_upd - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'100010 - assign \LDST_upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'100011 - assign \LDST_upd 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'101010 - assign \LDST_upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'101011 - assign \LDST_upd 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'101000 - assign \LDST_upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'101001 - assign \LDST_upd 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'100000 - assign \LDST_upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'100001 - assign \LDST_upd 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'100110 - assign \LDST_upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'100111 - assign \LDST_upd 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'101100 - assign \LDST_upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'101101 - assign \LDST_upd 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'100100 - assign \LDST_upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'100101 - assign \LDST_upd 2'01 - end - sync init - end - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 2 \LDST_rc_sel$17 - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 2 \LDST_rc_sel$18 - process $group_14 - assign \LDST_rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'010011 - assign \LDST_rc_sel \LDST_rc_sel$17 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'011110 - assign \LDST_rc_sel \LDST_rc_sel$18 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'011111 - assign \LDST_rc_sel \LDST_dec31_LDST_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'111010 - assign \LDST_rc_sel \LDST_dec58_LDST_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'111110 - assign \LDST_rc_sel \LDST_dec62_LDST_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'100010 - assign \LDST_rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'100011 - assign \LDST_rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'101010 - assign \LDST_rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'101011 - assign \LDST_rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'101000 - assign \LDST_rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'101001 - assign \LDST_rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'100000 - assign \LDST_rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'100001 - assign \LDST_rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'100110 - assign \LDST_rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'100111 - assign \LDST_rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'101100 - assign \LDST_rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'101101 - assign \LDST_rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'100100 - assign \LDST_rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'100101 - assign \LDST_rc_sel 2'00 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \LDST_br$19 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \LDST_br$20 - process $group_15 - assign \LDST_br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'010011 - assign \LDST_br \LDST_br$19 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'011110 - assign \LDST_br \LDST_br$20 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'011111 - assign \LDST_br \LDST_dec31_LDST_br - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'111010 - assign \LDST_br \LDST_dec58_LDST_br - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'111110 - assign \LDST_br \LDST_dec62_LDST_br - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'100010 - assign \LDST_br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'100011 - assign \LDST_br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'101010 - assign \LDST_br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'101011 - assign \LDST_br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'101000 - assign \LDST_br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'101001 - assign \LDST_br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'100000 - assign \LDST_br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'100001 - assign \LDST_br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'100110 - assign \LDST_br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'100111 - assign \LDST_br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'101100 - assign \LDST_br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'101101 - assign \LDST_br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'100100 - assign \LDST_br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'100101 - assign \LDST_br 1'0 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \LDST_sgn_ext$21 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \LDST_sgn_ext$22 - process $group_16 - assign \LDST_sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'010011 - assign \LDST_sgn_ext \LDST_sgn_ext$21 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'011110 - assign \LDST_sgn_ext \LDST_sgn_ext$22 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'011111 - assign \LDST_sgn_ext \LDST_dec31_LDST_sgn_ext - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'111010 - assign \LDST_sgn_ext \LDST_dec58_LDST_sgn_ext - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'111110 - assign \LDST_sgn_ext \LDST_dec62_LDST_sgn_ext - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'100010 - assign \LDST_sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'100011 - assign \LDST_sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'101010 - assign \LDST_sgn_ext 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'101011 - assign \LDST_sgn_ext 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'101000 - assign \LDST_sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'101001 - assign \LDST_sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'100000 - assign \LDST_sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'100001 - assign \LDST_sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'100110 - assign \LDST_sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'100111 - assign \LDST_sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'101100 - assign \LDST_sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'101101 - assign \LDST_sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'100100 - assign \LDST_sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'100101 - assign \LDST_sgn_ext 1'0 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \LDST_is_32b$23 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \LDST_is_32b$24 - process $group_17 - assign \LDST_is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'010011 - assign \LDST_is_32b \LDST_is_32b$23 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'011110 - assign \LDST_is_32b \LDST_is_32b$24 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'011111 - assign \LDST_is_32b \LDST_dec31_LDST_is_32b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'111010 - assign \LDST_is_32b \LDST_dec58_LDST_is_32b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'111110 - assign \LDST_is_32b \LDST_dec62_LDST_is_32b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'100010 - assign \LDST_is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'100011 - assign \LDST_is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'101010 - assign \LDST_is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'101011 - assign \LDST_is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'101000 - assign \LDST_is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'101001 - assign \LDST_is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'100000 - assign \LDST_is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'100001 - assign \LDST_is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'100110 - assign \LDST_is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'100111 - assign \LDST_is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'101100 - assign \LDST_is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'101101 - assign \LDST_is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'100100 - assign \LDST_is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'100101 - assign \LDST_is_32b 1'0 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \LDST_sgn$25 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \LDST_sgn$26 - process $group_18 - assign \LDST_sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'010011 - assign \LDST_sgn \LDST_sgn$25 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'011110 - assign \LDST_sgn \LDST_sgn$26 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'011111 - assign \LDST_sgn \LDST_dec31_LDST_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'111010 - assign \LDST_sgn \LDST_dec58_LDST_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'111110 - assign \LDST_sgn \LDST_dec62_LDST_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'100010 - assign \LDST_sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'100011 - assign \LDST_sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'101010 - assign \LDST_sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'101011 - assign \LDST_sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'101000 - assign \LDST_sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'101001 - assign \LDST_sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'100000 - assign \LDST_sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'100001 - assign \LDST_sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'100110 - assign \LDST_sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'100111 - assign \LDST_sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'101100 - assign \LDST_sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'101101 - assign \LDST_sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'100100 - assign \LDST_sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'100101 - assign \LDST_sgn 1'0 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:308" - wire width 32 \opcode_switch$27 - process $group_19 - assign \opcode_switch$27 32'00000000000000000000000000000000 - assign \opcode_switch$27 \opcode_in - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:418" - wire width 32 $28 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:418" - cell $mux $29 - parameter \WIDTH 32 - connect \A \raw_opcode_in - connect \B { \raw_opcode_in [7:0] \raw_opcode_in [15:8] \raw_opcode_in [23:16] \raw_opcode_in [31:24] } - connect \S \bigendian - connect \Y $28 - end - process $group_20 - assign \opcode_in 32'00000000000000000000000000000000 - assign \opcode_in $28 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 5 \LDST_RS - process $group_21 - assign \LDST_RS 5'00000 - assign \LDST_RS { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 5 \LDST_RT - process $group_22 - assign \LDST_RT 5'00000 - assign \LDST_RT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - process $group_23 - assign \LDST_RA 5'00000 - assign \LDST_RA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 5 \LDST_RB - process $group_24 - assign \LDST_RB 5'00000 - assign \LDST_RB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - process $group_25 - assign \LDST_SI 16'0000000000000000 - assign \LDST_SI { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] \opcode_in [0] } - sync init - end - process $group_26 - assign \LDST_UI 16'0000000000000000 - assign \LDST_UI { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] \opcode_in [0] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 1 \LDST_L - process $group_27 - assign \LDST_L 1'0 - assign \LDST_L { \opcode_in [21] } - sync init - end - process $group_28 - assign \LDST_SH32 5'00000 - assign \LDST_SH32 { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - process $group_29 - assign \LDST_sh 6'000000 - assign \LDST_sh { \opcode_in [1] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 5 \LDST_MB32 - process $group_30 - assign \LDST_MB32 5'00000 - assign \LDST_MB32 { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 5 \LDST_ME32 - process $group_31 - assign \LDST_ME32 5'00000 - assign \LDST_ME32 { \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] } - sync init - end - process $group_32 - assign \LDST_LI 24'000000000000000000000000 - assign \LDST_LI { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 1 \LDST_LK - process $group_33 - assign \LDST_LK 1'0 - assign \LDST_LK { \opcode_in [0] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 1 \LDST_AA - process $group_34 - assign \LDST_AA 1'0 - assign \LDST_AA { \opcode_in [1] } - sync init - end - process $group_35 - assign \LDST_Rc 1'0 - assign \LDST_Rc { \opcode_in [0] } - sync init - end - process $group_36 - assign \LDST_OE 1'0 - assign \LDST_OE { \opcode_in [10] } - sync init - end - process $group_37 - assign \LDST_BD 14'00000000000000 - assign \LDST_BD { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 3 \LDST_BF - process $group_38 - assign \LDST_BF 3'000 - assign \LDST_BF { \opcode_in [25] \opcode_in [24] \opcode_in [23] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 10 \LDST_CR - process $group_39 - assign \LDST_CR 10'0000000000 - assign \LDST_CR { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] } - sync init - end - process $group_40 - assign \LDST_BB 5'00000 - assign \LDST_BB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - process $group_41 - assign \LDST_BA 5'00000 - assign \LDST_BA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - process $group_42 - assign \LDST_BT 5'00000 - assign \LDST_BT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - process $group_43 - assign \LDST_FXM 8'00000000 - assign \LDST_FXM { \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 5 \LDST_BO - process $group_44 - assign \LDST_BO 5'00000 - assign \LDST_BO { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - process $group_45 - assign \LDST_BI 5'00000 - assign \LDST_BI { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 2 \LDST_BH - process $group_46 - assign \LDST_BH 2'00 - assign \LDST_BH { \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 16 \LDST_D - process $group_47 - assign \LDST_D 16'0000000000000000 - assign \LDST_D { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] \opcode_in [0] } - sync init - end - process $group_48 - assign \LDST_DS 14'00000000000000 - assign \LDST_DS { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 5 \LDST_TO - process $group_49 - assign \LDST_TO 5'00000 - assign \LDST_TO { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - process $group_50 - assign \LDST_BC 5'00000 - assign \LDST_BC { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 5 \LDST_SH - process $group_51 - assign \LDST_SH 5'00000 - assign \LDST_SH { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 5 \LDST_ME - process $group_52 - assign \LDST_ME 5'00000 - assign \LDST_ME { \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 5 \LDST_MB - process $group_53 - assign \LDST_MB 5'00000 - assign \LDST_MB { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 10 \LDST_SPR - process $group_54 - assign \LDST_SPR 10'0000000000 - assign \LDST_SPR { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \X_A - process $group_55 - assign \X_A 1'0 - assign \X_A { \opcode_in [25] } - sync init - end - process $group_56 - assign \X_BF 3'000 - assign \X_BF { \opcode_in [25] \opcode_in [24] \opcode_in [23] } - sync init - end - process $group_57 - assign \X_BFA 3'000 - assign \X_BFA { \opcode_in [20] \opcode_in [19] \opcode_in [18] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \X_BO - process $group_58 - assign \X_BO 5'00000 - assign \X_BO { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 4 \X_CT - process $group_59 - assign \X_CT 4'0000 - assign \X_CT { \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 7 \X_DCMX - process $group_60 - assign \X_DCMX 7'0000000 - assign \X_DCMX { \opcode_in [22] \opcode_in [21] \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 3 \X_DRM - process $group_61 - assign \X_DRM 3'000 - assign \X_DRM { \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \X_E - process $group_62 - assign \X_E 1'0 - assign \X_E { \opcode_in [15] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 4 \X_E_1 - process $group_63 - assign \X_E_1 4'0000 - assign \X_E_1 { \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 2 \X_EO - process $group_64 - assign \X_EO 2'00 - assign \X_EO { \opcode_in [20] \opcode_in [19] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \X_EO_1 - process $group_65 - assign \X_EO_1 5'00000 - assign \X_EO_1 { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \X_EX - process $group_66 - assign \X_EX 1'0 - assign \X_EX { \opcode_in [0] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \X_FC - process $group_67 - assign \X_FC 5'00000 - assign \X_FC { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \X_FRA - process $group_68 - assign \X_FRA 5'00000 - assign \X_FRA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \X_FRAp - process $group_69 - assign \X_FRAp 5'00000 - assign \X_FRAp { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \X_FRB - process $group_70 - assign \X_FRB 5'00000 - assign \X_FRB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \X_FRBp - process $group_71 - assign \X_FRBp 5'00000 - assign \X_FRBp { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \X_FRS - process $group_72 - assign \X_FRS 5'00000 - assign \X_FRS { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \X_FRSp - process $group_73 - assign \X_FRSp 5'00000 - assign \X_FRSp { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \X_FRT - process $group_74 - assign \X_FRT 5'00000 - assign \X_FRT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \X_FRTp - process $group_75 - assign \X_FRTp 5'00000 - assign \X_FRTp { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 3 \X_IH - process $group_76 - assign \X_IH 3'000 - assign \X_IH { \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 8 \X_IMM8 - process $group_77 - assign \X_IMM8 8'00000000 - assign \X_IMM8 { \opcode_in [18] \opcode_in [17] \opcode_in [16] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 2 \X_L2 - process $group_78 - assign \X_L2 2'00 - assign \X_L2 { \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \X_L - process $group_79 - assign \X_L 1'0 - assign \X_L { \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \X_L1 - process $group_80 - assign \X_L1 1'0 - assign \X_L1 { \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 2 \X_L3 - process $group_81 - assign \X_L3 2'00 - assign \X_L3 { \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \X_MO - process $group_82 - assign \X_MO 5'00000 - assign \X_MO { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \X_NB - process $group_83 - assign \X_NB 5'00000 - assign \X_NB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \X_PRS - process $group_84 - assign \X_PRS 1'0 - assign \X_PRS { \opcode_in [17] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \X_R - process $group_85 - assign \X_R 1'0 - assign \X_R { \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \X_R_1 - process $group_86 - assign \X_R_1 1'0 - assign \X_R_1 { \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \X_RA - process $group_87 - assign \X_RA 5'00000 - assign \X_RA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \X_RB - process $group_88 - assign \X_RB 5'00000 - assign \X_RB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \X_Rc - process $group_89 - assign \X_Rc 1'0 - assign \X_Rc { \opcode_in [0] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 2 \X_RIC - process $group_90 - assign \X_RIC 2'00 - assign \X_RIC { \opcode_in [19] \opcode_in [18] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 2 \X_RM - process $group_91 - assign \X_RM 2'00 - assign \X_RM { \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \X_RO - process $group_92 - assign \X_RO 1'0 - assign \X_RO { \opcode_in [0] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \X_RS - process $group_93 - assign \X_RS 5'00000 - assign \X_RS { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \X_RSp - process $group_94 - assign \X_RSp 5'00000 - assign \X_RSp { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \X_RT - process $group_95 - assign \X_RT 5'00000 - assign \X_RT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \X_RTp - process $group_96 - assign \X_RTp 5'00000 - assign \X_RTp { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \X_S - process $group_97 - assign \X_S 5'00000 - assign \X_S { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \X_SH - process $group_98 - assign \X_SH 5'00000 - assign \X_SH { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \X_SI - process $group_99 - assign \X_SI 5'00000 - assign \X_SI { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 2 \X_SP - process $group_100 - assign \X_SP 2'00 - assign \X_SP { \opcode_in [20] \opcode_in [19] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 4 \X_SR - process $group_101 - assign \X_SR 4'0000 - assign \X_SR { \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \X_SX - process $group_102 - assign \X_SX 1'0 - assign \X_SX { \opcode_in [0] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 6 \X_SX_S - process $group_103 - assign \X_SX_S 6'000000 - assign \X_SX_S { \opcode_in [0] \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \X_T - process $group_104 - assign \X_T 5'00000 - assign \X_T { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 10 \X_TBR - process $group_105 - assign \X_TBR 10'0000000000 - assign \X_TBR { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \X_TH - process $group_106 - assign \X_TH 5'00000 - assign \X_TH { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \X_TO - process $group_107 - assign \X_TO 5'00000 - assign \X_TO { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \X_TX - process $group_108 - assign \X_TX 1'0 - assign \X_TX { \opcode_in [0] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 6 \X_TX_T - process $group_109 - assign \X_TX_T 6'000000 - assign \X_TX_T { \opcode_in [0] \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 4 \X_U - process $group_110 - assign \X_U 4'0000 - assign \X_U { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \X_UIM - process $group_111 - assign \X_UIM 5'00000 - assign \X_UIM { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \X_VRS - process $group_112 - assign \X_VRS 5'00000 - assign \X_VRS { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \X_VRT - process $group_113 - assign \X_VRT 5'00000 - assign \X_VRT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \X_W - process $group_114 - assign \X_W 1'0 - assign \X_W { \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 2 \X_WC - process $group_115 - assign \X_WC 2'00 - assign \X_WC { \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 10 \X_XO - process $group_116 - assign \X_XO 10'0000000000 - assign \X_XO { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 8 \X_XO_1 - process $group_117 - assign \X_XO_1 8'00000000 - assign \X_XO_1 { \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \B_AA - process $group_118 - assign \B_AA 1'0 - assign \B_AA { \opcode_in [1] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 14 \B_BD - process $group_119 - assign \B_BD 14'00000000000000 - assign \B_BD { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \B_BI - process $group_120 - assign \B_BI 5'00000 - assign \B_BI { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \B_BO - process $group_121 - assign \B_BO 5'00000 - assign \B_BO { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \B_LK - process $group_122 - assign \B_LK 1'0 - assign \B_LK { \opcode_in [0] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \I_AA - process $group_123 - assign \I_AA 1'0 - assign \I_AA { \opcode_in [1] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 24 \I_LI - process $group_124 - assign \I_LI 24'000000000000000000000000 - assign \I_LI { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \I_LK - process $group_125 - assign \I_LK 1'0 - assign \I_LK { \opcode_in [0] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \XX3_AX - process $group_126 - assign \XX3_AX 1'0 - assign \XX3_AX { \opcode_in [2] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \XX3_A - process $group_127 - assign \XX3_A 5'00000 - assign \XX3_A { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 6 \XX3_AX_A - process $group_128 - assign \XX3_AX_A 6'000000 - assign \XX3_AX_A { \opcode_in [2] \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 3 \XX3_BF - process $group_129 - assign \XX3_BF 3'000 - assign \XX3_BF { \opcode_in [25] \opcode_in [24] \opcode_in [23] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \XX3_BX - process $group_130 - assign \XX3_BX 1'0 - assign \XX3_BX { \opcode_in [1] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \XX3_B - process $group_131 - assign \XX3_B 5'00000 - assign \XX3_B { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 6 \XX3_BX_B - process $group_132 - assign \XX3_BX_B 6'000000 - assign \XX3_BX_B { \opcode_in [1] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 2 \XX3_DM - process $group_133 - assign \XX3_DM 2'00 - assign \XX3_DM { \opcode_in [9] \opcode_in [8] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \XX3_Rc - process $group_134 - assign \XX3_Rc 1'0 - assign \XX3_Rc { \opcode_in [10] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 2 \XX3_SHW - process $group_135 - assign \XX3_SHW 2'00 - assign \XX3_SHW { \opcode_in [9] \opcode_in [8] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \XX3_TX - process $group_136 - assign \XX3_TX 1'0 - assign \XX3_TX { \opcode_in [0] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \XX3_T - process $group_137 - assign \XX3_T 5'00000 - assign \XX3_T { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 6 \XX3_TX_T - process $group_138 - assign \XX3_TX_T 6'000000 - assign \XX3_TX_T { \opcode_in [0] \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 4 \XX3_XO - process $group_139 - assign \XX3_XO 4'0000 - assign \XX3_XO { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 8 \XX3_XO_1 - process $group_140 - assign \XX3_XO_1 8'00000000 - assign \XX3_XO_1 { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 9 \XX3_XO_2 - process $group_141 - assign \XX3_XO_2 9'000000000 - assign \XX3_XO_2 { \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \XX4_AX - process $group_142 - assign \XX4_AX 1'0 - assign \XX4_AX { \opcode_in [2] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \XX4_A - process $group_143 - assign \XX4_A 5'00000 - assign \XX4_A { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 6 \XX4_AX_A - process $group_144 - assign \XX4_AX_A 6'000000 - assign \XX4_AX_A { \opcode_in [2] \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \XX4_BX - process $group_145 - assign \XX4_BX 1'0 - assign \XX4_BX { \opcode_in [1] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \XX4_B - process $group_146 - assign \XX4_B 5'00000 - assign \XX4_B { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 6 \XX4_BX_B - process $group_147 - assign \XX4_BX_B 6'000000 - assign \XX4_BX_B { \opcode_in [1] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \XX4_CX - process $group_148 - assign \XX4_CX 1'0 - assign \XX4_CX { \opcode_in [3] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \XX4_C - process $group_149 - assign \XX4_C 5'00000 - assign \XX4_C { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 6 \XX4_CX_C - process $group_150 - assign \XX4_CX_C 6'000000 - assign \XX4_CX_C { \opcode_in [3] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \XX4_TX - process $group_151 - assign \XX4_TX 1'0 - assign \XX4_TX { \opcode_in [0] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \XX4_T - process $group_152 - assign \XX4_T 5'00000 - assign \XX4_T { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 6 \XX4_TX_T - process $group_153 - assign \XX4_TX_T 6'000000 - assign \XX4_TX_T { \opcode_in [0] \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 2 \XX4_XO - process $group_154 - assign \XX4_XO 2'00 - assign \XX4_XO { \opcode_in [5] \opcode_in [4] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \XL_BA - process $group_155 - assign \XL_BA 5'00000 - assign \XL_BA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \XL_BB - process $group_156 - assign \XL_BB 5'00000 - assign \XL_BB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 3 \XL_BF - process $group_157 - assign \XL_BF 3'000 - assign \XL_BF { \opcode_in [25] \opcode_in [24] \opcode_in [23] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 3 \XL_BFA - process $group_158 - assign \XL_BFA 3'000 - assign \XL_BFA { \opcode_in [20] \opcode_in [19] \opcode_in [18] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 2 \XL_BH - process $group_159 - assign \XL_BH 2'00 - assign \XL_BH { \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \XL_BI - process $group_160 - assign \XL_BI 5'00000 - assign \XL_BI { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \XL_BO - process $group_161 - assign \XL_BO 5'00000 - assign \XL_BO { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \XL_BO_1 - process $group_162 - assign \XL_BO_1 5'00000 - assign \XL_BO_1 { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - process $group_163 - assign \XL_BT 5'00000 - assign \XL_BT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \XL_LK - process $group_164 - assign \XL_LK 1'0 - assign \XL_LK { \opcode_in [0] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 15 \XL_OC - process $group_165 - assign \XL_OC 15'000000000000000 - assign \XL_OC { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \XL_S - process $group_166 - assign \XL_S 1'0 - assign \XL_S { \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 10 \XL_XO - process $group_167 - assign \XL_XO 10'0000000000 - assign \XL_XO { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \A_BC - process $group_168 - assign \A_BC 5'00000 - assign \A_BC { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \A_FRA - process $group_169 - assign \A_FRA 5'00000 - assign \A_FRA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \A_FRB - process $group_170 - assign \A_FRB 5'00000 - assign \A_FRB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \A_FRC - process $group_171 - assign \A_FRC 5'00000 - assign \A_FRC { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \A_FRT - process $group_172 - assign \A_FRT 5'00000 - assign \A_FRT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \A_RA - process $group_173 - assign \A_RA 5'00000 - assign \A_RA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \A_RB - process $group_174 - assign \A_RB 5'00000 - assign \A_RB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \A_Rc - process $group_175 - assign \A_Rc 1'0 - assign \A_Rc { \opcode_in [0] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \A_RT - process $group_176 - assign \A_RT 5'00000 - assign \A_RT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \A_XO - process $group_177 - assign \A_XO 5'00000 - assign \A_XO { \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 3 \D_BF - process $group_178 - assign \D_BF 3'000 - assign \D_BF { \opcode_in [25] \opcode_in [24] \opcode_in [23] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 16 \D_D - process $group_179 - assign \D_D 16'0000000000000000 - assign \D_D { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] \opcode_in [0] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \D_FRS - process $group_180 - assign \D_FRS 5'00000 - assign \D_FRS { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \D_FRT - process $group_181 - assign \D_FRT 5'00000 - assign \D_FRT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \D_L - process $group_182 - assign \D_L 1'0 - assign \D_L { \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \D_RA - process $group_183 - assign \D_RA 5'00000 - assign \D_RA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \D_RS - process $group_184 - assign \D_RS 5'00000 - assign \D_RS { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \D_RT - process $group_185 - assign \D_RT 5'00000 - assign \D_RT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 16 \D_SI - process $group_186 - assign \D_SI 16'0000000000000000 - assign \D_SI { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] \opcode_in [0] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \D_TO - process $group_187 - assign \D_TO 5'00000 - assign \D_TO { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 16 \D_UI - process $group_188 - assign \D_UI 16'0000000000000000 - assign \D_UI { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] \opcode_in [0] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 3 \XX2_BF - process $group_189 - assign \XX2_BF 3'000 - assign \XX2_BF { \opcode_in [25] \opcode_in [24] \opcode_in [23] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \XX2_BX - process $group_190 - assign \XX2_BX 1'0 - assign \XX2_BX { \opcode_in [1] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \XX2_B - process $group_191 - assign \XX2_B 5'00000 - assign \XX2_B { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 6 \XX2_BX_B - process $group_192 - assign \XX2_BX_B 6'000000 - assign \XX2_BX_B { \opcode_in [1] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \XX2_dc - process $group_193 - assign \XX2_dc 1'0 - assign \XX2_dc { \opcode_in [6] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \XX2_dm - process $group_194 - assign \XX2_dm 1'0 - assign \XX2_dm { \opcode_in [2] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \XX2_dx - process $group_195 - assign \XX2_dx 5'00000 - assign \XX2_dx { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 7 \XX2_dc_dm_dx - process $group_196 - assign \XX2_dc_dm_dx 7'0000000 - assign \XX2_dc_dm_dx { \opcode_in [6] \opcode_in [2] \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 7 \XX2_DCMX - process $group_197 - assign \XX2_DCMX 7'0000000 - assign \XX2_DCMX { \opcode_in [22] \opcode_in [21] \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \XX2_EO - process $group_198 - assign \XX2_EO 5'00000 - assign \XX2_EO { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \XX2_RT - process $group_199 - assign \XX2_RT 5'00000 - assign \XX2_RT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \XX2_TX - process $group_200 - assign \XX2_TX 1'0 - assign \XX2_TX { \opcode_in [0] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \XX2_T - process $group_201 - assign \XX2_T 5'00000 - assign \XX2_T { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 6 \XX2_TX_T - process $group_202 - assign \XX2_TX_T 6'000000 - assign \XX2_TX_T { \opcode_in [0] \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 4 \XX2_UIM - process $group_203 - assign \XX2_UIM 4'0000 - assign \XX2_UIM { \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 2 \XX2_UIM_1 - process $group_204 - assign \XX2_UIM_1 2'00 - assign \XX2_UIM_1 { \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 7 \XX2_XO - process $group_205 - assign \XX2_XO 7'0000000 - assign \XX2_XO { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [5] \opcode_in [4] \opcode_in [3] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 9 \XX2_XO_1 - process $group_206 - assign \XX2_XO_1 9'000000000 - assign \XX2_XO_1 { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 3 \Z22_BF - process $group_207 - assign \Z22_BF 3'000 - assign \Z22_BF { \opcode_in [25] \opcode_in [24] \opcode_in [23] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 6 \Z22_DCM - process $group_208 - assign \Z22_DCM 6'000000 - assign \Z22_DCM { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 6 \Z22_DGM - process $group_209 - assign \Z22_DGM 6'000000 - assign \Z22_DGM { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \Z22_FRA - process $group_210 - assign \Z22_FRA 5'00000 - assign \Z22_FRA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \Z22_FRAp - process $group_211 - assign \Z22_FRAp 5'00000 - assign \Z22_FRAp { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \Z22_FRT - process $group_212 - assign \Z22_FRT 5'00000 - assign \Z22_FRT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \Z22_FRTp - process $group_213 - assign \Z22_FRTp 5'00000 - assign \Z22_FRTp { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \Z22_Rc - process $group_214 - assign \Z22_Rc 1'0 - assign \Z22_Rc { \opcode_in [0] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 6 \Z22_SH - process $group_215 - assign \Z22_SH 6'000000 - assign \Z22_SH { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 9 \Z22_XO - process $group_216 - assign \Z22_XO 9'000000000 - assign \Z22_XO { \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 3 \EVS_BFA - process $group_217 - assign \EVS_BFA 3'000 - assign \EVS_BFA { \opcode_in [2] \opcode_in [1] \opcode_in [0] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 10 \XFX_BHRBE - process $group_218 - assign \XFX_BHRBE 10'0000000000 - assign \XFX_BHRBE { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \XFX_DUI - process $group_219 - assign \XFX_DUI 5'00000 - assign \XFX_DUI { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 10 \XFX_DUIS - process $group_220 - assign \XFX_DUIS 10'0000000000 - assign \XFX_DUIS { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 8 \XFX_FXM - process $group_221 - assign \XFX_FXM 8'00000000 - assign \XFX_FXM { \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \XFX_RS - process $group_222 - assign \XFX_RS 5'00000 - assign \XFX_RS { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \XFX_RT - process $group_223 - assign \XFX_RT 5'00000 - assign \XFX_RT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 10 \XFX_SPR - process $group_224 - assign \XFX_SPR 10'0000000000 - assign \XFX_SPR { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 10 \XFX_XO - process $group_225 - assign \XFX_XO 10'0000000000 - assign \XFX_XO { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 10 \DX_d0 - process $group_226 - assign \DX_d0 10'0000000000 - assign \DX_d0 { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \DX_d1 - process $group_227 - assign \DX_d1 5'00000 - assign \DX_d1 { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \DX_d2 - process $group_228 - assign \DX_d2 1'0 - assign \DX_d2 { \opcode_in [0] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 16 \DX_d0_d1_d2 - process $group_229 - assign \DX_d0_d1_d2 16'0000000000000000 - assign \DX_d0_d1_d2 { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] \opcode_in [0] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \DX_RT - process $group_230 - assign \DX_RT 5'00000 - assign \DX_RT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \DX_XO - process $group_231 - assign \DX_XO 5'00000 - assign \DX_XO { \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 12 \DQ_DQ - process $group_232 - assign \DQ_DQ 12'000000000000 - assign \DQ_DQ { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 4 \DQ_PT - process $group_233 - assign \DQ_PT 4'0000 - assign \DQ_PT { \opcode_in [3] \opcode_in [2] \opcode_in [1] \opcode_in [0] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \DQ_RA - process $group_234 - assign \DQ_RA 5'00000 - assign \DQ_RA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \DQ_RTp - process $group_235 - assign \DQ_RTp 5'00000 - assign \DQ_RTp { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \DQ_SX - process $group_236 - assign \DQ_SX 1'0 - assign \DQ_SX { \opcode_in [3] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \DQ_S - process $group_237 - assign \DQ_S 5'00000 - assign \DQ_S { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 6 \DQ_SX_S - process $group_238 - assign \DQ_SX_S 6'000000 - assign \DQ_SX_S { \opcode_in [3] \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \DQ_TX - process $group_239 - assign \DQ_TX 1'0 - assign \DQ_TX { \opcode_in [3] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \DQ_T - process $group_240 - assign \DQ_T 5'00000 - assign \DQ_T { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 6 \DQ_TX_T - process $group_241 - assign \DQ_TX_T 6'000000 - assign \DQ_TX_T { \opcode_in [3] \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 3 \DQ_XO - process $group_242 - assign \DQ_XO 3'000 - assign \DQ_XO { \opcode_in [2] \opcode_in [1] \opcode_in [0] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 14 \DS_DS - process $group_243 - assign \DS_DS 14'00000000000000 - assign \DS_DS { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \DS_FRSp - process $group_244 - assign \DS_FRSp 5'00000 - assign \DS_FRSp { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \DS_FRTp - process $group_245 - assign \DS_FRTp 5'00000 - assign \DS_FRTp { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \DS_RA - process $group_246 - assign \DS_RA 5'00000 - assign \DS_RA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \DS_RS - process $group_247 - assign \DS_RS 5'00000 - assign \DS_RS { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \DS_RSp - process $group_248 - assign \DS_RSp 5'00000 - assign \DS_RSp { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \DS_RT - process $group_249 - assign \DS_RT 5'00000 - assign \DS_RT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \DS_VRS - process $group_250 - assign \DS_VRS 5'00000 - assign \DS_VRS { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \DS_VRT - process $group_251 - assign \DS_VRT 5'00000 - assign \DS_VRT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 2 \DS_XO - process $group_252 - assign \DS_XO 2'00 - assign \DS_XO { \opcode_in [1] \opcode_in [0] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \VX_EO - process $group_253 - assign \VX_EO 5'00000 - assign \VX_EO { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \VX_PS - process $group_254 - assign \VX_PS 1'0 - assign \VX_PS { \opcode_in [9] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \VX_RA - process $group_255 - assign \VX_RA 5'00000 - assign \VX_RA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \VX_RT - process $group_256 - assign \VX_RT 5'00000 - assign \VX_RT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \VX_SIM - process $group_257 - assign \VX_SIM 5'00000 - assign \VX_SIM { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \VX_UIM - process $group_258 - assign \VX_UIM 5'00000 - assign \VX_UIM { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 4 \VX_UIM_1 - process $group_259 - assign \VX_UIM_1 4'0000 - assign \VX_UIM_1 { \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 3 \VX_UIM_2 - process $group_260 - assign \VX_UIM_2 3'000 - assign \VX_UIM_2 { \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 2 \VX_UIM_3 - process $group_261 - assign \VX_UIM_3 2'00 - assign \VX_UIM_3 { \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \VX_VRA - process $group_262 - assign \VX_VRA 5'00000 - assign \VX_VRA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \VX_VRB - process $group_263 - assign \VX_VRB 5'00000 - assign \VX_VRB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \VX_VRT - process $group_264 - assign \VX_VRT 5'00000 - assign \VX_VRT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 10 \VX_XO - process $group_265 - assign \VX_XO 10'0000000000 - assign \VX_XO { \opcode_in [10] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] \opcode_in [0] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 11 \VX_XO_1 - process $group_266 - assign \VX_XO_1 11'00000000000 - assign \VX_XO_1 { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] \opcode_in [0] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 8 \XFL_FLM - process $group_267 - assign \XFL_FLM 8'00000000 - assign \XFL_FLM { \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \XFL_FRB - process $group_268 - assign \XFL_FRB 5'00000 - assign \XFL_FRB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \XFL_L - process $group_269 - assign \XFL_L 1'0 - assign \XFL_L { \opcode_in [25] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \XFL_Rc - process $group_270 - assign \XFL_Rc 1'0 - assign \XFL_Rc { \opcode_in [0] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \XFL_W - process $group_271 - assign \XFL_W 1'0 - assign \XFL_W { \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 10 \XFL_XO - process $group_272 - assign \XFL_XO 10'0000000000 - assign \XFL_XO { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \Z23_FRA - process $group_273 - assign \Z23_FRA 5'00000 - assign \Z23_FRA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \Z23_FRAp - process $group_274 - assign \Z23_FRAp 5'00000 - assign \Z23_FRAp { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \Z23_FRB - process $group_275 - assign \Z23_FRB 5'00000 - assign \Z23_FRB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \Z23_FRBp - process $group_276 - assign \Z23_FRBp 5'00000 - assign \Z23_FRBp { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \Z23_FRT - process $group_277 - assign \Z23_FRT 5'00000 - assign \Z23_FRT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \Z23_FRTp - process $group_278 - assign \Z23_FRTp 5'00000 - assign \Z23_FRTp { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \Z23_R - process $group_279 - assign \Z23_R 1'0 - assign \Z23_R { \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \Z23_Rc - process $group_280 - assign \Z23_Rc 1'0 - assign \Z23_Rc { \opcode_in [0] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 2 \Z23_RMC - process $group_281 - assign \Z23_RMC 2'00 - assign \Z23_RMC { \opcode_in [10] \opcode_in [9] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \Z23_TE - process $group_282 - assign \Z23_TE 5'00000 - assign \Z23_TE { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 8 \Z23_XO - process $group_283 - assign \Z23_XO 8'00000000 - assign \Z23_XO { \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \MDS_IB - process $group_284 - assign \MDS_IB 5'00000 - assign \MDS_IB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \MDS_IS - process $group_285 - assign \MDS_IS 5'00000 - assign \MDS_IS { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 6 \MDS_mb - process $group_286 - assign \MDS_mb 6'000000 - assign \MDS_mb { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 6 \MDS_me - process $group_287 - assign \MDS_me 6'000000 - assign \MDS_me { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \MDS_RA - process $group_288 - assign \MDS_RA 5'00000 - assign \MDS_RA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \MDS_RB - process $group_289 - assign \MDS_RB 5'00000 - assign \MDS_RB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \MDS_Rc - process $group_290 - assign \MDS_Rc 1'0 - assign \MDS_Rc { \opcode_in [0] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \MDS_RS - process $group_291 - assign \MDS_RS 5'00000 - assign \MDS_RS { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 4 \MDS_XBI - process $group_292 - assign \MDS_XBI 4'0000 - assign \MDS_XBI { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 4 \MDS_XBI_1 - process $group_293 - assign \MDS_XBI_1 4'0000 - assign \MDS_XBI_1 { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 4 \MDS_XO - process $group_294 - assign \MDS_XO 4'0000 - assign \MDS_XO { \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 7 \SC_LEV - process $group_295 - assign \SC_LEV 7'0000000 - assign \SC_LEV { \opcode_in [11] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \SC_XO - process $group_296 - assign \SC_XO 1'0 - assign \SC_XO { \opcode_in [1] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 2 \SC_XO_1 - process $group_297 - assign \SC_XO_1 2'00 - assign \SC_XO_1 { \opcode_in [1] \opcode_in [0] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \M_MB - process $group_298 - assign \M_MB 5'00000 - assign \M_MB { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \M_ME - process $group_299 - assign \M_ME 5'00000 - assign \M_ME { \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \M_RA - process $group_300 - assign \M_RA 5'00000 - assign \M_RA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \M_RB - process $group_301 - assign \M_RB 5'00000 - assign \M_RB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \M_Rc - process $group_302 - assign \M_Rc 1'0 - assign \M_Rc { \opcode_in [0] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \M_RS - process $group_303 - assign \M_RS 5'00000 - assign \M_RS { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \M_SH - process $group_304 - assign \M_SH 5'00000 - assign \M_SH { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 6 \MD_mb - process $group_305 - assign \MD_mb 6'000000 - assign \MD_mb { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 6 \MD_me - process $group_306 - assign \MD_me 6'000000 - assign \MD_me { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \MD_RA - process $group_307 - assign \MD_RA 5'00000 - assign \MD_RA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \MD_Rc - process $group_308 - assign \MD_Rc 1'0 - assign \MD_Rc { \opcode_in [0] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \MD_RS - process $group_309 - assign \MD_RS 5'00000 - assign \MD_RS { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 6 \MD_sh - process $group_310 - assign \MD_sh 6'000000 - assign \MD_sh { \opcode_in [1] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 3 \MD_XO - process $group_311 - assign \MD_XO 3'000 - assign \MD_XO { \opcode_in [4] \opcode_in [3] \opcode_in [2] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 6 \all_OPCD - process $group_312 - assign \all_OPCD 6'000000 - assign \all_OPCD { \opcode_in [31] \opcode_in [30] \opcode_in [29] \opcode_in [28] \opcode_in [27] \opcode_in [26] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 6 \all_PO - process $group_313 - assign \all_PO 6'000000 - assign \all_PO { \opcode_in [31] \opcode_in [30] \opcode_in [29] \opcode_in [28] \opcode_in [27] \opcode_in [26] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \XO_OE - process $group_314 - assign \XO_OE 1'0 - assign \XO_OE { \opcode_in [10] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \XO_RA - process $group_315 - assign \XO_RA 5'00000 - assign \XO_RA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \XO_RB - process $group_316 - assign \XO_RB 5'00000 - assign \XO_RB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \XO_Rc - process $group_317 - assign \XO_Rc 1'0 - assign \XO_Rc { \opcode_in [0] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \XO_RT - process $group_318 - assign \XO_RT 5'00000 - assign \XO_RT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 9 \XO_XO - process $group_319 - assign \XO_XO 9'000000000 - assign \XO_XO { \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \DQE_RA - process $group_320 - assign \DQE_RA 5'00000 - assign \DQE_RA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \DQE_RT - process $group_321 - assign \DQE_RT 5'00000 - assign \DQE_RT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 2 \DQE_XO - process $group_322 - assign \DQE_XO 2'00 - assign \DQE_XO { \opcode_in [1] \opcode_in [0] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \TX_RA - process $group_323 - assign \TX_RA 5'00000 - assign \TX_RA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \TX_UI - process $group_324 - assign \TX_UI 5'00000 - assign \TX_UI { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 4 \TX_XBI - process $group_325 - assign \TX_XBI 4'0000 - assign \TX_XBI { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 6 \TX_XO - process $group_326 - assign \TX_XO 6'000000 - assign \TX_XO { \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \VA_RA - process $group_327 - assign \VA_RA 5'00000 - assign \VA_RA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \VA_RB - process $group_328 - assign \VA_RB 5'00000 - assign \VA_RB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \VA_RC - process $group_329 - assign \VA_RC 5'00000 - assign \VA_RC { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \VA_RT - process $group_330 - assign \VA_RT 5'00000 - assign \VA_RT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 4 \VA_SHB - process $group_331 - assign \VA_SHB 4'0000 - assign \VA_SHB { \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \VA_VRA - process $group_332 - assign \VA_VRA 5'00000 - assign \VA_VRA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \VA_VRB - process $group_333 - assign \VA_VRB 5'00000 - assign \VA_VRB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \VA_VRC - process $group_334 - assign \VA_VRC 5'00000 - assign \VA_VRC { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \VA_VRT - process $group_335 - assign \VA_VRT 5'00000 - assign \VA_VRT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 6 \VA_XO - process $group_336 - assign \VA_XO 6'000000 - assign \VA_XO { \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] \opcode_in [0] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \XS_RA - process $group_337 - assign \XS_RA 5'00000 - assign \XS_RA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \XS_Rc - process $group_338 - assign \XS_Rc 1'0 - assign \XS_Rc { \opcode_in [0] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \XS_RS - process $group_339 - assign \XS_RS 5'00000 - assign \XS_RS { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 6 \XS_sh - process $group_340 - assign \XS_sh 6'000000 - assign \XS_sh { \opcode_in [1] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 9 \XS_XO - process $group_341 - assign \XS_XO 9'000000000 - assign \XS_XO { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \VC_Rc - process $group_342 - assign \VC_Rc 1'0 - assign \VC_Rc { \opcode_in [10] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \VC_VRA - process $group_343 - assign \VC_VRA 5'00000 - assign \VC_VRA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \VC_VRB - process $group_344 - assign \VC_VRB 5'00000 - assign \VC_VRB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \VC_VRT - process $group_345 - assign \VC_VRT 5'00000 - assign \VC_VRT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 10 \VC_XO - process $group_346 - assign \VC_XO 10'0000000000 - assign \VC_XO { \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] \opcode_in [0] } - sync init - end - connect \LDST_function_unit$1 11'00000000000 - connect \LDST_function_unit$2 11'00000000000 - connect \LDST_internal_op$3 7'0000000 - connect \LDST_internal_op$4 7'0000000 - connect \LDST_in1_sel$5 3'000 - connect \LDST_in1_sel$6 3'000 - connect \LDST_in2_sel$7 4'0000 - connect \LDST_in2_sel$8 4'0000 - connect \LDST_cr_in$9 3'000 - connect \LDST_cr_in$10 3'000 - connect \LDST_cr_out$11 3'000 - connect \LDST_cr_out$12 3'000 - connect \LDST_ldst_len$13 4'0000 - connect \LDST_ldst_len$14 4'0000 - connect \LDST_upd$15 2'00 - connect \LDST_upd$16 2'00 - connect \LDST_rc_sel$17 2'00 - connect \LDST_rc_sel$18 2'00 - connect \LDST_br$19 1'0 - connect \LDST_br$20 1'0 - connect \LDST_sgn_ext$21 1'0 - connect \LDST_sgn_ext$22 1'0 - connect \LDST_is_32b$23 1'0 - connect \LDST_is_32b$24 1'0 - connect \LDST_sgn$25 1'0 - connect \LDST_sgn$26 1'0 -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.dec_LDST.dec_rc" -module \dec_rc$194 - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:404" - wire width 2 input 0 \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 1 \rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 2 \rc_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 1 input 3 \LDST_Rc - process $group_0 - assign \rc 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:413" - switch \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:414" - attribute \nmigen.decoding "RC/2" - case 2'10 - assign \rc \LDST_Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:417" - attribute \nmigen.decoding "ONE/1" - case 2'01 - assign \rc 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:420" - attribute \nmigen.decoding "NONE/0" - case 2'00 - assign \rc 1'0 - end - sync init - end - process $group_1 - assign \rc_ok 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:413" - switch \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:414" - attribute \nmigen.decoding "RC/2" - case 2'10 - assign \rc_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:417" - attribute \nmigen.decoding "ONE/1" - case 2'01 - assign \rc_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:420" - attribute \nmigen.decoding "NONE/0" - case 2'00 - assign \rc_ok 1'1 - end - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.dec_LDST.dec_oe" -module \dec_oe$195 - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:441" - wire width 2 input 0 \sel_in - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 7 input 1 \LDST_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 2 \oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 3 \oe_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 1 input 4 \LDST_OE - process $group_0 - assign \oe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:450" - switch \LDST_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:461" - attribute \nmigen.decoding "OP_MUL_H64/51|OP_MUL_H32/52|OP_EXTS/31|OP_CNTZ/14|OP_SHL/60|OP_SHR/61|OP_RLC/56|OP_LOAD/37|OP_STORE/38|OP_RLCL/57|OP_RLCR/58|OP_EXTSWSLI/32" - case 7'0110011, 7'0110100, 7'0011111, 7'0001110, 7'0111100, 7'0111101, 7'0111000, 7'0100101, 7'0100110, 7'0111001, 7'0111010, 7'0100000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:465" - attribute \nmigen.decoding "" - case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:467" - switch \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:468" - attribute \nmigen.decoding "RC/2" - case 2'10 - assign \oe \LDST_OE - end - end - sync init - end - process $group_1 - assign \oe_ok 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:450" - switch \LDST_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:461" - attribute \nmigen.decoding "OP_MUL_H64/51|OP_MUL_H32/52|OP_EXTS/31|OP_CNTZ/14|OP_SHL/60|OP_SHR/61|OP_RLC/56|OP_LOAD/37|OP_STORE/38|OP_RLCL/57|OP_RLCR/58|OP_EXTSWSLI/32" - case 7'0110011, 7'0110100, 7'0011111, 7'0001110, 7'0111100, 7'0111101, 7'0111000, 7'0100101, 7'0100110, 7'0111001, 7'0111010, 7'0100000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:465" - attribute \nmigen.decoding "" - case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:467" - switch \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:468" - attribute \nmigen.decoding "RC/2" - case 2'10 - assign \oe_ok 1'1 - end - end - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.dec_LDST.dec_cr_in.ppick" -module \ppick$197 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" - wire width 8 input 0 \i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" - wire width 8 output 1 \o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:49" - wire width 8 \ni - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" - wire width 8 $1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" - cell $not $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \Y_WIDTH 8 - connect \A { \i [0] \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] } - connect \Y $1 - end - process $group_0 - assign \ni 8'00000000 - assign \ni $1 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire width 1 \t0 - process $group_1 - assign \t0 1'0 - assign \t0 \i [7] - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire width 1 \t1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire width 1 $3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire width 1 $4 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_bool $5 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A { \i [7] \ni [1] } - connect \Y $4 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $6 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $4 - connect \Y $3 - end - process $group_2 - assign \t1 1'0 - assign \t1 $3 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire width 1 \t2 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire width 1 $7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire width 1 $8 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_bool $9 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A { \i [6] \i [7] \ni [2] } - connect \Y $8 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $10 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $8 - connect \Y $7 - end - process $group_3 - assign \t2 1'0 - assign \t2 $7 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire width 1 \t3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire width 1 $11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire width 1 $12 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_bool $13 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A { \i [5] \i [6] \i [7] \ni [3] } - connect \Y $12 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $14 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $12 - connect \Y $11 - end - process $group_4 - assign \t3 1'0 - assign \t3 $11 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire width 1 \t4 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire width 1 $15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire width 1 $16 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_bool $17 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A { \i [4] \i [5] \i [6] \i [7] \ni [4] } - connect \Y $16 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $18 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $16 - connect \Y $15 - end - process $group_5 - assign \t4 1'0 - assign \t4 $15 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire width 1 \t5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire width 1 $19 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire width 1 $20 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_bool $21 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \Y_WIDTH 1 - connect \A { \i [3] \i [4] \i [5] \i [6] \i [7] \ni [5] } - connect \Y $20 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $22 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $20 - connect \Y $19 - end - process $group_6 - assign \t5 1'0 - assign \t5 $19 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire width 1 \t6 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire width 1 $23 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire width 1 $24 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_bool $25 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A { \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [6] } - connect \Y $24 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $26 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $24 - connect \Y $23 - end - process $group_7 - assign \t6 1'0 - assign \t6 $23 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire width 1 \t7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire width 1 $27 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire width 1 $28 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_bool $29 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A { \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [7] } - connect \Y $28 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $30 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $28 - connect \Y $27 - end - process $group_8 - assign \t7 1'0 - assign \t7 $27 - sync init - end - process $group_9 - assign \o 8'00000000 - assign \o { \t0 \t1 \t2 \t3 \t4 \t5 \t6 \t7 } - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" - wire width 1 \en_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" - wire width 1 $31 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" - cell $reduce_bool $32 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \o - connect \Y $31 - end - process $group_10 - assign \en_o 1'0 - assign \en_o $31 - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.dec_LDST.dec_cr_in" -module \dec_cr_in$196 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:485" - wire width 32 input 0 \insn_in - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:484" - wire width 3 input 1 \sel_in - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 7 input 2 \LDST_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 5 input 3 \LDST_BB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 5 input 4 \LDST_BA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 5 input 5 \LDST_BT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 8 input 6 \LDST_FXM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 5 input 7 \LDST_BI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 5 input 8 \LDST_BC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 3 input 9 \X_BFA - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" - wire width 8 \ppick_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" - wire width 8 \ppick_o - cell \ppick$197 \ppick - connect \i \ppick_i - connect \o \ppick_o - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \cr_bitfield_ok - process $group_0 - assign \cr_bitfield_ok 1'0 - assign \cr_bitfield_ok 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" - switch \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" - attribute \nmigen.decoding "NONE/0" - case 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:505" - attribute \nmigen.decoding "CR0/1" - case 3'001 - assign \cr_bitfield_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:508" - attribute \nmigen.decoding "BI/2" - case 3'010 - assign \cr_bitfield_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:511" - attribute \nmigen.decoding "BFA/3" - case 3'011 - assign \cr_bitfield_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:514" - attribute \nmigen.decoding "BA_BB/4" - case 3'100 - assign \cr_bitfield_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:521" - attribute \nmigen.decoding "BC/5" - case 3'101 - assign \cr_bitfield_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:524" - attribute \nmigen.decoding "WHOLE_REG/6" - case 3'110 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \cr_bitfield_b_ok - process $group_1 - assign \cr_bitfield_b_ok 1'0 - assign \cr_bitfield_b_ok 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" - switch \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" - attribute \nmigen.decoding "NONE/0" - case 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:505" - attribute \nmigen.decoding "CR0/1" - case 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:508" - attribute \nmigen.decoding "BI/2" - case 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:511" - attribute \nmigen.decoding "BFA/3" - case 3'011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:514" - attribute \nmigen.decoding "BA_BB/4" - case 3'100 - assign \cr_bitfield_b_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:521" - attribute \nmigen.decoding "BC/5" - case 3'101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:524" - attribute \nmigen.decoding "WHOLE_REG/6" - case 3'110 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \cr_fxm_ok - process $group_2 - assign \cr_fxm_ok 1'0 - assign \cr_fxm_ok 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" - switch \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" - attribute \nmigen.decoding "NONE/0" - case 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:505" - attribute \nmigen.decoding "CR0/1" - case 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:508" - attribute \nmigen.decoding "BI/2" - case 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:511" - attribute \nmigen.decoding "BFA/3" - case 3'011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:514" - attribute \nmigen.decoding "BA_BB/4" - case 3'100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:521" - attribute \nmigen.decoding "BC/5" - case 3'101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:524" - attribute \nmigen.decoding "WHOLE_REG/6" - case 3'110 - assign \cr_fxm_ok 1'1 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 3 \cr_bitfield - process $group_3 - assign \cr_bitfield 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" - switch \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" - attribute \nmigen.decoding "NONE/0" - case 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:505" - attribute \nmigen.decoding "CR0/1" - case 3'001 - assign \cr_bitfield 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:508" - attribute \nmigen.decoding "BI/2" - case 3'010 - assign \cr_bitfield \LDST_BI [4:2] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:511" - attribute \nmigen.decoding "BFA/3" - case 3'011 - assign \cr_bitfield \X_BFA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:514" - attribute \nmigen.decoding "BA_BB/4" - case 3'100 - assign \cr_bitfield \LDST_BA [4:2] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:521" - attribute \nmigen.decoding "BC/5" - case 3'101 - assign \cr_bitfield \LDST_BC [4:2] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:524" - attribute \nmigen.decoding "WHOLE_REG/6" - case 3'110 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 3 \cr_bitfield_b - process $group_4 - assign \cr_bitfield_b 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" - switch \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" - attribute \nmigen.decoding "NONE/0" - case 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:505" - attribute \nmigen.decoding "CR0/1" - case 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:508" - attribute \nmigen.decoding "BI/2" - case 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:511" - attribute \nmigen.decoding "BFA/3" - case 3'011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:514" - attribute \nmigen.decoding "BA_BB/4" - case 3'100 - assign \cr_bitfield_b \LDST_BB [4:2] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:521" - attribute \nmigen.decoding "BC/5" - case 3'101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:524" - attribute \nmigen.decoding "WHOLE_REG/6" - case 3'110 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 3 \cr_bitfield_o - process $group_5 - assign \cr_bitfield_o 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" - switch \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" - attribute \nmigen.decoding "NONE/0" - case 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:505" - attribute \nmigen.decoding "CR0/1" - case 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:508" - attribute \nmigen.decoding "BI/2" - case 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:511" - attribute \nmigen.decoding "BFA/3" - case 3'011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:514" - attribute \nmigen.decoding "BA_BB/4" - case 3'100 - assign \cr_bitfield_o \LDST_BT [4:2] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:521" - attribute \nmigen.decoding "BC/5" - case 3'101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:524" - attribute \nmigen.decoding "WHOLE_REG/6" - case 3'110 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \cr_bitfield_o_ok - process $group_6 - assign \cr_bitfield_o_ok 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" - switch \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" - attribute \nmigen.decoding "NONE/0" - case 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:505" - attribute \nmigen.decoding "CR0/1" - case 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:508" - attribute \nmigen.decoding "BI/2" - case 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:511" - attribute \nmigen.decoding "BFA/3" - case 3'011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:514" - attribute \nmigen.decoding "BA_BB/4" - case 3'100 - assign \cr_bitfield_o_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:521" - attribute \nmigen.decoding "BC/5" - case 3'101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:524" - attribute \nmigen.decoding "WHOLE_REG/6" - case 3'110 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:526" - wire width 1 \move_one - process $group_7 - assign \move_one 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" - switch \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" - attribute \nmigen.decoding "NONE/0" - case 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:505" - attribute \nmigen.decoding "CR0/1" - case 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:508" - attribute \nmigen.decoding "BI/2" - case 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:511" - attribute \nmigen.decoding "BFA/3" - case 3'011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:514" - attribute \nmigen.decoding "BA_BB/4" - case 3'100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:521" - attribute \nmigen.decoding "BC/5" - case 3'101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:524" - attribute \nmigen.decoding "WHOLE_REG/6" - case 3'110 - assign \move_one \insn_in [20] - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" - cell $eq $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A \LDST_internal_op - connect \B 7'0101101 - connect \Y $1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" - wire width 1 $3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" - cell $and $4 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $1 - connect \B \move_one - connect \Y $3 - end - process $group_8 - assign \ppick_i 8'00000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" - switch \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" - attribute \nmigen.decoding "NONE/0" - case 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:505" - attribute \nmigen.decoding "CR0/1" - case 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:508" - attribute \nmigen.decoding "BI/2" - case 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:511" - attribute \nmigen.decoding "BFA/3" - case 3'011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:514" - attribute \nmigen.decoding "BA_BB/4" - case 3'100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:521" - attribute \nmigen.decoding "BC/5" - case 3'101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:524" - attribute \nmigen.decoding "WHOLE_REG/6" - case 3'110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" - switch { $3 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" - case 1'1 - assign \ppick_i \LDST_FXM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532" - case - end - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 8 \cr_fxm - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" - wire width 1 $5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" - cell $eq $6 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A \LDST_internal_op - connect \B 7'0101101 - connect \Y $5 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" - wire width 1 $7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" - cell $and $8 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $5 - connect \B \move_one - connect \Y $7 - end - process $group_9 - assign \cr_fxm 8'00000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" - switch \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" - attribute \nmigen.decoding "NONE/0" - case 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:505" - attribute \nmigen.decoding "CR0/1" - case 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:508" - attribute \nmigen.decoding "BI/2" - case 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:511" - attribute \nmigen.decoding "BFA/3" - case 3'011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:514" - attribute \nmigen.decoding "BA_BB/4" - case 3'100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:521" - attribute \nmigen.decoding "BC/5" - case 3'101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:524" - attribute \nmigen.decoding "WHOLE_REG/6" - case 3'110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" - switch { $7 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" - case 1'1 - assign \cr_fxm \ppick_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532" - case - assign \cr_fxm 8'11111111 - end - end - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.dec_LDST.dec_cr_out.ppick" -module \ppick$199 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" - wire width 8 input 0 \i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" - wire width 1 output 1 \en_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" - wire width 8 output 2 \o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:49" - wire width 8 \ni - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" - wire width 8 $1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" - cell $not $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \Y_WIDTH 8 - connect \A { \i [0] \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] } - connect \Y $1 - end - process $group_0 - assign \ni 8'00000000 - assign \ni $1 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire width 1 \t0 - process $group_1 - assign \t0 1'0 - assign \t0 \i [7] - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire width 1 \t1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire width 1 $3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire width 1 $4 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_bool $5 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A { \i [7] \ni [1] } - connect \Y $4 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $6 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $4 - connect \Y $3 - end - process $group_2 - assign \t1 1'0 - assign \t1 $3 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire width 1 \t2 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire width 1 $7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire width 1 $8 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_bool $9 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A { \i [6] \i [7] \ni [2] } - connect \Y $8 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $10 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $8 - connect \Y $7 - end - process $group_3 - assign \t2 1'0 - assign \t2 $7 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire width 1 \t3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire width 1 $11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire width 1 $12 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_bool $13 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A { \i [5] \i [6] \i [7] \ni [3] } - connect \Y $12 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $14 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $12 - connect \Y $11 - end - process $group_4 - assign \t3 1'0 - assign \t3 $11 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire width 1 \t4 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire width 1 $15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire width 1 $16 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_bool $17 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A { \i [4] \i [5] \i [6] \i [7] \ni [4] } - connect \Y $16 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $18 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $16 - connect \Y $15 - end - process $group_5 - assign \t4 1'0 - assign \t4 $15 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire width 1 \t5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire width 1 $19 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire width 1 $20 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_bool $21 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \Y_WIDTH 1 - connect \A { \i [3] \i [4] \i [5] \i [6] \i [7] \ni [5] } - connect \Y $20 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $22 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $20 - connect \Y $19 - end - process $group_6 - assign \t5 1'0 - assign \t5 $19 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire width 1 \t6 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire width 1 $23 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire width 1 $24 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_bool $25 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A { \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [6] } - connect \Y $24 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $26 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $24 - connect \Y $23 - end - process $group_7 - assign \t6 1'0 - assign \t6 $23 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire width 1 \t7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire width 1 $27 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire width 1 $28 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_bool $29 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A { \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [7] } - connect \Y $28 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $30 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $28 - connect \Y $27 - end - process $group_8 - assign \t7 1'0 - assign \t7 $27 - sync init - end - process $group_9 - assign \o 8'00000000 - assign \o { \t0 \t1 \t2 \t3 \t4 \t5 \t6 \t7 } - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" - wire width 1 $31 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" - cell $reduce_bool $32 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \o - connect \Y $31 - end - process $group_10 - assign \en_o 1'0 - assign \en_o $31 - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.dec_LDST.dec_cr_out" -module \dec_cr_out$198 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:550" - wire width 32 input 0 \insn_in - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:549" - wire width 3 input 1 \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:548" - wire width 1 input 2 \rc_in - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute 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"/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 8 input 4 \LDST_FXM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 3 input 5 \X_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 input 6 \XL_BT - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" - wire width 8 \ppick_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" - wire width 1 \ppick_en_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" - wire width 8 \ppick_o - cell \ppick$199 \ppick - connect \i \ppick_i - connect \en_o \ppick_en_o - connect \o \ppick_o - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \cr_bitfield_ok - process $group_0 - assign \cr_bitfield_ok 1'0 - assign \cr_bitfield_ok 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:563" - switch \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:564" - attribute \nmigen.decoding "NONE/0" - case 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:566" - attribute \nmigen.decoding "CR0/1" - case 3'001 - assign \cr_bitfield_ok \rc_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:569" - attribute \nmigen.decoding "BF/2" - case 3'010 - assign \cr_bitfield_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:572" - attribute \nmigen.decoding "BT/3" - case 3'011 - assign \cr_bitfield_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:575" - attribute \nmigen.decoding "WHOLE_REG/4" - case 3'100 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \cr_fxm_ok - process $group_1 - assign \cr_fxm_ok 1'0 - assign \cr_fxm_ok 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:563" - switch \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:564" - attribute \nmigen.decoding "NONE/0" - case 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:566" - attribute \nmigen.decoding "CR0/1" - case 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:569" - attribute \nmigen.decoding "BF/2" - case 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:572" - attribute \nmigen.decoding "BT/3" - case 3'011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:575" - attribute \nmigen.decoding "WHOLE_REG/4" - case 3'100 - assign \cr_fxm_ok 1'1 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 3 \cr_bitfield - process $group_2 - assign \cr_bitfield 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:563" - switch \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:564" - attribute \nmigen.decoding "NONE/0" - case 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:566" - attribute \nmigen.decoding "CR0/1" - case 3'001 - assign \cr_bitfield 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:569" - attribute \nmigen.decoding "BF/2" - case 3'010 - assign \cr_bitfield \X_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:572" - attribute \nmigen.decoding "BT/3" - case 3'011 - assign \cr_bitfield \XL_BT [4:2] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:575" - attribute \nmigen.decoding "WHOLE_REG/4" - case 3'100 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:577" - wire width 1 \move_one - process $group_3 - assign \move_one 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:563" - switch \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:564" - attribute \nmigen.decoding "NONE/0" - case 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:566" - attribute \nmigen.decoding "CR0/1" - case 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:569" - attribute \nmigen.decoding "BF/2" - case 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:572" - attribute \nmigen.decoding "BT/3" - case 3'011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:575" - attribute \nmigen.decoding "WHOLE_REG/4" - case 3'100 - assign \move_one \insn_in [20] - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:579" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:579" - cell $eq $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A \LDST_internal_op - connect \B 7'0110000 - connect \Y $1 - end - process $group_4 - assign \ppick_i 8'00000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:563" - switch \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:564" - attribute \nmigen.decoding "NONE/0" - case 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:566" - attribute \nmigen.decoding "CR0/1" - case 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:569" - attribute \nmigen.decoding "BF/2" - case 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:572" - attribute \nmigen.decoding "BT/3" - case 3'011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:575" - attribute \nmigen.decoding "WHOLE_REG/4" - case 3'100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:579" - switch { $1 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:579" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:580" - switch { \move_one } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:580" - case 1'1 - assign \ppick_i \LDST_FXM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:587" - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:589" - case - end - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 8 \cr_fxm - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:579" - wire width 1 $3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:579" - cell $eq $4 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A \LDST_internal_op - connect \B 7'0110000 - connect \Y $3 - end - process $group_5 - assign \cr_fxm 8'00000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:563" - switch \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:564" - attribute \nmigen.decoding "NONE/0" - case 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:566" - attribute \nmigen.decoding "CR0/1" - case 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:569" - attribute \nmigen.decoding "BF/2" - case 3'010 - attribute \src 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8'00000001 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:587" - case - assign \cr_fxm \LDST_FXM - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:589" - case - assign \cr_fxm 8'11111111 - end - end - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.dec_LDST.dec_ai" -module \dec_ai$200 - attribute \enum_base_type "In1Sel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "RA" - attribute \enum_value_010 "RA_OR_ZERO" - attribute \enum_value_011 "SPR" - attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:148" - wire width 3 input 0 \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:149" - wire width 1 output 1 \immz_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 5 input 2 \LDST_RA - attribute \src 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attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:216" - wire width 4 input 0 \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 output 1 \imm_b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 2 \imm_b_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 16 input 3 \LDST_SI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 16 input 4 \LDST_UI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 5 input 5 \LDST_SH32 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 6 input 6 \LDST_sh - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 24 input 7 \LDST_LI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 14 input 8 \LDST_BD - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 14 input 9 \LDST_DS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 64 $1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - cell $pos $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 16 - parameter \Y_WIDTH 64 - connect \A \LDST_UI - connect \Y $1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:229" - wire width 16 \si - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:234" - wire width 32 \si_hi - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:241" - wire width 64 $3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:239" - wire width 16 \ui - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:241" - wire width 47 $4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:241" - cell $sshl $5 - parameter \A_SIGNED 0 - parameter \A_WIDTH 16 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 47 - connect \A \ui - connect \B 5'10000 - connect \Y $4 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:241" - cell $pos $6 - parameter \A_SIGNED 0 - parameter \A_WIDTH 47 - parameter \Y_WIDTH 64 - connect \A $4 - connect \Y $3 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:244" - wire width 26 \li - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:249" - wire width 16 \bd - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:254" - wire width 16 \ds - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:259" - wire width 64 $7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:259" - cell $not $8 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \Y_WIDTH 64 - connect \A 64'0000000000000000000000000000000000000000000000000000000000000000 - connect \Y $7 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 64 $9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - cell $pos $10 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \Y_WIDTH 64 - connect \A \LDST_sh - connect \Y $9 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 64 $11 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - cell $pos $12 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \Y_WIDTH 64 - connect \A \LDST_SH32 - connect \Y $11 - end - process $group_0 - assign \imm_b 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:224" - switch \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:225" - attribute \nmigen.decoding "CONST_UI/2" - case 4'0010 - assign \imm_b $1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:228" - attribute \nmigen.decoding "CONST_SI/3" - case 4'0011 - assign \imm_b { { \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] \si [15] } \si } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:233" - attribute \nmigen.decoding "CONST_SI_HI/5" - case 4'0101 - assign \imm_b { { \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] \si_hi [31] } \si_hi } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:238" - attribute \nmigen.decoding "CONST_UI_HI/4" - case 4'0100 - assign \imm_b $3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:243" - attribute \nmigen.decoding "CONST_LI/6" - case 4'0110 - assign \imm_b { { \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] \li [25] } \li } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:248" - attribute \nmigen.decoding "CONST_BD/7" - case 4'0111 - assign \imm_b { { \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] \bd [15] } \bd } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:253" - attribute \nmigen.decoding "CONST_DS/8" - case 4'1000 - assign \imm_b { { \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] \ds [15] } \ds } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:258" - attribute \nmigen.decoding "CONST_M1/9" - case 4'1001 - assign \imm_b $7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" - attribute \nmigen.decoding "CONST_SH/10" - case 4'1010 - assign \imm_b $9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:264" - attribute \nmigen.decoding "CONST_SH32/11" - case 4'1011 - assign \imm_b $11 - end - sync init - end - process $group_1 - assign \imm_b_ok 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:224" - switch \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:225" - attribute \nmigen.decoding "CONST_UI/2" - case 4'0010 - assign \imm_b_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:228" - attribute \nmigen.decoding "CONST_SI/3" - case 4'0011 - assign \imm_b_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:233" - attribute \nmigen.decoding "CONST_SI_HI/5" - case 4'0101 - assign \imm_b_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:238" - attribute \nmigen.decoding "CONST_UI_HI/4" - case 4'0100 - assign \imm_b_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:243" - attribute \nmigen.decoding "CONST_LI/6" - case 4'0110 - assign \imm_b_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:248" - attribute \nmigen.decoding "CONST_BD/7" - case 4'0111 - assign \imm_b_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:253" - attribute \nmigen.decoding "CONST_DS/8" - case 4'1000 - assign \imm_b_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:258" - attribute \nmigen.decoding "CONST_M1/9" - case 4'1001 - assign \imm_b_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" - attribute \nmigen.decoding "CONST_SH/10" - case 4'1010 - assign \imm_b_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:264" - attribute \nmigen.decoding "CONST_SH32/11" - case 4'1011 - assign \imm_b_ok 1'1 - end - sync init - end - process $group_2 - assign \si 16'0000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:224" - switch \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:225" - attribute \nmigen.decoding "CONST_UI/2" - case 4'0010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:228" - attribute \nmigen.decoding "CONST_SI/3" - case 4'0011 - assign \si \LDST_SI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:233" - attribute \nmigen.decoding "CONST_SI_HI/5" - case 4'0101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:238" - attribute \nmigen.decoding "CONST_UI_HI/4" - case 4'0100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:243" - attribute \nmigen.decoding "CONST_LI/6" - case 4'0110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:248" - attribute \nmigen.decoding "CONST_BD/7" - case 4'0111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:253" - attribute \nmigen.decoding "CONST_DS/8" - case 4'1000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:258" - attribute \nmigen.decoding "CONST_M1/9" - case 4'1001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" - attribute \nmigen.decoding "CONST_SH/10" - case 4'1010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:264" - attribute \nmigen.decoding "CONST_SH32/11" - case 4'1011 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:235" - wire width 47 $13 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:235" - wire width 47 $14 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:235" - cell $sshl $15 - parameter \A_SIGNED 0 - parameter \A_WIDTH 16 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 47 - connect \A \LDST_SI - connect \B 5'10000 - connect \Y $14 - end - connect $13 $14 - process $group_3 - assign \si_hi 32'00000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:224" - switch \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:225" - attribute \nmigen.decoding "CONST_UI/2" - case 4'0010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:228" - attribute \nmigen.decoding "CONST_SI/3" - case 4'0011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:233" - attribute \nmigen.decoding "CONST_SI_HI/5" - case 4'0101 - assign \si_hi $13 [31:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:238" - attribute \nmigen.decoding "CONST_UI_HI/4" - case 4'0100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:243" - attribute \nmigen.decoding "CONST_LI/6" - case 4'0110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:248" - attribute \nmigen.decoding "CONST_BD/7" - case 4'0111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:253" - attribute \nmigen.decoding "CONST_DS/8" - case 4'1000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:258" - attribute \nmigen.decoding "CONST_M1/9" - case 4'1001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" - attribute \nmigen.decoding "CONST_SH/10" - case 4'1010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:264" - attribute \nmigen.decoding "CONST_SH32/11" - case 4'1011 - end - sync init - end - process $group_4 - assign \ui 16'0000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:224" - switch \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:225" - attribute \nmigen.decoding "CONST_UI/2" - case 4'0010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:228" - attribute \nmigen.decoding "CONST_SI/3" - case 4'0011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:233" - attribute \nmigen.decoding "CONST_SI_HI/5" - case 4'0101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:238" - attribute \nmigen.decoding "CONST_UI_HI/4" - case 4'0100 - assign \ui \LDST_UI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:243" - attribute \nmigen.decoding "CONST_LI/6" - case 4'0110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:248" - attribute \nmigen.decoding "CONST_BD/7" - case 4'0111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:253" - attribute \nmigen.decoding "CONST_DS/8" - case 4'1000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:258" - attribute \nmigen.decoding "CONST_M1/9" - case 4'1001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" - attribute \nmigen.decoding "CONST_SH/10" - case 4'1010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:264" - attribute \nmigen.decoding "CONST_SH32/11" - case 4'1011 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:245" - wire width 27 $16 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:245" - wire width 27 $17 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:245" - cell $sshl $18 - parameter \A_SIGNED 0 - parameter \A_WIDTH 24 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 27 - connect \A \LDST_LI - connect \B 2'10 - connect \Y $17 - end - connect $16 $17 - process $group_5 - assign \li 26'00000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:224" - switch \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:225" - attribute \nmigen.decoding "CONST_UI/2" - case 4'0010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:228" - attribute \nmigen.decoding "CONST_SI/3" - case 4'0011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:233" - attribute \nmigen.decoding "CONST_SI_HI/5" - case 4'0101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:238" - attribute \nmigen.decoding "CONST_UI_HI/4" - case 4'0100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:243" - attribute \nmigen.decoding "CONST_LI/6" - case 4'0110 - assign \li $16 [25:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:248" - attribute \nmigen.decoding "CONST_BD/7" - case 4'0111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:253" - attribute \nmigen.decoding "CONST_DS/8" - case 4'1000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:258" - attribute \nmigen.decoding "CONST_M1/9" - case 4'1001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" - attribute \nmigen.decoding "CONST_SH/10" - case 4'1010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:264" - attribute \nmigen.decoding "CONST_SH32/11" - case 4'1011 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:250" - wire width 17 $19 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:250" - wire width 17 $20 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:250" - cell $sshl $21 - parameter \A_SIGNED 0 - parameter \A_WIDTH 14 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 17 - connect \A \LDST_BD - connect \B 2'10 - connect \Y $20 - end - connect $19 $20 - process $group_6 - assign \bd 16'0000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:224" - switch \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:225" - attribute \nmigen.decoding "CONST_UI/2" - case 4'0010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:228" - attribute \nmigen.decoding "CONST_SI/3" - case 4'0011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:233" - attribute \nmigen.decoding "CONST_SI_HI/5" - case 4'0101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:238" - attribute \nmigen.decoding "CONST_UI_HI/4" - case 4'0100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:243" - attribute \nmigen.decoding "CONST_LI/6" - case 4'0110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:248" - attribute \nmigen.decoding "CONST_BD/7" - case 4'0111 - assign \bd $19 [15:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:253" - attribute \nmigen.decoding "CONST_DS/8" - case 4'1000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:258" - attribute \nmigen.decoding "CONST_M1/9" - case 4'1001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" - attribute \nmigen.decoding "CONST_SH/10" - case 4'1010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:264" - attribute \nmigen.decoding "CONST_SH32/11" - case 4'1011 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:255" - wire width 17 $22 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:255" - wire width 17 $23 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:255" - cell $sshl $24 - parameter \A_SIGNED 0 - parameter \A_WIDTH 14 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 17 - connect \A \LDST_DS - connect \B 2'10 - connect \Y $23 - end - connect $22 $23 - process $group_7 - assign \ds 16'0000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:224" - switch \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:225" - attribute \nmigen.decoding "CONST_UI/2" - case 4'0010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:228" - attribute \nmigen.decoding "CONST_SI/3" - case 4'0011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:233" - attribute \nmigen.decoding "CONST_SI_HI/5" - case 4'0101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:238" - attribute \nmigen.decoding "CONST_UI_HI/4" - case 4'0100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:243" - attribute \nmigen.decoding "CONST_LI/6" - case 4'0110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:248" - attribute \nmigen.decoding "CONST_BD/7" - case 4'0111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:253" - attribute \nmigen.decoding "CONST_DS/8" - case 4'1000 - assign \ds $22 [15:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:258" - attribute \nmigen.decoding "CONST_M1/9" - case 4'1001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:261" - attribute \nmigen.decoding "CONST_SH/10" - case 4'1010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:264" - attribute \nmigen.decoding "CONST_SH32/11" - case 4'1011 - end - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.dec_LDST" -module \dec_LDST - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:384" - wire width 32 input 0 \raw_opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:385" - wire width 1 input 1 \bigendian - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute 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\dec_oe_sel_in 2'00 - assign \dec_oe_sel_in \dec_LDST_rc_sel - sync init - end - process $group_7 - assign \dec_cr_in_sel_in 3'000 - assign \dec_cr_in_sel_in \dec_LDST_cr_in - sync init - end - process $group_8 - assign \dec_cr_out_sel_in 3'000 - assign \dec_cr_out_sel_in \dec_LDST_cr_out - sync init - end - process $group_9 - assign \dec_cr_out_rc_in 1'0 - assign \dec_cr_out_rc_in \dec_rc_rc - sync init - end - process $group_10 - assign \LDST_LDST__insn_type 7'0000000 - assign \LDST_LDST__insn_type \dec_LDST_internal_op - sync init - end - process $group_11 - assign \LDST_LDST__fn_unit 11'00000000000 - assign \LDST_LDST__fn_unit \dec_LDST_function_unit - sync init - end - process $group_12 - assign \dec_ai_sel_in 3'000 - assign \dec_ai_sel_in \dec_LDST_in1_sel - sync init - end - process $group_13 - assign \LDST_LDST__zero_a 1'0 - assign \LDST_LDST__zero_a \dec_ai_immz_out - sync init - end - process $group_14 - assign \dec_bi_sel_in 4'0000 - assign \dec_bi_sel_in \dec_LDST_in2_sel - sync init - end - process $group_15 - assign \LDST_LDST__imm_data__data 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \LDST_LDST__imm_data__ok 1'0 - assign { \LDST_LDST__imm_data__ok \LDST_LDST__imm_data__data } { \dec_bi_imm_b_ok \dec_bi_imm_b } - sync init - end - process $group_17 - assign \LDST_LDST__rc__rc 1'0 - assign \LDST_LDST__rc__ok 1'0 - assign { \LDST_LDST__rc__ok \LDST_LDST__rc__rc } { \dec_rc_rc_ok \dec_rc_rc } - sync init - end - process $group_19 - assign \LDST_LDST__oe__oe 1'0 - assign \LDST_LDST__oe__ok 1'0 - assign { \LDST_LDST__oe__ok \LDST_LDST__oe__oe } { \dec_oe_oe_ok \dec_oe_oe } - sync init - end - process $group_21 - assign \LDST_LDST__data_len 4'0000 - assign \LDST_LDST__data_len \dec_LDST_ldst_len - sync init - end - process $group_22 - assign \LDST_LDST__is_32bit 1'0 - assign \LDST_LDST__is_32bit \dec_LDST_is_32b - sync init - end - process $group_23 - assign \LDST_LDST__is_signed 1'0 - assign \LDST_LDST__is_signed \dec_LDST_sgn - sync init - end - process $group_24 - assign \LDST_LDST__byte_reverse 1'0 - assign \LDST_LDST__byte_reverse \dec_LDST_br - sync init - end - process $group_25 - assign \LDST_LDST__sign_extend 1'0 - assign \LDST_LDST__sign_extend \dec_LDST_sgn_ext - sync init - end - process $group_26 - assign \LDST_LDST__ldst_mode 2'00 - assign \LDST_LDST__ldst_mode \dec_LDST_upd - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.rdpick_INT_ra" -module \rdpick_INT_ra - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" - wire width 9 input 0 \i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" - wire width 9 output 1 \o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" - wire width 1 output 2 \en_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:49" - wire width 9 \ni - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" - wire width 9 $1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" - cell $not $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 9 - parameter \Y_WIDTH 9 - connect \A { \i [8] \i [7] \i [6] \i [5] \i [4] \i [3] \i [2] \i [1] \i [0] } - connect \Y $1 - end - process $group_0 - assign \ni 9'000000000 - assign \ni $1 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire width 1 \t0 - process $group_1 - assign \t0 1'0 - assign \t0 \i [0] - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire width 1 \t1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire width 1 $3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire width 1 $4 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_bool $5 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A { \i [0] \ni [1] } - connect \Y $4 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $6 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $4 - connect \Y $3 - end - process $group_2 - assign \t1 1'0 - assign \t1 $3 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire width 1 \t2 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire width 1 $7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire width 1 $8 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_bool $9 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A { \i [1] \i [0] \ni [2] } - connect \Y $8 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $10 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $8 - connect \Y $7 - end - process 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[1] \i [0] \ni [6] } - connect \Y $24 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $26 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $24 - connect \Y $23 - end - process $group_7 - assign \t6 1'0 - assign \t6 $23 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire width 1 \t7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire width 1 $27 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire width 1 $28 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_bool $29 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A { \i [6] \i [5] \i [4] \i [3] \i [2] \i [1] \i [0] \ni [7] } - connect \Y $28 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $30 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $28 - connect \Y $27 - end - process $group_8 - assign \t7 1'0 - assign \t7 $27 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire width 1 \t8 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire width 1 $31 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire width 1 $32 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_bool $33 - parameter \A_SIGNED 0 - parameter \A_WIDTH 9 - parameter \Y_WIDTH 1 - connect \A { \i [7] \i [6] \i [5] \i [4] \i [3] \i [2] \i [1] \i [0] \ni [8] } - connect \Y $32 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $34 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $32 - connect \Y $31 - end - process $group_9 - assign \t8 1'0 - assign \t8 $31 - sync init - end - process $group_10 - assign \o 9'000000000 - assign \o { \t8 \t7 \t6 \t5 \t4 \t3 \t2 \t1 \t0 } - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" - wire width 1 $35 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" - cell $reduce_bool $36 - parameter \A_SIGNED 0 - parameter \A_WIDTH 9 - parameter \Y_WIDTH 1 - connect \A \o - connect \Y $35 - end - process $group_11 - assign \en_o 1'0 - assign \en_o $35 - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.rdpick_INT_rb" -module \rdpick_INT_rb - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" - wire width 8 input 0 \i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" - wire width 8 output 1 \o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" - wire width 1 output 2 \en_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:49" - wire width 8 \ni - attribute \src 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parameter \Y_WIDTH 1 - connect \A { \i [0] \ni [1] } - connect \Y $4 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $6 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $4 - connect \Y $3 - end - process $group_2 - assign \t1 1'0 - assign \t1 $3 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire width 1 \t2 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire width 1 $7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire width 1 $8 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_bool $9 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A { \i [1] \i [0] \ni [2] } - connect \Y $8 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $10 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter 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[1] \i [0] \ni [6] } - connect \Y $24 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $26 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $24 - connect \Y $23 - end - process $group_7 - assign \t6 1'0 - assign \t6 $23 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire width 1 \t7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire width 1 $27 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire width 1 $28 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_bool $29 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A { \i [6] \i [5] \i [4] \i [3] \i [2] \i [1] \i [0] \ni [7] } - connect \Y $28 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $30 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - 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attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_bool $5 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A { \i [0] \ni [1] } - connect \Y $4 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $6 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $4 - connect \Y $3 - end - process $group_2 - assign \t1 1'0 - assign \t1 $3 - sync init - end - process $group_3 - assign \o 2'00 - assign \o { \t1 \t0 } - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" - wire width 1 $7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" - cell $reduce_bool $8 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \o - connect \Y $7 - end - process $group_4 - assign \en_o 1'0 - assign \en_o $7 - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy 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\en_o 1'0 - assign \en_o $3 - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.rdpick_CR_full_cr" -module \rdpick_CR_full_cr - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" - wire width 1 input 0 \i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" - wire width 1 output 1 \o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" - wire width 1 output 2 \en_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:49" - wire width 1 \ni - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" - cell $not $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A { \i } - connect \Y $1 - end - process $group_0 - assign \ni 1'0 - assign \ni $1 - sync init - end - attribute \src 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1 output 2 \en_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:49" - wire width 2 \ni - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" - wire width 2 $1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" - cell $not $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \Y_WIDTH 2 - connect \A { \i [1] \i [0] } - connect \Y $1 - end - process $group_0 - assign \ni 2'00 - assign \ni $1 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire width 1 \t0 - process $group_1 - assign \t0 1'0 - assign \t0 \i [0] - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire width 1 \t1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire width 1 $3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire width 1 $4 - attribute \src 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"test_issuer.core.rdpick_CR_cr_b" -module \rdpick_CR_cr_b - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" - wire width 1 input 0 \i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" - wire width 1 output 1 \o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" - wire width 1 output 2 \en_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:49" - wire width 1 \ni - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" - cell $not $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A { \i } - connect \Y $1 - end - process $group_0 - assign \ni 1'0 - assign \ni $1 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire width 1 \t0 - process $group_1 - assign \t0 1'0 - assign \t0 \i - sync init - end - process $group_2 - assign \o 1'0 - assign \o { \t0 } - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" - wire width 1 $3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" - cell $reduce_bool $4 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \o - connect \Y $3 - end - process $group_3 - assign \en_o 1'0 - assign \en_o $3 - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.rdpick_CR_cr_c" -module \rdpick_CR_cr_c - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" - wire width 1 input 0 \i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" - wire width 1 output 1 \o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" - wire width 1 output 2 \en_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:49" - wire width 1 \ni - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" - cell $not $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A { \i } - connect \Y $1 - end - process $group_0 - assign \ni 1'0 - assign \ni $1 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire width 1 \t0 - process $group_1 - assign \t0 1'0 - assign \t0 \i - sync init - end - process $group_2 - assign \o 1'0 - assign \o { \t0 } - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" - wire width 1 $3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" - cell $reduce_bool $4 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \o - connect \Y $3 - end - process $group_3 - assign \en_o 1'0 - assign \en_o $3 - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.rdpick_FAST_fast1" -module \rdpick_FAST_fast1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" - wire width 3 input 0 \i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" - wire width 3 output 1 \o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" - wire width 1 output 2 \en_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:49" - wire width 3 \ni - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" - wire width 3 $1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" - cell $not $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A { \i [2] \i [1] \i [0] } - connect \Y $1 - end - process $group_0 - assign \ni 3'000 - assign \ni $1 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire width 1 \t0 - process $group_1 - assign \t0 1'0 - assign \t0 \i [0] - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire width 1 \t1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire width 1 $3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire width 1 $4 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_bool $5 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A { \i [0] \ni [1] } - connect \Y $4 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $6 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $4 - connect \Y $3 - end - process $group_2 - assign \t1 1'0 - assign \t1 $3 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire width 1 \t2 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire width 1 $7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire width 1 $8 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_bool $9 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A { \i [1] \i [0] \ni [2] } - connect \Y $8 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $10 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $8 - connect \Y $7 - end - process $group_3 - assign \t2 1'0 - assign \t2 $7 - sync init - end - process $group_4 - assign \o 3'000 - assign \o { \t2 \t1 \t0 } - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" - wire width 1 $11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" - cell $reduce_bool $12 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \o - connect \Y $11 - end - process $group_5 - assign \en_o 1'0 - assign \en_o $11 - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.rdpick_FAST_fast2" -module \rdpick_FAST_fast2 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" - wire width 2 input 0 \i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" - wire width 2 output 1 \o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" - wire width 1 output 2 \en_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:49" - wire width 2 \ni - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" - wire width 2 $1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" - cell $not $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \Y_WIDTH 2 - connect \A { \i [1] \i [0] } - connect \Y $1 - end - process $group_0 - assign \ni 2'00 - assign \ni $1 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire width 1 \t0 - process $group_1 - assign \t0 1'0 - assign \t0 \i [0] - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire width 1 \t1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire width 1 $3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire width 1 $4 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_bool $5 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A { \i [0] \ni [1] } - connect \Y $4 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $6 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $4 - connect \Y $3 - end - process $group_2 - assign \t1 1'0 - assign \t1 $3 - sync init - end - process $group_3 - assign \o 2'00 - assign \o { \t1 \t0 } - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" - wire width 1 $7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" - cell $reduce_bool $8 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \o - connect \Y $7 - end - process $group_4 - assign \en_o 1'0 - assign \en_o $7 - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.rdpick_SPR_spr1" -module \rdpick_SPR_spr1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" - wire width 1 input 0 \i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" - wire width 1 output 1 \o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" - wire width 1 output 2 \en_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:49" - wire width 1 \ni - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" - cell $not $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A { \i } - connect \Y $1 - end - process $group_0 - assign \ni 1'0 - assign \ni $1 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire width 1 \t0 - process $group_1 - assign \t0 1'0 - assign \t0 \i - sync init - end - process $group_2 - assign \o 1'0 - assign \o { \t0 } - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" - wire width 1 $3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" - cell $reduce_bool $4 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \o - connect \Y $3 - end - process $group_3 - assign \en_o 1'0 - assign \en_o $3 - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.wrpick_INT_o" -module \wrpick_INT_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" - wire width 10 input 0 \i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" - wire width 10 output 1 \o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" - wire width 1 output 2 \en_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:49" - wire width 10 \ni - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" - wire width 10 $1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" - cell $not $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 10 - parameter \Y_WIDTH 10 - connect \A { \i [9] \i [8] \i [7] \i [6] \i [5] \i [4] \i [3] \i [2] \i [1] \i [0] } - connect \Y $1 - end - process $group_0 - assign \ni 10'0000000000 - assign \ni $1 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire width 1 \t0 - process $group_1 - assign \t0 1'0 - assign \t0 \i [0] - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire width 1 \t1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire width 1 $3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire width 1 $4 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_bool $5 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A { \i [0] \ni [1] } - connect \Y $4 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $6 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $4 - connect \Y $3 - end - process $group_2 - assign \t1 1'0 - assign \t1 $3 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire width 1 \t2 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire width 1 $7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire width 1 $8 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_bool $9 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A { \i [1] \i [0] \ni [2] } - connect \Y $8 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $10 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $8 - connect \Y $7 - end - process $group_3 - assign \t2 1'0 - assign \t2 $7 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire width 1 \t3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire width 1 $11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire width 1 $12 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_bool $13 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A { \i [2] \i [1] \i [0] \ni [3] } - connect \Y $12 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $14 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $12 - connect \Y $11 - end - process $group_4 - assign \t3 1'0 - assign \t3 $11 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire width 1 \t4 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire width 1 $15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire width 1 $16 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_bool $17 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A { \i [3] \i [2] \i [1] \i [0] \ni [4] } - connect \Y $16 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $18 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $16 - connect \Y $15 - end - process $group_5 - assign \t4 1'0 - assign \t4 $15 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire width 1 \t5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire width 1 $19 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire width 1 $20 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_bool $21 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \Y_WIDTH 1 - connect \A { \i [4] \i [3] \i [2] \i [1] \i [0] \ni [5] } - connect \Y $20 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $22 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $20 - connect \Y $19 - end - process $group_6 - assign \t5 1'0 - assign \t5 $19 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire width 1 \t6 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire width 1 $23 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire width 1 $24 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_bool $25 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A { \i [5] \i [4] \i [3] \i [2] \i [1] \i [0] \ni [6] } - connect \Y $24 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $26 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $24 - connect \Y $23 - end - process $group_7 - assign \t6 1'0 - assign \t6 $23 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire width 1 \t7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire width 1 $27 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire width 1 $28 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_bool $29 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A { \i [6] \i [5] \i [4] \i [3] \i [2] \i [1] \i [0] \ni [7] } - connect \Y $28 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $30 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $28 - connect \Y $27 - end - process $group_8 - assign \t7 1'0 - assign \t7 $27 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire width 1 \t8 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire width 1 $31 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire width 1 $32 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_bool $33 - parameter \A_SIGNED 0 - parameter \A_WIDTH 9 - parameter \Y_WIDTH 1 - connect \A { \i [7] \i [6] \i [5] \i [4] \i [3] \i [2] \i [1] \i [0] \ni [8] } - connect \Y $32 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $34 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $32 - connect \Y $31 - end - process $group_9 - assign \t8 1'0 - assign \t8 $31 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire width 1 \t9 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire width 1 $35 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire width 1 $36 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_bool $37 - parameter \A_SIGNED 0 - parameter \A_WIDTH 10 - parameter \Y_WIDTH 1 - connect \A { \i [8] \i [7] \i [6] \i [5] \i [4] \i [3] \i [2] \i [1] \i [0] \ni [9] } - connect \Y $36 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $38 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $36 - connect \Y $35 - end - process $group_10 - assign \t9 1'0 - assign \t9 $35 - sync init - end - process $group_11 - assign \o 10'0000000000 - assign \o { \t9 \t8 \t7 \t6 \t5 \t4 \t3 \t2 \t1 \t0 } - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" - wire width 1 $39 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" - cell $reduce_bool $40 - parameter \A_SIGNED 0 - parameter \A_WIDTH 10 - parameter \Y_WIDTH 1 - connect \A \o - connect \Y $39 - end - process $group_12 - assign \en_o 1'0 - assign \en_o $39 - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.wrpick_CR_full_cr" -module \wrpick_CR_full_cr - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" - wire width 1 input 0 \i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" - wire width 1 output 1 \o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" - wire width 1 output 2 \en_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:49" - wire width 1 \ni - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" - cell $not $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A { \i } - connect \Y $1 - end - process $group_0 - assign \ni 1'0 - assign \ni $1 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire width 1 \t0 - process $group_1 - assign \t0 1'0 - assign \t0 \i - sync init - end - process $group_2 - assign \o 1'0 - assign \o { \t0 } - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" - wire width 1 $3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" - cell $reduce_bool $4 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \o - connect \Y $3 - end - process $group_3 - assign \en_o 1'0 - assign \en_o $3 - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.core.wrpick_CR_cr_a" -module \wrpick_CR_cr_a - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" - wire width 6 input 0 \i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" - wire width 6 output 1 \o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" - wire width 1 output 2 \en_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:49" - wire width 6 \ni - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" - wire width 6 $1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" - cell $not $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \Y_WIDTH 6 - connect \A { \i [5] \i [4] \i [3] \i [2] \i [1] \i [0] } - connect \Y $1 - end - process $group_0 - assign \ni 6'000000 - assign \ni $1 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire width 1 \t0 - process $group_1 - assign \t0 1'0 - assign \t0 \i [0] - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire width 1 \t1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire width 1 $3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire width 1 $4 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_bool $5 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A { \i [0] \ni [1] } - connect \Y $4 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $6 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 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\nmigen.hierarchy "test_issuer.core.wrpick_XER_xer_ov" -module \wrpick_XER_xer_ov - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" - wire width 4 input 0 \i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" - wire width 4 output 1 \o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" - wire width 1 output 2 \en_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:49" - wire width 4 \ni - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" - wire width 4 $1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" - cell $not $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A { \i [3] \i [2] \i [1] \i [0] } - connect \Y $1 - end - process $group_0 - assign \ni 4'0000 - assign \ni $1 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire width 1 \t0 - process $group_1 - assign \t0 1'0 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"/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 64 \fus_src4_i$81 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:72" - wire width 64 \fus_src2_i$82 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \fus_o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 5 \fus_cu_wr__rel_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 5 \fus_cu_wr__go_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \fus_o_ok$83 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 3 \fus_cu_wr__rel_o$84 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 3 \fus_cu_wr__go_i$85 - attribute \src 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"/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" - wire width 64 \fus_dest1_o$109 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" - wire width 64 \fus_dest1_o$110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" - wire width 64 \fus_dest1_o$111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" - wire width 64 \fus_dest1_o$112 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 \fus_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 \fus_ea - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \fus_full_cr_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" - wire width 32 \fus_dest2_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \fus_cr_a_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \fus_cr_a_ok$113 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \fus_cr_a_ok$114 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \fus_cr_a_ok$115 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \fus_cr_a_ok$116 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \fus_cr_a_ok$117 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" - wire width 4 \fus_dest2_o$118 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" - wire width 4 \fus_dest3_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" - wire width 4 \fus_dest2_o$119 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" - wire width 4 \fus_dest2_o$120 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" - wire width 4 \fus_dest2_o$121 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" - wire width 4 \fus_dest2_o$122 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \fus_xer_ca_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \fus_xer_ca_ok$123 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \fus_xer_ca_ok$124 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" - wire width 2 \fus_dest3_o$125 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" - wire width 2 \fus_dest6_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" - wire width 2 \fus_dest3_o$126 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \fus_xer_ov_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \fus_xer_ov_ok$127 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \fus_xer_ov_ok$128 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \fus_xer_ov_ok$129 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" - wire width 2 \fus_dest4_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" - wire width 2 \fus_dest5_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" - wire width 2 \fus_dest3_o$130 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" - wire width 2 \fus_dest3_o$131 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \fus_xer_so_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \fus_xer_so_ok$132 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \fus_xer_so_ok$133 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \fus_xer_so_ok$134 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" - wire width 1 \fus_dest5_o$135 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" - wire width 1 \fus_dest4_o$136 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" - wire width 1 \fus_dest4_o$137 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" - wire width 1 \fus_dest4_o$138 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \fus_fast1_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 3 \fus_cu_wr__rel_o$139 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:34" - wire width 3 \fus_cu_wr__go_i$140 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \fus_fast1_ok$141 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \fus_fast1_ok$142 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \fus_fast2_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \fus_fast2_ok$143 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" - wire width 64 \fus_dest1_o$144 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" - wire width 64 \fus_dest2_o$145 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" - wire width 64 \fus_dest3_o$146 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" - wire width 64 \fus_dest2_o$147 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" - wire width 64 \fus_dest3_o$148 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \fus_nia_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \fus_nia_ok$149 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" - wire width 64 \fus_dest3_o$150 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" - wire width 64 \fus_dest4_o$151 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \fus_msr_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" - wire width 64 \fus_dest5_o$152 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \fus_spr1_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/compalu_multi.py:84" - wire width 64 \fus_dest2_o$153 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:105" - wire width 1 \fus_ldst_port0_busy_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:98" - wire width 1 \fus_ldst_port0_is_ld_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:99" - wire width 1 \fus_ldst_port0_is_st_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:102" - wire width 4 \fus_ldst_port0_data_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 96 \fus_ldst_port0_addr_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \fus_ldst_port0_addr_i_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:110" - wire width 1 \fus_ldst_port0_addr_exc_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/experiment/pimem.py:109" - wire width 1 \fus_ldst_port0_addr_ok_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 \fus_ldst_port0_ld_data_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \fus_ldst_port0_ld_data_o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 64 \fus_ldst_port0_st_data_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \fus_ldst_port0_st_data_i_ok - cell \fus \fus - connect \coresync_clk \coresync_clk - connect \cu_st__rel_o \cu_st__rel_o - connect \cu_ad__go_i \cu_ad__go_i - connect \cu_ad__rel_o \cu_ad__rel_o - connect \cu_st__go_i \cu_st__go_i - connect \oper_i_alu_alu0__insn_type \fus_oper_i_alu_alu0__insn_type - connect \oper_i_alu_alu0__fn_unit \fus_oper_i_alu_alu0__fn_unit - connect \oper_i_alu_alu0__imm_data__data \fus_oper_i_alu_alu0__imm_data__data - connect \oper_i_alu_alu0__imm_data__ok \fus_oper_i_alu_alu0__imm_data__ok - connect \oper_i_alu_alu0__rc__rc \fus_oper_i_alu_alu0__rc__rc - connect \oper_i_alu_alu0__rc__ok \fus_oper_i_alu_alu0__rc__ok - connect \oper_i_alu_alu0__oe__oe \fus_oper_i_alu_alu0__oe__oe - connect \oper_i_alu_alu0__oe__ok \fus_oper_i_alu_alu0__oe__ok - connect \oper_i_alu_alu0__invert_in \fus_oper_i_alu_alu0__invert_in - connect \oper_i_alu_alu0__zero_a \fus_oper_i_alu_alu0__zero_a - connect \oper_i_alu_alu0__invert_out \fus_oper_i_alu_alu0__invert_out - connect \oper_i_alu_alu0__write_cr0 \fus_oper_i_alu_alu0__write_cr0 - connect \oper_i_alu_alu0__input_carry \fus_oper_i_alu_alu0__input_carry - connect \oper_i_alu_alu0__output_carry \fus_oper_i_alu_alu0__output_carry - connect \oper_i_alu_alu0__is_32bit \fus_oper_i_alu_alu0__is_32bit - connect \oper_i_alu_alu0__is_signed \fus_oper_i_alu_alu0__is_signed - connect \oper_i_alu_alu0__data_len \fus_oper_i_alu_alu0__data_len - connect \oper_i_alu_alu0__insn \fus_oper_i_alu_alu0__insn - connect \cu_issue_i \fus_cu_issue_i - connect \cu_busy_o \fus_cu_busy_o - connect \cu_rdmaskn_i \fus_cu_rdmaskn_i - connect \oper_i_alu_cr0__insn_type \fus_oper_i_alu_cr0__insn_type - connect \oper_i_alu_cr0__fn_unit \fus_oper_i_alu_cr0__fn_unit - connect \oper_i_alu_cr0__insn \fus_oper_i_alu_cr0__insn - connect \cu_issue_i$1 \fus_cu_issue_i$4 - connect \cu_busy_o$2 \fus_cu_busy_o$5 - connect \cu_rdmaskn_i$3 \fus_cu_rdmaskn_i$6 - connect \oper_i_alu_branch0__cia \fus_oper_i_alu_branch0__cia - connect \oper_i_alu_branch0__insn_type \fus_oper_i_alu_branch0__insn_type - connect \oper_i_alu_branch0__fn_unit \fus_oper_i_alu_branch0__fn_unit - connect \oper_i_alu_branch0__insn \fus_oper_i_alu_branch0__insn - connect \oper_i_alu_branch0__imm_data__data \fus_oper_i_alu_branch0__imm_data__data - connect \oper_i_alu_branch0__imm_data__ok \fus_oper_i_alu_branch0__imm_data__ok - connect \oper_i_alu_branch0__lk \fus_oper_i_alu_branch0__lk - connect \oper_i_alu_branch0__is_32bit \fus_oper_i_alu_branch0__is_32bit - connect \cu_issue_i$4 \fus_cu_issue_i$7 - connect \cu_busy_o$5 \fus_cu_busy_o$8 - connect \cu_rdmaskn_i$6 \fus_cu_rdmaskn_i$9 - connect \oper_i_alu_trap0__insn_type \fus_oper_i_alu_trap0__insn_type - connect \oper_i_alu_trap0__fn_unit \fus_oper_i_alu_trap0__fn_unit - connect \oper_i_alu_trap0__insn \fus_oper_i_alu_trap0__insn - connect \oper_i_alu_trap0__msr \fus_oper_i_alu_trap0__msr - connect \oper_i_alu_trap0__cia \fus_oper_i_alu_trap0__cia - connect \oper_i_alu_trap0__is_32bit \fus_oper_i_alu_trap0__is_32bit - connect \oper_i_alu_trap0__traptype \fus_oper_i_alu_trap0__traptype - connect \oper_i_alu_trap0__trapaddr \fus_oper_i_alu_trap0__trapaddr - connect \cu_issue_i$7 \fus_cu_issue_i$10 - connect \cu_busy_o$8 \fus_cu_busy_o$11 - connect \cu_rdmaskn_i$9 \fus_cu_rdmaskn_i$12 - connect \oper_i_alu_logical0__insn_type \fus_oper_i_alu_logical0__insn_type - connect \oper_i_alu_logical0__fn_unit \fus_oper_i_alu_logical0__fn_unit - connect \oper_i_alu_logical0__imm_data__data \fus_oper_i_alu_logical0__imm_data__data - connect \oper_i_alu_logical0__imm_data__ok \fus_oper_i_alu_logical0__imm_data__ok - connect \oper_i_alu_logical0__rc__rc \fus_oper_i_alu_logical0__rc__rc - connect \oper_i_alu_logical0__rc__ok \fus_oper_i_alu_logical0__rc__ok - connect \oper_i_alu_logical0__oe__oe \fus_oper_i_alu_logical0__oe__oe - connect \oper_i_alu_logical0__oe__ok \fus_oper_i_alu_logical0__oe__ok - connect \oper_i_alu_logical0__invert_in \fus_oper_i_alu_logical0__invert_in - connect \oper_i_alu_logical0__zero_a \fus_oper_i_alu_logical0__zero_a - connect \oper_i_alu_logical0__input_carry \fus_oper_i_alu_logical0__input_carry - connect \oper_i_alu_logical0__invert_out \fus_oper_i_alu_logical0__invert_out - connect \oper_i_alu_logical0__write_cr0 \fus_oper_i_alu_logical0__write_cr0 - connect \oper_i_alu_logical0__output_carry \fus_oper_i_alu_logical0__output_carry - connect \oper_i_alu_logical0__is_32bit \fus_oper_i_alu_logical0__is_32bit - connect \oper_i_alu_logical0__is_signed \fus_oper_i_alu_logical0__is_signed - connect \oper_i_alu_logical0__data_len \fus_oper_i_alu_logical0__data_len - connect \oper_i_alu_logical0__insn \fus_oper_i_alu_logical0__insn - connect \cu_issue_i$10 \fus_cu_issue_i$13 - connect \cu_busy_o$11 \fus_cu_busy_o$14 - connect \cu_rdmaskn_i$12 \fus_cu_rdmaskn_i$15 - connect \oper_i_alu_spr0__insn_type \fus_oper_i_alu_spr0__insn_type - connect \oper_i_alu_spr0__fn_unit \fus_oper_i_alu_spr0__fn_unit - connect \oper_i_alu_spr0__insn \fus_oper_i_alu_spr0__insn - connect \oper_i_alu_spr0__is_32bit \fus_oper_i_alu_spr0__is_32bit - connect \cu_issue_i$13 \fus_cu_issue_i$16 - connect \cu_busy_o$14 \fus_cu_busy_o$17 - connect \cu_rdmaskn_i$15 \fus_cu_rdmaskn_i$18 - connect \oper_i_alu_div0__insn_type \fus_oper_i_alu_div0__insn_type - connect \oper_i_alu_div0__fn_unit \fus_oper_i_alu_div0__fn_unit - connect \oper_i_alu_div0__imm_data__data \fus_oper_i_alu_div0__imm_data__data - connect \oper_i_alu_div0__imm_data__ok \fus_oper_i_alu_div0__imm_data__ok - connect \oper_i_alu_div0__rc__rc \fus_oper_i_alu_div0__rc__rc - connect \oper_i_alu_div0__rc__ok \fus_oper_i_alu_div0__rc__ok - connect \oper_i_alu_div0__oe__oe \fus_oper_i_alu_div0__oe__oe - connect \oper_i_alu_div0__oe__ok \fus_oper_i_alu_div0__oe__ok - connect \oper_i_alu_div0__invert_in \fus_oper_i_alu_div0__invert_in - connect \oper_i_alu_div0__zero_a \fus_oper_i_alu_div0__zero_a - connect \oper_i_alu_div0__input_carry \fus_oper_i_alu_div0__input_carry - connect \oper_i_alu_div0__invert_out \fus_oper_i_alu_div0__invert_out - connect \oper_i_alu_div0__write_cr0 \fus_oper_i_alu_div0__write_cr0 - connect \oper_i_alu_div0__output_carry \fus_oper_i_alu_div0__output_carry - connect \oper_i_alu_div0__is_32bit \fus_oper_i_alu_div0__is_32bit - connect \oper_i_alu_div0__is_signed \fus_oper_i_alu_div0__is_signed - connect \oper_i_alu_div0__data_len \fus_oper_i_alu_div0__data_len - connect \oper_i_alu_div0__insn \fus_oper_i_alu_div0__insn - connect \cu_issue_i$16 \fus_cu_issue_i$19 - connect \cu_busy_o$17 \fus_cu_busy_o$20 - connect \cu_rdmaskn_i$18 \fus_cu_rdmaskn_i$21 - connect \oper_i_alu_mul0__insn_type \fus_oper_i_alu_mul0__insn_type - connect \oper_i_alu_mul0__fn_unit \fus_oper_i_alu_mul0__fn_unit - connect \oper_i_alu_mul0__imm_data__data \fus_oper_i_alu_mul0__imm_data__data - connect \oper_i_alu_mul0__imm_data__ok \fus_oper_i_alu_mul0__imm_data__ok - connect \oper_i_alu_mul0__rc__rc \fus_oper_i_alu_mul0__rc__rc - connect \oper_i_alu_mul0__rc__ok \fus_oper_i_alu_mul0__rc__ok - connect \oper_i_alu_mul0__oe__oe \fus_oper_i_alu_mul0__oe__oe - connect \oper_i_alu_mul0__oe__ok \fus_oper_i_alu_mul0__oe__ok - connect \oper_i_alu_mul0__write_cr0 \fus_oper_i_alu_mul0__write_cr0 - connect \oper_i_alu_mul0__is_32bit \fus_oper_i_alu_mul0__is_32bit - connect \oper_i_alu_mul0__is_signed \fus_oper_i_alu_mul0__is_signed - connect \oper_i_alu_mul0__insn \fus_oper_i_alu_mul0__insn - connect \cu_issue_i$19 \fus_cu_issue_i$22 - connect \cu_busy_o$20 \fus_cu_busy_o$23 - connect \cu_rdmaskn_i$21 \fus_cu_rdmaskn_i$24 - connect \oper_i_alu_shift_rot0__insn_type \fus_oper_i_alu_shift_rot0__insn_type - connect \oper_i_alu_shift_rot0__fn_unit \fus_oper_i_alu_shift_rot0__fn_unit - connect \oper_i_alu_shift_rot0__imm_data__data \fus_oper_i_alu_shift_rot0__imm_data__data - connect \oper_i_alu_shift_rot0__imm_data__ok \fus_oper_i_alu_shift_rot0__imm_data__ok - connect \oper_i_alu_shift_rot0__rc__rc \fus_oper_i_alu_shift_rot0__rc__rc - connect \oper_i_alu_shift_rot0__rc__ok \fus_oper_i_alu_shift_rot0__rc__ok - connect \oper_i_alu_shift_rot0__oe__oe \fus_oper_i_alu_shift_rot0__oe__oe - connect \oper_i_alu_shift_rot0__oe__ok \fus_oper_i_alu_shift_rot0__oe__ok - connect \oper_i_alu_shift_rot0__write_cr0 \fus_oper_i_alu_shift_rot0__write_cr0 - connect \oper_i_alu_shift_rot0__input_carry \fus_oper_i_alu_shift_rot0__input_carry - connect \oper_i_alu_shift_rot0__output_carry \fus_oper_i_alu_shift_rot0__output_carry - connect \oper_i_alu_shift_rot0__input_cr \fus_oper_i_alu_shift_rot0__input_cr - connect \oper_i_alu_shift_rot0__output_cr \fus_oper_i_alu_shift_rot0__output_cr - connect \oper_i_alu_shift_rot0__is_32bit \fus_oper_i_alu_shift_rot0__is_32bit - connect \oper_i_alu_shift_rot0__is_signed \fus_oper_i_alu_shift_rot0__is_signed - connect \oper_i_alu_shift_rot0__insn \fus_oper_i_alu_shift_rot0__insn - connect \cu_issue_i$22 \fus_cu_issue_i$25 - connect \cu_busy_o$23 \fus_cu_busy_o$26 - connect \cu_rdmaskn_i$24 \fus_cu_rdmaskn_i$27 - connect \oper_i_ldst_ldst0__insn_type \fus_oper_i_ldst_ldst0__insn_type - connect \oper_i_ldst_ldst0__fn_unit \fus_oper_i_ldst_ldst0__fn_unit - connect \oper_i_ldst_ldst0__imm_data__data \fus_oper_i_ldst_ldst0__imm_data__data - connect \oper_i_ldst_ldst0__imm_data__ok \fus_oper_i_ldst_ldst0__imm_data__ok - connect \oper_i_ldst_ldst0__zero_a \fus_oper_i_ldst_ldst0__zero_a - connect \oper_i_ldst_ldst0__rc__rc \fus_oper_i_ldst_ldst0__rc__rc - connect \oper_i_ldst_ldst0__rc__ok \fus_oper_i_ldst_ldst0__rc__ok - connect \oper_i_ldst_ldst0__oe__oe \fus_oper_i_ldst_ldst0__oe__oe - connect \oper_i_ldst_ldst0__oe__ok \fus_oper_i_ldst_ldst0__oe__ok - connect \oper_i_ldst_ldst0__is_32bit \fus_oper_i_ldst_ldst0__is_32bit - connect \oper_i_ldst_ldst0__is_signed \fus_oper_i_ldst_ldst0__is_signed - connect \oper_i_ldst_ldst0__data_len \fus_oper_i_ldst_ldst0__data_len - connect \oper_i_ldst_ldst0__byte_reverse \fus_oper_i_ldst_ldst0__byte_reverse - connect \oper_i_ldst_ldst0__sign_extend \fus_oper_i_ldst_ldst0__sign_extend - connect \oper_i_ldst_ldst0__ldst_mode \fus_oper_i_ldst_ldst0__ldst_mode - connect \oper_i_ldst_ldst0__insn \fus_oper_i_ldst_ldst0__insn - connect \cu_issue_i$25 \fus_cu_issue_i$28 - connect \cu_busy_o$26 \fus_cu_busy_o$29 - connect \cu_rdmaskn_i$27 \fus_cu_rdmaskn_i$30 - connect \cu_rd__rel_o \fus_cu_rd__rel_o - connect \cu_rd__go_i \fus_cu_rd__go_i - connect \src1_i \fus_src1_i - connect \cu_rd__rel_o$28 \fus_cu_rd__rel_o$31 - connect \cu_rd__go_i$29 \fus_cu_rd__go_i$32 - connect \src1_i$30 \fus_src1_i$33 - connect \cu_rd__rel_o$31 \fus_cu_rd__rel_o$34 - connect \cu_rd__go_i$32 \fus_cu_rd__go_i$35 - connect \src1_i$33 \fus_src1_i$36 - connect \cu_rd__rel_o$34 \fus_cu_rd__rel_o$37 - connect \cu_rd__go_i$35 \fus_cu_rd__go_i$38 - connect \src1_i$36 \fus_src1_i$39 - connect \cu_rd__rel_o$37 \fus_cu_rd__rel_o$40 - connect \cu_rd__go_i$38 \fus_cu_rd__go_i$41 - connect \src1_i$39 \fus_src1_i$42 - connect \cu_rd__rel_o$40 \fus_cu_rd__rel_o$43 - connect \cu_rd__go_i$41 \fus_cu_rd__go_i$44 - connect \src1_i$42 \fus_src1_i$45 - connect \cu_rd__rel_o$43 \fus_cu_rd__rel_o$46 - connect \cu_rd__go_i$44 \fus_cu_rd__go_i$47 - connect \src1_i$45 \fus_src1_i$48 - connect \cu_rd__rel_o$46 \fus_cu_rd__rel_o$49 - connect \cu_rd__go_i$47 \fus_cu_rd__go_i$50 - connect \src1_i$48 \fus_src1_i$51 - connect \cu_rd__rel_o$49 \fus_cu_rd__rel_o$52 - connect \cu_rd__go_i$50 \fus_cu_rd__go_i$53 - connect \src1_i$51 \fus_src1_i$54 - connect \src2_i \fus_src2_i - connect \src2_i$52 \fus_src2_i$55 - connect \src2_i$53 \fus_src2_i$56 - connect \src2_i$54 \fus_src2_i$57 - connect \src2_i$55 \fus_src2_i$58 - connect \src2_i$56 \fus_src2_i$59 - connect \src2_i$57 \fus_src2_i$60 - connect \src2_i$58 \fus_src2_i$61 - connect \src3_i \fus_src3_i - connect \src3_i$59 \fus_src3_i$62 - connect \src3_i$60 \fus_src3_i$63 - connect \src3_i$61 \fus_src3_i$64 - connect \src4_i \fus_src4_i - connect \src3_i$62 \fus_src3_i$65 - connect \src3_i$63 \fus_src3_i$66 - connect \src4_i$64 \fus_src4_i$67 - connect \src4_i$65 \fus_src4_i$68 - connect \src6_i \fus_src6_i - connect \src5_i \fus_src5_i - connect \src5_i$66 \fus_src5_i$69 - connect \src3_i$67 \fus_src3_i$70 - connect \src4_i$68 \fus_src4_i$71 - connect \cu_rd__rel_o$69 \fus_cu_rd__rel_o$72 - connect \cu_rd__go_i$70 \fus_cu_rd__go_i$73 - connect \src3_i$71 \fus_src3_i$74 - connect \src5_i$72 \fus_src5_i$75 - connect \src6_i$73 \fus_src6_i$76 - connect \src1_i$74 \fus_src1_i$77 - connect \src3_i$75 \fus_src3_i$78 - connect \src3_i$76 \fus_src3_i$79 - connect \src2_i$77 \fus_src2_i$80 - connect \src4_i$78 \fus_src4_i$81 - connect \src2_i$79 \fus_src2_i$82 - connect \o_ok \fus_o_ok - connect \cu_wr__rel_o \fus_cu_wr__rel_o - connect \cu_wr__go_i \fus_cu_wr__go_i - connect \o_ok$80 \fus_o_ok$83 - connect \cu_wr__rel_o$81 \fus_cu_wr__rel_o$84 - connect \cu_wr__go_i$82 \fus_cu_wr__go_i$85 - connect \o_ok$83 \fus_o_ok$86 - connect \cu_wr__rel_o$84 \fus_cu_wr__rel_o$87 - connect \cu_wr__go_i$85 \fus_cu_wr__go_i$88 - connect \o_ok$86 \fus_o_ok$89 - connect \cu_wr__rel_o$87 \fus_cu_wr__rel_o$90 - connect \cu_wr__go_i$88 \fus_cu_wr__go_i$91 - connect \o_ok$89 \fus_o_ok$92 - connect \cu_wr__rel_o$90 \fus_cu_wr__rel_o$93 - connect \cu_wr__go_i$91 \fus_cu_wr__go_i$94 - connect \o_ok$92 \fus_o_ok$95 - connect \cu_wr__rel_o$93 \fus_cu_wr__rel_o$96 - connect \cu_wr__go_i$94 \fus_cu_wr__go_i$97 - connect \o_ok$95 \fus_o_ok$98 - connect \cu_wr__rel_o$96 \fus_cu_wr__rel_o$99 - connect \cu_wr__go_i$97 \fus_cu_wr__go_i$100 - connect \o_ok$98 \fus_o_ok$101 - connect \cu_wr__rel_o$99 \fus_cu_wr__rel_o$102 - connect \cu_wr__go_i$100 \fus_cu_wr__go_i$103 - connect \cu_wr__rel_o$101 \fus_cu_wr__rel_o$104 - connect \cu_wr__go_i$102 \fus_cu_wr__go_i$105 - connect \dest1_o \fus_dest1_o - connect \dest1_o$103 \fus_dest1_o$106 - connect \dest1_o$104 \fus_dest1_o$107 - connect \dest1_o$105 \fus_dest1_o$108 - connect \dest1_o$106 \fus_dest1_o$109 - connect \dest1_o$107 \fus_dest1_o$110 - connect \dest1_o$108 \fus_dest1_o$111 - connect \dest1_o$109 \fus_dest1_o$112 - connect \o \fus_o - connect \ea \fus_ea - connect \full_cr_ok \fus_full_cr_ok - connect \dest2_o \fus_dest2_o - connect \cr_a_ok \fus_cr_a_ok - connect \cr_a_ok$110 \fus_cr_a_ok$113 - connect \cr_a_ok$111 \fus_cr_a_ok$114 - connect \cr_a_ok$112 \fus_cr_a_ok$115 - connect \cr_a_ok$113 \fus_cr_a_ok$116 - connect \cr_a_ok$114 \fus_cr_a_ok$117 - connect \dest2_o$115 \fus_dest2_o$118 - connect \dest3_o \fus_dest3_o - connect \dest2_o$116 \fus_dest2_o$119 - connect \dest2_o$117 \fus_dest2_o$120 - connect \dest2_o$118 \fus_dest2_o$121 - connect \dest2_o$119 \fus_dest2_o$122 - connect \xer_ca_ok \fus_xer_ca_ok - connect \xer_ca_ok$120 \fus_xer_ca_ok$123 - connect \xer_ca_ok$121 \fus_xer_ca_ok$124 - connect \dest3_o$122 \fus_dest3_o$125 - connect \dest6_o \fus_dest6_o - connect \dest3_o$123 \fus_dest3_o$126 - connect \xer_ov_ok \fus_xer_ov_ok - connect \xer_ov_ok$124 \fus_xer_ov_ok$127 - connect \xer_ov_ok$125 \fus_xer_ov_ok$128 - connect \xer_ov_ok$126 \fus_xer_ov_ok$129 - connect \dest4_o \fus_dest4_o - connect \dest5_o \fus_dest5_o - connect \dest3_o$127 \fus_dest3_o$130 - connect \dest3_o$128 \fus_dest3_o$131 - connect \xer_so_ok \fus_xer_so_ok - connect \xer_so_ok$129 \fus_xer_so_ok$132 - connect \xer_so_ok$130 \fus_xer_so_ok$133 - connect \xer_so_ok$131 \fus_xer_so_ok$134 - connect \dest5_o$132 \fus_dest5_o$135 - connect \dest4_o$133 \fus_dest4_o$136 - connect \dest4_o$134 \fus_dest4_o$137 - connect \dest4_o$135 \fus_dest4_o$138 - connect \fast1_ok \fus_fast1_ok - connect \cu_wr__rel_o$136 \fus_cu_wr__rel_o$139 - connect \cu_wr__go_i$137 \fus_cu_wr__go_i$140 - connect \fast1_ok$138 \fus_fast1_ok$141 - connect \fast1_ok$139 \fus_fast1_ok$142 - connect \fast2_ok \fus_fast2_ok - connect \fast2_ok$140 \fus_fast2_ok$143 - connect \dest1_o$141 \fus_dest1_o$144 - connect \dest2_o$142 \fus_dest2_o$145 - connect \dest3_o$143 \fus_dest3_o$146 - connect \dest2_o$144 \fus_dest2_o$147 - connect \dest3_o$145 \fus_dest3_o$148 - connect \nia_ok \fus_nia_ok - connect \nia_ok$146 \fus_nia_ok$149 - connect \dest3_o$147 \fus_dest3_o$150 - connect \dest4_o$148 \fus_dest4_o$151 - connect \msr_ok \fus_msr_ok - connect \dest5_o$149 \fus_dest5_o$152 - connect \spr1_ok \fus_spr1_ok - connect \dest2_o$150 \fus_dest2_o$153 - connect \coresync_rst \coresync_rst - connect \ldst_port0_busy_o \fus_ldst_port0_busy_o - connect \ldst_port0_is_ld_i \fus_ldst_port0_is_ld_i - connect \ldst_port0_is_st_i \fus_ldst_port0_is_st_i - connect \ldst_port0_data_len \fus_ldst_port0_data_len - connect \ldst_port0_addr_i \fus_ldst_port0_addr_i - connect \ldst_port0_addr_i_ok \fus_ldst_port0_addr_i_ok - connect \ldst_port0_addr_exc_o \fus_ldst_port0_addr_exc_o - connect \ldst_port0_addr_ok_o \fus_ldst_port0_addr_ok_o - connect \ldst_port0_ld_data_o \fus_ldst_port0_ld_data_o - connect \ldst_port0_ld_data_o_ok \fus_ldst_port0_ld_data_o_ok - connect \ldst_port0_st_data_i \fus_ldst_port0_st_data_i - connect \ldst_port0_st_data_i_ok \fus_ldst_port0_st_data_i_ok - end - cell \l0 \l0 - connect \coresync_clk \coresync_clk - connect \coresync_rst \coresync_rst - connect \ldst_port0_busy_o \fus_ldst_port0_busy_o - connect \ldst_port0_is_ld_i \fus_ldst_port0_is_ld_i - connect \ldst_port0_is_st_i \fus_ldst_port0_is_st_i - connect \ldst_port0_data_len \fus_ldst_port0_data_len - connect \ldst_port0_addr_i \fus_ldst_port0_addr_i - connect \ldst_port0_addr_i_ok \fus_ldst_port0_addr_i_ok - connect \ldst_port0_addr_exc_o \fus_ldst_port0_addr_exc_o - connect \ldst_port0_addr_ok_o \fus_ldst_port0_addr_ok_o - connect \ldst_port0_ld_data_o \fus_ldst_port0_ld_data_o - connect \ldst_port0_ld_data_o_ok \fus_ldst_port0_ld_data_o_ok - connect \ldst_port0_st_data_i \fus_ldst_port0_st_data_i - connect \ldst_port0_st_data_i_ok \fus_ldst_port0_st_data_i_ok - connect \dbus__cyc \dbus__cyc - connect \dbus__ack \dbus__ack - connect \dbus__err \dbus__err - connect \dbus__stb \dbus__stb - connect \dbus__sel \dbus__sel - connect \dbus__dat_r \dbus__dat_r - connect \dbus__adr \dbus__adr - connect \dbus__we \dbus__we - connect \dbus__dat_w \dbus__dat_w - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 \int_src1__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 5 \int_src1__addr - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 \int_src1__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 \int_src2__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 5 \int_src2__addr - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 \int_src2__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 \int_src3__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 5 \int_src3__addr - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 \int_src3__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 \int_dest1__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 5 \int_dest1__addr - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 \int_dest1__wen - cell \int \int - connect \coresync_clk \coresync_clk - connect \dmi__addr \dmi__addr - connect \dmi__ren \dmi__ren - connect \dmi__data_o \dmi__data_o - connect \src1__data_o \int_src1__data_o - connect \src1__addr \int_src1__addr - connect \src1__ren \int_src1__ren - connect \src2__data_o \int_src2__data_o - connect \src2__addr \int_src2__addr - connect \src2__ren \int_src2__ren - connect \src3__data_o \int_src3__data_o - connect \src3__addr \int_src3__addr - connect \src3__ren \int_src3__ren - connect \dest1__data_i \int_dest1__data_i - connect \dest1__addr \int_dest1__addr - connect \dest1__wen \int_dest1__wen - connect \coresync_rst \coresync_rst - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 32 \cr_full_rd__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 8 \cr_full_rd__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 \cr_src1__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 8 \cr_src1__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 \cr_src2__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 8 \cr_src2__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 \cr_src3__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 8 \cr_src3__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 32 \cr_full_wr__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 8 \cr_full_wr__wen - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 \cr_data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 8 \cr_wen - cell \cr \cr - connect \coresync_clk \coresync_clk - connect \full_rd2__ren \full_rd2__ren - connect \full_rd2__data_o \full_rd2__data_o - connect \full_rd__data_o \cr_full_rd__data_o - connect \full_rd__ren \cr_full_rd__ren - connect \src1__data_o \cr_src1__data_o - connect \src1__ren \cr_src1__ren - connect \src2__data_o \cr_src2__data_o - connect \src2__ren \cr_src2__ren - connect \src3__data_o \cr_src3__data_o - connect \src3__ren \cr_src3__ren - connect \full_wr__data_i \cr_full_wr__data_i - connect \full_wr__wen \cr_full_wr__wen - connect \data_i \cr_data_i - connect \wen \cr_wen - connect \coresync_rst \coresync_rst - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 2 \xer_src1__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 3 \xer_src1__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 2 \xer_src2__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 3 \xer_src2__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 2 \xer_src3__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 3 \xer_src3__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 2 \xer_data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 3 \xer_wen - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 2 \xer_data_i$154 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 3 \xer_wen$155 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 2 \xer_data_i$156 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 3 \xer_wen$157 - cell \xer \xer - connect \coresync_clk \coresync_clk - connect \full_rd__ren \full_rd__ren - connect \full_rd__data_o \full_rd__data_o - connect \src1__data_o \xer_src1__data_o - connect \src1__ren \xer_src1__ren - connect \src2__data_o \xer_src2__data_o - connect \src2__ren \xer_src2__ren - connect \src3__data_o \xer_src3__data_o - connect \src3__ren \xer_src3__ren - connect \data_i \xer_data_i - connect \wen \xer_wen - connect \data_i$1 \xer_data_i$154 - connect \wen$2 \xer_wen$155 - connect \data_i$3 \xer_data_i$156 - connect \wen$4 \xer_wen$157 - connect \coresync_rst \coresync_rst - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 \fast_src1__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 3 \fast_src1__addr - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 \fast_src1__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 \fast_src2__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 3 \fast_src2__addr - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 \fast_src2__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 \fast_dest1__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 3 \fast_dest1__addr - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 \fast_dest1__wen - cell \fast \fast - connect \coresync_clk \coresync_clk - connect \issue__addr \issue__addr - connect \issue__ren \issue__ren - connect \issue__data_o \issue__data_o - connect \issue__addr$1 \issue__addr$3 - connect \issue__wen \issue__wen - connect \issue__data_i \issue__data_i - connect \src1__data_o \fast_src1__data_o - connect \src1__addr \fast_src1__addr - connect \src1__ren \fast_src1__ren - connect \src2__data_o \fast_src2__data_o - connect \src2__addr \fast_src2__addr - connect \src2__ren \fast_src2__ren - connect \dest1__data_i \fast_dest1__data_i - connect \dest1__addr \fast_dest1__addr - connect \dest1__wen \fast_dest1__wen - connect \coresync_rst \coresync_rst - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 \state_data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 \state_data_i$158 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 \state_wen - cell \state \state - connect \coresync_clk \coresync_clk - connect \cia__ren \cia__ren - connect \cia__data_o \cia__data_o - connect \wen \wen - connect \data_i \data_i - connect \msr__ren \msr__ren - connect \msr__data_o \msr__data_o - connect \state_nia_wen \state_nia_wen - connect \data_i$1 \state_data_i - connect \data_i$2 \state_data_i$158 - connect \wen$3 \state_wen - connect \coresync_rst \coresync_rst - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 \spr_spr1__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 7 \spr_spr1__addr - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 \spr_spr1__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 \spr_spr1__data_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 7 \spr_spr1__addr$159 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 \spr_spr1__wen - cell \spr \spr - connect \coresync_clk \coresync_clk - connect \spr1__data_o \spr_spr1__data_o - connect \spr1__addr \spr_spr1__addr - connect \spr1__ren \spr_spr1__ren - connect \spr1__data_i \spr_spr1__data_i - connect \spr1__addr$1 \spr_spr1__addr$159 - connect \spr1__wen \spr_spr1__wen - connect \coresync_rst \coresync_rst - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:384" - wire width 32 \dec_ALU_raw_opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:385" - wire width 1 \dec_ALU_bigendian - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \dec_ALU_ALU_ALU__insn_type - attribute \enum_base_type "Function" - attribute \enum_value_00000000000 "NONE" - attribute \enum_value_00000000010 "ALU" - attribute \enum_value_00000000100 "LDST" - attribute \enum_value_00000001000 "SHIFT_ROT" - attribute \enum_value_00000010000 "LOGICAL" - attribute \enum_value_00000100000 "BRANCH" - attribute \enum_value_00001000000 "CR" - attribute \enum_value_00010000000 "TRAP" - attribute \enum_value_00100000000 "MUL" - attribute \enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 \dec_ALU_ALU_ALU__fn_unit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \dec_ALU_ALU_ALU__imm_data__data - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \dec_ALU_ALU_ALU__imm_data__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \dec_ALU_ALU_ALU__rc__rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \dec_ALU_ALU_ALU__rc__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \dec_ALU_ALU_ALU__oe__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \dec_ALU_ALU_ALU__oe__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \dec_ALU_ALU_ALU__invert_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \dec_ALU_ALU_ALU__zero_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \dec_ALU_ALU_ALU__invert_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \dec_ALU_ALU_ALU__write_cr0 - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \dec_ALU_ALU_ALU__input_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \dec_ALU_ALU_ALU__output_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \dec_ALU_ALU_ALU__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \dec_ALU_ALU_ALU__is_signed - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \dec_ALU_ALU_ALU__data_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \dec_ALU_ALU_ALU__insn - cell \dec_ALU \dec_ALU - connect \raw_opcode_in \dec_ALU_raw_opcode_in - connect \bigendian \dec_ALU_bigendian - connect \ALU_ALU__insn_type \dec_ALU_ALU_ALU__insn_type - connect \ALU_ALU__fn_unit \dec_ALU_ALU_ALU__fn_unit - connect \ALU_ALU__imm_data__data \dec_ALU_ALU_ALU__imm_data__data - connect \ALU_ALU__imm_data__ok \dec_ALU_ALU_ALU__imm_data__ok - connect \ALU_ALU__rc__rc \dec_ALU_ALU_ALU__rc__rc - connect \ALU_ALU__rc__ok \dec_ALU_ALU_ALU__rc__ok - connect \ALU_ALU__oe__oe \dec_ALU_ALU_ALU__oe__oe - connect \ALU_ALU__oe__ok \dec_ALU_ALU_ALU__oe__ok - connect \ALU_ALU__invert_in \dec_ALU_ALU_ALU__invert_in - connect \ALU_ALU__zero_a \dec_ALU_ALU_ALU__zero_a - connect \ALU_ALU__invert_out \dec_ALU_ALU_ALU__invert_out - connect \ALU_ALU__write_cr0 \dec_ALU_ALU_ALU__write_cr0 - connect \ALU_ALU__input_carry \dec_ALU_ALU_ALU__input_carry - connect \ALU_ALU__output_carry \dec_ALU_ALU_ALU__output_carry - connect \ALU_ALU__is_32bit \dec_ALU_ALU_ALU__is_32bit - connect \ALU_ALU__is_signed \dec_ALU_ALU_ALU__is_signed - connect \ALU_ALU__data_len \dec_ALU_ALU_ALU__data_len - connect \ALU_ALU__insn \dec_ALU_ALU_ALU__insn - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:384" - wire width 32 \dec_CR_raw_opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:385" - wire width 1 \dec_CR_bigendian - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \dec_CR_CR_CR__insn_type - attribute \enum_base_type "Function" - attribute \enum_value_00000000000 "NONE" - attribute \enum_value_00000000010 "ALU" - attribute \enum_value_00000000100 "LDST" - attribute \enum_value_00000001000 "SHIFT_ROT" - attribute \enum_value_00000010000 "LOGICAL" - attribute \enum_value_00000100000 "BRANCH" - attribute \enum_value_00001000000 "CR" - attribute \enum_value_00010000000 "TRAP" - attribute \enum_value_00100000000 "MUL" - attribute \enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 \dec_CR_CR_CR__fn_unit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \dec_CR_CR_CR__insn - cell \dec_CR \dec_CR - connect \raw_opcode_in \dec_CR_raw_opcode_in - connect \bigendian \dec_CR_bigendian - connect \CR_CR__insn_type \dec_CR_CR_CR__insn_type - connect \CR_CR__fn_unit \dec_CR_CR_CR__fn_unit - connect \CR_CR__insn \dec_CR_CR_CR__insn - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:384" - wire width 32 \dec_BRANCH_raw_opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:385" - wire width 1 \dec_BRANCH_bigendian - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \dec_BRANCH_BRANCH_BRANCH__cia - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \dec_BRANCH_BRANCH_BRANCH__insn_type - attribute \enum_base_type "Function" - attribute \enum_value_00000000000 "NONE" - attribute \enum_value_00000000010 "ALU" - attribute \enum_value_00000000100 "LDST" - attribute \enum_value_00000001000 "SHIFT_ROT" - attribute \enum_value_00000010000 "LOGICAL" - attribute \enum_value_00000100000 "BRANCH" - attribute \enum_value_00001000000 "CR" - attribute \enum_value_00010000000 "TRAP" - attribute \enum_value_00100000000 "MUL" - attribute \enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 \dec_BRANCH_BRANCH_BRANCH__fn_unit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \dec_BRANCH_BRANCH_BRANCH__insn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \dec_BRANCH_BRANCH_BRANCH__imm_data__data - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \dec_BRANCH_BRANCH_BRANCH__imm_data__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \dec_BRANCH_BRANCH_BRANCH__lk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \dec_BRANCH_BRANCH_BRANCH__is_32bit - cell \dec_BRANCH \dec_BRANCH - connect \core_pc \core_pc - connect \raw_opcode_in \dec_BRANCH_raw_opcode_in - connect \bigendian \dec_BRANCH_bigendian - connect \BRANCH_BRANCH__cia \dec_BRANCH_BRANCH_BRANCH__cia - connect \BRANCH_BRANCH__insn_type \dec_BRANCH_BRANCH_BRANCH__insn_type - connect \BRANCH_BRANCH__fn_unit \dec_BRANCH_BRANCH_BRANCH__fn_unit - connect \BRANCH_BRANCH__insn \dec_BRANCH_BRANCH_BRANCH__insn - connect \BRANCH_BRANCH__imm_data__data \dec_BRANCH_BRANCH_BRANCH__imm_data__data - connect \BRANCH_BRANCH__imm_data__ok \dec_BRANCH_BRANCH_BRANCH__imm_data__ok - connect \BRANCH_BRANCH__lk \dec_BRANCH_BRANCH_BRANCH__lk - connect \BRANCH_BRANCH__is_32bit \dec_BRANCH_BRANCH_BRANCH__is_32bit - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:384" - wire width 32 \dec_LOGICAL_raw_opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:385" - wire width 1 \dec_LOGICAL_bigendian - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \dec_LOGICAL_LOGICAL_LOGICAL__insn_type - attribute \enum_base_type "Function" - attribute \enum_value_00000000000 "NONE" - attribute \enum_value_00000000010 "ALU" - attribute \enum_value_00000000100 "LDST" - attribute \enum_value_00000001000 "SHIFT_ROT" - attribute \enum_value_00000010000 "LOGICAL" - attribute \enum_value_00000100000 "BRANCH" - attribute \enum_value_00001000000 "CR" - attribute \enum_value_00010000000 "TRAP" - attribute \enum_value_00100000000 "MUL" - attribute \enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 \dec_LOGICAL_LOGICAL_LOGICAL__fn_unit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \dec_LOGICAL_LOGICAL_LOGICAL__imm_data__data - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \dec_LOGICAL_LOGICAL_LOGICAL__imm_data__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \dec_LOGICAL_LOGICAL_LOGICAL__rc__rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \dec_LOGICAL_LOGICAL_LOGICAL__rc__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \dec_LOGICAL_LOGICAL_LOGICAL__oe__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \dec_LOGICAL_LOGICAL_LOGICAL__oe__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \dec_LOGICAL_LOGICAL_LOGICAL__invert_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \dec_LOGICAL_LOGICAL_LOGICAL__zero_a - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \dec_LOGICAL_LOGICAL_LOGICAL__input_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \dec_LOGICAL_LOGICAL_LOGICAL__invert_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \dec_LOGICAL_LOGICAL_LOGICAL__write_cr0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \dec_LOGICAL_LOGICAL_LOGICAL__output_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \dec_LOGICAL_LOGICAL_LOGICAL__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \dec_LOGICAL_LOGICAL_LOGICAL__is_signed - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \dec_LOGICAL_LOGICAL_LOGICAL__data_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \dec_LOGICAL_LOGICAL_LOGICAL__insn - cell \dec_LOGICAL \dec_LOGICAL - connect \raw_opcode_in \dec_LOGICAL_raw_opcode_in - connect \bigendian \dec_LOGICAL_bigendian - connect \LOGICAL_LOGICAL__insn_type \dec_LOGICAL_LOGICAL_LOGICAL__insn_type - connect \LOGICAL_LOGICAL__fn_unit \dec_LOGICAL_LOGICAL_LOGICAL__fn_unit - connect \LOGICAL_LOGICAL__imm_data__data \dec_LOGICAL_LOGICAL_LOGICAL__imm_data__data - connect \LOGICAL_LOGICAL__imm_data__ok \dec_LOGICAL_LOGICAL_LOGICAL__imm_data__ok - connect \LOGICAL_LOGICAL__rc__rc \dec_LOGICAL_LOGICAL_LOGICAL__rc__rc - connect \LOGICAL_LOGICAL__rc__ok \dec_LOGICAL_LOGICAL_LOGICAL__rc__ok - connect \LOGICAL_LOGICAL__oe__oe \dec_LOGICAL_LOGICAL_LOGICAL__oe__oe - connect \LOGICAL_LOGICAL__oe__ok \dec_LOGICAL_LOGICAL_LOGICAL__oe__ok - connect \LOGICAL_LOGICAL__invert_in \dec_LOGICAL_LOGICAL_LOGICAL__invert_in - connect \LOGICAL_LOGICAL__zero_a \dec_LOGICAL_LOGICAL_LOGICAL__zero_a - connect \LOGICAL_LOGICAL__input_carry \dec_LOGICAL_LOGICAL_LOGICAL__input_carry - connect \LOGICAL_LOGICAL__invert_out \dec_LOGICAL_LOGICAL_LOGICAL__invert_out - connect \LOGICAL_LOGICAL__write_cr0 \dec_LOGICAL_LOGICAL_LOGICAL__write_cr0 - connect \LOGICAL_LOGICAL__output_carry \dec_LOGICAL_LOGICAL_LOGICAL__output_carry - connect \LOGICAL_LOGICAL__is_32bit \dec_LOGICAL_LOGICAL_LOGICAL__is_32bit - connect \LOGICAL_LOGICAL__is_signed \dec_LOGICAL_LOGICAL_LOGICAL__is_signed - connect \LOGICAL_LOGICAL__data_len \dec_LOGICAL_LOGICAL_LOGICAL__data_len - connect \LOGICAL_LOGICAL__insn \dec_LOGICAL_LOGICAL_LOGICAL__insn - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:384" - wire width 32 \dec_SPR_raw_opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:385" - wire width 1 \dec_SPR_bigendian - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \dec_SPR_SPR_SPR__insn_type - attribute \enum_base_type "Function" - attribute \enum_value_00000000000 "NONE" - attribute \enum_value_00000000010 "ALU" - attribute \enum_value_00000000100 "LDST" - attribute \enum_value_00000001000 "SHIFT_ROT" - attribute \enum_value_00000010000 "LOGICAL" - attribute \enum_value_00000100000 "BRANCH" - attribute \enum_value_00001000000 "CR" - attribute \enum_value_00010000000 "TRAP" - attribute \enum_value_00100000000 "MUL" - attribute \enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 \dec_SPR_SPR_SPR__fn_unit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \dec_SPR_SPR_SPR__insn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \dec_SPR_SPR_SPR__is_32bit - cell \dec_SPR \dec_SPR - connect \raw_opcode_in \dec_SPR_raw_opcode_in - connect \bigendian \dec_SPR_bigendian - connect \SPR_SPR__insn_type \dec_SPR_SPR_SPR__insn_type - connect \SPR_SPR__fn_unit \dec_SPR_SPR_SPR__fn_unit - connect \SPR_SPR__insn \dec_SPR_SPR_SPR__insn - connect \SPR_SPR__is_32bit \dec_SPR_SPR_SPR__is_32bit - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:384" - wire width 32 \dec_DIV_raw_opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:385" - wire width 1 \dec_DIV_bigendian - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \dec_DIV_DIV_DIV__insn_type - attribute \enum_base_type "Function" - attribute \enum_value_00000000000 "NONE" - attribute \enum_value_00000000010 "ALU" - attribute \enum_value_00000000100 "LDST" - attribute \enum_value_00000001000 "SHIFT_ROT" - attribute \enum_value_00000010000 "LOGICAL" - attribute \enum_value_00000100000 "BRANCH" - attribute \enum_value_00001000000 "CR" - attribute \enum_value_00010000000 "TRAP" - attribute \enum_value_00100000000 "MUL" - attribute \enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 \dec_DIV_DIV_DIV__fn_unit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \dec_DIV_DIV_DIV__imm_data__data - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \dec_DIV_DIV_DIV__imm_data__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \dec_DIV_DIV_DIV__rc__rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \dec_DIV_DIV_DIV__rc__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \dec_DIV_DIV_DIV__oe__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \dec_DIV_DIV_DIV__oe__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \dec_DIV_DIV_DIV__invert_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \dec_DIV_DIV_DIV__zero_a - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \dec_DIV_DIV_DIV__input_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \dec_DIV_DIV_DIV__invert_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \dec_DIV_DIV_DIV__write_cr0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \dec_DIV_DIV_DIV__output_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \dec_DIV_DIV_DIV__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \dec_DIV_DIV_DIV__is_signed - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \dec_DIV_DIV_DIV__data_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \dec_DIV_DIV_DIV__insn - cell \dec_DIV \dec_DIV - connect \raw_opcode_in \dec_DIV_raw_opcode_in - connect \bigendian \dec_DIV_bigendian - connect \DIV_DIV__insn_type \dec_DIV_DIV_DIV__insn_type - connect \DIV_DIV__fn_unit \dec_DIV_DIV_DIV__fn_unit - connect \DIV_DIV__imm_data__data \dec_DIV_DIV_DIV__imm_data__data - connect \DIV_DIV__imm_data__ok \dec_DIV_DIV_DIV__imm_data__ok - connect \DIV_DIV__rc__rc \dec_DIV_DIV_DIV__rc__rc - connect \DIV_DIV__rc__ok \dec_DIV_DIV_DIV__rc__ok - connect \DIV_DIV__oe__oe \dec_DIV_DIV_DIV__oe__oe - connect \DIV_DIV__oe__ok \dec_DIV_DIV_DIV__oe__ok - connect \DIV_DIV__invert_in \dec_DIV_DIV_DIV__invert_in - connect \DIV_DIV__zero_a \dec_DIV_DIV_DIV__zero_a - connect \DIV_DIV__input_carry \dec_DIV_DIV_DIV__input_carry - connect \DIV_DIV__invert_out \dec_DIV_DIV_DIV__invert_out - connect \DIV_DIV__write_cr0 \dec_DIV_DIV_DIV__write_cr0 - connect \DIV_DIV__output_carry \dec_DIV_DIV_DIV__output_carry - connect \DIV_DIV__is_32bit \dec_DIV_DIV_DIV__is_32bit - connect \DIV_DIV__is_signed \dec_DIV_DIV_DIV__is_signed - connect \DIV_DIV__data_len \dec_DIV_DIV_DIV__data_len - connect \DIV_DIV__insn \dec_DIV_DIV_DIV__insn - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:384" - wire width 32 \dec_MUL_raw_opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:385" - wire width 1 \dec_MUL_bigendian - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \dec_MUL_MUL_MUL__insn_type - attribute \enum_base_type "Function" - attribute \enum_value_00000000000 "NONE" - attribute \enum_value_00000000010 "ALU" - attribute \enum_value_00000000100 "LDST" - attribute \enum_value_00000001000 "SHIFT_ROT" - attribute \enum_value_00000010000 "LOGICAL" - attribute \enum_value_00000100000 "BRANCH" - attribute \enum_value_00001000000 "CR" - attribute \enum_value_00010000000 "TRAP" - attribute \enum_value_00100000000 "MUL" - attribute \enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 \dec_MUL_MUL_MUL__fn_unit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \dec_MUL_MUL_MUL__imm_data__data - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \dec_MUL_MUL_MUL__imm_data__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \dec_MUL_MUL_MUL__rc__rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \dec_MUL_MUL_MUL__rc__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \dec_MUL_MUL_MUL__oe__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \dec_MUL_MUL_MUL__oe__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \dec_MUL_MUL_MUL__write_cr0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \dec_MUL_MUL_MUL__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \dec_MUL_MUL_MUL__is_signed - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \dec_MUL_MUL_MUL__insn - cell \dec_MUL \dec_MUL - connect \raw_opcode_in \dec_MUL_raw_opcode_in - connect \bigendian \dec_MUL_bigendian - connect \MUL_MUL__insn_type \dec_MUL_MUL_MUL__insn_type - connect \MUL_MUL__fn_unit \dec_MUL_MUL_MUL__fn_unit - connect \MUL_MUL__imm_data__data \dec_MUL_MUL_MUL__imm_data__data - connect \MUL_MUL__imm_data__ok \dec_MUL_MUL_MUL__imm_data__ok - connect \MUL_MUL__rc__rc \dec_MUL_MUL_MUL__rc__rc - connect \MUL_MUL__rc__ok \dec_MUL_MUL_MUL__rc__ok - connect \MUL_MUL__oe__oe \dec_MUL_MUL_MUL__oe__oe - connect \MUL_MUL__oe__ok \dec_MUL_MUL_MUL__oe__ok - connect \MUL_MUL__write_cr0 \dec_MUL_MUL_MUL__write_cr0 - connect \MUL_MUL__is_32bit \dec_MUL_MUL_MUL__is_32bit - connect \MUL_MUL__is_signed \dec_MUL_MUL_MUL__is_signed - connect \MUL_MUL__insn \dec_MUL_MUL_MUL__insn - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:384" - wire width 32 \dec_SHIFT_ROT_raw_opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:385" - wire width 1 \dec_SHIFT_ROT_bigendian - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - 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\enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \dec_SHIFT_ROT_SHIFT_ROT_SHIFT_ROT__insn_type - attribute \enum_base_type "Function" - attribute \enum_value_00000000000 "NONE" - attribute \enum_value_00000000010 "ALU" - attribute \enum_value_00000000100 "LDST" - attribute \enum_value_00000001000 "SHIFT_ROT" - attribute \enum_value_00000010000 "LOGICAL" - attribute \enum_value_00000100000 "BRANCH" - attribute \enum_value_00001000000 "CR" - attribute \enum_value_00010000000 "TRAP" - attribute \enum_value_00100000000 "MUL" - attribute \enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 \dec_SHIFT_ROT_SHIFT_ROT_SHIFT_ROT__fn_unit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \dec_SHIFT_ROT_SHIFT_ROT_SHIFT_ROT__imm_data__data - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \dec_SHIFT_ROT_SHIFT_ROT_SHIFT_ROT__imm_data__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \dec_SHIFT_ROT_SHIFT_ROT_SHIFT_ROT__rc__rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \dec_SHIFT_ROT_SHIFT_ROT_SHIFT_ROT__rc__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \dec_SHIFT_ROT_SHIFT_ROT_SHIFT_ROT__oe__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \dec_SHIFT_ROT_SHIFT_ROT_SHIFT_ROT__oe__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \dec_SHIFT_ROT_SHIFT_ROT_SHIFT_ROT__write_cr0 - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \dec_SHIFT_ROT_SHIFT_ROT_SHIFT_ROT__input_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \dec_SHIFT_ROT_SHIFT_ROT_SHIFT_ROT__output_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \dec_SHIFT_ROT_SHIFT_ROT_SHIFT_ROT__input_cr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \dec_SHIFT_ROT_SHIFT_ROT_SHIFT_ROT__output_cr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \dec_SHIFT_ROT_SHIFT_ROT_SHIFT_ROT__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \dec_SHIFT_ROT_SHIFT_ROT_SHIFT_ROT__is_signed - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \dec_SHIFT_ROT_SHIFT_ROT_SHIFT_ROT__insn - cell \dec_SHIFT_ROT \dec_SHIFT_ROT - connect \raw_opcode_in \dec_SHIFT_ROT_raw_opcode_in - connect \bigendian \dec_SHIFT_ROT_bigendian - connect \SHIFT_ROT_SHIFT_ROT__insn_type \dec_SHIFT_ROT_SHIFT_ROT_SHIFT_ROT__insn_type - connect \SHIFT_ROT_SHIFT_ROT__fn_unit \dec_SHIFT_ROT_SHIFT_ROT_SHIFT_ROT__fn_unit - connect \SHIFT_ROT_SHIFT_ROT__imm_data__data \dec_SHIFT_ROT_SHIFT_ROT_SHIFT_ROT__imm_data__data - connect \SHIFT_ROT_SHIFT_ROT__imm_data__ok \dec_SHIFT_ROT_SHIFT_ROT_SHIFT_ROT__imm_data__ok - connect \SHIFT_ROT_SHIFT_ROT__rc__rc \dec_SHIFT_ROT_SHIFT_ROT_SHIFT_ROT__rc__rc - connect \SHIFT_ROT_SHIFT_ROT__rc__ok \dec_SHIFT_ROT_SHIFT_ROT_SHIFT_ROT__rc__ok - connect \SHIFT_ROT_SHIFT_ROT__oe__oe \dec_SHIFT_ROT_SHIFT_ROT_SHIFT_ROT__oe__oe - connect \SHIFT_ROT_SHIFT_ROT__oe__ok \dec_SHIFT_ROT_SHIFT_ROT_SHIFT_ROT__oe__ok - connect \SHIFT_ROT_SHIFT_ROT__write_cr0 \dec_SHIFT_ROT_SHIFT_ROT_SHIFT_ROT__write_cr0 - connect \SHIFT_ROT_SHIFT_ROT__input_carry \dec_SHIFT_ROT_SHIFT_ROT_SHIFT_ROT__input_carry - connect \SHIFT_ROT_SHIFT_ROT__output_carry \dec_SHIFT_ROT_SHIFT_ROT_SHIFT_ROT__output_carry - connect \SHIFT_ROT_SHIFT_ROT__input_cr \dec_SHIFT_ROT_SHIFT_ROT_SHIFT_ROT__input_cr - connect \SHIFT_ROT_SHIFT_ROT__output_cr \dec_SHIFT_ROT_SHIFT_ROT_SHIFT_ROT__output_cr - connect \SHIFT_ROT_SHIFT_ROT__is_32bit \dec_SHIFT_ROT_SHIFT_ROT_SHIFT_ROT__is_32bit - connect \SHIFT_ROT_SHIFT_ROT__is_signed \dec_SHIFT_ROT_SHIFT_ROT_SHIFT_ROT__is_signed - connect \SHIFT_ROT_SHIFT_ROT__insn \dec_SHIFT_ROT_SHIFT_ROT_SHIFT_ROT__insn - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:384" - wire width 32 \dec_LDST_raw_opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:385" - wire width 1 \dec_LDST_bigendian - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 7 \dec_LDST_LDST_LDST__insn_type - attribute \enum_base_type "Function" - attribute \enum_value_00000000000 "NONE" - attribute \enum_value_00000000010 "ALU" - attribute \enum_value_00000000100 "LDST" - attribute \enum_value_00000001000 "SHIFT_ROT" - attribute \enum_value_00000010000 "LOGICAL" - attribute \enum_value_00000100000 "BRANCH" - attribute \enum_value_00001000000 "CR" - attribute \enum_value_00010000000 "TRAP" - attribute \enum_value_00100000000 "MUL" - attribute \enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 11 \dec_LDST_LDST_LDST__fn_unit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 64 \dec_LDST_LDST_LDST__imm_data__data - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \dec_LDST_LDST_LDST__imm_data__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \dec_LDST_LDST_LDST__zero_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \dec_LDST_LDST_LDST__rc__rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \dec_LDST_LDST_LDST__rc__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \dec_LDST_LDST_LDST__oe__oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \dec_LDST_LDST_LDST__oe__ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \dec_LDST_LDST_LDST__is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \dec_LDST_LDST_LDST__is_signed - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 4 \dec_LDST_LDST_LDST__data_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \dec_LDST_LDST_LDST__byte_reverse - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 1 \dec_LDST_LDST_LDST__sign_extend - attribute \enum_base_type "LDSTMode" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "update" - attribute \enum_value_10 "cix" - attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 2 \dec_LDST_LDST_LDST__ldst_mode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/fu/base_input_record.py:18" - wire width 32 \dec_LDST_LDST_LDST__insn - cell \dec_LDST \dec_LDST - connect \raw_opcode_in \dec_LDST_raw_opcode_in - connect \bigendian \dec_LDST_bigendian - connect \LDST_LDST__insn_type \dec_LDST_LDST_LDST__insn_type - connect \LDST_LDST__fn_unit \dec_LDST_LDST_LDST__fn_unit - connect \LDST_LDST__imm_data__data \dec_LDST_LDST_LDST__imm_data__data - connect \LDST_LDST__imm_data__ok \dec_LDST_LDST_LDST__imm_data__ok - connect \LDST_LDST__zero_a \dec_LDST_LDST_LDST__zero_a - connect \LDST_LDST__rc__rc \dec_LDST_LDST_LDST__rc__rc - connect \LDST_LDST__rc__ok \dec_LDST_LDST_LDST__rc__ok - connect \LDST_LDST__oe__oe \dec_LDST_LDST_LDST__oe__oe - connect \LDST_LDST__oe__ok \dec_LDST_LDST_LDST__oe__ok - connect \LDST_LDST__is_32bit \dec_LDST_LDST_LDST__is_32bit - connect \LDST_LDST__is_signed \dec_LDST_LDST_LDST__is_signed - connect \LDST_LDST__data_len \dec_LDST_LDST_LDST__data_len - connect \LDST_LDST__byte_reverse \dec_LDST_LDST_LDST__byte_reverse - connect \LDST_LDST__sign_extend \dec_LDST_LDST_LDST__sign_extend - connect \LDST_LDST__ldst_mode \dec_LDST_LDST_LDST__ldst_mode - connect \LDST_LDST__insn \dec_LDST_LDST_LDST__insn - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" - wire width 9 \rdpick_INT_ra_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" - wire width 9 \rdpick_INT_ra_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" - wire width 1 \rdpick_INT_ra_en_o - cell \rdpick_INT_ra \rdpick_INT_ra - connect \i \rdpick_INT_ra_i - connect \o \rdpick_INT_ra_o - connect \en_o \rdpick_INT_ra_en_o - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" - wire width 8 \rdpick_INT_rb_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" - wire width 8 \rdpick_INT_rb_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" - wire width 1 \rdpick_INT_rb_en_o - cell \rdpick_INT_rb \rdpick_INT_rb - connect \i \rdpick_INT_rb_i - connect \o \rdpick_INT_rb_o - connect \en_o \rdpick_INT_rb_en_o - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" - wire width 2 \rdpick_INT_rc_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" - wire width 2 \rdpick_INT_rc_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" - wire width 1 \rdpick_INT_rc_en_o - cell \rdpick_INT_rc \rdpick_INT_rc - connect \i \rdpick_INT_rc_i - connect \o \rdpick_INT_rc_o - connect \en_o \rdpick_INT_rc_en_o - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" - wire width 6 \rdpick_XER_xer_so_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" - wire width 6 \rdpick_XER_xer_so_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" - wire width 1 \rdpick_XER_xer_so_en_o - cell \rdpick_XER_xer_so \rdpick_XER_xer_so - connect \i \rdpick_XER_xer_so_i - connect \o \rdpick_XER_xer_so_o - connect \en_o \rdpick_XER_xer_so_en_o - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" - wire width 3 \rdpick_XER_xer_ca_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" - wire width 3 \rdpick_XER_xer_ca_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" - wire width 1 \rdpick_XER_xer_ca_en_o - cell \rdpick_XER_xer_ca \rdpick_XER_xer_ca - connect \i \rdpick_XER_xer_ca_i - connect \o \rdpick_XER_xer_ca_o - connect \en_o \rdpick_XER_xer_ca_en_o - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" - wire width 1 \rdpick_XER_xer_ov_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" - wire width 1 \rdpick_XER_xer_ov_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" - wire width 1 \rdpick_XER_xer_ov_en_o - cell \rdpick_XER_xer_ov \rdpick_XER_xer_ov - connect \i \rdpick_XER_xer_ov_i - connect \o \rdpick_XER_xer_ov_o - connect \en_o \rdpick_XER_xer_ov_en_o - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" - wire width 1 \rdpick_CR_full_cr_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" - wire width 1 \rdpick_CR_full_cr_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" - wire width 1 \rdpick_CR_full_cr_en_o - cell \rdpick_CR_full_cr \rdpick_CR_full_cr - connect \i \rdpick_CR_full_cr_i - connect \o \rdpick_CR_full_cr_o - connect \en_o \rdpick_CR_full_cr_en_o - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" - wire width 2 \rdpick_CR_cr_a_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" - wire width 2 \rdpick_CR_cr_a_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" - wire width 1 \rdpick_CR_cr_a_en_o - cell \rdpick_CR_cr_a \rdpick_CR_cr_a - connect \i \rdpick_CR_cr_a_i - connect \o \rdpick_CR_cr_a_o - connect \en_o \rdpick_CR_cr_a_en_o - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" - wire width 1 \rdpick_CR_cr_b_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" - wire width 1 \rdpick_CR_cr_b_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" - wire width 1 \rdpick_CR_cr_b_en_o - cell \rdpick_CR_cr_b \rdpick_CR_cr_b - connect \i \rdpick_CR_cr_b_i - connect \o \rdpick_CR_cr_b_o - connect \en_o \rdpick_CR_cr_b_en_o - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" - wire width 1 \rdpick_CR_cr_c_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" - wire width 1 \rdpick_CR_cr_c_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" - wire width 1 \rdpick_CR_cr_c_en_o - cell \rdpick_CR_cr_c \rdpick_CR_cr_c - connect \i \rdpick_CR_cr_c_i - connect \o \rdpick_CR_cr_c_o - connect \en_o \rdpick_CR_cr_c_en_o - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" - wire width 3 \rdpick_FAST_fast1_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" - wire width 3 \rdpick_FAST_fast1_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" - wire width 1 \rdpick_FAST_fast1_en_o - cell \rdpick_FAST_fast1 \rdpick_FAST_fast1 - connect \i \rdpick_FAST_fast1_i - connect \o \rdpick_FAST_fast1_o - connect \en_o \rdpick_FAST_fast1_en_o - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" - wire width 2 \rdpick_FAST_fast2_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" - wire width 2 \rdpick_FAST_fast2_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" - wire width 1 \rdpick_FAST_fast2_en_o - cell \rdpick_FAST_fast2 \rdpick_FAST_fast2 - connect \i \rdpick_FAST_fast2_i - connect \o \rdpick_FAST_fast2_o - connect \en_o \rdpick_FAST_fast2_en_o - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" - wire width 1 \rdpick_SPR_spr1_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" - wire width 1 \rdpick_SPR_spr1_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" - wire width 1 \rdpick_SPR_spr1_en_o - cell \rdpick_SPR_spr1 \rdpick_SPR_spr1 - connect \i \rdpick_SPR_spr1_i - connect \o \rdpick_SPR_spr1_o - connect \en_o \rdpick_SPR_spr1_en_o - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" - wire width 10 \wrpick_INT_o_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" - wire width 10 \wrpick_INT_o_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" - wire width 1 \wrpick_INT_o_en_o - cell \wrpick_INT_o \wrpick_INT_o - connect \i \wrpick_INT_o_i - connect \o \wrpick_INT_o_o - connect \en_o \wrpick_INT_o_en_o - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" - wire width 1 \wrpick_CR_full_cr_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" - wire width 1 \wrpick_CR_full_cr_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" - wire width 1 \wrpick_CR_full_cr_en_o - cell \wrpick_CR_full_cr \wrpick_CR_full_cr - connect \i \wrpick_CR_full_cr_i - connect \o \wrpick_CR_full_cr_o - connect \en_o \wrpick_CR_full_cr_en_o - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" - wire width 6 \wrpick_CR_cr_a_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" - wire width 6 \wrpick_CR_cr_a_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" - wire width 1 \wrpick_CR_cr_a_en_o - cell \wrpick_CR_cr_a \wrpick_CR_cr_a - connect \i \wrpick_CR_cr_a_i - connect \o \wrpick_CR_cr_a_o - connect \en_o \wrpick_CR_cr_a_en_o - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" - wire width 3 \wrpick_XER_xer_ca_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" - wire width 3 \wrpick_XER_xer_ca_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" - wire width 1 \wrpick_XER_xer_ca_en_o - cell \wrpick_XER_xer_ca \wrpick_XER_xer_ca - connect \i \wrpick_XER_xer_ca_i - connect \o \wrpick_XER_xer_ca_o - connect \en_o \wrpick_XER_xer_ca_en_o - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" - wire width 4 \wrpick_XER_xer_ov_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" - wire width 4 \wrpick_XER_xer_ov_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" - wire width 1 \wrpick_XER_xer_ov_en_o - cell \wrpick_XER_xer_ov \wrpick_XER_xer_ov - connect \i \wrpick_XER_xer_ov_i - connect \o \wrpick_XER_xer_ov_o - connect \en_o \wrpick_XER_xer_ov_en_o - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" - wire width 4 \wrpick_XER_xer_so_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" - wire width 4 \wrpick_XER_xer_so_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" - wire width 1 \wrpick_XER_xer_so_en_o - cell \wrpick_XER_xer_so \wrpick_XER_xer_so - connect \i \wrpick_XER_xer_so_i - connect \o \wrpick_XER_xer_so_o - connect \en_o \wrpick_XER_xer_so_en_o - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" - wire width 5 \wrpick_FAST_fast1_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" - wire width 5 \wrpick_FAST_fast1_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" - wire width 1 \wrpick_FAST_fast1_en_o - cell \wrpick_FAST_fast1 \wrpick_FAST_fast1 - connect \i \wrpick_FAST_fast1_i - connect \o \wrpick_FAST_fast1_o - connect \en_o \wrpick_FAST_fast1_en_o - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" - wire width 2 \wrpick_STATE_nia_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" - wire width 2 \wrpick_STATE_nia_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" - wire width 1 \wrpick_STATE_nia_en_o - cell \wrpick_STATE_nia \wrpick_STATE_nia - connect \i \wrpick_STATE_nia_i - connect \o \wrpick_STATE_nia_o - connect \en_o \wrpick_STATE_nia_en_o - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" - wire width 1 \wrpick_STATE_msr_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" - wire width 1 \wrpick_STATE_msr_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" - wire width 1 \wrpick_STATE_msr_en_o - cell \wrpick_STATE_msr \wrpick_STATE_msr - connect \i \wrpick_STATE_msr_i - connect \o \wrpick_STATE_msr_o - connect \en_o \wrpick_STATE_msr_en_o - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" - wire width 1 \wrpick_SPR_spr1_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" - wire width 1 \wrpick_SPR_spr1_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" - wire width 1 \wrpick_SPR_spr1_en_o - cell \wrpick_SPR_spr1 \wrpick_SPR_spr1 - connect \i \wrpick_SPR_spr1_i - connect \o \wrpick_SPR_spr1_o - connect \en_o \wrpick_SPR_spr1_en_o - end - process $group_0 - assign \dec_ALU_raw_opcode_in 32'00000000000000000000000000000000 - assign \dec_ALU_raw_opcode_in \raw_insn_i - sync init - end - process $group_1 - assign \dec_ALU_bigendian 1'0 - assign \dec_ALU_bigendian \bigendian_i - sync init - end - process $group_2 - assign \dec_CR_raw_opcode_in 32'00000000000000000000000000000000 - assign \dec_CR_raw_opcode_in \raw_insn_i - sync init - end - process $group_3 - assign \dec_CR_bigendian 1'0 - assign \dec_CR_bigendian \bigendian_i - sync init - end - process $group_4 - assign \dec_BRANCH_raw_opcode_in 32'00000000000000000000000000000000 - assign \dec_BRANCH_raw_opcode_in \raw_insn_i - sync init - end - process $group_5 - assign \dec_BRANCH_bigendian 1'0 - assign \dec_BRANCH_bigendian \bigendian_i - sync init - end - process $group_6 - assign \dec_LOGICAL_raw_opcode_in 32'00000000000000000000000000000000 - assign \dec_LOGICAL_raw_opcode_in \raw_insn_i - sync init - end - process $group_7 - assign \dec_LOGICAL_bigendian 1'0 - assign \dec_LOGICAL_bigendian \bigendian_i - sync init - end - process $group_8 - assign \dec_SPR_raw_opcode_in 32'00000000000000000000000000000000 - assign \dec_SPR_raw_opcode_in \raw_insn_i - sync init - end - process $group_9 - assign \dec_SPR_bigendian 1'0 - assign \dec_SPR_bigendian \bigendian_i - sync init - end - process $group_10 - assign \dec_DIV_raw_opcode_in 32'00000000000000000000000000000000 - assign \dec_DIV_raw_opcode_in \raw_insn_i - sync init - end - process $group_11 - assign \dec_DIV_bigendian 1'0 - assign \dec_DIV_bigendian \bigendian_i - sync init - end - process $group_12 - assign \dec_MUL_raw_opcode_in 32'00000000000000000000000000000000 - assign \dec_MUL_raw_opcode_in \raw_insn_i - sync init - end - process $group_13 - assign \dec_MUL_bigendian 1'0 - assign \dec_MUL_bigendian \bigendian_i - sync init - end - process $group_14 - assign \dec_SHIFT_ROT_raw_opcode_in 32'00000000000000000000000000000000 - assign \dec_SHIFT_ROT_raw_opcode_in \raw_insn_i - sync init - end - process $group_15 - assign \dec_SHIFT_ROT_bigendian 1'0 - assign \dec_SHIFT_ROT_bigendian \bigendian_i - sync init - end - process $group_16 - assign \dec_LDST_raw_opcode_in 32'00000000000000000000000000000000 - assign \dec_LDST_raw_opcode_in \raw_insn_i - sync init - end - process $group_17 - assign \dec_LDST_bigendian 1'0 - assign \dec_LDST_bigendian \bigendian_i - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:171" - wire width 1 \en_alu0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:172" - wire width 1 $160 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:172" - wire width 11 $161 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:172" - cell $and $162 - parameter \A_SIGNED 0 - parameter \A_WIDTH 11 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 11 - connect \A \core_core_fn_unit - connect \B 2'10 - connect \Y $161 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:172" - cell $reduce_bool $163 - parameter \A_SIGNED 0 - parameter \A_WIDTH 11 - parameter \Y_WIDTH 1 - connect \A $161 - connect \Y $160 - end - process $group_18 - assign \en_alu0 1'0 - assign \en_alu0 $160 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:161" - wire width 10 \fu_enable - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:171" - wire width 1 \en_cr0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:171" - wire width 1 \en_branch0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:171" - wire width 1 \en_trap0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:171" - wire width 1 \en_logical0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:171" - wire width 1 \en_spr0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:171" - wire width 1 \en_div0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:171" - wire width 1 \en_mul0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:171" - wire width 1 \en_shiftrot0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:171" - wire width 1 \en_ldst0 - process $group_19 - assign \fu_enable 10'0000000000 - assign \fu_enable [0] \en_alu0 - assign \fu_enable [1] \en_cr0 - assign \fu_enable [2] \en_branch0 - assign \fu_enable [3] \en_trap0 - assign \fu_enable [4] \en_logical0 - assign \fu_enable [5] \en_spr0 - assign \fu_enable [6] \en_div0 - assign \fu_enable [7] \en_mul0 - assign \fu_enable [8] \en_shiftrot0 - assign \fu_enable [9] \en_ldst0 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:172" - wire width 1 $164 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:172" - wire width 11 $165 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:172" - cell $and $166 - parameter \A_SIGNED 0 - parameter \A_WIDTH 11 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 11 - connect \A \core_core_fn_unit - connect \B 7'1000000 - connect \Y $165 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:172" - cell $reduce_bool $167 - parameter \A_SIGNED 0 - parameter \A_WIDTH 11 - parameter \Y_WIDTH 1 - connect \A $165 - connect \Y $164 - end - process $group_20 - assign \en_cr0 1'0 - assign \en_cr0 $164 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:172" - wire width 1 $168 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:172" - wire width 11 $169 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:172" - cell $and $170 - parameter \A_SIGNED 0 - parameter \A_WIDTH 11 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 11 - connect \A \core_core_fn_unit - connect \B 6'100000 - connect \Y $169 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:172" - cell $reduce_bool $171 - parameter \A_SIGNED 0 - parameter \A_WIDTH 11 - parameter \Y_WIDTH 1 - connect \A $169 - connect \Y $168 - end - process $group_21 - assign \en_branch0 1'0 - assign \en_branch0 $168 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:172" - wire width 1 $172 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:172" - wire width 11 $173 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:172" - cell $and $174 - parameter \A_SIGNED 0 - parameter \A_WIDTH 11 - parameter \B_SIGNED 0 - parameter \B_WIDTH 8 - parameter \Y_WIDTH 11 - connect \A \core_core_fn_unit - connect \B 8'10000000 - connect \Y $173 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:172" - cell $reduce_bool $175 - parameter \A_SIGNED 0 - parameter \A_WIDTH 11 - parameter \Y_WIDTH 1 - connect \A $173 - connect \Y $172 - end - process $group_22 - assign \en_trap0 1'0 - assign \en_trap0 $172 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:172" - wire width 1 $176 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:172" - wire width 11 $177 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:172" - cell $and $178 - parameter \A_SIGNED 0 - parameter \A_WIDTH 11 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 11 - connect \A \core_core_fn_unit - connect \B 5'10000 - connect \Y $177 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:172" - cell $reduce_bool $179 - parameter \A_SIGNED 0 - parameter \A_WIDTH 11 - parameter \Y_WIDTH 1 - connect \A $177 - connect \Y $176 - end - process $group_23 - assign \en_logical0 1'0 - assign \en_logical0 $176 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:172" - wire width 1 $180 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:172" - wire width 11 $181 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:172" - cell $and $182 - parameter \A_SIGNED 0 - parameter \A_WIDTH 11 - parameter \B_SIGNED 0 - parameter \B_WIDTH 11 - parameter \Y_WIDTH 11 - connect \A \core_core_fn_unit - connect \B 11'10000000000 - connect \Y $181 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:172" - cell $reduce_bool $183 - parameter \A_SIGNED 0 - parameter \A_WIDTH 11 - parameter \Y_WIDTH 1 - connect \A $181 - connect \Y $180 - end - process $group_24 - assign \en_spr0 1'0 - assign \en_spr0 $180 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:172" - wire width 1 $184 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:172" - wire width 11 $185 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:172" - cell $and $186 - parameter \A_SIGNED 0 - parameter \A_WIDTH 11 - parameter \B_SIGNED 0 - parameter \B_WIDTH 10 - parameter \Y_WIDTH 11 - connect \A \core_core_fn_unit - connect \B 10'1000000000 - connect \Y $185 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:172" - cell $reduce_bool $187 - parameter \A_SIGNED 0 - parameter \A_WIDTH 11 - parameter \Y_WIDTH 1 - connect \A $185 - connect \Y $184 - end - process $group_25 - assign \en_div0 1'0 - assign \en_div0 $184 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:172" - wire width 1 $188 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:172" - wire width 11 $189 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:172" - cell $and $190 - parameter \A_SIGNED 0 - parameter \A_WIDTH 11 - parameter \B_SIGNED 0 - parameter \B_WIDTH 9 - parameter \Y_WIDTH 11 - connect \A \core_core_fn_unit - connect \B 9'100000000 - connect \Y $189 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:172" - cell $reduce_bool $191 - parameter \A_SIGNED 0 - parameter \A_WIDTH 11 - parameter \Y_WIDTH 1 - connect \A $189 - connect \Y $188 - end - process $group_26 - assign \en_mul0 1'0 - assign \en_mul0 $188 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:172" - wire width 1 $192 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:172" - wire width 11 $193 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:172" - cell $and $194 - parameter \A_SIGNED 0 - parameter \A_WIDTH 11 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 11 - connect \A \core_core_fn_unit - connect \B 4'1000 - connect \Y $193 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:172" - cell $reduce_bool $195 - parameter \A_SIGNED 0 - parameter \A_WIDTH 11 - parameter \Y_WIDTH 1 - connect \A $193 - connect \Y $192 - end - process $group_27 - assign \en_shiftrot0 1'0 - assign \en_shiftrot0 $192 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:172" - wire width 1 $196 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:172" - wire width 11 $197 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:172" - cell $and $198 - parameter \A_SIGNED 0 - parameter \A_WIDTH 11 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 11 - connect \A \core_core_fn_unit - connect \B 3'100 - connect \Y $197 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:172" - cell $reduce_bool $199 - parameter \A_SIGNED 0 - parameter \A_WIDTH 11 - parameter \Y_WIDTH 1 - connect \A $197 - connect \Y $196 - end - process $group_28 - assign \en_ldst0 1'0 - assign \en_ldst0 $196 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:176" - wire width 2 \counter - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:176" - wire width 2 \counter$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:177" - wire width 1 $200 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:177" - cell $ne $201 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \counter - connect \B 1'0 - connect \Y $200 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:178" - wire width 3 $202 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:178" - wire width 3 $203 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:178" - cell $sub $204 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 3 - connect \A \counter - connect \B 1'1 - connect \Y $203 - end - connect $202 $203 - process $group_29 - assign \counter$next \counter - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:177" - switch { $200 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:177" - case 1'1 - assign \counter$next $202 [1:0] - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" - switch { \ivalid_i } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" - switch \core_core_insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:184" - attribute \nmigen.decoding "OP_ATTN/5" - case 7'0000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" - attribute \nmigen.decoding "OP_NOP/1" - case 7'0000001 - assign \counter$next 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" - attribute \nmigen.decoding "" - case - end - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \counter$next 2'00 - end - sync init - update \counter 2'00 - sync posedge \coresync_clk - update \counter \counter$next - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:177" - wire width 1 $205 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:177" - cell $ne $206 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \counter - connect \B 1'0 - connect \Y $205 - end - process $group_30 - assign \corebusy_o 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:177" - switch { $205 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:177" - case 1'1 - assign \corebusy_o 1'1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" - switch { \ivalid_i } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" - switch \core_core_insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:184" - attribute \nmigen.decoding "OP_ATTN/5" - case 7'0000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" - attribute \nmigen.decoding "OP_NOP/1" - case 7'0000001 - assign \corebusy_o 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" - attribute \nmigen.decoding "" - case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" - switch { \fu_enable [0] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" - case 1'1 - assign \corebusy_o \fus_cu_busy_o - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" - switch { \fu_enable [1] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" - case 1'1 - assign \corebusy_o \fus_cu_busy_o$5 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" - switch { \fu_enable [2] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" - case 1'1 - assign \corebusy_o \fus_cu_busy_o$8 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" - switch { \fu_enable [3] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" - case 1'1 - assign \corebusy_o \fus_cu_busy_o$11 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" - switch { \fu_enable [4] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" - case 1'1 - assign \corebusy_o \fus_cu_busy_o$14 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" - switch { \fu_enable [5] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" - case 1'1 - assign \corebusy_o \fus_cu_busy_o$17 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" - switch { \fu_enable [6] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" - case 1'1 - assign \corebusy_o \fus_cu_busy_o$20 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" - switch { \fu_enable [7] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" - case 1'1 - assign \corebusy_o \fus_cu_busy_o$23 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" - switch { \fu_enable [8] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" - case 1'1 - assign \corebusy_o \fus_cu_busy_o$26 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" - switch { \fu_enable [9] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" - case 1'1 - assign \corebusy_o \fus_cu_busy_o$29 - end - end - end - sync init - end - process $group_31 - assign \core_terminate_o$next \core_terminate_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" - switch { \ivalid_i } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" - switch \core_core_insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:184" - attribute \nmigen.decoding "OP_ATTN/5" - case 7'0000101 - assign \core_terminate_o$next 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" - attribute \nmigen.decoding "OP_NOP/1" - case 7'0000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" - attribute \nmigen.decoding "" - case - end - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \core_terminate_o$next 1'0 - end - sync init - update \core_terminate_o 1'0 - sync posedge \coresync_clk - update \core_terminate_o \core_terminate_o$next - end - process $group_32 - assign \fus_oper_i_alu_alu0__insn_type 7'0000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" - switch { \ivalid_i } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" - switch \core_core_insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:184" - attribute \nmigen.decoding "OP_ATTN/5" - case 7'0000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" - attribute \nmigen.decoding "OP_NOP/1" - case 7'0000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" - attribute \nmigen.decoding "" - case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" - switch { \fu_enable [0] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" - case 1'1 - assign \fus_oper_i_alu_alu0__insn_type \dec_ALU_ALU_ALU__insn_type - end - end - end - sync init - end - process $group_33 - assign \fus_oper_i_alu_alu0__fn_unit 11'00000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" - switch { \ivalid_i } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" - switch \core_core_insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:184" - attribute \nmigen.decoding "OP_ATTN/5" - case 7'0000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" - attribute \nmigen.decoding "OP_NOP/1" - case 7'0000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" - attribute \nmigen.decoding "" - case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" - switch { \fu_enable [0] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" - case 1'1 - assign \fus_oper_i_alu_alu0__fn_unit \dec_ALU_ALU_ALU__fn_unit - end - end - end - sync init - end - process $group_34 - assign \fus_oper_i_alu_alu0__imm_data__data 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \fus_oper_i_alu_alu0__imm_data__ok 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" - switch { \ivalid_i } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" - switch \core_core_insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:184" - attribute \nmigen.decoding "OP_ATTN/5" - case 7'0000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" - attribute \nmigen.decoding "OP_NOP/1" - case 7'0000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" - attribute \nmigen.decoding "" - case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" - switch { \fu_enable [0] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" - case 1'1 - assign { \fus_oper_i_alu_alu0__imm_data__ok \fus_oper_i_alu_alu0__imm_data__data } { \dec_ALU_ALU_ALU__imm_data__ok \dec_ALU_ALU_ALU__imm_data__data } - end - end - end - sync init - end - process $group_36 - assign \fus_oper_i_alu_alu0__rc__rc 1'0 - assign \fus_oper_i_alu_alu0__rc__ok 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" - switch { \ivalid_i } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" - switch \core_core_insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:184" - attribute \nmigen.decoding "OP_ATTN/5" - case 7'0000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" - attribute \nmigen.decoding "OP_NOP/1" - case 7'0000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" - attribute \nmigen.decoding "" - case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" - switch { \fu_enable [0] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" - case 1'1 - assign { \fus_oper_i_alu_alu0__rc__ok \fus_oper_i_alu_alu0__rc__rc } { \dec_ALU_ALU_ALU__rc__ok \dec_ALU_ALU_ALU__rc__rc } - end - end - end - sync init - end - process $group_38 - assign \fus_oper_i_alu_alu0__oe__oe 1'0 - assign \fus_oper_i_alu_alu0__oe__ok 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" - switch { \ivalid_i } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" - switch \core_core_insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:184" - attribute \nmigen.decoding "OP_ATTN/5" - case 7'0000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" - attribute \nmigen.decoding "OP_NOP/1" - case 7'0000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" - attribute \nmigen.decoding "" - case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" - switch { \fu_enable [0] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" - case 1'1 - assign { \fus_oper_i_alu_alu0__oe__ok \fus_oper_i_alu_alu0__oe__oe } { \dec_ALU_ALU_ALU__oe__ok \dec_ALU_ALU_ALU__oe__oe } - end - end - end - sync init - end - process $group_40 - assign \fus_oper_i_alu_alu0__invert_in 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" - switch { \ivalid_i } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" - switch \core_core_insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:184" - attribute \nmigen.decoding "OP_ATTN/5" - case 7'0000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" - attribute \nmigen.decoding "OP_NOP/1" - case 7'0000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" - attribute \nmigen.decoding "" - case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" - switch { \fu_enable [0] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" - case 1'1 - assign \fus_oper_i_alu_alu0__invert_in \dec_ALU_ALU_ALU__invert_in - end - end - end - sync init - end - process $group_41 - assign \fus_oper_i_alu_alu0__zero_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" - switch { \ivalid_i } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" - switch \core_core_insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:184" - attribute \nmigen.decoding "OP_ATTN/5" - case 7'0000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" - attribute \nmigen.decoding "OP_NOP/1" - case 7'0000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" - attribute \nmigen.decoding "" - case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" - switch { \fu_enable [0] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" - case 1'1 - assign \fus_oper_i_alu_alu0__zero_a \dec_ALU_ALU_ALU__zero_a - end - end - end - sync init - end - process $group_42 - assign \fus_oper_i_alu_alu0__invert_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" - switch { \ivalid_i } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" - switch \core_core_insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:184" - attribute \nmigen.decoding "OP_ATTN/5" - case 7'0000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" - attribute \nmigen.decoding "OP_NOP/1" - case 7'0000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" - attribute \nmigen.decoding "" - case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" - switch { \fu_enable [0] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" - case 1'1 - assign \fus_oper_i_alu_alu0__invert_out \dec_ALU_ALU_ALU__invert_out - end - end - end - sync init - end - process $group_43 - assign \fus_oper_i_alu_alu0__write_cr0 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" - switch { \ivalid_i } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" - switch \core_core_insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:184" - attribute \nmigen.decoding "OP_ATTN/5" - case 7'0000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" - attribute \nmigen.decoding "OP_NOP/1" - case 7'0000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" - attribute \nmigen.decoding "" - case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" - switch { \fu_enable [0] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" - case 1'1 - assign \fus_oper_i_alu_alu0__write_cr0 \dec_ALU_ALU_ALU__write_cr0 - end - end - end - sync init - end - process $group_44 - assign \fus_oper_i_alu_alu0__input_carry 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" - switch { \ivalid_i } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" - switch \core_core_insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:184" - attribute \nmigen.decoding "OP_ATTN/5" - case 7'0000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" - attribute \nmigen.decoding "OP_NOP/1" - case 7'0000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" - attribute \nmigen.decoding "" - case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" - switch { \fu_enable [0] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" - case 1'1 - assign \fus_oper_i_alu_alu0__input_carry \dec_ALU_ALU_ALU__input_carry - end - end - end - sync init - end - process $group_45 - assign \fus_oper_i_alu_alu0__output_carry 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" - switch { \ivalid_i } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" - switch \core_core_insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:184" - attribute \nmigen.decoding "OP_ATTN/5" - case 7'0000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" - attribute \nmigen.decoding "OP_NOP/1" - case 7'0000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" - attribute \nmigen.decoding "" - case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" - switch { \fu_enable [0] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" - case 1'1 - assign \fus_oper_i_alu_alu0__output_carry \dec_ALU_ALU_ALU__output_carry - end - end - end - sync init - end - process $group_46 - assign \fus_oper_i_alu_alu0__is_32bit 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" - switch { \ivalid_i } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" - switch \core_core_insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:184" - attribute \nmigen.decoding "OP_ATTN/5" - case 7'0000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" - attribute \nmigen.decoding "OP_NOP/1" - case 7'0000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" - attribute \nmigen.decoding "" - case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" - switch { \fu_enable [0] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" - case 1'1 - assign \fus_oper_i_alu_alu0__is_32bit \dec_ALU_ALU_ALU__is_32bit - end - end - end - sync init - end - process $group_47 - assign \fus_oper_i_alu_alu0__is_signed 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" - switch { \ivalid_i } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" - switch \core_core_insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:184" - attribute \nmigen.decoding "OP_ATTN/5" - case 7'0000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" - attribute \nmigen.decoding "OP_NOP/1" - case 7'0000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" - attribute \nmigen.decoding "" - case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" - switch { \fu_enable [0] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" - case 1'1 - assign \fus_oper_i_alu_alu0__is_signed \dec_ALU_ALU_ALU__is_signed - end - end - end - sync init - end - process $group_48 - assign \fus_oper_i_alu_alu0__data_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" - switch { \ivalid_i } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" - switch \core_core_insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:184" - attribute \nmigen.decoding "OP_ATTN/5" - case 7'0000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" - attribute \nmigen.decoding "OP_NOP/1" - case 7'0000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" - attribute \nmigen.decoding "" - case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" - switch { \fu_enable [0] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" - case 1'1 - assign \fus_oper_i_alu_alu0__data_len \dec_ALU_ALU_ALU__data_len - end - end - end - sync init - end - process $group_49 - assign \fus_oper_i_alu_alu0__insn 32'00000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" - switch { \ivalid_i } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" - switch \core_core_insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:184" - attribute \nmigen.decoding "OP_ATTN/5" - case 7'0000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" - attribute \nmigen.decoding "OP_NOP/1" - case 7'0000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" - attribute \nmigen.decoding "" - case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" - switch { \fu_enable [0] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" - case 1'1 - assign \fus_oper_i_alu_alu0__insn \dec_ALU_ALU_ALU__insn - end - end - end - sync init - end - process $group_50 - assign \fus_cu_issue_i 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" - switch { \ivalid_i } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" - switch \core_core_insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:184" - attribute \nmigen.decoding "OP_ATTN/5" - case 7'0000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" - attribute \nmigen.decoding "OP_NOP/1" - case 7'0000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" - attribute \nmigen.decoding "" - case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" - switch { \fu_enable [0] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" - case 1'1 - assign \fus_cu_issue_i \issue_i - end - end - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" - wire width 4 $207 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" - wire width 1 $208 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" - cell $and $209 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \core_core_oe - connect \B \core_core_oe_ok - connect \Y $208 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" - wire width 3 $210 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" - cell $and $211 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 3 - connect \A \core_xer_in - connect \B 1'1 - connect \Y $210 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" - wire width 1 $212 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" - cell $eq $213 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $210 - connect \B 1'1 - connect \Y $212 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" - wire width 1 $214 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" - cell $or $215 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $208 - connect \B $212 - connect \Y $214 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81" - wire width 1 $216 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81" - cell $and $217 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \core_core_rc - connect \B \core_core_rc_ok - connect \Y $216 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81" - wire width 1 $218 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81" - cell $or $219 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $214 - connect \B $216 - connect \Y $218 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:86" - wire width 1 $220 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:86" - cell $eq $221 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \core_core_input_carry - connect \B 2'10 - connect \Y $220 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:87" - wire width 3 $222 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:87" - cell $and $223 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A \core_xer_in - connect \B 3'100 - connect \Y $222 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:87" - wire width 1 $224 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:87" - cell $eq $225 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A $222 - connect \B 3'100 - connect \Y $224 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:87" - wire width 1 $226 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:87" - cell $or $227 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $220 - connect \B $224 - connect \Y $226 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" - cell $not $228 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A { $226 $218 \core_reg2_ok \core_reg1_ok } - connect \Y $207 - end - process $group_51 - assign \fus_cu_rdmaskn_i 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" - switch { \ivalid_i } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" - switch \core_core_insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:184" - attribute \nmigen.decoding "OP_ATTN/5" - case 7'0000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" - attribute \nmigen.decoding "OP_NOP/1" - case 7'0000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" - attribute \nmigen.decoding "" - case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" - switch { \fu_enable [0] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" - case 1'1 - assign \fus_cu_rdmaskn_i $207 - end - end - end - sync init - end - process $group_52 - assign \fus_oper_i_alu_cr0__insn_type 7'0000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" - switch { \ivalid_i } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" - switch \core_core_insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:184" - attribute \nmigen.decoding "OP_ATTN/5" - case 7'0000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" - attribute \nmigen.decoding "OP_NOP/1" - case 7'0000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" - attribute \nmigen.decoding "" - case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" - switch { \fu_enable [1] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" - case 1'1 - assign \fus_oper_i_alu_cr0__insn_type \dec_CR_CR_CR__insn_type - end - end - end - sync init - end - process $group_53 - assign \fus_oper_i_alu_cr0__fn_unit 11'00000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" - switch { \ivalid_i } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" - switch \core_core_insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:184" - attribute \nmigen.decoding "OP_ATTN/5" - case 7'0000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" - attribute \nmigen.decoding "OP_NOP/1" - case 7'0000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" - attribute \nmigen.decoding "" - case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" - switch { \fu_enable [1] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" - case 1'1 - assign \fus_oper_i_alu_cr0__fn_unit \dec_CR_CR_CR__fn_unit - end - end - end - sync init - end - process $group_54 - assign \fus_oper_i_alu_cr0__insn 32'00000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" - switch { \ivalid_i } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" - switch \core_core_insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:184" - attribute \nmigen.decoding "OP_ATTN/5" - case 7'0000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" - attribute \nmigen.decoding "OP_NOP/1" - case 7'0000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" - attribute \nmigen.decoding "" - case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" - switch { \fu_enable [1] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" - case 1'1 - assign \fus_oper_i_alu_cr0__insn \dec_CR_CR_CR__insn - end - end - end - sync init - end - process $group_55 - assign \fus_cu_issue_i$4 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" - switch { \ivalid_i } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" - switch \core_core_insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:184" - attribute \nmigen.decoding "OP_ATTN/5" - case 7'0000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" - attribute \nmigen.decoding "OP_NOP/1" - case 7'0000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" - attribute \nmigen.decoding "" - case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" - switch { \fu_enable [1] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" - case 1'1 - assign \fus_cu_issue_i$4 \issue_i - end - end - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" - wire width 6 $229 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" - cell $not $230 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \Y_WIDTH 6 - connect \A { \core_cr_in2_ok$2 \core_cr_in2_ok \core_cr_in1_ok \core_core_cr_rd_ok \core_reg2_ok \core_reg1_ok } - connect \Y $229 - end - process $group_56 - assign \fus_cu_rdmaskn_i$6 6'000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" - switch { \ivalid_i } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" - switch \core_core_insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:184" - attribute \nmigen.decoding "OP_ATTN/5" - case 7'0000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" - attribute \nmigen.decoding "OP_NOP/1" - case 7'0000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" - attribute \nmigen.decoding "" - case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" - switch { \fu_enable [1] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" - case 1'1 - assign \fus_cu_rdmaskn_i$6 $229 - end - end - end - sync init - end - process $group_57 - assign \fus_oper_i_alu_branch0__cia 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" - switch { \ivalid_i } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" - switch \core_core_insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:184" - attribute \nmigen.decoding "OP_ATTN/5" - case 7'0000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" - attribute \nmigen.decoding "OP_NOP/1" - case 7'0000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" - attribute \nmigen.decoding "" - case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" - switch { \fu_enable [2] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" - case 1'1 - assign \fus_oper_i_alu_branch0__cia \dec_BRANCH_BRANCH_BRANCH__cia - end - end - end - sync init - end - process $group_58 - assign \fus_oper_i_alu_branch0__insn_type 7'0000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" - switch { \ivalid_i } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" - switch \core_core_insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:184" - attribute \nmigen.decoding "OP_ATTN/5" - case 7'0000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" - attribute \nmigen.decoding "OP_NOP/1" - case 7'0000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" - attribute \nmigen.decoding "" - case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" - switch { \fu_enable [2] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" - case 1'1 - assign \fus_oper_i_alu_branch0__insn_type \dec_BRANCH_BRANCH_BRANCH__insn_type - end - end - end - sync init - end - process $group_59 - assign \fus_oper_i_alu_branch0__fn_unit 11'00000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" - switch { \ivalid_i } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" - switch \core_core_insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:184" - attribute \nmigen.decoding "OP_ATTN/5" - case 7'0000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" - attribute \nmigen.decoding "OP_NOP/1" - case 7'0000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" - attribute \nmigen.decoding "" - case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" - switch { \fu_enable [2] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" - case 1'1 - assign \fus_oper_i_alu_branch0__fn_unit \dec_BRANCH_BRANCH_BRANCH__fn_unit - end - end - end - sync init - end - process $group_60 - assign \fus_oper_i_alu_branch0__insn 32'00000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" - switch { \ivalid_i } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" - switch \core_core_insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:184" - attribute \nmigen.decoding "OP_ATTN/5" - case 7'0000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" - attribute \nmigen.decoding "OP_NOP/1" - case 7'0000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" - attribute \nmigen.decoding "" - case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" - switch { \fu_enable [2] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" - case 1'1 - assign \fus_oper_i_alu_branch0__insn \dec_BRANCH_BRANCH_BRANCH__insn - end - end - end - sync init - end - process $group_61 - assign \fus_oper_i_alu_branch0__imm_data__data 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \fus_oper_i_alu_branch0__imm_data__ok 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" - switch { \ivalid_i } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" - switch \core_core_insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:184" - attribute \nmigen.decoding "OP_ATTN/5" - case 7'0000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" - attribute \nmigen.decoding "OP_NOP/1" - case 7'0000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" - attribute \nmigen.decoding "" - case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" - switch { \fu_enable [2] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" - case 1'1 - assign { \fus_oper_i_alu_branch0__imm_data__ok \fus_oper_i_alu_branch0__imm_data__data } { \dec_BRANCH_BRANCH_BRANCH__imm_data__ok \dec_BRANCH_BRANCH_BRANCH__imm_data__data } - end - end - end - sync init - end - process $group_63 - assign \fus_oper_i_alu_branch0__lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" - switch { \ivalid_i } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" - switch \core_core_insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:184" - attribute \nmigen.decoding "OP_ATTN/5" - case 7'0000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" - attribute \nmigen.decoding "OP_NOP/1" - case 7'0000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" - attribute \nmigen.decoding "" - case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" - switch { \fu_enable [2] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" - case 1'1 - assign \fus_oper_i_alu_branch0__lk \dec_BRANCH_BRANCH_BRANCH__lk - end - end - end - sync init - end - process $group_64 - assign \fus_oper_i_alu_branch0__is_32bit 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" - switch { \ivalid_i } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" - switch \core_core_insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:184" - attribute \nmigen.decoding "OP_ATTN/5" - case 7'0000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" - attribute \nmigen.decoding "OP_NOP/1" - case 7'0000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" - attribute \nmigen.decoding "" - case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" - switch { \fu_enable [2] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" - case 1'1 - assign \fus_oper_i_alu_branch0__is_32bit \dec_BRANCH_BRANCH_BRANCH__is_32bit - end - end - end - sync init - end - process $group_65 - assign \fus_cu_issue_i$7 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" - switch { \ivalid_i } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" - switch \core_core_insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:184" - attribute \nmigen.decoding "OP_ATTN/5" - case 7'0000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" - attribute \nmigen.decoding "OP_NOP/1" - case 7'0000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" - attribute \nmigen.decoding "" - case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" - switch { \fu_enable [2] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" - case 1'1 - assign \fus_cu_issue_i$7 \issue_i - end - end - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" - wire width 3 $231 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" - cell $not $232 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A { \core_cr_in1_ok \core_fast2_ok \core_fast1_ok } - connect \Y $231 - end - process $group_66 - assign \fus_cu_rdmaskn_i$9 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" - switch { \ivalid_i } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" - switch \core_core_insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:184" - attribute \nmigen.decoding "OP_ATTN/5" - case 7'0000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" - attribute \nmigen.decoding "OP_NOP/1" - case 7'0000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" - attribute \nmigen.decoding "" - case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" - switch { \fu_enable [2] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" - case 1'1 - assign \fus_cu_rdmaskn_i$9 $231 - end - end - end - sync init - end - process $group_67 - assign \fus_oper_i_alu_trap0__insn_type 7'0000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" - switch { \ivalid_i } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" - switch \core_core_insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:184" - attribute \nmigen.decoding "OP_ATTN/5" - case 7'0000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" - attribute \nmigen.decoding "OP_NOP/1" - case 7'0000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" - attribute \nmigen.decoding "" - case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" - switch { \fu_enable [3] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" - case 1'1 - assign \fus_oper_i_alu_trap0__insn_type \core_core_insn_type - end - end - end - sync init - end - process $group_68 - assign \fus_oper_i_alu_trap0__fn_unit 11'00000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" - switch { \ivalid_i } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" - switch \core_core_insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:184" - attribute \nmigen.decoding "OP_ATTN/5" - case 7'0000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" - attribute \nmigen.decoding "OP_NOP/1" - case 7'0000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" - attribute \nmigen.decoding "" - case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" - switch { \fu_enable [3] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" - case 1'1 - assign \fus_oper_i_alu_trap0__fn_unit \core_core_fn_unit - end - end - end - sync init - end - process $group_69 - assign \fus_oper_i_alu_trap0__insn 32'00000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" - switch { \ivalid_i } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" - switch \core_core_insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:184" - attribute \nmigen.decoding "OP_ATTN/5" - case 7'0000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" - attribute \nmigen.decoding "OP_NOP/1" - case 7'0000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" - attribute \nmigen.decoding "" - case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" - switch { \fu_enable [3] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" - case 1'1 - assign \fus_oper_i_alu_trap0__insn \core_core_insn - end - end - end - sync init - end - process $group_70 - assign \fus_oper_i_alu_trap0__msr 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" - switch { \ivalid_i } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" - switch \core_core_insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:184" - attribute \nmigen.decoding "OP_ATTN/5" - case 7'0000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" - attribute \nmigen.decoding "OP_NOP/1" - case 7'0000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" - attribute \nmigen.decoding "" - case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" - switch { \fu_enable [3] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" - case 1'1 - assign \fus_oper_i_alu_trap0__msr \core_core_msr - end - end - end - sync init - end - process $group_71 - assign \fus_oper_i_alu_trap0__cia 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" - switch { \ivalid_i } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" - switch \core_core_insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:184" - attribute \nmigen.decoding "OP_ATTN/5" - case 7'0000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" - attribute \nmigen.decoding "OP_NOP/1" - case 7'0000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" - attribute \nmigen.decoding "" - case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" - switch { \fu_enable [3] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" - case 1'1 - assign \fus_oper_i_alu_trap0__cia \core_core_cia - end - end - end - sync init - end - process $group_72 - assign \fus_oper_i_alu_trap0__is_32bit 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" - switch { \ivalid_i } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" - switch \core_core_insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:184" - attribute \nmigen.decoding "OP_ATTN/5" - case 7'0000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" - attribute \nmigen.decoding "OP_NOP/1" - case 7'0000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" - attribute \nmigen.decoding "" - case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" - switch { \fu_enable [3] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" - case 1'1 - assign \fus_oper_i_alu_trap0__is_32bit \core_core_is_32bit - end - end - end - sync init - end - process $group_73 - assign \fus_oper_i_alu_trap0__traptype 7'0000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" - switch { \ivalid_i } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" - switch \core_core_insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:184" - attribute \nmigen.decoding "OP_ATTN/5" - case 7'0000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" - attribute \nmigen.decoding "OP_NOP/1" - case 7'0000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" - attribute \nmigen.decoding "" - case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" - switch { \fu_enable [3] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" - case 1'1 - assign \fus_oper_i_alu_trap0__traptype \core_core_traptype - end - end - end - sync init - end - process $group_74 - assign \fus_oper_i_alu_trap0__trapaddr 13'0000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" - switch { \ivalid_i } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" - switch \core_core_insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:184" - attribute \nmigen.decoding "OP_ATTN/5" - case 7'0000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" - attribute \nmigen.decoding "OP_NOP/1" - case 7'0000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" - attribute \nmigen.decoding "" - case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" - switch { \fu_enable [3] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" - case 1'1 - assign \fus_oper_i_alu_trap0__trapaddr \core_core_trapaddr - end - end - end - sync init - end - process $group_75 - assign \fus_cu_issue_i$10 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" - switch { \ivalid_i } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" - switch \core_core_insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:184" - attribute \nmigen.decoding "OP_ATTN/5" - case 7'0000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" - attribute \nmigen.decoding "OP_NOP/1" - case 7'0000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" - attribute \nmigen.decoding "" - case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" - switch { \fu_enable [3] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" - case 1'1 - assign \fus_cu_issue_i$10 \issue_i - end - end - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" - wire width 4 $233 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" - cell $not $234 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A { \core_fast2_ok \core_fast1_ok \core_reg2_ok \core_reg1_ok } - connect \Y $233 - end - process $group_76 - assign \fus_cu_rdmaskn_i$12 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" - switch { \ivalid_i } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" - switch \core_core_insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:184" - attribute \nmigen.decoding "OP_ATTN/5" - case 7'0000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" - attribute \nmigen.decoding "OP_NOP/1" - case 7'0000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" - attribute \nmigen.decoding "" - case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" - switch { \fu_enable [3] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" - case 1'1 - assign \fus_cu_rdmaskn_i$12 $233 - end - end - end - sync init - end - process $group_77 - assign \fus_oper_i_alu_logical0__insn_type 7'0000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" - switch { \ivalid_i } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" - switch \core_core_insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:184" - attribute \nmigen.decoding "OP_ATTN/5" - case 7'0000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" - attribute \nmigen.decoding "OP_NOP/1" - case 7'0000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" - attribute \nmigen.decoding "" - case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" - switch { \fu_enable [4] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" - case 1'1 - assign \fus_oper_i_alu_logical0__insn_type \dec_LOGICAL_LOGICAL_LOGICAL__insn_type - end - end - end - sync init - end - process $group_78 - assign \fus_oper_i_alu_logical0__fn_unit 11'00000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" - switch { \ivalid_i } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" - switch \core_core_insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:184" - attribute \nmigen.decoding "OP_ATTN/5" - case 7'0000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" - attribute \nmigen.decoding "OP_NOP/1" - case 7'0000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" - attribute \nmigen.decoding "" - case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" - switch { \fu_enable [4] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" - case 1'1 - assign \fus_oper_i_alu_logical0__fn_unit \dec_LOGICAL_LOGICAL_LOGICAL__fn_unit - end - end - end - sync init - end - process $group_79 - assign \fus_oper_i_alu_logical0__imm_data__data 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \fus_oper_i_alu_logical0__imm_data__ok 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" - switch { \ivalid_i } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" - switch \core_core_insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:184" - attribute \nmigen.decoding "OP_ATTN/5" - case 7'0000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" - attribute \nmigen.decoding "OP_NOP/1" - case 7'0000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" - attribute \nmigen.decoding "" - case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" - switch { \fu_enable [4] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" - case 1'1 - assign { \fus_oper_i_alu_logical0__imm_data__ok \fus_oper_i_alu_logical0__imm_data__data } { \dec_LOGICAL_LOGICAL_LOGICAL__imm_data__ok \dec_LOGICAL_LOGICAL_LOGICAL__imm_data__data } - end - end - end - sync init - end - process $group_81 - assign \fus_oper_i_alu_logical0__rc__rc 1'0 - assign \fus_oper_i_alu_logical0__rc__ok 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" - switch { \ivalid_i } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" - switch \core_core_insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:184" - attribute \nmigen.decoding "OP_ATTN/5" - case 7'0000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" - attribute \nmigen.decoding "OP_NOP/1" - case 7'0000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" - attribute \nmigen.decoding "" - case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" - switch { \fu_enable [4] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" - case 1'1 - assign { \fus_oper_i_alu_logical0__rc__ok \fus_oper_i_alu_logical0__rc__rc } { \dec_LOGICAL_LOGICAL_LOGICAL__rc__ok \dec_LOGICAL_LOGICAL_LOGICAL__rc__rc } - end - end - end - sync init - end - process $group_83 - assign \fus_oper_i_alu_logical0__oe__oe 1'0 - assign \fus_oper_i_alu_logical0__oe__ok 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" - switch { \ivalid_i } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" - switch \core_core_insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:184" - attribute \nmigen.decoding "OP_ATTN/5" - case 7'0000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" - attribute \nmigen.decoding "OP_NOP/1" - case 7'0000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" - attribute \nmigen.decoding "" - case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" - switch { \fu_enable [4] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" - case 1'1 - assign { \fus_oper_i_alu_logical0__oe__ok \fus_oper_i_alu_logical0__oe__oe } { \dec_LOGICAL_LOGICAL_LOGICAL__oe__ok \dec_LOGICAL_LOGICAL_LOGICAL__oe__oe } - end - end - end - sync init - end - process $group_85 - assign \fus_oper_i_alu_logical0__invert_in 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" - switch { \ivalid_i } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" - switch \core_core_insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:184" - attribute \nmigen.decoding "OP_ATTN/5" - case 7'0000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" - attribute \nmigen.decoding "OP_NOP/1" - case 7'0000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" - attribute \nmigen.decoding "" - case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" - switch { \fu_enable [4] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" - case 1'1 - assign \fus_oper_i_alu_logical0__invert_in \dec_LOGICAL_LOGICAL_LOGICAL__invert_in - end - end - end - sync init - end - process $group_86 - assign \fus_oper_i_alu_logical0__zero_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" - switch { \ivalid_i } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" - switch \core_core_insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:184" - attribute \nmigen.decoding "OP_ATTN/5" - case 7'0000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" - attribute \nmigen.decoding "OP_NOP/1" - case 7'0000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" - attribute \nmigen.decoding "" - case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" - switch { \fu_enable [4] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" - case 1'1 - assign \fus_oper_i_alu_logical0__zero_a \dec_LOGICAL_LOGICAL_LOGICAL__zero_a - end - end - end - sync init - end - process $group_87 - assign \fus_oper_i_alu_logical0__input_carry 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" - switch { \ivalid_i } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" - switch \core_core_insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:184" - attribute \nmigen.decoding "OP_ATTN/5" - case 7'0000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" - attribute \nmigen.decoding "OP_NOP/1" - case 7'0000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" - attribute \nmigen.decoding "" - case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" - switch { \fu_enable [4] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" - case 1'1 - assign \fus_oper_i_alu_logical0__input_carry \dec_LOGICAL_LOGICAL_LOGICAL__input_carry - end - end - end - sync init - end - process $group_88 - assign \fus_oper_i_alu_logical0__invert_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" - switch { \ivalid_i } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" - switch \core_core_insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:184" - attribute \nmigen.decoding "OP_ATTN/5" - case 7'0000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" - attribute \nmigen.decoding "OP_NOP/1" - case 7'0000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" - attribute \nmigen.decoding "" - case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" - switch { \fu_enable [4] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" - case 1'1 - assign \fus_oper_i_alu_logical0__invert_out \dec_LOGICAL_LOGICAL_LOGICAL__invert_out - end - end - end - sync init - end - process $group_89 - assign \fus_oper_i_alu_logical0__write_cr0 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" - switch { \ivalid_i } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" - switch \core_core_insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:184" - attribute \nmigen.decoding "OP_ATTN/5" - case 7'0000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" - attribute \nmigen.decoding "OP_NOP/1" - case 7'0000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" - attribute \nmigen.decoding "" - case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" - switch { \fu_enable [4] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" - case 1'1 - assign \fus_oper_i_alu_logical0__write_cr0 \dec_LOGICAL_LOGICAL_LOGICAL__write_cr0 - end - end - end - sync init - end - process $group_90 - assign \fus_oper_i_alu_logical0__output_carry 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" - switch { \ivalid_i } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" - switch \core_core_insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:184" - attribute \nmigen.decoding "OP_ATTN/5" - case 7'0000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" - attribute \nmigen.decoding "OP_NOP/1" - case 7'0000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" - attribute \nmigen.decoding "" - case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" - switch { \fu_enable [4] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" - case 1'1 - assign \fus_oper_i_alu_logical0__output_carry \dec_LOGICAL_LOGICAL_LOGICAL__output_carry - end - end - end - sync init - end - process $group_91 - assign \fus_oper_i_alu_logical0__is_32bit 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" - switch { \ivalid_i } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" - switch \core_core_insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:184" - attribute \nmigen.decoding "OP_ATTN/5" - case 7'0000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" - attribute \nmigen.decoding "OP_NOP/1" - case 7'0000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" - attribute \nmigen.decoding "" - case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" - switch { \fu_enable [4] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" - case 1'1 - assign \fus_oper_i_alu_logical0__is_32bit \dec_LOGICAL_LOGICAL_LOGICAL__is_32bit - end - end - end - sync init - end - process $group_92 - assign \fus_oper_i_alu_logical0__is_signed 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" - switch { \ivalid_i } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" - switch \core_core_insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:184" - attribute \nmigen.decoding "OP_ATTN/5" - case 7'0000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" - attribute \nmigen.decoding "OP_NOP/1" - case 7'0000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" - attribute \nmigen.decoding "" - case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" - switch { \fu_enable [4] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" - case 1'1 - assign \fus_oper_i_alu_logical0__is_signed \dec_LOGICAL_LOGICAL_LOGICAL__is_signed - end - end - end - sync init - end - process $group_93 - assign \fus_oper_i_alu_logical0__data_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" - switch { \ivalid_i } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" - switch \core_core_insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:184" - attribute \nmigen.decoding "OP_ATTN/5" - case 7'0000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" - attribute \nmigen.decoding "OP_NOP/1" - case 7'0000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" - attribute \nmigen.decoding "" - case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" - switch { \fu_enable [4] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" - case 1'1 - assign \fus_oper_i_alu_logical0__data_len \dec_LOGICAL_LOGICAL_LOGICAL__data_len - end - end - end - sync init - end - process $group_94 - assign \fus_oper_i_alu_logical0__insn 32'00000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" - switch { \ivalid_i } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" - switch \core_core_insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:184" - attribute \nmigen.decoding "OP_ATTN/5" - case 7'0000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" - attribute \nmigen.decoding "OP_NOP/1" - case 7'0000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" - attribute \nmigen.decoding "" - case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" - switch { \fu_enable [4] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" - case 1'1 - assign \fus_oper_i_alu_logical0__insn \dec_LOGICAL_LOGICAL_LOGICAL__insn - end - end - end - sync init - end - process $group_95 - assign \fus_cu_issue_i$13 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" - switch { \ivalid_i } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" - switch \core_core_insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:184" - attribute \nmigen.decoding "OP_ATTN/5" - case 7'0000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" - attribute \nmigen.decoding "OP_NOP/1" - case 7'0000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" - attribute \nmigen.decoding "" - case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" - switch { \fu_enable [4] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" - case 1'1 - assign \fus_cu_issue_i$13 \issue_i - end - end - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" - wire width 3 $235 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" - wire width 1 $236 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" - cell $and $237 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \core_core_oe - connect \B \core_core_oe_ok - connect \Y $236 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" - wire width 3 $238 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" - cell $and $239 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 3 - connect \A \core_xer_in - connect \B 1'1 - connect \Y $238 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" - wire width 1 $240 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" - cell $eq $241 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $238 - connect \B 1'1 - connect \Y $240 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" - wire width 1 $242 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" - cell $or $243 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $236 - connect \B $240 - connect \Y $242 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81" - wire width 1 $244 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81" - cell $and $245 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \core_core_rc - connect \B \core_core_rc_ok - connect \Y $244 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81" - wire width 1 $246 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81" - cell $or $247 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $242 - connect \B $244 - connect \Y $246 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" - cell $not $248 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A { $246 \core_reg2_ok \core_reg1_ok } - connect \Y $235 - end - process $group_96 - assign \fus_cu_rdmaskn_i$15 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" - switch { \ivalid_i } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" - switch \core_core_insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:184" - attribute \nmigen.decoding "OP_ATTN/5" - case 7'0000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" - attribute \nmigen.decoding "OP_NOP/1" - case 7'0000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" - attribute \nmigen.decoding "" - case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" - switch { \fu_enable [4] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" - case 1'1 - assign \fus_cu_rdmaskn_i$15 $235 - end - end - end - sync init - end - process $group_97 - assign \fus_oper_i_alu_spr0__insn_type 7'0000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" - switch { \ivalid_i } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" - switch \core_core_insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:184" - attribute \nmigen.decoding "OP_ATTN/5" - case 7'0000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" - attribute \nmigen.decoding "OP_NOP/1" - case 7'0000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" - attribute \nmigen.decoding "" - case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" - switch { \fu_enable [5] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" - case 1'1 - assign \fus_oper_i_alu_spr0__insn_type \dec_SPR_SPR_SPR__insn_type - end - end - end - sync init - end - process $group_98 - assign \fus_oper_i_alu_spr0__fn_unit 11'00000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" - switch { \ivalid_i } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" - switch \core_core_insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:184" - attribute \nmigen.decoding "OP_ATTN/5" - case 7'0000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" - attribute \nmigen.decoding "OP_NOP/1" - case 7'0000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" - attribute \nmigen.decoding "" - case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" - switch { \fu_enable [5] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" - case 1'1 - assign \fus_oper_i_alu_spr0__fn_unit \dec_SPR_SPR_SPR__fn_unit - end - end - end - sync init - end - process $group_99 - assign \fus_oper_i_alu_spr0__insn 32'00000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" - switch { \ivalid_i } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" - switch \core_core_insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:184" - attribute \nmigen.decoding "OP_ATTN/5" - case 7'0000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" - attribute \nmigen.decoding "OP_NOP/1" - case 7'0000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" - attribute \nmigen.decoding "" - case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" - switch { \fu_enable [5] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" - case 1'1 - assign \fus_oper_i_alu_spr0__insn \dec_SPR_SPR_SPR__insn - end - end - end - sync init - end - process $group_100 - assign \fus_oper_i_alu_spr0__is_32bit 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" - switch { \ivalid_i } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" - switch \core_core_insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:184" - attribute \nmigen.decoding "OP_ATTN/5" - case 7'0000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" - attribute \nmigen.decoding "OP_NOP/1" - case 7'0000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" - attribute \nmigen.decoding "" - case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" - switch { \fu_enable [5] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" - case 1'1 - assign \fus_oper_i_alu_spr0__is_32bit \dec_SPR_SPR_SPR__is_32bit - end - end - end - sync init - end - process $group_101 - assign \fus_cu_issue_i$16 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" - switch { \ivalid_i } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" - switch \core_core_insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:184" - attribute \nmigen.decoding "OP_ATTN/5" - case 7'0000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" - attribute \nmigen.decoding "OP_NOP/1" - case 7'0000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" - attribute \nmigen.decoding "" - case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" - switch { \fu_enable [5] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" - case 1'1 - assign \fus_cu_issue_i$16 \issue_i - end - end - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" - wire width 6 $249 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" - wire width 1 $250 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" - cell $and $251 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \core_core_oe - connect \B \core_core_oe_ok - connect \Y $250 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" - wire width 3 $252 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" - cell $and $253 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 3 - connect \A \core_xer_in - connect \B 1'1 - connect \Y $252 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" - wire width 1 $254 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" - cell $eq $255 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $252 - connect \B 1'1 - connect \Y $254 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" - wire width 1 $256 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" - cell $or $257 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $250 - connect \B $254 - connect \Y $256 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81" - wire width 1 $258 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81" - cell $and $259 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \core_core_rc - connect \B \core_core_rc_ok - connect \Y $258 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81" - wire width 1 $260 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81" - cell $or $261 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $256 - connect \B $258 - connect \Y $260 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:83" - wire width 1 $262 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:83" - cell $and $263 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \core_core_oe - connect \B \core_core_oe_ok - connect \Y $262 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:84" - wire width 3 $264 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:84" - cell $and $265 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 3 - connect \A \core_xer_in - connect \B 2'10 - connect \Y $264 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:84" - wire width 1 $266 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:84" - cell $eq $267 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A $264 - connect \B 2'10 - connect \Y $266 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:84" - wire width 1 $268 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:84" - cell $or $269 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $262 - connect \B $266 - connect \Y $268 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:86" - wire width 1 $270 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:86" - cell $eq $271 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \core_core_input_carry - connect \B 2'10 - connect \Y $270 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:87" - wire width 3 $272 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:87" - cell $and $273 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A \core_xer_in - connect \B 3'100 - connect \Y $272 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:87" - wire width 1 $274 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:87" - cell $eq $275 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A $272 - connect \B 3'100 - connect \Y $274 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:87" - wire width 1 $276 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:87" - cell $or $277 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $270 - connect \B $274 - connect \Y $276 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" - cell $not $278 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \Y_WIDTH 6 - connect \A { $276 $268 $260 \core_fast1_ok \core_spr1_ok \core_reg1_ok } - connect \Y $249 - end - process $group_102 - assign \fus_cu_rdmaskn_i$18 6'000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" - switch { \ivalid_i } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" - switch \core_core_insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:184" - attribute \nmigen.decoding "OP_ATTN/5" - case 7'0000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" - attribute \nmigen.decoding "OP_NOP/1" - case 7'0000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" - attribute \nmigen.decoding "" - case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" - switch { \fu_enable [5] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" - case 1'1 - assign \fus_cu_rdmaskn_i$18 $249 - end - end - end - sync init - end - process $group_103 - assign \fus_oper_i_alu_div0__insn_type 7'0000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" - switch { \ivalid_i } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" - switch \core_core_insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:184" - attribute \nmigen.decoding "OP_ATTN/5" - case 7'0000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" - attribute \nmigen.decoding "OP_NOP/1" - case 7'0000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" - attribute \nmigen.decoding "" - case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" - switch { \fu_enable [6] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" - case 1'1 - assign \fus_oper_i_alu_div0__insn_type \dec_DIV_DIV_DIV__insn_type - end - end - end - sync init - end - process $group_104 - assign \fus_oper_i_alu_div0__fn_unit 11'00000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" - switch { \ivalid_i } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" - switch \core_core_insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:184" - attribute \nmigen.decoding "OP_ATTN/5" - case 7'0000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" - attribute \nmigen.decoding "OP_NOP/1" - case 7'0000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" - attribute \nmigen.decoding "" - case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" - switch { \fu_enable [6] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" - case 1'1 - assign \fus_oper_i_alu_div0__fn_unit \dec_DIV_DIV_DIV__fn_unit - end - end - end - sync init - end - process $group_105 - assign \fus_oper_i_alu_div0__imm_data__data 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \fus_oper_i_alu_div0__imm_data__ok 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" - switch { \ivalid_i } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" - switch \core_core_insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:184" - attribute \nmigen.decoding "OP_ATTN/5" - case 7'0000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" - attribute \nmigen.decoding "OP_NOP/1" - case 7'0000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" - attribute \nmigen.decoding "" - case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" - switch { \fu_enable [6] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" - case 1'1 - assign { \fus_oper_i_alu_div0__imm_data__ok \fus_oper_i_alu_div0__imm_data__data } { \dec_DIV_DIV_DIV__imm_data__ok \dec_DIV_DIV_DIV__imm_data__data } - end - end - end - sync init - end - process $group_107 - assign \fus_oper_i_alu_div0__rc__rc 1'0 - assign \fus_oper_i_alu_div0__rc__ok 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" - switch { \ivalid_i } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" - switch \core_core_insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:184" - attribute \nmigen.decoding "OP_ATTN/5" - case 7'0000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" - attribute \nmigen.decoding "OP_NOP/1" - case 7'0000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" - attribute \nmigen.decoding "" - case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" - switch { \fu_enable [6] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" - case 1'1 - assign { \fus_oper_i_alu_div0__rc__ok \fus_oper_i_alu_div0__rc__rc } { \dec_DIV_DIV_DIV__rc__ok \dec_DIV_DIV_DIV__rc__rc } - end - end - end - sync init - end - process $group_109 - assign \fus_oper_i_alu_div0__oe__oe 1'0 - assign \fus_oper_i_alu_div0__oe__ok 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" - switch { \ivalid_i } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" - switch \core_core_insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:184" - attribute \nmigen.decoding "OP_ATTN/5" - case 7'0000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" - attribute \nmigen.decoding "OP_NOP/1" - case 7'0000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" - attribute \nmigen.decoding "" - case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" - switch { \fu_enable [6] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" - case 1'1 - assign { \fus_oper_i_alu_div0__oe__ok \fus_oper_i_alu_div0__oe__oe } { \dec_DIV_DIV_DIV__oe__ok \dec_DIV_DIV_DIV__oe__oe } - end - end - end - sync init - end - process $group_111 - assign \fus_oper_i_alu_div0__invert_in 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" - switch { \ivalid_i } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" - switch \core_core_insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:184" - attribute \nmigen.decoding "OP_ATTN/5" - case 7'0000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" - attribute \nmigen.decoding "OP_NOP/1" - case 7'0000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" - attribute \nmigen.decoding "" - case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" - switch { \fu_enable [6] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" - case 1'1 - assign \fus_oper_i_alu_div0__invert_in \dec_DIV_DIV_DIV__invert_in - end - end - end - sync init - end - process $group_112 - assign \fus_oper_i_alu_div0__zero_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" - switch { \ivalid_i } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" - switch \core_core_insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:184" - attribute \nmigen.decoding "OP_ATTN/5" - case 7'0000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" - attribute \nmigen.decoding "OP_NOP/1" - case 7'0000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" - attribute \nmigen.decoding "" - case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" - switch { \fu_enable [6] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" - case 1'1 - assign \fus_oper_i_alu_div0__zero_a \dec_DIV_DIV_DIV__zero_a - end - end - end - sync init - end - process $group_113 - assign \fus_oper_i_alu_div0__input_carry 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" - switch { \ivalid_i } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" - switch \core_core_insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:184" - attribute \nmigen.decoding "OP_ATTN/5" - case 7'0000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" - attribute \nmigen.decoding "OP_NOP/1" - case 7'0000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" - attribute \nmigen.decoding "" - case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" - switch { \fu_enable [6] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" - case 1'1 - assign \fus_oper_i_alu_div0__input_carry \dec_DIV_DIV_DIV__input_carry - end - end - end - sync init - end - process $group_114 - assign \fus_oper_i_alu_div0__invert_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" - switch { \ivalid_i } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" - switch \core_core_insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:184" - attribute \nmigen.decoding "OP_ATTN/5" - case 7'0000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" - attribute \nmigen.decoding "OP_NOP/1" - case 7'0000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" - attribute \nmigen.decoding "" - case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" - switch { \fu_enable [6] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" - case 1'1 - assign \fus_oper_i_alu_div0__invert_out \dec_DIV_DIV_DIV__invert_out - end - end - end - sync init - end - process $group_115 - assign \fus_oper_i_alu_div0__write_cr0 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" - switch { \ivalid_i } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" - switch \core_core_insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:184" - attribute \nmigen.decoding "OP_ATTN/5" - case 7'0000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" - attribute \nmigen.decoding "OP_NOP/1" - case 7'0000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" - attribute \nmigen.decoding "" - case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" - switch { \fu_enable [6] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" - case 1'1 - assign \fus_oper_i_alu_div0__write_cr0 \dec_DIV_DIV_DIV__write_cr0 - end - end - end - sync init - end - process $group_116 - assign \fus_oper_i_alu_div0__output_carry 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" - switch { \ivalid_i } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" - switch \core_core_insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:184" - attribute \nmigen.decoding "OP_ATTN/5" - case 7'0000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" - attribute \nmigen.decoding "OP_NOP/1" - case 7'0000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" - attribute \nmigen.decoding "" - case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" - switch { \fu_enable [6] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" - case 1'1 - assign \fus_oper_i_alu_div0__output_carry \dec_DIV_DIV_DIV__output_carry - end - end - end - sync init - end - process $group_117 - assign \fus_oper_i_alu_div0__is_32bit 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" - switch { \ivalid_i } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" - switch \core_core_insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:184" - attribute \nmigen.decoding "OP_ATTN/5" - case 7'0000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" - attribute \nmigen.decoding "OP_NOP/1" - case 7'0000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" - attribute \nmigen.decoding "" - case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" - switch { \fu_enable [6] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" - case 1'1 - assign \fus_oper_i_alu_div0__is_32bit \dec_DIV_DIV_DIV__is_32bit - end - end - end - sync init - end - process $group_118 - assign \fus_oper_i_alu_div0__is_signed 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" - switch { \ivalid_i } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" - switch \core_core_insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:184" - attribute \nmigen.decoding "OP_ATTN/5" - case 7'0000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" - attribute \nmigen.decoding "OP_NOP/1" - case 7'0000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" - attribute \nmigen.decoding "" - case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" - switch { \fu_enable [6] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" - case 1'1 - assign \fus_oper_i_alu_div0__is_signed \dec_DIV_DIV_DIV__is_signed - end - end - end - sync init - end - process $group_119 - assign \fus_oper_i_alu_div0__data_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" - switch { \ivalid_i } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" - switch \core_core_insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:184" - attribute \nmigen.decoding "OP_ATTN/5" - case 7'0000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" - attribute \nmigen.decoding "OP_NOP/1" - case 7'0000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" - attribute \nmigen.decoding "" - case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" - switch { \fu_enable [6] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" - case 1'1 - assign \fus_oper_i_alu_div0__data_len \dec_DIV_DIV_DIV__data_len - end - end - end - sync init - end - process $group_120 - assign \fus_oper_i_alu_div0__insn 32'00000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" - switch { \ivalid_i } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" - switch \core_core_insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:184" - attribute \nmigen.decoding "OP_ATTN/5" - case 7'0000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" - attribute \nmigen.decoding "OP_NOP/1" - case 7'0000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" - attribute \nmigen.decoding "" - case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" - switch { \fu_enable [6] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" - case 1'1 - assign \fus_oper_i_alu_div0__insn \dec_DIV_DIV_DIV__insn - end - end - end - sync init - end - process $group_121 - assign \fus_cu_issue_i$19 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" - switch { \ivalid_i } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" - switch \core_core_insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:184" - attribute \nmigen.decoding "OP_ATTN/5" - case 7'0000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" - attribute \nmigen.decoding "OP_NOP/1" - case 7'0000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" - attribute \nmigen.decoding "" - case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" - switch { \fu_enable [6] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" - case 1'1 - assign \fus_cu_issue_i$19 \issue_i - end - end - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" - wire width 3 $279 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" - wire width 1 $280 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" - cell $and $281 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \core_core_oe - connect \B \core_core_oe_ok - connect \Y $280 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" - wire width 3 $282 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" - cell $and $283 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 3 - connect \A \core_xer_in - connect \B 1'1 - connect \Y $282 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" - wire width 1 $284 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" - cell $eq $285 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $282 - connect \B 1'1 - connect \Y $284 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" - wire width 1 $286 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" - cell $or $287 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $280 - connect \B $284 - connect \Y $286 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81" - wire width 1 $288 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81" - cell $and $289 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \core_core_rc - connect \B \core_core_rc_ok - connect \Y $288 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81" - wire width 1 $290 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81" - cell $or $291 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $286 - connect \B $288 - connect \Y $290 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" - cell $not $292 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A { $290 \core_reg2_ok \core_reg1_ok } - connect \Y $279 - end - process $group_122 - assign \fus_cu_rdmaskn_i$21 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" - switch { \ivalid_i } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" - switch \core_core_insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:184" - attribute \nmigen.decoding "OP_ATTN/5" - case 7'0000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" - attribute \nmigen.decoding "OP_NOP/1" - case 7'0000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" - attribute \nmigen.decoding "" - case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" - switch { \fu_enable [6] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" - case 1'1 - assign \fus_cu_rdmaskn_i$21 $279 - end - end - end - sync init - end - process $group_123 - assign \fus_oper_i_alu_mul0__insn_type 7'0000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" - switch { \ivalid_i } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" - switch \core_core_insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:184" - attribute \nmigen.decoding "OP_ATTN/5" - case 7'0000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" - attribute \nmigen.decoding "OP_NOP/1" - case 7'0000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" - attribute \nmigen.decoding "" - case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" - switch { \fu_enable [7] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" - case 1'1 - assign \fus_oper_i_alu_mul0__insn_type \dec_MUL_MUL_MUL__insn_type - end - end - end - sync init - end - process $group_124 - assign \fus_oper_i_alu_mul0__fn_unit 11'00000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" - switch { \ivalid_i } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" - switch \core_core_insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:184" - attribute \nmigen.decoding "OP_ATTN/5" - case 7'0000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" - attribute \nmigen.decoding "OP_NOP/1" - case 7'0000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" - attribute \nmigen.decoding "" - case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" - switch { \fu_enable [7] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" - case 1'1 - assign \fus_oper_i_alu_mul0__fn_unit \dec_MUL_MUL_MUL__fn_unit - end - end - end - sync init - end - process $group_125 - assign \fus_oper_i_alu_mul0__imm_data__data 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \fus_oper_i_alu_mul0__imm_data__ok 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" - switch { \ivalid_i } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" - switch \core_core_insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:184" - attribute \nmigen.decoding "OP_ATTN/5" - case 7'0000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" - attribute \nmigen.decoding "OP_NOP/1" - case 7'0000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" - attribute \nmigen.decoding "" - case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" - switch { \fu_enable [7] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" - case 1'1 - assign { \fus_oper_i_alu_mul0__imm_data__ok \fus_oper_i_alu_mul0__imm_data__data } { \dec_MUL_MUL_MUL__imm_data__ok \dec_MUL_MUL_MUL__imm_data__data } - end - end - end - sync init - end - process $group_127 - assign \fus_oper_i_alu_mul0__rc__rc 1'0 - assign \fus_oper_i_alu_mul0__rc__ok 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" - switch { \ivalid_i } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" - switch \core_core_insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:184" - attribute \nmigen.decoding "OP_ATTN/5" - case 7'0000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" - attribute \nmigen.decoding "OP_NOP/1" - case 7'0000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" - attribute \nmigen.decoding "" - case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" - switch { \fu_enable [7] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" - case 1'1 - assign { \fus_oper_i_alu_mul0__rc__ok \fus_oper_i_alu_mul0__rc__rc } { \dec_MUL_MUL_MUL__rc__ok \dec_MUL_MUL_MUL__rc__rc } - end - end - end - sync init - end - process $group_129 - assign \fus_oper_i_alu_mul0__oe__oe 1'0 - assign \fus_oper_i_alu_mul0__oe__ok 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" - switch { \ivalid_i } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" - switch \core_core_insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:184" - attribute \nmigen.decoding "OP_ATTN/5" - case 7'0000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" - attribute \nmigen.decoding "OP_NOP/1" - case 7'0000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" - attribute \nmigen.decoding "" - case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" - switch { \fu_enable [7] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" - case 1'1 - assign { \fus_oper_i_alu_mul0__oe__ok \fus_oper_i_alu_mul0__oe__oe } { \dec_MUL_MUL_MUL__oe__ok \dec_MUL_MUL_MUL__oe__oe } - end - end - end - sync init - end - process $group_131 - assign \fus_oper_i_alu_mul0__write_cr0 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" - switch { \ivalid_i } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" - switch \core_core_insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:184" - attribute \nmigen.decoding "OP_ATTN/5" - case 7'0000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" - attribute \nmigen.decoding "OP_NOP/1" - case 7'0000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" - attribute \nmigen.decoding "" - case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" - switch { \fu_enable [7] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" - case 1'1 - assign \fus_oper_i_alu_mul0__write_cr0 \dec_MUL_MUL_MUL__write_cr0 - end - end - end - sync init - end - process $group_132 - assign \fus_oper_i_alu_mul0__is_32bit 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" - switch { \ivalid_i } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" - switch \core_core_insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:184" - attribute \nmigen.decoding "OP_ATTN/5" - case 7'0000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" - attribute \nmigen.decoding "OP_NOP/1" - case 7'0000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" - attribute \nmigen.decoding "" - case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" - switch { \fu_enable [7] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" - case 1'1 - assign \fus_oper_i_alu_mul0__is_32bit \dec_MUL_MUL_MUL__is_32bit - end - end - end - sync init - end - process $group_133 - assign \fus_oper_i_alu_mul0__is_signed 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" - switch { \ivalid_i } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" - switch \core_core_insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:184" - attribute \nmigen.decoding "OP_ATTN/5" - case 7'0000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" - attribute \nmigen.decoding "OP_NOP/1" - case 7'0000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" - attribute \nmigen.decoding "" - case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" - switch { \fu_enable [7] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" - case 1'1 - assign \fus_oper_i_alu_mul0__is_signed \dec_MUL_MUL_MUL__is_signed - end - end - end - sync init - end - process $group_134 - assign \fus_oper_i_alu_mul0__insn 32'00000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" - switch { \ivalid_i } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" - switch \core_core_insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:184" - attribute \nmigen.decoding "OP_ATTN/5" - case 7'0000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" - attribute \nmigen.decoding "OP_NOP/1" - case 7'0000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" - attribute \nmigen.decoding "" - case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" - switch { \fu_enable [7] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" - case 1'1 - assign \fus_oper_i_alu_mul0__insn \dec_MUL_MUL_MUL__insn - end - end - end - sync init - end - process $group_135 - assign \fus_cu_issue_i$22 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" - switch { \ivalid_i } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" - switch \core_core_insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:184" - attribute \nmigen.decoding "OP_ATTN/5" - case 7'0000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" - attribute \nmigen.decoding "OP_NOP/1" - case 7'0000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" - attribute \nmigen.decoding "" - case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" - switch { \fu_enable [7] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" - case 1'1 - assign \fus_cu_issue_i$22 \issue_i - end - end - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" - wire width 3 $293 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" - wire width 1 $294 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" - cell $and $295 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \core_core_oe - connect \B \core_core_oe_ok - connect \Y $294 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" - wire width 3 $296 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" - cell $and $297 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 3 - connect \A \core_xer_in - connect \B 1'1 - connect \Y $296 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" - wire width 1 $298 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" - cell $eq $299 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $296 - connect \B 1'1 - connect \Y $298 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" - wire width 1 $300 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" - cell $or $301 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $294 - connect \B $298 - connect \Y $300 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81" - wire width 1 $302 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81" - cell $and $303 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \core_core_rc - connect \B \core_core_rc_ok - connect \Y $302 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81" - wire width 1 $304 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81" - cell $or $305 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $300 - connect \B $302 - connect \Y $304 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" - cell $not $306 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A { $304 \core_reg2_ok \core_reg1_ok } - connect \Y $293 - end - process $group_136 - assign \fus_cu_rdmaskn_i$24 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" - switch { \ivalid_i } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" - switch \core_core_insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:184" - attribute \nmigen.decoding "OP_ATTN/5" - case 7'0000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" - attribute \nmigen.decoding "OP_NOP/1" - case 7'0000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" - attribute \nmigen.decoding "" - case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" - switch { \fu_enable [7] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" - case 1'1 - assign \fus_cu_rdmaskn_i$24 $293 - end - end - end - sync init - end - process $group_137 - assign \fus_oper_i_alu_shift_rot0__insn_type 7'0000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" - switch { \ivalid_i } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" - switch \core_core_insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:184" - attribute \nmigen.decoding "OP_ATTN/5" - case 7'0000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" - attribute \nmigen.decoding "OP_NOP/1" - case 7'0000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" - attribute \nmigen.decoding "" - case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" - switch { \fu_enable [8] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" - case 1'1 - assign \fus_oper_i_alu_shift_rot0__insn_type \dec_SHIFT_ROT_SHIFT_ROT_SHIFT_ROT__insn_type - end - end - end - sync init - end - process $group_138 - assign \fus_oper_i_alu_shift_rot0__fn_unit 11'00000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" - switch { \ivalid_i } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" - switch \core_core_insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:184" - attribute \nmigen.decoding "OP_ATTN/5" - case 7'0000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" - attribute \nmigen.decoding "OP_NOP/1" - case 7'0000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" - attribute \nmigen.decoding "" - case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" - switch { \fu_enable [8] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" - case 1'1 - assign \fus_oper_i_alu_shift_rot0__fn_unit \dec_SHIFT_ROT_SHIFT_ROT_SHIFT_ROT__fn_unit - end - end - end - sync init - end - process $group_139 - assign \fus_oper_i_alu_shift_rot0__imm_data__data 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \fus_oper_i_alu_shift_rot0__imm_data__ok 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" - switch { \ivalid_i } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" - switch \core_core_insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:184" - attribute \nmigen.decoding "OP_ATTN/5" - case 7'0000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" - attribute \nmigen.decoding "OP_NOP/1" - case 7'0000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" - attribute \nmigen.decoding "" - case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" - switch { \fu_enable [8] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" - case 1'1 - assign { \fus_oper_i_alu_shift_rot0__imm_data__ok \fus_oper_i_alu_shift_rot0__imm_data__data } { \dec_SHIFT_ROT_SHIFT_ROT_SHIFT_ROT__imm_data__ok \dec_SHIFT_ROT_SHIFT_ROT_SHIFT_ROT__imm_data__data } - end - end - end - sync init - end - process $group_141 - assign \fus_oper_i_alu_shift_rot0__rc__rc 1'0 - assign \fus_oper_i_alu_shift_rot0__rc__ok 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" - switch { \ivalid_i } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" - switch \core_core_insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:184" - attribute \nmigen.decoding "OP_ATTN/5" - case 7'0000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" - attribute \nmigen.decoding "OP_NOP/1" - case 7'0000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" - attribute \nmigen.decoding "" - case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" - switch { \fu_enable [8] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" - case 1'1 - assign { \fus_oper_i_alu_shift_rot0__rc__ok \fus_oper_i_alu_shift_rot0__rc__rc } { \dec_SHIFT_ROT_SHIFT_ROT_SHIFT_ROT__rc__ok \dec_SHIFT_ROT_SHIFT_ROT_SHIFT_ROT__rc__rc } - end - end - end - sync init - end - process $group_143 - assign \fus_oper_i_alu_shift_rot0__oe__oe 1'0 - assign \fus_oper_i_alu_shift_rot0__oe__ok 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" - switch { \ivalid_i } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" - switch \core_core_insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:184" - attribute \nmigen.decoding "OP_ATTN/5" - case 7'0000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" - attribute \nmigen.decoding "OP_NOP/1" - case 7'0000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" - attribute \nmigen.decoding "" - case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" - switch { \fu_enable [8] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" - case 1'1 - assign { \fus_oper_i_alu_shift_rot0__oe__ok \fus_oper_i_alu_shift_rot0__oe__oe } { \dec_SHIFT_ROT_SHIFT_ROT_SHIFT_ROT__oe__ok \dec_SHIFT_ROT_SHIFT_ROT_SHIFT_ROT__oe__oe } - end - end - end - sync init - end - process $group_145 - assign \fus_oper_i_alu_shift_rot0__write_cr0 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" - switch { \ivalid_i } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" - switch \core_core_insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:184" - attribute \nmigen.decoding "OP_ATTN/5" - case 7'0000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" - attribute \nmigen.decoding "OP_NOP/1" - case 7'0000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" - attribute \nmigen.decoding "" - case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" - switch { \fu_enable [8] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" - case 1'1 - assign \fus_oper_i_alu_shift_rot0__write_cr0 \dec_SHIFT_ROT_SHIFT_ROT_SHIFT_ROT__write_cr0 - end - end - end - sync init - end - process $group_146 - assign \fus_oper_i_alu_shift_rot0__input_carry 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" - switch { \ivalid_i } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" - switch \core_core_insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:184" - attribute \nmigen.decoding "OP_ATTN/5" - case 7'0000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" - attribute \nmigen.decoding "OP_NOP/1" - case 7'0000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" - attribute \nmigen.decoding "" - case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" - switch { \fu_enable [8] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" - case 1'1 - assign \fus_oper_i_alu_shift_rot0__input_carry \dec_SHIFT_ROT_SHIFT_ROT_SHIFT_ROT__input_carry - end - end - end - sync init - end - process $group_147 - assign \fus_oper_i_alu_shift_rot0__output_carry 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" - switch { \ivalid_i } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" - switch \core_core_insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:184" - attribute \nmigen.decoding "OP_ATTN/5" - case 7'0000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" - attribute \nmigen.decoding "OP_NOP/1" - case 7'0000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" - attribute \nmigen.decoding "" - case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" - switch { \fu_enable [8] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" - case 1'1 - assign \fus_oper_i_alu_shift_rot0__output_carry \dec_SHIFT_ROT_SHIFT_ROT_SHIFT_ROT__output_carry - end - end - end - sync init - end - process $group_148 - assign \fus_oper_i_alu_shift_rot0__input_cr 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" - switch { \ivalid_i } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" - switch \core_core_insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:184" - attribute \nmigen.decoding "OP_ATTN/5" - case 7'0000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" - attribute \nmigen.decoding "OP_NOP/1" - case 7'0000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" - attribute \nmigen.decoding "" - case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" - switch { \fu_enable [8] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" - case 1'1 - assign \fus_oper_i_alu_shift_rot0__input_cr \dec_SHIFT_ROT_SHIFT_ROT_SHIFT_ROT__input_cr - end - end - end - sync init - end - process $group_149 - assign \fus_oper_i_alu_shift_rot0__output_cr 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" - switch { \ivalid_i } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" - switch \core_core_insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:184" - attribute \nmigen.decoding "OP_ATTN/5" - case 7'0000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" - attribute \nmigen.decoding "OP_NOP/1" - case 7'0000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" - attribute \nmigen.decoding "" - case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" - switch { \fu_enable [8] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" - case 1'1 - assign \fus_oper_i_alu_shift_rot0__output_cr \dec_SHIFT_ROT_SHIFT_ROT_SHIFT_ROT__output_cr - end - end - end - sync init - end - process $group_150 - assign \fus_oper_i_alu_shift_rot0__is_32bit 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" - switch { \ivalid_i } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" - switch \core_core_insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:184" - attribute \nmigen.decoding "OP_ATTN/5" - case 7'0000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" - attribute \nmigen.decoding "OP_NOP/1" - case 7'0000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" - attribute \nmigen.decoding "" - case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" - switch { \fu_enable [8] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" - case 1'1 - assign \fus_oper_i_alu_shift_rot0__is_32bit \dec_SHIFT_ROT_SHIFT_ROT_SHIFT_ROT__is_32bit - end - end - end - sync init - end - process $group_151 - assign \fus_oper_i_alu_shift_rot0__is_signed 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" - switch { \ivalid_i } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" - switch \core_core_insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:184" - attribute \nmigen.decoding "OP_ATTN/5" - case 7'0000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" - attribute \nmigen.decoding "OP_NOP/1" - case 7'0000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" - attribute \nmigen.decoding "" - case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" - switch { \fu_enable [8] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" - case 1'1 - assign \fus_oper_i_alu_shift_rot0__is_signed \dec_SHIFT_ROT_SHIFT_ROT_SHIFT_ROT__is_signed - end - end - end - sync init - end - process $group_152 - assign \fus_oper_i_alu_shift_rot0__insn 32'00000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" - switch { \ivalid_i } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" - switch \core_core_insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:184" - attribute \nmigen.decoding "OP_ATTN/5" - case 7'0000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" - attribute \nmigen.decoding "OP_NOP/1" - case 7'0000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" - attribute \nmigen.decoding "" - case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" - switch { \fu_enable [8] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" - case 1'1 - assign \fus_oper_i_alu_shift_rot0__insn \dec_SHIFT_ROT_SHIFT_ROT_SHIFT_ROT__insn - end - end - end - sync init - end - process $group_153 - assign \fus_cu_issue_i$25 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" - switch { \ivalid_i } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" - switch \core_core_insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:184" - attribute \nmigen.decoding "OP_ATTN/5" - case 7'0000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" - attribute \nmigen.decoding "OP_NOP/1" - case 7'0000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" - attribute \nmigen.decoding "" - case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" - switch { \fu_enable [8] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" - case 1'1 - assign \fus_cu_issue_i$25 \issue_i - end - end - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" - wire width 5 $307 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" - wire width 1 $308 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" - cell $and $309 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \core_core_oe - connect \B \core_core_oe_ok - connect \Y $308 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" - wire width 3 $310 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" - cell $and $311 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 3 - connect \A \core_xer_in - connect \B 1'1 - connect \Y $310 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" - wire width 1 $312 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" - cell $eq $313 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $310 - connect \B 1'1 - connect \Y $312 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" - wire width 1 $314 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" - cell $or $315 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $308 - connect \B $312 - connect \Y $314 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81" - wire width 1 $316 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81" - cell $and $317 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \core_core_rc - connect \B \core_core_rc_ok - connect \Y $316 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81" - wire width 1 $318 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81" - cell $or $319 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $314 - connect \B $316 - connect \Y $318 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:86" - wire width 1 $320 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:86" - cell $eq $321 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \core_core_input_carry - connect \B 2'10 - connect \Y $320 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:87" - wire width 3 $322 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:87" - cell $and $323 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A \core_xer_in - connect \B 3'100 - connect \Y $322 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:87" - wire width 1 $324 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:87" - cell $eq $325 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A $322 - connect \B 3'100 - connect \Y $324 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:87" - wire width 1 $326 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:87" - cell $or $327 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $320 - connect \B $324 - connect \Y $326 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" - cell $not $328 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \Y_WIDTH 5 - connect \A { $326 $318 \core_reg3_ok \core_reg2_ok \core_reg1_ok } - connect \Y $307 - end - process $group_154 - assign \fus_cu_rdmaskn_i$27 5'00000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" - switch { \ivalid_i } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" - switch \core_core_insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:184" - attribute \nmigen.decoding "OP_ATTN/5" - case 7'0000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" - attribute \nmigen.decoding "OP_NOP/1" - case 7'0000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" - attribute \nmigen.decoding "" - case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" - switch { \fu_enable [8] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" - case 1'1 - assign \fus_cu_rdmaskn_i$27 $307 - end - end - end - sync init - end - process $group_155 - assign \fus_oper_i_ldst_ldst0__insn_type 7'0000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" - switch { \ivalid_i } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" - switch \core_core_insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:184" - attribute \nmigen.decoding "OP_ATTN/5" - case 7'0000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" - attribute \nmigen.decoding "OP_NOP/1" - case 7'0000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" - attribute \nmigen.decoding "" - case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" - switch { \fu_enable [9] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" - case 1'1 - assign \fus_oper_i_ldst_ldst0__insn_type \dec_LDST_LDST_LDST__insn_type - end - end - end - sync init - end - process $group_156 - assign \fus_oper_i_ldst_ldst0__fn_unit 11'00000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" - switch { \ivalid_i } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" - switch \core_core_insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:184" - attribute \nmigen.decoding "OP_ATTN/5" - case 7'0000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" - attribute \nmigen.decoding "OP_NOP/1" - case 7'0000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" - attribute \nmigen.decoding "" - case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" - switch { \fu_enable [9] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" - case 1'1 - assign \fus_oper_i_ldst_ldst0__fn_unit \dec_LDST_LDST_LDST__fn_unit - end - end - end - sync init - end - process $group_157 - assign \fus_oper_i_ldst_ldst0__imm_data__data 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \fus_oper_i_ldst_ldst0__imm_data__ok 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" - switch { \ivalid_i } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" - switch \core_core_insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:184" - attribute \nmigen.decoding "OP_ATTN/5" - case 7'0000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" - attribute \nmigen.decoding "OP_NOP/1" - case 7'0000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" - attribute \nmigen.decoding "" - case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" - switch { \fu_enable [9] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" - case 1'1 - assign { \fus_oper_i_ldst_ldst0__imm_data__ok \fus_oper_i_ldst_ldst0__imm_data__data } { \dec_LDST_LDST_LDST__imm_data__ok \dec_LDST_LDST_LDST__imm_data__data } - end - end - end - sync init - end - process $group_159 - assign \fus_oper_i_ldst_ldst0__zero_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" - switch { \ivalid_i } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" - switch \core_core_insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:184" - attribute \nmigen.decoding "OP_ATTN/5" - case 7'0000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" - attribute \nmigen.decoding "OP_NOP/1" - case 7'0000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" - attribute \nmigen.decoding "" - case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" - switch { \fu_enable [9] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" - case 1'1 - assign \fus_oper_i_ldst_ldst0__zero_a \dec_LDST_LDST_LDST__zero_a - end - end - end - sync init - end - process $group_160 - assign \fus_oper_i_ldst_ldst0__rc__rc 1'0 - assign \fus_oper_i_ldst_ldst0__rc__ok 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" - switch { \ivalid_i } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" - switch \core_core_insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:184" - attribute \nmigen.decoding "OP_ATTN/5" - case 7'0000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" - attribute \nmigen.decoding "OP_NOP/1" - case 7'0000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" - attribute \nmigen.decoding "" - case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" - switch { \fu_enable [9] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" - case 1'1 - assign { \fus_oper_i_ldst_ldst0__rc__ok \fus_oper_i_ldst_ldst0__rc__rc } { \dec_LDST_LDST_LDST__rc__ok \dec_LDST_LDST_LDST__rc__rc } - end - end - end - sync init - end - process $group_162 - assign \fus_oper_i_ldst_ldst0__oe__oe 1'0 - assign \fus_oper_i_ldst_ldst0__oe__ok 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" - switch { \ivalid_i } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" - switch \core_core_insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:184" - attribute \nmigen.decoding "OP_ATTN/5" - case 7'0000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" - attribute \nmigen.decoding "OP_NOP/1" - case 7'0000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" - attribute \nmigen.decoding "" - case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" - switch { \fu_enable [9] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" - case 1'1 - assign { \fus_oper_i_ldst_ldst0__oe__ok \fus_oper_i_ldst_ldst0__oe__oe } { \dec_LDST_LDST_LDST__oe__ok \dec_LDST_LDST_LDST__oe__oe } - end - end - end - sync init - end - process $group_164 - assign \fus_oper_i_ldst_ldst0__is_32bit 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" - switch { \ivalid_i } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" - switch \core_core_insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:184" - attribute \nmigen.decoding "OP_ATTN/5" - case 7'0000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" - attribute \nmigen.decoding "OP_NOP/1" - case 7'0000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" - attribute \nmigen.decoding "" - case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" - switch { \fu_enable [9] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" - case 1'1 - assign \fus_oper_i_ldst_ldst0__is_32bit \dec_LDST_LDST_LDST__is_32bit - end - end - end - sync init - end - process $group_165 - assign \fus_oper_i_ldst_ldst0__is_signed 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" - switch { \ivalid_i } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" - switch \core_core_insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:184" - attribute \nmigen.decoding "OP_ATTN/5" - case 7'0000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" - attribute \nmigen.decoding "OP_NOP/1" - case 7'0000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" - attribute \nmigen.decoding "" - case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" - switch { \fu_enable [9] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" - case 1'1 - assign \fus_oper_i_ldst_ldst0__is_signed \dec_LDST_LDST_LDST__is_signed - end - end - end - sync init - end - process $group_166 - assign \fus_oper_i_ldst_ldst0__data_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" - switch { \ivalid_i } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" - switch \core_core_insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:184" - attribute \nmigen.decoding "OP_ATTN/5" - case 7'0000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" - attribute \nmigen.decoding "OP_NOP/1" - case 7'0000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" - attribute \nmigen.decoding "" - case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" - switch { \fu_enable [9] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" - case 1'1 - assign \fus_oper_i_ldst_ldst0__data_len \dec_LDST_LDST_LDST__data_len - end - end - end - sync init - end - process $group_167 - assign \fus_oper_i_ldst_ldst0__byte_reverse 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" - switch { \ivalid_i } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" - switch \core_core_insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:184" - attribute \nmigen.decoding "OP_ATTN/5" - case 7'0000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" - attribute \nmigen.decoding "OP_NOP/1" - case 7'0000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" - attribute \nmigen.decoding "" - case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" - switch { \fu_enable [9] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" - case 1'1 - assign \fus_oper_i_ldst_ldst0__byte_reverse \dec_LDST_LDST_LDST__byte_reverse - end - end - end - sync init - end - process $group_168 - assign \fus_oper_i_ldst_ldst0__sign_extend 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" - switch { \ivalid_i } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" - switch \core_core_insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:184" - attribute \nmigen.decoding "OP_ATTN/5" - case 7'0000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" - attribute \nmigen.decoding "OP_NOP/1" - case 7'0000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" - attribute \nmigen.decoding "" - case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" - switch { \fu_enable [9] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" - case 1'1 - assign \fus_oper_i_ldst_ldst0__sign_extend \dec_LDST_LDST_LDST__sign_extend - end - end - end - sync init - end - process $group_169 - assign \fus_oper_i_ldst_ldst0__ldst_mode 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" - switch { \ivalid_i } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" - switch \core_core_insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:184" - attribute \nmigen.decoding "OP_ATTN/5" - case 7'0000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" - attribute \nmigen.decoding "OP_NOP/1" - case 7'0000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" - attribute \nmigen.decoding "" - case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" - switch { \fu_enable [9] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" - case 1'1 - assign \fus_oper_i_ldst_ldst0__ldst_mode \dec_LDST_LDST_LDST__ldst_mode - end - end - end - sync init - end - process $group_170 - assign \fus_oper_i_ldst_ldst0__insn 32'00000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" - switch { \ivalid_i } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" - switch \core_core_insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:184" - attribute \nmigen.decoding "OP_ATTN/5" - case 7'0000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" - attribute \nmigen.decoding "OP_NOP/1" - case 7'0000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" - attribute \nmigen.decoding "" - case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" - switch { \fu_enable [9] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" - case 1'1 - assign \fus_oper_i_ldst_ldst0__insn \dec_LDST_LDST_LDST__insn - end - end - end - sync init - end - process $group_171 - assign \fus_cu_issue_i$28 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" - switch { \ivalid_i } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" - switch \core_core_insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:184" - attribute \nmigen.decoding "OP_ATTN/5" - case 7'0000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" - attribute \nmigen.decoding "OP_NOP/1" - case 7'0000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" - attribute \nmigen.decoding "" - case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" - switch { \fu_enable [9] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" - case 1'1 - assign \fus_cu_issue_i$28 \issue_i - end - end - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" - wire width 3 $329 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:208" - cell $not $330 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A { \core_reg3_ok \core_reg2_ok \core_reg1_ok } - connect \Y $329 - end - process $group_172 - assign \fus_cu_rdmaskn_i$30 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" - switch { \ivalid_i } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:181" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:182" - switch \core_core_insn_type - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:184" - attribute \nmigen.decoding "OP_ATTN/5" - case 7'0000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:187" - attribute \nmigen.decoding "OP_NOP/1" - case 7'0000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:191" - attribute \nmigen.decoding "" - case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" - switch { \fu_enable [9] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:199" - case 1'1 - assign \fus_cu_rdmaskn_i$30 $329 - end - end - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:240" - wire width 1 \rdflag_INT_ra_0 - process $group_173 - assign \rdflag_INT_ra_0 1'0 - assign \rdflag_INT_ra_0 \core_reg1_ok - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:264" - wire width 1 \pick_INT_ra_alu0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" - wire width 1 $331 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" - cell $and $332 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \fus_cu_rd__rel_o [0] - connect \B \fu_enable [0] - connect \Y $331 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" - wire width 1 $333 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" - cell $and $334 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $331 - connect \B \rdflag_INT_ra_0 - connect \Y $333 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" - wire width 1 $335 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:266" - wire width 1 \dp_INT_ra_alu0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:266" - wire width 1 \dp_INT_ra_alu0_0$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" - cell $not $336 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \dp_INT_ra_alu0_0 - connect \Y $335 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" - wire width 1 $337 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" - cell $and $338 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $333 - connect \B $335 - connect \Y $337 - end - process $group_174 - assign \pick_INT_ra_alu0_0 1'0 - assign \pick_INT_ra_alu0_0 $337 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:264" - wire width 1 \pick_INT_ra_cr0_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:264" - wire width 1 \pick_INT_ra_trap0_2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:264" - wire width 1 \pick_INT_ra_logical0_3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:264" - wire width 1 \pick_INT_ra_spr0_4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:264" - wire width 1 \pick_INT_ra_div0_5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:264" - wire width 1 \pick_INT_ra_mul0_6 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:264" - wire width 1 \pick_INT_ra_shiftrot0_7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:264" - wire width 1 \pick_INT_ra_ldst0_8 - process $group_175 - assign \rdpick_INT_ra_i 9'000000000 - assign \rdpick_INT_ra_i [0] \pick_INT_ra_alu0_0 - assign \rdpick_INT_ra_i [1] \pick_INT_ra_cr0_1 - assign \rdpick_INT_ra_i [2] \pick_INT_ra_trap0_2 - assign \rdpick_INT_ra_i [3] \pick_INT_ra_logical0_3 - assign \rdpick_INT_ra_i [4] \pick_INT_ra_spr0_4 - assign \rdpick_INT_ra_i [5] \pick_INT_ra_div0_5 - assign \rdpick_INT_ra_i [6] \pick_INT_ra_mul0_6 - assign \rdpick_INT_ra_i [7] \pick_INT_ra_shiftrot0_7 - assign \rdpick_INT_ra_i [8] \pick_INT_ra_ldst0_8 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:266" - wire width 1 \dp_INT_rb_alu0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:266" - wire width 1 \dp_INT_rb_alu0_0$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:266" - wire width 1 \dp_XER_xer_so_alu0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:266" - wire width 1 \dp_XER_xer_so_alu0_0$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:266" - wire width 1 \dp_XER_xer_ca_alu0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:266" - wire width 1 \dp_XER_xer_ca_alu0_0$next - process $group_176 - assign \fus_cu_rd__go_i 4'0000 - assign \fus_cu_rd__go_i [0] \dp_INT_ra_alu0_0 - assign \fus_cu_rd__go_i [1] \dp_INT_rb_alu0_0 - assign \fus_cu_rd__go_i [2] \dp_XER_xer_so_alu0_0 - assign \fus_cu_rd__go_i [3] \dp_XER_xer_ca_alu0_0 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:265" - wire width 1 \rp_INT_ra_alu0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" - wire width 1 $339 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" - cell $and $340 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \rdpick_INT_ra_o [0] - connect \B \rdpick_INT_ra_en_o - connect \Y $339 - end - process $group_177 - assign \rp_INT_ra_alu0_0 1'0 - assign \rp_INT_ra_alu0_0 $339 - sync init - end - process $group_178 - assign \dp_INT_ra_alu0_0$next \dp_INT_ra_alu0_0 - assign \dp_INT_ra_alu0_0$next \rp_INT_ra_alu0_0 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \dp_INT_ra_alu0_0$next 1'0 - end - sync init - update \dp_INT_ra_alu0_0 1'0 - sync posedge \coresync_clk - update \dp_INT_ra_alu0_0 \dp_INT_ra_alu0_0$next - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:263" - wire width 5 \addr_en_INT_ra_alu0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" - wire width 5 $341 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" - cell $mux $342 - parameter \WIDTH 5 - connect \A 5'00000 - connect \B \core_reg1 - connect \S \rp_INT_ra_alu0_0 - connect \Y $341 - end - process $group_179 - assign \addr_en_INT_ra_alu0_0 5'00000 - assign \addr_en_INT_ra_alu0_0 $341 - sync init - end - process $group_180 - assign \fus_src1_i 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" - switch { \dp_INT_ra_alu0_0 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" - case 1'1 - assign \fus_src1_i \int_src1__data_o - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" - wire width 1 $343 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" - cell $and $344 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \fus_cu_rd__rel_o$31 [0] - connect \B \fu_enable [1] - connect \Y $343 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" - wire width 1 $345 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" - cell $and $346 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $343 - connect \B \rdflag_INT_ra_0 - connect \Y $345 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" - wire width 1 $347 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:266" - wire width 1 \dp_INT_ra_cr0_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:266" - wire width 1 \dp_INT_ra_cr0_1$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" - cell $not $348 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \dp_INT_ra_cr0_1 - connect \Y $347 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" - wire width 1 $349 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" - cell $and $350 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $345 - connect \B $347 - connect \Y $349 - end - process $group_181 - assign \pick_INT_ra_cr0_1 1'0 - assign \pick_INT_ra_cr0_1 $349 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:266" - wire width 1 \dp_INT_rb_cr0_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:266" - wire width 1 \dp_INT_rb_cr0_1$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:266" - wire width 1 \dp_CR_full_cr_cr0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:266" - wire width 1 \dp_CR_full_cr_cr0_0$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:266" - wire width 1 \dp_CR_cr_a_cr0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:266" - wire width 1 \dp_CR_cr_a_cr0_0$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:266" - wire width 1 \dp_CR_cr_b_cr0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:266" - wire width 1 \dp_CR_cr_b_cr0_0$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:266" - wire width 1 \dp_CR_cr_c_cr0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:266" - wire width 1 \dp_CR_cr_c_cr0_0$next - process $group_182 - assign \fus_cu_rd__go_i$32 6'000000 - assign \fus_cu_rd__go_i$32 [0] \dp_INT_ra_cr0_1 - assign \fus_cu_rd__go_i$32 [1] \dp_INT_rb_cr0_1 - assign \fus_cu_rd__go_i$32 [2] \dp_CR_full_cr_cr0_0 - assign \fus_cu_rd__go_i$32 [3] \dp_CR_cr_a_cr0_0 - assign \fus_cu_rd__go_i$32 [4] \dp_CR_cr_b_cr0_0 - assign \fus_cu_rd__go_i$32 [5] \dp_CR_cr_c_cr0_0 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:265" - wire width 1 \rp_INT_ra_cr0_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" - wire width 1 $351 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" - cell $and $352 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \rdpick_INT_ra_o [1] - connect \B \rdpick_INT_ra_en_o - connect \Y $351 - end - process $group_183 - assign \rp_INT_ra_cr0_1 1'0 - assign \rp_INT_ra_cr0_1 $351 - sync init - end - process $group_184 - assign \dp_INT_ra_cr0_1$next \dp_INT_ra_cr0_1 - assign \dp_INT_ra_cr0_1$next \rp_INT_ra_cr0_1 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \dp_INT_ra_cr0_1$next 1'0 - end - sync init - update \dp_INT_ra_cr0_1 1'0 - sync posedge \coresync_clk - update \dp_INT_ra_cr0_1 \dp_INT_ra_cr0_1$next - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:263" - wire width 5 \addr_en_INT_ra_cr0_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" - wire width 5 $353 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" - cell $mux $354 - parameter \WIDTH 5 - connect \A 5'00000 - connect \B \core_reg1 - connect \S \rp_INT_ra_cr0_1 - connect \Y $353 - end - process $group_185 - assign \addr_en_INT_ra_cr0_1 5'00000 - assign \addr_en_INT_ra_cr0_1 $353 - sync init - end - process $group_186 - assign \fus_src1_i$33 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" - switch { \dp_INT_ra_cr0_1 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" - case 1'1 - assign \fus_src1_i$33 \int_src1__data_o - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" - wire width 1 $355 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" - cell $and $356 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \fus_cu_rd__rel_o$34 [0] - connect \B \fu_enable [3] - connect \Y $355 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" - wire width 1 $357 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" - cell $and $358 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $355 - connect \B \rdflag_INT_ra_0 - connect \Y $357 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" - wire width 1 $359 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:266" - wire width 1 \dp_INT_ra_trap0_2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:266" - wire width 1 \dp_INT_ra_trap0_2$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" - cell $not $360 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \dp_INT_ra_trap0_2 - connect \Y $359 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" - wire width 1 $361 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" - cell $and $362 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $357 - connect \B $359 - connect \Y $361 - end - process $group_187 - assign \pick_INT_ra_trap0_2 1'0 - assign \pick_INT_ra_trap0_2 $361 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:266" - wire width 1 \dp_INT_rb_trap0_2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:266" - wire width 1 \dp_INT_rb_trap0_2$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:266" - wire width 1 \dp_FAST_fast1_trap0_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:266" - wire width 1 \dp_FAST_fast1_trap0_1$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:266" - wire width 1 \dp_FAST_fast2_trap0_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:266" - wire width 1 \dp_FAST_fast2_trap0_1$next - process $group_188 - assign \fus_cu_rd__go_i$35 4'0000 - assign \fus_cu_rd__go_i$35 [0] \dp_INT_ra_trap0_2 - assign \fus_cu_rd__go_i$35 [1] \dp_INT_rb_trap0_2 - assign \fus_cu_rd__go_i$35 [2] \dp_FAST_fast1_trap0_1 - assign \fus_cu_rd__go_i$35 [3] \dp_FAST_fast2_trap0_1 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:265" - wire width 1 \rp_INT_ra_trap0_2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" - wire width 1 $363 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" - cell $and $364 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \rdpick_INT_ra_o [2] - connect \B \rdpick_INT_ra_en_o - connect \Y $363 - end - process $group_189 - assign \rp_INT_ra_trap0_2 1'0 - assign \rp_INT_ra_trap0_2 $363 - sync init - end - process $group_190 - assign \dp_INT_ra_trap0_2$next \dp_INT_ra_trap0_2 - assign \dp_INT_ra_trap0_2$next \rp_INT_ra_trap0_2 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \dp_INT_ra_trap0_2$next 1'0 - end - sync init - update \dp_INT_ra_trap0_2 1'0 - sync posedge \coresync_clk - update \dp_INT_ra_trap0_2 \dp_INT_ra_trap0_2$next - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:263" - wire width 5 \addr_en_INT_ra_trap0_2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" - wire width 5 $365 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" - cell $mux $366 - parameter \WIDTH 5 - connect \A 5'00000 - connect \B \core_reg1 - connect \S \rp_INT_ra_trap0_2 - connect \Y $365 - end - process $group_191 - assign \addr_en_INT_ra_trap0_2 5'00000 - assign \addr_en_INT_ra_trap0_2 $365 - sync init - end - process $group_192 - assign \fus_src1_i$36 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" - switch { \dp_INT_ra_trap0_2 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" - case 1'1 - assign \fus_src1_i$36 \int_src1__data_o - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" - wire width 1 $367 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" - cell $and $368 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \fus_cu_rd__rel_o$37 [0] - connect \B \fu_enable [4] - connect \Y $367 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" - wire width 1 $369 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" - cell $and $370 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $367 - connect \B \rdflag_INT_ra_0 - connect \Y $369 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" - wire width 1 $371 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:266" - wire width 1 \dp_INT_ra_logical0_3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:266" - wire width 1 \dp_INT_ra_logical0_3$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" - cell $not $372 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \dp_INT_ra_logical0_3 - connect \Y $371 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" - wire width 1 $373 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" - cell $and $374 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $369 - connect \B $371 - connect \Y $373 - end - process $group_193 - assign \pick_INT_ra_logical0_3 1'0 - assign \pick_INT_ra_logical0_3 $373 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:266" - wire width 1 \dp_INT_rb_logical0_3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:266" - wire width 1 \dp_INT_rb_logical0_3$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:266" - wire width 1 \dp_XER_xer_so_logical0_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:266" - wire width 1 \dp_XER_xer_so_logical0_1$next - process $group_194 - assign \fus_cu_rd__go_i$38 3'000 - assign \fus_cu_rd__go_i$38 [0] \dp_INT_ra_logical0_3 - assign \fus_cu_rd__go_i$38 [1] \dp_INT_rb_logical0_3 - assign \fus_cu_rd__go_i$38 [2] \dp_XER_xer_so_logical0_1 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:265" - wire width 1 \rp_INT_ra_logical0_3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" - wire width 1 $375 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" - cell $and $376 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \rdpick_INT_ra_o [3] - connect \B \rdpick_INT_ra_en_o - connect \Y $375 - end - process $group_195 - assign \rp_INT_ra_logical0_3 1'0 - assign \rp_INT_ra_logical0_3 $375 - sync init - end - process $group_196 - assign \dp_INT_ra_logical0_3$next \dp_INT_ra_logical0_3 - assign \dp_INT_ra_logical0_3$next \rp_INT_ra_logical0_3 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \dp_INT_ra_logical0_3$next 1'0 - end - sync init - update \dp_INT_ra_logical0_3 1'0 - sync posedge \coresync_clk - update \dp_INT_ra_logical0_3 \dp_INT_ra_logical0_3$next - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:263" - wire width 5 \addr_en_INT_ra_logical0_3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" - wire width 5 $377 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" - cell $mux $378 - parameter \WIDTH 5 - connect \A 5'00000 - connect \B \core_reg1 - connect \S \rp_INT_ra_logical0_3 - connect \Y $377 - end - process $group_197 - assign \addr_en_INT_ra_logical0_3 5'00000 - assign \addr_en_INT_ra_logical0_3 $377 - sync init - end - process $group_198 - assign \fus_src1_i$39 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" - switch { \dp_INT_ra_logical0_3 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" - case 1'1 - assign \fus_src1_i$39 \int_src1__data_o - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" - wire width 1 $379 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" - cell $and $380 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \fus_cu_rd__rel_o$40 [0] - connect \B \fu_enable [5] - connect \Y $379 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" - wire width 1 $381 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" - cell $and $382 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $379 - connect \B \rdflag_INT_ra_0 - connect \Y $381 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" - wire width 1 $383 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:266" - wire width 1 \dp_INT_ra_spr0_4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:266" - wire width 1 \dp_INT_ra_spr0_4$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" - cell $not $384 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \dp_INT_ra_spr0_4 - connect \Y $383 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" - wire width 1 $385 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" - cell $and $386 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $381 - connect \B $383 - connect \Y $385 - end - process $group_199 - assign \pick_INT_ra_spr0_4 1'0 - assign \pick_INT_ra_spr0_4 $385 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:266" - wire width 1 \dp_XER_xer_so_spr0_2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:266" - wire width 1 \dp_XER_xer_so_spr0_2$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:266" - wire width 1 \dp_XER_xer_ca_spr0_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:266" - wire width 1 \dp_XER_xer_ca_spr0_1$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:266" - wire width 1 \dp_XER_xer_ov_spr0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:266" - wire width 1 \dp_XER_xer_ov_spr0_0$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:266" - wire width 1 \dp_FAST_fast1_spr0_2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:266" - wire width 1 \dp_FAST_fast1_spr0_2$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:266" - wire width 1 \dp_SPR_spr1_spr0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:266" - wire width 1 \dp_SPR_spr1_spr0_0$next - process $group_200 - assign \fus_cu_rd__go_i$41 6'000000 - assign \fus_cu_rd__go_i$41 [0] \dp_INT_ra_spr0_4 - assign \fus_cu_rd__go_i$41 [3] \dp_XER_xer_so_spr0_2 - assign \fus_cu_rd__go_i$41 [5] \dp_XER_xer_ca_spr0_1 - assign \fus_cu_rd__go_i$41 [4] \dp_XER_xer_ov_spr0_0 - assign \fus_cu_rd__go_i$41 [2] \dp_FAST_fast1_spr0_2 - assign \fus_cu_rd__go_i$41 [1] \dp_SPR_spr1_spr0_0 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:265" - wire width 1 \rp_INT_ra_spr0_4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" - wire width 1 $387 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" - cell $and $388 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \rdpick_INT_ra_o [4] - connect \B \rdpick_INT_ra_en_o - connect \Y $387 - end - process $group_201 - assign \rp_INT_ra_spr0_4 1'0 - assign \rp_INT_ra_spr0_4 $387 - sync init - end - process $group_202 - assign \dp_INT_ra_spr0_4$next \dp_INT_ra_spr0_4 - assign \dp_INT_ra_spr0_4$next \rp_INT_ra_spr0_4 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \dp_INT_ra_spr0_4$next 1'0 - end - sync init - update \dp_INT_ra_spr0_4 1'0 - sync posedge \coresync_clk - update \dp_INT_ra_spr0_4 \dp_INT_ra_spr0_4$next - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:263" - wire width 5 \addr_en_INT_ra_spr0_4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" - wire width 5 $389 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" - cell $mux $390 - parameter \WIDTH 5 - connect \A 5'00000 - connect \B \core_reg1 - connect \S \rp_INT_ra_spr0_4 - connect \Y $389 - end - process $group_203 - assign \addr_en_INT_ra_spr0_4 5'00000 - assign \addr_en_INT_ra_spr0_4 $389 - sync init - end - process $group_204 - assign \fus_src1_i$42 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" - switch { \dp_INT_ra_spr0_4 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" - case 1'1 - assign \fus_src1_i$42 \int_src1__data_o - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" - wire width 1 $391 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" - cell $and $392 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \fus_cu_rd__rel_o$43 [0] - connect \B \fu_enable [6] - connect \Y $391 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" - wire width 1 $393 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" - cell $and $394 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $391 - connect \B \rdflag_INT_ra_0 - connect \Y $393 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" - wire width 1 $395 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:266" - wire width 1 \dp_INT_ra_div0_5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:266" - wire width 1 \dp_INT_ra_div0_5$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" - cell $not $396 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \dp_INT_ra_div0_5 - connect \Y $395 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" - wire width 1 $397 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" - cell $and $398 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $393 - connect \B $395 - connect \Y $397 - end - process $group_205 - assign \pick_INT_ra_div0_5 1'0 - assign \pick_INT_ra_div0_5 $397 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:266" - wire width 1 \dp_INT_rb_div0_4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:266" - wire width 1 \dp_INT_rb_div0_4$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:266" - wire width 1 \dp_XER_xer_so_div0_3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:266" - wire width 1 \dp_XER_xer_so_div0_3$next - process $group_206 - assign \fus_cu_rd__go_i$44 3'000 - assign \fus_cu_rd__go_i$44 [0] \dp_INT_ra_div0_5 - assign \fus_cu_rd__go_i$44 [1] \dp_INT_rb_div0_4 - assign \fus_cu_rd__go_i$44 [2] \dp_XER_xer_so_div0_3 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:265" - wire width 1 \rp_INT_ra_div0_5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" - wire width 1 $399 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" - cell $and $400 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \rdpick_INT_ra_o [5] - connect \B \rdpick_INT_ra_en_o - connect \Y $399 - end - process $group_207 - assign \rp_INT_ra_div0_5 1'0 - assign \rp_INT_ra_div0_5 $399 - sync init - end - process $group_208 - assign \dp_INT_ra_div0_5$next \dp_INT_ra_div0_5 - assign \dp_INT_ra_div0_5$next \rp_INT_ra_div0_5 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \dp_INT_ra_div0_5$next 1'0 - end - sync init - update \dp_INT_ra_div0_5 1'0 - sync posedge \coresync_clk - update \dp_INT_ra_div0_5 \dp_INT_ra_div0_5$next - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:263" - wire width 5 \addr_en_INT_ra_div0_5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" - wire width 5 $401 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" - cell $mux $402 - parameter \WIDTH 5 - connect \A 5'00000 - connect \B \core_reg1 - connect \S \rp_INT_ra_div0_5 - connect \Y $401 - end - process $group_209 - assign \addr_en_INT_ra_div0_5 5'00000 - assign \addr_en_INT_ra_div0_5 $401 - sync init - end - process $group_210 - assign \fus_src1_i$45 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" - switch { \dp_INT_ra_div0_5 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" - case 1'1 - assign \fus_src1_i$45 \int_src1__data_o - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" - wire width 1 $403 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" - cell $and $404 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \fus_cu_rd__rel_o$46 [0] - connect \B \fu_enable [7] - connect \Y $403 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" - wire width 1 $405 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" - cell $and $406 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $403 - connect \B \rdflag_INT_ra_0 - connect \Y $405 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" - wire width 1 $407 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:266" - wire width 1 \dp_INT_ra_mul0_6 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:266" - wire width 1 \dp_INT_ra_mul0_6$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" - cell $not $408 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \dp_INT_ra_mul0_6 - connect \Y $407 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" - wire width 1 $409 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" - cell $and $410 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $405 - connect \B $407 - connect \Y $409 - end - process $group_211 - assign \pick_INT_ra_mul0_6 1'0 - assign \pick_INT_ra_mul0_6 $409 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:266" - wire width 1 \dp_INT_rb_mul0_5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:266" - wire width 1 \dp_INT_rb_mul0_5$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:266" - wire width 1 \dp_XER_xer_so_mul0_4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:266" - wire width 1 \dp_XER_xer_so_mul0_4$next - process $group_212 - assign \fus_cu_rd__go_i$47 3'000 - assign \fus_cu_rd__go_i$47 [0] \dp_INT_ra_mul0_6 - assign \fus_cu_rd__go_i$47 [1] \dp_INT_rb_mul0_5 - assign \fus_cu_rd__go_i$47 [2] \dp_XER_xer_so_mul0_4 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:265" - wire width 1 \rp_INT_ra_mul0_6 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" - wire width 1 $411 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" - cell $and $412 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \rdpick_INT_ra_o [6] - connect \B \rdpick_INT_ra_en_o - connect \Y $411 - end - process $group_213 - assign \rp_INT_ra_mul0_6 1'0 - assign \rp_INT_ra_mul0_6 $411 - sync init - end - process $group_214 - assign \dp_INT_ra_mul0_6$next \dp_INT_ra_mul0_6 - assign \dp_INT_ra_mul0_6$next \rp_INT_ra_mul0_6 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \dp_INT_ra_mul0_6$next 1'0 - end - sync init - update \dp_INT_ra_mul0_6 1'0 - sync posedge \coresync_clk - update \dp_INT_ra_mul0_6 \dp_INT_ra_mul0_6$next - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:263" - wire width 5 \addr_en_INT_ra_mul0_6 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" - wire width 5 $413 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" - cell $mux $414 - parameter \WIDTH 5 - connect \A 5'00000 - connect \B \core_reg1 - connect \S \rp_INT_ra_mul0_6 - connect \Y $413 - end - process $group_215 - assign \addr_en_INT_ra_mul0_6 5'00000 - assign \addr_en_INT_ra_mul0_6 $413 - sync init - end - process $group_216 - assign \fus_src1_i$48 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" - switch { \dp_INT_ra_mul0_6 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" - case 1'1 - assign \fus_src1_i$48 \int_src1__data_o - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" - wire width 1 $415 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" - cell $and $416 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \fus_cu_rd__rel_o$49 [0] - connect \B \fu_enable [8] - connect \Y $415 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" - wire width 1 $417 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" - cell $and $418 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $415 - connect \B \rdflag_INT_ra_0 - connect \Y $417 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" - wire width 1 $419 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:266" - wire width 1 \dp_INT_ra_shiftrot0_7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:266" - wire width 1 \dp_INT_ra_shiftrot0_7$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" - cell $not $420 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \dp_INT_ra_shiftrot0_7 - connect \Y $419 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" - wire width 1 $421 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" - cell $and $422 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $417 - connect \B $419 - connect \Y $421 - end - process $group_217 - assign \pick_INT_ra_shiftrot0_7 1'0 - assign \pick_INT_ra_shiftrot0_7 $421 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:266" - wire width 1 \dp_INT_rb_shiftrot0_6 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:266" - wire width 1 \dp_INT_rb_shiftrot0_6$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:266" - wire width 1 \dp_INT_rc_shiftrot0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:266" - wire width 1 \dp_INT_rc_shiftrot0_0$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:266" - wire width 1 \dp_XER_xer_so_shiftrot0_5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:266" - wire width 1 \dp_XER_xer_so_shiftrot0_5$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:266" - wire width 1 \dp_XER_xer_ca_shiftrot0_2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:266" - wire width 1 \dp_XER_xer_ca_shiftrot0_2$next - process $group_218 - assign \fus_cu_rd__go_i$50 5'00000 - assign \fus_cu_rd__go_i$50 [0] \dp_INT_ra_shiftrot0_7 - assign \fus_cu_rd__go_i$50 [1] \dp_INT_rb_shiftrot0_6 - assign \fus_cu_rd__go_i$50 [2] \dp_INT_rc_shiftrot0_0 - assign \fus_cu_rd__go_i$50 [3] \dp_XER_xer_so_shiftrot0_5 - assign \fus_cu_rd__go_i$50 [4] \dp_XER_xer_ca_shiftrot0_2 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:265" - wire width 1 \rp_INT_ra_shiftrot0_7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" - wire width 1 $423 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" - cell $and $424 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \rdpick_INT_ra_o [7] - connect \B \rdpick_INT_ra_en_o - connect \Y $423 - end - process $group_219 - assign \rp_INT_ra_shiftrot0_7 1'0 - assign \rp_INT_ra_shiftrot0_7 $423 - sync init - end - process $group_220 - assign \dp_INT_ra_shiftrot0_7$next \dp_INT_ra_shiftrot0_7 - assign \dp_INT_ra_shiftrot0_7$next \rp_INT_ra_shiftrot0_7 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \dp_INT_ra_shiftrot0_7$next 1'0 - end - sync init - update \dp_INT_ra_shiftrot0_7 1'0 - sync posedge \coresync_clk - update \dp_INT_ra_shiftrot0_7 \dp_INT_ra_shiftrot0_7$next - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:263" - wire width 5 \addr_en_INT_ra_shiftrot0_7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" - wire width 5 $425 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" - cell $mux $426 - parameter \WIDTH 5 - connect \A 5'00000 - connect \B \core_reg1 - connect \S \rp_INT_ra_shiftrot0_7 - connect \Y $425 - end - process $group_221 - assign \addr_en_INT_ra_shiftrot0_7 5'00000 - assign \addr_en_INT_ra_shiftrot0_7 $425 - sync init - end - process $group_222 - assign \fus_src1_i$51 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" - switch { \dp_INT_ra_shiftrot0_7 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" - case 1'1 - assign \fus_src1_i$51 \int_src1__data_o - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" - wire width 1 $427 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" - cell $and $428 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \fus_cu_rd__rel_o$52 [0] - connect \B \fu_enable [9] - connect \Y $427 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" - wire width 1 $429 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" - cell $and $430 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $427 - connect \B \rdflag_INT_ra_0 - connect \Y $429 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" - wire width 1 $431 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:266" - wire width 1 \dp_INT_ra_ldst0_8 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:266" - wire width 1 \dp_INT_ra_ldst0_8$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" - cell $not $432 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \dp_INT_ra_ldst0_8 - connect \Y $431 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" - wire width 1 $433 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" - cell $and $434 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $429 - connect \B $431 - connect \Y $433 - end - process $group_223 - assign \pick_INT_ra_ldst0_8 1'0 - assign \pick_INT_ra_ldst0_8 $433 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:266" - wire width 1 \dp_INT_rb_ldst0_7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:266" - wire width 1 \dp_INT_rb_ldst0_7$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:266" - wire width 1 \dp_INT_rc_ldst0_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:266" - wire width 1 \dp_INT_rc_ldst0_1$next - process $group_224 - assign \fus_cu_rd__go_i$53 3'000 - assign \fus_cu_rd__go_i$53 [0] \dp_INT_ra_ldst0_8 - assign \fus_cu_rd__go_i$53 [1] \dp_INT_rb_ldst0_7 - assign \fus_cu_rd__go_i$53 [2] \dp_INT_rc_ldst0_1 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:265" - wire width 1 \rp_INT_ra_ldst0_8 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" - wire width 1 $435 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" - cell $and $436 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \rdpick_INT_ra_o [8] - connect \B \rdpick_INT_ra_en_o - connect \Y $435 - end - process $group_225 - assign \rp_INT_ra_ldst0_8 1'0 - assign \rp_INT_ra_ldst0_8 $435 - sync init - end - process $group_226 - assign \dp_INT_ra_ldst0_8$next \dp_INT_ra_ldst0_8 - assign \dp_INT_ra_ldst0_8$next \rp_INT_ra_ldst0_8 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \dp_INT_ra_ldst0_8$next 1'0 - end - sync init - update \dp_INT_ra_ldst0_8 1'0 - sync posedge \coresync_clk - update \dp_INT_ra_ldst0_8 \dp_INT_ra_ldst0_8$next - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:263" - wire width 5 \addr_en_INT_ra_ldst0_8 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" - wire width 5 $437 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" - cell $mux $438 - parameter \WIDTH 5 - connect \A 5'00000 - connect \B \core_reg1 - connect \S \rp_INT_ra_ldst0_8 - connect \Y $437 - end - process $group_227 - assign \addr_en_INT_ra_ldst0_8 5'00000 - assign \addr_en_INT_ra_ldst0_8 $437 - sync init - end - process $group_228 - assign \fus_src1_i$54 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" - switch { \dp_INT_ra_ldst0_8 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" - case 1'1 - assign \fus_src1_i$54 \int_src1__data_o - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - wire width 5 $439 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $or $440 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 5 - connect \A \addr_en_INT_ra_alu0_0 - connect \B \addr_en_INT_ra_cr0_1 - connect \Y $439 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - wire width 5 $441 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $or $442 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 5 - connect \A \addr_en_INT_ra_trap0_2 - connect \B \addr_en_INT_ra_logical0_3 - connect \Y $441 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - wire width 5 $443 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - cell $or $444 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 5 - connect \A $439 - connect \B $441 - connect \Y $443 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - wire width 5 $445 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $or $446 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 5 - connect \A \addr_en_INT_ra_spr0_4 - connect \B \addr_en_INT_ra_div0_5 - connect \Y $445 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - wire width 5 $447 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $or $448 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 5 - connect \A \addr_en_INT_ra_shiftrot0_7 - connect \B \addr_en_INT_ra_ldst0_8 - connect \Y $447 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - wire width 5 $449 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - cell $or $450 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 5 - connect \A \addr_en_INT_ra_mul0_6 - connect \B $447 - connect \Y $449 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - wire width 5 $451 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - cell $or $452 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 5 - connect \A $445 - connect \B $449 - connect \Y $451 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - wire width 5 $453 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - cell $or $454 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 5 - connect \A $443 - connect \B $451 - connect \Y $453 - end - process $group_229 - assign \int_src1__addr 5'00000 - assign \int_src1__addr $453 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:304" - wire width 1 $455 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:304" - cell $reduce_bool $456 - parameter \A_SIGNED 0 - parameter \A_WIDTH 9 - parameter \Y_WIDTH 1 - connect \A { \rp_INT_ra_ldst0_8 \rp_INT_ra_shiftrot0_7 \rp_INT_ra_mul0_6 \rp_INT_ra_div0_5 \rp_INT_ra_spr0_4 \rp_INT_ra_logical0_3 \rp_INT_ra_trap0_2 \rp_INT_ra_cr0_1 \rp_INT_ra_alu0_0 } - connect \Y $455 - end - process $group_230 - assign \int_src1__ren 1'0 - assign \int_src1__ren $455 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:240" - wire width 1 \rdflag_INT_rb_0 - process $group_231 - assign \rdflag_INT_rb_0 1'0 - assign \rdflag_INT_rb_0 \core_reg2_ok - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:264" - wire width 1 \pick_INT_rb_alu0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" - wire width 1 $457 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" - cell $and $458 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \fus_cu_rd__rel_o [1] - connect \B \fu_enable [0] - connect \Y $457 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" - wire width 1 $459 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" - cell $and $460 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $457 - connect \B \rdflag_INT_rb_0 - connect \Y $459 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" - wire width 1 $461 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" - cell $not $462 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \dp_INT_rb_alu0_0 - connect \Y $461 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" - wire width 1 $463 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" - cell $and $464 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $459 - connect \B $461 - connect \Y $463 - end - process $group_232 - assign \pick_INT_rb_alu0_0 1'0 - assign \pick_INT_rb_alu0_0 $463 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:264" - wire width 1 \pick_INT_rb_cr0_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:264" - wire width 1 \pick_INT_rb_trap0_2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:264" - wire width 1 \pick_INT_rb_logical0_3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:264" - wire width 1 \pick_INT_rb_div0_4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:264" - wire width 1 \pick_INT_rb_mul0_5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:264" - wire width 1 \pick_INT_rb_shiftrot0_6 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:264" - wire width 1 \pick_INT_rb_ldst0_7 - process $group_233 - assign \rdpick_INT_rb_i 8'00000000 - assign \rdpick_INT_rb_i [0] \pick_INT_rb_alu0_0 - assign \rdpick_INT_rb_i [1] \pick_INT_rb_cr0_1 - assign \rdpick_INT_rb_i [2] \pick_INT_rb_trap0_2 - assign \rdpick_INT_rb_i [3] \pick_INT_rb_logical0_3 - assign \rdpick_INT_rb_i [4] \pick_INT_rb_div0_4 - assign \rdpick_INT_rb_i [5] \pick_INT_rb_mul0_5 - assign \rdpick_INT_rb_i [6] \pick_INT_rb_shiftrot0_6 - assign \rdpick_INT_rb_i [7] \pick_INT_rb_ldst0_7 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:265" - wire width 1 \rp_INT_rb_alu0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" - wire width 1 $465 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" - cell $and $466 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \rdpick_INT_rb_o [0] - connect \B \rdpick_INT_rb_en_o - connect \Y $465 - end - process $group_234 - assign \rp_INT_rb_alu0_0 1'0 - assign \rp_INT_rb_alu0_0 $465 - sync init - end - process $group_235 - assign \dp_INT_rb_alu0_0$next \dp_INT_rb_alu0_0 - assign \dp_INT_rb_alu0_0$next \rp_INT_rb_alu0_0 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \dp_INT_rb_alu0_0$next 1'0 - end - sync init - update \dp_INT_rb_alu0_0 1'0 - sync posedge \coresync_clk - update \dp_INT_rb_alu0_0 \dp_INT_rb_alu0_0$next - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:263" - wire width 5 \addr_en_INT_rb_alu0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" - wire width 5 $467 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" - cell $mux $468 - parameter \WIDTH 5 - connect \A 5'00000 - connect \B \core_reg2 - connect \S \rp_INT_rb_alu0_0 - connect \Y $467 - end - process $group_236 - assign \addr_en_INT_rb_alu0_0 5'00000 - assign \addr_en_INT_rb_alu0_0 $467 - sync init - end - process $group_237 - assign \fus_src2_i 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" - switch { \dp_INT_rb_alu0_0 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" - case 1'1 - assign \fus_src2_i \int_src2__data_o - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" - wire width 1 $469 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" - cell $and $470 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \fus_cu_rd__rel_o$31 [1] - connect \B \fu_enable [1] - connect \Y $469 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" - wire width 1 $471 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" - cell $and $472 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $469 - connect \B \rdflag_INT_rb_0 - connect \Y $471 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" - wire width 1 $473 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" - cell $not $474 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \dp_INT_rb_cr0_1 - connect \Y $473 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" - wire width 1 $475 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" - cell $and $476 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $471 - connect \B $473 - connect \Y $475 - end - process $group_238 - assign \pick_INT_rb_cr0_1 1'0 - assign \pick_INT_rb_cr0_1 $475 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:265" - wire width 1 \rp_INT_rb_cr0_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" - wire width 1 $477 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" - cell $and $478 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \rdpick_INT_rb_o [1] - connect \B \rdpick_INT_rb_en_o - connect \Y $477 - end - process $group_239 - assign \rp_INT_rb_cr0_1 1'0 - assign \rp_INT_rb_cr0_1 $477 - sync init - end - process $group_240 - assign \dp_INT_rb_cr0_1$next \dp_INT_rb_cr0_1 - assign \dp_INT_rb_cr0_1$next \rp_INT_rb_cr0_1 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \dp_INT_rb_cr0_1$next 1'0 - end - sync init - update \dp_INT_rb_cr0_1 1'0 - sync posedge \coresync_clk - update \dp_INT_rb_cr0_1 \dp_INT_rb_cr0_1$next - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:263" - wire width 5 \addr_en_INT_rb_cr0_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" - wire width 5 $479 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" - cell $mux $480 - parameter \WIDTH 5 - connect \A 5'00000 - connect \B \core_reg2 - connect \S \rp_INT_rb_cr0_1 - connect \Y $479 - end - process $group_241 - assign \addr_en_INT_rb_cr0_1 5'00000 - assign \addr_en_INT_rb_cr0_1 $479 - sync init - end - process $group_242 - assign \fus_src2_i$55 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" - switch { \dp_INT_rb_cr0_1 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" - case 1'1 - assign \fus_src2_i$55 \int_src2__data_o - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" - wire width 1 $481 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" - cell $and $482 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \fus_cu_rd__rel_o$34 [1] - connect \B \fu_enable [3] - connect \Y $481 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" - wire width 1 $483 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" - cell $and $484 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $481 - connect \B \rdflag_INT_rb_0 - connect \Y $483 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" - wire width 1 $485 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" - cell $not $486 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \dp_INT_rb_trap0_2 - connect \Y $485 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" - wire width 1 $487 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" - cell $and $488 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $483 - connect \B $485 - connect \Y $487 - end - process $group_243 - assign \pick_INT_rb_trap0_2 1'0 - assign \pick_INT_rb_trap0_2 $487 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:265" - wire width 1 \rp_INT_rb_trap0_2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" - wire width 1 $489 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" - cell $and $490 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \rdpick_INT_rb_o [2] - connect \B \rdpick_INT_rb_en_o - connect \Y $489 - end - process $group_244 - assign \rp_INT_rb_trap0_2 1'0 - assign \rp_INT_rb_trap0_2 $489 - sync init - end - process $group_245 - assign \dp_INT_rb_trap0_2$next \dp_INT_rb_trap0_2 - assign \dp_INT_rb_trap0_2$next \rp_INT_rb_trap0_2 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \dp_INT_rb_trap0_2$next 1'0 - end - sync init - update \dp_INT_rb_trap0_2 1'0 - sync posedge \coresync_clk - update \dp_INT_rb_trap0_2 \dp_INT_rb_trap0_2$next - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:263" - wire width 5 \addr_en_INT_rb_trap0_2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" - wire width 5 $491 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" - cell $mux $492 - parameter \WIDTH 5 - connect \A 5'00000 - connect \B \core_reg2 - connect \S \rp_INT_rb_trap0_2 - connect \Y $491 - end - process $group_246 - assign \addr_en_INT_rb_trap0_2 5'00000 - assign \addr_en_INT_rb_trap0_2 $491 - sync init - end - process $group_247 - assign \fus_src2_i$56 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" - switch { \dp_INT_rb_trap0_2 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" - case 1'1 - assign \fus_src2_i$56 \int_src2__data_o - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" - wire width 1 $493 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" - cell $and $494 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \fus_cu_rd__rel_o$37 [1] - connect \B \fu_enable [4] - connect \Y $493 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" - wire width 1 $495 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" - cell $and $496 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $493 - connect \B \rdflag_INT_rb_0 - connect \Y $495 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" - wire width 1 $497 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" - cell $not $498 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \dp_INT_rb_logical0_3 - connect \Y $497 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" - wire width 1 $499 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" - cell $and $500 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $495 - connect \B $497 - connect \Y $499 - end - process $group_248 - assign \pick_INT_rb_logical0_3 1'0 - assign \pick_INT_rb_logical0_3 $499 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:265" - wire width 1 \rp_INT_rb_logical0_3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" - wire width 1 $501 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" - cell $and $502 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \rdpick_INT_rb_o [3] - connect \B \rdpick_INT_rb_en_o - connect \Y $501 - end - process $group_249 - assign \rp_INT_rb_logical0_3 1'0 - assign \rp_INT_rb_logical0_3 $501 - sync init - end - process $group_250 - assign \dp_INT_rb_logical0_3$next \dp_INT_rb_logical0_3 - assign \dp_INT_rb_logical0_3$next \rp_INT_rb_logical0_3 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \dp_INT_rb_logical0_3$next 1'0 - end - sync init - update \dp_INT_rb_logical0_3 1'0 - sync posedge \coresync_clk - update \dp_INT_rb_logical0_3 \dp_INT_rb_logical0_3$next - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:263" - wire width 5 \addr_en_INT_rb_logical0_3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" - wire width 5 $503 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" - cell $mux $504 - parameter \WIDTH 5 - connect \A 5'00000 - connect \B \core_reg2 - connect \S \rp_INT_rb_logical0_3 - connect \Y $503 - end - process $group_251 - assign \addr_en_INT_rb_logical0_3 5'00000 - assign \addr_en_INT_rb_logical0_3 $503 - sync init - end - process $group_252 - assign \fus_src2_i$57 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" - switch { \dp_INT_rb_logical0_3 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" - case 1'1 - assign \fus_src2_i$57 \int_src2__data_o - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" - wire width 1 $505 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" - cell $and $506 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \fus_cu_rd__rel_o$43 [1] - connect \B \fu_enable [6] - connect \Y $505 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" - wire width 1 $507 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" - cell $and $508 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $505 - connect \B \rdflag_INT_rb_0 - connect \Y $507 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" - wire width 1 $509 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" - cell $not $510 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \dp_INT_rb_div0_4 - connect \Y $509 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" - wire width 1 $511 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" - cell $and $512 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $507 - connect \B $509 - connect \Y $511 - end - process $group_253 - assign \pick_INT_rb_div0_4 1'0 - assign \pick_INT_rb_div0_4 $511 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:265" - wire width 1 \rp_INT_rb_div0_4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" - wire width 1 $513 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" - cell $and $514 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \rdpick_INT_rb_o [4] - connect \B \rdpick_INT_rb_en_o - connect \Y $513 - end - process $group_254 - assign \rp_INT_rb_div0_4 1'0 - assign \rp_INT_rb_div0_4 $513 - sync init - end - process $group_255 - assign \dp_INT_rb_div0_4$next \dp_INT_rb_div0_4 - assign \dp_INT_rb_div0_4$next \rp_INT_rb_div0_4 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \dp_INT_rb_div0_4$next 1'0 - end - sync init - update \dp_INT_rb_div0_4 1'0 - sync posedge \coresync_clk - update \dp_INT_rb_div0_4 \dp_INT_rb_div0_4$next - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:263" - wire width 5 \addr_en_INT_rb_div0_4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" - wire width 5 $515 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" - cell $mux $516 - parameter \WIDTH 5 - connect \A 5'00000 - connect \B \core_reg2 - connect \S \rp_INT_rb_div0_4 - connect \Y $515 - end - process $group_256 - assign \addr_en_INT_rb_div0_4 5'00000 - assign \addr_en_INT_rb_div0_4 $515 - sync init - end - process $group_257 - assign \fus_src2_i$58 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" - switch { \dp_INT_rb_div0_4 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" - case 1'1 - assign \fus_src2_i$58 \int_src2__data_o - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" - wire width 1 $517 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" - cell $and $518 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \fus_cu_rd__rel_o$46 [1] - connect \B \fu_enable [7] - connect \Y $517 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" - wire width 1 $519 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" - cell $and $520 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $517 - connect \B \rdflag_INT_rb_0 - connect \Y $519 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" - wire width 1 $521 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" - cell $not $522 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \dp_INT_rb_mul0_5 - connect \Y $521 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" - wire width 1 $523 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" - cell $and $524 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $519 - connect \B $521 - connect \Y $523 - end - process $group_258 - assign \pick_INT_rb_mul0_5 1'0 - assign \pick_INT_rb_mul0_5 $523 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:265" - wire width 1 \rp_INT_rb_mul0_5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" - wire width 1 $525 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" - cell $and $526 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \rdpick_INT_rb_o [5] - connect \B \rdpick_INT_rb_en_o - connect \Y $525 - end - process $group_259 - assign \rp_INT_rb_mul0_5 1'0 - assign \rp_INT_rb_mul0_5 $525 - sync init - end - process $group_260 - assign \dp_INT_rb_mul0_5$next \dp_INT_rb_mul0_5 - assign \dp_INT_rb_mul0_5$next \rp_INT_rb_mul0_5 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \dp_INT_rb_mul0_5$next 1'0 - end - sync init - update \dp_INT_rb_mul0_5 1'0 - sync posedge \coresync_clk - update \dp_INT_rb_mul0_5 \dp_INT_rb_mul0_5$next - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:263" - wire width 5 \addr_en_INT_rb_mul0_5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" - wire width 5 $527 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" - cell $mux $528 - parameter \WIDTH 5 - connect \A 5'00000 - connect \B \core_reg2 - connect \S \rp_INT_rb_mul0_5 - connect \Y $527 - end - process $group_261 - assign \addr_en_INT_rb_mul0_5 5'00000 - assign \addr_en_INT_rb_mul0_5 $527 - sync init - end - process $group_262 - assign \fus_src2_i$59 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" - switch { \dp_INT_rb_mul0_5 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" - case 1'1 - assign \fus_src2_i$59 \int_src2__data_o - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" - wire width 1 $529 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" - cell $and $530 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \fus_cu_rd__rel_o$49 [1] - connect \B \fu_enable [8] - connect \Y $529 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" - wire width 1 $531 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" - cell $and $532 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $529 - connect \B \rdflag_INT_rb_0 - connect \Y $531 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" - wire width 1 $533 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" - cell $not $534 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \dp_INT_rb_shiftrot0_6 - connect \Y $533 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" - wire width 1 $535 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" - cell $and $536 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $531 - connect \B $533 - connect \Y $535 - end - process $group_263 - assign \pick_INT_rb_shiftrot0_6 1'0 - assign \pick_INT_rb_shiftrot0_6 $535 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:265" - wire width 1 \rp_INT_rb_shiftrot0_6 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" - wire width 1 $537 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" - cell $and $538 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \rdpick_INT_rb_o [6] - connect \B \rdpick_INT_rb_en_o - connect \Y $537 - end - process $group_264 - assign \rp_INT_rb_shiftrot0_6 1'0 - assign \rp_INT_rb_shiftrot0_6 $537 - sync init - end - process $group_265 - assign \dp_INT_rb_shiftrot0_6$next \dp_INT_rb_shiftrot0_6 - assign \dp_INT_rb_shiftrot0_6$next \rp_INT_rb_shiftrot0_6 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \dp_INT_rb_shiftrot0_6$next 1'0 - end - sync init - update \dp_INT_rb_shiftrot0_6 1'0 - sync posedge \coresync_clk - update \dp_INT_rb_shiftrot0_6 \dp_INT_rb_shiftrot0_6$next - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:263" - wire width 5 \addr_en_INT_rb_shiftrot0_6 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" - wire width 5 $539 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" - cell $mux $540 - parameter \WIDTH 5 - connect \A 5'00000 - connect \B \core_reg2 - connect \S \rp_INT_rb_shiftrot0_6 - connect \Y $539 - end - process $group_266 - assign \addr_en_INT_rb_shiftrot0_6 5'00000 - assign \addr_en_INT_rb_shiftrot0_6 $539 - sync init - end - process $group_267 - assign \fus_src2_i$60 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" - switch { \dp_INT_rb_shiftrot0_6 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" - case 1'1 - assign \fus_src2_i$60 \int_src2__data_o - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" - wire width 1 $541 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" - cell $and $542 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \fus_cu_rd__rel_o$52 [1] - connect \B \fu_enable [9] - connect \Y $541 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" - wire width 1 $543 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" - cell $and $544 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $541 - connect \B \rdflag_INT_rb_0 - connect \Y $543 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" - wire width 1 $545 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" - cell $not $546 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \dp_INT_rb_ldst0_7 - connect \Y $545 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" - wire width 1 $547 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" - cell $and $548 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $543 - connect \B $545 - connect \Y $547 - end - process $group_268 - assign \pick_INT_rb_ldst0_7 1'0 - assign \pick_INT_rb_ldst0_7 $547 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:265" - wire width 1 \rp_INT_rb_ldst0_7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" - wire width 1 $549 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" - cell $and $550 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \rdpick_INT_rb_o [7] - connect \B \rdpick_INT_rb_en_o - connect \Y $549 - end - process $group_269 - assign \rp_INT_rb_ldst0_7 1'0 - assign \rp_INT_rb_ldst0_7 $549 - sync init - end - process $group_270 - assign \dp_INT_rb_ldst0_7$next \dp_INT_rb_ldst0_7 - assign \dp_INT_rb_ldst0_7$next \rp_INT_rb_ldst0_7 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \dp_INT_rb_ldst0_7$next 1'0 - end - sync init - update \dp_INT_rb_ldst0_7 1'0 - sync posedge \coresync_clk - update \dp_INT_rb_ldst0_7 \dp_INT_rb_ldst0_7$next - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:263" - wire width 5 \addr_en_INT_rb_ldst0_7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" - wire width 5 $551 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" - cell $mux $552 - parameter \WIDTH 5 - connect \A 5'00000 - connect \B \core_reg2 - connect \S \rp_INT_rb_ldst0_7 - connect \Y $551 - end - process $group_271 - assign \addr_en_INT_rb_ldst0_7 5'00000 - assign \addr_en_INT_rb_ldst0_7 $551 - sync init - end - process $group_272 - assign \fus_src2_i$61 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" - switch { \dp_INT_rb_ldst0_7 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" - case 1'1 - assign \fus_src2_i$61 \int_src2__data_o - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - wire width 5 $553 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $or $554 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 5 - connect \A \addr_en_INT_rb_alu0_0 - connect \B \addr_en_INT_rb_cr0_1 - connect \Y $553 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - wire width 5 $555 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $or $556 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 5 - connect \A \addr_en_INT_rb_trap0_2 - connect \B \addr_en_INT_rb_logical0_3 - connect \Y $555 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - wire width 5 $557 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - cell $or $558 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 5 - connect \A $553 - connect \B $555 - connect \Y $557 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - wire width 5 $559 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $or $560 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 5 - connect \A \addr_en_INT_rb_div0_4 - connect \B \addr_en_INT_rb_mul0_5 - connect \Y $559 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - wire width 5 $561 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $or $562 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 5 - connect \A \addr_en_INT_rb_shiftrot0_6 - connect \B \addr_en_INT_rb_ldst0_7 - connect \Y $561 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - wire width 5 $563 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - cell $or $564 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 5 - connect \A $559 - connect \B $561 - connect \Y $563 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - wire width 5 $565 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - cell $or $566 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 5 - connect \A $557 - connect \B $563 - connect \Y $565 - end - process $group_273 - assign \int_src2__addr 5'00000 - assign \int_src2__addr $565 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:304" - wire width 1 $567 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:304" - cell $reduce_bool $568 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A { \rp_INT_rb_ldst0_7 \rp_INT_rb_shiftrot0_6 \rp_INT_rb_mul0_5 \rp_INT_rb_div0_4 \rp_INT_rb_logical0_3 \rp_INT_rb_trap0_2 \rp_INT_rb_cr0_1 \rp_INT_rb_alu0_0 } - connect \Y $567 - end - process $group_274 - assign \int_src2__ren 1'0 - assign \int_src2__ren $567 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:240" - wire width 1 \rdflag_INT_rc_0 - process $group_275 - assign \rdflag_INT_rc_0 1'0 - assign \rdflag_INT_rc_0 \core_reg3_ok - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:264" - wire width 1 \pick_INT_rc_shiftrot0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" - wire width 1 $569 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" - cell $and $570 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \fus_cu_rd__rel_o$49 [2] - connect \B \fu_enable [8] - connect \Y $569 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" - wire width 1 $571 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" - cell $and $572 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $569 - connect \B \rdflag_INT_rc_0 - connect \Y $571 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" - wire width 1 $573 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" - cell $not $574 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \dp_INT_rc_shiftrot0_0 - connect \Y $573 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" - wire width 1 $575 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" - cell $and $576 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $571 - connect \B $573 - connect \Y $575 - end - process $group_276 - assign \pick_INT_rc_shiftrot0_0 1'0 - assign \pick_INT_rc_shiftrot0_0 $575 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:264" - wire width 1 \pick_INT_rc_ldst0_1 - process $group_277 - assign \rdpick_INT_rc_i 2'00 - assign \rdpick_INT_rc_i [0] \pick_INT_rc_shiftrot0_0 - assign \rdpick_INT_rc_i [1] \pick_INT_rc_ldst0_1 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:265" - wire width 1 \rp_INT_rc_shiftrot0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" - wire width 1 $577 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" - cell $and $578 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \rdpick_INT_rc_o [0] - connect \B \rdpick_INT_rc_en_o - connect \Y $577 - end - process $group_278 - assign \rp_INT_rc_shiftrot0_0 1'0 - assign \rp_INT_rc_shiftrot0_0 $577 - sync init - end - process $group_279 - assign \dp_INT_rc_shiftrot0_0$next \dp_INT_rc_shiftrot0_0 - assign \dp_INT_rc_shiftrot0_0$next \rp_INT_rc_shiftrot0_0 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \dp_INT_rc_shiftrot0_0$next 1'0 - end - sync init - update \dp_INT_rc_shiftrot0_0 1'0 - sync posedge \coresync_clk - update \dp_INT_rc_shiftrot0_0 \dp_INT_rc_shiftrot0_0$next - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:263" - wire width 5 \addr_en_INT_rc_shiftrot0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" - wire width 5 $579 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" - cell $mux $580 - parameter \WIDTH 5 - connect \A 5'00000 - connect \B \core_reg3 - connect \S \rp_INT_rc_shiftrot0_0 - connect \Y $579 - end - process $group_280 - assign \addr_en_INT_rc_shiftrot0_0 5'00000 - assign \addr_en_INT_rc_shiftrot0_0 $579 - sync init - end - process $group_281 - assign \fus_src3_i 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" - switch { \dp_INT_rc_shiftrot0_0 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" - case 1'1 - assign \fus_src3_i \int_src3__data_o - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" - wire width 1 $581 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" - cell $and $582 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \fus_cu_rd__rel_o$52 [2] - connect \B \fu_enable [9] - connect \Y $581 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" - wire width 1 $583 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" - cell $and $584 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $581 - connect \B \rdflag_INT_rc_0 - connect \Y $583 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" - wire width 1 $585 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" - cell $not $586 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \dp_INT_rc_ldst0_1 - connect \Y $585 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" - wire width 1 $587 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" - cell $and $588 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $583 - connect \B $585 - connect \Y $587 - end - process $group_282 - assign \pick_INT_rc_ldst0_1 1'0 - assign \pick_INT_rc_ldst0_1 $587 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:265" - wire width 1 \rp_INT_rc_ldst0_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" - wire width 1 $589 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" - cell $and $590 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \rdpick_INT_rc_o [1] - connect \B \rdpick_INT_rc_en_o - connect \Y $589 - end - process $group_283 - assign \rp_INT_rc_ldst0_1 1'0 - assign \rp_INT_rc_ldst0_1 $589 - sync init - end - process $group_284 - assign \dp_INT_rc_ldst0_1$next \dp_INT_rc_ldst0_1 - assign \dp_INT_rc_ldst0_1$next \rp_INT_rc_ldst0_1 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \dp_INT_rc_ldst0_1$next 1'0 - end - sync init - update \dp_INT_rc_ldst0_1 1'0 - sync posedge \coresync_clk - update \dp_INT_rc_ldst0_1 \dp_INT_rc_ldst0_1$next - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:263" - wire width 5 \addr_en_INT_rc_ldst0_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" - wire width 5 $591 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" - cell $mux $592 - parameter \WIDTH 5 - connect \A 5'00000 - connect \B \core_reg3 - connect \S \rp_INT_rc_ldst0_1 - connect \Y $591 - end - process $group_285 - assign \addr_en_INT_rc_ldst0_1 5'00000 - assign \addr_en_INT_rc_ldst0_1 $591 - sync init - end - process $group_286 - assign \fus_src3_i$62 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" - switch { \dp_INT_rc_ldst0_1 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" - case 1'1 - assign \fus_src3_i$62 \int_src3__data_o - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - wire width 5 $593 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $or $594 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 5 - connect \A \addr_en_INT_rc_shiftrot0_0 - connect \B \addr_en_INT_rc_ldst0_1 - connect \Y $593 - end - process $group_287 - assign \int_src3__addr 5'00000 - assign \int_src3__addr $593 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:304" - wire width 1 $595 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:304" - cell $reduce_bool $596 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A { \rp_INT_rc_ldst0_1 \rp_INT_rc_shiftrot0_0 } - connect \Y $595 - end - process $group_288 - assign \int_src3__ren 1'0 - assign \int_src3__ren $595 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:240" - wire width 1 \rdflag_XER_xer_so_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" - wire width 1 $597 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" - cell $and $598 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \core_core_oe - connect \B \core_core_oe_ok - connect \Y $597 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" - wire width 3 $599 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" - cell $and $600 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 3 - connect \A \core_xer_in - connect \B 1'1 - connect \Y $599 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" - wire width 1 $601 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" - cell $eq $602 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $599 - connect \B 1'1 - connect \Y $601 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" - wire width 1 $603 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:80" - cell $or $604 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $597 - connect \B $601 - connect \Y $603 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81" - wire width 1 $605 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81" - cell $and $606 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \core_core_rc - connect \B \core_core_rc_ok - connect \Y $605 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81" - wire width 1 $607 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:81" - cell $or $608 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $603 - connect \B $605 - connect \Y $607 - end - process $group_289 - assign \rdflag_XER_xer_so_0 1'0 - assign \rdflag_XER_xer_so_0 $607 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:264" - wire width 1 \pick_XER_xer_so_alu0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" - wire width 1 $609 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" - cell $and $610 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \fus_cu_rd__rel_o [2] - connect \B \fu_enable [0] - connect \Y $609 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" - wire width 1 $611 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" - cell $and $612 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $609 - connect \B \rdflag_XER_xer_so_0 - connect \Y $611 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" - wire width 1 $613 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" - cell $not $614 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \dp_XER_xer_so_alu0_0 - connect \Y $613 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" - wire width 1 $615 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" - cell $and $616 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $611 - connect \B $613 - connect \Y $615 - end - process $group_290 - assign \pick_XER_xer_so_alu0_0 1'0 - assign \pick_XER_xer_so_alu0_0 $615 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:264" - wire width 1 \pick_XER_xer_so_logical0_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:264" - wire width 1 \pick_XER_xer_so_spr0_2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:264" - wire width 1 \pick_XER_xer_so_div0_3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:264" - wire width 1 \pick_XER_xer_so_mul0_4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:264" - wire width 1 \pick_XER_xer_so_shiftrot0_5 - process $group_291 - assign \rdpick_XER_xer_so_i 6'000000 - assign \rdpick_XER_xer_so_i [0] \pick_XER_xer_so_alu0_0 - assign \rdpick_XER_xer_so_i [1] \pick_XER_xer_so_logical0_1 - assign \rdpick_XER_xer_so_i [2] \pick_XER_xer_so_spr0_2 - assign \rdpick_XER_xer_so_i [3] \pick_XER_xer_so_div0_3 - assign \rdpick_XER_xer_so_i [4] \pick_XER_xer_so_mul0_4 - assign \rdpick_XER_xer_so_i [5] \pick_XER_xer_so_shiftrot0_5 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:265" - wire width 1 \rp_XER_xer_so_alu0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" - wire width 1 $617 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" - cell $and $618 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \rdpick_XER_xer_so_o [0] - connect \B \rdpick_XER_xer_so_en_o - connect \Y $617 - end - process $group_292 - assign \rp_XER_xer_so_alu0_0 1'0 - assign \rp_XER_xer_so_alu0_0 $617 - sync init - end - process $group_293 - assign \dp_XER_xer_so_alu0_0$next \dp_XER_xer_so_alu0_0 - assign \dp_XER_xer_so_alu0_0$next \rp_XER_xer_so_alu0_0 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \dp_XER_xer_so_alu0_0$next 1'0 - end - sync init - update \dp_XER_xer_so_alu0_0 1'0 - sync posedge \coresync_clk - update \dp_XER_xer_so_alu0_0 \dp_XER_xer_so_alu0_0$next - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:263" - wire width 1 \addr_en_XER_xer_so_alu0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" - wire width 1 $619 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" - cell $mux $620 - parameter \WIDTH 1 - connect \A 1'0 - connect \B 1'1 - connect \S \rp_XER_xer_so_alu0_0 - connect \Y $619 - end - process $group_294 - assign \addr_en_XER_xer_so_alu0_0 1'0 - assign \addr_en_XER_xer_so_alu0_0 $619 - sync init - end - process $group_295 - assign \fus_src3_i$63 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" - switch { \dp_XER_xer_so_alu0_0 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" - case 1'1 - assign \fus_src3_i$63 \xer_src1__data_o [0] - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" - wire width 1 $621 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" - cell $and $622 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \fus_cu_rd__rel_o$37 [2] - connect \B \fu_enable [4] - connect \Y $621 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" - wire width 1 $623 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" - cell $and $624 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $621 - connect \B \rdflag_XER_xer_so_0 - connect \Y $623 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" - wire width 1 $625 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" - cell $not $626 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \dp_XER_xer_so_logical0_1 - connect \Y $625 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" - wire width 1 $627 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" - cell $and $628 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $623 - connect \B $625 - connect \Y $627 - end - process $group_296 - assign \pick_XER_xer_so_logical0_1 1'0 - assign \pick_XER_xer_so_logical0_1 $627 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:265" - wire width 1 \rp_XER_xer_so_logical0_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" - wire width 1 $629 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" - cell $and $630 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \rdpick_XER_xer_so_o [1] - connect \B \rdpick_XER_xer_so_en_o - connect \Y $629 - end - process $group_297 - assign \rp_XER_xer_so_logical0_1 1'0 - assign \rp_XER_xer_so_logical0_1 $629 - sync init - end - process $group_298 - assign \dp_XER_xer_so_logical0_1$next \dp_XER_xer_so_logical0_1 - assign \dp_XER_xer_so_logical0_1$next \rp_XER_xer_so_logical0_1 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \dp_XER_xer_so_logical0_1$next 1'0 - end - sync init - update \dp_XER_xer_so_logical0_1 1'0 - sync posedge \coresync_clk - update \dp_XER_xer_so_logical0_1 \dp_XER_xer_so_logical0_1$next - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:263" - wire width 1 \addr_en_XER_xer_so_logical0_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" - wire width 1 $631 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" - cell $mux $632 - parameter \WIDTH 1 - connect \A 1'0 - connect \B 1'1 - connect \S \rp_XER_xer_so_logical0_1 - connect \Y $631 - end - process $group_299 - assign \addr_en_XER_xer_so_logical0_1 1'0 - assign \addr_en_XER_xer_so_logical0_1 $631 - sync init - end - process $group_300 - assign \fus_src3_i$64 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" - switch { \dp_XER_xer_so_logical0_1 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" - case 1'1 - assign \fus_src3_i$64 \xer_src1__data_o [0] - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" - wire width 1 $633 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" - cell $and $634 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \fus_cu_rd__rel_o$40 [3] - connect \B \fu_enable [5] - connect \Y $633 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" - wire width 1 $635 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" - cell $and $636 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $633 - connect \B \rdflag_XER_xer_so_0 - connect \Y $635 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" - wire width 1 $637 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" - cell $not $638 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \dp_XER_xer_so_spr0_2 - connect \Y $637 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" - wire width 1 $639 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" - cell $and $640 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $635 - connect \B $637 - connect \Y $639 - end - process $group_301 - assign \pick_XER_xer_so_spr0_2 1'0 - assign \pick_XER_xer_so_spr0_2 $639 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:265" - wire width 1 \rp_XER_xer_so_spr0_2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" - wire width 1 $641 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" - cell $and $642 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \rdpick_XER_xer_so_o [2] - connect \B \rdpick_XER_xer_so_en_o - connect \Y $641 - end - process $group_302 - assign \rp_XER_xer_so_spr0_2 1'0 - assign \rp_XER_xer_so_spr0_2 $641 - sync init - end - process $group_303 - assign \dp_XER_xer_so_spr0_2$next \dp_XER_xer_so_spr0_2 - assign \dp_XER_xer_so_spr0_2$next \rp_XER_xer_so_spr0_2 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \dp_XER_xer_so_spr0_2$next 1'0 - end - sync init - update \dp_XER_xer_so_spr0_2 1'0 - sync posedge \coresync_clk - update \dp_XER_xer_so_spr0_2 \dp_XER_xer_so_spr0_2$next - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:263" - wire width 1 \addr_en_XER_xer_so_spr0_2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" - wire width 1 $643 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" - cell $mux $644 - parameter \WIDTH 1 - connect \A 1'0 - connect \B 1'1 - connect \S \rp_XER_xer_so_spr0_2 - connect \Y $643 - end - process $group_304 - assign \addr_en_XER_xer_so_spr0_2 1'0 - assign \addr_en_XER_xer_so_spr0_2 $643 - sync init - end - process $group_305 - assign \fus_src4_i 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" - switch { \dp_XER_xer_so_spr0_2 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" - case 1'1 - assign \fus_src4_i \xer_src1__data_o [0] - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" - wire width 1 $645 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" - cell $and $646 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \fus_cu_rd__rel_o$43 [2] - connect \B \fu_enable [6] - connect \Y $645 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" - wire width 1 $647 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" - cell $and $648 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $645 - connect \B \rdflag_XER_xer_so_0 - connect \Y $647 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" - wire width 1 $649 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" - cell $not $650 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \dp_XER_xer_so_div0_3 - connect \Y $649 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" - wire width 1 $651 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" - cell $and $652 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $647 - connect \B $649 - connect \Y $651 - end - process $group_306 - assign \pick_XER_xer_so_div0_3 1'0 - assign \pick_XER_xer_so_div0_3 $651 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:265" - wire width 1 \rp_XER_xer_so_div0_3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" - wire width 1 $653 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" - cell $and $654 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \rdpick_XER_xer_so_o [3] - connect \B \rdpick_XER_xer_so_en_o - connect \Y $653 - end - process $group_307 - assign \rp_XER_xer_so_div0_3 1'0 - assign \rp_XER_xer_so_div0_3 $653 - sync init - end - process $group_308 - assign \dp_XER_xer_so_div0_3$next \dp_XER_xer_so_div0_3 - assign \dp_XER_xer_so_div0_3$next \rp_XER_xer_so_div0_3 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \dp_XER_xer_so_div0_3$next 1'0 - end - sync init - update \dp_XER_xer_so_div0_3 1'0 - sync posedge \coresync_clk - update \dp_XER_xer_so_div0_3 \dp_XER_xer_so_div0_3$next - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:263" - wire width 1 \addr_en_XER_xer_so_div0_3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" - wire width 1 $655 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" - cell $mux $656 - parameter \WIDTH 1 - connect \A 1'0 - connect \B 1'1 - connect \S \rp_XER_xer_so_div0_3 - connect \Y $655 - end - process $group_309 - assign \addr_en_XER_xer_so_div0_3 1'0 - assign \addr_en_XER_xer_so_div0_3 $655 - sync init - end - process $group_310 - assign \fus_src3_i$65 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" - switch { \dp_XER_xer_so_div0_3 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" - case 1'1 - assign \fus_src3_i$65 \xer_src1__data_o [0] - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" - wire width 1 $657 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" - cell $and $658 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \fus_cu_rd__rel_o$46 [2] - connect \B \fu_enable [7] - connect \Y $657 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" - wire width 1 $659 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" - cell $and $660 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $657 - connect \B \rdflag_XER_xer_so_0 - connect \Y $659 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" - wire width 1 $661 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" - cell $not $662 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \dp_XER_xer_so_mul0_4 - connect \Y $661 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" - wire width 1 $663 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" - cell $and $664 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $659 - connect \B $661 - connect \Y $663 - end - process $group_311 - assign \pick_XER_xer_so_mul0_4 1'0 - assign \pick_XER_xer_so_mul0_4 $663 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:265" - wire width 1 \rp_XER_xer_so_mul0_4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" - wire width 1 $665 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" - cell $and $666 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \rdpick_XER_xer_so_o [4] - connect \B \rdpick_XER_xer_so_en_o - connect \Y $665 - end - process $group_312 - assign \rp_XER_xer_so_mul0_4 1'0 - assign \rp_XER_xer_so_mul0_4 $665 - sync init - end - process $group_313 - assign \dp_XER_xer_so_mul0_4$next \dp_XER_xer_so_mul0_4 - assign \dp_XER_xer_so_mul0_4$next \rp_XER_xer_so_mul0_4 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \dp_XER_xer_so_mul0_4$next 1'0 - end - sync init - update \dp_XER_xer_so_mul0_4 1'0 - sync posedge \coresync_clk - update \dp_XER_xer_so_mul0_4 \dp_XER_xer_so_mul0_4$next - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:263" - wire width 1 \addr_en_XER_xer_so_mul0_4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" - wire width 1 $667 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" - cell $mux $668 - parameter \WIDTH 1 - connect \A 1'0 - connect \B 1'1 - connect \S \rp_XER_xer_so_mul0_4 - connect \Y $667 - end - process $group_314 - assign \addr_en_XER_xer_so_mul0_4 1'0 - assign \addr_en_XER_xer_so_mul0_4 $667 - sync init - end - process $group_315 - assign \fus_src3_i$66 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" - switch { \dp_XER_xer_so_mul0_4 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" - case 1'1 - assign \fus_src3_i$66 \xer_src1__data_o [0] - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" - wire width 1 $669 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" - cell $and $670 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \fus_cu_rd__rel_o$49 [3] - connect \B \fu_enable [8] - connect \Y $669 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" - wire width 1 $671 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" - cell $and $672 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $669 - connect \B \rdflag_XER_xer_so_0 - connect \Y $671 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" - wire width 1 $673 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" - cell $not $674 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \dp_XER_xer_so_shiftrot0_5 - connect \Y $673 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" - wire width 1 $675 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" - cell $and $676 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $671 - connect \B $673 - connect \Y $675 - end - process $group_316 - assign \pick_XER_xer_so_shiftrot0_5 1'0 - assign \pick_XER_xer_so_shiftrot0_5 $675 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:265" - wire width 1 \rp_XER_xer_so_shiftrot0_5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" - wire width 1 $677 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" - cell $and $678 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \rdpick_XER_xer_so_o [5] - connect \B \rdpick_XER_xer_so_en_o - connect \Y $677 - end - process $group_317 - assign \rp_XER_xer_so_shiftrot0_5 1'0 - assign \rp_XER_xer_so_shiftrot0_5 $677 - sync init - end - process $group_318 - assign \dp_XER_xer_so_shiftrot0_5$next \dp_XER_xer_so_shiftrot0_5 - assign \dp_XER_xer_so_shiftrot0_5$next \rp_XER_xer_so_shiftrot0_5 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \dp_XER_xer_so_shiftrot0_5$next 1'0 - end - sync init - update \dp_XER_xer_so_shiftrot0_5 1'0 - sync posedge \coresync_clk - update \dp_XER_xer_so_shiftrot0_5 \dp_XER_xer_so_shiftrot0_5$next - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:263" - wire width 1 \addr_en_XER_xer_so_shiftrot0_5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" - wire width 1 $679 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" - cell $mux $680 - parameter \WIDTH 1 - connect \A 1'0 - connect \B 1'1 - connect \S \rp_XER_xer_so_shiftrot0_5 - connect \Y $679 - end - process $group_319 - assign \addr_en_XER_xer_so_shiftrot0_5 1'0 - assign \addr_en_XER_xer_so_shiftrot0_5 $679 - sync init - end - process $group_320 - assign \fus_src4_i$67 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" - switch { \dp_XER_xer_so_shiftrot0_5 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" - case 1'1 - assign \fus_src4_i$67 \xer_src1__data_o [0] - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - wire width 3 $681 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - wire width 1 $682 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $or $683 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \addr_en_XER_xer_so_logical0_1 - connect \B \addr_en_XER_xer_so_spr0_2 - connect \Y $682 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - wire width 1 $684 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - cell $or $685 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \addr_en_XER_xer_so_alu0_0 - connect \B $682 - connect \Y $684 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - wire width 1 $686 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $or $687 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \addr_en_XER_xer_so_mul0_4 - connect \B \addr_en_XER_xer_so_shiftrot0_5 - connect \Y $686 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - wire width 1 $688 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - cell $or $689 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \addr_en_XER_xer_so_div0_3 - connect \B $686 - connect \Y $688 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - wire width 1 $690 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - cell $or $691 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $684 - connect \B $688 - connect \Y $690 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - cell $pos $692 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 3 - connect \A $690 - connect \Y $681 - end - process $group_321 - assign \xer_src1__ren 3'000 - assign \xer_src1__ren $681 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:240" - wire width 1 \rdflag_XER_xer_ca_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:86" - wire width 1 $693 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:86" - cell $eq $694 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \core_core_input_carry - connect \B 2'10 - connect \Y $693 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:87" - wire width 3 $695 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:87" - cell $and $696 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A \core_xer_in - connect \B 3'100 - connect \Y $695 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:87" - wire width 1 $697 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:87" - cell $eq $698 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A $695 - connect \B 3'100 - connect \Y $697 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:87" - wire width 1 $699 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:87" - cell $or $700 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $693 - connect \B $697 - connect \Y $699 - end - process $group_322 - assign \rdflag_XER_xer_ca_0 1'0 - assign \rdflag_XER_xer_ca_0 $699 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:264" - wire width 1 \pick_XER_xer_ca_alu0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" - wire width 1 $701 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" - cell $and $702 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \fus_cu_rd__rel_o [3] - connect \B \fu_enable [0] - connect \Y $701 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" - wire width 1 $703 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" - cell $and $704 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $701 - connect \B \rdflag_XER_xer_ca_0 - connect \Y $703 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" - wire width 1 $705 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" - cell $not $706 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \dp_XER_xer_ca_alu0_0 - connect \Y $705 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" - wire width 1 $707 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" - cell $and $708 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $703 - connect \B $705 - connect \Y $707 - end - process $group_323 - assign \pick_XER_xer_ca_alu0_0 1'0 - assign \pick_XER_xer_ca_alu0_0 $707 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:264" - wire width 1 \pick_XER_xer_ca_spr0_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:264" - wire width 1 \pick_XER_xer_ca_shiftrot0_2 - process $group_324 - assign \rdpick_XER_xer_ca_i 3'000 - assign \rdpick_XER_xer_ca_i [0] \pick_XER_xer_ca_alu0_0 - assign \rdpick_XER_xer_ca_i [1] \pick_XER_xer_ca_spr0_1 - assign \rdpick_XER_xer_ca_i [2] \pick_XER_xer_ca_shiftrot0_2 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:265" - wire width 1 \rp_XER_xer_ca_alu0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" - wire width 1 $709 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" - cell $and $710 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \rdpick_XER_xer_ca_o [0] - connect \B \rdpick_XER_xer_ca_en_o - connect \Y $709 - end - process $group_325 - assign \rp_XER_xer_ca_alu0_0 1'0 - assign \rp_XER_xer_ca_alu0_0 $709 - sync init - end - process $group_326 - assign \dp_XER_xer_ca_alu0_0$next \dp_XER_xer_ca_alu0_0 - assign \dp_XER_xer_ca_alu0_0$next \rp_XER_xer_ca_alu0_0 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \dp_XER_xer_ca_alu0_0$next 1'0 - end - sync init - update \dp_XER_xer_ca_alu0_0 1'0 - sync posedge \coresync_clk - update \dp_XER_xer_ca_alu0_0 \dp_XER_xer_ca_alu0_0$next - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:263" - wire width 2 \addr_en_XER_xer_ca_alu0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" - wire width 2 $711 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" - cell $mux $712 - parameter \WIDTH 2 - connect \A 2'00 - connect \B 2'10 - connect \S \rp_XER_xer_ca_alu0_0 - connect \Y $711 - end - process $group_327 - assign \addr_en_XER_xer_ca_alu0_0 2'00 - assign \addr_en_XER_xer_ca_alu0_0 $711 - sync init - end - process $group_328 - assign \fus_src4_i$68 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" - switch { \dp_XER_xer_ca_alu0_0 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" - case 1'1 - assign \fus_src4_i$68 \xer_src2__data_o - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" - wire width 1 $713 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" - cell $and $714 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \fus_cu_rd__rel_o$40 [5] - connect \B \fu_enable [5] - connect \Y $713 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" - wire width 1 $715 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" - cell $and $716 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $713 - connect \B \rdflag_XER_xer_ca_0 - connect \Y $715 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" - wire width 1 $717 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" - cell $not $718 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \dp_XER_xer_ca_spr0_1 - connect \Y $717 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" - wire width 1 $719 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" - cell $and $720 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $715 - connect \B $717 - connect \Y $719 - end - process $group_329 - assign \pick_XER_xer_ca_spr0_1 1'0 - assign \pick_XER_xer_ca_spr0_1 $719 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:265" - wire width 1 \rp_XER_xer_ca_spr0_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" - wire width 1 $721 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" - cell $and $722 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \rdpick_XER_xer_ca_o [1] - connect \B \rdpick_XER_xer_ca_en_o - connect \Y $721 - end - process $group_330 - assign \rp_XER_xer_ca_spr0_1 1'0 - assign \rp_XER_xer_ca_spr0_1 $721 - sync init - end - process $group_331 - assign \dp_XER_xer_ca_spr0_1$next \dp_XER_xer_ca_spr0_1 - assign \dp_XER_xer_ca_spr0_1$next \rp_XER_xer_ca_spr0_1 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \dp_XER_xer_ca_spr0_1$next 1'0 - end - sync init - update \dp_XER_xer_ca_spr0_1 1'0 - sync posedge \coresync_clk - update \dp_XER_xer_ca_spr0_1 \dp_XER_xer_ca_spr0_1$next - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:263" - wire width 2 \addr_en_XER_xer_ca_spr0_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" - wire width 2 $723 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" - cell $mux $724 - parameter \WIDTH 2 - connect \A 2'00 - connect \B 2'10 - connect \S \rp_XER_xer_ca_spr0_1 - connect \Y $723 - end - process $group_332 - assign \addr_en_XER_xer_ca_spr0_1 2'00 - assign \addr_en_XER_xer_ca_spr0_1 $723 - sync init - end - process $group_333 - assign \fus_src6_i 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" - switch { \dp_XER_xer_ca_spr0_1 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" - case 1'1 - assign \fus_src6_i \xer_src2__data_o - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" - wire width 1 $725 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" - cell $and $726 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \fus_cu_rd__rel_o$49 [4] - connect \B \fu_enable [8] - connect \Y $725 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" - wire width 1 $727 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" - cell $and $728 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $725 - connect \B \rdflag_XER_xer_ca_0 - connect \Y $727 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" - wire width 1 $729 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" - cell $not $730 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \dp_XER_xer_ca_shiftrot0_2 - connect \Y $729 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" - wire width 1 $731 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" - cell $and $732 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $727 - connect \B $729 - connect \Y $731 - end - process $group_334 - assign \pick_XER_xer_ca_shiftrot0_2 1'0 - assign \pick_XER_xer_ca_shiftrot0_2 $731 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:265" - wire width 1 \rp_XER_xer_ca_shiftrot0_2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" - wire width 1 $733 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" - cell $and $734 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \rdpick_XER_xer_ca_o [2] - connect \B \rdpick_XER_xer_ca_en_o - connect \Y $733 - end - process $group_335 - assign \rp_XER_xer_ca_shiftrot0_2 1'0 - assign \rp_XER_xer_ca_shiftrot0_2 $733 - sync init - end - process $group_336 - assign \dp_XER_xer_ca_shiftrot0_2$next \dp_XER_xer_ca_shiftrot0_2 - assign \dp_XER_xer_ca_shiftrot0_2$next \rp_XER_xer_ca_shiftrot0_2 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \dp_XER_xer_ca_shiftrot0_2$next 1'0 - end - sync init - update \dp_XER_xer_ca_shiftrot0_2 1'0 - sync posedge \coresync_clk - update \dp_XER_xer_ca_shiftrot0_2 \dp_XER_xer_ca_shiftrot0_2$next - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:263" - wire width 2 \addr_en_XER_xer_ca_shiftrot0_2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" - wire width 2 $735 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" - cell $mux $736 - parameter \WIDTH 2 - connect \A 2'00 - connect \B 2'10 - connect \S \rp_XER_xer_ca_shiftrot0_2 - connect \Y $735 - end - process $group_337 - assign \addr_en_XER_xer_ca_shiftrot0_2 2'00 - assign \addr_en_XER_xer_ca_shiftrot0_2 $735 - sync init - end - process $group_338 - assign \fus_src5_i 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" - switch { \dp_XER_xer_ca_shiftrot0_2 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" - case 1'1 - assign \fus_src5_i \xer_src2__data_o - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - wire width 3 $737 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - wire width 2 $738 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $or $739 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 2 - connect \A \addr_en_XER_xer_ca_spr0_1 - connect \B \addr_en_XER_xer_ca_shiftrot0_2 - connect \Y $738 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - wire width 2 $740 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - cell $or $741 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 2 - connect \A \addr_en_XER_xer_ca_alu0_0 - connect \B $738 - connect \Y $740 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - cell $pos $742 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \Y_WIDTH 3 - connect \A $740 - connect \Y $737 - end - process $group_339 - assign \xer_src2__ren 3'000 - assign \xer_src2__ren $737 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:240" - wire width 1 \rdflag_XER_xer_ov_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:83" - wire width 1 $743 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:83" - cell $and $744 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \core_core_oe - connect \B \core_core_oe_ok - connect \Y $743 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:84" - wire width 3 $745 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:84" - cell $and $746 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 3 - connect \A \core_xer_in - connect \B 2'10 - connect \Y $745 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:84" - wire width 1 $747 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:84" - cell $eq $748 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A $745 - connect \B 2'10 - connect \Y $747 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:84" - wire width 1 $749 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:84" - cell $or $750 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $743 - connect \B $747 - connect \Y $749 - end - process $group_340 - assign \rdflag_XER_xer_ov_0 1'0 - assign \rdflag_XER_xer_ov_0 $749 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:264" - wire width 1 \pick_XER_xer_ov_spr0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" - wire width 1 $751 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" - cell $and $752 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \fus_cu_rd__rel_o$40 [4] - connect \B \fu_enable [5] - connect \Y $751 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" - wire width 1 $753 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" - cell $and $754 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $751 - connect \B \rdflag_XER_xer_ov_0 - connect \Y $753 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" - wire width 1 $755 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" - cell $not $756 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \dp_XER_xer_ov_spr0_0 - connect \Y $755 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" - wire width 1 $757 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" - cell $and $758 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $753 - connect \B $755 - connect \Y $757 - end - process $group_341 - assign \pick_XER_xer_ov_spr0_0 1'0 - assign \pick_XER_xer_ov_spr0_0 $757 - sync init - end - process $group_342 - assign \rdpick_XER_xer_ov_i 1'0 - assign \rdpick_XER_xer_ov_i \pick_XER_xer_ov_spr0_0 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:265" - wire width 1 \rp_XER_xer_ov_spr0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" - wire width 1 $759 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" - cell $and $760 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \rdpick_XER_xer_ov_o - connect \B \rdpick_XER_xer_ov_en_o - connect \Y $759 - end - process $group_343 - assign \rp_XER_xer_ov_spr0_0 1'0 - assign \rp_XER_xer_ov_spr0_0 $759 - sync init - end - process $group_344 - assign \dp_XER_xer_ov_spr0_0$next \dp_XER_xer_ov_spr0_0 - assign \dp_XER_xer_ov_spr0_0$next \rp_XER_xer_ov_spr0_0 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \dp_XER_xer_ov_spr0_0$next 1'0 - end - sync init - update \dp_XER_xer_ov_spr0_0 1'0 - sync posedge \coresync_clk - update \dp_XER_xer_ov_spr0_0 \dp_XER_xer_ov_spr0_0$next - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:263" - wire width 3 \addr_en_XER_xer_ov_spr0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" - wire width 3 $761 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" - cell $mux $762 - parameter \WIDTH 3 - connect \A 3'000 - connect \B 3'100 - connect \S \rp_XER_xer_ov_spr0_0 - connect \Y $761 - end - process $group_345 - assign \addr_en_XER_xer_ov_spr0_0 3'000 - assign \addr_en_XER_xer_ov_spr0_0 $761 - sync init - end - process $group_346 - assign \fus_src5_i$69 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" - switch { \dp_XER_xer_ov_spr0_0 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" - case 1'1 - assign \fus_src5_i$69 \xer_src3__data_o - end - sync init - end - process $group_347 - assign \xer_src3__ren 3'000 - assign \xer_src3__ren \addr_en_XER_xer_ov_spr0_0 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:240" - wire width 1 \rdflag_CR_full_cr_0 - process $group_348 - assign \rdflag_CR_full_cr_0 1'0 - assign \rdflag_CR_full_cr_0 \core_core_cr_rd_ok - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:264" - wire width 1 \pick_CR_full_cr_cr0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" - wire width 1 $763 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" - cell $and $764 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \fus_cu_rd__rel_o$31 [2] - connect \B \fu_enable [1] - connect \Y $763 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" - wire width 1 $765 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" - cell $and $766 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $763 - connect \B \rdflag_CR_full_cr_0 - connect \Y $765 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" - wire width 1 $767 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" - cell $not $768 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \dp_CR_full_cr_cr0_0 - connect \Y $767 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" - wire width 1 $769 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" - cell $and $770 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $765 - connect \B $767 - connect \Y $769 - end - process $group_349 - assign \pick_CR_full_cr_cr0_0 1'0 - assign \pick_CR_full_cr_cr0_0 $769 - sync init - end - process $group_350 - assign \rdpick_CR_full_cr_i 1'0 - assign \rdpick_CR_full_cr_i \pick_CR_full_cr_cr0_0 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:265" - wire width 1 \rp_CR_full_cr_cr0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" - wire width 1 $771 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" - cell $and $772 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \rdpick_CR_full_cr_o - connect \B \rdpick_CR_full_cr_en_o - connect \Y $771 - end - process $group_351 - assign \rp_CR_full_cr_cr0_0 1'0 - assign \rp_CR_full_cr_cr0_0 $771 - sync init - end - process $group_352 - assign \dp_CR_full_cr_cr0_0$next \dp_CR_full_cr_cr0_0 - assign \dp_CR_full_cr_cr0_0$next \rp_CR_full_cr_cr0_0 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \dp_CR_full_cr_cr0_0$next 1'0 - end - sync init - update \dp_CR_full_cr_cr0_0 1'0 - sync posedge \coresync_clk - update \dp_CR_full_cr_cr0_0 \dp_CR_full_cr_cr0_0$next - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:263" - wire width 8 \addr_en_CR_full_cr_cr0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" - wire width 8 $773 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" - cell $mux $774 - parameter \WIDTH 8 - connect \A 8'00000000 - connect \B \core_core_cr_rd - connect \S \rp_CR_full_cr_cr0_0 - connect \Y $773 - end - process $group_353 - assign \addr_en_CR_full_cr_cr0_0 8'00000000 - assign \addr_en_CR_full_cr_cr0_0 $773 - sync init - end - process $group_354 - assign \fus_src3_i$70 32'00000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" - switch { \dp_CR_full_cr_cr0_0 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" - case 1'1 - assign \fus_src3_i$70 \cr_full_rd__data_o - end - sync init - end - process $group_355 - assign \cr_full_rd__ren 8'00000000 - assign \cr_full_rd__ren \addr_en_CR_full_cr_cr0_0 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:240" - wire width 1 \rdflag_CR_cr_a_0 - process $group_356 - assign \rdflag_CR_cr_a_0 1'0 - assign \rdflag_CR_cr_a_0 \core_cr_in1_ok - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:264" - wire width 1 \pick_CR_cr_a_cr0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" - wire width 1 $775 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" - cell $and $776 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \fus_cu_rd__rel_o$31 [3] - connect \B \fu_enable [1] - connect \Y $775 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" - wire width 1 $777 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" - cell $and $778 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $775 - connect \B \rdflag_CR_cr_a_0 - connect \Y $777 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" - wire width 1 $779 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" - cell $not $780 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \dp_CR_cr_a_cr0_0 - connect \Y $779 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" - wire width 1 $781 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" - cell $and $782 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $777 - connect \B $779 - connect \Y $781 - end - process $group_357 - assign \pick_CR_cr_a_cr0_0 1'0 - assign \pick_CR_cr_a_cr0_0 $781 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:264" - wire width 1 \pick_CR_cr_a_branch0_1 - process $group_358 - assign \rdpick_CR_cr_a_i 2'00 - assign \rdpick_CR_cr_a_i [0] \pick_CR_cr_a_cr0_0 - assign \rdpick_CR_cr_a_i [1] \pick_CR_cr_a_branch0_1 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:265" - wire width 1 \rp_CR_cr_a_cr0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" - wire width 1 $783 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" - cell $and $784 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \rdpick_CR_cr_a_o [0] - connect \B \rdpick_CR_cr_a_en_o - connect \Y $783 - end - process $group_359 - assign \rp_CR_cr_a_cr0_0 1'0 - assign \rp_CR_cr_a_cr0_0 $783 - sync init - end - process $group_360 - assign \dp_CR_cr_a_cr0_0$next \dp_CR_cr_a_cr0_0 - assign \dp_CR_cr_a_cr0_0$next \rp_CR_cr_a_cr0_0 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \dp_CR_cr_a_cr0_0$next 1'0 - end - sync init - update \dp_CR_cr_a_cr0_0 1'0 - sync posedge \coresync_clk - update \dp_CR_cr_a_cr0_0 \dp_CR_cr_a_cr0_0$next - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:263" - wire width 16 \addr_en_CR_cr_a_cr0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:64" - wire width 4 $785 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:64" - cell $sub $786 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 4 - connect \A 3'111 - connect \B \core_cr_in1 - connect \Y $785 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:64" - wire width 16 $787 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:64" - cell $sshl $788 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 16 - connect \A 1'1 - connect \B $785 - connect \Y $787 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" - wire width 16 $789 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" - cell $mux $790 - parameter \WIDTH 16 - connect \A 16'0000000000000000 - connect \B $787 - connect \S \rp_CR_cr_a_cr0_0 - connect \Y $789 - end - process $group_361 - assign \addr_en_CR_cr_a_cr0_0 16'0000000000000000 - assign \addr_en_CR_cr_a_cr0_0 $789 - sync init - end - process $group_362 - assign \fus_src4_i$71 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" - switch { \dp_CR_cr_a_cr0_0 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" - case 1'1 - assign \fus_src4_i$71 \cr_src1__data_o - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" - wire width 1 $791 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" - cell $and $792 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \fus_cu_rd__rel_o$72 [2] - connect \B \fu_enable [2] - connect \Y $791 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" - wire width 1 $793 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" - cell $and $794 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $791 - connect \B \rdflag_CR_cr_a_0 - connect \Y $793 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" - wire width 1 $795 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:266" - wire width 1 \dp_CR_cr_a_branch0_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:266" - wire width 1 \dp_CR_cr_a_branch0_1$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" - cell $not $796 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \dp_CR_cr_a_branch0_1 - connect \Y $795 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" - wire width 1 $797 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" - cell $and $798 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $793 - connect \B $795 - connect \Y $797 - end - process $group_363 - assign \pick_CR_cr_a_branch0_1 1'0 - assign \pick_CR_cr_a_branch0_1 $797 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:266" - wire width 1 \dp_FAST_fast1_branch0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:266" - wire width 1 \dp_FAST_fast1_branch0_0$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:266" - wire width 1 \dp_FAST_fast2_branch0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:266" - wire width 1 \dp_FAST_fast2_branch0_0$next - process $group_364 - assign \fus_cu_rd__go_i$73 3'000 - assign \fus_cu_rd__go_i$73 [2] \dp_CR_cr_a_branch0_1 - assign \fus_cu_rd__go_i$73 [0] \dp_FAST_fast1_branch0_0 - assign \fus_cu_rd__go_i$73 [1] \dp_FAST_fast2_branch0_0 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:265" - wire width 1 \rp_CR_cr_a_branch0_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" - wire width 1 $799 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" - cell $and $800 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \rdpick_CR_cr_a_o [1] - connect \B \rdpick_CR_cr_a_en_o - connect \Y $799 - end - process $group_365 - assign \rp_CR_cr_a_branch0_1 1'0 - assign \rp_CR_cr_a_branch0_1 $799 - sync init - end - process $group_366 - assign \dp_CR_cr_a_branch0_1$next \dp_CR_cr_a_branch0_1 - assign \dp_CR_cr_a_branch0_1$next \rp_CR_cr_a_branch0_1 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \dp_CR_cr_a_branch0_1$next 1'0 - end - sync init - update \dp_CR_cr_a_branch0_1 1'0 - sync posedge \coresync_clk - update \dp_CR_cr_a_branch0_1 \dp_CR_cr_a_branch0_1$next - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:263" - wire width 16 \addr_en_CR_cr_a_branch0_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:64" - wire width 4 $801 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:64" - cell $sub $802 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 4 - connect \A 3'111 - connect \B \core_cr_in1 - connect \Y $801 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:64" - wire width 16 $803 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:64" - cell $sshl $804 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 16 - connect \A 1'1 - connect \B $801 - connect \Y $803 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" - wire width 16 $805 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" - cell $mux $806 - parameter \WIDTH 16 - connect \A 16'0000000000000000 - connect \B $803 - connect \S \rp_CR_cr_a_branch0_1 - connect \Y $805 - end - process $group_367 - assign \addr_en_CR_cr_a_branch0_1 16'0000000000000000 - assign \addr_en_CR_cr_a_branch0_1 $805 - sync init - end - process $group_368 - assign \fus_src3_i$74 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" - switch { \dp_CR_cr_a_branch0_1 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" - case 1'1 - assign \fus_src3_i$74 \cr_src1__data_o - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - wire width 16 $807 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - wire width 16 $808 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $or $809 - parameter \A_SIGNED 0 - parameter \A_WIDTH 16 - parameter \B_SIGNED 0 - parameter \B_WIDTH 16 - parameter \Y_WIDTH 16 - connect \A \addr_en_CR_cr_a_cr0_0 - connect \B \addr_en_CR_cr_a_branch0_1 - connect \Y $808 - end - connect $807 $808 - process $group_369 - assign \cr_src1__ren 8'00000000 - assign \cr_src1__ren $807 [7:0] - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:240" - wire width 1 \rdflag_CR_cr_b_0 - process $group_370 - assign \rdflag_CR_cr_b_0 1'0 - assign \rdflag_CR_cr_b_0 \core_cr_in2_ok - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:264" - wire width 1 \pick_CR_cr_b_cr0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" - wire width 1 $810 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" - cell $and $811 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \fus_cu_rd__rel_o$31 [4] - connect \B \fu_enable [1] - connect \Y $810 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" - wire width 1 $812 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" - cell $and $813 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $810 - connect \B \rdflag_CR_cr_b_0 - connect \Y $812 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" - wire width 1 $814 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" - cell $not $815 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \dp_CR_cr_b_cr0_0 - connect \Y $814 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" - wire width 1 $816 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" - cell $and $817 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $812 - connect \B $814 - connect \Y $816 - end - process $group_371 - assign \pick_CR_cr_b_cr0_0 1'0 - assign \pick_CR_cr_b_cr0_0 $816 - sync init - end - process $group_372 - assign \rdpick_CR_cr_b_i 1'0 - assign \rdpick_CR_cr_b_i \pick_CR_cr_b_cr0_0 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:265" - wire width 1 \rp_CR_cr_b_cr0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" - wire width 1 $818 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" - cell $and $819 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \rdpick_CR_cr_b_o - connect \B \rdpick_CR_cr_b_en_o - connect \Y $818 - end - process $group_373 - assign \rp_CR_cr_b_cr0_0 1'0 - assign \rp_CR_cr_b_cr0_0 $818 - sync init - end - process $group_374 - assign \dp_CR_cr_b_cr0_0$next \dp_CR_cr_b_cr0_0 - assign \dp_CR_cr_b_cr0_0$next \rp_CR_cr_b_cr0_0 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \dp_CR_cr_b_cr0_0$next 1'0 - end - sync init - update \dp_CR_cr_b_cr0_0 1'0 - sync posedge \coresync_clk - update \dp_CR_cr_b_cr0_0 \dp_CR_cr_b_cr0_0$next - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:263" - wire width 16 \addr_en_CR_cr_b_cr0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:66" - wire width 4 $820 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:66" - cell $sub $821 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 4 - connect \A 3'111 - connect \B \core_cr_in2 - connect \Y $820 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:66" - wire width 16 $822 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:66" - cell $sshl $823 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 16 - connect \A 1'1 - connect \B $820 - connect \Y $822 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" - wire width 16 $824 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" - cell $mux $825 - parameter \WIDTH 16 - connect \A 16'0000000000000000 - connect \B $822 - connect \S \rp_CR_cr_b_cr0_0 - connect \Y $824 - end - process $group_375 - assign \addr_en_CR_cr_b_cr0_0 16'0000000000000000 - assign \addr_en_CR_cr_b_cr0_0 $824 - sync init - end - process $group_376 - assign \fus_src5_i$75 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" - switch { \dp_CR_cr_b_cr0_0 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" - case 1'1 - assign \fus_src5_i$75 \cr_src2__data_o - end - sync init - end - process $group_377 - assign \cr_src2__ren 8'00000000 - assign \cr_src2__ren \addr_en_CR_cr_b_cr0_0 [7:0] - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:240" - wire width 1 \rdflag_CR_cr_c_0 - process $group_378 - assign \rdflag_CR_cr_c_0 1'0 - assign \rdflag_CR_cr_c_0 \core_cr_in2_ok$2 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:264" - wire width 1 \pick_CR_cr_c_cr0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" - wire width 1 $826 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" - cell $and $827 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \fus_cu_rd__rel_o$31 [5] - connect \B \fu_enable [1] - connect \Y $826 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" - wire width 1 $828 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" - cell $and $829 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $826 - connect \B \rdflag_CR_cr_c_0 - connect \Y $828 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" - wire width 1 $830 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" - cell $not $831 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \dp_CR_cr_c_cr0_0 - connect \Y $830 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" - wire width 1 $832 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" - cell $and $833 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $828 - connect \B $830 - connect \Y $832 - end - process $group_379 - assign \pick_CR_cr_c_cr0_0 1'0 - assign \pick_CR_cr_c_cr0_0 $832 - sync init - end - process $group_380 - assign \rdpick_CR_cr_c_i 1'0 - assign \rdpick_CR_cr_c_i \pick_CR_cr_c_cr0_0 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:265" - wire width 1 \rp_CR_cr_c_cr0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" - wire width 1 $834 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" - cell $and $835 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \rdpick_CR_cr_c_o - connect \B \rdpick_CR_cr_c_en_o - connect \Y $834 - end - process $group_381 - assign \rp_CR_cr_c_cr0_0 1'0 - assign \rp_CR_cr_c_cr0_0 $834 - sync init - end - process $group_382 - assign \dp_CR_cr_c_cr0_0$next \dp_CR_cr_c_cr0_0 - assign \dp_CR_cr_c_cr0_0$next \rp_CR_cr_c_cr0_0 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \dp_CR_cr_c_cr0_0$next 1'0 - end - sync init - update \dp_CR_cr_c_cr0_0 1'0 - sync posedge \coresync_clk - update \dp_CR_cr_c_cr0_0 \dp_CR_cr_c_cr0_0$next - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:263" - wire width 16 \addr_en_CR_cr_c_cr0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:68" - wire width 4 $836 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:68" - cell $sub $837 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 4 - connect \A 3'111 - connect \B \core_cr_in2$1 - connect \Y $836 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:68" - wire width 16 $838 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:68" - cell $sshl $839 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 16 - connect \A 1'1 - connect \B $836 - connect \Y $838 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" - wire width 16 $840 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" - cell $mux $841 - parameter \WIDTH 16 - connect \A 16'0000000000000000 - connect \B $838 - connect \S \rp_CR_cr_c_cr0_0 - connect \Y $840 - end - process $group_383 - assign \addr_en_CR_cr_c_cr0_0 16'0000000000000000 - assign \addr_en_CR_cr_c_cr0_0 $840 - sync init - end - process $group_384 - assign \fus_src6_i$76 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" - switch { \dp_CR_cr_c_cr0_0 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" - case 1'1 - assign \fus_src6_i$76 \cr_src3__data_o - end - sync init - end - process $group_385 - assign \cr_src3__ren 8'00000000 - assign \cr_src3__ren \addr_en_CR_cr_c_cr0_0 [7:0] - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:240" - wire width 1 \rdflag_FAST_fast1_0 - process $group_386 - assign \rdflag_FAST_fast1_0 1'0 - assign \rdflag_FAST_fast1_0 \core_fast1_ok - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:264" - wire width 1 \pick_FAST_fast1_branch0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" - wire width 1 $842 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" - cell $and $843 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \fus_cu_rd__rel_o$72 [0] - connect \B \fu_enable [2] - connect \Y $842 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" - wire width 1 $844 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" - cell $and $845 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $842 - connect \B \rdflag_FAST_fast1_0 - connect \Y $844 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" - wire width 1 $846 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" - cell $not $847 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \dp_FAST_fast1_branch0_0 - connect \Y $846 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" - wire width 1 $848 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" - cell $and $849 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $844 - connect \B $846 - connect \Y $848 - end - process $group_387 - assign \pick_FAST_fast1_branch0_0 1'0 - assign \pick_FAST_fast1_branch0_0 $848 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:264" - wire width 1 \pick_FAST_fast1_trap0_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:264" - wire width 1 \pick_FAST_fast1_spr0_2 - process $group_388 - assign \rdpick_FAST_fast1_i 3'000 - assign \rdpick_FAST_fast1_i [0] \pick_FAST_fast1_branch0_0 - assign \rdpick_FAST_fast1_i [1] \pick_FAST_fast1_trap0_1 - assign \rdpick_FAST_fast1_i [2] \pick_FAST_fast1_spr0_2 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:265" - wire width 1 \rp_FAST_fast1_branch0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" - wire width 1 $850 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" - cell $and $851 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \rdpick_FAST_fast1_o [0] - connect \B \rdpick_FAST_fast1_en_o - connect \Y $850 - end - process $group_389 - assign \rp_FAST_fast1_branch0_0 1'0 - assign \rp_FAST_fast1_branch0_0 $850 - sync init - end - process $group_390 - assign \dp_FAST_fast1_branch0_0$next \dp_FAST_fast1_branch0_0 - assign \dp_FAST_fast1_branch0_0$next \rp_FAST_fast1_branch0_0 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \dp_FAST_fast1_branch0_0$next 1'0 - end - sync init - update \dp_FAST_fast1_branch0_0 1'0 - sync posedge \coresync_clk - update \dp_FAST_fast1_branch0_0 \dp_FAST_fast1_branch0_0$next - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:263" - wire width 3 \addr_en_FAST_fast1_branch0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" - wire width 3 $852 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" - cell $mux $853 - parameter \WIDTH 3 - connect \A 3'000 - connect \B \core_fast1 - connect \S \rp_FAST_fast1_branch0_0 - connect \Y $852 - end - process $group_391 - assign \addr_en_FAST_fast1_branch0_0 3'000 - assign \addr_en_FAST_fast1_branch0_0 $852 - sync init - end - process $group_392 - assign \fus_src1_i$77 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" - switch { \dp_FAST_fast1_branch0_0 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" - case 1'1 - assign \fus_src1_i$77 \fast_src1__data_o - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" - wire width 1 $854 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" - cell $and $855 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \fus_cu_rd__rel_o$34 [2] - connect \B \fu_enable [3] - connect \Y $854 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" - wire width 1 $856 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" - cell $and $857 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $854 - connect \B \rdflag_FAST_fast1_0 - connect \Y $856 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" - wire width 1 $858 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" - cell $not $859 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \dp_FAST_fast1_trap0_1 - connect \Y $858 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" - wire width 1 $860 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" - cell $and $861 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $856 - connect \B $858 - connect \Y $860 - end - process $group_393 - assign \pick_FAST_fast1_trap0_1 1'0 - assign \pick_FAST_fast1_trap0_1 $860 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:265" - wire width 1 \rp_FAST_fast1_trap0_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" - wire width 1 $862 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" - cell $and $863 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \rdpick_FAST_fast1_o [1] - connect \B \rdpick_FAST_fast1_en_o - connect \Y $862 - end - process $group_394 - assign \rp_FAST_fast1_trap0_1 1'0 - assign \rp_FAST_fast1_trap0_1 $862 - sync init - end - process $group_395 - assign \dp_FAST_fast1_trap0_1$next \dp_FAST_fast1_trap0_1 - assign \dp_FAST_fast1_trap0_1$next \rp_FAST_fast1_trap0_1 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \dp_FAST_fast1_trap0_1$next 1'0 - end - sync init - update \dp_FAST_fast1_trap0_1 1'0 - sync posedge \coresync_clk - update \dp_FAST_fast1_trap0_1 \dp_FAST_fast1_trap0_1$next - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:263" - wire width 3 \addr_en_FAST_fast1_trap0_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" - wire width 3 $864 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" - cell $mux $865 - parameter \WIDTH 3 - connect \A 3'000 - connect \B \core_fast1 - connect \S \rp_FAST_fast1_trap0_1 - connect \Y $864 - end - process $group_396 - assign \addr_en_FAST_fast1_trap0_1 3'000 - assign \addr_en_FAST_fast1_trap0_1 $864 - sync init - end - process $group_397 - assign \fus_src3_i$78 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" - switch { \dp_FAST_fast1_trap0_1 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" - case 1'1 - assign \fus_src3_i$78 \fast_src1__data_o - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" - wire width 1 $866 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" - cell $and $867 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \fus_cu_rd__rel_o$40 [2] - connect \B \fu_enable [5] - connect \Y $866 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" - wire width 1 $868 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" - cell $and $869 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $866 - connect \B \rdflag_FAST_fast1_0 - connect \Y $868 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" - wire width 1 $870 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" - cell $not $871 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \dp_FAST_fast1_spr0_2 - connect \Y $870 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" - wire width 1 $872 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" - cell $and $873 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $868 - connect \B $870 - connect \Y $872 - end - process $group_398 - assign \pick_FAST_fast1_spr0_2 1'0 - assign \pick_FAST_fast1_spr0_2 $872 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:265" - wire width 1 \rp_FAST_fast1_spr0_2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" - wire width 1 $874 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" - cell $and $875 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \rdpick_FAST_fast1_o [2] - connect \B \rdpick_FAST_fast1_en_o - connect \Y $874 - end - process $group_399 - assign \rp_FAST_fast1_spr0_2 1'0 - assign \rp_FAST_fast1_spr0_2 $874 - sync init - end - process $group_400 - assign \dp_FAST_fast1_spr0_2$next \dp_FAST_fast1_spr0_2 - assign \dp_FAST_fast1_spr0_2$next \rp_FAST_fast1_spr0_2 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \dp_FAST_fast1_spr0_2$next 1'0 - end - sync init - update \dp_FAST_fast1_spr0_2 1'0 - sync posedge \coresync_clk - update \dp_FAST_fast1_spr0_2 \dp_FAST_fast1_spr0_2$next - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:263" - wire width 3 \addr_en_FAST_fast1_spr0_2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" - wire width 3 $876 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" - cell $mux $877 - parameter \WIDTH 3 - connect \A 3'000 - connect \B \core_fast1 - connect \S \rp_FAST_fast1_spr0_2 - connect \Y $876 - end - process $group_401 - assign \addr_en_FAST_fast1_spr0_2 3'000 - assign \addr_en_FAST_fast1_spr0_2 $876 - sync init - end - process $group_402 - assign \fus_src3_i$79 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" - switch { \dp_FAST_fast1_spr0_2 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" - case 1'1 - assign \fus_src3_i$79 \fast_src1__data_o - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - wire width 3 $878 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $or $879 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A \addr_en_FAST_fast1_trap0_1 - connect \B \addr_en_FAST_fast1_spr0_2 - connect \Y $878 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - wire width 3 $880 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - cell $or $881 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A \addr_en_FAST_fast1_branch0_0 - connect \B $878 - connect \Y $880 - end - process $group_403 - assign \fast_src1__addr 3'000 - assign \fast_src1__addr $880 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:304" - wire width 1 $882 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:304" - cell $reduce_bool $883 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A { \rp_FAST_fast1_spr0_2 \rp_FAST_fast1_trap0_1 \rp_FAST_fast1_branch0_0 } - connect \Y $882 - end - process $group_404 - assign \fast_src1__ren 1'0 - assign \fast_src1__ren $882 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:240" - wire width 1 \rdflag_FAST_fast2_0 - process $group_405 - assign \rdflag_FAST_fast2_0 1'0 - assign \rdflag_FAST_fast2_0 \core_fast2_ok - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:264" - wire width 1 \pick_FAST_fast2_branch0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" - wire width 1 $884 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" - cell $and $885 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \fus_cu_rd__rel_o$72 [1] - connect \B \fu_enable [2] - connect \Y $884 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" - wire width 1 $886 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" - cell $and $887 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $884 - connect \B \rdflag_FAST_fast2_0 - connect \Y $886 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" - wire width 1 $888 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" - cell $not $889 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \dp_FAST_fast2_branch0_0 - connect \Y $888 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" - wire width 1 $890 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" - cell $and $891 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $886 - connect \B $888 - connect \Y $890 - end - process $group_406 - assign \pick_FAST_fast2_branch0_0 1'0 - assign \pick_FAST_fast2_branch0_0 $890 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:264" - wire width 1 \pick_FAST_fast2_trap0_1 - process $group_407 - assign \rdpick_FAST_fast2_i 2'00 - assign \rdpick_FAST_fast2_i [0] \pick_FAST_fast2_branch0_0 - assign \rdpick_FAST_fast2_i [1] \pick_FAST_fast2_trap0_1 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:265" - wire width 1 \rp_FAST_fast2_branch0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" - wire width 1 $892 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" - cell $and $893 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \rdpick_FAST_fast2_o [0] - connect \B \rdpick_FAST_fast2_en_o - connect \Y $892 - end - process $group_408 - assign \rp_FAST_fast2_branch0_0 1'0 - assign \rp_FAST_fast2_branch0_0 $892 - sync init - end - process $group_409 - assign \dp_FAST_fast2_branch0_0$next \dp_FAST_fast2_branch0_0 - assign \dp_FAST_fast2_branch0_0$next \rp_FAST_fast2_branch0_0 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \dp_FAST_fast2_branch0_0$next 1'0 - end - sync init - update \dp_FAST_fast2_branch0_0 1'0 - sync posedge \coresync_clk - update \dp_FAST_fast2_branch0_0 \dp_FAST_fast2_branch0_0$next - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:263" - wire width 3 \addr_en_FAST_fast2_branch0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" - wire width 3 $894 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" - cell $mux $895 - parameter \WIDTH 3 - connect \A 3'000 - connect \B \core_fast2 - connect \S \rp_FAST_fast2_branch0_0 - connect \Y $894 - end - process $group_410 - assign \addr_en_FAST_fast2_branch0_0 3'000 - assign \addr_en_FAST_fast2_branch0_0 $894 - sync init - end - process $group_411 - assign \fus_src2_i$80 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" - switch { \dp_FAST_fast2_branch0_0 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" - case 1'1 - assign \fus_src2_i$80 \fast_src2__data_o - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" - wire width 1 $896 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" - cell $and $897 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \fus_cu_rd__rel_o$34 [3] - connect \B \fu_enable [3] - connect \Y $896 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" - wire width 1 $898 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" - cell $and $899 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $896 - connect \B \rdflag_FAST_fast2_0 - connect \Y $898 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" - wire width 1 $900 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" - cell $not $901 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \dp_FAST_fast2_trap0_1 - connect \Y $900 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" - wire width 1 $902 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" - cell $and $903 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $898 - connect \B $900 - connect \Y $902 - end - process $group_412 - assign \pick_FAST_fast2_trap0_1 1'0 - assign \pick_FAST_fast2_trap0_1 $902 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:265" - wire width 1 \rp_FAST_fast2_trap0_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" - wire width 1 $904 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" - cell $and $905 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \rdpick_FAST_fast2_o [1] - connect \B \rdpick_FAST_fast2_en_o - connect \Y $904 - end - process $group_413 - assign \rp_FAST_fast2_trap0_1 1'0 - assign \rp_FAST_fast2_trap0_1 $904 - sync init - end - process $group_414 - assign \dp_FAST_fast2_trap0_1$next \dp_FAST_fast2_trap0_1 - assign \dp_FAST_fast2_trap0_1$next \rp_FAST_fast2_trap0_1 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \dp_FAST_fast2_trap0_1$next 1'0 - end - sync init - update \dp_FAST_fast2_trap0_1 1'0 - sync posedge \coresync_clk - update \dp_FAST_fast2_trap0_1 \dp_FAST_fast2_trap0_1$next - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:263" - wire width 3 \addr_en_FAST_fast2_trap0_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" - wire width 3 $906 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" - cell $mux $907 - parameter \WIDTH 3 - connect \A 3'000 - connect \B \core_fast2 - connect \S \rp_FAST_fast2_trap0_1 - connect \Y $906 - end - process $group_415 - assign \addr_en_FAST_fast2_trap0_1 3'000 - assign \addr_en_FAST_fast2_trap0_1 $906 - sync init - end - process $group_416 - assign \fus_src4_i$81 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" - switch { \dp_FAST_fast2_trap0_1 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" - case 1'1 - assign \fus_src4_i$81 \fast_src2__data_o - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - wire width 3 $908 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $or $909 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A \addr_en_FAST_fast2_branch0_0 - connect \B \addr_en_FAST_fast2_trap0_1 - connect \Y $908 - end - process $group_417 - assign \fast_src2__addr 3'000 - assign \fast_src2__addr $908 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:304" - wire width 1 $910 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:304" - cell $reduce_bool $911 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A { \rp_FAST_fast2_trap0_1 \rp_FAST_fast2_branch0_0 } - connect \Y $910 - end - process $group_418 - assign \fast_src2__ren 1'0 - assign \fast_src2__ren $910 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:240" - wire width 1 \rdflag_SPR_spr1_0 - process $group_419 - assign \rdflag_SPR_spr1_0 1'0 - assign \rdflag_SPR_spr1_0 \core_spr1_ok - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:264" - wire width 1 \pick_SPR_spr1_spr0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" - wire width 1 $912 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" - cell $and $913 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \fus_cu_rd__rel_o$40 [1] - connect \B \fu_enable [5] - connect \Y $912 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" - wire width 1 $914 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:269" - cell $and $915 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $912 - connect \B \rdflag_SPR_spr1_0 - connect \Y $914 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" - wire width 1 $916 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" - cell $not $917 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \dp_SPR_spr1_spr0_0 - connect \Y $916 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" - wire width 1 $918 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:270" - cell $and $919 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $914 - connect \B $916 - connect \Y $918 - end - process $group_420 - assign \pick_SPR_spr1_spr0_0 1'0 - assign \pick_SPR_spr1_spr0_0 $918 - sync init - end - process $group_421 - assign \rdpick_SPR_spr1_i 1'0 - assign \rdpick_SPR_spr1_i \pick_SPR_spr1_spr0_0 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:265" - wire width 1 \rp_SPR_spr1_spr0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" - wire width 1 $920 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:275" - cell $and $921 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \rdpick_SPR_spr1_o - connect \B \rdpick_SPR_spr1_en_o - connect \Y $920 - end - process $group_422 - assign \rp_SPR_spr1_spr0_0 1'0 - assign \rp_SPR_spr1_spr0_0 $920 - sync init - end - process $group_423 - assign \dp_SPR_spr1_spr0_0$next \dp_SPR_spr1_spr0_0 - assign \dp_SPR_spr1_spr0_0$next \rp_SPR_spr1_spr0_0 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \dp_SPR_spr1_spr0_0$next 1'0 - end - sync init - update \dp_SPR_spr1_spr0_0 1'0 - sync posedge \coresync_clk - update \dp_SPR_spr1_spr0_0 \dp_SPR_spr1_spr0_0$next - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:263" - wire width 10 \addr_en_SPR_spr1_spr0_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" - wire width 10 $922 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:277" - cell $mux $923 - parameter \WIDTH 10 - connect \A 10'0000000000 - connect \B \core_spr1 - connect \S \rp_SPR_spr1_spr0_0 - connect \Y $922 - end - process $group_424 - assign \addr_en_SPR_spr1_spr0_0 10'0000000000 - assign \addr_en_SPR_spr1_spr0_0 $922 - sync init - end - process $group_425 - assign \fus_src2_i$82 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" - switch { \dp_SPR_spr1_spr0_0 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:288" - case 1'1 - assign \fus_src2_i$82 \spr_spr1__data_o - end - sync init - end - process $group_426 - assign \spr_spr1__addr 7'0000000 - assign \spr_spr1__addr \addr_en_SPR_spr1_spr0_0 [6:0] - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:304" - wire width 1 $924 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:304" - cell $reduce_bool $925 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A { \rp_SPR_spr1_spr0_0 } - connect \Y $924 - end - process $group_427 - assign \spr_spr1__ren 1'0 - assign \spr_spr1__ren $924 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:390" - wire width 1 \wrflag_alu0_o_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:391" - wire width 1 $926 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:391" - cell $and $927 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \fus_o_ok - connect \B \fus_cu_busy_o - connect \Y $926 - end - process $group_428 - assign \wrflag_alu0_o_0 1'0 - assign \wrflag_alu0_o_0 $926 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:395" - wire width 1 $928 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:395" - cell $and $929 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \fus_cu_wr__rel_o [0] - connect \B \fu_enable [0] - connect \Y $928 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:395" - wire width 1 $930 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:395" - cell $and $931 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \fus_cu_wr__rel_o$84 [0] - connect \B \fu_enable [1] - connect \Y $930 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:395" - wire width 1 $932 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:395" - cell $and $933 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \fus_cu_wr__rel_o$87 [0] - connect \B \fu_enable [3] - connect \Y $932 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:395" - wire width 1 $934 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:395" - cell $and $935 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \fus_cu_wr__rel_o$90 [0] - connect \B \fu_enable [4] - connect \Y $934 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:395" - wire width 1 $936 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:395" - cell $and $937 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \fus_cu_wr__rel_o$93 [0] - connect \B \fu_enable [5] - connect \Y $936 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:395" - wire width 1 $938 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:395" - cell $and $939 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \fus_cu_wr__rel_o$96 [0] - connect \B \fu_enable [6] - connect \Y $938 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:395" - wire width 1 $940 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:395" - cell $and $941 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \fus_cu_wr__rel_o$99 [0] - connect \B \fu_enable [7] - connect \Y $940 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:395" - wire width 1 $942 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:395" - cell $and $943 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \fus_cu_wr__rel_o$102 [0] - connect \B \fu_enable [8] - connect \Y $942 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:395" - wire width 1 $944 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:395" - cell $and $945 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \fus_cu_wr__rel_o$104 [0] - connect \B \fu_enable [9] - connect \Y $944 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:395" - wire width 1 $946 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:395" - cell $and $947 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \fus_cu_wr__rel_o$104 [1] - connect \B \fu_enable [9] - connect \Y $946 - end - process $group_429 - assign \wrpick_INT_o_i 10'0000000000 - assign \wrpick_INT_o_i [0] $928 - assign \wrpick_INT_o_i [1] $930 - assign \wrpick_INT_o_i [2] $932 - assign \wrpick_INT_o_i [3] $934 - assign \wrpick_INT_o_i [4] $936 - assign \wrpick_INT_o_i [5] $938 - assign \wrpick_INT_o_i [6] $940 - assign \wrpick_INT_o_i [7] $942 - assign \wrpick_INT_o_i [8] $944 - assign \wrpick_INT_o_i [9] $946 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:398" - wire width 1 \wr_pick - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:399" - wire width 1 $948 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:399" - cell $and $949 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wrpick_INT_o_o [0] - connect \B \wrpick_INT_o_en_o - connect \Y $948 - end - process $group_430 - assign \wr_pick 1'0 - assign \wr_pick $948 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire width 1 \wr_pick_dly - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire width 1 \wr_pick_dly$next - process $group_431 - assign \wr_pick_dly$next \wr_pick_dly - assign \wr_pick_dly$next \wr_pick - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \wr_pick_dly$next 1'0 - end - sync init - update \wr_pick_dly 1'0 - sync posedge \coresync_clk - update \wr_pick_dly \wr_pick_dly$next - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" - wire width 1 \wr_pick_rise - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - wire width 1 $950 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $not $951 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_pick_dly - connect \Y $950 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - wire width 1 $952 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $and $953 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_pick - connect \B $950 - connect \Y $952 - end - process $group_432 - assign \wr_pick_rise 1'0 - assign \wr_pick_rise $952 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" - wire width 1 \wr_pick_rise$954 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" - wire width 1 \wr_pick_rise$955 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" - wire width 1 \wr_pick_rise$956 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" - wire width 1 \wr_pick_rise$957 - process $group_433 - assign \fus_cu_wr__go_i 5'00000 - assign \fus_cu_wr__go_i [0] \wr_pick_rise - assign \fus_cu_wr__go_i [1] \wr_pick_rise$954 - assign \fus_cu_wr__go_i [2] \wr_pick_rise$955 - assign \fus_cu_wr__go_i [3] \wr_pick_rise$956 - assign \fus_cu_wr__go_i [4] \wr_pick_rise$957 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:406" - wire width 1 \wp - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" - wire width 1 $958 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" - cell $and $959 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_pick - connect \B \wrpick_INT_o_en_o - connect \Y $958 - end - process $group_434 - assign \wp 1'0 - assign \wp $958 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:405" - wire width 5 \addr_en - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408" - wire width 5 $960 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408" - cell $mux $961 - parameter \WIDTH 5 - connect \A 5'00000 - connect \B \core_rego - connect \S \wp - connect \Y $960 - end - process $group_435 - assign \addr_en 5'00000 - assign \addr_en $960 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:390" - wire width 1 \wrflag_cr0_o_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:391" - wire width 1 $962 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:391" - cell $and $963 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \fus_o_ok$83 - connect \B \fus_cu_busy_o$5 - connect \Y $962 - end - process $group_436 - assign \wrflag_cr0_o_0 1'0 - assign \wrflag_cr0_o_0 $962 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:398" - wire width 1 \wr_pick$964 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:399" - wire width 1 $965 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:399" - cell $and $966 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wrpick_INT_o_o [1] - connect \B \wrpick_INT_o_en_o - connect \Y $965 - end - process $group_437 - assign \wr_pick$964 1'0 - assign \wr_pick$964 $965 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire width 1 \wr_pick_dly$967 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire width 1 \wr_pick_dly$967$next - process $group_438 - assign \wr_pick_dly$967$next \wr_pick_dly$967 - assign \wr_pick_dly$967$next \wr_pick$964 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \wr_pick_dly$967$next 1'0 - end - sync init - update \wr_pick_dly$967 1'0 - sync posedge \coresync_clk - update \wr_pick_dly$967 \wr_pick_dly$967$next - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" - wire width 1 \wr_pick_rise$968 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - wire width 1 $969 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $not $970 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_pick_dly$967 - connect \Y $969 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - wire width 1 $971 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $and $972 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_pick$964 - connect \B $969 - connect \Y $971 - end - process $group_439 - assign \wr_pick_rise$968 1'0 - assign \wr_pick_rise$968 $971 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" - wire width 1 \wr_pick_rise$973 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" - wire width 1 \wr_pick_rise$974 - process $group_440 - assign \fus_cu_wr__go_i$85 3'000 - assign \fus_cu_wr__go_i$85 [0] \wr_pick_rise$968 - assign \fus_cu_wr__go_i$85 [1] \wr_pick_rise$973 - assign \fus_cu_wr__go_i$85 [2] \wr_pick_rise$974 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:406" - wire width 1 \wp$975 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" - wire width 1 $976 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" - cell $and $977 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_pick$964 - connect \B \wrpick_INT_o_en_o - connect \Y $976 - end - process $group_441 - assign \wp$975 1'0 - assign \wp$975 $976 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:405" - wire width 5 \addr_en$978 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408" - wire width 5 $979 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408" - cell $mux $980 - parameter \WIDTH 5 - connect \A 5'00000 - connect \B \core_rego - connect \S \wp$975 - connect \Y $979 - end - process $group_442 - assign \addr_en$978 5'00000 - assign \addr_en$978 $979 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:390" - wire width 1 \wrflag_trap0_o_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:391" - wire width 1 $981 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:391" - cell $and $982 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \fus_o_ok$86 - connect \B \fus_cu_busy_o$11 - connect \Y $981 - end - process $group_443 - assign \wrflag_trap0_o_0 1'0 - assign \wrflag_trap0_o_0 $981 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:398" - wire width 1 \wr_pick$983 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:399" - wire width 1 $984 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:399" - cell $and $985 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wrpick_INT_o_o [2] - connect \B \wrpick_INT_o_en_o - connect \Y $984 - end - process $group_444 - assign \wr_pick$983 1'0 - assign \wr_pick$983 $984 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire width 1 \wr_pick_dly$986 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire width 1 \wr_pick_dly$986$next - process $group_445 - assign \wr_pick_dly$986$next \wr_pick_dly$986 - assign \wr_pick_dly$986$next \wr_pick$983 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \wr_pick_dly$986$next 1'0 - end - sync init - update \wr_pick_dly$986 1'0 - sync posedge \coresync_clk - update \wr_pick_dly$986 \wr_pick_dly$986$next - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" - wire width 1 \wr_pick_rise$987 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - wire width 1 $988 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $not $989 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_pick_dly$986 - connect \Y $988 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - wire width 1 $990 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $and $991 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_pick$983 - connect \B $988 - connect \Y $990 - end - process $group_446 - assign \wr_pick_rise$987 1'0 - assign \wr_pick_rise$987 $990 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" - wire width 1 \wr_pick_rise$992 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" - wire width 1 \wr_pick_rise$993 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" - wire width 1 \wr_pick_rise$994 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" - wire width 1 \wr_pick_rise$995 - process $group_447 - assign \fus_cu_wr__go_i$88 5'00000 - assign \fus_cu_wr__go_i$88 [0] \wr_pick_rise$987 - assign \fus_cu_wr__go_i$88 [1] \wr_pick_rise$992 - assign \fus_cu_wr__go_i$88 [2] \wr_pick_rise$993 - assign \fus_cu_wr__go_i$88 [3] \wr_pick_rise$994 - assign \fus_cu_wr__go_i$88 [4] \wr_pick_rise$995 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:406" - wire width 1 \wp$996 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" - wire width 1 $997 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" - cell $and $998 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_pick$983 - connect \B \wrpick_INT_o_en_o - connect \Y $997 - end - process $group_448 - assign \wp$996 1'0 - assign \wp$996 $997 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:405" - wire width 5 \addr_en$999 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408" - wire width 5 $1000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408" - cell $mux $1001 - parameter \WIDTH 5 - connect \A 5'00000 - connect \B \core_rego - connect \S \wp$996 - connect \Y $1000 - end - process $group_449 - assign \addr_en$999 5'00000 - assign \addr_en$999 $1000 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:390" - wire width 1 \wrflag_logical0_o_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:391" - wire width 1 $1002 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:391" - cell $and $1003 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \fus_o_ok$89 - connect \B \fus_cu_busy_o$14 - connect \Y $1002 - end - process $group_450 - assign \wrflag_logical0_o_0 1'0 - assign \wrflag_logical0_o_0 $1002 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:398" - wire width 1 \wr_pick$1004 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:399" - wire width 1 $1005 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:399" - cell $and $1006 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wrpick_INT_o_o [3] - connect \B \wrpick_INT_o_en_o - connect \Y $1005 - end - process $group_451 - assign \wr_pick$1004 1'0 - assign \wr_pick$1004 $1005 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire width 1 \wr_pick_dly$1007 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire width 1 \wr_pick_dly$1007$next - process $group_452 - assign \wr_pick_dly$1007$next \wr_pick_dly$1007 - assign \wr_pick_dly$1007$next \wr_pick$1004 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \wr_pick_dly$1007$next 1'0 - end - sync init - update \wr_pick_dly$1007 1'0 - sync posedge \coresync_clk - update \wr_pick_dly$1007 \wr_pick_dly$1007$next - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" - wire width 1 \wr_pick_rise$1008 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - wire width 1 $1009 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $not $1010 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_pick_dly$1007 - connect \Y $1009 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - wire width 1 $1011 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $and $1012 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_pick$1004 - connect \B $1009 - connect \Y $1011 - end - process $group_453 - assign \wr_pick_rise$1008 1'0 - assign \wr_pick_rise$1008 $1011 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" - wire width 1 \wr_pick_rise$1013 - process $group_454 - assign \fus_cu_wr__go_i$91 2'00 - assign \fus_cu_wr__go_i$91 [0] \wr_pick_rise$1008 - assign \fus_cu_wr__go_i$91 [1] \wr_pick_rise$1013 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:406" - wire width 1 \wp$1014 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" - wire width 1 $1015 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" - cell $and $1016 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_pick$1004 - connect \B \wrpick_INT_o_en_o - connect \Y $1015 - end - process $group_455 - assign \wp$1014 1'0 - assign \wp$1014 $1015 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:405" - wire width 5 \addr_en$1017 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408" - wire width 5 $1018 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408" - cell $mux $1019 - parameter \WIDTH 5 - connect \A 5'00000 - connect \B \core_rego - connect \S \wp$1014 - connect \Y $1018 - end - process $group_456 - assign \addr_en$1017 5'00000 - assign \addr_en$1017 $1018 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:390" - wire width 1 \wrflag_spr0_o_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:391" - wire width 1 $1020 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:391" - cell $and $1021 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \fus_o_ok$92 - connect \B \fus_cu_busy_o$17 - connect \Y $1020 - end - process $group_457 - assign \wrflag_spr0_o_0 1'0 - assign \wrflag_spr0_o_0 $1020 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:398" - wire width 1 \wr_pick$1022 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:399" - wire width 1 $1023 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:399" - cell $and $1024 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wrpick_INT_o_o [4] - connect \B \wrpick_INT_o_en_o - connect \Y $1023 - end - process $group_458 - assign \wr_pick$1022 1'0 - assign \wr_pick$1022 $1023 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire width 1 \wr_pick_dly$1025 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire width 1 \wr_pick_dly$1025$next - process $group_459 - assign \wr_pick_dly$1025$next \wr_pick_dly$1025 - assign \wr_pick_dly$1025$next \wr_pick$1022 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \wr_pick_dly$1025$next 1'0 - end - sync init - update \wr_pick_dly$1025 1'0 - sync posedge \coresync_clk - update \wr_pick_dly$1025 \wr_pick_dly$1025$next - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" - wire width 1 \wr_pick_rise$1026 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - wire width 1 $1027 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $not $1028 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_pick_dly$1025 - connect \Y $1027 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - wire width 1 $1029 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $and $1030 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_pick$1022 - connect \B $1027 - connect \Y $1029 - end - process $group_460 - assign \wr_pick_rise$1026 1'0 - assign \wr_pick_rise$1026 $1029 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" - wire width 1 \wr_pick_rise$1031 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" - wire width 1 \wr_pick_rise$1032 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" - wire width 1 \wr_pick_rise$1033 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" - wire width 1 \wr_pick_rise$1034 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" - wire width 1 \wr_pick_rise$1035 - process $group_461 - assign \fus_cu_wr__go_i$94 6'000000 - assign \fus_cu_wr__go_i$94 [0] \wr_pick_rise$1026 - assign \fus_cu_wr__go_i$94 [5] \wr_pick_rise$1031 - assign \fus_cu_wr__go_i$94 [4] \wr_pick_rise$1032 - assign \fus_cu_wr__go_i$94 [3] \wr_pick_rise$1033 - assign \fus_cu_wr__go_i$94 [2] \wr_pick_rise$1034 - assign \fus_cu_wr__go_i$94 [1] \wr_pick_rise$1035 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:406" - wire width 1 \wp$1036 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" - wire width 1 $1037 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" - cell $and $1038 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_pick$1022 - connect \B \wrpick_INT_o_en_o - connect \Y $1037 - end - process $group_462 - assign \wp$1036 1'0 - assign \wp$1036 $1037 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:405" - wire width 5 \addr_en$1039 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408" - wire width 5 $1040 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408" - cell $mux $1041 - parameter \WIDTH 5 - connect \A 5'00000 - connect \B \core_rego - connect \S \wp$1036 - connect \Y $1040 - end - process $group_463 - assign \addr_en$1039 5'00000 - assign \addr_en$1039 $1040 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:390" - wire width 1 \wrflag_div0_o_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:391" - wire width 1 $1042 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:391" - cell $and $1043 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \fus_o_ok$95 - connect \B \fus_cu_busy_o$20 - connect \Y $1042 - end - process $group_464 - assign \wrflag_div0_o_0 1'0 - assign \wrflag_div0_o_0 $1042 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:398" - wire width 1 \wr_pick$1044 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:399" - wire width 1 $1045 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:399" - cell $and $1046 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wrpick_INT_o_o [5] - connect \B \wrpick_INT_o_en_o - connect \Y $1045 - end - process $group_465 - assign \wr_pick$1044 1'0 - assign \wr_pick$1044 $1045 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire width 1 \wr_pick_dly$1047 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire width 1 \wr_pick_dly$1047$next - process $group_466 - assign \wr_pick_dly$1047$next \wr_pick_dly$1047 - assign \wr_pick_dly$1047$next \wr_pick$1044 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \wr_pick_dly$1047$next 1'0 - end - sync init - update \wr_pick_dly$1047 1'0 - sync posedge \coresync_clk - update \wr_pick_dly$1047 \wr_pick_dly$1047$next - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" - wire width 1 \wr_pick_rise$1048 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - wire width 1 $1049 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $not $1050 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_pick_dly$1047 - connect \Y $1049 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - wire width 1 $1051 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $and $1052 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_pick$1044 - connect \B $1049 - connect \Y $1051 - end - process $group_467 - assign \wr_pick_rise$1048 1'0 - assign \wr_pick_rise$1048 $1051 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" - wire width 1 \wr_pick_rise$1053 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" - wire width 1 \wr_pick_rise$1054 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" - wire width 1 \wr_pick_rise$1055 - process $group_468 - assign \fus_cu_wr__go_i$97 4'0000 - assign \fus_cu_wr__go_i$97 [0] \wr_pick_rise$1048 - assign \fus_cu_wr__go_i$97 [1] \wr_pick_rise$1053 - assign \fus_cu_wr__go_i$97 [2] \wr_pick_rise$1054 - assign \fus_cu_wr__go_i$97 [3] \wr_pick_rise$1055 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:406" - wire width 1 \wp$1056 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" - wire width 1 $1057 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" - cell $and $1058 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_pick$1044 - connect \B \wrpick_INT_o_en_o - connect \Y $1057 - end - process $group_469 - assign \wp$1056 1'0 - assign \wp$1056 $1057 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:405" - wire width 5 \addr_en$1059 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408" - wire width 5 $1060 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408" - cell $mux $1061 - parameter \WIDTH 5 - connect \A 5'00000 - connect \B \core_rego - connect \S \wp$1056 - connect \Y $1060 - end - process $group_470 - assign \addr_en$1059 5'00000 - assign \addr_en$1059 $1060 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:390" - wire width 1 \wrflag_mul0_o_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:391" - wire width 1 $1062 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:391" - cell $and $1063 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \fus_o_ok$98 - connect \B \fus_cu_busy_o$23 - connect \Y $1062 - end - process $group_471 - assign \wrflag_mul0_o_0 1'0 - assign \wrflag_mul0_o_0 $1062 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:398" - wire width 1 \wr_pick$1064 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:399" - wire width 1 $1065 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:399" - cell $and $1066 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wrpick_INT_o_o [6] - connect \B \wrpick_INT_o_en_o - connect \Y $1065 - end - process $group_472 - assign \wr_pick$1064 1'0 - assign \wr_pick$1064 $1065 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire width 1 \wr_pick_dly$1067 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire width 1 \wr_pick_dly$1067$next - process $group_473 - assign \wr_pick_dly$1067$next \wr_pick_dly$1067 - assign \wr_pick_dly$1067$next \wr_pick$1064 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \wr_pick_dly$1067$next 1'0 - end - sync init - update \wr_pick_dly$1067 1'0 - sync posedge \coresync_clk - update \wr_pick_dly$1067 \wr_pick_dly$1067$next - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" - wire width 1 \wr_pick_rise$1068 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - wire width 1 $1069 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $not $1070 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_pick_dly$1067 - connect \Y $1069 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - wire width 1 $1071 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $and $1072 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_pick$1064 - connect \B $1069 - connect \Y $1071 - end - process $group_474 - assign \wr_pick_rise$1068 1'0 - assign \wr_pick_rise$1068 $1071 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" - wire width 1 \wr_pick_rise$1073 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" - wire width 1 \wr_pick_rise$1074 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" - wire width 1 \wr_pick_rise$1075 - process $group_475 - assign \fus_cu_wr__go_i$100 4'0000 - assign \fus_cu_wr__go_i$100 [0] \wr_pick_rise$1068 - assign \fus_cu_wr__go_i$100 [1] \wr_pick_rise$1073 - assign \fus_cu_wr__go_i$100 [2] \wr_pick_rise$1074 - assign \fus_cu_wr__go_i$100 [3] \wr_pick_rise$1075 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:406" - wire width 1 \wp$1076 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" - wire width 1 $1077 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" - cell $and $1078 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_pick$1064 - connect \B \wrpick_INT_o_en_o - connect \Y $1077 - end - process $group_476 - assign \wp$1076 1'0 - assign \wp$1076 $1077 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:405" - wire width 5 \addr_en$1079 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408" - wire width 5 $1080 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408" - cell $mux $1081 - parameter \WIDTH 5 - connect \A 5'00000 - connect \B \core_rego - connect \S \wp$1076 - connect \Y $1080 - end - process $group_477 - assign \addr_en$1079 5'00000 - assign \addr_en$1079 $1080 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:390" - wire width 1 \wrflag_shiftrot0_o_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:391" - wire width 1 $1082 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:391" - cell $and $1083 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \fus_o_ok$101 - connect \B \fus_cu_busy_o$26 - connect \Y $1082 - end - process $group_478 - assign \wrflag_shiftrot0_o_0 1'0 - assign \wrflag_shiftrot0_o_0 $1082 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:398" - wire width 1 \wr_pick$1084 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:399" - wire width 1 $1085 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:399" - cell $and $1086 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wrpick_INT_o_o [7] - connect \B \wrpick_INT_o_en_o - connect \Y $1085 - end - process $group_479 - assign \wr_pick$1084 1'0 - assign \wr_pick$1084 $1085 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire width 1 \wr_pick_dly$1087 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire width 1 \wr_pick_dly$1087$next - process $group_480 - assign \wr_pick_dly$1087$next \wr_pick_dly$1087 - assign \wr_pick_dly$1087$next \wr_pick$1084 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \wr_pick_dly$1087$next 1'0 - end - sync init - update \wr_pick_dly$1087 1'0 - sync posedge \coresync_clk - update \wr_pick_dly$1087 \wr_pick_dly$1087$next - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" - wire width 1 \wr_pick_rise$1088 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - wire width 1 $1089 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $not $1090 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_pick_dly$1087 - connect \Y $1089 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - wire width 1 $1091 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $and $1092 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_pick$1084 - connect \B $1089 - connect \Y $1091 - end - process $group_481 - assign \wr_pick_rise$1088 1'0 - assign \wr_pick_rise$1088 $1091 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" - wire width 1 \wr_pick_rise$1093 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" - wire width 1 \wr_pick_rise$1094 - process $group_482 - assign \fus_cu_wr__go_i$103 3'000 - assign \fus_cu_wr__go_i$103 [0] \wr_pick_rise$1088 - assign \fus_cu_wr__go_i$103 [1] \wr_pick_rise$1093 - assign \fus_cu_wr__go_i$103 [2] \wr_pick_rise$1094 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:406" - wire width 1 \wp$1095 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" - wire width 1 $1096 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" - cell $and $1097 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_pick$1084 - connect \B \wrpick_INT_o_en_o - connect \Y $1096 - end - process $group_483 - assign \wp$1095 1'0 - assign \wp$1095 $1096 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:405" - wire width 5 \addr_en$1098 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408" - wire width 5 $1099 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408" - cell $mux $1100 - parameter \WIDTH 5 - connect \A 5'00000 - connect \B \core_rego - connect \S \wp$1095 - connect \Y $1099 - end - process $group_484 - assign \addr_en$1098 5'00000 - assign \addr_en$1098 $1099 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:390" - wire width 1 \wrflag_ldst0_o_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:391" - wire width 1 $1101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:391" - cell $and $1102 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \o_ok - connect \B \fus_cu_busy_o$29 - connect \Y $1101 - end - process $group_485 - assign \wrflag_ldst0_o_0 1'0 - assign \wrflag_ldst0_o_0 $1101 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:398" - wire width 1 \wr_pick$1103 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:399" - wire width 1 $1104 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:399" - cell $and $1105 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wrpick_INT_o_o [8] - connect \B \wrpick_INT_o_en_o - connect \Y $1104 - end - process $group_486 - assign \wr_pick$1103 1'0 - assign \wr_pick$1103 $1104 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire width 1 \wr_pick_dly$1106 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire width 1 \wr_pick_dly$1106$next - process $group_487 - assign \wr_pick_dly$1106$next \wr_pick_dly$1106 - assign \wr_pick_dly$1106$next \wr_pick$1103 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \wr_pick_dly$1106$next 1'0 - end - sync init - update \wr_pick_dly$1106 1'0 - sync posedge \coresync_clk - update \wr_pick_dly$1106 \wr_pick_dly$1106$next - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" - wire width 1 \wr_pick_rise$1107 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - wire width 1 $1108 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $not $1109 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_pick_dly$1106 - connect \Y $1108 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - wire width 1 $1110 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $and $1111 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_pick$1103 - connect \B $1108 - connect \Y $1110 - end - process $group_488 - assign \wr_pick_rise$1107 1'0 - assign \wr_pick_rise$1107 $1110 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" - wire width 1 \wr_pick_rise$1112 - process $group_489 - assign \fus_cu_wr__go_i$105 2'00 - assign \fus_cu_wr__go_i$105 [0] \wr_pick_rise$1107 - assign \fus_cu_wr__go_i$105 [1] \wr_pick_rise$1112 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:406" - wire width 1 \wp$1113 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" - wire width 1 $1114 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" - cell $and $1115 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_pick$1103 - connect \B \wrpick_INT_o_en_o - connect \Y $1114 - end - process $group_490 - assign \wp$1113 1'0 - assign \wp$1113 $1114 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:405" - wire width 5 \addr_en$1116 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408" - wire width 5 $1117 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408" - cell $mux $1118 - parameter \WIDTH 5 - connect \A 5'00000 - connect \B \core_rego - connect \S \wp$1113 - connect \Y $1117 - end - process $group_491 - assign \addr_en$1116 5'00000 - assign \addr_en$1116 $1117 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:390" - wire width 1 \wrflag_ldst0_o_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \ea_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:391" - wire width 1 $1119 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:391" - cell $and $1120 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \ea_ok - connect \B \fus_cu_busy_o$29 - connect \Y $1119 - end - process $group_492 - assign \wrflag_ldst0_o_1 1'0 - assign \wrflag_ldst0_o_1 $1119 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:398" - wire width 1 \wr_pick$1121 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:399" - wire width 1 $1122 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:399" - cell $and $1123 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wrpick_INT_o_o [9] - connect \B \wrpick_INT_o_en_o - connect \Y $1122 - end - process $group_493 - assign \wr_pick$1121 1'0 - assign \wr_pick$1121 $1122 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire width 1 \wr_pick_dly$1124 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire width 1 \wr_pick_dly$1124$next - process $group_494 - assign \wr_pick_dly$1124$next \wr_pick_dly$1124 - assign \wr_pick_dly$1124$next \wr_pick$1121 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \wr_pick_dly$1124$next 1'0 - end - sync init - update \wr_pick_dly$1124 1'0 - sync posedge \coresync_clk - update \wr_pick_dly$1124 \wr_pick_dly$1124$next - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - wire width 1 $1125 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $not $1126 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_pick_dly$1124 - connect \Y $1125 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - wire width 1 $1127 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $and $1128 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_pick$1121 - connect \B $1125 - connect \Y $1127 - end - process $group_495 - assign \wr_pick_rise$1112 1'0 - assign \wr_pick_rise$1112 $1127 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:406" - wire width 1 \wp$1129 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" - wire width 1 $1130 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" - cell $and $1131 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_pick$1121 - connect \B \wrpick_INT_o_en_o - connect \Y $1130 - end - process $group_496 - assign \wp$1129 1'0 - assign \wp$1129 $1130 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:405" - wire width 5 \addr_en$1132 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408" - wire width 5 $1133 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408" - cell $mux $1134 - parameter \WIDTH 5 - connect \A 5'00000 - connect \B \core_ea - connect \S \wp$1129 - connect \Y $1133 - end - process $group_497 - assign \addr_en$1132 5'00000 - assign \addr_en$1132 $1133 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - wire width 65 $1135 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - wire width 64 $1136 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $or $1137 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \B_SIGNED 0 - parameter \B_WIDTH 64 - parameter \Y_WIDTH 64 - connect \A \fus_dest1_o - connect \B \fus_dest1_o$106 - connect \Y $1136 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - wire width 64 $1138 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $or $1139 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \B_SIGNED 0 - parameter \B_WIDTH 64 - parameter \Y_WIDTH 64 - connect \A \fus_dest1_o$108 - connect \B \fus_dest1_o$109 - connect \Y $1138 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - wire width 64 $1140 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - cell $or $1141 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \B_SIGNED 0 - parameter \B_WIDTH 64 - parameter \Y_WIDTH 64 - connect \A \fus_dest1_o$107 - connect \B $1138 - connect \Y $1140 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - wire width 64 $1142 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - cell $or $1143 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \B_SIGNED 0 - parameter \B_WIDTH 64 - parameter \Y_WIDTH 64 - connect \A $1136 - connect \B $1140 - connect \Y $1142 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - wire width 64 $1144 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $or $1145 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \B_SIGNED 0 - parameter \B_WIDTH 64 - parameter \Y_WIDTH 64 - connect \A \fus_dest1_o$110 - connect \B \fus_dest1_o$111 - connect \Y $1144 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - wire width 65 $1146 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $or $1147 - parameter \A_SIGNED 0 - parameter \A_WIDTH 65 - parameter \B_SIGNED 0 - parameter \B_WIDTH 65 - parameter \Y_WIDTH 65 - connect \A { \o_ok \fus_o } - connect \B { \ea_ok \fus_ea } - connect \Y $1146 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - wire width 65 $1148 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - cell $or $1149 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \B_SIGNED 0 - parameter \B_WIDTH 65 - parameter \Y_WIDTH 65 - connect \A \fus_dest1_o$112 - connect \B $1146 - connect \Y $1148 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - wire width 65 $1150 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - cell $or $1151 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \B_SIGNED 0 - parameter \B_WIDTH 65 - parameter \Y_WIDTH 65 - connect \A $1144 - connect \B $1148 - connect \Y $1150 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - wire width 65 $1152 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - cell $or $1153 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \B_SIGNED 0 - parameter \B_WIDTH 65 - parameter \Y_WIDTH 65 - connect \A $1142 - connect \B $1150 - connect \Y $1152 - end - connect $1135 $1152 - process $group_498 - assign \int_dest1__data_i 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \int_dest1__data_i $1135 [63:0] - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - wire width 5 $1154 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $or $1155 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 5 - connect \A \addr_en - connect \B \addr_en$978 - connect \Y $1154 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - wire width 5 $1156 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $or $1157 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 5 - connect \A \addr_en$1017 - connect \B \addr_en$1039 - connect \Y $1156 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - wire width 5 $1158 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - cell $or $1159 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 5 - connect \A \addr_en$999 - connect \B $1156 - connect \Y $1158 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - wire width 5 $1160 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - cell $or $1161 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 5 - connect \A $1154 - connect \B $1158 - connect \Y $1160 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - wire width 5 $1162 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $or $1163 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 5 - connect \A \addr_en$1059 - connect \B \addr_en$1079 - connect \Y $1162 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - wire width 5 $1164 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $or $1165 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 5 - connect \A \addr_en$1116 - connect \B \addr_en$1132 - connect \Y $1164 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - wire width 5 $1166 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - cell $or $1167 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 5 - connect \A \addr_en$1098 - connect \B $1164 - connect \Y $1166 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - wire width 5 $1168 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - cell $or $1169 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 5 - connect \A $1162 - connect \B $1166 - connect \Y $1168 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - wire width 5 $1170 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - cell $or $1171 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 5 - connect \A $1160 - connect \B $1168 - connect \Y $1170 - end - process $group_499 - assign \int_dest1__addr 5'00000 - assign \int_dest1__addr $1170 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - wire width 1 $1172 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $or $1173 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wp - connect \B \wp$975 - connect \Y $1172 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - wire width 1 $1174 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $or $1175 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wp$1014 - connect \B \wp$1036 - connect \Y $1174 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - wire width 1 $1176 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - cell $or $1177 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wp$996 - connect \B $1174 - connect \Y $1176 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - wire width 1 $1178 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - cell $or $1179 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $1172 - connect \B $1176 - connect \Y $1178 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - wire width 1 $1180 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $or $1181 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wp$1056 - connect \B \wp$1076 - connect \Y $1180 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - wire width 1 $1182 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $or $1183 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wp$1113 - connect \B \wp$1129 - connect \Y $1182 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - wire width 1 $1184 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - cell $or $1185 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wp$1095 - connect \B $1182 - connect \Y $1184 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - wire width 1 $1186 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - cell $or $1187 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $1180 - connect \B $1184 - connect \Y $1186 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - wire width 1 $1188 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - cell $or $1189 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $1178 - connect \B $1186 - connect \Y $1188 - end - process $group_500 - assign \int_dest1__wen 1'0 - assign \int_dest1__wen $1188 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:390" - wire width 1 \wrflag_cr0_full_cr_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:391" - wire width 1 $1190 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:391" - cell $and $1191 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \fus_full_cr_ok - connect \B \fus_cu_busy_o$5 - connect \Y $1190 - end - process $group_501 - assign \wrflag_cr0_full_cr_1 1'0 - assign \wrflag_cr0_full_cr_1 $1190 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:395" - wire width 1 $1192 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:395" - cell $and $1193 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \fus_cu_wr__rel_o$84 [1] - connect \B \fu_enable [1] - connect \Y $1192 - end - process $group_502 - assign \wrpick_CR_full_cr_i 1'0 - assign \wrpick_CR_full_cr_i $1192 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:398" - wire width 1 \wr_pick$1194 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:399" - wire width 1 $1195 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:399" - cell $and $1196 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wrpick_CR_full_cr_o - connect \B \wrpick_CR_full_cr_en_o - connect \Y $1195 - end - process $group_503 - assign \wr_pick$1194 1'0 - assign \wr_pick$1194 $1195 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire width 1 \wr_pick_dly$1197 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire width 1 \wr_pick_dly$1197$next - process $group_504 - assign \wr_pick_dly$1197$next \wr_pick_dly$1197 - assign \wr_pick_dly$1197$next \wr_pick$1194 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \wr_pick_dly$1197$next 1'0 - end - sync init - update \wr_pick_dly$1197 1'0 - sync posedge \coresync_clk - update \wr_pick_dly$1197 \wr_pick_dly$1197$next - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - wire width 1 $1198 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $not $1199 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_pick_dly$1197 - connect \Y $1198 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - wire width 1 $1200 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $and $1201 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_pick$1194 - connect \B $1198 - connect \Y $1200 - end - process $group_505 - assign \wr_pick_rise$973 1'0 - assign \wr_pick_rise$973 $1200 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:406" - wire width 1 \wp$1202 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" - wire width 1 $1203 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" - cell $and $1204 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_pick$1194 - connect \B \wrpick_CR_full_cr_en_o - connect \Y $1203 - end - process $group_506 - assign \wp$1202 1'0 - assign \wp$1202 $1203 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:405" - wire width 8 \addr_en$1205 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408" - wire width 8 $1206 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408" - cell $mux $1207 - parameter \WIDTH 8 - connect \A 8'00000000 - connect \B \core_core_cr_wr - connect \S \wp$1202 - connect \Y $1206 - end - process $group_507 - assign \addr_en$1205 8'00000000 - assign \addr_en$1205 $1206 - sync init - end - process $group_508 - assign \cr_full_wr__data_i 32'00000000000000000000000000000000 - assign \cr_full_wr__data_i \fus_dest2_o - sync init - end - process $group_509 - assign \cr_full_wr__wen 8'00000000 - assign \cr_full_wr__wen \addr_en$1205 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:390" - wire width 1 \wrflag_alu0_cr_a_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:391" - wire width 1 $1208 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:391" - cell $and $1209 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \fus_cr_a_ok - connect \B \fus_cu_busy_o - connect \Y $1208 - end - process $group_510 - assign \wrflag_alu0_cr_a_1 1'0 - assign \wrflag_alu0_cr_a_1 $1208 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:395" - wire width 1 $1210 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:395" - cell $and $1211 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \fus_cu_wr__rel_o [1] - connect \B \fu_enable [0] - connect \Y $1210 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:395" - wire width 1 $1212 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:395" - cell $and $1213 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \fus_cu_wr__rel_o$84 [2] - connect \B \fu_enable [1] - connect \Y $1212 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:395" - wire width 1 $1214 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:395" - cell $and $1215 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \fus_cu_wr__rel_o$90 [1] - connect \B \fu_enable [4] - connect \Y $1214 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:395" - wire width 1 $1216 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:395" - cell $and $1217 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \fus_cu_wr__rel_o$96 [1] - connect \B \fu_enable [6] - connect \Y $1216 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:395" - wire width 1 $1218 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:395" - cell $and $1219 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \fus_cu_wr__rel_o$99 [1] - connect \B \fu_enable [7] - connect \Y $1218 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:395" - wire width 1 $1220 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:395" - cell $and $1221 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \fus_cu_wr__rel_o$102 [1] - connect \B \fu_enable [8] - connect \Y $1220 - end - process $group_511 - assign \wrpick_CR_cr_a_i 6'000000 - assign \wrpick_CR_cr_a_i [0] $1210 - assign \wrpick_CR_cr_a_i [1] $1212 - assign \wrpick_CR_cr_a_i [2] $1214 - assign \wrpick_CR_cr_a_i [3] $1216 - assign \wrpick_CR_cr_a_i [4] $1218 - assign \wrpick_CR_cr_a_i [5] $1220 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:398" - wire width 1 \wr_pick$1222 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:399" - wire width 1 $1223 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:399" - cell $and $1224 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wrpick_CR_cr_a_o [0] - connect \B \wrpick_CR_cr_a_en_o - connect \Y $1223 - end - process $group_512 - assign \wr_pick$1222 1'0 - assign \wr_pick$1222 $1223 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire width 1 \wr_pick_dly$1225 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire width 1 \wr_pick_dly$1225$next - process $group_513 - assign \wr_pick_dly$1225$next \wr_pick_dly$1225 - assign \wr_pick_dly$1225$next \wr_pick$1222 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \wr_pick_dly$1225$next 1'0 - end - sync init - update \wr_pick_dly$1225 1'0 - sync posedge \coresync_clk - update \wr_pick_dly$1225 \wr_pick_dly$1225$next - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - wire width 1 $1226 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $not $1227 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_pick_dly$1225 - connect \Y $1226 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - wire width 1 $1228 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $and $1229 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_pick$1222 - connect \B $1226 - connect \Y $1228 - end - process $group_514 - assign \wr_pick_rise$954 1'0 - assign \wr_pick_rise$954 $1228 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:406" - wire width 1 \wp$1230 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" - wire width 1 $1231 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" - cell $and $1232 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_pick$1222 - connect \B \wrpick_CR_cr_a_en_o - connect \Y $1231 - end - process $group_515 - assign \wp$1230 1'0 - assign \wp$1230 $1231 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:405" - wire width 16 \addr_en$1233 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:140" - wire width 4 $1234 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:140" - cell $sub $1235 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 4 - connect \A 3'111 - connect \B \core_cr_out - connect \Y $1234 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:140" - wire width 16 $1236 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:140" - cell $sshl $1237 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 16 - connect \A 1'1 - connect \B $1234 - connect \Y $1236 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408" - wire width 16 $1238 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408" - cell $mux $1239 - parameter \WIDTH 16 - connect \A 16'0000000000000000 - connect \B $1236 - connect \S \wp$1230 - connect \Y $1238 - end - process $group_516 - assign \addr_en$1233 16'0000000000000000 - assign \addr_en$1233 $1238 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:390" - wire width 1 \wrflag_cr0_cr_a_2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:391" - wire width 1 $1240 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:391" - cell $and $1241 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \fus_cr_a_ok$113 - connect \B \fus_cu_busy_o$5 - connect \Y $1240 - end - process $group_517 - assign \wrflag_cr0_cr_a_2 1'0 - assign \wrflag_cr0_cr_a_2 $1240 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:398" - wire width 1 \wr_pick$1242 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:399" - wire width 1 $1243 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:399" - cell $and $1244 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wrpick_CR_cr_a_o [1] - connect \B \wrpick_CR_cr_a_en_o - connect \Y $1243 - end - process $group_518 - assign \wr_pick$1242 1'0 - assign \wr_pick$1242 $1243 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire width 1 \wr_pick_dly$1245 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire width 1 \wr_pick_dly$1245$next - process $group_519 - assign \wr_pick_dly$1245$next \wr_pick_dly$1245 - assign \wr_pick_dly$1245$next \wr_pick$1242 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \wr_pick_dly$1245$next 1'0 - end - sync init - update \wr_pick_dly$1245 1'0 - sync posedge \coresync_clk - update \wr_pick_dly$1245 \wr_pick_dly$1245$next - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - wire width 1 $1246 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $not $1247 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_pick_dly$1245 - connect \Y $1246 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - wire width 1 $1248 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $and $1249 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_pick$1242 - connect \B $1246 - connect \Y $1248 - end - process $group_520 - assign \wr_pick_rise$974 1'0 - assign \wr_pick_rise$974 $1248 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:406" - wire width 1 \wp$1250 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" - wire width 1 $1251 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" - cell $and $1252 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_pick$1242 - connect \B \wrpick_CR_cr_a_en_o - connect \Y $1251 - end - process $group_521 - assign \wp$1250 1'0 - assign \wp$1250 $1251 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:405" - wire width 16 \addr_en$1253 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:140" - wire width 4 $1254 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:140" - cell $sub $1255 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 4 - connect \A 3'111 - connect \B \core_cr_out - connect \Y $1254 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:140" - wire width 16 $1256 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:140" - cell $sshl $1257 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 16 - connect \A 1'1 - connect \B $1254 - connect \Y $1256 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408" - wire width 16 $1258 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408" - cell $mux $1259 - parameter \WIDTH 16 - connect \A 16'0000000000000000 - connect \B $1256 - connect \S \wp$1250 - connect \Y $1258 - end - process $group_522 - assign \addr_en$1253 16'0000000000000000 - assign \addr_en$1253 $1258 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:390" - wire width 1 \wrflag_logical0_cr_a_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:391" - wire width 1 $1260 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:391" - cell $and $1261 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \fus_cr_a_ok$114 - connect \B \fus_cu_busy_o$14 - connect \Y $1260 - end - process $group_523 - assign \wrflag_logical0_cr_a_1 1'0 - assign \wrflag_logical0_cr_a_1 $1260 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:398" - wire width 1 \wr_pick$1262 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:399" - wire width 1 $1263 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:399" - cell $and $1264 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wrpick_CR_cr_a_o [2] - connect \B \wrpick_CR_cr_a_en_o - connect \Y $1263 - end - process $group_524 - assign \wr_pick$1262 1'0 - assign \wr_pick$1262 $1263 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire width 1 \wr_pick_dly$1265 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire width 1 \wr_pick_dly$1265$next - process $group_525 - assign \wr_pick_dly$1265$next \wr_pick_dly$1265 - assign \wr_pick_dly$1265$next \wr_pick$1262 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \wr_pick_dly$1265$next 1'0 - end - sync init - update \wr_pick_dly$1265 1'0 - sync posedge \coresync_clk - update \wr_pick_dly$1265 \wr_pick_dly$1265$next - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - wire width 1 $1266 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $not $1267 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_pick_dly$1265 - connect \Y $1266 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - wire width 1 $1268 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $and $1269 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_pick$1262 - connect \B $1266 - connect \Y $1268 - end - process $group_526 - assign \wr_pick_rise$1013 1'0 - assign \wr_pick_rise$1013 $1268 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:406" - wire width 1 \wp$1270 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" - wire width 1 $1271 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" - cell $and $1272 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_pick$1262 - connect \B \wrpick_CR_cr_a_en_o - connect \Y $1271 - end - process $group_527 - assign \wp$1270 1'0 - assign \wp$1270 $1271 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:405" - wire width 16 \addr_en$1273 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:140" - wire width 4 $1274 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:140" - cell $sub $1275 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 4 - connect \A 3'111 - connect \B \core_cr_out - connect \Y $1274 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:140" - wire width 16 $1276 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:140" - cell $sshl $1277 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 16 - connect \A 1'1 - connect \B $1274 - connect \Y $1276 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408" - wire width 16 $1278 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408" - cell $mux $1279 - parameter \WIDTH 16 - connect \A 16'0000000000000000 - connect \B $1276 - connect \S \wp$1270 - connect \Y $1278 - end - process $group_528 - assign \addr_en$1273 16'0000000000000000 - assign \addr_en$1273 $1278 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:390" - wire width 1 \wrflag_div0_cr_a_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:391" - wire width 1 $1280 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:391" - cell $and $1281 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \fus_cr_a_ok$115 - connect \B \fus_cu_busy_o$20 - connect \Y $1280 - end - process $group_529 - assign \wrflag_div0_cr_a_1 1'0 - assign \wrflag_div0_cr_a_1 $1280 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:398" - wire width 1 \wr_pick$1282 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:399" - wire width 1 $1283 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:399" - cell $and $1284 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wrpick_CR_cr_a_o [3] - connect \B \wrpick_CR_cr_a_en_o - connect \Y $1283 - end - process $group_530 - assign \wr_pick$1282 1'0 - assign \wr_pick$1282 $1283 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire width 1 \wr_pick_dly$1285 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire width 1 \wr_pick_dly$1285$next - process $group_531 - assign \wr_pick_dly$1285$next \wr_pick_dly$1285 - assign \wr_pick_dly$1285$next \wr_pick$1282 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \wr_pick_dly$1285$next 1'0 - end - sync init - update \wr_pick_dly$1285 1'0 - sync posedge \coresync_clk - update \wr_pick_dly$1285 \wr_pick_dly$1285$next - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - wire width 1 $1286 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $not $1287 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_pick_dly$1285 - connect \Y $1286 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - wire width 1 $1288 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $and $1289 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_pick$1282 - connect \B $1286 - connect \Y $1288 - end - process $group_532 - assign \wr_pick_rise$1053 1'0 - assign \wr_pick_rise$1053 $1288 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:406" - wire width 1 \wp$1290 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" - wire width 1 $1291 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" - cell $and $1292 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_pick$1282 - connect \B \wrpick_CR_cr_a_en_o - connect \Y $1291 - end - process $group_533 - assign \wp$1290 1'0 - assign \wp$1290 $1291 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:405" - wire width 16 \addr_en$1293 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:140" - wire width 4 $1294 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:140" - cell $sub $1295 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 4 - connect \A 3'111 - connect \B \core_cr_out - connect \Y $1294 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:140" - wire width 16 $1296 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:140" - cell $sshl $1297 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 16 - connect \A 1'1 - connect \B $1294 - connect \Y $1296 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408" - wire width 16 $1298 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408" - cell $mux $1299 - parameter \WIDTH 16 - connect \A 16'0000000000000000 - connect \B $1296 - connect \S \wp$1290 - connect \Y $1298 - end - process $group_534 - assign \addr_en$1293 16'0000000000000000 - assign \addr_en$1293 $1298 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:390" - wire width 1 \wrflag_mul0_cr_a_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:391" - wire width 1 $1300 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:391" - cell $and $1301 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \fus_cr_a_ok$116 - connect \B \fus_cu_busy_o$23 - connect \Y $1300 - end - process $group_535 - assign \wrflag_mul0_cr_a_1 1'0 - assign \wrflag_mul0_cr_a_1 $1300 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:398" - wire width 1 \wr_pick$1302 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:399" - wire width 1 $1303 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:399" - cell $and $1304 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wrpick_CR_cr_a_o [4] - connect \B \wrpick_CR_cr_a_en_o - connect \Y $1303 - end - process $group_536 - assign \wr_pick$1302 1'0 - assign \wr_pick$1302 $1303 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire width 1 \wr_pick_dly$1305 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire width 1 \wr_pick_dly$1305$next - process $group_537 - assign \wr_pick_dly$1305$next \wr_pick_dly$1305 - assign \wr_pick_dly$1305$next \wr_pick$1302 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \wr_pick_dly$1305$next 1'0 - end - sync init - update \wr_pick_dly$1305 1'0 - sync posedge \coresync_clk - update \wr_pick_dly$1305 \wr_pick_dly$1305$next - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - wire width 1 $1306 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $not $1307 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_pick_dly$1305 - connect \Y $1306 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - wire width 1 $1308 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $and $1309 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_pick$1302 - connect \B $1306 - connect \Y $1308 - end - process $group_538 - assign \wr_pick_rise$1073 1'0 - assign \wr_pick_rise$1073 $1308 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:406" - wire width 1 \wp$1310 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" - wire width 1 $1311 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" - cell $and $1312 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_pick$1302 - connect \B \wrpick_CR_cr_a_en_o - connect \Y $1311 - end - process $group_539 - assign \wp$1310 1'0 - assign \wp$1310 $1311 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:405" - wire width 16 \addr_en$1313 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:140" - wire width 4 $1314 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:140" - cell $sub $1315 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 4 - connect \A 3'111 - connect \B \core_cr_out - connect \Y $1314 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:140" - wire width 16 $1316 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:140" - cell $sshl $1317 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 16 - connect \A 1'1 - connect \B $1314 - connect \Y $1316 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408" - wire width 16 $1318 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408" - cell $mux $1319 - parameter \WIDTH 16 - connect \A 16'0000000000000000 - connect \B $1316 - connect \S \wp$1310 - connect \Y $1318 - end - process $group_540 - assign \addr_en$1313 16'0000000000000000 - assign \addr_en$1313 $1318 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:390" - wire width 1 \wrflag_shiftrot0_cr_a_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:391" - wire width 1 $1320 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:391" - cell $and $1321 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \fus_cr_a_ok$117 - connect \B \fus_cu_busy_o$26 - connect \Y $1320 - end - process $group_541 - assign \wrflag_shiftrot0_cr_a_1 1'0 - assign \wrflag_shiftrot0_cr_a_1 $1320 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:398" - wire width 1 \wr_pick$1322 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:399" - wire width 1 $1323 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:399" - cell $and $1324 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wrpick_CR_cr_a_o [5] - connect \B \wrpick_CR_cr_a_en_o - connect \Y $1323 - end - process $group_542 - assign \wr_pick$1322 1'0 - assign \wr_pick$1322 $1323 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire width 1 \wr_pick_dly$1325 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire width 1 \wr_pick_dly$1325$next - process $group_543 - assign \wr_pick_dly$1325$next \wr_pick_dly$1325 - assign \wr_pick_dly$1325$next \wr_pick$1322 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \wr_pick_dly$1325$next 1'0 - end - sync init - update \wr_pick_dly$1325 1'0 - sync posedge \coresync_clk - update \wr_pick_dly$1325 \wr_pick_dly$1325$next - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - wire width 1 $1326 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $not $1327 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_pick_dly$1325 - connect \Y $1326 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - wire width 1 $1328 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $and $1329 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_pick$1322 - connect \B $1326 - connect \Y $1328 - end - process $group_544 - assign \wr_pick_rise$1093 1'0 - assign \wr_pick_rise$1093 $1328 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:406" - wire width 1 \wp$1330 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" - wire width 1 $1331 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" - cell $and $1332 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_pick$1322 - connect \B \wrpick_CR_cr_a_en_o - connect \Y $1331 - end - process $group_545 - assign \wp$1330 1'0 - assign \wp$1330 $1331 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:405" - wire width 16 \addr_en$1333 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:140" - wire width 4 $1334 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:140" - cell $sub $1335 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 4 - connect \A 3'111 - connect \B \core_cr_out - connect \Y $1334 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:140" - wire width 16 $1336 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_regspec_map.py:140" - cell $sshl $1337 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 16 - connect \A 1'1 - connect \B $1334 - connect \Y $1336 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408" - wire width 16 $1338 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408" - cell $mux $1339 - parameter \WIDTH 16 - connect \A 16'0000000000000000 - connect \B $1336 - connect \S \wp$1330 - connect \Y $1338 - end - process $group_546 - assign \addr_en$1333 16'0000000000000000 - assign \addr_en$1333 $1338 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - wire width 4 $1340 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $or $1341 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A \fus_dest3_o - connect \B \fus_dest2_o$119 - connect \Y $1340 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - wire width 4 $1342 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - cell $or $1343 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A \fus_dest2_o$118 - connect \B $1340 - connect \Y $1342 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - wire width 4 $1344 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $or $1345 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A \fus_dest2_o$121 - connect \B \fus_dest2_o$122 - connect \Y $1344 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - wire width 4 $1346 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - cell $or $1347 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A \fus_dest2_o$120 - connect \B $1344 - connect \Y $1346 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - wire width 4 $1348 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - cell $or $1349 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 4 - parameter \Y_WIDTH 4 - connect \A $1342 - connect \B $1346 - connect \Y $1348 - end - process $group_547 - assign \cr_data_i 4'0000 - assign \cr_data_i $1348 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - wire width 16 $1350 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - wire width 16 $1351 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $or $1352 - parameter \A_SIGNED 0 - parameter \A_WIDTH 16 - parameter \B_SIGNED 0 - parameter \B_WIDTH 16 - parameter \Y_WIDTH 16 - connect \A \addr_en$1253 - connect \B \addr_en$1273 - connect \Y $1351 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - wire width 16 $1353 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - cell $or $1354 - parameter \A_SIGNED 0 - parameter \A_WIDTH 16 - parameter \B_SIGNED 0 - parameter \B_WIDTH 16 - parameter \Y_WIDTH 16 - connect \A \addr_en$1233 - connect \B $1351 - connect \Y $1353 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - wire width 16 $1355 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $or $1356 - parameter \A_SIGNED 0 - parameter \A_WIDTH 16 - parameter \B_SIGNED 0 - parameter \B_WIDTH 16 - parameter \Y_WIDTH 16 - connect \A \addr_en$1313 - connect \B \addr_en$1333 - connect \Y $1355 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - wire width 16 $1357 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - cell $or $1358 - parameter \A_SIGNED 0 - parameter \A_WIDTH 16 - parameter \B_SIGNED 0 - parameter \B_WIDTH 16 - parameter \Y_WIDTH 16 - connect \A \addr_en$1293 - connect \B $1355 - connect \Y $1357 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - wire width 16 $1359 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - cell $or $1360 - parameter \A_SIGNED 0 - parameter \A_WIDTH 16 - parameter \B_SIGNED 0 - parameter \B_WIDTH 16 - parameter \Y_WIDTH 16 - connect \A $1353 - connect \B $1357 - connect \Y $1359 - end - connect $1350 $1359 - process $group_548 - assign \cr_wen 8'00000000 - assign \cr_wen $1350 [7:0] - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:390" - wire width 1 \wrflag_alu0_xer_ca_2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:391" - wire width 1 $1361 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:391" - cell $and $1362 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \fus_xer_ca_ok - connect \B \fus_cu_busy_o - connect \Y $1361 - end - process $group_549 - assign \wrflag_alu0_xer_ca_2 1'0 - assign \wrflag_alu0_xer_ca_2 $1361 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:395" - wire width 1 $1363 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:395" - cell $and $1364 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \fus_cu_wr__rel_o [2] - connect \B \fu_enable [0] - connect \Y $1363 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:395" - wire width 1 $1365 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:395" - cell $and $1366 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \fus_cu_wr__rel_o$93 [5] - connect \B \fu_enable [5] - connect \Y $1365 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:395" - wire width 1 $1367 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:395" - cell $and $1368 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \fus_cu_wr__rel_o$102 [2] - connect \B \fu_enable [8] - connect \Y $1367 - end - process $group_550 - assign \wrpick_XER_xer_ca_i 3'000 - assign \wrpick_XER_xer_ca_i [0] $1363 - assign \wrpick_XER_xer_ca_i [1] $1365 - assign \wrpick_XER_xer_ca_i [2] $1367 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:398" - wire width 1 \wr_pick$1369 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:399" - wire width 1 $1370 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:399" - cell $and $1371 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wrpick_XER_xer_ca_o [0] - connect \B \wrpick_XER_xer_ca_en_o - connect \Y $1370 - end - process $group_551 - assign \wr_pick$1369 1'0 - assign \wr_pick$1369 $1370 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire width 1 \wr_pick_dly$1372 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire width 1 \wr_pick_dly$1372$next - process $group_552 - assign \wr_pick_dly$1372$next \wr_pick_dly$1372 - assign \wr_pick_dly$1372$next \wr_pick$1369 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \wr_pick_dly$1372$next 1'0 - end - sync init - update \wr_pick_dly$1372 1'0 - sync posedge \coresync_clk - update \wr_pick_dly$1372 \wr_pick_dly$1372$next - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - wire width 1 $1373 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $not $1374 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_pick_dly$1372 - connect \Y $1373 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - wire width 1 $1375 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $and $1376 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_pick$1369 - connect \B $1373 - connect \Y $1375 - end - process $group_553 - assign \wr_pick_rise$955 1'0 - assign \wr_pick_rise$955 $1375 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:406" - wire width 1 \wp$1377 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" - wire width 1 $1378 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" - cell $and $1379 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_pick$1369 - connect \B \wrpick_XER_xer_ca_en_o - connect \Y $1378 - end - process $group_554 - assign \wp$1377 1'0 - assign \wp$1377 $1378 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:405" - wire width 2 \addr_en$1380 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408" - wire width 2 $1381 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408" - cell $mux $1382 - parameter \WIDTH 2 - connect \A 2'00 - connect \B 2'10 - connect \S \wp$1377 - connect \Y $1381 - end - process $group_555 - assign \addr_en$1380 2'00 - assign \addr_en$1380 $1381 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:390" - wire width 1 \wrflag_spr0_xer_ca_5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:391" - wire width 1 $1383 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:391" - cell $and $1384 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \fus_xer_ca_ok$123 - connect \B \fus_cu_busy_o$17 - connect \Y $1383 - end - process $group_556 - assign \wrflag_spr0_xer_ca_5 1'0 - assign \wrflag_spr0_xer_ca_5 $1383 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:398" - wire width 1 \wr_pick$1385 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:399" - wire width 1 $1386 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:399" - cell $and $1387 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wrpick_XER_xer_ca_o [1] - connect \B \wrpick_XER_xer_ca_en_o - connect \Y $1386 - end - process $group_557 - assign \wr_pick$1385 1'0 - assign \wr_pick$1385 $1386 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire width 1 \wr_pick_dly$1388 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire width 1 \wr_pick_dly$1388$next - process $group_558 - assign \wr_pick_dly$1388$next \wr_pick_dly$1388 - assign \wr_pick_dly$1388$next \wr_pick$1385 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \wr_pick_dly$1388$next 1'0 - end - sync init - update \wr_pick_dly$1388 1'0 - sync posedge \coresync_clk - update \wr_pick_dly$1388 \wr_pick_dly$1388$next - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - wire width 1 $1389 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $not $1390 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_pick_dly$1388 - connect \Y $1389 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - wire width 1 $1391 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $and $1392 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_pick$1385 - connect \B $1389 - connect \Y $1391 - end - process $group_559 - assign \wr_pick_rise$1031 1'0 - assign \wr_pick_rise$1031 $1391 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:406" - wire width 1 \wp$1393 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" - wire width 1 $1394 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" - cell $and $1395 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_pick$1385 - connect \B \wrpick_XER_xer_ca_en_o - connect \Y $1394 - end - process $group_560 - assign \wp$1393 1'0 - assign \wp$1393 $1394 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:405" - wire width 2 \addr_en$1396 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408" - wire width 2 $1397 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408" - cell $mux $1398 - parameter \WIDTH 2 - connect \A 2'00 - connect \B 2'10 - connect \S \wp$1393 - connect \Y $1397 - end - process $group_561 - assign \addr_en$1396 2'00 - assign \addr_en$1396 $1397 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:390" - wire width 1 \wrflag_shiftrot0_xer_ca_2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:391" - wire width 1 $1399 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:391" - cell $and $1400 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \fus_xer_ca_ok$124 - connect \B \fus_cu_busy_o$26 - connect \Y $1399 - end - process $group_562 - assign \wrflag_shiftrot0_xer_ca_2 1'0 - assign \wrflag_shiftrot0_xer_ca_2 $1399 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:398" - wire width 1 \wr_pick$1401 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:399" - wire width 1 $1402 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:399" - cell $and $1403 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wrpick_XER_xer_ca_o [2] - connect \B \wrpick_XER_xer_ca_en_o - connect \Y $1402 - end - process $group_563 - assign \wr_pick$1401 1'0 - assign \wr_pick$1401 $1402 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire width 1 \wr_pick_dly$1404 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire width 1 \wr_pick_dly$1404$next - process $group_564 - assign \wr_pick_dly$1404$next \wr_pick_dly$1404 - assign \wr_pick_dly$1404$next \wr_pick$1401 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \wr_pick_dly$1404$next 1'0 - end - sync init - update \wr_pick_dly$1404 1'0 - sync posedge \coresync_clk - update \wr_pick_dly$1404 \wr_pick_dly$1404$next - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - wire width 1 $1405 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $not $1406 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_pick_dly$1404 - connect \Y $1405 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - wire width 1 $1407 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $and $1408 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_pick$1401 - connect \B $1405 - connect \Y $1407 - end - process $group_565 - assign \wr_pick_rise$1094 1'0 - assign \wr_pick_rise$1094 $1407 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:406" - wire width 1 \wp$1409 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" - wire width 1 $1410 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" - cell $and $1411 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_pick$1401 - connect \B \wrpick_XER_xer_ca_en_o - connect \Y $1410 - end - process $group_566 - assign \wp$1409 1'0 - assign \wp$1409 $1410 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:405" - wire width 2 \addr_en$1412 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408" - wire width 2 $1413 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408" - cell $mux $1414 - parameter \WIDTH 2 - connect \A 2'00 - connect \B 2'10 - connect \S \wp$1409 - connect \Y $1413 - end - process $group_567 - assign \addr_en$1412 2'00 - assign \addr_en$1412 $1413 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - wire width 2 $1415 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $or $1416 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 2 - connect \A \fus_dest6_o - connect \B \fus_dest3_o$126 - connect \Y $1415 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - wire width 2 $1417 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - cell $or $1418 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 2 - connect \A \fus_dest3_o$125 - connect \B $1415 - connect \Y $1417 - end - process $group_568 - assign \xer_data_i 2'00 - assign \xer_data_i $1417 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - wire width 3 $1419 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - wire width 2 $1420 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $or $1421 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 2 - connect \A \addr_en$1396 - connect \B \addr_en$1412 - connect \Y $1420 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - wire width 2 $1422 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - cell $or $1423 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 2 - connect \A \addr_en$1380 - connect \B $1420 - connect \Y $1422 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - cell $pos $1424 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \Y_WIDTH 3 - connect \A $1422 - connect \Y $1419 - end - process $group_569 - assign \xer_wen 3'000 - assign \xer_wen $1419 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:390" - wire width 1 \wrflag_alu0_xer_ov_3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:391" - wire width 1 $1425 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:391" - cell $and $1426 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \fus_xer_ov_ok - connect \B \fus_cu_busy_o - connect \Y $1425 - end - process $group_570 - assign \wrflag_alu0_xer_ov_3 1'0 - assign \wrflag_alu0_xer_ov_3 $1425 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:395" - wire width 1 $1427 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:395" - cell $and $1428 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \fus_cu_wr__rel_o [3] - connect \B \fu_enable [0] - connect \Y $1427 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:395" - wire width 1 $1429 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:395" - cell $and $1430 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \fus_cu_wr__rel_o$93 [4] - connect \B \fu_enable [5] - connect \Y $1429 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:395" - wire width 1 $1431 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:395" - cell $and $1432 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \fus_cu_wr__rel_o$96 [2] - connect \B \fu_enable [6] - connect \Y $1431 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:395" - wire width 1 $1433 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:395" - cell $and $1434 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \fus_cu_wr__rel_o$99 [2] - connect \B \fu_enable [7] - connect \Y $1433 - end - process $group_571 - assign \wrpick_XER_xer_ov_i 4'0000 - assign \wrpick_XER_xer_ov_i [0] $1427 - assign \wrpick_XER_xer_ov_i [1] $1429 - assign \wrpick_XER_xer_ov_i [2] $1431 - assign \wrpick_XER_xer_ov_i [3] $1433 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:398" - wire width 1 \wr_pick$1435 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:399" - wire width 1 $1436 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:399" - cell $and $1437 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wrpick_XER_xer_ov_o [0] - connect \B \wrpick_XER_xer_ov_en_o - connect \Y $1436 - end - process $group_572 - assign \wr_pick$1435 1'0 - assign \wr_pick$1435 $1436 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire width 1 \wr_pick_dly$1438 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire width 1 \wr_pick_dly$1438$next - process $group_573 - assign \wr_pick_dly$1438$next \wr_pick_dly$1438 - assign \wr_pick_dly$1438$next \wr_pick$1435 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \wr_pick_dly$1438$next 1'0 - end - sync init - update \wr_pick_dly$1438 1'0 - sync posedge \coresync_clk - update \wr_pick_dly$1438 \wr_pick_dly$1438$next - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - wire width 1 $1439 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $not $1440 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_pick_dly$1438 - connect \Y $1439 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - wire width 1 $1441 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $and $1442 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_pick$1435 - connect \B $1439 - connect \Y $1441 - end - process $group_574 - assign \wr_pick_rise$956 1'0 - assign \wr_pick_rise$956 $1441 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:406" - wire width 1 \wp$1443 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" - wire width 1 $1444 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" - cell $and $1445 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_pick$1435 - connect \B \wrpick_XER_xer_ov_en_o - connect \Y $1444 - end - process $group_575 - assign \wp$1443 1'0 - assign \wp$1443 $1444 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:405" - wire width 3 \addr_en$1446 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408" - wire width 3 $1447 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408" - cell $mux $1448 - parameter \WIDTH 3 - connect \A 3'000 - connect \B 3'100 - connect \S \wp$1443 - connect \Y $1447 - end - process $group_576 - assign \addr_en$1446 3'000 - assign \addr_en$1446 $1447 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:390" - wire width 1 \wrflag_spr0_xer_ov_4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:391" - wire width 1 $1449 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:391" - cell $and $1450 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \fus_xer_ov_ok$127 - connect \B \fus_cu_busy_o$17 - connect \Y $1449 - end - process $group_577 - assign \wrflag_spr0_xer_ov_4 1'0 - assign \wrflag_spr0_xer_ov_4 $1449 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:398" - wire width 1 \wr_pick$1451 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:399" - wire width 1 $1452 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:399" - cell $and $1453 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wrpick_XER_xer_ov_o [1] - connect \B \wrpick_XER_xer_ov_en_o - connect \Y $1452 - end - process $group_578 - assign \wr_pick$1451 1'0 - assign \wr_pick$1451 $1452 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire width 1 \wr_pick_dly$1454 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire width 1 \wr_pick_dly$1454$next - process $group_579 - assign \wr_pick_dly$1454$next \wr_pick_dly$1454 - assign \wr_pick_dly$1454$next \wr_pick$1451 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \wr_pick_dly$1454$next 1'0 - end - sync init - update \wr_pick_dly$1454 1'0 - sync posedge \coresync_clk - update \wr_pick_dly$1454 \wr_pick_dly$1454$next - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - wire width 1 $1455 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $not $1456 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_pick_dly$1454 - connect \Y $1455 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - wire width 1 $1457 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $and $1458 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_pick$1451 - connect \B $1455 - connect \Y $1457 - end - process $group_580 - assign \wr_pick_rise$1032 1'0 - assign \wr_pick_rise$1032 $1457 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:406" - wire width 1 \wp$1459 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" - wire width 1 $1460 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" - cell $and $1461 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_pick$1451 - connect \B \wrpick_XER_xer_ov_en_o - connect \Y $1460 - end - process $group_581 - assign \wp$1459 1'0 - assign \wp$1459 $1460 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:405" - wire width 3 \addr_en$1462 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408" - wire width 3 $1463 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408" - cell $mux $1464 - parameter \WIDTH 3 - connect \A 3'000 - connect \B 3'100 - connect \S \wp$1459 - connect \Y $1463 - end - process $group_582 - assign \addr_en$1462 3'000 - assign \addr_en$1462 $1463 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:390" - wire width 1 \wrflag_div0_xer_ov_2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:391" - wire width 1 $1465 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:391" - cell $and $1466 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \fus_xer_ov_ok$128 - connect \B \fus_cu_busy_o$20 - connect \Y $1465 - end - process $group_583 - assign \wrflag_div0_xer_ov_2 1'0 - assign \wrflag_div0_xer_ov_2 $1465 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:398" - wire width 1 \wr_pick$1467 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:399" - wire width 1 $1468 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:399" - cell $and $1469 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wrpick_XER_xer_ov_o [2] - connect \B \wrpick_XER_xer_ov_en_o - connect \Y $1468 - end - process $group_584 - assign \wr_pick$1467 1'0 - assign \wr_pick$1467 $1468 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire width 1 \wr_pick_dly$1470 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire width 1 \wr_pick_dly$1470$next - process $group_585 - assign \wr_pick_dly$1470$next \wr_pick_dly$1470 - assign \wr_pick_dly$1470$next \wr_pick$1467 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \wr_pick_dly$1470$next 1'0 - end - sync init - update \wr_pick_dly$1470 1'0 - sync posedge \coresync_clk - update \wr_pick_dly$1470 \wr_pick_dly$1470$next - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - wire width 1 $1471 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $not $1472 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_pick_dly$1470 - connect \Y $1471 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - wire width 1 $1473 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $and $1474 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_pick$1467 - connect \B $1471 - connect \Y $1473 - end - process $group_586 - assign \wr_pick_rise$1054 1'0 - assign \wr_pick_rise$1054 $1473 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:406" - wire width 1 \wp$1475 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" - wire width 1 $1476 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" - cell $and $1477 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_pick$1467 - connect \B \wrpick_XER_xer_ov_en_o - connect \Y $1476 - end - process $group_587 - assign \wp$1475 1'0 - assign \wp$1475 $1476 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:405" - wire width 3 \addr_en$1478 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408" - wire width 3 $1479 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408" - cell $mux $1480 - parameter \WIDTH 3 - connect \A 3'000 - connect \B 3'100 - connect \S \wp$1475 - connect \Y $1479 - end - process $group_588 - assign \addr_en$1478 3'000 - assign \addr_en$1478 $1479 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:390" - wire width 1 \wrflag_mul0_xer_ov_2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:391" - wire width 1 $1481 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:391" - cell $and $1482 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \fus_xer_ov_ok$129 - connect \B \fus_cu_busy_o$23 - connect \Y $1481 - end - process $group_589 - assign \wrflag_mul0_xer_ov_2 1'0 - assign \wrflag_mul0_xer_ov_2 $1481 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:398" - wire width 1 \wr_pick$1483 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:399" - wire width 1 $1484 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:399" - cell $and $1485 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wrpick_XER_xer_ov_o [3] - connect \B \wrpick_XER_xer_ov_en_o - connect \Y $1484 - end - process $group_590 - assign \wr_pick$1483 1'0 - assign \wr_pick$1483 $1484 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire width 1 \wr_pick_dly$1486 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire width 1 \wr_pick_dly$1486$next - process $group_591 - assign \wr_pick_dly$1486$next \wr_pick_dly$1486 - assign \wr_pick_dly$1486$next \wr_pick$1483 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \wr_pick_dly$1486$next 1'0 - end - sync init - update \wr_pick_dly$1486 1'0 - sync posedge \coresync_clk - update \wr_pick_dly$1486 \wr_pick_dly$1486$next - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - wire width 1 $1487 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $not $1488 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_pick_dly$1486 - connect \Y $1487 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - wire width 1 $1489 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $and $1490 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_pick$1483 - connect \B $1487 - connect \Y $1489 - end - process $group_592 - assign \wr_pick_rise$1074 1'0 - assign \wr_pick_rise$1074 $1489 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:406" - wire width 1 \wp$1491 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" - wire width 1 $1492 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" - cell $and $1493 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_pick$1483 - connect \B \wrpick_XER_xer_ov_en_o - connect \Y $1492 - end - process $group_593 - assign \wp$1491 1'0 - assign \wp$1491 $1492 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:405" - wire width 3 \addr_en$1494 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408" - wire width 3 $1495 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408" - cell $mux $1496 - parameter \WIDTH 3 - connect \A 3'000 - connect \B 3'100 - connect \S \wp$1491 - connect \Y $1495 - end - process $group_594 - assign \addr_en$1494 3'000 - assign \addr_en$1494 $1495 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - wire width 2 $1497 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $or $1498 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 2 - connect \A \fus_dest4_o - connect \B \fus_dest5_o - connect \Y $1497 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - wire width 2 $1499 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $or $1500 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 2 - connect \A \fus_dest3_o$130 - connect \B \fus_dest3_o$131 - connect \Y $1499 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - wire width 2 $1501 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - cell $or $1502 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 2 - connect \A $1497 - connect \B $1499 - connect \Y $1501 - end - process $group_595 - assign \xer_data_i$154 2'00 - assign \xer_data_i$154 $1501 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - wire width 3 $1503 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $or $1504 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A \addr_en$1446 - connect \B \addr_en$1462 - connect \Y $1503 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - wire width 3 $1505 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $or $1506 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A \addr_en$1478 - connect \B \addr_en$1494 - connect \Y $1505 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - wire width 3 $1507 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - cell $or $1508 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A $1503 - connect \B $1505 - connect \Y $1507 - end - process $group_596 - assign \xer_wen$155 3'000 - assign \xer_wen$155 $1507 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:390" - wire width 1 \wrflag_alu0_xer_so_4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:391" - wire width 1 $1509 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:391" - cell $and $1510 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \fus_xer_so_ok - connect \B \fus_cu_busy_o - connect \Y $1509 - end - process $group_597 - assign \wrflag_alu0_xer_so_4 1'0 - assign \wrflag_alu0_xer_so_4 $1509 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:395" - wire width 1 $1511 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:395" - cell $and $1512 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \fus_cu_wr__rel_o [4] - connect \B \fu_enable [0] - connect \Y $1511 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:395" - wire width 1 $1513 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:395" - cell $and $1514 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \fus_cu_wr__rel_o$93 [3] - connect \B \fu_enable [5] - connect \Y $1513 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:395" - wire width 1 $1515 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:395" - cell $and $1516 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \fus_cu_wr__rel_o$96 [3] - connect \B \fu_enable [6] - connect \Y $1515 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:395" - wire width 1 $1517 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:395" - cell $and $1518 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \fus_cu_wr__rel_o$99 [3] - connect \B \fu_enable [7] - connect \Y $1517 - end - process $group_598 - assign \wrpick_XER_xer_so_i 4'0000 - assign \wrpick_XER_xer_so_i [0] $1511 - assign \wrpick_XER_xer_so_i [1] $1513 - assign \wrpick_XER_xer_so_i [2] $1515 - assign \wrpick_XER_xer_so_i [3] $1517 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:398" - wire width 1 \wr_pick$1519 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:399" - wire width 1 $1520 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:399" - cell $and $1521 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wrpick_XER_xer_so_o [0] - connect \B \wrpick_XER_xer_so_en_o - connect \Y $1520 - end - process $group_599 - assign \wr_pick$1519 1'0 - assign \wr_pick$1519 $1520 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire width 1 \wr_pick_dly$1522 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire width 1 \wr_pick_dly$1522$next - process $group_600 - assign \wr_pick_dly$1522$next \wr_pick_dly$1522 - assign \wr_pick_dly$1522$next \wr_pick$1519 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \wr_pick_dly$1522$next 1'0 - end - sync init - update \wr_pick_dly$1522 1'0 - sync posedge \coresync_clk - update \wr_pick_dly$1522 \wr_pick_dly$1522$next - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - wire width 1 $1523 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $not $1524 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_pick_dly$1522 - connect \Y $1523 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - wire width 1 $1525 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $and $1526 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_pick$1519 - connect \B $1523 - connect \Y $1525 - end - process $group_601 - assign \wr_pick_rise$957 1'0 - assign \wr_pick_rise$957 $1525 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:406" - wire width 1 \wp$1527 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" - wire width 1 $1528 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" - cell $and $1529 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_pick$1519 - connect \B \wrpick_XER_xer_so_en_o - connect \Y $1528 - end - process $group_602 - assign \wp$1527 1'0 - assign \wp$1527 $1528 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:405" - wire width 1 \addr_en$1530 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408" - wire width 1 $1531 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408" - cell $mux $1532 - parameter \WIDTH 1 - connect \A 1'0 - connect \B 1'1 - connect \S \wp$1527 - connect \Y $1531 - end - process $group_603 - assign \addr_en$1530 1'0 - assign \addr_en$1530 $1531 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:390" - wire width 1 \wrflag_spr0_xer_so_3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:391" - wire width 1 $1533 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:391" - cell $and $1534 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \fus_xer_so_ok$132 - connect \B \fus_cu_busy_o$17 - connect \Y $1533 - end - process $group_604 - assign \wrflag_spr0_xer_so_3 1'0 - assign \wrflag_spr0_xer_so_3 $1533 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:398" - wire width 1 \wr_pick$1535 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:399" - wire width 1 $1536 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:399" - cell $and $1537 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wrpick_XER_xer_so_o [1] - connect \B \wrpick_XER_xer_so_en_o - connect \Y $1536 - end - process $group_605 - assign \wr_pick$1535 1'0 - assign \wr_pick$1535 $1536 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire width 1 \wr_pick_dly$1538 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire width 1 \wr_pick_dly$1538$next - process $group_606 - assign \wr_pick_dly$1538$next \wr_pick_dly$1538 - assign \wr_pick_dly$1538$next \wr_pick$1535 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \wr_pick_dly$1538$next 1'0 - end - sync init - update \wr_pick_dly$1538 1'0 - sync posedge \coresync_clk - update \wr_pick_dly$1538 \wr_pick_dly$1538$next - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - wire width 1 $1539 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $not $1540 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_pick_dly$1538 - connect \Y $1539 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - wire width 1 $1541 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $and $1542 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_pick$1535 - connect \B $1539 - connect \Y $1541 - end - process $group_607 - assign \wr_pick_rise$1033 1'0 - assign \wr_pick_rise$1033 $1541 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:406" - wire width 1 \wp$1543 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" - wire width 1 $1544 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" - cell $and $1545 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_pick$1535 - connect \B \wrpick_XER_xer_so_en_o - connect \Y $1544 - end - process $group_608 - assign \wp$1543 1'0 - assign \wp$1543 $1544 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:405" - wire width 1 \addr_en$1546 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408" - wire width 1 $1547 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408" - cell $mux $1548 - parameter \WIDTH 1 - connect \A 1'0 - connect \B 1'1 - connect \S \wp$1543 - connect \Y $1547 - end - process $group_609 - assign \addr_en$1546 1'0 - assign \addr_en$1546 $1547 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:390" - wire width 1 \wrflag_div0_xer_so_3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:391" - wire width 1 $1549 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:391" - cell $and $1550 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \fus_xer_so_ok$133 - connect \B \fus_cu_busy_o$20 - connect \Y $1549 - end - process $group_610 - assign \wrflag_div0_xer_so_3 1'0 - assign \wrflag_div0_xer_so_3 $1549 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:398" - wire width 1 \wr_pick$1551 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:399" - wire width 1 $1552 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:399" - cell $and $1553 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wrpick_XER_xer_so_o [2] - connect \B \wrpick_XER_xer_so_en_o - connect \Y $1552 - end - process $group_611 - assign \wr_pick$1551 1'0 - assign \wr_pick$1551 $1552 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire width 1 \wr_pick_dly$1554 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire width 1 \wr_pick_dly$1554$next - process $group_612 - assign \wr_pick_dly$1554$next \wr_pick_dly$1554 - assign \wr_pick_dly$1554$next \wr_pick$1551 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \wr_pick_dly$1554$next 1'0 - end - sync init - update \wr_pick_dly$1554 1'0 - sync posedge \coresync_clk - update \wr_pick_dly$1554 \wr_pick_dly$1554$next - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - wire width 1 $1555 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $not $1556 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_pick_dly$1554 - connect \Y $1555 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - wire width 1 $1557 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $and $1558 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_pick$1551 - connect \B $1555 - connect \Y $1557 - end - process $group_613 - assign \wr_pick_rise$1055 1'0 - assign \wr_pick_rise$1055 $1557 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:406" - wire width 1 \wp$1559 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" - wire width 1 $1560 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" - cell $and $1561 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_pick$1551 - connect \B \wrpick_XER_xer_so_en_o - connect \Y $1560 - end - process $group_614 - assign \wp$1559 1'0 - assign \wp$1559 $1560 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:405" - wire width 1 \addr_en$1562 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408" - wire width 1 $1563 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408" - cell $mux $1564 - parameter \WIDTH 1 - connect \A 1'0 - connect \B 1'1 - connect \S \wp$1559 - connect \Y $1563 - end - process $group_615 - assign \addr_en$1562 1'0 - assign \addr_en$1562 $1563 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:390" - wire width 1 \wrflag_mul0_xer_so_3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:391" - wire width 1 $1565 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:391" - cell $and $1566 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \fus_xer_so_ok$134 - connect \B \fus_cu_busy_o$23 - connect \Y $1565 - end - process $group_616 - assign \wrflag_mul0_xer_so_3 1'0 - assign \wrflag_mul0_xer_so_3 $1565 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:398" - wire width 1 \wr_pick$1567 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:399" - wire width 1 $1568 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:399" - cell $and $1569 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wrpick_XER_xer_so_o [3] - connect \B \wrpick_XER_xer_so_en_o - connect \Y $1568 - end - process $group_617 - assign \wr_pick$1567 1'0 - assign \wr_pick$1567 $1568 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire width 1 \wr_pick_dly$1570 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire width 1 \wr_pick_dly$1570$next - process $group_618 - assign \wr_pick_dly$1570$next \wr_pick_dly$1570 - assign \wr_pick_dly$1570$next \wr_pick$1567 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \wr_pick_dly$1570$next 1'0 - end - sync init - update \wr_pick_dly$1570 1'0 - sync posedge \coresync_clk - update \wr_pick_dly$1570 \wr_pick_dly$1570$next - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - wire width 1 $1571 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $not $1572 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_pick_dly$1570 - connect \Y $1571 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - wire width 1 $1573 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $and $1574 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_pick$1567 - connect \B $1571 - connect \Y $1573 - end - process $group_619 - assign \wr_pick_rise$1075 1'0 - assign \wr_pick_rise$1075 $1573 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:406" - wire width 1 \wp$1575 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" - wire width 1 $1576 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" - cell $and $1577 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_pick$1567 - connect \B \wrpick_XER_xer_so_en_o - connect \Y $1576 - end - process $group_620 - assign \wp$1575 1'0 - assign \wp$1575 $1576 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:405" - wire width 1 \addr_en$1578 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408" - wire width 1 $1579 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408" - cell $mux $1580 - parameter \WIDTH 1 - connect \A 1'0 - connect \B 1'1 - connect \S \wp$1575 - connect \Y $1579 - end - process $group_621 - assign \addr_en$1578 1'0 - assign \addr_en$1578 $1579 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - wire width 2 $1581 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - wire width 1 $1582 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $or $1583 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \fus_dest5_o$135 - connect \B \fus_dest4_o$136 - connect \Y $1582 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - wire width 1 $1584 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $or $1585 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \fus_dest4_o$137 - connect \B \fus_dest4_o$138 - connect \Y $1584 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - wire width 1 $1586 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - cell $or $1587 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $1582 - connect \B $1584 - connect \Y $1586 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - cell $pos $1588 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 2 - connect \A $1586 - connect \Y $1581 - end - process $group_622 - assign \xer_data_i$156 2'00 - assign \xer_data_i$156 $1581 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - wire width 3 $1589 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - wire width 1 $1590 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $or $1591 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \addr_en$1530 - connect \B \addr_en$1546 - connect \Y $1590 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - wire width 1 $1592 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $or $1593 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \addr_en$1562 - connect \B \addr_en$1578 - connect \Y $1592 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - wire width 1 $1594 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - cell $or $1595 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $1590 - connect \B $1592 - connect \Y $1594 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - cell $pos $1596 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 3 - connect \A $1594 - connect \Y $1589 - end - process $group_623 - assign \xer_wen$157 3'000 - assign \xer_wen$157 $1589 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:390" - wire width 1 \wrflag_branch0_fast1_0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:391" - wire width 1 $1597 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:391" - cell $and $1598 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \fus_fast1_ok - connect \B \fus_cu_busy_o$8 - connect \Y $1597 - end - process $group_624 - assign \wrflag_branch0_fast1_0 1'0 - assign \wrflag_branch0_fast1_0 $1597 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:395" - wire width 1 $1599 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:395" - cell $and $1600 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \fus_cu_wr__rel_o$139 [0] - connect \B \fu_enable [2] - connect \Y $1599 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:395" - wire width 1 $1601 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:395" - cell $and $1602 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \fus_cu_wr__rel_o$87 [1] - connect \B \fu_enable [3] - connect \Y $1601 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:395" - wire width 1 $1603 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:395" - cell $and $1604 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \fus_cu_wr__rel_o$93 [2] - connect \B \fu_enable [5] - connect \Y $1603 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:395" - wire width 1 $1605 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:395" - cell $and $1606 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \fus_cu_wr__rel_o$139 [1] - connect \B \fu_enable [2] - connect \Y $1605 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:395" - wire width 1 $1607 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:395" - cell $and $1608 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \fus_cu_wr__rel_o$87 [2] - connect \B \fu_enable [3] - connect \Y $1607 - end - process $group_625 - assign \wrpick_FAST_fast1_i 5'00000 - assign \wrpick_FAST_fast1_i [0] $1599 - assign \wrpick_FAST_fast1_i [1] $1601 - assign \wrpick_FAST_fast1_i [2] $1603 - assign \wrpick_FAST_fast1_i [3] $1605 - assign \wrpick_FAST_fast1_i [4] $1607 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:398" - wire width 1 \wr_pick$1609 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:399" - wire width 1 $1610 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:399" - cell $and $1611 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wrpick_FAST_fast1_o [0] - connect \B \wrpick_FAST_fast1_en_o - connect \Y $1610 - end - process $group_626 - assign \wr_pick$1609 1'0 - assign \wr_pick$1609 $1610 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire width 1 \wr_pick_dly$1612 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire width 1 \wr_pick_dly$1612$next - process $group_627 - assign \wr_pick_dly$1612$next \wr_pick_dly$1612 - assign \wr_pick_dly$1612$next \wr_pick$1609 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \wr_pick_dly$1612$next 1'0 - end - sync init - update \wr_pick_dly$1612 1'0 - sync posedge \coresync_clk - update \wr_pick_dly$1612 \wr_pick_dly$1612$next - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" - wire width 1 \wr_pick_rise$1613 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - wire width 1 $1614 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $not $1615 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_pick_dly$1612 - connect \Y $1614 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - wire width 1 $1616 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $and $1617 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_pick$1609 - connect \B $1614 - connect \Y $1616 - end - process $group_628 - assign \wr_pick_rise$1613 1'0 - assign \wr_pick_rise$1613 $1616 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" - wire width 1 \wr_pick_rise$1618 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" - wire width 1 \wr_pick_rise$1619 - process $group_629 - assign \fus_cu_wr__go_i$140 3'000 - assign \fus_cu_wr__go_i$140 [0] \wr_pick_rise$1613 - assign \fus_cu_wr__go_i$140 [1] \wr_pick_rise$1618 - assign \fus_cu_wr__go_i$140 [2] \wr_pick_rise$1619 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:406" - wire width 1 \wp$1620 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" - wire width 1 $1621 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" - cell $and $1622 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_pick$1609 - connect \B \wrpick_FAST_fast1_en_o - connect \Y $1621 - end - process $group_630 - assign \wp$1620 1'0 - assign \wp$1620 $1621 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:405" - wire width 3 \addr_en$1623 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408" - wire width 3 $1624 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408" - cell $mux $1625 - parameter \WIDTH 3 - connect \A 3'000 - connect \B \core_fasto1 - connect \S \wp$1620 - connect \Y $1624 - end - process $group_631 - assign \addr_en$1623 3'000 - assign \addr_en$1623 $1624 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:390" - wire width 1 \wrflag_trap0_fast1_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:391" - wire width 1 $1626 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:391" - cell $and $1627 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \fus_fast1_ok$141 - connect \B \fus_cu_busy_o$11 - connect \Y $1626 - end - process $group_632 - assign \wrflag_trap0_fast1_1 1'0 - assign \wrflag_trap0_fast1_1 $1626 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:398" - wire width 1 \wr_pick$1628 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:399" - wire width 1 $1629 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:399" - cell $and $1630 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wrpick_FAST_fast1_o [1] - connect \B \wrpick_FAST_fast1_en_o - connect \Y $1629 - end - process $group_633 - assign \wr_pick$1628 1'0 - assign \wr_pick$1628 $1629 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire width 1 \wr_pick_dly$1631 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire width 1 \wr_pick_dly$1631$next - process $group_634 - assign \wr_pick_dly$1631$next \wr_pick_dly$1631 - assign \wr_pick_dly$1631$next \wr_pick$1628 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \wr_pick_dly$1631$next 1'0 - end - sync init - update \wr_pick_dly$1631 1'0 - sync posedge \coresync_clk - update \wr_pick_dly$1631 \wr_pick_dly$1631$next - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - wire width 1 $1632 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $not $1633 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_pick_dly$1631 - connect \Y $1632 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - wire width 1 $1634 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $and $1635 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_pick$1628 - connect \B $1632 - connect \Y $1634 - end - process $group_635 - assign \wr_pick_rise$992 1'0 - assign \wr_pick_rise$992 $1634 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:406" - wire width 1 \wp$1636 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" - wire width 1 $1637 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" - cell $and $1638 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_pick$1628 - connect \B \wrpick_FAST_fast1_en_o - connect \Y $1637 - end - process $group_636 - assign \wp$1636 1'0 - assign \wp$1636 $1637 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:405" - wire width 3 \addr_en$1639 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408" - wire width 3 $1640 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408" - cell $mux $1641 - parameter \WIDTH 3 - connect \A 3'000 - connect \B \core_fasto1 - connect \S \wp$1636 - connect \Y $1640 - end - process $group_637 - assign \addr_en$1639 3'000 - assign \addr_en$1639 $1640 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:390" - wire width 1 \wrflag_spr0_fast1_2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:391" - wire width 1 $1642 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:391" - cell $and $1643 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \fus_fast1_ok$142 - connect \B \fus_cu_busy_o$17 - connect \Y $1642 - end - process $group_638 - assign \wrflag_spr0_fast1_2 1'0 - assign \wrflag_spr0_fast1_2 $1642 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:398" - wire width 1 \wr_pick$1644 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:399" - wire width 1 $1645 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:399" - cell $and $1646 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wrpick_FAST_fast1_o [2] - connect \B \wrpick_FAST_fast1_en_o - connect \Y $1645 - end - process $group_639 - assign \wr_pick$1644 1'0 - assign \wr_pick$1644 $1645 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire width 1 \wr_pick_dly$1647 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire width 1 \wr_pick_dly$1647$next - process $group_640 - assign \wr_pick_dly$1647$next \wr_pick_dly$1647 - assign \wr_pick_dly$1647$next \wr_pick$1644 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \wr_pick_dly$1647$next 1'0 - end - sync init - update \wr_pick_dly$1647 1'0 - sync posedge \coresync_clk - update \wr_pick_dly$1647 \wr_pick_dly$1647$next - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - wire width 1 $1648 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $not $1649 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_pick_dly$1647 - connect \Y $1648 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - wire width 1 $1650 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $and $1651 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_pick$1644 - connect \B $1648 - connect \Y $1650 - end - process $group_641 - assign \wr_pick_rise$1034 1'0 - assign \wr_pick_rise$1034 $1650 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:406" - wire width 1 \wp$1652 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" - wire width 1 $1653 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" - cell $and $1654 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_pick$1644 - connect \B \wrpick_FAST_fast1_en_o - connect \Y $1653 - end - process $group_642 - assign \wp$1652 1'0 - assign \wp$1652 $1653 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:405" - wire width 3 \addr_en$1655 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408" - wire width 3 $1656 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408" - cell $mux $1657 - parameter \WIDTH 3 - connect \A 3'000 - connect \B \core_fasto1 - connect \S \wp$1652 - connect \Y $1656 - end - process $group_643 - assign \addr_en$1655 3'000 - assign \addr_en$1655 $1656 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:390" - wire width 1 \wrflag_branch0_fast1_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:391" - wire width 1 $1658 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:391" - cell $and $1659 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \fus_fast2_ok - connect \B \fus_cu_busy_o$8 - connect \Y $1658 - end - process $group_644 - assign \wrflag_branch0_fast1_1 1'0 - assign \wrflag_branch0_fast1_1 $1658 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:398" - wire width 1 \wr_pick$1660 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:399" - wire width 1 $1661 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:399" - cell $and $1662 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wrpick_FAST_fast1_o [3] - connect \B \wrpick_FAST_fast1_en_o - connect \Y $1661 - end - process $group_645 - assign \wr_pick$1660 1'0 - assign \wr_pick$1660 $1661 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire width 1 \wr_pick_dly$1663 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire width 1 \wr_pick_dly$1663$next - process $group_646 - assign \wr_pick_dly$1663$next \wr_pick_dly$1663 - assign \wr_pick_dly$1663$next \wr_pick$1660 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \wr_pick_dly$1663$next 1'0 - end - sync init - update \wr_pick_dly$1663 1'0 - sync posedge \coresync_clk - update \wr_pick_dly$1663 \wr_pick_dly$1663$next - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - wire width 1 $1664 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $not $1665 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_pick_dly$1663 - connect \Y $1664 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - wire width 1 $1666 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $and $1667 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_pick$1660 - connect \B $1664 - connect \Y $1666 - end - process $group_647 - assign \wr_pick_rise$1618 1'0 - assign \wr_pick_rise$1618 $1666 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:406" - wire width 1 \wp$1668 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" - wire width 1 $1669 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" - cell $and $1670 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_pick$1660 - connect \B \wrpick_FAST_fast1_en_o - connect \Y $1669 - end - process $group_648 - assign \wp$1668 1'0 - assign \wp$1668 $1669 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:405" - wire width 3 \addr_en$1671 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408" - wire width 3 $1672 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408" - cell $mux $1673 - parameter \WIDTH 3 - connect \A 3'000 - connect \B \core_fasto2 - connect \S \wp$1668 - connect \Y $1672 - end - process $group_649 - assign \addr_en$1671 3'000 - assign \addr_en$1671 $1672 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:390" - wire width 1 \wrflag_trap0_fast1_2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:391" - wire width 1 $1674 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:391" - cell $and $1675 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \fus_fast2_ok$143 - connect \B \fus_cu_busy_o$11 - connect \Y $1674 - end - process $group_650 - assign \wrflag_trap0_fast1_2 1'0 - assign \wrflag_trap0_fast1_2 $1674 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:398" - wire width 1 \wr_pick$1676 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:399" - wire width 1 $1677 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:399" - cell $and $1678 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wrpick_FAST_fast1_o [4] - connect \B \wrpick_FAST_fast1_en_o - connect \Y $1677 - end - process $group_651 - assign \wr_pick$1676 1'0 - assign \wr_pick$1676 $1677 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire width 1 \wr_pick_dly$1679 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire width 1 \wr_pick_dly$1679$next - process $group_652 - assign \wr_pick_dly$1679$next \wr_pick_dly$1679 - assign \wr_pick_dly$1679$next \wr_pick$1676 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \wr_pick_dly$1679$next 1'0 - end - sync init - update \wr_pick_dly$1679 1'0 - sync posedge \coresync_clk - update \wr_pick_dly$1679 \wr_pick_dly$1679$next - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - wire width 1 $1680 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $not $1681 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_pick_dly$1679 - connect \Y $1680 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - wire width 1 $1682 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $and $1683 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_pick$1676 - connect \B $1680 - connect \Y $1682 - end - process $group_653 - assign \wr_pick_rise$993 1'0 - assign \wr_pick_rise$993 $1682 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:406" - wire width 1 \wp$1684 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" - wire width 1 $1685 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" - cell $and $1686 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_pick$1676 - connect \B \wrpick_FAST_fast1_en_o - connect \Y $1685 - end - process $group_654 - assign \wp$1684 1'0 - assign \wp$1684 $1685 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:405" - wire width 3 \addr_en$1687 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408" - wire width 3 $1688 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408" - cell $mux $1689 - parameter \WIDTH 3 - connect \A 3'000 - connect \B \core_fasto2 - connect \S \wp$1684 - connect \Y $1688 - end - process $group_655 - assign \addr_en$1687 3'000 - assign \addr_en$1687 $1688 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - wire width 64 $1690 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $or $1691 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \B_SIGNED 0 - parameter \B_WIDTH 64 - parameter \Y_WIDTH 64 - connect \A \fus_dest1_o$144 - connect \B \fus_dest2_o$145 - connect \Y $1690 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - wire width 64 $1692 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $or $1693 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \B_SIGNED 0 - parameter \B_WIDTH 64 - parameter \Y_WIDTH 64 - connect \A \fus_dest2_o$147 - connect \B \fus_dest3_o$148 - connect \Y $1692 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - wire width 64 $1694 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - cell $or $1695 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \B_SIGNED 0 - parameter \B_WIDTH 64 - parameter \Y_WIDTH 64 - connect \A \fus_dest3_o$146 - connect \B $1692 - connect \Y $1694 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - wire width 64 $1696 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - cell $or $1697 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \B_SIGNED 0 - parameter \B_WIDTH 64 - parameter \Y_WIDTH 64 - connect \A $1690 - connect \B $1694 - connect \Y $1696 - end - process $group_656 - assign \fast_dest1__data_i 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \fast_dest1__data_i $1696 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - wire width 3 $1698 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $or $1699 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A \addr_en$1623 - connect \B \addr_en$1639 - connect \Y $1698 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - wire width 3 $1700 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $or $1701 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A \addr_en$1671 - connect \B \addr_en$1687 - connect \Y $1700 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - wire width 3 $1702 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - cell $or $1703 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A \addr_en$1655 - connect \B $1700 - connect \Y $1702 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - wire width 3 $1704 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - cell $or $1705 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 3 - connect \A $1698 - connect \B $1702 - connect \Y $1704 - end - process $group_657 - assign \fast_dest1__addr 3'000 - assign \fast_dest1__addr $1704 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - wire width 1 $1706 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $or $1707 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wp$1620 - connect \B \wp$1636 - connect \Y $1706 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - wire width 1 $1708 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $or $1709 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wp$1668 - connect \B \wp$1684 - connect \Y $1708 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - wire width 1 $1710 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - cell $or $1711 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wp$1652 - connect \B $1708 - connect \Y $1710 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - wire width 1 $1712 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:29" - cell $or $1713 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $1706 - connect \B $1710 - connect \Y $1712 - end - process $group_658 - assign \fast_dest1__wen 1'0 - assign \fast_dest1__wen $1712 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:390" - wire width 1 \wrflag_branch0_nia_2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:391" - wire width 1 $1714 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:391" - cell $and $1715 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \fus_nia_ok - connect \B \fus_cu_busy_o$8 - connect \Y $1714 - end - process $group_659 - assign \wrflag_branch0_nia_2 1'0 - assign \wrflag_branch0_nia_2 $1714 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:395" - wire width 1 $1716 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:395" - cell $and $1717 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \fus_cu_wr__rel_o$139 [2] - connect \B \fu_enable [2] - connect \Y $1716 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:395" - wire width 1 $1718 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:395" - cell $and $1719 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \fus_cu_wr__rel_o$87 [3] - connect \B \fu_enable [3] - connect \Y $1718 - end - process $group_660 - assign \wrpick_STATE_nia_i 2'00 - assign \wrpick_STATE_nia_i [0] $1716 - assign \wrpick_STATE_nia_i [1] $1718 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:398" - wire width 1 \wr_pick$1720 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:399" - wire width 1 $1721 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:399" - cell $and $1722 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wrpick_STATE_nia_o [0] - connect \B \wrpick_STATE_nia_en_o - connect \Y $1721 - end - process $group_661 - assign \wr_pick$1720 1'0 - assign \wr_pick$1720 $1721 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire width 1 \wr_pick_dly$1723 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire width 1 \wr_pick_dly$1723$next - process $group_662 - assign \wr_pick_dly$1723$next \wr_pick_dly$1723 - assign \wr_pick_dly$1723$next \wr_pick$1720 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \wr_pick_dly$1723$next 1'0 - end - sync init - update \wr_pick_dly$1723 1'0 - sync posedge \coresync_clk - update \wr_pick_dly$1723 \wr_pick_dly$1723$next - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - wire width 1 $1724 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $not $1725 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_pick_dly$1723 - connect \Y $1724 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - wire width 1 $1726 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $and $1727 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_pick$1720 - connect \B $1724 - connect \Y $1726 - end - process $group_663 - assign \wr_pick_rise$1619 1'0 - assign \wr_pick_rise$1619 $1726 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:406" - wire width 1 \wp$1728 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" - wire width 1 $1729 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" - cell $and $1730 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_pick$1720 - connect \B \wrpick_STATE_nia_en_o - connect \Y $1729 - end - process $group_664 - assign \wp$1728 1'0 - assign \wp$1728 $1729 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:405" - wire width 1 \addr_en$1731 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408" - wire width 1 $1732 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408" - cell $mux $1733 - parameter \WIDTH 1 - connect \A 1'0 - connect \B 1'1 - connect \S \wp$1728 - connect \Y $1732 - end - process $group_665 - assign \addr_en$1731 1'0 - assign \addr_en$1731 $1732 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:390" - wire width 1 \wrflag_trap0_nia_3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:391" - wire width 1 $1734 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:391" - cell $and $1735 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \fus_nia_ok$149 - connect \B \fus_cu_busy_o$11 - connect \Y $1734 - end - process $group_666 - assign \wrflag_trap0_nia_3 1'0 - assign \wrflag_trap0_nia_3 $1734 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:398" - wire width 1 \wr_pick$1736 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:399" - wire width 1 $1737 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:399" - cell $and $1738 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wrpick_STATE_nia_o [1] - connect \B \wrpick_STATE_nia_en_o - connect \Y $1737 - end - process $group_667 - assign \wr_pick$1736 1'0 - assign \wr_pick$1736 $1737 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire width 1 \wr_pick_dly$1739 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire width 1 \wr_pick_dly$1739$next - process $group_668 - assign \wr_pick_dly$1739$next \wr_pick_dly$1739 - assign \wr_pick_dly$1739$next \wr_pick$1736 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \wr_pick_dly$1739$next 1'0 - end - sync init - update \wr_pick_dly$1739 1'0 - sync posedge \coresync_clk - update \wr_pick_dly$1739 \wr_pick_dly$1739$next - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - wire width 1 $1740 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $not $1741 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_pick_dly$1739 - connect \Y $1740 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - wire width 1 $1742 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $and $1743 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_pick$1736 - connect \B $1740 - connect \Y $1742 - end - process $group_669 - assign \wr_pick_rise$994 1'0 - assign \wr_pick_rise$994 $1742 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:406" - wire width 1 \wp$1744 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" - wire width 1 $1745 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" - cell $and $1746 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_pick$1736 - connect \B \wrpick_STATE_nia_en_o - connect \Y $1745 - end - process $group_670 - assign \wp$1744 1'0 - assign \wp$1744 $1745 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:405" - wire width 1 \addr_en$1747 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408" - wire width 1 $1748 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408" - cell $mux $1749 - parameter \WIDTH 1 - connect \A 1'0 - connect \B 1'1 - connect \S \wp$1744 - connect \Y $1748 - end - process $group_671 - assign \addr_en$1747 1'0 - assign \addr_en$1747 $1748 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - wire width 64 $1750 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $or $1751 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \B_SIGNED 0 - parameter \B_WIDTH 64 - parameter \Y_WIDTH 64 - connect \A \fus_dest3_o$150 - connect \B \fus_dest4_o$151 - connect \Y $1750 - end - process $group_672 - assign \state_data_i 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \state_data_i $1750 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - wire width 4 $1752 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - wire width 1 $1753 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $or $1754 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \addr_en$1731 - connect \B \addr_en$1747 - connect \Y $1753 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:26" - cell $pos $1755 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 4 - connect \A $1753 - connect \Y $1752 - end - process $group_673 - assign \state_nia_wen 4'0000 - assign \state_nia_wen $1752 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:390" - wire width 1 \wrflag_trap0_msr_4 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:391" - wire width 1 $1756 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:391" - cell $and $1757 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \fus_msr_ok - connect \B \fus_cu_busy_o$11 - connect \Y $1756 - end - process $group_674 - assign \wrflag_trap0_msr_4 1'0 - assign \wrflag_trap0_msr_4 $1756 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:395" - wire width 1 $1758 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:395" - cell $and $1759 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \fus_cu_wr__rel_o$87 [4] - connect \B \fu_enable [3] - connect \Y $1758 - end - process $group_675 - assign \wrpick_STATE_msr_i 1'0 - assign \wrpick_STATE_msr_i $1758 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:398" - wire width 1 \wr_pick$1760 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:399" - wire width 1 $1761 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:399" - cell $and $1762 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wrpick_STATE_msr_o - connect \B \wrpick_STATE_msr_en_o - connect \Y $1761 - end - process $group_676 - assign \wr_pick$1760 1'0 - assign \wr_pick$1760 $1761 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire width 1 \wr_pick_dly$1763 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire width 1 \wr_pick_dly$1763$next - process $group_677 - assign \wr_pick_dly$1763$next \wr_pick_dly$1763 - assign \wr_pick_dly$1763$next \wr_pick$1760 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \wr_pick_dly$1763$next 1'0 - end - sync init - update \wr_pick_dly$1763 1'0 - sync posedge \coresync_clk - update \wr_pick_dly$1763 \wr_pick_dly$1763$next - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - wire width 1 $1764 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $not $1765 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_pick_dly$1763 - connect \Y $1764 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - wire width 1 $1766 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $and $1767 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_pick$1760 - connect \B $1764 - connect \Y $1766 - end - process $group_678 - assign \wr_pick_rise$995 1'0 - assign \wr_pick_rise$995 $1766 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:406" - wire width 1 \wp$1768 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" - wire width 1 $1769 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" - cell $and $1770 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_pick$1760 - connect \B \wrpick_STATE_msr_en_o - connect \Y $1769 - end - process $group_679 - assign \wp$1768 1'0 - assign \wp$1768 $1769 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:405" - wire width 2 \addr_en$1771 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408" - wire width 2 $1772 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408" - cell $mux $1773 - parameter \WIDTH 2 - connect \A 2'00 - connect \B 2'10 - connect \S \wp$1768 - connect \Y $1772 - end - process $group_680 - assign \addr_en$1771 2'00 - assign \addr_en$1771 $1772 - sync init - end - process $group_681 - assign \state_data_i$158 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \state_data_i$158 \fus_dest5_o$152 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:405" - wire width 4 $1774 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:405" - cell $pos $1775 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \Y_WIDTH 4 - connect \A \addr_en$1771 - connect \Y $1774 - end - process $group_682 - assign \state_wen 4'0000 - assign \state_wen $1774 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:390" - wire width 1 \wrflag_spr0_spr1_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:391" - wire width 1 $1776 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:391" - cell $and $1777 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \fus_spr1_ok - connect \B \fus_cu_busy_o$17 - connect \Y $1776 - end - process $group_683 - assign \wrflag_spr0_spr1_1 1'0 - assign \wrflag_spr0_spr1_1 $1776 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:395" - wire width 1 $1778 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:395" - cell $and $1779 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \fus_cu_wr__rel_o$93 [1] - connect \B \fu_enable [5] - connect \Y $1778 - end - process $group_684 - assign \wrpick_SPR_spr1_i 1'0 - assign \wrpick_SPR_spr1_i $1778 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:398" - wire width 1 \wr_pick$1780 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:399" - wire width 1 $1781 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:399" - cell $and $1782 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wrpick_SPR_spr1_o - connect \B \wrpick_SPR_spr1_en_o - connect \Y $1781 - end - process $group_685 - assign \wr_pick$1780 1'0 - assign \wr_pick$1780 $1781 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire width 1 \wr_pick_dly$1783 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire width 1 \wr_pick_dly$1783$next - process $group_686 - assign \wr_pick_dly$1783$next \wr_pick_dly$1783 - assign \wr_pick_dly$1783$next \wr_pick$1780 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \coresync_rst - case 1'1 - assign \wr_pick_dly$1783$next 1'0 - end - sync init - update \wr_pick_dly$1783 1'0 - sync posedge \coresync_clk - update \wr_pick_dly$1783 \wr_pick_dly$1783$next - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - wire width 1 $1784 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $not $1785 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_pick_dly$1783 - connect \Y $1784 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - wire width 1 $1786 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $and $1787 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_pick$1780 - connect \B $1784 - connect \Y $1786 - end - process $group_687 - assign \wr_pick_rise$1035 1'0 - assign \wr_pick_rise$1035 $1786 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:406" - wire width 1 \wp$1788 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" - wire width 1 $1789 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:407" - cell $and $1790 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \wr_pick$1780 - connect \B \wrpick_SPR_spr1_en_o - connect \Y $1789 - end - process $group_688 - assign \wp$1788 1'0 - assign \wp$1788 $1789 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:405" - wire width 10 \addr_en$1791 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408" - wire width 10 $1792 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:408" - cell $mux $1793 - parameter \WIDTH 10 - connect \A 10'0000000000 - connect \B \core_spro - connect \S \wp$1788 - connect \Y $1792 - end - process $group_689 - assign \addr_en$1791 10'0000000000 - assign \addr_en$1791 $1792 - sync init - end - process $group_690 - assign \spr_spr1__data_i 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \spr_spr1__data_i \fus_dest2_o$153 - sync init - end - process $group_691 - assign \spr_spr1__addr$159 7'0000000 - assign \spr_spr1__addr$159 \addr_en$1791 [6:0] - sync init - end - process $group_692 - assign \spr_spr1__wen 1'0 - assign \spr_spr1__wen \wp$1788 - sync init - end - process $group_693 - assign \coresync_rst 1'0 - assign \coresync_rst \core_reset_i - sync init - end - connect \o_ok 1'0 - connect \ea_ok 1'0 -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.imem" -module \imem - attribute \src "simple/issuer.py:140" - wire width 1 input 0 \clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:24" - wire width 48 input 1 \a_pc_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:26" - wire width 1 input 2 \a_valid_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:28" - wire width 1 input 3 \f_valid_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:32" - wire width 1 output 4 \f_busy_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:33" - wire width 64 output 5 \f_instr_o - attribute \src "simple/issuer.py:140" - wire width 1 input 6 \rst - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" - wire width 1 output 7 \ibus__cyc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" - wire width 1 \ibus__cyc$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" - wire width 1 input 8 \ibus__ack - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" - wire width 1 input 9 \ibus__err - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" - wire width 1 output 10 \ibus__stb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" - wire width 1 \ibus__stb$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" - wire width 8 output 11 \ibus__sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" - wire width 8 \ibus__sel$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" - wire width 64 input 12 \ibus__dat_r - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" - wire width 45 output 13 \ibus__adr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:20" - wire width 45 \ibus__adr$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:68" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:25" - wire width 1 \a_stall_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:68" - cell $not $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \a_stall_i - connect \Y $1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:68" - wire width 1 $3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:68" - cell $and $4 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \a_valid_i - connect \B $1 - connect \Y $3 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:61" - wire width 1 $5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:61" - cell $or $6 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \ibus__ack - connect \B \ibus__err - connect \Y $5 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:61" - wire width 1 $7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:61" - cell $not $8 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \f_valid_i - connect \Y $7 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:61" - wire width 1 $9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:61" - cell $or $10 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $5 - connect \B $7 - connect \Y $9 - end - process $group_0 - assign \ibus__cyc$next \ibus__cyc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:60" - switch { $3 \ibus__cyc } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:60" - case 2'-1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:61" - switch { $9 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:61" - case 1'1 - assign \ibus__cyc$next 1'0 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:68" - case 2'1- - assign \ibus__cyc$next 1'1 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \rst - case 1'1 - assign \ibus__cyc$next 1'0 - end - sync init - update \ibus__cyc 1'0 - sync posedge \clk - update \ibus__cyc \ibus__cyc$next - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:68" - wire width 1 $11 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:68" - cell $not $12 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \a_stall_i - connect \Y $11 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:68" - wire width 1 $13 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:68" - cell $and $14 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \a_valid_i - connect \B $11 - connect \Y $13 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:61" - wire width 1 $15 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:61" - cell $or $16 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \ibus__ack - connect \B \ibus__err - connect \Y $15 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:61" - wire width 1 $17 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:61" - cell $not $18 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \f_valid_i - connect \Y $17 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:61" - wire width 1 $19 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:61" - cell $or $20 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $15 - connect \B $17 - connect \Y $19 - end - process $group_1 - assign \ibus__stb$next \ibus__stb - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:60" - switch { $13 \ibus__cyc } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:60" - case 2'-1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:61" - switch { $19 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:61" - case 1'1 - assign \ibus__stb$next 1'0 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:68" - case 2'1- - assign \ibus__stb$next 1'1 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \rst - case 1'1 - assign \ibus__stb$next 1'0 - end - sync init - update \ibus__stb 1'0 - sync posedge \clk - update \ibus__stb \ibus__stb$next - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:68" - wire width 1 $21 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:68" - cell $not $22 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \a_stall_i - connect \Y $21 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:68" - wire width 1 $23 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:68" - cell $and $24 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \a_valid_i - connect \B $21 - connect \Y $23 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:61" - wire width 1 $25 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:61" - cell $or $26 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \ibus__ack - connect \B \ibus__err - connect \Y $25 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:61" - wire width 1 $27 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:61" - cell $not $28 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \f_valid_i - connect \Y $27 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:61" - wire width 1 $29 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:61" - cell $or $30 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $25 - connect \B $27 - connect \Y $29 - end - process $group_2 - assign \ibus__sel$next \ibus__sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:60" - switch { $23 \ibus__cyc } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:60" - case 2'-1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:61" - switch { $29 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:61" - case 1'1 - assign \ibus__sel$next 8'00000000 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:68" - case 2'1- - assign \ibus__sel$next 8'11111111 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \rst - case 1'1 - assign \ibus__sel$next 8'00000000 - end - sync init - update \ibus__sel 8'00000000 - sync posedge \clk - update \ibus__sel \ibus__sel$next - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:59" - wire width 64 \ibus_rdata - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:59" - wire width 64 \ibus_rdata$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:68" - wire width 1 $31 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:68" - cell $not $32 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \a_stall_i - connect \Y $31 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:68" - wire width 1 $33 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:68" - cell $and $34 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \a_valid_i - connect \B $31 - connect \Y $33 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:61" - wire width 1 $35 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:61" - cell $or $36 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \ibus__ack - connect \B \ibus__err - connect \Y $35 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:61" - wire width 1 $37 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:61" - cell $not $38 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \f_valid_i - connect \Y $37 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:61" - wire width 1 $39 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:61" - cell $or $40 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $35 - connect \B $37 - connect \Y $39 - end - process $group_3 - assign \ibus_rdata$next \ibus_rdata - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:60" - switch { $33 \ibus__cyc } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:60" - case 2'-1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:61" - switch { $39 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:61" - case 1'1 - assign \ibus_rdata$next \ibus__dat_r - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:68" - case 2'1- - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \rst - case 1'1 - assign \ibus_rdata$next 64'0000000000000000000000000000000000000000000000000000000000000000 - end - sync init - update \ibus_rdata 64'0000000000000000000000000000000000000000000000000000000000000000 - sync posedge \clk - update \ibus_rdata \ibus_rdata$next - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:68" - wire width 1 $41 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:68" - cell $not $42 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \a_stall_i - connect \Y $41 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:68" - wire width 1 $43 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:68" - cell $and $44 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \a_valid_i - connect \B $41 - connect \Y $43 - end - process $group_4 - assign \ibus__adr$next \ibus__adr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:60" - switch { $43 \ibus__cyc } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:60" - case 2'-1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:68" - case 2'1- - assign \ibus__adr$next \a_pc_i [47:3] - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \rst - case 1'1 - assign \ibus__adr$next 45'000000000000000000000000000000000000000000000 - end - sync init - update \ibus__adr 45'000000000000000000000000000000000000000000000 - sync posedge \clk - update \ibus__adr \ibus__adr$next - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:34" - wire width 1 \f_fetch_err_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:34" - wire width 1 \f_fetch_err_o$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:76" - wire width 1 $45 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:76" - cell $and $46 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \ibus__cyc - connect \B \ibus__err - connect \Y $45 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:81" - wire width 1 $47 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:27" - wire width 1 \f_stall_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:81" - cell $not $48 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \f_stall_i - connect \Y $47 - end - process $group_5 - assign \f_fetch_err_o$next \f_fetch_err_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:76" - switch { $47 $45 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:76" - case 2'-1 - assign \f_fetch_err_o$next 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:81" - case 2'1- - assign \f_fetch_err_o$next 1'0 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \rst - case 1'1 - assign \f_fetch_err_o$next 1'0 - end - sync init - update \f_fetch_err_o 1'0 - sync posedge \clk - update \f_fetch_err_o \f_fetch_err_o$next - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:35" - wire width 45 \f_badaddr_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:35" - wire width 45 \f_badaddr_o$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:76" - wire width 1 $49 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:76" - cell $and $50 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \ibus__cyc - connect \B \ibus__err - connect \Y $49 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:81" - wire width 1 $51 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:81" - cell $not $52 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \f_stall_i - connect \Y $51 - end - process $group_6 - assign \f_badaddr_o$next \f_badaddr_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:76" - switch { $51 $49 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:76" - case 2'-1 - assign \f_badaddr_o$next \ibus__adr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:81" - case 2'1- - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \rst - case 1'1 - assign \f_badaddr_o$next 45'000000000000000000000000000000000000000000000 - end - sync init - update \f_badaddr_o 45'000000000000000000000000000000000000000000000 - sync posedge \clk - update \f_badaddr_o \f_badaddr_o$next - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:31" - wire width 1 \a_busy_o - process $group_7 - assign \a_busy_o 1'0 - assign \a_busy_o \ibus__cyc - sync init - end - process $group_8 - assign \f_busy_o 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:86" - switch { \f_fetch_err_o } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:86" - case 1'1 - assign \f_busy_o 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:88" - case - assign \f_busy_o \ibus__cyc - end - sync init - end - process $group_9 - assign \f_instr_o 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:86" - switch { \f_fetch_err_o } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:86" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:88" - case - assign \f_instr_o \ibus_rdata - end - sync init - end - connect \a_stall_i 1'0 - connect \f_stall_i 1'0 -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.dbg" -module \dbg - attribute \src "simple/issuer.py:140" - wire width 1 input 0 \clk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:90" - wire width 1 output 1 \core_rst_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:94" - wire width 1 input 2 \terminate_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:8" - wire width 64 input 3 \core_dbg_pc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:9" - wire width 64 input 4 \core_dbg_msr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:89" - wire width 1 output 5 \core_stop_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:95" - wire width 1 input 6 \core_stopped_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:68" - wire width 1 output 7 \d_gpr_req - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:70" - wire width 7 output 8 \d_gpr_addr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:71" - wire width 64 input 9 \d_gpr_data - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:69" - wire width 1 input 10 \d_gpr_ack - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:68" - wire width 1 output 11 \d_cr_req - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:71" - wire width 64 input 12 \d_cr_data - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:69" - wire width 1 input 13 \d_cr_ack - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:68" - wire width 1 output 14 \d_xer_req - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:71" - wire width 64 input 15 \d_xer_data - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:69" - wire width 1 input 16 \d_xer_ack - attribute \src "simple/issuer.py:140" - wire width 1 input 17 \rst - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:57" - wire width 4 input 18 \dmi_addr_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:62" - wire width 1 output 19 \dmi_ack_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:60" - wire width 1 input 20 \dmi_req_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:59" - wire width 64 output 21 \dmi_dout - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:61" - wire width 1 input 22 \dmi_we_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:58" - wire width 64 input 23 \dmi_din - process $group_0 - assign \dmi_ack_o 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:146" - switch \dmi_addr_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:147" - case 4'0101 - assign \dmi_ack_o \d_gpr_ack - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:150" - case 4'1000 - assign \dmi_ack_o \d_cr_ack - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:153" - case 4'1001 - assign \dmi_ack_o \d_xer_ack - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:156" - case - assign \dmi_ack_o \dmi_req_i - end - sync init - end - process $group_1 - assign \d_gpr_req 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:146" - switch \dmi_addr_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:147" - case 4'0101 - assign \d_gpr_req \dmi_req_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:150" - case 4'1000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:153" - case 4'1001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:156" - case - end - sync init - end - process $group_2 - assign \d_cr_req 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:146" - switch \dmi_addr_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:147" - case 4'0101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:150" - case 4'1000 - assign \d_cr_req \dmi_req_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:153" - case 4'1001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:156" - case - end - sync init - end - process $group_3 - assign \d_xer_req 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:146" - switch \dmi_addr_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:147" - case 4'0101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:150" - case 4'1000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:153" - case 4'1001 - assign \d_xer_req \dmi_req_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:156" - case - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:126" - wire width 64 \stat_reg - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:162" - wire width 64 $1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:129" - wire width 1 \stopping - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:129" - wire width 1 \stopping$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:133" - wire width 1 \terminated - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:133" - wire width 1 \terminated$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:162" - cell $pos $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 64 - connect \A { \terminated \core_stopped_i \stopping } - connect \Y $1 - end - process $group_4 - assign \stat_reg 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \stat_reg $1 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:137" - wire width 32 \log_dmi_addr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:137" - wire width 32 \log_dmi_addr$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:111" - wire width 32 \log_write_addr_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:138" - wire width 64 \log_dmi_data - process $group_5 - assign \dmi_dout 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:165" - switch \dmi_addr_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:166" - case 4'0001 - assign \dmi_dout \stat_reg - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:168" - case 4'0010 - assign \dmi_dout \core_dbg_pc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:170" - case 4'0011 - assign \dmi_dout \core_dbg_msr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:172" - case 4'0101 - assign \dmi_dout \d_gpr_data - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:174" - case 4'0110 - assign \dmi_dout { \log_write_addr_o \log_dmi_addr } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:176" - case 4'0111 - assign \dmi_dout \log_dmi_data - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:178" - case 4'1000 - assign \dmi_dout \d_cr_data - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:180" - case 4'1001 - assign \dmi_dout \d_xer_data - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:130" - wire width 1 \do_step - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:130" - wire width 1 \do_step$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:192" - wire width 1 $3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:123" - wire width 1 \dmi_req_i_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:123" - wire width 1 \dmi_req_i_1$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:192" - cell $not $4 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \dmi_req_i_1 - connect \Y $3 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:192" - wire width 1 $5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:192" - cell $and $6 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \dmi_req_i - connect \B $3 - connect \Y $5 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:141" - wire width 1 \dmi_read_log_data_1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:141" - wire width 1 \dmi_read_log_data_1$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:226" - wire width 1 $7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:140" - wire width 1 \dmi_read_log_data - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:140" - wire width 1 \dmi_read_log_data$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:226" - cell $not $8 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \dmi_read_log_data - connect \Y $7 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:226" - wire width 1 $9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:226" - cell $and $10 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \dmi_read_log_data_1 - connect \B $7 - connect \Y $9 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:199" - wire width 1 $11 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:199" - cell $eq $12 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \dmi_addr_i - connect \B 1'0 - connect \Y $11 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:215" - wire width 1 $13 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:215" - cell $eq $14 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \dmi_addr_i - connect \B 3'100 - connect \Y $13 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:219" - wire width 1 $15 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:219" - cell $eq $16 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \dmi_addr_i - connect \B 3'110 - connect \Y $15 - end - process $group_6 - assign \do_step$next \do_step - assign \do_step$next 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:192" - switch { $9 $5 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:192" - case 2'-1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:193" - switch { \dmi_we_i } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:193" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:199" - switch { $15 $13 $11 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:199" - case 3'--1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:205" - switch { \dmi_din [3] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:205" - case 1'1 - assign \do_step$next 1'1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:215" - case 3'-1- - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:219" - case 3'1-- - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:222" - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:226" - case 2'1- - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \rst - case 1'1 - assign \do_step$next 1'0 - end - sync init - update \do_step 1'0 - sync posedge \clk - update \do_step \do_step$next - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:131" - wire width 1 \do_reset - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:131" - wire width 1 \do_reset$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:192" - wire width 1 $17 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:192" - cell $not $18 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \dmi_req_i_1 - connect \Y $17 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:192" - wire width 1 $19 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:192" - cell $and $20 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \dmi_req_i - connect \B $17 - connect \Y $19 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:226" - wire width 1 $21 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:226" - cell $not $22 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \dmi_read_log_data - connect \Y $21 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:226" - wire width 1 $23 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:226" - cell $and $24 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \dmi_read_log_data_1 - connect \B $21 - connect \Y $23 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:199" - wire width 1 $25 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:199" - cell $eq $26 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \dmi_addr_i - connect \B 1'0 - connect \Y $25 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:215" - wire width 1 $27 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:215" - cell $eq $28 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \dmi_addr_i - connect \B 3'100 - connect \Y $27 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:219" - wire width 1 $29 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:219" - cell $eq $30 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \dmi_addr_i - connect \B 3'110 - connect \Y $29 - end - process $group_7 - assign \do_reset$next \do_reset - assign \do_reset$next 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:192" - switch { $23 $19 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:192" - case 2'-1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:193" - switch { \dmi_we_i } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:193" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:199" - switch { $29 $27 $25 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:199" - case 3'--1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200" - switch { \dmi_din [1] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200" - case 1'1 - assign \do_reset$next 1'1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:215" - case 3'-1- - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:219" - case 3'1-- - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:222" - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:226" - case 2'1- - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \rst - case 1'1 - assign \do_reset$next 1'0 - end - sync init - update \do_reset 1'0 - sync posedge \clk - update \do_reset \do_reset$next - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:132" - wire width 1 \do_icreset - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:132" - wire width 1 \do_icreset$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:192" - wire width 1 $31 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:192" - cell $not $32 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \dmi_req_i_1 - connect \Y $31 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:192" - wire width 1 $33 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:192" - cell $and $34 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \dmi_req_i - connect \B $31 - connect \Y $33 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:226" - wire width 1 $35 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:226" - cell $not $36 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \dmi_read_log_data - connect \Y $35 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:226" - wire width 1 $37 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:226" - cell $and $38 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \dmi_read_log_data_1 - connect \B $35 - connect \Y $37 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:199" - wire width 1 $39 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:199" - cell $eq $40 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \dmi_addr_i - connect \B 1'0 - connect \Y $39 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:215" - wire width 1 $41 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:215" - cell $eq $42 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \dmi_addr_i - connect \B 3'100 - connect \Y $41 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:219" - wire width 1 $43 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:219" - cell $eq $44 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \dmi_addr_i - connect \B 3'110 - connect \Y $43 - end - process $group_8 - assign \do_icreset$next \do_icreset - assign \do_icreset$next 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:192" - switch { $37 $33 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:192" - case 2'-1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:193" - switch { \dmi_we_i } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:193" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:199" - switch { $43 $41 $39 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:199" - case 3'--1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:208" - switch { \dmi_din [2] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:208" - case 1'1 - assign \do_icreset$next 1'1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:215" - case 3'-1- - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:219" - case 3'1-- - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:222" - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:226" - case 2'1- - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \rst - case 1'1 - assign \do_icreset$next 1'0 - end - sync init - update \do_icreset 1'0 - sync posedge \clk - update \do_icreset \do_icreset$next - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:139" - wire width 1 \do_dmi_log_rd - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:139" - wire width 1 \do_dmi_log_rd$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:192" - wire width 1 $45 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:192" - cell $not $46 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \dmi_req_i_1 - connect \Y $45 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:192" - wire width 1 $47 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:192" - cell $and $48 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \dmi_req_i - connect \B $45 - connect \Y $47 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:226" - wire width 1 $49 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:226" - cell $not $50 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \dmi_read_log_data - connect \Y $49 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:226" - wire width 1 $51 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:226" - cell $and $52 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \dmi_read_log_data_1 - connect \B $49 - connect \Y $51 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:199" - wire width 1 $53 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:199" - cell $eq $54 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \dmi_addr_i - connect \B 1'0 - connect \Y $53 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:215" - wire width 1 $55 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:215" - cell $eq $56 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \dmi_addr_i - connect \B 3'100 - connect \Y $55 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:219" - wire width 1 $57 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:219" - cell $eq $58 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \dmi_addr_i - connect \B 3'110 - connect \Y $57 - end - process $group_9 - assign \do_dmi_log_rd$next \do_dmi_log_rd - assign \do_dmi_log_rd$next 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:192" - switch { $51 $47 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:192" - case 2'-1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:193" - switch { \dmi_we_i } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:193" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:199" - switch { $57 $55 $53 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:199" - case 3'--1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:215" - case 3'-1- - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:219" - case 3'1-- - assign \do_dmi_log_rd$next 1'1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:222" - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:226" - case 2'1- - assign \do_dmi_log_rd$next 1'1 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \rst - case 1'1 - assign \do_dmi_log_rd$next 1'0 - end - sync init - update \do_dmi_log_rd 1'0 - sync posedge \clk - update \do_dmi_log_rd \do_dmi_log_rd$next - end - process $group_10 - assign \dmi_req_i_1$next \dmi_req_i_1 - assign \dmi_req_i_1$next \dmi_req_i - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \rst - case 1'1 - assign \dmi_req_i_1$next 1'0 - end - sync init - update \dmi_req_i_1 1'0 - sync posedge \clk - update \dmi_req_i_1 \dmi_req_i_1$next - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:192" - wire width 1 $59 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:192" - cell $not $60 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \dmi_req_i_1 - connect \Y $59 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:192" - wire width 1 $61 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:192" - cell $and $62 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \dmi_req_i - connect \B $59 - connect \Y $61 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:226" - wire width 1 $63 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:226" - cell $not $64 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \dmi_read_log_data - connect \Y $63 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:226" - wire width 1 $65 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:226" - cell $and $66 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \dmi_read_log_data_1 - connect \B $63 - connect \Y $65 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:199" - wire width 1 $67 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:199" - cell $eq $68 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \dmi_addr_i - connect \B 1'0 - connect \Y $67 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:215" - wire width 1 $69 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:215" - cell $eq $70 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \dmi_addr_i - connect \B 3'100 - connect \Y $69 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:219" - wire width 1 $71 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:219" - cell $eq $72 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \dmi_addr_i - connect \B 3'110 - connect \Y $71 - end - process $group_11 - assign \terminated$next \terminated - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:192" - switch { $65 $61 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:192" - case 2'-1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:193" - switch { \dmi_we_i } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:193" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:199" - switch { $71 $69 $67 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:199" - case 3'--1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200" - switch { \dmi_din [1] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:200" - case 1'1 - assign \terminated$next 1'0 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:205" - switch { \dmi_din [3] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:205" - case 1'1 - assign \terminated$next 1'0 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:210" - switch { \dmi_din [4] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:210" - case 1'1 - assign \terminated$next 1'0 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:215" - case 3'-1- - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:219" - case 3'1-- - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:222" - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:226" - case 2'1- - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:239" - switch { \terminate_i } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:239" - case 1'1 - assign \terminated$next 1'1 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \rst - case 1'1 - assign \terminated$next 1'0 - end - sync init - update \terminated 1'0 - sync posedge \clk - update \terminated \terminated$next - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:192" - wire width 1 $73 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:192" - cell $not $74 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \dmi_req_i_1 - connect \Y $73 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:192" - wire width 1 $75 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:192" - cell $and $76 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \dmi_req_i - connect \B $73 - connect \Y $75 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:226" - wire width 1 $77 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:226" - cell $not $78 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \dmi_read_log_data - connect \Y $77 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:226" - wire width 1 $79 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:226" - cell $and $80 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \dmi_read_log_data_1 - connect \B $77 - connect \Y $79 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:199" - wire width 1 $81 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:199" - cell $eq $82 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \dmi_addr_i - connect \B 1'0 - connect \Y $81 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:215" - wire width 1 $83 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:215" - cell $eq $84 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \dmi_addr_i - connect \B 3'100 - connect \Y $83 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:219" - wire width 1 $85 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:219" - cell $eq $86 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \dmi_addr_i - connect \B 3'110 - connect \Y $85 - end - process $group_12 - assign \stopping$next \stopping - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:192" - switch { $79 $75 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:192" - case 2'-1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:193" - switch { \dmi_we_i } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:193" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:199" - switch { $85 $83 $81 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:199" - case 3'--1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:203" - switch { \dmi_din [0] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:203" - case 1'1 - assign \stopping$next 1'1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:210" - switch { \dmi_din [4] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:210" - case 1'1 - assign \stopping$next 1'0 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:215" - case 3'-1- - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:219" - case 3'1-- - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:222" - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:226" - case 2'1- - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:239" - switch { \terminate_i } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:239" - case 1'1 - assign \stopping$next 1'1 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \rst - case 1'1 - assign \stopping$next 1'0 - end - sync init - update \stopping 1'0 - sync posedge \clk - update \stopping \stopping$next - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:135" - wire width 7 \gspr_index - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:135" - wire width 7 \gspr_index$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:192" - wire width 1 $87 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:192" - cell $not $88 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \dmi_req_i_1 - connect \Y $87 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:192" - wire width 1 $89 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:192" - cell $and $90 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \dmi_req_i - connect \B $87 - connect \Y $89 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:226" - wire width 1 $91 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:226" - cell $not $92 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \dmi_read_log_data - connect \Y $91 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:226" - wire width 1 $93 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:226" - cell $and $94 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \dmi_read_log_data_1 - connect \B $91 - connect \Y $93 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:199" - wire width 1 $95 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:199" - cell $eq $96 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \dmi_addr_i - connect \B 1'0 - connect \Y $95 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:215" - wire width 1 $97 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:215" - cell $eq $98 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \dmi_addr_i - connect \B 3'100 - connect \Y $97 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:219" - wire width 1 $99 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:219" - cell $eq $100 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \dmi_addr_i - connect \B 3'110 - connect \Y $99 - end - process $group_13 - assign \gspr_index$next \gspr_index - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:192" - switch { $93 $89 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:192" - case 2'-1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:193" - switch { \dmi_we_i } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:193" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:199" - switch { $99 $97 $95 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:199" - case 3'--1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:215" - case 3'-1- - assign \gspr_index$next \dmi_din [6:0] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:219" - case 3'1-- - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:222" - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:226" - case 2'1- - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \rst - case 1'1 - assign \gspr_index$next 7'0000000 - end - sync init - update \gspr_index 7'0000000 - sync posedge \clk - update \gspr_index \gspr_index$next - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:192" - wire width 1 $101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:192" - cell $not $102 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \dmi_req_i_1 - connect \Y $101 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:192" - wire width 1 $103 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:192" - cell $and $104 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \dmi_req_i - connect \B $101 - connect \Y $103 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:226" - wire width 1 $105 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:226" - cell $not $106 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \dmi_read_log_data - connect \Y $105 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:226" - wire width 1 $107 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:226" - cell $and $108 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \dmi_read_log_data_1 - connect \B $105 - connect \Y $107 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:199" - wire width 1 $109 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:199" - cell $eq $110 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \dmi_addr_i - connect \B 1'0 - connect \Y $109 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:215" - wire width 1 $111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:215" - cell $eq $112 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \dmi_addr_i - connect \B 3'100 - connect \Y $111 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:219" - wire width 1 $113 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:219" - cell $eq $114 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \dmi_addr_i - connect \B 3'110 - connect \Y $113 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:229" - wire width 3 $115 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:229" - wire width 3 $116 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:229" - cell $add $117 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 3 - connect \A \log_dmi_addr [1:0] - connect \B 1'1 - connect \Y $116 - end - connect $115 $116 - process $group_14 - assign \log_dmi_addr$next \log_dmi_addr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:192" - switch { $107 $103 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:192" - case 2'-1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:193" - switch { \dmi_we_i } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:193" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:199" - switch { $113 $111 $109 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:199" - case 3'--1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:215" - case 3'-1- - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:219" - case 3'1-- - assign \log_dmi_addr$next \dmi_din [31:0] - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:222" - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:226" - case 2'1- - assign \log_dmi_addr$next [1:0] $115 [1:0] - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \rst - case 1'1 - assign \log_dmi_addr$next 32'00000000000000000000000000000000 - end - sync init - update \log_dmi_addr 32'00000000000000000000000000000000 - sync posedge \clk - update \log_dmi_addr \log_dmi_addr$next - end - process $group_15 - assign \dmi_read_log_data_1$next \dmi_read_log_data_1 - assign \dmi_read_log_data_1$next \dmi_read_log_data - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \rst - case 1'1 - assign \dmi_read_log_data_1$next 1'0 - end - sync init - update \dmi_read_log_data_1 1'0 - sync posedge \clk - update \dmi_read_log_data_1 \dmi_read_log_data_1$next - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:234" - wire width 1 $118 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:234" - cell $eq $119 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \dmi_addr_i - connect \B 3'111 - connect \Y $118 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:234" - wire width 1 $120 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:234" - cell $and $121 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \dmi_req_i - connect \B $118 - connect \Y $120 - end - process $group_16 - assign \dmi_read_log_data$next \dmi_read_log_data - assign \dmi_read_log_data$next $120 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \rst - case 1'1 - assign \dmi_read_log_data$next 1'0 - end - sync init - update \dmi_read_log_data 1'0 - sync posedge \clk - update \dmi_read_log_data \dmi_read_log_data$next - end - process $group_17 - assign \d_gpr_addr 7'0000000 - assign \d_gpr_addr \gspr_index - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:246" - wire width 1 $122 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:246" - cell $not $123 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \do_step - connect \Y $122 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:246" - wire width 1 $124 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:246" - cell $and $125 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \stopping - connect \B $122 - connect \Y $124 - end - process $group_18 - assign \core_stop_o 1'0 - assign \core_stop_o $124 - sync init - end - process $group_19 - assign \core_rst_o 1'0 - assign \core_rst_o \do_reset - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:91" - wire width 1 \icache_rst_o - process $group_20 - assign \icache_rst_o 1'0 - assign \icache_rst_o \do_icreset - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:114" - wire width 1 \terminated_o - process $group_21 - assign \terminated_o 1'0 - assign \terminated_o \terminated - sync init - end - connect \log_write_addr_o 32'00000000000000000000000000000000 - connect \log_dmi_data 64'0000000000000000000000000000000000000000000000000000000000000000 -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.dec2.dec.dec19" -module \dec19 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" - wire width 32 input 0 \opcode_in - attribute \enum_base_type "Function" - attribute \enum_value_00000000000 "NONE" - attribute \enum_value_00000000010 "ALU" - attribute \enum_value_00000000100 "LDST" - attribute \enum_value_00000001000 "SHIFT_ROT" - attribute \enum_value_00000010000 "LOGICAL" - attribute \enum_value_00000100000 "BRANCH" - attribute \enum_value_00001000000 "CR" - attribute \enum_value_00010000000 "TRAP" - attribute \enum_value_00100000000 "MUL" - attribute \enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 11 output 1 \function_unit - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 7 output 2 \internal_op - attribute \enum_base_type "Form" - attribute \enum_value_00000 "NONE" - attribute \enum_value_00001 "I" - attribute \enum_value_00010 "B" - attribute \enum_value_00011 "SC" - attribute \enum_value_00100 "D" - attribute \enum_value_00101 "DS" - attribute \enum_value_00110 "DQ" - attribute \enum_value_00111 "DX" - attribute \enum_value_01000 "X" - attribute \enum_value_01001 "XL" - attribute \enum_value_01010 "XFX" - attribute \enum_value_01011 "XFL" - attribute \enum_value_01100 "XX1" - attribute \enum_value_01101 "XX2" - attribute \enum_value_01110 "XX3" - attribute \enum_value_01111 "XX4" - attribute \enum_value_10000 "XS" - attribute \enum_value_10001 "XO" - attribute \enum_value_10010 "A" - attribute \enum_value_10011 "M" - attribute \enum_value_10100 "MD" - attribute \enum_value_10101 "MDS" - attribute \enum_value_10110 "VA" - attribute \enum_value_10111 "VC" - attribute \enum_value_11000 "VX" - attribute \enum_value_11001 "EVX" - attribute \enum_value_11010 "EVS" - attribute \enum_value_11011 "Z22" - attribute \enum_value_11100 "Z23" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 5 output 3 \form - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 8 output 4 \asmcode - attribute \enum_base_type "In1Sel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "RA" - attribute \enum_value_010 "RA_OR_ZERO" - attribute \enum_value_011 "SPR" - attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 output 5 \in1_sel - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 4 output 6 \in2_sel - attribute \enum_base_type "In3Sel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RS" - attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 2 output 7 \in3_sel - attribute \enum_base_type "OutSel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RT" - attribute \enum_value_10 "RA" - attribute \enum_value_11 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 2 output 8 \out_sel - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 output 9 \cr_in - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 output 10 \cr_out - attribute \enum_base_type "LdstLen" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "is1B" - attribute \enum_value_0010 "is2B" - attribute \enum_value_0100 "is4B" - attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 4 output 11 \ldst_len - attribute \enum_base_type "LDSTMode" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "update" - attribute \enum_value_10 "cix" - attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 2 output 12 \upd - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 2 output 13 \rc_sel - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 2 output 14 \cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 output 15 \inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 output 16 \inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 output 17 \cry_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 output 18 \br - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 output 19 \sgn_ext - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 output 20 \rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 output 21 \is_32b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 output 22 \sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 output 23 \lk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 output 24 \sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:308" - wire width 10 \opcode_switch - process $group_0 - assign \opcode_switch 10'0000000000 - assign \opcode_switch \opcode_in [10:1] - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:308" - wire width 5 \opcode_switch$1 - process $group_1 - assign \function_unit 11'00000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 10'0000000000 - assign \function_unit 11'00001000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 10'0100000001 - assign \function_unit 11'00001000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 10'0010000001 - assign \function_unit 11'00001000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 10'0100100001 - assign \function_unit 11'00001000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 10'0011100001 - assign \function_unit 11'00001000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 10'0000100001 - assign \function_unit 11'00001000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 10'0111000001 - assign \function_unit 11'00001000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 10'0110100001 - assign \function_unit 11'00001000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 10'0011000001 - assign \function_unit 11'00001000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 10'1000010000 - assign \function_unit 11'00000100000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 10'0000010000 - assign \function_unit 11'00000100000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 10'1000110000 - assign \function_unit 11'00000100000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 10'0010010110 - assign \function_unit 11'00000000010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 10'0000010010 - assign \function_unit 11'00010000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 10'0100010010 - assign \function_unit 11'00010000000 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00010 - assign \function_unit 11'00000000010 - end - sync init - end - process $group_2 - assign \internal_op 7'0000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 10'0000000000 - assign \internal_op 7'0101010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 10'0100000001 - assign \internal_op 7'1000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 10'0010000001 - assign \internal_op 7'1000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 10'0100100001 - assign \internal_op 7'1000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 10'0011100001 - assign \internal_op 7'1000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 10'0000100001 - assign \internal_op 7'1000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 10'0111000001 - assign \internal_op 7'1000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 10'0110100001 - assign \internal_op 7'1000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 10'0011000001 - assign \internal_op 7'1000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 10'1000010000 - assign \internal_op 7'0001000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 10'0000010000 - assign \internal_op 7'0001000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 10'1000110000 - assign \internal_op 7'0001000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 10'0010010110 - assign \internal_op 7'0100100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 10'0000010010 - assign \internal_op 7'1000110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 10'0100010010 - assign \internal_op 7'1000110 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00010 - assign \internal_op 7'0000000 - end - sync init - end - process $group_3 - assign \form 5'00000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 10'0000000000 - assign \form 5'01001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 10'0100000001 - assign \form 5'01001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 10'0010000001 - assign \form 5'01001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 10'0100100001 - assign \form 5'01001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 10'0011100001 - assign \form 5'01001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 10'0000100001 - assign \form 5'01001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 10'0111000001 - assign \form 5'01001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 10'0110100001 - assign \form 5'01001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 10'0011000001 - assign \form 5'01001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 10'1000010000 - assign \form 5'01001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 10'0000010000 - assign \form 5'01001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 10'1000110000 - assign \form 5'01001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 10'0010010110 - assign \form 5'01001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 10'0000010010 - assign \form 5'01001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 10'0100010010 - assign \form 5'01001 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00010 - assign \form 5'00111 - end - sync init - end - process $group_4 - assign \in1_sel 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 10'0000000000 - assign \in1_sel 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 10'0100000001 - assign \in1_sel 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 10'0010000001 - assign \in1_sel 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 10'0100100001 - assign \in1_sel 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 10'0011100001 - assign \in1_sel 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 10'0000100001 - assign \in1_sel 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 10'0111000001 - assign \in1_sel 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 10'0110100001 - assign \in1_sel 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 10'0011000001 - assign \in1_sel 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 10'1000010000 - assign \in1_sel 3'011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 10'0000010000 - assign \in1_sel 3'011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 10'1000110000 - assign \in1_sel 3'011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 10'0010010110 - assign \in1_sel 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 10'0000010010 - assign \in1_sel 3'011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 10'0100010010 - assign \in1_sel 3'011 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00010 - assign \in1_sel 3'000 - end - sync init - end - process $group_5 - assign \in2_sel 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 10'0000000000 - assign \in2_sel 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 10'0100000001 - assign \in2_sel 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 10'0010000001 - assign \in2_sel 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 10'0100100001 - assign \in2_sel 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 10'0011100001 - assign \in2_sel 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 10'0000100001 - assign \in2_sel 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 10'0111000001 - assign \in2_sel 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 10'0110100001 - assign \in2_sel 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 10'0011000001 - assign \in2_sel 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 10'1000010000 - assign \in2_sel 4'1100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 10'0000010000 - assign \in2_sel 4'1100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 10'1000110000 - assign \in2_sel 4'1100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 10'0010010110 - assign \in2_sel 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 10'0000010010 - assign \in2_sel 4'1100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 10'0100010010 - assign \in2_sel 4'1100 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00010 - assign \in2_sel 4'0000 - end - sync init - end - process $group_6 - assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 10'0000000000 - assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 10'0100000001 - assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 10'0010000001 - assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 10'0100100001 - assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 10'0011100001 - assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 10'0000100001 - assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 10'0111000001 - assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 10'0110100001 - assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 10'0011000001 - assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 10'1000010000 - assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 10'0000010000 - assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 10'1000110000 - assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 10'0010010110 - assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 10'0000010010 - assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 10'0100010010 - assign \in3_sel 2'00 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00010 - assign \in3_sel 2'00 - end - sync init - end - process $group_7 - assign \out_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 10'0000000000 - assign \out_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 10'0100000001 - assign \out_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 10'0010000001 - assign \out_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 10'0100100001 - assign \out_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 10'0011100001 - assign \out_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 10'0000100001 - assign \out_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 10'0111000001 - assign \out_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 10'0110100001 - assign \out_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 10'0011000001 - assign \out_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 10'1000010000 - assign \out_sel 2'11 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 10'0000010000 - assign \out_sel 2'11 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 10'1000110000 - assign \out_sel 2'11 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 10'0010010110 - assign \out_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 10'0000010010 - assign \out_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 10'0100010010 - assign \out_sel 2'00 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00010 - assign \out_sel 2'00 - end - sync init - end - process $group_8 - assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 10'0000000000 - assign \cr_in 3'011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 10'0100000001 - assign \cr_in 3'100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 10'0010000001 - assign \cr_in 3'100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 10'0100100001 - assign \cr_in 3'100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 10'0011100001 - assign \cr_in 3'100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 10'0000100001 - assign \cr_in 3'100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 10'0111000001 - assign \cr_in 3'100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 10'0110100001 - assign \cr_in 3'100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 10'0011000001 - assign \cr_in 3'100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 10'1000010000 - assign \cr_in 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 10'0000010000 - assign \cr_in 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 10'1000110000 - assign \cr_in 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 10'0010010110 - assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 10'0000010010 - assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 10'0100010010 - assign \cr_in 3'000 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00010 - assign \cr_in 3'000 - end - sync init - end - process $group_9 - assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 10'0000000000 - assign \cr_out 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 10'0100000001 - assign \cr_out 3'011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 10'0010000001 - assign \cr_out 3'011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 10'0100100001 - assign \cr_out 3'011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 10'0011100001 - assign \cr_out 3'011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 10'0000100001 - assign \cr_out 3'011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 10'0111000001 - assign \cr_out 3'011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 10'0110100001 - assign \cr_out 3'011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 10'0011000001 - assign \cr_out 3'011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 10'1000010000 - assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 10'0000010000 - assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 10'1000110000 - assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 10'0010010110 - assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 10'0000010010 - assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 10'0100010010 - assign \cr_out 3'000 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00010 - assign \cr_out 3'000 - end - sync init - end - process $group_10 - assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 10'0000000000 - assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 10'0100000001 - assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 10'0010000001 - assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 10'0100100001 - assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 10'0011100001 - assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 10'0000100001 - assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 10'0111000001 - assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 10'0110100001 - assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 10'0011000001 - assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 10'1000010000 - assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 10'0000010000 - assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 10'1000110000 - assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 10'0010010110 - assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 10'0000010010 - assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 10'0100010010 - assign \ldst_len 4'0000 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00010 - assign \ldst_len 4'0000 - end - sync init - end - process $group_11 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 10'0000000000 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 10'0100000001 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 10'0010000001 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 10'0100100001 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 10'0011100001 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 10'0000100001 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 10'0111000001 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 10'0110100001 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 10'0011000001 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 10'1000010000 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 10'0000010000 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 10'1000110000 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 10'0010010110 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 10'0000010010 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 10'0100010010 - assign \upd 2'00 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00010 - assign \upd 2'00 - end - sync init - end - process $group_12 - assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 10'0000000000 - assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 10'0100000001 - assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 10'0010000001 - assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 10'0100100001 - assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 10'0011100001 - assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 10'0000100001 - assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 10'0111000001 - assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 10'0110100001 - assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 10'0011000001 - assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 10'1000010000 - assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 10'0000010000 - assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 10'1000110000 - assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 10'0010010110 - assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 10'0000010010 - assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 10'0100010010 - assign \rc_sel 2'00 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00010 - assign \rc_sel 2'10 - end - sync init - end - process $group_13 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 10'0000000000 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 10'0100000001 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 10'0010000001 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 10'0100100001 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 10'0011100001 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 10'0000100001 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 10'0111000001 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 10'0110100001 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 10'0011000001 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 10'1000010000 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 10'0000010000 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 10'1000110000 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 10'0010010110 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 10'0000010010 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 10'0100010010 - assign \cry_in 2'00 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00010 - assign \cry_in 2'00 - end - sync init - end - process $group_14 - assign \asmcode 8'00000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 10'0000000000 - assign \asmcode 8'01101100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 10'0100000001 - assign \asmcode 8'00100101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 10'0010000001 - assign \asmcode 8'00100110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 10'0100100001 - assign \asmcode 8'00100111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 10'0011100001 - assign \asmcode 8'00101000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 10'0000100001 - assign \asmcode 8'00101001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 10'0111000001 - assign \asmcode 8'00101010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 10'0110100001 - assign \asmcode 8'00101011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 10'0011000001 - assign \asmcode 8'00101100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 10'1000010000 - assign \asmcode 8'00010110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 10'0000010000 - assign \asmcode 8'00010111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 10'1000110000 - assign \asmcode 8'00011000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 10'0010010110 - assign \asmcode 8'01001100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 10'0000010010 - assign \asmcode 8'10010001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 10'0100010010 - assign \asmcode 8'01001000 - end - sync init - end - process $group_15 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 10'0000000000 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 10'0100000001 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 10'0010000001 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 10'0100100001 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 10'0011100001 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 10'0000100001 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 10'0111000001 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 10'0110100001 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 10'0011000001 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 10'1000010000 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 10'0000010000 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 10'1000110000 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 10'0010010110 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 10'0000010010 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 10'0100010010 - assign \inv_a 1'0 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00010 - assign \inv_a 1'0 - end - sync init - end - process $group_16 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 10'0000000000 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 10'0100000001 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 10'0010000001 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 10'0100100001 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 10'0011100001 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 10'0000100001 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 10'0111000001 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 10'0110100001 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 10'0011000001 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 10'1000010000 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 10'0000010000 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 10'1000110000 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 10'0010010110 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 10'0000010010 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 10'0100010010 - assign \inv_out 1'0 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00010 - assign \inv_out 1'0 - end - sync init - end - process $group_17 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 10'0000000000 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 10'0100000001 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 10'0010000001 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 10'0100100001 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 10'0011100001 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 10'0000100001 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 10'0111000001 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 10'0110100001 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 10'0011000001 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 10'1000010000 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 10'0000010000 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 10'1000110000 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 10'0010010110 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 10'0000010010 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 10'0100010010 - assign \cry_out 1'0 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00010 - assign \cry_out 1'0 - end - sync init - end - process $group_18 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 10'0000000000 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 10'0100000001 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 10'0010000001 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 10'0100100001 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 10'0011100001 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 10'0000100001 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 10'0111000001 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 10'0110100001 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 10'0011000001 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 10'1000010000 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 10'0000010000 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 10'1000110000 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 10'0010010110 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 10'0000010010 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 10'0100010010 - assign \br 1'0 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00010 - assign \br 1'0 - end - sync init - end - process $group_19 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 10'0000000000 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 10'0100000001 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 10'0010000001 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 10'0100100001 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 10'0011100001 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 10'0000100001 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 10'0111000001 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 10'0110100001 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 10'0011000001 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 10'1000010000 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 10'0000010000 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 10'1000110000 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 10'0010010110 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 10'0000010010 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 10'0100010010 - assign \sgn_ext 1'0 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00010 - assign \sgn_ext 1'0 - end - sync init - end - process $group_20 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 10'0000000000 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 10'0100000001 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 10'0010000001 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 10'0100100001 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 10'0011100001 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 10'0000100001 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 10'0111000001 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 10'0110100001 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 10'0011000001 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 10'1000010000 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 10'0000010000 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 10'1000110000 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 10'0010010110 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 10'0000010010 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 10'0100010010 - assign \rsrv 1'0 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00010 - assign \rsrv 1'0 - end - sync init - end - process $group_21 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 10'0000000000 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 10'0100000001 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 10'0010000001 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 10'0100100001 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 10'0011100001 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 10'0000100001 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 10'0111000001 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 10'0110100001 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 10'0011000001 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 10'1000010000 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 10'0000010000 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 10'1000110000 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 10'0010010110 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 10'0000010010 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 10'0100010010 - assign \is_32b 1'0 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00010 - assign \is_32b 1'0 - end - sync init - end - process $group_22 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 10'0000000000 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 10'0100000001 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 10'0010000001 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 10'0100100001 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 10'0011100001 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 10'0000100001 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 10'0111000001 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 10'0110100001 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 10'0011000001 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 10'1000010000 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 10'0000010000 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 10'1000110000 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 10'0010010110 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 10'0000010010 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 10'0100010010 - assign \sgn 1'0 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00010 - assign \sgn 1'0 - end - sync init - end - process $group_23 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 10'0000000000 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 10'0100000001 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 10'0010000001 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 10'0100100001 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 10'0011100001 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 10'0000100001 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 10'0111000001 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 10'0110100001 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 10'0011000001 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 10'1000010000 - assign \lk 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 10'0000010000 - assign \lk 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 10'1000110000 - assign \lk 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 10'0010010110 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 10'0000010010 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 10'0100010010 - assign \lk 1'0 - end - attribute \src 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attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 4 output 6 \in2_sel - attribute \enum_base_type "In3Sel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RS" - attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 2 output 7 \in3_sel - attribute \enum_base_type "OutSel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RT" - attribute \enum_value_10 "RA" - attribute \enum_value_11 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 2 output 8 \out_sel - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 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"/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 2 output 12 \upd - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 2 output 13 \rc_sel - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 2 output 14 \cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 output 15 \inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 output 16 \inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 output 17 \cry_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 output 18 \br - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 output 19 \sgn_ext - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 output 20 \rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 output 21 \is_32b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 output 22 \sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 output 23 \lk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 output 24 \sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:308" - wire width 4 \opcode_switch - process $group_0 - assign \opcode_switch 4'0000 - assign \opcode_switch \opcode_in [4:1] - sync init - end - process $group_1 - assign \function_unit 11'00000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 4'0100 - assign \function_unit 11'00000001000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 4'0101 - assign \function_unit 11'00000001000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 4'0000 - assign \function_unit 11'00000001000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 4'0001 - assign \function_unit 11'00000001000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 4'0010 - assign \function_unit 11'00000001000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 4'0011 - assign \function_unit 11'00000001000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 4'0110 - assign \function_unit 11'00000001000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 4'0111 - assign \function_unit 11'00000001000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 4'1000 - assign \function_unit 11'00000001000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 4'1001 - assign \function_unit 11'00000001000 - end - sync init - end - process $group_2 - assign \internal_op 7'0000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 4'0100 - assign \internal_op 7'0111000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 4'0101 - assign \internal_op 7'0111000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 4'0000 - assign \internal_op 7'0111001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 4'0001 - assign \internal_op 7'0111001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 4'0010 - assign \internal_op 7'0111010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 4'0011 - assign \internal_op 7'0111010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 4'0110 - assign \internal_op 7'0111000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 4'0111 - assign \internal_op 7'0111000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 4'1000 - assign \internal_op 7'0111001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 4'1001 - assign \internal_op 7'0111010 - end - sync init - end - process $group_3 - assign \form 5'00000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 4'0100 - assign \form 5'10100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 4'0101 - assign \form 5'10100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 4'0000 - assign \form 5'10101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 4'0001 - assign \form 5'10101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 4'0010 - assign \form 5'10100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 4'0011 - assign \form 5'10100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 4'0110 - assign \form 5'10100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 4'0111 - assign \form 5'10100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 4'1000 - assign \form 5'10100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 4'1001 - assign \form 5'10100 - end - sync init - end - process $group_4 - assign \in1_sel 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 4'0100 - assign \in1_sel 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 4'0101 - assign \in1_sel 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 4'0000 - assign \in1_sel 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 4'0001 - assign \in1_sel 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 4'0010 - assign \in1_sel 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 4'0011 - assign \in1_sel 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 4'0110 - assign \in1_sel 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 4'0111 - assign \in1_sel 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 4'1000 - assign \in1_sel 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 4'1001 - assign \in1_sel 3'000 - end - sync init - end - process $group_5 - assign \in2_sel 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 4'0100 - assign \in2_sel 4'1010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 4'0101 - assign \in2_sel 4'1010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 4'0000 - assign \in2_sel 4'1010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 4'0001 - assign \in2_sel 4'1010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 4'0010 - assign \in2_sel 4'1010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 4'0011 - assign \in2_sel 4'1010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 4'0110 - assign \in2_sel 4'1010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 4'0111 - assign \in2_sel 4'1010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 4'1000 - assign \in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 4'1001 - assign \in2_sel 4'0001 - end - sync init - end - process $group_6 - assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 4'0100 - assign \in3_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 4'0101 - assign \in3_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 4'0000 - assign \in3_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 4'0001 - assign \in3_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 4'0010 - assign \in3_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 4'0011 - assign \in3_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 4'0110 - assign \in3_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 4'0111 - assign \in3_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 4'1000 - assign \in3_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 4'1001 - assign \in3_sel 2'01 - end - sync init - end - process $group_7 - assign \out_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 4'0100 - assign \out_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 4'0101 - assign \out_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 4'0000 - assign \out_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 4'0001 - assign \out_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 4'0010 - assign \out_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 4'0011 - assign \out_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 4'0110 - assign \out_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 4'0111 - assign \out_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 4'1000 - assign \out_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 4'1001 - assign \out_sel 2'10 - end - sync init - end - process $group_8 - assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 4'0100 - assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 4'0101 - assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 4'0000 - assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 4'0001 - assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 4'0010 - assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 4'0011 - assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 4'0110 - assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 4'0111 - assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 4'1000 - assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 4'1001 - assign \cr_in 3'000 - end - sync init - end - process $group_9 - assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 4'0100 - assign \cr_out 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 4'0101 - assign \cr_out 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 4'0000 - assign \cr_out 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 4'0001 - assign \cr_out 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 4'0010 - assign \cr_out 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 4'0011 - assign \cr_out 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 4'0110 - assign \cr_out 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 4'0111 - assign \cr_out 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 4'1000 - assign \cr_out 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 4'1001 - assign \cr_out 3'001 - end - sync init - end - process $group_10 - assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 4'0100 - assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 4'0101 - assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 4'0000 - assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 4'0001 - assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 4'0010 - assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 4'0011 - assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 4'0110 - assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 4'0111 - assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 4'1000 - assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 4'1001 - assign \ldst_len 4'0000 - end - sync init - end - process $group_11 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 4'0100 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 4'0101 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 4'0000 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 4'0001 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 4'0010 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 4'0011 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 4'0110 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 4'0111 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 4'1000 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 4'1001 - assign \upd 2'00 - end - sync init - end - process $group_12 - assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 4'0100 - assign \rc_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 4'0101 - assign \rc_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 4'0000 - assign \rc_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 4'0001 - assign \rc_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 4'0010 - assign \rc_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 4'0011 - assign \rc_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 4'0110 - assign \rc_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 4'0111 - assign \rc_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 4'1000 - assign \rc_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 4'1001 - assign \rc_sel 2'10 - end - sync init - end - process $group_13 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 4'0100 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 4'0101 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 4'0000 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 4'0001 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 4'0010 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 4'0011 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 4'0110 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 4'0111 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 4'1000 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 4'1001 - assign \cry_in 2'00 - end - sync init - end - process $group_14 - assign \asmcode 8'00000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 4'0100 - assign \asmcode 8'10010100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 4'0101 - assign \asmcode 8'10010100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 4'0000 - assign \asmcode 8'10010101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 4'0001 - assign \asmcode 8'10010101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 4'0010 - assign \asmcode 8'10010110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 4'0011 - assign \asmcode 8'10010110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 4'0110 - assign \asmcode 8'10010111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 4'0111 - assign \asmcode 8'10010111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 4'1000 - assign \asmcode 8'10010010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 4'1001 - assign \asmcode 8'10010011 - end - sync init - end - process $group_15 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 4'0100 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 4'0101 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 4'0000 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 4'0001 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 4'0010 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 4'0011 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 4'0110 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 4'0111 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 4'1000 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 4'1001 - assign \inv_a 1'0 - end - sync init - end - process $group_16 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 4'0100 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 4'0101 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 4'0000 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 4'0001 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 4'0010 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 4'0011 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 4'0110 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 4'0111 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 4'1000 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 4'1001 - assign \inv_out 1'0 - end - sync init - end - process $group_17 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 4'0100 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 4'0101 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 4'0000 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 4'0001 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 4'0010 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 4'0011 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 4'0110 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 4'0111 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 4'1000 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 4'1001 - assign \cry_out 1'0 - end - sync init - end - process $group_18 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 4'0100 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 4'0101 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 4'0000 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 4'0001 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 4'0010 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 4'0011 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 4'0110 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 4'0111 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 4'1000 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 4'1001 - assign \br 1'0 - end - sync init - end - process $group_19 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 4'0100 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 4'0101 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 4'0000 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 4'0001 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 4'0010 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 4'0011 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 4'0110 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 4'0111 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 4'1000 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 4'1001 - assign \sgn_ext 1'0 - end - sync init - end - process $group_20 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 4'0100 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 4'0101 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 4'0000 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 4'0001 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 4'0010 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 4'0011 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 4'0110 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 4'0111 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 4'1000 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 4'1001 - assign \rsrv 1'0 - end - sync init - end - process $group_21 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 4'0100 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 4'0101 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 4'0000 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 4'0001 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 4'0010 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 4'0011 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 4'0110 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 4'0111 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 4'1000 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 4'1001 - assign \is_32b 1'0 - end - sync init - end - process $group_22 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 4'0100 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 4'0101 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 4'0000 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 4'0001 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 4'0010 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 4'0011 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 4'0110 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 4'0111 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 4'1000 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 4'1001 - assign \sgn 1'0 - end - sync init - end - process $group_23 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 4'0100 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 4'0101 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 4'0000 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 4'0001 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 4'0010 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 4'0011 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 4'0110 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 4'0111 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 4'1000 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 4'1001 - assign \lk 1'0 - end - sync init - end - process $group_24 - assign \sgl_pipe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 4'0100 - assign \sgl_pipe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 4'0101 - assign \sgl_pipe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 4'0000 - assign \sgl_pipe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 4'0001 - assign \sgl_pipe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 4'0010 - assign \sgl_pipe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 4'0011 - assign \sgl_pipe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 4'0110 - assign \sgl_pipe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 4'0111 - assign \sgl_pipe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 4'1000 - assign \sgl_pipe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 4'1001 - assign \sgl_pipe 1'0 - end - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.dec2.dec.dec31.dec_sub10" -module \dec_sub10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" - wire width 32 input 0 \opcode_in - attribute \enum_base_type "Function" - attribute \enum_value_00000000000 "NONE" - attribute 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attribute \enum_value_00101 "DS" - attribute \enum_value_00110 "DQ" - attribute \enum_value_00111 "DX" - attribute \enum_value_01000 "X" - attribute \enum_value_01001 "XL" - attribute \enum_value_01010 "XFX" - attribute \enum_value_01011 "XFL" - attribute \enum_value_01100 "XX1" - attribute \enum_value_01101 "XX2" - attribute \enum_value_01110 "XX3" - attribute \enum_value_01111 "XX4" - attribute \enum_value_10000 "XS" - attribute \enum_value_10001 "XO" - attribute \enum_value_10010 "A" - attribute \enum_value_10011 "M" - attribute \enum_value_10100 "MD" - attribute \enum_value_10101 "MDS" - attribute \enum_value_10110 "VA" - attribute \enum_value_10111 "VC" - attribute \enum_value_11000 "VX" - attribute \enum_value_11001 "EVX" - attribute \enum_value_11010 "EVS" - attribute \enum_value_11011 "Z22" - attribute \enum_value_11100 "Z23" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 5 output 3 \form - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 8 output 4 \asmcode - attribute \enum_base_type "In1Sel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "RA" - attribute \enum_value_010 "RA_OR_ZERO" - attribute \enum_value_011 "SPR" - attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 output 5 \in1_sel - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 4 output 6 \in2_sel - attribute \enum_base_type "In3Sel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RS" - attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 2 output 7 \in3_sel - attribute \enum_base_type "OutSel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RT" - attribute \enum_value_10 "RA" - attribute \enum_value_11 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 2 output 8 \out_sel - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 output 9 \cr_in - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 output 10 \cr_out - attribute \enum_base_type "LdstLen" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "is1B" - attribute \enum_value_0010 "is2B" - attribute \enum_value_0100 "is4B" - attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 4 output 11 \ldst_len - attribute \enum_base_type "LDSTMode" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "update" - attribute \enum_value_10 "cix" - attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 2 output 12 \upd - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 2 output 13 \rc_sel - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 2 output 14 \cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 output 15 \inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 output 16 \inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 output 17 \cry_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 output 18 \br - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 output 19 \sgn_ext - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 output 20 \rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 output 21 \is_32b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 output 22 \sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 output 23 \lk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 output 24 \sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:308" - wire width 5 \opcode_switch - process $group_0 - assign \opcode_switch 5'00000 - assign \opcode_switch \opcode_in [10:6] - sync init - end - process $group_1 - assign \function_unit 11'00000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01000 - assign \function_unit 11'00000000010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11000 - assign \function_unit 11'00000000010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \function_unit 11'00000000010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10000 - assign \function_unit 11'00000000010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00100 - assign \function_unit 11'00000000010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10100 - assign \function_unit 11'00000000010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00111 - assign \function_unit 11'00000000010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10111 - assign \function_unit 11'00000000010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00110 - assign \function_unit 11'00000000010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10110 - assign \function_unit 11'00000000010 - end - sync init - end - process $group_2 - assign \internal_op 7'0000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01000 - assign \internal_op 7'0000010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11000 - assign \internal_op 7'0000010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \internal_op 7'0000010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10000 - assign \internal_op 7'0000010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00100 - assign \internal_op 7'0000010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10100 - assign \internal_op 7'0000010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00111 - assign \internal_op 7'0000010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10111 - assign \internal_op 7'0000010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00110 - assign \internal_op 7'0000010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10110 - assign \internal_op 7'0000010 - end - sync init - end - process $group_3 - assign \form 5'00000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01000 - assign \form 5'10001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11000 - assign \form 5'10001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \form 5'10001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10000 - assign \form 5'10001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00100 - assign \form 5'10001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10100 - assign \form 5'10001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00111 - assign \form 5'10001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10111 - assign \form 5'10001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00110 - assign \form 5'10001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10110 - assign \form 5'10001 - end - sync init - end - process $group_4 - assign \in1_sel 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01000 - assign \in1_sel 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11000 - assign \in1_sel 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \in1_sel 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10000 - assign \in1_sel 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00100 - assign \in1_sel 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10100 - assign \in1_sel 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00111 - assign \in1_sel 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10111 - assign \in1_sel 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00110 - assign \in1_sel 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10110 - assign \in1_sel 3'001 - end - sync init - end - process $group_5 - assign \in2_sel 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01000 - assign \in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11000 - assign \in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10000 - assign \in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00100 - assign \in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10100 - assign \in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00111 - assign \in2_sel 4'1001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10111 - assign \in2_sel 4'1001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00110 - assign \in2_sel 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10110 - assign \in2_sel 4'0000 - end - sync init - end - process $group_6 - assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01000 - assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11000 - assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10000 - assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00100 - assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10100 - assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00111 - assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10111 - assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00110 - assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10110 - assign \in3_sel 2'00 - end - sync init - end - process $group_7 - assign \out_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01000 - assign \out_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11000 - assign \out_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \out_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10000 - assign \out_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00100 - assign \out_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10100 - assign \out_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00111 - assign \out_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10111 - assign \out_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00110 - assign \out_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10110 - assign \out_sel 2'01 - end - sync init - end - process $group_8 - assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01000 - assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11000 - assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10000 - assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00100 - assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10100 - assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00111 - assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10111 - assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00110 - assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10110 - assign \cr_in 3'000 - end - sync init - end - process $group_9 - assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01000 - assign \cr_out 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11000 - assign \cr_out 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \cr_out 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10000 - assign \cr_out 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00100 - assign \cr_out 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10100 - assign \cr_out 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00111 - assign \cr_out 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10111 - assign \cr_out 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00110 - assign \cr_out 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10110 - assign \cr_out 3'001 - end - sync init - end - process $group_10 - assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01000 - assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11000 - assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10000 - assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00100 - assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10100 - assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00111 - assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10111 - assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00110 - assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10110 - assign \ldst_len 4'0000 - end - sync init - end - process $group_11 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01000 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11000 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10000 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00100 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10100 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00111 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10111 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00110 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10110 - assign \upd 2'00 - end - sync init - end - process $group_12 - assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01000 - assign \rc_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11000 - assign \rc_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \rc_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10000 - assign \rc_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00100 - assign \rc_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10100 - assign \rc_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00111 - assign \rc_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10111 - assign \rc_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00110 - assign \rc_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10110 - assign \rc_sel 2'10 - end - sync init - end - process $group_13 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01000 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11000 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10000 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00100 - assign \cry_in 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10100 - assign \cry_in 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00111 - assign \cry_in 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10111 - assign \cry_in 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00110 - assign \cry_in 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10110 - assign \cry_in 2'10 - end - sync init - end - process $group_14 - assign \asmcode 8'00000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01000 - assign \asmcode 8'00000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11000 - assign \asmcode 8'00001100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \asmcode 8'00000010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10000 - assign \asmcode 8'00000011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00100 - assign \asmcode 8'00000100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10100 - assign \asmcode 8'00000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00111 - assign \asmcode 8'00001010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10111 - assign \asmcode 8'00001011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00110 - assign \asmcode 8'00001101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10110 - assign \asmcode 8'00001110 - end - sync init - end - process $group_15 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01000 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11000 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10000 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00100 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10100 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00111 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10111 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00110 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10110 - assign \inv_a 1'0 - end - sync init - end - process $group_16 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01000 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11000 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10000 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00100 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10100 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00111 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10111 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00110 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10110 - assign \inv_out 1'0 - end - sync init - end - process $group_17 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01000 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11000 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \cry_out 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10000 - assign \cry_out 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00100 - assign \cry_out 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10100 - assign \cry_out 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00111 - assign \cry_out 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10111 - assign \cry_out 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00110 - assign \cry_out 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10110 - assign \cry_out 1'1 - end - sync init - end - process $group_18 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01000 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11000 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10000 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00100 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10100 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00111 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10111 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00110 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10110 - assign \br 1'0 - end - sync init - end - process $group_19 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01000 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11000 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10000 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00100 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10100 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00111 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10111 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00110 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10110 - assign \sgn_ext 1'0 - end - sync init - end - process $group_20 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01000 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11000 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10000 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00100 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10100 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00111 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10111 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00110 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10110 - assign \rsrv 1'0 - end - sync init - end - process $group_21 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01000 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11000 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10000 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00100 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10100 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00111 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10111 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00110 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10110 - assign \is_32b 1'0 - end - sync init - end - process $group_22 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01000 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11000 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10000 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00100 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10100 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00111 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10111 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00110 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10110 - assign \sgn 1'0 - end - sync init - end - process $group_23 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01000 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11000 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10000 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00100 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10100 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00111 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10111 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00110 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10110 - assign \lk 1'0 - end - sync init - end - process $group_24 - assign \sgl_pipe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01000 - assign \sgl_pipe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11000 - assign \sgl_pipe 1'0 - attribute \src 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\enum_value_11000 "VX" - attribute \enum_value_11001 "EVX" - attribute \enum_value_11010 "EVS" - attribute \enum_value_11011 "Z22" - attribute \enum_value_11100 "Z23" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 5 output 3 \form - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 8 output 4 \asmcode - attribute \enum_base_type "In1Sel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "RA" - attribute \enum_value_010 "RA_OR_ZERO" - attribute \enum_value_011 "SPR" - attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 output 5 \in1_sel - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 4 output 6 \in2_sel - attribute \enum_base_type "In3Sel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RS" - attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 2 output 7 \in3_sel - attribute \enum_base_type "OutSel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RT" - attribute \enum_value_10 "RA" - attribute \enum_value_11 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 2 output 8 \out_sel - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 output 9 \cr_in - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 output 10 \cr_out - attribute \enum_base_type "LdstLen" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "is1B" - attribute \enum_value_0010 "is2B" - attribute \enum_value_0100 "is4B" - attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 4 output 11 \ldst_len - attribute \enum_base_type "LDSTMode" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "update" - attribute \enum_value_10 "cix" - attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 2 output 12 \upd - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 2 output 13 \rc_sel - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 2 output 14 \cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 output 15 \inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 output 16 \inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 output 17 \cry_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 output 18 \br - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 output 19 \sgn_ext - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 output 20 \rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 output 21 \is_32b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 output 22 \sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 output 23 \lk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 output 24 \sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:308" - wire width 5 \opcode_switch - process $group_0 - assign \opcode_switch 5'00000 - assign \opcode_switch \opcode_in [10:6] - sync init - end - process $group_1 - assign \function_unit 11'00000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \function_unit 11'00000010000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00001 - assign \function_unit 11'00000010000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00111 - assign \function_unit 11'00000010000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01111 - assign \function_unit 11'00000010000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01000 - assign \function_unit 11'00000010000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01110 - assign \function_unit 11'00000010000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00011 - assign \function_unit 11'00000010000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01101 - assign \function_unit 11'00000010000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01100 - assign \function_unit 11'00000010000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01001 - assign \function_unit 11'00000010000 - end - sync init - end - process $group_2 - assign \internal_op 7'0000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \internal_op 7'0000100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00001 - assign \internal_op 7'0000100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00111 - assign \internal_op 7'0001001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01111 - assign \internal_op 7'0001011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01000 - assign \internal_op 7'1000011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01110 - assign \internal_op 7'0000100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00011 - assign \internal_op 7'0110101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01101 - assign \internal_op 7'0110101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01100 - assign \internal_op 7'0110101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01001 - assign \internal_op 7'1000011 - end - sync init - end - process $group_3 - assign \form 5'00000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \form 5'01000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00001 - assign \form 5'01000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00111 - assign \form 5'01000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01111 - assign \form 5'01000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01000 - assign \form 5'01000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01110 - assign \form 5'01000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00011 - assign \form 5'01000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01101 - assign \form 5'01000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01100 - assign \form 5'01000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01001 - assign \form 5'01000 - end - sync init - end - process $group_4 - assign \in1_sel 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \in1_sel 3'100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00001 - assign \in1_sel 3'100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00111 - assign \in1_sel 3'100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01111 - assign \in1_sel 3'100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01000 - assign \in1_sel 3'100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01110 - assign \in1_sel 3'100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00011 - assign \in1_sel 3'100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01101 - assign \in1_sel 3'100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01100 - assign \in1_sel 3'100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01001 - assign \in1_sel 3'100 - end - sync init - end - process $group_5 - assign \in2_sel 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00001 - assign \in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00111 - assign \in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01111 - assign \in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01000 - assign \in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01110 - assign \in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00011 - assign \in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01101 - assign \in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01100 - assign \in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01001 - assign \in2_sel 4'0001 - end - sync init - end - process $group_6 - assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00001 - assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00111 - assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01111 - assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01000 - assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01110 - assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00011 - assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01101 - assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01100 - assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01001 - assign \in3_sel 2'00 - end - sync init - end - process $group_7 - assign \out_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \out_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00001 - assign \out_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00111 - assign \out_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01111 - assign \out_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01000 - assign \out_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01110 - assign \out_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00011 - assign \out_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01101 - assign \out_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01100 - assign \out_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01001 - assign \out_sel 2'10 - end - sync init - end - process $group_8 - assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00001 - assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00111 - assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01111 - assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01000 - assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01110 - assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00011 - assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01101 - assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01100 - assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01001 - assign \cr_in 3'000 - end - sync init - end - process $group_9 - assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \cr_out 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00001 - assign \cr_out 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00111 - assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01111 - assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01000 - assign \cr_out 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01110 - assign \cr_out 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00011 - assign \cr_out 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01101 - assign \cr_out 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01100 - assign \cr_out 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01001 - assign \cr_out 3'001 - end - sync init - end - process $group_10 - assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00001 - assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00111 - assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01111 - assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01000 - assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01110 - assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00011 - assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01101 - assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01100 - assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01001 - assign \ldst_len 4'0000 - end - sync init - end - process $group_11 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00001 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00111 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01111 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01000 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01110 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00011 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01101 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01100 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01001 - assign \upd 2'00 - end - sync init - end - process $group_12 - assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \rc_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00001 - assign \rc_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00111 - assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01111 - assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01000 - assign \rc_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01110 - assign \rc_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00011 - assign \rc_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01101 - assign \rc_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01100 - assign \rc_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01001 - assign \rc_sel 2'10 - end - sync init - end - process $group_13 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00001 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00111 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01111 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01000 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01110 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00011 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01101 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01100 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01001 - assign \cry_in 2'00 - end - sync init - end - process $group_14 - assign \asmcode 8'00000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \asmcode 8'00001111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00001 - assign \asmcode 8'00010000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00111 - assign \asmcode 8'00011001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01111 - assign \asmcode 8'00011011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01000 - assign \asmcode 8'01000011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01110 - assign \asmcode 8'10000011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00011 - assign \asmcode 8'10000111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01101 - assign \asmcode 8'10001000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01100 - assign \asmcode 8'10001001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01001 - assign \asmcode 8'11001101 - end - sync init - end - process $group_15 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00001 - assign \inv_a 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00111 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01111 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01000 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01110 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00011 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01101 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01100 - assign \inv_a 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01001 - assign \inv_a 1'0 - end - sync init - end - process $group_16 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00001 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00111 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01111 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01000 - assign \inv_out 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01110 - assign \inv_out 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00011 - assign \inv_out 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01101 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01100 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01001 - assign \inv_out 1'0 - end - sync init - end - process $group_17 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00001 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00111 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01111 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01000 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01110 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00011 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01101 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01100 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01001 - assign \cry_out 1'0 - end - sync init - end - process $group_18 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00001 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00111 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01111 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01000 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01110 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00011 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01101 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01100 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01001 - assign \br 1'0 - end - sync init - end - process $group_19 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00001 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00111 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01111 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01000 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01110 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00011 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01101 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01100 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01001 - assign \sgn_ext 1'0 - end - sync init - end - process $group_20 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00001 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00111 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01111 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01000 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01110 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00011 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01101 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01100 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01001 - assign \rsrv 1'0 - end - sync init - end - process $group_21 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00001 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00111 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01111 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01000 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01110 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00011 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01101 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01100 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01001 - assign \is_32b 1'0 - end - sync init - end - process $group_22 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00001 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00111 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01111 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01000 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01110 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00011 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01101 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01100 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01001 - assign \sgn 1'0 - end - sync init - end - process $group_23 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00001 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00111 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01111 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01000 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01110 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00011 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01101 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01100 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01001 - assign \lk 1'0 - end - sync init - end - process $group_24 - assign \sgl_pipe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \sgl_pipe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00001 - assign \sgl_pipe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00111 - assign \sgl_pipe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01111 - assign \sgl_pipe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01000 - assign \sgl_pipe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01110 - assign \sgl_pipe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00011 - assign \sgl_pipe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01101 - assign \sgl_pipe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01100 - assign \sgl_pipe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01001 - assign \sgl_pipe 1'0 - end - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.dec2.dec.dec31.dec_sub0" -module \dec_sub0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" - wire width 32 input 0 \opcode_in - attribute \enum_base_type "Function" - attribute \enum_value_00000000000 "NONE" - attribute \enum_value_00000000010 "ALU" - attribute \enum_value_00000000100 "LDST" - attribute \enum_value_00000001000 "SHIFT_ROT" - attribute \enum_value_00000010000 "LOGICAL" - attribute \enum_value_00000100000 "BRANCH" - attribute \enum_value_00001000000 "CR" - attribute \enum_value_00010000000 "TRAP" - attribute \enum_value_00100000000 "MUL" - attribute \enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 11 output 1 \function_unit - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 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attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 output 10 \cr_out - attribute \enum_base_type "LdstLen" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "is1B" - attribute \enum_value_0010 "is2B" - attribute \enum_value_0100 "is4B" - attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 4 output 11 \ldst_len - attribute \enum_base_type "LDSTMode" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "update" - attribute \enum_value_10 "cix" - attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 2 output 12 \upd - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 2 output 13 \rc_sel - attribute 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"/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 output 21 \is_32b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 output 22 \sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 output 23 \lk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 output 24 \sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:308" - wire width 5 \opcode_switch - process $group_0 - assign \opcode_switch 5'00000 - assign \opcode_switch \opcode_in [10:6] - sync init - end - process $group_1 - assign \function_unit 11'00000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \function_unit 11'00000000010 - attribute \src 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"/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \in1_sel 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00111 - assign \in1_sel 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00001 - assign \in1_sel 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00100 - assign \in1_sel 3'000 - end - sync init - end - process $group_5 - assign \in2_sel 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00111 - assign \in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00001 - assign \in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00100 - assign \in2_sel 4'0000 - end - sync init - end - process $group_6 - assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00111 - assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00001 - assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00100 - assign \in3_sel 2'00 - end - sync init - end - process $group_7 - assign \out_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \out_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00111 - assign \out_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00001 - assign \out_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00100 - assign \out_sel 2'01 - end - sync init - end - process $group_8 - assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00111 - assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00001 - assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00100 - assign \cr_in 3'011 - end - sync init - end - process $group_9 - assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \cr_out 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00111 - assign \cr_out 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00001 - assign \cr_out 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00100 - assign \cr_out 3'000 - end - sync init - end - process $group_10 - assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00111 - assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00001 - assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00100 - assign \ldst_len 4'0000 - end - sync init - end - process $group_11 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00111 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00001 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00100 - assign \upd 2'00 - end - sync init - end - process $group_12 - assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00111 - assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00001 - assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00100 - assign \rc_sel 2'00 - end - sync init - end - process $group_13 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \cry_in 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00111 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00001 - assign \cry_in 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00100 - assign \cry_in 2'00 - end - sync init - end - process $group_14 - assign \asmcode 8'00000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \asmcode 8'00011010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00111 - assign \asmcode 8'00011100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00001 - assign \asmcode 8'00011110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00100 - assign \asmcode 8'10011011 - end - sync init - end - process $group_15 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \inv_a 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00111 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00001 - assign \inv_a 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00100 - assign \inv_a 1'0 - end - sync init - end - process $group_16 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00111 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00001 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00100 - assign \inv_out 1'0 - end - sync init - end - process $group_17 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00111 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00001 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00100 - assign \cry_out 1'0 - end - sync init - end - process $group_18 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00111 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00001 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00100 - assign \br 1'0 - end - sync init - end - process $group_19 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src 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\cry_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 output 18 \br - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 output 19 \sgn_ext - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 output 20 \rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 output 21 \is_32b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 output 22 \sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 output 23 \lk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 output 24 \sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:308" - wire width 5 \opcode_switch - process $group_0 - assign \opcode_switch 5'00000 - assign \opcode_switch \opcode_in [10:6] - sync init - end - process $group_1 - assign \function_unit 11'00000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00001 - assign \function_unit 11'00000010000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \function_unit 11'00000010000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10001 - assign \function_unit 11'00000010000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10000 - assign \function_unit 11'00000010000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11101 - assign \function_unit 11'00000000010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11100 - assign \function_unit 11'00000000010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11110 - assign \function_unit 11'00000000010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11011 - assign \function_unit 11'00000001000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00011 - assign \function_unit 11'00000010000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01111 - assign \function_unit 11'00000010000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01011 - assign \function_unit 11'00000010000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00101 - assign \function_unit 11'00000010000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00100 - assign \function_unit 11'00000010000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11000 - assign \function_unit 11'00000001000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11001 - assign \function_unit 11'00000001000 - end - sync init - end - process $group_2 - assign \internal_op 7'0000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00001 - assign \internal_op 7'0001110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \internal_op 7'0001110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10001 - assign \internal_op 7'0001110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10000 - assign \internal_op 7'0001110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11101 - assign \internal_op 7'0011111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11100 - assign \internal_op 7'0011111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11110 - assign \internal_op 7'0011111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11011 - assign \internal_op 7'0100000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00011 - assign \internal_op 7'0110110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01111 - assign \internal_op 7'0110110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01011 - assign \internal_op 7'0110110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00101 - assign \internal_op 7'0110111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00100 - assign \internal_op 7'0110111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11000 - assign \internal_op 7'0111101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11001 - assign \internal_op 7'0111101 - end - sync init - end - process $group_3 - assign \form 5'00000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00001 - assign \form 5'01000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \form 5'01000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10001 - assign \form 5'01000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10000 - assign \form 5'01000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11101 - assign \form 5'01000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11100 - assign \form 5'01000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11110 - assign \form 5'01000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11011 - assign \form 5'10000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00011 - assign \form 5'01000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01111 - assign \form 5'01000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01011 - assign \form 5'01000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00101 - assign \form 5'01000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00100 - assign \form 5'01000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11000 - assign \form 5'01000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11001 - assign \form 5'10000 - end - sync init - end - process $group_4 - assign \in1_sel 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00001 - assign \in1_sel 3'100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \in1_sel 3'100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10001 - assign \in1_sel 3'100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10000 - assign \in1_sel 3'100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11101 - assign \in1_sel 3'100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11100 - assign \in1_sel 3'100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11110 - assign \in1_sel 3'100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11011 - assign \in1_sel 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00011 - assign \in1_sel 3'100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01111 - assign \in1_sel 3'100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01011 - assign \in1_sel 3'100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00101 - assign \in1_sel 3'100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00100 - assign \in1_sel 3'100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11000 - assign \in1_sel 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11001 - assign \in1_sel 3'000 - end - sync init - end - process $group_5 - assign \in2_sel 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00001 - assign \in2_sel 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \in2_sel 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10001 - assign \in2_sel 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10000 - assign \in2_sel 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11101 - assign \in2_sel 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11100 - assign \in2_sel 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11110 - assign \in2_sel 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11011 - assign \in2_sel 4'1010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00011 - assign \in2_sel 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01111 - assign \in2_sel 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01011 - assign \in2_sel 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00101 - assign \in2_sel 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00100 - assign \in2_sel 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11000 - assign \in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11001 - assign \in2_sel 4'1010 - end - sync init - end - process $group_6 - assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00001 - assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10001 - assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10000 - assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11101 - assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11100 - assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11110 - assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11011 - assign \in3_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00011 - assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01111 - assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01011 - assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00101 - assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00100 - assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11000 - assign \in3_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11001 - assign \in3_sel 2'01 - end - sync init - end - process $group_7 - assign \out_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00001 - assign \out_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \out_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10001 - assign \out_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10000 - assign \out_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11101 - assign \out_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11100 - assign \out_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11110 - assign \out_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11011 - assign \out_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00011 - assign \out_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01111 - assign \out_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01011 - assign \out_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00101 - assign \out_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00100 - assign \out_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11000 - assign \out_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11001 - assign \out_sel 2'10 - end - sync init - end - process $group_8 - assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00001 - assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10001 - assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10000 - assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11101 - assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11100 - assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11110 - assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11011 - assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00011 - assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01111 - assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01011 - assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00101 - assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00100 - assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11000 - assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11001 - assign \cr_in 3'000 - end - sync init - end - process $group_9 - assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00001 - assign \cr_out 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \cr_out 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10001 - assign \cr_out 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10000 - assign \cr_out 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11101 - assign \cr_out 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11100 - assign \cr_out 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11110 - assign \cr_out 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11011 - assign \cr_out 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00011 - assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01111 - assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01011 - assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00101 - assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00100 - assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11000 - assign \cr_out 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11001 - assign \cr_out 3'001 - end - sync init - end - process $group_10 - assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00001 - assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10001 - assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10000 - assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11101 - assign \ldst_len 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11100 - assign \ldst_len 4'0010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11110 - assign \ldst_len 4'0100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11011 - assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00011 - assign \ldst_len 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01111 - assign \ldst_len 4'1000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01011 - assign \ldst_len 4'0100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00101 - assign \ldst_len 4'1000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00100 - assign \ldst_len 4'0100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11000 - assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11001 - assign \ldst_len 4'0000 - end - sync init - end - process $group_11 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00001 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10001 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10000 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11101 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11100 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11110 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11011 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00011 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01111 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01011 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00101 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00100 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11000 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11001 - assign \upd 2'00 - end - sync init - end - process $group_12 - assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00001 - assign \rc_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \rc_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10001 - assign \rc_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10000 - assign \rc_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11101 - assign \rc_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11100 - assign \rc_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11110 - assign \rc_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11011 - assign \rc_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00011 - assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01111 - assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01011 - assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00101 - assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00100 - assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11000 - assign \rc_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11001 - assign \rc_sel 2'10 - end - sync init - end - process $group_13 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00001 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10001 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10000 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11101 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11100 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11110 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11011 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00011 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01111 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01011 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00101 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00100 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11000 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11001 - assign \cry_in 2'00 - end - sync init - end - process $group_14 - assign \asmcode 8'00000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00001 - assign \asmcode 8'00100001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \asmcode 8'00100010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10001 - assign \asmcode 8'00100011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10000 - assign \asmcode 8'00100100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11101 - assign \asmcode 8'01000100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11100 - assign \asmcode 8'01000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11110 - assign \asmcode 8'01000110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11011 - assign \asmcode 8'01000111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00011 - assign \asmcode 8'10001100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01111 - assign \asmcode 8'10001101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01011 - assign \asmcode 8'10001110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00101 - assign \asmcode 8'10001111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00100 - assign \asmcode 8'10010000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11000 - assign \asmcode 8'10011111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11001 - assign \asmcode 8'10100000 - end - sync init - end - process $group_15 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00001 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10001 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10000 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11101 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11100 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11110 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11011 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00011 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01111 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01011 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00101 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00100 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11000 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11001 - assign \inv_a 1'0 - end - sync init - end - process $group_16 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00001 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10001 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10000 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11101 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11100 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11110 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11011 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00011 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01111 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01011 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00101 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00100 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11000 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11001 - assign \inv_out 1'0 - end - sync init - end - process $group_17 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00001 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10001 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10000 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11101 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11100 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11110 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11011 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00011 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01111 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01011 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00101 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00100 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11000 - assign \cry_out 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11001 - assign \cry_out 1'1 - end - sync init - end - process $group_18 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00001 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10001 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10000 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11101 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11100 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11110 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11011 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00011 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01111 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01011 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00101 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00100 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11000 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11001 - assign \br 1'0 - end - sync init - end - process $group_19 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00001 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10001 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10000 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11101 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11100 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11110 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11011 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00011 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01111 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01011 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00101 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00100 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11000 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11001 - assign \sgn_ext 1'0 - end - sync init - end - process $group_20 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00001 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10001 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10000 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11101 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11100 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11110 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11011 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00011 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01111 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01011 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00101 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00100 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11000 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11001 - assign \rsrv 1'0 - end - sync init - end - process $group_21 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00001 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \is_32b 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10001 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10000 - assign \is_32b 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11101 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11100 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11110 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11011 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00011 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01111 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01011 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00101 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00100 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11000 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11001 - assign \is_32b 1'0 - end - sync init - end - process $group_22 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00001 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10001 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10000 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11101 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11100 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11110 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11011 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00011 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01111 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01011 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00101 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00100 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11000 - assign \sgn 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11001 - assign \sgn 1'1 - end - sync init - end - process $group_23 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00001 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10001 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10000 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11101 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11100 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11110 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11011 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00011 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01111 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01011 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00101 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00100 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11000 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11001 - assign \lk 1'0 - end - sync init - end - process $group_24 - assign \sgl_pipe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00001 - assign \sgl_pipe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \sgl_pipe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10001 - assign \sgl_pipe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10000 - assign \sgl_pipe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11101 - assign \sgl_pipe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11100 - assign \sgl_pipe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11110 - assign \sgl_pipe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11011 - assign \sgl_pipe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00011 - assign \sgl_pipe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01111 - assign \sgl_pipe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01011 - assign \sgl_pipe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00101 - assign \sgl_pipe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00100 - assign \sgl_pipe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11000 - assign \sgl_pipe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11001 - assign \sgl_pipe 1'0 - end - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.dec2.dec.dec31.dec_sub19" -module \dec_sub19 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" - wire width 32 input 0 \opcode_in - attribute \enum_base_type "Function" - attribute \enum_value_00000000000 "NONE" - attribute \enum_value_00000000010 "ALU" - attribute \enum_value_00000000100 "LDST" - attribute \enum_value_00000001000 "SHIFT_ROT" - attribute \enum_value_00000010000 "LOGICAL" - attribute \enum_value_00000100000 "BRANCH" - attribute \enum_value_00001000000 "CR" - attribute \enum_value_00010000000 "TRAP" - attribute \enum_value_00100000000 "MUL" - attribute \enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 11 output 1 \function_unit - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 7 output 2 \internal_op - attribute \enum_base_type "Form" - attribute \enum_value_00000 "NONE" - attribute \enum_value_00001 "I" - attribute \enum_value_00010 "B" - attribute \enum_value_00011 "SC" - attribute \enum_value_00100 "D" - attribute \enum_value_00101 "DS" - attribute \enum_value_00110 "DQ" - attribute \enum_value_00111 "DX" - attribute \enum_value_01000 "X" - attribute \enum_value_01001 "XL" - attribute \enum_value_01010 "XFX" - attribute \enum_value_01011 "XFL" - attribute \enum_value_01100 "XX1" - attribute \enum_value_01101 "XX2" - attribute \enum_value_01110 "XX3" - attribute \enum_value_01111 "XX4" - attribute \enum_value_10000 "XS" - attribute \enum_value_10001 "XO" - attribute \enum_value_10010 "A" - attribute \enum_value_10011 "M" - attribute \enum_value_10100 "MD" - attribute \enum_value_10101 "MDS" - attribute \enum_value_10110 "VA" - attribute \enum_value_10111 "VC" - attribute \enum_value_11000 "VX" - attribute \enum_value_11001 "EVX" - attribute \enum_value_11010 "EVS" - attribute \enum_value_11011 "Z22" - attribute \enum_value_11100 "Z23" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 5 output 3 \form - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 8 output 4 \asmcode - attribute \enum_base_type "In1Sel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "RA" - attribute \enum_value_010 "RA_OR_ZERO" - attribute \enum_value_011 "SPR" - attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 output 5 \in1_sel - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 4 output 6 \in2_sel - attribute \enum_base_type "In3Sel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RS" - attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 2 output 7 \in3_sel - attribute \enum_base_type "OutSel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RT" - attribute \enum_value_10 "RA" - attribute \enum_value_11 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 2 output 8 \out_sel - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 output 9 \cr_in - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 output 10 \cr_out - attribute \enum_base_type "LdstLen" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "is1B" - attribute \enum_value_0010 "is2B" - attribute \enum_value_0100 "is4B" - attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 4 output 11 \ldst_len - attribute \enum_base_type "LDSTMode" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "update" - attribute \enum_value_10 "cix" - attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 2 output 12 \upd - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 2 output 13 \rc_sel - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 2 output 14 \cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 output 15 \inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 output 16 \inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 output 17 \cry_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 output 18 \br - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 output 19 \sgn_ext - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 output 20 \rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 output 21 \is_32b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 output 22 \sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 output 23 \lk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 output 24 \sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:308" - wire width 5 \opcode_switch - process $group_0 - assign \opcode_switch 5'00000 - assign \opcode_switch \opcode_in [10:6] - sync init - end - process $group_1 - assign \function_unit 11'00000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \function_unit 11'00001000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00010 - assign \function_unit 11'00010000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01010 - assign \function_unit 11'10000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01110 - assign \function_unit 11'10000000000 - end - sync init - end - process $group_2 - assign \internal_op 7'0000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \internal_op 7'0101101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00010 - assign \internal_op 7'1000111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01010 - assign \internal_op 7'0101110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01110 - assign \internal_op 7'0110001 - end - sync init - end - process $group_3 - assign \form 5'00000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \form 5'01010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00010 - assign \form 5'01000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01010 - assign \form 5'01010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01110 - assign \form 5'01010 - end - sync init - end - process $group_4 - assign \in1_sel 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \in1_sel 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00010 - assign \in1_sel 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01010 - assign \in1_sel 3'011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01110 - assign \in1_sel 3'100 - end - sync init - end - process $group_5 - assign \in2_sel 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \in2_sel 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00010 - assign \in2_sel 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01010 - assign \in2_sel 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01110 - assign \in2_sel 4'0000 - end - sync init - end - process $group_6 - assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00010 - assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01010 - assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01110 - assign \in3_sel 2'00 - end - sync init - end - process $group_7 - assign \out_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \out_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00010 - assign \out_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01010 - assign \out_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01110 - assign \out_sel 2'11 - end - sync init - end - process $group_8 - assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \cr_in 3'110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00010 - assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01010 - assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01110 - assign \cr_in 3'000 - end - sync init - end - process $group_9 - assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00010 - assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01010 - assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01110 - assign \cr_out 3'000 - end - sync init - end - process $group_10 - assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00010 - assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01010 - assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01110 - assign \ldst_len 4'0000 - end - sync init - end - process $group_11 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00010 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01010 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01110 - assign \upd 2'00 - end - sync init - end - process $group_12 - assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00010 - assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01010 - assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01110 - assign \rc_sel 2'00 - end - sync init - end - process $group_13 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00010 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01010 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01110 - assign \cry_in 2'00 - end - sync init - end - process $group_14 - assign \asmcode 8'00000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \asmcode 8'01101111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00010 - assign \asmcode 8'01110000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01010 - assign \asmcode 8'01110001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01110 - assign \asmcode 8'01111001 - end - sync init - end - process $group_15 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00010 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01010 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01110 - assign \inv_a 1'0 - end - sync init - end - process $group_16 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00010 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01010 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01110 - assign \inv_out 1'0 - end - sync init - end - process $group_17 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00010 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01010 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01110 - assign \cry_out 1'0 - end - sync init - end - process $group_18 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00010 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01010 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01110 - assign \br 1'0 - end - sync init - end - process $group_19 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00010 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01010 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01110 - assign \sgn_ext 1'0 - end - sync init - end - process $group_20 - assign \rsrv 1'0 - attribute \src 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output 5 \in1_sel - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 4 output 6 \in2_sel - attribute \enum_base_type "In3Sel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RS" - attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 2 output 7 \in3_sel - attribute \enum_base_type "OutSel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RT" - attribute \enum_value_10 "RA" - attribute \enum_value_11 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 2 output 8 \out_sel - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 output 9 \cr_in - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 output 10 \cr_out - attribute \enum_base_type "LdstLen" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "is1B" - attribute \enum_value_0010 "is2B" - attribute \enum_value_0100 "is4B" - attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 4 output 11 \ldst_len - attribute \enum_base_type "LDSTMode" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "update" - attribute \enum_value_10 "cix" - attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 2 output 12 \upd - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 2 output 13 \rc_sel - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 2 output 14 \cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 output 15 \inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 output 16 \inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 output 17 \cry_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 output 18 \br - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 output 19 \sgn_ext - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 output 20 \rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 output 21 \is_32b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 output 22 \sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 output 23 \lk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 output 24 \sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:308" - wire width 5 \opcode_switch - process $group_0 - assign \opcode_switch 5'00000 - assign \opcode_switch \opcode_in [10:6] - sync init - end - process $group_1 - assign \function_unit 11'00000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00010 - assign \function_unit 11'00000000010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00001 - assign \function_unit 11'00000000010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01000 - assign \function_unit 11'00000000010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00111 - assign \function_unit 11'00000000010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11110 - assign \function_unit 11'00000000010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \function_unit 11'00000000010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11000 - assign \function_unit 11'00000000100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10000 - assign \function_unit 11'00000000100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10101 - assign \function_unit 11'00000000100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00110 - assign \function_unit 11'00000000100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11100 - assign \function_unit 11'00000000100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10110 - assign \function_unit 11'00000000100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10100 - assign \function_unit 11'00000000100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00100 - assign \function_unit 11'00000000100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10010 - assign \function_unit 11'00000000010 - end - sync init - end - process $group_2 - assign \internal_op 7'0000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00010 - assign \internal_op 7'0000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00001 - assign \internal_op 7'0000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01000 - assign \internal_op 7'0000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00111 - assign \internal_op 7'0000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11110 - assign \internal_op 7'0100001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \internal_op 7'0000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11000 - assign \internal_op 7'0100101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10000 - assign \internal_op 7'0100101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10101 - assign \internal_op 7'0100110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00110 - assign \internal_op 7'0100110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11100 - assign \internal_op 7'0100110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10110 - assign \internal_op 7'0100110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10100 - assign \internal_op 7'0100110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00100 - assign \internal_op 7'0100110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10010 - assign \internal_op 7'0000001 - end - sync init - end - process $group_3 - assign \form 5'00000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00010 - assign \form 5'01000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00001 - assign \form 5'01000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01000 - assign \form 5'01000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00111 - assign \form 5'01000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11110 - assign \form 5'01000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \form 5'01000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11000 - assign \form 5'01000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10000 - assign \form 5'01000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10101 - assign \form 5'01000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00110 - assign \form 5'01000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11100 - assign \form 5'01000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10110 - assign \form 5'01000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10100 - assign \form 5'01000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00100 - assign \form 5'01000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10010 - assign \form 5'01000 - end - sync init - end - process $group_4 - assign \in1_sel 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00010 - assign \in1_sel 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00001 - assign \in1_sel 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01000 - assign \in1_sel 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00111 - assign \in1_sel 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11110 - assign \in1_sel 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \in1_sel 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11000 - assign \in1_sel 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10000 - assign \in1_sel 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10101 - assign \in1_sel 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00110 - assign \in1_sel 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11100 - assign \in1_sel 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10110 - assign \in1_sel 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10100 - assign \in1_sel 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00100 - assign \in1_sel 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10010 - assign \in1_sel 3'000 - end - sync init - end - process $group_5 - assign \in2_sel 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00010 - assign \in2_sel 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00001 - assign \in2_sel 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01000 - assign \in2_sel 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00111 - assign \in2_sel 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11110 - assign \in2_sel 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \in2_sel 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11000 - assign \in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10000 - assign \in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10101 - assign \in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00110 - assign \in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11100 - assign \in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10110 - assign \in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10100 - assign \in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00100 - assign \in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10010 - assign \in2_sel 4'0000 - end - sync init - end - process $group_6 - assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00010 - assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00001 - assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01000 - assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00111 - assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11110 - assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11000 - assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10000 - assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10101 - assign \in3_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00110 - assign \in3_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11100 - assign \in3_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10110 - assign \in3_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10100 - assign \in3_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00100 - assign \in3_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10010 - assign \in3_sel 2'00 - end - sync init - end - process $group_7 - assign \out_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00010 - assign \out_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00001 - assign \out_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01000 - assign \out_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00111 - assign \out_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11110 - assign \out_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \out_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11000 - assign \out_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10000 - assign \out_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10101 - assign \out_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00110 - assign \out_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11100 - assign \out_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10110 - assign \out_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10100 - assign \out_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00100 - assign \out_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10010 - assign \out_sel 2'00 - end - sync init - end - process $group_8 - assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00010 - assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00001 - assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01000 - assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00111 - assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11110 - assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11000 - assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10000 - assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10101 - assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00110 - assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11100 - assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10110 - assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10100 - assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00100 - assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10010 - assign \cr_in 3'000 - end - sync init - end - process $group_9 - assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00010 - assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00001 - assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01000 - assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00111 - assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11110 - assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11000 - assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10000 - assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10101 - assign \cr_out 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00110 - assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11100 - assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10110 - assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10100 - assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00100 - assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10010 - assign \cr_out 3'000 - end - sync init - end - process $group_10 - assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00010 - assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00001 - assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01000 - assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00111 - assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11110 - assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11000 - assign \ldst_len 4'0010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10000 - assign \ldst_len 4'0100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10101 - assign \ldst_len 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00110 - assign \ldst_len 4'1000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11100 - assign \ldst_len 4'0010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10110 - assign \ldst_len 4'0010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10100 - assign \ldst_len 4'0100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00100 - assign \ldst_len 4'0100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10010 - assign \ldst_len 4'0000 - end - sync init - end - process $group_11 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00010 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00001 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01000 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00111 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11110 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11000 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10000 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10101 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00110 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11100 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10110 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10100 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00100 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10010 - assign \upd 2'00 - end - sync init - end - process $group_12 - assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00010 - assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00001 - assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01000 - assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00111 - assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11110 - assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11000 - assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10000 - assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10101 - assign \rc_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00110 - assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11100 - assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10110 - assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10100 - assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00100 - assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10010 - assign \rc_sel 2'00 - end - sync init - end - process $group_13 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00010 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00001 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01000 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00111 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11110 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11000 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10000 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10101 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00110 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11100 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10110 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10100 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00100 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10010 - assign \cry_in 2'00 - end - sync init - end - process $group_14 - assign \asmcode 8'00000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00010 - assign \asmcode 8'00101110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00001 - assign \asmcode 8'00101111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01000 - assign \asmcode 8'00110000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00111 - assign \asmcode 8'00110001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11110 - assign \asmcode 8'01001001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \asmcode 8'01001010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11000 - assign \asmcode 8'01011101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10000 - assign \asmcode 8'01100110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10101 - assign \asmcode 8'10100111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00110 - assign \asmcode 8'10101101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11100 - assign \asmcode 8'10110010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10110 - assign \asmcode 8'10110011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10100 - assign \asmcode 8'10111000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00100 - assign \asmcode 8'10111001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10010 - assign \asmcode 8'11001000 - end - sync init - end - process $group_15 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00010 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00001 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01000 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00111 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11110 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11000 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10000 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10101 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00110 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11100 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10110 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10100 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00100 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10010 - assign \inv_a 1'0 - end - sync init - end - process $group_16 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00010 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00001 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01000 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00111 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11110 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11000 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10000 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10101 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00110 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11100 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10110 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10100 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00100 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10010 - assign \inv_out 1'0 - end - sync init - end - process $group_17 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00010 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00001 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01000 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00111 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11110 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11000 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10000 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10101 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00110 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11100 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10110 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10100 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00100 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10010 - assign \cry_out 1'0 - end - sync init - end - process $group_18 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00010 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00001 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01000 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00111 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11110 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11000 - assign \br 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10000 - assign \br 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10101 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00110 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11100 - assign \br 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10110 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10100 - assign \br 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00100 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10010 - assign \br 1'0 - end - sync init - end - process $group_19 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00010 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00001 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01000 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00111 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11110 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11000 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10000 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10101 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00110 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11100 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10110 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10100 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00100 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10010 - assign \sgn_ext 1'0 - end - sync init - end - process $group_20 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00010 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00001 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01000 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00111 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11110 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11000 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10000 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10101 - assign \rsrv 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00110 - assign \rsrv 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11100 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10110 - assign \rsrv 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10100 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00100 - assign \rsrv 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10010 - assign \rsrv 1'0 - end - sync init - end - process $group_21 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00010 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00001 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01000 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00111 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11110 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11000 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10000 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10101 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00110 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11100 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10110 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10100 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00100 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10010 - assign \is_32b 1'0 - end - sync init - end - process $group_22 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00010 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00001 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01000 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00111 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11110 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11000 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10000 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10101 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00110 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11100 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10110 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10100 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00100 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10010 - assign \sgn 1'0 - end - sync init - end - process $group_23 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00010 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00001 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01000 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00111 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11110 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11000 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10000 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10101 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00110 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11100 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10110 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10100 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00100 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10010 - assign \lk 1'0 - end - sync init - end - process $group_24 - assign \sgl_pipe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00010 - assign \sgl_pipe 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00001 - assign \sgl_pipe 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01000 - assign \sgl_pipe 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00111 - assign \sgl_pipe 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11110 - assign \sgl_pipe 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \sgl_pipe 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11000 - assign \sgl_pipe 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10000 - assign \sgl_pipe 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10101 - assign \sgl_pipe 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00110 - assign \sgl_pipe 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11100 - assign \sgl_pipe 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10110 - assign \sgl_pipe 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10100 - assign \sgl_pipe 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00100 - assign \sgl_pipe 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10010 - assign \sgl_pipe 1'1 - end - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.dec2.dec.dec31.dec_sub9" -module \dec_sub9 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" - wire width 32 input 0 \opcode_in - attribute \enum_base_type "Function" - attribute \enum_value_00000000000 "NONE" - attribute \enum_value_00000000010 "ALU" - attribute \enum_value_00000000100 "LDST" - attribute \enum_value_00000001000 "SHIFT_ROT" - attribute \enum_value_00000010000 "LOGICAL" - attribute \enum_value_00000100000 "BRANCH" - attribute \enum_value_00001000000 "CR" - attribute \enum_value_00010000000 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\enum_value_01101 "XX2" - attribute \enum_value_01110 "XX3" - attribute \enum_value_01111 "XX4" - attribute \enum_value_10000 "XS" - attribute \enum_value_10001 "XO" - attribute \enum_value_10010 "A" - attribute \enum_value_10011 "M" - attribute \enum_value_10100 "MD" - attribute \enum_value_10101 "MDS" - attribute \enum_value_10110 "VA" - attribute \enum_value_10111 "VC" - attribute \enum_value_11000 "VX" - attribute \enum_value_11001 "EVX" - attribute \enum_value_11010 "EVS" - attribute \enum_value_11011 "Z22" - attribute \enum_value_11100 "Z23" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 5 output 3 \form - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 8 output 4 \asmcode - attribute \enum_base_type "In1Sel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "RA" - attribute \enum_value_010 "RA_OR_ZERO" - attribute \enum_value_011 "SPR" - attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 output 5 \in1_sel - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 4 output 6 \in2_sel - attribute \enum_base_type "In3Sel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RS" - attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 2 output 7 \in3_sel - attribute \enum_base_type "OutSel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RT" - attribute \enum_value_10 "RA" - attribute \enum_value_11 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 2 output 8 \out_sel - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 output 9 \cr_in - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 output 10 \cr_out - attribute \enum_base_type "LdstLen" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "is1B" - attribute \enum_value_0010 "is2B" - attribute \enum_value_0100 "is4B" - attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 4 output 11 \ldst_len - attribute \enum_base_type "LDSTMode" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "update" - attribute \enum_value_10 "cix" - attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 2 output 12 \upd - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 2 output 13 \rc_sel - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 2 output 14 \cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 output 15 \inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 output 16 \inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 output 17 \cry_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 output 18 \br - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 output 19 \sgn_ext - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 output 20 \rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 output 21 \is_32b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 output 22 \sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 output 23 \lk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 output 24 \sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:308" - wire width 5 \opcode_switch - process $group_0 - assign \opcode_switch 5'00000 - assign \opcode_switch \opcode_in [10:6] - sync init - end - process $group_1 - assign \function_unit 11'00000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01100 - assign \function_unit 11'01000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11100 - assign \function_unit 11'01000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01101 - assign \function_unit 11'01000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11101 - assign \function_unit 11'01000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01110 - assign \function_unit 11'01000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11110 - assign \function_unit 11'01000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01111 - assign \function_unit 11'01000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11111 - assign \function_unit 11'01000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01000 - assign \function_unit 11'01000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11000 - assign \function_unit 11'01000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00010 - assign \function_unit 11'00100000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \function_unit 11'00100000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10010 - assign \function_unit 11'00100000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10000 - assign \function_unit 11'00100000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00111 - assign \function_unit 11'00100000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10111 - assign \function_unit 11'00100000000 - end - sync init - end - process $group_2 - assign \internal_op 7'0000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01100 - assign \internal_op 7'0011110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11100 - assign \internal_op 7'0011110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01101 - assign \internal_op 7'0011110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11101 - assign \internal_op 7'0011110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01110 - assign \internal_op 7'0011101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11110 - assign \internal_op 7'0011101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01111 - assign \internal_op 7'0011101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11111 - assign \internal_op 7'0011101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01000 - assign \internal_op 7'0101111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11000 - assign \internal_op 7'0101111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00010 - assign \internal_op 7'0110011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \internal_op 7'0110011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10010 - assign \internal_op 7'0110011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10000 - assign \internal_op 7'0110011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00111 - assign \internal_op 7'0110010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10111 - assign \internal_op 7'0110010 - end - sync init - end - process $group_3 - assign \form 5'00000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01100 - assign \form 5'10001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11100 - assign \form 5'10001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01101 - assign \form 5'10001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11101 - assign \form 5'10001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01110 - assign \form 5'10001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11110 - assign \form 5'10001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01111 - assign \form 5'10001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11111 - assign \form 5'10001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01000 - assign \form 5'01000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11000 - assign \form 5'01000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00010 - assign \form 5'10001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \form 5'10001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10010 - assign \form 5'10001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10000 - assign \form 5'10001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00111 - assign \form 5'10001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10111 - assign \form 5'10001 - end - sync init - end - process $group_4 - assign \in1_sel 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01100 - assign \in1_sel 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11100 - assign \in1_sel 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01101 - assign \in1_sel 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11101 - assign \in1_sel 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01110 - assign \in1_sel 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11110 - assign \in1_sel 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01111 - assign \in1_sel 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11111 - assign \in1_sel 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01000 - assign \in1_sel 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11000 - assign \in1_sel 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00010 - assign \in1_sel 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \in1_sel 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10010 - assign \in1_sel 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10000 - assign \in1_sel 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00111 - assign \in1_sel 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10111 - assign \in1_sel 3'001 - end - sync init - end - process $group_5 - assign \in2_sel 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01100 - assign \in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11100 - assign \in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01101 - assign \in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11101 - assign \in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01110 - assign \in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11110 - assign \in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01111 - assign \in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11111 - assign \in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01000 - assign \in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11000 - assign \in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00010 - assign \in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10010 - assign \in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10000 - assign \in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00111 - assign \in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10111 - assign \in2_sel 4'0001 - end - sync init - end - process $group_6 - assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01100 - assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11100 - assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01101 - assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11101 - assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01110 - assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11110 - assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01111 - assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11111 - assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01000 - assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11000 - assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00010 - assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10010 - assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10000 - assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00111 - assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10111 - assign \in3_sel 2'00 - end - sync init - end - process $group_7 - assign \out_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01100 - assign \out_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11100 - assign \out_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01101 - assign \out_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11101 - assign \out_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01110 - assign \out_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11110 - assign \out_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01111 - assign \out_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11111 - assign \out_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01000 - assign \out_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11000 - assign \out_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00010 - assign \out_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \out_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10010 - assign \out_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10000 - assign \out_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00111 - assign \out_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10111 - assign \out_sel 2'01 - end - sync init - end - process $group_8 - assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01100 - assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11100 - assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01101 - assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11101 - assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01110 - assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11110 - assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01111 - assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11111 - assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01000 - assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11000 - assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00010 - assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10010 - assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10000 - assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00111 - assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10111 - assign \cr_in 3'000 - end - sync init - end - process $group_9 - assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01100 - assign \cr_out 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11100 - assign \cr_out 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01101 - assign \cr_out 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11101 - assign \cr_out 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01110 - assign \cr_out 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11110 - assign \cr_out 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01111 - assign \cr_out 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11111 - assign \cr_out 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01000 - assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11000 - assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00010 - assign \cr_out 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \cr_out 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10010 - assign \cr_out 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10000 - assign \cr_out 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00111 - assign \cr_out 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10111 - assign \cr_out 3'001 - end - sync init - end - process $group_10 - assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01100 - assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11100 - assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01101 - assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11101 - assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01110 - assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11110 - assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01111 - assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11111 - assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01000 - assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11000 - assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00010 - assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10010 - assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10000 - assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00111 - assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10111 - assign \ldst_len 4'0000 - end - sync init - end - process $group_11 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01100 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11100 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01101 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11101 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01110 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11110 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01111 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11111 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01000 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11000 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00010 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10010 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10000 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00111 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10111 - assign \upd 2'00 - end - sync init - end - process $group_12 - assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01100 - assign \rc_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11100 - assign \rc_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01101 - assign \rc_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11101 - assign \rc_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01110 - assign \rc_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11110 - assign \rc_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01111 - assign \rc_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11111 - assign \rc_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01000 - assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11000 - assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00010 - assign \rc_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \rc_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10010 - assign \rc_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10000 - assign \rc_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00111 - assign \rc_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10111 - assign \rc_sel 2'10 - end - sync init - end - process $group_13 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01100 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11100 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01101 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11101 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01110 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11110 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01111 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11111 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01000 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11000 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00010 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10010 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10000 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00111 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10111 - assign \cry_in 2'00 - end - sync init - end - process $group_14 - assign \asmcode 8'00000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01100 - assign \asmcode 8'00110110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11100 - assign \asmcode 8'00110111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01101 - assign \asmcode 8'00110100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11101 - assign \asmcode 8'00110101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01110 - assign \asmcode 8'00111001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11110 - assign \asmcode 8'00111010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01111 - assign \asmcode 8'00110011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11111 - assign \asmcode 8'00111000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01000 - assign \asmcode 8'01110100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11000 - assign \asmcode 8'01110010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00010 - assign \asmcode 8'01111010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \asmcode 8'01111011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10010 - assign \asmcode 8'01111010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10000 - assign \asmcode 8'01111011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00111 - assign \asmcode 8'01111110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10111 - assign \asmcode 8'01111111 - end - sync init - end - process $group_15 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01100 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11100 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01101 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11101 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01110 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11110 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01111 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11111 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01000 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11000 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00010 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10010 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10000 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00111 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10111 - assign \inv_a 1'0 - end - sync init - end - process $group_16 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01100 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11100 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01101 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11101 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01110 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11110 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01111 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11111 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01000 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11000 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00010 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10010 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10000 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00111 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10111 - assign \inv_out 1'0 - end - sync init - end - process $group_17 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01100 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11100 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01101 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11101 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01110 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11110 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01111 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11111 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01000 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11000 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00010 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10010 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10000 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00111 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10111 - assign \cry_out 1'0 - end - sync init - end - process $group_18 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01100 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11100 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01101 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11101 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01110 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11110 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01111 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11111 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01000 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11000 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00010 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10010 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10000 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00111 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10111 - assign \br 1'0 - end - sync init - end - process $group_19 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01100 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11100 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01101 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11101 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01110 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11110 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01111 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11111 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01000 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11000 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00010 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10010 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10000 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00111 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10111 - assign \sgn_ext 1'0 - end - sync init - end - process $group_20 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01100 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11100 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01101 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11101 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01110 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11110 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01111 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11111 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01000 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11000 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00010 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10010 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10000 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00111 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10111 - assign \rsrv 1'0 - end - sync init - end - process $group_21 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01100 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11100 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01101 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11101 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01110 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11110 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01111 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11111 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01000 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11000 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00010 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10010 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10000 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00111 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10111 - assign \is_32b 1'0 - end - sync init - end - process $group_22 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01100 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11100 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01101 - assign \sgn 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11101 - assign \sgn 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01110 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11110 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01111 - assign \sgn 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11111 - assign \sgn 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01000 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11000 - assign \sgn 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00010 - assign \sgn 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10010 - assign \sgn 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10000 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00111 - assign \sgn 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10111 - assign \sgn 1'1 - end - sync init - end - process $group_23 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01100 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11100 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01101 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11101 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01110 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11110 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01111 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11111 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01000 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11000 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00010 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10010 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10000 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00111 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10111 - assign \lk 1'0 - end - sync init - end - process $group_24 - assign \sgl_pipe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01100 - assign \sgl_pipe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11100 - assign \sgl_pipe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01101 - assign \sgl_pipe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11101 - assign \sgl_pipe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01110 - assign \sgl_pipe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11110 - assign \sgl_pipe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01111 - assign \sgl_pipe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11111 - assign \sgl_pipe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01000 - assign \sgl_pipe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11000 - assign \sgl_pipe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00010 - assign \sgl_pipe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \sgl_pipe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10010 - assign \sgl_pipe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10000 - assign \sgl_pipe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00111 - assign \sgl_pipe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10111 - assign \sgl_pipe 1'0 - end - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.dec2.dec.dec31.dec_sub11" -module \dec_sub11 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" - wire width 32 input 0 \opcode_in - attribute \enum_base_type "Function" - attribute \enum_value_00000000000 "NONE" - attribute \enum_value_00000000010 "ALU" - attribute \enum_value_00000000100 "LDST" - attribute \enum_value_00000001000 "SHIFT_ROT" - attribute \enum_value_00000010000 "LOGICAL" - attribute \enum_value_00000100000 "BRANCH" - attribute \enum_value_00001000000 "CR" - attribute \enum_value_00010000000 "TRAP" - attribute \enum_value_00100000000 "MUL" - attribute \enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 11 output 1 \function_unit - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 7 output 2 \internal_op - attribute \enum_base_type "Form" - attribute \enum_value_00000 "NONE" - attribute \enum_value_00001 "I" - attribute \enum_value_00010 "B" - attribute \enum_value_00011 "SC" - attribute \enum_value_00100 "D" - attribute \enum_value_00101 "DS" - attribute \enum_value_00110 "DQ" - attribute \enum_value_00111 "DX" - attribute \enum_value_01000 "X" - attribute \enum_value_01001 "XL" - attribute \enum_value_01010 "XFX" - attribute \enum_value_01011 "XFL" - attribute \enum_value_01100 "XX1" - attribute \enum_value_01101 "XX2" - attribute \enum_value_01110 "XX3" - attribute \enum_value_01111 "XX4" - attribute \enum_value_10000 "XS" - attribute \enum_value_10001 "XO" - attribute \enum_value_10010 "A" - attribute \enum_value_10011 "M" - attribute \enum_value_10100 "MD" - attribute \enum_value_10101 "MDS" - attribute \enum_value_10110 "VA" - attribute \enum_value_10111 "VC" - attribute \enum_value_11000 "VX" - attribute \enum_value_11001 "EVX" - attribute \enum_value_11010 "EVS" - attribute \enum_value_11011 "Z22" - attribute \enum_value_11100 "Z23" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 5 output 3 \form - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 8 output 4 \asmcode - attribute \enum_base_type "In1Sel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "RA" - attribute \enum_value_010 "RA_OR_ZERO" - attribute \enum_value_011 "SPR" - attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 output 5 \in1_sel - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 4 output 6 \in2_sel - attribute \enum_base_type "In3Sel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RS" - attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 2 output 7 \in3_sel - attribute \enum_base_type "OutSel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RT" - attribute \enum_value_10 "RA" - attribute \enum_value_11 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 2 output 8 \out_sel - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 output 9 \cr_in - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 output 10 \cr_out - attribute \enum_base_type "LdstLen" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "is1B" - attribute \enum_value_0010 "is2B" - attribute \enum_value_0100 "is4B" - attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 4 output 11 \ldst_len - attribute \enum_base_type "LDSTMode" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "update" - attribute \enum_value_10 "cix" - attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 2 output 12 \upd - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 2 output 13 \rc_sel - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 2 output 14 \cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 output 15 \inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 output 16 \inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 output 17 \cry_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 output 18 \br - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 output 19 \sgn_ext - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 output 20 \rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 output 21 \is_32b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 output 22 \sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 output 23 \lk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 output 24 \sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:308" - wire width 5 \opcode_switch - process $group_0 - assign \opcode_switch 5'00000 - assign \opcode_switch \opcode_in [10:6] - sync init - end - process $group_1 - assign \function_unit 11'00000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01100 - assign \function_unit 11'01000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11100 - assign \function_unit 11'01000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01101 - assign \function_unit 11'01000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11101 - assign \function_unit 11'01000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01110 - assign \function_unit 11'01000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11110 - assign \function_unit 11'01000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01111 - assign \function_unit 11'01000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11111 - assign \function_unit 11'01000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01000 - assign \function_unit 11'01000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11000 - assign \function_unit 11'01000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00010 - assign \function_unit 11'00100000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \function_unit 11'00100000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10010 - assign \function_unit 11'00100000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10000 - assign \function_unit 11'00100000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00111 - assign \function_unit 11'00100000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10111 - assign \function_unit 11'00100000000 - end - sync init - end - process $group_2 - assign \internal_op 7'0000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01100 - assign \internal_op 7'0011110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11100 - assign \internal_op 7'0011110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01101 - assign \internal_op 7'0011110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11101 - assign \internal_op 7'0011110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01110 - assign \internal_op 7'0011101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11110 - assign \internal_op 7'0011101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01111 - assign \internal_op 7'0011101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11111 - assign \internal_op 7'0011101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01000 - assign \internal_op 7'0101111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11000 - assign \internal_op 7'0101111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00010 - assign \internal_op 7'0110100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \internal_op 7'0110100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10010 - assign \internal_op 7'0110100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10000 - assign \internal_op 7'0110100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00111 - assign \internal_op 7'0110010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10111 - assign \internal_op 7'0110010 - end - sync init - end - process $group_3 - assign \form 5'00000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01100 - assign \form 5'10001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11100 - assign \form 5'10001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01101 - assign \form 5'10001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11101 - assign \form 5'10001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01110 - assign \form 5'10001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11110 - assign \form 5'10001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01111 - assign \form 5'10001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11111 - assign \form 5'10001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01000 - assign \form 5'01000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11000 - assign \form 5'01000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00010 - assign \form 5'10001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \form 5'10001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10010 - assign \form 5'10001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10000 - assign \form 5'10001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00111 - assign \form 5'10001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10111 - assign \form 5'10001 - end - sync init - end - process $group_4 - assign \in1_sel 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01100 - assign \in1_sel 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11100 - assign \in1_sel 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01101 - assign \in1_sel 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11101 - assign \in1_sel 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01110 - assign \in1_sel 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11110 - assign \in1_sel 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01111 - assign \in1_sel 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11111 - assign \in1_sel 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01000 - assign \in1_sel 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11000 - assign \in1_sel 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00010 - assign \in1_sel 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \in1_sel 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10010 - assign \in1_sel 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10000 - assign \in1_sel 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00111 - assign \in1_sel 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10111 - assign \in1_sel 3'001 - end - sync init - end - process $group_5 - assign \in2_sel 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01100 - assign \in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11100 - assign \in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01101 - assign \in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11101 - assign \in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01110 - assign \in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11110 - assign \in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01111 - assign \in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11111 - assign \in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01000 - assign \in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11000 - assign \in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00010 - assign \in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10010 - assign \in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10000 - assign \in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00111 - assign \in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10111 - assign \in2_sel 4'0001 - end - sync init - end - process $group_6 - assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01100 - assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11100 - assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01101 - assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11101 - assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01110 - assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11110 - assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01111 - assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11111 - assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01000 - assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11000 - assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00010 - assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10010 - assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10000 - assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00111 - assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10111 - assign \in3_sel 2'00 - end - sync init - end - process $group_7 - assign \out_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01100 - assign \out_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11100 - assign \out_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01101 - assign \out_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11101 - assign \out_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01110 - assign \out_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11110 - assign \out_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01111 - assign \out_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11111 - assign \out_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01000 - assign \out_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11000 - assign \out_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00010 - assign \out_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \out_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10010 - assign \out_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10000 - assign \out_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00111 - assign \out_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10111 - assign \out_sel 2'01 - end - sync init - end - process $group_8 - assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01100 - assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11100 - assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01101 - assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11101 - assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01110 - assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11110 - assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01111 - assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11111 - assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01000 - assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11000 - assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00010 - assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10010 - assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10000 - assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00111 - assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10111 - assign \cr_in 3'000 - end - sync init - end - process $group_9 - assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01100 - assign \cr_out 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11100 - assign \cr_out 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01101 - assign \cr_out 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11101 - assign \cr_out 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01110 - assign \cr_out 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11110 - assign \cr_out 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01111 - assign \cr_out 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11111 - assign \cr_out 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01000 - assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11000 - assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00010 - assign \cr_out 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \cr_out 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10010 - assign \cr_out 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10000 - assign \cr_out 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00111 - assign \cr_out 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10111 - assign \cr_out 3'001 - end - sync init - end - process $group_10 - assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01100 - assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11100 - assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01101 - assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11101 - assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01110 - assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11110 - assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01111 - assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11111 - assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01000 - assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11000 - assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00010 - assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10010 - assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10000 - assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00111 - assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10111 - assign \ldst_len 4'0000 - end - sync init - end - process $group_11 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01100 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11100 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01101 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11101 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01110 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11110 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01111 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11111 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01000 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11000 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00010 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10010 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10000 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00111 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10111 - assign \upd 2'00 - end - sync init - end - process $group_12 - assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01100 - assign \rc_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11100 - assign \rc_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01101 - assign \rc_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11101 - assign \rc_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01110 - assign \rc_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11110 - assign \rc_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01111 - assign \rc_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11111 - assign \rc_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01000 - assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11000 - assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00010 - assign \rc_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \rc_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10010 - assign \rc_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10000 - assign \rc_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00111 - assign \rc_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10111 - assign \rc_sel 2'10 - end - sync init - end - process $group_13 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01100 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11100 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01101 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11101 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01110 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11110 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01111 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11111 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01000 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11000 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00010 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10010 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10000 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00111 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10111 - assign \cry_in 2'00 - end - sync init - end - process $group_14 - assign \asmcode 8'00000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01100 - assign \asmcode 8'00111110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11100 - assign \asmcode 8'00111111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01101 - assign \asmcode 8'00111100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11101 - assign \asmcode 8'00111101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01110 - assign \asmcode 8'01000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11110 - assign \asmcode 8'01000010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01111 - assign \asmcode 8'00111011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11111 - assign \asmcode 8'01000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01000 - assign \asmcode 8'01110101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11000 - assign \asmcode 8'01110011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00010 - assign \asmcode 8'01111100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \asmcode 8'01111101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10010 - assign \asmcode 8'01111100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10000 - assign \asmcode 8'01111101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00111 - assign \asmcode 8'10000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10111 - assign \asmcode 8'10000010 - end - sync init - end - process $group_15 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01100 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11100 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01101 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11101 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01110 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11110 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01111 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11111 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01000 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11000 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00010 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10010 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10000 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00111 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10111 - assign \inv_a 1'0 - end - sync init - end - process $group_16 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01100 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11100 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01101 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11101 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01110 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11110 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01111 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11111 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01000 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11000 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00010 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10010 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10000 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00111 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10111 - assign \inv_out 1'0 - end - sync init - end - process $group_17 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01100 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11100 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01101 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11101 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01110 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11110 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01111 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11111 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01000 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11000 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00010 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10010 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10000 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00111 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10111 - assign \cry_out 1'0 - end - sync init - end - process $group_18 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01100 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11100 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01101 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11101 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01110 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11110 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01111 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11111 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01000 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11000 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00010 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10010 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10000 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00111 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10111 - assign \br 1'0 - end - sync init - end - process $group_19 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01100 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11100 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01101 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11101 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01110 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11110 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01111 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11111 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01000 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11000 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00010 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10010 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10000 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00111 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10111 - assign \sgn_ext 1'0 - end - sync init - end - process $group_20 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01100 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11100 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01101 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11101 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01110 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11110 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01111 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11111 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01000 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11000 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00010 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10010 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10000 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00111 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10111 - assign \rsrv 1'0 - end - sync init - end - process $group_21 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01100 - assign \is_32b 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11100 - assign \is_32b 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01101 - assign \is_32b 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11101 - assign \is_32b 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01110 - assign \is_32b 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11110 - assign \is_32b 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01111 - assign \is_32b 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11111 - assign \is_32b 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01000 - assign \is_32b 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11000 - assign \is_32b 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00010 - assign \is_32b 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \is_32b 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10010 - assign \is_32b 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10000 - assign \is_32b 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00111 - assign \is_32b 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10111 - assign \is_32b 1'1 - end - sync init - end - process $group_22 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01100 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11100 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01101 - assign \sgn 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11101 - assign \sgn 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01110 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11110 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01111 - assign \sgn 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11111 - assign \sgn 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01000 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11000 - assign \sgn 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00010 - assign \sgn 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10010 - assign \sgn 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10000 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00111 - assign \sgn 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10111 - assign \sgn 1'1 - end - sync init - end - process $group_23 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01100 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11100 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01101 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11101 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01110 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11110 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01111 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11111 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01000 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11000 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00010 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10010 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10000 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00111 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10111 - assign \lk 1'0 - end - sync init - end - process $group_24 - assign \sgl_pipe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01100 - assign \sgl_pipe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 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\cry_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 output 18 \br - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 output 19 \sgn_ext - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 output 20 \rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 output 21 \is_32b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 output 22 \sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 output 23 \lk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 output 24 \sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:308" - wire width 5 \opcode_switch - process $group_0 - assign \opcode_switch 5'00000 - assign \opcode_switch \opcode_in [10:6] - sync init - end - process $group_1 - assign \function_unit 11'00000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11011 - assign \function_unit 11'00000001000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \function_unit 11'00000001000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11001 - assign \function_unit 11'00000001000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10000 - assign \function_unit 11'00000001000 - end - sync init - end - process $group_2 - assign \internal_op 7'0000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11011 - assign \internal_op 7'0100000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \internal_op 7'0111100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11001 - assign \internal_op 7'0111101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10000 - assign \internal_op 7'0111101 - end - sync init - end - process $group_3 - assign \form 5'00000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11011 - assign \form 5'10000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \form 5'01000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11001 - assign \form 5'10000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10000 - assign \form 5'01000 - end - sync init - end - process $group_4 - assign \in1_sel 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11011 - assign \in1_sel 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \in1_sel 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11001 - assign \in1_sel 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10000 - assign \in1_sel 3'000 - end - sync init - end - process $group_5 - assign \in2_sel 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11011 - assign \in2_sel 4'1010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11001 - assign \in2_sel 4'1010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10000 - assign \in2_sel 4'0001 - end - sync init - end - process $group_6 - assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11011 - assign \in3_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \in3_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11001 - assign \in3_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10000 - assign \in3_sel 2'01 - end - sync init - end - process $group_7 - assign \out_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11011 - assign \out_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \out_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11001 - assign \out_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10000 - assign \out_sel 2'10 - end - sync init - end - process $group_8 - assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11011 - assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11001 - assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10000 - assign \cr_in 3'000 - end - sync init - end - process $group_9 - assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11011 - assign \cr_out 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \cr_out 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11001 - assign \cr_out 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10000 - assign \cr_out 3'001 - end - sync init - end - process $group_10 - assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11011 - assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11001 - assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10000 - assign \ldst_len 4'0000 - end - sync init - end - process $group_11 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11011 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11001 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10000 - assign \upd 2'00 - end - sync init - end - process $group_12 - assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11011 - assign \rc_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \rc_sel 2'10 - attribute \src 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"/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 output 22 \sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 output 23 \lk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 output 24 \sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:308" - wire width 5 \opcode_switch - process $group_0 - assign \opcode_switch 5'00000 - assign \opcode_switch \opcode_in [10:6] - sync init - end - process $group_1 - assign \function_unit 11'00000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \function_unit 11'00001000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00001 - assign \function_unit 11'00001000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00010 - assign \function_unit 11'00001000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00011 - assign \function_unit 11'00001000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00100 - assign \function_unit 11'00001000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00101 - assign \function_unit 11'00001000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00110 - assign \function_unit 11'00001000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00111 - assign \function_unit 11'00001000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01000 - assign \function_unit 11'00001000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01001 - assign \function_unit 11'00001000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01010 - assign \function_unit 11'00001000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01011 - assign \function_unit 11'00001000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01100 - assign \function_unit 11'00001000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01101 - assign \function_unit 11'00001000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01110 - assign \function_unit 11'00001000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01111 - assign \function_unit 11'00001000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10000 - assign \function_unit 11'00001000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10001 - assign \function_unit 11'00001000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10010 - assign \function_unit 11'00001000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10011 - assign \function_unit 11'00001000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10100 - assign \function_unit 11'00001000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10101 - assign \function_unit 11'00001000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10110 - assign \function_unit 11'00001000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10111 - assign \function_unit 11'00001000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11000 - assign \function_unit 11'00001000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11001 - assign \function_unit 11'00001000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11010 - assign \function_unit 11'00001000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11011 - assign \function_unit 11'00001000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11100 - assign \function_unit 11'00001000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11101 - assign \function_unit 11'00001000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11110 - assign \function_unit 11'00001000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11111 - assign \function_unit 11'00001000000 - end - sync init - end - process $group_2 - assign \internal_op 7'0000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \internal_op 7'0100011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00001 - assign \internal_op 7'0100011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00010 - assign \internal_op 7'0100011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00011 - assign \internal_op 7'0100011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00100 - assign \internal_op 7'0100011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00101 - assign \internal_op 7'0100011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00110 - assign \internal_op 7'0100011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00111 - assign \internal_op 7'0100011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01000 - assign \internal_op 7'0100011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01001 - assign \internal_op 7'0100011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01010 - assign \internal_op 7'0100011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01011 - assign \internal_op 7'0100011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01100 - assign \internal_op 7'0100011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01101 - assign \internal_op 7'0100011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01110 - assign \internal_op 7'0100011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01111 - assign \internal_op 7'0100011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10000 - assign \internal_op 7'0100011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10001 - assign \internal_op 7'0100011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10010 - assign \internal_op 7'0100011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10011 - assign \internal_op 7'0100011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10100 - assign \internal_op 7'0100011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10101 - assign \internal_op 7'0100011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10110 - assign \internal_op 7'0100011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10111 - assign \internal_op 7'0100011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11000 - assign \internal_op 7'0100011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11001 - assign \internal_op 7'0100011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11010 - assign \internal_op 7'0100011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11011 - assign \internal_op 7'0100011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11100 - assign \internal_op 7'0100011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11101 - assign \internal_op 7'0100011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11110 - assign \internal_op 7'0100011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11111 - assign \internal_op 7'0100011 - end - sync init - end - process $group_3 - assign \form 5'00000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \form 5'10010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00001 - assign \form 5'10010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00010 - assign \form 5'10010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00011 - assign \form 5'10010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00100 - assign \form 5'10010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00101 - assign \form 5'10010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00110 - assign \form 5'10010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00111 - assign \form 5'10010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01000 - assign \form 5'10010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01001 - assign \form 5'10010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01010 - assign \form 5'10010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01011 - assign \form 5'10010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01100 - assign \form 5'10010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01101 - assign \form 5'10010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01110 - assign \form 5'10010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01111 - assign \form 5'10010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10000 - assign \form 5'10010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10001 - assign \form 5'10010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10010 - assign \form 5'10010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10011 - assign \form 5'10010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10100 - assign \form 5'10010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10101 - assign \form 5'10010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10110 - assign \form 5'10010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10111 - assign \form 5'10010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11000 - assign \form 5'10010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11001 - assign \form 5'10010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11010 - assign \form 5'10010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11011 - assign \form 5'10010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11100 - assign \form 5'10010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11101 - assign \form 5'10010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11110 - assign \form 5'10010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11111 - assign \form 5'10010 - end - sync init - end - process $group_4 - assign \in1_sel 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \in1_sel 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00001 - assign \in1_sel 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00010 - assign \in1_sel 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00011 - assign \in1_sel 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00100 - assign \in1_sel 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00101 - assign \in1_sel 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00110 - assign \in1_sel 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00111 - assign \in1_sel 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01000 - assign \in1_sel 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01001 - assign \in1_sel 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01010 - assign \in1_sel 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01011 - assign \in1_sel 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01100 - assign \in1_sel 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01101 - assign \in1_sel 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01110 - assign \in1_sel 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01111 - assign \in1_sel 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10000 - assign \in1_sel 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10001 - assign \in1_sel 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10010 - assign \in1_sel 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10011 - assign \in1_sel 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10100 - assign \in1_sel 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10101 - assign \in1_sel 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10110 - assign \in1_sel 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10111 - assign \in1_sel 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11000 - assign \in1_sel 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11001 - assign \in1_sel 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11010 - assign \in1_sel 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11011 - assign \in1_sel 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11100 - assign \in1_sel 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11101 - assign \in1_sel 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11110 - assign \in1_sel 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11111 - assign \in1_sel 3'010 - end - sync init - end - process $group_5 - assign \in2_sel 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00001 - assign \in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00010 - assign \in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00011 - assign \in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00100 - assign \in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00101 - assign \in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00110 - assign \in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00111 - assign \in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01000 - assign \in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01001 - assign \in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01010 - assign \in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01011 - assign \in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01100 - assign \in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01101 - assign \in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01110 - assign \in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01111 - assign \in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10000 - assign \in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10001 - assign \in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10010 - assign \in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10011 - assign \in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10100 - assign \in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10101 - assign \in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10110 - assign \in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10111 - assign \in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11000 - assign \in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11001 - assign \in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11010 - assign \in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11011 - assign \in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11100 - assign \in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11101 - assign \in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11110 - assign \in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11111 - assign \in2_sel 4'0001 - end - sync init - end - process $group_6 - assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00001 - assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00010 - assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00011 - assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00100 - assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00101 - assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00110 - assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00111 - assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01000 - assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01001 - assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01010 - assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01011 - assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01100 - assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01101 - assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01110 - assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01111 - assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10000 - assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10001 - assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10010 - assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10011 - assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10100 - assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10101 - assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10110 - assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10111 - assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11000 - assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11001 - assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11010 - assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11011 - assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11100 - assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11101 - assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11110 - assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11111 - assign \in3_sel 2'00 - end - sync init - end - process $group_7 - assign \out_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \out_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00001 - assign \out_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00010 - assign \out_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00011 - assign \out_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00100 - assign \out_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00101 - assign \out_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00110 - assign \out_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00111 - assign \out_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01000 - assign \out_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01001 - assign \out_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01010 - assign \out_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01011 - assign \out_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01100 - assign \out_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01101 - assign \out_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01110 - assign \out_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01111 - assign \out_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10000 - assign \out_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10001 - assign \out_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10010 - assign \out_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10011 - assign \out_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10100 - assign \out_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10101 - assign \out_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10110 - assign \out_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10111 - assign \out_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11000 - assign \out_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11001 - assign \out_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11010 - assign \out_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11011 - assign \out_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11100 - assign \out_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11101 - assign \out_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11110 - assign \out_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11111 - assign \out_sel 2'01 - end - sync init - end - process $group_8 - assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \cr_in 3'101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00001 - assign \cr_in 3'101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00010 - assign \cr_in 3'101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00011 - assign \cr_in 3'101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00100 - assign \cr_in 3'101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00101 - assign \cr_in 3'101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00110 - assign \cr_in 3'101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00111 - assign \cr_in 3'101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01000 - assign \cr_in 3'101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01001 - assign \cr_in 3'101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01010 - assign \cr_in 3'101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01011 - assign \cr_in 3'101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01100 - assign \cr_in 3'101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01101 - assign \cr_in 3'101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01110 - assign \cr_in 3'101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01111 - assign \cr_in 3'101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10000 - assign \cr_in 3'101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10001 - assign \cr_in 3'101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10010 - assign \cr_in 3'101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10011 - assign \cr_in 3'101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10100 - assign \cr_in 3'101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10101 - assign \cr_in 3'101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10110 - assign \cr_in 3'101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10111 - assign \cr_in 3'101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11000 - assign \cr_in 3'101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11001 - assign \cr_in 3'101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11010 - assign \cr_in 3'101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11011 - assign \cr_in 3'101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11100 - assign \cr_in 3'101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11101 - assign \cr_in 3'101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11110 - assign \cr_in 3'101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11111 - assign \cr_in 3'101 - end - sync init - end - process $group_9 - assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00001 - assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00010 - assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00011 - assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00100 - assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00101 - assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00110 - assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00111 - assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01000 - assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01001 - assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01010 - assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01011 - assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01100 - assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01101 - assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01110 - assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01111 - assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10000 - assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10001 - assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10010 - assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10011 - assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10100 - assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10101 - assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10110 - assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10111 - assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11000 - assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11001 - assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11010 - assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11011 - assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11100 - assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11101 - assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11110 - assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11111 - assign \cr_out 3'000 - end - sync init - end - process $group_10 - assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00001 - assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00010 - assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00011 - assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00100 - assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00101 - assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00110 - assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00111 - assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01000 - assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01001 - assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01010 - assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01011 - assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01100 - assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01101 - assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01110 - assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01111 - assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10000 - assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10001 - assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10010 - assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10011 - assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10100 - assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10101 - assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10110 - assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10111 - assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11000 - assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11001 - assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11010 - assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11011 - assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11100 - assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11101 - assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11110 - assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11111 - assign \ldst_len 4'0000 - end - sync init - end - process $group_11 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00001 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00010 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00011 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00100 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00101 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00110 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00111 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01000 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01001 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01010 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01011 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01100 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01101 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01110 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01111 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10000 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10001 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10010 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10011 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10100 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10101 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10110 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10111 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11000 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11001 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11010 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11011 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11100 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11101 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11110 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11111 - assign \upd 2'00 - end - sync init - end - process $group_12 - assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00001 - assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00010 - assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00011 - assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00100 - assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00101 - assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00110 - assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00111 - assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01000 - assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01001 - assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01010 - assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01011 - assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01100 - assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01101 - assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01110 - assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01111 - assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10000 - assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10001 - assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10010 - assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10011 - assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10100 - assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10101 - assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10110 - assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10111 - assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11000 - assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11001 - assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11010 - assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11011 - assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11100 - assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11101 - assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11110 - assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11111 - assign \rc_sel 2'00 - end - sync init - end - process $group_13 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00001 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00010 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00011 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00100 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00101 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00110 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00111 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01000 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01001 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01010 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01011 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01100 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01101 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01110 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01111 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10000 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10001 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10010 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10011 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10100 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10101 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10110 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10111 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11000 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11001 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11010 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11011 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11100 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11101 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11110 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11111 - assign \cry_in 2'00 - end - sync init - end - process $group_14 - assign \asmcode 8'00000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \asmcode 8'01001011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00001 - assign \asmcode 8'01001011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00010 - assign \asmcode 8'01001011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00011 - assign \asmcode 8'01001011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00100 - assign \asmcode 8'01001011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00101 - assign \asmcode 8'01001011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00110 - assign \asmcode 8'01001011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00111 - assign \asmcode 8'01001011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01000 - assign \asmcode 8'01001011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01001 - assign \asmcode 8'01001011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01010 - assign \asmcode 8'01001011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01011 - assign \asmcode 8'01001011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01100 - assign \asmcode 8'01001011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01101 - assign \asmcode 8'01001011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01110 - assign \asmcode 8'01001011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01111 - assign \asmcode 8'01001011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10000 - assign \asmcode 8'01001011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10001 - assign \asmcode 8'01001011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10010 - assign \asmcode 8'01001011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10011 - assign \asmcode 8'01001011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10100 - assign \asmcode 8'01001011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10101 - assign \asmcode 8'01001011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10110 - assign \asmcode 8'01001011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10111 - assign \asmcode 8'01001011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11000 - assign \asmcode 8'01001011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11001 - assign \asmcode 8'01001011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11010 - assign \asmcode 8'01001011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11011 - assign \asmcode 8'01001011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11100 - assign \asmcode 8'01001011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11101 - assign \asmcode 8'01001011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11110 - assign \asmcode 8'01001011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11111 - assign \asmcode 8'01001011 - end - sync init - end - process $group_15 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00001 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00010 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00011 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00100 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00101 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00110 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00111 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01000 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01001 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01010 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01011 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01100 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01101 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01110 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01111 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10000 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10001 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10010 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10011 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10100 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10101 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10110 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10111 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11000 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11001 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11010 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11011 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11100 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11101 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11110 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11111 - assign \inv_a 1'0 - end - sync init - end - process $group_16 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00001 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00010 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00011 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00100 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00101 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00110 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00111 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01000 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01001 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01010 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01011 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01100 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01101 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01110 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01111 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10000 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10001 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10010 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10011 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10100 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10101 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10110 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10111 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11000 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11001 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11010 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11011 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11100 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11101 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11110 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11111 - assign \inv_out 1'0 - end - sync init - end - process $group_17 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00001 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00010 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00011 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00100 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00101 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00110 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00111 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01000 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01001 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01010 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01011 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01100 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01101 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01110 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01111 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10000 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10001 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10010 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10011 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10100 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10101 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10110 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10111 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11000 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11001 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11010 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11011 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11100 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11101 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11110 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11111 - assign \cry_out 1'0 - end - sync init - end - process $group_18 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00001 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00010 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00011 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00100 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00101 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00110 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00111 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01000 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01001 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01010 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01011 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01100 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01101 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01110 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01111 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10000 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10001 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10010 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10011 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10100 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10101 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10110 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10111 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11000 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11001 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11010 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11011 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11100 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11101 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11110 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11111 - assign \br 1'0 - end - sync init - end - process $group_19 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00001 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00010 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00011 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00100 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00101 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00110 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00111 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01000 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01001 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01010 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01011 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01100 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01101 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01110 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01111 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10000 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10001 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10010 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10011 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10100 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10101 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10110 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10111 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11000 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11001 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11010 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11011 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11100 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11101 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11110 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11111 - assign \sgn_ext 1'0 - end - sync init - end - process $group_20 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00001 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00010 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00011 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00100 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00101 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00110 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00111 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01000 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01001 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01010 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01011 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01100 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01101 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01110 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01111 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10000 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10001 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10010 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10011 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10100 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10101 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10110 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10111 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11000 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11001 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11010 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11011 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11100 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11101 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11110 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11111 - assign \rsrv 1'0 - end - sync init - end - process $group_21 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00001 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00010 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00011 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00100 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00101 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00110 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00111 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01000 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01001 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01010 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01011 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01100 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01101 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01110 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01111 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10000 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10001 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10010 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10011 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10100 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10101 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10110 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10111 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11000 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11001 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11010 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11011 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11100 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11101 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11110 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11111 - assign \is_32b 1'0 - end - sync init - end - process $group_22 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00001 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00010 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00011 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00100 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00101 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00110 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00111 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01000 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01001 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01010 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01011 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01100 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01101 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01110 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01111 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10000 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10001 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10010 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10011 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10100 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10101 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10110 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10111 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11000 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11001 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11010 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11011 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11100 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11101 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11110 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11111 - assign \sgn 1'0 - end - sync init - end - process $group_23 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00001 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00010 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00011 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00100 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00101 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00110 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00111 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01000 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01001 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01010 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01011 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01100 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01101 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01110 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01111 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10000 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10001 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10010 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10011 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10100 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10101 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10110 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10111 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11000 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11001 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11010 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11011 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11100 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11101 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11110 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11111 - assign \lk 1'0 - end - sync init - end - process $group_24 - assign \sgl_pipe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \sgl_pipe 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00001 - assign \sgl_pipe 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00010 - assign \sgl_pipe 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00011 - assign \sgl_pipe 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00100 - assign \sgl_pipe 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00101 - assign \sgl_pipe 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00110 - assign \sgl_pipe 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00111 - assign \sgl_pipe 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01000 - assign \sgl_pipe 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01001 - assign \sgl_pipe 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01010 - assign \sgl_pipe 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01011 - assign \sgl_pipe 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01100 - assign \sgl_pipe 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01101 - assign \sgl_pipe 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01110 - assign \sgl_pipe 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01111 - assign \sgl_pipe 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10000 - assign \sgl_pipe 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10001 - assign \sgl_pipe 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10010 - assign \sgl_pipe 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10011 - assign \sgl_pipe 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10100 - assign \sgl_pipe 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10101 - assign \sgl_pipe 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10110 - assign \sgl_pipe 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10111 - assign \sgl_pipe 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11000 - assign \sgl_pipe 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11001 - assign \sgl_pipe 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11010 - assign \sgl_pipe 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11011 - assign \sgl_pipe 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11100 - assign \sgl_pipe 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11101 - assign \sgl_pipe 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11110 - assign \sgl_pipe 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11111 - assign \sgl_pipe 1'1 - end - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.dec2.dec.dec31.dec_sub20" -module \dec_sub20 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" - wire width 32 input 0 \opcode_in - attribute \enum_base_type "Function" - attribute \enum_value_00000000000 "NONE" - attribute \enum_value_00000000010 "ALU" - attribute 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attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute 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wire width 8 output 4 \asmcode - attribute \enum_base_type "In1Sel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "RA" - attribute \enum_value_010 "RA_OR_ZERO" - attribute \enum_value_011 "SPR" - attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 output 5 \in1_sel - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 4 output 6 \in2_sel - attribute \enum_base_type "In3Sel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RS" - attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 2 output 7 \in3_sel - attribute \enum_base_type "OutSel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RT" - attribute \enum_value_10 "RA" - attribute \enum_value_11 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 2 output 8 \out_sel - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 output 9 \cr_in - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 output 10 \cr_out - attribute \enum_base_type "LdstLen" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "is1B" - attribute \enum_value_0010 "is2B" - attribute \enum_value_0100 "is4B" - attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 4 output 11 \ldst_len - attribute \enum_base_type "LDSTMode" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "update" - attribute \enum_value_10 "cix" - attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 2 output 12 \upd - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 2 output 13 \rc_sel - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 2 output 14 \cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 output 15 \inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 output 16 \inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 output 17 \cry_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 output 18 \br - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 output 19 \sgn_ext - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 output 20 \rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 output 21 \is_32b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 output 22 \sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 output 23 \lk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 output 24 \sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:308" - wire width 5 \opcode_switch - process $group_0 - assign \opcode_switch 5'00000 - assign \opcode_switch \opcode_in [10:6] - sync init - end - process $group_1 - assign \function_unit 11'00000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00001 - assign \function_unit 11'00000000100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00010 - assign \function_unit 11'00000000100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10000 - assign \function_unit 11'00000000100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00011 - assign \function_unit 11'00000000100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \function_unit 11'00000000100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10100 - assign \function_unit 11'00000000100 - end - sync init - end - process $group_2 - assign \internal_op 7'0000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00001 - assign \internal_op 7'0100101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00010 - assign \internal_op 7'0100101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10000 - assign \internal_op 7'0100101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00011 - assign \internal_op 7'0100101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \internal_op 7'0100101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10100 - assign \internal_op 7'0100110 - end - sync init - end - process $group_3 - assign \form 5'00000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00001 - assign \form 5'01000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00010 - assign \form 5'01000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10000 - assign \form 5'01000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00011 - assign \form 5'01000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \form 5'01000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10100 - assign \form 5'01000 - end - sync init - end - process $group_4 - assign \in1_sel 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00001 - assign \in1_sel 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00010 - assign \in1_sel 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10000 - assign \in1_sel 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00011 - assign \in1_sel 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \in1_sel 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10100 - assign \in1_sel 3'010 - end - sync init - end - process $group_5 - assign \in2_sel 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00001 - assign \in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00010 - assign \in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10000 - assign \in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00011 - assign \in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10100 - assign \in2_sel 4'0001 - end - sync init - end - process $group_6 - assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00001 - assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00010 - assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10000 - assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00011 - assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10100 - assign \in3_sel 2'01 - end - sync init - end - process $group_7 - assign \out_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00001 - assign \out_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00010 - assign \out_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10000 - assign \out_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00011 - assign \out_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \out_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10100 - assign \out_sel 2'00 - end - sync init - end - process $group_8 - assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00001 - assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00010 - assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10000 - assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00011 - assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10100 - assign \cr_in 3'000 - end - sync init - end - process $group_9 - assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00001 - assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00010 - assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10000 - assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00011 - assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10100 - assign \cr_out 3'000 - end - sync init - end - process $group_10 - assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00001 - assign \ldst_len 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00010 - assign \ldst_len 4'1000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10000 - assign \ldst_len 4'1000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00011 - assign \ldst_len 4'0010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \ldst_len 4'0100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10100 - assign \ldst_len 4'1000 - end - sync init - end - process $group_11 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00001 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00010 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10000 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00011 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10100 - assign \upd 2'00 - end - sync init - end - process $group_12 - assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00001 - assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00010 - assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10000 - assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00011 - assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10100 - assign \rc_sel 2'00 - end - sync init - end - process $group_13 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00001 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00010 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10000 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00011 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10100 - assign \cry_in 2'00 - end - sync init - end - process $group_14 - assign \asmcode 8'00000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00001 - assign \asmcode 8'01001101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00010 - assign \asmcode 8'01010011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10000 - assign \asmcode 8'01010100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00011 - assign \asmcode 8'01011001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \asmcode 8'01100011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10100 - assign \asmcode 8'10101100 - end - sync init - end - process $group_15 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00001 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00010 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10000 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00011 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10100 - assign \inv_a 1'0 - end - sync init - end - process $group_16 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00001 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00010 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10000 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00011 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10100 - assign \inv_out 1'0 - end - sync init - end - process $group_17 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00001 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00010 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10000 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00011 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10100 - assign \cry_out 1'0 - end - sync init - end - process $group_18 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00001 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00010 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10000 - assign \br 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00011 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10100 - assign \br 1'1 - end - sync init - end - process $group_19 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00001 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00010 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10000 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00011 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10100 - assign \sgn_ext 1'0 - end - sync init - end - process $group_20 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00001 - assign \rsrv 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00010 - assign \rsrv 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10000 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00011 - assign \rsrv 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \rsrv 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10100 - assign \rsrv 1'0 - end - sync init - end - process $group_21 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00001 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00010 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10000 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00011 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10100 - assign \is_32b 1'0 - end - sync init - end - process $group_22 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00001 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00010 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10000 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00011 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10100 - assign \sgn 1'0 - end - sync init - end - process $group_23 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00001 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00010 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10000 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00011 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10100 - assign \lk 1'0 - end - sync init - end - process $group_24 - assign \sgl_pipe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00001 - assign \sgl_pipe 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00010 - assign \sgl_pipe 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10000 - assign \sgl_pipe 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00011 - assign \sgl_pipe 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \sgl_pipe 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10100 - assign \sgl_pipe 1'1 - end - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.dec2.dec.dec31.dec_sub21" -module \dec_sub21 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" - wire width 32 input 0 \opcode_in - attribute \enum_base_type "Function" - attribute \enum_value_00000000000 "NONE" - attribute \enum_value_00000000010 "ALU" - attribute \enum_value_00000000100 "LDST" - attribute \enum_value_00000001000 "SHIFT_ROT" - attribute \enum_value_00000010000 "LOGICAL" - attribute \enum_value_00000100000 "BRANCH" - attribute \enum_value_00001000000 "CR" - attribute \enum_value_00010000000 "TRAP" - attribute \enum_value_00100000000 "MUL" - attribute \enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 11 output 1 \function_unit - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 7 output 2 \internal_op - attribute \enum_base_type "Form" - attribute \enum_value_00000 "NONE" - attribute \enum_value_00001 "I" - attribute \enum_value_00010 "B" - attribute \enum_value_00011 "SC" - attribute \enum_value_00100 "D" - attribute \enum_value_00101 "DS" - attribute \enum_value_00110 "DQ" - attribute \enum_value_00111 "DX" - attribute \enum_value_01000 "X" - attribute \enum_value_01001 "XL" - attribute \enum_value_01010 "XFX" - attribute \enum_value_01011 "XFL" - attribute \enum_value_01100 "XX1" - attribute \enum_value_01101 "XX2" - attribute \enum_value_01110 "XX3" - attribute \enum_value_01111 "XX4" - attribute \enum_value_10000 "XS" - attribute \enum_value_10001 "XO" - attribute \enum_value_10010 "A" - attribute \enum_value_10011 "M" - attribute \enum_value_10100 "MD" - attribute \enum_value_10101 "MDS" - attribute \enum_value_10110 "VA" - attribute \enum_value_10111 "VC" - attribute \enum_value_11000 "VX" - attribute \enum_value_11001 "EVX" - attribute \enum_value_11010 "EVS" - attribute \enum_value_11011 "Z22" - attribute \enum_value_11100 "Z23" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 5 output 3 \form - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 8 output 4 \asmcode - attribute \enum_base_type "In1Sel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "RA" - attribute \enum_value_010 "RA_OR_ZERO" - attribute \enum_value_011 "SPR" - attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 output 5 \in1_sel - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 4 output 6 \in2_sel - attribute \enum_base_type "In3Sel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RS" - attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 2 output 7 \in3_sel - attribute \enum_base_type "OutSel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RT" - attribute \enum_value_10 "RA" - attribute \enum_value_11 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 2 output 8 \out_sel - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 output 9 \cr_in - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 output 10 \cr_out - attribute \enum_base_type "LdstLen" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "is1B" - attribute \enum_value_0010 "is2B" - attribute \enum_value_0100 "is4B" - attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 4 output 11 \ldst_len - attribute \enum_base_type "LDSTMode" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "update" - attribute \enum_value_10 "cix" - attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 2 output 12 \upd - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 2 output 13 \rc_sel - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 2 output 14 \cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 output 15 \inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 output 16 \inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 output 17 \cry_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 output 18 \br - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 output 19 \sgn_ext - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 output 20 \rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 output 21 \is_32b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 output 22 \sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 output 23 \lk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 output 24 \sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:308" - wire width 5 \opcode_switch - process $group_0 - assign \opcode_switch 5'00000 - assign \opcode_switch \opcode_in [10:6] - sync init - end - process $group_1 - assign \function_unit 11'00000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11010 - assign \function_unit 11'00000000100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11011 - assign \function_unit 11'00000000100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00001 - assign \function_unit 11'00000000100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \function_unit 11'00000000100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11001 - assign \function_unit 11'00000000100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01011 - assign \function_unit 11'00000000100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01010 - assign \function_unit 11'00000000100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11000 - assign \function_unit 11'00000000100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11110 - assign \function_unit 11'00000000100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11111 - assign \function_unit 11'00000000100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00101 - assign \function_unit 11'00000000100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00100 - assign \function_unit 11'00000000100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11101 - assign \function_unit 11'00000000100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11100 - assign \function_unit 11'00000000100 - end - sync init - end - process $group_2 - assign \internal_op 7'0000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11010 - assign \internal_op 7'0100101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11011 - assign \internal_op 7'0100101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00001 - assign \internal_op 7'0100101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \internal_op 7'0100101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11001 - assign \internal_op 7'0100101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01011 - assign \internal_op 7'0100101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01010 - assign \internal_op 7'0100101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11000 - assign \internal_op 7'0100101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11110 - assign \internal_op 7'0100110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11111 - assign \internal_op 7'0100110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00101 - assign \internal_op 7'0100110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00100 - assign \internal_op 7'0100110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11101 - assign \internal_op 7'0100110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11100 - assign \internal_op 7'0100110 - end - sync init - end - process $group_3 - assign \form 5'00000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11010 - assign \form 5'01000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11011 - assign \form 5'01000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00001 - assign \form 5'01000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \form 5'01000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11001 - assign \form 5'01000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01011 - assign \form 5'01000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01010 - assign \form 5'01000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11000 - assign \form 5'01000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11110 - assign \form 5'01000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11111 - assign \form 5'01000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00101 - assign \form 5'01000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00100 - assign \form 5'01000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11101 - assign \form 5'01000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11100 - assign \form 5'01000 - end - sync init - end - process $group_4 - assign \in1_sel 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11010 - assign \in1_sel 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11011 - assign \in1_sel 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00001 - assign \in1_sel 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \in1_sel 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11001 - assign \in1_sel 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01011 - assign \in1_sel 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01010 - assign \in1_sel 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11000 - assign \in1_sel 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11110 - assign \in1_sel 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11111 - assign \in1_sel 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00101 - assign \in1_sel 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00100 - assign \in1_sel 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11101 - assign \in1_sel 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11100 - assign \in1_sel 3'010 - end - sync init - end - process $group_5 - assign \in2_sel 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11010 - assign \in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11011 - assign \in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00001 - assign \in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11001 - assign \in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01011 - assign \in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01010 - assign \in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11000 - assign \in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11110 - assign \in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11111 - assign \in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00101 - assign \in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00100 - assign \in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11101 - assign \in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11100 - assign \in2_sel 4'0001 - end - sync init - end - process $group_6 - assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11010 - assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11011 - assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00001 - assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11001 - assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01011 - assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01010 - assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11000 - assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11110 - assign \in3_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11111 - assign \in3_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00101 - assign \in3_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00100 - assign \in3_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11101 - assign \in3_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11100 - assign \in3_sel 2'01 - end - sync init - end - process $group_7 - assign \out_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11010 - assign \out_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11011 - assign \out_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00001 - assign \out_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \out_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11001 - assign \out_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01011 - assign \out_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01010 - assign \out_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11000 - assign \out_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11110 - assign \out_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11111 - assign \out_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00101 - assign \out_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00100 - assign \out_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11101 - assign \out_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11100 - assign \out_sel 2'00 - end - sync init - end - process $group_8 - assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11010 - assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11011 - assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00001 - assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11001 - assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01011 - assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01010 - assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11000 - assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11110 - assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11111 - assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00101 - assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00100 - assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11101 - assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11100 - assign \cr_in 3'000 - end - sync init - end - process $group_9 - assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11010 - assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11011 - assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00001 - assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11001 - assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01011 - assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01010 - assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11000 - assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11110 - assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11111 - assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00101 - assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00100 - assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11101 - assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11100 - assign \cr_out 3'000 - end - sync init - end - process $group_10 - assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11010 - assign \ldst_len 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11011 - assign \ldst_len 4'1000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00001 - assign \ldst_len 4'1000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \ldst_len 4'1000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11001 - assign \ldst_len 4'0010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01011 - assign \ldst_len 4'0100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01010 - assign \ldst_len 4'0100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11000 - assign \ldst_len 4'0100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11110 - assign \ldst_len 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11111 - assign \ldst_len 4'1000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00101 - assign \ldst_len 4'1000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00100 - assign \ldst_len 4'1000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11101 - assign \ldst_len 4'0010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11100 - assign \ldst_len 4'0100 - end - sync init - end - process $group_11 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11010 - assign \upd 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11011 - assign \upd 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00001 - assign \upd 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11001 - assign \upd 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01011 - assign \upd 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01010 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11000 - assign \upd 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11110 - assign \upd 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11111 - assign \upd 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00101 - assign \upd 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00100 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11101 - assign \upd 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11100 - assign \upd 2'10 - end - sync init - end - process $group_12 - assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11010 - assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11011 - assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00001 - assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11001 - assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01011 - assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01010 - assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11000 - assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11110 - assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11111 - assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00101 - assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00100 - assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11101 - assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11100 - assign \rc_sel 2'00 - end - sync init - end - process $group_13 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11010 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11011 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00001 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11001 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01011 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01010 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11000 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11110 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11111 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00101 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00100 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11101 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11100 - assign \cry_in 2'00 - end - sync init - end - process $group_14 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11010 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11011 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00001 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11001 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01011 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01010 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11000 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11110 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11111 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00101 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00100 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11101 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11100 - assign \inv_a 1'0 - end - sync init - end - process $group_15 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11010 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11011 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00001 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11001 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01011 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01010 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11000 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11110 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11111 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00101 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00100 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11101 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11100 - assign \inv_out 1'0 - end - sync init - end - process $group_16 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11010 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11011 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00001 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11001 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01011 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01010 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11000 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11110 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11111 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00101 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00100 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11101 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11100 - assign \cry_out 1'0 - end - sync init - end - process $group_17 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11010 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11011 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00001 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11001 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01011 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01010 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11000 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11110 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11111 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00101 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00100 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11101 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11100 - assign \br 1'0 - end - sync init - end - process $group_18 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11010 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11011 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00001 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11001 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01011 - assign \sgn_ext 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01010 - assign \sgn_ext 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11000 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11110 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11111 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00101 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00100 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11101 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11100 - assign \sgn_ext 1'0 - end - sync init - end - process $group_19 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11010 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11011 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00001 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11001 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01011 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01010 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11000 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11110 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11111 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00101 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00100 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11101 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11100 - assign \rsrv 1'0 - end - sync init - end - process $group_20 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11010 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11011 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00001 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11001 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01011 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01010 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11000 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11110 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11111 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00101 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00100 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11101 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11100 - assign \is_32b 1'0 - end - sync init - end - process $group_21 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11010 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11011 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00001 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11001 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01011 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01010 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11000 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11110 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11111 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00101 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00100 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11101 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11100 - assign \sgn 1'0 - end - sync init - end - process $group_22 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11010 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11011 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00001 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11001 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01011 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01010 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11000 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11110 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11111 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00101 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00100 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11101 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11100 - assign \lk 1'0 - end - sync init - end - process $group_23 - assign \sgl_pipe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11010 - assign \sgl_pipe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11011 - assign \sgl_pipe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00001 - assign \sgl_pipe 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \sgl_pipe 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11001 - assign \sgl_pipe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01011 - assign \sgl_pipe 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01010 - assign \sgl_pipe 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11000 - assign \sgl_pipe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11110 - assign \sgl_pipe 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11111 - assign \sgl_pipe 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00101 - assign \sgl_pipe 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00100 - assign \sgl_pipe 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11101 - assign \sgl_pipe 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11100 - assign \sgl_pipe 1'1 - end - sync init - end - process $group_24 - assign \asmcode 8'00000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00001 - assign \asmcode 8'01010110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \asmcode 8'01010111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01011 - assign \asmcode 8'01100100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01010 - assign \asmcode 8'01100101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11000 - assign \asmcode 8'01101000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11110 - assign \asmcode 8'10100110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00101 - assign \asmcode 8'10101111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00100 - assign \asmcode 8'10110000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11100 - end - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.dec2.dec.dec31.dec_sub23" -module \dec_sub23 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" - wire width 32 input 0 \opcode_in - attribute \enum_base_type "Function" - attribute \enum_value_00000000000 "NONE" - attribute \enum_value_00000000010 "ALU" - attribute \enum_value_00000000100 "LDST" - attribute \enum_value_00000001000 "SHIFT_ROT" - attribute \enum_value_00000010000 "LOGICAL" - attribute \enum_value_00000100000 "BRANCH" - attribute \enum_value_00001000000 "CR" - attribute \enum_value_00010000000 "TRAP" - attribute \enum_value_00100000000 "MUL" - attribute \enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 11 output 1 \function_unit - attribute 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\enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 4 output 6 \in2_sel - attribute \enum_base_type "In3Sel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RS" - attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 2 output 7 \in3_sel - attribute \enum_base_type "OutSel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RT" - attribute \enum_value_10 "RA" - attribute \enum_value_11 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 2 output 8 \out_sel - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 output 9 \cr_in - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 output 10 \cr_out - attribute \enum_base_type "LdstLen" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "is1B" - attribute \enum_value_0010 "is2B" - attribute \enum_value_0100 "is4B" - attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 4 output 11 \ldst_len - attribute \enum_base_type "LDSTMode" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "update" - attribute \enum_value_10 "cix" - attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 2 output 12 \upd - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 2 output 13 \rc_sel - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 2 output 14 \cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 output 15 \inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 output 16 \inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 output 17 \cry_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 output 18 \br - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 output 19 \sgn_ext - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 output 20 \rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 output 21 \is_32b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 output 22 \sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 output 23 \lk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 output 24 \sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:308" - wire width 5 \opcode_switch - process $group_0 - assign \opcode_switch 5'00000 - assign \opcode_switch \opcode_in [10:6] - sync init - end - process $group_1 - assign \function_unit 11'00000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00011 - assign \function_unit 11'00000000100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00010 - assign \function_unit 11'00000000100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01011 - assign \function_unit 11'00000000100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01010 - assign \function_unit 11'00000000100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01001 - assign \function_unit 11'00000000100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01000 - assign \function_unit 11'00000000100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00001 - assign \function_unit 11'00000000100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \function_unit 11'00000000100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00111 - assign \function_unit 11'00000000100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00110 - assign \function_unit 11'00000000100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01101 - assign \function_unit 11'00000000100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01100 - assign \function_unit 11'00000000100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00101 - assign \function_unit 11'00000000100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00100 - assign \function_unit 11'00000000100 - end - sync init - end - process $group_2 - assign \internal_op 7'0000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00011 - assign \internal_op 7'0100101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00010 - assign \internal_op 7'0100101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01011 - assign \internal_op 7'0100101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01010 - assign \internal_op 7'0100101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01001 - assign \internal_op 7'0100101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01000 - assign \internal_op 7'0100101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00001 - assign \internal_op 7'0100101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \internal_op 7'0100101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00111 - assign \internal_op 7'0100110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00110 - assign \internal_op 7'0100110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01101 - assign \internal_op 7'0100110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01100 - assign \internal_op 7'0100110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00101 - assign \internal_op 7'0100110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00100 - assign \internal_op 7'0100110 - end - sync init - end - process $group_3 - assign \form 5'00000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00011 - assign \form 5'01000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00010 - assign \form 5'01000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01011 - assign \form 5'01000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01010 - assign \form 5'01000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01001 - assign \form 5'01000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01000 - assign \form 5'01000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00001 - assign \form 5'01000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \form 5'01000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00111 - assign \form 5'01000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00110 - assign \form 5'01000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01101 - assign \form 5'01000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01100 - assign \form 5'01000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00101 - assign \form 5'01000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00100 - assign \form 5'01000 - end - sync init - end - process $group_4 - assign \in1_sel 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00011 - assign \in1_sel 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00010 - assign \in1_sel 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01011 - assign \in1_sel 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01010 - assign \in1_sel 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01001 - assign \in1_sel 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01000 - assign \in1_sel 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00001 - assign \in1_sel 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \in1_sel 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00111 - assign \in1_sel 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00110 - assign \in1_sel 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01101 - assign \in1_sel 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01100 - assign \in1_sel 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00101 - assign \in1_sel 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00100 - assign \in1_sel 3'010 - end - sync init - end - process $group_5 - assign \in2_sel 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00011 - assign \in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00010 - assign \in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01011 - assign \in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01010 - assign \in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01001 - assign \in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01000 - assign \in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00001 - assign \in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00111 - assign \in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00110 - assign \in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01101 - assign \in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01100 - assign \in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00101 - assign \in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00100 - assign \in2_sel 4'0001 - end - sync init - end - process $group_6 - assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00011 - assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00010 - assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01011 - assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01010 - assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01001 - assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01000 - assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00001 - assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00111 - assign \in3_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00110 - assign \in3_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01101 - assign \in3_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01100 - assign \in3_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00101 - assign \in3_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00100 - assign \in3_sel 2'01 - end - sync init - end - process $group_7 - assign \out_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00011 - assign \out_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00010 - assign \out_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01011 - assign \out_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01010 - assign \out_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01001 - assign \out_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01000 - assign \out_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00001 - assign \out_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \out_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00111 - assign \out_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00110 - assign \out_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01101 - assign \out_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01100 - assign \out_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00101 - assign \out_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00100 - assign \out_sel 2'00 - end - sync init - end - process $group_8 - assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00011 - assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00010 - assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01011 - assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01010 - assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01001 - assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01000 - assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00001 - assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00111 - assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00110 - assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01101 - assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01100 - assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00101 - assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00100 - assign \cr_in 3'000 - end - sync init - end - process $group_9 - assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00011 - assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00010 - assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01011 - assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01010 - assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01001 - assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01000 - assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00001 - assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00111 - assign \cr_out 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00110 - assign \cr_out 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01101 - assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01100 - assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00101 - assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00100 - assign \cr_out 3'000 - end - sync init - end - process $group_10 - assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00011 - assign \ldst_len 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00010 - assign \ldst_len 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01011 - assign \ldst_len 4'0010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01010 - assign \ldst_len 4'0010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01001 - assign \ldst_len 4'0010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01000 - assign \ldst_len 4'0010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00001 - assign \ldst_len 4'0100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \ldst_len 4'0100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00111 - assign \ldst_len 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00110 - assign \ldst_len 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01101 - assign \ldst_len 4'0010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01100 - assign \ldst_len 4'0010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00101 - assign \ldst_len 4'0100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00100 - assign \ldst_len 4'0100 - end - sync init - end - process $group_11 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00011 - assign \upd 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00010 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01011 - assign \upd 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01010 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01001 - assign \upd 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01000 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00001 - assign \upd 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00111 - assign \upd 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00110 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01101 - assign \upd 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01100 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00101 - assign \upd 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00100 - assign \upd 2'00 - end - sync init - end - process $group_12 - assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00011 - assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00010 - assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01011 - assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01010 - assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01001 - assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01000 - assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00001 - assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00111 - assign \rc_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00110 - assign \rc_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01101 - assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01100 - assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00101 - assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00100 - assign \rc_sel 2'00 - end - sync init - end - process $group_13 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00011 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00010 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01011 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01010 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01001 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01000 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00001 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00111 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00110 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01101 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01100 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00101 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00100 - assign \cry_in 2'00 - end - sync init - end - process $group_14 - assign \asmcode 8'00000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00011 - assign \asmcode 8'01010000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00010 - assign \asmcode 8'01010001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01011 - assign \asmcode 8'01011011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01010 - assign \asmcode 8'01011100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01001 - assign \asmcode 8'01100000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01000 - assign \asmcode 8'01100001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00001 - assign \asmcode 8'01101010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \asmcode 8'01101011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00111 - assign \asmcode 8'10101001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00110 - assign \asmcode 8'10101010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01101 - assign \asmcode 8'10110101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01100 - assign \asmcode 8'10110110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00101 - assign \asmcode 8'10111011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00100 - assign \asmcode 8'10111100 - end - sync init - end - process $group_15 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00011 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00010 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01011 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01010 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01001 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01000 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00001 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00111 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00110 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01101 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01100 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00101 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00100 - assign \inv_a 1'0 - end - sync init - end - process $group_16 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00011 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00010 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01011 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01010 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01001 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01000 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00001 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00111 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00110 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01101 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01100 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00101 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00100 - assign \inv_out 1'0 - end - sync init - end - process $group_17 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00011 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00010 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01011 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01010 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01001 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01000 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00001 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00111 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00110 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01101 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01100 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00101 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00100 - assign \cry_out 1'0 - end - sync init - end - process $group_18 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00011 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00010 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01011 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01010 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01001 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01000 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00001 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00111 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00110 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01101 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01100 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00101 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00100 - assign \br 1'0 - end - sync init - end - process $group_19 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00011 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00010 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01011 - assign \sgn_ext 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01010 - assign \sgn_ext 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01001 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01000 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00001 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00111 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00110 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01101 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01100 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00101 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00100 - assign \sgn_ext 1'0 - end - sync init - end - process $group_20 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00011 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00010 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01011 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01010 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01001 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01000 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00001 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00111 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00110 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01101 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01100 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00101 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00100 - assign \rsrv 1'0 - end - sync init - end - process $group_21 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00011 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00010 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01011 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01010 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01001 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01000 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00001 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00111 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00110 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01101 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01100 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00101 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00100 - assign \is_32b 1'0 - end - sync init - end - process $group_22 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00011 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00010 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01011 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01010 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01001 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01000 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00001 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00111 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00110 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01101 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01100 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00101 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00100 - assign \sgn 1'0 - end - sync init - end - process $group_23 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00011 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00010 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01011 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01010 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01001 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01000 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00001 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00111 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00110 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01101 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01100 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00101 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00100 - assign \lk 1'0 - end - sync init - end - process $group_24 - assign \sgl_pipe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00011 - assign \sgl_pipe 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00010 - assign \sgl_pipe 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'01011 - assign \sgl_pipe 1'1 - attribute \src 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"/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00101 - assign \out_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00100 - assign \out_sel 2'00 - end - sync init - end - process $group_8 - assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00101 - assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00100 - assign \cr_in 3'000 - end - sync init - end - process $group_9 - assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00101 - assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00100 - assign \cr_out 3'000 - end - sync init - end - process $group_10 - assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00101 - assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00100 - assign \ldst_len 4'0000 - end - sync init - end - process $group_11 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00101 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00100 - assign \upd 2'00 - end - sync init - end - process $group_12 - assign \rc_sel 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"/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 output 20 \rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 output 21 \is_32b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 output 22 \sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 output 23 \lk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 output 24 \sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:308" - wire width 5 \opcode_switch - process $group_0 - assign \opcode_switch 5'00000 - assign \opcode_switch \opcode_in [10:6] - sync init - end - process $group_1 - assign \function_unit 11'00000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00011 - assign \function_unit 11'00000000010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10011 - assign \function_unit 11'00000000010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00001 - assign \function_unit 11'00000000010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10001 - assign \function_unit 11'00000000010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \function_unit 11'00000000010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10000 - assign \function_unit 11'00000000010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00100 - assign \function_unit 11'00000000010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10100 - assign \function_unit 11'00000000010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00111 - assign \function_unit 11'00000000010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10111 - assign \function_unit 11'00000000010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00110 - assign \function_unit 11'00000000010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10110 - assign \function_unit 11'00000000010 - end - sync init - end - process $group_2 - assign \internal_op 7'0000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00011 - assign \internal_op 7'0000010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10011 - assign \internal_op 7'0000010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00001 - assign \internal_op 7'0000010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10001 - assign \internal_op 7'0000010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \internal_op 7'0000010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10000 - assign \internal_op 7'0000010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00100 - assign \internal_op 7'0000010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10100 - assign \internal_op 7'0000010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00111 - assign \internal_op 7'0000010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10111 - assign \internal_op 7'0000010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00110 - assign \internal_op 7'0000010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10110 - assign \internal_op 7'0000010 - end - sync init - end - process $group_3 - assign \form 5'00000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00011 - assign \form 5'10001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10011 - assign \form 5'10001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00001 - assign \form 5'10001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10001 - assign \form 5'10001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \form 5'10001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10000 - assign \form 5'10001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00100 - assign \form 5'10001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10100 - assign \form 5'10001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00111 - assign \form 5'10001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10111 - assign \form 5'10001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00110 - assign \form 5'10001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10110 - assign \form 5'10001 - end - sync init - end - process $group_4 - assign \in1_sel 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00011 - assign \in1_sel 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10011 - assign \in1_sel 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00001 - assign \in1_sel 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10001 - assign \in1_sel 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \in1_sel 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10000 - assign \in1_sel 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00100 - assign \in1_sel 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10100 - assign \in1_sel 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00111 - assign \in1_sel 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10111 - assign \in1_sel 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00110 - assign \in1_sel 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10110 - assign \in1_sel 3'001 - end - sync init - end - process $group_5 - assign \in2_sel 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00011 - assign \in2_sel 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10011 - assign \in2_sel 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00001 - assign \in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10001 - assign \in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10000 - assign \in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00100 - assign \in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10100 - assign \in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00111 - assign \in2_sel 4'1001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10111 - assign \in2_sel 4'1001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00110 - assign \in2_sel 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10110 - assign \in2_sel 4'0000 - end - sync init - end - process $group_6 - assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00011 - assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10011 - assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00001 - assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10001 - assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10000 - assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00100 - assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10100 - assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00111 - assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10111 - assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00110 - assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10110 - assign \in3_sel 2'00 - end - sync init - end - process $group_7 - assign \out_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00011 - assign \out_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10011 - assign \out_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00001 - assign \out_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10001 - assign \out_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \out_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10000 - assign \out_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00100 - assign \out_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10100 - assign \out_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00111 - assign \out_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10111 - assign \out_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00110 - assign \out_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10110 - assign \out_sel 2'01 - end - sync init - end - process $group_8 - assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00011 - assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10011 - assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00001 - assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10001 - assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10000 - assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00100 - assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10100 - assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00111 - assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10111 - assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00110 - assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10110 - assign \cr_in 3'000 - end - sync init - end - process $group_9 - assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00011 - assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10011 - assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00001 - assign \cr_out 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10001 - assign \cr_out 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \cr_out 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10000 - assign \cr_out 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00100 - assign \cr_out 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10100 - assign \cr_out 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00111 - assign \cr_out 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10111 - assign \cr_out 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00110 - assign \cr_out 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10110 - assign \cr_out 3'001 - end - sync init - end - process $group_10 - assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00011 - assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10011 - assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00001 - assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10001 - assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10000 - assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00100 - assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10100 - assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00111 - assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10111 - assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00110 - assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10110 - assign \ldst_len 4'0000 - end - sync init - end - process $group_11 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00011 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10011 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00001 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10001 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10000 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00100 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10100 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00111 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10111 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00110 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10110 - assign \upd 2'00 - end - sync init - end - process $group_12 - assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00011 - assign \rc_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10011 - assign \rc_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00001 - assign \rc_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10001 - assign \rc_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \rc_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10000 - assign \rc_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00100 - assign \rc_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10100 - assign \rc_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00111 - assign \rc_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10111 - assign \rc_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00110 - assign \rc_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10110 - assign \rc_sel 2'10 - end - sync init - end - process $group_13 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00011 - assign \cry_in 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10011 - assign \cry_in 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00001 - assign \cry_in 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10001 - assign \cry_in 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \cry_in 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10000 - assign \cry_in 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00100 - assign \cry_in 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10100 - assign \cry_in 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00111 - assign \cry_in 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10111 - assign \cry_in 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00110 - assign \cry_in 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10110 - assign \cry_in 2'10 - end - sync init - end - process $group_14 - assign \asmcode 8'00000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00011 - assign \asmcode 8'10000100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10011 - assign \asmcode 8'10000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00001 - assign \asmcode 8'10111101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10001 - assign \asmcode 8'11000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \asmcode 8'10111110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10000 - assign \asmcode 8'10111111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00100 - assign \asmcode 8'11000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10100 - assign \asmcode 8'11000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00111 - assign \asmcode 8'11000011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10111 - assign \asmcode 8'11000100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00110 - assign \asmcode 8'11000110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10110 - assign \asmcode 8'11000111 - end - sync init - end - process $group_15 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00011 - assign \inv_a 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10011 - assign \inv_a 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00001 - assign \inv_a 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10001 - assign \inv_a 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \inv_a 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10000 - assign \inv_a 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00100 - assign \inv_a 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10100 - assign \inv_a 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00111 - assign \inv_a 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10111 - assign \inv_a 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00110 - assign \inv_a 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10110 - assign \inv_a 1'1 - end - sync init - end - process $group_16 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00011 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10011 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00001 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10001 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10000 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00100 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10100 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00111 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10111 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00110 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10110 - assign \inv_out 1'0 - end - sync init - end - process $group_17 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00011 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10011 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00001 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10001 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \cry_out 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10000 - assign \cry_out 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00100 - assign \cry_out 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10100 - assign \cry_out 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00111 - assign \cry_out 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10111 - assign \cry_out 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00110 - assign \cry_out 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10110 - assign \cry_out 1'1 - end - sync init - end - process $group_18 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00011 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10011 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00001 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10001 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10000 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00100 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10100 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00111 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10111 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00110 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10110 - assign \br 1'0 - end - sync init - end - process $group_19 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00011 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10011 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00001 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10001 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10000 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00100 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10100 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00111 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10111 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00110 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10110 - assign \sgn_ext 1'0 - end - sync init - end - process $group_20 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00011 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10011 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00001 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10001 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10000 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00100 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10100 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00111 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10111 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00110 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10110 - assign \rsrv 1'0 - end - sync init - end - process $group_21 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00011 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10011 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00001 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10001 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10000 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00100 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10100 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00111 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10111 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00110 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10110 - assign \is_32b 1'0 - end - sync init - end - process $group_22 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00011 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10011 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00001 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10001 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10000 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00100 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10100 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00111 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10111 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00110 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10110 - assign \sgn 1'0 - end - sync init - end - process $group_23 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00011 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10011 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00001 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10001 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10000 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00100 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10100 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00111 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10111 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00110 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10110 - assign \lk 1'0 - end - sync init - end - process $group_24 - assign \sgl_pipe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00011 - assign \sgl_pipe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10011 - assign \sgl_pipe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00001 - assign \sgl_pipe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10001 - assign \sgl_pipe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \sgl_pipe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10000 - assign \sgl_pipe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00100 - assign \sgl_pipe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10100 - assign \sgl_pipe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00111 - assign \sgl_pipe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10111 - assign \sgl_pipe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00110 - assign \sgl_pipe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10110 - assign \sgl_pipe 1'0 - end - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.dec2.dec.dec31.dec_sub24" -module \dec_sub24 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" - wire width 32 input 0 \opcode_in - attribute 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"/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 5 output 3 \form - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 8 output 4 \asmcode - attribute \enum_base_type "In1Sel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "RA" - attribute \enum_value_010 "RA_OR_ZERO" - attribute \enum_value_011 "SPR" - attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 output 5 \in1_sel - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute 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"cix" - attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 2 output 12 \upd - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 2 output 13 \rc_sel - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 2 output 14 \cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 output 15 \inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 output 16 \inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 output 17 \cry_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 output 18 \br - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 output 19 \sgn_ext - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 output 20 \rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 output 21 \is_32b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 output 22 \sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 output 23 \lk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 output 24 \sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:308" - wire width 5 \opcode_switch - process $group_0 - assign \opcode_switch 5'00000 - assign \opcode_switch \opcode_in [10:6] - sync init - end - process $group_1 - assign \function_unit 11'00000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \function_unit 11'00000001000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11000 - assign \function_unit 11'00000001000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11001 - assign \function_unit 11'00000001000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10000 - assign \function_unit 11'00000001000 - end - sync init - end - process $group_2 - assign \internal_op 7'0000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \internal_op 7'0111100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11000 - assign \internal_op 7'0111101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11001 - assign \internal_op 7'0111101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10000 - assign \internal_op 7'0111101 - end - sync init - end - process $group_3 - assign \form 5'00000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \form 5'01000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11000 - assign \form 5'01000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11001 - assign \form 5'01000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10000 - assign \form 5'01000 - end - sync init - end - process $group_4 - assign \in1_sel 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \in1_sel 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11000 - assign \in1_sel 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11001 - assign \in1_sel 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10000 - assign \in1_sel 3'000 - end - sync init - end - process $group_5 - assign \in2_sel 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11000 - assign \in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11001 - assign \in2_sel 4'1011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10000 - assign \in2_sel 4'0001 - end - sync init - end - process $group_6 - assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \in3_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11000 - assign \in3_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11001 - assign \in3_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10000 - assign \in3_sel 2'01 - end - sync init - end - process $group_7 - assign \out_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \out_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11000 - assign \out_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11001 - assign \out_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10000 - assign \out_sel 2'10 - end - sync init - end - process $group_8 - assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11000 - assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11001 - assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10000 - assign \cr_in 3'000 - end - sync init - end - process $group_9 - assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \cr_out 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11000 - assign \cr_out 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11001 - assign \cr_out 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10000 - assign \cr_out 3'001 - end - sync init - end - process $group_10 - assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11000 - assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11001 - assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10000 - assign \ldst_len 4'0000 - end - sync init - end - process $group_11 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11000 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11001 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10000 - assign \upd 2'00 - end - sync init - end - process $group_12 - assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \rc_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11000 - assign \rc_sel 2'10 - attribute \src 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assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11001 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10000 - assign \inv_a 1'0 - end - sync init - end - process $group_16 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11000 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'11001 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'10000 - assign \inv_out 1'0 - end - sync init - end - process $group_17 - assign \cry_out 1'0 - attribute \src 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"/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00010 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \cry_in 2'00 - end - sync init - end - process $group_14 - assign \asmcode 8'00000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00010 - assign \asmcode 8'11001001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00000 - assign \asmcode 8'11001011 - end - sync init - end - process $group_15 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 5'00010 - assign \inv_a 1'0 - attribute \src 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attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src 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\enum_value_11000 "VX" - attribute \enum_value_11001 "EVX" - attribute \enum_value_11010 "EVS" - attribute \enum_value_11011 "Z22" - attribute \enum_value_11100 "Z23" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 5 \dec_sub0_form - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 8 \dec_sub0_asmcode - attribute \enum_base_type "In1Sel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "RA" - attribute \enum_value_010 "RA_OR_ZERO" - attribute \enum_value_011 "SPR" - attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \dec_sub0_in1_sel - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" 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"/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 4 \dec_sub0_ldst_len - attribute \enum_base_type "LDSTMode" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "update" - attribute \enum_value_10 "cix" - attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 2 \dec_sub0_upd - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 2 \dec_sub0_rc_sel - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 2 \dec_sub0_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \dec_sub0_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \dec_sub0_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \dec_sub0_cry_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \dec_sub0_br - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \dec_sub0_sgn_ext - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \dec_sub0_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \dec_sub0_is_32b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \dec_sub0_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \dec_sub0_lk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \dec_sub0_sgl_pipe - cell \dec_sub0 \dec_sub0 - connect \opcode_in \dec_sub0_opcode_in - connect \function_unit \dec_sub0_function_unit - connect \internal_op \dec_sub0_internal_op - connect \form \dec_sub0_form - connect \asmcode \dec_sub0_asmcode - connect \in1_sel \dec_sub0_in1_sel - connect \in2_sel \dec_sub0_in2_sel - connect \in3_sel \dec_sub0_in3_sel - connect \out_sel \dec_sub0_out_sel - connect \cr_in \dec_sub0_cr_in - connect \cr_out \dec_sub0_cr_out - connect \ldst_len \dec_sub0_ldst_len - connect \upd \dec_sub0_upd - connect \rc_sel \dec_sub0_rc_sel - connect \cry_in \dec_sub0_cry_in - connect \inv_a \dec_sub0_inv_a - connect \inv_out \dec_sub0_inv_out - connect \cry_out \dec_sub0_cry_out - connect \br \dec_sub0_br - connect \sgn_ext \dec_sub0_sgn_ext - connect \rsrv \dec_sub0_rsrv - connect \is_32b \dec_sub0_is_32b - connect \sgn \dec_sub0_sgn - connect \lk \dec_sub0_lk - connect \sgl_pipe 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attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src 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- attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 4 \dec_sub4_in2_sel - attribute \enum_base_type "In3Sel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RS" - attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 2 \dec_sub4_in3_sel - attribute \enum_base_type "OutSel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RT" - attribute \enum_value_10 "RA" - attribute \enum_value_11 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 2 \dec_sub4_out_sel - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \dec_sub4_cr_in - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \dec_sub4_cr_out - attribute \enum_base_type "LdstLen" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "is1B" - attribute \enum_value_0010 "is2B" - attribute \enum_value_0100 "is4B" - attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 4 \dec_sub4_ldst_len - attribute \enum_base_type "LDSTMode" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "update" - attribute \enum_value_10 "cix" - attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 2 \dec_sub4_upd - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 2 \dec_sub4_rc_sel - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 2 \dec_sub4_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \dec_sub4_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \dec_sub4_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \dec_sub4_cry_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \dec_sub4_br - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \dec_sub4_sgn_ext - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \dec_sub4_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \dec_sub4_is_32b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \dec_sub4_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \dec_sub4_lk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \dec_sub4_sgl_pipe - cell \dec_sub4 \dec_sub4 - connect \opcode_in \dec_sub4_opcode_in - connect \function_unit \dec_sub4_function_unit - connect \internal_op \dec_sub4_internal_op - connect \form \dec_sub4_form - connect \asmcode \dec_sub4_asmcode - connect \in1_sel \dec_sub4_in1_sel - connect \in2_sel \dec_sub4_in2_sel - connect \in3_sel \dec_sub4_in3_sel - connect \out_sel \dec_sub4_out_sel - connect \cr_in \dec_sub4_cr_in - connect \cr_out \dec_sub4_cr_out - connect \ldst_len \dec_sub4_ldst_len - connect \upd \dec_sub4_upd - connect \rc_sel \dec_sub4_rc_sel - connect \cry_in \dec_sub4_cry_in - connect \inv_a \dec_sub4_inv_a - connect \inv_out \dec_sub4_inv_out - connect \cry_out \dec_sub4_cry_out - connect \br \dec_sub4_br - connect \sgn_ext \dec_sub4_sgn_ext - connect \rsrv \dec_sub4_rsrv - connect \is_32b \dec_sub4_is_32b - connect \sgn \dec_sub4_sgn - connect \lk \dec_sub4_lk - connect \sgl_pipe \dec_sub4_sgl_pipe - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:308" - wire width 10 \opcode_switch - process $group_0 - assign \opcode_switch 10'0000000000 - assign \opcode_switch \opcode_in [10:1] - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:312" - wire width 5 \opc_in - process $group_1 - assign \opc_in 5'00000 - assign \opc_in \opcode_switch [4:0] - sync init - end - process $group_2 - assign \dec_sub10_opcode_in 32'00000000000000000000000000000000 - assign \dec_sub10_opcode_in \opcode_in - sync init - end - process $group_3 - assign \dec_sub28_opcode_in 32'00000000000000000000000000000000 - assign \dec_sub28_opcode_in \opcode_in - sync init - end - process $group_4 - assign \dec_sub0_opcode_in 32'00000000000000000000000000000000 - assign \dec_sub0_opcode_in \opcode_in - sync init - end - process $group_5 - assign \dec_sub26_opcode_in 32'00000000000000000000000000000000 - assign \dec_sub26_opcode_in \opcode_in - sync init - end - process $group_6 - assign \dec_sub19_opcode_in 32'00000000000000000000000000000000 - assign \dec_sub19_opcode_in \opcode_in - sync init - end - process $group_7 - assign \dec_sub22_opcode_in 32'00000000000000000000000000000000 - assign \dec_sub22_opcode_in \opcode_in - sync init - end - process $group_8 - assign \dec_sub9_opcode_in 32'00000000000000000000000000000000 - assign \dec_sub9_opcode_in \opcode_in - sync init - end - process $group_9 - assign \dec_sub11_opcode_in 32'00000000000000000000000000000000 - assign \dec_sub11_opcode_in \opcode_in - sync init - end - process $group_10 - assign \dec_sub27_opcode_in 32'00000000000000000000000000000000 - assign \dec_sub27_opcode_in \opcode_in - sync init - end - process $group_11 - assign \dec_sub15_opcode_in 32'00000000000000000000000000000000 - assign \dec_sub15_opcode_in \opcode_in - sync init - end - process $group_12 - assign \dec_sub20_opcode_in 32'00000000000000000000000000000000 - assign \dec_sub20_opcode_in \opcode_in - sync init - end - process $group_13 - assign \dec_sub21_opcode_in 32'00000000000000000000000000000000 - assign \dec_sub21_opcode_in \opcode_in - sync init - end - process $group_14 - assign \dec_sub23_opcode_in 32'00000000000000000000000000000000 - assign \dec_sub23_opcode_in \opcode_in - sync init - end - process $group_15 - assign \dec_sub16_opcode_in 32'00000000000000000000000000000000 - assign \dec_sub16_opcode_in \opcode_in - sync init - end - process $group_16 - assign \dec_sub18_opcode_in 32'00000000000000000000000000000000 - assign \dec_sub18_opcode_in \opcode_in - sync init - end - process $group_17 - assign \dec_sub8_opcode_in 32'00000000000000000000000000000000 - assign \dec_sub8_opcode_in \opcode_in - sync init - end - process $group_18 - assign \dec_sub24_opcode_in 32'00000000000000000000000000000000 - assign \dec_sub24_opcode_in \opcode_in - sync init - end - process $group_19 - assign \dec_sub4_opcode_in 32'00000000000000000000000000000000 - assign \dec_sub4_opcode_in \opcode_in - sync init - end - process $group_20 - assign \function_unit 11'00000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:315" - switch \opc_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01010 - assign \function_unit \dec_sub10_function_unit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'11100 - assign \function_unit \dec_sub28_function_unit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'00000 - assign \function_unit \dec_sub0_function_unit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'11010 - assign \function_unit \dec_sub26_function_unit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10011 - assign \function_unit \dec_sub19_function_unit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10110 - assign \function_unit \dec_sub22_function_unit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01001 - assign \function_unit \dec_sub9_function_unit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01011 - assign \function_unit \dec_sub11_function_unit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'11011 - assign \function_unit \dec_sub27_function_unit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01111 - assign \function_unit \dec_sub15_function_unit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10100 - assign \function_unit \dec_sub20_function_unit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10101 - assign \function_unit \dec_sub21_function_unit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10111 - assign \function_unit \dec_sub23_function_unit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10000 - assign \function_unit \dec_sub16_function_unit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10010 - assign \function_unit \dec_sub18_function_unit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01000 - assign \function_unit \dec_sub8_function_unit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'11000 - assign \function_unit \dec_sub24_function_unit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'00100 - assign \function_unit \dec_sub4_function_unit - end - sync init - end - process $group_21 - assign \internal_op 7'0000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:315" - switch \opc_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01010 - assign \internal_op \dec_sub10_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'11100 - assign \internal_op \dec_sub28_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'00000 - assign \internal_op \dec_sub0_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'11010 - assign \internal_op \dec_sub26_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10011 - assign \internal_op \dec_sub19_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10110 - assign \internal_op \dec_sub22_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01001 - assign \internal_op \dec_sub9_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01011 - assign \internal_op \dec_sub11_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'11011 - assign \internal_op \dec_sub27_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01111 - assign \internal_op \dec_sub15_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10100 - assign \internal_op \dec_sub20_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10101 - assign \internal_op \dec_sub21_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10111 - assign \internal_op \dec_sub23_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10000 - assign \internal_op \dec_sub16_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10010 - assign \internal_op \dec_sub18_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01000 - assign \internal_op \dec_sub8_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'11000 - assign \internal_op \dec_sub24_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'00100 - assign \internal_op \dec_sub4_internal_op - end - sync init - end - process $group_22 - assign \form 5'00000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:315" - switch \opc_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01010 - assign \form \dec_sub10_form - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'11100 - assign \form \dec_sub28_form - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'00000 - assign \form \dec_sub0_form - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'11010 - assign \form \dec_sub26_form - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10011 - assign \form \dec_sub19_form - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10110 - assign \form \dec_sub22_form - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01001 - assign \form \dec_sub9_form - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01011 - assign \form \dec_sub11_form - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'11011 - assign \form \dec_sub27_form - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01111 - assign \form \dec_sub15_form - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10100 - assign \form \dec_sub20_form - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10101 - assign \form \dec_sub21_form - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10111 - assign \form \dec_sub23_form - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10000 - assign \form \dec_sub16_form - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10010 - assign \form \dec_sub18_form - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01000 - assign \form \dec_sub8_form - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'11000 - assign \form \dec_sub24_form - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'00100 - assign \form \dec_sub4_form - end - sync init - end - process $group_23 - assign \asmcode 8'00000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:315" - switch \opc_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01010 - assign \asmcode \dec_sub10_asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'11100 - assign \asmcode \dec_sub28_asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'00000 - assign \asmcode \dec_sub0_asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'11010 - assign \asmcode \dec_sub26_asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10011 - assign \asmcode \dec_sub19_asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10110 - assign \asmcode \dec_sub22_asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01001 - assign \asmcode \dec_sub9_asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01011 - assign \asmcode \dec_sub11_asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'11011 - assign \asmcode \dec_sub27_asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01111 - assign \asmcode \dec_sub15_asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10100 - assign \asmcode \dec_sub20_asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10101 - assign \asmcode \dec_sub21_asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10111 - assign \asmcode \dec_sub23_asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10000 - assign \asmcode \dec_sub16_asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10010 - assign \asmcode \dec_sub18_asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01000 - assign \asmcode \dec_sub8_asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'11000 - assign \asmcode \dec_sub24_asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'00100 - assign \asmcode \dec_sub4_asmcode - end - sync init - end - process $group_24 - assign \in1_sel 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:315" - switch \opc_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01010 - assign \in1_sel \dec_sub10_in1_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'11100 - assign \in1_sel \dec_sub28_in1_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'00000 - assign \in1_sel \dec_sub0_in1_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'11010 - assign \in1_sel \dec_sub26_in1_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10011 - assign \in1_sel \dec_sub19_in1_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10110 - assign \in1_sel \dec_sub22_in1_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01001 - assign \in1_sel \dec_sub9_in1_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01011 - assign \in1_sel \dec_sub11_in1_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'11011 - assign \in1_sel \dec_sub27_in1_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01111 - assign \in1_sel \dec_sub15_in1_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10100 - assign \in1_sel \dec_sub20_in1_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10101 - assign \in1_sel \dec_sub21_in1_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10111 - assign \in1_sel \dec_sub23_in1_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10000 - assign \in1_sel \dec_sub16_in1_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10010 - assign \in1_sel \dec_sub18_in1_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01000 - assign \in1_sel \dec_sub8_in1_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'11000 - assign \in1_sel \dec_sub24_in1_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'00100 - assign \in1_sel \dec_sub4_in1_sel - end - sync init - end - process $group_25 - assign \in2_sel 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:315" - switch \opc_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01010 - assign \in2_sel \dec_sub10_in2_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'11100 - assign \in2_sel \dec_sub28_in2_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'00000 - assign \in2_sel \dec_sub0_in2_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'11010 - assign \in2_sel \dec_sub26_in2_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10011 - assign \in2_sel \dec_sub19_in2_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10110 - assign \in2_sel \dec_sub22_in2_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01001 - assign \in2_sel \dec_sub9_in2_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01011 - assign \in2_sel \dec_sub11_in2_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'11011 - assign \in2_sel \dec_sub27_in2_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01111 - assign \in2_sel \dec_sub15_in2_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10100 - assign \in2_sel \dec_sub20_in2_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10101 - assign \in2_sel \dec_sub21_in2_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10111 - assign \in2_sel \dec_sub23_in2_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10000 - assign \in2_sel \dec_sub16_in2_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10010 - assign \in2_sel \dec_sub18_in2_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01000 - assign \in2_sel \dec_sub8_in2_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'11000 - assign \in2_sel \dec_sub24_in2_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'00100 - assign \in2_sel \dec_sub4_in2_sel - end - sync init - end - process $group_26 - assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:315" - switch \opc_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01010 - assign \in3_sel \dec_sub10_in3_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'11100 - assign \in3_sel \dec_sub28_in3_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'00000 - assign \in3_sel \dec_sub0_in3_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'11010 - assign \in3_sel \dec_sub26_in3_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10011 - assign \in3_sel \dec_sub19_in3_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10110 - assign \in3_sel \dec_sub22_in3_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01001 - assign \in3_sel \dec_sub9_in3_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01011 - assign \in3_sel \dec_sub11_in3_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'11011 - assign \in3_sel \dec_sub27_in3_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01111 - assign \in3_sel \dec_sub15_in3_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10100 - assign \in3_sel \dec_sub20_in3_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10101 - assign \in3_sel \dec_sub21_in3_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10111 - assign \in3_sel \dec_sub23_in3_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10000 - assign \in3_sel \dec_sub16_in3_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10010 - assign \in3_sel \dec_sub18_in3_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01000 - assign \in3_sel \dec_sub8_in3_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'11000 - assign \in3_sel \dec_sub24_in3_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'00100 - assign \in3_sel \dec_sub4_in3_sel - end - sync init - end - process $group_27 - assign \out_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:315" - switch \opc_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01010 - assign \out_sel \dec_sub10_out_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'11100 - assign \out_sel \dec_sub28_out_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'00000 - assign \out_sel \dec_sub0_out_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'11010 - assign \out_sel \dec_sub26_out_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10011 - assign \out_sel \dec_sub19_out_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10110 - assign \out_sel \dec_sub22_out_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01001 - assign \out_sel \dec_sub9_out_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01011 - assign \out_sel \dec_sub11_out_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'11011 - assign \out_sel \dec_sub27_out_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01111 - assign \out_sel \dec_sub15_out_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10100 - assign \out_sel \dec_sub20_out_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10101 - assign \out_sel \dec_sub21_out_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10111 - assign \out_sel \dec_sub23_out_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10000 - assign \out_sel \dec_sub16_out_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10010 - assign \out_sel \dec_sub18_out_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01000 - assign \out_sel \dec_sub8_out_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'11000 - assign \out_sel \dec_sub24_out_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'00100 - assign \out_sel \dec_sub4_out_sel - end - sync init - end - process $group_28 - assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:315" - switch \opc_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01010 - assign \cr_in \dec_sub10_cr_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'11100 - assign \cr_in \dec_sub28_cr_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'00000 - assign \cr_in \dec_sub0_cr_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'11010 - assign \cr_in \dec_sub26_cr_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10011 - assign \cr_in \dec_sub19_cr_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10110 - assign \cr_in \dec_sub22_cr_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01001 - assign \cr_in \dec_sub9_cr_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01011 - assign \cr_in \dec_sub11_cr_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'11011 - assign \cr_in \dec_sub27_cr_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01111 - assign \cr_in \dec_sub15_cr_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10100 - assign \cr_in \dec_sub20_cr_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10101 - assign \cr_in \dec_sub21_cr_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10111 - assign \cr_in \dec_sub23_cr_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10000 - assign \cr_in \dec_sub16_cr_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10010 - assign \cr_in \dec_sub18_cr_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01000 - assign \cr_in \dec_sub8_cr_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'11000 - assign \cr_in \dec_sub24_cr_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'00100 - assign \cr_in \dec_sub4_cr_in - end - sync init - end - process $group_29 - assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:315" - switch \opc_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01010 - assign \cr_out \dec_sub10_cr_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'11100 - assign \cr_out \dec_sub28_cr_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'00000 - assign \cr_out \dec_sub0_cr_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'11010 - assign \cr_out \dec_sub26_cr_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10011 - assign \cr_out \dec_sub19_cr_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10110 - assign \cr_out \dec_sub22_cr_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01001 - assign \cr_out \dec_sub9_cr_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01011 - assign \cr_out \dec_sub11_cr_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'11011 - assign \cr_out \dec_sub27_cr_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01111 - assign \cr_out \dec_sub15_cr_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10100 - assign \cr_out \dec_sub20_cr_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10101 - assign \cr_out \dec_sub21_cr_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10111 - assign \cr_out \dec_sub23_cr_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10000 - assign \cr_out \dec_sub16_cr_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10010 - assign \cr_out \dec_sub18_cr_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01000 - assign \cr_out \dec_sub8_cr_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'11000 - assign \cr_out \dec_sub24_cr_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'00100 - assign \cr_out \dec_sub4_cr_out - end - sync init - end - process $group_30 - assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:315" - switch \opc_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01010 - assign \ldst_len \dec_sub10_ldst_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'11100 - assign \ldst_len \dec_sub28_ldst_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'00000 - assign \ldst_len \dec_sub0_ldst_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'11010 - assign \ldst_len \dec_sub26_ldst_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10011 - assign \ldst_len \dec_sub19_ldst_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10110 - assign \ldst_len \dec_sub22_ldst_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01001 - assign \ldst_len \dec_sub9_ldst_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01011 - assign \ldst_len \dec_sub11_ldst_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'11011 - assign \ldst_len \dec_sub27_ldst_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01111 - assign \ldst_len \dec_sub15_ldst_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10100 - assign \ldst_len \dec_sub20_ldst_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10101 - assign \ldst_len \dec_sub21_ldst_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10111 - assign \ldst_len \dec_sub23_ldst_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10000 - assign \ldst_len \dec_sub16_ldst_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10010 - assign \ldst_len \dec_sub18_ldst_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01000 - assign \ldst_len \dec_sub8_ldst_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'11000 - assign \ldst_len \dec_sub24_ldst_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'00100 - assign \ldst_len \dec_sub4_ldst_len - end - sync init - end - process $group_31 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:315" - switch \opc_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01010 - assign \upd \dec_sub10_upd - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'11100 - assign \upd \dec_sub28_upd - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'00000 - assign \upd \dec_sub0_upd - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'11010 - assign \upd \dec_sub26_upd - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10011 - assign \upd \dec_sub19_upd - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10110 - assign \upd \dec_sub22_upd - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01001 - assign \upd \dec_sub9_upd - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01011 - assign \upd \dec_sub11_upd - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'11011 - assign \upd \dec_sub27_upd - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01111 - assign \upd \dec_sub15_upd - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10100 - assign \upd \dec_sub20_upd - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10101 - assign \upd \dec_sub21_upd - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10111 - assign \upd \dec_sub23_upd - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10000 - assign \upd \dec_sub16_upd - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10010 - assign \upd \dec_sub18_upd - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01000 - assign \upd \dec_sub8_upd - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'11000 - assign \upd \dec_sub24_upd - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'00100 - assign \upd \dec_sub4_upd - end - sync init - end - process $group_32 - assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:315" - switch \opc_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01010 - assign \rc_sel \dec_sub10_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'11100 - assign \rc_sel \dec_sub28_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'00000 - assign \rc_sel \dec_sub0_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'11010 - assign \rc_sel \dec_sub26_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10011 - assign \rc_sel \dec_sub19_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10110 - assign \rc_sel \dec_sub22_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01001 - assign \rc_sel \dec_sub9_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01011 - assign \rc_sel \dec_sub11_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'11011 - assign \rc_sel \dec_sub27_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01111 - assign \rc_sel \dec_sub15_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10100 - assign \rc_sel \dec_sub20_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10101 - assign \rc_sel \dec_sub21_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10111 - assign \rc_sel \dec_sub23_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10000 - assign \rc_sel \dec_sub16_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10010 - assign \rc_sel \dec_sub18_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01000 - assign \rc_sel \dec_sub8_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'11000 - assign \rc_sel \dec_sub24_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'00100 - assign \rc_sel \dec_sub4_rc_sel - end - sync init - end - process $group_33 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:315" - switch \opc_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01010 - assign \cry_in \dec_sub10_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'11100 - assign \cry_in \dec_sub28_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'00000 - assign \cry_in \dec_sub0_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'11010 - assign \cry_in \dec_sub26_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10011 - assign \cry_in \dec_sub19_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10110 - assign \cry_in \dec_sub22_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01001 - assign \cry_in \dec_sub9_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01011 - assign \cry_in \dec_sub11_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'11011 - assign \cry_in \dec_sub27_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01111 - assign \cry_in \dec_sub15_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10100 - assign \cry_in \dec_sub20_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10101 - assign \cry_in \dec_sub21_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10111 - assign \cry_in \dec_sub23_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10000 - assign \cry_in \dec_sub16_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10010 - assign \cry_in \dec_sub18_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01000 - assign \cry_in \dec_sub8_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'11000 - assign \cry_in \dec_sub24_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'00100 - assign \cry_in \dec_sub4_cry_in - end - sync init - end - process $group_34 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:315" - switch \opc_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01010 - assign \inv_a \dec_sub10_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'11100 - assign \inv_a \dec_sub28_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'00000 - assign \inv_a \dec_sub0_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'11010 - assign \inv_a \dec_sub26_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10011 - assign \inv_a \dec_sub19_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10110 - assign \inv_a \dec_sub22_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01001 - assign \inv_a \dec_sub9_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01011 - assign \inv_a \dec_sub11_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'11011 - assign \inv_a \dec_sub27_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01111 - assign \inv_a \dec_sub15_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10100 - assign \inv_a \dec_sub20_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10101 - assign \inv_a \dec_sub21_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10111 - assign \inv_a \dec_sub23_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10000 - assign \inv_a \dec_sub16_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10010 - assign \inv_a \dec_sub18_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01000 - assign \inv_a \dec_sub8_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'11000 - assign \inv_a \dec_sub24_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'00100 - assign \inv_a \dec_sub4_inv_a - end - sync init - end - process $group_35 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:315" - switch \opc_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01010 - assign \inv_out \dec_sub10_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'11100 - assign \inv_out \dec_sub28_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'00000 - assign \inv_out \dec_sub0_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'11010 - assign \inv_out \dec_sub26_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10011 - assign \inv_out \dec_sub19_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10110 - assign \inv_out \dec_sub22_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01001 - assign \inv_out \dec_sub9_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01011 - assign \inv_out \dec_sub11_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'11011 - assign \inv_out \dec_sub27_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01111 - assign \inv_out \dec_sub15_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10100 - assign \inv_out \dec_sub20_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10101 - assign \inv_out \dec_sub21_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10111 - assign \inv_out \dec_sub23_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10000 - assign \inv_out \dec_sub16_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10010 - assign \inv_out \dec_sub18_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01000 - assign \inv_out \dec_sub8_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'11000 - assign \inv_out \dec_sub24_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'00100 - assign \inv_out \dec_sub4_inv_out - end - sync init - end - process $group_36 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:315" - switch \opc_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01010 - assign \cry_out \dec_sub10_cry_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'11100 - assign \cry_out \dec_sub28_cry_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'00000 - assign \cry_out \dec_sub0_cry_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'11010 - assign \cry_out \dec_sub26_cry_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10011 - assign \cry_out \dec_sub19_cry_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10110 - assign \cry_out \dec_sub22_cry_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01001 - assign \cry_out \dec_sub9_cry_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01011 - assign \cry_out \dec_sub11_cry_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'11011 - assign \cry_out \dec_sub27_cry_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01111 - assign \cry_out \dec_sub15_cry_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10100 - assign \cry_out \dec_sub20_cry_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10101 - assign \cry_out \dec_sub21_cry_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10111 - assign \cry_out \dec_sub23_cry_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10000 - assign \cry_out \dec_sub16_cry_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10010 - assign \cry_out \dec_sub18_cry_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01000 - assign \cry_out \dec_sub8_cry_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'11000 - assign \cry_out \dec_sub24_cry_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'00100 - assign \cry_out \dec_sub4_cry_out - end - sync init - end - process $group_37 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:315" - switch \opc_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01010 - assign \br \dec_sub10_br - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'11100 - assign \br \dec_sub28_br - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'00000 - assign \br \dec_sub0_br - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'11010 - assign \br \dec_sub26_br - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10011 - assign \br \dec_sub19_br - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10110 - assign \br \dec_sub22_br - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01001 - assign \br \dec_sub9_br - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01011 - assign \br \dec_sub11_br - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'11011 - assign \br \dec_sub27_br - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01111 - assign \br \dec_sub15_br - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10100 - assign \br \dec_sub20_br - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10101 - assign \br \dec_sub21_br - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10111 - assign \br \dec_sub23_br - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10000 - assign \br \dec_sub16_br - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10010 - assign \br \dec_sub18_br - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01000 - assign \br \dec_sub8_br - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'11000 - assign \br \dec_sub24_br - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'00100 - assign \br \dec_sub4_br - end - sync init - end - process $group_38 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:315" - switch \opc_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01010 - assign \sgn_ext \dec_sub10_sgn_ext - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'11100 - assign \sgn_ext \dec_sub28_sgn_ext - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'00000 - assign \sgn_ext \dec_sub0_sgn_ext - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'11010 - assign \sgn_ext \dec_sub26_sgn_ext - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10011 - assign \sgn_ext \dec_sub19_sgn_ext - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10110 - assign \sgn_ext \dec_sub22_sgn_ext - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01001 - assign \sgn_ext \dec_sub9_sgn_ext - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01011 - assign \sgn_ext \dec_sub11_sgn_ext - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'11011 - assign \sgn_ext \dec_sub27_sgn_ext - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01111 - assign \sgn_ext \dec_sub15_sgn_ext - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10100 - assign \sgn_ext \dec_sub20_sgn_ext - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10101 - assign \sgn_ext \dec_sub21_sgn_ext - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10111 - assign \sgn_ext \dec_sub23_sgn_ext - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10000 - assign \sgn_ext \dec_sub16_sgn_ext - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10010 - assign \sgn_ext \dec_sub18_sgn_ext - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01000 - assign \sgn_ext \dec_sub8_sgn_ext - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'11000 - assign \sgn_ext \dec_sub24_sgn_ext - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'00100 - assign \sgn_ext \dec_sub4_sgn_ext - end - sync init - end - process $group_39 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:315" - switch \opc_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01010 - assign \rsrv \dec_sub10_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'11100 - assign \rsrv \dec_sub28_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'00000 - assign \rsrv \dec_sub0_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'11010 - assign \rsrv \dec_sub26_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10011 - assign \rsrv \dec_sub19_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10110 - assign \rsrv \dec_sub22_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01001 - assign \rsrv \dec_sub9_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01011 - assign \rsrv \dec_sub11_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'11011 - assign \rsrv \dec_sub27_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01111 - assign \rsrv \dec_sub15_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10100 - assign \rsrv \dec_sub20_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10101 - assign \rsrv \dec_sub21_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10111 - assign \rsrv \dec_sub23_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10000 - assign \rsrv \dec_sub16_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10010 - assign \rsrv \dec_sub18_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01000 - assign \rsrv \dec_sub8_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'11000 - assign \rsrv \dec_sub24_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'00100 - assign \rsrv \dec_sub4_rsrv - end - sync init - end - process $group_40 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:315" - switch \opc_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01010 - assign \is_32b \dec_sub10_is_32b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'11100 - assign \is_32b \dec_sub28_is_32b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'00000 - assign \is_32b \dec_sub0_is_32b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'11010 - assign \is_32b \dec_sub26_is_32b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10011 - assign \is_32b \dec_sub19_is_32b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10110 - assign \is_32b \dec_sub22_is_32b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01001 - assign \is_32b \dec_sub9_is_32b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01011 - assign \is_32b \dec_sub11_is_32b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'11011 - assign \is_32b \dec_sub27_is_32b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01111 - assign \is_32b \dec_sub15_is_32b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10100 - assign \is_32b \dec_sub20_is_32b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10101 - assign \is_32b \dec_sub21_is_32b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10111 - assign \is_32b \dec_sub23_is_32b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10000 - assign \is_32b \dec_sub16_is_32b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10010 - assign \is_32b \dec_sub18_is_32b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01000 - assign \is_32b \dec_sub8_is_32b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'11000 - assign \is_32b \dec_sub24_is_32b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'00100 - assign \is_32b \dec_sub4_is_32b - end - sync init - end - process $group_41 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:315" - switch \opc_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01010 - assign \sgn \dec_sub10_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'11100 - assign \sgn \dec_sub28_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'00000 - assign \sgn \dec_sub0_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'11010 - assign \sgn \dec_sub26_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10011 - assign \sgn \dec_sub19_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10110 - assign \sgn \dec_sub22_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01001 - assign \sgn \dec_sub9_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01011 - assign \sgn \dec_sub11_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'11011 - assign \sgn \dec_sub27_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01111 - assign \sgn \dec_sub15_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10100 - assign \sgn \dec_sub20_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10101 - assign \sgn \dec_sub21_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10111 - assign \sgn \dec_sub23_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10000 - assign \sgn \dec_sub16_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10010 - assign \sgn \dec_sub18_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01000 - assign \sgn \dec_sub8_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'11000 - assign \sgn \dec_sub24_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'00100 - assign \sgn \dec_sub4_sgn - end - sync init - end - process $group_42 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:315" - switch \opc_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01010 - assign \lk \dec_sub10_lk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'11100 - assign \lk \dec_sub28_lk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'00000 - assign \lk \dec_sub0_lk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'11010 - assign \lk \dec_sub26_lk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10011 - assign \lk \dec_sub19_lk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10110 - assign \lk \dec_sub22_lk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01001 - assign \lk \dec_sub9_lk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01011 - assign \lk \dec_sub11_lk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'11011 - assign \lk \dec_sub27_lk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01111 - assign \lk \dec_sub15_lk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10100 - assign \lk \dec_sub20_lk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10101 - assign \lk \dec_sub21_lk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10111 - assign \lk \dec_sub23_lk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10000 - assign \lk \dec_sub16_lk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10010 - assign \lk \dec_sub18_lk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01000 - assign \lk \dec_sub8_lk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'11000 - assign \lk \dec_sub24_lk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'00100 - assign \lk \dec_sub4_lk - end - sync init - end - process $group_43 - assign \sgl_pipe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:315" - switch \opc_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01010 - assign \sgl_pipe \dec_sub10_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'11100 - assign \sgl_pipe \dec_sub28_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'00000 - assign \sgl_pipe \dec_sub0_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'11010 - assign \sgl_pipe \dec_sub26_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10011 - assign \sgl_pipe \dec_sub19_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10110 - assign \sgl_pipe \dec_sub22_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01001 - assign \sgl_pipe \dec_sub9_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01011 - assign \sgl_pipe \dec_sub11_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'11011 - assign \sgl_pipe \dec_sub27_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01111 - assign \sgl_pipe \dec_sub15_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10100 - assign \sgl_pipe \dec_sub20_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10101 - assign \sgl_pipe \dec_sub21_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10111 - assign \sgl_pipe \dec_sub23_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10000 - assign \sgl_pipe \dec_sub16_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'10010 - assign \sgl_pipe \dec_sub18_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'01000 - assign \sgl_pipe \dec_sub8_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'11000 - assign \sgl_pipe \dec_sub24_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:333" - case 5'00100 - assign \sgl_pipe \dec_sub4_sgl_pipe - end - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.dec2.dec.dec58" -module \dec58 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" - wire width 32 input 0 \opcode_in - attribute \enum_base_type "Function" - attribute \enum_value_00000000000 "NONE" - attribute \enum_value_00000000010 "ALU" - attribute \enum_value_00000000100 "LDST" - attribute \enum_value_00000001000 "SHIFT_ROT" - attribute \enum_value_00000010000 "LOGICAL" - attribute \enum_value_00000100000 "BRANCH" - attribute \enum_value_00001000000 "CR" - attribute \enum_value_00010000000 "TRAP" - attribute \enum_value_00100000000 "MUL" - attribute \enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 11 output 1 \function_unit - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 7 output 2 \internal_op - attribute \enum_base_type "Form" - attribute \enum_value_00000 "NONE" - attribute \enum_value_00001 "I" - attribute \enum_value_00010 "B" - attribute \enum_value_00011 "SC" - attribute \enum_value_00100 "D" - attribute \enum_value_00101 "DS" - attribute \enum_value_00110 "DQ" - attribute \enum_value_00111 "DX" - attribute \enum_value_01000 "X" - attribute \enum_value_01001 "XL" - attribute \enum_value_01010 "XFX" - attribute \enum_value_01011 "XFL" - attribute \enum_value_01100 "XX1" - attribute \enum_value_01101 "XX2" - attribute \enum_value_01110 "XX3" - attribute \enum_value_01111 "XX4" - attribute \enum_value_10000 "XS" - attribute \enum_value_10001 "XO" - attribute \enum_value_10010 "A" - attribute \enum_value_10011 "M" - attribute \enum_value_10100 "MD" - attribute \enum_value_10101 "MDS" - attribute \enum_value_10110 "VA" - attribute \enum_value_10111 "VC" - attribute \enum_value_11000 "VX" - attribute \enum_value_11001 "EVX" - attribute \enum_value_11010 "EVS" - attribute \enum_value_11011 "Z22" - attribute \enum_value_11100 "Z23" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 5 output 3 \form - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 8 output 4 \asmcode - attribute \enum_base_type "In1Sel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "RA" - attribute \enum_value_010 "RA_OR_ZERO" - attribute \enum_value_011 "SPR" - attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 output 5 \in1_sel - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 4 output 6 \in2_sel - attribute \enum_base_type "In3Sel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RS" - attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 2 output 7 \in3_sel - attribute \enum_base_type "OutSel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RT" - attribute \enum_value_10 "RA" - attribute \enum_value_11 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 2 output 8 \out_sel - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 output 9 \cr_in - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 output 10 \cr_out - attribute \enum_base_type "LdstLen" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "is1B" - attribute \enum_value_0010 "is2B" - attribute \enum_value_0100 "is4B" - attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 4 output 11 \ldst_len - attribute \enum_base_type "LDSTMode" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "update" - attribute \enum_value_10 "cix" - attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 2 output 12 \upd - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 2 output 13 \rc_sel - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 2 output 14 \cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 output 15 \inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 output 16 \inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 output 17 \cry_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 output 18 \br - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 output 19 \sgn_ext - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 output 20 \rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 output 21 \is_32b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 output 22 \sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 output 23 \lk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 output 24 \sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:308" - wire width 2 \opcode_switch - process $group_0 - assign \opcode_switch 2'00 - assign \opcode_switch \opcode_in [1:0] - sync init - end - process $group_1 - assign \function_unit 11'00000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 2'00 - assign \function_unit 11'00000000100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 2'01 - assign \function_unit 11'00000000100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 2'10 - assign \function_unit 11'00000000100 - end - sync init - end - process $group_2 - assign \internal_op 7'0000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 2'00 - assign \internal_op 7'0100101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 2'01 - assign \internal_op 7'0100101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 2'10 - assign \internal_op 7'0100101 - end - sync init - end - process $group_3 - assign \form 5'00000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 2'00 - assign \form 5'00101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 2'01 - assign \form 5'00101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 2'10 - assign \form 5'00101 - end - sync init - end - process $group_4 - assign \in1_sel 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 2'00 - assign \in1_sel 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 2'01 - assign \in1_sel 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 2'10 - assign \in1_sel 3'010 - end - sync init - end - process $group_5 - assign \in2_sel 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 2'00 - assign \in2_sel 4'1000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 2'01 - assign \in2_sel 4'1000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 2'10 - assign \in2_sel 4'1000 - end - sync init - end - process $group_6 - assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 2'00 - assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 2'01 - assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 2'10 - assign \in3_sel 2'00 - end - sync init - end - process $group_7 - assign \out_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 2'00 - assign \out_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 2'01 - assign \out_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 2'10 - assign \out_sel 2'01 - end - sync init - end - process $group_8 - assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 2'00 - assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 2'01 - assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 2'10 - assign \cr_in 3'000 - end - sync init - end - process $group_9 - assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 2'00 - assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 2'01 - assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 2'10 - assign \cr_out 3'000 - end - sync init - end - process $group_10 - assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 2'00 - assign \ldst_len 4'1000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 2'01 - assign \ldst_len 4'1000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 2'10 - assign \ldst_len 4'0100 - end - sync init - end - process $group_11 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 2'00 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 2'01 - assign \upd 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 2'10 - assign \upd 2'00 - end - sync init - end - process $group_12 - assign \rc_sel 2'00 - attribute \src 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width 1 \dec58_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \dec58_is_32b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \dec58_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \dec58_lk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \dec58_sgl_pipe - cell \dec58 \dec58 - connect \opcode_in \dec58_opcode_in - connect \function_unit \dec58_function_unit - connect \internal_op \dec58_internal_op - connect \form \dec58_form - connect \asmcode \dec58_asmcode - connect \in1_sel \dec58_in1_sel - connect \in2_sel \dec58_in2_sel - connect \in3_sel \dec58_in3_sel - connect \out_sel \dec58_out_sel - connect \cr_in \dec58_cr_in - connect \cr_out \dec58_cr_out - connect \ldst_len \dec58_ldst_len - connect \upd \dec58_upd - connect \rc_sel \dec58_rc_sel - connect \cry_in \dec58_cry_in - connect \inv_a \dec58_inv_a - connect \inv_out \dec58_inv_out - connect \cry_out \dec58_cry_out - connect \br \dec58_br - connect \sgn_ext \dec58_sgn_ext - connect \rsrv \dec58_rsrv - connect \is_32b \dec58_is_32b - connect \sgn \dec58_sgn - connect \lk \dec58_lk - connect \sgl_pipe \dec58_sgl_pipe - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:270" - wire width 32 \dec62_opcode_in - attribute \enum_base_type "Function" - attribute \enum_value_00000000000 "NONE" - attribute \enum_value_00000000010 "ALU" - attribute \enum_value_00000000100 "LDST" - attribute \enum_value_00000001000 "SHIFT_ROT" - attribute \enum_value_00000010000 "LOGICAL" - attribute \enum_value_00000100000 "BRANCH" - attribute \enum_value_00001000000 "CR" - attribute \enum_value_00010000000 "TRAP" - attribute \enum_value_00100000000 "MUL" - attribute \enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 11 \dec62_function_unit - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 7 \dec62_internal_op - attribute \enum_base_type "Form" - attribute \enum_value_00000 "NONE" - attribute \enum_value_00001 "I" - attribute \enum_value_00010 "B" - attribute \enum_value_00011 "SC" - attribute \enum_value_00100 "D" - attribute \enum_value_00101 "DS" - attribute \enum_value_00110 "DQ" - attribute \enum_value_00111 "DX" - attribute \enum_value_01000 "X" - attribute \enum_value_01001 "XL" - attribute \enum_value_01010 "XFX" - attribute \enum_value_01011 "XFL" - attribute \enum_value_01100 "XX1" - attribute \enum_value_01101 "XX2" - attribute \enum_value_01110 "XX3" - attribute \enum_value_01111 "XX4" - attribute \enum_value_10000 "XS" - attribute \enum_value_10001 "XO" - attribute \enum_value_10010 "A" - attribute \enum_value_10011 "M" - attribute \enum_value_10100 "MD" - attribute \enum_value_10101 "MDS" - attribute \enum_value_10110 "VA" - attribute \enum_value_10111 "VC" - attribute \enum_value_11000 "VX" - attribute \enum_value_11001 "EVX" - attribute \enum_value_11010 "EVS" - attribute \enum_value_11011 "Z22" - attribute \enum_value_11100 "Z23" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 5 \dec62_form - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 8 \dec62_asmcode - attribute \enum_base_type "In1Sel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "RA" - attribute \enum_value_010 "RA_OR_ZERO" - attribute \enum_value_011 "SPR" - attribute \enum_value_100 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \dec62_in1_sel - attribute \enum_base_type "In2Sel" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "RB" - attribute \enum_value_0010 "CONST_UI" - attribute \enum_value_0011 "CONST_SI" - attribute \enum_value_0100 "CONST_UI_HI" - attribute \enum_value_0101 "CONST_SI_HI" - attribute \enum_value_0110 "CONST_LI" - attribute \enum_value_0111 "CONST_BD" - attribute \enum_value_1000 "CONST_DS" - attribute \enum_value_1001 "CONST_M1" - attribute \enum_value_1010 "CONST_SH" - attribute \enum_value_1011 "CONST_SH32" - attribute \enum_value_1100 "SPR" - attribute \enum_value_1101 "RS" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 4 \dec62_in2_sel - attribute \enum_base_type "In3Sel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RS" - attribute \enum_value_10 "RB" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 2 \dec62_in3_sel - attribute \enum_base_type "OutSel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RT" - attribute \enum_value_10 "RA" - attribute \enum_value_11 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 2 \dec62_out_sel - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \dec62_cr_in - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 3 \dec62_cr_out - attribute \enum_base_type "LdstLen" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "is1B" - attribute \enum_value_0010 "is2B" - attribute \enum_value_0100 "is4B" - attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 4 \dec62_ldst_len - attribute \enum_base_type "LDSTMode" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "update" - attribute \enum_value_10 "cix" - attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 2 \dec62_upd - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 2 \dec62_rc_sel - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 2 \dec62_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \dec62_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \dec62_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \dec62_cry_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \dec62_br - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \dec62_sgn_ext - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \dec62_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \dec62_is_32b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \dec62_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \dec62_lk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \dec62_sgl_pipe - cell \dec62 \dec62 - connect \opcode_in \dec62_opcode_in - connect \function_unit \dec62_function_unit - connect \internal_op \dec62_internal_op - connect \form \dec62_form - connect \asmcode \dec62_asmcode - connect \in1_sel \dec62_in1_sel - connect \in2_sel \dec62_in2_sel - connect \in3_sel \dec62_in3_sel - connect \out_sel \dec62_out_sel - connect \cr_in \dec62_cr_in - connect \cr_out \dec62_cr_out - connect \ldst_len \dec62_ldst_len - connect \upd \dec62_upd - connect \rc_sel \dec62_rc_sel - connect \cry_in \dec62_cry_in - connect \inv_a \dec62_inv_a - connect \inv_out \dec62_inv_out - connect \cry_out \dec62_cry_out - connect \br \dec62_br - connect \sgn_ext \dec62_sgn_ext - connect \rsrv \dec62_rsrv - connect \is_32b \dec62_is_32b - connect \sgn \dec62_sgn - connect \lk \dec62_lk - connect \sgl_pipe \dec62_sgl_pipe - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:308" - wire width 6 \opcode_switch - process $group_0 - assign \opcode_switch 6'000000 - assign \opcode_switch \opcode_in [31:26] - sync init - end - process $group_1 - assign \dec19_opcode_in 32'00000000000000000000000000000000 - assign \dec19_opcode_in \opcode_in - sync init - end - process $group_2 - assign \dec30_opcode_in 32'00000000000000000000000000000000 - assign \dec30_opcode_in \opcode_in - sync init - end - process $group_3 - assign \dec31_opcode_in 32'00000000000000000000000000000000 - assign \dec31_opcode_in \opcode_in - sync init - end - process $group_4 - assign \dec58_opcode_in 32'00000000000000000000000000000000 - assign \dec58_opcode_in \opcode_in - sync init - end - process $group_5 - assign \dec62_opcode_in 32'00000000000000000000000000000000 - assign \dec62_opcode_in \opcode_in - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:308" - wire width 32 \opcode_switch$1 - process $group_6 - assign \function_unit 11'00000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'010011 - assign \function_unit \dec19_function_unit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'011110 - assign \function_unit \dec30_function_unit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'011111 - assign \function_unit \dec31_function_unit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'111010 - assign \function_unit \dec58_function_unit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'111110 - assign \function_unit \dec62_function_unit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'001100 - assign \function_unit 11'00000000010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'001101 - assign \function_unit 11'00000000010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'001110 - assign \function_unit 11'00000000010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'001111 - assign \function_unit 11'00000000010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'010001 - assign \function_unit 11'00010000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'011100 - assign \function_unit 11'00000010000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'011101 - assign \function_unit 11'00000010000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'010010 - assign \function_unit 11'00000100000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'010000 - assign \function_unit 11'00000100000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'001011 - assign \function_unit 11'00000000010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'001010 - assign \function_unit 11'00000000010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'100010 - assign \function_unit 11'00000000100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'100011 - assign \function_unit 11'00000000100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'101010 - assign \function_unit 11'00000000100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'101011 - assign \function_unit 11'00000000100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'101000 - assign \function_unit 11'00000000100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'101001 - assign \function_unit 11'00000000100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'100000 - assign \function_unit 11'00000000100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'100001 - assign \function_unit 11'00000000100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'000111 - assign \function_unit 11'00100000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'011000 - assign \function_unit 11'00000010000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'011001 - assign \function_unit 11'00000010000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'010100 - assign \function_unit 11'00000001000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'010101 - assign \function_unit 11'00000001000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'010111 - assign \function_unit 11'00000001000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'100110 - assign \function_unit 11'00000000100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'100111 - assign \function_unit 11'00000000100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'101100 - assign \function_unit 11'00000000100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'101101 - assign \function_unit 11'00000000100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'100100 - assign \function_unit 11'00000000100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'100101 - assign \function_unit 11'00000000100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'001000 - assign \function_unit 11'00000000010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'000010 - assign \function_unit 11'00010000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'000011 - assign \function_unit 11'00010000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'011010 - assign \function_unit 11'00000010000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'011011 - assign \function_unit 11'00000010000 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 32'000000---------------0100000000- - assign \function_unit 11'00000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 32'01100000000000000000000000000000 - assign \function_unit 11'00000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 32'000001---------------0000000011- - assign \function_unit 11'00000000000 - end - sync init - end - process $group_7 - assign \internal_op 7'0000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'010011 - assign \internal_op \dec19_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'011110 - assign \internal_op \dec30_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'011111 - assign \internal_op \dec31_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'111010 - assign \internal_op \dec58_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'111110 - assign \internal_op \dec62_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'001100 - assign \internal_op 7'0000010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'001101 - assign \internal_op 7'0000010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'001110 - assign \internal_op 7'0000010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'001111 - assign \internal_op 7'0000010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'010001 - assign \internal_op 7'1001001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'011100 - assign \internal_op 7'0000100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'011101 - assign \internal_op 7'0000100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'010010 - assign \internal_op 7'0000110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'010000 - assign \internal_op 7'0000111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'001011 - assign \internal_op 7'0001010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'001010 - assign \internal_op 7'0001010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'100010 - assign \internal_op 7'0100101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'100011 - assign \internal_op 7'0100101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'101010 - assign \internal_op 7'0100101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'101011 - assign \internal_op 7'0100101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'101000 - assign \internal_op 7'0100101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'101001 - assign \internal_op 7'0100101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'100000 - assign \internal_op 7'0100101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'100001 - assign \internal_op 7'0100101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'000111 - assign \internal_op 7'0110010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'011000 - assign \internal_op 7'0110101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'011001 - assign \internal_op 7'0110101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'010100 - assign \internal_op 7'0111000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'010101 - assign \internal_op 7'0111000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'010111 - assign \internal_op 7'0111000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'100110 - assign \internal_op 7'0100110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'100111 - assign \internal_op 7'0100110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'101100 - assign \internal_op 7'0100110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'101101 - assign \internal_op 7'0100110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'100100 - assign \internal_op 7'0100110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'100101 - assign \internal_op 7'0100110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'001000 - assign \internal_op 7'0000010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'000010 - assign \internal_op 7'0111111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'000011 - assign \internal_op 7'0111111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'011010 - assign \internal_op 7'1000011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'011011 - assign \internal_op 7'1000011 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 32'000000---------------0100000000- - assign \internal_op 7'0000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 32'01100000000000000000000000000000 - assign \internal_op 7'0000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 32'000001---------------0000000011- - assign \internal_op 7'1000100 - end - sync init - end - attribute \enum_base_type "Form" - attribute \enum_value_00000 "NONE" - attribute \enum_value_00001 "I" - attribute \enum_value_00010 "B" - attribute \enum_value_00011 "SC" - attribute \enum_value_00100 "D" - attribute \enum_value_00101 "DS" - attribute \enum_value_00110 "DQ" - attribute \enum_value_00111 "DX" - attribute \enum_value_01000 "X" - attribute \enum_value_01001 "XL" - attribute \enum_value_01010 "XFX" - attribute \enum_value_01011 "XFL" - attribute \enum_value_01100 "XX1" - attribute \enum_value_01101 "XX2" - attribute \enum_value_01110 "XX3" - attribute \enum_value_01111 "XX4" - attribute \enum_value_10000 "XS" - attribute \enum_value_10001 "XO" - attribute \enum_value_10010 "A" - attribute \enum_value_10011 "M" - attribute \enum_value_10100 "MD" - attribute \enum_value_10101 "MDS" - attribute \enum_value_10110 "VA" - attribute \enum_value_10111 "VC" - attribute \enum_value_11000 "VX" - attribute \enum_value_11001 "EVX" - attribute \enum_value_11010 "EVS" - attribute \enum_value_11011 "Z22" - attribute \enum_value_11100 "Z23" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 5 \form - process $group_8 - assign \form 5'00000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'010011 - assign \form \dec19_form - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'011110 - assign \form \dec30_form - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'011111 - assign \form \dec31_form - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'111010 - assign \form \dec58_form - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'111110 - assign \form \dec62_form - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'001100 - assign \form 5'00100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'001101 - assign \form 5'00100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'001110 - assign \form 5'00100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'001111 - assign \form 5'00100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'010001 - assign \form 5'00011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'011100 - assign \form 5'00010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'011101 - assign \form 5'00010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'010010 - assign \form 5'00001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'010000 - assign \form 5'00010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'001011 - assign \form 5'00100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'001010 - assign \form 5'00100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'100010 - assign \form 5'00100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'100011 - assign \form 5'00100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'101010 - assign \form 5'00100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'101011 - assign \form 5'00100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'101000 - assign \form 5'00100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'101001 - assign \form 5'00100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'100000 - assign \form 5'00100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'100001 - assign \form 5'00100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'000111 - assign \form 5'00100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'011000 - assign \form 5'00100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'011001 - assign \form 5'00100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'010100 - assign \form 5'10011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'010101 - assign \form 5'10011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'010111 - assign \form 5'10011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'100110 - assign \form 5'00100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'100111 - assign \form 5'00100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'101100 - assign \form 5'00100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'101101 - assign \form 5'00100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'100100 - assign \form 5'00100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'100101 - assign \form 5'00100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'001000 - assign \form 5'00100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'000010 - assign \form 5'00100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'000011 - assign \form 5'00100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'011010 - assign \form 5'00100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'011011 - assign \form 5'00100 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 32'000000---------------0100000000- - assign \form 5'00000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 32'01100000000000000000000000000000 - assign \form 5'00100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 32'000001---------------0000000011- - assign \form 5'00000 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 8 \asmcode - process $group_9 - assign \asmcode 8'00000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'010011 - assign \asmcode \dec19_asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'011110 - assign \asmcode \dec30_asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'011111 - assign \asmcode \dec31_asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'111010 - assign \asmcode \dec58_asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'111110 - assign \asmcode \dec62_asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'001100 - assign \asmcode 8'00000111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'001101 - assign \asmcode 8'00001000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'001110 - assign \asmcode 8'00000110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'001111 - assign \asmcode 8'00001001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'010001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'011100 - assign \asmcode 8'00010001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'011101 - assign \asmcode 8'00010010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'010010 - assign \asmcode 8'00010100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'010000 - assign \asmcode 8'00010101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'001011 - assign \asmcode 8'00011101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'001010 - assign \asmcode 8'00011111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'100010 - assign \asmcode 8'01001110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'100011 - assign \asmcode 8'01001111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'101010 - assign \asmcode 8'01011000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'101011 - assign \asmcode 8'01011010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'101000 - assign \asmcode 8'01011110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'101001 - assign \asmcode 8'01011111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'100000 - assign \asmcode 8'01100111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'100001 - assign \asmcode 8'01101001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'000111 - assign \asmcode 8'10000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'011000 - assign \asmcode 8'10001010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'011001 - assign \asmcode 8'10001011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'010100 - assign \asmcode 8'10011000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'010101 - assign \asmcode 8'10011001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'010111 - assign \asmcode 8'10011010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'100110 - assign \asmcode 8'10100101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'100111 - assign \asmcode 8'10101000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'101100 - assign \asmcode 8'10110001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'101101 - assign \asmcode 8'10110100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'100100 - assign \asmcode 8'10110111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'100101 - assign \asmcode 8'10111010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'001000 - assign \asmcode 8'11000010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'000010 - assign \asmcode 8'11001010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'000011 - assign \asmcode 8'11001100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'011010 - assign \asmcode 8'11001110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'011011 - assign \asmcode 8'11001111 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 32'000000---------------0100000000- - assign \asmcode 8'00010011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 32'01100000000000000000000000000000 - assign \asmcode 8'10000110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 32'000001---------------0000000011- - assign \asmcode 8'10011100 - end - sync init - end - process $group_10 - assign \in1_sel 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'010011 - assign \in1_sel \dec19_in1_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'011110 - assign \in1_sel \dec30_in1_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'011111 - assign \in1_sel \dec31_in1_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'111010 - assign \in1_sel \dec58_in1_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'111110 - assign \in1_sel \dec62_in1_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'001100 - assign \in1_sel 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'001101 - assign \in1_sel 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'001110 - assign \in1_sel 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'001111 - assign \in1_sel 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'010001 - assign \in1_sel 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'011100 - assign \in1_sel 3'100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'011101 - assign \in1_sel 3'100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'010010 - assign \in1_sel 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'010000 - assign \in1_sel 3'011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'001011 - assign \in1_sel 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'001010 - assign \in1_sel 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'100010 - assign \in1_sel 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'100011 - assign \in1_sel 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'101010 - assign \in1_sel 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'101011 - assign \in1_sel 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'101000 - assign \in1_sel 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'101001 - assign \in1_sel 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'100000 - assign \in1_sel 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'100001 - assign \in1_sel 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'000111 - assign \in1_sel 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'011000 - assign \in1_sel 3'100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'011001 - assign \in1_sel 3'100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'010100 - assign \in1_sel 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'010101 - assign \in1_sel 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'010111 - assign \in1_sel 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'100110 - assign \in1_sel 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'100111 - assign \in1_sel 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'101100 - assign \in1_sel 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'101101 - assign \in1_sel 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'100100 - assign \in1_sel 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'100101 - assign \in1_sel 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'001000 - assign \in1_sel 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'000010 - assign \in1_sel 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'000011 - assign \in1_sel 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'011010 - assign \in1_sel 3'100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'011011 - assign \in1_sel 3'100 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 32'000000---------------0100000000- - assign \in1_sel 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 32'01100000000000000000000000000000 - assign \in1_sel 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 32'000001---------------0000000011- - assign \in1_sel 3'000 - end - sync init - end - process $group_11 - assign \in2_sel 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'010011 - assign \in2_sel \dec19_in2_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'011110 - assign \in2_sel \dec30_in2_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'011111 - assign \in2_sel \dec31_in2_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'111010 - assign \in2_sel \dec58_in2_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'111110 - assign \in2_sel \dec62_in2_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'001100 - assign \in2_sel 4'0011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'001101 - assign \in2_sel 4'0011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'001110 - assign \in2_sel 4'0011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'001111 - assign \in2_sel 4'0101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'010001 - assign \in2_sel 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'011100 - assign \in2_sel 4'0010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'011101 - assign \in2_sel 4'0100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'010010 - assign \in2_sel 4'0110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'010000 - assign \in2_sel 4'0111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'001011 - assign \in2_sel 4'0011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'001010 - assign \in2_sel 4'0010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'100010 - assign \in2_sel 4'0011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'100011 - assign \in2_sel 4'0011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'101010 - assign \in2_sel 4'0011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'101011 - assign \in2_sel 4'0011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'101000 - assign \in2_sel 4'0011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'101001 - assign \in2_sel 4'0011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'100000 - assign \in2_sel 4'0011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'100001 - assign \in2_sel 4'0011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'000111 - assign \in2_sel 4'0011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'011000 - assign \in2_sel 4'0010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'011001 - assign \in2_sel 4'0100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'010100 - assign \in2_sel 4'1011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'010101 - assign \in2_sel 4'1011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'010111 - assign \in2_sel 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'100110 - assign \in2_sel 4'0011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'100111 - assign \in2_sel 4'0011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'101100 - assign \in2_sel 4'0011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'101101 - assign \in2_sel 4'0011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'100100 - assign \in2_sel 4'0011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'100101 - assign \in2_sel 4'0011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'001000 - assign \in2_sel 4'0011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'000010 - assign \in2_sel 4'0011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'000011 - assign \in2_sel 4'0011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'011010 - assign \in2_sel 4'0010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'011011 - assign \in2_sel 4'0100 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 32'000000---------------0100000000- - assign \in2_sel 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 32'01100000000000000000000000000000 - assign \in2_sel 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 32'000001---------------0000000011- - assign \in2_sel 4'0000 - end - sync init - end - process $group_12 - assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'010011 - assign \in3_sel \dec19_in3_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'011110 - assign \in3_sel \dec30_in3_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'011111 - assign \in3_sel \dec31_in3_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'111010 - assign \in3_sel \dec58_in3_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'111110 - assign \in3_sel \dec62_in3_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'001100 - assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'001101 - assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'001110 - assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'001111 - assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'010001 - assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'011100 - assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'011101 - assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'010010 - assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'010000 - assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'001011 - assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'001010 - assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'100010 - assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'100011 - assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'101010 - assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'101011 - assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'101000 - assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'101001 - assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'100000 - assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'100001 - assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'000111 - assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'011000 - assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'011001 - assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'010100 - assign \in3_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'010101 - assign \in3_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'010111 - assign \in3_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'100110 - assign \in3_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'100111 - assign \in3_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'101100 - assign \in3_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'101101 - assign \in3_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'100100 - assign \in3_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'100101 - assign \in3_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'001000 - assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'000010 - assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'000011 - assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'011010 - assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'011011 - assign \in3_sel 2'00 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 32'000000---------------0100000000- - assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 32'01100000000000000000000000000000 - assign \in3_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 32'000001---------------0000000011- - assign \in3_sel 2'00 - end - sync init - end - process $group_13 - assign \out_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'010011 - assign \out_sel \dec19_out_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'011110 - assign \out_sel \dec30_out_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'011111 - assign \out_sel \dec31_out_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'111010 - assign \out_sel \dec58_out_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'111110 - assign \out_sel \dec62_out_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'001100 - assign \out_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'001101 - assign \out_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'001110 - assign \out_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'001111 - assign \out_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'010001 - assign \out_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'011100 - assign \out_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'011101 - assign \out_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'010010 - assign \out_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'010000 - assign \out_sel 2'11 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'001011 - assign \out_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'001010 - assign \out_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'100010 - assign \out_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'100011 - assign \out_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'101010 - assign \out_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'101011 - assign \out_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'101000 - assign \out_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'101001 - assign \out_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'100000 - assign \out_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'100001 - assign \out_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'000111 - assign \out_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'011000 - assign \out_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'011001 - assign \out_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'010100 - assign \out_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'010101 - assign \out_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'010111 - assign \out_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'100110 - assign \out_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'100111 - assign \out_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'101100 - assign \out_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'101101 - assign \out_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'100100 - assign \out_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'100101 - assign \out_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'001000 - assign \out_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'000010 - assign \out_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'000011 - assign \out_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'011010 - assign \out_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'011011 - assign \out_sel 2'10 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 32'000000---------------0100000000- - assign \out_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 32'01100000000000000000000000000000 - assign \out_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 32'000001---------------0000000011- - assign \out_sel 2'01 - end - sync init - end - process $group_14 - assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'010011 - assign \cr_in \dec19_cr_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'011110 - assign \cr_in \dec30_cr_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'011111 - assign \cr_in \dec31_cr_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'111010 - assign \cr_in \dec58_cr_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'111110 - assign \cr_in \dec62_cr_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'001100 - assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'001101 - assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'001110 - assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'001111 - assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'010001 - assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'011100 - assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'011101 - assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'010010 - assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'010000 - assign \cr_in 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'001011 - assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'001010 - assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'100010 - assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'100011 - assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'101010 - assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'101011 - assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'101000 - assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'101001 - assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'100000 - assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'100001 - assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'000111 - assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'011000 - assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'011001 - assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'010100 - assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'010101 - assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'010111 - assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'100110 - assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'100111 - assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'101100 - assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'101101 - assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'100100 - assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'100101 - assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'001000 - assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'000010 - assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'000011 - assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'011010 - assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'011011 - assign \cr_in 3'000 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 32'000000---------------0100000000- - assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 32'01100000000000000000000000000000 - assign \cr_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 32'000001---------------0000000011- - assign \cr_in 3'000 - end - sync init - end - process $group_15 - assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'010011 - assign \cr_out \dec19_cr_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'011110 - assign \cr_out \dec30_cr_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'011111 - assign \cr_out \dec31_cr_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'111010 - assign \cr_out \dec58_cr_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'111110 - assign \cr_out \dec62_cr_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'001100 - assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'001101 - assign \cr_out 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'001110 - assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'001111 - assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'010001 - assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'011100 - assign \cr_out 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'011101 - assign \cr_out 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'010010 - assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'010000 - assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'001011 - assign \cr_out 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'001010 - assign \cr_out 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'100010 - assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'100011 - assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'101010 - assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'101011 - assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'101000 - assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'101001 - assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'100000 - assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'100001 - assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'000111 - assign \cr_out 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'011000 - assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'011001 - assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'010100 - assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'010101 - assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'010111 - assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'100110 - assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'100111 - assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'101100 - assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'101101 - assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'100100 - assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'100101 - assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'001000 - assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'000010 - assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'000011 - assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'011010 - assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'011011 - assign \cr_out 3'000 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 32'000000---------------0100000000- - assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 32'01100000000000000000000000000000 - assign \cr_out 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 32'000001---------------0000000011- - assign \cr_out 3'000 - end - sync init - end - attribute \enum_base_type "LdstLen" - attribute \enum_value_0000 "NONE" - attribute \enum_value_0001 "is1B" - attribute \enum_value_0010 "is2B" - attribute \enum_value_0100 "is4B" - attribute \enum_value_1000 "is8B" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 4 \ldst_len - process $group_16 - assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'010011 - assign \ldst_len \dec19_ldst_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'011110 - assign \ldst_len \dec30_ldst_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'011111 - assign \ldst_len \dec31_ldst_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'111010 - assign \ldst_len \dec58_ldst_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'111110 - assign \ldst_len \dec62_ldst_len - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'001100 - assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'001101 - assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'001110 - assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'001111 - assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'010001 - assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'011100 - assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'011101 - assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'010010 - assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'010000 - assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'001011 - assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'001010 - assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'100010 - assign \ldst_len 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'100011 - assign \ldst_len 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'101010 - assign \ldst_len 4'0010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'101011 - assign \ldst_len 4'0010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'101000 - assign \ldst_len 4'0010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'101001 - assign \ldst_len 4'0010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'100000 - assign \ldst_len 4'0100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'100001 - assign \ldst_len 4'0100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'000111 - assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'011000 - assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'011001 - assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'010100 - assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'010101 - assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'010111 - assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'100110 - assign \ldst_len 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'100111 - assign \ldst_len 4'0001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'101100 - assign \ldst_len 4'0010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'101101 - assign \ldst_len 4'0010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'100100 - assign \ldst_len 4'0100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'100101 - assign \ldst_len 4'0100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'001000 - assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'000010 - assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'000011 - assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'011010 - assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'011011 - assign \ldst_len 4'0000 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 32'000000---------------0100000000- - assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 32'01100000000000000000000000000000 - assign \ldst_len 4'0000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 32'000001---------------0000000011- - assign \ldst_len 4'0000 - end - sync init - end - process $group_17 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'010011 - assign \upd \dec19_upd - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'011110 - assign \upd \dec30_upd - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'011111 - assign \upd \dec31_upd - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'111010 - assign \upd \dec58_upd - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'111110 - assign \upd \dec62_upd - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'001100 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'001101 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'001110 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'001111 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'010001 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'011100 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'011101 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'010010 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'010000 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'001011 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'001010 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'100010 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'100011 - assign \upd 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'101010 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'101011 - assign \upd 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'101000 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'101001 - assign \upd 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'100000 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'100001 - assign \upd 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'000111 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'011000 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'011001 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'010100 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'010101 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'010111 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'100110 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'100111 - assign \upd 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'101100 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'101101 - assign \upd 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'100100 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'100101 - assign \upd 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'001000 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'000010 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'000011 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'011010 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'011011 - assign \upd 2'00 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 32'000000---------------0100000000- - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 32'01100000000000000000000000000000 - assign \upd 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 32'000001---------------0000000011- - assign \upd 2'00 - end - sync init - end - process $group_18 - assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'010011 - assign \rc_sel \dec19_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'011110 - assign \rc_sel \dec30_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'011111 - assign \rc_sel \dec31_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'111010 - assign \rc_sel \dec58_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'111110 - assign \rc_sel \dec62_rc_sel - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'001100 - assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'001101 - assign \rc_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'001110 - assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'001111 - assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'010001 - assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'011100 - assign \rc_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'011101 - assign \rc_sel 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'010010 - assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'010000 - assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'001011 - assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'001010 - assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'100010 - assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'100011 - assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'101010 - assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'101011 - assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'101000 - assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'101001 - assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'100000 - assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'100001 - assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'000111 - assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'011000 - assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'011001 - assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'010100 - assign \rc_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'010101 - assign \rc_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'010111 - assign \rc_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'100110 - assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'100111 - assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'101100 - assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'101101 - assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'100100 - assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'100101 - assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'001000 - assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'000010 - assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'000011 - assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'011010 - assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'011011 - assign \rc_sel 2'00 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 32'000000---------------0100000000- - assign \rc_sel 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 32'01100000000000000000000000000000 - assign \rc_sel 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 32'000001---------------0000000011- - assign \rc_sel 2'00 - end - sync init - end - process $group_19 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'010011 - assign \cry_in \dec19_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'011110 - assign \cry_in \dec30_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'011111 - assign \cry_in \dec31_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'111010 - assign \cry_in \dec58_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'111110 - assign \cry_in \dec62_cry_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'001100 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'001101 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'001110 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'001111 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'010001 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'011100 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'011101 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'010010 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'010000 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'001011 - assign \cry_in 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'001010 - assign \cry_in 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'100010 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'100011 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'101010 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'101011 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'101000 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'101001 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'100000 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'100001 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'000111 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'011000 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'011001 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'010100 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'010101 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'010111 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'100110 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'100111 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'101100 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'101101 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'100100 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'100101 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'001000 - assign \cry_in 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'000010 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'000011 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'011010 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'011011 - assign \cry_in 2'00 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 32'000000---------------0100000000- - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 32'01100000000000000000000000000000 - assign \cry_in 2'00 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 32'000001---------------0000000011- - assign \cry_in 2'00 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \inv_a - process $group_20 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'010011 - assign \inv_a \dec19_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'011110 - assign \inv_a \dec30_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'011111 - assign \inv_a \dec31_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'111010 - assign \inv_a \dec58_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'111110 - assign \inv_a \dec62_inv_a - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'001100 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'001101 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'001110 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'001111 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'010001 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'011100 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'011101 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'010010 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'010000 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'001011 - assign \inv_a 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'001010 - assign \inv_a 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'100010 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'100011 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'101010 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'101011 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'101000 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'101001 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'100000 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'100001 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'000111 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'011000 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'011001 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'010100 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'010101 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'010111 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'100110 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'100111 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'101100 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'101101 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'100100 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'100101 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'001000 - assign \inv_a 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'000010 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'000011 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'011010 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'011011 - assign \inv_a 1'0 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 32'000000---------------0100000000- - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 32'01100000000000000000000000000000 - assign \inv_a 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 32'000001---------------0000000011- - assign \inv_a 1'0 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \inv_out - process $group_21 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'010011 - assign \inv_out \dec19_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'011110 - assign \inv_out \dec30_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'011111 - assign \inv_out \dec31_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'111010 - assign \inv_out \dec58_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'111110 - assign \inv_out \dec62_inv_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'001100 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'001101 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'001110 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'001111 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'010001 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'011100 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'011101 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'010010 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'010000 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'001011 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'001010 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'100010 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'100011 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'101010 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'101011 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'101000 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'101001 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'100000 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'100001 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'000111 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'011000 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'011001 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'010100 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'010101 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'010111 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'100110 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'100111 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'101100 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'101101 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'100100 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'100101 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'001000 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'000010 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'000011 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'011010 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'011011 - assign \inv_out 1'0 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 32'000000---------------0100000000- - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 32'01100000000000000000000000000000 - assign \inv_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 32'000001---------------0000000011- - assign \inv_out 1'0 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \cry_out - process $group_22 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'010011 - assign \cry_out \dec19_cry_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'011110 - assign \cry_out \dec30_cry_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'011111 - assign \cry_out \dec31_cry_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'111010 - assign \cry_out \dec58_cry_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'111110 - assign \cry_out \dec62_cry_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'001100 - assign \cry_out 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'001101 - assign \cry_out 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'001110 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'001111 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'010001 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'011100 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'011101 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'010010 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'010000 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'001011 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'001010 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'100010 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'100011 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'101010 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'101011 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'101000 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'101001 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'100000 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'100001 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'000111 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'011000 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'011001 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'010100 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'010101 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'010111 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'100110 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'100111 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'101100 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'101101 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'100100 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'100101 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'001000 - assign \cry_out 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'000010 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'000011 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'011010 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'011011 - assign \cry_out 1'0 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 32'000000---------------0100000000- - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 32'01100000000000000000000000000000 - assign \cry_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 32'000001---------------0000000011- - assign \cry_out 1'0 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \br - process $group_23 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'010011 - assign \br \dec19_br - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'011110 - assign \br \dec30_br - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'011111 - assign \br \dec31_br - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'111010 - assign \br \dec58_br - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'111110 - assign \br \dec62_br - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'001100 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'001101 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'001110 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'001111 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'010001 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'011100 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'011101 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'010010 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'010000 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'001011 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'001010 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'100010 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'100011 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'101010 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'101011 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'101000 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'101001 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'100000 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'100001 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'000111 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'011000 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'011001 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'010100 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'010101 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'010111 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'100110 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'100111 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'101100 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'101101 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'100100 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'100101 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'001000 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'000010 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'000011 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'011010 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'011011 - assign \br 1'0 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 32'000000---------------0100000000- - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 32'01100000000000000000000000000000 - assign \br 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 32'000001---------------0000000011- - assign \br 1'0 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \sgn_ext - process $group_24 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'010011 - assign \sgn_ext \dec19_sgn_ext - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'011110 - assign \sgn_ext \dec30_sgn_ext - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'011111 - assign \sgn_ext \dec31_sgn_ext - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'111010 - assign \sgn_ext \dec58_sgn_ext - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'111110 - assign \sgn_ext \dec62_sgn_ext - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'001100 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'001101 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'001110 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'001111 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'010001 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'011100 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'011101 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'010010 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'010000 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'001011 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'001010 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'100010 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'100011 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'101010 - assign \sgn_ext 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'101011 - assign \sgn_ext 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'101000 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'101001 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'100000 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'100001 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'000111 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'011000 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'011001 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'010100 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'010101 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'010111 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'100110 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'100111 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'101100 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'101101 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'100100 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'100101 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'001000 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'000010 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'000011 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'011010 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'011011 - assign \sgn_ext 1'0 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 32'000000---------------0100000000- - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 32'01100000000000000000000000000000 - assign \sgn_ext 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 32'000001---------------0000000011- - assign \sgn_ext 1'0 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \rsrv - process $group_25 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'010011 - assign \rsrv \dec19_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'011110 - assign \rsrv \dec30_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'011111 - assign \rsrv \dec31_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'111010 - assign \rsrv \dec58_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'111110 - assign \rsrv \dec62_rsrv - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'001100 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'001101 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'001110 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'001111 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'010001 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'011100 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'011101 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'010010 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'010000 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'001011 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'001010 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'100010 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'100011 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'101010 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'101011 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'101000 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'101001 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'100000 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'100001 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'000111 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'011000 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'011001 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'010100 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'010101 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'010111 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'100110 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'100111 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'101100 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'101101 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'100100 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'100101 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'001000 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'000010 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'000011 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'011010 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'011011 - assign \rsrv 1'0 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 32'000000---------------0100000000- - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 32'01100000000000000000000000000000 - assign \rsrv 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 32'000001---------------0000000011- - assign \rsrv 1'0 - end - sync init - end - process $group_26 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'010011 - assign \is_32b \dec19_is_32b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'011110 - assign \is_32b \dec30_is_32b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'011111 - assign \is_32b \dec31_is_32b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'111010 - assign \is_32b \dec58_is_32b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'111110 - assign \is_32b \dec62_is_32b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'001100 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'001101 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'001110 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'001111 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'010001 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'011100 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'011101 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'010010 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'010000 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'001011 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'001010 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'100010 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'100011 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'101010 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'101011 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'101000 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'101001 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'100000 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'100001 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'000111 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'011000 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'011001 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'010100 - assign \is_32b 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'010101 - assign \is_32b 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'010111 - assign \is_32b 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'100110 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'100111 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'101100 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'101101 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'100100 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'100101 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'001000 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'000010 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'000011 - assign \is_32b 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'011010 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'011011 - assign \is_32b 1'0 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 32'000000---------------0100000000- - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 32'01100000000000000000000000000000 - assign \is_32b 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 32'000001---------------0000000011- - assign \is_32b 1'0 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \sgn - process $group_27 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'010011 - assign \sgn \dec19_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'011110 - assign \sgn \dec30_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'011111 - assign \sgn \dec31_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'111010 - assign \sgn \dec58_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'111110 - assign \sgn \dec62_sgn - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'001100 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'001101 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'001110 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'001111 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'010001 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'011100 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'011101 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'010010 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'010000 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'001011 - assign \sgn 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'001010 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'100010 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'100011 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'101010 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'101011 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'101000 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'101001 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'100000 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'100001 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'000111 - assign \sgn 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'011000 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'011001 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'010100 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'010101 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'010111 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'100110 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'100111 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'101100 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'101101 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'100100 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'100101 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'001000 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'000010 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'000011 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'011010 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'011011 - assign \sgn 1'0 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 32'000000---------------0100000000- - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 32'01100000000000000000000000000000 - assign \sgn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 32'000001---------------0000000011- - assign \sgn 1'0 - end - sync init - end - process $group_28 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'010011 - assign \lk \dec19_lk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'011110 - assign \lk \dec30_lk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'011111 - assign \lk \dec31_lk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'111010 - assign \lk \dec58_lk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'111110 - assign \lk \dec62_lk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'001100 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'001101 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'001110 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'001111 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'010001 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'011100 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'011101 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'010010 - assign \lk 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'010000 - assign \lk 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'001011 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'001010 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'100010 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'100011 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'101010 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'101011 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'101000 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'101001 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'100000 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'100001 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'000111 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'011000 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'011001 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'010100 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'010101 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'010111 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'100110 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'100111 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'101100 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'101101 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'100100 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'100101 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'001000 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'000010 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'000011 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'011010 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'011011 - assign \lk 1'0 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 32'000000---------------0100000000- - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 32'01100000000000000000000000000000 - assign \lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 32'000001---------------0000000011- - assign \lk 1'0 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:182" - wire width 1 \sgl_pipe - process $group_29 - assign \sgl_pipe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'010011 - assign \sgl_pipe \dec19_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'011110 - assign \sgl_pipe \dec30_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'011111 - assign \sgl_pipe \dec31_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'111010 - assign \sgl_pipe \dec58_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:365" - case 6'111110 - assign \sgl_pipe \dec62_sgl_pipe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'001100 - assign \sgl_pipe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'001101 - assign \sgl_pipe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'001110 - assign \sgl_pipe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'001111 - assign \sgl_pipe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'010001 - assign \sgl_pipe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'011100 - assign \sgl_pipe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'011101 - assign \sgl_pipe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'010010 - assign \sgl_pipe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'010000 - assign \sgl_pipe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'001011 - assign \sgl_pipe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'001010 - assign \sgl_pipe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'100010 - assign \sgl_pipe 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'100011 - assign \sgl_pipe 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'101010 - assign \sgl_pipe 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'101011 - assign \sgl_pipe 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'101000 - assign \sgl_pipe 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'101001 - assign \sgl_pipe 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'100000 - assign \sgl_pipe 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'100001 - assign \sgl_pipe 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'000111 - assign \sgl_pipe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'011000 - assign \sgl_pipe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'011001 - assign \sgl_pipe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'010100 - assign \sgl_pipe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'010101 - assign \sgl_pipe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'010111 - assign \sgl_pipe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'100110 - assign \sgl_pipe 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'100111 - assign \sgl_pipe 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'101100 - assign \sgl_pipe 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'101101 - assign \sgl_pipe 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'100100 - assign \sgl_pipe 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'100101 - assign \sgl_pipe 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'001000 - assign \sgl_pipe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'000010 - assign \sgl_pipe 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'000011 - assign \sgl_pipe 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'011010 - assign \sgl_pipe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 6'011011 - assign \sgl_pipe 1'0 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:338" - switch \opcode_switch$1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 32'000000---------------0100000000- - assign \sgl_pipe 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 32'01100000000000000000000000000000 - assign \sgl_pipe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:350" - case 32'000001---------------0000000011- - assign \sgl_pipe 1'1 - end - sync init - end - process $group_30 - assign \opcode_switch$1 32'00000000000000000000000000000000 - assign \opcode_switch$1 \opcode_in - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:418" - wire width 32 $2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:418" - cell $mux $3 - parameter \WIDTH 32 - connect \A \raw_opcode_in - connect \B { \raw_opcode_in [7:0] \raw_opcode_in [15:8] \raw_opcode_in [23:16] \raw_opcode_in [31:24] } - connect \S \bigendian - connect \Y $2 - end - process $group_31 - assign \opcode_in 32'00000000000000000000000000000000 - assign \opcode_in $2 - sync init - end - process $group_32 - assign \RS 5'00000 - assign \RS { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - process $group_33 - assign \RT 5'00000 - assign \RT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - process $group_34 - assign \RA 5'00000 - assign \RA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - process $group_35 - assign \RB 5'00000 - assign \RB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 16 \SI - process $group_36 - assign \SI 16'0000000000000000 - assign \SI { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] \opcode_in [0] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 16 \UI - process $group_37 - assign \UI 16'0000000000000000 - assign \UI { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] \opcode_in [0] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 1 \L - process $group_38 - assign \L 1'0 - assign \L { \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 5 \SH32 - process $group_39 - assign \SH32 5'00000 - assign \SH32 { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 6 \sh - process $group_40 - assign \sh 6'000000 - assign \sh { \opcode_in [1] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 5 \MB32 - process $group_41 - assign \MB32 5'00000 - assign \MB32 { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 5 \ME32 - process $group_42 - assign \ME32 5'00000 - assign \ME32 { \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 24 \LI - process $group_43 - assign \LI 24'000000000000000000000000 - assign \LI { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] } - sync init - end - process $group_44 - assign \LK 1'0 - assign \LK { \opcode_in [0] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 1 \AA - process $group_45 - assign \AA 1'0 - assign \AA { \opcode_in [1] } - sync init - end - process $group_46 - assign \Rc 1'0 - assign \Rc { \opcode_in [0] } - sync init - end - process $group_47 - assign \OE 1'0 - assign \OE { \opcode_in [10] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 14 \BD - process $group_48 - assign \BD 14'00000000000000 - assign \BD { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 3 \BF - process $group_49 - assign \BF 3'000 - assign \BF { \opcode_in [25] \opcode_in [24] \opcode_in [23] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 10 \CR - process $group_50 - assign \CR 10'0000000000 - assign \CR { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] } - sync init - end - process $group_51 - assign \BB 5'00000 - assign \BB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - process $group_52 - assign \BA 5'00000 - assign \BA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - process $group_53 - assign \BT 5'00000 - assign \BT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - process $group_54 - assign \FXM 8'00000000 - assign \FXM { \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] } - sync init - end - process $group_55 - assign \BO 5'00000 - assign \BO { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - process $group_56 - assign \BI 5'00000 - assign \BI { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 2 \BH - process $group_57 - assign \BH 2'00 - assign \BH { \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 16 \D - process $group_58 - assign \D 16'0000000000000000 - assign \D { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] \opcode_in [0] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 14 \DS - process $group_59 - assign \DS 14'00000000000000 - assign \DS { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 5 \TO - process $group_60 - assign \TO 5'00000 - assign \TO { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - process $group_61 - assign \BC 5'00000 - assign \BC { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 5 \SH - process $group_62 - assign \SH 5'00000 - assign \SH { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 5 \ME - process $group_63 - assign \ME 5'00000 - assign \ME { \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 5 \MB - process $group_64 - assign \MB 5'00000 - assign \MB { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] } - sync init - end - process $group_65 - assign \SPR 10'0000000000 - assign \SPR { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \X_A - process $group_66 - assign \X_A 1'0 - assign \X_A { \opcode_in [25] } - sync init - end - process $group_67 - assign \X_BF 3'000 - assign \X_BF { \opcode_in [25] \opcode_in [24] \opcode_in [23] } - sync init - end - process $group_68 - assign \X_BFA 3'000 - assign \X_BFA { \opcode_in [20] \opcode_in [19] \opcode_in [18] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \X_BO - process $group_69 - assign \X_BO 5'00000 - assign \X_BO { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 4 \X_CT - process $group_70 - assign \X_CT 4'0000 - assign \X_CT { \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 7 \X_DCMX - process $group_71 - assign \X_DCMX 7'0000000 - assign \X_DCMX { \opcode_in [22] \opcode_in [21] \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 3 \X_DRM - process $group_72 - assign \X_DRM 3'000 - assign \X_DRM { \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \X_E - process $group_73 - assign \X_E 1'0 - assign \X_E { \opcode_in [15] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 4 \X_E_1 - process $group_74 - assign \X_E_1 4'0000 - assign \X_E_1 { \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 2 \X_EO - process $group_75 - assign \X_EO 2'00 - assign \X_EO { \opcode_in [20] \opcode_in [19] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \X_EO_1 - process $group_76 - assign \X_EO_1 5'00000 - assign \X_EO_1 { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \X_EX - process $group_77 - assign \X_EX 1'0 - assign \X_EX { \opcode_in [0] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \X_FC - process $group_78 - assign \X_FC 5'00000 - assign \X_FC { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \X_FRA - process $group_79 - assign \X_FRA 5'00000 - assign \X_FRA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \X_FRAp - process $group_80 - assign \X_FRAp 5'00000 - assign \X_FRAp { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \X_FRB - process $group_81 - assign \X_FRB 5'00000 - assign \X_FRB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \X_FRBp - process $group_82 - assign \X_FRBp 5'00000 - assign \X_FRBp { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \X_FRS - process $group_83 - assign \X_FRS 5'00000 - assign \X_FRS { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \X_FRSp - process $group_84 - assign \X_FRSp 5'00000 - assign \X_FRSp { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \X_FRT - process $group_85 - assign \X_FRT 5'00000 - assign \X_FRT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \X_FRTp - process $group_86 - assign \X_FRTp 5'00000 - assign \X_FRTp { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 3 \X_IH - process $group_87 - assign \X_IH 3'000 - assign \X_IH { \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 8 \X_IMM8 - process $group_88 - assign \X_IMM8 8'00000000 - assign \X_IMM8 { \opcode_in [18] \opcode_in [17] \opcode_in [16] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 2 \X_L2 - process $group_89 - assign \X_L2 2'00 - assign \X_L2 { \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \X_L - process $group_90 - assign \X_L 1'0 - assign \X_L { \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \X_L1 - process $group_91 - assign \X_L1 1'0 - assign \X_L1 { \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 2 \X_L3 - process $group_92 - assign \X_L3 2'00 - assign \X_L3 { \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \X_MO - process $group_93 - assign \X_MO 5'00000 - assign \X_MO { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \X_NB - process $group_94 - assign \X_NB 5'00000 - assign \X_NB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \X_PRS - process $group_95 - assign \X_PRS 1'0 - assign \X_PRS { \opcode_in [17] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \X_R - process $group_96 - assign \X_R 1'0 - assign \X_R { \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \X_R_1 - process $group_97 - assign \X_R_1 1'0 - assign \X_R_1 { \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \X_RA - process $group_98 - assign \X_RA 5'00000 - assign \X_RA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \X_RB - process $group_99 - assign \X_RB 5'00000 - assign \X_RB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \X_Rc - process $group_100 - assign \X_Rc 1'0 - assign \X_Rc { \opcode_in [0] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 2 \X_RIC - process $group_101 - assign \X_RIC 2'00 - assign \X_RIC { \opcode_in [19] \opcode_in [18] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 2 \X_RM - process $group_102 - assign \X_RM 2'00 - assign \X_RM { \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \X_RO - process $group_103 - assign \X_RO 1'0 - assign \X_RO { \opcode_in [0] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \X_RS - process $group_104 - assign \X_RS 5'00000 - assign \X_RS { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \X_RSp - process $group_105 - assign \X_RSp 5'00000 - assign \X_RSp { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \X_RT - process $group_106 - assign \X_RT 5'00000 - assign \X_RT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \X_RTp - process $group_107 - assign \X_RTp 5'00000 - assign \X_RTp { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \X_S - process $group_108 - assign \X_S 5'00000 - assign \X_S { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \X_SH - process $group_109 - assign \X_SH 5'00000 - assign \X_SH { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \X_SI - process $group_110 - assign \X_SI 5'00000 - assign \X_SI { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 2 \X_SP - process $group_111 - assign \X_SP 2'00 - assign \X_SP { \opcode_in [20] \opcode_in [19] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 4 \X_SR - process $group_112 - assign \X_SR 4'0000 - assign \X_SR { \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \X_SX - process $group_113 - assign \X_SX 1'0 - assign \X_SX { \opcode_in [0] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 6 \X_SX_S - process $group_114 - assign \X_SX_S 6'000000 - assign \X_SX_S { \opcode_in [0] \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \X_T - process $group_115 - assign \X_T 5'00000 - assign \X_T { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 10 \X_TBR - process $group_116 - assign \X_TBR 10'0000000000 - assign \X_TBR { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \X_TH - process $group_117 - assign \X_TH 5'00000 - assign \X_TH { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \X_TO - process $group_118 - assign \X_TO 5'00000 - assign \X_TO { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \X_TX - process $group_119 - assign \X_TX 1'0 - assign \X_TX { \opcode_in [0] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 6 \X_TX_T - process $group_120 - assign \X_TX_T 6'000000 - assign \X_TX_T { \opcode_in [0] \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 4 \X_U - process $group_121 - assign \X_U 4'0000 - assign \X_U { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \X_UIM - process $group_122 - assign \X_UIM 5'00000 - assign \X_UIM { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \X_VRS - process $group_123 - assign \X_VRS 5'00000 - assign \X_VRS { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \X_VRT - process $group_124 - assign \X_VRT 5'00000 - assign \X_VRT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \X_W - process $group_125 - assign \X_W 1'0 - assign \X_W { \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 2 \X_WC - process $group_126 - assign \X_WC 2'00 - assign \X_WC { \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 10 \X_XO - process $group_127 - assign \X_XO 10'0000000000 - assign \X_XO { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 8 \X_XO_1 - process $group_128 - assign \X_XO_1 8'00000000 - assign \X_XO_1 { \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \B_AA - process $group_129 - assign \B_AA 1'0 - assign \B_AA { \opcode_in [1] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 14 \B_BD - process $group_130 - assign \B_BD 14'00000000000000 - assign \B_BD { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \B_BI - process $group_131 - assign \B_BI 5'00000 - assign \B_BI { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \B_BO - process $group_132 - assign \B_BO 5'00000 - assign \B_BO { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \B_LK - process $group_133 - assign \B_LK 1'0 - assign \B_LK { \opcode_in [0] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \I_AA - process $group_134 - assign \I_AA 1'0 - assign \I_AA { \opcode_in [1] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 24 \I_LI - process $group_135 - assign \I_LI 24'000000000000000000000000 - assign \I_LI { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \I_LK - process $group_136 - assign \I_LK 1'0 - assign \I_LK { \opcode_in [0] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \XX3_AX - process $group_137 - assign \XX3_AX 1'0 - assign \XX3_AX { \opcode_in [2] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \XX3_A - process $group_138 - assign \XX3_A 5'00000 - assign \XX3_A { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 6 \XX3_AX_A - process $group_139 - assign \XX3_AX_A 6'000000 - assign \XX3_AX_A { \opcode_in [2] \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 3 \XX3_BF - process $group_140 - assign \XX3_BF 3'000 - assign \XX3_BF { \opcode_in [25] \opcode_in [24] \opcode_in [23] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \XX3_BX - process $group_141 - assign \XX3_BX 1'0 - assign \XX3_BX { \opcode_in [1] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \XX3_B - process $group_142 - assign \XX3_B 5'00000 - assign \XX3_B { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 6 \XX3_BX_B - process $group_143 - assign \XX3_BX_B 6'000000 - assign \XX3_BX_B { \opcode_in [1] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 2 \XX3_DM - process $group_144 - assign \XX3_DM 2'00 - assign \XX3_DM { \opcode_in [9] \opcode_in [8] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \XX3_Rc - process $group_145 - assign \XX3_Rc 1'0 - assign \XX3_Rc { \opcode_in [10] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 2 \XX3_SHW - process $group_146 - assign \XX3_SHW 2'00 - assign \XX3_SHW { \opcode_in [9] \opcode_in [8] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \XX3_TX - process $group_147 - assign \XX3_TX 1'0 - assign \XX3_TX { \opcode_in [0] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \XX3_T - process $group_148 - assign \XX3_T 5'00000 - assign \XX3_T { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 6 \XX3_TX_T - process $group_149 - assign \XX3_TX_T 6'000000 - assign \XX3_TX_T { \opcode_in [0] \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 4 \XX3_XO - process $group_150 - assign \XX3_XO 4'0000 - assign \XX3_XO { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 8 \XX3_XO_1 - process $group_151 - assign \XX3_XO_1 8'00000000 - assign \XX3_XO_1 { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 9 \XX3_XO_2 - process $group_152 - assign \XX3_XO_2 9'000000000 - assign \XX3_XO_2 { \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \XX4_AX - process $group_153 - assign \XX4_AX 1'0 - assign \XX4_AX { \opcode_in [2] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \XX4_A - process $group_154 - assign \XX4_A 5'00000 - assign \XX4_A { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 6 \XX4_AX_A - process $group_155 - assign \XX4_AX_A 6'000000 - assign \XX4_AX_A { \opcode_in [2] \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \XX4_BX - process $group_156 - assign \XX4_BX 1'0 - assign \XX4_BX { \opcode_in [1] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \XX4_B - process $group_157 - assign \XX4_B 5'00000 - assign \XX4_B { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 6 \XX4_BX_B - process $group_158 - assign \XX4_BX_B 6'000000 - assign \XX4_BX_B { \opcode_in [1] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \XX4_CX - process $group_159 - assign \XX4_CX 1'0 - assign \XX4_CX { \opcode_in [3] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \XX4_C - process $group_160 - assign \XX4_C 5'00000 - assign \XX4_C { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 6 \XX4_CX_C - process $group_161 - assign \XX4_CX_C 6'000000 - assign \XX4_CX_C { \opcode_in [3] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \XX4_TX - process $group_162 - assign \XX4_TX 1'0 - assign \XX4_TX { \opcode_in [0] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \XX4_T - process $group_163 - assign \XX4_T 5'00000 - assign \XX4_T { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 6 \XX4_TX_T - process $group_164 - assign \XX4_TX_T 6'000000 - assign \XX4_TX_T { \opcode_in [0] \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 2 \XX4_XO - process $group_165 - assign \XX4_XO 2'00 - assign \XX4_XO { \opcode_in [5] \opcode_in [4] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \XL_BA - process $group_166 - assign \XL_BA 5'00000 - assign \XL_BA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \XL_BB - process $group_167 - assign \XL_BB 5'00000 - assign \XL_BB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 3 \XL_BF - process $group_168 - assign \XL_BF 3'000 - assign \XL_BF { \opcode_in [25] \opcode_in [24] \opcode_in [23] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 3 \XL_BFA - process $group_169 - assign \XL_BFA 3'000 - assign \XL_BFA { \opcode_in [20] \opcode_in [19] \opcode_in [18] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 2 \XL_BH - process $group_170 - assign \XL_BH 2'00 - assign \XL_BH { \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \XL_BI - process $group_171 - assign \XL_BI 5'00000 - assign \XL_BI { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \XL_BO - process $group_172 - assign \XL_BO 5'00000 - assign \XL_BO { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \XL_BO_1 - process $group_173 - assign \XL_BO_1 5'00000 - assign \XL_BO_1 { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - process $group_174 - assign \XL_BT 5'00000 - assign \XL_BT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \XL_LK - process $group_175 - assign \XL_LK 1'0 - assign \XL_LK { \opcode_in [0] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 15 \XL_OC - process $group_176 - assign \XL_OC 15'000000000000000 - assign \XL_OC { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \XL_S - process $group_177 - assign \XL_S 1'0 - assign \XL_S { \opcode_in [11] } - sync init - end - process $group_178 - assign \XL_XO 10'0000000000 - assign \XL_XO { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \A_BC - process $group_179 - assign \A_BC 5'00000 - assign \A_BC { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \A_FRA - process $group_180 - assign \A_FRA 5'00000 - assign \A_FRA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \A_FRB - process $group_181 - assign \A_FRB 5'00000 - assign \A_FRB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \A_FRC - process $group_182 - assign \A_FRC 5'00000 - assign \A_FRC { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \A_FRT - process $group_183 - assign \A_FRT 5'00000 - assign \A_FRT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \A_RA - process $group_184 - assign \A_RA 5'00000 - assign \A_RA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \A_RB - process $group_185 - assign \A_RB 5'00000 - assign \A_RB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \A_Rc - process $group_186 - assign \A_Rc 1'0 - assign \A_Rc { \opcode_in [0] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \A_RT - process $group_187 - assign \A_RT 5'00000 - assign \A_RT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \A_XO - process $group_188 - assign \A_XO 5'00000 - assign \A_XO { \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 3 \D_BF - process $group_189 - assign \D_BF 3'000 - assign \D_BF { \opcode_in [25] \opcode_in [24] \opcode_in [23] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 16 \D_D - process $group_190 - assign \D_D 16'0000000000000000 - assign \D_D { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] \opcode_in [0] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \D_FRS - process $group_191 - assign \D_FRS 5'00000 - assign \D_FRS { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \D_FRT - process $group_192 - assign \D_FRT 5'00000 - assign \D_FRT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \D_L - process $group_193 - assign \D_L 1'0 - assign \D_L { \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \D_RA - process $group_194 - assign \D_RA 5'00000 - assign \D_RA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \D_RS - process $group_195 - assign \D_RS 5'00000 - assign \D_RS { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \D_RT - process $group_196 - assign \D_RT 5'00000 - assign \D_RT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 16 \D_SI - process $group_197 - assign \D_SI 16'0000000000000000 - assign \D_SI { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] \opcode_in [0] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \D_TO - process $group_198 - assign \D_TO 5'00000 - assign \D_TO { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 16 \D_UI - process $group_199 - assign \D_UI 16'0000000000000000 - assign \D_UI { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] \opcode_in [0] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 3 \XX2_BF - process $group_200 - assign \XX2_BF 3'000 - assign \XX2_BF { \opcode_in [25] \opcode_in [24] \opcode_in [23] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \XX2_BX - process $group_201 - assign \XX2_BX 1'0 - assign \XX2_BX { \opcode_in [1] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \XX2_B - process $group_202 - assign \XX2_B 5'00000 - assign \XX2_B { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 6 \XX2_BX_B - process $group_203 - assign \XX2_BX_B 6'000000 - assign \XX2_BX_B { \opcode_in [1] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \XX2_dc - process $group_204 - assign \XX2_dc 1'0 - assign \XX2_dc { \opcode_in [6] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \XX2_dm - process $group_205 - assign \XX2_dm 1'0 - assign \XX2_dm { \opcode_in [2] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \XX2_dx - process $group_206 - assign \XX2_dx 5'00000 - assign \XX2_dx { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 7 \XX2_dc_dm_dx - process $group_207 - assign \XX2_dc_dm_dx 7'0000000 - assign \XX2_dc_dm_dx { \opcode_in [6] \opcode_in [2] \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 7 \XX2_DCMX - process $group_208 - assign \XX2_DCMX 7'0000000 - assign \XX2_DCMX { \opcode_in [22] \opcode_in [21] \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \XX2_EO - process $group_209 - assign \XX2_EO 5'00000 - assign \XX2_EO { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \XX2_RT - process $group_210 - assign \XX2_RT 5'00000 - assign \XX2_RT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \XX2_TX - process $group_211 - assign \XX2_TX 1'0 - assign \XX2_TX { \opcode_in [0] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \XX2_T - process $group_212 - assign \XX2_T 5'00000 - assign \XX2_T { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 6 \XX2_TX_T - process $group_213 - assign \XX2_TX_T 6'000000 - assign \XX2_TX_T { \opcode_in [0] \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 4 \XX2_UIM - process $group_214 - assign \XX2_UIM 4'0000 - assign \XX2_UIM { \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 2 \XX2_UIM_1 - process $group_215 - assign \XX2_UIM_1 2'00 - assign \XX2_UIM_1 { \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 7 \XX2_XO - process $group_216 - assign \XX2_XO 7'0000000 - assign \XX2_XO { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [5] \opcode_in [4] \opcode_in [3] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 9 \XX2_XO_1 - process $group_217 - assign \XX2_XO_1 9'000000000 - assign \XX2_XO_1 { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 3 \Z22_BF - process $group_218 - assign \Z22_BF 3'000 - assign \Z22_BF { \opcode_in [25] \opcode_in [24] \opcode_in [23] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 6 \Z22_DCM - process $group_219 - assign \Z22_DCM 6'000000 - assign \Z22_DCM { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 6 \Z22_DGM - process $group_220 - assign \Z22_DGM 6'000000 - assign \Z22_DGM { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \Z22_FRA - process $group_221 - assign \Z22_FRA 5'00000 - assign \Z22_FRA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \Z22_FRAp - process $group_222 - assign \Z22_FRAp 5'00000 - assign \Z22_FRAp { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \Z22_FRT - process $group_223 - assign \Z22_FRT 5'00000 - assign \Z22_FRT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \Z22_FRTp - process $group_224 - assign \Z22_FRTp 5'00000 - assign \Z22_FRTp { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \Z22_Rc - process $group_225 - assign \Z22_Rc 1'0 - assign \Z22_Rc { \opcode_in [0] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 6 \Z22_SH - process $group_226 - assign \Z22_SH 6'000000 - assign \Z22_SH { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 9 \Z22_XO - process $group_227 - assign \Z22_XO 9'000000000 - assign \Z22_XO { \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 3 \EVS_BFA - process $group_228 - assign \EVS_BFA 3'000 - assign \EVS_BFA { \opcode_in [2] \opcode_in [1] \opcode_in [0] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 10 \XFX_BHRBE - process $group_229 - assign \XFX_BHRBE 10'0000000000 - assign \XFX_BHRBE { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \XFX_DUI - process $group_230 - assign \XFX_DUI 5'00000 - assign \XFX_DUI { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 10 \XFX_DUIS - process $group_231 - assign \XFX_DUIS 10'0000000000 - assign \XFX_DUIS { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 8 \XFX_FXM - process $group_232 - assign \XFX_FXM 8'00000000 - assign \XFX_FXM { \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \XFX_RS - process $group_233 - assign \XFX_RS 5'00000 - assign \XFX_RS { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \XFX_RT - process $group_234 - assign \XFX_RT 5'00000 - assign \XFX_RT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 10 \XFX_SPR - process $group_235 - assign \XFX_SPR 10'0000000000 - assign \XFX_SPR { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 10 \XFX_XO - process $group_236 - assign \XFX_XO 10'0000000000 - assign \XFX_XO { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 10 \DX_d0 - process $group_237 - assign \DX_d0 10'0000000000 - assign \DX_d0 { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \DX_d1 - process $group_238 - assign \DX_d1 5'00000 - assign \DX_d1 { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \DX_d2 - process $group_239 - assign \DX_d2 1'0 - assign \DX_d2 { \opcode_in [0] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 16 \DX_d0_d1_d2 - process $group_240 - assign \DX_d0_d1_d2 16'0000000000000000 - assign \DX_d0_d1_d2 { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] \opcode_in [0] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \DX_RT - process $group_241 - assign \DX_RT 5'00000 - assign \DX_RT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \DX_XO - process $group_242 - assign \DX_XO 5'00000 - assign \DX_XO { \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 12 \DQ_DQ - process $group_243 - assign \DQ_DQ 12'000000000000 - assign \DQ_DQ { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 4 \DQ_PT - process $group_244 - assign \DQ_PT 4'0000 - assign \DQ_PT { \opcode_in [3] \opcode_in [2] \opcode_in [1] \opcode_in [0] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \DQ_RA - process $group_245 - assign \DQ_RA 5'00000 - assign \DQ_RA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \DQ_RTp - process $group_246 - assign \DQ_RTp 5'00000 - assign \DQ_RTp { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \DQ_SX - process $group_247 - assign \DQ_SX 1'0 - assign \DQ_SX { \opcode_in [3] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \DQ_S - process $group_248 - assign \DQ_S 5'00000 - assign \DQ_S { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 6 \DQ_SX_S - process $group_249 - assign \DQ_SX_S 6'000000 - assign \DQ_SX_S { \opcode_in [3] \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \DQ_TX - process $group_250 - assign \DQ_TX 1'0 - assign \DQ_TX { \opcode_in [3] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \DQ_T - process $group_251 - assign \DQ_T 5'00000 - assign \DQ_T { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 6 \DQ_TX_T - process $group_252 - assign \DQ_TX_T 6'000000 - assign \DQ_TX_T { \opcode_in [3] \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 3 \DQ_XO - process $group_253 - assign \DQ_XO 3'000 - assign \DQ_XO { \opcode_in [2] \opcode_in [1] \opcode_in [0] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 14 \DS_DS - process $group_254 - assign \DS_DS 14'00000000000000 - assign \DS_DS { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \DS_FRSp - process $group_255 - assign \DS_FRSp 5'00000 - assign \DS_FRSp { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \DS_FRTp - process $group_256 - assign \DS_FRTp 5'00000 - assign \DS_FRTp { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \DS_RA - process $group_257 - assign \DS_RA 5'00000 - assign \DS_RA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \DS_RS - process $group_258 - assign \DS_RS 5'00000 - assign \DS_RS { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \DS_RSp - process $group_259 - assign \DS_RSp 5'00000 - assign \DS_RSp { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \DS_RT - process $group_260 - assign \DS_RT 5'00000 - assign \DS_RT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \DS_VRS - process $group_261 - assign \DS_VRS 5'00000 - assign \DS_VRS { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \DS_VRT - process $group_262 - assign \DS_VRT 5'00000 - assign \DS_VRT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 2 \DS_XO - process $group_263 - assign \DS_XO 2'00 - assign \DS_XO { \opcode_in [1] \opcode_in [0] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \VX_EO - process $group_264 - assign \VX_EO 5'00000 - assign \VX_EO { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \VX_PS - process $group_265 - assign \VX_PS 1'0 - assign \VX_PS { \opcode_in [9] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \VX_RA - process $group_266 - assign \VX_RA 5'00000 - assign \VX_RA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \VX_RT - process $group_267 - assign \VX_RT 5'00000 - assign \VX_RT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \VX_SIM - process $group_268 - assign \VX_SIM 5'00000 - assign \VX_SIM { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \VX_UIM - process $group_269 - assign \VX_UIM 5'00000 - assign \VX_UIM { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 4 \VX_UIM_1 - process $group_270 - assign \VX_UIM_1 4'0000 - assign \VX_UIM_1 { \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 3 \VX_UIM_2 - process $group_271 - assign \VX_UIM_2 3'000 - assign \VX_UIM_2 { \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 2 \VX_UIM_3 - process $group_272 - assign \VX_UIM_3 2'00 - assign \VX_UIM_3 { \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \VX_VRA - process $group_273 - assign \VX_VRA 5'00000 - assign \VX_VRA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \VX_VRB - process $group_274 - assign \VX_VRB 5'00000 - assign \VX_VRB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \VX_VRT - process $group_275 - assign \VX_VRT 5'00000 - assign \VX_VRT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 10 \VX_XO - process $group_276 - assign \VX_XO 10'0000000000 - assign \VX_XO { \opcode_in [10] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] \opcode_in [0] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 11 \VX_XO_1 - process $group_277 - assign \VX_XO_1 11'00000000000 - assign \VX_XO_1 { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] \opcode_in [0] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 8 \XFL_FLM - process $group_278 - assign \XFL_FLM 8'00000000 - assign \XFL_FLM { \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \XFL_FRB - process $group_279 - assign \XFL_FRB 5'00000 - assign \XFL_FRB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \XFL_L - process $group_280 - assign \XFL_L 1'0 - assign \XFL_L { \opcode_in [25] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \XFL_Rc - process $group_281 - assign \XFL_Rc 1'0 - assign \XFL_Rc { \opcode_in [0] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \XFL_W - process $group_282 - assign \XFL_W 1'0 - assign \XFL_W { \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 10 \XFL_XO - process $group_283 - assign \XFL_XO 10'0000000000 - assign \XFL_XO { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \Z23_FRA - process $group_284 - assign \Z23_FRA 5'00000 - assign \Z23_FRA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \Z23_FRAp - process $group_285 - assign \Z23_FRAp 5'00000 - assign \Z23_FRAp { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \Z23_FRB - process $group_286 - assign \Z23_FRB 5'00000 - assign \Z23_FRB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \Z23_FRBp - process $group_287 - assign \Z23_FRBp 5'00000 - assign \Z23_FRBp { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \Z23_FRT - process $group_288 - assign \Z23_FRT 5'00000 - assign \Z23_FRT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \Z23_FRTp - process $group_289 - assign \Z23_FRTp 5'00000 - assign \Z23_FRTp { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \Z23_R - process $group_290 - assign \Z23_R 1'0 - assign \Z23_R { \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \Z23_Rc - process $group_291 - assign \Z23_Rc 1'0 - assign \Z23_Rc { \opcode_in [0] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 2 \Z23_RMC - process $group_292 - assign \Z23_RMC 2'00 - assign \Z23_RMC { \opcode_in [10] \opcode_in [9] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \Z23_TE - process $group_293 - assign \Z23_TE 5'00000 - assign \Z23_TE { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 8 \Z23_XO - process $group_294 - assign \Z23_XO 8'00000000 - assign \Z23_XO { \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \MDS_IB - process $group_295 - assign \MDS_IB 5'00000 - assign \MDS_IB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \MDS_IS - process $group_296 - assign \MDS_IS 5'00000 - assign \MDS_IS { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 6 \MDS_mb - process $group_297 - assign \MDS_mb 6'000000 - assign \MDS_mb { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 6 \MDS_me - process $group_298 - assign \MDS_me 6'000000 - assign \MDS_me { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \MDS_RA - process $group_299 - assign \MDS_RA 5'00000 - assign \MDS_RA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \MDS_RB - process $group_300 - assign \MDS_RB 5'00000 - assign \MDS_RB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \MDS_Rc - process $group_301 - assign \MDS_Rc 1'0 - assign \MDS_Rc { \opcode_in [0] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \MDS_RS - process $group_302 - assign \MDS_RS 5'00000 - assign \MDS_RS { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 4 \MDS_XBI - process $group_303 - assign \MDS_XBI 4'0000 - assign \MDS_XBI { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 4 \MDS_XBI_1 - process $group_304 - assign \MDS_XBI_1 4'0000 - assign \MDS_XBI_1 { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 4 \MDS_XO - process $group_305 - assign \MDS_XO 4'0000 - assign \MDS_XO { \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 7 \SC_LEV - process $group_306 - assign \SC_LEV 7'0000000 - assign \SC_LEV { \opcode_in [11] \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \SC_XO - process $group_307 - assign \SC_XO 1'0 - assign \SC_XO { \opcode_in [1] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 2 \SC_XO_1 - process $group_308 - assign \SC_XO_1 2'00 - assign \SC_XO_1 { \opcode_in [1] \opcode_in [0] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \M_MB - process $group_309 - assign \M_MB 5'00000 - assign \M_MB { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \M_ME - process $group_310 - assign \M_ME 5'00000 - assign \M_ME { \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \M_RA - process $group_311 - assign \M_RA 5'00000 - assign \M_RA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \M_RB - process $group_312 - assign \M_RB 5'00000 - assign \M_RB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \M_Rc - process $group_313 - assign \M_Rc 1'0 - assign \M_Rc { \opcode_in [0] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \M_RS - process $group_314 - assign \M_RS 5'00000 - assign \M_RS { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \M_SH - process $group_315 - assign \M_SH 5'00000 - assign \M_SH { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 6 \MD_mb - process $group_316 - assign \MD_mb 6'000000 - assign \MD_mb { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 6 \MD_me - process $group_317 - assign \MD_me 6'000000 - assign \MD_me { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \MD_RA - process $group_318 - assign \MD_RA 5'00000 - assign \MD_RA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \MD_Rc - process $group_319 - assign \MD_Rc 1'0 - assign \MD_Rc { \opcode_in [0] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \MD_RS - process $group_320 - assign \MD_RS 5'00000 - assign \MD_RS { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 6 \MD_sh - process $group_321 - assign \MD_sh 6'000000 - assign \MD_sh { \opcode_in [1] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 3 \MD_XO - process $group_322 - assign \MD_XO 3'000 - assign \MD_XO { \opcode_in [4] \opcode_in [3] \opcode_in [2] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 6 \all_OPCD - process $group_323 - assign \all_OPCD 6'000000 - assign \all_OPCD { \opcode_in [31] \opcode_in [30] \opcode_in [29] \opcode_in [28] \opcode_in [27] \opcode_in [26] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 6 \all_PO - process $group_324 - assign \all_PO 6'000000 - assign \all_PO { \opcode_in [31] \opcode_in [30] \opcode_in [29] \opcode_in [28] \opcode_in [27] \opcode_in [26] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \XO_OE - process $group_325 - assign \XO_OE 1'0 - assign \XO_OE { \opcode_in [10] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \XO_RA - process $group_326 - assign \XO_RA 5'00000 - assign \XO_RA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \XO_RB - process $group_327 - assign \XO_RB 5'00000 - assign \XO_RB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \XO_Rc - process $group_328 - assign \XO_Rc 1'0 - assign \XO_Rc { \opcode_in [0] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \XO_RT - process $group_329 - assign \XO_RT 5'00000 - assign \XO_RT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 9 \XO_XO - process $group_330 - assign \XO_XO 9'000000000 - assign \XO_XO { \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \DQE_RA - process $group_331 - assign \DQE_RA 5'00000 - assign \DQE_RA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \DQE_RT - process $group_332 - assign \DQE_RT 5'00000 - assign \DQE_RT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 2 \DQE_XO - process $group_333 - assign \DQE_XO 2'00 - assign \DQE_XO { \opcode_in [1] \opcode_in [0] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \TX_RA - process $group_334 - assign \TX_RA 5'00000 - assign \TX_RA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \TX_UI - process $group_335 - assign \TX_UI 5'00000 - assign \TX_UI { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 4 \TX_XBI - process $group_336 - assign \TX_XBI 4'0000 - assign \TX_XBI { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 6 \TX_XO - process $group_337 - assign \TX_XO 6'000000 - assign \TX_XO { \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \VA_RA - process $group_338 - assign \VA_RA 5'00000 - assign \VA_RA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \VA_RB - process $group_339 - assign \VA_RB 5'00000 - assign \VA_RB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \VA_RC - process $group_340 - assign \VA_RC 5'00000 - assign \VA_RC { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \VA_RT - process $group_341 - assign \VA_RT 5'00000 - assign \VA_RT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 4 \VA_SHB - process $group_342 - assign \VA_SHB 4'0000 - assign \VA_SHB { \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \VA_VRA - process $group_343 - assign \VA_VRA 5'00000 - assign \VA_VRA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \VA_VRB - process $group_344 - assign \VA_VRB 5'00000 - assign \VA_VRB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \VA_VRC - process $group_345 - assign \VA_VRC 5'00000 - assign \VA_VRC { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \VA_VRT - process $group_346 - assign \VA_VRT 5'00000 - assign \VA_VRT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 6 \VA_XO - process $group_347 - assign \VA_XO 6'000000 - assign \VA_XO { \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] \opcode_in [0] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \XS_RA - process $group_348 - assign \XS_RA 5'00000 - assign \XS_RA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \XS_Rc - process $group_349 - assign \XS_Rc 1'0 - assign \XS_Rc { \opcode_in [0] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \XS_RS - process $group_350 - assign \XS_RS 5'00000 - assign \XS_RS { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 6 \XS_sh - process $group_351 - assign \XS_sh 6'000000 - assign \XS_sh { \opcode_in [1] \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 9 \XS_XO - process $group_352 - assign \XS_XO 9'000000000 - assign \XS_XO { \opcode_in [10] \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 1 \VC_Rc - process $group_353 - assign \VC_Rc 1'0 - assign \VC_Rc { \opcode_in [10] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \VC_VRA - process $group_354 - assign \VC_VRA 5'00000 - assign \VC_VRA { \opcode_in [20] \opcode_in [19] \opcode_in [18] \opcode_in [17] \opcode_in [16] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \VC_VRB - process $group_355 - assign \VC_VRB 5'00000 - assign \VC_VRB { \opcode_in [15] \opcode_in [14] \opcode_in [13] \opcode_in [12] \opcode_in [11] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 \VC_VRT - process $group_356 - assign \VC_VRT 5'00000 - assign \VC_VRT { \opcode_in [25] \opcode_in [24] \opcode_in [23] \opcode_in [22] \opcode_in [21] } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 10 \VC_XO - process $group_357 - assign \VC_XO 10'0000000000 - assign \VC_XO { \opcode_in [9] \opcode_in [8] \opcode_in [7] \opcode_in [6] \opcode_in [5] \opcode_in [4] \opcode_in [3] \opcode_in [2] \opcode_in [1] \opcode_in [0] } - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.dec2.dec_rc" -module \dec_rc$203 - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:404" - wire width 2 input 0 \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 1 \rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 2 \rc_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 1 input 3 \Rc - process $group_0 - assign \rc 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:413" - switch \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:414" - attribute \nmigen.decoding "RC/2" - case 2'10 - assign \rc \Rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:417" - attribute \nmigen.decoding "ONE/1" - case 2'01 - assign \rc 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:420" - attribute \nmigen.decoding "NONE/0" - case 2'00 - assign \rc 1'0 - end - sync init - end - process $group_1 - assign \rc_ok 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:413" - switch \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:414" - attribute \nmigen.decoding "RC/2" - case 2'10 - assign \rc_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:417" - attribute \nmigen.decoding "ONE/1" - case 2'01 - assign \rc_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:420" - attribute \nmigen.decoding "NONE/0" - case 2'00 - assign \rc_ok 1'1 - end - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.dec2.dec_oe" -module \dec_oe$204 - attribute \enum_base_type "RC" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:441" - wire width 2 input 0 \sel_in - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 7 input 1 \internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 2 \oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 3 \oe_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 1 input 4 \OE - process $group_0 - assign \oe 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:450" - switch \internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:461" - attribute \nmigen.decoding "OP_MUL_H64/51|OP_MUL_H32/52|OP_EXTS/31|OP_CNTZ/14|OP_SHL/60|OP_SHR/61|OP_RLC/56|OP_LOAD/37|OP_STORE/38|OP_RLCL/57|OP_RLCR/58|OP_EXTSWSLI/32" - case 7'0110011, 7'0110100, 7'0011111, 7'0001110, 7'0111100, 7'0111101, 7'0111000, 7'0100101, 7'0100110, 7'0111001, 7'0111010, 7'0100000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:465" - attribute \nmigen.decoding "" - case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:467" - switch \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:468" - attribute \nmigen.decoding "RC/2" - case 2'10 - assign \oe \OE - end - end - sync init - end - process $group_1 - assign \oe_ok 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:450" - switch \internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:461" - attribute \nmigen.decoding "OP_MUL_H64/51|OP_MUL_H32/52|OP_EXTS/31|OP_CNTZ/14|OP_SHL/60|OP_SHR/61|OP_RLC/56|OP_LOAD/37|OP_STORE/38|OP_RLCL/57|OP_RLCR/58|OP_EXTSWSLI/32" - case 7'0110011, 7'0110100, 7'0011111, 7'0001110, 7'0111100, 7'0111101, 7'0111000, 7'0100101, 7'0100110, 7'0111001, 7'0111010, 7'0100000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:465" - attribute \nmigen.decoding "" - case - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:467" - switch \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:468" - attribute \nmigen.decoding "RC/2" - case 2'10 - assign \oe_ok 1'1 - end - end - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.dec2.dec_cr_in.ppick" -module \ppick$206 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" - wire width 8 input 0 \i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" - wire width 8 output 1 \o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:49" - wire width 8 \ni - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" - wire width 8 $1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" - cell $not $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \Y_WIDTH 8 - connect \A { \i [0] \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] } - connect \Y $1 - end - process $group_0 - assign \ni 8'00000000 - assign \ni $1 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire width 1 \t0 - process $group_1 - assign \t0 1'0 - assign \t0 \i [7] - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire width 1 \t1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire width 1 $3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire width 1 $4 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_bool $5 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A { \i [7] \ni [1] } - connect \Y $4 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $6 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $4 - connect \Y $3 - end - process $group_2 - assign \t1 1'0 - assign \t1 $3 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire width 1 \t2 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire width 1 $7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire width 1 $8 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_bool $9 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A { \i [6] \i [7] \ni [2] } - connect \Y $8 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $10 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $8 - connect \Y $7 - end - process $group_3 - assign \t2 1'0 - assign \t2 $7 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire width 1 \t3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire width 1 $11 - attribute \src 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\en_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" - wire width 1 $31 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" - cell $reduce_bool $32 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \o - connect \Y $31 - end - process $group_10 - assign \en_o 1'0 - assign \en_o $31 - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.dec2.dec_cr_in" -module \dec_cr_in$205 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:485" - wire width 32 input 0 \insn_in - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:484" - wire width 3 input 1 \sel_in - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 7 input 2 \internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 8 output 3 \cr_fxm - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 4 \cr_fxm_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 3 output 5 \cr_bitfield - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 6 \cr_bitfield_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 3 output 7 \cr_bitfield_b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 8 \cr_bitfield_b_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 3 output 9 \cr_bitfield_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 10 \cr_bitfield_o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 5 input 11 \BB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 5 input 12 \BA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 5 input 13 \BT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 8 input 14 \FXM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 5 input 15 \BI - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 5 input 16 \BC - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 3 input 17 \X_BFA - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" - wire width 8 \ppick_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" - wire width 8 \ppick_o - cell \ppick$206 \ppick - connect \i \ppick_i - connect \o \ppick_o - end - process $group_0 - assign \cr_bitfield_ok 1'0 - assign \cr_bitfield_ok 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" - switch \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" - attribute \nmigen.decoding "NONE/0" - case 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:505" - attribute \nmigen.decoding "CR0/1" - case 3'001 - assign \cr_bitfield_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:508" - attribute \nmigen.decoding "BI/2" - case 3'010 - assign \cr_bitfield_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:511" - attribute \nmigen.decoding "BFA/3" - case 3'011 - assign \cr_bitfield_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:514" - attribute \nmigen.decoding "BA_BB/4" - case 3'100 - assign \cr_bitfield_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:521" - attribute \nmigen.decoding "BC/5" - case 3'101 - assign \cr_bitfield_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:524" - attribute \nmigen.decoding "WHOLE_REG/6" - case 3'110 - end - sync init - end - process $group_1 - assign \cr_bitfield_b_ok 1'0 - assign \cr_bitfield_b_ok 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" - switch \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" - attribute \nmigen.decoding "NONE/0" - case 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:505" - attribute \nmigen.decoding "CR0/1" - case 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:508" - attribute \nmigen.decoding "BI/2" - case 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:511" - attribute \nmigen.decoding "BFA/3" - case 3'011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:514" - attribute \nmigen.decoding "BA_BB/4" - case 3'100 - assign \cr_bitfield_b_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:521" - attribute \nmigen.decoding "BC/5" - case 3'101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:524" - attribute \nmigen.decoding "WHOLE_REG/6" - case 3'110 - end - sync init - end - process $group_2 - assign \cr_fxm_ok 1'0 - assign \cr_fxm_ok 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" - switch \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" - attribute \nmigen.decoding "NONE/0" - case 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:505" - attribute \nmigen.decoding "CR0/1" - case 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:508" - attribute \nmigen.decoding "BI/2" - case 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:511" - attribute \nmigen.decoding "BFA/3" - case 3'011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:514" - attribute \nmigen.decoding "BA_BB/4" - case 3'100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:521" - attribute \nmigen.decoding "BC/5" - case 3'101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:524" - attribute \nmigen.decoding "WHOLE_REG/6" - case 3'110 - assign \cr_fxm_ok 1'1 - end - sync init - end - process $group_3 - assign \cr_bitfield 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" - switch \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" - attribute \nmigen.decoding "NONE/0" - case 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:505" - attribute \nmigen.decoding "CR0/1" - case 3'001 - assign \cr_bitfield 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:508" - attribute \nmigen.decoding "BI/2" - case 3'010 - assign \cr_bitfield \BI [4:2] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:511" - attribute \nmigen.decoding "BFA/3" - case 3'011 - assign \cr_bitfield \X_BFA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:514" - attribute \nmigen.decoding "BA_BB/4" - case 3'100 - assign \cr_bitfield \BA [4:2] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:521" - attribute \nmigen.decoding "BC/5" - case 3'101 - assign \cr_bitfield \BC [4:2] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:524" - attribute \nmigen.decoding "WHOLE_REG/6" - case 3'110 - end - sync init - end - process $group_4 - assign \cr_bitfield_b 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" - switch \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" - attribute \nmigen.decoding "NONE/0" - case 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:505" - attribute \nmigen.decoding "CR0/1" - case 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:508" - attribute \nmigen.decoding "BI/2" - case 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:511" - attribute \nmigen.decoding "BFA/3" - case 3'011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:514" - attribute \nmigen.decoding "BA_BB/4" - case 3'100 - assign \cr_bitfield_b \BB [4:2] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:521" - attribute \nmigen.decoding "BC/5" - case 3'101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:524" - attribute \nmigen.decoding "WHOLE_REG/6" - case 3'110 - end - sync init - end - process $group_5 - assign \cr_bitfield_o 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" - switch \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" - attribute \nmigen.decoding "NONE/0" - case 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:505" - attribute \nmigen.decoding "CR0/1" - case 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:508" - attribute \nmigen.decoding "BI/2" - case 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:511" - attribute \nmigen.decoding "BFA/3" - case 3'011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:514" - attribute \nmigen.decoding "BA_BB/4" - case 3'100 - assign \cr_bitfield_o \BT [4:2] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:521" - attribute \nmigen.decoding "BC/5" - case 3'101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:524" - attribute \nmigen.decoding "WHOLE_REG/6" - case 3'110 - end - sync init - end - process $group_6 - assign \cr_bitfield_o_ok 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" - switch \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" - attribute \nmigen.decoding "NONE/0" - case 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:505" - attribute \nmigen.decoding "CR0/1" - case 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:508" - attribute \nmigen.decoding "BI/2" - case 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:511" - attribute \nmigen.decoding "BFA/3" - case 3'011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:514" - attribute \nmigen.decoding "BA_BB/4" - case 3'100 - assign \cr_bitfield_o_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:521" - attribute \nmigen.decoding "BC/5" - case 3'101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:524" - attribute \nmigen.decoding "WHOLE_REG/6" - case 3'110 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:526" - wire width 1 \move_one - process $group_7 - assign \move_one 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" - switch \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" - attribute \nmigen.decoding "NONE/0" - case 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:505" - attribute \nmigen.decoding "CR0/1" - case 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:508" - attribute \nmigen.decoding "BI/2" - case 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:511" - attribute \nmigen.decoding "BFA/3" - case 3'011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:514" - attribute \nmigen.decoding "BA_BB/4" - case 3'100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:521" - attribute \nmigen.decoding "BC/5" - case 3'101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:524" - attribute \nmigen.decoding "WHOLE_REG/6" - case 3'110 - assign \move_one \insn_in [20] - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" - cell $eq $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A \internal_op - connect \B 7'0101101 - connect \Y $1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" - wire width 1 $3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" - cell $and $4 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $1 - connect \B \move_one - connect \Y $3 - end - process $group_8 - assign \ppick_i 8'00000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" - switch \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" - attribute \nmigen.decoding "NONE/0" - case 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:505" - attribute \nmigen.decoding "CR0/1" - case 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:508" - attribute \nmigen.decoding "BI/2" - case 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:511" - attribute \nmigen.decoding "BFA/3" - case 3'011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:514" - attribute \nmigen.decoding "BA_BB/4" - case 3'100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:521" - attribute \nmigen.decoding "BC/5" - case 3'101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:524" - attribute \nmigen.decoding "WHOLE_REG/6" - case 3'110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" - switch { $3 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" - case 1'1 - assign \ppick_i \FXM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532" - case - end - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" - wire width 1 $5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" - cell $eq $6 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A \internal_op - connect \B 7'0101101 - connect \Y $5 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" - wire width 1 $7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" - cell $and $8 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $5 - connect \B \move_one - connect \Y $7 - end - process $group_9 - assign \cr_fxm 8'00000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:502" - switch \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:503" - attribute \nmigen.decoding "NONE/0" - case 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:505" - attribute \nmigen.decoding "CR0/1" - case 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:508" - attribute \nmigen.decoding "BI/2" - case 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:511" - attribute \nmigen.decoding "BFA/3" - case 3'011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:514" - attribute \nmigen.decoding "BA_BB/4" - case 3'100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:521" - attribute \nmigen.decoding "BC/5" - case 3'101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:524" - attribute \nmigen.decoding "WHOLE_REG/6" - case 3'110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" - switch { $7 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:528" - case 1'1 - assign \cr_fxm \ppick_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:532" - case - assign \cr_fxm 8'11111111 - end - end - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.dec2.dec_cr_out.ppick" -module \ppick$208 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" - wire width 8 input 0 \i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" - wire width 1 output 1 \en_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" - wire width 8 output 2 \o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:49" - wire width 8 \ni - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" - wire width 8 $1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:53" - cell $not $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \Y_WIDTH 8 - connect \A { \i [0] \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] } - connect \Y $1 - end - process $group_0 - assign \ni 8'00000000 - assign \ni $1 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire width 1 \t0 - process $group_1 - assign \t0 1'0 - assign \t0 \i [7] - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire width 1 \t1 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire width 1 $3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire width 1 $4 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_bool $5 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A { \i [7] \ni [1] } - connect \Y $4 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $6 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $4 - connect \Y $3 - end - process $group_2 - assign \t1 1'0 - assign \t1 $3 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire width 1 \t2 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire width 1 $7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire width 1 $8 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_bool $9 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A { \i [6] \i [7] \ni [2] } - connect \Y $8 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $10 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $8 - connect \Y $7 - end - process $group_3 - assign \t2 1'0 - assign \t2 $7 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire width 1 \t3 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire width 1 $11 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire width 1 $12 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_bool $13 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A { \i [5] \i [6] \i [7] \ni [3] } - connect \Y $12 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $14 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $12 - connect \Y $11 - end - process $group_4 - assign \t3 1'0 - assign \t3 $11 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire width 1 \t4 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire width 1 $15 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire width 1 $16 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_bool $17 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A { \i [4] \i [5] \i [6] \i [7] \ni [4] } - connect \Y $16 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $18 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $16 - connect \Y $15 - end - process $group_5 - assign \t4 1'0 - assign \t4 $15 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire width 1 \t5 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire width 1 $19 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire width 1 $20 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_bool $21 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \Y_WIDTH 1 - connect \A { \i [3] \i [4] \i [5] \i [6] \i [7] \ni [5] } - connect \Y $20 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $22 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $20 - connect \Y $19 - end - process $group_6 - assign \t5 1'0 - assign \t5 $19 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire width 1 \t6 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire width 1 $23 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire width 1 $24 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_bool $25 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A { \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [6] } - connect \Y $24 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $26 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $24 - connect \Y $23 - end - process $group_7 - assign \t6 1'0 - assign \t6 $23 - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:58" - wire width 1 \t7 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire width 1 $27 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - wire width 1 $28 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $reduce_bool $29 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A { \i [1] \i [2] \i [3] \i [4] \i [5] \i [6] \i [7] \ni [7] } - connect \Y $28 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:63" - cell $not $30 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $28 - connect \Y $27 - end - process $group_8 - assign \t7 1'0 - assign \t7 $27 - sync init - end - process $group_9 - assign \o 8'00000000 - assign \o { \t0 \t1 \t2 \t3 \t4 \t5 \t6 \t7 } - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" - wire width 1 $31 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:69" - cell $reduce_bool $32 - parameter \A_SIGNED 0 - parameter \A_WIDTH 8 - parameter \Y_WIDTH 1 - connect \A \o - connect \Y $31 - end - process $group_10 - assign \en_o 1'0 - assign \en_o $31 - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.dec2.dec_cr_out" -module \dec_cr_out$207 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:550" - wire width 32 input 0 \insn_in - attribute \enum_base_type "CROutSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BF" - attribute \enum_value_011 "BT" - attribute \enum_value_100 "WHOLE_REG" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:549" - wire width 3 input 1 \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:548" - wire width 1 input 2 \rc_in - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 7 input 3 \internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 8 output 4 \cr_fxm - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 5 \cr_fxm_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 3 output 6 \cr_bitfield - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 7 \cr_bitfield_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 8 input 8 \FXM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 3 input 9 \X_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 5 input 10 \XL_BT - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:40" - wire width 8 \ppick_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:42" - wire width 1 \ppick_en_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/picker.py:41" - wire width 8 \ppick_o - cell \ppick$208 \ppick - connect \i \ppick_i - connect \en_o \ppick_en_o - connect \o \ppick_o - end - process $group_0 - assign \cr_bitfield_ok 1'0 - assign \cr_bitfield_ok 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:563" - switch \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:564" - attribute \nmigen.decoding "NONE/0" - case 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:566" - attribute \nmigen.decoding "CR0/1" - case 3'001 - assign \cr_bitfield_ok \rc_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:569" - attribute \nmigen.decoding "BF/2" - case 3'010 - assign \cr_bitfield_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:572" - attribute \nmigen.decoding "BT/3" - case 3'011 - assign \cr_bitfield_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:575" - attribute \nmigen.decoding "WHOLE_REG/4" - case 3'100 - end - sync init - end - process $group_1 - assign \cr_fxm_ok 1'0 - assign \cr_fxm_ok 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:563" - switch \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:564" - attribute \nmigen.decoding "NONE/0" - case 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:566" - attribute \nmigen.decoding "CR0/1" - case 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:569" - attribute \nmigen.decoding "BF/2" - case 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:572" - attribute \nmigen.decoding "BT/3" - case 3'011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:575" - attribute \nmigen.decoding "WHOLE_REG/4" - case 3'100 - assign \cr_fxm_ok 1'1 - end - sync init - end - process $group_2 - assign \cr_bitfield 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:563" - switch \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:564" - attribute \nmigen.decoding "NONE/0" - case 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:566" - attribute \nmigen.decoding "CR0/1" - case 3'001 - assign \cr_bitfield 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:569" - attribute \nmigen.decoding "BF/2" - case 3'010 - assign \cr_bitfield \X_BF - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:572" - attribute \nmigen.decoding "BT/3" - case 3'011 - assign \cr_bitfield \XL_BT [4:2] - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:575" - attribute \nmigen.decoding "WHOLE_REG/4" - case 3'100 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:577" - wire width 1 \move_one - process $group_3 - assign \move_one 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:563" - switch \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:564" - attribute \nmigen.decoding "NONE/0" - case 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:566" - attribute \nmigen.decoding "CR0/1" - case 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:569" - attribute \nmigen.decoding "BF/2" - case 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:572" - attribute \nmigen.decoding "BT/3" - case 3'011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:575" - attribute \nmigen.decoding "WHOLE_REG/4" - case 3'100 - assign \move_one \insn_in [20] - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:579" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:579" - cell $eq $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A \internal_op - connect \B 7'0110000 - connect \Y $1 - end - process $group_4 - assign \ppick_i 8'00000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:563" - switch \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:564" - attribute \nmigen.decoding "NONE/0" - case 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:566" - attribute \nmigen.decoding "CR0/1" - case 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:569" - attribute \nmigen.decoding "BF/2" - case 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:572" - attribute \nmigen.decoding "BT/3" - case 3'011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:575" - attribute \nmigen.decoding "WHOLE_REG/4" - case 3'100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:579" - switch { $1 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:579" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:580" - switch { \move_one } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:580" - case 1'1 - assign \ppick_i \FXM - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:587" - case - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:589" - case - end - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:579" - wire width 1 $3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:579" - cell $eq $4 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A \internal_op - connect \B 7'0110000 - connect \Y $3 - end - process $group_5 - assign \cr_fxm 8'00000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:563" - switch \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:564" - attribute \nmigen.decoding "NONE/0" - case 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:566" - attribute \nmigen.decoding "CR0/1" - case 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:569" - attribute \nmigen.decoding "BF/2" - case 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:572" - attribute \nmigen.decoding "BT/3" - case 3'011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:575" - attribute \nmigen.decoding "WHOLE_REG/4" - case 3'100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:579" - switch { $3 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:579" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:580" - switch { \move_one } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:580" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:583" - switch { \ppick_en_o } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:583" - case 1'1 - assign \cr_fxm \ppick_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:585" - case - assign \cr_fxm 8'00000001 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:587" - case - assign \cr_fxm \FXM - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:589" - case - assign \cr_fxm 8'11111111 - end - end - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.dec2.dec_a.sprmap" -module \sprmap - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:59" - wire width 10 input 0 \spr_i - attribute \enum_base_type "SPR" - attribute \enum_value_0000000001 "XER" - attribute \enum_value_0000000011 "DSCR" - attribute \enum_value_0000001000 "LR" - attribute \enum_value_0000001001 "CTR" - attribute \enum_value_0000001101 "AMR" - attribute \enum_value_0000010001 "DSCR_priv" - attribute \enum_value_0000010010 "DSISR" - attribute \enum_value_0000010011 "DAR" - attribute \enum_value_0000010110 "DEC" - attribute \enum_value_0000011010 "SRR0" - attribute \enum_value_0000011011 "SRR1" - attribute \enum_value_0000011100 "CFAR" - attribute \enum_value_0000011101 "AMR_priv" - attribute \enum_value_0000110000 "PIDR" - attribute \enum_value_0000111101 "IAMR" - attribute \enum_value_0010000000 "TFHAR" - attribute \enum_value_0010000001 "TFIAR" - attribute \enum_value_0010000010 "TEXASR" - attribute \enum_value_0010000011 "TEXASRU" - attribute \enum_value_0010001000 "CTRL" - attribute \enum_value_0010010000 "TIDR" - attribute \enum_value_0010011000 "CTRL_priv" - attribute \enum_value_0010011001 "FSCR" - attribute \enum_value_0010011101 "UAMOR" - attribute \enum_value_0010011110 "GSR" - attribute \enum_value_0010011111 "PSPB" - attribute \enum_value_0010110000 "DPDES" - attribute \enum_value_0010110100 "DAWR0" - attribute \enum_value_0010111010 "RPR" - attribute \enum_value_0010111011 "CIABR" - attribute \enum_value_0010111100 "DAWRX0" - attribute \enum_value_0010111110 "HFSCR" - attribute \enum_value_0100000000 "VRSAVE" - attribute \enum_value_0100000011 "SPRG3" - attribute \enum_value_0100001100 "TB" - attribute \enum_value_0100001101 "TBU" - attribute \enum_value_0100010000 "SPRG0_priv" - attribute \enum_value_0100010001 "SPRG1_priv" - attribute \enum_value_0100010010 "SPRG2_priv" - attribute \enum_value_0100010011 "SPRG3_priv" - attribute \enum_value_0100011011 "CIR" - attribute \enum_value_0100011100 "TBL" - attribute \enum_value_0100011101 "TBU_hypv" - attribute \enum_value_0100011110 "TBU40" - attribute \enum_value_0100011111 "PVR" - attribute \enum_value_0100110000 "HSPRG0" - attribute \enum_value_0100110001 "HSPRG1" - attribute \enum_value_0100110010 "HDSISR" - attribute \enum_value_0100110011 "HDAR" - attribute \enum_value_0100110100 "SPURR" - attribute \enum_value_0100110101 "PURR" - attribute \enum_value_0100110110 "HDEC" - attribute \enum_value_0100111001 "HRMOR" - attribute \enum_value_0100111010 "HSRR0" - attribute \enum_value_0100111011 "HSRR1" - attribute \enum_value_0100111110 "LPCR" - attribute \enum_value_0100111111 "LPIDR" - attribute \enum_value_0101010000 "HMER" - attribute \enum_value_0101010001 "HMEER" - attribute \enum_value_0101010010 "PCR" - attribute \enum_value_0101010011 "HEIR" - attribute \enum_value_0101011101 "AMOR" - attribute \enum_value_0110111110 "TIR" - attribute \enum_value_0111010000 "PTCR" - attribute \enum_value_1100000000 "SIER" - attribute \enum_value_1100000001 "MMCR2" - attribute \enum_value_1100000010 "MMCRA" - attribute \enum_value_1100000011 "PMC1" - attribute \enum_value_1100000100 "PMC2" - attribute \enum_value_1100000101 "PMC3" - attribute \enum_value_1100000110 "PMC4" - attribute \enum_value_1100000111 "PMC5" - attribute \enum_value_1100001000 "PMC6" - attribute \enum_value_1100001011 "MMCR0" - attribute \enum_value_1100001100 "SIAR" - attribute \enum_value_1100001101 "SDAR" - attribute \enum_value_1100001110 "MMCR1" - attribute \enum_value_1100010000 "SIER_priv" - attribute \enum_value_1100010001 "MMCR2_priv" - attribute \enum_value_1100010010 "MMCRA_priv" - attribute \enum_value_1100010011 "PMC1_priv" - attribute \enum_value_1100010100 "PMC2_priv" - attribute \enum_value_1100010101 "PMC3_priv" - attribute \enum_value_1100010110 "PMC4_priv" - attribute \enum_value_1100010111 "PMC5_priv" - attribute \enum_value_1100011000 "PMC6_priv" - attribute \enum_value_1100011011 "MMCR0_priv" - attribute \enum_value_1100011100 "SIAR_priv" - attribute \enum_value_1100011101 "SDAR_priv" - attribute \enum_value_1100011110 "MMCR1_priv" - attribute \enum_value_1100100000 "BESCRS" - attribute \enum_value_1100100001 "BESCRSU" - attribute \enum_value_1100100010 "BESCRR" - attribute \enum_value_1100100011 "BESCRRU" - attribute \enum_value_1100100100 "EBBHR" - attribute \enum_value_1100100101 "EBBRR" - attribute \enum_value_1100100110 "BESCR" - attribute \enum_value_1100101000 "reserved808" - attribute \enum_value_1100101001 "reserved809" - attribute \enum_value_1100101010 "reserved810" - attribute \enum_value_1100101011 "reserved811" - attribute \enum_value_1100101111 "TAR" - attribute \enum_value_1100110000 "ASDR" - attribute \enum_value_1100110111 "PSSCR" - attribute \enum_value_1101010000 "IC" - attribute \enum_value_1101010001 "VTB" - attribute \enum_value_1101010111 "PSSCR_hypv" - attribute \enum_value_1110000000 "PPR" - attribute \enum_value_1110000010 "PPR32" - attribute \enum_value_1111111111 "PIR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 10 output 1 \spr_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 2 \spr_o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 3 output 3 \fast_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 4 \fast_o_ok - process $group_0 - assign \fast_o 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:65" - switch \spr_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:71" - case 10'0000000001 - assign \fast_o 3'101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0000000011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:71" - case 10'0000001000 - assign \fast_o 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:71" - case 10'0000001001 - assign \fast_o 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0000001101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0000010001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0000010010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0000010011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:71" - case 10'0000010110 - assign \fast_o 3'110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:71" - case 10'0000011010 - assign \fast_o 3'011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:71" - case 10'0000011011 - assign \fast_o 3'100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0000011100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0000011101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0000110000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0000111101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0010000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0010000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0010000010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0010000011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0010001000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0010010000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0010011000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0010011001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0010011101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0010011110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0010011111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0010110000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0010110100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0010111010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0010111011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0010111100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0010111110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0100000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0100000011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:71" - case 10'0100001100 - assign \fast_o 3'111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0100001101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0100010000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0100010001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0100010010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0100010011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0100011011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0100011100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0100011101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0100011110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0100011111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0100110000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0100110001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0100110010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0100110011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0100110100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0100110101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0100110110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0100111001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0100111010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0100111011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0100111110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0100111111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0101010000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0101010001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0101010010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0101010011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0101011101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0110111110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0111010000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'1100000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'1100000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'1100000010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'1100000011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'1100000100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'1100000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'1100000110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'1100000111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'1100001000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'1100001011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'1100001100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'1100001101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'1100001110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'1100010000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'1100010001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'1100010010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'1100010011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'1100010100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'1100010101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'1100010110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'1100010111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'1100011000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'1100011011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'1100011100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'1100011101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'1100011110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'1100100000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'1100100001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'1100100010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'1100100011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'1100100100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'1100100101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'1100100110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'1100101000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'1100101001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'1100101010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'1100101011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:71" - case 10'1100101111 - assign \fast_o 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'1100110000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'1100110111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'1101010000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'1101010001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'1101010111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'1110000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'1110000010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'1111111111 - end - sync init - end - process $group_1 - assign \fast_o_ok 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:65" - switch \spr_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:71" - case 10'0000000001 - assign \fast_o_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0000000011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:71" - case 10'0000001000 - assign \fast_o_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:71" - case 10'0000001001 - assign \fast_o_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0000001101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0000010001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0000010010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0000010011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:71" - case 10'0000010110 - assign \fast_o_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:71" - case 10'0000011010 - assign \fast_o_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:71" - case 10'0000011011 - assign \fast_o_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0000011100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0000011101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0000110000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0000111101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0010000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0010000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0010000010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0010000011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0010001000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0010010000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0010011000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0010011001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0010011101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0010011110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0010011111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0010110000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0010110100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0010111010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0010111011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0010111100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0010111110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0100000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0100000011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:71" - case 10'0100001100 - assign \fast_o_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0100001101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0100010000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0100010001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0100010010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0100010011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0100011011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0100011100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0100011101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0100011110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0100011111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0100110000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0100110001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0100110010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0100110011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0100110100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0100110101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0100110110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0100111001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0100111010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0100111011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0100111110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0100111111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0101010000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0101010001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0101010010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0101010011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0101011101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0110111110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0111010000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'1100000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'1100000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'1100000010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'1100000011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'1100000100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'1100000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'1100000110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'1100000111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'1100001000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'1100001011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'1100001100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'1100001101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'1100001110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'1100010000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'1100010001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'1100010010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'1100010011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'1100010100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'1100010101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'1100010110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'1100010111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'1100011000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'1100011011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'1100011100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'1100011101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'1100011110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'1100100000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'1100100001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'1100100010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'1100100011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'1100100100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'1100100101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'1100100110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'1100101000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'1100101001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'1100101010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'1100101011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:71" - case 10'1100101111 - assign \fast_o_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'1100110000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'1100110111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'1101010000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'1101010001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'1101010111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'1110000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'1110000010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'1111111111 - end - sync init - end - process $group_2 - assign \spr_o 10'0000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:65" - switch \spr_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:71" - case 10'0000000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0000000011 - assign \spr_o 10'0000000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:71" - case 10'0000001000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:71" - case 10'0000001001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0000001101 - assign \spr_o 10'0000000100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0000010001 - assign \spr_o 10'0000000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0000010010 - assign \spr_o 10'0000000110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0000010011 - assign \spr_o 10'0000000111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:71" - case 10'0000010110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:71" - case 10'0000011010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:71" - case 10'0000011011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0000011100 - assign \spr_o 10'0000001011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0000011101 - assign \spr_o 10'0000001100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0000110000 - assign \spr_o 10'0000001101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0000111101 - assign \spr_o 10'0000001110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0010000000 - assign \spr_o 10'0000001111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0010000001 - assign \spr_o 10'0000010000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0010000010 - assign \spr_o 10'0000010001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0010000011 - assign \spr_o 10'0000010010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0010001000 - assign \spr_o 10'0000010011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0010010000 - assign \spr_o 10'0000010100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0010011000 - assign \spr_o 10'0000010101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0010011001 - assign \spr_o 10'0000010110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0010011101 - assign \spr_o 10'0000010111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0010011110 - assign \spr_o 10'0000011000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0010011111 - assign \spr_o 10'0000011001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0010110000 - assign \spr_o 10'0000011010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0010110100 - assign \spr_o 10'0000011011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0010111010 - assign \spr_o 10'0000011100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0010111011 - assign \spr_o 10'0000011101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0010111100 - assign \spr_o 10'0000011110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0010111110 - assign \spr_o 10'0000011111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0100000000 - assign \spr_o 10'0000100000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0100000011 - assign \spr_o 10'0000100001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:71" - case 10'0100001100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0100001101 - assign \spr_o 10'0000100011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0100010000 - assign \spr_o 10'0000100100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0100010001 - assign \spr_o 10'0000100101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0100010010 - assign \spr_o 10'0000100110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0100010011 - assign \spr_o 10'0000100111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0100011011 - assign \spr_o 10'0000101000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0100011100 - assign \spr_o 10'0000101001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0100011101 - assign \spr_o 10'0000101010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0100011110 - assign \spr_o 10'0000101011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0100011111 - assign \spr_o 10'0000101100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0100110000 - assign \spr_o 10'0000101101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0100110001 - assign \spr_o 10'0000101110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0100110010 - assign \spr_o 10'0000101111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0100110011 - assign \spr_o 10'0000110000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0100110100 - assign \spr_o 10'0000110001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0100110101 - assign \spr_o 10'0000110010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0100110110 - assign \spr_o 10'0000110011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0100111001 - assign \spr_o 10'0000110100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0100111010 - assign \spr_o 10'0000110101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0100111011 - assign \spr_o 10'0000110110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0100111110 - assign \spr_o 10'0000110111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0100111111 - assign \spr_o 10'0000111000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0101010000 - assign \spr_o 10'0000111001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0101010001 - assign \spr_o 10'0000111010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0101010010 - assign \spr_o 10'0000111011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0101010011 - assign \spr_o 10'0000111100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0101011101 - assign \spr_o 10'0000111101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0110111110 - assign \spr_o 10'0000111110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0111010000 - assign \spr_o 10'0000111111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'1100000000 - assign \spr_o 10'0001000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'1100000001 - assign \spr_o 10'0001000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'1100000010 - assign \spr_o 10'0001000010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'1100000011 - assign \spr_o 10'0001000011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'1100000100 - assign \spr_o 10'0001000100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'1100000101 - assign \spr_o 10'0001000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'1100000110 - assign \spr_o 10'0001000110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'1100000111 - assign \spr_o 10'0001000111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'1100001000 - assign \spr_o 10'0001001000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'1100001011 - assign \spr_o 10'0001001001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'1100001100 - assign \spr_o 10'0001001010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'1100001101 - assign \spr_o 10'0001001011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'1100001110 - assign \spr_o 10'0001001100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'1100010000 - assign \spr_o 10'0001001101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'1100010001 - assign \spr_o 10'0001001110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'1100010010 - assign \spr_o 10'0001001111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'1100010011 - assign \spr_o 10'0001010000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'1100010100 - assign \spr_o 10'0001010001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'1100010101 - assign \spr_o 10'0001010010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'1100010110 - assign \spr_o 10'0001010011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'1100010111 - assign \spr_o 10'0001010100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'1100011000 - assign \spr_o 10'0001010101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'1100011011 - assign \spr_o 10'0001010110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'1100011100 - assign \spr_o 10'0001010111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'1100011101 - assign \spr_o 10'0001011000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'1100011110 - assign \spr_o 10'0001011001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'1100100000 - assign \spr_o 10'0001011010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'1100100001 - assign \spr_o 10'0001011011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'1100100010 - assign \spr_o 10'0001011100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'1100100011 - assign \spr_o 10'0001011101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'1100100100 - assign \spr_o 10'0001011110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'1100100101 - assign \spr_o 10'0001011111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'1100100110 - assign \spr_o 10'0001100000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'1100101000 - assign \spr_o 10'0001100001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'1100101001 - assign \spr_o 10'0001100010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'1100101010 - assign \spr_o 10'0001100011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'1100101011 - assign \spr_o 10'0001100100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:71" - case 10'1100101111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'1100110000 - assign \spr_o 10'0001100110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'1100110111 - assign \spr_o 10'0001100111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'1101010000 - assign \spr_o 10'0001101000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'1101010001 - assign \spr_o 10'0001101001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'1101010111 - assign \spr_o 10'0001101010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'1110000000 - assign \spr_o 10'0001101011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'1110000010 - assign \spr_o 10'0001101100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'1111111111 - assign \spr_o 10'0001101101 - end - sync init - end - process $group_3 - assign \spr_o_ok 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:65" - switch \spr_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:71" - case 10'0000000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0000000011 - assign \spr_o_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:71" - case 10'0000001000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:71" - case 10'0000001001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0000001101 - assign \spr_o_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0000010001 - assign \spr_o_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0000010010 - assign \spr_o_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0000010011 - assign \spr_o_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:71" - case 10'0000010110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:71" - case 10'0000011010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:71" - case 10'0000011011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0000011100 - assign \spr_o_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0000011101 - assign \spr_o_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0000110000 - assign \spr_o_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0000111101 - assign \spr_o_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0010000000 - assign \spr_o_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0010000001 - assign \spr_o_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0010000010 - assign \spr_o_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0010000011 - assign \spr_o_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0010001000 - assign \spr_o_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0010010000 - assign \spr_o_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0010011000 - assign \spr_o_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0010011001 - assign \spr_o_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0010011101 - assign \spr_o_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0010011110 - assign \spr_o_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0010011111 - assign \spr_o_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0010110000 - assign \spr_o_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0010110100 - assign \spr_o_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0010111010 - assign \spr_o_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0010111011 - assign \spr_o_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0010111100 - assign \spr_o_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0010111110 - assign \spr_o_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0100000000 - assign \spr_o_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0100000011 - assign \spr_o_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:71" - case 10'0100001100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0100001101 - assign \spr_o_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0100010000 - assign \spr_o_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0100010001 - assign \spr_o_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0100010010 - assign \spr_o_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0100010011 - assign \spr_o_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0100011011 - assign \spr_o_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0100011100 - assign \spr_o_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0100011101 - assign \spr_o_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0100011110 - assign \spr_o_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0100011111 - assign \spr_o_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0100110000 - assign \spr_o_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0100110001 - assign \spr_o_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0100110010 - assign \spr_o_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0100110011 - assign \spr_o_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0100110100 - assign \spr_o_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0100110101 - assign \spr_o_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0100110110 - assign \spr_o_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0100111001 - assign \spr_o_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0100111010 - assign \spr_o_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0100111011 - assign \spr_o_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0100111110 - assign \spr_o_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0100111111 - assign \spr_o_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0101010000 - assign \spr_o_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0101010001 - assign \spr_o_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0101010010 - assign \spr_o_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0101010011 - assign \spr_o_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0101011101 - assign \spr_o_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0110111110 - assign \spr_o_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0111010000 - assign \spr_o_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'1100000000 - assign \spr_o_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'1100000001 - assign \spr_o_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'1100000010 - assign \spr_o_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'1100000011 - assign \spr_o_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'1100000100 - assign \spr_o_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'1100000101 - assign \spr_o_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'1100000110 - assign \spr_o_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'1100000111 - assign \spr_o_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'1100001000 - assign \spr_o_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'1100001011 - assign \spr_o_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'1100001100 - assign \spr_o_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'1100001101 - assign \spr_o_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'1100001110 - assign \spr_o_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'1100010000 - assign \spr_o_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'1100010001 - assign \spr_o_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'1100010010 - assign \spr_o_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'1100010011 - assign \spr_o_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'1100010100 - assign \spr_o_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'1100010101 - assign \spr_o_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'1100010110 - assign \spr_o_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'1100010111 - assign \spr_o_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'1100011000 - assign \spr_o_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'1100011011 - assign \spr_o_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'1100011100 - assign \spr_o_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'1100011101 - assign \spr_o_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'1100011110 - assign \spr_o_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'1100100000 - assign \spr_o_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'1100100001 - assign \spr_o_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'1100100010 - assign \spr_o_ok 1'1 - attribute \src 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parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \sel_in - connect \B 3'100 - connect \Y $11 - end - process $group_1 - assign \reg_a 5'00000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:101" - switch { $9 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:101" - case 1'1 - assign \reg_a \ra - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:106" - switch { $11 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:106" - case 1'1 - assign \reg_a \RS - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:99" - wire width 1 $13 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:99" - cell $eq $14 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \sel_in - connect \B 3'001 - connect \Y $13 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:100" - wire width 1 $15 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:100" - cell $eq $16 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \sel_in - connect \B 3'010 - connect \Y $15 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:101" - wire width 1 $17 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:101" - cell $ne $18 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \B_SIGNED 0 - parameter \B_WIDTH 5 - parameter \Y_WIDTH 1 - connect \A \ra - connect \B 5'00000 - connect \Y $17 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:101" - wire width 1 $19 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:101" - cell $and $20 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $15 - connect \B $17 - connect \Y $19 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:101" - wire width 1 $21 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:101" - cell $or $22 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $13 - connect \B $19 - connect \Y $21 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:106" - wire width 1 $23 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:106" - cell $eq $24 - parameter \A_SIGNED 0 - parameter \A_WIDTH 3 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 1 - connect \A \sel_in - connect \B 3'100 - connect \Y $23 - end - process $group_2 - assign \reg_a_ok 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:101" - switch { $21 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:101" - case 1'1 - assign \reg_a_ok 1'1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:106" - switch { $23 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:106" - case 1'1 - assign \reg_a_ok 1'1 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:116" - wire width 1 $25 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:116" - cell $not $26 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \BO [2] - connect \Y $25 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:123" - wire width 1 $27 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:123" - cell $not $28 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \XL_XO [5] - connect \Y $27 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:123" - wire width 1 $29 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:123" - cell $and $30 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \XL_XO [9] - connect \B $27 - connect \Y $29 - end - process $group_3 - assign \fast_a 3'000 - assign \fast_a_ok 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:112" - switch \internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:115" - attribute \nmigen.decoding "OP_BC/7" - case 7'0000111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:116" - switch { $25 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:116" - case 1'1 - assign \fast_a 3'000 - assign \fast_a_ok 1'1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:120" - attribute \nmigen.decoding "OP_BCREG/8" - case 7'0001000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:123" - switch { $29 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:123" - case 1'1 - assign \fast_a 3'000 - assign \fast_a_ok 1'1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:129" - attribute \nmigen.decoding "OP_MFSPR/46" - case 7'0101110 - assign { \fast_a_ok \fast_a } { \sprmap_fast_o_ok \sprmap_fast_o } - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:130" - wire width 10 \spr - process $group_5 - assign \spr 10'0000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:112" - switch \internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:115" - attribute \nmigen.decoding "OP_BC/7" - case 7'0000111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:120" - attribute \nmigen.decoding "OP_BCREG/8" - case 7'0001000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:129" - attribute \nmigen.decoding "OP_MFSPR/46" - case 7'0101110 - assign \spr { \SPR [4:0] \SPR [9:5] } - end - sync init - end - process $group_6 - assign \sprmap_spr_i 10'0000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:112" - switch \internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:115" - attribute \nmigen.decoding "OP_BC/7" - case 7'0000111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:120" - attribute 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- attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 5 output 2 \reg_b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 3 \reg_b_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 3 output 4 \fast_b - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 5 \fast_b_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 5 input 6 \RS - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 5 input 7 \RB - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:402" - wire width 10 input 8 \XL_XO - process $group_0 - assign \reg_b 5'00000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:185" - switch \sel_in - attribute \src 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$eq $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A \internal_op - connect \B 7'0001000 - connect \Y $1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:201" - wire width 1 $3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:201" - cell $not $4 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \XL_XO [9] - connect \Y $3 - end - process $group_2 - assign \fast_b 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:198" - switch { $1 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:198" - case 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:201" - switch { \XL_XO [5] $3 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:201" - case 2'-1 - assign \fast_b 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:204" - case 2'1- - assign \fast_b 3'010 - end - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:198" - wire width 1 $5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:198" - cell $eq $6 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A \internal_op - connect \B 7'0001000 - connect \Y $5 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:201" - wire width 1 $7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:201" - cell $not $8 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \XL_XO [9] - connect \Y $7 - end - process $group_3 - assign \fast_b_ok 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:198" - switch { $5 } - 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attribute \enum_value_0100000011 "SPRG3" - attribute \enum_value_0100001100 "TB" - attribute \enum_value_0100001101 "TBU" - attribute \enum_value_0100010000 "SPRG0_priv" - attribute \enum_value_0100010001 "SPRG1_priv" - attribute \enum_value_0100010010 "SPRG2_priv" - attribute \enum_value_0100010011 "SPRG3_priv" - attribute \enum_value_0100011011 "CIR" - attribute \enum_value_0100011100 "TBL" - attribute \enum_value_0100011101 "TBU_hypv" - attribute \enum_value_0100011110 "TBU40" - attribute \enum_value_0100011111 "PVR" - attribute \enum_value_0100110000 "HSPRG0" - attribute \enum_value_0100110001 "HSPRG1" - attribute \enum_value_0100110010 "HDSISR" - attribute \enum_value_0100110011 "HDAR" - attribute \enum_value_0100110100 "SPURR" - attribute \enum_value_0100110101 "PURR" - attribute \enum_value_0100110110 "HDEC" - attribute \enum_value_0100111001 "HRMOR" - attribute \enum_value_0100111010 "HSRR0" - attribute \enum_value_0100111011 "HSRR1" - attribute \enum_value_0100111110 "LPCR" - attribute \enum_value_0100111111 "LPIDR" - attribute \enum_value_0101010000 "HMER" - attribute \enum_value_0101010001 "HMEER" - attribute \enum_value_0101010010 "PCR" - attribute \enum_value_0101010011 "HEIR" - attribute \enum_value_0101011101 "AMOR" - attribute \enum_value_0110111110 "TIR" - attribute \enum_value_0111010000 "PTCR" - attribute \enum_value_1100000000 "SIER" - attribute \enum_value_1100000001 "MMCR2" - attribute \enum_value_1100000010 "MMCRA" - attribute \enum_value_1100000011 "PMC1" - attribute \enum_value_1100000100 "PMC2" - attribute \enum_value_1100000101 "PMC3" - attribute \enum_value_1100000110 "PMC4" - attribute \enum_value_1100000111 "PMC5" - attribute \enum_value_1100001000 "PMC6" - attribute \enum_value_1100001011 "MMCR0" - attribute \enum_value_1100001100 "SIAR" - attribute \enum_value_1100001101 "SDAR" - attribute \enum_value_1100001110 "MMCR1" - attribute \enum_value_1100010000 "SIER_priv" - attribute \enum_value_1100010001 "MMCR2_priv" - attribute \enum_value_1100010010 "MMCRA_priv" - attribute \enum_value_1100010011 "PMC1_priv" - attribute \enum_value_1100010100 "PMC2_priv" - attribute \enum_value_1100010101 "PMC3_priv" - attribute \enum_value_1100010110 "PMC4_priv" - attribute \enum_value_1100010111 "PMC5_priv" - attribute \enum_value_1100011000 "PMC6_priv" - attribute \enum_value_1100011011 "MMCR0_priv" - attribute \enum_value_1100011100 "SIAR_priv" - attribute \enum_value_1100011101 "SDAR_priv" - attribute \enum_value_1100011110 "MMCR1_priv" - attribute \enum_value_1100100000 "BESCRS" - attribute \enum_value_1100100001 "BESCRSU" - attribute \enum_value_1100100010 "BESCRR" - attribute \enum_value_1100100011 "BESCRRU" - attribute \enum_value_1100100100 "EBBHR" - attribute \enum_value_1100100101 "EBBRR" - attribute \enum_value_1100100110 "BESCR" - attribute \enum_value_1100101000 "reserved808" - attribute \enum_value_1100101001 "reserved809" - attribute \enum_value_1100101010 "reserved810" - attribute \enum_value_1100101011 "reserved811" - attribute \enum_value_1100101111 "TAR" - attribute \enum_value_1100110000 "ASDR" - attribute \enum_value_1100110111 "PSSCR" - attribute \enum_value_1101010000 "IC" - attribute \enum_value_1101010001 "VTB" - attribute \enum_value_1101010111 "PSSCR_hypv" - attribute \enum_value_1110000000 "PPR" - attribute \enum_value_1110000010 "PPR32" - attribute \enum_value_1111111111 "PIR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 10 output 1 \spr_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 2 \spr_o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 3 output 3 \fast_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 4 \fast_o_ok - process $group_0 - assign \fast_o 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:65" - switch \spr_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:71" - case 10'0000000001 - assign \fast_o 3'101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0000000011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:71" - case 10'0000001000 - assign \fast_o 3'001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:71" - case 10'0000001001 - assign \fast_o 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0000001101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0000010001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0000010010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0000010011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:71" - case 10'0000010110 - assign \fast_o 3'110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:71" - case 10'0000011010 - assign \fast_o 3'011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:71" - case 10'0000011011 - assign \fast_o 3'100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0000011100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0000011101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0000110000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0000111101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0010000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0010000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0010000010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0010000011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0010001000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0010010000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0010011000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0010011001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0010011101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0010011110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0010011111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0010110000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0010110100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0010111010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0010111011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0010111100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0010111110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0100000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0100000011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:71" - case 10'0100001100 - assign \fast_o 3'111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0100001101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0100010000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0100010001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0100010010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0100010011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0100011011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0100011100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0100011101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0100011110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0100011111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0100110000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0100110001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0100110010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0100110011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0100110100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0100110101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0100110110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0100111001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0100111010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0100111011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0100111110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0100111111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0101010000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0101010001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0101010010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0101010011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0101011101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0110111110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0111010000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'1100000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'1100000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'1100000010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'1100000011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'1100000100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'1100000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'1100000110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'1100000111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'1100001000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'1100001011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'1100001100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'1100001101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'1100001110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'1100010000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'1100010001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'1100010010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'1100010011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'1100010100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'1100010101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'1100010110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'1100010111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'1100011000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'1100011011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'1100011100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'1100011101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'1100011110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'1100100000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'1100100001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'1100100010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'1100100011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'1100100100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'1100100101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'1100100110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'1100101000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'1100101001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'1100101010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'1100101011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:71" - case 10'1100101111 - assign \fast_o 3'010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'1100110000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'1100110111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'1101010000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'1101010001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'1101010111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'1110000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'1110000010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'1111111111 - end - sync init - end - process $group_1 - assign \fast_o_ok 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:65" - switch \spr_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:71" - case 10'0000000001 - assign \fast_o_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0000000011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:71" - case 10'0000001000 - assign \fast_o_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:71" - case 10'0000001001 - assign \fast_o_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0000001101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0000010001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0000010010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0000010011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:71" - case 10'0000010110 - assign \fast_o_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:71" - case 10'0000011010 - assign \fast_o_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:71" - case 10'0000011011 - assign \fast_o_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0000011100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0000011101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0000110000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0000111101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0010000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0010000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0010000010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0010000011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0010001000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0010010000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0010011000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0010011001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0010011101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0010011110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0010011111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0010110000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0010110100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0010111010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0010111011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0010111100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0010111110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0100000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0100000011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:71" - case 10'0100001100 - assign \fast_o_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0100001101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0100010000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0100010001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0100010010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0100010011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0100011011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0100011100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0100011101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0100011110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0100011111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0100110000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0100110001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0100110010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0100110011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0100110100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0100110101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0100110110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0100111001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0100111010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0100111011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0100111110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0100111111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0101010000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0101010001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0101010010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0101010011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0101011101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0110111110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0111010000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'1100000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'1100000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'1100000010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'1100000011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'1100000100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'1100000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'1100000110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'1100000111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'1100001000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'1100001011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'1100001100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'1100001101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'1100001110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'1100010000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'1100010001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'1100010010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'1100010011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'1100010100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'1100010101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'1100010110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'1100010111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'1100011000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'1100011011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'1100011100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'1100011101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'1100011110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'1100100000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'1100100001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'1100100010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'1100100011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'1100100100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'1100100101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'1100100110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'1100101000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'1100101001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'1100101010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'1100101011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:71" - case 10'1100101111 - assign \fast_o_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'1100110000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'1100110111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'1101010000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'1101010001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'1101010111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'1110000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'1110000010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'1111111111 - end - sync init - end - process $group_2 - assign \spr_o 10'0000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:65" - switch \spr_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:71" - case 10'0000000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0000000011 - assign \spr_o 10'0000000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:71" - case 10'0000001000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:71" - case 10'0000001001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0000001101 - assign \spr_o 10'0000000100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0000010001 - assign \spr_o 10'0000000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0000010010 - assign \spr_o 10'0000000110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0000010011 - assign \spr_o 10'0000000111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:71" - case 10'0000010110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:71" - case 10'0000011010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:71" - case 10'0000011011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0000011100 - assign \spr_o 10'0000001011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0000011101 - assign \spr_o 10'0000001100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0000110000 - assign \spr_o 10'0000001101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0000111101 - assign \spr_o 10'0000001110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0010000000 - assign \spr_o 10'0000001111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0010000001 - assign \spr_o 10'0000010000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0010000010 - assign \spr_o 10'0000010001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0010000011 - assign \spr_o 10'0000010010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0010001000 - assign \spr_o 10'0000010011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0010010000 - assign \spr_o 10'0000010100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0010011000 - assign \spr_o 10'0000010101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0010011001 - assign \spr_o 10'0000010110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0010011101 - assign \spr_o 10'0000010111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0010011110 - assign \spr_o 10'0000011000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0010011111 - assign \spr_o 10'0000011001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0010110000 - assign \spr_o 10'0000011010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0010110100 - assign \spr_o 10'0000011011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0010111010 - assign \spr_o 10'0000011100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0010111011 - assign \spr_o 10'0000011101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0010111100 - assign \spr_o 10'0000011110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0010111110 - assign \spr_o 10'0000011111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0100000000 - assign \spr_o 10'0000100000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0100000011 - assign \spr_o 10'0000100001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:71" - case 10'0100001100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0100001101 - assign \spr_o 10'0000100011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0100010000 - assign \spr_o 10'0000100100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0100010001 - assign \spr_o 10'0000100101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0100010010 - assign \spr_o 10'0000100110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0100010011 - assign \spr_o 10'0000100111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0100011011 - assign \spr_o 10'0000101000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0100011100 - assign \spr_o 10'0000101001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0100011101 - assign \spr_o 10'0000101010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0100011110 - assign \spr_o 10'0000101011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0100011111 - assign \spr_o 10'0000101100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0100110000 - assign \spr_o 10'0000101101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0100110001 - assign \spr_o 10'0000101110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0100110010 - assign \spr_o 10'0000101111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0100110011 - assign \spr_o 10'0000110000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0100110100 - assign \spr_o 10'0000110001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0100110101 - assign \spr_o 10'0000110010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0100110110 - assign \spr_o 10'0000110011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0100111001 - assign \spr_o 10'0000110100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0100111010 - assign \spr_o 10'0000110101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0100111011 - assign \spr_o 10'0000110110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0100111110 - assign \spr_o 10'0000110111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0100111111 - assign \spr_o 10'0000111000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0101010000 - assign \spr_o 10'0000111001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0101010001 - assign \spr_o 10'0000111010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0101010010 - assign \spr_o 10'0000111011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0101010011 - assign \spr_o 10'0000111100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0101011101 - assign \spr_o 10'0000111101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0110111110 - assign \spr_o 10'0000111110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0111010000 - assign \spr_o 10'0000111111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'1100000000 - assign \spr_o 10'0001000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'1100000001 - assign \spr_o 10'0001000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'1100000010 - assign \spr_o 10'0001000010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'1100000011 - assign \spr_o 10'0001000011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'1100000100 - assign \spr_o 10'0001000100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'1100000101 - assign \spr_o 10'0001000101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'1100000110 - assign \spr_o 10'0001000110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'1100000111 - assign \spr_o 10'0001000111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'1100001000 - assign \spr_o 10'0001001000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'1100001011 - assign \spr_o 10'0001001001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'1100001100 - assign \spr_o 10'0001001010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'1100001101 - assign \spr_o 10'0001001011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'1100001110 - assign \spr_o 10'0001001100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'1100010000 - assign \spr_o 10'0001001101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'1100010001 - assign \spr_o 10'0001001110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'1100010010 - assign \spr_o 10'0001001111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'1100010011 - assign \spr_o 10'0001010000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'1100010100 - assign \spr_o 10'0001010001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'1100010101 - assign \spr_o 10'0001010010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'1100010110 - assign \spr_o 10'0001010011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'1100010111 - assign \spr_o 10'0001010100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'1100011000 - assign \spr_o 10'0001010101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'1100011011 - assign \spr_o 10'0001010110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'1100011100 - assign \spr_o 10'0001010111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'1100011101 - assign \spr_o 10'0001011000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'1100011110 - assign \spr_o 10'0001011001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'1100100000 - assign \spr_o 10'0001011010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'1100100001 - assign \spr_o 10'0001011011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'1100100010 - assign \spr_o 10'0001011100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'1100100011 - assign \spr_o 10'0001011101 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'1100100100 - assign \spr_o 10'0001011110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'1100100101 - assign \spr_o 10'0001011111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'1100100110 - assign \spr_o 10'0001100000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'1100101000 - assign \spr_o 10'0001100001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'1100101001 - assign \spr_o 10'0001100010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'1100101010 - assign \spr_o 10'0001100011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'1100101011 - assign \spr_o 10'0001100100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:71" - case 10'1100101111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'1100110000 - assign \spr_o 10'0001100110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'1100110111 - assign \spr_o 10'0001100111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'1101010000 - assign \spr_o 10'0001101000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'1101010001 - assign \spr_o 10'0001101001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'1101010111 - assign \spr_o 10'0001101010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'1110000000 - assign \spr_o 10'0001101011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'1110000010 - assign \spr_o 10'0001101100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'1111111111 - assign \spr_o 10'0001101101 - end - sync init - end - process $group_3 - assign \spr_o_ok 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:65" - switch \spr_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:71" - case 10'0000000001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0000000011 - assign \spr_o_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:71" - case 10'0000001000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:71" - case 10'0000001001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0000001101 - assign \spr_o_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0000010001 - assign \spr_o_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0000010010 - assign \spr_o_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0000010011 - assign \spr_o_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:71" - case 10'0000010110 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:71" - case 10'0000011010 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:71" - case 10'0000011011 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0000011100 - assign \spr_o_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0000011101 - assign \spr_o_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0000110000 - assign \spr_o_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0000111101 - assign \spr_o_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0010000000 - assign \spr_o_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0010000001 - assign \spr_o_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0010000010 - assign \spr_o_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0010000011 - assign \spr_o_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0010001000 - assign \spr_o_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0010010000 - assign \spr_o_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0010011000 - assign \spr_o_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0010011001 - assign \spr_o_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0010011101 - assign \spr_o_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0010011110 - assign \spr_o_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0010011111 - assign \spr_o_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0010110000 - assign \spr_o_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0010110100 - assign \spr_o_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0010111010 - assign \spr_o_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0010111011 - assign \spr_o_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0010111100 - assign \spr_o_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0010111110 - assign \spr_o_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0100000000 - assign \spr_o_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0100000011 - assign \spr_o_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:71" - case 10'0100001100 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0100001101 - assign \spr_o_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0100010000 - assign \spr_o_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0100010001 - assign \spr_o_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0100010010 - assign \spr_o_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0100010011 - assign \spr_o_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0100011011 - assign \spr_o_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0100011100 - assign \spr_o_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0100011101 - assign \spr_o_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0100011110 - assign \spr_o_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0100011111 - assign \spr_o_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0100110000 - assign \spr_o_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0100110001 - assign \spr_o_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0100110010 - assign \spr_o_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0100110011 - assign \spr_o_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0100110100 - assign \spr_o_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0100110101 - assign \spr_o_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0100110110 - assign \spr_o_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0100111001 - assign \spr_o_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0100111010 - assign \spr_o_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0100111011 - assign \spr_o_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0100111110 - assign \spr_o_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0100111111 - assign \spr_o_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0101010000 - assign \spr_o_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0101010001 - assign \spr_o_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0101010010 - assign \spr_o_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0101010011 - assign \spr_o_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0101011101 - assign \spr_o_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0110111110 - assign \spr_o_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'0111010000 - assign \spr_o_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'1100000000 - assign \spr_o_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'1100000001 - assign \spr_o_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'1100000010 - assign \spr_o_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'1100000011 - assign \spr_o_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'1100000100 - assign \spr_o_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'1100000101 - assign \spr_o_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'1100000110 - assign \spr_o_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'1100000111 - assign \spr_o_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'1100001000 - assign \spr_o_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'1100001011 - assign \spr_o_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'1100001100 - assign \spr_o_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'1100001101 - assign \spr_o_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'1100001110 - assign \spr_o_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'1100010000 - assign \spr_o_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'1100010001 - assign \spr_o_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'1100010010 - assign \spr_o_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'1100010011 - assign \spr_o_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'1100010100 - assign \spr_o_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'1100010101 - assign \spr_o_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'1100010110 - assign \spr_o_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'1100010111 - assign \spr_o_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'1100011000 - assign \spr_o_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'1100011011 - assign \spr_o_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'1100011100 - assign \spr_o_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'1100011101 - assign \spr_o_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'1100011110 - assign \spr_o_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'1100100000 - assign \spr_o_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'1100100001 - assign \spr_o_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'1100100010 - assign \spr_o_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'1100100011 - assign \spr_o_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'1100100100 - assign \spr_o_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'1100100101 - assign \spr_o_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'1100100110 - assign \spr_o_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'1100101000 - assign \spr_o_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'1100101001 - assign \spr_o_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'1100101010 - assign \spr_o_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'1100101011 - assign \spr_o_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:71" - case 10'1100101111 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'1100110000 - assign \spr_o_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'1100110111 - assign \spr_o_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'1101010000 - assign \spr_o_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'1101010001 - assign \spr_o_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'1101010111 - assign \spr_o_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'1110000000 - assign \spr_o_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'1110000010 - assign \spr_o_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:67" - case 10'1111111111 - assign \spr_o_ok 1'1 - end - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.dec2.dec_o" -module \dec_o - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute 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\enum_value_1100011101 "SDAR_priv" - attribute \enum_value_1100011110 "MMCR1_priv" - attribute \enum_value_1100100000 "BESCRS" - attribute \enum_value_1100100001 "BESCRSU" - attribute \enum_value_1100100010 "BESCRR" - attribute \enum_value_1100100011 "BESCRRU" - attribute \enum_value_1100100100 "EBBHR" - attribute \enum_value_1100100101 "EBBRR" - attribute \enum_value_1100100110 "BESCR" - attribute \enum_value_1100101000 "reserved808" - attribute \enum_value_1100101001 "reserved809" - attribute \enum_value_1100101010 "reserved810" - attribute \enum_value_1100101011 "reserved811" - attribute \enum_value_1100101111 "TAR" - attribute \enum_value_1100110000 "ASDR" - attribute \enum_value_1100110111 "PSSCR" - attribute \enum_value_1101010000 "IC" - attribute \enum_value_1101010001 "VTB" - attribute \enum_value_1101010111 "PSSCR_hypv" - attribute \enum_value_1110000000 "PPR" - attribute \enum_value_1110000010 "PPR32" - attribute \enum_value_1111111111 "PIR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 10 \sprmap_spr_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \sprmap_spr_o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 3 \sprmap_fast_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \sprmap_fast_o_ok - cell \sprmap$209 \sprmap - connect \spr_i \sprmap_spr_i - connect \spr_o \sprmap_spr_o - connect \spr_o_ok \sprmap_spr_o_ok - connect \fast_o \sprmap_fast_o - connect \fast_o_ok \sprmap_fast_o_ok - end - process $group_0 - assign \reg_o 5'00000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:321" - switch \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:322" - attribute \nmigen.decoding "RT/1" - case 2'01 - assign \reg_o \RT - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:325" - attribute \nmigen.decoding "RA/2" - case 2'10 - assign \reg_o \RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:328" - attribute \nmigen.decoding "SPR/3" - case 2'11 - end - sync init - end - process $group_1 - assign \reg_o_ok 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:321" - switch \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:322" - attribute \nmigen.decoding "RT/1" - case 2'01 - assign \reg_o_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:325" - attribute \nmigen.decoding "RA/2" - case 2'10 - assign \reg_o_ok 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:328" - attribute \nmigen.decoding "SPR/3" - case 2'11 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:329" - wire width 10 \spr - process $group_2 - assign \spr 10'0000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:321" - switch \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:322" - attribute \nmigen.decoding "RT/1" - case 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:325" - attribute \nmigen.decoding "RA/2" - case 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:328" - attribute \nmigen.decoding "SPR/3" - case 2'11 - assign \spr { \SPR [4:0] \SPR [9:5] } - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:332" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:332" - cell $eq $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A \internal_op - connect \B 7'0110001 - connect \Y $1 - end - process $group_3 - assign \sprmap_spr_i 10'0000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:321" - switch \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:322" - attribute \nmigen.decoding "RT/1" - case 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:325" - attribute \nmigen.decoding "RA/2" - case 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:328" - attribute \nmigen.decoding "SPR/3" - case 2'11 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:332" - switch { $1 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:332" - case 1'1 - assign \sprmap_spr_i \spr - end - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:332" - wire width 1 $3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:332" - cell $eq $4 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A \internal_op - connect \B 7'0110001 - connect \Y $3 - end - process $group_4 - assign \spr_o 10'0000000000 - assign \spr_o_ok 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:321" - switch \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:322" - attribute \nmigen.decoding "RT/1" - case 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:325" - attribute \nmigen.decoding "RA/2" - case 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:328" - attribute \nmigen.decoding "SPR/3" - case 2'11 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:332" - switch { $3 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:332" - case 1'1 - assign { \spr_o_ok \spr_o } { \sprmap_spr_o_ok \sprmap_spr_o } - end - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:332" - wire width 1 $5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:332" - cell $eq $6 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A \internal_op - connect \B 7'0110001 - connect \Y $5 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:341" - wire width 1 $7 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:341" - cell $not $8 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \BO [2] - connect \Y $7 - end - process $group_6 - assign \fast_o 3'000 - assign \fast_o_ok 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:321" - switch \sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:322" - attribute \nmigen.decoding "RT/1" - case 2'01 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:325" - attribute \nmigen.decoding "RA/2" - case 2'10 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:328" - attribute \nmigen.decoding "SPR/3" - case 2'11 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:332" - switch { $5 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:332" - case 1'1 - assign { \fast_o_ok \fast_o } { \sprmap_fast_o_ok \sprmap_fast_o } - end - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:337" - switch \internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:340" - attribute \nmigen.decoding "OP_BC/7|OP_BCREG/8" - case 7'0000111, 7'0001000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:341" - switch { $7 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:341" - case 1'1 - assign \fast_o 3'000 - assign \fast_o_ok 1'1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:347" - attribute \nmigen.decoding "OP_RFID/70" - case 7'1000110 - assign \fast_o 3'011 - assign \fast_o_ok 1'1 - end - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.dec2.dec_o2" -module \dec_o2 - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - 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"/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 5 output 2 \reg_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 3 \reg_o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 3 output 4 \fast_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 output 5 \fast_o_ok - attribute \enum_base_type "LDSTMode" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "update" - attribute \enum_value_10 "cix" - attribute \enum_value_11 "cx" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:173" - wire width 2 input 6 \upd - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 5 input 7 \RA - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:373" - wire width 1 $1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:373" - cell $eq $2 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 2 - parameter \Y_WIDTH 1 - connect \A \upd - connect \B 2'01 - connect \Y $1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - wire width 6 $3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:389" - cell $pos $4 - parameter \A_SIGNED 0 - parameter \A_WIDTH 5 - parameter \Y_WIDTH 6 - connect \A \RA - connect \Y $3 - end - process $group_0 - assign \reg_o 5'00000 - assign \reg_o_ok 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:373" - switch { $1 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:373" - case 1'1 - assign { \reg_o_ok \reg_o } $3 - assign \reg_o_ok 1'1 - end - sync init - end - process $group_2 - assign \fast_o 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:380" - switch \internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:383" - attribute \nmigen.decoding "OP_BC/7|OP_B/6|OP_BCREG/8" - case 7'0000111, 7'0000110, 7'0001000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:384" - switch { \lk } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:384" - case 1'1 - assign \fast_o 3'001 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:389" - attribute \nmigen.decoding "OP_RFID/70" - case 7'1000110 - assign \fast_o 3'100 - end - sync init - end - process $group_3 - assign \fast_o_ok 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:380" - switch \internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:383" - attribute \nmigen.decoding "OP_BC/7|OP_B/6|OP_BCREG/8" - case 7'0000111, 7'0000110, 7'0001000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:384" - switch { \lk } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:384" - case 1'1 - assign \fast_o_ok 1'1 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:389" - attribute \nmigen.decoding "OP_RFID/70" - case 7'1000110 - assign \fast_o_ok 1'1 - end - sync init - end -end -attribute \generator "nMigen" -attribute \nmigen.hierarchy "test_issuer.dec2" -module \dec2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:385" - wire width 1 input 0 \bigendian - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:8" - wire width 64 input 1 \cur_pc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:9" - wire width 64 input 2 \cur_msr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:384" - wire width 32 input 3 \raw_opcode_in - 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\enum_value_01 "ONE" - attribute \enum_value_10 "RC" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:441" - wire width 2 \dec_oe_sel_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \dec_oe_oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \dec_oe_oe_ok - cell \dec_oe$204 \dec_oe - connect \sel_in \dec_oe_sel_in - connect \internal_op \dec_internal_op - connect \oe \dec_oe_oe - connect \oe_ok \dec_oe_oe_ok - connect \OE \dec_OE - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:485" - wire width 32 \dec_cr_in_insn_in - attribute \enum_base_type "CRInSel" - attribute \enum_value_000 "NONE" - attribute \enum_value_001 "CR0" - attribute \enum_value_010 "BI" - attribute \enum_value_011 "BFA" - attribute \enum_value_100 "BA_BB" - attribute \enum_value_101 "BC" - attribute \enum_value_110 "WHOLE_REG" - attribute \src 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attribute \enum_value_1101010111 "PSSCR_hypv" - attribute \enum_value_1110000000 "PPR" - attribute \enum_value_1110000010 "PPR32" - attribute \enum_value_1111111111 "PIR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 10 \dec_o_spr_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \dec_o_spr_o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 3 \dec_o_fast_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \dec_o_fast_o_ok - cell \dec_o \dec_o - connect \internal_op \dec_internal_op - connect \sel_in \dec_o_sel_in - connect \reg_o \dec_o_reg_o - connect \reg_o_ok \dec_o_reg_o_ok - connect \spr_o \dec_o_spr_o - connect \spr_o_ok \dec_o_spr_o_ok - connect \fast_o \dec_o_fast_o - connect \fast_o_ok \dec_o_fast_o_ok - connect \RT \dec_RT - connect \RA \dec_RA - connect \BO \dec_BO - connect \SPR \dec_SPR - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:363" - wire width 1 \dec_o2_lk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 5 \dec_o2_reg_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \dec_o2_reg_o_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 3 \dec_o2_fast_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \dec_o2_fast_o_ok - cell \dec_o2 \dec_o2 - connect \internal_op \dec_internal_op - connect \lk \dec_o2_lk - connect \reg_o \dec_o2_reg_o - connect \reg_o_ok \dec_o2_reg_o_ok - connect \fast_o \dec_o2_fast_o - connect \fast_o_ok \dec_o2_fast_o_ok - connect \upd \dec_upd - connect \RA \dec_RA - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:45" - wire width 32 \tmp_tmp_insn - process $group_0 - assign \tmp_tmp_insn 32'00000000000000000000000000000000 - assign \tmp_tmp_insn \dec_opcode_in - assign \tmp_tmp_insn \dec_opcode_in - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:405" - wire width 32 \insn_in - process $group_1 - assign \insn_in 32'00000000000000000000000000000000 - assign \insn_in \dec_opcode_in - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:442" - wire width 32 \insn_in$5 - process $group_2 - assign \insn_in$5 32'00000000000000000000000000000000 - assign \insn_in$5 \dec_opcode_in - sync init - end - process $group_3 - assign \dec_cr_in_insn_in 32'00000000000000000000000000000000 - assign \dec_cr_in_insn_in \dec_opcode_in - sync init - end - process $group_4 - assign \dec_cr_out_insn_in 32'00000000000000000000000000000000 - assign \dec_cr_out_insn_in \dec_opcode_in - sync init - end - process $group_5 - assign \dec_rc_sel_in 2'00 - assign \dec_rc_sel_in \dec_rc_sel - sync init - end - process $group_6 - assign \dec_oe_sel_in 2'00 - assign \dec_oe_sel_in \dec_rc_sel - sync init - end - process $group_7 - assign \dec_cr_in_sel_in 3'000 - assign \dec_cr_in_sel_in \dec_cr_in - sync init - end - process $group_8 - assign \dec_cr_out_sel_in 3'000 - assign \dec_cr_out_sel_in \dec_cr_out - sync init - end - process $group_9 - assign \dec_cr_out_rc_in 1'0 - assign \dec_cr_out_rc_in \dec_rc_rc - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:41" - wire width 64 \tmp_tmp_msr - process $group_10 - assign \tmp_tmp_msr 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \tmp_tmp_msr \cur_msr - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:42" - wire width 64 \tmp_tmp_cia - process $group_11 - assign \tmp_tmp_cia 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \tmp_tmp_cia \cur_pc - sync init - end - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:46" - wire width 7 \tmp_tmp_insn_type - process $group_12 - assign \tmp_tmp_insn_type 7'0000000 - assign \tmp_tmp_insn_type \dec_internal_op - sync init - end - attribute \enum_base_type "Function" - attribute \enum_value_00000000000 "NONE" - attribute \enum_value_00000000010 "ALU" - attribute \enum_value_00000000100 "LDST" - attribute \enum_value_00000001000 "SHIFT_ROT" - attribute \enum_value_00000010000 "LOGICAL" - attribute \enum_value_00000100000 "BRANCH" - attribute \enum_value_00001000000 "CR" - attribute \enum_value_00010000000 "TRAP" - attribute \enum_value_00100000000 "MUL" - attribute \enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:47" - wire width 11 \tmp_tmp_fn_unit - process $group_13 - assign \tmp_tmp_fn_unit 11'00000000000 - assign \tmp_tmp_fn_unit \dec_function_unit - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \tmp_tmp_rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \tmp_tmp_rc_ok - process $group_14 - assign \tmp_tmp_rc 1'0 - assign \tmp_tmp_rc_ok 1'0 - assign { \tmp_tmp_rc_ok \tmp_tmp_rc } { \dec_rc_rc_ok \dec_rc_rc } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \tmp_tmp_oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \tmp_tmp_oe_ok - process $group_16 - assign \tmp_tmp_oe 1'0 - assign \tmp_tmp_oe_ok 1'0 - assign { \tmp_tmp_oe_ok \tmp_tmp_oe } { \dec_oe_oe_ok \dec_oe_oe } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 8 \tmp_tmp_cr_rd - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \tmp_tmp_cr_rd_ok - process $group_18 - assign \tmp_tmp_cr_rd 8'00000000 - assign \tmp_tmp_cr_rd_ok 1'0 - assign { \tmp_tmp_cr_rd_ok \tmp_tmp_cr_rd } { \dec_cr_in_cr_fxm_ok \dec_cr_in_cr_fxm } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 8 \tmp_tmp_cr_wr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \tmp_tmp_cr_wr_ok - process $group_20 - assign \tmp_tmp_cr_wr 8'00000000 - assign \tmp_tmp_cr_wr_ok 1'0 - assign { \tmp_tmp_cr_wr_ok \tmp_tmp_cr_wr } { \dec_cr_out_cr_fxm_ok \dec_cr_out_cr_fxm } - sync init - end - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:51" - wire width 2 \tmp_tmp_input_carry - process $group_22 - assign \tmp_tmp_input_carry 2'00 - assign \tmp_tmp_input_carry \dec_cry_in - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:56" - wire width 1 \tmp_tmp_is_32bit - process $group_23 - assign \tmp_tmp_is_32bit 1'0 - assign \tmp_tmp_is_32bit \dec_is_32b - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:48" - wire width 1 \tmp_tmp_lk - process $group_24 - assign \tmp_tmp_lk 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:756" - switch { \dec_lk } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:756" - case 1'1 - assign \tmp_tmp_lk \dec_LK - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:86" - wire width 32 \insn_in$6 - process $group_25 - assign \insn_in$6 32'00000000000000000000000000000000 - assign \insn_in$6 \dec_opcode_in - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:176" - wire width 32 \insn_in$7 - process $group_26 - assign \insn_in$7 32'00000000000000000000000000000000 - assign \insn_in$7 \dec_opcode_in - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:280" - wire width 32 \insn_in$8 - process $group_27 - assign \insn_in$8 32'00000000000000000000000000000000 - assign \insn_in$8 \dec_opcode_in - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:309" - wire width 32 \insn_in$9 - process $group_28 - assign \insn_in$9 32'00000000000000000000000000000000 - assign \insn_in$9 \dec_opcode_in - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:364" - wire width 32 \insn_in$10 - process $group_29 - assign \insn_in$10 32'00000000000000000000000000000000 - assign \insn_in$10 \dec_opcode_in - sync init - end - process $group_30 - assign \dec_a_sel_in 3'000 - assign \dec_a_sel_in \dec_in1_sel - sync init - end - process $group_31 - assign \dec_b_sel_in 4'0000 - assign \dec_b_sel_in \dec_in2_sel - sync init - end - process $group_32 - assign \dec_c_sel_in 2'00 - assign \dec_c_sel_in \dec_in3_sel - sync init - end - process $group_33 - assign \dec_o_sel_in 2'00 - assign \dec_o_sel_in \dec_out_sel - sync init - end - attribute \enum_base_type "OutSel" - attribute \enum_value_00 "NONE" - attribute \enum_value_01 "RT" - attribute \enum_value_10 "RA" - attribute \enum_value_11 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:362" - wire width 2 \sel_in - process $group_34 - assign \sel_in 2'00 - assign \sel_in \dec_out_sel - sync init - end - process $group_35 - assign \dec_o2_lk 1'0 - assign \dec_o2_lk \tmp_tmp_lk - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 5 \tmp_reg1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \tmp_reg1_ok - process $group_36 - assign \tmp_reg1 5'00000 - assign \tmp_reg1_ok 1'0 - assign { \tmp_reg1_ok \tmp_reg1 } { \dec_a_reg_a_ok \dec_a_reg_a } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 5 \tmp_reg2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \tmp_reg2_ok - process $group_38 - assign \tmp_reg2 5'00000 - assign \tmp_reg2_ok 1'0 - assign { \tmp_reg2_ok \tmp_reg2 } { \dec_b_reg_b_ok \dec_b_reg_b } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 5 \tmp_reg3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \tmp_reg3_ok - process $group_40 - assign \tmp_reg3 5'00000 - assign \tmp_reg3_ok 1'0 - assign { \tmp_reg3_ok \tmp_reg3 } { \dec_c_reg_c_ok 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attribute \enum_value_0100110101 "PURR" - attribute \enum_value_0100110110 "HDEC" - attribute \enum_value_0100111001 "HRMOR" - attribute \enum_value_0100111010 "HSRR0" - attribute \enum_value_0100111011 "HSRR1" - attribute \enum_value_0100111110 "LPCR" - attribute \enum_value_0100111111 "LPIDR" - attribute \enum_value_0101010000 "HMER" - attribute \enum_value_0101010001 "HMEER" - attribute \enum_value_0101010010 "PCR" - attribute \enum_value_0101010011 "HEIR" - attribute \enum_value_0101011101 "AMOR" - attribute \enum_value_0110111110 "TIR" - attribute \enum_value_0111010000 "PTCR" - attribute \enum_value_1100000000 "SIER" - attribute \enum_value_1100000001 "MMCR2" - attribute \enum_value_1100000010 "MMCRA" - attribute \enum_value_1100000011 "PMC1" - attribute \enum_value_1100000100 "PMC2" - attribute \enum_value_1100000101 "PMC3" - attribute \enum_value_1100000110 "PMC4" - attribute \enum_value_1100000111 "PMC5" - attribute \enum_value_1100001000 "PMC6" - attribute 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attribute \enum_value_1100100101 "EBBRR" - attribute \enum_value_1100100110 "BESCR" - attribute \enum_value_1100101000 "reserved808" - attribute \enum_value_1100101001 "reserved809" - attribute \enum_value_1100101010 "reserved810" - attribute \enum_value_1100101011 "reserved811" - attribute \enum_value_1100101111 "TAR" - attribute \enum_value_1100110000 "ASDR" - attribute \enum_value_1100110111 "PSSCR" - attribute \enum_value_1101010000 "IC" - attribute \enum_value_1101010001 "VTB" - attribute \enum_value_1101010111 "PSSCR_hypv" - attribute \enum_value_1110000000 "PPR" - attribute \enum_value_1110000010 "PPR32" - attribute \enum_value_1111111111 "PIR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 10 \tmp_spr1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \tmp_spr1_ok - process $group_46 - assign \tmp_spr1 10'0000000000 - assign \tmp_spr1_ok 1'0 - assign { \tmp_spr1_ok \tmp_spr1 } { \dec_a_spr_a_ok \dec_a_spr_a } - sync init - end - attribute \enum_base_type "SPR" - attribute \enum_value_0000000001 "XER" - attribute \enum_value_0000000011 "DSCR" - attribute \enum_value_0000001000 "LR" - attribute \enum_value_0000001001 "CTR" - attribute \enum_value_0000001101 "AMR" - attribute \enum_value_0000010001 "DSCR_priv" - attribute \enum_value_0000010010 "DSISR" - attribute \enum_value_0000010011 "DAR" - attribute \enum_value_0000010110 "DEC" - attribute \enum_value_0000011010 "SRR0" - attribute \enum_value_0000011011 "SRR1" - attribute \enum_value_0000011100 "CFAR" - attribute \enum_value_0000011101 "AMR_priv" - attribute \enum_value_0000110000 "PIDR" - attribute \enum_value_0000111101 "IAMR" - attribute \enum_value_0010000000 "TFHAR" - attribute \enum_value_0010000001 "TFIAR" - attribute \enum_value_0010000010 "TEXASR" - attribute \enum_value_0010000011 "TEXASRU" - attribute \enum_value_0010001000 "CTRL" - attribute \enum_value_0010010000 "TIDR" - attribute \enum_value_0010011000 "CTRL_priv" - attribute \enum_value_0010011001 "FSCR" - attribute \enum_value_0010011101 "UAMOR" - attribute \enum_value_0010011110 "GSR" - attribute \enum_value_0010011111 "PSPB" - attribute \enum_value_0010110000 "DPDES" - attribute \enum_value_0010110100 "DAWR0" - attribute \enum_value_0010111010 "RPR" - attribute \enum_value_0010111011 "CIABR" - attribute \enum_value_0010111100 "DAWRX0" - attribute \enum_value_0010111110 "HFSCR" - attribute \enum_value_0100000000 "VRSAVE" - attribute \enum_value_0100000011 "SPRG3" - attribute \enum_value_0100001100 "TB" - attribute \enum_value_0100001101 "TBU" - attribute \enum_value_0100010000 "SPRG0_priv" - attribute \enum_value_0100010001 "SPRG1_priv" - attribute \enum_value_0100010010 "SPRG2_priv" - attribute \enum_value_0100010011 "SPRG3_priv" - attribute \enum_value_0100011011 "CIR" - attribute \enum_value_0100011100 "TBL" - attribute \enum_value_0100011101 "TBU_hypv" - attribute \enum_value_0100011110 "TBU40" - attribute \enum_value_0100011111 "PVR" - attribute \enum_value_0100110000 "HSPRG0" - attribute \enum_value_0100110001 "HSPRG1" - attribute \enum_value_0100110010 "HDSISR" - attribute \enum_value_0100110011 "HDAR" - attribute \enum_value_0100110100 "SPURR" - attribute \enum_value_0100110101 "PURR" - attribute \enum_value_0100110110 "HDEC" - attribute \enum_value_0100111001 "HRMOR" - attribute \enum_value_0100111010 "HSRR0" - attribute \enum_value_0100111011 "HSRR1" - attribute \enum_value_0100111110 "LPCR" - attribute \enum_value_0100111111 "LPIDR" - attribute \enum_value_0101010000 "HMER" - attribute \enum_value_0101010001 "HMEER" - attribute \enum_value_0101010010 "PCR" - attribute \enum_value_0101010011 "HEIR" - attribute \enum_value_0101011101 "AMOR" - attribute \enum_value_0110111110 "TIR" - attribute \enum_value_0111010000 "PTCR" - attribute \enum_value_1100000000 "SIER" - attribute \enum_value_1100000001 "MMCR2" - attribute \enum_value_1100000010 "MMCRA" - attribute \enum_value_1100000011 "PMC1" - attribute \enum_value_1100000100 "PMC2" - attribute \enum_value_1100000101 "PMC3" - attribute \enum_value_1100000110 "PMC4" - attribute \enum_value_1100000111 "PMC5" - attribute \enum_value_1100001000 "PMC6" - attribute \enum_value_1100001011 "MMCR0" - attribute \enum_value_1100001100 "SIAR" - attribute \enum_value_1100001101 "SDAR" - attribute \enum_value_1100001110 "MMCR1" - attribute \enum_value_1100010000 "SIER_priv" - attribute \enum_value_1100010001 "MMCR2_priv" - attribute \enum_value_1100010010 "MMCRA_priv" - attribute \enum_value_1100010011 "PMC1_priv" - attribute \enum_value_1100010100 "PMC2_priv" - attribute \enum_value_1100010101 "PMC3_priv" - attribute \enum_value_1100010110 "PMC4_priv" - attribute \enum_value_1100010111 "PMC5_priv" - attribute \enum_value_1100011000 "PMC6_priv" - attribute \enum_value_1100011011 "MMCR0_priv" - attribute \enum_value_1100011100 "SIAR_priv" - attribute \enum_value_1100011101 "SDAR_priv" - attribute \enum_value_1100011110 "MMCR1_priv" - attribute \enum_value_1100100000 "BESCRS" - attribute \enum_value_1100100001 "BESCRSU" - attribute \enum_value_1100100010 "BESCRR" - attribute \enum_value_1100100011 "BESCRRU" - attribute \enum_value_1100100100 "EBBHR" - attribute \enum_value_1100100101 "EBBRR" - attribute \enum_value_1100100110 "BESCR" - attribute \enum_value_1100101000 "reserved808" - attribute \enum_value_1100101001 "reserved809" - attribute \enum_value_1100101010 "reserved810" - attribute \enum_value_1100101011 "reserved811" - attribute \enum_value_1100101111 "TAR" - attribute \enum_value_1100110000 "ASDR" - attribute \enum_value_1100110111 "PSSCR" - attribute \enum_value_1101010000 "IC" - attribute \enum_value_1101010001 "VTB" - attribute \enum_value_1101010111 "PSSCR_hypv" - attribute \enum_value_1110000000 "PPR" - attribute \enum_value_1110000010 "PPR32" - attribute \enum_value_1111111111 "PIR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 10 \tmp_spro - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \tmp_spro_ok - process $group_48 - assign \tmp_spro 10'0000000000 - assign \tmp_spro_ok 1'0 - assign { \tmp_spro_ok \tmp_spro } { \dec_o_spr_o_ok \dec_o_spr_o } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 3 \tmp_fast1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \tmp_fast1_ok - process $group_50 - assign \tmp_fast1 3'000 - assign \tmp_fast1_ok 1'0 - assign { \tmp_fast1_ok \tmp_fast1 } { \dec_a_fast_a_ok \dec_a_fast_a } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 3 \tmp_fast2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \tmp_fast2_ok - process $group_52 - assign \tmp_fast2 3'000 - assign \tmp_fast2_ok 1'0 - assign { \tmp_fast2_ok \tmp_fast2 } { \dec_b_fast_b_ok \dec_b_fast_b } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 3 \tmp_fasto1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \tmp_fasto1_ok - process $group_54 - assign \tmp_fasto1 3'000 - assign \tmp_fasto1_ok 1'0 - assign { \tmp_fasto1_ok \tmp_fasto1 } { \dec_o_fast_o_ok \dec_o_fast_o } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 3 \tmp_fasto2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \tmp_fasto2_ok - process $group_56 - assign \tmp_fasto2 3'000 - assign \tmp_fasto2_ok 1'0 - assign { \tmp_fasto2_ok \tmp_fasto2 } { \dec_o2_fast_o_ok \dec_o2_fast_o } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 3 \tmp_cr_in1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \tmp_cr_in1_ok - process $group_58 - assign \tmp_cr_in1 3'000 - assign \tmp_cr_in1_ok 1'0 - assign { \tmp_cr_in1_ok \tmp_cr_in1 } { \dec_cr_in_cr_bitfield_ok \dec_cr_in_cr_bitfield } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 3 \tmp_cr_in2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \tmp_cr_in2_ok - process $group_60 - assign \tmp_cr_in2 3'000 - assign \tmp_cr_in2_ok 1'0 - assign { \tmp_cr_in2_ok \tmp_cr_in2 } { \dec_cr_in_cr_bitfield_b_ok \dec_cr_in_cr_bitfield_b } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 3 \tmp_cr_in2$11 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \tmp_cr_in2_ok$12 - process $group_62 - assign \tmp_cr_in2$11 3'000 - assign \tmp_cr_in2_ok$12 1'0 - assign { \tmp_cr_in2_ok$12 \tmp_cr_in2$11 } { \dec_cr_in_cr_bitfield_o_ok \dec_cr_in_cr_bitfield_o } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 3 \tmp_cr_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \tmp_cr_out_ok - process $group_64 - assign \tmp_cr_out 3'000 - assign \tmp_cr_out_ok 1'0 - assign { \tmp_cr_out_ok \tmp_cr_out } { \dec_cr_out_cr_bitfield_ok \dec_cr_out_cr_bitfield } - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:102" - wire width 3 \tmp_xer_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:856" - wire width 1 $13 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:856" - cell $eq $14 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A \dec_internal_op - connect \B 7'0101110 - connect \Y $13 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:858" - wire width 1 $15 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:858" - cell $eq $16 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A \dec_internal_op - connect \B 7'0001010 - connect \Y $15 - end - process $group_66 - assign \tmp_xer_in 3'000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:856" - switch { $13 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:856" - case 1'1 - assign \tmp_xer_in 3'111 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:858" - switch { $15 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:858" - case 1'1 - assign \tmp_xer_in 3'001 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:103" - wire width 1 \tmp_xer_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:860" - wire width 1 $17 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:860" - cell $eq $18 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A \dec_internal_op - connect \B 7'0110001 - connect \Y $17 - end - process $group_67 - assign \tmp_xer_out 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:860" - switch { $17 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:860" - case 1'1 - assign \tmp_xer_out 1'1 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:53" - wire width 13 \tmp_tmp_trapaddr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:864" - wire width 1 $19 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:864" - cell $eq $20 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A \dec_internal_op - connect \B 7'0111111 - connect \Y $19 - end - process $group_68 - assign \tmp_tmp_trapaddr 13'0000000000000 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:864" - switch { $19 } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:864" - case 1'1 - assign \tmp_tmp_trapaddr 13'0000001110000 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:41" - wire width 1 \is_priv_insn - process $group_69 - assign \is_priv_insn 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:42" - switch \dec_internal_op - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:44" - attribute \nmigen.decoding "OP_ATTN/5|OP_MFMSR/71|OP_MTMSRD/72|OP_MTMSR/74|OP_RFID/70" - case 7'0000101, 7'1000111, 7'1001000, 7'1001010, 7'1000110 - assign \is_priv_insn 1'1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:48" - attribute \nmigen.decoding "OP_MFSPR/46|OP_MTSPR/49" - case 7'0101110, 7'0110001 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:49" - switch { \tmp_tmp_insn [20] } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:49" - case 1'1 - assign \is_priv_insn 1'1 - end - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:881" - wire width 1 \ext_irq_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:886" - wire width 1 $21 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:886" - cell $and $22 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cur_eint - connect \B \cur_msr [15] - connect \Y $21 - end - process $group_70 - assign \ext_irq_ok 1'0 - assign \ext_irq_ok $21 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:882" - wire width 1 \dec_irq_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:887" - wire width 1 $23 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:887" - cell $and $24 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cur_dec [63] - connect \B \cur_msr [15] - connect \Y $23 - end - process $group_71 - assign \dec_irq_ok 1'0 - assign \dec_irq_ok $23 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:883" - wire width 1 \priv_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:888" - wire width 1 $25 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:888" - cell $and $26 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \is_priv_insn - connect \B \cur_msr [14] - connect \Y $25 - end - process $group_72 - assign \priv_ok 1'0 - assign \priv_ok $25 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:884" - wire width 1 \illeg_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:889" - wire width 1 $27 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:889" - cell $eq $28 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A \dec_internal_op - connect \B 7'0000000 - connect \Y $27 - end - process $group_73 - assign \illeg_ok 1'0 - assign \illeg_ok $27 - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:92" - wire width 8 \tmp_asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:52" - wire width 7 \tmp_tmp_traptype - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:920" - wire width 1 $29 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:920" - cell $eq $30 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A \insn_type - connect \B 7'0111111 - connect \Y $29 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:921" - wire width 1 $31 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:921" - cell $eq $32 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A \insn_type - connect \B 7'1001001 - connect \Y $31 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:921" - wire width 1 $33 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:921" - cell $or $34 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $29 - connect \B $31 - connect \Y $33 - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:930" - wire width 1 $35 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:930" - cell $eq $36 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A \insn_type - connect \B 7'1000110 - connect \Y $35 - end - process $group_74 - assign \asmcode 8'00000000 - assign \rego 5'00000 - assign \rego_ok 1'0 - assign \ea 5'00000 - assign \ea_ok 1'0 - assign \reg1 5'00000 - assign \reg1_ok 1'0 - assign \reg2 5'00000 - assign \reg2_ok 1'0 - assign \reg3 5'00000 - assign \reg3_ok 1'0 - assign \spro 10'0000000000 - assign \spro_ok 1'0 - assign \spr1 10'0000000000 - assign \spr1_ok 1'0 - assign \xer_in 3'000 - assign \xer_out 1'0 - assign \fast1 3'000 - assign \fast1_ok 1'0 - assign \fast2 3'000 - assign \fast2_ok 1'0 - assign \fasto1 3'000 - assign \fasto1_ok 1'0 - assign \fasto2 3'000 - assign \fasto2_ok 1'0 - assign \cr_in1 3'000 - assign \cr_in1_ok 1'0 - assign \cr_in2 3'000 - assign \cr_in2_ok 1'0 - assign \cr_in2$1 3'000 - assign \cr_in2_ok$2 1'0 - assign \cr_out 3'000 - assign \cr_out_ok 1'0 - assign \msr 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \cia 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \insn 32'00000000000000000000000000000000 - assign \insn_type 7'0000000 - assign \fn_unit 11'00000000000 - assign \lk 1'0 - assign \rc 1'0 - assign \rc_ok 1'0 - assign \oe 1'0 - assign \oe_ok 1'0 - assign \input_carry 2'00 - assign \traptype 7'0000000 - assign \trapaddr 13'0000000000000 - assign \cr_rd 8'00000000 - assign \cr_rd_ok 1'0 - assign \cr_wr 8'00000000 - assign \cr_wr_ok 1'0 - assign \is_32bit 1'0 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:892" - switch { \illeg_ok \priv_ok \ext_irq_ok \dec_irq_ok } - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:892" - case 4'---1 - assign { \is_32bit \cr_wr_ok \cr_wr \cr_rd_ok \cr_rd \trapaddr \traptype \input_carry \oe_ok \oe \rc_ok \rc \lk \fn_unit \insn_type \insn \cia \msr { \cr_out_ok \cr_out } { \cr_in2_ok$2 \cr_in2$1 } { \cr_in2_ok \cr_in2 } { \cr_in1_ok \cr_in1 } { \fasto2_ok \fasto2 } { \fasto1_ok \fasto1 } { \fast2_ok \fast2 } { \fast1_ok \fast1 } \xer_out \xer_in { \spr1_ok \spr1 } { \spro_ok \spro } { \reg3_ok \reg3 } { \reg2_ok \reg2 } { \reg1_ok \reg1 } { \ea_ok \ea } { \rego_ok \rego } \asmcode } 320'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \insn \dec_opcode_in - assign \insn_type 7'0111111 - assign \fn_unit 11'00010000000 - assign \trapaddr 13'0000010010000 - assign \traptype 7'0100000 - assign \msr \cur_msr - assign \cia \cur_pc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:896" - case 4'--1- - assign { \is_32bit \cr_wr_ok \cr_wr \cr_rd_ok \cr_rd \trapaddr \traptype \input_carry \oe_ok \oe \rc_ok \rc \lk \fn_unit \insn_type \insn \cia \msr { \cr_out_ok \cr_out } { \cr_in2_ok$2 \cr_in2$1 } { \cr_in2_ok \cr_in2 } { \cr_in1_ok \cr_in1 } { \fasto2_ok \fasto2 } { \fasto1_ok \fasto1 } { \fast2_ok \fast2 } { \fast1_ok \fast1 } \xer_out \xer_in { \spr1_ok \spr1 } { \spro_ok \spro } { \reg3_ok \reg3 } { \reg2_ok \reg2 } { \reg1_ok \reg1 } { \ea_ok \ea } { \rego_ok \rego } \asmcode } 320'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \insn \dec_opcode_in - assign \insn_type 7'0111111 - assign \fn_unit 11'00010000000 - assign \trapaddr 13'0000001010000 - assign \traptype 7'0010000 - assign \msr \cur_msr - assign \cia \cur_pc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:900" - case 4'-1-- - assign { \is_32bit \cr_wr_ok \cr_wr \cr_rd_ok \cr_rd \trapaddr \traptype \input_carry \oe_ok \oe \rc_ok \rc \lk \fn_unit \insn_type \insn \cia \msr { \cr_out_ok \cr_out } { \cr_in2_ok$2 \cr_in2$1 } { \cr_in2_ok \cr_in2 } { \cr_in1_ok \cr_in1 } { \fasto2_ok \fasto2 } { \fasto1_ok \fasto1 } { \fast2_ok \fast2 } { \fast1_ok \fast1 } \xer_out \xer_in { \spr1_ok \spr1 } { \spro_ok \spro } { \reg3_ok \reg3 } { \reg2_ok \reg2 } { \reg1_ok \reg1 } { \ea_ok \ea } { \rego_ok \rego } \asmcode } 320'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \insn \dec_opcode_in - assign \insn_type 7'0111111 - assign \fn_unit 11'00010000000 - assign \trapaddr 13'0000001110000 - assign \traptype 7'0000010 - assign \msr \cur_msr - assign \cia \cur_pc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder2.py:907" - case 4'1--- - assign { \is_32bit \cr_wr_ok \cr_wr \cr_rd_ok \cr_rd \trapaddr \traptype \input_carry \oe_ok \oe \rc_ok \rc \lk \fn_unit \insn_type \insn \cia \msr { \cr_out_ok \cr_out } { \cr_in2_ok$2 \cr_in2$1 } { \cr_in2_ok \cr_in2 } { \cr_in1_ok \cr_in1 } { \fasto2_ok \fasto2 } { \fasto1_ok \fasto1 } { \fast2_ok \fast2 } { \fast1_ok \fast1 } \xer_out \xer_in { \spr1_ok \spr1 } { \spro_ok \spro } { \reg3_ok \reg3 } { \reg2_ok \reg2 } { \reg1_ok \reg1 } { \ea_ok \ea } { \rego_ok \rego } \asmcode } 320'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - assign \insn \dec_opcode_in - assign \insn_type 7'0111111 - assign \fn_unit 11'00010000000 - assign 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width 2 \core_core_core_input_carry$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:52" - wire width 7 \core_core_core_traptype - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:52" - wire width 7 \core_core_core_traptype$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:53" - wire width 13 \core_core_core_trapaddr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:53" - wire width 13 \core_core_core_trapaddr$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 8 \core_core_core_cr_rd - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 8 \core_core_core_cr_rd$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \core_core_core_cr_rd_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \core_core_core_cr_rd_ok$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 8 \core_core_core_cr_wr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 8 \core_core_core_cr_wr$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:56" - wire width 1 \core_core_core_is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:56" - wire width 1 \core_core_core_is_32bit$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:87" - wire width 32 \core_raw_insn_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:87" - wire width 32 \core_raw_insn_i$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:88" - wire width 1 \core_bigendian_i$3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:88" - wire width 1 \core_bigendian_i$3$next - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 \core_msr__data_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:8" - wire width 64 \core_core_pc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:8" - wire width 64 \core_core_pc$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:91" - wire width 1 \core_ivalid_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:92" - wire width 1 \core_issue_i - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 4 \core_state_nia_wen - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 5 \core_dmi__addr - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 \core_dmi__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 \core_dmi__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 8 \core_full_rd2__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 32 \core_full_rd2__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 3 \core_full_rd__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 6 \core_full_rd__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 3 \core_issue__addr - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 \core_issue__ren - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 \core_issue__data_o - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 3 \core_issue__addr$4 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 1 \core_issue__wen - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 \core_issue__data_i - cell \core \core - connect \coresync_clk \core_coresync_clk - connect \core_reset_i \core_core_reset_i - connect \corebusy_o \core_corebusy_o - connect \cu_st__rel_o \core_cu_st__rel_o - connect \cu_ad__go_i \core_cu_ad__go_i - connect \cu_ad__rel_o \core_cu_ad__rel_o - connect \cu_st__go_i \core_cu_st__go_i - connect \cia__ren \core_cia__ren - connect \cia__data_o \core_cia__data_o - connect \wen \core_wen - connect \data_i \core_data_i - connect \msr__ren \core_msr__ren - connect \core_terminate_o \core_core_terminate_o - connect \core_rego \core_core_rego - connect \core_ea \core_core_ea - connect \core_reg1 \core_core_reg1 - connect \core_reg1_ok \core_core_reg1_ok - connect \core_reg2 \core_core_reg2 - connect \core_reg2_ok \core_core_reg2_ok - connect \core_reg3 \core_core_reg3 - connect \core_reg3_ok \core_core_reg3_ok - connect \core_spro \core_core_spro - connect \core_spr1 \core_core_spr1 - connect \core_spr1_ok \core_core_spr1_ok - connect \core_xer_in \core_core_xer_in - connect \core_fast1 \core_core_fast1 - connect \core_fast1_ok \core_core_fast1_ok - connect \core_fast2 \core_core_fast2 - connect \core_fast2_ok \core_core_fast2_ok - connect \core_fasto1 \core_core_fasto1 - connect \core_fasto2 \core_core_fasto2 - connect \core_cr_in1 \core_core_cr_in1 - connect \core_cr_in1_ok \core_core_cr_in1_ok - connect \core_cr_in2 \core_core_cr_in2 - connect \core_cr_in2_ok \core_core_cr_in2_ok - connect \core_cr_in2$1 \core_core_cr_in2$1 - connect \core_cr_in2_ok$2 \core_core_cr_in2_ok$2 - connect \core_cr_out \core_core_cr_out - connect \core_core_msr \core_core_core_msr - connect \core_core_cia \core_core_core_cia - connect \core_core_insn \core_core_core_insn - connect \core_core_insn_type \core_core_core_insn_type - connect \core_core_fn_unit \core_core_core_fn_unit - connect \core_core_rc \core_core_core_rc - connect \core_core_rc_ok \core_core_core_rc_ok - connect \core_core_oe \core_core_core_oe - connect \core_core_oe_ok \core_core_core_oe_ok - connect \core_core_input_carry \core_core_core_input_carry - connect \core_core_traptype \core_core_core_traptype - connect \core_core_trapaddr \core_core_core_trapaddr - connect \core_core_cr_rd \core_core_core_cr_rd - connect \core_core_cr_rd_ok \core_core_core_cr_rd_ok - connect \core_core_cr_wr \core_core_core_cr_wr - connect \core_core_is_32bit \core_core_core_is_32bit - connect \raw_insn_i \core_raw_insn_i - connect \bigendian_i \core_bigendian_i$3 - connect \msr__data_o \core_msr__data_o - connect \core_pc \core_core_pc - connect \ivalid_i \core_ivalid_i - connect \issue_i \core_issue_i - connect \state_nia_wen \core_state_nia_wen - connect \dmi__addr \core_dmi__addr - connect \dmi__ren \core_dmi__ren - connect \dmi__data_o \core_dmi__data_o - connect \full_rd2__ren \core_full_rd2__ren - connect \full_rd2__data_o \core_full_rd2__data_o - connect \full_rd__ren \core_full_rd__ren - connect \full_rd__data_o \core_full_rd__data_o - connect \issue__addr \core_issue__addr - connect \issue__ren \core_issue__ren - connect \issue__data_o \core_issue__data_o - connect \issue__addr$3 \core_issue__addr$4 - connect \issue__wen \core_issue__wen - connect \issue__data_i \core_issue__data_i - connect \dbus__cyc \dbus__cyc - connect \dbus__ack \dbus__ack - connect \dbus__err \dbus__err - connect \dbus__stb \dbus__stb - connect \dbus__sel \dbus__sel - connect \dbus__dat_r \dbus__dat_r - connect \dbus__adr \dbus__adr - connect \dbus__we \dbus__we - connect \dbus__dat_w \dbus__dat_w - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:24" - wire width 48 \imem_a_pc_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:26" - wire width 1 \imem_a_valid_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:28" - wire width 1 \imem_f_valid_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:32" - wire width 1 \imem_f_busy_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/minerva/units/fetch.py:33" - wire width 64 \imem_f_instr_o - cell \imem \imem - connect \clk \clk - connect \a_pc_i \imem_a_pc_i - connect \a_valid_i \imem_a_valid_i - connect \f_valid_i \imem_f_valid_i - connect \f_busy_o \imem_f_busy_o - connect \f_instr_o \imem_f_instr_o - connect \rst \rst - connect \ibus__cyc \ibus__cyc - connect \ibus__ack \ibus__ack - connect \ibus__err \ibus__err - connect \ibus__stb \ibus__stb - connect \ibus__sel \ibus__sel - connect \ibus__dat_r \ibus__dat_r - connect \ibus__adr \ibus__adr - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:90" - wire width 1 \dbg_core_rst_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:94" - wire width 1 \dbg_terminate_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:8" - wire width 64 \dbg_core_dbg_pc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:9" - wire width 64 \dbg_core_dbg_msr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:89" - wire width 1 \dbg_core_stop_o - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:95" - wire width 1 \dbg_core_stopped_i - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:68" - wire width 1 \dbg_d_gpr_req - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:70" - wire width 7 \dbg_d_gpr_addr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:71" - wire width 64 \dbg_d_gpr_data - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:69" - wire width 1 \dbg_d_gpr_ack - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:68" - wire width 1 \dbg_d_cr_req - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:71" - wire width 64 \dbg_d_cr_data - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:69" - wire width 1 \dbg_d_cr_ack - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:68" - wire width 1 \dbg_d_xer_req - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:71" - wire width 64 \dbg_d_xer_data - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/debug/dmi.py:69" - wire width 1 \dbg_d_xer_ack - cell \dbg \dbg - connect \clk \clk - connect \core_rst_o \dbg_core_rst_o - connect \terminate_i \dbg_terminate_i - connect \core_dbg_pc \dbg_core_dbg_pc - connect \core_dbg_msr \dbg_core_dbg_msr - connect \core_stop_o \dbg_core_stop_o - connect \core_stopped_i \dbg_core_stopped_i - connect \d_gpr_req \dbg_d_gpr_req - connect \d_gpr_addr \dbg_d_gpr_addr - connect \d_gpr_data \dbg_d_gpr_data - connect \d_gpr_ack \dbg_d_gpr_ack - connect \d_cr_req \dbg_d_cr_req - connect \d_cr_data \dbg_d_cr_data - connect \d_cr_ack \dbg_d_cr_ack - connect \d_xer_req \dbg_d_xer_req - connect \d_xer_data \dbg_d_xer_data - connect \d_xer_ack \dbg_d_xer_ack - connect \rst \rst - connect \dmi_addr_i \dmi_addr_i - connect \dmi_ack_o \dmi_ack_o - connect \dmi_req_i \dmi_req_i - connect \dmi_dout \dmi_dout - connect \dmi_we_i \dmi_we_i - connect \dmi_din \dmi_din - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:385" - wire width 1 \dec2_bigendian - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:8" - wire width 64 \dec2_cur_pc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:8" - wire width 64 \dec2_cur_pc$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:9" - wire width 64 \dec2_cur_msr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:9" - wire width 64 \dec2_cur_msr$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/power_decoder.py:384" - wire width 32 \dec2_raw_opcode_in - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:92" - wire width 8 \dec2_asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 5 \dec2_rego - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \dec2_rego_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 5 \dec2_ea - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \dec2_ea_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 5 \dec2_reg1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \dec2_reg1_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 5 \dec2_reg2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \dec2_reg2_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 5 \dec2_reg3 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \dec2_reg3_ok - attribute \enum_base_type "SPR" - attribute \enum_value_0000000001 "XER" - attribute \enum_value_0000000011 "DSCR" - attribute \enum_value_0000001000 "LR" - attribute \enum_value_0000001001 "CTR" - attribute \enum_value_0000001101 "AMR" - attribute \enum_value_0000010001 "DSCR_priv" - attribute \enum_value_0000010010 "DSISR" - attribute \enum_value_0000010011 "DAR" - attribute \enum_value_0000010110 "DEC" - attribute \enum_value_0000011010 "SRR0" - attribute \enum_value_0000011011 "SRR1" - attribute \enum_value_0000011100 "CFAR" - attribute \enum_value_0000011101 "AMR_priv" - attribute \enum_value_0000110000 "PIDR" - attribute \enum_value_0000111101 "IAMR" - attribute \enum_value_0010000000 "TFHAR" - attribute \enum_value_0010000001 "TFIAR" - attribute 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attribute \enum_value_0100011011 "CIR" - attribute \enum_value_0100011100 "TBL" - attribute \enum_value_0100011101 "TBU_hypv" - attribute \enum_value_0100011110 "TBU40" - attribute \enum_value_0100011111 "PVR" - attribute \enum_value_0100110000 "HSPRG0" - attribute \enum_value_0100110001 "HSPRG1" - attribute \enum_value_0100110010 "HDSISR" - attribute \enum_value_0100110011 "HDAR" - attribute \enum_value_0100110100 "SPURR" - attribute \enum_value_0100110101 "PURR" - attribute \enum_value_0100110110 "HDEC" - attribute \enum_value_0100111001 "HRMOR" - attribute \enum_value_0100111010 "HSRR0" - attribute \enum_value_0100111011 "HSRR1" - attribute \enum_value_0100111110 "LPCR" - attribute \enum_value_0100111111 "LPIDR" - attribute \enum_value_0101010000 "HMER" - attribute \enum_value_0101010001 "HMEER" - attribute \enum_value_0101010010 "PCR" - attribute \enum_value_0101010011 "HEIR" - attribute \enum_value_0101011101 "AMOR" - attribute \enum_value_0110111110 "TIR" - attribute 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- attribute \enum_value_1110000010 "PPR32" - attribute \enum_value_1111111111 "PIR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 10 \dec2_spro - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \dec2_spro_ok - attribute \enum_base_type "SPR" - attribute \enum_value_0000000001 "XER" - attribute \enum_value_0000000011 "DSCR" - attribute \enum_value_0000001000 "LR" - attribute \enum_value_0000001001 "CTR" - attribute \enum_value_0000001101 "AMR" - attribute \enum_value_0000010001 "DSCR_priv" - attribute \enum_value_0000010010 "DSISR" - attribute \enum_value_0000010011 "DAR" - attribute \enum_value_0000010110 "DEC" - attribute \enum_value_0000011010 "SRR0" - attribute \enum_value_0000011011 "SRR1" - attribute \enum_value_0000011100 "CFAR" - attribute \enum_value_0000011101 "AMR_priv" - attribute \enum_value_0000110000 "PIDR" - attribute \enum_value_0000111101 "IAMR" - attribute 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"/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \dec2_fast2_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 3 \dec2_fasto1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \dec2_fasto1_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 3 \dec2_fasto2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \dec2_fasto2_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 3 \dec2_cr_in1 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \dec2_cr_in1_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 3 \dec2_cr_in2 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \dec2_cr_in2_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 3 \dec2_cr_in2$5 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \dec2_cr_in2_ok$6 - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 3 \dec2_cr_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \dec2_cr_out_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:41" - wire width 64 \dec2_msr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:42" - wire width 64 \dec2_cia - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:45" - wire width 32 \dec2_insn - attribute \enum_base_type "MicrOp" - attribute \enum_value_0000000 "OP_ILLEGAL" - attribute \enum_value_0000001 "OP_NOP" - attribute \enum_value_0000010 "OP_ADD" - attribute \enum_value_0000011 "OP_ADDPCIS" - attribute \enum_value_0000100 "OP_AND" - attribute \enum_value_0000101 "OP_ATTN" - attribute \enum_value_0000110 "OP_B" - attribute \enum_value_0000111 "OP_BC" - attribute \enum_value_0001000 "OP_BCREG" - attribute \enum_value_0001001 "OP_BPERM" - attribute \enum_value_0001010 "OP_CMP" - attribute \enum_value_0001011 "OP_CMPB" - attribute \enum_value_0001100 "OP_CMPEQB" - attribute \enum_value_0001101 "OP_CMPRB" - attribute \enum_value_0001110 "OP_CNTZ" - attribute \enum_value_0001111 "OP_CRAND" - attribute \enum_value_0010000 "OP_CRANDC" - attribute \enum_value_0010001 "OP_CREQV" - attribute \enum_value_0010010 "OP_CRNAND" - attribute \enum_value_0010011 "OP_CRNOR" - attribute \enum_value_0010100 "OP_CROR" - attribute \enum_value_0010101 "OP_CRORC" - attribute \enum_value_0010110 "OP_CRXOR" - attribute \enum_value_0010111 "OP_DARN" - attribute \enum_value_0011000 "OP_DCBF" - attribute \enum_value_0011001 "OP_DCBST" - attribute \enum_value_0011010 "OP_DCBT" - attribute \enum_value_0011011 "OP_DCBTST" - attribute \enum_value_0011100 "OP_DCBZ" - attribute \enum_value_0011101 "OP_DIV" - attribute \enum_value_0011110 "OP_DIVE" - attribute \enum_value_0011111 "OP_EXTS" - attribute \enum_value_0100000 "OP_EXTSWSLI" - attribute \enum_value_0100001 "OP_ICBI" - attribute \enum_value_0100010 "OP_ICBT" - attribute \enum_value_0100011 "OP_ISEL" - attribute \enum_value_0100100 "OP_ISYNC" - attribute \enum_value_0100101 "OP_LOAD" - attribute \enum_value_0100110 "OP_STORE" - attribute \enum_value_0100111 "OP_MADDHD" - attribute \enum_value_0101000 "OP_MADDHDU" - attribute \enum_value_0101001 "OP_MADDLD" - attribute \enum_value_0101010 "OP_MCRF" - attribute \enum_value_0101011 "OP_MCRXR" - attribute \enum_value_0101100 "OP_MCRXRX" - attribute \enum_value_0101101 "OP_MFCR" - attribute \enum_value_0101110 "OP_MFSPR" - attribute \enum_value_0101111 "OP_MOD" - attribute \enum_value_0110000 "OP_MTCRF" - attribute \enum_value_0110001 "OP_MTSPR" - attribute \enum_value_0110010 "OP_MUL_L64" - attribute \enum_value_0110011 "OP_MUL_H64" - attribute \enum_value_0110100 "OP_MUL_H32" - attribute \enum_value_0110101 "OP_OR" - attribute \enum_value_0110110 "OP_POPCNT" - attribute \enum_value_0110111 "OP_PRTY" - attribute \enum_value_0111000 "OP_RLC" - attribute \enum_value_0111001 "OP_RLCL" - attribute \enum_value_0111010 "OP_RLCR" - attribute \enum_value_0111011 "OP_SETB" - attribute \enum_value_0111100 "OP_SHL" - attribute \enum_value_0111101 "OP_SHR" - attribute \enum_value_0111110 "OP_SYNC" - attribute \enum_value_0111111 "OP_TRAP" - attribute \enum_value_1000011 "OP_XOR" - attribute \enum_value_1000100 "OP_SIM_CONFIG" - attribute \enum_value_1000101 "OP_CROP" - attribute \enum_value_1000110 "OP_RFID" - attribute \enum_value_1000111 "OP_MFMSR" - attribute \enum_value_1001000 "OP_MTMSRD" - attribute \enum_value_1001001 "OP_SC" - attribute \enum_value_1001010 "OP_MTMSR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:46" - wire width 7 \dec2_insn_type - attribute \enum_base_type "Function" - attribute \enum_value_00000000000 "NONE" - attribute \enum_value_00000000010 "ALU" - attribute \enum_value_00000000100 "LDST" - attribute \enum_value_00000001000 "SHIFT_ROT" - attribute \enum_value_00000010000 "LOGICAL" - attribute \enum_value_00000100000 "BRANCH" - attribute \enum_value_00001000000 "CR" - attribute \enum_value_00010000000 "TRAP" - attribute \enum_value_00100000000 "MUL" - attribute \enum_value_01000000000 "DIV" - attribute \enum_value_10000000000 "SPR" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:47" - wire width 11 \dec2_fn_unit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:48" - wire width 1 \dec2_lk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \dec2_rc - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \dec2_rc_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \dec2_oe - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \dec2_oe_ok - attribute \enum_base_type "CryIn" - attribute \enum_value_00 "ZERO" - attribute \enum_value_01 "ONE" - attribute \enum_value_10 "CA" - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:51" - wire width 2 \dec2_input_carry - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:52" - wire width 7 \dec2_traptype - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:53" - wire width 13 \dec2_trapaddr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 8 \dec2_cr_rd - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \dec2_cr_rd_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 8 \dec2_cr_wr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \dec2_cr_wr_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:56" - wire width 1 \dec2_is_32bit - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:10" - wire width 1 \dec2_cur_eint - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:11" - wire width 64 \dec2_cur_dec - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:11" - wire width 64 \dec2_cur_dec$next - cell \dec2 \dec2 - connect \bigendian \dec2_bigendian - connect \cur_pc \dec2_cur_pc - connect \cur_msr \dec2_cur_msr - connect \raw_opcode_in \dec2_raw_opcode_in - connect \asmcode \dec2_asmcode - connect \rego \dec2_rego - connect \rego_ok \dec2_rego_ok - connect \ea \dec2_ea - connect \ea_ok \dec2_ea_ok - connect \reg1 \dec2_reg1 - connect \reg1_ok \dec2_reg1_ok - connect \reg2 \dec2_reg2 - connect \reg2_ok \dec2_reg2_ok - connect \reg3 \dec2_reg3 - connect \reg3_ok \dec2_reg3_ok - connect \spro \dec2_spro - connect \spro_ok \dec2_spro_ok - connect \spr1 \dec2_spr1 - connect \spr1_ok \dec2_spr1_ok - connect \xer_in \dec2_xer_in - connect \xer_out \dec2_xer_out - connect \fast1 \dec2_fast1 - connect \fast1_ok \dec2_fast1_ok - connect \fast2 \dec2_fast2 - connect \fast2_ok \dec2_fast2_ok - connect \fasto1 \dec2_fasto1 - connect \fasto1_ok \dec2_fasto1_ok - connect \fasto2 \dec2_fasto2 - connect \fasto2_ok \dec2_fasto2_ok - connect \cr_in1 \dec2_cr_in1 - connect \cr_in1_ok \dec2_cr_in1_ok - connect \cr_in2 \dec2_cr_in2 - connect \cr_in2_ok \dec2_cr_in2_ok - connect \cr_in2$1 \dec2_cr_in2$5 - connect \cr_in2_ok$2 \dec2_cr_in2_ok$6 - connect \cr_out \dec2_cr_out - connect \cr_out_ok \dec2_cr_out_ok - connect \msr \dec2_msr - connect \cia \dec2_cia - connect \insn \dec2_insn - connect \insn_type \dec2_insn_type - connect \fn_unit \dec2_fn_unit - connect \lk \dec2_lk - connect \rc \dec2_rc - connect \rc_ok \dec2_rc_ok - connect \oe \dec2_oe - connect \oe_ok \dec2_oe_ok - connect \input_carry \dec2_input_carry - connect \traptype \dec2_traptype - connect \trapaddr \dec2_trapaddr - connect \cr_rd \dec2_cr_rd - connect \cr_rd_ok \dec2_cr_rd_ok - connect \cr_wr \dec2_cr_wr - connect \cr_wr_ok \dec2_cr_wr_ok - connect \is_32bit \dec2_is_32bit - connect \cur_eint \dec2_cur_eint - connect \cur_dec \dec2_cur_dec - end - attribute \src "simple/issuer.py:144" - wire width 2 \delay - attribute \src "simple/issuer.py:144" - wire width 2 \delay$next - attribute \src "simple/issuer.py:145" - wire width 1 $7 - attribute \src "simple/issuer.py:145" - cell $ne $8 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \delay - connect \B 1'0 - connect \Y $7 - end - attribute \src "simple/issuer.py:146" - wire width 3 $9 - attribute \src "simple/issuer.py:146" - wire width 3 $10 - attribute \src "simple/issuer.py:146" - cell $sub $11 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 3 - connect \A \delay - connect \B 1'1 - connect \Y $10 - end - connect $9 $10 - process $group_0 - assign \delay$next \delay - attribute \src "simple/issuer.py:145" - switch { $7 } - attribute \src "simple/issuer.py:145" - case 1'1 - assign \delay$next $9 [1:0] - end - sync init - update \delay 2'11 - sync posedge \por_clk - update \delay \delay$next - end - process $group_1 - assign \por_clk 1'0 - assign \por_clk \clk - sync init - end - process $group_2 - assign \core_coresync_clk 1'0 - assign \core_coresync_clk \clk - sync init - end - attribute \src "simple/issuer.py:150" - wire width 1 $12 - attribute \src "simple/issuer.py:150" - cell $or $13 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A 1'0 - connect \B \dbg_core_rst_o - connect \Y $12 - end - attribute \src "simple/issuer.py:150" - wire width 1 $14 - attribute \src "simple/issuer.py:150" - cell $ne $15 - parameter \A_SIGNED 0 - parameter \A_WIDTH 2 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \delay - connect \B $12 - connect \Y $14 - end - process $group_3 - assign \core_core_reset_i 1'0 - assign \core_core_reset_i $14 - sync init - end - process $group_4 - assign \busy_o 1'0 - assign \busy_o \core_corebusy_o - sync init - end - process $group_5 - assign \dec2_bigendian 1'0 - assign \dec2_bigendian \core_bigendian_i - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire width 1 \cu_st__rel_o_dly - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:53" - wire width 1 \cu_st__rel_o_dly$next - process $group_6 - assign \cu_st__rel_o_dly$next \cu_st__rel_o_dly - assign \cu_st__rel_o_dly$next \core_cu_st__rel_o - sync init - update \cu_st__rel_o_dly 1'0 - sync posedge \clk - update \cu_st__rel_o_dly \cu_st__rel_o_dly$next - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:54" - wire width 1 \cu_st__rel_o_rise - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - wire width 1 $16 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $not $17 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \cu_st__rel_o_dly - connect \Y $16 - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - wire width 1 $18 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/util.py:58" - cell $and $19 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \core_cu_st__rel_o - connect \B $16 - connect \Y $18 - end - process $group_7 - assign \cu_st__rel_o_rise 1'0 - assign \cu_st__rel_o_rise $18 - sync init - end - process $group_8 - assign \core_cu_ad__go_i 1'0 - assign \core_cu_ad__go_i \core_cu_ad__rel_o - sync init - end - process $group_9 - assign \core_cu_st__go_i 1'0 - assign \core_cu_st__go_i \cu_st__rel_o_rise - sync init - end - process $group_10 - assign \pc_o 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \pc_o \dec2_cur_pc - sync init - end - attribute \src "simple/issuer.py:169" - wire width 64 \nia - attribute \src "simple/issuer.py:170" - wire width 65 $20 - attribute \src "simple/issuer.py:170" - wire width 65 $21 - attribute \src "simple/issuer.py:170" - cell $add $22 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \B_SIGNED 0 - parameter \B_WIDTH 3 - parameter \Y_WIDTH 65 - connect \A \dec2_cur_pc - connect \B 3'100 - connect \Y $21 - end - connect $20 $21 - process $group_11 - assign \nia 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \nia $20 [63:0] - sync init - end - attribute \src "simple/issuer.py:174" - wire width 1 \pc_ok_delay - attribute \src "simple/issuer.py:174" - wire width 1 \pc_ok_delay$next - attribute \src "simple/issuer.py:175" - wire width 1 $23 - attribute \src "simple/issuer.py:175" - cell $not $24 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \pc_i_ok - connect \Y $23 - end - process $group_12 - assign \pc_ok_delay$next \pc_ok_delay - assign \pc_ok_delay$next $23 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \rst - case 1'1 - assign \pc_ok_delay$next 1'0 - end - sync init - update \pc_ok_delay 1'0 - sync posedge \clk - update \pc_ok_delay \pc_ok_delay$next - end - attribute \src "simple/issuer.py:173" - wire width 64 \pc - process $group_13 - assign \pc 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "simple/issuer.py:176" - switch { \pc_i_ok } - attribute \src "simple/issuer.py:176" - case 1'1 - assign \pc \pc_i - attribute \src "simple/issuer.py:179" - case - end - attribute \src "simple/issuer.py:183" - switch { \pc_ok_delay } - attribute \src "simple/issuer.py:183" - case 1'1 - assign \pc \core_cia__data_o - end - sync init - end - process $group_14 - assign \core_cia__ren 4'0000 - attribute \src "simple/issuer.py:176" - switch { \pc_i_ok } - attribute \src "simple/issuer.py:176" - case 1'1 - attribute \src "simple/issuer.py:179" - case - assign \core_cia__ren 4'0001 - end - sync init - end - attribute \src "simple/issuer.py:214" - wire width 2 \fsm_state - attribute \src "simple/issuer.py:214" - wire width 2 \fsm_state$next - attribute \src "simple/issuer.py:280" - wire width 1 $25 - attribute \src "simple/issuer.py:280" - cell $not $26 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \core_corebusy_o - connect \Y $25 - end - attribute \src "simple/issuer.py:284" - wire width 1 $27 - attribute \src "simple/issuer.py:164" - wire width 1 \pc_changed - attribute \src "simple/issuer.py:164" - wire width 1 \pc_changed$next - attribute \src "simple/issuer.py:284" - cell $not $28 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \pc_changed - connect \Y $27 - end - process $group_15 - assign \core_wen 4'0000 - assign \core_wen 4'0000 - attribute \src "simple/issuer.py:214" - switch \fsm_state - attribute \src "simple/issuer.py:217" - attribute \nmigen.decoding "IDLE/0" - case 2'00 - attribute \src "simple/issuer.py:242" - attribute \nmigen.decoding "INSN_READ/1" - case 2'01 - attribute \src "simple/issuer.py:268" - attribute \nmigen.decoding "INSN_START/2" - case 2'10 - attribute \src "simple/issuer.py:275" - attribute \nmigen.decoding "INSN_ACTIVE/3" - case 2'11 - attribute \src "simple/issuer.py:280" - switch { $25 } - attribute \src "simple/issuer.py:280" - case 1'1 - attribute \src "simple/issuer.py:284" - switch { $27 } - attribute \src "simple/issuer.py:284" - case 1'1 - assign \core_wen 4'0001 - end - end - end - sync init - end - attribute \src "simple/issuer.py:280" - wire width 1 $29 - attribute \src "simple/issuer.py:280" - cell $not $30 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \core_corebusy_o - connect \Y $29 - end - attribute \src "simple/issuer.py:284" - wire width 1 $31 - attribute \src "simple/issuer.py:284" - cell $not $32 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \pc_changed - connect \Y $31 - end - process $group_16 - assign \core_data_i 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \core_data_i 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "simple/issuer.py:214" - switch \fsm_state - attribute \src "simple/issuer.py:217" - attribute \nmigen.decoding "IDLE/0" - case 2'00 - attribute \src "simple/issuer.py:242" - attribute \nmigen.decoding "INSN_READ/1" - case 2'01 - attribute \src "simple/issuer.py:268" - attribute \nmigen.decoding "INSN_START/2" - case 2'10 - attribute \src "simple/issuer.py:275" - attribute \nmigen.decoding "INSN_ACTIVE/3" - case 2'11 - attribute \src "simple/issuer.py:280" - switch { $29 } - attribute \src "simple/issuer.py:280" - case 1'1 - attribute \src "simple/issuer.py:284" - switch { $31 } - attribute \src "simple/issuer.py:284" - case 1'1 - assign \core_data_i \nia - end - end - end - sync init - end - attribute \src "simple/issuer.py:222" - wire width 1 $33 - attribute \src "simple/issuer.py:222" - cell $not $34 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \dbg_core_stop_o - connect \Y $33 - end - attribute \src "simple/issuer.py:222" - wire width 1 $35 - attribute \src "simple/issuer.py:222" - cell $not $36 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \core_core_reset_i - connect \Y $35 - end - attribute \src "simple/issuer.py:222" - wire width 1 $37 - attribute \src "simple/issuer.py:222" - cell $and $38 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $33 - connect \B $35 - connect \Y $37 - end - process $group_17 - assign \core_msr__ren 4'0000 - assign \core_msr__ren 4'0000 - attribute \src "simple/issuer.py:214" - switch \fsm_state - attribute \src "simple/issuer.py:217" - attribute \nmigen.decoding "IDLE/0" - case 2'00 - attribute \src "simple/issuer.py:222" - switch { $37 } - attribute \src "simple/issuer.py:222" - case 1'1 - assign \core_msr__ren 4'0010 - attribute \src "simple/issuer.py:237" - case - end - attribute \src "simple/issuer.py:242" - attribute \nmigen.decoding "INSN_READ/1" - case 2'01 - attribute \src "simple/issuer.py:268" - attribute \nmigen.decoding "INSN_START/2" - case 2'10 - attribute \src "simple/issuer.py:275" - attribute \nmigen.decoding "INSN_ACTIVE/3" - case 2'11 - end - sync init - end - process $group_18 - assign \dbg_terminate_i 1'0 - assign \dbg_terminate_i \core_core_terminate_o - sync init - end - process $group_19 - assign \dbg_core_dbg_pc 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \dbg_core_dbg_pc \pc - sync init - end - process $group_20 - assign \dbg_core_dbg_msr 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \dbg_core_dbg_msr \dec2_cur_msr - sync init - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" - wire width 1 $39 - attribute \src "simple/issuer.py:278" - wire width 4 $40 - attribute \src "simple/issuer.py:278" - cell $and $41 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 4 - connect \A \core_state_nia_wen - connect \B 1'1 - connect \Y $40 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/dsl.py:438" - cell $reduce_bool $42 - parameter \A_SIGNED 0 - parameter \A_WIDTH 4 - parameter \Y_WIDTH 1 - connect \A $40 - connect \Y $39 - end - process $group_21 - assign \pc_changed$next \pc_changed - attribute \src "simple/issuer.py:214" - switch \fsm_state - attribute \src "simple/issuer.py:217" - attribute \nmigen.decoding "IDLE/0" - case 2'00 - assign \pc_changed$next 1'0 - attribute \src "simple/issuer.py:242" - attribute \nmigen.decoding "INSN_READ/1" - case 2'01 - attribute \src "simple/issuer.py:268" - attribute \nmigen.decoding "INSN_START/2" - case 2'10 - attribute \src "simple/issuer.py:275" - attribute \nmigen.decoding "INSN_ACTIVE/3" - case 2'11 - attribute \src "simple/issuer.py:278" - switch { $39 } - attribute \src "simple/issuer.py:278" - case 1'1 - assign \pc_changed$next 1'1 - end - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \rst - case 1'1 - assign \pc_changed$next 1'0 - end - sync init - update \pc_changed 1'0 - sync posedge \clk - update \pc_changed \pc_changed$next - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:92" - wire width 8 \core_asmcode - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:92" - wire width 8 \core_asmcode$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \core_rego_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \core_rego_ok$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \core_ea_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \core_ea_ok$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \core_spro_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \core_spro_ok$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:103" - wire width 1 \core_xer_out - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:103" - wire width 1 \core_xer_out$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \core_fasto1_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \core_fasto1_ok$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \core_fasto2_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \core_fasto2_ok$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \core_cr_out_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \core_cr_out_ok$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:48" - wire width 1 \core_core_lk - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:48" - wire width 1 \core_core_lk$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \core_core_cr_wr_ok - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/decoder/decode2execute1.py:17" - wire width 1 \core_core_cr_wr_ok$next - attribute \src "simple/issuer.py:280" - wire width 1 $43 - attribute \src "simple/issuer.py:280" - cell $not $44 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \core_corebusy_o - connect \Y $43 - end - process $group_22 - assign \core_asmcode$next \core_asmcode - assign \core_core_rego$next \core_core_rego - assign \core_rego_ok$next \core_rego_ok - assign \core_core_ea$next \core_core_ea - assign \core_ea_ok$next \core_ea_ok - assign \core_core_reg1$next \core_core_reg1 - assign \core_core_reg1_ok$next \core_core_reg1_ok - assign \core_core_reg2$next \core_core_reg2 - assign \core_core_reg2_ok$next \core_core_reg2_ok - assign \core_core_reg3$next \core_core_reg3 - assign \core_core_reg3_ok$next \core_core_reg3_ok - assign \core_core_spro$next \core_core_spro - assign \core_spro_ok$next \core_spro_ok - assign \core_core_spr1$next \core_core_spr1 - assign \core_core_spr1_ok$next \core_core_spr1_ok - assign \core_core_xer_in$next \core_core_xer_in - assign \core_xer_out$next \core_xer_out - assign \core_core_fast1$next \core_core_fast1 - assign \core_core_fast1_ok$next \core_core_fast1_ok - assign \core_core_fast2$next \core_core_fast2 - assign \core_core_fast2_ok$next \core_core_fast2_ok - assign \core_core_fasto1$next \core_core_fasto1 - assign \core_fasto1_ok$next \core_fasto1_ok - assign \core_core_fasto2$next \core_core_fasto2 - assign \core_fasto2_ok$next \core_fasto2_ok - assign \core_core_cr_in1$next \core_core_cr_in1 - assign \core_core_cr_in1_ok$next \core_core_cr_in1_ok - assign \core_core_cr_in2$next \core_core_cr_in2 - assign \core_core_cr_in2_ok$next \core_core_cr_in2_ok - assign \core_core_cr_in2$1$next \core_core_cr_in2$1 - assign \core_core_cr_in2_ok$2$next \core_core_cr_in2_ok$2 - assign \core_core_cr_out$next \core_core_cr_out - assign \core_cr_out_ok$next \core_cr_out_ok - assign \core_core_core_msr$next \core_core_core_msr - assign \core_core_core_cia$next \core_core_core_cia - assign \core_core_core_insn$next \core_core_core_insn - assign \core_core_core_insn_type$next \core_core_core_insn_type - assign \core_core_core_fn_unit$next \core_core_core_fn_unit - assign \core_core_lk$next \core_core_lk - assign \core_core_core_rc$next \core_core_core_rc - assign \core_core_core_rc_ok$next \core_core_core_rc_ok - assign \core_core_core_oe$next \core_core_core_oe - assign \core_core_core_oe_ok$next \core_core_core_oe_ok - assign \core_core_core_input_carry$next \core_core_core_input_carry - assign \core_core_core_traptype$next \core_core_core_traptype - assign \core_core_core_trapaddr$next \core_core_core_trapaddr - assign \core_core_core_cr_rd$next \core_core_core_cr_rd - assign \core_core_core_cr_rd_ok$next \core_core_core_cr_rd_ok - assign \core_core_core_cr_wr$next \core_core_core_cr_wr - assign \core_core_cr_wr_ok$next \core_core_cr_wr_ok - assign \core_core_core_is_32bit$next \core_core_core_is_32bit - attribute \src "simple/issuer.py:214" - switch \fsm_state - attribute \src "simple/issuer.py:217" - attribute \nmigen.decoding "IDLE/0" - case 2'00 - assign { \core_core_core_is_32bit$next \core_core_cr_wr_ok$next \core_core_core_cr_wr$next \core_core_core_cr_rd_ok$next \core_core_core_cr_rd$next \core_core_core_trapaddr$next \core_core_core_traptype$next \core_core_core_input_carry$next \core_core_core_oe_ok$next \core_core_core_oe$next \core_core_core_rc_ok$next \core_core_core_rc$next \core_core_lk$next \core_core_core_fn_unit$next \core_core_core_insn_type$next \core_core_core_insn$next \core_core_core_cia$next \core_core_core_msr$next { \core_cr_out_ok$next \core_core_cr_out$next } { \core_core_cr_in2_ok$2$next \core_core_cr_in2$1$next } { \core_core_cr_in2_ok$next \core_core_cr_in2$next } { \core_core_cr_in1_ok$next \core_core_cr_in1$next } { \core_fasto2_ok$next \core_core_fasto2$next } { \core_fasto1_ok$next \core_core_fasto1$next } { \core_core_fast2_ok$next \core_core_fast2$next } { \core_core_fast1_ok$next \core_core_fast1$next } \core_xer_out$next \core_core_xer_in$next { \core_core_spr1_ok$next \core_core_spr1$next } { \core_spro_ok$next \core_core_spro$next } { \core_core_reg3_ok$next \core_core_reg3$next } { \core_core_reg2_ok$next \core_core_reg2$next } { \core_core_reg1_ok$next \core_core_reg1$next } { \core_ea_ok$next \core_core_ea$next } { \core_rego_ok$next \core_core_rego$next } \core_asmcode$next } 320'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - attribute \src "simple/issuer.py:242" - attribute \nmigen.decoding "INSN_READ/1" - case 2'01 - attribute \src "simple/issuer.py:247" - switch { \imem_f_busy_o } - attribute \src "simple/issuer.py:247" - case 1'1 - attribute \src "simple/issuer.py:251" - case - assign { \core_core_core_is_32bit$next \core_core_cr_wr_ok$next \core_core_core_cr_wr$next \core_core_core_cr_rd_ok$next \core_core_core_cr_rd$next \core_core_core_trapaddr$next \core_core_core_traptype$next \core_core_core_input_carry$next \core_core_core_oe_ok$next \core_core_core_oe$next \core_core_core_rc_ok$next \core_core_core_rc$next \core_core_lk$next \core_core_core_fn_unit$next \core_core_core_insn_type$next \core_core_core_insn$next \core_core_core_cia$next \core_core_core_msr$next { \core_cr_out_ok$next \core_core_cr_out$next } { \core_core_cr_in2_ok$2$next \core_core_cr_in2$1$next } { \core_core_cr_in2_ok$next \core_core_cr_in2$next } { \core_core_cr_in1_ok$next \core_core_cr_in1$next } { \core_fasto2_ok$next \core_core_fasto2$next } { \core_fasto1_ok$next \core_core_fasto1$next } { \core_core_fast2_ok$next \core_core_fast2$next } { \core_core_fast1_ok$next \core_core_fast1$next } \core_xer_out$next \core_core_xer_in$next { \core_core_spr1_ok$next \core_core_spr1$next } { \core_spro_ok$next \core_core_spro$next } { \core_core_reg3_ok$next \core_core_reg3$next } { \core_core_reg2_ok$next \core_core_reg2$next } { \core_core_reg1_ok$next \core_core_reg1$next } { \core_ea_ok$next \core_core_ea$next } { \core_rego_ok$next \core_core_rego$next } \core_asmcode$next } { \dec2_is_32bit \dec2_cr_wr_ok \dec2_cr_wr \dec2_cr_rd_ok \dec2_cr_rd \dec2_trapaddr \dec2_traptype \dec2_input_carry \dec2_oe_ok \dec2_oe \dec2_rc_ok \dec2_rc \dec2_lk \dec2_fn_unit \dec2_insn_type \dec2_insn \dec2_cia \dec2_msr { \dec2_cr_out_ok \dec2_cr_out } { \dec2_cr_in2_ok$6 \dec2_cr_in2$5 } { \dec2_cr_in2_ok \dec2_cr_in2 } { \dec2_cr_in1_ok \dec2_cr_in1 } { \dec2_fasto2_ok \dec2_fasto2 } { \dec2_fasto1_ok \dec2_fasto1 } { \dec2_fast2_ok \dec2_fast2 } { \dec2_fast1_ok \dec2_fast1 } \dec2_xer_out \dec2_xer_in { \dec2_spr1_ok \dec2_spr1 } { \dec2_spro_ok \dec2_spro } { \dec2_reg3_ok \dec2_reg3 } { \dec2_reg2_ok \dec2_reg2 } { \dec2_reg1_ok \dec2_reg1 } { \dec2_ea_ok \dec2_ea } { \dec2_rego_ok \dec2_rego } \dec2_asmcode } - end - attribute \src "simple/issuer.py:268" - attribute \nmigen.decoding "INSN_START/2" - case 2'10 - attribute \src "simple/issuer.py:275" - attribute \nmigen.decoding "INSN_ACTIVE/3" - case 2'11 - attribute \src "simple/issuer.py:280" - switch { $43 } - attribute \src "simple/issuer.py:280" - case 1'1 - assign { \core_core_core_is_32bit$next \core_core_cr_wr_ok$next \core_core_core_cr_wr$next \core_core_core_cr_rd_ok$next \core_core_core_cr_rd$next \core_core_core_trapaddr$next \core_core_core_traptype$next \core_core_core_input_carry$next \core_core_core_oe_ok$next \core_core_core_oe$next \core_core_core_rc_ok$next \core_core_core_rc$next \core_core_lk$next \core_core_core_fn_unit$next \core_core_core_insn_type$next \core_core_core_insn$next \core_core_core_cia$next \core_core_core_msr$next { \core_cr_out_ok$next \core_core_cr_out$next } { \core_core_cr_in2_ok$2$next \core_core_cr_in2$1$next } { \core_core_cr_in2_ok$next \core_core_cr_in2$next } { \core_core_cr_in1_ok$next \core_core_cr_in1$next } { \core_fasto2_ok$next \core_core_fasto2$next } { \core_fasto1_ok$next \core_core_fasto1$next } { \core_core_fast2_ok$next \core_core_fast2$next } { \core_core_fast1_ok$next \core_core_fast1$next } \core_xer_out$next \core_core_xer_in$next { \core_core_spr1_ok$next \core_core_spr1$next } { \core_spro_ok$next \core_core_spro$next } { \core_core_reg3_ok$next \core_core_reg3$next } { \core_core_reg2_ok$next \core_core_reg2$next } { \core_core_reg1_ok$next \core_core_reg1$next } { \core_ea_ok$next \core_core_ea$next } { \core_rego_ok$next \core_core_rego$next } \core_asmcode$next } 320'00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 - end - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \rst - case 1'1 - assign \core_rego_ok$next 1'0 - assign \core_ea_ok$next 1'0 - assign \core_core_reg1_ok$next 1'0 - assign \core_core_reg2_ok$next 1'0 - assign \core_core_reg3_ok$next 1'0 - assign \core_spro_ok$next 1'0 - assign \core_core_spr1_ok$next 1'0 - assign \core_core_fast1_ok$next 1'0 - assign \core_core_fast2_ok$next 1'0 - assign \core_fasto1_ok$next 1'0 - assign \core_fasto2_ok$next 1'0 - assign \core_core_cr_in1_ok$next 1'0 - assign \core_core_cr_in2_ok$next 1'0 - assign \core_core_cr_in2_ok$2$next 1'0 - assign \core_cr_out_ok$next 1'0 - assign \core_core_core_rc_ok$next 1'0 - assign \core_core_core_oe_ok$next 1'0 - assign \core_core_core_cr_rd_ok$next 1'0 - assign \core_core_cr_wr_ok$next 1'0 - end - sync init - update \core_asmcode 8'00000000 - update \core_core_rego 5'00000 - update \core_rego_ok 1'0 - update \core_core_ea 5'00000 - update \core_ea_ok 1'0 - update \core_core_reg1 5'00000 - update \core_core_reg1_ok 1'0 - update \core_core_reg2 5'00000 - update \core_core_reg2_ok 1'0 - update \core_core_reg3 5'00000 - update \core_core_reg3_ok 1'0 - update \core_core_spro 10'0000000000 - update \core_spro_ok 1'0 - update \core_core_spr1 10'0000000000 - update \core_core_spr1_ok 1'0 - update \core_core_xer_in 3'000 - update \core_xer_out 1'0 - update \core_core_fast1 3'000 - update \core_core_fast1_ok 1'0 - update \core_core_fast2 3'000 - update \core_core_fast2_ok 1'0 - update \core_core_fasto1 3'000 - update \core_fasto1_ok 1'0 - update \core_core_fasto2 3'000 - update \core_fasto2_ok 1'0 - update \core_core_cr_in1 3'000 - update \core_core_cr_in1_ok 1'0 - update \core_core_cr_in2 3'000 - update \core_core_cr_in2_ok 1'0 - update \core_core_cr_in2$1 3'000 - update \core_core_cr_in2_ok$2 1'0 - update \core_core_cr_out 3'000 - update \core_cr_out_ok 1'0 - update \core_core_core_msr 64'0000000000000000000000000000000000000000000000000000000000000000 - update \core_core_core_cia 64'0000000000000000000000000000000000000000000000000000000000000000 - update \core_core_core_insn 32'00000000000000000000000000000000 - update \core_core_core_insn_type 7'0000000 - update \core_core_core_fn_unit 11'00000000000 - update \core_core_lk 1'0 - update \core_core_core_rc 1'0 - update \core_core_core_rc_ok 1'0 - update \core_core_core_oe 1'0 - update \core_core_core_oe_ok 1'0 - update \core_core_core_input_carry 2'00 - update \core_core_core_traptype 7'0000000 - update \core_core_core_trapaddr 13'0000000000000 - update \core_core_core_cr_rd 8'00000000 - update \core_core_core_cr_rd_ok 1'0 - update \core_core_core_cr_wr 8'00000000 - update \core_core_cr_wr_ok 1'0 - update \core_core_core_is_32bit 1'0 - sync posedge \clk - update \core_asmcode \core_asmcode$next - update \core_core_rego \core_core_rego$next - update \core_rego_ok \core_rego_ok$next - update \core_core_ea \core_core_ea$next - update \core_ea_ok \core_ea_ok$next - update \core_core_reg1 \core_core_reg1$next - update \core_core_reg1_ok \core_core_reg1_ok$next - update \core_core_reg2 \core_core_reg2$next - update \core_core_reg2_ok \core_core_reg2_ok$next - update \core_core_reg3 \core_core_reg3$next - update \core_core_reg3_ok \core_core_reg3_ok$next - update \core_core_spro \core_core_spro$next - update \core_spro_ok \core_spro_ok$next - update \core_core_spr1 \core_core_spr1$next - update \core_core_spr1_ok \core_core_spr1_ok$next - update \core_core_xer_in \core_core_xer_in$next - update \core_xer_out \core_xer_out$next - update \core_core_fast1 \core_core_fast1$next - update \core_core_fast1_ok \core_core_fast1_ok$next - update \core_core_fast2 \core_core_fast2$next - update \core_core_fast2_ok \core_core_fast2_ok$next - update \core_core_fasto1 \core_core_fasto1$next - update \core_fasto1_ok \core_fasto1_ok$next - update \core_core_fasto2 \core_core_fasto2$next - update \core_fasto2_ok \core_fasto2_ok$next - update \core_core_cr_in1 \core_core_cr_in1$next - update \core_core_cr_in1_ok \core_core_cr_in1_ok$next - update \core_core_cr_in2 \core_core_cr_in2$next - update \core_core_cr_in2_ok \core_core_cr_in2_ok$next - update \core_core_cr_in2$1 \core_core_cr_in2$1$next - update \core_core_cr_in2_ok$2 \core_core_cr_in2_ok$2$next - update \core_core_cr_out \core_core_cr_out$next - update \core_cr_out_ok \core_cr_out_ok$next - update \core_core_core_msr \core_core_core_msr$next - update \core_core_core_cia \core_core_core_cia$next - update \core_core_core_insn \core_core_core_insn$next - update \core_core_core_insn_type \core_core_core_insn_type$next - update \core_core_core_fn_unit \core_core_core_fn_unit$next - update \core_core_lk \core_core_lk$next - update \core_core_core_rc \core_core_core_rc$next - update \core_core_core_rc_ok \core_core_core_rc_ok$next - update \core_core_core_oe \core_core_core_oe$next - update \core_core_core_oe_ok \core_core_core_oe_ok$next - update \core_core_core_input_carry \core_core_core_input_carry$next - update \core_core_core_traptype \core_core_core_traptype$next - update \core_core_core_trapaddr \core_core_core_trapaddr$next - update \core_core_core_cr_rd \core_core_core_cr_rd$next - update \core_core_core_cr_rd_ok \core_core_core_cr_rd_ok$next - update \core_core_core_cr_wr \core_core_core_cr_wr$next - update \core_core_cr_wr_ok \core_core_cr_wr_ok$next - update \core_core_core_is_32bit \core_core_core_is_32bit$next - end - attribute \src "simple/issuer.py:280" - wire width 1 $45 - attribute \src "simple/issuer.py:280" - cell $not $46 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \core_corebusy_o - connect \Y $45 - end - process $group_73 - assign \core_raw_insn_i$next \core_raw_insn_i - attribute \src "simple/issuer.py:214" - switch \fsm_state - attribute \src "simple/issuer.py:217" - attribute \nmigen.decoding "IDLE/0" - case 2'00 - assign \core_raw_insn_i$next 32'00000000000000000000000000000000 - attribute \src "simple/issuer.py:242" - attribute \nmigen.decoding "INSN_READ/1" - case 2'01 - attribute \src "simple/issuer.py:247" - switch { \imem_f_busy_o } - attribute \src "simple/issuer.py:247" - case 1'1 - attribute \src "simple/issuer.py:251" - case - assign \core_raw_insn_i$next \dec2_raw_opcode_in - end - attribute \src "simple/issuer.py:268" - attribute \nmigen.decoding "INSN_START/2" - case 2'10 - attribute \src "simple/issuer.py:275" - attribute \nmigen.decoding "INSN_ACTIVE/3" - case 2'11 - attribute \src "simple/issuer.py:280" - switch { $45 } - attribute \src "simple/issuer.py:280" - case 1'1 - assign \core_raw_insn_i$next 32'00000000000000000000000000000000 - end - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \rst - case 1'1 - assign \core_raw_insn_i$next 32'00000000000000000000000000000000 - end - sync init - update \core_raw_insn_i 32'00000000000000000000000000000000 - sync posedge \clk - update \core_raw_insn_i \core_raw_insn_i$next - end - attribute \src "simple/issuer.py:280" - wire width 1 $47 - attribute \src "simple/issuer.py:280" - cell $not $48 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \core_corebusy_o - connect \Y $47 - end - process $group_74 - assign \core_bigendian_i$3$next \core_bigendian_i$3 - attribute \src "simple/issuer.py:214" - switch \fsm_state - attribute \src "simple/issuer.py:217" - attribute \nmigen.decoding "IDLE/0" - case 2'00 - assign \core_bigendian_i$3$next 1'0 - attribute \src "simple/issuer.py:242" - attribute \nmigen.decoding "INSN_READ/1" - case 2'01 - attribute \src "simple/issuer.py:247" - switch { \imem_f_busy_o } - attribute \src "simple/issuer.py:247" - case 1'1 - attribute \src "simple/issuer.py:251" - case - assign \core_bigendian_i$3$next \core_bigendian_i - end - attribute \src "simple/issuer.py:268" - attribute \nmigen.decoding "INSN_START/2" - case 2'10 - attribute \src "simple/issuer.py:275" - attribute \nmigen.decoding "INSN_ACTIVE/3" - case 2'11 - attribute \src "simple/issuer.py:280" - switch { $47 } - attribute \src "simple/issuer.py:280" - case 1'1 - assign \core_bigendian_i$3$next 1'0 - end - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \rst - case 1'1 - assign \core_bigendian_i$3$next 1'0 - end - sync init - update \core_bigendian_i$3 1'0 - sync posedge \clk - update \core_bigendian_i$3 \core_bigendian_i$3$next - end - attribute \src "simple/issuer.py:222" - wire width 1 $49 - attribute \src "simple/issuer.py:222" - cell $not $50 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \dbg_core_stop_o - connect \Y $49 - end - attribute \src "simple/issuer.py:222" - wire width 1 $51 - attribute \src "simple/issuer.py:222" - cell $not $52 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \core_core_reset_i - connect \Y $51 - end - attribute \src "simple/issuer.py:222" - wire width 1 $53 - attribute \src "simple/issuer.py:222" - cell $and $54 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $49 - connect \B $51 - connect \Y $53 - end - process $group_75 - assign \imem_a_pc_i 48'000000000000000000000000000000000000000000000000 - attribute \src "simple/issuer.py:214" - switch \fsm_state - attribute \src "simple/issuer.py:217" - attribute \nmigen.decoding "IDLE/0" - case 2'00 - attribute \src "simple/issuer.py:222" - switch { $53 } - attribute \src "simple/issuer.py:222" - case 1'1 - assign \imem_a_pc_i \pc [47:0] - attribute \src "simple/issuer.py:237" - case - end - attribute \src "simple/issuer.py:242" - attribute \nmigen.decoding "INSN_READ/1" - case 2'01 - attribute \src "simple/issuer.py:268" - attribute \nmigen.decoding "INSN_START/2" - case 2'10 - attribute \src "simple/issuer.py:275" - attribute \nmigen.decoding "INSN_ACTIVE/3" - case 2'11 - end - sync init - end - attribute \src "simple/issuer.py:222" - wire width 1 $55 - attribute \src "simple/issuer.py:222" - cell $not $56 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \dbg_core_stop_o - connect \Y $55 - end - attribute \src "simple/issuer.py:222" - wire width 1 $57 - attribute \src "simple/issuer.py:222" - cell $not $58 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \core_core_reset_i - connect \Y $57 - end - attribute \src "simple/issuer.py:222" - wire width 1 $59 - attribute \src "simple/issuer.py:222" - cell $and $60 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $55 - connect \B $57 - connect \Y $59 - end - process $group_76 - assign \imem_a_valid_i 1'0 - attribute \src "simple/issuer.py:214" - switch \fsm_state - attribute \src "simple/issuer.py:217" - attribute \nmigen.decoding "IDLE/0" - case 2'00 - attribute \src "simple/issuer.py:222" - switch { $59 } - attribute \src "simple/issuer.py:222" - case 1'1 - assign \imem_a_valid_i 1'1 - attribute \src "simple/issuer.py:237" - case - end - attribute \src "simple/issuer.py:242" - attribute \nmigen.decoding "INSN_READ/1" - case 2'01 - attribute \src "simple/issuer.py:247" - switch { \imem_f_busy_o } - attribute \src "simple/issuer.py:247" - case 1'1 - assign \imem_a_valid_i 1'1 - attribute \src "simple/issuer.py:251" - case - end - attribute \src "simple/issuer.py:268" - attribute \nmigen.decoding "INSN_START/2" - case 2'10 - attribute \src "simple/issuer.py:275" - attribute \nmigen.decoding "INSN_ACTIVE/3" - case 2'11 - end - sync init - end - attribute \src "simple/issuer.py:222" - wire width 1 $61 - attribute \src "simple/issuer.py:222" - cell $not $62 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \dbg_core_stop_o - connect \Y $61 - end - attribute \src "simple/issuer.py:222" - wire width 1 $63 - attribute \src "simple/issuer.py:222" - cell $not $64 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \core_core_reset_i - connect \Y $63 - end - attribute \src "simple/issuer.py:222" - wire width 1 $65 - attribute \src "simple/issuer.py:222" - cell $and $66 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $61 - connect \B $63 - connect \Y $65 - end - process $group_77 - assign \imem_f_valid_i 1'0 - attribute \src "simple/issuer.py:214" - switch \fsm_state - attribute \src "simple/issuer.py:217" - attribute \nmigen.decoding "IDLE/0" - case 2'00 - attribute \src "simple/issuer.py:222" - switch { $65 } - attribute \src "simple/issuer.py:222" - case 1'1 - assign \imem_f_valid_i 1'1 - attribute \src "simple/issuer.py:237" - case - end - attribute \src "simple/issuer.py:242" - attribute \nmigen.decoding "INSN_READ/1" - case 2'01 - attribute \src "simple/issuer.py:247" - switch { \imem_f_busy_o } - attribute \src "simple/issuer.py:247" - case 1'1 - assign \imem_f_valid_i 1'1 - attribute \src "simple/issuer.py:251" - case - end - attribute \src "simple/issuer.py:268" - attribute \nmigen.decoding "INSN_START/2" - case 2'10 - attribute \src "simple/issuer.py:275" - attribute \nmigen.decoding "INSN_ACTIVE/3" - case 2'11 - end - sync init - end - attribute \src "simple/issuer.py:222" - wire width 1 $67 - attribute \src "simple/issuer.py:222" - cell $not $68 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \dbg_core_stop_o - connect \Y $67 - end - attribute \src "simple/issuer.py:222" - wire width 1 $69 - attribute \src "simple/issuer.py:222" - cell $not $70 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \core_core_reset_i - connect \Y $69 - end - attribute \src "simple/issuer.py:222" - wire width 1 $71 - attribute \src "simple/issuer.py:222" - cell $and $72 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $67 - connect \B $69 - connect \Y $71 - end - process $group_78 - assign \dec2_cur_pc$next \dec2_cur_pc - attribute \src "simple/issuer.py:214" - switch \fsm_state - attribute \src "simple/issuer.py:217" - attribute \nmigen.decoding "IDLE/0" - case 2'00 - attribute \src "simple/issuer.py:222" - switch { $71 } - attribute \src "simple/issuer.py:222" - case 1'1 - assign \dec2_cur_pc$next \pc - attribute \src "simple/issuer.py:237" - case - end - attribute \src "simple/issuer.py:242" - attribute \nmigen.decoding "INSN_READ/1" - case 2'01 - attribute \src "simple/issuer.py:268" - attribute \nmigen.decoding "INSN_START/2" - case 2'10 - attribute \src "simple/issuer.py:275" - attribute \nmigen.decoding "INSN_ACTIVE/3" - case 2'11 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \rst - case 1'1 - assign \dec2_cur_pc$next 64'0000000000000000000000000000000000000000000000000000000000000000 - end - sync init - update \dec2_cur_pc 64'0000000000000000000000000000000000000000000000000000000000000000 - sync posedge \clk - update \dec2_cur_pc \dec2_cur_pc$next - end - attribute \src "simple/issuer.py:192" - wire width 1 \msr_read - attribute \src "simple/issuer.py:192" - wire width 1 \msr_read$next - attribute \src "simple/issuer.py:222" - wire width 1 $73 - attribute \src "simple/issuer.py:222" - cell $not $74 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \dbg_core_stop_o - connect \Y $73 - end - attribute \src "simple/issuer.py:222" - wire width 1 $75 - attribute \src "simple/issuer.py:222" - cell $not $76 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \core_core_reset_i - connect \Y $75 - end - attribute \src "simple/issuer.py:222" - wire width 1 $77 - attribute \src "simple/issuer.py:222" - cell $and $78 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $73 - connect \B $75 - connect \Y $77 - end - attribute \src "simple/issuer.py:244" - wire width 1 $79 - attribute \src "simple/issuer.py:244" - cell $not $80 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \msr_read - connect \Y $79 - end - process $group_79 - assign \msr_read$next \msr_read - attribute \src "simple/issuer.py:214" - switch \fsm_state - attribute \src "simple/issuer.py:217" - attribute \nmigen.decoding "IDLE/0" - case 2'00 - attribute \src "simple/issuer.py:222" - switch { $77 } - attribute \src "simple/issuer.py:222" - case 1'1 - assign \msr_read$next 1'0 - attribute \src "simple/issuer.py:237" - case - end - attribute \src "simple/issuer.py:242" - attribute \nmigen.decoding "INSN_READ/1" - case 2'01 - attribute \src "simple/issuer.py:244" - switch { $79 } - attribute \src "simple/issuer.py:244" - case 1'1 - assign \msr_read$next 1'1 - end - attribute \src "simple/issuer.py:268" - attribute \nmigen.decoding "INSN_START/2" - case 2'10 - attribute \src "simple/issuer.py:275" - attribute \nmigen.decoding "INSN_ACTIVE/3" - case 2'11 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \rst - case 1'1 - assign \msr_read$next 1'1 - end - sync init - update \msr_read 1'1 - sync posedge \clk - update \msr_read \msr_read$next - end - attribute \src "simple/issuer.py:222" - wire width 1 $81 - attribute \src "simple/issuer.py:222" - cell $not $82 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \dbg_core_stop_o - connect \Y $81 - end - attribute \src "simple/issuer.py:222" - wire width 1 $83 - attribute \src "simple/issuer.py:222" - cell $not $84 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \core_core_reset_i - connect \Y $83 - end - attribute \src "simple/issuer.py:222" - wire width 1 $85 - attribute \src "simple/issuer.py:222" - cell $and $86 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $81 - connect \B $83 - connect \Y $85 - end - attribute \src "simple/issuer.py:280" - wire width 1 $87 - attribute \src "simple/issuer.py:280" - cell $not $88 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \core_corebusy_o - connect \Y $87 - end - process $group_80 - assign \fsm_state$next \fsm_state - attribute \src "simple/issuer.py:214" - switch \fsm_state - attribute \src "simple/issuer.py:217" - attribute \nmigen.decoding "IDLE/0" - case 2'00 - attribute \src "simple/issuer.py:222" - switch { $85 } - attribute \src "simple/issuer.py:222" - case 1'1 - assign \fsm_state$next 2'01 - attribute \src "simple/issuer.py:237" - case - end - attribute \src "simple/issuer.py:242" - attribute \nmigen.decoding "INSN_READ/1" - case 2'01 - attribute \src "simple/issuer.py:247" - switch { \imem_f_busy_o } - attribute \src "simple/issuer.py:247" - case 1'1 - attribute \src "simple/issuer.py:251" - case - assign \fsm_state$next 2'10 - end - attribute \src "simple/issuer.py:268" - attribute \nmigen.decoding "INSN_START/2" - case 2'10 - assign \fsm_state$next 2'11 - attribute \src "simple/issuer.py:275" - attribute \nmigen.decoding "INSN_ACTIVE/3" - case 2'11 - attribute \src "simple/issuer.py:280" - switch { $87 } - attribute \src "simple/issuer.py:280" - case 1'1 - assign \fsm_state$next 2'00 - end - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \rst - case 1'1 - assign \fsm_state$next 2'00 - end - sync init - update \fsm_state 2'00 - sync posedge \clk - update \fsm_state \fsm_state$next - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/simple/core.py:96" - wire width 1 \core_stopped_i - attribute \src "simple/issuer.py:222" - wire width 1 $89 - attribute \src "simple/issuer.py:222" - cell $not $90 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \dbg_core_stop_o - connect \Y $89 - end - attribute \src "simple/issuer.py:222" - wire width 1 $91 - attribute \src "simple/issuer.py:222" - cell $not $92 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \core_core_reset_i - connect \Y $91 - end - attribute \src "simple/issuer.py:222" - wire width 1 $93 - attribute \src "simple/issuer.py:222" - cell $and $94 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $89 - connect \B $91 - connect \Y $93 - end - process $group_81 - assign \core_stopped_i 1'0 - attribute \src "simple/issuer.py:214" - switch \fsm_state - attribute \src "simple/issuer.py:217" - attribute \nmigen.decoding "IDLE/0" - case 2'00 - attribute \src "simple/issuer.py:222" - switch { $93 } - attribute \src "simple/issuer.py:222" - case 1'1 - attribute \src "simple/issuer.py:237" - case - assign \core_stopped_i 1'1 - end - attribute \src "simple/issuer.py:242" - attribute \nmigen.decoding "INSN_READ/1" - case 2'01 - attribute \src "simple/issuer.py:268" - attribute \nmigen.decoding "INSN_START/2" - case 2'10 - attribute \src "simple/issuer.py:275" - attribute \nmigen.decoding "INSN_ACTIVE/3" - case 2'11 - end - sync init - end - attribute \src "simple/issuer.py:222" - wire width 1 $95 - attribute \src "simple/issuer.py:222" - cell $not $96 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \dbg_core_stop_o - connect \Y $95 - end - attribute \src "simple/issuer.py:222" - wire width 1 $97 - attribute \src "simple/issuer.py:222" - cell $not $98 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \core_core_reset_i - connect \Y $97 - end - attribute \src "simple/issuer.py:222" - wire width 1 $99 - attribute \src "simple/issuer.py:222" - cell $and $100 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A $95 - connect \B $97 - connect \Y $99 - end - process $group_82 - assign \dbg_core_stopped_i 1'0 - attribute \src "simple/issuer.py:214" - switch \fsm_state - attribute \src "simple/issuer.py:217" - attribute \nmigen.decoding "IDLE/0" - case 2'00 - attribute \src "simple/issuer.py:222" - switch { $99 } - attribute \src "simple/issuer.py:222" - case 1'1 - attribute \src "simple/issuer.py:237" - case - assign \dbg_core_stopped_i 1'1 - end - attribute \src "simple/issuer.py:242" - attribute \nmigen.decoding "INSN_READ/1" - case 2'01 - attribute \src "simple/issuer.py:268" - attribute \nmigen.decoding "INSN_START/2" - case 2'10 - attribute \src "simple/issuer.py:275" - attribute \nmigen.decoding "INSN_ACTIVE/3" - case 2'11 - end - sync init - end - attribute \src "simple/issuer.py:244" - wire width 1 $101 - attribute \src "simple/issuer.py:244" - cell $not $102 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \Y_WIDTH 1 - connect \A \msr_read - connect \Y $101 - end - process $group_83 - assign \dec2_cur_msr$next \dec2_cur_msr - attribute \src "simple/issuer.py:214" - switch \fsm_state - attribute \src "simple/issuer.py:217" - attribute \nmigen.decoding "IDLE/0" - case 2'00 - attribute \src "simple/issuer.py:242" - attribute \nmigen.decoding "INSN_READ/1" - case 2'01 - attribute \src "simple/issuer.py:244" - switch { $101 } - attribute \src "simple/issuer.py:244" - case 1'1 - assign \dec2_cur_msr$next \core_msr__data_o - end - attribute \src "simple/issuer.py:268" - attribute \nmigen.decoding "INSN_START/2" - case 2'10 - attribute \src "simple/issuer.py:275" - attribute \nmigen.decoding "INSN_ACTIVE/3" - case 2'11 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \rst - case 1'1 - assign \dec2_cur_msr$next 64'0000000000000000000000000000000000000000000000000000000000000000 - end - sync init - update \dec2_cur_msr 64'0000000000000000000000000000000000000000000000000000000000000000 - sync posedge \clk - update \dec2_cur_msr \dec2_cur_msr$next - end - attribute \src "simple/issuer.py:257" - wire width 32 $103 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/back/rtlil.py:609" - wire width 7 $104 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/back/rtlil.py:609" - cell $mul $105 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 7 - connect \A \dec2_cur_pc [2] - connect \B 6'100000 - connect \Y $104 - end - attribute \src "simple/issuer.py:257" - cell $shift $106 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 32 - connect \A \imem_f_instr_o - connect \B $104 - connect \Y $103 - end - process $group_84 - assign \dec2_raw_opcode_in 32'00000000000000000000000000000000 - attribute \src "simple/issuer.py:214" - switch \fsm_state - attribute \src "simple/issuer.py:217" - attribute \nmigen.decoding "IDLE/0" - case 2'00 - attribute \src "simple/issuer.py:242" - attribute \nmigen.decoding "INSN_READ/1" - case 2'01 - attribute \src "simple/issuer.py:247" - switch { \imem_f_busy_o } - attribute \src "simple/issuer.py:247" - case 1'1 - attribute \src "simple/issuer.py:251" - case - assign \dec2_raw_opcode_in $103 - end - attribute \src "simple/issuer.py:268" - attribute \nmigen.decoding "INSN_START/2" - case 2'10 - attribute \src "simple/issuer.py:275" - attribute \nmigen.decoding "INSN_ACTIVE/3" - case 2'11 - end - sync init - end - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:9" - wire width 64 \core_msr - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:9" - wire width 64 \core_msr$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:10" - wire width 1 \core_eint - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:10" - wire width 1 \core_eint$next - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:11" - wire width 64 \core_dec - attribute \src "/home/lkcl/src/libresoc/soc/src/soc/config/state.py:11" - wire width 64 \core_dec$next - process $group_85 - assign \core_core_pc$next \core_core_pc - assign \core_msr$next \core_msr - assign \core_eint$next \core_eint - assign \core_dec$next \core_dec - attribute \src "simple/issuer.py:214" - switch \fsm_state - attribute \src "simple/issuer.py:217" - attribute \nmigen.decoding "IDLE/0" - case 2'00 - attribute \src "simple/issuer.py:242" - attribute \nmigen.decoding "INSN_READ/1" - case 2'01 - attribute \src "simple/issuer.py:247" - switch { \imem_f_busy_o } - attribute \src "simple/issuer.py:247" - case 1'1 - attribute \src "simple/issuer.py:251" - case - assign { \core_dec$next \core_eint$next \core_msr$next \core_core_pc$next } { \dec2_cur_dec \dec2_cur_eint \dec2_cur_msr \dec2_cur_pc } - end - attribute \src "simple/issuer.py:268" - attribute \nmigen.decoding "INSN_START/2" - case 2'10 - attribute \src "simple/issuer.py:275" - attribute \nmigen.decoding "INSN_ACTIVE/3" - case 2'11 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \rst - case 1'1 - assign \core_core_pc$next 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \core_msr$next 64'0000000000000000000000000000000000000000000000000000000000000000 - assign \core_eint$next 1'0 - assign \core_dec$next 64'0000000000000000000000000000000000000000000000000000000000000000 - end - sync init - update \core_core_pc 64'0000000000000000000000000000000000000000000000000000000000000000 - update \core_msr 64'0000000000000000000000000000000000000000000000000000000000000000 - update \core_eint 1'0 - update \core_dec 64'0000000000000000000000000000000000000000000000000000000000000000 - sync posedge \clk - update \core_core_pc \core_core_pc$next - update \core_msr \core_msr$next - update \core_eint \core_eint$next - update \core_dec \core_dec$next - end - attribute \src "simple/issuer.py:166" - wire width 32 \ilatch - attribute \src "simple/issuer.py:166" - wire width 32 \ilatch$next - attribute \src "simple/issuer.py:257" - wire width 32 $107 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/back/rtlil.py:609" - wire width 7 $108 - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/back/rtlil.py:609" - cell $mul $109 - parameter \A_SIGNED 0 - parameter \A_WIDTH 1 - parameter \B_SIGNED 0 - parameter \B_WIDTH 6 - parameter \Y_WIDTH 7 - connect \A \dec2_cur_pc [2] - connect \B 6'100000 - connect \Y $108 - end - attribute \src "simple/issuer.py:257" - cell $shift $110 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 32 - connect \A \imem_f_instr_o - connect \B $108 - connect \Y $107 - end - process $group_89 - assign \ilatch$next \ilatch - attribute \src "simple/issuer.py:214" - switch \fsm_state - attribute \src "simple/issuer.py:217" - attribute \nmigen.decoding "IDLE/0" - case 2'00 - attribute \src "simple/issuer.py:242" - attribute \nmigen.decoding "INSN_READ/1" - case 2'01 - attribute \src "simple/issuer.py:247" - switch { \imem_f_busy_o } - attribute \src "simple/issuer.py:247" - case 1'1 - attribute \src "simple/issuer.py:251" - case - assign \ilatch$next $107 - end - attribute \src "simple/issuer.py:268" - attribute \nmigen.decoding "INSN_START/2" - case 2'10 - attribute \src "simple/issuer.py:275" - attribute \nmigen.decoding "INSN_ACTIVE/3" - case 2'11 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \rst - case 1'1 - assign \ilatch$next 32'00000000000000000000000000000000 - end - sync init - update \ilatch 32'00000000000000000000000000000000 - sync posedge \clk - update \ilatch \ilatch$next - end - attribute \src "simple/issuer.py:276" - wire width 1 $111 - attribute \src "simple/issuer.py:276" - cell $ne $112 - parameter \A_SIGNED 0 - parameter \A_WIDTH 7 - parameter \B_SIGNED 0 - parameter \B_WIDTH 7 - parameter \Y_WIDTH 1 - connect \A \core_core_core_insn_type - connect \B 7'0000001 - connect \Y $111 - end - process $group_90 - assign \core_ivalid_i 1'0 - attribute \src "simple/issuer.py:214" - switch \fsm_state - attribute \src "simple/issuer.py:217" - attribute \nmigen.decoding "IDLE/0" - case 2'00 - attribute \src "simple/issuer.py:242" - attribute \nmigen.decoding "INSN_READ/1" - case 2'01 - attribute \src "simple/issuer.py:268" - attribute \nmigen.decoding "INSN_START/2" - case 2'10 - assign \core_ivalid_i 1'1 - attribute \src "simple/issuer.py:275" - attribute \nmigen.decoding "INSN_ACTIVE/3" - case 2'11 - attribute \src "simple/issuer.py:276" - switch { $111 } - attribute \src "simple/issuer.py:276" - case 1'1 - assign \core_ivalid_i 1'1 - end - end - sync init - end - process $group_91 - assign \core_issue_i 1'0 - attribute \src "simple/issuer.py:214" - switch \fsm_state - attribute \src "simple/issuer.py:217" - attribute \nmigen.decoding "IDLE/0" - case 2'00 - attribute \src "simple/issuer.py:242" - attribute \nmigen.decoding "INSN_READ/1" - case 2'01 - attribute \src "simple/issuer.py:268" - attribute \nmigen.decoding "INSN_START/2" - case 2'10 - assign \core_issue_i 1'1 - attribute \src "simple/issuer.py:275" - attribute \nmigen.decoding "INSN_ACTIVE/3" - case 2'11 - end - sync init - end - process $group_92 - assign \core_dmi__addr 5'00000 - attribute \src "simple/issuer.py:294" - switch { \dbg_d_gpr_req } - attribute \src "simple/issuer.py:294" - case 1'1 - assign \core_dmi__addr \dbg_d_gpr_addr [4:0] - end - sync init - end - process $group_93 - assign \core_dmi__ren 1'0 - attribute \src "simple/issuer.py:294" - switch { \dbg_d_gpr_req } - attribute \src "simple/issuer.py:294" - case 1'1 - assign \core_dmi__ren 1'1 - end - sync init - end - attribute \src "simple/issuer.py:302" - wire width 1 \d_reg_delay - attribute \src "simple/issuer.py:302" - wire width 1 \d_reg_delay$next - process $group_94 - assign \d_reg_delay$next \d_reg_delay - assign \d_reg_delay$next \dbg_d_gpr_req - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \rst - case 1'1 - assign \d_reg_delay$next 1'0 - end - sync init - update \d_reg_delay 1'0 - sync posedge \clk - update \d_reg_delay \d_reg_delay$next - end - process $group_95 - assign \dbg_d_gpr_data 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "simple/issuer.py:304" - switch { \d_reg_delay } - attribute \src "simple/issuer.py:304" - case 1'1 - assign \dbg_d_gpr_data \core_dmi__data_o - end - sync init - end - process $group_96 - assign \dbg_d_gpr_ack 1'0 - attribute \src "simple/issuer.py:304" - switch { \d_reg_delay } - attribute \src "simple/issuer.py:304" - case 1'1 - assign \dbg_d_gpr_ack 1'1 - end - sync init - end - process $group_97 - assign \core_full_rd2__ren 8'00000000 - attribute \src "simple/issuer.py:310" - switch { \dbg_d_cr_req } - attribute \src "simple/issuer.py:310" - case 1'1 - assign \core_full_rd2__ren 8'11111111 - end - sync init - end - attribute \src "simple/issuer.py:312" - wire width 1 \d_cr_delay - attribute \src "simple/issuer.py:312" - wire width 1 \d_cr_delay$next - process $group_98 - assign \d_cr_delay$next \d_cr_delay - assign \d_cr_delay$next \dbg_d_cr_req - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \rst - case 1'1 - assign \d_cr_delay$next 1'0 - end - sync init - update \d_cr_delay 1'0 - sync posedge \clk - update \d_cr_delay \d_cr_delay$next - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 $113 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - cell $pos $114 - parameter \A_SIGNED 0 - parameter \A_WIDTH 32 - parameter \Y_WIDTH 64 - connect \A \core_full_rd2__data_o - connect \Y $113 - end - process $group_99 - assign \dbg_d_cr_data 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "simple/issuer.py:314" - switch { \d_cr_delay } - attribute \src "simple/issuer.py:314" - case 1'1 - assign \dbg_d_cr_data $113 - end - sync init - end - process $group_100 - assign \dbg_d_cr_ack 1'0 - attribute \src "simple/issuer.py:314" - switch { \d_cr_delay } - attribute \src "simple/issuer.py:314" - case 1'1 - assign \dbg_d_cr_ack 1'1 - end - sync init - end - process $group_101 - assign \core_full_rd__ren 3'000 - attribute \src "simple/issuer.py:320" - switch { \dbg_d_xer_req } - attribute \src "simple/issuer.py:320" - case 1'1 - assign \core_full_rd__ren 3'111 - end - sync init - end - attribute \src "simple/issuer.py:322" - wire width 1 \d_xer_delay - attribute \src "simple/issuer.py:322" - wire width 1 \d_xer_delay$next - process $group_102 - assign \d_xer_delay$next \d_xer_delay - assign \d_xer_delay$next \dbg_d_xer_req - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \rst - case 1'1 - assign \d_xer_delay$next 1'0 - end - sync init - update \d_xer_delay 1'0 - sync posedge \clk - update \d_xer_delay \d_xer_delay$next - end - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - wire width 64 $115 - attribute \src "/home/lkcl/src/libresoc/nmutil/src/nmutil/iocontrol.py:91" - cell $pos $116 - parameter \A_SIGNED 0 - parameter \A_WIDTH 6 - parameter \Y_WIDTH 64 - connect \A \core_full_rd__data_o - connect \Y $115 - end - process $group_103 - assign \dbg_d_xer_data 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "simple/issuer.py:324" - switch { \d_xer_delay } - attribute \src "simple/issuer.py:324" - case 1'1 - assign \dbg_d_xer_data $115 - end - sync init - end - process $group_104 - assign \dbg_d_xer_ack 1'0 - attribute \src "simple/issuer.py:324" - switch { \d_xer_delay } - attribute \src "simple/issuer.py:324" - case 1'1 - assign \dbg_d_xer_ack 1'1 - end - sync init - end - attribute \src "simple/issuer.py:350" - wire width 2 \fsm_state$117 - attribute \src "simple/issuer.py:350" - wire width 2 \fsm_state$117$next - process $group_105 - assign \core_issue__addr 3'000 - attribute \src "simple/issuer.py:350" - switch \fsm_state$117 - attribute \src "simple/issuer.py:353" - attribute \nmigen.decoding "DEC_READ/0" - case 2'00 - assign \core_issue__addr 3'110 - attribute \src "simple/issuer.py:359" - attribute \nmigen.decoding "DEC_WRITE/1" - case 2'01 - attribute \src "simple/issuer.py:370" - attribute \nmigen.decoding "TB_READ/2" - case 2'10 - assign \core_issue__addr 3'111 - attribute \src "simple/issuer.py:376" - attribute \nmigen.decoding "TB_WRITE/3" - case 2'11 - end - sync init - end - process $group_106 - assign \core_issue__ren 1'0 - attribute \src "simple/issuer.py:350" - switch \fsm_state$117 - attribute \src "simple/issuer.py:353" - attribute \nmigen.decoding "DEC_READ/0" - case 2'00 - assign \core_issue__ren 1'1 - attribute \src "simple/issuer.py:359" - attribute \nmigen.decoding "DEC_WRITE/1" - case 2'01 - attribute \src "simple/issuer.py:370" - attribute \nmigen.decoding "TB_READ/2" - case 2'10 - assign \core_issue__ren 1'1 - attribute \src "simple/issuer.py:376" - attribute \nmigen.decoding "TB_WRITE/3" - case 2'11 - end - sync init - end - process $group_107 - assign \fsm_state$117$next \fsm_state$117 - attribute \src "simple/issuer.py:350" - switch \fsm_state$117 - attribute \src "simple/issuer.py:353" - attribute \nmigen.decoding "DEC_READ/0" - case 2'00 - assign \fsm_state$117$next 2'01 - attribute \src "simple/issuer.py:359" - attribute \nmigen.decoding "DEC_WRITE/1" - case 2'01 - assign \fsm_state$117$next 2'10 - attribute \src "simple/issuer.py:370" - attribute \nmigen.decoding "TB_READ/2" - case 2'10 - assign \fsm_state$117$next 2'11 - attribute \src "simple/issuer.py:376" - attribute \nmigen.decoding "TB_WRITE/3" - case 2'11 - assign \fsm_state$117$next 2'00 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \rst - case 1'1 - assign \fsm_state$117$next 2'00 - end - sync init - update \fsm_state$117 2'00 - sync posedge \clk - update \fsm_state$117 \fsm_state$117$next - end - attribute \src "simple/issuer.py:360" - wire width 64 \new_dec - attribute \src "simple/issuer.py:362" - wire width 65 $118 - attribute \src "simple/issuer.py:362" - wire width 65 $119 - attribute \src "simple/issuer.py:362" - cell $sub $120 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 65 - connect \A \core_issue__data_o - connect \B 1'1 - connect \Y $119 - end - connect $118 $119 - process $group_108 - assign \new_dec 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "simple/issuer.py:350" - switch \fsm_state$117 - attribute \src "simple/issuer.py:353" - attribute \nmigen.decoding "DEC_READ/0" - case 2'00 - attribute \src "simple/issuer.py:359" - attribute \nmigen.decoding "DEC_WRITE/1" - case 2'01 - assign \new_dec $118 [63:0] - attribute \src "simple/issuer.py:370" - attribute \nmigen.decoding "TB_READ/2" - case 2'10 - attribute \src "simple/issuer.py:376" - attribute \nmigen.decoding "TB_WRITE/3" - case 2'11 - end - sync init - end - process $group_109 - assign \core_issue__addr$4 3'000 - attribute \src "simple/issuer.py:350" - switch \fsm_state$117 - attribute \src "simple/issuer.py:353" - attribute \nmigen.decoding "DEC_READ/0" - case 2'00 - attribute \src "simple/issuer.py:359" - attribute \nmigen.decoding "DEC_WRITE/1" - case 2'01 - assign \core_issue__addr$4 3'110 - attribute \src "simple/issuer.py:370" - attribute \nmigen.decoding "TB_READ/2" - case 2'10 - attribute \src "simple/issuer.py:376" - attribute \nmigen.decoding "TB_WRITE/3" - case 2'11 - assign \core_issue__addr$4 3'111 - end - sync init - end - process $group_110 - assign \core_issue__wen 1'0 - attribute \src "simple/issuer.py:350" - switch \fsm_state$117 - attribute \src "simple/issuer.py:353" - attribute \nmigen.decoding "DEC_READ/0" - case 2'00 - attribute \src "simple/issuer.py:359" - attribute \nmigen.decoding "DEC_WRITE/1" - case 2'01 - assign \core_issue__wen 1'1 - attribute \src "simple/issuer.py:370" - attribute \nmigen.decoding "TB_READ/2" - case 2'10 - attribute \src "simple/issuer.py:376" - attribute \nmigen.decoding "TB_WRITE/3" - case 2'11 - assign \core_issue__wen 1'1 - end - sync init - end - attribute \src "simple/issuer.py:377" - wire width 64 \new_tb - process $group_111 - assign \core_issue__data_i 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "simple/issuer.py:350" - switch \fsm_state$117 - attribute \src "simple/issuer.py:353" - attribute \nmigen.decoding "DEC_READ/0" - case 2'00 - attribute \src "simple/issuer.py:359" - attribute \nmigen.decoding "DEC_WRITE/1" - case 2'01 - assign \core_issue__data_i \new_dec - attribute \src "simple/issuer.py:370" - attribute \nmigen.decoding "TB_READ/2" - case 2'10 - attribute \src "simple/issuer.py:376" - attribute \nmigen.decoding "TB_WRITE/3" - case 2'11 - assign \core_issue__data_i \new_tb - end - sync init - end - process $group_112 - assign \dec2_cur_dec$next \dec2_cur_dec - attribute \src "simple/issuer.py:350" - switch \fsm_state$117 - attribute \src "simple/issuer.py:353" - attribute \nmigen.decoding "DEC_READ/0" - case 2'00 - attribute \src "simple/issuer.py:359" - attribute \nmigen.decoding "DEC_WRITE/1" - case 2'01 - assign \dec2_cur_dec$next \new_dec - attribute \src "simple/issuer.py:370" - attribute \nmigen.decoding "TB_READ/2" - case 2'10 - attribute \src "simple/issuer.py:376" - attribute \nmigen.decoding "TB_WRITE/3" - case 2'11 - end - attribute \src "/home/lkcl/src/libresoc/nmigen/nmigen/hdl/xfrm.py:519" - switch \rst - case 1'1 - assign \dec2_cur_dec$next 64'0000000000000000000000000000000000000000000000000000000000000000 - end - sync init - update \dec2_cur_dec 64'0000000000000000000000000000000000000000000000000000000000000000 - sync posedge \clk - update \dec2_cur_dec \dec2_cur_dec$next - end - attribute \src "simple/issuer.py:378" - wire width 65 $121 - attribute \src "simple/issuer.py:378" - wire width 65 $122 - attribute \src "simple/issuer.py:378" - cell $add $123 - parameter \A_SIGNED 0 - parameter \A_WIDTH 64 - parameter \B_SIGNED 0 - parameter \B_WIDTH 1 - parameter \Y_WIDTH 65 - connect \A \core_issue__data_o - connect \B 1'1 - connect \Y $122 - end - connect $121 $122 - process $group_113 - assign \new_tb 64'0000000000000000000000000000000000000000000000000000000000000000 - attribute \src "simple/issuer.py:350" - switch \fsm_state$117 - attribute \src "simple/issuer.py:353" - attribute \nmigen.decoding "DEC_READ/0" - case 2'00 - attribute \src "simple/issuer.py:359" - attribute \nmigen.decoding "DEC_WRITE/1" - case 2'01 - attribute \src "simple/issuer.py:370" - attribute \nmigen.decoding "TB_READ/2" - case 2'10 - attribute \src "simple/issuer.py:376" - attribute \nmigen.decoding "TB_WRITE/3" - case 2'11 - assign \new_tb $121 [63:0] - end - sync init - end - connect \dec2_cur_eint 1'0 -end -- 2.30.2